From af3dc0e63efa6ed6f7feae926065a68542090f80 Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Sat, 7 Jun 2014 16:46:00 +0800
Subject: [PATCH 01/86] tools/building.py: more descriptive on error

Print the command that failed to execute and try to tell the reason to
fall.
---
 tools/building.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tools/building.py b/tools/building.py
index 726056533f..3572daabbe 100644
--- a/tools/building.py
+++ b/tools/building.py
@@ -43,8 +43,9 @@ class Win32Spawn:
             proc = subprocess.Popen(cmdline, env=_e,
                     startupinfo=startupinfo, shell=False)
         except Exception as e:
-            print 'Error in Popen: %s' % e
-            return -1
+            print 'Error in calling:\n%s' % cmdline
+            print 'Exception: %s: %s' % (e, os.strerror(e.errno))
+            return e.errno
         finally:
             os.environ['PATH'] = old_path
 

From f296c582a54480395ea6a420673b6689d282e17f Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Sat, 14 Jun 2014 21:49:46 +0800
Subject: [PATCH 02/86] fixed bug: close socket when ping() exit.

---
 components/net/lwip-1.3.2/apps/ping.c | 2 ++
 components/net/lwip/apps/ping.c       | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/components/net/lwip-1.3.2/apps/ping.c b/components/net/lwip-1.3.2/apps/ping.c
index d3c3dd399b..1360c932fa 100644
--- a/components/net/lwip-1.3.2/apps/ping.c
+++ b/components/net/lwip-1.3.2/apps/ping.c
@@ -166,6 +166,8 @@ rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 
 		rt_thread_delay(PING_DELAY); /* take a delay */
 	}
+	
+	lwip_close(s);
 
 	return RT_EOK;
 }
diff --git a/components/net/lwip/apps/ping.c b/components/net/lwip/apps/ping.c
index d3c3dd399b..1360c932fa 100644
--- a/components/net/lwip/apps/ping.c
+++ b/components/net/lwip/apps/ping.c
@@ -166,6 +166,8 @@ rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 
 		rt_thread_delay(PING_DELAY); /* take a delay */
 	}
+	
+	lwip_close(s);
 
 	return RT_EOK;
 }

From 9ab59cf1e055dc9e8b9217ea0923ad4e1b1c62d9 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Sat, 14 Jun 2014 21:54:15 +0800
Subject: [PATCH 03/86] used parameter: size.

---
 components/net/lwip-1.3.2/apps/ping.c | 9 ++++++---
 components/net/lwip/apps/ping.c       | 9 ++++++---
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/components/net/lwip-1.3.2/apps/ping.c b/components/net/lwip-1.3.2/apps/ping.c
index 1360c932fa..45021e7112 100644
--- a/components/net/lwip-1.3.2/apps/ping.c
+++ b/components/net/lwip-1.3.2/apps/ping.c
@@ -64,12 +64,12 @@ static void ping_prepare_echo( struct icmp_echo_hdr *iecho, u16_t len)
 }
 
 /* Ping using the socket ip */
-static err_t ping_send(int s, struct ip_addr *addr)
+static err_t ping_send(int s, struct ip_addr *addr, int size)
 {
 	int err;
 	struct icmp_echo_hdr *iecho;
 	struct sockaddr_in to;
-	size_t ping_size = sizeof(struct icmp_echo_hdr) + PING_DATA_SIZE;
+	size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
 	LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
 
 	iecho = rt_malloc(ping_size);
@@ -137,6 +137,9 @@ rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 	} *addr;
 
     send_time = 0;
+	
+	if(size == 0)
+		size = PING_DATA_SIZE;
 
 	if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
 	addr = (struct _ip_addr*)&ping_target;
@@ -151,7 +154,7 @@ rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 
 	while (1)
 	{
-		if (ping_send(s, &ping_target) == ERR_OK)
+		if (ping_send(s, &ping_target, size) == ERR_OK)
 		{
 			rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
 			ping_recv(s);
diff --git a/components/net/lwip/apps/ping.c b/components/net/lwip/apps/ping.c
index 1360c932fa..45021e7112 100644
--- a/components/net/lwip/apps/ping.c
+++ b/components/net/lwip/apps/ping.c
@@ -64,12 +64,12 @@ static void ping_prepare_echo( struct icmp_echo_hdr *iecho, u16_t len)
 }
 
 /* Ping using the socket ip */
-static err_t ping_send(int s, struct ip_addr *addr)
+static err_t ping_send(int s, struct ip_addr *addr, int size)
 {
 	int err;
 	struct icmp_echo_hdr *iecho;
 	struct sockaddr_in to;
-	size_t ping_size = sizeof(struct icmp_echo_hdr) + PING_DATA_SIZE;
+	size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
 	LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
 
 	iecho = rt_malloc(ping_size);
@@ -137,6 +137,9 @@ rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 	} *addr;
 
     send_time = 0;
+	
+	if(size == 0)
+		size = PING_DATA_SIZE;
 
 	if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
 	addr = (struct _ip_addr*)&ping_target;
@@ -151,7 +154,7 @@ rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 
 	while (1)
 	{
-		if (ping_send(s, &ping_target) == ERR_OK)
+		if (ping_send(s, &ping_target, size) == ERR_OK)
 		{
 			rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
 			ping_recv(s);

From 7a0e9c3fc73d72154b9610d29c9c2c7cabc16100 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Sat, 14 Jun 2014 21:55:51 +0800
Subject: [PATCH 04/86] format code Astyle.

---
 components/net/lwip-1.3.2/apps/ping.c | 192 +++++++++++++-------------
 components/net/lwip/apps/ping.c       | 192 +++++++++++++-------------
 2 files changed, 192 insertions(+), 192 deletions(-)

diff --git a/components/net/lwip-1.3.2/apps/ping.c b/components/net/lwip-1.3.2/apps/ping.c
index 45021e7112..1e595dce61 100644
--- a/components/net/lwip-1.3.2/apps/ping.c
+++ b/components/net/lwip-1.3.2/apps/ping.c
@@ -39,140 +39,140 @@
 static u16_t ping_seq_num;
 struct _ip_addr
 {
-	rt_uint8_t addr0, addr1, addr2, addr3;
+    rt_uint8_t addr0, addr1, addr2, addr3;
 };
 
 /** Prepare a echo ICMP request */
 static void ping_prepare_echo( struct icmp_echo_hdr *iecho, u16_t len)
 {
-	size_t i;
-	size_t data_len = len - sizeof(struct icmp_echo_hdr);
+    size_t i;
+    size_t data_len = len - sizeof(struct icmp_echo_hdr);
 
-	ICMPH_TYPE_SET(iecho, ICMP_ECHO);
-	ICMPH_CODE_SET(iecho, 0);
-	iecho->chksum = 0;
-	iecho->id     = PING_ID;
-	iecho->seqno  = htons(++ping_seq_num);
+    ICMPH_TYPE_SET(iecho, ICMP_ECHO);
+    ICMPH_CODE_SET(iecho, 0);
+    iecho->chksum = 0;
+    iecho->id     = PING_ID;
+    iecho->seqno  = htons(++ping_seq_num);
 
-	/* fill the additional data buffer with some data */
-	for(i = 0; i < data_len; i++)
-	{
-		((char*)iecho)[sizeof(struct icmp_echo_hdr) + i] = (char)i;
-	}
+    /* fill the additional data buffer with some data */
+    for(i = 0; i < data_len; i++)
+    {
+        ((char*)iecho)[sizeof(struct icmp_echo_hdr) + i] = (char)i;
+    }
 
-	iecho->chksum = inet_chksum(iecho, len);
+    iecho->chksum = inet_chksum(iecho, len);
 }
 
 /* Ping using the socket ip */
 static err_t ping_send(int s, struct ip_addr *addr, int size)
 {
-	int err;
-	struct icmp_echo_hdr *iecho;
-	struct sockaddr_in to;
-	size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
-	LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
+    int err;
+    struct icmp_echo_hdr *iecho;
+    struct sockaddr_in to;
+    size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
+    LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
 
-	iecho = rt_malloc(ping_size);
-	if (iecho == RT_NULL)
-	{
-		return ERR_MEM;
-	}
+    iecho = rt_malloc(ping_size);
+    if (iecho == RT_NULL)
+    {
+        return ERR_MEM;
+    }
 
-	ping_prepare_echo(iecho, (u16_t)ping_size);
+    ping_prepare_echo(iecho, (u16_t)ping_size);
 
-	to.sin_len = sizeof(to);
-	to.sin_family = AF_INET;
-	to.sin_addr.s_addr = addr->addr;
+    to.sin_len = sizeof(to);
+    to.sin_family = AF_INET;
+    to.sin_addr.s_addr = addr->addr;
 
-	err = lwip_sendto(s, iecho, ping_size, 0, (struct sockaddr*)&to, sizeof(to));
-	rt_free(iecho);
+    err = lwip_sendto(s, iecho, ping_size, 0, (struct sockaddr*)&to, sizeof(to));
+    rt_free(iecho);
 
-	return (err ? ERR_OK : ERR_VAL);
+    return (err ? ERR_OK : ERR_VAL);
 }
 
 static void ping_recv(int s)
 {
-	char buf[64];
-	int fromlen, len;
-	struct sockaddr_in from;
-	struct ip_hdr *iphdr;
-	struct icmp_echo_hdr *iecho;
-	struct _ip_addr *addr;
+    char buf[64];
+    int fromlen, len;
+    struct sockaddr_in from;
+    struct ip_hdr *iphdr;
+    struct icmp_echo_hdr *iecho;
+    struct _ip_addr *addr;
 
-	while((len = lwip_recvfrom(s, buf, sizeof(buf), 0, (struct sockaddr*)&from, (socklen_t*)&fromlen)) > 0)
-	{
-		if (len >= (sizeof(struct ip_hdr)+sizeof(struct icmp_echo_hdr)))
-		{
-			addr = (struct _ip_addr *)&(from.sin_addr);
-			rt_kprintf("ping: recv %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+    while((len = lwip_recvfrom(s, buf, sizeof(buf), 0, (struct sockaddr*)&from, (socklen_t*)&fromlen)) > 0)
+    {
+        if (len >= (sizeof(struct ip_hdr)+sizeof(struct icmp_echo_hdr)))
+        {
+            addr = (struct _ip_addr *)&(from.sin_addr);
+            rt_kprintf("ping: recv %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
 
-			iphdr = (struct ip_hdr *)buf;
-			iecho = (struct icmp_echo_hdr *)(buf+(IPH_HL(iphdr) * 4));
-			if ((iecho->id == PING_ID) && (iecho->seqno == htons(ping_seq_num)))
-			{
-				return;
-			}
-			else
-			{
-				rt_kprintf("ping: drop\n");
-			}
-		}
-	}
+            iphdr = (struct ip_hdr *)buf;
+            iecho = (struct icmp_echo_hdr *)(buf+(IPH_HL(iphdr) * 4));
+            if ((iecho->id == PING_ID) && (iecho->seqno == htons(ping_seq_num)))
+            {
+                return;
+            }
+            else
+            {
+                rt_kprintf("ping: drop\n");
+            }
+        }
+    }
 
-	if (len <= 0)
-	{
-		rt_kprintf("ping: timeout\n");
-	}
+    if (len <= 0)
+    {
+        rt_kprintf("ping: timeout\n");
+    }
 }
 
 rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 {
-	int s;
-	int timeout = PING_RCV_TIMEO;
-	struct ip_addr ping_target;
-	rt_uint32_t send_time;
-	struct _ip_addr
-	{
-		rt_uint8_t addr0, addr1, addr2, addr3;
-	} *addr;
+    int s;
+    int timeout = PING_RCV_TIMEO;
+    struct ip_addr ping_target;
+    rt_uint32_t send_time;
+    struct _ip_addr
+    {
+        rt_uint8_t addr0, addr1, addr2, addr3;
+    } *addr;
 
     send_time = 0;
-	
-	if(size == 0)
-		size = PING_DATA_SIZE;
 
-	if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
-	addr = (struct _ip_addr*)&ping_target;
+    if(size == 0)
+        size = PING_DATA_SIZE;
 
-	if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
-	{
-	    rt_kprintf("create socket failled\n");
-		return -RT_ERROR;
-	}
+    if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
+    addr = (struct _ip_addr*)&ping_target;
 
-	lwip_setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
+    if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
+    {
+        rt_kprintf("create socket failled\n");
+        return -RT_ERROR;
+    }
 
-	while (1)
-	{
-		if (ping_send(s, &ping_target, size) == ERR_OK)
-		{
-			rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
-			ping_recv(s);
-		}
-		else
-		{
-			rt_kprintf("ping: send %d.%d.%d.%d - error\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
-		}
+    lwip_setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
 
-		send_time ++;
-		if (send_time >= time) break; /* send ping times reached, stop */
+    while (1)
+    {
+        if (ping_send(s, &ping_target, size) == ERR_OK)
+        {
+            rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+            ping_recv(s);
+        }
+        else
+        {
+            rt_kprintf("ping: send %d.%d.%d.%d - error\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+        }
 
-		rt_thread_delay(PING_DELAY); /* take a delay */
-	}
-	
-	lwip_close(s);
+        send_time ++;
+        if (send_time >= time) break; /* send ping times reached, stop */
 
-	return RT_EOK;
+        rt_thread_delay(PING_DELAY); /* take a delay */
+    }
+
+    lwip_close(s);
+
+    return RT_EOK;
 }
 #ifdef RT_USING_FINSH
 #include <finsh.h>
diff --git a/components/net/lwip/apps/ping.c b/components/net/lwip/apps/ping.c
index 45021e7112..1e595dce61 100644
--- a/components/net/lwip/apps/ping.c
+++ b/components/net/lwip/apps/ping.c
@@ -39,140 +39,140 @@
 static u16_t ping_seq_num;
 struct _ip_addr
 {
-	rt_uint8_t addr0, addr1, addr2, addr3;
+    rt_uint8_t addr0, addr1, addr2, addr3;
 };
 
 /** Prepare a echo ICMP request */
 static void ping_prepare_echo( struct icmp_echo_hdr *iecho, u16_t len)
 {
-	size_t i;
-	size_t data_len = len - sizeof(struct icmp_echo_hdr);
+    size_t i;
+    size_t data_len = len - sizeof(struct icmp_echo_hdr);
 
-	ICMPH_TYPE_SET(iecho, ICMP_ECHO);
-	ICMPH_CODE_SET(iecho, 0);
-	iecho->chksum = 0;
-	iecho->id     = PING_ID;
-	iecho->seqno  = htons(++ping_seq_num);
+    ICMPH_TYPE_SET(iecho, ICMP_ECHO);
+    ICMPH_CODE_SET(iecho, 0);
+    iecho->chksum = 0;
+    iecho->id     = PING_ID;
+    iecho->seqno  = htons(++ping_seq_num);
 
-	/* fill the additional data buffer with some data */
-	for(i = 0; i < data_len; i++)
-	{
-		((char*)iecho)[sizeof(struct icmp_echo_hdr) + i] = (char)i;
-	}
+    /* fill the additional data buffer with some data */
+    for(i = 0; i < data_len; i++)
+    {
+        ((char*)iecho)[sizeof(struct icmp_echo_hdr) + i] = (char)i;
+    }
 
-	iecho->chksum = inet_chksum(iecho, len);
+    iecho->chksum = inet_chksum(iecho, len);
 }
 
 /* Ping using the socket ip */
 static err_t ping_send(int s, struct ip_addr *addr, int size)
 {
-	int err;
-	struct icmp_echo_hdr *iecho;
-	struct sockaddr_in to;
-	size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
-	LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
+    int err;
+    struct icmp_echo_hdr *iecho;
+    struct sockaddr_in to;
+    size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
+    LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
 
-	iecho = rt_malloc(ping_size);
-	if (iecho == RT_NULL)
-	{
-		return ERR_MEM;
-	}
+    iecho = rt_malloc(ping_size);
+    if (iecho == RT_NULL)
+    {
+        return ERR_MEM;
+    }
 
-	ping_prepare_echo(iecho, (u16_t)ping_size);
+    ping_prepare_echo(iecho, (u16_t)ping_size);
 
-	to.sin_len = sizeof(to);
-	to.sin_family = AF_INET;
-	to.sin_addr.s_addr = addr->addr;
+    to.sin_len = sizeof(to);
+    to.sin_family = AF_INET;
+    to.sin_addr.s_addr = addr->addr;
 
-	err = lwip_sendto(s, iecho, ping_size, 0, (struct sockaddr*)&to, sizeof(to));
-	rt_free(iecho);
+    err = lwip_sendto(s, iecho, ping_size, 0, (struct sockaddr*)&to, sizeof(to));
+    rt_free(iecho);
 
-	return (err ? ERR_OK : ERR_VAL);
+    return (err ? ERR_OK : ERR_VAL);
 }
 
 static void ping_recv(int s)
 {
-	char buf[64];
-	int fromlen, len;
-	struct sockaddr_in from;
-	struct ip_hdr *iphdr;
-	struct icmp_echo_hdr *iecho;
-	struct _ip_addr *addr;
+    char buf[64];
+    int fromlen, len;
+    struct sockaddr_in from;
+    struct ip_hdr *iphdr;
+    struct icmp_echo_hdr *iecho;
+    struct _ip_addr *addr;
 
-	while((len = lwip_recvfrom(s, buf, sizeof(buf), 0, (struct sockaddr*)&from, (socklen_t*)&fromlen)) > 0)
-	{
-		if (len >= (sizeof(struct ip_hdr)+sizeof(struct icmp_echo_hdr)))
-		{
-			addr = (struct _ip_addr *)&(from.sin_addr);
-			rt_kprintf("ping: recv %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+    while((len = lwip_recvfrom(s, buf, sizeof(buf), 0, (struct sockaddr*)&from, (socklen_t*)&fromlen)) > 0)
+    {
+        if (len >= (sizeof(struct ip_hdr)+sizeof(struct icmp_echo_hdr)))
+        {
+            addr = (struct _ip_addr *)&(from.sin_addr);
+            rt_kprintf("ping: recv %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
 
-			iphdr = (struct ip_hdr *)buf;
-			iecho = (struct icmp_echo_hdr *)(buf+(IPH_HL(iphdr) * 4));
-			if ((iecho->id == PING_ID) && (iecho->seqno == htons(ping_seq_num)))
-			{
-				return;
-			}
-			else
-			{
-				rt_kprintf("ping: drop\n");
-			}
-		}
-	}
+            iphdr = (struct ip_hdr *)buf;
+            iecho = (struct icmp_echo_hdr *)(buf+(IPH_HL(iphdr) * 4));
+            if ((iecho->id == PING_ID) && (iecho->seqno == htons(ping_seq_num)))
+            {
+                return;
+            }
+            else
+            {
+                rt_kprintf("ping: drop\n");
+            }
+        }
+    }
 
-	if (len <= 0)
-	{
-		rt_kprintf("ping: timeout\n");
-	}
+    if (len <= 0)
+    {
+        rt_kprintf("ping: timeout\n");
+    }
 }
 
 rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
 {
-	int s;
-	int timeout = PING_RCV_TIMEO;
-	struct ip_addr ping_target;
-	rt_uint32_t send_time;
-	struct _ip_addr
-	{
-		rt_uint8_t addr0, addr1, addr2, addr3;
-	} *addr;
+    int s;
+    int timeout = PING_RCV_TIMEO;
+    struct ip_addr ping_target;
+    rt_uint32_t send_time;
+    struct _ip_addr
+    {
+        rt_uint8_t addr0, addr1, addr2, addr3;
+    } *addr;
 
     send_time = 0;
-	
-	if(size == 0)
-		size = PING_DATA_SIZE;
 
-	if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
-	addr = (struct _ip_addr*)&ping_target;
+    if(size == 0)
+        size = PING_DATA_SIZE;
 
-	if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
-	{
-	    rt_kprintf("create socket failled\n");
-		return -RT_ERROR;
-	}
+    if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
+    addr = (struct _ip_addr*)&ping_target;
 
-	lwip_setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
+    if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
+    {
+        rt_kprintf("create socket failled\n");
+        return -RT_ERROR;
+    }
 
-	while (1)
-	{
-		if (ping_send(s, &ping_target, size) == ERR_OK)
-		{
-			rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
-			ping_recv(s);
-		}
-		else
-		{
-			rt_kprintf("ping: send %d.%d.%d.%d - error\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
-		}
+    lwip_setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
 
-		send_time ++;
-		if (send_time >= time) break; /* send ping times reached, stop */
+    while (1)
+    {
+        if (ping_send(s, &ping_target, size) == ERR_OK)
+        {
+            rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+            ping_recv(s);
+        }
+        else
+        {
+            rt_kprintf("ping: send %d.%d.%d.%d - error\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+        }
 
-		rt_thread_delay(PING_DELAY); /* take a delay */
-	}
-	
-	lwip_close(s);
+        send_time ++;
+        if (send_time >= time) break; /* send ping times reached, stop */
 
-	return RT_EOK;
+        rt_thread_delay(PING_DELAY); /* take a delay */
+    }
+
+    lwip_close(s);
+
+    return RT_EOK;
 }
 #ifdef RT_USING_FINSH
 #include <finsh.h>

From dc366ecf7a2946c8f071735f5f2065d51000240a Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Wed, 18 Jun 2014 11:16:21 +0800
Subject: [PATCH 05/86] device: only increase the ref_count when device is
 truly opened

---
 src/device.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/device.c b/src/device.c
index 75b88bf6eb..7ee130041c 100644
--- a/src/device.c
+++ b/src/device.c
@@ -239,11 +239,6 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag)
         return -RT_EBUSY;
     }
 
-    dev->ref_count++;
-    /* don't let bad things happen silently. If you are bitten by this assert,
-     * please set the ref_count to a bigger type. */
-    RT_ASSERT(dev->ref_count != 0);
-
     /* call device open interface */
     if (dev->open != RT_NULL)
     {
@@ -252,8 +247,15 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag)
 
     /* set open flag */
     if (result == RT_EOK || result == -RT_ENOSYS)
+    {
         dev->open_flag = oflag | RT_DEVICE_OFLAG_OPEN;
 
+        dev->ref_count++;
+        /* don't let bad things happen silently. If you are bitten by this assert,
+         * please set the ref_count to a bigger type. */
+        RT_ASSERT(dev->ref_count != 0);
+    }
+
     return result;
 }
 RTM_EXPORT(rt_device_open);

From aca8f8eb2d732af34be31b7c9dce43de5187496e Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Wed, 18 Jun 2014 11:18:43 +0800
Subject: [PATCH 06/86] shell: print the ref count in `list_device`

---
 components/finsh/cmd.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c
index 9a79ba396b..e449e0c2dc 100644
--- a/components/finsh/cmd.c
+++ b/components/finsh/cmd.c
@@ -471,17 +471,18 @@ static long _list_device(struct rt_list_node *list)
         "Unknown"
     };
 
-    rt_kprintf("device    type      \n");
-    rt_kprintf("-------- ---------- \n");
+    rt_kprintf("device   type                 ref count\n");
+    rt_kprintf("-------- -------------------- ----------\n");
     for (node = list->next; node != list; node = node->next)
     {
         device = (struct rt_device *)(rt_list_entry(node, struct rt_object, list));
-        rt_kprintf("%-8.*s %-8s \n",
+        rt_kprintf("%-8.*s %-20s %-8d\n",
                    RT_NAME_MAX,
                    device->parent.name,
                    (device->type <= RT_Device_Class_Unknown) ?
                    device_type_str[device->type] :
-                   device_type_str[RT_Device_Class_Unknown]);
+                   device_type_str[RT_Device_Class_Unknown],
+                   device->ref_count);
     }
 
     return 0;

From bf733ae2aab82c65d538a686dc9571c7afd3cfb5 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Tue, 24 Jun 2014 14:49:33 +0800
Subject: [PATCH 07/86] [LwIP] Fix the MEMP_NUM_TCP_SEG issue.

---
 components/net/lwip-1.4.1/src/lwipopts.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/components/net/lwip-1.4.1/src/lwipopts.h b/components/net/lwip-1.4.1/src/lwipopts.h
index 10cb7893a7..029a758747 100644
--- a/components/net/lwip-1.4.1/src/lwipopts.h
+++ b/components/net/lwip-1.4.1/src/lwipopts.h
@@ -117,6 +117,8 @@
 
 /* the number of simultaneously queued TCP */
 #ifdef RT_LWIP_TCP_SEG_NUM
+#define MEMP_NUM_TCP_SEG            RT_LWIP_TCP_SEG_NUM
+#else
 #define MEMP_NUM_TCP_SEG            TCP_SND_QUEUELEN
 #endif
 
@@ -176,7 +178,7 @@
 
 /* TCP sender buffer space (bytes). */
 #ifdef RT_LWIP_TCP_SND_BUF
-#define TCP_SND_BUF					RT_LWIP_TCP_SND_BUF
+#define TCP_SND_BUF					   RT_LWIP_TCP_SND_BUF
 #else
 #define TCP_SND_BUF                 (TCP_MSS * 2)
 #endif

From d10444337bed805965737e70820588ea179ba75e Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Tue, 24 Jun 2014 15:14:39 +0800
Subject: [PATCH 08/86] [lwIP] code cleanup

---
 components/net/lwip-1.4.1/src/lwipopts.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/components/net/lwip-1.4.1/src/lwipopts.h b/components/net/lwip-1.4.1/src/lwipopts.h
index 029a758747..dd5a3ace96 100644
--- a/components/net/lwip-1.4.1/src/lwipopts.h
+++ b/components/net/lwip-1.4.1/src/lwipopts.h
@@ -137,12 +137,12 @@
 /* ---------- Pbuf options ---------- */
 /* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
 #ifdef RT_LWIP_PBUF_NUM
-#define PBUF_POOL_SIZE              RT_LWIP_PBUF_NUM
+#define PBUF_POOL_SIZE               RT_LWIP_PBUF_NUM
 #endif
 
 /* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
 #ifdef RT_LWIP_PBUF_POOL_BUFSIZE
-#define PBUF_POOL_BUFSIZE			 RT_LWIP_PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE            RT_LWIP_PBUF_POOL_BUFSIZE
 #endif
 
 /* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
@@ -178,7 +178,7 @@
 
 /* TCP sender buffer space (bytes). */
 #ifdef RT_LWIP_TCP_SND_BUF
-#define TCP_SND_BUF					   RT_LWIP_TCP_SND_BUF
+#define TCP_SND_BUF                 RT_LWIP_TCP_SND_BUF
 #else
 #define TCP_SND_BUF                 (TCP_MSS * 2)
 #endif
@@ -309,7 +309,7 @@
  * in this file.
  */
 #ifdef RT_LWIP_PPPOE
-#define PPPOE_SUPPORT				1
+#define PPPOE_SUPPORT               1
 #else
 #define PPPOE_SUPPORT               0
 #endif
@@ -317,7 +317,7 @@
 #ifdef RT_LWIP_PPPOS
 #define PPPOS_SUPPORT               1
 #else
-#define PPPOS_SUPPORT				0
+#define PPPOS_SUPPORT               0
 #endif
 
 #define PAP_SUPPORT                 1      /* Set > 0 for PAP. */

From a58593f784d4b84ce09f194c15bc79e20a80aa6a Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Wed, 25 Jun 2014 17:20:57 +0800
Subject: [PATCH 09/86] [libc] code cleanup.

---
 components/libc/armlibc/stubs.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/components/libc/armlibc/stubs.c b/components/libc/armlibc/stubs.c
index 301f654182..d219b3430a 100644
--- a/components/libc/armlibc/stubs.c
+++ b/components/libc/armlibc/stubs.c
@@ -46,8 +46,10 @@ const char __stderr_name[] = "STDERR";
  */
 FILEHANDLE _sys_open(const char *name, int openmode)
 {
+#ifdef RT_USING_DFS    
     int fd;
-
+#endif
+    
     /* Register standard Input Output devices. */
     if (strcmp(name, __stdin_name) == 0)
         return (STDIN);
@@ -91,12 +93,13 @@ int _sys_close(FILEHANDLE fh)
  */
 int _sys_read(FILEHANDLE fh, unsigned char *buf, unsigned len, int mode)
 {
+#ifdef RT_USING_DFS    
     int size;
-
+#endif
+    
     if (fh == STDIN)
     {
         /* TODO */
-
         return 0;
     }
 
@@ -125,8 +128,10 @@ int _sys_read(FILEHANDLE fh, unsigned char *buf, unsigned len, int mode)
  */
 int _sys_write(FILEHANDLE fh, const unsigned char *buf, unsigned len, int mode)
 {
+#ifdef RT_USING_DFS
     int size;
-
+#endif
+    
     if ((fh == STDOUT) || (fh == STDERR))
     {
 #ifndef RT_USING_CONSOLE

From dcd79747947803dbc724bcd49bcfca42a5932c06 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Wed, 25 Jun 2014 17:23:28 +0800
Subject: [PATCH 10/86] [Finsh] Enhance mv command.

---
 components/finsh/msh_cmd.c | 44 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/components/finsh/msh_cmd.c b/components/finsh/msh_cmd.c
index 3bbd46958f..7c67681833 100644
--- a/components/finsh/msh_cmd.c
+++ b/components/finsh/msh_cmd.c
@@ -88,8 +88,50 @@ int cmd_mv(int argc, char** argv)
     }
     else
     {
+		int fd;
+		char *dest = RT_NULL;
+
         rt_kprintf("%s => %s\n", argv[1], argv[2]);
-		rename(argv[1], argv[2]);
+
+		fd = open(argv[2], O_DIRECTORY, 0);
+		if (fd >= 0)
+		{
+			char *src;
+			
+			close(fd);
+
+			/* it's a directory */			
+			dest = (char*)rt_malloc(DFS_PATH_MAX);
+			if (dest == RT_NULL)
+			{
+				rt_kprintf("out of memory\n");
+				return -RT_ENOMEM;
+			}
+
+			src = argv[1] + rt_strlen(argv[1]);
+			while (src != argv[1]) 
+			{
+				if (*src == '/') break;
+				src --;
+			}
+
+			rt_snprintf(dest, DFS_PATH_MAX - 1, "%s/%s", argv[2], src);
+		}
+		else
+		{
+			fd = open(argv[2], O_RDONLY, 0);
+			if (fd >= 0)
+			{
+				close(fd);
+				
+				unlink(argv[2]);
+			}
+
+			dest = argv[2];
+		}
+
+		rename(argv[1], dest);
+		if (dest != RT_NULL && dest != argv[2]) rt_free(dest);
     }
 
     return 0;

From a118801bfeefb8579255f04f8fcab540a2f0deba Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 26 Jun 2014 13:59:26 +0800
Subject: [PATCH 11/86] [DFS] Add dfs_filesystem_get_mounted_path() function.

---
 components/dfs/include/dfs_fs.h |  2 ++
 components/dfs/src/dfs_fs.c     | 31 +++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/components/dfs/include/dfs_fs.h b/components/dfs/include/dfs_fs.h
index 3fa999c344..498aa5db54 100644
--- a/components/dfs/include/dfs_fs.h
+++ b/components/dfs/include/dfs_fs.h
@@ -94,6 +94,8 @@ struct dfs_mount_tbl
 
 int dfs_register(const struct dfs_filesystem_operation *ops);
 struct dfs_filesystem *dfs_filesystem_lookup(const char *path);
+const char* dfs_filesystem_get_mounted_path(struct rt_device* device);
+
 rt_err_t dfs_filesystem_get_partition(struct dfs_partition *part,
                                       rt_uint8_t           *buf,
                                       rt_uint32_t           pindex);
diff --git a/components/dfs/src/dfs_fs.c b/components/dfs/src/dfs_fs.c
index a41f36cf09..bdd9560d56 100644
--- a/components/dfs/src/dfs_fs.c
+++ b/components/dfs/src/dfs_fs.c
@@ -115,6 +115,37 @@ struct dfs_filesystem *dfs_filesystem_lookup(const char *path)
     return fs;
 }
 
+/**
+ * this function will return the mounted path for specified device. 
+ *
+ * @param device the device object which is mounted.
+ *
+ * @return the mounted path or RT_NULL if none device mounted. 
+ */
+const char* dfs_filesystem_get_mounted_path(struct rt_device* device)
+{
+	const char* path = RT_NULL;
+    struct dfs_filesystem *iter;
+
+    dfs_lock();
+    for (iter = &filesystem_table[0];
+            iter < &filesystem_table[DFS_FILESYSTEMS_MAX]; iter++)
+    {
+		/* fint the mounted device */
+        if (iter->ops == RT_NULL) continue;
+		else if (iter->dev_id == device) 
+		{
+			path = iter->path;
+			break;
+		}
+    }
+
+    /* release filesystem_table lock */
+    dfs_unlock();
+
+	return path;
+}
+
 /**
  * this function will fetch the partition table on specified buffer.
  *

From ceaf9cd3fabc142177ea50da758cdc0cb659e61f Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 26 Jun 2014 14:47:31 +0800
Subject: [PATCH 12/86] Add WEAK definition; Add AUTO Refresh option for block
 device.

---
 include/rtdef.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/rtdef.h b/include/rtdef.h
index e6b302d298..01ccc3fc44 100644
--- a/include/rtdef.h
+++ b/include/rtdef.h
@@ -96,6 +96,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define UNUSED                      __attribute__((unused))
     #define USED                        __attribute__((used))
     #define ALIGN(n)                    __attribute__((aligned(n)))
+    #define WEAK						__weak
     #define rt_inline                   static __inline
     /* module compiling */
     #ifdef RT_USING_MODULE
@@ -111,6 +112,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define USED
     #define PRAGMA(x)                   _Pragma(#x)
     #define ALIGN(n)                    PRAGMA(data_alignment=n)
+    #define WEAK                        __weak
     #define rt_inline                   static inline
     #define RTT_API
 
@@ -130,6 +132,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define UNUSED                      __attribute__((unused))
     #define USED                        __attribute__((used))
     #define ALIGN(n)                    __attribute__((aligned(n)))
+    #define WEAK						__attribute__((weak))
     #define rt_inline                   static __inline
     #define RTT_API
 #elif defined (__ADSPBLACKFIN__)        /* for VisualDSP++ Compiler */
@@ -138,6 +141,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define UNUSED                      __attribute__((unused))
     #define USED                        __attribute__((used))
     #define ALIGN(n)                    __attribute__((aligned(n)))
+	#define WEAK                        __attribute__((weak))
     #define rt_inline                   static inline
     #define RTT_API
 #elif defined (_MSC_VER)
@@ -146,6 +150,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define UNUSED
     #define USED
     #define ALIGN(n)                    __declspec(align(n))
+	#define WEAK
     #define rt_inline                   static __inline
     #define RTT_API
 #elif defined (__TI_COMPILER_VERSION__)
@@ -158,6 +163,7 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define USED
 	#define PRAGMA(x)					_Pragma(#x)
     #define ALIGN(n)
+	#define WEAK
     #define rt_inline                   static inline
     #define RTT_API
 #else
@@ -793,6 +799,7 @@ enum rt_device_class_type
 #define RT_DEVICE_CTRL_BLK_GETGEOME     0x10            /**< get geometry information   */
 #define RT_DEVICE_CTRL_BLK_SYNC         0x11            /**< flush data to block device */
 #define RT_DEVICE_CTRL_BLK_ERASE        0x12            /**< erase block on block device */
+#define RT_DEVICE_CTRL_BLK_AUTOREFRESH  0x13            /**< block device : enter/exit auto refresh mode */
 #define RT_DEVICE_CTRL_NETIF_GETMAC     0x10            /**< get mac address */
 #define RT_DEVICE_CTRL_MTD_FORMAT       0x10            /**< format a MTD device */
 #define RT_DEVICE_CTRL_RTC_GET_TIME     0x10            /**< get time */

From a1766b6c7131f93cf7c641ec96d3bd08b7b86360 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 26 Jun 2014 14:47:53 +0800
Subject: [PATCH 13/86] Add WEAK definition;

---
 src/kservice.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/src/kservice.c b/src/kservice.c
index 0f06806087..cb0064f38b 100644
--- a/src/kservice.c
+++ b/src/kservice.c
@@ -1081,19 +1081,7 @@ rt_device_t rt_console_set_device(const char *name)
 RTM_EXPORT(rt_console_set_device);
 #endif
 
-#if defined(__GNUC__) || defined(__ADSPBLACKFIN__)
-void rt_hw_console_output(const char *str) __attribute__((weak));
-void rt_hw_console_output(const char *str)
-#elif defined(__CC_ARM)
-__weak void rt_hw_console_output(const char *str)
-#elif defined(__IAR_SYSTEMS_ICC__)
-    #if __VER__ > 540
-    __weak
-    #endif
-void rt_hw_console_output(const char *str)
-#else
-void rt_hw_console_output(const char *str)
-#endif
+WEAK void rt_hw_console_output(const char *str)
 {
     /* empty console output */
 }

From 7dbb4dc9390726e0d547b9e090b1e32ba260a45f Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 26 Jun 2014 15:55:45 +0800
Subject: [PATCH 14/86] [lwIP] Add LWIP_NO_RX_THREAD/LWIP_NO_TX_THREAD options
 for lwIP.

---
 .../lwip-1.4.1/src/include/netif/ethernetif.h |  4 ++
 components/net/lwip-1.4.1/src/lwipopts.h      | 10 ++++-
 .../net/lwip-1.4.1/src/netif/ethernetif.c     | 45 +++++++++++++++++--
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/components/net/lwip-1.4.1/src/include/netif/ethernetif.h b/components/net/lwip-1.4.1/src/include/netif/ethernetif.h
index 53dacf2270..2019df7017 100644
--- a/components/net/lwip-1.4.1/src/include/netif/ethernetif.h
+++ b/components/net/lwip-1.4.1/src/include/netif/ethernetif.h
@@ -5,7 +5,11 @@
 #include <rtthread.h>
 
 #define NIOCTL_GADDR		0x01
+#ifndef RT_LWIP_ETH_MTU
 #define ETHERNET_MTU		1500
+#else
+#define ETHERNET_MTU		RT_LWIP_ETH_MTU
+#endif
 
 struct eth_device
 {
diff --git a/components/net/lwip-1.4.1/src/lwipopts.h b/components/net/lwip-1.4.1/src/lwipopts.h
index dd5a3ace96..bff172e280 100644
--- a/components/net/lwip-1.4.1/src/lwipopts.h
+++ b/components/net/lwip-1.4.1/src/lwipopts.h
@@ -38,8 +38,9 @@
 #define LWIP_PLATFORM_BYTESWAP      0
 #define BYTE_ORDER                  LITTLE_ENDIAN
 
-/* Enable SO_RCVTIMEO processing.   */
+/* Enable SO_RCVTIMEO/LWIP_SO_SNDTIMEO processing.   */
 #define LWIP_SO_RCVTIMEO            1
+#define LWIP_SO_SNDTIMEO            1
 
 /* #define RT_LWIP_DEBUG */
 
@@ -232,10 +233,15 @@
 
 /* IP reassembly and segmentation.These are orthogonal even
  * if they both deal with IP fragments */
-#define IP_REASSEMBLY               0
+#ifdef RT_LWIP_REASSEMBLY_FRAG
+#define IP_REASSEMBLY               1
+#define IP_FRAG                     1
 #define IP_REASS_MAX_PBUFS          10
 #define MEMP_NUM_REASSDATA          10
+#else
+#define IP_REASSEMBLY               0
 #define IP_FRAG                     0
+#endif
 
 /* ---------- ICMP options ---------- */
 #define ICMP_TTL                    255
diff --git a/components/net/lwip-1.4.1/src/netif/ethernetif.c b/components/net/lwip-1.4.1/src/netif/ethernetif.c
index 2853fdcd7c..ab7743290a 100644
--- a/components/net/lwip-1.4.1/src/netif/ethernetif.c
+++ b/components/net/lwip-1.4.1/src/netif/ethernetif.c
@@ -67,6 +67,7 @@
 #define netifapi_netif_set_link_up(n)      netifapi_netif_common(n, netif_set_link_up, NULL)
 #define netifapi_netif_set_link_down(n)    netifapi_netif_common(n, netif_set_link_down, NULL)
 
+#ifndef LWIP_NO_TX_THREAD
 /**
  * Tx message structure for Ethernet interface
  */
@@ -85,7 +86,9 @@ static char eth_tx_thread_stack[512];
 static char eth_tx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4];
 static char eth_tx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE];
 #endif
+#endif
 
+#ifndef LWIP_NO_RX_THREAD
 static struct rt_mailbox eth_rx_thread_mb;
 static struct rt_thread eth_rx_thread;
 #ifndef RT_LWIP_ETHTHREAD_PRIORITY
@@ -97,12 +100,15 @@ static char eth_rx_thread_stack[1024];
 static char eth_rx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4];
 static char eth_rx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE];
 #endif
+#endif
 
 static err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p)
 {
+#ifndef LWIP_NO_TX_THREAD
     struct eth_tx_msg msg;
     struct eth_device* enetif;
 
+	RT_ASSERT(netif != RT_NULL);
     enetif = (struct eth_device*)netif->state;
 
     /* send a message to eth tx thread */
@@ -113,7 +119,17 @@ static err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p)
         /* waiting for ack */
         rt_sem_take(&(enetif->tx_ack), RT_WAITING_FOREVER);
     }
+#else
+    struct eth_device* enetif;
 
+	RT_ASSERT(netif != RT_NULL);
+    enetif = (struct eth_device*)netif->state;
+
+	if (enetif->eth_tx(&(enetif->parent), p) != RT_EOK)
+	{
+		return ERR_IF;
+	}
+#endif
     return ERR_OK;
 }
 
@@ -241,6 +257,7 @@ rt_err_t eth_device_init(struct eth_device * dev, char *name)
     return eth_device_init_with_flag(dev, name, flags);
 }
 
+#ifndef LWIP_NO_RX_THREAD
 rt_err_t eth_device_ready(struct eth_device* dev)
 {
     if (dev->netif)
@@ -267,7 +284,20 @@ rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up)
     /* post message to ethernet thread */
     return rt_mb_send(&eth_rx_thread_mb, (rt_uint32_t)dev);
 }
+#else
+/* NOTE: please not use it in interrupt when no RxThread exist */
+rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up)
+{
+	if (up == RT_TRUE)
+		netifapi_netif_set_link_up(dev->netif);
+	else
+		netifapi_netif_set_link_down(dev->netif);
 
+	return RT_EOK;
+}
+#endif
+
+#ifndef LWIP_NO_TX_THREAD
 /* Ethernet Tx Thread */
 static void eth_tx_thread_entry(void* parameter)
 {
@@ -297,7 +327,9 @@ static void eth_tx_thread_entry(void* parameter)
         }
     }
 }
+#endif
 
+#ifndef LWIP_NO_RX_THREAD
 /* Ethernet Rx Thread */
 static void eth_rx_thread_entry(void* parameter)
 {
@@ -349,13 +381,15 @@ static void eth_rx_thread_entry(void* parameter)
         }
     }
 }
+#endif
 
 int eth_system_device_init(void)
 {
     rt_err_t result = RT_EOK;
 
-    /* initialize Rx thread.
-     * initialize mailbox and create Ethernet Rx thread */
+    /* initialize Rx thread. */
+#ifndef LWIP_NO_RX_THREAD
+    /* initialize mailbox and create Ethernet Rx thread */
     result = rt_mb_init(&eth_rx_thread_mb, "erxmb",
                         &eth_rx_thread_mb_pool[0], sizeof(eth_rx_thread_mb_pool)/4,
                         RT_IPC_FLAG_FIFO);
@@ -367,8 +401,10 @@ int eth_system_device_init(void)
     RT_ASSERT(result == RT_EOK);
     result = rt_thread_startup(&eth_rx_thread);
     RT_ASSERT(result == RT_EOK);
+#endif
 
     /* initialize Tx thread */
+#ifndef LWIP_NO_TX_THREAD
     /* initialize mailbox and create Ethernet Tx thread */
     result = rt_mb_init(&eth_tx_thread_mb, "etxmb",
                         &eth_tx_thread_mb_pool[0], sizeof(eth_tx_thread_mb_pool)/4,
@@ -382,8 +418,9 @@ int eth_system_device_init(void)
 
     result = rt_thread_startup(&eth_tx_thread);
     RT_ASSERT(result == RT_EOK);
-	
-	return 0;
+#endif
+
+	return (int)result;
 }
 INIT_DEVICE_EXPORT(eth_system_device_init);
 

From e175b0724dcc7cf35edeccf6d19222add34a23b0 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Fri, 27 Jun 2014 13:35:12 +0800
Subject: [PATCH 15/86] [BSP] Fix compiling error

---
 bsp/lpc176x/rtconfig.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h
index 61b2f82711..8aefe475d3 100644
--- a/bsp/lpc176x/rtconfig.h
+++ b/bsp/lpc176x/rtconfig.h
@@ -149,8 +149,6 @@
 // #define RT_LWIP_SNMP
 // <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
 // #define RT_LWIP_DHCP
-// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
-#define RT_LWIP_TCP_SEG_NUM	4
 // <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
 #define RT_LWIP_TCPTHREAD_PRIORITY	12
 // <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />

From 97fb91dcc675d058309570dcbdd5c3120ebcf118 Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Fri, 27 Jun 2014 12:26:24 +0800
Subject: [PATCH 16/86] bsp: add zynq7000

---
 bsp/zynq7000/README.txt                 |   5 +
 bsp/zynq7000/SConscript                 |  14 ++
 bsp/zynq7000/SConstruct                 |  34 +++
 bsp/zynq7000/applications/SConscript    |  11 +
 bsp/zynq7000/applications/application.c |  49 ++++
 bsp/zynq7000/applications/startup.c     |  81 +++++++
 bsp/zynq7000/drivers/SConscript         |  22 ++
 bsp/zynq7000/drivers/board.c            |  88 +++++++
 bsp/zynq7000/drivers/board.h            |  64 +++++
 bsp/zynq7000/drivers/uart.c             | 304 +++++++++++++++++++++++
 bsp/zynq7000/drivers/uart_hw.h          | 307 ++++++++++++++++++++++++
 bsp/zynq7000/drivers/zynq7000.h         |  59 +++++
 bsp/zynq7000/rtconfig.h                 | 143 +++++++++++
 bsp/zynq7000/rtconfig.py                |  84 +++++++
 bsp/zynq7000/zynq7000.ld                | 116 +++++++++
 libcpu/arm/zynq7000/SConscript          |  17 ++
 libcpu/arm/zynq7000/armv7.h             |  65 +++++
 libcpu/arm/zynq7000/context_gcc.S       | 102 ++++++++
 libcpu/arm/zynq7000/cp15.h              |  31 +++
 libcpu/arm/zynq7000/cp15_gcc.S          | 140 +++++++++++
 libcpu/arm/zynq7000/cpu.c               |  45 ++++
 libcpu/arm/zynq7000/gic.c               | 239 ++++++++++++++++++
 libcpu/arm/zynq7000/gic.h               |  41 ++++
 libcpu/arm/zynq7000/interrupt.c         | 143 +++++++++++
 libcpu/arm/zynq7000/interrupt.h         |  26 ++
 libcpu/arm/zynq7000/mmu.c               | 182 ++++++++++++++
 libcpu/arm/zynq7000/stack.c             |  60 +++++
 libcpu/arm/zynq7000/start_gcc.S         | 254 ++++++++++++++++++++
 libcpu/arm/zynq7000/trap.c              | 185 ++++++++++++++
 libcpu/arm/zynq7000/vector_gcc.S        |  65 +++++
 30 files changed, 2976 insertions(+)
 create mode 100644 bsp/zynq7000/README.txt
 create mode 100644 bsp/zynq7000/SConscript
 create mode 100644 bsp/zynq7000/SConstruct
 create mode 100644 bsp/zynq7000/applications/SConscript
 create mode 100644 bsp/zynq7000/applications/application.c
 create mode 100644 bsp/zynq7000/applications/startup.c
 create mode 100644 bsp/zynq7000/drivers/SConscript
 create mode 100644 bsp/zynq7000/drivers/board.c
 create mode 100644 bsp/zynq7000/drivers/board.h
 create mode 100644 bsp/zynq7000/drivers/uart.c
 create mode 100644 bsp/zynq7000/drivers/uart_hw.h
 create mode 100644 bsp/zynq7000/drivers/zynq7000.h
 create mode 100644 bsp/zynq7000/rtconfig.h
 create mode 100644 bsp/zynq7000/rtconfig.py
 create mode 100644 bsp/zynq7000/zynq7000.ld
 create mode 100644 libcpu/arm/zynq7000/SConscript
 create mode 100644 libcpu/arm/zynq7000/armv7.h
 create mode 100644 libcpu/arm/zynq7000/context_gcc.S
 create mode 100644 libcpu/arm/zynq7000/cp15.h
 create mode 100644 libcpu/arm/zynq7000/cp15_gcc.S
 create mode 100644 libcpu/arm/zynq7000/cpu.c
 create mode 100644 libcpu/arm/zynq7000/gic.c
 create mode 100644 libcpu/arm/zynq7000/gic.h
 create mode 100644 libcpu/arm/zynq7000/interrupt.c
 create mode 100644 libcpu/arm/zynq7000/interrupt.h
 create mode 100644 libcpu/arm/zynq7000/mmu.c
 create mode 100644 libcpu/arm/zynq7000/stack.c
 create mode 100644 libcpu/arm/zynq7000/start_gcc.S
 create mode 100644 libcpu/arm/zynq7000/trap.c
 create mode 100644 libcpu/arm/zynq7000/vector_gcc.S

diff --git a/bsp/zynq7000/README.txt b/bsp/zynq7000/README.txt
new file mode 100644
index 0000000000..f84aaa81e7
--- /dev/null
+++ b/bsp/zynq7000/README.txt
@@ -0,0 +1,5 @@
+Place the rtthread.bin in the SD card and run:
+
+     mmcinfo; fatload mmc 0 0x1ff00000 rtthread.bin; go 0x1ff00000
+
+in the uboot console.
diff --git a/bsp/zynq7000/SConscript b/bsp/zynq7000/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/zynq7000/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/zynq7000/SConstruct b/bsp/zynq7000/SConstruct
new file mode 100644
index 0000000000..9d9b35277a
--- /dev/null
+++ b/bsp/zynq7000/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.path.isdir('./rt-thread'):
+    RTT_ROOT = os.path.normpath(os.path.join(os.getcwd(), 'rt-thread/'))
+elif os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-zynq7000.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# if the linker script changed, relink the target
+Depends(TARGET, rtconfig.LINK_SCRIPT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/zynq7000/applications/SConscript b/bsp/zynq7000/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/zynq7000/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/zynq7000/applications/application.c b/bsp/zynq7000/applications/application.c
new file mode 100644
index 0000000000..ad89c80751
--- /dev/null
+++ b/bsp/zynq7000/applications/application.c
@@ -0,0 +1,49 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#ifdef RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+#include <cp15.h>
+
+/* thread phase init */
+static void rt_init_thread_entry(void *parameter)
+{
+    /* do component initialization */
+    rt_components_init();
+    rt_kprintf("running on cpu %d\n",
+               rt_cpu_get_smp_id() & 0x0f);
+
+    /* add your initialization here */
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
+                            RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+
+    return 0;
+}
+
diff --git a/bsp/zynq7000/applications/startup.c b/bsp/zynq7000/applications/startup.c
new file mode 100644
index 0000000000..d2958a2c58
--- /dev/null
+++ b/bsp/zynq7000/applications/startup.c
@@ -0,0 +1,81 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+extern int rt_application_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    rt_hw_mmu_init();
+
+    /* initialzie hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize system timer */
+    rt_system_timer_init();
+
+    /* initialize soft timer thread */
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}
+
diff --git a/bsp/zynq7000/drivers/SConscript b/bsp/zynq7000/drivers/SConscript
new file mode 100644
index 0000000000..a630c8a7c4
--- /dev/null
+++ b/bsp/zynq7000/drivers/SConscript
@@ -0,0 +1,22 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_LWIP') == False:
+    src_need_remove = ['dm9000.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+if GetDepend('RT_USING_DFS') == False:
+    src_need_remove = ['sd.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/zynq7000/drivers/board.c b/bsp/zynq7000/drivers/board.c
new file mode 100644
index 0000000000..1df6199b60
--- /dev/null
+++ b/bsp/zynq7000/drivers/board.c
@@ -0,0 +1,88 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <components.h>
+
+#include "board.h"
+
+typedef struct
+{
+    volatile rt_uint32_t LOAD;
+    volatile rt_uint32_t COUNTER;
+    volatile rt_uint32_t CONTROL;
+    volatile rt_uint32_t ISR;
+} ptimer_reg_t;
+
+/* Values for control register */
+#define PRIVATE_TIMER_CONTROL_PRESCALER_MASK     0x0000FF00
+#define PRIVATE_TIMER_CONTROL_PRESCALER_SHIFT    8
+#define PRIVATE_TIMER_CONTROL_IRQ_ENABLE_MASK    0x00000004
+#define PRIVATE_TIMER_CONTROL_AUTO_RELOAD_MASK   0x00000002
+#define PRIVATE_TIMER_CONTROL_ENABLE_MASK        0x00000001
+
+/* Values for ISR register */
+#define PRIVATE_TIMER_ISR_EVENT_FLAG_MASK        0x00000001
+
+
+#define PRIVATE_TIMER_BASE            0xF8F00600
+#define PRIVATE_TIMER                ((ptimer_reg_t*)PRIVATE_TIMER_BASE)
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    rt_tick_increase();
+    /* clear interrupt */
+    PRIVATE_TIMER->ISR = PRIVATE_TIMER_ISR_EVENT_FLAG_MASK;
+}
+
+int rt_hw_timer_init(void)
+{
+    PRIVATE_TIMER->CONTROL &= ~PRIVATE_TIMER_CONTROL_ENABLE_MASK;
+    {
+        /* Clear the prescaler. */
+        rt_uint32_t ctrl = PRIVATE_TIMER->CONTROL;
+        ctrl &= ~PRIVATE_TIMER_CONTROL_PRESCALER_MASK;
+        PRIVATE_TIMER->CONTROL = ctrl;
+    }
+    /* The processor timer is always clocked at 1/2 CPU frequency(CPU_3x2x). */
+    PRIVATE_TIMER->COUNTER = APU_FREQ/2/RT_TICK_PER_SECOND;
+    /* Set reload value. */
+    PRIVATE_TIMER->LOAD = APU_FREQ/2/RT_TICK_PER_SECOND;
+    PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_AUTO_RELOAD_MASK;
+
+    PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_IRQ_ENABLE_MASK;
+    PRIVATE_TIMER->ISR = PRIVATE_TIMER_ISR_EVENT_FLAG_MASK;
+
+    rt_hw_interrupt_install(IRQ_Zynq7000_PTIMER, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IRQ_Zynq7000_PTIMER);
+
+    PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_ENABLE_MASK;
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+void rt_hw_board_init()
+{
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
diff --git a/bsp/zynq7000/drivers/board.h b/bsp/zynq7000/drivers/board.h
new file mode 100644
index 0000000000..cfd617f824
--- /dev/null
+++ b/bsp/zynq7000/drivers/board.h
@@ -0,0 +1,64 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <zynq7000.h>
+
+/* Freq of all peripherals */
+#define APU_FREQ     666666667
+#define DDR_FREQ     533333313
+#define DCI_FREQ     10159000
+#define QSPI_FREQ    200000000
+#define SMC_FREQ     100000000
+#define ENET0_FREQ   125000000
+#define ENET1_FREQ   125000000
+#define USB0_FREQ    60000000
+#define USB1_FREQ    60000000
+#define SDIO_FREQ    50000000
+#define UART_FREQ    50000000
+#define SPI_FREQ     166666666
+#define I2C_FREQ     25000000
+#define WDT_FREQ     133333333
+#define TTC_FREQ     50000000
+#define CAN_FREQ     100000000
+#define PCAP_FREQ    200000000
+#define TPIU_FREQ    0
+#define FPGA0_FREQ   100000000
+#define FPGA1_FREQ   200000000
+#define FPGA2_FREQ   200000000
+#define FPGA3_FREQ   80000000
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+#endif
+
+#define HEAP_END        (void*)(0x20000000)
+
+void rt_hw_board_init();
+
+int rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/zynq7000/drivers/uart.c b/bsp/zynq7000/drivers/uart.c
new file mode 100644
index 0000000000..f10c48d330
--- /dev/null
+++ b/bsp/zynq7000/drivers/uart.c
@@ -0,0 +1,304 @@
+/*
+ *  serial.c UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "board.h"
+
+#include "gic.h"
+#include "cp15.h"
+
+#include "uart_hw.h"
+
+#define Zynq7000_UART_INT_DISABLE(UART)       \
+    (UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
+#define Zynq7000_UART_INT_ENABLE(UART)        \
+    (UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL))
+
+#define Zynq7000_UART_SENDCHAR(UART, ch)          \
+    do {                                     \
+        while ((UART->SR) & UART_SR_TXFULL); \
+        UART->FIFO = ch;                     \
+    } while(0)
+
+#define Zynq7000_UART_GETCHAR(UART, ch)                          \
+    do {                                                    \
+        if (UART->ISR & UART_SR_RXOVR)                      \
+        {                                                   \
+            ch = UART->FIFO & 0xff;                         \
+            UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \
+        }                                                   \
+    } while(0)
+
+static void UartEnable(UART_Registers* uart)
+{
+	uint32_t tmp = uart->CR;
+	tmp &= ~UART_CR_EN_DIS_MASK;
+	tmp |= (UART_CR_TX_EN | UART_CR_RX_EN);
+
+	uart->CR = tmp;
+}
+
+static void UartDisable(UART_Registers* uart)
+{
+	uint32_t tmp = uart->CR;
+	tmp &= ~UART_CR_EN_DIS_MASK;
+	tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS);
+	uart->CR = tmp;
+}
+
+static void UartResetTXRXLogic(UART_Registers* uart)
+{
+	uart->CR |= 0x03;
+    while (uart->CR & 0x03)
+        ;
+}
+
+/*                        PULLUP       | LVCMOS18     | Fast CMOS     | UART  */
+#define RX_MIO_PIN_MODE ((0x1UL << 12) | (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5))
+#define TX_MIO_PIN_MODE (                (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5))
+
+struct hw_uart_device
+{
+    UART_Registers * uart;
+    rt_uint32_t irqno;
+
+    /* MIO pin mode address */
+    rt_uint32_t *rxmio;
+    rt_uint32_t *txmio;
+};
+
+/* RT-Thread UART interface */
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial);
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    uint32_t mr;
+    struct hw_uart_device *pdev = serial->parent.user_data;
+    UART_Registers *uart = pdev->uart;
+
+    /* unlock SLCR */
+    __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UNLOCK) = 0xDF0D;
+
+    /* no loopback */
+    __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_MIO_LOOPBACK) &= ~(1 << 1);
+
+    if (uart == (void*)Zynq7000_UART0_BASE)
+    {
+        /* enable the coresponding AMBA Peripheral Clock */
+        __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 20;
+        /* enable uart clock. Divider 0x14 gives 50MHZ ref clock on IO PLL input. */
+        __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x01;
+        /* deassert the AMBA clock and software reset */
+        __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 2)|(0x01 << 0));
+    }
+    else if (uart == (void*)Zynq7000_UART1_BASE)
+    {
+        __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 21;
+        __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x02;
+        __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 3)|(0x01 << 1));
+    }
+    else
+        return -RT_ERROR;
+
+    UartDisable(uart);
+    UartResetTXRXLogic(uart);
+    UartEnable(uart);
+
+    mr = uart->MR & ~(UART_MR_CHARLEN_MASK |
+                      UART_MR_STOPMODE_MASK |
+                      UART_MR_PARITY_MASK);
+
+    if (cfg->stop_bits == STOP_BITS_2)
+        mr |= UART_MR_STOPMODE_2_BIT;
+    else if (cfg->stop_bits == STOP_BITS_1)
+        mr |= UART_MR_STOPMODE_1_BIT;
+    else
+        return -RT_ERROR;
+
+    if (cfg->parity == PARITY_EVEN)
+        mr |= UART_MR_PARITY_EVEN;
+    else if (cfg->parity == PARITY_ODD)
+        mr |= UART_MR_PARITY_ODD;
+    else if (cfg->parity == PARITY_NONE)
+        mr |= UART_MR_PARITY_NONE;
+    else
+        return -1;
+
+    if (cfg->data_bits == DATA_BITS_8)
+        mr |= UART_MR_CHARLEN_8_BIT;
+    else if (cfg->data_bits == DATA_BITS_7)
+        mr |= UART_MR_CHARLEN_7_BIT;
+    else if (cfg->data_bits == DATA_BITS_6)
+        mr |= UART_MR_CHARLEN_6_BIT;
+    else
+        return -RT_ERROR;
+
+	uart->MR = mr;
+
+    uart->TXWM = 8;
+    uart->RXWM = 1;
+
+    if (cfg->baud_rate == BAUD_RATE_115200)
+    {
+        uart->BAUDGEN = UART_BAUDGEN_115200;
+        uart->BAUDDIV = UART_BAUDDIV_115200;
+    }
+    else
+    {
+        rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate);
+    }
+
+    /* disable all interrupts */
+    uart->IDR = UART_IXR_MASK;
+
+    /* configure the pin */
+    *(pdev->txmio) = TX_MIO_PIN_MODE;
+    *(pdev->rxmio) = RX_MIO_PIN_MODE;
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *pdev;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    pdev = serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        Zynq7000_UART_INT_DISABLE(pdev->uart);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        Zynq7000_UART_INT_ENABLE(pdev->uart);
+        rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, "uart");
+        /* set the interrupt to this cpu */
+        arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id());
+        rt_hw_interrupt_umask(pdev->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *dev;
+
+    RT_ASSERT(serial != RT_NULL);
+    dev = (struct hw_uart_device *)serial->parent.user_data;
+
+    Zynq7000_UART_SENDCHAR(dev->uart, c);
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct hw_uart_device *dev;
+
+    RT_ASSERT(serial != RT_NULL);
+    dev = (struct hw_uart_device *)serial->parent.user_data;
+
+    ch = -1;
+    Zynq7000_UART_GETCHAR(dev->uart, ch);
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+/* UART device driver structure */
+static struct hw_uart_device _uart_device0 =
+{
+    .uart  = (UART_Registers*)Zynq7000_UART0_BASE,
+    .irqno = IRQ_Zynq7000_UART0,
+    .rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x0728), /* MIO10 */
+    .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x072C), /* MIO11 */
+};
+static struct hw_uart_device _uart_device1 =
+{
+    .uart  = (UART_Registers*)Zynq7000_UART1_BASE,
+    .irqno = IRQ_Zynq7000_UART1,
+    .rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C4), /* MIO49 */
+    .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C0), /* MIO48 */
+};
+
+static struct serial_ringbuffer _uart_int_rx0;
+static struct rt_serial_device _serial0;
+static struct serial_ringbuffer _uart_int_rx1;
+static struct rt_serial_device _serial1;
+
+int rt_hw_uart_init(void)
+{
+    struct serial_configure config;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.int_rx = &_uart_int_rx0;
+    _serial0.config = config;
+
+    _serial1.ops    = &_uart_ops;
+    _serial1.int_rx = &_uart_int_rx1;
+    _serial1.config = config;
+
+    /* register uart device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &_uart_device0);
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &_uart_device1);
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
diff --git a/bsp/zynq7000/drivers/uart_hw.h b/bsp/zynq7000/drivers/uart_hw.h
new file mode 100644
index 0000000000..75e3937559
--- /dev/null
+++ b/bsp/zynq7000/drivers/uart_hw.h
@@ -0,0 +1,307 @@
+#ifndef _UART_HW_H_
+#define _UART_HW_H_
+
+#include <stdint.h>
+
+/** @name Register Map
+ *
+ * Registers of the UART.
+ * @{
+ */
+typedef struct
+{
+    volatile uint32_t CR;            /**< Control Register */
+    volatile uint32_t MR;            /**< Mode Register */
+    volatile uint32_t IER;           /**< Interrupt Enable */
+    volatile uint32_t IDR;           /**< Interrupt Disable */
+    volatile uint32_t IMR;           /**< Interrupt Mask */
+    volatile uint32_t ISR;           /**< Interrupt Status */
+    volatile uint32_t BAUDGEN;       /**< Baud Rate Generator */
+    volatile uint32_t RXTOUT;        /**< RX Timeout */
+    volatile uint32_t RXWM;          /**< RX FIFO Trigger Level */
+    volatile uint32_t MODEMCR;       /**< Modem Control */
+    volatile uint32_t MODEMSR;       /**< Modem Status */
+    volatile uint32_t SR;            /**< Channel Status */
+    volatile uint32_t FIFO;          /**< FIFO */
+    volatile uint32_t BAUDDIV;       /**< Baud Rate Divider */
+    volatile uint32_t FLOWDEL;       /**< Flow Delay */
+    volatile uint32_t RESERVED1;
+    volatile uint32_t RESERVED2;
+    volatile uint32_t TXWM;            /* TX FIFO Trigger Level */
+} UART_Registers;
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+#define UART_CR_STOPBRK             0x00000100        /**< Stop transmission of break */
+#define UART_CR_STARTBRK            0x00000080        /**< Set break */
+#define UART_CR_TORST               0x00000040        /**< RX timeout counter restart */
+#define UART_CR_TX_DIS              0x00000020        /**< TX disabled. */
+#define UART_CR_TX_EN               0x00000010        /**< TX enabled */
+#define UART_CR_RX_DIS              0x00000008        /**< RX disabled. */
+#define UART_CR_RX_EN               0x00000004        /**< RX enabled */
+#define UART_CR_EN_DIS_MASK         0x0000003C        /**< Enable/disable Mask */
+#define UART_CR_TXRST               0x00000002        /**< TX logic reset */
+#define UART_CR_RXRST               0x00000001        /**< RX logic reset */
+/* @}*/
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define UART_MR_CCLK                0x00000400        /**< Input clock selection */
+#define UART_MR_CHMODE_R_LOOP       0x00000300        /**< Remote loopback mode */
+#define UART_MR_CHMODE_L_LOOP       0x00000200        /**< Local loopback mode */
+#define UART_MR_CHMODE_ECHO         0x00000100        /**< Auto echo mode */
+#define UART_MR_CHMODE_NORM         0x00000000        /**< Normal mode */
+#define UART_MR_CHMODE_SHIFT        8                /**< Mode shift */
+#define UART_MR_CHMODE_MASK         0x00000300        /**< Mode mask */
+#define UART_MR_STOPMODE_2_BIT      0x00000080        /**< 2 stop bits */
+#define UART_MR_STOPMODE_1_5_BIT    0x00000040        /**< 1.5 stop bits */
+#define UART_MR_STOPMODE_1_BIT      0x00000000        /**< 1 stop bit */
+#define UART_MR_STOPMODE_SHIFT      6                /**< Stop bits shift */
+#define UART_MR_STOPMODE_MASK       0x000000A0        /**< Stop bits mask */
+#define UART_MR_PARITY_NONE         0x00000020        /**< No parity mode */
+#define UART_MR_PARITY_MARK         0x00000018        /**< Mark parity mode */
+#define UART_MR_PARITY_SPACE        0x00000010        /**< Space parity mode */
+#define UART_MR_PARITY_ODD          0x00000008        /**< Odd parity mode */
+#define UART_MR_PARITY_EVEN         0x00000000        /**< Even parity mode */
+#define UART_MR_PARITY_SHIFT        3                /**< Parity setting shift */
+#define UART_MR_PARITY_MASK         0x00000038        /**< Parity mask */
+#define UART_MR_CHARLEN_6_BIT       0x00000006        /**< 6 bits data */
+#define UART_MR_CHARLEN_7_BIT       0x00000004        /**< 7 bits data */
+#define UART_MR_CHARLEN_8_BIT       0x00000000        /**< 8 bits data */
+#define UART_MR_CHARLEN_SHIFT       1                /**< Data Length shift */
+#define UART_MR_CHARLEN_MASK        0x00000006        /**< Data length mask */
+#define UART_MR_CLKSEL              0x00000001        /**< Input clock selection */
+/* @} */
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define UART_IXR_DMS                0x00000200        /**< Modem status change interrupt */
+#define UART_IXR_TOUT               0x00000100        /**< Timeout error interrupt */
+#define UART_IXR_PARITY             0x00000080        /**< Parity error interrupt */
+#define UART_IXR_FRAMING            0x00000040        /**< Framing error interrupt */
+#define UART_IXR_OVER               0x00000020        /**< Overrun error interrupt */
+#define UART_IXR_TXFULL             0x00000010        /**< TX FIFO full interrupt. */
+#define UART_IXR_TXEMPTY            0x00000008        /**< TX FIFO empty interrupt. */
+#define UART_IXR_RXFULL             0x00000004        /**< RX FIFO full interrupt. */
+#define UART_IXR_RXEMPTY            0x00000002        /**< RX FIFO empty interrupt. */
+#define UART_IXR_RXOVR              0x00000001        /**< RX FIFO trigger interrupt. */
+#define UART_IXR_MASK               0x000003FF        /**< Valid bit mask */
+/* @} */
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define UART_BAUDGEN_DISABLE        0x00000000        /**< Disable clock */
+#define UART_BAUDGEN_MASK           0x0000FFFF        /**< Valid bits mask */
+/* @} */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define UART_BAUDDIV_MASK            0x000000FF        /**< 8 bit baud divider mask */
+/* @} */
+
+/*
+    Page 496
+    Simplifyed Table 19-1 UART Parameter Value Examples
+    Parameter Value Examples
+    Clock                Baud  BRGR-CD   BDIV-CD                    Actual Baud Rate
+    UART Ref clock        600   10417     7
+    UART Ref clock      9,600     651     7
+    UART Ref clock     28,800     347     4
+    UART Ref clock    115,200      62     6
+    UART Ref clock    230,400      31     6
+*/
+
+/*Baudrates assuming input clock speed is 3125000L */
+/*Baud_rate_gen_reg0*/
+#define UART_BAUDGEN_115200       62 /*Baud Rate Clock Divisor*/
+
+/*Register Baud_rate_divider_reg0 Details*/
+#define UART_BAUDDIV_115200       6  /*Baud Rate Clock Divisor*/
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define UART_RXTOUT_DISABLE          0x00000000        /**< Disable time out */
+#define UART_RXTOUT_MASK             0x000000FF        /**< Valid bits mask */
+/* @} */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+#define UART_RXWM_DISABLE            0x00000000        /**< Disable RX trigger interrupt */
+#define UART_RXWM_MASK               0x0000003F        /**< Valid bits mask */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define UART_MODEMCR_FCM            0x00000010        /**< Flow control mode */
+#define UART_MODEMCR_RTS            0x00000002        /**< Request to send */
+#define UART_MODEMCR_DTR            0x00000001        /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define UART_MODEMSR_FCMS           0x00000100        /**< Flow control mode (FCMS) */
+#define UART_MODEMSR_DCD            0x00000080        /**< Complement of DCD input */
+#define UART_MODEMSR_RI             0x00000040        /**< Complement of RI input */
+#define UART_MODEMSR_DSR            0x00000020        /**< Complement of DSR input */
+#define UART_MODEMSR_CTS            0x00000010        /**< Complement of CTS input */
+#define UART_MEDEMSR_DCDX           0x00000008        /**< Delta DCD indicator */
+#define UART_MEDEMSR_RIX            0x00000004        /**< Change of RI */
+#define UART_MEDEMSR_DSRX           0x00000002        /**< Change of DSR */
+#define UART_MEDEMSR_CTSX           0x00000001        /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define UART_SR_FLOWDEL             0x00001000        /**< RX FIFO fill over flow delay */
+#define UART_SR_TACTIVE             0x00000800        /**< TX active */
+#define UART_SR_RACTIVE             0x00000400        /**< RX active */
+#define UART_SR_DMS                 0x00000200        /**< Delta modem status change */
+#define UART_SR_TOUT                0x00000100        /**< RX timeout */
+#define UART_SR_PARITY              0x00000080        /**< RX parity error */
+#define UART_SR_FRAME               0x00000040        /**< RX frame error */
+#define UART_SR_OVER                0x00000020        /**< RX overflow error */
+#define UART_SR_TXFULL              0x00000010        /**< TX FIFO full */
+#define UART_SR_TXEMPTY             0x00000008        /**< TX FIFO empty */
+#define UART_SR_RXFULL              0x00000004        /**< RX FIFO full */
+#define UART_SR_RXEMPTY             0x00000002        /**< RX FIFO empty */
+#define UART_SR_RXOVR               0x00000001        /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define UART_FLOWDEL_MASK           UART_RXWM_MASK    /**< Valid bit mask */
+/* @} */
+
+
+/** @name Base Address of UART0
+ *
+ * The base address of UART0
+ */
+#define UART0_BASE                  0xE0000000
+
+/** @name Base Address of UART1
+ *
+ * The base address of UART1
+ */
+#define UART1_BASE                  0xE0001000
+
+
+#define UART0                       ((UART_Registers*)UART0_BASE)
+#define UART1                       ((UART_Registers*)UART1_BASE)
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param    BaseAddress contains the base address of the device.
+*
+* @return    TRUE if there is receive data, FALSE otherwise.
+*
+* @note        C-Style signature:
+*        uint32_t UartDataReceived(uint32_t BaseAddress)
+*
+******************************************************************************/
+#define UartDataReceived(BaseAddress)            \
+    !((io_in32((BaseAddress) + UART_SR_OFFSET) & \
+    UART_SR_RXEMPTY) == UART_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param    BaseAddress contains the base address of the device.
+*
+* @return    TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*        FIFO.
+*
+* @note        C-Style signature:
+*        uint32_t UartTXFIFOFull(uint32_t BaseAddress)
+*
+******************************************************************************/
+#define UartTXFIFOFull(BaseAddress)             \
+    ((io_in32((BaseAddress) + UART_SR_OFFSET) & \
+     UART_SR_TXFULL) == UART_SR_TXFULL)
+
+#endif
+
diff --git a/bsp/zynq7000/drivers/zynq7000.h b/bsp/zynq7000/drivers/zynq7000.h
new file mode 100644
index 0000000000..fb3d349b04
--- /dev/null
+++ b/bsp/zynq7000/drivers/zynq7000.h
@@ -0,0 +1,59 @@
+#ifndef __AM33XX_H__
+#define __AM33XX_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "armv7.h"
+
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+#define __REG16(x)  (*((volatile unsigned short *)(x)))
+
+#define Zynq7000_UART0_BASE              0xE0000000
+#define Zynq7000_UART1_BASE              0xE0001000
+
+#define Zynq7000_SLCR_BASE               0xF8000000
+#define Zynq7000_SLCR_LOCK               0x004
+#define Zynq7000_SLCR_UNLOCK             0x008
+#define Zynq7000_SLCR_APER_CLK_CTRL      0x12C
+#define Zynq7000_SLCR_UART_CLK_CTRL      0x154
+#define Zynq7000_SLCR_UART_RST_CTRL      0x228
+#define Zynq7000_SLCR_MIO_LOOPBACK       0x804
+#define Zynq7000_SLCR_MIO_MST_TRI0       0x80C
+#define Zynq7000_SLCR_MIO_MST_TRI1       0x810
+
+#define Zynq7000_SCTL_BASE               0xF8F00000  /* System Controller */
+#define Zynq7000_TIMER_GLOBAL_BASE       0xF8F00200  /* Global 64bit timer */
+
+#define Zynq7000_GIC_CPU_BASE            0xF8F00100  /* Generic interrupt controller CPU interface */
+#define Zynq7000_GIC_DIST_BASE           0xF8F01000  /* Generic interrupt controller distributor */
+
+/* zynq on-board gic irq sources */
+#define IRQ_Zynq7000_GTIMER      27
+#define IRQ_Zynq7000_PTIMER      29
+#define IRQ_Zynq7000_AWDT        30
+#define IRQ_Zynq7000_UART0       59
+#define IRQ_Zynq7000_UART1       82
+#define IRQ_Zynq7000_MAXNR       94
+
+#define ARM_GIC_NR_IRQS     IRQ_Zynq7000_MAXNR
+/* only one GIC available */
+#define ARM_GIC_MAX_NR      1
+
+#endif
diff --git a/bsp/zynq7000/rtconfig.h b/bsp/zynq7000/rtconfig.h
new file mode 100644
index 0000000000..bc015321d0
--- /dev/null
+++ b/bsp/zynq7000/rtconfig.h
@@ -0,0 +1,143 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX	6
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE	4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX	32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
+#define RT_TICK_PER_SECOND	1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE	512
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+// #define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO	4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE	512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND	10
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+// #define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
+// #define RT_USING_MEMHEAP_AS_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    64
+// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
+#define RT_USING_INTERRUPT_INFO
+// </section>
+
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME	"uart0"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
+#define FINSH_USING_MSH
+// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
+#define FINSH_USING_MSH_DEFAULT
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE	4096
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
+#define RT_USING_NEWLIB
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+// #define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+// #define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX	2
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX	4
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN1">1</item>
+// <item description="LFN1">2</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN	1
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN	64
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+// #define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
+// #define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
+#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+// </section>
+// </RDTConfigurator>
+
+
+#endif
diff --git a/bsp/zynq7000/rtconfig.py b/bsp/zynq7000/rtconfig.py
new file mode 100644
index 0000000000..45889fb7a5
--- /dev/null
+++ b/bsp/zynq7000/rtconfig.py
@@ -0,0 +1,84 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='zynq7000'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    EXEC_PATH 	= '/home/grissiom/'
+elif CROSS_TOOL == 'keil':
+    PLATFORM 	= 'armcc'
+    EXEC_PATH 	= 'C:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support IAR yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    #ARCH    = -mcpu=cortex-a9 -mfpu=vfpv3 
+    DEVICE = ' -Wall -mcpu=cortex-a9 -mfpu=vfpv3 -ftree-vectorize -ffast-math -mfloat-abi=softfp'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LINK_SCRIPT = 'zynq7000.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=zynq7000.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+            SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMP'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-zynq7000.map --scatter zynq7000.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
diff --git a/bsp/zynq7000/zynq7000.ld b/bsp/zynq7000/zynq7000.ld
new file mode 100644
index 0000000000..ae9b8ea38d
--- /dev/null
+++ b/bsp/zynq7000/zynq7000.ld
@@ -0,0 +1,116 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+    . = 0x1ff00000;
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        /* make the ISRs close to vectors may be more cache-friendly */
+        *(.text.isr)
+
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    __data_start = .;
+    . = ALIGN(4);
+    .data :
+    {
+        KEEP(*(.resource_table))
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(4);
+    __bss_start = __data_end;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}
diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript
new file mode 100644
index 0000000000..2ad51b573e
--- /dev/null
+++ b/libcpu/arm/zynq7000/SConscript
@@ -0,0 +1,17 @@
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'iar':
+        src += Glob('*_iar.S')
+elif rtconfig.PLATFORM == 'gcc':
+        src += Glob('*_gcc.S')
+elif rtconfig.PLATFORM == 'armcc':
+        src += Glob('*_rvds.S')
+
+group = DefineGroup('AM1808', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/zynq7000/armv7.h b/libcpu/arm/zynq7000/armv7.h
new file mode 100644
index 0000000000..65f6c27860
--- /dev/null
+++ b/libcpu/arm/zynq7000/armv7.h
@@ -0,0 +1,65 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+void rt_hw_mmu_init(void);
+
+#endif
diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S
new file mode 100644
index 0000000000..3dbf3c861d
--- /dev/null
+++ b/libcpu/arm/zynq7000/context_gcc.S
@@ -0,0 +1,102 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#define NOINT           0xc0
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    orr r1, r0, #NOINT
+    msr cpsr_c, r1
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    beq _ARM_MODE
+    orr r4, r4, #0x20       @ it's thumb code
+
+_ARM_MODE:
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    bic r4, r4, #0x20       @ must be ARM mode
+    msr cpsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r3, [r2]
+    ldr r2, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    str r0, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h
new file mode 100644
index 0000000000..bd6a23f1b2
--- /dev/null
+++ b/libcpu/arm/zynq7000/cp15.h
@@ -0,0 +1,31 @@
+#ifndef __CP15_H__
+#define __CP15_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif
diff --git a/libcpu/arm/zynq7000/cp15_gcc.S b/libcpu/arm/zynq7000/cp15_gcc.S
new file mode 100644
index 0000000000..f1ed6492aa
--- /dev/null
+++ b/libcpu/arm/zynq7000/cp15_gcc.S
@@ -0,0 +1,140 @@
+/*
+ * File      : cp15_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * http://www.rt-thread.org
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr
diff --git a/libcpu/arm/zynq7000/cpu.c b/libcpu/arm/zynq7000/cpu.c
new file mode 100644
index 0000000000..9853effe3c
--- /dev/null
+++ b/libcpu/arm/zynq7000/cpu.c
@@ -0,0 +1,45 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "zynq7000.h"
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+    while (1);  /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
new file mode 100644
index 0000000000..498446db43
--- /dev/null
+++ b/libcpu/arm/zynq7000/gic.c
@@ -0,0 +1,239 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#include <board.h>
+
+#include "gic.h"
+#include "cp15.h"
+
+struct arm_gic
+{
+    rt_uint32_t offset;
+
+    rt_uint32_t dist_hw_base;
+    rt_uint32_t cpu_hw_base;
+};
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)               __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + (n/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + (n/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + (n/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280)
+#define GIC_DIST_ACTIVE_BIT(hw_base)        __REG32((hw_base) + 0x300)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  (n/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  (n/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + (n/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + (n/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS)
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+
+    /* Set the FIQEn bit, signal FIQ for IGROUP0. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq)
+{
+    unsigned int reg;
+
+    RT_ASSERT(irq <= 15);
+    RT_ASSERT(target_cpu <= 255);
+
+    reg = (target_cpu << 16) | irq;
+    GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg;
+}
+
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq)
+{
+    RT_ASSERT(irq <= 15);
+    RT_ASSERT(target_cpu <= 255);
+
+    GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4);
+}
diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h
new file mode 100644
index 0000000000..4b89538948
--- /dev/null
+++ b/libcpu/arm/zynq7000/gic.h
@@ -0,0 +1,41 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq);
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+
+#endif
+
diff --git a/libcpu/arm/zynq7000/interrupt.c b/libcpu/arm/zynq7000/interrupt.c
new file mode 100644
index 0000000000..ce3fbc8dfb
--- /dev/null
+++ b/libcpu/arm/zynq7000/interrupt.c
@@ -0,0 +1,143 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "zynq7000.h"
+#include "cp15.h"
+#include "gic.h"
+
+#define MAX_HANDLERS                IRQ_Zynq7000_MAXNR
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+static void rt_hw_interrupt_handle(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+const unsigned int VECTOR_BASE = 0x00;
+extern int system_vectors;
+
+static void rt_hw_vector_init(void)
+{
+    int sctrl;
+    unsigned int *src = (unsigned int *)&system_vectors;
+
+    /* C12-C0 is only active when SCTLR.V = 0 */
+    asm volatile ("mrc p15, #0, %0, c1, c0, #0"
+                  :"=r" (sctrl));
+    sctrl &= ~(1 << 13);
+    asm volatile ("mcr p15, #0, %0, c1, c0, #0"
+                  :
+                  :"r" (sctrl));
+
+    asm volatile ("mcr p15, #0, %0, c12, c0, #0"
+                  :
+                  :"r" (src));
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    register rt_uint32_t idx;
+
+    /* set vector table */
+    rt_hw_vector_init();
+
+    /* init exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+    for (idx = 0; idx < MAX_HANDLERS; idx++)
+    {
+        isr_table[idx].handler = rt_hw_interrupt_handle;
+    }
+
+    /* initialize ARM GIC */
+    arm_gic_dist_init(0, Zynq7000_GIC_DIST_BASE, 0);
+    arm_gic_cpu_init(0, Zynq7000_GIC_CPU_BASE);
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+        /* set the interrupt to this cpu */
+        arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
+    }
+
+    return old_handler;
+}
+
+void rt_hw_interrupt_clear(int vector)
+{
+    /* SGI will be cleared automatically. */
+    if (vector < 16)
+        return;
+}
diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h
new file mode 100644
index 0000000000..07eafc84e5
--- /dev/null
+++ b/libcpu/arm/zynq7000/interrupt.h
@@ -0,0 +1,26 @@
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+void rt_hw_interrupt_clear(int vector);
+
+#endif /* end of include guard: __INTERRUPT_H__ */
+
diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c
new file mode 100644
index 0000000000..2a58fabe4f
--- /dev/null
+++ b/libcpu/arm/zynq7000/mmu.c
@@ -0,0 +1,182 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  //eXecute Never
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write, device type */
+#define RW_NCB         (AP_RW|DOMAIN0|NCB|DESC_SEC)
+/* Read/Write strongly ordered type */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+/* MMUTable is the name used by codes of Xilinx */
+volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_mmu_init(void)
+{
+    extern rt_uint32_t __text_start;
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /* set page table */
+    /* no access to the memory below .text */
+    /* 128M cached DDR memory */
+    rt_hw_mmu_setmtt((rt_uint32_t)&__text_start, 0x20000000-1,
+                     0x1ff00000, RW_CB);
+    /* PL region */
+    rt_hw_mmu_setmtt(0x40000000, 0xBFFFFFFF, 0x40000000, RW_NCNBXN);
+    /* IOP registers */
+    rt_hw_mmu_setmtt(0xE0000000, 0xE02FFFFF, 0xE0000000, RW_NCNBXN);
+    /* no access to the SMC memory(enable it if you want) */
+    /* SLCR, PS and CPU private registers, note we map more memory space as the
+     * entry is 1MB in size. */
+    rt_hw_mmu_setmtt(0xF8000000, 0xF8FFFFFF, 0xF8000000, RW_NCNBXN);
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+
+    /* become clients for all domains */
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
diff --git a/libcpu/arm/zynq7000/stack.c b/libcpu/arm/zynq7000/stack.c
new file mode 100644
index 0000000000..8e1b86432e
--- /dev/null
+++ b/libcpu/arm/zynq7000/stack.c
@@ -0,0 +1,60 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ * 2013-07-15     Bernard      add Cortex-A8 support.
+ */
+#include <rtthread.h>
+#include "zynq7000.h"
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stk      = (rt_uint32_t *)stack_addr;
+    *(stk)   = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0;                           /* r12 */
+    *(--stk) = 0;                           /* r11 */
+    *(--stk) = 0;                           /* r10 */
+    *(--stk) = 0;                           /* r9 */
+    *(--stk) = 0;                           /* r8 */
+    *(--stk) = 0;                           /* r7 */
+    *(--stk) = 0;                           /* r6 */
+    *(--stk) = 0;                           /* r5 */
+    *(--stk) = 0;                           /* r4 */
+    *(--stk) = 0;                           /* r3 */
+    *(--stk) = 0;                           /* r2 */
+    *(--stk) = 0;                           /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S
new file mode 100644
index 0000000000..41a7906b00
--- /dev/null
+++ b/libcpu/arm/zynq7000/start_gcc.S
@@ -0,0 +1,254 @@
+/*
+ * File      : start_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,  0x00000000
+.equ SVC_Stack_Size,  0x00000000
+.equ ABT_Stack_Size,  0x00000000
+.equ FIQ_Stack_Size,  0x00000100
+.equ IRQ_Stack_Size,  0x00000100
+.equ USR_Stack_Size,  0x00000000
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 FIQ_Stack_Size + IRQ_Stack_Size)
+
+/* stack */
+.globl stack_start
+.globl stack_top
+
+.bss
+stack_start:
+.rept ISR_Stack_Size
+.long 0
+.endr
+stack_top:
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+	/* invalidate SCU */
+	ldr	r7, =0xF8F0000C
+	ldr	r6, =0xFFFF
+	str	r6, [r7]
+
+	/* disable MMU */
+	mrc	p15, 0, r0, c1, c0, 0		/* read CP15 register 1 */
+	bic	r0, r0, #0x1				/* clear bit 0 */
+	mcr	p15, 0, r0, c1, c0, 0		/* write value back */
+
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+
+    /* setup stack */
+    bl      stack_setup
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* call C++ constructors of global objects                          */
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
+
+ctor_loop:
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
+ctor_end:
+
+    /* start RT-Thread Kernel       */
+    ldr     pc, _rtthread_startup
+
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+    ldr     r0, =stack_top
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #FIQ_Stack_Size
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #IRQ_Stack_Size
+
+    @  Switch back to SVC
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+
+    bx      lr
+
+.section .text.isr, "ax"
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc,lr,#4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+    .align  5
+.globl vector_irq
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc, lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r7,  [r6]
+    ldr     sp,  [r7]       @ get new task's stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl	vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl	vector_undef
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_undef
+    b       .
+
+    .align  5
+    .globl	vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl	vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl	vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c
new file mode 100644
index 0000000000..9bf58f916c
--- /dev/null
+++ b/libcpu/arm/zynq7000/trap.c
@@ -0,0 +1,185 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "zynq7000.h"
+#include "gic.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register (struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK					0x000003ff
+
+void rt_hw_trap_irq()
+{
+    void *param;
+    unsigned long ir;
+    unsigned long fullir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    fullir = arm_gic_get_active_irq(0);
+    ir = fullir & GIC_ACK_INTID_MASK;
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    if (isr_func)
+    {
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    arm_gic_ack(0, fullir);
+}
+
+void rt_hw_trap_fiq()
+{
+    void *param;
+    unsigned long ir;
+    unsigned long fullir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    fullir = arm_gic_get_active_irq(0);
+    ir = fullir & GIC_ACK_INTID_MASK;
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    param = isr_table[ir].param;
+
+    /* turn to interrupt service routine */
+    isr_func(ir, param);
+
+    /* end of interrupt */
+    arm_gic_ack(0, fullir);
+}
+
diff --git a/libcpu/arm/zynq7000/vector_gcc.S b/libcpu/arm/zynq7000/vector_gcc.S
new file mode 100644
index 0000000000..4a44a7395c
--- /dev/null
+++ b/libcpu/arm/zynq7000/vector_gcc.S
@@ -0,0 +1,65 @@
+/*
+ * File      : vector_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl 	16,0xdeadbeef

From b0c94dc4d9dd14d04239312500ada9baecb4701f Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Fri, 27 Jun 2014 14:49:51 +0800
Subject: [PATCH 17/86] [lwIP] Fix the usage issue of NETIF_LINK_CALLBACK.

---
 components/net/lwip-1.4.1/src/arch/sys_arch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/net/lwip-1.4.1/src/arch/sys_arch.c b/components/net/lwip-1.4.1/src/arch/sys_arch.c
index ee1d952410..356dc101cf 100644
--- a/components/net/lwip-1.4.1/src/arch/sys_arch.c
+++ b/components/net/lwip-1.4.1/src/arch/sys_arch.c
@@ -108,7 +108,7 @@ static void tcpip_init_done_callback(void *arg)
                 netif_set_up(ethif->netif);
             }
 
-#ifdef LWIP_NETIF_LINK_CALLBACK
+#if LWIP_NETIF_LINK_CALLBACK
             netif_set_link_up(ethif->netif);
 #endif
 

From 8f7ec645fd888d8c1547e7b59b793985ed218606 Mon Sep 17 00:00:00 2001
From: geniusgogo <xeonrun@gmail.com>
Date: Sun, 29 Jun 2014 00:34:20 +0800
Subject: [PATCH 18/86] add Freescale k64F bsp. FRDM-K64 based

---
 bsp/k64Fxxxx/K64FN1M0xxx12.ld                 |   164 +
 bsp/k64Fxxxx/MK64F.sct                        |    14 +
 bsp/k64Fxxxx/SConscript                       |    14 +
 bsp/k64Fxxxx/SConstruct                       |    37 +
 bsp/k64Fxxxx/applications/SConscript          |    11 +
 bsp/k64Fxxxx/applications/application.c       |   118 +
 bsp/k64Fxxxx/applications/startup.c           |   123 +
 bsp/k64Fxxxx/board/SConscript                 |    12 +
 bsp/k64Fxxxx/board/board.c                    |    88 +
 bsp/k64Fxxxx/board/board.h                    |    58 +
 bsp/k64Fxxxx/board/drv_uart.c                 |   269 +
 bsp/k64Fxxxx/board/drv_uart.h                 |    31 +
 bsp/k64Fxxxx/board/led.c                      |    74 +
 bsp/k64Fxxxx/board/led.h                      |    33 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12.h         | 13416 +++++++++++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h     |  2578 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h    | 14135 ++++++++++++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h    |  1078 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h     |  3963 +++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h     |  1463 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h     |  1018 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h     |  1194 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h     |  1499 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h     |   879 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h     |  5973 +++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h  |   220 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h    |  8441 +++++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h     |   430 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h      |   959 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h     |  2177 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h    |  2500 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h     |  6616 ++++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h    |   500 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h     |  1902 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h     |  3463 ++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h    |  2252 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h   |   629 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h     |  1939 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h     |  1164 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h     |  1923 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h      |   958 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h     |   302 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h     |  1433 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h     |   517 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h     |   577 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h    |   957 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h     |   730 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h   |   210 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h  |   210 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h     |   590 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h     |  1828 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h    |  5761 +++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h     |  4553 +++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h     |   566 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h     |  2445 +++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h    |  4933 ++++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h     |  4276 +++++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h  |   957 ++
 bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h    |   369 +
 bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h    |  1244 ++
 bsp/k64Fxxxx/device/MK64F12/regs.h            |   525 +
 bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c  |   422 +
 bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h  |    92 +
 bsp/k64Fxxxx/device/SConscript                |    24 +
 .../TOOLCHAIN_ARM_STD/startup_MK64F12.s       |   732 +
 .../TOOLCHAIN_GCC_ARM/startup_MK64F12.S       |   369 +
 bsp/k64Fxxxx/device/core_cm4.h                |  1772 ++
 bsp/k64Fxxxx/device/core_cm4_simd.h           |   673 +
 bsp/k64Fxxxx/device/core_cmFunc.h             |   636 +
 bsp/k64Fxxxx/device/core_cmInstr.h            |   688 +
 bsp/k64Fxxxx/device/fsl_device_registers.h    |   572 +
 bsp/k64Fxxxx/project.uvproj                   |   720 +
 bsp/k64Fxxxx/rtconfig.h                       |   156 +
 bsp/k64Fxxxx/rtconfig.py                      |    82 +
 bsp/k64Fxxxx/template.uvproj                  |   400 +
 75 files changed, 124636 insertions(+)
 create mode 100644 bsp/k64Fxxxx/K64FN1M0xxx12.ld
 create mode 100644 bsp/k64Fxxxx/MK64F.sct
 create mode 100644 bsp/k64Fxxxx/SConscript
 create mode 100644 bsp/k64Fxxxx/SConstruct
 create mode 100644 bsp/k64Fxxxx/applications/SConscript
 create mode 100644 bsp/k64Fxxxx/applications/application.c
 create mode 100644 bsp/k64Fxxxx/applications/startup.c
 create mode 100644 bsp/k64Fxxxx/board/SConscript
 create mode 100644 bsp/k64Fxxxx/board/board.c
 create mode 100644 bsp/k64Fxxxx/board/board.h
 create mode 100644 bsp/k64Fxxxx/board/drv_uart.c
 create mode 100644 bsp/k64Fxxxx/board/drv_uart.h
 create mode 100644 bsp/k64Fxxxx/board/led.c
 create mode 100644 bsp/k64Fxxxx/board/led.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/regs.h
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c
 create mode 100644 bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h
 create mode 100644 bsp/k64Fxxxx/device/SConscript
 create mode 100644 bsp/k64Fxxxx/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s
 create mode 100644 bsp/k64Fxxxx/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
 create mode 100644 bsp/k64Fxxxx/device/core_cm4.h
 create mode 100644 bsp/k64Fxxxx/device/core_cm4_simd.h
 create mode 100644 bsp/k64Fxxxx/device/core_cmFunc.h
 create mode 100644 bsp/k64Fxxxx/device/core_cmInstr.h
 create mode 100644 bsp/k64Fxxxx/device/fsl_device_registers.h
 create mode 100644 bsp/k64Fxxxx/project.uvproj
 create mode 100644 bsp/k64Fxxxx/rtconfig.h
 create mode 100644 bsp/k64Fxxxx/rtconfig.py
 create mode 100644 bsp/k64Fxxxx/template.uvproj

diff --git a/bsp/k64Fxxxx/K64FN1M0xxx12.ld b/bsp/k64Fxxxx/K64FN1M0xxx12.ld
new file mode 100644
index 0000000000..5bf14b145e
--- /dev/null
+++ b/bsp/k64Fxxxx/K64FN1M0xxx12.ld
@@ -0,0 +1,164 @@
+/*
+ * K64F ARM GCC linker script file
+ */
+
+MEMORY
+{
+  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  FLASH (rx)            : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410
+  RAM (rwx)             : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .isr_vector :
+    {
+        __vector_table = .;
+        KEEP(*(.vector_table))
+        *(.text.Reset_Handler)
+        *(.text.System_Init)
+         . = ALIGN(4);
+    } > VECTORS
+
+    .flash_protect :
+    {
+        KEEP(*(.kinetis_flash_config_field))
+         . = ALIGN(4);
+    } > FLASH_PROTECTION
+
+    .text :
+    {
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/bsp/k64Fxxxx/MK64F.sct b/bsp/k64Fxxxx/MK64F.sct
new file mode 100644
index 0000000000..1aafaed200
--- /dev/null
+++ b/bsp/k64Fxxxx/MK64F.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x100000  {    ; load region size_region (1000k)
+  ER_IROM1 0x00000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(62 vect * 4 bytes) =  8_byte_aligned(0x194) = 0x198
+  ; 0x40000 - 0x198 = 0x3FE68
+  RW_IRAM1 0x1FFF0198 0x3FE68 {
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/k64Fxxxx/SConscript b/bsp/k64Fxxxx/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/k64Fxxxx/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/k64Fxxxx/SConstruct b/bsp/k64Fxxxx/SConstruct
new file mode 100644
index 0000000000..d4132b593c
--- /dev/null
+++ b/bsp/k64Fxxxx/SConstruct
@@ -0,0 +1,37 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-k64f.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# build program 
+env.Program(TARGET, objs)
+
+# end building 
+EndBuilding(TARGET)
diff --git a/bsp/k64Fxxxx/applications/SConscript b/bsp/k64Fxxxx/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/k64Fxxxx/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/k64Fxxxx/applications/application.c b/bsp/k64Fxxxx/applications/application.c
new file mode 100644
index 0000000000..f311c9a77c
--- /dev/null
+++ b/bsp/k64Fxxxx/applications/application.c
@@ -0,0 +1,118 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ *
+ */
+
+/**
+ * @addtogroup k64
+ */
+/*@{*/
+
+#include <stdio.h>
+
+#include "MK64F12.h"
+#include <board.h>
+#include <rtthread.h>
+
+#include "led.h"
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#include <lwip/api.h>
+#include <netif/ethernetif.h>
+#include "stm32_eth.h"
+#endif
+
+void rt_init_thread_entry(void* parameter)
+{
+    /* LwIP Initialization */
+#ifdef RT_USING_LWIP
+    {
+        extern void lwip_sys_init(void);
+
+        /* register ethernetif device */
+        eth_system_device_init();
+
+        rt_hw_stm32_eth_init();
+        /* re-init device driver */
+        rt_device_init_all();
+
+        /* init lwip system */
+        lwip_sys_init();
+        rt_kprintf("TCP/IP initialized!\n");
+    }
+#endif
+
+//FS
+
+//GUI
+}
+
+float f_var1;
+float f_var2;
+float f_var3;
+float f_var4;
+
+ALIGN(RT_ALIGN_SIZE)
+static char thread_led1_stack[1024];
+struct rt_thread thread_led1;
+static void rt_thread_entry_led1(void* parameter)
+{
+    int n = 0;
+    rt_hw_led_init();
+
+    while (1)
+    {
+        //rt_kprintf("LED\t%d\tis shining\r\n",n);
+
+        rt_hw_led_on(n);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+        rt_hw_led_off(n);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+
+        n++;
+
+        if (n == LED_MAX)
+            n = 0;
+    }
+}
+
+int rt_application_init()
+{
+    rt_thread_t init_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, 8, 20);
+#else
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, 80, 20);
+#endif
+
+    if (init_thread != RT_NULL)
+        rt_thread_startup(init_thread);
+
+    //------- init led1 thread
+    rt_thread_init(&thread_led1,
+                   "led_demo",
+                   rt_thread_entry_led1,
+                   RT_NULL,
+                   &thread_led1_stack[0],
+                   sizeof(thread_led1_stack),11,5);
+    rt_thread_startup(&thread_led1);
+
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/k64Fxxxx/applications/startup.c b/bsp/k64Fxxxx/applications/startup.c
new file mode 100644
index 0000000000..b8edf49cf5
--- /dev/null
+++ b/bsp/k64Fxxxx/applications/startup.c
@@ -0,0 +1,123 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <MK64F12.H>
+#include <board.h>
+
+/**
+ * @addtogroup k64
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define K64_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define K64_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define K64_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(rt_uint8_t* file, rt_uint32_t line)
+{
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
+
+    while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init tick */
+    rt_system_tick_init();
+
+    /* init kernel object */
+    rt_system_object_init();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+    rt_system_heap_init((void*)K64_SRAM_BEGIN, (void*)K64_SRAM_END);
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init all device */
+    rt_device_init_all();
+
+    /* init application */
+    rt_application_init();
+
+#ifdef RT_USING_FINSH
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device( FINSH_DEVICE_NAME );
+#endif
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/k64Fxxxx/board/SConscript b/bsp/k64Fxxxx/board/SConscript
new file mode 100644
index 0000000000..f694ada865
--- /dev/null
+++ b/bsp/k64Fxxxx/board/SConscript
@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'board')
+src	= Glob('*.c')
+src	+= Glob('*.s')
+CPPPATH = [cwd]
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/k64Fxxxx/board/board.c b/bsp/k64Fxxxx/board/board.c
new file mode 100644
index 0000000000..05f57e35e2
--- /dev/null
+++ b/bsp/k64Fxxxx/board/board.c
@@ -0,0 +1,88 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <MK64F12.H>
+#include "board.h"
+
+#include "drv_uart.h"
+
+
+/**
+ * @addtogroup K60
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    SystemCoreClockUpdate();              /* Update Core Clock Frequency        */
+    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); /* Generate interrupt each 1 ms       */
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial Tower board.
+ */
+void rt_hw_board_init()
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+    rt_hw_uart_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(CONSOLE_DEVICE);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/k64Fxxxx/board/board.h b/bsp/k64Fxxxx/board/board.h
new file mode 100644
index 0000000000..a624177887
--- /dev/null
+++ b/bsp/k64Fxxxx/board/board.h
@@ -0,0 +1,58 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ *
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <MK64F12.H>
+
+
+/* board configuration */
+
+// <o> Internal SRAM memory size[Kbytes] <8-64>
+// <i>Default: 64
+#define K64_SRAM_SIZE         256
+#define K64_SRAM_END          (0x1FFF0000 + (K64_SRAM_SIZE * 1024))
+
+//#define RT_USING_UART1
+#define RT_USING_UART5
+//#define RT_USING_UART3
+
+// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
+// <i>Default: 1
+#define K64_CONSOLE_USART        0
+
+void rt_hw_board_init(void);
+
+#if K64_CONSOLE_USART == 0
+#define CONSOLE_DEVICE "uart0"
+#elif K64_CONSOLE_USART == 1
+#define CONSOLE_DEVICE "uart1"
+#elif K64_CONSOLE_USART == 2
+#define CONSOLE_DEVICE "uart2"
+#elif K64_CONSOLE_USART == 3
+#define CONSOLE_DEVICE "uart3"
+#elif K64_CONSOLE_USART == 4
+#define CONSOLE_DEVICE "uart4"
+#elif K64_CONSOLE_USART == 5
+#define CONSOLE_DEVICE "uart5"
+#endif
+
+#define FINSH_DEVICE_NAME   CONSOLE_DEVICE
+
+
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>
diff --git a/bsp/k64Fxxxx/board/drv_uart.c b/bsp/k64Fxxxx/board/drv_uart.c
new file mode 100644
index 0000000000..7813b21ad7
--- /dev/null
+++ b/bsp/k64Fxxxx/board/drv_uart.c
@@ -0,0 +1,269 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ *
+ */
+
+
+#include "drv_uart.h"
+
+static struct rt_serial_device _k64_serial;  //abstracted serial for RTT
+static struct serial_ringbuffer _k64_int_rx; //UART send buffer area
+
+struct k64_serial_device
+{
+    /* UART base address */
+    UART_Type *baseAddress;
+
+    /* UART IRQ Number */
+    int irq_num;
+
+    /* device config */
+    struct serial_configure config;
+};
+
+//hardware abstract device
+static struct k64_serial_device _k64_node =
+{
+    (UART_Type *)UART0,
+    UART0_RX_TX_IRQn,
+};
+
+static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2 = 0,reg_BRFA=0;
+    unsigned int cal_SBR = 0;
+    UART_Type *uart_reg;
+
+    /* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
+     * calculate baud_rate
+     */
+    uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
+
+    /*
+     * set bit order
+     */
+    if (cfg->bit_order == BIT_ORDER_LSB)
+        reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
+    else if (cfg->bit_order == BIT_ORDER_MSB)
+        reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
+
+    /*
+     * set data_bits
+     */
+    if (cfg->data_bits == DATA_BITS_8)
+        reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
+    else if (cfg->data_bits == DATA_BITS_9)
+        reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
+
+    /*
+     * set parity
+     */
+    if (cfg->parity == PARITY_NONE)
+    {
+        reg_C1 &= ~(UART_C1_PE_MASK);
+    }
+    else
+    {
+        /* first ,set parity enable bit */
+        reg_C1 |= (UART_C1_PE_MASK);
+
+        /* second ,determine parity odd or even*/
+        if (cfg->parity == PARITY_ODD)
+            reg_C1 |= UART_C1_PT_MASK;
+        if (cfg->parity == PARITY_EVEN)
+            reg_C1 &= ~(UART_C1_PT_MASK);
+    }
+
+    /*
+     * set NZR mode
+     * not tested
+     */
+    if (cfg->invert != NRZ_NORMAL)
+    {
+        /* not in normal mode ,set inverted polarity */
+        reg_C3 |= UART_C3_TXINV_MASK;
+    }
+
+    switch ((unsigned int)uart_reg)
+    {
+    /*
+     * if you're using other board
+     * set clock and pin map for UARTx
+     */
+    case UART0_BASE:
+            /* calc SBR */
+        cal_SBR = SystemCoreClock / (16 * cfg->baud_rate);
+
+        /* check to see if sbr is out of range of register bits */
+        if ((cal_SBR > 0x1FFF) || (cal_SBR < 1))
+        {
+            /* unsupported baud rate for given source clock input*/
+            return -RT_ERROR;
+        }
+
+        /* calc baud_rate */
+        reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
+        reg_BDL = cal_SBR & 0x00FF;
+
+        /* fractional divider */
+        reg_BRFA = ((SystemCoreClock * 32) / (cfg->baud_rate * 16)) - (cal_SBR * 32);
+
+        reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
+
+        SIM_SOPT5 &= ~ SIM_SOPT5_UART0RXSRC(0);
+        SIM_SOPT5 |= SIM_SOPT5_UART0RXSRC(0);
+        SIM_SOPT5 &= ~ SIM_SOPT5_UART0TXSRC(0);
+        SIM_SOPT5 |= SIM_SOPT5_UART0TXSRC(0);
+
+        // set UART0 clock
+        // Enable UART gate clocking
+        // Enable PORTE gate clocking
+        SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
+        SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
+
+        // set UART0 pin
+        PORTB->PCR[16] &= ~(3UL <<  8);
+        PORTB->PCR[16] |= (3UL <<  8);      // Pin mux configured as ALT3
+
+        PORTB->PCR[17] &= ~(3UL <<  8);
+        PORTB->PCR[17] |= (3UL <<  8);      // Pin mux configured as ALT3
+        break;
+
+    default:
+        return -RT_ERROR;
+    }
+
+    uart_reg->BDH = reg_BDH;
+    uart_reg->BDL = reg_BDL;
+    uart_reg->C1 = reg_C1;
+    uart_reg->C4 = reg_C4;
+    uart_reg->S2 = reg_S2;
+
+    uart_reg->S2  =  0;
+    uart_reg->C3  =  0;
+
+    uart_reg->RWFIFO = UART_RWFIFO_RXWATER(1);
+    uart_reg->TWFIFO = UART_TWFIFO_TXWATER(0);
+
+    uart_reg->C2  =  UART_C2_RE_MASK |    //Receiver enable
+                     UART_C2_TE_MASK;     //Transmitter enable
+
+    return RT_EOK;
+}
+
+static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    UART_Type *uart_reg;
+    int uart_irq_num = 0;
+
+    uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
+    uart_irq_num = ((struct k64_serial_device *)serial->parent.user_data)->irq_num;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        uart_reg->C2 &= ~UART_C2_RIE_MASK;
+        //disable NVIC
+        NVIC->ICER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        uart_reg->C2 |= UART_C2_RIE_MASK;
+        //enable NVIC,we are sure uart's NVIC vector is in NVICICPR1
+        NVIC->ICPR[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
+        NVIC->ISER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
+        break;
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        uart_reg->C2  &=  ~(UART_C2_RE_MASK |    //Receiver enable
+                            UART_C2_TE_MASK);     //Transmitter enable
+        break;
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        uart_reg->C2  =  UART_C2_RE_MASK |    //Receiver enable
+                         UART_C2_TE_MASK;     //Transmitter enable
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int _putc(struct rt_serial_device *serial, char c)
+{
+    UART_Type *uart_reg;
+    uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
+
+    while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
+    uart_reg->D = (c & 0xFF);
+    return 1;
+}
+
+static int _getc(struct rt_serial_device *serial)
+{
+    UART_Type *uart_reg;
+    uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
+
+    if (uart_reg->S1 & UART_S1_RDRF_MASK)
+        return (uart_reg->D);
+    else
+        return -1;
+}
+
+static const struct rt_uart_ops _k64_ops =
+{
+    _configure,
+    _control,
+    _putc,
+    _getc,
+};
+
+
+void UART0_RX_TX_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_hw_serial_isr((struct rt_serial_device*)&_k64_serial);
+    rt_interrupt_leave();
+}
+
+
+void rt_hw_uart_init(void)
+{
+    struct serial_configure config;
+
+    /* fake configuration */
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    _k64_serial.ops    = &_k64_ops;
+    _k64_serial.int_rx = &_k64_int_rx;
+    _k64_serial.config = config;
+
+    rt_hw_serial_register(&_k64_serial, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          (void*)&_k64_node);
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while(*str != '\0')
+    {
+        if (*str == '\n')
+            _putc(&_k64_serial,'\r');
+        _putc(&_k64_serial,*str);
+        str++;
+    }
+}
diff --git a/bsp/k64Fxxxx/board/drv_uart.h b/bsp/k64Fxxxx/board/drv_uart.h
new file mode 100644
index 0000000000..fca42557fb
--- /dev/null
+++ b/bsp/k64Fxxxx/board/drv_uart.h
@@ -0,0 +1,31 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 
+ */
+
+#ifndef DRV_UART_H
+#define DRV_UART_H
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <MK64F12.H>
+
+#include <drivers/serial.h>
+
+void rt_hw_uart_init(void);
+
+//for kernel debug when console not registered
+void rt_hw_console_output(const char *str);
+
+#endif /* end of include guard: DRV_UART_H */
diff --git a/bsp/k64Fxxxx/board/led.c b/bsp/k64Fxxxx/board/led.c
new file mode 100644
index 0000000000..1a57dcc005
--- /dev/null
+++ b/bsp/k64Fxxxx/board/led.c
@@ -0,0 +1,74 @@
+/*
+ * File      : led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ *
+ */
+
+#include <MK64F12.H>
+#include "led.h"
+
+const rt_uint32_t led_mask[] = {1 << 21, 1 << 22, 1 << 26};
+
+void rt_hw_led_init(void)
+{
+    SIM_SCGC5 |= (1 << SIM_SCGC5_PORTB_SHIFT);
+    SIM_SCGC5 |= (1 << SIM_SCGC5_PORTE_SHIFT);
+
+    PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
+    PORTB->PCR[21] |= PORT_PCR_MUX(1);   //PTB21 is GPIO pin
+
+    PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
+    PORTB->PCR[22] |= PORT_PCR_MUX(1);  //PTB22 is GPIO pin
+
+    PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
+    PORTE->PCR[26] |= PORT_PCR_MUX(1);  //PTE26 is GPIO pin
+
+    /* Switch LEDs off and enable output*/
+    PTB->PDDR |= GPIO_PDDR_PDD(led_mask[1] | led_mask[0]);
+    PTE->PDDR |= GPIO_PDDR_PDD(led_mask[2]);
+
+    rt_hw_led_off(LED_RED);
+    rt_hw_led_off(LED_GREEN);
+    rt_hw_led_off(LED_BLUE);
+}
+
+void rt_hw_led_uninit(void)
+{
+    PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
+
+    PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
+
+    PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
+}
+
+void rt_hw_led_on(rt_uint32_t n)
+{
+    if (n != LED_GREEN)
+    {
+        PTB->PCOR |= led_mask[n];
+    }
+    else
+    {
+        PTE->PCOR |= led_mask[n];
+    }
+}
+
+void rt_hw_led_off(rt_uint32_t n)
+{
+    if (n != LED_GREEN)
+    {
+        PTB->PSOR |= led_mask[n];
+    }
+    else
+    {
+        PTE->PSOR |= led_mask[n];
+    }
+}
diff --git a/bsp/k64Fxxxx/board/led.h b/bsp/k64Fxxxx/board/led.h
new file mode 100644
index 0000000000..ca08d3f266
--- /dev/null
+++ b/bsp/k64Fxxxx/board/led.h
@@ -0,0 +1,33 @@
+/*
+ * File      : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ *
+ */
+
+#ifndef __LED_H__
+#define __LED_H__
+
+#include <rtthread.h>
+
+enum LED_NUM
+{
+    LED_BLUE,
+    LED_RED,
+    LED_GREEN,
+    LED_MAX
+};
+
+void rt_hw_led_init(void);
+void rt_hw_led_uninit(void);
+void rt_hw_led_on(rt_uint32_t n);
+void rt_hw_led_off(rt_uint32_t n);
+
+#endif /* end  of __LED_H__ */
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12.h
new file mode 100644
index 0000000000..016ab5c33c
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12.h
@@ -0,0 +1,13416 @@
+/*
+** ###################################################################
+**     Processor:           MK64FN1M0VMD12
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.1, July 2013
+**     Version:             rev. 2.1, 2013-10-29
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-29)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.1
+ * @date 2013-10-29
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+#if !defined(MK64F12_H_)
+#define MK64F12_H_                               /**< Symbol preventing repeated inclusion */
+
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MCU_MK64F12)  /* Check if memory map has not been already included */
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLW_IRQn                     = 21,               /**< Low Leakage Wakeup */
+  Watchdog_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTimer_IRQn                 = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES                                { ADC0, ADC1 }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASES                               { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASES                               { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASES                                { CAN0 }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register  - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register  - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register  - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register  - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register  - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register  - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register  - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register  - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASES                                { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES                                { CMP0, CMP1, CMP2 }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASES                                { CMT }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASES                                { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES                                { DAC0, DAC1 }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+       uint8_t RESERVED_6[184];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_7[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_EARS_REG(base)                       ((base)->EARS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+/* EARS Bit Fields */
+#define DMA_EARS_EDREQ_0_MASK                    0x1u
+#define DMA_EARS_EDREQ_0_SHIFT                   0
+#define DMA_EARS_EDREQ_1_MASK                    0x2u
+#define DMA_EARS_EDREQ_1_SHIFT                   1
+#define DMA_EARS_EDREQ_2_MASK                    0x4u
+#define DMA_EARS_EDREQ_2_SHIFT                   2
+#define DMA_EARS_EDREQ_3_MASK                    0x8u
+#define DMA_EARS_EDREQ_3_SHIFT                   3
+#define DMA_EARS_EDREQ_4_MASK                    0x10u
+#define DMA_EARS_EDREQ_4_SHIFT                   4
+#define DMA_EARS_EDREQ_5_MASK                    0x20u
+#define DMA_EARS_EDREQ_5_SHIFT                   5
+#define DMA_EARS_EDREQ_6_MASK                    0x40u
+#define DMA_EARS_EDREQ_6_SHIFT                   6
+#define DMA_EARS_EDREQ_7_MASK                    0x80u
+#define DMA_EARS_EDREQ_7_SHIFT                   7
+#define DMA_EARS_EDREQ_8_MASK                    0x100u
+#define DMA_EARS_EDREQ_8_SHIFT                   8
+#define DMA_EARS_EDREQ_9_MASK                    0x200u
+#define DMA_EARS_EDREQ_9_SHIFT                   9
+#define DMA_EARS_EDREQ_10_MASK                   0x400u
+#define DMA_EARS_EDREQ_10_SHIFT                  10
+#define DMA_EARS_EDREQ_11_MASK                   0x800u
+#define DMA_EARS_EDREQ_11_SHIFT                  11
+#define DMA_EARS_EDREQ_12_MASK                   0x1000u
+#define DMA_EARS_EDREQ_12_SHIFT                  12
+#define DMA_EARS_EDREQ_13_MASK                   0x2000u
+#define DMA_EARS_EDREQ_13_SHIFT                  13
+#define DMA_EARS_EDREQ_14_MASK                   0x4000u
+#define DMA_EARS_EDREQ_14_SHIFT                  14
+#define DMA_EARS_EDREQ_15_MASK                   0x8000u
+#define DMA_EARS_EDREQ_15_SHIFT                  15
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES                                { DMA0 }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_EARS                                 DMA_EARS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES                             { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[56];
+  __IO uint32_t RMON_T_DROP;                       /**< Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200 */
+  __IO uint32_t RMON_T_PACKETS;                    /**< RMON Tx packet count (RMON_T_PACKETS), offset: 0x204 */
+  __IO uint32_t RMON_T_BC_PKT;                     /**< RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208 */
+  __IO uint32_t RMON_T_MC_PKT;                     /**< RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C */
+  __IO uint32_t RMON_T_CRC_ALIGN;                  /**< RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210 */
+  __IO uint32_t RMON_T_UNDERSIZE;                  /**< RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214 */
+  __IO uint32_t RMON_T_OVERSIZE;                   /**< RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */
+  __IO uint32_t RMON_T_FRAG;                       /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */
+  __IO uint32_t RMON_T_JAB;                        /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */
+  __IO uint32_t RMON_T_COL;                        /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */
+  __IO uint32_t RMON_T_P64;                        /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */
+  __IO uint32_t RMON_T_P65TO127;                   /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */
+  __IO uint32_t RMON_T_P128TO255;                  /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */
+  __IO uint32_t RMON_T_P256TO511;                  /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */
+  __IO uint32_t RMON_T_P512TO1023;                 /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */
+  __IO uint32_t RMON_T_P1024TO2047;                /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */
+  __IO uint32_t RMON_T_P_GTE2048;                  /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */
+  __IO uint32_t RMON_T_OCTETS;                     /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */
+  __IO uint32_t IEEE_T_DROP;                       /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */
+  __IO uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */
+  __IO uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */
+  __IO uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */
+  __IO uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */
+  __IO uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */
+  __IO uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */
+  __IO uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */
+  __IO uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */
+  __IO uint32_t IEEE_T_SQE;                        /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */
+  __IO uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */
+  __IO uint32_t IEEE_T_OCTETS_OK;                  /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */
+       uint8_t RESERVED_14[12];
+  __IO uint32_t RMON_R_PACKETS;                    /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */
+  __IO uint32_t RMON_R_BC_PKT;                     /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */
+  __IO uint32_t RMON_R_MC_PKT;                     /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */
+  __IO uint32_t RMON_R_CRC_ALIGN;                  /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */
+  __IO uint32_t RMON_R_UNDERSIZE;                  /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */
+  __IO uint32_t RMON_R_OVERSIZE;                   /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */
+  __IO uint32_t RMON_R_FRAG;                       /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */
+  __IO uint32_t RMON_R_JAB;                        /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */
+  __IO uint32_t RMON_R_RESVD_0;                    /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */
+  __IO uint32_t RMON_R_P64;                        /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */
+  __IO uint32_t RMON_R_P65TO127;                   /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */
+  __IO uint32_t RMON_R_P128TO255;                  /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */
+  __IO uint32_t RMON_R_P256TO511;                  /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */
+  __IO uint32_t RMON_R_P512TO1023;                 /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */
+  __IO uint32_t RMON_R_P1024TO2047;                /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */
+  __IO uint32_t RMON_R_P_GTE2048;                  /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */
+  __IO uint32_t RMON_R_OCTETS;                     /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */
+  __IO uint32_t RMON_R_DROP;                       /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */
+  __IO uint32_t RMON_R_FRAME_OK;                   /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */
+  __IO uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */
+  __IO uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */
+  __IO uint32_t IEEE_R_MACERR;                     /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */
+  __IO uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */
+  __IO uint32_t IEEE_R_OCTETS_OK;                  /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */
+       uint8_t RESERVED_15[284];
+  __IO uint32_t ATCR;                              /**< Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __IO uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_16[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_DROP_REG(base)               ((base)->RMON_T_DROP)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_DROP_REG(base)               ((base)->IEEE_T_DROP)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_SQE_REG(base)                ((base)->IEEE_T_SQE)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_RESVD_0_REG(base)            ((base)->RMON_R_RESVD_0)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_RMON_R_DROP_REG(base)               ((base)->RMON_R_DROP)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ((base)->RMON_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASES                               { ENET }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_DROP                         ENET_RMON_T_DROP_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_DROP                         ENET_IEEE_T_DROP_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_SQE                          ENET_IEEE_T_SQE_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_RESVD_0                      ENET_RMON_R_RESVD_0_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_RMON_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_RMON_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASES                                { EWM }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASES                                 { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASES                                { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASES                               { FTFE }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASES                                { FTM0, FTM1, FTM2, FTM3 }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES                               { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES                                { I2C0, I2C1, I2C2 }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASES                                { I2S0 }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES                               { LLWU }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES                              { LPTMR0 }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+  __I  uint8_t C9;                                 /**< MCG Control 9 Register, offset: 0xE */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+#define MCG_C9_REG(base)                         ((base)->C9)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_EREFS0_MASK                       0x4u
+#define MCG_C2_EREFS0_SHIFT                      2
+#define MCG_C2_HGO0_MASK                         0x8u
+#define MCG_C2_HGO0_SHIFT                        3
+#define MCG_C2_RANGE0_MASK                       0x30u
+#define MCG_C2_RANGE0_SHIFT                      4
+#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES                                { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+#define MCG_C9                                   MCG_C9_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __I  uint32_t PLACR;                             /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
+  __IO uint32_t ISR;                               /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_PLACR_REG(base)                      ((base)->PLACR)
+#define MCM_ISR_REG(base)                        ((base)->ISR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK                       0x200u
+#define MCM_PLACR_ARB_SHIFT                      9
+/* ISR Bit Fields */
+#define MCM_ISR_IRQ_MASK                         0x2u
+#define MCM_ISR_IRQ_SHIFT                        1
+#define MCM_ISR_NMI_MASK                         0x4u
+#define MCM_ISR_NMI_SHIFT                        2
+#define MCM_ISR_DHREQ_MASK                       0x8u
+#define MCM_ISR_DHREQ_SHIFT                      3
+#define MCM_ISR_FIOC_MASK                        0x100u
+#define MCM_ISR_FIOC_SHIFT                       8
+#define MCM_ISR_FDZC_MASK                        0x200u
+#define MCM_ISR_FDZC_SHIFT                       9
+#define MCM_ISR_FOFC_MASK                        0x400u
+#define MCM_ISR_FOFC_SHIFT                       10
+#define MCM_ISR_FUFC_MASK                        0x800u
+#define MCM_ISR_FUFC_SHIFT                       11
+#define MCM_ISR_FIXC_MASK                        0x1000u
+#define MCM_ISR_FIXC_SHIFT                       12
+#define MCM_ISR_FIDC_MASK                        0x8000u
+#define MCM_ISR_FIDC_SHIFT                       15
+#define MCM_ISR_FIOCE_MASK                       0x1000000u
+#define MCM_ISR_FIOCE_SHIFT                      24
+#define MCM_ISR_FDZCE_MASK                       0x2000000u
+#define MCM_ISR_FDZCE_SHIFT                      25
+#define MCM_ISR_FOFCE_MASK                       0x4000000u
+#define MCM_ISR_FOFCE_SHIFT                      26
+#define MCM_ISR_FUFCE_MASK                       0x8000000u
+#define MCM_ISR_FUFCE_SHIFT                      27
+#define MCM_ISR_FIXCE_MASK                       0x10000000u
+#define MCM_ISR_FIXCE_SHIFT                      28
+#define MCM_ISR_FIDCE_MASK                       0x80000000u
+#define MCM_ISR_FIDCE_SHIFT                      31
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES                                { MCM }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_PLACR                                MCM_PLACR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASES                                { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES                                 { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES                                { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASES                                { PDB0 }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES                                { PIT }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES                                { PMC }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES                               { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES                                { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASES                              { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASES                             { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASES                                { RNG }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES                                { RTC }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASES                               { SDHC }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES                                { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES                                { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES                                { SPI0, SPI1, SPI2 }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816_T_TYPE0;                     /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816_T_TYPE1;                     /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816_T_TYPE0_REG(base)            ((base)->WP7816_T_TYPE0)
+#define UART_WP7816_T_TYPE1_REG(base)            ((base)->WP7816_T_TYPE1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK              0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT             0
+#define UART_WP7816_T_TYPE0_WI(x)                (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK             0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT            0
+#define UART_WP7816_T_TYPE1_BWI(x)               (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK             0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT            4
+#define UART_WP7816_T_TYPE1_CWI(x)               (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES                               { UART0, UART1, UART2, UART3, UART4, UART5 }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816_T_TYPE0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816_T_TYPE1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES                                { USB0 }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASES                             { USBDCD }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASES                               { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASES                               { WDOG }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MCU_MK64F12) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MCU_MK64F12) */
+
+#endif  /* #if !defined(MK64F12_H_) */
+/* MK64F12.h, eof. */
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h
new file mode 100644
index 0000000000..536b456cc1
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h
@@ -0,0 +1,2578 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_ADC_REGISTERS_H__
+#define __HW_ADC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - HW_ADC_SC1n - ADC Status and Control Registers 1
+ * - HW_ADC_CFG1 - ADC Configuration Register 1
+ * - HW_ADC_CFG2 - ADC Configuration Register 2
+ * - HW_ADC_Rn - ADC Data Result Register
+ * - HW_ADC_CV1 - Compare Value Registers
+ * - HW_ADC_CV2 - Compare Value Registers
+ * - HW_ADC_SC2 - Status and Control Register 2
+ * - HW_ADC_SC3 - Status and Control Register 3
+ * - HW_ADC_OFS - ADC Offset Correction Register
+ * - HW_ADC_PG - ADC Plus-Side Gain Register
+ * - HW_ADC_MG - ADC Minus-Side Gain Register
+ * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ *
+ * - hw_adc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_ADC_BASE
+#define HW_ADC_INSTANCE_COUNT (2U) //!< Number of instances of the ADC module.
+#define HW_ADC0 (0U) //!< Instance number for ADC0.
+#define HW_ADC1 (1U) //!< Instance number for ADC1.
+#define REGS_ADC0_BASE (0x4003B000U) //!< Base address for ADC0.
+#define REGS_ADC1_BASE (0x400BB000U) //!< Base address for ADC1.
+
+//! @brief Table of base addresses for ADC instances.
+static const uint32_t __g_regs_ADC_base_addresses[] = {
+        REGS_ADC0_BASE,
+        REGS_ADC1_BASE,
+    };
+
+//! @brief Get the base address of ADC by instance number.
+//! @param x ADC instance number, from 0 through 1.
+#define REGS_ADC_BASE(x) (__g_regs_ADC_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of ADC.
+#define REGS_ADC_INSTANCE(b) ((b) == REGS_ADC0_BASE ? HW_ADC0 : (b) == REGS_ADC1_BASE ? HW_ADC1 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_SC1n - ADC Status and Control Registers 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+typedef union _hw_adc_sc1n
+{
+    uint32_t U;
+    struct _hw_adc_sc1n_bitfields
+    {
+        uint32_t ADCH : 5;             //!< [4:0] Input channel select
+        uint32_t DIFF : 1;             //!< [5] Differential Mode Enable
+        uint32_t AIEN : 1;             //!< [6] Interrupt Enable
+        uint32_t COCO : 1;             //!< [7] Conversion Complete Flag
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_adc_sc1n_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_SC1n register
+ */
+//@{
+#define HW_ADC_SC1n_COUNT (2U)
+
+#define HW_ADC_SC1n_ADDR(x, n)   (REGS_ADC_BASE(x) + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_SC1n(x, n)        (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
+#define HW_ADC_SC1n_RD(x, n)     (HW_ADC_SC1n(x, n).U)
+#define HW_ADC_SC1n_WR(x, n, v)  (HW_ADC_SC1n(x, n).U = (v))
+#define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) |  (v)))
+#define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
+#define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_SC1n bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1n, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
+ * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
+ * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
+ * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
+ * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
+ * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
+ * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
+ * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
+ * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
+ * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
+ * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
+ * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
+ * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
+ * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
+ * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
+ * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
+ * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
+ * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
+ * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
+ * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
+ * - 11000 - Reserved.
+ * - 11001 - Reserved.
+ * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
+ *     DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 11100 - Reserved.
+ * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 11111 - Module is disabled.
+ */
+//@{
+#define BP_ADC_SC1n_ADCH     (0U)          //!< Bit position for ADC_SC1n_ADCH.
+#define BM_ADC_SC1n_ADCH     (0x0000001FU) //!< Bit mask for ADC_SC1n_ADCH.
+#define BS_ADC_SC1n_ADCH     (5U)          //!< Bit field size in bits for ADC_SC1n_ADCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_ADCH field.
+#define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
+#endif
+
+//! @brief Format value for bitfield ADC_SC1n_ADCH.
+#define BF_ADC_SC1n_ADCH(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_ADCH), uint32_t) & BM_ADC_SC1n_ADCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADCH field to a new value.
+#define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC1n, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0 - Single-ended conversions and input channels are selected.
+ * - 1 - Differential conversions and input channels are selected.
+ */
+//@{
+#define BP_ADC_SC1n_DIFF     (5U)          //!< Bit position for ADC_SC1n_DIFF.
+#define BM_ADC_SC1n_DIFF     (0x00000020U) //!< Bit mask for ADC_SC1n_DIFF.
+#define BS_ADC_SC1n_DIFF     (1U)          //!< Bit field size in bits for ADC_SC1n_DIFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_DIFF field.
+#define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
+#endif
+
+//! @brief Format value for bitfield ADC_SC1n_DIFF.
+#define BF_ADC_SC1n_DIFF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_DIFF), uint32_t) & BM_ADC_SC1n_DIFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIFF field to a new value.
+#define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC1n, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0 - Conversion complete interrupt is disabled.
+ * - 1 - Conversion complete interrupt is enabled.
+ */
+//@{
+#define BP_ADC_SC1n_AIEN     (6U)          //!< Bit position for ADC_SC1n_AIEN.
+#define BM_ADC_SC1n_AIEN     (0x00000040U) //!< Bit mask for ADC_SC1n_AIEN.
+#define BS_ADC_SC1n_AIEN     (1U)          //!< Bit field size in bits for ADC_SC1n_AIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_AIEN field.
+#define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
+#endif
+
+//! @brief Format value for bitfield ADC_SC1n_AIEN.
+#define BF_ADC_SC1n_AIEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_AIEN), uint32_t) & BM_ADC_SC1n_AIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AIEN field to a new value.
+#define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC1n, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0 - Conversion is not completed.
+ * - 1 - Conversion is completed.
+ */
+//@{
+#define BP_ADC_SC1n_COCO     (7U)          //!< Bit position for ADC_SC1n_COCO.
+#define BM_ADC_SC1n_COCO     (0x00000080U) //!< Bit mask for ADC_SC1n_COCO.
+#define BS_ADC_SC1n_COCO     (1U)          //!< Bit field size in bits for ADC_SC1n_COCO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_COCO field.
+#define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CFG1 - ADC Configuration Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+typedef union _hw_adc_cfg1
+{
+    uint32_t U;
+    struct _hw_adc_cfg1_bitfields
+    {
+        uint32_t ADICLK : 2;           //!< [1:0] Input Clock Select
+        uint32_t MODE : 2;             //!< [3:2] Conversion mode selection
+        uint32_t ADLSMP : 1;           //!< [4] Sample Time Configuration
+        uint32_t ADIV : 2;             //!< [6:5] Clock Divide Select
+        uint32_t ADLPC : 1;            //!< [7] Low-Power Configuration
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_adc_cfg1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+//@{
+#define HW_ADC_CFG1_ADDR(x)      (REGS_ADC_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CFG1(x)           (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
+#define HW_ADC_CFG1_RD(x)        (HW_ADC_CFG1(x).U)
+#define HW_ADC_CFG1_WR(x, v)     (HW_ADC_CFG1(x).U = (v))
+#define HW_ADC_CFG1_SET(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) |  (v)))
+#define HW_ADC_CFG1_CLR(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
+#define HW_ADC_CFG1_TOG(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 00 - Bus clock
+ * - 01 - Alternate clock 2 (ALTCLK2)
+ * - 10 - Alternate clock (ALTCLK)
+ * - 11 - Asynchronous clock (ADACK)
+ */
+//@{
+#define BP_ADC_CFG1_ADICLK   (0U)          //!< Bit position for ADC_CFG1_ADICLK.
+#define BM_ADC_CFG1_ADICLK   (0x00000003U) //!< Bit mask for ADC_CFG1_ADICLK.
+#define BS_ADC_CFG1_ADICLK   (2U)          //!< Bit field size in bits for ADC_CFG1_ADICLK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADICLK field.
+#define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADICLK.
+#define BF_ADC_CFG1_ADICLK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADICLK), uint32_t) & BM_ADC_CFG1_ADICLK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADICLK field to a new value.
+#define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
+ *     differential 13-bit conversion with 2's complement output.
+ * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
+ *     differential 11-bit conversion with 2's complement output
+ * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
+ *     differential 16-bit conversion with 2's complement output
+ */
+//@{
+#define BP_ADC_CFG1_MODE     (2U)          //!< Bit position for ADC_CFG1_MODE.
+#define BM_ADC_CFG1_MODE     (0x0000000CU) //!< Bit mask for ADC_CFG1_MODE.
+#define BS_ADC_CFG1_MODE     (2U)          //!< Bit field size in bits for ADC_CFG1_MODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_MODE field.
+#define BR_ADC_CFG1_MODE(x)  (HW_ADC_CFG1(x).B.MODE)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_MODE.
+#define BF_ADC_CFG1_MODE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_MODE), uint32_t) & BM_ADC_CFG1_MODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MODE field to a new value.
+#define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0 - Short sample time.
+ * - 1 - Long sample time.
+ */
+//@{
+#define BP_ADC_CFG1_ADLSMP   (4U)          //!< Bit position for ADC_CFG1_ADLSMP.
+#define BM_ADC_CFG1_ADLSMP   (0x00000010U) //!< Bit mask for ADC_CFG1_ADLSMP.
+#define BS_ADC_CFG1_ADLSMP   (1U)          //!< Bit field size in bits for ADC_CFG1_ADLSMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADLSMP field.
+#define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADLSMP.
+#define BF_ADC_CFG1_ADLSMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLSMP), uint32_t) & BM_ADC_CFG1_ADLSMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADLSMP field to a new value.
+#define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+//@{
+#define BP_ADC_CFG1_ADIV     (5U)          //!< Bit position for ADC_CFG1_ADIV.
+#define BM_ADC_CFG1_ADIV     (0x00000060U) //!< Bit mask for ADC_CFG1_ADIV.
+#define BS_ADC_CFG1_ADIV     (2U)          //!< Bit field size in bits for ADC_CFG1_ADIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADIV field.
+#define BR_ADC_CFG1_ADIV(x)  (HW_ADC_CFG1(x).B.ADIV)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADIV.
+#define BF_ADC_CFG1_ADIV(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADIV), uint32_t) & BM_ADC_CFG1_ADIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADIV field to a new value.
+#define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0 - Normal power configuration.
+ * - 1 - Low-power configuration. The power is reduced at the expense of maximum
+ *     clock speed.
+ */
+//@{
+#define BP_ADC_CFG1_ADLPC    (7U)          //!< Bit position for ADC_CFG1_ADLPC.
+#define BM_ADC_CFG1_ADLPC    (0x00000080U) //!< Bit mask for ADC_CFG1_ADLPC.
+#define BS_ADC_CFG1_ADLPC    (1U)          //!< Bit field size in bits for ADC_CFG1_ADLPC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADLPC field.
+#define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADLPC.
+#define BF_ADC_CFG1_ADLPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLPC), uint32_t) & BM_ADC_CFG1_ADLPC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADLPC field to a new value.
+#define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CFG2 - ADC Configuration Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+typedef union _hw_adc_cfg2
+{
+    uint32_t U;
+    struct _hw_adc_cfg2_bitfields
+    {
+        uint32_t ADLSTS : 2;           //!< [1:0] Long Sample Time Select
+        uint32_t ADHSC : 1;            //!< [2] High-Speed Configuration
+        uint32_t ADACKEN : 1;          //!< [3] Asynchronous Clock Output Enable
+        uint32_t MUXSEL : 1;           //!< [4] ADC Mux Select
+        uint32_t RESERVED0 : 27;       //!< [31:5]
+    } B;
+} hw_adc_cfg2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+//@{
+#define HW_ADC_CFG2_ADDR(x)      (REGS_ADC_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CFG2(x)           (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
+#define HW_ADC_CFG2_RD(x)        (HW_ADC_CFG2(x).U)
+#define HW_ADC_CFG2_WR(x, v)     (HW_ADC_CFG2(x).U = (v))
+#define HW_ADC_CFG2_SET(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) |  (v)))
+#define HW_ADC_CFG2_CLR(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
+#define HW_ADC_CFG2_TOG(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+//@{
+#define BP_ADC_CFG2_ADLSTS   (0U)          //!< Bit position for ADC_CFG2_ADLSTS.
+#define BM_ADC_CFG2_ADLSTS   (0x00000003U) //!< Bit mask for ADC_CFG2_ADLSTS.
+#define BS_ADC_CFG2_ADLSTS   (2U)          //!< Bit field size in bits for ADC_CFG2_ADLSTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_ADLSTS field.
+#define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_ADLSTS.
+#define BF_ADC_CFG2_ADLSTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADLSTS), uint32_t) & BM_ADC_CFG2_ADLSTS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADLSTS field to a new value.
+#define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0 - Normal conversion sequence selected.
+ * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+//@{
+#define BP_ADC_CFG2_ADHSC    (2U)          //!< Bit position for ADC_CFG2_ADHSC.
+#define BM_ADC_CFG2_ADHSC    (0x00000004U) //!< Bit mask for ADC_CFG2_ADHSC.
+#define BS_ADC_CFG2_ADHSC    (1U)          //!< Bit field size in bits for ADC_CFG2_ADHSC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_ADHSC field.
+#define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_ADHSC.
+#define BF_ADC_CFG2_ADHSC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADHSC), uint32_t) & BM_ADC_CFG2_ADHSC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADHSC field to a new value.
+#define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
+ *     if selected by ADICLK and a conversion is active.
+ * - 1 - Asynchronous clock and clock output is enabled regardless of the state
+ *     of the ADC.
+ */
+//@{
+#define BP_ADC_CFG2_ADACKEN  (3U)          //!< Bit position for ADC_CFG2_ADACKEN.
+#define BM_ADC_CFG2_ADACKEN  (0x00000008U) //!< Bit mask for ADC_CFG2_ADACKEN.
+#define BS_ADC_CFG2_ADACKEN  (1U)          //!< Bit field size in bits for ADC_CFG2_ADACKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_ADACKEN field.
+#define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_ADACKEN.
+#define BF_ADC_CFG2_ADACKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADACKEN), uint32_t) & BM_ADC_CFG2_ADACKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADACKEN field to a new value.
+#define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0 - ADxxa channels are selected.
+ * - 1 - ADxxb channels are selected.
+ */
+//@{
+#define BP_ADC_CFG2_MUXSEL   (4U)          //!< Bit position for ADC_CFG2_MUXSEL.
+#define BM_ADC_CFG2_MUXSEL   (0x00000010U) //!< Bit mask for ADC_CFG2_MUXSEL.
+#define BS_ADC_CFG2_MUXSEL   (1U)          //!< Bit field size in bits for ADC_CFG2_MUXSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_MUXSEL field.
+#define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_MUXSEL.
+#define BF_ADC_CFG2_MUXSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_MUXSEL), uint32_t) & BM_ADC_CFG2_MUXSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MUXSEL field to a new value.
+#define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_Rn - ADC Data Result Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_Rn - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+typedef union _hw_adc_rn
+{
+    uint32_t U;
+    struct _hw_adc_rn_bitfields
+    {
+        uint32_t D : 16;               //!< [15:0] Data result
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_adc_rn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_Rn register
+ */
+//@{
+#define HW_ADC_Rn_COUNT (2U)
+
+#define HW_ADC_Rn_ADDR(x, n)     (REGS_ADC_BASE(x) + 0x10U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_Rn(x, n)          (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
+#define HW_ADC_Rn_RD(x, n)       (HW_ADC_Rn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_Rn bitfields
+ */
+
+/*!
+ * @name Register ADC_Rn, field D[15:0] (RO)
+ */
+//@{
+#define BP_ADC_Rn_D          (0U)          //!< Bit position for ADC_Rn_D.
+#define BM_ADC_Rn_D          (0x0000FFFFU) //!< Bit mask for ADC_Rn_D.
+#define BS_ADC_Rn_D          (16U)         //!< Bit field size in bits for ADC_Rn_D.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_Rn_D field.
+#define BR_ADC_Rn_D(x, n)    (HW_ADC_Rn(x, n).B.D)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CV1 - Compare Value Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+typedef union _hw_adc_cv1
+{
+    uint32_t U;
+    struct _hw_adc_cv1_bitfields
+    {
+        uint32_t CV : 16;              //!< [15:0] Compare Value.
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_adc_cv1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+//@{
+#define HW_ADC_CV1_ADDR(x)       (REGS_ADC_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CV1(x)            (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
+#define HW_ADC_CV1_RD(x)         (HW_ADC_CV1(x).U)
+#define HW_ADC_CV1_WR(x, v)      (HW_ADC_CV1(x).U = (v))
+#define HW_ADC_CV1_SET(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) |  (v)))
+#define HW_ADC_CV1_CLR(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
+#define HW_ADC_CV1_TOG(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+//@{
+#define BP_ADC_CV1_CV        (0U)          //!< Bit position for ADC_CV1_CV.
+#define BM_ADC_CV1_CV        (0x0000FFFFU) //!< Bit mask for ADC_CV1_CV.
+#define BS_ADC_CV1_CV        (16U)         //!< Bit field size in bits for ADC_CV1_CV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CV1_CV field.
+#define BR_ADC_CV1_CV(x)     (HW_ADC_CV1(x).B.CV)
+#endif
+
+//! @brief Format value for bitfield ADC_CV1_CV.
+#define BF_ADC_CV1_CV(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV1_CV), uint32_t) & BM_ADC_CV1_CV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CV field to a new value.
+#define BW_ADC_CV1_CV(x, v)  (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CV2 - Compare Value Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+typedef union _hw_adc_cv2
+{
+    uint32_t U;
+    struct _hw_adc_cv2_bitfields
+    {
+        uint32_t CV : 16;              //!< [15:0] Compare Value.
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_adc_cv2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+//@{
+#define HW_ADC_CV2_ADDR(x)       (REGS_ADC_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CV2(x)            (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
+#define HW_ADC_CV2_RD(x)         (HW_ADC_CV2(x).U)
+#define HW_ADC_CV2_WR(x, v)      (HW_ADC_CV2(x).U = (v))
+#define HW_ADC_CV2_SET(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) |  (v)))
+#define HW_ADC_CV2_CLR(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
+#define HW_ADC_CV2_TOG(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+//@{
+#define BP_ADC_CV2_CV        (0U)          //!< Bit position for ADC_CV2_CV.
+#define BM_ADC_CV2_CV        (0x0000FFFFU) //!< Bit mask for ADC_CV2_CV.
+#define BS_ADC_CV2_CV        (16U)         //!< Bit field size in bits for ADC_CV2_CV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CV2_CV field.
+#define BR_ADC_CV2_CV(x)     (HW_ADC_CV2(x).B.CV)
+#endif
+
+//! @brief Format value for bitfield ADC_CV2_CV.
+#define BF_ADC_CV2_CV(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV2_CV), uint32_t) & BM_ADC_CV2_CV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CV field to a new value.
+#define BW_ADC_CV2_CV(x, v)  (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_SC2 - Status and Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+typedef union _hw_adc_sc2
+{
+    uint32_t U;
+    struct _hw_adc_sc2_bitfields
+    {
+        uint32_t REFSEL : 2;           //!< [1:0] Voltage Reference Selection
+        uint32_t DMAEN : 1;            //!< [2] DMA Enable
+        uint32_t ACREN : 1;            //!< [3] Compare Function Range Enable
+        uint32_t ACFGT : 1;            //!< [4] Compare Function Greater Than Enable
+        uint32_t ACFE : 1;             //!< [5] Compare Function Enable
+        uint32_t ADTRG : 1;            //!< [6] Conversion Trigger Select
+        uint32_t ADACT : 1;            //!< [7] Conversion Active
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_adc_sc2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+//@{
+#define HW_ADC_SC2_ADDR(x)       (REGS_ADC_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_SC2(x)            (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
+#define HW_ADC_SC2_RD(x)         (HW_ADC_SC2(x).U)
+#define HW_ADC_SC2_WR(x, v)      (HW_ADC_SC2(x).U = (v))
+#define HW_ADC_SC2_SET(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) |  (v)))
+#define HW_ADC_SC2_CLR(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
+#define HW_ADC_SC2_TOG(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
+ *     additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to this
+ *     MCU
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_ADC_SC2_REFSEL    (0U)          //!< Bit position for ADC_SC2_REFSEL.
+#define BM_ADC_SC2_REFSEL    (0x00000003U) //!< Bit mask for ADC_SC2_REFSEL.
+#define BS_ADC_SC2_REFSEL    (2U)          //!< Bit field size in bits for ADC_SC2_REFSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_REFSEL field.
+#define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_REFSEL.
+#define BF_ADC_SC2_REFSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_REFSEL), uint32_t) & BM_ADC_SC2_REFSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REFSEL field to a new value.
+#define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+//@{
+#define BP_ADC_SC2_DMAEN     (2U)          //!< Bit position for ADC_SC2_DMAEN.
+#define BM_ADC_SC2_DMAEN     (0x00000004U) //!< Bit mask for ADC_SC2_DMAEN.
+#define BS_ADC_SC2_DMAEN     (1U)          //!< Bit field size in bits for ADC_SC2_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_DMAEN field.
+#define BR_ADC_SC2_DMAEN(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_DMAEN.
+#define BF_ADC_SC2_DMAEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_DMAEN), uint32_t) & BM_ADC_SC2_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0 - Range function disabled. Only CV1 is compared.
+ * - 1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+//@{
+#define BP_ADC_SC2_ACREN     (3U)          //!< Bit position for ADC_SC2_ACREN.
+#define BM_ADC_SC2_ACREN     (0x00000008U) //!< Bit mask for ADC_SC2_ACREN.
+#define BS_ADC_SC2_ACREN     (1U)          //!< Bit field size in bits for ADC_SC2_ACREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ACREN field.
+#define BR_ADC_SC2_ACREN(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ACREN.
+#define BF_ADC_SC2_ACREN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACREN), uint32_t) & BM_ADC_SC2_ACREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACREN field to a new value.
+#define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0 - Configures less than threshold, outside range not inclusive and inside
+ *     range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+//@{
+#define BP_ADC_SC2_ACFGT     (4U)          //!< Bit position for ADC_SC2_ACFGT.
+#define BM_ADC_SC2_ACFGT     (0x00000010U) //!< Bit mask for ADC_SC2_ACFGT.
+#define BS_ADC_SC2_ACFGT     (1U)          //!< Bit field size in bits for ADC_SC2_ACFGT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ACFGT field.
+#define BR_ADC_SC2_ACFGT(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ACFGT.
+#define BF_ADC_SC2_ACFGT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFGT), uint32_t) & BM_ADC_SC2_ACFGT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACFGT field to a new value.
+#define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0 - Compare function disabled.
+ * - 1 - Compare function enabled.
+ */
+//@{
+#define BP_ADC_SC2_ACFE      (5U)          //!< Bit position for ADC_SC2_ACFE.
+#define BM_ADC_SC2_ACFE      (0x00000020U) //!< Bit mask for ADC_SC2_ACFE.
+#define BS_ADC_SC2_ACFE      (1U)          //!< Bit field size in bits for ADC_SC2_ACFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ACFE field.
+#define BR_ADC_SC2_ACFE(x)   (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ACFE.
+#define BF_ADC_SC2_ACFE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFE), uint32_t) & BM_ADC_SC2_ACFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACFE field to a new value.
+#define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0 - Software trigger selected.
+ * - 1 - Hardware trigger selected.
+ */
+//@{
+#define BP_ADC_SC2_ADTRG     (6U)          //!< Bit position for ADC_SC2_ADTRG.
+#define BM_ADC_SC2_ADTRG     (0x00000040U) //!< Bit mask for ADC_SC2_ADTRG.
+#define BS_ADC_SC2_ADTRG     (1U)          //!< Bit field size in bits for ADC_SC2_ADTRG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ADTRG field.
+#define BR_ADC_SC2_ADTRG(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ADTRG.
+#define BF_ADC_SC2_ADTRG(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ADTRG), uint32_t) & BM_ADC_SC2_ADTRG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADTRG field to a new value.
+#define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0 - Conversion not in progress.
+ * - 1 - Conversion in progress.
+ */
+//@{
+#define BP_ADC_SC2_ADACT     (7U)          //!< Bit position for ADC_SC2_ADACT.
+#define BM_ADC_SC2_ADACT     (0x00000080U) //!< Bit mask for ADC_SC2_ADACT.
+#define BS_ADC_SC2_ADACT     (1U)          //!< Bit field size in bits for ADC_SC2_ADACT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ADACT field.
+#define BR_ADC_SC2_ADACT(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_SC3 - Status and Control Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+typedef union _hw_adc_sc3
+{
+    uint32_t U;
+    struct _hw_adc_sc3_bitfields
+    {
+        uint32_t AVGS : 2;             //!< [1:0] Hardware Average Select
+        uint32_t AVGE : 1;             //!< [2] Hardware Average Enable
+        uint32_t ADCO : 1;             //!< [3] Continuous Conversion Enable
+        uint32_t RESERVED0 : 2;        //!< [5:4]
+        uint32_t CALF : 1;             //!< [6] Calibration Failed Flag
+        uint32_t CAL : 1;              //!< [7] Calibration
+        uint32_t RESERVED1 : 24;       //!< [31:8]
+    } B;
+} hw_adc_sc3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+//@{
+#define HW_ADC_SC3_ADDR(x)       (REGS_ADC_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_SC3(x)            (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
+#define HW_ADC_SC3_RD(x)         (HW_ADC_SC3(x).U)
+#define HW_ADC_SC3_WR(x, v)      (HW_ADC_SC3(x).U = (v))
+#define HW_ADC_SC3_SET(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) |  (v)))
+#define HW_ADC_SC3_CLR(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
+#define HW_ADC_SC3_TOG(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 00 - 4 samples averaged.
+ * - 01 - 8 samples averaged.
+ * - 10 - 16 samples averaged.
+ * - 11 - 32 samples averaged.
+ */
+//@{
+#define BP_ADC_SC3_AVGS      (0U)          //!< Bit position for ADC_SC3_AVGS.
+#define BM_ADC_SC3_AVGS      (0x00000003U) //!< Bit mask for ADC_SC3_AVGS.
+#define BS_ADC_SC3_AVGS      (2U)          //!< Bit field size in bits for ADC_SC3_AVGS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_AVGS field.
+#define BR_ADC_SC3_AVGS(x)   (HW_ADC_SC3(x).B.AVGS)
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_AVGS.
+#define BF_ADC_SC3_AVGS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGS), uint32_t) & BM_ADC_SC3_AVGS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVGS field to a new value.
+#define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0 - Hardware average function disabled.
+ * - 1 - Hardware average function enabled.
+ */
+//@{
+#define BP_ADC_SC3_AVGE      (2U)          //!< Bit position for ADC_SC3_AVGE.
+#define BM_ADC_SC3_AVGE      (0x00000004U) //!< Bit mask for ADC_SC3_AVGE.
+#define BS_ADC_SC3_AVGE      (1U)          //!< Bit field size in bits for ADC_SC3_AVGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_AVGE field.
+#define BR_ADC_SC3_AVGE(x)   (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_AVGE.
+#define BF_ADC_SC3_AVGE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGE), uint32_t) & BM_ADC_SC3_AVGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVGE field to a new value.
+#define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+//@{
+#define BP_ADC_SC3_ADCO      (3U)          //!< Bit position for ADC_SC3_ADCO.
+#define BM_ADC_SC3_ADCO      (0x00000008U) //!< Bit mask for ADC_SC3_ADCO.
+#define BS_ADC_SC3_ADCO      (1U)          //!< Bit field size in bits for ADC_SC3_ADCO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_ADCO field.
+#define BR_ADC_SC3_ADCO(x)   (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_ADCO.
+#define BF_ADC_SC3_ADCO(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_ADCO), uint32_t) & BM_ADC_SC3_ADCO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADCO field to a new value.
+#define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (RO)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0 - Calibration completed normally.
+ * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+//@{
+#define BP_ADC_SC3_CALF      (6U)          //!< Bit position for ADC_SC3_CALF.
+#define BM_ADC_SC3_CALF      (0x00000040U) //!< Bit mask for ADC_SC3_CALF.
+#define BS_ADC_SC3_CALF      (1U)          //!< Bit field size in bits for ADC_SC3_CALF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_CALF field.
+#define BR_ADC_SC3_CALF(x)   (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+//@{
+#define BP_ADC_SC3_CAL       (7U)          //!< Bit position for ADC_SC3_CAL.
+#define BM_ADC_SC3_CAL       (0x00000080U) //!< Bit mask for ADC_SC3_CAL.
+#define BS_ADC_SC3_CAL       (1U)          //!< Bit field size in bits for ADC_SC3_CAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_CAL field.
+#define BR_ADC_SC3_CAL(x)    (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_CAL.
+#define BF_ADC_SC3_CAL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_CAL), uint32_t) & BM_ADC_SC3_CAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAL field to a new value.
+#define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_OFS - ADC Offset Correction Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+typedef union _hw_adc_ofs
+{
+    uint32_t U;
+    struct _hw_adc_ofs_bitfields
+    {
+        uint32_t OFS : 16;             //!< [15:0] Offset Error Correction Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_adc_ofs_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+//@{
+#define HW_ADC_OFS_ADDR(x)       (REGS_ADC_BASE(x) + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_OFS(x)            (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
+#define HW_ADC_OFS_RD(x)         (HW_ADC_OFS(x).U)
+#define HW_ADC_OFS_WR(x, v)      (HW_ADC_OFS(x).U = (v))
+#define HW_ADC_OFS_SET(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) |  (v)))
+#define HW_ADC_OFS_CLR(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
+#define HW_ADC_OFS_TOG(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+//@{
+#define BP_ADC_OFS_OFS       (0U)          //!< Bit position for ADC_OFS_OFS.
+#define BM_ADC_OFS_OFS       (0x0000FFFFU) //!< Bit mask for ADC_OFS_OFS.
+#define BS_ADC_OFS_OFS       (16U)         //!< Bit field size in bits for ADC_OFS_OFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_OFS_OFS field.
+#define BR_ADC_OFS_OFS(x)    (HW_ADC_OFS(x).B.OFS)
+#endif
+
+//! @brief Format value for bitfield ADC_OFS_OFS.
+#define BF_ADC_OFS_OFS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_OFS_OFS), uint32_t) & BM_ADC_OFS_OFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFS field to a new value.
+#define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_PG - ADC Plus-Side Gain Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+typedef union _hw_adc_pg
+{
+    uint32_t U;
+    struct _hw_adc_pg_bitfields
+    {
+        uint32_t PG : 16;              //!< [15:0] Plus-Side Gain
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_adc_pg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+//@{
+#define HW_ADC_PG_ADDR(x)        (REGS_ADC_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_PG(x)             (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
+#define HW_ADC_PG_RD(x)          (HW_ADC_PG(x).U)
+#define HW_ADC_PG_WR(x, v)       (HW_ADC_PG(x).U = (v))
+#define HW_ADC_PG_SET(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) |  (v)))
+#define HW_ADC_PG_CLR(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
+#define HW_ADC_PG_TOG(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+//@{
+#define BP_ADC_PG_PG         (0U)          //!< Bit position for ADC_PG_PG.
+#define BM_ADC_PG_PG         (0x0000FFFFU) //!< Bit mask for ADC_PG_PG.
+#define BS_ADC_PG_PG         (16U)         //!< Bit field size in bits for ADC_PG_PG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_PG_PG field.
+#define BR_ADC_PG_PG(x)      (HW_ADC_PG(x).B.PG)
+#endif
+
+//! @brief Format value for bitfield ADC_PG_PG.
+#define BF_ADC_PG_PG(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_PG_PG), uint32_t) & BM_ADC_PG_PG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PG field to a new value.
+#define BW_ADC_PG_PG(x, v)   (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_MG - ADC Minus-Side Gain Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+typedef union _hw_adc_mg
+{
+    uint32_t U;
+    struct _hw_adc_mg_bitfields
+    {
+        uint32_t MG : 16;              //!< [15:0] Minus-Side Gain
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_adc_mg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+//@{
+#define HW_ADC_MG_ADDR(x)        (REGS_ADC_BASE(x) + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_MG(x)             (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
+#define HW_ADC_MG_RD(x)          (HW_ADC_MG(x).U)
+#define HW_ADC_MG_WR(x, v)       (HW_ADC_MG(x).U = (v))
+#define HW_ADC_MG_SET(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) |  (v)))
+#define HW_ADC_MG_CLR(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
+#define HW_ADC_MG_TOG(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+//@{
+#define BP_ADC_MG_MG         (0U)          //!< Bit position for ADC_MG_MG.
+#define BM_ADC_MG_MG         (0x0000FFFFU) //!< Bit mask for ADC_MG_MG.
+#define BS_ADC_MG_MG         (16U)         //!< Bit field size in bits for ADC_MG_MG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_MG_MG field.
+#define BR_ADC_MG_MG(x)      (HW_ADC_MG(x).B.MG)
+#endif
+
+//! @brief Format value for bitfield ADC_MG_MG.
+#define BF_ADC_MG_MG(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_MG_MG), uint32_t) & BM_ADC_MG_MG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MG field to a new value.
+#define BW_ADC_MG_MG(x, v)   (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+typedef union _hw_adc_clpd
+{
+    uint32_t U;
+    struct _hw_adc_clpd_bitfields
+    {
+        uint32_t CLPD : 6;             //!< [5:0]
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_adc_clpd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+//@{
+#define HW_ADC_CLPD_ADDR(x)      (REGS_ADC_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLPD(x)           (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
+#define HW_ADC_CLPD_RD(x)        (HW_ADC_CLPD(x).U)
+#define HW_ADC_CLPD_WR(x, v)     (HW_ADC_CLPD(x).U = (v))
+#define HW_ADC_CLPD_SET(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) |  (v)))
+#define HW_ADC_CLPD_CLR(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
+#define HW_ADC_CLPD_TOG(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLPD_CLPD     (0U)          //!< Bit position for ADC_CLPD_CLPD.
+#define BM_ADC_CLPD_CLPD     (0x0000003FU) //!< Bit mask for ADC_CLPD_CLPD.
+#define BS_ADC_CLPD_CLPD     (6U)          //!< Bit field size in bits for ADC_CLPD_CLPD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLPD_CLPD field.
+#define BR_ADC_CLPD_CLPD(x)  (HW_ADC_CLPD(x).B.CLPD)
+#endif
+
+//! @brief Format value for bitfield ADC_CLPD_CLPD.
+#define BF_ADC_CLPD_CLPD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPD_CLPD), uint32_t) & BM_ADC_CLPD_CLPD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLPD field to a new value.
+#define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clps
+{
+    uint32_t U;
+    struct _hw_adc_clps_bitfields
+    {
+        uint32_t CLPS : 6;             //!< [5:0]
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_adc_clps_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+//@{
+#define HW_ADC_CLPS_ADDR(x)      (REGS_ADC_BASE(x) + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLPS(x)           (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
+#define HW_ADC_CLPS_RD(x)        (HW_ADC_CLPS(x).U)
+#define HW_ADC_CLPS_WR(x, v)     (HW_ADC_CLPS(x).U = (v))
+#define HW_ADC_CLPS_SET(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) |  (v)))
+#define HW_ADC_CLPS_CLR(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
+#define HW_ADC_CLPS_TOG(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLPS_CLPS     (0U)          //!< Bit position for ADC_CLPS_CLPS.
+#define BM_ADC_CLPS_CLPS     (0x0000003FU) //!< Bit mask for ADC_CLPS_CLPS.
+#define BS_ADC_CLPS_CLPS     (6U)          //!< Bit field size in bits for ADC_CLPS_CLPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLPS_CLPS field.
+#define BR_ADC_CLPS_CLPS(x)  (HW_ADC_CLPS(x).B.CLPS)
+#endif
+
+//! @brief Format value for bitfield ADC_CLPS_CLPS.
+#define BF_ADC_CLPS_CLPS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPS_CLPS), uint32_t) & BM_ADC_CLPS_CLPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLPS field to a new value.
+#define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp4
+{
+    uint32_t U;
+    struct _hw_adc_clp4_bitfields
+    {
+        uint32_t CLP4 : 10;            //!< [9:0]
+        uint32_t RESERVED0 : 22;       //!< [31:10]
+    } B;
+} hw_adc_clp4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+//@{
+#define HW_ADC_CLP4_ADDR(x)      (REGS_ADC_BASE(x) + 0x3CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP4(x)           (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
+#define HW_ADC_CLP4_RD(x)        (HW_ADC_CLP4(x).U)
+#define HW_ADC_CLP4_WR(x, v)     (HW_ADC_CLP4(x).U = (v))
+#define HW_ADC_CLP4_SET(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) |  (v)))
+#define HW_ADC_CLP4_CLR(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
+#define HW_ADC_CLP4_TOG(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP4_CLP4     (0U)          //!< Bit position for ADC_CLP4_CLP4.
+#define BM_ADC_CLP4_CLP4     (0x000003FFU) //!< Bit mask for ADC_CLP4_CLP4.
+#define BS_ADC_CLP4_CLP4     (10U)         //!< Bit field size in bits for ADC_CLP4_CLP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP4_CLP4 field.
+#define BR_ADC_CLP4_CLP4(x)  (HW_ADC_CLP4(x).B.CLP4)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP4_CLP4.
+#define BF_ADC_CLP4_CLP4(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP4_CLP4), uint32_t) & BM_ADC_CLP4_CLP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP4 field to a new value.
+#define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp3
+{
+    uint32_t U;
+    struct _hw_adc_clp3_bitfields
+    {
+        uint32_t CLP3 : 9;             //!< [8:0]
+        uint32_t RESERVED0 : 23;       //!< [31:9]
+    } B;
+} hw_adc_clp3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+//@{
+#define HW_ADC_CLP3_ADDR(x)      (REGS_ADC_BASE(x) + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP3(x)           (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
+#define HW_ADC_CLP3_RD(x)        (HW_ADC_CLP3(x).U)
+#define HW_ADC_CLP3_WR(x, v)     (HW_ADC_CLP3(x).U = (v))
+#define HW_ADC_CLP3_SET(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) |  (v)))
+#define HW_ADC_CLP3_CLR(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
+#define HW_ADC_CLP3_TOG(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP3_CLP3     (0U)          //!< Bit position for ADC_CLP3_CLP3.
+#define BM_ADC_CLP3_CLP3     (0x000001FFU) //!< Bit mask for ADC_CLP3_CLP3.
+#define BS_ADC_CLP3_CLP3     (9U)          //!< Bit field size in bits for ADC_CLP3_CLP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP3_CLP3 field.
+#define BR_ADC_CLP3_CLP3(x)  (HW_ADC_CLP3(x).B.CLP3)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP3_CLP3.
+#define BF_ADC_CLP3_CLP3(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP3_CLP3), uint32_t) & BM_ADC_CLP3_CLP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP3 field to a new value.
+#define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp2
+{
+    uint32_t U;
+    struct _hw_adc_clp2_bitfields
+    {
+        uint32_t CLP2 : 8;             //!< [7:0]
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_adc_clp2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+//@{
+#define HW_ADC_CLP2_ADDR(x)      (REGS_ADC_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP2(x)           (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
+#define HW_ADC_CLP2_RD(x)        (HW_ADC_CLP2(x).U)
+#define HW_ADC_CLP2_WR(x, v)     (HW_ADC_CLP2(x).U = (v))
+#define HW_ADC_CLP2_SET(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) |  (v)))
+#define HW_ADC_CLP2_CLR(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
+#define HW_ADC_CLP2_TOG(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP2_CLP2     (0U)          //!< Bit position for ADC_CLP2_CLP2.
+#define BM_ADC_CLP2_CLP2     (0x000000FFU) //!< Bit mask for ADC_CLP2_CLP2.
+#define BS_ADC_CLP2_CLP2     (8U)          //!< Bit field size in bits for ADC_CLP2_CLP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP2_CLP2 field.
+#define BR_ADC_CLP2_CLP2(x)  (HW_ADC_CLP2(x).B.CLP2)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP2_CLP2.
+#define BF_ADC_CLP2_CLP2(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP2_CLP2), uint32_t) & BM_ADC_CLP2_CLP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP2 field to a new value.
+#define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp1
+{
+    uint32_t U;
+    struct _hw_adc_clp1_bitfields
+    {
+        uint32_t CLP1 : 7;             //!< [6:0]
+        uint32_t RESERVED0 : 25;       //!< [31:7]
+    } B;
+} hw_adc_clp1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+//@{
+#define HW_ADC_CLP1_ADDR(x)      (REGS_ADC_BASE(x) + 0x48U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP1(x)           (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
+#define HW_ADC_CLP1_RD(x)        (HW_ADC_CLP1(x).U)
+#define HW_ADC_CLP1_WR(x, v)     (HW_ADC_CLP1(x).U = (v))
+#define HW_ADC_CLP1_SET(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) |  (v)))
+#define HW_ADC_CLP1_CLR(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
+#define HW_ADC_CLP1_TOG(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP1_CLP1     (0U)          //!< Bit position for ADC_CLP1_CLP1.
+#define BM_ADC_CLP1_CLP1     (0x0000007FU) //!< Bit mask for ADC_CLP1_CLP1.
+#define BS_ADC_CLP1_CLP1     (7U)          //!< Bit field size in bits for ADC_CLP1_CLP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP1_CLP1 field.
+#define BR_ADC_CLP1_CLP1(x)  (HW_ADC_CLP1(x).B.CLP1)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP1_CLP1.
+#define BF_ADC_CLP1_CLP1(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP1_CLP1), uint32_t) & BM_ADC_CLP1_CLP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP1 field to a new value.
+#define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp0
+{
+    uint32_t U;
+    struct _hw_adc_clp0_bitfields
+    {
+        uint32_t CLP0 : 6;             //!< [5:0]
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_adc_clp0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+//@{
+#define HW_ADC_CLP0_ADDR(x)      (REGS_ADC_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP0(x)           (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
+#define HW_ADC_CLP0_RD(x)        (HW_ADC_CLP0(x).U)
+#define HW_ADC_CLP0_WR(x, v)     (HW_ADC_CLP0(x).U = (v))
+#define HW_ADC_CLP0_SET(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) |  (v)))
+#define HW_ADC_CLP0_CLR(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
+#define HW_ADC_CLP0_TOG(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP0_CLP0     (0U)          //!< Bit position for ADC_CLP0_CLP0.
+#define BM_ADC_CLP0_CLP0     (0x0000003FU) //!< Bit mask for ADC_CLP0_CLP0.
+#define BS_ADC_CLP0_CLP0     (6U)          //!< Bit field size in bits for ADC_CLP0_CLP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP0_CLP0 field.
+#define BR_ADC_CLP0_CLP0(x)  (HW_ADC_CLP0(x).B.CLP0)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP0_CLP0.
+#define BF_ADC_CLP0_CLP0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP0_CLP0), uint32_t) & BM_ADC_CLP0_CLP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP0 field to a new value.
+#define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+typedef union _hw_adc_clmd
+{
+    uint32_t U;
+    struct _hw_adc_clmd_bitfields
+    {
+        uint32_t CLMD : 6;             //!< [5:0]
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_adc_clmd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+//@{
+#define HW_ADC_CLMD_ADDR(x)      (REGS_ADC_BASE(x) + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLMD(x)           (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
+#define HW_ADC_CLMD_RD(x)        (HW_ADC_CLMD(x).U)
+#define HW_ADC_CLMD_WR(x, v)     (HW_ADC_CLMD(x).U = (v))
+#define HW_ADC_CLMD_SET(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) |  (v)))
+#define HW_ADC_CLMD_CLR(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
+#define HW_ADC_CLMD_TOG(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLMD_CLMD     (0U)          //!< Bit position for ADC_CLMD_CLMD.
+#define BM_ADC_CLMD_CLMD     (0x0000003FU) //!< Bit mask for ADC_CLMD_CLMD.
+#define BS_ADC_CLMD_CLMD     (6U)          //!< Bit field size in bits for ADC_CLMD_CLMD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLMD_CLMD field.
+#define BR_ADC_CLMD_CLMD(x)  (HW_ADC_CLMD(x).B.CLMD)
+#endif
+
+//! @brief Format value for bitfield ADC_CLMD_CLMD.
+#define BF_ADC_CLMD_CLMD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMD_CLMD), uint32_t) & BM_ADC_CLMD_CLMD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLMD field to a new value.
+#define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clms
+{
+    uint32_t U;
+    struct _hw_adc_clms_bitfields
+    {
+        uint32_t CLMS : 6;             //!< [5:0]
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_adc_clms_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+//@{
+#define HW_ADC_CLMS_ADDR(x)      (REGS_ADC_BASE(x) + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLMS(x)           (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
+#define HW_ADC_CLMS_RD(x)        (HW_ADC_CLMS(x).U)
+#define HW_ADC_CLMS_WR(x, v)     (HW_ADC_CLMS(x).U = (v))
+#define HW_ADC_CLMS_SET(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) |  (v)))
+#define HW_ADC_CLMS_CLR(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
+#define HW_ADC_CLMS_TOG(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLMS_CLMS     (0U)          //!< Bit position for ADC_CLMS_CLMS.
+#define BM_ADC_CLMS_CLMS     (0x0000003FU) //!< Bit mask for ADC_CLMS_CLMS.
+#define BS_ADC_CLMS_CLMS     (6U)          //!< Bit field size in bits for ADC_CLMS_CLMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLMS_CLMS field.
+#define BR_ADC_CLMS_CLMS(x)  (HW_ADC_CLMS(x).B.CLMS)
+#endif
+
+//! @brief Format value for bitfield ADC_CLMS_CLMS.
+#define BF_ADC_CLMS_CLMS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMS_CLMS), uint32_t) & BM_ADC_CLMS_CLMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLMS field to a new value.
+#define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm4
+{
+    uint32_t U;
+    struct _hw_adc_clm4_bitfields
+    {
+        uint32_t CLM4 : 10;            //!< [9:0]
+        uint32_t RESERVED0 : 22;       //!< [31:10]
+    } B;
+} hw_adc_clm4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+//@{
+#define HW_ADC_CLM4_ADDR(x)      (REGS_ADC_BASE(x) + 0x5CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM4(x)           (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
+#define HW_ADC_CLM4_RD(x)        (HW_ADC_CLM4(x).U)
+#define HW_ADC_CLM4_WR(x, v)     (HW_ADC_CLM4(x).U = (v))
+#define HW_ADC_CLM4_SET(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) |  (v)))
+#define HW_ADC_CLM4_CLR(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
+#define HW_ADC_CLM4_TOG(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM4_CLM4     (0U)          //!< Bit position for ADC_CLM4_CLM4.
+#define BM_ADC_CLM4_CLM4     (0x000003FFU) //!< Bit mask for ADC_CLM4_CLM4.
+#define BS_ADC_CLM4_CLM4     (10U)         //!< Bit field size in bits for ADC_CLM4_CLM4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM4_CLM4 field.
+#define BR_ADC_CLM4_CLM4(x)  (HW_ADC_CLM4(x).B.CLM4)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM4_CLM4.
+#define BF_ADC_CLM4_CLM4(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM4_CLM4), uint32_t) & BM_ADC_CLM4_CLM4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM4 field to a new value.
+#define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm3
+{
+    uint32_t U;
+    struct _hw_adc_clm3_bitfields
+    {
+        uint32_t CLM3 : 9;             //!< [8:0]
+        uint32_t RESERVED0 : 23;       //!< [31:9]
+    } B;
+} hw_adc_clm3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+//@{
+#define HW_ADC_CLM3_ADDR(x)      (REGS_ADC_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM3(x)           (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
+#define HW_ADC_CLM3_RD(x)        (HW_ADC_CLM3(x).U)
+#define HW_ADC_CLM3_WR(x, v)     (HW_ADC_CLM3(x).U = (v))
+#define HW_ADC_CLM3_SET(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) |  (v)))
+#define HW_ADC_CLM3_CLR(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
+#define HW_ADC_CLM3_TOG(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM3_CLM3     (0U)          //!< Bit position for ADC_CLM3_CLM3.
+#define BM_ADC_CLM3_CLM3     (0x000001FFU) //!< Bit mask for ADC_CLM3_CLM3.
+#define BS_ADC_CLM3_CLM3     (9U)          //!< Bit field size in bits for ADC_CLM3_CLM3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM3_CLM3 field.
+#define BR_ADC_CLM3_CLM3(x)  (HW_ADC_CLM3(x).B.CLM3)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM3_CLM3.
+#define BF_ADC_CLM3_CLM3(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM3_CLM3), uint32_t) & BM_ADC_CLM3_CLM3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM3 field to a new value.
+#define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm2
+{
+    uint32_t U;
+    struct _hw_adc_clm2_bitfields
+    {
+        uint32_t CLM2 : 8;             //!< [7:0]
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_adc_clm2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+//@{
+#define HW_ADC_CLM2_ADDR(x)      (REGS_ADC_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM2(x)           (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
+#define HW_ADC_CLM2_RD(x)        (HW_ADC_CLM2(x).U)
+#define HW_ADC_CLM2_WR(x, v)     (HW_ADC_CLM2(x).U = (v))
+#define HW_ADC_CLM2_SET(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) |  (v)))
+#define HW_ADC_CLM2_CLR(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
+#define HW_ADC_CLM2_TOG(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM2_CLM2     (0U)          //!< Bit position for ADC_CLM2_CLM2.
+#define BM_ADC_CLM2_CLM2     (0x000000FFU) //!< Bit mask for ADC_CLM2_CLM2.
+#define BS_ADC_CLM2_CLM2     (8U)          //!< Bit field size in bits for ADC_CLM2_CLM2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM2_CLM2 field.
+#define BR_ADC_CLM2_CLM2(x)  (HW_ADC_CLM2(x).B.CLM2)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM2_CLM2.
+#define BF_ADC_CLM2_CLM2(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM2_CLM2), uint32_t) & BM_ADC_CLM2_CLM2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM2 field to a new value.
+#define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm1
+{
+    uint32_t U;
+    struct _hw_adc_clm1_bitfields
+    {
+        uint32_t CLM1 : 7;             //!< [6:0]
+        uint32_t RESERVED0 : 25;       //!< [31:7]
+    } B;
+} hw_adc_clm1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+//@{
+#define HW_ADC_CLM1_ADDR(x)      (REGS_ADC_BASE(x) + 0x68U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM1(x)           (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
+#define HW_ADC_CLM1_RD(x)        (HW_ADC_CLM1(x).U)
+#define HW_ADC_CLM1_WR(x, v)     (HW_ADC_CLM1(x).U = (v))
+#define HW_ADC_CLM1_SET(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) |  (v)))
+#define HW_ADC_CLM1_CLR(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
+#define HW_ADC_CLM1_TOG(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM1_CLM1     (0U)          //!< Bit position for ADC_CLM1_CLM1.
+#define BM_ADC_CLM1_CLM1     (0x0000007FU) //!< Bit mask for ADC_CLM1_CLM1.
+#define BS_ADC_CLM1_CLM1     (7U)          //!< Bit field size in bits for ADC_CLM1_CLM1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM1_CLM1 field.
+#define BR_ADC_CLM1_CLM1(x)  (HW_ADC_CLM1(x).B.CLM1)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM1_CLM1.
+#define BF_ADC_CLM1_CLM1(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM1_CLM1), uint32_t) & BM_ADC_CLM1_CLM1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM1 field to a new value.
+#define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm0
+{
+    uint32_t U;
+    struct _hw_adc_clm0_bitfields
+    {
+        uint32_t CLM0 : 6;             //!< [5:0]
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_adc_clm0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+//@{
+#define HW_ADC_CLM0_ADDR(x)      (REGS_ADC_BASE(x) + 0x6CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM0(x)           (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
+#define HW_ADC_CLM0_RD(x)        (HW_ADC_CLM0(x).U)
+#define HW_ADC_CLM0_WR(x, v)     (HW_ADC_CLM0(x).U = (v))
+#define HW_ADC_CLM0_SET(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) |  (v)))
+#define HW_ADC_CLM0_CLR(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
+#define HW_ADC_CLM0_TOG(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM0_CLM0     (0U)          //!< Bit position for ADC_CLM0_CLM0.
+#define BM_ADC_CLM0_CLM0     (0x0000003FU) //!< Bit mask for ADC_CLM0_CLM0.
+#define BS_ADC_CLM0_CLM0     (6U)          //!< Bit field size in bits for ADC_CLM0_CLM0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM0_CLM0 field.
+#define BR_ADC_CLM0_CLM0(x)  (HW_ADC_CLM0(x).B.CLM0)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM0_CLM0.
+#define BF_ADC_CLM0_CLM0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM0_CLM0), uint32_t) & BM_ADC_CLM0_CLM0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM0 field to a new value.
+#define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_adc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All ADC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_adc
+{
+    __IO hw_adc_sc1n_t SC1n[2];            //!< [0x0] ADC Status and Control Registers 1
+    __IO hw_adc_cfg1_t CFG1;               //!< [0x8] ADC Configuration Register 1
+    __IO hw_adc_cfg2_t CFG2;               //!< [0xC] ADC Configuration Register 2
+    __I hw_adc_rn_t Rn[2];                 //!< [0x10] ADC Data Result Register
+    __IO hw_adc_cv1_t CV1;                 //!< [0x18] Compare Value Registers
+    __IO hw_adc_cv2_t CV2;                 //!< [0x1C] Compare Value Registers
+    __IO hw_adc_sc2_t SC2;                 //!< [0x20] Status and Control Register 2
+    __IO hw_adc_sc3_t SC3;                 //!< [0x24] Status and Control Register 3
+    __IO hw_adc_ofs_t OFS;                 //!< [0x28] ADC Offset Correction Register
+    __IO hw_adc_pg_t PG;                   //!< [0x2C] ADC Plus-Side Gain Register
+    __IO hw_adc_mg_t MG;                   //!< [0x30] ADC Minus-Side Gain Register
+    __IO hw_adc_clpd_t CLPD;               //!< [0x34] ADC Plus-Side General Calibration Value Register
+    __IO hw_adc_clps_t CLPS;               //!< [0x38] ADC Plus-Side General Calibration Value Register
+    __IO hw_adc_clp4_t CLP4;               //!< [0x3C] ADC Plus-Side General Calibration Value Register
+    __IO hw_adc_clp3_t CLP3;               //!< [0x40] ADC Plus-Side General Calibration Value Register
+    __IO hw_adc_clp2_t CLP2;               //!< [0x44] ADC Plus-Side General Calibration Value Register
+    __IO hw_adc_clp1_t CLP1;               //!< [0x48] ADC Plus-Side General Calibration Value Register
+    __IO hw_adc_clp0_t CLP0;               //!< [0x4C] ADC Plus-Side General Calibration Value Register
+    uint8_t _reserved0[4];
+    __IO hw_adc_clmd_t CLMD;               //!< [0x54] ADC Minus-Side General Calibration Value Register
+    __IO hw_adc_clms_t CLMS;               //!< [0x58] ADC Minus-Side General Calibration Value Register
+    __IO hw_adc_clm4_t CLM4;               //!< [0x5C] ADC Minus-Side General Calibration Value Register
+    __IO hw_adc_clm3_t CLM3;               //!< [0x60] ADC Minus-Side General Calibration Value Register
+    __IO hw_adc_clm2_t CLM2;               //!< [0x64] ADC Minus-Side General Calibration Value Register
+    __IO hw_adc_clm1_t CLM1;               //!< [0x68] ADC Minus-Side General Calibration Value Register
+    __IO hw_adc_clm0_t CLM0;               //!< [0x6C] ADC Minus-Side General Calibration Value Register
+} hw_adc_t;
+#pragma pack()
+
+//! @brief Macro to access all ADC registers.
+//! @param x ADC instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_ADC(0)</code>.
+#define HW_ADC(x)      (*(hw_adc_t *) REGS_ADC_BASE(x))
+#endif
+
+#endif // __HW_ADC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h
new file mode 100644
index 0000000000..d2c40754f8
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h
@@ -0,0 +1,14135 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_AIPS_REGISTERS_H__
+#define __HW_AIPS_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - HW_AIPS_MPRA - Master Privilege Register A
+ * - HW_AIPS_PACRA - Peripheral Access Control Register
+ * - HW_AIPS_PACRB - Peripheral Access Control Register
+ * - HW_AIPS_PACRC - Peripheral Access Control Register
+ * - HW_AIPS_PACRD - Peripheral Access Control Register
+ * - HW_AIPS_PACRE - Peripheral Access Control Register
+ * - HW_AIPS_PACRF - Peripheral Access Control Register
+ * - HW_AIPS_PACRG - Peripheral Access Control Register
+ * - HW_AIPS_PACRH - Peripheral Access Control Register
+ * - HW_AIPS_PACRI - Peripheral Access Control Register
+ * - HW_AIPS_PACRJ - Peripheral Access Control Register
+ * - HW_AIPS_PACRK - Peripheral Access Control Register
+ * - HW_AIPS_PACRL - Peripheral Access Control Register
+ * - HW_AIPS_PACRM - Peripheral Access Control Register
+ * - HW_AIPS_PACRN - Peripheral Access Control Register
+ * - HW_AIPS_PACRO - Peripheral Access Control Register
+ * - HW_AIPS_PACRP - Peripheral Access Control Register
+ * - HW_AIPS_PACRU - Peripheral Access Control Register
+ *
+ * - hw_aips_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_AIPS_BASE
+#define HW_AIPS_INSTANCE_COUNT (2U) //!< Number of instances of the AIPS module.
+#define HW_AIPS0 (0U) //!< Instance number for AIPS0.
+#define HW_AIPS1 (1U) //!< Instance number for AIPS1.
+#define REGS_AIPS0_BASE (0x40000000U) //!< Base address for AIPS0.
+#define REGS_AIPS1_BASE (0x40080000U) //!< Base address for AIPS1.
+
+//! @brief Table of base addresses for AIPS instances.
+static const uint32_t __g_regs_AIPS_base_addresses[] = {
+        REGS_AIPS0_BASE,
+        REGS_AIPS1_BASE,
+    };
+
+//! @brief Get the base address of AIPS by instance number.
+//! @param x AIPS instance number, from 0 through 1.
+#define REGS_AIPS_BASE(x) (__g_regs_AIPS_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of AIPS.
+#define REGS_AIPS_INSTANCE(b) ((b) == REGS_AIPS0_BASE ? HW_AIPS0 : (b) == REGS_AIPS1_BASE ? HW_AIPS1 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_MPRA - Master Privilege Register A
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+typedef union _hw_aips_mpra
+{
+    uint32_t U;
+    struct _hw_aips_mpra_bitfields
+    {
+        uint32_t RESERVED0 : 8;        //!< [7:0]
+        uint32_t MPL5 : 1;             //!< [8] Master 5 Privilege Level
+        uint32_t MTW5 : 1;             //!< [9] Master 5 Trusted For Writes
+        uint32_t MTR5 : 1;             //!< [10] Master 5 Trusted For Read
+        uint32_t RESERVED1 : 1;        //!< [11]
+        uint32_t MPL4 : 1;             //!< [12] Master 4 Privilege Level
+        uint32_t MTW4 : 1;             //!< [13] Master 4 Trusted For Writes
+        uint32_t MTR4 : 1;             //!< [14] Master 4 Trusted For Read
+        uint32_t RESERVED2 : 1;        //!< [15]
+        uint32_t MPL3 : 1;             //!< [16] Master 3 Privilege Level
+        uint32_t MTW3 : 1;             //!< [17] Master 3 Trusted For Writes
+        uint32_t MTR3 : 1;             //!< [18] Master 3 Trusted For Read
+        uint32_t RESERVED3 : 1;        //!< [19]
+        uint32_t MPL2 : 1;             //!< [20] Master 2 Privilege Level
+        uint32_t MTW2 : 1;             //!< [21] Master 2 Trusted For Writes
+        uint32_t MTR2 : 1;             //!< [22] Master 2 Trusted For Read
+        uint32_t RESERVED4 : 1;        //!< [23]
+        uint32_t MPL1 : 1;             //!< [24] Master 1 Privilege Level
+        uint32_t MTW1 : 1;             //!< [25] Master 1 Trusted for Writes
+        uint32_t MTR1 : 1;             //!< [26] Master 1 Trusted for Read
+        uint32_t RESERVED5 : 1;        //!< [27]
+        uint32_t MPL0 : 1;             //!< [28] Master 0 Privilege Level
+        uint32_t MTW0 : 1;             //!< [29] Master 0 Trusted For Writes
+        uint32_t MTR0 : 1;             //!< [30] Master 0 Trusted For Read
+        uint32_t RESERVED6 : 1;        //!< [31]
+    } B;
+} hw_aips_mpra_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+//@{
+#define HW_AIPS_MPRA_ADDR(x)     (REGS_AIPS_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_MPRA(x)          (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x))
+#define HW_AIPS_MPRA_RD(x)       (HW_AIPS_MPRA(x).U)
+#define HW_AIPS_MPRA_WR(x, v)    (HW_AIPS_MPRA(x).U = (v))
+#define HW_AIPS_MPRA_SET(x, v)   (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) |  (v)))
+#define HW_AIPS_MPRA_CLR(x, v)   (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v)))
+#define HW_AIPS_MPRA_TOG(x, v)   (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL5    (8U)          //!< Bit position for AIPS_MPRA_MPL5.
+#define BM_AIPS_MPRA_MPL5    (0x00000100U) //!< Bit mask for AIPS_MPRA_MPL5.
+#define BS_AIPS_MPRA_MPL5    (1U)          //!< Bit field size in bits for AIPS_MPRA_MPL5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL5 field.
+#define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL5.
+#define BF_AIPS_MPRA_MPL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL5), uint32_t) & BM_AIPS_MPRA_MPL5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL5 field to a new value.
+#define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW5    (9U)          //!< Bit position for AIPS_MPRA_MTW5.
+#define BM_AIPS_MPRA_MTW5    (0x00000200U) //!< Bit mask for AIPS_MPRA_MTW5.
+#define BS_AIPS_MPRA_MTW5    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTW5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW5 field.
+#define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW5.
+#define BF_AIPS_MPRA_MTW5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW5), uint32_t) & BM_AIPS_MPRA_MTW5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW5 field to a new value.
+#define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR5    (10U)         //!< Bit position for AIPS_MPRA_MTR5.
+#define BM_AIPS_MPRA_MTR5    (0x00000400U) //!< Bit mask for AIPS_MPRA_MTR5.
+#define BS_AIPS_MPRA_MTR5    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTR5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR5 field.
+#define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR5.
+#define BF_AIPS_MPRA_MTR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR5), uint32_t) & BM_AIPS_MPRA_MTR5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR5 field to a new value.
+#define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL4    (12U)         //!< Bit position for AIPS_MPRA_MPL4.
+#define BM_AIPS_MPRA_MPL4    (0x00001000U) //!< Bit mask for AIPS_MPRA_MPL4.
+#define BS_AIPS_MPRA_MPL4    (1U)          //!< Bit field size in bits for AIPS_MPRA_MPL4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL4 field.
+#define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL4.
+#define BF_AIPS_MPRA_MPL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL4), uint32_t) & BM_AIPS_MPRA_MPL4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL4 field to a new value.
+#define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW4    (13U)         //!< Bit position for AIPS_MPRA_MTW4.
+#define BM_AIPS_MPRA_MTW4    (0x00002000U) //!< Bit mask for AIPS_MPRA_MTW4.
+#define BS_AIPS_MPRA_MTW4    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTW4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW4 field.
+#define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW4.
+#define BF_AIPS_MPRA_MTW4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW4), uint32_t) & BM_AIPS_MPRA_MTW4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW4 field to a new value.
+#define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR4    (14U)         //!< Bit position for AIPS_MPRA_MTR4.
+#define BM_AIPS_MPRA_MTR4    (0x00004000U) //!< Bit mask for AIPS_MPRA_MTR4.
+#define BS_AIPS_MPRA_MTR4    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTR4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR4 field.
+#define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR4.
+#define BF_AIPS_MPRA_MTR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR4), uint32_t) & BM_AIPS_MPRA_MTR4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR4 field to a new value.
+#define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL3    (16U)         //!< Bit position for AIPS_MPRA_MPL3.
+#define BM_AIPS_MPRA_MPL3    (0x00010000U) //!< Bit mask for AIPS_MPRA_MPL3.
+#define BS_AIPS_MPRA_MPL3    (1U)          //!< Bit field size in bits for AIPS_MPRA_MPL3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL3 field.
+#define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL3.
+#define BF_AIPS_MPRA_MPL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL3), uint32_t) & BM_AIPS_MPRA_MPL3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL3 field to a new value.
+#define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW3    (17U)         //!< Bit position for AIPS_MPRA_MTW3.
+#define BM_AIPS_MPRA_MTW3    (0x00020000U) //!< Bit mask for AIPS_MPRA_MTW3.
+#define BS_AIPS_MPRA_MTW3    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTW3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW3 field.
+#define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW3.
+#define BF_AIPS_MPRA_MTW3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW3), uint32_t) & BM_AIPS_MPRA_MTW3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW3 field to a new value.
+#define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR3    (18U)         //!< Bit position for AIPS_MPRA_MTR3.
+#define BM_AIPS_MPRA_MTR3    (0x00040000U) //!< Bit mask for AIPS_MPRA_MTR3.
+#define BS_AIPS_MPRA_MTR3    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTR3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR3 field.
+#define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR3.
+#define BF_AIPS_MPRA_MTR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR3), uint32_t) & BM_AIPS_MPRA_MTR3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR3 field to a new value.
+#define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL2    (20U)         //!< Bit position for AIPS_MPRA_MPL2.
+#define BM_AIPS_MPRA_MPL2    (0x00100000U) //!< Bit mask for AIPS_MPRA_MPL2.
+#define BS_AIPS_MPRA_MPL2    (1U)          //!< Bit field size in bits for AIPS_MPRA_MPL2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL2 field.
+#define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL2.
+#define BF_AIPS_MPRA_MPL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL2), uint32_t) & BM_AIPS_MPRA_MPL2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL2 field to a new value.
+#define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW2    (21U)         //!< Bit position for AIPS_MPRA_MTW2.
+#define BM_AIPS_MPRA_MTW2    (0x00200000U) //!< Bit mask for AIPS_MPRA_MTW2.
+#define BS_AIPS_MPRA_MTW2    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTW2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW2 field.
+#define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW2.
+#define BF_AIPS_MPRA_MTW2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW2), uint32_t) & BM_AIPS_MPRA_MTW2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW2 field to a new value.
+#define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR2    (22U)         //!< Bit position for AIPS_MPRA_MTR2.
+#define BM_AIPS_MPRA_MTR2    (0x00400000U) //!< Bit mask for AIPS_MPRA_MTR2.
+#define BS_AIPS_MPRA_MTR2    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR2 field.
+#define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR2.
+#define BF_AIPS_MPRA_MTR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR2), uint32_t) & BM_AIPS_MPRA_MTR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR2 field to a new value.
+#define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL1    (24U)         //!< Bit position for AIPS_MPRA_MPL1.
+#define BM_AIPS_MPRA_MPL1    (0x01000000U) //!< Bit mask for AIPS_MPRA_MPL1.
+#define BS_AIPS_MPRA_MPL1    (1U)          //!< Bit field size in bits for AIPS_MPRA_MPL1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL1 field.
+#define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL1.
+#define BF_AIPS_MPRA_MPL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL1), uint32_t) & BM_AIPS_MPRA_MPL1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL1 field to a new value.
+#define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW1    (25U)         //!< Bit position for AIPS_MPRA_MTW1.
+#define BM_AIPS_MPRA_MTW1    (0x02000000U) //!< Bit mask for AIPS_MPRA_MTW1.
+#define BS_AIPS_MPRA_MTW1    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTW1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW1 field.
+#define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW1.
+#define BF_AIPS_MPRA_MTW1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW1), uint32_t) & BM_AIPS_MPRA_MTW1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW1 field to a new value.
+#define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR1    (26U)         //!< Bit position for AIPS_MPRA_MTR1.
+#define BM_AIPS_MPRA_MTR1    (0x04000000U) //!< Bit mask for AIPS_MPRA_MTR1.
+#define BS_AIPS_MPRA_MTR1    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR1 field.
+#define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR1.
+#define BF_AIPS_MPRA_MTR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR1), uint32_t) & BM_AIPS_MPRA_MTR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR1 field to a new value.
+#define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL0    (28U)         //!< Bit position for AIPS_MPRA_MPL0.
+#define BM_AIPS_MPRA_MPL0    (0x10000000U) //!< Bit mask for AIPS_MPRA_MPL0.
+#define BS_AIPS_MPRA_MPL0    (1U)          //!< Bit field size in bits for AIPS_MPRA_MPL0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL0 field.
+#define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL0.
+#define BF_AIPS_MPRA_MPL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL0), uint32_t) & BM_AIPS_MPRA_MPL0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL0 field to a new value.
+#define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW0    (29U)         //!< Bit position for AIPS_MPRA_MTW0.
+#define BM_AIPS_MPRA_MTW0    (0x20000000U) //!< Bit mask for AIPS_MPRA_MTW0.
+#define BS_AIPS_MPRA_MTW0    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTW0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW0 field.
+#define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW0.
+#define BF_AIPS_MPRA_MTW0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW0), uint32_t) & BM_AIPS_MPRA_MTW0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW0 field to a new value.
+#define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR0    (30U)         //!< Bit position for AIPS_MPRA_MTR0.
+#define BM_AIPS_MPRA_MTR0    (0x40000000U) //!< Bit mask for AIPS_MPRA_MTR0.
+#define BS_AIPS_MPRA_MTR0    (1U)          //!< Bit field size in bits for AIPS_MPRA_MTR0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR0 field.
+#define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR0.
+#define BF_AIPS_MPRA_MTR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR0), uint32_t) & BM_AIPS_MPRA_MTR0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR0 field to a new value.
+#define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRA - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacra
+{
+    uint32_t U;
+    struct _hw_aips_pacra_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacra_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+//@{
+#define HW_AIPS_PACRA_ADDR(x)    (REGS_AIPS_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRA(x)         (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x))
+#define HW_AIPS_PACRA_RD(x)      (HW_AIPS_PACRA(x).U)
+#define HW_AIPS_PACRA_WR(x, v)   (HW_AIPS_PACRA(x).U = (v))
+#define HW_AIPS_PACRA_SET(x, v)  (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) |  (v)))
+#define HW_AIPS_PACRA_CLR(x, v)  (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v)))
+#define HW_AIPS_PACRA_TOG(x, v)  (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP7    (0U)          //!< Bit position for AIPS_PACRA_TP7.
+#define BM_AIPS_PACRA_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRA_TP7.
+#define BS_AIPS_PACRA_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP7 field.
+#define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP7.
+#define BF_AIPS_PACRA_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP7), uint32_t) & BM_AIPS_PACRA_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP7    (1U)          //!< Bit position for AIPS_PACRA_WP7.
+#define BM_AIPS_PACRA_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRA_WP7.
+#define BS_AIPS_PACRA_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP7 field.
+#define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP7.
+#define BF_AIPS_PACRA_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP7), uint32_t) & BM_AIPS_PACRA_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP7    (2U)          //!< Bit position for AIPS_PACRA_SP7.
+#define BM_AIPS_PACRA_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRA_SP7.
+#define BS_AIPS_PACRA_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP7 field.
+#define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP7.
+#define BF_AIPS_PACRA_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP7), uint32_t) & BM_AIPS_PACRA_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP6    (4U)          //!< Bit position for AIPS_PACRA_TP6.
+#define BM_AIPS_PACRA_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRA_TP6.
+#define BS_AIPS_PACRA_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP6 field.
+#define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP6.
+#define BF_AIPS_PACRA_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP6), uint32_t) & BM_AIPS_PACRA_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP6    (5U)          //!< Bit position for AIPS_PACRA_WP6.
+#define BM_AIPS_PACRA_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRA_WP6.
+#define BS_AIPS_PACRA_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP6 field.
+#define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP6.
+#define BF_AIPS_PACRA_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP6), uint32_t) & BM_AIPS_PACRA_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP6    (6U)          //!< Bit position for AIPS_PACRA_SP6.
+#define BM_AIPS_PACRA_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRA_SP6.
+#define BS_AIPS_PACRA_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP6 field.
+#define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP6.
+#define BF_AIPS_PACRA_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP6), uint32_t) & BM_AIPS_PACRA_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP5    (8U)          //!< Bit position for AIPS_PACRA_TP5.
+#define BM_AIPS_PACRA_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRA_TP5.
+#define BS_AIPS_PACRA_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP5 field.
+#define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP5.
+#define BF_AIPS_PACRA_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP5), uint32_t) & BM_AIPS_PACRA_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP5    (9U)          //!< Bit position for AIPS_PACRA_WP5.
+#define BM_AIPS_PACRA_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRA_WP5.
+#define BS_AIPS_PACRA_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP5 field.
+#define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP5.
+#define BF_AIPS_PACRA_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP5), uint32_t) & BM_AIPS_PACRA_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP5    (10U)         //!< Bit position for AIPS_PACRA_SP5.
+#define BM_AIPS_PACRA_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRA_SP5.
+#define BS_AIPS_PACRA_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP5 field.
+#define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP5.
+#define BF_AIPS_PACRA_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP5), uint32_t) & BM_AIPS_PACRA_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP4    (12U)         //!< Bit position for AIPS_PACRA_TP4.
+#define BM_AIPS_PACRA_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRA_TP4.
+#define BS_AIPS_PACRA_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP4 field.
+#define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP4.
+#define BF_AIPS_PACRA_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP4), uint32_t) & BM_AIPS_PACRA_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP4    (13U)         //!< Bit position for AIPS_PACRA_WP4.
+#define BM_AIPS_PACRA_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRA_WP4.
+#define BS_AIPS_PACRA_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP4 field.
+#define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP4.
+#define BF_AIPS_PACRA_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP4), uint32_t) & BM_AIPS_PACRA_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP4    (14U)         //!< Bit position for AIPS_PACRA_SP4.
+#define BM_AIPS_PACRA_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRA_SP4.
+#define BS_AIPS_PACRA_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP4 field.
+#define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP4.
+#define BF_AIPS_PACRA_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP4), uint32_t) & BM_AIPS_PACRA_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP3    (16U)         //!< Bit position for AIPS_PACRA_TP3.
+#define BM_AIPS_PACRA_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRA_TP3.
+#define BS_AIPS_PACRA_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP3 field.
+#define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP3.
+#define BF_AIPS_PACRA_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP3), uint32_t) & BM_AIPS_PACRA_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP3    (17U)         //!< Bit position for AIPS_PACRA_WP3.
+#define BM_AIPS_PACRA_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRA_WP3.
+#define BS_AIPS_PACRA_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP3 field.
+#define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP3.
+#define BF_AIPS_PACRA_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP3), uint32_t) & BM_AIPS_PACRA_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP3    (18U)         //!< Bit position for AIPS_PACRA_SP3.
+#define BM_AIPS_PACRA_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRA_SP3.
+#define BS_AIPS_PACRA_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP3 field.
+#define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP3.
+#define BF_AIPS_PACRA_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP3), uint32_t) & BM_AIPS_PACRA_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP2    (20U)         //!< Bit position for AIPS_PACRA_TP2.
+#define BM_AIPS_PACRA_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRA_TP2.
+#define BS_AIPS_PACRA_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP2 field.
+#define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP2.
+#define BF_AIPS_PACRA_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP2), uint32_t) & BM_AIPS_PACRA_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP2    (21U)         //!< Bit position for AIPS_PACRA_WP2.
+#define BM_AIPS_PACRA_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRA_WP2.
+#define BS_AIPS_PACRA_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP2 field.
+#define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP2.
+#define BF_AIPS_PACRA_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP2), uint32_t) & BM_AIPS_PACRA_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP2    (22U)         //!< Bit position for AIPS_PACRA_SP2.
+#define BM_AIPS_PACRA_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRA_SP2.
+#define BS_AIPS_PACRA_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP2 field.
+#define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP2.
+#define BF_AIPS_PACRA_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP2), uint32_t) & BM_AIPS_PACRA_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP1    (24U)         //!< Bit position for AIPS_PACRA_TP1.
+#define BM_AIPS_PACRA_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRA_TP1.
+#define BS_AIPS_PACRA_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP1 field.
+#define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP1.
+#define BF_AIPS_PACRA_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP1), uint32_t) & BM_AIPS_PACRA_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP1    (25U)         //!< Bit position for AIPS_PACRA_WP1.
+#define BM_AIPS_PACRA_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRA_WP1.
+#define BS_AIPS_PACRA_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP1 field.
+#define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP1.
+#define BF_AIPS_PACRA_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP1), uint32_t) & BM_AIPS_PACRA_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP1    (26U)         //!< Bit position for AIPS_PACRA_SP1.
+#define BM_AIPS_PACRA_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRA_SP1.
+#define BS_AIPS_PACRA_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP1 field.
+#define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP1.
+#define BF_AIPS_PACRA_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP1), uint32_t) & BM_AIPS_PACRA_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP0    (28U)         //!< Bit position for AIPS_PACRA_TP0.
+#define BM_AIPS_PACRA_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRA_TP0.
+#define BS_AIPS_PACRA_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRA_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP0 field.
+#define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP0.
+#define BF_AIPS_PACRA_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP0), uint32_t) & BM_AIPS_PACRA_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP0    (29U)         //!< Bit position for AIPS_PACRA_WP0.
+#define BM_AIPS_PACRA_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRA_WP0.
+#define BS_AIPS_PACRA_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRA_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP0 field.
+#define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP0.
+#define BF_AIPS_PACRA_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP0), uint32_t) & BM_AIPS_PACRA_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP0    (30U)         //!< Bit position for AIPS_PACRA_SP0.
+#define BM_AIPS_PACRA_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRA_SP0.
+#define BS_AIPS_PACRA_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRA_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP0 field.
+#define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP0.
+#define BF_AIPS_PACRA_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP0), uint32_t) & BM_AIPS_PACRA_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRB - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacrb
+{
+    uint32_t U;
+    struct _hw_aips_pacrb_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrb_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+//@{
+#define HW_AIPS_PACRB_ADDR(x)    (REGS_AIPS_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRB(x)         (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x))
+#define HW_AIPS_PACRB_RD(x)      (HW_AIPS_PACRB(x).U)
+#define HW_AIPS_PACRB_WR(x, v)   (HW_AIPS_PACRB(x).U = (v))
+#define HW_AIPS_PACRB_SET(x, v)  (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) |  (v)))
+#define HW_AIPS_PACRB_CLR(x, v)  (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v)))
+#define HW_AIPS_PACRB_TOG(x, v)  (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP7    (0U)          //!< Bit position for AIPS_PACRB_TP7.
+#define BM_AIPS_PACRB_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRB_TP7.
+#define BS_AIPS_PACRB_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP7 field.
+#define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP7.
+#define BF_AIPS_PACRB_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP7), uint32_t) & BM_AIPS_PACRB_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP7    (1U)          //!< Bit position for AIPS_PACRB_WP7.
+#define BM_AIPS_PACRB_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRB_WP7.
+#define BS_AIPS_PACRB_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP7 field.
+#define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP7.
+#define BF_AIPS_PACRB_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP7), uint32_t) & BM_AIPS_PACRB_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP7    (2U)          //!< Bit position for AIPS_PACRB_SP7.
+#define BM_AIPS_PACRB_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRB_SP7.
+#define BS_AIPS_PACRB_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP7 field.
+#define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP7.
+#define BF_AIPS_PACRB_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP7), uint32_t) & BM_AIPS_PACRB_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP6    (4U)          //!< Bit position for AIPS_PACRB_TP6.
+#define BM_AIPS_PACRB_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRB_TP6.
+#define BS_AIPS_PACRB_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP6 field.
+#define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP6.
+#define BF_AIPS_PACRB_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP6), uint32_t) & BM_AIPS_PACRB_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP6    (5U)          //!< Bit position for AIPS_PACRB_WP6.
+#define BM_AIPS_PACRB_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRB_WP6.
+#define BS_AIPS_PACRB_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP6 field.
+#define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP6.
+#define BF_AIPS_PACRB_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP6), uint32_t) & BM_AIPS_PACRB_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP6    (6U)          //!< Bit position for AIPS_PACRB_SP6.
+#define BM_AIPS_PACRB_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRB_SP6.
+#define BS_AIPS_PACRB_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP6 field.
+#define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP6.
+#define BF_AIPS_PACRB_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP6), uint32_t) & BM_AIPS_PACRB_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP5    (8U)          //!< Bit position for AIPS_PACRB_TP5.
+#define BM_AIPS_PACRB_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRB_TP5.
+#define BS_AIPS_PACRB_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP5 field.
+#define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP5.
+#define BF_AIPS_PACRB_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP5), uint32_t) & BM_AIPS_PACRB_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP5    (9U)          //!< Bit position for AIPS_PACRB_WP5.
+#define BM_AIPS_PACRB_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRB_WP5.
+#define BS_AIPS_PACRB_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP5 field.
+#define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP5.
+#define BF_AIPS_PACRB_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP5), uint32_t) & BM_AIPS_PACRB_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP5    (10U)         //!< Bit position for AIPS_PACRB_SP5.
+#define BM_AIPS_PACRB_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRB_SP5.
+#define BS_AIPS_PACRB_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP5 field.
+#define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP5.
+#define BF_AIPS_PACRB_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP5), uint32_t) & BM_AIPS_PACRB_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP4    (12U)         //!< Bit position for AIPS_PACRB_TP4.
+#define BM_AIPS_PACRB_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRB_TP4.
+#define BS_AIPS_PACRB_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP4 field.
+#define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP4.
+#define BF_AIPS_PACRB_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP4), uint32_t) & BM_AIPS_PACRB_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP4    (13U)         //!< Bit position for AIPS_PACRB_WP4.
+#define BM_AIPS_PACRB_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRB_WP4.
+#define BS_AIPS_PACRB_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP4 field.
+#define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP4.
+#define BF_AIPS_PACRB_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP4), uint32_t) & BM_AIPS_PACRB_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP4    (14U)         //!< Bit position for AIPS_PACRB_SP4.
+#define BM_AIPS_PACRB_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRB_SP4.
+#define BS_AIPS_PACRB_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP4 field.
+#define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP4.
+#define BF_AIPS_PACRB_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP4), uint32_t) & BM_AIPS_PACRB_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP3    (16U)         //!< Bit position for AIPS_PACRB_TP3.
+#define BM_AIPS_PACRB_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRB_TP3.
+#define BS_AIPS_PACRB_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP3 field.
+#define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP3.
+#define BF_AIPS_PACRB_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP3), uint32_t) & BM_AIPS_PACRB_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP3    (17U)         //!< Bit position for AIPS_PACRB_WP3.
+#define BM_AIPS_PACRB_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRB_WP3.
+#define BS_AIPS_PACRB_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP3 field.
+#define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP3.
+#define BF_AIPS_PACRB_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP3), uint32_t) & BM_AIPS_PACRB_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP3    (18U)         //!< Bit position for AIPS_PACRB_SP3.
+#define BM_AIPS_PACRB_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRB_SP3.
+#define BS_AIPS_PACRB_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP3 field.
+#define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP3.
+#define BF_AIPS_PACRB_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP3), uint32_t) & BM_AIPS_PACRB_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP2    (20U)         //!< Bit position for AIPS_PACRB_TP2.
+#define BM_AIPS_PACRB_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRB_TP2.
+#define BS_AIPS_PACRB_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP2 field.
+#define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP2.
+#define BF_AIPS_PACRB_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP2), uint32_t) & BM_AIPS_PACRB_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP2    (21U)         //!< Bit position for AIPS_PACRB_WP2.
+#define BM_AIPS_PACRB_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRB_WP2.
+#define BS_AIPS_PACRB_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP2 field.
+#define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP2.
+#define BF_AIPS_PACRB_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP2), uint32_t) & BM_AIPS_PACRB_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP2    (22U)         //!< Bit position for AIPS_PACRB_SP2.
+#define BM_AIPS_PACRB_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRB_SP2.
+#define BS_AIPS_PACRB_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP2 field.
+#define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP2.
+#define BF_AIPS_PACRB_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP2), uint32_t) & BM_AIPS_PACRB_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP1    (24U)         //!< Bit position for AIPS_PACRB_TP1.
+#define BM_AIPS_PACRB_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRB_TP1.
+#define BS_AIPS_PACRB_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP1 field.
+#define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP1.
+#define BF_AIPS_PACRB_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP1), uint32_t) & BM_AIPS_PACRB_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP1    (25U)         //!< Bit position for AIPS_PACRB_WP1.
+#define BM_AIPS_PACRB_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRB_WP1.
+#define BS_AIPS_PACRB_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP1 field.
+#define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP1.
+#define BF_AIPS_PACRB_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP1), uint32_t) & BM_AIPS_PACRB_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP1    (26U)         //!< Bit position for AIPS_PACRB_SP1.
+#define BM_AIPS_PACRB_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRB_SP1.
+#define BS_AIPS_PACRB_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP1 field.
+#define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP1.
+#define BF_AIPS_PACRB_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP1), uint32_t) & BM_AIPS_PACRB_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP0    (28U)         //!< Bit position for AIPS_PACRB_TP0.
+#define BM_AIPS_PACRB_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRB_TP0.
+#define BS_AIPS_PACRB_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRB_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP0 field.
+#define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP0.
+#define BF_AIPS_PACRB_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP0), uint32_t) & BM_AIPS_PACRB_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP0    (29U)         //!< Bit position for AIPS_PACRB_WP0.
+#define BM_AIPS_PACRB_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRB_WP0.
+#define BS_AIPS_PACRB_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRB_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP0 field.
+#define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP0.
+#define BF_AIPS_PACRB_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP0), uint32_t) & BM_AIPS_PACRB_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP0    (30U)         //!< Bit position for AIPS_PACRB_SP0.
+#define BM_AIPS_PACRB_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRB_SP0.
+#define BS_AIPS_PACRB_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRB_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP0 field.
+#define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP0.
+#define BF_AIPS_PACRB_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP0), uint32_t) & BM_AIPS_PACRB_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRC - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacrc
+{
+    uint32_t U;
+    struct _hw_aips_pacrc_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+//@{
+#define HW_AIPS_PACRC_ADDR(x)    (REGS_AIPS_BASE(x) + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRC(x)         (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x))
+#define HW_AIPS_PACRC_RD(x)      (HW_AIPS_PACRC(x).U)
+#define HW_AIPS_PACRC_WR(x, v)   (HW_AIPS_PACRC(x).U = (v))
+#define HW_AIPS_PACRC_SET(x, v)  (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) |  (v)))
+#define HW_AIPS_PACRC_CLR(x, v)  (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v)))
+#define HW_AIPS_PACRC_TOG(x, v)  (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP7    (0U)          //!< Bit position for AIPS_PACRC_TP7.
+#define BM_AIPS_PACRC_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRC_TP7.
+#define BS_AIPS_PACRC_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP7 field.
+#define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP7.
+#define BF_AIPS_PACRC_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP7), uint32_t) & BM_AIPS_PACRC_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP7    (1U)          //!< Bit position for AIPS_PACRC_WP7.
+#define BM_AIPS_PACRC_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRC_WP7.
+#define BS_AIPS_PACRC_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP7 field.
+#define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP7.
+#define BF_AIPS_PACRC_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP7), uint32_t) & BM_AIPS_PACRC_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP7    (2U)          //!< Bit position for AIPS_PACRC_SP7.
+#define BM_AIPS_PACRC_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRC_SP7.
+#define BS_AIPS_PACRC_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP7 field.
+#define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP7.
+#define BF_AIPS_PACRC_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP7), uint32_t) & BM_AIPS_PACRC_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP6    (4U)          //!< Bit position for AIPS_PACRC_TP6.
+#define BM_AIPS_PACRC_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRC_TP6.
+#define BS_AIPS_PACRC_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP6 field.
+#define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP6.
+#define BF_AIPS_PACRC_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP6), uint32_t) & BM_AIPS_PACRC_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP6    (5U)          //!< Bit position for AIPS_PACRC_WP6.
+#define BM_AIPS_PACRC_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRC_WP6.
+#define BS_AIPS_PACRC_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP6 field.
+#define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP6.
+#define BF_AIPS_PACRC_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP6), uint32_t) & BM_AIPS_PACRC_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP6    (6U)          //!< Bit position for AIPS_PACRC_SP6.
+#define BM_AIPS_PACRC_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRC_SP6.
+#define BS_AIPS_PACRC_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP6 field.
+#define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP6.
+#define BF_AIPS_PACRC_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP6), uint32_t) & BM_AIPS_PACRC_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP5    (8U)          //!< Bit position for AIPS_PACRC_TP5.
+#define BM_AIPS_PACRC_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRC_TP5.
+#define BS_AIPS_PACRC_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP5 field.
+#define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP5.
+#define BF_AIPS_PACRC_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP5), uint32_t) & BM_AIPS_PACRC_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP5    (9U)          //!< Bit position for AIPS_PACRC_WP5.
+#define BM_AIPS_PACRC_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRC_WP5.
+#define BS_AIPS_PACRC_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP5 field.
+#define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP5.
+#define BF_AIPS_PACRC_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP5), uint32_t) & BM_AIPS_PACRC_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP5    (10U)         //!< Bit position for AIPS_PACRC_SP5.
+#define BM_AIPS_PACRC_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRC_SP5.
+#define BS_AIPS_PACRC_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP5 field.
+#define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP5.
+#define BF_AIPS_PACRC_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP5), uint32_t) & BM_AIPS_PACRC_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP4    (12U)         //!< Bit position for AIPS_PACRC_TP4.
+#define BM_AIPS_PACRC_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRC_TP4.
+#define BS_AIPS_PACRC_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP4 field.
+#define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP4.
+#define BF_AIPS_PACRC_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP4), uint32_t) & BM_AIPS_PACRC_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP4    (13U)         //!< Bit position for AIPS_PACRC_WP4.
+#define BM_AIPS_PACRC_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRC_WP4.
+#define BS_AIPS_PACRC_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP4 field.
+#define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP4.
+#define BF_AIPS_PACRC_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP4), uint32_t) & BM_AIPS_PACRC_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP4    (14U)         //!< Bit position for AIPS_PACRC_SP4.
+#define BM_AIPS_PACRC_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRC_SP4.
+#define BS_AIPS_PACRC_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP4 field.
+#define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP4.
+#define BF_AIPS_PACRC_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP4), uint32_t) & BM_AIPS_PACRC_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP3    (16U)         //!< Bit position for AIPS_PACRC_TP3.
+#define BM_AIPS_PACRC_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRC_TP3.
+#define BS_AIPS_PACRC_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP3 field.
+#define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP3.
+#define BF_AIPS_PACRC_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP3), uint32_t) & BM_AIPS_PACRC_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP3    (17U)         //!< Bit position for AIPS_PACRC_WP3.
+#define BM_AIPS_PACRC_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRC_WP3.
+#define BS_AIPS_PACRC_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP3 field.
+#define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP3.
+#define BF_AIPS_PACRC_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP3), uint32_t) & BM_AIPS_PACRC_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP3    (18U)         //!< Bit position for AIPS_PACRC_SP3.
+#define BM_AIPS_PACRC_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRC_SP3.
+#define BS_AIPS_PACRC_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP3 field.
+#define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP3.
+#define BF_AIPS_PACRC_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP3), uint32_t) & BM_AIPS_PACRC_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP2    (20U)         //!< Bit position for AIPS_PACRC_TP2.
+#define BM_AIPS_PACRC_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRC_TP2.
+#define BS_AIPS_PACRC_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP2 field.
+#define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP2.
+#define BF_AIPS_PACRC_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP2), uint32_t) & BM_AIPS_PACRC_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP2    (21U)         //!< Bit position for AIPS_PACRC_WP2.
+#define BM_AIPS_PACRC_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRC_WP2.
+#define BS_AIPS_PACRC_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP2 field.
+#define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP2.
+#define BF_AIPS_PACRC_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP2), uint32_t) & BM_AIPS_PACRC_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP2    (22U)         //!< Bit position for AIPS_PACRC_SP2.
+#define BM_AIPS_PACRC_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRC_SP2.
+#define BS_AIPS_PACRC_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP2 field.
+#define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP2.
+#define BF_AIPS_PACRC_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP2), uint32_t) & BM_AIPS_PACRC_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP1    (24U)         //!< Bit position for AIPS_PACRC_TP1.
+#define BM_AIPS_PACRC_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRC_TP1.
+#define BS_AIPS_PACRC_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP1 field.
+#define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP1.
+#define BF_AIPS_PACRC_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP1), uint32_t) & BM_AIPS_PACRC_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP1    (25U)         //!< Bit position for AIPS_PACRC_WP1.
+#define BM_AIPS_PACRC_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRC_WP1.
+#define BS_AIPS_PACRC_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP1 field.
+#define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP1.
+#define BF_AIPS_PACRC_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP1), uint32_t) & BM_AIPS_PACRC_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP1    (26U)         //!< Bit position for AIPS_PACRC_SP1.
+#define BM_AIPS_PACRC_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRC_SP1.
+#define BS_AIPS_PACRC_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP1 field.
+#define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP1.
+#define BF_AIPS_PACRC_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP1), uint32_t) & BM_AIPS_PACRC_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP0    (28U)         //!< Bit position for AIPS_PACRC_TP0.
+#define BM_AIPS_PACRC_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRC_TP0.
+#define BS_AIPS_PACRC_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRC_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP0 field.
+#define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP0.
+#define BF_AIPS_PACRC_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP0), uint32_t) & BM_AIPS_PACRC_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP0    (29U)         //!< Bit position for AIPS_PACRC_WP0.
+#define BM_AIPS_PACRC_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRC_WP0.
+#define BS_AIPS_PACRC_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRC_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP0 field.
+#define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP0.
+#define BF_AIPS_PACRC_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP0), uint32_t) & BM_AIPS_PACRC_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP0    (30U)         //!< Bit position for AIPS_PACRC_SP0.
+#define BM_AIPS_PACRC_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRC_SP0.
+#define BS_AIPS_PACRC_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRC_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP0 field.
+#define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP0.
+#define BF_AIPS_PACRC_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP0), uint32_t) & BM_AIPS_PACRC_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRD - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacrd
+{
+    uint32_t U;
+    struct _hw_aips_pacrd_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+//@{
+#define HW_AIPS_PACRD_ADDR(x)    (REGS_AIPS_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRD(x)         (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x))
+#define HW_AIPS_PACRD_RD(x)      (HW_AIPS_PACRD(x).U)
+#define HW_AIPS_PACRD_WR(x, v)   (HW_AIPS_PACRD(x).U = (v))
+#define HW_AIPS_PACRD_SET(x, v)  (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) |  (v)))
+#define HW_AIPS_PACRD_CLR(x, v)  (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v)))
+#define HW_AIPS_PACRD_TOG(x, v)  (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP7    (0U)          //!< Bit position for AIPS_PACRD_TP7.
+#define BM_AIPS_PACRD_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRD_TP7.
+#define BS_AIPS_PACRD_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP7 field.
+#define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP7.
+#define BF_AIPS_PACRD_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP7), uint32_t) & BM_AIPS_PACRD_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP7    (1U)          //!< Bit position for AIPS_PACRD_WP7.
+#define BM_AIPS_PACRD_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRD_WP7.
+#define BS_AIPS_PACRD_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP7 field.
+#define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP7.
+#define BF_AIPS_PACRD_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP7), uint32_t) & BM_AIPS_PACRD_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP7    (2U)          //!< Bit position for AIPS_PACRD_SP7.
+#define BM_AIPS_PACRD_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRD_SP7.
+#define BS_AIPS_PACRD_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP7 field.
+#define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP7.
+#define BF_AIPS_PACRD_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP7), uint32_t) & BM_AIPS_PACRD_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP6    (4U)          //!< Bit position for AIPS_PACRD_TP6.
+#define BM_AIPS_PACRD_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRD_TP6.
+#define BS_AIPS_PACRD_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP6 field.
+#define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP6.
+#define BF_AIPS_PACRD_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP6), uint32_t) & BM_AIPS_PACRD_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP6    (5U)          //!< Bit position for AIPS_PACRD_WP6.
+#define BM_AIPS_PACRD_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRD_WP6.
+#define BS_AIPS_PACRD_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP6 field.
+#define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP6.
+#define BF_AIPS_PACRD_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP6), uint32_t) & BM_AIPS_PACRD_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP6    (6U)          //!< Bit position for AIPS_PACRD_SP6.
+#define BM_AIPS_PACRD_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRD_SP6.
+#define BS_AIPS_PACRD_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP6 field.
+#define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP6.
+#define BF_AIPS_PACRD_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP6), uint32_t) & BM_AIPS_PACRD_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP5    (8U)          //!< Bit position for AIPS_PACRD_TP5.
+#define BM_AIPS_PACRD_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRD_TP5.
+#define BS_AIPS_PACRD_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP5 field.
+#define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP5.
+#define BF_AIPS_PACRD_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP5), uint32_t) & BM_AIPS_PACRD_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP5    (9U)          //!< Bit position for AIPS_PACRD_WP5.
+#define BM_AIPS_PACRD_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRD_WP5.
+#define BS_AIPS_PACRD_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP5 field.
+#define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP5.
+#define BF_AIPS_PACRD_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP5), uint32_t) & BM_AIPS_PACRD_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP5    (10U)         //!< Bit position for AIPS_PACRD_SP5.
+#define BM_AIPS_PACRD_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRD_SP5.
+#define BS_AIPS_PACRD_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP5 field.
+#define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP5.
+#define BF_AIPS_PACRD_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP5), uint32_t) & BM_AIPS_PACRD_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP4    (12U)         //!< Bit position for AIPS_PACRD_TP4.
+#define BM_AIPS_PACRD_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRD_TP4.
+#define BS_AIPS_PACRD_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP4 field.
+#define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP4.
+#define BF_AIPS_PACRD_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP4), uint32_t) & BM_AIPS_PACRD_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP4    (13U)         //!< Bit position for AIPS_PACRD_WP4.
+#define BM_AIPS_PACRD_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRD_WP4.
+#define BS_AIPS_PACRD_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP4 field.
+#define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP4.
+#define BF_AIPS_PACRD_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP4), uint32_t) & BM_AIPS_PACRD_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP4    (14U)         //!< Bit position for AIPS_PACRD_SP4.
+#define BM_AIPS_PACRD_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRD_SP4.
+#define BS_AIPS_PACRD_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP4 field.
+#define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP4.
+#define BF_AIPS_PACRD_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP4), uint32_t) & BM_AIPS_PACRD_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP3    (16U)         //!< Bit position for AIPS_PACRD_TP3.
+#define BM_AIPS_PACRD_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRD_TP3.
+#define BS_AIPS_PACRD_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP3 field.
+#define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP3.
+#define BF_AIPS_PACRD_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP3), uint32_t) & BM_AIPS_PACRD_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP3    (17U)         //!< Bit position for AIPS_PACRD_WP3.
+#define BM_AIPS_PACRD_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRD_WP3.
+#define BS_AIPS_PACRD_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP3 field.
+#define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP3.
+#define BF_AIPS_PACRD_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP3), uint32_t) & BM_AIPS_PACRD_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP3    (18U)         //!< Bit position for AIPS_PACRD_SP3.
+#define BM_AIPS_PACRD_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRD_SP3.
+#define BS_AIPS_PACRD_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP3 field.
+#define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP3.
+#define BF_AIPS_PACRD_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP3), uint32_t) & BM_AIPS_PACRD_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP2    (20U)         //!< Bit position for AIPS_PACRD_TP2.
+#define BM_AIPS_PACRD_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRD_TP2.
+#define BS_AIPS_PACRD_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP2 field.
+#define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP2.
+#define BF_AIPS_PACRD_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP2), uint32_t) & BM_AIPS_PACRD_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP2    (21U)         //!< Bit position for AIPS_PACRD_WP2.
+#define BM_AIPS_PACRD_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRD_WP2.
+#define BS_AIPS_PACRD_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP2 field.
+#define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP2.
+#define BF_AIPS_PACRD_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP2), uint32_t) & BM_AIPS_PACRD_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP2    (22U)         //!< Bit position for AIPS_PACRD_SP2.
+#define BM_AIPS_PACRD_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRD_SP2.
+#define BS_AIPS_PACRD_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP2 field.
+#define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP2.
+#define BF_AIPS_PACRD_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP2), uint32_t) & BM_AIPS_PACRD_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP1    (24U)         //!< Bit position for AIPS_PACRD_TP1.
+#define BM_AIPS_PACRD_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRD_TP1.
+#define BS_AIPS_PACRD_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP1 field.
+#define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP1.
+#define BF_AIPS_PACRD_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP1), uint32_t) & BM_AIPS_PACRD_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP1    (25U)         //!< Bit position for AIPS_PACRD_WP1.
+#define BM_AIPS_PACRD_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRD_WP1.
+#define BS_AIPS_PACRD_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP1 field.
+#define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP1.
+#define BF_AIPS_PACRD_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP1), uint32_t) & BM_AIPS_PACRD_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP1    (26U)         //!< Bit position for AIPS_PACRD_SP1.
+#define BM_AIPS_PACRD_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRD_SP1.
+#define BS_AIPS_PACRD_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP1 field.
+#define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP1.
+#define BF_AIPS_PACRD_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP1), uint32_t) & BM_AIPS_PACRD_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP0    (28U)         //!< Bit position for AIPS_PACRD_TP0.
+#define BM_AIPS_PACRD_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRD_TP0.
+#define BS_AIPS_PACRD_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRD_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP0 field.
+#define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP0.
+#define BF_AIPS_PACRD_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP0), uint32_t) & BM_AIPS_PACRD_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP0    (29U)         //!< Bit position for AIPS_PACRD_WP0.
+#define BM_AIPS_PACRD_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRD_WP0.
+#define BS_AIPS_PACRD_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRD_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP0 field.
+#define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP0.
+#define BF_AIPS_PACRD_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP0), uint32_t) & BM_AIPS_PACRD_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP0    (30U)         //!< Bit position for AIPS_PACRD_SP0.
+#define BM_AIPS_PACRD_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRD_SP0.
+#define BS_AIPS_PACRD_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRD_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP0 field.
+#define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP0.
+#define BF_AIPS_PACRD_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP0), uint32_t) & BM_AIPS_PACRD_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRE - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacre
+{
+    uint32_t U;
+    struct _hw_aips_pacre_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacre_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+//@{
+#define HW_AIPS_PACRE_ADDR(x)    (REGS_AIPS_BASE(x) + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRE(x)         (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x))
+#define HW_AIPS_PACRE_RD(x)      (HW_AIPS_PACRE(x).U)
+#define HW_AIPS_PACRE_WR(x, v)   (HW_AIPS_PACRE(x).U = (v))
+#define HW_AIPS_PACRE_SET(x, v)  (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) |  (v)))
+#define HW_AIPS_PACRE_CLR(x, v)  (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v)))
+#define HW_AIPS_PACRE_TOG(x, v)  (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP7    (0U)          //!< Bit position for AIPS_PACRE_TP7.
+#define BM_AIPS_PACRE_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRE_TP7.
+#define BS_AIPS_PACRE_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP7 field.
+#define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP7.
+#define BF_AIPS_PACRE_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP7), uint32_t) & BM_AIPS_PACRE_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP7    (1U)          //!< Bit position for AIPS_PACRE_WP7.
+#define BM_AIPS_PACRE_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRE_WP7.
+#define BS_AIPS_PACRE_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP7 field.
+#define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP7.
+#define BF_AIPS_PACRE_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP7), uint32_t) & BM_AIPS_PACRE_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP7    (2U)          //!< Bit position for AIPS_PACRE_SP7.
+#define BM_AIPS_PACRE_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRE_SP7.
+#define BS_AIPS_PACRE_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP7 field.
+#define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP7.
+#define BF_AIPS_PACRE_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP7), uint32_t) & BM_AIPS_PACRE_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP6    (4U)          //!< Bit position for AIPS_PACRE_TP6.
+#define BM_AIPS_PACRE_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRE_TP6.
+#define BS_AIPS_PACRE_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP6 field.
+#define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP6.
+#define BF_AIPS_PACRE_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP6), uint32_t) & BM_AIPS_PACRE_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP6    (5U)          //!< Bit position for AIPS_PACRE_WP6.
+#define BM_AIPS_PACRE_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRE_WP6.
+#define BS_AIPS_PACRE_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP6 field.
+#define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP6.
+#define BF_AIPS_PACRE_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP6), uint32_t) & BM_AIPS_PACRE_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP6    (6U)          //!< Bit position for AIPS_PACRE_SP6.
+#define BM_AIPS_PACRE_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRE_SP6.
+#define BS_AIPS_PACRE_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP6 field.
+#define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP6.
+#define BF_AIPS_PACRE_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP6), uint32_t) & BM_AIPS_PACRE_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP5    (8U)          //!< Bit position for AIPS_PACRE_TP5.
+#define BM_AIPS_PACRE_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRE_TP5.
+#define BS_AIPS_PACRE_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP5 field.
+#define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP5.
+#define BF_AIPS_PACRE_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP5), uint32_t) & BM_AIPS_PACRE_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP5    (9U)          //!< Bit position for AIPS_PACRE_WP5.
+#define BM_AIPS_PACRE_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRE_WP5.
+#define BS_AIPS_PACRE_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP5 field.
+#define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP5.
+#define BF_AIPS_PACRE_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP5), uint32_t) & BM_AIPS_PACRE_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP5    (10U)         //!< Bit position for AIPS_PACRE_SP5.
+#define BM_AIPS_PACRE_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRE_SP5.
+#define BS_AIPS_PACRE_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP5 field.
+#define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP5.
+#define BF_AIPS_PACRE_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP5), uint32_t) & BM_AIPS_PACRE_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP4    (12U)         //!< Bit position for AIPS_PACRE_TP4.
+#define BM_AIPS_PACRE_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRE_TP4.
+#define BS_AIPS_PACRE_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP4 field.
+#define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP4.
+#define BF_AIPS_PACRE_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP4), uint32_t) & BM_AIPS_PACRE_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP4    (13U)         //!< Bit position for AIPS_PACRE_WP4.
+#define BM_AIPS_PACRE_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRE_WP4.
+#define BS_AIPS_PACRE_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP4 field.
+#define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP4.
+#define BF_AIPS_PACRE_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP4), uint32_t) & BM_AIPS_PACRE_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP4    (14U)         //!< Bit position for AIPS_PACRE_SP4.
+#define BM_AIPS_PACRE_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRE_SP4.
+#define BS_AIPS_PACRE_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP4 field.
+#define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP4.
+#define BF_AIPS_PACRE_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP4), uint32_t) & BM_AIPS_PACRE_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP3    (16U)         //!< Bit position for AIPS_PACRE_TP3.
+#define BM_AIPS_PACRE_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRE_TP3.
+#define BS_AIPS_PACRE_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP3 field.
+#define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP3.
+#define BF_AIPS_PACRE_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP3), uint32_t) & BM_AIPS_PACRE_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP3    (17U)         //!< Bit position for AIPS_PACRE_WP3.
+#define BM_AIPS_PACRE_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRE_WP3.
+#define BS_AIPS_PACRE_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP3 field.
+#define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP3.
+#define BF_AIPS_PACRE_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP3), uint32_t) & BM_AIPS_PACRE_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP3    (18U)         //!< Bit position for AIPS_PACRE_SP3.
+#define BM_AIPS_PACRE_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRE_SP3.
+#define BS_AIPS_PACRE_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP3 field.
+#define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP3.
+#define BF_AIPS_PACRE_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP3), uint32_t) & BM_AIPS_PACRE_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP2    (20U)         //!< Bit position for AIPS_PACRE_TP2.
+#define BM_AIPS_PACRE_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRE_TP2.
+#define BS_AIPS_PACRE_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP2 field.
+#define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP2.
+#define BF_AIPS_PACRE_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP2), uint32_t) & BM_AIPS_PACRE_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP2    (21U)         //!< Bit position for AIPS_PACRE_WP2.
+#define BM_AIPS_PACRE_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRE_WP2.
+#define BS_AIPS_PACRE_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP2 field.
+#define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP2.
+#define BF_AIPS_PACRE_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP2), uint32_t) & BM_AIPS_PACRE_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP2    (22U)         //!< Bit position for AIPS_PACRE_SP2.
+#define BM_AIPS_PACRE_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRE_SP2.
+#define BS_AIPS_PACRE_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP2 field.
+#define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP2.
+#define BF_AIPS_PACRE_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP2), uint32_t) & BM_AIPS_PACRE_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP1    (24U)         //!< Bit position for AIPS_PACRE_TP1.
+#define BM_AIPS_PACRE_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRE_TP1.
+#define BS_AIPS_PACRE_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP1 field.
+#define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP1.
+#define BF_AIPS_PACRE_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP1), uint32_t) & BM_AIPS_PACRE_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP1    (25U)         //!< Bit position for AIPS_PACRE_WP1.
+#define BM_AIPS_PACRE_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRE_WP1.
+#define BS_AIPS_PACRE_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP1 field.
+#define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP1.
+#define BF_AIPS_PACRE_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP1), uint32_t) & BM_AIPS_PACRE_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP1    (26U)         //!< Bit position for AIPS_PACRE_SP1.
+#define BM_AIPS_PACRE_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRE_SP1.
+#define BS_AIPS_PACRE_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP1 field.
+#define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP1.
+#define BF_AIPS_PACRE_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP1), uint32_t) & BM_AIPS_PACRE_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP0    (28U)         //!< Bit position for AIPS_PACRE_TP0.
+#define BM_AIPS_PACRE_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRE_TP0.
+#define BS_AIPS_PACRE_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRE_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP0 field.
+#define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP0.
+#define BF_AIPS_PACRE_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP0), uint32_t) & BM_AIPS_PACRE_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP0    (29U)         //!< Bit position for AIPS_PACRE_WP0.
+#define BM_AIPS_PACRE_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRE_WP0.
+#define BS_AIPS_PACRE_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRE_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP0 field.
+#define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP0.
+#define BF_AIPS_PACRE_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP0), uint32_t) & BM_AIPS_PACRE_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP0    (30U)         //!< Bit position for AIPS_PACRE_SP0.
+#define BM_AIPS_PACRE_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRE_SP0.
+#define BS_AIPS_PACRE_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRE_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP0 field.
+#define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP0.
+#define BF_AIPS_PACRE_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP0), uint32_t) & BM_AIPS_PACRE_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRF - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrf
+{
+    uint32_t U;
+    struct _hw_aips_pacrf_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrf_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+//@{
+#define HW_AIPS_PACRF_ADDR(x)    (REGS_AIPS_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRF(x)         (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x))
+#define HW_AIPS_PACRF_RD(x)      (HW_AIPS_PACRF(x).U)
+#define HW_AIPS_PACRF_WR(x, v)   (HW_AIPS_PACRF(x).U = (v))
+#define HW_AIPS_PACRF_SET(x, v)  (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) |  (v)))
+#define HW_AIPS_PACRF_CLR(x, v)  (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v)))
+#define HW_AIPS_PACRF_TOG(x, v)  (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP7    (0U)          //!< Bit position for AIPS_PACRF_TP7.
+#define BM_AIPS_PACRF_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRF_TP7.
+#define BS_AIPS_PACRF_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP7 field.
+#define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP7.
+#define BF_AIPS_PACRF_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP7), uint32_t) & BM_AIPS_PACRF_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP7    (1U)          //!< Bit position for AIPS_PACRF_WP7.
+#define BM_AIPS_PACRF_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRF_WP7.
+#define BS_AIPS_PACRF_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP7 field.
+#define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP7.
+#define BF_AIPS_PACRF_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP7), uint32_t) & BM_AIPS_PACRF_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP7    (2U)          //!< Bit position for AIPS_PACRF_SP7.
+#define BM_AIPS_PACRF_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRF_SP7.
+#define BS_AIPS_PACRF_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP7 field.
+#define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP7.
+#define BF_AIPS_PACRF_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP7), uint32_t) & BM_AIPS_PACRF_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP6    (4U)          //!< Bit position for AIPS_PACRF_TP6.
+#define BM_AIPS_PACRF_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRF_TP6.
+#define BS_AIPS_PACRF_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP6 field.
+#define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP6.
+#define BF_AIPS_PACRF_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP6), uint32_t) & BM_AIPS_PACRF_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP6    (5U)          //!< Bit position for AIPS_PACRF_WP6.
+#define BM_AIPS_PACRF_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRF_WP6.
+#define BS_AIPS_PACRF_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP6 field.
+#define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP6.
+#define BF_AIPS_PACRF_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP6), uint32_t) & BM_AIPS_PACRF_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP6    (6U)          //!< Bit position for AIPS_PACRF_SP6.
+#define BM_AIPS_PACRF_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRF_SP6.
+#define BS_AIPS_PACRF_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP6 field.
+#define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP6.
+#define BF_AIPS_PACRF_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP6), uint32_t) & BM_AIPS_PACRF_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP5    (8U)          //!< Bit position for AIPS_PACRF_TP5.
+#define BM_AIPS_PACRF_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRF_TP5.
+#define BS_AIPS_PACRF_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP5 field.
+#define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP5.
+#define BF_AIPS_PACRF_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP5), uint32_t) & BM_AIPS_PACRF_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP5    (9U)          //!< Bit position for AIPS_PACRF_WP5.
+#define BM_AIPS_PACRF_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRF_WP5.
+#define BS_AIPS_PACRF_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP5 field.
+#define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP5.
+#define BF_AIPS_PACRF_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP5), uint32_t) & BM_AIPS_PACRF_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP5    (10U)         //!< Bit position for AIPS_PACRF_SP5.
+#define BM_AIPS_PACRF_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRF_SP5.
+#define BS_AIPS_PACRF_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP5 field.
+#define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP5.
+#define BF_AIPS_PACRF_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP5), uint32_t) & BM_AIPS_PACRF_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP4    (12U)         //!< Bit position for AIPS_PACRF_TP4.
+#define BM_AIPS_PACRF_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRF_TP4.
+#define BS_AIPS_PACRF_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP4 field.
+#define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP4.
+#define BF_AIPS_PACRF_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP4), uint32_t) & BM_AIPS_PACRF_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP4    (13U)         //!< Bit position for AIPS_PACRF_WP4.
+#define BM_AIPS_PACRF_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRF_WP4.
+#define BS_AIPS_PACRF_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP4 field.
+#define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP4.
+#define BF_AIPS_PACRF_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP4), uint32_t) & BM_AIPS_PACRF_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP4    (14U)         //!< Bit position for AIPS_PACRF_SP4.
+#define BM_AIPS_PACRF_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRF_SP4.
+#define BS_AIPS_PACRF_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP4 field.
+#define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP4.
+#define BF_AIPS_PACRF_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP4), uint32_t) & BM_AIPS_PACRF_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP3    (16U)         //!< Bit position for AIPS_PACRF_TP3.
+#define BM_AIPS_PACRF_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRF_TP3.
+#define BS_AIPS_PACRF_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP3 field.
+#define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP3.
+#define BF_AIPS_PACRF_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP3), uint32_t) & BM_AIPS_PACRF_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP3    (17U)         //!< Bit position for AIPS_PACRF_WP3.
+#define BM_AIPS_PACRF_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRF_WP3.
+#define BS_AIPS_PACRF_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP3 field.
+#define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP3.
+#define BF_AIPS_PACRF_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP3), uint32_t) & BM_AIPS_PACRF_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP3    (18U)         //!< Bit position for AIPS_PACRF_SP3.
+#define BM_AIPS_PACRF_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRF_SP3.
+#define BS_AIPS_PACRF_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP3 field.
+#define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP3.
+#define BF_AIPS_PACRF_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP3), uint32_t) & BM_AIPS_PACRF_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP2    (20U)         //!< Bit position for AIPS_PACRF_TP2.
+#define BM_AIPS_PACRF_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRF_TP2.
+#define BS_AIPS_PACRF_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP2 field.
+#define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP2.
+#define BF_AIPS_PACRF_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP2), uint32_t) & BM_AIPS_PACRF_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP2    (21U)         //!< Bit position for AIPS_PACRF_WP2.
+#define BM_AIPS_PACRF_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRF_WP2.
+#define BS_AIPS_PACRF_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP2 field.
+#define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP2.
+#define BF_AIPS_PACRF_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP2), uint32_t) & BM_AIPS_PACRF_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP2    (22U)         //!< Bit position for AIPS_PACRF_SP2.
+#define BM_AIPS_PACRF_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRF_SP2.
+#define BS_AIPS_PACRF_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP2 field.
+#define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP2.
+#define BF_AIPS_PACRF_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP2), uint32_t) & BM_AIPS_PACRF_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP1    (24U)         //!< Bit position for AIPS_PACRF_TP1.
+#define BM_AIPS_PACRF_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRF_TP1.
+#define BS_AIPS_PACRF_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP1 field.
+#define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP1.
+#define BF_AIPS_PACRF_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP1), uint32_t) & BM_AIPS_PACRF_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP1    (25U)         //!< Bit position for AIPS_PACRF_WP1.
+#define BM_AIPS_PACRF_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRF_WP1.
+#define BS_AIPS_PACRF_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP1 field.
+#define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP1.
+#define BF_AIPS_PACRF_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP1), uint32_t) & BM_AIPS_PACRF_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP1    (26U)         //!< Bit position for AIPS_PACRF_SP1.
+#define BM_AIPS_PACRF_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRF_SP1.
+#define BS_AIPS_PACRF_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP1 field.
+#define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP1.
+#define BF_AIPS_PACRF_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP1), uint32_t) & BM_AIPS_PACRF_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP0    (28U)         //!< Bit position for AIPS_PACRF_TP0.
+#define BM_AIPS_PACRF_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRF_TP0.
+#define BS_AIPS_PACRF_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRF_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP0 field.
+#define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP0.
+#define BF_AIPS_PACRF_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP0), uint32_t) & BM_AIPS_PACRF_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP0    (29U)         //!< Bit position for AIPS_PACRF_WP0.
+#define BM_AIPS_PACRF_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRF_WP0.
+#define BS_AIPS_PACRF_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRF_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP0 field.
+#define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP0.
+#define BF_AIPS_PACRF_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP0), uint32_t) & BM_AIPS_PACRF_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP0    (30U)         //!< Bit position for AIPS_PACRF_SP0.
+#define BM_AIPS_PACRF_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRF_SP0.
+#define BS_AIPS_PACRF_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRF_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP0 field.
+#define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP0.
+#define BF_AIPS_PACRF_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP0), uint32_t) & BM_AIPS_PACRF_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRG - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrg
+{
+    uint32_t U;
+    struct _hw_aips_pacrg_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+//@{
+#define HW_AIPS_PACRG_ADDR(x)    (REGS_AIPS_BASE(x) + 0x48U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRG(x)         (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x))
+#define HW_AIPS_PACRG_RD(x)      (HW_AIPS_PACRG(x).U)
+#define HW_AIPS_PACRG_WR(x, v)   (HW_AIPS_PACRG(x).U = (v))
+#define HW_AIPS_PACRG_SET(x, v)  (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) |  (v)))
+#define HW_AIPS_PACRG_CLR(x, v)  (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v)))
+#define HW_AIPS_PACRG_TOG(x, v)  (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP7    (0U)          //!< Bit position for AIPS_PACRG_TP7.
+#define BM_AIPS_PACRG_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRG_TP7.
+#define BS_AIPS_PACRG_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP7 field.
+#define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP7.
+#define BF_AIPS_PACRG_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP7), uint32_t) & BM_AIPS_PACRG_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP7    (1U)          //!< Bit position for AIPS_PACRG_WP7.
+#define BM_AIPS_PACRG_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRG_WP7.
+#define BS_AIPS_PACRG_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP7 field.
+#define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP7.
+#define BF_AIPS_PACRG_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP7), uint32_t) & BM_AIPS_PACRG_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP7    (2U)          //!< Bit position for AIPS_PACRG_SP7.
+#define BM_AIPS_PACRG_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRG_SP7.
+#define BS_AIPS_PACRG_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP7 field.
+#define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP7.
+#define BF_AIPS_PACRG_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP7), uint32_t) & BM_AIPS_PACRG_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP6    (4U)          //!< Bit position for AIPS_PACRG_TP6.
+#define BM_AIPS_PACRG_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRG_TP6.
+#define BS_AIPS_PACRG_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP6 field.
+#define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP6.
+#define BF_AIPS_PACRG_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP6), uint32_t) & BM_AIPS_PACRG_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP6    (5U)          //!< Bit position for AIPS_PACRG_WP6.
+#define BM_AIPS_PACRG_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRG_WP6.
+#define BS_AIPS_PACRG_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP6 field.
+#define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP6.
+#define BF_AIPS_PACRG_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP6), uint32_t) & BM_AIPS_PACRG_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP6    (6U)          //!< Bit position for AIPS_PACRG_SP6.
+#define BM_AIPS_PACRG_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRG_SP6.
+#define BS_AIPS_PACRG_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP6 field.
+#define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP6.
+#define BF_AIPS_PACRG_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP6), uint32_t) & BM_AIPS_PACRG_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP5    (8U)          //!< Bit position for AIPS_PACRG_TP5.
+#define BM_AIPS_PACRG_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRG_TP5.
+#define BS_AIPS_PACRG_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP5 field.
+#define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP5.
+#define BF_AIPS_PACRG_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP5), uint32_t) & BM_AIPS_PACRG_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP5    (9U)          //!< Bit position for AIPS_PACRG_WP5.
+#define BM_AIPS_PACRG_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRG_WP5.
+#define BS_AIPS_PACRG_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP5 field.
+#define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP5.
+#define BF_AIPS_PACRG_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP5), uint32_t) & BM_AIPS_PACRG_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP5    (10U)         //!< Bit position for AIPS_PACRG_SP5.
+#define BM_AIPS_PACRG_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRG_SP5.
+#define BS_AIPS_PACRG_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP5 field.
+#define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP5.
+#define BF_AIPS_PACRG_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP5), uint32_t) & BM_AIPS_PACRG_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP4    (12U)         //!< Bit position for AIPS_PACRG_TP4.
+#define BM_AIPS_PACRG_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRG_TP4.
+#define BS_AIPS_PACRG_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP4 field.
+#define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP4.
+#define BF_AIPS_PACRG_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP4), uint32_t) & BM_AIPS_PACRG_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP4    (13U)         //!< Bit position for AIPS_PACRG_WP4.
+#define BM_AIPS_PACRG_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRG_WP4.
+#define BS_AIPS_PACRG_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP4 field.
+#define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP4.
+#define BF_AIPS_PACRG_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP4), uint32_t) & BM_AIPS_PACRG_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP4    (14U)         //!< Bit position for AIPS_PACRG_SP4.
+#define BM_AIPS_PACRG_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRG_SP4.
+#define BS_AIPS_PACRG_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP4 field.
+#define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP4.
+#define BF_AIPS_PACRG_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP4), uint32_t) & BM_AIPS_PACRG_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP3    (16U)         //!< Bit position for AIPS_PACRG_TP3.
+#define BM_AIPS_PACRG_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRG_TP3.
+#define BS_AIPS_PACRG_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP3 field.
+#define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP3.
+#define BF_AIPS_PACRG_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP3), uint32_t) & BM_AIPS_PACRG_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP3    (17U)         //!< Bit position for AIPS_PACRG_WP3.
+#define BM_AIPS_PACRG_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRG_WP3.
+#define BS_AIPS_PACRG_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP3 field.
+#define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP3.
+#define BF_AIPS_PACRG_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP3), uint32_t) & BM_AIPS_PACRG_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP3    (18U)         //!< Bit position for AIPS_PACRG_SP3.
+#define BM_AIPS_PACRG_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRG_SP3.
+#define BS_AIPS_PACRG_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP3 field.
+#define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP3.
+#define BF_AIPS_PACRG_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP3), uint32_t) & BM_AIPS_PACRG_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP2    (20U)         //!< Bit position for AIPS_PACRG_TP2.
+#define BM_AIPS_PACRG_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRG_TP2.
+#define BS_AIPS_PACRG_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP2 field.
+#define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP2.
+#define BF_AIPS_PACRG_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP2), uint32_t) & BM_AIPS_PACRG_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP2    (21U)         //!< Bit position for AIPS_PACRG_WP2.
+#define BM_AIPS_PACRG_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRG_WP2.
+#define BS_AIPS_PACRG_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP2 field.
+#define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP2.
+#define BF_AIPS_PACRG_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP2), uint32_t) & BM_AIPS_PACRG_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP2    (22U)         //!< Bit position for AIPS_PACRG_SP2.
+#define BM_AIPS_PACRG_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRG_SP2.
+#define BS_AIPS_PACRG_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP2 field.
+#define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP2.
+#define BF_AIPS_PACRG_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP2), uint32_t) & BM_AIPS_PACRG_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP1    (24U)         //!< Bit position for AIPS_PACRG_TP1.
+#define BM_AIPS_PACRG_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRG_TP1.
+#define BS_AIPS_PACRG_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP1 field.
+#define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP1.
+#define BF_AIPS_PACRG_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP1), uint32_t) & BM_AIPS_PACRG_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP1    (25U)         //!< Bit position for AIPS_PACRG_WP1.
+#define BM_AIPS_PACRG_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRG_WP1.
+#define BS_AIPS_PACRG_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP1 field.
+#define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP1.
+#define BF_AIPS_PACRG_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP1), uint32_t) & BM_AIPS_PACRG_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP1    (26U)         //!< Bit position for AIPS_PACRG_SP1.
+#define BM_AIPS_PACRG_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRG_SP1.
+#define BS_AIPS_PACRG_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP1 field.
+#define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP1.
+#define BF_AIPS_PACRG_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP1), uint32_t) & BM_AIPS_PACRG_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP0    (28U)         //!< Bit position for AIPS_PACRG_TP0.
+#define BM_AIPS_PACRG_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRG_TP0.
+#define BS_AIPS_PACRG_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRG_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP0 field.
+#define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP0.
+#define BF_AIPS_PACRG_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP0), uint32_t) & BM_AIPS_PACRG_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP0    (29U)         //!< Bit position for AIPS_PACRG_WP0.
+#define BM_AIPS_PACRG_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRG_WP0.
+#define BS_AIPS_PACRG_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRG_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP0 field.
+#define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP0.
+#define BF_AIPS_PACRG_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP0), uint32_t) & BM_AIPS_PACRG_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP0    (30U)         //!< Bit position for AIPS_PACRG_SP0.
+#define BM_AIPS_PACRG_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRG_SP0.
+#define BS_AIPS_PACRG_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRG_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP0 field.
+#define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP0.
+#define BF_AIPS_PACRG_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP0), uint32_t) & BM_AIPS_PACRG_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRH - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrh
+{
+    uint32_t U;
+    struct _hw_aips_pacrh_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+//@{
+#define HW_AIPS_PACRH_ADDR(x)    (REGS_AIPS_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRH(x)         (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x))
+#define HW_AIPS_PACRH_RD(x)      (HW_AIPS_PACRH(x).U)
+#define HW_AIPS_PACRH_WR(x, v)   (HW_AIPS_PACRH(x).U = (v))
+#define HW_AIPS_PACRH_SET(x, v)  (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) |  (v)))
+#define HW_AIPS_PACRH_CLR(x, v)  (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v)))
+#define HW_AIPS_PACRH_TOG(x, v)  (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP7    (0U)          //!< Bit position for AIPS_PACRH_TP7.
+#define BM_AIPS_PACRH_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRH_TP7.
+#define BS_AIPS_PACRH_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP7 field.
+#define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP7.
+#define BF_AIPS_PACRH_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP7), uint32_t) & BM_AIPS_PACRH_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP7    (1U)          //!< Bit position for AIPS_PACRH_WP7.
+#define BM_AIPS_PACRH_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRH_WP7.
+#define BS_AIPS_PACRH_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP7 field.
+#define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP7.
+#define BF_AIPS_PACRH_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP7), uint32_t) & BM_AIPS_PACRH_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP7    (2U)          //!< Bit position for AIPS_PACRH_SP7.
+#define BM_AIPS_PACRH_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRH_SP7.
+#define BS_AIPS_PACRH_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP7 field.
+#define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP7.
+#define BF_AIPS_PACRH_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP7), uint32_t) & BM_AIPS_PACRH_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP6    (4U)          //!< Bit position for AIPS_PACRH_TP6.
+#define BM_AIPS_PACRH_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRH_TP6.
+#define BS_AIPS_PACRH_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP6 field.
+#define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP6.
+#define BF_AIPS_PACRH_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP6), uint32_t) & BM_AIPS_PACRH_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP6    (5U)          //!< Bit position for AIPS_PACRH_WP6.
+#define BM_AIPS_PACRH_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRH_WP6.
+#define BS_AIPS_PACRH_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP6 field.
+#define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP6.
+#define BF_AIPS_PACRH_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP6), uint32_t) & BM_AIPS_PACRH_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP6    (6U)          //!< Bit position for AIPS_PACRH_SP6.
+#define BM_AIPS_PACRH_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRH_SP6.
+#define BS_AIPS_PACRH_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP6 field.
+#define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP6.
+#define BF_AIPS_PACRH_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP6), uint32_t) & BM_AIPS_PACRH_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP5    (8U)          //!< Bit position for AIPS_PACRH_TP5.
+#define BM_AIPS_PACRH_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRH_TP5.
+#define BS_AIPS_PACRH_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP5 field.
+#define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP5.
+#define BF_AIPS_PACRH_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP5), uint32_t) & BM_AIPS_PACRH_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP5    (9U)          //!< Bit position for AIPS_PACRH_WP5.
+#define BM_AIPS_PACRH_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRH_WP5.
+#define BS_AIPS_PACRH_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP5 field.
+#define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP5.
+#define BF_AIPS_PACRH_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP5), uint32_t) & BM_AIPS_PACRH_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP5    (10U)         //!< Bit position for AIPS_PACRH_SP5.
+#define BM_AIPS_PACRH_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRH_SP5.
+#define BS_AIPS_PACRH_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP5 field.
+#define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP5.
+#define BF_AIPS_PACRH_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP5), uint32_t) & BM_AIPS_PACRH_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP4    (12U)         //!< Bit position for AIPS_PACRH_TP4.
+#define BM_AIPS_PACRH_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRH_TP4.
+#define BS_AIPS_PACRH_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP4 field.
+#define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP4.
+#define BF_AIPS_PACRH_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP4), uint32_t) & BM_AIPS_PACRH_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP4    (13U)         //!< Bit position for AIPS_PACRH_WP4.
+#define BM_AIPS_PACRH_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRH_WP4.
+#define BS_AIPS_PACRH_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP4 field.
+#define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP4.
+#define BF_AIPS_PACRH_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP4), uint32_t) & BM_AIPS_PACRH_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP4    (14U)         //!< Bit position for AIPS_PACRH_SP4.
+#define BM_AIPS_PACRH_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRH_SP4.
+#define BS_AIPS_PACRH_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP4 field.
+#define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP4.
+#define BF_AIPS_PACRH_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP4), uint32_t) & BM_AIPS_PACRH_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP3    (16U)         //!< Bit position for AIPS_PACRH_TP3.
+#define BM_AIPS_PACRH_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRH_TP3.
+#define BS_AIPS_PACRH_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP3 field.
+#define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP3.
+#define BF_AIPS_PACRH_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP3), uint32_t) & BM_AIPS_PACRH_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP3    (17U)         //!< Bit position for AIPS_PACRH_WP3.
+#define BM_AIPS_PACRH_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRH_WP3.
+#define BS_AIPS_PACRH_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP3 field.
+#define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP3.
+#define BF_AIPS_PACRH_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP3), uint32_t) & BM_AIPS_PACRH_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP3    (18U)         //!< Bit position for AIPS_PACRH_SP3.
+#define BM_AIPS_PACRH_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRH_SP3.
+#define BS_AIPS_PACRH_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP3 field.
+#define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP3.
+#define BF_AIPS_PACRH_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP3), uint32_t) & BM_AIPS_PACRH_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP2    (20U)         //!< Bit position for AIPS_PACRH_TP2.
+#define BM_AIPS_PACRH_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRH_TP2.
+#define BS_AIPS_PACRH_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP2 field.
+#define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP2.
+#define BF_AIPS_PACRH_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP2), uint32_t) & BM_AIPS_PACRH_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP2    (21U)         //!< Bit position for AIPS_PACRH_WP2.
+#define BM_AIPS_PACRH_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRH_WP2.
+#define BS_AIPS_PACRH_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP2 field.
+#define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP2.
+#define BF_AIPS_PACRH_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP2), uint32_t) & BM_AIPS_PACRH_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP2    (22U)         //!< Bit position for AIPS_PACRH_SP2.
+#define BM_AIPS_PACRH_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRH_SP2.
+#define BS_AIPS_PACRH_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP2 field.
+#define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP2.
+#define BF_AIPS_PACRH_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP2), uint32_t) & BM_AIPS_PACRH_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP1    (24U)         //!< Bit position for AIPS_PACRH_TP1.
+#define BM_AIPS_PACRH_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRH_TP1.
+#define BS_AIPS_PACRH_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP1 field.
+#define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP1.
+#define BF_AIPS_PACRH_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP1), uint32_t) & BM_AIPS_PACRH_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP1    (25U)         //!< Bit position for AIPS_PACRH_WP1.
+#define BM_AIPS_PACRH_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRH_WP1.
+#define BS_AIPS_PACRH_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP1 field.
+#define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP1.
+#define BF_AIPS_PACRH_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP1), uint32_t) & BM_AIPS_PACRH_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP1    (26U)         //!< Bit position for AIPS_PACRH_SP1.
+#define BM_AIPS_PACRH_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRH_SP1.
+#define BS_AIPS_PACRH_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP1 field.
+#define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP1.
+#define BF_AIPS_PACRH_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP1), uint32_t) & BM_AIPS_PACRH_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP0    (28U)         //!< Bit position for AIPS_PACRH_TP0.
+#define BM_AIPS_PACRH_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRH_TP0.
+#define BS_AIPS_PACRH_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRH_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP0 field.
+#define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP0.
+#define BF_AIPS_PACRH_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP0), uint32_t) & BM_AIPS_PACRH_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP0    (29U)         //!< Bit position for AIPS_PACRH_WP0.
+#define BM_AIPS_PACRH_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRH_WP0.
+#define BS_AIPS_PACRH_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRH_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP0 field.
+#define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP0.
+#define BF_AIPS_PACRH_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP0), uint32_t) & BM_AIPS_PACRH_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP0    (30U)         //!< Bit position for AIPS_PACRH_SP0.
+#define BM_AIPS_PACRH_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRH_SP0.
+#define BS_AIPS_PACRH_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRH_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP0 field.
+#define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP0.
+#define BF_AIPS_PACRH_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP0), uint32_t) & BM_AIPS_PACRH_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRI - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacri
+{
+    uint32_t U;
+    struct _hw_aips_pacri_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacri_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+//@{
+#define HW_AIPS_PACRI_ADDR(x)    (REGS_AIPS_BASE(x) + 0x50U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRI(x)         (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x))
+#define HW_AIPS_PACRI_RD(x)      (HW_AIPS_PACRI(x).U)
+#define HW_AIPS_PACRI_WR(x, v)   (HW_AIPS_PACRI(x).U = (v))
+#define HW_AIPS_PACRI_SET(x, v)  (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) |  (v)))
+#define HW_AIPS_PACRI_CLR(x, v)  (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v)))
+#define HW_AIPS_PACRI_TOG(x, v)  (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP7    (0U)          //!< Bit position for AIPS_PACRI_TP7.
+#define BM_AIPS_PACRI_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRI_TP7.
+#define BS_AIPS_PACRI_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP7 field.
+#define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP7.
+#define BF_AIPS_PACRI_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP7), uint32_t) & BM_AIPS_PACRI_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP7    (1U)          //!< Bit position for AIPS_PACRI_WP7.
+#define BM_AIPS_PACRI_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRI_WP7.
+#define BS_AIPS_PACRI_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP7 field.
+#define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP7.
+#define BF_AIPS_PACRI_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP7), uint32_t) & BM_AIPS_PACRI_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP7    (2U)          //!< Bit position for AIPS_PACRI_SP7.
+#define BM_AIPS_PACRI_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRI_SP7.
+#define BS_AIPS_PACRI_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP7 field.
+#define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP7.
+#define BF_AIPS_PACRI_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP7), uint32_t) & BM_AIPS_PACRI_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP6    (4U)          //!< Bit position for AIPS_PACRI_TP6.
+#define BM_AIPS_PACRI_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRI_TP6.
+#define BS_AIPS_PACRI_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP6 field.
+#define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP6.
+#define BF_AIPS_PACRI_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP6), uint32_t) & BM_AIPS_PACRI_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP6    (5U)          //!< Bit position for AIPS_PACRI_WP6.
+#define BM_AIPS_PACRI_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRI_WP6.
+#define BS_AIPS_PACRI_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP6 field.
+#define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP6.
+#define BF_AIPS_PACRI_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP6), uint32_t) & BM_AIPS_PACRI_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP6    (6U)          //!< Bit position for AIPS_PACRI_SP6.
+#define BM_AIPS_PACRI_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRI_SP6.
+#define BS_AIPS_PACRI_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP6 field.
+#define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP6.
+#define BF_AIPS_PACRI_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP6), uint32_t) & BM_AIPS_PACRI_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP5    (8U)          //!< Bit position for AIPS_PACRI_TP5.
+#define BM_AIPS_PACRI_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRI_TP5.
+#define BS_AIPS_PACRI_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP5 field.
+#define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP5.
+#define BF_AIPS_PACRI_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP5), uint32_t) & BM_AIPS_PACRI_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP5    (9U)          //!< Bit position for AIPS_PACRI_WP5.
+#define BM_AIPS_PACRI_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRI_WP5.
+#define BS_AIPS_PACRI_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP5 field.
+#define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP5.
+#define BF_AIPS_PACRI_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP5), uint32_t) & BM_AIPS_PACRI_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP5    (10U)         //!< Bit position for AIPS_PACRI_SP5.
+#define BM_AIPS_PACRI_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRI_SP5.
+#define BS_AIPS_PACRI_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP5 field.
+#define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP5.
+#define BF_AIPS_PACRI_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP5), uint32_t) & BM_AIPS_PACRI_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP4    (12U)         //!< Bit position for AIPS_PACRI_TP4.
+#define BM_AIPS_PACRI_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRI_TP4.
+#define BS_AIPS_PACRI_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP4 field.
+#define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP4.
+#define BF_AIPS_PACRI_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP4), uint32_t) & BM_AIPS_PACRI_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP4    (13U)         //!< Bit position for AIPS_PACRI_WP4.
+#define BM_AIPS_PACRI_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRI_WP4.
+#define BS_AIPS_PACRI_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP4 field.
+#define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP4.
+#define BF_AIPS_PACRI_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP4), uint32_t) & BM_AIPS_PACRI_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP4    (14U)         //!< Bit position for AIPS_PACRI_SP4.
+#define BM_AIPS_PACRI_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRI_SP4.
+#define BS_AIPS_PACRI_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP4 field.
+#define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP4.
+#define BF_AIPS_PACRI_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP4), uint32_t) & BM_AIPS_PACRI_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP3    (16U)         //!< Bit position for AIPS_PACRI_TP3.
+#define BM_AIPS_PACRI_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRI_TP3.
+#define BS_AIPS_PACRI_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP3 field.
+#define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP3.
+#define BF_AIPS_PACRI_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP3), uint32_t) & BM_AIPS_PACRI_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP3    (17U)         //!< Bit position for AIPS_PACRI_WP3.
+#define BM_AIPS_PACRI_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRI_WP3.
+#define BS_AIPS_PACRI_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP3 field.
+#define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP3.
+#define BF_AIPS_PACRI_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP3), uint32_t) & BM_AIPS_PACRI_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP3    (18U)         //!< Bit position for AIPS_PACRI_SP3.
+#define BM_AIPS_PACRI_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRI_SP3.
+#define BS_AIPS_PACRI_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP3 field.
+#define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP3.
+#define BF_AIPS_PACRI_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP3), uint32_t) & BM_AIPS_PACRI_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP2    (20U)         //!< Bit position for AIPS_PACRI_TP2.
+#define BM_AIPS_PACRI_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRI_TP2.
+#define BS_AIPS_PACRI_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP2 field.
+#define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP2.
+#define BF_AIPS_PACRI_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP2), uint32_t) & BM_AIPS_PACRI_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP2    (21U)         //!< Bit position for AIPS_PACRI_WP2.
+#define BM_AIPS_PACRI_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRI_WP2.
+#define BS_AIPS_PACRI_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP2 field.
+#define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP2.
+#define BF_AIPS_PACRI_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP2), uint32_t) & BM_AIPS_PACRI_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP2    (22U)         //!< Bit position for AIPS_PACRI_SP2.
+#define BM_AIPS_PACRI_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRI_SP2.
+#define BS_AIPS_PACRI_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP2 field.
+#define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP2.
+#define BF_AIPS_PACRI_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP2), uint32_t) & BM_AIPS_PACRI_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP1    (24U)         //!< Bit position for AIPS_PACRI_TP1.
+#define BM_AIPS_PACRI_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRI_TP1.
+#define BS_AIPS_PACRI_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP1 field.
+#define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP1.
+#define BF_AIPS_PACRI_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP1), uint32_t) & BM_AIPS_PACRI_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP1    (25U)         //!< Bit position for AIPS_PACRI_WP1.
+#define BM_AIPS_PACRI_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRI_WP1.
+#define BS_AIPS_PACRI_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP1 field.
+#define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP1.
+#define BF_AIPS_PACRI_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP1), uint32_t) & BM_AIPS_PACRI_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP1    (26U)         //!< Bit position for AIPS_PACRI_SP1.
+#define BM_AIPS_PACRI_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRI_SP1.
+#define BS_AIPS_PACRI_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP1 field.
+#define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP1.
+#define BF_AIPS_PACRI_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP1), uint32_t) & BM_AIPS_PACRI_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP0    (28U)         //!< Bit position for AIPS_PACRI_TP0.
+#define BM_AIPS_PACRI_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRI_TP0.
+#define BS_AIPS_PACRI_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRI_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP0 field.
+#define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP0.
+#define BF_AIPS_PACRI_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP0), uint32_t) & BM_AIPS_PACRI_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP0    (29U)         //!< Bit position for AIPS_PACRI_WP0.
+#define BM_AIPS_PACRI_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRI_WP0.
+#define BS_AIPS_PACRI_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRI_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP0 field.
+#define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP0.
+#define BF_AIPS_PACRI_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP0), uint32_t) & BM_AIPS_PACRI_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP0    (30U)         //!< Bit position for AIPS_PACRI_SP0.
+#define BM_AIPS_PACRI_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRI_SP0.
+#define BS_AIPS_PACRI_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRI_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP0 field.
+#define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP0.
+#define BF_AIPS_PACRI_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP0), uint32_t) & BM_AIPS_PACRI_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRJ - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrj
+{
+    uint32_t U;
+    struct _hw_aips_pacrj_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrj_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+//@{
+#define HW_AIPS_PACRJ_ADDR(x)    (REGS_AIPS_BASE(x) + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRJ(x)         (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x))
+#define HW_AIPS_PACRJ_RD(x)      (HW_AIPS_PACRJ(x).U)
+#define HW_AIPS_PACRJ_WR(x, v)   (HW_AIPS_PACRJ(x).U = (v))
+#define HW_AIPS_PACRJ_SET(x, v)  (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) |  (v)))
+#define HW_AIPS_PACRJ_CLR(x, v)  (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v)))
+#define HW_AIPS_PACRJ_TOG(x, v)  (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP7    (0U)          //!< Bit position for AIPS_PACRJ_TP7.
+#define BM_AIPS_PACRJ_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRJ_TP7.
+#define BS_AIPS_PACRJ_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP7 field.
+#define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP7.
+#define BF_AIPS_PACRJ_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP7), uint32_t) & BM_AIPS_PACRJ_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP7    (1U)          //!< Bit position for AIPS_PACRJ_WP7.
+#define BM_AIPS_PACRJ_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRJ_WP7.
+#define BS_AIPS_PACRJ_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP7 field.
+#define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP7.
+#define BF_AIPS_PACRJ_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP7), uint32_t) & BM_AIPS_PACRJ_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP7    (2U)          //!< Bit position for AIPS_PACRJ_SP7.
+#define BM_AIPS_PACRJ_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRJ_SP7.
+#define BS_AIPS_PACRJ_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP7 field.
+#define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP7.
+#define BF_AIPS_PACRJ_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP7), uint32_t) & BM_AIPS_PACRJ_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP6    (4U)          //!< Bit position for AIPS_PACRJ_TP6.
+#define BM_AIPS_PACRJ_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRJ_TP6.
+#define BS_AIPS_PACRJ_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP6 field.
+#define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP6.
+#define BF_AIPS_PACRJ_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP6), uint32_t) & BM_AIPS_PACRJ_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP6    (5U)          //!< Bit position for AIPS_PACRJ_WP6.
+#define BM_AIPS_PACRJ_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRJ_WP6.
+#define BS_AIPS_PACRJ_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP6 field.
+#define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP6.
+#define BF_AIPS_PACRJ_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP6), uint32_t) & BM_AIPS_PACRJ_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP6    (6U)          //!< Bit position for AIPS_PACRJ_SP6.
+#define BM_AIPS_PACRJ_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRJ_SP6.
+#define BS_AIPS_PACRJ_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP6 field.
+#define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP6.
+#define BF_AIPS_PACRJ_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP6), uint32_t) & BM_AIPS_PACRJ_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP5    (8U)          //!< Bit position for AIPS_PACRJ_TP5.
+#define BM_AIPS_PACRJ_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRJ_TP5.
+#define BS_AIPS_PACRJ_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP5 field.
+#define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP5.
+#define BF_AIPS_PACRJ_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP5), uint32_t) & BM_AIPS_PACRJ_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP5    (9U)          //!< Bit position for AIPS_PACRJ_WP5.
+#define BM_AIPS_PACRJ_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRJ_WP5.
+#define BS_AIPS_PACRJ_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP5 field.
+#define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP5.
+#define BF_AIPS_PACRJ_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP5), uint32_t) & BM_AIPS_PACRJ_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP5    (10U)         //!< Bit position for AIPS_PACRJ_SP5.
+#define BM_AIPS_PACRJ_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRJ_SP5.
+#define BS_AIPS_PACRJ_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP5 field.
+#define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP5.
+#define BF_AIPS_PACRJ_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP5), uint32_t) & BM_AIPS_PACRJ_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP4    (12U)         //!< Bit position for AIPS_PACRJ_TP4.
+#define BM_AIPS_PACRJ_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRJ_TP4.
+#define BS_AIPS_PACRJ_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP4 field.
+#define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP4.
+#define BF_AIPS_PACRJ_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP4), uint32_t) & BM_AIPS_PACRJ_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP4    (13U)         //!< Bit position for AIPS_PACRJ_WP4.
+#define BM_AIPS_PACRJ_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRJ_WP4.
+#define BS_AIPS_PACRJ_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP4 field.
+#define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP4.
+#define BF_AIPS_PACRJ_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP4), uint32_t) & BM_AIPS_PACRJ_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP4    (14U)         //!< Bit position for AIPS_PACRJ_SP4.
+#define BM_AIPS_PACRJ_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRJ_SP4.
+#define BS_AIPS_PACRJ_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP4 field.
+#define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP4.
+#define BF_AIPS_PACRJ_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP4), uint32_t) & BM_AIPS_PACRJ_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP3    (16U)         //!< Bit position for AIPS_PACRJ_TP3.
+#define BM_AIPS_PACRJ_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRJ_TP3.
+#define BS_AIPS_PACRJ_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP3 field.
+#define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP3.
+#define BF_AIPS_PACRJ_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP3), uint32_t) & BM_AIPS_PACRJ_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP3    (17U)         //!< Bit position for AIPS_PACRJ_WP3.
+#define BM_AIPS_PACRJ_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRJ_WP3.
+#define BS_AIPS_PACRJ_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP3 field.
+#define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP3.
+#define BF_AIPS_PACRJ_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP3), uint32_t) & BM_AIPS_PACRJ_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP3    (18U)         //!< Bit position for AIPS_PACRJ_SP3.
+#define BM_AIPS_PACRJ_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRJ_SP3.
+#define BS_AIPS_PACRJ_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP3 field.
+#define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP3.
+#define BF_AIPS_PACRJ_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP3), uint32_t) & BM_AIPS_PACRJ_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP2    (20U)         //!< Bit position for AIPS_PACRJ_TP2.
+#define BM_AIPS_PACRJ_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRJ_TP2.
+#define BS_AIPS_PACRJ_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP2 field.
+#define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP2.
+#define BF_AIPS_PACRJ_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP2), uint32_t) & BM_AIPS_PACRJ_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP2    (21U)         //!< Bit position for AIPS_PACRJ_WP2.
+#define BM_AIPS_PACRJ_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRJ_WP2.
+#define BS_AIPS_PACRJ_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP2 field.
+#define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP2.
+#define BF_AIPS_PACRJ_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP2), uint32_t) & BM_AIPS_PACRJ_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP2    (22U)         //!< Bit position for AIPS_PACRJ_SP2.
+#define BM_AIPS_PACRJ_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRJ_SP2.
+#define BS_AIPS_PACRJ_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP2 field.
+#define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP2.
+#define BF_AIPS_PACRJ_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP2), uint32_t) & BM_AIPS_PACRJ_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP1    (24U)         //!< Bit position for AIPS_PACRJ_TP1.
+#define BM_AIPS_PACRJ_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRJ_TP1.
+#define BS_AIPS_PACRJ_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP1 field.
+#define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP1.
+#define BF_AIPS_PACRJ_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP1), uint32_t) & BM_AIPS_PACRJ_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP1    (25U)         //!< Bit position for AIPS_PACRJ_WP1.
+#define BM_AIPS_PACRJ_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRJ_WP1.
+#define BS_AIPS_PACRJ_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP1 field.
+#define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP1.
+#define BF_AIPS_PACRJ_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP1), uint32_t) & BM_AIPS_PACRJ_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP1    (26U)         //!< Bit position for AIPS_PACRJ_SP1.
+#define BM_AIPS_PACRJ_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRJ_SP1.
+#define BS_AIPS_PACRJ_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP1 field.
+#define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP1.
+#define BF_AIPS_PACRJ_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP1), uint32_t) & BM_AIPS_PACRJ_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP0    (28U)         //!< Bit position for AIPS_PACRJ_TP0.
+#define BM_AIPS_PACRJ_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRJ_TP0.
+#define BS_AIPS_PACRJ_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRJ_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP0 field.
+#define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP0.
+#define BF_AIPS_PACRJ_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP0), uint32_t) & BM_AIPS_PACRJ_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP0    (29U)         //!< Bit position for AIPS_PACRJ_WP0.
+#define BM_AIPS_PACRJ_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRJ_WP0.
+#define BS_AIPS_PACRJ_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRJ_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP0 field.
+#define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP0.
+#define BF_AIPS_PACRJ_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP0), uint32_t) & BM_AIPS_PACRJ_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP0    (30U)         //!< Bit position for AIPS_PACRJ_SP0.
+#define BM_AIPS_PACRJ_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRJ_SP0.
+#define BS_AIPS_PACRJ_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRJ_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP0 field.
+#define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP0.
+#define BF_AIPS_PACRJ_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP0), uint32_t) & BM_AIPS_PACRJ_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRK - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrk
+{
+    uint32_t U;
+    struct _hw_aips_pacrk_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrk_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+//@{
+#define HW_AIPS_PACRK_ADDR(x)    (REGS_AIPS_BASE(x) + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRK(x)         (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x))
+#define HW_AIPS_PACRK_RD(x)      (HW_AIPS_PACRK(x).U)
+#define HW_AIPS_PACRK_WR(x, v)   (HW_AIPS_PACRK(x).U = (v))
+#define HW_AIPS_PACRK_SET(x, v)  (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) |  (v)))
+#define HW_AIPS_PACRK_CLR(x, v)  (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v)))
+#define HW_AIPS_PACRK_TOG(x, v)  (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP7    (0U)          //!< Bit position for AIPS_PACRK_TP7.
+#define BM_AIPS_PACRK_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRK_TP7.
+#define BS_AIPS_PACRK_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP7 field.
+#define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP7.
+#define BF_AIPS_PACRK_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP7), uint32_t) & BM_AIPS_PACRK_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP7    (1U)          //!< Bit position for AIPS_PACRK_WP7.
+#define BM_AIPS_PACRK_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRK_WP7.
+#define BS_AIPS_PACRK_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP7 field.
+#define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP7.
+#define BF_AIPS_PACRK_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP7), uint32_t) & BM_AIPS_PACRK_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP7    (2U)          //!< Bit position for AIPS_PACRK_SP7.
+#define BM_AIPS_PACRK_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRK_SP7.
+#define BS_AIPS_PACRK_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP7 field.
+#define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP7.
+#define BF_AIPS_PACRK_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP7), uint32_t) & BM_AIPS_PACRK_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP6    (4U)          //!< Bit position for AIPS_PACRK_TP6.
+#define BM_AIPS_PACRK_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRK_TP6.
+#define BS_AIPS_PACRK_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP6 field.
+#define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP6.
+#define BF_AIPS_PACRK_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP6), uint32_t) & BM_AIPS_PACRK_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP6    (5U)          //!< Bit position for AIPS_PACRK_WP6.
+#define BM_AIPS_PACRK_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRK_WP6.
+#define BS_AIPS_PACRK_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP6 field.
+#define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP6.
+#define BF_AIPS_PACRK_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP6), uint32_t) & BM_AIPS_PACRK_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP6    (6U)          //!< Bit position for AIPS_PACRK_SP6.
+#define BM_AIPS_PACRK_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRK_SP6.
+#define BS_AIPS_PACRK_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP6 field.
+#define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP6.
+#define BF_AIPS_PACRK_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP6), uint32_t) & BM_AIPS_PACRK_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP5    (8U)          //!< Bit position for AIPS_PACRK_TP5.
+#define BM_AIPS_PACRK_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRK_TP5.
+#define BS_AIPS_PACRK_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP5 field.
+#define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP5.
+#define BF_AIPS_PACRK_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP5), uint32_t) & BM_AIPS_PACRK_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP5    (9U)          //!< Bit position for AIPS_PACRK_WP5.
+#define BM_AIPS_PACRK_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRK_WP5.
+#define BS_AIPS_PACRK_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP5 field.
+#define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP5.
+#define BF_AIPS_PACRK_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP5), uint32_t) & BM_AIPS_PACRK_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP5    (10U)         //!< Bit position for AIPS_PACRK_SP5.
+#define BM_AIPS_PACRK_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRK_SP5.
+#define BS_AIPS_PACRK_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP5 field.
+#define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP5.
+#define BF_AIPS_PACRK_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP5), uint32_t) & BM_AIPS_PACRK_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP4    (12U)         //!< Bit position for AIPS_PACRK_TP4.
+#define BM_AIPS_PACRK_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRK_TP4.
+#define BS_AIPS_PACRK_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP4 field.
+#define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP4.
+#define BF_AIPS_PACRK_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP4), uint32_t) & BM_AIPS_PACRK_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP4    (13U)         //!< Bit position for AIPS_PACRK_WP4.
+#define BM_AIPS_PACRK_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRK_WP4.
+#define BS_AIPS_PACRK_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP4 field.
+#define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP4.
+#define BF_AIPS_PACRK_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP4), uint32_t) & BM_AIPS_PACRK_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP4    (14U)         //!< Bit position for AIPS_PACRK_SP4.
+#define BM_AIPS_PACRK_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRK_SP4.
+#define BS_AIPS_PACRK_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP4 field.
+#define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP4.
+#define BF_AIPS_PACRK_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP4), uint32_t) & BM_AIPS_PACRK_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP3    (16U)         //!< Bit position for AIPS_PACRK_TP3.
+#define BM_AIPS_PACRK_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRK_TP3.
+#define BS_AIPS_PACRK_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP3 field.
+#define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP3.
+#define BF_AIPS_PACRK_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP3), uint32_t) & BM_AIPS_PACRK_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP3    (17U)         //!< Bit position for AIPS_PACRK_WP3.
+#define BM_AIPS_PACRK_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRK_WP3.
+#define BS_AIPS_PACRK_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP3 field.
+#define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP3.
+#define BF_AIPS_PACRK_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP3), uint32_t) & BM_AIPS_PACRK_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP3    (18U)         //!< Bit position for AIPS_PACRK_SP3.
+#define BM_AIPS_PACRK_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRK_SP3.
+#define BS_AIPS_PACRK_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP3 field.
+#define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP3.
+#define BF_AIPS_PACRK_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP3), uint32_t) & BM_AIPS_PACRK_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP2    (20U)         //!< Bit position for AIPS_PACRK_TP2.
+#define BM_AIPS_PACRK_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRK_TP2.
+#define BS_AIPS_PACRK_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP2 field.
+#define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP2.
+#define BF_AIPS_PACRK_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP2), uint32_t) & BM_AIPS_PACRK_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP2    (21U)         //!< Bit position for AIPS_PACRK_WP2.
+#define BM_AIPS_PACRK_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRK_WP2.
+#define BS_AIPS_PACRK_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP2 field.
+#define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP2.
+#define BF_AIPS_PACRK_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP2), uint32_t) & BM_AIPS_PACRK_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP2    (22U)         //!< Bit position for AIPS_PACRK_SP2.
+#define BM_AIPS_PACRK_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRK_SP2.
+#define BS_AIPS_PACRK_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP2 field.
+#define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP2.
+#define BF_AIPS_PACRK_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP2), uint32_t) & BM_AIPS_PACRK_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP1    (24U)         //!< Bit position for AIPS_PACRK_TP1.
+#define BM_AIPS_PACRK_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRK_TP1.
+#define BS_AIPS_PACRK_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP1 field.
+#define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP1.
+#define BF_AIPS_PACRK_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP1), uint32_t) & BM_AIPS_PACRK_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP1    (25U)         //!< Bit position for AIPS_PACRK_WP1.
+#define BM_AIPS_PACRK_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRK_WP1.
+#define BS_AIPS_PACRK_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP1 field.
+#define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP1.
+#define BF_AIPS_PACRK_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP1), uint32_t) & BM_AIPS_PACRK_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP1    (26U)         //!< Bit position for AIPS_PACRK_SP1.
+#define BM_AIPS_PACRK_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRK_SP1.
+#define BS_AIPS_PACRK_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP1 field.
+#define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP1.
+#define BF_AIPS_PACRK_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP1), uint32_t) & BM_AIPS_PACRK_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP0    (28U)         //!< Bit position for AIPS_PACRK_TP0.
+#define BM_AIPS_PACRK_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRK_TP0.
+#define BS_AIPS_PACRK_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRK_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP0 field.
+#define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP0.
+#define BF_AIPS_PACRK_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP0), uint32_t) & BM_AIPS_PACRK_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP0    (29U)         //!< Bit position for AIPS_PACRK_WP0.
+#define BM_AIPS_PACRK_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRK_WP0.
+#define BS_AIPS_PACRK_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRK_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP0 field.
+#define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP0.
+#define BF_AIPS_PACRK_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP0), uint32_t) & BM_AIPS_PACRK_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP0    (30U)         //!< Bit position for AIPS_PACRK_SP0.
+#define BM_AIPS_PACRK_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRK_SP0.
+#define BS_AIPS_PACRK_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRK_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP0 field.
+#define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP0.
+#define BF_AIPS_PACRK_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP0), uint32_t) & BM_AIPS_PACRK_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRL - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrl
+{
+    uint32_t U;
+    struct _hw_aips_pacrl_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+//@{
+#define HW_AIPS_PACRL_ADDR(x)    (REGS_AIPS_BASE(x) + 0x5CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRL(x)         (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x))
+#define HW_AIPS_PACRL_RD(x)      (HW_AIPS_PACRL(x).U)
+#define HW_AIPS_PACRL_WR(x, v)   (HW_AIPS_PACRL(x).U = (v))
+#define HW_AIPS_PACRL_SET(x, v)  (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) |  (v)))
+#define HW_AIPS_PACRL_CLR(x, v)  (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v)))
+#define HW_AIPS_PACRL_TOG(x, v)  (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP7    (0U)          //!< Bit position for AIPS_PACRL_TP7.
+#define BM_AIPS_PACRL_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRL_TP7.
+#define BS_AIPS_PACRL_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP7 field.
+#define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP7.
+#define BF_AIPS_PACRL_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP7), uint32_t) & BM_AIPS_PACRL_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP7    (1U)          //!< Bit position for AIPS_PACRL_WP7.
+#define BM_AIPS_PACRL_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRL_WP7.
+#define BS_AIPS_PACRL_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP7 field.
+#define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP7.
+#define BF_AIPS_PACRL_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP7), uint32_t) & BM_AIPS_PACRL_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP7    (2U)          //!< Bit position for AIPS_PACRL_SP7.
+#define BM_AIPS_PACRL_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRL_SP7.
+#define BS_AIPS_PACRL_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP7 field.
+#define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP7.
+#define BF_AIPS_PACRL_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP7), uint32_t) & BM_AIPS_PACRL_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP6    (4U)          //!< Bit position for AIPS_PACRL_TP6.
+#define BM_AIPS_PACRL_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRL_TP6.
+#define BS_AIPS_PACRL_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP6 field.
+#define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP6.
+#define BF_AIPS_PACRL_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP6), uint32_t) & BM_AIPS_PACRL_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP6    (5U)          //!< Bit position for AIPS_PACRL_WP6.
+#define BM_AIPS_PACRL_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRL_WP6.
+#define BS_AIPS_PACRL_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP6 field.
+#define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP6.
+#define BF_AIPS_PACRL_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP6), uint32_t) & BM_AIPS_PACRL_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP6    (6U)          //!< Bit position for AIPS_PACRL_SP6.
+#define BM_AIPS_PACRL_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRL_SP6.
+#define BS_AIPS_PACRL_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP6 field.
+#define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP6.
+#define BF_AIPS_PACRL_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP6), uint32_t) & BM_AIPS_PACRL_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP5    (8U)          //!< Bit position for AIPS_PACRL_TP5.
+#define BM_AIPS_PACRL_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRL_TP5.
+#define BS_AIPS_PACRL_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP5 field.
+#define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP5.
+#define BF_AIPS_PACRL_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP5), uint32_t) & BM_AIPS_PACRL_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP5    (9U)          //!< Bit position for AIPS_PACRL_WP5.
+#define BM_AIPS_PACRL_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRL_WP5.
+#define BS_AIPS_PACRL_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP5 field.
+#define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP5.
+#define BF_AIPS_PACRL_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP5), uint32_t) & BM_AIPS_PACRL_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP5    (10U)         //!< Bit position for AIPS_PACRL_SP5.
+#define BM_AIPS_PACRL_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRL_SP5.
+#define BS_AIPS_PACRL_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP5 field.
+#define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP5.
+#define BF_AIPS_PACRL_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP5), uint32_t) & BM_AIPS_PACRL_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP4    (12U)         //!< Bit position for AIPS_PACRL_TP4.
+#define BM_AIPS_PACRL_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRL_TP4.
+#define BS_AIPS_PACRL_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP4 field.
+#define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP4.
+#define BF_AIPS_PACRL_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP4), uint32_t) & BM_AIPS_PACRL_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP4    (13U)         //!< Bit position for AIPS_PACRL_WP4.
+#define BM_AIPS_PACRL_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRL_WP4.
+#define BS_AIPS_PACRL_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP4 field.
+#define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP4.
+#define BF_AIPS_PACRL_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP4), uint32_t) & BM_AIPS_PACRL_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP4    (14U)         //!< Bit position for AIPS_PACRL_SP4.
+#define BM_AIPS_PACRL_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRL_SP4.
+#define BS_AIPS_PACRL_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP4 field.
+#define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP4.
+#define BF_AIPS_PACRL_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP4), uint32_t) & BM_AIPS_PACRL_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP3    (16U)         //!< Bit position for AIPS_PACRL_TP3.
+#define BM_AIPS_PACRL_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRL_TP3.
+#define BS_AIPS_PACRL_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP3 field.
+#define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP3.
+#define BF_AIPS_PACRL_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP3), uint32_t) & BM_AIPS_PACRL_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP3    (17U)         //!< Bit position for AIPS_PACRL_WP3.
+#define BM_AIPS_PACRL_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRL_WP3.
+#define BS_AIPS_PACRL_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP3 field.
+#define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP3.
+#define BF_AIPS_PACRL_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP3), uint32_t) & BM_AIPS_PACRL_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP3    (18U)         //!< Bit position for AIPS_PACRL_SP3.
+#define BM_AIPS_PACRL_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRL_SP3.
+#define BS_AIPS_PACRL_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP3 field.
+#define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP3.
+#define BF_AIPS_PACRL_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP3), uint32_t) & BM_AIPS_PACRL_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP2    (20U)         //!< Bit position for AIPS_PACRL_TP2.
+#define BM_AIPS_PACRL_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRL_TP2.
+#define BS_AIPS_PACRL_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP2 field.
+#define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP2.
+#define BF_AIPS_PACRL_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP2), uint32_t) & BM_AIPS_PACRL_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP2    (21U)         //!< Bit position for AIPS_PACRL_WP2.
+#define BM_AIPS_PACRL_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRL_WP2.
+#define BS_AIPS_PACRL_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP2 field.
+#define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP2.
+#define BF_AIPS_PACRL_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP2), uint32_t) & BM_AIPS_PACRL_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP2    (22U)         //!< Bit position for AIPS_PACRL_SP2.
+#define BM_AIPS_PACRL_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRL_SP2.
+#define BS_AIPS_PACRL_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP2 field.
+#define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP2.
+#define BF_AIPS_PACRL_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP2), uint32_t) & BM_AIPS_PACRL_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP1    (24U)         //!< Bit position for AIPS_PACRL_TP1.
+#define BM_AIPS_PACRL_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRL_TP1.
+#define BS_AIPS_PACRL_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP1 field.
+#define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP1.
+#define BF_AIPS_PACRL_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP1), uint32_t) & BM_AIPS_PACRL_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP1    (25U)         //!< Bit position for AIPS_PACRL_WP1.
+#define BM_AIPS_PACRL_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRL_WP1.
+#define BS_AIPS_PACRL_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP1 field.
+#define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP1.
+#define BF_AIPS_PACRL_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP1), uint32_t) & BM_AIPS_PACRL_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP1    (26U)         //!< Bit position for AIPS_PACRL_SP1.
+#define BM_AIPS_PACRL_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRL_SP1.
+#define BS_AIPS_PACRL_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP1 field.
+#define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP1.
+#define BF_AIPS_PACRL_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP1), uint32_t) & BM_AIPS_PACRL_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP0    (28U)         //!< Bit position for AIPS_PACRL_TP0.
+#define BM_AIPS_PACRL_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRL_TP0.
+#define BS_AIPS_PACRL_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRL_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP0 field.
+#define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP0.
+#define BF_AIPS_PACRL_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP0), uint32_t) & BM_AIPS_PACRL_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP0    (29U)         //!< Bit position for AIPS_PACRL_WP0.
+#define BM_AIPS_PACRL_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRL_WP0.
+#define BS_AIPS_PACRL_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRL_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP0 field.
+#define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP0.
+#define BF_AIPS_PACRL_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP0), uint32_t) & BM_AIPS_PACRL_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP0    (30U)         //!< Bit position for AIPS_PACRL_SP0.
+#define BM_AIPS_PACRL_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRL_SP0.
+#define BS_AIPS_PACRL_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRL_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP0 field.
+#define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP0.
+#define BF_AIPS_PACRL_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP0), uint32_t) & BM_AIPS_PACRL_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRM - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrm
+{
+    uint32_t U;
+    struct _hw_aips_pacrm_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrm_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+//@{
+#define HW_AIPS_PACRM_ADDR(x)    (REGS_AIPS_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRM(x)         (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x))
+#define HW_AIPS_PACRM_RD(x)      (HW_AIPS_PACRM(x).U)
+#define HW_AIPS_PACRM_WR(x, v)   (HW_AIPS_PACRM(x).U = (v))
+#define HW_AIPS_PACRM_SET(x, v)  (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) |  (v)))
+#define HW_AIPS_PACRM_CLR(x, v)  (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v)))
+#define HW_AIPS_PACRM_TOG(x, v)  (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP7    (0U)          //!< Bit position for AIPS_PACRM_TP7.
+#define BM_AIPS_PACRM_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRM_TP7.
+#define BS_AIPS_PACRM_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP7 field.
+#define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP7.
+#define BF_AIPS_PACRM_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP7), uint32_t) & BM_AIPS_PACRM_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP7    (1U)          //!< Bit position for AIPS_PACRM_WP7.
+#define BM_AIPS_PACRM_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRM_WP7.
+#define BS_AIPS_PACRM_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP7 field.
+#define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP7.
+#define BF_AIPS_PACRM_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP7), uint32_t) & BM_AIPS_PACRM_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP7    (2U)          //!< Bit position for AIPS_PACRM_SP7.
+#define BM_AIPS_PACRM_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRM_SP7.
+#define BS_AIPS_PACRM_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP7 field.
+#define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP7.
+#define BF_AIPS_PACRM_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP7), uint32_t) & BM_AIPS_PACRM_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP6    (4U)          //!< Bit position for AIPS_PACRM_TP6.
+#define BM_AIPS_PACRM_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRM_TP6.
+#define BS_AIPS_PACRM_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP6 field.
+#define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP6.
+#define BF_AIPS_PACRM_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP6), uint32_t) & BM_AIPS_PACRM_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP6    (5U)          //!< Bit position for AIPS_PACRM_WP6.
+#define BM_AIPS_PACRM_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRM_WP6.
+#define BS_AIPS_PACRM_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP6 field.
+#define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP6.
+#define BF_AIPS_PACRM_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP6), uint32_t) & BM_AIPS_PACRM_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP6    (6U)          //!< Bit position for AIPS_PACRM_SP6.
+#define BM_AIPS_PACRM_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRM_SP6.
+#define BS_AIPS_PACRM_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP6 field.
+#define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP6.
+#define BF_AIPS_PACRM_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP6), uint32_t) & BM_AIPS_PACRM_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP5    (8U)          //!< Bit position for AIPS_PACRM_TP5.
+#define BM_AIPS_PACRM_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRM_TP5.
+#define BS_AIPS_PACRM_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP5 field.
+#define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP5.
+#define BF_AIPS_PACRM_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP5), uint32_t) & BM_AIPS_PACRM_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP5    (9U)          //!< Bit position for AIPS_PACRM_WP5.
+#define BM_AIPS_PACRM_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRM_WP5.
+#define BS_AIPS_PACRM_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP5 field.
+#define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP5.
+#define BF_AIPS_PACRM_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP5), uint32_t) & BM_AIPS_PACRM_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP5    (10U)         //!< Bit position for AIPS_PACRM_SP5.
+#define BM_AIPS_PACRM_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRM_SP5.
+#define BS_AIPS_PACRM_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP5 field.
+#define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP5.
+#define BF_AIPS_PACRM_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP5), uint32_t) & BM_AIPS_PACRM_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP4    (12U)         //!< Bit position for AIPS_PACRM_TP4.
+#define BM_AIPS_PACRM_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRM_TP4.
+#define BS_AIPS_PACRM_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP4 field.
+#define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP4.
+#define BF_AIPS_PACRM_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP4), uint32_t) & BM_AIPS_PACRM_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP4    (13U)         //!< Bit position for AIPS_PACRM_WP4.
+#define BM_AIPS_PACRM_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRM_WP4.
+#define BS_AIPS_PACRM_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP4 field.
+#define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP4.
+#define BF_AIPS_PACRM_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP4), uint32_t) & BM_AIPS_PACRM_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP4    (14U)         //!< Bit position for AIPS_PACRM_SP4.
+#define BM_AIPS_PACRM_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRM_SP4.
+#define BS_AIPS_PACRM_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP4 field.
+#define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP4.
+#define BF_AIPS_PACRM_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP4), uint32_t) & BM_AIPS_PACRM_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP3    (16U)         //!< Bit position for AIPS_PACRM_TP3.
+#define BM_AIPS_PACRM_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRM_TP3.
+#define BS_AIPS_PACRM_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP3 field.
+#define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP3.
+#define BF_AIPS_PACRM_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP3), uint32_t) & BM_AIPS_PACRM_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP3    (17U)         //!< Bit position for AIPS_PACRM_WP3.
+#define BM_AIPS_PACRM_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRM_WP3.
+#define BS_AIPS_PACRM_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP3 field.
+#define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP3.
+#define BF_AIPS_PACRM_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP3), uint32_t) & BM_AIPS_PACRM_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP3    (18U)         //!< Bit position for AIPS_PACRM_SP3.
+#define BM_AIPS_PACRM_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRM_SP3.
+#define BS_AIPS_PACRM_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP3 field.
+#define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP3.
+#define BF_AIPS_PACRM_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP3), uint32_t) & BM_AIPS_PACRM_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP2    (20U)         //!< Bit position for AIPS_PACRM_TP2.
+#define BM_AIPS_PACRM_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRM_TP2.
+#define BS_AIPS_PACRM_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP2 field.
+#define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP2.
+#define BF_AIPS_PACRM_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP2), uint32_t) & BM_AIPS_PACRM_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP2    (21U)         //!< Bit position for AIPS_PACRM_WP2.
+#define BM_AIPS_PACRM_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRM_WP2.
+#define BS_AIPS_PACRM_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP2 field.
+#define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP2.
+#define BF_AIPS_PACRM_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP2), uint32_t) & BM_AIPS_PACRM_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP2    (22U)         //!< Bit position for AIPS_PACRM_SP2.
+#define BM_AIPS_PACRM_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRM_SP2.
+#define BS_AIPS_PACRM_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP2 field.
+#define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP2.
+#define BF_AIPS_PACRM_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP2), uint32_t) & BM_AIPS_PACRM_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP1    (24U)         //!< Bit position for AIPS_PACRM_TP1.
+#define BM_AIPS_PACRM_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRM_TP1.
+#define BS_AIPS_PACRM_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP1 field.
+#define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP1.
+#define BF_AIPS_PACRM_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP1), uint32_t) & BM_AIPS_PACRM_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP1    (25U)         //!< Bit position for AIPS_PACRM_WP1.
+#define BM_AIPS_PACRM_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRM_WP1.
+#define BS_AIPS_PACRM_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP1 field.
+#define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP1.
+#define BF_AIPS_PACRM_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP1), uint32_t) & BM_AIPS_PACRM_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP1    (26U)         //!< Bit position for AIPS_PACRM_SP1.
+#define BM_AIPS_PACRM_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRM_SP1.
+#define BS_AIPS_PACRM_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP1 field.
+#define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP1.
+#define BF_AIPS_PACRM_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP1), uint32_t) & BM_AIPS_PACRM_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP0    (28U)         //!< Bit position for AIPS_PACRM_TP0.
+#define BM_AIPS_PACRM_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRM_TP0.
+#define BS_AIPS_PACRM_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRM_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP0 field.
+#define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP0.
+#define BF_AIPS_PACRM_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP0), uint32_t) & BM_AIPS_PACRM_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP0    (29U)         //!< Bit position for AIPS_PACRM_WP0.
+#define BM_AIPS_PACRM_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRM_WP0.
+#define BS_AIPS_PACRM_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRM_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP0 field.
+#define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP0.
+#define BF_AIPS_PACRM_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP0), uint32_t) & BM_AIPS_PACRM_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP0    (30U)         //!< Bit position for AIPS_PACRM_SP0.
+#define BM_AIPS_PACRM_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRM_SP0.
+#define BS_AIPS_PACRM_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRM_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP0 field.
+#define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP0.
+#define BF_AIPS_PACRM_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP0), uint32_t) & BM_AIPS_PACRM_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRN - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrn
+{
+    uint32_t U;
+    struct _hw_aips_pacrn_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+//@{
+#define HW_AIPS_PACRN_ADDR(x)    (REGS_AIPS_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRN(x)         (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x))
+#define HW_AIPS_PACRN_RD(x)      (HW_AIPS_PACRN(x).U)
+#define HW_AIPS_PACRN_WR(x, v)   (HW_AIPS_PACRN(x).U = (v))
+#define HW_AIPS_PACRN_SET(x, v)  (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) |  (v)))
+#define HW_AIPS_PACRN_CLR(x, v)  (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v)))
+#define HW_AIPS_PACRN_TOG(x, v)  (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP7    (0U)          //!< Bit position for AIPS_PACRN_TP7.
+#define BM_AIPS_PACRN_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRN_TP7.
+#define BS_AIPS_PACRN_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP7 field.
+#define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP7.
+#define BF_AIPS_PACRN_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP7), uint32_t) & BM_AIPS_PACRN_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP7    (1U)          //!< Bit position for AIPS_PACRN_WP7.
+#define BM_AIPS_PACRN_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRN_WP7.
+#define BS_AIPS_PACRN_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP7 field.
+#define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP7.
+#define BF_AIPS_PACRN_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP7), uint32_t) & BM_AIPS_PACRN_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP7    (2U)          //!< Bit position for AIPS_PACRN_SP7.
+#define BM_AIPS_PACRN_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRN_SP7.
+#define BS_AIPS_PACRN_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP7 field.
+#define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP7.
+#define BF_AIPS_PACRN_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP7), uint32_t) & BM_AIPS_PACRN_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP6    (4U)          //!< Bit position for AIPS_PACRN_TP6.
+#define BM_AIPS_PACRN_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRN_TP6.
+#define BS_AIPS_PACRN_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP6 field.
+#define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP6.
+#define BF_AIPS_PACRN_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP6), uint32_t) & BM_AIPS_PACRN_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP6    (5U)          //!< Bit position for AIPS_PACRN_WP6.
+#define BM_AIPS_PACRN_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRN_WP6.
+#define BS_AIPS_PACRN_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP6 field.
+#define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP6.
+#define BF_AIPS_PACRN_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP6), uint32_t) & BM_AIPS_PACRN_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP6    (6U)          //!< Bit position for AIPS_PACRN_SP6.
+#define BM_AIPS_PACRN_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRN_SP6.
+#define BS_AIPS_PACRN_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP6 field.
+#define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP6.
+#define BF_AIPS_PACRN_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP6), uint32_t) & BM_AIPS_PACRN_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP5    (8U)          //!< Bit position for AIPS_PACRN_TP5.
+#define BM_AIPS_PACRN_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRN_TP5.
+#define BS_AIPS_PACRN_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP5 field.
+#define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP5.
+#define BF_AIPS_PACRN_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP5), uint32_t) & BM_AIPS_PACRN_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP5    (9U)          //!< Bit position for AIPS_PACRN_WP5.
+#define BM_AIPS_PACRN_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRN_WP5.
+#define BS_AIPS_PACRN_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP5 field.
+#define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP5.
+#define BF_AIPS_PACRN_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP5), uint32_t) & BM_AIPS_PACRN_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP5    (10U)         //!< Bit position for AIPS_PACRN_SP5.
+#define BM_AIPS_PACRN_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRN_SP5.
+#define BS_AIPS_PACRN_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP5 field.
+#define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP5.
+#define BF_AIPS_PACRN_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP5), uint32_t) & BM_AIPS_PACRN_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP4    (12U)         //!< Bit position for AIPS_PACRN_TP4.
+#define BM_AIPS_PACRN_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRN_TP4.
+#define BS_AIPS_PACRN_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP4 field.
+#define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP4.
+#define BF_AIPS_PACRN_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP4), uint32_t) & BM_AIPS_PACRN_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP4    (13U)         //!< Bit position for AIPS_PACRN_WP4.
+#define BM_AIPS_PACRN_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRN_WP4.
+#define BS_AIPS_PACRN_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP4 field.
+#define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP4.
+#define BF_AIPS_PACRN_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP4), uint32_t) & BM_AIPS_PACRN_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP4    (14U)         //!< Bit position for AIPS_PACRN_SP4.
+#define BM_AIPS_PACRN_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRN_SP4.
+#define BS_AIPS_PACRN_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP4 field.
+#define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP4.
+#define BF_AIPS_PACRN_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP4), uint32_t) & BM_AIPS_PACRN_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP3    (16U)         //!< Bit position for AIPS_PACRN_TP3.
+#define BM_AIPS_PACRN_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRN_TP3.
+#define BS_AIPS_PACRN_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP3 field.
+#define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP3.
+#define BF_AIPS_PACRN_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP3), uint32_t) & BM_AIPS_PACRN_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP3    (17U)         //!< Bit position for AIPS_PACRN_WP3.
+#define BM_AIPS_PACRN_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRN_WP3.
+#define BS_AIPS_PACRN_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP3 field.
+#define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP3.
+#define BF_AIPS_PACRN_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP3), uint32_t) & BM_AIPS_PACRN_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP3    (18U)         //!< Bit position for AIPS_PACRN_SP3.
+#define BM_AIPS_PACRN_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRN_SP3.
+#define BS_AIPS_PACRN_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP3 field.
+#define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP3.
+#define BF_AIPS_PACRN_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP3), uint32_t) & BM_AIPS_PACRN_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP2    (20U)         //!< Bit position for AIPS_PACRN_TP2.
+#define BM_AIPS_PACRN_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRN_TP2.
+#define BS_AIPS_PACRN_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP2 field.
+#define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP2.
+#define BF_AIPS_PACRN_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP2), uint32_t) & BM_AIPS_PACRN_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP2    (21U)         //!< Bit position for AIPS_PACRN_WP2.
+#define BM_AIPS_PACRN_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRN_WP2.
+#define BS_AIPS_PACRN_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP2 field.
+#define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP2.
+#define BF_AIPS_PACRN_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP2), uint32_t) & BM_AIPS_PACRN_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP2    (22U)         //!< Bit position for AIPS_PACRN_SP2.
+#define BM_AIPS_PACRN_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRN_SP2.
+#define BS_AIPS_PACRN_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP2 field.
+#define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP2.
+#define BF_AIPS_PACRN_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP2), uint32_t) & BM_AIPS_PACRN_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP1    (24U)         //!< Bit position for AIPS_PACRN_TP1.
+#define BM_AIPS_PACRN_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRN_TP1.
+#define BS_AIPS_PACRN_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP1 field.
+#define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP1.
+#define BF_AIPS_PACRN_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP1), uint32_t) & BM_AIPS_PACRN_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP1    (25U)         //!< Bit position for AIPS_PACRN_WP1.
+#define BM_AIPS_PACRN_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRN_WP1.
+#define BS_AIPS_PACRN_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP1 field.
+#define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP1.
+#define BF_AIPS_PACRN_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP1), uint32_t) & BM_AIPS_PACRN_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP1    (26U)         //!< Bit position for AIPS_PACRN_SP1.
+#define BM_AIPS_PACRN_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRN_SP1.
+#define BS_AIPS_PACRN_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP1 field.
+#define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP1.
+#define BF_AIPS_PACRN_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP1), uint32_t) & BM_AIPS_PACRN_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP0    (28U)         //!< Bit position for AIPS_PACRN_TP0.
+#define BM_AIPS_PACRN_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRN_TP0.
+#define BS_AIPS_PACRN_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRN_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP0 field.
+#define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP0.
+#define BF_AIPS_PACRN_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP0), uint32_t) & BM_AIPS_PACRN_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP0    (29U)         //!< Bit position for AIPS_PACRN_WP0.
+#define BM_AIPS_PACRN_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRN_WP0.
+#define BS_AIPS_PACRN_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRN_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP0 field.
+#define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP0.
+#define BF_AIPS_PACRN_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP0), uint32_t) & BM_AIPS_PACRN_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP0    (30U)         //!< Bit position for AIPS_PACRN_SP0.
+#define BM_AIPS_PACRN_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRN_SP0.
+#define BS_AIPS_PACRN_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRN_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP0 field.
+#define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP0.
+#define BF_AIPS_PACRN_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP0), uint32_t) & BM_AIPS_PACRN_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRO - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacro
+{
+    uint32_t U;
+    struct _hw_aips_pacro_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacro_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+//@{
+#define HW_AIPS_PACRO_ADDR(x)    (REGS_AIPS_BASE(x) + 0x68U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRO(x)         (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x))
+#define HW_AIPS_PACRO_RD(x)      (HW_AIPS_PACRO(x).U)
+#define HW_AIPS_PACRO_WR(x, v)   (HW_AIPS_PACRO(x).U = (v))
+#define HW_AIPS_PACRO_SET(x, v)  (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) |  (v)))
+#define HW_AIPS_PACRO_CLR(x, v)  (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v)))
+#define HW_AIPS_PACRO_TOG(x, v)  (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP7    (0U)          //!< Bit position for AIPS_PACRO_TP7.
+#define BM_AIPS_PACRO_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRO_TP7.
+#define BS_AIPS_PACRO_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP7 field.
+#define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP7.
+#define BF_AIPS_PACRO_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP7), uint32_t) & BM_AIPS_PACRO_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP7    (1U)          //!< Bit position for AIPS_PACRO_WP7.
+#define BM_AIPS_PACRO_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRO_WP7.
+#define BS_AIPS_PACRO_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP7 field.
+#define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP7.
+#define BF_AIPS_PACRO_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP7), uint32_t) & BM_AIPS_PACRO_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP7    (2U)          //!< Bit position for AIPS_PACRO_SP7.
+#define BM_AIPS_PACRO_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRO_SP7.
+#define BS_AIPS_PACRO_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP7 field.
+#define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP7.
+#define BF_AIPS_PACRO_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP7), uint32_t) & BM_AIPS_PACRO_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP6    (4U)          //!< Bit position for AIPS_PACRO_TP6.
+#define BM_AIPS_PACRO_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRO_TP6.
+#define BS_AIPS_PACRO_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP6 field.
+#define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP6.
+#define BF_AIPS_PACRO_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP6), uint32_t) & BM_AIPS_PACRO_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP6    (5U)          //!< Bit position for AIPS_PACRO_WP6.
+#define BM_AIPS_PACRO_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRO_WP6.
+#define BS_AIPS_PACRO_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP6 field.
+#define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP6.
+#define BF_AIPS_PACRO_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP6), uint32_t) & BM_AIPS_PACRO_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP6    (6U)          //!< Bit position for AIPS_PACRO_SP6.
+#define BM_AIPS_PACRO_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRO_SP6.
+#define BS_AIPS_PACRO_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP6 field.
+#define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP6.
+#define BF_AIPS_PACRO_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP6), uint32_t) & BM_AIPS_PACRO_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP5    (8U)          //!< Bit position for AIPS_PACRO_TP5.
+#define BM_AIPS_PACRO_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRO_TP5.
+#define BS_AIPS_PACRO_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP5 field.
+#define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP5.
+#define BF_AIPS_PACRO_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP5), uint32_t) & BM_AIPS_PACRO_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP5    (9U)          //!< Bit position for AIPS_PACRO_WP5.
+#define BM_AIPS_PACRO_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRO_WP5.
+#define BS_AIPS_PACRO_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP5 field.
+#define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP5.
+#define BF_AIPS_PACRO_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP5), uint32_t) & BM_AIPS_PACRO_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP5    (10U)         //!< Bit position for AIPS_PACRO_SP5.
+#define BM_AIPS_PACRO_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRO_SP5.
+#define BS_AIPS_PACRO_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP5 field.
+#define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP5.
+#define BF_AIPS_PACRO_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP5), uint32_t) & BM_AIPS_PACRO_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP4    (12U)         //!< Bit position for AIPS_PACRO_TP4.
+#define BM_AIPS_PACRO_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRO_TP4.
+#define BS_AIPS_PACRO_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP4 field.
+#define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP4.
+#define BF_AIPS_PACRO_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP4), uint32_t) & BM_AIPS_PACRO_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP4    (13U)         //!< Bit position for AIPS_PACRO_WP4.
+#define BM_AIPS_PACRO_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRO_WP4.
+#define BS_AIPS_PACRO_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP4 field.
+#define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP4.
+#define BF_AIPS_PACRO_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP4), uint32_t) & BM_AIPS_PACRO_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP4    (14U)         //!< Bit position for AIPS_PACRO_SP4.
+#define BM_AIPS_PACRO_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRO_SP4.
+#define BS_AIPS_PACRO_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP4 field.
+#define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP4.
+#define BF_AIPS_PACRO_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP4), uint32_t) & BM_AIPS_PACRO_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP3    (16U)         //!< Bit position for AIPS_PACRO_TP3.
+#define BM_AIPS_PACRO_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRO_TP3.
+#define BS_AIPS_PACRO_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP3 field.
+#define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP3.
+#define BF_AIPS_PACRO_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP3), uint32_t) & BM_AIPS_PACRO_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP3    (17U)         //!< Bit position for AIPS_PACRO_WP3.
+#define BM_AIPS_PACRO_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRO_WP3.
+#define BS_AIPS_PACRO_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP3 field.
+#define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP3.
+#define BF_AIPS_PACRO_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP3), uint32_t) & BM_AIPS_PACRO_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP3    (18U)         //!< Bit position for AIPS_PACRO_SP3.
+#define BM_AIPS_PACRO_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRO_SP3.
+#define BS_AIPS_PACRO_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP3 field.
+#define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP3.
+#define BF_AIPS_PACRO_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP3), uint32_t) & BM_AIPS_PACRO_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP2    (20U)         //!< Bit position for AIPS_PACRO_TP2.
+#define BM_AIPS_PACRO_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRO_TP2.
+#define BS_AIPS_PACRO_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP2 field.
+#define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP2.
+#define BF_AIPS_PACRO_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP2), uint32_t) & BM_AIPS_PACRO_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP2    (21U)         //!< Bit position for AIPS_PACRO_WP2.
+#define BM_AIPS_PACRO_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRO_WP2.
+#define BS_AIPS_PACRO_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP2 field.
+#define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP2.
+#define BF_AIPS_PACRO_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP2), uint32_t) & BM_AIPS_PACRO_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP2    (22U)         //!< Bit position for AIPS_PACRO_SP2.
+#define BM_AIPS_PACRO_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRO_SP2.
+#define BS_AIPS_PACRO_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP2 field.
+#define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP2.
+#define BF_AIPS_PACRO_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP2), uint32_t) & BM_AIPS_PACRO_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP1    (24U)         //!< Bit position for AIPS_PACRO_TP1.
+#define BM_AIPS_PACRO_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRO_TP1.
+#define BS_AIPS_PACRO_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP1 field.
+#define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP1.
+#define BF_AIPS_PACRO_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP1), uint32_t) & BM_AIPS_PACRO_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP1    (25U)         //!< Bit position for AIPS_PACRO_WP1.
+#define BM_AIPS_PACRO_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRO_WP1.
+#define BS_AIPS_PACRO_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP1 field.
+#define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP1.
+#define BF_AIPS_PACRO_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP1), uint32_t) & BM_AIPS_PACRO_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP1    (26U)         //!< Bit position for AIPS_PACRO_SP1.
+#define BM_AIPS_PACRO_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRO_SP1.
+#define BS_AIPS_PACRO_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP1 field.
+#define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP1.
+#define BF_AIPS_PACRO_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP1), uint32_t) & BM_AIPS_PACRO_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP0    (28U)         //!< Bit position for AIPS_PACRO_TP0.
+#define BM_AIPS_PACRO_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRO_TP0.
+#define BS_AIPS_PACRO_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRO_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP0 field.
+#define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP0.
+#define BF_AIPS_PACRO_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP0), uint32_t) & BM_AIPS_PACRO_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP0    (29U)         //!< Bit position for AIPS_PACRO_WP0.
+#define BM_AIPS_PACRO_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRO_WP0.
+#define BS_AIPS_PACRO_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRO_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP0 field.
+#define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP0.
+#define BF_AIPS_PACRO_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP0), uint32_t) & BM_AIPS_PACRO_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP0    (30U)         //!< Bit position for AIPS_PACRO_SP0.
+#define BM_AIPS_PACRO_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRO_SP0.
+#define BS_AIPS_PACRO_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRO_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP0 field.
+#define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP0.
+#define BF_AIPS_PACRO_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP0), uint32_t) & BM_AIPS_PACRO_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRP - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrp
+{
+    uint32_t U;
+    struct _hw_aips_pacrp_bitfields
+    {
+        uint32_t TP7 : 1;              //!< [0] Trusted Protect
+        uint32_t WP7 : 1;              //!< [1] Write Protect
+        uint32_t SP7 : 1;              //!< [2] Supervisor Protect
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TP6 : 1;              //!< [4] Trusted Protect
+        uint32_t WP6 : 1;              //!< [5] Write Protect
+        uint32_t SP6 : 1;              //!< [6] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t TP5 : 1;              //!< [8] Trusted Protect
+        uint32_t WP5 : 1;              //!< [9] Write Protect
+        uint32_t SP5 : 1;              //!< [10] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t TP4 : 1;              //!< [12] Trusted Protect
+        uint32_t WP4 : 1;              //!< [13] Write Protect
+        uint32_t SP4 : 1;              //!< [14] Supervisor Protect
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t TP3 : 1;              //!< [16] Trusted Protect
+        uint32_t WP3 : 1;              //!< [17] Write Protect
+        uint32_t SP3 : 1;              //!< [18] Supervisor Protect
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t TP2 : 1;              //!< [20] Trusted Protect
+        uint32_t WP2 : 1;              //!< [21] Write Protect
+        uint32_t SP2 : 1;              //!< [22] Supervisor Protect
+        uint32_t RESERVED5 : 1;        //!< [23]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED6 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED7 : 1;        //!< [31]
+    } B;
+} hw_aips_pacrp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+//@{
+#define HW_AIPS_PACRP_ADDR(x)    (REGS_AIPS_BASE(x) + 0x6CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRP(x)         (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x))
+#define HW_AIPS_PACRP_RD(x)      (HW_AIPS_PACRP(x).U)
+#define HW_AIPS_PACRP_WR(x, v)   (HW_AIPS_PACRP(x).U = (v))
+#define HW_AIPS_PACRP_SET(x, v)  (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) |  (v)))
+#define HW_AIPS_PACRP_CLR(x, v)  (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v)))
+#define HW_AIPS_PACRP_TOG(x, v)  (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP7    (0U)          //!< Bit position for AIPS_PACRP_TP7.
+#define BM_AIPS_PACRP_TP7    (0x00000001U) //!< Bit mask for AIPS_PACRP_TP7.
+#define BS_AIPS_PACRP_TP7    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP7 field.
+#define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP7.
+#define BF_AIPS_PACRP_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP7), uint32_t) & BM_AIPS_PACRP_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP7    (1U)          //!< Bit position for AIPS_PACRP_WP7.
+#define BM_AIPS_PACRP_WP7    (0x00000002U) //!< Bit mask for AIPS_PACRP_WP7.
+#define BS_AIPS_PACRP_WP7    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP7 field.
+#define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP7.
+#define BF_AIPS_PACRP_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP7), uint32_t) & BM_AIPS_PACRP_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP7    (2U)          //!< Bit position for AIPS_PACRP_SP7.
+#define BM_AIPS_PACRP_SP7    (0x00000004U) //!< Bit mask for AIPS_PACRP_SP7.
+#define BS_AIPS_PACRP_SP7    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP7 field.
+#define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP7.
+#define BF_AIPS_PACRP_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP7), uint32_t) & BM_AIPS_PACRP_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP6    (4U)          //!< Bit position for AIPS_PACRP_TP6.
+#define BM_AIPS_PACRP_TP6    (0x00000010U) //!< Bit mask for AIPS_PACRP_TP6.
+#define BS_AIPS_PACRP_TP6    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP6 field.
+#define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP6.
+#define BF_AIPS_PACRP_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP6), uint32_t) & BM_AIPS_PACRP_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP6    (5U)          //!< Bit position for AIPS_PACRP_WP6.
+#define BM_AIPS_PACRP_WP6    (0x00000020U) //!< Bit mask for AIPS_PACRP_WP6.
+#define BS_AIPS_PACRP_WP6    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP6 field.
+#define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP6.
+#define BF_AIPS_PACRP_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP6), uint32_t) & BM_AIPS_PACRP_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP6    (6U)          //!< Bit position for AIPS_PACRP_SP6.
+#define BM_AIPS_PACRP_SP6    (0x00000040U) //!< Bit mask for AIPS_PACRP_SP6.
+#define BS_AIPS_PACRP_SP6    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP6 field.
+#define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP6.
+#define BF_AIPS_PACRP_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP6), uint32_t) & BM_AIPS_PACRP_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP5    (8U)          //!< Bit position for AIPS_PACRP_TP5.
+#define BM_AIPS_PACRP_TP5    (0x00000100U) //!< Bit mask for AIPS_PACRP_TP5.
+#define BS_AIPS_PACRP_TP5    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP5 field.
+#define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP5.
+#define BF_AIPS_PACRP_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP5), uint32_t) & BM_AIPS_PACRP_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP5    (9U)          //!< Bit position for AIPS_PACRP_WP5.
+#define BM_AIPS_PACRP_WP5    (0x00000200U) //!< Bit mask for AIPS_PACRP_WP5.
+#define BS_AIPS_PACRP_WP5    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP5 field.
+#define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP5.
+#define BF_AIPS_PACRP_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP5), uint32_t) & BM_AIPS_PACRP_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP5    (10U)         //!< Bit position for AIPS_PACRP_SP5.
+#define BM_AIPS_PACRP_SP5    (0x00000400U) //!< Bit mask for AIPS_PACRP_SP5.
+#define BS_AIPS_PACRP_SP5    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP5 field.
+#define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP5.
+#define BF_AIPS_PACRP_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP5), uint32_t) & BM_AIPS_PACRP_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP4    (12U)         //!< Bit position for AIPS_PACRP_TP4.
+#define BM_AIPS_PACRP_TP4    (0x00001000U) //!< Bit mask for AIPS_PACRP_TP4.
+#define BS_AIPS_PACRP_TP4    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP4 field.
+#define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP4.
+#define BF_AIPS_PACRP_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP4), uint32_t) & BM_AIPS_PACRP_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP4    (13U)         //!< Bit position for AIPS_PACRP_WP4.
+#define BM_AIPS_PACRP_WP4    (0x00002000U) //!< Bit mask for AIPS_PACRP_WP4.
+#define BS_AIPS_PACRP_WP4    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP4 field.
+#define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP4.
+#define BF_AIPS_PACRP_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP4), uint32_t) & BM_AIPS_PACRP_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP4    (14U)         //!< Bit position for AIPS_PACRP_SP4.
+#define BM_AIPS_PACRP_SP4    (0x00004000U) //!< Bit mask for AIPS_PACRP_SP4.
+#define BS_AIPS_PACRP_SP4    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP4 field.
+#define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP4.
+#define BF_AIPS_PACRP_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP4), uint32_t) & BM_AIPS_PACRP_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP3    (16U)         //!< Bit position for AIPS_PACRP_TP3.
+#define BM_AIPS_PACRP_TP3    (0x00010000U) //!< Bit mask for AIPS_PACRP_TP3.
+#define BS_AIPS_PACRP_TP3    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP3 field.
+#define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP3.
+#define BF_AIPS_PACRP_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP3), uint32_t) & BM_AIPS_PACRP_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP3    (17U)         //!< Bit position for AIPS_PACRP_WP3.
+#define BM_AIPS_PACRP_WP3    (0x00020000U) //!< Bit mask for AIPS_PACRP_WP3.
+#define BS_AIPS_PACRP_WP3    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP3 field.
+#define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP3.
+#define BF_AIPS_PACRP_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP3), uint32_t) & BM_AIPS_PACRP_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP3    (18U)         //!< Bit position for AIPS_PACRP_SP3.
+#define BM_AIPS_PACRP_SP3    (0x00040000U) //!< Bit mask for AIPS_PACRP_SP3.
+#define BS_AIPS_PACRP_SP3    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP3 field.
+#define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP3.
+#define BF_AIPS_PACRP_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP3), uint32_t) & BM_AIPS_PACRP_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP2    (20U)         //!< Bit position for AIPS_PACRP_TP2.
+#define BM_AIPS_PACRP_TP2    (0x00100000U) //!< Bit mask for AIPS_PACRP_TP2.
+#define BS_AIPS_PACRP_TP2    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP2 field.
+#define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP2.
+#define BF_AIPS_PACRP_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP2), uint32_t) & BM_AIPS_PACRP_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP2    (21U)         //!< Bit position for AIPS_PACRP_WP2.
+#define BM_AIPS_PACRP_WP2    (0x00200000U) //!< Bit mask for AIPS_PACRP_WP2.
+#define BS_AIPS_PACRP_WP2    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP2 field.
+#define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP2.
+#define BF_AIPS_PACRP_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP2), uint32_t) & BM_AIPS_PACRP_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP2    (22U)         //!< Bit position for AIPS_PACRP_SP2.
+#define BM_AIPS_PACRP_SP2    (0x00400000U) //!< Bit mask for AIPS_PACRP_SP2.
+#define BS_AIPS_PACRP_SP2    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP2 field.
+#define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP2.
+#define BF_AIPS_PACRP_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP2), uint32_t) & BM_AIPS_PACRP_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP1    (24U)         //!< Bit position for AIPS_PACRP_TP1.
+#define BM_AIPS_PACRP_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRP_TP1.
+#define BS_AIPS_PACRP_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP1 field.
+#define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP1.
+#define BF_AIPS_PACRP_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP1), uint32_t) & BM_AIPS_PACRP_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP1    (25U)         //!< Bit position for AIPS_PACRP_WP1.
+#define BM_AIPS_PACRP_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRP_WP1.
+#define BS_AIPS_PACRP_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP1 field.
+#define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP1.
+#define BF_AIPS_PACRP_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP1), uint32_t) & BM_AIPS_PACRP_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP1    (26U)         //!< Bit position for AIPS_PACRP_SP1.
+#define BM_AIPS_PACRP_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRP_SP1.
+#define BS_AIPS_PACRP_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP1 field.
+#define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP1.
+#define BF_AIPS_PACRP_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP1), uint32_t) & BM_AIPS_PACRP_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP0    (28U)         //!< Bit position for AIPS_PACRP_TP0.
+#define BM_AIPS_PACRP_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRP_TP0.
+#define BS_AIPS_PACRP_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRP_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP0 field.
+#define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP0.
+#define BF_AIPS_PACRP_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP0), uint32_t) & BM_AIPS_PACRP_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP0    (29U)         //!< Bit position for AIPS_PACRP_WP0.
+#define BM_AIPS_PACRP_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRP_WP0.
+#define BS_AIPS_PACRP_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRP_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP0 field.
+#define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP0.
+#define BF_AIPS_PACRP_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP0), uint32_t) & BM_AIPS_PACRP_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP0    (30U)         //!< Bit position for AIPS_PACRP_SP0.
+#define BM_AIPS_PACRP_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRP_SP0.
+#define BS_AIPS_PACRP_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRP_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP0 field.
+#define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP0.
+#define BF_AIPS_PACRP_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP0), uint32_t) & BM_AIPS_PACRP_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRU - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+typedef union _hw_aips_pacru
+{
+    uint32_t U;
+    struct _hw_aips_pacru_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t TP1 : 1;              //!< [24] Trusted Protect
+        uint32_t WP1 : 1;              //!< [25] Write Protect
+        uint32_t SP1 : 1;              //!< [26] Supervisor Protect
+        uint32_t RESERVED1 : 1;        //!< [27]
+        uint32_t TP0 : 1;              //!< [28] Trusted Protect
+        uint32_t WP0 : 1;              //!< [29] Write Protect
+        uint32_t SP0 : 1;              //!< [30] Supervisor Protect
+        uint32_t RESERVED2 : 1;        //!< [31]
+    } B;
+} hw_aips_pacru_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+//@{
+#define HW_AIPS_PACRU_ADDR(x)    (REGS_AIPS_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRU(x)         (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x))
+#define HW_AIPS_PACRU_RD(x)      (HW_AIPS_PACRU(x).U)
+#define HW_AIPS_PACRU_WR(x, v)   (HW_AIPS_PACRU(x).U = (v))
+#define HW_AIPS_PACRU_SET(x, v)  (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) |  (v)))
+#define HW_AIPS_PACRU_CLR(x, v)  (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v)))
+#define HW_AIPS_PACRU_TOG(x, v)  (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRU_TP1    (24U)         //!< Bit position for AIPS_PACRU_TP1.
+#define BM_AIPS_PACRU_TP1    (0x01000000U) //!< Bit mask for AIPS_PACRU_TP1.
+#define BS_AIPS_PACRU_TP1    (1U)          //!< Bit field size in bits for AIPS_PACRU_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_TP1 field.
+#define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_TP1.
+#define BF_AIPS_PACRU_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP1), uint32_t) & BM_AIPS_PACRU_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRU_WP1    (25U)         //!< Bit position for AIPS_PACRU_WP1.
+#define BM_AIPS_PACRU_WP1    (0x02000000U) //!< Bit mask for AIPS_PACRU_WP1.
+#define BS_AIPS_PACRU_WP1    (1U)          //!< Bit field size in bits for AIPS_PACRU_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_WP1 field.
+#define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_WP1.
+#define BF_AIPS_PACRU_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP1), uint32_t) & BM_AIPS_PACRU_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRU_SP1    (26U)         //!< Bit position for AIPS_PACRU_SP1.
+#define BM_AIPS_PACRU_SP1    (0x04000000U) //!< Bit mask for AIPS_PACRU_SP1.
+#define BS_AIPS_PACRU_SP1    (1U)          //!< Bit field size in bits for AIPS_PACRU_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_SP1 field.
+#define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_SP1.
+#define BF_AIPS_PACRU_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP1), uint32_t) & BM_AIPS_PACRU_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRU_TP0    (28U)         //!< Bit position for AIPS_PACRU_TP0.
+#define BM_AIPS_PACRU_TP0    (0x10000000U) //!< Bit mask for AIPS_PACRU_TP0.
+#define BS_AIPS_PACRU_TP0    (1U)          //!< Bit field size in bits for AIPS_PACRU_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_TP0 field.
+#define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_TP0.
+#define BF_AIPS_PACRU_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP0), uint32_t) & BM_AIPS_PACRU_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRU_WP0    (29U)         //!< Bit position for AIPS_PACRU_WP0.
+#define BM_AIPS_PACRU_WP0    (0x20000000U) //!< Bit mask for AIPS_PACRU_WP0.
+#define BS_AIPS_PACRU_WP0    (1U)          //!< Bit field size in bits for AIPS_PACRU_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_WP0 field.
+#define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_WP0.
+#define BF_AIPS_PACRU_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP0), uint32_t) & BM_AIPS_PACRU_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRU_SP0    (30U)         //!< Bit position for AIPS_PACRU_SP0.
+#define BM_AIPS_PACRU_SP0    (0x40000000U) //!< Bit mask for AIPS_PACRU_SP0.
+#define BS_AIPS_PACRU_SP0    (1U)          //!< Bit field size in bits for AIPS_PACRU_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_SP0 field.
+#define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_SP0.
+#define BF_AIPS_PACRU_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP0), uint32_t) & BM_AIPS_PACRU_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_aips_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All AIPS module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_aips
+{
+    __IO hw_aips_mpra_t MPRA;              //!< [0x0] Master Privilege Register A
+    uint8_t _reserved0[28];
+    __IO hw_aips_pacra_t PACRA;            //!< [0x20] Peripheral Access Control Register
+    __IO hw_aips_pacrb_t PACRB;            //!< [0x24] Peripheral Access Control Register
+    __IO hw_aips_pacrc_t PACRC;            //!< [0x28] Peripheral Access Control Register
+    __IO hw_aips_pacrd_t PACRD;            //!< [0x2C] Peripheral Access Control Register
+    uint8_t _reserved1[16];
+    __IO hw_aips_pacre_t PACRE;            //!< [0x40] Peripheral Access Control Register
+    __IO hw_aips_pacrf_t PACRF;            //!< [0x44] Peripheral Access Control Register
+    __IO hw_aips_pacrg_t PACRG;            //!< [0x48] Peripheral Access Control Register
+    __IO hw_aips_pacrh_t PACRH;            //!< [0x4C] Peripheral Access Control Register
+    __IO hw_aips_pacri_t PACRI;            //!< [0x50] Peripheral Access Control Register
+    __IO hw_aips_pacrj_t PACRJ;            //!< [0x54] Peripheral Access Control Register
+    __IO hw_aips_pacrk_t PACRK;            //!< [0x58] Peripheral Access Control Register
+    __IO hw_aips_pacrl_t PACRL;            //!< [0x5C] Peripheral Access Control Register
+    __IO hw_aips_pacrm_t PACRM;            //!< [0x60] Peripheral Access Control Register
+    __IO hw_aips_pacrn_t PACRN;            //!< [0x64] Peripheral Access Control Register
+    __IO hw_aips_pacro_t PACRO;            //!< [0x68] Peripheral Access Control Register
+    __IO hw_aips_pacrp_t PACRP;            //!< [0x6C] Peripheral Access Control Register
+    uint8_t _reserved2[16];
+    __IO hw_aips_pacru_t PACRU;            //!< [0x80] Peripheral Access Control Register
+} hw_aips_t;
+#pragma pack()
+
+//! @brief Macro to access all AIPS registers.
+//! @param x AIPS instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_AIPS(0)</code>.
+#define HW_AIPS(x)     (*(hw_aips_t *) REGS_AIPS_BASE(x))
+#endif
+
+#endif // __HW_AIPS_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h
new file mode 100644
index 0000000000..0a2e6a288f
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h
@@ -0,0 +1,1078 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_AXBS_REGISTERS_H__
+#define __HW_AXBS_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - HW_AXBS_PRSn - Priority Registers Slave
+ * - HW_AXBS_CRSn - Control Register
+ * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
+ *
+ * - hw_axbs_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_AXBS_BASE
+#define HW_AXBS_INSTANCE_COUNT (1U) //!< Number of instances of the AXBS module.
+#define REGS_AXBS_BASE (0x40004000U) //!< Base address for AXBS.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_PRSn - Priority Registers Slave
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+typedef union _hw_axbs_prsn
+{
+    uint32_t U;
+    struct _hw_axbs_prsn_bitfields
+    {
+        uint32_t M0 : 3;               //!< [2:0] Master 0 Priority. Sets the arbitration
+                                       //! priority for this port on the associated slave port.
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t M1 : 3;               //!< [6:4] Master 1 Priority. Sets the arbitration
+                                       //! priority for this port on the associated slave port.
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t M2 : 3;               //!< [10:8] Master 2 Priority. Sets the arbitration
+                                       //! priority for this port on the associated slave port.
+        uint32_t RESERVED2 : 1;        //!< [11]
+        uint32_t M3 : 3;               //!< [14:12] Master 3 Priority. Sets the arbitration
+                                       //! priority for this port on the associated slave port.
+        uint32_t RESERVED3 : 1;        //!< [15]
+        uint32_t M4 : 3;               //!< [18:16] Master 4 Priority. Sets the arbitration
+                                       //! priority for this port on the associated slave port.
+        uint32_t RESERVED4 : 1;        //!< [19]
+        uint32_t M5 : 3;               //!< [22:20] Master 5 Priority. Sets the arbitration
+                                       //! priority for this port on the associated slave port.
+        uint32_t RESERVED5 : 9;        //!< [31:23]
+    } B;
+} hw_axbs_prsn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_PRSn register
+ */
+//@{
+#define HW_AXBS_PRSn_COUNT (5U)
+
+#define HW_AXBS_PRSn_ADDR(n)     (REGS_AXBS_BASE + 0x0U + (0x100U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_PRSn(n)          (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(n))
+#define HW_AXBS_PRSn_RD(n)       (HW_AXBS_PRSn(n).U)
+#define HW_AXBS_PRSn_WR(n, v)    (HW_AXBS_PRSn(n).U = (v))
+#define HW_AXBS_PRSn_SET(n, v)   (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) |  (v)))
+#define HW_AXBS_PRSn_CLR(n, v)   (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) & ~(v)))
+#define HW_AXBS_PRSn_TOG(n, v)   (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_PRSn bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRSn, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ *     port.
+ */
+//@{
+#define BP_AXBS_PRSn_M0      (0U)          //!< Bit position for AXBS_PRSn_M0.
+#define BM_AXBS_PRSn_M0      (0x00000007U) //!< Bit mask for AXBS_PRSn_M0.
+#define BS_AXBS_PRSn_M0      (3U)          //!< Bit field size in bits for AXBS_PRSn_M0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M0 field.
+#define BR_AXBS_PRSn_M0(n)   (HW_AXBS_PRSn(n).B.M0)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M0.
+#define BF_AXBS_PRSn_M0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M0), uint32_t) & BM_AXBS_PRSn_M0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0 field to a new value.
+#define BW_AXBS_PRSn_M0(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ *     port.
+ */
+//@{
+#define BP_AXBS_PRSn_M1      (4U)          //!< Bit position for AXBS_PRSn_M1.
+#define BM_AXBS_PRSn_M1      (0x00000070U) //!< Bit mask for AXBS_PRSn_M1.
+#define BS_AXBS_PRSn_M1      (3U)          //!< Bit field size in bits for AXBS_PRSn_M1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M1 field.
+#define BR_AXBS_PRSn_M1(n)   (HW_AXBS_PRSn(n).B.M1)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M1.
+#define BF_AXBS_PRSn_M1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M1), uint32_t) & BM_AXBS_PRSn_M1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1 field to a new value.
+#define BW_AXBS_PRSn_M1(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ *     port.
+ */
+//@{
+#define BP_AXBS_PRSn_M2      (8U)          //!< Bit position for AXBS_PRSn_M2.
+#define BM_AXBS_PRSn_M2      (0x00000700U) //!< Bit mask for AXBS_PRSn_M2.
+#define BS_AXBS_PRSn_M2      (3U)          //!< Bit field size in bits for AXBS_PRSn_M2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M2 field.
+#define BR_AXBS_PRSn_M2(n)   (HW_AXBS_PRSn(n).B.M2)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M2.
+#define BF_AXBS_PRSn_M2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M2), uint32_t) & BM_AXBS_PRSn_M2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2 field to a new value.
+#define BW_AXBS_PRSn_M2(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ *     port.
+ */
+//@{
+#define BP_AXBS_PRSn_M3      (12U)         //!< Bit position for AXBS_PRSn_M3.
+#define BM_AXBS_PRSn_M3      (0x00007000U) //!< Bit mask for AXBS_PRSn_M3.
+#define BS_AXBS_PRSn_M3      (3U)          //!< Bit field size in bits for AXBS_PRSn_M3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M3 field.
+#define BR_AXBS_PRSn_M3(n)   (HW_AXBS_PRSn(n).B.M3)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M3.
+#define BF_AXBS_PRSn_M3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M3), uint32_t) & BM_AXBS_PRSn_M3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3 field to a new value.
+#define BW_AXBS_PRSn_M3(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ *     port.
+ */
+//@{
+#define BP_AXBS_PRSn_M4      (16U)         //!< Bit position for AXBS_PRSn_M4.
+#define BM_AXBS_PRSn_M4      (0x00070000U) //!< Bit mask for AXBS_PRSn_M4.
+#define BS_AXBS_PRSn_M4      (3U)          //!< Bit field size in bits for AXBS_PRSn_M4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M4 field.
+#define BR_AXBS_PRSn_M4(n)   (HW_AXBS_PRSn(n).B.M4)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M4.
+#define BF_AXBS_PRSn_M4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M4), uint32_t) & BM_AXBS_PRSn_M4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4 field to a new value.
+#define BW_AXBS_PRSn_M4(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ *     port.
+ */
+//@{
+#define BP_AXBS_PRSn_M5      (20U)         //!< Bit position for AXBS_PRSn_M5.
+#define BM_AXBS_PRSn_M5      (0x00700000U) //!< Bit mask for AXBS_PRSn_M5.
+#define BS_AXBS_PRSn_M5      (3U)          //!< Bit field size in bits for AXBS_PRSn_M5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M5 field.
+#define BR_AXBS_PRSn_M5(n)   (HW_AXBS_PRSn(n).B.M5)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M5.
+#define BF_AXBS_PRSn_M5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M5), uint32_t) & BM_AXBS_PRSn_M5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5 field to a new value.
+#define BW_AXBS_PRSn_M5(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_CRSn - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_CRSn - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+typedef union _hw_axbs_crsn
+{
+    uint32_t U;
+    struct _hw_axbs_crsn_bitfields
+    {
+        uint32_t PARK : 3;             //!< [2:0] Park
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t PCTL : 2;             //!< [5:4] Parking Control
+        uint32_t RESERVED1 : 2;        //!< [7:6]
+        uint32_t ARB : 2;              //!< [9:8] Arbitration Mode
+        uint32_t RESERVED2 : 20;       //!< [29:10]
+        uint32_t HLP : 1;              //!< [30] Halt Low Priority
+        uint32_t RO : 1;               //!< [31] Read Only
+    } B;
+} hw_axbs_crsn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_CRSn register
+ */
+//@{
+#define HW_AXBS_CRSn_COUNT (5U)
+
+#define HW_AXBS_CRSn_ADDR(n)     (REGS_AXBS_BASE + 0x10U + (0x100U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_CRSn(n)          (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(n))
+#define HW_AXBS_CRSn_RD(n)       (HW_AXBS_CRSn(n).U)
+#define HW_AXBS_CRSn_WR(n, v)    (HW_AXBS_CRSn(n).U = (v))
+#define HW_AXBS_CRSn_SET(n, v)   (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) |  (v)))
+#define HW_AXBS_CRSn_CLR(n, v)   (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) & ~(v)))
+#define HW_AXBS_CRSn_TOG(n, v)   (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_CRSn bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRSn, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 000 - Park on master port M0
+ * - 001 - Park on master port M1
+ * - 010 - Park on master port M2
+ * - 011 - Park on master port M3
+ * - 100 - Park on master port M4
+ * - 101 - Park on master port M5
+ * - 110 - Park on master port M6
+ * - 111 - Park on master port M7
+ */
+//@{
+#define BP_AXBS_CRSn_PARK    (0U)          //!< Bit position for AXBS_CRSn_PARK.
+#define BM_AXBS_CRSn_PARK    (0x00000007U) //!< Bit mask for AXBS_CRSn_PARK.
+#define BS_AXBS_CRSn_PARK    (3U)          //!< Bit field size in bits for AXBS_CRSn_PARK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_PARK field.
+#define BR_AXBS_CRSn_PARK(n) (HW_AXBS_CRSn(n).B.PARK)
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_PARK.
+#define BF_AXBS_CRSn_PARK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PARK), uint32_t) & BM_AXBS_CRSn_PARK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PARK field to a new value.
+#define BW_AXBS_CRSn_PARK(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 11 - Reserved
+ */
+//@{
+#define BP_AXBS_CRSn_PCTL    (4U)          //!< Bit position for AXBS_CRSn_PCTL.
+#define BM_AXBS_CRSn_PCTL    (0x00000030U) //!< Bit mask for AXBS_CRSn_PCTL.
+#define BS_AXBS_CRSn_PCTL    (2U)          //!< Bit field size in bits for AXBS_CRSn_PCTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_PCTL field.
+#define BR_AXBS_CRSn_PCTL(n) (HW_AXBS_CRSn(n).B.PCTL)
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_PCTL.
+#define BF_AXBS_CRSn_PCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PCTL), uint32_t) & BM_AXBS_CRSn_PCTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCTL field to a new value.
+#define BW_AXBS_CRSn_PCTL(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 00 - Fixed priority
+ * - 01 - Round-robin, or rotating, priority
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_AXBS_CRSn_ARB     (8U)          //!< Bit position for AXBS_CRSn_ARB.
+#define BM_AXBS_CRSn_ARB     (0x00000300U) //!< Bit mask for AXBS_CRSn_ARB.
+#define BS_AXBS_CRSn_ARB     (2U)          //!< Bit field size in bits for AXBS_CRSn_ARB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_ARB field.
+#define BR_AXBS_CRSn_ARB(n)  (HW_AXBS_CRSn(n).B.ARB)
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_ARB.
+#define BF_AXBS_CRSn_ARB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_ARB), uint32_t) & BM_AXBS_CRSn_ARB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ARB field to a new value.
+#define BW_AXBS_CRSn_ARB(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0 - The low power mode request has the highest priority for arbitration on
+ *     this slave port
+ * - 1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+//@{
+#define BP_AXBS_CRSn_HLP     (30U)         //!< Bit position for AXBS_CRSn_HLP.
+#define BM_AXBS_CRSn_HLP     (0x40000000U) //!< Bit mask for AXBS_CRSn_HLP.
+#define BS_AXBS_CRSn_HLP     (1U)          //!< Bit field size in bits for AXBS_CRSn_HLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_HLP field.
+#define BR_AXBS_CRSn_HLP(n)  (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP))
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_HLP.
+#define BF_AXBS_CRSn_HLP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_HLP), uint32_t) & BM_AXBS_CRSn_HLP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HLP field to a new value.
+#define BW_AXBS_CRSn_HLP(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0 - The slave port's registers are writeable
+ * - 1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+//@{
+#define BP_AXBS_CRSn_RO      (31U)         //!< Bit position for AXBS_CRSn_RO.
+#define BM_AXBS_CRSn_RO      (0x80000000U) //!< Bit mask for AXBS_CRSn_RO.
+#define BS_AXBS_CRSn_RO      (1U)          //!< Bit field size in bits for AXBS_CRSn_RO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_RO field.
+#define BR_AXBS_CRSn_RO(n)   (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO))
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_RO.
+#define BF_AXBS_CRSn_RO(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_RO), uint32_t) & BM_AXBS_CRSn_RO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RO field to a new value.
+#define BW_AXBS_CRSn_RO(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR0 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr0
+{
+    uint32_t U;
+    struct _hw_axbs_mgpcr0_bitfields
+    {
+        uint32_t AULB : 3;             //!< [2:0] Arbitrates On Undefined Length Bursts
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_axbs_mgpcr0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+//@{
+#define HW_AXBS_MGPCR0_ADDR      (REGS_AXBS_BASE + 0x800U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR0           (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR)
+#define HW_AXBS_MGPCR0_RD()      (HW_AXBS_MGPCR0.U)
+#define HW_AXBS_MGPCR0_WR(v)     (HW_AXBS_MGPCR0.U = (v))
+#define HW_AXBS_MGPCR0_SET(v)    (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() |  (v)))
+#define HW_AXBS_MGPCR0_CLR(v)    (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() & ~(v)))
+#define HW_AXBS_MGPCR0_TOG(v)    (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR0_AULB  (0U)          //!< Bit position for AXBS_MGPCR0_AULB.
+#define BM_AXBS_MGPCR0_AULB  (0x00000007U) //!< Bit mask for AXBS_MGPCR0_AULB.
+#define BS_AXBS_MGPCR0_AULB  (3U)          //!< Bit field size in bits for AXBS_MGPCR0_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR0_AULB field.
+#define BR_AXBS_MGPCR0_AULB  (HW_AXBS_MGPCR0.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR0_AULB.
+#define BF_AXBS_MGPCR0_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR0_AULB), uint32_t) & BM_AXBS_MGPCR0_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR0_AULB(v) (HW_AXBS_MGPCR0_WR((HW_AXBS_MGPCR0_RD() & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR1 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr1
+{
+    uint32_t U;
+    struct _hw_axbs_mgpcr1_bitfields
+    {
+        uint32_t AULB : 3;             //!< [2:0] Arbitrates On Undefined Length Bursts
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_axbs_mgpcr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+//@{
+#define HW_AXBS_MGPCR1_ADDR      (REGS_AXBS_BASE + 0x900U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR1           (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR)
+#define HW_AXBS_MGPCR1_RD()      (HW_AXBS_MGPCR1.U)
+#define HW_AXBS_MGPCR1_WR(v)     (HW_AXBS_MGPCR1.U = (v))
+#define HW_AXBS_MGPCR1_SET(v)    (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() |  (v)))
+#define HW_AXBS_MGPCR1_CLR(v)    (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() & ~(v)))
+#define HW_AXBS_MGPCR1_TOG(v)    (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR1_AULB  (0U)          //!< Bit position for AXBS_MGPCR1_AULB.
+#define BM_AXBS_MGPCR1_AULB  (0x00000007U) //!< Bit mask for AXBS_MGPCR1_AULB.
+#define BS_AXBS_MGPCR1_AULB  (3U)          //!< Bit field size in bits for AXBS_MGPCR1_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR1_AULB field.
+#define BR_AXBS_MGPCR1_AULB  (HW_AXBS_MGPCR1.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR1_AULB.
+#define BF_AXBS_MGPCR1_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR1_AULB), uint32_t) & BM_AXBS_MGPCR1_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR1_AULB(v) (HW_AXBS_MGPCR1_WR((HW_AXBS_MGPCR1_RD() & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR2 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr2
+{
+    uint32_t U;
+    struct _hw_axbs_mgpcr2_bitfields
+    {
+        uint32_t AULB : 3;             //!< [2:0] Arbitrates On Undefined Length Bursts
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_axbs_mgpcr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+//@{
+#define HW_AXBS_MGPCR2_ADDR      (REGS_AXBS_BASE + 0xA00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR2           (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR)
+#define HW_AXBS_MGPCR2_RD()      (HW_AXBS_MGPCR2.U)
+#define HW_AXBS_MGPCR2_WR(v)     (HW_AXBS_MGPCR2.U = (v))
+#define HW_AXBS_MGPCR2_SET(v)    (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() |  (v)))
+#define HW_AXBS_MGPCR2_CLR(v)    (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() & ~(v)))
+#define HW_AXBS_MGPCR2_TOG(v)    (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR2_AULB  (0U)          //!< Bit position for AXBS_MGPCR2_AULB.
+#define BM_AXBS_MGPCR2_AULB  (0x00000007U) //!< Bit mask for AXBS_MGPCR2_AULB.
+#define BS_AXBS_MGPCR2_AULB  (3U)          //!< Bit field size in bits for AXBS_MGPCR2_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR2_AULB field.
+#define BR_AXBS_MGPCR2_AULB  (HW_AXBS_MGPCR2.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR2_AULB.
+#define BF_AXBS_MGPCR2_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR2_AULB), uint32_t) & BM_AXBS_MGPCR2_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR2_AULB(v) (HW_AXBS_MGPCR2_WR((HW_AXBS_MGPCR2_RD() & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR3 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr3
+{
+    uint32_t U;
+    struct _hw_axbs_mgpcr3_bitfields
+    {
+        uint32_t AULB : 3;             //!< [2:0] Arbitrates On Undefined Length Bursts
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_axbs_mgpcr3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+//@{
+#define HW_AXBS_MGPCR3_ADDR      (REGS_AXBS_BASE + 0xB00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR3           (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR)
+#define HW_AXBS_MGPCR3_RD()      (HW_AXBS_MGPCR3.U)
+#define HW_AXBS_MGPCR3_WR(v)     (HW_AXBS_MGPCR3.U = (v))
+#define HW_AXBS_MGPCR3_SET(v)    (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() |  (v)))
+#define HW_AXBS_MGPCR3_CLR(v)    (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() & ~(v)))
+#define HW_AXBS_MGPCR3_TOG(v)    (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR3_AULB  (0U)          //!< Bit position for AXBS_MGPCR3_AULB.
+#define BM_AXBS_MGPCR3_AULB  (0x00000007U) //!< Bit mask for AXBS_MGPCR3_AULB.
+#define BS_AXBS_MGPCR3_AULB  (3U)          //!< Bit field size in bits for AXBS_MGPCR3_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR3_AULB field.
+#define BR_AXBS_MGPCR3_AULB  (HW_AXBS_MGPCR3.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR3_AULB.
+#define BF_AXBS_MGPCR3_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR3_AULB), uint32_t) & BM_AXBS_MGPCR3_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR3_AULB(v) (HW_AXBS_MGPCR3_WR((HW_AXBS_MGPCR3_RD() & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR4 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr4
+{
+    uint32_t U;
+    struct _hw_axbs_mgpcr4_bitfields
+    {
+        uint32_t AULB : 3;             //!< [2:0] Arbitrates On Undefined Length Bursts
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_axbs_mgpcr4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+//@{
+#define HW_AXBS_MGPCR4_ADDR      (REGS_AXBS_BASE + 0xC00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR4           (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR)
+#define HW_AXBS_MGPCR4_RD()      (HW_AXBS_MGPCR4.U)
+#define HW_AXBS_MGPCR4_WR(v)     (HW_AXBS_MGPCR4.U = (v))
+#define HW_AXBS_MGPCR4_SET(v)    (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() |  (v)))
+#define HW_AXBS_MGPCR4_CLR(v)    (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() & ~(v)))
+#define HW_AXBS_MGPCR4_TOG(v)    (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR4_AULB  (0U)          //!< Bit position for AXBS_MGPCR4_AULB.
+#define BM_AXBS_MGPCR4_AULB  (0x00000007U) //!< Bit mask for AXBS_MGPCR4_AULB.
+#define BS_AXBS_MGPCR4_AULB  (3U)          //!< Bit field size in bits for AXBS_MGPCR4_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR4_AULB field.
+#define BR_AXBS_MGPCR4_AULB  (HW_AXBS_MGPCR4.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR4_AULB.
+#define BF_AXBS_MGPCR4_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR4_AULB), uint32_t) & BM_AXBS_MGPCR4_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR4_AULB(v) (HW_AXBS_MGPCR4_WR((HW_AXBS_MGPCR4_RD() & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR5 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr5
+{
+    uint32_t U;
+    struct _hw_axbs_mgpcr5_bitfields
+    {
+        uint32_t AULB : 3;             //!< [2:0] Arbitrates On Undefined Length Bursts
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_axbs_mgpcr5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+//@{
+#define HW_AXBS_MGPCR5_ADDR      (REGS_AXBS_BASE + 0xD00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR5           (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR)
+#define HW_AXBS_MGPCR5_RD()      (HW_AXBS_MGPCR5.U)
+#define HW_AXBS_MGPCR5_WR(v)     (HW_AXBS_MGPCR5.U = (v))
+#define HW_AXBS_MGPCR5_SET(v)    (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() |  (v)))
+#define HW_AXBS_MGPCR5_CLR(v)    (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() & ~(v)))
+#define HW_AXBS_MGPCR5_TOG(v)    (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR5_AULB  (0U)          //!< Bit position for AXBS_MGPCR5_AULB.
+#define BM_AXBS_MGPCR5_AULB  (0x00000007U) //!< Bit mask for AXBS_MGPCR5_AULB.
+#define BS_AXBS_MGPCR5_AULB  (3U)          //!< Bit field size in bits for AXBS_MGPCR5_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR5_AULB field.
+#define BR_AXBS_MGPCR5_AULB  (HW_AXBS_MGPCR5.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR5_AULB.
+#define BF_AXBS_MGPCR5_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR5_AULB), uint32_t) & BM_AXBS_MGPCR5_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR5_AULB(v) (HW_AXBS_MGPCR5_WR((HW_AXBS_MGPCR5_RD() & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_axbs_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All AXBS module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_axbs
+{
+    struct {
+        __IO hw_axbs_prsn_t PRSn;          //!< [0x0] Priority Registers Slave
+        uint8_t _reserved0[12];
+        __IO hw_axbs_crsn_t CRSn;          //!< [0x10] Control Register
+        uint8_t _reserved1[236];
+    } SLAVE[5];
+    uint8_t _reserved0[768];
+    __IO hw_axbs_mgpcr0_t MGPCR0;          //!< [0x800] Master General Purpose Control Register
+    uint8_t _reserved1[252];
+    __IO hw_axbs_mgpcr1_t MGPCR1;          //!< [0x900] Master General Purpose Control Register
+    uint8_t _reserved2[252];
+    __IO hw_axbs_mgpcr2_t MGPCR2;          //!< [0xA00] Master General Purpose Control Register
+    uint8_t _reserved3[252];
+    __IO hw_axbs_mgpcr3_t MGPCR3;          //!< [0xB00] Master General Purpose Control Register
+    uint8_t _reserved4[252];
+    __IO hw_axbs_mgpcr4_t MGPCR4;          //!< [0xC00] Master General Purpose Control Register
+    uint8_t _reserved5[252];
+    __IO hw_axbs_mgpcr5_t MGPCR5;          //!< [0xD00] Master General Purpose Control Register
+} hw_axbs_t;
+#pragma pack()
+
+//! @brief Macro to access all AXBS registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_AXBS</code>.
+#define HW_AXBS        (*(hw_axbs_t *) REGS_AXBS_BASE)
+#endif
+
+#endif // __HW_AXBS_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h
new file mode 100644
index 0000000000..f8d04b256e
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h
@@ -0,0 +1,3963 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CAN_REGISTERS_H__
+#define __HW_CAN_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - HW_CAN_MCR - Module Configuration Register
+ * - HW_CAN_CTRL1 - Control 1 register
+ * - HW_CAN_TIMER - Free Running Timer
+ * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - HW_CAN_RX14MASK - Rx 14 Mask register
+ * - HW_CAN_RX15MASK - Rx 15 Mask register
+ * - HW_CAN_ECR - Error Counter
+ * - HW_CAN_ESR1 - Error and Status 1 register
+ * - HW_CAN_IMASK1 - Interrupt Masks 1 register
+ * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
+ * - HW_CAN_CTRL2 - Control 2 register
+ * - HW_CAN_ESR2 - Error and Status 2 register
+ * - HW_CAN_CRCR - CRC Register
+ * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - HW_CAN_RXFIR - Rx FIFO Information Register
+ * - HW_CAN_CS - Message Buffer 0 CS Register
+ * - HW_CAN_ID - Message Buffer 0 ID Register
+ * - HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - HW_CAN_RXIMRn - Rx Individual Mask Registers
+ *
+ * - hw_can_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CAN_BASE
+#define HW_CAN_INSTANCE_COUNT (1U) //!< Number of instances of the CAN module.
+#define HW_CAN0 (0U) //!< Instance number for CAN0.
+#define REGS_CAN0_BASE (0x40024000U) //!< Base address for CAN0.
+
+//! @brief Table of base addresses for CAN instances.
+static const uint32_t __g_regs_CAN_base_addresses[] = {
+        REGS_CAN0_BASE,
+    };
+
+//! @brief Get the base address of CAN by instance number.
+//! @param x CAN instance number, from 0 through 0.
+#define REGS_CAN_BASE(x) (__g_regs_CAN_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of CAN.
+#define REGS_CAN_INSTANCE(b) ((b) == REGS_CAN0_BASE ? HW_CAN0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_MCR - Module Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+typedef union _hw_can_mcr
+{
+    uint32_t U;
+    struct _hw_can_mcr_bitfields
+    {
+        uint32_t MAXMB : 7;            //!< [6:0] Number Of The Last Message Buffer
+        uint32_t RESERVED0 : 1;        //!< [7]
+        uint32_t IDAM : 2;             //!< [9:8] ID Acceptance Mode
+        uint32_t RESERVED1 : 2;        //!< [11:10]
+        uint32_t AEN : 1;              //!< [12] Abort Enable
+        uint32_t LPRIOEN : 1;          //!< [13] Local Priority Enable
+        uint32_t RESERVED2 : 2;        //!< [15:14]
+        uint32_t IRMQ : 1;             //!< [16] Individual Rx Masking And Queue Enable
+        uint32_t SRXDIS : 1;           //!< [17] Self Reception Disable
+        uint32_t RESERVED3 : 1;        //!< [18]
+        uint32_t WAKSRC : 1;           //!< [19] Wake Up Source
+        uint32_t LPMACK : 1;           //!< [20] Low-Power Mode Acknowledge
+        uint32_t WRNEN : 1;            //!< [21] Warning Interrupt Enable
+        uint32_t SLFWAK : 1;           //!< [22] Self Wake Up
+        uint32_t SUPV : 1;             //!< [23] Supervisor Mode
+        uint32_t FRZACK : 1;           //!< [24] Freeze Mode Acknowledge
+        uint32_t SOFTRST : 1;          //!< [25] Soft Reset
+        uint32_t WAKMSK : 1;           //!< [26] Wake Up Interrupt Mask
+        uint32_t NOTRDY : 1;           //!< [27] FlexCAN Not Ready
+        uint32_t HALT : 1;             //!< [28] Halt FlexCAN
+        uint32_t RFEN : 1;             //!< [29] Rx FIFO Enable
+        uint32_t FRZ : 1;              //!< [30] Freeze Enable
+        uint32_t MDIS : 1;             //!< [31] Module Disable
+    } B;
+} hw_can_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+//@{
+#define HW_CAN_MCR_ADDR(x)       (REGS_CAN_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_MCR(x)            (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
+#define HW_CAN_MCR_RD(x)         (HW_CAN_MCR(x).U)
+#define HW_CAN_MCR_WR(x, v)      (HW_CAN_MCR(x).U = (v))
+#define HW_CAN_MCR_SET(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) |  (v)))
+#define HW_CAN_MCR_CLR(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
+#define HW_CAN_MCR_TOG(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+//@{
+#define BP_CAN_MCR_MAXMB     (0U)          //!< Bit position for CAN_MCR_MAXMB.
+#define BM_CAN_MCR_MAXMB     (0x0000007FU) //!< Bit mask for CAN_MCR_MAXMB.
+#define BS_CAN_MCR_MAXMB     (7U)          //!< Bit field size in bits for CAN_MCR_MAXMB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_MAXMB field.
+#define BR_CAN_MCR_MAXMB(x)  (HW_CAN_MCR(x).B.MAXMB)
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_MAXMB.
+#define BF_CAN_MCR_MAXMB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MAXMB), uint32_t) & BM_CAN_MCR_MAXMB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAXMB field to a new value.
+#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
+ * - 11 - Format D: All frames rejected.
+ */
+//@{
+#define BP_CAN_MCR_IDAM      (8U)          //!< Bit position for CAN_MCR_IDAM.
+#define BM_CAN_MCR_IDAM      (0x00000300U) //!< Bit mask for CAN_MCR_IDAM.
+#define BS_CAN_MCR_IDAM      (2U)          //!< Bit field size in bits for CAN_MCR_IDAM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_IDAM field.
+#define BR_CAN_MCR_IDAM(x)   (HW_CAN_MCR(x).B.IDAM)
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_IDAM.
+#define BF_CAN_MCR_IDAM(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IDAM), uint32_t) & BM_CAN_MCR_IDAM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDAM field to a new value.
+#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0 - Abort disabled.
+ * - 1 - Abort enabled.
+ */
+//@{
+#define BP_CAN_MCR_AEN       (12U)         //!< Bit position for CAN_MCR_AEN.
+#define BM_CAN_MCR_AEN       (0x00001000U) //!< Bit mask for CAN_MCR_AEN.
+#define BS_CAN_MCR_AEN       (1U)          //!< Bit field size in bits for CAN_MCR_AEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_AEN field.
+#define BR_CAN_MCR_AEN(x)    (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_AEN.
+#define BF_CAN_MCR_AEN(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_AEN), uint32_t) & BM_CAN_MCR_AEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AEN field to a new value.
+#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0 - Local Priority disabled.
+ * - 1 - Local Priority enabled.
+ */
+//@{
+#define BP_CAN_MCR_LPRIOEN   (13U)         //!< Bit position for CAN_MCR_LPRIOEN.
+#define BM_CAN_MCR_LPRIOEN   (0x00002000U) //!< Bit mask for CAN_MCR_LPRIOEN.
+#define BS_CAN_MCR_LPRIOEN   (1U)          //!< Bit field size in bits for CAN_MCR_LPRIOEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_LPRIOEN field.
+#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_LPRIOEN.
+#define BF_CAN_MCR_LPRIOEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_LPRIOEN), uint32_t) & BM_CAN_MCR_LPRIOEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPRIOEN field to a new value.
+#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 1 - Individual Rx masking and queue feature are enabled.
+ */
+//@{
+#define BP_CAN_MCR_IRMQ      (16U)         //!< Bit position for CAN_MCR_IRMQ.
+#define BM_CAN_MCR_IRMQ      (0x00010000U) //!< Bit mask for CAN_MCR_IRMQ.
+#define BS_CAN_MCR_IRMQ      (1U)          //!< Bit field size in bits for CAN_MCR_IRMQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_IRMQ field.
+#define BR_CAN_MCR_IRMQ(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_IRMQ.
+#define BF_CAN_MCR_IRMQ(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IRMQ), uint32_t) & BM_CAN_MCR_IRMQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRMQ field to a new value.
+#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Self reception enabled.
+ * - 1 - Self reception disabled.
+ */
+//@{
+#define BP_CAN_MCR_SRXDIS    (17U)         //!< Bit position for CAN_MCR_SRXDIS.
+#define BM_CAN_MCR_SRXDIS    (0x00020000U) //!< Bit mask for CAN_MCR_SRXDIS.
+#define BS_CAN_MCR_SRXDIS    (1U)          //!< Bit field size in bits for CAN_MCR_SRXDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SRXDIS field.
+#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SRXDIS.
+#define BF_CAN_MCR_SRXDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SRXDIS), uint32_t) & BM_CAN_MCR_SRXDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRXDIS field to a new value.
+#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+//@{
+#define BP_CAN_MCR_WAKSRC    (19U)         //!< Bit position for CAN_MCR_WAKSRC.
+#define BM_CAN_MCR_WAKSRC    (0x00080000U) //!< Bit mask for CAN_MCR_WAKSRC.
+#define BS_CAN_MCR_WAKSRC    (1U)          //!< Bit field size in bits for CAN_MCR_WAKSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_WAKSRC field.
+#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_WAKSRC.
+#define BF_CAN_MCR_WAKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKSRC), uint32_t) & BM_CAN_MCR_WAKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKSRC field to a new value.
+#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0 - FlexCAN is not in a low-power mode.
+ * - 1 - FlexCAN is in a low-power mode.
+ */
+//@{
+#define BP_CAN_MCR_LPMACK    (20U)         //!< Bit position for CAN_MCR_LPMACK.
+#define BM_CAN_MCR_LPMACK    (0x00100000U) //!< Bit mask for CAN_MCR_LPMACK.
+#define BS_CAN_MCR_LPMACK    (1U)          //!< Bit field size in bits for CAN_MCR_LPMACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_LPMACK field.
+#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+//@{
+#define BP_CAN_MCR_WRNEN     (21U)         //!< Bit position for CAN_MCR_WRNEN.
+#define BM_CAN_MCR_WRNEN     (0x00200000U) //!< Bit mask for CAN_MCR_WRNEN.
+#define BS_CAN_MCR_WRNEN     (1U)          //!< Bit field size in bits for CAN_MCR_WRNEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_WRNEN field.
+#define BR_CAN_MCR_WRNEN(x)  (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_WRNEN.
+#define BF_CAN_MCR_WRNEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WRNEN), uint32_t) & BM_CAN_MCR_WRNEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRNEN field to a new value.
+#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0 - FlexCAN Self Wake Up feature is disabled.
+ * - 1 - FlexCAN Self Wake Up feature is enabled.
+ */
+//@{
+#define BP_CAN_MCR_SLFWAK    (22U)         //!< Bit position for CAN_MCR_SLFWAK.
+#define BM_CAN_MCR_SLFWAK    (0x00400000U) //!< Bit mask for CAN_MCR_SLFWAK.
+#define BS_CAN_MCR_SLFWAK    (1U)          //!< Bit field size in bits for CAN_MCR_SLFWAK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SLFWAK field.
+#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SLFWAK.
+#define BF_CAN_MCR_SLFWAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SLFWAK), uint32_t) & BM_CAN_MCR_SLFWAK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLFWAK field to a new value.
+#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
+ *     access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+//@{
+#define BP_CAN_MCR_SUPV      (23U)         //!< Bit position for CAN_MCR_SUPV.
+#define BM_CAN_MCR_SUPV      (0x00800000U) //!< Bit mask for CAN_MCR_SUPV.
+#define BS_CAN_MCR_SUPV      (1U)          //!< Bit field size in bits for CAN_MCR_SUPV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SUPV field.
+#define BR_CAN_MCR_SUPV(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SUPV.
+#define BF_CAN_MCR_SUPV(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SUPV), uint32_t) & BM_CAN_MCR_SUPV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SUPV field to a new value.
+#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+//@{
+#define BP_CAN_MCR_FRZACK    (24U)         //!< Bit position for CAN_MCR_FRZACK.
+#define BM_CAN_MCR_FRZACK    (0x01000000U) //!< Bit mask for CAN_MCR_FRZACK.
+#define BS_CAN_MCR_FRZACK    (1U)          //!< Bit field size in bits for CAN_MCR_FRZACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_FRZACK field.
+#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0 - No reset request.
+ * - 1 - Resets the registers affected by soft reset.
+ */
+//@{
+#define BP_CAN_MCR_SOFTRST   (25U)         //!< Bit position for CAN_MCR_SOFTRST.
+#define BM_CAN_MCR_SOFTRST   (0x02000000U) //!< Bit mask for CAN_MCR_SOFTRST.
+#define BS_CAN_MCR_SOFTRST   (1U)          //!< Bit field size in bits for CAN_MCR_SOFTRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SOFTRST field.
+#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SOFTRST.
+#define BF_CAN_MCR_SOFTRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SOFTRST), uint32_t) & BM_CAN_MCR_SOFTRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFTRST field to a new value.
+#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0 - Wake Up Interrupt is disabled.
+ * - 1 - Wake Up Interrupt is enabled.
+ */
+//@{
+#define BP_CAN_MCR_WAKMSK    (26U)         //!< Bit position for CAN_MCR_WAKMSK.
+#define BM_CAN_MCR_WAKMSK    (0x04000000U) //!< Bit mask for CAN_MCR_WAKMSK.
+#define BS_CAN_MCR_WAKMSK    (1U)          //!< Bit field size in bits for CAN_MCR_WAKMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_WAKMSK field.
+#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_WAKMSK.
+#define BF_CAN_MCR_WAKMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKMSK), uint32_t) & BM_CAN_MCR_WAKMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKMSK field to a new value.
+#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
+ *     mode.
+ * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+//@{
+#define BP_CAN_MCR_NOTRDY    (27U)         //!< Bit position for CAN_MCR_NOTRDY.
+#define BM_CAN_MCR_NOTRDY    (0x08000000U) //!< Bit mask for CAN_MCR_NOTRDY.
+#define BS_CAN_MCR_NOTRDY    (1U)          //!< Bit field size in bits for CAN_MCR_NOTRDY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_NOTRDY field.
+#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0 - No Freeze mode request.
+ * - 1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+//@{
+#define BP_CAN_MCR_HALT      (28U)         //!< Bit position for CAN_MCR_HALT.
+#define BM_CAN_MCR_HALT      (0x10000000U) //!< Bit mask for CAN_MCR_HALT.
+#define BS_CAN_MCR_HALT      (1U)          //!< Bit field size in bits for CAN_MCR_HALT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_HALT field.
+#define BR_CAN_MCR_HALT(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_HALT.
+#define BF_CAN_MCR_HALT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_HALT), uint32_t) & BM_CAN_MCR_HALT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HALT field to a new value.
+#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Rx FIFO not enabled.
+ * - 1 - Rx FIFO enabled.
+ */
+//@{
+#define BP_CAN_MCR_RFEN      (29U)         //!< Bit position for CAN_MCR_RFEN.
+#define BM_CAN_MCR_RFEN      (0x20000000U) //!< Bit mask for CAN_MCR_RFEN.
+#define BS_CAN_MCR_RFEN      (1U)          //!< Bit field size in bits for CAN_MCR_RFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_RFEN field.
+#define BR_CAN_MCR_RFEN(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_RFEN.
+#define BF_CAN_MCR_RFEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_RFEN), uint32_t) & BM_CAN_MCR_RFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFEN field to a new value.
+#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0 - Not enabled to enter Freeze mode.
+ * - 1 - Enabled to enter Freeze mode.
+ */
+//@{
+#define BP_CAN_MCR_FRZ       (30U)         //!< Bit position for CAN_MCR_FRZ.
+#define BM_CAN_MCR_FRZ       (0x40000000U) //!< Bit mask for CAN_MCR_FRZ.
+#define BS_CAN_MCR_FRZ       (1U)          //!< Bit field size in bits for CAN_MCR_FRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_FRZ field.
+#define BR_CAN_MCR_FRZ(x)    (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_FRZ.
+#define BF_CAN_MCR_FRZ(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_FRZ), uint32_t) & BM_CAN_MCR_FRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRZ field to a new value.
+#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0 - Enable the FlexCAN module.
+ * - 1 - Disable the FlexCAN module.
+ */
+//@{
+#define BP_CAN_MCR_MDIS      (31U)         //!< Bit position for CAN_MCR_MDIS.
+#define BM_CAN_MCR_MDIS      (0x80000000U) //!< Bit mask for CAN_MCR_MDIS.
+#define BS_CAN_MCR_MDIS      (1U)          //!< Bit field size in bits for CAN_MCR_MDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_MDIS field.
+#define BR_CAN_MCR_MDIS(x)   (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_MDIS.
+#define BF_CAN_MCR_MDIS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MDIS), uint32_t) & BM_CAN_MCR_MDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MDIS field to a new value.
+#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CTRL1 - Control 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+typedef union _hw_can_ctrl1
+{
+    uint32_t U;
+    struct _hw_can_ctrl1_bitfields
+    {
+        uint32_t PROPSEG : 3;          //!< [2:0] Propagation Segment
+        uint32_t LOM : 1;              //!< [3] Listen-Only Mode
+        uint32_t LBUF : 1;             //!< [4] Lowest Buffer Transmitted First
+        uint32_t TSYN : 1;             //!< [5] Timer Sync
+        uint32_t BOFFREC : 1;          //!< [6] Bus Off Recovery
+        uint32_t SMP : 1;              //!< [7] CAN Bit Sampling
+        uint32_t RESERVED0 : 2;        //!< [9:8]
+        uint32_t RWRNMSK : 1;          //!< [10] Rx Warning Interrupt Mask
+        uint32_t TWRNMSK : 1;          //!< [11] Tx Warning Interrupt Mask
+        uint32_t LPB : 1;              //!< [12] Loop Back Mode
+        uint32_t CLKSRC : 1;           //!< [13] CAN Engine Clock Source
+        uint32_t ERRMSK : 1;           //!< [14] Error Mask
+        uint32_t BOFFMSK : 1;          //!< [15] Bus Off Mask
+        uint32_t PSEG2 : 3;            //!< [18:16] Phase Segment 2
+        uint32_t PSEG1 : 3;            //!< [21:19] Phase Segment 1
+        uint32_t RJW : 2;              //!< [23:22] Resync Jump Width
+        uint32_t PRESDIV : 8;          //!< [31:24] Prescaler Division Factor
+    } B;
+} hw_can_ctrl1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+//@{
+#define HW_CAN_CTRL1_ADDR(x)     (REGS_CAN_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CTRL1(x)          (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
+#define HW_CAN_CTRL1_RD(x)       (HW_CAN_CTRL1(x).U)
+#define HW_CAN_CTRL1_WR(x, v)    (HW_CAN_CTRL1(x).U = (v))
+#define HW_CAN_CTRL1_SET(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) |  (v)))
+#define HW_CAN_CTRL1_CLR(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
+#define HW_CAN_CTRL1_TOG(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+//@{
+#define BP_CAN_CTRL1_PROPSEG (0U)          //!< Bit position for CAN_CTRL1_PROPSEG.
+#define BM_CAN_CTRL1_PROPSEG (0x00000007U) //!< Bit mask for CAN_CTRL1_PROPSEG.
+#define BS_CAN_CTRL1_PROPSEG (3U)          //!< Bit field size in bits for CAN_CTRL1_PROPSEG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PROPSEG field.
+#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PROPSEG.
+#define BF_CAN_CTRL1_PROPSEG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PROPSEG), uint32_t) & BM_CAN_CTRL1_PROPSEG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROPSEG field to a new value.
+#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0 - Listen-Only mode is deactivated.
+ * - 1 - FlexCAN module operates in Listen-Only mode.
+ */
+//@{
+#define BP_CAN_CTRL1_LOM     (3U)          //!< Bit position for CAN_CTRL1_LOM.
+#define BM_CAN_CTRL1_LOM     (0x00000008U) //!< Bit mask for CAN_CTRL1_LOM.
+#define BS_CAN_CTRL1_LOM     (1U)          //!< Bit field size in bits for CAN_CTRL1_LOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_LOM field.
+#define BR_CAN_CTRL1_LOM(x)  (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_LOM.
+#define BF_CAN_CTRL1_LOM(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LOM), uint32_t) & BM_CAN_CTRL1_LOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOM field to a new value.
+#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0 - Buffer with highest priority is transmitted first.
+ * - 1 - Lowest number buffer is transmitted first.
+ */
+//@{
+#define BP_CAN_CTRL1_LBUF    (4U)          //!< Bit position for CAN_CTRL1_LBUF.
+#define BM_CAN_CTRL1_LBUF    (0x00000010U) //!< Bit mask for CAN_CTRL1_LBUF.
+#define BS_CAN_CTRL1_LBUF    (1U)          //!< Bit field size in bits for CAN_CTRL1_LBUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_LBUF field.
+#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_LBUF.
+#define BF_CAN_CTRL1_LBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LBUF), uint32_t) & BM_CAN_CTRL1_LBUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBUF field to a new value.
+#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Timer Sync feature disabled
+ * - 1 - Timer Sync feature enabled
+ */
+//@{
+#define BP_CAN_CTRL1_TSYN    (5U)          //!< Bit position for CAN_CTRL1_TSYN.
+#define BM_CAN_CTRL1_TSYN    (0x00000020U) //!< Bit mask for CAN_CTRL1_TSYN.
+#define BS_CAN_CTRL1_TSYN    (1U)          //!< Bit field size in bits for CAN_CTRL1_TSYN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_TSYN field.
+#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_TSYN.
+#define BF_CAN_CTRL1_TSYN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TSYN), uint32_t) & BM_CAN_CTRL1_TSYN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSYN field to a new value.
+#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
+ *     2.0 part B.
+ * - 1 - Automatic recovering from Bus Off state disabled.
+ */
+//@{
+#define BP_CAN_CTRL1_BOFFREC (6U)          //!< Bit position for CAN_CTRL1_BOFFREC.
+#define BM_CAN_CTRL1_BOFFREC (0x00000040U) //!< Bit mask for CAN_CTRL1_BOFFREC.
+#define BS_CAN_CTRL1_BOFFREC (1U)          //!< Bit field size in bits for CAN_CTRL1_BOFFREC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_BOFFREC field.
+#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_BOFFREC.
+#define BF_CAN_CTRL1_BOFFREC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFREC), uint32_t) & BM_CAN_CTRL1_BOFFREC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOFFREC field to a new value.
+#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0 - Just one sample is used to determine the bit value.
+ * - 1 - Three samples are used to determine the value of the received bit: the
+ *     regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+//@{
+#define BP_CAN_CTRL1_SMP     (7U)          //!< Bit position for CAN_CTRL1_SMP.
+#define BM_CAN_CTRL1_SMP     (0x00000080U) //!< Bit mask for CAN_CTRL1_SMP.
+#define BS_CAN_CTRL1_SMP     (1U)          //!< Bit field size in bits for CAN_CTRL1_SMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_SMP field.
+#define BR_CAN_CTRL1_SMP(x)  (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_SMP.
+#define BF_CAN_CTRL1_SMP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_SMP), uint32_t) & BM_CAN_CTRL1_SMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMP field to a new value.
+#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0 - Rx Warning Interrupt disabled.
+ * - 1 - Rx Warning Interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_RWRNMSK (10U)         //!< Bit position for CAN_CTRL1_RWRNMSK.
+#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) //!< Bit mask for CAN_CTRL1_RWRNMSK.
+#define BS_CAN_CTRL1_RWRNMSK (1U)          //!< Bit field size in bits for CAN_CTRL1_RWRNMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_RWRNMSK field.
+#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_RWRNMSK.
+#define BF_CAN_CTRL1_RWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RWRNMSK), uint32_t) & BM_CAN_CTRL1_RWRNMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWRNMSK field to a new value.
+#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0 - Tx Warning Interrupt disabled.
+ * - 1 - Tx Warning Interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_TWRNMSK (11U)         //!< Bit position for CAN_CTRL1_TWRNMSK.
+#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) //!< Bit mask for CAN_CTRL1_TWRNMSK.
+#define BS_CAN_CTRL1_TWRNMSK (1U)          //!< Bit field size in bits for CAN_CTRL1_TWRNMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_TWRNMSK field.
+#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_TWRNMSK.
+#define BF_CAN_CTRL1_TWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TWRNMSK), uint32_t) & BM_CAN_CTRL1_TWRNMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWRNMSK field to a new value.
+#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0 - Loop Back disabled.
+ * - 1 - Loop Back enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_LPB     (12U)         //!< Bit position for CAN_CTRL1_LPB.
+#define BM_CAN_CTRL1_LPB     (0x00001000U) //!< Bit mask for CAN_CTRL1_LPB.
+#define BS_CAN_CTRL1_LPB     (1U)          //!< Bit field size in bits for CAN_CTRL1_LPB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_LPB field.
+#define BR_CAN_CTRL1_LPB(x)  (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_LPB.
+#define BF_CAN_CTRL1_LPB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LPB), uint32_t) & BM_CAN_CTRL1_LPB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPB field to a new value.
+#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 1 - The CAN engine clock source is the peripheral clock.
+ */
+//@{
+#define BP_CAN_CTRL1_CLKSRC  (13U)         //!< Bit position for CAN_CTRL1_CLKSRC.
+#define BM_CAN_CTRL1_CLKSRC  (0x00002000U) //!< Bit mask for CAN_CTRL1_CLKSRC.
+#define BS_CAN_CTRL1_CLKSRC  (1U)          //!< Bit field size in bits for CAN_CTRL1_CLKSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_CLKSRC field.
+#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_CLKSRC.
+#define BF_CAN_CTRL1_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_CLKSRC), uint32_t) & BM_CAN_CTRL1_CLKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKSRC field to a new value.
+#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0 - Error interrupt disabled.
+ * - 1 - Error interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_ERRMSK  (14U)         //!< Bit position for CAN_CTRL1_ERRMSK.
+#define BM_CAN_CTRL1_ERRMSK  (0x00004000U) //!< Bit mask for CAN_CTRL1_ERRMSK.
+#define BS_CAN_CTRL1_ERRMSK  (1U)          //!< Bit field size in bits for CAN_CTRL1_ERRMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_ERRMSK field.
+#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_ERRMSK.
+#define BF_CAN_CTRL1_ERRMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_ERRMSK), uint32_t) & BM_CAN_CTRL1_ERRMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERRMSK field to a new value.
+#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0 - Bus Off interrupt disabled.
+ * - 1 - Bus Off interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_BOFFMSK (15U)         //!< Bit position for CAN_CTRL1_BOFFMSK.
+#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) //!< Bit mask for CAN_CTRL1_BOFFMSK.
+#define BS_CAN_CTRL1_BOFFMSK (1U)          //!< Bit field size in bits for CAN_CTRL1_BOFFMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_BOFFMSK field.
+#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_BOFFMSK.
+#define BF_CAN_CTRL1_BOFFMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFMSK), uint32_t) & BM_CAN_CTRL1_BOFFMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOFFMSK field to a new value.
+#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+//@{
+#define BP_CAN_CTRL1_PSEG2   (16U)         //!< Bit position for CAN_CTRL1_PSEG2.
+#define BM_CAN_CTRL1_PSEG2   (0x00070000U) //!< Bit mask for CAN_CTRL1_PSEG2.
+#define BS_CAN_CTRL1_PSEG2   (3U)          //!< Bit field size in bits for CAN_CTRL1_PSEG2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PSEG2 field.
+#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PSEG2.
+#define BF_CAN_CTRL1_PSEG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG2), uint32_t) & BM_CAN_CTRL1_PSEG2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSEG2 field to a new value.
+#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+//@{
+#define BP_CAN_CTRL1_PSEG1   (19U)         //!< Bit position for CAN_CTRL1_PSEG1.
+#define BM_CAN_CTRL1_PSEG1   (0x00380000U) //!< Bit mask for CAN_CTRL1_PSEG1.
+#define BS_CAN_CTRL1_PSEG1   (3U)          //!< Bit field size in bits for CAN_CTRL1_PSEG1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PSEG1 field.
+#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PSEG1.
+#define BF_CAN_CTRL1_PSEG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG1), uint32_t) & BM_CAN_CTRL1_PSEG1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSEG1 field to a new value.
+#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+//@{
+#define BP_CAN_CTRL1_RJW     (22U)         //!< Bit position for CAN_CTRL1_RJW.
+#define BM_CAN_CTRL1_RJW     (0x00C00000U) //!< Bit mask for CAN_CTRL1_RJW.
+#define BS_CAN_CTRL1_RJW     (2U)          //!< Bit field size in bits for CAN_CTRL1_RJW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_RJW field.
+#define BR_CAN_CTRL1_RJW(x)  (HW_CAN_CTRL1(x).B.RJW)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_RJW.
+#define BF_CAN_CTRL1_RJW(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RJW), uint32_t) & BM_CAN_CTRL1_RJW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RJW field to a new value.
+#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+//@{
+#define BP_CAN_CTRL1_PRESDIV (24U)         //!< Bit position for CAN_CTRL1_PRESDIV.
+#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) //!< Bit mask for CAN_CTRL1_PRESDIV.
+#define BS_CAN_CTRL1_PRESDIV (8U)          //!< Bit field size in bits for CAN_CTRL1_PRESDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PRESDIV field.
+#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PRESDIV.
+#define BF_CAN_CTRL1_PRESDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PRESDIV), uint32_t) & BM_CAN_CTRL1_PRESDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESDIV field to a new value.
+#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_TIMER - Free Running Timer
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+typedef union _hw_can_timer
+{
+    uint32_t U;
+    struct _hw_can_timer_bitfields
+    {
+        uint32_t TIMER : 16;           //!< [15:0] Timer Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_can_timer_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+//@{
+#define HW_CAN_TIMER_ADDR(x)     (REGS_CAN_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_TIMER(x)          (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
+#define HW_CAN_TIMER_RD(x)       (HW_CAN_TIMER(x).U)
+#define HW_CAN_TIMER_WR(x, v)    (HW_CAN_TIMER(x).U = (v))
+#define HW_CAN_TIMER_SET(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) |  (v)))
+#define HW_CAN_TIMER_CLR(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
+#define HW_CAN_TIMER_TOG(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+//@{
+#define BP_CAN_TIMER_TIMER   (0U)          //!< Bit position for CAN_TIMER_TIMER.
+#define BM_CAN_TIMER_TIMER   (0x0000FFFFU) //!< Bit mask for CAN_TIMER_TIMER.
+#define BS_CAN_TIMER_TIMER   (16U)         //!< Bit field size in bits for CAN_TIMER_TIMER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_TIMER_TIMER field.
+#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
+#endif
+
+//! @brief Format value for bitfield CAN_TIMER_TIMER.
+#define BF_CAN_TIMER_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_TIMER_TIMER), uint32_t) & BM_CAN_TIMER_TIMER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMER field to a new value.
+#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+typedef union _hw_can_rxmgmask
+{
+    uint32_t U;
+    struct _hw_can_rxmgmask_bitfields
+    {
+        uint32_t MG : 32;              //!< [31:0] Rx Mailboxes Global Mask Bits
+    } B;
+} hw_can_rxmgmask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+//@{
+#define HW_CAN_RXMGMASK_ADDR(x)  (REGS_CAN_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXMGMASK(x)       (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
+#define HW_CAN_RXMGMASK_RD(x)    (HW_CAN_RXMGMASK(x).U)
+#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
+#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) |  (v)))
+#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
+#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXMGMASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
+ *
+ * These bits mask the Mailbox filter bits. Note that the alignment with the ID
+ * word of the Mailbox is not perfect as the two most significant MG bits affect
+ * the fields RTR and IDE, which are located in the Control and Status word of
+ * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
+ * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
+ * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
+ * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
+ * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
+ * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
+ * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
+ * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
+ * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RXMGMASK_MG   (0U)          //!< Bit position for CAN_RXMGMASK_MG.
+#define BM_CAN_RXMGMASK_MG   (0xFFFFFFFFU) //!< Bit mask for CAN_RXMGMASK_MG.
+#define BS_CAN_RXMGMASK_MG   (32U)         //!< Bit field size in bits for CAN_RXMGMASK_MG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXMGMASK_MG field.
+#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RXMGMASK_MG.
+#define BF_CAN_RXMGMASK_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXMGMASK_MG), uint32_t) & BM_CAN_RXMGMASK_MG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MG field to a new value.
+#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RX14MASK - Rx 14 Mask register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+typedef union _hw_can_rx14mask
+{
+    uint32_t U;
+    struct _hw_can_rx14mask_bitfields
+    {
+        uint32_t RX14M : 32;           //!< [31:0] Rx Buffer 14 Mask Bits
+    } B;
+} hw_can_rx14mask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+//@{
+#define HW_CAN_RX14MASK_ADDR(x)  (REGS_CAN_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RX14MASK(x)       (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
+#define HW_CAN_RX14MASK_RD(x)    (HW_CAN_RX14MASK(x).U)
+#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
+#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) |  (v)))
+#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
+#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RX14MASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
+ *
+ * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
+ * that RXMGMASK masks other Mailboxes' filters. See the description of the
+ * CAN_RXMGMASK register.
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RX14MASK_RX14M (0U)         //!< Bit position for CAN_RX14MASK_RX14M.
+#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) //!< Bit mask for CAN_RX14MASK_RX14M.
+#define BS_CAN_RX14MASK_RX14M (32U)        //!< Bit field size in bits for CAN_RX14MASK_RX14M.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RX14MASK_RX14M field.
+#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RX14MASK_RX14M.
+#define BF_CAN_RX14MASK_RX14M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX14MASK_RX14M), uint32_t) & BM_CAN_RX14MASK_RX14M)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX14M field to a new value.
+#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RX15MASK - Rx 15 Mask register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+typedef union _hw_can_rx15mask
+{
+    uint32_t U;
+    struct _hw_can_rx15mask_bitfields
+    {
+        uint32_t RX15M : 32;           //!< [31:0] Rx Buffer 15 Mask Bits
+    } B;
+} hw_can_rx15mask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+//@{
+#define HW_CAN_RX15MASK_ADDR(x)  (REGS_CAN_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RX15MASK(x)       (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
+#define HW_CAN_RX15MASK_RD(x)    (HW_CAN_RX15MASK(x).U)
+#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
+#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) |  (v)))
+#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
+#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RX15MASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
+ *
+ * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
+ * that RXMGMASK masks other Mailboxes' filters. See the description of the
+ * CAN_RXMGMASK register.
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RX15MASK_RX15M (0U)         //!< Bit position for CAN_RX15MASK_RX15M.
+#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) //!< Bit mask for CAN_RX15MASK_RX15M.
+#define BS_CAN_RX15MASK_RX15M (32U)        //!< Bit field size in bits for CAN_RX15MASK_RX15M.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RX15MASK_RX15M field.
+#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RX15MASK_RX15M.
+#define BF_CAN_RX15MASK_RX15M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX15MASK_RX15M), uint32_t) & BM_CAN_RX15MASK_RX15M)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX15M field to a new value.
+#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ECR - Error Counter
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+typedef union _hw_can_ecr
+{
+    uint32_t U;
+    struct _hw_can_ecr_bitfields
+    {
+        uint32_t TXERRCNT : 8;         //!< [7:0] Transmit Error Counter
+        uint32_t RXERRCNT : 8;         //!< [15:8] Receive Error Counter
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_can_ecr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+//@{
+#define HW_CAN_ECR_ADDR(x)       (REGS_CAN_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ECR(x)            (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
+#define HW_CAN_ECR_RD(x)         (HW_CAN_ECR(x).U)
+#define HW_CAN_ECR_WR(x, v)      (HW_CAN_ECR(x).U = (v))
+#define HW_CAN_ECR_SET(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) |  (v)))
+#define HW_CAN_ECR_CLR(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
+#define HW_CAN_ECR_TOG(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+//@{
+#define BP_CAN_ECR_TXERRCNT  (0U)          //!< Bit position for CAN_ECR_TXERRCNT.
+#define BM_CAN_ECR_TXERRCNT  (0x000000FFU) //!< Bit mask for CAN_ECR_TXERRCNT.
+#define BS_CAN_ECR_TXERRCNT  (8U)          //!< Bit field size in bits for CAN_ECR_TXERRCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ECR_TXERRCNT field.
+#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
+#endif
+
+//! @brief Format value for bitfield CAN_ECR_TXERRCNT.
+#define BF_CAN_ECR_TXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_TXERRCNT), uint32_t) & BM_CAN_ECR_TXERRCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXERRCNT field to a new value.
+#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+//@{
+#define BP_CAN_ECR_RXERRCNT  (8U)          //!< Bit position for CAN_ECR_RXERRCNT.
+#define BM_CAN_ECR_RXERRCNT  (0x0000FF00U) //!< Bit mask for CAN_ECR_RXERRCNT.
+#define BS_CAN_ECR_RXERRCNT  (8U)          //!< Bit field size in bits for CAN_ECR_RXERRCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ECR_RXERRCNT field.
+#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
+#endif
+
+//! @brief Format value for bitfield CAN_ECR_RXERRCNT.
+#define BF_CAN_ECR_RXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_RXERRCNT), uint32_t) & BM_CAN_ECR_RXERRCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXERRCNT field to a new value.
+#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ESR1 - Error and Status 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+typedef union _hw_can_esr1
+{
+    uint32_t U;
+    struct _hw_can_esr1_bitfields
+    {
+        uint32_t WAKINT : 1;           //!< [0] Wake-Up Interrupt
+        uint32_t ERRINT : 1;           //!< [1] Error Interrupt
+        uint32_t BOFFINT : 1;          //!< [2] Bus Off Interrupt
+        uint32_t RX : 1;               //!< [3] FlexCAN In Reception
+        uint32_t FLTCONF : 2;          //!< [5:4] Fault Confinement State
+        uint32_t TX : 1;               //!< [6] FlexCAN In Transmission
+        uint32_t IDLE : 1;             //!< [7]
+        uint32_t RXWRN : 1;            //!< [8] Rx Error Warning
+        uint32_t TXWRN : 1;            //!< [9] TX Error Warning
+        uint32_t STFERR : 1;           //!< [10] Stuffing Error
+        uint32_t FRMERR : 1;           //!< [11] Form Error
+        uint32_t CRCERR : 1;           //!< [12] Cyclic Redundancy Check Error
+        uint32_t ACKERR : 1;           //!< [13] Acknowledge Error
+        uint32_t BIT0ERR : 1;          //!< [14] Bit0 Error
+        uint32_t BIT1ERR : 1;          //!< [15] Bit1 Error
+        uint32_t RWRNINT : 1;          //!< [16] Rx Warning Interrupt Flag
+        uint32_t TWRNINT : 1;          //!< [17] Tx Warning Interrupt Flag
+        uint32_t SYNCH : 1;            //!< [18] CAN Synchronization Status
+        uint32_t RESERVED0 : 13;       //!< [31:19]
+    } B;
+} hw_can_esr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+//@{
+#define HW_CAN_ESR1_ADDR(x)      (REGS_CAN_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ESR1(x)           (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
+#define HW_CAN_ESR1_RD(x)        (HW_CAN_ESR1(x).U)
+#define HW_CAN_ESR1_WR(x, v)     (HW_CAN_ESR1(x).U = (v))
+#define HW_CAN_ESR1_SET(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) |  (v)))
+#define HW_CAN_ESR1_CLR(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
+#define HW_CAN_ESR1_TOG(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+//@{
+#define BP_CAN_ESR1_WAKINT   (0U)          //!< Bit position for CAN_ESR1_WAKINT.
+#define BM_CAN_ESR1_WAKINT   (0x00000001U) //!< Bit mask for CAN_ESR1_WAKINT.
+#define BS_CAN_ESR1_WAKINT   (1U)          //!< Bit field size in bits for CAN_ESR1_WAKINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_WAKINT field.
+#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_WAKINT.
+#define BF_CAN_ESR1_WAKINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_WAKINT), uint32_t) & BM_CAN_ESR1_WAKINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKINT field to a new value.
+#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+//@{
+#define BP_CAN_ESR1_ERRINT   (1U)          //!< Bit position for CAN_ESR1_ERRINT.
+#define BM_CAN_ESR1_ERRINT   (0x00000002U) //!< Bit mask for CAN_ESR1_ERRINT.
+#define BS_CAN_ESR1_ERRINT   (1U)          //!< Bit field size in bits for CAN_ESR1_ERRINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_ERRINT field.
+#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_ERRINT.
+#define BF_CAN_ESR1_ERRINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_ERRINT), uint32_t) & BM_CAN_ESR1_ERRINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERRINT field to a new value.
+#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - FlexCAN module entered Bus Off state.
+ */
+//@{
+#define BP_CAN_ESR1_BOFFINT  (2U)          //!< Bit position for CAN_ESR1_BOFFINT.
+#define BM_CAN_ESR1_BOFFINT  (0x00000004U) //!< Bit mask for CAN_ESR1_BOFFINT.
+#define BS_CAN_ESR1_BOFFINT  (1U)          //!< Bit field size in bits for CAN_ESR1_BOFFINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_BOFFINT field.
+#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_BOFFINT.
+#define BF_CAN_ESR1_BOFFINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_BOFFINT), uint32_t) & BM_CAN_ESR1_BOFFINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOFFINT field to a new value.
+#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - FlexCAN is not receiving a message.
+ * - 1 - FlexCAN is receiving a message.
+ */
+//@{
+#define BP_CAN_ESR1_RX       (3U)          //!< Bit position for CAN_ESR1_RX.
+#define BM_CAN_ESR1_RX       (0x00000008U) //!< Bit mask for CAN_ESR1_RX.
+#define BS_CAN_ESR1_RX       (1U)          //!< Bit field size in bits for CAN_ESR1_RX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_RX field.
+#define BR_CAN_ESR1_RX(x)    (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 00 - Error Active
+ * - 01 - Error Passive
+ * - 1x - Bus Off
+ */
+//@{
+#define BP_CAN_ESR1_FLTCONF  (4U)          //!< Bit position for CAN_ESR1_FLTCONF.
+#define BM_CAN_ESR1_FLTCONF  (0x00000030U) //!< Bit mask for CAN_ESR1_FLTCONF.
+#define BS_CAN_ESR1_FLTCONF  (2U)          //!< Bit field size in bits for CAN_ESR1_FLTCONF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_FLTCONF field.
+#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - FlexCAN is not transmitting a message.
+ * - 1 - FlexCAN is transmitting a message.
+ */
+//@{
+#define BP_CAN_ESR1_TX       (6U)          //!< Bit position for CAN_ESR1_TX.
+#define BM_CAN_ESR1_TX       (0x00000040U) //!< Bit mask for CAN_ESR1_TX.
+#define BS_CAN_ESR1_TX       (1U)          //!< Bit field size in bits for CAN_ESR1_TX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_TX field.
+#define BR_CAN_ESR1_TX(x)    (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - CAN bus is now IDLE.
+ */
+//@{
+#define BP_CAN_ESR1_IDLE     (7U)          //!< Bit position for CAN_ESR1_IDLE.
+#define BM_CAN_ESR1_IDLE     (0x00000080U) //!< Bit mask for CAN_ESR1_IDLE.
+#define BS_CAN_ESR1_IDLE     (1U)          //!< Bit field size in bits for CAN_ESR1_IDLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_IDLE field.
+#define BR_CAN_ESR1_IDLE(x)  (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - RXERRCNT is greater than or equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_RXWRN    (8U)          //!< Bit position for CAN_ESR1_RXWRN.
+#define BM_CAN_ESR1_RXWRN    (0x00000100U) //!< Bit mask for CAN_ESR1_RXWRN.
+#define BS_CAN_ESR1_RXWRN    (1U)          //!< Bit field size in bits for CAN_ESR1_RXWRN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_RXWRN field.
+#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - TXERRCNT is greater than or equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_TXWRN    (9U)          //!< Bit position for CAN_ESR1_TXWRN.
+#define BM_CAN_ESR1_TXWRN    (0x00000200U) //!< Bit mask for CAN_ESR1_TXWRN.
+#define BS_CAN_ESR1_TXWRN    (1U)          //!< Bit field size in bits for CAN_ESR1_TXWRN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_TXWRN field.
+#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - A Stuffing Error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_STFERR   (10U)         //!< Bit position for CAN_ESR1_STFERR.
+#define BM_CAN_ESR1_STFERR   (0x00000400U) //!< Bit mask for CAN_ESR1_STFERR.
+#define BS_CAN_ESR1_STFERR   (1U)          //!< Bit field size in bits for CAN_ESR1_STFERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_STFERR field.
+#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - A Form Error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_FRMERR   (11U)         //!< Bit position for CAN_ESR1_FRMERR.
+#define BM_CAN_ESR1_FRMERR   (0x00000800U) //!< Bit mask for CAN_ESR1_FRMERR.
+#define BS_CAN_ESR1_FRMERR   (1U)          //!< Bit field size in bits for CAN_ESR1_FRMERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_FRMERR field.
+#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - A CRC error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_CRCERR   (12U)         //!< Bit position for CAN_ESR1_CRCERR.
+#define BM_CAN_ESR1_CRCERR   (0x00001000U) //!< Bit mask for CAN_ESR1_CRCERR.
+#define BS_CAN_ESR1_CRCERR   (1U)          //!< Bit field size in bits for CAN_ESR1_CRCERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_CRCERR field.
+#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - An ACK error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_ACKERR   (13U)         //!< Bit position for CAN_ESR1_ACKERR.
+#define BM_CAN_ESR1_ACKERR   (0x00002000U) //!< Bit mask for CAN_ESR1_ACKERR.
+#define BS_CAN_ESR1_ACKERR   (1U)          //!< Bit field size in bits for CAN_ESR1_ACKERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_ACKERR field.
+#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - At least one bit sent as dominant is received as recessive.
+ */
+//@{
+#define BP_CAN_ESR1_BIT0ERR  (14U)         //!< Bit position for CAN_ESR1_BIT0ERR.
+#define BM_CAN_ESR1_BIT0ERR  (0x00004000U) //!< Bit mask for CAN_ESR1_BIT0ERR.
+#define BS_CAN_ESR1_BIT0ERR  (1U)          //!< Bit field size in bits for CAN_ESR1_BIT0ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_BIT0ERR field.
+#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - At least one bit sent as recessive is received as dominant.
+ */
+//@{
+#define BP_CAN_ESR1_BIT1ERR  (15U)         //!< Bit position for CAN_ESR1_BIT1ERR.
+#define BM_CAN_ESR1_BIT1ERR  (0x00008000U) //!< Bit mask for CAN_ESR1_BIT1ERR.
+#define BS_CAN_ESR1_BIT1ERR  (1U)          //!< Bit field size in bits for CAN_ESR1_BIT1ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_BIT1ERR field.
+#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - The Rx error counter transitioned from less than 96 to greater than or
+ *     equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_RWRNINT  (16U)         //!< Bit position for CAN_ESR1_RWRNINT.
+#define BM_CAN_ESR1_RWRNINT  (0x00010000U) //!< Bit mask for CAN_ESR1_RWRNINT.
+#define BS_CAN_ESR1_RWRNINT  (1U)          //!< Bit field size in bits for CAN_ESR1_RWRNINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_RWRNINT field.
+#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_RWRNINT.
+#define BF_CAN_ESR1_RWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_RWRNINT), uint32_t) & BM_CAN_ESR1_RWRNINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWRNINT field to a new value.
+#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - The Tx error counter transitioned from less than 96 to greater than or
+ *     equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_TWRNINT  (17U)         //!< Bit position for CAN_ESR1_TWRNINT.
+#define BM_CAN_ESR1_TWRNINT  (0x00020000U) //!< Bit mask for CAN_ESR1_TWRNINT.
+#define BS_CAN_ESR1_TWRNINT  (1U)          //!< Bit field size in bits for CAN_ESR1_TWRNINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_TWRNINT field.
+#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_TWRNINT.
+#define BF_CAN_ESR1_TWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_TWRNINT), uint32_t) & BM_CAN_ESR1_TWRNINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWRNINT field to a new value.
+#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - FlexCAN is not synchronized to the CAN bus.
+ * - 1 - FlexCAN is synchronized to the CAN bus.
+ */
+//@{
+#define BP_CAN_ESR1_SYNCH    (18U)         //!< Bit position for CAN_ESR1_SYNCH.
+#define BM_CAN_ESR1_SYNCH    (0x00040000U) //!< Bit mask for CAN_ESR1_SYNCH.
+#define BS_CAN_ESR1_SYNCH    (1U)          //!< Bit field size in bits for CAN_ESR1_SYNCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_SYNCH field.
+#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_IMASK1 - Interrupt Masks 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+typedef union _hw_can_imask1
+{
+    uint32_t U;
+    struct _hw_can_imask1_bitfields
+    {
+        uint32_t BUFLM : 32;           //!< [31:0] Buffer MB i Mask
+    } B;
+} hw_can_imask1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+//@{
+#define HW_CAN_IMASK1_ADDR(x)    (REGS_CAN_BASE(x) + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_IMASK1(x)         (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
+#define HW_CAN_IMASK1_RD(x)      (HW_CAN_IMASK1(x).U)
+#define HW_CAN_IMASK1_WR(x, v)   (HW_CAN_IMASK1(x).U = (v))
+#define HW_CAN_IMASK1_SET(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) |  (v)))
+#define HW_CAN_IMASK1_CLR(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
+#define HW_CAN_IMASK1_TOG(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_IMASK1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
+ *
+ * Each bit enables or disables the corresponding FlexCAN Message Buffer
+ * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
+ * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
+ *
+ * Values:
+ * - 0 - The corresponding buffer Interrupt is disabled.
+ * - 1 - The corresponding buffer Interrupt is enabled.
+ */
+//@{
+#define BP_CAN_IMASK1_BUFLM  (0U)          //!< Bit position for CAN_IMASK1_BUFLM.
+#define BM_CAN_IMASK1_BUFLM  (0xFFFFFFFFU) //!< Bit mask for CAN_IMASK1_BUFLM.
+#define BS_CAN_IMASK1_BUFLM  (32U)         //!< Bit field size in bits for CAN_IMASK1_BUFLM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IMASK1_BUFLM field.
+#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_IMASK1_BUFLM.
+#define BF_CAN_IMASK1_BUFLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IMASK1_BUFLM), uint32_t) & BM_CAN_IMASK1_BUFLM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUFLM field to a new value.
+#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_IFLAG1 - Interrupt Flags 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+typedef union _hw_can_iflag1
+{
+    uint32_t U;
+    struct _hw_can_iflag1_bitfields
+    {
+        uint32_t BUF0I : 1;            //!< [0] Buffer MB0 Interrupt Or "reserved"
+        uint32_t BUF4TO1I : 4;         //!< [4:1] Buffer MB i Interrupt Or "reserved"
+        uint32_t BUF5I : 1;            //!< [5] Buffer MB5 Interrupt Or "Frames
+                                       //! available in Rx FIFO"
+        uint32_t BUF6I : 1;            //!< [6] Buffer MB6 Interrupt Or "Rx FIFO Warning"
+        uint32_t BUF7I : 1;            //!< [7] Buffer MB7 Interrupt Or "Rx FIFO
+                                       //! Overflow"
+        uint32_t BUF31TO8I : 24;       //!< [31:8] Buffer MBi Interrupt
+    } B;
+} hw_can_iflag1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+//@{
+#define HW_CAN_IFLAG1_ADDR(x)    (REGS_CAN_BASE(x) + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_IFLAG1(x)         (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
+#define HW_CAN_IFLAG1_RD(x)      (HW_CAN_IFLAG1(x).U)
+#define HW_CAN_IFLAG1_WR(x, v)   (HW_CAN_IFLAG1(x).U = (v))
+#define HW_CAN_IFLAG1_SET(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) |  (v)))
+#define HW_CAN_IFLAG1_CLR(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
+#define HW_CAN_IFLAG1_TOG(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF0I  (0U)          //!< Bit position for CAN_IFLAG1_BUF0I.
+#define BM_CAN_IFLAG1_BUF0I  (0x00000001U) //!< Bit mask for CAN_IFLAG1_BUF0I.
+#define BS_CAN_IFLAG1_BUF0I  (1U)          //!< Bit field size in bits for CAN_IFLAG1_BUF0I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF0I field.
+#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF0I.
+#define BF_CAN_IFLAG1_BUF0I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF0I), uint32_t) & BM_CAN_IFLAG1_BUF0I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF0I field to a new value.
+#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF4TO1I (1U)        //!< Bit position for CAN_IFLAG1_BUF4TO1I.
+#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) //!< Bit mask for CAN_IFLAG1_BUF4TO1I.
+#define BS_CAN_IFLAG1_BUF4TO1I (4U)        //!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field.
+#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I.
+#define BF_CAN_IFLAG1_BUF4TO1I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF4TO1I), uint32_t) & BM_CAN_IFLAG1_BUF4TO1I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF4TO1I field to a new value.
+#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF5I  (5U)          //!< Bit position for CAN_IFLAG1_BUF5I.
+#define BM_CAN_IFLAG1_BUF5I  (0x00000020U) //!< Bit mask for CAN_IFLAG1_BUF5I.
+#define BS_CAN_IFLAG1_BUF5I  (1U)          //!< Bit field size in bits for CAN_IFLAG1_BUF5I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF5I field.
+#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF5I.
+#define BF_CAN_IFLAG1_BUF5I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF5I), uint32_t) & BM_CAN_IFLAG1_BUF5I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF5I field to a new value.
+#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF6I  (6U)          //!< Bit position for CAN_IFLAG1_BUF6I.
+#define BM_CAN_IFLAG1_BUF6I  (0x00000040U) //!< Bit mask for CAN_IFLAG1_BUF6I.
+#define BS_CAN_IFLAG1_BUF6I  (1U)          //!< Bit field size in bits for CAN_IFLAG1_BUF6I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF6I field.
+#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF6I.
+#define BF_CAN_IFLAG1_BUF6I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF6I), uint32_t) & BM_CAN_IFLAG1_BUF6I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF6I field to a new value.
+#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF7I  (7U)          //!< Bit position for CAN_IFLAG1_BUF7I.
+#define BM_CAN_IFLAG1_BUF7I  (0x00000080U) //!< Bit mask for CAN_IFLAG1_BUF7I.
+#define BS_CAN_IFLAG1_BUF7I  (1U)          //!< Bit field size in bits for CAN_IFLAG1_BUF7I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF7I field.
+#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF7I.
+#define BF_CAN_IFLAG1_BUF7I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF7I), uint32_t) & BM_CAN_IFLAG1_BUF7I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF7I field to a new value.
+#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception.
+ * - 1 - The corresponding buffer has successfully completed transmission or
+ *     reception.
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF31TO8I (8U)       //!< Bit position for CAN_IFLAG1_BUF31TO8I.
+#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) //!< Bit mask for CAN_IFLAG1_BUF31TO8I.
+#define BS_CAN_IFLAG1_BUF31TO8I (24U)      //!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field.
+#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I.
+#define BF_CAN_IFLAG1_BUF31TO8I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF31TO8I), uint32_t) & BM_CAN_IFLAG1_BUF31TO8I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF31TO8I field to a new value.
+#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CTRL2 - Control 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+typedef union _hw_can_ctrl2
+{
+    uint32_t U;
+    struct _hw_can_ctrl2_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t EACEN : 1;            //!< [16] Entire Frame Arbitration Field
+                                       //! Comparison Enable For Rx Mailboxes
+        uint32_t RRS : 1;              //!< [17] Remote Request Storing
+        uint32_t MRP : 1;              //!< [18] Mailboxes Reception Priority
+        uint32_t TASD : 5;             //!< [23:19] Tx Arbitration Start Delay
+        uint32_t RFFN : 4;             //!< [27:24] Number Of Rx FIFO Filters
+        uint32_t WRMFRZ : 1;           //!< [28] Write-Access To Memory In Freeze Mode
+        uint32_t RESERVED1 : 3;        //!< [31:29]
+    } B;
+} hw_can_ctrl2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+//@{
+#define HW_CAN_CTRL2_ADDR(x)     (REGS_CAN_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CTRL2(x)          (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
+#define HW_CAN_CTRL2_RD(x)       (HW_CAN_CTRL2(x).U)
+#define HW_CAN_CTRL2_WR(x, v)    (HW_CAN_CTRL2(x).U = (v))
+#define HW_CAN_CTRL2_SET(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) |  (v)))
+#define HW_CAN_CTRL2_CLR(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
+#define HW_CAN_CTRL2_TOG(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
+ *     their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+//@{
+#define BP_CAN_CTRL2_EACEN   (16U)         //!< Bit position for CAN_CTRL2_EACEN.
+#define BM_CAN_CTRL2_EACEN   (0x00010000U) //!< Bit mask for CAN_CTRL2_EACEN.
+#define BS_CAN_CTRL2_EACEN   (1U)          //!< Bit field size in bits for CAN_CTRL2_EACEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_EACEN field.
+#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_EACEN.
+#define BF_CAN_CTRL2_EACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_EACEN), uint32_t) & BM_CAN_CTRL2_EACEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EACEN field to a new value.
+#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Remote Response Frame is generated.
+ * - 1 - Remote Request Frame is stored.
+ */
+//@{
+#define BP_CAN_CTRL2_RRS     (17U)         //!< Bit position for CAN_CTRL2_RRS.
+#define BM_CAN_CTRL2_RRS     (0x00020000U) //!< Bit mask for CAN_CTRL2_RRS.
+#define BS_CAN_CTRL2_RRS     (1U)          //!< Bit field size in bits for CAN_CTRL2_RRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_RRS field.
+#define BR_CAN_CTRL2_RRS(x)  (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_RRS.
+#define BF_CAN_CTRL2_RRS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RRS), uint32_t) & BM_CAN_CTRL2_RRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RRS field to a new value.
+#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+//@{
+#define BP_CAN_CTRL2_MRP     (18U)         //!< Bit position for CAN_CTRL2_MRP.
+#define BM_CAN_CTRL2_MRP     (0x00040000U) //!< Bit mask for CAN_CTRL2_MRP.
+#define BS_CAN_CTRL2_MRP     (1U)          //!< Bit field size in bits for CAN_CTRL2_MRP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_MRP field.
+#define BR_CAN_CTRL2_MRP(x)  (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_MRP.
+#define BF_CAN_CTRL2_MRP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_MRP), uint32_t) & BM_CAN_CTRL2_MRP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MRP field to a new value.
+#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+//@{
+#define BP_CAN_CTRL2_TASD    (19U)         //!< Bit position for CAN_CTRL2_TASD.
+#define BM_CAN_CTRL2_TASD    (0x00F80000U) //!< Bit mask for CAN_CTRL2_TASD.
+#define BS_CAN_CTRL2_TASD    (5U)          //!< Bit field size in bits for CAN_CTRL2_TASD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_TASD field.
+#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_TASD.
+#define BF_CAN_CTRL2_TASD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_TASD), uint32_t) & BM_CAN_CTRL2_TASD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TASD field to a new value.
+#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+//@{
+#define BP_CAN_CTRL2_RFFN    (24U)         //!< Bit position for CAN_CTRL2_RFFN.
+#define BM_CAN_CTRL2_RFFN    (0x0F000000U) //!< Bit mask for CAN_CTRL2_RFFN.
+#define BS_CAN_CTRL2_RFFN    (4U)          //!< Bit field size in bits for CAN_CTRL2_RFFN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_RFFN field.
+#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_RFFN.
+#define BF_CAN_CTRL2_RFFN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RFFN), uint32_t) & BM_CAN_CTRL2_RFFN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFFN field to a new value.
+#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0 - Maintain the write access restrictions.
+ * - 1 - Enable unrestricted write access to FlexCAN memory.
+ */
+//@{
+#define BP_CAN_CTRL2_WRMFRZ  (28U)         //!< Bit position for CAN_CTRL2_WRMFRZ.
+#define BM_CAN_CTRL2_WRMFRZ  (0x10000000U) //!< Bit mask for CAN_CTRL2_WRMFRZ.
+#define BS_CAN_CTRL2_WRMFRZ  (1U)          //!< Bit field size in bits for CAN_CTRL2_WRMFRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_WRMFRZ field.
+#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_WRMFRZ.
+#define BF_CAN_CTRL2_WRMFRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_WRMFRZ), uint32_t) & BM_CAN_CTRL2_WRMFRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRMFRZ field to a new value.
+#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ESR2 - Error and Status 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+typedef union _hw_can_esr2
+{
+    uint32_t U;
+    struct _hw_can_esr2_bitfields
+    {
+        uint32_t RESERVED0 : 13;       //!< [12:0]
+        uint32_t IMB : 1;              //!< [13] Inactive Mailbox
+        uint32_t VPS : 1;              //!< [14] Valid Priority Status
+        uint32_t RESERVED1 : 1;        //!< [15]
+        uint32_t LPTM : 7;             //!< [22:16] Lowest Priority Tx Mailbox
+        uint32_t RESERVED2 : 9;        //!< [31:23]
+    } B;
+} hw_can_esr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+//@{
+#define HW_CAN_ESR2_ADDR(x)      (REGS_CAN_BASE(x) + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ESR2(x)           (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
+#define HW_CAN_ESR2_RD(x)        (HW_CAN_ESR2(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
+ *     content is the number of the first one.
+ */
+//@{
+#define BP_CAN_ESR2_IMB      (13U)         //!< Bit position for CAN_ESR2_IMB.
+#define BM_CAN_ESR2_IMB      (0x00002000U) //!< Bit mask for CAN_ESR2_IMB.
+#define BS_CAN_ESR2_IMB      (1U)          //!< Bit field size in bits for CAN_ESR2_IMB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR2_IMB field.
+#define BR_CAN_ESR2_IMB(x)   (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0 - Contents of IMB and LPTM are invalid.
+ * - 1 - Contents of IMB and LPTM are valid.
+ */
+//@{
+#define BP_CAN_ESR2_VPS      (14U)         //!< Bit position for CAN_ESR2_VPS.
+#define BM_CAN_ESR2_VPS      (0x00004000U) //!< Bit mask for CAN_ESR2_VPS.
+#define BS_CAN_ESR2_VPS      (1U)          //!< Bit field size in bits for CAN_ESR2_VPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR2_VPS field.
+#define BR_CAN_ESR2_VPS(x)   (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+//@{
+#define BP_CAN_ESR2_LPTM     (16U)         //!< Bit position for CAN_ESR2_LPTM.
+#define BM_CAN_ESR2_LPTM     (0x007F0000U) //!< Bit mask for CAN_ESR2_LPTM.
+#define BS_CAN_ESR2_LPTM     (7U)          //!< Bit field size in bits for CAN_ESR2_LPTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR2_LPTM field.
+#define BR_CAN_ESR2_LPTM(x)  (HW_CAN_ESR2(x).B.LPTM)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CRCR - CRC Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+typedef union _hw_can_crcr
+{
+    uint32_t U;
+    struct _hw_can_crcr_bitfields
+    {
+        uint32_t TXCRC : 15;           //!< [14:0] CRC Transmitted
+        uint32_t RESERVED0 : 1;        //!< [15]
+        uint32_t MBCRC : 7;            //!< [22:16] CRC Mailbox
+        uint32_t RESERVED1 : 9;        //!< [31:23]
+    } B;
+} hw_can_crcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+//@{
+#define HW_CAN_CRCR_ADDR(x)      (REGS_CAN_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CRCR(x)           (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
+#define HW_CAN_CRCR_RD(x)        (HW_CAN_CRCR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+//@{
+#define BP_CAN_CRCR_TXCRC    (0U)          //!< Bit position for CAN_CRCR_TXCRC.
+#define BM_CAN_CRCR_TXCRC    (0x00007FFFU) //!< Bit mask for CAN_CRCR_TXCRC.
+#define BS_CAN_CRCR_TXCRC    (15U)         //!< Bit field size in bits for CAN_CRCR_TXCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CRCR_TXCRC field.
+#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+//@{
+#define BP_CAN_CRCR_MBCRC    (16U)         //!< Bit position for CAN_CRCR_MBCRC.
+#define BM_CAN_CRCR_MBCRC    (0x007F0000U) //!< Bit mask for CAN_CRCR_MBCRC.
+#define BS_CAN_CRCR_MBCRC    (7U)          //!< Bit field size in bits for CAN_CRCR_MBCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CRCR_MBCRC field.
+#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXFGMASK - Rx FIFO Global Mask register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+typedef union _hw_can_rxfgmask
+{
+    uint32_t U;
+    struct _hw_can_rxfgmask_bitfields
+    {
+        uint32_t FGM : 32;             //!< [31:0] Rx FIFO Global Mask Bits
+    } B;
+} hw_can_rxfgmask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+//@{
+#define HW_CAN_RXFGMASK_ADDR(x)  (REGS_CAN_BASE(x) + 0x48U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXFGMASK(x)       (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
+#define HW_CAN_RXFGMASK_RD(x)    (HW_CAN_RXFGMASK(x).U)
+#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
+#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) |  (v)))
+#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
+#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXFGMASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
+ *
+ * These bits mask the ID Filter Table elements bits in a perfect alignment. The
+ * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
+ * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
+ * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
+ * the fourteen most significant bits of the Identifier of the incoming frame are
+ * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
+ * the format C only the eight most significant bits of the Identifier of the
+ * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
+ * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
+ * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RXFGMASK_FGM  (0U)          //!< Bit position for CAN_RXFGMASK_FGM.
+#define BM_CAN_RXFGMASK_FGM  (0xFFFFFFFFU) //!< Bit mask for CAN_RXFGMASK_FGM.
+#define BS_CAN_RXFGMASK_FGM  (32U)         //!< Bit field size in bits for CAN_RXFGMASK_FGM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXFGMASK_FGM field.
+#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RXFGMASK_FGM.
+#define BF_CAN_RXFGMASK_FGM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXFGMASK_FGM), uint32_t) & BM_CAN_RXFGMASK_FGM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FGM field to a new value.
+#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXFIR - Rx FIFO Information Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+typedef union _hw_can_rxfir
+{
+    uint32_t U;
+    struct _hw_can_rxfir_bitfields
+    {
+        uint32_t IDHIT : 9;            //!< [8:0] Identifier Acceptance Filter Hit
+                                       //! Indicator
+        uint32_t RESERVED0 : 23;       //!< [31:9]
+    } B;
+} hw_can_rxfir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+//@{
+#define HW_CAN_RXFIR_ADDR(x)     (REGS_CAN_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXFIR(x)          (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
+#define HW_CAN_RXFIR_RD(x)       (HW_CAN_RXFIR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+//@{
+#define BP_CAN_RXFIR_IDHIT   (0U)          //!< Bit position for CAN_RXFIR_IDHIT.
+#define BM_CAN_RXFIR_IDHIT   (0x000001FFU) //!< Bit mask for CAN_RXFIR_IDHIT.
+#define BS_CAN_RXFIR_IDHIT   (9U)          //!< Bit field size in bits for CAN_RXFIR_IDHIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXFIR_IDHIT field.
+#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CS - Message Buffer 0 CS Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_cs
+{
+    uint32_t U;
+    struct _hw_can_cs_bitfields
+    {
+        uint32_t TIME_STAMP : 16;      //!< [15:0] Free-Running Counter Time
+                                       //! stamp. This 16-bit field is a copy of the Free-Running Timer, captured for
+                                       //! Tx and Rx frames at the time when the beginning of the Identifier
+                                       //! field appears on the CAN bus.
+        uint32_t DLC : 4;              //!< [19:16] Length of the data to be
+                                       //! stored/transmitted.
+        uint32_t RTR : 1;              //!< [20] Remote Transmission Request. One/zero for
+                                       //! remote/data frame.
+        uint32_t IDE : 1;              //!< [21] ID Extended. One/zero for
+                                       //! extended/standard format frame.
+        uint32_t SRR : 1;              //!< [22] Substitute Remote Request. Contains a
+                                       //! fixed recessive bit.
+        uint32_t RESERVED0 : 1;        //!< [23] Reserved
+        uint32_t CODE : 4;             //!< [27:24] Reserved
+        uint32_t RESERVED1 : 4;        //!< [31:28] Reserved
+    } B;
+} hw_can_cs_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+//@{
+#define HW_CAN_CS_COUNT (16U)
+
+#define HW_CAN_CS_ADDR(x, n)     (REGS_CAN_BASE(x) + 0x80U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CS(x, n)          (*(__IO hw_can_cs_t *) HW_CAN_CS_ADDR(x, n))
+#define HW_CAN_CS_RD(x, n)       (HW_CAN_CS(x, n).U)
+#define HW_CAN_CS_WR(x, n, v)    (HW_CAN_CS(x, n).U = (v))
+#define HW_CAN_CS_SET(x, n, v)   (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) |  (v)))
+#define HW_CAN_CS_CLR(x, n, v)   (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) & ~(v)))
+#define HW_CAN_CS_TOG(x, n, v)   (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+//@{
+#define BP_CAN_CS_TIME_STAMP (0U)          //!< Bit position for CAN_CS_TIME_STAMP.
+#define BM_CAN_CS_TIME_STAMP (0x0000FFFFU) //!< Bit mask for CAN_CS_TIME_STAMP.
+#define BS_CAN_CS_TIME_STAMP (16U)         //!< Bit field size in bits for CAN_CS_TIME_STAMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_TIME_STAMP field.
+#define BR_CAN_CS_TIME_STAMP(x, n) (HW_CAN_CS(x, n).B.TIME_STAMP)
+#endif
+
+//! @brief Format value for bitfield CAN_CS_TIME_STAMP.
+#define BF_CAN_CS_TIME_STAMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_TIME_STAMP), uint32_t) & BM_CAN_CS_TIME_STAMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIME_STAMP field to a new value.
+#define BW_CAN_CS_TIME_STAMP(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_TIME_STAMP) | BF_CAN_CS_TIME_STAMP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+//@{
+#define BP_CAN_CS_DLC        (16U)         //!< Bit position for CAN_CS_DLC.
+#define BM_CAN_CS_DLC        (0x000F0000U) //!< Bit mask for CAN_CS_DLC.
+#define BS_CAN_CS_DLC        (4U)          //!< Bit field size in bits for CAN_CS_DLC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_DLC field.
+#define BR_CAN_CS_DLC(x, n)  (HW_CAN_CS(x, n).B.DLC)
+#endif
+
+//! @brief Format value for bitfield CAN_CS_DLC.
+#define BF_CAN_CS_DLC(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_DLC), uint32_t) & BM_CAN_CS_DLC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLC field to a new value.
+#define BW_CAN_CS_DLC(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_DLC) | BF_CAN_CS_DLC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+//@{
+#define BP_CAN_CS_RTR        (20U)         //!< Bit position for CAN_CS_RTR.
+#define BM_CAN_CS_RTR        (0x00100000U) //!< Bit mask for CAN_CS_RTR.
+#define BS_CAN_CS_RTR        (1U)          //!< Bit field size in bits for CAN_CS_RTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_RTR field.
+#define BR_CAN_CS_RTR(x, n)  (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR))
+#endif
+
+//! @brief Format value for bitfield CAN_CS_RTR.
+#define BF_CAN_CS_RTR(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_RTR), uint32_t) & BM_CAN_CS_RTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RTR field to a new value.
+#define BW_CAN_CS_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+//@{
+#define BP_CAN_CS_IDE        (21U)         //!< Bit position for CAN_CS_IDE.
+#define BM_CAN_CS_IDE        (0x00200000U) //!< Bit mask for CAN_CS_IDE.
+#define BS_CAN_CS_IDE        (1U)          //!< Bit field size in bits for CAN_CS_IDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_IDE field.
+#define BR_CAN_CS_IDE(x, n)  (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE))
+#endif
+
+//! @brief Format value for bitfield CAN_CS_IDE.
+#define BF_CAN_CS_IDE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_IDE), uint32_t) & BM_CAN_CS_IDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDE field to a new value.
+#define BW_CAN_CS_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+//@{
+#define BP_CAN_CS_SRR        (22U)         //!< Bit position for CAN_CS_SRR.
+#define BM_CAN_CS_SRR        (0x00400000U) //!< Bit mask for CAN_CS_SRR.
+#define BS_CAN_CS_SRR        (1U)          //!< Bit field size in bits for CAN_CS_SRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_SRR field.
+#define BR_CAN_CS_SRR(x, n)  (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR))
+#endif
+
+//! @brief Format value for bitfield CAN_CS_SRR.
+#define BF_CAN_CS_SRR(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_SRR), uint32_t) & BM_CAN_CS_SRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRR field to a new value.
+#define BW_CAN_CS_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+//@{
+#define BP_CAN_CS_CODE       (24U)         //!< Bit position for CAN_CS_CODE.
+#define BM_CAN_CS_CODE       (0x0F000000U) //!< Bit mask for CAN_CS_CODE.
+#define BS_CAN_CS_CODE       (4U)          //!< Bit field size in bits for CAN_CS_CODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_CODE field.
+#define BR_CAN_CS_CODE(x, n) (HW_CAN_CS(x, n).B.CODE)
+#endif
+
+//! @brief Format value for bitfield CAN_CS_CODE.
+#define BF_CAN_CS_CODE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_CODE), uint32_t) & BM_CAN_CS_CODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CODE field to a new value.
+#define BW_CAN_CS_CODE(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_CODE) | BF_CAN_CS_CODE(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ID - Message Buffer 0 ID Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_id
+{
+    uint32_t U;
+    struct _hw_can_id_bitfields
+    {
+        uint32_t EXT : 18;             //!< [17:0] Contains extended (LOW word)
+                                       //! identifier of message buffer.
+        uint32_t STD : 11;             //!< [28:18] Contains standard/extended (HIGH
+                                       //! word) identifier of message buffer.
+        uint32_t PRIO : 3;             //!< [31:29] Local priority. This 3-bit fieldis
+                                       //! only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
+                                       //! buffers. These bits are not transmitted. They are appended to the
+                                       //! regular ID to define the transmission priority.
+    } B;
+} hw_can_id_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+//@{
+#define HW_CAN_ID_COUNT (16U)
+
+#define HW_CAN_ID_ADDR(x, n)     (REGS_CAN_BASE(x) + 0x84U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ID(x, n)          (*(__IO hw_can_id_t *) HW_CAN_ID_ADDR(x, n))
+#define HW_CAN_ID_RD(x, n)       (HW_CAN_ID(x, n).U)
+#define HW_CAN_ID_WR(x, n, v)    (HW_CAN_ID(x, n).U = (v))
+#define HW_CAN_ID_SET(x, n, v)   (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) |  (v)))
+#define HW_CAN_ID_CLR(x, n, v)   (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) & ~(v)))
+#define HW_CAN_ID_TOG(x, n, v)   (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+//@{
+#define BP_CAN_ID_EXT        (0U)          //!< Bit position for CAN_ID_EXT.
+#define BM_CAN_ID_EXT        (0x0003FFFFU) //!< Bit mask for CAN_ID_EXT.
+#define BS_CAN_ID_EXT        (18U)         //!< Bit field size in bits for CAN_ID_EXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ID_EXT field.
+#define BR_CAN_ID_EXT(x, n)  (HW_CAN_ID(x, n).B.EXT)
+#endif
+
+//! @brief Format value for bitfield CAN_ID_EXT.
+#define BF_CAN_ID_EXT(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_EXT), uint32_t) & BM_CAN_ID_EXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXT field to a new value.
+#define BW_CAN_ID_EXT(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_EXT) | BF_CAN_ID_EXT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+//@{
+#define BP_CAN_ID_STD        (18U)         //!< Bit position for CAN_ID_STD.
+#define BM_CAN_ID_STD        (0x1FFC0000U) //!< Bit mask for CAN_ID_STD.
+#define BS_CAN_ID_STD        (11U)         //!< Bit field size in bits for CAN_ID_STD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ID_STD field.
+#define BR_CAN_ID_STD(x, n)  (HW_CAN_ID(x, n).B.STD)
+#endif
+
+//! @brief Format value for bitfield CAN_ID_STD.
+#define BF_CAN_ID_STD(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_STD), uint32_t) & BM_CAN_ID_STD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STD field to a new value.
+#define BW_CAN_ID_STD(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_STD) | BF_CAN_ID_STD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+//@{
+#define BP_CAN_ID_PRIO       (29U)         //!< Bit position for CAN_ID_PRIO.
+#define BM_CAN_ID_PRIO       (0xE0000000U) //!< Bit mask for CAN_ID_PRIO.
+#define BS_CAN_ID_PRIO       (3U)          //!< Bit field size in bits for CAN_ID_PRIO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ID_PRIO field.
+#define BR_CAN_ID_PRIO(x, n) (HW_CAN_ID(x, n).B.PRIO)
+#endif
+
+//! @brief Format value for bitfield CAN_ID_PRIO.
+#define BF_CAN_ID_PRIO(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_PRIO), uint32_t) & BM_CAN_ID_PRIO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRIO field to a new value.
+#define BW_CAN_ID_PRIO(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_PRIO) | BF_CAN_ID_PRIO(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_word0
+{
+    uint32_t U;
+    struct _hw_can_word0_bitfields
+    {
+        uint32_t DATA_BYTE_3 : 8;      //!< [7:0] Data byte 3 of Rx/Tx frame.
+        uint32_t DATA_BYTE_2 : 8;      //!< [15:8] Data byte 2 of Rx/Tx frame.
+        uint32_t DATA_BYTE_1 : 8;      //!< [23:16] Data byte 1 of Rx/Tx frame.
+        uint32_t DATA_BYTE_0 : 8;      //!< [31:24] Data byte 0 of Rx/Tx frame.
+    } B;
+} hw_can_word0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+//@{
+#define HW_CAN_WORD0_COUNT (16U)
+
+#define HW_CAN_WORD0_ADDR(x, n)  (REGS_CAN_BASE(x) + 0x88U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_WORD0(x, n)       (*(__IO hw_can_word0_t *) HW_CAN_WORD0_ADDR(x, n))
+#define HW_CAN_WORD0_RD(x, n)    (HW_CAN_WORD0(x, n).U)
+#define HW_CAN_WORD0_WR(x, n, v) (HW_CAN_WORD0(x, n).U = (v))
+#define HW_CAN_WORD0_SET(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) |  (v)))
+#define HW_CAN_WORD0_CLR(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) & ~(v)))
+#define HW_CAN_WORD0_TOG(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_3 (0U)      //!< Bit position for CAN_WORD0_DATA_BYTE_3.
+#define BM_CAN_WORD0_DATA_BYTE_3 (0x000000FFU) //!< Bit mask for CAN_WORD0_DATA_BYTE_3.
+#define BS_CAN_WORD0_DATA_BYTE_3 (8U)      //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field.
+#define BR_CAN_WORD0_DATA_BYTE_3(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_3)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_3.
+#define BF_CAN_WORD0_DATA_BYTE_3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_3), uint32_t) & BM_CAN_WORD0_DATA_BYTE_3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_3 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_3) | BF_CAN_WORD0_DATA_BYTE_3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_2 (8U)      //!< Bit position for CAN_WORD0_DATA_BYTE_2.
+#define BM_CAN_WORD0_DATA_BYTE_2 (0x0000FF00U) //!< Bit mask for CAN_WORD0_DATA_BYTE_2.
+#define BS_CAN_WORD0_DATA_BYTE_2 (8U)      //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field.
+#define BR_CAN_WORD0_DATA_BYTE_2(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_2)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_2.
+#define BF_CAN_WORD0_DATA_BYTE_2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_2), uint32_t) & BM_CAN_WORD0_DATA_BYTE_2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_2 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_2) | BF_CAN_WORD0_DATA_BYTE_2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_1 (16U)     //!< Bit position for CAN_WORD0_DATA_BYTE_1.
+#define BM_CAN_WORD0_DATA_BYTE_1 (0x00FF0000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_1.
+#define BS_CAN_WORD0_DATA_BYTE_1 (8U)      //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field.
+#define BR_CAN_WORD0_DATA_BYTE_1(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_1)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_1.
+#define BF_CAN_WORD0_DATA_BYTE_1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_1), uint32_t) & BM_CAN_WORD0_DATA_BYTE_1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_1 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_1) | BF_CAN_WORD0_DATA_BYTE_1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_0 (24U)     //!< Bit position for CAN_WORD0_DATA_BYTE_0.
+#define BM_CAN_WORD0_DATA_BYTE_0 (0xFF000000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_0.
+#define BS_CAN_WORD0_DATA_BYTE_0 (8U)      //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field.
+#define BR_CAN_WORD0_DATA_BYTE_0(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_0)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_0.
+#define BF_CAN_WORD0_DATA_BYTE_0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_0), uint32_t) & BM_CAN_WORD0_DATA_BYTE_0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_0 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_0) | BF_CAN_WORD0_DATA_BYTE_0(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_word1
+{
+    uint32_t U;
+    struct _hw_can_word1_bitfields
+    {
+        uint32_t DATA_BYTE_7 : 8;      //!< [7:0] Data byte 7 of Rx/Tx frame.
+        uint32_t DATA_BYTE_6 : 8;      //!< [15:8] Data byte 6 of Rx/Tx frame.
+        uint32_t DATA_BYTE_5 : 8;      //!< [23:16] Data byte 5 of Rx/Tx frame.
+        uint32_t DATA_BYTE_4 : 8;      //!< [31:24] Data byte 4 of Rx/Tx frame.
+    } B;
+} hw_can_word1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+//@{
+#define HW_CAN_WORD1_COUNT (16U)
+
+#define HW_CAN_WORD1_ADDR(x, n)  (REGS_CAN_BASE(x) + 0x8CU + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_WORD1(x, n)       (*(__IO hw_can_word1_t *) HW_CAN_WORD1_ADDR(x, n))
+#define HW_CAN_WORD1_RD(x, n)    (HW_CAN_WORD1(x, n).U)
+#define HW_CAN_WORD1_WR(x, n, v) (HW_CAN_WORD1(x, n).U = (v))
+#define HW_CAN_WORD1_SET(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) |  (v)))
+#define HW_CAN_WORD1_CLR(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) & ~(v)))
+#define HW_CAN_WORD1_TOG(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_7 (0U)      //!< Bit position for CAN_WORD1_DATA_BYTE_7.
+#define BM_CAN_WORD1_DATA_BYTE_7 (0x000000FFU) //!< Bit mask for CAN_WORD1_DATA_BYTE_7.
+#define BS_CAN_WORD1_DATA_BYTE_7 (8U)      //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field.
+#define BR_CAN_WORD1_DATA_BYTE_7(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_7)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_7.
+#define BF_CAN_WORD1_DATA_BYTE_7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_7), uint32_t) & BM_CAN_WORD1_DATA_BYTE_7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_7 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_7) | BF_CAN_WORD1_DATA_BYTE_7(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_6 (8U)      //!< Bit position for CAN_WORD1_DATA_BYTE_6.
+#define BM_CAN_WORD1_DATA_BYTE_6 (0x0000FF00U) //!< Bit mask for CAN_WORD1_DATA_BYTE_6.
+#define BS_CAN_WORD1_DATA_BYTE_6 (8U)      //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field.
+#define BR_CAN_WORD1_DATA_BYTE_6(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_6)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_6.
+#define BF_CAN_WORD1_DATA_BYTE_6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_6), uint32_t) & BM_CAN_WORD1_DATA_BYTE_6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_6 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_6) | BF_CAN_WORD1_DATA_BYTE_6(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_5 (16U)     //!< Bit position for CAN_WORD1_DATA_BYTE_5.
+#define BM_CAN_WORD1_DATA_BYTE_5 (0x00FF0000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_5.
+#define BS_CAN_WORD1_DATA_BYTE_5 (8U)      //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field.
+#define BR_CAN_WORD1_DATA_BYTE_5(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_5)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_5.
+#define BF_CAN_WORD1_DATA_BYTE_5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_5), uint32_t) & BM_CAN_WORD1_DATA_BYTE_5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_5 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_5) | BF_CAN_WORD1_DATA_BYTE_5(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_4 (24U)     //!< Bit position for CAN_WORD1_DATA_BYTE_4.
+#define BM_CAN_WORD1_DATA_BYTE_4 (0xFF000000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_4.
+#define BS_CAN_WORD1_DATA_BYTE_4 (8U)      //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field.
+#define BR_CAN_WORD1_DATA_BYTE_4(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_4)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_4.
+#define BF_CAN_WORD1_DATA_BYTE_4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_4), uint32_t) & BM_CAN_WORD1_DATA_BYTE_4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_4 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_4) | BF_CAN_WORD1_DATA_BYTE_4(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXIMRn - Rx Individual Mask Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+typedef union _hw_can_rximrn
+{
+    uint32_t U;
+    struct _hw_can_rximrn_bitfields
+    {
+        uint32_t MI : 32;              //!< [31:0] Individual Mask Bits
+    } B;
+} hw_can_rximrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXIMRn register
+ */
+//@{
+#define HW_CAN_RXIMRn_COUNT (16U)
+
+#define HW_CAN_RXIMRn_ADDR(x, n) (REGS_CAN_BASE(x) + 0x880U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXIMRn(x, n)      (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
+#define HW_CAN_RXIMRn_RD(x, n)   (HW_CAN_RXIMRn(x, n).U)
+#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
+#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) |  (v)))
+#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
+#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXIMRn bitfields
+ */
+
+/*!
+ * @name Register CAN_RXIMRn, field MI[31:0] (RW)
+ *
+ * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
+ * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
+ * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
+ * see the RXFGMASK register description.
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RXIMRn_MI     (0U)          //!< Bit position for CAN_RXIMRn_MI.
+#define BM_CAN_RXIMRn_MI     (0xFFFFFFFFU) //!< Bit mask for CAN_RXIMRn_MI.
+#define BS_CAN_RXIMRn_MI     (32U)         //!< Bit field size in bits for CAN_RXIMRn_MI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXIMRn_MI field.
+#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RXIMRn_MI.
+#define BF_CAN_RXIMRn_MI(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXIMRn_MI), uint32_t) & BM_CAN_RXIMRn_MI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MI field to a new value.
+#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_can_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CAN module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_can
+{
+    __IO hw_can_mcr_t MCR;                 //!< [0x0] Module Configuration Register
+    __IO hw_can_ctrl1_t CTRL1;             //!< [0x4] Control 1 register
+    __IO hw_can_timer_t TIMER;             //!< [0x8] Free Running Timer
+    uint8_t _reserved0[4];
+    __IO hw_can_rxmgmask_t RXMGMASK;       //!< [0x10] Rx Mailboxes Global Mask Register
+    __IO hw_can_rx14mask_t RX14MASK;       //!< [0x14] Rx 14 Mask register
+    __IO hw_can_rx15mask_t RX15MASK;       //!< [0x18] Rx 15 Mask register
+    __IO hw_can_ecr_t ECR;                 //!< [0x1C] Error Counter
+    __IO hw_can_esr1_t ESR1;               //!< [0x20] Error and Status 1 register
+    uint8_t _reserved1[4];
+    __IO hw_can_imask1_t IMASK1;           //!< [0x28] Interrupt Masks 1 register
+    uint8_t _reserved2[4];
+    __IO hw_can_iflag1_t IFLAG1;           //!< [0x30] Interrupt Flags 1 register
+    __IO hw_can_ctrl2_t CTRL2;             //!< [0x34] Control 2 register
+    __I hw_can_esr2_t ESR2;                //!< [0x38] Error and Status 2 register
+    uint8_t _reserved3[8];
+    __I hw_can_crcr_t CRCR;                //!< [0x44] CRC Register
+    __IO hw_can_rxfgmask_t RXFGMASK;       //!< [0x48] Rx FIFO Global Mask register
+    __I hw_can_rxfir_t RXFIR;              //!< [0x4C] Rx FIFO Information Register
+    uint8_t _reserved4[48];
+    struct {
+        __IO hw_can_cs_t CS;               //!< [0x80] Message Buffer 0 CS Register
+        __IO hw_can_id_t ID;               //!< [0x84] Message Buffer 0 ID Register
+        __IO hw_can_word0_t WORD0;         //!< [0x88] Message Buffer 0 WORD0 Register
+        __IO hw_can_word1_t WORD1;         //!< [0x8C] Message Buffer 0 WORD1 Register
+    } MB[16];
+    uint8_t _reserved5[1792];
+    __IO hw_can_rximrn_t RXIMRn[16];       //!< [0x880] Rx Individual Mask Registers
+} hw_can_t;
+#pragma pack()
+
+//! @brief Macro to access all CAN registers.
+//! @param x CAN instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_CAN(0)</code>.
+#define HW_CAN(x)      (*(hw_can_t *) REGS_CAN_BASE(x))
+#endif
+
+#endif // __HW_CAN_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h
new file mode 100644
index 0000000000..6a24633264
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h
@@ -0,0 +1,1463 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CAU_REGISTERS_H__
+#define __HW_CAU_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - HW_CAU_DIRECT - Direct access register 0
+ * - HW_CAU_LDR_CASR - Status register  - Load Register command
+ * - HW_CAU_LDR_CAA - Accumulator register - Load Register command
+ * - HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - HW_CAU_STR_CASR - Status register  - Store Register command
+ * - HW_CAU_STR_CAA - Accumulator register - Store Register command
+ * - HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - HW_CAU_ADR_CASR - Status register  - Add Register command
+ * - HW_CAU_ADR_CAA - Accumulator register - Add to register command
+ * - HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - HW_CAU_RADR_CASR - Status register  - Reverse and Add to Register command
+ * - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - HW_CAU_XOR_CASR - Status register  - Exclusive Or command
+ * - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - HW_CAU_ROTL_CASR - Status register  - Rotate Left command
+ * - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - HW_CAU_AESC_CASR - Status register  - AES Column Operation command
+ * - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - HW_CAU_AESIC_CASR - Status register  - AES Inverse Column Operation command
+ * - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ *
+ * - hw_cau_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CAU_BASE
+#define HW_CAU_INSTANCE_COUNT (1U) //!< Number of instances of the CAU module.
+#define REGS_CAU_BASE (0xE0081000U) //!< Base address for CAU.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_DIRECT - Direct access register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_direct
+{
+    uint32_t U;
+    struct _hw_cau_direct_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_direct_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+//@{
+#define HW_CAU_DIRECT_COUNT (16U)
+
+#define HW_CAU_DIRECT_ADDR(n)    (REGS_CAU_BASE + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_DIRECT(n)         (*(__O hw_cau_direct_t *) HW_CAU_DIRECT_ADDR(n))
+#define HW_CAU_DIRECT_WR(n, v)   (HW_CAU_DIRECT(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_DIRECT bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_LDR_CASR - Status register  - Load Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_LDR_CASR - Status register  - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_ldr_casr
+{
+    uint32_t U;
+    struct _hw_cau_ldr_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_ldr_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+//@{
+#define HW_CAU_LDR_CASR_ADDR     (REGS_CAU_BASE + 0x840U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_LDR_CASR          (*(__O hw_cau_ldr_casr_t *) HW_CAU_LDR_CASR_ADDR)
+#define HW_CAU_LDR_CASR_WR(v)    (HW_CAU_LDR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_LDR_CASR_IC   (0U)          //!< Bit position for CAU_LDR_CASR_IC.
+#define BM_CAU_LDR_CASR_IC   (0x00000001U) //!< Bit mask for CAU_LDR_CASR_IC.
+#define BS_CAU_LDR_CASR_IC   (1U)          //!< Bit field size in bits for CAU_LDR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_LDR_CASR_IC.
+#define BF_CAU_LDR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_IC), uint32_t) & BM_CAU_LDR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_LDR_CASR_DPE  (1U)          //!< Bit position for CAU_LDR_CASR_DPE.
+#define BM_CAU_LDR_CASR_DPE  (0x00000002U) //!< Bit mask for CAU_LDR_CASR_DPE.
+#define BS_CAU_LDR_CASR_DPE  (1U)          //!< Bit field size in bits for CAU_LDR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_LDR_CASR_DPE.
+#define BF_CAU_LDR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_DPE), uint32_t) & BM_CAU_LDR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_LDR_CASR_VER  (28U)         //!< Bit position for CAU_LDR_CASR_VER.
+#define BM_CAU_LDR_CASR_VER  (0xF0000000U) //!< Bit mask for CAU_LDR_CASR_VER.
+#define BS_CAU_LDR_CASR_VER  (4U)          //!< Bit field size in bits for CAU_LDR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_LDR_CASR_VER.
+#define BF_CAU_LDR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_VER), uint32_t) & BM_CAU_LDR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_LDR_CAA - Accumulator register - Load Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_ldr_caa
+{
+    uint32_t U;
+    struct _hw_cau_ldr_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_ldr_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+//@{
+#define HW_CAU_LDR_CAA_ADDR      (REGS_CAU_BASE + 0x844U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_LDR_CAA           (*(__O hw_cau_ldr_caa_t *) HW_CAU_LDR_CAA_ADDR)
+#define HW_CAU_LDR_CAA_WR(v)     (HW_CAU_LDR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_LDR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_ldr_ca
+{
+    uint32_t U;
+    struct _hw_cau_ldr_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_ldr_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+//@{
+#define HW_CAU_LDR_CA_COUNT (9U)
+
+#define HW_CAU_LDR_CA_ADDR(n)    (REGS_CAU_BASE + 0x848U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_LDR_CA(n)         (*(__O hw_cau_ldr_ca_t *) HW_CAU_LDR_CA_ADDR(n))
+#define HW_CAU_LDR_CA_WR(n, v)   (HW_CAU_LDR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_LDR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_STR_CASR - Status register  - Store Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_STR_CASR - Status register  - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_str_casr
+{
+    uint32_t U;
+    struct _hw_cau_str_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_str_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+//@{
+#define HW_CAU_STR_CASR_ADDR     (REGS_CAU_BASE + 0x880U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_STR_CASR          (*(__I hw_cau_str_casr_t *) HW_CAU_STR_CASR_ADDR)
+#define HW_CAU_STR_CASR_RD()     (HW_CAU_STR_CASR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_STR_CASR_IC   (0U)          //!< Bit position for CAU_STR_CASR_IC.
+#define BM_CAU_STR_CASR_IC   (0x00000001U) //!< Bit mask for CAU_STR_CASR_IC.
+#define BS_CAU_STR_CASR_IC   (1U)          //!< Bit field size in bits for CAU_STR_CASR_IC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAU_STR_CASR_IC field.
+#define BR_CAU_STR_CASR_IC   (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_IC))
+#endif
+//@}
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_STR_CASR_DPE  (1U)          //!< Bit position for CAU_STR_CASR_DPE.
+#define BM_CAU_STR_CASR_DPE  (0x00000002U) //!< Bit mask for CAU_STR_CASR_DPE.
+#define BS_CAU_STR_CASR_DPE  (1U)          //!< Bit field size in bits for CAU_STR_CASR_DPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAU_STR_CASR_DPE field.
+#define BR_CAU_STR_CASR_DPE  (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_DPE))
+#endif
+//@}
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_STR_CASR_VER  (28U)         //!< Bit position for CAU_STR_CASR_VER.
+#define BM_CAU_STR_CASR_VER  (0xF0000000U) //!< Bit mask for CAU_STR_CASR_VER.
+#define BS_CAU_STR_CASR_VER  (4U)          //!< Bit field size in bits for CAU_STR_CASR_VER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAU_STR_CASR_VER field.
+#define BR_CAU_STR_CASR_VER  (HW_CAU_STR_CASR.B.VER)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_STR_CAA - Accumulator register - Store Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_str_caa
+{
+    uint32_t U;
+    struct _hw_cau_str_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_str_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+//@{
+#define HW_CAU_STR_CAA_ADDR      (REGS_CAU_BASE + 0x884U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_STR_CAA           (*(__I hw_cau_str_caa_t *) HW_CAU_STR_CAA_ADDR)
+#define HW_CAU_STR_CAA_RD()      (HW_CAU_STR_CAA.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_STR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_str_ca
+{
+    uint32_t U;
+    struct _hw_cau_str_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_str_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+//@{
+#define HW_CAU_STR_CA_COUNT (9U)
+
+#define HW_CAU_STR_CA_ADDR(n)    (REGS_CAU_BASE + 0x888U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_STR_CA(n)         (*(__I hw_cau_str_ca_t *) HW_CAU_STR_CA_ADDR(n))
+#define HW_CAU_STR_CA_RD(n)      (HW_CAU_STR_CA(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_STR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ADR_CASR - Status register  - Add Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ADR_CASR - Status register  - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_adr_casr
+{
+    uint32_t U;
+    struct _hw_cau_adr_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_adr_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+//@{
+#define HW_CAU_ADR_CASR_ADDR     (REGS_CAU_BASE + 0x8C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ADR_CASR          (*(__O hw_cau_adr_casr_t *) HW_CAU_ADR_CASR_ADDR)
+#define HW_CAU_ADR_CASR_WR(v)    (HW_CAU_ADR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_ADR_CASR_IC   (0U)          //!< Bit position for CAU_ADR_CASR_IC.
+#define BM_CAU_ADR_CASR_IC   (0x00000001U) //!< Bit mask for CAU_ADR_CASR_IC.
+#define BS_CAU_ADR_CASR_IC   (1U)          //!< Bit field size in bits for CAU_ADR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_ADR_CASR_IC.
+#define BF_CAU_ADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_IC), uint32_t) & BM_CAU_ADR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_ADR_CASR_DPE  (1U)          //!< Bit position for CAU_ADR_CASR_DPE.
+#define BM_CAU_ADR_CASR_DPE  (0x00000002U) //!< Bit mask for CAU_ADR_CASR_DPE.
+#define BS_CAU_ADR_CASR_DPE  (1U)          //!< Bit field size in bits for CAU_ADR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_ADR_CASR_DPE.
+#define BF_CAU_ADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_DPE), uint32_t) & BM_CAU_ADR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_ADR_CASR_VER  (28U)         //!< Bit position for CAU_ADR_CASR_VER.
+#define BM_CAU_ADR_CASR_VER  (0xF0000000U) //!< Bit mask for CAU_ADR_CASR_VER.
+#define BS_CAU_ADR_CASR_VER  (4U)          //!< Bit field size in bits for CAU_ADR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_ADR_CASR_VER.
+#define BF_CAU_ADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_VER), uint32_t) & BM_CAU_ADR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ADR_CAA - Accumulator register - Add to register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_adr_caa
+{
+    uint32_t U;
+    struct _hw_cau_adr_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_adr_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+//@{
+#define HW_CAU_ADR_CAA_ADDR      (REGS_CAU_BASE + 0x8C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ADR_CAA           (*(__O hw_cau_adr_caa_t *) HW_CAU_ADR_CAA_ADDR)
+#define HW_CAU_ADR_CAA_WR(v)     (HW_CAU_ADR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ADR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_adr_ca
+{
+    uint32_t U;
+    struct _hw_cau_adr_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_adr_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+//@{
+#define HW_CAU_ADR_CA_COUNT (9U)
+
+#define HW_CAU_ADR_CA_ADDR(n)    (REGS_CAU_BASE + 0x8C8U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ADR_CA(n)         (*(__O hw_cau_adr_ca_t *) HW_CAU_ADR_CA_ADDR(n))
+#define HW_CAU_ADR_CA_WR(n, v)   (HW_CAU_ADR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ADR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_RADR_CASR - Status register  - Reverse and Add to Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_RADR_CASR - Status register  - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_radr_casr
+{
+    uint32_t U;
+    struct _hw_cau_radr_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_radr_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+//@{
+#define HW_CAU_RADR_CASR_ADDR    (REGS_CAU_BASE + 0x900U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_RADR_CASR         (*(__O hw_cau_radr_casr_t *) HW_CAU_RADR_CASR_ADDR)
+#define HW_CAU_RADR_CASR_WR(v)   (HW_CAU_RADR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_RADR_CASR_IC  (0U)          //!< Bit position for CAU_RADR_CASR_IC.
+#define BM_CAU_RADR_CASR_IC  (0x00000001U) //!< Bit mask for CAU_RADR_CASR_IC.
+#define BS_CAU_RADR_CASR_IC  (1U)          //!< Bit field size in bits for CAU_RADR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_RADR_CASR_IC.
+#define BF_CAU_RADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_IC), uint32_t) & BM_CAU_RADR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_RADR_CASR_DPE (1U)          //!< Bit position for CAU_RADR_CASR_DPE.
+#define BM_CAU_RADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_RADR_CASR_DPE.
+#define BS_CAU_RADR_CASR_DPE (1U)          //!< Bit field size in bits for CAU_RADR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_RADR_CASR_DPE.
+#define BF_CAU_RADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_DPE), uint32_t) & BM_CAU_RADR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_RADR_CASR_VER (28U)         //!< Bit position for CAU_RADR_CASR_VER.
+#define BM_CAU_RADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_RADR_CASR_VER.
+#define BS_CAU_RADR_CASR_VER (4U)          //!< Bit field size in bits for CAU_RADR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_RADR_CASR_VER.
+#define BF_CAU_RADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_VER), uint32_t) & BM_CAU_RADR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_radr_caa
+{
+    uint32_t U;
+    struct _hw_cau_radr_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_radr_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+//@{
+#define HW_CAU_RADR_CAA_ADDR     (REGS_CAU_BASE + 0x904U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_RADR_CAA          (*(__O hw_cau_radr_caa_t *) HW_CAU_RADR_CAA_ADDR)
+#define HW_CAU_RADR_CAA_WR(v)    (HW_CAU_RADR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_RADR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_radr_ca
+{
+    uint32_t U;
+    struct _hw_cau_radr_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_radr_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+//@{
+#define HW_CAU_RADR_CA_COUNT (9U)
+
+#define HW_CAU_RADR_CA_ADDR(n)   (REGS_CAU_BASE + 0x908U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_RADR_CA(n)        (*(__O hw_cau_radr_ca_t *) HW_CAU_RADR_CA_ADDR(n))
+#define HW_CAU_RADR_CA_WR(n, v)  (HW_CAU_RADR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_RADR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_XOR_CASR - Status register  - Exclusive Or command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_XOR_CASR - Status register  - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_xor_casr
+{
+    uint32_t U;
+    struct _hw_cau_xor_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_xor_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+//@{
+#define HW_CAU_XOR_CASR_ADDR     (REGS_CAU_BASE + 0x980U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_XOR_CASR          (*(__O hw_cau_xor_casr_t *) HW_CAU_XOR_CASR_ADDR)
+#define HW_CAU_XOR_CASR_WR(v)    (HW_CAU_XOR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_XOR_CASR_IC   (0U)          //!< Bit position for CAU_XOR_CASR_IC.
+#define BM_CAU_XOR_CASR_IC   (0x00000001U) //!< Bit mask for CAU_XOR_CASR_IC.
+#define BS_CAU_XOR_CASR_IC   (1U)          //!< Bit field size in bits for CAU_XOR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_XOR_CASR_IC.
+#define BF_CAU_XOR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_IC), uint32_t) & BM_CAU_XOR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_XOR_CASR_DPE  (1U)          //!< Bit position for CAU_XOR_CASR_DPE.
+#define BM_CAU_XOR_CASR_DPE  (0x00000002U) //!< Bit mask for CAU_XOR_CASR_DPE.
+#define BS_CAU_XOR_CASR_DPE  (1U)          //!< Bit field size in bits for CAU_XOR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_XOR_CASR_DPE.
+#define BF_CAU_XOR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_DPE), uint32_t) & BM_CAU_XOR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_XOR_CASR_VER  (28U)         //!< Bit position for CAU_XOR_CASR_VER.
+#define BM_CAU_XOR_CASR_VER  (0xF0000000U) //!< Bit mask for CAU_XOR_CASR_VER.
+#define BS_CAU_XOR_CASR_VER  (4U)          //!< Bit field size in bits for CAU_XOR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_XOR_CASR_VER.
+#define BF_CAU_XOR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_VER), uint32_t) & BM_CAU_XOR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_xor_caa
+{
+    uint32_t U;
+    struct _hw_cau_xor_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_xor_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+//@{
+#define HW_CAU_XOR_CAA_ADDR      (REGS_CAU_BASE + 0x984U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_XOR_CAA           (*(__O hw_cau_xor_caa_t *) HW_CAU_XOR_CAA_ADDR)
+#define HW_CAU_XOR_CAA_WR(v)     (HW_CAU_XOR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_XOR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_xor_ca
+{
+    uint32_t U;
+    struct _hw_cau_xor_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_xor_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+//@{
+#define HW_CAU_XOR_CA_COUNT (9U)
+
+#define HW_CAU_XOR_CA_ADDR(n)    (REGS_CAU_BASE + 0x988U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_XOR_CA(n)         (*(__O hw_cau_xor_ca_t *) HW_CAU_XOR_CA_ADDR(n))
+#define HW_CAU_XOR_CA_WR(n, v)   (HW_CAU_XOR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_XOR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ROTL_CASR - Status register  - Rotate Left command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ROTL_CASR - Status register  - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_rotl_casr
+{
+    uint32_t U;
+    struct _hw_cau_rotl_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_rotl_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+//@{
+#define HW_CAU_ROTL_CASR_ADDR    (REGS_CAU_BASE + 0x9C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ROTL_CASR         (*(__O hw_cau_rotl_casr_t *) HW_CAU_ROTL_CASR_ADDR)
+#define HW_CAU_ROTL_CASR_WR(v)   (HW_CAU_ROTL_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_ROTL_CASR_IC  (0U)          //!< Bit position for CAU_ROTL_CASR_IC.
+#define BM_CAU_ROTL_CASR_IC  (0x00000001U) //!< Bit mask for CAU_ROTL_CASR_IC.
+#define BS_CAU_ROTL_CASR_IC  (1U)          //!< Bit field size in bits for CAU_ROTL_CASR_IC.
+
+//! @brief Format value for bitfield CAU_ROTL_CASR_IC.
+#define BF_CAU_ROTL_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_IC), uint32_t) & BM_CAU_ROTL_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_ROTL_CASR_DPE (1U)          //!< Bit position for CAU_ROTL_CASR_DPE.
+#define BM_CAU_ROTL_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ROTL_CASR_DPE.
+#define BS_CAU_ROTL_CASR_DPE (1U)          //!< Bit field size in bits for CAU_ROTL_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_ROTL_CASR_DPE.
+#define BF_CAU_ROTL_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_DPE), uint32_t) & BM_CAU_ROTL_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_ROTL_CASR_VER (28U)         //!< Bit position for CAU_ROTL_CASR_VER.
+#define BM_CAU_ROTL_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ROTL_CASR_VER.
+#define BS_CAU_ROTL_CASR_VER (4U)          //!< Bit field size in bits for CAU_ROTL_CASR_VER.
+
+//! @brief Format value for bitfield CAU_ROTL_CASR_VER.
+#define BF_CAU_ROTL_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_VER), uint32_t) & BM_CAU_ROTL_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_rotl_caa
+{
+    uint32_t U;
+    struct _hw_cau_rotl_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_rotl_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+//@{
+#define HW_CAU_ROTL_CAA_ADDR     (REGS_CAU_BASE + 0x9C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ROTL_CAA          (*(__O hw_cau_rotl_caa_t *) HW_CAU_ROTL_CAA_ADDR)
+#define HW_CAU_ROTL_CAA_WR(v)    (HW_CAU_ROTL_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ROTL_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_rotl_ca
+{
+    uint32_t U;
+    struct _hw_cau_rotl_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_rotl_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+//@{
+#define HW_CAU_ROTL_CA_COUNT (9U)
+
+#define HW_CAU_ROTL_CA_ADDR(n)   (REGS_CAU_BASE + 0x9C8U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ROTL_CA(n)        (*(__O hw_cau_rotl_ca_t *) HW_CAU_ROTL_CA_ADDR(n))
+#define HW_CAU_ROTL_CA_WR(n, v)  (HW_CAU_ROTL_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ROTL_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESC_CASR - Status register  - AES Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESC_CASR - Status register  - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_aesc_casr
+{
+    uint32_t U;
+    struct _hw_cau_aesc_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_aesc_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+//@{
+#define HW_CAU_AESC_CASR_ADDR    (REGS_CAU_BASE + 0xB00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESC_CASR         (*(__O hw_cau_aesc_casr_t *) HW_CAU_AESC_CASR_ADDR)
+#define HW_CAU_AESC_CASR_WR(v)   (HW_CAU_AESC_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_AESC_CASR_IC  (0U)          //!< Bit position for CAU_AESC_CASR_IC.
+#define BM_CAU_AESC_CASR_IC  (0x00000001U) //!< Bit mask for CAU_AESC_CASR_IC.
+#define BS_CAU_AESC_CASR_IC  (1U)          //!< Bit field size in bits for CAU_AESC_CASR_IC.
+
+//! @brief Format value for bitfield CAU_AESC_CASR_IC.
+#define BF_CAU_AESC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_IC), uint32_t) & BM_CAU_AESC_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_AESC_CASR_DPE (1U)          //!< Bit position for CAU_AESC_CASR_DPE.
+#define BM_CAU_AESC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESC_CASR_DPE.
+#define BS_CAU_AESC_CASR_DPE (1U)          //!< Bit field size in bits for CAU_AESC_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_AESC_CASR_DPE.
+#define BF_CAU_AESC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_DPE), uint32_t) & BM_CAU_AESC_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_AESC_CASR_VER (28U)         //!< Bit position for CAU_AESC_CASR_VER.
+#define BM_CAU_AESC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESC_CASR_VER.
+#define BS_CAU_AESC_CASR_VER (4U)          //!< Bit field size in bits for CAU_AESC_CASR_VER.
+
+//! @brief Format value for bitfield CAU_AESC_CASR_VER.
+#define BF_CAU_AESC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_VER), uint32_t) & BM_CAU_AESC_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesc_caa
+{
+    uint32_t U;
+    struct _hw_cau_aesc_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_aesc_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+//@{
+#define HW_CAU_AESC_CAA_ADDR     (REGS_CAU_BASE + 0xB04U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESC_CAA          (*(__O hw_cau_aesc_caa_t *) HW_CAU_AESC_CAA_ADDR)
+#define HW_CAU_AESC_CAA_WR(v)    (HW_CAU_AESC_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESC_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesc_ca
+{
+    uint32_t U;
+    struct _hw_cau_aesc_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_aesc_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+//@{
+#define HW_CAU_AESC_CA_COUNT (9U)
+
+#define HW_CAU_AESC_CA_ADDR(n)   (REGS_CAU_BASE + 0xB08U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESC_CA(n)        (*(__O hw_cau_aesc_ca_t *) HW_CAU_AESC_CA_ADDR(n))
+#define HW_CAU_AESC_CA_WR(n, v)  (HW_CAU_AESC_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESC_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESIC_CASR - Status register  - AES Inverse Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESIC_CASR - Status register  - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_aesic_casr
+{
+    uint32_t U;
+    struct _hw_cau_aesic_casr_bitfields
+    {
+        uint32_t IC : 1;               //!< [0]
+        uint32_t DPE : 1;              //!< [1]
+        uint32_t RESERVED0 : 26;       //!< [27:2]
+        uint32_t VER : 4;              //!< [31:28] CAU version
+    } B;
+} hw_cau_aesic_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+//@{
+#define HW_CAU_AESIC_CASR_ADDR   (REGS_CAU_BASE + 0xB40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESIC_CASR        (*(__O hw_cau_aesic_casr_t *) HW_CAU_AESIC_CASR_ADDR)
+#define HW_CAU_AESIC_CASR_WR(v)  (HW_CAU_AESIC_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_AESIC_CASR_IC (0U)          //!< Bit position for CAU_AESIC_CASR_IC.
+#define BM_CAU_AESIC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESIC_CASR_IC.
+#define BS_CAU_AESIC_CASR_IC (1U)          //!< Bit field size in bits for CAU_AESIC_CASR_IC.
+
+//! @brief Format value for bitfield CAU_AESIC_CASR_IC.
+#define BF_CAU_AESIC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_IC), uint32_t) & BM_CAU_AESIC_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_AESIC_CASR_DPE (1U)         //!< Bit position for CAU_AESIC_CASR_DPE.
+#define BM_CAU_AESIC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESIC_CASR_DPE.
+#define BS_CAU_AESIC_CASR_DPE (1U)         //!< Bit field size in bits for CAU_AESIC_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_AESIC_CASR_DPE.
+#define BF_CAU_AESIC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_DPE), uint32_t) & BM_CAU_AESIC_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+//@{
+#define BP_CAU_AESIC_CASR_VER (28U)        //!< Bit position for CAU_AESIC_CASR_VER.
+#define BM_CAU_AESIC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESIC_CASR_VER.
+#define BS_CAU_AESIC_CASR_VER (4U)         //!< Bit field size in bits for CAU_AESIC_CASR_VER.
+
+//! @brief Format value for bitfield CAU_AESIC_CASR_VER.
+#define BF_CAU_AESIC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_VER), uint32_t) & BM_CAU_AESIC_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesic_caa
+{
+    uint32_t U;
+    struct _hw_cau_aesic_caa_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_aesic_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+//@{
+#define HW_CAU_AESIC_CAA_ADDR    (REGS_CAU_BASE + 0xB44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESIC_CAA         (*(__O hw_cau_aesic_caa_t *) HW_CAU_AESIC_CAA_ADDR)
+#define HW_CAU_AESIC_CAA_WR(v)   (HW_CAU_AESIC_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESIC_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesic_ca
+{
+    uint32_t U;
+    struct _hw_cau_aesic_ca_bitfields
+    {
+        uint32_t RESERVED0 : 32;       //!< [31:0]
+    } B;
+} hw_cau_aesic_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+//@{
+#define HW_CAU_AESIC_CA_COUNT (9U)
+
+#define HW_CAU_AESIC_CA_ADDR(n)  (REGS_CAU_BASE + 0xB48U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESIC_CA(n)       (*(__O hw_cau_aesic_ca_t *) HW_CAU_AESIC_CA_ADDR(n))
+#define HW_CAU_AESIC_CA_WR(n, v) (HW_CAU_AESIC_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESIC_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// hw_cau_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CAU module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_cau
+{
+    __O hw_cau_direct_t DIRECT[16];        //!< [0x0] Direct access register 0
+    uint8_t _reserved0[2048];
+    __O hw_cau_ldr_casr_t LDR_CASR;        //!< [0x840] Status register  - Load Register command
+    __O hw_cau_ldr_caa_t LDR_CAA;          //!< [0x844] Accumulator register - Load Register command
+    __O hw_cau_ldr_ca_t LDR_CA[9];         //!< [0x848] General Purpose Register 0 - Load Register command
+    uint8_t _reserved1[20];
+    __I hw_cau_str_casr_t STR_CASR;        //!< [0x880] Status register  - Store Register command
+    __I hw_cau_str_caa_t STR_CAA;          //!< [0x884] Accumulator register - Store Register command
+    __I hw_cau_str_ca_t STR_CA[9];         //!< [0x888] General Purpose Register 0 - Store Register command
+    uint8_t _reserved2[20];
+    __O hw_cau_adr_casr_t ADR_CASR;        //!< [0x8C0] Status register  - Add Register command
+    __O hw_cau_adr_caa_t ADR_CAA;          //!< [0x8C4] Accumulator register - Add to register command
+    __O hw_cau_adr_ca_t ADR_CA[9];         //!< [0x8C8] General Purpose Register 0 - Add to register command
+    uint8_t _reserved3[20];
+    __O hw_cau_radr_casr_t RADR_CASR;      //!< [0x900] Status register  - Reverse and Add to Register command
+    __O hw_cau_radr_caa_t RADR_CAA;        //!< [0x904] Accumulator register - Reverse and Add to Register command
+    __O hw_cau_radr_ca_t RADR_CA[9];       //!< [0x908] General Purpose Register 0 - Reverse and Add to Register command
+    uint8_t _reserved4[84];
+    __O hw_cau_xor_casr_t XOR_CASR;        //!< [0x980] Status register  - Exclusive Or command
+    __O hw_cau_xor_caa_t XOR_CAA;          //!< [0x984] Accumulator register - Exclusive Or command
+    __O hw_cau_xor_ca_t XOR_CA[9];         //!< [0x988] General Purpose Register 0 - Exclusive Or command
+    uint8_t _reserved5[20];
+    __O hw_cau_rotl_casr_t ROTL_CASR;      //!< [0x9C0] Status register  - Rotate Left command
+    __O hw_cau_rotl_caa_t ROTL_CAA;        //!< [0x9C4] Accumulator register - Rotate Left command
+    __O hw_cau_rotl_ca_t ROTL_CA[9];       //!< [0x9C8] General Purpose Register 0 - Rotate Left command
+    uint8_t _reserved6[276];
+    __O hw_cau_aesc_casr_t AESC_CASR;      //!< [0xB00] Status register  - AES Column Operation command
+    __O hw_cau_aesc_caa_t AESC_CAA;        //!< [0xB04] Accumulator register - AES Column Operation command
+    __O hw_cau_aesc_ca_t AESC_CA[9];       //!< [0xB08] General Purpose Register 0 - AES Column Operation command
+    uint8_t _reserved7[20];
+    __O hw_cau_aesic_casr_t AESIC_CASR;    //!< [0xB40] Status register  - AES Inverse Column Operation command
+    __O hw_cau_aesic_caa_t AESIC_CAA;      //!< [0xB44] Accumulator register - AES Inverse Column Operation command
+    __O hw_cau_aesic_ca_t AESIC_CA[9];     //!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command
+} hw_cau_t;
+#pragma pack()
+
+//! @brief Macro to access all CAU registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_CAU</code>.
+#define HW_CAU         (*(hw_cau_t *) REGS_CAU_BASE)
+#endif
+
+#endif // __HW_CAU_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h
new file mode 100644
index 0000000000..cb02d608d2
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h
@@ -0,0 +1,1018 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CMP_REGISTERS_H__
+#define __HW_CMP_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - HW_CMP_CR0 - CMP Control Register 0
+ * - HW_CMP_CR1 - CMP Control Register 1
+ * - HW_CMP_FPR - CMP Filter Period Register
+ * - HW_CMP_SCR - CMP Status and Control Register
+ * - HW_CMP_DACCR - DAC Control Register
+ * - HW_CMP_MUXCR - MUX Control Register
+ *
+ * - hw_cmp_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CMP_BASE
+#define HW_CMP_INSTANCE_COUNT (3U) //!< Number of instances of the CMP module.
+#define HW_CMP0 (0U) //!< Instance number for CMP0.
+#define HW_CMP1 (1U) //!< Instance number for CMP1.
+#define HW_CMP2 (2U) //!< Instance number for CMP2.
+#define REGS_CMP0_BASE (0x40073000U) //!< Base address for CMP0.
+#define REGS_CMP1_BASE (0x40073008U) //!< Base address for CMP1.
+#define REGS_CMP2_BASE (0x40073010U) //!< Base address for CMP2.
+
+//! @brief Table of base addresses for CMP instances.
+static const uint32_t __g_regs_CMP_base_addresses[] = {
+        REGS_CMP0_BASE,
+        REGS_CMP1_BASE,
+        REGS_CMP2_BASE,
+    };
+
+//! @brief Get the base address of CMP by instance number.
+//! @param x CMP instance number, from 0 through 2.
+#define REGS_CMP_BASE(x) (__g_regs_CMP_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of CMP.
+#define REGS_CMP_INSTANCE(b) ((b) == REGS_CMP0_BASE ? HW_CMP0 : (b) == REGS_CMP1_BASE ? HW_CMP1 : (b) == REGS_CMP2_BASE ? HW_CMP2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_CR0 - CMP Control Register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_cr0
+{
+    uint8_t U;
+    struct _hw_cmp_cr0_bitfields
+    {
+        uint8_t HYSTCTR : 2;           //!< [1:0] Comparator hard block hysteresis
+                                       //! control
+        uint8_t RESERVED0 : 2;         //!< [3:2]
+        uint8_t FILTER_CNT : 3;        //!< [6:4] Filter Sample Count
+        uint8_t RESERVED1 : 1;         //!< [7]
+    } B;
+} hw_cmp_cr0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+//@{
+#define HW_CMP_CR0_ADDR(x)       (REGS_CMP_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_CR0(x)            (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
+#define HW_CMP_CR0_RD(x)         (HW_CMP_CR0(x).U)
+#define HW_CMP_CR0_WR(x, v)      (HW_CMP_CR0(x).U = (v))
+#define HW_CMP_CR0_SET(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) |  (v)))
+#define HW_CMP_CR0_CLR(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
+#define HW_CMP_CR0_TOG(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 00 - Level 0
+ * - 01 - Level 1
+ * - 10 - Level 2
+ * - 11 - Level 3
+ */
+//@{
+#define BP_CMP_CR0_HYSTCTR   (0U)          //!< Bit position for CMP_CR0_HYSTCTR.
+#define BM_CMP_CR0_HYSTCTR   (0x03U)       //!< Bit mask for CMP_CR0_HYSTCTR.
+#define BS_CMP_CR0_HYSTCTR   (2U)          //!< Bit field size in bits for CMP_CR0_HYSTCTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR0_HYSTCTR field.
+#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
+#endif
+
+//! @brief Format value for bitfield CMP_CR0_HYSTCTR.
+#define BF_CMP_CR0_HYSTCTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_HYSTCTR), uint8_t) & BM_CMP_CR0_HYSTCTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HYSTCTR field to a new value.
+#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
+ *     legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 001 - One sample must agree. The comparator output is simply sampled.
+ * - 010 - 2 consecutive samples must agree.
+ * - 011 - 3 consecutive samples must agree.
+ * - 100 - 4 consecutive samples must agree.
+ * - 101 - 5 consecutive samples must agree.
+ * - 110 - 6 consecutive samples must agree.
+ * - 111 - 7 consecutive samples must agree.
+ */
+//@{
+#define BP_CMP_CR0_FILTER_CNT (4U)         //!< Bit position for CMP_CR0_FILTER_CNT.
+#define BM_CMP_CR0_FILTER_CNT (0x70U)      //!< Bit mask for CMP_CR0_FILTER_CNT.
+#define BS_CMP_CR0_FILTER_CNT (3U)         //!< Bit field size in bits for CMP_CR0_FILTER_CNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR0_FILTER_CNT field.
+#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
+#endif
+
+//! @brief Format value for bitfield CMP_CR0_FILTER_CNT.
+#define BF_CMP_CR0_FILTER_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_FILTER_CNT), uint8_t) & BM_CMP_CR0_FILTER_CNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTER_CNT field to a new value.
+#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_CR1 - CMP Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_cr1
+{
+    uint8_t U;
+    struct _hw_cmp_cr1_bitfields
+    {
+        uint8_t EN : 1;                //!< [0] Comparator Module Enable
+        uint8_t OPE : 1;               //!< [1] Comparator Output Pin Enable
+        uint8_t COS : 1;               //!< [2] Comparator Output Select
+        uint8_t INV : 1;               //!< [3] Comparator INVERT
+        uint8_t PMODE : 1;             //!< [4] Power Mode Select
+        uint8_t RESERVED0 : 1;         //!< [5]
+        uint8_t WE : 1;                //!< [6] Windowing Enable
+        uint8_t SE : 1;                //!< [7] Sample Enable
+    } B;
+} hw_cmp_cr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+//@{
+#define HW_CMP_CR1_ADDR(x)       (REGS_CMP_BASE(x) + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_CR1(x)            (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
+#define HW_CMP_CR1_RD(x)         (HW_CMP_CR1(x).U)
+#define HW_CMP_CR1_WR(x, v)      (HW_CMP_CR1(x).U = (v))
+#define HW_CMP_CR1_SET(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) |  (v)))
+#define HW_CMP_CR1_CLR(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
+#define HW_CMP_CR1_TOG(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0 - Analog Comparator is disabled.
+ * - 1 - Analog Comparator is enabled.
+ */
+//@{
+#define BP_CMP_CR1_EN        (0U)          //!< Bit position for CMP_CR1_EN.
+#define BM_CMP_CR1_EN        (0x01U)       //!< Bit mask for CMP_CR1_EN.
+#define BS_CMP_CR1_EN        (1U)          //!< Bit field size in bits for CMP_CR1_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_EN field.
+#define BR_CMP_CR1_EN(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_EN.
+#define BF_CMP_CR1_EN(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_EN), uint8_t) & BM_CMP_CR1_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_CMP_CR1_EN(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has no
+ *     effect.
+ */
+//@{
+#define BP_CMP_CR1_OPE       (1U)          //!< Bit position for CMP_CR1_OPE.
+#define BM_CMP_CR1_OPE       (0x02U)       //!< Bit mask for CMP_CR1_OPE.
+#define BS_CMP_CR1_OPE       (1U)          //!< Bit field size in bits for CMP_CR1_OPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_OPE field.
+#define BR_CMP_CR1_OPE(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_OPE.
+#define BF_CMP_CR1_OPE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_OPE), uint8_t) & BM_CMP_CR1_OPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OPE field to a new value.
+#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+//@{
+#define BP_CMP_CR1_COS       (2U)          //!< Bit position for CMP_CR1_COS.
+#define BM_CMP_CR1_COS       (0x04U)       //!< Bit mask for CMP_CR1_COS.
+#define BS_CMP_CR1_COS       (1U)          //!< Bit field size in bits for CMP_CR1_COS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_COS field.
+#define BR_CMP_CR1_COS(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_COS.
+#define BF_CMP_CR1_COS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_COS), uint8_t) & BM_CMP_CR1_COS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COS field to a new value.
+#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0 - Does not invert the comparator output.
+ * - 1 - Inverts the comparator output.
+ */
+//@{
+#define BP_CMP_CR1_INV       (3U)          //!< Bit position for CMP_CR1_INV.
+#define BM_CMP_CR1_INV       (0x08U)       //!< Bit mask for CMP_CR1_INV.
+#define BS_CMP_CR1_INV       (1U)          //!< Bit field size in bits for CMP_CR1_INV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_INV field.
+#define BR_CMP_CR1_INV(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_INV.
+#define BF_CMP_CR1_INV(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_INV), uint8_t) & BM_CMP_CR1_INV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV field to a new value.
+#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
+ *     output propagation delay and higher current consumption.
+ */
+//@{
+#define BP_CMP_CR1_PMODE     (4U)          //!< Bit position for CMP_CR1_PMODE.
+#define BM_CMP_CR1_PMODE     (0x10U)       //!< Bit mask for CMP_CR1_PMODE.
+#define BS_CMP_CR1_PMODE     (1U)          //!< Bit field size in bits for CMP_CR1_PMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_PMODE field.
+#define BR_CMP_CR1_PMODE(x)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_PMODE.
+#define BF_CMP_CR1_PMODE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_PMODE), uint8_t) & BM_CMP_CR1_PMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PMODE field to a new value.
+#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0 - Windowing mode is not selected.
+ * - 1 - Windowing mode is selected.
+ */
+//@{
+#define BP_CMP_CR1_WE        (6U)          //!< Bit position for CMP_CR1_WE.
+#define BM_CMP_CR1_WE        (0x40U)       //!< Bit mask for CMP_CR1_WE.
+#define BS_CMP_CR1_WE        (1U)          //!< Bit field size in bits for CMP_CR1_WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_WE field.
+#define BR_CMP_CR1_WE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_WE.
+#define BF_CMP_CR1_WE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_WE), uint8_t) & BM_CMP_CR1_WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WE field to a new value.
+#define BW_CMP_CR1_WE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0 - Sampling mode is not selected.
+ * - 1 - Sampling mode is selected.
+ */
+//@{
+#define BP_CMP_CR1_SE        (7U)          //!< Bit position for CMP_CR1_SE.
+#define BM_CMP_CR1_SE        (0x80U)       //!< Bit mask for CMP_CR1_SE.
+#define BS_CMP_CR1_SE        (1U)          //!< Bit field size in bits for CMP_CR1_SE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_SE field.
+#define BR_CMP_CR1_SE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_SE.
+#define BF_CMP_CR1_SE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_SE), uint8_t) & BM_CMP_CR1_SE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SE field to a new value.
+#define BW_CMP_CR1_SE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_FPR - CMP Filter Period Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_fpr
+{
+    uint8_t U;
+    struct _hw_cmp_fpr_bitfields
+    {
+        uint8_t FILT_PER : 8;          //!< [7:0] Filter Sample Period
+    } B;
+} hw_cmp_fpr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+//@{
+#define HW_CMP_FPR_ADDR(x)       (REGS_CMP_BASE(x) + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_FPR(x)            (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
+#define HW_CMP_FPR_RD(x)         (HW_CMP_FPR(x).U)
+#define HW_CMP_FPR_WR(x, v)      (HW_CMP_FPR(x).U = (v))
+#define HW_CMP_FPR_SET(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) |  (v)))
+#define HW_CMP_FPR_CLR(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
+#define HW_CMP_FPR_TOG(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_FPR bitfields
+ */
+
+/*!
+ * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
+ *
+ * Specifies the sampling period, in bus clock cycles, of the comparator output
+ * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
+ * programming and latency details appear in the Functional descriptionThe CMP
+ * module can be used to compare two analog input voltages applied to INP and INM. .
+ * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
+ * signal is used to determine the sampling period.
+ */
+//@{
+#define BP_CMP_FPR_FILT_PER  (0U)          //!< Bit position for CMP_FPR_FILT_PER.
+#define BM_CMP_FPR_FILT_PER  (0xFFU)       //!< Bit mask for CMP_FPR_FILT_PER.
+#define BS_CMP_FPR_FILT_PER  (8U)          //!< Bit field size in bits for CMP_FPR_FILT_PER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_FPR_FILT_PER field.
+#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
+#endif
+
+//! @brief Format value for bitfield CMP_FPR_FILT_PER.
+#define BF_CMP_FPR_FILT_PER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_FPR_FILT_PER), uint8_t) & BM_CMP_FPR_FILT_PER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILT_PER field to a new value.
+#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_SCR - CMP Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_scr
+{
+    uint8_t U;
+    struct _hw_cmp_scr_bitfields
+    {
+        uint8_t COUT : 1;              //!< [0] Analog Comparator Output
+        uint8_t CFF : 1;               //!< [1] Analog Comparator Flag Falling
+        uint8_t CFR : 1;               //!< [2] Analog Comparator Flag Rising
+        uint8_t IEF : 1;               //!< [3] Comparator Interrupt Enable Falling
+        uint8_t IER : 1;               //!< [4] Comparator Interrupt Enable Rising
+        uint8_t RESERVED0 : 1;         //!< [5]
+        uint8_t DMAEN : 1;             //!< [6] DMA Enable Control
+        uint8_t RESERVED1 : 1;         //!< [7]
+    } B;
+} hw_cmp_scr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+//@{
+#define HW_CMP_SCR_ADDR(x)       (REGS_CMP_BASE(x) + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_SCR(x)            (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
+#define HW_CMP_SCR_RD(x)         (HW_CMP_SCR(x).U)
+#define HW_CMP_SCR_WR(x, v)      (HW_CMP_SCR(x).U = (v))
+#define HW_CMP_SCR_SET(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) |  (v)))
+#define HW_CMP_SCR_CLR(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
+#define HW_CMP_SCR_TOG(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+//@{
+#define BP_CMP_SCR_COUT      (0U)          //!< Bit position for CMP_SCR_COUT.
+#define BM_CMP_SCR_COUT      (0x01U)       //!< Bit mask for CMP_SCR_COUT.
+#define BS_CMP_SCR_COUT      (1U)          //!< Bit field size in bits for CMP_SCR_COUT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_COUT field.
+#define BR_CMP_SCR_COUT(x)   (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0 - Falling-edge on COUT has not been detected.
+ * - 1 - Falling-edge on COUT has occurred.
+ */
+//@{
+#define BP_CMP_SCR_CFF       (1U)          //!< Bit position for CMP_SCR_CFF.
+#define BM_CMP_SCR_CFF       (0x02U)       //!< Bit mask for CMP_SCR_CFF.
+#define BS_CMP_SCR_CFF       (1U)          //!< Bit field size in bits for CMP_SCR_CFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_CFF field.
+#define BR_CMP_SCR_CFF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_CFF.
+#define BF_CMP_SCR_CFF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFF), uint8_t) & BM_CMP_SCR_CFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CFF field to a new value.
+#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0 - Rising-edge on COUT has not been detected.
+ * - 1 - Rising-edge on COUT has occurred.
+ */
+//@{
+#define BP_CMP_SCR_CFR       (2U)          //!< Bit position for CMP_SCR_CFR.
+#define BM_CMP_SCR_CFR       (0x04U)       //!< Bit mask for CMP_SCR_CFR.
+#define BS_CMP_SCR_CFR       (1U)          //!< Bit field size in bits for CMP_SCR_CFR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_CFR field.
+#define BR_CMP_SCR_CFR(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_CFR.
+#define BF_CMP_SCR_CFR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFR), uint8_t) & BM_CMP_SCR_CFR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CFR field to a new value.
+#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0 - Interrupt is disabled.
+ * - 1 - Interrupt is enabled.
+ */
+//@{
+#define BP_CMP_SCR_IEF       (3U)          //!< Bit position for CMP_SCR_IEF.
+#define BM_CMP_SCR_IEF       (0x08U)       //!< Bit mask for CMP_SCR_IEF.
+#define BS_CMP_SCR_IEF       (1U)          //!< Bit field size in bits for CMP_SCR_IEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_IEF field.
+#define BR_CMP_SCR_IEF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_IEF.
+#define BF_CMP_SCR_IEF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IEF), uint8_t) & BM_CMP_SCR_IEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IEF field to a new value.
+#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0 - Interrupt is disabled.
+ * - 1 - Interrupt is enabled.
+ */
+//@{
+#define BP_CMP_SCR_IER       (4U)          //!< Bit position for CMP_SCR_IER.
+#define BM_CMP_SCR_IER       (0x10U)       //!< Bit mask for CMP_SCR_IER.
+#define BS_CMP_SCR_IER       (1U)          //!< Bit field size in bits for CMP_SCR_IER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_IER field.
+#define BR_CMP_SCR_IER(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_IER.
+#define BF_CMP_SCR_IER(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IER), uint8_t) & BM_CMP_SCR_IER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IER field to a new value.
+#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled.
+ */
+//@{
+#define BP_CMP_SCR_DMAEN     (6U)          //!< Bit position for CMP_SCR_DMAEN.
+#define BM_CMP_SCR_DMAEN     (0x40U)       //!< Bit mask for CMP_SCR_DMAEN.
+#define BS_CMP_SCR_DMAEN     (1U)          //!< Bit field size in bits for CMP_SCR_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_DMAEN field.
+#define BR_CMP_SCR_DMAEN(x)  (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_DMAEN.
+#define BF_CMP_SCR_DMAEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_DMAEN), uint8_t) & BM_CMP_SCR_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_DACCR - DAC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_daccr
+{
+    uint8_t U;
+    struct _hw_cmp_daccr_bitfields
+    {
+        uint8_t VOSEL : 6;             //!< [5:0] DAC Output Voltage Select
+        uint8_t VRSEL : 1;             //!< [6] Supply Voltage Reference Source Select
+        uint8_t DACEN : 1;             //!< [7] DAC Enable
+    } B;
+} hw_cmp_daccr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+//@{
+#define HW_CMP_DACCR_ADDR(x)     (REGS_CMP_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_DACCR(x)          (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
+#define HW_CMP_DACCR_RD(x)       (HW_CMP_DACCR(x).U)
+#define HW_CMP_DACCR_WR(x, v)    (HW_CMP_DACCR(x).U = (v))
+#define HW_CMP_DACCR_SET(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) |  (v)))
+#define HW_CMP_DACCR_CLR(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
+#define HW_CMP_DACCR_TOG(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+//@{
+#define BP_CMP_DACCR_VOSEL   (0U)          //!< Bit position for CMP_DACCR_VOSEL.
+#define BM_CMP_DACCR_VOSEL   (0x3FU)       //!< Bit mask for CMP_DACCR_VOSEL.
+#define BS_CMP_DACCR_VOSEL   (6U)          //!< Bit field size in bits for CMP_DACCR_VOSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_DACCR_VOSEL field.
+#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
+#endif
+
+//! @brief Format value for bitfield CMP_DACCR_VOSEL.
+#define BF_CMP_DACCR_VOSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VOSEL), uint8_t) & BM_CMP_DACCR_VOSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VOSEL field to a new value.
+#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+//@{
+#define BP_CMP_DACCR_VRSEL   (6U)          //!< Bit position for CMP_DACCR_VRSEL.
+#define BM_CMP_DACCR_VRSEL   (0x40U)       //!< Bit mask for CMP_DACCR_VRSEL.
+#define BS_CMP_DACCR_VRSEL   (1U)          //!< Bit field size in bits for CMP_DACCR_VRSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_DACCR_VRSEL field.
+#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
+#endif
+
+//! @brief Format value for bitfield CMP_DACCR_VRSEL.
+#define BF_CMP_DACCR_VRSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VRSEL), uint8_t) & BM_CMP_DACCR_VRSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VRSEL field to a new value.
+#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0 - DAC is disabled.
+ * - 1 - DAC is enabled.
+ */
+//@{
+#define BP_CMP_DACCR_DACEN   (7U)          //!< Bit position for CMP_DACCR_DACEN.
+#define BM_CMP_DACCR_DACEN   (0x80U)       //!< Bit mask for CMP_DACCR_DACEN.
+#define BS_CMP_DACCR_DACEN   (1U)          //!< Bit field size in bits for CMP_DACCR_DACEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_DACCR_DACEN field.
+#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
+#endif
+
+//! @brief Format value for bitfield CMP_DACCR_DACEN.
+#define BF_CMP_DACCR_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_DACEN), uint8_t) & BM_CMP_DACCR_DACEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACEN field to a new value.
+#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_MUXCR - MUX Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_muxcr
+{
+    uint8_t U;
+    struct _hw_cmp_muxcr_bitfields
+    {
+        uint8_t MSEL : 3;              //!< [2:0] Minus Input Mux Control
+        uint8_t PSEL : 3;              //!< [5:3] Plus Input Mux Control
+        uint8_t RESERVED0 : 1;         //!< [6]
+        uint8_t PSTM : 1;              //!< [7] Pass Through Mode Enable
+    } B;
+} hw_cmp_muxcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+//@{
+#define HW_CMP_MUXCR_ADDR(x)     (REGS_CMP_BASE(x) + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_MUXCR(x)          (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
+#define HW_CMP_MUXCR_RD(x)       (HW_CMP_MUXCR(x).U)
+#define HW_CMP_MUXCR_WR(x, v)    (HW_CMP_MUXCR(x).U = (v))
+#define HW_CMP_MUXCR_SET(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) |  (v)))
+#define HW_CMP_MUXCR_CLR(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
+#define HW_CMP_MUXCR_TOG(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 000 - IN0
+ * - 001 - IN1
+ * - 010 - IN2
+ * - 011 - IN3
+ * - 100 - IN4
+ * - 101 - IN5
+ * - 110 - IN6
+ * - 111 - IN7
+ */
+//@{
+#define BP_CMP_MUXCR_MSEL    (0U)          //!< Bit position for CMP_MUXCR_MSEL.
+#define BM_CMP_MUXCR_MSEL    (0x07U)       //!< Bit mask for CMP_MUXCR_MSEL.
+#define BS_CMP_MUXCR_MSEL    (3U)          //!< Bit field size in bits for CMP_MUXCR_MSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_MUXCR_MSEL field.
+#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
+#endif
+
+//! @brief Format value for bitfield CMP_MUXCR_MSEL.
+#define BF_CMP_MUXCR_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_MSEL), uint8_t) & BM_CMP_MUXCR_MSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSEL field to a new value.
+#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 000 - IN0
+ * - 001 - IN1
+ * - 010 - IN2
+ * - 011 - IN3
+ * - 100 - IN4
+ * - 101 - IN5
+ * - 110 - IN6
+ * - 111 - IN7
+ */
+//@{
+#define BP_CMP_MUXCR_PSEL    (3U)          //!< Bit position for CMP_MUXCR_PSEL.
+#define BM_CMP_MUXCR_PSEL    (0x38U)       //!< Bit mask for CMP_MUXCR_PSEL.
+#define BS_CMP_MUXCR_PSEL    (3U)          //!< Bit field size in bits for CMP_MUXCR_PSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_MUXCR_PSEL field.
+#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
+#endif
+
+//! @brief Format value for bitfield CMP_MUXCR_PSEL.
+#define BF_CMP_MUXCR_PSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSEL), uint8_t) & BM_CMP_MUXCR_PSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSEL field to a new value.
+#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0 - Pass Through Mode is disabled.
+ * - 1 - Pass Through Mode is enabled.
+ */
+//@{
+#define BP_CMP_MUXCR_PSTM    (7U)          //!< Bit position for CMP_MUXCR_PSTM.
+#define BM_CMP_MUXCR_PSTM    (0x80U)       //!< Bit mask for CMP_MUXCR_PSTM.
+#define BS_CMP_MUXCR_PSTM    (1U)          //!< Bit field size in bits for CMP_MUXCR_PSTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_MUXCR_PSTM field.
+#define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
+#endif
+
+//! @brief Format value for bitfield CMP_MUXCR_PSTM.
+#define BF_CMP_MUXCR_PSTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSTM), uint8_t) & BM_CMP_MUXCR_PSTM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSTM field to a new value.
+#define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_cmp_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CMP module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_cmp
+{
+    __IO hw_cmp_cr0_t CR0;                 //!< [0x0] CMP Control Register 0
+    __IO hw_cmp_cr1_t CR1;                 //!< [0x1] CMP Control Register 1
+    __IO hw_cmp_fpr_t FPR;                 //!< [0x2] CMP Filter Period Register
+    __IO hw_cmp_scr_t SCR;                 //!< [0x3] CMP Status and Control Register
+    __IO hw_cmp_daccr_t DACCR;             //!< [0x4] DAC Control Register
+    __IO hw_cmp_muxcr_t MUXCR;             //!< [0x5] MUX Control Register
+} hw_cmp_t;
+#pragma pack()
+
+//! @brief Macro to access all CMP registers.
+//! @param x CMP instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_CMP(0)</code>.
+#define HW_CMP(x)      (*(hw_cmp_t *) REGS_CMP_BASE(x))
+#endif
+
+#endif // __HW_CMP_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h
new file mode 100644
index 0000000000..6adfd07a21
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h
@@ -0,0 +1,1194 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CMT_REGISTERS_H__
+#define __HW_CMT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - HW_CMT_OC - CMT Output Control Register
+ * - HW_CMT_MSC - CMT Modulator Status and Control Register
+ * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
+ * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - HW_CMT_PPS - CMT Primary Prescaler Register
+ * - HW_CMT_DMA - CMT Direct Memory Access Register
+ *
+ * - hw_cmt_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CMT_BASE
+#define HW_CMT_INSTANCE_COUNT (1U) //!< Number of instances of the CMT module.
+#define REGS_CMT_BASE (0x40062000U) //!< Base address for CMT.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+typedef union _hw_cmt_cgh1
+{
+    uint8_t U;
+    struct _hw_cmt_cgh1_bitfields
+    {
+        uint8_t PH : 8;                //!< [7:0] Primary Carrier High Time Data Value
+    } B;
+} hw_cmt_cgh1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+//@{
+#define HW_CMT_CGH1_ADDR         (REGS_CMT_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGH1              (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR)
+#define HW_CMT_CGH1_RD()         (HW_CMT_CGH1.U)
+#define HW_CMT_CGH1_WR(v)        (HW_CMT_CGH1.U = (v))
+#define HW_CMT_CGH1_SET(v)       (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() |  (v)))
+#define HW_CMT_CGH1_CLR(v)       (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() & ~(v)))
+#define HW_CMT_CGH1_TOG(v)       (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGH1 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGH1, field PH[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier high
+ * time period. When operating in Time mode, this register is always selected. When
+ * operating in FSK mode, this register and the secondary register pair are
+ * alternately selected under the control of the modulator. The primary carrier high
+ * time value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled to avoid spurious results.
+ */
+//@{
+#define BP_CMT_CGH1_PH       (0U)          //!< Bit position for CMT_CGH1_PH.
+#define BM_CMT_CGH1_PH       (0xFFU)       //!< Bit mask for CMT_CGH1_PH.
+#define BS_CMT_CGH1_PH       (8U)          //!< Bit field size in bits for CMT_CGH1_PH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGH1_PH field.
+#define BR_CMT_CGH1_PH       (HW_CMT_CGH1.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGH1_PH.
+#define BF_CMT_CGH1_PH(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH1_PH), uint8_t) & BM_CMT_CGH1_PH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PH field to a new value.
+#define BW_CMT_CGH1_PH(v)    (HW_CMT_CGH1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+typedef union _hw_cmt_cgl1
+{
+    uint8_t U;
+    struct _hw_cmt_cgl1_bitfields
+    {
+        uint8_t PL : 8;                //!< [7:0] Primary Carrier Low Time Data Value
+    } B;
+} hw_cmt_cgl1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+//@{
+#define HW_CMT_CGL1_ADDR         (REGS_CMT_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGL1              (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR)
+#define HW_CMT_CGL1_RD()         (HW_CMT_CGL1.U)
+#define HW_CMT_CGL1_WR(v)        (HW_CMT_CGL1.U = (v))
+#define HW_CMT_CGL1_SET(v)       (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() |  (v)))
+#define HW_CMT_CGL1_CLR(v)       (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() & ~(v)))
+#define HW_CMT_CGL1_TOG(v)       (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGL1 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGL1, field PL[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier low time
+ * period. When operating in Time mode, this register is always selected. When
+ * operating in FSK mode, this register and the secondary register pair are
+ * alternately selected under the control of the modulator. The primary carrier low
+ * time value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled to avoid spurious results.
+ */
+//@{
+#define BP_CMT_CGL1_PL       (0U)          //!< Bit position for CMT_CGL1_PL.
+#define BM_CMT_CGL1_PL       (0xFFU)       //!< Bit mask for CMT_CGL1_PL.
+#define BS_CMT_CGL1_PL       (8U)          //!< Bit field size in bits for CMT_CGL1_PL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGL1_PL field.
+#define BR_CMT_CGL1_PL       (HW_CMT_CGL1.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGL1_PL.
+#define BF_CMT_CGL1_PL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL1_PL), uint8_t) & BM_CMT_CGL1_PL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PL field to a new value.
+#define BW_CMT_CGL1_PL(v)    (HW_CMT_CGL1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+typedef union _hw_cmt_cgh2
+{
+    uint8_t U;
+    struct _hw_cmt_cgh2_bitfields
+    {
+        uint8_t SH : 8;                //!< [7:0] Secondary Carrier High Time Data Value
+    } B;
+} hw_cmt_cgh2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+//@{
+#define HW_CMT_CGH2_ADDR         (REGS_CMT_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGH2              (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR)
+#define HW_CMT_CGH2_RD()         (HW_CMT_CGH2.U)
+#define HW_CMT_CGH2_WR(v)        (HW_CMT_CGH2.U = (v))
+#define HW_CMT_CGH2_SET(v)       (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() |  (v)))
+#define HW_CMT_CGH2_CLR(v)       (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() & ~(v)))
+#define HW_CMT_CGH2_TOG(v)       (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGH2 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGH2, field SH[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier high
+ * time period. When operating in Time mode, this register is never selected. When
+ * operating in FSK mode, this register and the primary register pair are
+ * alternately selected under control of the modulator. The secondary carrier high time
+ * value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled when operating in FSK mode.
+ */
+//@{
+#define BP_CMT_CGH2_SH       (0U)          //!< Bit position for CMT_CGH2_SH.
+#define BM_CMT_CGH2_SH       (0xFFU)       //!< Bit mask for CMT_CGH2_SH.
+#define BS_CMT_CGH2_SH       (8U)          //!< Bit field size in bits for CMT_CGH2_SH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGH2_SH field.
+#define BR_CMT_CGH2_SH       (HW_CMT_CGH2.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGH2_SH.
+#define BF_CMT_CGH2_SH(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH2_SH), uint8_t) & BM_CMT_CGH2_SH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SH field to a new value.
+#define BW_CMT_CGH2_SH(v)    (HW_CMT_CGH2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+typedef union _hw_cmt_cgl2
+{
+    uint8_t U;
+    struct _hw_cmt_cgl2_bitfields
+    {
+        uint8_t SL : 8;                //!< [7:0] Secondary Carrier Low Time Data Value
+    } B;
+} hw_cmt_cgl2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+//@{
+#define HW_CMT_CGL2_ADDR         (REGS_CMT_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGL2              (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR)
+#define HW_CMT_CGL2_RD()         (HW_CMT_CGL2.U)
+#define HW_CMT_CGL2_WR(v)        (HW_CMT_CGL2.U = (v))
+#define HW_CMT_CGL2_SET(v)       (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() |  (v)))
+#define HW_CMT_CGL2_CLR(v)       (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() & ~(v)))
+#define HW_CMT_CGL2_TOG(v)       (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGL2 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGL2, field SL[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier low time
+ * period. When operating in Time mode, this register is never selected. When
+ * operating in FSK mode, this register and the primary register pair are
+ * alternately selected under the control of the modulator. The secondary carrier low time
+ * value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled when operating in FSK mode.
+ */
+//@{
+#define BP_CMT_CGL2_SL       (0U)          //!< Bit position for CMT_CGL2_SL.
+#define BM_CMT_CGL2_SL       (0xFFU)       //!< Bit mask for CMT_CGL2_SL.
+#define BS_CMT_CGL2_SL       (8U)          //!< Bit field size in bits for CMT_CGL2_SL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGL2_SL field.
+#define BR_CMT_CGL2_SL       (HW_CMT_CGL2.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGL2_SL.
+#define BF_CMT_CGL2_SL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL2_SL), uint8_t) & BM_CMT_CGL2_SL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SL field to a new value.
+#define BW_CMT_CGL2_SL(v)    (HW_CMT_CGL2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_OC - CMT Output Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+typedef union _hw_cmt_oc
+{
+    uint8_t U;
+    struct _hw_cmt_oc_bitfields
+    {
+        uint8_t RESERVED0 : 5;         //!< [4:0]
+        uint8_t IROPEN : 1;            //!< [5] IRO Pin Enable
+        uint8_t CMTPOL : 1;            //!< [6] CMT Output Polarity
+        uint8_t IROL : 1;              //!< [7] IRO Latch Control
+    } B;
+} hw_cmt_oc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+//@{
+#define HW_CMT_OC_ADDR           (REGS_CMT_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_OC                (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR)
+#define HW_CMT_OC_RD()           (HW_CMT_OC.U)
+#define HW_CMT_OC_WR(v)          (HW_CMT_OC.U = (v))
+#define HW_CMT_OC_SET(v)         (HW_CMT_OC_WR(HW_CMT_OC_RD() |  (v)))
+#define HW_CMT_OC_CLR(v)         (HW_CMT_OC_WR(HW_CMT_OC_RD() & ~(v)))
+#define HW_CMT_OC_TOG(v)         (HW_CMT_OC_WR(HW_CMT_OC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0 - The IRO signal is disabled.
+ * - 1 - The IRO signal is enabled as output.
+ */
+//@{
+#define BP_CMT_OC_IROPEN     (5U)          //!< Bit position for CMT_OC_IROPEN.
+#define BM_CMT_OC_IROPEN     (0x20U)       //!< Bit mask for CMT_OC_IROPEN.
+#define BS_CMT_OC_IROPEN     (1U)          //!< Bit field size in bits for CMT_OC_IROPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_OC_IROPEN field.
+#define BR_CMT_OC_IROPEN     (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN))
+#endif
+
+//! @brief Format value for bitfield CMT_OC_IROPEN.
+#define BF_CMT_OC_IROPEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROPEN), uint8_t) & BM_CMT_OC_IROPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IROPEN field to a new value.
+#define BW_CMT_OC_IROPEN(v)  (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0 - The IRO signal is active-low.
+ * - 1 - The IRO signal is active-high.
+ */
+//@{
+#define BP_CMT_OC_CMTPOL     (6U)          //!< Bit position for CMT_OC_CMTPOL.
+#define BM_CMT_OC_CMTPOL     (0x40U)       //!< Bit mask for CMT_OC_CMTPOL.
+#define BS_CMT_OC_CMTPOL     (1U)          //!< Bit field size in bits for CMT_OC_CMTPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_OC_CMTPOL field.
+#define BR_CMT_OC_CMTPOL     (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL))
+#endif
+
+//! @brief Format value for bitfield CMT_OC_CMTPOL.
+#define BF_CMT_OC_CMTPOL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_CMTPOL), uint8_t) & BM_CMT_OC_CMTPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMTPOL field to a new value.
+#define BW_CMT_OC_CMTPOL(v)  (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+//@{
+#define BP_CMT_OC_IROL       (7U)          //!< Bit position for CMT_OC_IROL.
+#define BM_CMT_OC_IROL       (0x80U)       //!< Bit mask for CMT_OC_IROL.
+#define BS_CMT_OC_IROL       (1U)          //!< Bit field size in bits for CMT_OC_IROL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_OC_IROL field.
+#define BR_CMT_OC_IROL       (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL))
+#endif
+
+//! @brief Format value for bitfield CMT_OC_IROL.
+#define BF_CMT_OC_IROL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROL), uint8_t) & BM_CMT_OC_IROL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IROL field to a new value.
+#define BW_CMT_OC_IROL(v)    (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_MSC - CMT Modulator Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+typedef union _hw_cmt_msc
+{
+    uint8_t U;
+    struct _hw_cmt_msc_bitfields
+    {
+        uint8_t MCGEN : 1;             //!< [0] Modulator and Carrier Generator Enable
+        uint8_t EOCIE : 1;             //!< [1] End of Cycle Interrupt Enable
+        uint8_t FSK : 1;               //!< [2] FSK Mode Select
+        uint8_t BASE : 1;              //!< [3] Baseband Enable
+        uint8_t EXSPC : 1;             //!< [4] Extended Space Enable
+        uint8_t CMTDIV : 2;            //!< [6:5] CMT Clock Divide Prescaler
+        uint8_t EOCF : 1;              //!< [7] End Of Cycle Status Flag
+    } B;
+} hw_cmt_msc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+//@{
+#define HW_CMT_MSC_ADDR          (REGS_CMT_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_MSC               (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR)
+#define HW_CMT_MSC_RD()          (HW_CMT_MSC.U)
+#define HW_CMT_MSC_WR(v)         (HW_CMT_MSC.U = (v))
+#define HW_CMT_MSC_SET(v)        (HW_CMT_MSC_WR(HW_CMT_MSC_RD() |  (v)))
+#define HW_CMT_MSC_CLR(v)        (HW_CMT_MSC_WR(HW_CMT_MSC_RD() & ~(v)))
+#define HW_CMT_MSC_TOG(v)        (HW_CMT_MSC_WR(HW_CMT_MSC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0 - Modulator and carrier generator disabled
+ * - 1 - Modulator and carrier generator enabled
+ */
+//@{
+#define BP_CMT_MSC_MCGEN     (0U)          //!< Bit position for CMT_MSC_MCGEN.
+#define BM_CMT_MSC_MCGEN     (0x01U)       //!< Bit mask for CMT_MSC_MCGEN.
+#define BS_CMT_MSC_MCGEN     (1U)          //!< Bit field size in bits for CMT_MSC_MCGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_MCGEN field.
+#define BR_CMT_MSC_MCGEN     (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_MCGEN.
+#define BF_CMT_MSC_MCGEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_MCGEN), uint8_t) & BM_CMT_MSC_MCGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MCGEN field to a new value.
+#define BW_CMT_MSC_MCGEN(v)  (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0 - CPU interrupt is disabled.
+ * - 1 - CPU interrupt is enabled.
+ */
+//@{
+#define BP_CMT_MSC_EOCIE     (1U)          //!< Bit position for CMT_MSC_EOCIE.
+#define BM_CMT_MSC_EOCIE     (0x02U)       //!< Bit mask for CMT_MSC_EOCIE.
+#define BS_CMT_MSC_EOCIE     (1U)          //!< Bit field size in bits for CMT_MSC_EOCIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_EOCIE field.
+#define BR_CMT_MSC_EOCIE     (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_EOCIE.
+#define BF_CMT_MSC_EOCIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EOCIE), uint8_t) & BM_CMT_MSC_EOCIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOCIE field to a new value.
+#define BW_CMT_MSC_EOCIE(v)  (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0 - The CMT operates in Time or Baseband mode.
+ * - 1 - The CMT operates in FSK mode.
+ */
+//@{
+#define BP_CMT_MSC_FSK       (2U)          //!< Bit position for CMT_MSC_FSK.
+#define BM_CMT_MSC_FSK       (0x04U)       //!< Bit mask for CMT_MSC_FSK.
+#define BS_CMT_MSC_FSK       (1U)          //!< Bit field size in bits for CMT_MSC_FSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_FSK field.
+#define BR_CMT_MSC_FSK       (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_FSK.
+#define BF_CMT_MSC_FSK(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_FSK), uint8_t) & BM_CMT_MSC_FSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSK field to a new value.
+#define BW_CMT_MSC_FSK(v)    (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0 - Baseband mode is disabled.
+ * - 1 - Baseband mode is enabled.
+ */
+//@{
+#define BP_CMT_MSC_BASE      (3U)          //!< Bit position for CMT_MSC_BASE.
+#define BM_CMT_MSC_BASE      (0x08U)       //!< Bit mask for CMT_MSC_BASE.
+#define BS_CMT_MSC_BASE      (1U)          //!< Bit field size in bits for CMT_MSC_BASE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_BASE field.
+#define BR_CMT_MSC_BASE      (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_BASE.
+#define BF_CMT_MSC_BASE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_BASE), uint8_t) & BM_CMT_MSC_BASE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BASE field to a new value.
+#define BW_CMT_MSC_BASE(v)   (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0 - Extended space is disabled.
+ * - 1 - Extended space is enabled.
+ */
+//@{
+#define BP_CMT_MSC_EXSPC     (4U)          //!< Bit position for CMT_MSC_EXSPC.
+#define BM_CMT_MSC_EXSPC     (0x10U)       //!< Bit mask for CMT_MSC_EXSPC.
+#define BS_CMT_MSC_EXSPC     (1U)          //!< Bit field size in bits for CMT_MSC_EXSPC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_EXSPC field.
+#define BR_CMT_MSC_EXSPC     (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_EXSPC.
+#define BF_CMT_MSC_EXSPC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EXSPC), uint8_t) & BM_CMT_MSC_EXSPC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXSPC field to a new value.
+#define BW_CMT_MSC_EXSPC(v)  (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 00 - IF * 1
+ * - 01 - IF * 2
+ * - 10 - IF * 4
+ * - 11 - IF * 8
+ */
+//@{
+#define BP_CMT_MSC_CMTDIV    (5U)          //!< Bit position for CMT_MSC_CMTDIV.
+#define BM_CMT_MSC_CMTDIV    (0x60U)       //!< Bit mask for CMT_MSC_CMTDIV.
+#define BS_CMT_MSC_CMTDIV    (2U)          //!< Bit field size in bits for CMT_MSC_CMTDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_CMTDIV field.
+#define BR_CMT_MSC_CMTDIV    (HW_CMT_MSC.B.CMTDIV)
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_CMTDIV.
+#define BF_CMT_MSC_CMTDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_CMTDIV), uint8_t) & BM_CMT_MSC_CMTDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMTDIV field to a new value.
+#define BW_CMT_MSC_CMTDIV(v) (HW_CMT_MSC_WR((HW_CMT_MSC_RD() & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 1 - End of modulator cycle has occurred.
+ */
+//@{
+#define BP_CMT_MSC_EOCF      (7U)          //!< Bit position for CMT_MSC_EOCF.
+#define BM_CMT_MSC_EOCF      (0x80U)       //!< Bit mask for CMT_MSC_EOCF.
+#define BS_CMT_MSC_EOCF      (1U)          //!< Bit field size in bits for CMT_MSC_EOCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_EOCF field.
+#define BR_CMT_MSC_EOCF      (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD1 - CMT Modulator Data Register Mark High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd1
+{
+    uint8_t U;
+    struct _hw_cmt_cmd1_bitfields
+    {
+        uint8_t MB : 8;                //!< [7:0]
+    } B;
+} hw_cmt_cmd1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+//@{
+#define HW_CMT_CMD1_ADDR         (REGS_CMT_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD1              (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR)
+#define HW_CMT_CMD1_RD()         (HW_CMT_CMD1.U)
+#define HW_CMT_CMD1_WR(v)        (HW_CMT_CMD1.U = (v))
+#define HW_CMT_CMD1_SET(v)       (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() |  (v)))
+#define HW_CMT_CMD1_CLR(v)       (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() & ~(v)))
+#define HW_CMT_CMD1_TOG(v)       (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD1 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD1, field MB[7:0] (RW)
+ *
+ * Controls the upper mark periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD1_MB       (0U)          //!< Bit position for CMT_CMD1_MB.
+#define BM_CMT_CMD1_MB       (0xFFU)       //!< Bit mask for CMT_CMD1_MB.
+#define BS_CMT_CMD1_MB       (8U)          //!< Bit field size in bits for CMT_CMD1_MB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD1_MB field.
+#define BR_CMT_CMD1_MB       (HW_CMT_CMD1.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD1_MB.
+#define BF_CMT_CMD1_MB(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD1_MB), uint8_t) & BM_CMT_CMD1_MB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MB field to a new value.
+#define BW_CMT_CMD1_MB(v)    (HW_CMT_CMD1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd2
+{
+    uint8_t U;
+    struct _hw_cmt_cmd2_bitfields
+    {
+        uint8_t MB : 8;                //!< [7:0]
+    } B;
+} hw_cmt_cmd2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+//@{
+#define HW_CMT_CMD2_ADDR         (REGS_CMT_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD2              (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR)
+#define HW_CMT_CMD2_RD()         (HW_CMT_CMD2.U)
+#define HW_CMT_CMD2_WR(v)        (HW_CMT_CMD2.U = (v))
+#define HW_CMT_CMD2_SET(v)       (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() |  (v)))
+#define HW_CMT_CMD2_CLR(v)       (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() & ~(v)))
+#define HW_CMT_CMD2_TOG(v)       (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD2 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD2, field MB[7:0] (RW)
+ *
+ * Controls the lower mark periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD2_MB       (0U)          //!< Bit position for CMT_CMD2_MB.
+#define BM_CMT_CMD2_MB       (0xFFU)       //!< Bit mask for CMT_CMD2_MB.
+#define BS_CMT_CMD2_MB       (8U)          //!< Bit field size in bits for CMT_CMD2_MB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD2_MB field.
+#define BR_CMT_CMD2_MB       (HW_CMT_CMD2.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD2_MB.
+#define BF_CMT_CMD2_MB(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD2_MB), uint8_t) & BM_CMT_CMD2_MB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MB field to a new value.
+#define BW_CMT_CMD2_MB(v)    (HW_CMT_CMD2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD3 - CMT Modulator Data Register Space High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd3
+{
+    uint8_t U;
+    struct _hw_cmt_cmd3_bitfields
+    {
+        uint8_t SB : 8;                //!< [7:0]
+    } B;
+} hw_cmt_cmd3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+//@{
+#define HW_CMT_CMD3_ADDR         (REGS_CMT_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD3              (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR)
+#define HW_CMT_CMD3_RD()         (HW_CMT_CMD3.U)
+#define HW_CMT_CMD3_WR(v)        (HW_CMT_CMD3.U = (v))
+#define HW_CMT_CMD3_SET(v)       (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() |  (v)))
+#define HW_CMT_CMD3_CLR(v)       (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() & ~(v)))
+#define HW_CMT_CMD3_TOG(v)       (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD3 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD3, field SB[7:0] (RW)
+ *
+ * Controls the upper space periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD3_SB       (0U)          //!< Bit position for CMT_CMD3_SB.
+#define BM_CMT_CMD3_SB       (0xFFU)       //!< Bit mask for CMT_CMD3_SB.
+#define BS_CMT_CMD3_SB       (8U)          //!< Bit field size in bits for CMT_CMD3_SB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD3_SB field.
+#define BR_CMT_CMD3_SB       (HW_CMT_CMD3.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD3_SB.
+#define BF_CMT_CMD3_SB(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD3_SB), uint8_t) & BM_CMT_CMD3_SB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SB field to a new value.
+#define BW_CMT_CMD3_SB(v)    (HW_CMT_CMD3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD4 - CMT Modulator Data Register Space Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd4
+{
+    uint8_t U;
+    struct _hw_cmt_cmd4_bitfields
+    {
+        uint8_t SB : 8;                //!< [7:0]
+    } B;
+} hw_cmt_cmd4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+//@{
+#define HW_CMT_CMD4_ADDR         (REGS_CMT_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD4              (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR)
+#define HW_CMT_CMD4_RD()         (HW_CMT_CMD4.U)
+#define HW_CMT_CMD4_WR(v)        (HW_CMT_CMD4.U = (v))
+#define HW_CMT_CMD4_SET(v)       (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() |  (v)))
+#define HW_CMT_CMD4_CLR(v)       (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() & ~(v)))
+#define HW_CMT_CMD4_TOG(v)       (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD4 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD4, field SB[7:0] (RW)
+ *
+ * Controls the lower space periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD4_SB       (0U)          //!< Bit position for CMT_CMD4_SB.
+#define BM_CMT_CMD4_SB       (0xFFU)       //!< Bit mask for CMT_CMD4_SB.
+#define BS_CMT_CMD4_SB       (8U)          //!< Bit field size in bits for CMT_CMD4_SB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD4_SB field.
+#define BR_CMT_CMD4_SB       (HW_CMT_CMD4.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD4_SB.
+#define BF_CMT_CMD4_SB(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD4_SB), uint8_t) & BM_CMT_CMD4_SB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SB field to a new value.
+#define BW_CMT_CMD4_SB(v)    (HW_CMT_CMD4_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_PPS - CMT Primary Prescaler Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+typedef union _hw_cmt_pps
+{
+    uint8_t U;
+    struct _hw_cmt_pps_bitfields
+    {
+        uint8_t PPSDIV : 4;            //!< [3:0] Primary Prescaler Divider
+        uint8_t RESERVED0 : 4;         //!< [7:4]
+    } B;
+} hw_cmt_pps_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+//@{
+#define HW_CMT_PPS_ADDR          (REGS_CMT_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_PPS               (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR)
+#define HW_CMT_PPS_RD()          (HW_CMT_PPS.U)
+#define HW_CMT_PPS_WR(v)         (HW_CMT_PPS.U = (v))
+#define HW_CMT_PPS_SET(v)        (HW_CMT_PPS_WR(HW_CMT_PPS_RD() |  (v)))
+#define HW_CMT_PPS_CLR(v)        (HW_CMT_PPS_WR(HW_CMT_PPS_RD() & ~(v)))
+#define HW_CMT_PPS_TOG(v)        (HW_CMT_PPS_WR(HW_CMT_PPS_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0000 - Bus clock * 1
+ * - 0001 - Bus clock * 2
+ * - 0010 - Bus clock * 3
+ * - 0011 - Bus clock * 4
+ * - 0100 - Bus clock * 5
+ * - 0101 - Bus clock * 6
+ * - 0110 - Bus clock * 7
+ * - 0111 - Bus clock * 8
+ * - 1000 - Bus clock * 9
+ * - 1001 - Bus clock * 10
+ * - 1010 - Bus clock * 11
+ * - 1011 - Bus clock * 12
+ * - 1100 - Bus clock * 13
+ * - 1101 - Bus clock * 14
+ * - 1110 - Bus clock * 15
+ * - 1111 - Bus clock * 16
+ */
+//@{
+#define BP_CMT_PPS_PPSDIV    (0U)          //!< Bit position for CMT_PPS_PPSDIV.
+#define BM_CMT_PPS_PPSDIV    (0x0FU)       //!< Bit mask for CMT_PPS_PPSDIV.
+#define BS_CMT_PPS_PPSDIV    (4U)          //!< Bit field size in bits for CMT_PPS_PPSDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_PPS_PPSDIV field.
+#define BR_CMT_PPS_PPSDIV    (HW_CMT_PPS.B.PPSDIV)
+#endif
+
+//! @brief Format value for bitfield CMT_PPS_PPSDIV.
+#define BF_CMT_PPS_PPSDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_PPS_PPSDIV), uint8_t) & BM_CMT_PPS_PPSDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PPSDIV field to a new value.
+#define BW_CMT_PPS_PPSDIV(v) (HW_CMT_PPS_WR((HW_CMT_PPS_RD() & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_DMA - CMT Direct Memory Access Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+typedef union _hw_cmt_dma
+{
+    uint8_t U;
+    struct _hw_cmt_dma_bitfields
+    {
+        uint8_t DMAb : 1;              //!< [0] DMA Enable
+        uint8_t RESERVED0 : 7;         //!< [7:1]
+    } B;
+} hw_cmt_dma_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+//@{
+#define HW_CMT_DMA_ADDR          (REGS_CMT_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_DMA               (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR)
+#define HW_CMT_DMA_RD()          (HW_CMT_DMA.U)
+#define HW_CMT_DMA_WR(v)         (HW_CMT_DMA.U = (v))
+#define HW_CMT_DMA_SET(v)        (HW_CMT_DMA_WR(HW_CMT_DMA_RD() |  (v)))
+#define HW_CMT_DMA_CLR(v)        (HW_CMT_DMA_WR(HW_CMT_DMA_RD() & ~(v)))
+#define HW_CMT_DMA_TOG(v)        (HW_CMT_DMA_WR(HW_CMT_DMA_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0 - DMA transfer request and done are disabled.
+ * - 1 - DMA transfer request and done are enabled.
+ */
+//@{
+#define BP_CMT_DMA_DMA       (0U)          //!< Bit position for CMT_DMA_DMA.
+#define BM_CMT_DMA_DMA       (0x01U)       //!< Bit mask for CMT_DMA_DMA.
+#define BS_CMT_DMA_DMA       (1U)          //!< Bit field size in bits for CMT_DMA_DMA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_DMA_DMA field.
+#define BR_CMT_DMA_DMA       (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA))
+#endif
+
+//! @brief Format value for bitfield CMT_DMA_DMA.
+#define BF_CMT_DMA_DMA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_DMA_DMA), uint8_t) & BM_CMT_DMA_DMA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMA field to a new value.
+#define BW_CMT_DMA_DMA(v)    (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_cmt_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CMT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_cmt
+{
+    __IO hw_cmt_cgh1_t CGH1;               //!< [0x0] CMT Carrier Generator High Data Register 1
+    __IO hw_cmt_cgl1_t CGL1;               //!< [0x1] CMT Carrier Generator Low Data Register 1
+    __IO hw_cmt_cgh2_t CGH2;               //!< [0x2] CMT Carrier Generator High Data Register 2
+    __IO hw_cmt_cgl2_t CGL2;               //!< [0x3] CMT Carrier Generator Low Data Register 2
+    __IO hw_cmt_oc_t OC;                   //!< [0x4] CMT Output Control Register
+    __IO hw_cmt_msc_t MSC;                 //!< [0x5] CMT Modulator Status and Control Register
+    __IO hw_cmt_cmd1_t CMD1;               //!< [0x6] CMT Modulator Data Register Mark High
+    __IO hw_cmt_cmd2_t CMD2;               //!< [0x7] CMT Modulator Data Register Mark Low
+    __IO hw_cmt_cmd3_t CMD3;               //!< [0x8] CMT Modulator Data Register Space High
+    __IO hw_cmt_cmd4_t CMD4;               //!< [0x9] CMT Modulator Data Register Space Low
+    __IO hw_cmt_pps_t PPS;                 //!< [0xA] CMT Primary Prescaler Register
+    __IO hw_cmt_dma_t DMA;                 //!< [0xB] CMT Direct Memory Access Register
+} hw_cmt_t;
+#pragma pack()
+
+//! @brief Macro to access all CMT registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_CMT</code>.
+#define HW_CMT         (*(hw_cmt_t *) REGS_CMT_BASE)
+#endif
+
+#endif // __HW_CMT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h
new file mode 100644
index 0000000000..89e818cdc6
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h
@@ -0,0 +1,1499 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CRC_REGISTERS_H__
+#define __HW_CRC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - HW_CRC_DATAL - CRC_DATAL register.
+ * - HW_CRC_DATAH - CRC_DATAH register.
+ * - HW_CRC_DATALL - CRC_DATALL register.
+ * - HW_CRC_DATALU - CRC_DATALU register.
+ * - HW_CRC_DATAHL - CRC_DATAHL register.
+ * - HW_CRC_DATAHU - CRC_DATAHU register.
+ * - HW_CRC_DATA - CRC Data register
+ * - HW_CRC_GPOLY - CRC Polynomial register
+ * - HW_CRC_GPOLYL - CRC_GPOLYL register.
+ * - HW_CRC_GPOLYH - CRC_GPOLYH register.
+ * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - HW_CRC_CTRL - CRC Control register
+ * - HW_CRC_CTRLHU - CRC_CTRLHU register.
+ *
+ * - hw_crc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CRC_BASE
+#define HW_CRC_INSTANCE_COUNT (1U) //!< Number of instances of the CRC module.
+#define REGS_CRC_BASE (0x40032000U) //!< Base address for CRC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAL - CRC_DATAL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_datal
+{
+    uint16_t U;
+    struct _hw_crc_datal_bitfields
+    {
+        uint16_t DATAL : 16;           //!< [15:0] DATAL stores the lower 16 bits of
+                                       //! the 16/32 bit CRC
+    } B;
+} hw_crc_datal_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+//@{
+#define HW_CRC_DATAL_ADDR        (REGS_CRC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAL             (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR)
+#define HW_CRC_DATAL_RD()        (HW_CRC_DATAL.U)
+#define HW_CRC_DATAL_WR(v)       (HW_CRC_DATAL.U = (v))
+#define HW_CRC_DATAL_SET(v)      (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() |  (v)))
+#define HW_CRC_DATAL_CLR(v)      (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() & ~(v)))
+#define HW_CRC_DATAL_TOG(v)      (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAL bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAL, field DATAL[15:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAL_DATAL   (0U)          //!< Bit position for CRC_DATAL_DATAL.
+#define BM_CRC_DATAL_DATAL   (0xFFFFU)     //!< Bit mask for CRC_DATAL_DATAL.
+#define BS_CRC_DATAL_DATAL   (16U)         //!< Bit field size in bits for CRC_DATAL_DATAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAL_DATAL field.
+#define BR_CRC_DATAL_DATAL   (HW_CRC_DATAL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAL_DATAL.
+#define BF_CRC_DATAL_DATAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAL_DATAL), uint16_t) & BM_CRC_DATAL_DATAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAL field to a new value.
+#define BW_CRC_DATAL_DATAL(v) (HW_CRC_DATAL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAH - CRC_DATAH register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_datah
+{
+    uint16_t U;
+    struct _hw_crc_datah_bitfields
+    {
+        uint16_t DATAH : 16;           //!< [15:0] DATAH stores the high 16 bits of the
+                                       //! 16/32 bit CRC
+    } B;
+} hw_crc_datah_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+//@{
+#define HW_CRC_DATAH_ADDR        (REGS_CRC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAH             (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR)
+#define HW_CRC_DATAH_RD()        (HW_CRC_DATAH.U)
+#define HW_CRC_DATAH_WR(v)       (HW_CRC_DATAH.U = (v))
+#define HW_CRC_DATAH_SET(v)      (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() |  (v)))
+#define HW_CRC_DATAH_CLR(v)      (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() & ~(v)))
+#define HW_CRC_DATAH_TOG(v)      (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAH bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAH, field DATAH[15:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAH_DATAH   (0U)          //!< Bit position for CRC_DATAH_DATAH.
+#define BM_CRC_DATAH_DATAH   (0xFFFFU)     //!< Bit mask for CRC_DATAH_DATAH.
+#define BS_CRC_DATAH_DATAH   (16U)         //!< Bit field size in bits for CRC_DATAH_DATAH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAH_DATAH field.
+#define BR_CRC_DATAH_DATAH   (HW_CRC_DATAH.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAH_DATAH.
+#define BF_CRC_DATAH_DATAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAH_DATAH), uint16_t) & BM_CRC_DATAH_DATAH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAH field to a new value.
+#define BW_CRC_DATAH_DATAH(v) (HW_CRC_DATAH_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATALL - CRC_DATALL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datall
+{
+    uint8_t U;
+    struct _hw_crc_datall_bitfields
+    {
+        uint8_t DATALL : 8;            //!< [7:0] CRCLL stores the first 8 bits of the
+                                       //! 32 bit DATA
+    } B;
+} hw_crc_datall_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+//@{
+#define HW_CRC_DATALL_ADDR       (REGS_CRC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATALL            (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR)
+#define HW_CRC_DATALL_RD()       (HW_CRC_DATALL.U)
+#define HW_CRC_DATALL_WR(v)      (HW_CRC_DATALL.U = (v))
+#define HW_CRC_DATALL_SET(v)     (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() |  (v)))
+#define HW_CRC_DATALL_CLR(v)     (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() & ~(v)))
+#define HW_CRC_DATALL_TOG(v)     (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATALL bitfields
+ */
+
+/*!
+ * @name Register CRC_DATALL, field DATALL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATALL_DATALL (0U)          //!< Bit position for CRC_DATALL_DATALL.
+#define BM_CRC_DATALL_DATALL (0xFFU)       //!< Bit mask for CRC_DATALL_DATALL.
+#define BS_CRC_DATALL_DATALL (8U)          //!< Bit field size in bits for CRC_DATALL_DATALL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATALL_DATALL field.
+#define BR_CRC_DATALL_DATALL (HW_CRC_DATALL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATALL_DATALL.
+#define BF_CRC_DATALL_DATALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALL_DATALL), uint8_t) & BM_CRC_DATALL_DATALL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATALL field to a new value.
+#define BW_CRC_DATALL_DATALL(v) (HW_CRC_DATALL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATALU - CRC_DATALU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datalu
+{
+    uint8_t U;
+    struct _hw_crc_datalu_bitfields
+    {
+        uint8_t DATALU : 8;            //!< [7:0] DATALL stores the second 8 bits of the
+                                       //! 32 bit CRC
+    } B;
+} hw_crc_datalu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+//@{
+#define HW_CRC_DATALU_ADDR       (REGS_CRC_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATALU            (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR)
+#define HW_CRC_DATALU_RD()       (HW_CRC_DATALU.U)
+#define HW_CRC_DATALU_WR(v)      (HW_CRC_DATALU.U = (v))
+#define HW_CRC_DATALU_SET(v)     (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() |  (v)))
+#define HW_CRC_DATALU_CLR(v)     (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() & ~(v)))
+#define HW_CRC_DATALU_TOG(v)     (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATALU bitfields
+ */
+
+/*!
+ * @name Register CRC_DATALU, field DATALU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATALU_DATALU (0U)          //!< Bit position for CRC_DATALU_DATALU.
+#define BM_CRC_DATALU_DATALU (0xFFU)       //!< Bit mask for CRC_DATALU_DATALU.
+#define BS_CRC_DATALU_DATALU (8U)          //!< Bit field size in bits for CRC_DATALU_DATALU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATALU_DATALU field.
+#define BR_CRC_DATALU_DATALU (HW_CRC_DATALU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATALU_DATALU.
+#define BF_CRC_DATALU_DATALU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALU_DATALU), uint8_t) & BM_CRC_DATALU_DATALU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATALU field to a new value.
+#define BW_CRC_DATALU_DATALU(v) (HW_CRC_DATALU_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAHL - CRC_DATAHL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datahl
+{
+    uint8_t U;
+    struct _hw_crc_datahl_bitfields
+    {
+        uint8_t DATAHL : 8;            //!< [7:0] DATAHL stores the third 8 bits of the
+                                       //! 32 bit CRC
+    } B;
+} hw_crc_datahl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+//@{
+#define HW_CRC_DATAHL_ADDR       (REGS_CRC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAHL            (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR)
+#define HW_CRC_DATAHL_RD()       (HW_CRC_DATAHL.U)
+#define HW_CRC_DATAHL_WR(v)      (HW_CRC_DATAHL.U = (v))
+#define HW_CRC_DATAHL_SET(v)     (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() |  (v)))
+#define HW_CRC_DATAHL_CLR(v)     (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() & ~(v)))
+#define HW_CRC_DATAHL_TOG(v)     (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAHL bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAHL_DATAHL (0U)          //!< Bit position for CRC_DATAHL_DATAHL.
+#define BM_CRC_DATAHL_DATAHL (0xFFU)       //!< Bit mask for CRC_DATAHL_DATAHL.
+#define BS_CRC_DATAHL_DATAHL (8U)          //!< Bit field size in bits for CRC_DATAHL_DATAHL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAHL_DATAHL field.
+#define BR_CRC_DATAHL_DATAHL (HW_CRC_DATAHL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAHL_DATAHL.
+#define BF_CRC_DATAHL_DATAHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHL_DATAHL), uint8_t) & BM_CRC_DATAHL_DATAHL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAHL field to a new value.
+#define BW_CRC_DATAHL_DATAHL(v) (HW_CRC_DATAHL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAHU - CRC_DATAHU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datahu
+{
+    uint8_t U;
+    struct _hw_crc_datahu_bitfields
+    {
+        uint8_t DATAHU : 8;            //!< [7:0] DATAHU stores the fourth 8 bits of the
+                                       //! 32 bit CRC
+    } B;
+} hw_crc_datahu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+//@{
+#define HW_CRC_DATAHU_ADDR       (REGS_CRC_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAHU            (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR)
+#define HW_CRC_DATAHU_RD()       (HW_CRC_DATAHU.U)
+#define HW_CRC_DATAHU_WR(v)      (HW_CRC_DATAHU.U = (v))
+#define HW_CRC_DATAHU_SET(v)     (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() |  (v)))
+#define HW_CRC_DATAHU_CLR(v)     (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() & ~(v)))
+#define HW_CRC_DATAHU_TOG(v)     (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAHU bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAHU_DATAHU (0U)          //!< Bit position for CRC_DATAHU_DATAHU.
+#define BM_CRC_DATAHU_DATAHU (0xFFU)       //!< Bit mask for CRC_DATAHU_DATAHU.
+#define BS_CRC_DATAHU_DATAHU (8U)          //!< Bit field size in bits for CRC_DATAHU_DATAHU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAHU_DATAHU field.
+#define BR_CRC_DATAHU_DATAHU (HW_CRC_DATAHU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAHU_DATAHU.
+#define BF_CRC_DATAHU_DATAHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHU_DATAHU), uint8_t) & BM_CRC_DATAHU_DATAHU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAHU field to a new value.
+#define BW_CRC_DATAHU_DATAHU(v) (HW_CRC_DATAHU_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATA - CRC Data register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+typedef union _hw_crc_data
+{
+    uint32_t U;
+    struct _hw_crc_data_bitfields
+    {
+        uint32_t LL : 8;               //!< [7:0] CRC Low Lower Byte
+        uint32_t LU : 8;               //!< [15:8] CRC Low Upper Byte
+        uint32_t HL : 8;               //!< [23:16] CRC High Lower Byte
+        uint32_t HU : 8;               //!< [31:24] CRC High Upper Byte
+    } B;
+} hw_crc_data_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+//@{
+#define HW_CRC_DATA_ADDR         (REGS_CRC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATA              (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR)
+#define HW_CRC_DATA_RD()         (HW_CRC_DATA.U)
+#define HW_CRC_DATA_WR(v)        (HW_CRC_DATA.U = (v))
+#define HW_CRC_DATA_SET(v)       (HW_CRC_DATA_WR(HW_CRC_DATA_RD() |  (v)))
+#define HW_CRC_DATA_CLR(v)       (HW_CRC_DATA_WR(HW_CRC_DATA_RD() & ~(v)))
+#define HW_CRC_DATA_TOG(v)       (HW_CRC_DATA_WR(HW_CRC_DATA_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+//@{
+#define BP_CRC_DATA_LL       (0U)          //!< Bit position for CRC_DATA_LL.
+#define BM_CRC_DATA_LL       (0x000000FFU) //!< Bit mask for CRC_DATA_LL.
+#define BS_CRC_DATA_LL       (8U)          //!< Bit field size in bits for CRC_DATA_LL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_LL field.
+#define BR_CRC_DATA_LL       (HW_CRC_DATA.B.LL)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_LL.
+#define BF_CRC_DATA_LL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LL), uint32_t) & BM_CRC_DATA_LL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LL field to a new value.
+#define BW_CRC_DATA_LL(v)    (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+//@{
+#define BP_CRC_DATA_LU       (8U)          //!< Bit position for CRC_DATA_LU.
+#define BM_CRC_DATA_LU       (0x0000FF00U) //!< Bit mask for CRC_DATA_LU.
+#define BS_CRC_DATA_LU       (8U)          //!< Bit field size in bits for CRC_DATA_LU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_LU field.
+#define BR_CRC_DATA_LU       (HW_CRC_DATA.B.LU)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_LU.
+#define BF_CRC_DATA_LU(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LU), uint32_t) & BM_CRC_DATA_LU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LU field to a new value.
+#define BW_CRC_DATA_LU(v)    (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+//@{
+#define BP_CRC_DATA_HL       (16U)         //!< Bit position for CRC_DATA_HL.
+#define BM_CRC_DATA_HL       (0x00FF0000U) //!< Bit mask for CRC_DATA_HL.
+#define BS_CRC_DATA_HL       (8U)          //!< Bit field size in bits for CRC_DATA_HL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_HL field.
+#define BR_CRC_DATA_HL       (HW_CRC_DATA.B.HL)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_HL.
+#define BF_CRC_DATA_HL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HL), uint32_t) & BM_CRC_DATA_HL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HL field to a new value.
+#define BW_CRC_DATA_HL(v)    (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+//@{
+#define BP_CRC_DATA_HU       (24U)         //!< Bit position for CRC_DATA_HU.
+#define BM_CRC_DATA_HU       (0xFF000000U) //!< Bit mask for CRC_DATA_HU.
+#define BS_CRC_DATA_HU       (8U)          //!< Bit field size in bits for CRC_DATA_HU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_HU field.
+#define BR_CRC_DATA_HU       (HW_CRC_DATA.B.HU)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_HU.
+#define BF_CRC_DATA_HU(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HU), uint32_t) & BM_CRC_DATA_HU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HU field to a new value.
+#define BW_CRC_DATA_HU(v)    (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLY - CRC Polynomial register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+typedef union _hw_crc_gpoly
+{
+    uint32_t U;
+    struct _hw_crc_gpoly_bitfields
+    {
+        uint32_t LOW : 16;             //!< [15:0] Low Polynominal Half-word
+        uint32_t HIGH : 16;            //!< [31:16] High Polynominal Half-word
+    } B;
+} hw_crc_gpoly_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+//@{
+#define HW_CRC_GPOLY_ADDR        (REGS_CRC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLY             (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR)
+#define HW_CRC_GPOLY_RD()        (HW_CRC_GPOLY.U)
+#define HW_CRC_GPOLY_WR(v)       (HW_CRC_GPOLY.U = (v))
+#define HW_CRC_GPOLY_SET(v)      (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() |  (v)))
+#define HW_CRC_GPOLY_CLR(v)      (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() & ~(v)))
+#define HW_CRC_GPOLY_TOG(v)      (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+//@{
+#define BP_CRC_GPOLY_LOW     (0U)          //!< Bit position for CRC_GPOLY_LOW.
+#define BM_CRC_GPOLY_LOW     (0x0000FFFFU) //!< Bit mask for CRC_GPOLY_LOW.
+#define BS_CRC_GPOLY_LOW     (16U)         //!< Bit field size in bits for CRC_GPOLY_LOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLY_LOW field.
+#define BR_CRC_GPOLY_LOW     (HW_CRC_GPOLY.B.LOW)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLY_LOW.
+#define BF_CRC_GPOLY_LOW(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_LOW), uint32_t) & BM_CRC_GPOLY_LOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOW field to a new value.
+#define BW_CRC_GPOLY_LOW(v)  (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+//@{
+#define BP_CRC_GPOLY_HIGH    (16U)         //!< Bit position for CRC_GPOLY_HIGH.
+#define BM_CRC_GPOLY_HIGH    (0xFFFF0000U) //!< Bit mask for CRC_GPOLY_HIGH.
+#define BS_CRC_GPOLY_HIGH    (16U)         //!< Bit field size in bits for CRC_GPOLY_HIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLY_HIGH field.
+#define BR_CRC_GPOLY_HIGH    (HW_CRC_GPOLY.B.HIGH)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLY_HIGH.
+#define BF_CRC_GPOLY_HIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_HIGH), uint32_t) & BM_CRC_GPOLY_HIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HIGH field to a new value.
+#define BW_CRC_GPOLY_HIGH(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYL - CRC_GPOLYL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_gpolyl
+{
+    uint16_t U;
+    struct _hw_crc_gpolyl_bitfields
+    {
+        uint16_t GPOLYL : 16;          //!< [15:0] POLYL stores the lower 16 bits of
+                                       //! the 16/32 bit CRC polynomial value
+    } B;
+} hw_crc_gpolyl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+//@{
+#define HW_CRC_GPOLYL_ADDR       (REGS_CRC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYL            (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR)
+#define HW_CRC_GPOLYL_RD()       (HW_CRC_GPOLYL.U)
+#define HW_CRC_GPOLYL_WR(v)      (HW_CRC_GPOLYL.U = (v))
+#define HW_CRC_GPOLYL_SET(v)     (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() |  (v)))
+#define HW_CRC_GPOLYL_CLR(v)     (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() & ~(v)))
+#define HW_CRC_GPOLYL_TOG(v)     (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYL bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYL_GPOLYL (0U)          //!< Bit position for CRC_GPOLYL_GPOLYL.
+#define BM_CRC_GPOLYL_GPOLYL (0xFFFFU)     //!< Bit mask for CRC_GPOLYL_GPOLYL.
+#define BS_CRC_GPOLYL_GPOLYL (16U)         //!< Bit field size in bits for CRC_GPOLYL_GPOLYL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYL_GPOLYL field.
+#define BR_CRC_GPOLYL_GPOLYL (HW_CRC_GPOLYL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYL_GPOLYL.
+#define BF_CRC_GPOLYL_GPOLYL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYL_GPOLYL), uint16_t) & BM_CRC_GPOLYL_GPOLYL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYL field to a new value.
+#define BW_CRC_GPOLYL_GPOLYL(v) (HW_CRC_GPOLYL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYH - CRC_GPOLYH register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_gpolyh
+{
+    uint16_t U;
+    struct _hw_crc_gpolyh_bitfields
+    {
+        uint16_t GPOLYH : 16;          //!< [15:0] POLYH stores the high 16 bits of
+                                       //! the 16/32 bit CRC polynomial value
+    } B;
+} hw_crc_gpolyh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+//@{
+#define HW_CRC_GPOLYH_ADDR       (REGS_CRC_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYH            (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR)
+#define HW_CRC_GPOLYH_RD()       (HW_CRC_GPOLYH.U)
+#define HW_CRC_GPOLYH_WR(v)      (HW_CRC_GPOLYH.U = (v))
+#define HW_CRC_GPOLYH_SET(v)     (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() |  (v)))
+#define HW_CRC_GPOLYH_CLR(v)     (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() & ~(v)))
+#define HW_CRC_GPOLYH_TOG(v)     (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYH bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYH_GPOLYH (0U)          //!< Bit position for CRC_GPOLYH_GPOLYH.
+#define BM_CRC_GPOLYH_GPOLYH (0xFFFFU)     //!< Bit mask for CRC_GPOLYH_GPOLYH.
+#define BS_CRC_GPOLYH_GPOLYH (16U)         //!< Bit field size in bits for CRC_GPOLYH_GPOLYH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYH_GPOLYH field.
+#define BR_CRC_GPOLYH_GPOLYH (HW_CRC_GPOLYH.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYH_GPOLYH.
+#define BF_CRC_GPOLYH_GPOLYH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYH_GPOLYH), uint16_t) & BM_CRC_GPOLYH_GPOLYH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYH field to a new value.
+#define BW_CRC_GPOLYH_GPOLYH(v) (HW_CRC_GPOLYH_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYLL - CRC_GPOLYLL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolyll
+{
+    uint8_t U;
+    struct _hw_crc_gpolyll_bitfields
+    {
+        uint8_t GPOLYLL : 8;           //!< [7:0] POLYLL stores the first 8 bits of the
+                                       //! 32 bit CRC
+    } B;
+} hw_crc_gpolyll_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+//@{
+#define HW_CRC_GPOLYLL_ADDR      (REGS_CRC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYLL           (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR)
+#define HW_CRC_GPOLYLL_RD()      (HW_CRC_GPOLYLL.U)
+#define HW_CRC_GPOLYLL_WR(v)     (HW_CRC_GPOLYLL.U = (v))
+#define HW_CRC_GPOLYLL_SET(v)    (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() |  (v)))
+#define HW_CRC_GPOLYLL_CLR(v)    (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() & ~(v)))
+#define HW_CRC_GPOLYLL_TOG(v)    (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYLL bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYLL_GPOLYLL (0U)        //!< Bit position for CRC_GPOLYLL_GPOLYLL.
+#define BM_CRC_GPOLYLL_GPOLYLL (0xFFU)     //!< Bit mask for CRC_GPOLYLL_GPOLYLL.
+#define BS_CRC_GPOLYLL_GPOLYLL (8U)        //!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field.
+#define BR_CRC_GPOLYLL_GPOLYLL (HW_CRC_GPOLYLL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL.
+#define BF_CRC_GPOLYLL_GPOLYLL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLL_GPOLYLL), uint8_t) & BM_CRC_GPOLYLL_GPOLYLL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYLL field to a new value.
+#define BW_CRC_GPOLYLL_GPOLYLL(v) (HW_CRC_GPOLYLL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYLU - CRC_GPOLYLU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolylu
+{
+    uint8_t U;
+    struct _hw_crc_gpolylu_bitfields
+    {
+        uint8_t GPOLYLU : 8;           //!< [7:0] POLYLL stores the second 8 bits of
+                                       //! the 32 bit CRC
+    } B;
+} hw_crc_gpolylu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+//@{
+#define HW_CRC_GPOLYLU_ADDR      (REGS_CRC_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYLU           (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR)
+#define HW_CRC_GPOLYLU_RD()      (HW_CRC_GPOLYLU.U)
+#define HW_CRC_GPOLYLU_WR(v)     (HW_CRC_GPOLYLU.U = (v))
+#define HW_CRC_GPOLYLU_SET(v)    (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() |  (v)))
+#define HW_CRC_GPOLYLU_CLR(v)    (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() & ~(v)))
+#define HW_CRC_GPOLYLU_TOG(v)    (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYLU bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYLU_GPOLYLU (0U)        //!< Bit position for CRC_GPOLYLU_GPOLYLU.
+#define BM_CRC_GPOLYLU_GPOLYLU (0xFFU)     //!< Bit mask for CRC_GPOLYLU_GPOLYLU.
+#define BS_CRC_GPOLYLU_GPOLYLU (8U)        //!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field.
+#define BR_CRC_GPOLYLU_GPOLYLU (HW_CRC_GPOLYLU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU.
+#define BF_CRC_GPOLYLU_GPOLYLU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLU_GPOLYLU), uint8_t) & BM_CRC_GPOLYLU_GPOLYLU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYLU field to a new value.
+#define BW_CRC_GPOLYLU_GPOLYLU(v) (HW_CRC_GPOLYLU_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYHL - CRC_GPOLYHL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolyhl
+{
+    uint8_t U;
+    struct _hw_crc_gpolyhl_bitfields
+    {
+        uint8_t GPOLYHL : 8;           //!< [7:0] POLYHL stores the third 8 bits of the
+                                       //! 32 bit CRC
+    } B;
+} hw_crc_gpolyhl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+//@{
+#define HW_CRC_GPOLYHL_ADDR      (REGS_CRC_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYHL           (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR)
+#define HW_CRC_GPOLYHL_RD()      (HW_CRC_GPOLYHL.U)
+#define HW_CRC_GPOLYHL_WR(v)     (HW_CRC_GPOLYHL.U = (v))
+#define HW_CRC_GPOLYHL_SET(v)    (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() |  (v)))
+#define HW_CRC_GPOLYHL_CLR(v)    (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() & ~(v)))
+#define HW_CRC_GPOLYHL_TOG(v)    (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYHL bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYHL_GPOLYHL (0U)        //!< Bit position for CRC_GPOLYHL_GPOLYHL.
+#define BM_CRC_GPOLYHL_GPOLYHL (0xFFU)     //!< Bit mask for CRC_GPOLYHL_GPOLYHL.
+#define BS_CRC_GPOLYHL_GPOLYHL (8U)        //!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field.
+#define BR_CRC_GPOLYHL_GPOLYHL (HW_CRC_GPOLYHL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL.
+#define BF_CRC_GPOLYHL_GPOLYHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHL_GPOLYHL), uint8_t) & BM_CRC_GPOLYHL_GPOLYHL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYHL field to a new value.
+#define BW_CRC_GPOLYHL_GPOLYHL(v) (HW_CRC_GPOLYHL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYHU - CRC_GPOLYHU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolyhu
+{
+    uint8_t U;
+    struct _hw_crc_gpolyhu_bitfields
+    {
+        uint8_t GPOLYHU : 8;           //!< [7:0] POLYHU stores the fourth 8 bits of
+                                       //! the 32 bit CRC
+    } B;
+} hw_crc_gpolyhu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+//@{
+#define HW_CRC_GPOLYHU_ADDR      (REGS_CRC_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYHU           (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR)
+#define HW_CRC_GPOLYHU_RD()      (HW_CRC_GPOLYHU.U)
+#define HW_CRC_GPOLYHU_WR(v)     (HW_CRC_GPOLYHU.U = (v))
+#define HW_CRC_GPOLYHU_SET(v)    (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() |  (v)))
+#define HW_CRC_GPOLYHU_CLR(v)    (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() & ~(v)))
+#define HW_CRC_GPOLYHU_TOG(v)    (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYHU bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYHU_GPOLYHU (0U)        //!< Bit position for CRC_GPOLYHU_GPOLYHU.
+#define BM_CRC_GPOLYHU_GPOLYHU (0xFFU)     //!< Bit mask for CRC_GPOLYHU_GPOLYHU.
+#define BS_CRC_GPOLYHU_GPOLYHU (8U)        //!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field.
+#define BR_CRC_GPOLYHU_GPOLYHU (HW_CRC_GPOLYHU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU.
+#define BF_CRC_GPOLYHU_GPOLYHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHU_GPOLYHU), uint8_t) & BM_CRC_GPOLYHU_GPOLYHU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYHU field to a new value.
+#define BW_CRC_GPOLYHU_GPOLYHU(v) (HW_CRC_GPOLYHU_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CRC_CTRL - CRC Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+typedef union _hw_crc_ctrl
+{
+    uint32_t U;
+    struct _hw_crc_ctrl_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t TCRC : 1;             //!< [24]
+        uint32_t WAS : 1;              //!< [25] Write CRC Data Register As Seed
+        uint32_t FXOR : 1;             //!< [26] Complement Read Of CRC Data Register
+        uint32_t RESERVED1 : 1;        //!< [27]
+        uint32_t TOTR : 2;             //!< [29:28] Type Of Transpose For Read
+        uint32_t TOT : 2;              //!< [31:30] Type Of Transpose For Writes
+    } B;
+} hw_crc_ctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+//@{
+#define HW_CRC_CTRL_ADDR         (REGS_CRC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_CTRL              (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR)
+#define HW_CRC_CTRL_RD()         (HW_CRC_CTRL.U)
+#define HW_CRC_CTRL_WR(v)        (HW_CRC_CTRL.U = (v))
+#define HW_CRC_CTRL_SET(v)       (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() |  (v)))
+#define HW_CRC_CTRL_CLR(v)       (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() & ~(v)))
+#define HW_CRC_CTRL_TOG(v)       (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0 - 16-bit CRC protocol.
+ * - 1 - 32-bit CRC protocol.
+ */
+//@{
+#define BP_CRC_CTRL_TCRC     (24U)         //!< Bit position for CRC_CTRL_TCRC.
+#define BM_CRC_CTRL_TCRC     (0x01000000U) //!< Bit mask for CRC_CTRL_TCRC.
+#define BS_CRC_CTRL_TCRC     (1U)          //!< Bit field size in bits for CRC_CTRL_TCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_TCRC field.
+#define BR_CRC_CTRL_TCRC     (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_TCRC.
+#define BF_CRC_CTRL_TCRC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TCRC), uint32_t) & BM_CRC_CTRL_TCRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRC field to a new value.
+#define BW_CRC_CTRL_TCRC(v)  (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0 - Writes to the CRC data register are data values.
+ * - 1 - Writes to the CRC data register are seed values.
+ */
+//@{
+#define BP_CRC_CTRL_WAS      (25U)         //!< Bit position for CRC_CTRL_WAS.
+#define BM_CRC_CTRL_WAS      (0x02000000U) //!< Bit mask for CRC_CTRL_WAS.
+#define BS_CRC_CTRL_WAS      (1U)          //!< Bit field size in bits for CRC_CTRL_WAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_WAS field.
+#define BR_CRC_CTRL_WAS      (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_WAS.
+#define BF_CRC_CTRL_WAS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_WAS), uint32_t) & BM_CRC_CTRL_WAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAS field to a new value.
+#define BW_CRC_CTRL_WAS(v)   (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0 - No XOR on reading.
+ * - 1 - Invert or complement the read value of the CRC Data register.
+ */
+//@{
+#define BP_CRC_CTRL_FXOR     (26U)         //!< Bit position for CRC_CTRL_FXOR.
+#define BM_CRC_CTRL_FXOR     (0x04000000U) //!< Bit mask for CRC_CTRL_FXOR.
+#define BS_CRC_CTRL_FXOR     (1U)          //!< Bit field size in bits for CRC_CTRL_FXOR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_FXOR field.
+#define BR_CRC_CTRL_FXOR     (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_FXOR.
+#define BF_CRC_CTRL_FXOR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_FXOR), uint32_t) & BM_CRC_CTRL_FXOR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FXOR field to a new value.
+#define BW_CRC_CTRL_FXOR(v)  (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 00 - No transposition.
+ * - 01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRL_TOTR     (28U)         //!< Bit position for CRC_CTRL_TOTR.
+#define BM_CRC_CTRL_TOTR     (0x30000000U) //!< Bit mask for CRC_CTRL_TOTR.
+#define BS_CRC_CTRL_TOTR     (2U)          //!< Bit field size in bits for CRC_CTRL_TOTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_TOTR field.
+#define BR_CRC_CTRL_TOTR     (HW_CRC_CTRL.B.TOTR)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_TOTR.
+#define BF_CRC_CTRL_TOTR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOTR), uint32_t) & BM_CRC_CTRL_TOTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOTR field to a new value.
+#define BW_CRC_CTRL_TOTR(v)  (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 00 - No transposition.
+ * - 01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRL_TOT      (30U)         //!< Bit position for CRC_CTRL_TOT.
+#define BM_CRC_CTRL_TOT      (0xC0000000U) //!< Bit mask for CRC_CTRL_TOT.
+#define BS_CRC_CTRL_TOT      (2U)          //!< Bit field size in bits for CRC_CTRL_TOT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_TOT field.
+#define BR_CRC_CTRL_TOT      (HW_CRC_CTRL.B.TOT)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_TOT.
+#define BF_CRC_CTRL_TOT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOT), uint32_t) & BM_CRC_CTRL_TOT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOT field to a new value.
+#define BW_CRC_CTRL_TOT(v)   (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_CTRLHU - CRC_CTRLHU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_crc_ctrlhu
+{
+    uint8_t U;
+    struct _hw_crc_ctrlhu_bitfields
+    {
+        uint8_t TCRC : 1;              //!< [0]
+        uint8_t WAS : 1;               //!< [1]
+        uint8_t FXOR : 1;              //!< [2]
+        uint8_t RESERVED0 : 1;         //!< [3]
+        uint8_t TOTR : 2;              //!< [5:4]
+        uint8_t TOT : 2;               //!< [7:6]
+    } B;
+} hw_crc_ctrlhu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+//@{
+#define HW_CRC_CTRLHU_ADDR       (REGS_CRC_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_CTRLHU            (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR)
+#define HW_CRC_CTRLHU_RD()       (HW_CRC_CTRLHU.U)
+#define HW_CRC_CTRLHU_WR(v)      (HW_CRC_CTRLHU.U = (v))
+#define HW_CRC_CTRLHU_SET(v)     (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() |  (v)))
+#define HW_CRC_CTRLHU_CLR(v)     (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() & ~(v)))
+#define HW_CRC_CTRLHU_TOG(v)     (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0 - 16-bit CRC protocol.
+ * - 1 - 32-bit CRC protocol.
+ */
+//@{
+#define BP_CRC_CTRLHU_TCRC   (0U)          //!< Bit position for CRC_CTRLHU_TCRC.
+#define BM_CRC_CTRLHU_TCRC   (0x01U)       //!< Bit mask for CRC_CTRLHU_TCRC.
+#define BS_CRC_CTRLHU_TCRC   (1U)          //!< Bit field size in bits for CRC_CTRLHU_TCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_TCRC field.
+#define BR_CRC_CTRLHU_TCRC   (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_TCRC.
+#define BF_CRC_CTRLHU_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TCRC), uint8_t) & BM_CRC_CTRLHU_TCRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRC field to a new value.
+#define BW_CRC_CTRLHU_TCRC(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0 - Writes to CRC data register are data values.
+ * - 1 - Writes to CRC data reguster are seed values.
+ */
+//@{
+#define BP_CRC_CTRLHU_WAS    (1U)          //!< Bit position for CRC_CTRLHU_WAS.
+#define BM_CRC_CTRLHU_WAS    (0x02U)       //!< Bit mask for CRC_CTRLHU_WAS.
+#define BS_CRC_CTRLHU_WAS    (1U)          //!< Bit field size in bits for CRC_CTRLHU_WAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_WAS field.
+#define BR_CRC_CTRLHU_WAS    (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_WAS.
+#define BF_CRC_CTRLHU_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_WAS), uint8_t) & BM_CRC_CTRLHU_WAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAS field to a new value.
+#define BW_CRC_CTRLHU_WAS(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0 - No XOR on reading.
+ * - 1 - Invert or complement the read value of CRC data register.
+ */
+//@{
+#define BP_CRC_CTRLHU_FXOR   (2U)          //!< Bit position for CRC_CTRLHU_FXOR.
+#define BM_CRC_CTRLHU_FXOR   (0x04U)       //!< Bit mask for CRC_CTRLHU_FXOR.
+#define BS_CRC_CTRLHU_FXOR   (1U)          //!< Bit field size in bits for CRC_CTRLHU_FXOR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_FXOR field.
+#define BR_CRC_CTRLHU_FXOR   (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_FXOR.
+#define BF_CRC_CTRLHU_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_FXOR), uint8_t) & BM_CRC_CTRLHU_FXOR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FXOR field to a new value.
+#define BW_CRC_CTRLHU_FXOR(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 00 - No Transposition.
+ * - 01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRLHU_TOTR   (4U)          //!< Bit position for CRC_CTRLHU_TOTR.
+#define BM_CRC_CTRLHU_TOTR   (0x30U)       //!< Bit mask for CRC_CTRLHU_TOTR.
+#define BS_CRC_CTRLHU_TOTR   (2U)          //!< Bit field size in bits for CRC_CTRLHU_TOTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_TOTR field.
+#define BR_CRC_CTRLHU_TOTR   (HW_CRC_CTRLHU.B.TOTR)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_TOTR.
+#define BF_CRC_CTRLHU_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOTR), uint8_t) & BM_CRC_CTRLHU_TOTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOTR field to a new value.
+#define BW_CRC_CTRLHU_TOTR(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 00 - No Transposition.
+ * - 01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRLHU_TOT    (6U)          //!< Bit position for CRC_CTRLHU_TOT.
+#define BM_CRC_CTRLHU_TOT    (0xC0U)       //!< Bit mask for CRC_CTRLHU_TOT.
+#define BS_CRC_CTRLHU_TOT    (2U)          //!< Bit field size in bits for CRC_CTRLHU_TOT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_TOT field.
+#define BR_CRC_CTRLHU_TOT    (HW_CRC_CTRLHU.B.TOT)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_TOT.
+#define BF_CRC_CTRLHU_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOT), uint8_t) & BM_CRC_CTRLHU_TOT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOT field to a new value.
+#define BW_CRC_CTRLHU_TOT(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_crc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CRC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_crc
+{
+    union {
+        struct {
+            __IO hw_crc_datal_t DATAL;     //!< [0x0] CRC_DATAL register.
+            __IO hw_crc_datah_t DATAH;     //!< [0x2] CRC_DATAH register.
+        } ACCESS16BIT;
+        struct {
+            __IO hw_crc_datall_t DATALL;   //!< [0x0] CRC_DATALL register.
+            __IO hw_crc_datalu_t DATALU;   //!< [0x1] CRC_DATALU register.
+            __IO hw_crc_datahl_t DATAHL;   //!< [0x2] CRC_DATAHL register.
+            __IO hw_crc_datahu_t DATAHU;   //!< [0x3] CRC_DATAHU register.
+        } ACCESS8BIT;
+        __IO hw_crc_data_t DATA;           //!< [0x0] CRC Data register
+    };
+    union {
+        __IO hw_crc_gpoly_t GPOLY;         //!< [0x4] CRC Polynomial register
+        struct {
+            __IO hw_crc_gpolyl_t GPOLYL;   //!< [0x4] CRC_GPOLYL register.
+            __IO hw_crc_gpolyh_t GPOLYH;   //!< [0x6] CRC_GPOLYH register.
+        } GPOLY_ACCESS16BIT;
+        struct {
+            __IO hw_crc_gpolyll_t GPOLYLL; //!< [0x4] CRC_GPOLYLL register.
+            __IO hw_crc_gpolylu_t GPOLYLU; //!< [0x5] CRC_GPOLYLU register.
+            __IO hw_crc_gpolyhl_t GPOLYHL; //!< [0x6] CRC_GPOLYHL register.
+            __IO hw_crc_gpolyhu_t GPOLYHU; //!< [0x7] CRC_GPOLYHU register.
+        } GPOLY_ACCESS8BIT;
+    };
+    union {
+        __IO hw_crc_ctrl_t CTRL;           //!< [0x8] CRC Control register
+        struct {
+            uint8_t _reserved0[3];
+            __IO hw_crc_ctrlhu_t CTRLHU;   //!< [0xB] CRC_CTRLHU register.
+        } CTRL_ACCESS8BIT;
+    };
+} hw_crc_t;
+#pragma pack()
+
+//! @brief Macro to access all CRC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_CRC</code>.
+#define HW_CRC         (*(hw_crc_t *) REGS_CRC_BASE)
+#endif
+
+#endif // __HW_CRC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h
new file mode 100644
index 0000000000..a4d4a7a6f9
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h
@@ -0,0 +1,879 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_DAC_REGISTERS_H__
+#define __HW_DAC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - HW_DAC_DATnL - DAC Data Low Register
+ * - HW_DAC_DATnH - DAC Data High Register
+ * - HW_DAC_SR - DAC Status Register
+ * - HW_DAC_C0 - DAC Control Register
+ * - HW_DAC_C1 - DAC Control Register 1
+ * - HW_DAC_C2 - DAC Control Register 2
+ *
+ * - hw_dac_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_DAC_BASE
+#define HW_DAC_INSTANCE_COUNT (2U) //!< Number of instances of the DAC module.
+#define HW_DAC0 (0U) //!< Instance number for DAC0.
+#define HW_DAC1 (1U) //!< Instance number for DAC1.
+#define REGS_DAC0_BASE (0x400CC000U) //!< Base address for DAC0.
+#define REGS_DAC1_BASE (0x400CD000U) //!< Base address for DAC1.
+
+//! @brief Table of base addresses for DAC instances.
+static const uint32_t __g_regs_DAC_base_addresses[] = {
+        REGS_DAC0_BASE,
+        REGS_DAC1_BASE,
+    };
+
+//! @brief Get the base address of DAC by instance number.
+//! @param x DAC instance number, from 0 through 1.
+#define REGS_DAC_BASE(x) (__g_regs_DAC_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of DAC.
+#define REGS_DAC_INSTANCE(b) ((b) == REGS_DAC0_BASE ? HW_DAC0 : (b) == REGS_DAC1_BASE ? HW_DAC1 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_DATnL - DAC Data Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_dac_datnl
+{
+    uint8_t U;
+    struct _hw_dac_datnl_bitfields
+    {
+        uint8_t DATA0 : 8;             //!< [7:0]
+    } B;
+} hw_dac_datnl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_DATnL register
+ */
+//@{
+#define HW_DAC_DATnL_COUNT (16U)
+
+#define HW_DAC_DATnL_ADDR(x, n)  (REGS_DAC_BASE(x) + 0x0U + (0x2U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_DATnL(x, n)       (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
+#define HW_DAC_DATnL_RD(x, n)    (HW_DAC_DATnL(x, n).U)
+#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
+#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) |  (v)))
+#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
+#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_DATnL bitfields
+ */
+
+/*!
+ * @name Register DAC_DATnL, field DATA0[7:0] (RW)
+ *
+ * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
+ */
+//@{
+#define BP_DAC_DATnL_DATA0   (0U)          //!< Bit position for DAC_DATnL_DATA0.
+#define BM_DAC_DATnL_DATA0   (0xFFU)       //!< Bit mask for DAC_DATnL_DATA0.
+#define BS_DAC_DATnL_DATA0   (8U)          //!< Bit field size in bits for DAC_DATnL_DATA0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_DATnL_DATA0 field.
+#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DAC_DATnL_DATA0.
+#define BF_DAC_DATnL_DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnL_DATA0), uint8_t) & BM_DAC_DATnL_DATA0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA0 field to a new value.
+#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DAC_DATnH - DAC Data High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_DATnH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_dac_datnh
+{
+    uint8_t U;
+    struct _hw_dac_datnh_bitfields
+    {
+        uint8_t DATA1 : 4;             //!< [3:0]
+        uint8_t RESERVED0 : 4;         //!< [7:4]
+    } B;
+} hw_dac_datnh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_DATnH register
+ */
+//@{
+#define HW_DAC_DATnH_COUNT (16U)
+
+#define HW_DAC_DATnH_ADDR(x, n)  (REGS_DAC_BASE(x) + 0x1U + (0x2U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_DATnH(x, n)       (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
+#define HW_DAC_DATnH_RD(x, n)    (HW_DAC_DATnH(x, n).U)
+#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
+#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) |  (v)))
+#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
+#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_DATnH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATnH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+//@{
+#define BP_DAC_DATnH_DATA1   (0U)          //!< Bit position for DAC_DATnH_DATA1.
+#define BM_DAC_DATnH_DATA1   (0x0FU)       //!< Bit mask for DAC_DATnH_DATA1.
+#define BS_DAC_DATnH_DATA1   (4U)          //!< Bit field size in bits for DAC_DATnH_DATA1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_DATnH_DATA1 field.
+#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
+#endif
+
+//! @brief Format value for bitfield DAC_DATnH_DATA1.
+#define BF_DAC_DATnH_DATA1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnH_DATA1), uint8_t) & BM_DAC_DATnH_DATA1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA1 field to a new value.
+#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_SR - DAC Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+typedef union _hw_dac_sr
+{
+    uint8_t U;
+    struct _hw_dac_sr_bitfields
+    {
+        uint8_t DACBFRPBF : 1;         //!< [0] DAC Buffer Read Pointer Bottom
+                                       //! Position Flag
+        uint8_t DACBFRPTF : 1;         //!< [1] DAC Buffer Read Pointer Top Position
+                                       //! Flag
+        uint8_t DACBFWMF : 1;          //!< [2] DAC Buffer Watermark Flag
+        uint8_t RESERVED0 : 5;         //!< [7:3]
+    } B;
+} hw_dac_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+//@{
+#define HW_DAC_SR_ADDR(x)        (REGS_DAC_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_SR(x)             (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
+#define HW_DAC_SR_RD(x)          (HW_DAC_SR(x).U)
+#define HW_DAC_SR_WR(x, v)       (HW_DAC_SR(x).U = (v))
+#define HW_DAC_SR_SET(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) |  (v)))
+#define HW_DAC_SR_CLR(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
+#define HW_DAC_SR_TOG(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+//@{
+#define BP_DAC_SR_DACBFRPBF  (0U)          //!< Bit position for DAC_SR_DACBFRPBF.
+#define BM_DAC_SR_DACBFRPBF  (0x01U)       //!< Bit mask for DAC_SR_DACBFRPBF.
+#define BS_DAC_SR_DACBFRPBF  (1U)          //!< Bit field size in bits for DAC_SR_DACBFRPBF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_SR_DACBFRPBF field.
+#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
+#endif
+
+//! @brief Format value for bitfield DAC_SR_DACBFRPBF.
+#define BF_DAC_SR_DACBFRPBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPBF), uint8_t) & BM_DAC_SR_DACBFRPBF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFRPBF field to a new value.
+#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer is not zero.
+ * - 1 - The DAC buffer read pointer is zero.
+ */
+//@{
+#define BP_DAC_SR_DACBFRPTF  (1U)          //!< Bit position for DAC_SR_DACBFRPTF.
+#define BM_DAC_SR_DACBFRPTF  (0x02U)       //!< Bit mask for DAC_SR_DACBFRPTF.
+#define BS_DAC_SR_DACBFRPTF  (1U)          //!< Bit field size in bits for DAC_SR_DACBFRPTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_SR_DACBFRPTF field.
+#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
+#endif
+
+//! @brief Format value for bitfield DAC_SR_DACBFRPTF.
+#define BF_DAC_SR_DACBFRPTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPTF), uint8_t) & BM_DAC_SR_DACBFRPTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFRPTF field to a new value.
+#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 1 - The DAC buffer read pointer has reached the watermark level.
+ */
+//@{
+#define BP_DAC_SR_DACBFWMF   (2U)          //!< Bit position for DAC_SR_DACBFWMF.
+#define BM_DAC_SR_DACBFWMF   (0x04U)       //!< Bit mask for DAC_SR_DACBFWMF.
+#define BS_DAC_SR_DACBFWMF   (1U)          //!< Bit field size in bits for DAC_SR_DACBFWMF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_SR_DACBFWMF field.
+#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
+#endif
+
+//! @brief Format value for bitfield DAC_SR_DACBFWMF.
+#define BF_DAC_SR_DACBFWMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFWMF), uint8_t) & BM_DAC_SR_DACBFWMF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFWMF field to a new value.
+#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_C0 - DAC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+typedef union _hw_dac_c0
+{
+    uint8_t U;
+    struct _hw_dac_c0_bitfields
+    {
+        uint8_t DACBBIEN : 1;          //!< [0] DAC Buffer Read Pointer Bottom Flag
+                                       //! Interrupt Enable
+        uint8_t DACBTIEN : 1;          //!< [1] DAC Buffer Read Pointer Top Flag
+                                       //! Interrupt Enable
+        uint8_t DACBWIEN : 1;          //!< [2] DAC Buffer Watermark Interrupt Enable
+        uint8_t LPEN : 1;              //!< [3] DAC Low Power Control
+        uint8_t DACSWTRG : 1;          //!< [4] DAC Software Trigger
+        uint8_t DACTRGSEL : 1;         //!< [5] DAC Trigger Select
+        uint8_t DACRFS : 1;            //!< [6] DAC Reference Select
+        uint8_t DACEN : 1;             //!< [7] DAC Enable
+    } B;
+} hw_dac_c0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+//@{
+#define HW_DAC_C0_ADDR(x)        (REGS_DAC_BASE(x) + 0x21U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_C0(x)             (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
+#define HW_DAC_C0_RD(x)          (HW_DAC_C0(x).U)
+#define HW_DAC_C0_WR(x, v)       (HW_DAC_C0(x).U = (v))
+#define HW_DAC_C0_SET(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) |  (v)))
+#define HW_DAC_C0_CLR(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
+#define HW_DAC_C0_TOG(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACBBIEN   (0U)          //!< Bit position for DAC_C0_DACBBIEN.
+#define BM_DAC_C0_DACBBIEN   (0x01U)       //!< Bit mask for DAC_C0_DACBBIEN.
+#define BS_DAC_C0_DACBBIEN   (1U)          //!< Bit field size in bits for DAC_C0_DACBBIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACBBIEN field.
+#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACBBIEN.
+#define BF_DAC_C0_DACBBIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBBIEN), uint8_t) & BM_DAC_C0_DACBBIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBBIEN field to a new value.
+#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACBTIEN   (1U)          //!< Bit position for DAC_C0_DACBTIEN.
+#define BM_DAC_C0_DACBTIEN   (0x02U)       //!< Bit mask for DAC_C0_DACBTIEN.
+#define BS_DAC_C0_DACBTIEN   (1U)          //!< Bit field size in bits for DAC_C0_DACBTIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACBTIEN field.
+#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACBTIEN.
+#define BF_DAC_C0_DACBTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBTIEN), uint8_t) & BM_DAC_C0_DACBTIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBTIEN field to a new value.
+#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer watermark interrupt is disabled.
+ * - 1 - The DAC buffer watermark interrupt is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACBWIEN   (2U)          //!< Bit position for DAC_C0_DACBWIEN.
+#define BM_DAC_C0_DACBWIEN   (0x04U)       //!< Bit mask for DAC_C0_DACBWIEN.
+#define BS_DAC_C0_DACBWIEN   (1U)          //!< Bit field size in bits for DAC_C0_DACBWIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACBWIEN field.
+#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACBWIEN.
+#define BF_DAC_C0_DACBWIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBWIEN), uint8_t) & BM_DAC_C0_DACBWIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBWIEN field to a new value.
+#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0 - High-Power mode
+ * - 1 - Low-Power mode
+ */
+//@{
+#define BP_DAC_C0_LPEN       (3U)          //!< Bit position for DAC_C0_LPEN.
+#define BM_DAC_C0_LPEN       (0x08U)       //!< Bit mask for DAC_C0_LPEN.
+#define BS_DAC_C0_LPEN       (1U)          //!< Bit field size in bits for DAC_C0_LPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_LPEN field.
+#define BR_DAC_C0_LPEN(x)    (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_LPEN.
+#define BF_DAC_C0_LPEN(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_LPEN), uint8_t) & BM_DAC_C0_LPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPEN field to a new value.
+#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0 - The DAC soft trigger is not valid.
+ * - 1 - The DAC soft trigger is valid.
+ */
+//@{
+#define BP_DAC_C0_DACSWTRG   (4U)          //!< Bit position for DAC_C0_DACSWTRG.
+#define BM_DAC_C0_DACSWTRG   (0x10U)       //!< Bit mask for DAC_C0_DACSWTRG.
+#define BS_DAC_C0_DACSWTRG   (1U)          //!< Bit field size in bits for DAC_C0_DACSWTRG.
+
+//! @brief Format value for bitfield DAC_C0_DACSWTRG.
+#define BF_DAC_C0_DACSWTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACSWTRG), uint8_t) & BM_DAC_C0_DACSWTRG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACSWTRG field to a new value.
+#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0 - The DAC hardware trigger is selected.
+ * - 1 - The DAC software trigger is selected.
+ */
+//@{
+#define BP_DAC_C0_DACTRGSEL  (5U)          //!< Bit position for DAC_C0_DACTRGSEL.
+#define BM_DAC_C0_DACTRGSEL  (0x20U)       //!< Bit mask for DAC_C0_DACTRGSEL.
+#define BS_DAC_C0_DACTRGSEL  (1U)          //!< Bit field size in bits for DAC_C0_DACTRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACTRGSEL field.
+#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACTRGSEL.
+#define BF_DAC_C0_DACTRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACTRGSEL), uint8_t) & BM_DAC_C0_DACTRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACTRGSEL field to a new value.
+#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+//@{
+#define BP_DAC_C0_DACRFS     (6U)          //!< Bit position for DAC_C0_DACRFS.
+#define BM_DAC_C0_DACRFS     (0x40U)       //!< Bit mask for DAC_C0_DACRFS.
+#define BS_DAC_C0_DACRFS     (1U)          //!< Bit field size in bits for DAC_C0_DACRFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACRFS field.
+#define BR_DAC_C0_DACRFS(x)  (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACRFS.
+#define BF_DAC_C0_DACRFS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACRFS), uint8_t) & BM_DAC_C0_DACRFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACRFS field to a new value.
+#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0 - The DAC system is disabled.
+ * - 1 - The DAC system is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACEN      (7U)          //!< Bit position for DAC_C0_DACEN.
+#define BM_DAC_C0_DACEN      (0x80U)       //!< Bit mask for DAC_C0_DACEN.
+#define BS_DAC_C0_DACEN      (1U)          //!< Bit field size in bits for DAC_C0_DACEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACEN field.
+#define BR_DAC_C0_DACEN(x)   (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACEN.
+#define BF_DAC_C0_DACEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACEN), uint8_t) & BM_DAC_C0_DACEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACEN field to a new value.
+#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_C1 - DAC Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+typedef union _hw_dac_c1
+{
+    uint8_t U;
+    struct _hw_dac_c1_bitfields
+    {
+        uint8_t DACBFEN : 1;           //!< [0] DAC Buffer Enable
+        uint8_t DACBFMD : 2;           //!< [2:1] DAC Buffer Work Mode Select
+        uint8_t DACBFWM : 2;           //!< [4:3] DAC Buffer Watermark Select
+        uint8_t RESERVED0 : 2;         //!< [6:5]
+        uint8_t DMAEN : 1;             //!< [7] DMA Enable Select
+    } B;
+} hw_dac_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+//@{
+#define HW_DAC_C1_ADDR(x)        (REGS_DAC_BASE(x) + 0x22U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_C1(x)             (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
+#define HW_DAC_C1_RD(x)          (HW_DAC_C1(x).U)
+#define HW_DAC_C1_WR(x, v)       (HW_DAC_C1(x).U = (v))
+#define HW_DAC_C1_SET(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) |  (v)))
+#define HW_DAC_C1_CLR(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
+#define HW_DAC_C1_TOG(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Buffer read pointer is disabled. The converted data is always the first
+ *     word of the buffer.
+ * - 1 - Buffer read pointer is enabled. The converted data is the word that the
+ *     read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+//@{
+#define BP_DAC_C1_DACBFEN    (0U)          //!< Bit position for DAC_C1_DACBFEN.
+#define BM_DAC_C1_DACBFEN    (0x01U)       //!< Bit mask for DAC_C1_DACBFEN.
+#define BS_DAC_C1_DACBFEN    (1U)          //!< Bit field size in bits for DAC_C1_DACBFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DACBFEN field.
+#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DACBFEN.
+#define BF_DAC_C1_DACBFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFEN), uint8_t) & BM_DAC_C1_DACBFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFEN field to a new value.
+#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 00 - Normal mode
+ * - 01 - Swing mode
+ * - 10 - One-Time Scan mode
+ * - 11 - Reserved
+ */
+//@{
+#define BP_DAC_C1_DACBFMD    (1U)          //!< Bit position for DAC_C1_DACBFMD.
+#define BM_DAC_C1_DACBFMD    (0x06U)       //!< Bit mask for DAC_C1_DACBFMD.
+#define BS_DAC_C1_DACBFMD    (2U)          //!< Bit field size in bits for DAC_C1_DACBFMD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DACBFMD field.
+#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DACBFMD.
+#define BF_DAC_C1_DACBFMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFMD), uint8_t) & BM_DAC_C1_DACBFMD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFMD field to a new value.
+#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 00 - 1 word
+ * - 01 - 2 words
+ * - 10 - 3 words
+ * - 11 - 4 words
+ */
+//@{
+#define BP_DAC_C1_DACBFWM    (3U)          //!< Bit position for DAC_C1_DACBFWM.
+#define BM_DAC_C1_DACBFWM    (0x18U)       //!< Bit mask for DAC_C1_DACBFWM.
+#define BS_DAC_C1_DACBFWM    (2U)          //!< Bit field size in bits for DAC_C1_DACBFWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DACBFWM field.
+#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DACBFWM.
+#define BF_DAC_C1_DACBFWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFWM), uint8_t) & BM_DAC_C1_DACBFWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFWM field to a new value.
+#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
+ *     by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+//@{
+#define BP_DAC_C1_DMAEN      (7U)          //!< Bit position for DAC_C1_DMAEN.
+#define BM_DAC_C1_DMAEN      (0x80U)       //!< Bit mask for DAC_C1_DMAEN.
+#define BS_DAC_C1_DMAEN      (1U)          //!< Bit field size in bits for DAC_C1_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DMAEN field.
+#define BR_DAC_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DMAEN.
+#define BF_DAC_C1_DMAEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DMAEN), uint8_t) & BM_DAC_C1_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_C2 - DAC Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+typedef union _hw_dac_c2
+{
+    uint8_t U;
+    struct _hw_dac_c2_bitfields
+    {
+        uint8_t DACBFUP : 4;           //!< [3:0] DAC Buffer Upper Limit
+        uint8_t DACBFRP : 4;           //!< [7:4] DAC Buffer Read Pointer
+    } B;
+} hw_dac_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+//@{
+#define HW_DAC_C2_ADDR(x)        (REGS_DAC_BASE(x) + 0x23U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_C2(x)             (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
+#define HW_DAC_C2_RD(x)          (HW_DAC_C2(x).U)
+#define HW_DAC_C2_WR(x, v)       (HW_DAC_C2(x).U = (v))
+#define HW_DAC_C2_SET(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) |  (v)))
+#define HW_DAC_C2_CLR(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
+#define HW_DAC_C2_TOG(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+//@{
+#define BP_DAC_C2_DACBFUP    (0U)          //!< Bit position for DAC_C2_DACBFUP.
+#define BM_DAC_C2_DACBFUP    (0x0FU)       //!< Bit mask for DAC_C2_DACBFUP.
+#define BS_DAC_C2_DACBFUP    (4U)          //!< Bit field size in bits for DAC_C2_DACBFUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C2_DACBFUP field.
+#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
+#endif
+
+//! @brief Format value for bitfield DAC_C2_DACBFUP.
+#define BF_DAC_C2_DACBFUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFUP), uint8_t) & BM_DAC_C2_DACBFUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFUP field to a new value.
+#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+//@{
+#define BP_DAC_C2_DACBFRP    (4U)          //!< Bit position for DAC_C2_DACBFRP.
+#define BM_DAC_C2_DACBFRP    (0xF0U)       //!< Bit mask for DAC_C2_DACBFRP.
+#define BS_DAC_C2_DACBFRP    (4U)          //!< Bit field size in bits for DAC_C2_DACBFRP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C2_DACBFRP field.
+#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
+#endif
+
+//! @brief Format value for bitfield DAC_C2_DACBFRP.
+#define BF_DAC_C2_DACBFRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFRP), uint8_t) & BM_DAC_C2_DACBFRP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFRP field to a new value.
+#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_dac_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All DAC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_dac
+{
+    struct {
+        __IO hw_dac_datnl_t DATnL;         //!< [0x0] DAC Data Low Register
+        __IO hw_dac_datnh_t DATnH;         //!< [0x1] DAC Data High Register
+    } DAT[16];
+    __IO hw_dac_sr_t SR;                   //!< [0x20] DAC Status Register
+    __IO hw_dac_c0_t C0;                   //!< [0x21] DAC Control Register
+    __IO hw_dac_c1_t C1;                   //!< [0x22] DAC Control Register 1
+    __IO hw_dac_c2_t C2;                   //!< [0x23] DAC Control Register 2
+} hw_dac_t;
+#pragma pack()
+
+//! @brief Macro to access all DAC registers.
+//! @param x DAC instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_DAC(0)</code>.
+#define HW_DAC(x)      (*(hw_dac_t *) REGS_DAC_BASE(x))
+#endif
+
+#endif // __HW_DAC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h
new file mode 100644
index 0000000000..b5d39fd4e0
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h
@@ -0,0 +1,5973 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_DMA_REGISTERS_H__
+#define __HW_DMA_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - HW_DMA_CR - Control Register
+ * - HW_DMA_ES - Error Status Register
+ * - HW_DMA_ERQ - Enable Request Register
+ * - HW_DMA_EEI - Enable Error Interrupt Register
+ * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
+ * - HW_DMA_SEEI - Set Enable Error Interrupt Register
+ * - HW_DMA_CERQ - Clear Enable Request Register
+ * - HW_DMA_SERQ - Set Enable Request Register
+ * - HW_DMA_CDNE - Clear DONE Status Bit Register
+ * - HW_DMA_SSRT - Set START Bit Register
+ * - HW_DMA_CERR - Clear Error Register
+ * - HW_DMA_CINT - Clear Interrupt Request Register
+ * - HW_DMA_INT - Interrupt Request Register
+ * - HW_DMA_ERR - Error Register
+ * - HW_DMA_HRS - Hardware Request Status Register
+ * - HW_DMA_DCHPRIn - Channel n Priority Register
+ * - HW_DMA_TCDn_SADDR - TCD Source Address
+ * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
+ * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
+ * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
+ * - HW_DMA_TCDn_DADDR - TCD Destination Address
+ * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
+ * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - HW_DMA_TCDn_CSR - TCD Control and Status
+ * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ *
+ * - hw_dma_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_DMA_BASE
+#define HW_DMA_INSTANCE_COUNT (1U) //!< Number of instances of the DMA module.
+#define HW_DMA0 (0U) //!< Instance number for DMA.
+#define REGS_DMA0_BASE (0x40008000U) //!< Base address for DMA.
+
+//! @brief Table of base addresses for DMA instances.
+static const uint32_t __g_regs_DMA_base_addresses[] = {
+        REGS_DMA0_BASE,
+    };
+
+//! @brief Get the base address of DMA by instance number.
+//! @param x DMA instance number, from 0 through 0.
+#define REGS_DMA_BASE(x) (__g_regs_DMA_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of DMA.
+#define REGS_DMA_INSTANCE(b) ((b) == REGS_DMA0_BASE ? HW_DMA0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CR - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+typedef union _hw_dma_cr
+{
+    uint32_t U;
+    struct _hw_dma_cr_bitfields
+    {
+        uint32_t RESERVED0 : 1;        //!< [0] Reserved.
+        uint32_t EDBG : 1;             //!< [1] Enable Debug
+        uint32_t ERCA : 1;             //!< [2] Enable Round Robin Channel Arbitration
+        uint32_t RESERVED1 : 1;        //!< [3] Reserved.
+        uint32_t HOE : 1;              //!< [4] Halt On Error
+        uint32_t HALT : 1;             //!< [5] Halt DMA Operations
+        uint32_t CLM : 1;              //!< [6] Continuous Link Mode
+        uint32_t EMLM : 1;             //!< [7] Enable Minor Loop Mapping
+        uint32_t RESERVED2 : 8;        //!< [15:8]
+        uint32_t ECX : 1;              //!< [16] Error Cancel Transfer
+        uint32_t CX : 1;               //!< [17] Cancel Transfer
+        uint32_t RESERVED3 : 14;       //!< [31:18]
+    } B;
+} hw_dma_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+//@{
+#define HW_DMA_CR_ADDR(x)        (REGS_DMA_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CR(x)             (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
+#define HW_DMA_CR_RD(x)          (HW_DMA_CR(x).U)
+#define HW_DMA_CR_WR(x, v)       (HW_DMA_CR(x).U = (v))
+#define HW_DMA_CR_SET(x, v)      (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) |  (v)))
+#define HW_DMA_CR_CLR(x, v)      (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
+#define HW_DMA_CR_TOG(x, v)      (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0 - When in debug mode, the DMA continues to operate.
+ * - 1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+//@{
+#define BP_DMA_CR_EDBG       (1U)          //!< Bit position for DMA_CR_EDBG.
+#define BM_DMA_CR_EDBG       (0x00000002U) //!< Bit mask for DMA_CR_EDBG.
+#define BS_DMA_CR_EDBG       (1U)          //!< Bit field size in bits for DMA_CR_EDBG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_EDBG field.
+#define BR_DMA_CR_EDBG(x)    (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_EDBG.
+#define BF_DMA_CR_EDBG(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EDBG), uint32_t) & BM_DMA_CR_EDBG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EDBG field to a new value.
+#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0 - Fixed priority arbitration is used for channel selection .
+ * - 1 - Round robin arbitration is used for channel selection .
+ */
+//@{
+#define BP_DMA_CR_ERCA       (2U)          //!< Bit position for DMA_CR_ERCA.
+#define BM_DMA_CR_ERCA       (0x00000004U) //!< Bit mask for DMA_CR_ERCA.
+#define BS_DMA_CR_ERCA       (1U)          //!< Bit field size in bits for DMA_CR_ERCA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_ERCA field.
+#define BR_DMA_CR_ERCA(x)    (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_ERCA.
+#define BF_DMA_CR_ERCA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ERCA), uint32_t) & BM_DMA_CR_ERCA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERCA field to a new value.
+#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+//@{
+#define BP_DMA_CR_HOE        (4U)          //!< Bit position for DMA_CR_HOE.
+#define BM_DMA_CR_HOE        (0x00000010U) //!< Bit mask for DMA_CR_HOE.
+#define BS_DMA_CR_HOE        (1U)          //!< Bit field size in bits for DMA_CR_HOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_HOE field.
+#define BR_DMA_CR_HOE(x)     (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_HOE.
+#define BF_DMA_CR_HOE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HOE), uint32_t) & BM_DMA_CR_HOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOE field to a new value.
+#define BW_DMA_CR_HOE(x, v)  (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Stall the start of any new channels. Executing channels are allowed to
+ *     complete. Channel execution resumes when this bit is cleared.
+ */
+//@{
+#define BP_DMA_CR_HALT       (5U)          //!< Bit position for DMA_CR_HALT.
+#define BM_DMA_CR_HALT       (0x00000020U) //!< Bit mask for DMA_CR_HALT.
+#define BS_DMA_CR_HALT       (1U)          //!< Bit field size in bits for DMA_CR_HALT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_HALT field.
+#define BR_DMA_CR_HALT(x)    (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_HALT.
+#define BF_DMA_CR_HALT(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HALT), uint32_t) & BM_DMA_CR_HALT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HALT field to a new value.
+#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor loop
+ *     offsets and restarts the next minor loop.
+ */
+//@{
+#define BP_DMA_CR_CLM        (6U)          //!< Bit position for DMA_CR_CLM.
+#define BM_DMA_CR_CLM        (0x00000040U) //!< Bit mask for DMA_CR_CLM.
+#define BS_DMA_CR_CLM        (1U)          //!< Bit field size in bits for DMA_CR_CLM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_CLM field.
+#define BR_DMA_CR_CLM(x)     (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_CLM.
+#define BF_DMA_CR_CLM(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CLM), uint32_t) & BM_DMA_CR_CLM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM field to a new value.
+#define BW_DMA_CR_CLM(x, v)  (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the destination
+ *     address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+//@{
+#define BP_DMA_CR_EMLM       (7U)          //!< Bit position for DMA_CR_EMLM.
+#define BM_DMA_CR_EMLM       (0x00000080U) //!< Bit mask for DMA_CR_EMLM.
+#define BS_DMA_CR_EMLM       (1U)          //!< Bit field size in bits for DMA_CR_EMLM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_EMLM field.
+#define BR_DMA_CR_EMLM(x)    (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_EMLM.
+#define BF_DMA_CR_EMLM(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EMLM), uint32_t) & BM_DMA_CR_EMLM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EMLM field to a new value.
+#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus updating
+ *     the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+//@{
+#define BP_DMA_CR_ECX        (16U)         //!< Bit position for DMA_CR_ECX.
+#define BM_DMA_CR_ECX        (0x00010000U) //!< Bit mask for DMA_CR_ECX.
+#define BS_DMA_CR_ECX        (1U)          //!< Bit field size in bits for DMA_CR_ECX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_ECX field.
+#define BR_DMA_CR_ECX(x)     (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_ECX.
+#define BF_DMA_CR_ECX(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ECX), uint32_t) & BM_DMA_CR_ECX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ECX field to a new value.
+#define BW_DMA_CR_ECX(x, v)  (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+//@{
+#define BP_DMA_CR_CX         (17U)         //!< Bit position for DMA_CR_CX.
+#define BM_DMA_CR_CX         (0x00020000U) //!< Bit mask for DMA_CR_CX.
+#define BS_DMA_CR_CX         (1U)          //!< Bit field size in bits for DMA_CR_CX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_CX field.
+#define BR_DMA_CR_CX(x)      (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_CX.
+#define BF_DMA_CR_CX(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CX), uint32_t) & BM_DMA_CR_CX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CX field to a new value.
+#define BW_DMA_CR_CX(x, v)   (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_ES - Error Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+typedef union _hw_dma_es
+{
+    uint32_t U;
+    struct _hw_dma_es_bitfields
+    {
+        uint32_t DBE : 1;              //!< [0] Destination Bus Error
+        uint32_t SBE : 1;              //!< [1] Source Bus Error
+        uint32_t SGE : 1;              //!< [2] Scatter/Gather Configuration Error
+        uint32_t NCE : 1;              //!< [3] NBYTES/CITER Configuration Error
+        uint32_t DOE : 1;              //!< [4] Destination Offset Error
+        uint32_t DAE : 1;              //!< [5] Destination Address Error
+        uint32_t SOE : 1;              //!< [6] Source Offset Error
+        uint32_t SAE : 1;              //!< [7] Source Address Error
+        uint32_t ERRCHN : 4;           //!< [11:8] Error Channel Number or Canceled
+                                       //! Channel Number
+        uint32_t RESERVED0 : 2;        //!< [13:12]
+        uint32_t CPE : 1;              //!< [14] Channel Priority Error
+        uint32_t RESERVED1 : 1;        //!< [15]
+        uint32_t ECX : 1;              //!< [16] Transfer Canceled
+        uint32_t RESERVED2 : 14;       //!< [30:17]
+        uint32_t VLD : 1;              //!< [31]
+    } B;
+} hw_dma_es_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+//@{
+#define HW_DMA_ES_ADDR(x)        (REGS_DMA_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_ES(x)             (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
+#define HW_DMA_ES_RD(x)          (HW_DMA_ES(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0 - No destination bus error
+ * - 1 - The last recorded error was a bus error on a destination write
+ */
+//@{
+#define BP_DMA_ES_DBE        (0U)          //!< Bit position for DMA_ES_DBE.
+#define BM_DMA_ES_DBE        (0x00000001U) //!< Bit mask for DMA_ES_DBE.
+#define BS_DMA_ES_DBE        (1U)          //!< Bit field size in bits for DMA_ES_DBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_DBE field.
+#define BR_DMA_ES_DBE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0 - No source bus error
+ * - 1 - The last recorded error was a bus error on a source read
+ */
+//@{
+#define BP_DMA_ES_SBE        (1U)          //!< Bit position for DMA_ES_SBE.
+#define BM_DMA_ES_SBE        (0x00000002U) //!< Bit mask for DMA_ES_SBE.
+#define BS_DMA_ES_SBE        (1U)          //!< Bit field size in bits for DMA_ES_SBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SBE field.
+#define BR_DMA_ES_SBE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0 - No scatter/gather configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
+ *     operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+//@{
+#define BP_DMA_ES_SGE        (2U)          //!< Bit position for DMA_ES_SGE.
+#define BM_DMA_ES_SGE        (0x00000004U) //!< Bit mask for DMA_ES_SGE.
+#define BS_DMA_ES_SGE        (1U)          //!< Bit field size in bits for DMA_ES_SGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SGE field.
+#define BR_DMA_ES_SGE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0 - No NBYTES/CITER configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+//@{
+#define BP_DMA_ES_NCE        (3U)          //!< Bit position for DMA_ES_NCE.
+#define BM_DMA_ES_NCE        (0x00000008U) //!< Bit mask for DMA_ES_NCE.
+#define BS_DMA_ES_NCE        (1U)          //!< Bit field size in bits for DMA_ES_NCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_NCE field.
+#define BR_DMA_ES_NCE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0 - No destination offset configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+//@{
+#define BP_DMA_ES_DOE        (4U)          //!< Bit position for DMA_ES_DOE.
+#define BM_DMA_ES_DOE        (0x00000010U) //!< Bit mask for DMA_ES_DOE.
+#define BS_DMA_ES_DOE        (1U)          //!< Bit field size in bits for DMA_ES_DOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_DOE field.
+#define BR_DMA_ES_DOE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0 - No destination address configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+//@{
+#define BP_DMA_ES_DAE        (5U)          //!< Bit position for DMA_ES_DAE.
+#define BM_DMA_ES_DAE        (0x00000020U) //!< Bit mask for DMA_ES_DAE.
+#define BS_DMA_ES_DAE        (1U)          //!< Bit field size in bits for DMA_ES_DAE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_DAE field.
+#define BR_DMA_ES_DAE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0 - No source offset configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+//@{
+#define BP_DMA_ES_SOE        (6U)          //!< Bit position for DMA_ES_SOE.
+#define BM_DMA_ES_SOE        (0x00000040U) //!< Bit mask for DMA_ES_SOE.
+#define BS_DMA_ES_SOE        (1U)          //!< Bit field size in bits for DMA_ES_SOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SOE field.
+#define BR_DMA_ES_SOE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0 - No source address configuration error.
+ * - 1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+//@{
+#define BP_DMA_ES_SAE        (7U)          //!< Bit position for DMA_ES_SAE.
+#define BM_DMA_ES_SAE        (0x00000080U) //!< Bit mask for DMA_ES_SAE.
+#define BS_DMA_ES_SAE        (1U)          //!< Bit field size in bits for DMA_ES_SAE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SAE field.
+#define BR_DMA_ES_SAE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+//@{
+#define BP_DMA_ES_ERRCHN     (8U)          //!< Bit position for DMA_ES_ERRCHN.
+#define BM_DMA_ES_ERRCHN     (0x00000F00U) //!< Bit mask for DMA_ES_ERRCHN.
+#define BS_DMA_ES_ERRCHN     (4U)          //!< Bit field size in bits for DMA_ES_ERRCHN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_ERRCHN field.
+#define BR_DMA_ES_ERRCHN(x)  (HW_DMA_ES(x).B.ERRCHN)
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0 - No channel priority error
+ * - 1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+//@{
+#define BP_DMA_ES_CPE        (14U)         //!< Bit position for DMA_ES_CPE.
+#define BM_DMA_ES_CPE        (0x00004000U) //!< Bit mask for DMA_ES_CPE.
+#define BS_DMA_ES_CPE        (1U)          //!< Bit field size in bits for DMA_ES_CPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_CPE field.
+#define BR_DMA_ES_CPE(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0 - No canceled transfers
+ * - 1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+//@{
+#define BP_DMA_ES_ECX        (16U)         //!< Bit position for DMA_ES_ECX.
+#define BM_DMA_ES_ECX        (0x00010000U) //!< Bit mask for DMA_ES_ECX.
+#define BS_DMA_ES_ECX        (1U)          //!< Bit field size in bits for DMA_ES_ECX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_ECX field.
+#define BR_DMA_ES_ECX(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0 - No ERR bits are set
+ * - 1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+//@{
+#define BP_DMA_ES_VLD        (31U)         //!< Bit position for DMA_ES_VLD.
+#define BM_DMA_ES_VLD        (0x80000000U) //!< Bit mask for DMA_ES_VLD.
+#define BS_DMA_ES_VLD        (1U)          //!< Bit field size in bits for DMA_ES_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_VLD field.
+#define BR_DMA_ES_VLD(x)     (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_ERQ - Enable Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+typedef union _hw_dma_erq
+{
+    uint32_t U;
+    struct _hw_dma_erq_bitfields
+    {
+        uint32_t ERQ0 : 1;             //!< [0] Enable DMA Request 0
+        uint32_t ERQ1 : 1;             //!< [1] Enable DMA Request 1
+        uint32_t ERQ2 : 1;             //!< [2] Enable DMA Request 2
+        uint32_t ERQ3 : 1;             //!< [3] Enable DMA Request 3
+        uint32_t ERQ4 : 1;             //!< [4] Enable DMA Request 4
+        uint32_t ERQ5 : 1;             //!< [5] Enable DMA Request 5
+        uint32_t ERQ6 : 1;             //!< [6] Enable DMA Request 6
+        uint32_t ERQ7 : 1;             //!< [7] Enable DMA Request 7
+        uint32_t ERQ8 : 1;             //!< [8] Enable DMA Request 8
+        uint32_t ERQ9 : 1;             //!< [9] Enable DMA Request 9
+        uint32_t ERQ10 : 1;            //!< [10] Enable DMA Request 10
+        uint32_t ERQ11 : 1;            //!< [11] Enable DMA Request 11
+        uint32_t ERQ12 : 1;            //!< [12] Enable DMA Request 12
+        uint32_t ERQ13 : 1;            //!< [13] Enable DMA Request 13
+        uint32_t ERQ14 : 1;            //!< [14] Enable DMA Request 14
+        uint32_t ERQ15 : 1;            //!< [15] Enable DMA Request 15
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_dma_erq_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+//@{
+#define HW_DMA_ERQ_ADDR(x)       (REGS_DMA_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_ERQ(x)            (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
+#define HW_DMA_ERQ_RD(x)         (HW_DMA_ERQ(x).U)
+#define HW_DMA_ERQ_WR(x, v)      (HW_DMA_ERQ(x).U = (v))
+#define HW_DMA_ERQ_SET(x, v)     (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) |  (v)))
+#define HW_DMA_ERQ_CLR(x, v)     (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
+#define HW_DMA_ERQ_TOG(x, v)     (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ0      (0U)          //!< Bit position for DMA_ERQ_ERQ0.
+#define BM_DMA_ERQ_ERQ0      (0x00000001U) //!< Bit mask for DMA_ERQ_ERQ0.
+#define BS_DMA_ERQ_ERQ0      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ0 field.
+#define BR_DMA_ERQ_ERQ0(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ0.
+#define BF_DMA_ERQ_ERQ0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ0), uint32_t) & BM_DMA_ERQ_ERQ0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ0 field to a new value.
+#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ1      (1U)          //!< Bit position for DMA_ERQ_ERQ1.
+#define BM_DMA_ERQ_ERQ1      (0x00000002U) //!< Bit mask for DMA_ERQ_ERQ1.
+#define BS_DMA_ERQ_ERQ1      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ1 field.
+#define BR_DMA_ERQ_ERQ1(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ1.
+#define BF_DMA_ERQ_ERQ1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ1), uint32_t) & BM_DMA_ERQ_ERQ1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ1 field to a new value.
+#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ2      (2U)          //!< Bit position for DMA_ERQ_ERQ2.
+#define BM_DMA_ERQ_ERQ2      (0x00000004U) //!< Bit mask for DMA_ERQ_ERQ2.
+#define BS_DMA_ERQ_ERQ2      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ2 field.
+#define BR_DMA_ERQ_ERQ2(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ2.
+#define BF_DMA_ERQ_ERQ2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ2), uint32_t) & BM_DMA_ERQ_ERQ2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ2 field to a new value.
+#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ3      (3U)          //!< Bit position for DMA_ERQ_ERQ3.
+#define BM_DMA_ERQ_ERQ3      (0x00000008U) //!< Bit mask for DMA_ERQ_ERQ3.
+#define BS_DMA_ERQ_ERQ3      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ3 field.
+#define BR_DMA_ERQ_ERQ3(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ3.
+#define BF_DMA_ERQ_ERQ3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ3), uint32_t) & BM_DMA_ERQ_ERQ3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ3 field to a new value.
+#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ4      (4U)          //!< Bit position for DMA_ERQ_ERQ4.
+#define BM_DMA_ERQ_ERQ4      (0x00000010U) //!< Bit mask for DMA_ERQ_ERQ4.
+#define BS_DMA_ERQ_ERQ4      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ4 field.
+#define BR_DMA_ERQ_ERQ4(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ4.
+#define BF_DMA_ERQ_ERQ4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ4), uint32_t) & BM_DMA_ERQ_ERQ4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ4 field to a new value.
+#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ5      (5U)          //!< Bit position for DMA_ERQ_ERQ5.
+#define BM_DMA_ERQ_ERQ5      (0x00000020U) //!< Bit mask for DMA_ERQ_ERQ5.
+#define BS_DMA_ERQ_ERQ5      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ5 field.
+#define BR_DMA_ERQ_ERQ5(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ5.
+#define BF_DMA_ERQ_ERQ5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ5), uint32_t) & BM_DMA_ERQ_ERQ5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ5 field to a new value.
+#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ6      (6U)          //!< Bit position for DMA_ERQ_ERQ6.
+#define BM_DMA_ERQ_ERQ6      (0x00000040U) //!< Bit mask for DMA_ERQ_ERQ6.
+#define BS_DMA_ERQ_ERQ6      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ6 field.
+#define BR_DMA_ERQ_ERQ6(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ6.
+#define BF_DMA_ERQ_ERQ6(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ6), uint32_t) & BM_DMA_ERQ_ERQ6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ6 field to a new value.
+#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ7      (7U)          //!< Bit position for DMA_ERQ_ERQ7.
+#define BM_DMA_ERQ_ERQ7      (0x00000080U) //!< Bit mask for DMA_ERQ_ERQ7.
+#define BS_DMA_ERQ_ERQ7      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ7 field.
+#define BR_DMA_ERQ_ERQ7(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ7.
+#define BF_DMA_ERQ_ERQ7(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ7), uint32_t) & BM_DMA_ERQ_ERQ7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ7 field to a new value.
+#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ8      (8U)          //!< Bit position for DMA_ERQ_ERQ8.
+#define BM_DMA_ERQ_ERQ8      (0x00000100U) //!< Bit mask for DMA_ERQ_ERQ8.
+#define BS_DMA_ERQ_ERQ8      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ8 field.
+#define BR_DMA_ERQ_ERQ8(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ8.
+#define BF_DMA_ERQ_ERQ8(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ8), uint32_t) & BM_DMA_ERQ_ERQ8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ8 field to a new value.
+#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ9      (9U)          //!< Bit position for DMA_ERQ_ERQ9.
+#define BM_DMA_ERQ_ERQ9      (0x00000200U) //!< Bit mask for DMA_ERQ_ERQ9.
+#define BS_DMA_ERQ_ERQ9      (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ9 field.
+#define BR_DMA_ERQ_ERQ9(x)   (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ9.
+#define BF_DMA_ERQ_ERQ9(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ9), uint32_t) & BM_DMA_ERQ_ERQ9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ9 field to a new value.
+#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ10     (10U)         //!< Bit position for DMA_ERQ_ERQ10.
+#define BM_DMA_ERQ_ERQ10     (0x00000400U) //!< Bit mask for DMA_ERQ_ERQ10.
+#define BS_DMA_ERQ_ERQ10     (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ10 field.
+#define BR_DMA_ERQ_ERQ10(x)  (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ10.
+#define BF_DMA_ERQ_ERQ10(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ10), uint32_t) & BM_DMA_ERQ_ERQ10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ10 field to a new value.
+#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ11     (11U)         //!< Bit position for DMA_ERQ_ERQ11.
+#define BM_DMA_ERQ_ERQ11     (0x00000800U) //!< Bit mask for DMA_ERQ_ERQ11.
+#define BS_DMA_ERQ_ERQ11     (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ11 field.
+#define BR_DMA_ERQ_ERQ11(x)  (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ11.
+#define BF_DMA_ERQ_ERQ11(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ11), uint32_t) & BM_DMA_ERQ_ERQ11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ11 field to a new value.
+#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ12     (12U)         //!< Bit position for DMA_ERQ_ERQ12.
+#define BM_DMA_ERQ_ERQ12     (0x00001000U) //!< Bit mask for DMA_ERQ_ERQ12.
+#define BS_DMA_ERQ_ERQ12     (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ12 field.
+#define BR_DMA_ERQ_ERQ12(x)  (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ12.
+#define BF_DMA_ERQ_ERQ12(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ12), uint32_t) & BM_DMA_ERQ_ERQ12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ12 field to a new value.
+#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ13     (13U)         //!< Bit position for DMA_ERQ_ERQ13.
+#define BM_DMA_ERQ_ERQ13     (0x00002000U) //!< Bit mask for DMA_ERQ_ERQ13.
+#define BS_DMA_ERQ_ERQ13     (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ13 field.
+#define BR_DMA_ERQ_ERQ13(x)  (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ13.
+#define BF_DMA_ERQ_ERQ13(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ13), uint32_t) & BM_DMA_ERQ_ERQ13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ13 field to a new value.
+#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ14     (14U)         //!< Bit position for DMA_ERQ_ERQ14.
+#define BM_DMA_ERQ_ERQ14     (0x00004000U) //!< Bit mask for DMA_ERQ_ERQ14.
+#define BS_DMA_ERQ_ERQ14     (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ14 field.
+#define BR_DMA_ERQ_ERQ14(x)  (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ14.
+#define BF_DMA_ERQ_ERQ14(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ14), uint32_t) & BM_DMA_ERQ_ERQ14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ14 field to a new value.
+#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ15     (15U)         //!< Bit position for DMA_ERQ_ERQ15.
+#define BM_DMA_ERQ_ERQ15     (0x00008000U) //!< Bit mask for DMA_ERQ_ERQ15.
+#define BS_DMA_ERQ_ERQ15     (1U)          //!< Bit field size in bits for DMA_ERQ_ERQ15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ15 field.
+#define BR_DMA_ERQ_ERQ15(x)  (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ15.
+#define BF_DMA_ERQ_ERQ15(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ15), uint32_t) & BM_DMA_ERQ_ERQ15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ15 field to a new value.
+#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_EEI - Enable Error Interrupt Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+typedef union _hw_dma_eei
+{
+    uint32_t U;
+    struct _hw_dma_eei_bitfields
+    {
+        uint32_t EEI0 : 1;             //!< [0] Enable Error Interrupt 0
+        uint32_t EEI1 : 1;             //!< [1] Enable Error Interrupt 1
+        uint32_t EEI2 : 1;             //!< [2] Enable Error Interrupt 2
+        uint32_t EEI3 : 1;             //!< [3] Enable Error Interrupt 3
+        uint32_t EEI4 : 1;             //!< [4] Enable Error Interrupt 4
+        uint32_t EEI5 : 1;             //!< [5] Enable Error Interrupt 5
+        uint32_t EEI6 : 1;             //!< [6] Enable Error Interrupt 6
+        uint32_t EEI7 : 1;             //!< [7] Enable Error Interrupt 7
+        uint32_t EEI8 : 1;             //!< [8] Enable Error Interrupt 8
+        uint32_t EEI9 : 1;             //!< [9] Enable Error Interrupt 9
+        uint32_t EEI10 : 1;            //!< [10] Enable Error Interrupt 10
+        uint32_t EEI11 : 1;            //!< [11] Enable Error Interrupt 11
+        uint32_t EEI12 : 1;            //!< [12] Enable Error Interrupt 12
+        uint32_t EEI13 : 1;            //!< [13] Enable Error Interrupt 13
+        uint32_t EEI14 : 1;            //!< [14] Enable Error Interrupt 14
+        uint32_t EEI15 : 1;            //!< [15] Enable Error Interrupt 15
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_dma_eei_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+//@{
+#define HW_DMA_EEI_ADDR(x)       (REGS_DMA_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_EEI(x)            (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
+#define HW_DMA_EEI_RD(x)         (HW_DMA_EEI(x).U)
+#define HW_DMA_EEI_WR(x, v)      (HW_DMA_EEI(x).U = (v))
+#define HW_DMA_EEI_SET(x, v)     (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) |  (v)))
+#define HW_DMA_EEI_CLR(x, v)     (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
+#define HW_DMA_EEI_TOG(x, v)     (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI0      (0U)          //!< Bit position for DMA_EEI_EEI0.
+#define BM_DMA_EEI_EEI0      (0x00000001U) //!< Bit mask for DMA_EEI_EEI0.
+#define BS_DMA_EEI_EEI0      (1U)          //!< Bit field size in bits for DMA_EEI_EEI0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI0 field.
+#define BR_DMA_EEI_EEI0(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI0.
+#define BF_DMA_EEI_EEI0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI0), uint32_t) & BM_DMA_EEI_EEI0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI0 field to a new value.
+#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI1      (1U)          //!< Bit position for DMA_EEI_EEI1.
+#define BM_DMA_EEI_EEI1      (0x00000002U) //!< Bit mask for DMA_EEI_EEI1.
+#define BS_DMA_EEI_EEI1      (1U)          //!< Bit field size in bits for DMA_EEI_EEI1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI1 field.
+#define BR_DMA_EEI_EEI1(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI1.
+#define BF_DMA_EEI_EEI1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI1), uint32_t) & BM_DMA_EEI_EEI1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI1 field to a new value.
+#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI2      (2U)          //!< Bit position for DMA_EEI_EEI2.
+#define BM_DMA_EEI_EEI2      (0x00000004U) //!< Bit mask for DMA_EEI_EEI2.
+#define BS_DMA_EEI_EEI2      (1U)          //!< Bit field size in bits for DMA_EEI_EEI2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI2 field.
+#define BR_DMA_EEI_EEI2(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI2.
+#define BF_DMA_EEI_EEI2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI2), uint32_t) & BM_DMA_EEI_EEI2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI2 field to a new value.
+#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI3      (3U)          //!< Bit position for DMA_EEI_EEI3.
+#define BM_DMA_EEI_EEI3      (0x00000008U) //!< Bit mask for DMA_EEI_EEI3.
+#define BS_DMA_EEI_EEI3      (1U)          //!< Bit field size in bits for DMA_EEI_EEI3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI3 field.
+#define BR_DMA_EEI_EEI3(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI3.
+#define BF_DMA_EEI_EEI3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI3), uint32_t) & BM_DMA_EEI_EEI3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI3 field to a new value.
+#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI4      (4U)          //!< Bit position for DMA_EEI_EEI4.
+#define BM_DMA_EEI_EEI4      (0x00000010U) //!< Bit mask for DMA_EEI_EEI4.
+#define BS_DMA_EEI_EEI4      (1U)          //!< Bit field size in bits for DMA_EEI_EEI4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI4 field.
+#define BR_DMA_EEI_EEI4(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI4.
+#define BF_DMA_EEI_EEI4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI4), uint32_t) & BM_DMA_EEI_EEI4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI4 field to a new value.
+#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI5      (5U)          //!< Bit position for DMA_EEI_EEI5.
+#define BM_DMA_EEI_EEI5      (0x00000020U) //!< Bit mask for DMA_EEI_EEI5.
+#define BS_DMA_EEI_EEI5      (1U)          //!< Bit field size in bits for DMA_EEI_EEI5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI5 field.
+#define BR_DMA_EEI_EEI5(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI5.
+#define BF_DMA_EEI_EEI5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI5), uint32_t) & BM_DMA_EEI_EEI5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI5 field to a new value.
+#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI6      (6U)          //!< Bit position for DMA_EEI_EEI6.
+#define BM_DMA_EEI_EEI6      (0x00000040U) //!< Bit mask for DMA_EEI_EEI6.
+#define BS_DMA_EEI_EEI6      (1U)          //!< Bit field size in bits for DMA_EEI_EEI6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI6 field.
+#define BR_DMA_EEI_EEI6(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI6.
+#define BF_DMA_EEI_EEI6(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI6), uint32_t) & BM_DMA_EEI_EEI6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI6 field to a new value.
+#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI7      (7U)          //!< Bit position for DMA_EEI_EEI7.
+#define BM_DMA_EEI_EEI7      (0x00000080U) //!< Bit mask for DMA_EEI_EEI7.
+#define BS_DMA_EEI_EEI7      (1U)          //!< Bit field size in bits for DMA_EEI_EEI7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI7 field.
+#define BR_DMA_EEI_EEI7(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI7.
+#define BF_DMA_EEI_EEI7(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI7), uint32_t) & BM_DMA_EEI_EEI7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI7 field to a new value.
+#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI8      (8U)          //!< Bit position for DMA_EEI_EEI8.
+#define BM_DMA_EEI_EEI8      (0x00000100U) //!< Bit mask for DMA_EEI_EEI8.
+#define BS_DMA_EEI_EEI8      (1U)          //!< Bit field size in bits for DMA_EEI_EEI8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI8 field.
+#define BR_DMA_EEI_EEI8(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI8.
+#define BF_DMA_EEI_EEI8(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI8), uint32_t) & BM_DMA_EEI_EEI8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI8 field to a new value.
+#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI9      (9U)          //!< Bit position for DMA_EEI_EEI9.
+#define BM_DMA_EEI_EEI9      (0x00000200U) //!< Bit mask for DMA_EEI_EEI9.
+#define BS_DMA_EEI_EEI9      (1U)          //!< Bit field size in bits for DMA_EEI_EEI9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI9 field.
+#define BR_DMA_EEI_EEI9(x)   (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI9.
+#define BF_DMA_EEI_EEI9(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI9), uint32_t) & BM_DMA_EEI_EEI9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI9 field to a new value.
+#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI10     (10U)         //!< Bit position for DMA_EEI_EEI10.
+#define BM_DMA_EEI_EEI10     (0x00000400U) //!< Bit mask for DMA_EEI_EEI10.
+#define BS_DMA_EEI_EEI10     (1U)          //!< Bit field size in bits for DMA_EEI_EEI10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI10 field.
+#define BR_DMA_EEI_EEI10(x)  (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI10.
+#define BF_DMA_EEI_EEI10(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI10), uint32_t) & BM_DMA_EEI_EEI10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI10 field to a new value.
+#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI11     (11U)         //!< Bit position for DMA_EEI_EEI11.
+#define BM_DMA_EEI_EEI11     (0x00000800U) //!< Bit mask for DMA_EEI_EEI11.
+#define BS_DMA_EEI_EEI11     (1U)          //!< Bit field size in bits for DMA_EEI_EEI11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI11 field.
+#define BR_DMA_EEI_EEI11(x)  (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI11.
+#define BF_DMA_EEI_EEI11(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI11), uint32_t) & BM_DMA_EEI_EEI11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI11 field to a new value.
+#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI12     (12U)         //!< Bit position for DMA_EEI_EEI12.
+#define BM_DMA_EEI_EEI12     (0x00001000U) //!< Bit mask for DMA_EEI_EEI12.
+#define BS_DMA_EEI_EEI12     (1U)          //!< Bit field size in bits for DMA_EEI_EEI12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI12 field.
+#define BR_DMA_EEI_EEI12(x)  (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI12.
+#define BF_DMA_EEI_EEI12(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI12), uint32_t) & BM_DMA_EEI_EEI12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI12 field to a new value.
+#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI13     (13U)         //!< Bit position for DMA_EEI_EEI13.
+#define BM_DMA_EEI_EEI13     (0x00002000U) //!< Bit mask for DMA_EEI_EEI13.
+#define BS_DMA_EEI_EEI13     (1U)          //!< Bit field size in bits for DMA_EEI_EEI13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI13 field.
+#define BR_DMA_EEI_EEI13(x)  (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI13.
+#define BF_DMA_EEI_EEI13(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI13), uint32_t) & BM_DMA_EEI_EEI13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI13 field to a new value.
+#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI14     (14U)         //!< Bit position for DMA_EEI_EEI14.
+#define BM_DMA_EEI_EEI14     (0x00004000U) //!< Bit mask for DMA_EEI_EEI14.
+#define BS_DMA_EEI_EEI14     (1U)          //!< Bit field size in bits for DMA_EEI_EEI14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI14 field.
+#define BR_DMA_EEI_EEI14(x)  (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI14.
+#define BF_DMA_EEI_EEI14(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI14), uint32_t) & BM_DMA_EEI_EEI14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI14 field to a new value.
+#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI15     (15U)         //!< Bit position for DMA_EEI_EEI15.
+#define BM_DMA_EEI_EEI15     (0x00008000U) //!< Bit mask for DMA_EEI_EEI15.
+#define BS_DMA_EEI_EEI15     (1U)          //!< Bit field size in bits for DMA_EEI_EEI15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI15 field.
+#define BR_DMA_EEI_EEI15(x)  (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI15.
+#define BF_DMA_EEI_EEI15(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI15), uint32_t) & BM_DMA_EEI_EEI15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI15 field to a new value.
+#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CEEI - Clear Enable Error Interrupt Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_ceei
+{
+    uint8_t U;
+    struct _hw_dma_ceei_bitfields
+    {
+        uint8_t CEEI : 4;              //!< [3:0] Clear Enable Error Interrupt
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t CAEE : 1;              //!< [6] Clear All Enable Error Interrupts
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_ceei_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+//@{
+#define HW_DMA_CEEI_ADDR(x)      (REGS_DMA_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CEEI(x)           (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
+#define HW_DMA_CEEI_RD(x)        (HW_DMA_CEEI(x).U)
+#define HW_DMA_CEEI_WR(x, v)     (HW_DMA_CEEI(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+//@{
+#define BP_DMA_CEEI_CEEI     (0U)          //!< Bit position for DMA_CEEI_CEEI.
+#define BM_DMA_CEEI_CEEI     (0x0FU)       //!< Bit mask for DMA_CEEI_CEEI.
+#define BS_DMA_CEEI_CEEI     (4U)          //!< Bit field size in bits for DMA_CEEI_CEEI.
+
+//! @brief Format value for bitfield DMA_CEEI_CEEI.
+#define BF_DMA_CEEI_CEEI(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CEEI), uint8_t) & BM_DMA_CEEI_CEEI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEEI field to a new value.
+#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the EEI bit specified in the CEEI field
+ * - 1 - Clear all bits in EEI
+ */
+//@{
+#define BP_DMA_CEEI_CAEE     (6U)          //!< Bit position for DMA_CEEI_CAEE.
+#define BM_DMA_CEEI_CAEE     (0x40U)       //!< Bit mask for DMA_CEEI_CAEE.
+#define BS_DMA_CEEI_CAEE     (1U)          //!< Bit field size in bits for DMA_CEEI_CAEE.
+
+//! @brief Format value for bitfield DMA_CEEI_CAEE.
+#define BF_DMA_CEEI_CAEE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CAEE), uint8_t) & BM_DMA_CEEI_CAEE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAEE field to a new value.
+#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CEEI_NOP      (7U)          //!< Bit position for DMA_CEEI_NOP.
+#define BM_DMA_CEEI_NOP      (0x80U)       //!< Bit mask for DMA_CEEI_NOP.
+#define BS_DMA_CEEI_NOP      (1U)          //!< Bit field size in bits for DMA_CEEI_NOP.
+
+//! @brief Format value for bitfield DMA_CEEI_NOP.
+#define BF_DMA_CEEI_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_NOP), uint8_t) & BM_DMA_CEEI_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_SEEI - Set Enable Error Interrupt Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+typedef union _hw_dma_seei
+{
+    uint8_t U;
+    struct _hw_dma_seei_bitfields
+    {
+        uint8_t SEEI : 4;              //!< [3:0] Set Enable Error Interrupt
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t SAEE : 1;              //!< [6] Sets All Enable Error Interrupts
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_seei_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+//@{
+#define HW_DMA_SEEI_ADDR(x)      (REGS_DMA_BASE(x) + 0x19U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_SEEI(x)           (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
+#define HW_DMA_SEEI_RD(x)        (HW_DMA_SEEI(x).U)
+#define HW_DMA_SEEI_WR(x, v)     (HW_DMA_SEEI(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+//@{
+#define BP_DMA_SEEI_SEEI     (0U)          //!< Bit position for DMA_SEEI_SEEI.
+#define BM_DMA_SEEI_SEEI     (0x0FU)       //!< Bit mask for DMA_SEEI_SEEI.
+#define BS_DMA_SEEI_SEEI     (4U)          //!< Bit field size in bits for DMA_SEEI_SEEI.
+
+//! @brief Format value for bitfield DMA_SEEI_SEEI.
+#define BF_DMA_SEEI_SEEI(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SEEI), uint8_t) & BM_DMA_SEEI_SEEI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEEI field to a new value.
+#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Set only the EEI bit specified in the SEEI field.
+ * - 1 - Sets all bits in EEI
+ */
+//@{
+#define BP_DMA_SEEI_SAEE     (6U)          //!< Bit position for DMA_SEEI_SAEE.
+#define BM_DMA_SEEI_SAEE     (0x40U)       //!< Bit mask for DMA_SEEI_SAEE.
+#define BS_DMA_SEEI_SAEE     (1U)          //!< Bit field size in bits for DMA_SEEI_SAEE.
+
+//! @brief Format value for bitfield DMA_SEEI_SAEE.
+#define BF_DMA_SEEI_SAEE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SAEE), uint8_t) & BM_DMA_SEEI_SAEE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAEE field to a new value.
+#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_SEEI_NOP      (7U)          //!< Bit position for DMA_SEEI_NOP.
+#define BM_DMA_SEEI_NOP      (0x80U)       //!< Bit mask for DMA_SEEI_NOP.
+#define BS_DMA_SEEI_NOP      (1U)          //!< Bit field size in bits for DMA_SEEI_NOP.
+
+//! @brief Format value for bitfield DMA_SEEI_NOP.
+#define BF_DMA_SEEI_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_NOP), uint8_t) & BM_DMA_SEEI_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CERQ - Clear Enable Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_cerq
+{
+    uint8_t U;
+    struct _hw_dma_cerq_bitfields
+    {
+        uint8_t CERQ : 4;              //!< [3:0] Clear Enable Request
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t CAER : 1;              //!< [6] Clear All Enable Requests
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_cerq_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+//@{
+#define HW_DMA_CERQ_ADDR(x)      (REGS_DMA_BASE(x) + 0x1AU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CERQ(x)           (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
+#define HW_DMA_CERQ_RD(x)        (HW_DMA_CERQ(x).U)
+#define HW_DMA_CERQ_WR(x, v)     (HW_DMA_CERQ(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+//@{
+#define BP_DMA_CERQ_CERQ     (0U)          //!< Bit position for DMA_CERQ_CERQ.
+#define BM_DMA_CERQ_CERQ     (0x0FU)       //!< Bit mask for DMA_CERQ_CERQ.
+#define BS_DMA_CERQ_CERQ     (4U)          //!< Bit field size in bits for DMA_CERQ_CERQ.
+
+//! @brief Format value for bitfield DMA_CERQ_CERQ.
+#define BF_DMA_CERQ_CERQ(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CERQ), uint8_t) & BM_DMA_CERQ_CERQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CERQ field to a new value.
+#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the ERQ bit specified in the CERQ field
+ * - 1 - Clear all bits in ERQ
+ */
+//@{
+#define BP_DMA_CERQ_CAER     (6U)          //!< Bit position for DMA_CERQ_CAER.
+#define BM_DMA_CERQ_CAER     (0x40U)       //!< Bit mask for DMA_CERQ_CAER.
+#define BS_DMA_CERQ_CAER     (1U)          //!< Bit field size in bits for DMA_CERQ_CAER.
+
+//! @brief Format value for bitfield DMA_CERQ_CAER.
+#define BF_DMA_CERQ_CAER(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CAER), uint8_t) & BM_DMA_CERQ_CAER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAER field to a new value.
+#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CERQ_NOP      (7U)          //!< Bit position for DMA_CERQ_NOP.
+#define BM_DMA_CERQ_NOP      (0x80U)       //!< Bit mask for DMA_CERQ_NOP.
+#define BS_DMA_CERQ_NOP      (1U)          //!< Bit field size in bits for DMA_CERQ_NOP.
+
+//! @brief Format value for bitfield DMA_CERQ_NOP.
+#define BF_DMA_CERQ_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_NOP), uint8_t) & BM_DMA_CERQ_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_SERQ - Set Enable Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_serq
+{
+    uint8_t U;
+    struct _hw_dma_serq_bitfields
+    {
+        uint8_t SERQ : 4;              //!< [3:0] Set enable request
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t SAER : 1;              //!< [6] Set All Enable Requests
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_serq_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+//@{
+#define HW_DMA_SERQ_ADDR(x)      (REGS_DMA_BASE(x) + 0x1BU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_SERQ(x)           (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
+#define HW_DMA_SERQ_RD(x)        (HW_DMA_SERQ(x).U)
+#define HW_DMA_SERQ_WR(x, v)     (HW_DMA_SERQ(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+//@{
+#define BP_DMA_SERQ_SERQ     (0U)          //!< Bit position for DMA_SERQ_SERQ.
+#define BM_DMA_SERQ_SERQ     (0x0FU)       //!< Bit mask for DMA_SERQ_SERQ.
+#define BS_DMA_SERQ_SERQ     (4U)          //!< Bit field size in bits for DMA_SERQ_SERQ.
+
+//! @brief Format value for bitfield DMA_SERQ_SERQ.
+#define BF_DMA_SERQ_SERQ(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SERQ), uint8_t) & BM_DMA_SERQ_SERQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SERQ field to a new value.
+#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Set only the ERQ bit specified in the SERQ field
+ * - 1 - Set all bits in ERQ
+ */
+//@{
+#define BP_DMA_SERQ_SAER     (6U)          //!< Bit position for DMA_SERQ_SAER.
+#define BM_DMA_SERQ_SAER     (0x40U)       //!< Bit mask for DMA_SERQ_SAER.
+#define BS_DMA_SERQ_SAER     (1U)          //!< Bit field size in bits for DMA_SERQ_SAER.
+
+//! @brief Format value for bitfield DMA_SERQ_SAER.
+#define BF_DMA_SERQ_SAER(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SAER), uint8_t) & BM_DMA_SERQ_SAER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAER field to a new value.
+#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_SERQ_NOP      (7U)          //!< Bit position for DMA_SERQ_NOP.
+#define BM_DMA_SERQ_NOP      (0x80U)       //!< Bit mask for DMA_SERQ_NOP.
+#define BS_DMA_SERQ_NOP      (1U)          //!< Bit field size in bits for DMA_SERQ_NOP.
+
+//! @brief Format value for bitfield DMA_SERQ_NOP.
+#define BF_DMA_SERQ_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_NOP), uint8_t) & BM_DMA_SERQ_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CDNE - Clear DONE Status Bit Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+typedef union _hw_dma_cdne
+{
+    uint8_t U;
+    struct _hw_dma_cdne_bitfields
+    {
+        uint8_t CDNE : 4;              //!< [3:0] Clear DONE Bit
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t CADN : 1;              //!< [6] Clears All DONE Bits
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_cdne_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+//@{
+#define HW_DMA_CDNE_ADDR(x)      (REGS_DMA_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CDNE(x)           (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
+#define HW_DMA_CDNE_RD(x)        (HW_DMA_CDNE(x).U)
+#define HW_DMA_CDNE_WR(x, v)     (HW_DMA_CDNE(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+//@{
+#define BP_DMA_CDNE_CDNE     (0U)          //!< Bit position for DMA_CDNE_CDNE.
+#define BM_DMA_CDNE_CDNE     (0x0FU)       //!< Bit mask for DMA_CDNE_CDNE.
+#define BS_DMA_CDNE_CDNE     (4U)          //!< Bit field size in bits for DMA_CDNE_CDNE.
+
+//! @brief Format value for bitfield DMA_CDNE_CDNE.
+#define BF_DMA_CDNE_CDNE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CDNE), uint8_t) & BM_DMA_CDNE_CDNE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CDNE field to a new value.
+#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 1 - Clears all bits in TCDn_CSR[DONE]
+ */
+//@{
+#define BP_DMA_CDNE_CADN     (6U)          //!< Bit position for DMA_CDNE_CADN.
+#define BM_DMA_CDNE_CADN     (0x40U)       //!< Bit mask for DMA_CDNE_CADN.
+#define BS_DMA_CDNE_CADN     (1U)          //!< Bit field size in bits for DMA_CDNE_CADN.
+
+//! @brief Format value for bitfield DMA_CDNE_CADN.
+#define BF_DMA_CDNE_CADN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CADN), uint8_t) & BM_DMA_CDNE_CADN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CADN field to a new value.
+#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CDNE_NOP      (7U)          //!< Bit position for DMA_CDNE_NOP.
+#define BM_DMA_CDNE_NOP      (0x80U)       //!< Bit mask for DMA_CDNE_NOP.
+#define BS_DMA_CDNE_NOP      (1U)          //!< Bit field size in bits for DMA_CDNE_NOP.
+
+//! @brief Format value for bitfield DMA_CDNE_NOP.
+#define BF_DMA_CDNE_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_NOP), uint8_t) & BM_DMA_CDNE_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_SSRT - Set START Bit Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_ssrt
+{
+    uint8_t U;
+    struct _hw_dma_ssrt_bitfields
+    {
+        uint8_t SSRT : 4;              //!< [3:0] Set START Bit
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t SAST : 1;              //!< [6] Set All START Bits (activates all channels)
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_ssrt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+//@{
+#define HW_DMA_SSRT_ADDR(x)      (REGS_DMA_BASE(x) + 0x1DU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_SSRT(x)           (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
+#define HW_DMA_SSRT_RD(x)        (HW_DMA_SSRT(x).U)
+#define HW_DMA_SSRT_WR(x, v)     (HW_DMA_SSRT(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+//@{
+#define BP_DMA_SSRT_SSRT     (0U)          //!< Bit position for DMA_SSRT_SSRT.
+#define BM_DMA_SSRT_SSRT     (0x0FU)       //!< Bit mask for DMA_SSRT_SSRT.
+#define BS_DMA_SSRT_SSRT     (4U)          //!< Bit field size in bits for DMA_SSRT_SSRT.
+
+//! @brief Format value for bitfield DMA_SSRT_SSRT.
+#define BF_DMA_SSRT_SSRT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SSRT), uint8_t) & BM_DMA_SSRT_SSRT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSRT field to a new value.
+#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 1 - Set all bits in TCDn_CSR[START]
+ */
+//@{
+#define BP_DMA_SSRT_SAST     (6U)          //!< Bit position for DMA_SSRT_SAST.
+#define BM_DMA_SSRT_SAST     (0x40U)       //!< Bit mask for DMA_SSRT_SAST.
+#define BS_DMA_SSRT_SAST     (1U)          //!< Bit field size in bits for DMA_SSRT_SAST.
+
+//! @brief Format value for bitfield DMA_SSRT_SAST.
+#define BF_DMA_SSRT_SAST(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SAST), uint8_t) & BM_DMA_SSRT_SAST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAST field to a new value.
+#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_SSRT_NOP      (7U)          //!< Bit position for DMA_SSRT_NOP.
+#define BM_DMA_SSRT_NOP      (0x80U)       //!< Bit mask for DMA_SSRT_NOP.
+#define BS_DMA_SSRT_NOP      (1U)          //!< Bit field size in bits for DMA_SSRT_NOP.
+
+//! @brief Format value for bitfield DMA_SSRT_NOP.
+#define BF_DMA_SSRT_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_NOP), uint8_t) & BM_DMA_SSRT_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CERR - Clear Error Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_cerr
+{
+    uint8_t U;
+    struct _hw_dma_cerr_bitfields
+    {
+        uint8_t CERR : 4;              //!< [3:0] Clear Error Indicator
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t CAEI : 1;              //!< [6] Clear All Error Indicators
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_cerr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+//@{
+#define HW_DMA_CERR_ADDR(x)      (REGS_DMA_BASE(x) + 0x1EU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CERR(x)           (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
+#define HW_DMA_CERR_RD(x)        (HW_DMA_CERR(x).U)
+#define HW_DMA_CERR_WR(x, v)     (HW_DMA_CERR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+//@{
+#define BP_DMA_CERR_CERR     (0U)          //!< Bit position for DMA_CERR_CERR.
+#define BM_DMA_CERR_CERR     (0x0FU)       //!< Bit mask for DMA_CERR_CERR.
+#define BS_DMA_CERR_CERR     (4U)          //!< Bit field size in bits for DMA_CERR_CERR.
+
+//! @brief Format value for bitfield DMA_CERR_CERR.
+#define BF_DMA_CERR_CERR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CERR), uint8_t) & BM_DMA_CERR_CERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CERR field to a new value.
+#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the ERR bit specified in the CERR field
+ * - 1 - Clear all bits in ERR
+ */
+//@{
+#define BP_DMA_CERR_CAEI     (6U)          //!< Bit position for DMA_CERR_CAEI.
+#define BM_DMA_CERR_CAEI     (0x40U)       //!< Bit mask for DMA_CERR_CAEI.
+#define BS_DMA_CERR_CAEI     (1U)          //!< Bit field size in bits for DMA_CERR_CAEI.
+
+//! @brief Format value for bitfield DMA_CERR_CAEI.
+#define BF_DMA_CERR_CAEI(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CAEI), uint8_t) & BM_DMA_CERR_CAEI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAEI field to a new value.
+#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CERR_NOP      (7U)          //!< Bit position for DMA_CERR_NOP.
+#define BM_DMA_CERR_NOP      (0x80U)       //!< Bit mask for DMA_CERR_NOP.
+#define BS_DMA_CERR_NOP      (1U)          //!< Bit field size in bits for DMA_CERR_NOP.
+
+//! @brief Format value for bitfield DMA_CERR_NOP.
+#define BF_DMA_CERR_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_NOP), uint8_t) & BM_DMA_CERR_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CINT - Clear Interrupt Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_cint
+{
+    uint8_t U;
+    struct _hw_dma_cint_bitfields
+    {
+        uint8_t CINT : 4;              //!< [3:0] Clear Interrupt Request
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t CAIR : 1;              //!< [6] Clear All Interrupt Requests
+        uint8_t NOP : 1;               //!< [7] No Op enable
+    } B;
+} hw_dma_cint_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+//@{
+#define HW_DMA_CINT_ADDR(x)      (REGS_DMA_BASE(x) + 0x1FU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CINT(x)           (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
+#define HW_DMA_CINT_RD(x)        (HW_DMA_CINT(x).U)
+#define HW_DMA_CINT_WR(x, v)     (HW_DMA_CINT(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+//@{
+#define BP_DMA_CINT_CINT     (0U)          //!< Bit position for DMA_CINT_CINT.
+#define BM_DMA_CINT_CINT     (0x0FU)       //!< Bit mask for DMA_CINT_CINT.
+#define BS_DMA_CINT_CINT     (4U)          //!< Bit field size in bits for DMA_CINT_CINT.
+
+//! @brief Format value for bitfield DMA_CINT_CINT.
+#define BF_DMA_CINT_CINT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CINT), uint8_t) & BM_DMA_CINT_CINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINT field to a new value.
+#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the INT bit specified in the CINT field
+ * - 1 - Clear all bits in INT
+ */
+//@{
+#define BP_DMA_CINT_CAIR     (6U)          //!< Bit position for DMA_CINT_CAIR.
+#define BM_DMA_CINT_CAIR     (0x40U)       //!< Bit mask for DMA_CINT_CAIR.
+#define BS_DMA_CINT_CAIR     (1U)          //!< Bit field size in bits for DMA_CINT_CAIR.
+
+//! @brief Format value for bitfield DMA_CINT_CAIR.
+#define BF_DMA_CINT_CAIR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CAIR), uint8_t) & BM_DMA_CINT_CAIR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAIR field to a new value.
+#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CINT_NOP      (7U)          //!< Bit position for DMA_CINT_NOP.
+#define BM_DMA_CINT_NOP      (0x80U)       //!< Bit mask for DMA_CINT_NOP.
+#define BS_DMA_CINT_NOP      (1U)          //!< Bit field size in bits for DMA_CINT_NOP.
+
+//! @brief Format value for bitfield DMA_CINT_NOP.
+#define BF_DMA_CINT_NOP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_NOP), uint8_t) & BM_DMA_CINT_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_INT - Interrupt Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+typedef union _hw_dma_int
+{
+    uint32_t U;
+    struct _hw_dma_int_bitfields
+    {
+        uint32_t INT0 : 1;             //!< [0] Interrupt Request 0
+        uint32_t INT1 : 1;             //!< [1] Interrupt Request 1
+        uint32_t INT2 : 1;             //!< [2] Interrupt Request 2
+        uint32_t INT3 : 1;             //!< [3] Interrupt Request 3
+        uint32_t INT4 : 1;             //!< [4] Interrupt Request 4
+        uint32_t INT5 : 1;             //!< [5] Interrupt Request 5
+        uint32_t INT6 : 1;             //!< [6] Interrupt Request 6
+        uint32_t INT7 : 1;             //!< [7] Interrupt Request 7
+        uint32_t INT8 : 1;             //!< [8] Interrupt Request 8
+        uint32_t INT9 : 1;             //!< [9] Interrupt Request 9
+        uint32_t INT10 : 1;            //!< [10] Interrupt Request 10
+        uint32_t INT11 : 1;            //!< [11] Interrupt Request 11
+        uint32_t INT12 : 1;            //!< [12] Interrupt Request 12
+        uint32_t INT13 : 1;            //!< [13] Interrupt Request 13
+        uint32_t INT14 : 1;            //!< [14] Interrupt Request 14
+        uint32_t INT15 : 1;            //!< [15] Interrupt Request 15
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_dma_int_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+//@{
+#define HW_DMA_INT_ADDR(x)       (REGS_DMA_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_INT(x)            (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
+#define HW_DMA_INT_RD(x)         (HW_DMA_INT(x).U)
+#define HW_DMA_INT_WR(x, v)      (HW_DMA_INT(x).U = (v))
+#define HW_DMA_INT_SET(x, v)     (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) |  (v)))
+#define HW_DMA_INT_CLR(x, v)     (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
+#define HW_DMA_INT_TOG(x, v)     (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT0      (0U)          //!< Bit position for DMA_INT_INT0.
+#define BM_DMA_INT_INT0      (0x00000001U) //!< Bit mask for DMA_INT_INT0.
+#define BS_DMA_INT_INT0      (1U)          //!< Bit field size in bits for DMA_INT_INT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT0 field.
+#define BR_DMA_INT_INT0(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT0.
+#define BF_DMA_INT_INT0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT0), uint32_t) & BM_DMA_INT_INT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT0 field to a new value.
+#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT1      (1U)          //!< Bit position for DMA_INT_INT1.
+#define BM_DMA_INT_INT1      (0x00000002U) //!< Bit mask for DMA_INT_INT1.
+#define BS_DMA_INT_INT1      (1U)          //!< Bit field size in bits for DMA_INT_INT1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT1 field.
+#define BR_DMA_INT_INT1(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT1.
+#define BF_DMA_INT_INT1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT1), uint32_t) & BM_DMA_INT_INT1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT1 field to a new value.
+#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT2      (2U)          //!< Bit position for DMA_INT_INT2.
+#define BM_DMA_INT_INT2      (0x00000004U) //!< Bit mask for DMA_INT_INT2.
+#define BS_DMA_INT_INT2      (1U)          //!< Bit field size in bits for DMA_INT_INT2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT2 field.
+#define BR_DMA_INT_INT2(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT2.
+#define BF_DMA_INT_INT2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT2), uint32_t) & BM_DMA_INT_INT2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT2 field to a new value.
+#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT3      (3U)          //!< Bit position for DMA_INT_INT3.
+#define BM_DMA_INT_INT3      (0x00000008U) //!< Bit mask for DMA_INT_INT3.
+#define BS_DMA_INT_INT3      (1U)          //!< Bit field size in bits for DMA_INT_INT3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT3 field.
+#define BR_DMA_INT_INT3(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT3.
+#define BF_DMA_INT_INT3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT3), uint32_t) & BM_DMA_INT_INT3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT3 field to a new value.
+#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT4      (4U)          //!< Bit position for DMA_INT_INT4.
+#define BM_DMA_INT_INT4      (0x00000010U) //!< Bit mask for DMA_INT_INT4.
+#define BS_DMA_INT_INT4      (1U)          //!< Bit field size in bits for DMA_INT_INT4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT4 field.
+#define BR_DMA_INT_INT4(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT4.
+#define BF_DMA_INT_INT4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT4), uint32_t) & BM_DMA_INT_INT4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT4 field to a new value.
+#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT5      (5U)          //!< Bit position for DMA_INT_INT5.
+#define BM_DMA_INT_INT5      (0x00000020U) //!< Bit mask for DMA_INT_INT5.
+#define BS_DMA_INT_INT5      (1U)          //!< Bit field size in bits for DMA_INT_INT5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT5 field.
+#define BR_DMA_INT_INT5(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT5.
+#define BF_DMA_INT_INT5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT5), uint32_t) & BM_DMA_INT_INT5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT5 field to a new value.
+#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT6      (6U)          //!< Bit position for DMA_INT_INT6.
+#define BM_DMA_INT_INT6      (0x00000040U) //!< Bit mask for DMA_INT_INT6.
+#define BS_DMA_INT_INT6      (1U)          //!< Bit field size in bits for DMA_INT_INT6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT6 field.
+#define BR_DMA_INT_INT6(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT6.
+#define BF_DMA_INT_INT6(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT6), uint32_t) & BM_DMA_INT_INT6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT6 field to a new value.
+#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT7      (7U)          //!< Bit position for DMA_INT_INT7.
+#define BM_DMA_INT_INT7      (0x00000080U) //!< Bit mask for DMA_INT_INT7.
+#define BS_DMA_INT_INT7      (1U)          //!< Bit field size in bits for DMA_INT_INT7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT7 field.
+#define BR_DMA_INT_INT7(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT7.
+#define BF_DMA_INT_INT7(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT7), uint32_t) & BM_DMA_INT_INT7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT7 field to a new value.
+#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT8      (8U)          //!< Bit position for DMA_INT_INT8.
+#define BM_DMA_INT_INT8      (0x00000100U) //!< Bit mask for DMA_INT_INT8.
+#define BS_DMA_INT_INT8      (1U)          //!< Bit field size in bits for DMA_INT_INT8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT8 field.
+#define BR_DMA_INT_INT8(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT8.
+#define BF_DMA_INT_INT8(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT8), uint32_t) & BM_DMA_INT_INT8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT8 field to a new value.
+#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT9      (9U)          //!< Bit position for DMA_INT_INT9.
+#define BM_DMA_INT_INT9      (0x00000200U) //!< Bit mask for DMA_INT_INT9.
+#define BS_DMA_INT_INT9      (1U)          //!< Bit field size in bits for DMA_INT_INT9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT9 field.
+#define BR_DMA_INT_INT9(x)   (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT9.
+#define BF_DMA_INT_INT9(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT9), uint32_t) & BM_DMA_INT_INT9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT9 field to a new value.
+#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT10     (10U)         //!< Bit position for DMA_INT_INT10.
+#define BM_DMA_INT_INT10     (0x00000400U) //!< Bit mask for DMA_INT_INT10.
+#define BS_DMA_INT_INT10     (1U)          //!< Bit field size in bits for DMA_INT_INT10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT10 field.
+#define BR_DMA_INT_INT10(x)  (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT10.
+#define BF_DMA_INT_INT10(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT10), uint32_t) & BM_DMA_INT_INT10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT10 field to a new value.
+#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT11     (11U)         //!< Bit position for DMA_INT_INT11.
+#define BM_DMA_INT_INT11     (0x00000800U) //!< Bit mask for DMA_INT_INT11.
+#define BS_DMA_INT_INT11     (1U)          //!< Bit field size in bits for DMA_INT_INT11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT11 field.
+#define BR_DMA_INT_INT11(x)  (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT11.
+#define BF_DMA_INT_INT11(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT11), uint32_t) & BM_DMA_INT_INT11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT11 field to a new value.
+#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT12     (12U)         //!< Bit position for DMA_INT_INT12.
+#define BM_DMA_INT_INT12     (0x00001000U) //!< Bit mask for DMA_INT_INT12.
+#define BS_DMA_INT_INT12     (1U)          //!< Bit field size in bits for DMA_INT_INT12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT12 field.
+#define BR_DMA_INT_INT12(x)  (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT12.
+#define BF_DMA_INT_INT12(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT12), uint32_t) & BM_DMA_INT_INT12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT12 field to a new value.
+#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT13     (13U)         //!< Bit position for DMA_INT_INT13.
+#define BM_DMA_INT_INT13     (0x00002000U) //!< Bit mask for DMA_INT_INT13.
+#define BS_DMA_INT_INT13     (1U)          //!< Bit field size in bits for DMA_INT_INT13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT13 field.
+#define BR_DMA_INT_INT13(x)  (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT13.
+#define BF_DMA_INT_INT13(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT13), uint32_t) & BM_DMA_INT_INT13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT13 field to a new value.
+#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT14     (14U)         //!< Bit position for DMA_INT_INT14.
+#define BM_DMA_INT_INT14     (0x00004000U) //!< Bit mask for DMA_INT_INT14.
+#define BS_DMA_INT_INT14     (1U)          //!< Bit field size in bits for DMA_INT_INT14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT14 field.
+#define BR_DMA_INT_INT14(x)  (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT14.
+#define BF_DMA_INT_INT14(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT14), uint32_t) & BM_DMA_INT_INT14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT14 field to a new value.
+#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT15     (15U)         //!< Bit position for DMA_INT_INT15.
+#define BM_DMA_INT_INT15     (0x00008000U) //!< Bit mask for DMA_INT_INT15.
+#define BS_DMA_INT_INT15     (1U)          //!< Bit field size in bits for DMA_INT_INT15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT15 field.
+#define BR_DMA_INT_INT15(x)  (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT15.
+#define BF_DMA_INT_INT15(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT15), uint32_t) & BM_DMA_INT_INT15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT15 field to a new value.
+#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_ERR - Error Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+typedef union _hw_dma_err
+{
+    uint32_t U;
+    struct _hw_dma_err_bitfields
+    {
+        uint32_t ERR0 : 1;             //!< [0] Error In Channel 0
+        uint32_t ERR1 : 1;             //!< [1] Error In Channel 1
+        uint32_t ERR2 : 1;             //!< [2] Error In Channel 2
+        uint32_t ERR3 : 1;             //!< [3] Error In Channel 3
+        uint32_t ERR4 : 1;             //!< [4] Error In Channel 4
+        uint32_t ERR5 : 1;             //!< [5] Error In Channel 5
+        uint32_t ERR6 : 1;             //!< [6] Error In Channel 6
+        uint32_t ERR7 : 1;             //!< [7] Error In Channel 7
+        uint32_t ERR8 : 1;             //!< [8] Error In Channel 8
+        uint32_t ERR9 : 1;             //!< [9] Error In Channel 9
+        uint32_t ERR10 : 1;            //!< [10] Error In Channel 10
+        uint32_t ERR11 : 1;            //!< [11] Error In Channel 11
+        uint32_t ERR12 : 1;            //!< [12] Error In Channel 12
+        uint32_t ERR13 : 1;            //!< [13] Error In Channel 13
+        uint32_t ERR14 : 1;            //!< [14] Error In Channel 14
+        uint32_t ERR15 : 1;            //!< [15] Error In Channel 15
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_dma_err_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+//@{
+#define HW_DMA_ERR_ADDR(x)       (REGS_DMA_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_ERR(x)            (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
+#define HW_DMA_ERR_RD(x)         (HW_DMA_ERR(x).U)
+#define HW_DMA_ERR_WR(x, v)      (HW_DMA_ERR(x).U = (v))
+#define HW_DMA_ERR_SET(x, v)     (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) |  (v)))
+#define HW_DMA_ERR_CLR(x, v)     (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
+#define HW_DMA_ERR_TOG(x, v)     (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR0      (0U)          //!< Bit position for DMA_ERR_ERR0.
+#define BM_DMA_ERR_ERR0      (0x00000001U) //!< Bit mask for DMA_ERR_ERR0.
+#define BS_DMA_ERR_ERR0      (1U)          //!< Bit field size in bits for DMA_ERR_ERR0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR0 field.
+#define BR_DMA_ERR_ERR0(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR0.
+#define BF_DMA_ERR_ERR0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR0), uint32_t) & BM_DMA_ERR_ERR0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR0 field to a new value.
+#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR1      (1U)          //!< Bit position for DMA_ERR_ERR1.
+#define BM_DMA_ERR_ERR1      (0x00000002U) //!< Bit mask for DMA_ERR_ERR1.
+#define BS_DMA_ERR_ERR1      (1U)          //!< Bit field size in bits for DMA_ERR_ERR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR1 field.
+#define BR_DMA_ERR_ERR1(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR1.
+#define BF_DMA_ERR_ERR1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR1), uint32_t) & BM_DMA_ERR_ERR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR1 field to a new value.
+#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR2      (2U)          //!< Bit position for DMA_ERR_ERR2.
+#define BM_DMA_ERR_ERR2      (0x00000004U) //!< Bit mask for DMA_ERR_ERR2.
+#define BS_DMA_ERR_ERR2      (1U)          //!< Bit field size in bits for DMA_ERR_ERR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR2 field.
+#define BR_DMA_ERR_ERR2(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR2.
+#define BF_DMA_ERR_ERR2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR2), uint32_t) & BM_DMA_ERR_ERR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR2 field to a new value.
+#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR3      (3U)          //!< Bit position for DMA_ERR_ERR3.
+#define BM_DMA_ERR_ERR3      (0x00000008U) //!< Bit mask for DMA_ERR_ERR3.
+#define BS_DMA_ERR_ERR3      (1U)          //!< Bit field size in bits for DMA_ERR_ERR3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR3 field.
+#define BR_DMA_ERR_ERR3(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR3.
+#define BF_DMA_ERR_ERR3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR3), uint32_t) & BM_DMA_ERR_ERR3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR3 field to a new value.
+#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR4      (4U)          //!< Bit position for DMA_ERR_ERR4.
+#define BM_DMA_ERR_ERR4      (0x00000010U) //!< Bit mask for DMA_ERR_ERR4.
+#define BS_DMA_ERR_ERR4      (1U)          //!< Bit field size in bits for DMA_ERR_ERR4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR4 field.
+#define BR_DMA_ERR_ERR4(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR4.
+#define BF_DMA_ERR_ERR4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR4), uint32_t) & BM_DMA_ERR_ERR4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR4 field to a new value.
+#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR5      (5U)          //!< Bit position for DMA_ERR_ERR5.
+#define BM_DMA_ERR_ERR5      (0x00000020U) //!< Bit mask for DMA_ERR_ERR5.
+#define BS_DMA_ERR_ERR5      (1U)          //!< Bit field size in bits for DMA_ERR_ERR5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR5 field.
+#define BR_DMA_ERR_ERR5(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR5.
+#define BF_DMA_ERR_ERR5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR5), uint32_t) & BM_DMA_ERR_ERR5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR5 field to a new value.
+#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR6      (6U)          //!< Bit position for DMA_ERR_ERR6.
+#define BM_DMA_ERR_ERR6      (0x00000040U) //!< Bit mask for DMA_ERR_ERR6.
+#define BS_DMA_ERR_ERR6      (1U)          //!< Bit field size in bits for DMA_ERR_ERR6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR6 field.
+#define BR_DMA_ERR_ERR6(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR6.
+#define BF_DMA_ERR_ERR6(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR6), uint32_t) & BM_DMA_ERR_ERR6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR6 field to a new value.
+#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR7      (7U)          //!< Bit position for DMA_ERR_ERR7.
+#define BM_DMA_ERR_ERR7      (0x00000080U) //!< Bit mask for DMA_ERR_ERR7.
+#define BS_DMA_ERR_ERR7      (1U)          //!< Bit field size in bits for DMA_ERR_ERR7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR7 field.
+#define BR_DMA_ERR_ERR7(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR7.
+#define BF_DMA_ERR_ERR7(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR7), uint32_t) & BM_DMA_ERR_ERR7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR7 field to a new value.
+#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR8      (8U)          //!< Bit position for DMA_ERR_ERR8.
+#define BM_DMA_ERR_ERR8      (0x00000100U) //!< Bit mask for DMA_ERR_ERR8.
+#define BS_DMA_ERR_ERR8      (1U)          //!< Bit field size in bits for DMA_ERR_ERR8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR8 field.
+#define BR_DMA_ERR_ERR8(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR8.
+#define BF_DMA_ERR_ERR8(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR8), uint32_t) & BM_DMA_ERR_ERR8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR8 field to a new value.
+#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR9      (9U)          //!< Bit position for DMA_ERR_ERR9.
+#define BM_DMA_ERR_ERR9      (0x00000200U) //!< Bit mask for DMA_ERR_ERR9.
+#define BS_DMA_ERR_ERR9      (1U)          //!< Bit field size in bits for DMA_ERR_ERR9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR9 field.
+#define BR_DMA_ERR_ERR9(x)   (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR9.
+#define BF_DMA_ERR_ERR9(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR9), uint32_t) & BM_DMA_ERR_ERR9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR9 field to a new value.
+#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR10     (10U)         //!< Bit position for DMA_ERR_ERR10.
+#define BM_DMA_ERR_ERR10     (0x00000400U) //!< Bit mask for DMA_ERR_ERR10.
+#define BS_DMA_ERR_ERR10     (1U)          //!< Bit field size in bits for DMA_ERR_ERR10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR10 field.
+#define BR_DMA_ERR_ERR10(x)  (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR10.
+#define BF_DMA_ERR_ERR10(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR10), uint32_t) & BM_DMA_ERR_ERR10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR10 field to a new value.
+#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR11     (11U)         //!< Bit position for DMA_ERR_ERR11.
+#define BM_DMA_ERR_ERR11     (0x00000800U) //!< Bit mask for DMA_ERR_ERR11.
+#define BS_DMA_ERR_ERR11     (1U)          //!< Bit field size in bits for DMA_ERR_ERR11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR11 field.
+#define BR_DMA_ERR_ERR11(x)  (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR11.
+#define BF_DMA_ERR_ERR11(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR11), uint32_t) & BM_DMA_ERR_ERR11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR11 field to a new value.
+#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR12     (12U)         //!< Bit position for DMA_ERR_ERR12.
+#define BM_DMA_ERR_ERR12     (0x00001000U) //!< Bit mask for DMA_ERR_ERR12.
+#define BS_DMA_ERR_ERR12     (1U)          //!< Bit field size in bits for DMA_ERR_ERR12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR12 field.
+#define BR_DMA_ERR_ERR12(x)  (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR12.
+#define BF_DMA_ERR_ERR12(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR12), uint32_t) & BM_DMA_ERR_ERR12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR12 field to a new value.
+#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR13     (13U)         //!< Bit position for DMA_ERR_ERR13.
+#define BM_DMA_ERR_ERR13     (0x00002000U) //!< Bit mask for DMA_ERR_ERR13.
+#define BS_DMA_ERR_ERR13     (1U)          //!< Bit field size in bits for DMA_ERR_ERR13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR13 field.
+#define BR_DMA_ERR_ERR13(x)  (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR13.
+#define BF_DMA_ERR_ERR13(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR13), uint32_t) & BM_DMA_ERR_ERR13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR13 field to a new value.
+#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR14     (14U)         //!< Bit position for DMA_ERR_ERR14.
+#define BM_DMA_ERR_ERR14     (0x00004000U) //!< Bit mask for DMA_ERR_ERR14.
+#define BS_DMA_ERR_ERR14     (1U)          //!< Bit field size in bits for DMA_ERR_ERR14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR14 field.
+#define BR_DMA_ERR_ERR14(x)  (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR14.
+#define BF_DMA_ERR_ERR14(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR14), uint32_t) & BM_DMA_ERR_ERR14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR14 field to a new value.
+#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR15     (15U)         //!< Bit position for DMA_ERR_ERR15.
+#define BM_DMA_ERR_ERR15     (0x00008000U) //!< Bit mask for DMA_ERR_ERR15.
+#define BS_DMA_ERR_ERR15     (1U)          //!< Bit field size in bits for DMA_ERR_ERR15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR15 field.
+#define BR_DMA_ERR_ERR15(x)  (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR15.
+#define BF_DMA_ERR_ERR15(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR15), uint32_t) & BM_DMA_ERR_ERR15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR15 field to a new value.
+#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_HRS - Hardware Request Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+typedef union _hw_dma_hrs
+{
+    uint32_t U;
+    struct _hw_dma_hrs_bitfields
+    {
+        uint32_t HRS0 : 1;             //!< [0] Hardware Request Status Channel 0
+        uint32_t HRS1 : 1;             //!< [1] Hardware Request Status Channel 1
+        uint32_t HRS2 : 1;             //!< [2] Hardware Request Status Channel 2
+        uint32_t HRS3 : 1;             //!< [3] Hardware Request Status Channel 3
+        uint32_t HRS4 : 1;             //!< [4] Hardware Request Status Channel 4
+        uint32_t HRS5 : 1;             //!< [5] Hardware Request Status Channel 5
+        uint32_t HRS6 : 1;             //!< [6] Hardware Request Status Channel 6
+        uint32_t HRS7 : 1;             //!< [7] Hardware Request Status Channel 7
+        uint32_t HRS8 : 1;             //!< [8] Hardware Request Status Channel 8
+        uint32_t HRS9 : 1;             //!< [9] Hardware Request Status Channel 9
+        uint32_t HRS10 : 1;            //!< [10] Hardware Request Status Channel 10
+        uint32_t HRS11 : 1;            //!< [11] Hardware Request Status Channel 11
+        uint32_t HRS12 : 1;            //!< [12] Hardware Request Status Channel 12
+        uint32_t HRS13 : 1;            //!< [13] Hardware Request Status Channel 13
+        uint32_t HRS14 : 1;            //!< [14] Hardware Request Status Channel 14
+        uint32_t HRS15 : 1;            //!< [15] Hardware Request Status Channel 15
+        uint32_t RESERVED0 : 16;       //!< [31:16] Reserved
+    } B;
+} hw_dma_hrs_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+//@{
+#define HW_DMA_HRS_ADDR(x)       (REGS_DMA_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_HRS(x)            (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
+#define HW_DMA_HRS_RD(x)         (HW_DMA_HRS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 0 is not present
+ * - 1 - A hardware service request for channel 0 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS0      (0U)          //!< Bit position for DMA_HRS_HRS0.
+#define BM_DMA_HRS_HRS0      (0x00000001U) //!< Bit mask for DMA_HRS_HRS0.
+#define BS_DMA_HRS_HRS0      (1U)          //!< Bit field size in bits for DMA_HRS_HRS0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS0 field.
+#define BR_DMA_HRS_HRS0(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 1 is not present
+ * - 1 - A hardware service request for channel 1 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS1      (1U)          //!< Bit position for DMA_HRS_HRS1.
+#define BM_DMA_HRS_HRS1      (0x00000002U) //!< Bit mask for DMA_HRS_HRS1.
+#define BS_DMA_HRS_HRS1      (1U)          //!< Bit field size in bits for DMA_HRS_HRS1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS1 field.
+#define BR_DMA_HRS_HRS1(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 2 is not present
+ * - 1 - A hardware service request for channel 2 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS2      (2U)          //!< Bit position for DMA_HRS_HRS2.
+#define BM_DMA_HRS_HRS2      (0x00000004U) //!< Bit mask for DMA_HRS_HRS2.
+#define BS_DMA_HRS_HRS2      (1U)          //!< Bit field size in bits for DMA_HRS_HRS2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS2 field.
+#define BR_DMA_HRS_HRS2(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 3 is not present
+ * - 1 - A hardware service request for channel 3 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS3      (3U)          //!< Bit position for DMA_HRS_HRS3.
+#define BM_DMA_HRS_HRS3      (0x00000008U) //!< Bit mask for DMA_HRS_HRS3.
+#define BS_DMA_HRS_HRS3      (1U)          //!< Bit field size in bits for DMA_HRS_HRS3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS3 field.
+#define BR_DMA_HRS_HRS3(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 4 is not present
+ * - 1 - A hardware service request for channel 4 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS4      (4U)          //!< Bit position for DMA_HRS_HRS4.
+#define BM_DMA_HRS_HRS4      (0x00000010U) //!< Bit mask for DMA_HRS_HRS4.
+#define BS_DMA_HRS_HRS4      (1U)          //!< Bit field size in bits for DMA_HRS_HRS4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS4 field.
+#define BR_DMA_HRS_HRS4(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 5 is not present
+ * - 1 - A hardware service request for channel 5 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS5      (5U)          //!< Bit position for DMA_HRS_HRS5.
+#define BM_DMA_HRS_HRS5      (0x00000020U) //!< Bit mask for DMA_HRS_HRS5.
+#define BS_DMA_HRS_HRS5      (1U)          //!< Bit field size in bits for DMA_HRS_HRS5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS5 field.
+#define BR_DMA_HRS_HRS5(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 6 is not present
+ * - 1 - A hardware service request for channel 6 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS6      (6U)          //!< Bit position for DMA_HRS_HRS6.
+#define BM_DMA_HRS_HRS6      (0x00000040U) //!< Bit mask for DMA_HRS_HRS6.
+#define BS_DMA_HRS_HRS6      (1U)          //!< Bit field size in bits for DMA_HRS_HRS6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS6 field.
+#define BR_DMA_HRS_HRS6(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 7 is not present
+ * - 1 - A hardware service request for channel 7 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS7      (7U)          //!< Bit position for DMA_HRS_HRS7.
+#define BM_DMA_HRS_HRS7      (0x00000080U) //!< Bit mask for DMA_HRS_HRS7.
+#define BS_DMA_HRS_HRS7      (1U)          //!< Bit field size in bits for DMA_HRS_HRS7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS7 field.
+#define BR_DMA_HRS_HRS7(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 8 is not present
+ * - 1 - A hardware service request for channel 8 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS8      (8U)          //!< Bit position for DMA_HRS_HRS8.
+#define BM_DMA_HRS_HRS8      (0x00000100U) //!< Bit mask for DMA_HRS_HRS8.
+#define BS_DMA_HRS_HRS8      (1U)          //!< Bit field size in bits for DMA_HRS_HRS8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS8 field.
+#define BR_DMA_HRS_HRS8(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 9 is not present
+ * - 1 - A hardware service request for channel 9 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS9      (9U)          //!< Bit position for DMA_HRS_HRS9.
+#define BM_DMA_HRS_HRS9      (0x00000200U) //!< Bit mask for DMA_HRS_HRS9.
+#define BS_DMA_HRS_HRS9      (1U)          //!< Bit field size in bits for DMA_HRS_HRS9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS9 field.
+#define BR_DMA_HRS_HRS9(x)   (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 10 is not present
+ * - 1 - A hardware service request for channel 10 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS10     (10U)         //!< Bit position for DMA_HRS_HRS10.
+#define BM_DMA_HRS_HRS10     (0x00000400U) //!< Bit mask for DMA_HRS_HRS10.
+#define BS_DMA_HRS_HRS10     (1U)          //!< Bit field size in bits for DMA_HRS_HRS10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS10 field.
+#define BR_DMA_HRS_HRS10(x)  (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 11 is not present
+ * - 1 - A hardware service request for channel 11 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS11     (11U)         //!< Bit position for DMA_HRS_HRS11.
+#define BM_DMA_HRS_HRS11     (0x00000800U) //!< Bit mask for DMA_HRS_HRS11.
+#define BS_DMA_HRS_HRS11     (1U)          //!< Bit field size in bits for DMA_HRS_HRS11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS11 field.
+#define BR_DMA_HRS_HRS11(x)  (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 12 is not present
+ * - 1 - A hardware service request for channel 12 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS12     (12U)         //!< Bit position for DMA_HRS_HRS12.
+#define BM_DMA_HRS_HRS12     (0x00001000U) //!< Bit mask for DMA_HRS_HRS12.
+#define BS_DMA_HRS_HRS12     (1U)          //!< Bit field size in bits for DMA_HRS_HRS12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS12 field.
+#define BR_DMA_HRS_HRS12(x)  (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 13 is not present
+ * - 1 - A hardware service request for channel 13 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS13     (13U)         //!< Bit position for DMA_HRS_HRS13.
+#define BM_DMA_HRS_HRS13     (0x00002000U) //!< Bit mask for DMA_HRS_HRS13.
+#define BS_DMA_HRS_HRS13     (1U)          //!< Bit field size in bits for DMA_HRS_HRS13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS13 field.
+#define BR_DMA_HRS_HRS13(x)  (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 14 is not present
+ * - 1 - A hardware service request for channel 14 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS14     (14U)         //!< Bit position for DMA_HRS_HRS14.
+#define BM_DMA_HRS_HRS14     (0x00004000U) //!< Bit mask for DMA_HRS_HRS14.
+#define BS_DMA_HRS_HRS14     (1U)          //!< Bit field size in bits for DMA_HRS_HRS14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS14 field.
+#define BR_DMA_HRS_HRS14(x)  (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 15 is not present
+ * - 1 - A hardware service request for channel 15 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS15     (15U)         //!< Bit position for DMA_HRS_HRS15.
+#define BM_DMA_HRS_HRS15     (0x00008000U) //!< Bit mask for DMA_HRS_HRS15.
+#define BS_DMA_HRS_HRS15     (1U)          //!< Bit field size in bits for DMA_HRS_HRS15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS15 field.
+#define BR_DMA_HRS_HRS15(x)  (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_DCHPRIn - Channel n Priority Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+typedef union _hw_dma_dchprin
+{
+    uint8_t U;
+    struct _hw_dma_dchprin_bitfields
+    {
+        uint8_t CHPRI : 4;             //!< [3:0] Channel n Arbitration Priority
+        uint8_t RESERVED0 : 2;         //!< [5:4]
+        uint8_t DPA : 1;               //!< [6] Disable Preempt Ability
+        uint8_t ECP : 1;               //!< [7] Enable Channel Preemption
+    } B;
+} hw_dma_dchprin_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_DCHPRIn register
+ */
+//@{
+#define HW_DMA_DCHPRIn_COUNT (16U)
+
+#define HW_DMA_DCHPRIn_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100U + (0x1U * n))
+
+/* DMA channel index to DMA channel priority register array index conversion macro */
+#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_DCHPRIn(x, n)     (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
+#define HW_DMA_DCHPRIn_RD(x, n)  (HW_DMA_DCHPRIn(x, n).U)
+#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
+#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) |  (v)))
+#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
+#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_DCHPRIn bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+//@{
+#define BP_DMA_DCHPRIn_CHPRI (0U)          //!< Bit position for DMA_DCHPRIn_CHPRI.
+#define BM_DMA_DCHPRIn_CHPRI (0x0FU)       //!< Bit mask for DMA_DCHPRIn_CHPRI.
+#define BS_DMA_DCHPRIn_CHPRI (4U)          //!< Bit field size in bits for DMA_DCHPRIn_CHPRI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_DCHPRIn_CHPRI field.
+#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
+#endif
+
+//! @brief Format value for bitfield DMA_DCHPRIn_CHPRI.
+#define BF_DMA_DCHPRIn_CHPRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_CHPRI), uint8_t) & BM_DMA_DCHPRIn_CHPRI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHPRI field to a new value.
+#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_DCHPRIn, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0 - Channel n can suspend a lower priority channel
+ * - 1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+//@{
+#define BP_DMA_DCHPRIn_DPA   (6U)          //!< Bit position for DMA_DCHPRIn_DPA.
+#define BM_DMA_DCHPRIn_DPA   (0x40U)       //!< Bit mask for DMA_DCHPRIn_DPA.
+#define BS_DMA_DCHPRIn_DPA   (1U)          //!< Bit field size in bits for DMA_DCHPRIn_DPA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_DCHPRIn_DPA field.
+#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
+#endif
+
+//! @brief Format value for bitfield DMA_DCHPRIn_DPA.
+#define BF_DMA_DCHPRIn_DPA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_DPA), uint8_t) & BM_DMA_DCHPRIn_DPA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPA field to a new value.
+#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_DCHPRIn, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+//@{
+#define BP_DMA_DCHPRIn_ECP   (7U)          //!< Bit position for DMA_DCHPRIn_ECP.
+#define BM_DMA_DCHPRIn_ECP   (0x80U)       //!< Bit mask for DMA_DCHPRIn_ECP.
+#define BS_DMA_DCHPRIn_ECP   (1U)          //!< Bit field size in bits for DMA_DCHPRIn_ECP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_DCHPRIn_ECP field.
+#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
+#endif
+
+//! @brief Format value for bitfield DMA_DCHPRIn_ECP.
+#define BF_DMA_DCHPRIn_ECP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_ECP), uint8_t) & BM_DMA_DCHPRIn_ECP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ECP field to a new value.
+#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_SADDR - TCD Source Address
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_saddr
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_saddr_bitfields
+    {
+        uint32_t SADDR : 32;           //!< [31:0] Source Address
+    } B;
+} hw_dma_tcdn_saddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_SADDR register
+ */
+//@{
+#define HW_DMA_TCDn_SADDR_COUNT (16U)
+
+#define HW_DMA_TCDn_SADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1000U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_SADDR(x, n)  (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
+#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
+#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
+#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_SADDR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
+ *
+ * Memory address pointing to the source data.
+ */
+//@{
+#define BP_DMA_TCDn_SADDR_SADDR (0U)       //!< Bit position for DMA_TCDn_SADDR_SADDR.
+#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SADDR_SADDR.
+#define BS_DMA_TCDn_SADDR_SADDR (32U)      //!< Bit field size in bits for DMA_TCDn_SADDR_SADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_SADDR_SADDR field.
+#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR.
+#define BF_DMA_TCDn_SADDR_SADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SADDR_SADDR), uint32_t) & BM_DMA_TCDn_SADDR_SADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SADDR field to a new value.
+#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_soff
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_soff_bitfields
+    {
+        uint16_t SOFF : 16;            //!< [15:0] Source address signed offset
+    } B;
+} hw_dma_tcdn_soff_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_SOFF register
+ */
+//@{
+#define HW_DMA_TCDn_SOFF_COUNT (16U)
+
+#define HW_DMA_TCDn_SOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1004U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_SOFF(x, n)   (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
+#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
+#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
+#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_SOFF bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
+ *
+ * Sign-extended offset applied to the current source address to form the
+ * next-state value as each source read is completed.
+ */
+//@{
+#define BP_DMA_TCDn_SOFF_SOFF (0U)         //!< Bit position for DMA_TCDn_SOFF_SOFF.
+#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU)    //!< Bit mask for DMA_TCDn_SOFF_SOFF.
+#define BS_DMA_TCDn_SOFF_SOFF (16U)        //!< Bit field size in bits for DMA_TCDn_SOFF_SOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_SOFF_SOFF field.
+#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF.
+#define BF_DMA_TCDn_SOFF_SOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_SOFF_SOFF), uint16_t) & BM_DMA_TCDn_SOFF_SOFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFF field to a new value.
+#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_ATTR - TCD Transfer Attributes
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_attr
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_attr_bitfields
+    {
+        uint16_t DSIZE : 3;            //!< [2:0] Destination Data Transfer Size
+        uint16_t DMOD : 5;             //!< [7:3] Destination Address Modulo
+        uint16_t SSIZE : 3;            //!< [10:8] Source data transfer size
+        uint16_t SMOD : 5;             //!< [15:11] Source Address Modulo.
+    } B;
+} hw_dma_tcdn_attr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_ATTR register
+ */
+//@{
+#define HW_DMA_TCDn_ATTR_COUNT (16U)
+
+#define HW_DMA_TCDn_ATTR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1006U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_ATTR(x, n)   (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
+#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
+#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
+#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_DSIZE (0U)        //!< Bit position for DMA_TCDn_ATTR_DSIZE.
+#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U)   //!< Bit mask for DMA_TCDn_ATTR_DSIZE.
+#define BS_DMA_TCDn_ATTR_DSIZE (3U)        //!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field.
+#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE.
+#define BF_DMA_TCDn_ATTR_DSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DSIZE), uint16_t) & BM_DMA_TCDn_ATTR_DSIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DSIZE field to a new value.
+#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_DMOD (3U)         //!< Bit position for DMA_TCDn_ATTR_DMOD.
+#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U)    //!< Bit mask for DMA_TCDn_ATTR_DMOD.
+#define BS_DMA_TCDn_ATTR_DMOD (5U)         //!< Bit field size in bits for DMA_TCDn_ATTR_DMOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_DMOD field.
+#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD.
+#define BF_DMA_TCDn_ATTR_DMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DMOD), uint16_t) & BM_DMA_TCDn_ATTR_DMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMOD field to a new value.
+#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 000 - 8-bit
+ * - 001 - 16-bit
+ * - 010 - 32-bit
+ * - 011 - Reserved
+ * - 100 - 16-byte
+ * - 101 - 32-byte
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_SSIZE (8U)        //!< Bit position for DMA_TCDn_ATTR_SSIZE.
+#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U)   //!< Bit mask for DMA_TCDn_ATTR_SSIZE.
+#define BS_DMA_TCDn_ATTR_SSIZE (3U)        //!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field.
+#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE.
+#define BF_DMA_TCDn_ATTR_SSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SSIZE), uint16_t) & BM_DMA_TCDn_ATTR_SSIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSIZE field to a new value.
+#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0 - Source address modulo feature is disabled
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_SMOD (11U)        //!< Bit position for DMA_TCDn_ATTR_SMOD.
+#define BM_DMA_TCDn_ATTR_SMOD (0xF800U)    //!< Bit mask for DMA_TCDn_ATTR_SMOD.
+#define BS_DMA_TCDn_ATTR_SMOD (5U)         //!< Bit field size in bits for DMA_TCDn_ATTR_SMOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_SMOD field.
+#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD.
+#define BF_DMA_TCDn_ATTR_SMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SMOD), uint16_t) & BM_DMA_TCDn_ATTR_SMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMOD field to a new value.
+#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+typedef union _hw_dma_tcdn_nbytes_mlno
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_nbytes_mlno_bitfields
+    {
+        uint32_t NBYTES : 32;          //!< [31:0] Minor Byte Transfer Count
+    } B;
+} hw_dma_tcdn_nbytes_mlno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
+ */
+//@{
+#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
+
+#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
+#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
+#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
+#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
+ * GB transfer.
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES.
+#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES.
+#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field.
+#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES.
+#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NBYTES field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+typedef union _hw_dma_tcdn_nbytes_mloffno
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_nbytes_mloffno_bitfields
+    {
+        uint32_t NBYTES : 30;          //!< [29:0] Minor Byte Transfer Count
+        uint32_t DMLOE : 1;            //!< [30] Destination Minor Loop Offset enable
+        uint32_t SMLOE : 1;            //!< [31] Source Minor Loop Offset Enable
+    } B;
+} hw_dma_tcdn_nbytes_mloffno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
+ */
+//@{
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
+
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field.
+#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NBYTES field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the DADDR
+ * - 1 - The minor loop offset is applied to the DADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the SADDR
+ * - 1 - The minor loop offset is applied to the SADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+typedef union _hw_dma_tcdn_nbytes_mloffyes
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
+    {
+        uint32_t NBYTES : 10;          //!< [9:0] Minor Byte Transfer Count
+        uint32_t MLOFF : 20;           //!< [29:10] If SMLOE or DMLOE is set, this
+                                       //! field represents a sign-extended offset applied to the source or
+                                       //! destination address to form the next-state value after the minor loop completes.
+        uint32_t DMLOE : 1;            //!< [30] Destination Minor Loop Offset enable
+        uint32_t SMLOE : 1;            //!< [31] Source Minor Loop Offset Enable
+    } B;
+} hw_dma_tcdn_nbytes_mloffyes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
+ */
+//@{
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
+
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NBYTES field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MLOFF field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the DADDR
+ * - 1 - The minor loop offset is applied to the DADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the SADDR
+ * - 1 - The minor loop offset is applied to the SADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_slast
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_slast_bitfields
+    {
+        uint32_t SLAST : 32;           //!< [31:0] Last source Address Adjustment
+    } B;
+} hw_dma_tcdn_slast_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_SLAST register
+ */
+//@{
+#define HW_DMA_TCDn_SLAST_COUNT (16U)
+
+#define HW_DMA_TCDn_SLAST_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100CU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_SLAST(x, n)  (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
+#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
+#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
+#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_SLAST bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
+ *
+ * Adjustment value added to the source address at the completion of the major
+ * iteration count. This value can be applied to restore the source address to the
+ * initial value, or adjust the address to reference the next data structure.
+ * This register uses two's complement notation; the overflow bit is discarded.
+ */
+//@{
+#define BP_DMA_TCDn_SLAST_SLAST (0U)       //!< Bit position for DMA_TCDn_SLAST_SLAST.
+#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SLAST_SLAST.
+#define BS_DMA_TCDn_SLAST_SLAST (32U)      //!< Bit field size in bits for DMA_TCDn_SLAST_SLAST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_SLAST_SLAST field.
+#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST.
+#define BF_DMA_TCDn_SLAST_SLAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SLAST_SLAST), uint32_t) & BM_DMA_TCDn_SLAST_SLAST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLAST field to a new value.
+#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_DADDR - TCD Destination Address
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_daddr
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_daddr_bitfields
+    {
+        uint32_t DADDR : 32;           //!< [31:0] Destination Address
+    } B;
+} hw_dma_tcdn_daddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_DADDR register
+ */
+//@{
+#define HW_DMA_TCDn_DADDR_COUNT (16U)
+
+#define HW_DMA_TCDn_DADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1010U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_DADDR(x, n)  (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
+#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
+#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
+#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_DADDR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
+ *
+ * Memory address pointing to the destination data.
+ */
+//@{
+#define BP_DMA_TCDn_DADDR_DADDR (0U)       //!< Bit position for DMA_TCDn_DADDR_DADDR.
+#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DADDR_DADDR.
+#define BS_DMA_TCDn_DADDR_DADDR (32U)      //!< Bit field size in bits for DMA_TCDn_DADDR_DADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_DADDR_DADDR field.
+#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR.
+#define BF_DMA_TCDn_DADDR_DADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DADDR_DADDR), uint32_t) & BM_DMA_TCDn_DADDR_DADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DADDR field to a new value.
+#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_doff
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_doff_bitfields
+    {
+        uint16_t DOFF : 16;            //!< [15:0] Destination Address Signed offset
+    } B;
+} hw_dma_tcdn_doff_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_DOFF register
+ */
+//@{
+#define HW_DMA_TCDn_DOFF_COUNT (16U)
+
+#define HW_DMA_TCDn_DOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1014U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_DOFF(x, n)   (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
+#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
+#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
+#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_DOFF bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
+ *
+ * Sign-extended offset applied to the current destination address to form the
+ * next-state value as each destination write is completed.
+ */
+//@{
+#define BP_DMA_TCDn_DOFF_DOFF (0U)         //!< Bit position for DMA_TCDn_DOFF_DOFF.
+#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU)    //!< Bit mask for DMA_TCDn_DOFF_DOFF.
+#define BS_DMA_TCDn_DOFF_DOFF (16U)        //!< Bit field size in bits for DMA_TCDn_DOFF_DOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_DOFF_DOFF field.
+#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF.
+#define BF_DMA_TCDn_DOFF_DOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_DOFF_DOFF), uint16_t) & BM_DMA_TCDn_DOFF_DOFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DOFF field to a new value.
+#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+typedef union _hw_dma_tcdn_citer_elinkno
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_citer_elinkno_bitfields
+    {
+        uint16_t CITER : 15;           //!< [14:0] Current Major Iteration Count
+        uint16_t ELINK : 1;            //!< [15] Enable channel-to-channel linking on
+                                       //! minor-loop complete
+    } B;
+} hw_dma_tcdn_citer_elinkno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
+ */
+//@{
+#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
+
+#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
+#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
+#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
+#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER.
+#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER.
+#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field.
+#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER.
+#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CITER field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK.
+#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK.
+#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field.
+#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK.
+#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+typedef union _hw_dma_tcdn_citer_elinkyes
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_citer_elinkyes_bitfields
+    {
+        uint16_t CITER : 9;            //!< [8:0] Current Major Iteration Count
+        uint16_t LINKCH : 4;           //!< [12:9] Link Channel Number
+        uint16_t RESERVED0 : 2;        //!< [14:13]
+        uint16_t ELINK : 1;            //!< [15] Enable channel-to-channel linking on
+                                       //! minor-loop complete
+    } B;
+} hw_dma_tcdn_citer_elinkyes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
+ */
+//@{
+#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
+
+#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
+#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
+#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
+#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER.
+#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER.
+#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field.
+#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER.
+#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CITER field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH.
+#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH.
+#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field.
+#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH.
+#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINKCH field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK.
+#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK.
+#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field.
+#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK.
+#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_dlastsga
+{
+    uint32_t U;
+    struct _hw_dma_tcdn_dlastsga_bitfields
+    {
+        uint32_t DLASTSGA : 32;        //!< [31:0]
+    } B;
+} hw_dma_tcdn_dlastsga_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
+ */
+//@{
+#define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
+
+#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1018U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
+#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
+#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
+#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
+ *
+ * Destination last address adjustment or the memory address for the next
+ * transfer control descriptor to be loaded into this channel (scatter/gather). If
+ * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
+ * the completion of the major iteration count. This value can apply to restore the
+ * destination address to the initial value or adjust the address to reference
+ * the next data structure. This field uses two's complement notation for the
+ * final destination address adjustment. Otherwise: This address points to the
+ * beginning of a 0-modulo-32-byte region containing the next transfer control
+ * descriptor to be loaded into this channel. This channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be
+ * 0-modulo-32-byte, else a configuration error is reported.
+ */
+//@{
+#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) //!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA.
+#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA.
+#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) //!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field.
+#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA.
+#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DLASTSGA_DLASTSGA), uint32_t) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLASTSGA field to a new value.
+#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_CSR - TCD Control and Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_csr
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_csr_bitfields
+    {
+        uint16_t START : 1;            //!< [0] Channel Start
+        uint16_t INTMAJOR : 1;         //!< [1] Enable an interrupt when major
+                                       //! iteration count completes
+        uint16_t INTHALF : 1;          //!< [2] Enable an interrupt when major counter
+                                       //! is half complete.
+        uint16_t DREQ : 1;             //!< [3] Disable Request
+        uint16_t ESG : 1;              //!< [4] Enable Scatter/Gather Processing
+        uint16_t MAJORELINK : 1;       //!< [5] Enable channel-to-channel linking
+                                       //! on major loop complete
+        uint16_t ACTIVE : 1;           //!< [6] Channel Active
+        uint16_t DONE : 1;             //!< [7] Channel Done
+        uint16_t MAJORLINKCH : 4;      //!< [11:8] Link Channel Number
+        uint16_t RESERVED0 : 2;        //!< [13:12]
+        uint16_t BWC : 2;              //!< [15:14] Bandwidth Control
+    } B;
+} hw_dma_tcdn_csr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_CSR register
+ */
+//@{
+#define HW_DMA_TCDn_CSR_COUNT (16U)
+
+#define HW_DMA_TCDn_CSR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101CU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_CSR(x, n)    (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
+#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
+#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
+#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0 - The channel is not explicitly started
+ * - 1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+//@{
+#define BP_DMA_TCDn_CSR_START (0U)         //!< Bit position for DMA_TCDn_CSR_START.
+#define BM_DMA_TCDn_CSR_START (0x0001U)    //!< Bit mask for DMA_TCDn_CSR_START.
+#define BS_DMA_TCDn_CSR_START (1U)         //!< Bit field size in bits for DMA_TCDn_CSR_START.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_START field.
+#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_START.
+#define BF_DMA_TCDn_CSR_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_START), uint16_t) & BM_DMA_TCDn_CSR_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the START field to a new value.
+#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0 - The end-of-major loop interrupt is disabled
+ * - 1 - The end-of-major loop interrupt is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CSR_INTMAJOR (1U)      //!< Bit position for DMA_TCDn_CSR_INTMAJOR.
+#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) //!< Bit mask for DMA_TCDn_CSR_INTMAJOR.
+#define BS_DMA_TCDn_CSR_INTMAJOR (1U)      //!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field.
+#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR.
+#define BF_DMA_TCDn_CSR_INTMAJOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTMAJOR), uint16_t) & BM_DMA_TCDn_CSR_INTMAJOR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTMAJOR field to a new value.
+#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0 - The half-point interrupt is disabled
+ * - 1 - The half-point interrupt is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CSR_INTHALF (2U)       //!< Bit position for DMA_TCDn_CSR_INTHALF.
+#define BM_DMA_TCDn_CSR_INTHALF (0x0004U)  //!< Bit mask for DMA_TCDn_CSR_INTHALF.
+#define BS_DMA_TCDn_CSR_INTHALF (1U)       //!< Bit field size in bits for DMA_TCDn_CSR_INTHALF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_INTHALF field.
+#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF.
+#define BF_DMA_TCDn_CSR_INTHALF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTHALF), uint16_t) & BM_DMA_TCDn_CSR_INTHALF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTHALF field to a new value.
+#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0 - The channel's ERQ bit is not affected
+ * - 1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+//@{
+#define BP_DMA_TCDn_CSR_DREQ (3U)          //!< Bit position for DMA_TCDn_CSR_DREQ.
+#define BM_DMA_TCDn_CSR_DREQ (0x0008U)     //!< Bit mask for DMA_TCDn_CSR_DREQ.
+#define BS_DMA_TCDn_CSR_DREQ (1U)          //!< Bit field size in bits for DMA_TCDn_CSR_DREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_DREQ field.
+#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_DREQ.
+#define BF_DMA_TCDn_CSR_DREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DREQ), uint16_t) & BM_DMA_TCDn_CSR_DREQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DREQ field to a new value.
+#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0 - The current channel's TCD is normal format.
+ * - 1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
+ *     channel after the major loop completes its execution.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_ESG  (4U)          //!< Bit position for DMA_TCDn_CSR_ESG.
+#define BM_DMA_TCDn_CSR_ESG  (0x0010U)     //!< Bit mask for DMA_TCDn_CSR_ESG.
+#define BS_DMA_TCDn_CSR_ESG  (1U)          //!< Bit field size in bits for DMA_TCDn_CSR_ESG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_ESG field.
+#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_ESG.
+#define BF_DMA_TCDn_CSR_ESG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ESG), uint16_t) & BM_DMA_TCDn_CSR_ESG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ESG field to a new value.
+#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CSR_MAJORELINK (5U)    //!< Bit position for DMA_TCDn_CSR_MAJORELINK.
+#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) //!< Bit mask for DMA_TCDn_CSR_MAJORELINK.
+#define BS_DMA_TCDn_CSR_MAJORELINK (1U)    //!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field.
+#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK.
+#define BF_DMA_TCDn_CSR_MAJORELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORELINK), uint16_t) & BM_DMA_TCDn_CSR_MAJORELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAJORELINK field to a new value.
+#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_ACTIVE (6U)        //!< Bit position for DMA_TCDn_CSR_ACTIVE.
+#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U)   //!< Bit mask for DMA_TCDn_CSR_ACTIVE.
+#define BS_DMA_TCDn_CSR_ACTIVE (1U)        //!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field.
+#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE.
+#define BF_DMA_TCDn_CSR_ACTIVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ACTIVE), uint16_t) & BM_DMA_TCDn_CSR_ACTIVE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACTIVE field to a new value.
+#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_DONE (7U)          //!< Bit position for DMA_TCDn_CSR_DONE.
+#define BM_DMA_TCDn_CSR_DONE (0x0080U)     //!< Bit mask for DMA_TCDn_CSR_DONE.
+#define BS_DMA_TCDn_CSR_DONE (1U)          //!< Bit field size in bits for DMA_TCDn_CSR_DONE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_DONE field.
+#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_DONE.
+#define BF_DMA_TCDn_CSR_DONE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DONE), uint16_t) & BM_DMA_TCDn_CSR_DONE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DONE field to a new value.
+#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U)   //!< Bit position for DMA_TCDn_CSR_MAJORLINKCH.
+#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) //!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH.
+#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U)   //!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field.
+#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH.
+#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORLINKCH), uint16_t) & BM_DMA_TCDn_CSR_MAJORLINKCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAJORLINKCH field to a new value.
+#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 00 - No eDMA engine stalls
+ * - 01 - Reserved
+ * - 10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+//@{
+#define BP_DMA_TCDn_CSR_BWC  (14U)         //!< Bit position for DMA_TCDn_CSR_BWC.
+#define BM_DMA_TCDn_CSR_BWC  (0xC000U)     //!< Bit mask for DMA_TCDn_CSR_BWC.
+#define BS_DMA_TCDn_CSR_BWC  (2U)          //!< Bit field size in bits for DMA_TCDn_CSR_BWC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_BWC field.
+#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_BWC.
+#define BF_DMA_TCDn_CSR_BWC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_BWC), uint16_t) & BM_DMA_TCDn_CSR_BWC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWC field to a new value.
+#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+typedef union _hw_dma_tcdn_biter_elinkno
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_biter_elinkno_bitfields
+    {
+        uint16_t BITER : 15;           //!< [14:0] Starting Major Iteration Count
+        uint16_t ELINK : 1;            //!< [15] Enables channel-to-channel linking on
+                                       //! minor loop complete
+    } B;
+} hw_dma_tcdn_biter_elinkno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
+ */
+//@{
+#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
+
+#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
+#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
+#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
+#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER.
+#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER.
+#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field.
+#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER.
+#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BITER field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK.
+#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK.
+#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field.
+#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK.
+#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+typedef union _hw_dma_tcdn_biter_elinkyes
+{
+    uint16_t U;
+    struct _hw_dma_tcdn_biter_elinkyes_bitfields
+    {
+        uint16_t BITER : 9;            //!< [8:0] Starting Major Iteration Count
+        uint16_t LINKCH : 4;           //!< [12:9] Link Channel Number
+        uint16_t RESERVED0 : 2;        //!< [14:13]
+        uint16_t ELINK : 1;            //!< [15] Enables channel-to-channel linking on
+                                       //! minor loop complete
+    } B;
+} hw_dma_tcdn_biter_elinkyes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
+ */
+//@{
+#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
+
+#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
+#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
+#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
+#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) |  (v)))
+#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER.
+#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER.
+#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field.
+#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER.
+#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BITER field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH.
+#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH.
+#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field.
+#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH.
+#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINKCH field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK.
+#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK.
+#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field.
+#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK.
+#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_dma_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All DMA module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_dma
+{
+    __IO hw_dma_cr_t CR;                   //!< [0x0] Control Register
+    __I hw_dma_es_t ES;                    //!< [0x4] Error Status Register
+    uint8_t _reserved0[4];
+    __IO hw_dma_erq_t ERQ;                 //!< [0xC] Enable Request Register
+    uint8_t _reserved1[4];
+    __IO hw_dma_eei_t EEI;                 //!< [0x14] Enable Error Interrupt Register
+    __O hw_dma_ceei_t CEEI;                //!< [0x18] Clear Enable Error Interrupt Register
+    __O hw_dma_seei_t SEEI;                //!< [0x19] Set Enable Error Interrupt Register
+    __O hw_dma_cerq_t CERQ;                //!< [0x1A] Clear Enable Request Register
+    __O hw_dma_serq_t SERQ;                //!< [0x1B] Set Enable Request Register
+    __O hw_dma_cdne_t CDNE;                //!< [0x1C] Clear DONE Status Bit Register
+    __O hw_dma_ssrt_t SSRT;                //!< [0x1D] Set START Bit Register
+    __O hw_dma_cerr_t CERR;                //!< [0x1E] Clear Error Register
+    __O hw_dma_cint_t CINT;                //!< [0x1F] Clear Interrupt Request Register
+    uint8_t _reserved2[4];
+    __IO hw_dma_int_t INT;                 //!< [0x24] Interrupt Request Register
+    uint8_t _reserved3[4];
+    __IO hw_dma_err_t ERR;                 //!< [0x2C] Error Register
+    uint8_t _reserved4[4];
+    __I hw_dma_hrs_t HRS;                  //!< [0x34] Hardware Request Status Register
+    uint8_t _reserved5[200];
+    __IO hw_dma_dchprin_t DCHPRIn[16];     //!< [0x100] Channel n Priority Register
+    uint8_t _reserved6[3824];
+    struct {
+        __IO hw_dma_tcdn_saddr_t TCDn_SADDR; //!< [0x1000] TCD Source Address
+        __IO hw_dma_tcdn_soff_t TCDn_SOFF; //!< [0x1004] TCD Signed Source Address Offset
+        __IO hw_dma_tcdn_attr_t TCDn_ATTR; //!< [0x1006] TCD Transfer Attributes
+        union {
+            __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; //!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled)
+            __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+            __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+        };
+        __IO hw_dma_tcdn_slast_t TCDn_SLAST; //!< [0x100C] TCD Last Source Address Adjustment
+        __IO hw_dma_tcdn_daddr_t TCDn_DADDR; //!< [0x1010] TCD Destination Address
+        __IO hw_dma_tcdn_doff_t TCDn_DOFF; //!< [0x1014] TCD Signed Destination Address Offset
+        union {
+            __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+            __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+        };
+        __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; //!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address
+        __IO hw_dma_tcdn_csr_t TCDn_CSR;   //!< [0x101C] TCD Control and Status
+        union {
+            __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+            __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+        };
+    } TCD[16];
+} hw_dma_t;
+#pragma pack()
+
+//! @brief Macro to access all DMA registers.
+//! @param x DMA instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_DMA(0)</code>.
+#define HW_DMA(x)      (*(hw_dma_t *) REGS_DMA_BASE(x))
+#endif
+
+#endif // __HW_DMA_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h
new file mode 100644
index 0000000000..858512195d
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_DMAMUX_REGISTERS_H__
+#define __HW_DMAMUX_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - HW_DMAMUX_CHCFGn - Channel Configuration register
+ *
+ * - hw_dmamux_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_DMAMUX_BASE
+#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
+#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
+#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
+
+//! @brief Table of base addresses for DMAMUX instances.
+static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
+        REGS_DMAMUX0_BASE,
+    };
+
+//! @brief Get the base address of DMAMUX by instance number.
+//! @param x DMAMUX instance number, from 0 through 0.
+#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of DMAMUX.
+#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMAMUX_CHCFGn - Channel Configuration register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+typedef union _hw_dmamux_chcfgn
+{
+    uint8_t U;
+    struct _hw_dmamux_chcfgn_bitfields
+    {
+        uint8_t SOURCE : 6;            //!< [5:0] DMA Channel Source (Slot)
+        uint8_t TRIG : 1;              //!< [6] DMA Channel Trigger Enable
+        uint8_t ENBL : 1;              //!< [7] DMA Channel Enable
+    } B;
+} hw_dmamux_chcfgn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFGn register
+ */
+//@{
+#define HW_DMAMUX_CHCFGn_COUNT (16U)
+
+#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMAMUX_CHCFGn(x, n)   (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
+#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
+#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
+#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) |  (v)))
+#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
+#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFGn bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+//@{
+#define BP_DMAMUX_CHCFGn_SOURCE (0U)       //!< Bit position for DMAMUX_CHCFGn_SOURCE.
+#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU)    //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
+#define BS_DMAMUX_CHCFGn_SOURCE (6U)       //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
+#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
+#endif
+
+//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
+#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOURCE field to a new value.
+#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
+ *     DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+//@{
+#define BP_DMAMUX_CHCFGn_TRIG (6U)         //!< Bit position for DMAMUX_CHCFGn_TRIG.
+#define BM_DMAMUX_CHCFGn_TRIG (0x40U)      //!< Bit mask for DMAMUX_CHCFGn_TRIG.
+#define BS_DMAMUX_CHCFGn_TRIG (1U)         //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
+#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
+#endif
+
+//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
+#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG field to a new value.
+#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 1 - DMA channel is enabled
+ */
+//@{
+#define BP_DMAMUX_CHCFGn_ENBL (7U)         //!< Bit position for DMAMUX_CHCFGn_ENBL.
+#define BM_DMAMUX_CHCFGn_ENBL (0x80U)      //!< Bit mask for DMAMUX_CHCFGn_ENBL.
+#define BS_DMAMUX_CHCFGn_ENBL (1U)         //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
+#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
+#endif
+
+//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
+#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENBL field to a new value.
+#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_dmamux_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All DMAMUX module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_dmamux
+{
+    __IO hw_dmamux_chcfgn_t CHCFGn[16];    //!< [0x0] Channel Configuration register
+} hw_dmamux_t;
+#pragma pack()
+
+//! @brief Macro to access all DMAMUX registers.
+//! @param x DMAMUX instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
+#define HW_DMAMUX(x)   (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
+#endif
+
+#endif // __HW_DMAMUX_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h
new file mode 100644
index 0000000000..804a2f4558
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h
@@ -0,0 +1,8441 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_ENET_REGISTERS_H__
+#define __HW_ENET_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - HW_ENET_EIR - Interrupt Event Register
+ * - HW_ENET_EIMR - Interrupt Mask Register
+ * - HW_ENET_RDAR - Receive Descriptor Active Register
+ * - HW_ENET_TDAR - Transmit Descriptor Active Register
+ * - HW_ENET_ECR - Ethernet Control Register
+ * - HW_ENET_MMFR - MII Management Frame Register
+ * - HW_ENET_MSCR - MII Speed Control Register
+ * - HW_ENET_MIBC - MIB Control Register
+ * - HW_ENET_RCR - Receive Control Register
+ * - HW_ENET_TCR - Transmit Control Register
+ * - HW_ENET_PALR - Physical Address Lower Register
+ * - HW_ENET_PAUR - Physical Address Upper Register
+ * - HW_ENET_OPD - Opcode/Pause Duration Register
+ * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
+ * - HW_ENET_IALR - Descriptor Individual Lower Address Register
+ * - HW_ENET_GAUR - Descriptor Group Upper Address Register
+ * - HW_ENET_GALR - Descriptor Group Lower Address Register
+ * - HW_ENET_TFWR - Transmit FIFO Watermark Register
+ * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
+ * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
+ * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
+ * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - HW_ENET_TIPG - Transmit Inter-Packet Gap
+ * - HW_ENET_FTRL - Frame Truncation Length
+ * - HW_ENET_TACC - Transmit Accelerator Function Configuration
+ * - HW_ENET_RACC - Receive Accelerator Function Configuration
+ * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - HW_ENET_ATCR - Adjustable Timer Control Register
+ * - HW_ENET_ATVR - Timer Value Register
+ * - HW_ENET_ATOFF - Timer Offset Register
+ * - HW_ENET_ATPER - Timer Period Register
+ * - HW_ENET_ATCOR - Timer Correction Register
+ * - HW_ENET_ATINC - Time-Stamping Clock Period Register
+ * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - HW_ENET_TGSR - Timer Global Status Register
+ * - HW_ENET_TCSRn - Timer Control Status Register
+ * - HW_ENET_TCCRn - Timer Compare Capture Register
+ *
+ * - hw_enet_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_ENET_BASE
+#define HW_ENET_INSTANCE_COUNT (1U) //!< Number of instances of the ENET module.
+#define HW_ENET0 (0U) //!< Instance number for ENET.
+#define REGS_ENET0_BASE (0x400C0000U) //!< Base address for ENET.
+
+//! @brief Table of base addresses for ENET instances.
+static const uint32_t __g_regs_ENET_base_addresses[] = {
+        REGS_ENET0_BASE,
+    };
+
+//! @brief Get the base address of ENET by instance number.
+//! @param x ENET instance number, from 0 through 0.
+#define REGS_ENET_BASE(x) (__g_regs_ENET_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of ENET.
+#define REGS_ENET_INSTANCE(b) ((b) == REGS_ENET0_BASE ? HW_ENET0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_EIR - Interrupt Event Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+typedef union _hw_enet_eir
+{
+    uint32_t U;
+    struct _hw_enet_eir_bitfields
+    {
+        uint32_t RESERVED0 : 15;       //!< [14:0]
+        uint32_t TS_TIMER : 1;         //!< [15] Timestamp Timer
+        uint32_t TS_AVAIL : 1;         //!< [16] Transmit Timestamp Available
+        uint32_t WAKEUP : 1;           //!< [17] Node Wakeup Request Indication
+        uint32_t PLR : 1;              //!< [18] Payload Receive Error
+        uint32_t UN : 1;               //!< [19] Transmit FIFO Underrun
+        uint32_t RL : 1;               //!< [20] Collision Retry Limit
+        uint32_t LC : 1;               //!< [21] Late Collision
+        uint32_t EBERR : 1;            //!< [22] Ethernet Bus Error
+        uint32_t MII : 1;              //!< [23] MII Interrupt.
+        uint32_t RXB : 1;              //!< [24] Receive Buffer Interrupt
+        uint32_t RXF : 1;              //!< [25] Receive Frame Interrupt
+        uint32_t TXB : 1;              //!< [26] Transmit Buffer Interrupt
+        uint32_t TXF : 1;              //!< [27] Transmit Frame Interrupt
+        uint32_t GRA : 1;              //!< [28] Graceful Stop Complete
+        uint32_t BABT : 1;             //!< [29] Babbling Transmit Error
+        uint32_t BABR : 1;             //!< [30] Babbling Receive Error
+        uint32_t RESERVED1 : 1;        //!< [31]
+    } B;
+} hw_enet_eir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+//@{
+#define HW_ENET_EIR_ADDR(x)      (REGS_ENET_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_EIR(x)           (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
+#define HW_ENET_EIR_RD(x)        (HW_ENET_EIR(x).U)
+#define HW_ENET_EIR_WR(x, v)     (HW_ENET_EIR(x).U = (v))
+#define HW_ENET_EIR_SET(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) |  (v)))
+#define HW_ENET_EIR_CLR(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
+#define HW_ENET_EIR_TOG(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+//@{
+#define BP_ENET_EIR_TS_TIMER (15U)         //!< Bit position for ENET_EIR_TS_TIMER.
+#define BM_ENET_EIR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIR_TS_TIMER.
+#define BS_ENET_EIR_TS_TIMER (1U)          //!< Bit field size in bits for ENET_EIR_TS_TIMER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TS_TIMER field.
+#define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TS_TIMER.
+#define BF_ENET_EIR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_TIMER), uint32_t) & BM_ENET_EIR_TS_TIMER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_TIMER field to a new value.
+#define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+//@{
+#define BP_ENET_EIR_TS_AVAIL (16U)         //!< Bit position for ENET_EIR_TS_AVAIL.
+#define BM_ENET_EIR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIR_TS_AVAIL.
+#define BS_ENET_EIR_TS_AVAIL (1U)          //!< Bit field size in bits for ENET_EIR_TS_AVAIL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TS_AVAIL field.
+#define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TS_AVAIL.
+#define BF_ENET_EIR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_AVAIL), uint32_t) & BM_ENET_EIR_TS_AVAIL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_AVAIL field to a new value.
+#define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+//@{
+#define BP_ENET_EIR_WAKEUP   (17U)         //!< Bit position for ENET_EIR_WAKEUP.
+#define BM_ENET_EIR_WAKEUP   (0x00020000U) //!< Bit mask for ENET_EIR_WAKEUP.
+#define BS_ENET_EIR_WAKEUP   (1U)          //!< Bit field size in bits for ENET_EIR_WAKEUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_WAKEUP field.
+#define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_WAKEUP.
+#define BF_ENET_EIR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_WAKEUP), uint32_t) & BM_ENET_EIR_WAKEUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKEUP field to a new value.
+#define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+//@{
+#define BP_ENET_EIR_PLR      (18U)         //!< Bit position for ENET_EIR_PLR.
+#define BM_ENET_EIR_PLR      (0x00040000U) //!< Bit mask for ENET_EIR_PLR.
+#define BS_ENET_EIR_PLR      (1U)          //!< Bit field size in bits for ENET_EIR_PLR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_PLR field.
+#define BR_ENET_EIR_PLR(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_PLR.
+#define BF_ENET_EIR_PLR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_PLR), uint32_t) & BM_ENET_EIR_PLR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLR field to a new value.
+#define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+//@{
+#define BP_ENET_EIR_UN       (19U)         //!< Bit position for ENET_EIR_UN.
+#define BM_ENET_EIR_UN       (0x00080000U) //!< Bit mask for ENET_EIR_UN.
+#define BS_ENET_EIR_UN       (1U)          //!< Bit field size in bits for ENET_EIR_UN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_UN field.
+#define BR_ENET_EIR_UN(x)    (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_UN.
+#define BF_ENET_EIR_UN(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_UN), uint32_t) & BM_ENET_EIR_UN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UN field to a new value.
+#define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+//@{
+#define BP_ENET_EIR_RL       (20U)         //!< Bit position for ENET_EIR_RL.
+#define BM_ENET_EIR_RL       (0x00100000U) //!< Bit mask for ENET_EIR_RL.
+#define BS_ENET_EIR_RL       (1U)          //!< Bit field size in bits for ENET_EIR_RL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_RL field.
+#define BR_ENET_EIR_RL(x)    (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_RL.
+#define BF_ENET_EIR_RL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RL), uint32_t) & BM_ENET_EIR_RL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RL field to a new value.
+#define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+//@{
+#define BP_ENET_EIR_LC       (21U)         //!< Bit position for ENET_EIR_LC.
+#define BM_ENET_EIR_LC       (0x00200000U) //!< Bit mask for ENET_EIR_LC.
+#define BS_ENET_EIR_LC       (1U)          //!< Bit field size in bits for ENET_EIR_LC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_LC field.
+#define BR_ENET_EIR_LC(x)    (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_LC.
+#define BF_ENET_EIR_LC(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_LC), uint32_t) & BM_ENET_EIR_LC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LC field to a new value.
+#define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+//@{
+#define BP_ENET_EIR_EBERR    (22U)         //!< Bit position for ENET_EIR_EBERR.
+#define BM_ENET_EIR_EBERR    (0x00400000U) //!< Bit mask for ENET_EIR_EBERR.
+#define BS_ENET_EIR_EBERR    (1U)          //!< Bit field size in bits for ENET_EIR_EBERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_EBERR field.
+#define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_EBERR.
+#define BF_ENET_EIR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_EBERR), uint32_t) & BM_ENET_EIR_EBERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EBERR field to a new value.
+#define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+//@{
+#define BP_ENET_EIR_MII      (23U)         //!< Bit position for ENET_EIR_MII.
+#define BM_ENET_EIR_MII      (0x00800000U) //!< Bit mask for ENET_EIR_MII.
+#define BS_ENET_EIR_MII      (1U)          //!< Bit field size in bits for ENET_EIR_MII.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_MII field.
+#define BR_ENET_EIR_MII(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_MII.
+#define BF_ENET_EIR_MII(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_MII), uint32_t) & BM_ENET_EIR_MII)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII field to a new value.
+#define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+//@{
+#define BP_ENET_EIR_RXB      (24U)         //!< Bit position for ENET_EIR_RXB.
+#define BM_ENET_EIR_RXB      (0x01000000U) //!< Bit mask for ENET_EIR_RXB.
+#define BS_ENET_EIR_RXB      (1U)          //!< Bit field size in bits for ENET_EIR_RXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_RXB field.
+#define BR_ENET_EIR_RXB(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_RXB.
+#define BF_ENET_EIR_RXB(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXB), uint32_t) & BM_ENET_EIR_RXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXB field to a new value.
+#define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+//@{
+#define BP_ENET_EIR_RXF      (25U)         //!< Bit position for ENET_EIR_RXF.
+#define BM_ENET_EIR_RXF      (0x02000000U) //!< Bit mask for ENET_EIR_RXF.
+#define BS_ENET_EIR_RXF      (1U)          //!< Bit field size in bits for ENET_EIR_RXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_RXF field.
+#define BR_ENET_EIR_RXF(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_RXF.
+#define BF_ENET_EIR_RXF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXF), uint32_t) & BM_ENET_EIR_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXF field to a new value.
+#define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+//@{
+#define BP_ENET_EIR_TXB      (26U)         //!< Bit position for ENET_EIR_TXB.
+#define BM_ENET_EIR_TXB      (0x04000000U) //!< Bit mask for ENET_EIR_TXB.
+#define BS_ENET_EIR_TXB      (1U)          //!< Bit field size in bits for ENET_EIR_TXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TXB field.
+#define BR_ENET_EIR_TXB(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TXB.
+#define BF_ENET_EIR_TXB(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXB), uint32_t) & BM_ENET_EIR_TXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXB field to a new value.
+#define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+//@{
+#define BP_ENET_EIR_TXF      (27U)         //!< Bit position for ENET_EIR_TXF.
+#define BM_ENET_EIR_TXF      (0x08000000U) //!< Bit mask for ENET_EIR_TXF.
+#define BS_ENET_EIR_TXF      (1U)          //!< Bit field size in bits for ENET_EIR_TXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TXF field.
+#define BR_ENET_EIR_TXF(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TXF.
+#define BF_ENET_EIR_TXF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXF), uint32_t) & BM_ENET_EIR_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXF field to a new value.
+#define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+//@{
+#define BP_ENET_EIR_GRA      (28U)         //!< Bit position for ENET_EIR_GRA.
+#define BM_ENET_EIR_GRA      (0x10000000U) //!< Bit mask for ENET_EIR_GRA.
+#define BS_ENET_EIR_GRA      (1U)          //!< Bit field size in bits for ENET_EIR_GRA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_GRA field.
+#define BR_ENET_EIR_GRA(x)   (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_GRA.
+#define BF_ENET_EIR_GRA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_GRA), uint32_t) & BM_ENET_EIR_GRA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GRA field to a new value.
+#define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+//@{
+#define BP_ENET_EIR_BABT     (29U)         //!< Bit position for ENET_EIR_BABT.
+#define BM_ENET_EIR_BABT     (0x20000000U) //!< Bit mask for ENET_EIR_BABT.
+#define BS_ENET_EIR_BABT     (1U)          //!< Bit field size in bits for ENET_EIR_BABT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_BABT field.
+#define BR_ENET_EIR_BABT(x)  (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_BABT.
+#define BF_ENET_EIR_BABT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABT), uint32_t) & BM_ENET_EIR_BABT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABT field to a new value.
+#define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+//@{
+#define BP_ENET_EIR_BABR     (30U)         //!< Bit position for ENET_EIR_BABR.
+#define BM_ENET_EIR_BABR     (0x40000000U) //!< Bit mask for ENET_EIR_BABR.
+#define BS_ENET_EIR_BABR     (1U)          //!< Bit field size in bits for ENET_EIR_BABR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_BABR field.
+#define BR_ENET_EIR_BABR(x)  (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_BABR.
+#define BF_ENET_EIR_BABR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABR), uint32_t) & BM_ENET_EIR_BABR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABR field to a new value.
+#define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_EIMR - Interrupt Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+typedef union _hw_enet_eimr
+{
+    uint32_t U;
+    struct _hw_enet_eimr_bitfields
+    {
+        uint32_t RESERVED0 : 15;       //!< [14:0]
+        uint32_t TS_TIMER : 1;         //!< [15] TS_TIMER Interrupt Mask
+        uint32_t TS_AVAIL : 1;         //!< [16] TS_AVAIL Interrupt Mask
+        uint32_t WAKEUP : 1;           //!< [17] WAKEUP Interrupt Mask
+        uint32_t PLR : 1;              //!< [18] PLR Interrupt Mask
+        uint32_t UN : 1;               //!< [19] UN Interrupt Mask
+        uint32_t RL : 1;               //!< [20] RL Interrupt Mask
+        uint32_t LC : 1;               //!< [21] LC Interrupt Mask
+        uint32_t EBERR : 1;            //!< [22] EBERR Interrupt Mask
+        uint32_t MII : 1;              //!< [23] MII Interrupt Mask
+        uint32_t RXB : 1;              //!< [24] RXB Interrupt Mask
+        uint32_t RXF : 1;              //!< [25] RXF Interrupt Mask
+        uint32_t TXB : 1;              //!< [26] TXB Interrupt Mask
+        uint32_t TXF : 1;              //!< [27] TXF Interrupt Mask
+        uint32_t GRA : 1;              //!< [28] GRA Interrupt Mask
+        uint32_t BABT : 1;             //!< [29] BABT Interrupt Mask
+        uint32_t BABR : 1;             //!< [30] BABR Interrupt Mask
+        uint32_t RESERVED1 : 1;        //!< [31]
+    } B;
+} hw_enet_eimr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+//@{
+#define HW_ENET_EIMR_ADDR(x)     (REGS_ENET_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_EIMR(x)          (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
+#define HW_ENET_EIMR_RD(x)       (HW_ENET_EIMR(x).U)
+#define HW_ENET_EIMR_WR(x, v)    (HW_ENET_EIMR(x).U = (v))
+#define HW_ENET_EIMR_SET(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) |  (v)))
+#define HW_ENET_EIMR_CLR(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
+#define HW_ENET_EIMR_TOG(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_TS_TIMER (15U)        //!< Bit position for ENET_EIMR_TS_TIMER.
+#define BM_ENET_EIMR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIMR_TS_TIMER.
+#define BS_ENET_EIMR_TS_TIMER (1U)         //!< Bit field size in bits for ENET_EIMR_TS_TIMER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TS_TIMER field.
+#define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TS_TIMER.
+#define BF_ENET_EIMR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_TIMER), uint32_t) & BM_ENET_EIMR_TS_TIMER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_TIMER field to a new value.
+#define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_TS_AVAIL (16U)        //!< Bit position for ENET_EIMR_TS_AVAIL.
+#define BM_ENET_EIMR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIMR_TS_AVAIL.
+#define BS_ENET_EIMR_TS_AVAIL (1U)         //!< Bit field size in bits for ENET_EIMR_TS_AVAIL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TS_AVAIL field.
+#define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TS_AVAIL.
+#define BF_ENET_EIMR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_AVAIL), uint32_t) & BM_ENET_EIMR_TS_AVAIL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_AVAIL field to a new value.
+#define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_WAKEUP  (17U)         //!< Bit position for ENET_EIMR_WAKEUP.
+#define BM_ENET_EIMR_WAKEUP  (0x00020000U) //!< Bit mask for ENET_EIMR_WAKEUP.
+#define BS_ENET_EIMR_WAKEUP  (1U)          //!< Bit field size in bits for ENET_EIMR_WAKEUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_WAKEUP field.
+#define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_WAKEUP.
+#define BF_ENET_EIMR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_WAKEUP), uint32_t) & BM_ENET_EIMR_WAKEUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKEUP field to a new value.
+#define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_PLR     (18U)         //!< Bit position for ENET_EIMR_PLR.
+#define BM_ENET_EIMR_PLR     (0x00040000U) //!< Bit mask for ENET_EIMR_PLR.
+#define BS_ENET_EIMR_PLR     (1U)          //!< Bit field size in bits for ENET_EIMR_PLR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_PLR field.
+#define BR_ENET_EIMR_PLR(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_PLR.
+#define BF_ENET_EIMR_PLR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_PLR), uint32_t) & BM_ENET_EIMR_PLR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLR field to a new value.
+#define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_UN      (19U)         //!< Bit position for ENET_EIMR_UN.
+#define BM_ENET_EIMR_UN      (0x00080000U) //!< Bit mask for ENET_EIMR_UN.
+#define BS_ENET_EIMR_UN      (1U)          //!< Bit field size in bits for ENET_EIMR_UN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_UN field.
+#define BR_ENET_EIMR_UN(x)   (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_UN.
+#define BF_ENET_EIMR_UN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_UN), uint32_t) & BM_ENET_EIMR_UN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UN field to a new value.
+#define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_RL      (20U)         //!< Bit position for ENET_EIMR_RL.
+#define BM_ENET_EIMR_RL      (0x00100000U) //!< Bit mask for ENET_EIMR_RL.
+#define BS_ENET_EIMR_RL      (1U)          //!< Bit field size in bits for ENET_EIMR_RL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_RL field.
+#define BR_ENET_EIMR_RL(x)   (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_RL.
+#define BF_ENET_EIMR_RL(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RL), uint32_t) & BM_ENET_EIMR_RL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RL field to a new value.
+#define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_LC      (21U)         //!< Bit position for ENET_EIMR_LC.
+#define BM_ENET_EIMR_LC      (0x00200000U) //!< Bit mask for ENET_EIMR_LC.
+#define BS_ENET_EIMR_LC      (1U)          //!< Bit field size in bits for ENET_EIMR_LC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_LC field.
+#define BR_ENET_EIMR_LC(x)   (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_LC.
+#define BF_ENET_EIMR_LC(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_LC), uint32_t) & BM_ENET_EIMR_LC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LC field to a new value.
+#define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_EBERR   (22U)         //!< Bit position for ENET_EIMR_EBERR.
+#define BM_ENET_EIMR_EBERR   (0x00400000U) //!< Bit mask for ENET_EIMR_EBERR.
+#define BS_ENET_EIMR_EBERR   (1U)          //!< Bit field size in bits for ENET_EIMR_EBERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_EBERR field.
+#define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_EBERR.
+#define BF_ENET_EIMR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_EBERR), uint32_t) & BM_ENET_EIMR_EBERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EBERR field to a new value.
+#define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_MII     (23U)         //!< Bit position for ENET_EIMR_MII.
+#define BM_ENET_EIMR_MII     (0x00800000U) //!< Bit mask for ENET_EIMR_MII.
+#define BS_ENET_EIMR_MII     (1U)          //!< Bit field size in bits for ENET_EIMR_MII.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_MII field.
+#define BR_ENET_EIMR_MII(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_MII.
+#define BF_ENET_EIMR_MII(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_MII), uint32_t) & BM_ENET_EIMR_MII)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII field to a new value.
+#define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_RXB     (24U)         //!< Bit position for ENET_EIMR_RXB.
+#define BM_ENET_EIMR_RXB     (0x01000000U) //!< Bit mask for ENET_EIMR_RXB.
+#define BS_ENET_EIMR_RXB     (1U)          //!< Bit field size in bits for ENET_EIMR_RXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_RXB field.
+#define BR_ENET_EIMR_RXB(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_RXB.
+#define BF_ENET_EIMR_RXB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXB), uint32_t) & BM_ENET_EIMR_RXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXB field to a new value.
+#define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_RXF     (25U)         //!< Bit position for ENET_EIMR_RXF.
+#define BM_ENET_EIMR_RXF     (0x02000000U) //!< Bit mask for ENET_EIMR_RXF.
+#define BS_ENET_EIMR_RXF     (1U)          //!< Bit field size in bits for ENET_EIMR_RXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_RXF field.
+#define BR_ENET_EIMR_RXF(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_RXF.
+#define BF_ENET_EIMR_RXF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXF), uint32_t) & BM_ENET_EIMR_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXF field to a new value.
+#define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_TXB     (26U)         //!< Bit position for ENET_EIMR_TXB.
+#define BM_ENET_EIMR_TXB     (0x04000000U) //!< Bit mask for ENET_EIMR_TXB.
+#define BS_ENET_EIMR_TXB     (1U)          //!< Bit field size in bits for ENET_EIMR_TXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TXB field.
+#define BR_ENET_EIMR_TXB(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TXB.
+#define BF_ENET_EIMR_TXB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXB), uint32_t) & BM_ENET_EIMR_TXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXB field to a new value.
+#define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_TXF     (27U)         //!< Bit position for ENET_EIMR_TXF.
+#define BM_ENET_EIMR_TXF     (0x08000000U) //!< Bit mask for ENET_EIMR_TXF.
+#define BS_ENET_EIMR_TXF     (1U)          //!< Bit field size in bits for ENET_EIMR_TXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TXF field.
+#define BR_ENET_EIMR_TXF(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TXF.
+#define BF_ENET_EIMR_TXF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXF), uint32_t) & BM_ENET_EIMR_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXF field to a new value.
+#define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_GRA     (28U)         //!< Bit position for ENET_EIMR_GRA.
+#define BM_ENET_EIMR_GRA     (0x10000000U) //!< Bit mask for ENET_EIMR_GRA.
+#define BS_ENET_EIMR_GRA     (1U)          //!< Bit field size in bits for ENET_EIMR_GRA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_GRA field.
+#define BR_ENET_EIMR_GRA(x)  (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_GRA.
+#define BF_ENET_EIMR_GRA(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_GRA), uint32_t) & BM_ENET_EIMR_GRA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GRA field to a new value.
+#define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_BABT    (29U)         //!< Bit position for ENET_EIMR_BABT.
+#define BM_ENET_EIMR_BABT    (0x20000000U) //!< Bit mask for ENET_EIMR_BABT.
+#define BS_ENET_EIMR_BABT    (1U)          //!< Bit field size in bits for ENET_EIMR_BABT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_BABT field.
+#define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_BABT.
+#define BF_ENET_EIMR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABT), uint32_t) & BM_ENET_EIMR_BABT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABT field to a new value.
+#define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_BABR    (30U)         //!< Bit position for ENET_EIMR_BABR.
+#define BM_ENET_EIMR_BABR    (0x40000000U) //!< Bit mask for ENET_EIMR_BABR.
+#define BS_ENET_EIMR_BABR    (1U)          //!< Bit field size in bits for ENET_EIMR_BABR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_BABR field.
+#define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_BABR.
+#define BF_ENET_EIMR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABR), uint32_t) & BM_ENET_EIMR_BABR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABR field to a new value.
+#define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RDAR - Receive Descriptor Active Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+typedef union _hw_enet_rdar
+{
+    uint32_t U;
+    struct _hw_enet_rdar_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t RDAR : 1;             //!< [24] Receive Descriptor Active
+        uint32_t RESERVED1 : 7;        //!< [31:25]
+    } B;
+} hw_enet_rdar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+//@{
+#define HW_ENET_RDAR_ADDR(x)     (REGS_ENET_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RDAR(x)          (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
+#define HW_ENET_RDAR_RD(x)       (HW_ENET_RDAR(x).U)
+#define HW_ENET_RDAR_WR(x, v)    (HW_ENET_RDAR(x).U = (v))
+#define HW_ENET_RDAR_SET(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) |  (v)))
+#define HW_ENET_RDAR_CLR(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
+#define HW_ENET_RDAR_TOG(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+//@{
+#define BP_ENET_RDAR_RDAR    (24U)         //!< Bit position for ENET_RDAR_RDAR.
+#define BM_ENET_RDAR_RDAR    (0x01000000U) //!< Bit mask for ENET_RDAR_RDAR.
+#define BS_ENET_RDAR_RDAR    (1U)          //!< Bit field size in bits for ENET_RDAR_RDAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RDAR_RDAR field.
+#define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
+#endif
+
+//! @brief Format value for bitfield ENET_RDAR_RDAR.
+#define BF_ENET_RDAR_RDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDAR_RDAR), uint32_t) & BM_ENET_RDAR_RDAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDAR field to a new value.
+#define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TDAR - Transmit Descriptor Active Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+typedef union _hw_enet_tdar
+{
+    uint32_t U;
+    struct _hw_enet_tdar_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t TDAR : 1;             //!< [24] Transmit Descriptor Active
+        uint32_t RESERVED1 : 7;        //!< [31:25]
+    } B;
+} hw_enet_tdar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+//@{
+#define HW_ENET_TDAR_ADDR(x)     (REGS_ENET_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TDAR(x)          (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
+#define HW_ENET_TDAR_RD(x)       (HW_ENET_TDAR(x).U)
+#define HW_ENET_TDAR_WR(x, v)    (HW_ENET_TDAR(x).U = (v))
+#define HW_ENET_TDAR_SET(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) |  (v)))
+#define HW_ENET_TDAR_CLR(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
+#define HW_ENET_TDAR_TOG(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+//@{
+#define BP_ENET_TDAR_TDAR    (24U)         //!< Bit position for ENET_TDAR_TDAR.
+#define BM_ENET_TDAR_TDAR    (0x01000000U) //!< Bit mask for ENET_TDAR_TDAR.
+#define BS_ENET_TDAR_TDAR    (1U)          //!< Bit field size in bits for ENET_TDAR_TDAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TDAR_TDAR field.
+#define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
+#endif
+
+//! @brief Format value for bitfield ENET_TDAR_TDAR.
+#define BF_ENET_TDAR_TDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDAR_TDAR), uint32_t) & BM_ENET_TDAR_TDAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDAR field to a new value.
+#define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ECR - Ethernet Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+typedef union _hw_enet_ecr
+{
+    uint32_t U;
+    struct _hw_enet_ecr_bitfields
+    {
+        uint32_t RESET : 1;            //!< [0] Ethernet MAC Reset
+        uint32_t ETHEREN : 1;          //!< [1] Ethernet Enable
+        uint32_t MAGICEN : 1;          //!< [2] Magic Packet Detection Enable
+        uint32_t SLEEP : 1;            //!< [3] Sleep Mode Enable
+        uint32_t EN1588 : 1;           //!< [4] EN1588 Enable
+        uint32_t RESERVED0 : 1;        //!< [5]
+        uint32_t DBGEN : 1;            //!< [6] Debug Enable
+        uint32_t STOPEN : 1;           //!< [7] STOPEN Signal Control
+        uint32_t DBSWP : 1;            //!< [8] Descriptor Byte Swapping Enable
+        uint32_t RESERVED1 : 23;       //!< [31:9]
+    } B;
+} hw_enet_ecr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+//@{
+#define HW_ENET_ECR_ADDR(x)      (REGS_ENET_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ECR(x)           (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
+#define HW_ENET_ECR_RD(x)        (HW_ENET_ECR(x).U)
+#define HW_ENET_ECR_WR(x, v)     (HW_ENET_ECR(x).U = (v))
+#define HW_ENET_ECR_SET(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) |  (v)))
+#define HW_ENET_ECR_CLR(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
+#define HW_ENET_ECR_TOG(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+//@{
+#define BP_ENET_ECR_RESET    (0U)          //!< Bit position for ENET_ECR_RESET.
+#define BM_ENET_ECR_RESET    (0x00000001U) //!< Bit mask for ENET_ECR_RESET.
+#define BS_ENET_ECR_RESET    (1U)          //!< Bit field size in bits for ENET_ECR_RESET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_RESET field.
+#define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_RESET.
+#define BF_ENET_ECR_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_RESET), uint32_t) & BM_ENET_ECR_RESET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESET field to a new value.
+#define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 1 - MAC is enabled, and reception and transmission are possible.
+ */
+//@{
+#define BP_ENET_ECR_ETHEREN  (1U)          //!< Bit position for ENET_ECR_ETHEREN.
+#define BM_ENET_ECR_ETHEREN  (0x00000002U) //!< Bit mask for ENET_ECR_ETHEREN.
+#define BS_ENET_ECR_ETHEREN  (1U)          //!< Bit field size in bits for ENET_ECR_ETHEREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_ETHEREN field.
+#define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_ETHEREN.
+#define BF_ENET_ECR_ETHEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_ETHEREN), uint32_t) & BM_ENET_ECR_ETHEREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ETHEREN field to a new value.
+#define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0 - Magic detection logic disabled.
+ * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
+ *     is detected.
+ */
+//@{
+#define BP_ENET_ECR_MAGICEN  (2U)          //!< Bit position for ENET_ECR_MAGICEN.
+#define BM_ENET_ECR_MAGICEN  (0x00000004U) //!< Bit mask for ENET_ECR_MAGICEN.
+#define BS_ENET_ECR_MAGICEN  (1U)          //!< Bit field size in bits for ENET_ECR_MAGICEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_MAGICEN field.
+#define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_MAGICEN.
+#define BF_ENET_ECR_MAGICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_MAGICEN), uint32_t) & BM_ENET_ECR_MAGICEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAGICEN field to a new value.
+#define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0 - Normal operating mode.
+ * - 1 - Sleep mode.
+ */
+//@{
+#define BP_ENET_ECR_SLEEP    (3U)          //!< Bit position for ENET_ECR_SLEEP.
+#define BM_ENET_ECR_SLEEP    (0x00000008U) //!< Bit mask for ENET_ECR_SLEEP.
+#define BS_ENET_ECR_SLEEP    (1U)          //!< Bit field size in bits for ENET_ECR_SLEEP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_SLEEP field.
+#define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_SLEEP.
+#define BF_ENET_ECR_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_SLEEP), uint32_t) & BM_ENET_ECR_SLEEP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLEEP field to a new value.
+#define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 1 - Enhanced frame time-stamping functions enabled.
+ */
+//@{
+#define BP_ENET_ECR_EN1588   (4U)          //!< Bit position for ENET_ECR_EN1588.
+#define BM_ENET_ECR_EN1588   (0x00000010U) //!< Bit mask for ENET_ECR_EN1588.
+#define BS_ENET_ECR_EN1588   (1U)          //!< Bit field size in bits for ENET_ECR_EN1588.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_EN1588 field.
+#define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_EN1588.
+#define BF_ENET_ECR_EN1588(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_EN1588), uint32_t) & BM_ENET_ECR_EN1588)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN1588 field to a new value.
+#define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0 - MAC continues operation in debug mode.
+ * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+//@{
+#define BP_ENET_ECR_DBGEN    (6U)          //!< Bit position for ENET_ECR_DBGEN.
+#define BM_ENET_ECR_DBGEN    (0x00000040U) //!< Bit mask for ENET_ECR_DBGEN.
+#define BS_ENET_ECR_DBGEN    (1U)          //!< Bit field size in bits for ENET_ECR_DBGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_DBGEN field.
+#define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_DBGEN.
+#define BF_ENET_ECR_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBGEN), uint32_t) & BM_ENET_ECR_DBGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGEN field to a new value.
+#define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+//@{
+#define BP_ENET_ECR_STOPEN   (7U)          //!< Bit position for ENET_ECR_STOPEN.
+#define BM_ENET_ECR_STOPEN   (0x00000080U) //!< Bit mask for ENET_ECR_STOPEN.
+#define BS_ENET_ECR_STOPEN   (1U)          //!< Bit field size in bits for ENET_ECR_STOPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_STOPEN field.
+#define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_STOPEN.
+#define BF_ENET_ECR_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_STOPEN), uint32_t) & BM_ENET_ECR_STOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPEN field to a new value.
+#define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+//@{
+#define BP_ENET_ECR_DBSWP    (8U)          //!< Bit position for ENET_ECR_DBSWP.
+#define BM_ENET_ECR_DBSWP    (0x00000100U) //!< Bit mask for ENET_ECR_DBSWP.
+#define BS_ENET_ECR_DBSWP    (1U)          //!< Bit field size in bits for ENET_ECR_DBSWP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_DBSWP field.
+#define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_DBSWP.
+#define BF_ENET_ECR_DBSWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBSWP), uint32_t) & BM_ENET_ECR_DBSWP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBSWP field to a new value.
+#define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MMFR - MII Management Frame Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+typedef union _hw_enet_mmfr
+{
+    uint32_t U;
+    struct _hw_enet_mmfr_bitfields
+    {
+        uint32_t DATA : 16;            //!< [15:0] Management Frame Data
+        uint32_t TA : 2;               //!< [17:16] Turn Around
+        uint32_t RA : 5;               //!< [22:18] Register Address
+        uint32_t PA : 5;               //!< [27:23] PHY Address
+        uint32_t OP : 2;               //!< [29:28] Operation Code
+        uint32_t ST : 2;               //!< [31:30] Start Of Frame Delimiter
+    } B;
+} hw_enet_mmfr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+//@{
+#define HW_ENET_MMFR_ADDR(x)     (REGS_ENET_BASE(x) + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MMFR(x)          (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
+#define HW_ENET_MMFR_RD(x)       (HW_ENET_MMFR(x).U)
+#define HW_ENET_MMFR_WR(x, v)    (HW_ENET_MMFR(x).U = (v))
+#define HW_ENET_MMFR_SET(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) |  (v)))
+#define HW_ENET_MMFR_CLR(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
+#define HW_ENET_MMFR_TOG(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+//@{
+#define BP_ENET_MMFR_DATA    (0U)          //!< Bit position for ENET_MMFR_DATA.
+#define BM_ENET_MMFR_DATA    (0x0000FFFFU) //!< Bit mask for ENET_MMFR_DATA.
+#define BS_ENET_MMFR_DATA    (16U)         //!< Bit field size in bits for ENET_MMFR_DATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_DATA field.
+#define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_DATA.
+#define BF_ENET_MMFR_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_DATA), uint32_t) & BM_ENET_MMFR_DATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA field to a new value.
+#define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+//@{
+#define BP_ENET_MMFR_TA      (16U)         //!< Bit position for ENET_MMFR_TA.
+#define BM_ENET_MMFR_TA      (0x00030000U) //!< Bit mask for ENET_MMFR_TA.
+#define BS_ENET_MMFR_TA      (2U)          //!< Bit field size in bits for ENET_MMFR_TA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_TA field.
+#define BR_ENET_MMFR_TA(x)   (HW_ENET_MMFR(x).B.TA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_TA.
+#define BF_ENET_MMFR_TA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_TA), uint32_t) & BM_ENET_MMFR_TA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TA field to a new value.
+#define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+//@{
+#define BP_ENET_MMFR_RA      (18U)         //!< Bit position for ENET_MMFR_RA.
+#define BM_ENET_MMFR_RA      (0x007C0000U) //!< Bit mask for ENET_MMFR_RA.
+#define BS_ENET_MMFR_RA      (5U)          //!< Bit field size in bits for ENET_MMFR_RA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_RA field.
+#define BR_ENET_MMFR_RA(x)   (HW_ENET_MMFR(x).B.RA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_RA.
+#define BF_ENET_MMFR_RA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_RA), uint32_t) & BM_ENET_MMFR_RA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RA field to a new value.
+#define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+//@{
+#define BP_ENET_MMFR_PA      (23U)         //!< Bit position for ENET_MMFR_PA.
+#define BM_ENET_MMFR_PA      (0x0F800000U) //!< Bit mask for ENET_MMFR_PA.
+#define BS_ENET_MMFR_PA      (5U)          //!< Bit field size in bits for ENET_MMFR_PA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_PA field.
+#define BR_ENET_MMFR_PA(x)   (HW_ENET_MMFR(x).B.PA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_PA.
+#define BF_ENET_MMFR_PA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_PA), uint32_t) & BM_ENET_MMFR_PA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PA field to a new value.
+#define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 00 - Write frame operation, but not MII compliant.
+ * - 01 - Write frame operation for a valid MII management frame.
+ * - 10 - Read frame operation for a valid MII management frame.
+ * - 11 - Read frame operation, but not MII compliant.
+ */
+//@{
+#define BP_ENET_MMFR_OP      (28U)         //!< Bit position for ENET_MMFR_OP.
+#define BM_ENET_MMFR_OP      (0x30000000U) //!< Bit mask for ENET_MMFR_OP.
+#define BS_ENET_MMFR_OP      (2U)          //!< Bit field size in bits for ENET_MMFR_OP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_OP field.
+#define BR_ENET_MMFR_OP(x)   (HW_ENET_MMFR(x).B.OP)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_OP.
+#define BF_ENET_MMFR_OP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_OP), uint32_t) & BM_ENET_MMFR_OP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OP field to a new value.
+#define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+//@{
+#define BP_ENET_MMFR_ST      (30U)         //!< Bit position for ENET_MMFR_ST.
+#define BM_ENET_MMFR_ST      (0xC0000000U) //!< Bit mask for ENET_MMFR_ST.
+#define BS_ENET_MMFR_ST      (2U)          //!< Bit field size in bits for ENET_MMFR_ST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_ST field.
+#define BR_ENET_MMFR_ST(x)   (HW_ENET_MMFR(x).B.ST)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_ST.
+#define BF_ENET_MMFR_ST(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_ST), uint32_t) & BM_ENET_MMFR_ST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ST field to a new value.
+#define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MSCR - MII Speed Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+typedef union _hw_enet_mscr
+{
+    uint32_t U;
+    struct _hw_enet_mscr_bitfields
+    {
+        uint32_t RESERVED0 : 1;        //!< [0]
+        uint32_t MII_SPEED : 6;        //!< [6:1] MII Speed
+        uint32_t DIS_PRE : 1;          //!< [7] Disable Preamble
+        uint32_t HOLDTIME : 3;         //!< [10:8] Hold time On MDIO Output
+        uint32_t RESERVED1 : 21;       //!< [31:11]
+    } B;
+} hw_enet_mscr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+//@{
+#define HW_ENET_MSCR_ADDR(x)     (REGS_ENET_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MSCR(x)          (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
+#define HW_ENET_MSCR_RD(x)       (HW_ENET_MSCR(x).U)
+#define HW_ENET_MSCR_WR(x, v)    (HW_ENET_MSCR(x).U = (v))
+#define HW_ENET_MSCR_SET(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) |  (v)))
+#define HW_ENET_MSCR_CLR(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
+#define HW_ENET_MSCR_TOG(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+//@{
+#define BP_ENET_MSCR_MII_SPEED (1U)        //!< Bit position for ENET_MSCR_MII_SPEED.
+#define BM_ENET_MSCR_MII_SPEED (0x0000007EU) //!< Bit mask for ENET_MSCR_MII_SPEED.
+#define BS_ENET_MSCR_MII_SPEED (6U)        //!< Bit field size in bits for ENET_MSCR_MII_SPEED.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MSCR_MII_SPEED field.
+#define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
+#endif
+
+//! @brief Format value for bitfield ENET_MSCR_MII_SPEED.
+#define BF_ENET_MSCR_MII_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_MII_SPEED), uint32_t) & BM_ENET_MSCR_MII_SPEED)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII_SPEED field to a new value.
+#define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0 - Preamble enabled.
+ * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+//@{
+#define BP_ENET_MSCR_DIS_PRE (7U)          //!< Bit position for ENET_MSCR_DIS_PRE.
+#define BM_ENET_MSCR_DIS_PRE (0x00000080U) //!< Bit mask for ENET_MSCR_DIS_PRE.
+#define BS_ENET_MSCR_DIS_PRE (1U)          //!< Bit field size in bits for ENET_MSCR_DIS_PRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MSCR_DIS_PRE field.
+#define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
+#endif
+
+//! @brief Format value for bitfield ENET_MSCR_DIS_PRE.
+#define BF_ENET_MSCR_DIS_PRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_DIS_PRE), uint32_t) & BM_ENET_MSCR_DIS_PRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIS_PRE field to a new value.
+#define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 000 - 1 internal module clock cycle
+ * - 001 - 2 internal module clock cycles
+ * - 010 - 3 internal module clock cycles
+ * - 111 - 8 internal module clock cycles
+ */
+//@{
+#define BP_ENET_MSCR_HOLDTIME (8U)         //!< Bit position for ENET_MSCR_HOLDTIME.
+#define BM_ENET_MSCR_HOLDTIME (0x00000700U) //!< Bit mask for ENET_MSCR_HOLDTIME.
+#define BS_ENET_MSCR_HOLDTIME (3U)         //!< Bit field size in bits for ENET_MSCR_HOLDTIME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MSCR_HOLDTIME field.
+#define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
+#endif
+
+//! @brief Format value for bitfield ENET_MSCR_HOLDTIME.
+#define BF_ENET_MSCR_HOLDTIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_HOLDTIME), uint32_t) & BM_ENET_MSCR_HOLDTIME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOLDTIME field to a new value.
+#define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MIBC - MIB Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+typedef union _hw_enet_mibc
+{
+    uint32_t U;
+    struct _hw_enet_mibc_bitfields
+    {
+        uint32_t RESERVED0 : 29;       //!< [28:0]
+        uint32_t MIB_CLEAR : 1;        //!< [29] MIB Clear
+        uint32_t MIB_IDLE : 1;         //!< [30] MIB Idle
+        uint32_t MIB_DIS : 1;          //!< [31] Disable MIB Logic
+    } B;
+} hw_enet_mibc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+//@{
+#define HW_ENET_MIBC_ADDR(x)     (REGS_ENET_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MIBC(x)          (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
+#define HW_ENET_MIBC_RD(x)       (HW_ENET_MIBC(x).U)
+#define HW_ENET_MIBC_WR(x, v)    (HW_ENET_MIBC(x).U = (v))
+#define HW_ENET_MIBC_SET(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) |  (v)))
+#define HW_ENET_MIBC_CLR(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
+#define HW_ENET_MIBC_TOG(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+//@{
+#define BP_ENET_MIBC_MIB_CLEAR (29U)       //!< Bit position for ENET_MIBC_MIB_CLEAR.
+#define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) //!< Bit mask for ENET_MIBC_MIB_CLEAR.
+#define BS_ENET_MIBC_MIB_CLEAR (1U)        //!< Bit field size in bits for ENET_MIBC_MIB_CLEAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MIBC_MIB_CLEAR field.
+#define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
+#endif
+
+//! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR.
+#define BF_ENET_MIBC_MIB_CLEAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_CLEAR), uint32_t) & BM_ENET_MIBC_MIB_CLEAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MIB_CLEAR field to a new value.
+#define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+//@{
+#define BP_ENET_MIBC_MIB_IDLE (30U)        //!< Bit position for ENET_MIBC_MIB_IDLE.
+#define BM_ENET_MIBC_MIB_IDLE (0x40000000U) //!< Bit mask for ENET_MIBC_MIB_IDLE.
+#define BS_ENET_MIBC_MIB_IDLE (1U)         //!< Bit field size in bits for ENET_MIBC_MIB_IDLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MIBC_MIB_IDLE field.
+#define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+//@{
+#define BP_ENET_MIBC_MIB_DIS (31U)         //!< Bit position for ENET_MIBC_MIB_DIS.
+#define BM_ENET_MIBC_MIB_DIS (0x80000000U) //!< Bit mask for ENET_MIBC_MIB_DIS.
+#define BS_ENET_MIBC_MIB_DIS (1U)          //!< Bit field size in bits for ENET_MIBC_MIB_DIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MIBC_MIB_DIS field.
+#define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
+#endif
+
+//! @brief Format value for bitfield ENET_MIBC_MIB_DIS.
+#define BF_ENET_MIBC_MIB_DIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_DIS), uint32_t) & BM_ENET_MIBC_MIB_DIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MIB_DIS field to a new value.
+#define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RCR - Receive Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+typedef union _hw_enet_rcr
+{
+    uint32_t U;
+    struct _hw_enet_rcr_bitfields
+    {
+        uint32_t LOOP : 1;             //!< [0] Internal Loopback
+        uint32_t DRT : 1;              //!< [1] Disable Receive On Transmit
+        uint32_t MII_MODE : 1;         //!< [2] Media Independent Interface Mode
+        uint32_t PROM : 1;             //!< [3] Promiscuous Mode
+        uint32_t BC_REJ : 1;           //!< [4] Broadcast Frame Reject
+        uint32_t FCE : 1;              //!< [5] Flow Control Enable
+        uint32_t RESERVED0 : 2;        //!< [7:6]
+        uint32_t RMII_MODE : 1;        //!< [8] RMII Mode Enable
+        uint32_t RMII_10T : 1;         //!< [9]
+        uint32_t RESERVED1 : 2;        //!< [11:10]
+        uint32_t PADEN : 1;            //!< [12] Enable Frame Padding Remove On Receive
+        uint32_t PAUFWD : 1;           //!< [13] Terminate/Forward Pause Frames
+        uint32_t CRCFWD : 1;           //!< [14] Terminate/Forward Received CRC
+        uint32_t CFEN : 1;             //!< [15] MAC Control Frame Enable
+        uint32_t MAX_FL : 14;          //!< [29:16] Maximum Frame Length
+        uint32_t NLC : 1;              //!< [30] Payload Length Check Disable
+        uint32_t GRS : 1;              //!< [31] Graceful Receive Stopped
+    } B;
+} hw_enet_rcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+//@{
+#define HW_ENET_RCR_ADDR(x)      (REGS_ENET_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RCR(x)           (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
+#define HW_ENET_RCR_RD(x)        (HW_ENET_RCR(x).U)
+#define HW_ENET_RCR_WR(x, v)     (HW_ENET_RCR(x).U = (v))
+#define HW_ENET_RCR_SET(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) |  (v)))
+#define HW_ENET_RCR_CLR(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
+#define HW_ENET_RCR_TOG(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0 - Loopback disabled.
+ * - 1 - Transmitted frames are looped back internal to the device and transmit
+ *     MII output signals are not asserted. DRT must be cleared.
+ */
+//@{
+#define BP_ENET_RCR_LOOP     (0U)          //!< Bit position for ENET_RCR_LOOP.
+#define BM_ENET_RCR_LOOP     (0x00000001U) //!< Bit mask for ENET_RCR_LOOP.
+#define BS_ENET_RCR_LOOP     (1U)          //!< Bit field size in bits for ENET_RCR_LOOP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_LOOP field.
+#define BR_ENET_RCR_LOOP(x)  (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_LOOP.
+#define BF_ENET_RCR_LOOP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_LOOP), uint32_t) & BM_ENET_RCR_LOOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOOP field to a new value.
+#define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+//@{
+#define BP_ENET_RCR_DRT      (1U)          //!< Bit position for ENET_RCR_DRT.
+#define BM_ENET_RCR_DRT      (0x00000002U) //!< Bit mask for ENET_RCR_DRT.
+#define BS_ENET_RCR_DRT      (1U)          //!< Bit field size in bits for ENET_RCR_DRT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_DRT field.
+#define BR_ENET_RCR_DRT(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_DRT.
+#define BF_ENET_RCR_DRT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_DRT), uint32_t) & BM_ENET_RCR_DRT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DRT field to a new value.
+#define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0 - Reserved.
+ * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+//@{
+#define BP_ENET_RCR_MII_MODE (2U)          //!< Bit position for ENET_RCR_MII_MODE.
+#define BM_ENET_RCR_MII_MODE (0x00000004U) //!< Bit mask for ENET_RCR_MII_MODE.
+#define BS_ENET_RCR_MII_MODE (1U)          //!< Bit field size in bits for ENET_RCR_MII_MODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_MII_MODE field.
+#define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_MII_MODE.
+#define BF_ENET_RCR_MII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MII_MODE), uint32_t) & BM_ENET_RCR_MII_MODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII_MODE field to a new value.
+#define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0 - Disabled.
+ * - 1 - Enabled.
+ */
+//@{
+#define BP_ENET_RCR_PROM     (3U)          //!< Bit position for ENET_RCR_PROM.
+#define BM_ENET_RCR_PROM     (0x00000008U) //!< Bit mask for ENET_RCR_PROM.
+#define BS_ENET_RCR_PROM     (1U)          //!< Bit field size in bits for ENET_RCR_PROM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_PROM field.
+#define BR_ENET_RCR_PROM(x)  (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_PROM.
+#define BF_ENET_RCR_PROM(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PROM), uint32_t) & BM_ENET_RCR_PROM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROM field to a new value.
+#define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+//@{
+#define BP_ENET_RCR_BC_REJ   (4U)          //!< Bit position for ENET_RCR_BC_REJ.
+#define BM_ENET_RCR_BC_REJ   (0x00000010U) //!< Bit mask for ENET_RCR_BC_REJ.
+#define BS_ENET_RCR_BC_REJ   (1U)          //!< Bit field size in bits for ENET_RCR_BC_REJ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_BC_REJ field.
+#define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_BC_REJ.
+#define BF_ENET_RCR_BC_REJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_BC_REJ), uint32_t) & BM_ENET_RCR_BC_REJ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BC_REJ field to a new value.
+#define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+//@{
+#define BP_ENET_RCR_FCE      (5U)          //!< Bit position for ENET_RCR_FCE.
+#define BM_ENET_RCR_FCE      (0x00000020U) //!< Bit mask for ENET_RCR_FCE.
+#define BS_ENET_RCR_FCE      (1U)          //!< Bit field size in bits for ENET_RCR_FCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_FCE field.
+#define BR_ENET_RCR_FCE(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_FCE.
+#define BF_ENET_RCR_FCE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_FCE), uint32_t) & BM_ENET_RCR_FCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCE field to a new value.
+#define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0 - MAC configured for MII mode.
+ * - 1 - MAC configured for RMII operation.
+ */
+//@{
+#define BP_ENET_RCR_RMII_MODE (8U)         //!< Bit position for ENET_RCR_RMII_MODE.
+#define BM_ENET_RCR_RMII_MODE (0x00000100U) //!< Bit mask for ENET_RCR_RMII_MODE.
+#define BS_ENET_RCR_RMII_MODE (1U)         //!< Bit field size in bits for ENET_RCR_RMII_MODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_RMII_MODE field.
+#define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_RMII_MODE.
+#define BF_ENET_RCR_RMII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_MODE), uint32_t) & BM_ENET_RCR_RMII_MODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMII_MODE field to a new value.
+#define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0 - 100 Mbps operation.
+ * - 1 - 10 Mbps operation.
+ */
+//@{
+#define BP_ENET_RCR_RMII_10T (9U)          //!< Bit position for ENET_RCR_RMII_10T.
+#define BM_ENET_RCR_RMII_10T (0x00000200U) //!< Bit mask for ENET_RCR_RMII_10T.
+#define BS_ENET_RCR_RMII_10T (1U)          //!< Bit field size in bits for ENET_RCR_RMII_10T.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_RMII_10T field.
+#define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_RMII_10T.
+#define BF_ENET_RCR_RMII_10T(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_10T), uint32_t) & BM_ENET_RCR_RMII_10T)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMII_10T field to a new value.
+#define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0 - No padding is removed on receive by the MAC.
+ * - 1 - Padding is removed from received frames.
+ */
+//@{
+#define BP_ENET_RCR_PADEN    (12U)         //!< Bit position for ENET_RCR_PADEN.
+#define BM_ENET_RCR_PADEN    (0x00001000U) //!< Bit mask for ENET_RCR_PADEN.
+#define BS_ENET_RCR_PADEN    (1U)          //!< Bit field size in bits for ENET_RCR_PADEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_PADEN field.
+#define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_PADEN.
+#define BF_ENET_RCR_PADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PADEN), uint32_t) & BM_ENET_RCR_PADEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADEN field to a new value.
+#define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0 - Pause frames are terminated and discarded in the MAC.
+ * - 1 - Pause frames are forwarded to the user application.
+ */
+//@{
+#define BP_ENET_RCR_PAUFWD   (13U)         //!< Bit position for ENET_RCR_PAUFWD.
+#define BM_ENET_RCR_PAUFWD   (0x00002000U) //!< Bit mask for ENET_RCR_PAUFWD.
+#define BS_ENET_RCR_PAUFWD   (1U)          //!< Bit field size in bits for ENET_RCR_PAUFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_PAUFWD field.
+#define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_PAUFWD.
+#define BF_ENET_RCR_PAUFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PAUFWD), uint32_t) & BM_ENET_RCR_PAUFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PAUFWD field to a new value.
+#define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0 - The CRC field of received frames is transmitted to the user application.
+ * - 1 - The CRC field is stripped from the frame.
+ */
+//@{
+#define BP_ENET_RCR_CRCFWD   (14U)         //!< Bit position for ENET_RCR_CRCFWD.
+#define BM_ENET_RCR_CRCFWD   (0x00004000U) //!< Bit mask for ENET_RCR_CRCFWD.
+#define BS_ENET_RCR_CRCFWD   (1U)          //!< Bit field size in bits for ENET_RCR_CRCFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_CRCFWD field.
+#define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_CRCFWD.
+#define BF_ENET_RCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CRCFWD), uint32_t) & BM_ENET_RCR_CRCFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRCFWD field to a new value.
+#define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
+ *     accepted and forwarded to the client interface.
+ * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
+ *     silently discarded.
+ */
+//@{
+#define BP_ENET_RCR_CFEN     (15U)         //!< Bit position for ENET_RCR_CFEN.
+#define BM_ENET_RCR_CFEN     (0x00008000U) //!< Bit mask for ENET_RCR_CFEN.
+#define BS_ENET_RCR_CFEN     (1U)          //!< Bit field size in bits for ENET_RCR_CFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_CFEN field.
+#define BR_ENET_RCR_CFEN(x)  (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_CFEN.
+#define BF_ENET_RCR_CFEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CFEN), uint32_t) & BM_ENET_RCR_CFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CFEN field to a new value.
+#define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+//@{
+#define BP_ENET_RCR_MAX_FL   (16U)         //!< Bit position for ENET_RCR_MAX_FL.
+#define BM_ENET_RCR_MAX_FL   (0x3FFF0000U) //!< Bit mask for ENET_RCR_MAX_FL.
+#define BS_ENET_RCR_MAX_FL   (14U)         //!< Bit field size in bits for ENET_RCR_MAX_FL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_MAX_FL field.
+#define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_MAX_FL.
+#define BF_ENET_RCR_MAX_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MAX_FL), uint32_t) & BM_ENET_RCR_MAX_FL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAX_FL field to a new value.
+#define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0 - The payload length check is disabled.
+ * - 1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+//@{
+#define BP_ENET_RCR_NLC      (30U)         //!< Bit position for ENET_RCR_NLC.
+#define BM_ENET_RCR_NLC      (0x40000000U) //!< Bit mask for ENET_RCR_NLC.
+#define BS_ENET_RCR_NLC      (1U)          //!< Bit field size in bits for ENET_RCR_NLC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_NLC field.
+#define BR_ENET_RCR_NLC(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_NLC.
+#define BF_ENET_RCR_NLC(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_NLC), uint32_t) & BM_ENET_RCR_NLC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NLC field to a new value.
+#define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+//@{
+#define BP_ENET_RCR_GRS      (31U)         //!< Bit position for ENET_RCR_GRS.
+#define BM_ENET_RCR_GRS      (0x80000000U) //!< Bit mask for ENET_RCR_GRS.
+#define BS_ENET_RCR_GRS      (1U)          //!< Bit field size in bits for ENET_RCR_GRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_GRS field.
+#define BR_ENET_RCR_GRS(x)   (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TCR - Transmit Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+typedef union _hw_enet_tcr
+{
+    uint32_t U;
+    struct _hw_enet_tcr_bitfields
+    {
+        uint32_t GTS : 1;              //!< [0] Graceful Transmit Stop
+        uint32_t RESERVED0 : 1;        //!< [1]
+        uint32_t FDEN : 1;             //!< [2] Full-Duplex Enable
+        uint32_t TFC_PAUSE : 1;        //!< [3] Transmit Frame Control Pause
+        uint32_t RFC_PAUSE : 1;        //!< [4] Receive Frame Control Pause
+        uint32_t ADDSEL : 3;           //!< [7:5] Source MAC Address Select On Transmit
+        uint32_t ADDINS : 1;           //!< [8] Set MAC Address On Transmit
+        uint32_t CRCFWD : 1;           //!< [9] Forward Frame From Application With CRC
+        uint32_t RESERVED1 : 22;       //!< [31:10]
+    } B;
+} hw_enet_tcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+//@{
+#define HW_ENET_TCR_ADDR(x)      (REGS_ENET_BASE(x) + 0xC4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TCR(x)           (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
+#define HW_ENET_TCR_RD(x)        (HW_ENET_TCR(x).U)
+#define HW_ENET_TCR_WR(x, v)     (HW_ENET_TCR(x).U = (v))
+#define HW_ENET_TCR_SET(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) |  (v)))
+#define HW_ENET_TCR_CLR(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
+#define HW_ENET_TCR_TOG(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+//@{
+#define BP_ENET_TCR_GTS      (0U)          //!< Bit position for ENET_TCR_GTS.
+#define BM_ENET_TCR_GTS      (0x00000001U) //!< Bit mask for ENET_TCR_GTS.
+#define BS_ENET_TCR_GTS      (1U)          //!< Bit field size in bits for ENET_TCR_GTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_GTS field.
+#define BR_ENET_TCR_GTS(x)   (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_GTS.
+#define BF_ENET_TCR_GTS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_GTS), uint32_t) & BM_ENET_TCR_GTS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTS field to a new value.
+#define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+//@{
+#define BP_ENET_TCR_FDEN     (2U)          //!< Bit position for ENET_TCR_FDEN.
+#define BM_ENET_TCR_FDEN     (0x00000004U) //!< Bit mask for ENET_TCR_FDEN.
+#define BS_ENET_TCR_FDEN     (1U)          //!< Bit field size in bits for ENET_TCR_FDEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_FDEN field.
+#define BR_ENET_TCR_FDEN(x)  (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_FDEN.
+#define BF_ENET_TCR_FDEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_FDEN), uint32_t) & BM_ENET_TCR_FDEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FDEN field to a new value.
+#define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0 - No PAUSE frame transmitted.
+ * - 1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+//@{
+#define BP_ENET_TCR_TFC_PAUSE (3U)         //!< Bit position for ENET_TCR_TFC_PAUSE.
+#define BM_ENET_TCR_TFC_PAUSE (0x00000008U) //!< Bit mask for ENET_TCR_TFC_PAUSE.
+#define BS_ENET_TCR_TFC_PAUSE (1U)         //!< Bit field size in bits for ENET_TCR_TFC_PAUSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_TFC_PAUSE field.
+#define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_TFC_PAUSE.
+#define BF_ENET_TCR_TFC_PAUSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_TFC_PAUSE), uint32_t) & BM_ENET_TCR_TFC_PAUSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFC_PAUSE field to a new value.
+#define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+//@{
+#define BP_ENET_TCR_RFC_PAUSE (4U)         //!< Bit position for ENET_TCR_RFC_PAUSE.
+#define BM_ENET_TCR_RFC_PAUSE (0x00000010U) //!< Bit mask for ENET_TCR_RFC_PAUSE.
+#define BS_ENET_TCR_RFC_PAUSE (1U)         //!< Bit field size in bits for ENET_TCR_RFC_PAUSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_RFC_PAUSE field.
+#define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 100 - Reserved.
+ * - 101 - Reserved.
+ * - 110 - Reserved.
+ */
+//@{
+#define BP_ENET_TCR_ADDSEL   (5U)          //!< Bit position for ENET_TCR_ADDSEL.
+#define BM_ENET_TCR_ADDSEL   (0x000000E0U) //!< Bit mask for ENET_TCR_ADDSEL.
+#define BS_ENET_TCR_ADDSEL   (3U)          //!< Bit field size in bits for ENET_TCR_ADDSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_ADDSEL field.
+#define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_ADDSEL.
+#define BF_ENET_TCR_ADDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDSEL), uint32_t) & BM_ENET_TCR_ADDSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADDSEL field to a new value.
+#define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0 - The source MAC address is not modified by the MAC.
+ * - 1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+//@{
+#define BP_ENET_TCR_ADDINS   (8U)          //!< Bit position for ENET_TCR_ADDINS.
+#define BM_ENET_TCR_ADDINS   (0x00000100U) //!< Bit mask for ENET_TCR_ADDINS.
+#define BS_ENET_TCR_ADDINS   (1U)          //!< Bit field size in bits for ENET_TCR_ADDINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_ADDINS field.
+#define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_ADDINS.
+#define BF_ENET_TCR_ADDINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDINS), uint32_t) & BM_ENET_TCR_ADDINS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADDINS field to a new value.
+#define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
+ *     expecting a frame with CRC from the application.
+ */
+//@{
+#define BP_ENET_TCR_CRCFWD   (9U)          //!< Bit position for ENET_TCR_CRCFWD.
+#define BM_ENET_TCR_CRCFWD   (0x00000200U) //!< Bit mask for ENET_TCR_CRCFWD.
+#define BS_ENET_TCR_CRCFWD   (1U)          //!< Bit field size in bits for ENET_TCR_CRCFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_CRCFWD field.
+#define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_CRCFWD.
+#define BF_ENET_TCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_CRCFWD), uint32_t) & BM_ENET_TCR_CRCFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRCFWD field to a new value.
+#define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_PALR - Physical Address Lower Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+typedef union _hw_enet_palr
+{
+    uint32_t U;
+    struct _hw_enet_palr_bitfields
+    {
+        uint32_t PADDR1 : 32;          //!< [31:0] Pause Address
+    } B;
+} hw_enet_palr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+//@{
+#define HW_ENET_PALR_ADDR(x)     (REGS_ENET_BASE(x) + 0xE4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_PALR(x)          (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
+#define HW_ENET_PALR_RD(x)       (HW_ENET_PALR(x).U)
+#define HW_ENET_PALR_WR(x, v)    (HW_ENET_PALR(x).U = (v))
+#define HW_ENET_PALR_SET(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) |  (v)))
+#define HW_ENET_PALR_CLR(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
+#define HW_ENET_PALR_TOG(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_PALR bitfields
+ */
+
+/*!
+ * @name Register ENET_PALR, field PADDR1[31:0] (RW)
+ *
+ * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
+ * 6-byte individual address are used for exact match and the source address
+ * field in PAUSE frames.
+ */
+//@{
+#define BP_ENET_PALR_PADDR1  (0U)          //!< Bit position for ENET_PALR_PADDR1.
+#define BM_ENET_PALR_PADDR1  (0xFFFFFFFFU) //!< Bit mask for ENET_PALR_PADDR1.
+#define BS_ENET_PALR_PADDR1  (32U)         //!< Bit field size in bits for ENET_PALR_PADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_PALR_PADDR1 field.
+#define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_PALR_PADDR1.
+#define BF_ENET_PALR_PADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PALR_PADDR1), uint32_t) & BM_ENET_PALR_PADDR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADDR1 field to a new value.
+#define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_PAUR - Physical Address Upper Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+typedef union _hw_enet_paur
+{
+    uint32_t U;
+    struct _hw_enet_paur_bitfields
+    {
+        uint32_t TYPE : 16;            //!< [15:0] Type Field In PAUSE Frames
+        uint32_t PADDR2 : 16;          //!< [31:16]
+    } B;
+} hw_enet_paur_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+//@{
+#define HW_ENET_PAUR_ADDR(x)     (REGS_ENET_BASE(x) + 0xE8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_PAUR(x)          (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
+#define HW_ENET_PAUR_RD(x)       (HW_ENET_PAUR(x).U)
+#define HW_ENET_PAUR_WR(x, v)    (HW_ENET_PAUR(x).U = (v))
+#define HW_ENET_PAUR_SET(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) |  (v)))
+#define HW_ENET_PAUR_CLR(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
+#define HW_ENET_PAUR_TOG(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+//@{
+#define BP_ENET_PAUR_TYPE    (0U)          //!< Bit position for ENET_PAUR_TYPE.
+#define BM_ENET_PAUR_TYPE    (0x0000FFFFU) //!< Bit mask for ENET_PAUR_TYPE.
+#define BS_ENET_PAUR_TYPE    (16U)         //!< Bit field size in bits for ENET_PAUR_TYPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_PAUR_TYPE field.
+#define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
+#endif
+//@}
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+//@{
+#define BP_ENET_PAUR_PADDR2  (16U)         //!< Bit position for ENET_PAUR_PADDR2.
+#define BM_ENET_PAUR_PADDR2  (0xFFFF0000U) //!< Bit mask for ENET_PAUR_PADDR2.
+#define BS_ENET_PAUR_PADDR2  (16U)         //!< Bit field size in bits for ENET_PAUR_PADDR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_PAUR_PADDR2 field.
+#define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
+#endif
+
+//! @brief Format value for bitfield ENET_PAUR_PADDR2.
+#define BF_ENET_PAUR_PADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PAUR_PADDR2), uint32_t) & BM_ENET_PAUR_PADDR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADDR2 field to a new value.
+#define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_OPD - Opcode/Pause Duration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+typedef union _hw_enet_opd
+{
+    uint32_t U;
+    struct _hw_enet_opd_bitfields
+    {
+        uint32_t PAUSE_DUR : 16;       //!< [15:0] Pause Duration
+        uint32_t OPCODE : 16;          //!< [31:16] Opcode Field In PAUSE Frames
+    } B;
+} hw_enet_opd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+//@{
+#define HW_ENET_OPD_ADDR(x)      (REGS_ENET_BASE(x) + 0xECU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_OPD(x)           (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
+#define HW_ENET_OPD_RD(x)        (HW_ENET_OPD(x).U)
+#define HW_ENET_OPD_WR(x, v)     (HW_ENET_OPD(x).U = (v))
+#define HW_ENET_OPD_SET(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) |  (v)))
+#define HW_ENET_OPD_CLR(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
+#define HW_ENET_OPD_TOG(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+//@{
+#define BP_ENET_OPD_PAUSE_DUR (0U)         //!< Bit position for ENET_OPD_PAUSE_DUR.
+#define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) //!< Bit mask for ENET_OPD_PAUSE_DUR.
+#define BS_ENET_OPD_PAUSE_DUR (16U)        //!< Bit field size in bits for ENET_OPD_PAUSE_DUR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_OPD_PAUSE_DUR field.
+#define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
+#endif
+
+//! @brief Format value for bitfield ENET_OPD_PAUSE_DUR.
+#define BF_ENET_OPD_PAUSE_DUR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_OPD_PAUSE_DUR), uint32_t) & BM_ENET_OPD_PAUSE_DUR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PAUSE_DUR field to a new value.
+#define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+//@{
+#define BP_ENET_OPD_OPCODE   (16U)         //!< Bit position for ENET_OPD_OPCODE.
+#define BM_ENET_OPD_OPCODE   (0xFFFF0000U) //!< Bit mask for ENET_OPD_OPCODE.
+#define BS_ENET_OPD_OPCODE   (16U)         //!< Bit field size in bits for ENET_OPD_OPCODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_OPD_OPCODE field.
+#define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IAUR - Descriptor Individual Upper Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+typedef union _hw_enet_iaur
+{
+    uint32_t U;
+    struct _hw_enet_iaur_bitfields
+    {
+        uint32_t IADDR1 : 32;          //!< [31:0]
+    } B;
+} hw_enet_iaur_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+//@{
+#define HW_ENET_IAUR_ADDR(x)     (REGS_ENET_BASE(x) + 0x118U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IAUR(x)          (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
+#define HW_ENET_IAUR_RD(x)       (HW_ENET_IAUR(x).U)
+#define HW_ENET_IAUR_WR(x, v)    (HW_ENET_IAUR(x).U = (v))
+#define HW_ENET_IAUR_SET(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) |  (v)))
+#define HW_ENET_IAUR_CLR(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
+#define HW_ENET_IAUR_TOG(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
+ *
+ * Contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
+ * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
+ */
+//@{
+#define BP_ENET_IAUR_IADDR1  (0U)          //!< Bit position for ENET_IAUR_IADDR1.
+#define BM_ENET_IAUR_IADDR1  (0xFFFFFFFFU) //!< Bit mask for ENET_IAUR_IADDR1.
+#define BS_ENET_IAUR_IADDR1  (32U)         //!< Bit field size in bits for ENET_IAUR_IADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IAUR_IADDR1 field.
+#define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_IAUR_IADDR1.
+#define BF_ENET_IAUR_IADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IAUR_IADDR1), uint32_t) & BM_ENET_IAUR_IADDR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IADDR1 field to a new value.
+#define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IALR - Descriptor Individual Lower Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+typedef union _hw_enet_ialr
+{
+    uint32_t U;
+    struct _hw_enet_ialr_bitfields
+    {
+        uint32_t IADDR2 : 32;          //!< [31:0]
+    } B;
+} hw_enet_ialr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+//@{
+#define HW_ENET_IALR_ADDR(x)     (REGS_ENET_BASE(x) + 0x11CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IALR(x)          (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
+#define HW_ENET_IALR_RD(x)       (HW_ENET_IALR(x).U)
+#define HW_ENET_IALR_WR(x, v)    (HW_ENET_IALR(x).U = (v))
+#define HW_ENET_IALR_SET(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) |  (v)))
+#define HW_ENET_IALR_CLR(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
+#define HW_ENET_IALR_TOG(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IALR bitfields
+ */
+
+/*!
+ * @name Register ENET_IALR, field IADDR2[31:0] (RW)
+ *
+ * Contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
+ * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
+ */
+//@{
+#define BP_ENET_IALR_IADDR2  (0U)          //!< Bit position for ENET_IALR_IADDR2.
+#define BM_ENET_IALR_IADDR2  (0xFFFFFFFFU) //!< Bit mask for ENET_IALR_IADDR2.
+#define BS_ENET_IALR_IADDR2  (32U)         //!< Bit field size in bits for ENET_IALR_IADDR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IALR_IADDR2 field.
+#define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_IALR_IADDR2.
+#define BF_ENET_IALR_IADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IALR_IADDR2), uint32_t) & BM_ENET_IALR_IADDR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IADDR2 field to a new value.
+#define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_GAUR - Descriptor Group Upper Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+typedef union _hw_enet_gaur
+{
+    uint32_t U;
+    struct _hw_enet_gaur_bitfields
+    {
+        uint32_t GADDR1 : 32;          //!< [31:0]
+    } B;
+} hw_enet_gaur_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+//@{
+#define HW_ENET_GAUR_ADDR(x)     (REGS_ENET_BASE(x) + 0x120U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_GAUR(x)          (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
+#define HW_ENET_GAUR_RD(x)       (HW_ENET_GAUR(x).U)
+#define HW_ENET_GAUR_WR(x, v)    (HW_ENET_GAUR(x).U = (v))
+#define HW_ENET_GAUR_SET(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) |  (v)))
+#define HW_ENET_GAUR_CLR(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
+#define HW_ENET_GAUR_TOG(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_GAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
+ *
+ * Contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
+ * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
+ */
+//@{
+#define BP_ENET_GAUR_GADDR1  (0U)          //!< Bit position for ENET_GAUR_GADDR1.
+#define BM_ENET_GAUR_GADDR1  (0xFFFFFFFFU) //!< Bit mask for ENET_GAUR_GADDR1.
+#define BS_ENET_GAUR_GADDR1  (32U)         //!< Bit field size in bits for ENET_GAUR_GADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_GAUR_GADDR1 field.
+#define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_GAUR_GADDR1.
+#define BF_ENET_GAUR_GADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GAUR_GADDR1), uint32_t) & BM_ENET_GAUR_GADDR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GADDR1 field to a new value.
+#define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_GALR - Descriptor Group Lower Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+typedef union _hw_enet_galr
+{
+    uint32_t U;
+    struct _hw_enet_galr_bitfields
+    {
+        uint32_t GADDR2 : 32;          //!< [31:0]
+    } B;
+} hw_enet_galr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+//@{
+#define HW_ENET_GALR_ADDR(x)     (REGS_ENET_BASE(x) + 0x124U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_GALR(x)          (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
+#define HW_ENET_GALR_RD(x)       (HW_ENET_GALR(x).U)
+#define HW_ENET_GALR_WR(x, v)    (HW_ENET_GALR(x).U = (v))
+#define HW_ENET_GALR_SET(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) |  (v)))
+#define HW_ENET_GALR_CLR(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
+#define HW_ENET_GALR_TOG(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_GALR bitfields
+ */
+
+/*!
+ * @name Register ENET_GALR, field GADDR2[31:0] (RW)
+ *
+ * Contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
+ * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
+ */
+//@{
+#define BP_ENET_GALR_GADDR2  (0U)          //!< Bit position for ENET_GALR_GADDR2.
+#define BM_ENET_GALR_GADDR2  (0xFFFFFFFFU) //!< Bit mask for ENET_GALR_GADDR2.
+#define BS_ENET_GALR_GADDR2  (32U)         //!< Bit field size in bits for ENET_GALR_GADDR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_GALR_GADDR2 field.
+#define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_GALR_GADDR2.
+#define BF_ENET_GALR_GADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GALR_GADDR2), uint32_t) & BM_ENET_GALR_GADDR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GADDR2 field to a new value.
+#define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TFWR - Transmit FIFO Watermark Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+typedef union _hw_enet_tfwr
+{
+    uint32_t U;
+    struct _hw_enet_tfwr_bitfields
+    {
+        uint32_t TFWR : 6;             //!< [5:0] Transmit FIFO Write
+        uint32_t RESERVED0 : 2;        //!< [7:6]
+        uint32_t STRFWD : 1;           //!< [8] Store And Forward Enable
+        uint32_t RESERVED1 : 23;       //!< [31:9]
+    } B;
+} hw_enet_tfwr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+//@{
+#define HW_ENET_TFWR_ADDR(x)     (REGS_ENET_BASE(x) + 0x144U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TFWR(x)          (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
+#define HW_ENET_TFWR_RD(x)       (HW_ENET_TFWR(x).U)
+#define HW_ENET_TFWR_WR(x, v)    (HW_ENET_TFWR(x).U = (v))
+#define HW_ENET_TFWR_SET(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) |  (v)))
+#define HW_ENET_TFWR_CLR(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
+#define HW_ENET_TFWR_TOG(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 000000 - 64 bytes written.
+ * - 000001 - 64 bytes written.
+ * - 000010 - 128 bytes written.
+ * - 000011 - 192 bytes written.
+ * - 111110 - 3968 bytes written.
+ * - 111111 - 4032 bytes written.
+ */
+//@{
+#define BP_ENET_TFWR_TFWR    (0U)          //!< Bit position for ENET_TFWR_TFWR.
+#define BM_ENET_TFWR_TFWR    (0x0000003FU) //!< Bit mask for ENET_TFWR_TFWR.
+#define BS_ENET_TFWR_TFWR    (6U)          //!< Bit field size in bits for ENET_TFWR_TFWR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TFWR_TFWR field.
+#define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
+#endif
+
+//! @brief Format value for bitfield ENET_TFWR_TFWR.
+#define BF_ENET_TFWR_TFWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_TFWR), uint32_t) & BM_ENET_TFWR_TFWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFWR field to a new value.
+#define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 1 - Enabled.
+ */
+//@{
+#define BP_ENET_TFWR_STRFWD  (8U)          //!< Bit position for ENET_TFWR_STRFWD.
+#define BM_ENET_TFWR_STRFWD  (0x00000100U) //!< Bit mask for ENET_TFWR_STRFWD.
+#define BS_ENET_TFWR_STRFWD  (1U)          //!< Bit field size in bits for ENET_TFWR_STRFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TFWR_STRFWD field.
+#define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_TFWR_STRFWD.
+#define BF_ENET_TFWR_STRFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_STRFWD), uint32_t) & BM_ENET_TFWR_STRFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STRFWD field to a new value.
+#define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RDSR - Receive Descriptor Ring Start Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+typedef union _hw_enet_rdsr
+{
+    uint32_t U;
+    struct _hw_enet_rdsr_bitfields
+    {
+        uint32_t RESERVED0 : 3;        //!< [2:0]
+        uint32_t R_DES_START : 29;     //!< [31:3]
+    } B;
+} hw_enet_rdsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+//@{
+#define HW_ENET_RDSR_ADDR(x)     (REGS_ENET_BASE(x) + 0x180U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RDSR(x)          (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
+#define HW_ENET_RDSR_RD(x)       (HW_ENET_RDSR(x).U)
+#define HW_ENET_RDSR_WR(x, v)    (HW_ENET_RDSR(x).U = (v))
+#define HW_ENET_RDSR_SET(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) |  (v)))
+#define HW_ENET_RDSR_CLR(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
+#define HW_ENET_RDSR_TOG(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+//@{
+#define BP_ENET_RDSR_R_DES_START (3U)      //!< Bit position for ENET_RDSR_R_DES_START.
+#define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_RDSR_R_DES_START.
+#define BS_ENET_RDSR_R_DES_START (29U)     //!< Bit field size in bits for ENET_RDSR_R_DES_START.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RDSR_R_DES_START field.
+#define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
+#endif
+
+//! @brief Format value for bitfield ENET_RDSR_R_DES_START.
+#define BF_ENET_RDSR_R_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDSR_R_DES_START), uint32_t) & BM_ENET_RDSR_R_DES_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the R_DES_START field to a new value.
+#define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+typedef union _hw_enet_tdsr
+{
+    uint32_t U;
+    struct _hw_enet_tdsr_bitfields
+    {
+        uint32_t RESERVED0 : 3;        //!< [2:0]
+        uint32_t X_DES_START : 29;     //!< [31:3]
+    } B;
+} hw_enet_tdsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+//@{
+#define HW_ENET_TDSR_ADDR(x)     (REGS_ENET_BASE(x) + 0x184U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TDSR(x)          (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
+#define HW_ENET_TDSR_RD(x)       (HW_ENET_TDSR(x).U)
+#define HW_ENET_TDSR_WR(x, v)    (HW_ENET_TDSR(x).U = (v))
+#define HW_ENET_TDSR_SET(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) |  (v)))
+#define HW_ENET_TDSR_CLR(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
+#define HW_ENET_TDSR_TOG(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+//@{
+#define BP_ENET_TDSR_X_DES_START (3U)      //!< Bit position for ENET_TDSR_X_DES_START.
+#define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_TDSR_X_DES_START.
+#define BS_ENET_TDSR_X_DES_START (29U)     //!< Bit field size in bits for ENET_TDSR_X_DES_START.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TDSR_X_DES_START field.
+#define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
+#endif
+
+//! @brief Format value for bitfield ENET_TDSR_X_DES_START.
+#define BF_ENET_TDSR_X_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDSR_X_DES_START), uint32_t) & BM_ENET_TDSR_X_DES_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the X_DES_START field to a new value.
+#define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MRBR - Maximum Receive Buffer Size Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+typedef union _hw_enet_mrbr
+{
+    uint32_t U;
+    struct _hw_enet_mrbr_bitfields
+    {
+        uint32_t RESERVED0 : 4;        //!< [3:0]
+        uint32_t R_BUF_SIZE : 10;      //!< [13:4]
+        uint32_t RESERVED1 : 18;       //!< [31:14]
+    } B;
+} hw_enet_mrbr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+//@{
+#define HW_ENET_MRBR_ADDR(x)     (REGS_ENET_BASE(x) + 0x188U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MRBR(x)          (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
+#define HW_ENET_MRBR_RD(x)       (HW_ENET_MRBR(x).U)
+#define HW_ENET_MRBR_WR(x, v)    (HW_ENET_MRBR(x).U = (v))
+#define HW_ENET_MRBR_SET(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) |  (v)))
+#define HW_ENET_MRBR_CLR(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
+#define HW_ENET_MRBR_TOG(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+//@{
+#define BP_ENET_MRBR_R_BUF_SIZE (4U)       //!< Bit position for ENET_MRBR_R_BUF_SIZE.
+#define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) //!< Bit mask for ENET_MRBR_R_BUF_SIZE.
+#define BS_ENET_MRBR_R_BUF_SIZE (10U)      //!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field.
+#define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
+#endif
+
+//! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE.
+#define BF_ENET_MRBR_R_BUF_SIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MRBR_R_BUF_SIZE), uint32_t) & BM_ENET_MRBR_R_BUF_SIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the R_BUF_SIZE field to a new value.
+#define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RSFL - Receive FIFO Section Full Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rsfl
+{
+    uint32_t U;
+    struct _hw_enet_rsfl_bitfields
+    {
+        uint32_t RX_SECTION_FULL : 8;  //!< [7:0] Value Of Receive FIFO
+                                       //! Section Full Threshold
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_enet_rsfl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+//@{
+#define HW_ENET_RSFL_ADDR(x)     (REGS_ENET_BASE(x) + 0x190U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RSFL(x)          (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
+#define HW_ENET_RSFL_RD(x)       (HW_ENET_RSFL(x).U)
+#define HW_ENET_RSFL_WR(x, v)    (HW_ENET_RSFL(x).U = (v))
+#define HW_ENET_RSFL_SET(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) |  (v)))
+#define HW_ENET_RSFL_CLR(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
+#define HW_ENET_RSFL_TOG(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+//@{
+#define BP_ENET_RSFL_RX_SECTION_FULL (0U)  //!< Bit position for ENET_RSFL_RX_SECTION_FULL.
+#define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) //!< Bit mask for ENET_RSFL_RX_SECTION_FULL.
+#define BS_ENET_RSFL_RX_SECTION_FULL (8U)  //!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field.
+#define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
+#endif
+
+//! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL.
+#define BF_ENET_RSFL_RX_SECTION_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSFL_RX_SECTION_FULL), uint32_t) & BM_ENET_RSFL_RX_SECTION_FULL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_SECTION_FULL field to a new value.
+#define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RSEM - Receive FIFO Section Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rsem
+{
+    uint32_t U;
+    struct _hw_enet_rsem_bitfields
+    {
+        uint32_t RX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
+                                       //! Section Empty Threshold
+        uint32_t RESERVED0 : 8;        //!< [15:8]
+        uint32_t STAT_SECTION_EMPTY : 5; //!< [20:16] RX Status FIFO Section
+                                       //! Empty Threshold
+        uint32_t RESERVED1 : 11;       //!< [31:21]
+    } B;
+} hw_enet_rsem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+//@{
+#define HW_ENET_RSEM_ADDR(x)     (REGS_ENET_BASE(x) + 0x194U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RSEM(x)          (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
+#define HW_ENET_RSEM_RD(x)       (HW_ENET_RSEM(x).U)
+#define HW_ENET_RSEM_WR(x, v)    (HW_ENET_RSEM(x).U = (v))
+#define HW_ENET_RSEM_SET(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) |  (v)))
+#define HW_ENET_RSEM_CLR(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
+#define HW_ENET_RSEM_TOG(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+//@{
+#define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) //!< Bit position for ENET_RSEM_RX_SECTION_EMPTY.
+#define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY.
+#define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field.
+#define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY.
+#define BF_ENET_RSEM_RX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_RX_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_RX_SECTION_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_SECTION_EMPTY field to a new value.
+#define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+//@{
+#define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) //!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY.
+#define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) //!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY.
+#define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) //!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field.
+#define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY.
+#define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_STAT_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STAT_SECTION_EMPTY field to a new value.
+#define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+typedef union _hw_enet_raem
+{
+    uint32_t U;
+    struct _hw_enet_raem_bitfields
+    {
+        uint32_t RX_ALMOST_EMPTY : 8;  //!< [7:0] Value Of The Receive FIFO
+                                       //! Almost Empty Threshold
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_enet_raem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+//@{
+#define HW_ENET_RAEM_ADDR(x)     (REGS_ENET_BASE(x) + 0x198U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RAEM(x)          (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
+#define HW_ENET_RAEM_RD(x)       (HW_ENET_RAEM(x).U)
+#define HW_ENET_RAEM_WR(x, v)    (HW_ENET_RAEM(x).U = (v))
+#define HW_ENET_RAEM_SET(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) |  (v)))
+#define HW_ENET_RAEM_CLR(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
+#define HW_ENET_RAEM_TOG(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+//@{
+#define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U)  //!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY.
+#define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY.
+#define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U)  //!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field.
+#define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY.
+#define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAEM_RX_ALMOST_EMPTY), uint32_t) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_ALMOST_EMPTY field to a new value.
+#define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RAFL - Receive FIFO Almost Full Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+typedef union _hw_enet_rafl
+{
+    uint32_t U;
+    struct _hw_enet_rafl_bitfields
+    {
+        uint32_t RX_ALMOST_FULL : 8;   //!< [7:0] Value Of The Receive FIFO
+                                       //! Almost Full Threshold
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_enet_rafl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+//@{
+#define HW_ENET_RAFL_ADDR(x)     (REGS_ENET_BASE(x) + 0x19CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RAFL(x)          (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
+#define HW_ENET_RAFL_RD(x)       (HW_ENET_RAFL(x).U)
+#define HW_ENET_RAFL_WR(x, v)    (HW_ENET_RAFL(x).U = (v))
+#define HW_ENET_RAFL_SET(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) |  (v)))
+#define HW_ENET_RAFL_CLR(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
+#define HW_ENET_RAFL_TOG(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+//@{
+#define BP_ENET_RAFL_RX_ALMOST_FULL (0U)   //!< Bit position for ENET_RAFL_RX_ALMOST_FULL.
+#define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_RAFL_RX_ALMOST_FULL.
+#define BS_ENET_RAFL_RX_ALMOST_FULL (8U)   //!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field.
+#define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
+#endif
+
+//! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL.
+#define BF_ENET_RAFL_RX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAFL_RX_ALMOST_FULL), uint32_t) & BM_ENET_RAFL_RX_ALMOST_FULL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_ALMOST_FULL field to a new value.
+#define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tsem
+{
+    uint32_t U;
+    struct _hw_enet_tsem_bitfields
+    {
+        uint32_t TX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Transmit FIFO
+                                       //! Section Empty Threshold
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_enet_tsem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+//@{
+#define HW_ENET_TSEM_ADDR(x)     (REGS_ENET_BASE(x) + 0x1A0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TSEM(x)          (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
+#define HW_ENET_TSEM_RD(x)       (HW_ENET_TSEM(x).U)
+#define HW_ENET_TSEM_WR(x, v)    (HW_ENET_TSEM(x).U = (v))
+#define HW_ENET_TSEM_SET(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) |  (v)))
+#define HW_ENET_TSEM_CLR(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
+#define HW_ENET_TSEM_TOG(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+//@{
+#define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) //!< Bit position for ENET_TSEM_TX_SECTION_EMPTY.
+#define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY.
+#define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field.
+#define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY.
+#define BF_ENET_TSEM_TX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TSEM_TX_SECTION_EMPTY), uint32_t) & BM_ENET_TSEM_TX_SECTION_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX_SECTION_EMPTY field to a new value.
+#define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+typedef union _hw_enet_taem
+{
+    uint32_t U;
+    struct _hw_enet_taem_bitfields
+    {
+        uint32_t TX_ALMOST_EMPTY : 8;  //!< [7:0] Value of Transmit FIFO
+                                       //! Almost Empty Threshold
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_enet_taem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+//@{
+#define HW_ENET_TAEM_ADDR(x)     (REGS_ENET_BASE(x) + 0x1A4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TAEM(x)          (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
+#define HW_ENET_TAEM_RD(x)       (HW_ENET_TAEM(x).U)
+#define HW_ENET_TAEM_WR(x, v)    (HW_ENET_TAEM(x).U = (v))
+#define HW_ENET_TAEM_SET(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) |  (v)))
+#define HW_ENET_TAEM_CLR(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
+#define HW_ENET_TAEM_TOG(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+//@{
+#define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U)  //!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY.
+#define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY.
+#define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U)  //!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field.
+#define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY.
+#define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAEM_TX_ALMOST_EMPTY), uint32_t) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX_ALMOST_EMPTY field to a new value.
+#define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+typedef union _hw_enet_tafl
+{
+    uint32_t U;
+    struct _hw_enet_tafl_bitfields
+    {
+        uint32_t TX_ALMOST_FULL : 8;   //!< [7:0] Value Of The Transmit FIFO
+                                       //! Almost Full Threshold
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_enet_tafl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+//@{
+#define HW_ENET_TAFL_ADDR(x)     (REGS_ENET_BASE(x) + 0x1A8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TAFL(x)          (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
+#define HW_ENET_TAFL_RD(x)       (HW_ENET_TAFL(x).U)
+#define HW_ENET_TAFL_WR(x, v)    (HW_ENET_TAFL(x).U = (v))
+#define HW_ENET_TAFL_SET(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) |  (v)))
+#define HW_ENET_TAFL_CLR(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
+#define HW_ENET_TAFL_TOG(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+//@{
+#define BP_ENET_TAFL_TX_ALMOST_FULL (0U)   //!< Bit position for ENET_TAFL_TX_ALMOST_FULL.
+#define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_TAFL_TX_ALMOST_FULL.
+#define BS_ENET_TAFL_TX_ALMOST_FULL (8U)   //!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field.
+#define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
+#endif
+
+//! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL.
+#define BF_ENET_TAFL_TX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAFL_TX_ALMOST_FULL), uint32_t) & BM_ENET_TAFL_TX_ALMOST_FULL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX_ALMOST_FULL field to a new value.
+#define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TIPG - Transmit Inter-Packet Gap
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+typedef union _hw_enet_tipg
+{
+    uint32_t U;
+    struct _hw_enet_tipg_bitfields
+    {
+        uint32_t IPG : 5;              //!< [4:0] Transmit Inter-Packet Gap
+        uint32_t RESERVED0 : 27;       //!< [31:5]
+    } B;
+} hw_enet_tipg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+//@{
+#define HW_ENET_TIPG_ADDR(x)     (REGS_ENET_BASE(x) + 0x1ACU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TIPG(x)          (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
+#define HW_ENET_TIPG_RD(x)       (HW_ENET_TIPG(x).U)
+#define HW_ENET_TIPG_WR(x, v)    (HW_ENET_TIPG(x).U = (v))
+#define HW_ENET_TIPG_SET(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) |  (v)))
+#define HW_ENET_TIPG_CLR(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
+#define HW_ENET_TIPG_TOG(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+//@{
+#define BP_ENET_TIPG_IPG     (0U)          //!< Bit position for ENET_TIPG_IPG.
+#define BM_ENET_TIPG_IPG     (0x0000001FU) //!< Bit mask for ENET_TIPG_IPG.
+#define BS_ENET_TIPG_IPG     (5U)          //!< Bit field size in bits for ENET_TIPG_IPG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TIPG_IPG field.
+#define BR_ENET_TIPG_IPG(x)  (HW_ENET_TIPG(x).B.IPG)
+#endif
+
+//! @brief Format value for bitfield ENET_TIPG_IPG.
+#define BF_ENET_TIPG_IPG(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TIPG_IPG), uint32_t) & BM_ENET_TIPG_IPG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPG field to a new value.
+#define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_FTRL - Frame Truncation Length
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+typedef union _hw_enet_ftrl
+{
+    uint32_t U;
+    struct _hw_enet_ftrl_bitfields
+    {
+        uint32_t TRUNC_FL : 14;        //!< [13:0] Frame Truncation Length
+        uint32_t RESERVED0 : 18;       //!< [31:14]
+    } B;
+} hw_enet_ftrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+//@{
+#define HW_ENET_FTRL_ADDR(x)     (REGS_ENET_BASE(x) + 0x1B0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_FTRL(x)          (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
+#define HW_ENET_FTRL_RD(x)       (HW_ENET_FTRL(x).U)
+#define HW_ENET_FTRL_WR(x, v)    (HW_ENET_FTRL(x).U = (v))
+#define HW_ENET_FTRL_SET(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) |  (v)))
+#define HW_ENET_FTRL_CLR(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
+#define HW_ENET_FTRL_TOG(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+//@{
+#define BP_ENET_FTRL_TRUNC_FL (0U)         //!< Bit position for ENET_FTRL_TRUNC_FL.
+#define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) //!< Bit mask for ENET_FTRL_TRUNC_FL.
+#define BS_ENET_FTRL_TRUNC_FL (14U)        //!< Bit field size in bits for ENET_FTRL_TRUNC_FL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_FTRL_TRUNC_FL field.
+#define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
+#endif
+
+//! @brief Format value for bitfield ENET_FTRL_TRUNC_FL.
+#define BF_ENET_FTRL_TRUNC_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_FTRL_TRUNC_FL), uint32_t) & BM_ENET_FTRL_TRUNC_FL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRUNC_FL field to a new value.
+#define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TACC - Transmit Accelerator Function Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+typedef union _hw_enet_tacc
+{
+    uint32_t U;
+    struct _hw_enet_tacc_bitfields
+    {
+        uint32_t SHIFT16 : 1;          //!< [0] TX FIFO Shift-16
+        uint32_t RESERVED0 : 2;        //!< [2:1]
+        uint32_t IPCHK : 1;            //!< [3]
+        uint32_t PROCHK : 1;           //!< [4]
+        uint32_t RESERVED1 : 27;       //!< [31:5]
+    } B;
+} hw_enet_tacc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+//@{
+#define HW_ENET_TACC_ADDR(x)     (REGS_ENET_BASE(x) + 0x1C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TACC(x)          (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
+#define HW_ENET_TACC_RD(x)       (HW_ENET_TACC(x).U)
+#define HW_ENET_TACC_WR(x, v)    (HW_ENET_TACC(x).U = (v))
+#define HW_ENET_TACC_SET(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) |  (v)))
+#define HW_ENET_TACC_CLR(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
+#define HW_ENET_TACC_TOG(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0 - Disabled.
+ * - 1 - Indicates to the transmit data FIFO that the written frames contain two
+ *     additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function allows
+ *     putting the frame payload on a 32-bit boundary in memory, as the 14-byte
+ *     Ethernet header is extended to a 16-byte header.
+ */
+//@{
+#define BP_ENET_TACC_SHIFT16 (0U)          //!< Bit position for ENET_TACC_SHIFT16.
+#define BM_ENET_TACC_SHIFT16 (0x00000001U) //!< Bit mask for ENET_TACC_SHIFT16.
+#define BS_ENET_TACC_SHIFT16 (1U)          //!< Bit field size in bits for ENET_TACC_SHIFT16.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TACC_SHIFT16 field.
+#define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
+#endif
+
+//! @brief Format value for bitfield ENET_TACC_SHIFT16.
+#define BF_ENET_TACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_SHIFT16), uint32_t) & BM_ENET_TACC_SHIFT16)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHIFT16 field to a new value.
+#define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0 - Checksum is not inserted.
+ * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
+ *     The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+//@{
+#define BP_ENET_TACC_IPCHK   (3U)          //!< Bit position for ENET_TACC_IPCHK.
+#define BM_ENET_TACC_IPCHK   (0x00000008U) //!< Bit mask for ENET_TACC_IPCHK.
+#define BS_ENET_TACC_IPCHK   (1U)          //!< Bit field size in bits for ENET_TACC_IPCHK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TACC_IPCHK field.
+#define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
+#endif
+
+//! @brief Format value for bitfield ENET_TACC_IPCHK.
+#define BF_ENET_TACC_IPCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_IPCHK), uint32_t) & BM_ENET_TACC_IPCHK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPCHK field to a new value.
+#define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0 - Checksum not inserted.
+ * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+//@{
+#define BP_ENET_TACC_PROCHK  (4U)          //!< Bit position for ENET_TACC_PROCHK.
+#define BM_ENET_TACC_PROCHK  (0x00000010U) //!< Bit mask for ENET_TACC_PROCHK.
+#define BS_ENET_TACC_PROCHK  (1U)          //!< Bit field size in bits for ENET_TACC_PROCHK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TACC_PROCHK field.
+#define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
+#endif
+
+//! @brief Format value for bitfield ENET_TACC_PROCHK.
+#define BF_ENET_TACC_PROCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_PROCHK), uint32_t) & BM_ENET_TACC_PROCHK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROCHK field to a new value.
+#define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RACC - Receive Accelerator Function Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_racc
+{
+    uint32_t U;
+    struct _hw_enet_racc_bitfields
+    {
+        uint32_t PADREM : 1;           //!< [0] Enable Padding Removal For Short IP
+                                       //! Frames
+        uint32_t IPDIS : 1;            //!< [1] Enable Discard Of Frames With Wrong IPv4
+                                       //! Header Checksum
+        uint32_t PRODIS : 1;           //!< [2] Enable Discard Of Frames With Wrong
+                                       //! Protocol Checksum
+        uint32_t RESERVED0 : 3;        //!< [5:3]
+        uint32_t LINEDIS : 1;          //!< [6] Enable Discard Of Frames With MAC
+                                       //! Layer Errors
+        uint32_t SHIFT16 : 1;          //!< [7] RX FIFO Shift-16
+        uint32_t RESERVED1 : 24;       //!< [31:8]
+    } B;
+} hw_enet_racc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+//@{
+#define HW_ENET_RACC_ADDR(x)     (REGS_ENET_BASE(x) + 0x1C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RACC(x)          (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
+#define HW_ENET_RACC_RD(x)       (HW_ENET_RACC(x).U)
+#define HW_ENET_RACC_WR(x, v)    (HW_ENET_RACC(x).U = (v))
+#define HW_ENET_RACC_SET(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) |  (v)))
+#define HW_ENET_RACC_CLR(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
+#define HW_ENET_RACC_TOG(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0 - Padding not removed.
+ * - 1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+//@{
+#define BP_ENET_RACC_PADREM  (0U)          //!< Bit position for ENET_RACC_PADREM.
+#define BM_ENET_RACC_PADREM  (0x00000001U) //!< Bit mask for ENET_RACC_PADREM.
+#define BS_ENET_RACC_PADREM  (1U)          //!< Bit field size in bits for ENET_RACC_PADREM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_PADREM field.
+#define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_PADREM.
+#define BF_ENET_RACC_PADREM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PADREM), uint32_t) & BM_ENET_RACC_PADREM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADREM field to a new value.
+#define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by this
+ *     setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+//@{
+#define BP_ENET_RACC_IPDIS   (1U)          //!< Bit position for ENET_RACC_IPDIS.
+#define BM_ENET_RACC_IPDIS   (0x00000002U) //!< Bit mask for ENET_RACC_IPDIS.
+#define BS_ENET_RACC_IPDIS   (1U)          //!< Bit field size in bits for ENET_RACC_IPDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_IPDIS field.
+#define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_IPDIS.
+#define BF_ENET_RACC_IPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_IPDIS), uint32_t) & BM_ENET_RACC_IPDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPDIS field to a new value.
+#define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0 - Frames with wrong checksum are not discarded.
+ * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
+ *     UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+//@{
+#define BP_ENET_RACC_PRODIS  (2U)          //!< Bit position for ENET_RACC_PRODIS.
+#define BM_ENET_RACC_PRODIS  (0x00000004U) //!< Bit mask for ENET_RACC_PRODIS.
+#define BS_ENET_RACC_PRODIS  (1U)          //!< Bit field size in bits for ENET_RACC_PRODIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_PRODIS field.
+#define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_PRODIS.
+#define BF_ENET_RACC_PRODIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PRODIS), uint32_t) & BM_ENET_RACC_PRODIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRODIS field to a new value.
+#define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0 - Frames with errors are not discarded.
+ * - 1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+//@{
+#define BP_ENET_RACC_LINEDIS (6U)          //!< Bit position for ENET_RACC_LINEDIS.
+#define BM_ENET_RACC_LINEDIS (0x00000040U) //!< Bit mask for ENET_RACC_LINEDIS.
+#define BS_ENET_RACC_LINEDIS (1U)          //!< Bit field size in bits for ENET_RACC_LINEDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_LINEDIS field.
+#define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_LINEDIS.
+#define BF_ENET_RACC_LINEDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_LINEDIS), uint32_t) & BM_ENET_RACC_LINEDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINEDIS field to a new value.
+#define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0 - Disabled.
+ * - 1 - Instructs the MAC to write two additional bytes in front of each frame
+ *     received into the RX FIFO.
+ */
+//@{
+#define BP_ENET_RACC_SHIFT16 (7U)          //!< Bit position for ENET_RACC_SHIFT16.
+#define BM_ENET_RACC_SHIFT16 (0x00000080U) //!< Bit mask for ENET_RACC_SHIFT16.
+#define BS_ENET_RACC_SHIFT16 (1U)          //!< Bit field size in bits for ENET_RACC_SHIFT16.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_SHIFT16 field.
+#define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_SHIFT16.
+#define BF_ENET_RACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_SHIFT16), uint32_t) & BM_ENET_RACC_SHIFT16)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHIFT16 field to a new value.
+#define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_packets
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_packets_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_packets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+//@{
+#define HW_ENET_RMON_T_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x204U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
+#define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) //!< Bit position for ENET_RMON_T_PACKETS_TXPKTS.
+#define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS.
+#define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field.
+#define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+typedef union _hw_enet_rmon_t_bc_pkt
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_bc_pkt_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Broadcast packets
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_bc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_T_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x208U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
+#define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U)  //!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS.
+#define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS.
+#define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field.
+#define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_mc_pkt
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_mc_pkt_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Multicast packets
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_mc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_T_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x20CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
+#define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U)  //!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS.
+#define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS.
+#define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field.
+#define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_crc_align
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_crc_align_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packets with CRC/align error
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_crc_align_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+//@{
+#define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x210U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
+#define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) //!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS.
+#define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS.
+#define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field.
+#define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_undersize
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_undersize_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_undersize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x214U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
+#define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS.
+#define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS.
+#define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field.
+#define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_oversize
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_oversize_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_oversize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_T_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x218U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
+#define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS.
+#define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS.
+#define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field.
+#define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+typedef union _hw_enet_rmon_t_frag
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_frag_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_frag_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+//@{
+#define HW_ENET_RMON_T_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x21CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_FRAG(x)   (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
+#define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_FRAG_TXPKTS (0U)    //!< Bit position for ENET_RMON_T_FRAG_TXPKTS.
+#define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_FRAG_TXPKTS.
+#define BS_ENET_RMON_T_FRAG_TXPKTS (16U)   //!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field.
+#define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_jab
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_jab_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_jab_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+//@{
+#define HW_ENET_RMON_T_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x220U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_JAB(x)    (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
+#define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_JAB_TXPKTS (0U)     //!< Bit position for ENET_RMON_T_JAB_TXPKTS.
+#define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_JAB_TXPKTS.
+#define BS_ENET_RMON_T_JAB_TXPKTS (16U)    //!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field.
+#define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_col
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_col_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_col_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+//@{
+#define HW_ENET_RMON_T_COL_ADDR(x) (REGS_ENET_BASE(x) + 0x224U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_COL(x)    (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
+#define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_COL_TXPKTS (0U)     //!< Bit position for ENET_RMON_T_COL_TXPKTS.
+#define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_COL_TXPKTS.
+#define BS_ENET_RMON_T_COL_TXPKTS (16U)    //!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field.
+#define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+typedef union _hw_enet_rmon_t_p64
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p64_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p64_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+//@{
+#define HW_ENET_RMON_T_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x228U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P64(x)    (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
+#define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P64_TXPKTS (0U)     //!< Bit position for ENET_RMON_T_P64_TXPKTS.
+#define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P64_TXPKTS.
+#define BS_ENET_RMON_T_P64_TXPKTS (16U)    //!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field.
+#define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p65to127
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p65to127_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p65to127_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+//@{
+#define HW_ENET_RMON_T_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x22CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
+#define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P65TO127_TXPKTS.
+#define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS.
+#define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field.
+#define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p128to255
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p128to255_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p128to255_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+//@{
+#define HW_ENET_RMON_T_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x230U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
+#define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P128TO255_TXPKTS.
+#define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS.
+#define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field.
+#define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p256to511
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p256to511_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p256to511_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+//@{
+#define HW_ENET_RMON_T_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x234U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
+#define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P256TO511_TXPKTS.
+#define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS.
+#define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field.
+#define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+typedef union _hw_enet_rmon_t_p512to1023
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p512to1023_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p512to1023_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+//@{
+#define HW_ENET_RMON_T_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x238U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
+#define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS.
+#define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS.
+#define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field.
+#define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p1024to2047
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p1024to2047_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p1024to2047_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+//@{
+#define HW_ENET_RMON_T_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x23CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
+#define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS.
+#define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS.
+#define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field.
+#define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p_gte2048
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_p_gte2048_bitfields
+    {
+        uint32_t TXPKTS : 16;          //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_t_p_gte2048_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+//@{
+#define HW_ENET_RMON_T_P_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x240U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
+#define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS.
+#define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS.
+#define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field.
+#define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_octets
+{
+    uint32_t U;
+    struct _hw_enet_rmon_t_octets_bitfields
+    {
+        uint32_t TXOCTS : 32;          //!< [31:0] Octet count
+    } B;
+} hw_enet_rmon_t_octets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+//@{
+#define HW_ENET_RMON_T_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x244U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
+#define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_OCTETS_TXOCTS (0U)  //!< Bit position for ENET_RMON_T_OCTETS_TXOCTS.
+#define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS.
+#define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) //!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field.
+#define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_frame_ok
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_frame_ok_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_frame_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+//@{
+#define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x24CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
+#define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT.
+#define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT.
+#define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field.
+#define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_1col
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_1col_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_1col_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+//@{
+#define HW_ENET_IEEE_T_1COL_ADDR(x) (REGS_ENET_BASE(x) + 0x250U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_1COL(x)   (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
+#define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_1COL_COUNT (0U)     //!< Bit position for ENET_IEEE_T_1COL_COUNT.
+#define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_1COL_COUNT.
+#define BS_ENET_IEEE_T_1COL_COUNT (16U)    //!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field.
+#define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_mcol
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_mcol_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_mcol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+//@{
+#define HW_ENET_IEEE_T_MCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x254U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_MCOL(x)   (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
+#define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_MCOL_COUNT (0U)     //!< Bit position for ENET_IEEE_T_MCOL_COUNT.
+#define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MCOL_COUNT.
+#define BS_ENET_IEEE_T_MCOL_COUNT (16U)    //!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field.
+#define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_def
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_def_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_def_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+//@{
+#define HW_ENET_IEEE_T_DEF_ADDR(x) (REGS_ENET_BASE(x) + 0x258U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_DEF(x)    (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
+#define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_DEF_COUNT (0U)      //!< Bit position for ENET_IEEE_T_DEF_COUNT.
+#define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_DEF_COUNT.
+#define BS_ENET_IEEE_T_DEF_COUNT (16U)     //!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field.
+#define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_lcol
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_lcol_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_lcol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+//@{
+#define HW_ENET_IEEE_T_LCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x25CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_LCOL(x)   (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
+#define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_LCOL_COUNT (0U)     //!< Bit position for ENET_IEEE_T_LCOL_COUNT.
+#define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_LCOL_COUNT.
+#define BS_ENET_IEEE_T_LCOL_COUNT (16U)    //!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field.
+#define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_excol
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_excol_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_excol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+//@{
+#define HW_ENET_IEEE_T_EXCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x260U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_EXCOL(x)  (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
+#define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_EXCOL_COUNT (0U)    //!< Bit position for ENET_IEEE_T_EXCOL_COUNT.
+#define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_EXCOL_COUNT.
+#define BS_ENET_IEEE_T_EXCOL_COUNT (16U)   //!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field.
+#define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_macerr
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_macerr_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_macerr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+//@{
+#define HW_ENET_IEEE_T_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x264U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
+#define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_MACERR_COUNT (0U)   //!< Bit position for ENET_IEEE_T_MACERR_COUNT.
+#define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MACERR_COUNT.
+#define BS_ENET_IEEE_T_MACERR_COUNT (16U)  //!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field.
+#define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_cserr
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_cserr_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_cserr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+//@{
+#define HW_ENET_IEEE_T_CSERR_ADDR(x) (REGS_ENET_BASE(x) + 0x268U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_CSERR(x)  (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
+#define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_CSERR_COUNT (0U)    //!< Bit position for ENET_IEEE_T_CSERR_COUNT.
+#define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_CSERR_COUNT.
+#define BS_ENET_IEEE_T_CSERR_COUNT (16U)   //!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field.
+#define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_fdxfc
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_fdxfc_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_t_fdxfc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+//@{
+#define HW_ENET_IEEE_T_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x270U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_FDXFC(x)  (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
+#define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_FDXFC_COUNT (0U)    //!< Bit position for ENET_IEEE_T_FDXFC_COUNT.
+#define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FDXFC_COUNT.
+#define BS_ENET_IEEE_T_FDXFC_COUNT (16U)   //!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field.
+#define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+typedef union _hw_enet_ieee_t_octets_ok
+{
+    uint32_t U;
+    struct _hw_enet_ieee_t_octets_ok_bitfields
+    {
+        uint32_t COUNT : 32;           //!< [31:0] Octet count
+    } B;
+} hw_enet_ieee_t_octets_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+//@{
+#define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x274U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
+#define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT.
+#define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT.
+#define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field.
+#define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_packets
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_packets_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_packets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+//@{
+#define HW_ENET_RMON_R_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x284U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
+#define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_PACKETS_COUNT (0U)  //!< Bit position for ENET_RMON_R_PACKETS_COUNT.
+#define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_PACKETS_COUNT.
+#define BS_ENET_RMON_R_PACKETS_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field.
+#define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_bc_pkt
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_bc_pkt_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_bc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_R_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x288U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
+#define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_BC_PKT_COUNT (0U)   //!< Bit position for ENET_RMON_R_BC_PKT_COUNT.
+#define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_BC_PKT_COUNT.
+#define BS_ENET_RMON_R_BC_PKT_COUNT (16U)  //!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field.
+#define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_mc_pkt
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_mc_pkt_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_mc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_R_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x28CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
+#define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_MC_PKT_COUNT (0U)   //!< Bit position for ENET_RMON_R_MC_PKT_COUNT.
+#define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_MC_PKT_COUNT.
+#define BS_ENET_RMON_R_MC_PKT_COUNT (16U)  //!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field.
+#define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_crc_align
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_crc_align_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_crc_align_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+//@{
+#define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x290U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
+#define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) //!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT.
+#define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT.
+#define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field.
+#define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_undersize
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_undersize_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_undersize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x294U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
+#define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT.
+#define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT.
+#define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field.
+#define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_oversize
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_oversize_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_oversize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_R_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x298U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
+#define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_OVERSIZE_COUNT.
+#define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT.
+#define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field.
+#define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_frag
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_frag_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_frag_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+//@{
+#define HW_ENET_RMON_R_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x29CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_FRAG(x)   (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
+#define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_FRAG_COUNT (0U)     //!< Bit position for ENET_RMON_R_FRAG_COUNT.
+#define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_FRAG_COUNT.
+#define BS_ENET_RMON_R_FRAG_COUNT (16U)    //!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field.
+#define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_jab
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_jab_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_jab_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+//@{
+#define HW_ENET_RMON_R_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x2A0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_JAB(x)    (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
+#define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_JAB_COUNT (0U)      //!< Bit position for ENET_RMON_R_JAB_COUNT.
+#define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_JAB_COUNT.
+#define BS_ENET_RMON_R_JAB_COUNT (16U)     //!< Bit field size in bits for ENET_RMON_R_JAB_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_JAB_COUNT field.
+#define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p64
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_p64_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_p64_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+//@{
+#define HW_ENET_RMON_R_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x2A8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P64(x)    (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
+#define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P64_COUNT (0U)      //!< Bit position for ENET_RMON_R_P64_COUNT.
+#define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P64_COUNT.
+#define BS_ENET_RMON_R_P64_COUNT (16U)     //!< Bit field size in bits for ENET_RMON_R_P64_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P64_COUNT field.
+#define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p65to127
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_p65to127_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_p65to127_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+//@{
+#define HW_ENET_RMON_R_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x2ACU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
+#define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P65TO127_COUNT (0U) //!< Bit position for ENET_RMON_R_P65TO127_COUNT.
+#define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P65TO127_COUNT.
+#define BS_ENET_RMON_R_P65TO127_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field.
+#define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p128to255
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_p128to255_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_p128to255_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+//@{
+#define HW_ENET_RMON_R_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x2B0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
+#define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P128TO255_COUNT (0U) //!< Bit position for ENET_RMON_R_P128TO255_COUNT.
+#define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P128TO255_COUNT.
+#define BS_ENET_RMON_R_P128TO255_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field.
+#define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p256to511
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_p256to511_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_p256to511_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+//@{
+#define HW_ENET_RMON_R_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x2B4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
+#define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P256TO511_COUNT (0U) //!< Bit position for ENET_RMON_R_P256TO511_COUNT.
+#define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P256TO511_COUNT.
+#define BS_ENET_RMON_R_P256TO511_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field.
+#define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p512to1023
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_p512to1023_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_p512to1023_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+//@{
+#define HW_ENET_RMON_R_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x2B8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
+#define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P512TO1023_COUNT (0U) //!< Bit position for ENET_RMON_R_P512TO1023_COUNT.
+#define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P512TO1023_COUNT.
+#define BS_ENET_RMON_R_P512TO1023_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field.
+#define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p1024to2047
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_p1024to2047_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_p1024to2047_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+//@{
+#define HW_ENET_RMON_R_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x2BCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
+#define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) //!< Bit position for ENET_RMON_R_P1024TO2047_COUNT.
+#define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT.
+#define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field.
+#define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_gte2048
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_gte2048_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Packet count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_rmon_r_gte2048_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_GTE2048 register
+ */
+//@{
+#define HW_ENET_RMON_R_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x2C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_GTE2048(x) (*(__I hw_enet_rmon_r_gte2048_t *) HW_ENET_RMON_R_GTE2048_ADDR(x))
+#define HW_ENET_RMON_R_GTE2048_RD(x) (HW_ENET_RMON_R_GTE2048(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_GTE2048, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_GTE2048_COUNT (0U)  //!< Bit position for ENET_RMON_R_GTE2048_COUNT.
+#define BM_ENET_RMON_R_GTE2048_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_GTE2048_COUNT.
+#define BS_ENET_RMON_R_GTE2048_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_GTE2048_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_GTE2048_COUNT field.
+#define BR_ENET_RMON_R_GTE2048_COUNT(x) (HW_ENET_RMON_R_GTE2048(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_octets
+{
+    uint32_t U;
+    struct _hw_enet_rmon_r_octets_bitfields
+    {
+        uint32_t COUNT : 32;           //!< [31:0] Octet count
+    } B;
+} hw_enet_rmon_r_octets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+//@{
+#define HW_ENET_RMON_R_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x2C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
+#define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_OCTETS_COUNT (0U)   //!< Bit position for ENET_RMON_R_OCTETS_COUNT.
+#define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_R_OCTETS_COUNT.
+#define BS_ENET_RMON_R_OCTETS_COUNT (32U)  //!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field.
+#define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+typedef union _hw_enet_ieee_r_drop
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_drop_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_r_drop_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+//@{
+#define HW_ENET_IEEE_R_DROP_ADDR(x) (REGS_ENET_BASE(x) + 0x2C8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_DROP(x)   (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
+#define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_DROP_COUNT (0U)     //!< Bit position for ENET_IEEE_R_DROP_COUNT.
+#define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_DROP_COUNT.
+#define BS_ENET_IEEE_R_DROP_COUNT (16U)    //!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field.
+#define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_frame_ok
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_frame_ok_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_r_frame_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+//@{
+#define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2CCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
+#define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT.
+#define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT.
+#define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field.
+#define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_crc
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_crc_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_r_crc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+//@{
+#define HW_ENET_IEEE_R_CRC_ADDR(x) (REGS_ENET_BASE(x) + 0x2D0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_CRC(x)    (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
+#define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_CRC_COUNT (0U)      //!< Bit position for ENET_IEEE_R_CRC_COUNT.
+#define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_CRC_COUNT.
+#define BS_ENET_IEEE_R_CRC_COUNT (16U)     //!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field.
+#define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_align
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_align_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_r_align_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+//@{
+#define HW_ENET_IEEE_R_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x2D4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_ALIGN(x)  (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
+#define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_ALIGN_COUNT (0U)    //!< Bit position for ENET_IEEE_R_ALIGN_COUNT.
+#define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_ALIGN_COUNT.
+#define BS_ENET_IEEE_R_ALIGN_COUNT (16U)   //!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field.
+#define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_macerr
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_macerr_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_r_macerr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+//@{
+#define HW_ENET_IEEE_R_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x2D8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
+#define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_MACERR_COUNT (0U)   //!< Bit position for ENET_IEEE_R_MACERR_COUNT.
+#define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_MACERR_COUNT.
+#define BS_ENET_IEEE_R_MACERR_COUNT (16U)  //!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field.
+#define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_fdxfc
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_fdxfc_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Pause frame count
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_enet_ieee_r_fdxfc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+//@{
+#define HW_ENET_IEEE_R_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x2DCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_FDXFC(x)  (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
+#define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_FDXFC_COUNT (0U)    //!< Bit position for ENET_IEEE_R_FDXFC_COUNT.
+#define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FDXFC_COUNT.
+#define BS_ENET_IEEE_R_FDXFC_COUNT (16U)   //!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field.
+#define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_octets_ok
+{
+    uint32_t U;
+    struct _hw_enet_ieee_r_octets_ok_bitfields
+    {
+        uint32_t COUNT : 32;           //!< [31:0] Octet count
+    } B;
+} hw_enet_ieee_r_octets_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+//@{
+#define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2E0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
+#define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT.
+#define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT.
+#define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field.
+#define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATCR - Adjustable Timer Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+typedef union _hw_enet_atcr
+{
+    uint32_t U;
+    struct _hw_enet_atcr_bitfields
+    {
+        uint32_t EN : 1;               //!< [0] Enable Timer
+        uint32_t RESERVED0 : 1;        //!< [1]
+        uint32_t OFFEN : 1;            //!< [2] Enable One-Shot Offset Event
+        uint32_t OFFRST : 1;           //!< [3] Reset Timer On Offset Event
+        uint32_t PEREN : 1;            //!< [4] Enable Periodical Event
+        uint32_t RESERVED1 : 2;        //!< [6:5]
+        uint32_t PINPER : 1;           //!< [7]
+        uint32_t RESERVED2 : 1;        //!< [8]
+        uint32_t RESTART : 1;          //!< [9] Reset Timer
+        uint32_t RESERVED3 : 1;        //!< [10]
+        uint32_t CAPTURE : 1;          //!< [11] Capture Timer Value
+        uint32_t RESERVED4 : 1;        //!< [12]
+        uint32_t SLAVE : 1;            //!< [13] Enable Timer Slave Mode
+        uint32_t RESERVED5 : 18;       //!< [31:14]
+    } B;
+} hw_enet_atcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+//@{
+#define HW_ENET_ATCR_ADDR(x)     (REGS_ENET_BASE(x) + 0x400U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATCR(x)          (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
+#define HW_ENET_ATCR_RD(x)       (HW_ENET_ATCR(x).U)
+#define HW_ENET_ATCR_WR(x, v)    (HW_ENET_ATCR(x).U = (v))
+#define HW_ENET_ATCR_SET(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) |  (v)))
+#define HW_ENET_ATCR_CLR(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
+#define HW_ENET_ATCR_TOG(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0 - The timer stops at the current value.
+ * - 1 - The timer starts incrementing.
+ */
+//@{
+#define BP_ENET_ATCR_EN      (0U)          //!< Bit position for ENET_ATCR_EN.
+#define BM_ENET_ATCR_EN      (0x00000001U) //!< Bit mask for ENET_ATCR_EN.
+#define BS_ENET_ATCR_EN      (1U)          //!< Bit field size in bits for ENET_ATCR_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_EN field.
+#define BR_ENET_ATCR_EN(x)   (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_EN.
+#define BF_ENET_ATCR_EN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_EN), uint32_t) & BM_ENET_ATCR_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disable.
+ * - 1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so no
+ *     further event occurs until the field is set again. The timer offset value
+ *     must be set before setting this field.
+ */
+//@{
+#define BP_ENET_ATCR_OFFEN   (2U)          //!< Bit position for ENET_ATCR_OFFEN.
+#define BM_ENET_ATCR_OFFEN   (0x00000004U) //!< Bit mask for ENET_ATCR_OFFEN.
+#define BS_ENET_ATCR_OFFEN   (1U)          //!< Bit field size in bits for ENET_ATCR_OFFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_OFFEN field.
+#define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_OFFEN.
+#define BF_ENET_ATCR_OFFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFEN), uint32_t) & BM_ENET_ATCR_OFFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFFEN field to a new value.
+#define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
+ *     when the offset is reached.
+ * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+//@{
+#define BP_ENET_ATCR_OFFRST  (3U)          //!< Bit position for ENET_ATCR_OFFRST.
+#define BM_ENET_ATCR_OFFRST  (0x00000008U) //!< Bit mask for ENET_ATCR_OFFRST.
+#define BS_ENET_ATCR_OFFRST  (1U)          //!< Bit field size in bits for ENET_ATCR_OFFRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_OFFRST field.
+#define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_OFFRST.
+#define BF_ENET_ATCR_OFFRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFRST), uint32_t) & BM_ENET_ATCR_OFFRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFFRST field to a new value.
+#define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disable.
+ * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
+ *     signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+//@{
+#define BP_ENET_ATCR_PEREN   (4U)          //!< Bit position for ENET_ATCR_PEREN.
+#define BM_ENET_ATCR_PEREN   (0x00000010U) //!< Bit mask for ENET_ATCR_PEREN.
+#define BS_ENET_ATCR_PEREN   (1U)          //!< Bit field size in bits for ENET_ATCR_PEREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_PEREN field.
+#define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_PEREN.
+#define BF_ENET_ATCR_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PEREN), uint32_t) & BM_ENET_ATCR_PEREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PEREN field to a new value.
+#define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0 - Disable.
+ * - 1 - Enable.
+ */
+//@{
+#define BP_ENET_ATCR_PINPER  (7U)          //!< Bit position for ENET_ATCR_PINPER.
+#define BM_ENET_ATCR_PINPER  (0x00000080U) //!< Bit mask for ENET_ATCR_PINPER.
+#define BS_ENET_ATCR_PINPER  (1U)          //!< Bit field size in bits for ENET_ATCR_PINPER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_PINPER field.
+#define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_PINPER.
+#define BF_ENET_ATCR_PINPER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PINPER), uint32_t) & BM_ENET_ATCR_PINPER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PINPER field to a new value.
+#define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+//@{
+#define BP_ENET_ATCR_RESTART (9U)          //!< Bit position for ENET_ATCR_RESTART.
+#define BM_ENET_ATCR_RESTART (0x00000200U) //!< Bit mask for ENET_ATCR_RESTART.
+#define BS_ENET_ATCR_RESTART (1U)          //!< Bit field size in bits for ENET_ATCR_RESTART.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_RESTART field.
+#define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_RESTART.
+#define BF_ENET_ATCR_RESTART(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_RESTART), uint32_t) & BM_ENET_ATCR_RESTART)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESTART field to a new value.
+#define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - The current time is captured and can be read from the ATVR register.
+ */
+//@{
+#define BP_ENET_ATCR_CAPTURE (11U)         //!< Bit position for ENET_ATCR_CAPTURE.
+#define BM_ENET_ATCR_CAPTURE (0x00000800U) //!< Bit mask for ENET_ATCR_CAPTURE.
+#define BS_ENET_ATCR_CAPTURE (1U)          //!< Bit field size in bits for ENET_ATCR_CAPTURE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_CAPTURE field.
+#define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_CAPTURE.
+#define BF_ENET_ATCR_CAPTURE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_CAPTURE), uint32_t) & BM_ENET_ATCR_CAPTURE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAPTURE field to a new value.
+#define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 1 - The internal timer is disabled and the externally provided timer value
+ *     is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+//@{
+#define BP_ENET_ATCR_SLAVE   (13U)         //!< Bit position for ENET_ATCR_SLAVE.
+#define BM_ENET_ATCR_SLAVE   (0x00002000U) //!< Bit mask for ENET_ATCR_SLAVE.
+#define BS_ENET_ATCR_SLAVE   (1U)          //!< Bit field size in bits for ENET_ATCR_SLAVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_SLAVE field.
+#define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_SLAVE.
+#define BF_ENET_ATCR_SLAVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_SLAVE), uint32_t) & BM_ENET_ATCR_SLAVE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLAVE field to a new value.
+#define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATVR - Timer Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atvr
+{
+    uint32_t U;
+    struct _hw_enet_atvr_bitfields
+    {
+        uint32_t ATIME : 32;           //!< [31:0]
+    } B;
+} hw_enet_atvr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+//@{
+#define HW_ENET_ATVR_ADDR(x)     (REGS_ENET_BASE(x) + 0x404U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATVR(x)          (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
+#define HW_ENET_ATVR_RD(x)       (HW_ENET_ATVR(x).U)
+#define HW_ENET_ATVR_WR(x, v)    (HW_ENET_ATVR(x).U = (v))
+#define HW_ENET_ATVR_SET(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) |  (v)))
+#define HW_ENET_ATVR_CLR(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
+#define HW_ENET_ATVR_TOG(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATVR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATVR, field ATIME[31:0] (RW)
+ *
+ * A write sets the timer. A read returns the last captured value. To read the
+ * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
+ * this register.
+ */
+//@{
+#define BP_ENET_ATVR_ATIME   (0U)          //!< Bit position for ENET_ATVR_ATIME.
+#define BM_ENET_ATVR_ATIME   (0xFFFFFFFFU) //!< Bit mask for ENET_ATVR_ATIME.
+#define BS_ENET_ATVR_ATIME   (32U)         //!< Bit field size in bits for ENET_ATVR_ATIME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATVR_ATIME field.
+#define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_ATVR_ATIME.
+#define BF_ENET_ATVR_ATIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATVR_ATIME), uint32_t) & BM_ENET_ATVR_ATIME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATIME field to a new value.
+#define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATOFF - Timer Offset Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atoff
+{
+    uint32_t U;
+    struct _hw_enet_atoff_bitfields
+    {
+        uint32_t OFFSET : 32;          //!< [31:0]
+    } B;
+} hw_enet_atoff_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+//@{
+#define HW_ENET_ATOFF_ADDR(x)    (REGS_ENET_BASE(x) + 0x408U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATOFF(x)         (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
+#define HW_ENET_ATOFF_RD(x)      (HW_ENET_ATOFF(x).U)
+#define HW_ENET_ATOFF_WR(x, v)   (HW_ENET_ATOFF(x).U = (v))
+#define HW_ENET_ATOFF_SET(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) |  (v)))
+#define HW_ENET_ATOFF_CLR(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
+#define HW_ENET_ATOFF_TOG(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATOFF bitfields
+ */
+
+/*!
+ * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
+ *
+ * Offset value for one-shot event generation. When the timer reaches the value,
+ * an event can be generated to reset the counter. If the increment value in
+ * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
+ */
+//@{
+#define BP_ENET_ATOFF_OFFSET (0U)          //!< Bit position for ENET_ATOFF_OFFSET.
+#define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) //!< Bit mask for ENET_ATOFF_OFFSET.
+#define BS_ENET_ATOFF_OFFSET (32U)         //!< Bit field size in bits for ENET_ATOFF_OFFSET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATOFF_OFFSET field.
+#define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_ATOFF_OFFSET.
+#define BF_ENET_ATOFF_OFFSET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATOFF_OFFSET), uint32_t) & BM_ENET_ATOFF_OFFSET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFFSET field to a new value.
+#define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATPER - Timer Period Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+typedef union _hw_enet_atper
+{
+    uint32_t U;
+    struct _hw_enet_atper_bitfields
+    {
+        uint32_t PERIOD : 32;          //!< [31:0]
+    } B;
+} hw_enet_atper_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+//@{
+#define HW_ENET_ATPER_ADDR(x)    (REGS_ENET_BASE(x) + 0x40CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATPER(x)         (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
+#define HW_ENET_ATPER_RD(x)      (HW_ENET_ATPER(x).U)
+#define HW_ENET_ATPER_WR(x, v)   (HW_ENET_ATPER(x).U = (v))
+#define HW_ENET_ATPER_SET(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) |  (v)))
+#define HW_ENET_ATPER_CLR(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
+#define HW_ENET_ATPER_TOG(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATPER bitfields
+ */
+
+/*!
+ * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
+ *
+ * Value for generating periodic events. Each instance the timer reaches this
+ * value, the period event occurs and the timer restarts. If the increment value in
+ * ATINC is given in true nanoseconds, this value is also given in true
+ * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
+ * a timer wrap around of one second. The increment value set in ATINC should be
+ * set to the true nanoseconds of the period of clock ts_clk, hence implementing
+ * a true 1 second counter.
+ */
+//@{
+#define BP_ENET_ATPER_PERIOD (0U)          //!< Bit position for ENET_ATPER_PERIOD.
+#define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) //!< Bit mask for ENET_ATPER_PERIOD.
+#define BS_ENET_ATPER_PERIOD (32U)         //!< Bit field size in bits for ENET_ATPER_PERIOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATPER_PERIOD field.
+#define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_ATPER_PERIOD.
+#define BF_ENET_ATPER_PERIOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATPER_PERIOD), uint32_t) & BM_ENET_ATPER_PERIOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PERIOD field to a new value.
+#define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATCOR - Timer Correction Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atcor
+{
+    uint32_t U;
+    struct _hw_enet_atcor_bitfields
+    {
+        uint32_t COR : 31;             //!< [30:0] Correction Counter Wrap-Around Value
+        uint32_t RESERVED0 : 1;        //!< [31]
+    } B;
+} hw_enet_atcor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+//@{
+#define HW_ENET_ATCOR_ADDR(x)    (REGS_ENET_BASE(x) + 0x410U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATCOR(x)         (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
+#define HW_ENET_ATCOR_RD(x)      (HW_ENET_ATCOR(x).U)
+#define HW_ENET_ATCOR_WR(x, v)   (HW_ENET_ATCOR(x).U = (v))
+#define HW_ENET_ATCOR_SET(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) |  (v)))
+#define HW_ENET_ATCOR_CLR(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
+#define HW_ENET_ATCOR_TOG(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+//@{
+#define BP_ENET_ATCOR_COR    (0U)          //!< Bit position for ENET_ATCOR_COR.
+#define BM_ENET_ATCOR_COR    (0x7FFFFFFFU) //!< Bit mask for ENET_ATCOR_COR.
+#define BS_ENET_ATCOR_COR    (31U)         //!< Bit field size in bits for ENET_ATCOR_COR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCOR_COR field.
+#define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
+#endif
+
+//! @brief Format value for bitfield ENET_ATCOR_COR.
+#define BF_ENET_ATCOR_COR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCOR_COR), uint32_t) & BM_ENET_ATCOR_COR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COR field to a new value.
+#define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATINC - Time-Stamping Clock Period Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atinc
+{
+    uint32_t U;
+    struct _hw_enet_atinc_bitfields
+    {
+        uint32_t INC : 7;              //!< [6:0] Clock Period Of The Timestamping Clock
+                                       //! (ts_clk) In Nanoseconds
+        uint32_t RESERVED0 : 1;        //!< [7]
+        uint32_t INC_CORR : 7;         //!< [14:8] Correction Increment Value
+        uint32_t RESERVED1 : 17;       //!< [31:15]
+    } B;
+} hw_enet_atinc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+//@{
+#define HW_ENET_ATINC_ADDR(x)    (REGS_ENET_BASE(x) + 0x414U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATINC(x)         (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
+#define HW_ENET_ATINC_RD(x)      (HW_ENET_ATINC(x).U)
+#define HW_ENET_ATINC_WR(x, v)   (HW_ENET_ATINC(x).U = (v))
+#define HW_ENET_ATINC_SET(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) |  (v)))
+#define HW_ENET_ATINC_CLR(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
+#define HW_ENET_ATINC_TOG(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+//@{
+#define BP_ENET_ATINC_INC    (0U)          //!< Bit position for ENET_ATINC_INC.
+#define BM_ENET_ATINC_INC    (0x0000007FU) //!< Bit mask for ENET_ATINC_INC.
+#define BS_ENET_ATINC_INC    (7U)          //!< Bit field size in bits for ENET_ATINC_INC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATINC_INC field.
+#define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
+#endif
+
+//! @brief Format value for bitfield ENET_ATINC_INC.
+#define BF_ENET_ATINC_INC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC), uint32_t) & BM_ENET_ATINC_INC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INC field to a new value.
+#define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+//@{
+#define BP_ENET_ATINC_INC_CORR (8U)        //!< Bit position for ENET_ATINC_INC_CORR.
+#define BM_ENET_ATINC_INC_CORR (0x00007F00U) //!< Bit mask for ENET_ATINC_INC_CORR.
+#define BS_ENET_ATINC_INC_CORR (7U)        //!< Bit field size in bits for ENET_ATINC_INC_CORR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATINC_INC_CORR field.
+#define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
+#endif
+
+//! @brief Format value for bitfield ENET_ATINC_INC_CORR.
+#define BF_ENET_ATINC_INC_CORR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC_CORR), uint32_t) & BM_ENET_ATINC_INC_CORR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INC_CORR field to a new value.
+#define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atstmp
+{
+    uint32_t U;
+    struct _hw_enet_atstmp_bitfields
+    {
+        uint32_t TIMESTAMP : 32;       //!< [31:0]
+    } B;
+} hw_enet_atstmp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+//@{
+#define HW_ENET_ATSTMP_ADDR(x)   (REGS_ENET_BASE(x) + 0x418U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATSTMP(x)        (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
+#define HW_ENET_ATSTMP_RD(x)     (HW_ENET_ATSTMP(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATSTMP bitfields
+ */
+
+/*!
+ * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
+ *
+ * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
+ * This register is only valid when EIR[TS_AVAIL] is set.
+ */
+//@{
+#define BP_ENET_ATSTMP_TIMESTAMP (0U)      //!< Bit position for ENET_ATSTMP_TIMESTAMP.
+#define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) //!< Bit mask for ENET_ATSTMP_TIMESTAMP.
+#define BS_ENET_ATSTMP_TIMESTAMP (32U)     //!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field.
+#define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TGSR - Timer Global Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tgsr
+{
+    uint32_t U;
+    struct _hw_enet_tgsr_bitfields
+    {
+        uint32_t TF0 : 1;              //!< [0] Copy Of Timer Flag For Channel 0
+        uint32_t TF1 : 1;              //!< [1] Copy Of Timer Flag For Channel 1
+        uint32_t TF2 : 1;              //!< [2] Copy Of Timer Flag For Channel 2
+        uint32_t TF3 : 1;              //!< [3] Copy Of Timer Flag For Channel 3
+        uint32_t RESERVED0 : 28;       //!< [31:4]
+    } B;
+} hw_enet_tgsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+//@{
+#define HW_ENET_TGSR_ADDR(x)     (REGS_ENET_BASE(x) + 0x604U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TGSR(x)          (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
+#define HW_ENET_TGSR_RD(x)       (HW_ENET_TGSR(x).U)
+#define HW_ENET_TGSR_WR(x, v)    (HW_ENET_TGSR(x).U = (v))
+#define HW_ENET_TGSR_SET(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) |  (v)))
+#define HW_ENET_TGSR_CLR(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
+#define HW_ENET_TGSR_TOG(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 0 is clear
+ * - 1 - Timer Flag for Channel 0 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF0     (0U)          //!< Bit position for ENET_TGSR_TF0.
+#define BM_ENET_TGSR_TF0     (0x00000001U) //!< Bit mask for ENET_TGSR_TF0.
+#define BS_ENET_TGSR_TF0     (1U)          //!< Bit field size in bits for ENET_TGSR_TF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF0 field.
+#define BR_ENET_TGSR_TF0(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF0.
+#define BF_ENET_TGSR_TF0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF0), uint32_t) & BM_ENET_TGSR_TF0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF0 field to a new value.
+#define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 1 is clear
+ * - 1 - Timer Flag for Channel 1 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF1     (1U)          //!< Bit position for ENET_TGSR_TF1.
+#define BM_ENET_TGSR_TF1     (0x00000002U) //!< Bit mask for ENET_TGSR_TF1.
+#define BS_ENET_TGSR_TF1     (1U)          //!< Bit field size in bits for ENET_TGSR_TF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF1 field.
+#define BR_ENET_TGSR_TF1(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF1.
+#define BF_ENET_TGSR_TF1(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF1), uint32_t) & BM_ENET_TGSR_TF1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF1 field to a new value.
+#define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 2 is clear
+ * - 1 - Timer Flag for Channel 2 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF2     (2U)          //!< Bit position for ENET_TGSR_TF2.
+#define BM_ENET_TGSR_TF2     (0x00000004U) //!< Bit mask for ENET_TGSR_TF2.
+#define BS_ENET_TGSR_TF2     (1U)          //!< Bit field size in bits for ENET_TGSR_TF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF2 field.
+#define BR_ENET_TGSR_TF2(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF2.
+#define BF_ENET_TGSR_TF2(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF2), uint32_t) & BM_ENET_TGSR_TF2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF2 field to a new value.
+#define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 3 is clear
+ * - 1 - Timer Flag for Channel 3 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF3     (3U)          //!< Bit position for ENET_TGSR_TF3.
+#define BM_ENET_TGSR_TF3     (0x00000008U) //!< Bit mask for ENET_TGSR_TF3.
+#define BS_ENET_TGSR_TF3     (1U)          //!< Bit field size in bits for ENET_TGSR_TF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF3 field.
+#define BR_ENET_TGSR_TF3(x)  (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF3.
+#define BF_ENET_TGSR_TF3(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF3), uint32_t) & BM_ENET_TGSR_TF3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF3 field to a new value.
+#define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TCSRn - Timer Control Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tcsrn
+{
+    uint32_t U;
+    struct _hw_enet_tcsrn_bitfields
+    {
+        uint32_t TDRE : 1;             //!< [0] Timer DMA Request Enable
+        uint32_t RESERVED0 : 1;        //!< [1]
+        uint32_t TMODE : 4;            //!< [5:2] Timer Mode
+        uint32_t TIE : 1;              //!< [6] Timer Interrupt Enable
+        uint32_t TF : 1;               //!< [7] Timer Flag
+        uint32_t RESERVED1 : 24;       //!< [31:8]
+    } B;
+} hw_enet_tcsrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TCSRn register
+ */
+//@{
+#define HW_ENET_TCSRn_COUNT (4U)
+
+#define HW_ENET_TCSRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x608U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TCSRn(x, n)      (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
+#define HW_ENET_TCSRn_RD(x, n)   (HW_ENET_TCSRn(x, n).U)
+#define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
+#define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) |  (v)))
+#define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
+#define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TCSRn bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSRn, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0 - DMA request is disabled
+ * - 1 - DMA request is enabled
+ */
+//@{
+#define BP_ENET_TCSRn_TDRE   (0U)          //!< Bit position for ENET_TCSRn_TDRE.
+#define BM_ENET_TCSRn_TDRE   (0x00000001U) //!< Bit mask for ENET_TCSRn_TDRE.
+#define BS_ENET_TCSRn_TDRE   (1U)          //!< Bit field size in bits for ENET_TCSRn_TDRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TDRE field.
+#define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TDRE.
+#define BF_ENET_TCSRn_TDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TDRE), uint32_t) & BM_ENET_TCSRn_TDRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDRE field to a new value.
+#define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0000 - Timer Channel is disabled.
+ * - 0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0100 - Timer Channel is configured for Output Compare - software only
+ * - 0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 1000 - Reserved
+ * - 1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 1100 - Reserved
+ * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
+ *     compare for one 1588 clock cycle
+ * - 1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+//@{
+#define BP_ENET_TCSRn_TMODE  (2U)          //!< Bit position for ENET_TCSRn_TMODE.
+#define BM_ENET_TCSRn_TMODE  (0x0000003CU) //!< Bit mask for ENET_TCSRn_TMODE.
+#define BS_ENET_TCSRn_TMODE  (4U)          //!< Bit field size in bits for ENET_TCSRn_TMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TMODE field.
+#define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TMODE.
+#define BF_ENET_TCSRn_TMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TMODE), uint32_t) & BM_ENET_TCSRn_TMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TMODE field to a new value.
+#define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCSRn, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0 - Interrupt is disabled
+ * - 1 - Interrupt is enabled
+ */
+//@{
+#define BP_ENET_TCSRn_TIE    (6U)          //!< Bit position for ENET_TCSRn_TIE.
+#define BM_ENET_TCSRn_TIE    (0x00000040U) //!< Bit mask for ENET_TCSRn_TIE.
+#define BS_ENET_TCSRn_TIE    (1U)          //!< Bit field size in bits for ENET_TCSRn_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TIE field.
+#define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TIE.
+#define BF_ENET_TCSRn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TIE), uint32_t) & BM_ENET_TCSRn_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCSRn, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0 - Input Capture or Output Compare has not occurred
+ * - 1 - Input Capture or Output Compare has occurred
+ */
+//@{
+#define BP_ENET_TCSRn_TF     (7U)          //!< Bit position for ENET_TCSRn_TF.
+#define BM_ENET_TCSRn_TF     (0x00000080U) //!< Bit mask for ENET_TCSRn_TF.
+#define BS_ENET_TCSRn_TF     (1U)          //!< Bit field size in bits for ENET_TCSRn_TF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TF field.
+#define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TF.
+#define BF_ENET_TCSRn_TF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TF), uint32_t) & BM_ENET_TCSRn_TF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF field to a new value.
+#define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TCCRn - Timer Compare Capture Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tccrn
+{
+    uint32_t U;
+    struct _hw_enet_tccrn_bitfields
+    {
+        uint32_t TCC : 32;             //!< [31:0] Timer Capture Compare
+    } B;
+} hw_enet_tccrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TCCRn register
+ */
+//@{
+#define HW_ENET_TCCRn_COUNT (4U)
+
+#define HW_ENET_TCCRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x60CU + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TCCRn(x, n)      (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
+#define HW_ENET_TCCRn_RD(x, n)   (HW_ENET_TCCRn(x, n).U)
+#define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
+#define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) |  (v)))
+#define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
+#define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TCCRn bitfields
+ */
+
+/*!
+ * @name Register ENET_TCCRn, field TCC[31:0] (RW)
+ *
+ * This register is double buffered between the module clock and 1588 clock
+ * domains. When configured for compare, the 1588 clock domain updates with the value
+ * in the module clock domain whenever the Timer Channel is first enabled and on
+ * each subsequent compare. Write to this register with the first compare value
+ * before enabling the Timer Channel. When the Timer Channel is enabled, write
+ * the second compare value either immediately, or at least before the first
+ * compare occurs. After each compare, write the next compare value before the previous
+ * compare occurs and before clearing the Timer Flag. The compare occurs one
+ * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
+ * the 1588 clock domain. If the compare value is less than the value of the
+ * 1588 Counter when the Timer Channel is first enabled, then the compare does not
+ * occur until following the next overflow of the 1588 Counter. If the compare
+ * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
+ * the compare value is less than the value of the IEEE 1588 Counter after the
+ * overflow, then the compare occurs one 1588 clock cycle following the overflow.
+ * When configured for Capture, the value of the IEEE 1588 Counter is captured into
+ * the 1588 clock domain and then updated into the module clock domain, provided
+ * the Timer Flag is clear. Always read the capture value before clearing the
+ * Timer Flag.
+ */
+//@{
+#define BP_ENET_TCCRn_TCC    (0U)          //!< Bit position for ENET_TCCRn_TCC.
+#define BM_ENET_TCCRn_TCC    (0xFFFFFFFFU) //!< Bit mask for ENET_TCCRn_TCC.
+#define BS_ENET_TCCRn_TCC    (32U)         //!< Bit field size in bits for ENET_TCCRn_TCC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCCRn_TCC field.
+#define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
+#endif
+
+//! @brief Format value for bitfield ENET_TCCRn_TCC.
+#define BF_ENET_TCCRn_TCC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCCRn_TCC), uint32_t) & BM_ENET_TCCRn_TCC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCC field to a new value.
+#define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_enet_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All ENET module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_enet
+{
+    uint8_t _reserved0[4];
+    __IO hw_enet_eir_t EIR;                //!< [0x4] Interrupt Event Register
+    __IO hw_enet_eimr_t EIMR;              //!< [0x8] Interrupt Mask Register
+    uint8_t _reserved1[4];
+    __IO hw_enet_rdar_t RDAR;              //!< [0x10] Receive Descriptor Active Register
+    __IO hw_enet_tdar_t TDAR;              //!< [0x14] Transmit Descriptor Active Register
+    uint8_t _reserved2[12];
+    __IO hw_enet_ecr_t ECR;                //!< [0x24] Ethernet Control Register
+    uint8_t _reserved3[24];
+    __IO hw_enet_mmfr_t MMFR;              //!< [0x40] MII Management Frame Register
+    __IO hw_enet_mscr_t MSCR;              //!< [0x44] MII Speed Control Register
+    uint8_t _reserved4[28];
+    __IO hw_enet_mibc_t MIBC;              //!< [0x64] MIB Control Register
+    uint8_t _reserved5[28];
+    __IO hw_enet_rcr_t RCR;                //!< [0x84] Receive Control Register
+    uint8_t _reserved6[60];
+    __IO hw_enet_tcr_t TCR;                //!< [0xC4] Transmit Control Register
+    uint8_t _reserved7[28];
+    __IO hw_enet_palr_t PALR;              //!< [0xE4] Physical Address Lower Register
+    __IO hw_enet_paur_t PAUR;              //!< [0xE8] Physical Address Upper Register
+    __IO hw_enet_opd_t OPD;                //!< [0xEC] Opcode/Pause Duration Register
+    uint8_t _reserved8[40];
+    __IO hw_enet_iaur_t IAUR;              //!< [0x118] Descriptor Individual Upper Address Register
+    __IO hw_enet_ialr_t IALR;              //!< [0x11C] Descriptor Individual Lower Address Register
+    __IO hw_enet_gaur_t GAUR;              //!< [0x120] Descriptor Group Upper Address Register
+    __IO hw_enet_galr_t GALR;              //!< [0x124] Descriptor Group Lower Address Register
+    uint8_t _reserved9[28];
+    __IO hw_enet_tfwr_t TFWR;              //!< [0x144] Transmit FIFO Watermark Register
+    uint8_t _reserved10[56];
+    __IO hw_enet_rdsr_t RDSR;              //!< [0x180] Receive Descriptor Ring Start Register
+    __IO hw_enet_tdsr_t TDSR;              //!< [0x184] Transmit Buffer Descriptor Ring Start Register
+    __IO hw_enet_mrbr_t MRBR;              //!< [0x188] Maximum Receive Buffer Size Register
+    uint8_t _reserved11[4];
+    __IO hw_enet_rsfl_t RSFL;              //!< [0x190] Receive FIFO Section Full Threshold
+    __IO hw_enet_rsem_t RSEM;              //!< [0x194] Receive FIFO Section Empty Threshold
+    __IO hw_enet_raem_t RAEM;              //!< [0x198] Receive FIFO Almost Empty Threshold
+    __IO hw_enet_rafl_t RAFL;              //!< [0x19C] Receive FIFO Almost Full Threshold
+    __IO hw_enet_tsem_t TSEM;              //!< [0x1A0] Transmit FIFO Section Empty Threshold
+    __IO hw_enet_taem_t TAEM;              //!< [0x1A4] Transmit FIFO Almost Empty Threshold
+    __IO hw_enet_tafl_t TAFL;              //!< [0x1A8] Transmit FIFO Almost Full Threshold
+    __IO hw_enet_tipg_t TIPG;              //!< [0x1AC] Transmit Inter-Packet Gap
+    __IO hw_enet_ftrl_t FTRL;              //!< [0x1B0] Frame Truncation Length
+    uint8_t _reserved12[12];
+    __IO hw_enet_tacc_t TACC;              //!< [0x1C0] Transmit Accelerator Function Configuration
+    __IO hw_enet_racc_t RACC;              //!< [0x1C4] Receive Accelerator Function Configuration
+    uint8_t _reserved13[60];
+    __I hw_enet_rmon_t_packets_t RMON_T_PACKETS; //!< [0x204] Tx Packet Count Statistic Register
+    __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; //!< [0x208] Tx Broadcast Packets Statistic Register
+    __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; //!< [0x20C] Tx Multicast Packets Statistic Register
+    __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; //!< [0x210] Tx Packets with CRC/Align Error Statistic Register
+    __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; //!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register
+    __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; //!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+    __I hw_enet_rmon_t_frag_t RMON_T_FRAG; //!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+    __I hw_enet_rmon_t_jab_t RMON_T_JAB;   //!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+    __I hw_enet_rmon_t_col_t RMON_T_COL;   //!< [0x224] Tx Collision Count Statistic Register
+    __I hw_enet_rmon_t_p64_t RMON_T_P64;   //!< [0x228] Tx 64-Byte Packets Statistic Register
+    __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; //!< [0x22C] Tx 65- to 127-byte Packets Statistic Register
+    __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; //!< [0x230] Tx 128- to 255-byte Packets Statistic Register
+    __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; //!< [0x234] Tx 256- to 511-byte Packets Statistic Register
+    __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; //!< [0x238] Tx 512- to 1023-byte Packets Statistic Register
+    __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; //!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register
+    __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; //!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register
+    __I hw_enet_rmon_t_octets_t RMON_T_OCTETS; //!< [0x244] Tx Octets Statistic Register
+    uint8_t _reserved14[4];
+    __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; //!< [0x24C] Frames Transmitted OK Statistic Register
+    __I hw_enet_ieee_t_1col_t IEEE_T_1COL; //!< [0x250] Frames Transmitted with Single Collision Statistic Register
+    __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; //!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register
+    __I hw_enet_ieee_t_def_t IEEE_T_DEF;   //!< [0x258] Frames Transmitted after Deferral Delay Statistic Register
+    __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; //!< [0x25C] Frames Transmitted with Late Collision Statistic Register
+    __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; //!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register
+    __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; //!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register
+    __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; //!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register
+    uint8_t _reserved15[4];
+    __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; //!< [0x270] Flow Control Pause Frames Transmitted Statistic Register
+    __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; //!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register
+    uint8_t _reserved16[12];
+    __I hw_enet_rmon_r_packets_t RMON_R_PACKETS; //!< [0x284] Rx Packet Count Statistic Register
+    __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; //!< [0x288] Rx Broadcast Packets Statistic Register
+    __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; //!< [0x28C] Rx Multicast Packets Statistic Register
+    __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; //!< [0x290] Rx Packets with CRC/Align Error Statistic Register
+    __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; //!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+    __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; //!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+    __I hw_enet_rmon_r_frag_t RMON_R_FRAG; //!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+    __I hw_enet_rmon_r_jab_t RMON_R_JAB;   //!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+    uint8_t _reserved17[4];
+    __I hw_enet_rmon_r_p64_t RMON_R_P64;   //!< [0x2A8] Rx 64-Byte Packets Statistic Register
+    __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; //!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register
+    __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; //!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register
+    __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; //!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register
+    __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; //!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register
+    __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; //!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register
+    __I hw_enet_rmon_r_gte2048_t RMON_R_GTE2048; //!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register
+    __I hw_enet_rmon_r_octets_t RMON_R_OCTETS; //!< [0x2C4] Rx Octets Statistic Register
+    __I hw_enet_ieee_r_drop_t IEEE_R_DROP; //!< [0x2C8] Frames not Counted Correctly Statistic Register
+    __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; //!< [0x2CC] Frames Received OK Statistic Register
+    __I hw_enet_ieee_r_crc_t IEEE_R_CRC;   //!< [0x2D0] Frames Received with CRC Error Statistic Register
+    __I hw_enet_ieee_r_align_t IEEE_R_ALIGN; //!< [0x2D4] Frames Received with Alignment Error Statistic Register
+    __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; //!< [0x2D8] Receive FIFO Overflow Count Statistic Register
+    __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; //!< [0x2DC] Flow Control Pause Frames Received Statistic Register
+    __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; //!< [0x2E0] Octet Count for Frames Received without Error Statistic Register
+    uint8_t _reserved18[284];
+    __IO hw_enet_atcr_t ATCR;              //!< [0x400] Adjustable Timer Control Register
+    __IO hw_enet_atvr_t ATVR;              //!< [0x404] Timer Value Register
+    __IO hw_enet_atoff_t ATOFF;            //!< [0x408] Timer Offset Register
+    __IO hw_enet_atper_t ATPER;            //!< [0x40C] Timer Period Register
+    __IO hw_enet_atcor_t ATCOR;            //!< [0x410] Timer Correction Register
+    __IO hw_enet_atinc_t ATINC;            //!< [0x414] Time-Stamping Clock Period Register
+    __I hw_enet_atstmp_t ATSTMP;           //!< [0x418] Timestamp of Last Transmitted Frame
+    uint8_t _reserved19[488];
+    __IO hw_enet_tgsr_t TGSR;              //!< [0x604] Timer Global Status Register
+    struct {
+        __IO hw_enet_tcsrn_t TCSRn;        //!< [0x608] Timer Control Status Register
+        __IO hw_enet_tccrn_t TCCRn;        //!< [0x60C] Timer Compare Capture Register
+    } CHANNEL[4];
+} hw_enet_t;
+#pragma pack()
+
+//! @brief Macro to access all ENET registers.
+//! @param x ENET instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_ENET(0)</code>.
+#define HW_ENET(x)     (*(hw_enet_t *) REGS_ENET_BASE(x))
+#endif
+
+#endif // __HW_ENET_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h
new file mode 100644
index 0000000000..b6c402d27b
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h
@@ -0,0 +1,430 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_EWM_REGISTERS_H__
+#define __HW_EWM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - HW_EWM_CTRL - Control Register
+ * - HW_EWM_SERV - Service Register
+ * - HW_EWM_CMPL - Compare Low Register
+ * - HW_EWM_CMPH - Compare High Register
+ *
+ * - hw_ewm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_EWM_BASE
+#define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
+#define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_CTRL - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+typedef union _hw_ewm_ctrl
+{
+    uint8_t U;
+    struct _hw_ewm_ctrl_bitfields
+    {
+        uint8_t EWMEN : 1;             //!< [0] EWM enable.
+        uint8_t ASSIN : 1;             //!< [1] EWM_in's Assertion State Select.
+        uint8_t INEN : 1;              //!< [2] Input Enable.
+        uint8_t INTEN : 1;             //!< [3] Interrupt Enable.
+        uint8_t RESERVED0 : 4;         //!< [7:4]
+    } B;
+} hw_ewm_ctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+//@{
+#define HW_EWM_CTRL_ADDR         (REGS_EWM_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_CTRL              (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
+#define HW_EWM_CTRL_RD()         (HW_EWM_CTRL.U)
+#define HW_EWM_CTRL_WR(v)        (HW_EWM_CTRL.U = (v))
+#define HW_EWM_CTRL_SET(v)       (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() |  (v)))
+#define HW_EWM_CTRL_CLR(v)       (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
+#define HW_EWM_CTRL_TOG(v)       (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+//@{
+#define BP_EWM_CTRL_EWMEN    (0U)          //!< Bit position for EWM_CTRL_EWMEN.
+#define BM_EWM_CTRL_EWMEN    (0x01U)       //!< Bit mask for EWM_CTRL_EWMEN.
+#define BS_EWM_CTRL_EWMEN    (1U)          //!< Bit field size in bits for EWM_CTRL_EWMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_EWMEN field.
+#define BR_EWM_CTRL_EWMEN    (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_EWMEN.
+#define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EWMEN field to a new value.
+#define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+//@{
+#define BP_EWM_CTRL_ASSIN    (1U)          //!< Bit position for EWM_CTRL_ASSIN.
+#define BM_EWM_CTRL_ASSIN    (0x02U)       //!< Bit mask for EWM_CTRL_ASSIN.
+#define BS_EWM_CTRL_ASSIN    (1U)          //!< Bit field size in bits for EWM_CTRL_ASSIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_ASSIN field.
+#define BR_EWM_CTRL_ASSIN    (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_ASSIN.
+#define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ASSIN field to a new value.
+#define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+//@{
+#define BP_EWM_CTRL_INEN     (2U)          //!< Bit position for EWM_CTRL_INEN.
+#define BM_EWM_CTRL_INEN     (0x04U)       //!< Bit mask for EWM_CTRL_INEN.
+#define BS_EWM_CTRL_INEN     (1U)          //!< Bit field size in bits for EWM_CTRL_INEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_INEN field.
+#define BR_EWM_CTRL_INEN     (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_INEN.
+#define BF_EWM_CTRL_INEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INEN field to a new value.
+#define BW_EWM_CTRL_INEN(v)  (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+//@{
+#define BP_EWM_CTRL_INTEN    (3U)          //!< Bit position for EWM_CTRL_INTEN.
+#define BM_EWM_CTRL_INTEN    (0x08U)       //!< Bit mask for EWM_CTRL_INTEN.
+#define BS_EWM_CTRL_INTEN    (1U)          //!< Bit field size in bits for EWM_CTRL_INTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_INTEN field.
+#define BR_EWM_CTRL_INTEN    (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_INTEN.
+#define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTEN field to a new value.
+#define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_SERV - Service Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+typedef union _hw_ewm_serv
+{
+    uint8_t U;
+    struct _hw_ewm_serv_bitfields
+    {
+        uint8_t SERVICE : 8;           //!< [7:0]
+    } B;
+} hw_ewm_serv_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+//@{
+#define HW_EWM_SERV_ADDR         (REGS_EWM_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_SERV              (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
+#define HW_EWM_SERV_RD()         (HW_EWM_SERV.U)
+#define HW_EWM_SERV_WR(v)        (HW_EWM_SERV.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_SERV bitfields
+ */
+
+/*!
+ * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
+ *
+ * The EWM service mechanism requires the CPU to write two values to the SERV
+ * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
+ * EWM service is illegal if either of the following conditions is true. The
+ * first or second data byte is not written correctly. The second data byte is not
+ * written within a fixed number of peripheral bus cycles of the first data byte.
+ * This fixed number of cycles is called EWM_service_time.
+ */
+//@{
+#define BP_EWM_SERV_SERVICE  (0U)          //!< Bit position for EWM_SERV_SERVICE.
+#define BM_EWM_SERV_SERVICE  (0xFFU)       //!< Bit mask for EWM_SERV_SERVICE.
+#define BS_EWM_SERV_SERVICE  (8U)          //!< Bit field size in bits for EWM_SERV_SERVICE.
+
+//! @brief Format value for bitfield EWM_SERV_SERVICE.
+#define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SERVICE field to a new value.
+#define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_CMPL - Compare Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+typedef union _hw_ewm_cmpl
+{
+    uint8_t U;
+    struct _hw_ewm_cmpl_bitfields
+    {
+        uint8_t COMPAREL : 8;          //!< [7:0]
+    } B;
+} hw_ewm_cmpl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+//@{
+#define HW_EWM_CMPL_ADDR         (REGS_EWM_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_CMPL              (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
+#define HW_EWM_CMPL_RD()         (HW_EWM_CMPL.U)
+#define HW_EWM_CMPL_WR(v)        (HW_EWM_CMPL.U = (v))
+#define HW_EWM_CMPL_SET(v)       (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() |  (v)))
+#define HW_EWM_CMPL_CLR(v)       (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
+#define HW_EWM_CMPL_TOG(v)       (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_CMPL bitfields
+ */
+
+/*!
+ * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
+ *
+ * To prevent runaway code from changing this field, software should write to
+ * this field after a CPU reset even if the (default) minimum service time is
+ * required.
+ */
+//@{
+#define BP_EWM_CMPL_COMPAREL (0U)          //!< Bit position for EWM_CMPL_COMPAREL.
+#define BM_EWM_CMPL_COMPAREL (0xFFU)       //!< Bit mask for EWM_CMPL_COMPAREL.
+#define BS_EWM_CMPL_COMPAREL (8U)          //!< Bit field size in bits for EWM_CMPL_COMPAREL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CMPL_COMPAREL field.
+#define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
+#endif
+
+//! @brief Format value for bitfield EWM_CMPL_COMPAREL.
+#define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPAREL field to a new value.
+#define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_CMPH - Compare High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+typedef union _hw_ewm_cmph
+{
+    uint8_t U;
+    struct _hw_ewm_cmph_bitfields
+    {
+        uint8_t COMPAREH : 8;          //!< [7:0]
+    } B;
+} hw_ewm_cmph_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+//@{
+#define HW_EWM_CMPH_ADDR         (REGS_EWM_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_CMPH              (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
+#define HW_EWM_CMPH_RD()         (HW_EWM_CMPH.U)
+#define HW_EWM_CMPH_WR(v)        (HW_EWM_CMPH.U = (v))
+#define HW_EWM_CMPH_SET(v)       (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() |  (v)))
+#define HW_EWM_CMPH_CLR(v)       (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
+#define HW_EWM_CMPH_TOG(v)       (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_CMPH bitfields
+ */
+
+/*!
+ * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
+ *
+ * To prevent runaway code from changing this field, software should write to
+ * this field after a CPU reset even if the (default) maximum service time is
+ * required.
+ */
+//@{
+#define BP_EWM_CMPH_COMPAREH (0U)          //!< Bit position for EWM_CMPH_COMPAREH.
+#define BM_EWM_CMPH_COMPAREH (0xFFU)       //!< Bit mask for EWM_CMPH_COMPAREH.
+#define BS_EWM_CMPH_COMPAREH (8U)          //!< Bit field size in bits for EWM_CMPH_COMPAREH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CMPH_COMPAREH field.
+#define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
+#endif
+
+//! @brief Format value for bitfield EWM_CMPH_COMPAREH.
+#define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPAREH field to a new value.
+#define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_ewm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All EWM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_ewm
+{
+    __IO hw_ewm_ctrl_t CTRL;               //!< [0x0] Control Register
+    __O hw_ewm_serv_t SERV;                //!< [0x1] Service Register
+    __IO hw_ewm_cmpl_t CMPL;               //!< [0x2] Compare Low Register
+    __IO hw_ewm_cmph_t CMPH;               //!< [0x3] Compare High Register
+} hw_ewm_t;
+#pragma pack()
+
+//! @brief Macro to access all EWM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_EWM</code>.
+#define HW_EWM         (*(hw_ewm_t *) REGS_EWM_BASE)
+#endif
+
+#endif // __HW_EWM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h
new file mode 100644
index 0000000000..407dc91c2a
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h
@@ -0,0 +1,959 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FB_REGISTERS_H__
+#define __HW_FB_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - HW_FB_CSARn - Chip Select Address Register
+ * - HW_FB_CSMRn - Chip Select Mask Register
+ * - HW_FB_CSCRn - Chip Select Control Register
+ * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
+ *
+ * - hw_fb_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FB_BASE
+#define HW_FB_INSTANCE_COUNT (1U) //!< Number of instances of the FB module.
+#define REGS_FB_BASE (0x4000C000U) //!< Base address for FB.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSARn - Chip Select Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSARn - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+typedef union _hw_fb_csarn
+{
+    uint32_t U;
+    struct _hw_fb_csarn_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t BA : 16;              //!< [31:16] Base Address
+    } B;
+} hw_fb_csarn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSARn register
+ */
+//@{
+#define HW_FB_CSARn_COUNT (6U)
+
+#define HW_FB_CSARn_ADDR(n)      (REGS_FB_BASE + 0x0U + (0xCU * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSARn(n)           (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(n))
+#define HW_FB_CSARn_RD(n)        (HW_FB_CSARn(n).U)
+#define HW_FB_CSARn_WR(n, v)     (HW_FB_CSARn(n).U = (v))
+#define HW_FB_CSARn_SET(n, v)    (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) |  (v)))
+#define HW_FB_CSARn_CLR(n, v)    (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) & ~(v)))
+#define HW_FB_CSARn_TOG(n, v)    (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSARn bitfields
+ */
+
+/*!
+ * @name Register FB_CSARn, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+//@{
+#define BP_FB_CSARn_BA       (16U)         //!< Bit position for FB_CSARn_BA.
+#define BM_FB_CSARn_BA       (0xFFFF0000U) //!< Bit mask for FB_CSARn_BA.
+#define BS_FB_CSARn_BA       (16U)         //!< Bit field size in bits for FB_CSARn_BA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSARn_BA field.
+#define BR_FB_CSARn_BA(n)    (HW_FB_CSARn(n).B.BA)
+#endif
+
+//! @brief Format value for bitfield FB_CSARn_BA.
+#define BF_FB_CSARn_BA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSARn_BA), uint32_t) & BM_FB_CSARn_BA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BA field to a new value.
+#define BW_FB_CSARn_BA(n, v) (HW_FB_CSARn_WR(n, (HW_FB_CSARn_RD(n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSMRn - Chip Select Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+typedef union _hw_fb_csmrn
+{
+    uint32_t U;
+    struct _hw_fb_csmrn_bitfields
+    {
+        uint32_t V : 1;                //!< [0] Valid
+        uint32_t RESERVED0 : 7;        //!< [7:1]
+        uint32_t WP : 1;               //!< [8] Write Protect
+        uint32_t RESERVED1 : 7;        //!< [15:9]
+        uint32_t BAM : 16;             //!< [31:16] Base Address Mask
+    } B;
+} hw_fb_csmrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSMRn register
+ */
+//@{
+#define HW_FB_CSMRn_COUNT (6U)
+
+#define HW_FB_CSMRn_ADDR(n)      (REGS_FB_BASE + 0x4U + (0xCU * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSMRn(n)           (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(n))
+#define HW_FB_CSMRn_RD(n)        (HW_FB_CSMRn(n).U)
+#define HW_FB_CSMRn_WR(n, v)     (HW_FB_CSMRn(n).U = (v))
+#define HW_FB_CSMRn_SET(n, v)    (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) |  (v)))
+#define HW_FB_CSMRn_CLR(n, v)    (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) & ~(v)))
+#define HW_FB_CSMRn_TOG(n, v)    (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSMRn bitfields
+ */
+
+/*!
+ * @name Register FB_CSMRn, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0 - Chip-select is invalid.
+ * - 1 - Chip-select is valid.
+ */
+//@{
+#define BP_FB_CSMRn_V        (0U)          //!< Bit position for FB_CSMRn_V.
+#define BM_FB_CSMRn_V        (0x00000001U) //!< Bit mask for FB_CSMRn_V.
+#define BS_FB_CSMRn_V        (1U)          //!< Bit field size in bits for FB_CSMRn_V.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSMRn_V field.
+#define BR_FB_CSMRn_V(n)     (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V))
+#endif
+
+//! @brief Format value for bitfield FB_CSMRn_V.
+#define BF_FB_CSMRn_V(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_V), uint32_t) & BM_FB_CSMRn_V)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the V field to a new value.
+#define BW_FB_CSMRn_V(n, v)  (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSMRn, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0 - Write accesses are allowed.
+ * - 1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+//@{
+#define BP_FB_CSMRn_WP       (8U)          //!< Bit position for FB_CSMRn_WP.
+#define BM_FB_CSMRn_WP       (0x00000100U) //!< Bit mask for FB_CSMRn_WP.
+#define BS_FB_CSMRn_WP       (1U)          //!< Bit field size in bits for FB_CSMRn_WP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSMRn_WP field.
+#define BR_FB_CSMRn_WP(n)    (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP))
+#endif
+
+//! @brief Format value for bitfield FB_CSMRn_WP.
+#define BF_FB_CSMRn_WP(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_WP), uint32_t) & BM_FB_CSMRn_WP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP field to a new value.
+#define BW_FB_CSMRn_WP(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSMRn, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
+ * - 1 - The corresponding address bit in CSAR is a don't care in the
+ *     chip-select decode.
+ */
+//@{
+#define BP_FB_CSMRn_BAM      (16U)         //!< Bit position for FB_CSMRn_BAM.
+#define BM_FB_CSMRn_BAM      (0xFFFF0000U) //!< Bit mask for FB_CSMRn_BAM.
+#define BS_FB_CSMRn_BAM      (16U)         //!< Bit field size in bits for FB_CSMRn_BAM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSMRn_BAM field.
+#define BR_FB_CSMRn_BAM(n)   (HW_FB_CSMRn(n).B.BAM)
+#endif
+
+//! @brief Format value for bitfield FB_CSMRn_BAM.
+#define BF_FB_CSMRn_BAM(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_BAM), uint32_t) & BM_FB_CSMRn_BAM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BAM field to a new value.
+#define BW_FB_CSMRn_BAM(n, v) (HW_FB_CSMRn_WR(n, (HW_FB_CSMRn_RD(n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSCRn - Chip Select Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+typedef union _hw_fb_cscrn
+{
+    uint32_t U;
+    struct _hw_fb_cscrn_bitfields
+    {
+        uint32_t RESERVED0 : 3;        //!< [2:0]
+        uint32_t BSTW : 1;             //!< [3] Burst-Write Enable
+        uint32_t BSTR : 1;             //!< [4] Burst-Read Enable
+        uint32_t BEM : 1;              //!< [5] Byte-Enable Mode
+        uint32_t PS : 2;               //!< [7:6] Port Size
+        uint32_t AA : 1;               //!< [8] Auto-Acknowledge Enable
+        uint32_t BLS : 1;              //!< [9] Byte-Lane Shift
+        uint32_t WS : 6;               //!< [15:10] Wait States
+        uint32_t WRAH : 2;             //!< [17:16] Write Address Hold or Deselect
+        uint32_t RDAH : 2;             //!< [19:18] Read Address Hold or Deselect
+        uint32_t ASET : 2;             //!< [21:20] Address Setup
+        uint32_t EXTS : 1;             //!< [22]
+        uint32_t SWSEN : 1;            //!< [23] Secondary Wait State Enable
+        uint32_t RESERVED1 : 2;        //!< [25:24]
+        uint32_t SWS : 6;              //!< [31:26] Secondary Wait States
+    } B;
+} hw_fb_cscrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSCRn register
+ */
+//@{
+#define HW_FB_CSCRn_COUNT (6U)
+
+#define HW_FB_CSCRn_ADDR(n)      (REGS_FB_BASE + 0x8U + (0xCU * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSCRn(n)           (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(n))
+#define HW_FB_CSCRn_RD(n)        (HW_FB_CSCRn(n).U)
+#define HW_FB_CSCRn_WR(n, v)     (HW_FB_CSCRn(n).U = (v))
+#define HW_FB_CSCRn_SET(n, v)    (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) |  (v)))
+#define HW_FB_CSCRn_CLR(n, v)    (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) & ~(v)))
+#define HW_FB_CSCRn_TOG(n, v)    (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSCRn bitfields
+ */
+
+/*!
+ * @name Register FB_CSCRn, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
+ *     port takes four byte writes.
+ * - 1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
+ *     ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+//@{
+#define BP_FB_CSCRn_BSTW     (3U)          //!< Bit position for FB_CSCRn_BSTW.
+#define BM_FB_CSCRn_BSTW     (0x00000008U) //!< Bit mask for FB_CSCRn_BSTW.
+#define BS_FB_CSCRn_BSTW     (1U)          //!< Bit field size in bits for FB_CSCRn_BSTW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BSTW field.
+#define BR_FB_CSCRn_BSTW(n)  (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BSTW.
+#define BF_FB_CSCRn_BSTW(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTW), uint32_t) & BM_FB_CSCRn_BSTW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSTW field to a new value.
+#define BW_FB_CSCRn_BSTW(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
+ *     port is broken into four 8-bit reads.
+ * - 1 - Enabled. Enables data burst reads larger than the specified port size,
+ *     including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+//@{
+#define BP_FB_CSCRn_BSTR     (4U)          //!< Bit position for FB_CSCRn_BSTR.
+#define BM_FB_CSCRn_BSTR     (0x00000010U) //!< Bit mask for FB_CSCRn_BSTR.
+#define BS_FB_CSCRn_BSTR     (1U)          //!< Bit field size in bits for FB_CSCRn_BSTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BSTR field.
+#define BR_FB_CSCRn_BSTR(n)  (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BSTR.
+#define BF_FB_CSCRn_BSTR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTR), uint32_t) & BM_FB_CSCRn_BSTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSTR field to a new value.
+#define BW_FB_CSCRn_BSTR(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0 - FB_BE is asserted for data write only.
+ * - 1 - FB_BE is asserted for data read and write accesses.
+ */
+//@{
+#define BP_FB_CSCRn_BEM      (5U)          //!< Bit position for FB_CSCRn_BEM.
+#define BM_FB_CSCRn_BEM      (0x00000020U) //!< Bit mask for FB_CSCRn_BEM.
+#define BS_FB_CSCRn_BEM      (1U)          //!< Bit field size in bits for FB_CSCRn_BEM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BEM field.
+#define BR_FB_CSCRn_BEM(n)   (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BEM.
+#define BF_FB_CSCRn_BEM(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BEM), uint32_t) & BM_FB_CSCRn_BEM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BEM field to a new value.
+#define BW_FB_CSCRn_BEM(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
+ *     BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+//@{
+#define BP_FB_CSCRn_PS       (6U)          //!< Bit position for FB_CSCRn_PS.
+#define BM_FB_CSCRn_PS       (0x000000C0U) //!< Bit mask for FB_CSCRn_PS.
+#define BS_FB_CSCRn_PS       (2U)          //!< Bit field size in bits for FB_CSCRn_PS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_PS field.
+#define BR_FB_CSCRn_PS(n)    (HW_FB_CSCRn(n).B.PS)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_PS.
+#define BF_FB_CSCRn_PS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_PS), uint32_t) & BM_FB_CSCRn_PS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PS field to a new value.
+#define BW_FB_CSCRn_PS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
+ *     terminated externally.
+ * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+//@{
+#define BP_FB_CSCRn_AA       (8U)          //!< Bit position for FB_CSCRn_AA.
+#define BM_FB_CSCRn_AA       (0x00000100U) //!< Bit mask for FB_CSCRn_AA.
+#define BS_FB_CSCRn_AA       (1U)          //!< Bit field size in bits for FB_CSCRn_AA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_AA field.
+#define BR_FB_CSCRn_AA(n)    (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_AA.
+#define BF_FB_CSCRn_AA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_AA), uint32_t) & BM_FB_CSCRn_AA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AA field to a new value.
+#define BW_FB_CSCRn_AA(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 1 - Shifted. Data is right-aligned on FB_AD.
+ */
+//@{
+#define BP_FB_CSCRn_BLS      (9U)          //!< Bit position for FB_CSCRn_BLS.
+#define BM_FB_CSCRn_BLS      (0x00000200U) //!< Bit mask for FB_CSCRn_BLS.
+#define BS_FB_CSCRn_BLS      (1U)          //!< Bit field size in bits for FB_CSCRn_BLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BLS field.
+#define BR_FB_CSCRn_BLS(n)   (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BLS.
+#define BF_FB_CSCRn_BLS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BLS), uint32_t) & BM_FB_CSCRn_BLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BLS field to a new value.
+#define BW_FB_CSCRn_BLS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+//@{
+#define BP_FB_CSCRn_WS       (10U)         //!< Bit position for FB_CSCRn_WS.
+#define BM_FB_CSCRn_WS       (0x0000FC00U) //!< Bit mask for FB_CSCRn_WS.
+#define BS_FB_CSCRn_WS       (6U)          //!< Bit field size in bits for FB_CSCRn_WS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_WS field.
+#define BR_FB_CSCRn_WS(n)    (HW_FB_CSCRn(n).B.WS)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_WS.
+#define BF_FB_CSCRn_WS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WS), uint32_t) & BM_FB_CSCRn_WS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WS field to a new value.
+#define BW_FB_CSCRn_WS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 00 - 1 cycle (default for all but FB_CS0 )
+ * - 01 - 2 cycles
+ * - 10 - 3 cycles
+ * - 11 - 4 cycles (default for FB_CS0 )
+ */
+//@{
+#define BP_FB_CSCRn_WRAH     (16U)         //!< Bit position for FB_CSCRn_WRAH.
+#define BM_FB_CSCRn_WRAH     (0x00030000U) //!< Bit mask for FB_CSCRn_WRAH.
+#define BS_FB_CSCRn_WRAH     (2U)          //!< Bit field size in bits for FB_CSCRn_WRAH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_WRAH field.
+#define BR_FB_CSCRn_WRAH(n)  (HW_FB_CSCRn(n).B.WRAH)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_WRAH.
+#define BF_FB_CSCRn_WRAH(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WRAH), uint32_t) & BM_FB_CSCRn_WRAH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRAH field to a new value.
+#define BW_FB_CSCRn_WRAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+//@{
+#define BP_FB_CSCRn_RDAH     (18U)         //!< Bit position for FB_CSCRn_RDAH.
+#define BM_FB_CSCRn_RDAH     (0x000C0000U) //!< Bit mask for FB_CSCRn_RDAH.
+#define BS_FB_CSCRn_RDAH     (2U)          //!< Bit field size in bits for FB_CSCRn_RDAH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_RDAH field.
+#define BR_FB_CSCRn_RDAH(n)  (HW_FB_CSCRn(n).B.RDAH)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_RDAH.
+#define BF_FB_CSCRn_RDAH(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_RDAH), uint32_t) & BM_FB_CSCRn_RDAH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDAH field to a new value.
+#define BW_FB_CSCRn_RDAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+//@{
+#define BP_FB_CSCRn_ASET     (20U)         //!< Bit position for FB_CSCRn_ASET.
+#define BM_FB_CSCRn_ASET     (0x00300000U) //!< Bit mask for FB_CSCRn_ASET.
+#define BS_FB_CSCRn_ASET     (2U)          //!< Bit field size in bits for FB_CSCRn_ASET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_ASET field.
+#define BR_FB_CSCRn_ASET(n)  (HW_FB_CSCRn(n).B.ASET)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_ASET.
+#define BF_FB_CSCRn_ASET(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_ASET), uint32_t) & BM_FB_CSCRn_ASET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ASET field to a new value.
+#define BW_FB_CSCRn_ASET(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
+ *     edge after FB_CSn asserts.
+ */
+//@{
+#define BP_FB_CSCRn_EXTS     (22U)         //!< Bit position for FB_CSCRn_EXTS.
+#define BM_FB_CSCRn_EXTS     (0x00400000U) //!< Bit mask for FB_CSCRn_EXTS.
+#define BS_FB_CSCRn_EXTS     (1U)          //!< Bit field size in bits for FB_CSCRn_EXTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_EXTS field.
+#define BR_FB_CSCRn_EXTS(n)  (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_EXTS.
+#define BF_FB_CSCRn_EXTS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_EXTS), uint32_t) & BM_FB_CSCRn_EXTS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXTS field to a new value.
+#define BW_FB_CSCRn_EXTS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
+ *     an internal transfer acknowledge is generated for all transfers.
+ * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
+ *     an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+//@{
+#define BP_FB_CSCRn_SWSEN    (23U)         //!< Bit position for FB_CSCRn_SWSEN.
+#define BM_FB_CSCRn_SWSEN    (0x00800000U) //!< Bit mask for FB_CSCRn_SWSEN.
+#define BS_FB_CSCRn_SWSEN    (1U)          //!< Bit field size in bits for FB_CSCRn_SWSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_SWSEN field.
+#define BR_FB_CSCRn_SWSEN(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_SWSEN.
+#define BF_FB_CSCRn_SWSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWSEN), uint32_t) & BM_FB_CSCRn_SWSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWSEN field to a new value.
+#define BW_FB_CSCRn_SWSEN(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+//@{
+#define BP_FB_CSCRn_SWS      (26U)         //!< Bit position for FB_CSCRn_SWS.
+#define BM_FB_CSCRn_SWS      (0xFC000000U) //!< Bit mask for FB_CSCRn_SWS.
+#define BS_FB_CSCRn_SWS      (6U)          //!< Bit field size in bits for FB_CSCRn_SWS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_SWS field.
+#define BR_FB_CSCRn_SWS(n)   (HW_FB_CSCRn(n).B.SWS)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_SWS.
+#define BF_FB_CSCRn_SWS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWS), uint32_t) & BM_FB_CSCRn_SWS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWS field to a new value.
+#define BW_FB_CSCRn_SWS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+typedef union _hw_fb_cspmcr
+{
+    uint32_t U;
+    struct _hw_fb_cspmcr_bitfields
+    {
+        uint32_t RESERVED0 : 12;       //!< [11:0]
+        uint32_t GROUP5 : 4;           //!< [15:12] FlexBus Signal Group 5 Multiplex
+                                       //! control
+        uint32_t GROUP4 : 4;           //!< [19:16] FlexBus Signal Group 4 Multiplex
+                                       //! control
+        uint32_t GROUP3 : 4;           //!< [23:20] FlexBus Signal Group 3 Multiplex
+                                       //! control
+        uint32_t GROUP2 : 4;           //!< [27:24] FlexBus Signal Group 2 Multiplex
+                                       //! control
+        uint32_t GROUP1 : 4;           //!< [31:28] FlexBus Signal Group 1 Multiplex
+                                       //! control
+    } B;
+} hw_fb_cspmcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+//@{
+#define HW_FB_CSPMCR_ADDR        (REGS_FB_BASE + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSPMCR             (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR)
+#define HW_FB_CSPMCR_RD()        (HW_FB_CSPMCR.U)
+#define HW_FB_CSPMCR_WR(v)       (HW_FB_CSPMCR.U = (v))
+#define HW_FB_CSPMCR_SET(v)      (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() |  (v)))
+#define HW_FB_CSPMCR_CLR(v)      (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() & ~(v)))
+#define HW_FB_CSPMCR_TOG(v)      (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0000 - FB_TA
+ * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP5  (12U)         //!< Bit position for FB_CSPMCR_GROUP5.
+#define BM_FB_CSPMCR_GROUP5  (0x0000F000U) //!< Bit mask for FB_CSPMCR_GROUP5.
+#define BS_FB_CSPMCR_GROUP5  (4U)          //!< Bit field size in bits for FB_CSPMCR_GROUP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP5 field.
+#define BR_FB_CSPMCR_GROUP5  (HW_FB_CSPMCR.B.GROUP5)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP5.
+#define BF_FB_CSPMCR_GROUP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP5), uint32_t) & BM_FB_CSPMCR_GROUP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP5 field to a new value.
+#define BW_FB_CSPMCR_GROUP5(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0000 - FB_TBST
+ * - 0001 - FB_CS2
+ * - 0010 - FB_BE_15_8
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP4  (16U)         //!< Bit position for FB_CSPMCR_GROUP4.
+#define BM_FB_CSPMCR_GROUP4  (0x000F0000U) //!< Bit mask for FB_CSPMCR_GROUP4.
+#define BS_FB_CSPMCR_GROUP4  (4U)          //!< Bit field size in bits for FB_CSPMCR_GROUP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP4 field.
+#define BR_FB_CSPMCR_GROUP4  (HW_FB_CSPMCR.B.GROUP4)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP4.
+#define BF_FB_CSPMCR_GROUP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP4), uint32_t) & BM_FB_CSPMCR_GROUP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP4 field to a new value.
+#define BW_FB_CSPMCR_GROUP4(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0000 - FB_CS5
+ * - 0001 - FB_TSIZ1
+ * - 0010 - FB_BE_23_16
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP3  (20U)         //!< Bit position for FB_CSPMCR_GROUP3.
+#define BM_FB_CSPMCR_GROUP3  (0x00F00000U) //!< Bit mask for FB_CSPMCR_GROUP3.
+#define BS_FB_CSPMCR_GROUP3  (4U)          //!< Bit field size in bits for FB_CSPMCR_GROUP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP3 field.
+#define BR_FB_CSPMCR_GROUP3  (HW_FB_CSPMCR.B.GROUP3)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP3.
+#define BF_FB_CSPMCR_GROUP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP3), uint32_t) & BM_FB_CSPMCR_GROUP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP3 field to a new value.
+#define BW_FB_CSPMCR_GROUP3(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0000 - FB_CS4
+ * - 0001 - FB_TSIZ0
+ * - 0010 - FB_BE_31_24
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP2  (24U)         //!< Bit position for FB_CSPMCR_GROUP2.
+#define BM_FB_CSPMCR_GROUP2  (0x0F000000U) //!< Bit mask for FB_CSPMCR_GROUP2.
+#define BS_FB_CSPMCR_GROUP2  (4U)          //!< Bit field size in bits for FB_CSPMCR_GROUP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP2 field.
+#define BR_FB_CSPMCR_GROUP2  (HW_FB_CSPMCR.B.GROUP2)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP2.
+#define BF_FB_CSPMCR_GROUP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP2), uint32_t) & BM_FB_CSPMCR_GROUP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP2 field to a new value.
+#define BW_FB_CSPMCR_GROUP2(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0000 - FB_ALE
+ * - 0001 - FB_CS1
+ * - 0010 - FB_TS
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP1  (28U)         //!< Bit position for FB_CSPMCR_GROUP1.
+#define BM_FB_CSPMCR_GROUP1  (0xF0000000U) //!< Bit mask for FB_CSPMCR_GROUP1.
+#define BS_FB_CSPMCR_GROUP1  (4U)          //!< Bit field size in bits for FB_CSPMCR_GROUP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP1 field.
+#define BR_FB_CSPMCR_GROUP1  (HW_FB_CSPMCR.B.GROUP1)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP1.
+#define BF_FB_CSPMCR_GROUP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP1), uint32_t) & BM_FB_CSPMCR_GROUP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP1 field to a new value.
+#define BW_FB_CSPMCR_GROUP1(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_fb_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FB module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_fb
+{
+    struct {
+        __IO hw_fb_csarn_t CSARn;          //!< [0x0] Chip Select Address Register
+        __IO hw_fb_csmrn_t CSMRn;          //!< [0x4] Chip Select Mask Register
+        __IO hw_fb_cscrn_t CSCRn;          //!< [0x8] Chip Select Control Register
+    } CS[6];
+    uint8_t _reserved0[24];
+    __IO hw_fb_cspmcr_t CSPMCR;            //!< [0x60] Chip Select port Multiplexing Control Register
+} hw_fb_t;
+#pragma pack()
+
+//! @brief Macro to access all FB registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_FB</code>.
+#define HW_FB          (*(hw_fb_t *) REGS_FB_BASE)
+#endif
+
+#endif // __HW_FB_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h
new file mode 100644
index 0000000000..f93107449f
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h
@@ -0,0 +1,2177 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FMC_REGISTERS_H__
+#define __HW_FMC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - HW_FMC_PFAPR - Flash Access Protection Register
+ * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
+ * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
+ * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
+ * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
+ * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
+ * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
+ * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
+ * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
+ * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
+ * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
+ *
+ * - hw_fmc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FMC_BASE
+#define HW_FMC_INSTANCE_COUNT (1U) //!< Number of instances of the FMC module.
+#define REGS_FMC_BASE (0x4001F000U) //!< Base address for FMC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_PFAPR - Flash Access Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+typedef union _hw_fmc_pfapr
+{
+    uint32_t U;
+    struct _hw_fmc_pfapr_bitfields
+    {
+        uint32_t M0AP : 2;             //!< [1:0] Master 0 Access Protection
+        uint32_t M1AP : 2;             //!< [3:2] Master 1 Access Protection
+        uint32_t M2AP : 2;             //!< [5:4] Master 2 Access Protection
+        uint32_t M3AP : 2;             //!< [7:6] Master 3 Access Protection
+        uint32_t M4AP : 2;             //!< [9:8] Master 4 Access Protection
+        uint32_t M5AP : 2;             //!< [11:10] Master 5 Access Protection
+        uint32_t M6AP : 2;             //!< [13:12] Master 6 Access Protection
+        uint32_t M7AP : 2;             //!< [15:14] Master 7 Access Protection
+        uint32_t M0PFD : 1;            //!< [16] Master 0 Prefetch Disable
+        uint32_t M1PFD : 1;            //!< [17] Master 1 Prefetch Disable
+        uint32_t M2PFD : 1;            //!< [18] Master 2 Prefetch Disable
+        uint32_t M3PFD : 1;            //!< [19] Master 3 Prefetch Disable
+        uint32_t M4PFD : 1;            //!< [20] Master 4 Prefetch Disable
+        uint32_t M5PFD : 1;            //!< [21] Master 5 Prefetch Disable
+        uint32_t M6PFD : 1;            //!< [22] Master 6 Prefetch Disable
+        uint32_t M7PFD : 1;            //!< [23] Master 7 Prefetch Disable
+        uint32_t RESERVED0 : 8;        //!< [31:24]
+    } B;
+} hw_fmc_pfapr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+//@{
+#define HW_FMC_PFAPR_ADDR        (REGS_FMC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_PFAPR             (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR)
+#define HW_FMC_PFAPR_RD()        (HW_FMC_PFAPR.U)
+#define HW_FMC_PFAPR_WR(v)       (HW_FMC_PFAPR.U = (v))
+#define HW_FMC_PFAPR_SET(v)      (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() |  (v)))
+#define HW_FMC_PFAPR_CLR(v)      (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() & ~(v)))
+#define HW_FMC_PFAPR_TOG(v)      (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M0AP    (0U)          //!< Bit position for FMC_PFAPR_M0AP.
+#define BM_FMC_PFAPR_M0AP    (0x00000003U) //!< Bit mask for FMC_PFAPR_M0AP.
+#define BS_FMC_PFAPR_M0AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M0AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M0AP field.
+#define BR_FMC_PFAPR_M0AP    (HW_FMC_PFAPR.B.M0AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M0AP.
+#define BF_FMC_PFAPR_M0AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0AP), uint32_t) & BM_FMC_PFAPR_M0AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0AP field to a new value.
+#define BW_FMC_PFAPR_M0AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M1AP    (2U)          //!< Bit position for FMC_PFAPR_M1AP.
+#define BM_FMC_PFAPR_M1AP    (0x0000000CU) //!< Bit mask for FMC_PFAPR_M1AP.
+#define BS_FMC_PFAPR_M1AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M1AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M1AP field.
+#define BR_FMC_PFAPR_M1AP    (HW_FMC_PFAPR.B.M1AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M1AP.
+#define BF_FMC_PFAPR_M1AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1AP), uint32_t) & BM_FMC_PFAPR_M1AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1AP field to a new value.
+#define BW_FMC_PFAPR_M1AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M2AP    (4U)          //!< Bit position for FMC_PFAPR_M2AP.
+#define BM_FMC_PFAPR_M2AP    (0x00000030U) //!< Bit mask for FMC_PFAPR_M2AP.
+#define BS_FMC_PFAPR_M2AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M2AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M2AP field.
+#define BR_FMC_PFAPR_M2AP    (HW_FMC_PFAPR.B.M2AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M2AP.
+#define BF_FMC_PFAPR_M2AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2AP), uint32_t) & BM_FMC_PFAPR_M2AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2AP field to a new value.
+#define BW_FMC_PFAPR_M2AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M3AP    (6U)          //!< Bit position for FMC_PFAPR_M3AP.
+#define BM_FMC_PFAPR_M3AP    (0x000000C0U) //!< Bit mask for FMC_PFAPR_M3AP.
+#define BS_FMC_PFAPR_M3AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M3AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M3AP field.
+#define BR_FMC_PFAPR_M3AP    (HW_FMC_PFAPR.B.M3AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M3AP.
+#define BF_FMC_PFAPR_M3AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3AP), uint32_t) & BM_FMC_PFAPR_M3AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3AP field to a new value.
+#define BW_FMC_PFAPR_M3AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M4AP    (8U)          //!< Bit position for FMC_PFAPR_M4AP.
+#define BM_FMC_PFAPR_M4AP    (0x00000300U) //!< Bit mask for FMC_PFAPR_M4AP.
+#define BS_FMC_PFAPR_M4AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M4AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M4AP field.
+#define BR_FMC_PFAPR_M4AP    (HW_FMC_PFAPR.B.M4AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M4AP.
+#define BF_FMC_PFAPR_M4AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4AP), uint32_t) & BM_FMC_PFAPR_M4AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4AP field to a new value.
+#define BW_FMC_PFAPR_M4AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M5AP    (10U)         //!< Bit position for FMC_PFAPR_M5AP.
+#define BM_FMC_PFAPR_M5AP    (0x00000C00U) //!< Bit mask for FMC_PFAPR_M5AP.
+#define BS_FMC_PFAPR_M5AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M5AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M5AP field.
+#define BR_FMC_PFAPR_M5AP    (HW_FMC_PFAPR.B.M5AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M5AP.
+#define BF_FMC_PFAPR_M5AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5AP), uint32_t) & BM_FMC_PFAPR_M5AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5AP field to a new value.
+#define BW_FMC_PFAPR_M5AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M6AP    (12U)         //!< Bit position for FMC_PFAPR_M6AP.
+#define BM_FMC_PFAPR_M6AP    (0x00003000U) //!< Bit mask for FMC_PFAPR_M6AP.
+#define BS_FMC_PFAPR_M6AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M6AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M6AP field.
+#define BR_FMC_PFAPR_M6AP    (HW_FMC_PFAPR.B.M6AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M6AP.
+#define BF_FMC_PFAPR_M6AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6AP), uint32_t) & BM_FMC_PFAPR_M6AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6AP field to a new value.
+#define BW_FMC_PFAPR_M6AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master.
+ * - 01 - Only read accesses may be performed by this master.
+ * - 10 - Only write accesses may be performed by this master.
+ * - 11 - Both read and write accesses may be performed by this master.
+ */
+//@{
+#define BP_FMC_PFAPR_M7AP    (14U)         //!< Bit position for FMC_PFAPR_M7AP.
+#define BM_FMC_PFAPR_M7AP    (0x0000C000U) //!< Bit mask for FMC_PFAPR_M7AP.
+#define BS_FMC_PFAPR_M7AP    (2U)          //!< Bit field size in bits for FMC_PFAPR_M7AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M7AP field.
+#define BR_FMC_PFAPR_M7AP    (HW_FMC_PFAPR.B.M7AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M7AP.
+#define BF_FMC_PFAPR_M7AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7AP), uint32_t) & BM_FMC_PFAPR_M7AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7AP field to a new value.
+#define BW_FMC_PFAPR_M7AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M0PFD   (16U)         //!< Bit position for FMC_PFAPR_M0PFD.
+#define BM_FMC_PFAPR_M0PFD   (0x00010000U) //!< Bit mask for FMC_PFAPR_M0PFD.
+#define BS_FMC_PFAPR_M0PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M0PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M0PFD field.
+#define BR_FMC_PFAPR_M0PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M0PFD.
+#define BF_FMC_PFAPR_M0PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0PFD), uint32_t) & BM_FMC_PFAPR_M0PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0PFD field to a new value.
+#define BW_FMC_PFAPR_M0PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M1PFD   (17U)         //!< Bit position for FMC_PFAPR_M1PFD.
+#define BM_FMC_PFAPR_M1PFD   (0x00020000U) //!< Bit mask for FMC_PFAPR_M1PFD.
+#define BS_FMC_PFAPR_M1PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M1PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M1PFD field.
+#define BR_FMC_PFAPR_M1PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M1PFD.
+#define BF_FMC_PFAPR_M1PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1PFD), uint32_t) & BM_FMC_PFAPR_M1PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1PFD field to a new value.
+#define BW_FMC_PFAPR_M1PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M2PFD   (18U)         //!< Bit position for FMC_PFAPR_M2PFD.
+#define BM_FMC_PFAPR_M2PFD   (0x00040000U) //!< Bit mask for FMC_PFAPR_M2PFD.
+#define BS_FMC_PFAPR_M2PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M2PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M2PFD field.
+#define BR_FMC_PFAPR_M2PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M2PFD.
+#define BF_FMC_PFAPR_M2PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2PFD), uint32_t) & BM_FMC_PFAPR_M2PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2PFD field to a new value.
+#define BW_FMC_PFAPR_M2PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M3PFD   (19U)         //!< Bit position for FMC_PFAPR_M3PFD.
+#define BM_FMC_PFAPR_M3PFD   (0x00080000U) //!< Bit mask for FMC_PFAPR_M3PFD.
+#define BS_FMC_PFAPR_M3PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M3PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M3PFD field.
+#define BR_FMC_PFAPR_M3PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M3PFD.
+#define BF_FMC_PFAPR_M3PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3PFD), uint32_t) & BM_FMC_PFAPR_M3PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3PFD field to a new value.
+#define BW_FMC_PFAPR_M3PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M4PFD   (20U)         //!< Bit position for FMC_PFAPR_M4PFD.
+#define BM_FMC_PFAPR_M4PFD   (0x00100000U) //!< Bit mask for FMC_PFAPR_M4PFD.
+#define BS_FMC_PFAPR_M4PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M4PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M4PFD field.
+#define BR_FMC_PFAPR_M4PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M4PFD.
+#define BF_FMC_PFAPR_M4PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4PFD), uint32_t) & BM_FMC_PFAPR_M4PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4PFD field to a new value.
+#define BW_FMC_PFAPR_M4PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M5PFD   (21U)         //!< Bit position for FMC_PFAPR_M5PFD.
+#define BM_FMC_PFAPR_M5PFD   (0x00200000U) //!< Bit mask for FMC_PFAPR_M5PFD.
+#define BS_FMC_PFAPR_M5PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M5PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M5PFD field.
+#define BR_FMC_PFAPR_M5PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M5PFD.
+#define BF_FMC_PFAPR_M5PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5PFD), uint32_t) & BM_FMC_PFAPR_M5PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5PFD field to a new value.
+#define BW_FMC_PFAPR_M5PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M6PFD   (22U)         //!< Bit position for FMC_PFAPR_M6PFD.
+#define BM_FMC_PFAPR_M6PFD   (0x00400000U) //!< Bit mask for FMC_PFAPR_M6PFD.
+#define BS_FMC_PFAPR_M6PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M6PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M6PFD field.
+#define BR_FMC_PFAPR_M6PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M6PFD.
+#define BF_FMC_PFAPR_M6PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6PFD), uint32_t) & BM_FMC_PFAPR_M6PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6PFD field to a new value.
+#define BW_FMC_PFAPR_M6PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M7PFD   (23U)         //!< Bit position for FMC_PFAPR_M7PFD.
+#define BM_FMC_PFAPR_M7PFD   (0x00800000U) //!< Bit mask for FMC_PFAPR_M7PFD.
+#define BS_FMC_PFAPR_M7PFD   (1U)          //!< Bit field size in bits for FMC_PFAPR_M7PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M7PFD field.
+#define BR_FMC_PFAPR_M7PFD   (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M7PFD.
+#define BF_FMC_PFAPR_M7PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7PFD), uint32_t) & BM_FMC_PFAPR_M7PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7PFD field to a new value.
+#define BW_FMC_PFAPR_M7PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_PFB0CR - Flash Bank 0 Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+typedef union _hw_fmc_pfb0cr
+{
+    uint32_t U;
+    struct _hw_fmc_pfb0cr_bitfields
+    {
+        uint32_t B0SEBE : 1;           //!< [0] Bank 0 Single Entry Buffer Enable
+        uint32_t B0IPE : 1;            //!< [1] Bank 0 Instruction Prefetch Enable
+        uint32_t B0DPE : 1;            //!< [2] Bank 0 Data Prefetch Enable
+        uint32_t B0ICE : 1;            //!< [3] Bank 0 Instruction Cache Enable
+        uint32_t B0DCE : 1;            //!< [4] Bank 0 Data Cache Enable
+        uint32_t CRCb : 3;             //!< [7:5] Cache Replacement Control
+        uint32_t RESERVED0 : 9;        //!< [16:8]
+        uint32_t B0MW : 2;             //!< [18:17] Bank 0 Memory Width
+        uint32_t S_B_INV : 1;          //!< [19] Invalidate Prefetch Speculation Buffer
+        uint32_t CINV_WAY : 4;         //!< [23:20] Cache Invalidate Way x
+        uint32_t CLCK_WAY : 4;         //!< [27:24] Cache Lock Way x
+        uint32_t B0RWSC : 4;           //!< [31:28] Bank 0 Read Wait State Control
+    } B;
+} hw_fmc_pfb0cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+//@{
+#define HW_FMC_PFB0CR_ADDR       (REGS_FMC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_PFB0CR            (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR)
+#define HW_FMC_PFB0CR_RD()       (HW_FMC_PFB0CR.U)
+#define HW_FMC_PFB0CR_WR(v)      (HW_FMC_PFB0CR.U = (v))
+#define HW_FMC_PFB0CR_SET(v)     (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() |  (v)))
+#define HW_FMC_PFB0CR_CLR(v)     (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() & ~(v)))
+#define HW_FMC_PFB0CR_TOG(v)     (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0 - Single entry buffer is disabled.
+ * - 1 - Single entry buffer is enabled.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0SEBE (0U)          //!< Bit position for FMC_PFB0CR_B0SEBE.
+#define BM_FMC_PFB0CR_B0SEBE (0x00000001U) //!< Bit mask for FMC_PFB0CR_B0SEBE.
+#define BS_FMC_PFB0CR_B0SEBE (1U)          //!< Bit field size in bits for FMC_PFB0CR_B0SEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0SEBE field.
+#define BR_FMC_PFB0CR_B0SEBE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0SEBE.
+#define BF_FMC_PFB0CR_B0SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0SEBE), uint32_t) & BM_FMC_PFB0CR_B0SEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0SEBE field to a new value.
+#define BW_FMC_PFB0CR_B0SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to instruction fetches.
+ * - 1 - Enable prefetches in response to instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0IPE  (1U)          //!< Bit position for FMC_PFB0CR_B0IPE.
+#define BM_FMC_PFB0CR_B0IPE  (0x00000002U) //!< Bit mask for FMC_PFB0CR_B0IPE.
+#define BS_FMC_PFB0CR_B0IPE  (1U)          //!< Bit field size in bits for FMC_PFB0CR_B0IPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0IPE field.
+#define BR_FMC_PFB0CR_B0IPE  (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0IPE.
+#define BF_FMC_PFB0CR_B0IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0IPE), uint32_t) & BM_FMC_PFB0CR_B0IPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0IPE field to a new value.
+#define BW_FMC_PFB0CR_B0IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to data references.
+ * - 1 - Enable prefetches in response to data references.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0DPE  (2U)          //!< Bit position for FMC_PFB0CR_B0DPE.
+#define BM_FMC_PFB0CR_B0DPE  (0x00000004U) //!< Bit mask for FMC_PFB0CR_B0DPE.
+#define BS_FMC_PFB0CR_B0DPE  (1U)          //!< Bit field size in bits for FMC_PFB0CR_B0DPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0DPE field.
+#define BR_FMC_PFB0CR_B0DPE  (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0DPE.
+#define BF_FMC_PFB0CR_B0DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DPE), uint32_t) & BM_FMC_PFB0CR_B0DPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0DPE field to a new value.
+#define BW_FMC_PFB0CR_B0DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache instruction fetches.
+ * - 1 - Cache instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0ICE  (3U)          //!< Bit position for FMC_PFB0CR_B0ICE.
+#define BM_FMC_PFB0CR_B0ICE  (0x00000008U) //!< Bit mask for FMC_PFB0CR_B0ICE.
+#define BS_FMC_PFB0CR_B0ICE  (1U)          //!< Bit field size in bits for FMC_PFB0CR_B0ICE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0ICE field.
+#define BR_FMC_PFB0CR_B0ICE  (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0ICE.
+#define BF_FMC_PFB0CR_B0ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0ICE), uint32_t) & BM_FMC_PFB0CR_B0ICE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0ICE field to a new value.
+#define BW_FMC_PFB0CR_B0ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache data references.
+ * - 1 - Cache data references.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0DCE  (4U)          //!< Bit position for FMC_PFB0CR_B0DCE.
+#define BM_FMC_PFB0CR_B0DCE  (0x00000010U) //!< Bit mask for FMC_PFB0CR_B0DCE.
+#define BS_FMC_PFB0CR_B0DCE  (1U)          //!< Bit field size in bits for FMC_PFB0CR_B0DCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0DCE field.
+#define BR_FMC_PFB0CR_B0DCE  (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0DCE.
+#define BF_FMC_PFB0CR_B0DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DCE), uint32_t) & BM_FMC_PFB0CR_B0DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0DCE field to a new value.
+#define BW_FMC_PFB0CR_B0DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 000 - LRU replacement algorithm per set across all four ways
+ * - 001 - Reserved
+ * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 1xx - Reserved
+ */
+//@{
+#define BP_FMC_PFB0CR_CRC    (5U)          //!< Bit position for FMC_PFB0CR_CRC.
+#define BM_FMC_PFB0CR_CRC    (0x000000E0U) //!< Bit mask for FMC_PFB0CR_CRC.
+#define BS_FMC_PFB0CR_CRC    (3U)          //!< Bit field size in bits for FMC_PFB0CR_CRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_CRC field.
+#define BR_FMC_PFB0CR_CRC    (HW_FMC_PFB0CR.B.CRC)
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_CRC.
+#define BF_FMC_PFB0CR_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CRC), uint32_t) & BM_FMC_PFB0CR_CRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC field to a new value.
+#define BW_FMC_PFB0CR_CRC(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 00 - 32 bits
+ * - 01 - 64 bits
+ * - 10 - 128 bits
+ * - 11 - Reserved
+ */
+//@{
+#define BP_FMC_PFB0CR_B0MW   (17U)         //!< Bit position for FMC_PFB0CR_B0MW.
+#define BM_FMC_PFB0CR_B0MW   (0x00060000U) //!< Bit mask for FMC_PFB0CR_B0MW.
+#define BS_FMC_PFB0CR_B0MW   (2U)          //!< Bit field size in bits for FMC_PFB0CR_B0MW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0MW field.
+#define BR_FMC_PFB0CR_B0MW   (HW_FMC_PFB0CR.B.B0MW)
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0 - Speculation buffer and single entry buffer are not affected.
+ * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+//@{
+#define BP_FMC_PFB0CR_S_B_INV (19U)        //!< Bit position for FMC_PFB0CR_S_B_INV.
+#define BM_FMC_PFB0CR_S_B_INV (0x00080000U) //!< Bit mask for FMC_PFB0CR_S_B_INV.
+#define BS_FMC_PFB0CR_S_B_INV (1U)         //!< Bit field size in bits for FMC_PFB0CR_S_B_INV.
+
+//! @brief Format value for bitfield FMC_PFB0CR_S_B_INV.
+#define BF_FMC_PFB0CR_S_B_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_S_B_INV), uint32_t) & BM_FMC_PFB0CR_S_B_INV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the S_B_INV field to a new value.
+#define BW_FMC_PFB0CR_S_B_INV(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_S_B_INV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0 - No cache way invalidation for the corresponding cache
+ * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
+ *     and vld bits of ways selected
+ */
+//@{
+#define BP_FMC_PFB0CR_CINV_WAY (20U)       //!< Bit position for FMC_PFB0CR_CINV_WAY.
+#define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) //!< Bit mask for FMC_PFB0CR_CINV_WAY.
+#define BS_FMC_PFB0CR_CINV_WAY (4U)        //!< Bit field size in bits for FMC_PFB0CR_CINV_WAY.
+
+//! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY.
+#define BF_FMC_PFB0CR_CINV_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CINV_WAY), uint32_t) & BM_FMC_PFB0CR_CINV_WAY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINV_WAY field to a new value.
+#define BW_FMC_PFB0CR_CINV_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0 - Cache way is unlocked and may be displaced
+ * - 1 - Cache way is locked and its contents are not displaced
+ */
+//@{
+#define BP_FMC_PFB0CR_CLCK_WAY (24U)       //!< Bit position for FMC_PFB0CR_CLCK_WAY.
+#define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) //!< Bit mask for FMC_PFB0CR_CLCK_WAY.
+#define BS_FMC_PFB0CR_CLCK_WAY (4U)        //!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field.
+#define BR_FMC_PFB0CR_CLCK_WAY (HW_FMC_PFB0CR.B.CLCK_WAY)
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY.
+#define BF_FMC_PFB0CR_CLCK_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CLCK_WAY), uint32_t) & BM_FMC_PFB0CR_CLCK_WAY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLCK_WAY field to a new value.
+#define BW_FMC_PFB0CR_CLCK_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0RWSC (28U)         //!< Bit position for FMC_PFB0CR_B0RWSC.
+#define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) //!< Bit mask for FMC_PFB0CR_B0RWSC.
+#define BS_FMC_PFB0CR_B0RWSC (4U)          //!< Bit field size in bits for FMC_PFB0CR_B0RWSC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0RWSC field.
+#define BR_FMC_PFB0CR_B0RWSC (HW_FMC_PFB0CR.B.B0RWSC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_PFB1CR - Flash Bank 1 Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+typedef union _hw_fmc_pfb1cr
+{
+    uint32_t U;
+    struct _hw_fmc_pfb1cr_bitfields
+    {
+        uint32_t B1SEBE : 1;           //!< [0] Bank 1 Single Entry Buffer Enable
+        uint32_t B1IPE : 1;            //!< [1] Bank 1 Instruction Prefetch Enable
+        uint32_t B1DPE : 1;            //!< [2] Bank 1 Data Prefetch Enable
+        uint32_t B1ICE : 1;            //!< [3] Bank 1 Instruction Cache Enable
+        uint32_t B1DCE : 1;            //!< [4] Bank 1 Data Cache Enable
+        uint32_t RESERVED0 : 12;       //!< [16:5]
+        uint32_t B1MW : 2;             //!< [18:17] Bank 1 Memory Width
+        uint32_t RESERVED1 : 9;        //!< [27:19]
+        uint32_t B1RWSC : 4;           //!< [31:28] Bank 1 Read Wait State Control
+    } B;
+} hw_fmc_pfb1cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+//@{
+#define HW_FMC_PFB1CR_ADDR       (REGS_FMC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_PFB1CR            (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR)
+#define HW_FMC_PFB1CR_RD()       (HW_FMC_PFB1CR.U)
+#define HW_FMC_PFB1CR_WR(v)      (HW_FMC_PFB1CR.U = (v))
+#define HW_FMC_PFB1CR_SET(v)     (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() |  (v)))
+#define HW_FMC_PFB1CR_CLR(v)     (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() & ~(v)))
+#define HW_FMC_PFB1CR_TOG(v)     (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0 - Single entry buffer is disabled.
+ * - 1 - Single entry buffer is enabled.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1SEBE (0U)          //!< Bit position for FMC_PFB1CR_B1SEBE.
+#define BM_FMC_PFB1CR_B1SEBE (0x00000001U) //!< Bit mask for FMC_PFB1CR_B1SEBE.
+#define BS_FMC_PFB1CR_B1SEBE (1U)          //!< Bit field size in bits for FMC_PFB1CR_B1SEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1SEBE field.
+#define BR_FMC_PFB1CR_B1SEBE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1SEBE.
+#define BF_FMC_PFB1CR_B1SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1SEBE), uint32_t) & BM_FMC_PFB1CR_B1SEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1SEBE field to a new value.
+#define BW_FMC_PFB1CR_B1SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to instruction fetches.
+ * - 1 - Enable prefetches in response to instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1IPE  (1U)          //!< Bit position for FMC_PFB1CR_B1IPE.
+#define BM_FMC_PFB1CR_B1IPE  (0x00000002U) //!< Bit mask for FMC_PFB1CR_B1IPE.
+#define BS_FMC_PFB1CR_B1IPE  (1U)          //!< Bit field size in bits for FMC_PFB1CR_B1IPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1IPE field.
+#define BR_FMC_PFB1CR_B1IPE  (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1IPE.
+#define BF_FMC_PFB1CR_B1IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1IPE), uint32_t) & BM_FMC_PFB1CR_B1IPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1IPE field to a new value.
+#define BW_FMC_PFB1CR_B1IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to data references.
+ * - 1 - Enable prefetches in response to data references.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1DPE  (2U)          //!< Bit position for FMC_PFB1CR_B1DPE.
+#define BM_FMC_PFB1CR_B1DPE  (0x00000004U) //!< Bit mask for FMC_PFB1CR_B1DPE.
+#define BS_FMC_PFB1CR_B1DPE  (1U)          //!< Bit field size in bits for FMC_PFB1CR_B1DPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1DPE field.
+#define BR_FMC_PFB1CR_B1DPE  (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1DPE.
+#define BF_FMC_PFB1CR_B1DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DPE), uint32_t) & BM_FMC_PFB1CR_B1DPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1DPE field to a new value.
+#define BW_FMC_PFB1CR_B1DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache instruction fetches.
+ * - 1 - Cache instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1ICE  (3U)          //!< Bit position for FMC_PFB1CR_B1ICE.
+#define BM_FMC_PFB1CR_B1ICE  (0x00000008U) //!< Bit mask for FMC_PFB1CR_B1ICE.
+#define BS_FMC_PFB1CR_B1ICE  (1U)          //!< Bit field size in bits for FMC_PFB1CR_B1ICE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1ICE field.
+#define BR_FMC_PFB1CR_B1ICE  (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1ICE.
+#define BF_FMC_PFB1CR_B1ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1ICE), uint32_t) & BM_FMC_PFB1CR_B1ICE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1ICE field to a new value.
+#define BW_FMC_PFB1CR_B1ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache data references.
+ * - 1 - Cache data references.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1DCE  (4U)          //!< Bit position for FMC_PFB1CR_B1DCE.
+#define BM_FMC_PFB1CR_B1DCE  (0x00000010U) //!< Bit mask for FMC_PFB1CR_B1DCE.
+#define BS_FMC_PFB1CR_B1DCE  (1U)          //!< Bit field size in bits for FMC_PFB1CR_B1DCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1DCE field.
+#define BR_FMC_PFB1CR_B1DCE  (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1DCE.
+#define BF_FMC_PFB1CR_B1DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DCE), uint32_t) & BM_FMC_PFB1CR_B1DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1DCE field to a new value.
+#define BW_FMC_PFB1CR_B1DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 00 - 32 bits
+ * - 01 - 64 bits
+ * - 10 - 128 bits
+ * - 11 - Reserved
+ */
+//@{
+#define BP_FMC_PFB1CR_B1MW   (17U)         //!< Bit position for FMC_PFB1CR_B1MW.
+#define BM_FMC_PFB1CR_B1MW   (0x00060000U) //!< Bit mask for FMC_PFB1CR_B1MW.
+#define BS_FMC_PFB1CR_B1MW   (2U)          //!< Bit field size in bits for FMC_PFB1CR_B1MW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1MW field.
+#define BR_FMC_PFB1CR_B1MW   (HW_FMC_PFB1CR.B.B1MW)
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1RWSC (28U)         //!< Bit position for FMC_PFB1CR_B1RWSC.
+#define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) //!< Bit mask for FMC_PFB1CR_B1RWSC.
+#define BS_FMC_PFB1CR_B1RWSC (4U)          //!< Bit field size in bits for FMC_PFB1CR_B1RWSC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1RWSC field.
+#define BR_FMC_PFB1CR_B1RWSC (HW_FMC_PFB1CR.B.B1RWSC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW0Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw0sn
+{
+    uint32_t U;
+    struct _hw_fmc_tagvdw0sn_bitfields
+    {
+        uint32_t valid : 1;            //!< [0] 1-bit valid for cache entry
+        uint32_t RESERVED0 : 4;        //!< [4:1]
+        uint32_t tag : 14;             //!< [18:5] 14-bit tag for cache entry
+        uint32_t RESERVED1 : 13;       //!< [31:19]
+    } B;
+} hw_fmc_tagvdw0sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW0Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW0Sn_ADDR(n) (REGS_FMC_BASE + 0x100U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW0Sn(n)      (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(n))
+#define HW_FMC_TAGVDW0Sn_RD(n)   (HW_FMC_TAGVDW0Sn(n).U)
+#define HW_FMC_TAGVDW0Sn_WR(n, v) (HW_FMC_TAGVDW0Sn(n).U = (v))
+#define HW_FMC_TAGVDW0Sn_SET(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) |  (v)))
+#define HW_FMC_TAGVDW0Sn_CLR(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW0Sn_TOG(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW0Sn_valid (0U)        //!< Bit position for FMC_TAGVDW0Sn_valid.
+#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW0Sn_valid.
+#define BS_FMC_TAGVDW0Sn_valid (1U)        //!< Bit field size in bits for FMC_TAGVDW0Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW0Sn_valid field.
+#define BR_FMC_TAGVDW0Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW0Sn_valid.
+#define BF_FMC_TAGVDW0Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_valid), uint32_t) & BM_FMC_TAGVDW0Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW0Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW0Sn_tag (5U)          //!< Bit position for FMC_TAGVDW0Sn_tag.
+#define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW0Sn_tag.
+#define BS_FMC_TAGVDW0Sn_tag (14U)         //!< Bit field size in bits for FMC_TAGVDW0Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW0Sn_tag field.
+#define BR_FMC_TAGVDW0Sn_tag(n) (HW_FMC_TAGVDW0Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW0Sn_tag.
+#define BF_FMC_TAGVDW0Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_tag), uint32_t) & BM_FMC_TAGVDW0Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW0Sn_tag(n, v) (HW_FMC_TAGVDW0Sn_WR(n, (HW_FMC_TAGVDW0Sn_RD(n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW1Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw1sn
+{
+    uint32_t U;
+    struct _hw_fmc_tagvdw1sn_bitfields
+    {
+        uint32_t valid : 1;            //!< [0] 1-bit valid for cache entry
+        uint32_t RESERVED0 : 4;        //!< [4:1]
+        uint32_t tag : 14;             //!< [18:5] 14-bit tag for cache entry
+        uint32_t RESERVED1 : 13;       //!< [31:19]
+    } B;
+} hw_fmc_tagvdw1sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW1Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW1Sn_ADDR(n) (REGS_FMC_BASE + 0x110U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW1Sn(n)      (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(n))
+#define HW_FMC_TAGVDW1Sn_RD(n)   (HW_FMC_TAGVDW1Sn(n).U)
+#define HW_FMC_TAGVDW1Sn_WR(n, v) (HW_FMC_TAGVDW1Sn(n).U = (v))
+#define HW_FMC_TAGVDW1Sn_SET(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) |  (v)))
+#define HW_FMC_TAGVDW1Sn_CLR(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW1Sn_TOG(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW1Sn_valid (0U)        //!< Bit position for FMC_TAGVDW1Sn_valid.
+#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW1Sn_valid.
+#define BS_FMC_TAGVDW1Sn_valid (1U)        //!< Bit field size in bits for FMC_TAGVDW1Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW1Sn_valid field.
+#define BR_FMC_TAGVDW1Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW1Sn_valid.
+#define BF_FMC_TAGVDW1Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_valid), uint32_t) & BM_FMC_TAGVDW1Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW1Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW1Sn_tag (5U)          //!< Bit position for FMC_TAGVDW1Sn_tag.
+#define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW1Sn_tag.
+#define BS_FMC_TAGVDW1Sn_tag (14U)         //!< Bit field size in bits for FMC_TAGVDW1Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW1Sn_tag field.
+#define BR_FMC_TAGVDW1Sn_tag(n) (HW_FMC_TAGVDW1Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW1Sn_tag.
+#define BF_FMC_TAGVDW1Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_tag), uint32_t) & BM_FMC_TAGVDW1Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW1Sn_tag(n, v) (HW_FMC_TAGVDW1Sn_WR(n, (HW_FMC_TAGVDW1Sn_RD(n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW2Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw2sn
+{
+    uint32_t U;
+    struct _hw_fmc_tagvdw2sn_bitfields
+    {
+        uint32_t valid : 1;            //!< [0] 1-bit valid for cache entry
+        uint32_t RESERVED0 : 4;        //!< [4:1]
+        uint32_t tag : 14;             //!< [18:5] 14-bit tag for cache entry
+        uint32_t RESERVED1 : 13;       //!< [31:19]
+    } B;
+} hw_fmc_tagvdw2sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW2Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW2Sn_ADDR(n) (REGS_FMC_BASE + 0x120U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW2Sn(n)      (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(n))
+#define HW_FMC_TAGVDW2Sn_RD(n)   (HW_FMC_TAGVDW2Sn(n).U)
+#define HW_FMC_TAGVDW2Sn_WR(n, v) (HW_FMC_TAGVDW2Sn(n).U = (v))
+#define HW_FMC_TAGVDW2Sn_SET(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) |  (v)))
+#define HW_FMC_TAGVDW2Sn_CLR(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW2Sn_TOG(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW2Sn_valid (0U)        //!< Bit position for FMC_TAGVDW2Sn_valid.
+#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW2Sn_valid.
+#define BS_FMC_TAGVDW2Sn_valid (1U)        //!< Bit field size in bits for FMC_TAGVDW2Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW2Sn_valid field.
+#define BR_FMC_TAGVDW2Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW2Sn_valid.
+#define BF_FMC_TAGVDW2Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_valid), uint32_t) & BM_FMC_TAGVDW2Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW2Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW2Sn_tag (5U)          //!< Bit position for FMC_TAGVDW2Sn_tag.
+#define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW2Sn_tag.
+#define BS_FMC_TAGVDW2Sn_tag (14U)         //!< Bit field size in bits for FMC_TAGVDW2Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW2Sn_tag field.
+#define BR_FMC_TAGVDW2Sn_tag(n) (HW_FMC_TAGVDW2Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW2Sn_tag.
+#define BF_FMC_TAGVDW2Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_tag), uint32_t) & BM_FMC_TAGVDW2Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW2Sn_tag(n, v) (HW_FMC_TAGVDW2Sn_WR(n, (HW_FMC_TAGVDW2Sn_RD(n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW3Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw3sn
+{
+    uint32_t U;
+    struct _hw_fmc_tagvdw3sn_bitfields
+    {
+        uint32_t valid : 1;            //!< [0] 1-bit valid for cache entry
+        uint32_t RESERVED0 : 4;        //!< [4:1]
+        uint32_t tag : 14;             //!< [18:5] 14-bit tag for cache entry
+        uint32_t RESERVED1 : 13;       //!< [31:19]
+    } B;
+} hw_fmc_tagvdw3sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW3Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW3Sn_ADDR(n) (REGS_FMC_BASE + 0x130U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW3Sn(n)      (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(n))
+#define HW_FMC_TAGVDW3Sn_RD(n)   (HW_FMC_TAGVDW3Sn(n).U)
+#define HW_FMC_TAGVDW3Sn_WR(n, v) (HW_FMC_TAGVDW3Sn(n).U = (v))
+#define HW_FMC_TAGVDW3Sn_SET(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) |  (v)))
+#define HW_FMC_TAGVDW3Sn_CLR(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW3Sn_TOG(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW3Sn_valid (0U)        //!< Bit position for FMC_TAGVDW3Sn_valid.
+#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW3Sn_valid.
+#define BS_FMC_TAGVDW3Sn_valid (1U)        //!< Bit field size in bits for FMC_TAGVDW3Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW3Sn_valid field.
+#define BR_FMC_TAGVDW3Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW3Sn_valid.
+#define BF_FMC_TAGVDW3Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_valid), uint32_t) & BM_FMC_TAGVDW3Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW3Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW3Sn_tag (5U)          //!< Bit position for FMC_TAGVDW3Sn_tag.
+#define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW3Sn_tag.
+#define BS_FMC_TAGVDW3Sn_tag (14U)         //!< Bit field size in bits for FMC_TAGVDW3Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW3Sn_tag field.
+#define BR_FMC_TAGVDW3Sn_tag(n) (HW_FMC_TAGVDW3Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW3Sn_tag.
+#define BF_FMC_TAGVDW3Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_tag), uint32_t) & BM_FMC_TAGVDW3Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW3Sn_tag(n, v) (HW_FMC_TAGVDW3Sn_WR(n, (HW_FMC_TAGVDW3Sn_RD(n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw0snu
+{
+    uint32_t U;
+    struct _hw_fmc_dataw0snu_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [63:32] of data entry
+    } B;
+} hw_fmc_dataw0snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW0SnU register
+ */
+//@{
+#define HW_FMC_DATAW0SnU_COUNT (4U)
+
+#define HW_FMC_DATAW0SnU_ADDR(n) (REGS_FMC_BASE + 0x200U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW0SnU(n)      (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(n))
+#define HW_FMC_DATAW0SnU_RD(n)   (HW_FMC_DATAW0SnU(n).U)
+#define HW_FMC_DATAW0SnU_WR(n, v) (HW_FMC_DATAW0SnU(n).U = (v))
+#define HW_FMC_DATAW0SnU_SET(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) |  (v)))
+#define HW_FMC_DATAW0SnU_CLR(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW0SnU_TOG(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW0SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW0SnU_data (0U)         //!< Bit position for FMC_DATAW0SnU_data.
+#define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnU_data.
+#define BS_FMC_DATAW0SnU_data (32U)        //!< Bit field size in bits for FMC_DATAW0SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW0SnU_data field.
+#define BR_FMC_DATAW0SnU_data(n) (HW_FMC_DATAW0SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW0SnU_data.
+#define BF_FMC_DATAW0SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnU_data), uint32_t) & BM_FMC_DATAW0SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW0SnU_data(n, v) (HW_FMC_DATAW0SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw0snl
+{
+    uint32_t U;
+    struct _hw_fmc_dataw0snl_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [31:0] of data entry
+    } B;
+} hw_fmc_dataw0snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW0SnL register
+ */
+//@{
+#define HW_FMC_DATAW0SnL_COUNT (4U)
+
+#define HW_FMC_DATAW0SnL_ADDR(n) (REGS_FMC_BASE + 0x204U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW0SnL(n)      (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(n))
+#define HW_FMC_DATAW0SnL_RD(n)   (HW_FMC_DATAW0SnL(n).U)
+#define HW_FMC_DATAW0SnL_WR(n, v) (HW_FMC_DATAW0SnL(n).U = (v))
+#define HW_FMC_DATAW0SnL_SET(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) |  (v)))
+#define HW_FMC_DATAW0SnL_CLR(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW0SnL_TOG(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW0SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW0SnL_data (0U)         //!< Bit position for FMC_DATAW0SnL_data.
+#define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnL_data.
+#define BS_FMC_DATAW0SnL_data (32U)        //!< Bit field size in bits for FMC_DATAW0SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW0SnL_data field.
+#define BR_FMC_DATAW0SnL_data(n) (HW_FMC_DATAW0SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW0SnL_data.
+#define BF_FMC_DATAW0SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnL_data), uint32_t) & BM_FMC_DATAW0SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW0SnL_data(n, v) (HW_FMC_DATAW0SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw1snu
+{
+    uint32_t U;
+    struct _hw_fmc_dataw1snu_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [63:32] of data entry
+    } B;
+} hw_fmc_dataw1snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW1SnU register
+ */
+//@{
+#define HW_FMC_DATAW1SnU_COUNT (4U)
+
+#define HW_FMC_DATAW1SnU_ADDR(n) (REGS_FMC_BASE + 0x220U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW1SnU(n)      (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(n))
+#define HW_FMC_DATAW1SnU_RD(n)   (HW_FMC_DATAW1SnU(n).U)
+#define HW_FMC_DATAW1SnU_WR(n, v) (HW_FMC_DATAW1SnU(n).U = (v))
+#define HW_FMC_DATAW1SnU_SET(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) |  (v)))
+#define HW_FMC_DATAW1SnU_CLR(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW1SnU_TOG(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW1SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW1SnU_data (0U)         //!< Bit position for FMC_DATAW1SnU_data.
+#define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnU_data.
+#define BS_FMC_DATAW1SnU_data (32U)        //!< Bit field size in bits for FMC_DATAW1SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW1SnU_data field.
+#define BR_FMC_DATAW1SnU_data(n) (HW_FMC_DATAW1SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW1SnU_data.
+#define BF_FMC_DATAW1SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnU_data), uint32_t) & BM_FMC_DATAW1SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW1SnU_data(n, v) (HW_FMC_DATAW1SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw1snl
+{
+    uint32_t U;
+    struct _hw_fmc_dataw1snl_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [31:0] of data entry
+    } B;
+} hw_fmc_dataw1snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW1SnL register
+ */
+//@{
+#define HW_FMC_DATAW1SnL_COUNT (4U)
+
+#define HW_FMC_DATAW1SnL_ADDR(n) (REGS_FMC_BASE + 0x224U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW1SnL(n)      (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(n))
+#define HW_FMC_DATAW1SnL_RD(n)   (HW_FMC_DATAW1SnL(n).U)
+#define HW_FMC_DATAW1SnL_WR(n, v) (HW_FMC_DATAW1SnL(n).U = (v))
+#define HW_FMC_DATAW1SnL_SET(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) |  (v)))
+#define HW_FMC_DATAW1SnL_CLR(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW1SnL_TOG(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW1SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW1SnL_data (0U)         //!< Bit position for FMC_DATAW1SnL_data.
+#define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnL_data.
+#define BS_FMC_DATAW1SnL_data (32U)        //!< Bit field size in bits for FMC_DATAW1SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW1SnL_data field.
+#define BR_FMC_DATAW1SnL_data(n) (HW_FMC_DATAW1SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW1SnL_data.
+#define BF_FMC_DATAW1SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnL_data), uint32_t) & BM_FMC_DATAW1SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW1SnL_data(n, v) (HW_FMC_DATAW1SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw2snu
+{
+    uint32_t U;
+    struct _hw_fmc_dataw2snu_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [63:32] of data entry
+    } B;
+} hw_fmc_dataw2snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW2SnU register
+ */
+//@{
+#define HW_FMC_DATAW2SnU_COUNT (4U)
+
+#define HW_FMC_DATAW2SnU_ADDR(n) (REGS_FMC_BASE + 0x240U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW2SnU(n)      (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(n))
+#define HW_FMC_DATAW2SnU_RD(n)   (HW_FMC_DATAW2SnU(n).U)
+#define HW_FMC_DATAW2SnU_WR(n, v) (HW_FMC_DATAW2SnU(n).U = (v))
+#define HW_FMC_DATAW2SnU_SET(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) |  (v)))
+#define HW_FMC_DATAW2SnU_CLR(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW2SnU_TOG(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW2SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW2SnU_data (0U)         //!< Bit position for FMC_DATAW2SnU_data.
+#define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnU_data.
+#define BS_FMC_DATAW2SnU_data (32U)        //!< Bit field size in bits for FMC_DATAW2SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW2SnU_data field.
+#define BR_FMC_DATAW2SnU_data(n) (HW_FMC_DATAW2SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW2SnU_data.
+#define BF_FMC_DATAW2SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnU_data), uint32_t) & BM_FMC_DATAW2SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW2SnU_data(n, v) (HW_FMC_DATAW2SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw2snl
+{
+    uint32_t U;
+    struct _hw_fmc_dataw2snl_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [31:0] of data entry
+    } B;
+} hw_fmc_dataw2snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW2SnL register
+ */
+//@{
+#define HW_FMC_DATAW2SnL_COUNT (4U)
+
+#define HW_FMC_DATAW2SnL_ADDR(n) (REGS_FMC_BASE + 0x244U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW2SnL(n)      (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(n))
+#define HW_FMC_DATAW2SnL_RD(n)   (HW_FMC_DATAW2SnL(n).U)
+#define HW_FMC_DATAW2SnL_WR(n, v) (HW_FMC_DATAW2SnL(n).U = (v))
+#define HW_FMC_DATAW2SnL_SET(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) |  (v)))
+#define HW_FMC_DATAW2SnL_CLR(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW2SnL_TOG(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW2SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW2SnL_data (0U)         //!< Bit position for FMC_DATAW2SnL_data.
+#define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnL_data.
+#define BS_FMC_DATAW2SnL_data (32U)        //!< Bit field size in bits for FMC_DATAW2SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW2SnL_data field.
+#define BR_FMC_DATAW2SnL_data(n) (HW_FMC_DATAW2SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW2SnL_data.
+#define BF_FMC_DATAW2SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnL_data), uint32_t) & BM_FMC_DATAW2SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW2SnL_data(n, v) (HW_FMC_DATAW2SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw3snu
+{
+    uint32_t U;
+    struct _hw_fmc_dataw3snu_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [63:32] of data entry
+    } B;
+} hw_fmc_dataw3snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW3SnU register
+ */
+//@{
+#define HW_FMC_DATAW3SnU_COUNT (4U)
+
+#define HW_FMC_DATAW3SnU_ADDR(n) (REGS_FMC_BASE + 0x260U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW3SnU(n)      (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(n))
+#define HW_FMC_DATAW3SnU_RD(n)   (HW_FMC_DATAW3SnU(n).U)
+#define HW_FMC_DATAW3SnU_WR(n, v) (HW_FMC_DATAW3SnU(n).U = (v))
+#define HW_FMC_DATAW3SnU_SET(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) |  (v)))
+#define HW_FMC_DATAW3SnU_CLR(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW3SnU_TOG(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW3SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW3SnU_data (0U)         //!< Bit position for FMC_DATAW3SnU_data.
+#define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnU_data.
+#define BS_FMC_DATAW3SnU_data (32U)        //!< Bit field size in bits for FMC_DATAW3SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW3SnU_data field.
+#define BR_FMC_DATAW3SnU_data(n) (HW_FMC_DATAW3SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW3SnU_data.
+#define BF_FMC_DATAW3SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnU_data), uint32_t) & BM_FMC_DATAW3SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW3SnU_data(n, v) (HW_FMC_DATAW3SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw3snl
+{
+    uint32_t U;
+    struct _hw_fmc_dataw3snl_bitfields
+    {
+        uint32_t data : 32;            //!< [31:0] Bits [31:0] of data entry
+    } B;
+} hw_fmc_dataw3snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW3SnL register
+ */
+//@{
+#define HW_FMC_DATAW3SnL_COUNT (4U)
+
+#define HW_FMC_DATAW3SnL_ADDR(n) (REGS_FMC_BASE + 0x264U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW3SnL(n)      (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(n))
+#define HW_FMC_DATAW3SnL_RD(n)   (HW_FMC_DATAW3SnL(n).U)
+#define HW_FMC_DATAW3SnL_WR(n, v) (HW_FMC_DATAW3SnL(n).U = (v))
+#define HW_FMC_DATAW3SnL_SET(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) |  (v)))
+#define HW_FMC_DATAW3SnL_CLR(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW3SnL_TOG(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW3SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW3SnL_data (0U)         //!< Bit position for FMC_DATAW3SnL_data.
+#define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnL_data.
+#define BS_FMC_DATAW3SnL_data (32U)        //!< Bit field size in bits for FMC_DATAW3SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW3SnL_data field.
+#define BR_FMC_DATAW3SnL_data(n) (HW_FMC_DATAW3SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW3SnL_data.
+#define BF_FMC_DATAW3SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnL_data), uint32_t) & BM_FMC_DATAW3SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW3SnL_data(n, v) (HW_FMC_DATAW3SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_fmc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FMC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_fmc
+{
+    __IO hw_fmc_pfapr_t PFAPR;             //!< [0x0] Flash Access Protection Register
+    __IO hw_fmc_pfb0cr_t PFB0CR;           //!< [0x4] Flash Bank 0 Control Register
+    __IO hw_fmc_pfb1cr_t PFB1CR;           //!< [0x8] Flash Bank 1 Control Register
+    uint8_t _reserved0[244];
+    __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4];  //!< [0x100] Cache Tag Storage
+    __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4];  //!< [0x110] Cache Tag Storage
+    __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4];  //!< [0x120] Cache Tag Storage
+    __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4];  //!< [0x130] Cache Tag Storage
+    uint8_t _reserved1[192];
+    struct {
+        __IO hw_fmc_dataw0snu_t DATAW0SnU; //!< [0x200] Cache Data Storage (upper word)
+        __IO hw_fmc_dataw0snl_t DATAW0SnL; //!< [0x204] Cache Data Storage (lower word)
+    } DATAW0Sn[4];
+    struct {
+        __IO hw_fmc_dataw1snu_t DATAW1SnU; //!< [0x220] Cache Data Storage (upper word)
+        __IO hw_fmc_dataw1snl_t DATAW1SnL; //!< [0x224] Cache Data Storage (lower word)
+    } DATAW1Sn[4];
+    struct {
+        __IO hw_fmc_dataw2snu_t DATAW2SnU; //!< [0x240] Cache Data Storage (upper word)
+        __IO hw_fmc_dataw2snl_t DATAW2SnL; //!< [0x244] Cache Data Storage (lower word)
+    } DATAW2Sn[4];
+    struct {
+        __IO hw_fmc_dataw3snu_t DATAW3SnU; //!< [0x260] Cache Data Storage (upper word)
+        __IO hw_fmc_dataw3snl_t DATAW3SnL; //!< [0x264] Cache Data Storage (lower word)
+    } DATAW3Sn[4];
+} hw_fmc_t;
+#pragma pack()
+
+//! @brief Macro to access all FMC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_FMC</code>.
+#define HW_FMC         (*(hw_fmc_t *) REGS_FMC_BASE)
+#endif
+
+#endif // __HW_FMC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h
new file mode 100644
index 0000000000..9bdf188c76
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h
@@ -0,0 +1,2500 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FTFE_REGISTERS_H__
+#define __HW_FTFE_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - HW_FTFE_FSTAT - Flash Status Register
+ * - HW_FTFE_FCNFG - Flash Configuration Register
+ * - HW_FTFE_FSEC - Flash Security Register
+ * - HW_FTFE_FOPT - Flash Option Register
+ * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOBB - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOBA - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - HW_FTFE_FPROT3 - Program Flash Protection Registers
+ * - HW_FTFE_FPROT2 - Program Flash Protection Registers
+ * - HW_FTFE_FPROT1 - Program Flash Protection Registers
+ * - HW_FTFE_FPROT0 - Program Flash Protection Registers
+ * - HW_FTFE_FEPROT - EEPROM Protection Register
+ * - HW_FTFE_FDPROT - Data Flash Protection Register
+ *
+ * - hw_ftfe_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FTFE_BASE
+#define HW_FTFE_INSTANCE_COUNT (1U) //!< Number of instances of the FTFE module.
+#define REGS_FTFE_BASE (0x40020000U) //!< Base address for FTFE.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FSTAT - Flash Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+typedef union _hw_ftfe_fstat
+{
+    uint8_t U;
+    struct _hw_ftfe_fstat_bitfields
+    {
+        uint8_t MGSTAT0 : 1;           //!< [0] Memory Controller Command Completion
+                                       //! Status Flag
+        uint8_t RESERVED0 : 3;         //!< [3:1]
+        uint8_t FPVIOL : 1;            //!< [4] Flash Protection Violation Flag
+        uint8_t ACCERR : 1;            //!< [5] Flash Access Error Flag
+        uint8_t RDCOLERR : 1;          //!< [6] FTFE Read Collision Error Flag
+        uint8_t CCIF : 1;              //!< [7] Command Complete Interrupt Flag
+    } B;
+} hw_ftfe_fstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+//@{
+#define HW_FTFE_FSTAT_ADDR       (REGS_FTFE_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FSTAT            (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR)
+#define HW_FTFE_FSTAT_RD()       (HW_FTFE_FSTAT.U)
+#define HW_FTFE_FSTAT_WR(v)      (HW_FTFE_FSTAT.U = (v))
+#define HW_FTFE_FSTAT_SET(v)     (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() |  (v)))
+#define HW_FTFE_FSTAT_CLR(v)     (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() & ~(v)))
+#define HW_FTFE_FSTAT_TOG(v)     (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+//@{
+#define BP_FTFE_FSTAT_MGSTAT0 (0U)         //!< Bit position for FTFE_FSTAT_MGSTAT0.
+#define BM_FTFE_FSTAT_MGSTAT0 (0x01U)      //!< Bit mask for FTFE_FSTAT_MGSTAT0.
+#define BS_FTFE_FSTAT_MGSTAT0 (1U)         //!< Bit field size in bits for FTFE_FSTAT_MGSTAT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field.
+#define BR_FTFE_FSTAT_MGSTAT0 (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_MGSTAT0))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0 - No protection violation detected
+ * - 1 - Protection violation detected
+ */
+//@{
+#define BP_FTFE_FSTAT_FPVIOL (4U)          //!< Bit position for FTFE_FSTAT_FPVIOL.
+#define BM_FTFE_FSTAT_FPVIOL (0x10U)       //!< Bit mask for FTFE_FSTAT_FPVIOL.
+#define BS_FTFE_FSTAT_FPVIOL (1U)          //!< Bit field size in bits for FTFE_FSTAT_FPVIOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_FPVIOL field.
+#define BR_FTFE_FSTAT_FPVIOL (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_FPVIOL.
+#define BF_FTFE_FSTAT_FPVIOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_FPVIOL), uint8_t) & BM_FTFE_FSTAT_FPVIOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FPVIOL field to a new value.
+#define BW_FTFE_FSTAT_FPVIOL(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0 - No access error detected
+ * - 1 - Access error detected
+ */
+//@{
+#define BP_FTFE_FSTAT_ACCERR (5U)          //!< Bit position for FTFE_FSTAT_ACCERR.
+#define BM_FTFE_FSTAT_ACCERR (0x20U)       //!< Bit mask for FTFE_FSTAT_ACCERR.
+#define BS_FTFE_FSTAT_ACCERR (1U)          //!< Bit field size in bits for FTFE_FSTAT_ACCERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_ACCERR field.
+#define BR_FTFE_FSTAT_ACCERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_ACCERR.
+#define BF_FTFE_FSTAT_ACCERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_ACCERR), uint8_t) & BM_FTFE_FSTAT_ACCERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACCERR field to a new value.
+#define BW_FTFE_FSTAT_ACCERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0 - No collision error detected
+ * - 1 - Collision error detected
+ */
+//@{
+#define BP_FTFE_FSTAT_RDCOLERR (6U)        //!< Bit position for FTFE_FSTAT_RDCOLERR.
+#define BM_FTFE_FSTAT_RDCOLERR (0x40U)     //!< Bit mask for FTFE_FSTAT_RDCOLERR.
+#define BS_FTFE_FSTAT_RDCOLERR (1U)        //!< Bit field size in bits for FTFE_FSTAT_RDCOLERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_RDCOLERR field.
+#define BR_FTFE_FSTAT_RDCOLERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR.
+#define BF_FTFE_FSTAT_RDCOLERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_RDCOLERR), uint8_t) & BM_FTFE_FSTAT_RDCOLERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDCOLERR field to a new value.
+#define BW_FTFE_FSTAT_RDCOLERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0 - FTFE command or EEPROM file system operation in progress
+ * - 1 - FTFE command or EEPROM file system operation has completed
+ */
+//@{
+#define BP_FTFE_FSTAT_CCIF   (7U)          //!< Bit position for FTFE_FSTAT_CCIF.
+#define BM_FTFE_FSTAT_CCIF   (0x80U)       //!< Bit mask for FTFE_FSTAT_CCIF.
+#define BS_FTFE_FSTAT_CCIF   (1U)          //!< Bit field size in bits for FTFE_FSTAT_CCIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_CCIF field.
+#define BR_FTFE_FSTAT_CCIF   (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_CCIF.
+#define BF_FTFE_FSTAT_CCIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_CCIF), uint8_t) & BM_FTFE_FSTAT_CCIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCIF field to a new value.
+#define BW_FTFE_FSTAT_CCIF(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCNFG - Flash Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+typedef union _hw_ftfe_fcnfg
+{
+    uint8_t U;
+    struct _hw_ftfe_fcnfg_bitfields
+    {
+        uint8_t EEERDY : 1;            //!< [0]
+        uint8_t RAMRDY : 1;            //!< [1] RAM Ready
+        uint8_t PFLSH : 1;             //!< [2] FTFE configuration
+        uint8_t SWAP : 1;              //!< [3] Swap
+        uint8_t ERSSUSP : 1;           //!< [4] Erase Suspend
+        uint8_t ERSAREQ : 1;           //!< [5] Erase All Request
+        uint8_t RDCOLLIE : 1;          //!< [6] Read Collision Error Interrupt Enable
+        uint8_t CCIE : 1;              //!< [7] Command Complete Interrupt Enable
+    } B;
+} hw_ftfe_fcnfg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+//@{
+#define HW_FTFE_FCNFG_ADDR       (REGS_FTFE_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCNFG            (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR)
+#define HW_FTFE_FCNFG_RD()       (HW_FTFE_FCNFG.U)
+#define HW_FTFE_FCNFG_WR(v)      (HW_FTFE_FCNFG.U = (v))
+#define HW_FTFE_FCNFG_SET(v)     (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() |  (v)))
+#define HW_FTFE_FCNFG_CLR(v)     (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() & ~(v)))
+#define HW_FTFE_FCNFG_TOG(v)     (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
+ * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the FlexRAM
+ *     in EEPROM mode and writes launch an EEPROM operation to store the written
+ *     data in the FlexRAM and EEPROM backup.
+ */
+//@{
+#define BP_FTFE_FCNFG_EEERDY (0U)          //!< Bit position for FTFE_FCNFG_EEERDY.
+#define BM_FTFE_FCNFG_EEERDY (0x01U)       //!< Bit mask for FTFE_FCNFG_EEERDY.
+#define BS_FTFE_FCNFG_EEERDY (1U)          //!< Bit field size in bits for FTFE_FCNFG_EEERDY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_EEERDY field.
+#define BR_FTFE_FCNFG_EEERDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_EEERDY))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM
+ *     access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only;
+ *     writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+//@{
+#define BP_FTFE_FCNFG_RAMRDY (1U)          //!< Bit position for FTFE_FCNFG_RAMRDY.
+#define BM_FTFE_FCNFG_RAMRDY (0x02U)       //!< Bit mask for FTFE_FCNFG_RAMRDY.
+#define BS_FTFE_FCNFG_RAMRDY (1U)          //!< Bit field size in bits for FTFE_FCNFG_RAMRDY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_RAMRDY field.
+#define BR_FTFE_FCNFG_RAMRDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RAMRDY))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash
+ *     blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
+ *     FTFE configuration supports four program flash blocks
+ */
+//@{
+#define BP_FTFE_FCNFG_PFLSH  (2U)          //!< Bit position for FTFE_FCNFG_PFLSH.
+#define BM_FTFE_FCNFG_PFLSH  (0x04U)       //!< Bit mask for FTFE_FCNFG_PFLSH.
+#define BS_FTFE_FCNFG_PFLSH  (1U)          //!< Bit field size in bits for FTFE_FCNFG_PFLSH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_PFLSH field.
+#define BR_FTFE_FCNFG_PFLSH  (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_PFLSH))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative
+ *     address 0x0000 For devices with program flash only: Program flash 0 block
+ *     is located at relative address 0x0000
+ * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
+ *     Program flash 1 block is located at relative address 0x0000
+ */
+//@{
+#define BP_FTFE_FCNFG_SWAP   (3U)          //!< Bit position for FTFE_FCNFG_SWAP.
+#define BM_FTFE_FCNFG_SWAP   (0x08U)       //!< Bit mask for FTFE_FCNFG_SWAP.
+#define BS_FTFE_FCNFG_SWAP   (1U)          //!< Bit field size in bits for FTFE_FCNFG_SWAP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_SWAP field.
+#define BR_FTFE_FCNFG_SWAP   (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_SWAP))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0 - No suspend requested
+ * - 1 - Suspend the current Erase Flash Sector command execution.
+ */
+//@{
+#define BP_FTFE_FCNFG_ERSSUSP (4U)         //!< Bit position for FTFE_FCNFG_ERSSUSP.
+#define BM_FTFE_FCNFG_ERSSUSP (0x10U)      //!< Bit mask for FTFE_FCNFG_ERSSUSP.
+#define BS_FTFE_FCNFG_ERSSUSP (1U)         //!< Bit field size in bits for FTFE_FCNFG_ERSSUSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_ERSSUSP field.
+#define BR_FTFE_FCNFG_ERSSUSP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP))
+#endif
+
+//! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP.
+#define BF_FTFE_FCNFG_ERSSUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_ERSSUSP), uint8_t) & BM_FTFE_FCNFG_ERSSUSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERSSUSP field to a new value.
+#define BW_FTFE_FCNFG_ERSSUSP(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0 - No request or request complete
+ * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
+ *     program the security byte in the Flash Configuration Field to the unsecure
+ *     state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+//@{
+#define BP_FTFE_FCNFG_ERSAREQ (5U)         //!< Bit position for FTFE_FCNFG_ERSAREQ.
+#define BM_FTFE_FCNFG_ERSAREQ (0x20U)      //!< Bit mask for FTFE_FCNFG_ERSAREQ.
+#define BS_FTFE_FCNFG_ERSAREQ (1U)         //!< Bit field size in bits for FTFE_FCNFG_ERSAREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_ERSAREQ field.
+#define BR_FTFE_FCNFG_ERSAREQ (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSAREQ))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0 - Read collision error interrupt disabled
+ * - 1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the description
+ *     of FSTAT[RDCOLERR]).
+ */
+//@{
+#define BP_FTFE_FCNFG_RDCOLLIE (6U)        //!< Bit position for FTFE_FCNFG_RDCOLLIE.
+#define BM_FTFE_FCNFG_RDCOLLIE (0x40U)     //!< Bit mask for FTFE_FCNFG_RDCOLLIE.
+#define BS_FTFE_FCNFG_RDCOLLIE (1U)        //!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field.
+#define BR_FTFE_FCNFG_RDCOLLIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE))
+#endif
+
+//! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE.
+#define BF_FTFE_FCNFG_RDCOLLIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_RDCOLLIE), uint8_t) & BM_FTFE_FCNFG_RDCOLLIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDCOLLIE field to a new value.
+#define BW_FTFE_FCNFG_RDCOLLIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0 - Command complete interrupt disabled
+ * - 1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+//@{
+#define BP_FTFE_FCNFG_CCIE   (7U)          //!< Bit position for FTFE_FCNFG_CCIE.
+#define BM_FTFE_FCNFG_CCIE   (0x80U)       //!< Bit mask for FTFE_FCNFG_CCIE.
+#define BS_FTFE_FCNFG_CCIE   (1U)          //!< Bit field size in bits for FTFE_FCNFG_CCIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_CCIE field.
+#define BR_FTFE_FCNFG_CCIE   (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE))
+#endif
+
+//! @brief Format value for bitfield FTFE_FCNFG_CCIE.
+#define BF_FTFE_FCNFG_CCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_CCIE), uint8_t) & BM_FTFE_FCNFG_CCIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCIE field to a new value.
+#define BW_FTFE_FCNFG_CCIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FSEC - Flash Security Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+typedef union _hw_ftfe_fsec
+{
+    uint8_t U;
+    struct _hw_ftfe_fsec_bitfields
+    {
+        uint8_t SEC : 2;               //!< [1:0] Flash Security
+        uint8_t FSLACC : 2;            //!< [3:2] Freescale Failure Analysis Access Code
+        uint8_t MEEN : 2;              //!< [5:4] Mass Erase Enable Bits
+        uint8_t KEYEN : 2;             //!< [7:6] Backdoor Key Security Enable
+    } B;
+} hw_ftfe_fsec_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+//@{
+#define HW_FTFE_FSEC_ADDR        (REGS_FTFE_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FSEC             (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR)
+#define HW_FTFE_FSEC_RD()        (HW_FTFE_FSEC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 00 - MCU security status is secure
+ * - 01 - MCU security status is secure
+ * - 10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 11 - MCU security status is secure
+ */
+//@{
+#define BP_FTFE_FSEC_SEC     (0U)          //!< Bit position for FTFE_FSEC_SEC.
+#define BM_FTFE_FSEC_SEC     (0x03U)       //!< Bit mask for FTFE_FSEC_SEC.
+#define BS_FTFE_FSEC_SEC     (2U)          //!< Bit field size in bits for FTFE_FSEC_SEC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_SEC field.
+#define BR_FTFE_FSEC_SEC     (HW_FTFE_FSEC.B.SEC)
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 00 - Freescale factory access granted
+ * - 01 - Freescale factory access denied
+ * - 10 - Freescale factory access denied
+ * - 11 - Freescale factory access granted
+ */
+//@{
+#define BP_FTFE_FSEC_FSLACC  (2U)          //!< Bit position for FTFE_FSEC_FSLACC.
+#define BM_FTFE_FSEC_FSLACC  (0x0CU)       //!< Bit mask for FTFE_FSEC_FSLACC.
+#define BS_FTFE_FSEC_FSLACC  (2U)          //!< Bit field size in bits for FTFE_FSEC_FSLACC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_FSLACC field.
+#define BR_FTFE_FSEC_FSLACC  (HW_FTFE_FSEC.B.FSLACC)
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 00 - Mass erase is enabled
+ * - 01 - Mass erase is enabled
+ * - 10 - Mass erase is disabled
+ * - 11 - Mass erase is enabled
+ */
+//@{
+#define BP_FTFE_FSEC_MEEN    (4U)          //!< Bit position for FTFE_FSEC_MEEN.
+#define BM_FTFE_FSEC_MEEN    (0x30U)       //!< Bit mask for FTFE_FSEC_MEEN.
+#define BS_FTFE_FSEC_MEEN    (2U)          //!< Bit field size in bits for FTFE_FSEC_MEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_MEEN field.
+#define BR_FTFE_FSEC_MEEN    (HW_FTFE_FSEC.B.MEEN)
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 00 - Backdoor key access disabled
+ * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 10 - Backdoor key access enabled
+ * - 11 - Backdoor key access disabled
+ */
+//@{
+#define BP_FTFE_FSEC_KEYEN   (6U)          //!< Bit position for FTFE_FSEC_KEYEN.
+#define BM_FTFE_FSEC_KEYEN   (0xC0U)       //!< Bit mask for FTFE_FSEC_KEYEN.
+#define BS_FTFE_FSEC_KEYEN   (2U)          //!< Bit field size in bits for FTFE_FSEC_KEYEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_KEYEN field.
+#define BR_FTFE_FSEC_KEYEN   (HW_FTFE_FSEC.B.KEYEN)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FOPT - Flash Option Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+typedef union _hw_ftfe_fopt
+{
+    uint8_t U;
+    struct _hw_ftfe_fopt_bitfields
+    {
+        uint8_t OPT : 8;               //!< [7:0] Nonvolatile Option
+    } B;
+} hw_ftfe_fopt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+//@{
+#define HW_FTFE_FOPT_ADDR        (REGS_FTFE_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FOPT             (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR)
+#define HW_FTFE_FOPT_RD()        (HW_FTFE_FOPT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FOPT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FOPT, field OPT[7:0] (RO)
+ *
+ * These bits are loaded from flash to this register at reset. Refer to the
+ * device's Chip Configuration details for the definition and use of these bits.
+ */
+//@{
+#define BP_FTFE_FOPT_OPT     (0U)          //!< Bit position for FTFE_FOPT_OPT.
+#define BM_FTFE_FOPT_OPT     (0xFFU)       //!< Bit mask for FTFE_FOPT_OPT.
+#define BS_FTFE_FOPT_OPT     (8U)          //!< Bit field size in bits for FTFE_FOPT_OPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FOPT_OPT field.
+#define BR_FTFE_FOPT_OPT     (HW_FTFE_FOPT.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB3 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob3
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob3_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+//@{
+#define HW_FTFE_FCCOB3_ADDR      (REGS_FTFE_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB3           (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR)
+#define HW_FTFE_FCCOB3_RD()      (HW_FTFE_FCCOB3.U)
+#define HW_FTFE_FCCOB3_WR(v)     (HW_FTFE_FCCOB3.U = (v))
+#define HW_FTFE_FCCOB3_SET(v)    (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() |  (v)))
+#define HW_FTFE_FCCOB3_CLR(v)    (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() & ~(v)))
+#define HW_FTFE_FCCOB3_TOG(v)    (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB3 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB3_CCOBn (0U)          //!< Bit position for FTFE_FCCOB3_CCOBn.
+#define BM_FTFE_FCCOB3_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB3_CCOBn.
+#define BS_FTFE_FCCOB3_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB3_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB3_CCOBn field.
+#define BR_FTFE_FCCOB3_CCOBn (HW_FTFE_FCCOB3.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB3_CCOBn.
+#define BF_FTFE_FCCOB3_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB3_CCOBn), uint8_t) & BM_FTFE_FCCOB3_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB3_CCOBn(v) (HW_FTFE_FCCOB3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB2 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob2
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob2_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+//@{
+#define HW_FTFE_FCCOB2_ADDR      (REGS_FTFE_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB2           (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR)
+#define HW_FTFE_FCCOB2_RD()      (HW_FTFE_FCCOB2.U)
+#define HW_FTFE_FCCOB2_WR(v)     (HW_FTFE_FCCOB2.U = (v))
+#define HW_FTFE_FCCOB2_SET(v)    (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() |  (v)))
+#define HW_FTFE_FCCOB2_CLR(v)    (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() & ~(v)))
+#define HW_FTFE_FCCOB2_TOG(v)    (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB2 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB2_CCOBn (0U)          //!< Bit position for FTFE_FCCOB2_CCOBn.
+#define BM_FTFE_FCCOB2_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB2_CCOBn.
+#define BS_FTFE_FCCOB2_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB2_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB2_CCOBn field.
+#define BR_FTFE_FCCOB2_CCOBn (HW_FTFE_FCCOB2.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB2_CCOBn.
+#define BF_FTFE_FCCOB2_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB2_CCOBn), uint8_t) & BM_FTFE_FCCOB2_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB2_CCOBn(v) (HW_FTFE_FCCOB2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB1 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob1
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob1_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+//@{
+#define HW_FTFE_FCCOB1_ADDR      (REGS_FTFE_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB1           (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR)
+#define HW_FTFE_FCCOB1_RD()      (HW_FTFE_FCCOB1.U)
+#define HW_FTFE_FCCOB1_WR(v)     (HW_FTFE_FCCOB1.U = (v))
+#define HW_FTFE_FCCOB1_SET(v)    (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() |  (v)))
+#define HW_FTFE_FCCOB1_CLR(v)    (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() & ~(v)))
+#define HW_FTFE_FCCOB1_TOG(v)    (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB1 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB1_CCOBn (0U)          //!< Bit position for FTFE_FCCOB1_CCOBn.
+#define BM_FTFE_FCCOB1_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB1_CCOBn.
+#define BS_FTFE_FCCOB1_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB1_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB1_CCOBn field.
+#define BR_FTFE_FCCOB1_CCOBn (HW_FTFE_FCCOB1.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB1_CCOBn.
+#define BF_FTFE_FCCOB1_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB1_CCOBn), uint8_t) & BM_FTFE_FCCOB1_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB1_CCOBn(v) (HW_FTFE_FCCOB1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB0 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob0
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob0_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+//@{
+#define HW_FTFE_FCCOB0_ADDR      (REGS_FTFE_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB0           (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR)
+#define HW_FTFE_FCCOB0_RD()      (HW_FTFE_FCCOB0.U)
+#define HW_FTFE_FCCOB0_WR(v)     (HW_FTFE_FCCOB0.U = (v))
+#define HW_FTFE_FCCOB0_SET(v)    (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() |  (v)))
+#define HW_FTFE_FCCOB0_CLR(v)    (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() & ~(v)))
+#define HW_FTFE_FCCOB0_TOG(v)    (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB0 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB0_CCOBn (0U)          //!< Bit position for FTFE_FCCOB0_CCOBn.
+#define BM_FTFE_FCCOB0_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB0_CCOBn.
+#define BS_FTFE_FCCOB0_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB0_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB0_CCOBn field.
+#define BR_FTFE_FCCOB0_CCOBn (HW_FTFE_FCCOB0.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB0_CCOBn.
+#define BF_FTFE_FCCOB0_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB0_CCOBn), uint8_t) & BM_FTFE_FCCOB0_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB0_CCOBn(v) (HW_FTFE_FCCOB0_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB7 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob7
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob7_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+//@{
+#define HW_FTFE_FCCOB7_ADDR      (REGS_FTFE_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB7           (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR)
+#define HW_FTFE_FCCOB7_RD()      (HW_FTFE_FCCOB7.U)
+#define HW_FTFE_FCCOB7_WR(v)     (HW_FTFE_FCCOB7.U = (v))
+#define HW_FTFE_FCCOB7_SET(v)    (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() |  (v)))
+#define HW_FTFE_FCCOB7_CLR(v)    (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() & ~(v)))
+#define HW_FTFE_FCCOB7_TOG(v)    (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB7 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB7_CCOBn (0U)          //!< Bit position for FTFE_FCCOB7_CCOBn.
+#define BM_FTFE_FCCOB7_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB7_CCOBn.
+#define BS_FTFE_FCCOB7_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB7_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB7_CCOBn field.
+#define BR_FTFE_FCCOB7_CCOBn (HW_FTFE_FCCOB7.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB7_CCOBn.
+#define BF_FTFE_FCCOB7_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB7_CCOBn), uint8_t) & BM_FTFE_FCCOB7_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB7_CCOBn(v) (HW_FTFE_FCCOB7_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB6 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob6
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob6_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+//@{
+#define HW_FTFE_FCCOB6_ADDR      (REGS_FTFE_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB6           (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR)
+#define HW_FTFE_FCCOB6_RD()      (HW_FTFE_FCCOB6.U)
+#define HW_FTFE_FCCOB6_WR(v)     (HW_FTFE_FCCOB6.U = (v))
+#define HW_FTFE_FCCOB6_SET(v)    (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() |  (v)))
+#define HW_FTFE_FCCOB6_CLR(v)    (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() & ~(v)))
+#define HW_FTFE_FCCOB6_TOG(v)    (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB6 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB6_CCOBn (0U)          //!< Bit position for FTFE_FCCOB6_CCOBn.
+#define BM_FTFE_FCCOB6_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB6_CCOBn.
+#define BS_FTFE_FCCOB6_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB6_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB6_CCOBn field.
+#define BR_FTFE_FCCOB6_CCOBn (HW_FTFE_FCCOB6.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB6_CCOBn.
+#define BF_FTFE_FCCOB6_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB6_CCOBn), uint8_t) & BM_FTFE_FCCOB6_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB6_CCOBn(v) (HW_FTFE_FCCOB6_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB5 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob5
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob5_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+//@{
+#define HW_FTFE_FCCOB5_ADDR      (REGS_FTFE_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB5           (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR)
+#define HW_FTFE_FCCOB5_RD()      (HW_FTFE_FCCOB5.U)
+#define HW_FTFE_FCCOB5_WR(v)     (HW_FTFE_FCCOB5.U = (v))
+#define HW_FTFE_FCCOB5_SET(v)    (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() |  (v)))
+#define HW_FTFE_FCCOB5_CLR(v)    (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() & ~(v)))
+#define HW_FTFE_FCCOB5_TOG(v)    (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB5 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB5_CCOBn (0U)          //!< Bit position for FTFE_FCCOB5_CCOBn.
+#define BM_FTFE_FCCOB5_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB5_CCOBn.
+#define BS_FTFE_FCCOB5_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB5_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB5_CCOBn field.
+#define BR_FTFE_FCCOB5_CCOBn (HW_FTFE_FCCOB5.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB5_CCOBn.
+#define BF_FTFE_FCCOB5_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB5_CCOBn), uint8_t) & BM_FTFE_FCCOB5_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB5_CCOBn(v) (HW_FTFE_FCCOB5_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB4 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob4
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob4_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+//@{
+#define HW_FTFE_FCCOB4_ADDR      (REGS_FTFE_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB4           (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR)
+#define HW_FTFE_FCCOB4_RD()      (HW_FTFE_FCCOB4.U)
+#define HW_FTFE_FCCOB4_WR(v)     (HW_FTFE_FCCOB4.U = (v))
+#define HW_FTFE_FCCOB4_SET(v)    (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() |  (v)))
+#define HW_FTFE_FCCOB4_CLR(v)    (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() & ~(v)))
+#define HW_FTFE_FCCOB4_TOG(v)    (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB4 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB4_CCOBn (0U)          //!< Bit position for FTFE_FCCOB4_CCOBn.
+#define BM_FTFE_FCCOB4_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB4_CCOBn.
+#define BS_FTFE_FCCOB4_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB4_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB4_CCOBn field.
+#define BR_FTFE_FCCOB4_CCOBn (HW_FTFE_FCCOB4.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB4_CCOBn.
+#define BF_FTFE_FCCOB4_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB4_CCOBn), uint8_t) & BM_FTFE_FCCOB4_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB4_CCOBn(v) (HW_FTFE_FCCOB4_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOBB - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccobb
+{
+    uint8_t U;
+    struct _hw_ftfe_fccobb_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccobb_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+//@{
+#define HW_FTFE_FCCOBB_ADDR      (REGS_FTFE_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOBB           (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR)
+#define HW_FTFE_FCCOBB_RD()      (HW_FTFE_FCCOBB.U)
+#define HW_FTFE_FCCOBB_WR(v)     (HW_FTFE_FCCOBB.U = (v))
+#define HW_FTFE_FCCOBB_SET(v)    (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() |  (v)))
+#define HW_FTFE_FCCOBB_CLR(v)    (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() & ~(v)))
+#define HW_FTFE_FCCOBB_TOG(v)    (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOBB bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOBB_CCOBn (0U)          //!< Bit position for FTFE_FCCOBB_CCOBn.
+#define BM_FTFE_FCCOBB_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOBB_CCOBn.
+#define BS_FTFE_FCCOBB_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOBB_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOBB_CCOBn field.
+#define BR_FTFE_FCCOBB_CCOBn (HW_FTFE_FCCOBB.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOBB_CCOBn.
+#define BF_FTFE_FCCOBB_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBB_CCOBn), uint8_t) & BM_FTFE_FCCOBB_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOBB_CCOBn(v) (HW_FTFE_FCCOBB_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOBA - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccoba
+{
+    uint8_t U;
+    struct _hw_ftfe_fccoba_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccoba_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+//@{
+#define HW_FTFE_FCCOBA_ADDR      (REGS_FTFE_BASE + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOBA           (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR)
+#define HW_FTFE_FCCOBA_RD()      (HW_FTFE_FCCOBA.U)
+#define HW_FTFE_FCCOBA_WR(v)     (HW_FTFE_FCCOBA.U = (v))
+#define HW_FTFE_FCCOBA_SET(v)    (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() |  (v)))
+#define HW_FTFE_FCCOBA_CLR(v)    (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() & ~(v)))
+#define HW_FTFE_FCCOBA_TOG(v)    (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOBA bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOBA_CCOBn (0U)          //!< Bit position for FTFE_FCCOBA_CCOBn.
+#define BM_FTFE_FCCOBA_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOBA_CCOBn.
+#define BS_FTFE_FCCOBA_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOBA_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOBA_CCOBn field.
+#define BR_FTFE_FCCOBA_CCOBn (HW_FTFE_FCCOBA.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOBA_CCOBn.
+#define BF_FTFE_FCCOBA_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBA_CCOBn), uint8_t) & BM_FTFE_FCCOBA_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOBA_CCOBn(v) (HW_FTFE_FCCOBA_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB9 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob9
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob9_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob9_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+//@{
+#define HW_FTFE_FCCOB9_ADDR      (REGS_FTFE_BASE + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB9           (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR)
+#define HW_FTFE_FCCOB9_RD()      (HW_FTFE_FCCOB9.U)
+#define HW_FTFE_FCCOB9_WR(v)     (HW_FTFE_FCCOB9.U = (v))
+#define HW_FTFE_FCCOB9_SET(v)    (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() |  (v)))
+#define HW_FTFE_FCCOB9_CLR(v)    (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() & ~(v)))
+#define HW_FTFE_FCCOB9_TOG(v)    (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB9 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB9_CCOBn (0U)          //!< Bit position for FTFE_FCCOB9_CCOBn.
+#define BM_FTFE_FCCOB9_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB9_CCOBn.
+#define BS_FTFE_FCCOB9_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB9_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB9_CCOBn field.
+#define BR_FTFE_FCCOB9_CCOBn (HW_FTFE_FCCOB9.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB9_CCOBn.
+#define BF_FTFE_FCCOB9_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB9_CCOBn), uint8_t) & BM_FTFE_FCCOB9_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB9_CCOBn(v) (HW_FTFE_FCCOB9_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB8 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob8
+{
+    uint8_t U;
+    struct _hw_ftfe_fccob8_bitfields
+    {
+        uint8_t CCOBn : 8;             //!< [7:0]
+    } B;
+} hw_ftfe_fccob8_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+//@{
+#define HW_FTFE_FCCOB8_ADDR      (REGS_FTFE_BASE + 0xFU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB8           (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR)
+#define HW_FTFE_FCCOB8_RD()      (HW_FTFE_FCCOB8.U)
+#define HW_FTFE_FCCOB8_WR(v)     (HW_FTFE_FCCOB8.U = (v))
+#define HW_FTFE_FCCOB8_SET(v)    (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() |  (v)))
+#define HW_FTFE_FCCOB8_CLR(v)    (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() & ~(v)))
+#define HW_FTFE_FCCOB8_TOG(v)    (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB8 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB8_CCOBn (0U)          //!< Bit position for FTFE_FCCOB8_CCOBn.
+#define BM_FTFE_FCCOB8_CCOBn (0xFFU)       //!< Bit mask for FTFE_FCCOB8_CCOBn.
+#define BS_FTFE_FCCOB8_CCOBn (8U)          //!< Bit field size in bits for FTFE_FCCOB8_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB8_CCOBn field.
+#define BR_FTFE_FCCOB8_CCOBn (HW_FTFE_FCCOB8.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB8_CCOBn.
+#define BF_FTFE_FCCOB8_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB8_CCOBn), uint8_t) & BM_FTFE_FCCOB8_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB8_CCOBn(v) (HW_FTFE_FCCOB8_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT3 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot3
+{
+    uint8_t U;
+    struct _hw_ftfe_fprot3_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] Program Flash Region Protect
+    } B;
+} hw_ftfe_fprot3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+//@{
+#define HW_FTFE_FPROT3_ADDR      (REGS_FTFE_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT3           (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR)
+#define HW_FTFE_FPROT3_RD()      (HW_FTFE_FPROT3.U)
+#define HW_FTFE_FPROT3_WR(v)     (HW_FTFE_FPROT3.U = (v))
+#define HW_FTFE_FPROT3_SET(v)    (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() |  (v)))
+#define HW_FTFE_FPROT3_CLR(v)    (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() & ~(v)))
+#define HW_FTFE_FPROT3_TOG(v)    (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT3 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT3, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT3_PROT  (0U)          //!< Bit position for FTFE_FPROT3_PROT.
+#define BM_FTFE_FPROT3_PROT  (0xFFU)       //!< Bit mask for FTFE_FPROT3_PROT.
+#define BS_FTFE_FPROT3_PROT  (8U)          //!< Bit field size in bits for FTFE_FPROT3_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT3_PROT field.
+#define BR_FTFE_FPROT3_PROT  (HW_FTFE_FPROT3.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT3_PROT.
+#define BF_FTFE_FPROT3_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT3_PROT), uint8_t) & BM_FTFE_FPROT3_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT3_PROT(v) (HW_FTFE_FPROT3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT2 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot2
+{
+    uint8_t U;
+    struct _hw_ftfe_fprot2_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] Program Flash Region Protect
+    } B;
+} hw_ftfe_fprot2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+//@{
+#define HW_FTFE_FPROT2_ADDR      (REGS_FTFE_BASE + 0x11U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT2           (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR)
+#define HW_FTFE_FPROT2_RD()      (HW_FTFE_FPROT2.U)
+#define HW_FTFE_FPROT2_WR(v)     (HW_FTFE_FPROT2.U = (v))
+#define HW_FTFE_FPROT2_SET(v)    (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() |  (v)))
+#define HW_FTFE_FPROT2_CLR(v)    (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() & ~(v)))
+#define HW_FTFE_FPROT2_TOG(v)    (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT2 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT2, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT2_PROT  (0U)          //!< Bit position for FTFE_FPROT2_PROT.
+#define BM_FTFE_FPROT2_PROT  (0xFFU)       //!< Bit mask for FTFE_FPROT2_PROT.
+#define BS_FTFE_FPROT2_PROT  (8U)          //!< Bit field size in bits for FTFE_FPROT2_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT2_PROT field.
+#define BR_FTFE_FPROT2_PROT  (HW_FTFE_FPROT2.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT2_PROT.
+#define BF_FTFE_FPROT2_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT2_PROT), uint8_t) & BM_FTFE_FPROT2_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT2_PROT(v) (HW_FTFE_FPROT2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT1 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot1
+{
+    uint8_t U;
+    struct _hw_ftfe_fprot1_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] Program Flash Region Protect
+    } B;
+} hw_ftfe_fprot1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+//@{
+#define HW_FTFE_FPROT1_ADDR      (REGS_FTFE_BASE + 0x12U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT1           (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR)
+#define HW_FTFE_FPROT1_RD()      (HW_FTFE_FPROT1.U)
+#define HW_FTFE_FPROT1_WR(v)     (HW_FTFE_FPROT1.U = (v))
+#define HW_FTFE_FPROT1_SET(v)    (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() |  (v)))
+#define HW_FTFE_FPROT1_CLR(v)    (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() & ~(v)))
+#define HW_FTFE_FPROT1_TOG(v)    (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT1 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT1, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT1_PROT  (0U)          //!< Bit position for FTFE_FPROT1_PROT.
+#define BM_FTFE_FPROT1_PROT  (0xFFU)       //!< Bit mask for FTFE_FPROT1_PROT.
+#define BS_FTFE_FPROT1_PROT  (8U)          //!< Bit field size in bits for FTFE_FPROT1_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT1_PROT field.
+#define BR_FTFE_FPROT1_PROT  (HW_FTFE_FPROT1.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT1_PROT.
+#define BF_FTFE_FPROT1_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT1_PROT), uint8_t) & BM_FTFE_FPROT1_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT1_PROT(v) (HW_FTFE_FPROT1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT0 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot0
+{
+    uint8_t U;
+    struct _hw_ftfe_fprot0_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] Program Flash Region Protect
+    } B;
+} hw_ftfe_fprot0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+//@{
+#define HW_FTFE_FPROT0_ADDR      (REGS_FTFE_BASE + 0x13U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT0           (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR)
+#define HW_FTFE_FPROT0_RD()      (HW_FTFE_FPROT0.U)
+#define HW_FTFE_FPROT0_WR(v)     (HW_FTFE_FPROT0.U = (v))
+#define HW_FTFE_FPROT0_SET(v)    (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() |  (v)))
+#define HW_FTFE_FPROT0_CLR(v)    (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() & ~(v)))
+#define HW_FTFE_FPROT0_TOG(v)    (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT0 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT0, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT0_PROT  (0U)          //!< Bit position for FTFE_FPROT0_PROT.
+#define BM_FTFE_FPROT0_PROT  (0xFFU)       //!< Bit mask for FTFE_FPROT0_PROT.
+#define BS_FTFE_FPROT0_PROT  (8U)          //!< Bit field size in bits for FTFE_FPROT0_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT0_PROT field.
+#define BR_FTFE_FPROT0_PROT  (HW_FTFE_FPROT0.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT0_PROT.
+#define BF_FTFE_FPROT0_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT0_PROT), uint8_t) & BM_FTFE_FPROT0_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT0_PROT(v) (HW_FTFE_FPROT0_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FEPROT - EEPROM Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+typedef union _hw_ftfe_feprot
+{
+    uint8_t U;
+    struct _hw_ftfe_feprot_bitfields
+    {
+        uint8_t EPROT : 8;             //!< [7:0] EEPROM Region Protect
+    } B;
+} hw_ftfe_feprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+//@{
+#define HW_FTFE_FEPROT_ADDR      (REGS_FTFE_BASE + 0x16U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FEPROT           (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR)
+#define HW_FTFE_FEPROT_RD()      (HW_FTFE_FEPROT.U)
+#define HW_FTFE_FEPROT_WR(v)     (HW_FTFE_FEPROT.U = (v))
+#define HW_FTFE_FEPROT_SET(v)    (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() |  (v)))
+#define HW_FTFE_FEPROT_CLR(v)    (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() & ~(v)))
+#define HW_FTFE_FEPROT_TOG(v)    (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FEPROT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FEPROT, field EPROT[7:0] (RW)
+ *
+ * For devices with program flash only: Reserved For devices with FlexNVM:
+ * Individual EEPROM regions can be protected from alteration by setting the
+ * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is
+ * set to data flash only. When the FlexNVM Partition Code is set to data flash and
+ * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured
+ * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal
+ * mode: The protection can only be increased. This means that
+ * currently-unprotected memory can be protected, but currently-protected memory cannot be
+ * unprotected. Since unprotected regions are marked with a 1 and protected regions use a
+ * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is
+ * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions
+ * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special
+ * mode: All bits of the FEPROT register are writable without restriction.
+ * Unprotected areas can be protected and protected areas can be unprotected. Never
+ * write to the FEPROT register while a command is running (CCIF=0). Reset: During
+ * the reset sequence, the FEPROT register is loaded with the contents of the
+ * FlexRAM protection byte in the Flash Configuration Field located in program flash.
+ * The flash basis for the reset values is signified by X in the register
+ * diagram. To change the EEPROM protection that will be loaded during the reset
+ * sequence, the sector of program flash that contains the Flash Configuration Field
+ * must be unprotected; then the EEPROM protection byte must be erased and
+ * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM
+ * results in a protection violation error and sets the FSTAT[FPVIOL] bit.
+ *
+ * Values:
+ * - 0 - For devices with program flash only: Reserved For devices with FlexNVM:
+ *     EEPROM region is protected
+ * - 1 - For devices with program flash only: Reserved For devices with FlexNVM:
+ *     EEPROM region is not protected
+ */
+//@{
+#define BP_FTFE_FEPROT_EPROT (0U)          //!< Bit position for FTFE_FEPROT_EPROT.
+#define BM_FTFE_FEPROT_EPROT (0xFFU)       //!< Bit mask for FTFE_FEPROT_EPROT.
+#define BS_FTFE_FEPROT_EPROT (8U)          //!< Bit field size in bits for FTFE_FEPROT_EPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FEPROT_EPROT field.
+#define BR_FTFE_FEPROT_EPROT (HW_FTFE_FEPROT.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FEPROT_EPROT.
+#define BF_FTFE_FEPROT_EPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FEPROT_EPROT), uint8_t) & BM_FTFE_FEPROT_EPROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPROT field to a new value.
+#define BW_FTFE_FEPROT_EPROT(v) (HW_FTFE_FEPROT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FDPROT - Data Flash Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+typedef union _hw_ftfe_fdprot
+{
+    uint8_t U;
+    struct _hw_ftfe_fdprot_bitfields
+    {
+        uint8_t DPROT : 8;             //!< [7:0] Data Flash Region Protect
+    } B;
+} hw_ftfe_fdprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+//@{
+#define HW_FTFE_FDPROT_ADDR      (REGS_FTFE_BASE + 0x17U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FDPROT           (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR)
+#define HW_FTFE_FDPROT_RD()      (HW_FTFE_FDPROT.U)
+#define HW_FTFE_FDPROT_WR(v)     (HW_FTFE_FDPROT.U = (v))
+#define HW_FTFE_FDPROT_SET(v)    (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() |  (v)))
+#define HW_FTFE_FDPROT_CLR(v)    (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() & ~(v)))
+#define HW_FTFE_FDPROT_TOG(v)    (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FDPROT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FDPROT, field DPROT[7:0] (RW)
+ *
+ * Individual data flash regions can be protected from program and erase
+ * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of
+ * the partitioned data flash memory space. The granularity of data flash
+ * protection cannot be less than the data flash sector size. If an unused DPROT bit is
+ * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL]
+ * bit. In NVM Normal mode: The protection can only be increased, meaning that
+ * currently unprotected memory can be protected but currently protected memory
+ * cannot be unprotected. Since unprotected regions are marked with a 1 and
+ * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0
+ * transition check is performed on a bit-by-bit basis. Those FDPROT bits with
+ * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are
+ * ignored. In NVM Special mode: All bits of the FDPROT register are writable without
+ * restriction. Unprotected areas can be protected and protected areas can be
+ * unprotected. The user must never write to the FDPROT register while a command is
+ * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is
+ * loaded with the contents of the data flash protection byte in the Flash
+ * Configuration Field located in program flash memory. The flash basis for the reset values
+ * is signified by X in the register diagram. To change the data flash
+ * protection that will be loaded during the reset sequence, unprotect the sector of
+ * program flash that contains the Flash Configuration Field. Then, erase and
+ * reprogram the data flash protection byte. Trying to alter data with the program and
+ * erase commands in any protected area in the data flash memory results in a
+ * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any
+ * data flash memory block (see the Erase Flash Block command description) is not
+ * possible if the data flash block contains any protected region or if the FlexNVM
+ * memory has been partitioned for EEPROM.
+ *
+ * Values:
+ * - 0 - Data Flash region is protected
+ * - 1 - Data Flash region is not protected
+ */
+//@{
+#define BP_FTFE_FDPROT_DPROT (0U)          //!< Bit position for FTFE_FDPROT_DPROT.
+#define BM_FTFE_FDPROT_DPROT (0xFFU)       //!< Bit mask for FTFE_FDPROT_DPROT.
+#define BS_FTFE_FDPROT_DPROT (8U)          //!< Bit field size in bits for FTFE_FDPROT_DPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FDPROT_DPROT field.
+#define BR_FTFE_FDPROT_DPROT (HW_FTFE_FDPROT.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FDPROT_DPROT.
+#define BF_FTFE_FDPROT_DPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FDPROT_DPROT), uint8_t) & BM_FTFE_FDPROT_DPROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPROT field to a new value.
+#define BW_FTFE_FDPROT_DPROT(v) (HW_FTFE_FDPROT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_ftfe_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FTFE module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_ftfe
+{
+    __IO hw_ftfe_fstat_t FSTAT;            //!< [0x0] Flash Status Register
+    __IO hw_ftfe_fcnfg_t FCNFG;            //!< [0x1] Flash Configuration Register
+    __I hw_ftfe_fsec_t FSEC;               //!< [0x2] Flash Security Register
+    __I hw_ftfe_fopt_t FOPT;               //!< [0x3] Flash Option Register
+    __IO hw_ftfe_fccob3_t FCCOB3;          //!< [0x4] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob2_t FCCOB2;          //!< [0x5] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob1_t FCCOB1;          //!< [0x6] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob0_t FCCOB0;          //!< [0x7] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob7_t FCCOB7;          //!< [0x8] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob6_t FCCOB6;          //!< [0x9] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob5_t FCCOB5;          //!< [0xA] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob4_t FCCOB4;          //!< [0xB] Flash Common Command Object Registers
+    __IO hw_ftfe_fccobb_t FCCOBB;          //!< [0xC] Flash Common Command Object Registers
+    __IO hw_ftfe_fccoba_t FCCOBA;          //!< [0xD] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob9_t FCCOB9;          //!< [0xE] Flash Common Command Object Registers
+    __IO hw_ftfe_fccob8_t FCCOB8;          //!< [0xF] Flash Common Command Object Registers
+    __IO hw_ftfe_fprot3_t FPROT3;          //!< [0x10] Program Flash Protection Registers
+    __IO hw_ftfe_fprot2_t FPROT2;          //!< [0x11] Program Flash Protection Registers
+    __IO hw_ftfe_fprot1_t FPROT1;          //!< [0x12] Program Flash Protection Registers
+    __IO hw_ftfe_fprot0_t FPROT0;          //!< [0x13] Program Flash Protection Registers
+    uint8_t _reserved0[2];
+    __IO hw_ftfe_feprot_t FEPROT;          //!< [0x16] EEPROM Protection Register
+    __IO hw_ftfe_fdprot_t FDPROT;          //!< [0x17] Data Flash Protection Register
+} hw_ftfe_t;
+#pragma pack()
+
+//! @brief Macro to access all FTFE registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_FTFE</code>.
+#define HW_FTFE        (*(hw_ftfe_t *) REGS_FTFE_BASE)
+#endif
+
+#endif // __HW_FTFE_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h
new file mode 100644
index 0000000000..5dc690bf5b
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h
@@ -0,0 +1,6616 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FTM_REGISTERS_H__
+#define __HW_FTM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - HW_FTM_SC - Status And Control
+ * - HW_FTM_CNT - Counter
+ * - HW_FTM_MOD - Modulo
+ * - HW_FTM_CnSC - Channel (n) Status And Control
+ * - HW_FTM_CnV - Channel (n) Value
+ * - HW_FTM_CNTIN - Counter Initial Value
+ * - HW_FTM_STATUS - Capture And Compare Status
+ * - HW_FTM_MODE - Features Mode Selection
+ * - HW_FTM_SYNC - Synchronization
+ * - HW_FTM_OUTINIT - Initial State For Channels Output
+ * - HW_FTM_OUTMASK - Output Mask
+ * - HW_FTM_COMBINE - Function For Linked Channels
+ * - HW_FTM_DEADTIME - Deadtime Insertion Control
+ * - HW_FTM_EXTTRIG - FTM External Trigger
+ * - HW_FTM_POL - Channels Polarity
+ * - HW_FTM_FMS - Fault Mode Status
+ * - HW_FTM_FILTER - Input Capture Filter Control
+ * - HW_FTM_FLTCTRL - Fault Control
+ * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - HW_FTM_CONF - Configuration
+ * - HW_FTM_FLTPOL - FTM Fault Input Polarity
+ * - HW_FTM_SYNCONF - Synchronization Configuration
+ * - HW_FTM_INVCTRL - FTM Inverting Control
+ * - HW_FTM_SWOCTRL - FTM Software Output Control
+ * - HW_FTM_PWMLOAD - FTM PWM Load
+ *
+ * - hw_ftm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FTM_BASE
+#define HW_FTM_INSTANCE_COUNT (4U) //!< Number of instances of the FTM module.
+#define HW_FTM0 (0U) //!< Instance number for FTM0.
+#define HW_FTM1 (1U) //!< Instance number for FTM1.
+#define HW_FTM2 (2U) //!< Instance number for FTM2.
+#define HW_FTM3 (3U) //!< Instance number for FTM3.
+#define REGS_FTM0_BASE (0x40038000U) //!< Base address for FTM0.
+#define REGS_FTM1_BASE (0x40039000U) //!< Base address for FTM1.
+#define REGS_FTM2_BASE (0x4003A000U) //!< Base address for FTM2.
+#define REGS_FTM3_BASE (0x400B9000U) //!< Base address for FTM3.
+
+//! @brief Table of base addresses for FTM instances.
+static const uint32_t __g_regs_FTM_base_addresses[] = {
+        REGS_FTM0_BASE,
+        REGS_FTM1_BASE,
+        REGS_FTM2_BASE,
+        REGS_FTM3_BASE,
+    };
+
+//! @brief Get the base address of FTM by instance number.
+//! @param x FTM instance number, from 0 through 3.
+#define REGS_FTM_BASE(x) (__g_regs_FTM_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of FTM.
+#define REGS_FTM_INSTANCE(b) ((b) == REGS_FTM0_BASE ? HW_FTM0 : (b) == REGS_FTM1_BASE ? HW_FTM1 : (b) == REGS_FTM2_BASE ? HW_FTM2 : (b) == REGS_FTM3_BASE ? HW_FTM3 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SC - Status And Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+typedef union _hw_ftm_sc
+{
+    uint32_t U;
+    struct _hw_ftm_sc_bitfields
+    {
+        uint32_t PS : 3;               //!< [2:0] Prescale Factor Selection
+        uint32_t CLKS : 2;             //!< [4:3] Clock Source Selection
+        uint32_t CPWMS : 1;            //!< [5] Center-Aligned PWM Select
+        uint32_t TOIE : 1;             //!< [6] Timer Overflow Interrupt Enable
+        uint32_t TOF : 1;              //!< [7] Timer Overflow Flag
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+//@{
+#define HW_FTM_SC_ADDR(x)        (REGS_FTM_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SC(x)             (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
+#define HW_FTM_SC_RD(x)          (HW_FTM_SC(x).U)
+#define HW_FTM_SC_WR(x, v)       (HW_FTM_SC(x).U = (v))
+#define HW_FTM_SC_SET(x, v)      (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) |  (v)))
+#define HW_FTM_SC_CLR(x, v)      (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
+#define HW_FTM_SC_TOG(x, v)      (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 000 - Divide by 1
+ * - 001 - Divide by 2
+ * - 010 - Divide by 4
+ * - 011 - Divide by 8
+ * - 100 - Divide by 16
+ * - 101 - Divide by 32
+ * - 110 - Divide by 64
+ * - 111 - Divide by 128
+ */
+//@{
+#define BP_FTM_SC_PS         (0U)          //!< Bit position for FTM_SC_PS.
+#define BM_FTM_SC_PS         (0x00000007U) //!< Bit mask for FTM_SC_PS.
+#define BS_FTM_SC_PS         (3U)          //!< Bit field size in bits for FTM_SC_PS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_PS field.
+#define BR_FTM_SC_PS(x)      (HW_FTM_SC(x).B.PS)
+#endif
+
+//! @brief Format value for bitfield FTM_SC_PS.
+#define BF_FTM_SC_PS(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_PS), uint32_t) & BM_FTM_SC_PS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PS field to a new value.
+#define BW_FTM_SC_PS(x, v)   (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 00 - No clock selected. This in effect disables the FTM counter.
+ * - 01 - System clock
+ * - 10 - Fixed frequency clock
+ * - 11 - External clock
+ */
+//@{
+#define BP_FTM_SC_CLKS       (3U)          //!< Bit position for FTM_SC_CLKS.
+#define BM_FTM_SC_CLKS       (0x00000018U) //!< Bit mask for FTM_SC_CLKS.
+#define BS_FTM_SC_CLKS       (2U)          //!< Bit field size in bits for FTM_SC_CLKS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_CLKS field.
+#define BR_FTM_SC_CLKS(x)    (HW_FTM_SC(x).B.CLKS)
+#endif
+
+//! @brief Format value for bitfield FTM_SC_CLKS.
+#define BF_FTM_SC_CLKS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CLKS), uint32_t) & BM_FTM_SC_CLKS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKS field to a new value.
+#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0 - FTM counter operates in Up Counting mode.
+ * - 1 - FTM counter operates in Up-Down Counting mode.
+ */
+//@{
+#define BP_FTM_SC_CPWMS      (5U)          //!< Bit position for FTM_SC_CPWMS.
+#define BM_FTM_SC_CPWMS      (0x00000020U) //!< Bit mask for FTM_SC_CPWMS.
+#define BS_FTM_SC_CPWMS      (1U)          //!< Bit field size in bits for FTM_SC_CPWMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_CPWMS field.
+#define BR_FTM_SC_CPWMS(x)   (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
+#endif
+
+//! @brief Format value for bitfield FTM_SC_CPWMS.
+#define BF_FTM_SC_CPWMS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CPWMS), uint32_t) & BM_FTM_SC_CPWMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPWMS field to a new value.
+#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0 - Disable TOF interrupts. Use software polling.
+ * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+//@{
+#define BP_FTM_SC_TOIE       (6U)          //!< Bit position for FTM_SC_TOIE.
+#define BM_FTM_SC_TOIE       (0x00000040U) //!< Bit mask for FTM_SC_TOIE.
+#define BS_FTM_SC_TOIE       (1U)          //!< Bit field size in bits for FTM_SC_TOIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_TOIE field.
+#define BR_FTM_SC_TOIE(x)    (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
+#endif
+
+//! @brief Format value for bitfield FTM_SC_TOIE.
+#define BF_FTM_SC_TOIE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_TOIE), uint32_t) & BM_FTM_SC_TOIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOIE field to a new value.
+#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0 - FTM counter has not overflowed.
+ * - 1 - FTM counter has overflowed.
+ */
+//@{
+#define BP_FTM_SC_TOF        (7U)          //!< Bit position for FTM_SC_TOF.
+#define BM_FTM_SC_TOF        (0x00000080U) //!< Bit mask for FTM_SC_TOF.
+#define BS_FTM_SC_TOF        (1U)          //!< Bit field size in bits for FTM_SC_TOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_TOF field.
+#define BR_FTM_SC_TOF(x)     (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CNT - Counter
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+typedef union _hw_ftm_cnt
+{
+    uint32_t U;
+    struct _hw_ftm_cnt_bitfields
+    {
+        uint32_t COUNT : 16;           //!< [15:0] Counter Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_ftm_cnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+//@{
+#define HW_FTM_CNT_ADDR(x)       (REGS_FTM_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CNT(x)            (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
+#define HW_FTM_CNT_RD(x)         (HW_FTM_CNT(x).U)
+#define HW_FTM_CNT_WR(x, v)      (HW_FTM_CNT(x).U = (v))
+#define HW_FTM_CNT_SET(x, v)     (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) |  (v)))
+#define HW_FTM_CNT_CLR(x, v)     (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
+#define HW_FTM_CNT_TOG(x, v)     (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+//@{
+#define BP_FTM_CNT_COUNT     (0U)          //!< Bit position for FTM_CNT_COUNT.
+#define BM_FTM_CNT_COUNT     (0x0000FFFFU) //!< Bit mask for FTM_CNT_COUNT.
+#define BS_FTM_CNT_COUNT     (16U)         //!< Bit field size in bits for FTM_CNT_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CNT_COUNT field.
+#define BR_FTM_CNT_COUNT(x)  (HW_FTM_CNT(x).B.COUNT)
+#endif
+
+//! @brief Format value for bitfield FTM_CNT_COUNT.
+#define BF_FTM_CNT_COUNT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNT_COUNT), uint32_t) & BM_FTM_CNT_COUNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COUNT field to a new value.
+#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_MOD - Modulo
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+typedef union _hw_ftm_mod
+{
+    uint32_t U;
+    struct _hw_ftm_mod_bitfields
+    {
+        uint32_t MOD : 16;             //!< [15:0]
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_ftm_mod_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+//@{
+#define HW_FTM_MOD_ADDR(x)       (REGS_FTM_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_MOD(x)            (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
+#define HW_FTM_MOD_RD(x)         (HW_FTM_MOD(x).U)
+#define HW_FTM_MOD_WR(x, v)      (HW_FTM_MOD(x).U = (v))
+#define HW_FTM_MOD_SET(x, v)     (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) |  (v)))
+#define HW_FTM_MOD_CLR(x, v)     (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
+#define HW_FTM_MOD_TOG(x, v)     (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+//@{
+#define BP_FTM_MOD_MOD       (0U)          //!< Bit position for FTM_MOD_MOD.
+#define BM_FTM_MOD_MOD       (0x0000FFFFU) //!< Bit mask for FTM_MOD_MOD.
+#define BS_FTM_MOD_MOD       (16U)         //!< Bit field size in bits for FTM_MOD_MOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MOD_MOD field.
+#define BR_FTM_MOD_MOD(x)    (HW_FTM_MOD(x).B.MOD)
+#endif
+
+//! @brief Format value for bitfield FTM_MOD_MOD.
+#define BF_FTM_MOD_MOD(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MOD_MOD), uint32_t) & BM_FTM_MOD_MOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MOD field to a new value.
+#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CnSC - Channel (n) Status And Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+typedef union _hw_ftm_cnsc
+{
+    uint32_t U;
+    struct _hw_ftm_cnsc_bitfields
+    {
+        uint32_t DMAb : 1;             //!< [0] DMA Enable
+        uint32_t RESERVED0 : 1;        //!< [1]
+        uint32_t ELSA : 1;             //!< [2] Edge or Level Select
+        uint32_t ELSB : 1;             //!< [3] Edge or Level Select
+        uint32_t MSA : 1;              //!< [4] Channel Mode Select
+        uint32_t MSB : 1;              //!< [5] Channel Mode Select
+        uint32_t CHIE : 1;             //!< [6] Channel Interrupt Enable
+        uint32_t CHF : 1;              //!< [7] Channel Flag
+        uint32_t RESERVED1 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_cnsc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+//@{
+#define HW_FTM_CnSC_COUNT (8U)
+
+#define HW_FTM_CnSC_ADDR(x, n)   (REGS_FTM_BASE(x) + 0xCU + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CnSC(x, n)        (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
+#define HW_FTM_CnSC_RD(x, n)     (HW_FTM_CnSC(x, n).U)
+#define HW_FTM_CnSC_WR(x, n, v)  (HW_FTM_CnSC(x, n).U = (v))
+#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) |  (v)))
+#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
+#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0 - Disable DMA transfers.
+ * - 1 - Enable DMA transfers.
+ */
+//@{
+#define BP_FTM_CnSC_DMA      (0U)          //!< Bit position for FTM_CnSC_DMA.
+#define BM_FTM_CnSC_DMA      (0x00000001U) //!< Bit mask for FTM_CnSC_DMA.
+#define BS_FTM_CnSC_DMA      (1U)          //!< Bit field size in bits for FTM_CnSC_DMA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_DMA field.
+#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_DMA.
+#define BF_FTM_CnSC_DMA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_DMA), uint32_t) & BM_FTM_CnSC_DMA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMA field to a new value.
+#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+//@{
+#define BP_FTM_CnSC_ELSA     (2U)          //!< Bit position for FTM_CnSC_ELSA.
+#define BM_FTM_CnSC_ELSA     (0x00000004U) //!< Bit mask for FTM_CnSC_ELSA.
+#define BS_FTM_CnSC_ELSA     (1U)          //!< Bit field size in bits for FTM_CnSC_ELSA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_ELSA field.
+#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_ELSA.
+#define BF_FTM_CnSC_ELSA(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSA), uint32_t) & BM_FTM_CnSC_ELSA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELSA field to a new value.
+#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+//@{
+#define BP_FTM_CnSC_ELSB     (3U)          //!< Bit position for FTM_CnSC_ELSB.
+#define BM_FTM_CnSC_ELSB     (0x00000008U) //!< Bit mask for FTM_CnSC_ELSB.
+#define BS_FTM_CnSC_ELSB     (1U)          //!< Bit field size in bits for FTM_CnSC_ELSB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_ELSB field.
+#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_ELSB.
+#define BF_FTM_CnSC_ELSB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSB), uint32_t) & BM_FTM_CnSC_ELSB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELSB field to a new value.
+#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+//@{
+#define BP_FTM_CnSC_MSA      (4U)          //!< Bit position for FTM_CnSC_MSA.
+#define BM_FTM_CnSC_MSA      (0x00000010U) //!< Bit mask for FTM_CnSC_MSA.
+#define BS_FTM_CnSC_MSA      (1U)          //!< Bit field size in bits for FTM_CnSC_MSA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_MSA field.
+#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_MSA.
+#define BF_FTM_CnSC_MSA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSA), uint32_t) & BM_FTM_CnSC_MSA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSA field to a new value.
+#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+//@{
+#define BP_FTM_CnSC_MSB      (5U)          //!< Bit position for FTM_CnSC_MSB.
+#define BM_FTM_CnSC_MSB      (0x00000020U) //!< Bit mask for FTM_CnSC_MSB.
+#define BS_FTM_CnSC_MSB      (1U)          //!< Bit field size in bits for FTM_CnSC_MSB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_MSB field.
+#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_MSB.
+#define BF_FTM_CnSC_MSB(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSB), uint32_t) & BM_FTM_CnSC_MSB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSB field to a new value.
+#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0 - Disable channel interrupts. Use software polling.
+ * - 1 - Enable channel interrupts.
+ */
+//@{
+#define BP_FTM_CnSC_CHIE     (6U)          //!< Bit position for FTM_CnSC_CHIE.
+#define BM_FTM_CnSC_CHIE     (0x00000040U) //!< Bit mask for FTM_CnSC_CHIE.
+#define BS_FTM_CnSC_CHIE     (1U)          //!< Bit field size in bits for FTM_CnSC_CHIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_CHIE field.
+#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_CHIE.
+#define BF_FTM_CnSC_CHIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_CHIE), uint32_t) & BM_FTM_CnSC_CHIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHIE field to a new value.
+#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_CnSC_CHF      (7U)          //!< Bit position for FTM_CnSC_CHF.
+#define BM_FTM_CnSC_CHF      (0x00000080U) //!< Bit mask for FTM_CnSC_CHF.
+#define BS_FTM_CnSC_CHF      (1U)          //!< Bit field size in bits for FTM_CnSC_CHF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_CHF field.
+#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CnV - Channel (n) Value
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+typedef union _hw_ftm_cnv
+{
+    uint32_t U;
+    struct _hw_ftm_cnv_bitfields
+    {
+        uint32_t VAL : 16;             //!< [15:0] Channel Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_ftm_cnv_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+//@{
+#define HW_FTM_CnV_COUNT (8U)
+
+#define HW_FTM_CnV_ADDR(x, n)    (REGS_FTM_BASE(x) + 0x10U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CnV(x, n)         (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
+#define HW_FTM_CnV_RD(x, n)      (HW_FTM_CnV(x, n).U)
+#define HW_FTM_CnV_WR(x, n, v)   (HW_FTM_CnV(x, n).U = (v))
+#define HW_FTM_CnV_SET(x, n, v)  (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) |  (v)))
+#define HW_FTM_CnV_CLR(x, n, v)  (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
+#define HW_FTM_CnV_TOG(x, n, v)  (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+//@{
+#define BP_FTM_CnV_VAL       (0U)          //!< Bit position for FTM_CnV_VAL.
+#define BM_FTM_CnV_VAL       (0x0000FFFFU) //!< Bit mask for FTM_CnV_VAL.
+#define BS_FTM_CnV_VAL       (16U)         //!< Bit field size in bits for FTM_CnV_VAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnV_VAL field.
+#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
+#endif
+
+//! @brief Format value for bitfield FTM_CnV_VAL.
+#define BF_FTM_CnV_VAL(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnV_VAL), uint32_t) & BM_FTM_CnV_VAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VAL field to a new value.
+#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CNTIN - Counter Initial Value
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+typedef union _hw_ftm_cntin
+{
+    uint32_t U;
+    struct _hw_ftm_cntin_bitfields
+    {
+        uint32_t INIT : 16;            //!< [15:0]
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_ftm_cntin_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+//@{
+#define HW_FTM_CNTIN_ADDR(x)     (REGS_FTM_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CNTIN(x)          (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
+#define HW_FTM_CNTIN_RD(x)       (HW_FTM_CNTIN(x).U)
+#define HW_FTM_CNTIN_WR(x, v)    (HW_FTM_CNTIN(x).U = (v))
+#define HW_FTM_CNTIN_SET(x, v)   (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) |  (v)))
+#define HW_FTM_CNTIN_CLR(x, v)   (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
+#define HW_FTM_CNTIN_TOG(x, v)   (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+//@{
+#define BP_FTM_CNTIN_INIT    (0U)          //!< Bit position for FTM_CNTIN_INIT.
+#define BM_FTM_CNTIN_INIT    (0x0000FFFFU) //!< Bit mask for FTM_CNTIN_INIT.
+#define BS_FTM_CNTIN_INIT    (16U)         //!< Bit field size in bits for FTM_CNTIN_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CNTIN_INIT field.
+#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
+#endif
+
+//! @brief Format value for bitfield FTM_CNTIN_INIT.
+#define BF_FTM_CNTIN_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNTIN_INIT), uint32_t) & BM_FTM_CNTIN_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INIT field to a new value.
+#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_STATUS - Capture And Compare Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+typedef union _hw_ftm_status
+{
+    uint32_t U;
+    struct _hw_ftm_status_bitfields
+    {
+        uint32_t CH0F : 1;             //!< [0] Channel 0 Flag
+        uint32_t CH1F : 1;             //!< [1] Channel 1 Flag
+        uint32_t CH2F : 1;             //!< [2] Channel 2 Flag
+        uint32_t CH3F : 1;             //!< [3] Channel 3 Flag
+        uint32_t CH4F : 1;             //!< [4] Channel 4 Flag
+        uint32_t CH5F : 1;             //!< [5] Channel 5 Flag
+        uint32_t CH6F : 1;             //!< [6] Channel 6 Flag
+        uint32_t CH7F : 1;             //!< [7] Channel 7 Flag
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_status_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+//@{
+#define HW_FTM_STATUS_ADDR(x)    (REGS_FTM_BASE(x) + 0x50U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_STATUS(x)         (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
+#define HW_FTM_STATUS_RD(x)      (HW_FTM_STATUS(x).U)
+#define HW_FTM_STATUS_WR(x, v)   (HW_FTM_STATUS(x).U = (v))
+#define HW_FTM_STATUS_SET(x, v)  (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) |  (v)))
+#define HW_FTM_STATUS_CLR(x, v)  (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
+#define HW_FTM_STATUS_TOG(x, v)  (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH0F   (0U)          //!< Bit position for FTM_STATUS_CH0F.
+#define BM_FTM_STATUS_CH0F   (0x00000001U) //!< Bit mask for FTM_STATUS_CH0F.
+#define BS_FTM_STATUS_CH0F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH0F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH0F field.
+#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH0F.
+#define BF_FTM_STATUS_CH0F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH0F), uint32_t) & BM_FTM_STATUS_CH0F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0F field to a new value.
+#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH1F   (1U)          //!< Bit position for FTM_STATUS_CH1F.
+#define BM_FTM_STATUS_CH1F   (0x00000002U) //!< Bit mask for FTM_STATUS_CH1F.
+#define BS_FTM_STATUS_CH1F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH1F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH1F field.
+#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH1F.
+#define BF_FTM_STATUS_CH1F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH1F), uint32_t) & BM_FTM_STATUS_CH1F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1F field to a new value.
+#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH2F   (2U)          //!< Bit position for FTM_STATUS_CH2F.
+#define BM_FTM_STATUS_CH2F   (0x00000004U) //!< Bit mask for FTM_STATUS_CH2F.
+#define BS_FTM_STATUS_CH2F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH2F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH2F field.
+#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH2F.
+#define BF_FTM_STATUS_CH2F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH2F), uint32_t) & BM_FTM_STATUS_CH2F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2F field to a new value.
+#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH3F   (3U)          //!< Bit position for FTM_STATUS_CH3F.
+#define BM_FTM_STATUS_CH3F   (0x00000008U) //!< Bit mask for FTM_STATUS_CH3F.
+#define BS_FTM_STATUS_CH3F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH3F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH3F field.
+#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH3F.
+#define BF_FTM_STATUS_CH3F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH3F), uint32_t) & BM_FTM_STATUS_CH3F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3F field to a new value.
+#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH4F   (4U)          //!< Bit position for FTM_STATUS_CH4F.
+#define BM_FTM_STATUS_CH4F   (0x00000010U) //!< Bit mask for FTM_STATUS_CH4F.
+#define BS_FTM_STATUS_CH4F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH4F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH4F field.
+#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH4F.
+#define BF_FTM_STATUS_CH4F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH4F), uint32_t) & BM_FTM_STATUS_CH4F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4F field to a new value.
+#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH5F   (5U)          //!< Bit position for FTM_STATUS_CH5F.
+#define BM_FTM_STATUS_CH5F   (0x00000020U) //!< Bit mask for FTM_STATUS_CH5F.
+#define BS_FTM_STATUS_CH5F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH5F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH5F field.
+#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH5F.
+#define BF_FTM_STATUS_CH5F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH5F), uint32_t) & BM_FTM_STATUS_CH5F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5F field to a new value.
+#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH6F   (6U)          //!< Bit position for FTM_STATUS_CH6F.
+#define BM_FTM_STATUS_CH6F   (0x00000040U) //!< Bit mask for FTM_STATUS_CH6F.
+#define BS_FTM_STATUS_CH6F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH6F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH6F field.
+#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH6F.
+#define BF_FTM_STATUS_CH6F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH6F), uint32_t) & BM_FTM_STATUS_CH6F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6F field to a new value.
+#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH7F   (7U)          //!< Bit position for FTM_STATUS_CH7F.
+#define BM_FTM_STATUS_CH7F   (0x00000080U) //!< Bit mask for FTM_STATUS_CH7F.
+#define BS_FTM_STATUS_CH7F   (1U)          //!< Bit field size in bits for FTM_STATUS_CH7F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH7F field.
+#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH7F.
+#define BF_FTM_STATUS_CH7F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH7F), uint32_t) & BM_FTM_STATUS_CH7F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7F field to a new value.
+#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_MODE - Features Mode Selection
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+typedef union _hw_ftm_mode
+{
+    uint32_t U;
+    struct _hw_ftm_mode_bitfields
+    {
+        uint32_t FTMEN : 1;            //!< [0] FTM Enable
+        uint32_t INIT : 1;             //!< [1] Initialize The Channels Output
+        uint32_t WPDIS : 1;            //!< [2] Write Protection Disable
+        uint32_t PWMSYNC : 1;          //!< [3] PWM Synchronization Mode
+        uint32_t CAPTEST : 1;          //!< [4] Capture Test Mode Enable
+        uint32_t FAULTM : 2;           //!< [6:5] Fault Control Mode
+        uint32_t FAULTIE : 1;          //!< [7] Fault Interrupt Enable
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_mode_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+//@{
+#define HW_FTM_MODE_ADDR(x)      (REGS_FTM_BASE(x) + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_MODE(x)           (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
+#define HW_FTM_MODE_RD(x)        (HW_FTM_MODE(x).U)
+#define HW_FTM_MODE_WR(x, v)     (HW_FTM_MODE(x).U = (v))
+#define HW_FTM_MODE_SET(x, v)    (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) |  (v)))
+#define HW_FTM_MODE_CLR(x, v)    (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
+#define HW_FTM_MODE_TOG(x, v)    (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Only the TPM-compatible registers (first set of registers) can be used
+ *     without any restriction. Do not use the FTM-specific registers.
+ * - 1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+//@{
+#define BP_FTM_MODE_FTMEN    (0U)          //!< Bit position for FTM_MODE_FTMEN.
+#define BM_FTM_MODE_FTMEN    (0x00000001U) //!< Bit mask for FTM_MODE_FTMEN.
+#define BS_FTM_MODE_FTMEN    (1U)          //!< Bit field size in bits for FTM_MODE_FTMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_FTMEN field.
+#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_FTMEN.
+#define BF_FTM_MODE_FTMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FTMEN), uint32_t) & BM_FTM_MODE_FTMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTMEN field to a new value.
+#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+//@{
+#define BP_FTM_MODE_INIT     (1U)          //!< Bit position for FTM_MODE_INIT.
+#define BM_FTM_MODE_INIT     (0x00000002U) //!< Bit mask for FTM_MODE_INIT.
+#define BS_FTM_MODE_INIT     (1U)          //!< Bit field size in bits for FTM_MODE_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_INIT field.
+#define BR_FTM_MODE_INIT(x)  (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_INIT.
+#define BF_FTM_MODE_INIT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_INIT), uint32_t) & BM_FTM_MODE_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INIT field to a new value.
+#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0 - Write protection is enabled.
+ * - 1 - Write protection is disabled.
+ */
+//@{
+#define BP_FTM_MODE_WPDIS    (2U)          //!< Bit position for FTM_MODE_WPDIS.
+#define BM_FTM_MODE_WPDIS    (0x00000004U) //!< Bit mask for FTM_MODE_WPDIS.
+#define BS_FTM_MODE_WPDIS    (1U)          //!< Bit field size in bits for FTM_MODE_WPDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_WPDIS field.
+#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_WPDIS.
+#define BF_FTM_MODE_WPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_WPDIS), uint32_t) & BM_FTM_MODE_WPDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPDIS field to a new value.
+#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+//@{
+#define BP_FTM_MODE_PWMSYNC  (3U)          //!< Bit position for FTM_MODE_PWMSYNC.
+#define BM_FTM_MODE_PWMSYNC  (0x00000008U) //!< Bit mask for FTM_MODE_PWMSYNC.
+#define BS_FTM_MODE_PWMSYNC  (1U)          //!< Bit field size in bits for FTM_MODE_PWMSYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_PWMSYNC field.
+#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_PWMSYNC.
+#define BF_FTM_MODE_PWMSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_PWMSYNC), uint32_t) & BM_FTM_MODE_PWMSYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PWMSYNC field to a new value.
+#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Capture test mode is disabled.
+ * - 1 - Capture test mode is enabled.
+ */
+//@{
+#define BP_FTM_MODE_CAPTEST  (4U)          //!< Bit position for FTM_MODE_CAPTEST.
+#define BM_FTM_MODE_CAPTEST  (0x00000010U) //!< Bit mask for FTM_MODE_CAPTEST.
+#define BS_FTM_MODE_CAPTEST  (1U)          //!< Bit field size in bits for FTM_MODE_CAPTEST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_CAPTEST field.
+#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_CAPTEST.
+#define BF_FTM_MODE_CAPTEST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_CAPTEST), uint32_t) & BM_FTM_MODE_CAPTEST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAPTEST field to a new value.
+#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 00 - Fault control is disabled for all channels.
+ * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
+ *     6), and the selected mode is the manual fault clearing.
+ * - 10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+//@{
+#define BP_FTM_MODE_FAULTM   (5U)          //!< Bit position for FTM_MODE_FAULTM.
+#define BM_FTM_MODE_FAULTM   (0x00000060U) //!< Bit mask for FTM_MODE_FAULTM.
+#define BS_FTM_MODE_FAULTM   (2U)          //!< Bit field size in bits for FTM_MODE_FAULTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_FAULTM field.
+#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_FAULTM.
+#define BF_FTM_MODE_FAULTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTM), uint32_t) & BM_FTM_MODE_FAULTM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTM field to a new value.
+#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0 - Fault control interrupt is disabled.
+ * - 1 - Fault control interrupt is enabled.
+ */
+//@{
+#define BP_FTM_MODE_FAULTIE  (7U)          //!< Bit position for FTM_MODE_FAULTIE.
+#define BM_FTM_MODE_FAULTIE  (0x00000080U) //!< Bit mask for FTM_MODE_FAULTIE.
+#define BS_FTM_MODE_FAULTIE  (1U)          //!< Bit field size in bits for FTM_MODE_FAULTIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_FAULTIE field.
+#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_FAULTIE.
+#define BF_FTM_MODE_FAULTIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTIE), uint32_t) & BM_FTM_MODE_FAULTIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTIE field to a new value.
+#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SYNC - Synchronization
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+typedef union _hw_ftm_sync
+{
+    uint32_t U;
+    struct _hw_ftm_sync_bitfields
+    {
+        uint32_t CNTMIN : 1;           //!< [0] Minimum Loading Point Enable
+        uint32_t CNTMAX : 1;           //!< [1] Maximum Loading Point Enable
+        uint32_t REINIT : 1;           //!< [2] FTM Counter Reinitialization By
+                                       //! Synchronization (FTM counter synchronization)
+        uint32_t SYNCHOM : 1;          //!< [3] Output Mask Synchronization
+        uint32_t TRIG0 : 1;            //!< [4] PWM Synchronization Hardware Trigger 0
+        uint32_t TRIG1 : 1;            //!< [5] PWM Synchronization Hardware Trigger 1
+        uint32_t TRIG2 : 1;            //!< [6] PWM Synchronization Hardware Trigger 2
+        uint32_t SWSYNC : 1;           //!< [7] PWM Synchronization Software Trigger
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_sync_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+//@{
+#define HW_FTM_SYNC_ADDR(x)      (REGS_FTM_BASE(x) + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SYNC(x)           (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
+#define HW_FTM_SYNC_RD(x)        (HW_FTM_SYNC(x).U)
+#define HW_FTM_SYNC_WR(x, v)     (HW_FTM_SYNC(x).U = (v))
+#define HW_FTM_SYNC_SET(x, v)    (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) |  (v)))
+#define HW_FTM_SYNC_CLR(x, v)    (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
+#define HW_FTM_SYNC_TOG(x, v)    (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0 - The minimum loading point is disabled.
+ * - 1 - The minimum loading point is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_CNTMIN   (0U)          //!< Bit position for FTM_SYNC_CNTMIN.
+#define BM_FTM_SYNC_CNTMIN   (0x00000001U) //!< Bit mask for FTM_SYNC_CNTMIN.
+#define BS_FTM_SYNC_CNTMIN   (1U)          //!< Bit field size in bits for FTM_SYNC_CNTMIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_CNTMIN field.
+#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_CNTMIN.
+#define BF_FTM_SYNC_CNTMIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMIN), uint32_t) & BM_FTM_SYNC_CNTMIN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTMIN field to a new value.
+#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0 - The maximum loading point is disabled.
+ * - 1 - The maximum loading point is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_CNTMAX   (1U)          //!< Bit position for FTM_SYNC_CNTMAX.
+#define BM_FTM_SYNC_CNTMAX   (0x00000002U) //!< Bit mask for FTM_SYNC_CNTMAX.
+#define BS_FTM_SYNC_CNTMAX   (1U)          //!< Bit field size in bits for FTM_SYNC_CNTMAX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_CNTMAX field.
+#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_CNTMAX.
+#define BF_FTM_SYNC_CNTMAX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMAX), uint32_t) & BM_FTM_SYNC_CNTMAX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTMAX field to a new value.
+#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0 - FTM counter continues to count normally.
+ * - 1 - FTM counter is updated with its initial value when the selected trigger
+ *     is detected.
+ */
+//@{
+#define BP_FTM_SYNC_REINIT   (2U)          //!< Bit position for FTM_SYNC_REINIT.
+#define BM_FTM_SYNC_REINIT   (0x00000004U) //!< Bit mask for FTM_SYNC_REINIT.
+#define BS_FTM_SYNC_REINIT   (1U)          //!< Bit field size in bits for FTM_SYNC_REINIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_REINIT field.
+#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_REINIT.
+#define BF_FTM_SYNC_REINIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_REINIT), uint32_t) & BM_FTM_SYNC_REINIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REINIT field to a new value.
+#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0 - OUTMASK register is updated with the value of its buffer in all rising
+ *     edges of the system clock.
+ * - 1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+//@{
+#define BP_FTM_SYNC_SYNCHOM  (3U)          //!< Bit position for FTM_SYNC_SYNCHOM.
+#define BM_FTM_SYNC_SYNCHOM  (0x00000008U) //!< Bit mask for FTM_SYNC_SYNCHOM.
+#define BS_FTM_SYNC_SYNCHOM  (1U)          //!< Bit field size in bits for FTM_SYNC_SYNCHOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_SYNCHOM field.
+#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_SYNCHOM.
+#define BF_FTM_SYNC_SYNCHOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SYNCHOM), uint32_t) & BM_FTM_SYNC_SYNCHOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCHOM field to a new value.
+#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0 - Trigger is disabled.
+ * - 1 - Trigger is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_TRIG0    (4U)          //!< Bit position for FTM_SYNC_TRIG0.
+#define BM_FTM_SYNC_TRIG0    (0x00000010U) //!< Bit mask for FTM_SYNC_TRIG0.
+#define BS_FTM_SYNC_TRIG0    (1U)          //!< Bit field size in bits for FTM_SYNC_TRIG0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_TRIG0 field.
+#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_TRIG0.
+#define BF_FTM_SYNC_TRIG0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG0), uint32_t) & BM_FTM_SYNC_TRIG0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG0 field to a new value.
+#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0 - Trigger is disabled.
+ * - 1 - Trigger is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_TRIG1    (5U)          //!< Bit position for FTM_SYNC_TRIG1.
+#define BM_FTM_SYNC_TRIG1    (0x00000020U) //!< Bit mask for FTM_SYNC_TRIG1.
+#define BS_FTM_SYNC_TRIG1    (1U)          //!< Bit field size in bits for FTM_SYNC_TRIG1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_TRIG1 field.
+#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_TRIG1.
+#define BF_FTM_SYNC_TRIG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG1), uint32_t) & BM_FTM_SYNC_TRIG1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG1 field to a new value.
+#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0 - Trigger is disabled.
+ * - 1 - Trigger is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_TRIG2    (6U)          //!< Bit position for FTM_SYNC_TRIG2.
+#define BM_FTM_SYNC_TRIG2    (0x00000040U) //!< Bit mask for FTM_SYNC_TRIG2.
+#define BS_FTM_SYNC_TRIG2    (1U)          //!< Bit field size in bits for FTM_SYNC_TRIG2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_TRIG2 field.
+#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_TRIG2.
+#define BF_FTM_SYNC_TRIG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG2), uint32_t) & BM_FTM_SYNC_TRIG2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG2 field to a new value.
+#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0 - Software trigger is not selected.
+ * - 1 - Software trigger is selected.
+ */
+//@{
+#define BP_FTM_SYNC_SWSYNC   (7U)          //!< Bit position for FTM_SYNC_SWSYNC.
+#define BM_FTM_SYNC_SWSYNC   (0x00000080U) //!< Bit mask for FTM_SYNC_SWSYNC.
+#define BS_FTM_SYNC_SWSYNC   (1U)          //!< Bit field size in bits for FTM_SYNC_SWSYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_SWSYNC field.
+#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_SWSYNC.
+#define BF_FTM_SYNC_SWSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SWSYNC), uint32_t) & BM_FTM_SYNC_SWSYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWSYNC field to a new value.
+#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_OUTINIT - Initial State For Channels Output
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_ftm_outinit
+{
+    uint32_t U;
+    struct _hw_ftm_outinit_bitfields
+    {
+        uint32_t CH0OI : 1;            //!< [0] Channel 0 Output Initialization Value
+        uint32_t CH1OI : 1;            //!< [1] Channel 1 Output Initialization Value
+        uint32_t CH2OI : 1;            //!< [2] Channel 2 Output Initialization Value
+        uint32_t CH3OI : 1;            //!< [3] Channel 3 Output Initialization Value
+        uint32_t CH4OI : 1;            //!< [4] Channel 4 Output Initialization Value
+        uint32_t CH5OI : 1;            //!< [5] Channel 5 Output Initialization Value
+        uint32_t CH6OI : 1;            //!< [6] Channel 6 Output Initialization Value
+        uint32_t CH7OI : 1;            //!< [7] Channel 7 Output Initialization Value
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_outinit_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+//@{
+#define HW_FTM_OUTINIT_ADDR(x)   (REGS_FTM_BASE(x) + 0x5CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_OUTINIT(x)        (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
+#define HW_FTM_OUTINIT_RD(x)     (HW_FTM_OUTINIT(x).U)
+#define HW_FTM_OUTINIT_WR(x, v)  (HW_FTM_OUTINIT(x).U = (v))
+#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) |  (v)))
+#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
+#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH0OI (0U)          //!< Bit position for FTM_OUTINIT_CH0OI.
+#define BM_FTM_OUTINIT_CH0OI (0x00000001U) //!< Bit mask for FTM_OUTINIT_CH0OI.
+#define BS_FTM_OUTINIT_CH0OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH0OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH0OI field.
+#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH0OI.
+#define BF_FTM_OUTINIT_CH0OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH0OI), uint32_t) & BM_FTM_OUTINIT_CH0OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OI field to a new value.
+#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH1OI (1U)          //!< Bit position for FTM_OUTINIT_CH1OI.
+#define BM_FTM_OUTINIT_CH1OI (0x00000002U) //!< Bit mask for FTM_OUTINIT_CH1OI.
+#define BS_FTM_OUTINIT_CH1OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH1OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH1OI field.
+#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH1OI.
+#define BF_FTM_OUTINIT_CH1OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH1OI), uint32_t) & BM_FTM_OUTINIT_CH1OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OI field to a new value.
+#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH2OI (2U)          //!< Bit position for FTM_OUTINIT_CH2OI.
+#define BM_FTM_OUTINIT_CH2OI (0x00000004U) //!< Bit mask for FTM_OUTINIT_CH2OI.
+#define BS_FTM_OUTINIT_CH2OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH2OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH2OI field.
+#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH2OI.
+#define BF_FTM_OUTINIT_CH2OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH2OI), uint32_t) & BM_FTM_OUTINIT_CH2OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OI field to a new value.
+#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH3OI (3U)          //!< Bit position for FTM_OUTINIT_CH3OI.
+#define BM_FTM_OUTINIT_CH3OI (0x00000008U) //!< Bit mask for FTM_OUTINIT_CH3OI.
+#define BS_FTM_OUTINIT_CH3OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH3OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH3OI field.
+#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH3OI.
+#define BF_FTM_OUTINIT_CH3OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH3OI), uint32_t) & BM_FTM_OUTINIT_CH3OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OI field to a new value.
+#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH4OI (4U)          //!< Bit position for FTM_OUTINIT_CH4OI.
+#define BM_FTM_OUTINIT_CH4OI (0x00000010U) //!< Bit mask for FTM_OUTINIT_CH4OI.
+#define BS_FTM_OUTINIT_CH4OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH4OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH4OI field.
+#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH4OI.
+#define BF_FTM_OUTINIT_CH4OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH4OI), uint32_t) & BM_FTM_OUTINIT_CH4OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OI field to a new value.
+#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH5OI (5U)          //!< Bit position for FTM_OUTINIT_CH5OI.
+#define BM_FTM_OUTINIT_CH5OI (0x00000020U) //!< Bit mask for FTM_OUTINIT_CH5OI.
+#define BS_FTM_OUTINIT_CH5OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH5OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH5OI field.
+#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH5OI.
+#define BF_FTM_OUTINIT_CH5OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH5OI), uint32_t) & BM_FTM_OUTINIT_CH5OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OI field to a new value.
+#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH6OI (6U)          //!< Bit position for FTM_OUTINIT_CH6OI.
+#define BM_FTM_OUTINIT_CH6OI (0x00000040U) //!< Bit mask for FTM_OUTINIT_CH6OI.
+#define BS_FTM_OUTINIT_CH6OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH6OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH6OI field.
+#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH6OI.
+#define BF_FTM_OUTINIT_CH6OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH6OI), uint32_t) & BM_FTM_OUTINIT_CH6OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OI field to a new value.
+#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH7OI (7U)          //!< Bit position for FTM_OUTINIT_CH7OI.
+#define BM_FTM_OUTINIT_CH7OI (0x00000080U) //!< Bit mask for FTM_OUTINIT_CH7OI.
+#define BS_FTM_OUTINIT_CH7OI (1U)          //!< Bit field size in bits for FTM_OUTINIT_CH7OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH7OI field.
+#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH7OI.
+#define BF_FTM_OUTINIT_CH7OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH7OI), uint32_t) & BM_FTM_OUTINIT_CH7OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OI field to a new value.
+#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_OUTMASK - Output Mask
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+typedef union _hw_ftm_outmask
+{
+    uint32_t U;
+    struct _hw_ftm_outmask_bitfields
+    {
+        uint32_t CH0OM : 1;            //!< [0] Channel 0 Output Mask
+        uint32_t CH1OM : 1;            //!< [1] Channel 1 Output Mask
+        uint32_t CH2OM : 1;            //!< [2] Channel 2 Output Mask
+        uint32_t CH3OM : 1;            //!< [3] Channel 3 Output Mask
+        uint32_t CH4OM : 1;            //!< [4] Channel 4 Output Mask
+        uint32_t CH5OM : 1;            //!< [5] Channel 5 Output Mask
+        uint32_t CH6OM : 1;            //!< [6] Channel 6 Output Mask
+        uint32_t CH7OM : 1;            //!< [7] Channel 7 Output Mask
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_outmask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+//@{
+#define HW_FTM_OUTMASK_ADDR(x)   (REGS_FTM_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_OUTMASK(x)        (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
+#define HW_FTM_OUTMASK_RD(x)     (HW_FTM_OUTMASK(x).U)
+#define HW_FTM_OUTMASK_WR(x, v)  (HW_FTM_OUTMASK(x).U = (v))
+#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) |  (v)))
+#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
+#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH0OM (0U)          //!< Bit position for FTM_OUTMASK_CH0OM.
+#define BM_FTM_OUTMASK_CH0OM (0x00000001U) //!< Bit mask for FTM_OUTMASK_CH0OM.
+#define BS_FTM_OUTMASK_CH0OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH0OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH0OM field.
+#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH0OM.
+#define BF_FTM_OUTMASK_CH0OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH0OM), uint32_t) & BM_FTM_OUTMASK_CH0OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OM field to a new value.
+#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH1OM (1U)          //!< Bit position for FTM_OUTMASK_CH1OM.
+#define BM_FTM_OUTMASK_CH1OM (0x00000002U) //!< Bit mask for FTM_OUTMASK_CH1OM.
+#define BS_FTM_OUTMASK_CH1OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH1OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH1OM field.
+#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH1OM.
+#define BF_FTM_OUTMASK_CH1OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH1OM), uint32_t) & BM_FTM_OUTMASK_CH1OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OM field to a new value.
+#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH2OM (2U)          //!< Bit position for FTM_OUTMASK_CH2OM.
+#define BM_FTM_OUTMASK_CH2OM (0x00000004U) //!< Bit mask for FTM_OUTMASK_CH2OM.
+#define BS_FTM_OUTMASK_CH2OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH2OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH2OM field.
+#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH2OM.
+#define BF_FTM_OUTMASK_CH2OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH2OM), uint32_t) & BM_FTM_OUTMASK_CH2OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OM field to a new value.
+#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH3OM (3U)          //!< Bit position for FTM_OUTMASK_CH3OM.
+#define BM_FTM_OUTMASK_CH3OM (0x00000008U) //!< Bit mask for FTM_OUTMASK_CH3OM.
+#define BS_FTM_OUTMASK_CH3OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH3OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH3OM field.
+#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH3OM.
+#define BF_FTM_OUTMASK_CH3OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH3OM), uint32_t) & BM_FTM_OUTMASK_CH3OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OM field to a new value.
+#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH4OM (4U)          //!< Bit position for FTM_OUTMASK_CH4OM.
+#define BM_FTM_OUTMASK_CH4OM (0x00000010U) //!< Bit mask for FTM_OUTMASK_CH4OM.
+#define BS_FTM_OUTMASK_CH4OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH4OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH4OM field.
+#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH4OM.
+#define BF_FTM_OUTMASK_CH4OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH4OM), uint32_t) & BM_FTM_OUTMASK_CH4OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OM field to a new value.
+#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH5OM (5U)          //!< Bit position for FTM_OUTMASK_CH5OM.
+#define BM_FTM_OUTMASK_CH5OM (0x00000020U) //!< Bit mask for FTM_OUTMASK_CH5OM.
+#define BS_FTM_OUTMASK_CH5OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH5OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH5OM field.
+#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH5OM.
+#define BF_FTM_OUTMASK_CH5OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH5OM), uint32_t) & BM_FTM_OUTMASK_CH5OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OM field to a new value.
+#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH6OM (6U)          //!< Bit position for FTM_OUTMASK_CH6OM.
+#define BM_FTM_OUTMASK_CH6OM (0x00000040U) //!< Bit mask for FTM_OUTMASK_CH6OM.
+#define BS_FTM_OUTMASK_CH6OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH6OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH6OM field.
+#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH6OM.
+#define BF_FTM_OUTMASK_CH6OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH6OM), uint32_t) & BM_FTM_OUTMASK_CH6OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OM field to a new value.
+#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH7OM (7U)          //!< Bit position for FTM_OUTMASK_CH7OM.
+#define BM_FTM_OUTMASK_CH7OM (0x00000080U) //!< Bit mask for FTM_OUTMASK_CH7OM.
+#define BS_FTM_OUTMASK_CH7OM (1U)          //!< Bit field size in bits for FTM_OUTMASK_CH7OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH7OM field.
+#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH7OM.
+#define BF_FTM_OUTMASK_CH7OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH7OM), uint32_t) & BM_FTM_OUTMASK_CH7OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OM field to a new value.
+#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_COMBINE - Function For Linked Channels
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+typedef union _hw_ftm_combine
+{
+    uint32_t U;
+    struct _hw_ftm_combine_bitfields
+    {
+        uint32_t COMBINE0 : 1;         //!< [0] Combine Channels For n = 0
+        uint32_t COMP0 : 1;            //!< [1] Complement Of Channel (n) For n = 0
+        uint32_t DECAPEN0 : 1;         //!< [2] Dual Edge Capture Mode Enable For n =
+                                       //! 0
+        uint32_t DECAP0 : 1;           //!< [3] Dual Edge Capture Mode Captures For n =
+                                       //! 0
+        uint32_t DTEN0 : 1;            //!< [4] Deadtime Enable For n = 0
+        uint32_t SYNCEN0 : 1;          //!< [5] Synchronization Enable For n = 0
+        uint32_t FAULTEN0 : 1;         //!< [6] Fault Control Enable For n = 0
+        uint32_t RESERVED0 : 1;        //!< [7]
+        uint32_t COMBINE1 : 1;         //!< [8] Combine Channels For n = 2
+        uint32_t COMP1 : 1;            //!< [9] Complement Of Channel (n) For n = 2
+        uint32_t DECAPEN1 : 1;         //!< [10] Dual Edge Capture Mode Enable For n
+                                       //! = 2
+        uint32_t DECAP1 : 1;           //!< [11] Dual Edge Capture Mode Captures For n
+                                       //! = 2
+        uint32_t DTEN1 : 1;            //!< [12] Deadtime Enable For n = 2
+        uint32_t SYNCEN1 : 1;          //!< [13] Synchronization Enable For n = 2
+        uint32_t FAULTEN1 : 1;         //!< [14] Fault Control Enable For n = 2
+        uint32_t RESERVED1 : 1;        //!< [15]
+        uint32_t COMBINE2 : 1;         //!< [16] Combine Channels For n = 4
+        uint32_t COMP2 : 1;            //!< [17] Complement Of Channel (n) For n = 4
+        uint32_t DECAPEN2 : 1;         //!< [18] Dual Edge Capture Mode Enable For n
+                                       //! = 4
+        uint32_t DECAP2 : 1;           //!< [19] Dual Edge Capture Mode Captures For n
+                                       //! = 4
+        uint32_t DTEN2 : 1;            //!< [20] Deadtime Enable For n = 4
+        uint32_t SYNCEN2 : 1;          //!< [21] Synchronization Enable For n = 4
+        uint32_t FAULTEN2 : 1;         //!< [22] Fault Control Enable For n = 4
+        uint32_t RESERVED2 : 1;        //!< [23]
+        uint32_t COMBINE3 : 1;         //!< [24] Combine Channels For n = 6
+        uint32_t COMP3 : 1;            //!< [25] Complement Of Channel (n) for n = 6
+        uint32_t DECAPEN3 : 1;         //!< [26] Dual Edge Capture Mode Enable For n
+                                       //! = 6
+        uint32_t DECAP3 : 1;           //!< [27] Dual Edge Capture Mode Captures For n
+                                       //! = 6
+        uint32_t DTEN3 : 1;            //!< [28] Deadtime Enable For n = 6
+        uint32_t SYNCEN3 : 1;          //!< [29] Synchronization Enable For n = 6
+        uint32_t FAULTEN3 : 1;         //!< [30] Fault Control Enable For n = 6
+        uint32_t RESERVED3 : 1;        //!< [31]
+    } B;
+} hw_ftm_combine_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+//@{
+#define HW_FTM_COMBINE_ADDR(x)   (REGS_FTM_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_COMBINE(x)        (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
+#define HW_FTM_COMBINE_RD(x)     (HW_FTM_COMBINE(x).U)
+#define HW_FTM_COMBINE_WR(x, v)  (HW_FTM_COMBINE(x).U = (v))
+#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) |  (v)))
+#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
+#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE0 (0U)       //!< Bit position for FTM_COMBINE_COMBINE0.
+#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) //!< Bit mask for FTM_COMBINE_COMBINE0.
+#define BS_FTM_COMBINE_COMBINE0 (1U)       //!< Bit field size in bits for FTM_COMBINE_COMBINE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE0 field.
+#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE0.
+#define BF_FTM_COMBINE_COMBINE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE0), uint32_t) & BM_FTM_COMBINE_COMBINE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE0 field to a new value.
+#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP0 (1U)          //!< Bit position for FTM_COMBINE_COMP0.
+#define BM_FTM_COMBINE_COMP0 (0x00000002U) //!< Bit mask for FTM_COMBINE_COMP0.
+#define BS_FTM_COMBINE_COMP0 (1U)          //!< Bit field size in bits for FTM_COMBINE_COMP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP0 field.
+#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP0.
+#define BF_FTM_COMBINE_COMP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP0), uint32_t) & BM_FTM_COMBINE_COMP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP0 field to a new value.
+#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN0 (2U)       //!< Bit position for FTM_COMBINE_DECAPEN0.
+#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) //!< Bit mask for FTM_COMBINE_DECAPEN0.
+#define BS_FTM_COMBINE_DECAPEN0 (1U)       //!< Bit field size in bits for FTM_COMBINE_DECAPEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN0 field.
+#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN0.
+#define BF_FTM_COMBINE_DECAPEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN0), uint32_t) & BM_FTM_COMBINE_DECAPEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN0 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP0 (3U)         //!< Bit position for FTM_COMBINE_DECAP0.
+#define BM_FTM_COMBINE_DECAP0 (0x00000008U) //!< Bit mask for FTM_COMBINE_DECAP0.
+#define BS_FTM_COMBINE_DECAP0 (1U)         //!< Bit field size in bits for FTM_COMBINE_DECAP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP0 field.
+#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP0.
+#define BF_FTM_COMBINE_DECAP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP0), uint32_t) & BM_FTM_COMBINE_DECAP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP0 field to a new value.
+#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN0 (4U)          //!< Bit position for FTM_COMBINE_DTEN0.
+#define BM_FTM_COMBINE_DTEN0 (0x00000010U) //!< Bit mask for FTM_COMBINE_DTEN0.
+#define BS_FTM_COMBINE_DTEN0 (1U)          //!< Bit field size in bits for FTM_COMBINE_DTEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN0 field.
+#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN0.
+#define BF_FTM_COMBINE_DTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN0), uint32_t) & BM_FTM_COMBINE_DTEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN0 field to a new value.
+#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN0 (5U)        //!< Bit position for FTM_COMBINE_SYNCEN0.
+#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) //!< Bit mask for FTM_COMBINE_SYNCEN0.
+#define BS_FTM_COMBINE_SYNCEN0 (1U)        //!< Bit field size in bits for FTM_COMBINE_SYNCEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN0 field.
+#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN0.
+#define BF_FTM_COMBINE_SYNCEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN0), uint32_t) & BM_FTM_COMBINE_SYNCEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN0 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN0 (6U)       //!< Bit position for FTM_COMBINE_FAULTEN0.
+#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) //!< Bit mask for FTM_COMBINE_FAULTEN0.
+#define BS_FTM_COMBINE_FAULTEN0 (1U)       //!< Bit field size in bits for FTM_COMBINE_FAULTEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN0 field.
+#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN0.
+#define BF_FTM_COMBINE_FAULTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN0), uint32_t) & BM_FTM_COMBINE_FAULTEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN0 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE1 (8U)       //!< Bit position for FTM_COMBINE_COMBINE1.
+#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) //!< Bit mask for FTM_COMBINE_COMBINE1.
+#define BS_FTM_COMBINE_COMBINE1 (1U)       //!< Bit field size in bits for FTM_COMBINE_COMBINE1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE1 field.
+#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE1.
+#define BF_FTM_COMBINE_COMBINE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE1), uint32_t) & BM_FTM_COMBINE_COMBINE1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE1 field to a new value.
+#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP1 (9U)          //!< Bit position for FTM_COMBINE_COMP1.
+#define BM_FTM_COMBINE_COMP1 (0x00000200U) //!< Bit mask for FTM_COMBINE_COMP1.
+#define BS_FTM_COMBINE_COMP1 (1U)          //!< Bit field size in bits for FTM_COMBINE_COMP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP1 field.
+#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP1.
+#define BF_FTM_COMBINE_COMP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP1), uint32_t) & BM_FTM_COMBINE_COMP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP1 field to a new value.
+#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN1 (10U)      //!< Bit position for FTM_COMBINE_DECAPEN1.
+#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) //!< Bit mask for FTM_COMBINE_DECAPEN1.
+#define BS_FTM_COMBINE_DECAPEN1 (1U)       //!< Bit field size in bits for FTM_COMBINE_DECAPEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN1 field.
+#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN1.
+#define BF_FTM_COMBINE_DECAPEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN1), uint32_t) & BM_FTM_COMBINE_DECAPEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN1 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP1 (11U)        //!< Bit position for FTM_COMBINE_DECAP1.
+#define BM_FTM_COMBINE_DECAP1 (0x00000800U) //!< Bit mask for FTM_COMBINE_DECAP1.
+#define BS_FTM_COMBINE_DECAP1 (1U)         //!< Bit field size in bits for FTM_COMBINE_DECAP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP1 field.
+#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP1.
+#define BF_FTM_COMBINE_DECAP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP1), uint32_t) & BM_FTM_COMBINE_DECAP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP1 field to a new value.
+#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN1 (12U)         //!< Bit position for FTM_COMBINE_DTEN1.
+#define BM_FTM_COMBINE_DTEN1 (0x00001000U) //!< Bit mask for FTM_COMBINE_DTEN1.
+#define BS_FTM_COMBINE_DTEN1 (1U)          //!< Bit field size in bits for FTM_COMBINE_DTEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN1 field.
+#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN1.
+#define BF_FTM_COMBINE_DTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN1), uint32_t) & BM_FTM_COMBINE_DTEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN1 field to a new value.
+#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN1 (13U)       //!< Bit position for FTM_COMBINE_SYNCEN1.
+#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) //!< Bit mask for FTM_COMBINE_SYNCEN1.
+#define BS_FTM_COMBINE_SYNCEN1 (1U)        //!< Bit field size in bits for FTM_COMBINE_SYNCEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN1 field.
+#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN1.
+#define BF_FTM_COMBINE_SYNCEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN1), uint32_t) & BM_FTM_COMBINE_SYNCEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN1 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN1 (14U)      //!< Bit position for FTM_COMBINE_FAULTEN1.
+#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) //!< Bit mask for FTM_COMBINE_FAULTEN1.
+#define BS_FTM_COMBINE_FAULTEN1 (1U)       //!< Bit field size in bits for FTM_COMBINE_FAULTEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN1 field.
+#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN1.
+#define BF_FTM_COMBINE_FAULTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN1), uint32_t) & BM_FTM_COMBINE_FAULTEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN1 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE2 (16U)      //!< Bit position for FTM_COMBINE_COMBINE2.
+#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) //!< Bit mask for FTM_COMBINE_COMBINE2.
+#define BS_FTM_COMBINE_COMBINE2 (1U)       //!< Bit field size in bits for FTM_COMBINE_COMBINE2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE2 field.
+#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE2.
+#define BF_FTM_COMBINE_COMBINE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE2), uint32_t) & BM_FTM_COMBINE_COMBINE2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE2 field to a new value.
+#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP2 (17U)         //!< Bit position for FTM_COMBINE_COMP2.
+#define BM_FTM_COMBINE_COMP2 (0x00020000U) //!< Bit mask for FTM_COMBINE_COMP2.
+#define BS_FTM_COMBINE_COMP2 (1U)          //!< Bit field size in bits for FTM_COMBINE_COMP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP2 field.
+#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP2.
+#define BF_FTM_COMBINE_COMP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP2), uint32_t) & BM_FTM_COMBINE_COMP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP2 field to a new value.
+#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN2 (18U)      //!< Bit position for FTM_COMBINE_DECAPEN2.
+#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) //!< Bit mask for FTM_COMBINE_DECAPEN2.
+#define BS_FTM_COMBINE_DECAPEN2 (1U)       //!< Bit field size in bits for FTM_COMBINE_DECAPEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN2 field.
+#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN2.
+#define BF_FTM_COMBINE_DECAPEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN2), uint32_t) & BM_FTM_COMBINE_DECAPEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN2 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP2 (19U)        //!< Bit position for FTM_COMBINE_DECAP2.
+#define BM_FTM_COMBINE_DECAP2 (0x00080000U) //!< Bit mask for FTM_COMBINE_DECAP2.
+#define BS_FTM_COMBINE_DECAP2 (1U)         //!< Bit field size in bits for FTM_COMBINE_DECAP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP2 field.
+#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP2.
+#define BF_FTM_COMBINE_DECAP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP2), uint32_t) & BM_FTM_COMBINE_DECAP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP2 field to a new value.
+#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN2 (20U)         //!< Bit position for FTM_COMBINE_DTEN2.
+#define BM_FTM_COMBINE_DTEN2 (0x00100000U) //!< Bit mask for FTM_COMBINE_DTEN2.
+#define BS_FTM_COMBINE_DTEN2 (1U)          //!< Bit field size in bits for FTM_COMBINE_DTEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN2 field.
+#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN2.
+#define BF_FTM_COMBINE_DTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN2), uint32_t) & BM_FTM_COMBINE_DTEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN2 field to a new value.
+#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN2 (21U)       //!< Bit position for FTM_COMBINE_SYNCEN2.
+#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) //!< Bit mask for FTM_COMBINE_SYNCEN2.
+#define BS_FTM_COMBINE_SYNCEN2 (1U)        //!< Bit field size in bits for FTM_COMBINE_SYNCEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN2 field.
+#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN2.
+#define BF_FTM_COMBINE_SYNCEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN2), uint32_t) & BM_FTM_COMBINE_SYNCEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN2 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN2 (22U)      //!< Bit position for FTM_COMBINE_FAULTEN2.
+#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) //!< Bit mask for FTM_COMBINE_FAULTEN2.
+#define BS_FTM_COMBINE_FAULTEN2 (1U)       //!< Bit field size in bits for FTM_COMBINE_FAULTEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN2 field.
+#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN2.
+#define BF_FTM_COMBINE_FAULTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN2), uint32_t) & BM_FTM_COMBINE_FAULTEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN2 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE3 (24U)      //!< Bit position for FTM_COMBINE_COMBINE3.
+#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) //!< Bit mask for FTM_COMBINE_COMBINE3.
+#define BS_FTM_COMBINE_COMBINE3 (1U)       //!< Bit field size in bits for FTM_COMBINE_COMBINE3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE3 field.
+#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE3.
+#define BF_FTM_COMBINE_COMBINE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE3), uint32_t) & BM_FTM_COMBINE_COMBINE3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE3 field to a new value.
+#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP3 (25U)         //!< Bit position for FTM_COMBINE_COMP3.
+#define BM_FTM_COMBINE_COMP3 (0x02000000U) //!< Bit mask for FTM_COMBINE_COMP3.
+#define BS_FTM_COMBINE_COMP3 (1U)          //!< Bit field size in bits for FTM_COMBINE_COMP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP3 field.
+#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP3.
+#define BF_FTM_COMBINE_COMP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP3), uint32_t) & BM_FTM_COMBINE_COMP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP3 field to a new value.
+#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN3 (26U)      //!< Bit position for FTM_COMBINE_DECAPEN3.
+#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) //!< Bit mask for FTM_COMBINE_DECAPEN3.
+#define BS_FTM_COMBINE_DECAPEN3 (1U)       //!< Bit field size in bits for FTM_COMBINE_DECAPEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN3 field.
+#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN3.
+#define BF_FTM_COMBINE_DECAPEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN3), uint32_t) & BM_FTM_COMBINE_DECAPEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN3 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP3 (27U)        //!< Bit position for FTM_COMBINE_DECAP3.
+#define BM_FTM_COMBINE_DECAP3 (0x08000000U) //!< Bit mask for FTM_COMBINE_DECAP3.
+#define BS_FTM_COMBINE_DECAP3 (1U)         //!< Bit field size in bits for FTM_COMBINE_DECAP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP3 field.
+#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP3.
+#define BF_FTM_COMBINE_DECAP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP3), uint32_t) & BM_FTM_COMBINE_DECAP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP3 field to a new value.
+#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN3 (28U)         //!< Bit position for FTM_COMBINE_DTEN3.
+#define BM_FTM_COMBINE_DTEN3 (0x10000000U) //!< Bit mask for FTM_COMBINE_DTEN3.
+#define BS_FTM_COMBINE_DTEN3 (1U)          //!< Bit field size in bits for FTM_COMBINE_DTEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN3 field.
+#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN3.
+#define BF_FTM_COMBINE_DTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN3), uint32_t) & BM_FTM_COMBINE_DTEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN3 field to a new value.
+#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN3 (29U)       //!< Bit position for FTM_COMBINE_SYNCEN3.
+#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) //!< Bit mask for FTM_COMBINE_SYNCEN3.
+#define BS_FTM_COMBINE_SYNCEN3 (1U)        //!< Bit field size in bits for FTM_COMBINE_SYNCEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN3 field.
+#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN3.
+#define BF_FTM_COMBINE_SYNCEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN3), uint32_t) & BM_FTM_COMBINE_SYNCEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN3 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN3 (30U)      //!< Bit position for FTM_COMBINE_FAULTEN3.
+#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) //!< Bit mask for FTM_COMBINE_FAULTEN3.
+#define BS_FTM_COMBINE_FAULTEN3 (1U)       //!< Bit field size in bits for FTM_COMBINE_FAULTEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN3 field.
+#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN3.
+#define BF_FTM_COMBINE_FAULTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN3), uint32_t) & BM_FTM_COMBINE_FAULTEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN3 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_DEADTIME - Deadtime Insertion Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+typedef union _hw_ftm_deadtime
+{
+    uint32_t U;
+    struct _hw_ftm_deadtime_bitfields
+    {
+        uint32_t DTVAL : 6;            //!< [5:0] Deadtime Value
+        uint32_t DTPS : 2;             //!< [7:6] Deadtime Prescaler Value
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_deadtime_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+//@{
+#define HW_FTM_DEADTIME_ADDR(x)  (REGS_FTM_BASE(x) + 0x68U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_DEADTIME(x)       (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
+#define HW_FTM_DEADTIME_RD(x)    (HW_FTM_DEADTIME(x).U)
+#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
+#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) |  (v)))
+#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
+#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+//@{
+#define BP_FTM_DEADTIME_DTVAL (0U)         //!< Bit position for FTM_DEADTIME_DTVAL.
+#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) //!< Bit mask for FTM_DEADTIME_DTVAL.
+#define BS_FTM_DEADTIME_DTVAL (6U)         //!< Bit field size in bits for FTM_DEADTIME_DTVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_DEADTIME_DTVAL field.
+#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_DEADTIME_DTVAL.
+#define BF_FTM_DEADTIME_DTVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTVAL), uint32_t) & BM_FTM_DEADTIME_DTVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTVAL field to a new value.
+#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0x - Divide the system clock by 1.
+ * - 10 - Divide the system clock by 4.
+ * - 11 - Divide the system clock by 16.
+ */
+//@{
+#define BP_FTM_DEADTIME_DTPS (6U)          //!< Bit position for FTM_DEADTIME_DTPS.
+#define BM_FTM_DEADTIME_DTPS (0x000000C0U) //!< Bit mask for FTM_DEADTIME_DTPS.
+#define BS_FTM_DEADTIME_DTPS (2U)          //!< Bit field size in bits for FTM_DEADTIME_DTPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_DEADTIME_DTPS field.
+#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
+#endif
+
+//! @brief Format value for bitfield FTM_DEADTIME_DTPS.
+#define BF_FTM_DEADTIME_DTPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTPS), uint32_t) & BM_FTM_DEADTIME_DTPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTPS field to a new value.
+#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_EXTTRIG - FTM External Trigger
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+typedef union _hw_ftm_exttrig
+{
+    uint32_t U;
+    struct _hw_ftm_exttrig_bitfields
+    {
+        uint32_t CH2TRIG : 1;          //!< [0] Channel 2 Trigger Enable
+        uint32_t CH3TRIG : 1;          //!< [1] Channel 3 Trigger Enable
+        uint32_t CH4TRIG : 1;          //!< [2] Channel 4 Trigger Enable
+        uint32_t CH5TRIG : 1;          //!< [3] Channel 5 Trigger Enable
+        uint32_t CH0TRIG : 1;          //!< [4] Channel 0 Trigger Enable
+        uint32_t CH1TRIG : 1;          //!< [5] Channel 1 Trigger Enable
+        uint32_t INITTRIGEN : 1;       //!< [6] Initialization Trigger Enable
+        uint32_t TRIGF : 1;            //!< [7] Channel Trigger Flag
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_exttrig_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+//@{
+#define HW_FTM_EXTTRIG_ADDR(x)   (REGS_FTM_BASE(x) + 0x6CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_EXTTRIG(x)        (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
+#define HW_FTM_EXTTRIG_RD(x)     (HW_FTM_EXTTRIG(x).U)
+#define HW_FTM_EXTTRIG_WR(x, v)  (HW_FTM_EXTTRIG(x).U = (v))
+#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) |  (v)))
+#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
+#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH2TRIG (0U)        //!< Bit position for FTM_EXTTRIG_CH2TRIG.
+#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) //!< Bit mask for FTM_EXTTRIG_CH2TRIG.
+#define BS_FTM_EXTTRIG_CH2TRIG (1U)        //!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field.
+#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG.
+#define BF_FTM_EXTTRIG_CH2TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH2TRIG), uint32_t) & BM_FTM_EXTTRIG_CH2TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH3TRIG (1U)        //!< Bit position for FTM_EXTTRIG_CH3TRIG.
+#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) //!< Bit mask for FTM_EXTTRIG_CH3TRIG.
+#define BS_FTM_EXTTRIG_CH3TRIG (1U)        //!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field.
+#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG.
+#define BF_FTM_EXTTRIG_CH3TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH3TRIG), uint32_t) & BM_FTM_EXTTRIG_CH3TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH4TRIG (2U)        //!< Bit position for FTM_EXTTRIG_CH4TRIG.
+#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) //!< Bit mask for FTM_EXTTRIG_CH4TRIG.
+#define BS_FTM_EXTTRIG_CH4TRIG (1U)        //!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field.
+#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG.
+#define BF_FTM_EXTTRIG_CH4TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH4TRIG), uint32_t) & BM_FTM_EXTTRIG_CH4TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH5TRIG (3U)        //!< Bit position for FTM_EXTTRIG_CH5TRIG.
+#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) //!< Bit mask for FTM_EXTTRIG_CH5TRIG.
+#define BS_FTM_EXTTRIG_CH5TRIG (1U)        //!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field.
+#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG.
+#define BF_FTM_EXTTRIG_CH5TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH5TRIG), uint32_t) & BM_FTM_EXTTRIG_CH5TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH0TRIG (4U)        //!< Bit position for FTM_EXTTRIG_CH0TRIG.
+#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) //!< Bit mask for FTM_EXTTRIG_CH0TRIG.
+#define BS_FTM_EXTTRIG_CH0TRIG (1U)        //!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field.
+#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG.
+#define BF_FTM_EXTTRIG_CH0TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH0TRIG), uint32_t) & BM_FTM_EXTTRIG_CH0TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH1TRIG (5U)        //!< Bit position for FTM_EXTTRIG_CH1TRIG.
+#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) //!< Bit mask for FTM_EXTTRIG_CH1TRIG.
+#define BS_FTM_EXTTRIG_CH1TRIG (1U)        //!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field.
+#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG.
+#define BF_FTM_EXTTRIG_CH1TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH1TRIG), uint32_t) & BM_FTM_EXTTRIG_CH1TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0 - The generation of initialization trigger is disabled.
+ * - 1 - The generation of initialization trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_INITTRIGEN (6U)     //!< Bit position for FTM_EXTTRIG_INITTRIGEN.
+#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) //!< Bit mask for FTM_EXTTRIG_INITTRIGEN.
+#define BS_FTM_EXTTRIG_INITTRIGEN (1U)     //!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field.
+#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN.
+#define BF_FTM_EXTTRIG_INITTRIGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_INITTRIGEN), uint32_t) & BM_FTM_EXTTRIG_INITTRIGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITTRIGEN field to a new value.
+#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0 - No channel trigger was generated.
+ * - 1 - A channel trigger was generated.
+ */
+//@{
+#define BP_FTM_EXTTRIG_TRIGF (7U)          //!< Bit position for FTM_EXTTRIG_TRIGF.
+#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) //!< Bit mask for FTM_EXTTRIG_TRIGF.
+#define BS_FTM_EXTTRIG_TRIGF (1U)          //!< Bit field size in bits for FTM_EXTTRIG_TRIGF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_TRIGF field.
+#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_POL - Channels Polarity
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+typedef union _hw_ftm_pol
+{
+    uint32_t U;
+    struct _hw_ftm_pol_bitfields
+    {
+        uint32_t POL0 : 1;             //!< [0] Channel 0 Polarity
+        uint32_t POL1 : 1;             //!< [1] Channel 1 Polarity
+        uint32_t POL2 : 1;             //!< [2] Channel 2 Polarity
+        uint32_t POL3 : 1;             //!< [3] Channel 3 Polarity
+        uint32_t POL4 : 1;             //!< [4] Channel 4 Polarity
+        uint32_t POL5 : 1;             //!< [5] Channel 5 Polarity
+        uint32_t POL6 : 1;             //!< [6] Channel 6 Polarity
+        uint32_t POL7 : 1;             //!< [7] Channel 7 Polarity
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_pol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+//@{
+#define HW_FTM_POL_ADDR(x)       (REGS_FTM_BASE(x) + 0x70U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_POL(x)            (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
+#define HW_FTM_POL_RD(x)         (HW_FTM_POL(x).U)
+#define HW_FTM_POL_WR(x, v)      (HW_FTM_POL(x).U = (v))
+#define HW_FTM_POL_SET(x, v)     (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) |  (v)))
+#define HW_FTM_POL_CLR(x, v)     (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
+#define HW_FTM_POL_TOG(x, v)     (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL0      (0U)          //!< Bit position for FTM_POL_POL0.
+#define BM_FTM_POL_POL0      (0x00000001U) //!< Bit mask for FTM_POL_POL0.
+#define BS_FTM_POL_POL0      (1U)          //!< Bit field size in bits for FTM_POL_POL0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL0 field.
+#define BR_FTM_POL_POL0(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL0.
+#define BF_FTM_POL_POL0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL0), uint32_t) & BM_FTM_POL_POL0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL0 field to a new value.
+#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL1      (1U)          //!< Bit position for FTM_POL_POL1.
+#define BM_FTM_POL_POL1      (0x00000002U) //!< Bit mask for FTM_POL_POL1.
+#define BS_FTM_POL_POL1      (1U)          //!< Bit field size in bits for FTM_POL_POL1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL1 field.
+#define BR_FTM_POL_POL1(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL1.
+#define BF_FTM_POL_POL1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL1), uint32_t) & BM_FTM_POL_POL1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL1 field to a new value.
+#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL2      (2U)          //!< Bit position for FTM_POL_POL2.
+#define BM_FTM_POL_POL2      (0x00000004U) //!< Bit mask for FTM_POL_POL2.
+#define BS_FTM_POL_POL2      (1U)          //!< Bit field size in bits for FTM_POL_POL2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL2 field.
+#define BR_FTM_POL_POL2(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL2.
+#define BF_FTM_POL_POL2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL2), uint32_t) & BM_FTM_POL_POL2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL2 field to a new value.
+#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL3      (3U)          //!< Bit position for FTM_POL_POL3.
+#define BM_FTM_POL_POL3      (0x00000008U) //!< Bit mask for FTM_POL_POL3.
+#define BS_FTM_POL_POL3      (1U)          //!< Bit field size in bits for FTM_POL_POL3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL3 field.
+#define BR_FTM_POL_POL3(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL3.
+#define BF_FTM_POL_POL3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL3), uint32_t) & BM_FTM_POL_POL3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL3 field to a new value.
+#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL4      (4U)          //!< Bit position for FTM_POL_POL4.
+#define BM_FTM_POL_POL4      (0x00000010U) //!< Bit mask for FTM_POL_POL4.
+#define BS_FTM_POL_POL4      (1U)          //!< Bit field size in bits for FTM_POL_POL4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL4 field.
+#define BR_FTM_POL_POL4(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL4.
+#define BF_FTM_POL_POL4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL4), uint32_t) & BM_FTM_POL_POL4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL4 field to a new value.
+#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL5      (5U)          //!< Bit position for FTM_POL_POL5.
+#define BM_FTM_POL_POL5      (0x00000020U) //!< Bit mask for FTM_POL_POL5.
+#define BS_FTM_POL_POL5      (1U)          //!< Bit field size in bits for FTM_POL_POL5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL5 field.
+#define BR_FTM_POL_POL5(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL5.
+#define BF_FTM_POL_POL5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL5), uint32_t) & BM_FTM_POL_POL5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL5 field to a new value.
+#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL6      (6U)          //!< Bit position for FTM_POL_POL6.
+#define BM_FTM_POL_POL6      (0x00000040U) //!< Bit mask for FTM_POL_POL6.
+#define BS_FTM_POL_POL6      (1U)          //!< Bit field size in bits for FTM_POL_POL6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL6 field.
+#define BR_FTM_POL_POL6(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL6.
+#define BF_FTM_POL_POL6(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL6), uint32_t) & BM_FTM_POL_POL6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL6 field to a new value.
+#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL7      (7U)          //!< Bit position for FTM_POL_POL7.
+#define BM_FTM_POL_POL7      (0x00000080U) //!< Bit mask for FTM_POL_POL7.
+#define BS_FTM_POL_POL7      (1U)          //!< Bit field size in bits for FTM_POL_POL7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL7 field.
+#define BR_FTM_POL_POL7(x)   (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL7.
+#define BF_FTM_POL_POL7(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL7), uint32_t) & BM_FTM_POL_POL7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL7 field to a new value.
+#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FMS - Fault Mode Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+typedef union _hw_ftm_fms
+{
+    uint32_t U;
+    struct _hw_ftm_fms_bitfields
+    {
+        uint32_t FAULTF0 : 1;          //!< [0] Fault Detection Flag 0
+        uint32_t FAULTF1 : 1;          //!< [1] Fault Detection Flag 1
+        uint32_t FAULTF2 : 1;          //!< [2] Fault Detection Flag 2
+        uint32_t FAULTF3 : 1;          //!< [3] Fault Detection Flag 3
+        uint32_t RESERVED0 : 1;        //!< [4]
+        uint32_t FAULTIN : 1;          //!< [5] Fault Inputs
+        uint32_t WPEN : 1;             //!< [6] Write Protection Enable
+        uint32_t FAULTF : 1;           //!< [7] Fault Detection Flag
+        uint32_t RESERVED1 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_fms_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+//@{
+#define HW_FTM_FMS_ADDR(x)       (REGS_FTM_BASE(x) + 0x74U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FMS(x)            (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
+#define HW_FTM_FMS_RD(x)         (HW_FTM_FMS(x).U)
+#define HW_FTM_FMS_WR(x, v)      (HW_FTM_FMS(x).U = (v))
+#define HW_FTM_FMS_SET(x, v)     (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) |  (v)))
+#define HW_FTM_FMS_CLR(x, v)     (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
+#define HW_FTM_FMS_TOG(x, v)     (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF0   (0U)          //!< Bit position for FTM_FMS_FAULTF0.
+#define BM_FTM_FMS_FAULTF0   (0x00000001U) //!< Bit mask for FTM_FMS_FAULTF0.
+#define BS_FTM_FMS_FAULTF0   (1U)          //!< Bit field size in bits for FTM_FMS_FAULTF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF0 field.
+#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF1   (1U)          //!< Bit position for FTM_FMS_FAULTF1.
+#define BM_FTM_FMS_FAULTF1   (0x00000002U) //!< Bit mask for FTM_FMS_FAULTF1.
+#define BS_FTM_FMS_FAULTF1   (1U)          //!< Bit field size in bits for FTM_FMS_FAULTF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF1 field.
+#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF2   (2U)          //!< Bit position for FTM_FMS_FAULTF2.
+#define BM_FTM_FMS_FAULTF2   (0x00000004U) //!< Bit mask for FTM_FMS_FAULTF2.
+#define BS_FTM_FMS_FAULTF2   (1U)          //!< Bit field size in bits for FTM_FMS_FAULTF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF2 field.
+#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF3   (3U)          //!< Bit position for FTM_FMS_FAULTF3.
+#define BM_FTM_FMS_FAULTF3   (0x00000008U) //!< Bit mask for FTM_FMS_FAULTF3.
+#define BS_FTM_FMS_FAULTF3   (1U)          //!< Bit field size in bits for FTM_FMS_FAULTF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF3 field.
+#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0 - The logic OR of the enabled fault inputs is 0.
+ * - 1 - The logic OR of the enabled fault inputs is 1.
+ */
+//@{
+#define BP_FTM_FMS_FAULTIN   (5U)          //!< Bit position for FTM_FMS_FAULTIN.
+#define BM_FTM_FMS_FAULTIN   (0x00000020U) //!< Bit mask for FTM_FMS_FAULTIN.
+#define BS_FTM_FMS_FAULTIN   (1U)          //!< Bit field size in bits for FTM_FMS_FAULTIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTIN field.
+#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0 - Write protection is disabled. Write protected bits can be written.
+ * - 1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+//@{
+#define BP_FTM_FMS_WPEN      (6U)          //!< Bit position for FTM_FMS_WPEN.
+#define BM_FTM_FMS_WPEN      (0x00000040U) //!< Bit mask for FTM_FMS_WPEN.
+#define BS_FTM_FMS_WPEN      (1U)          //!< Bit field size in bits for FTM_FMS_WPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_WPEN field.
+#define BR_FTM_FMS_WPEN(x)   (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
+#endif
+
+//! @brief Format value for bitfield FTM_FMS_WPEN.
+#define BF_FTM_FMS_WPEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FMS_WPEN), uint32_t) & BM_FTM_FMS_WPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPEN field to a new value.
+#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0 - No fault condition was detected.
+ * - 1 - A fault condition was detected.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF    (7U)          //!< Bit position for FTM_FMS_FAULTF.
+#define BM_FTM_FMS_FAULTF    (0x00000080U) //!< Bit mask for FTM_FMS_FAULTF.
+#define BS_FTM_FMS_FAULTF    (1U)          //!< Bit field size in bits for FTM_FMS_FAULTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF field.
+#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FILTER - Input Capture Filter Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+typedef union _hw_ftm_filter
+{
+    uint32_t U;
+    struct _hw_ftm_filter_bitfields
+    {
+        uint32_t CH0FVAL : 4;          //!< [3:0] Channel 0 Input Filter
+        uint32_t CH1FVAL : 4;          //!< [7:4] Channel 1 Input Filter
+        uint32_t CH2FVAL : 4;          //!< [11:8] Channel 2 Input Filter
+        uint32_t CH3FVAL : 4;          //!< [15:12] Channel 3 Input Filter
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_ftm_filter_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+//@{
+#define HW_FTM_FILTER_ADDR(x)    (REGS_FTM_BASE(x) + 0x78U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FILTER(x)         (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
+#define HW_FTM_FILTER_RD(x)      (HW_FTM_FILTER(x).U)
+#define HW_FTM_FILTER_WR(x, v)   (HW_FTM_FILTER(x).U = (v))
+#define HW_FTM_FILTER_SET(x, v)  (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) |  (v)))
+#define HW_FTM_FILTER_CLR(x, v)  (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
+#define HW_FTM_FILTER_TOG(x, v)  (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH0FVAL (0U)         //!< Bit position for FTM_FILTER_CH0FVAL.
+#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) //!< Bit mask for FTM_FILTER_CH0FVAL.
+#define BS_FTM_FILTER_CH0FVAL (4U)         //!< Bit field size in bits for FTM_FILTER_CH0FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH0FVAL field.
+#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH0FVAL.
+#define BF_FTM_FILTER_CH0FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH0FVAL), uint32_t) & BM_FTM_FILTER_CH0FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0FVAL field to a new value.
+#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH1FVAL (4U)         //!< Bit position for FTM_FILTER_CH1FVAL.
+#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) //!< Bit mask for FTM_FILTER_CH1FVAL.
+#define BS_FTM_FILTER_CH1FVAL (4U)         //!< Bit field size in bits for FTM_FILTER_CH1FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH1FVAL field.
+#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH1FVAL.
+#define BF_FTM_FILTER_CH1FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH1FVAL), uint32_t) & BM_FTM_FILTER_CH1FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1FVAL field to a new value.
+#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH2FVAL (8U)         //!< Bit position for FTM_FILTER_CH2FVAL.
+#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) //!< Bit mask for FTM_FILTER_CH2FVAL.
+#define BS_FTM_FILTER_CH2FVAL (4U)         //!< Bit field size in bits for FTM_FILTER_CH2FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH2FVAL field.
+#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH2FVAL.
+#define BF_FTM_FILTER_CH2FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH2FVAL), uint32_t) & BM_FTM_FILTER_CH2FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2FVAL field to a new value.
+#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH3FVAL (12U)        //!< Bit position for FTM_FILTER_CH3FVAL.
+#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) //!< Bit mask for FTM_FILTER_CH3FVAL.
+#define BS_FTM_FILTER_CH3FVAL (4U)         //!< Bit field size in bits for FTM_FILTER_CH3FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH3FVAL field.
+#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH3FVAL.
+#define BF_FTM_FILTER_CH3FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH3FVAL), uint32_t) & BM_FTM_FILTER_CH3FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3FVAL field to a new value.
+#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FLTCTRL - Fault Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+typedef union _hw_ftm_fltctrl
+{
+    uint32_t U;
+    struct _hw_ftm_fltctrl_bitfields
+    {
+        uint32_t FAULT0EN : 1;         //!< [0] Fault Input 0 Enable
+        uint32_t FAULT1EN : 1;         //!< [1] Fault Input 1 Enable
+        uint32_t FAULT2EN : 1;         //!< [2] Fault Input 2 Enable
+        uint32_t FAULT3EN : 1;         //!< [3] Fault Input 3 Enable
+        uint32_t FFLTR0EN : 1;         //!< [4] Fault Input 0 Filter Enable
+        uint32_t FFLTR1EN : 1;         //!< [5] Fault Input 1 Filter Enable
+        uint32_t FFLTR2EN : 1;         //!< [6] Fault Input 2 Filter Enable
+        uint32_t FFLTR3EN : 1;         //!< [7] Fault Input 3 Filter Enable
+        uint32_t FFVAL : 4;            //!< [11:8] Fault Input Filter
+        uint32_t RESERVED0 : 20;       //!< [31:12]
+    } B;
+} hw_ftm_fltctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+//@{
+#define HW_FTM_FLTCTRL_ADDR(x)   (REGS_FTM_BASE(x) + 0x7CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FLTCTRL(x)        (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
+#define HW_FTM_FLTCTRL_RD(x)     (HW_FTM_FLTCTRL(x).U)
+#define HW_FTM_FLTCTRL_WR(x, v)  (HW_FTM_FLTCTRL(x).U = (v))
+#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) |  (v)))
+#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
+#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT0EN (0U)       //!< Bit position for FTM_FLTCTRL_FAULT0EN.
+#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) //!< Bit mask for FTM_FLTCTRL_FAULT0EN.
+#define BS_FTM_FLTCTRL_FAULT0EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field.
+#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN.
+#define BF_FTM_FLTCTRL_FAULT0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT0EN), uint32_t) & BM_FTM_FLTCTRL_FAULT0EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT0EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT1EN (1U)       //!< Bit position for FTM_FLTCTRL_FAULT1EN.
+#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) //!< Bit mask for FTM_FLTCTRL_FAULT1EN.
+#define BS_FTM_FLTCTRL_FAULT1EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field.
+#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN.
+#define BF_FTM_FLTCTRL_FAULT1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT1EN), uint32_t) & BM_FTM_FLTCTRL_FAULT1EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT1EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT2EN (2U)       //!< Bit position for FTM_FLTCTRL_FAULT2EN.
+#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) //!< Bit mask for FTM_FLTCTRL_FAULT2EN.
+#define BS_FTM_FLTCTRL_FAULT2EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field.
+#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN.
+#define BF_FTM_FLTCTRL_FAULT2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT2EN), uint32_t) & BM_FTM_FLTCTRL_FAULT2EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT2EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT3EN (3U)       //!< Bit position for FTM_FLTCTRL_FAULT3EN.
+#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) //!< Bit mask for FTM_FLTCTRL_FAULT3EN.
+#define BS_FTM_FLTCTRL_FAULT3EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field.
+#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN.
+#define BF_FTM_FLTCTRL_FAULT3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT3EN), uint32_t) & BM_FTM_FLTCTRL_FAULT3EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT3EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR0EN (4U)       //!< Bit position for FTM_FLTCTRL_FFLTR0EN.
+#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) //!< Bit mask for FTM_FLTCTRL_FFLTR0EN.
+#define BS_FTM_FLTCTRL_FFLTR0EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field.
+#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN.
+#define BF_FTM_FLTCTRL_FFLTR0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR0EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR0EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR0EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR1EN (5U)       //!< Bit position for FTM_FLTCTRL_FFLTR1EN.
+#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) //!< Bit mask for FTM_FLTCTRL_FFLTR1EN.
+#define BS_FTM_FLTCTRL_FFLTR1EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field.
+#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN.
+#define BF_FTM_FLTCTRL_FFLTR1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR1EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR1EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR1EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR2EN (6U)       //!< Bit position for FTM_FLTCTRL_FFLTR2EN.
+#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) //!< Bit mask for FTM_FLTCTRL_FFLTR2EN.
+#define BS_FTM_FLTCTRL_FFLTR2EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field.
+#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN.
+#define BF_FTM_FLTCTRL_FFLTR2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR2EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR2EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR2EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR3EN (7U)       //!< Bit position for FTM_FLTCTRL_FFLTR3EN.
+#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) //!< Bit mask for FTM_FLTCTRL_FFLTR3EN.
+#define BS_FTM_FLTCTRL_FFLTR3EN (1U)       //!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field.
+#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN.
+#define BF_FTM_FLTCTRL_FFLTR3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR3EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR3EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR3EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFVAL (8U)          //!< Bit position for FTM_FLTCTRL_FFVAL.
+#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) //!< Bit mask for FTM_FLTCTRL_FFVAL.
+#define BS_FTM_FLTCTRL_FFVAL (4U)          //!< Bit field size in bits for FTM_FLTCTRL_FFVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFVAL field.
+#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFVAL.
+#define BF_FTM_FLTCTRL_FFVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFVAL), uint32_t) & BM_FTM_FLTCTRL_FFVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFVAL field to a new value.
+#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_QDCTRL - Quadrature Decoder Control And Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+typedef union _hw_ftm_qdctrl
+{
+    uint32_t U;
+    struct _hw_ftm_qdctrl_bitfields
+    {
+        uint32_t QUADEN : 1;           //!< [0] Quadrature Decoder Mode Enable
+        uint32_t TOFDIR : 1;           //!< [1] Timer Overflow Direction In Quadrature
+                                       //! Decoder Mode
+        uint32_t QUADIR : 1;           //!< [2] FTM Counter Direction In Quadrature
+                                       //! Decoder Mode
+        uint32_t QUADMODE : 1;         //!< [3] Quadrature Decoder Mode
+        uint32_t PHBPOL : 1;           //!< [4] Phase B Input Polarity
+        uint32_t PHAPOL : 1;           //!< [5] Phase A Input Polarity
+        uint32_t PHBFLTREN : 1;        //!< [6] Phase B Input Filter Enable
+        uint32_t PHAFLTREN : 1;        //!< [7] Phase A Input Filter Enable
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_ftm_qdctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+//@{
+#define HW_FTM_QDCTRL_ADDR(x)    (REGS_FTM_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_QDCTRL(x)         (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
+#define HW_FTM_QDCTRL_RD(x)      (HW_FTM_QDCTRL(x).U)
+#define HW_FTM_QDCTRL_WR(x, v)   (HW_FTM_QDCTRL(x).U = (v))
+#define HW_FTM_QDCTRL_SET(x, v)  (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) |  (v)))
+#define HW_FTM_QDCTRL_CLR(x, v)  (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
+#define HW_FTM_QDCTRL_TOG(x, v)  (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Quadrature Decoder mode is disabled.
+ * - 1 - Quadrature Decoder mode is enabled.
+ */
+//@{
+#define BP_FTM_QDCTRL_QUADEN (0U)          //!< Bit position for FTM_QDCTRL_QUADEN.
+#define BM_FTM_QDCTRL_QUADEN (0x00000001U) //!< Bit mask for FTM_QDCTRL_QUADEN.
+#define BS_FTM_QDCTRL_QUADEN (1U)          //!< Bit field size in bits for FTM_QDCTRL_QUADEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_QUADEN field.
+#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_QUADEN.
+#define BF_FTM_QDCTRL_QUADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADEN), uint32_t) & BM_FTM_QDCTRL_QUADEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the QUADEN field to a new value.
+#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register) to
+ *     its maximum value (MOD register).
+ * - 1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+//@{
+#define BP_FTM_QDCTRL_TOFDIR (1U)          //!< Bit position for FTM_QDCTRL_TOFDIR.
+#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) //!< Bit mask for FTM_QDCTRL_TOFDIR.
+#define BS_FTM_QDCTRL_TOFDIR (1U)          //!< Bit field size in bits for FTM_QDCTRL_TOFDIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_TOFDIR field.
+#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0 - Counting direction is decreasing (FTM counter decrement).
+ * - 1 - Counting direction is increasing (FTM counter increment).
+ */
+//@{
+#define BP_FTM_QDCTRL_QUADIR (2U)          //!< Bit position for FTM_QDCTRL_QUADIR.
+#define BM_FTM_QDCTRL_QUADIR (0x00000004U) //!< Bit mask for FTM_QDCTRL_QUADIR.
+#define BS_FTM_QDCTRL_QUADIR (1U)          //!< Bit field size in bits for FTM_QDCTRL_QUADIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_QUADIR field.
+#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0 - Phase A and phase B encoding mode.
+ * - 1 - Count and direction encoding mode.
+ */
+//@{
+#define BP_FTM_QDCTRL_QUADMODE (3U)        //!< Bit position for FTM_QDCTRL_QUADMODE.
+#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) //!< Bit mask for FTM_QDCTRL_QUADMODE.
+#define BS_FTM_QDCTRL_QUADMODE (1U)        //!< Bit field size in bits for FTM_QDCTRL_QUADMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_QUADMODE field.
+#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_QUADMODE.
+#define BF_FTM_QDCTRL_QUADMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADMODE), uint32_t) & BM_FTM_QDCTRL_QUADMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the QUADMODE field to a new value.
+#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
+ *     the rising and falling edges of this signal.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHBPOL (4U)          //!< Bit position for FTM_QDCTRL_PHBPOL.
+#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) //!< Bit mask for FTM_QDCTRL_PHBPOL.
+#define BS_FTM_QDCTRL_PHBPOL (1U)          //!< Bit field size in bits for FTM_QDCTRL_PHBPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHBPOL field.
+#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHBPOL.
+#define BF_FTM_QDCTRL_PHBPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBPOL), uint32_t) & BM_FTM_QDCTRL_PHBPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHBPOL field to a new value.
+#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
+ *     the rising and falling edges of this signal.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHAPOL (5U)          //!< Bit position for FTM_QDCTRL_PHAPOL.
+#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) //!< Bit mask for FTM_QDCTRL_PHAPOL.
+#define BS_FTM_QDCTRL_PHAPOL (1U)          //!< Bit field size in bits for FTM_QDCTRL_PHAPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHAPOL field.
+#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHAPOL.
+#define BF_FTM_QDCTRL_PHAPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAPOL), uint32_t) & BM_FTM_QDCTRL_PHAPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHAPOL field to a new value.
+#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0 - Phase B input filter is disabled.
+ * - 1 - Phase B input filter is enabled.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHBFLTREN (6U)       //!< Bit position for FTM_QDCTRL_PHBFLTREN.
+#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) //!< Bit mask for FTM_QDCTRL_PHBFLTREN.
+#define BS_FTM_QDCTRL_PHBFLTREN (1U)       //!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field.
+#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN.
+#define BF_FTM_QDCTRL_PHBFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBFLTREN), uint32_t) & BM_FTM_QDCTRL_PHBFLTREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHBFLTREN field to a new value.
+#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0 - Phase A input filter is disabled.
+ * - 1 - Phase A input filter is enabled.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHAFLTREN (7U)       //!< Bit position for FTM_QDCTRL_PHAFLTREN.
+#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) //!< Bit mask for FTM_QDCTRL_PHAFLTREN.
+#define BS_FTM_QDCTRL_PHAFLTREN (1U)       //!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field.
+#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN.
+#define BF_FTM_QDCTRL_PHAFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAFLTREN), uint32_t) & BM_FTM_QDCTRL_PHAFLTREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHAFLTREN field to a new value.
+#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CONF - Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+typedef union _hw_ftm_conf
+{
+    uint32_t U;
+    struct _hw_ftm_conf_bitfields
+    {
+        uint32_t NUMTOF : 5;           //!< [4:0] TOF Frequency
+        uint32_t RESERVED0 : 1;        //!< [5]
+        uint32_t BDMMODE : 2;          //!< [7:6] BDM Mode
+        uint32_t RESERVED1 : 1;        //!< [8]
+        uint32_t GTBEEN : 1;           //!< [9] Global Time Base Enable
+        uint32_t GTBEOUT : 1;          //!< [10] Global Time Base Output
+        uint32_t RESERVED2 : 21;       //!< [31:11]
+    } B;
+} hw_ftm_conf_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+//@{
+#define HW_FTM_CONF_ADDR(x)      (REGS_FTM_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CONF(x)           (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
+#define HW_FTM_CONF_RD(x)        (HW_FTM_CONF(x).U)
+#define HW_FTM_CONF_WR(x, v)     (HW_FTM_CONF(x).U = (v))
+#define HW_FTM_CONF_SET(x, v)    (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) |  (v)))
+#define HW_FTM_CONF_CLR(x, v)    (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
+#define HW_FTM_CONF_TOG(x, v)    (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+//@{
+#define BP_FTM_CONF_NUMTOF   (0U)          //!< Bit position for FTM_CONF_NUMTOF.
+#define BM_FTM_CONF_NUMTOF   (0x0000001FU) //!< Bit mask for FTM_CONF_NUMTOF.
+#define BS_FTM_CONF_NUMTOF   (5U)          //!< Bit field size in bits for FTM_CONF_NUMTOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_NUMTOF field.
+#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_NUMTOF.
+#define BF_FTM_CONF_NUMTOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_NUMTOF), uint32_t) & BM_FTM_CONF_NUMTOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NUMTOF field to a new value.
+#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+//@{
+#define BP_FTM_CONF_BDMMODE  (6U)          //!< Bit position for FTM_CONF_BDMMODE.
+#define BM_FTM_CONF_BDMMODE  (0x000000C0U) //!< Bit mask for FTM_CONF_BDMMODE.
+#define BS_FTM_CONF_BDMMODE  (2U)          //!< Bit field size in bits for FTM_CONF_BDMMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_BDMMODE field.
+#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_BDMMODE.
+#define BF_FTM_CONF_BDMMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_BDMMODE), uint32_t) & BM_FTM_CONF_BDMMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDMMODE field to a new value.
+#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0 - Use of an external global time base is disabled.
+ * - 1 - Use of an external global time base is enabled.
+ */
+//@{
+#define BP_FTM_CONF_GTBEEN   (9U)          //!< Bit position for FTM_CONF_GTBEEN.
+#define BM_FTM_CONF_GTBEEN   (0x00000200U) //!< Bit mask for FTM_CONF_GTBEEN.
+#define BS_FTM_CONF_GTBEEN   (1U)          //!< Bit field size in bits for FTM_CONF_GTBEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_GTBEEN field.
+#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_GTBEEN.
+#define BF_FTM_CONF_GTBEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEEN), uint32_t) & BM_FTM_CONF_GTBEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTBEEN field to a new value.
+#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0 - A global time base signal generation is disabled.
+ * - 1 - A global time base signal generation is enabled.
+ */
+//@{
+#define BP_FTM_CONF_GTBEOUT  (10U)         //!< Bit position for FTM_CONF_GTBEOUT.
+#define BM_FTM_CONF_GTBEOUT  (0x00000400U) //!< Bit mask for FTM_CONF_GTBEOUT.
+#define BS_FTM_CONF_GTBEOUT  (1U)          //!< Bit field size in bits for FTM_CONF_GTBEOUT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_GTBEOUT field.
+#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_GTBEOUT.
+#define BF_FTM_CONF_GTBEOUT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEOUT), uint32_t) & BM_FTM_CONF_GTBEOUT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTBEOUT field to a new value.
+#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FLTPOL - FTM Fault Input Polarity
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+typedef union _hw_ftm_fltpol
+{
+    uint32_t U;
+    struct _hw_ftm_fltpol_bitfields
+    {
+        uint32_t FLT0POL : 1;          //!< [0] Fault Input 0 Polarity
+        uint32_t FLT1POL : 1;          //!< [1] Fault Input 1 Polarity
+        uint32_t FLT2POL : 1;          //!< [2] Fault Input 2 Polarity
+        uint32_t FLT3POL : 1;          //!< [3] Fault Input 3 Polarity
+        uint32_t RESERVED0 : 28;       //!< [31:4]
+    } B;
+} hw_ftm_fltpol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+//@{
+#define HW_FTM_FLTPOL_ADDR(x)    (REGS_FTM_BASE(x) + 0x88U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FLTPOL(x)         (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
+#define HW_FTM_FLTPOL_RD(x)      (HW_FTM_FLTPOL(x).U)
+#define HW_FTM_FLTPOL_WR(x, v)   (HW_FTM_FLTPOL(x).U = (v))
+#define HW_FTM_FLTPOL_SET(x, v)  (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) |  (v)))
+#define HW_FTM_FLTPOL_CLR(x, v)  (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
+#define HW_FTM_FLTPOL_TOG(x, v)  (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT0POL (0U)         //!< Bit position for FTM_FLTPOL_FLT0POL.
+#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) //!< Bit mask for FTM_FLTPOL_FLT0POL.
+#define BS_FTM_FLTPOL_FLT0POL (1U)         //!< Bit field size in bits for FTM_FLTPOL_FLT0POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT0POL field.
+#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT0POL.
+#define BF_FTM_FLTPOL_FLT0POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT0POL), uint32_t) & BM_FTM_FLTPOL_FLT0POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT0POL field to a new value.
+#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT1POL (1U)         //!< Bit position for FTM_FLTPOL_FLT1POL.
+#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) //!< Bit mask for FTM_FLTPOL_FLT1POL.
+#define BS_FTM_FLTPOL_FLT1POL (1U)         //!< Bit field size in bits for FTM_FLTPOL_FLT1POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT1POL field.
+#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT1POL.
+#define BF_FTM_FLTPOL_FLT1POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT1POL), uint32_t) & BM_FTM_FLTPOL_FLT1POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT1POL field to a new value.
+#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT2POL (2U)         //!< Bit position for FTM_FLTPOL_FLT2POL.
+#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) //!< Bit mask for FTM_FLTPOL_FLT2POL.
+#define BS_FTM_FLTPOL_FLT2POL (1U)         //!< Bit field size in bits for FTM_FLTPOL_FLT2POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT2POL field.
+#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT2POL.
+#define BF_FTM_FLTPOL_FLT2POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT2POL), uint32_t) & BM_FTM_FLTPOL_FLT2POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT2POL field to a new value.
+#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT3POL (3U)         //!< Bit position for FTM_FLTPOL_FLT3POL.
+#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) //!< Bit mask for FTM_FLTPOL_FLT3POL.
+#define BS_FTM_FLTPOL_FLT3POL (1U)         //!< Bit field size in bits for FTM_FLTPOL_FLT3POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT3POL field.
+#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT3POL.
+#define BF_FTM_FLTPOL_FLT3POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT3POL), uint32_t) & BM_FTM_FLTPOL_FLT3POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT3POL field to a new value.
+#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SYNCONF - Synchronization Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+typedef union _hw_ftm_synconf
+{
+    uint32_t U;
+    struct _hw_ftm_synconf_bitfields
+    {
+        uint32_t HWTRIGMODE : 1;       //!< [0] Hardware Trigger Mode
+        uint32_t RESERVED0 : 1;        //!< [1]
+        uint32_t CNTINC : 1;           //!< [2] CNTIN Register Synchronization
+        uint32_t RESERVED1 : 1;        //!< [3]
+        uint32_t INVC : 1;             //!< [4] INVCTRL Register Synchronization
+        uint32_t SWOC : 1;             //!< [5] SWOCTRL Register Synchronization
+        uint32_t RESERVED2 : 1;        //!< [6]
+        uint32_t SYNCMODE : 1;         //!< [7] Synchronization Mode
+        uint32_t SWRSTCNT : 1;         //!< [8]
+        uint32_t SWWRBUF : 1;          //!< [9]
+        uint32_t SWOM : 1;             //!< [10]
+        uint32_t SWINVC : 1;           //!< [11]
+        uint32_t SWSOC : 1;            //!< [12]
+        uint32_t RESERVED3 : 3;        //!< [15:13]
+        uint32_t HWRSTCNT : 1;         //!< [16]
+        uint32_t HWWRBUF : 1;          //!< [17]
+        uint32_t HWOM : 1;             //!< [18]
+        uint32_t HWINVC : 1;           //!< [19]
+        uint32_t HWSOC : 1;            //!< [20]
+        uint32_t RESERVED4 : 11;       //!< [31:21]
+    } B;
+} hw_ftm_synconf_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+//@{
+#define HW_FTM_SYNCONF_ADDR(x)   (REGS_FTM_BASE(x) + 0x8CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SYNCONF(x)        (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
+#define HW_FTM_SYNCONF_RD(x)     (HW_FTM_SYNCONF(x).U)
+#define HW_FTM_SYNCONF_WR(x, v)  (HW_FTM_SYNCONF(x).U = (v))
+#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) |  (v)))
+#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
+#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
+ *     j = 0, 1,2.
+ * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWTRIGMODE (0U)     //!< Bit position for FTM_SYNCONF_HWTRIGMODE.
+#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) //!< Bit mask for FTM_SYNCONF_HWTRIGMODE.
+#define BS_FTM_SYNCONF_HWTRIGMODE (1U)     //!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field.
+#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE.
+#define BF_FTM_SYNCONF_HWTRIGMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWTRIGMODE), uint32_t) & BM_FTM_SYNCONF_HWTRIGMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWTRIGMODE field to a new value.
+#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0 - CNTIN register is updated with its buffer value at all rising edges of
+ *     system clock.
+ * - 1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_CNTINC (2U)         //!< Bit position for FTM_SYNCONF_CNTINC.
+#define BM_FTM_SYNCONF_CNTINC (0x00000004U) //!< Bit mask for FTM_SYNCONF_CNTINC.
+#define BS_FTM_SYNCONF_CNTINC (1U)         //!< Bit field size in bits for FTM_SYNCONF_CNTINC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_CNTINC field.
+#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_CNTINC.
+#define BF_FTM_SYNCONF_CNTINC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_CNTINC), uint32_t) & BM_FTM_SYNCONF_CNTINC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTINC field to a new value.
+#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_INVC  (4U)          //!< Bit position for FTM_SYNCONF_INVC.
+#define BM_FTM_SYNCONF_INVC  (0x00000010U) //!< Bit mask for FTM_SYNCONF_INVC.
+#define BS_FTM_SYNCONF_INVC  (1U)          //!< Bit field size in bits for FTM_SYNCONF_INVC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_INVC field.
+#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_INVC.
+#define BF_FTM_SYNCONF_INVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_INVC), uint32_t) & BM_FTM_SYNCONF_INVC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INVC field to a new value.
+#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWOC  (5U)          //!< Bit position for FTM_SYNCONF_SWOC.
+#define BM_FTM_SYNCONF_SWOC  (0x00000020U) //!< Bit mask for FTM_SYNCONF_SWOC.
+#define BS_FTM_SYNCONF_SWOC  (1U)          //!< Bit field size in bits for FTM_SYNCONF_SWOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWOC field.
+#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWOC.
+#define BF_FTM_SYNCONF_SWOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOC), uint32_t) & BM_FTM_SYNCONF_SWOC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWOC field to a new value.
+#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0 - Legacy PWM synchronization is selected.
+ * - 1 - Enhanced PWM synchronization is selected.
+ */
+//@{
+#define BP_FTM_SYNCONF_SYNCMODE (7U)       //!< Bit position for FTM_SYNCONF_SYNCMODE.
+#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) //!< Bit mask for FTM_SYNCONF_SYNCMODE.
+#define BS_FTM_SYNCONF_SYNCMODE (1U)       //!< Bit field size in bits for FTM_SYNCONF_SYNCMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SYNCMODE field.
+#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE.
+#define BF_FTM_SYNCONF_SYNCMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SYNCMODE), uint32_t) & BM_FTM_SYNCONF_SYNCMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCMODE field to a new value.
+#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the FTM counter synchronization.
+ * - 1 - The software trigger activates the FTM counter synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWRSTCNT (8U)       //!< Bit position for FTM_SYNCONF_SWRSTCNT.
+#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) //!< Bit mask for FTM_SYNCONF_SWRSTCNT.
+#define BS_FTM_SYNCONF_SWRSTCNT (1U)       //!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field.
+#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT.
+#define BF_FTM_SYNCONF_SWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWRSTCNT), uint32_t) & BM_FTM_SYNCONF_SWRSTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWRSTCNT field to a new value.
+#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWWRBUF (9U)        //!< Bit position for FTM_SYNCONF_SWWRBUF.
+#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) //!< Bit mask for FTM_SYNCONF_SWWRBUF.
+#define BS_FTM_SYNCONF_SWWRBUF (1U)        //!< Bit field size in bits for FTM_SYNCONF_SWWRBUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWWRBUF field.
+#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF.
+#define BF_FTM_SYNCONF_SWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWWRBUF), uint32_t) & BM_FTM_SYNCONF_SWWRBUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWWRBUF field to a new value.
+#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 1 - The software trigger activates the OUTMASK register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWOM  (10U)         //!< Bit position for FTM_SYNCONF_SWOM.
+#define BM_FTM_SYNCONF_SWOM  (0x00000400U) //!< Bit mask for FTM_SYNCONF_SWOM.
+#define BS_FTM_SYNCONF_SWOM  (1U)          //!< Bit field size in bits for FTM_SYNCONF_SWOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWOM field.
+#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWOM.
+#define BF_FTM_SYNCONF_SWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOM), uint32_t) & BM_FTM_SYNCONF_SWOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWOM field to a new value.
+#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 1 - The software trigger activates the INVCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWINVC (11U)        //!< Bit position for FTM_SYNCONF_SWINVC.
+#define BM_FTM_SYNCONF_SWINVC (0x00000800U) //!< Bit mask for FTM_SYNCONF_SWINVC.
+#define BS_FTM_SYNCONF_SWINVC (1U)         //!< Bit field size in bits for FTM_SYNCONF_SWINVC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWINVC field.
+#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWINVC.
+#define BF_FTM_SYNCONF_SWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWINVC), uint32_t) & BM_FTM_SYNCONF_SWINVC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWINVC field to a new value.
+#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWSOC (12U)         //!< Bit position for FTM_SYNCONF_SWSOC.
+#define BM_FTM_SYNCONF_SWSOC (0x00001000U) //!< Bit mask for FTM_SYNCONF_SWSOC.
+#define BS_FTM_SYNCONF_SWSOC (1U)          //!< Bit field size in bits for FTM_SYNCONF_SWSOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWSOC field.
+#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWSOC.
+#define BF_FTM_SYNCONF_SWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWSOC), uint32_t) & BM_FTM_SYNCONF_SWSOC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWSOC field to a new value.
+#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 1 - A hardware trigger activates the FTM counter synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWRSTCNT (16U)      //!< Bit position for FTM_SYNCONF_HWRSTCNT.
+#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) //!< Bit mask for FTM_SYNCONF_HWRSTCNT.
+#define BS_FTM_SYNCONF_HWRSTCNT (1U)       //!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field.
+#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT.
+#define BF_FTM_SYNCONF_HWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWRSTCNT), uint32_t) & BM_FTM_SYNCONF_HWRSTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWRSTCNT field to a new value.
+#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWWRBUF (17U)       //!< Bit position for FTM_SYNCONF_HWWRBUF.
+#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) //!< Bit mask for FTM_SYNCONF_HWWRBUF.
+#define BS_FTM_SYNCONF_HWWRBUF (1U)        //!< Bit field size in bits for FTM_SYNCONF_HWWRBUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWWRBUF field.
+#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF.
+#define BF_FTM_SYNCONF_HWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWWRBUF), uint32_t) & BM_FTM_SYNCONF_HWWRBUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWWRBUF field to a new value.
+#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWOM  (18U)         //!< Bit position for FTM_SYNCONF_HWOM.
+#define BM_FTM_SYNCONF_HWOM  (0x00040000U) //!< Bit mask for FTM_SYNCONF_HWOM.
+#define BS_FTM_SYNCONF_HWOM  (1U)          //!< Bit field size in bits for FTM_SYNCONF_HWOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWOM field.
+#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWOM.
+#define BF_FTM_SYNCONF_HWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWOM), uint32_t) & BM_FTM_SYNCONF_HWOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWOM field to a new value.
+#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWINVC (19U)        //!< Bit position for FTM_SYNCONF_HWINVC.
+#define BM_FTM_SYNCONF_HWINVC (0x00080000U) //!< Bit mask for FTM_SYNCONF_HWINVC.
+#define BS_FTM_SYNCONF_HWINVC (1U)         //!< Bit field size in bits for FTM_SYNCONF_HWINVC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWINVC field.
+#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWINVC.
+#define BF_FTM_SYNCONF_HWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWINVC), uint32_t) & BM_FTM_SYNCONF_HWINVC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWINVC field to a new value.
+#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWSOC (20U)         //!< Bit position for FTM_SYNCONF_HWSOC.
+#define BM_FTM_SYNCONF_HWSOC (0x00100000U) //!< Bit mask for FTM_SYNCONF_HWSOC.
+#define BS_FTM_SYNCONF_HWSOC (1U)          //!< Bit field size in bits for FTM_SYNCONF_HWSOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWSOC field.
+#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWSOC.
+#define BF_FTM_SYNCONF_HWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWSOC), uint32_t) & BM_FTM_SYNCONF_HWSOC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWSOC field to a new value.
+#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_INVCTRL - FTM Inverting Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+typedef union _hw_ftm_invctrl
+{
+    uint32_t U;
+    struct _hw_ftm_invctrl_bitfields
+    {
+        uint32_t INV0EN : 1;           //!< [0] Pair Channels 0 Inverting Enable
+        uint32_t INV1EN : 1;           //!< [1] Pair Channels 1 Inverting Enable
+        uint32_t INV2EN : 1;           //!< [2] Pair Channels 2 Inverting Enable
+        uint32_t INV3EN : 1;           //!< [3] Pair Channels 3 Inverting Enable
+        uint32_t RESERVED0 : 28;       //!< [31:4]
+    } B;
+} hw_ftm_invctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+//@{
+#define HW_FTM_INVCTRL_ADDR(x)   (REGS_FTM_BASE(x) + 0x90U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_INVCTRL(x)        (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
+#define HW_FTM_INVCTRL_RD(x)     (HW_FTM_INVCTRL(x).U)
+#define HW_FTM_INVCTRL_WR(x, v)  (HW_FTM_INVCTRL(x).U = (v))
+#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) |  (v)))
+#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
+#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV0EN (0U)         //!< Bit position for FTM_INVCTRL_INV0EN.
+#define BM_FTM_INVCTRL_INV0EN (0x00000001U) //!< Bit mask for FTM_INVCTRL_INV0EN.
+#define BS_FTM_INVCTRL_INV0EN (1U)         //!< Bit field size in bits for FTM_INVCTRL_INV0EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV0EN field.
+#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV0EN.
+#define BF_FTM_INVCTRL_INV0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV0EN), uint32_t) & BM_FTM_INVCTRL_INV0EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV0EN field to a new value.
+#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV1EN (1U)         //!< Bit position for FTM_INVCTRL_INV1EN.
+#define BM_FTM_INVCTRL_INV1EN (0x00000002U) //!< Bit mask for FTM_INVCTRL_INV1EN.
+#define BS_FTM_INVCTRL_INV1EN (1U)         //!< Bit field size in bits for FTM_INVCTRL_INV1EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV1EN field.
+#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV1EN.
+#define BF_FTM_INVCTRL_INV1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV1EN), uint32_t) & BM_FTM_INVCTRL_INV1EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV1EN field to a new value.
+#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV2EN (2U)         //!< Bit position for FTM_INVCTRL_INV2EN.
+#define BM_FTM_INVCTRL_INV2EN (0x00000004U) //!< Bit mask for FTM_INVCTRL_INV2EN.
+#define BS_FTM_INVCTRL_INV2EN (1U)         //!< Bit field size in bits for FTM_INVCTRL_INV2EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV2EN field.
+#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV2EN.
+#define BF_FTM_INVCTRL_INV2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV2EN), uint32_t) & BM_FTM_INVCTRL_INV2EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV2EN field to a new value.
+#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV3EN (3U)         //!< Bit position for FTM_INVCTRL_INV3EN.
+#define BM_FTM_INVCTRL_INV3EN (0x00000008U) //!< Bit mask for FTM_INVCTRL_INV3EN.
+#define BS_FTM_INVCTRL_INV3EN (1U)         //!< Bit field size in bits for FTM_INVCTRL_INV3EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV3EN field.
+#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV3EN.
+#define BF_FTM_INVCTRL_INV3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV3EN), uint32_t) & BM_FTM_INVCTRL_INV3EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV3EN field to a new value.
+#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SWOCTRL - FTM Software Output Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+typedef union _hw_ftm_swoctrl
+{
+    uint32_t U;
+    struct _hw_ftm_swoctrl_bitfields
+    {
+        uint32_t CH0OC : 1;            //!< [0] Channel 0 Software Output Control Enable
+        uint32_t CH1OC : 1;            //!< [1] Channel 1 Software Output Control Enable
+        uint32_t CH2OC : 1;            //!< [2] Channel 2 Software Output Control Enable
+        uint32_t CH3OC : 1;            //!< [3] Channel 3 Software Output Control Enable
+        uint32_t CH4OC : 1;            //!< [4] Channel 4 Software Output Control Enable
+        uint32_t CH5OC : 1;            //!< [5] Channel 5 Software Output Control Enable
+        uint32_t CH6OC : 1;            //!< [6] Channel 6 Software Output Control Enable
+        uint32_t CH7OC : 1;            //!< [7] Channel 7 Software Output Control Enable
+        uint32_t CH0OCV : 1;           //!< [8] Channel 0 Software Output Control Value
+        uint32_t CH1OCV : 1;           //!< [9] Channel 1 Software Output Control Value
+        uint32_t CH2OCV : 1;           //!< [10] Channel 2 Software Output Control Value
+        uint32_t CH3OCV : 1;           //!< [11] Channel 3 Software Output Control Value
+        uint32_t CH4OCV : 1;           //!< [12] Channel 4 Software Output Control Value
+        uint32_t CH5OCV : 1;           //!< [13] Channel 5 Software Output Control Value
+        uint32_t CH6OCV : 1;           //!< [14] Channel 6 Software Output Control Value
+        uint32_t CH7OCV : 1;           //!< [15] Channel 7 Software Output Control Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_ftm_swoctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+//@{
+#define HW_FTM_SWOCTRL_ADDR(x)   (REGS_FTM_BASE(x) + 0x94U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SWOCTRL(x)        (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
+#define HW_FTM_SWOCTRL_RD(x)     (HW_FTM_SWOCTRL(x).U)
+#define HW_FTM_SWOCTRL_WR(x, v)  (HW_FTM_SWOCTRL(x).U = (v))
+#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) |  (v)))
+#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
+#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH0OC (0U)          //!< Bit position for FTM_SWOCTRL_CH0OC.
+#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) //!< Bit mask for FTM_SWOCTRL_CH0OC.
+#define BS_FTM_SWOCTRL_CH0OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH0OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH0OC field.
+#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH0OC.
+#define BF_FTM_SWOCTRL_CH0OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OC), uint32_t) & BM_FTM_SWOCTRL_CH0OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OC field to a new value.
+#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH1OC (1U)          //!< Bit position for FTM_SWOCTRL_CH1OC.
+#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) //!< Bit mask for FTM_SWOCTRL_CH1OC.
+#define BS_FTM_SWOCTRL_CH1OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH1OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH1OC field.
+#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH1OC.
+#define BF_FTM_SWOCTRL_CH1OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OC), uint32_t) & BM_FTM_SWOCTRL_CH1OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OC field to a new value.
+#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH2OC (2U)          //!< Bit position for FTM_SWOCTRL_CH2OC.
+#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) //!< Bit mask for FTM_SWOCTRL_CH2OC.
+#define BS_FTM_SWOCTRL_CH2OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH2OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH2OC field.
+#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH2OC.
+#define BF_FTM_SWOCTRL_CH2OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OC), uint32_t) & BM_FTM_SWOCTRL_CH2OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OC field to a new value.
+#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH3OC (3U)          //!< Bit position for FTM_SWOCTRL_CH3OC.
+#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) //!< Bit mask for FTM_SWOCTRL_CH3OC.
+#define BS_FTM_SWOCTRL_CH3OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH3OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH3OC field.
+#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH3OC.
+#define BF_FTM_SWOCTRL_CH3OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OC), uint32_t) & BM_FTM_SWOCTRL_CH3OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OC field to a new value.
+#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH4OC (4U)          //!< Bit position for FTM_SWOCTRL_CH4OC.
+#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) //!< Bit mask for FTM_SWOCTRL_CH4OC.
+#define BS_FTM_SWOCTRL_CH4OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH4OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH4OC field.
+#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH4OC.
+#define BF_FTM_SWOCTRL_CH4OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OC), uint32_t) & BM_FTM_SWOCTRL_CH4OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OC field to a new value.
+#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH5OC (5U)          //!< Bit position for FTM_SWOCTRL_CH5OC.
+#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) //!< Bit mask for FTM_SWOCTRL_CH5OC.
+#define BS_FTM_SWOCTRL_CH5OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH5OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH5OC field.
+#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH5OC.
+#define BF_FTM_SWOCTRL_CH5OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OC), uint32_t) & BM_FTM_SWOCTRL_CH5OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OC field to a new value.
+#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH6OC (6U)          //!< Bit position for FTM_SWOCTRL_CH6OC.
+#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) //!< Bit mask for FTM_SWOCTRL_CH6OC.
+#define BS_FTM_SWOCTRL_CH6OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH6OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH6OC field.
+#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH6OC.
+#define BF_FTM_SWOCTRL_CH6OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OC), uint32_t) & BM_FTM_SWOCTRL_CH6OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OC field to a new value.
+#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH7OC (7U)          //!< Bit position for FTM_SWOCTRL_CH7OC.
+#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) //!< Bit mask for FTM_SWOCTRL_CH7OC.
+#define BS_FTM_SWOCTRL_CH7OC (1U)          //!< Bit field size in bits for FTM_SWOCTRL_CH7OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH7OC field.
+#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH7OC.
+#define BF_FTM_SWOCTRL_CH7OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OC), uint32_t) & BM_FTM_SWOCTRL_CH7OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OC field to a new value.
+#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH0OCV (8U)         //!< Bit position for FTM_SWOCTRL_CH0OCV.
+#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) //!< Bit mask for FTM_SWOCTRL_CH0OCV.
+#define BS_FTM_SWOCTRL_CH0OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH0OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH0OCV field.
+#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV.
+#define BF_FTM_SWOCTRL_CH0OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OCV), uint32_t) & BM_FTM_SWOCTRL_CH0OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH1OCV (9U)         //!< Bit position for FTM_SWOCTRL_CH1OCV.
+#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) //!< Bit mask for FTM_SWOCTRL_CH1OCV.
+#define BS_FTM_SWOCTRL_CH1OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH1OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH1OCV field.
+#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV.
+#define BF_FTM_SWOCTRL_CH1OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OCV), uint32_t) & BM_FTM_SWOCTRL_CH1OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH2OCV (10U)        //!< Bit position for FTM_SWOCTRL_CH2OCV.
+#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) //!< Bit mask for FTM_SWOCTRL_CH2OCV.
+#define BS_FTM_SWOCTRL_CH2OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH2OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH2OCV field.
+#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV.
+#define BF_FTM_SWOCTRL_CH2OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OCV), uint32_t) & BM_FTM_SWOCTRL_CH2OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH3OCV (11U)        //!< Bit position for FTM_SWOCTRL_CH3OCV.
+#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) //!< Bit mask for FTM_SWOCTRL_CH3OCV.
+#define BS_FTM_SWOCTRL_CH3OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH3OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH3OCV field.
+#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV.
+#define BF_FTM_SWOCTRL_CH3OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OCV), uint32_t) & BM_FTM_SWOCTRL_CH3OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH4OCV (12U)        //!< Bit position for FTM_SWOCTRL_CH4OCV.
+#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) //!< Bit mask for FTM_SWOCTRL_CH4OCV.
+#define BS_FTM_SWOCTRL_CH4OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH4OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH4OCV field.
+#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV.
+#define BF_FTM_SWOCTRL_CH4OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OCV), uint32_t) & BM_FTM_SWOCTRL_CH4OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH5OCV (13U)        //!< Bit position for FTM_SWOCTRL_CH5OCV.
+#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) //!< Bit mask for FTM_SWOCTRL_CH5OCV.
+#define BS_FTM_SWOCTRL_CH5OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH5OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH5OCV field.
+#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV.
+#define BF_FTM_SWOCTRL_CH5OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OCV), uint32_t) & BM_FTM_SWOCTRL_CH5OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH6OCV (14U)        //!< Bit position for FTM_SWOCTRL_CH6OCV.
+#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) //!< Bit mask for FTM_SWOCTRL_CH6OCV.
+#define BS_FTM_SWOCTRL_CH6OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH6OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH6OCV field.
+#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV.
+#define BF_FTM_SWOCTRL_CH6OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OCV), uint32_t) & BM_FTM_SWOCTRL_CH6OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH7OCV (15U)        //!< Bit position for FTM_SWOCTRL_CH7OCV.
+#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) //!< Bit mask for FTM_SWOCTRL_CH7OCV.
+#define BS_FTM_SWOCTRL_CH7OCV (1U)         //!< Bit field size in bits for FTM_SWOCTRL_CH7OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH7OCV field.
+#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV.
+#define BF_FTM_SWOCTRL_CH7OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OCV), uint32_t) & BM_FTM_SWOCTRL_CH7OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_PWMLOAD - FTM PWM Load
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+typedef union _hw_ftm_pwmload
+{
+    uint32_t U;
+    struct _hw_ftm_pwmload_bitfields
+    {
+        uint32_t CH0SEL : 1;           //!< [0] Channel 0 Select
+        uint32_t CH1SEL : 1;           //!< [1] Channel 1 Select
+        uint32_t CH2SEL : 1;           //!< [2] Channel 2 Select
+        uint32_t CH3SEL : 1;           //!< [3] Channel 3 Select
+        uint32_t CH4SEL : 1;           //!< [4] Channel 4 Select
+        uint32_t CH5SEL : 1;           //!< [5] Channel 5 Select
+        uint32_t CH6SEL : 1;           //!< [6] Channel 6 Select
+        uint32_t CH7SEL : 1;           //!< [7] Channel 7 Select
+        uint32_t RESERVED0 : 1;        //!< [8]
+        uint32_t LDOK : 1;             //!< [9] Load Enable
+        uint32_t RESERVED1 : 22;       //!< [31:10]
+    } B;
+} hw_ftm_pwmload_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+//@{
+#define HW_FTM_PWMLOAD_ADDR(x)   (REGS_FTM_BASE(x) + 0x98U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_PWMLOAD(x)        (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
+#define HW_FTM_PWMLOAD_RD(x)     (HW_FTM_PWMLOAD(x).U)
+#define HW_FTM_PWMLOAD_WR(x, v)  (HW_FTM_PWMLOAD(x).U = (v))
+#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) |  (v)))
+#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
+#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH0SEL (0U)         //!< Bit position for FTM_PWMLOAD_CH0SEL.
+#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) //!< Bit mask for FTM_PWMLOAD_CH0SEL.
+#define BS_FTM_PWMLOAD_CH0SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH0SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH0SEL field.
+#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL.
+#define BF_FTM_PWMLOAD_CH0SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH0SEL), uint32_t) & BM_FTM_PWMLOAD_CH0SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH1SEL (1U)         //!< Bit position for FTM_PWMLOAD_CH1SEL.
+#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) //!< Bit mask for FTM_PWMLOAD_CH1SEL.
+#define BS_FTM_PWMLOAD_CH1SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH1SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH1SEL field.
+#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL.
+#define BF_FTM_PWMLOAD_CH1SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH1SEL), uint32_t) & BM_FTM_PWMLOAD_CH1SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH2SEL (2U)         //!< Bit position for FTM_PWMLOAD_CH2SEL.
+#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) //!< Bit mask for FTM_PWMLOAD_CH2SEL.
+#define BS_FTM_PWMLOAD_CH2SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH2SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH2SEL field.
+#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL.
+#define BF_FTM_PWMLOAD_CH2SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH2SEL), uint32_t) & BM_FTM_PWMLOAD_CH2SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH3SEL (3U)         //!< Bit position for FTM_PWMLOAD_CH3SEL.
+#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) //!< Bit mask for FTM_PWMLOAD_CH3SEL.
+#define BS_FTM_PWMLOAD_CH3SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH3SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH3SEL field.
+#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL.
+#define BF_FTM_PWMLOAD_CH3SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH3SEL), uint32_t) & BM_FTM_PWMLOAD_CH3SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH4SEL (4U)         //!< Bit position for FTM_PWMLOAD_CH4SEL.
+#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) //!< Bit mask for FTM_PWMLOAD_CH4SEL.
+#define BS_FTM_PWMLOAD_CH4SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH4SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH4SEL field.
+#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL.
+#define BF_FTM_PWMLOAD_CH4SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH4SEL), uint32_t) & BM_FTM_PWMLOAD_CH4SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH5SEL (5U)         //!< Bit position for FTM_PWMLOAD_CH5SEL.
+#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) //!< Bit mask for FTM_PWMLOAD_CH5SEL.
+#define BS_FTM_PWMLOAD_CH5SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH5SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH5SEL field.
+#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL.
+#define BF_FTM_PWMLOAD_CH5SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH5SEL), uint32_t) & BM_FTM_PWMLOAD_CH5SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH6SEL (6U)         //!< Bit position for FTM_PWMLOAD_CH6SEL.
+#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) //!< Bit mask for FTM_PWMLOAD_CH6SEL.
+#define BS_FTM_PWMLOAD_CH6SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH6SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH6SEL field.
+#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL.
+#define BF_FTM_PWMLOAD_CH6SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH6SEL), uint32_t) & BM_FTM_PWMLOAD_CH6SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH7SEL (7U)         //!< Bit position for FTM_PWMLOAD_CH7SEL.
+#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) //!< Bit mask for FTM_PWMLOAD_CH7SEL.
+#define BS_FTM_PWMLOAD_CH7SEL (1U)         //!< Bit field size in bits for FTM_PWMLOAD_CH7SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH7SEL field.
+#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL.
+#define BF_FTM_PWMLOAD_CH7SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH7SEL), uint32_t) & BM_FTM_PWMLOAD_CH7SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0 - Loading updated values is disabled.
+ * - 1 - Loading updated values is enabled.
+ */
+//@{
+#define BP_FTM_PWMLOAD_LDOK  (9U)          //!< Bit position for FTM_PWMLOAD_LDOK.
+#define BM_FTM_PWMLOAD_LDOK  (0x00000200U) //!< Bit mask for FTM_PWMLOAD_LDOK.
+#define BS_FTM_PWMLOAD_LDOK  (1U)          //!< Bit field size in bits for FTM_PWMLOAD_LDOK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_LDOK field.
+#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_LDOK.
+#define BF_FTM_PWMLOAD_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_LDOK), uint32_t) & BM_FTM_PWMLOAD_LDOK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LDOK field to a new value.
+#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_ftm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FTM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_ftm
+{
+    __IO hw_ftm_sc_t SC;                   //!< [0x0] Status And Control
+    __IO hw_ftm_cnt_t CNT;                 //!< [0x4] Counter
+    __IO hw_ftm_mod_t MOD;                 //!< [0x8] Modulo
+    struct {
+        __IO hw_ftm_cnsc_t CnSC;           //!< [0xC] Channel (n) Status And Control
+        __IO hw_ftm_cnv_t CnV;             //!< [0x10] Channel (n) Value
+    } CONTROLS[8];
+    __IO hw_ftm_cntin_t CNTIN;             //!< [0x4C] Counter Initial Value
+    __IO hw_ftm_status_t STATUS;           //!< [0x50] Capture And Compare Status
+    __IO hw_ftm_mode_t MODE;               //!< [0x54] Features Mode Selection
+    __IO hw_ftm_sync_t SYNC;               //!< [0x58] Synchronization
+    __IO hw_ftm_outinit_t OUTINIT;         //!< [0x5C] Initial State For Channels Output
+    __IO hw_ftm_outmask_t OUTMASK;         //!< [0x60] Output Mask
+    __IO hw_ftm_combine_t COMBINE;         //!< [0x64] Function For Linked Channels
+    __IO hw_ftm_deadtime_t DEADTIME;       //!< [0x68] Deadtime Insertion Control
+    __IO hw_ftm_exttrig_t EXTTRIG;         //!< [0x6C] FTM External Trigger
+    __IO hw_ftm_pol_t POL;                 //!< [0x70] Channels Polarity
+    __IO hw_ftm_fms_t FMS;                 //!< [0x74] Fault Mode Status
+    __IO hw_ftm_filter_t FILTER;           //!< [0x78] Input Capture Filter Control
+    __IO hw_ftm_fltctrl_t FLTCTRL;         //!< [0x7C] Fault Control
+    __IO hw_ftm_qdctrl_t QDCTRL;           //!< [0x80] Quadrature Decoder Control And Status
+    __IO hw_ftm_conf_t CONF;               //!< [0x84] Configuration
+    __IO hw_ftm_fltpol_t FLTPOL;           //!< [0x88] FTM Fault Input Polarity
+    __IO hw_ftm_synconf_t SYNCONF;         //!< [0x8C] Synchronization Configuration
+    __IO hw_ftm_invctrl_t INVCTRL;         //!< [0x90] FTM Inverting Control
+    __IO hw_ftm_swoctrl_t SWOCTRL;         //!< [0x94] FTM Software Output Control
+    __IO hw_ftm_pwmload_t PWMLOAD;         //!< [0x98] FTM PWM Load
+} hw_ftm_t;
+#pragma pack()
+
+//! @brief Macro to access all FTM registers.
+//! @param x FTM instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_FTM(0)</code>.
+#define HW_FTM(x)      (*(hw_ftm_t *) REGS_FTM_BASE(x))
+#endif
+
+#endif // __HW_FTM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h
new file mode 100644
index 0000000000..dad7692850
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_GPIO_REGISTERS_H__
+#define __HW_GPIO_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - HW_GPIO_PDOR - Port Data Output Register
+ * - HW_GPIO_PSOR - Port Set Output Register
+ * - HW_GPIO_PCOR - Port Clear Output Register
+ * - HW_GPIO_PTOR - Port Toggle Output Register
+ * - HW_GPIO_PDIR - Port Data Input Register
+ * - HW_GPIO_PDDR - Port Data Direction Register
+ *
+ * - hw_gpio_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_GPIO_BASE
+#define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
+#define HW_GPIOA (0U) //!< Instance number for GPIOA.
+#define HW_GPIOB (1U) //!< Instance number for GPIOB.
+#define HW_GPIOC (2U) //!< Instance number for GPIOC.
+#define HW_GPIOD (3U) //!< Instance number for GPIOD.
+#define HW_GPIOE (4U) //!< Instance number for GPIOE.
+#define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
+#define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
+#define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
+#define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
+#define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
+
+//! @brief Table of base addresses for GPIO instances.
+static const uint32_t __g_regs_GPIO_base_addresses[] = {
+        REGS_GPIOA_BASE,
+        REGS_GPIOB_BASE,
+        REGS_GPIOC_BASE,
+        REGS_GPIOD_BASE,
+        REGS_GPIOE_BASE,
+    };
+
+//! @brief Get the base address of GPIO by instance number.
+//! @param x GPIO instance number, from 0 through 4.
+#define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of GPIO.
+#define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PDOR - Port Data Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+typedef union _hw_gpio_pdor
+{
+    uint32_t U;
+    struct _hw_gpio_pdor_bitfields
+    {
+        uint32_t PDO : 32;             //!< [31:0] Port Data Output
+    } B;
+} hw_gpio_pdor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+//@{
+#define HW_GPIO_PDOR_ADDR(x)     (REGS_GPIO_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PDOR(x)          (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
+#define HW_GPIO_PDOR_RD(x)       (HW_GPIO_PDOR(x).U)
+#define HW_GPIO_PDOR_WR(x, v)    (HW_GPIO_PDOR(x).U = (v))
+#define HW_GPIO_PDOR_SET(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) |  (v)))
+#define HW_GPIO_PDOR_CLR(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
+#define HW_GPIO_PDOR_TOG(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PDOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PDOR, field PDO[31:0] (RW)
+ *
+ * Register bits for unbonded pins return a undefined value when read.
+ *
+ * Values:
+ * - 0 - Logic level 0 is driven on pin, provided pin is configured for
+ *     general-purpose output.
+ * - 1 - Logic level 1 is driven on pin, provided pin is configured for
+ *     general-purpose output.
+ */
+//@{
+#define BP_GPIO_PDOR_PDO     (0U)          //!< Bit position for GPIO_PDOR_PDO.
+#define BM_GPIO_PDOR_PDO     (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
+#define BS_GPIO_PDOR_PDO     (32U)         //!< Bit field size in bits for GPIO_PDOR_PDO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the GPIO_PDOR_PDO field.
+#define BR_GPIO_PDOR_PDO(x)  (HW_GPIO_PDOR(x).U)
+#endif
+
+//! @brief Format value for bitfield GPIO_PDOR_PDO.
+#define BF_GPIO_PDOR_PDO(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDO field to a new value.
+#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PSOR - Port Set Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+typedef union _hw_gpio_psor
+{
+    uint32_t U;
+    struct _hw_gpio_psor_bitfields
+    {
+        uint32_t PTSO : 32;            //!< [31:0] Port Set Output
+    } B;
+} hw_gpio_psor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+//@{
+#define HW_GPIO_PSOR_ADDR(x)     (REGS_GPIO_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PSOR(x)          (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
+#define HW_GPIO_PSOR_RD(x)       (HW_GPIO_PSOR(x).U)
+#define HW_GPIO_PSOR_WR(x, v)    (HW_GPIO_PSOR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PSOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
+ *
+ * Writing to this register will update the contents of the corresponding bit in
+ * the PDOR as follows:
+ *
+ * Values:
+ * - 0 - Corresponding bit in PDORn does not change.
+ * - 1 - Corresponding bit in PDORn is set to logic 1.
+ */
+//@{
+#define BP_GPIO_PSOR_PTSO    (0U)          //!< Bit position for GPIO_PSOR_PTSO.
+#define BM_GPIO_PSOR_PTSO    (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
+#define BS_GPIO_PSOR_PTSO    (32U)         //!< Bit field size in bits for GPIO_PSOR_PTSO.
+
+//! @brief Format value for bitfield GPIO_PSOR_PTSO.
+#define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTSO field to a new value.
+#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PCOR - Port Clear Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+typedef union _hw_gpio_pcor
+{
+    uint32_t U;
+    struct _hw_gpio_pcor_bitfields
+    {
+        uint32_t PTCO : 32;            //!< [31:0] Port Clear Output
+    } B;
+} hw_gpio_pcor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+//@{
+#define HW_GPIO_PCOR_ADDR(x)     (REGS_GPIO_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PCOR(x)          (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
+#define HW_GPIO_PCOR_RD(x)       (HW_GPIO_PCOR(x).U)
+#define HW_GPIO_PCOR_WR(x, v)    (HW_GPIO_PCOR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PCOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
+ *
+ * Writing to this register will update the contents of the corresponding bit in
+ * the Port Data Output Register (PDOR) as follows:
+ *
+ * Values:
+ * - 0 - Corresponding bit in PDORn does not change.
+ * - 1 - Corresponding bit in PDORn is cleared to logic 0.
+ */
+//@{
+#define BP_GPIO_PCOR_PTCO    (0U)          //!< Bit position for GPIO_PCOR_PTCO.
+#define BM_GPIO_PCOR_PTCO    (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
+#define BS_GPIO_PCOR_PTCO    (32U)         //!< Bit field size in bits for GPIO_PCOR_PTCO.
+
+//! @brief Format value for bitfield GPIO_PCOR_PTCO.
+#define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTCO field to a new value.
+#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PTOR - Port Toggle Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_gpio_ptor
+{
+    uint32_t U;
+    struct _hw_gpio_ptor_bitfields
+    {
+        uint32_t PTTO : 32;            //!< [31:0] Port Toggle Output
+    } B;
+} hw_gpio_ptor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+//@{
+#define HW_GPIO_PTOR_ADDR(x)     (REGS_GPIO_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PTOR(x)          (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
+#define HW_GPIO_PTOR_RD(x)       (HW_GPIO_PTOR(x).U)
+#define HW_GPIO_PTOR_WR(x, v)    (HW_GPIO_PTOR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PTOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
+ *
+ * Writing to this register will update the contents of the corresponding bit in
+ * the PDOR as follows:
+ *
+ * Values:
+ * - 0 - Corresponding bit in PDORn does not change.
+ * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
+ *     state.
+ */
+//@{
+#define BP_GPIO_PTOR_PTTO    (0U)          //!< Bit position for GPIO_PTOR_PTTO.
+#define BM_GPIO_PTOR_PTTO    (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
+#define BS_GPIO_PTOR_PTTO    (32U)         //!< Bit field size in bits for GPIO_PTOR_PTTO.
+
+//! @brief Format value for bitfield GPIO_PTOR_PTTO.
+#define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTTO field to a new value.
+#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PDIR - Port Data Input Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+typedef union _hw_gpio_pdir
+{
+    uint32_t U;
+    struct _hw_gpio_pdir_bitfields
+    {
+        uint32_t PDI : 32;             //!< [31:0] Port Data Input
+    } B;
+} hw_gpio_pdir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+//@{
+#define HW_GPIO_PDIR_ADDR(x)     (REGS_GPIO_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PDIR(x)          (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
+#define HW_GPIO_PDIR_RD(x)       (HW_GPIO_PDIR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PDIR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PDIR, field PDI[31:0] (RO)
+ *
+ * Reads 0 at the unimplemented pins for a particular device. Pins that are not
+ * configured for a digital function read 0. If the Port Control and Interrupt
+ * module is disabled, then the corresponding bit in PDIR does not update.
+ *
+ * Values:
+ * - 0 - Pin logic level is logic 0, or is not configured for use by digital
+ *     function.
+ * - 1 - Pin logic level is logic 1.
+ */
+//@{
+#define BP_GPIO_PDIR_PDI     (0U)          //!< Bit position for GPIO_PDIR_PDI.
+#define BM_GPIO_PDIR_PDI     (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
+#define BS_GPIO_PDIR_PDI     (32U)         //!< Bit field size in bits for GPIO_PDIR_PDI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the GPIO_PDIR_PDI field.
+#define BR_GPIO_PDIR_PDI(x)  (HW_GPIO_PDIR(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PDDR - Port Data Direction Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+typedef union _hw_gpio_pddr
+{
+    uint32_t U;
+    struct _hw_gpio_pddr_bitfields
+    {
+        uint32_t PDD : 32;             //!< [31:0] Port Data Direction
+    } B;
+} hw_gpio_pddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+//@{
+#define HW_GPIO_PDDR_ADDR(x)     (REGS_GPIO_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PDDR(x)          (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
+#define HW_GPIO_PDDR_RD(x)       (HW_GPIO_PDDR(x).U)
+#define HW_GPIO_PDDR_WR(x, v)    (HW_GPIO_PDDR(x).U = (v))
+#define HW_GPIO_PDDR_SET(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) |  (v)))
+#define HW_GPIO_PDDR_CLR(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
+#define HW_GPIO_PDDR_TOG(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PDDR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PDDR, field PDD[31:0] (RW)
+ *
+ * Configures individual port pins for input or output.
+ *
+ * Values:
+ * - 0 - Pin is configured as general-purpose input, for the GPIO function.
+ * - 1 - Pin is configured as general-purpose output, for the GPIO function.
+ */
+//@{
+#define BP_GPIO_PDDR_PDD     (0U)          //!< Bit position for GPIO_PDDR_PDD.
+#define BM_GPIO_PDDR_PDD     (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
+#define BS_GPIO_PDDR_PDD     (32U)         //!< Bit field size in bits for GPIO_PDDR_PDD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the GPIO_PDDR_PDD field.
+#define BR_GPIO_PDDR_PDD(x)  (HW_GPIO_PDDR(x).U)
+#endif
+
+//! @brief Format value for bitfield GPIO_PDDR_PDD.
+#define BF_GPIO_PDDR_PDD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDD field to a new value.
+#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_gpio_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All GPIO module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_gpio
+{
+    __IO hw_gpio_pdor_t PDOR;              //!< [0x0] Port Data Output Register
+    __O hw_gpio_psor_t PSOR;               //!< [0x4] Port Set Output Register
+    __O hw_gpio_pcor_t PCOR;               //!< [0x8] Port Clear Output Register
+    __O hw_gpio_ptor_t PTOR;               //!< [0xC] Port Toggle Output Register
+    __I hw_gpio_pdir_t PDIR;               //!< [0x10] Port Data Input Register
+    __IO hw_gpio_pddr_t PDDR;              //!< [0x14] Port Data Direction Register
+} hw_gpio_t;
+#pragma pack()
+
+//! @brief Macro to access all GPIO registers.
+//! @param x GPIO instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_GPIO(0)</code>.
+#define HW_GPIO(x)     (*(hw_gpio_t *) REGS_GPIO_BASE(x))
+#endif
+
+#endif // __HW_GPIO_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h
new file mode 100644
index 0000000000..73a6957006
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h
@@ -0,0 +1,1902 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_I2C_REGISTERS_H__
+#define __HW_I2C_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - HW_I2C_A1 - I2C Address Register 1
+ * - HW_I2C_F - I2C Frequency Divider register
+ * - HW_I2C_C1 - I2C Control Register 1
+ * - HW_I2C_S - I2C Status register
+ * - HW_I2C_D - I2C Data I/O register
+ * - HW_I2C_C2 - I2C Control Register 2
+ * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - HW_I2C_RA - I2C Range Address register
+ * - HW_I2C_SMB - I2C SMBus Control and Status register
+ * - HW_I2C_A2 - I2C Address Register 2
+ * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
+ * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
+ *
+ * - hw_i2c_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_I2C_BASE
+#define HW_I2C_INSTANCE_COUNT (3U) //!< Number of instances of the I2C module.
+#define HW_I2C0 (0U) //!< Instance number for I2C0.
+#define HW_I2C1 (1U) //!< Instance number for I2C1.
+#define HW_I2C2 (2U) //!< Instance number for I2C2.
+#define REGS_I2C0_BASE (0x40066000U) //!< Base address for I2C0.
+#define REGS_I2C1_BASE (0x40067000U) //!< Base address for I2C1.
+#define REGS_I2C2_BASE (0x400E6000U) //!< Base address for I2C2.
+
+//! @brief Table of base addresses for I2C instances.
+static const uint32_t __g_regs_I2C_base_addresses[] = {
+        REGS_I2C0_BASE,
+        REGS_I2C1_BASE,
+        REGS_I2C2_BASE,
+    };
+
+//! @brief Get the base address of I2C by instance number.
+//! @param x I2C instance number, from 0 through 2.
+#define REGS_I2C_BASE(x) (__g_regs_I2C_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of I2C.
+#define REGS_I2C_INSTANCE(b) ((b) == REGS_I2C0_BASE ? HW_I2C0 : (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_A1 - I2C Address Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+typedef union _hw_i2c_a1
+{
+    uint8_t U;
+    struct _hw_i2c_a1_bitfields
+    {
+        uint8_t RESERVED0 : 1;         //!< [0]
+        uint8_t AD : 7;                //!< [7:1] Address
+    } B;
+} hw_i2c_a1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+//@{
+#define HW_I2C_A1_ADDR(x)        (REGS_I2C_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_A1(x)             (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
+#define HW_I2C_A1_RD(x)          (HW_I2C_A1(x).U)
+#define HW_I2C_A1_WR(x, v)       (HW_I2C_A1(x).U = (v))
+#define HW_I2C_A1_SET(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) |  (v)))
+#define HW_I2C_A1_CLR(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
+#define HW_I2C_A1_TOG(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+//@{
+#define BP_I2C_A1_AD         (1U)          //!< Bit position for I2C_A1_AD.
+#define BM_I2C_A1_AD         (0xFEU)       //!< Bit mask for I2C_A1_AD.
+#define BS_I2C_A1_AD         (7U)          //!< Bit field size in bits for I2C_A1_AD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_A1_AD field.
+#define BR_I2C_A1_AD(x)      (HW_I2C_A1(x).B.AD)
+#endif
+
+//! @brief Format value for bitfield I2C_A1_AD.
+#define BF_I2C_A1_AD(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A1_AD), uint8_t) & BM_I2C_A1_AD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AD field to a new value.
+#define BW_I2C_A1_AD(x, v)   (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_F - I2C Frequency Divider register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_f
+{
+    uint8_t U;
+    struct _hw_i2c_f_bitfields
+    {
+        uint8_t ICR : 6;               //!< [5:0] ClockRate
+        uint8_t MULT : 2;              //!< [7:6] Multiplier Factor
+    } B;
+} hw_i2c_f_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+//@{
+#define HW_I2C_F_ADDR(x)         (REGS_I2C_BASE(x) + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_F(x)              (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
+#define HW_I2C_F_RD(x)           (HW_I2C_F(x).U)
+#define HW_I2C_F_WR(x, v)        (HW_I2C_F(x).U = (v))
+#define HW_I2C_F_SET(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) |  (v)))
+#define HW_I2C_F_CLR(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
+#define HW_I2C_F_TOG(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (μs) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h
+ * 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+//@{
+#define BP_I2C_F_ICR         (0U)          //!< Bit position for I2C_F_ICR.
+#define BM_I2C_F_ICR         (0x3FU)       //!< Bit mask for I2C_F_ICR.
+#define BS_I2C_F_ICR         (6U)          //!< Bit field size in bits for I2C_F_ICR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_F_ICR field.
+#define BR_I2C_F_ICR(x)      (HW_I2C_F(x).B.ICR)
+#endif
+
+//! @brief Format value for bitfield I2C_F_ICR.
+#define BF_I2C_F_ICR(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_ICR), uint8_t) & BM_I2C_F_ICR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ICR field to a new value.
+#define BW_I2C_F_ICR(x, v)   (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 00 - mul = 1
+ * - 01 - mul = 2
+ * - 10 - mul = 4
+ * - 11 - Reserved
+ */
+//@{
+#define BP_I2C_F_MULT        (6U)          //!< Bit position for I2C_F_MULT.
+#define BM_I2C_F_MULT        (0xC0U)       //!< Bit mask for I2C_F_MULT.
+#define BS_I2C_F_MULT        (2U)          //!< Bit field size in bits for I2C_F_MULT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_F_MULT field.
+#define BR_I2C_F_MULT(x)     (HW_I2C_F(x).B.MULT)
+#endif
+
+//! @brief Format value for bitfield I2C_F_MULT.
+#define BF_I2C_F_MULT(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_MULT), uint8_t) & BM_I2C_F_MULT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MULT field to a new value.
+#define BW_I2C_F_MULT(x, v)  (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_C1 - I2C Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_c1
+{
+    uint8_t U;
+    struct _hw_i2c_c1_bitfields
+    {
+        uint8_t DMAEN : 1;             //!< [0] DMA Enable
+        uint8_t WUEN : 1;              //!< [1] Wakeup Enable
+        uint8_t RSTA : 1;              //!< [2] Repeat START
+        uint8_t TXAK : 1;              //!< [3] Transmit Acknowledge Enable
+        uint8_t TX : 1;                //!< [4] Transmit Mode Select
+        uint8_t MST : 1;               //!< [5] Master Mode Select
+        uint8_t IICIE : 1;             //!< [6] I2C Interrupt Enable
+        uint8_t IICEN : 1;             //!< [7] I2C Enable
+    } B;
+} hw_i2c_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+//@{
+#define HW_I2C_C1_ADDR(x)        (REGS_I2C_BASE(x) + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_C1(x)             (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
+#define HW_I2C_C1_RD(x)          (HW_I2C_C1(x).U)
+#define HW_I2C_C1_WR(x, v)       (HW_I2C_C1(x).U = (v))
+#define HW_I2C_C1_SET(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) |  (v)))
+#define HW_I2C_C1_CLR(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
+#define HW_I2C_C1_TOG(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0 - All DMA signalling disabled.
+ * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
+ *     trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received matches
+ *     the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+//@{
+#define BP_I2C_C1_DMAEN      (0U)          //!< Bit position for I2C_C1_DMAEN.
+#define BM_I2C_C1_DMAEN      (0x01U)       //!< Bit mask for I2C_C1_DMAEN.
+#define BS_I2C_C1_DMAEN      (1U)          //!< Bit field size in bits for I2C_C1_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_DMAEN field.
+#define BR_I2C_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_DMAEN.
+#define BF_I2C_C1_DMAEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_DMAEN), uint8_t) & BM_I2C_C1_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 1 - Enables the wakeup function in low power mode.
+ */
+//@{
+#define BP_I2C_C1_WUEN       (1U)          //!< Bit position for I2C_C1_WUEN.
+#define BM_I2C_C1_WUEN       (0x02U)       //!< Bit mask for I2C_C1_WUEN.
+#define BS_I2C_C1_WUEN       (1U)          //!< Bit field size in bits for I2C_C1_WUEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_WUEN field.
+#define BR_I2C_C1_WUEN(x)    (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_WUEN.
+#define BF_I2C_C1_WUEN(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_WUEN), uint8_t) & BM_I2C_C1_WUEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUEN field to a new value.
+#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+//@{
+#define BP_I2C_C1_RSTA       (2U)          //!< Bit position for I2C_C1_RSTA.
+#define BM_I2C_C1_RSTA       (0x04U)       //!< Bit mask for I2C_C1_RSTA.
+#define BS_I2C_C1_RSTA       (1U)          //!< Bit field size in bits for I2C_C1_RSTA.
+
+//! @brief Format value for bitfield I2C_C1_RSTA.
+#define BF_I2C_C1_RSTA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_RSTA), uint8_t) & BM_I2C_C1_RSTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTA field to a new value.
+#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK is
+ *     set).
+ */
+//@{
+#define BP_I2C_C1_TXAK       (3U)          //!< Bit position for I2C_C1_TXAK.
+#define BM_I2C_C1_TXAK       (0x08U)       //!< Bit mask for I2C_C1_TXAK.
+#define BS_I2C_C1_TXAK       (1U)          //!< Bit field size in bits for I2C_C1_TXAK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_TXAK field.
+#define BR_I2C_C1_TXAK(x)    (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_TXAK.
+#define BF_I2C_C1_TXAK(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TXAK), uint8_t) & BM_I2C_C1_TXAK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXAK field to a new value.
+#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0 - Receive
+ * - 1 - Transmit
+ */
+//@{
+#define BP_I2C_C1_TX         (4U)          //!< Bit position for I2C_C1_TX.
+#define BM_I2C_C1_TX         (0x10U)       //!< Bit mask for I2C_C1_TX.
+#define BS_I2C_C1_TX         (1U)          //!< Bit field size in bits for I2C_C1_TX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_TX field.
+#define BR_I2C_C1_TX(x)      (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_TX.
+#define BF_I2C_C1_TX(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TX), uint8_t) & BM_I2C_C1_TX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX field to a new value.
+#define BW_I2C_C1_TX(x, v)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0 - Slave mode
+ * - 1 - Master mode
+ */
+//@{
+#define BP_I2C_C1_MST        (5U)          //!< Bit position for I2C_C1_MST.
+#define BM_I2C_C1_MST        (0x20U)       //!< Bit mask for I2C_C1_MST.
+#define BS_I2C_C1_MST        (1U)          //!< Bit field size in bits for I2C_C1_MST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_MST field.
+#define BR_I2C_C1_MST(x)     (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_MST.
+#define BF_I2C_C1_MST(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_MST), uint8_t) & BM_I2C_C1_MST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MST field to a new value.
+#define BW_I2C_C1_MST(x, v)  (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_I2C_C1_IICIE      (6U)          //!< Bit position for I2C_C1_IICIE.
+#define BM_I2C_C1_IICIE      (0x40U)       //!< Bit mask for I2C_C1_IICIE.
+#define BS_I2C_C1_IICIE      (1U)          //!< Bit field size in bits for I2C_C1_IICIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_IICIE field.
+#define BR_I2C_C1_IICIE(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_IICIE.
+#define BF_I2C_C1_IICIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICIE), uint8_t) & BM_I2C_C1_IICIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IICIE field to a new value.
+#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_I2C_C1_IICEN      (7U)          //!< Bit position for I2C_C1_IICEN.
+#define BM_I2C_C1_IICEN      (0x80U)       //!< Bit mask for I2C_C1_IICEN.
+#define BS_I2C_C1_IICEN      (1U)          //!< Bit field size in bits for I2C_C1_IICEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_IICEN field.
+#define BR_I2C_C1_IICEN(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_IICEN.
+#define BF_I2C_C1_IICEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICEN), uint8_t) & BM_I2C_C1_IICEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IICEN field to a new value.
+#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_S - I2C Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+typedef union _hw_i2c_s
+{
+    uint8_t U;
+    struct _hw_i2c_s_bitfields
+    {
+        uint8_t RXAK : 1;              //!< [0] Receive Acknowledge
+        uint8_t IICIF : 1;             //!< [1] Interrupt Flag
+        uint8_t SRW : 1;               //!< [2] Slave Read/Write
+        uint8_t RAM : 1;               //!< [3] Range Address Match
+        uint8_t ARBL : 1;              //!< [4] Arbitration Lost
+        uint8_t BUSY : 1;              //!< [5] Bus Busy
+        uint8_t IAAS : 1;              //!< [6] Addressed As A Slave
+        uint8_t TCF : 1;               //!< [7] Transfer Complete Flag
+    } B;
+} hw_i2c_s_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+//@{
+#define HW_I2C_S_ADDR(x)         (REGS_I2C_BASE(x) + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_S(x)              (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
+#define HW_I2C_S_RD(x)           (HW_I2C_S(x).U)
+#define HW_I2C_S_WR(x, v)        (HW_I2C_S(x).U = (v))
+#define HW_I2C_S_SET(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) |  (v)))
+#define HW_I2C_S_CLR(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
+#define HW_I2C_S_TOG(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 1 - No acknowledge signal detected
+ */
+//@{
+#define BP_I2C_S_RXAK        (0U)          //!< Bit position for I2C_S_RXAK.
+#define BM_I2C_S_RXAK        (0x01U)       //!< Bit mask for I2C_S_RXAK.
+#define BS_I2C_S_RXAK        (1U)          //!< Bit field size in bits for I2C_S_RXAK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_RXAK field.
+#define BR_I2C_S_RXAK(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0 - No interrupt pending
+ * - 1 - Interrupt pending
+ */
+//@{
+#define BP_I2C_S_IICIF       (1U)          //!< Bit position for I2C_S_IICIF.
+#define BM_I2C_S_IICIF       (0x02U)       //!< Bit mask for I2C_S_IICIF.
+#define BS_I2C_S_IICIF       (1U)          //!< Bit field size in bits for I2C_S_IICIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_IICIF field.
+#define BR_I2C_S_IICIF(x)    (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
+#endif
+
+//! @brief Format value for bitfield I2C_S_IICIF.
+#define BF_I2C_S_IICIF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IICIF), uint8_t) & BM_I2C_S_IICIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IICIF field to a new value.
+#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0 - Slave receive, master writing to slave
+ * - 1 - Slave transmit, master reading from slave
+ */
+//@{
+#define BP_I2C_S_SRW         (2U)          //!< Bit position for I2C_S_SRW.
+#define BM_I2C_S_SRW         (0x04U)       //!< Bit mask for I2C_S_SRW.
+#define BS_I2C_S_SRW         (1U)          //!< Bit field size in bits for I2C_S_SRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_SRW field.
+#define BR_I2C_S_SRW(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave
+ */
+//@{
+#define BP_I2C_S_RAM         (3U)          //!< Bit position for I2C_S_RAM.
+#define BM_I2C_S_RAM         (0x08U)       //!< Bit mask for I2C_S_RAM.
+#define BS_I2C_S_RAM         (1U)          //!< Bit field size in bits for I2C_S_RAM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_RAM field.
+#define BR_I2C_S_RAM(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
+#endif
+
+//! @brief Format value for bitfield I2C_S_RAM.
+#define BF_I2C_S_RAM(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_RAM), uint8_t) & BM_I2C_S_RAM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RAM field to a new value.
+#define BW_I2C_S_RAM(x, v)   (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0 - Standard bus operation.
+ * - 1 - Loss of arbitration.
+ */
+//@{
+#define BP_I2C_S_ARBL        (4U)          //!< Bit position for I2C_S_ARBL.
+#define BM_I2C_S_ARBL        (0x10U)       //!< Bit mask for I2C_S_ARBL.
+#define BS_I2C_S_ARBL        (1U)          //!< Bit field size in bits for I2C_S_ARBL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_ARBL field.
+#define BR_I2C_S_ARBL(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
+#endif
+
+//! @brief Format value for bitfield I2C_S_ARBL.
+#define BF_I2C_S_ARBL(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_ARBL), uint8_t) & BM_I2C_S_ARBL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ARBL field to a new value.
+#define BW_I2C_S_ARBL(x, v)  (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0 - Bus is idle
+ * - 1 - Bus is busy
+ */
+//@{
+#define BP_I2C_S_BUSY        (5U)          //!< Bit position for I2C_S_BUSY.
+#define BM_I2C_S_BUSY        (0x20U)       //!< Bit mask for I2C_S_BUSY.
+#define BS_I2C_S_BUSY        (1U)          //!< Bit field size in bits for I2C_S_BUSY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_BUSY field.
+#define BR_I2C_S_BUSY(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave
+ */
+//@{
+#define BP_I2C_S_IAAS        (6U)          //!< Bit position for I2C_S_IAAS.
+#define BM_I2C_S_IAAS        (0x40U)       //!< Bit mask for I2C_S_IAAS.
+#define BS_I2C_S_IAAS        (1U)          //!< Bit field size in bits for I2C_S_IAAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_IAAS field.
+#define BR_I2C_S_IAAS(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
+#endif
+
+//! @brief Format value for bitfield I2C_S_IAAS.
+#define BF_I2C_S_IAAS(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IAAS), uint8_t) & BM_I2C_S_IAAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IAAS field to a new value.
+#define BW_I2C_S_IAAS(x, v)  (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0 - Transfer in progress
+ * - 1 - Transfer complete
+ */
+//@{
+#define BP_I2C_S_TCF         (7U)          //!< Bit position for I2C_S_TCF.
+#define BM_I2C_S_TCF         (0x80U)       //!< Bit mask for I2C_S_TCF.
+#define BS_I2C_S_TCF         (1U)          //!< Bit field size in bits for I2C_S_TCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_TCF field.
+#define BR_I2C_S_TCF(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_D - I2C Data I/O register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_d
+{
+    uint8_t U;
+    struct _hw_i2c_d_bitfields
+    {
+        uint8_t DATA : 8;              //!< [7:0] Data
+    } B;
+} hw_i2c_d_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+//@{
+#define HW_I2C_D_ADDR(x)         (REGS_I2C_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_D(x)              (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
+#define HW_I2C_D_RD(x)           (HW_I2C_D(x).U)
+#define HW_I2C_D_WR(x, v)        (HW_I2C_D(x).U = (v))
+#define HW_I2C_D_SET(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) |  (v)))
+#define HW_I2C_D_CLR(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
+#define HW_I2C_D_TOG(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_D bitfields
+ */
+
+/*!
+ * @name Register I2C_D, field DATA[7:0] (RW)
+ *
+ * In master transmit mode, when data is written to this register, a data
+ * transfer is initiated. The most significant bit is sent first. In master receive
+ * mode, reading this register initiates receiving of the next byte of data. When
+ * making the transition out of master receive mode, switch the I2C mode before
+ * reading the Data register to prevent an inadvertent initiation of a master
+ * receive data transfer. In slave mode, the same functions are available after an
+ * address match occurs. The C1[TX] bit must correctly reflect the desired direction
+ * of transfer in master and slave modes for the transmission to begin. For
+ * example, if the I2C module is configured for master transmit but a master receive
+ * is desired, reading the Data register does not initiate the receive. Reading
+ * the Data register returns the last byte received while the I2C module is
+ * configured in master receive or slave receive mode. The Data register does not
+ * reflect every byte that is transmitted on the I2C bus, and neither can software
+ * verify that a byte has been written to the Data register correctly by reading it
+ * back. In master transmit mode, the first byte of data written to the Data
+ * register following assertion of MST (start bit) or assertion of RSTA (repeated
+ * start bit) is used for the address transfer and must consist of the calling
+ * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
+ */
+//@{
+#define BP_I2C_D_DATA        (0U)          //!< Bit position for I2C_D_DATA.
+#define BM_I2C_D_DATA        (0xFFU)       //!< Bit mask for I2C_D_DATA.
+#define BS_I2C_D_DATA        (8U)          //!< Bit field size in bits for I2C_D_DATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_D_DATA field.
+#define BR_I2C_D_DATA(x)     (HW_I2C_D(x).U)
+#endif
+
+//! @brief Format value for bitfield I2C_D_DATA.
+#define BF_I2C_D_DATA(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_D_DATA), uint8_t) & BM_I2C_D_DATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA field to a new value.
+#define BW_I2C_D_DATA(x, v)  (HW_I2C_D_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_C2 - I2C Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_c2
+{
+    uint8_t U;
+    struct _hw_i2c_c2_bitfields
+    {
+        uint8_t AD : 3;                //!< [2:0] Slave Address
+        uint8_t RMEN : 1;              //!< [3] Range Address Matching Enable
+        uint8_t SBRC : 1;              //!< [4] Slave Baud Rate Control
+        uint8_t HDRS : 1;              //!< [5] High Drive Select
+        uint8_t ADEXT : 1;             //!< [6] Address Extension
+        uint8_t GCAEN : 1;             //!< [7] General Call Address Enable
+    } B;
+} hw_i2c_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+//@{
+#define HW_I2C_C2_ADDR(x)        (REGS_I2C_BASE(x) + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_C2(x)             (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
+#define HW_I2C_C2_RD(x)          (HW_I2C_C2(x).U)
+#define HW_I2C_C2_WR(x, v)       (HW_I2C_C2(x).U = (v))
+#define HW_I2C_C2_SET(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) |  (v)))
+#define HW_I2C_C2_CLR(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
+#define HW_I2C_C2_TOG(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+//@{
+#define BP_I2C_C2_AD         (0U)          //!< Bit position for I2C_C2_AD.
+#define BM_I2C_C2_AD         (0x07U)       //!< Bit mask for I2C_C2_AD.
+#define BS_I2C_C2_AD         (3U)          //!< Bit field size in bits for I2C_C2_AD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_AD field.
+#define BR_I2C_C2_AD(x)      (HW_I2C_C2(x).B.AD)
+#endif
+
+//! @brief Format value for bitfield I2C_C2_AD.
+#define BF_I2C_C2_AD(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_AD), uint8_t) & BM_I2C_C2_AD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AD field to a new value.
+#define BW_I2C_C2_AD(x, v)   (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+//@{
+#define BP_I2C_C2_RMEN       (3U)          //!< Bit position for I2C_C2_RMEN.
+#define BM_I2C_C2_RMEN       (0x08U)       //!< Bit mask for I2C_C2_RMEN.
+#define BS_I2C_C2_RMEN       (1U)          //!< Bit field size in bits for I2C_C2_RMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_RMEN field.
+#define BR_I2C_C2_RMEN(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_RMEN.
+#define BF_I2C_C2_RMEN(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_RMEN), uint8_t) & BM_I2C_C2_RMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMEN field to a new value.
+#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 1 - Slave baud rate is independent of the master baud rate
+ */
+//@{
+#define BP_I2C_C2_SBRC       (4U)          //!< Bit position for I2C_C2_SBRC.
+#define BM_I2C_C2_SBRC       (0x10U)       //!< Bit mask for I2C_C2_SBRC.
+#define BS_I2C_C2_SBRC       (1U)          //!< Bit field size in bits for I2C_C2_SBRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_SBRC field.
+#define BR_I2C_C2_SBRC(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_SBRC.
+#define BF_I2C_C2_SBRC(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_SBRC), uint8_t) & BM_I2C_C2_SBRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBRC field to a new value.
+#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0 - Normal drive mode
+ * - 1 - High drive mode
+ */
+//@{
+#define BP_I2C_C2_HDRS       (5U)          //!< Bit position for I2C_C2_HDRS.
+#define BM_I2C_C2_HDRS       (0x20U)       //!< Bit mask for I2C_C2_HDRS.
+#define BS_I2C_C2_HDRS       (1U)          //!< Bit field size in bits for I2C_C2_HDRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_HDRS field.
+#define BR_I2C_C2_HDRS(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_HDRS.
+#define BF_I2C_C2_HDRS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_HDRS), uint8_t) & BM_I2C_C2_HDRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HDRS field to a new value.
+#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0 - 7-bit address scheme
+ * - 1 - 10-bit address scheme
+ */
+//@{
+#define BP_I2C_C2_ADEXT      (6U)          //!< Bit position for I2C_C2_ADEXT.
+#define BM_I2C_C2_ADEXT      (0x40U)       //!< Bit mask for I2C_C2_ADEXT.
+#define BS_I2C_C2_ADEXT      (1U)          //!< Bit field size in bits for I2C_C2_ADEXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_ADEXT field.
+#define BR_I2C_C2_ADEXT(x)   (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_ADEXT.
+#define BF_I2C_C2_ADEXT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_ADEXT), uint8_t) & BM_I2C_C2_ADEXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADEXT field to a new value.
+#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_I2C_C2_GCAEN      (7U)          //!< Bit position for I2C_C2_GCAEN.
+#define BM_I2C_C2_GCAEN      (0x80U)       //!< Bit mask for I2C_C2_GCAEN.
+#define BS_I2C_C2_GCAEN      (1U)          //!< Bit field size in bits for I2C_C2_GCAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_GCAEN field.
+#define BR_I2C_C2_GCAEN(x)   (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_GCAEN.
+#define BF_I2C_C2_GCAEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_GCAEN), uint8_t) & BM_I2C_C2_GCAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GCAEN field to a new value.
+#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_FLT - I2C Programmable Input Glitch Filter register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_flt
+{
+    uint8_t U;
+    struct _hw_i2c_flt_bitfields
+    {
+        uint8_t FLT : 4;               //!< [3:0] I2C Programmable Filter Factor
+        uint8_t STARTF : 1;            //!< [4] I2C Bus Start Detect Flag
+        uint8_t SSIE : 1;              //!< [5] I2C Bus Stop or Start Interrupt Enable
+        uint8_t STOPF : 1;             //!< [6] I2C Bus Stop Detect Flag
+        uint8_t SHEN : 1;              //!< [7] Stop Hold Enable
+    } B;
+} hw_i2c_flt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+//@{
+#define HW_I2C_FLT_ADDR(x)       (REGS_I2C_BASE(x) + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_FLT(x)            (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
+#define HW_I2C_FLT_RD(x)         (HW_I2C_FLT(x).U)
+#define HW_I2C_FLT_WR(x, v)      (HW_I2C_FLT(x).U = (v))
+#define HW_I2C_FLT_SET(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) |  (v)))
+#define HW_I2C_FLT_CLR(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
+#define HW_I2C_FLT_TOG(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0 - No filter/bypass
+ */
+//@{
+#define BP_I2C_FLT_FLT       (0U)          //!< Bit position for I2C_FLT_FLT.
+#define BM_I2C_FLT_FLT       (0x0FU)       //!< Bit mask for I2C_FLT_FLT.
+#define BS_I2C_FLT_FLT       (4U)          //!< Bit field size in bits for I2C_FLT_FLT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_FLT field.
+#define BR_I2C_FLT_FLT(x)    (HW_I2C_FLT(x).B.FLT)
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_FLT.
+#define BF_I2C_FLT_FLT(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_FLT), uint8_t) & BM_I2C_FLT_FLT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT field to a new value.
+#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No start happens on I2C bus
+ * - 1 - Start detected on I2C bus
+ */
+//@{
+#define BP_I2C_FLT_STARTF    (4U)          //!< Bit position for I2C_FLT_STARTF.
+#define BM_I2C_FLT_STARTF    (0x10U)       //!< Bit mask for I2C_FLT_STARTF.
+#define BS_I2C_FLT_STARTF    (1U)          //!< Bit field size in bits for I2C_FLT_STARTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_STARTF field.
+#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_STARTF.
+#define BF_I2C_FLT_STARTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STARTF), uint8_t) & BM_I2C_FLT_STARTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STARTF field to a new value.
+#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0 - Stop or start detection interrupt is disabled
+ * - 1 - Stop or start detection interrupt is enabled
+ */
+//@{
+#define BP_I2C_FLT_SSIE      (5U)          //!< Bit position for I2C_FLT_SSIE.
+#define BM_I2C_FLT_SSIE      (0x20U)       //!< Bit mask for I2C_FLT_SSIE.
+#define BS_I2C_FLT_SSIE      (1U)          //!< Bit field size in bits for I2C_FLT_SSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_SSIE field.
+#define BR_I2C_FLT_SSIE(x)   (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_SSIE.
+#define BF_I2C_FLT_SSIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SSIE), uint8_t) & BM_I2C_FLT_SSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSIE field to a new value.
+#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No stop happens on I2C bus
+ * - 1 - Stop detected on I2C bus
+ */
+//@{
+#define BP_I2C_FLT_STOPF     (6U)          //!< Bit position for I2C_FLT_STOPF.
+#define BM_I2C_FLT_STOPF     (0x40U)       //!< Bit mask for I2C_FLT_STOPF.
+#define BS_I2C_FLT_STOPF     (1U)          //!< Bit field size in bits for I2C_FLT_STOPF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_STOPF field.
+#define BR_I2C_FLT_STOPF(x)  (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_STOPF.
+#define BF_I2C_FLT_STOPF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STOPF), uint8_t) & BM_I2C_FLT_STOPF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPF field to a new value.
+#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 1 - Stop holdoff is enabled.
+ */
+//@{
+#define BP_I2C_FLT_SHEN      (7U)          //!< Bit position for I2C_FLT_SHEN.
+#define BM_I2C_FLT_SHEN      (0x80U)       //!< Bit mask for I2C_FLT_SHEN.
+#define BS_I2C_FLT_SHEN      (1U)          //!< Bit field size in bits for I2C_FLT_SHEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_SHEN field.
+#define BR_I2C_FLT_SHEN(x)   (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_SHEN.
+#define BF_I2C_FLT_SHEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SHEN), uint8_t) & BM_I2C_FLT_SHEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHEN field to a new value.
+#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_RA - I2C Range Address register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_ra
+{
+    uint8_t U;
+    struct _hw_i2c_ra_bitfields
+    {
+        uint8_t RESERVED0 : 1;         //!< [0]
+        uint8_t RAD : 7;               //!< [7:1] Range Slave Address
+    } B;
+} hw_i2c_ra_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+//@{
+#define HW_I2C_RA_ADDR(x)        (REGS_I2C_BASE(x) + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_RA(x)             (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
+#define HW_I2C_RA_RD(x)          (HW_I2C_RA(x).U)
+#define HW_I2C_RA_WR(x, v)       (HW_I2C_RA(x).U = (v))
+#define HW_I2C_RA_SET(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) |  (v)))
+#define HW_I2C_RA_CLR(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
+#define HW_I2C_RA_TOG(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+//@{
+#define BP_I2C_RA_RAD        (1U)          //!< Bit position for I2C_RA_RAD.
+#define BM_I2C_RA_RAD        (0xFEU)       //!< Bit mask for I2C_RA_RAD.
+#define BS_I2C_RA_RAD        (7U)          //!< Bit field size in bits for I2C_RA_RAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_RA_RAD field.
+#define BR_I2C_RA_RAD(x)     (HW_I2C_RA(x).B.RAD)
+#endif
+
+//! @brief Format value for bitfield I2C_RA_RAD.
+#define BF_I2C_RA_RAD(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_RA_RAD), uint8_t) & BM_I2C_RA_RAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RAD field to a new value.
+#define BW_I2C_RA_RAD(x, v)  (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_SMB - I2C SMBus Control and Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+typedef union _hw_i2c_smb
+{
+    uint8_t U;
+    struct _hw_i2c_smb_bitfields
+    {
+        uint8_t SHTF2IE : 1;           //!< [0] SHTF2 Interrupt Enable
+        uint8_t SHTF2 : 1;             //!< [1] SCL High Timeout Flag 2
+        uint8_t SHTF1 : 1;             //!< [2] SCL High Timeout Flag 1
+        uint8_t SLTF : 1;              //!< [3] SCL Low Timeout Flag
+        uint8_t TCKSEL : 1;            //!< [4] Timeout Counter Clock Select
+        uint8_t SIICAEN : 1;           //!< [5] Second I2C Address Enable
+        uint8_t ALERTEN : 1;           //!< [6] SMBus Alert Response Address Enable
+        uint8_t FACK : 1;              //!< [7] Fast NACK/ACK Enable
+    } B;
+} hw_i2c_smb_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+//@{
+#define HW_I2C_SMB_ADDR(x)       (REGS_I2C_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_SMB(x)            (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
+#define HW_I2C_SMB_RD(x)         (HW_I2C_SMB(x).U)
+#define HW_I2C_SMB_WR(x, v)      (HW_I2C_SMB(x).U = (v))
+#define HW_I2C_SMB_SET(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) |  (v)))
+#define HW_I2C_SMB_CLR(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
+#define HW_I2C_SMB_TOG(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0 - SHTF2 interrupt is disabled
+ * - 1 - SHTF2 interrupt is enabled
+ */
+//@{
+#define BP_I2C_SMB_SHTF2IE   (0U)          //!< Bit position for I2C_SMB_SHTF2IE.
+#define BM_I2C_SMB_SHTF2IE   (0x01U)       //!< Bit mask for I2C_SMB_SHTF2IE.
+#define BS_I2C_SMB_SHTF2IE   (1U)          //!< Bit field size in bits for I2C_SMB_SHTF2IE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SHTF2IE field.
+#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SHTF2IE.
+#define BF_I2C_SMB_SHTF2IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2IE), uint8_t) & BM_I2C_SMB_SHTF2IE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHTF2IE field to a new value.
+#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No SCL high and SDA low timeout occurs
+ * - 1 - SCL high and SDA low timeout occurs
+ */
+//@{
+#define BP_I2C_SMB_SHTF2     (1U)          //!< Bit position for I2C_SMB_SHTF2.
+#define BM_I2C_SMB_SHTF2     (0x02U)       //!< Bit mask for I2C_SMB_SHTF2.
+#define BS_I2C_SMB_SHTF2     (1U)          //!< Bit field size in bits for I2C_SMB_SHTF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SHTF2 field.
+#define BR_I2C_SMB_SHTF2(x)  (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SHTF2.
+#define BF_I2C_SMB_SHTF2(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2), uint8_t) & BM_I2C_SMB_SHTF2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHTF2 field to a new value.
+#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0 - No SCL high and SDA high timeout occurs
+ * - 1 - SCL high and SDA high timeout occurs
+ */
+//@{
+#define BP_I2C_SMB_SHTF1     (2U)          //!< Bit position for I2C_SMB_SHTF1.
+#define BM_I2C_SMB_SHTF1     (0x04U)       //!< Bit mask for I2C_SMB_SHTF1.
+#define BS_I2C_SMB_SHTF1     (1U)          //!< Bit field size in bits for I2C_SMB_SHTF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SHTF1 field.
+#define BR_I2C_SMB_SHTF1(x)  (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0 - No low timeout occurs
+ * - 1 - Low timeout occurs
+ */
+//@{
+#define BP_I2C_SMB_SLTF      (3U)          //!< Bit position for I2C_SMB_SLTF.
+#define BM_I2C_SMB_SLTF      (0x08U)       //!< Bit mask for I2C_SMB_SLTF.
+#define BS_I2C_SMB_SLTF      (1U)          //!< Bit field size in bits for I2C_SMB_SLTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SLTF field.
+#define BR_I2C_SMB_SLTF(x)   (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SLTF.
+#define BF_I2C_SMB_SLTF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SLTF), uint8_t) & BM_I2C_SMB_SLTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLTF field to a new value.
+#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+//@{
+#define BP_I2C_SMB_TCKSEL    (4U)          //!< Bit position for I2C_SMB_TCKSEL.
+#define BM_I2C_SMB_TCKSEL    (0x10U)       //!< Bit mask for I2C_SMB_TCKSEL.
+#define BS_I2C_SMB_TCKSEL    (1U)          //!< Bit field size in bits for I2C_SMB_TCKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_TCKSEL field.
+#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_TCKSEL.
+#define BF_I2C_SMB_TCKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_TCKSEL), uint8_t) & BM_I2C_SMB_TCKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCKSEL field to a new value.
+#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0 - I2C address register 2 matching is disabled
+ * - 1 - I2C address register 2 matching is enabled
+ */
+//@{
+#define BP_I2C_SMB_SIICAEN   (5U)          //!< Bit position for I2C_SMB_SIICAEN.
+#define BM_I2C_SMB_SIICAEN   (0x20U)       //!< Bit mask for I2C_SMB_SIICAEN.
+#define BS_I2C_SMB_SIICAEN   (1U)          //!< Bit field size in bits for I2C_SMB_SIICAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SIICAEN field.
+#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SIICAEN.
+#define BF_I2C_SMB_SIICAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SIICAEN), uint8_t) & BM_I2C_SMB_SIICAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SIICAEN field to a new value.
+#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0 - SMBus alert response address matching is disabled
+ * - 1 - SMBus alert response address matching is enabled
+ */
+//@{
+#define BP_I2C_SMB_ALERTEN   (6U)          //!< Bit position for I2C_SMB_ALERTEN.
+#define BM_I2C_SMB_ALERTEN   (0x40U)       //!< Bit mask for I2C_SMB_ALERTEN.
+#define BS_I2C_SMB_ALERTEN   (1U)          //!< Bit field size in bits for I2C_SMB_ALERTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_ALERTEN field.
+#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_ALERTEN.
+#define BF_I2C_SMB_ALERTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_ALERTEN), uint8_t) & BM_I2C_SMB_ALERTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ALERTEN field to a new value.
+#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0 - An ACK or NACK is sent on the following receiving data byte
+ * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
+ *     1 to TXAK after receiving a data byte generates a NACK.
+ */
+//@{
+#define BP_I2C_SMB_FACK      (7U)          //!< Bit position for I2C_SMB_FACK.
+#define BM_I2C_SMB_FACK      (0x80U)       //!< Bit mask for I2C_SMB_FACK.
+#define BS_I2C_SMB_FACK      (1U)          //!< Bit field size in bits for I2C_SMB_FACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_FACK field.
+#define BR_I2C_SMB_FACK(x)   (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_FACK.
+#define BF_I2C_SMB_FACK(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_FACK), uint8_t) & BM_I2C_SMB_FACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FACK field to a new value.
+#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_A2 - I2C Address Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+typedef union _hw_i2c_a2
+{
+    uint8_t U;
+    struct _hw_i2c_a2_bitfields
+    {
+        uint8_t RESERVED0 : 1;         //!< [0]
+        uint8_t SAD : 7;               //!< [7:1] SMBus Address
+    } B;
+} hw_i2c_a2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+//@{
+#define HW_I2C_A2_ADDR(x)        (REGS_I2C_BASE(x) + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_A2(x)             (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
+#define HW_I2C_A2_RD(x)          (HW_I2C_A2(x).U)
+#define HW_I2C_A2_WR(x, v)       (HW_I2C_A2(x).U = (v))
+#define HW_I2C_A2_SET(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) |  (v)))
+#define HW_I2C_A2_CLR(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
+#define HW_I2C_A2_TOG(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+//@{
+#define BP_I2C_A2_SAD        (1U)          //!< Bit position for I2C_A2_SAD.
+#define BM_I2C_A2_SAD        (0xFEU)       //!< Bit mask for I2C_A2_SAD.
+#define BS_I2C_A2_SAD        (7U)          //!< Bit field size in bits for I2C_A2_SAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_A2_SAD field.
+#define BR_I2C_A2_SAD(x)     (HW_I2C_A2(x).B.SAD)
+#endif
+
+//! @brief Format value for bitfield I2C_A2_SAD.
+#define BF_I2C_A2_SAD(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A2_SAD), uint8_t) & BM_I2C_A2_SAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAD field to a new value.
+#define BW_I2C_A2_SAD(x, v)  (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_SLTH - I2C SCL Low Timeout Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_slth
+{
+    uint8_t U;
+    struct _hw_i2c_slth_bitfields
+    {
+        uint8_t SSLT : 8;              //!< [7:0]
+    } B;
+} hw_i2c_slth_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+//@{
+#define HW_I2C_SLTH_ADDR(x)      (REGS_I2C_BASE(x) + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_SLTH(x)           (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
+#define HW_I2C_SLTH_RD(x)        (HW_I2C_SLTH(x).U)
+#define HW_I2C_SLTH_WR(x, v)     (HW_I2C_SLTH(x).U = (v))
+#define HW_I2C_SLTH_SET(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) |  (v)))
+#define HW_I2C_SLTH_CLR(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
+#define HW_I2C_SLTH_TOG(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_SLTH bitfields
+ */
+
+/*!
+ * @name Register I2C_SLTH, field SSLT[7:0] (RW)
+ *
+ * Most significant byte of SCL low timeout value that determines the timeout
+ * period of SCL low.
+ */
+//@{
+#define BP_I2C_SLTH_SSLT     (0U)          //!< Bit position for I2C_SLTH_SSLT.
+#define BM_I2C_SLTH_SSLT     (0xFFU)       //!< Bit mask for I2C_SLTH_SSLT.
+#define BS_I2C_SLTH_SSLT     (8U)          //!< Bit field size in bits for I2C_SLTH_SSLT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SLTH_SSLT field.
+#define BR_I2C_SLTH_SSLT(x)  (HW_I2C_SLTH(x).U)
+#endif
+
+//! @brief Format value for bitfield I2C_SLTH_SSLT.
+#define BF_I2C_SLTH_SSLT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTH_SSLT), uint8_t) & BM_I2C_SLTH_SSLT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSLT field to a new value.
+#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_SLTL - I2C SCL Low Timeout Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_sltl
+{
+    uint8_t U;
+    struct _hw_i2c_sltl_bitfields
+    {
+        uint8_t SSLT : 8;              //!< [7:0]
+    } B;
+} hw_i2c_sltl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+//@{
+#define HW_I2C_SLTL_ADDR(x)      (REGS_I2C_BASE(x) + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_SLTL(x)           (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
+#define HW_I2C_SLTL_RD(x)        (HW_I2C_SLTL(x).U)
+#define HW_I2C_SLTL_WR(x, v)     (HW_I2C_SLTL(x).U = (v))
+#define HW_I2C_SLTL_SET(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) |  (v)))
+#define HW_I2C_SLTL_CLR(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
+#define HW_I2C_SLTL_TOG(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_SLTL bitfields
+ */
+
+/*!
+ * @name Register I2C_SLTL, field SSLT[7:0] (RW)
+ *
+ * Least significant byte of SCL low timeout value that determines the timeout
+ * period of SCL low.
+ */
+//@{
+#define BP_I2C_SLTL_SSLT     (0U)          //!< Bit position for I2C_SLTL_SSLT.
+#define BM_I2C_SLTL_SSLT     (0xFFU)       //!< Bit mask for I2C_SLTL_SSLT.
+#define BS_I2C_SLTL_SSLT     (8U)          //!< Bit field size in bits for I2C_SLTL_SSLT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SLTL_SSLT field.
+#define BR_I2C_SLTL_SSLT(x)  (HW_I2C_SLTL(x).U)
+#endif
+
+//! @brief Format value for bitfield I2C_SLTL_SSLT.
+#define BF_I2C_SLTL_SSLT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTL_SSLT), uint8_t) & BM_I2C_SLTL_SSLT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSLT field to a new value.
+#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_i2c_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All I2C module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_i2c
+{
+    __IO hw_i2c_a1_t A1;                   //!< [0x0] I2C Address Register 1
+    __IO hw_i2c_f_t F;                     //!< [0x1] I2C Frequency Divider register
+    __IO hw_i2c_c1_t C1;                   //!< [0x2] I2C Control Register 1
+    __IO hw_i2c_s_t S;                     //!< [0x3] I2C Status register
+    __IO hw_i2c_d_t D;                     //!< [0x4] I2C Data I/O register
+    __IO hw_i2c_c2_t C2;                   //!< [0x5] I2C Control Register 2
+    __IO hw_i2c_flt_t FLT;                 //!< [0x6] I2C Programmable Input Glitch Filter register
+    __IO hw_i2c_ra_t RA;                   //!< [0x7] I2C Range Address register
+    __IO hw_i2c_smb_t SMB;                 //!< [0x8] I2C SMBus Control and Status register
+    __IO hw_i2c_a2_t A2;                   //!< [0x9] I2C Address Register 2
+    __IO hw_i2c_slth_t SLTH;               //!< [0xA] I2C SCL Low Timeout Register High
+    __IO hw_i2c_sltl_t SLTL;               //!< [0xB] I2C SCL Low Timeout Register Low
+} hw_i2c_t;
+#pragma pack()
+
+//! @brief Macro to access all I2C registers.
+//! @param x I2C instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_I2C(0)</code>.
+#define HW_I2C(x)      (*(hw_i2c_t *) REGS_I2C_BASE(x))
+#endif
+
+#endif // __HW_I2C_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h
new file mode 100644
index 0000000000..8933fbec86
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h
@@ -0,0 +1,3463 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_I2S_REGISTERS_H__
+#define __HW_I2S_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - HW_I2S_TCSR - SAI Transmit Control Register
+ * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - HW_I2S_TDRn - SAI Transmit Data Register
+ * - HW_I2S_TFRn - SAI Transmit FIFO Register
+ * - HW_I2S_TMR - SAI Transmit Mask Register
+ * - HW_I2S_RCSR - SAI Receive Control Register
+ * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - HW_I2S_RDRn - SAI Receive Data Register
+ * - HW_I2S_RFRn - SAI Receive FIFO Register
+ * - HW_I2S_RMR - SAI Receive Mask Register
+ * - HW_I2S_MCR - SAI MCLK Control Register
+ * - HW_I2S_MDR - SAI MCLK Divide Register
+ *
+ * - hw_i2s_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_I2S_BASE
+#define HW_I2S_INSTANCE_COUNT (1U) //!< Number of instances of the I2S module.
+#define HW_I2S0 (0U) //!< Instance number for I2S0.
+#define REGS_I2S0_BASE (0x4002F000U) //!< Base address for I2S0.
+
+//! @brief Table of base addresses for I2S instances.
+static const uint32_t __g_regs_I2S_base_addresses[] = {
+        REGS_I2S0_BASE,
+    };
+
+//! @brief Get the base address of I2S by instance number.
+//! @param x I2S instance number, from 0 through 0.
+#define REGS_I2S_BASE(x) (__g_regs_I2S_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of I2S.
+#define REGS_I2S_INSTANCE(b) ((b) == REGS_I2S0_BASE ? HW_I2S0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCSR - SAI Transmit Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_tcsr
+{
+    uint32_t U;
+    struct _hw_i2s_tcsr_bitfields
+    {
+        uint32_t FRDE : 1;             //!< [0] FIFO Request DMA Enable
+        uint32_t FWDE : 1;             //!< [1] FIFO Warning DMA Enable
+        uint32_t RESERVED0 : 6;        //!< [7:2]
+        uint32_t FRIE : 1;             //!< [8] FIFO Request Interrupt Enable
+        uint32_t FWIE : 1;             //!< [9] FIFO Warning Interrupt Enable
+        uint32_t FEIE : 1;             //!< [10] FIFO Error Interrupt Enable
+        uint32_t SEIE : 1;             //!< [11] Sync Error Interrupt Enable
+        uint32_t WSIE : 1;             //!< [12] Word Start Interrupt Enable
+        uint32_t RESERVED1 : 3;        //!< [15:13]
+        uint32_t FRF : 1;              //!< [16] FIFO Request Flag
+        uint32_t FWF : 1;              //!< [17] FIFO Warning Flag
+        uint32_t FEF : 1;              //!< [18] FIFO Error Flag
+        uint32_t SEF : 1;              //!< [19] Sync Error Flag
+        uint32_t WSF : 1;              //!< [20] Word Start Flag
+        uint32_t RESERVED2 : 3;        //!< [23:21]
+        uint32_t SR : 1;               //!< [24] Software Reset
+        uint32_t FR : 1;               //!< [25] FIFO Reset
+        uint32_t RESERVED3 : 2;        //!< [27:26]
+        uint32_t BCE : 1;              //!< [28] Bit Clock Enable
+        uint32_t DBGE : 1;             //!< [29] Debug Enable
+        uint32_t STOPE : 1;            //!< [30] Stop Enable
+        uint32_t TE : 1;               //!< [31] Transmitter Enable
+    } B;
+} hw_i2s_tcsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+//@{
+#define HW_I2S_TCSR_ADDR(x)      (REGS_I2S_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCSR(x)           (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
+#define HW_I2S_TCSR_RD(x)        (HW_I2S_TCSR(x).U)
+#define HW_I2S_TCSR_WR(x, v)     (HW_I2S_TCSR(x).U = (v))
+#define HW_I2S_TCSR_SET(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) |  (v)))
+#define HW_I2S_TCSR_CLR(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
+#define HW_I2S_TCSR_TOG(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_TCSR_FRDE     (0U)          //!< Bit position for I2S_TCSR_FRDE.
+#define BM_I2S_TCSR_FRDE     (0x00000001U) //!< Bit mask for I2S_TCSR_FRDE.
+#define BS_I2S_TCSR_FRDE     (1U)          //!< Bit field size in bits for I2S_TCSR_FRDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FRDE field.
+#define BR_I2S_TCSR_FRDE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FRDE.
+#define BF_I2S_TCSR_FRDE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRDE), uint32_t) & BM_I2S_TCSR_FRDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRDE field to a new value.
+#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_TCSR_FWDE     (1U)          //!< Bit position for I2S_TCSR_FWDE.
+#define BM_I2S_TCSR_FWDE     (0x00000002U) //!< Bit mask for I2S_TCSR_FWDE.
+#define BS_I2S_TCSR_FWDE     (1U)          //!< Bit field size in bits for I2S_TCSR_FWDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FWDE field.
+#define BR_I2S_TCSR_FWDE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FWDE.
+#define BF_I2S_TCSR_FWDE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWDE), uint32_t) & BM_I2S_TCSR_FWDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWDE field to a new value.
+#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_FRIE     (8U)          //!< Bit position for I2S_TCSR_FRIE.
+#define BM_I2S_TCSR_FRIE     (0x00000100U) //!< Bit mask for I2S_TCSR_FRIE.
+#define BS_I2S_TCSR_FRIE     (1U)          //!< Bit field size in bits for I2S_TCSR_FRIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FRIE field.
+#define BR_I2S_TCSR_FRIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FRIE.
+#define BF_I2S_TCSR_FRIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRIE), uint32_t) & BM_I2S_TCSR_FRIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRIE field to a new value.
+#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_FWIE     (9U)          //!< Bit position for I2S_TCSR_FWIE.
+#define BM_I2S_TCSR_FWIE     (0x00000200U) //!< Bit mask for I2S_TCSR_FWIE.
+#define BS_I2S_TCSR_FWIE     (1U)          //!< Bit field size in bits for I2S_TCSR_FWIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FWIE field.
+#define BR_I2S_TCSR_FWIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FWIE.
+#define BF_I2S_TCSR_FWIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWIE), uint32_t) & BM_I2S_TCSR_FWIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWIE field to a new value.
+#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_FEIE     (10U)         //!< Bit position for I2S_TCSR_FEIE.
+#define BM_I2S_TCSR_FEIE     (0x00000400U) //!< Bit mask for I2S_TCSR_FEIE.
+#define BS_I2S_TCSR_FEIE     (1U)          //!< Bit field size in bits for I2S_TCSR_FEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FEIE field.
+#define BR_I2S_TCSR_FEIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FEIE.
+#define BF_I2S_TCSR_FEIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEIE), uint32_t) & BM_I2S_TCSR_FEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEIE field to a new value.
+#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_SEIE     (11U)         //!< Bit position for I2S_TCSR_SEIE.
+#define BM_I2S_TCSR_SEIE     (0x00000800U) //!< Bit mask for I2S_TCSR_SEIE.
+#define BS_I2S_TCSR_SEIE     (1U)          //!< Bit field size in bits for I2S_TCSR_SEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_SEIE field.
+#define BR_I2S_TCSR_SEIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_SEIE.
+#define BF_I2S_TCSR_SEIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEIE), uint32_t) & BM_I2S_TCSR_SEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEIE field to a new value.
+#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_WSIE     (12U)         //!< Bit position for I2S_TCSR_WSIE.
+#define BM_I2S_TCSR_WSIE     (0x00001000U) //!< Bit mask for I2S_TCSR_WSIE.
+#define BS_I2S_TCSR_WSIE     (1U)          //!< Bit field size in bits for I2S_TCSR_WSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_WSIE field.
+#define BR_I2S_TCSR_WSIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_WSIE.
+#define BF_I2S_TCSR_WSIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSIE), uint32_t) & BM_I2S_TCSR_WSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSIE field to a new value.
+#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0 - Transmit FIFO watermark has not been reached.
+ * - 1 - Transmit FIFO watermark has been reached.
+ */
+//@{
+#define BP_I2S_TCSR_FRF      (16U)         //!< Bit position for I2S_TCSR_FRF.
+#define BM_I2S_TCSR_FRF      (0x00010000U) //!< Bit mask for I2S_TCSR_FRF.
+#define BS_I2S_TCSR_FRF      (1U)          //!< Bit field size in bits for I2S_TCSR_FRF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FRF field.
+#define BR_I2S_TCSR_FRF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0 - No enabled transmit FIFO is empty.
+ * - 1 - Enabled transmit FIFO is empty.
+ */
+//@{
+#define BP_I2S_TCSR_FWF      (17U)         //!< Bit position for I2S_TCSR_FWF.
+#define BM_I2S_TCSR_FWF      (0x00020000U) //!< Bit mask for I2S_TCSR_FWF.
+#define BS_I2S_TCSR_FWF      (1U)          //!< Bit field size in bits for I2S_TCSR_FWF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FWF field.
+#define BR_I2S_TCSR_FWF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0 - Transmit underrun not detected.
+ * - 1 - Transmit underrun detected.
+ */
+//@{
+#define BP_I2S_TCSR_FEF      (18U)         //!< Bit position for I2S_TCSR_FEF.
+#define BM_I2S_TCSR_FEF      (0x00040000U) //!< Bit mask for I2S_TCSR_FEF.
+#define BS_I2S_TCSR_FEF      (1U)          //!< Bit field size in bits for I2S_TCSR_FEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FEF field.
+#define BR_I2S_TCSR_FEF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FEF.
+#define BF_I2S_TCSR_FEF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEF), uint32_t) & BM_I2S_TCSR_FEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEF field to a new value.
+#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Sync error not detected.
+ * - 1 - Frame sync error detected.
+ */
+//@{
+#define BP_I2S_TCSR_SEF      (19U)         //!< Bit position for I2S_TCSR_SEF.
+#define BM_I2S_TCSR_SEF      (0x00080000U) //!< Bit mask for I2S_TCSR_SEF.
+#define BS_I2S_TCSR_SEF      (1U)          //!< Bit field size in bits for I2S_TCSR_SEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_SEF field.
+#define BR_I2S_TCSR_SEF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_SEF.
+#define BF_I2S_TCSR_SEF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEF), uint32_t) & BM_I2S_TCSR_SEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEF field to a new value.
+#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Start of word not detected.
+ * - 1 - Start of word detected.
+ */
+//@{
+#define BP_I2S_TCSR_WSF      (20U)         //!< Bit position for I2S_TCSR_WSF.
+#define BM_I2S_TCSR_WSF      (0x00100000U) //!< Bit mask for I2S_TCSR_WSF.
+#define BS_I2S_TCSR_WSF      (1U)          //!< Bit field size in bits for I2S_TCSR_WSF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_WSF field.
+#define BR_I2S_TCSR_WSF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_WSF.
+#define BF_I2S_TCSR_WSF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSF), uint32_t) & BM_I2S_TCSR_WSF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSF field to a new value.
+#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Software reset.
+ */
+//@{
+#define BP_I2S_TCSR_SR       (24U)         //!< Bit position for I2S_TCSR_SR.
+#define BM_I2S_TCSR_SR       (0x01000000U) //!< Bit mask for I2S_TCSR_SR.
+#define BS_I2S_TCSR_SR       (1U)          //!< Bit field size in bits for I2S_TCSR_SR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_SR field.
+#define BR_I2S_TCSR_SR(x)    (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_SR.
+#define BF_I2S_TCSR_SR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SR), uint32_t) & BM_I2S_TCSR_SR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SR field to a new value.
+#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - FIFO reset.
+ */
+//@{
+#define BP_I2S_TCSR_FR       (25U)         //!< Bit position for I2S_TCSR_FR.
+#define BM_I2S_TCSR_FR       (0x02000000U) //!< Bit mask for I2S_TCSR_FR.
+#define BS_I2S_TCSR_FR       (1U)          //!< Bit field size in bits for I2S_TCSR_FR.
+
+//! @brief Format value for bitfield I2S_TCSR_FR.
+#define BF_I2S_TCSR_FR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FR), uint32_t) & BM_I2S_TCSR_FR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FR field to a new value.
+#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0 - Transmit bit clock is disabled.
+ * - 1 - Transmit bit clock is enabled.
+ */
+//@{
+#define BP_I2S_TCSR_BCE      (28U)         //!< Bit position for I2S_TCSR_BCE.
+#define BM_I2S_TCSR_BCE      (0x10000000U) //!< Bit mask for I2S_TCSR_BCE.
+#define BS_I2S_TCSR_BCE      (1U)          //!< Bit field size in bits for I2S_TCSR_BCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_BCE field.
+#define BR_I2S_TCSR_BCE(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_BCE.
+#define BF_I2S_TCSR_BCE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_BCE), uint32_t) & BM_I2S_TCSR_BCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCE field to a new value.
+#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 1 - Transmitter is enabled in Debug mode.
+ */
+//@{
+#define BP_I2S_TCSR_DBGE     (29U)         //!< Bit position for I2S_TCSR_DBGE.
+#define BM_I2S_TCSR_DBGE     (0x20000000U) //!< Bit mask for I2S_TCSR_DBGE.
+#define BS_I2S_TCSR_DBGE     (1U)          //!< Bit field size in bits for I2S_TCSR_DBGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_DBGE field.
+#define BR_I2S_TCSR_DBGE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_DBGE.
+#define BF_I2S_TCSR_DBGE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_DBGE), uint32_t) & BM_I2S_TCSR_DBGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGE field to a new value.
+#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - Transmitter disabled in Stop mode.
+ * - 1 - Transmitter enabled in Stop mode.
+ */
+//@{
+#define BP_I2S_TCSR_STOPE    (30U)         //!< Bit position for I2S_TCSR_STOPE.
+#define BM_I2S_TCSR_STOPE    (0x40000000U) //!< Bit mask for I2S_TCSR_STOPE.
+#define BS_I2S_TCSR_STOPE    (1U)          //!< Bit field size in bits for I2S_TCSR_STOPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_STOPE field.
+#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_STOPE.
+#define BF_I2S_TCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_STOPE), uint32_t) & BM_I2S_TCSR_STOPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPE field to a new value.
+#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0 - Transmitter is disabled.
+ * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+//@{
+#define BP_I2S_TCSR_TE       (31U)         //!< Bit position for I2S_TCSR_TE.
+#define BM_I2S_TCSR_TE       (0x80000000U) //!< Bit mask for I2S_TCSR_TE.
+#define BS_I2S_TCSR_TE       (1U)          //!< Bit field size in bits for I2S_TCSR_TE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_TE field.
+#define BR_I2S_TCSR_TE(x)    (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_TE.
+#define BF_I2S_TCSR_TE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_TE), uint32_t) & BM_I2S_TCSR_TE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TE field to a new value.
+#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_tcr1
+{
+    uint32_t U;
+    struct _hw_i2s_tcr1_bitfields
+    {
+        uint32_t TFW : 3;              //!< [2:0] Transmit FIFO Watermark
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_i2s_tcr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+//@{
+#define HW_I2S_TCR1_ADDR(x)      (REGS_I2S_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR1(x)           (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
+#define HW_I2S_TCR1_RD(x)        (HW_I2S_TCR1(x).U)
+#define HW_I2S_TCR1_WR(x, v)     (HW_I2S_TCR1(x).U = (v))
+#define HW_I2S_TCR1_SET(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) |  (v)))
+#define HW_I2S_TCR1_CLR(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
+#define HW_I2S_TCR1_TOG(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+//@{
+#define BP_I2S_TCR1_TFW      (0U)          //!< Bit position for I2S_TCR1_TFW.
+#define BM_I2S_TCR1_TFW      (0x00000007U) //!< Bit mask for I2S_TCR1_TFW.
+#define BS_I2S_TCR1_TFW      (3U)          //!< Bit field size in bits for I2S_TCR1_TFW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR1_TFW field.
+#define BR_I2S_TCR1_TFW(x)   (HW_I2S_TCR1(x).B.TFW)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR1_TFW.
+#define BF_I2S_TCR1_TFW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR1_TFW), uint32_t) & BM_I2S_TCR1_TFW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFW field to a new value.
+#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr2
+{
+    uint32_t U;
+    struct _hw_i2s_tcr2_bitfields
+    {
+        uint32_t DIV : 8;              //!< [7:0] Bit Clock Divide
+        uint32_t RESERVED0 : 16;       //!< [23:8]
+        uint32_t BCD : 1;              //!< [24] Bit Clock Direction
+        uint32_t BCP : 1;              //!< [25] Bit Clock Polarity
+        uint32_t MSEL : 2;             //!< [27:26] MCLK Select
+        uint32_t BCI : 1;              //!< [28] Bit Clock Input
+        uint32_t BCS : 1;              //!< [29] Bit Clock Swap
+        uint32_t SYNC : 2;             //!< [31:30] Synchronous Mode
+    } B;
+} hw_i2s_tcr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+//@{
+#define HW_I2S_TCR2_ADDR(x)      (REGS_I2S_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR2(x)           (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
+#define HW_I2S_TCR2_RD(x)        (HW_I2S_TCR2(x).U)
+#define HW_I2S_TCR2_WR(x, v)     (HW_I2S_TCR2(x).U = (v))
+#define HW_I2S_TCR2_SET(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) |  (v)))
+#define HW_I2S_TCR2_CLR(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
+#define HW_I2S_TCR2_TOG(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+//@{
+#define BP_I2S_TCR2_DIV      (0U)          //!< Bit position for I2S_TCR2_DIV.
+#define BM_I2S_TCR2_DIV      (0x000000FFU) //!< Bit mask for I2S_TCR2_DIV.
+#define BS_I2S_TCR2_DIV      (8U)          //!< Bit field size in bits for I2S_TCR2_DIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_DIV field.
+#define BR_I2S_TCR2_DIV(x)   (HW_I2S_TCR2(x).B.DIV)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_DIV.
+#define BF_I2S_TCR2_DIV(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_DIV), uint32_t) & BM_I2S_TCR2_DIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIV field to a new value.
+#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is generated externally in Slave mode.
+ * - 1 - Bit clock is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_TCR2_BCD      (24U)         //!< Bit position for I2S_TCR2_BCD.
+#define BM_I2S_TCR2_BCD      (0x01000000U) //!< Bit mask for I2S_TCR2_BCD.
+#define BS_I2S_TCR2_BCD      (1U)          //!< Bit field size in bits for I2S_TCR2_BCD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCD field.
+#define BR_I2S_TCR2_BCD(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCD.
+#define BF_I2S_TCR2_BCD(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCD), uint32_t) & BM_I2S_TCR2_BCD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCD field to a new value.
+#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+//@{
+#define BP_I2S_TCR2_BCP      (25U)         //!< Bit position for I2S_TCR2_BCP.
+#define BM_I2S_TCR2_BCP      (0x02000000U) //!< Bit mask for I2S_TCR2_BCP.
+#define BS_I2S_TCR2_BCP      (1U)          //!< Bit field size in bits for I2S_TCR2_BCP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCP field.
+#define BR_I2S_TCR2_BCP(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCP.
+#define BF_I2S_TCR2_BCP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCP), uint32_t) & BM_I2S_TCR2_BCP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCP field to a new value.
+#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 00 - Bus Clock selected.
+ * - 01 - Master Clock (MCLK) 1 option selected.
+ * - 10 - Master Clock (MCLK) 2 option selected.
+ * - 11 - Master Clock (MCLK) 3 option selected.
+ */
+//@{
+#define BP_I2S_TCR2_MSEL     (26U)         //!< Bit position for I2S_TCR2_MSEL.
+#define BM_I2S_TCR2_MSEL     (0x0C000000U) //!< Bit mask for I2S_TCR2_MSEL.
+#define BS_I2S_TCR2_MSEL     (2U)          //!< Bit field size in bits for I2S_TCR2_MSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_MSEL field.
+#define BR_I2S_TCR2_MSEL(x)  (HW_I2S_TCR2(x).B.MSEL)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_MSEL.
+#define BF_I2S_TCR2_MSEL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_MSEL), uint32_t) & BM_I2S_TCR2_MSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSEL field to a new value.
+#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+//@{
+#define BP_I2S_TCR2_BCI      (28U)         //!< Bit position for I2S_TCR2_BCI.
+#define BM_I2S_TCR2_BCI      (0x10000000U) //!< Bit mask for I2S_TCR2_BCI.
+#define BS_I2S_TCR2_BCI      (1U)          //!< Bit field size in bits for I2S_TCR2_BCI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCI field.
+#define BR_I2S_TCR2_BCI(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCI.
+#define BF_I2S_TCR2_BCI(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCI), uint32_t) & BM_I2S_TCR2_BCI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCI field to a new value.
+#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0 - Use the normal bit clock source.
+ * - 1 - Swap the bit clock source.
+ */
+//@{
+#define BP_I2S_TCR2_BCS      (29U)         //!< Bit position for I2S_TCR2_BCS.
+#define BM_I2S_TCR2_BCS      (0x20000000U) //!< Bit mask for I2S_TCR2_BCS.
+#define BS_I2S_TCR2_BCS      (1U)          //!< Bit field size in bits for I2S_TCR2_BCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCS field.
+#define BR_I2S_TCR2_BCS(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCS.
+#define BF_I2S_TCR2_BCS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCS), uint32_t) & BM_I2S_TCR2_BCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCS field to a new value.
+#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 00 - Asynchronous mode.
+ * - 01 - Synchronous with receiver.
+ * - 10 - Synchronous with another SAI transmitter.
+ * - 11 - Synchronous with another SAI receiver.
+ */
+//@{
+#define BP_I2S_TCR2_SYNC     (30U)         //!< Bit position for I2S_TCR2_SYNC.
+#define BM_I2S_TCR2_SYNC     (0xC0000000U) //!< Bit mask for I2S_TCR2_SYNC.
+#define BS_I2S_TCR2_SYNC     (2U)          //!< Bit field size in bits for I2S_TCR2_SYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_SYNC field.
+#define BR_I2S_TCR2_SYNC(x)  (HW_I2S_TCR2(x).B.SYNC)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_SYNC.
+#define BF_I2S_TCR2_SYNC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_SYNC), uint32_t) & BM_I2S_TCR2_SYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNC field to a new value.
+#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr3
+{
+    uint32_t U;
+    struct _hw_i2s_tcr3_bitfields
+    {
+        uint32_t WDFL : 5;             //!< [4:0] Word Flag Configuration
+        uint32_t RESERVED0 : 11;       //!< [15:5]
+        uint32_t TCE : 2;              //!< [17:16] Transmit Channel Enable
+        uint32_t RESERVED1 : 14;       //!< [31:18]
+    } B;
+} hw_i2s_tcr3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+//@{
+#define HW_I2S_TCR3_ADDR(x)      (REGS_I2S_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR3(x)           (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
+#define HW_I2S_TCR3_RD(x)        (HW_I2S_TCR3(x).U)
+#define HW_I2S_TCR3_WR(x, v)     (HW_I2S_TCR3(x).U = (v))
+#define HW_I2S_TCR3_SET(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) |  (v)))
+#define HW_I2S_TCR3_CLR(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
+#define HW_I2S_TCR3_TOG(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+//@{
+#define BP_I2S_TCR3_WDFL     (0U)          //!< Bit position for I2S_TCR3_WDFL.
+#define BM_I2S_TCR3_WDFL     (0x0000001FU) //!< Bit mask for I2S_TCR3_WDFL.
+#define BS_I2S_TCR3_WDFL     (5U)          //!< Bit field size in bits for I2S_TCR3_WDFL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR3_WDFL field.
+#define BR_I2S_TCR3_WDFL(x)  (HW_I2S_TCR3(x).B.WDFL)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR3_WDFL.
+#define BF_I2S_TCR3_WDFL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_WDFL), uint32_t) & BM_I2S_TCR3_WDFL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDFL field to a new value.
+#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0 - Transmit data channel N is disabled.
+ * - 1 - Transmit data channel N is enabled.
+ */
+//@{
+#define BP_I2S_TCR3_TCE      (16U)         //!< Bit position for I2S_TCR3_TCE.
+#define BM_I2S_TCR3_TCE      (0x00030000U) //!< Bit mask for I2S_TCR3_TCE.
+#define BS_I2S_TCR3_TCE      (2U)          //!< Bit field size in bits for I2S_TCR3_TCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR3_TCE field.
+#define BR_I2S_TCR3_TCE(x)   (HW_I2S_TCR3(x).B.TCE)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR3_TCE.
+#define BF_I2S_TCR3_TCE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_TCE), uint32_t) & BM_I2S_TCR3_TCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCE field to a new value.
+#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr4
+{
+    uint32_t U;
+    struct _hw_i2s_tcr4_bitfields
+    {
+        uint32_t FSD : 1;              //!< [0] Frame Sync Direction
+        uint32_t FSP : 1;              //!< [1] Frame Sync Polarity
+        uint32_t RESERVED0 : 1;        //!< [2]
+        uint32_t FSE : 1;              //!< [3] Frame Sync Early
+        uint32_t MF : 1;               //!< [4] MSB First
+        uint32_t RESERVED1 : 3;        //!< [7:5]
+        uint32_t SYWD : 5;             //!< [12:8] Sync Width
+        uint32_t RESERVED2 : 3;        //!< [15:13]
+        uint32_t FRSZ : 5;             //!< [20:16] Frame size
+        uint32_t RESERVED3 : 11;       //!< [31:21]
+    } B;
+} hw_i2s_tcr4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+//@{
+#define HW_I2S_TCR4_ADDR(x)      (REGS_I2S_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR4(x)           (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
+#define HW_I2S_TCR4_RD(x)        (HW_I2S_TCR4(x).U)
+#define HW_I2S_TCR4_WR(x, v)     (HW_I2S_TCR4(x).U = (v))
+#define HW_I2S_TCR4_SET(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) |  (v)))
+#define HW_I2S_TCR4_CLR(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
+#define HW_I2S_TCR4_TOG(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is generated externally in Slave mode.
+ * - 1 - Frame sync is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_TCR4_FSD      (0U)          //!< Bit position for I2S_TCR4_FSD.
+#define BM_I2S_TCR4_FSD      (0x00000001U) //!< Bit mask for I2S_TCR4_FSD.
+#define BS_I2S_TCR4_FSD      (1U)          //!< Bit field size in bits for I2S_TCR4_FSD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FSD field.
+#define BR_I2S_TCR4_FSD(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FSD.
+#define BF_I2S_TCR4_FSD(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSD), uint32_t) & BM_I2S_TCR4_FSD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSD field to a new value.
+#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is active high.
+ * - 1 - Frame sync is active low.
+ */
+//@{
+#define BP_I2S_TCR4_FSP      (1U)          //!< Bit position for I2S_TCR4_FSP.
+#define BM_I2S_TCR4_FSP      (0x00000002U) //!< Bit mask for I2S_TCR4_FSP.
+#define BS_I2S_TCR4_FSP      (1U)          //!< Bit field size in bits for I2S_TCR4_FSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FSP field.
+#define BR_I2S_TCR4_FSP(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FSP.
+#define BF_I2S_TCR4_FSP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSP), uint32_t) & BM_I2S_TCR4_FSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSP field to a new value.
+#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0 - Frame sync asserts with the first bit of the frame.
+ * - 1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+//@{
+#define BP_I2S_TCR4_FSE      (3U)          //!< Bit position for I2S_TCR4_FSE.
+#define BM_I2S_TCR4_FSE      (0x00000008U) //!< Bit mask for I2S_TCR4_FSE.
+#define BS_I2S_TCR4_FSE      (1U)          //!< Bit field size in bits for I2S_TCR4_FSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FSE field.
+#define BR_I2S_TCR4_FSE(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FSE.
+#define BF_I2S_TCR4_FSE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSE), uint32_t) & BM_I2S_TCR4_FSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSE field to a new value.
+#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0 - LSB is transmitted first.
+ * - 1 - MSB is transmitted first.
+ */
+//@{
+#define BP_I2S_TCR4_MF       (4U)          //!< Bit position for I2S_TCR4_MF.
+#define BM_I2S_TCR4_MF       (0x00000010U) //!< Bit mask for I2S_TCR4_MF.
+#define BS_I2S_TCR4_MF       (1U)          //!< Bit field size in bits for I2S_TCR4_MF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_MF field.
+#define BR_I2S_TCR4_MF(x)    (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_MF.
+#define BF_I2S_TCR4_MF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_MF), uint32_t) & BM_I2S_TCR4_MF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MF field to a new value.
+#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+//@{
+#define BP_I2S_TCR4_SYWD     (8U)          //!< Bit position for I2S_TCR4_SYWD.
+#define BM_I2S_TCR4_SYWD     (0x00001F00U) //!< Bit mask for I2S_TCR4_SYWD.
+#define BS_I2S_TCR4_SYWD     (5U)          //!< Bit field size in bits for I2S_TCR4_SYWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_SYWD field.
+#define BR_I2S_TCR4_SYWD(x)  (HW_I2S_TCR4(x).B.SYWD)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_SYWD.
+#define BF_I2S_TCR4_SYWD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_SYWD), uint32_t) & BM_I2S_TCR4_SYWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYWD field to a new value.
+#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+//@{
+#define BP_I2S_TCR4_FRSZ     (16U)         //!< Bit position for I2S_TCR4_FRSZ.
+#define BM_I2S_TCR4_FRSZ     (0x001F0000U) //!< Bit mask for I2S_TCR4_FRSZ.
+#define BS_I2S_TCR4_FRSZ     (5U)          //!< Bit field size in bits for I2S_TCR4_FRSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FRSZ field.
+#define BR_I2S_TCR4_FRSZ(x)  (HW_I2S_TCR4(x).B.FRSZ)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FRSZ.
+#define BF_I2S_TCR4_FRSZ(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FRSZ), uint32_t) & BM_I2S_TCR4_FRSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRSZ field to a new value.
+#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr5
+{
+    uint32_t U;
+    struct _hw_i2s_tcr5_bitfields
+    {
+        uint32_t RESERVED0 : 8;        //!< [7:0]
+        uint32_t FBT : 5;              //!< [12:8] First Bit Shifted
+        uint32_t RESERVED1 : 3;        //!< [15:13]
+        uint32_t W0W : 5;              //!< [20:16] Word 0 Width
+        uint32_t RESERVED2 : 3;        //!< [23:21]
+        uint32_t WNW : 5;              //!< [28:24] Word N Width
+        uint32_t RESERVED3 : 3;        //!< [31:29]
+    } B;
+} hw_i2s_tcr5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+//@{
+#define HW_I2S_TCR5_ADDR(x)      (REGS_I2S_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR5(x)           (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
+#define HW_I2S_TCR5_RD(x)        (HW_I2S_TCR5(x).U)
+#define HW_I2S_TCR5_WR(x, v)     (HW_I2S_TCR5(x).U = (v))
+#define HW_I2S_TCR5_SET(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) |  (v)))
+#define HW_I2S_TCR5_CLR(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
+#define HW_I2S_TCR5_TOG(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+//@{
+#define BP_I2S_TCR5_FBT      (8U)          //!< Bit position for I2S_TCR5_FBT.
+#define BM_I2S_TCR5_FBT      (0x00001F00U) //!< Bit mask for I2S_TCR5_FBT.
+#define BS_I2S_TCR5_FBT      (5U)          //!< Bit field size in bits for I2S_TCR5_FBT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR5_FBT field.
+#define BR_I2S_TCR5_FBT(x)   (HW_I2S_TCR5(x).B.FBT)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR5_FBT.
+#define BF_I2S_TCR5_FBT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_FBT), uint32_t) & BM_I2S_TCR5_FBT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FBT field to a new value.
+#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+//@{
+#define BP_I2S_TCR5_W0W      (16U)         //!< Bit position for I2S_TCR5_W0W.
+#define BM_I2S_TCR5_W0W      (0x001F0000U) //!< Bit mask for I2S_TCR5_W0W.
+#define BS_I2S_TCR5_W0W      (5U)          //!< Bit field size in bits for I2S_TCR5_W0W.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR5_W0W field.
+#define BR_I2S_TCR5_W0W(x)   (HW_I2S_TCR5(x).B.W0W)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR5_W0W.
+#define BF_I2S_TCR5_W0W(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_W0W), uint32_t) & BM_I2S_TCR5_W0W)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the W0W field to a new value.
+#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+//@{
+#define BP_I2S_TCR5_WNW      (24U)         //!< Bit position for I2S_TCR5_WNW.
+#define BM_I2S_TCR5_WNW      (0x1F000000U) //!< Bit mask for I2S_TCR5_WNW.
+#define BS_I2S_TCR5_WNW      (5U)          //!< Bit field size in bits for I2S_TCR5_WNW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR5_WNW field.
+#define BR_I2S_TCR5_WNW(x)   (HW_I2S_TCR5(x).B.WNW)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR5_WNW.
+#define BF_I2S_TCR5_WNW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_WNW), uint32_t) & BM_I2S_TCR5_WNW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WNW field to a new value.
+#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TDRn - SAI Transmit Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_tdrn
+{
+    uint32_t U;
+    struct _hw_i2s_tdrn_bitfields
+    {
+        uint32_t TDR : 32;             //!< [31:0] Transmit Data Register
+    } B;
+} hw_i2s_tdrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TDRn register
+ */
+//@{
+#define HW_I2S_TDRn_COUNT (2U)
+
+#define HW_I2S_TDRn_ADDR(x, n)   (REGS_I2S_BASE(x) + 0x20U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TDRn(x, n)        (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
+#define HW_I2S_TDRn_RD(x, n)     (HW_I2S_TDRn(x, n).U)
+#define HW_I2S_TDRn_WR(x, n, v)  (HW_I2S_TDRn(x, n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TDRn bitfields
+ */
+
+/*!
+ * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
+ *
+ * The corresponding TCR3[TCE] bit must be set before accessing the channel's
+ * transmit data register. Writes to this register when the transmit FIFO is not
+ * full will push the data written into the transmit data FIFO. Writes to this
+ * register when the transmit FIFO is full are ignored.
+ */
+//@{
+#define BP_I2S_TDRn_TDR      (0U)          //!< Bit position for I2S_TDRn_TDR.
+#define BM_I2S_TDRn_TDR      (0xFFFFFFFFU) //!< Bit mask for I2S_TDRn_TDR.
+#define BS_I2S_TDRn_TDR      (32U)         //!< Bit field size in bits for I2S_TDRn_TDR.
+
+//! @brief Format value for bitfield I2S_TDRn_TDR.
+#define BF_I2S_TDRn_TDR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TDRn_TDR), uint32_t) & BM_I2S_TDRn_TDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDR field to a new value.
+#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TFRn - SAI Transmit FIFO Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+typedef union _hw_i2s_tfrn
+{
+    uint32_t U;
+    struct _hw_i2s_tfrn_bitfields
+    {
+        uint32_t RFP : 4;              //!< [3:0] Read FIFO Pointer
+        uint32_t RESERVED0 : 12;       //!< [15:4]
+        uint32_t WFP : 4;              //!< [19:16] Write FIFO Pointer
+        uint32_t RESERVED1 : 12;       //!< [31:20]
+    } B;
+} hw_i2s_tfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TFRn register
+ */
+//@{
+#define HW_I2S_TFRn_COUNT (2U)
+
+#define HW_I2S_TFRn_ADDR(x, n)   (REGS_I2S_BASE(x) + 0x40U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TFRn(x, n)        (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
+#define HW_I2S_TFRn_RD(x, n)     (HW_I2S_TFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TFRn bitfields
+ */
+
+/*!
+ * @name Register I2S_TFRn, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+//@{
+#define BP_I2S_TFRn_RFP      (0U)          //!< Bit position for I2S_TFRn_RFP.
+#define BM_I2S_TFRn_RFP      (0x0000000FU) //!< Bit mask for I2S_TFRn_RFP.
+#define BS_I2S_TFRn_RFP      (4U)          //!< Bit field size in bits for I2S_TFRn_RFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TFRn_RFP field.
+#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TFRn, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+//@{
+#define BP_I2S_TFRn_WFP      (16U)         //!< Bit position for I2S_TFRn_WFP.
+#define BM_I2S_TFRn_WFP      (0x000F0000U) //!< Bit mask for I2S_TFRn_WFP.
+#define BS_I2S_TFRn_WFP      (4U)          //!< Bit field size in bits for I2S_TFRn_WFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TFRn_WFP field.
+#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TMR - SAI Transmit Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+typedef union _hw_i2s_tmr
+{
+    uint32_t U;
+    struct _hw_i2s_tmr_bitfields
+    {
+        uint32_t TWM : 32;             //!< [31:0] Transmit Word Mask
+    } B;
+} hw_i2s_tmr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+//@{
+#define HW_I2S_TMR_ADDR(x)       (REGS_I2S_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TMR(x)            (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
+#define HW_I2S_TMR_RD(x)         (HW_I2S_TMR(x).U)
+#define HW_I2S_TMR_WR(x, v)      (HW_I2S_TMR(x).U = (v))
+#define HW_I2S_TMR_SET(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) |  (v)))
+#define HW_I2S_TMR_CLR(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
+#define HW_I2S_TMR_TOG(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TMR bitfields
+ */
+
+/*!
+ * @name Register I2S_TMR, field TWM[31:0] (RW)
+ *
+ * Configures whether the transmit word is masked (transmit data pin tristated
+ * and transmit data not read from FIFO) for the corresponding word in the frame.
+ *
+ * Values:
+ * - 0 - Word N is enabled.
+ * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
+ */
+//@{
+#define BP_I2S_TMR_TWM       (0U)          //!< Bit position for I2S_TMR_TWM.
+#define BM_I2S_TMR_TWM       (0xFFFFFFFFU) //!< Bit mask for I2S_TMR_TWM.
+#define BS_I2S_TMR_TWM       (32U)         //!< Bit field size in bits for I2S_TMR_TWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TMR_TWM field.
+#define BR_I2S_TMR_TWM(x)    (HW_I2S_TMR(x).U)
+#endif
+
+//! @brief Format value for bitfield I2S_TMR_TWM.
+#define BF_I2S_TMR_TWM(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TMR_TWM), uint32_t) & BM_I2S_TMR_TWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWM field to a new value.
+#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCSR - SAI Receive Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_rcsr
+{
+    uint32_t U;
+    struct _hw_i2s_rcsr_bitfields
+    {
+        uint32_t FRDE : 1;             //!< [0] FIFO Request DMA Enable
+        uint32_t FWDE : 1;             //!< [1] FIFO Warning DMA Enable
+        uint32_t RESERVED0 : 6;        //!< [7:2]
+        uint32_t FRIE : 1;             //!< [8] FIFO Request Interrupt Enable
+        uint32_t FWIE : 1;             //!< [9] FIFO Warning Interrupt Enable
+        uint32_t FEIE : 1;             //!< [10] FIFO Error Interrupt Enable
+        uint32_t SEIE : 1;             //!< [11] Sync Error Interrupt Enable
+        uint32_t WSIE : 1;             //!< [12] Word Start Interrupt Enable
+        uint32_t RESERVED1 : 3;        //!< [15:13]
+        uint32_t FRF : 1;              //!< [16] FIFO Request Flag
+        uint32_t FWF : 1;              //!< [17] FIFO Warning Flag
+        uint32_t FEF : 1;              //!< [18] FIFO Error Flag
+        uint32_t SEF : 1;              //!< [19] Sync Error Flag
+        uint32_t WSF : 1;              //!< [20] Word Start Flag
+        uint32_t RESERVED2 : 3;        //!< [23:21]
+        uint32_t SR : 1;               //!< [24] Software Reset
+        uint32_t FR : 1;               //!< [25] FIFO Reset
+        uint32_t RESERVED3 : 2;        //!< [27:26]
+        uint32_t BCE : 1;              //!< [28] Bit Clock Enable
+        uint32_t DBGE : 1;             //!< [29] Debug Enable
+        uint32_t STOPE : 1;            //!< [30] Stop Enable
+        uint32_t RE : 1;               //!< [31] Receiver Enable
+    } B;
+} hw_i2s_rcsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+//@{
+#define HW_I2S_RCSR_ADDR(x)      (REGS_I2S_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCSR(x)           (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
+#define HW_I2S_RCSR_RD(x)        (HW_I2S_RCSR(x).U)
+#define HW_I2S_RCSR_WR(x, v)     (HW_I2S_RCSR(x).U = (v))
+#define HW_I2S_RCSR_SET(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) |  (v)))
+#define HW_I2S_RCSR_CLR(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
+#define HW_I2S_RCSR_TOG(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_RCSR_FRDE     (0U)          //!< Bit position for I2S_RCSR_FRDE.
+#define BM_I2S_RCSR_FRDE     (0x00000001U) //!< Bit mask for I2S_RCSR_FRDE.
+#define BS_I2S_RCSR_FRDE     (1U)          //!< Bit field size in bits for I2S_RCSR_FRDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FRDE field.
+#define BR_I2S_RCSR_FRDE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FRDE.
+#define BF_I2S_RCSR_FRDE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRDE), uint32_t) & BM_I2S_RCSR_FRDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRDE field to a new value.
+#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_RCSR_FWDE     (1U)          //!< Bit position for I2S_RCSR_FWDE.
+#define BM_I2S_RCSR_FWDE     (0x00000002U) //!< Bit mask for I2S_RCSR_FWDE.
+#define BS_I2S_RCSR_FWDE     (1U)          //!< Bit field size in bits for I2S_RCSR_FWDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FWDE field.
+#define BR_I2S_RCSR_FWDE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FWDE.
+#define BF_I2S_RCSR_FWDE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWDE), uint32_t) & BM_I2S_RCSR_FWDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWDE field to a new value.
+#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_FRIE     (8U)          //!< Bit position for I2S_RCSR_FRIE.
+#define BM_I2S_RCSR_FRIE     (0x00000100U) //!< Bit mask for I2S_RCSR_FRIE.
+#define BS_I2S_RCSR_FRIE     (1U)          //!< Bit field size in bits for I2S_RCSR_FRIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FRIE field.
+#define BR_I2S_RCSR_FRIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FRIE.
+#define BF_I2S_RCSR_FRIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRIE), uint32_t) & BM_I2S_RCSR_FRIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRIE field to a new value.
+#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_FWIE     (9U)          //!< Bit position for I2S_RCSR_FWIE.
+#define BM_I2S_RCSR_FWIE     (0x00000200U) //!< Bit mask for I2S_RCSR_FWIE.
+#define BS_I2S_RCSR_FWIE     (1U)          //!< Bit field size in bits for I2S_RCSR_FWIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FWIE field.
+#define BR_I2S_RCSR_FWIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FWIE.
+#define BF_I2S_RCSR_FWIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWIE), uint32_t) & BM_I2S_RCSR_FWIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWIE field to a new value.
+#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_FEIE     (10U)         //!< Bit position for I2S_RCSR_FEIE.
+#define BM_I2S_RCSR_FEIE     (0x00000400U) //!< Bit mask for I2S_RCSR_FEIE.
+#define BS_I2S_RCSR_FEIE     (1U)          //!< Bit field size in bits for I2S_RCSR_FEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FEIE field.
+#define BR_I2S_RCSR_FEIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FEIE.
+#define BF_I2S_RCSR_FEIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEIE), uint32_t) & BM_I2S_RCSR_FEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEIE field to a new value.
+#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_SEIE     (11U)         //!< Bit position for I2S_RCSR_SEIE.
+#define BM_I2S_RCSR_SEIE     (0x00000800U) //!< Bit mask for I2S_RCSR_SEIE.
+#define BS_I2S_RCSR_SEIE     (1U)          //!< Bit field size in bits for I2S_RCSR_SEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_SEIE field.
+#define BR_I2S_RCSR_SEIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_SEIE.
+#define BF_I2S_RCSR_SEIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEIE), uint32_t) & BM_I2S_RCSR_SEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEIE field to a new value.
+#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_WSIE     (12U)         //!< Bit position for I2S_RCSR_WSIE.
+#define BM_I2S_RCSR_WSIE     (0x00001000U) //!< Bit mask for I2S_RCSR_WSIE.
+#define BS_I2S_RCSR_WSIE     (1U)          //!< Bit field size in bits for I2S_RCSR_WSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_WSIE field.
+#define BR_I2S_RCSR_WSIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_WSIE.
+#define BF_I2S_RCSR_WSIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSIE), uint32_t) & BM_I2S_RCSR_WSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSIE field to a new value.
+#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0 - Receive FIFO watermark not reached.
+ * - 1 - Receive FIFO watermark has been reached.
+ */
+//@{
+#define BP_I2S_RCSR_FRF      (16U)         //!< Bit position for I2S_RCSR_FRF.
+#define BM_I2S_RCSR_FRF      (0x00010000U) //!< Bit mask for I2S_RCSR_FRF.
+#define BS_I2S_RCSR_FRF      (1U)          //!< Bit field size in bits for I2S_RCSR_FRF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FRF field.
+#define BR_I2S_RCSR_FRF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0 - No enabled receive FIFO is full.
+ * - 1 - Enabled receive FIFO is full.
+ */
+//@{
+#define BP_I2S_RCSR_FWF      (17U)         //!< Bit position for I2S_RCSR_FWF.
+#define BM_I2S_RCSR_FWF      (0x00020000U) //!< Bit mask for I2S_RCSR_FWF.
+#define BS_I2S_RCSR_FWF      (1U)          //!< Bit field size in bits for I2S_RCSR_FWF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FWF field.
+#define BR_I2S_RCSR_FWF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Receive overflow not detected.
+ * - 1 - Receive overflow detected.
+ */
+//@{
+#define BP_I2S_RCSR_FEF      (18U)         //!< Bit position for I2S_RCSR_FEF.
+#define BM_I2S_RCSR_FEF      (0x00040000U) //!< Bit mask for I2S_RCSR_FEF.
+#define BS_I2S_RCSR_FEF      (1U)          //!< Bit field size in bits for I2S_RCSR_FEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FEF field.
+#define BR_I2S_RCSR_FEF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FEF.
+#define BF_I2S_RCSR_FEF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEF), uint32_t) & BM_I2S_RCSR_FEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEF field to a new value.
+#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Sync error not detected.
+ * - 1 - Frame sync error detected.
+ */
+//@{
+#define BP_I2S_RCSR_SEF      (19U)         //!< Bit position for I2S_RCSR_SEF.
+#define BM_I2S_RCSR_SEF      (0x00080000U) //!< Bit mask for I2S_RCSR_SEF.
+#define BS_I2S_RCSR_SEF      (1U)          //!< Bit field size in bits for I2S_RCSR_SEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_SEF field.
+#define BR_I2S_RCSR_SEF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_SEF.
+#define BF_I2S_RCSR_SEF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEF), uint32_t) & BM_I2S_RCSR_SEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEF field to a new value.
+#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Start of word not detected.
+ * - 1 - Start of word detected.
+ */
+//@{
+#define BP_I2S_RCSR_WSF      (20U)         //!< Bit position for I2S_RCSR_WSF.
+#define BM_I2S_RCSR_WSF      (0x00100000U) //!< Bit mask for I2S_RCSR_WSF.
+#define BS_I2S_RCSR_WSF      (1U)          //!< Bit field size in bits for I2S_RCSR_WSF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_WSF field.
+#define BR_I2S_RCSR_WSF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_WSF.
+#define BF_I2S_RCSR_WSF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSF), uint32_t) & BM_I2S_RCSR_WSF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSF field to a new value.
+#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Software reset.
+ */
+//@{
+#define BP_I2S_RCSR_SR       (24U)         //!< Bit position for I2S_RCSR_SR.
+#define BM_I2S_RCSR_SR       (0x01000000U) //!< Bit mask for I2S_RCSR_SR.
+#define BS_I2S_RCSR_SR       (1U)          //!< Bit field size in bits for I2S_RCSR_SR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_SR field.
+#define BR_I2S_RCSR_SR(x)    (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_SR.
+#define BF_I2S_RCSR_SR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SR), uint32_t) & BM_I2S_RCSR_SR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SR field to a new value.
+#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - FIFO reset.
+ */
+//@{
+#define BP_I2S_RCSR_FR       (25U)         //!< Bit position for I2S_RCSR_FR.
+#define BM_I2S_RCSR_FR       (0x02000000U) //!< Bit mask for I2S_RCSR_FR.
+#define BS_I2S_RCSR_FR       (1U)          //!< Bit field size in bits for I2S_RCSR_FR.
+
+//! @brief Format value for bitfield I2S_RCSR_FR.
+#define BF_I2S_RCSR_FR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FR), uint32_t) & BM_I2S_RCSR_FR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FR field to a new value.
+#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0 - Receive bit clock is disabled.
+ * - 1 - Receive bit clock is enabled.
+ */
+//@{
+#define BP_I2S_RCSR_BCE      (28U)         //!< Bit position for I2S_RCSR_BCE.
+#define BM_I2S_RCSR_BCE      (0x10000000U) //!< Bit mask for I2S_RCSR_BCE.
+#define BS_I2S_RCSR_BCE      (1U)          //!< Bit field size in bits for I2S_RCSR_BCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_BCE field.
+#define BR_I2S_RCSR_BCE(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_BCE.
+#define BF_I2S_RCSR_BCE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_BCE), uint32_t) & BM_I2S_RCSR_BCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCE field to a new value.
+#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
+ * - 1 - Receiver is enabled in Debug mode.
+ */
+//@{
+#define BP_I2S_RCSR_DBGE     (29U)         //!< Bit position for I2S_RCSR_DBGE.
+#define BM_I2S_RCSR_DBGE     (0x20000000U) //!< Bit mask for I2S_RCSR_DBGE.
+#define BS_I2S_RCSR_DBGE     (1U)          //!< Bit field size in bits for I2S_RCSR_DBGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_DBGE field.
+#define BR_I2S_RCSR_DBGE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_DBGE.
+#define BF_I2S_RCSR_DBGE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_DBGE), uint32_t) & BM_I2S_RCSR_DBGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGE field to a new value.
+#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - Receiver disabled in Stop mode.
+ * - 1 - Receiver enabled in Stop mode.
+ */
+//@{
+#define BP_I2S_RCSR_STOPE    (30U)         //!< Bit position for I2S_RCSR_STOPE.
+#define BM_I2S_RCSR_STOPE    (0x40000000U) //!< Bit mask for I2S_RCSR_STOPE.
+#define BS_I2S_RCSR_STOPE    (1U)          //!< Bit field size in bits for I2S_RCSR_STOPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_STOPE field.
+#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_STOPE.
+#define BF_I2S_RCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_STOPE), uint32_t) & BM_I2S_RCSR_STOPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPE field to a new value.
+#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0 - Receiver is disabled.
+ * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+//@{
+#define BP_I2S_RCSR_RE       (31U)         //!< Bit position for I2S_RCSR_RE.
+#define BM_I2S_RCSR_RE       (0x80000000U) //!< Bit mask for I2S_RCSR_RE.
+#define BS_I2S_RCSR_RE       (1U)          //!< Bit field size in bits for I2S_RCSR_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_RE field.
+#define BR_I2S_RCSR_RE(x)    (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_RE.
+#define BF_I2S_RCSR_RE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_RE), uint32_t) & BM_I2S_RCSR_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RE field to a new value.
+#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR1 - SAI Receive Configuration 1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_rcr1
+{
+    uint32_t U;
+    struct _hw_i2s_rcr1_bitfields
+    {
+        uint32_t RFW : 3;              //!< [2:0] Receive FIFO Watermark
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_i2s_rcr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+//@{
+#define HW_I2S_RCR1_ADDR(x)      (REGS_I2S_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR1(x)           (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
+#define HW_I2S_RCR1_RD(x)        (HW_I2S_RCR1(x).U)
+#define HW_I2S_RCR1_WR(x, v)     (HW_I2S_RCR1(x).U = (v))
+#define HW_I2S_RCR1_SET(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) |  (v)))
+#define HW_I2S_RCR1_CLR(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
+#define HW_I2S_RCR1_TOG(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+//@{
+#define BP_I2S_RCR1_RFW      (0U)          //!< Bit position for I2S_RCR1_RFW.
+#define BM_I2S_RCR1_RFW      (0x00000007U) //!< Bit mask for I2S_RCR1_RFW.
+#define BS_I2S_RCR1_RFW      (3U)          //!< Bit field size in bits for I2S_RCR1_RFW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR1_RFW field.
+#define BR_I2S_RCR1_RFW(x)   (HW_I2S_RCR1(x).B.RFW)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR1_RFW.
+#define BF_I2S_RCR1_RFW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR1_RFW), uint32_t) & BM_I2S_RCR1_RFW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFW field to a new value.
+#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR2 - SAI Receive Configuration 2 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr2
+{
+    uint32_t U;
+    struct _hw_i2s_rcr2_bitfields
+    {
+        uint32_t DIV : 8;              //!< [7:0] Bit Clock Divide
+        uint32_t RESERVED0 : 16;       //!< [23:8]
+        uint32_t BCD : 1;              //!< [24] Bit Clock Direction
+        uint32_t BCP : 1;              //!< [25] Bit Clock Polarity
+        uint32_t MSEL : 2;             //!< [27:26] MCLK Select
+        uint32_t BCI : 1;              //!< [28] Bit Clock Input
+        uint32_t BCS : 1;              //!< [29] Bit Clock Swap
+        uint32_t SYNC : 2;             //!< [31:30] Synchronous Mode
+    } B;
+} hw_i2s_rcr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+//@{
+#define HW_I2S_RCR2_ADDR(x)      (REGS_I2S_BASE(x) + 0x88U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR2(x)           (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
+#define HW_I2S_RCR2_RD(x)        (HW_I2S_RCR2(x).U)
+#define HW_I2S_RCR2_WR(x, v)     (HW_I2S_RCR2(x).U = (v))
+#define HW_I2S_RCR2_SET(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) |  (v)))
+#define HW_I2S_RCR2_CLR(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
+#define HW_I2S_RCR2_TOG(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+//@{
+#define BP_I2S_RCR2_DIV      (0U)          //!< Bit position for I2S_RCR2_DIV.
+#define BM_I2S_RCR2_DIV      (0x000000FFU) //!< Bit mask for I2S_RCR2_DIV.
+#define BS_I2S_RCR2_DIV      (8U)          //!< Bit field size in bits for I2S_RCR2_DIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_DIV field.
+#define BR_I2S_RCR2_DIV(x)   (HW_I2S_RCR2(x).B.DIV)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_DIV.
+#define BF_I2S_RCR2_DIV(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_DIV), uint32_t) & BM_I2S_RCR2_DIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIV field to a new value.
+#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is generated externally in Slave mode.
+ * - 1 - Bit clock is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_RCR2_BCD      (24U)         //!< Bit position for I2S_RCR2_BCD.
+#define BM_I2S_RCR2_BCD      (0x01000000U) //!< Bit mask for I2S_RCR2_BCD.
+#define BS_I2S_RCR2_BCD      (1U)          //!< Bit field size in bits for I2S_RCR2_BCD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCD field.
+#define BR_I2S_RCR2_BCD(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCD.
+#define BF_I2S_RCR2_BCD(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCD), uint32_t) & BM_I2S_RCR2_BCD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCD field to a new value.
+#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+//@{
+#define BP_I2S_RCR2_BCP      (25U)         //!< Bit position for I2S_RCR2_BCP.
+#define BM_I2S_RCR2_BCP      (0x02000000U) //!< Bit mask for I2S_RCR2_BCP.
+#define BS_I2S_RCR2_BCP      (1U)          //!< Bit field size in bits for I2S_RCR2_BCP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCP field.
+#define BR_I2S_RCR2_BCP(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCP.
+#define BF_I2S_RCR2_BCP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCP), uint32_t) & BM_I2S_RCR2_BCP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCP field to a new value.
+#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 00 - Bus Clock selected.
+ * - 01 - Master Clock (MCLK) 1 option selected.
+ * - 10 - Master Clock (MCLK) 2 option selected.
+ * - 11 - Master Clock (MCLK) 3 option selected.
+ */
+//@{
+#define BP_I2S_RCR2_MSEL     (26U)         //!< Bit position for I2S_RCR2_MSEL.
+#define BM_I2S_RCR2_MSEL     (0x0C000000U) //!< Bit mask for I2S_RCR2_MSEL.
+#define BS_I2S_RCR2_MSEL     (2U)          //!< Bit field size in bits for I2S_RCR2_MSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_MSEL field.
+#define BR_I2S_RCR2_MSEL(x)  (HW_I2S_RCR2(x).B.MSEL)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_MSEL.
+#define BF_I2S_RCR2_MSEL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_MSEL), uint32_t) & BM_I2S_RCR2_MSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSEL field to a new value.
+#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+//@{
+#define BP_I2S_RCR2_BCI      (28U)         //!< Bit position for I2S_RCR2_BCI.
+#define BM_I2S_RCR2_BCI      (0x10000000U) //!< Bit mask for I2S_RCR2_BCI.
+#define BS_I2S_RCR2_BCI      (1U)          //!< Bit field size in bits for I2S_RCR2_BCI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCI field.
+#define BR_I2S_RCR2_BCI(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCI.
+#define BF_I2S_RCR2_BCI(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCI), uint32_t) & BM_I2S_RCR2_BCI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCI field to a new value.
+#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0 - Use the normal bit clock source.
+ * - 1 - Swap the bit clock source.
+ */
+//@{
+#define BP_I2S_RCR2_BCS      (29U)         //!< Bit position for I2S_RCR2_BCS.
+#define BM_I2S_RCR2_BCS      (0x20000000U) //!< Bit mask for I2S_RCR2_BCS.
+#define BS_I2S_RCR2_BCS      (1U)          //!< Bit field size in bits for I2S_RCR2_BCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCS field.
+#define BR_I2S_RCR2_BCS(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCS.
+#define BF_I2S_RCR2_BCS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCS), uint32_t) & BM_I2S_RCR2_BCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCS field to a new value.
+#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 00 - Asynchronous mode.
+ * - 01 - Synchronous with transmitter.
+ * - 10 - Synchronous with another SAI receiver.
+ * - 11 - Synchronous with another SAI transmitter.
+ */
+//@{
+#define BP_I2S_RCR2_SYNC     (30U)         //!< Bit position for I2S_RCR2_SYNC.
+#define BM_I2S_RCR2_SYNC     (0xC0000000U) //!< Bit mask for I2S_RCR2_SYNC.
+#define BS_I2S_RCR2_SYNC     (2U)          //!< Bit field size in bits for I2S_RCR2_SYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_SYNC field.
+#define BR_I2S_RCR2_SYNC(x)  (HW_I2S_RCR2(x).B.SYNC)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_SYNC.
+#define BF_I2S_RCR2_SYNC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_SYNC), uint32_t) & BM_I2S_RCR2_SYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNC field to a new value.
+#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR3 - SAI Receive Configuration 3 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr3
+{
+    uint32_t U;
+    struct _hw_i2s_rcr3_bitfields
+    {
+        uint32_t WDFL : 5;             //!< [4:0] Word Flag Configuration
+        uint32_t RESERVED0 : 11;       //!< [15:5]
+        uint32_t RCE : 2;              //!< [17:16] Receive Channel Enable
+        uint32_t RESERVED1 : 14;       //!< [31:18]
+    } B;
+} hw_i2s_rcr3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+//@{
+#define HW_I2S_RCR3_ADDR(x)      (REGS_I2S_BASE(x) + 0x8CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR3(x)           (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
+#define HW_I2S_RCR3_RD(x)        (HW_I2S_RCR3(x).U)
+#define HW_I2S_RCR3_WR(x, v)     (HW_I2S_RCR3(x).U = (v))
+#define HW_I2S_RCR3_SET(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) |  (v)))
+#define HW_I2S_RCR3_CLR(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
+#define HW_I2S_RCR3_TOG(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+//@{
+#define BP_I2S_RCR3_WDFL     (0U)          //!< Bit position for I2S_RCR3_WDFL.
+#define BM_I2S_RCR3_WDFL     (0x0000001FU) //!< Bit mask for I2S_RCR3_WDFL.
+#define BS_I2S_RCR3_WDFL     (5U)          //!< Bit field size in bits for I2S_RCR3_WDFL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR3_WDFL field.
+#define BR_I2S_RCR3_WDFL(x)  (HW_I2S_RCR3(x).B.WDFL)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR3_WDFL.
+#define BF_I2S_RCR3_WDFL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_WDFL), uint32_t) & BM_I2S_RCR3_WDFL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDFL field to a new value.
+#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0 - Receive data channel N is disabled.
+ * - 1 - Receive data channel N is enabled.
+ */
+//@{
+#define BP_I2S_RCR3_RCE      (16U)         //!< Bit position for I2S_RCR3_RCE.
+#define BM_I2S_RCR3_RCE      (0x00030000U) //!< Bit mask for I2S_RCR3_RCE.
+#define BS_I2S_RCR3_RCE      (2U)          //!< Bit field size in bits for I2S_RCR3_RCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR3_RCE field.
+#define BR_I2S_RCR3_RCE(x)   (HW_I2S_RCR3(x).B.RCE)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR3_RCE.
+#define BF_I2S_RCR3_RCE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_RCE), uint32_t) & BM_I2S_RCR3_RCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RCE field to a new value.
+#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR4 - SAI Receive Configuration 4 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr4
+{
+    uint32_t U;
+    struct _hw_i2s_rcr4_bitfields
+    {
+        uint32_t FSD : 1;              //!< [0] Frame Sync Direction
+        uint32_t FSP : 1;              //!< [1] Frame Sync Polarity
+        uint32_t RESERVED0 : 1;        //!< [2]
+        uint32_t FSE : 1;              //!< [3] Frame Sync Early
+        uint32_t MF : 1;               //!< [4] MSB First
+        uint32_t RESERVED1 : 3;        //!< [7:5]
+        uint32_t SYWD : 5;             //!< [12:8] Sync Width
+        uint32_t RESERVED2 : 3;        //!< [15:13]
+        uint32_t FRSZ : 5;             //!< [20:16] Frame Size
+        uint32_t RESERVED3 : 11;       //!< [31:21]
+    } B;
+} hw_i2s_rcr4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+//@{
+#define HW_I2S_RCR4_ADDR(x)      (REGS_I2S_BASE(x) + 0x90U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR4(x)           (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
+#define HW_I2S_RCR4_RD(x)        (HW_I2S_RCR4(x).U)
+#define HW_I2S_RCR4_WR(x, v)     (HW_I2S_RCR4(x).U = (v))
+#define HW_I2S_RCR4_SET(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) |  (v)))
+#define HW_I2S_RCR4_CLR(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
+#define HW_I2S_RCR4_TOG(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame Sync is generated externally in Slave mode.
+ * - 1 - Frame Sync is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_RCR4_FSD      (0U)          //!< Bit position for I2S_RCR4_FSD.
+#define BM_I2S_RCR4_FSD      (0x00000001U) //!< Bit mask for I2S_RCR4_FSD.
+#define BS_I2S_RCR4_FSD      (1U)          //!< Bit field size in bits for I2S_RCR4_FSD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FSD field.
+#define BR_I2S_RCR4_FSD(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FSD.
+#define BF_I2S_RCR4_FSD(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSD), uint32_t) & BM_I2S_RCR4_FSD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSD field to a new value.
+#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is active high.
+ * - 1 - Frame sync is active low.
+ */
+//@{
+#define BP_I2S_RCR4_FSP      (1U)          //!< Bit position for I2S_RCR4_FSP.
+#define BM_I2S_RCR4_FSP      (0x00000002U) //!< Bit mask for I2S_RCR4_FSP.
+#define BS_I2S_RCR4_FSP      (1U)          //!< Bit field size in bits for I2S_RCR4_FSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FSP field.
+#define BR_I2S_RCR4_FSP(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FSP.
+#define BF_I2S_RCR4_FSP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSP), uint32_t) & BM_I2S_RCR4_FSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSP field to a new value.
+#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0 - Frame sync asserts with the first bit of the frame.
+ * - 1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+//@{
+#define BP_I2S_RCR4_FSE      (3U)          //!< Bit position for I2S_RCR4_FSE.
+#define BM_I2S_RCR4_FSE      (0x00000008U) //!< Bit mask for I2S_RCR4_FSE.
+#define BS_I2S_RCR4_FSE      (1U)          //!< Bit field size in bits for I2S_RCR4_FSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FSE field.
+#define BR_I2S_RCR4_FSE(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FSE.
+#define BF_I2S_RCR4_FSE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSE), uint32_t) & BM_I2S_RCR4_FSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSE field to a new value.
+#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0 - LSB is received first.
+ * - 1 - MSB is received first.
+ */
+//@{
+#define BP_I2S_RCR4_MF       (4U)          //!< Bit position for I2S_RCR4_MF.
+#define BM_I2S_RCR4_MF       (0x00000010U) //!< Bit mask for I2S_RCR4_MF.
+#define BS_I2S_RCR4_MF       (1U)          //!< Bit field size in bits for I2S_RCR4_MF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_MF field.
+#define BR_I2S_RCR4_MF(x)    (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_MF.
+#define BF_I2S_RCR4_MF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_MF), uint32_t) & BM_I2S_RCR4_MF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MF field to a new value.
+#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+//@{
+#define BP_I2S_RCR4_SYWD     (8U)          //!< Bit position for I2S_RCR4_SYWD.
+#define BM_I2S_RCR4_SYWD     (0x00001F00U) //!< Bit mask for I2S_RCR4_SYWD.
+#define BS_I2S_RCR4_SYWD     (5U)          //!< Bit field size in bits for I2S_RCR4_SYWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_SYWD field.
+#define BR_I2S_RCR4_SYWD(x)  (HW_I2S_RCR4(x).B.SYWD)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_SYWD.
+#define BF_I2S_RCR4_SYWD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_SYWD), uint32_t) & BM_I2S_RCR4_SYWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYWD field to a new value.
+#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+//@{
+#define BP_I2S_RCR4_FRSZ     (16U)         //!< Bit position for I2S_RCR4_FRSZ.
+#define BM_I2S_RCR4_FRSZ     (0x001F0000U) //!< Bit mask for I2S_RCR4_FRSZ.
+#define BS_I2S_RCR4_FRSZ     (5U)          //!< Bit field size in bits for I2S_RCR4_FRSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FRSZ field.
+#define BR_I2S_RCR4_FRSZ(x)  (HW_I2S_RCR4(x).B.FRSZ)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FRSZ.
+#define BF_I2S_RCR4_FRSZ(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FRSZ), uint32_t) & BM_I2S_RCR4_FRSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRSZ field to a new value.
+#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR5 - SAI Receive Configuration 5 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr5
+{
+    uint32_t U;
+    struct _hw_i2s_rcr5_bitfields
+    {
+        uint32_t RESERVED0 : 8;        //!< [7:0]
+        uint32_t FBT : 5;              //!< [12:8] First Bit Shifted
+        uint32_t RESERVED1 : 3;        //!< [15:13]
+        uint32_t W0W : 5;              //!< [20:16] Word 0 Width
+        uint32_t RESERVED2 : 3;        //!< [23:21]
+        uint32_t WNW : 5;              //!< [28:24] Word N Width
+        uint32_t RESERVED3 : 3;        //!< [31:29]
+    } B;
+} hw_i2s_rcr5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+//@{
+#define HW_I2S_RCR5_ADDR(x)      (REGS_I2S_BASE(x) + 0x94U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR5(x)           (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
+#define HW_I2S_RCR5_RD(x)        (HW_I2S_RCR5(x).U)
+#define HW_I2S_RCR5_WR(x, v)     (HW_I2S_RCR5(x).U = (v))
+#define HW_I2S_RCR5_SET(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) |  (v)))
+#define HW_I2S_RCR5_CLR(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
+#define HW_I2S_RCR5_TOG(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+//@{
+#define BP_I2S_RCR5_FBT      (8U)          //!< Bit position for I2S_RCR5_FBT.
+#define BM_I2S_RCR5_FBT      (0x00001F00U) //!< Bit mask for I2S_RCR5_FBT.
+#define BS_I2S_RCR5_FBT      (5U)          //!< Bit field size in bits for I2S_RCR5_FBT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR5_FBT field.
+#define BR_I2S_RCR5_FBT(x)   (HW_I2S_RCR5(x).B.FBT)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR5_FBT.
+#define BF_I2S_RCR5_FBT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_FBT), uint32_t) & BM_I2S_RCR5_FBT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FBT field to a new value.
+#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+//@{
+#define BP_I2S_RCR5_W0W      (16U)         //!< Bit position for I2S_RCR5_W0W.
+#define BM_I2S_RCR5_W0W      (0x001F0000U) //!< Bit mask for I2S_RCR5_W0W.
+#define BS_I2S_RCR5_W0W      (5U)          //!< Bit field size in bits for I2S_RCR5_W0W.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR5_W0W field.
+#define BR_I2S_RCR5_W0W(x)   (HW_I2S_RCR5(x).B.W0W)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR5_W0W.
+#define BF_I2S_RCR5_W0W(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_W0W), uint32_t) & BM_I2S_RCR5_W0W)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the W0W field to a new value.
+#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+//@{
+#define BP_I2S_RCR5_WNW      (24U)         //!< Bit position for I2S_RCR5_WNW.
+#define BM_I2S_RCR5_WNW      (0x1F000000U) //!< Bit mask for I2S_RCR5_WNW.
+#define BS_I2S_RCR5_WNW      (5U)          //!< Bit field size in bits for I2S_RCR5_WNW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR5_WNW field.
+#define BR_I2S_RCR5_WNW(x)   (HW_I2S_RCR5(x).B.WNW)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR5_WNW.
+#define BF_I2S_RCR5_WNW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_WNW), uint32_t) & BM_I2S_RCR5_WNW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WNW field to a new value.
+#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RDRn - SAI Receive Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+typedef union _hw_i2s_rdrn
+{
+    uint32_t U;
+    struct _hw_i2s_rdrn_bitfields
+    {
+        uint32_t RDR : 32;             //!< [31:0] Receive Data Register
+    } B;
+} hw_i2s_rdrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RDRn register
+ */
+//@{
+#define HW_I2S_RDRn_COUNT (2U)
+
+#define HW_I2S_RDRn_ADDR(x, n)   (REGS_I2S_BASE(x) + 0xA0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RDRn(x, n)        (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
+#define HW_I2S_RDRn_RD(x, n)     (HW_I2S_RDRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RDRn bitfields
+ */
+
+/*!
+ * @name Register I2S_RDRn, field RDR[31:0] (RO)
+ *
+ * The corresponding RCR3[RCE] bit must be set before accessing the channel's
+ * receive data register. Reads from this register when the receive FIFO is not
+ * empty will return the data from the top of the receive FIFO. Reads from this
+ * register when the receive FIFO is empty are ignored.
+ */
+//@{
+#define BP_I2S_RDRn_RDR      (0U)          //!< Bit position for I2S_RDRn_RDR.
+#define BM_I2S_RDRn_RDR      (0xFFFFFFFFU) //!< Bit mask for I2S_RDRn_RDR.
+#define BS_I2S_RDRn_RDR      (32U)         //!< Bit field size in bits for I2S_RDRn_RDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RDRn_RDR field.
+#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RFRn - SAI Receive FIFO Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+typedef union _hw_i2s_rfrn
+{
+    uint32_t U;
+    struct _hw_i2s_rfrn_bitfields
+    {
+        uint32_t RFP : 4;              //!< [3:0] Read FIFO Pointer
+        uint32_t RESERVED0 : 12;       //!< [15:4]
+        uint32_t WFP : 4;              //!< [19:16] Write FIFO Pointer
+        uint32_t RESERVED1 : 12;       //!< [31:20]
+    } B;
+} hw_i2s_rfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RFRn register
+ */
+//@{
+#define HW_I2S_RFRn_COUNT (2U)
+
+#define HW_I2S_RFRn_ADDR(x, n)   (REGS_I2S_BASE(x) + 0xC0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RFRn(x, n)        (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
+#define HW_I2S_RFRn_RD(x, n)     (HW_I2S_RFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RFRn bitfields
+ */
+
+/*!
+ * @name Register I2S_RFRn, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+//@{
+#define BP_I2S_RFRn_RFP      (0U)          //!< Bit position for I2S_RFRn_RFP.
+#define BM_I2S_RFRn_RFP      (0x0000000FU) //!< Bit mask for I2S_RFRn_RFP.
+#define BS_I2S_RFRn_RFP      (4U)          //!< Bit field size in bits for I2S_RFRn_RFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RFRn_RFP field.
+#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RFRn, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+//@{
+#define BP_I2S_RFRn_WFP      (16U)         //!< Bit position for I2S_RFRn_WFP.
+#define BM_I2S_RFRn_WFP      (0x000F0000U) //!< Bit mask for I2S_RFRn_WFP.
+#define BS_I2S_RFRn_WFP      (4U)          //!< Bit field size in bits for I2S_RFRn_WFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RFRn_WFP field.
+#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RMR - SAI Receive Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+typedef union _hw_i2s_rmr
+{
+    uint32_t U;
+    struct _hw_i2s_rmr_bitfields
+    {
+        uint32_t RWM : 32;             //!< [31:0] Receive Word Mask
+    } B;
+} hw_i2s_rmr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+//@{
+#define HW_I2S_RMR_ADDR(x)       (REGS_I2S_BASE(x) + 0xE0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RMR(x)            (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
+#define HW_I2S_RMR_RD(x)         (HW_I2S_RMR(x).U)
+#define HW_I2S_RMR_WR(x, v)      (HW_I2S_RMR(x).U = (v))
+#define HW_I2S_RMR_SET(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) |  (v)))
+#define HW_I2S_RMR_CLR(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
+#define HW_I2S_RMR_TOG(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RMR bitfields
+ */
+
+/*!
+ * @name Register I2S_RMR, field RWM[31:0] (RW)
+ *
+ * Configures whether the receive word is masked (received data ignored and not
+ * written to receive FIFO) for the corresponding word in the frame.
+ *
+ * Values:
+ * - 0 - Word N is enabled.
+ * - 1 - Word N is masked.
+ */
+//@{
+#define BP_I2S_RMR_RWM       (0U)          //!< Bit position for I2S_RMR_RWM.
+#define BM_I2S_RMR_RWM       (0xFFFFFFFFU) //!< Bit mask for I2S_RMR_RWM.
+#define BS_I2S_RMR_RWM       (32U)         //!< Bit field size in bits for I2S_RMR_RWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RMR_RWM field.
+#define BR_I2S_RMR_RWM(x)    (HW_I2S_RMR(x).U)
+#endif
+
+//! @brief Format value for bitfield I2S_RMR_RWM.
+#define BF_I2S_RMR_RWM(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RMR_RWM), uint32_t) & BM_I2S_RMR_RWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWM field to a new value.
+#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_MCR - SAI MCLK Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+typedef union _hw_i2s_mcr
+{
+    uint32_t U;
+    struct _hw_i2s_mcr_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t MICS : 2;             //!< [25:24] MCLK Input Clock Select
+        uint32_t RESERVED1 : 4;        //!< [29:26]
+        uint32_t MOE : 1;              //!< [30] MCLK Output Enable
+        uint32_t DUF : 1;              //!< [31] Divider Update Flag
+    } B;
+} hw_i2s_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+//@{
+#define HW_I2S_MCR_ADDR(x)       (REGS_I2S_BASE(x) + 0x100U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_MCR(x)            (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
+#define HW_I2S_MCR_RD(x)         (HW_I2S_MCR(x).U)
+#define HW_I2S_MCR_WR(x, v)      (HW_I2S_MCR(x).U = (v))
+#define HW_I2S_MCR_SET(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) |  (v)))
+#define HW_I2S_MCR_CLR(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
+#define HW_I2S_MCR_TOG(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 00 - MCLK divider input clock 0 selected.
+ * - 01 - MCLK divider input clock 1 selected.
+ * - 10 - MCLK divider input clock 2 selected.
+ * - 11 - MCLK divider input clock 3 selected.
+ */
+//@{
+#define BP_I2S_MCR_MICS      (24U)         //!< Bit position for I2S_MCR_MICS.
+#define BM_I2S_MCR_MICS      (0x03000000U) //!< Bit mask for I2S_MCR_MICS.
+#define BS_I2S_MCR_MICS      (2U)          //!< Bit field size in bits for I2S_MCR_MICS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MCR_MICS field.
+#define BR_I2S_MCR_MICS(x)   (HW_I2S_MCR(x).B.MICS)
+#endif
+
+//! @brief Format value for bitfield I2S_MCR_MICS.
+#define BF_I2S_MCR_MICS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MICS), uint32_t) & BM_I2S_MCR_MICS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MICS field to a new value.
+#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+//@{
+#define BP_I2S_MCR_MOE       (30U)         //!< Bit position for I2S_MCR_MOE.
+#define BM_I2S_MCR_MOE       (0x40000000U) //!< Bit mask for I2S_MCR_MOE.
+#define BS_I2S_MCR_MOE       (1U)          //!< Bit field size in bits for I2S_MCR_MOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MCR_MOE field.
+#define BR_I2S_MCR_MOE(x)    (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
+#endif
+
+//! @brief Format value for bitfield I2S_MCR_MOE.
+#define BF_I2S_MCR_MOE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MOE), uint32_t) & BM_I2S_MCR_MOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MOE field to a new value.
+#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0 - MCLK divider ratio is not being updated currently.
+ * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
+ *     divider ratio are blocked while this flag remains set.
+ */
+//@{
+#define BP_I2S_MCR_DUF       (31U)         //!< Bit position for I2S_MCR_DUF.
+#define BM_I2S_MCR_DUF       (0x80000000U) //!< Bit mask for I2S_MCR_DUF.
+#define BS_I2S_MCR_DUF       (1U)          //!< Bit field size in bits for I2S_MCR_DUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MCR_DUF field.
+#define BR_I2S_MCR_DUF(x)    (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_MDR - SAI MCLK Divide Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+typedef union _hw_i2s_mdr
+{
+    uint32_t U;
+    struct _hw_i2s_mdr_bitfields
+    {
+        uint32_t DIVIDE : 12;          //!< [11:0] MCLK Divide
+        uint32_t FRACT : 8;            //!< [19:12] MCLK Fraction
+        uint32_t RESERVED0 : 12;       //!< [31:20]
+    } B;
+} hw_i2s_mdr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+//@{
+#define HW_I2S_MDR_ADDR(x)       (REGS_I2S_BASE(x) + 0x104U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_MDR(x)            (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
+#define HW_I2S_MDR_RD(x)         (HW_I2S_MDR(x).U)
+#define HW_I2S_MDR_WR(x, v)      (HW_I2S_MDR(x).U = (v))
+#define HW_I2S_MDR_SET(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) |  (v)))
+#define HW_I2S_MDR_CLR(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
+#define HW_I2S_MDR_TOG(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+//@{
+#define BP_I2S_MDR_DIVIDE    (0U)          //!< Bit position for I2S_MDR_DIVIDE.
+#define BM_I2S_MDR_DIVIDE    (0x00000FFFU) //!< Bit mask for I2S_MDR_DIVIDE.
+#define BS_I2S_MDR_DIVIDE    (12U)         //!< Bit field size in bits for I2S_MDR_DIVIDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MDR_DIVIDE field.
+#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
+#endif
+
+//! @brief Format value for bitfield I2S_MDR_DIVIDE.
+#define BF_I2S_MDR_DIVIDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_DIVIDE), uint32_t) & BM_I2S_MDR_DIVIDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIVIDE field to a new value.
+#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+//@{
+#define BP_I2S_MDR_FRACT     (12U)         //!< Bit position for I2S_MDR_FRACT.
+#define BM_I2S_MDR_FRACT     (0x000FF000U) //!< Bit mask for I2S_MDR_FRACT.
+#define BS_I2S_MDR_FRACT     (8U)          //!< Bit field size in bits for I2S_MDR_FRACT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MDR_FRACT field.
+#define BR_I2S_MDR_FRACT(x)  (HW_I2S_MDR(x).B.FRACT)
+#endif
+
+//! @brief Format value for bitfield I2S_MDR_FRACT.
+#define BF_I2S_MDR_FRACT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_FRACT), uint32_t) & BM_I2S_MDR_FRACT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRACT field to a new value.
+#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_i2s_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All I2S module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_i2s
+{
+    __IO hw_i2s_tcsr_t TCSR;               //!< [0x0] SAI Transmit Control Register
+    __IO hw_i2s_tcr1_t TCR1;               //!< [0x4] SAI Transmit Configuration 1 Register
+    __IO hw_i2s_tcr2_t TCR2;               //!< [0x8] SAI Transmit Configuration 2 Register
+    __IO hw_i2s_tcr3_t TCR3;               //!< [0xC] SAI Transmit Configuration 3 Register
+    __IO hw_i2s_tcr4_t TCR4;               //!< [0x10] SAI Transmit Configuration 4 Register
+    __IO hw_i2s_tcr5_t TCR5;               //!< [0x14] SAI Transmit Configuration 5 Register
+    uint8_t _reserved0[8];
+    __O hw_i2s_tdrn_t TDRn[2];             //!< [0x20] SAI Transmit Data Register
+    uint8_t _reserved1[24];
+    __I hw_i2s_tfrn_t TFRn[2];             //!< [0x40] SAI Transmit FIFO Register
+    uint8_t _reserved2[24];
+    __IO hw_i2s_tmr_t TMR;                 //!< [0x60] SAI Transmit Mask Register
+    uint8_t _reserved3[28];
+    __IO hw_i2s_rcsr_t RCSR;               //!< [0x80] SAI Receive Control Register
+    __IO hw_i2s_rcr1_t RCR1;               //!< [0x84] SAI Receive Configuration 1 Register
+    __IO hw_i2s_rcr2_t RCR2;               //!< [0x88] SAI Receive Configuration 2 Register
+    __IO hw_i2s_rcr3_t RCR3;               //!< [0x8C] SAI Receive Configuration 3 Register
+    __IO hw_i2s_rcr4_t RCR4;               //!< [0x90] SAI Receive Configuration 4 Register
+    __IO hw_i2s_rcr5_t RCR5;               //!< [0x94] SAI Receive Configuration 5 Register
+    uint8_t _reserved4[8];
+    __I hw_i2s_rdrn_t RDRn[2];             //!< [0xA0] SAI Receive Data Register
+    uint8_t _reserved5[24];
+    __I hw_i2s_rfrn_t RFRn[2];             //!< [0xC0] SAI Receive FIFO Register
+    uint8_t _reserved6[24];
+    __IO hw_i2s_rmr_t RMR;                 //!< [0xE0] SAI Receive Mask Register
+    uint8_t _reserved7[28];
+    __IO hw_i2s_mcr_t MCR;                 //!< [0x100] SAI MCLK Control Register
+    __IO hw_i2s_mdr_t MDR;                 //!< [0x104] SAI MCLK Divide Register
+} hw_i2s_t;
+#pragma pack()
+
+//! @brief Macro to access all I2S registers.
+//! @param x I2S instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_I2S(0)</code>.
+#define HW_I2S(x)      (*(hw_i2s_t *) REGS_I2S_BASE(x))
+#endif
+
+#endif // __HW_I2S_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h
new file mode 100644
index 0000000000..6f5c4cd72d
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h
@@ -0,0 +1,2252 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_LLWU_REGISTERS_H__
+#define __HW_LLWU_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
+ * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
+ * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
+ * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
+ * - HW_LLWU_ME - LLWU Module Enable register
+ * - HW_LLWU_F1 - LLWU Flag 1 register
+ * - HW_LLWU_F2 - LLWU Flag 2 register
+ * - HW_LLWU_F3 - LLWU Flag 3 register
+ * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - HW_LLWU_RST - LLWU Reset Enable register
+ *
+ * - hw_llwu_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_LLWU_BASE
+#define HW_LLWU_INSTANCE_COUNT (1U) //!< Number of instances of the LLWU module.
+#define REGS_LLWU_BASE (0x4007C000U) //!< Base address for LLWU.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE1 - LLWU Pin Enable 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe1
+{
+    uint8_t U;
+    struct _hw_llwu_pe1_bitfields
+    {
+        uint8_t WUPE0 : 2;             //!< [1:0] Wakeup Pin Enable For LLWU_P0
+        uint8_t WUPE1 : 2;             //!< [3:2] Wakeup Pin Enable For LLWU_P1
+        uint8_t WUPE2 : 2;             //!< [5:4] Wakeup Pin Enable For LLWU_P2
+        uint8_t WUPE3 : 2;             //!< [7:6] Wakeup Pin Enable For LLWU_P3
+    } B;
+} hw_llwu_pe1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+//@{
+#define HW_LLWU_PE1_ADDR         (REGS_LLWU_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE1              (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR)
+#define HW_LLWU_PE1_RD()         (HW_LLWU_PE1.U)
+#define HW_LLWU_PE1_WR(v)        (HW_LLWU_PE1.U = (v))
+#define HW_LLWU_PE1_SET(v)       (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() |  (v)))
+#define HW_LLWU_PE1_CLR(v)       (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() & ~(v)))
+#define HW_LLWU_PE1_TOG(v)       (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE0    (0U)          //!< Bit position for LLWU_PE1_WUPE0.
+#define BM_LLWU_PE1_WUPE0    (0x03U)       //!< Bit mask for LLWU_PE1_WUPE0.
+#define BS_LLWU_PE1_WUPE0    (2U)          //!< Bit field size in bits for LLWU_PE1_WUPE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE0 field.
+#define BR_LLWU_PE1_WUPE0    (HW_LLWU_PE1.B.WUPE0)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE0.
+#define BF_LLWU_PE1_WUPE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE0), uint8_t) & BM_LLWU_PE1_WUPE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE0 field to a new value.
+#define BW_LLWU_PE1_WUPE0(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE1    (2U)          //!< Bit position for LLWU_PE1_WUPE1.
+#define BM_LLWU_PE1_WUPE1    (0x0CU)       //!< Bit mask for LLWU_PE1_WUPE1.
+#define BS_LLWU_PE1_WUPE1    (2U)          //!< Bit field size in bits for LLWU_PE1_WUPE1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE1 field.
+#define BR_LLWU_PE1_WUPE1    (HW_LLWU_PE1.B.WUPE1)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE1.
+#define BF_LLWU_PE1_WUPE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE1), uint8_t) & BM_LLWU_PE1_WUPE1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE1 field to a new value.
+#define BW_LLWU_PE1_WUPE1(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE2    (4U)          //!< Bit position for LLWU_PE1_WUPE2.
+#define BM_LLWU_PE1_WUPE2    (0x30U)       //!< Bit mask for LLWU_PE1_WUPE2.
+#define BS_LLWU_PE1_WUPE2    (2U)          //!< Bit field size in bits for LLWU_PE1_WUPE2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE2 field.
+#define BR_LLWU_PE1_WUPE2    (HW_LLWU_PE1.B.WUPE2)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE2.
+#define BF_LLWU_PE1_WUPE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE2), uint8_t) & BM_LLWU_PE1_WUPE2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE2 field to a new value.
+#define BW_LLWU_PE1_WUPE2(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE3    (6U)          //!< Bit position for LLWU_PE1_WUPE3.
+#define BM_LLWU_PE1_WUPE3    (0xC0U)       //!< Bit mask for LLWU_PE1_WUPE3.
+#define BS_LLWU_PE1_WUPE3    (2U)          //!< Bit field size in bits for LLWU_PE1_WUPE3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE3 field.
+#define BR_LLWU_PE1_WUPE3    (HW_LLWU_PE1.B.WUPE3)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE3.
+#define BF_LLWU_PE1_WUPE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE3), uint8_t) & BM_LLWU_PE1_WUPE3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE3 field to a new value.
+#define BW_LLWU_PE1_WUPE3(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE2 - LLWU Pin Enable 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe2
+{
+    uint8_t U;
+    struct _hw_llwu_pe2_bitfields
+    {
+        uint8_t WUPE4 : 2;             //!< [1:0] Wakeup Pin Enable For LLWU_P4
+        uint8_t WUPE5 : 2;             //!< [3:2] Wakeup Pin Enable For LLWU_P5
+        uint8_t WUPE6 : 2;             //!< [5:4] Wakeup Pin Enable For LLWU_P6
+        uint8_t WUPE7 : 2;             //!< [7:6] Wakeup Pin Enable For LLWU_P7
+    } B;
+} hw_llwu_pe2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+//@{
+#define HW_LLWU_PE2_ADDR         (REGS_LLWU_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE2              (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR)
+#define HW_LLWU_PE2_RD()         (HW_LLWU_PE2.U)
+#define HW_LLWU_PE2_WR(v)        (HW_LLWU_PE2.U = (v))
+#define HW_LLWU_PE2_SET(v)       (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() |  (v)))
+#define HW_LLWU_PE2_CLR(v)       (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() & ~(v)))
+#define HW_LLWU_PE2_TOG(v)       (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE4    (0U)          //!< Bit position for LLWU_PE2_WUPE4.
+#define BM_LLWU_PE2_WUPE4    (0x03U)       //!< Bit mask for LLWU_PE2_WUPE4.
+#define BS_LLWU_PE2_WUPE4    (2U)          //!< Bit field size in bits for LLWU_PE2_WUPE4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE4 field.
+#define BR_LLWU_PE2_WUPE4    (HW_LLWU_PE2.B.WUPE4)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE4.
+#define BF_LLWU_PE2_WUPE4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE4), uint8_t) & BM_LLWU_PE2_WUPE4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE4 field to a new value.
+#define BW_LLWU_PE2_WUPE4(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE5    (2U)          //!< Bit position for LLWU_PE2_WUPE5.
+#define BM_LLWU_PE2_WUPE5    (0x0CU)       //!< Bit mask for LLWU_PE2_WUPE5.
+#define BS_LLWU_PE2_WUPE5    (2U)          //!< Bit field size in bits for LLWU_PE2_WUPE5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE5 field.
+#define BR_LLWU_PE2_WUPE5    (HW_LLWU_PE2.B.WUPE5)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE5.
+#define BF_LLWU_PE2_WUPE5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE5), uint8_t) & BM_LLWU_PE2_WUPE5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE5 field to a new value.
+#define BW_LLWU_PE2_WUPE5(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE6    (4U)          //!< Bit position for LLWU_PE2_WUPE6.
+#define BM_LLWU_PE2_WUPE6    (0x30U)       //!< Bit mask for LLWU_PE2_WUPE6.
+#define BS_LLWU_PE2_WUPE6    (2U)          //!< Bit field size in bits for LLWU_PE2_WUPE6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE6 field.
+#define BR_LLWU_PE2_WUPE6    (HW_LLWU_PE2.B.WUPE6)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE6.
+#define BF_LLWU_PE2_WUPE6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE6), uint8_t) & BM_LLWU_PE2_WUPE6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE6 field to a new value.
+#define BW_LLWU_PE2_WUPE6(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE7    (6U)          //!< Bit position for LLWU_PE2_WUPE7.
+#define BM_LLWU_PE2_WUPE7    (0xC0U)       //!< Bit mask for LLWU_PE2_WUPE7.
+#define BS_LLWU_PE2_WUPE7    (2U)          //!< Bit field size in bits for LLWU_PE2_WUPE7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE7 field.
+#define BR_LLWU_PE2_WUPE7    (HW_LLWU_PE2.B.WUPE7)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE7.
+#define BF_LLWU_PE2_WUPE7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE7), uint8_t) & BM_LLWU_PE2_WUPE7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE7 field to a new value.
+#define BW_LLWU_PE2_WUPE7(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE3 - LLWU Pin Enable 3 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe3
+{
+    uint8_t U;
+    struct _hw_llwu_pe3_bitfields
+    {
+        uint8_t WUPE8 : 2;             //!< [1:0] Wakeup Pin Enable For LLWU_P8
+        uint8_t WUPE9 : 2;             //!< [3:2] Wakeup Pin Enable For LLWU_P9
+        uint8_t WUPE10 : 2;            //!< [5:4] Wakeup Pin Enable For LLWU_P10
+        uint8_t WUPE11 : 2;            //!< [7:6] Wakeup Pin Enable For LLWU_P11
+    } B;
+} hw_llwu_pe3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+//@{
+#define HW_LLWU_PE3_ADDR         (REGS_LLWU_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE3              (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR)
+#define HW_LLWU_PE3_RD()         (HW_LLWU_PE3.U)
+#define HW_LLWU_PE3_WR(v)        (HW_LLWU_PE3.U = (v))
+#define HW_LLWU_PE3_SET(v)       (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() |  (v)))
+#define HW_LLWU_PE3_CLR(v)       (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() & ~(v)))
+#define HW_LLWU_PE3_TOG(v)       (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE8    (0U)          //!< Bit position for LLWU_PE3_WUPE8.
+#define BM_LLWU_PE3_WUPE8    (0x03U)       //!< Bit mask for LLWU_PE3_WUPE8.
+#define BS_LLWU_PE3_WUPE8    (2U)          //!< Bit field size in bits for LLWU_PE3_WUPE8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE8 field.
+#define BR_LLWU_PE3_WUPE8    (HW_LLWU_PE3.B.WUPE8)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE8.
+#define BF_LLWU_PE3_WUPE8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE8), uint8_t) & BM_LLWU_PE3_WUPE8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE8 field to a new value.
+#define BW_LLWU_PE3_WUPE8(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE9    (2U)          //!< Bit position for LLWU_PE3_WUPE9.
+#define BM_LLWU_PE3_WUPE9    (0x0CU)       //!< Bit mask for LLWU_PE3_WUPE9.
+#define BS_LLWU_PE3_WUPE9    (2U)          //!< Bit field size in bits for LLWU_PE3_WUPE9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE9 field.
+#define BR_LLWU_PE3_WUPE9    (HW_LLWU_PE3.B.WUPE9)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE9.
+#define BF_LLWU_PE3_WUPE9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE9), uint8_t) & BM_LLWU_PE3_WUPE9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE9 field to a new value.
+#define BW_LLWU_PE3_WUPE9(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE10   (4U)          //!< Bit position for LLWU_PE3_WUPE10.
+#define BM_LLWU_PE3_WUPE10   (0x30U)       //!< Bit mask for LLWU_PE3_WUPE10.
+#define BS_LLWU_PE3_WUPE10   (2U)          //!< Bit field size in bits for LLWU_PE3_WUPE10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE10 field.
+#define BR_LLWU_PE3_WUPE10   (HW_LLWU_PE3.B.WUPE10)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE10.
+#define BF_LLWU_PE3_WUPE10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE10), uint8_t) & BM_LLWU_PE3_WUPE10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE10 field to a new value.
+#define BW_LLWU_PE3_WUPE10(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE11   (6U)          //!< Bit position for LLWU_PE3_WUPE11.
+#define BM_LLWU_PE3_WUPE11   (0xC0U)       //!< Bit mask for LLWU_PE3_WUPE11.
+#define BS_LLWU_PE3_WUPE11   (2U)          //!< Bit field size in bits for LLWU_PE3_WUPE11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE11 field.
+#define BR_LLWU_PE3_WUPE11   (HW_LLWU_PE3.B.WUPE11)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE11.
+#define BF_LLWU_PE3_WUPE11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE11), uint8_t) & BM_LLWU_PE3_WUPE11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE11 field to a new value.
+#define BW_LLWU_PE3_WUPE11(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE4 - LLWU Pin Enable 4 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe4
+{
+    uint8_t U;
+    struct _hw_llwu_pe4_bitfields
+    {
+        uint8_t WUPE12 : 2;            //!< [1:0] Wakeup Pin Enable For LLWU_P12
+        uint8_t WUPE13 : 2;            //!< [3:2] Wakeup Pin Enable For LLWU_P13
+        uint8_t WUPE14 : 2;            //!< [5:4] Wakeup Pin Enable For LLWU_P14
+        uint8_t WUPE15 : 2;            //!< [7:6] Wakeup Pin Enable For LLWU_P15
+    } B;
+} hw_llwu_pe4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+//@{
+#define HW_LLWU_PE4_ADDR         (REGS_LLWU_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE4              (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR)
+#define HW_LLWU_PE4_RD()         (HW_LLWU_PE4.U)
+#define HW_LLWU_PE4_WR(v)        (HW_LLWU_PE4.U = (v))
+#define HW_LLWU_PE4_SET(v)       (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() |  (v)))
+#define HW_LLWU_PE4_CLR(v)       (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() & ~(v)))
+#define HW_LLWU_PE4_TOG(v)       (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE12   (0U)          //!< Bit position for LLWU_PE4_WUPE12.
+#define BM_LLWU_PE4_WUPE12   (0x03U)       //!< Bit mask for LLWU_PE4_WUPE12.
+#define BS_LLWU_PE4_WUPE12   (2U)          //!< Bit field size in bits for LLWU_PE4_WUPE12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE12 field.
+#define BR_LLWU_PE4_WUPE12   (HW_LLWU_PE4.B.WUPE12)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE12.
+#define BF_LLWU_PE4_WUPE12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE12), uint8_t) & BM_LLWU_PE4_WUPE12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE12 field to a new value.
+#define BW_LLWU_PE4_WUPE12(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE13   (2U)          //!< Bit position for LLWU_PE4_WUPE13.
+#define BM_LLWU_PE4_WUPE13   (0x0CU)       //!< Bit mask for LLWU_PE4_WUPE13.
+#define BS_LLWU_PE4_WUPE13   (2U)          //!< Bit field size in bits for LLWU_PE4_WUPE13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE13 field.
+#define BR_LLWU_PE4_WUPE13   (HW_LLWU_PE4.B.WUPE13)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE13.
+#define BF_LLWU_PE4_WUPE13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE13), uint8_t) & BM_LLWU_PE4_WUPE13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE13 field to a new value.
+#define BW_LLWU_PE4_WUPE13(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE14   (4U)          //!< Bit position for LLWU_PE4_WUPE14.
+#define BM_LLWU_PE4_WUPE14   (0x30U)       //!< Bit mask for LLWU_PE4_WUPE14.
+#define BS_LLWU_PE4_WUPE14   (2U)          //!< Bit field size in bits for LLWU_PE4_WUPE14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE14 field.
+#define BR_LLWU_PE4_WUPE14   (HW_LLWU_PE4.B.WUPE14)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE14.
+#define BF_LLWU_PE4_WUPE14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE14), uint8_t) & BM_LLWU_PE4_WUPE14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE14 field to a new value.
+#define BW_LLWU_PE4_WUPE14(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE15   (6U)          //!< Bit position for LLWU_PE4_WUPE15.
+#define BM_LLWU_PE4_WUPE15   (0xC0U)       //!< Bit mask for LLWU_PE4_WUPE15.
+#define BS_LLWU_PE4_WUPE15   (2U)          //!< Bit field size in bits for LLWU_PE4_WUPE15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE15 field.
+#define BR_LLWU_PE4_WUPE15   (HW_LLWU_PE4.B.WUPE15)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE15.
+#define BF_LLWU_PE4_WUPE15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE15), uint8_t) & BM_LLWU_PE4_WUPE15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE15 field to a new value.
+#define BW_LLWU_PE4_WUPE15(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_ME - LLWU Module Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_me
+{
+    uint8_t U;
+    struct _hw_llwu_me_bitfields
+    {
+        uint8_t WUME0 : 1;             //!< [0] Wakeup Module Enable For Module 0
+        uint8_t WUME1 : 1;             //!< [1] Wakeup Module Enable for Module 1
+        uint8_t WUME2 : 1;             //!< [2] Wakeup Module Enable For Module 2
+        uint8_t WUME3 : 1;             //!< [3] Wakeup Module Enable For Module 3
+        uint8_t WUME4 : 1;             //!< [4] Wakeup Module Enable For Module 4
+        uint8_t WUME5 : 1;             //!< [5] Wakeup Module Enable For Module 5
+        uint8_t WUME6 : 1;             //!< [6] Wakeup Module Enable For Module 6
+        uint8_t WUME7 : 1;             //!< [7] Wakeup Module Enable For Module 7
+    } B;
+} hw_llwu_me_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+//@{
+#define HW_LLWU_ME_ADDR          (REGS_LLWU_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_ME               (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR)
+#define HW_LLWU_ME_RD()          (HW_LLWU_ME.U)
+#define HW_LLWU_ME_WR(v)         (HW_LLWU_ME.U = (v))
+#define HW_LLWU_ME_SET(v)        (HW_LLWU_ME_WR(HW_LLWU_ME_RD() |  (v)))
+#define HW_LLWU_ME_CLR(v)        (HW_LLWU_ME_WR(HW_LLWU_ME_RD() & ~(v)))
+#define HW_LLWU_ME_TOG(v)        (HW_LLWU_ME_WR(HW_LLWU_ME_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME0     (0U)          //!< Bit position for LLWU_ME_WUME0.
+#define BM_LLWU_ME_WUME0     (0x01U)       //!< Bit mask for LLWU_ME_WUME0.
+#define BS_LLWU_ME_WUME0     (1U)          //!< Bit field size in bits for LLWU_ME_WUME0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME0 field.
+#define BR_LLWU_ME_WUME0     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME0.
+#define BF_LLWU_ME_WUME0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME0), uint8_t) & BM_LLWU_ME_WUME0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME0 field to a new value.
+#define BW_LLWU_ME_WUME0(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME1     (1U)          //!< Bit position for LLWU_ME_WUME1.
+#define BM_LLWU_ME_WUME1     (0x02U)       //!< Bit mask for LLWU_ME_WUME1.
+#define BS_LLWU_ME_WUME1     (1U)          //!< Bit field size in bits for LLWU_ME_WUME1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME1 field.
+#define BR_LLWU_ME_WUME1     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME1.
+#define BF_LLWU_ME_WUME1(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME1), uint8_t) & BM_LLWU_ME_WUME1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME1 field to a new value.
+#define BW_LLWU_ME_WUME1(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME2     (2U)          //!< Bit position for LLWU_ME_WUME2.
+#define BM_LLWU_ME_WUME2     (0x04U)       //!< Bit mask for LLWU_ME_WUME2.
+#define BS_LLWU_ME_WUME2     (1U)          //!< Bit field size in bits for LLWU_ME_WUME2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME2 field.
+#define BR_LLWU_ME_WUME2     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME2.
+#define BF_LLWU_ME_WUME2(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME2), uint8_t) & BM_LLWU_ME_WUME2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME2 field to a new value.
+#define BW_LLWU_ME_WUME2(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME3     (3U)          //!< Bit position for LLWU_ME_WUME3.
+#define BM_LLWU_ME_WUME3     (0x08U)       //!< Bit mask for LLWU_ME_WUME3.
+#define BS_LLWU_ME_WUME3     (1U)          //!< Bit field size in bits for LLWU_ME_WUME3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME3 field.
+#define BR_LLWU_ME_WUME3     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME3.
+#define BF_LLWU_ME_WUME3(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME3), uint8_t) & BM_LLWU_ME_WUME3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME3 field to a new value.
+#define BW_LLWU_ME_WUME3(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME4     (4U)          //!< Bit position for LLWU_ME_WUME4.
+#define BM_LLWU_ME_WUME4     (0x10U)       //!< Bit mask for LLWU_ME_WUME4.
+#define BS_LLWU_ME_WUME4     (1U)          //!< Bit field size in bits for LLWU_ME_WUME4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME4 field.
+#define BR_LLWU_ME_WUME4     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME4.
+#define BF_LLWU_ME_WUME4(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME4), uint8_t) & BM_LLWU_ME_WUME4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME4 field to a new value.
+#define BW_LLWU_ME_WUME4(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME5     (5U)          //!< Bit position for LLWU_ME_WUME5.
+#define BM_LLWU_ME_WUME5     (0x20U)       //!< Bit mask for LLWU_ME_WUME5.
+#define BS_LLWU_ME_WUME5     (1U)          //!< Bit field size in bits for LLWU_ME_WUME5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME5 field.
+#define BR_LLWU_ME_WUME5     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME5.
+#define BF_LLWU_ME_WUME5(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME5), uint8_t) & BM_LLWU_ME_WUME5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME5 field to a new value.
+#define BW_LLWU_ME_WUME5(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME6     (6U)          //!< Bit position for LLWU_ME_WUME6.
+#define BM_LLWU_ME_WUME6     (0x40U)       //!< Bit mask for LLWU_ME_WUME6.
+#define BS_LLWU_ME_WUME6     (1U)          //!< Bit field size in bits for LLWU_ME_WUME6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME6 field.
+#define BR_LLWU_ME_WUME6     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME6.
+#define BF_LLWU_ME_WUME6(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME6), uint8_t) & BM_LLWU_ME_WUME6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME6 field to a new value.
+#define BW_LLWU_ME_WUME6(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME7     (7U)          //!< Bit position for LLWU_ME_WUME7.
+#define BM_LLWU_ME_WUME7     (0x80U)       //!< Bit mask for LLWU_ME_WUME7.
+#define BS_LLWU_ME_WUME7     (1U)          //!< Bit field size in bits for LLWU_ME_WUME7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME7 field.
+#define BR_LLWU_ME_WUME7     (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME7.
+#define BF_LLWU_ME_WUME7(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME7), uint8_t) & BM_LLWU_ME_WUME7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME7 field to a new value.
+#define BW_LLWU_ME_WUME7(v)  (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_F1 - LLWU Flag 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_f1
+{
+    uint8_t U;
+    struct _hw_llwu_f1_bitfields
+    {
+        uint8_t WUF0 : 1;              //!< [0] Wakeup Flag For LLWU_P0
+        uint8_t WUF1 : 1;              //!< [1] Wakeup Flag For LLWU_P1
+        uint8_t WUF2 : 1;              //!< [2] Wakeup Flag For LLWU_P2
+        uint8_t WUF3 : 1;              //!< [3] Wakeup Flag For LLWU_P3
+        uint8_t WUF4 : 1;              //!< [4] Wakeup Flag For LLWU_P4
+        uint8_t WUF5 : 1;              //!< [5] Wakeup Flag For LLWU_P5
+        uint8_t WUF6 : 1;              //!< [6] Wakeup Flag For LLWU_P6
+        uint8_t WUF7 : 1;              //!< [7] Wakeup Flag For LLWU_P7
+    } B;
+} hw_llwu_f1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+//@{
+#define HW_LLWU_F1_ADDR          (REGS_LLWU_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_F1               (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR)
+#define HW_LLWU_F1_RD()          (HW_LLWU_F1.U)
+#define HW_LLWU_F1_WR(v)         (HW_LLWU_F1.U = (v))
+#define HW_LLWU_F1_SET(v)        (HW_LLWU_F1_WR(HW_LLWU_F1_RD() |  (v)))
+#define HW_LLWU_F1_CLR(v)        (HW_LLWU_F1_WR(HW_LLWU_F1_RD() & ~(v)))
+#define HW_LLWU_F1_TOG(v)        (HW_LLWU_F1_WR(HW_LLWU_F1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0 - LLWU_P0 input was not a wakeup source
+ * - 1 - LLWU_P0 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF0      (0U)          //!< Bit position for LLWU_F1_WUF0.
+#define BM_LLWU_F1_WUF0      (0x01U)       //!< Bit mask for LLWU_F1_WUF0.
+#define BS_LLWU_F1_WUF0      (1U)          //!< Bit field size in bits for LLWU_F1_WUF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF0 field.
+#define BR_LLWU_F1_WUF0      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF0.
+#define BF_LLWU_F1_WUF0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF0), uint8_t) & BM_LLWU_F1_WUF0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF0 field to a new value.
+#define BW_LLWU_F1_WUF0(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0 - LLWU_P1 input was not a wakeup source
+ * - 1 - LLWU_P1 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF1      (1U)          //!< Bit position for LLWU_F1_WUF1.
+#define BM_LLWU_F1_WUF1      (0x02U)       //!< Bit mask for LLWU_F1_WUF1.
+#define BS_LLWU_F1_WUF1      (1U)          //!< Bit field size in bits for LLWU_F1_WUF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF1 field.
+#define BR_LLWU_F1_WUF1      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF1.
+#define BF_LLWU_F1_WUF1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF1), uint8_t) & BM_LLWU_F1_WUF1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF1 field to a new value.
+#define BW_LLWU_F1_WUF1(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0 - LLWU_P2 input was not a wakeup source
+ * - 1 - LLWU_P2 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF2      (2U)          //!< Bit position for LLWU_F1_WUF2.
+#define BM_LLWU_F1_WUF2      (0x04U)       //!< Bit mask for LLWU_F1_WUF2.
+#define BS_LLWU_F1_WUF2      (1U)          //!< Bit field size in bits for LLWU_F1_WUF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF2 field.
+#define BR_LLWU_F1_WUF2      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF2.
+#define BF_LLWU_F1_WUF2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF2), uint8_t) & BM_LLWU_F1_WUF2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF2 field to a new value.
+#define BW_LLWU_F1_WUF2(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0 - LLWU_P3 input was not a wake-up source
+ * - 1 - LLWU_P3 input was a wake-up source
+ */
+//@{
+#define BP_LLWU_F1_WUF3      (3U)          //!< Bit position for LLWU_F1_WUF3.
+#define BM_LLWU_F1_WUF3      (0x08U)       //!< Bit mask for LLWU_F1_WUF3.
+#define BS_LLWU_F1_WUF3      (1U)          //!< Bit field size in bits for LLWU_F1_WUF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF3 field.
+#define BR_LLWU_F1_WUF3      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF3.
+#define BF_LLWU_F1_WUF3(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF3), uint8_t) & BM_LLWU_F1_WUF3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF3 field to a new value.
+#define BW_LLWU_F1_WUF3(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0 - LLWU_P4 input was not a wakeup source
+ * - 1 - LLWU_P4 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF4      (4U)          //!< Bit position for LLWU_F1_WUF4.
+#define BM_LLWU_F1_WUF4      (0x10U)       //!< Bit mask for LLWU_F1_WUF4.
+#define BS_LLWU_F1_WUF4      (1U)          //!< Bit field size in bits for LLWU_F1_WUF4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF4 field.
+#define BR_LLWU_F1_WUF4      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF4.
+#define BF_LLWU_F1_WUF4(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF4), uint8_t) & BM_LLWU_F1_WUF4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF4 field to a new value.
+#define BW_LLWU_F1_WUF4(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0 - LLWU_P5 input was not a wakeup source
+ * - 1 - LLWU_P5 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF5      (5U)          //!< Bit position for LLWU_F1_WUF5.
+#define BM_LLWU_F1_WUF5      (0x20U)       //!< Bit mask for LLWU_F1_WUF5.
+#define BS_LLWU_F1_WUF5      (1U)          //!< Bit field size in bits for LLWU_F1_WUF5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF5 field.
+#define BR_LLWU_F1_WUF5      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF5.
+#define BF_LLWU_F1_WUF5(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF5), uint8_t) & BM_LLWU_F1_WUF5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF5 field to a new value.
+#define BW_LLWU_F1_WUF5(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0 - LLWU_P6 input was not a wakeup source
+ * - 1 - LLWU_P6 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF6      (6U)          //!< Bit position for LLWU_F1_WUF6.
+#define BM_LLWU_F1_WUF6      (0x40U)       //!< Bit mask for LLWU_F1_WUF6.
+#define BS_LLWU_F1_WUF6      (1U)          //!< Bit field size in bits for LLWU_F1_WUF6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF6 field.
+#define BR_LLWU_F1_WUF6      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF6.
+#define BF_LLWU_F1_WUF6(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF6), uint8_t) & BM_LLWU_F1_WUF6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF6 field to a new value.
+#define BW_LLWU_F1_WUF6(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0 - LLWU_P7 input was not a wakeup source
+ * - 1 - LLWU_P7 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF7      (7U)          //!< Bit position for LLWU_F1_WUF7.
+#define BM_LLWU_F1_WUF7      (0x80U)       //!< Bit mask for LLWU_F1_WUF7.
+#define BS_LLWU_F1_WUF7      (1U)          //!< Bit field size in bits for LLWU_F1_WUF7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF7 field.
+#define BR_LLWU_F1_WUF7      (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF7.
+#define BF_LLWU_F1_WUF7(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF7), uint8_t) & BM_LLWU_F1_WUF7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF7 field to a new value.
+#define BW_LLWU_F1_WUF7(v)   (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_F2 - LLWU Flag 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_f2
+{
+    uint8_t U;
+    struct _hw_llwu_f2_bitfields
+    {
+        uint8_t WUF8 : 1;              //!< [0] Wakeup Flag For LLWU_P8
+        uint8_t WUF9 : 1;              //!< [1] Wakeup Flag For LLWU_P9
+        uint8_t WUF10 : 1;             //!< [2] Wakeup Flag For LLWU_P10
+        uint8_t WUF11 : 1;             //!< [3] Wakeup Flag For LLWU_P11
+        uint8_t WUF12 : 1;             //!< [4] Wakeup Flag For LLWU_P12
+        uint8_t WUF13 : 1;             //!< [5] Wakeup Flag For LLWU_P13
+        uint8_t WUF14 : 1;             //!< [6] Wakeup Flag For LLWU_P14
+        uint8_t WUF15 : 1;             //!< [7] Wakeup Flag For LLWU_P15
+    } B;
+} hw_llwu_f2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+//@{
+#define HW_LLWU_F2_ADDR          (REGS_LLWU_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_F2               (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR)
+#define HW_LLWU_F2_RD()          (HW_LLWU_F2.U)
+#define HW_LLWU_F2_WR(v)         (HW_LLWU_F2.U = (v))
+#define HW_LLWU_F2_SET(v)        (HW_LLWU_F2_WR(HW_LLWU_F2_RD() |  (v)))
+#define HW_LLWU_F2_CLR(v)        (HW_LLWU_F2_WR(HW_LLWU_F2_RD() & ~(v)))
+#define HW_LLWU_F2_TOG(v)        (HW_LLWU_F2_WR(HW_LLWU_F2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0 - LLWU_P8 input was not a wakeup source
+ * - 1 - LLWU_P8 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF8      (0U)          //!< Bit position for LLWU_F2_WUF8.
+#define BM_LLWU_F2_WUF8      (0x01U)       //!< Bit mask for LLWU_F2_WUF8.
+#define BS_LLWU_F2_WUF8      (1U)          //!< Bit field size in bits for LLWU_F2_WUF8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF8 field.
+#define BR_LLWU_F2_WUF8      (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF8.
+#define BF_LLWU_F2_WUF8(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF8), uint8_t) & BM_LLWU_F2_WUF8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF8 field to a new value.
+#define BW_LLWU_F2_WUF8(v)   (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0 - LLWU_P9 input was not a wakeup source
+ * - 1 - LLWU_P9 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF9      (1U)          //!< Bit position for LLWU_F2_WUF9.
+#define BM_LLWU_F2_WUF9      (0x02U)       //!< Bit mask for LLWU_F2_WUF9.
+#define BS_LLWU_F2_WUF9      (1U)          //!< Bit field size in bits for LLWU_F2_WUF9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF9 field.
+#define BR_LLWU_F2_WUF9      (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF9.
+#define BF_LLWU_F2_WUF9(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF9), uint8_t) & BM_LLWU_F2_WUF9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF9 field to a new value.
+#define BW_LLWU_F2_WUF9(v)   (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0 - LLWU_P10 input was not a wakeup source
+ * - 1 - LLWU_P10 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF10     (2U)          //!< Bit position for LLWU_F2_WUF10.
+#define BM_LLWU_F2_WUF10     (0x04U)       //!< Bit mask for LLWU_F2_WUF10.
+#define BS_LLWU_F2_WUF10     (1U)          //!< Bit field size in bits for LLWU_F2_WUF10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF10 field.
+#define BR_LLWU_F2_WUF10     (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF10.
+#define BF_LLWU_F2_WUF10(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF10), uint8_t) & BM_LLWU_F2_WUF10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF10 field to a new value.
+#define BW_LLWU_F2_WUF10(v)  (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0 - LLWU_P11 input was not a wakeup source
+ * - 1 - LLWU_P11 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF11     (3U)          //!< Bit position for LLWU_F2_WUF11.
+#define BM_LLWU_F2_WUF11     (0x08U)       //!< Bit mask for LLWU_F2_WUF11.
+#define BS_LLWU_F2_WUF11     (1U)          //!< Bit field size in bits for LLWU_F2_WUF11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF11 field.
+#define BR_LLWU_F2_WUF11     (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF11.
+#define BF_LLWU_F2_WUF11(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF11), uint8_t) & BM_LLWU_F2_WUF11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF11 field to a new value.
+#define BW_LLWU_F2_WUF11(v)  (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0 - LLWU_P12 input was not a wakeup source
+ * - 1 - LLWU_P12 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF12     (4U)          //!< Bit position for LLWU_F2_WUF12.
+#define BM_LLWU_F2_WUF12     (0x10U)       //!< Bit mask for LLWU_F2_WUF12.
+#define BS_LLWU_F2_WUF12     (1U)          //!< Bit field size in bits for LLWU_F2_WUF12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF12 field.
+#define BR_LLWU_F2_WUF12     (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF12.
+#define BF_LLWU_F2_WUF12(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF12), uint8_t) & BM_LLWU_F2_WUF12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF12 field to a new value.
+#define BW_LLWU_F2_WUF12(v)  (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0 - LLWU_P13 input was not a wakeup source
+ * - 1 - LLWU_P13 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF13     (5U)          //!< Bit position for LLWU_F2_WUF13.
+#define BM_LLWU_F2_WUF13     (0x20U)       //!< Bit mask for LLWU_F2_WUF13.
+#define BS_LLWU_F2_WUF13     (1U)          //!< Bit field size in bits for LLWU_F2_WUF13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF13 field.
+#define BR_LLWU_F2_WUF13     (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF13.
+#define BF_LLWU_F2_WUF13(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF13), uint8_t) & BM_LLWU_F2_WUF13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF13 field to a new value.
+#define BW_LLWU_F2_WUF13(v)  (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0 - LLWU_P14 input was not a wakeup source
+ * - 1 - LLWU_P14 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF14     (6U)          //!< Bit position for LLWU_F2_WUF14.
+#define BM_LLWU_F2_WUF14     (0x40U)       //!< Bit mask for LLWU_F2_WUF14.
+#define BS_LLWU_F2_WUF14     (1U)          //!< Bit field size in bits for LLWU_F2_WUF14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF14 field.
+#define BR_LLWU_F2_WUF14     (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF14.
+#define BF_LLWU_F2_WUF14(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF14), uint8_t) & BM_LLWU_F2_WUF14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF14 field to a new value.
+#define BW_LLWU_F2_WUF14(v)  (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0 - LLWU_P15 input was not a wakeup source
+ * - 1 - LLWU_P15 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF15     (7U)          //!< Bit position for LLWU_F2_WUF15.
+#define BM_LLWU_F2_WUF15     (0x80U)       //!< Bit mask for LLWU_F2_WUF15.
+#define BS_LLWU_F2_WUF15     (1U)          //!< Bit field size in bits for LLWU_F2_WUF15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF15 field.
+#define BR_LLWU_F2_WUF15     (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF15.
+#define BF_LLWU_F2_WUF15(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF15), uint8_t) & BM_LLWU_F2_WUF15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF15 field to a new value.
+#define BW_LLWU_F2_WUF15(v)  (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_F3 - LLWU Flag 3 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+typedef union _hw_llwu_f3
+{
+    uint8_t U;
+    struct _hw_llwu_f3_bitfields
+    {
+        uint8_t MWUF0 : 1;             //!< [0] Wakeup flag For module 0
+        uint8_t MWUF1 : 1;             //!< [1] Wakeup flag For module 1
+        uint8_t MWUF2 : 1;             //!< [2] Wakeup flag For module 2
+        uint8_t MWUF3 : 1;             //!< [3] Wakeup flag For module 3
+        uint8_t MWUF4 : 1;             //!< [4] Wakeup flag For module 4
+        uint8_t MWUF5 : 1;             //!< [5] Wakeup flag For module 5
+        uint8_t MWUF6 : 1;             //!< [6] Wakeup flag For module 6
+        uint8_t MWUF7 : 1;             //!< [7] Wakeup flag For module 7
+    } B;
+} hw_llwu_f3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+//@{
+#define HW_LLWU_F3_ADDR          (REGS_LLWU_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_F3               (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR)
+#define HW_LLWU_F3_RD()          (HW_LLWU_F3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 0 input was not a wakeup source
+ * - 1 - Module 0 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF0     (0U)          //!< Bit position for LLWU_F3_MWUF0.
+#define BM_LLWU_F3_MWUF0     (0x01U)       //!< Bit mask for LLWU_F3_MWUF0.
+#define BS_LLWU_F3_MWUF0     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF0 field.
+#define BR_LLWU_F3_MWUF0     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF0))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 1 input was not a wakeup source
+ * - 1 - Module 1 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF1     (1U)          //!< Bit position for LLWU_F3_MWUF1.
+#define BM_LLWU_F3_MWUF1     (0x02U)       //!< Bit mask for LLWU_F3_MWUF1.
+#define BS_LLWU_F3_MWUF1     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF1 field.
+#define BR_LLWU_F3_MWUF1     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF1))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 2 input was not a wakeup source
+ * - 1 - Module 2 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF2     (2U)          //!< Bit position for LLWU_F3_MWUF2.
+#define BM_LLWU_F3_MWUF2     (0x04U)       //!< Bit mask for LLWU_F3_MWUF2.
+#define BS_LLWU_F3_MWUF2     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF2 field.
+#define BR_LLWU_F3_MWUF2     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF2))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 3 input was not a wakeup source
+ * - 1 - Module 3 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF3     (3U)          //!< Bit position for LLWU_F3_MWUF3.
+#define BM_LLWU_F3_MWUF3     (0x08U)       //!< Bit mask for LLWU_F3_MWUF3.
+#define BS_LLWU_F3_MWUF3     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF3 field.
+#define BR_LLWU_F3_MWUF3     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF3))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 4 input was not a wakeup source
+ * - 1 - Module 4 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF4     (4U)          //!< Bit position for LLWU_F3_MWUF4.
+#define BM_LLWU_F3_MWUF4     (0x10U)       //!< Bit mask for LLWU_F3_MWUF4.
+#define BS_LLWU_F3_MWUF4     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF4 field.
+#define BR_LLWU_F3_MWUF4     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF4))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 5 input was not a wakeup source
+ * - 1 - Module 5 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF5     (5U)          //!< Bit position for LLWU_F3_MWUF5.
+#define BM_LLWU_F3_MWUF5     (0x20U)       //!< Bit mask for LLWU_F3_MWUF5.
+#define BS_LLWU_F3_MWUF5     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF5 field.
+#define BR_LLWU_F3_MWUF5     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF5))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 6 input was not a wakeup source
+ * - 1 - Module 6 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF6     (6U)          //!< Bit position for LLWU_F3_MWUF6.
+#define BM_LLWU_F3_MWUF6     (0x40U)       //!< Bit mask for LLWU_F3_MWUF6.
+#define BS_LLWU_F3_MWUF6     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF6 field.
+#define BR_LLWU_F3_MWUF6     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF6))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 7 input was not a wakeup source
+ * - 1 - Module 7 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF7     (7U)          //!< Bit position for LLWU_F3_MWUF7.
+#define BM_LLWU_F3_MWUF7     (0x80U)       //!< Bit mask for LLWU_F3_MWUF7.
+#define BS_LLWU_F3_MWUF7     (1U)          //!< Bit field size in bits for LLWU_F3_MWUF7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF7 field.
+#define BR_LLWU_F3_MWUF7     (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF7))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_FILT1 - LLWU Pin Filter 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_filt1
+{
+    uint8_t U;
+    struct _hw_llwu_filt1_bitfields
+    {
+        uint8_t FILTSEL : 4;           //!< [3:0] Filter Pin Select
+        uint8_t RESERVED0 : 1;         //!< [4]
+        uint8_t FILTE : 2;             //!< [6:5] Digital Filter On External Pin
+        uint8_t FILTF : 1;             //!< [7] Filter Detect Flag
+    } B;
+} hw_llwu_filt1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+//@{
+#define HW_LLWU_FILT1_ADDR       (REGS_LLWU_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_FILT1            (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR)
+#define HW_LLWU_FILT1_RD()       (HW_LLWU_FILT1.U)
+#define HW_LLWU_FILT1_WR(v)      (HW_LLWU_FILT1.U = (v))
+#define HW_LLWU_FILT1_SET(v)     (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() |  (v)))
+#define HW_LLWU_FILT1_CLR(v)     (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() & ~(v)))
+#define HW_LLWU_FILT1_TOG(v)     (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0000 - Select LLWU_P0 for filter
+ * - 1111 - Select LLWU_P15 for filter
+ */
+//@{
+#define BP_LLWU_FILT1_FILTSEL (0U)         //!< Bit position for LLWU_FILT1_FILTSEL.
+#define BM_LLWU_FILT1_FILTSEL (0x0FU)      //!< Bit mask for LLWU_FILT1_FILTSEL.
+#define BS_LLWU_FILT1_FILTSEL (4U)         //!< Bit field size in bits for LLWU_FILT1_FILTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT1_FILTSEL field.
+#define BR_LLWU_FILT1_FILTSEL (HW_LLWU_FILT1.B.FILTSEL)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT1_FILTSEL.
+#define BF_LLWU_FILT1_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTSEL), uint8_t) & BM_LLWU_FILT1_FILTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTSEL field to a new value.
+#define BW_LLWU_FILT1_FILTSEL(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 00 - Filter disabled
+ * - 01 - Filter posedge detect enabled
+ * - 10 - Filter negedge detect enabled
+ * - 11 - Filter any edge detect enabled
+ */
+//@{
+#define BP_LLWU_FILT1_FILTE  (5U)          //!< Bit position for LLWU_FILT1_FILTE.
+#define BM_LLWU_FILT1_FILTE  (0x60U)       //!< Bit mask for LLWU_FILT1_FILTE.
+#define BS_LLWU_FILT1_FILTE  (2U)          //!< Bit field size in bits for LLWU_FILT1_FILTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT1_FILTE field.
+#define BR_LLWU_FILT1_FILTE  (HW_LLWU_FILT1.B.FILTE)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT1_FILTE.
+#define BF_LLWU_FILT1_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTE), uint8_t) & BM_LLWU_FILT1_FILTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTE field to a new value.
+#define BW_LLWU_FILT1_FILTE(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0 - Pin Filter 1 was not a wakeup source
+ * - 1 - Pin Filter 1 was a wakeup source
+ */
+//@{
+#define BP_LLWU_FILT1_FILTF  (7U)          //!< Bit position for LLWU_FILT1_FILTF.
+#define BM_LLWU_FILT1_FILTF  (0x80U)       //!< Bit mask for LLWU_FILT1_FILTF.
+#define BS_LLWU_FILT1_FILTF  (1U)          //!< Bit field size in bits for LLWU_FILT1_FILTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT1_FILTF field.
+#define BR_LLWU_FILT1_FILTF  (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF))
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT1_FILTF.
+#define BF_LLWU_FILT1_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTF), uint8_t) & BM_LLWU_FILT1_FILTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTF field to a new value.
+#define BW_LLWU_FILT1_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_FILT2 - LLWU Pin Filter 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_filt2
+{
+    uint8_t U;
+    struct _hw_llwu_filt2_bitfields
+    {
+        uint8_t FILTSEL : 4;           //!< [3:0] Filter Pin Select
+        uint8_t RESERVED0 : 1;         //!< [4]
+        uint8_t FILTE : 2;             //!< [6:5] Digital Filter On External Pin
+        uint8_t FILTF : 1;             //!< [7] Filter Detect Flag
+    } B;
+} hw_llwu_filt2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+//@{
+#define HW_LLWU_FILT2_ADDR       (REGS_LLWU_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_FILT2            (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR)
+#define HW_LLWU_FILT2_RD()       (HW_LLWU_FILT2.U)
+#define HW_LLWU_FILT2_WR(v)      (HW_LLWU_FILT2.U = (v))
+#define HW_LLWU_FILT2_SET(v)     (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() |  (v)))
+#define HW_LLWU_FILT2_CLR(v)     (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() & ~(v)))
+#define HW_LLWU_FILT2_TOG(v)     (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0000 - Select LLWU_P0 for filter
+ * - 1111 - Select LLWU_P15 for filter
+ */
+//@{
+#define BP_LLWU_FILT2_FILTSEL (0U)         //!< Bit position for LLWU_FILT2_FILTSEL.
+#define BM_LLWU_FILT2_FILTSEL (0x0FU)      //!< Bit mask for LLWU_FILT2_FILTSEL.
+#define BS_LLWU_FILT2_FILTSEL (4U)         //!< Bit field size in bits for LLWU_FILT2_FILTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT2_FILTSEL field.
+#define BR_LLWU_FILT2_FILTSEL (HW_LLWU_FILT2.B.FILTSEL)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT2_FILTSEL.
+#define BF_LLWU_FILT2_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTSEL), uint8_t) & BM_LLWU_FILT2_FILTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTSEL field to a new value.
+#define BW_LLWU_FILT2_FILTSEL(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 00 - Filter disabled
+ * - 01 - Filter posedge detect enabled
+ * - 10 - Filter negedge detect enabled
+ * - 11 - Filter any edge detect enabled
+ */
+//@{
+#define BP_LLWU_FILT2_FILTE  (5U)          //!< Bit position for LLWU_FILT2_FILTE.
+#define BM_LLWU_FILT2_FILTE  (0x60U)       //!< Bit mask for LLWU_FILT2_FILTE.
+#define BS_LLWU_FILT2_FILTE  (2U)          //!< Bit field size in bits for LLWU_FILT2_FILTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT2_FILTE field.
+#define BR_LLWU_FILT2_FILTE  (HW_LLWU_FILT2.B.FILTE)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT2_FILTE.
+#define BF_LLWU_FILT2_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTE), uint8_t) & BM_LLWU_FILT2_FILTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTE field to a new value.
+#define BW_LLWU_FILT2_FILTE(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0 - Pin Filter 2 was not a wakeup source
+ * - 1 - Pin Filter 2 was a wakeup source
+ */
+//@{
+#define BP_LLWU_FILT2_FILTF  (7U)          //!< Bit position for LLWU_FILT2_FILTF.
+#define BM_LLWU_FILT2_FILTF  (0x80U)       //!< Bit mask for LLWU_FILT2_FILTF.
+#define BS_LLWU_FILT2_FILTF  (1U)          //!< Bit field size in bits for LLWU_FILT2_FILTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT2_FILTF field.
+#define BR_LLWU_FILT2_FILTF  (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF))
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT2_FILTF.
+#define BF_LLWU_FILT2_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTF), uint8_t) & BM_LLWU_FILT2_FILTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTF field to a new value.
+#define BW_LLWU_FILT2_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_RST - LLWU Reset Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_rst
+{
+    uint8_t U;
+    struct _hw_llwu_rst_bitfields
+    {
+        uint8_t RSTFILT : 1;           //!< [0] Digital Filter On RESET Pin
+        uint8_t LLRSTE : 1;            //!< [1] Low-Leakage Mode RESET Enable
+        uint8_t RESERVED0 : 6;         //!< [7:2]
+    } B;
+} hw_llwu_rst_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+//@{
+#define HW_LLWU_RST_ADDR         (REGS_LLWU_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_RST              (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR)
+#define HW_LLWU_RST_RD()         (HW_LLWU_RST.U)
+#define HW_LLWU_RST_WR(v)        (HW_LLWU_RST.U = (v))
+#define HW_LLWU_RST_SET(v)       (HW_LLWU_RST_WR(HW_LLWU_RST_RD() |  (v)))
+#define HW_LLWU_RST_CLR(v)       (HW_LLWU_RST_WR(HW_LLWU_RST_RD() & ~(v)))
+#define HW_LLWU_RST_TOG(v)       (HW_LLWU_RST_WR(HW_LLWU_RST_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0 - Filter not enabled
+ * - 1 - Filter enabled
+ */
+//@{
+#define BP_LLWU_RST_RSTFILT  (0U)          //!< Bit position for LLWU_RST_RSTFILT.
+#define BM_LLWU_RST_RSTFILT  (0x01U)       //!< Bit mask for LLWU_RST_RSTFILT.
+#define BS_LLWU_RST_RSTFILT  (1U)          //!< Bit field size in bits for LLWU_RST_RSTFILT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_RST_RSTFILT field.
+#define BR_LLWU_RST_RSTFILT  (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT))
+#endif
+
+//! @brief Format value for bitfield LLWU_RST_RSTFILT.
+#define BF_LLWU_RST_RSTFILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_RSTFILT), uint8_t) & BM_LLWU_RST_RSTFILT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFILT field to a new value.
+#define BW_LLWU_RST_RSTFILT(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0 - RESET pin not enabled as a leakage mode exit source
+ * - 1 - RESET pin enabled as a low leakage mode exit source
+ */
+//@{
+#define BP_LLWU_RST_LLRSTE   (1U)          //!< Bit position for LLWU_RST_LLRSTE.
+#define BM_LLWU_RST_LLRSTE   (0x02U)       //!< Bit mask for LLWU_RST_LLRSTE.
+#define BS_LLWU_RST_LLRSTE   (1U)          //!< Bit field size in bits for LLWU_RST_LLRSTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_RST_LLRSTE field.
+#define BR_LLWU_RST_LLRSTE   (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE))
+#endif
+
+//! @brief Format value for bitfield LLWU_RST_LLRSTE.
+#define BF_LLWU_RST_LLRSTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_LLRSTE), uint8_t) & BM_LLWU_RST_LLRSTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LLRSTE field to a new value.
+#define BW_LLWU_RST_LLRSTE(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_llwu_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All LLWU module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_llwu
+{
+    __IO hw_llwu_pe1_t PE1;                //!< [0x0] LLWU Pin Enable 1 register
+    __IO hw_llwu_pe2_t PE2;                //!< [0x1] LLWU Pin Enable 2 register
+    __IO hw_llwu_pe3_t PE3;                //!< [0x2] LLWU Pin Enable 3 register
+    __IO hw_llwu_pe4_t PE4;                //!< [0x3] LLWU Pin Enable 4 register
+    __IO hw_llwu_me_t ME;                  //!< [0x4] LLWU Module Enable register
+    __IO hw_llwu_f1_t F1;                  //!< [0x5] LLWU Flag 1 register
+    __IO hw_llwu_f2_t F2;                  //!< [0x6] LLWU Flag 2 register
+    __I hw_llwu_f3_t F3;                   //!< [0x7] LLWU Flag 3 register
+    __IO hw_llwu_filt1_t FILT1;            //!< [0x8] LLWU Pin Filter 1 register
+    __IO hw_llwu_filt2_t FILT2;            //!< [0x9] LLWU Pin Filter 2 register
+    __IO hw_llwu_rst_t RST;                //!< [0xA] LLWU Reset Enable register
+} hw_llwu_t;
+#pragma pack()
+
+//! @brief Macro to access all LLWU registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_LLWU</code>.
+#define HW_LLWU        (*(hw_llwu_t *) REGS_LLWU_BASE)
+#endif
+
+#endif // __HW_LLWU_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h
new file mode 100644
index 0000000000..0caa4cc7bd
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_LPTMR_REGISTERS_H__
+#define __HW_LPTMR_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - HW_LPTMR_CSR - Low Power Timer Control Status Register
+ * - HW_LPTMR_PSR - Low Power Timer Prescale Register
+ * - HW_LPTMR_CMR - Low Power Timer Compare Register
+ * - HW_LPTMR_CNR - Low Power Timer Counter Register
+ *
+ * - hw_lptmr_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_LPTMR_BASE
+#define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module.
+#define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_CSR - Low Power Timer Control Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_csr
+{
+    uint32_t U;
+    struct _hw_lptmr_csr_bitfields
+    {
+        uint32_t TEN : 1;              //!< [0] Timer Enable
+        uint32_t TMS : 1;              //!< [1] Timer Mode Select
+        uint32_t TFC : 1;              //!< [2] Timer Free-Running Counter
+        uint32_t TPP : 1;              //!< [3] Timer Pin Polarity
+        uint32_t TPS : 2;              //!< [5:4] Timer Pin Select
+        uint32_t TIE : 1;              //!< [6] Timer Interrupt Enable
+        uint32_t TCF : 1;              //!< [7] Timer Compare Flag
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_lptmr_csr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+//@{
+#define HW_LPTMR_CSR_ADDR        (REGS_LPTMR_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_CSR             (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR)
+#define HW_LPTMR_CSR_RD()        (HW_LPTMR_CSR.U)
+#define HW_LPTMR_CSR_WR(v)       (HW_LPTMR_CSR.U = (v))
+#define HW_LPTMR_CSR_SET(v)      (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() |  (v)))
+#define HW_LPTMR_CSR_CLR(v)      (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v)))
+#define HW_LPTMR_CSR_TOG(v)      (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0 - LPTMR is disabled and internal logic is reset.
+ * - 1 - LPTMR is enabled.
+ */
+//@{
+#define BP_LPTMR_CSR_TEN     (0U)          //!< Bit position for LPTMR_CSR_TEN.
+#define BM_LPTMR_CSR_TEN     (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN.
+#define BS_LPTMR_CSR_TEN     (1U)          //!< Bit field size in bits for LPTMR_CSR_TEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TEN field.
+#define BR_LPTMR_CSR_TEN     (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TEN.
+#define BF_LPTMR_CSR_TEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TEN field to a new value.
+#define BW_LPTMR_CSR_TEN(v)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0 - Time Counter mode.
+ * - 1 - Pulse Counter mode.
+ */
+//@{
+#define BP_LPTMR_CSR_TMS     (1U)          //!< Bit position for LPTMR_CSR_TMS.
+#define BM_LPTMR_CSR_TMS     (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS.
+#define BS_LPTMR_CSR_TMS     (1U)          //!< Bit field size in bits for LPTMR_CSR_TMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TMS field.
+#define BR_LPTMR_CSR_TMS     (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TMS.
+#define BF_LPTMR_CSR_TMS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TMS field to a new value.
+#define BW_LPTMR_CSR_TMS(v)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - CNR is reset whenever TCF is set.
+ * - 1 - CNR is reset on overflow.
+ */
+//@{
+#define BP_LPTMR_CSR_TFC     (2U)          //!< Bit position for LPTMR_CSR_TFC.
+#define BM_LPTMR_CSR_TFC     (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC.
+#define BS_LPTMR_CSR_TFC     (1U)          //!< Bit field size in bits for LPTMR_CSR_TFC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TFC field.
+#define BR_LPTMR_CSR_TFC     (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TFC.
+#define BF_LPTMR_CSR_TFC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFC field to a new value.
+#define BW_LPTMR_CSR_TFC(v)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
+ *     the falling-edge.
+ */
+//@{
+#define BP_LPTMR_CSR_TPP     (3U)          //!< Bit position for LPTMR_CSR_TPP.
+#define BM_LPTMR_CSR_TPP     (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP.
+#define BS_LPTMR_CSR_TPP     (1U)          //!< Bit field size in bits for LPTMR_CSR_TPP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TPP field.
+#define BR_LPTMR_CSR_TPP     (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TPP.
+#define BF_LPTMR_CSR_TPP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPP field to a new value.
+#define BW_LPTMR_CSR_TPP(v)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 00 - Pulse counter input 0 is selected.
+ * - 01 - Pulse counter input 1 is selected.
+ * - 10 - Pulse counter input 2 is selected.
+ * - 11 - Pulse counter input 3 is selected.
+ */
+//@{
+#define BP_LPTMR_CSR_TPS     (4U)          //!< Bit position for LPTMR_CSR_TPS.
+#define BM_LPTMR_CSR_TPS     (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS.
+#define BS_LPTMR_CSR_TPS     (2U)          //!< Bit field size in bits for LPTMR_CSR_TPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TPS field.
+#define BR_LPTMR_CSR_TPS     (HW_LPTMR_CSR.B.TPS)
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TPS.
+#define BF_LPTMR_CSR_TPS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPS field to a new value.
+#define BW_LPTMR_CSR_TPS(v)  (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0 - Timer interrupt disabled.
+ * - 1 - Timer interrupt enabled.
+ */
+//@{
+#define BP_LPTMR_CSR_TIE     (6U)          //!< Bit position for LPTMR_CSR_TIE.
+#define BM_LPTMR_CSR_TIE     (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE.
+#define BS_LPTMR_CSR_TIE     (1U)          //!< Bit field size in bits for LPTMR_CSR_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TIE field.
+#define BR_LPTMR_CSR_TIE     (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TIE.
+#define BF_LPTMR_CSR_TIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_LPTMR_CSR_TIE(v)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0 - The value of CNR is not equal to CMR and increments.
+ * - 1 - The value of CNR is equal to CMR and increments.
+ */
+//@{
+#define BP_LPTMR_CSR_TCF     (7U)          //!< Bit position for LPTMR_CSR_TCF.
+#define BM_LPTMR_CSR_TCF     (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF.
+#define BS_LPTMR_CSR_TCF     (1U)          //!< Bit field size in bits for LPTMR_CSR_TCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TCF field.
+#define BR_LPTMR_CSR_TCF     (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TCF.
+#define BF_LPTMR_CSR_TCF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCF field to a new value.
+#define BW_LPTMR_CSR_TCF(v)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_PSR - Low Power Timer Prescale Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_psr
+{
+    uint32_t U;
+    struct _hw_lptmr_psr_bitfields
+    {
+        uint32_t PCS : 2;              //!< [1:0] Prescaler Clock Select
+        uint32_t PBYP : 1;             //!< [2] Prescaler Bypass
+        uint32_t PRESCALE : 4;         //!< [6:3] Prescale Value
+        uint32_t RESERVED0 : 25;       //!< [31:7]
+    } B;
+} hw_lptmr_psr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+//@{
+#define HW_LPTMR_PSR_ADDR        (REGS_LPTMR_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_PSR             (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR)
+#define HW_LPTMR_PSR_RD()        (HW_LPTMR_PSR.U)
+#define HW_LPTMR_PSR_WR(v)       (HW_LPTMR_PSR.U = (v))
+#define HW_LPTMR_PSR_SET(v)      (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() |  (v)))
+#define HW_LPTMR_PSR_CLR(v)      (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v)))
+#define HW_LPTMR_PSR_TOG(v)      (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 00 - Prescaler/glitch filter clock 0 selected.
+ * - 01 - Prescaler/glitch filter clock 1 selected.
+ * - 10 - Prescaler/glitch filter clock 2 selected.
+ * - 11 - Prescaler/glitch filter clock 3 selected.
+ */
+//@{
+#define BP_LPTMR_PSR_PCS     (0U)          //!< Bit position for LPTMR_PSR_PCS.
+#define BM_LPTMR_PSR_PCS     (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS.
+#define BS_LPTMR_PSR_PCS     (2U)          //!< Bit field size in bits for LPTMR_PSR_PCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_PSR_PCS field.
+#define BR_LPTMR_PSR_PCS     (HW_LPTMR_PSR.B.PCS)
+#endif
+
+//! @brief Format value for bitfield LPTMR_PSR_PCS.
+#define BF_LPTMR_PSR_PCS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCS field to a new value.
+#define BW_LPTMR_PSR_PCS(v)  (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - Prescaler/glitch filter is enabled.
+ * - 1 - Prescaler/glitch filter is bypassed.
+ */
+//@{
+#define BP_LPTMR_PSR_PBYP    (2U)          //!< Bit position for LPTMR_PSR_PBYP.
+#define BM_LPTMR_PSR_PBYP    (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP.
+#define BS_LPTMR_PSR_PBYP    (1U)          //!< Bit field size in bits for LPTMR_PSR_PBYP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_PSR_PBYP field.
+#define BR_LPTMR_PSR_PBYP    (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP))
+#endif
+
+//! @brief Format value for bitfield LPTMR_PSR_PBYP.
+#define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PBYP field to a new value.
+#define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
+ *     change on input pin after 2 rising clock edges.
+ * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
+ *     change on input pin after 4 rising clock edges.
+ * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+//@{
+#define BP_LPTMR_PSR_PRESCALE (3U)         //!< Bit position for LPTMR_PSR_PRESCALE.
+#define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE.
+#define BS_LPTMR_PSR_PRESCALE (4U)         //!< Bit field size in bits for LPTMR_PSR_PRESCALE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_PSR_PRESCALE field.
+#define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE)
+#endif
+
+//! @brief Format value for bitfield LPTMR_PSR_PRESCALE.
+#define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCALE field to a new value.
+#define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_CMR - Low Power Timer Compare Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_cmr
+{
+    uint32_t U;
+    struct _hw_lptmr_cmr_bitfields
+    {
+        uint32_t COMPARE : 16;         //!< [15:0] Compare Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_lptmr_cmr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+//@{
+#define HW_LPTMR_CMR_ADDR        (REGS_LPTMR_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_CMR             (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR)
+#define HW_LPTMR_CMR_RD()        (HW_LPTMR_CMR.U)
+#define HW_LPTMR_CMR_WR(v)       (HW_LPTMR_CMR.U = (v))
+#define HW_LPTMR_CMR_SET(v)      (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() |  (v)))
+#define HW_LPTMR_CMR_CLR(v)      (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v)))
+#define HW_LPTMR_CMR_TOG(v)      (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+//@{
+#define BP_LPTMR_CMR_COMPARE (0U)          //!< Bit position for LPTMR_CMR_COMPARE.
+#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE.
+#define BS_LPTMR_CMR_COMPARE (16U)         //!< Bit field size in bits for LPTMR_CMR_COMPARE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CMR_COMPARE field.
+#define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE)
+#endif
+
+//! @brief Format value for bitfield LPTMR_CMR_COMPARE.
+#define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPARE field to a new value.
+#define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_CNR - Low Power Timer Counter Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_cnr
+{
+    uint32_t U;
+    struct _hw_lptmr_cnr_bitfields
+    {
+        uint32_t COUNTER : 16;         //!< [15:0] Counter Value
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_lptmr_cnr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+//@{
+#define HW_LPTMR_CNR_ADDR        (REGS_LPTMR_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_CNR             (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR)
+#define HW_LPTMR_CNR_RD()        (HW_LPTMR_CNR.U)
+#define HW_LPTMR_CNR_WR(v)       (HW_LPTMR_CNR.U = (v))
+#define HW_LPTMR_CNR_SET(v)      (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() |  (v)))
+#define HW_LPTMR_CNR_CLR(v)      (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v)))
+#define HW_LPTMR_CNR_TOG(v)      (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+//@{
+#define BP_LPTMR_CNR_COUNTER (0U)          //!< Bit position for LPTMR_CNR_COUNTER.
+#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER.
+#define BS_LPTMR_CNR_COUNTER (16U)         //!< Bit field size in bits for LPTMR_CNR_COUNTER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CNR_COUNTER field.
+#define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER)
+#endif
+
+//! @brief Format value for bitfield LPTMR_CNR_COUNTER.
+#define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COUNTER field to a new value.
+#define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_lptmr_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All LPTMR module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_lptmr
+{
+    __IO hw_lptmr_csr_t CSR;               //!< [0x0] Low Power Timer Control Status Register
+    __IO hw_lptmr_psr_t PSR;               //!< [0x4] Low Power Timer Prescale Register
+    __IO hw_lptmr_cmr_t CMR;               //!< [0x8] Low Power Timer Compare Register
+    __IO hw_lptmr_cnr_t CNR;               //!< [0xC] Low Power Timer Counter Register
+} hw_lptmr_t;
+#pragma pack()
+
+//! @brief Macro to access all LPTMR registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_LPTMR</code>.
+#define HW_LPTMR       (*(hw_lptmr_t *) REGS_LPTMR_BASE)
+#endif
+
+#endif // __HW_LPTMR_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h
new file mode 100644
index 0000000000..f8e835e812
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h
@@ -0,0 +1,1939 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_MCG_REGISTERS_H__
+#define __HW_MCG_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - HW_MCG_C1 - MCG Control 1 Register
+ * - HW_MCG_C2 - MCG Control 2 Register
+ * - HW_MCG_C3 - MCG Control 3 Register
+ * - HW_MCG_C4 - MCG Control 4 Register
+ * - HW_MCG_C5 - MCG Control 5 Register
+ * - HW_MCG_C6 - MCG Control 6 Register
+ * - HW_MCG_S - MCG Status Register
+ * - HW_MCG_SC - MCG Status and Control Register
+ * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - HW_MCG_C7 - MCG Control 7 Register
+ * - HW_MCG_C8 - MCG Control 8 Register
+ *
+ * - hw_mcg_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_MCG_BASE
+#define HW_MCG_INSTANCE_COUNT (1U) //!< Number of instances of the MCG module.
+#define REGS_MCG_BASE (0x40064000U) //!< Base address for MCG.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C1 - MCG Control 1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+typedef union _hw_mcg_c1
+{
+    uint8_t U;
+    struct _hw_mcg_c1_bitfields
+    {
+        uint8_t IREFSTEN : 1;          //!< [0] Internal Reference Stop Enable
+        uint8_t IRCLKEN : 1;           //!< [1] Internal Reference Clock Enable
+        uint8_t IREFS : 1;             //!< [2] Internal Reference Select
+        uint8_t FRDIV : 3;             //!< [5:3] FLL External Reference Divider
+        uint8_t CLKS : 2;              //!< [7:6] Clock Source Select
+    } B;
+} hw_mcg_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+//@{
+#define HW_MCG_C1_ADDR           (REGS_MCG_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C1                (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR)
+#define HW_MCG_C1_RD()           (HW_MCG_C1.U)
+#define HW_MCG_C1_WR(v)          (HW_MCG_C1.U = (v))
+#define HW_MCG_C1_SET(v)         (HW_MCG_C1_WR(HW_MCG_C1_RD() |  (v)))
+#define HW_MCG_C1_CLR(v)         (HW_MCG_C1_WR(HW_MCG_C1_RD() & ~(v)))
+#define HW_MCG_C1_TOG(v)         (HW_MCG_C1_WR(HW_MCG_C1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0 - Internal reference clock is disabled in Stop mode.
+ * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+//@{
+#define BP_MCG_C1_IREFSTEN   (0U)          //!< Bit position for MCG_C1_IREFSTEN.
+#define BM_MCG_C1_IREFSTEN   (0x01U)       //!< Bit mask for MCG_C1_IREFSTEN.
+#define BS_MCG_C1_IREFSTEN   (1U)          //!< Bit field size in bits for MCG_C1_IREFSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_IREFSTEN field.
+#define BR_MCG_C1_IREFSTEN   (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN))
+#endif
+
+//! @brief Format value for bitfield MCG_C1_IREFSTEN.
+#define BF_MCG_C1_IREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFSTEN), uint8_t) & BM_MCG_C1_IREFSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IREFSTEN field to a new value.
+#define BW_MCG_C1_IREFSTEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0 - MCGIRCLK inactive.
+ * - 1 - MCGIRCLK active.
+ */
+//@{
+#define BP_MCG_C1_IRCLKEN    (1U)          //!< Bit position for MCG_C1_IRCLKEN.
+#define BM_MCG_C1_IRCLKEN    (0x02U)       //!< Bit mask for MCG_C1_IRCLKEN.
+#define BS_MCG_C1_IRCLKEN    (1U)          //!< Bit field size in bits for MCG_C1_IRCLKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_IRCLKEN field.
+#define BR_MCG_C1_IRCLKEN    (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN))
+#endif
+
+//! @brief Format value for bitfield MCG_C1_IRCLKEN.
+#define BF_MCG_C1_IRCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IRCLKEN), uint8_t) & BM_MCG_C1_IRCLKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRCLKEN field to a new value.
+#define BW_MCG_C1_IRCLKEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0 - External reference clock is selected.
+ * - 1 - The slow internal reference clock is selected.
+ */
+//@{
+#define BP_MCG_C1_IREFS      (2U)          //!< Bit position for MCG_C1_IREFS.
+#define BM_MCG_C1_IREFS      (0x04U)       //!< Bit mask for MCG_C1_IREFS.
+#define BS_MCG_C1_IREFS      (1U)          //!< Bit field size in bits for MCG_C1_IREFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_IREFS field.
+#define BR_MCG_C1_IREFS      (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS))
+#endif
+
+//! @brief Format value for bitfield MCG_C1_IREFS.
+#define BF_MCG_C1_IREFS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFS), uint8_t) & BM_MCG_C1_IREFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IREFS field to a new value.
+#define BW_MCG_C1_IREFS(v)   (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
+ *     values, Divide Factor is 1536 .
+ */
+//@{
+#define BP_MCG_C1_FRDIV      (3U)          //!< Bit position for MCG_C1_FRDIV.
+#define BM_MCG_C1_FRDIV      (0x38U)       //!< Bit mask for MCG_C1_FRDIV.
+#define BS_MCG_C1_FRDIV      (3U)          //!< Bit field size in bits for MCG_C1_FRDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_FRDIV field.
+#define BR_MCG_C1_FRDIV      (HW_MCG_C1.B.FRDIV)
+#endif
+
+//! @brief Format value for bitfield MCG_C1_FRDIV.
+#define BF_MCG_C1_FRDIV(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_FRDIV), uint8_t) & BM_MCG_C1_FRDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRDIV field to a new value.
+#define BW_MCG_C1_FRDIV(v)   (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
+ *     bit).
+ * - 01 - Encoding 1 - Internal reference clock is selected.
+ * - 10 - Encoding 2 - External reference clock is selected.
+ * - 11 - Encoding 3 - Reserved.
+ */
+//@{
+#define BP_MCG_C1_CLKS       (6U)          //!< Bit position for MCG_C1_CLKS.
+#define BM_MCG_C1_CLKS       (0xC0U)       //!< Bit mask for MCG_C1_CLKS.
+#define BS_MCG_C1_CLKS       (2U)          //!< Bit field size in bits for MCG_C1_CLKS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_CLKS field.
+#define BR_MCG_C1_CLKS       (HW_MCG_C1.B.CLKS)
+#endif
+
+//! @brief Format value for bitfield MCG_C1_CLKS.
+#define BF_MCG_C1_CLKS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_CLKS), uint8_t) & BM_MCG_C1_CLKS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKS field to a new value.
+#define BW_MCG_C1_CLKS(v)    (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C2 - MCG Control 2 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+typedef union _hw_mcg_c2
+{
+    uint8_t U;
+    struct _hw_mcg_c2_bitfields
+    {
+        uint8_t IRCS : 1;              //!< [0] Internal Reference Clock Select
+        uint8_t LP : 1;                //!< [1] Low Power Select
+        uint8_t EREFS : 1;             //!< [2] External Reference Select
+        uint8_t HGO : 1;               //!< [3] High Gain Oscillator Select
+        uint8_t RANGE : 2;             //!< [5:4] Frequency Range Select
+        uint8_t FCFTRIM : 1;           //!< [6] Fast Internal Reference Clock Fine Trim
+        uint8_t LOCRE0 : 1;            //!< [7] Loss of Clock Reset Enable
+    } B;
+} hw_mcg_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+//@{
+#define HW_MCG_C2_ADDR           (REGS_MCG_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C2                (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR)
+#define HW_MCG_C2_RD()           (HW_MCG_C2.U)
+#define HW_MCG_C2_WR(v)          (HW_MCG_C2.U = (v))
+#define HW_MCG_C2_SET(v)         (HW_MCG_C2_WR(HW_MCG_C2_RD() |  (v)))
+#define HW_MCG_C2_CLR(v)         (HW_MCG_C2_WR(HW_MCG_C2_RD() & ~(v)))
+#define HW_MCG_C2_TOG(v)         (HW_MCG_C2_WR(HW_MCG_C2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0 - Slow internal reference clock selected.
+ * - 1 - Fast internal reference clock selected.
+ */
+//@{
+#define BP_MCG_C2_IRCS       (0U)          //!< Bit position for MCG_C2_IRCS.
+#define BM_MCG_C2_IRCS       (0x01U)       //!< Bit mask for MCG_C2_IRCS.
+#define BS_MCG_C2_IRCS       (1U)          //!< Bit field size in bits for MCG_C2_IRCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_IRCS field.
+#define BR_MCG_C2_IRCS       (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_IRCS.
+#define BF_MCG_C2_IRCS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_IRCS), uint8_t) & BM_MCG_C2_IRCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRCS field to a new value.
+#define BW_MCG_C2_IRCS(v)    (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0 - FLL or PLL is not disabled in bypass modes.
+ * - 1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+//@{
+#define BP_MCG_C2_LP         (1U)          //!< Bit position for MCG_C2_LP.
+#define BM_MCG_C2_LP         (0x02U)       //!< Bit mask for MCG_C2_LP.
+#define BS_MCG_C2_LP         (1U)          //!< Bit field size in bits for MCG_C2_LP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_LP field.
+#define BR_MCG_C2_LP         (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_LP.
+#define BF_MCG_C2_LP(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LP), uint8_t) & BM_MCG_C2_LP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LP field to a new value.
+#define BW_MCG_C2_LP(v)      (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0 - External reference clock requested.
+ * - 1 - Oscillator requested.
+ */
+//@{
+#define BP_MCG_C2_EREFS      (2U)          //!< Bit position for MCG_C2_EREFS.
+#define BM_MCG_C2_EREFS      (0x04U)       //!< Bit mask for MCG_C2_EREFS.
+#define BS_MCG_C2_EREFS      (1U)          //!< Bit field size in bits for MCG_C2_EREFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_EREFS field.
+#define BR_MCG_C2_EREFS      (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_EREFS.
+#define BF_MCG_C2_EREFS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_EREFS), uint8_t) & BM_MCG_C2_EREFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EREFS field to a new value.
+#define BW_MCG_C2_EREFS(v)   (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0 - Configure crystal oscillator for low-power operation.
+ * - 1 - Configure crystal oscillator for high-gain operation.
+ */
+//@{
+#define BP_MCG_C2_HGO        (3U)          //!< Bit position for MCG_C2_HGO.
+#define BM_MCG_C2_HGO        (0x08U)       //!< Bit mask for MCG_C2_HGO.
+#define BS_MCG_C2_HGO        (1U)          //!< Bit field size in bits for MCG_C2_HGO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_HGO field.
+#define BR_MCG_C2_HGO        (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_HGO.
+#define BF_MCG_C2_HGO(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_HGO), uint8_t) & BM_MCG_C2_HGO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HGO field to a new value.
+#define BW_MCG_C2_HGO(v)     (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
+ * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
+ */
+//@{
+#define BP_MCG_C2_RANGE      (4U)          //!< Bit position for MCG_C2_RANGE.
+#define BM_MCG_C2_RANGE      (0x30U)       //!< Bit mask for MCG_C2_RANGE.
+#define BS_MCG_C2_RANGE      (2U)          //!< Bit field size in bits for MCG_C2_RANGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_RANGE field.
+#define BR_MCG_C2_RANGE      (HW_MCG_C2.B.RANGE)
+#endif
+
+//! @brief Format value for bitfield MCG_C2_RANGE.
+#define BF_MCG_C2_RANGE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_RANGE), uint8_t) & BM_MCG_C2_RANGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RANGE field to a new value.
+#define BW_MCG_C2_RANGE(v)   (HW_MCG_C2_WR((HW_MCG_C2_RD() & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+//@{
+#define BP_MCG_C2_FCFTRIM    (6U)          //!< Bit position for MCG_C2_FCFTRIM.
+#define BM_MCG_C2_FCFTRIM    (0x40U)       //!< Bit mask for MCG_C2_FCFTRIM.
+#define BS_MCG_C2_FCFTRIM    (1U)          //!< Bit field size in bits for MCG_C2_FCFTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_FCFTRIM field.
+#define BR_MCG_C2_FCFTRIM    (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_FCFTRIM.
+#define BF_MCG_C2_FCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_FCFTRIM), uint8_t) & BM_MCG_C2_FCFTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCFTRIM field to a new value.
+#define BW_MCG_C2_FCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+//@{
+#define BP_MCG_C2_LOCRE0     (7U)          //!< Bit position for MCG_C2_LOCRE0.
+#define BM_MCG_C2_LOCRE0     (0x80U)       //!< Bit mask for MCG_C2_LOCRE0.
+#define BS_MCG_C2_LOCRE0     (1U)          //!< Bit field size in bits for MCG_C2_LOCRE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_LOCRE0 field.
+#define BR_MCG_C2_LOCRE0     (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_LOCRE0.
+#define BF_MCG_C2_LOCRE0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LOCRE0), uint8_t) & BM_MCG_C2_LOCRE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCRE0 field to a new value.
+#define BW_MCG_C2_LOCRE0(v)  (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C3 - MCG Control 3 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c3
+{
+    uint8_t U;
+    struct _hw_mcg_c3_bitfields
+    {
+        uint8_t SCTRIM : 8;            //!< [7:0] Slow Internal Reference Clock Trim
+                                       //! Setting
+    } B;
+} hw_mcg_c3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+//@{
+#define HW_MCG_C3_ADDR           (REGS_MCG_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C3                (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR)
+#define HW_MCG_C3_RD()           (HW_MCG_C3.U)
+#define HW_MCG_C3_WR(v)          (HW_MCG_C3.U = (v))
+#define HW_MCG_C3_SET(v)         (HW_MCG_C3_WR(HW_MCG_C3_RD() |  (v)))
+#define HW_MCG_C3_CLR(v)         (HW_MCG_C3_WR(HW_MCG_C3_RD() & ~(v)))
+#define HW_MCG_C3_TOG(v)         (HW_MCG_C3_WR(HW_MCG_C3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C3 bitfields
+ */
+
+/*!
+ * @name Register MCG_C3, field SCTRIM[7:0] (RW)
+ *
+ * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
+ * location. controls the slow internal reference clock frequency by controlling
+ * the slow internal reference clock period. The SCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. An additional
+ * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
+ * this value is loaded with a factory trim value. If an SCTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this register.
+ */
+//@{
+#define BP_MCG_C3_SCTRIM     (0U)          //!< Bit position for MCG_C3_SCTRIM.
+#define BM_MCG_C3_SCTRIM     (0xFFU)       //!< Bit mask for MCG_C3_SCTRIM.
+#define BS_MCG_C3_SCTRIM     (8U)          //!< Bit field size in bits for MCG_C3_SCTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C3_SCTRIM field.
+#define BR_MCG_C3_SCTRIM     (HW_MCG_C3.U)
+#endif
+
+//! @brief Format value for bitfield MCG_C3_SCTRIM.
+#define BF_MCG_C3_SCTRIM(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C3_SCTRIM), uint8_t) & BM_MCG_C3_SCTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SCTRIM field to a new value.
+#define BW_MCG_C3_SCTRIM(v)  (HW_MCG_C3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C4 - MCG Control 4 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+typedef union _hw_mcg_c4
+{
+    uint8_t U;
+    struct _hw_mcg_c4_bitfields
+    {
+        uint8_t SCFTRIM : 1;           //!< [0] Slow Internal Reference Clock Fine Trim
+        uint8_t FCTRIM : 4;            //!< [4:1] Fast Internal Reference Clock Trim
+                                       //! Setting
+        uint8_t DRST_DRS : 2;          //!< [6:5] DCO Range Select
+        uint8_t DMX32 : 1;             //!< [7] DCO Maximum Frequency with 32.768 kHz
+                                       //! Reference
+    } B;
+} hw_mcg_c4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+//@{
+#define HW_MCG_C4_ADDR           (REGS_MCG_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C4                (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR)
+#define HW_MCG_C4_RD()           (HW_MCG_C4.U)
+#define HW_MCG_C4_WR(v)          (HW_MCG_C4.U = (v))
+#define HW_MCG_C4_SET(v)         (HW_MCG_C4_WR(HW_MCG_C4_RD() |  (v)))
+#define HW_MCG_C4_CLR(v)         (HW_MCG_C4_WR(HW_MCG_C4_RD() & ~(v)))
+#define HW_MCG_C4_TOG(v)         (HW_MCG_C4_WR(HW_MCG_C4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+//@{
+#define BP_MCG_C4_SCFTRIM    (0U)          //!< Bit position for MCG_C4_SCFTRIM.
+#define BM_MCG_C4_SCFTRIM    (0x01U)       //!< Bit mask for MCG_C4_SCFTRIM.
+#define BS_MCG_C4_SCFTRIM    (1U)          //!< Bit field size in bits for MCG_C4_SCFTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_SCFTRIM field.
+#define BR_MCG_C4_SCFTRIM    (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM))
+#endif
+
+//! @brief Format value for bitfield MCG_C4_SCFTRIM.
+#define BF_MCG_C4_SCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_SCFTRIM), uint8_t) & BM_MCG_C4_SCFTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SCFTRIM field to a new value.
+#define BW_MCG_C4_SCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+//@{
+#define BP_MCG_C4_FCTRIM     (1U)          //!< Bit position for MCG_C4_FCTRIM.
+#define BM_MCG_C4_FCTRIM     (0x1EU)       //!< Bit mask for MCG_C4_FCTRIM.
+#define BS_MCG_C4_FCTRIM     (4U)          //!< Bit field size in bits for MCG_C4_FCTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_FCTRIM field.
+#define BR_MCG_C4_FCTRIM     (HW_MCG_C4.B.FCTRIM)
+#endif
+
+//! @brief Format value for bitfield MCG_C4_FCTRIM.
+#define BF_MCG_C4_FCTRIM(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_FCTRIM), uint8_t) & BM_MCG_C4_FCTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCTRIM field to a new value.
+#define BW_MCG_C4_FCTRIM(v)  (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 00 - Encoding 0 - Low range (reset default).
+ * - 01 - Encoding 1 - Mid range.
+ * - 10 - Encoding 2 - Mid-high range.
+ * - 11 - Encoding 3 - High range.
+ */
+//@{
+#define BP_MCG_C4_DRST_DRS   (5U)          //!< Bit position for MCG_C4_DRST_DRS.
+#define BM_MCG_C4_DRST_DRS   (0x60U)       //!< Bit mask for MCG_C4_DRST_DRS.
+#define BS_MCG_C4_DRST_DRS   (2U)          //!< Bit field size in bits for MCG_C4_DRST_DRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_DRST_DRS field.
+#define BR_MCG_C4_DRST_DRS   (HW_MCG_C4.B.DRST_DRS)
+#endif
+
+//! @brief Format value for bitfield MCG_C4_DRST_DRS.
+#define BF_MCG_C4_DRST_DRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DRST_DRS), uint8_t) & BM_MCG_C4_DRST_DRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DRST_DRS field to a new value.
+#define BW_MCG_C4_DRST_DRS(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0 - DCO has a default range of 25%.
+ * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+//@{
+#define BP_MCG_C4_DMX32      (7U)          //!< Bit position for MCG_C4_DMX32.
+#define BM_MCG_C4_DMX32      (0x80U)       //!< Bit mask for MCG_C4_DMX32.
+#define BS_MCG_C4_DMX32      (1U)          //!< Bit field size in bits for MCG_C4_DMX32.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_DMX32 field.
+#define BR_MCG_C4_DMX32      (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32))
+#endif
+
+//! @brief Format value for bitfield MCG_C4_DMX32.
+#define BF_MCG_C4_DMX32(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DMX32), uint8_t) & BM_MCG_C4_DMX32)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMX32 field to a new value.
+#define BW_MCG_C4_DMX32(v)   (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C5 - MCG Control 5 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c5
+{
+    uint8_t U;
+    struct _hw_mcg_c5_bitfields
+    {
+        uint8_t PRDIV0 : 5;            //!< [4:0] PLL External Reference Divider
+        uint8_t PLLSTEN0 : 1;          //!< [5] PLL Stop Enable
+        uint8_t PLLCLKEN0 : 1;         //!< [6] PLL Clock Enable
+        uint8_t RESERVED0 : 1;         //!< [7]
+    } B;
+} hw_mcg_c5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+//@{
+#define HW_MCG_C5_ADDR           (REGS_MCG_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C5                (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR)
+#define HW_MCG_C5_RD()           (HW_MCG_C5.U)
+#define HW_MCG_C5_WR(v)          (HW_MCG_C5.U = (v))
+#define HW_MCG_C5_SET(v)         (HW_MCG_C5_WR(HW_MCG_C5_RD() |  (v)))
+#define HW_MCG_C5_CLR(v)         (HW_MCG_C5_WR(HW_MCG_C5_RD() & ~(v)))
+#define HW_MCG_C5_TOG(v)         (HW_MCG_C5_WR(HW_MCG_C5_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+//@{
+#define BP_MCG_C5_PRDIV0     (0U)          //!< Bit position for MCG_C5_PRDIV0.
+#define BM_MCG_C5_PRDIV0     (0x1FU)       //!< Bit mask for MCG_C5_PRDIV0.
+#define BS_MCG_C5_PRDIV0     (5U)          //!< Bit field size in bits for MCG_C5_PRDIV0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C5_PRDIV0 field.
+#define BR_MCG_C5_PRDIV0     (HW_MCG_C5.B.PRDIV0)
+#endif
+
+//! @brief Format value for bitfield MCG_C5_PRDIV0.
+#define BF_MCG_C5_PRDIV0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PRDIV0), uint8_t) & BM_MCG_C5_PRDIV0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRDIV0 field to a new value.
+#define BW_MCG_C5_PRDIV0(v)  (HW_MCG_C5_WR((HW_MCG_C5_RD() & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+//@{
+#define BP_MCG_C5_PLLSTEN0   (5U)          //!< Bit position for MCG_C5_PLLSTEN0.
+#define BM_MCG_C5_PLLSTEN0   (0x20U)       //!< Bit mask for MCG_C5_PLLSTEN0.
+#define BS_MCG_C5_PLLSTEN0   (1U)          //!< Bit field size in bits for MCG_C5_PLLSTEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C5_PLLSTEN0 field.
+#define BR_MCG_C5_PLLSTEN0   (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0))
+#endif
+
+//! @brief Format value for bitfield MCG_C5_PLLSTEN0.
+#define BF_MCG_C5_PLLSTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLSTEN0), uint8_t) & BM_MCG_C5_PLLSTEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLSTEN0 field to a new value.
+#define BW_MCG_C5_PLLSTEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0 - MCGPLLCLK is inactive.
+ * - 1 - MCGPLLCLK is active.
+ */
+//@{
+#define BP_MCG_C5_PLLCLKEN0  (6U)          //!< Bit position for MCG_C5_PLLCLKEN0.
+#define BM_MCG_C5_PLLCLKEN0  (0x40U)       //!< Bit mask for MCG_C5_PLLCLKEN0.
+#define BS_MCG_C5_PLLCLKEN0  (1U)          //!< Bit field size in bits for MCG_C5_PLLCLKEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C5_PLLCLKEN0 field.
+#define BR_MCG_C5_PLLCLKEN0  (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0))
+#endif
+
+//! @brief Format value for bitfield MCG_C5_PLLCLKEN0.
+#define BF_MCG_C5_PLLCLKEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLCLKEN0), uint8_t) & BM_MCG_C5_PLLCLKEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLCLKEN0 field to a new value.
+#define BW_MCG_C5_PLLCLKEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C6 - MCG Control 6 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c6
+{
+    uint8_t U;
+    struct _hw_mcg_c6_bitfields
+    {
+        uint8_t VDIV0 : 5;             //!< [4:0] VCO 0 Divider
+        uint8_t CME0 : 1;              //!< [5] Clock Monitor Enable
+        uint8_t PLLS : 1;              //!< [6] PLL Select
+        uint8_t LOLIE0 : 1;            //!< [7] Loss of Lock Interrrupt Enable
+    } B;
+} hw_mcg_c6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+//@{
+#define HW_MCG_C6_ADDR           (REGS_MCG_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C6                (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR)
+#define HW_MCG_C6_RD()           (HW_MCG_C6.U)
+#define HW_MCG_C6_WR(v)          (HW_MCG_C6.U = (v))
+#define HW_MCG_C6_SET(v)         (HW_MCG_C6_WR(HW_MCG_C6_RD() |  (v)))
+#define HW_MCG_C6_CLR(v)         (HW_MCG_C6_WR(HW_MCG_C6_RD() & ~(v)))
+#define HW_MCG_C6_TOG(v)         (HW_MCG_C6_WR(HW_MCG_C6_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+//@{
+#define BP_MCG_C6_VDIV0      (0U)          //!< Bit position for MCG_C6_VDIV0.
+#define BM_MCG_C6_VDIV0      (0x1FU)       //!< Bit mask for MCG_C6_VDIV0.
+#define BS_MCG_C6_VDIV0      (5U)          //!< Bit field size in bits for MCG_C6_VDIV0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_VDIV0 field.
+#define BR_MCG_C6_VDIV0      (HW_MCG_C6.B.VDIV0)
+#endif
+
+//! @brief Format value for bitfield MCG_C6_VDIV0.
+#define BF_MCG_C6_VDIV0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_VDIV0), uint8_t) & BM_MCG_C6_VDIV0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VDIV0 field to a new value.
+#define BW_MCG_C6_VDIV0(v)   (HW_MCG_C6_WR((HW_MCG_C6_RD() & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0 - External clock monitor is disabled for OSC0.
+ * - 1 - External clock monitor is enabled for OSC0.
+ */
+//@{
+#define BP_MCG_C6_CME0       (5U)          //!< Bit position for MCG_C6_CME0.
+#define BM_MCG_C6_CME0       (0x20U)       //!< Bit mask for MCG_C6_CME0.
+#define BS_MCG_C6_CME0       (1U)          //!< Bit field size in bits for MCG_C6_CME0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_CME0 field.
+#define BR_MCG_C6_CME0       (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0))
+#endif
+
+//! @brief Format value for bitfield MCG_C6_CME0.
+#define BF_MCG_C6_CME0(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_CME0), uint8_t) & BM_MCG_C6_CME0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CME0 field to a new value.
+#define BW_MCG_C6_CME0(v)    (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0 - FLL is selected.
+ * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to setting
+ *     the PLLS bit).
+ */
+//@{
+#define BP_MCG_C6_PLLS       (6U)          //!< Bit position for MCG_C6_PLLS.
+#define BM_MCG_C6_PLLS       (0x40U)       //!< Bit mask for MCG_C6_PLLS.
+#define BS_MCG_C6_PLLS       (1U)          //!< Bit field size in bits for MCG_C6_PLLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_PLLS field.
+#define BR_MCG_C6_PLLS       (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS))
+#endif
+
+//! @brief Format value for bitfield MCG_C6_PLLS.
+#define BF_MCG_C6_PLLS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_PLLS), uint8_t) & BM_MCG_C6_PLLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLS field to a new value.
+#define BW_MCG_C6_PLLS(v)    (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0 - No interrupt request is generated on loss of lock.
+ * - 1 - Generate an interrupt request on loss of lock.
+ */
+//@{
+#define BP_MCG_C6_LOLIE0     (7U)          //!< Bit position for MCG_C6_LOLIE0.
+#define BM_MCG_C6_LOLIE0     (0x80U)       //!< Bit mask for MCG_C6_LOLIE0.
+#define BS_MCG_C6_LOLIE0     (1U)          //!< Bit field size in bits for MCG_C6_LOLIE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_LOLIE0 field.
+#define BR_MCG_C6_LOLIE0     (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0))
+#endif
+
+//! @brief Format value for bitfield MCG_C6_LOLIE0.
+#define BF_MCG_C6_LOLIE0(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_LOLIE0), uint8_t) & BM_MCG_C6_LOLIE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOLIE0 field to a new value.
+#define BW_MCG_C6_LOLIE0(v)  (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_S - MCG Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+typedef union _hw_mcg_s
+{
+    uint8_t U;
+    struct _hw_mcg_s_bitfields
+    {
+        uint8_t IRCST : 1;             //!< [0] Internal Reference Clock Status
+        uint8_t OSCINIT0 : 1;          //!< [1] OSC Initialization
+        uint8_t CLKST : 2;             //!< [3:2] Clock Mode Status
+        uint8_t IREFST : 1;            //!< [4] Internal Reference Status
+        uint8_t PLLST : 1;             //!< [5] PLL Select Status
+        uint8_t LOCK0 : 1;             //!< [6] Lock Status
+        uint8_t LOLS0 : 1;             //!< [7] Loss of Lock Status
+    } B;
+} hw_mcg_s_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+//@{
+#define HW_MCG_S_ADDR            (REGS_MCG_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_S                 (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR)
+#define HW_MCG_S_RD()            (HW_MCG_S.U)
+#define HW_MCG_S_WR(v)           (HW_MCG_S.U = (v))
+#define HW_MCG_S_SET(v)          (HW_MCG_S_WR(HW_MCG_S_RD() |  (v)))
+#define HW_MCG_S_CLR(v)          (HW_MCG_S_WR(HW_MCG_S_RD() & ~(v)))
+#define HW_MCG_S_TOG(v)          (HW_MCG_S_WR(HW_MCG_S_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+//@{
+#define BP_MCG_S_IRCST       (0U)          //!< Bit position for MCG_S_IRCST.
+#define BM_MCG_S_IRCST       (0x01U)       //!< Bit mask for MCG_S_IRCST.
+#define BS_MCG_S_IRCST       (1U)          //!< Bit field size in bits for MCG_S_IRCST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_IRCST field.
+#define BR_MCG_S_IRCST       (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IRCST))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+//@{
+#define BP_MCG_S_OSCINIT0    (1U)          //!< Bit position for MCG_S_OSCINIT0.
+#define BM_MCG_S_OSCINIT0    (0x02U)       //!< Bit mask for MCG_S_OSCINIT0.
+#define BS_MCG_S_OSCINIT0    (1U)          //!< Bit field size in bits for MCG_S_OSCINIT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_OSCINIT0 field.
+#define BR_MCG_S_OSCINIT0    (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_OSCINIT0))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 01 - Encoding 1 - Internal reference clock is selected.
+ * - 10 - Encoding 2 - External reference clock is selected.
+ * - 11 - Encoding 3 - Output of the PLL is selected.
+ */
+//@{
+#define BP_MCG_S_CLKST       (2U)          //!< Bit position for MCG_S_CLKST.
+#define BM_MCG_S_CLKST       (0x0CU)       //!< Bit mask for MCG_S_CLKST.
+#define BS_MCG_S_CLKST       (2U)          //!< Bit field size in bits for MCG_S_CLKST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_CLKST field.
+#define BR_MCG_S_CLKST       (HW_MCG_S.B.CLKST)
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0 - Source of FLL reference clock is the external reference clock.
+ * - 1 - Source of FLL reference clock is the internal reference clock.
+ */
+//@{
+#define BP_MCG_S_IREFST      (4U)          //!< Bit position for MCG_S_IREFST.
+#define BM_MCG_S_IREFST      (0x10U)       //!< Bit mask for MCG_S_IREFST.
+#define BS_MCG_S_IREFST      (1U)          //!< Bit field size in bits for MCG_S_IREFST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_IREFST field.
+#define BR_MCG_S_IREFST      (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IREFST))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0 - Source of PLLS clock is FLL clock.
+ * - 1 - Source of PLLS clock is PLL output clock.
+ */
+//@{
+#define BP_MCG_S_PLLST       (5U)          //!< Bit position for MCG_S_PLLST.
+#define BM_MCG_S_PLLST       (0x20U)       //!< Bit mask for MCG_S_PLLST.
+#define BS_MCG_S_PLLST       (1U)          //!< Bit field size in bits for MCG_S_PLLST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_PLLST field.
+#define BR_MCG_S_PLLST       (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_PLLST))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0 - PLL is currently unlocked.
+ * - 1 - PLL is currently locked.
+ */
+//@{
+#define BP_MCG_S_LOCK0       (6U)          //!< Bit position for MCG_S_LOCK0.
+#define BM_MCG_S_LOCK0       (0x40U)       //!< Bit mask for MCG_S_LOCK0.
+#define BS_MCG_S_LOCK0       (1U)          //!< Bit field size in bits for MCG_S_LOCK0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_LOCK0 field.
+#define BR_MCG_S_LOCK0       (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOCK0))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+//@{
+#define BP_MCG_S_LOLS0       (7U)          //!< Bit position for MCG_S_LOLS0.
+#define BM_MCG_S_LOLS0       (0x80U)       //!< Bit mask for MCG_S_LOLS0.
+#define BS_MCG_S_LOLS0       (1U)          //!< Bit field size in bits for MCG_S_LOLS0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_LOLS0 field.
+#define BR_MCG_S_LOLS0       (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0))
+#endif
+
+//! @brief Format value for bitfield MCG_S_LOLS0.
+#define BF_MCG_S_LOLS0(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_S_LOLS0), uint8_t) & BM_MCG_S_LOLS0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOLS0 field to a new value.
+#define BW_MCG_S_LOLS0(v)    (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_SC - MCG Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+typedef union _hw_mcg_sc
+{
+    uint8_t U;
+    struct _hw_mcg_sc_bitfields
+    {
+        uint8_t LOCS0 : 1;             //!< [0] OSC0 Loss of Clock Status
+        uint8_t FCRDIV : 3;            //!< [3:1] Fast Clock Internal Reference Divider
+        uint8_t FLTPRSRV : 1;          //!< [4] FLL Filter Preserve Enable
+        uint8_t ATMF : 1;              //!< [5] Automatic Trim Machine Fail Flag
+        uint8_t ATMS : 1;              //!< [6] Automatic Trim Machine Select
+        uint8_t ATME : 1;              //!< [7] Automatic Trim Machine Enable
+    } B;
+} hw_mcg_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+//@{
+#define HW_MCG_SC_ADDR           (REGS_MCG_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_SC                (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR)
+#define HW_MCG_SC_RD()           (HW_MCG_SC.U)
+#define HW_MCG_SC_WR(v)          (HW_MCG_SC.U = (v))
+#define HW_MCG_SC_SET(v)         (HW_MCG_SC_WR(HW_MCG_SC_RD() |  (v)))
+#define HW_MCG_SC_CLR(v)         (HW_MCG_SC_WR(HW_MCG_SC_RD() & ~(v)))
+#define HW_MCG_SC_TOG(v)         (HW_MCG_SC_WR(HW_MCG_SC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0 - Loss of OSC0 has not occurred.
+ * - 1 - Loss of OSC0 has occurred.
+ */
+//@{
+#define BP_MCG_SC_LOCS0      (0U)          //!< Bit position for MCG_SC_LOCS0.
+#define BM_MCG_SC_LOCS0      (0x01U)       //!< Bit mask for MCG_SC_LOCS0.
+#define BS_MCG_SC_LOCS0      (1U)          //!< Bit field size in bits for MCG_SC_LOCS0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_LOCS0 field.
+#define BR_MCG_SC_LOCS0      (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_LOCS0.
+#define BF_MCG_SC_LOCS0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_LOCS0), uint8_t) & BM_MCG_SC_LOCS0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCS0 field to a new value.
+#define BW_MCG_SC_LOCS0(v)   (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 000 - Divide Factor is 1
+ * - 001 - Divide Factor is 2.
+ * - 010 - Divide Factor is 4.
+ * - 011 - Divide Factor is 8.
+ * - 100 - Divide Factor is 16
+ * - 101 - Divide Factor is 32
+ * - 110 - Divide Factor is 64
+ * - 111 - Divide Factor is 128.
+ */
+//@{
+#define BP_MCG_SC_FCRDIV     (1U)          //!< Bit position for MCG_SC_FCRDIV.
+#define BM_MCG_SC_FCRDIV     (0x0EU)       //!< Bit mask for MCG_SC_FCRDIV.
+#define BS_MCG_SC_FCRDIV     (3U)          //!< Bit field size in bits for MCG_SC_FCRDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_FCRDIV field.
+#define BR_MCG_SC_FCRDIV     (HW_MCG_SC.B.FCRDIV)
+#endif
+
+//! @brief Format value for bitfield MCG_SC_FCRDIV.
+#define BF_MCG_SC_FCRDIV(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FCRDIV), uint8_t) & BM_MCG_SC_FCRDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCRDIV field to a new value.
+#define BW_MCG_SC_FCRDIV(v)  (HW_MCG_SC_WR((HW_MCG_SC_RD() & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+//@{
+#define BP_MCG_SC_FLTPRSRV   (4U)          //!< Bit position for MCG_SC_FLTPRSRV.
+#define BM_MCG_SC_FLTPRSRV   (0x10U)       //!< Bit mask for MCG_SC_FLTPRSRV.
+#define BS_MCG_SC_FLTPRSRV   (1U)          //!< Bit field size in bits for MCG_SC_FLTPRSRV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_FLTPRSRV field.
+#define BR_MCG_SC_FLTPRSRV   (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_FLTPRSRV.
+#define BF_MCG_SC_FLTPRSRV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FLTPRSRV), uint8_t) & BM_MCG_SC_FLTPRSRV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLTPRSRV field to a new value.
+#define BW_MCG_SC_FLTPRSRV(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0 - Automatic Trim Machine completed normally.
+ * - 1 - Automatic Trim Machine failed.
+ */
+//@{
+#define BP_MCG_SC_ATMF       (5U)          //!< Bit position for MCG_SC_ATMF.
+#define BM_MCG_SC_ATMF       (0x20U)       //!< Bit mask for MCG_SC_ATMF.
+#define BS_MCG_SC_ATMF       (1U)          //!< Bit field size in bits for MCG_SC_ATMF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_ATMF field.
+#define BR_MCG_SC_ATMF       (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_ATMF.
+#define BF_MCG_SC_ATMF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMF), uint8_t) & BM_MCG_SC_ATMF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATMF field to a new value.
+#define BW_MCG_SC_ATMF(v)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0 - 32 kHz Internal Reference Clock selected.
+ * - 1 - 4 MHz Internal Reference Clock selected.
+ */
+//@{
+#define BP_MCG_SC_ATMS       (6U)          //!< Bit position for MCG_SC_ATMS.
+#define BM_MCG_SC_ATMS       (0x40U)       //!< Bit mask for MCG_SC_ATMS.
+#define BS_MCG_SC_ATMS       (1U)          //!< Bit field size in bits for MCG_SC_ATMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_ATMS field.
+#define BR_MCG_SC_ATMS       (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_ATMS.
+#define BF_MCG_SC_ATMS(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMS), uint8_t) & BM_MCG_SC_ATMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATMS field to a new value.
+#define BW_MCG_SC_ATMS(v)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0 - Auto Trim Machine disabled.
+ * - 1 - Auto Trim Machine enabled.
+ */
+//@{
+#define BP_MCG_SC_ATME       (7U)          //!< Bit position for MCG_SC_ATME.
+#define BM_MCG_SC_ATME       (0x80U)       //!< Bit mask for MCG_SC_ATME.
+#define BS_MCG_SC_ATME       (1U)          //!< Bit field size in bits for MCG_SC_ATME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_ATME field.
+#define BR_MCG_SC_ATME       (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_ATME.
+#define BF_MCG_SC_ATME(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATME), uint8_t) & BM_MCG_SC_ATME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATME field to a new value.
+#define BW_MCG_SC_ATME(v)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_atcvh
+{
+    uint8_t U;
+    struct _hw_mcg_atcvh_bitfields
+    {
+        uint8_t ATCVH : 8;             //!< [7:0] ATM Compare Value High
+    } B;
+} hw_mcg_atcvh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+//@{
+#define HW_MCG_ATCVH_ADDR        (REGS_MCG_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_ATCVH             (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR)
+#define HW_MCG_ATCVH_RD()        (HW_MCG_ATCVH.U)
+#define HW_MCG_ATCVH_WR(v)       (HW_MCG_ATCVH.U = (v))
+#define HW_MCG_ATCVH_SET(v)      (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() |  (v)))
+#define HW_MCG_ATCVH_CLR(v)      (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() & ~(v)))
+#define HW_MCG_ATCVH_TOG(v)      (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_ATCVH bitfields
+ */
+
+/*!
+ * @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
+ *
+ * Values are used by Auto Trim Machine to compare and adjust Internal Reference
+ * trim values during ATM SAR conversion.
+ */
+//@{
+#define BP_MCG_ATCVH_ATCVH   (0U)          //!< Bit position for MCG_ATCVH_ATCVH.
+#define BM_MCG_ATCVH_ATCVH   (0xFFU)       //!< Bit mask for MCG_ATCVH_ATCVH.
+#define BS_MCG_ATCVH_ATCVH   (8U)          //!< Bit field size in bits for MCG_ATCVH_ATCVH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_ATCVH_ATCVH field.
+#define BR_MCG_ATCVH_ATCVH   (HW_MCG_ATCVH.U)
+#endif
+
+//! @brief Format value for bitfield MCG_ATCVH_ATCVH.
+#define BF_MCG_ATCVH_ATCVH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVH_ATCVH), uint8_t) & BM_MCG_ATCVH_ATCVH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATCVH field to a new value.
+#define BW_MCG_ATCVH_ATCVH(v) (HW_MCG_ATCVH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_atcvl
+{
+    uint8_t U;
+    struct _hw_mcg_atcvl_bitfields
+    {
+        uint8_t ATCVL : 8;             //!< [7:0] ATM Compare Value Low
+    } B;
+} hw_mcg_atcvl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+//@{
+#define HW_MCG_ATCVL_ADDR        (REGS_MCG_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_ATCVL             (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR)
+#define HW_MCG_ATCVL_RD()        (HW_MCG_ATCVL.U)
+#define HW_MCG_ATCVL_WR(v)       (HW_MCG_ATCVL.U = (v))
+#define HW_MCG_ATCVL_SET(v)      (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() |  (v)))
+#define HW_MCG_ATCVL_CLR(v)      (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() & ~(v)))
+#define HW_MCG_ATCVL_TOG(v)      (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_ATCVL bitfields
+ */
+
+/*!
+ * @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
+ *
+ * Values are used by Auto Trim Machine to compare and adjust Internal Reference
+ * trim values during ATM SAR conversion.
+ */
+//@{
+#define BP_MCG_ATCVL_ATCVL   (0U)          //!< Bit position for MCG_ATCVL_ATCVL.
+#define BM_MCG_ATCVL_ATCVL   (0xFFU)       //!< Bit mask for MCG_ATCVL_ATCVL.
+#define BS_MCG_ATCVL_ATCVL   (8U)          //!< Bit field size in bits for MCG_ATCVL_ATCVL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_ATCVL_ATCVL field.
+#define BR_MCG_ATCVL_ATCVL   (HW_MCG_ATCVL.U)
+#endif
+
+//! @brief Format value for bitfield MCG_ATCVL_ATCVL.
+#define BF_MCG_ATCVL_ATCVL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVL_ATCVL), uint8_t) & BM_MCG_ATCVL_ATCVL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATCVL field to a new value.
+#define BW_MCG_ATCVL_ATCVL(v) (HW_MCG_ATCVL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C7 - MCG Control 7 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c7
+{
+    uint8_t U;
+    struct _hw_mcg_c7_bitfields
+    {
+        uint8_t OSCSEL : 2;            //!< [1:0] MCG OSC Clock Select
+        uint8_t RESERVED0 : 6;         //!< [7:2]
+    } B;
+} hw_mcg_c7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+//@{
+#define HW_MCG_C7_ADDR           (REGS_MCG_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C7                (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR)
+#define HW_MCG_C7_RD()           (HW_MCG_C7.U)
+#define HW_MCG_C7_WR(v)          (HW_MCG_C7.U = (v))
+#define HW_MCG_C7_SET(v)         (HW_MCG_C7_WR(HW_MCG_C7_RD() |  (v)))
+#define HW_MCG_C7_CLR(v)         (HW_MCG_C7_WR(HW_MCG_C7_RD() & ~(v)))
+#define HW_MCG_C7_TOG(v)         (HW_MCG_C7_WR(HW_MCG_C7_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 00 - Selects Oscillator (OSCCLK0).
+ * - 01 - Selects 32 kHz RTC Oscillator.
+ * - 10 - Selects Oscillator (OSCCLK1).
+ * - 11 - RESERVED
+ */
+//@{
+#define BP_MCG_C7_OSCSEL     (0U)          //!< Bit position for MCG_C7_OSCSEL.
+#define BM_MCG_C7_OSCSEL     (0x03U)       //!< Bit mask for MCG_C7_OSCSEL.
+#define BS_MCG_C7_OSCSEL     (2U)          //!< Bit field size in bits for MCG_C7_OSCSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C7_OSCSEL field.
+#define BR_MCG_C7_OSCSEL     (HW_MCG_C7.B.OSCSEL)
+#endif
+
+//! @brief Format value for bitfield MCG_C7_OSCSEL.
+#define BF_MCG_C7_OSCSEL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C7_OSCSEL), uint8_t) & BM_MCG_C7_OSCSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OSCSEL field to a new value.
+#define BW_MCG_C7_OSCSEL(v)  (HW_MCG_C7_WR((HW_MCG_C7_RD() & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C8 - MCG Control 8 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+typedef union _hw_mcg_c8
+{
+    uint8_t U;
+    struct _hw_mcg_c8_bitfields
+    {
+        uint8_t LOCS1 : 1;             //!< [0] RTC Loss of Clock Status
+        uint8_t RESERVED0 : 4;         //!< [4:1]
+        uint8_t CME1 : 1;              //!< [5] Clock Monitor Enable1
+        uint8_t LOLRE : 1;             //!< [6] PLL Loss of Lock Reset Enable
+        uint8_t LOCRE1 : 1;            //!< [7] Loss of Clock Reset Enable
+    } B;
+} hw_mcg_c8_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+//@{
+#define HW_MCG_C8_ADDR           (REGS_MCG_BASE + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C8                (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR)
+#define HW_MCG_C8_RD()           (HW_MCG_C8.U)
+#define HW_MCG_C8_WR(v)          (HW_MCG_C8.U = (v))
+#define HW_MCG_C8_SET(v)         (HW_MCG_C8_WR(HW_MCG_C8_RD() |  (v)))
+#define HW_MCG_C8_CLR(v)         (HW_MCG_C8_WR(HW_MCG_C8_RD() & ~(v)))
+#define HW_MCG_C8_TOG(v)         (HW_MCG_C8_WR(HW_MCG_C8_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0 - Loss of RTC has not occur.
+ * - 1 - Loss of RTC has occur
+ */
+//@{
+#define BP_MCG_C8_LOCS1      (0U)          //!< Bit position for MCG_C8_LOCS1.
+#define BM_MCG_C8_LOCS1      (0x01U)       //!< Bit mask for MCG_C8_LOCS1.
+#define BS_MCG_C8_LOCS1      (1U)          //!< Bit field size in bits for MCG_C8_LOCS1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_LOCS1 field.
+#define BR_MCG_C8_LOCS1      (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_LOCS1.
+#define BF_MCG_C8_LOCS1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCS1), uint8_t) & BM_MCG_C8_LOCS1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCS1 field to a new value.
+#define BW_MCG_C8_LOCS1(v)   (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0 - External clock monitor is disabled for RTC clock.
+ * - 1 - External clock monitor is enabled for RTC clock.
+ */
+//@{
+#define BP_MCG_C8_CME1       (5U)          //!< Bit position for MCG_C8_CME1.
+#define BM_MCG_C8_CME1       (0x20U)       //!< Bit mask for MCG_C8_CME1.
+#define BS_MCG_C8_CME1       (1U)          //!< Bit field size in bits for MCG_C8_CME1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_CME1 field.
+#define BR_MCG_C8_CME1       (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_CME1.
+#define BF_MCG_C8_CME1(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_CME1), uint8_t) & BM_MCG_C8_CME1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CME1 field to a new value.
+#define BW_MCG_C8_CME1(v)    (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 1 - Generate a reset request on a PLL loss of lock indication.
+ */
+//@{
+#define BP_MCG_C8_LOLRE      (6U)          //!< Bit position for MCG_C8_LOLRE.
+#define BM_MCG_C8_LOLRE      (0x40U)       //!< Bit mask for MCG_C8_LOLRE.
+#define BS_MCG_C8_LOLRE      (1U)          //!< Bit field size in bits for MCG_C8_LOLRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_LOLRE field.
+#define BR_MCG_C8_LOLRE      (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_LOLRE.
+#define BF_MCG_C8_LOLRE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOLRE), uint8_t) & BM_MCG_C8_LOLRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOLRE field to a new value.
+#define BW_MCG_C8_LOLRE(v)   (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 1 - Generate a reset request on a loss of RTC external reference clock
+ */
+//@{
+#define BP_MCG_C8_LOCRE1     (7U)          //!< Bit position for MCG_C8_LOCRE1.
+#define BM_MCG_C8_LOCRE1     (0x80U)       //!< Bit mask for MCG_C8_LOCRE1.
+#define BS_MCG_C8_LOCRE1     (1U)          //!< Bit field size in bits for MCG_C8_LOCRE1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_LOCRE1 field.
+#define BR_MCG_C8_LOCRE1     (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_LOCRE1.
+#define BF_MCG_C8_LOCRE1(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCRE1), uint8_t) & BM_MCG_C8_LOCRE1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCRE1 field to a new value.
+#define BW_MCG_C8_LOCRE1(v)  (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_mcg_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All MCG module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_mcg
+{
+    __IO hw_mcg_c1_t C1;                   //!< [0x0] MCG Control 1 Register
+    __IO hw_mcg_c2_t C2;                   //!< [0x1] MCG Control 2 Register
+    __IO hw_mcg_c3_t C3;                   //!< [0x2] MCG Control 3 Register
+    __IO hw_mcg_c4_t C4;                   //!< [0x3] MCG Control 4 Register
+    __IO hw_mcg_c5_t C5;                   //!< [0x4] MCG Control 5 Register
+    __IO hw_mcg_c6_t C6;                   //!< [0x5] MCG Control 6 Register
+    __IO hw_mcg_s_t S;                     //!< [0x6] MCG Status Register
+    uint8_t _reserved0[1];
+    __IO hw_mcg_sc_t SC;                   //!< [0x8] MCG Status and Control Register
+    uint8_t _reserved1[1];
+    __IO hw_mcg_atcvh_t ATCVH;             //!< [0xA] MCG Auto Trim Compare Value High Register
+    __IO hw_mcg_atcvl_t ATCVL;             //!< [0xB] MCG Auto Trim Compare Value Low Register
+    __IO hw_mcg_c7_t C7;                   //!< [0xC] MCG Control 7 Register
+    __IO hw_mcg_c8_t C8;                   //!< [0xD] MCG Control 8 Register
+} hw_mcg_t;
+#pragma pack()
+
+//! @brief Macro to access all MCG registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_MCG</code>.
+#define HW_MCG         (*(hw_mcg_t *) REGS_MCG_BASE)
+#endif
+
+#endif // __HW_MCG_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h
new file mode 100644
index 0000000000..e494978a81
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h
@@ -0,0 +1,1164 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_MCM_REGISTERS_H__
+#define __HW_MCM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - HW_MCM_CR - Control Register
+ * - HW_MCM_ISR - Interrupt Status Register
+ * - HW_MCM_ETBCC - ETB Counter Control register
+ * - HW_MCM_ETBRL - ETB Reload register
+ * - HW_MCM_ETBCNT - ETB Counter Value register
+ * - HW_MCM_PID - Process ID register
+ *
+ * - hw_mcm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_MCM_BASE
+#define HW_MCM_INSTANCE_COUNT (1U) //!< Number of instances of the MCM module.
+#define REGS_MCM_BASE (0xE0080000U) //!< Base address for MCM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+typedef union _hw_mcm_plasc
+{
+    uint16_t U;
+    struct _hw_mcm_plasc_bitfields
+    {
+        uint16_t ASC : 8;              //!< [7:0] Each bit in the ASC field indicates
+                                       //! whether there is a corresponding connection to the crossbar switch's slave
+                                       //! input port.
+        uint16_t RESERVED0 : 8;        //!< [15:8]
+    } B;
+} hw_mcm_plasc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+//@{
+#define HW_MCM_PLASC_ADDR        (REGS_MCM_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_PLASC             (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR)
+#define HW_MCM_PLASC_RD()        (HW_MCM_PLASC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0 - A bus slave connection to AXBS input port n is absent
+ * - 1 - A bus slave connection to AXBS input port n is present
+ */
+//@{
+#define BP_MCM_PLASC_ASC     (0U)          //!< Bit position for MCM_PLASC_ASC.
+#define BM_MCM_PLASC_ASC     (0x00FFU)     //!< Bit mask for MCM_PLASC_ASC.
+#define BS_MCM_PLASC_ASC     (8U)          //!< Bit field size in bits for MCM_PLASC_ASC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_PLASC_ASC field.
+#define BR_MCM_PLASC_ASC     (HW_MCM_PLASC.B.ASC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+typedef union _hw_mcm_plamc
+{
+    uint16_t U;
+    struct _hw_mcm_plamc_bitfields
+    {
+        uint16_t AMC : 8;              //!< [7:0] Each bit in the AMC field indicates
+                                       //! whether there is a corresponding connection to the AXBS master input port.
+        uint16_t RESERVED0 : 8;        //!< [15:8]
+    } B;
+} hw_mcm_plamc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+//@{
+#define HW_MCM_PLAMC_ADDR        (REGS_MCM_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_PLAMC             (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR)
+#define HW_MCM_PLAMC_RD()        (HW_MCM_PLAMC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0 - A bus master connection to AXBS input port n is absent
+ * - 1 - A bus master connection to AXBS input port n is present
+ */
+//@{
+#define BP_MCM_PLAMC_AMC     (0U)          //!< Bit position for MCM_PLAMC_AMC.
+#define BM_MCM_PLAMC_AMC     (0x00FFU)     //!< Bit mask for MCM_PLAMC_AMC.
+#define BS_MCM_PLAMC_AMC     (8U)          //!< Bit field size in bits for MCM_PLAMC_AMC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_PLAMC_AMC field.
+#define BR_MCM_PLAMC_AMC     (HW_MCM_PLAMC.B.AMC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_CR - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+typedef union _hw_mcm_cr
+{
+    uint32_t U;
+    struct _hw_mcm_cr_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t SRAMUAP : 2;          //!< [25:24] SRAM_U arbitration priority
+        uint32_t SRAMUWP : 1;          //!< [26] SRAM_U write protect
+        uint32_t RESERVED1 : 1;        //!< [27]
+        uint32_t SRAMLAP : 2;          //!< [29:28] SRAM_L arbitration priority
+        uint32_t SRAMLWP : 1;          //!< [30] SRAM_L Write Protect
+        uint32_t RESERVED2 : 1;        //!< [31]
+    } B;
+} hw_mcm_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+//@{
+#define HW_MCM_CR_ADDR           (REGS_MCM_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_CR                (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR)
+#define HW_MCM_CR_RD()           (HW_MCM_CR.U)
+#define HW_MCM_CR_WR(v)          (HW_MCM_CR.U = (v))
+#define HW_MCM_CR_SET(v)         (HW_MCM_CR_WR(HW_MCM_CR_RD() |  (v)))
+#define HW_MCM_CR_CLR(v)         (HW_MCM_CR_WR(HW_MCM_CR_RD() & ~(v)))
+#define HW_MCM_CR_TOG(v)         (HW_MCM_CR_WR(HW_MCM_CR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 00 - Round robin
+ * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+//@{
+#define BP_MCM_CR_SRAMUAP    (24U)         //!< Bit position for MCM_CR_SRAMUAP.
+#define BM_MCM_CR_SRAMUAP    (0x03000000U) //!< Bit mask for MCM_CR_SRAMUAP.
+#define BS_MCM_CR_SRAMUAP    (2U)          //!< Bit field size in bits for MCM_CR_SRAMUAP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMUAP field.
+#define BR_MCM_CR_SRAMUAP    (HW_MCM_CR.B.SRAMUAP)
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMUAP.
+#define BF_MCM_CR_SRAMUAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUAP), uint32_t) & BM_MCM_CR_SRAMUAP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMUAP field to a new value.
+#define BW_MCM_CR_SRAMUAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+//@{
+#define BP_MCM_CR_SRAMUWP    (26U)         //!< Bit position for MCM_CR_SRAMUWP.
+#define BM_MCM_CR_SRAMUWP    (0x04000000U) //!< Bit mask for MCM_CR_SRAMUWP.
+#define BS_MCM_CR_SRAMUWP    (1U)          //!< Bit field size in bits for MCM_CR_SRAMUWP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMUWP field.
+#define BR_MCM_CR_SRAMUWP    (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP))
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMUWP.
+#define BF_MCM_CR_SRAMUWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUWP), uint32_t) & BM_MCM_CR_SRAMUWP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMUWP field to a new value.
+#define BW_MCM_CR_SRAMUWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 00 - Round robin
+ * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+//@{
+#define BP_MCM_CR_SRAMLAP    (28U)         //!< Bit position for MCM_CR_SRAMLAP.
+#define BM_MCM_CR_SRAMLAP    (0x30000000U) //!< Bit mask for MCM_CR_SRAMLAP.
+#define BS_MCM_CR_SRAMLAP    (2U)          //!< Bit field size in bits for MCM_CR_SRAMLAP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMLAP field.
+#define BR_MCM_CR_SRAMLAP    (HW_MCM_CR.B.SRAMLAP)
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMLAP.
+#define BF_MCM_CR_SRAMLAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLAP), uint32_t) & BM_MCM_CR_SRAMLAP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMLAP field to a new value.
+#define BW_MCM_CR_SRAMLAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+//@{
+#define BP_MCM_CR_SRAMLWP    (30U)         //!< Bit position for MCM_CR_SRAMLWP.
+#define BM_MCM_CR_SRAMLWP    (0x40000000U) //!< Bit mask for MCM_CR_SRAMLWP.
+#define BS_MCM_CR_SRAMLWP    (1U)          //!< Bit field size in bits for MCM_CR_SRAMLWP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMLWP field.
+#define BR_MCM_CR_SRAMLWP    (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP))
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMLWP.
+#define BF_MCM_CR_SRAMLWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLWP), uint32_t) & BM_MCM_CR_SRAMLWP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMLWP field to a new value.
+#define BW_MCM_CR_SRAMLWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ISR - Interrupt Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ISR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_isr
+{
+    uint32_t U;
+    struct _hw_mcm_isr_bitfields
+    {
+        uint32_t RESERVED0 : 1;        //!< [0]
+        uint32_t IRQ : 1;              //!< [1] Normal Interrupt Pending
+        uint32_t NMI : 1;              //!< [2] Non-maskable Interrupt Pending
+        uint32_t DHREQ : 1;            //!< [3] Debug Halt Request Indicator
+        uint32_t RESERVED1 : 4;        //!< [7:4]
+        uint32_t FIOC : 1;             //!< [8] FPU invalid operation interrupt status
+        uint32_t FDZC : 1;             //!< [9] FPU divide-by-zero interrupt status
+        uint32_t FOFC : 1;             //!< [10] FPU overflow interrupt status
+        uint32_t FUFC : 1;             //!< [11] FPU underflow interrupt status
+        uint32_t FIXC : 1;             //!< [12] FPU inexact interrupt status
+        uint32_t RESERVED2 : 2;        //!< [14:13]
+        uint32_t FIDC : 1;             //!< [15] FPU input denormal interrupt status
+        uint32_t RESERVED3 : 8;        //!< [23:16]
+        uint32_t FIOCE : 1;            //!< [24] FPU invalid operation interrupt enable
+        uint32_t FDZCE : 1;            //!< [25] FPU divide-by-zero interrupt enable
+        uint32_t FOFCE : 1;            //!< [26] FPU overflow interrupt enable
+        uint32_t FUFCE : 1;            //!< [27] FPU underflow interrupt enable
+        uint32_t FIXCE : 1;            //!< [28] FPU inexact interrupt enable
+        uint32_t RESERVED4 : 2;        //!< [30:29]
+        uint32_t FIDCE : 1;            //!< [31] FPU input denormal interrupt enable
+    } B;
+} hw_mcm_isr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ISR register
+ */
+//@{
+#define HW_MCM_ISR_ADDR          (REGS_MCM_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ISR               (*(__IO hw_mcm_isr_t *) HW_MCM_ISR_ADDR)
+#define HW_MCM_ISR_RD()          (HW_MCM_ISR.U)
+#define HW_MCM_ISR_WR(v)         (HW_MCM_ISR.U = (v))
+#define HW_MCM_ISR_SET(v)        (HW_MCM_ISR_WR(HW_MCM_ISR_RD() |  (v)))
+#define HW_MCM_ISR_CLR(v)        (HW_MCM_ISR_WR(HW_MCM_ISR_RD() & ~(v)))
+#define HW_MCM_ISR_TOG(v)        (HW_MCM_ISR_WR(HW_MCM_ISR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ISR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0 - No pending interrupt
+ * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+//@{
+#define BP_MCM_ISR_IRQ       (1U)          //!< Bit position for MCM_ISR_IRQ.
+#define BM_MCM_ISR_IRQ       (0x00000002U) //!< Bit mask for MCM_ISR_IRQ.
+#define BS_MCM_ISR_IRQ       (1U)          //!< Bit field size in bits for MCM_ISR_IRQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_IRQ field.
+#define BR_MCM_ISR_IRQ       (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_IRQ.
+#define BF_MCM_ISR_IRQ(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_IRQ), uint32_t) & BM_MCM_ISR_IRQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRQ field to a new value.
+#define BW_MCM_ISR_IRQ(v)    (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0 - No pending NMI
+ * - 1 - Due to the ETB counter expiring, an NMI is pending
+ */
+//@{
+#define BP_MCM_ISR_NMI       (2U)          //!< Bit position for MCM_ISR_NMI.
+#define BM_MCM_ISR_NMI       (0x00000004U) //!< Bit mask for MCM_ISR_NMI.
+#define BS_MCM_ISR_NMI       (1U)          //!< Bit field size in bits for MCM_ISR_NMI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_NMI field.
+#define BR_MCM_ISR_NMI       (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_NMI.
+#define BF_MCM_ISR_NMI(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_NMI), uint32_t) & BM_MCM_ISR_NMI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NMI field to a new value.
+#define BW_MCM_ISR_NMI(v)    (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0 - No debug halt request
+ * - 1 - Debug halt request initiated
+ */
+//@{
+#define BP_MCM_ISR_DHREQ     (3U)          //!< Bit position for MCM_ISR_DHREQ.
+#define BM_MCM_ISR_DHREQ     (0x00000008U) //!< Bit mask for MCM_ISR_DHREQ.
+#define BS_MCM_ISR_DHREQ     (1U)          //!< Bit field size in bits for MCM_ISR_DHREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_DHREQ field.
+#define BR_MCM_ISR_DHREQ     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_DHREQ))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FIOC      (8U)          //!< Bit position for MCM_ISR_FIOC.
+#define BM_MCM_ISR_FIOC      (0x00000100U) //!< Bit mask for MCM_ISR_FIOC.
+#define BS_MCM_ISR_FIOC      (1U)          //!< Bit field size in bits for MCM_ISR_FIOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIOC field.
+#define BR_MCM_ISR_FIOC      (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FDZC      (9U)          //!< Bit position for MCM_ISR_FDZC.
+#define BM_MCM_ISR_FDZC      (0x00000200U) //!< Bit mask for MCM_ISR_FDZC.
+#define BS_MCM_ISR_FDZC      (1U)          //!< Bit field size in bits for MCM_ISR_FDZC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FDZC field.
+#define BR_MCM_ISR_FDZC      (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FOFC      (10U)         //!< Bit position for MCM_ISR_FOFC.
+#define BM_MCM_ISR_FOFC      (0x00000400U) //!< Bit mask for MCM_ISR_FOFC.
+#define BS_MCM_ISR_FOFC      (1U)          //!< Bit field size in bits for MCM_ISR_FOFC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FOFC field.
+#define BR_MCM_ISR_FOFC      (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FUFC      (11U)         //!< Bit position for MCM_ISR_FUFC.
+#define BM_MCM_ISR_FUFC      (0x00000800U) //!< Bit mask for MCM_ISR_FUFC.
+#define BS_MCM_ISR_FUFC      (1U)          //!< Bit field size in bits for MCM_ISR_FUFC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FUFC field.
+#define BR_MCM_ISR_FUFC      (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FIXC      (12U)         //!< Bit position for MCM_ISR_FIXC.
+#define BM_MCM_ISR_FIXC      (0x00001000U) //!< Bit mask for MCM_ISR_FIXC.
+#define BS_MCM_ISR_FIXC      (1U)          //!< Bit field size in bits for MCM_ISR_FIXC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIXC field.
+#define BR_MCM_ISR_FIXC      (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FIDC      (15U)         //!< Bit position for MCM_ISR_FIDC.
+#define BM_MCM_ISR_FIDC      (0x00008000U) //!< Bit mask for MCM_ISR_FIDC.
+#define BS_MCM_ISR_FIDC      (1U)          //!< Bit field size in bits for MCM_ISR_FIDC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIDC field.
+#define BR_MCM_ISR_FIDC      (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FIOCE     (24U)         //!< Bit position for MCM_ISR_FIOCE.
+#define BM_MCM_ISR_FIOCE     (0x01000000U) //!< Bit mask for MCM_ISR_FIOCE.
+#define BS_MCM_ISR_FIOCE     (1U)          //!< Bit field size in bits for MCM_ISR_FIOCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIOCE field.
+#define BR_MCM_ISR_FIOCE     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FIOCE.
+#define BF_MCM_ISR_FIOCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIOCE), uint32_t) & BM_MCM_ISR_FIOCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FIOCE field to a new value.
+#define BW_MCM_ISR_FIOCE(v)  (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FDZCE     (25U)         //!< Bit position for MCM_ISR_FDZCE.
+#define BM_MCM_ISR_FDZCE     (0x02000000U) //!< Bit mask for MCM_ISR_FDZCE.
+#define BS_MCM_ISR_FDZCE     (1U)          //!< Bit field size in bits for MCM_ISR_FDZCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FDZCE field.
+#define BR_MCM_ISR_FDZCE     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FDZCE.
+#define BF_MCM_ISR_FDZCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FDZCE), uint32_t) & BM_MCM_ISR_FDZCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FDZCE field to a new value.
+#define BW_MCM_ISR_FDZCE(v)  (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FOFCE     (26U)         //!< Bit position for MCM_ISR_FOFCE.
+#define BM_MCM_ISR_FOFCE     (0x04000000U) //!< Bit mask for MCM_ISR_FOFCE.
+#define BS_MCM_ISR_FOFCE     (1U)          //!< Bit field size in bits for MCM_ISR_FOFCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FOFCE field.
+#define BR_MCM_ISR_FOFCE     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FOFCE.
+#define BF_MCM_ISR_FOFCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FOFCE), uint32_t) & BM_MCM_ISR_FOFCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FOFCE field to a new value.
+#define BW_MCM_ISR_FOFCE(v)  (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FUFCE     (27U)         //!< Bit position for MCM_ISR_FUFCE.
+#define BM_MCM_ISR_FUFCE     (0x08000000U) //!< Bit mask for MCM_ISR_FUFCE.
+#define BS_MCM_ISR_FUFCE     (1U)          //!< Bit field size in bits for MCM_ISR_FUFCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FUFCE field.
+#define BR_MCM_ISR_FUFCE     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FUFCE.
+#define BF_MCM_ISR_FUFCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FUFCE), uint32_t) & BM_MCM_ISR_FUFCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FUFCE field to a new value.
+#define BW_MCM_ISR_FUFCE(v)  (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FIXCE     (28U)         //!< Bit position for MCM_ISR_FIXCE.
+#define BM_MCM_ISR_FIXCE     (0x10000000U) //!< Bit mask for MCM_ISR_FIXCE.
+#define BS_MCM_ISR_FIXCE     (1U)          //!< Bit field size in bits for MCM_ISR_FIXCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIXCE field.
+#define BR_MCM_ISR_FIXCE     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FIXCE.
+#define BF_MCM_ISR_FIXCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIXCE), uint32_t) & BM_MCM_ISR_FIXCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FIXCE field to a new value.
+#define BW_MCM_ISR_FIXCE(v)  (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FIDCE     (31U)         //!< Bit position for MCM_ISR_FIDCE.
+#define BM_MCM_ISR_FIDCE     (0x80000000U) //!< Bit mask for MCM_ISR_FIDCE.
+#define BS_MCM_ISR_FIDCE     (1U)          //!< Bit field size in bits for MCM_ISR_FIDCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIDCE field.
+#define BR_MCM_ISR_FIDCE     (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FIDCE.
+#define BF_MCM_ISR_FIDCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIDCE), uint32_t) & BM_MCM_ISR_FIDCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FIDCE field to a new value.
+#define BW_MCM_ISR_FIDCE(v)  (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ETBCC - ETB Counter Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_etbcc
+{
+    uint32_t U;
+    struct _hw_mcm_etbcc_bitfields
+    {
+        uint32_t CNTEN : 1;            //!< [0] Counter Enable
+        uint32_t RSPT : 2;             //!< [2:1] Response Type
+        uint32_t RLRQ : 1;             //!< [3] Reload Request
+        uint32_t ETDIS : 1;            //!< [4] ETM-To-TPIU Disable
+        uint32_t ITDIS : 1;            //!< [5] ITM-To-TPIU Disable
+        uint32_t RESERVED0 : 26;       //!< [31:6]
+    } B;
+} hw_mcm_etbcc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+//@{
+#define HW_MCM_ETBCC_ADDR        (REGS_MCM_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ETBCC             (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR)
+#define HW_MCM_ETBCC_RD()        (HW_MCM_ETBCC.U)
+#define HW_MCM_ETBCC_WR(v)       (HW_MCM_ETBCC.U = (v))
+#define HW_MCM_ETBCC_SET(v)      (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() |  (v)))
+#define HW_MCM_ETBCC_CLR(v)      (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() & ~(v)))
+#define HW_MCM_ETBCC_TOG(v)      (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0 - ETB counter disabled
+ * - 1 - ETB counter enabled
+ */
+//@{
+#define BP_MCM_ETBCC_CNTEN   (0U)          //!< Bit position for MCM_ETBCC_CNTEN.
+#define BM_MCM_ETBCC_CNTEN   (0x00000001U) //!< Bit mask for MCM_ETBCC_CNTEN.
+#define BS_MCM_ETBCC_CNTEN   (1U)          //!< Bit field size in bits for MCM_ETBCC_CNTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_CNTEN field.
+#define BR_MCM_ETBCC_CNTEN   (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_CNTEN.
+#define BF_MCM_ETBCC_CNTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_CNTEN), uint32_t) & BM_MCM_ETBCC_CNTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTEN field to a new value.
+#define BW_MCM_ETBCC_CNTEN(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 00 - No response when the ETB count expires
+ * - 01 - Generate a normal interrupt when the ETB count expires
+ * - 10 - Generate an NMI when the ETB count expires
+ * - 11 - Generate a debug halt when the ETB count expires
+ */
+//@{
+#define BP_MCM_ETBCC_RSPT    (1U)          //!< Bit position for MCM_ETBCC_RSPT.
+#define BM_MCM_ETBCC_RSPT    (0x00000006U) //!< Bit mask for MCM_ETBCC_RSPT.
+#define BS_MCM_ETBCC_RSPT    (2U)          //!< Bit field size in bits for MCM_ETBCC_RSPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_RSPT field.
+#define BR_MCM_ETBCC_RSPT    (HW_MCM_ETBCC.B.RSPT)
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_RSPT.
+#define BF_MCM_ETBCC_RSPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RSPT), uint32_t) & BM_MCM_ETBCC_RSPT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSPT field to a new value.
+#define BW_MCM_ETBCC_RSPT(v) (HW_MCM_ETBCC_WR((HW_MCM_ETBCC_RD() & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0 - No effect
+ * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+//@{
+#define BP_MCM_ETBCC_RLRQ    (3U)          //!< Bit position for MCM_ETBCC_RLRQ.
+#define BM_MCM_ETBCC_RLRQ    (0x00000008U) //!< Bit mask for MCM_ETBCC_RLRQ.
+#define BS_MCM_ETBCC_RLRQ    (1U)          //!< Bit field size in bits for MCM_ETBCC_RLRQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_RLRQ field.
+#define BR_MCM_ETBCC_RLRQ    (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_RLRQ.
+#define BF_MCM_ETBCC_RLRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RLRQ), uint32_t) & BM_MCM_ETBCC_RLRQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RLRQ field to a new value.
+#define BW_MCM_ETBCC_RLRQ(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0 - ETM-to-TPIU trace path enabled
+ * - 1 - ETM-to-TPIU trace path disabled
+ */
+//@{
+#define BP_MCM_ETBCC_ETDIS   (4U)          //!< Bit position for MCM_ETBCC_ETDIS.
+#define BM_MCM_ETBCC_ETDIS   (0x00000010U) //!< Bit mask for MCM_ETBCC_ETDIS.
+#define BS_MCM_ETBCC_ETDIS   (1U)          //!< Bit field size in bits for MCM_ETBCC_ETDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_ETDIS field.
+#define BR_MCM_ETBCC_ETDIS   (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_ETDIS.
+#define BF_MCM_ETBCC_ETDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ETDIS), uint32_t) & BM_MCM_ETBCC_ETDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ETDIS field to a new value.
+#define BW_MCM_ETBCC_ETDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0 - ITM-to-TPIU trace path enabled
+ * - 1 - ITM-to-TPIU trace path disabled
+ */
+//@{
+#define BP_MCM_ETBCC_ITDIS   (5U)          //!< Bit position for MCM_ETBCC_ITDIS.
+#define BM_MCM_ETBCC_ITDIS   (0x00000020U) //!< Bit mask for MCM_ETBCC_ITDIS.
+#define BS_MCM_ETBCC_ITDIS   (1U)          //!< Bit field size in bits for MCM_ETBCC_ITDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_ITDIS field.
+#define BR_MCM_ETBCC_ITDIS   (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_ITDIS.
+#define BF_MCM_ETBCC_ITDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ITDIS), uint32_t) & BM_MCM_ETBCC_ITDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ITDIS field to a new value.
+#define BW_MCM_ETBCC_ITDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ETBRL - ETB Reload register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_etbrl
+{
+    uint32_t U;
+    struct _hw_mcm_etbrl_bitfields
+    {
+        uint32_t RELOAD : 11;          //!< [10:0] Byte Count Reload Value
+        uint32_t RESERVED0 : 21;       //!< [31:11]
+    } B;
+} hw_mcm_etbrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+//@{
+#define HW_MCM_ETBRL_ADDR        (REGS_MCM_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ETBRL             (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR)
+#define HW_MCM_ETBRL_RD()        (HW_MCM_ETBRL.U)
+#define HW_MCM_ETBRL_WR(v)       (HW_MCM_ETBRL.U = (v))
+#define HW_MCM_ETBRL_SET(v)      (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() |  (v)))
+#define HW_MCM_ETBRL_CLR(v)      (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() & ~(v)))
+#define HW_MCM_ETBRL_TOG(v)      (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+//@{
+#define BP_MCM_ETBRL_RELOAD  (0U)          //!< Bit position for MCM_ETBRL_RELOAD.
+#define BM_MCM_ETBRL_RELOAD  (0x000007FFU) //!< Bit mask for MCM_ETBRL_RELOAD.
+#define BS_MCM_ETBRL_RELOAD  (11U)         //!< Bit field size in bits for MCM_ETBRL_RELOAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBRL_RELOAD field.
+#define BR_MCM_ETBRL_RELOAD  (HW_MCM_ETBRL.B.RELOAD)
+#endif
+
+//! @brief Format value for bitfield MCM_ETBRL_RELOAD.
+#define BF_MCM_ETBRL_RELOAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBRL_RELOAD), uint32_t) & BM_MCM_ETBRL_RELOAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RELOAD field to a new value.
+#define BW_MCM_ETBRL_RELOAD(v) (HW_MCM_ETBRL_WR((HW_MCM_ETBRL_RD() & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ETBCNT - ETB Counter Value register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_etbcnt
+{
+    uint32_t U;
+    struct _hw_mcm_etbcnt_bitfields
+    {
+        uint32_t COUNTER : 11;         //!< [10:0] Byte Count Counter Value
+        uint32_t RESERVED0 : 21;       //!< [31:11]
+    } B;
+} hw_mcm_etbcnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+//@{
+#define HW_MCM_ETBCNT_ADDR       (REGS_MCM_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ETBCNT            (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR)
+#define HW_MCM_ETBCNT_RD()       (HW_MCM_ETBCNT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+//@{
+#define BP_MCM_ETBCNT_COUNTER (0U)         //!< Bit position for MCM_ETBCNT_COUNTER.
+#define BM_MCM_ETBCNT_COUNTER (0x000007FFU) //!< Bit mask for MCM_ETBCNT_COUNTER.
+#define BS_MCM_ETBCNT_COUNTER (11U)        //!< Bit field size in bits for MCM_ETBCNT_COUNTER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCNT_COUNTER field.
+#define BR_MCM_ETBCNT_COUNTER (HW_MCM_ETBCNT.B.COUNTER)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_PID - Process ID register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+typedef union _hw_mcm_pid
+{
+    uint32_t U;
+    struct _hw_mcm_pid_bitfields
+    {
+        uint32_t PID : 8;              //!< [7:0] M0_PID And M1_PID For MPU
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_mcm_pid_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+//@{
+#define HW_MCM_PID_ADDR          (REGS_MCM_BASE + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_PID               (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR)
+#define HW_MCM_PID_RD()          (HW_MCM_PID.U)
+#define HW_MCM_PID_WR(v)         (HW_MCM_PID.U = (v))
+#define HW_MCM_PID_SET(v)        (HW_MCM_PID_WR(HW_MCM_PID_RD() |  (v)))
+#define HW_MCM_PID_CLR(v)        (HW_MCM_PID_WR(HW_MCM_PID_RD() & ~(v)))
+#define HW_MCM_PID_TOG(v)        (HW_MCM_PID_WR(HW_MCM_PID_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+//@{
+#define BP_MCM_PID_PID       (0U)          //!< Bit position for MCM_PID_PID.
+#define BM_MCM_PID_PID       (0x000000FFU) //!< Bit mask for MCM_PID_PID.
+#define BS_MCM_PID_PID       (8U)          //!< Bit field size in bits for MCM_PID_PID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_PID_PID field.
+#define BR_MCM_PID_PID       (HW_MCM_PID.B.PID)
+#endif
+
+//! @brief Format value for bitfield MCM_PID_PID.
+#define BF_MCM_PID_PID(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_PID_PID), uint32_t) & BM_MCM_PID_PID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PID field to a new value.
+#define BW_MCM_PID_PID(v)    (HW_MCM_PID_WR((HW_MCM_PID_RD() & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_mcm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All MCM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_mcm
+{
+    uint8_t _reserved0[8];
+    __I hw_mcm_plasc_t PLASC;              //!< [0x8] Crossbar Switch (AXBS) Slave Configuration
+    __I hw_mcm_plamc_t PLAMC;              //!< [0xA] Crossbar Switch (AXBS) Master Configuration
+    __IO hw_mcm_cr_t CR;                   //!< [0xC] Control Register
+    __IO hw_mcm_isr_t ISR;                 //!< [0x10] Interrupt Status Register
+    __IO hw_mcm_etbcc_t ETBCC;             //!< [0x14] ETB Counter Control register
+    __IO hw_mcm_etbrl_t ETBRL;             //!< [0x18] ETB Reload register
+    __I hw_mcm_etbcnt_t ETBCNT;            //!< [0x1C] ETB Counter Value register
+    uint8_t _reserved1[16];
+    __IO hw_mcm_pid_t PID;                 //!< [0x30] Process ID register
+} hw_mcm_t;
+#pragma pack()
+
+//! @brief Macro to access all MCM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_MCM</code>.
+#define HW_MCM         (*(hw_mcm_t *) REGS_MCM_BASE)
+#endif
+
+#endif // __HW_MCM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h
new file mode 100644
index 0000000000..7ffd8a9506
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h
@@ -0,0 +1,1923 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_MPU_REGISTERS_H__
+#define __HW_MPU_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - HW_MPU_CESR - Control/Error Status Register
+ * - HW_MPU_EARn - Error Address Register, slave port n
+ * - HW_MPU_EDRn - Error Detail Register, slave port n
+ * - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
+ * - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
+ * - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
+ * - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
+ * - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
+ *
+ * - hw_mpu_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_MPU_BASE
+#define HW_MPU_INSTANCE_COUNT (1U) //!< Number of instances of the MPU module.
+#define REGS_MPU_BASE (0x4000D000U) //!< Base address for MPU.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_CESR - Control/Error Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+typedef union _hw_mpu_cesr
+{
+    uint32_t U;
+    struct _hw_mpu_cesr_bitfields
+    {
+        uint32_t VLD : 1;              //!< [0] Valid
+        uint32_t RESERVED0 : 7;        //!< [7:1]
+        uint32_t NRGD : 4;             //!< [11:8] Number Of Region Descriptors
+        uint32_t NSP : 4;              //!< [15:12] Number Of Slave Ports
+        uint32_t HRL : 4;              //!< [19:16] Hardware Revision Level
+        uint32_t RESERVED1 : 7;        //!< [26:20]
+        uint32_t SPERR : 5;            //!< [31:27] Slave Port n Error
+    } B;
+} hw_mpu_cesr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+//@{
+#define HW_MPU_CESR_ADDR         (REGS_MPU_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_CESR              (*(__IO hw_mpu_cesr_t *) HW_MPU_CESR_ADDR)
+#define HW_MPU_CESR_RD()         (HW_MPU_CESR.U)
+#define HW_MPU_CESR_WR(v)        (HW_MPU_CESR.U = (v))
+#define HW_MPU_CESR_SET(v)       (HW_MPU_CESR_WR(HW_MPU_CESR_RD() |  (v)))
+#define HW_MPU_CESR_CLR(v)       (HW_MPU_CESR_WR(HW_MPU_CESR_RD() & ~(v)))
+#define HW_MPU_CESR_TOG(v)       (HW_MPU_CESR_WR(HW_MPU_CESR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 1 - MPU is enabled
+ */
+//@{
+#define BP_MPU_CESR_VLD      (0U)          //!< Bit position for MPU_CESR_VLD.
+#define BM_MPU_CESR_VLD      (0x00000001U) //!< Bit mask for MPU_CESR_VLD.
+#define BS_MPU_CESR_VLD      (1U)          //!< Bit field size in bits for MPU_CESR_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_VLD field.
+#define BR_MPU_CESR_VLD      (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD))
+#endif
+
+//! @brief Format value for bitfield MPU_CESR_VLD.
+#define BF_MPU_CESR_VLD(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_VLD), uint32_t) & BM_MPU_CESR_VLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VLD field to a new value.
+#define BW_MPU_CESR_VLD(v)   (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0000 - 8 region descriptors
+ * - 0001 - 12 region descriptors
+ * - 0010 - 16 region descriptors
+ */
+//@{
+#define BP_MPU_CESR_NRGD     (8U)          //!< Bit position for MPU_CESR_NRGD.
+#define BM_MPU_CESR_NRGD     (0x00000F00U) //!< Bit mask for MPU_CESR_NRGD.
+#define BS_MPU_CESR_NRGD     (4U)          //!< Bit field size in bits for MPU_CESR_NRGD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_NRGD field.
+#define BR_MPU_CESR_NRGD     (HW_MPU_CESR.B.NRGD)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+//@{
+#define BP_MPU_CESR_NSP      (12U)         //!< Bit position for MPU_CESR_NSP.
+#define BM_MPU_CESR_NSP      (0x0000F000U) //!< Bit mask for MPU_CESR_NSP.
+#define BS_MPU_CESR_NSP      (4U)          //!< Bit field size in bits for MPU_CESR_NSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_NSP field.
+#define BR_MPU_CESR_NSP      (HW_MPU_CESR.B.NSP)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+//@{
+#define BP_MPU_CESR_HRL      (16U)         //!< Bit position for MPU_CESR_HRL.
+#define BM_MPU_CESR_HRL      (0x000F0000U) //!< Bit mask for MPU_CESR_HRL.
+#define BS_MPU_CESR_HRL      (4U)          //!< Bit field size in bits for MPU_CESR_HRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_HRL field.
+#define BR_MPU_CESR_HRL      (HW_MPU_CESR.B.HRL)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0 - No error has occurred for slave port n.
+ * - 1 - An error has occurred for slave port n.
+ */
+//@{
+#define BP_MPU_CESR_SPERR    (27U)         //!< Bit position for MPU_CESR_SPERR.
+#define BM_MPU_CESR_SPERR    (0xF8000000U) //!< Bit mask for MPU_CESR_SPERR.
+#define BS_MPU_CESR_SPERR    (5U)          //!< Bit field size in bits for MPU_CESR_SPERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_SPERR field.
+#define BR_MPU_CESR_SPERR    (HW_MPU_CESR.B.SPERR)
+#endif
+
+//! @brief Format value for bitfield MPU_CESR_SPERR.
+#define BF_MPU_CESR_SPERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_SPERR), uint32_t) & BM_MPU_CESR_SPERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPERR field to a new value.
+#define BW_MPU_CESR_SPERR(v) (HW_MPU_CESR_WR((HW_MPU_CESR_RD() & ~BM_MPU_CESR_SPERR) | BF_MPU_CESR_SPERR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_EARn - Error Address Register, slave port n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+typedef union _hw_mpu_earn
+{
+    uint32_t U;
+    struct _hw_mpu_earn_bitfields
+    {
+        uint32_t EADDR : 32;           //!< [31:0] Error Address
+    } B;
+} hw_mpu_earn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_EARn register
+ */
+//@{
+#define HW_MPU_EARn_COUNT (5U)
+
+#define HW_MPU_EARn_ADDR(n)      (REGS_MPU_BASE + 0x10U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_EARn(n)           (*(__I hw_mpu_earn_t *) HW_MPU_EARn_ADDR(n))
+#define HW_MPU_EARn_RD(n)        (HW_MPU_EARn(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_EARn bitfields
+ */
+
+/*!
+ * @name Register MPU_EARn, field EADDR[31:0] (RO)
+ *
+ * Indicates the reference address from slave port n that generated the access
+ * error
+ */
+//@{
+#define BP_MPU_EARn_EADDR    (0U)          //!< Bit position for MPU_EARn_EADDR.
+#define BM_MPU_EARn_EADDR    (0xFFFFFFFFU) //!< Bit mask for MPU_EARn_EADDR.
+#define BS_MPU_EARn_EADDR    (32U)         //!< Bit field size in bits for MPU_EARn_EADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EARn_EADDR field.
+#define BR_MPU_EARn_EADDR(n) (HW_MPU_EARn(n).U)
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_EDRn - Error Detail Register, slave port n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+typedef union _hw_mpu_edrn
+{
+    uint32_t U;
+    struct _hw_mpu_edrn_bitfields
+    {
+        uint32_t ERW : 1;              //!< [0] Error Read/Write
+        uint32_t EATTR : 3;            //!< [3:1] Error Attributes
+        uint32_t EMN : 4;              //!< [7:4] Error Master Number
+        uint32_t EPID : 8;             //!< [15:8] Error Process Identification
+        uint32_t EACD : 16;            //!< [31:16] Error Access Control Detail
+    } B;
+} hw_mpu_edrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_EDRn register
+ */
+//@{
+#define HW_MPU_EDRn_COUNT (5U)
+
+#define HW_MPU_EDRn_ADDR(n)      (REGS_MPU_BASE + 0x14U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_EDRn(n)           (*(__I hw_mpu_edrn_t *) HW_MPU_EDRn_ADDR(n))
+#define HW_MPU_EDRn_RD(n)        (HW_MPU_EDRn(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_EDRn bitfields
+ */
+
+/*!
+ * @name Register MPU_EDRn, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0 - Read
+ * - 1 - Write
+ */
+//@{
+#define BP_MPU_EDRn_ERW      (0U)          //!< Bit position for MPU_EDRn_ERW.
+#define BM_MPU_EDRn_ERW      (0x00000001U) //!< Bit mask for MPU_EDRn_ERW.
+#define BS_MPU_EDRn_ERW      (1U)          //!< Bit field size in bits for MPU_EDRn_ERW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_ERW field.
+#define BR_MPU_EDRn_ERW(n)   (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(n), BP_MPU_EDRn_ERW))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 000 - User mode, instruction access
+ * - 001 - User mode, data access
+ * - 010 - Supervisor mode, instruction access
+ * - 011 - Supervisor mode, data access
+ */
+//@{
+#define BP_MPU_EDRn_EATTR    (1U)          //!< Bit position for MPU_EDRn_EATTR.
+#define BM_MPU_EDRn_EATTR    (0x0000000EU) //!< Bit mask for MPU_EDRn_EATTR.
+#define BS_MPU_EDRn_EATTR    (3U)          //!< Bit field size in bits for MPU_EDRn_EATTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EATTR field.
+#define BR_MPU_EDRn_EATTR(n) (HW_MPU_EDRn(n).B.EATTR)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+//@{
+#define BP_MPU_EDRn_EMN      (4U)          //!< Bit position for MPU_EDRn_EMN.
+#define BM_MPU_EDRn_EMN      (0x000000F0U) //!< Bit mask for MPU_EDRn_EMN.
+#define BS_MPU_EDRn_EMN      (4U)          //!< Bit field size in bits for MPU_EDRn_EMN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EMN field.
+#define BR_MPU_EDRn_EMN(n)   (HW_MPU_EDRn(n).B.EMN)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+//@{
+#define BP_MPU_EDRn_EPID     (8U)          //!< Bit position for MPU_EDRn_EPID.
+#define BM_MPU_EDRn_EPID     (0x0000FF00U) //!< Bit mask for MPU_EDRn_EPID.
+#define BS_MPU_EDRn_EPID     (8U)          //!< Bit field size in bits for MPU_EDRn_EPID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EPID field.
+#define BR_MPU_EDRn_EPID(n)  (HW_MPU_EDRn(n).B.EPID)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+//@{
+#define BP_MPU_EDRn_EACD     (16U)         //!< Bit position for MPU_EDRn_EACD.
+#define BM_MPU_EDRn_EACD     (0xFFFF0000U) //!< Bit mask for MPU_EDRn_EACD.
+#define BS_MPU_EDRn_EACD     (16U)         //!< Bit field size in bits for MPU_EDRn_EACD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EACD field.
+#define BR_MPU_EDRn_EACD(n)  (HW_MPU_EDRn(n).B.EACD)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+typedef union _hw_mpu_rgdn_word0
+{
+    uint32_t U;
+    struct _hw_mpu_rgdn_word0_bitfields
+    {
+        uint32_t RESERVED0 : 5;        //!< [4:0]
+        uint32_t SRTADDR : 27;         //!< [31:5] Start Address
+    } B;
+} hw_mpu_rgdn_word0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD0 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD0_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD0_ADDR(n) (REGS_MPU_BASE + 0x400U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD0(n)     (*(__IO hw_mpu_rgdn_word0_t *) HW_MPU_RGDn_WORD0_ADDR(n))
+#define HW_MPU_RGDn_WORD0_RD(n)  (HW_MPU_RGDn_WORD0(n).U)
+#define HW_MPU_RGDn_WORD0_WR(n, v) (HW_MPU_RGDn_WORD0(n).U = (v))
+#define HW_MPU_RGDn_WORD0_SET(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) |  (v)))
+#define HW_MPU_RGDn_WORD0_CLR(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD0_TOG(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD0 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+//@{
+#define BP_MPU_RGDn_WORD0_SRTADDR (5U)     //!< Bit position for MPU_RGDn_WORD0_SRTADDR.
+#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD0_SRTADDR.
+#define BS_MPU_RGDn_WORD0_SRTADDR (27U)    //!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field.
+#define BR_MPU_RGDn_WORD0_SRTADDR(n) (HW_MPU_RGDn_WORD0(n).B.SRTADDR)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR.
+#define BF_MPU_RGDn_WORD0_SRTADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD0_SRTADDR), uint32_t) & BM_MPU_RGDn_WORD0_SRTADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRTADDR field to a new value.
+#define BW_MPU_RGDn_WORD0_SRTADDR(n, v) (HW_MPU_RGDn_WORD0_WR(n, (HW_MPU_RGDn_WORD0_RD(n) & ~BM_MPU_RGDn_WORD0_SRTADDR) | BF_MPU_RGDn_WORD0_SRTADDR(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The second word of the region descriptor defines the 31-modulo-32 byte end
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+typedef union _hw_mpu_rgdn_word1
+{
+    uint32_t U;
+    struct _hw_mpu_rgdn_word1_bitfields
+    {
+        uint32_t RESERVED0 : 5;        //!< [4:0]
+        uint32_t ENDADDR : 27;         //!< [31:5] End Address
+    } B;
+} hw_mpu_rgdn_word1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD1 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD1_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD1_ADDR(n) (REGS_MPU_BASE + 0x404U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD1(n)     (*(__IO hw_mpu_rgdn_word1_t *) HW_MPU_RGDn_WORD1_ADDR(n))
+#define HW_MPU_RGDn_WORD1_RD(n)  (HW_MPU_RGDn_WORD1(n).U)
+#define HW_MPU_RGDn_WORD1_WR(n, v) (HW_MPU_RGDn_WORD1(n).U = (v))
+#define HW_MPU_RGDn_WORD1_SET(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) |  (v)))
+#define HW_MPU_RGDn_WORD1_CLR(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD1_TOG(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD1 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+//@{
+#define BP_MPU_RGDn_WORD1_ENDADDR (5U)     //!< Bit position for MPU_RGDn_WORD1_ENDADDR.
+#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD1_ENDADDR.
+#define BS_MPU_RGDn_WORD1_ENDADDR (27U)    //!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field.
+#define BR_MPU_RGDn_WORD1_ENDADDR(n) (HW_MPU_RGDn_WORD1(n).B.ENDADDR)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR.
+#define BF_MPU_RGDn_WORD1_ENDADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD1_ENDADDR), uint32_t) & BM_MPU_RGDn_WORD1_ENDADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENDADDR field to a new value.
+#define BW_MPU_RGDn_WORD1_ENDADDR(n, v) (HW_MPU_RGDn_WORD1_WR(n, (HW_MPU_RGDn_WORD1_RD(n) & ~BM_MPU_RGDn_WORD1_ENDADDR) | BF_MPU_RGDn_WORD1_ENDADDR(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * The third word of the region descriptor defines the access control rights of
+ * the memory region. The access control privileges depend on two broad
+ * classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
+ * privilege rights for user and supervisor mode accesses, as well as the optional
+ * inclusion of a process identification field within the definition. Bus masters
+ * 4-7 are limited to separate read and write permissions. For the privilege
+ * rights of bus masters 0-3, there are three flags associated with this function:
+ * Read (r) refers to accessing the referenced memory address using an operand
+ * (data) fetch Write (w) refers to updating the referenced memory address using a
+ * store (data) instruction Execute (x) refers to reading the referenced memory
+ * address using an instruction fetch Writes to RGDn_WORD2 clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
+ * to RGDAACn instead because stores to these locations do not affect the
+ * descriptor's valid bit.
+ */
+typedef union _hw_mpu_rgdn_word2
+{
+    uint32_t U;
+    struct _hw_mpu_rgdn_word2_bitfields
+    {
+        uint32_t M0UM : 3;             //!< [2:0] Bus Master 0 User Mode Access Control
+        uint32_t M0SM : 2;             //!< [4:3] Bus Master 0 Supervisor Mode Access
+                                       //! Control
+        uint32_t M0PE : 1;             //!< [5] Bus Master 0 Process Identifier enable
+        uint32_t M1UM : 3;             //!< [8:6] Bus Master 1 User Mode Access Control
+        uint32_t M1SM : 2;             //!< [10:9] Bus Master 1 Supervisor Mode Access
+                                       //! Control
+        uint32_t M1PE : 1;             //!< [11] Bus Master 1 Process Identifier enable
+        uint32_t M2UM : 3;             //!< [14:12] Bus Master 2 User Mode Access control
+        uint32_t M2SM : 2;             //!< [16:15] Bus Master 2 Supervisor Mode Access
+                                       //! Control
+        uint32_t M2PE : 1;             //!< [17] Bus Master 2 Process Identifier Enable
+        uint32_t M3UM : 3;             //!< [20:18] Bus Master 3 User Mode Access Control
+        uint32_t M3SM : 2;             //!< [22:21] Bus Master 3 Supervisor Mode Access
+                                       //! Control
+        uint32_t M3PE : 1;             //!< [23] Bus Master 3 Process Identifier Enable
+        uint32_t M4WE : 1;             //!< [24] Bus Master 4 Write Enable
+        uint32_t M4RE : 1;             //!< [25] Bus Master 4 Read Enable
+        uint32_t M5WE : 1;             //!< [26] Bus Master 5 Write Enable
+        uint32_t M5RE : 1;             //!< [27] Bus Master 5 Read Enable
+        uint32_t M6WE : 1;             //!< [28] Bus Master 6 Write Enable
+        uint32_t M6RE : 1;             //!< [29] Bus Master 6 Read Enable
+        uint32_t M7WE : 1;             //!< [30] Bus Master 7 Write Enable
+        uint32_t M7RE : 1;             //!< [31] Bus Master 7 Read Enable
+    } B;
+} hw_mpu_rgdn_word2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD2 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD2_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD2_ADDR(n) (REGS_MPU_BASE + 0x408U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD2(n)     (*(__IO hw_mpu_rgdn_word2_t *) HW_MPU_RGDn_WORD2_ADDR(n))
+#define HW_MPU_RGDn_WORD2_RD(n)  (HW_MPU_RGDn_WORD2(n).U)
+#define HW_MPU_RGDn_WORD2_WR(n, v) (HW_MPU_RGDn_WORD2(n).U = (v))
+#define HW_MPU_RGDn_WORD2_SET(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) |  (v)))
+#define HW_MPU_RGDn_WORD2_CLR(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD2_TOG(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD2 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M0UM (0U)        //!< Bit position for MPU_RGDn_WORD2_M0UM.
+#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) //!< Bit mask for MPU_RGDn_WORD2_M0UM.
+#define BS_MPU_RGDn_WORD2_M0UM (3U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M0UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M0UM field.
+#define BR_MPU_RGDn_WORD2_M0UM(n) (HW_MPU_RGDn_WORD2(n).B.M0UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM.
+#define BF_MPU_RGDn_WORD2_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0UM), uint32_t) & BM_MPU_RGDn_WORD2_M0UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M0UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0UM) | BF_MPU_RGDn_WORD2_M0UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M0SM (3U)        //!< Bit position for MPU_RGDn_WORD2_M0SM.
+#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) //!< Bit mask for MPU_RGDn_WORD2_M0SM.
+#define BS_MPU_RGDn_WORD2_M0SM (2U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M0SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M0SM field.
+#define BR_MPU_RGDn_WORD2_M0SM(n) (HW_MPU_RGDn_WORD2(n).B.M0SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM.
+#define BF_MPU_RGDn_WORD2_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0SM), uint32_t) & BM_MPU_RGDn_WORD2_M0SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M0SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0SM) | BF_MPU_RGDn_WORD2_M0SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M0PE (5U)        //!< Bit position for MPU_RGDn_WORD2_M0PE.
+#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) //!< Bit mask for MPU_RGDn_WORD2_M0PE.
+#define BS_MPU_RGDn_WORD2_M0PE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M0PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M0PE field.
+#define BR_MPU_RGDn_WORD2_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE.
+#define BF_MPU_RGDn_WORD2_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0PE), uint32_t) & BM_MPU_RGDn_WORD2_M0PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M1UM (6U)        //!< Bit position for MPU_RGDn_WORD2_M1UM.
+#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDn_WORD2_M1UM.
+#define BS_MPU_RGDn_WORD2_M1UM (3U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M1UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M1UM field.
+#define BR_MPU_RGDn_WORD2_M1UM(n) (HW_MPU_RGDn_WORD2(n).B.M1UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM.
+#define BF_MPU_RGDn_WORD2_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1UM), uint32_t) & BM_MPU_RGDn_WORD2_M1UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M1UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1UM) | BF_MPU_RGDn_WORD2_M1UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M1SM (9U)        //!< Bit position for MPU_RGDn_WORD2_M1SM.
+#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) //!< Bit mask for MPU_RGDn_WORD2_M1SM.
+#define BS_MPU_RGDn_WORD2_M1SM (2U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M1SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M1SM field.
+#define BR_MPU_RGDn_WORD2_M1SM(n) (HW_MPU_RGDn_WORD2(n).B.M1SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM.
+#define BF_MPU_RGDn_WORD2_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1SM), uint32_t) & BM_MPU_RGDn_WORD2_M1SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M1SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1SM) | BF_MPU_RGDn_WORD2_M1SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M1PE (11U)       //!< Bit position for MPU_RGDn_WORD2_M1PE.
+#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) //!< Bit mask for MPU_RGDn_WORD2_M1PE.
+#define BS_MPU_RGDn_WORD2_M1PE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M1PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M1PE field.
+#define BR_MPU_RGDn_WORD2_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE.
+#define BF_MPU_RGDn_WORD2_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1PE), uint32_t) & BM_MPU_RGDn_WORD2_M1PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M2UM (12U)       //!< Bit position for MPU_RGDn_WORD2_M2UM.
+#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) //!< Bit mask for MPU_RGDn_WORD2_M2UM.
+#define BS_MPU_RGDn_WORD2_M2UM (3U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M2UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M2UM field.
+#define BR_MPU_RGDn_WORD2_M2UM(n) (HW_MPU_RGDn_WORD2(n).B.M2UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM.
+#define BF_MPU_RGDn_WORD2_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2UM), uint32_t) & BM_MPU_RGDn_WORD2_M2UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M2UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2UM) | BF_MPU_RGDn_WORD2_M2UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M2SM (15U)       //!< Bit position for MPU_RGDn_WORD2_M2SM.
+#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) //!< Bit mask for MPU_RGDn_WORD2_M2SM.
+#define BS_MPU_RGDn_WORD2_M2SM (2U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M2SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M2SM field.
+#define BR_MPU_RGDn_WORD2_M2SM(n) (HW_MPU_RGDn_WORD2(n).B.M2SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM.
+#define BF_MPU_RGDn_WORD2_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2SM), uint32_t) & BM_MPU_RGDn_WORD2_M2SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M2SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2SM) | BF_MPU_RGDn_WORD2_M2SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M2PE (17U)       //!< Bit position for MPU_RGDn_WORD2_M2PE.
+#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) //!< Bit mask for MPU_RGDn_WORD2_M2PE.
+#define BS_MPU_RGDn_WORD2_M2PE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M2PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M2PE field.
+#define BR_MPU_RGDn_WORD2_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE.
+#define BF_MPU_RGDn_WORD2_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2PE), uint32_t) & BM_MPU_RGDn_WORD2_M2PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0 - An attempted access of that mode may be terminated with an access error
+ *     (if not allowed by another descriptor) and the access not performed.
+ * - 1 - Allows the given access type to occur
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M3UM (18U)       //!< Bit position for MPU_RGDn_WORD2_M3UM.
+#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDn_WORD2_M3UM.
+#define BS_MPU_RGDn_WORD2_M3UM (3U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M3UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M3UM field.
+#define BR_MPU_RGDn_WORD2_M3UM(n) (HW_MPU_RGDn_WORD2(n).B.M3UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM.
+#define BF_MPU_RGDn_WORD2_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3UM), uint32_t) & BM_MPU_RGDn_WORD2_M3UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M3UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3UM) | BF_MPU_RGDn_WORD2_M3UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 00 - r/w/x; read, write and execute allowed
+ * - 01 - r/x; read and execute allowed, but no write
+ * - 10 - r/w; read and write allowed, but no execute
+ * - 11 - Same as User mode defined in M3UM
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M3SM (21U)       //!< Bit position for MPU_RGDn_WORD2_M3SM.
+#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) //!< Bit mask for MPU_RGDn_WORD2_M3SM.
+#define BS_MPU_RGDn_WORD2_M3SM (2U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M3SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M3SM field.
+#define BR_MPU_RGDn_WORD2_M3SM(n) (HW_MPU_RGDn_WORD2(n).B.M3SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM.
+#define BF_MPU_RGDn_WORD2_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3SM), uint32_t) & BM_MPU_RGDn_WORD2_M3SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M3SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3SM) | BF_MPU_RGDn_WORD2_M3SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the process identifier in the evaluation
+ * - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
+ *     evaluation
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M3PE (23U)       //!< Bit position for MPU_RGDn_WORD2_M3PE.
+#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) //!< Bit mask for MPU_RGDn_WORD2_M3PE.
+#define BS_MPU_RGDn_WORD2_M3PE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M3PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M3PE field.
+#define BR_MPU_RGDn_WORD2_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE.
+#define BF_MPU_RGDn_WORD2_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3PE), uint32_t) & BM_MPU_RGDn_WORD2_M3PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 4 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M4WE (24U)       //!< Bit position for MPU_RGDn_WORD2_M4WE.
+#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) //!< Bit mask for MPU_RGDn_WORD2_M4WE.
+#define BS_MPU_RGDn_WORD2_M4WE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M4WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M4WE field.
+#define BR_MPU_RGDn_WORD2_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE.
+#define BF_MPU_RGDn_WORD2_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4WE), uint32_t) & BM_MPU_RGDn_WORD2_M4WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 4 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M4RE (25U)       //!< Bit position for MPU_RGDn_WORD2_M4RE.
+#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) //!< Bit mask for MPU_RGDn_WORD2_M4RE.
+#define BS_MPU_RGDn_WORD2_M4RE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M4RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M4RE field.
+#define BR_MPU_RGDn_WORD2_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE.
+#define BF_MPU_RGDn_WORD2_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4RE), uint32_t) & BM_MPU_RGDn_WORD2_M4RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 5 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M5WE (26U)       //!< Bit position for MPU_RGDn_WORD2_M5WE.
+#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) //!< Bit mask for MPU_RGDn_WORD2_M5WE.
+#define BS_MPU_RGDn_WORD2_M5WE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M5WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M5WE field.
+#define BR_MPU_RGDn_WORD2_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE.
+#define BF_MPU_RGDn_WORD2_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5WE), uint32_t) & BM_MPU_RGDn_WORD2_M5WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 5 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M5RE (27U)       //!< Bit position for MPU_RGDn_WORD2_M5RE.
+#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) //!< Bit mask for MPU_RGDn_WORD2_M5RE.
+#define BS_MPU_RGDn_WORD2_M5RE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M5RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M5RE field.
+#define BR_MPU_RGDn_WORD2_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE.
+#define BF_MPU_RGDn_WORD2_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5RE), uint32_t) & BM_MPU_RGDn_WORD2_M5RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 6 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M6WE (28U)       //!< Bit position for MPU_RGDn_WORD2_M6WE.
+#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) //!< Bit mask for MPU_RGDn_WORD2_M6WE.
+#define BS_MPU_RGDn_WORD2_M6WE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M6WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M6WE field.
+#define BR_MPU_RGDn_WORD2_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE.
+#define BF_MPU_RGDn_WORD2_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6WE), uint32_t) & BM_MPU_RGDn_WORD2_M6WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 6 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M6RE (29U)       //!< Bit position for MPU_RGDn_WORD2_M6RE.
+#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) //!< Bit mask for MPU_RGDn_WORD2_M6RE.
+#define BS_MPU_RGDn_WORD2_M6RE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M6RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M6RE field.
+#define BR_MPU_RGDn_WORD2_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE.
+#define BF_MPU_RGDn_WORD2_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6RE), uint32_t) & BM_MPU_RGDn_WORD2_M6RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 7 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M7WE (30U)       //!< Bit position for MPU_RGDn_WORD2_M7WE.
+#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) //!< Bit mask for MPU_RGDn_WORD2_M7WE.
+#define BS_MPU_RGDn_WORD2_M7WE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M7WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M7WE field.
+#define BR_MPU_RGDn_WORD2_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE.
+#define BF_MPU_RGDn_WORD2_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7WE), uint32_t) & BM_MPU_RGDn_WORD2_M7WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 7 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M7RE (31U)       //!< Bit position for MPU_RGDn_WORD2_M7RE.
+#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) //!< Bit mask for MPU_RGDn_WORD2_M7RE.
+#define BS_MPU_RGDn_WORD2_M7RE (1U)        //!< Bit field size in bits for MPU_RGDn_WORD2_M7RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M7RE field.
+#define BR_MPU_RGDn_WORD2_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE.
+#define BF_MPU_RGDn_WORD2_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7RE), uint32_t) & BM_MPU_RGDn_WORD2_M7RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * The fourth word of the region descriptor contains the optional process
+ * identifier and mask, plus the region descriptor's valid bit.
+ */
+typedef union _hw_mpu_rgdn_word3
+{
+    uint32_t U;
+    struct _hw_mpu_rgdn_word3_bitfields
+    {
+        uint32_t VLD : 1;              //!< [0] Valid
+        uint32_t RESERVED0 : 15;       //!< [15:1]
+        uint32_t PIDMASK : 8;          //!< [23:16] Process Identifier Mask
+        uint32_t PID : 8;              //!< [31:24] Process Identifier
+    } B;
+} hw_mpu_rgdn_word3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD3 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD3_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD3_ADDR(n) (REGS_MPU_BASE + 0x40CU + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD3(n)     (*(__IO hw_mpu_rgdn_word3_t *) HW_MPU_RGDn_WORD3_ADDR(n))
+#define HW_MPU_RGDn_WORD3_RD(n)  (HW_MPU_RGDn_WORD3(n).U)
+#define HW_MPU_RGDn_WORD3_WR(n, v) (HW_MPU_RGDn_WORD3(n).U = (v))
+#define HW_MPU_RGDn_WORD3_SET(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) |  (v)))
+#define HW_MPU_RGDn_WORD3_CLR(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD3_TOG(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD3 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0 - Region descriptor is invalid
+ * - 1 - Region descriptor is valid
+ */
+//@{
+#define BP_MPU_RGDn_WORD3_VLD (0U)         //!< Bit position for MPU_RGDn_WORD3_VLD.
+#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) //!< Bit mask for MPU_RGDn_WORD3_VLD.
+#define BS_MPU_RGDn_WORD3_VLD (1U)         //!< Bit field size in bits for MPU_RGDn_WORD3_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD3_VLD field.
+#define BR_MPU_RGDn_WORD3_VLD(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD3_VLD.
+#define BF_MPU_RGDn_WORD3_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_VLD), uint32_t) & BM_MPU_RGDn_WORD3_VLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VLD field to a new value.
+#define BW_MPU_RGDn_WORD3_VLD(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+//@{
+#define BP_MPU_RGDn_WORD3_PIDMASK (16U)    //!< Bit position for MPU_RGDn_WORD3_PIDMASK.
+#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) //!< Bit mask for MPU_RGDn_WORD3_PIDMASK.
+#define BS_MPU_RGDn_WORD3_PIDMASK (8U)     //!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field.
+#define BR_MPU_RGDn_WORD3_PIDMASK(n) (HW_MPU_RGDn_WORD3(n).B.PIDMASK)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK.
+#define BF_MPU_RGDn_WORD3_PIDMASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PIDMASK), uint32_t) & BM_MPU_RGDn_WORD3_PIDMASK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIDMASK field to a new value.
+#define BW_MPU_RGDn_WORD3_PIDMASK(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PIDMASK) | BF_MPU_RGDn_WORD3_PIDMASK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+//@{
+#define BP_MPU_RGDn_WORD3_PID (24U)        //!< Bit position for MPU_RGDn_WORD3_PID.
+#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) //!< Bit mask for MPU_RGDn_WORD3_PID.
+#define BS_MPU_RGDn_WORD3_PID (8U)         //!< Bit field size in bits for MPU_RGDn_WORD3_PID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD3_PID field.
+#define BR_MPU_RGDn_WORD3_PID(n) (HW_MPU_RGDn_WORD3(n).B.PID)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD3_PID.
+#define BF_MPU_RGDn_WORD3_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PID), uint32_t) & BM_MPU_RGDn_WORD3_PID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PID field to a new value.
+#define BW_MPU_RGDn_WORD3_PID(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PID) | BF_MPU_RGDn_WORD3_PID(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+typedef union _hw_mpu_rgdaacn
+{
+    uint32_t U;
+    struct _hw_mpu_rgdaacn_bitfields
+    {
+        uint32_t M0UM : 3;             //!< [2:0] Bus Master 0 User Mode Access Control
+        uint32_t M0SM : 2;             //!< [4:3] Bus Master 0 Supervisor Mode Access
+                                       //! Control
+        uint32_t M0PE : 1;             //!< [5] Bus Master 0 Process Identifier Enable
+        uint32_t M1UM : 3;             //!< [8:6] Bus Master 1 User Mode Access Control
+        uint32_t M1SM : 2;             //!< [10:9] Bus Master 1 Supervisor Mode Access
+                                       //! Control
+        uint32_t M1PE : 1;             //!< [11] Bus Master 1 Process Identifier Enable
+        uint32_t M2UM : 3;             //!< [14:12] Bus Master 2 User Mode Access Control
+        uint32_t M2SM : 2;             //!< [16:15] Bus Master 2 Supervisor Mode Access
+                                       //! Control
+        uint32_t M2PE : 1;             //!< [17] Bus Master 2 Process Identifier Enable
+        uint32_t M3UM : 3;             //!< [20:18] Bus Master 3 User Mode Access Control
+        uint32_t M3SM : 2;             //!< [22:21] Bus Master 3 Supervisor Mode Access
+                                       //! Control
+        uint32_t M3PE : 1;             //!< [23] Bus Master 3 Process Identifier Enable
+        uint32_t M4WE : 1;             //!< [24] Bus Master 4 Write Enable
+        uint32_t M4RE : 1;             //!< [25] Bus Master 4 Read Enable
+        uint32_t M5WE : 1;             //!< [26] Bus Master 5 Write Enable
+        uint32_t M5RE : 1;             //!< [27] Bus Master 5 Read Enable
+        uint32_t M6WE : 1;             //!< [28] Bus Master 6 Write Enable
+        uint32_t M6RE : 1;             //!< [29] Bus Master 6 Read Enable
+        uint32_t M7WE : 1;             //!< [30] Bus Master 7 Write Enable
+        uint32_t M7RE : 1;             //!< [31] Bus Master 7 Read Enable
+    } B;
+} hw_mpu_rgdaacn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDAACn register
+ */
+//@{
+#define HW_MPU_RGDAACn_COUNT (12U)
+
+#define HW_MPU_RGDAACn_ADDR(n)   (REGS_MPU_BASE + 0x800U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDAACn(n)        (*(__IO hw_mpu_rgdaacn_t *) HW_MPU_RGDAACn_ADDR(n))
+#define HW_MPU_RGDAACn_RD(n)     (HW_MPU_RGDAACn(n).U)
+#define HW_MPU_RGDAACn_WR(n, v)  (HW_MPU_RGDAACn(n).U = (v))
+#define HW_MPU_RGDAACn_SET(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) |  (v)))
+#define HW_MPU_RGDAACn_CLR(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) & ~(v)))
+#define HW_MPU_RGDAACn_TOG(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDAACn bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M0UM  (0U)          //!< Bit position for MPU_RGDAACn_M0UM.
+#define BM_MPU_RGDAACn_M0UM  (0x00000007U) //!< Bit mask for MPU_RGDAACn_M0UM.
+#define BS_MPU_RGDAACn_M0UM  (3U)          //!< Bit field size in bits for MPU_RGDAACn_M0UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M0UM field.
+#define BR_MPU_RGDAACn_M0UM(n) (HW_MPU_RGDAACn(n).B.M0UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M0UM.
+#define BF_MPU_RGDAACn_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0UM), uint32_t) & BM_MPU_RGDAACn_M0UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0UM field to a new value.
+#define BW_MPU_RGDAACn_M0UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0UM) | BF_MPU_RGDAACn_M0UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M0SM  (3U)          //!< Bit position for MPU_RGDAACn_M0SM.
+#define BM_MPU_RGDAACn_M0SM  (0x00000018U) //!< Bit mask for MPU_RGDAACn_M0SM.
+#define BS_MPU_RGDAACn_M0SM  (2U)          //!< Bit field size in bits for MPU_RGDAACn_M0SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M0SM field.
+#define BR_MPU_RGDAACn_M0SM(n) (HW_MPU_RGDAACn(n).B.M0SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M0SM.
+#define BF_MPU_RGDAACn_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0SM), uint32_t) & BM_MPU_RGDAACn_M0SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0SM field to a new value.
+#define BW_MPU_RGDAACn_M0SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0SM) | BF_MPU_RGDAACn_M0SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M0PE  (5U)          //!< Bit position for MPU_RGDAACn_M0PE.
+#define BM_MPU_RGDAACn_M0PE  (0x00000020U) //!< Bit mask for MPU_RGDAACn_M0PE.
+#define BS_MPU_RGDAACn_M0PE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M0PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M0PE field.
+#define BR_MPU_RGDAACn_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M0PE.
+#define BF_MPU_RGDAACn_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0PE), uint32_t) & BM_MPU_RGDAACn_M0PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0PE field to a new value.
+#define BW_MPU_RGDAACn_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M1UM  (6U)          //!< Bit position for MPU_RGDAACn_M1UM.
+#define BM_MPU_RGDAACn_M1UM  (0x000001C0U) //!< Bit mask for MPU_RGDAACn_M1UM.
+#define BS_MPU_RGDAACn_M1UM  (3U)          //!< Bit field size in bits for MPU_RGDAACn_M1UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M1UM field.
+#define BR_MPU_RGDAACn_M1UM(n) (HW_MPU_RGDAACn(n).B.M1UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M1UM.
+#define BF_MPU_RGDAACn_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1UM), uint32_t) & BM_MPU_RGDAACn_M1UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1UM field to a new value.
+#define BW_MPU_RGDAACn_M1UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1UM) | BF_MPU_RGDAACn_M1UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M1SM  (9U)          //!< Bit position for MPU_RGDAACn_M1SM.
+#define BM_MPU_RGDAACn_M1SM  (0x00000600U) //!< Bit mask for MPU_RGDAACn_M1SM.
+#define BS_MPU_RGDAACn_M1SM  (2U)          //!< Bit field size in bits for MPU_RGDAACn_M1SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M1SM field.
+#define BR_MPU_RGDAACn_M1SM(n) (HW_MPU_RGDAACn(n).B.M1SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M1SM.
+#define BF_MPU_RGDAACn_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1SM), uint32_t) & BM_MPU_RGDAACn_M1SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1SM field to a new value.
+#define BW_MPU_RGDAACn_M1SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1SM) | BF_MPU_RGDAACn_M1SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M1PE  (11U)         //!< Bit position for MPU_RGDAACn_M1PE.
+#define BM_MPU_RGDAACn_M1PE  (0x00000800U) //!< Bit mask for MPU_RGDAACn_M1PE.
+#define BS_MPU_RGDAACn_M1PE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M1PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M1PE field.
+#define BR_MPU_RGDAACn_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M1PE.
+#define BF_MPU_RGDAACn_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1PE), uint32_t) & BM_MPU_RGDAACn_M1PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1PE field to a new value.
+#define BW_MPU_RGDAACn_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M2UM  (12U)         //!< Bit position for MPU_RGDAACn_M2UM.
+#define BM_MPU_RGDAACn_M2UM  (0x00007000U) //!< Bit mask for MPU_RGDAACn_M2UM.
+#define BS_MPU_RGDAACn_M2UM  (3U)          //!< Bit field size in bits for MPU_RGDAACn_M2UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M2UM field.
+#define BR_MPU_RGDAACn_M2UM(n) (HW_MPU_RGDAACn(n).B.M2UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M2UM.
+#define BF_MPU_RGDAACn_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2UM), uint32_t) & BM_MPU_RGDAACn_M2UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2UM field to a new value.
+#define BW_MPU_RGDAACn_M2UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2UM) | BF_MPU_RGDAACn_M2UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M2SM  (15U)         //!< Bit position for MPU_RGDAACn_M2SM.
+#define BM_MPU_RGDAACn_M2SM  (0x00018000U) //!< Bit mask for MPU_RGDAACn_M2SM.
+#define BS_MPU_RGDAACn_M2SM  (2U)          //!< Bit field size in bits for MPU_RGDAACn_M2SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M2SM field.
+#define BR_MPU_RGDAACn_M2SM(n) (HW_MPU_RGDAACn(n).B.M2SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M2SM.
+#define BF_MPU_RGDAACn_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2SM), uint32_t) & BM_MPU_RGDAACn_M2SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2SM field to a new value.
+#define BW_MPU_RGDAACn_M2SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2SM) | BF_MPU_RGDAACn_M2SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M2PE  (17U)         //!< Bit position for MPU_RGDAACn_M2PE.
+#define BM_MPU_RGDAACn_M2PE  (0x00020000U) //!< Bit mask for MPU_RGDAACn_M2PE.
+#define BS_MPU_RGDAACn_M2PE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M2PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M2PE field.
+#define BR_MPU_RGDAACn_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M2PE.
+#define BF_MPU_RGDAACn_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2PE), uint32_t) & BM_MPU_RGDAACn_M2PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2PE field to a new value.
+#define BW_MPU_RGDAACn_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0 - An attempted access of that mode may be terminated with an access error
+ *     (if not allowed by another descriptor) and the access not performed.
+ * - 1 - Allows the given access type to occur
+ */
+//@{
+#define BP_MPU_RGDAACn_M3UM  (18U)         //!< Bit position for MPU_RGDAACn_M3UM.
+#define BM_MPU_RGDAACn_M3UM  (0x001C0000U) //!< Bit mask for MPU_RGDAACn_M3UM.
+#define BS_MPU_RGDAACn_M3UM  (3U)          //!< Bit field size in bits for MPU_RGDAACn_M3UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M3UM field.
+#define BR_MPU_RGDAACn_M3UM(n) (HW_MPU_RGDAACn(n).B.M3UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M3UM.
+#define BF_MPU_RGDAACn_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3UM), uint32_t) & BM_MPU_RGDAACn_M3UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3UM field to a new value.
+#define BW_MPU_RGDAACn_M3UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3UM) | BF_MPU_RGDAACn_M3UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 00 - r/w/x; read, write and execute allowed
+ * - 01 - r/x; read and execute allowed, but no write
+ * - 10 - r/w; read and write allowed, but no execute
+ * - 11 - Same as User mode defined in M3UM
+ */
+//@{
+#define BP_MPU_RGDAACn_M3SM  (21U)         //!< Bit position for MPU_RGDAACn_M3SM.
+#define BM_MPU_RGDAACn_M3SM  (0x00600000U) //!< Bit mask for MPU_RGDAACn_M3SM.
+#define BS_MPU_RGDAACn_M3SM  (2U)          //!< Bit field size in bits for MPU_RGDAACn_M3SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M3SM field.
+#define BR_MPU_RGDAACn_M3SM(n) (HW_MPU_RGDAACn(n).B.M3SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M3SM.
+#define BF_MPU_RGDAACn_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3SM), uint32_t) & BM_MPU_RGDAACn_M3SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3SM field to a new value.
+#define BW_MPU_RGDAACn_M3SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3SM) | BF_MPU_RGDAACn_M3SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the process identifier in the evaluation
+ * - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
+ *     evaluation
+ */
+//@{
+#define BP_MPU_RGDAACn_M3PE  (23U)         //!< Bit position for MPU_RGDAACn_M3PE.
+#define BM_MPU_RGDAACn_M3PE  (0x00800000U) //!< Bit mask for MPU_RGDAACn_M3PE.
+#define BS_MPU_RGDAACn_M3PE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M3PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M3PE field.
+#define BR_MPU_RGDAACn_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M3PE.
+#define BF_MPU_RGDAACn_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3PE), uint32_t) & BM_MPU_RGDAACn_M3PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3PE field to a new value.
+#define BW_MPU_RGDAACn_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 4 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M4WE  (24U)         //!< Bit position for MPU_RGDAACn_M4WE.
+#define BM_MPU_RGDAACn_M4WE  (0x01000000U) //!< Bit mask for MPU_RGDAACn_M4WE.
+#define BS_MPU_RGDAACn_M4WE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M4WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M4WE field.
+#define BR_MPU_RGDAACn_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M4WE.
+#define BF_MPU_RGDAACn_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4WE), uint32_t) & BM_MPU_RGDAACn_M4WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4WE field to a new value.
+#define BW_MPU_RGDAACn_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 4 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M4RE  (25U)         //!< Bit position for MPU_RGDAACn_M4RE.
+#define BM_MPU_RGDAACn_M4RE  (0x02000000U) //!< Bit mask for MPU_RGDAACn_M4RE.
+#define BS_MPU_RGDAACn_M4RE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M4RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M4RE field.
+#define BR_MPU_RGDAACn_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M4RE.
+#define BF_MPU_RGDAACn_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4RE), uint32_t) & BM_MPU_RGDAACn_M4RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4RE field to a new value.
+#define BW_MPU_RGDAACn_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 5 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M5WE  (26U)         //!< Bit position for MPU_RGDAACn_M5WE.
+#define BM_MPU_RGDAACn_M5WE  (0x04000000U) //!< Bit mask for MPU_RGDAACn_M5WE.
+#define BS_MPU_RGDAACn_M5WE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M5WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M5WE field.
+#define BR_MPU_RGDAACn_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M5WE.
+#define BF_MPU_RGDAACn_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5WE), uint32_t) & BM_MPU_RGDAACn_M5WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5WE field to a new value.
+#define BW_MPU_RGDAACn_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 5 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M5RE  (27U)         //!< Bit position for MPU_RGDAACn_M5RE.
+#define BM_MPU_RGDAACn_M5RE  (0x08000000U) //!< Bit mask for MPU_RGDAACn_M5RE.
+#define BS_MPU_RGDAACn_M5RE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M5RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M5RE field.
+#define BR_MPU_RGDAACn_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M5RE.
+#define BF_MPU_RGDAACn_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5RE), uint32_t) & BM_MPU_RGDAACn_M5RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5RE field to a new value.
+#define BW_MPU_RGDAACn_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 6 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M6WE  (28U)         //!< Bit position for MPU_RGDAACn_M6WE.
+#define BM_MPU_RGDAACn_M6WE  (0x10000000U) //!< Bit mask for MPU_RGDAACn_M6WE.
+#define BS_MPU_RGDAACn_M6WE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M6WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M6WE field.
+#define BR_MPU_RGDAACn_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M6WE.
+#define BF_MPU_RGDAACn_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6WE), uint32_t) & BM_MPU_RGDAACn_M6WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6WE field to a new value.
+#define BW_MPU_RGDAACn_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 6 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M6RE  (29U)         //!< Bit position for MPU_RGDAACn_M6RE.
+#define BM_MPU_RGDAACn_M6RE  (0x20000000U) //!< Bit mask for MPU_RGDAACn_M6RE.
+#define BS_MPU_RGDAACn_M6RE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M6RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M6RE field.
+#define BR_MPU_RGDAACn_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M6RE.
+#define BF_MPU_RGDAACn_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6RE), uint32_t) & BM_MPU_RGDAACn_M6RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6RE field to a new value.
+#define BW_MPU_RGDAACn_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 writes terminate with an access error and the write is not
+ *     performed
+ * - 1 - Bus master 7 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M7WE  (30U)         //!< Bit position for MPU_RGDAACn_M7WE.
+#define BM_MPU_RGDAACn_M7WE  (0x40000000U) //!< Bit mask for MPU_RGDAACn_M7WE.
+#define BS_MPU_RGDAACn_M7WE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M7WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M7WE field.
+#define BR_MPU_RGDAACn_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M7WE.
+#define BF_MPU_RGDAACn_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7WE), uint32_t) & BM_MPU_RGDAACn_M7WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7WE field to a new value.
+#define BW_MPU_RGDAACn_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 1 - Bus master 7 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M7RE  (31U)         //!< Bit position for MPU_RGDAACn_M7RE.
+#define BM_MPU_RGDAACn_M7RE  (0x80000000U) //!< Bit mask for MPU_RGDAACn_M7RE.
+#define BS_MPU_RGDAACn_M7RE  (1U)          //!< Bit field size in bits for MPU_RGDAACn_M7RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M7RE field.
+#define BR_MPU_RGDAACn_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M7RE.
+#define BF_MPU_RGDAACn_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7RE), uint32_t) & BM_MPU_RGDAACn_M7RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7RE field to a new value.
+#define BW_MPU_RGDAACn_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_mpu_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All MPU module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_mpu
+{
+    __IO hw_mpu_cesr_t CESR;               //!< [0x0] Control/Error Status Register
+    uint8_t _reserved0[12];
+    struct {
+        __I hw_mpu_earn_t EARn;            //!< [0x10] Error Address Register, slave port n
+        __I hw_mpu_edrn_t EDRn;            //!< [0x14] Error Detail Register, slave port n
+    } SP[5];
+    uint8_t _reserved1[968];
+    struct {
+        __IO hw_mpu_rgdn_word0_t RGDn_WORD0; //!< [0x400] Region Descriptor n, Word 0
+        __IO hw_mpu_rgdn_word1_t RGDn_WORD1; //!< [0x404] Region Descriptor n, Word 1
+        __IO hw_mpu_rgdn_word2_t RGDn_WORD2; //!< [0x408] Region Descriptor n, Word 2
+        __IO hw_mpu_rgdn_word3_t RGDn_WORD3; //!< [0x40C] Region Descriptor n, Word 3
+    } RGD[12];
+    uint8_t _reserved2[832];
+    __IO hw_mpu_rgdaacn_t RGDAACn[12];     //!< [0x800] Region Descriptor Alternate Access Control n
+} hw_mpu_t;
+#pragma pack()
+
+//! @brief Macro to access all MPU registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_MPU</code>.
+#define HW_MPU         (*(hw_mpu_t *) REGS_MPU_BASE)
+#endif
+
+#endif // __HW_MPU_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h
new file mode 100644
index 0000000000..d8c25337a2
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h
@@ -0,0 +1,958 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_NV_REGISTERS_H__
+#define __HW_NV_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - HW_NV_FSEC - Non-volatile Flash Security Register
+ * - HW_NV_FOPT - Non-volatile Flash Option Register
+ * - HW_NV_FEPROT - Non-volatile EERAM Protection Register
+ * - HW_NV_FDPROT - Non-volatile D-Flash Protection Register
+ *
+ * - hw_nv_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_NV_BASE
+#define HW_NV_INSTANCE_COUNT (1U) //!< Number of instances of the NV module.
+#define REGS_NV_BASE (0x400U) //!< Base address for FTFE_FlashConfig.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey3
+{
+    uint8_t U;
+    struct _hw_nv_backkey3_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+//@{
+#define HW_NV_BACKKEY3_ADDR      (REGS_NV_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY3           (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR)
+#define HW_NV_BACKKEY3_RD()      (HW_NV_BACKKEY3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY3 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY3, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY3_KEY   (0U)          //!< Bit position for NV_BACKKEY3_KEY.
+#define BM_NV_BACKKEY3_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY3_KEY.
+#define BS_NV_BACKKEY3_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY3_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY3_KEY field.
+#define BR_NV_BACKKEY3_KEY   (HW_NV_BACKKEY3.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey2
+{
+    uint8_t U;
+    struct _hw_nv_backkey2_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+//@{
+#define HW_NV_BACKKEY2_ADDR      (REGS_NV_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY2           (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR)
+#define HW_NV_BACKKEY2_RD()      (HW_NV_BACKKEY2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY2 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY2, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY2_KEY   (0U)          //!< Bit position for NV_BACKKEY2_KEY.
+#define BM_NV_BACKKEY2_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY2_KEY.
+#define BS_NV_BACKKEY2_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY2_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY2_KEY field.
+#define BR_NV_BACKKEY2_KEY   (HW_NV_BACKKEY2.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey1
+{
+    uint8_t U;
+    struct _hw_nv_backkey1_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+//@{
+#define HW_NV_BACKKEY1_ADDR      (REGS_NV_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY1           (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR)
+#define HW_NV_BACKKEY1_RD()      (HW_NV_BACKKEY1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY1 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY1, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY1_KEY   (0U)          //!< Bit position for NV_BACKKEY1_KEY.
+#define BM_NV_BACKKEY1_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY1_KEY.
+#define BS_NV_BACKKEY1_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY1_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY1_KEY field.
+#define BR_NV_BACKKEY1_KEY   (HW_NV_BACKKEY1.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey0
+{
+    uint8_t U;
+    struct _hw_nv_backkey0_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+//@{
+#define HW_NV_BACKKEY0_ADDR      (REGS_NV_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY0           (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR)
+#define HW_NV_BACKKEY0_RD()      (HW_NV_BACKKEY0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY0 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY0, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY0_KEY   (0U)          //!< Bit position for NV_BACKKEY0_KEY.
+#define BM_NV_BACKKEY0_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY0_KEY.
+#define BS_NV_BACKKEY0_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY0_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY0_KEY field.
+#define BR_NV_BACKKEY0_KEY   (HW_NV_BACKKEY0.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey7
+{
+    uint8_t U;
+    struct _hw_nv_backkey7_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+//@{
+#define HW_NV_BACKKEY7_ADDR      (REGS_NV_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY7           (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR)
+#define HW_NV_BACKKEY7_RD()      (HW_NV_BACKKEY7.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY7 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY7, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY7_KEY   (0U)          //!< Bit position for NV_BACKKEY7_KEY.
+#define BM_NV_BACKKEY7_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY7_KEY.
+#define BS_NV_BACKKEY7_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY7_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY7_KEY field.
+#define BR_NV_BACKKEY7_KEY   (HW_NV_BACKKEY7.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey6
+{
+    uint8_t U;
+    struct _hw_nv_backkey6_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+//@{
+#define HW_NV_BACKKEY6_ADDR      (REGS_NV_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY6           (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR)
+#define HW_NV_BACKKEY6_RD()      (HW_NV_BACKKEY6.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY6 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY6, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY6_KEY   (0U)          //!< Bit position for NV_BACKKEY6_KEY.
+#define BM_NV_BACKKEY6_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY6_KEY.
+#define BS_NV_BACKKEY6_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY6_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY6_KEY field.
+#define BR_NV_BACKKEY6_KEY   (HW_NV_BACKKEY6.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey5
+{
+    uint8_t U;
+    struct _hw_nv_backkey5_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+//@{
+#define HW_NV_BACKKEY5_ADDR      (REGS_NV_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY5           (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR)
+#define HW_NV_BACKKEY5_RD()      (HW_NV_BACKKEY5.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY5 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY5, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY5_KEY   (0U)          //!< Bit position for NV_BACKKEY5_KEY.
+#define BM_NV_BACKKEY5_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY5_KEY.
+#define BS_NV_BACKKEY5_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY5_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY5_KEY field.
+#define BR_NV_BACKKEY5_KEY   (HW_NV_BACKKEY5.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey4
+{
+    uint8_t U;
+    struct _hw_nv_backkey4_bitfields
+    {
+        uint8_t KEY : 8;               //!< [7:0] Backdoor Comparison Key.
+    } B;
+} hw_nv_backkey4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+//@{
+#define HW_NV_BACKKEY4_ADDR      (REGS_NV_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY4           (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR)
+#define HW_NV_BACKKEY4_RD()      (HW_NV_BACKKEY4.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY4 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY4, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY4_KEY   (0U)          //!< Bit position for NV_BACKKEY4_KEY.
+#define BM_NV_BACKKEY4_KEY   (0xFFU)       //!< Bit mask for NV_BACKKEY4_KEY.
+#define BS_NV_BACKKEY4_KEY   (8U)          //!< Bit field size in bits for NV_BACKKEY4_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY4_KEY field.
+#define BR_NV_BACKKEY4_KEY   (HW_NV_BACKKEY4.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot3
+{
+    uint8_t U;
+    struct _hw_nv_fprot3_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] P-Flash Region Protect
+    } B;
+} hw_nv_fprot3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+//@{
+#define HW_NV_FPROT3_ADDR        (REGS_NV_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT3             (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR)
+#define HW_NV_FPROT3_RD()        (HW_NV_FPROT3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT3 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT3, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT3_PROT    (0U)          //!< Bit position for NV_FPROT3_PROT.
+#define BM_NV_FPROT3_PROT    (0xFFU)       //!< Bit mask for NV_FPROT3_PROT.
+#define BS_NV_FPROT3_PROT    (8U)          //!< Bit field size in bits for NV_FPROT3_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT3_PROT field.
+#define BR_NV_FPROT3_PROT    (HW_NV_FPROT3.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot2
+{
+    uint8_t U;
+    struct _hw_nv_fprot2_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] P-Flash Region Protect
+    } B;
+} hw_nv_fprot2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+//@{
+#define HW_NV_FPROT2_ADDR        (REGS_NV_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT2             (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR)
+#define HW_NV_FPROT2_RD()        (HW_NV_FPROT2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT2 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT2, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT2_PROT    (0U)          //!< Bit position for NV_FPROT2_PROT.
+#define BM_NV_FPROT2_PROT    (0xFFU)       //!< Bit mask for NV_FPROT2_PROT.
+#define BS_NV_FPROT2_PROT    (8U)          //!< Bit field size in bits for NV_FPROT2_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT2_PROT field.
+#define BR_NV_FPROT2_PROT    (HW_NV_FPROT2.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot1
+{
+    uint8_t U;
+    struct _hw_nv_fprot1_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] P-Flash Region Protect
+    } B;
+} hw_nv_fprot1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+//@{
+#define HW_NV_FPROT1_ADDR        (REGS_NV_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT1             (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR)
+#define HW_NV_FPROT1_RD()        (HW_NV_FPROT1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT1 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT1, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT1_PROT    (0U)          //!< Bit position for NV_FPROT1_PROT.
+#define BM_NV_FPROT1_PROT    (0xFFU)       //!< Bit mask for NV_FPROT1_PROT.
+#define BS_NV_FPROT1_PROT    (8U)          //!< Bit field size in bits for NV_FPROT1_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT1_PROT field.
+#define BR_NV_FPROT1_PROT    (HW_NV_FPROT1.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot0
+{
+    uint8_t U;
+    struct _hw_nv_fprot0_bitfields
+    {
+        uint8_t PROT : 8;              //!< [7:0] P-Flash Region Protect
+    } B;
+} hw_nv_fprot0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+//@{
+#define HW_NV_FPROT0_ADDR        (REGS_NV_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT0             (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR)
+#define HW_NV_FPROT0_RD()        (HW_NV_FPROT0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT0 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT0, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT0_PROT    (0U)          //!< Bit position for NV_FPROT0_PROT.
+#define BM_NV_FPROT0_PROT    (0xFFU)       //!< Bit mask for NV_FPROT0_PROT.
+#define BS_NV_FPROT0_PROT    (8U)          //!< Bit field size in bits for NV_FPROT0_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT0_PROT field.
+#define BR_NV_FPROT0_PROT    (HW_NV_FPROT0.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FSEC - Non-volatile Flash Security Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fsec
+{
+    uint8_t U;
+    struct _hw_nv_fsec_bitfields
+    {
+        uint8_t SEC : 2;               //!< [1:0] Flash Security
+        uint8_t FSLACC : 2;            //!< [3:2] Freescale Failure Analysis Access Code
+        uint8_t MEEN : 2;              //!< [5:4]
+        uint8_t KEYEN : 2;             //!< [7:6] Backdoor Key Security Enable
+    } B;
+} hw_nv_fsec_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+//@{
+#define HW_NV_FSEC_ADDR          (REGS_NV_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FSEC               (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR)
+#define HW_NV_FSEC_RD()          (HW_NV_FSEC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ */
+//@{
+#define BP_NV_FSEC_SEC       (0U)          //!< Bit position for NV_FSEC_SEC.
+#define BM_NV_FSEC_SEC       (0x03U)       //!< Bit mask for NV_FSEC_SEC.
+#define BS_NV_FSEC_SEC       (2U)          //!< Bit field size in bits for NV_FSEC_SEC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_SEC field.
+#define BR_NV_FSEC_SEC       (HW_NV_FSEC.B.SEC)
+#endif
+//@}
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ */
+//@{
+#define BP_NV_FSEC_FSLACC    (2U)          //!< Bit position for NV_FSEC_FSLACC.
+#define BM_NV_FSEC_FSLACC    (0x0CU)       //!< Bit mask for NV_FSEC_FSLACC.
+#define BS_NV_FSEC_FSLACC    (2U)          //!< Bit field size in bits for NV_FSEC_FSLACC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_FSLACC field.
+#define BR_NV_FSEC_FSLACC    (HW_NV_FSEC.B.FSLACC)
+#endif
+//@}
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ */
+//@{
+#define BP_NV_FSEC_MEEN      (4U)          //!< Bit position for NV_FSEC_MEEN.
+#define BM_NV_FSEC_MEEN      (0x30U)       //!< Bit mask for NV_FSEC_MEEN.
+#define BS_NV_FSEC_MEEN      (2U)          //!< Bit field size in bits for NV_FSEC_MEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_MEEN field.
+#define BR_NV_FSEC_MEEN      (HW_NV_FSEC.B.MEEN)
+#endif
+//@}
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ */
+//@{
+#define BP_NV_FSEC_KEYEN     (6U)          //!< Bit position for NV_FSEC_KEYEN.
+#define BM_NV_FSEC_KEYEN     (0xC0U)       //!< Bit mask for NV_FSEC_KEYEN.
+#define BS_NV_FSEC_KEYEN     (2U)          //!< Bit field size in bits for NV_FSEC_KEYEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_KEYEN field.
+#define BR_NV_FSEC_KEYEN     (HW_NV_FSEC.B.KEYEN)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FOPT - Non-volatile Flash Option Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fopt
+{
+    uint8_t U;
+    struct _hw_nv_fopt_bitfields
+    {
+        uint8_t LPBOOT : 1;            //!< [0]
+        uint8_t EZPORT_DIS : 1;        //!< [1]
+        uint8_t RESERVED0 : 6;         //!< [7:2]
+    } B;
+} hw_nv_fopt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+//@{
+#define HW_NV_FOPT_ADDR          (REGS_NV_BASE + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FOPT               (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR)
+#define HW_NV_FOPT_RD()          (HW_NV_FOPT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ */
+//@{
+#define BP_NV_FOPT_LPBOOT    (0U)          //!< Bit position for NV_FOPT_LPBOOT.
+#define BM_NV_FOPT_LPBOOT    (0x01U)       //!< Bit mask for NV_FOPT_LPBOOT.
+#define BS_NV_FOPT_LPBOOT    (1U)          //!< Bit field size in bits for NV_FOPT_LPBOOT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FOPT_LPBOOT field.
+#define BR_NV_FOPT_LPBOOT    (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_LPBOOT))
+#endif
+//@}
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ */
+//@{
+#define BP_NV_FOPT_EZPORT_DIS (1U)         //!< Bit position for NV_FOPT_EZPORT_DIS.
+#define BM_NV_FOPT_EZPORT_DIS (0x02U)      //!< Bit mask for NV_FOPT_EZPORT_DIS.
+#define BS_NV_FOPT_EZPORT_DIS (1U)         //!< Bit field size in bits for NV_FOPT_EZPORT_DIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FOPT_EZPORT_DIS field.
+#define BR_NV_FOPT_EZPORT_DIS (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_EZPORT_DIS))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FEPROT - Non-volatile EERAM Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_feprot
+{
+    uint8_t U;
+    struct _hw_nv_feprot_bitfields
+    {
+        uint8_t EPROT : 8;             //!< [7:0]
+    } B;
+} hw_nv_feprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+//@{
+#define HW_NV_FEPROT_ADDR        (REGS_NV_BASE + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FEPROT             (*(__I hw_nv_feprot_t *) HW_NV_FEPROT_ADDR)
+#define HW_NV_FEPROT_RD()        (HW_NV_FEPROT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FEPROT bitfields
+ */
+
+/*!
+ * @name Register NV_FEPROT, field EPROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FEPROT_EPROT   (0U)          //!< Bit position for NV_FEPROT_EPROT.
+#define BM_NV_FEPROT_EPROT   (0xFFU)       //!< Bit mask for NV_FEPROT_EPROT.
+#define BS_NV_FEPROT_EPROT   (8U)          //!< Bit field size in bits for NV_FEPROT_EPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FEPROT_EPROT field.
+#define BR_NV_FEPROT_EPROT   (HW_NV_FEPROT.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FDPROT - Non-volatile D-Flash Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fdprot
+{
+    uint8_t U;
+    struct _hw_nv_fdprot_bitfields
+    {
+        uint8_t DPROT : 8;             //!< [7:0] D-Flash Region Protect
+    } B;
+} hw_nv_fdprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+//@{
+#define HW_NV_FDPROT_ADDR        (REGS_NV_BASE + 0xFU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FDPROT             (*(__I hw_nv_fdprot_t *) HW_NV_FDPROT_ADDR)
+#define HW_NV_FDPROT_RD()        (HW_NV_FDPROT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FDPROT bitfields
+ */
+
+/*!
+ * @name Register NV_FDPROT, field DPROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FDPROT_DPROT   (0U)          //!< Bit position for NV_FDPROT_DPROT.
+#define BM_NV_FDPROT_DPROT   (0xFFU)       //!< Bit mask for NV_FDPROT_DPROT.
+#define BS_NV_FDPROT_DPROT   (8U)          //!< Bit field size in bits for NV_FDPROT_DPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FDPROT_DPROT field.
+#define BR_NV_FDPROT_DPROT   (HW_NV_FDPROT.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_nv_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All NV module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_nv
+{
+    __I hw_nv_backkey3_t BACKKEY3;         //!< [0x0] Backdoor Comparison Key 3.
+    __I hw_nv_backkey2_t BACKKEY2;         //!< [0x1] Backdoor Comparison Key 2.
+    __I hw_nv_backkey1_t BACKKEY1;         //!< [0x2] Backdoor Comparison Key 1.
+    __I hw_nv_backkey0_t BACKKEY0;         //!< [0x3] Backdoor Comparison Key 0.
+    __I hw_nv_backkey7_t BACKKEY7;         //!< [0x4] Backdoor Comparison Key 7.
+    __I hw_nv_backkey6_t BACKKEY6;         //!< [0x5] Backdoor Comparison Key 6.
+    __I hw_nv_backkey5_t BACKKEY5;         //!< [0x6] Backdoor Comparison Key 5.
+    __I hw_nv_backkey4_t BACKKEY4;         //!< [0x7] Backdoor Comparison Key 4.
+    __I hw_nv_fprot3_t FPROT3;             //!< [0x8] Non-volatile P-Flash Protection 1 - Low Register
+    __I hw_nv_fprot2_t FPROT2;             //!< [0x9] Non-volatile P-Flash Protection 1 - High Register
+    __I hw_nv_fprot1_t FPROT1;             //!< [0xA] Non-volatile P-Flash Protection 0 - Low Register
+    __I hw_nv_fprot0_t FPROT0;             //!< [0xB] Non-volatile P-Flash Protection 0 - High Register
+    __I hw_nv_fsec_t FSEC;                 //!< [0xC] Non-volatile Flash Security Register
+    __I hw_nv_fopt_t FOPT;                 //!< [0xD] Non-volatile Flash Option Register
+    __I hw_nv_feprot_t FEPROT;             //!< [0xE] Non-volatile EERAM Protection Register
+    __I hw_nv_fdprot_t FDPROT;             //!< [0xF] Non-volatile D-Flash Protection Register
+} hw_nv_t;
+#pragma pack()
+
+//! @brief Macro to access all NV registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_NV</code>.
+#define HW_NV          (*(hw_nv_t *) REGS_NV_BASE)
+#endif
+
+#endif // __HW_NV_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h
new file mode 100644
index 0000000000..84176d135f
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_OSC_REGISTERS_H__
+#define __HW_OSC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - HW_OSC_CR - OSC Control Register
+ *
+ * - hw_osc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_OSC_BASE
+#define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
+#define HW_OSC0 (0U) //!< Instance number for OSC.
+#define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
+
+//! @brief Table of base addresses for OSC instances.
+static const uint32_t __g_regs_OSC_base_addresses[] = {
+        REGS_OSC0_BASE,
+    };
+
+//! @brief Get the base address of OSC by instance number.
+//! @param x OSC instance number, from 0 through 0.
+#define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of OSC.
+#define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_OSC_CR - OSC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+typedef union _hw_osc_cr
+{
+    uint8_t U;
+    struct _hw_osc_cr_bitfields
+    {
+        uint8_t SC16P : 1;             //!< [0] Oscillator 16 pF Capacitor Load Configure
+        uint8_t SC8P : 1;              //!< [1] Oscillator 8 pF Capacitor Load Configure
+        uint8_t SC4P : 1;              //!< [2] Oscillator 4 pF Capacitor Load Configure
+        uint8_t SC2P : 1;              //!< [3] Oscillator 2 pF Capacitor Load Configure
+        uint8_t RESERVED0 : 1;         //!< [4]
+        uint8_t EREFSTEN : 1;          //!< [5] External Reference Stop Enable
+        uint8_t RESERVED1 : 1;         //!< [6]
+        uint8_t ERCLKEN : 1;           //!< [7] External Reference Enable
+    } B;
+} hw_osc_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+//@{
+#define HW_OSC_CR_ADDR(x)        (REGS_OSC_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_OSC_CR(x)             (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
+#define HW_OSC_CR_RD(x)          (HW_OSC_CR(x).U)
+#define HW_OSC_CR_WR(x, v)       (HW_OSC_CR(x).U = (v))
+#define HW_OSC_CR_SET(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) |  (v)))
+#define HW_OSC_CR_CLR(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
+#define HW_OSC_CR_TOG(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 16 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC16P      (0U)          //!< Bit position for OSC_CR_SC16P.
+#define BM_OSC_CR_SC16P      (0x01U)       //!< Bit mask for OSC_CR_SC16P.
+#define BS_OSC_CR_SC16P      (1U)          //!< Bit field size in bits for OSC_CR_SC16P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC16P field.
+#define BR_OSC_CR_SC16P(x)   (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC16P.
+#define BF_OSC_CR_SC16P(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC16P field to a new value.
+#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 8 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC8P       (1U)          //!< Bit position for OSC_CR_SC8P.
+#define BM_OSC_CR_SC8P       (0x02U)       //!< Bit mask for OSC_CR_SC8P.
+#define BS_OSC_CR_SC8P       (1U)          //!< Bit field size in bits for OSC_CR_SC8P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC8P field.
+#define BR_OSC_CR_SC8P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC8P.
+#define BF_OSC_CR_SC8P(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC8P field to a new value.
+#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 4 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC4P       (2U)          //!< Bit position for OSC_CR_SC4P.
+#define BM_OSC_CR_SC4P       (0x04U)       //!< Bit mask for OSC_CR_SC4P.
+#define BS_OSC_CR_SC4P       (1U)          //!< Bit field size in bits for OSC_CR_SC4P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC4P field.
+#define BR_OSC_CR_SC4P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC4P.
+#define BF_OSC_CR_SC4P(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC4P field to a new value.
+#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 2 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC2P       (3U)          //!< Bit position for OSC_CR_SC2P.
+#define BM_OSC_CR_SC2P       (0x08U)       //!< Bit mask for OSC_CR_SC2P.
+#define BS_OSC_CR_SC2P       (1U)          //!< Bit field size in bits for OSC_CR_SC2P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC2P field.
+#define BR_OSC_CR_SC2P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC2P.
+#define BF_OSC_CR_SC2P(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC2P field to a new value.
+#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0 - External reference clock is disabled in Stop mode.
+ * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+//@{
+#define BP_OSC_CR_EREFSTEN   (5U)          //!< Bit position for OSC_CR_EREFSTEN.
+#define BM_OSC_CR_EREFSTEN   (0x20U)       //!< Bit mask for OSC_CR_EREFSTEN.
+#define BS_OSC_CR_EREFSTEN   (1U)          //!< Bit field size in bits for OSC_CR_EREFSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_EREFSTEN field.
+#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_EREFSTEN.
+#define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EREFSTEN field to a new value.
+#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0 - External reference clock is inactive.
+ * - 1 - External reference clock is enabled.
+ */
+//@{
+#define BP_OSC_CR_ERCLKEN    (7U)          //!< Bit position for OSC_CR_ERCLKEN.
+#define BM_OSC_CR_ERCLKEN    (0x80U)       //!< Bit mask for OSC_CR_ERCLKEN.
+#define BS_OSC_CR_ERCLKEN    (1U)          //!< Bit field size in bits for OSC_CR_ERCLKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_ERCLKEN field.
+#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_ERCLKEN.
+#define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERCLKEN field to a new value.
+#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_osc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All OSC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_osc
+{
+    __IO hw_osc_cr_t CR;                   //!< [0x0] OSC Control Register
+} hw_osc_t;
+#pragma pack()
+
+//! @brief Macro to access all OSC registers.
+//! @param x OSC instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_OSC(0)</code>.
+#define HW_OSC(x)      (*(hw_osc_t *) REGS_OSC_BASE(x))
+#endif
+
+#endif // __HW_OSC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h
new file mode 100644
index 0000000000..37605286c2
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h
@@ -0,0 +1,1433 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PDB_REGISTERS_H__
+#define __HW_PDB_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - HW_PDB_SC - Status and Control register
+ * - HW_PDB_MOD - Modulus register
+ * - HW_PDB_CNT - Counter register
+ * - HW_PDB_IDLY - Interrupt Delay register
+ * - HW_PDB_CHnC1 - Channel n Control register 1
+ * - HW_PDB_CHnS - Channel n Status register
+ * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
+ * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
+ * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
+ * - HW_PDB_DACINTn - DAC Interval n register
+ * - HW_PDB_POEN - Pulse-Out n Enable register
+ * - HW_PDB_POnDLY - Pulse-Out n Delay register
+ *
+ * - hw_pdb_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PDB_BASE
+#define HW_PDB_INSTANCE_COUNT (1U) //!< Number of instances of the PDB module.
+#define REGS_PDB_BASE (0x40036000U) //!< Base address for PDB0.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_SC - Status and Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_sc
+{
+    uint32_t U;
+    struct _hw_pdb_sc_bitfields
+    {
+        uint32_t LDOK : 1;             //!< [0] Load OK
+        uint32_t CONT : 1;             //!< [1] Continuous Mode Enable
+        uint32_t MULT : 2;             //!< [3:2] Multiplication Factor Select for
+                                       //! Prescaler
+        uint32_t RESERVED0 : 1;        //!< [4]
+        uint32_t PDBIE : 1;            //!< [5] PDB Interrupt Enable
+        uint32_t PDBIF : 1;            //!< [6] PDB Interrupt Flag
+        uint32_t PDBEN : 1;            //!< [7] PDB Enable
+        uint32_t TRGSEL : 4;           //!< [11:8] Trigger Input Source Select
+        uint32_t PRESCALER : 3;        //!< [14:12] Prescaler Divider Select
+        uint32_t DMAEN : 1;            //!< [15] DMA Enable
+        uint32_t SWTRIG : 1;           //!< [16] Software Trigger
+        uint32_t PDBEIE : 1;           //!< [17] PDB Sequence Error Interrupt Enable
+        uint32_t LDMOD : 2;            //!< [19:18] Load Mode Select
+        uint32_t RESERVED1 : 12;       //!< [31:20]
+    } B;
+} hw_pdb_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+//@{
+#define HW_PDB_SC_ADDR           (REGS_PDB_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_SC                (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR)
+#define HW_PDB_SC_RD()           (HW_PDB_SC.U)
+#define HW_PDB_SC_WR(v)          (HW_PDB_SC.U = (v))
+#define HW_PDB_SC_SET(v)         (HW_PDB_SC_WR(HW_PDB_SC_RD() |  (v)))
+#define HW_PDB_SC_CLR(v)         (HW_PDB_SC_WR(HW_PDB_SC_RD() & ~(v)))
+#define HW_PDB_SC_TOG(v)         (HW_PDB_SC_WR(HW_PDB_SC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+//@{
+#define BP_PDB_SC_LDOK       (0U)          //!< Bit position for PDB_SC_LDOK.
+#define BM_PDB_SC_LDOK       (0x00000001U) //!< Bit mask for PDB_SC_LDOK.
+#define BS_PDB_SC_LDOK       (1U)          //!< Bit field size in bits for PDB_SC_LDOK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_LDOK field.
+#define BR_PDB_SC_LDOK       (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_LDOK.
+#define BF_PDB_SC_LDOK(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDOK), uint32_t) & BM_PDB_SC_LDOK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LDOK field to a new value.
+#define BW_PDB_SC_LDOK(v)    (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0 - PDB operation in One-Shot mode
+ * - 1 - PDB operation in Continuous mode
+ */
+//@{
+#define BP_PDB_SC_CONT       (1U)          //!< Bit position for PDB_SC_CONT.
+#define BM_PDB_SC_CONT       (0x00000002U) //!< Bit mask for PDB_SC_CONT.
+#define BS_PDB_SC_CONT       (1U)          //!< Bit field size in bits for PDB_SC_CONT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_CONT field.
+#define BR_PDB_SC_CONT       (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_CONT.
+#define BF_PDB_SC_CONT(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_CONT), uint32_t) & BM_PDB_SC_CONT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CONT field to a new value.
+#define BW_PDB_SC_CONT(v)    (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 00 - Multiplication factor is 1.
+ * - 01 - Multiplication factor is 10.
+ * - 10 - Multiplication factor is 20.
+ * - 11 - Multiplication factor is 40.
+ */
+//@{
+#define BP_PDB_SC_MULT       (2U)          //!< Bit position for PDB_SC_MULT.
+#define BM_PDB_SC_MULT       (0x0000000CU) //!< Bit mask for PDB_SC_MULT.
+#define BS_PDB_SC_MULT       (2U)          //!< Bit field size in bits for PDB_SC_MULT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_MULT field.
+#define BR_PDB_SC_MULT       (HW_PDB_SC.B.MULT)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_MULT.
+#define BF_PDB_SC_MULT(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_MULT), uint32_t) & BM_PDB_SC_MULT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MULT field to a new value.
+#define BW_PDB_SC_MULT(v)    (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0 - PDB interrupt disabled.
+ * - 1 - PDB interrupt enabled.
+ */
+//@{
+#define BP_PDB_SC_PDBIE      (5U)          //!< Bit position for PDB_SC_PDBIE.
+#define BM_PDB_SC_PDBIE      (0x00000020U) //!< Bit mask for PDB_SC_PDBIE.
+#define BS_PDB_SC_PDBIE      (1U)          //!< Bit field size in bits for PDB_SC_PDBIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBIE field.
+#define BR_PDB_SC_PDBIE      (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBIE.
+#define BF_PDB_SC_PDBIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIE), uint32_t) & BM_PDB_SC_PDBIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBIE field to a new value.
+#define BW_PDB_SC_PDBIE(v)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+//@{
+#define BP_PDB_SC_PDBIF      (6U)          //!< Bit position for PDB_SC_PDBIF.
+#define BM_PDB_SC_PDBIF      (0x00000040U) //!< Bit mask for PDB_SC_PDBIF.
+#define BS_PDB_SC_PDBIF      (1U)          //!< Bit field size in bits for PDB_SC_PDBIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBIF field.
+#define BR_PDB_SC_PDBIF      (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBIF.
+#define BF_PDB_SC_PDBIF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIF), uint32_t) & BM_PDB_SC_PDBIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBIF field to a new value.
+#define BW_PDB_SC_PDBIF(v)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0 - PDB disabled. Counter is off.
+ * - 1 - PDB enabled.
+ */
+//@{
+#define BP_PDB_SC_PDBEN      (7U)          //!< Bit position for PDB_SC_PDBEN.
+#define BM_PDB_SC_PDBEN      (0x00000080U) //!< Bit mask for PDB_SC_PDBEN.
+#define BS_PDB_SC_PDBEN      (1U)          //!< Bit field size in bits for PDB_SC_PDBEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBEN field.
+#define BR_PDB_SC_PDBEN      (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBEN.
+#define BF_PDB_SC_PDBEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEN), uint32_t) & BM_PDB_SC_PDBEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBEN field to a new value.
+#define BW_PDB_SC_PDBEN(v)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0000 - Trigger-In 0 is selected.
+ * - 0001 - Trigger-In 1 is selected.
+ * - 0010 - Trigger-In 2 is selected.
+ * - 0011 - Trigger-In 3 is selected.
+ * - 0100 - Trigger-In 4 is selected.
+ * - 0101 - Trigger-In 5 is selected.
+ * - 0110 - Trigger-In 6 is selected.
+ * - 0111 - Trigger-In 7 is selected.
+ * - 1000 - Trigger-In 8 is selected.
+ * - 1001 - Trigger-In 9 is selected.
+ * - 1010 - Trigger-In 10 is selected.
+ * - 1011 - Trigger-In 11 is selected.
+ * - 1100 - Trigger-In 12 is selected.
+ * - 1101 - Trigger-In 13 is selected.
+ * - 1110 - Trigger-In 14 is selected.
+ * - 1111 - Software trigger is selected.
+ */
+//@{
+#define BP_PDB_SC_TRGSEL     (8U)          //!< Bit position for PDB_SC_TRGSEL.
+#define BM_PDB_SC_TRGSEL     (0x00000F00U) //!< Bit mask for PDB_SC_TRGSEL.
+#define BS_PDB_SC_TRGSEL     (4U)          //!< Bit field size in bits for PDB_SC_TRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_TRGSEL field.
+#define BR_PDB_SC_TRGSEL     (HW_PDB_SC.B.TRGSEL)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_TRGSEL.
+#define BF_PDB_SC_TRGSEL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_TRGSEL), uint32_t) & BM_PDB_SC_TRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRGSEL field to a new value.
+#define BW_PDB_SC_TRGSEL(v)  (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+//@{
+#define BP_PDB_SC_PRESCALER  (12U)         //!< Bit position for PDB_SC_PRESCALER.
+#define BM_PDB_SC_PRESCALER  (0x00007000U) //!< Bit mask for PDB_SC_PRESCALER.
+#define BS_PDB_SC_PRESCALER  (3U)          //!< Bit field size in bits for PDB_SC_PRESCALER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PRESCALER field.
+#define BR_PDB_SC_PRESCALER  (HW_PDB_SC.B.PRESCALER)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PRESCALER.
+#define BF_PDB_SC_PRESCALER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PRESCALER), uint32_t) & BM_PDB_SC_PRESCALER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCALER field to a new value.
+#define BW_PDB_SC_PRESCALER(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0 - DMA disabled.
+ * - 1 - DMA enabled.
+ */
+//@{
+#define BP_PDB_SC_DMAEN      (15U)         //!< Bit position for PDB_SC_DMAEN.
+#define BM_PDB_SC_DMAEN      (0x00008000U) //!< Bit mask for PDB_SC_DMAEN.
+#define BS_PDB_SC_DMAEN      (1U)          //!< Bit field size in bits for PDB_SC_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_DMAEN field.
+#define BR_PDB_SC_DMAEN      (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_DMAEN.
+#define BF_PDB_SC_DMAEN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_DMAEN), uint32_t) & BM_PDB_SC_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_PDB_SC_DMAEN(v)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+//@{
+#define BP_PDB_SC_SWTRIG     (16U)         //!< Bit position for PDB_SC_SWTRIG.
+#define BM_PDB_SC_SWTRIG     (0x00010000U) //!< Bit mask for PDB_SC_SWTRIG.
+#define BS_PDB_SC_SWTRIG     (1U)          //!< Bit field size in bits for PDB_SC_SWTRIG.
+
+//! @brief Format value for bitfield PDB_SC_SWTRIG.
+#define BF_PDB_SC_SWTRIG(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_SWTRIG), uint32_t) & BM_PDB_SC_SWTRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWTRIG field to a new value.
+#define BW_PDB_SC_SWTRIG(v)  (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_SWTRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0 - PDB sequence error interrupt disabled.
+ * - 1 - PDB sequence error interrupt enabled.
+ */
+//@{
+#define BP_PDB_SC_PDBEIE     (17U)         //!< Bit position for PDB_SC_PDBEIE.
+#define BM_PDB_SC_PDBEIE     (0x00020000U) //!< Bit mask for PDB_SC_PDBEIE.
+#define BS_PDB_SC_PDBEIE     (1U)          //!< Bit field size in bits for PDB_SC_PDBEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBEIE field.
+#define BR_PDB_SC_PDBEIE     (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBEIE.
+#define BF_PDB_SC_PDBEIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEIE), uint32_t) & BM_PDB_SC_PDBEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBEIE field to a new value.
+#define BW_PDB_SC_PDBEIE(v)  (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+//@{
+#define BP_PDB_SC_LDMOD      (18U)         //!< Bit position for PDB_SC_LDMOD.
+#define BM_PDB_SC_LDMOD      (0x000C0000U) //!< Bit mask for PDB_SC_LDMOD.
+#define BS_PDB_SC_LDMOD      (2U)          //!< Bit field size in bits for PDB_SC_LDMOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_LDMOD field.
+#define BR_PDB_SC_LDMOD      (HW_PDB_SC.B.LDMOD)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_LDMOD.
+#define BF_PDB_SC_LDMOD(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDMOD), uint32_t) & BM_PDB_SC_LDMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LDMOD field to a new value.
+#define BW_PDB_SC_LDMOD(v)   (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_MOD - Modulus register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+typedef union _hw_pdb_mod
+{
+    uint32_t U;
+    struct _hw_pdb_mod_bitfields
+    {
+        uint32_t MOD : 16;             //!< [15:0] PDB Modulus
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_pdb_mod_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+//@{
+#define HW_PDB_MOD_ADDR          (REGS_PDB_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_MOD               (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR)
+#define HW_PDB_MOD_RD()          (HW_PDB_MOD.U)
+#define HW_PDB_MOD_WR(v)         (HW_PDB_MOD.U = (v))
+#define HW_PDB_MOD_SET(v)        (HW_PDB_MOD_WR(HW_PDB_MOD_RD() |  (v)))
+#define HW_PDB_MOD_CLR(v)        (HW_PDB_MOD_WR(HW_PDB_MOD_RD() & ~(v)))
+#define HW_PDB_MOD_TOG(v)        (HW_PDB_MOD_WR(HW_PDB_MOD_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+//@{
+#define BP_PDB_MOD_MOD       (0U)          //!< Bit position for PDB_MOD_MOD.
+#define BM_PDB_MOD_MOD       (0x0000FFFFU) //!< Bit mask for PDB_MOD_MOD.
+#define BS_PDB_MOD_MOD       (16U)         //!< Bit field size in bits for PDB_MOD_MOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_MOD_MOD field.
+#define BR_PDB_MOD_MOD       (HW_PDB_MOD.B.MOD)
+#endif
+
+//! @brief Format value for bitfield PDB_MOD_MOD.
+#define BF_PDB_MOD_MOD(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_MOD_MOD), uint32_t) & BM_PDB_MOD_MOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MOD field to a new value.
+#define BW_PDB_MOD_MOD(v)    (HW_PDB_MOD_WR((HW_PDB_MOD_RD() & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CNT - Counter register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_cnt
+{
+    uint32_t U;
+    struct _hw_pdb_cnt_bitfields
+    {
+        uint32_t CNT : 16;             //!< [15:0] PDB Counter
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_pdb_cnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+//@{
+#define HW_PDB_CNT_ADDR          (REGS_PDB_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CNT               (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR)
+#define HW_PDB_CNT_RD()          (HW_PDB_CNT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+//@{
+#define BP_PDB_CNT_CNT       (0U)          //!< Bit position for PDB_CNT_CNT.
+#define BM_PDB_CNT_CNT       (0x0000FFFFU) //!< Bit mask for PDB_CNT_CNT.
+#define BS_PDB_CNT_CNT       (16U)         //!< Bit field size in bits for PDB_CNT_CNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CNT_CNT field.
+#define BR_PDB_CNT_CNT       (HW_PDB_CNT.B.CNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_IDLY - Interrupt Delay register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+typedef union _hw_pdb_idly
+{
+    uint32_t U;
+    struct _hw_pdb_idly_bitfields
+    {
+        uint32_t IDLY : 16;            //!< [15:0] PDB Interrupt Delay
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_pdb_idly_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+//@{
+#define HW_PDB_IDLY_ADDR         (REGS_PDB_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_IDLY              (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR)
+#define HW_PDB_IDLY_RD()         (HW_PDB_IDLY.U)
+#define HW_PDB_IDLY_WR(v)        (HW_PDB_IDLY.U = (v))
+#define HW_PDB_IDLY_SET(v)       (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() |  (v)))
+#define HW_PDB_IDLY_CLR(v)       (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() & ~(v)))
+#define HW_PDB_IDLY_TOG(v)       (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+//@{
+#define BP_PDB_IDLY_IDLY     (0U)          //!< Bit position for PDB_IDLY_IDLY.
+#define BM_PDB_IDLY_IDLY     (0x0000FFFFU) //!< Bit mask for PDB_IDLY_IDLY.
+#define BS_PDB_IDLY_IDLY     (16U)         //!< Bit field size in bits for PDB_IDLY_IDLY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_IDLY_IDLY field.
+#define BR_PDB_IDLY_IDLY     (HW_PDB_IDLY.B.IDLY)
+#endif
+
+//! @brief Format value for bitfield PDB_IDLY_IDLY.
+#define BF_PDB_IDLY_IDLY(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_IDLY_IDLY), uint32_t) & BM_PDB_IDLY_IDLY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDLY field to a new value.
+#define BW_PDB_IDLY_IDLY(v)  (HW_PDB_IDLY_WR((HW_PDB_IDLY_RD() & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnC1 - Channel n Control register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+typedef union _hw_pdb_chnc1
+{
+    uint32_t U;
+    struct _hw_pdb_chnc1_bitfields
+    {
+        uint32_t EN : 8;               //!< [7:0] PDB Channel Pre-Trigger Enable
+        uint32_t TOS : 8;              //!< [15:8] PDB Channel Pre-Trigger Output Select
+        uint32_t BB : 8;               //!< [23:16] PDB Channel Pre-Trigger Back-to-Back
+                                       //! Operation Enable
+        uint32_t RESERVED0 : 8;        //!< [31:24]
+    } B;
+} hw_pdb_chnc1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnC1 register
+ */
+//@{
+#define HW_PDB_CHnC1_COUNT (2U)
+
+#define HW_PDB_CHnC1_ADDR(n)     (REGS_PDB_BASE + 0x10U + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnC1(n)          (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(n))
+#define HW_PDB_CHnC1_RD(n)       (HW_PDB_CHnC1(n).U)
+#define HW_PDB_CHnC1_WR(n, v)    (HW_PDB_CHnC1(n).U = (v))
+#define HW_PDB_CHnC1_SET(n, v)   (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) |  (v)))
+#define HW_PDB_CHnC1_CLR(n, v)   (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) & ~(v)))
+#define HW_PDB_CHnC1_TOG(n, v)   (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnC1 bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnC1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0 - PDB channel's corresponding pre-trigger disabled.
+ * - 1 - PDB channel's corresponding pre-trigger enabled.
+ */
+//@{
+#define BP_PDB_CHnC1_EN      (0U)          //!< Bit position for PDB_CHnC1_EN.
+#define BM_PDB_CHnC1_EN      (0x000000FFU) //!< Bit mask for PDB_CHnC1_EN.
+#define BS_PDB_CHnC1_EN      (8U)          //!< Bit field size in bits for PDB_CHnC1_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnC1_EN field.
+#define BR_PDB_CHnC1_EN(n)   (HW_PDB_CHnC1(n).B.EN)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnC1_EN.
+#define BF_PDB_CHnC1_EN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_EN), uint32_t) & BM_PDB_CHnC1_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_PDB_CHnC1_EN(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_CHnC1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
+ *     pre-trigger asserts one peripheral clock cycle after a rising edge is detected
+ *     on selected trigger input source or software trigger is selected and SWTRIG
+ *     is written with 1.
+ * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
+ *     reaches the channel delay register and one peripheral clock cycle after a rising
+ *     edge is detected on selected trigger input source or software trigger is
+ *     selected and SETRIG is written with 1.
+ */
+//@{
+#define BP_PDB_CHnC1_TOS     (8U)          //!< Bit position for PDB_CHnC1_TOS.
+#define BM_PDB_CHnC1_TOS     (0x0000FF00U) //!< Bit mask for PDB_CHnC1_TOS.
+#define BS_PDB_CHnC1_TOS     (8U)          //!< Bit field size in bits for PDB_CHnC1_TOS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnC1_TOS field.
+#define BR_PDB_CHnC1_TOS(n)  (HW_PDB_CHnC1(n).B.TOS)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnC1_TOS.
+#define BF_PDB_CHnC1_TOS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_TOS), uint32_t) & BM_PDB_CHnC1_TOS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOS field to a new value.
+#define BW_PDB_CHnC1_TOS(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_CHnC1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
+ * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
+ */
+//@{
+#define BP_PDB_CHnC1_BB      (16U)         //!< Bit position for PDB_CHnC1_BB.
+#define BM_PDB_CHnC1_BB      (0x00FF0000U) //!< Bit mask for PDB_CHnC1_BB.
+#define BS_PDB_CHnC1_BB      (8U)          //!< Bit field size in bits for PDB_CHnC1_BB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnC1_BB field.
+#define BR_PDB_CHnC1_BB(n)   (HW_PDB_CHnC1(n).B.BB)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnC1_BB.
+#define BF_PDB_CHnC1_BB(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_BB), uint32_t) & BM_PDB_CHnC1_BB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BB field to a new value.
+#define BW_PDB_CHnC1_BB(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnS - Channel n Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnS - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_chns
+{
+    uint32_t U;
+    struct _hw_pdb_chns_bitfields
+    {
+        uint32_t ERR : 8;              //!< [7:0] PDB Channel Sequence Error Flags
+        uint32_t RESERVED0 : 8;        //!< [15:8]
+        uint32_t CF : 8;               //!< [23:16] PDB Channel Flags
+        uint32_t RESERVED1 : 8;        //!< [31:24]
+    } B;
+} hw_pdb_chns_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnS register
+ */
+//@{
+#define HW_PDB_CHnS_COUNT (2U)
+
+#define HW_PDB_CHnS_ADDR(n)      (REGS_PDB_BASE + 0x14U + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnS(n)           (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(n))
+#define HW_PDB_CHnS_RD(n)        (HW_PDB_CHnS(n).U)
+#define HW_PDB_CHnS_WR(n, v)     (HW_PDB_CHnS(n).U = (v))
+#define HW_PDB_CHnS_SET(n, v)    (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) |  (v)))
+#define HW_PDB_CHnS_CLR(n, v)    (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) & ~(v)))
+#define HW_PDB_CHnS_TOG(n, v)    (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnS bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnS, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
+ * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
+ *     ADCn block can be triggered for a conversion by one pre-trigger from PDB
+ *     channel n. When one conversion, which is triggered by one of the pre-triggers
+ *     from PDB channel n, is in progress, new trigger from PDB channel's
+ *     corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
+ *     Writing 0's to clear the sequence error flags.
+ */
+//@{
+#define BP_PDB_CHnS_ERR      (0U)          //!< Bit position for PDB_CHnS_ERR.
+#define BM_PDB_CHnS_ERR      (0x000000FFU) //!< Bit mask for PDB_CHnS_ERR.
+#define BS_PDB_CHnS_ERR      (8U)          //!< Bit field size in bits for PDB_CHnS_ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnS_ERR field.
+#define BR_PDB_CHnS_ERR(n)   (HW_PDB_CHnS(n).B.ERR)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnS_ERR.
+#define BF_PDB_CHnS_ERR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_ERR), uint32_t) & BM_PDB_CHnS_ERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR field to a new value.
+#define BW_PDB_CHnS_ERR(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_CHnS, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+//@{
+#define BP_PDB_CHnS_CF       (16U)         //!< Bit position for PDB_CHnS_CF.
+#define BM_PDB_CHnS_CF       (0x00FF0000U) //!< Bit mask for PDB_CHnS_CF.
+#define BS_PDB_CHnS_CF       (8U)          //!< Bit field size in bits for PDB_CHnS_CF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnS_CF field.
+#define BR_PDB_CHnS_CF(n)    (HW_PDB_CHnS(n).B.CF)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnS_CF.
+#define BF_PDB_CHnS_CF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_CF), uint32_t) & BM_PDB_CHnS_CF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CF field to a new value.
+#define BW_PDB_CHnS_CF(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnDLY0 - Channel n Delay 0 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_chndly0
+{
+    uint32_t U;
+    struct _hw_pdb_chndly0_bitfields
+    {
+        uint32_t DLY : 16;             //!< [15:0] PDB Channel Delay
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_pdb_chndly0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnDLY0 register
+ */
+//@{
+#define HW_PDB_CHnDLY0_COUNT (2U)
+
+#define HW_PDB_CHnDLY0_ADDR(n)   (REGS_PDB_BASE + 0x18U + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnDLY0(n)        (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(n))
+#define HW_PDB_CHnDLY0_RD(n)     (HW_PDB_CHnDLY0(n).U)
+#define HW_PDB_CHnDLY0_WR(n, v)  (HW_PDB_CHnDLY0(n).U = (v))
+#define HW_PDB_CHnDLY0_SET(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) |  (v)))
+#define HW_PDB_CHnDLY0_CLR(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) & ~(v)))
+#define HW_PDB_CHnDLY0_TOG(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnDLY0 bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_CHnDLY0_DLY   (0U)          //!< Bit position for PDB_CHnDLY0_DLY.
+#define BM_PDB_CHnDLY0_DLY   (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY0_DLY.
+#define BS_PDB_CHnDLY0_DLY   (16U)         //!< Bit field size in bits for PDB_CHnDLY0_DLY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnDLY0_DLY field.
+#define BR_PDB_CHnDLY0_DLY(n) (HW_PDB_CHnDLY0(n).B.DLY)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnDLY0_DLY.
+#define BF_PDB_CHnDLY0_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY0_DLY), uint32_t) & BM_PDB_CHnDLY0_DLY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY field to a new value.
+#define BW_PDB_CHnDLY0_DLY(n, v) (HW_PDB_CHnDLY0_WR(n, (HW_PDB_CHnDLY0_RD(n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnDLY1 - Channel n Delay 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_chndly1
+{
+    uint32_t U;
+    struct _hw_pdb_chndly1_bitfields
+    {
+        uint32_t DLY : 16;             //!< [15:0] PDB Channel Delay
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_pdb_chndly1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnDLY1 register
+ */
+//@{
+#define HW_PDB_CHnDLY1_COUNT (2U)
+
+#define HW_PDB_CHnDLY1_ADDR(n)   (REGS_PDB_BASE + 0x1CU + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnDLY1(n)        (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(n))
+#define HW_PDB_CHnDLY1_RD(n)     (HW_PDB_CHnDLY1(n).U)
+#define HW_PDB_CHnDLY1_WR(n, v)  (HW_PDB_CHnDLY1(n).U = (v))
+#define HW_PDB_CHnDLY1_SET(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) |  (v)))
+#define HW_PDB_CHnDLY1_CLR(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) & ~(v)))
+#define HW_PDB_CHnDLY1_TOG(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnDLY1 bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
+ *
+ * These bits specify the delay value for the channel's corresponding
+ * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
+ * bits returns the value of internal register that is effective for the current PDB
+ * cycle.
+ */
+//@{
+#define BP_PDB_CHnDLY1_DLY   (0U)          //!< Bit position for PDB_CHnDLY1_DLY.
+#define BM_PDB_CHnDLY1_DLY   (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY1_DLY.
+#define BS_PDB_CHnDLY1_DLY   (16U)         //!< Bit field size in bits for PDB_CHnDLY1_DLY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnDLY1_DLY field.
+#define BR_PDB_CHnDLY1_DLY(n) (HW_PDB_CHnDLY1(n).B.DLY)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnDLY1_DLY.
+#define BF_PDB_CHnDLY1_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY1_DLY), uint32_t) & BM_PDB_CHnDLY1_DLY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY field to a new value.
+#define BW_PDB_CHnDLY1_DLY(n, v) (HW_PDB_CHnDLY1_WR(n, (HW_PDB_CHnDLY1_RD(n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_DACINTCn - DAC Interval Trigger n Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_dacintcn
+{
+    uint32_t U;
+    struct _hw_pdb_dacintcn_bitfields
+    {
+        uint32_t TOE : 1;              //!< [0] DAC Interval Trigger Enable
+        uint32_t EXT : 1;              //!< [1] DAC External Trigger Input Enable
+        uint32_t RESERVED0 : 30;       //!< [31:2]
+    } B;
+} hw_pdb_dacintcn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_DACINTCn register
+ */
+//@{
+#define HW_PDB_DACINTCn_COUNT (2U)
+
+#define HW_PDB_DACINTCn_ADDR(n)  (REGS_PDB_BASE + 0x150U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_DACINTCn(n)       (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(n))
+#define HW_PDB_DACINTCn_RD(n)    (HW_PDB_DACINTCn(n).U)
+#define HW_PDB_DACINTCn_WR(n, v) (HW_PDB_DACINTCn(n).U = (v))
+#define HW_PDB_DACINTCn_SET(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) |  (v)))
+#define HW_PDB_DACINTCn_CLR(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) & ~(v)))
+#define HW_PDB_DACINTCn_TOG(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_DACINTCn bitfields
+ */
+
+/*!
+ * @name Register PDB_DACINTCn, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0 - DAC interval trigger disabled.
+ * - 1 - DAC interval trigger enabled.
+ */
+//@{
+#define BP_PDB_DACINTCn_TOE  (0U)          //!< Bit position for PDB_DACINTCn_TOE.
+#define BM_PDB_DACINTCn_TOE  (0x00000001U) //!< Bit mask for PDB_DACINTCn_TOE.
+#define BS_PDB_DACINTCn_TOE  (1U)          //!< Bit field size in bits for PDB_DACINTCn_TOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_DACINTCn_TOE field.
+#define BR_PDB_DACINTCn_TOE(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE))
+#endif
+
+//! @brief Format value for bitfield PDB_DACINTCn_TOE.
+#define BF_PDB_DACINTCn_TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_TOE), uint32_t) & BM_PDB_DACINTCn_TOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOE field to a new value.
+#define BW_PDB_DACINTCn_TOE(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_DACINTCn, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
+ *     counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+//@{
+#define BP_PDB_DACINTCn_EXT  (1U)          //!< Bit position for PDB_DACINTCn_EXT.
+#define BM_PDB_DACINTCn_EXT  (0x00000002U) //!< Bit mask for PDB_DACINTCn_EXT.
+#define BS_PDB_DACINTCn_EXT  (1U)          //!< Bit field size in bits for PDB_DACINTCn_EXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_DACINTCn_EXT field.
+#define BR_PDB_DACINTCn_EXT(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT))
+#endif
+
+//! @brief Format value for bitfield PDB_DACINTCn_EXT.
+#define BF_PDB_DACINTCn_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_EXT), uint32_t) & BM_PDB_DACINTCn_EXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXT field to a new value.
+#define BW_PDB_DACINTCn_EXT(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_DACINTn - DAC Interval n register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_dacintn
+{
+    uint32_t U;
+    struct _hw_pdb_dacintn_bitfields
+    {
+        uint32_t INT : 16;             //!< [15:0] DAC Interval
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_pdb_dacintn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_DACINTn register
+ */
+//@{
+#define HW_PDB_DACINTn_COUNT (2U)
+
+#define HW_PDB_DACINTn_ADDR(n)   (REGS_PDB_BASE + 0x154U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_DACINTn(n)        (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(n))
+#define HW_PDB_DACINTn_RD(n)     (HW_PDB_DACINTn(n).U)
+#define HW_PDB_DACINTn_WR(n, v)  (HW_PDB_DACINTn(n).U = (v))
+#define HW_PDB_DACINTn_SET(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) |  (v)))
+#define HW_PDB_DACINTn_CLR(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) & ~(v)))
+#define HW_PDB_DACINTn_TOG(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_DACINTn bitfields
+ */
+
+/*!
+ * @name Register PDB_DACINTn, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_DACINTn_INT   (0U)          //!< Bit position for PDB_DACINTn_INT.
+#define BM_PDB_DACINTn_INT   (0x0000FFFFU) //!< Bit mask for PDB_DACINTn_INT.
+#define BS_PDB_DACINTn_INT   (16U)         //!< Bit field size in bits for PDB_DACINTn_INT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_DACINTn_INT field.
+#define BR_PDB_DACINTn_INT(n) (HW_PDB_DACINTn(n).B.INT)
+#endif
+
+//! @brief Format value for bitfield PDB_DACINTn_INT.
+#define BF_PDB_DACINTn_INT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTn_INT), uint32_t) & BM_PDB_DACINTn_INT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT field to a new value.
+#define BW_PDB_DACINTn_INT(n, v) (HW_PDB_DACINTn_WR(n, (HW_PDB_DACINTn_RD(n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_POEN - Pulse-Out n Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_poen
+{
+    uint32_t U;
+    struct _hw_pdb_poen_bitfields
+    {
+        uint32_t POEN : 8;             //!< [7:0] PDB Pulse-Out Enable
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_pdb_poen_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+//@{
+#define HW_PDB_POEN_ADDR         (REGS_PDB_BASE + 0x190U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_POEN              (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR)
+#define HW_PDB_POEN_RD()         (HW_PDB_POEN.U)
+#define HW_PDB_POEN_WR(v)        (HW_PDB_POEN.U = (v))
+#define HW_PDB_POEN_SET(v)       (HW_PDB_POEN_WR(HW_PDB_POEN_RD() |  (v)))
+#define HW_PDB_POEN_CLR(v)       (HW_PDB_POEN_WR(HW_PDB_POEN_RD() & ~(v)))
+#define HW_PDB_POEN_TOG(v)       (HW_PDB_POEN_WR(HW_PDB_POEN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0 - PDB Pulse-Out disabled
+ * - 1 - PDB Pulse-Out enabled
+ */
+//@{
+#define BP_PDB_POEN_POEN     (0U)          //!< Bit position for PDB_POEN_POEN.
+#define BM_PDB_POEN_POEN     (0x000000FFU) //!< Bit mask for PDB_POEN_POEN.
+#define BS_PDB_POEN_POEN     (8U)          //!< Bit field size in bits for PDB_POEN_POEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_POEN_POEN field.
+#define BR_PDB_POEN_POEN     (HW_PDB_POEN.B.POEN)
+#endif
+
+//! @brief Format value for bitfield PDB_POEN_POEN.
+#define BF_PDB_POEN_POEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POEN_POEN), uint32_t) & BM_PDB_POEN_POEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POEN field to a new value.
+#define BW_PDB_POEN_POEN(v)  (HW_PDB_POEN_WR((HW_PDB_POEN_RD() & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_POnDLY - Pulse-Out n Delay register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_pondly
+{
+    uint32_t U;
+    struct _hw_pdb_pondly_bitfields
+    {
+        uint32_t DLY2 : 16;            //!< [15:0] PDB Pulse-Out Delay 2
+        uint32_t DLY1 : 16;            //!< [31:16] PDB Pulse-Out Delay 1
+    } B;
+} hw_pdb_pondly_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_POnDLY register
+ */
+//@{
+#define HW_PDB_POnDLY_COUNT (3U)
+
+#define HW_PDB_POnDLY_ADDR(n)    (REGS_PDB_BASE + 0x194U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_POnDLY(n)         (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(n))
+#define HW_PDB_POnDLY_RD(n)      (HW_PDB_POnDLY(n).U)
+#define HW_PDB_POnDLY_WR(n, v)   (HW_PDB_POnDLY(n).U = (v))
+#define HW_PDB_POnDLY_SET(n, v)  (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) |  (v)))
+#define HW_PDB_POnDLY_CLR(n, v)  (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) & ~(v)))
+#define HW_PDB_POnDLY_TOG(n, v)  (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_POnDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_POnDLY_DLY2   (0U)          //!< Bit position for PDB_POnDLY_DLY2.
+#define BM_PDB_POnDLY_DLY2   (0x0000FFFFU) //!< Bit mask for PDB_POnDLY_DLY2.
+#define BS_PDB_POnDLY_DLY2   (16U)         //!< Bit field size in bits for PDB_POnDLY_DLY2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_POnDLY_DLY2 field.
+#define BR_PDB_POnDLY_DLY2(n) (HW_PDB_POnDLY(n).B.DLY2)
+#endif
+
+//! @brief Format value for bitfield PDB_POnDLY_DLY2.
+#define BF_PDB_POnDLY_DLY2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY2), uint32_t) & BM_PDB_POnDLY_DLY2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY2 field to a new value.
+#define BW_PDB_POnDLY_DLY2(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_POnDLY_DLY1   (16U)         //!< Bit position for PDB_POnDLY_DLY1.
+#define BM_PDB_POnDLY_DLY1   (0xFFFF0000U) //!< Bit mask for PDB_POnDLY_DLY1.
+#define BS_PDB_POnDLY_DLY1   (16U)         //!< Bit field size in bits for PDB_POnDLY_DLY1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_POnDLY_DLY1 field.
+#define BR_PDB_POnDLY_DLY1(n) (HW_PDB_POnDLY(n).B.DLY1)
+#endif
+
+//! @brief Format value for bitfield PDB_POnDLY_DLY1.
+#define BF_PDB_POnDLY_DLY1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY1), uint32_t) & BM_PDB_POnDLY_DLY1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY1 field to a new value.
+#define BW_PDB_POnDLY_DLY1(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_pdb_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PDB module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_pdb
+{
+    __IO hw_pdb_sc_t SC;                   //!< [0x0] Status and Control register
+    __IO hw_pdb_mod_t MOD;                 //!< [0x4] Modulus register
+    __I hw_pdb_cnt_t CNT;                  //!< [0x8] Counter register
+    __IO hw_pdb_idly_t IDLY;               //!< [0xC] Interrupt Delay register
+    struct {
+        __IO hw_pdb_chnc1_t CHnC1;         //!< [0x10] Channel n Control register 1
+        __IO hw_pdb_chns_t CHnS;           //!< [0x14] Channel n Status register
+        __IO hw_pdb_chndly0_t CHnDLY0;     //!< [0x18] Channel n Delay 0 register
+        __IO hw_pdb_chndly1_t CHnDLY1;     //!< [0x1C] Channel n Delay 1 register
+        uint8_t _reserved0[24];
+    } CH[2];
+    uint8_t _reserved0[240];
+    struct {
+        __IO hw_pdb_dacintcn_t DACINTCn;   //!< [0x150] DAC Interval Trigger n Control register
+        __IO hw_pdb_dacintn_t DACINTn;     //!< [0x154] DAC Interval n register
+    } DAC[2];
+    uint8_t _reserved1[48];
+    __IO hw_pdb_poen_t POEN;               //!< [0x190] Pulse-Out n Enable register
+    __IO hw_pdb_pondly_t POnDLY[3];        //!< [0x194] Pulse-Out n Delay register
+} hw_pdb_t;
+#pragma pack()
+
+//! @brief Macro to access all PDB registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_PDB</code>.
+#define HW_PDB         (*(hw_pdb_t *) REGS_PDB_BASE)
+#endif
+
+#endif // __HW_PDB_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h
new file mode 100644
index 0000000000..a9830e1697
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h
@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PIT_REGISTERS_H__
+#define __HW_PIT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - HW_PIT_MCR - PIT Module Control Register
+ * - HW_PIT_LDVALn - Timer Load Value Register
+ * - HW_PIT_CVALn - Current Timer Value Register
+ * - HW_PIT_TCTRLn - Timer Control Register
+ * - HW_PIT_TFLGn - Timer Flag Register
+ *
+ * - hw_pit_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PIT_BASE
+#define HW_PIT_INSTANCE_COUNT (1U) //!< Number of instances of the PIT module.
+#define REGS_PIT_BASE (0x40037000U) //!< Base address for PIT.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PIT_MCR - PIT Module Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+typedef union _hw_pit_mcr
+{
+    uint32_t U;
+    struct _hw_pit_mcr_bitfields
+    {
+        uint32_t FRZ : 1;              //!< [0] Freeze
+        uint32_t MDIS : 1;             //!< [1] Module Disable - (PIT section)
+        uint32_t RESERVED0 : 30;       //!< [31:2]
+    } B;
+} hw_pit_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+//@{
+#define HW_PIT_MCR_ADDR          (REGS_PIT_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_MCR               (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR)
+#define HW_PIT_MCR_RD()          (HW_PIT_MCR.U)
+#define HW_PIT_MCR_WR(v)         (HW_PIT_MCR.U = (v))
+#define HW_PIT_MCR_SET(v)        (HW_PIT_MCR_WR(HW_PIT_MCR_RD() |  (v)))
+#define HW_PIT_MCR_CLR(v)        (HW_PIT_MCR_WR(HW_PIT_MCR_RD() & ~(v)))
+#define HW_PIT_MCR_TOG(v)        (HW_PIT_MCR_WR(HW_PIT_MCR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0 - Timers continue to run in Debug mode.
+ * - 1 - Timers are stopped in Debug mode.
+ */
+//@{
+#define BP_PIT_MCR_FRZ       (0U)          //!< Bit position for PIT_MCR_FRZ.
+#define BM_PIT_MCR_FRZ       (0x00000001U) //!< Bit mask for PIT_MCR_FRZ.
+#define BS_PIT_MCR_FRZ       (1U)          //!< Bit field size in bits for PIT_MCR_FRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_MCR_FRZ field.
+#define BR_PIT_MCR_FRZ       (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ))
+#endif
+
+//! @brief Format value for bitfield PIT_MCR_FRZ.
+#define BF_PIT_MCR_FRZ(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_FRZ), uint32_t) & BM_PIT_MCR_FRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRZ field to a new value.
+#define BW_PIT_MCR_FRZ(v)    (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0 - Clock for standard PIT timers is enabled.
+ * - 1 - Clock for standard PIT timers is disabled.
+ */
+//@{
+#define BP_PIT_MCR_MDIS      (1U)          //!< Bit position for PIT_MCR_MDIS.
+#define BM_PIT_MCR_MDIS      (0x00000002U) //!< Bit mask for PIT_MCR_MDIS.
+#define BS_PIT_MCR_MDIS      (1U)          //!< Bit field size in bits for PIT_MCR_MDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_MCR_MDIS field.
+#define BR_PIT_MCR_MDIS      (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS))
+#endif
+
+//! @brief Format value for bitfield PIT_MCR_MDIS.
+#define BF_PIT_MCR_MDIS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_MDIS), uint32_t) & BM_PIT_MCR_MDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MDIS field to a new value.
+#define BW_PIT_MCR_MDIS(v)   (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PIT_LDVALn - Timer Load Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+typedef union _hw_pit_ldvaln
+{
+    uint32_t U;
+    struct _hw_pit_ldvaln_bitfields
+    {
+        uint32_t TSV : 32;             //!< [31:0] Timer Start Value
+    } B;
+} hw_pit_ldvaln_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_LDVALn register
+ */
+//@{
+#define HW_PIT_LDVALn_COUNT (4U)
+
+#define HW_PIT_LDVALn_ADDR(n)    (REGS_PIT_BASE + 0x100U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_LDVALn(n)         (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(n))
+#define HW_PIT_LDVALn_RD(n)      (HW_PIT_LDVALn(n).U)
+#define HW_PIT_LDVALn_WR(n, v)   (HW_PIT_LDVALn(n).U = (v))
+#define HW_PIT_LDVALn_SET(n, v)  (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) |  (v)))
+#define HW_PIT_LDVALn_CLR(n, v)  (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) & ~(v)))
+#define HW_PIT_LDVALn_TOG(n, v)  (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_LDVALn bitfields
+ */
+
+/*!
+ * @name Register PIT_LDVALn, field TSV[31:0] (RW)
+ *
+ * Sets the timer start value. The timer will count down until it reaches 0,
+ * then it will generate an interrupt and load this register value again. Writing a
+ * new value to this register will not restart the timer; instead the value will
+ * be loaded after the timer expires. To abort the current cycle and start a
+ * timer period with the new value, the timer must be disabled and enabled again.
+ */
+//@{
+#define BP_PIT_LDVALn_TSV    (0U)          //!< Bit position for PIT_LDVALn_TSV.
+#define BM_PIT_LDVALn_TSV    (0xFFFFFFFFU) //!< Bit mask for PIT_LDVALn_TSV.
+#define BS_PIT_LDVALn_TSV    (32U)         //!< Bit field size in bits for PIT_LDVALn_TSV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_LDVALn_TSV field.
+#define BR_PIT_LDVALn_TSV(n) (HW_PIT_LDVALn(n).U)
+#endif
+
+//! @brief Format value for bitfield PIT_LDVALn_TSV.
+#define BF_PIT_LDVALn_TSV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_LDVALn_TSV), uint32_t) & BM_PIT_LDVALn_TSV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSV field to a new value.
+#define BW_PIT_LDVALn_TSV(n, v) (HW_PIT_LDVALn_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PIT_CVALn - Current Timer Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+typedef union _hw_pit_cvaln
+{
+    uint32_t U;
+    struct _hw_pit_cvaln_bitfields
+    {
+        uint32_t TVL : 32;             //!< [31:0] Current Timer Value
+    } B;
+} hw_pit_cvaln_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_CVALn register
+ */
+//@{
+#define HW_PIT_CVALn_COUNT (4U)
+
+#define HW_PIT_CVALn_ADDR(n)     (REGS_PIT_BASE + 0x104U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_CVALn(n)          (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(n))
+#define HW_PIT_CVALn_RD(n)       (HW_PIT_CVALn(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_CVALn bitfields
+ */
+
+/*!
+ * @name Register PIT_CVALn, field TVL[31:0] (RO)
+ *
+ * Represents the current timer value, if the timer is enabled. If the timer is
+ * disabled, do not use this field as its value is unreliable. The timer uses a
+ * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
+ */
+//@{
+#define BP_PIT_CVALn_TVL     (0U)          //!< Bit position for PIT_CVALn_TVL.
+#define BM_PIT_CVALn_TVL     (0xFFFFFFFFU) //!< Bit mask for PIT_CVALn_TVL.
+#define BS_PIT_CVALn_TVL     (32U)         //!< Bit field size in bits for PIT_CVALn_TVL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_CVALn_TVL field.
+#define BR_PIT_CVALn_TVL(n)  (HW_PIT_CVALn(n).U)
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PIT_TCTRLn - Timer Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+typedef union _hw_pit_tctrln
+{
+    uint32_t U;
+    struct _hw_pit_tctrln_bitfields
+    {
+        uint32_t TEN : 1;              //!< [0] Timer Enable
+        uint32_t TIE : 1;              //!< [1] Timer Interrupt Enable
+        uint32_t CHN : 1;              //!< [2] Chain Mode
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_pit_tctrln_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_TCTRLn register
+ */
+//@{
+#define HW_PIT_TCTRLn_COUNT (4U)
+
+#define HW_PIT_TCTRLn_ADDR(n)    (REGS_PIT_BASE + 0x108U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_TCTRLn(n)         (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(n))
+#define HW_PIT_TCTRLn_RD(n)      (HW_PIT_TCTRLn(n).U)
+#define HW_PIT_TCTRLn_WR(n, v)   (HW_PIT_TCTRLn(n).U = (v))
+#define HW_PIT_TCTRLn_SET(n, v)  (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) |  (v)))
+#define HW_PIT_TCTRLn_CLR(n, v)  (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) & ~(v)))
+#define HW_PIT_TCTRLn_TOG(n, v)  (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_TCTRLn bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRLn, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0 - Timer n is disabled.
+ * - 1 - Timer n is enabled.
+ */
+//@{
+#define BP_PIT_TCTRLn_TEN    (0U)          //!< Bit position for PIT_TCTRLn_TEN.
+#define BM_PIT_TCTRLn_TEN    (0x00000001U) //!< Bit mask for PIT_TCTRLn_TEN.
+#define BS_PIT_TCTRLn_TEN    (1U)          //!< Bit field size in bits for PIT_TCTRLn_TEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TCTRLn_TEN field.
+#define BR_PIT_TCTRLn_TEN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN))
+#endif
+
+//! @brief Format value for bitfield PIT_TCTRLn_TEN.
+#define BF_PIT_TCTRLn_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TEN), uint32_t) & BM_PIT_TCTRLn_TEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TEN field to a new value.
+#define BW_PIT_TCTRLn_TEN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PIT_TCTRLn, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0 - Interrupt requests from Timer n are disabled.
+ * - 1 - Interrupt will be requested whenever TIF is set.
+ */
+//@{
+#define BP_PIT_TCTRLn_TIE    (1U)          //!< Bit position for PIT_TCTRLn_TIE.
+#define BM_PIT_TCTRLn_TIE    (0x00000002U) //!< Bit mask for PIT_TCTRLn_TIE.
+#define BS_PIT_TCTRLn_TIE    (1U)          //!< Bit field size in bits for PIT_TCTRLn_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TCTRLn_TIE field.
+#define BR_PIT_TCTRLn_TIE(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE))
+#endif
+
+//! @brief Format value for bitfield PIT_TCTRLn_TIE.
+#define BF_PIT_TCTRLn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TIE), uint32_t) & BM_PIT_TCTRLn_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_PIT_TCTRLn_TIE(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PIT_TCTRLn, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0 - Timer is not chained.
+ * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
+ *     field is set, Timer 2 is chained to Timer 1.
+ */
+//@{
+#define BP_PIT_TCTRLn_CHN    (2U)          //!< Bit position for PIT_TCTRLn_CHN.
+#define BM_PIT_TCTRLn_CHN    (0x00000004U) //!< Bit mask for PIT_TCTRLn_CHN.
+#define BS_PIT_TCTRLn_CHN    (1U)          //!< Bit field size in bits for PIT_TCTRLn_CHN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TCTRLn_CHN field.
+#define BR_PIT_TCTRLn_CHN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN))
+#endif
+
+//! @brief Format value for bitfield PIT_TCTRLn_CHN.
+#define BF_PIT_TCTRLn_CHN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_CHN), uint32_t) & BM_PIT_TCTRLn_CHN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHN field to a new value.
+#define BW_PIT_TCTRLn_CHN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PIT_TFLGn - Timer Flag Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+typedef union _hw_pit_tflgn
+{
+    uint32_t U;
+    struct _hw_pit_tflgn_bitfields
+    {
+        uint32_t TIF : 1;              //!< [0] Timer Interrupt Flag
+        uint32_t RESERVED0 : 31;       //!< [31:1]
+    } B;
+} hw_pit_tflgn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_TFLGn register
+ */
+//@{
+#define HW_PIT_TFLGn_COUNT (4U)
+
+#define HW_PIT_TFLGn_ADDR(n)     (REGS_PIT_BASE + 0x10CU + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_TFLGn(n)          (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(n))
+#define HW_PIT_TFLGn_RD(n)       (HW_PIT_TFLGn(n).U)
+#define HW_PIT_TFLGn_WR(n, v)    (HW_PIT_TFLGn(n).U = (v))
+#define HW_PIT_TFLGn_SET(n, v)   (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) |  (v)))
+#define HW_PIT_TFLGn_CLR(n, v)   (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) & ~(v)))
+#define HW_PIT_TFLGn_TOG(n, v)   (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_TFLGn bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLGn, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0 - Timeout has not yet occurred.
+ * - 1 - Timeout has occurred.
+ */
+//@{
+#define BP_PIT_TFLGn_TIF     (0U)          //!< Bit position for PIT_TFLGn_TIF.
+#define BM_PIT_TFLGn_TIF     (0x00000001U) //!< Bit mask for PIT_TFLGn_TIF.
+#define BS_PIT_TFLGn_TIF     (1U)          //!< Bit field size in bits for PIT_TFLGn_TIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TFLGn_TIF field.
+#define BR_PIT_TFLGn_TIF(n)  (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF))
+#endif
+
+//! @brief Format value for bitfield PIT_TFLGn_TIF.
+#define BF_PIT_TFLGn_TIF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TFLGn_TIF), uint32_t) & BM_PIT_TFLGn_TIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIF field to a new value.
+#define BW_PIT_TFLGn_TIF(n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_pit_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PIT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_pit
+{
+    __IO hw_pit_mcr_t MCR;                 //!< [0x0] PIT Module Control Register
+    uint8_t _reserved0[252];
+    struct {
+        __IO hw_pit_ldvaln_t LDVALn;       //!< [0x100] Timer Load Value Register
+        __I hw_pit_cvaln_t CVALn;          //!< [0x104] Current Timer Value Register
+        __IO hw_pit_tctrln_t TCTRLn;       //!< [0x108] Timer Control Register
+        __IO hw_pit_tflgn_t TFLGn;         //!< [0x10C] Timer Flag Register
+    } CHANNEL[4];
+} hw_pit_t;
+#pragma pack()
+
+//! @brief Macro to access all PIT registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_PIT</code>.
+#define HW_PIT         (*(hw_pit_t *) REGS_PIT_BASE)
+#endif
+
+#endif // __HW_PIT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h
new file mode 100644
index 0000000000..a67afbd398
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h
@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PMC_REGISTERS_H__
+#define __HW_PMC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - HW_PMC_REGSC - Regulator Status And Control register
+ *
+ * - hw_pmc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PMC_BASE
+#define HW_PMC_INSTANCE_COUNT (1U) //!< Number of instances of the PMC module.
+#define REGS_PMC_BASE (0x4007D000U) //!< Base address for PMC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+typedef union _hw_pmc_lvdsc1
+{
+    uint8_t U;
+    struct _hw_pmc_lvdsc1_bitfields
+    {
+        uint8_t LVDV : 2;              //!< [1:0] Low-Voltage Detect Voltage Select
+        uint8_t RESERVED0 : 2;         //!< [3:2]
+        uint8_t LVDRE : 1;             //!< [4] Low-Voltage Detect Reset Enable
+        uint8_t LVDIE : 1;             //!< [5] Low-Voltage Detect Interrupt Enable
+        uint8_t LVDACK : 1;            //!< [6] Low-Voltage Detect Acknowledge
+        uint8_t LVDF : 1;              //!< [7] Low-Voltage Detect Flag
+    } B;
+} hw_pmc_lvdsc1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+//@{
+#define HW_PMC_LVDSC1_ADDR       (REGS_PMC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PMC_LVDSC1            (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR)
+#define HW_PMC_LVDSC1_RD()       (HW_PMC_LVDSC1.U)
+#define HW_PMC_LVDSC1_WR(v)      (HW_PMC_LVDSC1.U = (v))
+#define HW_PMC_LVDSC1_SET(v)     (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() |  (v)))
+#define HW_PMC_LVDSC1_CLR(v)     (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() & ~(v)))
+#define HW_PMC_LVDSC1_TOG(v)     (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 00 - Low trip point selected (V LVD = V LVDL )
+ * - 01 - High trip point selected (V LVD = V LVDH )
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDV   (0U)          //!< Bit position for PMC_LVDSC1_LVDV.
+#define BM_PMC_LVDSC1_LVDV   (0x03U)       //!< Bit mask for PMC_LVDSC1_LVDV.
+#define BS_PMC_LVDSC1_LVDV   (2U)          //!< Bit field size in bits for PMC_LVDSC1_LVDV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDV field.
+#define BR_PMC_LVDSC1_LVDV   (HW_PMC_LVDSC1.B.LVDV)
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDV.
+#define BF_PMC_LVDSC1_LVDV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDV), uint8_t) & BM_PMC_LVDSC1_LVDV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDV field to a new value.
+#define BW_PMC_LVDSC1_LVDV(v) (HW_PMC_LVDSC1_WR((HW_PMC_LVDSC1_RD() & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0 - LVDF does not generate hardware resets
+ * - 1 - Force an MCU reset when LVDF = 1
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDRE  (4U)          //!< Bit position for PMC_LVDSC1_LVDRE.
+#define BM_PMC_LVDSC1_LVDRE  (0x10U)       //!< Bit mask for PMC_LVDSC1_LVDRE.
+#define BS_PMC_LVDSC1_LVDRE  (1U)          //!< Bit field size in bits for PMC_LVDSC1_LVDRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDRE field.
+#define BR_PMC_LVDSC1_LVDRE  (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE))
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDRE.
+#define BF_PMC_LVDSC1_LVDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDRE), uint8_t) & BM_PMC_LVDSC1_LVDRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDRE field to a new value.
+#define BW_PMC_LVDSC1_LVDRE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0 - Hardware interrupt disabled (use polling)
+ * - 1 - Request a hardware interrupt when LVDF = 1
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDIE  (5U)          //!< Bit position for PMC_LVDSC1_LVDIE.
+#define BM_PMC_LVDSC1_LVDIE  (0x20U)       //!< Bit mask for PMC_LVDSC1_LVDIE.
+#define BS_PMC_LVDSC1_LVDIE  (1U)          //!< Bit field size in bits for PMC_LVDSC1_LVDIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDIE field.
+#define BR_PMC_LVDSC1_LVDIE  (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE))
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDIE.
+#define BF_PMC_LVDSC1_LVDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDIE), uint8_t) & BM_PMC_LVDSC1_LVDIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDIE field to a new value.
+#define BW_PMC_LVDSC1_LVDIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDACK (6U)          //!< Bit position for PMC_LVDSC1_LVDACK.
+#define BM_PMC_LVDSC1_LVDACK (0x40U)       //!< Bit mask for PMC_LVDSC1_LVDACK.
+#define BS_PMC_LVDSC1_LVDACK (1U)          //!< Bit field size in bits for PMC_LVDSC1_LVDACK.
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDACK.
+#define BF_PMC_LVDSC1_LVDACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDACK), uint8_t) & BM_PMC_LVDSC1_LVDACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDACK field to a new value.
+#define BW_PMC_LVDSC1_LVDACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0 - Low-voltage event not detected
+ * - 1 - Low-voltage event detected
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDF   (7U)          //!< Bit position for PMC_LVDSC1_LVDF.
+#define BM_PMC_LVDSC1_LVDF   (0x80U)       //!< Bit mask for PMC_LVDSC1_LVDF.
+#define BS_PMC_LVDSC1_LVDF   (1U)          //!< Bit field size in bits for PMC_LVDSC1_LVDF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDF field.
+#define BR_PMC_LVDSC1_LVDF   (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+typedef union _hw_pmc_lvdsc2
+{
+    uint8_t U;
+    struct _hw_pmc_lvdsc2_bitfields
+    {
+        uint8_t LVWV : 2;              //!< [1:0] Low-Voltage Warning Voltage Select
+        uint8_t RESERVED0 : 3;         //!< [4:2]
+        uint8_t LVWIE : 1;             //!< [5] Low-Voltage Warning Interrupt Enable
+        uint8_t LVWACK : 1;            //!< [6] Low-Voltage Warning Acknowledge
+        uint8_t LVWF : 1;              //!< [7] Low-Voltage Warning Flag
+    } B;
+} hw_pmc_lvdsc2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+//@{
+#define HW_PMC_LVDSC2_ADDR       (REGS_PMC_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PMC_LVDSC2            (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR)
+#define HW_PMC_LVDSC2_RD()       (HW_PMC_LVDSC2.U)
+#define HW_PMC_LVDSC2_WR(v)      (HW_PMC_LVDSC2.U = (v))
+#define HW_PMC_LVDSC2_SET(v)     (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() |  (v)))
+#define HW_PMC_LVDSC2_CLR(v)     (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() & ~(v)))
+#define HW_PMC_LVDSC2_TOG(v)     (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 00 - Low trip point selected (VLVW = VLVW1)
+ * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 11 - High trip point selected (VLVW = VLVW4)
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWV   (0U)          //!< Bit position for PMC_LVDSC2_LVWV.
+#define BM_PMC_LVDSC2_LVWV   (0x03U)       //!< Bit mask for PMC_LVDSC2_LVWV.
+#define BS_PMC_LVDSC2_LVWV   (2U)          //!< Bit field size in bits for PMC_LVDSC2_LVWV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC2_LVWV field.
+#define BR_PMC_LVDSC2_LVWV   (HW_PMC_LVDSC2.B.LVWV)
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC2_LVWV.
+#define BF_PMC_LVDSC2_LVWV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWV), uint8_t) & BM_PMC_LVDSC2_LVWV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVWV field to a new value.
+#define BW_PMC_LVDSC2_LVWV(v) (HW_PMC_LVDSC2_WR((HW_PMC_LVDSC2_RD() & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0 - Hardware interrupt disabled (use polling)
+ * - 1 - Request a hardware interrupt when LVWF = 1
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWIE  (5U)          //!< Bit position for PMC_LVDSC2_LVWIE.
+#define BM_PMC_LVDSC2_LVWIE  (0x20U)       //!< Bit mask for PMC_LVDSC2_LVWIE.
+#define BS_PMC_LVDSC2_LVWIE  (1U)          //!< Bit field size in bits for PMC_LVDSC2_LVWIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC2_LVWIE field.
+#define BR_PMC_LVDSC2_LVWIE  (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE))
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC2_LVWIE.
+#define BF_PMC_LVDSC2_LVWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWIE), uint8_t) & BM_PMC_LVDSC2_LVWIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVWIE field to a new value.
+#define BW_PMC_LVDSC2_LVWIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWACK (6U)          //!< Bit position for PMC_LVDSC2_LVWACK.
+#define BM_PMC_LVDSC2_LVWACK (0x40U)       //!< Bit mask for PMC_LVDSC2_LVWACK.
+#define BS_PMC_LVDSC2_LVWACK (1U)          //!< Bit field size in bits for PMC_LVDSC2_LVWACK.
+
+//! @brief Format value for bitfield PMC_LVDSC2_LVWACK.
+#define BF_PMC_LVDSC2_LVWACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWACK), uint8_t) & BM_PMC_LVDSC2_LVWACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVWACK field to a new value.
+#define BW_PMC_LVDSC2_LVWACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0 - Low-voltage warning event not detected
+ * - 1 - Low-voltage warning event detected
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWF   (7U)          //!< Bit position for PMC_LVDSC2_LVWF.
+#define BM_PMC_LVDSC2_LVWF   (0x80U)       //!< Bit mask for PMC_LVDSC2_LVWF.
+#define BS_PMC_LVDSC2_LVWF   (1U)          //!< Bit field size in bits for PMC_LVDSC2_LVWF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC2_LVWF field.
+#define BR_PMC_LVDSC2_LVWF   (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PMC_REGSC - Regulator Status And Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+typedef union _hw_pmc_regsc
+{
+    uint8_t U;
+    struct _hw_pmc_regsc_bitfields
+    {
+        uint8_t BGBE : 1;              //!< [0] Bandgap Buffer Enable
+        uint8_t RESERVED0 : 1;         //!< [1]
+        uint8_t REGONS : 1;            //!< [2] Regulator In Run Regulation Status
+        uint8_t ACKISO : 1;            //!< [3] Acknowledge Isolation
+        uint8_t BGEN : 1;              //!< [4] Bandgap Enable In VLPx Operation
+        uint8_t RESERVED1 : 3;         //!< [7:5]
+    } B;
+} hw_pmc_regsc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+//@{
+#define HW_PMC_REGSC_ADDR        (REGS_PMC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PMC_REGSC             (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR)
+#define HW_PMC_REGSC_RD()        (HW_PMC_REGSC.U)
+#define HW_PMC_REGSC_WR(v)       (HW_PMC_REGSC.U = (v))
+#define HW_PMC_REGSC_SET(v)      (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() |  (v)))
+#define HW_PMC_REGSC_CLR(v)      (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() & ~(v)))
+#define HW_PMC_REGSC_TOG(v)      (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0 - Bandgap buffer not enabled
+ * - 1 - Bandgap buffer enabled
+ */
+//@{
+#define BP_PMC_REGSC_BGBE    (0U)          //!< Bit position for PMC_REGSC_BGBE.
+#define BM_PMC_REGSC_BGBE    (0x01U)       //!< Bit mask for PMC_REGSC_BGBE.
+#define BS_PMC_REGSC_BGBE    (1U)          //!< Bit field size in bits for PMC_REGSC_BGBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_BGBE field.
+#define BR_PMC_REGSC_BGBE    (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE))
+#endif
+
+//! @brief Format value for bitfield PMC_REGSC_BGBE.
+#define BF_PMC_REGSC_BGBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGBE), uint8_t) & BM_PMC_REGSC_BGBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGBE field to a new value.
+#define BW_PMC_REGSC_BGBE(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0 - Regulator is in stop regulation or in transition to/from it
+ * - 1 - Regulator is in run regulation
+ */
+//@{
+#define BP_PMC_REGSC_REGONS  (2U)          //!< Bit position for PMC_REGSC_REGONS.
+#define BM_PMC_REGSC_REGONS  (0x04U)       //!< Bit mask for PMC_REGSC_REGONS.
+#define BS_PMC_REGSC_REGONS  (1U)          //!< Bit field size in bits for PMC_REGSC_REGONS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_REGONS field.
+#define BR_PMC_REGSC_REGONS  (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_REGONS))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0 - Peripherals and I/O pads are in normal run state.
+ * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+//@{
+#define BP_PMC_REGSC_ACKISO  (3U)          //!< Bit position for PMC_REGSC_ACKISO.
+#define BM_PMC_REGSC_ACKISO  (0x08U)       //!< Bit mask for PMC_REGSC_ACKISO.
+#define BS_PMC_REGSC_ACKISO  (1U)          //!< Bit field size in bits for PMC_REGSC_ACKISO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_ACKISO field.
+#define BR_PMC_REGSC_ACKISO  (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO))
+#endif
+
+//! @brief Format value for bitfield PMC_REGSC_ACKISO.
+#define BF_PMC_REGSC_ACKISO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_ACKISO), uint8_t) & BM_PMC_REGSC_ACKISO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACKISO field to a new value.
+#define BW_PMC_REGSC_ACKISO(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+//@{
+#define BP_PMC_REGSC_BGEN    (4U)          //!< Bit position for PMC_REGSC_BGEN.
+#define BM_PMC_REGSC_BGEN    (0x10U)       //!< Bit mask for PMC_REGSC_BGEN.
+#define BS_PMC_REGSC_BGEN    (1U)          //!< Bit field size in bits for PMC_REGSC_BGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_BGEN field.
+#define BR_PMC_REGSC_BGEN    (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN))
+#endif
+
+//! @brief Format value for bitfield PMC_REGSC_BGEN.
+#define BF_PMC_REGSC_BGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGEN), uint8_t) & BM_PMC_REGSC_BGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGEN field to a new value.
+#define BW_PMC_REGSC_BGEN(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_pmc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PMC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_pmc
+{
+    __IO hw_pmc_lvdsc1_t LVDSC1;           //!< [0x0] Low Voltage Detect Status And Control 1 register
+    __IO hw_pmc_lvdsc2_t LVDSC2;           //!< [0x1] Low Voltage Detect Status And Control 2 register
+    __IO hw_pmc_regsc_t REGSC;             //!< [0x2] Regulator Status And Control register
+} hw_pmc_t;
+#pragma pack()
+
+//! @brief Macro to access all PMC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_PMC</code>.
+#define HW_PMC         (*(hw_pmc_t *) REGS_PMC_BASE)
+#endif
+
+#endif // __HW_PMC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h
new file mode 100644
index 0000000000..ea0a36d225
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h
@@ -0,0 +1,957 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PORT_REGISTERS_H__
+#define __HW_PORT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - HW_PORT_PCRn - Pin Control Register n
+ * - HW_PORT_GPCLR - Global Pin Control Low Register
+ * - HW_PORT_GPCHR - Global Pin Control High Register
+ * - HW_PORT_ISFR - Interrupt Status Flag Register
+ * - HW_PORT_DFER - Digital Filter Enable Register
+ * - HW_PORT_DFCR - Digital Filter Clock Register
+ * - HW_PORT_DFWR - Digital Filter Width Register
+ *
+ * - hw_port_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PORT_BASE
+#define HW_PORT_INSTANCE_COUNT (5U) //!< Number of instances of the PORT module.
+#define HW_PORTA (0U) //!< Instance number for PORTA.
+#define HW_PORTB (1U) //!< Instance number for PORTB.
+#define HW_PORTC (2U) //!< Instance number for PORTC.
+#define HW_PORTD (3U) //!< Instance number for PORTD.
+#define HW_PORTE (4U) //!< Instance number for PORTE.
+#define REGS_PORTA_BASE (0x40049000U) //!< Base address for PORTA.
+#define REGS_PORTB_BASE (0x4004A000U) //!< Base address for PORTB.
+#define REGS_PORTC_BASE (0x4004B000U) //!< Base address for PORTC.
+#define REGS_PORTD_BASE (0x4004C000U) //!< Base address for PORTD.
+#define REGS_PORTE_BASE (0x4004D000U) //!< Base address for PORTE.
+
+//! @brief Table of base addresses for PORT instances.
+static const uint32_t __g_regs_PORT_base_addresses[] = {
+        REGS_PORTA_BASE,
+        REGS_PORTB_BASE,
+        REGS_PORTC_BASE,
+        REGS_PORTD_BASE,
+        REGS_PORTE_BASE,
+    };
+
+//! @brief Get the base address of PORT by instance number.
+//! @param x PORT instance number, from 0 through 4.
+#define REGS_PORT_BASE(x) (__g_regs_PORT_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of PORT.
+#define REGS_PORT_INSTANCE(b) ((b) == REGS_PORTA_BASE ? HW_PORTA : (b) == REGS_PORTB_BASE ? HW_PORTB : (b) == REGS_PORTC_BASE ? HW_PORTC : (b) == REGS_PORTD_BASE ? HW_PORTD : (b) == REGS_PORTE_BASE ? HW_PORTE : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_PCRn - Pin Control Register n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_PCRn - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000742U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+typedef union _hw_port_pcrn
+{
+    uint32_t U;
+    struct _hw_port_pcrn_bitfields
+    {
+        uint32_t PS : 1;               //!< [0] Pull Select
+        uint32_t PE : 1;               //!< [1] Pull Enable
+        uint32_t SRE : 1;              //!< [2] Slew Rate Enable
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t PFE : 1;              //!< [4] Passive Filter Enable
+        uint32_t ODE : 1;              //!< [5] Open Drain Enable
+        uint32_t DSE : 1;              //!< [6] Drive Strength Enable
+        uint32_t RESERVED1 : 1;        //!< [7]
+        uint32_t MUX : 3;              //!< [10:8] Pin Mux Control
+        uint32_t RESERVED2 : 4;        //!< [14:11]
+        uint32_t LK : 1;               //!< [15] Lock Register
+        uint32_t IRQC : 4;             //!< [19:16] Interrupt Configuration
+        uint32_t RESERVED3 : 4;        //!< [23:20]
+        uint32_t ISF : 1;              //!< [24] Interrupt Status Flag
+        uint32_t RESERVED4 : 7;        //!< [31:25]
+    } B;
+} hw_port_pcrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_PCRn register
+ */
+//@{
+#define HW_PORT_PCRn_COUNT (32U)
+
+#define HW_PORT_PCRn_ADDR(x, n)  (REGS_PORT_BASE(x) + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_PCRn(x, n)       (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
+#define HW_PORT_PCRn_RD(x, n)    (HW_PORT_PCRn(x, n).U)
+#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
+#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) |  (v)))
+#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
+#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_PCRn bitfields
+ */
+
+/*!
+ * @name Register PORT_PCRn, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+//@{
+#define BP_PORT_PCRn_PS      (0U)          //!< Bit position for PORT_PCRn_PS.
+#define BM_PORT_PCRn_PS      (0x00000001U) //!< Bit mask for PORT_PCRn_PS.
+#define BS_PORT_PCRn_PS      (1U)          //!< Bit field size in bits for PORT_PCRn_PS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_PS field.
+#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_PS.
+#define BF_PORT_PCRn_PS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PS), uint32_t) & BM_PORT_PCRn_PS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PS field to a new value.
+#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+//@{
+#define BP_PORT_PCRn_PE      (1U)          //!< Bit position for PORT_PCRn_PE.
+#define BM_PORT_PCRn_PE      (0x00000002U) //!< Bit mask for PORT_PCRn_PE.
+#define BS_PORT_PCRn_PE      (1U)          //!< Bit field size in bits for PORT_PCRn_PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_PE field.
+#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_PE.
+#define BF_PORT_PCRn_PE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PE), uint32_t) & BM_PORT_PCRn_PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PE field to a new value.
+#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+//@{
+#define BP_PORT_PCRn_SRE     (2U)          //!< Bit position for PORT_PCRn_SRE.
+#define BM_PORT_PCRn_SRE     (0x00000004U) //!< Bit mask for PORT_PCRn_SRE.
+#define BS_PORT_PCRn_SRE     (1U)          //!< Bit field size in bits for PORT_PCRn_SRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_SRE field.
+#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_SRE.
+#define BF_PORT_PCRn_SRE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_SRE), uint32_t) & BM_PORT_PCRn_SRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRE field to a new value.
+#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Passive input filter is disabled on the corresponding pin.
+ * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
+ *     configured as a digital input. Refer to the device data sheet for filter
+ *     characteristics.
+ */
+//@{
+#define BP_PORT_PCRn_PFE     (4U)          //!< Bit position for PORT_PCRn_PFE.
+#define BM_PORT_PCRn_PFE     (0x00000010U) //!< Bit mask for PORT_PCRn_PFE.
+#define BS_PORT_PCRn_PFE     (1U)          //!< Bit field size in bits for PORT_PCRn_PFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_PFE field.
+#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_PFE.
+#define BF_PORT_PCRn_PFE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PFE), uint32_t) & BM_PORT_PCRn_PFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PFE field to a new value.
+#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Open drain output is disabled on the corresponding pin.
+ * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+//@{
+#define BP_PORT_PCRn_ODE     (5U)          //!< Bit position for PORT_PCRn_ODE.
+#define BM_PORT_PCRn_ODE     (0x00000020U) //!< Bit mask for PORT_PCRn_ODE.
+#define BS_PORT_PCRn_ODE     (1U)          //!< Bit field size in bits for PORT_PCRn_ODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_ODE field.
+#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_ODE.
+#define BF_PORT_PCRn_ODE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ODE), uint32_t) & BM_PORT_PCRn_ODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ODE field to a new value.
+#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+//@{
+#define BP_PORT_PCRn_DSE     (6U)          //!< Bit position for PORT_PCRn_DSE.
+#define BM_PORT_PCRn_DSE     (0x00000040U) //!< Bit mask for PORT_PCRn_DSE.
+#define BS_PORT_PCRn_DSE     (1U)          //!< Bit field size in bits for PORT_PCRn_DSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_DSE field.
+#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_DSE.
+#define BF_PORT_PCRn_DSE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_DSE), uint32_t) & BM_PORT_PCRn_DSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DSE field to a new value.
+#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 000 - Pin disabled (analog).
+ * - 001 - Alternative 1 (GPIO).
+ * - 010 - Alternative 2 (chip-specific).
+ * - 011 - Alternative 3 (chip-specific).
+ * - 100 - Alternative 4 (chip-specific).
+ * - 101 - Alternative 5 (chip-specific).
+ * - 110 - Alternative 6 (chip-specific).
+ * - 111 - Alternative 7 (chip-specific).
+ */
+//@{
+#define BP_PORT_PCRn_MUX     (8U)          //!< Bit position for PORT_PCRn_MUX.
+#define BM_PORT_PCRn_MUX     (0x00000700U) //!< Bit mask for PORT_PCRn_MUX.
+#define BS_PORT_PCRn_MUX     (3U)          //!< Bit field size in bits for PORT_PCRn_MUX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_MUX field.
+#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_MUX.
+#define BF_PORT_PCRn_MUX(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_MUX), uint32_t) & BM_PORT_PCRn_MUX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MUX field to a new value.
+#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field LK[15] (RW)
+ *
+ * Values:
+ * - 0 - Pin Control Register fields [15:0] are not locked.
+ * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+//@{
+#define BP_PORT_PCRn_LK      (15U)         //!< Bit position for PORT_PCRn_LK.
+#define BM_PORT_PCRn_LK      (0x00008000U) //!< Bit mask for PORT_PCRn_LK.
+#define BS_PORT_PCRn_LK      (1U)          //!< Bit field size in bits for PORT_PCRn_LK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_LK field.
+#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_LK.
+#define BF_PORT_PCRn_LK(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_LK), uint32_t) & BM_PORT_PCRn_LK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LK field to a new value.
+#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0000 - Interrupt/DMA request disabled.
+ * - 0001 - DMA request on rising edge.
+ * - 0010 - DMA request on falling edge.
+ * - 0011 - DMA request on either edge.
+ * - 1000 - Interrupt when logic 0.
+ * - 1001 - Interrupt on rising-edge.
+ * - 1010 - Interrupt on falling-edge.
+ * - 1011 - Interrupt on either edge.
+ * - 1100 - Interrupt when logic 1.
+ */
+//@{
+#define BP_PORT_PCRn_IRQC    (16U)         //!< Bit position for PORT_PCRn_IRQC.
+#define BM_PORT_PCRn_IRQC    (0x000F0000U) //!< Bit mask for PORT_PCRn_IRQC.
+#define BS_PORT_PCRn_IRQC    (4U)          //!< Bit field size in bits for PORT_PCRn_IRQC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_IRQC field.
+#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_IRQC.
+#define BF_PORT_PCRn_IRQC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_IRQC), uint32_t) & BM_PORT_PCRn_IRQC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRQC field to a new value.
+#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Configured interrupt is not detected.
+ * - 1 - Configured interrupt is detected. If the pin is configured to generate
+ *     a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured for
+ *     a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+//@{
+#define BP_PORT_PCRn_ISF     (24U)         //!< Bit position for PORT_PCRn_ISF.
+#define BM_PORT_PCRn_ISF     (0x01000000U) //!< Bit mask for PORT_PCRn_ISF.
+#define BS_PORT_PCRn_ISF     (1U)          //!< Bit field size in bits for PORT_PCRn_ISF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_ISF field.
+#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_ISF.
+#define BF_PORT_PCRn_ISF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ISF), uint32_t) & BM_PORT_PCRn_ISF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ISF field to a new value.
+#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_GPCLR - Global Pin Control Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+typedef union _hw_port_gpclr
+{
+    uint32_t U;
+    struct _hw_port_gpclr_bitfields
+    {
+        uint32_t GPWD : 16;            //!< [15:0] Global Pin Write Data
+        uint32_t GPWE : 16;            //!< [31:16] Global Pin Write Enable
+    } B;
+} hw_port_gpclr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+//@{
+#define HW_PORT_GPCLR_ADDR(x)    (REGS_PORT_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_GPCLR(x)         (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
+#define HW_PORT_GPCLR_RD(x)      (HW_PORT_GPCLR(x).U)
+#define HW_PORT_GPCLR_WR(x, v)   (HW_PORT_GPCLR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+//@{
+#define BP_PORT_GPCLR_GPWD   (0U)          //!< Bit position for PORT_GPCLR_GPWD.
+#define BM_PORT_GPCLR_GPWD   (0x0000FFFFU) //!< Bit mask for PORT_GPCLR_GPWD.
+#define BS_PORT_GPCLR_GPWD   (16U)         //!< Bit field size in bits for PORT_GPCLR_GPWD.
+
+//! @brief Format value for bitfield PORT_GPCLR_GPWD.
+#define BF_PORT_GPCLR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWD), uint32_t) & BM_PORT_GPCLR_GPWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWD field to a new value.
+#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0 - Corresponding Pin Control Register is not updated with the value in
+ *     GPWD.
+ * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+//@{
+#define BP_PORT_GPCLR_GPWE   (16U)         //!< Bit position for PORT_GPCLR_GPWE.
+#define BM_PORT_GPCLR_GPWE   (0xFFFF0000U) //!< Bit mask for PORT_GPCLR_GPWE.
+#define BS_PORT_GPCLR_GPWE   (16U)         //!< Bit field size in bits for PORT_GPCLR_GPWE.
+
+//! @brief Format value for bitfield PORT_GPCLR_GPWE.
+#define BF_PORT_GPCLR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWE), uint32_t) & BM_PORT_GPCLR_GPWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWE field to a new value.
+#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_GPCHR - Global Pin Control High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+typedef union _hw_port_gpchr
+{
+    uint32_t U;
+    struct _hw_port_gpchr_bitfields
+    {
+        uint32_t GPWD : 16;            //!< [15:0] Global Pin Write Data
+        uint32_t GPWE : 16;            //!< [31:16] Global Pin Write Enable
+    } B;
+} hw_port_gpchr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+//@{
+#define HW_PORT_GPCHR_ADDR(x)    (REGS_PORT_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_GPCHR(x)         (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
+#define HW_PORT_GPCHR_RD(x)      (HW_PORT_GPCHR(x).U)
+#define HW_PORT_GPCHR_WR(x, v)   (HW_PORT_GPCHR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+//@{
+#define BP_PORT_GPCHR_GPWD   (0U)          //!< Bit position for PORT_GPCHR_GPWD.
+#define BM_PORT_GPCHR_GPWD   (0x0000FFFFU) //!< Bit mask for PORT_GPCHR_GPWD.
+#define BS_PORT_GPCHR_GPWD   (16U)         //!< Bit field size in bits for PORT_GPCHR_GPWD.
+
+//! @brief Format value for bitfield PORT_GPCHR_GPWD.
+#define BF_PORT_GPCHR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWD), uint32_t) & BM_PORT_GPCHR_GPWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWD field to a new value.
+#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0 - Corresponding Pin Control Register is not updated with the value in
+ *     GPWD.
+ * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+//@{
+#define BP_PORT_GPCHR_GPWE   (16U)         //!< Bit position for PORT_GPCHR_GPWE.
+#define BM_PORT_GPCHR_GPWE   (0xFFFF0000U) //!< Bit mask for PORT_GPCHR_GPWE.
+#define BS_PORT_GPCHR_GPWE   (16U)         //!< Bit field size in bits for PORT_GPCHR_GPWE.
+
+//! @brief Format value for bitfield PORT_GPCHR_GPWE.
+#define BF_PORT_GPCHR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWE), uint32_t) & BM_PORT_GPCHR_GPWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWE field to a new value.
+#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_ISFR - Interrupt Status Flag Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+typedef union _hw_port_isfr
+{
+    uint32_t U;
+    struct _hw_port_isfr_bitfields
+    {
+        uint32_t ISF : 32;             //!< [31:0] Interrupt Status Flag
+    } B;
+} hw_port_isfr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+//@{
+#define HW_PORT_ISFR_ADDR(x)     (REGS_PORT_BASE(x) + 0xA0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_ISFR(x)          (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
+#define HW_PORT_ISFR_RD(x)       (HW_PORT_ISFR(x).U)
+#define HW_PORT_ISFR_WR(x, v)    (HW_PORT_ISFR(x).U = (v))
+#define HW_PORT_ISFR_SET(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) |  (v)))
+#define HW_PORT_ISFR_CLR(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
+#define HW_PORT_ISFR_TOG(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_ISFR bitfields
+ */
+
+/*!
+ * @name Register PORT_ISFR, field ISF[31:0] (W1C)
+ *
+ * Each bit in the field indicates the detection of the configured interrupt of
+ * the same number as the field.
+ *
+ * Values:
+ * - 0 - Configured interrupt is not detected.
+ * - 1 - Configured interrupt is detected. If the pin is configured to generate
+ *     a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured for
+ *     a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+//@{
+#define BP_PORT_ISFR_ISF     (0U)          //!< Bit position for PORT_ISFR_ISF.
+#define BM_PORT_ISFR_ISF     (0xFFFFFFFFU) //!< Bit mask for PORT_ISFR_ISF.
+#define BS_PORT_ISFR_ISF     (32U)         //!< Bit field size in bits for PORT_ISFR_ISF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_ISFR_ISF field.
+#define BR_PORT_ISFR_ISF(x)  (HW_PORT_ISFR(x).U)
+#endif
+
+//! @brief Format value for bitfield PORT_ISFR_ISF.
+#define BF_PORT_ISFR_ISF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_ISFR_ISF), uint32_t) & BM_PORT_ISFR_ISF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ISF field to a new value.
+#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_DFER - Digital Filter Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+typedef union _hw_port_dfer
+{
+    uint32_t U;
+    struct _hw_port_dfer_bitfields
+    {
+        uint32_t DFE : 32;             //!< [31:0] Digital Filter Enable
+    } B;
+} hw_port_dfer_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+//@{
+#define HW_PORT_DFER_ADDR(x)     (REGS_PORT_BASE(x) + 0xC0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_DFER(x)          (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
+#define HW_PORT_DFER_RD(x)       (HW_PORT_DFER(x).U)
+#define HW_PORT_DFER_WR(x, v)    (HW_PORT_DFER(x).U = (v))
+#define HW_PORT_DFER_SET(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) |  (v)))
+#define HW_PORT_DFER_CLR(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
+#define HW_PORT_DFER_TOG(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_DFER bitfields
+ */
+
+/*!
+ * @name Register PORT_DFER, field DFE[31:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * The output of each digital filter is reset to zero at system reset and whenever
+ * the digital filter is disabled. Each bit in the field enables the digital
+ * filter of the same number as the field.
+ *
+ * Values:
+ * - 0 - Digital filter is disabled on the corresponding pin and output of the
+ *     digital filter is reset to zero.
+ * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
+ *     configured as a digital input.
+ */
+//@{
+#define BP_PORT_DFER_DFE     (0U)          //!< Bit position for PORT_DFER_DFE.
+#define BM_PORT_DFER_DFE     (0xFFFFFFFFU) //!< Bit mask for PORT_DFER_DFE.
+#define BS_PORT_DFER_DFE     (32U)         //!< Bit field size in bits for PORT_DFER_DFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_DFER_DFE field.
+#define BR_PORT_DFER_DFE(x)  (HW_PORT_DFER(x).U)
+#endif
+
+//! @brief Format value for bitfield PORT_DFER_DFE.
+#define BF_PORT_DFER_DFE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFER_DFE), uint32_t) & BM_PORT_DFER_DFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DFE field to a new value.
+#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_DFCR - Digital Filter Clock Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+typedef union _hw_port_dfcr
+{
+    uint32_t U;
+    struct _hw_port_dfcr_bitfields
+    {
+        uint32_t CS : 1;               //!< [0] Clock Source
+        uint32_t RESERVED0 : 31;       //!< [31:1]
+    } B;
+} hw_port_dfcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+//@{
+#define HW_PORT_DFCR_ADDR(x)     (REGS_PORT_BASE(x) + 0xC4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_DFCR(x)          (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
+#define HW_PORT_DFCR_RD(x)       (HW_PORT_DFCR(x).U)
+#define HW_PORT_DFCR_WR(x, v)    (HW_PORT_DFCR(x).U = (v))
+#define HW_PORT_DFCR_SET(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) |  (v)))
+#define HW_PORT_DFCR_CLR(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
+#define HW_PORT_DFCR_TOG(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0 - Digital filters are clocked by the bus clock.
+ * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+//@{
+#define BP_PORT_DFCR_CS      (0U)          //!< Bit position for PORT_DFCR_CS.
+#define BM_PORT_DFCR_CS      (0x00000001U) //!< Bit mask for PORT_DFCR_CS.
+#define BS_PORT_DFCR_CS      (1U)          //!< Bit field size in bits for PORT_DFCR_CS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_DFCR_CS field.
+#define BR_PORT_DFCR_CS(x)   (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
+#endif
+
+//! @brief Format value for bitfield PORT_DFCR_CS.
+#define BF_PORT_DFCR_CS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFCR_CS), uint32_t) & BM_PORT_DFCR_CS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CS field to a new value.
+#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_DFWR - Digital Filter Width Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+typedef union _hw_port_dfwr
+{
+    uint32_t U;
+    struct _hw_port_dfwr_bitfields
+    {
+        uint32_t FILT : 5;             //!< [4:0] Filter Length
+        uint32_t RESERVED0 : 27;       //!< [31:5]
+    } B;
+} hw_port_dfwr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+//@{
+#define HW_PORT_DFWR_ADDR(x)     (REGS_PORT_BASE(x) + 0xC8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_DFWR(x)          (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
+#define HW_PORT_DFWR_RD(x)       (HW_PORT_DFWR(x).U)
+#define HW_PORT_DFWR_WR(x, v)    (HW_PORT_DFWR(x).U = (v))
+#define HW_PORT_DFWR_SET(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) |  (v)))
+#define HW_PORT_DFWR_CLR(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
+#define HW_PORT_DFWR_TOG(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+//@{
+#define BP_PORT_DFWR_FILT    (0U)          //!< Bit position for PORT_DFWR_FILT.
+#define BM_PORT_DFWR_FILT    (0x0000001FU) //!< Bit mask for PORT_DFWR_FILT.
+#define BS_PORT_DFWR_FILT    (5U)          //!< Bit field size in bits for PORT_DFWR_FILT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_DFWR_FILT field.
+#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
+#endif
+
+//! @brief Format value for bitfield PORT_DFWR_FILT.
+#define BF_PORT_DFWR_FILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFWR_FILT), uint32_t) & BM_PORT_DFWR_FILT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILT field to a new value.
+#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_port_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PORT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_port
+{
+    __IO hw_port_pcrn_t PCRn[32];          //!< [0x0] Pin Control Register n
+    __O hw_port_gpclr_t GPCLR;             //!< [0x80] Global Pin Control Low Register
+    __O hw_port_gpchr_t GPCHR;             //!< [0x84] Global Pin Control High Register
+    uint8_t _reserved0[24];
+    __IO hw_port_isfr_t ISFR;              //!< [0xA0] Interrupt Status Flag Register
+    uint8_t _reserved1[28];
+    __IO hw_port_dfer_t DFER;              //!< [0xC0] Digital Filter Enable Register
+    __IO hw_port_dfcr_t DFCR;              //!< [0xC4] Digital Filter Clock Register
+    __IO hw_port_dfwr_t DFWR;              //!< [0xC8] Digital Filter Width Register
+} hw_port_t;
+#pragma pack()
+
+//! @brief Macro to access all PORT registers.
+//! @param x PORT instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_PORT(0)</code>.
+#define HW_PORT(x)     (*(hw_port_t *) REGS_PORT_BASE(x))
+#endif
+
+#endif // __HW_PORT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h
new file mode 100644
index 0000000000..efcc81ddc2
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h
@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RCM_REGISTERS_H__
+#define __HW_RCM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - HW_RCM_SRS0 - System Reset Status Register 0
+ * - HW_RCM_SRS1 - System Reset Status Register 1
+ * - HW_RCM_RPFC - Reset Pin Filter Control register
+ * - HW_RCM_RPFW - Reset Pin Filter Width register
+ * - HW_RCM_MR - Mode Register
+ *
+ * - hw_rcm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RCM_BASE
+#define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
+#define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_SRS0 - System Reset Status Register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+typedef union _hw_rcm_srs0
+{
+    uint8_t U;
+    struct _hw_rcm_srs0_bitfields
+    {
+        uint8_t WAKEUP : 1;            //!< [0] Low Leakage Wakeup Reset
+        uint8_t LVD : 1;               //!< [1] Low-Voltage Detect Reset
+        uint8_t LOC : 1;               //!< [2] Loss-of-Clock Reset
+        uint8_t LOL : 1;               //!< [3] Loss-of-Lock Reset
+        uint8_t RESERVED0 : 1;         //!< [4]
+        uint8_t WDOGb : 1;             //!< [5] Watchdog
+        uint8_t PIN : 1;               //!< [6] External Reset Pin
+        uint8_t POR : 1;               //!< [7] Power-On Reset
+    } B;
+} hw_rcm_srs0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+//@{
+#define HW_RCM_SRS0_ADDR         (REGS_RCM_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_SRS0              (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
+#define HW_RCM_SRS0_RD()         (HW_RCM_SRS0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0 - Reset not caused by LLWU module wakeup source
+ * - 1 - Reset caused by LLWU module wakeup source
+ */
+//@{
+#define BP_RCM_SRS0_WAKEUP   (0U)          //!< Bit position for RCM_SRS0_WAKEUP.
+#define BM_RCM_SRS0_WAKEUP   (0x01U)       //!< Bit mask for RCM_SRS0_WAKEUP.
+#define BS_RCM_SRS0_WAKEUP   (1U)          //!< Bit field size in bits for RCM_SRS0_WAKEUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_WAKEUP field.
+#define BR_RCM_SRS0_WAKEUP   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0 - Reset not caused by LVD trip or POR
+ * - 1 - Reset caused by LVD trip or POR
+ */
+//@{
+#define BP_RCM_SRS0_LVD      (1U)          //!< Bit position for RCM_SRS0_LVD.
+#define BM_RCM_SRS0_LVD      (0x02U)       //!< Bit mask for RCM_SRS0_LVD.
+#define BS_RCM_SRS0_LVD      (1U)          //!< Bit field size in bits for RCM_SRS0_LVD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_LVD field.
+#define BR_RCM_SRS0_LVD      (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0 - Reset not caused by a loss of external clock.
+ * - 1 - Reset caused by a loss of external clock.
+ */
+//@{
+#define BP_RCM_SRS0_LOC      (2U)          //!< Bit position for RCM_SRS0_LOC.
+#define BM_RCM_SRS0_LOC      (0x04U)       //!< Bit mask for RCM_SRS0_LOC.
+#define BS_RCM_SRS0_LOC      (1U)          //!< Bit field size in bits for RCM_SRS0_LOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_LOC field.
+#define BR_RCM_SRS0_LOC      (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0 - Reset not caused by a loss of lock in the PLL
+ * - 1 - Reset caused by a loss of lock in the PLL
+ */
+//@{
+#define BP_RCM_SRS0_LOL      (3U)          //!< Bit position for RCM_SRS0_LOL.
+#define BM_RCM_SRS0_LOL      (0x08U)       //!< Bit mask for RCM_SRS0_LOL.
+#define BS_RCM_SRS0_LOL      (1U)          //!< Bit field size in bits for RCM_SRS0_LOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_LOL field.
+#define BR_RCM_SRS0_LOL      (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0 - Reset not caused by watchdog timeout
+ * - 1 - Reset caused by watchdog timeout
+ */
+//@{
+#define BP_RCM_SRS0_WDOG     (5U)          //!< Bit position for RCM_SRS0_WDOG.
+#define BM_RCM_SRS0_WDOG     (0x20U)       //!< Bit mask for RCM_SRS0_WDOG.
+#define BS_RCM_SRS0_WDOG     (1U)          //!< Bit field size in bits for RCM_SRS0_WDOG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_WDOG field.
+#define BR_RCM_SRS0_WDOG     (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0 - Reset not caused by external reset pin
+ * - 1 - Reset caused by external reset pin
+ */
+//@{
+#define BP_RCM_SRS0_PIN      (6U)          //!< Bit position for RCM_SRS0_PIN.
+#define BM_RCM_SRS0_PIN      (0x40U)       //!< Bit mask for RCM_SRS0_PIN.
+#define BS_RCM_SRS0_PIN      (1U)          //!< Bit field size in bits for RCM_SRS0_PIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_PIN field.
+#define BR_RCM_SRS0_PIN      (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0 - Reset not caused by POR
+ * - 1 - Reset caused by POR
+ */
+//@{
+#define BP_RCM_SRS0_POR      (7U)          //!< Bit position for RCM_SRS0_POR.
+#define BM_RCM_SRS0_POR      (0x80U)       //!< Bit mask for RCM_SRS0_POR.
+#define BS_RCM_SRS0_POR      (1U)          //!< Bit field size in bits for RCM_SRS0_POR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_POR field.
+#define BR_RCM_SRS0_POR      (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_SRS1 - System Reset Status Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+typedef union _hw_rcm_srs1
+{
+    uint8_t U;
+    struct _hw_rcm_srs1_bitfields
+    {
+        uint8_t JTAG : 1;              //!< [0] JTAG Generated Reset
+        uint8_t LOCKUP : 1;            //!< [1] Core Lockup
+        uint8_t SW : 1;                //!< [2] Software
+        uint8_t MDM_AP : 1;            //!< [3] MDM-AP System Reset Request
+        uint8_t EZPT : 1;              //!< [4] EzPort Reset
+        uint8_t SACKERR : 1;           //!< [5] Stop Mode Acknowledge Error Reset
+        uint8_t RESERVED0 : 2;         //!< [7:6]
+    } B;
+} hw_rcm_srs1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+//@{
+#define HW_RCM_SRS1_ADDR         (REGS_RCM_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_SRS1              (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
+#define HW_RCM_SRS1_RD()         (HW_RCM_SRS1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0 - Reset not caused by JTAG
+ * - 1 - Reset caused by JTAG
+ */
+//@{
+#define BP_RCM_SRS1_JTAG     (0U)          //!< Bit position for RCM_SRS1_JTAG.
+#define BM_RCM_SRS1_JTAG     (0x01U)       //!< Bit mask for RCM_SRS1_JTAG.
+#define BS_RCM_SRS1_JTAG     (1U)          //!< Bit field size in bits for RCM_SRS1_JTAG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_JTAG field.
+#define BR_RCM_SRS1_JTAG     (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0 - Reset not caused by core LOCKUP event
+ * - 1 - Reset caused by core LOCKUP event
+ */
+//@{
+#define BP_RCM_SRS1_LOCKUP   (1U)          //!< Bit position for RCM_SRS1_LOCKUP.
+#define BM_RCM_SRS1_LOCKUP   (0x02U)       //!< Bit mask for RCM_SRS1_LOCKUP.
+#define BS_RCM_SRS1_LOCKUP   (1U)          //!< Bit field size in bits for RCM_SRS1_LOCKUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_LOCKUP field.
+#define BR_RCM_SRS1_LOCKUP   (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+//@{
+#define BP_RCM_SRS1_SW       (2U)          //!< Bit position for RCM_SRS1_SW.
+#define BM_RCM_SRS1_SW       (0x04U)       //!< Bit mask for RCM_SRS1_SW.
+#define BS_RCM_SRS1_SW       (1U)          //!< Bit field size in bits for RCM_SRS1_SW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_SW field.
+#define BR_RCM_SRS1_SW       (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+//@{
+#define BP_RCM_SRS1_MDM_AP   (3U)          //!< Bit position for RCM_SRS1_MDM_AP.
+#define BM_RCM_SRS1_MDM_AP   (0x08U)       //!< Bit mask for RCM_SRS1_MDM_AP.
+#define BS_RCM_SRS1_MDM_AP   (1U)          //!< Bit field size in bits for RCM_SRS1_MDM_AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_MDM_AP field.
+#define BR_RCM_SRS1_MDM_AP   (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0 - Reset not caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ * - 1 - Reset caused by EzPort receiving the RESET command while the device is
+ *     in EzPort mode
+ */
+//@{
+#define BP_RCM_SRS1_EZPT     (4U)          //!< Bit position for RCM_SRS1_EZPT.
+#define BM_RCM_SRS1_EZPT     (0x10U)       //!< Bit mask for RCM_SRS1_EZPT.
+#define BS_RCM_SRS1_EZPT     (1U)          //!< Bit field size in bits for RCM_SRS1_EZPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_EZPT field.
+#define BR_RCM_SRS1_EZPT     (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
+ *     mode
+ */
+//@{
+#define BP_RCM_SRS1_SACKERR  (5U)          //!< Bit position for RCM_SRS1_SACKERR.
+#define BM_RCM_SRS1_SACKERR  (0x20U)       //!< Bit mask for RCM_SRS1_SACKERR.
+#define BS_RCM_SRS1_SACKERR  (1U)          //!< Bit field size in bits for RCM_SRS1_SACKERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_SACKERR field.
+#define BR_RCM_SRS1_SACKERR  (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_RPFC - Reset Pin Filter Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+typedef union _hw_rcm_rpfc
+{
+    uint8_t U;
+    struct _hw_rcm_rpfc_bitfields
+    {
+        uint8_t RSTFLTSRW : 2;         //!< [1:0] Reset Pin Filter Select in Run and
+                                       //! Wait Modes
+        uint8_t RSTFLTSS : 1;          //!< [2] Reset Pin Filter Select in Stop Mode
+        uint8_t RESERVED0 : 5;         //!< [7:3]
+    } B;
+} hw_rcm_rpfc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+//@{
+#define HW_RCM_RPFC_ADDR         (REGS_RCM_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_RPFC              (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
+#define HW_RCM_RPFC_RD()         (HW_RCM_RPFC.U)
+#define HW_RCM_RPFC_WR(v)        (HW_RCM_RPFC.U = (v))
+#define HW_RCM_RPFC_SET(v)       (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() |  (v)))
+#define HW_RCM_RPFC_CLR(v)       (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
+#define HW_RCM_RPFC_TOG(v)       (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 00 - All filtering disabled
+ * - 01 - Bus clock filter enabled for normal operation
+ * - 10 - LPO clock filter enabled for normal operation
+ * - 11 - Reserved
+ */
+//@{
+#define BP_RCM_RPFC_RSTFLTSRW (0U)         //!< Bit position for RCM_RPFC_RSTFLTSRW.
+#define BM_RCM_RPFC_RSTFLTSRW (0x03U)      //!< Bit mask for RCM_RPFC_RSTFLTSRW.
+#define BS_RCM_RPFC_RSTFLTSRW (2U)         //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
+#define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
+#endif
+
+//! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
+#define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFLTSRW field to a new value.
+#define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0 - All filtering disabled
+ * - 1 - LPO clock filter enabled
+ */
+//@{
+#define BP_RCM_RPFC_RSTFLTSS (2U)          //!< Bit position for RCM_RPFC_RSTFLTSS.
+#define BM_RCM_RPFC_RSTFLTSS (0x04U)       //!< Bit mask for RCM_RPFC_RSTFLTSS.
+#define BS_RCM_RPFC_RSTFLTSS (1U)          //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
+#define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
+#endif
+
+//! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
+#define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFLTSS field to a new value.
+#define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_RPFW - Reset Pin Filter Width register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+typedef union _hw_rcm_rpfw
+{
+    uint8_t U;
+    struct _hw_rcm_rpfw_bitfields
+    {
+        uint8_t RSTFLTSEL : 5;         //!< [4:0] Reset Pin Filter Bus Clock Select
+        uint8_t RESERVED0 : 3;         //!< [7:5]
+    } B;
+} hw_rcm_rpfw_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+//@{
+#define HW_RCM_RPFW_ADDR         (REGS_RCM_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_RPFW              (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
+#define HW_RCM_RPFW_RD()         (HW_RCM_RPFW.U)
+#define HW_RCM_RPFW_WR(v)        (HW_RCM_RPFW.U = (v))
+#define HW_RCM_RPFW_SET(v)       (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() |  (v)))
+#define HW_RCM_RPFW_CLR(v)       (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
+#define HW_RCM_RPFW_TOG(v)       (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 00000 - Bus clock filter count is 1
+ * - 00001 - Bus clock filter count is 2
+ * - 00010 - Bus clock filter count is 3
+ * - 00011 - Bus clock filter count is 4
+ * - 00100 - Bus clock filter count is 5
+ * - 00101 - Bus clock filter count is 6
+ * - 00110 - Bus clock filter count is 7
+ * - 00111 - Bus clock filter count is 8
+ * - 01000 - Bus clock filter count is 9
+ * - 01001 - Bus clock filter count is 10
+ * - 01010 - Bus clock filter count is 11
+ * - 01011 - Bus clock filter count is 12
+ * - 01100 - Bus clock filter count is 13
+ * - 01101 - Bus clock filter count is 14
+ * - 01110 - Bus clock filter count is 15
+ * - 01111 - Bus clock filter count is 16
+ * - 10000 - Bus clock filter count is 17
+ * - 10001 - Bus clock filter count is 18
+ * - 10010 - Bus clock filter count is 19
+ * - 10011 - Bus clock filter count is 20
+ * - 10100 - Bus clock filter count is 21
+ * - 10101 - Bus clock filter count is 22
+ * - 10110 - Bus clock filter count is 23
+ * - 10111 - Bus clock filter count is 24
+ * - 11000 - Bus clock filter count is 25
+ * - 11001 - Bus clock filter count is 26
+ * - 11010 - Bus clock filter count is 27
+ * - 11011 - Bus clock filter count is 28
+ * - 11100 - Bus clock filter count is 29
+ * - 11101 - Bus clock filter count is 30
+ * - 11110 - Bus clock filter count is 31
+ * - 11111 - Bus clock filter count is 32
+ */
+//@{
+#define BP_RCM_RPFW_RSTFLTSEL (0U)         //!< Bit position for RCM_RPFW_RSTFLTSEL.
+#define BM_RCM_RPFW_RSTFLTSEL (0x1FU)      //!< Bit mask for RCM_RPFW_RSTFLTSEL.
+#define BS_RCM_RPFW_RSTFLTSEL (5U)         //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
+#define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
+#endif
+
+//! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
+#define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFLTSEL field to a new value.
+#define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_MR - Mode Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+typedef union _hw_rcm_mr
+{
+    uint8_t U;
+    struct _hw_rcm_mr_bitfields
+    {
+        uint8_t RESERVED0 : 1;         //!< [0]
+        uint8_t EZP_MS : 1;            //!< [1] EZP_MS_B pin state
+        uint8_t RESERVED1 : 6;         //!< [7:2]
+    } B;
+} hw_rcm_mr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+//@{
+#define HW_RCM_MR_ADDR           (REGS_RCM_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_MR                (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
+#define HW_RCM_MR_RD()           (HW_RCM_MR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0 - Pin deasserted (logic 1)
+ * - 1 - Pin asserted (logic 0)
+ */
+//@{
+#define BP_RCM_MR_EZP_MS     (1U)          //!< Bit position for RCM_MR_EZP_MS.
+#define BM_RCM_MR_EZP_MS     (0x02U)       //!< Bit mask for RCM_MR_EZP_MS.
+#define BS_RCM_MR_EZP_MS     (1U)          //!< Bit field size in bits for RCM_MR_EZP_MS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_MR_EZP_MS field.
+#define BR_RCM_MR_EZP_MS     (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rcm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RCM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rcm
+{
+    __I hw_rcm_srs0_t SRS0;                //!< [0x0] System Reset Status Register 0
+    __I hw_rcm_srs1_t SRS1;                //!< [0x1] System Reset Status Register 1
+    uint8_t _reserved0[2];
+    __IO hw_rcm_rpfc_t RPFC;               //!< [0x4] Reset Pin Filter Control register
+    __IO hw_rcm_rpfw_t RPFW;               //!< [0x5] Reset Pin Filter Width register
+    uint8_t _reserved1[1];
+    __I hw_rcm_mr_t MR;                    //!< [0x7] Mode Register
+} hw_rcm_t;
+#pragma pack()
+
+//! @brief Macro to access all RCM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_RCM</code>.
+#define HW_RCM         (*(hw_rcm_t *) REGS_RCM_BASE)
+#endif
+
+#endif // __HW_RCM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h
new file mode 100644
index 0000000000..5c93b0b79c
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RFSYS_REGISTERS_H__
+#define __HW_RFSYS_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - HW_RFSYS_REGn - Register file register
+ *
+ * - hw_rfsys_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RFSYS_BASE
+#define HW_RFSYS_INSTANCE_COUNT (1U) //!< Number of instances of the RFSYS module.
+#define REGS_RFSYS_BASE (0x40041000U) //!< Base address for RFSYS.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RFSYS_REGn - Register file register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RFSYS_REGn - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+typedef union _hw_rfsys_regn
+{
+    uint32_t U;
+    struct _hw_rfsys_regn_bitfields
+    {
+        uint32_t LL : 8;               //!< [7:0]
+        uint32_t LH : 8;               //!< [15:8]
+        uint32_t HL : 8;               //!< [23:16]
+        uint32_t HH : 8;               //!< [31:24]
+    } B;
+} hw_rfsys_regn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RFSYS_REGn register
+ */
+//@{
+#define HW_RFSYS_REGn_COUNT (8U)
+
+#define HW_RFSYS_REGn_ADDR(n)    (REGS_RFSYS_BASE + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RFSYS_REGn(n)         (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(n))
+#define HW_RFSYS_REGn_RD(n)      (HW_RFSYS_REGn(n).U)
+#define HW_RFSYS_REGn_WR(n, v)   (HW_RFSYS_REGn(n).U = (v))
+#define HW_RFSYS_REGn_SET(n, v)  (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) |  (v)))
+#define HW_RFSYS_REGn_CLR(n, v)  (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) & ~(v)))
+#define HW_RFSYS_REGn_TOG(n, v)  (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RFSYS_REGn bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REGn, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+//@{
+#define BP_RFSYS_REGn_LL     (0U)          //!< Bit position for RFSYS_REGn_LL.
+#define BM_RFSYS_REGn_LL     (0x000000FFU) //!< Bit mask for RFSYS_REGn_LL.
+#define BS_RFSYS_REGn_LL     (8U)          //!< Bit field size in bits for RFSYS_REGn_LL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_LL field.
+#define BR_RFSYS_REGn_LL(n)  (HW_RFSYS_REGn(n).B.LL)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_LL.
+#define BF_RFSYS_REGn_LL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LL), uint32_t) & BM_RFSYS_REGn_LL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LL field to a new value.
+#define BW_RFSYS_REGn_LL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFSYS_REGn, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+//@{
+#define BP_RFSYS_REGn_LH     (8U)          //!< Bit position for RFSYS_REGn_LH.
+#define BM_RFSYS_REGn_LH     (0x0000FF00U) //!< Bit mask for RFSYS_REGn_LH.
+#define BS_RFSYS_REGn_LH     (8U)          //!< Bit field size in bits for RFSYS_REGn_LH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_LH field.
+#define BR_RFSYS_REGn_LH(n)  (HW_RFSYS_REGn(n).B.LH)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_LH.
+#define BF_RFSYS_REGn_LH(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LH), uint32_t) & BM_RFSYS_REGn_LH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LH field to a new value.
+#define BW_RFSYS_REGn_LH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFSYS_REGn, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+//@{
+#define BP_RFSYS_REGn_HL     (16U)         //!< Bit position for RFSYS_REGn_HL.
+#define BM_RFSYS_REGn_HL     (0x00FF0000U) //!< Bit mask for RFSYS_REGn_HL.
+#define BS_RFSYS_REGn_HL     (8U)          //!< Bit field size in bits for RFSYS_REGn_HL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_HL field.
+#define BR_RFSYS_REGn_HL(n)  (HW_RFSYS_REGn(n).B.HL)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_HL.
+#define BF_RFSYS_REGn_HL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HL), uint32_t) & BM_RFSYS_REGn_HL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HL field to a new value.
+#define BW_RFSYS_REGn_HL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFSYS_REGn, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+//@{
+#define BP_RFSYS_REGn_HH     (24U)         //!< Bit position for RFSYS_REGn_HH.
+#define BM_RFSYS_REGn_HH     (0xFF000000U) //!< Bit mask for RFSYS_REGn_HH.
+#define BS_RFSYS_REGn_HH     (8U)          //!< Bit field size in bits for RFSYS_REGn_HH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_HH field.
+#define BR_RFSYS_REGn_HH(n)  (HW_RFSYS_REGn(n).B.HH)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_HH.
+#define BF_RFSYS_REGn_HH(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HH), uint32_t) & BM_RFSYS_REGn_HH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HH field to a new value.
+#define BW_RFSYS_REGn_HH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rfsys_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RFSYS module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rfsys
+{
+    __IO hw_rfsys_regn_t REGn[8];          //!< [0x0] Register file register
+} hw_rfsys_t;
+#pragma pack()
+
+//! @brief Macro to access all RFSYS registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_RFSYS</code>.
+#define HW_RFSYS       (*(hw_rfsys_t *) REGS_RFSYS_BASE)
+#endif
+
+#endif // __HW_RFSYS_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h
new file mode 100644
index 0000000000..19b6d917ed
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RFVBAT_REGISTERS_H__
+#define __HW_RFVBAT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - HW_RFVBAT_REGn - VBAT register file register
+ *
+ * - hw_rfvbat_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RFVBAT_BASE
+#define HW_RFVBAT_INSTANCE_COUNT (1U) //!< Number of instances of the RFVBAT module.
+#define REGS_RFVBAT_BASE (0x4003E000U) //!< Base address for RFVBAT.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RFVBAT_REGn - VBAT register file register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RFVBAT_REGn - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+typedef union _hw_rfvbat_regn
+{
+    uint32_t U;
+    struct _hw_rfvbat_regn_bitfields
+    {
+        uint32_t LL : 8;               //!< [7:0]
+        uint32_t LH : 8;               //!< [15:8]
+        uint32_t HL : 8;               //!< [23:16]
+        uint32_t HH : 8;               //!< [31:24]
+    } B;
+} hw_rfvbat_regn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RFVBAT_REGn register
+ */
+//@{
+#define HW_RFVBAT_REGn_COUNT (8U)
+
+#define HW_RFVBAT_REGn_ADDR(n)   (REGS_RFVBAT_BASE + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RFVBAT_REGn(n)        (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(n))
+#define HW_RFVBAT_REGn_RD(n)     (HW_RFVBAT_REGn(n).U)
+#define HW_RFVBAT_REGn_WR(n, v)  (HW_RFVBAT_REGn(n).U = (v))
+#define HW_RFVBAT_REGn_SET(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) |  (v)))
+#define HW_RFVBAT_REGn_CLR(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) & ~(v)))
+#define HW_RFVBAT_REGn_TOG(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RFVBAT_REGn bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REGn, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+//@{
+#define BP_RFVBAT_REGn_LL    (0U)          //!< Bit position for RFVBAT_REGn_LL.
+#define BM_RFVBAT_REGn_LL    (0x000000FFU) //!< Bit mask for RFVBAT_REGn_LL.
+#define BS_RFVBAT_REGn_LL    (8U)          //!< Bit field size in bits for RFVBAT_REGn_LL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_LL field.
+#define BR_RFVBAT_REGn_LL(n) (HW_RFVBAT_REGn(n).B.LL)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_LL.
+#define BF_RFVBAT_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LL), uint32_t) & BM_RFVBAT_REGn_LL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LL field to a new value.
+#define BW_RFVBAT_REGn_LL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFVBAT_REGn, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+//@{
+#define BP_RFVBAT_REGn_LH    (8U)          //!< Bit position for RFVBAT_REGn_LH.
+#define BM_RFVBAT_REGn_LH    (0x0000FF00U) //!< Bit mask for RFVBAT_REGn_LH.
+#define BS_RFVBAT_REGn_LH    (8U)          //!< Bit field size in bits for RFVBAT_REGn_LH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_LH field.
+#define BR_RFVBAT_REGn_LH(n) (HW_RFVBAT_REGn(n).B.LH)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_LH.
+#define BF_RFVBAT_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LH), uint32_t) & BM_RFVBAT_REGn_LH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LH field to a new value.
+#define BW_RFVBAT_REGn_LH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFVBAT_REGn, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+//@{
+#define BP_RFVBAT_REGn_HL    (16U)         //!< Bit position for RFVBAT_REGn_HL.
+#define BM_RFVBAT_REGn_HL    (0x00FF0000U) //!< Bit mask for RFVBAT_REGn_HL.
+#define BS_RFVBAT_REGn_HL    (8U)          //!< Bit field size in bits for RFVBAT_REGn_HL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_HL field.
+#define BR_RFVBAT_REGn_HL(n) (HW_RFVBAT_REGn(n).B.HL)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_HL.
+#define BF_RFVBAT_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HL), uint32_t) & BM_RFVBAT_REGn_HL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HL field to a new value.
+#define BW_RFVBAT_REGn_HL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFVBAT_REGn, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+//@{
+#define BP_RFVBAT_REGn_HH    (24U)         //!< Bit position for RFVBAT_REGn_HH.
+#define BM_RFVBAT_REGn_HH    (0xFF000000U) //!< Bit mask for RFVBAT_REGn_HH.
+#define BS_RFVBAT_REGn_HH    (8U)          //!< Bit field size in bits for RFVBAT_REGn_HH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_HH field.
+#define BR_RFVBAT_REGn_HH(n) (HW_RFVBAT_REGn(n).B.HH)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_HH.
+#define BF_RFVBAT_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HH), uint32_t) & BM_RFVBAT_REGn_HH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HH field to a new value.
+#define BW_RFVBAT_REGn_HH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rfvbat_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RFVBAT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rfvbat
+{
+    __IO hw_rfvbat_regn_t REGn[8];         //!< [0x0] VBAT register file register
+} hw_rfvbat_t;
+#pragma pack()
+
+//! @brief Macro to access all RFVBAT registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_RFVBAT</code>.
+#define HW_RFVBAT      (*(hw_rfvbat_t *) REGS_RFVBAT_BASE)
+#endif
+
+#endif // __HW_RFVBAT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h
new file mode 100644
index 0000000000..5f2ecaed23
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h
@@ -0,0 +1,590 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RNG_REGISTERS_H__
+#define __HW_RNG_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - HW_RNG_CR - RNGA Control Register
+ * - HW_RNG_SR - RNGA Status Register
+ * - HW_RNG_ER - RNGA Entropy Register
+ * - HW_RNG_OR - RNGA Output Register
+ *
+ * - hw_rng_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RNG_BASE
+#define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module.
+#define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_CR - RNGA Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+typedef union _hw_rng_cr
+{
+    uint32_t U;
+    struct _hw_rng_cr_bitfields
+    {
+        uint32_t GO : 1;               //!< [0] Go
+        uint32_t HA : 1;               //!< [1] High Assurance
+        uint32_t INTM : 1;             //!< [2] Interrupt Mask
+        uint32_t CLRI : 1;             //!< [3] Clear Interrupt
+        uint32_t SLP : 1;              //!< [4] Sleep
+        uint32_t RESERVED0 : 27;       //!< [31:5]
+    } B;
+} hw_rng_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+//@{
+#define HW_RNG_CR_ADDR           (REGS_RNG_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_CR                (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR)
+#define HW_RNG_CR_RD()           (HW_RNG_CR.U)
+#define HW_RNG_CR_WR(v)          (HW_RNG_CR.U = (v))
+#define HW_RNG_CR_SET(v)         (HW_RNG_CR_WR(HW_RNG_CR_RD() |  (v)))
+#define HW_RNG_CR_CLR(v)         (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v)))
+#define HW_RNG_CR_TOG(v)         (HW_RNG_CR_WR(HW_RNG_CR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_RNG_CR_GO         (0U)          //!< Bit position for RNG_CR_GO.
+#define BM_RNG_CR_GO         (0x00000001U) //!< Bit mask for RNG_CR_GO.
+#define BS_RNG_CR_GO         (1U)          //!< Bit field size in bits for RNG_CR_GO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_GO field.
+#define BR_RNG_CR_GO         (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_GO.
+#define BF_RNG_CR_GO(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GO field to a new value.
+#define BW_RNG_CR_GO(v)      (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_RNG_CR_HA         (1U)          //!< Bit position for RNG_CR_HA.
+#define BM_RNG_CR_HA         (0x00000002U) //!< Bit mask for RNG_CR_HA.
+#define BS_RNG_CR_HA         (1U)          //!< Bit field size in bits for RNG_CR_HA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_HA field.
+#define BR_RNG_CR_HA         (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_HA.
+#define BF_RNG_CR_HA(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HA field to a new value.
+#define BW_RNG_CR_HA(v)      (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0 - Not masked
+ * - 1 - Masked
+ */
+//@{
+#define BP_RNG_CR_INTM       (2U)          //!< Bit position for RNG_CR_INTM.
+#define BM_RNG_CR_INTM       (0x00000004U) //!< Bit mask for RNG_CR_INTM.
+#define BS_RNG_CR_INTM       (1U)          //!< Bit field size in bits for RNG_CR_INTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_INTM field.
+#define BR_RNG_CR_INTM       (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_INTM.
+#define BF_RNG_CR_INTM(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTM field to a new value.
+#define BW_RNG_CR_INTM(v)    (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0 - Do not clear the interrupt.
+ * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+//@{
+#define BP_RNG_CR_CLRI       (3U)          //!< Bit position for RNG_CR_CLRI.
+#define BM_RNG_CR_CLRI       (0x00000008U) //!< Bit mask for RNG_CR_CLRI.
+#define BS_RNG_CR_CLRI       (1U)          //!< Bit field size in bits for RNG_CR_CLRI.
+
+//! @brief Format value for bitfield RNG_CR_CLRI.
+#define BF_RNG_CR_CLRI(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLRI field to a new value.
+#define BW_RNG_CR_CLRI(v)    (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0 - Normal mode
+ * - 1 - Sleep (low-power) mode
+ */
+//@{
+#define BP_RNG_CR_SLP        (4U)          //!< Bit position for RNG_CR_SLP.
+#define BM_RNG_CR_SLP        (0x00000010U) //!< Bit mask for RNG_CR_SLP.
+#define BS_RNG_CR_SLP        (1U)          //!< Bit field size in bits for RNG_CR_SLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_SLP field.
+#define BR_RNG_CR_SLP        (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_SLP.
+#define BF_RNG_CR_SLP(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLP field to a new value.
+#define BW_RNG_CR_SLP(v)     (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_SR - RNGA Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+typedef union _hw_rng_sr
+{
+    uint32_t U;
+    struct _hw_rng_sr_bitfields
+    {
+        uint32_t SECV : 1;             //!< [0] Security Violation
+        uint32_t LRS : 1;              //!< [1] Last Read Status
+        uint32_t ORU : 1;              //!< [2] Output Register Underflow
+        uint32_t ERRI : 1;             //!< [3] Error Interrupt
+        uint32_t SLP : 1;              //!< [4] Sleep
+        uint32_t RESERVED0 : 3;        //!< [7:5]
+        uint32_t OREG_LVL : 8;         //!< [15:8] Output Register Level
+        uint32_t OREG_SIZE : 8;        //!< [23:16] Output Register Size
+        uint32_t RESERVED1 : 8;        //!< [31:24]
+    } B;
+} hw_rng_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+//@{
+#define HW_RNG_SR_ADDR           (REGS_RNG_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_SR                (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR)
+#define HW_RNG_SR_RD()           (HW_RNG_SR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0 - No security violation
+ * - 1 - Security violation
+ */
+//@{
+#define BP_RNG_SR_SECV       (0U)          //!< Bit position for RNG_SR_SECV.
+#define BM_RNG_SR_SECV       (0x00000001U) //!< Bit mask for RNG_SR_SECV.
+#define BS_RNG_SR_SECV       (1U)          //!< Bit field size in bits for RNG_SR_SECV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_SECV field.
+#define BR_RNG_SR_SECV       (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0 - No underflow
+ * - 1 - Underflow
+ */
+//@{
+#define BP_RNG_SR_LRS        (1U)          //!< Bit position for RNG_SR_LRS.
+#define BM_RNG_SR_LRS        (0x00000002U) //!< Bit mask for RNG_SR_LRS.
+#define BS_RNG_SR_LRS        (1U)          //!< Bit field size in bits for RNG_SR_LRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_LRS field.
+#define BR_RNG_SR_LRS        (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0 - No underflow
+ * - 1 - Underflow
+ */
+//@{
+#define BP_RNG_SR_ORU        (2U)          //!< Bit position for RNG_SR_ORU.
+#define BM_RNG_SR_ORU        (0x00000004U) //!< Bit mask for RNG_SR_ORU.
+#define BS_RNG_SR_ORU        (1U)          //!< Bit field size in bits for RNG_SR_ORU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_ORU field.
+#define BR_RNG_SR_ORU        (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0 - No underflow
+ * - 1 - Underflow
+ */
+//@{
+#define BP_RNG_SR_ERRI       (3U)          //!< Bit position for RNG_SR_ERRI.
+#define BM_RNG_SR_ERRI       (0x00000008U) //!< Bit mask for RNG_SR_ERRI.
+#define BS_RNG_SR_ERRI       (1U)          //!< Bit field size in bits for RNG_SR_ERRI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_ERRI field.
+#define BR_RNG_SR_ERRI       (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0 - Normal mode
+ * - 1 - Sleep (low-power) mode
+ */
+//@{
+#define BP_RNG_SR_SLP        (4U)          //!< Bit position for RNG_SR_SLP.
+#define BM_RNG_SR_SLP        (0x00000010U) //!< Bit mask for RNG_SR_SLP.
+#define BS_RNG_SR_SLP        (1U)          //!< Bit field size in bits for RNG_SR_SLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_SLP field.
+#define BR_RNG_SR_SLP        (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0 - No words (empty)
+ * - 1 - One word (valid)
+ */
+//@{
+#define BP_RNG_SR_OREG_LVL   (8U)          //!< Bit position for RNG_SR_OREG_LVL.
+#define BM_RNG_SR_OREG_LVL   (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL.
+#define BS_RNG_SR_OREG_LVL   (8U)          //!< Bit field size in bits for RNG_SR_OREG_LVL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_OREG_LVL field.
+#define BR_RNG_SR_OREG_LVL   (HW_RNG_SR.B.OREG_LVL)
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 1 - One word (this value is fixed)
+ */
+//@{
+#define BP_RNG_SR_OREG_SIZE  (16U)         //!< Bit position for RNG_SR_OREG_SIZE.
+#define BM_RNG_SR_OREG_SIZE  (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE.
+#define BS_RNG_SR_OREG_SIZE  (8U)          //!< Bit field size in bits for RNG_SR_OREG_SIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_OREG_SIZE field.
+#define BR_RNG_SR_OREG_SIZE  (HW_RNG_SR.B.OREG_SIZE)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_ER - RNGA Entropy Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+typedef union _hw_rng_er
+{
+    uint32_t U;
+    struct _hw_rng_er_bitfields
+    {
+        uint32_t EXT_ENT : 32;         //!< [31:0] External Entropy
+    } B;
+} hw_rng_er_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+//@{
+#define HW_RNG_ER_ADDR           (REGS_RNG_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_ER                (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR)
+#define HW_RNG_ER_RD()           (HW_RNG_ER.U)
+#define HW_RNG_ER_WR(v)          (HW_RNG_ER.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_ER bitfields
+ */
+
+/*!
+ * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm.Specifying a value for this field is
+ * optional but recommended. You can write to this field at any time during operation.
+ */
+//@{
+#define BP_RNG_ER_EXT_ENT    (0U)          //!< Bit position for RNG_ER_EXT_ENT.
+#define BM_RNG_ER_EXT_ENT    (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT.
+#define BS_RNG_ER_EXT_ENT    (32U)         //!< Bit field size in bits for RNG_ER_EXT_ENT.
+
+//! @brief Format value for bitfield RNG_ER_EXT_ENT.
+#define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXT_ENT field to a new value.
+#define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_OR - RNGA Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+typedef union _hw_rng_or
+{
+    uint32_t U;
+    struct _hw_rng_or_bitfields
+    {
+        uint32_t RANDOUT : 32;         //!< [31:0] Random Output
+    } B;
+} hw_rng_or_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+//@{
+#define HW_RNG_OR_ADDR           (REGS_RNG_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_OR                (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR)
+#define HW_RNG_OR_RD()           (HW_RNG_OR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_OR bitfields
+ */
+
+/*!
+ * @name Register RNG_OR, field RANDOUT[31:0] (RO)
+ *
+ * Stores a random-data word generated by RNGA. This is a read-only field.Before
+ * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
+ *
+ * Values:
+ * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
+ *     0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
+ *     interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
+ *     request to the interrupt controller).
+ */
+//@{
+#define BP_RNG_OR_RANDOUT    (0U)          //!< Bit position for RNG_OR_RANDOUT.
+#define BM_RNG_OR_RANDOUT    (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT.
+#define BS_RNG_OR_RANDOUT    (32U)         //!< Bit field size in bits for RNG_OR_RANDOUT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_OR_RANDOUT field.
+#define BR_RNG_OR_RANDOUT    (HW_RNG_OR.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rng_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RNG module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rng
+{
+    __IO hw_rng_cr_t CR;                   //!< [0x0] RNGA Control Register
+    __I hw_rng_sr_t SR;                    //!< [0x4] RNGA Status Register
+    __O hw_rng_er_t ER;                    //!< [0x8] RNGA Entropy Register
+    __I hw_rng_or_t OR;                    //!< [0xC] RNGA Output Register
+} hw_rng_t;
+#pragma pack()
+
+//! @brief Macro to access all RNG registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_RNG</code>.
+#define HW_RNG         (*(hw_rng_t *) REGS_RNG_BASE)
+#endif
+
+#endif // __HW_RNG_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h
new file mode 100644
index 0000000000..0a1c263332
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h
@@ -0,0 +1,1828 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RTC_REGISTERS_H__
+#define __HW_RTC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - HW_RTC_TSR - RTC Time Seconds Register
+ * - HW_RTC_TPR - RTC Time Prescaler Register
+ * - HW_RTC_TAR - RTC Time Alarm Register
+ * - HW_RTC_TCR - RTC Time Compensation Register
+ * - HW_RTC_CR - RTC Control Register
+ * - HW_RTC_SR - RTC Status Register
+ * - HW_RTC_LR - RTC Lock Register
+ * - HW_RTC_IER - RTC Interrupt Enable Register
+ * - HW_RTC_WAR - RTC Write Access Register
+ * - HW_RTC_RAR - RTC Read Access Register
+ *
+ * - hw_rtc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RTC_BASE
+#define HW_RTC_INSTANCE_COUNT (1U) //!< Number of instances of the RTC module.
+#define REGS_RTC_BASE (0x4003D000U) //!< Base address for RTC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TSR - RTC Time Seconds Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tsr
+{
+    uint32_t U;
+    struct _hw_rtc_tsr_bitfields
+    {
+        uint32_t TSR : 32;             //!< [31:0] Time Seconds Register
+    } B;
+} hw_rtc_tsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+//@{
+#define HW_RTC_TSR_ADDR          (REGS_RTC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TSR               (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR)
+#define HW_RTC_TSR_RD()          (HW_RTC_TSR.U)
+#define HW_RTC_TSR_WR(v)         (HW_RTC_TSR.U = (v))
+#define HW_RTC_TSR_SET(v)        (HW_RTC_TSR_WR(HW_RTC_TSR_RD() |  (v)))
+#define HW_RTC_TSR_CLR(v)        (HW_RTC_TSR_WR(HW_RTC_TSR_RD() & ~(v)))
+#define HW_RTC_TSR_TOG(v)        (HW_RTC_TSR_WR(HW_RTC_TSR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TSR bitfields
+ */
+
+/*!
+ * @name Register RTC_TSR, field TSR[31:0] (RW)
+ *
+ * When the time counter is enabled, the TSR is read only and increments once a
+ * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
+ * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
+ * TSR can be read or written. Writing to the TSR when the time counter is
+ * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
+ * supported, but not recommended because TSR will read as zero when SR[TIF] or
+ * SR[TOF] are set (indicating the time is invalid).
+ */
+//@{
+#define BP_RTC_TSR_TSR       (0U)          //!< Bit position for RTC_TSR_TSR.
+#define BM_RTC_TSR_TSR       (0xFFFFFFFFU) //!< Bit mask for RTC_TSR_TSR.
+#define BS_RTC_TSR_TSR       (32U)         //!< Bit field size in bits for RTC_TSR_TSR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TSR_TSR field.
+#define BR_RTC_TSR_TSR       (HW_RTC_TSR.U)
+#endif
+
+//! @brief Format value for bitfield RTC_TSR_TSR.
+#define BF_RTC_TSR_TSR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TSR_TSR), uint32_t) & BM_RTC_TSR_TSR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSR field to a new value.
+#define BW_RTC_TSR_TSR(v)    (HW_RTC_TSR_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TPR - RTC Time Prescaler Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tpr
+{
+    uint32_t U;
+    struct _hw_rtc_tpr_bitfields
+    {
+        uint32_t TPR : 16;             //!< [15:0] Time Prescaler Register
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_rtc_tpr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+//@{
+#define HW_RTC_TPR_ADDR          (REGS_RTC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TPR               (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR)
+#define HW_RTC_TPR_RD()          (HW_RTC_TPR.U)
+#define HW_RTC_TPR_WR(v)         (HW_RTC_TPR.U = (v))
+#define HW_RTC_TPR_SET(v)        (HW_RTC_TPR_WR(HW_RTC_TPR_RD() |  (v)))
+#define HW_RTC_TPR_CLR(v)        (HW_RTC_TPR_WR(HW_RTC_TPR_RD() & ~(v)))
+#define HW_RTC_TPR_TOG(v)        (HW_RTC_TPR_WR(HW_RTC_TPR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+//@{
+#define BP_RTC_TPR_TPR       (0U)          //!< Bit position for RTC_TPR_TPR.
+#define BM_RTC_TPR_TPR       (0x0000FFFFU) //!< Bit mask for RTC_TPR_TPR.
+#define BS_RTC_TPR_TPR       (16U)         //!< Bit field size in bits for RTC_TPR_TPR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TPR_TPR field.
+#define BR_RTC_TPR_TPR       (HW_RTC_TPR.B.TPR)
+#endif
+
+//! @brief Format value for bitfield RTC_TPR_TPR.
+#define BF_RTC_TPR_TPR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TPR_TPR), uint32_t) & BM_RTC_TPR_TPR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPR field to a new value.
+#define BW_RTC_TPR_TPR(v)    (HW_RTC_TPR_WR((HW_RTC_TPR_RD() & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TAR - RTC Time Alarm Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tar
+{
+    uint32_t U;
+    struct _hw_rtc_tar_bitfields
+    {
+        uint32_t TAR : 32;             //!< [31:0] Time Alarm Register
+    } B;
+} hw_rtc_tar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+//@{
+#define HW_RTC_TAR_ADDR          (REGS_RTC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TAR               (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR)
+#define HW_RTC_TAR_RD()          (HW_RTC_TAR.U)
+#define HW_RTC_TAR_WR(v)         (HW_RTC_TAR.U = (v))
+#define HW_RTC_TAR_SET(v)        (HW_RTC_TAR_WR(HW_RTC_TAR_RD() |  (v)))
+#define HW_RTC_TAR_CLR(v)        (HW_RTC_TAR_WR(HW_RTC_TAR_RD() & ~(v)))
+#define HW_RTC_TAR_TOG(v)        (HW_RTC_TAR_WR(HW_RTC_TAR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TAR bitfields
+ */
+
+/*!
+ * @name Register RTC_TAR, field TAR[31:0] (RW)
+ *
+ * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
+ * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
+ * SR[TAF].
+ */
+//@{
+#define BP_RTC_TAR_TAR       (0U)          //!< Bit position for RTC_TAR_TAR.
+#define BM_RTC_TAR_TAR       (0xFFFFFFFFU) //!< Bit mask for RTC_TAR_TAR.
+#define BS_RTC_TAR_TAR       (32U)         //!< Bit field size in bits for RTC_TAR_TAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TAR_TAR field.
+#define BR_RTC_TAR_TAR       (HW_RTC_TAR.U)
+#endif
+
+//! @brief Format value for bitfield RTC_TAR_TAR.
+#define BF_RTC_TAR_TAR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TAR_TAR), uint32_t) & BM_RTC_TAR_TAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TAR field to a new value.
+#define BW_RTC_TAR_TAR(v)    (HW_RTC_TAR_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TCR - RTC Time Compensation Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tcr
+{
+    uint32_t U;
+    struct _hw_rtc_tcr_bitfields
+    {
+        uint32_t TCR : 8;              //!< [7:0] Time Compensation Register
+        uint32_t CIR : 8;              //!< [15:8] Compensation Interval Register
+        uint32_t TCV : 8;              //!< [23:16] Time Compensation Value
+        uint32_t CIC : 8;              //!< [31:24] Compensation Interval Counter
+    } B;
+} hw_rtc_tcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+//@{
+#define HW_RTC_TCR_ADDR          (REGS_RTC_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TCR               (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR)
+#define HW_RTC_TCR_RD()          (HW_RTC_TCR.U)
+#define HW_RTC_TCR_WR(v)         (HW_RTC_TCR.U = (v))
+#define HW_RTC_TCR_SET(v)        (HW_RTC_TCR_WR(HW_RTC_TCR_RD() |  (v)))
+#define HW_RTC_TCR_CLR(v)        (HW_RTC_TCR_WR(HW_RTC_TCR_RD() & ~(v)))
+#define HW_RTC_TCR_TOG(v)        (HW_RTC_TCR_WR(HW_RTC_TCR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 1 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+//@{
+#define BP_RTC_TCR_TCR       (0U)          //!< Bit position for RTC_TCR_TCR.
+#define BM_RTC_TCR_TCR       (0x000000FFU) //!< Bit mask for RTC_TCR_TCR.
+#define BS_RTC_TCR_TCR       (8U)          //!< Bit field size in bits for RTC_TCR_TCR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_TCR field.
+#define BR_RTC_TCR_TCR       (HW_RTC_TCR.B.TCR)
+#endif
+
+//! @brief Format value for bitfield RTC_TCR_TCR.
+#define BF_RTC_TCR_TCR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_TCR), uint32_t) & BM_RTC_TCR_TCR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCR field to a new value.
+#define BW_RTC_TCR_TCR(v)    (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+//@{
+#define BP_RTC_TCR_CIR       (8U)          //!< Bit position for RTC_TCR_CIR.
+#define BM_RTC_TCR_CIR       (0x0000FF00U) //!< Bit mask for RTC_TCR_CIR.
+#define BS_RTC_TCR_CIR       (8U)          //!< Bit field size in bits for RTC_TCR_CIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_CIR field.
+#define BR_RTC_TCR_CIR       (HW_RTC_TCR.B.CIR)
+#endif
+
+//! @brief Format value for bitfield RTC_TCR_CIR.
+#define BF_RTC_TCR_CIR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_CIR), uint32_t) & BM_RTC_TCR_CIR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIR field to a new value.
+#define BW_RTC_TCR_CIR(v)    (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+//@{
+#define BP_RTC_TCR_TCV       (16U)         //!< Bit position for RTC_TCR_TCV.
+#define BM_RTC_TCR_TCV       (0x00FF0000U) //!< Bit mask for RTC_TCR_TCV.
+#define BS_RTC_TCR_TCV       (8U)          //!< Bit field size in bits for RTC_TCR_TCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_TCV field.
+#define BR_RTC_TCR_TCV       (HW_RTC_TCR.B.TCV)
+#endif
+//@}
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+//@{
+#define BP_RTC_TCR_CIC       (24U)         //!< Bit position for RTC_TCR_CIC.
+#define BM_RTC_TCR_CIC       (0xFF000000U) //!< Bit mask for RTC_TCR_CIC.
+#define BS_RTC_TCR_CIC       (8U)          //!< Bit field size in bits for RTC_TCR_CIC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_CIC field.
+#define BR_RTC_TCR_CIC       (HW_RTC_TCR.B.CIC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_CR - RTC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_cr
+{
+    uint32_t U;
+    struct _hw_rtc_cr_bitfields
+    {
+        uint32_t SWR : 1;              //!< [0] Software Reset
+        uint32_t WPE : 1;              //!< [1] Wakeup Pin Enable
+        uint32_t SUP : 1;              //!< [2] Supervisor Access
+        uint32_t UM : 1;               //!< [3] Update Mode
+        uint32_t WPS : 1;              //!< [4] Wakeup Pin Select
+        uint32_t RESERVED0 : 3;        //!< [7:5]
+        uint32_t OSCE : 1;             //!< [8] Oscillator Enable
+        uint32_t CLKO : 1;             //!< [9] Clock Output
+        uint32_t SC16P : 1;            //!< [10] Oscillator 16pF Load Configure
+        uint32_t SC8P : 1;             //!< [11] Oscillator 8pF Load Configure
+        uint32_t SC4P : 1;             //!< [12] Oscillator 4pF Load Configure
+        uint32_t SC2P : 1;             //!< [13] Oscillator 2pF Load Configure
+        uint32_t RESERVED1 : 18;       //!< [31:14]
+    } B;
+} hw_rtc_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+//@{
+#define HW_RTC_CR_ADDR           (REGS_RTC_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_CR                (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR)
+#define HW_RTC_CR_RD()           (HW_RTC_CR.U)
+#define HW_RTC_CR_WR(v)          (HW_RTC_CR.U = (v))
+#define HW_RTC_CR_SET(v)         (HW_RTC_CR_WR(HW_RTC_CR_RD() |  (v)))
+#define HW_RTC_CR_CLR(v)         (HW_RTC_CR_WR(HW_RTC_CR_RD() & ~(v)))
+#define HW_RTC_CR_TOG(v)         (HW_RTC_CR_WR(HW_RTC_CR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+//@{
+#define BP_RTC_CR_SWR        (0U)          //!< Bit position for RTC_CR_SWR.
+#define BM_RTC_CR_SWR        (0x00000001U) //!< Bit mask for RTC_CR_SWR.
+#define BS_RTC_CR_SWR        (1U)          //!< Bit field size in bits for RTC_CR_SWR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SWR field.
+#define BR_RTC_CR_SWR        (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SWR.
+#define BF_RTC_CR_SWR(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SWR), uint32_t) & BM_RTC_CR_SWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWR field to a new value.
+#define BW_RTC_CR_SWR(v)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0 - Wakeup pin is disabled.
+ * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+//@{
+#define BP_RTC_CR_WPE        (1U)          //!< Bit position for RTC_CR_WPE.
+#define BM_RTC_CR_WPE        (0x00000002U) //!< Bit mask for RTC_CR_WPE.
+#define BS_RTC_CR_WPE        (1U)          //!< Bit field size in bits for RTC_CR_WPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_WPE field.
+#define BR_RTC_CR_WPE        (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_WPE.
+#define BF_RTC_CR_WPE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPE), uint32_t) & BM_RTC_CR_WPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPE field to a new value.
+#define BW_RTC_CR_WPE(v)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0 - Non-supervisor mode write accesses are not supported and generate a bus
+ *     error.
+ * - 1 - Non-supervisor mode write accesses are supported.
+ */
+//@{
+#define BP_RTC_CR_SUP        (2U)          //!< Bit position for RTC_CR_SUP.
+#define BM_RTC_CR_SUP        (0x00000004U) //!< Bit mask for RTC_CR_SUP.
+#define BS_RTC_CR_SUP        (1U)          //!< Bit field size in bits for RTC_CR_SUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SUP field.
+#define BR_RTC_CR_SUP        (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SUP.
+#define BF_RTC_CR_SUP(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SUP), uint32_t) & BM_RTC_CR_SUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SUP field to a new value.
+#define BW_RTC_CR_SUP(v)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0 - Registers cannot be written when locked.
+ * - 1 - Registers can be written when locked under limited conditions.
+ */
+//@{
+#define BP_RTC_CR_UM         (3U)          //!< Bit position for RTC_CR_UM.
+#define BM_RTC_CR_UM         (0x00000008U) //!< Bit mask for RTC_CR_UM.
+#define BS_RTC_CR_UM         (1U)          //!< Bit field size in bits for RTC_CR_UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_UM field.
+#define BR_RTC_CR_UM         (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_UM.
+#define BF_RTC_CR_UM(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_UM), uint32_t) & BM_RTC_CR_UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UM field to a new value.
+#define BW_RTC_CR_UM(v)      (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
+ *     is turned on and the 32kHz clock is output to other peripherals.
+ */
+//@{
+#define BP_RTC_CR_WPS        (4U)          //!< Bit position for RTC_CR_WPS.
+#define BM_RTC_CR_WPS        (0x00000010U) //!< Bit mask for RTC_CR_WPS.
+#define BS_RTC_CR_WPS        (1U)          //!< Bit field size in bits for RTC_CR_WPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_WPS field.
+#define BR_RTC_CR_WPS        (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_WPS.
+#define BF_RTC_CR_WPS(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPS), uint32_t) & BM_RTC_CR_WPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPS field to a new value.
+#define BW_RTC_CR_WPS(v)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0 - 32.768 kHz oscillator is disabled.
+ * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+//@{
+#define BP_RTC_CR_OSCE       (8U)          //!< Bit position for RTC_CR_OSCE.
+#define BM_RTC_CR_OSCE       (0x00000100U) //!< Bit mask for RTC_CR_OSCE.
+#define BS_RTC_CR_OSCE       (1U)          //!< Bit field size in bits for RTC_CR_OSCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_OSCE field.
+#define BR_RTC_CR_OSCE       (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_OSCE.
+#define BF_RTC_CR_OSCE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_OSCE), uint32_t) & BM_RTC_CR_OSCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OSCE field to a new value.
+#define BW_RTC_CR_OSCE(v)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0 - The 32 kHz clock is output to other peripherals.
+ * - 1 - The 32 kHz clock is not output to other peripherals.
+ */
+//@{
+#define BP_RTC_CR_CLKO       (9U)          //!< Bit position for RTC_CR_CLKO.
+#define BM_RTC_CR_CLKO       (0x00000200U) //!< Bit mask for RTC_CR_CLKO.
+#define BS_RTC_CR_CLKO       (1U)          //!< Bit field size in bits for RTC_CR_CLKO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_CLKO field.
+#define BR_RTC_CR_CLKO       (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_CLKO.
+#define BF_RTC_CR_CLKO(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_CLKO), uint32_t) & BM_RTC_CR_CLKO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKO field to a new value.
+#define BW_RTC_CR_CLKO(v)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC16P      (10U)         //!< Bit position for RTC_CR_SC16P.
+#define BM_RTC_CR_SC16P      (0x00000400U) //!< Bit mask for RTC_CR_SC16P.
+#define BS_RTC_CR_SC16P      (1U)          //!< Bit field size in bits for RTC_CR_SC16P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC16P field.
+#define BR_RTC_CR_SC16P      (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC16P.
+#define BF_RTC_CR_SC16P(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC16P), uint32_t) & BM_RTC_CR_SC16P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC16P field to a new value.
+#define BW_RTC_CR_SC16P(v)   (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC8P       (11U)         //!< Bit position for RTC_CR_SC8P.
+#define BM_RTC_CR_SC8P       (0x00000800U) //!< Bit mask for RTC_CR_SC8P.
+#define BS_RTC_CR_SC8P       (1U)          //!< Bit field size in bits for RTC_CR_SC8P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC8P field.
+#define BR_RTC_CR_SC8P       (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC8P.
+#define BF_RTC_CR_SC8P(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC8P), uint32_t) & BM_RTC_CR_SC8P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC8P field to a new value.
+#define BW_RTC_CR_SC8P(v)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC4P       (12U)         //!< Bit position for RTC_CR_SC4P.
+#define BM_RTC_CR_SC4P       (0x00001000U) //!< Bit mask for RTC_CR_SC4P.
+#define BS_RTC_CR_SC4P       (1U)          //!< Bit field size in bits for RTC_CR_SC4P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC4P field.
+#define BR_RTC_CR_SC4P       (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC4P.
+#define BF_RTC_CR_SC4P(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC4P), uint32_t) & BM_RTC_CR_SC4P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC4P field to a new value.
+#define BW_RTC_CR_SC4P(v)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC2P       (13U)         //!< Bit position for RTC_CR_SC2P.
+#define BM_RTC_CR_SC2P       (0x00002000U) //!< Bit mask for RTC_CR_SC2P.
+#define BS_RTC_CR_SC2P       (1U)          //!< Bit field size in bits for RTC_CR_SC2P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC2P field.
+#define BR_RTC_CR_SC2P       (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC2P.
+#define BF_RTC_CR_SC2P(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC2P), uint32_t) & BM_RTC_CR_SC2P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC2P field to a new value.
+#define BW_RTC_CR_SC2P(v)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_SR - RTC Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+typedef union _hw_rtc_sr
+{
+    uint32_t U;
+    struct _hw_rtc_sr_bitfields
+    {
+        uint32_t TIF : 1;              //!< [0] Time Invalid Flag
+        uint32_t TOF : 1;              //!< [1] Time Overflow Flag
+        uint32_t TAF : 1;              //!< [2] Time Alarm Flag
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TCE : 1;              //!< [4] Time Counter Enable
+        uint32_t RESERVED1 : 27;       //!< [31:5]
+    } B;
+} hw_rtc_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+//@{
+#define HW_RTC_SR_ADDR           (REGS_RTC_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_SR                (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR)
+#define HW_RTC_SR_RD()           (HW_RTC_SR.U)
+#define HW_RTC_SR_WR(v)          (HW_RTC_SR.U = (v))
+#define HW_RTC_SR_SET(v)         (HW_RTC_SR_WR(HW_RTC_SR_RD() |  (v)))
+#define HW_RTC_SR_CLR(v)         (HW_RTC_SR_WR(HW_RTC_SR_RD() & ~(v)))
+#define HW_RTC_SR_TOG(v)         (HW_RTC_SR_WR(HW_RTC_SR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0 - Time is valid.
+ * - 1 - Time is invalid and time counter is read as zero.
+ */
+//@{
+#define BP_RTC_SR_TIF        (0U)          //!< Bit position for RTC_SR_TIF.
+#define BM_RTC_SR_TIF        (0x00000001U) //!< Bit mask for RTC_SR_TIF.
+#define BS_RTC_SR_TIF        (1U)          //!< Bit field size in bits for RTC_SR_TIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TIF field.
+#define BR_RTC_SR_TIF        (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TIF))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0 - Time overflow has not occurred.
+ * - 1 - Time overflow has occurred and time counter is read as zero.
+ */
+//@{
+#define BP_RTC_SR_TOF        (1U)          //!< Bit position for RTC_SR_TOF.
+#define BM_RTC_SR_TOF        (0x00000002U) //!< Bit mask for RTC_SR_TOF.
+#define BS_RTC_SR_TOF        (1U)          //!< Bit field size in bits for RTC_SR_TOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TOF field.
+#define BR_RTC_SR_TOF        (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TOF))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0 - Time alarm has not occurred.
+ * - 1 - Time alarm has occurred.
+ */
+//@{
+#define BP_RTC_SR_TAF        (2U)          //!< Bit position for RTC_SR_TAF.
+#define BM_RTC_SR_TAF        (0x00000004U) //!< Bit mask for RTC_SR_TAF.
+#define BS_RTC_SR_TAF        (1U)          //!< Bit field size in bits for RTC_SR_TAF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TAF field.
+#define BR_RTC_SR_TAF        (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TAF))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0 - Time counter is disabled.
+ * - 1 - Time counter is enabled.
+ */
+//@{
+#define BP_RTC_SR_TCE        (4U)          //!< Bit position for RTC_SR_TCE.
+#define BM_RTC_SR_TCE        (0x00000010U) //!< Bit mask for RTC_SR_TCE.
+#define BS_RTC_SR_TCE        (1U)          //!< Bit field size in bits for RTC_SR_TCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TCE field.
+#define BR_RTC_SR_TCE        (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE))
+#endif
+
+//! @brief Format value for bitfield RTC_SR_TCE.
+#define BF_RTC_SR_TCE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_SR_TCE), uint32_t) & BM_RTC_SR_TCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCE field to a new value.
+#define BW_RTC_SR_TCE(v)     (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_LR - RTC Lock Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+typedef union _hw_rtc_lr
+{
+    uint32_t U;
+    struct _hw_rtc_lr_bitfields
+    {
+        uint32_t RESERVED0 : 3;        //!< [2:0]
+        uint32_t TCL : 1;              //!< [3] Time Compensation Lock
+        uint32_t CRL : 1;              //!< [4] Control Register Lock
+        uint32_t SRL : 1;              //!< [5] Status Register Lock
+        uint32_t LRL : 1;              //!< [6] Lock Register Lock
+        uint32_t RESERVED1 : 25;       //!< [31:7]
+    } B;
+} hw_rtc_lr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+//@{
+#define HW_RTC_LR_ADDR           (REGS_RTC_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_LR                (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR)
+#define HW_RTC_LR_RD()           (HW_RTC_LR.U)
+#define HW_RTC_LR_WR(v)          (HW_RTC_LR.U = (v))
+#define HW_RTC_LR_SET(v)         (HW_RTC_LR_WR(HW_RTC_LR_RD() |  (v)))
+#define HW_RTC_LR_CLR(v)         (HW_RTC_LR_WR(HW_RTC_LR_RD() & ~(v)))
+#define HW_RTC_LR_TOG(v)         (HW_RTC_LR_WR(HW_RTC_LR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Time Compensation Register is locked and writes are ignored.
+ * - 1 - Time Compensation Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_TCL        (3U)          //!< Bit position for RTC_LR_TCL.
+#define BM_RTC_LR_TCL        (0x00000008U) //!< Bit mask for RTC_LR_TCL.
+#define BS_RTC_LR_TCL        (1U)          //!< Bit field size in bits for RTC_LR_TCL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_TCL field.
+#define BR_RTC_LR_TCL        (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_TCL.
+#define BF_RTC_LR_TCL(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_TCL), uint32_t) & BM_RTC_LR_TCL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCL field to a new value.
+#define BW_RTC_LR_TCL(v)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0 - Control Register is locked and writes are ignored.
+ * - 1 - Control Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_CRL        (4U)          //!< Bit position for RTC_LR_CRL.
+#define BM_RTC_LR_CRL        (0x00000010U) //!< Bit mask for RTC_LR_CRL.
+#define BS_RTC_LR_CRL        (1U)          //!< Bit field size in bits for RTC_LR_CRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_CRL field.
+#define BR_RTC_LR_CRL        (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_CRL.
+#define BF_RTC_LR_CRL(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_CRL), uint32_t) & BM_RTC_LR_CRL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRL field to a new value.
+#define BW_RTC_LR_CRL(v)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Status Register is locked and writes are ignored.
+ * - 1 - Status Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_SRL        (5U)          //!< Bit position for RTC_LR_SRL.
+#define BM_RTC_LR_SRL        (0x00000020U) //!< Bit mask for RTC_LR_SRL.
+#define BS_RTC_LR_SRL        (1U)          //!< Bit field size in bits for RTC_LR_SRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_SRL field.
+#define BR_RTC_LR_SRL        (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_SRL.
+#define BF_RTC_LR_SRL(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_SRL), uint32_t) & BM_RTC_LR_SRL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRL field to a new value.
+#define BW_RTC_LR_SRL(v)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Lock Register is locked and writes are ignored.
+ * - 1 - Lock Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_LRL        (6U)          //!< Bit position for RTC_LR_LRL.
+#define BM_RTC_LR_LRL        (0x00000040U) //!< Bit mask for RTC_LR_LRL.
+#define BS_RTC_LR_LRL        (1U)          //!< Bit field size in bits for RTC_LR_LRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_LRL field.
+#define BR_RTC_LR_LRL        (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_LRL.
+#define BF_RTC_LR_LRL(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_LRL), uint32_t) & BM_RTC_LR_LRL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LRL field to a new value.
+#define BW_RTC_LR_LRL(v)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_IER - RTC Interrupt Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+typedef union _hw_rtc_ier
+{
+    uint32_t U;
+    struct _hw_rtc_ier_bitfields
+    {
+        uint32_t TIIE : 1;             //!< [0] Time Invalid Interrupt Enable
+        uint32_t TOIE : 1;             //!< [1] Time Overflow Interrupt Enable
+        uint32_t TAIE : 1;             //!< [2] Time Alarm Interrupt Enable
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t TSIE : 1;             //!< [4] Time Seconds Interrupt Enable
+        uint32_t RESERVED1 : 2;        //!< [6:5]
+        uint32_t WPON : 1;             //!< [7] Wakeup Pin On
+        uint32_t RESERVED2 : 24;       //!< [31:8]
+    } B;
+} hw_rtc_ier_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+//@{
+#define HW_RTC_IER_ADDR          (REGS_RTC_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_IER               (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR)
+#define HW_RTC_IER_RD()          (HW_RTC_IER.U)
+#define HW_RTC_IER_WR(v)         (HW_RTC_IER.U = (v))
+#define HW_RTC_IER_SET(v)        (HW_RTC_IER_WR(HW_RTC_IER_RD() |  (v)))
+#define HW_RTC_IER_CLR(v)        (HW_RTC_IER_WR(HW_RTC_IER_RD() & ~(v)))
+#define HW_RTC_IER_TOG(v)        (HW_RTC_IER_WR(HW_RTC_IER_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0 - Time invalid flag does not generate an interrupt.
+ * - 1 - Time invalid flag does generate an interrupt.
+ */
+//@{
+#define BP_RTC_IER_TIIE      (0U)          //!< Bit position for RTC_IER_TIIE.
+#define BM_RTC_IER_TIIE      (0x00000001U) //!< Bit mask for RTC_IER_TIIE.
+#define BS_RTC_IER_TIIE      (1U)          //!< Bit field size in bits for RTC_IER_TIIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TIIE field.
+#define BR_RTC_IER_TIIE      (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TIIE.
+#define BF_RTC_IER_TIIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TIIE), uint32_t) & BM_RTC_IER_TIIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIIE field to a new value.
+#define BW_RTC_IER_TIIE(v)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0 - Time overflow flag does not generate an interrupt.
+ * - 1 - Time overflow flag does generate an interrupt.
+ */
+//@{
+#define BP_RTC_IER_TOIE      (1U)          //!< Bit position for RTC_IER_TOIE.
+#define BM_RTC_IER_TOIE      (0x00000002U) //!< Bit mask for RTC_IER_TOIE.
+#define BS_RTC_IER_TOIE      (1U)          //!< Bit field size in bits for RTC_IER_TOIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TOIE field.
+#define BR_RTC_IER_TOIE      (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TOIE.
+#define BF_RTC_IER_TOIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TOIE), uint32_t) & BM_RTC_IER_TOIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOIE field to a new value.
+#define BW_RTC_IER_TOIE(v)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0 - Time alarm flag does not generate an interrupt.
+ * - 1 - Time alarm flag does generate an interrupt.
+ */
+//@{
+#define BP_RTC_IER_TAIE      (2U)          //!< Bit position for RTC_IER_TAIE.
+#define BM_RTC_IER_TAIE      (0x00000004U) //!< Bit mask for RTC_IER_TAIE.
+#define BS_RTC_IER_TAIE      (1U)          //!< Bit field size in bits for RTC_IER_TAIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TAIE field.
+#define BR_RTC_IER_TAIE      (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TAIE.
+#define BF_RTC_IER_TAIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TAIE), uint32_t) & BM_RTC_IER_TAIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TAIE field to a new value.
+#define BW_RTC_IER_TAIE(v)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0 - Seconds interrupt is disabled.
+ * - 1 - Seconds interrupt is enabled.
+ */
+//@{
+#define BP_RTC_IER_TSIE      (4U)          //!< Bit position for RTC_IER_TSIE.
+#define BM_RTC_IER_TSIE      (0x00000010U) //!< Bit mask for RTC_IER_TSIE.
+#define BS_RTC_IER_TSIE      (1U)          //!< Bit field size in bits for RTC_IER_TSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TSIE field.
+#define BR_RTC_IER_TSIE      (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TSIE.
+#define BF_RTC_IER_TSIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TSIE), uint32_t) & BM_RTC_IER_TSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSIE field to a new value.
+#define BW_RTC_IER_TSIE(v)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+//@{
+#define BP_RTC_IER_WPON      (7U)          //!< Bit position for RTC_IER_WPON.
+#define BM_RTC_IER_WPON      (0x00000080U) //!< Bit mask for RTC_IER_WPON.
+#define BS_RTC_IER_WPON      (1U)          //!< Bit field size in bits for RTC_IER_WPON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_WPON field.
+#define BR_RTC_IER_WPON      (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_WPON.
+#define BF_RTC_IER_WPON(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_WPON), uint32_t) & BM_RTC_IER_WPON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPON field to a new value.
+#define BW_RTC_IER_WPON(v)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_WAR - RTC Write Access Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+typedef union _hw_rtc_war
+{
+    uint32_t U;
+    struct _hw_rtc_war_bitfields
+    {
+        uint32_t TSRW : 1;             //!< [0] Time Seconds Register Write
+        uint32_t TPRW : 1;             //!< [1] Time Prescaler Register Write
+        uint32_t TARW : 1;             //!< [2] Time Alarm Register Write
+        uint32_t TCRW : 1;             //!< [3] Time Compensation Register Write
+        uint32_t CRW : 1;              //!< [4] Control Register Write
+        uint32_t SRW : 1;              //!< [5] Status Register Write
+        uint32_t LRW : 1;              //!< [6] Lock Register Write
+        uint32_t IERW : 1;             //!< [7] Interrupt Enable Register Write
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_rtc_war_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+//@{
+#define HW_RTC_WAR_ADDR          (REGS_RTC_BASE + 0x800U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_WAR               (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR)
+#define HW_RTC_WAR_RD()          (HW_RTC_WAR.U)
+#define HW_RTC_WAR_WR(v)         (HW_RTC_WAR.U = (v))
+#define HW_RTC_WAR_SET(v)        (HW_RTC_WAR_WR(HW_RTC_WAR_RD() |  (v)))
+#define HW_RTC_WAR_CLR(v)        (HW_RTC_WAR_WR(HW_RTC_WAR_RD() & ~(v)))
+#define HW_RTC_WAR_TOG(v)        (HW_RTC_WAR_WR(HW_RTC_WAR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Seconds Register are ignored.
+ * - 1 - Writes to the Time Seconds Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TSRW      (0U)          //!< Bit position for RTC_WAR_TSRW.
+#define BM_RTC_WAR_TSRW      (0x00000001U) //!< Bit mask for RTC_WAR_TSRW.
+#define BS_RTC_WAR_TSRW      (1U)          //!< Bit field size in bits for RTC_WAR_TSRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TSRW field.
+#define BR_RTC_WAR_TSRW      (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TSRW.
+#define BF_RTC_WAR_TSRW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TSRW), uint32_t) & BM_RTC_WAR_TSRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSRW field to a new value.
+#define BW_RTC_WAR_TSRW(v)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Prescaler Register are ignored.
+ * - 1 - Writes to the Time Prescaler Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TPRW      (1U)          //!< Bit position for RTC_WAR_TPRW.
+#define BM_RTC_WAR_TPRW      (0x00000002U) //!< Bit mask for RTC_WAR_TPRW.
+#define BS_RTC_WAR_TPRW      (1U)          //!< Bit field size in bits for RTC_WAR_TPRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TPRW field.
+#define BR_RTC_WAR_TPRW      (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TPRW.
+#define BF_RTC_WAR_TPRW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TPRW), uint32_t) & BM_RTC_WAR_TPRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPRW field to a new value.
+#define BW_RTC_WAR_TPRW(v)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Alarm Register are ignored.
+ * - 1 - Writes to the Time Alarm Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TARW      (2U)          //!< Bit position for RTC_WAR_TARW.
+#define BM_RTC_WAR_TARW      (0x00000004U) //!< Bit mask for RTC_WAR_TARW.
+#define BS_RTC_WAR_TARW      (1U)          //!< Bit field size in bits for RTC_WAR_TARW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TARW field.
+#define BR_RTC_WAR_TARW      (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TARW.
+#define BF_RTC_WAR_TARW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TARW), uint32_t) & BM_RTC_WAR_TARW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TARW field to a new value.
+#define BW_RTC_WAR_TARW(v)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Compensation Register are ignored.
+ * - 1 - Writes to the Time Compensation Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TCRW      (3U)          //!< Bit position for RTC_WAR_TCRW.
+#define BM_RTC_WAR_TCRW      (0x00000008U) //!< Bit mask for RTC_WAR_TCRW.
+#define BS_RTC_WAR_TCRW      (1U)          //!< Bit field size in bits for RTC_WAR_TCRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TCRW field.
+#define BR_RTC_WAR_TCRW      (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TCRW.
+#define BF_RTC_WAR_TCRW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TCRW), uint32_t) & BM_RTC_WAR_TCRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRW field to a new value.
+#define BW_RTC_WAR_TCRW(v)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Control Register are ignored.
+ * - 1 - Writes to the Control Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_CRW       (4U)          //!< Bit position for RTC_WAR_CRW.
+#define BM_RTC_WAR_CRW       (0x00000010U) //!< Bit mask for RTC_WAR_CRW.
+#define BS_RTC_WAR_CRW       (1U)          //!< Bit field size in bits for RTC_WAR_CRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_CRW field.
+#define BR_RTC_WAR_CRW       (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_CRW.
+#define BF_RTC_WAR_CRW(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_CRW), uint32_t) & BM_RTC_WAR_CRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRW field to a new value.
+#define BW_RTC_WAR_CRW(v)    (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Status Register are ignored.
+ * - 1 - Writes to the Status Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_SRW       (5U)          //!< Bit position for RTC_WAR_SRW.
+#define BM_RTC_WAR_SRW       (0x00000020U) //!< Bit mask for RTC_WAR_SRW.
+#define BS_RTC_WAR_SRW       (1U)          //!< Bit field size in bits for RTC_WAR_SRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_SRW field.
+#define BR_RTC_WAR_SRW       (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_SRW.
+#define BF_RTC_WAR_SRW(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_SRW), uint32_t) & BM_RTC_WAR_SRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRW field to a new value.
+#define BW_RTC_WAR_SRW(v)    (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Lock Register are ignored.
+ * - 1 - Writes to the Lock Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_LRW       (6U)          //!< Bit position for RTC_WAR_LRW.
+#define BM_RTC_WAR_LRW       (0x00000040U) //!< Bit mask for RTC_WAR_LRW.
+#define BS_RTC_WAR_LRW       (1U)          //!< Bit field size in bits for RTC_WAR_LRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_LRW field.
+#define BR_RTC_WAR_LRW       (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_LRW.
+#define BF_RTC_WAR_LRW(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_LRW), uint32_t) & BM_RTC_WAR_LRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LRW field to a new value.
+#define BW_RTC_WAR_LRW(v)    (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Interupt Enable Register are ignored.
+ * - 1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_IERW      (7U)          //!< Bit position for RTC_WAR_IERW.
+#define BM_RTC_WAR_IERW      (0x00000080U) //!< Bit mask for RTC_WAR_IERW.
+#define BS_RTC_WAR_IERW      (1U)          //!< Bit field size in bits for RTC_WAR_IERW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_IERW field.
+#define BR_RTC_WAR_IERW      (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_IERW.
+#define BF_RTC_WAR_IERW(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_IERW), uint32_t) & BM_RTC_WAR_IERW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IERW field to a new value.
+#define BW_RTC_WAR_IERW(v)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_RAR - RTC Read Access Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+typedef union _hw_rtc_rar
+{
+    uint32_t U;
+    struct _hw_rtc_rar_bitfields
+    {
+        uint32_t TSRR : 1;             //!< [0] Time Seconds Register Read
+        uint32_t TPRR : 1;             //!< [1] Time Prescaler Register Read
+        uint32_t TARR : 1;             //!< [2] Time Alarm Register Read
+        uint32_t TCRR : 1;             //!< [3] Time Compensation Register Read
+        uint32_t CRR : 1;              //!< [4] Control Register Read
+        uint32_t SRR : 1;              //!< [5] Status Register Read
+        uint32_t LRR : 1;              //!< [6] Lock Register Read
+        uint32_t IERR : 1;             //!< [7] Interrupt Enable Register Read
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_rtc_rar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+//@{
+#define HW_RTC_RAR_ADDR          (REGS_RTC_BASE + 0x804U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_RAR               (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR)
+#define HW_RTC_RAR_RD()          (HW_RTC_RAR.U)
+#define HW_RTC_RAR_WR(v)         (HW_RTC_RAR.U = (v))
+#define HW_RTC_RAR_SET(v)        (HW_RTC_RAR_WR(HW_RTC_RAR_RD() |  (v)))
+#define HW_RTC_RAR_CLR(v)        (HW_RTC_RAR_WR(HW_RTC_RAR_RD() & ~(v)))
+#define HW_RTC_RAR_TOG(v)        (HW_RTC_RAR_WR(HW_RTC_RAR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Seconds Register are ignored.
+ * - 1 - Reads to the Time Seconds Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TSRR      (0U)          //!< Bit position for RTC_RAR_TSRR.
+#define BM_RTC_RAR_TSRR      (0x00000001U) //!< Bit mask for RTC_RAR_TSRR.
+#define BS_RTC_RAR_TSRR      (1U)          //!< Bit field size in bits for RTC_RAR_TSRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TSRR field.
+#define BR_RTC_RAR_TSRR      (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TSRR.
+#define BF_RTC_RAR_TSRR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TSRR), uint32_t) & BM_RTC_RAR_TSRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSRR field to a new value.
+#define BW_RTC_RAR_TSRR(v)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Pprescaler Register are ignored.
+ * - 1 - Reads to the Time Prescaler Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TPRR      (1U)          //!< Bit position for RTC_RAR_TPRR.
+#define BM_RTC_RAR_TPRR      (0x00000002U) //!< Bit mask for RTC_RAR_TPRR.
+#define BS_RTC_RAR_TPRR      (1U)          //!< Bit field size in bits for RTC_RAR_TPRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TPRR field.
+#define BR_RTC_RAR_TPRR      (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TPRR.
+#define BF_RTC_RAR_TPRR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TPRR), uint32_t) & BM_RTC_RAR_TPRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPRR field to a new value.
+#define BW_RTC_RAR_TPRR(v)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Alarm Register are ignored.
+ * - 1 - Reads to the Time Alarm Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TARR      (2U)          //!< Bit position for RTC_RAR_TARR.
+#define BM_RTC_RAR_TARR      (0x00000004U) //!< Bit mask for RTC_RAR_TARR.
+#define BS_RTC_RAR_TARR      (1U)          //!< Bit field size in bits for RTC_RAR_TARR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TARR field.
+#define BR_RTC_RAR_TARR      (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TARR.
+#define BF_RTC_RAR_TARR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TARR), uint32_t) & BM_RTC_RAR_TARR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TARR field to a new value.
+#define BW_RTC_RAR_TARR(v)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Compensation Register are ignored.
+ * - 1 - Reads to the Time Compensation Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TCRR      (3U)          //!< Bit position for RTC_RAR_TCRR.
+#define BM_RTC_RAR_TCRR      (0x00000008U) //!< Bit mask for RTC_RAR_TCRR.
+#define BS_RTC_RAR_TCRR      (1U)          //!< Bit field size in bits for RTC_RAR_TCRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TCRR field.
+#define BR_RTC_RAR_TCRR      (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TCRR.
+#define BF_RTC_RAR_TCRR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TCRR), uint32_t) & BM_RTC_RAR_TCRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRR field to a new value.
+#define BW_RTC_RAR_TCRR(v)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Control Register are ignored.
+ * - 1 - Reads to the Control Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_CRR       (4U)          //!< Bit position for RTC_RAR_CRR.
+#define BM_RTC_RAR_CRR       (0x00000010U) //!< Bit mask for RTC_RAR_CRR.
+#define BS_RTC_RAR_CRR       (1U)          //!< Bit field size in bits for RTC_RAR_CRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_CRR field.
+#define BR_RTC_RAR_CRR       (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_CRR.
+#define BF_RTC_RAR_CRR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_CRR), uint32_t) & BM_RTC_RAR_CRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRR field to a new value.
+#define BW_RTC_RAR_CRR(v)    (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Status Register are ignored.
+ * - 1 - Reads to the Status Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_SRR       (5U)          //!< Bit position for RTC_RAR_SRR.
+#define BM_RTC_RAR_SRR       (0x00000020U) //!< Bit mask for RTC_RAR_SRR.
+#define BS_RTC_RAR_SRR       (1U)          //!< Bit field size in bits for RTC_RAR_SRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_SRR field.
+#define BR_RTC_RAR_SRR       (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_SRR.
+#define BF_RTC_RAR_SRR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_SRR), uint32_t) & BM_RTC_RAR_SRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRR field to a new value.
+#define BW_RTC_RAR_SRR(v)    (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Lock Register are ignored.
+ * - 1 - Reads to the Lock Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_LRR       (6U)          //!< Bit position for RTC_RAR_LRR.
+#define BM_RTC_RAR_LRR       (0x00000040U) //!< Bit mask for RTC_RAR_LRR.
+#define BS_RTC_RAR_LRR       (1U)          //!< Bit field size in bits for RTC_RAR_LRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_LRR field.
+#define BR_RTC_RAR_LRR       (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_LRR.
+#define BF_RTC_RAR_LRR(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_LRR), uint32_t) & BM_RTC_RAR_LRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LRR field to a new value.
+#define BW_RTC_RAR_LRR(v)    (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Interrupt Enable Register are ignored.
+ * - 1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_IERR      (7U)          //!< Bit position for RTC_RAR_IERR.
+#define BM_RTC_RAR_IERR      (0x00000080U) //!< Bit mask for RTC_RAR_IERR.
+#define BS_RTC_RAR_IERR      (1U)          //!< Bit field size in bits for RTC_RAR_IERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_IERR field.
+#define BR_RTC_RAR_IERR      (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_IERR.
+#define BF_RTC_RAR_IERR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_IERR), uint32_t) & BM_RTC_RAR_IERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IERR field to a new value.
+#define BW_RTC_RAR_IERR(v)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rtc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RTC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rtc
+{
+    __IO hw_rtc_tsr_t TSR;                 //!< [0x0] RTC Time Seconds Register
+    __IO hw_rtc_tpr_t TPR;                 //!< [0x4] RTC Time Prescaler Register
+    __IO hw_rtc_tar_t TAR;                 //!< [0x8] RTC Time Alarm Register
+    __IO hw_rtc_tcr_t TCR;                 //!< [0xC] RTC Time Compensation Register
+    __IO hw_rtc_cr_t CR;                   //!< [0x10] RTC Control Register
+    __IO hw_rtc_sr_t SR;                   //!< [0x14] RTC Status Register
+    __IO hw_rtc_lr_t LR;                   //!< [0x18] RTC Lock Register
+    __IO hw_rtc_ier_t IER;                 //!< [0x1C] RTC Interrupt Enable Register
+    uint8_t _reserved0[2016];
+    __IO hw_rtc_war_t WAR;                 //!< [0x800] RTC Write Access Register
+    __IO hw_rtc_rar_t RAR;                 //!< [0x804] RTC Read Access Register
+} hw_rtc_t;
+#pragma pack()
+
+//! @brief Macro to access all RTC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_RTC</code>.
+#define HW_RTC         (*(hw_rtc_t *) REGS_RTC_BASE)
+#endif
+
+#endif // __HW_RTC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h
new file mode 100644
index 0000000000..c562f7be36
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h
@@ -0,0 +1,5761 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SDHC_REGISTERS_H__
+#define __HW_SDHC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - HW_SDHC_DSADDR - DMA System Address register
+ * - HW_SDHC_BLKATTR - Block Attributes register
+ * - HW_SDHC_CMDARG - Command Argument register
+ * - HW_SDHC_XFERTYP - Transfer Type register
+ * - HW_SDHC_CMDRSP0 - Command Response 0
+ * - HW_SDHC_CMDRSP1 - Command Response 1
+ * - HW_SDHC_CMDRSP2 - Command Response 2
+ * - HW_SDHC_CMDRSP3 - Command Response 3
+ * - HW_SDHC_DATPORT - Buffer Data Port register
+ * - HW_SDHC_PRSSTAT - Present State register
+ * - HW_SDHC_PROCTL - Protocol Control register
+ * - HW_SDHC_SYSCTL - System Control register
+ * - HW_SDHC_IRQSTAT - Interrupt Status register
+ * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - HW_SDHC_HTCAPBLT - Host Controller Capabilities
+ * - HW_SDHC_WML - Watermark Level Register
+ * - HW_SDHC_FEVT - Force Event register
+ * - HW_SDHC_ADMAES - ADMA Error Status register
+ * - HW_SDHC_ADSADDR - ADMA System Addressregister
+ * - HW_SDHC_VENDOR - Vendor Specific register
+ * - HW_SDHC_MMCBOOT - MMC Boot register
+ * - HW_SDHC_HOSTVER - Host Controller Version
+ *
+ * - hw_sdhc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SDHC_BASE
+#define HW_SDHC_INSTANCE_COUNT (1U) //!< Number of instances of the SDHC module.
+#define REGS_SDHC_BASE (0x400B1000U) //!< Base address for SDHC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_DSADDR - DMA System Address register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+typedef union _hw_sdhc_dsaddr
+{
+    uint32_t U;
+    struct _hw_sdhc_dsaddr_bitfields
+    {
+        uint32_t RESERVED0 : 2;        //!< [1:0]
+        uint32_t DSADDR : 30;          //!< [31:2] DMA System Address
+    } B;
+} hw_sdhc_dsaddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+//@{
+#define HW_SDHC_DSADDR_ADDR      (REGS_SDHC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_DSADDR           (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR)
+#define HW_SDHC_DSADDR_RD()      (HW_SDHC_DSADDR.U)
+#define HW_SDHC_DSADDR_WR(v)     (HW_SDHC_DSADDR.U = (v))
+#define HW_SDHC_DSADDR_SET(v)    (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() |  (v)))
+#define HW_SDHC_DSADDR_CLR(v)    (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() & ~(v)))
+#define HW_SDHC_DSADDR_TOG(v)    (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+//@{
+#define BP_SDHC_DSADDR_DSADDR (2U)         //!< Bit position for SDHC_DSADDR_DSADDR.
+#define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_DSADDR_DSADDR.
+#define BS_SDHC_DSADDR_DSADDR (30U)        //!< Bit field size in bits for SDHC_DSADDR_DSADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_DSADDR_DSADDR field.
+#define BR_SDHC_DSADDR_DSADDR (HW_SDHC_DSADDR.B.DSADDR)
+#endif
+
+//! @brief Format value for bitfield SDHC_DSADDR_DSADDR.
+#define BF_SDHC_DSADDR_DSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DSADDR_DSADDR), uint32_t) & BM_SDHC_DSADDR_DSADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DSADDR field to a new value.
+#define BW_SDHC_DSADDR_DSADDR(v) (HW_SDHC_DSADDR_WR((HW_SDHC_DSADDR_RD() & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_BLKATTR - Block Attributes register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+typedef union _hw_sdhc_blkattr
+{
+    uint32_t U;
+    struct _hw_sdhc_blkattr_bitfields
+    {
+        uint32_t BLKSIZE : 13;         //!< [12:0] Transfer Block Size
+        uint32_t RESERVED0 : 3;        //!< [15:13]
+        uint32_t BLKCNT : 16;          //!< [31:16] Blocks Count For Current Transfer
+    } B;
+} hw_sdhc_blkattr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+//@{
+#define HW_SDHC_BLKATTR_ADDR     (REGS_SDHC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_BLKATTR          (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR)
+#define HW_SDHC_BLKATTR_RD()     (HW_SDHC_BLKATTR.U)
+#define HW_SDHC_BLKATTR_WR(v)    (HW_SDHC_BLKATTR.U = (v))
+#define HW_SDHC_BLKATTR_SET(v)   (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() |  (v)))
+#define HW_SDHC_BLKATTR_CLR(v)   (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() & ~(v)))
+#define HW_SDHC_BLKATTR_TOG(v)   (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0 - No data transfer.
+ * - 1 - 1 Byte
+ * - 10 - 2 Bytes
+ * - 11 - 3 Bytes
+ * - 100 - 4 Bytes
+ * - 111111111 - 511 Bytes
+ * - 1000000000 - 512 Bytes
+ * - 100000000000 - 2048 Bytes
+ * - 1000000000000 - 4096 Bytes
+ */
+//@{
+#define BP_SDHC_BLKATTR_BLKSIZE (0U)       //!< Bit position for SDHC_BLKATTR_BLKSIZE.
+#define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) //!< Bit mask for SDHC_BLKATTR_BLKSIZE.
+#define BS_SDHC_BLKATTR_BLKSIZE (13U)      //!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field.
+#define BR_SDHC_BLKATTR_BLKSIZE (HW_SDHC_BLKATTR.B.BLKSIZE)
+#endif
+
+//! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE.
+#define BF_SDHC_BLKATTR_BLKSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKSIZE), uint32_t) & BM_SDHC_BLKATTR_BLKSIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BLKSIZE field to a new value.
+#define BW_SDHC_BLKATTR_BLKSIZE(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0 - Stop count.
+ * - 1 - 1 block
+ * - 10 - 2 blocks
+ * - 1111111111111111 - 65535 blocks
+ */
+//@{
+#define BP_SDHC_BLKATTR_BLKCNT (16U)       //!< Bit position for SDHC_BLKATTR_BLKCNT.
+#define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_BLKATTR_BLKCNT.
+#define BS_SDHC_BLKATTR_BLKCNT (16U)       //!< Bit field size in bits for SDHC_BLKATTR_BLKCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_BLKATTR_BLKCNT field.
+#define BR_SDHC_BLKATTR_BLKCNT (HW_SDHC_BLKATTR.B.BLKCNT)
+#endif
+
+//! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT.
+#define BF_SDHC_BLKATTR_BLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKCNT), uint32_t) & BM_SDHC_BLKATTR_BLKCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BLKCNT field to a new value.
+#define BW_SDHC_BLKATTR_BLKCNT(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDARG - Command Argument register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+typedef union _hw_sdhc_cmdarg
+{
+    uint32_t U;
+    struct _hw_sdhc_cmdarg_bitfields
+    {
+        uint32_t CMDARG : 32;          //!< [31:0] Command Argument
+    } B;
+} hw_sdhc_cmdarg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+//@{
+#define HW_SDHC_CMDARG_ADDR      (REGS_SDHC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDARG           (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR)
+#define HW_SDHC_CMDARG_RD()      (HW_SDHC_CMDARG.U)
+#define HW_SDHC_CMDARG_WR(v)     (HW_SDHC_CMDARG.U = (v))
+#define HW_SDHC_CMDARG_SET(v)    (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() |  (v)))
+#define HW_SDHC_CMDARG_CLR(v)    (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() & ~(v)))
+#define HW_SDHC_CMDARG_TOG(v)    (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDARG bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
+ *
+ * The SD/MMC command argument is specified as bits 39-8 of the command format
+ * in the SD or MMC specification. This register is write protected when
+ * PRSSTAT[CDIHB0] is set.
+ */
+//@{
+#define BP_SDHC_CMDARG_CMDARG (0U)         //!< Bit position for SDHC_CMDARG_CMDARG.
+#define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDARG_CMDARG.
+#define BS_SDHC_CMDARG_CMDARG (32U)        //!< Bit field size in bits for SDHC_CMDARG_CMDARG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDARG_CMDARG field.
+#define BR_SDHC_CMDARG_CMDARG (HW_SDHC_CMDARG.U)
+#endif
+
+//! @brief Format value for bitfield SDHC_CMDARG_CMDARG.
+#define BF_SDHC_CMDARG_CMDARG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_CMDARG_CMDARG), uint32_t) & BM_SDHC_CMDARG_CMDARG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMDARG field to a new value.
+#define BW_SDHC_CMDARG_CMDARG(v) (HW_SDHC_CMDARG_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_XFERTYP - Transfer Type register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+typedef union _hw_sdhc_xfertyp
+{
+    uint32_t U;
+    struct _hw_sdhc_xfertyp_bitfields
+    {
+        uint32_t DMAEN : 1;            //!< [0] DMA Enable
+        uint32_t BCEN : 1;             //!< [1] Block Count Enable
+        uint32_t AC12EN : 1;           //!< [2] Auto CMD12 Enable
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t DTDSEL : 1;           //!< [4] Data Transfer Direction Select
+        uint32_t MSBSEL : 1;           //!< [5] Multi/Single Block Select
+        uint32_t RESERVED1 : 10;       //!< [15:6]
+        uint32_t RSPTYP : 2;           //!< [17:16] Response Type Select
+        uint32_t RESERVED2 : 1;        //!< [18]
+        uint32_t CCCEN : 1;            //!< [19] Command CRC Check Enable
+        uint32_t CICEN : 1;            //!< [20] Command Index Check Enable
+        uint32_t DPSEL : 1;            //!< [21] Data Present Select
+        uint32_t CMDTYP : 2;           //!< [23:22] Command Type
+        uint32_t CMDINX : 6;           //!< [29:24] Command Index
+        uint32_t RESERVED3 : 2;        //!< [31:30]
+    } B;
+} hw_sdhc_xfertyp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+//@{
+#define HW_SDHC_XFERTYP_ADDR     (REGS_SDHC_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_XFERTYP          (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR)
+#define HW_SDHC_XFERTYP_RD()     (HW_SDHC_XFERTYP.U)
+#define HW_SDHC_XFERTYP_WR(v)    (HW_SDHC_XFERTYP.U = (v))
+#define HW_SDHC_XFERTYP_SET(v)   (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() |  (v)))
+#define HW_SDHC_XFERTYP_CLR(v)   (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() & ~(v)))
+#define HW_SDHC_XFERTYP_TOG(v)   (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_DMAEN (0U)         //!< Bit position for SDHC_XFERTYP_DMAEN.
+#define BM_SDHC_XFERTYP_DMAEN (0x00000001U) //!< Bit mask for SDHC_XFERTYP_DMAEN.
+#define BS_SDHC_XFERTYP_DMAEN (1U)         //!< Bit field size in bits for SDHC_XFERTYP_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_DMAEN field.
+#define BR_SDHC_XFERTYP_DMAEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_DMAEN.
+#define BF_SDHC_XFERTYP_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DMAEN), uint32_t) & BM_SDHC_XFERTYP_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_SDHC_XFERTYP_DMAEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_BCEN (1U)          //!< Bit position for SDHC_XFERTYP_BCEN.
+#define BM_SDHC_XFERTYP_BCEN (0x00000002U) //!< Bit mask for SDHC_XFERTYP_BCEN.
+#define BS_SDHC_XFERTYP_BCEN (1U)          //!< Bit field size in bits for SDHC_XFERTYP_BCEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_BCEN field.
+#define BR_SDHC_XFERTYP_BCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_BCEN.
+#define BF_SDHC_XFERTYP_BCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_BCEN), uint32_t) & BM_SDHC_XFERTYP_BCEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCEN field to a new value.
+#define BW_SDHC_XFERTYP_BCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_AC12EN (2U)        //!< Bit position for SDHC_XFERTYP_AC12EN.
+#define BM_SDHC_XFERTYP_AC12EN (0x00000004U) //!< Bit mask for SDHC_XFERTYP_AC12EN.
+#define BS_SDHC_XFERTYP_AC12EN (1U)        //!< Bit field size in bits for SDHC_XFERTYP_AC12EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_AC12EN field.
+#define BR_SDHC_XFERTYP_AC12EN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_AC12EN.
+#define BF_SDHC_XFERTYP_AC12EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_AC12EN), uint32_t) & BM_SDHC_XFERTYP_AC12EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12EN field to a new value.
+#define BW_SDHC_XFERTYP_AC12EN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0 - Write host to card.
+ * - 1 - Read card to host.
+ */
+//@{
+#define BP_SDHC_XFERTYP_DTDSEL (4U)        //!< Bit position for SDHC_XFERTYP_DTDSEL.
+#define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) //!< Bit mask for SDHC_XFERTYP_DTDSEL.
+#define BS_SDHC_XFERTYP_DTDSEL (1U)        //!< Bit field size in bits for SDHC_XFERTYP_DTDSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_DTDSEL field.
+#define BR_SDHC_XFERTYP_DTDSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL.
+#define BF_SDHC_XFERTYP_DTDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DTDSEL), uint32_t) & BM_SDHC_XFERTYP_DTDSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTDSEL field to a new value.
+#define BW_SDHC_XFERTYP_DTDSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0 - Single block.
+ * - 1 - Multiple blocks.
+ */
+//@{
+#define BP_SDHC_XFERTYP_MSBSEL (5U)        //!< Bit position for SDHC_XFERTYP_MSBSEL.
+#define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) //!< Bit mask for SDHC_XFERTYP_MSBSEL.
+#define BS_SDHC_XFERTYP_MSBSEL (1U)        //!< Bit field size in bits for SDHC_XFERTYP_MSBSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_MSBSEL field.
+#define BR_SDHC_XFERTYP_MSBSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL.
+#define BF_SDHC_XFERTYP_MSBSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_MSBSEL), uint32_t) & BM_SDHC_XFERTYP_MSBSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSBSEL field to a new value.
+#define BW_SDHC_XFERTYP_MSBSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 00 - No response.
+ * - 01 - Response length 136.
+ * - 10 - Response length 48.
+ * - 11 - Response length 48, check busy after response.
+ */
+//@{
+#define BP_SDHC_XFERTYP_RSPTYP (16U)       //!< Bit position for SDHC_XFERTYP_RSPTYP.
+#define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) //!< Bit mask for SDHC_XFERTYP_RSPTYP.
+#define BS_SDHC_XFERTYP_RSPTYP (2U)        //!< Bit field size in bits for SDHC_XFERTYP_RSPTYP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_RSPTYP field.
+#define BR_SDHC_XFERTYP_RSPTYP (HW_SDHC_XFERTYP.B.RSPTYP)
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP.
+#define BF_SDHC_XFERTYP_RSPTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_RSPTYP), uint32_t) & BM_SDHC_XFERTYP_RSPTYP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSPTYP field to a new value.
+#define BW_SDHC_XFERTYP_RSPTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_CCCEN (19U)        //!< Bit position for SDHC_XFERTYP_CCCEN.
+#define BM_SDHC_XFERTYP_CCCEN (0x00080000U) //!< Bit mask for SDHC_XFERTYP_CCCEN.
+#define BS_SDHC_XFERTYP_CCCEN (1U)         //!< Bit field size in bits for SDHC_XFERTYP_CCCEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CCCEN field.
+#define BR_SDHC_XFERTYP_CCCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CCCEN.
+#define BF_SDHC_XFERTYP_CCCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CCCEN), uint32_t) & BM_SDHC_XFERTYP_CCCEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCCEN field to a new value.
+#define BW_SDHC_XFERTYP_CCCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_CICEN (20U)        //!< Bit position for SDHC_XFERTYP_CICEN.
+#define BM_SDHC_XFERTYP_CICEN (0x00100000U) //!< Bit mask for SDHC_XFERTYP_CICEN.
+#define BS_SDHC_XFERTYP_CICEN (1U)         //!< Bit field size in bits for SDHC_XFERTYP_CICEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CICEN field.
+#define BR_SDHC_XFERTYP_CICEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CICEN.
+#define BF_SDHC_XFERTYP_CICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CICEN), uint32_t) & BM_SDHC_XFERTYP_CICEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CICEN field to a new value.
+#define BW_SDHC_XFERTYP_CICEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0 - No data present.
+ * - 1 - Data present.
+ */
+//@{
+#define BP_SDHC_XFERTYP_DPSEL (21U)        //!< Bit position for SDHC_XFERTYP_DPSEL.
+#define BM_SDHC_XFERTYP_DPSEL (0x00200000U) //!< Bit mask for SDHC_XFERTYP_DPSEL.
+#define BS_SDHC_XFERTYP_DPSEL (1U)         //!< Bit field size in bits for SDHC_XFERTYP_DPSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_DPSEL field.
+#define BR_SDHC_XFERTYP_DPSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_DPSEL.
+#define BF_SDHC_XFERTYP_DPSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DPSEL), uint32_t) & BM_SDHC_XFERTYP_DPSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPSEL field to a new value.
+#define BW_SDHC_XFERTYP_DPSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 00 - Normal other commands.
+ * - 01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 10 - Resume CMD52 for writing function select in CCCR.
+ * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+//@{
+#define BP_SDHC_XFERTYP_CMDTYP (22U)       //!< Bit position for SDHC_XFERTYP_CMDTYP.
+#define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) //!< Bit mask for SDHC_XFERTYP_CMDTYP.
+#define BS_SDHC_XFERTYP_CMDTYP (2U)        //!< Bit field size in bits for SDHC_XFERTYP_CMDTYP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CMDTYP field.
+#define BR_SDHC_XFERTYP_CMDTYP (HW_SDHC_XFERTYP.B.CMDTYP)
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP.
+#define BF_SDHC_XFERTYP_CMDTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDTYP), uint32_t) & BM_SDHC_XFERTYP_CMDTYP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMDTYP field to a new value.
+#define BW_SDHC_XFERTYP_CMDTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+//@{
+#define BP_SDHC_XFERTYP_CMDINX (24U)       //!< Bit position for SDHC_XFERTYP_CMDINX.
+#define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) //!< Bit mask for SDHC_XFERTYP_CMDINX.
+#define BS_SDHC_XFERTYP_CMDINX (6U)        //!< Bit field size in bits for SDHC_XFERTYP_CMDINX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CMDINX field.
+#define BR_SDHC_XFERTYP_CMDINX (HW_SDHC_XFERTYP.B.CMDINX)
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CMDINX.
+#define BF_SDHC_XFERTYP_CMDINX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDINX), uint32_t) & BM_SDHC_XFERTYP_CMDINX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMDINX field to a new value.
+#define BW_SDHC_XFERTYP_CMDINX(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP0 - Command Response 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+typedef union _hw_sdhc_cmdrsp0
+{
+    uint32_t U;
+    struct _hw_sdhc_cmdrsp0_bitfields
+    {
+        uint32_t CMDRSP0 : 32;         //!< [31:0] Command Response 0
+    } B;
+} hw_sdhc_cmdrsp0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP0 register
+ */
+//@{
+#define HW_SDHC_CMDRSP0_ADDR     (REGS_SDHC_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP0          (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR)
+#define HW_SDHC_CMDRSP0_RD()     (HW_SDHC_CMDRSP0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP0 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP0_CMDRSP0 (0U)       //!< Bit position for SDHC_CMDRSP0_CMDRSP0.
+#define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP0_CMDRSP0.
+#define BS_SDHC_CMDRSP0_CMDRSP0 (32U)      //!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field.
+#define BR_SDHC_CMDRSP0_CMDRSP0 (HW_SDHC_CMDRSP0.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP1 - Command Response 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 1 of the response bits from the card.
+ */
+typedef union _hw_sdhc_cmdrsp1
+{
+    uint32_t U;
+    struct _hw_sdhc_cmdrsp1_bitfields
+    {
+        uint32_t CMDRSP1 : 32;         //!< [31:0] Command Response 1
+    } B;
+} hw_sdhc_cmdrsp1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP1 register
+ */
+//@{
+#define HW_SDHC_CMDRSP1_ADDR     (REGS_SDHC_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP1          (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR)
+#define HW_SDHC_CMDRSP1_RD()     (HW_SDHC_CMDRSP1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP1 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP1_CMDRSP1 (0U)       //!< Bit position for SDHC_CMDRSP1_CMDRSP1.
+#define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP1_CMDRSP1.
+#define BS_SDHC_CMDRSP1_CMDRSP1 (32U)      //!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field.
+#define BR_SDHC_CMDRSP1_CMDRSP1 (HW_SDHC_CMDRSP1.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP2 - Command Response 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 2 of the response bits from the card.
+ */
+typedef union _hw_sdhc_cmdrsp2
+{
+    uint32_t U;
+    struct _hw_sdhc_cmdrsp2_bitfields
+    {
+        uint32_t CMDRSP2 : 32;         //!< [31:0] Command Response 2
+    } B;
+} hw_sdhc_cmdrsp2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP2 register
+ */
+//@{
+#define HW_SDHC_CMDRSP2_ADDR     (REGS_SDHC_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP2          (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR)
+#define HW_SDHC_CMDRSP2_RD()     (HW_SDHC_CMDRSP2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP2 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP2_CMDRSP2 (0U)       //!< Bit position for SDHC_CMDRSP2_CMDRSP2.
+#define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP2_CMDRSP2.
+#define BS_SDHC_CMDRSP2_CMDRSP2 (32U)      //!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field.
+#define BR_SDHC_CMDRSP2_CMDRSP2 (HW_SDHC_CMDRSP2.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP3 - Command Response 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 3 of the response bits from the card. The
+ * following table describes the mapping of command responses from the SD bus to
+ * command response registers for each response type. In the table, R[ ] refers
+ * to a bit range within the response data as transmitted on the SD bus. Response
+ * bit definition for each response type Response type Meaning of response
+ * Response field Response register R1,R1b (normal response) Card status R[39:8]
+ * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
+ * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
+ * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
+ * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
+ * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
+ * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
+ * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
+ * register. Responses of type R1b (auto CMD12 responses) have response data bits
+ * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
+ * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
+ * registers. To be able to read the response status efficiently, the SDHC stores
+ * only a part of the response data in the command response registers. This
+ * enables the host driver to efficiently read 32-bit of response data in one read
+ * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
+ * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * and generate an error interrupt if any error is detected. The bit range for the
+ * CRC check depends on the response length. If the response length is 48, the
+ * SDHC will check R[47:1], and if the response length is 136 the SDHC will check
+ * R[119:1]. Because the SDHC may have a multiple block data transfer executing
+ * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
+ * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
+ * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
+ * and vice versa. When the SDHC modifies part of the command response
+ * registers, as shown in the table above, it preserves the unmodified bits.
+ */
+typedef union _hw_sdhc_cmdrsp3
+{
+    uint32_t U;
+    struct _hw_sdhc_cmdrsp3_bitfields
+    {
+        uint32_t CMDRSP3 : 32;         //!< [31:0] Command Response 3
+    } B;
+} hw_sdhc_cmdrsp3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP3 register
+ */
+//@{
+#define HW_SDHC_CMDRSP3_ADDR     (REGS_SDHC_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP3          (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR)
+#define HW_SDHC_CMDRSP3_RD()     (HW_SDHC_CMDRSP3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP3 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP3_CMDRSP3 (0U)       //!< Bit position for SDHC_CMDRSP3_CMDRSP3.
+#define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP3_CMDRSP3.
+#define BS_SDHC_CMDRSP3_CMDRSP3 (32U)      //!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field.
+#define BR_SDHC_CMDRSP3_CMDRSP3 (HW_SDHC_CMDRSP3.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_DATPORT - Buffer Data Port register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+typedef union _hw_sdhc_datport
+{
+    uint32_t U;
+    struct _hw_sdhc_datport_bitfields
+    {
+        uint32_t DATCONT : 32;         //!< [31:0] Data Content
+    } B;
+} hw_sdhc_datport_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+//@{
+#define HW_SDHC_DATPORT_ADDR     (REGS_SDHC_BASE + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_DATPORT          (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR)
+#define HW_SDHC_DATPORT_RD()     (HW_SDHC_DATPORT.U)
+#define HW_SDHC_DATPORT_WR(v)    (HW_SDHC_DATPORT.U = (v))
+#define HW_SDHC_DATPORT_SET(v)   (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() |  (v)))
+#define HW_SDHC_DATPORT_CLR(v)   (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() & ~(v)))
+#define HW_SDHC_DATPORT_TOG(v)   (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_DATPORT bitfields
+ */
+
+/*!
+ * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
+ *
+ * The Buffer Data Port register is for 32-bit data access by the CPU or the
+ * external DMA. When the internal DMA is enabled, any write to this register is
+ * ignored, and any read from this register will always yield 0s.
+ */
+//@{
+#define BP_SDHC_DATPORT_DATCONT (0U)       //!< Bit position for SDHC_DATPORT_DATCONT.
+#define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) //!< Bit mask for SDHC_DATPORT_DATCONT.
+#define BS_SDHC_DATPORT_DATCONT (32U)      //!< Bit field size in bits for SDHC_DATPORT_DATCONT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_DATPORT_DATCONT field.
+#define BR_SDHC_DATPORT_DATCONT (HW_SDHC_DATPORT.U)
+#endif
+
+//! @brief Format value for bitfield SDHC_DATPORT_DATCONT.
+#define BF_SDHC_DATPORT_DATCONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DATPORT_DATCONT), uint32_t) & BM_SDHC_DATPORT_DATCONT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATCONT field to a new value.
+#define BW_SDHC_DATPORT_DATCONT(v) (HW_SDHC_DATPORT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_PRSSTAT - Present State register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+typedef union _hw_sdhc_prsstat
+{
+    uint32_t U;
+    struct _hw_sdhc_prsstat_bitfields
+    {
+        uint32_t CIHB : 1;             //!< [0] Command Inhibit (CMD)
+        uint32_t CDIHB : 1;            //!< [1] Command Inhibit (DAT)
+        uint32_t DLA : 1;              //!< [2] Data Line Active
+        uint32_t SDSTB : 1;            //!< [3] SD Clock Stable
+        uint32_t IPGOFF : 1;           //!< [4] Bus Clock Gated Off Internally
+        uint32_t HCKOFF : 1;           //!< [5] System Clock Gated Off Internally
+        uint32_t PEROFF : 1;           //!< [6] SDHC clock Gated Off Internally
+        uint32_t SDOFF : 1;            //!< [7] SD Clock Gated Off Internally
+        uint32_t WTA : 1;              //!< [8] Write Transfer Active
+        uint32_t RTA : 1;              //!< [9] Read Transfer Active
+        uint32_t BWEN : 1;             //!< [10] Buffer Write Enable
+        uint32_t BREN : 1;             //!< [11] Buffer Read Enable
+        uint32_t RESERVED0 : 4;        //!< [15:12]
+        uint32_t CINS : 1;             //!< [16] Card Inserted
+        uint32_t RESERVED1 : 6;        //!< [22:17]
+        uint32_t CLSL : 1;             //!< [23] CMD Line Signal Level
+        uint32_t DLSL : 8;             //!< [31:24] DAT Line Signal Level
+    } B;
+} hw_sdhc_prsstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+//@{
+#define HW_SDHC_PRSSTAT_ADDR     (REGS_SDHC_BASE + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_PRSSTAT          (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR)
+#define HW_SDHC_PRSSTAT_RD()     (HW_SDHC_PRSSTAT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0 - Can issue command using only CMD line.
+ * - 1 - Cannot issue command.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CIHB (0U)          //!< Bit position for SDHC_PRSSTAT_CIHB.
+#define BM_SDHC_PRSSTAT_CIHB (0x00000001U) //!< Bit mask for SDHC_PRSSTAT_CIHB.
+#define BS_SDHC_PRSSTAT_CIHB (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_CIHB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CIHB field.
+#define BR_SDHC_PRSSTAT_CIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CIHB))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0 - Can issue command which uses the DAT line.
+ * - 1 - Cannot issue command which uses the DAT line.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CDIHB (1U)         //!< Bit position for SDHC_PRSSTAT_CDIHB.
+#define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) //!< Bit mask for SDHC_PRSSTAT_CDIHB.
+#define BS_SDHC_PRSSTAT_CDIHB (1U)         //!< Bit field size in bits for SDHC_PRSSTAT_CDIHB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CDIHB field.
+#define BR_SDHC_PRSSTAT_CDIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CDIHB))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0 - DAT line inactive.
+ * - 1 - DAT line active.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_DLA  (2U)          //!< Bit position for SDHC_PRSSTAT_DLA.
+#define BM_SDHC_PRSSTAT_DLA  (0x00000004U) //!< Bit mask for SDHC_PRSSTAT_DLA.
+#define BS_SDHC_PRSSTAT_DLA  (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_DLA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_DLA field.
+#define BR_SDHC_PRSSTAT_DLA  (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_DLA))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0 - Clock is changing frequency and not stable.
+ * - 1 - Clock is stable.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_SDSTB (3U)         //!< Bit position for SDHC_PRSSTAT_SDSTB.
+#define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) //!< Bit mask for SDHC_PRSSTAT_SDSTB.
+#define BS_SDHC_PRSSTAT_SDSTB (1U)         //!< Bit field size in bits for SDHC_PRSSTAT_SDSTB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_SDSTB field.
+#define BR_SDHC_PRSSTAT_SDSTB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDSTB))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0 - Bus clock is active.
+ * - 1 - Bus clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_IPGOFF (4U)        //!< Bit position for SDHC_PRSSTAT_IPGOFF.
+#define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) //!< Bit mask for SDHC_PRSSTAT_IPGOFF.
+#define BS_SDHC_PRSSTAT_IPGOFF (1U)        //!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field.
+#define BR_SDHC_PRSSTAT_IPGOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_IPGOFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0 - System clock is active.
+ * - 1 - System clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_HCKOFF (5U)        //!< Bit position for SDHC_PRSSTAT_HCKOFF.
+#define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) //!< Bit mask for SDHC_PRSSTAT_HCKOFF.
+#define BS_SDHC_PRSSTAT_HCKOFF (1U)        //!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field.
+#define BR_SDHC_PRSSTAT_HCKOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_HCKOFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0 - SDHC clock is active.
+ * - 1 - SDHC clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_PEROFF (6U)        //!< Bit position for SDHC_PRSSTAT_PEROFF.
+#define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) //!< Bit mask for SDHC_PRSSTAT_PEROFF.
+#define BS_SDHC_PRSSTAT_PEROFF (1U)        //!< Bit field size in bits for SDHC_PRSSTAT_PEROFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_PEROFF field.
+#define BR_SDHC_PRSSTAT_PEROFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_PEROFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0 - SD clock is active.
+ * - 1 - SD clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_SDOFF (7U)         //!< Bit position for SDHC_PRSSTAT_SDOFF.
+#define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) //!< Bit mask for SDHC_PRSSTAT_SDOFF.
+#define BS_SDHC_PRSSTAT_SDOFF (1U)         //!< Bit field size in bits for SDHC_PRSSTAT_SDOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_SDOFF field.
+#define BR_SDHC_PRSSTAT_SDOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDOFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0 - No valid data.
+ * - 1 - Transferring data.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_WTA  (8U)          //!< Bit position for SDHC_PRSSTAT_WTA.
+#define BM_SDHC_PRSSTAT_WTA  (0x00000100U) //!< Bit mask for SDHC_PRSSTAT_WTA.
+#define BS_SDHC_PRSSTAT_WTA  (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_WTA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_WTA field.
+#define BR_SDHC_PRSSTAT_WTA  (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_WTA))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0 - No valid data.
+ * - 1 - Transferring data.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_RTA  (9U)          //!< Bit position for SDHC_PRSSTAT_RTA.
+#define BM_SDHC_PRSSTAT_RTA  (0x00000200U) //!< Bit mask for SDHC_PRSSTAT_RTA.
+#define BS_SDHC_PRSSTAT_RTA  (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_RTA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_RTA field.
+#define BR_SDHC_PRSSTAT_RTA  (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_RTA))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_BWEN (10U)         //!< Bit position for SDHC_PRSSTAT_BWEN.
+#define BM_SDHC_PRSSTAT_BWEN (0x00000400U) //!< Bit mask for SDHC_PRSSTAT_BWEN.
+#define BS_SDHC_PRSSTAT_BWEN (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_BWEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_BWEN field.
+#define BR_SDHC_PRSSTAT_BWEN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BWEN))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_BREN (11U)         //!< Bit position for SDHC_PRSSTAT_BREN.
+#define BM_SDHC_PRSSTAT_BREN (0x00000800U) //!< Bit mask for SDHC_PRSSTAT_BREN.
+#define BS_SDHC_PRSSTAT_BREN (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_BREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_BREN field.
+#define BR_SDHC_PRSSTAT_BREN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BREN))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0 - Power on reset or no card.
+ * - 1 - Card inserted.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CINS (16U)         //!< Bit position for SDHC_PRSSTAT_CINS.
+#define BM_SDHC_PRSSTAT_CINS (0x00010000U) //!< Bit mask for SDHC_PRSSTAT_CINS.
+#define BS_SDHC_PRSSTAT_CINS (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_CINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CINS field.
+#define BR_SDHC_PRSSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CINS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CLSL (23U)         //!< Bit position for SDHC_PRSSTAT_CLSL.
+#define BM_SDHC_PRSSTAT_CLSL (0x00800000U) //!< Bit mask for SDHC_PRSSTAT_CLSL.
+#define BS_SDHC_PRSSTAT_CLSL (1U)          //!< Bit field size in bits for SDHC_PRSSTAT_CLSL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CLSL field.
+#define BR_SDHC_PRSSTAT_CLSL (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CLSL))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_DLSL (24U)         //!< Bit position for SDHC_PRSSTAT_DLSL.
+#define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) //!< Bit mask for SDHC_PRSSTAT_DLSL.
+#define BS_SDHC_PRSSTAT_DLSL (8U)          //!< Bit field size in bits for SDHC_PRSSTAT_DLSL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_DLSL field.
+#define BR_SDHC_PRSSTAT_DLSL (HW_SDHC_PRSSTAT.B.DLSL)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_PROCTL - Protocol Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+typedef union _hw_sdhc_proctl
+{
+    uint32_t U;
+    struct _hw_sdhc_proctl_bitfields
+    {
+        uint32_t LCTL : 1;             //!< [0] LED Control
+        uint32_t DTW : 2;              //!< [2:1] Data Transfer Width
+        uint32_t D3CD : 1;             //!< [3] DAT3 As Card Detection Pin
+        uint32_t EMODE : 2;            //!< [5:4] Endian Mode
+        uint32_t CDTL : 1;             //!< [6] Card Detect Test Level
+        uint32_t CDSS : 1;             //!< [7] Card Detect Signal Selection
+        uint32_t DMAS : 2;             //!< [9:8] DMA Select
+        uint32_t RESERVED0 : 6;        //!< [15:10]
+        uint32_t SABGREQ : 1;          //!< [16] Stop At Block Gap Request
+        uint32_t CREQ : 1;             //!< [17] Continue Request
+        uint32_t RWCTL : 1;            //!< [18] Read Wait Control
+        uint32_t IABG : 1;             //!< [19] Interrupt At Block Gap
+        uint32_t RESERVED1 : 4;        //!< [23:20]
+        uint32_t WECINT : 1;           //!< [24] Wakeup Event Enable On Card Interrupt
+        uint32_t WECINS : 1;           //!< [25] Wakeup Event Enable On SD Card
+                                       //! Insertion
+        uint32_t WECRM : 1;            //!< [26] Wakeup Event Enable On SD Card Removal
+        uint32_t RESERVED2 : 5;        //!< [31:27]
+    } B;
+} hw_sdhc_proctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+//@{
+#define HW_SDHC_PROCTL_ADDR      (REGS_SDHC_BASE + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_PROCTL           (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR)
+#define HW_SDHC_PROCTL_RD()      (HW_SDHC_PROCTL.U)
+#define HW_SDHC_PROCTL_WR(v)     (HW_SDHC_PROCTL.U = (v))
+#define HW_SDHC_PROCTL_SET(v)    (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() |  (v)))
+#define HW_SDHC_PROCTL_CLR(v)    (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() & ~(v)))
+#define HW_SDHC_PROCTL_TOG(v)    (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0 - LED off.
+ * - 1 - LED on.
+ */
+//@{
+#define BP_SDHC_PROCTL_LCTL  (0U)          //!< Bit position for SDHC_PROCTL_LCTL.
+#define BM_SDHC_PROCTL_LCTL  (0x00000001U) //!< Bit mask for SDHC_PROCTL_LCTL.
+#define BS_SDHC_PROCTL_LCTL  (1U)          //!< Bit field size in bits for SDHC_PROCTL_LCTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_LCTL field.
+#define BR_SDHC_PROCTL_LCTL  (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_LCTL.
+#define BF_SDHC_PROCTL_LCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_LCTL), uint32_t) & BM_SDHC_PROCTL_LCTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LCTL field to a new value.
+#define BW_SDHC_PROCTL_LCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 00 - 1-bit mode
+ * - 01 - 4-bit mode
+ * - 10 - 8-bit mode
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SDHC_PROCTL_DTW   (1U)          //!< Bit position for SDHC_PROCTL_DTW.
+#define BM_SDHC_PROCTL_DTW   (0x00000006U) //!< Bit mask for SDHC_PROCTL_DTW.
+#define BS_SDHC_PROCTL_DTW   (2U)          //!< Bit field size in bits for SDHC_PROCTL_DTW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_DTW field.
+#define BR_SDHC_PROCTL_DTW   (HW_SDHC_PROCTL.B.DTW)
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_DTW.
+#define BF_SDHC_PROCTL_DTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DTW), uint32_t) & BM_SDHC_PROCTL_DTW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTW field to a new value.
+#define BW_SDHC_PROCTL_DTW(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0 - DAT3 does not monitor card Insertion.
+ * - 1 - DAT3 as card detection pin.
+ */
+//@{
+#define BP_SDHC_PROCTL_D3CD  (3U)          //!< Bit position for SDHC_PROCTL_D3CD.
+#define BM_SDHC_PROCTL_D3CD  (0x00000008U) //!< Bit mask for SDHC_PROCTL_D3CD.
+#define BS_SDHC_PROCTL_D3CD  (1U)          //!< Bit field size in bits for SDHC_PROCTL_D3CD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_D3CD field.
+#define BR_SDHC_PROCTL_D3CD  (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_D3CD.
+#define BF_SDHC_PROCTL_D3CD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_D3CD), uint32_t) & BM_SDHC_PROCTL_D3CD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the D3CD field to a new value.
+#define BW_SDHC_PROCTL_D3CD(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 00 - Big endian mode
+ * - 01 - Half word big endian mode
+ * - 10 - Little endian mode
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SDHC_PROCTL_EMODE (4U)          //!< Bit position for SDHC_PROCTL_EMODE.
+#define BM_SDHC_PROCTL_EMODE (0x00000030U) //!< Bit mask for SDHC_PROCTL_EMODE.
+#define BS_SDHC_PROCTL_EMODE (2U)          //!< Bit field size in bits for SDHC_PROCTL_EMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_EMODE field.
+#define BR_SDHC_PROCTL_EMODE (HW_SDHC_PROCTL.B.EMODE)
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_EMODE.
+#define BF_SDHC_PROCTL_EMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_EMODE), uint32_t) & BM_SDHC_PROCTL_EMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EMODE field to a new value.
+#define BW_SDHC_PROCTL_EMODE(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0 - Card detect test level is 0, no card inserted.
+ * - 1 - Card detect test level is 1, card inserted.
+ */
+//@{
+#define BP_SDHC_PROCTL_CDTL  (6U)          //!< Bit position for SDHC_PROCTL_CDTL.
+#define BM_SDHC_PROCTL_CDTL  (0x00000040U) //!< Bit mask for SDHC_PROCTL_CDTL.
+#define BS_SDHC_PROCTL_CDTL  (1U)          //!< Bit field size in bits for SDHC_PROCTL_CDTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_CDTL field.
+#define BR_SDHC_PROCTL_CDTL  (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_CDTL.
+#define BF_SDHC_PROCTL_CDTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDTL), uint32_t) & BM_SDHC_PROCTL_CDTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CDTL field to a new value.
+#define BW_SDHC_PROCTL_CDTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0 - Card detection level is selected for normal purpose.
+ * - 1 - Card detection test level is selected for test purpose.
+ */
+//@{
+#define BP_SDHC_PROCTL_CDSS  (7U)          //!< Bit position for SDHC_PROCTL_CDSS.
+#define BM_SDHC_PROCTL_CDSS  (0x00000080U) //!< Bit mask for SDHC_PROCTL_CDSS.
+#define BS_SDHC_PROCTL_CDSS  (1U)          //!< Bit field size in bits for SDHC_PROCTL_CDSS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_CDSS field.
+#define BR_SDHC_PROCTL_CDSS  (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_CDSS.
+#define BF_SDHC_PROCTL_CDSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDSS), uint32_t) & BM_SDHC_PROCTL_CDSS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CDSS field to a new value.
+#define BW_SDHC_PROCTL_CDSS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 00 - No DMA or simple DMA is selected.
+ * - 01 - ADMA1 is selected.
+ * - 10 - ADMA2 is selected.
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SDHC_PROCTL_DMAS  (8U)          //!< Bit position for SDHC_PROCTL_DMAS.
+#define BM_SDHC_PROCTL_DMAS  (0x00000300U) //!< Bit mask for SDHC_PROCTL_DMAS.
+#define BS_SDHC_PROCTL_DMAS  (2U)          //!< Bit field size in bits for SDHC_PROCTL_DMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_DMAS field.
+#define BR_SDHC_PROCTL_DMAS  (HW_SDHC_PROCTL.B.DMAS)
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_DMAS.
+#define BF_SDHC_PROCTL_DMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DMAS), uint32_t) & BM_SDHC_PROCTL_DMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAS field to a new value.
+#define BW_SDHC_PROCTL_DMAS(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0 - Transfer
+ * - 1 - Stop
+ */
+//@{
+#define BP_SDHC_PROCTL_SABGREQ (16U)       //!< Bit position for SDHC_PROCTL_SABGREQ.
+#define BM_SDHC_PROCTL_SABGREQ (0x00010000U) //!< Bit mask for SDHC_PROCTL_SABGREQ.
+#define BS_SDHC_PROCTL_SABGREQ (1U)        //!< Bit field size in bits for SDHC_PROCTL_SABGREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_SABGREQ field.
+#define BR_SDHC_PROCTL_SABGREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_SABGREQ.
+#define BF_SDHC_PROCTL_SABGREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_SABGREQ), uint32_t) & BM_SDHC_PROCTL_SABGREQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SABGREQ field to a new value.
+#define BW_SDHC_PROCTL_SABGREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Restart
+ */
+//@{
+#define BP_SDHC_PROCTL_CREQ  (17U)         //!< Bit position for SDHC_PROCTL_CREQ.
+#define BM_SDHC_PROCTL_CREQ  (0x00020000U) //!< Bit mask for SDHC_PROCTL_CREQ.
+#define BS_SDHC_PROCTL_CREQ  (1U)          //!< Bit field size in bits for SDHC_PROCTL_CREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_CREQ field.
+#define BR_SDHC_PROCTL_CREQ  (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_CREQ.
+#define BF_SDHC_PROCTL_CREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CREQ), uint32_t) & BM_SDHC_PROCTL_CREQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CREQ field to a new value.
+#define BW_SDHC_PROCTL_CREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
+ *     is set.
+ * - 1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+//@{
+#define BP_SDHC_PROCTL_RWCTL (18U)         //!< Bit position for SDHC_PROCTL_RWCTL.
+#define BM_SDHC_PROCTL_RWCTL (0x00040000U) //!< Bit mask for SDHC_PROCTL_RWCTL.
+#define BS_SDHC_PROCTL_RWCTL (1U)          //!< Bit field size in bits for SDHC_PROCTL_RWCTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_RWCTL field.
+#define BR_SDHC_PROCTL_RWCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_RWCTL.
+#define BF_SDHC_PROCTL_RWCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_RWCTL), uint32_t) & BM_SDHC_PROCTL_RWCTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWCTL field to a new value.
+#define BW_SDHC_PROCTL_RWCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_IABG  (19U)         //!< Bit position for SDHC_PROCTL_IABG.
+#define BM_SDHC_PROCTL_IABG  (0x00080000U) //!< Bit mask for SDHC_PROCTL_IABG.
+#define BS_SDHC_PROCTL_IABG  (1U)          //!< Bit field size in bits for SDHC_PROCTL_IABG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_IABG field.
+#define BR_SDHC_PROCTL_IABG  (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_IABG.
+#define BF_SDHC_PROCTL_IABG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_IABG), uint32_t) & BM_SDHC_PROCTL_IABG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IABG field to a new value.
+#define BW_SDHC_PROCTL_IABG(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_WECINT (24U)        //!< Bit position for SDHC_PROCTL_WECINT.
+#define BM_SDHC_PROCTL_WECINT (0x01000000U) //!< Bit mask for SDHC_PROCTL_WECINT.
+#define BS_SDHC_PROCTL_WECINT (1U)         //!< Bit field size in bits for SDHC_PROCTL_WECINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_WECINT field.
+#define BR_SDHC_PROCTL_WECINT (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_WECINT.
+#define BF_SDHC_PROCTL_WECINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINT), uint32_t) & BM_SDHC_PROCTL_WECINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WECINT field to a new value.
+#define BW_SDHC_PROCTL_WECINT(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_WECINS (25U)        //!< Bit position for SDHC_PROCTL_WECINS.
+#define BM_SDHC_PROCTL_WECINS (0x02000000U) //!< Bit mask for SDHC_PROCTL_WECINS.
+#define BS_SDHC_PROCTL_WECINS (1U)         //!< Bit field size in bits for SDHC_PROCTL_WECINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_WECINS field.
+#define BR_SDHC_PROCTL_WECINS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_WECINS.
+#define BF_SDHC_PROCTL_WECINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINS), uint32_t) & BM_SDHC_PROCTL_WECINS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WECINS field to a new value.
+#define BW_SDHC_PROCTL_WECINS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_WECRM (26U)         //!< Bit position for SDHC_PROCTL_WECRM.
+#define BM_SDHC_PROCTL_WECRM (0x04000000U) //!< Bit mask for SDHC_PROCTL_WECRM.
+#define BS_SDHC_PROCTL_WECRM (1U)          //!< Bit field size in bits for SDHC_PROCTL_WECRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_WECRM field.
+#define BR_SDHC_PROCTL_WECRM (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_WECRM.
+#define BF_SDHC_PROCTL_WECRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECRM), uint32_t) & BM_SDHC_PROCTL_WECRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WECRM field to a new value.
+#define BW_SDHC_PROCTL_WECRM(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_SYSCTL - System Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+typedef union _hw_sdhc_sysctl
+{
+    uint32_t U;
+    struct _hw_sdhc_sysctl_bitfields
+    {
+        uint32_t IPGEN : 1;            //!< [0] IPG Clock Enable
+        uint32_t HCKEN : 1;            //!< [1] System Clock Enable
+        uint32_t PEREN : 1;            //!< [2] Peripheral Clock Enable
+        uint32_t SDCLKEN : 1;          //!< [3] SD Clock Enable
+        uint32_t DVS : 4;              //!< [7:4] Divisor
+        uint32_t SDCLKFS : 8;          //!< [15:8] SDCLK Frequency Select
+        uint32_t DTOCV : 4;            //!< [19:16] Data Timeout Counter Value
+        uint32_t RESERVED0 : 4;        //!< [23:20]
+        uint32_t RSTA : 1;             //!< [24] Software Reset For ALL
+        uint32_t RSTC : 1;             //!< [25] Software Reset For CMD Line
+        uint32_t RSTD : 1;             //!< [26] Software Reset For DAT Line
+        uint32_t INITA : 1;            //!< [27] Initialization Active
+        uint32_t RESERVED1 : 4;        //!< [31:28]
+    } B;
+} hw_sdhc_sysctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+//@{
+#define HW_SDHC_SYSCTL_ADDR      (REGS_SDHC_BASE + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_SYSCTL           (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR)
+#define HW_SDHC_SYSCTL_RD()      (HW_SDHC_SYSCTL.U)
+#define HW_SDHC_SYSCTL_WR(v)     (HW_SDHC_SYSCTL.U = (v))
+#define HW_SDHC_SYSCTL_SET(v)    (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() |  (v)))
+#define HW_SDHC_SYSCTL_CLR(v)    (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() & ~(v)))
+#define HW_SDHC_SYSCTL_TOG(v)    (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0 - Bus clock will be internally gated off.
+ * - 1 - Bus clock will not be automatically gated off.
+ */
+//@{
+#define BP_SDHC_SYSCTL_IPGEN (0U)          //!< Bit position for SDHC_SYSCTL_IPGEN.
+#define BM_SDHC_SYSCTL_IPGEN (0x00000001U) //!< Bit mask for SDHC_SYSCTL_IPGEN.
+#define BS_SDHC_SYSCTL_IPGEN (1U)          //!< Bit field size in bits for SDHC_SYSCTL_IPGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_IPGEN field.
+#define BR_SDHC_SYSCTL_IPGEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_IPGEN.
+#define BF_SDHC_SYSCTL_IPGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_IPGEN), uint32_t) & BM_SDHC_SYSCTL_IPGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPGEN field to a new value.
+#define BW_SDHC_SYSCTL_IPGEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0 - System clock will be internally gated off.
+ * - 1 - System clock will not be automatically gated off.
+ */
+//@{
+#define BP_SDHC_SYSCTL_HCKEN (1U)          //!< Bit position for SDHC_SYSCTL_HCKEN.
+#define BM_SDHC_SYSCTL_HCKEN (0x00000002U) //!< Bit mask for SDHC_SYSCTL_HCKEN.
+#define BS_SDHC_SYSCTL_HCKEN (1U)          //!< Bit field size in bits for SDHC_SYSCTL_HCKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_HCKEN field.
+#define BR_SDHC_SYSCTL_HCKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_HCKEN.
+#define BF_SDHC_SYSCTL_HCKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_HCKEN), uint32_t) & BM_SDHC_SYSCTL_HCKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HCKEN field to a new value.
+#define BW_SDHC_SYSCTL_HCKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0 - SDHC clock will be internally gated off.
+ * - 1 - SDHC clock will not be automatically gated off.
+ */
+//@{
+#define BP_SDHC_SYSCTL_PEREN (2U)          //!< Bit position for SDHC_SYSCTL_PEREN.
+#define BM_SDHC_SYSCTL_PEREN (0x00000004U) //!< Bit mask for SDHC_SYSCTL_PEREN.
+#define BS_SDHC_SYSCTL_PEREN (1U)          //!< Bit field size in bits for SDHC_SYSCTL_PEREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_PEREN field.
+#define BR_SDHC_SYSCTL_PEREN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_PEREN.
+#define BF_SDHC_SYSCTL_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_PEREN), uint32_t) & BM_SDHC_SYSCTL_PEREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PEREN field to a new value.
+#define BW_SDHC_SYSCTL_PEREN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+//@{
+#define BP_SDHC_SYSCTL_SDCLKEN (3U)        //!< Bit position for SDHC_SYSCTL_SDCLKEN.
+#define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) //!< Bit mask for SDHC_SYSCTL_SDCLKEN.
+#define BS_SDHC_SYSCTL_SDCLKEN (1U)        //!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field.
+#define BR_SDHC_SYSCTL_SDCLKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN.
+#define BF_SDHC_SYSCTL_SDCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKEN), uint32_t) & BM_SDHC_SYSCTL_SDCLKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDCLKEN field to a new value.
+#define BW_SDHC_SYSCTL_SDCLKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0 - Divisor by 1.
+ * - 1 - Divisor by 2.
+ * - 1110 - Divisor by 15.
+ * - 1111 - Divisor by 16.
+ */
+//@{
+#define BP_SDHC_SYSCTL_DVS   (4U)          //!< Bit position for SDHC_SYSCTL_DVS.
+#define BM_SDHC_SYSCTL_DVS   (0x000000F0U) //!< Bit mask for SDHC_SYSCTL_DVS.
+#define BS_SDHC_SYSCTL_DVS   (4U)          //!< Bit field size in bits for SDHC_SYSCTL_DVS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_DVS field.
+#define BR_SDHC_SYSCTL_DVS   (HW_SDHC_SYSCTL.B.DVS)
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_DVS.
+#define BF_SDHC_SYSCTL_DVS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DVS), uint32_t) & BM_SDHC_SYSCTL_DVS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DVS field to a new value.
+#define BW_SDHC_SYSCTL_DVS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 1 - Base clock divided by 2.
+ * - 10 - Base clock divided by 4.
+ * - 100 - Base clock divided by 8.
+ * - 1000 - Base clock divided by 16.
+ * - 10000 - Base clock divided by 32.
+ * - 100000 - Base clock divided by 64.
+ * - 1000000 - Base clock divided by 128.
+ * - 10000000 - Base clock divided by 256.
+ */
+//@{
+#define BP_SDHC_SYSCTL_SDCLKFS (8U)        //!< Bit position for SDHC_SYSCTL_SDCLKFS.
+#define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) //!< Bit mask for SDHC_SYSCTL_SDCLKFS.
+#define BS_SDHC_SYSCTL_SDCLKFS (8U)        //!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field.
+#define BR_SDHC_SYSCTL_SDCLKFS (HW_SDHC_SYSCTL.B.SDCLKFS)
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS.
+#define BF_SDHC_SYSCTL_SDCLKFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKFS), uint32_t) & BM_SDHC_SYSCTL_SDCLKFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDCLKFS field to a new value.
+#define BW_SDHC_SYSCTL_SDCLKFS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0000 - SDCLK x 2 13
+ * - 0001 - SDCLK x 2 14
+ * - 1110 - SDCLK x 2 27
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SDHC_SYSCTL_DTOCV (16U)         //!< Bit position for SDHC_SYSCTL_DTOCV.
+#define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) //!< Bit mask for SDHC_SYSCTL_DTOCV.
+#define BS_SDHC_SYSCTL_DTOCV (4U)          //!< Bit field size in bits for SDHC_SYSCTL_DTOCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_DTOCV field.
+#define BR_SDHC_SYSCTL_DTOCV (HW_SDHC_SYSCTL.B.DTOCV)
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_DTOCV.
+#define BF_SDHC_SYSCTL_DTOCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DTOCV), uint32_t) & BM_SDHC_SYSCTL_DTOCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOCV field to a new value.
+#define BW_SDHC_SYSCTL_DTOCV(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0 - No reset.
+ * - 1 - Reset.
+ */
+//@{
+#define BP_SDHC_SYSCTL_RSTA  (24U)         //!< Bit position for SDHC_SYSCTL_RSTA.
+#define BM_SDHC_SYSCTL_RSTA  (0x01000000U) //!< Bit mask for SDHC_SYSCTL_RSTA.
+#define BS_SDHC_SYSCTL_RSTA  (1U)          //!< Bit field size in bits for SDHC_SYSCTL_RSTA.
+
+//! @brief Format value for bitfield SDHC_SYSCTL_RSTA.
+#define BF_SDHC_SYSCTL_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTA), uint32_t) & BM_SDHC_SYSCTL_RSTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTA field to a new value.
+#define BW_SDHC_SYSCTL_RSTA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0 - No reset.
+ * - 1 - Reset.
+ */
+//@{
+#define BP_SDHC_SYSCTL_RSTC  (25U)         //!< Bit position for SDHC_SYSCTL_RSTC.
+#define BM_SDHC_SYSCTL_RSTC  (0x02000000U) //!< Bit mask for SDHC_SYSCTL_RSTC.
+#define BS_SDHC_SYSCTL_RSTC  (1U)          //!< Bit field size in bits for SDHC_SYSCTL_RSTC.
+
+//! @brief Format value for bitfield SDHC_SYSCTL_RSTC.
+#define BF_SDHC_SYSCTL_RSTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTC), uint32_t) & BM_SDHC_SYSCTL_RSTC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTC field to a new value.
+#define BW_SDHC_SYSCTL_RSTC(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0 - No reset.
+ * - 1 - Reset.
+ */
+//@{
+#define BP_SDHC_SYSCTL_RSTD  (26U)         //!< Bit position for SDHC_SYSCTL_RSTD.
+#define BM_SDHC_SYSCTL_RSTD  (0x04000000U) //!< Bit mask for SDHC_SYSCTL_RSTD.
+#define BS_SDHC_SYSCTL_RSTD  (1U)          //!< Bit field size in bits for SDHC_SYSCTL_RSTD.
+
+//! @brief Format value for bitfield SDHC_SYSCTL_RSTD.
+#define BF_SDHC_SYSCTL_RSTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTD), uint32_t) & BM_SDHC_SYSCTL_RSTD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTD field to a new value.
+#define BW_SDHC_SYSCTL_RSTD(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+//@{
+#define BP_SDHC_SYSCTL_INITA (27U)         //!< Bit position for SDHC_SYSCTL_INITA.
+#define BM_SDHC_SYSCTL_INITA (0x08000000U) //!< Bit mask for SDHC_SYSCTL_INITA.
+#define BS_SDHC_SYSCTL_INITA (1U)          //!< Bit field size in bits for SDHC_SYSCTL_INITA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_INITA field.
+#define BR_SDHC_SYSCTL_INITA (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_INITA.
+#define BF_SDHC_SYSCTL_INITA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_INITA), uint32_t) & BM_SDHC_SYSCTL_INITA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITA field to a new value.
+#define BW_SDHC_SYSCTL_INITA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_IRQSTAT - Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+typedef union _hw_sdhc_irqstat
+{
+    uint32_t U;
+    struct _hw_sdhc_irqstat_bitfields
+    {
+        uint32_t CC : 1;               //!< [0] Command Complete
+        uint32_t TC : 1;               //!< [1] Transfer Complete
+        uint32_t BGE : 1;              //!< [2] Block Gap Event
+        uint32_t DINT : 1;             //!< [3] DMA Interrupt
+        uint32_t BWR : 1;              //!< [4] Buffer Write Ready
+        uint32_t BRR : 1;              //!< [5] Buffer Read Ready
+        uint32_t CINS : 1;             //!< [6] Card Insertion
+        uint32_t CRM : 1;              //!< [7] Card Removal
+        uint32_t CINT : 1;             //!< [8] Card Interrupt
+        uint32_t RESERVED0 : 7;        //!< [15:9]
+        uint32_t CTOE : 1;             //!< [16] Command Timeout Error
+        uint32_t CCE : 1;              //!< [17] Command CRC Error
+        uint32_t CEBE : 1;             //!< [18] Command End Bit Error
+        uint32_t CIE : 1;              //!< [19] Command Index Error
+        uint32_t DTOE : 1;             //!< [20] Data Timeout Error
+        uint32_t DCE : 1;              //!< [21] Data CRC Error
+        uint32_t DEBE : 1;             //!< [22] Data End Bit Error
+        uint32_t RESERVED1 : 1;        //!< [23]
+        uint32_t AC12E : 1;            //!< [24] Auto CMD12 Error
+        uint32_t RESERVED2 : 3;        //!< [27:25]
+        uint32_t DMAE : 1;             //!< [28] DMA Error
+        uint32_t RESERVED3 : 3;        //!< [31:29]
+    } B;
+} hw_sdhc_irqstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+//@{
+#define HW_SDHC_IRQSTAT_ADDR     (REGS_SDHC_BASE + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_IRQSTAT          (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR)
+#define HW_SDHC_IRQSTAT_RD()     (HW_SDHC_IRQSTAT.U)
+#define HW_SDHC_IRQSTAT_WR(v)    (HW_SDHC_IRQSTAT.U = (v))
+#define HW_SDHC_IRQSTAT_SET(v)   (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() |  (v)))
+#define HW_SDHC_IRQSTAT_CLR(v)   (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() & ~(v)))
+#define HW_SDHC_IRQSTAT_TOG(v)   (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0 - Command not complete.
+ * - 1 - Command complete.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CC   (0U)          //!< Bit position for SDHC_IRQSTAT_CC.
+#define BM_SDHC_IRQSTAT_CC   (0x00000001U) //!< Bit mask for SDHC_IRQSTAT_CC.
+#define BS_SDHC_IRQSTAT_CC   (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CC field.
+#define BR_SDHC_IRQSTAT_CC   (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CC.
+#define BF_SDHC_IRQSTAT_CC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CC), uint32_t) & BM_SDHC_IRQSTAT_CC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CC field to a new value.
+#define BW_SDHC_IRQSTAT_CC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0 - Transfer not complete.
+ * - 1 - Transfer complete.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_TC   (1U)          //!< Bit position for SDHC_IRQSTAT_TC.
+#define BM_SDHC_IRQSTAT_TC   (0x00000002U) //!< Bit mask for SDHC_IRQSTAT_TC.
+#define BS_SDHC_IRQSTAT_TC   (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_TC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_TC field.
+#define BR_SDHC_IRQSTAT_TC   (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_TC.
+#define BF_SDHC_IRQSTAT_TC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_TC), uint32_t) & BM_SDHC_IRQSTAT_TC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TC field to a new value.
+#define BW_SDHC_IRQSTAT_TC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0 - No block gap event.
+ * - 1 - Transaction stopped at block gap.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_BGE  (2U)          //!< Bit position for SDHC_IRQSTAT_BGE.
+#define BM_SDHC_IRQSTAT_BGE  (0x00000004U) //!< Bit mask for SDHC_IRQSTAT_BGE.
+#define BS_SDHC_IRQSTAT_BGE  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_BGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_BGE field.
+#define BR_SDHC_IRQSTAT_BGE  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_BGE.
+#define BF_SDHC_IRQSTAT_BGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BGE), uint32_t) & BM_SDHC_IRQSTAT_BGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGE field to a new value.
+#define BW_SDHC_IRQSTAT_BGE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0 - No DMA Interrupt.
+ * - 1 - DMA Interrupt is generated.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DINT (3U)          //!< Bit position for SDHC_IRQSTAT_DINT.
+#define BM_SDHC_IRQSTAT_DINT (0x00000008U) //!< Bit mask for SDHC_IRQSTAT_DINT.
+#define BS_SDHC_IRQSTAT_DINT (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_DINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DINT field.
+#define BR_SDHC_IRQSTAT_DINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DINT.
+#define BF_SDHC_IRQSTAT_DINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DINT), uint32_t) & BM_SDHC_IRQSTAT_DINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DINT field to a new value.
+#define BW_SDHC_IRQSTAT_DINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0 - Not ready to write buffer.
+ * - 1 - Ready to write buffer.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_BWR  (4U)          //!< Bit position for SDHC_IRQSTAT_BWR.
+#define BM_SDHC_IRQSTAT_BWR  (0x00000010U) //!< Bit mask for SDHC_IRQSTAT_BWR.
+#define BS_SDHC_IRQSTAT_BWR  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_BWR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_BWR field.
+#define BR_SDHC_IRQSTAT_BWR  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_BWR.
+#define BF_SDHC_IRQSTAT_BWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BWR), uint32_t) & BM_SDHC_IRQSTAT_BWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWR field to a new value.
+#define BW_SDHC_IRQSTAT_BWR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0 - Not ready to read buffer.
+ * - 1 - Ready to read buffer.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_BRR  (5U)          //!< Bit position for SDHC_IRQSTAT_BRR.
+#define BM_SDHC_IRQSTAT_BRR  (0x00000020U) //!< Bit mask for SDHC_IRQSTAT_BRR.
+#define BS_SDHC_IRQSTAT_BRR  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_BRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_BRR field.
+#define BR_SDHC_IRQSTAT_BRR  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_BRR.
+#define BF_SDHC_IRQSTAT_BRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BRR), uint32_t) & BM_SDHC_IRQSTAT_BRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRR field to a new value.
+#define BW_SDHC_IRQSTAT_BRR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0 - Card state unstable or removed.
+ * - 1 - Card inserted.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CINS (6U)          //!< Bit position for SDHC_IRQSTAT_CINS.
+#define BM_SDHC_IRQSTAT_CINS (0x00000040U) //!< Bit mask for SDHC_IRQSTAT_CINS.
+#define BS_SDHC_IRQSTAT_CINS (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CINS field.
+#define BR_SDHC_IRQSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CINS.
+#define BF_SDHC_IRQSTAT_CINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINS), uint32_t) & BM_SDHC_IRQSTAT_CINS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINS field to a new value.
+#define BW_SDHC_IRQSTAT_CINS(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0 - Card state unstable or inserted.
+ * - 1 - Card removed.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CRM  (7U)          //!< Bit position for SDHC_IRQSTAT_CRM.
+#define BM_SDHC_IRQSTAT_CRM  (0x00000080U) //!< Bit mask for SDHC_IRQSTAT_CRM.
+#define BS_SDHC_IRQSTAT_CRM  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CRM field.
+#define BR_SDHC_IRQSTAT_CRM  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CRM.
+#define BF_SDHC_IRQSTAT_CRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CRM), uint32_t) & BM_SDHC_IRQSTAT_CRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRM field to a new value.
+#define BW_SDHC_IRQSTAT_CRM(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0 - No Card Interrupt.
+ * - 1 - Generate Card Interrupt.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CINT (8U)          //!< Bit position for SDHC_IRQSTAT_CINT.
+#define BM_SDHC_IRQSTAT_CINT (0x00000100U) //!< Bit mask for SDHC_IRQSTAT_CINT.
+#define BS_SDHC_IRQSTAT_CINT (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CINT field.
+#define BR_SDHC_IRQSTAT_CINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CINT.
+#define BF_SDHC_IRQSTAT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINT), uint32_t) & BM_SDHC_IRQSTAT_CINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINT field to a new value.
+#define BW_SDHC_IRQSTAT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Time out.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CTOE (16U)         //!< Bit position for SDHC_IRQSTAT_CTOE.
+#define BM_SDHC_IRQSTAT_CTOE (0x00010000U) //!< Bit mask for SDHC_IRQSTAT_CTOE.
+#define BS_SDHC_IRQSTAT_CTOE (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CTOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CTOE field.
+#define BR_SDHC_IRQSTAT_CTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CTOE.
+#define BF_SDHC_IRQSTAT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CTOE), uint32_t) & BM_SDHC_IRQSTAT_CTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOE field to a new value.
+#define BW_SDHC_IRQSTAT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - CRC Error generated.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CCE  (17U)         //!< Bit position for SDHC_IRQSTAT_CCE.
+#define BM_SDHC_IRQSTAT_CCE  (0x00020000U) //!< Bit mask for SDHC_IRQSTAT_CCE.
+#define BS_SDHC_IRQSTAT_CCE  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CCE field.
+#define BR_SDHC_IRQSTAT_CCE  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CCE.
+#define BF_SDHC_IRQSTAT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CCE), uint32_t) & BM_SDHC_IRQSTAT_CCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCE field to a new value.
+#define BW_SDHC_IRQSTAT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - End Bit Error generated.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CEBE (18U)         //!< Bit position for SDHC_IRQSTAT_CEBE.
+#define BM_SDHC_IRQSTAT_CEBE (0x00040000U) //!< Bit mask for SDHC_IRQSTAT_CEBE.
+#define BS_SDHC_IRQSTAT_CEBE (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CEBE field.
+#define BR_SDHC_IRQSTAT_CEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CEBE.
+#define BF_SDHC_IRQSTAT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CEBE), uint32_t) & BM_SDHC_IRQSTAT_CEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBE field to a new value.
+#define BW_SDHC_IRQSTAT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CIE  (19U)         //!< Bit position for SDHC_IRQSTAT_CIE.
+#define BM_SDHC_IRQSTAT_CIE  (0x00080000U) //!< Bit mask for SDHC_IRQSTAT_CIE.
+#define BS_SDHC_IRQSTAT_CIE  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_CIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CIE field.
+#define BR_SDHC_IRQSTAT_CIE  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CIE.
+#define BF_SDHC_IRQSTAT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CIE), uint32_t) & BM_SDHC_IRQSTAT_CIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIE field to a new value.
+#define BW_SDHC_IRQSTAT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Time out.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DTOE (20U)         //!< Bit position for SDHC_IRQSTAT_DTOE.
+#define BM_SDHC_IRQSTAT_DTOE (0x00100000U) //!< Bit mask for SDHC_IRQSTAT_DTOE.
+#define BS_SDHC_IRQSTAT_DTOE (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_DTOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DTOE field.
+#define BR_SDHC_IRQSTAT_DTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DTOE.
+#define BF_SDHC_IRQSTAT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DTOE), uint32_t) & BM_SDHC_IRQSTAT_DTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOE field to a new value.
+#define BW_SDHC_IRQSTAT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DCE  (21U)         //!< Bit position for SDHC_IRQSTAT_DCE.
+#define BM_SDHC_IRQSTAT_DCE  (0x00200000U) //!< Bit mask for SDHC_IRQSTAT_DCE.
+#define BS_SDHC_IRQSTAT_DCE  (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_DCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DCE field.
+#define BR_SDHC_IRQSTAT_DCE  (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DCE.
+#define BF_SDHC_IRQSTAT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DCE), uint32_t) & BM_SDHC_IRQSTAT_DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCE field to a new value.
+#define BW_SDHC_IRQSTAT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DEBE (22U)         //!< Bit position for SDHC_IRQSTAT_DEBE.
+#define BM_SDHC_IRQSTAT_DEBE (0x00400000U) //!< Bit mask for SDHC_IRQSTAT_DEBE.
+#define BS_SDHC_IRQSTAT_DEBE (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_DEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DEBE field.
+#define BR_SDHC_IRQSTAT_DEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DEBE.
+#define BF_SDHC_IRQSTAT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DEBE), uint32_t) & BM_SDHC_IRQSTAT_DEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBE field to a new value.
+#define BW_SDHC_IRQSTAT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_AC12E (24U)        //!< Bit position for SDHC_IRQSTAT_AC12E.
+#define BM_SDHC_IRQSTAT_AC12E (0x01000000U) //!< Bit mask for SDHC_IRQSTAT_AC12E.
+#define BS_SDHC_IRQSTAT_AC12E (1U)         //!< Bit field size in bits for SDHC_IRQSTAT_AC12E.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_AC12E field.
+#define BR_SDHC_IRQSTAT_AC12E (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_AC12E.
+#define BF_SDHC_IRQSTAT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_AC12E), uint32_t) & BM_SDHC_IRQSTAT_AC12E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12E field to a new value.
+#define BW_SDHC_IRQSTAT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DMAE (28U)         //!< Bit position for SDHC_IRQSTAT_DMAE.
+#define BM_SDHC_IRQSTAT_DMAE (0x10000000U) //!< Bit mask for SDHC_IRQSTAT_DMAE.
+#define BS_SDHC_IRQSTAT_DMAE (1U)          //!< Bit field size in bits for SDHC_IRQSTAT_DMAE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DMAE field.
+#define BR_SDHC_IRQSTAT_DMAE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DMAE.
+#define BF_SDHC_IRQSTAT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DMAE), uint32_t) & BM_SDHC_IRQSTAT_DMAE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAE field to a new value.
+#define BW_SDHC_IRQSTAT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_IRQSTATEN - Interrupt Status Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+typedef union _hw_sdhc_irqstaten
+{
+    uint32_t U;
+    struct _hw_sdhc_irqstaten_bitfields
+    {
+        uint32_t CCSEN : 1;            //!< [0] Command Complete Status Enable
+        uint32_t TCSEN : 1;            //!< [1] Transfer Complete Status Enable
+        uint32_t BGESEN : 1;           //!< [2] Block Gap Event Status Enable
+        uint32_t DINTSEN : 1;          //!< [3] DMA Interrupt Status Enable
+        uint32_t BWRSEN : 1;           //!< [4] Buffer Write Ready Status Enable
+        uint32_t BRRSEN : 1;           //!< [5] Buffer Read Ready Status Enable
+        uint32_t CINSEN : 1;           //!< [6] Card Insertion Status Enable
+        uint32_t CRMSEN : 1;           //!< [7] Card Removal Status Enable
+        uint32_t CINTSEN : 1;          //!< [8] Card Interrupt Status Enable
+        uint32_t RESERVED0 : 7;        //!< [15:9]
+        uint32_t CTOESEN : 1;          //!< [16] Command Timeout Error Status Enable
+        uint32_t CCESEN : 1;           //!< [17] Command CRC Error Status Enable
+        uint32_t CEBESEN : 1;          //!< [18] Command End Bit Error Status Enable
+        uint32_t CIESEN : 1;           //!< [19] Command Index Error Status Enable
+        uint32_t DTOESEN : 1;          //!< [20] Data Timeout Error Status Enable
+        uint32_t DCESEN : 1;           //!< [21] Data CRC Error Status Enable
+        uint32_t DEBESEN : 1;          //!< [22] Data End Bit Error Status Enable
+        uint32_t RESERVED1 : 1;        //!< [23]
+        uint32_t AC12ESEN : 1;         //!< [24] Auto CMD12 Error Status Enable
+        uint32_t RESERVED2 : 3;        //!< [27:25]
+        uint32_t DMAESEN : 1;          //!< [28] DMA Error Status Enable
+        uint32_t RESERVED3 : 3;        //!< [31:29]
+    } B;
+} hw_sdhc_irqstaten_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+//@{
+#define HW_SDHC_IRQSTATEN_ADDR   (REGS_SDHC_BASE + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_IRQSTATEN        (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR)
+#define HW_SDHC_IRQSTATEN_RD()   (HW_SDHC_IRQSTATEN.U)
+#define HW_SDHC_IRQSTATEN_WR(v)  (HW_SDHC_IRQSTATEN.U = (v))
+#define HW_SDHC_IRQSTATEN_SET(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() |  (v)))
+#define HW_SDHC_IRQSTATEN_CLR(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() & ~(v)))
+#define HW_SDHC_IRQSTATEN_TOG(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CCSEN (0U)       //!< Bit position for SDHC_IRQSTATEN_CCSEN.
+#define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) //!< Bit mask for SDHC_IRQSTATEN_CCSEN.
+#define BS_SDHC_IRQSTATEN_CCSEN (1U)       //!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field.
+#define BR_SDHC_IRQSTATEN_CCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN.
+#define BF_SDHC_IRQSTATEN_CCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCSEN), uint32_t) & BM_SDHC_IRQSTATEN_CCSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_TCSEN (1U)       //!< Bit position for SDHC_IRQSTATEN_TCSEN.
+#define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) //!< Bit mask for SDHC_IRQSTATEN_TCSEN.
+#define BS_SDHC_IRQSTATEN_TCSEN (1U)       //!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field.
+#define BR_SDHC_IRQSTATEN_TCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN.
+#define BF_SDHC_IRQSTATEN_TCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_TCSEN), uint32_t) & BM_SDHC_IRQSTATEN_TCSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_TCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_BGESEN (2U)      //!< Bit position for SDHC_IRQSTATEN_BGESEN.
+#define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) //!< Bit mask for SDHC_IRQSTATEN_BGESEN.
+#define BS_SDHC_IRQSTATEN_BGESEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field.
+#define BR_SDHC_IRQSTATEN_BGESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN.
+#define BF_SDHC_IRQSTATEN_BGESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BGESEN), uint32_t) & BM_SDHC_IRQSTATEN_BGESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_BGESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DINTSEN (3U)     //!< Bit position for SDHC_IRQSTATEN_DINTSEN.
+#define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) //!< Bit mask for SDHC_IRQSTATEN_DINTSEN.
+#define BS_SDHC_IRQSTATEN_DINTSEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field.
+#define BR_SDHC_IRQSTATEN_DINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN.
+#define BF_SDHC_IRQSTATEN_DINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_DINTSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DINTSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_BWRSEN (4U)      //!< Bit position for SDHC_IRQSTATEN_BWRSEN.
+#define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) //!< Bit mask for SDHC_IRQSTATEN_BWRSEN.
+#define BS_SDHC_IRQSTATEN_BWRSEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field.
+#define BR_SDHC_IRQSTATEN_BWRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN.
+#define BF_SDHC_IRQSTATEN_BWRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BWRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BWRSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWRSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_BWRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_BRRSEN (5U)      //!< Bit position for SDHC_IRQSTATEN_BRRSEN.
+#define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) //!< Bit mask for SDHC_IRQSTATEN_BRRSEN.
+#define BS_SDHC_IRQSTATEN_BRRSEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field.
+#define BR_SDHC_IRQSTATEN_BRRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN.
+#define BF_SDHC_IRQSTATEN_BRRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BRRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BRRSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRRSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_BRRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CINSEN (6U)      //!< Bit position for SDHC_IRQSTATEN_CINSEN.
+#define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) //!< Bit mask for SDHC_IRQSTATEN_CINSEN.
+#define BS_SDHC_IRQSTATEN_CINSEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field.
+#define BR_SDHC_IRQSTATEN_CINSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN.
+#define BF_SDHC_IRQSTATEN_CINSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CINSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CRMSEN (7U)      //!< Bit position for SDHC_IRQSTATEN_CRMSEN.
+#define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) //!< Bit mask for SDHC_IRQSTATEN_CRMSEN.
+#define BS_SDHC_IRQSTATEN_CRMSEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field.
+#define BR_SDHC_IRQSTATEN_CRMSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN.
+#define BF_SDHC_IRQSTATEN_CRMSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CRMSEN), uint32_t) & BM_SDHC_IRQSTATEN_CRMSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRMSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CRMSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CINTSEN (8U)     //!< Bit position for SDHC_IRQSTATEN_CINTSEN.
+#define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) //!< Bit mask for SDHC_IRQSTATEN_CINTSEN.
+#define BS_SDHC_IRQSTATEN_CINTSEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field.
+#define BR_SDHC_IRQSTATEN_CINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN.
+#define BF_SDHC_IRQSTATEN_CINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINTSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINTSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CTOESEN (16U)    //!< Bit position for SDHC_IRQSTATEN_CTOESEN.
+#define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) //!< Bit mask for SDHC_IRQSTATEN_CTOESEN.
+#define BS_SDHC_IRQSTATEN_CTOESEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field.
+#define BR_SDHC_IRQSTATEN_CTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN.
+#define BF_SDHC_IRQSTATEN_CTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_CTOESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CCESEN (17U)     //!< Bit position for SDHC_IRQSTATEN_CCESEN.
+#define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) //!< Bit mask for SDHC_IRQSTATEN_CCESEN.
+#define BS_SDHC_IRQSTATEN_CCESEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field.
+#define BR_SDHC_IRQSTATEN_CCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN.
+#define BF_SDHC_IRQSTATEN_CCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCESEN), uint32_t) & BM_SDHC_IRQSTATEN_CCESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CEBESEN (18U)    //!< Bit position for SDHC_IRQSTATEN_CEBESEN.
+#define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) //!< Bit mask for SDHC_IRQSTATEN_CEBESEN.
+#define BS_SDHC_IRQSTATEN_CEBESEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field.
+#define BR_SDHC_IRQSTATEN_CEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN.
+#define BF_SDHC_IRQSTATEN_CEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_CEBESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CIESEN (19U)     //!< Bit position for SDHC_IRQSTATEN_CIESEN.
+#define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) //!< Bit mask for SDHC_IRQSTATEN_CIESEN.
+#define BS_SDHC_IRQSTATEN_CIESEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field.
+#define BR_SDHC_IRQSTATEN_CIESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN.
+#define BF_SDHC_IRQSTATEN_CIESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CIESEN), uint32_t) & BM_SDHC_IRQSTATEN_CIESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CIESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DTOESEN (20U)    //!< Bit position for SDHC_IRQSTATEN_DTOESEN.
+#define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) //!< Bit mask for SDHC_IRQSTATEN_DTOESEN.
+#define BS_SDHC_IRQSTATEN_DTOESEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field.
+#define BR_SDHC_IRQSTATEN_DTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN.
+#define BF_SDHC_IRQSTATEN_DTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_DTOESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DCESEN (21U)     //!< Bit position for SDHC_IRQSTATEN_DCESEN.
+#define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) //!< Bit mask for SDHC_IRQSTATEN_DCESEN.
+#define BS_SDHC_IRQSTATEN_DCESEN (1U)      //!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field.
+#define BR_SDHC_IRQSTATEN_DCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN.
+#define BF_SDHC_IRQSTATEN_DCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DCESEN), uint32_t) & BM_SDHC_IRQSTATEN_DCESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DEBESEN (22U)    //!< Bit position for SDHC_IRQSTATEN_DEBESEN.
+#define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) //!< Bit mask for SDHC_IRQSTATEN_DEBESEN.
+#define BS_SDHC_IRQSTATEN_DEBESEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field.
+#define BR_SDHC_IRQSTATEN_DEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN.
+#define BF_SDHC_IRQSTATEN_DEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_DEBESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_AC12ESEN (24U)   //!< Bit position for SDHC_IRQSTATEN_AC12ESEN.
+#define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) //!< Bit mask for SDHC_IRQSTATEN_AC12ESEN.
+#define BS_SDHC_IRQSTATEN_AC12ESEN (1U)    //!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field.
+#define BR_SDHC_IRQSTATEN_AC12ESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN.
+#define BF_SDHC_IRQSTATEN_AC12ESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_AC12ESEN), uint32_t) & BM_SDHC_IRQSTATEN_AC12ESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12ESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_AC12ESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DMAESEN (28U)    //!< Bit position for SDHC_IRQSTATEN_DMAESEN.
+#define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) //!< Bit mask for SDHC_IRQSTATEN_DMAESEN.
+#define BS_SDHC_IRQSTATEN_DMAESEN (1U)     //!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field.
+#define BR_SDHC_IRQSTATEN_DMAESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN.
+#define BF_SDHC_IRQSTATEN_DMAESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DMAESEN), uint32_t) & BM_SDHC_IRQSTATEN_DMAESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DMAESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+typedef union _hw_sdhc_irqsigen
+{
+    uint32_t U;
+    struct _hw_sdhc_irqsigen_bitfields
+    {
+        uint32_t CCIEN : 1;            //!< [0] Command Complete Interrupt Enable
+        uint32_t TCIEN : 1;            //!< [1] Transfer Complete Interrupt Enable
+        uint32_t BGEIEN : 1;           //!< [2] Block Gap Event Interrupt Enable
+        uint32_t DINTIEN : 1;          //!< [3] DMA Interrupt Enable
+        uint32_t BWRIEN : 1;           //!< [4] Buffer Write Ready Interrupt Enable
+        uint32_t BRRIEN : 1;           //!< [5] Buffer Read Ready Interrupt Enable
+        uint32_t CINSIEN : 1;          //!< [6] Card Insertion Interrupt Enable
+        uint32_t CRMIEN : 1;           //!< [7] Card Removal Interrupt Enable
+        uint32_t CINTIEN : 1;          //!< [8] Card Interrupt Enable
+        uint32_t RESERVED0 : 7;        //!< [15:9]
+        uint32_t CTOEIEN : 1;          //!< [16] Command Timeout Error Interrupt Enable
+        uint32_t CCEIEN : 1;           //!< [17] Command CRC Error Interrupt Enable
+        uint32_t CEBEIEN : 1;          //!< [18] Command End Bit Error Interrupt Enable
+        uint32_t CIEIEN : 1;           //!< [19] Command Index Error Interrupt Enable
+        uint32_t DTOEIEN : 1;          //!< [20] Data Timeout Error Interrupt Enable
+        uint32_t DCEIEN : 1;           //!< [21] Data CRC Error Interrupt Enable
+        uint32_t DEBEIEN : 1;          //!< [22] Data End Bit Error Interrupt Enable
+        uint32_t RESERVED1 : 1;        //!< [23]
+        uint32_t AC12EIEN : 1;         //!< [24] Auto CMD12 Error Interrupt Enable
+        uint32_t RESERVED2 : 3;        //!< [27:25]
+        uint32_t DMAEIEN : 1;          //!< [28] DMA Error Interrupt Enable
+        uint32_t RESERVED3 : 3;        //!< [31:29]
+    } B;
+} hw_sdhc_irqsigen_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+//@{
+#define HW_SDHC_IRQSIGEN_ADDR    (REGS_SDHC_BASE + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_IRQSIGEN         (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR)
+#define HW_SDHC_IRQSIGEN_RD()    (HW_SDHC_IRQSIGEN.U)
+#define HW_SDHC_IRQSIGEN_WR(v)   (HW_SDHC_IRQSIGEN.U = (v))
+#define HW_SDHC_IRQSIGEN_SET(v)  (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() |  (v)))
+#define HW_SDHC_IRQSIGEN_CLR(v)  (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() & ~(v)))
+#define HW_SDHC_IRQSIGEN_TOG(v)  (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CCIEN (0U)        //!< Bit position for SDHC_IRQSIGEN_CCIEN.
+#define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) //!< Bit mask for SDHC_IRQSIGEN_CCIEN.
+#define BS_SDHC_IRQSIGEN_CCIEN (1U)        //!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field.
+#define BR_SDHC_IRQSIGEN_CCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN.
+#define BF_SDHC_IRQSIGEN_CCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_TCIEN (1U)        //!< Bit position for SDHC_IRQSIGEN_TCIEN.
+#define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) //!< Bit mask for SDHC_IRQSIGEN_TCIEN.
+#define BS_SDHC_IRQSIGEN_TCIEN (1U)        //!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field.
+#define BR_SDHC_IRQSIGEN_TCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN.
+#define BF_SDHC_IRQSIGEN_TCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_TCIEN), uint32_t) & BM_SDHC_IRQSIGEN_TCIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_TCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_BGEIEN (2U)       //!< Bit position for SDHC_IRQSIGEN_BGEIEN.
+#define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) //!< Bit mask for SDHC_IRQSIGEN_BGEIEN.
+#define BS_SDHC_IRQSIGEN_BGEIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field.
+#define BR_SDHC_IRQSIGEN_BGEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN.
+#define BF_SDHC_IRQSIGEN_BGEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BGEIEN), uint32_t) & BM_SDHC_IRQSIGEN_BGEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_BGEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DINTIEN (3U)      //!< Bit position for SDHC_IRQSIGEN_DINTIEN.
+#define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) //!< Bit mask for SDHC_IRQSIGEN_DINTIEN.
+#define BS_SDHC_IRQSIGEN_DINTIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field.
+#define BR_SDHC_IRQSIGEN_DINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN.
+#define BF_SDHC_IRQSIGEN_DINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_DINTIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DINTIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_BWRIEN (4U)       //!< Bit position for SDHC_IRQSIGEN_BWRIEN.
+#define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) //!< Bit mask for SDHC_IRQSIGEN_BWRIEN.
+#define BS_SDHC_IRQSIGEN_BWRIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field.
+#define BR_SDHC_IRQSIGEN_BWRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN.
+#define BF_SDHC_IRQSIGEN_BWRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BWRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BWRIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWRIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_BWRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_BRRIEN (5U)       //!< Bit position for SDHC_IRQSIGEN_BRRIEN.
+#define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) //!< Bit mask for SDHC_IRQSIGEN_BRRIEN.
+#define BS_SDHC_IRQSIGEN_BRRIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field.
+#define BR_SDHC_IRQSIGEN_BRRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN.
+#define BF_SDHC_IRQSIGEN_BRRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BRRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BRRIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRRIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_BRRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CINSIEN (6U)      //!< Bit position for SDHC_IRQSIGEN_CINSIEN.
+#define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) //!< Bit mask for SDHC_IRQSIGEN_CINSIEN.
+#define BS_SDHC_IRQSIGEN_CINSIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field.
+#define BR_SDHC_IRQSIGEN_CINSIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN.
+#define BF_SDHC_IRQSIGEN_CINSIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINSIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINSIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINSIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CINSIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CRMIEN (7U)       //!< Bit position for SDHC_IRQSIGEN_CRMIEN.
+#define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) //!< Bit mask for SDHC_IRQSIGEN_CRMIEN.
+#define BS_SDHC_IRQSIGEN_CRMIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field.
+#define BR_SDHC_IRQSIGEN_CRMIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN.
+#define BF_SDHC_IRQSIGEN_CRMIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CRMIEN), uint32_t) & BM_SDHC_IRQSIGEN_CRMIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRMIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CRMIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CINTIEN (8U)      //!< Bit position for SDHC_IRQSIGEN_CINTIEN.
+#define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) //!< Bit mask for SDHC_IRQSIGEN_CINTIEN.
+#define BS_SDHC_IRQSIGEN_CINTIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field.
+#define BR_SDHC_IRQSIGEN_CINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN.
+#define BF_SDHC_IRQSIGEN_CINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINTIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINTIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CTOEIEN (16U)     //!< Bit position for SDHC_IRQSIGEN_CTOEIEN.
+#define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) //!< Bit mask for SDHC_IRQSIGEN_CTOEIEN.
+#define BS_SDHC_IRQSIGEN_CTOEIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field.
+#define BR_SDHC_IRQSIGEN_CTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN.
+#define BF_SDHC_IRQSIGEN_CTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CTOEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CCEIEN (17U)      //!< Bit position for SDHC_IRQSIGEN_CCEIEN.
+#define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) //!< Bit mask for SDHC_IRQSIGEN_CCEIEN.
+#define BS_SDHC_IRQSIGEN_CCEIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field.
+#define BR_SDHC_IRQSIGEN_CCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN.
+#define BF_SDHC_IRQSIGEN_CCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CEBEIEN (18U)     //!< Bit position for SDHC_IRQSIGEN_CEBEIEN.
+#define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) //!< Bit mask for SDHC_IRQSIGEN_CEBEIEN.
+#define BS_SDHC_IRQSIGEN_CEBEIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field.
+#define BR_SDHC_IRQSIGEN_CEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN.
+#define BF_SDHC_IRQSIGEN_CEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CEBEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CIEIEN (19U)      //!< Bit position for SDHC_IRQSIGEN_CIEIEN.
+#define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) //!< Bit mask for SDHC_IRQSIGEN_CIEIEN.
+#define BS_SDHC_IRQSIGEN_CIEIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field.
+#define BR_SDHC_IRQSIGEN_CIEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN.
+#define BF_SDHC_IRQSIGEN_CIEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CIEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CIEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CIEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DTOEIEN (20U)     //!< Bit position for SDHC_IRQSIGEN_DTOEIEN.
+#define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) //!< Bit mask for SDHC_IRQSIGEN_DTOEIEN.
+#define BS_SDHC_IRQSIGEN_DTOEIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field.
+#define BR_SDHC_IRQSIGEN_DTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN.
+#define BF_SDHC_IRQSIGEN_DTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DTOEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DCEIEN (21U)      //!< Bit position for SDHC_IRQSIGEN_DCEIEN.
+#define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) //!< Bit mask for SDHC_IRQSIGEN_DCEIEN.
+#define BS_SDHC_IRQSIGEN_DCEIEN (1U)       //!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field.
+#define BR_SDHC_IRQSIGEN_DCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN.
+#define BF_SDHC_IRQSIGEN_DCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DCEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DEBEIEN (22U)     //!< Bit position for SDHC_IRQSIGEN_DEBEIEN.
+#define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) //!< Bit mask for SDHC_IRQSIGEN_DEBEIEN.
+#define BS_SDHC_IRQSIGEN_DEBEIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field.
+#define BR_SDHC_IRQSIGEN_DEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN.
+#define BF_SDHC_IRQSIGEN_DEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DEBEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_AC12EIEN (24U)    //!< Bit position for SDHC_IRQSIGEN_AC12EIEN.
+#define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) //!< Bit mask for SDHC_IRQSIGEN_AC12EIEN.
+#define BS_SDHC_IRQSIGEN_AC12EIEN (1U)     //!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field.
+#define BR_SDHC_IRQSIGEN_AC12EIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN.
+#define BF_SDHC_IRQSIGEN_AC12EIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_AC12EIEN), uint32_t) & BM_SDHC_IRQSIGEN_AC12EIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12EIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_AC12EIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DMAEIEN (28U)     //!< Bit position for SDHC_IRQSIGEN_DMAEIEN.
+#define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) //!< Bit mask for SDHC_IRQSIGEN_DMAEIEN.
+#define BS_SDHC_IRQSIGEN_DMAEIEN (1U)      //!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field.
+#define BR_SDHC_IRQSIGEN_DMAEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN.
+#define BF_SDHC_IRQSIGEN_DMAEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DMAEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DMAEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DMAEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+typedef union _hw_sdhc_ac12err
+{
+    uint32_t U;
+    struct _hw_sdhc_ac12err_bitfields
+    {
+        uint32_t AC12NE : 1;           //!< [0] Auto CMD12 Not Executed
+        uint32_t AC12TOE : 1;          //!< [1] Auto CMD12 Timeout Error
+        uint32_t AC12EBE : 1;          //!< [2] Auto CMD12 End Bit Error
+        uint32_t AC12CE : 1;           //!< [3] Auto CMD12 CRC Error
+        uint32_t AC12IE : 1;           //!< [4] Auto CMD12 Index Error
+        uint32_t RESERVED0 : 2;        //!< [6:5]
+        uint32_t CNIBAC12E : 1;        //!< [7] Command Not Issued By Auto CMD12
+                                       //! Error
+        uint32_t RESERVED1 : 24;       //!< [31:8]
+    } B;
+} hw_sdhc_ac12err_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+//@{
+#define HW_SDHC_AC12ERR_ADDR     (REGS_SDHC_BASE + 0x3CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_AC12ERR          (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR)
+#define HW_SDHC_AC12ERR_RD()     (HW_SDHC_AC12ERR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0 - Executed.
+ * - 1 - Not executed.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12NE (0U)        //!< Bit position for SDHC_AC12ERR_AC12NE.
+#define BM_SDHC_AC12ERR_AC12NE (0x00000001U) //!< Bit mask for SDHC_AC12ERR_AC12NE.
+#define BS_SDHC_AC12ERR_AC12NE (1U)        //!< Bit field size in bits for SDHC_AC12ERR_AC12NE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12NE field.
+#define BR_SDHC_AC12ERR_AC12NE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12NE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Time out.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12TOE (1U)       //!< Bit position for SDHC_AC12ERR_AC12TOE.
+#define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) //!< Bit mask for SDHC_AC12ERR_AC12TOE.
+#define BS_SDHC_AC12ERR_AC12TOE (1U)       //!< Bit field size in bits for SDHC_AC12ERR_AC12TOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12TOE field.
+#define BR_SDHC_AC12ERR_AC12TOE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12TOE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - End bit error generated.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12EBE (2U)       //!< Bit position for SDHC_AC12ERR_AC12EBE.
+#define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) //!< Bit mask for SDHC_AC12ERR_AC12EBE.
+#define BS_SDHC_AC12ERR_AC12EBE (1U)       //!< Bit field size in bits for SDHC_AC12ERR_AC12EBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12EBE field.
+#define BR_SDHC_AC12ERR_AC12EBE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12EBE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0 - No CRC error.
+ * - 1 - CRC error met in Auto CMD12 response.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12CE (3U)        //!< Bit position for SDHC_AC12ERR_AC12CE.
+#define BM_SDHC_AC12ERR_AC12CE (0x00000008U) //!< Bit mask for SDHC_AC12ERR_AC12CE.
+#define BS_SDHC_AC12ERR_AC12CE (1U)        //!< Bit field size in bits for SDHC_AC12ERR_AC12CE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12CE field.
+#define BR_SDHC_AC12ERR_AC12CE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12CE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error, the CMD index in response is not CMD12.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12IE (4U)        //!< Bit position for SDHC_AC12ERR_AC12IE.
+#define BM_SDHC_AC12ERR_AC12IE (0x00000010U) //!< Bit mask for SDHC_AC12ERR_AC12IE.
+#define BS_SDHC_AC12ERR_AC12IE (1U)        //!< Bit field size in bits for SDHC_AC12ERR_AC12IE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12IE field.
+#define BR_SDHC_AC12ERR_AC12IE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12IE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Not issued.
+ */
+//@{
+#define BP_SDHC_AC12ERR_CNIBAC12E (7U)     //!< Bit position for SDHC_AC12ERR_CNIBAC12E.
+#define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_AC12ERR_CNIBAC12E.
+#define BS_SDHC_AC12ERR_CNIBAC12E (1U)     //!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field.
+#define BR_SDHC_AC12ERR_CNIBAC12E (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_CNIBAC12E))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_HTCAPBLT - Host Controller Capabilities
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+typedef union _hw_sdhc_htcapblt
+{
+    uint32_t U;
+    struct _hw_sdhc_htcapblt_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t MBL : 3;              //!< [18:16] Max Block Length
+        uint32_t RESERVED1 : 1;        //!< [19]
+        uint32_t ADMAS : 1;            //!< [20] ADMA Support
+        uint32_t HSS : 1;              //!< [21] High Speed Support
+        uint32_t DMAS : 1;             //!< [22] DMA Support
+        uint32_t SRS : 1;              //!< [23] Suspend/Resume Support
+        uint32_t VS33 : 1;             //!< [24] Voltage Support 3.3 V
+        uint32_t RESERVED2 : 7;        //!< [31:25]
+    } B;
+} hw_sdhc_htcapblt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+//@{
+#define HW_SDHC_HTCAPBLT_ADDR    (REGS_SDHC_BASE + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_HTCAPBLT         (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR)
+#define HW_SDHC_HTCAPBLT_RD()    (HW_SDHC_HTCAPBLT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 000 - 512 bytes
+ * - 001 - 1024 bytes
+ * - 010 - 2048 bytes
+ * - 011 - 4096 bytes
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_MBL (16U)         //!< Bit position for SDHC_HTCAPBLT_MBL.
+#define BM_SDHC_HTCAPBLT_MBL (0x00070000U) //!< Bit mask for SDHC_HTCAPBLT_MBL.
+#define BS_SDHC_HTCAPBLT_MBL (3U)          //!< Bit field size in bits for SDHC_HTCAPBLT_MBL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_MBL field.
+#define BR_SDHC_HTCAPBLT_MBL (HW_SDHC_HTCAPBLT.B.MBL)
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0 - Advanced DMA not supported.
+ * - 1 - Advanced DMA supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_ADMAS (20U)       //!< Bit position for SDHC_HTCAPBLT_ADMAS.
+#define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) //!< Bit mask for SDHC_HTCAPBLT_ADMAS.
+#define BS_SDHC_HTCAPBLT_ADMAS (1U)        //!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field.
+#define BR_SDHC_HTCAPBLT_ADMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_ADMAS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0 - High speed not supported.
+ * - 1 - High speed supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_HSS (21U)         //!< Bit position for SDHC_HTCAPBLT_HSS.
+#define BM_SDHC_HTCAPBLT_HSS (0x00200000U) //!< Bit mask for SDHC_HTCAPBLT_HSS.
+#define BS_SDHC_HTCAPBLT_HSS (1U)          //!< Bit field size in bits for SDHC_HTCAPBLT_HSS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_HSS field.
+#define BR_SDHC_HTCAPBLT_HSS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_HSS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0 - DMA not supported.
+ * - 1 - DMA supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_DMAS (22U)        //!< Bit position for SDHC_HTCAPBLT_DMAS.
+#define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) //!< Bit mask for SDHC_HTCAPBLT_DMAS.
+#define BS_SDHC_HTCAPBLT_DMAS (1U)         //!< Bit field size in bits for SDHC_HTCAPBLT_DMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_DMAS field.
+#define BR_SDHC_HTCAPBLT_DMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_DMAS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0 - Not supported.
+ * - 1 - Supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_SRS (23U)         //!< Bit position for SDHC_HTCAPBLT_SRS.
+#define BM_SDHC_HTCAPBLT_SRS (0x00800000U) //!< Bit mask for SDHC_HTCAPBLT_SRS.
+#define BS_SDHC_HTCAPBLT_SRS (1U)          //!< Bit field size in bits for SDHC_HTCAPBLT_SRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_SRS field.
+#define BR_SDHC_HTCAPBLT_SRS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_SRS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0 - 3.3 V not supported.
+ * - 1 - 3.3 V supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_VS33 (24U)        //!< Bit position for SDHC_HTCAPBLT_VS33.
+#define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) //!< Bit mask for SDHC_HTCAPBLT_VS33.
+#define BS_SDHC_HTCAPBLT_VS33 (1U)         //!< Bit field size in bits for SDHC_HTCAPBLT_VS33.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_VS33 field.
+#define BR_SDHC_HTCAPBLT_VS33 (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_VS33))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_WML - Watermark Level Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+typedef union _hw_sdhc_wml
+{
+    uint32_t U;
+    struct _hw_sdhc_wml_bitfields
+    {
+        uint32_t RDWML : 8;            //!< [7:0] Read Watermark Level
+        uint32_t RESERVED0 : 8;        //!< [15:8]
+        uint32_t WRWML : 8;            //!< [23:16] Write Watermark Level
+        uint32_t RESERVED1 : 8;        //!< [31:24]
+    } B;
+} hw_sdhc_wml_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+//@{
+#define HW_SDHC_WML_ADDR         (REGS_SDHC_BASE + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_WML              (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR)
+#define HW_SDHC_WML_RD()         (HW_SDHC_WML.U)
+#define HW_SDHC_WML_WR(v)        (HW_SDHC_WML.U = (v))
+#define HW_SDHC_WML_SET(v)       (HW_SDHC_WML_WR(HW_SDHC_WML_RD() |  (v)))
+#define HW_SDHC_WML_CLR(v)       (HW_SDHC_WML_WR(HW_SDHC_WML_RD() & ~(v)))
+#define HW_SDHC_WML_TOG(v)       (HW_SDHC_WML_WR(HW_SDHC_WML_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+//@{
+#define BP_SDHC_WML_RDWML    (0U)          //!< Bit position for SDHC_WML_RDWML.
+#define BM_SDHC_WML_RDWML    (0x000000FFU) //!< Bit mask for SDHC_WML_RDWML.
+#define BS_SDHC_WML_RDWML    (8U)          //!< Bit field size in bits for SDHC_WML_RDWML.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_WML_RDWML field.
+#define BR_SDHC_WML_RDWML    (HW_SDHC_WML.B.RDWML)
+#endif
+
+//! @brief Format value for bitfield SDHC_WML_RDWML.
+#define BF_SDHC_WML_RDWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_RDWML), uint32_t) & BM_SDHC_WML_RDWML)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDWML field to a new value.
+#define BW_SDHC_WML_RDWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+//@{
+#define BP_SDHC_WML_WRWML    (16U)         //!< Bit position for SDHC_WML_WRWML.
+#define BM_SDHC_WML_WRWML    (0x00FF0000U) //!< Bit mask for SDHC_WML_WRWML.
+#define BS_SDHC_WML_WRWML    (8U)          //!< Bit field size in bits for SDHC_WML_WRWML.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_WML_WRWML field.
+#define BR_SDHC_WML_WRWML    (HW_SDHC_WML.B.WRWML)
+#endif
+
+//! @brief Format value for bitfield SDHC_WML_WRWML.
+#define BF_SDHC_WML_WRWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_WRWML), uint32_t) & BM_SDHC_WML_WRWML)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRWML field to a new value.
+#define BW_SDHC_WML_WRWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_FEVT - Force Event register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+typedef union _hw_sdhc_fevt
+{
+    uint32_t U;
+    struct _hw_sdhc_fevt_bitfields
+    {
+        uint32_t AC12NE : 1;           //!< [0] Force Event Auto Command 12 Not Executed
+        uint32_t AC12TOE : 1;          //!< [1] Force Event Auto Command 12 Time Out
+                                       //! Error
+        uint32_t AC12CE : 1;           //!< [2] Force Event Auto Command 12 CRC Error
+        uint32_t AC12EBE : 1;          //!< [3] Force Event Auto Command 12 End Bit
+                                       //! Error
+        uint32_t AC12IE : 1;           //!< [4] Force Event Auto Command 12 Index Error
+        uint32_t RESERVED0 : 2;        //!< [6:5]
+        uint32_t CNIBAC12E : 1;        //!< [7] Force Event Command Not Executed By
+                                       //! Auto Command 12 Error
+        uint32_t RESERVED1 : 8;        //!< [15:8]
+        uint32_t CTOE : 1;             //!< [16] Force Event Command Time Out Error
+        uint32_t CCE : 1;              //!< [17] Force Event Command CRC Error
+        uint32_t CEBE : 1;             //!< [18] Force Event Command End Bit Error
+        uint32_t CIE : 1;              //!< [19] Force Event Command Index Error
+        uint32_t DTOE : 1;             //!< [20] Force Event Data Time Out Error
+        uint32_t DCE : 1;              //!< [21] Force Event Data CRC Error
+        uint32_t DEBE : 1;             //!< [22] Force Event Data End Bit Error
+        uint32_t RESERVED2 : 1;        //!< [23]
+        uint32_t AC12E : 1;            //!< [24] Force Event Auto Command 12 Error
+        uint32_t RESERVED3 : 3;        //!< [27:25]
+        uint32_t DMAE : 1;             //!< [28] Force Event DMA Error
+        uint32_t RESERVED4 : 2;        //!< [30:29]
+        uint32_t CINT : 1;             //!< [31] Force Event Card Interrupt
+    } B;
+} hw_sdhc_fevt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+//@{
+#define HW_SDHC_FEVT_ADDR        (REGS_SDHC_BASE + 0x50U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_FEVT             (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR)
+#define HW_SDHC_FEVT_RD()        (HW_SDHC_FEVT.U)
+#define HW_SDHC_FEVT_WR(v)       (HW_SDHC_FEVT.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12NE  (0U)          //!< Bit position for SDHC_FEVT_AC12NE.
+#define BM_SDHC_FEVT_AC12NE  (0x00000001U) //!< Bit mask for SDHC_FEVT_AC12NE.
+#define BS_SDHC_FEVT_AC12NE  (1U)          //!< Bit field size in bits for SDHC_FEVT_AC12NE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12NE.
+#define BF_SDHC_FEVT_AC12NE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12NE), uint32_t) & BM_SDHC_FEVT_AC12NE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12NE field to a new value.
+#define BW_SDHC_FEVT_AC12NE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12NE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12TOE (1U)          //!< Bit position for SDHC_FEVT_AC12TOE.
+#define BM_SDHC_FEVT_AC12TOE (0x00000002U) //!< Bit mask for SDHC_FEVT_AC12TOE.
+#define BS_SDHC_FEVT_AC12TOE (1U)          //!< Bit field size in bits for SDHC_FEVT_AC12TOE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12TOE.
+#define BF_SDHC_FEVT_AC12TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12TOE), uint32_t) & BM_SDHC_FEVT_AC12TOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12TOE field to a new value.
+#define BW_SDHC_FEVT_AC12TOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12TOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12CE  (2U)          //!< Bit position for SDHC_FEVT_AC12CE.
+#define BM_SDHC_FEVT_AC12CE  (0x00000004U) //!< Bit mask for SDHC_FEVT_AC12CE.
+#define BS_SDHC_FEVT_AC12CE  (1U)          //!< Bit field size in bits for SDHC_FEVT_AC12CE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12CE.
+#define BF_SDHC_FEVT_AC12CE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12CE), uint32_t) & BM_SDHC_FEVT_AC12CE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12CE field to a new value.
+#define BW_SDHC_FEVT_AC12CE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12CE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12EBE (3U)          //!< Bit position for SDHC_FEVT_AC12EBE.
+#define BM_SDHC_FEVT_AC12EBE (0x00000008U) //!< Bit mask for SDHC_FEVT_AC12EBE.
+#define BS_SDHC_FEVT_AC12EBE (1U)          //!< Bit field size in bits for SDHC_FEVT_AC12EBE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12EBE.
+#define BF_SDHC_FEVT_AC12EBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12EBE), uint32_t) & BM_SDHC_FEVT_AC12EBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12EBE field to a new value.
+#define BW_SDHC_FEVT_AC12EBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12EBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12IE  (4U)          //!< Bit position for SDHC_FEVT_AC12IE.
+#define BM_SDHC_FEVT_AC12IE  (0x00000010U) //!< Bit mask for SDHC_FEVT_AC12IE.
+#define BS_SDHC_FEVT_AC12IE  (1U)          //!< Bit field size in bits for SDHC_FEVT_AC12IE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12IE.
+#define BF_SDHC_FEVT_AC12IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12IE), uint32_t) & BM_SDHC_FEVT_AC12IE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12IE field to a new value.
+#define BW_SDHC_FEVT_AC12IE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12IE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CNIBAC12E (7U)        //!< Bit position for SDHC_FEVT_CNIBAC12E.
+#define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_FEVT_CNIBAC12E.
+#define BS_SDHC_FEVT_CNIBAC12E (1U)        //!< Bit field size in bits for SDHC_FEVT_CNIBAC12E.
+
+//! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E.
+#define BF_SDHC_FEVT_CNIBAC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CNIBAC12E), uint32_t) & BM_SDHC_FEVT_CNIBAC12E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNIBAC12E field to a new value.
+#define BW_SDHC_FEVT_CNIBAC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CNIBAC12E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CTOE    (16U)         //!< Bit position for SDHC_FEVT_CTOE.
+#define BM_SDHC_FEVT_CTOE    (0x00010000U) //!< Bit mask for SDHC_FEVT_CTOE.
+#define BS_SDHC_FEVT_CTOE    (1U)          //!< Bit field size in bits for SDHC_FEVT_CTOE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CTOE.
+#define BF_SDHC_FEVT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CTOE), uint32_t) & BM_SDHC_FEVT_CTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOE field to a new value.
+#define BW_SDHC_FEVT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CCE     (17U)         //!< Bit position for SDHC_FEVT_CCE.
+#define BM_SDHC_FEVT_CCE     (0x00020000U) //!< Bit mask for SDHC_FEVT_CCE.
+#define BS_SDHC_FEVT_CCE     (1U)          //!< Bit field size in bits for SDHC_FEVT_CCE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CCE.
+#define BF_SDHC_FEVT_CCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CCE), uint32_t) & BM_SDHC_FEVT_CCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCE field to a new value.
+#define BW_SDHC_FEVT_CCE(v)  (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CEBE    (18U)         //!< Bit position for SDHC_FEVT_CEBE.
+#define BM_SDHC_FEVT_CEBE    (0x00040000U) //!< Bit mask for SDHC_FEVT_CEBE.
+#define BS_SDHC_FEVT_CEBE    (1U)          //!< Bit field size in bits for SDHC_FEVT_CEBE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CEBE.
+#define BF_SDHC_FEVT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CEBE), uint32_t) & BM_SDHC_FEVT_CEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBE field to a new value.
+#define BW_SDHC_FEVT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CIE     (19U)         //!< Bit position for SDHC_FEVT_CIE.
+#define BM_SDHC_FEVT_CIE     (0x00080000U) //!< Bit mask for SDHC_FEVT_CIE.
+#define BS_SDHC_FEVT_CIE     (1U)          //!< Bit field size in bits for SDHC_FEVT_CIE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CIE.
+#define BF_SDHC_FEVT_CIE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CIE), uint32_t) & BM_SDHC_FEVT_CIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIE field to a new value.
+#define BW_SDHC_FEVT_CIE(v)  (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DTOE    (20U)         //!< Bit position for SDHC_FEVT_DTOE.
+#define BM_SDHC_FEVT_DTOE    (0x00100000U) //!< Bit mask for SDHC_FEVT_DTOE.
+#define BS_SDHC_FEVT_DTOE    (1U)          //!< Bit field size in bits for SDHC_FEVT_DTOE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DTOE.
+#define BF_SDHC_FEVT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DTOE), uint32_t) & BM_SDHC_FEVT_DTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOE field to a new value.
+#define BW_SDHC_FEVT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DCE     (21U)         //!< Bit position for SDHC_FEVT_DCE.
+#define BM_SDHC_FEVT_DCE     (0x00200000U) //!< Bit mask for SDHC_FEVT_DCE.
+#define BS_SDHC_FEVT_DCE     (1U)          //!< Bit field size in bits for SDHC_FEVT_DCE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DCE.
+#define BF_SDHC_FEVT_DCE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DCE), uint32_t) & BM_SDHC_FEVT_DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCE field to a new value.
+#define BW_SDHC_FEVT_DCE(v)  (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DEBE    (22U)         //!< Bit position for SDHC_FEVT_DEBE.
+#define BM_SDHC_FEVT_DEBE    (0x00400000U) //!< Bit mask for SDHC_FEVT_DEBE.
+#define BS_SDHC_FEVT_DEBE    (1U)          //!< Bit field size in bits for SDHC_FEVT_DEBE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DEBE.
+#define BF_SDHC_FEVT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DEBE), uint32_t) & BM_SDHC_FEVT_DEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBE field to a new value.
+#define BW_SDHC_FEVT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12E   (24U)         //!< Bit position for SDHC_FEVT_AC12E.
+#define BM_SDHC_FEVT_AC12E   (0x01000000U) //!< Bit mask for SDHC_FEVT_AC12E.
+#define BS_SDHC_FEVT_AC12E   (1U)          //!< Bit field size in bits for SDHC_FEVT_AC12E.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12E.
+#define BF_SDHC_FEVT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12E), uint32_t) & BM_SDHC_FEVT_AC12E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12E field to a new value.
+#define BW_SDHC_FEVT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DMAE    (28U)         //!< Bit position for SDHC_FEVT_DMAE.
+#define BM_SDHC_FEVT_DMAE    (0x10000000U) //!< Bit mask for SDHC_FEVT_DMAE.
+#define BS_SDHC_FEVT_DMAE    (1U)          //!< Bit field size in bits for SDHC_FEVT_DMAE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DMAE.
+#define BF_SDHC_FEVT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DMAE), uint32_t) & BM_SDHC_FEVT_DMAE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAE field to a new value.
+#define BW_SDHC_FEVT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DMAE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+//@{
+#define BP_SDHC_FEVT_CINT    (31U)         //!< Bit position for SDHC_FEVT_CINT.
+#define BM_SDHC_FEVT_CINT    (0x80000000U) //!< Bit mask for SDHC_FEVT_CINT.
+#define BS_SDHC_FEVT_CINT    (1U)          //!< Bit field size in bits for SDHC_FEVT_CINT.
+
+//! @brief Format value for bitfield SDHC_FEVT_CINT.
+#define BF_SDHC_FEVT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CINT), uint32_t) & BM_SDHC_FEVT_CINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINT field to a new value.
+#define BW_SDHC_FEVT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CINT) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_ADMAES - ADMA Error Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+typedef union _hw_sdhc_admaes
+{
+    uint32_t U;
+    struct _hw_sdhc_admaes_bitfields
+    {
+        uint32_t ADMAES : 2;           //!< [1:0] ADMA Error State (When ADMA Error Is
+                                       //! Occurred.)
+        uint32_t ADMALME : 1;          //!< [2] ADMA Length Mismatch Error
+        uint32_t ADMADCE : 1;          //!< [3] ADMA Descriptor Error
+        uint32_t RESERVED0 : 28;       //!< [31:4]
+    } B;
+} hw_sdhc_admaes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+//@{
+#define HW_SDHC_ADMAES_ADDR      (REGS_SDHC_BASE + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_ADMAES           (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR)
+#define HW_SDHC_ADMAES_RD()      (HW_SDHC_ADMAES.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+//@{
+#define BP_SDHC_ADMAES_ADMAES (0U)         //!< Bit position for SDHC_ADMAES_ADMAES.
+#define BM_SDHC_ADMAES_ADMAES (0x00000003U) //!< Bit mask for SDHC_ADMAES_ADMAES.
+#define BS_SDHC_ADMAES_ADMAES (2U)         //!< Bit field size in bits for SDHC_ADMAES_ADMAES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADMAES_ADMAES field.
+#define BR_SDHC_ADMAES_ADMAES (HW_SDHC_ADMAES.B.ADMAES)
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_ADMAES_ADMALME (2U)        //!< Bit position for SDHC_ADMAES_ADMALME.
+#define BM_SDHC_ADMAES_ADMALME (0x00000004U) //!< Bit mask for SDHC_ADMAES_ADMALME.
+#define BS_SDHC_ADMAES_ADMALME (1U)        //!< Bit field size in bits for SDHC_ADMAES_ADMALME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADMAES_ADMALME field.
+#define BR_SDHC_ADMAES_ADMALME (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMALME))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_ADMAES_ADMADCE (3U)        //!< Bit position for SDHC_ADMAES_ADMADCE.
+#define BM_SDHC_ADMAES_ADMADCE (0x00000008U) //!< Bit mask for SDHC_ADMAES_ADMADCE.
+#define BS_SDHC_ADMAES_ADMADCE (1U)        //!< Bit field size in bits for SDHC_ADMAES_ADMADCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADMAES_ADMADCE field.
+#define BR_SDHC_ADMAES_ADMADCE (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMADCE))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_ADSADDR - ADMA System Addressregister
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+typedef union _hw_sdhc_adsaddr
+{
+    uint32_t U;
+    struct _hw_sdhc_adsaddr_bitfields
+    {
+        uint32_t RESERVED0 : 2;        //!< [1:0]
+        uint32_t ADSADDR : 30;         //!< [31:2] ADMA System Address
+    } B;
+} hw_sdhc_adsaddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+//@{
+#define HW_SDHC_ADSADDR_ADDR     (REGS_SDHC_BASE + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_ADSADDR          (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR)
+#define HW_SDHC_ADSADDR_RD()     (HW_SDHC_ADSADDR.U)
+#define HW_SDHC_ADSADDR_WR(v)    (HW_SDHC_ADSADDR.U = (v))
+#define HW_SDHC_ADSADDR_SET(v)   (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() |  (v)))
+#define HW_SDHC_ADSADDR_CLR(v)   (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() & ~(v)))
+#define HW_SDHC_ADSADDR_TOG(v)   (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+//@{
+#define BP_SDHC_ADSADDR_ADSADDR (2U)       //!< Bit position for SDHC_ADSADDR_ADSADDR.
+#define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_ADSADDR_ADSADDR.
+#define BS_SDHC_ADSADDR_ADSADDR (30U)      //!< Bit field size in bits for SDHC_ADSADDR_ADSADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADSADDR_ADSADDR field.
+#define BR_SDHC_ADSADDR_ADSADDR (HW_SDHC_ADSADDR.B.ADSADDR)
+#endif
+
+//! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR.
+#define BF_SDHC_ADSADDR_ADSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_ADSADDR_ADSADDR), uint32_t) & BM_SDHC_ADSADDR_ADSADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADSADDR field to a new value.
+#define BW_SDHC_ADSADDR_ADSADDR(v) (HW_SDHC_ADSADDR_WR((HW_SDHC_ADSADDR_RD() & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_VENDOR - Vendor Specific register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+typedef union _hw_sdhc_vendor
+{
+    uint32_t U;
+    struct _hw_sdhc_vendor_bitfields
+    {
+        uint32_t EXTDMAEN : 1;         //!< [0] External DMA Request Enable
+        uint32_t EXBLKNU : 1;          //!< [1] Exact Block Number Block Read Enable
+                                       //! For SDIO CMD53
+        uint32_t RESERVED0 : 14;       //!< [15:2]
+        uint32_t INTSTVAL : 8;         //!< [23:16] Internal State Value
+        uint32_t RESERVED1 : 8;        //!< [31:24]
+    } B;
+} hw_sdhc_vendor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+//@{
+#define HW_SDHC_VENDOR_ADDR      (REGS_SDHC_BASE + 0xC0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_VENDOR           (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR)
+#define HW_SDHC_VENDOR_RD()      (HW_SDHC_VENDOR.U)
+#define HW_SDHC_VENDOR_WR(v)     (HW_SDHC_VENDOR.U = (v))
+#define HW_SDHC_VENDOR_SET(v)    (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() |  (v)))
+#define HW_SDHC_VENDOR_CLR(v)    (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() & ~(v)))
+#define HW_SDHC_VENDOR_TOG(v)    (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 1 - When internal DMA is not active, the external DMA request will be sent
+ *     out.
+ */
+//@{
+#define BP_SDHC_VENDOR_EXTDMAEN (0U)       //!< Bit position for SDHC_VENDOR_EXTDMAEN.
+#define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) //!< Bit mask for SDHC_VENDOR_EXTDMAEN.
+#define BS_SDHC_VENDOR_EXTDMAEN (1U)       //!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field.
+#define BR_SDHC_VENDOR_EXTDMAEN (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN.
+#define BF_SDHC_VENDOR_EXTDMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXTDMAEN), uint32_t) & BM_SDHC_VENDOR_EXTDMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXTDMAEN field to a new value.
+#define BW_SDHC_VENDOR_EXTDMAEN(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0 - None exact block read.
+ * - 1 - Exact block read for SDIO CMD53.
+ */
+//@{
+#define BP_SDHC_VENDOR_EXBLKNU (1U)        //!< Bit position for SDHC_VENDOR_EXBLKNU.
+#define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) //!< Bit mask for SDHC_VENDOR_EXBLKNU.
+#define BS_SDHC_VENDOR_EXBLKNU (1U)        //!< Bit field size in bits for SDHC_VENDOR_EXBLKNU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_VENDOR_EXBLKNU field.
+#define BR_SDHC_VENDOR_EXBLKNU (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU))
+#endif
+
+//! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU.
+#define BF_SDHC_VENDOR_EXBLKNU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXBLKNU), uint32_t) & BM_SDHC_VENDOR_EXBLKNU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXBLKNU field to a new value.
+#define BW_SDHC_VENDOR_EXBLKNU(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+//@{
+#define BP_SDHC_VENDOR_INTSTVAL (16U)      //!< Bit position for SDHC_VENDOR_INTSTVAL.
+#define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) //!< Bit mask for SDHC_VENDOR_INTSTVAL.
+#define BS_SDHC_VENDOR_INTSTVAL (8U)       //!< Bit field size in bits for SDHC_VENDOR_INTSTVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_VENDOR_INTSTVAL field.
+#define BR_SDHC_VENDOR_INTSTVAL (HW_SDHC_VENDOR.B.INTSTVAL)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_MMCBOOT - MMC Boot register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+typedef union _hw_sdhc_mmcboot
+{
+    uint32_t U;
+    struct _hw_sdhc_mmcboot_bitfields
+    {
+        uint32_t DTOCVACK : 4;         //!< [3:0] Boot ACK Time Out Counter Value
+        uint32_t BOOTACK : 1;          //!< [4] Boot Ack Mode Select
+        uint32_t BOOTMODE : 1;         //!< [5] Boot Mode Select
+        uint32_t BOOTEN : 1;           //!< [6] Boot Mode Enable
+        uint32_t AUTOSABGEN : 1;       //!< [7]
+        uint32_t RESERVED0 : 8;        //!< [15:8]
+        uint32_t BOOTBLKCNT : 16;      //!< [31:16]
+    } B;
+} hw_sdhc_mmcboot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+//@{
+#define HW_SDHC_MMCBOOT_ADDR     (REGS_SDHC_BASE + 0xC4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_MMCBOOT          (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR)
+#define HW_SDHC_MMCBOOT_RD()     (HW_SDHC_MMCBOOT.U)
+#define HW_SDHC_MMCBOOT_WR(v)    (HW_SDHC_MMCBOOT.U = (v))
+#define HW_SDHC_MMCBOOT_SET(v)   (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() |  (v)))
+#define HW_SDHC_MMCBOOT_CLR(v)   (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() & ~(v)))
+#define HW_SDHC_MMCBOOT_TOG(v)   (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0000 - SDCLK x 2^8
+ * - 0001 - SDCLK x 2^9
+ * - 0010 - SDCLK x 2^10
+ * - 0011 - SDCLK x 2^11
+ * - 0100 - SDCLK x 2^12
+ * - 0101 - SDCLK x 2^13
+ * - 0110 - SDCLK x 2^14
+ * - 0111 - SDCLK x 2^15
+ * - 1110 - SDCLK x 2^22
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SDHC_MMCBOOT_DTOCVACK (0U)      //!< Bit position for SDHC_MMCBOOT_DTOCVACK.
+#define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) //!< Bit mask for SDHC_MMCBOOT_DTOCVACK.
+#define BS_SDHC_MMCBOOT_DTOCVACK (4U)      //!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field.
+#define BR_SDHC_MMCBOOT_DTOCVACK (HW_SDHC_MMCBOOT.B.DTOCVACK)
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK.
+#define BF_SDHC_MMCBOOT_DTOCVACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_DTOCVACK), uint32_t) & BM_SDHC_MMCBOOT_DTOCVACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOCVACK field to a new value.
+#define BW_SDHC_MMCBOOT_DTOCVACK(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0 - No ack.
+ * - 1 - Ack.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTACK (4U)       //!< Bit position for SDHC_MMCBOOT_BOOTACK.
+#define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) //!< Bit mask for SDHC_MMCBOOT_BOOTACK.
+#define BS_SDHC_MMCBOOT_BOOTACK (1U)       //!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field.
+#define BR_SDHC_MMCBOOT_BOOTACK (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK.
+#define BF_SDHC_MMCBOOT_BOOTACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTACK), uint32_t) & BM_SDHC_MMCBOOT_BOOTACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTACK field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTACK(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0 - Normal boot.
+ * - 1 - Alternative boot.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTMODE (5U)      //!< Bit position for SDHC_MMCBOOT_BOOTMODE.
+#define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) //!< Bit mask for SDHC_MMCBOOT_BOOTMODE.
+#define BS_SDHC_MMCBOOT_BOOTMODE (1U)      //!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field.
+#define BR_SDHC_MMCBOOT_BOOTMODE (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE.
+#define BF_SDHC_MMCBOOT_BOOTMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTMODE), uint32_t) & BM_SDHC_MMCBOOT_BOOTMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTMODE field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTMODE(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Fast boot disable.
+ * - 1 - Fast boot enable.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTEN (6U)        //!< Bit position for SDHC_MMCBOOT_BOOTEN.
+#define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) //!< Bit mask for SDHC_MMCBOOT_BOOTEN.
+#define BS_SDHC_MMCBOOT_BOOTEN (1U)        //!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field.
+#define BR_SDHC_MMCBOOT_BOOTEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN.
+#define BF_SDHC_MMCBOOT_BOOTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTEN), uint32_t) & BM_SDHC_MMCBOOT_BOOTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTEN field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_AUTOSABGEN (7U)    //!< Bit position for SDHC_MMCBOOT_AUTOSABGEN.
+#define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) //!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN.
+#define BS_SDHC_MMCBOOT_AUTOSABGEN (1U)    //!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field.
+#define BR_SDHC_MMCBOOT_AUTOSABGEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN.
+#define BF_SDHC_MMCBOOT_AUTOSABGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_AUTOSABGEN), uint32_t) & BM_SDHC_MMCBOOT_AUTOSABGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AUTOSABGEN field to a new value.
+#define BW_SDHC_MMCBOOT_AUTOSABGEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U)   //!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT.
+#define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT.
+#define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U)   //!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field.
+#define BR_SDHC_MMCBOOT_BOOTBLKCNT (HW_SDHC_MMCBOOT.B.BOOTBLKCNT)
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT.
+#define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTBLKCNT), uint32_t) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTBLKCNT field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTBLKCNT(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_HOSTVER - Host Controller Version
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+typedef union _hw_sdhc_hostver
+{
+    uint32_t U;
+    struct _hw_sdhc_hostver_bitfields
+    {
+        uint32_t SVN : 8;              //!< [7:0] Specification Version Number
+        uint32_t VVN : 8;              //!< [15:8] Vendor Version Number
+        uint32_t RESERVED0 : 16;       //!< [31:16]
+    } B;
+} hw_sdhc_hostver_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+//@{
+#define HW_SDHC_HOSTVER_ADDR     (REGS_SDHC_BASE + 0xFCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_HOSTVER          (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR)
+#define HW_SDHC_HOSTVER_RD()     (HW_SDHC_HOSTVER.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 1 - SD host specification version 2.0, supports test event register and
+ *     ADMA.
+ */
+//@{
+#define BP_SDHC_HOSTVER_SVN  (0U)          //!< Bit position for SDHC_HOSTVER_SVN.
+#define BM_SDHC_HOSTVER_SVN  (0x000000FFU) //!< Bit mask for SDHC_HOSTVER_SVN.
+#define BS_SDHC_HOSTVER_SVN  (8U)          //!< Bit field size in bits for SDHC_HOSTVER_SVN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HOSTVER_SVN field.
+#define BR_SDHC_HOSTVER_SVN  (HW_SDHC_HOSTVER.B.SVN)
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0 - Freescale SDHC version 1.0
+ * - 10000 - Freescale SDHC version 2.0
+ * - 10001 - Freescale SDHC version 2.1
+ * - 10010 - Freescale SDHC version 2.2
+ */
+//@{
+#define BP_SDHC_HOSTVER_VVN  (8U)          //!< Bit position for SDHC_HOSTVER_VVN.
+#define BM_SDHC_HOSTVER_VVN  (0x0000FF00U) //!< Bit mask for SDHC_HOSTVER_VVN.
+#define BS_SDHC_HOSTVER_VVN  (8U)          //!< Bit field size in bits for SDHC_HOSTVER_VVN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HOSTVER_VVN field.
+#define BR_SDHC_HOSTVER_VVN  (HW_SDHC_HOSTVER.B.VVN)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_sdhc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SDHC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_sdhc
+{
+    __IO hw_sdhc_dsaddr_t DSADDR;          //!< [0x0] DMA System Address register
+    __IO hw_sdhc_blkattr_t BLKATTR;        //!< [0x4] Block Attributes register
+    __IO hw_sdhc_cmdarg_t CMDARG;          //!< [0x8] Command Argument register
+    __IO hw_sdhc_xfertyp_t XFERTYP;        //!< [0xC] Transfer Type register
+    __I hw_sdhc_cmdrsp0_t CMDRSP0;         //!< [0x10] Command Response 0
+    __I hw_sdhc_cmdrsp1_t CMDRSP1;         //!< [0x14] Command Response 1
+    __I hw_sdhc_cmdrsp2_t CMDRSP2;         //!< [0x18] Command Response 2
+    __I hw_sdhc_cmdrsp3_t CMDRSP3;         //!< [0x1C] Command Response 3
+    __IO hw_sdhc_datport_t DATPORT;        //!< [0x20] Buffer Data Port register
+    __I hw_sdhc_prsstat_t PRSSTAT;         //!< [0x24] Present State register
+    __IO hw_sdhc_proctl_t PROCTL;          //!< [0x28] Protocol Control register
+    __IO hw_sdhc_sysctl_t SYSCTL;          //!< [0x2C] System Control register
+    __IO hw_sdhc_irqstat_t IRQSTAT;        //!< [0x30] Interrupt Status register
+    __IO hw_sdhc_irqstaten_t IRQSTATEN;    //!< [0x34] Interrupt Status Enable register
+    __IO hw_sdhc_irqsigen_t IRQSIGEN;      //!< [0x38] Interrupt Signal Enable register
+    __I hw_sdhc_ac12err_t AC12ERR;         //!< [0x3C] Auto CMD12 Error Status Register
+    __I hw_sdhc_htcapblt_t HTCAPBLT;       //!< [0x40] Host Controller Capabilities
+    __IO hw_sdhc_wml_t WML;                //!< [0x44] Watermark Level Register
+    uint8_t _reserved0[8];
+    __O hw_sdhc_fevt_t FEVT;               //!< [0x50] Force Event register
+    __I hw_sdhc_admaes_t ADMAES;           //!< [0x54] ADMA Error Status register
+    __IO hw_sdhc_adsaddr_t ADSADDR;        //!< [0x58] ADMA System Addressregister
+    uint8_t _reserved1[100];
+    __IO hw_sdhc_vendor_t VENDOR;          //!< [0xC0] Vendor Specific register
+    __IO hw_sdhc_mmcboot_t MMCBOOT;        //!< [0xC4] MMC Boot register
+    uint8_t _reserved2[52];
+    __I hw_sdhc_hostver_t HOSTVER;         //!< [0xFC] Host Controller Version
+} hw_sdhc_t;
+#pragma pack()
+
+//! @brief Macro to access all SDHC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_SDHC</code>.
+#define HW_SDHC        (*(hw_sdhc_t *) REGS_SDHC_BASE)
+#endif
+
+#endif // __HW_SDHC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h
new file mode 100644
index 0000000000..0b746404ad
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h
@@ -0,0 +1,4553 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SIM_REGISTERS_H__
+#define __HW_SIM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - HW_SIM_SOPT1 - System Options Register 1
+ * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - HW_SIM_SOPT2 - System Options Register 2
+ * - HW_SIM_SOPT4 - System Options Register 4
+ * - HW_SIM_SOPT5 - System Options Register 5
+ * - HW_SIM_SOPT7 - System Options Register 7
+ * - HW_SIM_SDID - System Device Identification Register
+ * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
+ * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
+ * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
+ * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
+ * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
+ * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
+ * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
+ * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
+ * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
+ * - HW_SIM_FCFG1 - Flash Configuration Register 1
+ * - HW_SIM_FCFG2 - Flash Configuration Register 2
+ * - HW_SIM_UIDH - Unique Identification Register High
+ * - HW_SIM_UIDMH - Unique Identification Register Mid-High
+ * - HW_SIM_UIDML - Unique Identification Register Mid Low
+ * - HW_SIM_UIDL - Unique Identification Register Low
+ *
+ * - hw_sim_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SIM_BASE
+#define HW_SIM_INSTANCE_COUNT (1U) //!< Number of instances of the SIM module.
+#define REGS_SIM_BASE (0x40047000U) //!< Base address for SIM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT1 - System Options Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+typedef union _hw_sim_sopt1
+{
+    uint32_t U;
+    struct _hw_sim_sopt1_bitfields
+    {
+        uint32_t RESERVED0 : 12;       //!< [11:0]
+        uint32_t RAMSIZE : 4;          //!< [15:12] RAM size
+        uint32_t RESERVED1 : 2;        //!< [17:16]
+        uint32_t OSC32KSEL : 2;        //!< [19:18] 32K oscillator clock select
+        uint32_t RESERVED2 : 9;        //!< [28:20]
+        uint32_t USBVSTBY : 1;         //!< [29] USB voltage regulator in standby
+                                       //! mode during VLPR and VLPW modes
+        uint32_t USBSSTBY : 1;         //!< [30] USB voltage regulator in standby
+                                       //! mode during Stop, VLPS, LLS and VLLS modes.
+        uint32_t USBREGEN : 1;         //!< [31] USB voltage regulator enable
+    } B;
+} hw_sim_sopt1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+//@{
+#define HW_SIM_SOPT1_ADDR        (REGS_SIM_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT1             (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR)
+#define HW_SIM_SOPT1_RD()        (HW_SIM_SOPT1.U)
+#define HW_SIM_SOPT1_WR(v)       (HW_SIM_SOPT1.U = (v))
+#define HW_SIM_SOPT1_SET(v)      (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() |  (v)))
+#define HW_SIM_SOPT1_CLR(v)      (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() & ~(v)))
+#define HW_SIM_SOPT1_TOG(v)      (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0001 - 8 KB
+ * - 0011 - 16 KB
+ * - 0100 - 24 KB
+ * - 0101 - 32 KB
+ * - 0110 - 48 KB
+ * - 0111 - 64 KB
+ * - 1000 - 96 KB
+ * - 1001 - 128 KB
+ * - 1011 - 256 KB
+ */
+//@{
+#define BP_SIM_SOPT1_RAMSIZE (12U)         //!< Bit position for SIM_SOPT1_RAMSIZE.
+#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) //!< Bit mask for SIM_SOPT1_RAMSIZE.
+#define BS_SIM_SOPT1_RAMSIZE (4U)          //!< Bit field size in bits for SIM_SOPT1_RAMSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_RAMSIZE field.
+#define BR_SIM_SOPT1_RAMSIZE (HW_SIM_SOPT1.B.RAMSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 00 - System oscillator (OSC32KCLK)
+ * - 01 - Reserved
+ * - 10 - RTC 32.768kHz oscillator
+ * - 11 - LPO 1 kHz
+ */
+//@{
+#define BP_SIM_SOPT1_OSC32KSEL (18U)       //!< Bit position for SIM_SOPT1_OSC32KSEL.
+#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) //!< Bit mask for SIM_SOPT1_OSC32KSEL.
+#define BS_SIM_SOPT1_OSC32KSEL (2U)        //!< Bit field size in bits for SIM_SOPT1_OSC32KSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_OSC32KSEL field.
+#define BR_SIM_SOPT1_OSC32KSEL (HW_SIM_SOPT1.B.OSC32KSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL.
+#define BF_SIM_SOPT1_OSC32KSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_OSC32KSEL), uint32_t) & BM_SIM_SOPT1_OSC32KSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OSC32KSEL field to a new value.
+#define BW_SIM_SOPT1_OSC32KSEL(v) (HW_SIM_SOPT1_WR((HW_SIM_SOPT1_RD() & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+//@{
+#define BP_SIM_SOPT1_USBVSTBY (29U)        //!< Bit position for SIM_SOPT1_USBVSTBY.
+#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) //!< Bit mask for SIM_SOPT1_USBVSTBY.
+#define BS_SIM_SOPT1_USBVSTBY (1U)         //!< Bit field size in bits for SIM_SOPT1_USBVSTBY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_USBVSTBY field.
+#define BR_SIM_SOPT1_USBVSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_USBVSTBY.
+#define BF_SIM_SOPT1_USBVSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBVSTBY), uint32_t) & BM_SIM_SOPT1_USBVSTBY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBVSTBY field to a new value.
+#define BW_SIM_SOPT1_USBVSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
+ */
+//@{
+#define BP_SIM_SOPT1_USBSSTBY (30U)        //!< Bit position for SIM_SOPT1_USBSSTBY.
+#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) //!< Bit mask for SIM_SOPT1_USBSSTBY.
+#define BS_SIM_SOPT1_USBSSTBY (1U)         //!< Bit field size in bits for SIM_SOPT1_USBSSTBY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_USBSSTBY field.
+#define BR_SIM_SOPT1_USBSSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_USBSSTBY.
+#define BF_SIM_SOPT1_USBSSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBSSTBY), uint32_t) & BM_SIM_SOPT1_USBSSTBY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBSSTBY field to a new value.
+#define BW_SIM_SOPT1_USBSSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0 - USB voltage regulator is disabled.
+ * - 1 - USB voltage regulator is enabled.
+ */
+//@{
+#define BP_SIM_SOPT1_USBREGEN (31U)        //!< Bit position for SIM_SOPT1_USBREGEN.
+#define BM_SIM_SOPT1_USBREGEN (0x80000000U) //!< Bit mask for SIM_SOPT1_USBREGEN.
+#define BS_SIM_SOPT1_USBREGEN (1U)         //!< Bit field size in bits for SIM_SOPT1_USBREGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_USBREGEN field.
+#define BR_SIM_SOPT1_USBREGEN (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_USBREGEN.
+#define BF_SIM_SOPT1_USBREGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBREGEN), uint32_t) & BM_SIM_SOPT1_USBREGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBREGEN field to a new value.
+#define BW_SIM_SOPT1_USBREGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT1CFG - SOPT1 Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+typedef union _hw_sim_sopt1cfg
+{
+    uint32_t U;
+    struct _hw_sim_sopt1cfg_bitfields
+    {
+        uint32_t RESERVED0 : 24;       //!< [23:0]
+        uint32_t URWE : 1;             //!< [24] USB voltage regulator enable write enable
+        uint32_t UVSWE : 1;            //!< [25] USB voltage regulator VLP standby write
+                                       //! enable
+        uint32_t USSWE : 1;            //!< [26] USB voltage regulator stop standby
+                                       //! write enable
+        uint32_t RESERVED1 : 5;        //!< [31:27]
+    } B;
+} hw_sim_sopt1cfg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+//@{
+#define HW_SIM_SOPT1CFG_ADDR     (REGS_SIM_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT1CFG          (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR)
+#define HW_SIM_SOPT1CFG_RD()     (HW_SIM_SOPT1CFG.U)
+#define HW_SIM_SOPT1CFG_WR(v)    (HW_SIM_SOPT1CFG.U = (v))
+#define HW_SIM_SOPT1CFG_SET(v)   (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() |  (v)))
+#define HW_SIM_SOPT1CFG_CLR(v)   (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() & ~(v)))
+#define HW_SIM_SOPT1CFG_TOG(v)   (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0 - SOPT1 USBREGEN cannot be written.
+ * - 1 - SOPT1 USBREGEN can be written.
+ */
+//@{
+#define BP_SIM_SOPT1CFG_URWE (24U)         //!< Bit position for SIM_SOPT1CFG_URWE.
+#define BM_SIM_SOPT1CFG_URWE (0x01000000U) //!< Bit mask for SIM_SOPT1CFG_URWE.
+#define BS_SIM_SOPT1CFG_URWE (1U)          //!< Bit field size in bits for SIM_SOPT1CFG_URWE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1CFG_URWE field.
+#define BR_SIM_SOPT1CFG_URWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1CFG_URWE.
+#define BF_SIM_SOPT1CFG_URWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_URWE), uint32_t) & BM_SIM_SOPT1CFG_URWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the URWE field to a new value.
+#define BW_SIM_SOPT1CFG_URWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0 - SOPT1 USBVSTBY cannot be written.
+ * - 1 - SOPT1 USBVSTBY can be written.
+ */
+//@{
+#define BP_SIM_SOPT1CFG_UVSWE (25U)        //!< Bit position for SIM_SOPT1CFG_UVSWE.
+#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) //!< Bit mask for SIM_SOPT1CFG_UVSWE.
+#define BS_SIM_SOPT1CFG_UVSWE (1U)         //!< Bit field size in bits for SIM_SOPT1CFG_UVSWE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1CFG_UVSWE field.
+#define BR_SIM_SOPT1CFG_UVSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE.
+#define BF_SIM_SOPT1CFG_UVSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_UVSWE), uint32_t) & BM_SIM_SOPT1CFG_UVSWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UVSWE field to a new value.
+#define BW_SIM_SOPT1CFG_UVSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0 - SOPT1 USBSSTBY cannot be written.
+ * - 1 - SOPT1 USBSSTBY can be written.
+ */
+//@{
+#define BP_SIM_SOPT1CFG_USSWE (26U)        //!< Bit position for SIM_SOPT1CFG_USSWE.
+#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) //!< Bit mask for SIM_SOPT1CFG_USSWE.
+#define BS_SIM_SOPT1CFG_USSWE (1U)         //!< Bit field size in bits for SIM_SOPT1CFG_USSWE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1CFG_USSWE field.
+#define BR_SIM_SOPT1CFG_USSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1CFG_USSWE.
+#define BF_SIM_SOPT1CFG_USSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_USSWE), uint32_t) & BM_SIM_SOPT1CFG_USSWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USSWE field to a new value.
+#define BW_SIM_SOPT1CFG_USSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT2 - System Options Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+typedef union _hw_sim_sopt2
+{
+    uint32_t U;
+    struct _hw_sim_sopt2_bitfields
+    {
+        uint32_t RESERVED0 : 4;        //!< [3:0]
+        uint32_t RTCCLKOUTSEL : 1;     //!< [4] RTC clock out select
+        uint32_t CLKOUTSEL : 3;        //!< [7:5] CLKOUT select
+        uint32_t FBSL : 2;             //!< [9:8] FlexBus security level
+        uint32_t RESERVED1 : 1;        //!< [10]
+        uint32_t PTD7PAD : 1;          //!< [11] PTD7 pad drive strength
+        uint32_t TRACECLKSEL : 1;      //!< [12] Debug trace clock select
+        uint32_t RESERVED2 : 3;        //!< [15:13]
+        uint32_t PLLFLLSEL : 2;        //!< [17:16] PLL/FLL clock select
+        uint32_t USBSRC : 1;           //!< [18] USB clock source select
+        uint32_t RMIISRC : 1;          //!< [19] RMII clock source select
+        uint32_t TIMESRC : 2;          //!< [21:20] IEEE 1588 timestamp clock source
+                                       //! select
+        uint32_t RESERVED3 : 6;        //!< [27:22]
+        uint32_t SDHCSRC : 2;          //!< [29:28] SDHC clock source select
+        uint32_t RESERVED4 : 2;        //!< [31:30]
+    } B;
+} hw_sim_sopt2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+//@{
+#define HW_SIM_SOPT2_ADDR        (REGS_SIM_BASE + 0x1004U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT2             (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR)
+#define HW_SIM_SOPT2_RD()        (HW_SIM_SOPT2.U)
+#define HW_SIM_SOPT2_WR(v)       (HW_SIM_SOPT2.U = (v))
+#define HW_SIM_SOPT2_SET(v)      (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() |  (v)))
+#define HW_SIM_SOPT2_CLR(v)      (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() & ~(v)))
+#define HW_SIM_SOPT2_TOG(v)      (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+//@{
+#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U)     //!< Bit position for SIM_SOPT2_RTCCLKOUTSEL.
+#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) //!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL.
+#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U)     //!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field.
+#define BR_SIM_SOPT2_RTCCLKOUTSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL.
+#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RTCCLKOUTSEL), uint32_t) & BM_SIM_SOPT2_RTCCLKOUTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RTCCLKOUTSEL field to a new value.
+#define BW_SIM_SOPT2_RTCCLKOUTSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 000 - FlexBus CLKOUT
+ * - 001 - Reserved
+ * - 010 - Flash clock
+ * - 011 - LPO clock (1 kHz)
+ * - 100 - MCGIRCLK
+ * - 101 - RTC 32.768kHz clock
+ * - 110 - OSCERCLK0
+ * - 111 - IRC 48 MHz clock
+ */
+//@{
+#define BP_SIM_SOPT2_CLKOUTSEL (5U)        //!< Bit position for SIM_SOPT2_CLKOUTSEL.
+#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) //!< Bit mask for SIM_SOPT2_CLKOUTSEL.
+#define BS_SIM_SOPT2_CLKOUTSEL (3U)        //!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field.
+#define BR_SIM_SOPT2_CLKOUTSEL (HW_SIM_SOPT2.B.CLKOUTSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL.
+#define BF_SIM_SOPT2_CLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_CLKOUTSEL), uint32_t) & BM_SIM_SOPT2_CLKOUTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKOUTSEL field to a new value.
+#define BW_SIM_SOPT2_CLKOUTSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+//@{
+#define BP_SIM_SOPT2_FBSL    (8U)          //!< Bit position for SIM_SOPT2_FBSL.
+#define BM_SIM_SOPT2_FBSL    (0x00000300U) //!< Bit mask for SIM_SOPT2_FBSL.
+#define BS_SIM_SOPT2_FBSL    (2U)          //!< Bit field size in bits for SIM_SOPT2_FBSL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_FBSL field.
+#define BR_SIM_SOPT2_FBSL    (HW_SIM_SOPT2.B.FBSL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_FBSL.
+#define BF_SIM_SOPT2_FBSL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_FBSL), uint32_t) & BM_SIM_SOPT2_FBSL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FBSL field to a new value.
+#define BW_SIM_SOPT2_FBSL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0 - Single-pad drive strength for PTD7.
+ * - 1 - Double pad drive strength for PTD7.
+ */
+//@{
+#define BP_SIM_SOPT2_PTD7PAD (11U)         //!< Bit position for SIM_SOPT2_PTD7PAD.
+#define BM_SIM_SOPT2_PTD7PAD (0x00000800U) //!< Bit mask for SIM_SOPT2_PTD7PAD.
+#define BS_SIM_SOPT2_PTD7PAD (1U)          //!< Bit field size in bits for SIM_SOPT2_PTD7PAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_PTD7PAD field.
+#define BR_SIM_SOPT2_PTD7PAD (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_PTD7PAD.
+#define BF_SIM_SOPT2_PTD7PAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PTD7PAD), uint32_t) & BM_SIM_SOPT2_PTD7PAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTD7PAD field to a new value.
+#define BW_SIM_SOPT2_PTD7PAD(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0 - MCGOUTCLK
+ * - 1 - Core/system clock
+ */
+//@{
+#define BP_SIM_SOPT2_TRACECLKSEL (12U)     //!< Bit position for SIM_SOPT2_TRACECLKSEL.
+#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) //!< Bit mask for SIM_SOPT2_TRACECLKSEL.
+#define BS_SIM_SOPT2_TRACECLKSEL (1U)      //!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field.
+#define BR_SIM_SOPT2_TRACECLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL.
+#define BF_SIM_SOPT2_TRACECLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TRACECLKSEL), uint32_t) & BM_SIM_SOPT2_TRACECLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRACECLKSEL field to a new value.
+#define BW_SIM_SOPT2_TRACECLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 00 - MCGFLLCLK clock
+ * - 01 - MCGPLLCLK clock
+ * - 10 - Reserved
+ * - 11 - IRC48 MHz clock
+ */
+//@{
+#define BP_SIM_SOPT2_PLLFLLSEL (16U)       //!< Bit position for SIM_SOPT2_PLLFLLSEL.
+#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) //!< Bit mask for SIM_SOPT2_PLLFLLSEL.
+#define BS_SIM_SOPT2_PLLFLLSEL (2U)        //!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field.
+#define BR_SIM_SOPT2_PLLFLLSEL (HW_SIM_SOPT2.B.PLLFLLSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL.
+#define BF_SIM_SOPT2_PLLFLLSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PLLFLLSEL), uint32_t) & BM_SIM_SOPT2_PLLFLLSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLFLLSEL field to a new value.
+#define BW_SIM_SOPT2_PLLFLLSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0 - External bypass clock (USB_CLKIN).
+ * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+//@{
+#define BP_SIM_SOPT2_USBSRC  (18U)         //!< Bit position for SIM_SOPT2_USBSRC.
+#define BM_SIM_SOPT2_USBSRC  (0x00040000U) //!< Bit mask for SIM_SOPT2_USBSRC.
+#define BS_SIM_SOPT2_USBSRC  (1U)          //!< Bit field size in bits for SIM_SOPT2_USBSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_USBSRC field.
+#define BR_SIM_SOPT2_USBSRC  (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_USBSRC.
+#define BF_SIM_SOPT2_USBSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_USBSRC), uint32_t) & BM_SIM_SOPT2_USBSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBSRC field to a new value.
+#define BW_SIM_SOPT2_USBSRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0 - EXTAL clock
+ * - 1 - External bypass clock (ENET_1588_CLKIN).
+ */
+//@{
+#define BP_SIM_SOPT2_RMIISRC (19U)         //!< Bit position for SIM_SOPT2_RMIISRC.
+#define BM_SIM_SOPT2_RMIISRC (0x00080000U) //!< Bit mask for SIM_SOPT2_RMIISRC.
+#define BS_SIM_SOPT2_RMIISRC (1U)          //!< Bit field size in bits for SIM_SOPT2_RMIISRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_RMIISRC field.
+#define BR_SIM_SOPT2_RMIISRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_RMIISRC.
+#define BF_SIM_SOPT2_RMIISRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RMIISRC), uint32_t) & BM_SIM_SOPT2_RMIISRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMIISRC field to a new value.
+#define BW_SIM_SOPT2_RMIISRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 00 - Core/system clock.
+ * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 10 - OSCERCLK clock
+ * - 11 - External bypass clock (ENET_1588_CLKIN).
+ */
+//@{
+#define BP_SIM_SOPT2_TIMESRC (20U)         //!< Bit position for SIM_SOPT2_TIMESRC.
+#define BM_SIM_SOPT2_TIMESRC (0x00300000U) //!< Bit mask for SIM_SOPT2_TIMESRC.
+#define BS_SIM_SOPT2_TIMESRC (2U)          //!< Bit field size in bits for SIM_SOPT2_TIMESRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_TIMESRC field.
+#define BR_SIM_SOPT2_TIMESRC (HW_SIM_SOPT2.B.TIMESRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_TIMESRC.
+#define BF_SIM_SOPT2_TIMESRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TIMESRC), uint32_t) & BM_SIM_SOPT2_TIMESRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMESRC field to a new value.
+#define BW_SIM_SOPT2_TIMESRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 00 - Core/system clock.
+ * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 10 - OSCERCLK clock
+ * - 11 - External bypass clock (SDHC0_CLKIN)
+ */
+//@{
+#define BP_SIM_SOPT2_SDHCSRC (28U)         //!< Bit position for SIM_SOPT2_SDHCSRC.
+#define BM_SIM_SOPT2_SDHCSRC (0x30000000U) //!< Bit mask for SIM_SOPT2_SDHCSRC.
+#define BS_SIM_SOPT2_SDHCSRC (2U)          //!< Bit field size in bits for SIM_SOPT2_SDHCSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_SDHCSRC field.
+#define BR_SIM_SOPT2_SDHCSRC (HW_SIM_SOPT2.B.SDHCSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_SDHCSRC.
+#define BF_SIM_SOPT2_SDHCSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_SDHCSRC), uint32_t) & BM_SIM_SOPT2_SDHCSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDHCSRC field to a new value.
+#define BW_SIM_SOPT2_SDHCSRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT4 - System Options Register 4
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_sopt4
+{
+    uint32_t U;
+    struct _hw_sim_sopt4_bitfields
+    {
+        uint32_t FTM0FLT0 : 1;         //!< [0] FTM0 Fault 0 Select
+        uint32_t FTM0FLT1 : 1;         //!< [1] FTM0 Fault 1 Select
+        uint32_t FTM0FLT2 : 1;         //!< [2] FTM0 Fault 2 Select
+        uint32_t RESERVED0 : 1;        //!< [3]
+        uint32_t FTM1FLT0 : 1;         //!< [4] FTM1 Fault 0 Select
+        uint32_t RESERVED1 : 3;        //!< [7:5]
+        uint32_t FTM2FLT0 : 1;         //!< [8] FTM2 Fault 0 Select
+        uint32_t RESERVED2 : 3;        //!< [11:9]
+        uint32_t FTM3FLT0 : 1;         //!< [12] FTM3 Fault 0 Select
+        uint32_t RESERVED3 : 5;        //!< [17:13]
+        uint32_t FTM1CH0SRC : 2;       //!< [19:18] FTM1 channel 0 input capture
+                                       //! source select
+        uint32_t FTM2CH0SRC : 2;       //!< [21:20] FTM2 channel 0 input capture
+                                       //! source select
+        uint32_t RESERVED4 : 2;        //!< [23:22]
+        uint32_t FTM0CLKSEL : 1;       //!< [24] FlexTimer 0 External Clock Pin
+                                       //! Select
+        uint32_t FTM1CLKSEL : 1;       //!< [25] FTM1 External Clock Pin Select
+        uint32_t FTM2CLKSEL : 1;       //!< [26] FlexTimer 2 External Clock Pin
+                                       //! Select
+        uint32_t FTM3CLKSEL : 1;       //!< [27] FlexTimer 3 External Clock Pin
+                                       //! Select
+        uint32_t FTM0TRG0SRC : 1;      //!< [28] FlexTimer 0 Hardware Trigger 0
+                                       //! Source Select
+        uint32_t FTM0TRG1SRC : 1;      //!< [29] FlexTimer 0 Hardware Trigger 1
+                                       //! Source Select
+        uint32_t FTM3TRG0SRC : 1;      //!< [30] FlexTimer 3 Hardware Trigger 0
+                                       //! Source Select
+        uint32_t FTM3TRG1SRC : 1;      //!< [31] FlexTimer 3 Hardware Trigger 1
+                                       //! Source Select
+    } B;
+} hw_sim_sopt4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+//@{
+#define HW_SIM_SOPT4_ADDR        (REGS_SIM_BASE + 0x100CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT4             (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR)
+#define HW_SIM_SOPT4_RD()        (HW_SIM_SOPT4.U)
+#define HW_SIM_SOPT4_WR(v)       (HW_SIM_SOPT4.U = (v))
+#define HW_SIM_SOPT4_SET(v)      (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() |  (v)))
+#define HW_SIM_SOPT4_CLR(v)      (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() & ~(v)))
+#define HW_SIM_SOPT4_TOG(v)      (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM0_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0FLT0 (0U)         //!< Bit position for SIM_SOPT4_FTM0FLT0.
+#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) //!< Bit mask for SIM_SOPT4_FTM0FLT0.
+#define BS_SIM_SOPT4_FTM0FLT0 (1U)         //!< Bit field size in bits for SIM_SOPT4_FTM0FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field.
+#define BR_SIM_SOPT4_FTM0FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0.
+#define BF_SIM_SOPT4_FTM0FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT0), uint32_t) & BM_SIM_SOPT4_FTM0FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM0FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM0_FLT1 pin
+ * - 1 - CMP1 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0FLT1 (1U)         //!< Bit position for SIM_SOPT4_FTM0FLT1.
+#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) //!< Bit mask for SIM_SOPT4_FTM0FLT1.
+#define BS_SIM_SOPT4_FTM0FLT1 (1U)         //!< Bit field size in bits for SIM_SOPT4_FTM0FLT1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field.
+#define BR_SIM_SOPT4_FTM0FLT1 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1.
+#define BF_SIM_SOPT4_FTM0FLT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT1), uint32_t) & BM_SIM_SOPT4_FTM0FLT1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0FLT1 field to a new value.
+#define BW_SIM_SOPT4_FTM0FLT1(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM0_FLT2 pin
+ * - 1 - CMP2 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0FLT2 (2U)         //!< Bit position for SIM_SOPT4_FTM0FLT2.
+#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) //!< Bit mask for SIM_SOPT4_FTM0FLT2.
+#define BS_SIM_SOPT4_FTM0FLT2 (1U)         //!< Bit field size in bits for SIM_SOPT4_FTM0FLT2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field.
+#define BR_SIM_SOPT4_FTM0FLT2 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2.
+#define BF_SIM_SOPT4_FTM0FLT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT2), uint32_t) & BM_SIM_SOPT4_FTM0FLT2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0FLT2 field to a new value.
+#define BW_SIM_SOPT4_FTM0FLT2(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM1_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM1FLT0 (4U)         //!< Bit position for SIM_SOPT4_FTM1FLT0.
+#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) //!< Bit mask for SIM_SOPT4_FTM1FLT0.
+#define BS_SIM_SOPT4_FTM1FLT0 (1U)         //!< Bit field size in bits for SIM_SOPT4_FTM1FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field.
+#define BR_SIM_SOPT4_FTM1FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0.
+#define BF_SIM_SOPT4_FTM1FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1FLT0), uint32_t) & BM_SIM_SOPT4_FTM1FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM1FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0 - FTM2_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM2FLT0 (8U)         //!< Bit position for SIM_SOPT4_FTM2FLT0.
+#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) //!< Bit mask for SIM_SOPT4_FTM2FLT0.
+#define BS_SIM_SOPT4_FTM2FLT0 (1U)         //!< Bit field size in bits for SIM_SOPT4_FTM2FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field.
+#define BR_SIM_SOPT4_FTM2FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0.
+#define BF_SIM_SOPT4_FTM2FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2FLT0), uint32_t) & BM_SIM_SOPT4_FTM2FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM2FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0 - FTM3_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3FLT0 (12U)        //!< Bit position for SIM_SOPT4_FTM3FLT0.
+#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) //!< Bit mask for SIM_SOPT4_FTM3FLT0.
+#define BS_SIM_SOPT4_FTM3FLT0 (1U)         //!< Bit field size in bits for SIM_SOPT4_FTM3FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field.
+#define BR_SIM_SOPT4_FTM3FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0.
+#define BF_SIM_SOPT4_FTM3FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3FLT0), uint32_t) & BM_SIM_SOPT4_FTM3FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM3FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 00 - FTM1_CH0 signal
+ * - 01 - CMP0 output
+ * - 10 - CMP1 output
+ * - 11 - USB start of frame pulse
+ */
+//@{
+#define BP_SIM_SOPT4_FTM1CH0SRC (18U)      //!< Bit position for SIM_SOPT4_FTM1CH0SRC.
+#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) //!< Bit mask for SIM_SOPT4_FTM1CH0SRC.
+#define BS_SIM_SOPT4_FTM1CH0SRC (2U)       //!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field.
+#define BR_SIM_SOPT4_FTM1CH0SRC (HW_SIM_SOPT4.B.FTM1CH0SRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC.
+#define BF_SIM_SOPT4_FTM1CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM1CH0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1CH0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM1CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 00 - FTM2_CH0 signal
+ * - 01 - CMP0 output
+ * - 10 - CMP1 output
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT4_FTM2CH0SRC (20U)      //!< Bit position for SIM_SOPT4_FTM2CH0SRC.
+#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) //!< Bit mask for SIM_SOPT4_FTM2CH0SRC.
+#define BS_SIM_SOPT4_FTM2CH0SRC (2U)       //!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field.
+#define BR_SIM_SOPT4_FTM2CH0SRC (HW_SIM_SOPT4.B.FTM2CH0SRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC.
+#define BF_SIM_SOPT4_FTM2CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM2CH0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2CH0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM2CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM_CLK0 pin
+ * - 1 - FTM_CLK1 pin
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0CLKSEL (24U)      //!< Bit position for SIM_SOPT4_FTM0CLKSEL.
+#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) //!< Bit mask for SIM_SOPT4_FTM0CLKSEL.
+#define BS_SIM_SOPT4_FTM0CLKSEL (1U)       //!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field.
+#define BR_SIM_SOPT4_FTM0CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL.
+#define BF_SIM_SOPT4_FTM0CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM0CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM0CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM_CLK0 pin
+ * - 1 - FTM_CLK1 pin
+ */
+//@{
+#define BP_SIM_SOPT4_FTM1CLKSEL (25U)      //!< Bit position for SIM_SOPT4_FTM1CLKSEL.
+#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) //!< Bit mask for SIM_SOPT4_FTM1CLKSEL.
+#define BS_SIM_SOPT4_FTM1CLKSEL (1U)       //!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field.
+#define BR_SIM_SOPT4_FTM1CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL.
+#define BF_SIM_SOPT4_FTM1CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM1CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM1CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+//@{
+#define BP_SIM_SOPT4_FTM2CLKSEL (26U)      //!< Bit position for SIM_SOPT4_FTM2CLKSEL.
+#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) //!< Bit mask for SIM_SOPT4_FTM2CLKSEL.
+#define BS_SIM_SOPT4_FTM2CLKSEL (1U)       //!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field.
+#define BR_SIM_SOPT4_FTM2CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL.
+#define BF_SIM_SOPT4_FTM2CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM2CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM2CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3CLKSEL (27U)      //!< Bit position for SIM_SOPT4_FTM3CLKSEL.
+#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) //!< Bit mask for SIM_SOPT4_FTM3CLKSEL.
+#define BS_SIM_SOPT4_FTM3CLKSEL (1U)       //!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field.
+#define BR_SIM_SOPT4_FTM3CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL.
+#define BF_SIM_SOPT4_FTM3CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM3CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM3CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0TRG0SRC (28U)     //!< Bit position for SIM_SOPT4_FTM0TRG0SRC.
+#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG0SRC.
+#define BS_SIM_SOPT4_FTM0TRG0SRC (1U)      //!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field.
+#define BR_SIM_SOPT4_FTM0TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC.
+#define BF_SIM_SOPT4_FTM0TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0TRG0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM0TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0TRG1SRC (29U)     //!< Bit position for SIM_SOPT4_FTM0TRG1SRC.
+#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG1SRC.
+#define BS_SIM_SOPT4_FTM0TRG1SRC (1U)      //!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field.
+#define BR_SIM_SOPT4_FTM0TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC.
+#define BF_SIM_SOPT4_FTM0TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG1SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0TRG1SRC field to a new value.
+#define BW_SIM_SOPT4_FTM0TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0 - Reserved
+ * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3TRG0SRC (30U)     //!< Bit position for SIM_SOPT4_FTM3TRG0SRC.
+#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG0SRC.
+#define BS_SIM_SOPT4_FTM3TRG0SRC (1U)      //!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field.
+#define BR_SIM_SOPT4_FTM3TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC.
+#define BF_SIM_SOPT4_FTM3TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3TRG0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM3TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0 - Reserved
+ * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3TRG1SRC (31U)     //!< Bit position for SIM_SOPT4_FTM3TRG1SRC.
+#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG1SRC.
+#define BS_SIM_SOPT4_FTM3TRG1SRC (1U)      //!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field.
+#define BR_SIM_SOPT4_FTM3TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC.
+#define BF_SIM_SOPT4_FTM3TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG1SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3TRG1SRC field to a new value.
+#define BW_SIM_SOPT4_FTM3TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT5 - System Options Register 5
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_sopt5
+{
+    uint32_t U;
+    struct _hw_sim_sopt5_bitfields
+    {
+        uint32_t UART0TXSRC : 2;       //!< [1:0] UART 0 transmit data source select
+        uint32_t UART0RXSRC : 2;       //!< [3:2] UART 0 receive data source select
+        uint32_t UART1TXSRC : 2;       //!< [5:4] UART 1 transmit data source select
+        uint32_t UART1RXSRC : 2;       //!< [7:6] UART 1 receive data source select
+        uint32_t RESERVED0 : 24;       //!< [31:8]
+    } B;
+} hw_sim_sopt5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+//@{
+#define HW_SIM_SOPT5_ADDR        (REGS_SIM_BASE + 0x1010U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT5             (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR)
+#define HW_SIM_SOPT5_RD()        (HW_SIM_SOPT5.U)
+#define HW_SIM_SOPT5_WR(v)       (HW_SIM_SOPT5.U = (v))
+#define HW_SIM_SOPT5_SET(v)      (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() |  (v)))
+#define HW_SIM_SOPT5_CLR(v)      (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() & ~(v)))
+#define HW_SIM_SOPT5_TOG(v)      (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 00 - UART0_TX pin
+ * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART0TXSRC (0U)       //!< Bit position for SIM_SOPT5_UART0TXSRC.
+#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) //!< Bit mask for SIM_SOPT5_UART0TXSRC.
+#define BS_SIM_SOPT5_UART0TXSRC (2U)       //!< Bit field size in bits for SIM_SOPT5_UART0TXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART0TXSRC field.
+#define BR_SIM_SOPT5_UART0TXSRC (HW_SIM_SOPT5.B.UART0TXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC.
+#define BF_SIM_SOPT5_UART0TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0TXSRC), uint32_t) & BM_SIM_SOPT5_UART0TXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART0TXSRC field to a new value.
+#define BW_SIM_SOPT5_UART0TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 00 - UART0_RX pin
+ * - 01 - CMP0
+ * - 10 - CMP1
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART0RXSRC (2U)       //!< Bit position for SIM_SOPT5_UART0RXSRC.
+#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) //!< Bit mask for SIM_SOPT5_UART0RXSRC.
+#define BS_SIM_SOPT5_UART0RXSRC (2U)       //!< Bit field size in bits for SIM_SOPT5_UART0RXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART0RXSRC field.
+#define BR_SIM_SOPT5_UART0RXSRC (HW_SIM_SOPT5.B.UART0RXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC.
+#define BF_SIM_SOPT5_UART0RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0RXSRC), uint32_t) & BM_SIM_SOPT5_UART0RXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART0RXSRC field to a new value.
+#define BW_SIM_SOPT5_UART0RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 00 - UART1_TX pin
+ * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART1TXSRC (4U)       //!< Bit position for SIM_SOPT5_UART1TXSRC.
+#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) //!< Bit mask for SIM_SOPT5_UART1TXSRC.
+#define BS_SIM_SOPT5_UART1TXSRC (2U)       //!< Bit field size in bits for SIM_SOPT5_UART1TXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART1TXSRC field.
+#define BR_SIM_SOPT5_UART1TXSRC (HW_SIM_SOPT5.B.UART1TXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC.
+#define BF_SIM_SOPT5_UART1TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1TXSRC), uint32_t) & BM_SIM_SOPT5_UART1TXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART1TXSRC field to a new value.
+#define BW_SIM_SOPT5_UART1TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 00 - UART1_RX pin
+ * - 01 - CMP0
+ * - 10 - CMP1
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART1RXSRC (6U)       //!< Bit position for SIM_SOPT5_UART1RXSRC.
+#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) //!< Bit mask for SIM_SOPT5_UART1RXSRC.
+#define BS_SIM_SOPT5_UART1RXSRC (2U)       //!< Bit field size in bits for SIM_SOPT5_UART1RXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART1RXSRC field.
+#define BR_SIM_SOPT5_UART1RXSRC (HW_SIM_SOPT5.B.UART1RXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC.
+#define BF_SIM_SOPT5_UART1RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1RXSRC), uint32_t) & BM_SIM_SOPT5_UART1RXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART1RXSRC field to a new value.
+#define BW_SIM_SOPT5_UART1RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT7 - System Options Register 7
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_sopt7
+{
+    uint32_t U;
+    struct _hw_sim_sopt7_bitfields
+    {
+        uint32_t ADC0TRGSEL : 4;       //!< [3:0] ADC0 trigger select
+        uint32_t ADC0PRETRGSEL : 1;    //!< [4] ADC0 pretrigger select
+        uint32_t RESERVED0 : 2;        //!< [6:5]
+        uint32_t ADC0ALTTRGEN : 1;     //!< [7] ADC0 alternate trigger enable
+        uint32_t ADC1TRGSEL : 4;       //!< [11:8] ADC1 trigger select
+        uint32_t ADC1PRETRGSEL : 1;    //!< [12] ADC1 pre-trigger select
+        uint32_t RESERVED1 : 2;        //!< [14:13]
+        uint32_t ADC1ALTTRGEN : 1;     //!< [15] ADC1 alternate trigger enable
+        uint32_t RESERVED2 : 16;       //!< [31:16]
+    } B;
+} hw_sim_sopt7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+//@{
+#define HW_SIM_SOPT7_ADDR        (REGS_SIM_BASE + 0x1018U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT7             (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR)
+#define HW_SIM_SOPT7_RD()        (HW_SIM_SOPT7.U)
+#define HW_SIM_SOPT7_WR(v)       (HW_SIM_SOPT7.U = (v))
+#define HW_SIM_SOPT7_SET(v)      (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() |  (v)))
+#define HW_SIM_SOPT7_CLR(v)      (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() & ~(v)))
+#define HW_SIM_SOPT7_TOG(v)      (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0001 - High speed comparator 0 output
+ * - 0010 - High speed comparator 1 output
+ * - 0011 - High speed comparator 2 output
+ * - 0100 - PIT trigger 0
+ * - 0101 - PIT trigger 1
+ * - 0110 - PIT trigger 2
+ * - 0111 - PIT trigger 3
+ * - 1000 - FTM0 trigger
+ * - 1001 - FTM1 trigger
+ * - 1010 - FTM2 trigger
+ * - 1011 - FTM3 trigger
+ * - 1100 - RTC alarm
+ * - 1101 - RTC seconds
+ * - 1110 - Low-power timer (LPTMR) trigger
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT7_ADC0TRGSEL (0U)       //!< Bit position for SIM_SOPT7_ADC0TRGSEL.
+#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) //!< Bit mask for SIM_SOPT7_ADC0TRGSEL.
+#define BS_SIM_SOPT7_ADC0TRGSEL (4U)       //!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field.
+#define BR_SIM_SOPT7_ADC0TRGSEL (HW_SIM_SOPT7.B.ADC0TRGSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL.
+#define BF_SIM_SOPT7_ADC0TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0TRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0TRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC0TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0 - Pre-trigger A
+ * - 1 - Pre-trigger B
+ */
+//@{
+#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U)    //!< Bit position for SIM_SOPT7_ADC0PRETRGSEL.
+#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) //!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL.
+#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U)    //!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field.
+#define BR_SIM_SOPT7_ADC0PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL.
+#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0PRETRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0PRETRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC0PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0 - PDB trigger selected for ADC0.
+ * - 1 - Alternate trigger selected for ADC0.
+ */
+//@{
+#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U)     //!< Bit position for SIM_SOPT7_ADC0ALTTRGEN.
+#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) //!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN.
+#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U)     //!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field.
+#define BR_SIM_SOPT7_ADC0ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN.
+#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC0ALTTRGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0ALTTRGEN field to a new value.
+#define BW_SIM_SOPT7_ADC0ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0001 - High speed comparator 0 output
+ * - 0010 - High speed comparator 1 output
+ * - 0011 - High speed comparator 2 output
+ * - 0100 - PIT trigger 0
+ * - 0101 - PIT trigger 1
+ * - 0110 - PIT trigger 2
+ * - 0111 - PIT trigger 3
+ * - 1000 - FTM0 trigger
+ * - 1001 - FTM1 trigger
+ * - 1010 - FTM2 trigger
+ * - 1011 - FTM3 trigger
+ * - 1100 - RTC alarm
+ * - 1101 - RTC seconds
+ * - 1110 - Low-power timer (LPTMR) trigger
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT7_ADC1TRGSEL (8U)       //!< Bit position for SIM_SOPT7_ADC1TRGSEL.
+#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) //!< Bit mask for SIM_SOPT7_ADC1TRGSEL.
+#define BS_SIM_SOPT7_ADC1TRGSEL (4U)       //!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field.
+#define BR_SIM_SOPT7_ADC1TRGSEL (HW_SIM_SOPT7.B.ADC1TRGSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL.
+#define BF_SIM_SOPT7_ADC1TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1TRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1TRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC1TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0 - Pre-trigger A selected for ADC1.
+ * - 1 - Pre-trigger B selected for ADC1.
+ */
+//@{
+#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U)   //!< Bit position for SIM_SOPT7_ADC1PRETRGSEL.
+#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) //!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL.
+#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U)    //!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field.
+#define BR_SIM_SOPT7_ADC1PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL.
+#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1PRETRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1PRETRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC1PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0 - PDB trigger selected for ADC1
+ * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+//@{
+#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U)    //!< Bit position for SIM_SOPT7_ADC1ALTTRGEN.
+#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) //!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN.
+#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U)     //!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field.
+#define BR_SIM_SOPT7_ADC1ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN.
+#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC1ALTTRGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1ALTTRGEN field to a new value.
+#define BW_SIM_SOPT7_ADC1ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SDID - System Device Identification Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+typedef union _hw_sim_sdid
+{
+    uint32_t U;
+    struct _hw_sim_sdid_bitfields
+    {
+        uint32_t PINID : 4;            //!< [3:0] Pincount identification
+        uint32_t FAMID : 3;            //!< [6:4] Kinetis family identification
+        uint32_t DIEID : 5;            //!< [11:7] Device Die ID
+        uint32_t REVID : 4;            //!< [15:12] Device revision number
+        uint32_t RESERVED0 : 4;        //!< [19:16]
+        uint32_t SERIESID : 4;         //!< [23:20] Kinetis Series ID
+        uint32_t SUBFAMID : 4;         //!< [27:24] Kinetis Sub-Family ID
+        uint32_t FAMILYID : 4;         //!< [31:28] Kinetis Family ID
+    } B;
+} hw_sim_sdid_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+//@{
+#define HW_SIM_SDID_ADDR         (REGS_SIM_BASE + 0x1024U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SDID              (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR)
+#define HW_SIM_SDID_RD()         (HW_SIM_SDID.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0000 - Reserved
+ * - 0001 - Reserved
+ * - 0010 - 32-pin
+ * - 0011 - Reserved
+ * - 0100 - 48-pin
+ * - 0101 - 64-pin
+ * - 0110 - 80-pin
+ * - 0111 - 81-pin or 121-pin
+ * - 1000 - 100-pin
+ * - 1001 - 121-pin
+ * - 1010 - 144-pin
+ * - 1011 - Custom pinout (WLCSP)
+ * - 1100 - 169-pin
+ * - 1101 - Reserved
+ * - 1110 - 256-pin
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SIM_SDID_PINID    (0U)          //!< Bit position for SIM_SDID_PINID.
+#define BM_SIM_SDID_PINID    (0x0000000FU) //!< Bit mask for SIM_SDID_PINID.
+#define BS_SIM_SDID_PINID    (4U)          //!< Bit field size in bits for SIM_SDID_PINID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_PINID field.
+#define BR_SIM_SDID_PINID    (HW_SIM_SDID.B.PINID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 000 - K1x Family (without tamper)
+ * - 001 - K2x Family (without tamper)
+ * - 010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 011 - K4x Family or K2x Family (with tamper)
+ * - 100 - K6x Family (without tamper)
+ * - 101 - K7x Family
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SIM_SDID_FAMID    (4U)          //!< Bit position for SIM_SDID_FAMID.
+#define BM_SIM_SDID_FAMID    (0x00000070U) //!< Bit mask for SIM_SDID_FAMID.
+#define BS_SIM_SDID_FAMID    (3U)          //!< Bit field size in bits for SIM_SDID_FAMID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_FAMID field.
+#define BR_SIM_SDID_FAMID    (HW_SIM_SDID.B.FAMID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+//@{
+#define BP_SIM_SDID_DIEID    (7U)          //!< Bit position for SIM_SDID_DIEID.
+#define BM_SIM_SDID_DIEID    (0x00000F80U) //!< Bit mask for SIM_SDID_DIEID.
+#define BS_SIM_SDID_DIEID    (5U)          //!< Bit field size in bits for SIM_SDID_DIEID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_DIEID field.
+#define BR_SIM_SDID_DIEID    (HW_SIM_SDID.B.DIEID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+//@{
+#define BP_SIM_SDID_REVID    (12U)         //!< Bit position for SIM_SDID_REVID.
+#define BM_SIM_SDID_REVID    (0x0000F000U) //!< Bit mask for SIM_SDID_REVID.
+#define BS_SIM_SDID_REVID    (4U)          //!< Bit field size in bits for SIM_SDID_REVID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_REVID field.
+#define BR_SIM_SDID_REVID    (HW_SIM_SDID.B.REVID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0000 - Kinetis K series
+ * - 0001 - Kinetis L series
+ * - 0101 - Kinetis W series
+ * - 0110 - Kinetis V series
+ */
+//@{
+#define BP_SIM_SDID_SERIESID (20U)         //!< Bit position for SIM_SDID_SERIESID.
+#define BM_SIM_SDID_SERIESID (0x00F00000U) //!< Bit mask for SIM_SDID_SERIESID.
+#define BS_SIM_SDID_SERIESID (4U)          //!< Bit field size in bits for SIM_SDID_SERIESID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_SERIESID field.
+#define BR_SIM_SDID_SERIESID (HW_SIM_SDID.B.SERIESID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0000 - Kx0 Subfamily
+ * - 0001 - Kx1 Subfamily (tamper detect)
+ * - 0010 - Kx2 Subfamily
+ * - 0011 - Kx3 Subfamily (tamper detect)
+ * - 0100 - Kx4 Subfamily
+ * - 0101 - Kx5 Subfamily (tamper detect)
+ * - 0110 - Kx6 Subfamily
+ */
+//@{
+#define BP_SIM_SDID_SUBFAMID (24U)         //!< Bit position for SIM_SDID_SUBFAMID.
+#define BM_SIM_SDID_SUBFAMID (0x0F000000U) //!< Bit mask for SIM_SDID_SUBFAMID.
+#define BS_SIM_SDID_SUBFAMID (4U)          //!< Bit field size in bits for SIM_SDID_SUBFAMID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_SUBFAMID field.
+#define BR_SIM_SDID_SUBFAMID (HW_SIM_SDID.B.SUBFAMID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0001 - K1x Family
+ * - 0010 - K2x Family
+ * - 0011 - K3x Family
+ * - 0100 - K4x Family
+ * - 0110 - K6x Family
+ * - 0111 - K7x Family
+ */
+//@{
+#define BP_SIM_SDID_FAMILYID (28U)         //!< Bit position for SIM_SDID_FAMILYID.
+#define BM_SIM_SDID_FAMILYID (0xF0000000U) //!< Bit mask for SIM_SDID_FAMILYID.
+#define BS_SIM_SDID_FAMILYID (4U)          //!< Bit field size in bits for SIM_SDID_FAMILYID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_FAMILYID field.
+#define BR_SIM_SDID_FAMILYID (HW_SIM_SDID.B.FAMILYID)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC1 - System Clock Gating Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_scgc1
+{
+    uint32_t U;
+    struct _hw_sim_scgc1_bitfields
+    {
+        uint32_t RESERVED0 : 6;        //!< [5:0]
+        uint32_t I2C2b : 1;            //!< [6] I2C2 Clock Gate Control
+        uint32_t RESERVED1 : 3;        //!< [9:7]
+        uint32_t UART4b : 1;           //!< [10] UART4 Clock Gate Control
+        uint32_t UART5b : 1;           //!< [11] UART5 Clock Gate Control
+        uint32_t RESERVED2 : 20;       //!< [31:12]
+    } B;
+} hw_sim_scgc1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+//@{
+#define HW_SIM_SCGC1_ADDR        (REGS_SIM_BASE + 0x1028U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC1             (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR)
+#define HW_SIM_SCGC1_RD()        (HW_SIM_SCGC1.U)
+#define HW_SIM_SCGC1_WR(v)       (HW_SIM_SCGC1.U = (v))
+#define HW_SIM_SCGC1_SET(v)      (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() |  (v)))
+#define HW_SIM_SCGC1_CLR(v)      (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() & ~(v)))
+#define HW_SIM_SCGC1_TOG(v)      (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC1_I2C2    (6U)          //!< Bit position for SIM_SCGC1_I2C2.
+#define BM_SIM_SCGC1_I2C2    (0x00000040U) //!< Bit mask for SIM_SCGC1_I2C2.
+#define BS_SIM_SCGC1_I2C2    (1U)          //!< Bit field size in bits for SIM_SCGC1_I2C2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC1_I2C2 field.
+#define BR_SIM_SCGC1_I2C2    (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC1_I2C2.
+#define BF_SIM_SCGC1_I2C2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_I2C2), uint32_t) & BM_SIM_SCGC1_I2C2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2C2 field to a new value.
+#define BW_SIM_SCGC1_I2C2(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC1_UART4   (10U)         //!< Bit position for SIM_SCGC1_UART4.
+#define BM_SIM_SCGC1_UART4   (0x00000400U) //!< Bit mask for SIM_SCGC1_UART4.
+#define BS_SIM_SCGC1_UART4   (1U)          //!< Bit field size in bits for SIM_SCGC1_UART4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC1_UART4 field.
+#define BR_SIM_SCGC1_UART4   (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC1_UART4.
+#define BF_SIM_SCGC1_UART4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART4), uint32_t) & BM_SIM_SCGC1_UART4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART4 field to a new value.
+#define BW_SIM_SCGC1_UART4(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC1_UART5   (11U)         //!< Bit position for SIM_SCGC1_UART5.
+#define BM_SIM_SCGC1_UART5   (0x00000800U) //!< Bit mask for SIM_SCGC1_UART5.
+#define BS_SIM_SCGC1_UART5   (1U)          //!< Bit field size in bits for SIM_SCGC1_UART5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC1_UART5 field.
+#define BR_SIM_SCGC1_UART5   (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC1_UART5.
+#define BF_SIM_SCGC1_UART5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART5), uint32_t) & BM_SIM_SCGC1_UART5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART5 field to a new value.
+#define BW_SIM_SCGC1_UART5(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC2 - System Clock Gating Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+typedef union _hw_sim_scgc2
+{
+    uint32_t U;
+    struct _hw_sim_scgc2_bitfields
+    {
+        uint32_t ENETb : 1;            //!< [0] ENET Clock Gate Control
+        uint32_t RESERVED0 : 11;       //!< [11:1]
+        uint32_t DAC0b : 1;            //!< [12] DAC0 Clock Gate Control
+        uint32_t DAC1b : 1;            //!< [13] DAC1 Clock Gate Control
+        uint32_t RESERVED1 : 18;       //!< [31:14]
+    } B;
+} hw_sim_scgc2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+//@{
+#define HW_SIM_SCGC2_ADDR        (REGS_SIM_BASE + 0x102CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC2             (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR)
+#define HW_SIM_SCGC2_RD()        (HW_SIM_SCGC2.U)
+#define HW_SIM_SCGC2_WR(v)       (HW_SIM_SCGC2.U = (v))
+#define HW_SIM_SCGC2_SET(v)      (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() |  (v)))
+#define HW_SIM_SCGC2_CLR(v)      (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() & ~(v)))
+#define HW_SIM_SCGC2_TOG(v)      (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC2_ENET    (0U)          //!< Bit position for SIM_SCGC2_ENET.
+#define BM_SIM_SCGC2_ENET    (0x00000001U) //!< Bit mask for SIM_SCGC2_ENET.
+#define BS_SIM_SCGC2_ENET    (1U)          //!< Bit field size in bits for SIM_SCGC2_ENET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC2_ENET field.
+#define BR_SIM_SCGC2_ENET    (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC2_ENET.
+#define BF_SIM_SCGC2_ENET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_ENET), uint32_t) & BM_SIM_SCGC2_ENET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENET field to a new value.
+#define BW_SIM_SCGC2_ENET(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC2_DAC0    (12U)         //!< Bit position for SIM_SCGC2_DAC0.
+#define BM_SIM_SCGC2_DAC0    (0x00001000U) //!< Bit mask for SIM_SCGC2_DAC0.
+#define BS_SIM_SCGC2_DAC0    (1U)          //!< Bit field size in bits for SIM_SCGC2_DAC0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC2_DAC0 field.
+#define BR_SIM_SCGC2_DAC0    (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC2_DAC0.
+#define BF_SIM_SCGC2_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC0), uint32_t) & BM_SIM_SCGC2_DAC0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DAC0 field to a new value.
+#define BW_SIM_SCGC2_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC2_DAC1    (13U)         //!< Bit position for SIM_SCGC2_DAC1.
+#define BM_SIM_SCGC2_DAC1    (0x00002000U) //!< Bit mask for SIM_SCGC2_DAC1.
+#define BS_SIM_SCGC2_DAC1    (1U)          //!< Bit field size in bits for SIM_SCGC2_DAC1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC2_DAC1 field.
+#define BR_SIM_SCGC2_DAC1    (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC2_DAC1.
+#define BF_SIM_SCGC2_DAC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC1), uint32_t) & BM_SIM_SCGC2_DAC1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DAC1 field to a new value.
+#define BW_SIM_SCGC2_DAC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC3 - System Clock Gating Control Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+typedef union _hw_sim_scgc3
+{
+    uint32_t U;
+    struct _hw_sim_scgc3_bitfields
+    {
+        uint32_t RNGA : 1;             //!< [0] RNGA Clock Gate Control
+        uint32_t RESERVED0 : 11;       //!< [11:1]
+        uint32_t SPI2b : 1;            //!< [12] SPI2 Clock Gate Control
+        uint32_t RESERVED1 : 4;        //!< [16:13]
+        uint32_t SDHCb : 1;            //!< [17] SDHC Clock Gate Control
+        uint32_t RESERVED2 : 6;        //!< [23:18]
+        uint32_t FTM2b : 1;            //!< [24] FTM2 Clock Gate Control
+        uint32_t FTM3b : 1;            //!< [25] FTM3 Clock Gate Control
+        uint32_t RESERVED3 : 1;        //!< [26]
+        uint32_t ADC1b : 1;            //!< [27] ADC1 Clock Gate Control
+        uint32_t RESERVED4 : 4;        //!< [31:28]
+    } B;
+} hw_sim_scgc3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+//@{
+#define HW_SIM_SCGC3_ADDR        (REGS_SIM_BASE + 0x1030U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC3             (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR)
+#define HW_SIM_SCGC3_RD()        (HW_SIM_SCGC3.U)
+#define HW_SIM_SCGC3_WR(v)       (HW_SIM_SCGC3.U = (v))
+#define HW_SIM_SCGC3_SET(v)      (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() |  (v)))
+#define HW_SIM_SCGC3_CLR(v)      (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() & ~(v)))
+#define HW_SIM_SCGC3_TOG(v)      (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_RNGA    (0U)          //!< Bit position for SIM_SCGC3_RNGA.
+#define BM_SIM_SCGC3_RNGA    (0x00000001U) //!< Bit mask for SIM_SCGC3_RNGA.
+#define BS_SIM_SCGC3_RNGA    (1U)          //!< Bit field size in bits for SIM_SCGC3_RNGA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_RNGA field.
+#define BR_SIM_SCGC3_RNGA    (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_RNGA.
+#define BF_SIM_SCGC3_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_RNGA), uint32_t) & BM_SIM_SCGC3_RNGA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RNGA field to a new value.
+#define BW_SIM_SCGC3_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_SPI2    (12U)         //!< Bit position for SIM_SCGC3_SPI2.
+#define BM_SIM_SCGC3_SPI2    (0x00001000U) //!< Bit mask for SIM_SCGC3_SPI2.
+#define BS_SIM_SCGC3_SPI2    (1U)          //!< Bit field size in bits for SIM_SCGC3_SPI2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_SPI2 field.
+#define BR_SIM_SCGC3_SPI2    (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_SPI2.
+#define BF_SIM_SCGC3_SPI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SPI2), uint32_t) & BM_SIM_SCGC3_SPI2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI2 field to a new value.
+#define BW_SIM_SCGC3_SPI2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_SDHC    (17U)         //!< Bit position for SIM_SCGC3_SDHC.
+#define BM_SIM_SCGC3_SDHC    (0x00020000U) //!< Bit mask for SIM_SCGC3_SDHC.
+#define BS_SIM_SCGC3_SDHC    (1U)          //!< Bit field size in bits for SIM_SCGC3_SDHC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_SDHC field.
+#define BR_SIM_SCGC3_SDHC    (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_SDHC.
+#define BF_SIM_SCGC3_SDHC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SDHC), uint32_t) & BM_SIM_SCGC3_SDHC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDHC field to a new value.
+#define BW_SIM_SCGC3_SDHC(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_FTM2    (24U)         //!< Bit position for SIM_SCGC3_FTM2.
+#define BM_SIM_SCGC3_FTM2    (0x01000000U) //!< Bit mask for SIM_SCGC3_FTM2.
+#define BS_SIM_SCGC3_FTM2    (1U)          //!< Bit field size in bits for SIM_SCGC3_FTM2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_FTM2 field.
+#define BR_SIM_SCGC3_FTM2    (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_FTM2.
+#define BF_SIM_SCGC3_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM2), uint32_t) & BM_SIM_SCGC3_FTM2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2 field to a new value.
+#define BW_SIM_SCGC3_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_FTM3    (25U)         //!< Bit position for SIM_SCGC3_FTM3.
+#define BM_SIM_SCGC3_FTM3    (0x02000000U) //!< Bit mask for SIM_SCGC3_FTM3.
+#define BS_SIM_SCGC3_FTM3    (1U)          //!< Bit field size in bits for SIM_SCGC3_FTM3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_FTM3 field.
+#define BR_SIM_SCGC3_FTM3    (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_FTM3.
+#define BF_SIM_SCGC3_FTM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM3), uint32_t) & BM_SIM_SCGC3_FTM3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3 field to a new value.
+#define BW_SIM_SCGC3_FTM3(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_ADC1    (27U)         //!< Bit position for SIM_SCGC3_ADC1.
+#define BM_SIM_SCGC3_ADC1    (0x08000000U) //!< Bit mask for SIM_SCGC3_ADC1.
+#define BS_SIM_SCGC3_ADC1    (1U)          //!< Bit field size in bits for SIM_SCGC3_ADC1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_ADC1 field.
+#define BR_SIM_SCGC3_ADC1    (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_ADC1.
+#define BF_SIM_SCGC3_ADC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_ADC1), uint32_t) & BM_SIM_SCGC3_ADC1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1 field to a new value.
+#define BW_SIM_SCGC3_ADC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC4 - System Clock Gating Control Register 4
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+typedef union _hw_sim_scgc4
+{
+    uint32_t U;
+    struct _hw_sim_scgc4_bitfields
+    {
+        uint32_t RESERVED0 : 1;        //!< [0]
+        uint32_t EWMb : 1;             //!< [1] EWM Clock Gate Control
+        uint32_t CMTb : 1;             //!< [2] CMT Clock Gate Control
+        uint32_t RESERVED1 : 3;        //!< [5:3]
+        uint32_t I2C0b : 1;            //!< [6] I2C0 Clock Gate Control
+        uint32_t I2C1b : 1;            //!< [7] I2C1 Clock Gate Control
+        uint32_t RESERVED2 : 2;        //!< [9:8]
+        uint32_t UART0b : 1;           //!< [10] UART0 Clock Gate Control
+        uint32_t UART1b : 1;           //!< [11] UART1 Clock Gate Control
+        uint32_t UART2b : 1;           //!< [12] UART2 Clock Gate Control
+        uint32_t UART3b : 1;           //!< [13] UART3 Clock Gate Control
+        uint32_t RESERVED3 : 4;        //!< [17:14]
+        uint32_t USBOTG : 1;           //!< [18] USB Clock Gate Control
+        uint32_t CMP : 1;              //!< [19] Comparator Clock Gate Control
+        uint32_t VREFb : 1;            //!< [20] VREF Clock Gate Control
+        uint32_t RESERVED4 : 11;       //!< [31:21]
+    } B;
+} hw_sim_scgc4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+//@{
+#define HW_SIM_SCGC4_ADDR        (REGS_SIM_BASE + 0x1034U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC4             (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR)
+#define HW_SIM_SCGC4_RD()        (HW_SIM_SCGC4.U)
+#define HW_SIM_SCGC4_WR(v)       (HW_SIM_SCGC4.U = (v))
+#define HW_SIM_SCGC4_SET(v)      (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() |  (v)))
+#define HW_SIM_SCGC4_CLR(v)      (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() & ~(v)))
+#define HW_SIM_SCGC4_TOG(v)      (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_EWM     (1U)          //!< Bit position for SIM_SCGC4_EWM.
+#define BM_SIM_SCGC4_EWM     (0x00000002U) //!< Bit mask for SIM_SCGC4_EWM.
+#define BS_SIM_SCGC4_EWM     (1U)          //!< Bit field size in bits for SIM_SCGC4_EWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_EWM field.
+#define BR_SIM_SCGC4_EWM     (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_EWM.
+#define BF_SIM_SCGC4_EWM(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_EWM), uint32_t) & BM_SIM_SCGC4_EWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EWM field to a new value.
+#define BW_SIM_SCGC4_EWM(v)  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_CMT     (2U)          //!< Bit position for SIM_SCGC4_CMT.
+#define BM_SIM_SCGC4_CMT     (0x00000004U) //!< Bit mask for SIM_SCGC4_CMT.
+#define BS_SIM_SCGC4_CMT     (1U)          //!< Bit field size in bits for SIM_SCGC4_CMT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_CMT field.
+#define BR_SIM_SCGC4_CMT     (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_CMT.
+#define BF_SIM_SCGC4_CMT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMT), uint32_t) & BM_SIM_SCGC4_CMT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMT field to a new value.
+#define BW_SIM_SCGC4_CMT(v)  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_I2C0    (6U)          //!< Bit position for SIM_SCGC4_I2C0.
+#define BM_SIM_SCGC4_I2C0    (0x00000040U) //!< Bit mask for SIM_SCGC4_I2C0.
+#define BS_SIM_SCGC4_I2C0    (1U)          //!< Bit field size in bits for SIM_SCGC4_I2C0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_I2C0 field.
+#define BR_SIM_SCGC4_I2C0    (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_I2C0.
+#define BF_SIM_SCGC4_I2C0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C0), uint32_t) & BM_SIM_SCGC4_I2C0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2C0 field to a new value.
+#define BW_SIM_SCGC4_I2C0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_I2C1    (7U)          //!< Bit position for SIM_SCGC4_I2C1.
+#define BM_SIM_SCGC4_I2C1    (0x00000080U) //!< Bit mask for SIM_SCGC4_I2C1.
+#define BS_SIM_SCGC4_I2C1    (1U)          //!< Bit field size in bits for SIM_SCGC4_I2C1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_I2C1 field.
+#define BR_SIM_SCGC4_I2C1    (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_I2C1.
+#define BF_SIM_SCGC4_I2C1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C1), uint32_t) & BM_SIM_SCGC4_I2C1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2C1 field to a new value.
+#define BW_SIM_SCGC4_I2C1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART0   (10U)         //!< Bit position for SIM_SCGC4_UART0.
+#define BM_SIM_SCGC4_UART0   (0x00000400U) //!< Bit mask for SIM_SCGC4_UART0.
+#define BS_SIM_SCGC4_UART0   (1U)          //!< Bit field size in bits for SIM_SCGC4_UART0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART0 field.
+#define BR_SIM_SCGC4_UART0   (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART0.
+#define BF_SIM_SCGC4_UART0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART0), uint32_t) & BM_SIM_SCGC4_UART0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART0 field to a new value.
+#define BW_SIM_SCGC4_UART0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART1   (11U)         //!< Bit position for SIM_SCGC4_UART1.
+#define BM_SIM_SCGC4_UART1   (0x00000800U) //!< Bit mask for SIM_SCGC4_UART1.
+#define BS_SIM_SCGC4_UART1   (1U)          //!< Bit field size in bits for SIM_SCGC4_UART1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART1 field.
+#define BR_SIM_SCGC4_UART1   (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART1.
+#define BF_SIM_SCGC4_UART1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART1), uint32_t) & BM_SIM_SCGC4_UART1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART1 field to a new value.
+#define BW_SIM_SCGC4_UART1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART2   (12U)         //!< Bit position for SIM_SCGC4_UART2.
+#define BM_SIM_SCGC4_UART2   (0x00001000U) //!< Bit mask for SIM_SCGC4_UART2.
+#define BS_SIM_SCGC4_UART2   (1U)          //!< Bit field size in bits for SIM_SCGC4_UART2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART2 field.
+#define BR_SIM_SCGC4_UART2   (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART2.
+#define BF_SIM_SCGC4_UART2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART2), uint32_t) & BM_SIM_SCGC4_UART2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART2 field to a new value.
+#define BW_SIM_SCGC4_UART2(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART3   (13U)         //!< Bit position for SIM_SCGC4_UART3.
+#define BM_SIM_SCGC4_UART3   (0x00002000U) //!< Bit mask for SIM_SCGC4_UART3.
+#define BS_SIM_SCGC4_UART3   (1U)          //!< Bit field size in bits for SIM_SCGC4_UART3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART3 field.
+#define BR_SIM_SCGC4_UART3   (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART3.
+#define BF_SIM_SCGC4_UART3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART3), uint32_t) & BM_SIM_SCGC4_UART3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART3 field to a new value.
+#define BW_SIM_SCGC4_UART3(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_USBOTG  (18U)         //!< Bit position for SIM_SCGC4_USBOTG.
+#define BM_SIM_SCGC4_USBOTG  (0x00040000U) //!< Bit mask for SIM_SCGC4_USBOTG.
+#define BS_SIM_SCGC4_USBOTG  (1U)          //!< Bit field size in bits for SIM_SCGC4_USBOTG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_USBOTG field.
+#define BR_SIM_SCGC4_USBOTG  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_USBOTG.
+#define BF_SIM_SCGC4_USBOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_USBOTG), uint32_t) & BM_SIM_SCGC4_USBOTG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBOTG field to a new value.
+#define BW_SIM_SCGC4_USBOTG(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_CMP     (19U)         //!< Bit position for SIM_SCGC4_CMP.
+#define BM_SIM_SCGC4_CMP     (0x00080000U) //!< Bit mask for SIM_SCGC4_CMP.
+#define BS_SIM_SCGC4_CMP     (1U)          //!< Bit field size in bits for SIM_SCGC4_CMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_CMP field.
+#define BR_SIM_SCGC4_CMP     (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_CMP.
+#define BF_SIM_SCGC4_CMP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMP), uint32_t) & BM_SIM_SCGC4_CMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMP field to a new value.
+#define BW_SIM_SCGC4_CMP(v)  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_VREF    (20U)         //!< Bit position for SIM_SCGC4_VREF.
+#define BM_SIM_SCGC4_VREF    (0x00100000U) //!< Bit mask for SIM_SCGC4_VREF.
+#define BS_SIM_SCGC4_VREF    (1U)          //!< Bit field size in bits for SIM_SCGC4_VREF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_VREF field.
+#define BR_SIM_SCGC4_VREF    (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_VREF.
+#define BF_SIM_SCGC4_VREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_VREF), uint32_t) & BM_SIM_SCGC4_VREF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VREF field to a new value.
+#define BW_SIM_SCGC4_VREF(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC5 - System Clock Gating Control Register 5
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+typedef union _hw_sim_scgc5
+{
+    uint32_t U;
+    struct _hw_sim_scgc5_bitfields
+    {
+        uint32_t LPTMR : 1;            //!< [0] Low Power Timer Access Control
+        uint32_t RESERVED0 : 8;        //!< [8:1]
+        uint32_t PORTAb : 1;           //!< [9] Port A Clock Gate Control
+        uint32_t PORTBb : 1;           //!< [10] Port B Clock Gate Control
+        uint32_t PORTCb : 1;           //!< [11] Port C Clock Gate Control
+        uint32_t PORTDb : 1;           //!< [12] Port D Clock Gate Control
+        uint32_t PORTEb : 1;           //!< [13] Port E Clock Gate Control
+        uint32_t RESERVED1 : 18;       //!< [31:14]
+    } B;
+} hw_sim_scgc5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+//@{
+#define HW_SIM_SCGC5_ADDR        (REGS_SIM_BASE + 0x1038U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC5             (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR)
+#define HW_SIM_SCGC5_RD()        (HW_SIM_SCGC5.U)
+#define HW_SIM_SCGC5_WR(v)       (HW_SIM_SCGC5.U = (v))
+#define HW_SIM_SCGC5_SET(v)      (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() |  (v)))
+#define HW_SIM_SCGC5_CLR(v)      (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() & ~(v)))
+#define HW_SIM_SCGC5_TOG(v)      (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0 - Access disabled
+ * - 1 - Access enabled
+ */
+//@{
+#define BP_SIM_SCGC5_LPTMR   (0U)          //!< Bit position for SIM_SCGC5_LPTMR.
+#define BM_SIM_SCGC5_LPTMR   (0x00000001U) //!< Bit mask for SIM_SCGC5_LPTMR.
+#define BS_SIM_SCGC5_LPTMR   (1U)          //!< Bit field size in bits for SIM_SCGC5_LPTMR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_LPTMR field.
+#define BR_SIM_SCGC5_LPTMR   (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_LPTMR.
+#define BF_SIM_SCGC5_LPTMR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_LPTMR), uint32_t) & BM_SIM_SCGC5_LPTMR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPTMR field to a new value.
+#define BW_SIM_SCGC5_LPTMR(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTA   (9U)          //!< Bit position for SIM_SCGC5_PORTA.
+#define BM_SIM_SCGC5_PORTA   (0x00000200U) //!< Bit mask for SIM_SCGC5_PORTA.
+#define BS_SIM_SCGC5_PORTA   (1U)          //!< Bit field size in bits for SIM_SCGC5_PORTA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTA field.
+#define BR_SIM_SCGC5_PORTA   (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTA.
+#define BF_SIM_SCGC5_PORTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTA), uint32_t) & BM_SIM_SCGC5_PORTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTA field to a new value.
+#define BW_SIM_SCGC5_PORTA(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTB   (10U)         //!< Bit position for SIM_SCGC5_PORTB.
+#define BM_SIM_SCGC5_PORTB   (0x00000400U) //!< Bit mask for SIM_SCGC5_PORTB.
+#define BS_SIM_SCGC5_PORTB   (1U)          //!< Bit field size in bits for SIM_SCGC5_PORTB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTB field.
+#define BR_SIM_SCGC5_PORTB   (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTB.
+#define BF_SIM_SCGC5_PORTB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTB), uint32_t) & BM_SIM_SCGC5_PORTB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTB field to a new value.
+#define BW_SIM_SCGC5_PORTB(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTC   (11U)         //!< Bit position for SIM_SCGC5_PORTC.
+#define BM_SIM_SCGC5_PORTC   (0x00000800U) //!< Bit mask for SIM_SCGC5_PORTC.
+#define BS_SIM_SCGC5_PORTC   (1U)          //!< Bit field size in bits for SIM_SCGC5_PORTC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTC field.
+#define BR_SIM_SCGC5_PORTC   (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTC.
+#define BF_SIM_SCGC5_PORTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTC), uint32_t) & BM_SIM_SCGC5_PORTC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTC field to a new value.
+#define BW_SIM_SCGC5_PORTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTD   (12U)         //!< Bit position for SIM_SCGC5_PORTD.
+#define BM_SIM_SCGC5_PORTD   (0x00001000U) //!< Bit mask for SIM_SCGC5_PORTD.
+#define BS_SIM_SCGC5_PORTD   (1U)          //!< Bit field size in bits for SIM_SCGC5_PORTD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTD field.
+#define BR_SIM_SCGC5_PORTD   (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTD.
+#define BF_SIM_SCGC5_PORTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTD), uint32_t) & BM_SIM_SCGC5_PORTD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTD field to a new value.
+#define BW_SIM_SCGC5_PORTD(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTE   (13U)         //!< Bit position for SIM_SCGC5_PORTE.
+#define BM_SIM_SCGC5_PORTE   (0x00002000U) //!< Bit mask for SIM_SCGC5_PORTE.
+#define BS_SIM_SCGC5_PORTE   (1U)          //!< Bit field size in bits for SIM_SCGC5_PORTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTE field.
+#define BR_SIM_SCGC5_PORTE   (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTE.
+#define BF_SIM_SCGC5_PORTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTE), uint32_t) & BM_SIM_SCGC5_PORTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTE field to a new value.
+#define BW_SIM_SCGC5_PORTE(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC6 - System Clock Gating Control Register 6
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+typedef union _hw_sim_scgc6
+{
+    uint32_t U;
+    struct _hw_sim_scgc6_bitfields
+    {
+        uint32_t FTF : 1;              //!< [0] Flash Memory Clock Gate Control
+        uint32_t DMAMUXb : 1;          //!< [1] DMA Mux Clock Gate Control
+        uint32_t RESERVED0 : 2;        //!< [3:2]
+        uint32_t FLEXCAN0 : 1;         //!< [4] FlexCAN0 Clock Gate Control
+        uint32_t RESERVED1 : 4;        //!< [8:5]
+        uint32_t RNGA : 1;             //!< [9] RNGA Clock Gate Control
+        uint32_t RESERVED2 : 2;        //!< [11:10]
+        uint32_t SPI0b : 1;            //!< [12] SPI0 Clock Gate Control
+        uint32_t SPI1b : 1;            //!< [13] SPI1 Clock Gate Control
+        uint32_t RESERVED3 : 1;        //!< [14]
+        uint32_t I2S : 1;              //!< [15] I2S Clock Gate Control
+        uint32_t RESERVED4 : 2;        //!< [17:16]
+        uint32_t CRCb : 1;             //!< [18] CRC Clock Gate Control
+        uint32_t RESERVED5 : 2;        //!< [20:19]
+        uint32_t USBDCDb : 1;          //!< [21] USB DCD Clock Gate Control
+        uint32_t PDB : 1;              //!< [22] PDB Clock Gate Control
+        uint32_t PITb : 1;             //!< [23] PIT Clock Gate Control
+        uint32_t FTM0b : 1;            //!< [24] FTM0 Clock Gate Control
+        uint32_t FTM1b : 1;            //!< [25] FTM1 Clock Gate Control
+        uint32_t FTM2b : 1;            //!< [26] FTM2 Clock Gate Control
+        uint32_t ADC0b : 1;            //!< [27] ADC0 Clock Gate Control
+        uint32_t RESERVED6 : 1;        //!< [28]
+        uint32_t RTCb : 1;             //!< [29] RTC Access Control
+        uint32_t RESERVED7 : 1;        //!< [30]
+        uint32_t DAC0b : 1;            //!< [31] DAC0 Clock Gate Control
+    } B;
+} hw_sim_scgc6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+//@{
+#define HW_SIM_SCGC6_ADDR        (REGS_SIM_BASE + 0x103CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC6             (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR)
+#define HW_SIM_SCGC6_RD()        (HW_SIM_SCGC6.U)
+#define HW_SIM_SCGC6_WR(v)       (HW_SIM_SCGC6.U = (v))
+#define HW_SIM_SCGC6_SET(v)      (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() |  (v)))
+#define HW_SIM_SCGC6_CLR(v)      (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() & ~(v)))
+#define HW_SIM_SCGC6_TOG(v)      (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTF     (0U)          //!< Bit position for SIM_SCGC6_FTF.
+#define BM_SIM_SCGC6_FTF     (0x00000001U) //!< Bit mask for SIM_SCGC6_FTF.
+#define BS_SIM_SCGC6_FTF     (1U)          //!< Bit field size in bits for SIM_SCGC6_FTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTF field.
+#define BR_SIM_SCGC6_FTF     (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTF.
+#define BF_SIM_SCGC6_FTF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTF), uint32_t) & BM_SIM_SCGC6_FTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTF field to a new value.
+#define BW_SIM_SCGC6_FTF(v)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_DMAMUX  (1U)          //!< Bit position for SIM_SCGC6_DMAMUX.
+#define BM_SIM_SCGC6_DMAMUX  (0x00000002U) //!< Bit mask for SIM_SCGC6_DMAMUX.
+#define BS_SIM_SCGC6_DMAMUX  (1U)          //!< Bit field size in bits for SIM_SCGC6_DMAMUX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_DMAMUX field.
+#define BR_SIM_SCGC6_DMAMUX  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_DMAMUX.
+#define BF_SIM_SCGC6_DMAMUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DMAMUX), uint32_t) & BM_SIM_SCGC6_DMAMUX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAMUX field to a new value.
+#define BW_SIM_SCGC6_DMAMUX(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FLEXCAN0 (4U)         //!< Bit position for SIM_SCGC6_FLEXCAN0.
+#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) //!< Bit mask for SIM_SCGC6_FLEXCAN0.
+#define BS_SIM_SCGC6_FLEXCAN0 (1U)         //!< Bit field size in bits for SIM_SCGC6_FLEXCAN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field.
+#define BR_SIM_SCGC6_FLEXCAN0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0.
+#define BF_SIM_SCGC6_FLEXCAN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FLEXCAN0), uint32_t) & BM_SIM_SCGC6_FLEXCAN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLEXCAN0 field to a new value.
+#define BW_SIM_SCGC6_FLEXCAN0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+//@{
+#define BP_SIM_SCGC6_RNGA    (9U)          //!< Bit position for SIM_SCGC6_RNGA.
+#define BM_SIM_SCGC6_RNGA    (0x00000200U) //!< Bit mask for SIM_SCGC6_RNGA.
+#define BS_SIM_SCGC6_RNGA    (1U)          //!< Bit field size in bits for SIM_SCGC6_RNGA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_RNGA field.
+#define BR_SIM_SCGC6_RNGA    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_RNGA.
+#define BF_SIM_SCGC6_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RNGA), uint32_t) & BM_SIM_SCGC6_RNGA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RNGA field to a new value.
+#define BW_SIM_SCGC6_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_SPI0    (12U)         //!< Bit position for SIM_SCGC6_SPI0.
+#define BM_SIM_SCGC6_SPI0    (0x00001000U) //!< Bit mask for SIM_SCGC6_SPI0.
+#define BS_SIM_SCGC6_SPI0    (1U)          //!< Bit field size in bits for SIM_SCGC6_SPI0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_SPI0 field.
+#define BR_SIM_SCGC6_SPI0    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_SPI0.
+#define BF_SIM_SCGC6_SPI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI0), uint32_t) & BM_SIM_SCGC6_SPI0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI0 field to a new value.
+#define BW_SIM_SCGC6_SPI0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_SPI1    (13U)         //!< Bit position for SIM_SCGC6_SPI1.
+#define BM_SIM_SCGC6_SPI1    (0x00002000U) //!< Bit mask for SIM_SCGC6_SPI1.
+#define BS_SIM_SCGC6_SPI1    (1U)          //!< Bit field size in bits for SIM_SCGC6_SPI1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_SPI1 field.
+#define BR_SIM_SCGC6_SPI1    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_SPI1.
+#define BF_SIM_SCGC6_SPI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI1), uint32_t) & BM_SIM_SCGC6_SPI1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI1 field to a new value.
+#define BW_SIM_SCGC6_SPI1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_I2S     (15U)         //!< Bit position for SIM_SCGC6_I2S.
+#define BM_SIM_SCGC6_I2S     (0x00008000U) //!< Bit mask for SIM_SCGC6_I2S.
+#define BS_SIM_SCGC6_I2S     (1U)          //!< Bit field size in bits for SIM_SCGC6_I2S.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_I2S field.
+#define BR_SIM_SCGC6_I2S     (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_I2S.
+#define BF_SIM_SCGC6_I2S(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_I2S), uint32_t) & BM_SIM_SCGC6_I2S)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2S field to a new value.
+#define BW_SIM_SCGC6_I2S(v)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_CRC     (18U)         //!< Bit position for SIM_SCGC6_CRC.
+#define BM_SIM_SCGC6_CRC     (0x00040000U) //!< Bit mask for SIM_SCGC6_CRC.
+#define BS_SIM_SCGC6_CRC     (1U)          //!< Bit field size in bits for SIM_SCGC6_CRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_CRC field.
+#define BR_SIM_SCGC6_CRC     (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_CRC.
+#define BF_SIM_SCGC6_CRC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_CRC), uint32_t) & BM_SIM_SCGC6_CRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC field to a new value.
+#define BW_SIM_SCGC6_CRC(v)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_USBDCD  (21U)         //!< Bit position for SIM_SCGC6_USBDCD.
+#define BM_SIM_SCGC6_USBDCD  (0x00200000U) //!< Bit mask for SIM_SCGC6_USBDCD.
+#define BS_SIM_SCGC6_USBDCD  (1U)          //!< Bit field size in bits for SIM_SCGC6_USBDCD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_USBDCD field.
+#define BR_SIM_SCGC6_USBDCD  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_USBDCD.
+#define BF_SIM_SCGC6_USBDCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_USBDCD), uint32_t) & BM_SIM_SCGC6_USBDCD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBDCD field to a new value.
+#define BW_SIM_SCGC6_USBDCD(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_PDB     (22U)         //!< Bit position for SIM_SCGC6_PDB.
+#define BM_SIM_SCGC6_PDB     (0x00400000U) //!< Bit mask for SIM_SCGC6_PDB.
+#define BS_SIM_SCGC6_PDB     (1U)          //!< Bit field size in bits for SIM_SCGC6_PDB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_PDB field.
+#define BR_SIM_SCGC6_PDB     (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_PDB.
+#define BF_SIM_SCGC6_PDB(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PDB), uint32_t) & BM_SIM_SCGC6_PDB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDB field to a new value.
+#define BW_SIM_SCGC6_PDB(v)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_PIT     (23U)         //!< Bit position for SIM_SCGC6_PIT.
+#define BM_SIM_SCGC6_PIT     (0x00800000U) //!< Bit mask for SIM_SCGC6_PIT.
+#define BS_SIM_SCGC6_PIT     (1U)          //!< Bit field size in bits for SIM_SCGC6_PIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_PIT field.
+#define BR_SIM_SCGC6_PIT     (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_PIT.
+#define BF_SIM_SCGC6_PIT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PIT), uint32_t) & BM_SIM_SCGC6_PIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIT field to a new value.
+#define BW_SIM_SCGC6_PIT(v)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTM0    (24U)         //!< Bit position for SIM_SCGC6_FTM0.
+#define BM_SIM_SCGC6_FTM0    (0x01000000U) //!< Bit mask for SIM_SCGC6_FTM0.
+#define BS_SIM_SCGC6_FTM0    (1U)          //!< Bit field size in bits for SIM_SCGC6_FTM0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTM0 field.
+#define BR_SIM_SCGC6_FTM0    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTM0.
+#define BF_SIM_SCGC6_FTM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM0), uint32_t) & BM_SIM_SCGC6_FTM0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0 field to a new value.
+#define BW_SIM_SCGC6_FTM0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTM1    (25U)         //!< Bit position for SIM_SCGC6_FTM1.
+#define BM_SIM_SCGC6_FTM1    (0x02000000U) //!< Bit mask for SIM_SCGC6_FTM1.
+#define BS_SIM_SCGC6_FTM1    (1U)          //!< Bit field size in bits for SIM_SCGC6_FTM1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTM1 field.
+#define BR_SIM_SCGC6_FTM1    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTM1.
+#define BF_SIM_SCGC6_FTM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM1), uint32_t) & BM_SIM_SCGC6_FTM1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1 field to a new value.
+#define BW_SIM_SCGC6_FTM1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTM2    (26U)         //!< Bit position for SIM_SCGC6_FTM2.
+#define BM_SIM_SCGC6_FTM2    (0x04000000U) //!< Bit mask for SIM_SCGC6_FTM2.
+#define BS_SIM_SCGC6_FTM2    (1U)          //!< Bit field size in bits for SIM_SCGC6_FTM2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTM2 field.
+#define BR_SIM_SCGC6_FTM2    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTM2.
+#define BF_SIM_SCGC6_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM2), uint32_t) & BM_SIM_SCGC6_FTM2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2 field to a new value.
+#define BW_SIM_SCGC6_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_ADC0    (27U)         //!< Bit position for SIM_SCGC6_ADC0.
+#define BM_SIM_SCGC6_ADC0    (0x08000000U) //!< Bit mask for SIM_SCGC6_ADC0.
+#define BS_SIM_SCGC6_ADC0    (1U)          //!< Bit field size in bits for SIM_SCGC6_ADC0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_ADC0 field.
+#define BR_SIM_SCGC6_ADC0    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_ADC0.
+#define BF_SIM_SCGC6_ADC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_ADC0), uint32_t) & BM_SIM_SCGC6_ADC0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0 field to a new value.
+#define BW_SIM_SCGC6_ADC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0 - Access and interrupts disabled
+ * - 1 - Access and interrupts enabled
+ */
+//@{
+#define BP_SIM_SCGC6_RTC     (29U)         //!< Bit position for SIM_SCGC6_RTC.
+#define BM_SIM_SCGC6_RTC     (0x20000000U) //!< Bit mask for SIM_SCGC6_RTC.
+#define BS_SIM_SCGC6_RTC     (1U)          //!< Bit field size in bits for SIM_SCGC6_RTC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_RTC field.
+#define BR_SIM_SCGC6_RTC     (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_RTC.
+#define BF_SIM_SCGC6_RTC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RTC), uint32_t) & BM_SIM_SCGC6_RTC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RTC field to a new value.
+#define BW_SIM_SCGC6_RTC(v)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_DAC0    (31U)         //!< Bit position for SIM_SCGC6_DAC0.
+#define BM_SIM_SCGC6_DAC0    (0x80000000U) //!< Bit mask for SIM_SCGC6_DAC0.
+#define BS_SIM_SCGC6_DAC0    (1U)          //!< Bit field size in bits for SIM_SCGC6_DAC0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_DAC0 field.
+#define BR_SIM_SCGC6_DAC0    (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_DAC0.
+#define BF_SIM_SCGC6_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DAC0), uint32_t) & BM_SIM_SCGC6_DAC0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DAC0 field to a new value.
+#define BW_SIM_SCGC6_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC7 - System Clock Gating Control Register 7
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+typedef union _hw_sim_scgc7
+{
+    uint32_t U;
+    struct _hw_sim_scgc7_bitfields
+    {
+        uint32_t FLEXBUS : 1;          //!< [0] FlexBus Clock Gate Control
+        uint32_t DMAb : 1;             //!< [1] DMA Clock Gate Control
+        uint32_t MPUb : 1;             //!< [2] MPU Clock Gate Control
+        uint32_t RESERVED0 : 29;       //!< [31:3]
+    } B;
+} hw_sim_scgc7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+//@{
+#define HW_SIM_SCGC7_ADDR        (REGS_SIM_BASE + 0x1040U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC7             (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR)
+#define HW_SIM_SCGC7_RD()        (HW_SIM_SCGC7.U)
+#define HW_SIM_SCGC7_WR(v)       (HW_SIM_SCGC7.U = (v))
+#define HW_SIM_SCGC7_SET(v)      (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() |  (v)))
+#define HW_SIM_SCGC7_CLR(v)      (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() & ~(v)))
+#define HW_SIM_SCGC7_TOG(v)      (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC7_FLEXBUS (0U)          //!< Bit position for SIM_SCGC7_FLEXBUS.
+#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) //!< Bit mask for SIM_SCGC7_FLEXBUS.
+#define BS_SIM_SCGC7_FLEXBUS (1U)          //!< Bit field size in bits for SIM_SCGC7_FLEXBUS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC7_FLEXBUS field.
+#define BR_SIM_SCGC7_FLEXBUS (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC7_FLEXBUS.
+#define BF_SIM_SCGC7_FLEXBUS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_FLEXBUS), uint32_t) & BM_SIM_SCGC7_FLEXBUS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLEXBUS field to a new value.
+#define BW_SIM_SCGC7_FLEXBUS(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC7_DMA     (1U)          //!< Bit position for SIM_SCGC7_DMA.
+#define BM_SIM_SCGC7_DMA     (0x00000002U) //!< Bit mask for SIM_SCGC7_DMA.
+#define BS_SIM_SCGC7_DMA     (1U)          //!< Bit field size in bits for SIM_SCGC7_DMA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC7_DMA field.
+#define BR_SIM_SCGC7_DMA     (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC7_DMA.
+#define BF_SIM_SCGC7_DMA(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_DMA), uint32_t) & BM_SIM_SCGC7_DMA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMA field to a new value.
+#define BW_SIM_SCGC7_DMA(v)  (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC7_MPU     (2U)          //!< Bit position for SIM_SCGC7_MPU.
+#define BM_SIM_SCGC7_MPU     (0x00000004U) //!< Bit mask for SIM_SCGC7_MPU.
+#define BS_SIM_SCGC7_MPU     (1U)          //!< Bit field size in bits for SIM_SCGC7_MPU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC7_MPU field.
+#define BR_SIM_SCGC7_MPU     (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC7_MPU.
+#define BF_SIM_SCGC7_MPU(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_MPU), uint32_t) & BM_SIM_SCGC7_MPU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPU field to a new value.
+#define BW_SIM_SCGC7_MPU(v)  (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_CLKDIV1 - System Clock Divider Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+typedef union _hw_sim_clkdiv1
+{
+    uint32_t U;
+    struct _hw_sim_clkdiv1_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t OUTDIV4 : 4;          //!< [19:16] Clock 4 output divider value
+        uint32_t OUTDIV3 : 4;          //!< [23:20] Clock 3 output divider value
+        uint32_t OUTDIV2 : 4;          //!< [27:24] Clock 2 output divider value
+        uint32_t OUTDIV1 : 4;          //!< [31:28] Clock 1 output divider value
+    } B;
+} hw_sim_clkdiv1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+//@{
+#define HW_SIM_CLKDIV1_ADDR      (REGS_SIM_BASE + 0x1044U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_CLKDIV1           (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR)
+#define HW_SIM_CLKDIV1_RD()      (HW_SIM_CLKDIV1.U)
+#define HW_SIM_CLKDIV1_WR(v)     (HW_SIM_CLKDIV1.U = (v))
+#define HW_SIM_CLKDIV1_SET(v)    (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() |  (v)))
+#define HW_SIM_CLKDIV1_CLR(v)    (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() & ~(v)))
+#define HW_SIM_CLKDIV1_TOG(v)    (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV4 (16U)       //!< Bit position for SIM_CLKDIV1_OUTDIV4.
+#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV4.
+#define BS_SIM_CLKDIV1_OUTDIV4 (4U)        //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field.
+#define BR_SIM_CLKDIV1_OUTDIV4 (HW_SIM_CLKDIV1.B.OUTDIV4)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4.
+#define BF_SIM_CLKDIV1_OUTDIV4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV4), uint32_t) & BM_SIM_CLKDIV1_OUTDIV4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV4 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV4(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV3 (20U)       //!< Bit position for SIM_CLKDIV1_OUTDIV3.
+#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV3.
+#define BS_SIM_CLKDIV1_OUTDIV3 (4U)        //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field.
+#define BR_SIM_CLKDIV1_OUTDIV3 (HW_SIM_CLKDIV1.B.OUTDIV3)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3.
+#define BF_SIM_CLKDIV1_OUTDIV3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV3), uint32_t) & BM_SIM_CLKDIV1_OUTDIV3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV3 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV3(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV2 (24U)       //!< Bit position for SIM_CLKDIV1_OUTDIV2.
+#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV2.
+#define BS_SIM_CLKDIV1_OUTDIV2 (4U)        //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field.
+#define BR_SIM_CLKDIV1_OUTDIV2 (HW_SIM_CLKDIV1.B.OUTDIV2)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2.
+#define BF_SIM_CLKDIV1_OUTDIV2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV2), uint32_t) & BM_SIM_CLKDIV1_OUTDIV2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV2 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV2(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV1 (28U)       //!< Bit position for SIM_CLKDIV1_OUTDIV1.
+#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV1.
+#define BS_SIM_CLKDIV1_OUTDIV1 (4U)        //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field.
+#define BR_SIM_CLKDIV1_OUTDIV1 (HW_SIM_CLKDIV1.B.OUTDIV1)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1.
+#define BF_SIM_CLKDIV1_OUTDIV1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV1), uint32_t) & BM_SIM_CLKDIV1_OUTDIV1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV1 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV1(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_CLKDIV2 - System Clock Divider Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_clkdiv2
+{
+    uint32_t U;
+    struct _hw_sim_clkdiv2_bitfields
+    {
+        uint32_t USBFRAC : 1;          //!< [0] USB clock divider fraction
+        uint32_t USBDIV : 3;           //!< [3:1] USB clock divider divisor
+        uint32_t RESERVED0 : 28;       //!< [31:4]
+    } B;
+} hw_sim_clkdiv2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+//@{
+#define HW_SIM_CLKDIV2_ADDR      (REGS_SIM_BASE + 0x1048U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_CLKDIV2           (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR)
+#define HW_SIM_CLKDIV2_RD()      (HW_SIM_CLKDIV2.U)
+#define HW_SIM_CLKDIV2_WR(v)     (HW_SIM_CLKDIV2.U = (v))
+#define HW_SIM_CLKDIV2_SET(v)    (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() |  (v)))
+#define HW_SIM_CLKDIV2_CLR(v)    (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() & ~(v)))
+#define HW_SIM_CLKDIV2_TOG(v)    (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+//@{
+#define BP_SIM_CLKDIV2_USBFRAC (0U)        //!< Bit position for SIM_CLKDIV2_USBFRAC.
+#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) //!< Bit mask for SIM_CLKDIV2_USBFRAC.
+#define BS_SIM_CLKDIV2_USBFRAC (1U)        //!< Bit field size in bits for SIM_CLKDIV2_USBFRAC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV2_USBFRAC field.
+#define BR_SIM_CLKDIV2_USBFRAC (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC))
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC.
+#define BF_SIM_CLKDIV2_USBFRAC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBFRAC), uint32_t) & BM_SIM_CLKDIV2_USBFRAC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBFRAC field to a new value.
+#define BW_SIM_CLKDIV2_USBFRAC(v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+//@{
+#define BP_SIM_CLKDIV2_USBDIV (1U)         //!< Bit position for SIM_CLKDIV2_USBDIV.
+#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) //!< Bit mask for SIM_CLKDIV2_USBDIV.
+#define BS_SIM_CLKDIV2_USBDIV (3U)         //!< Bit field size in bits for SIM_CLKDIV2_USBDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV2_USBDIV field.
+#define BR_SIM_CLKDIV2_USBDIV (HW_SIM_CLKDIV2.B.USBDIV)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV2_USBDIV.
+#define BF_SIM_CLKDIV2_USBDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBDIV), uint32_t) & BM_SIM_CLKDIV2_USBDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBDIV field to a new value.
+#define BW_SIM_CLKDIV2_USBDIV(v) (HW_SIM_CLKDIV2_WR((HW_SIM_CLKDIV2_RD() & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_FCFG1 - Flash Configuration Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+typedef union _hw_sim_fcfg1
+{
+    uint32_t U;
+    struct _hw_sim_fcfg1_bitfields
+    {
+        uint32_t FLASHDIS : 1;         //!< [0] Flash Disable
+        uint32_t FLASHDOZE : 1;        //!< [1] Flash Doze
+        uint32_t RESERVED0 : 6;        //!< [7:2]
+        uint32_t DEPART : 4;           //!< [11:8] FlexNVM partition
+        uint32_t RESERVED1 : 4;        //!< [15:12]
+        uint32_t EESIZE : 4;           //!< [19:16] EEPROM size
+        uint32_t RESERVED2 : 4;        //!< [23:20]
+        uint32_t PFSIZE : 4;           //!< [27:24] Program flash size
+        uint32_t NVMSIZE : 4;          //!< [31:28] FlexNVM size
+    } B;
+} hw_sim_fcfg1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+//@{
+#define HW_SIM_FCFG1_ADDR        (REGS_SIM_BASE + 0x104CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_FCFG1             (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR)
+#define HW_SIM_FCFG1_RD()        (HW_SIM_FCFG1.U)
+#define HW_SIM_FCFG1_WR(v)       (HW_SIM_FCFG1.U = (v))
+#define HW_SIM_FCFG1_SET(v)      (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() |  (v)))
+#define HW_SIM_FCFG1_CLR(v)      (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() & ~(v)))
+#define HW_SIM_FCFG1_TOG(v)      (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0 - Flash is enabled
+ * - 1 - Flash is disabled
+ */
+//@{
+#define BP_SIM_FCFG1_FLASHDIS (0U)         //!< Bit position for SIM_FCFG1_FLASHDIS.
+#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) //!< Bit mask for SIM_FCFG1_FLASHDIS.
+#define BS_SIM_FCFG1_FLASHDIS (1U)         //!< Bit field size in bits for SIM_FCFG1_FLASHDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_FLASHDIS field.
+#define BR_SIM_FCFG1_FLASHDIS (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS))
+#endif
+
+//! @brief Format value for bitfield SIM_FCFG1_FLASHDIS.
+#define BF_SIM_FCFG1_FLASHDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDIS), uint32_t) & BM_SIM_FCFG1_FLASHDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLASHDIS field to a new value.
+#define BW_SIM_FCFG1_FLASHDIS(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0 - Flash remains enabled during Wait mode
+ * - 1 - Flash is disabled for the duration of Wait mode
+ */
+//@{
+#define BP_SIM_FCFG1_FLASHDOZE (1U)        //!< Bit position for SIM_FCFG1_FLASHDOZE.
+#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) //!< Bit mask for SIM_FCFG1_FLASHDOZE.
+#define BS_SIM_FCFG1_FLASHDOZE (1U)        //!< Bit field size in bits for SIM_FCFG1_FLASHDOZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_FLASHDOZE field.
+#define BR_SIM_FCFG1_FLASHDOZE (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE))
+#endif
+
+//! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE.
+#define BF_SIM_FCFG1_FLASHDOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDOZE), uint32_t) & BM_SIM_FCFG1_FLASHDOZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLASHDOZE field to a new value.
+#define BW_SIM_FCFG1_FLASHDOZE(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+//@{
+#define BP_SIM_FCFG1_DEPART  (8U)          //!< Bit position for SIM_FCFG1_DEPART.
+#define BM_SIM_FCFG1_DEPART  (0x00000F00U) //!< Bit mask for SIM_FCFG1_DEPART.
+#define BS_SIM_FCFG1_DEPART  (4U)          //!< Bit field size in bits for SIM_FCFG1_DEPART.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_DEPART field.
+#define BR_SIM_FCFG1_DEPART  (HW_SIM_FCFG1.B.DEPART)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0000 - 16 KB
+ * - 0001 - 8 KB
+ * - 0010 - 4 KB
+ * - 0011 - 2 KB
+ * - 0100 - 1 KB
+ * - 0101 - 512 Bytes
+ * - 0110 - 256 Bytes
+ * - 0111 - 128 Bytes
+ * - 1000 - 64 Bytes
+ * - 1001 - 32 Bytes
+ * - 1111 - 0 Bytes
+ */
+//@{
+#define BP_SIM_FCFG1_EESIZE  (16U)         //!< Bit position for SIM_FCFG1_EESIZE.
+#define BM_SIM_FCFG1_EESIZE  (0x000F0000U) //!< Bit mask for SIM_FCFG1_EESIZE.
+#define BS_SIM_FCFG1_EESIZE  (4U)          //!< Bit field size in bits for SIM_FCFG1_EESIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_EESIZE field.
+#define BR_SIM_FCFG1_EESIZE  (HW_SIM_FCFG1.B.EESIZE)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0011 - 32 KB of program flash memory
+ * - 0101 - 64 KB of program flash memory
+ * - 0111 - 128 KB of program flash memory
+ * - 1001 - 256 KB of program flash memory
+ * - 1011 - 512 KB of program flash memory
+ * - 1101 - 1024 KB of program flash memory
+ * - 1111 - 1024 KB of program flash memory
+ */
+//@{
+#define BP_SIM_FCFG1_PFSIZE  (24U)         //!< Bit position for SIM_FCFG1_PFSIZE.
+#define BM_SIM_FCFG1_PFSIZE  (0x0F000000U) //!< Bit mask for SIM_FCFG1_PFSIZE.
+#define BS_SIM_FCFG1_PFSIZE  (4U)          //!< Bit field size in bits for SIM_FCFG1_PFSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_PFSIZE field.
+#define BR_SIM_FCFG1_PFSIZE  (HW_SIM_FCFG1.B.PFSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0000 - 0 KB of FlexNVM
+ * - 0011 - 32 KB of FlexNVM
+ * - 0101 - 64 KB of FlexNVM
+ * - 0111 - 128 KB of FlexNVM
+ * - 1001 - 256 KB of FlexNVM
+ * - 1011 - 512 KB of FlexNVM
+ * - 1111 - 512 KB of FlexNVM
+ */
+//@{
+#define BP_SIM_FCFG1_NVMSIZE (28U)         //!< Bit position for SIM_FCFG1_NVMSIZE.
+#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) //!< Bit mask for SIM_FCFG1_NVMSIZE.
+#define BS_SIM_FCFG1_NVMSIZE (4U)          //!< Bit field size in bits for SIM_FCFG1_NVMSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_NVMSIZE field.
+#define BR_SIM_FCFG1_NVMSIZE (HW_SIM_FCFG1.B.NVMSIZE)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_FCFG2 - Flash Configuration Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+typedef union _hw_sim_fcfg2
+{
+    uint32_t U;
+    struct _hw_sim_fcfg2_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t MAXADDR1 : 7;         //!< [22:16] Max address block 1
+        uint32_t PFLSH : 1;            //!< [23] Program flash only
+        uint32_t MAXADDR0 : 7;         //!< [30:24] Max address block 0
+        uint32_t RESERVED1 : 1;        //!< [31]
+    } B;
+} hw_sim_fcfg2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+//@{
+#define HW_SIM_FCFG2_ADDR        (REGS_SIM_BASE + 0x1050U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_FCFG2             (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR)
+#define HW_SIM_FCFG2_RD()        (HW_SIM_FCFG2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+//@{
+#define BP_SIM_FCFG2_MAXADDR1 (16U)        //!< Bit position for SIM_FCFG2_MAXADDR1.
+#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) //!< Bit mask for SIM_FCFG2_MAXADDR1.
+#define BS_SIM_FCFG2_MAXADDR1 (7U)         //!< Bit field size in bits for SIM_FCFG2_MAXADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG2_MAXADDR1 field.
+#define BR_SIM_FCFG2_MAXADDR1 (HW_SIM_FCFG2.B.MAXADDR1)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0 - Device supports FlexNVM
+ * - 1 - Program Flash only, device does not support FlexNVM
+ */
+//@{
+#define BP_SIM_FCFG2_PFLSH   (23U)         //!< Bit position for SIM_FCFG2_PFLSH.
+#define BM_SIM_FCFG2_PFLSH   (0x00800000U) //!< Bit mask for SIM_FCFG2_PFLSH.
+#define BS_SIM_FCFG2_PFLSH   (1U)          //!< Bit field size in bits for SIM_FCFG2_PFLSH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG2_PFLSH field.
+#define BR_SIM_FCFG2_PFLSH   (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR, BP_SIM_FCFG2_PFLSH))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+//@{
+#define BP_SIM_FCFG2_MAXADDR0 (24U)        //!< Bit position for SIM_FCFG2_MAXADDR0.
+#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) //!< Bit mask for SIM_FCFG2_MAXADDR0.
+#define BS_SIM_FCFG2_MAXADDR0 (7U)         //!< Bit field size in bits for SIM_FCFG2_MAXADDR0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG2_MAXADDR0 field.
+#define BR_SIM_FCFG2_MAXADDR0 (HW_SIM_FCFG2.B.MAXADDR0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDH - Unique Identification Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidh
+{
+    uint32_t U;
+    struct _hw_sim_uidh_bitfields
+    {
+        uint32_t UID : 32;             //!< [31:0] Unique Identification
+    } B;
+} hw_sim_uidh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+//@{
+#define HW_SIM_UIDH_ADDR         (REGS_SIM_BASE + 0x1054U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDH              (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR)
+#define HW_SIM_UIDH_RD()         (HW_SIM_UIDH.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDH bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDH, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDH_UID      (0U)          //!< Bit position for SIM_UIDH_UID.
+#define BM_SIM_UIDH_UID      (0xFFFFFFFFU) //!< Bit mask for SIM_UIDH_UID.
+#define BS_SIM_UIDH_UID      (32U)         //!< Bit field size in bits for SIM_UIDH_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDH_UID field.
+#define BR_SIM_UIDH_UID      (HW_SIM_UIDH.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDMH - Unique Identification Register Mid-High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidmh
+{
+    uint32_t U;
+    struct _hw_sim_uidmh_bitfields
+    {
+        uint32_t UID : 32;             //!< [31:0] Unique Identification
+    } B;
+} hw_sim_uidmh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+//@{
+#define HW_SIM_UIDMH_ADDR        (REGS_SIM_BASE + 0x1058U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDMH             (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR)
+#define HW_SIM_UIDMH_RD()        (HW_SIM_UIDMH.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDMH bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDMH, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDMH_UID     (0U)          //!< Bit position for SIM_UIDMH_UID.
+#define BM_SIM_UIDMH_UID     (0xFFFFFFFFU) //!< Bit mask for SIM_UIDMH_UID.
+#define BS_SIM_UIDMH_UID     (32U)         //!< Bit field size in bits for SIM_UIDMH_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDMH_UID field.
+#define BR_SIM_UIDMH_UID     (HW_SIM_UIDMH.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDML - Unique Identification Register Mid Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidml
+{
+    uint32_t U;
+    struct _hw_sim_uidml_bitfields
+    {
+        uint32_t UID : 32;             //!< [31:0] Unique Identification
+    } B;
+} hw_sim_uidml_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+//@{
+#define HW_SIM_UIDML_ADDR        (REGS_SIM_BASE + 0x105CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDML             (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR)
+#define HW_SIM_UIDML_RD()        (HW_SIM_UIDML.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDML bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDML, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDML_UID     (0U)          //!< Bit position for SIM_UIDML_UID.
+#define BM_SIM_UIDML_UID     (0xFFFFFFFFU) //!< Bit mask for SIM_UIDML_UID.
+#define BS_SIM_UIDML_UID     (32U)         //!< Bit field size in bits for SIM_UIDML_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDML_UID field.
+#define BR_SIM_UIDML_UID     (HW_SIM_UIDML.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDL - Unique Identification Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidl
+{
+    uint32_t U;
+    struct _hw_sim_uidl_bitfields
+    {
+        uint32_t UID : 32;             //!< [31:0] Unique Identification
+    } B;
+} hw_sim_uidl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+//@{
+#define HW_SIM_UIDL_ADDR         (REGS_SIM_BASE + 0x1060U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDL              (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR)
+#define HW_SIM_UIDL_RD()         (HW_SIM_UIDL.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDL bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDL, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDL_UID      (0U)          //!< Bit position for SIM_UIDL_UID.
+#define BM_SIM_UIDL_UID      (0xFFFFFFFFU) //!< Bit mask for SIM_UIDL_UID.
+#define BS_SIM_UIDL_UID      (32U)         //!< Bit field size in bits for SIM_UIDL_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDL_UID field.
+#define BR_SIM_UIDL_UID      (HW_SIM_UIDL.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_sim_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SIM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_sim
+{
+    __IO hw_sim_sopt1_t SOPT1;             //!< [0x0] System Options Register 1
+    __IO hw_sim_sopt1cfg_t SOPT1CFG;       //!< [0x4] SOPT1 Configuration Register
+    uint8_t _reserved0[4092];
+    __IO hw_sim_sopt2_t SOPT2;             //!< [0x1004] System Options Register 2
+    uint8_t _reserved1[4];
+    __IO hw_sim_sopt4_t SOPT4;             //!< [0x100C] System Options Register 4
+    __IO hw_sim_sopt5_t SOPT5;             //!< [0x1010] System Options Register 5
+    uint8_t _reserved2[4];
+    __IO hw_sim_sopt7_t SOPT7;             //!< [0x1018] System Options Register 7
+    uint8_t _reserved3[8];
+    __I hw_sim_sdid_t SDID;                //!< [0x1024] System Device Identification Register
+    __IO hw_sim_scgc1_t SCGC1;             //!< [0x1028] System Clock Gating Control Register 1
+    __IO hw_sim_scgc2_t SCGC2;             //!< [0x102C] System Clock Gating Control Register 2
+    __IO hw_sim_scgc3_t SCGC3;             //!< [0x1030] System Clock Gating Control Register 3
+    __IO hw_sim_scgc4_t SCGC4;             //!< [0x1034] System Clock Gating Control Register 4
+    __IO hw_sim_scgc5_t SCGC5;             //!< [0x1038] System Clock Gating Control Register 5
+    __IO hw_sim_scgc6_t SCGC6;             //!< [0x103C] System Clock Gating Control Register 6
+    __IO hw_sim_scgc7_t SCGC7;             //!< [0x1040] System Clock Gating Control Register 7
+    __IO hw_sim_clkdiv1_t CLKDIV1;         //!< [0x1044] System Clock Divider Register 1
+    __IO hw_sim_clkdiv2_t CLKDIV2;         //!< [0x1048] System Clock Divider Register 2
+    __IO hw_sim_fcfg1_t FCFG1;             //!< [0x104C] Flash Configuration Register 1
+    __I hw_sim_fcfg2_t FCFG2;              //!< [0x1050] Flash Configuration Register 2
+    __I hw_sim_uidh_t UIDH;                //!< [0x1054] Unique Identification Register High
+    __I hw_sim_uidmh_t UIDMH;              //!< [0x1058] Unique Identification Register Mid-High
+    __I hw_sim_uidml_t UIDML;              //!< [0x105C] Unique Identification Register Mid Low
+    __I hw_sim_uidl_t UIDL;                //!< [0x1060] Unique Identification Register Low
+} hw_sim_t;
+#pragma pack()
+
+//! @brief Macro to access all SIM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_SIM</code>.
+#define HW_SIM         (*(hw_sim_t *) REGS_SIM_BASE)
+#endif
+
+#endif // __HW_SIM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h
new file mode 100644
index 0000000000..6f05c5d5cd
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h
@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SMC_REGISTERS_H__
+#define __HW_SMC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - HW_SMC_PMPROT - Power Mode Protection register
+ * - HW_SMC_PMCTRL - Power Mode Control register
+ * - HW_SMC_VLLSCTRL - VLLS Control register
+ * - HW_SMC_PMSTAT - Power Mode Status register
+ *
+ * - hw_smc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SMC_BASE
+#define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
+#define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_PMPROT - Power Mode Protection register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+typedef union _hw_smc_pmprot
+{
+    uint8_t U;
+    struct _hw_smc_pmprot_bitfields
+    {
+        uint8_t RESERVED0 : 1;         //!< [0]
+        uint8_t AVLLS : 1;             //!< [1] Allow Very-Low-Leakage Stop Mode
+        uint8_t RESERVED1 : 1;         //!< [2]
+        uint8_t ALLS : 1;              //!< [3] Allow Low-Leakage Stop Mode
+        uint8_t RESERVED2 : 1;         //!< [4]
+        uint8_t AVLP : 1;              //!< [5] Allow Very-Low-Power Modes
+        uint8_t RESERVED3 : 2;         //!< [7:6]
+    } B;
+} hw_smc_pmprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+//@{
+#define HW_SMC_PMPROT_ADDR       (REGS_SMC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_PMPROT            (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
+#define HW_SMC_PMPROT_RD()       (HW_SMC_PMPROT.U)
+#define HW_SMC_PMPROT_WR(v)      (HW_SMC_PMPROT.U = (v))
+#define HW_SMC_PMPROT_SET(v)     (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() |  (v)))
+#define HW_SMC_PMPROT_CLR(v)     (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
+#define HW_SMC_PMPROT_TOG(v)     (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0 - Any VLLSx mode is not allowed
+ * - 1 - Any VLLSx mode is allowed
+ */
+//@{
+#define BP_SMC_PMPROT_AVLLS  (1U)          //!< Bit position for SMC_PMPROT_AVLLS.
+#define BM_SMC_PMPROT_AVLLS  (0x02U)       //!< Bit mask for SMC_PMPROT_AVLLS.
+#define BS_SMC_PMPROT_AVLLS  (1U)          //!< Bit field size in bits for SMC_PMPROT_AVLLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMPROT_AVLLS field.
+#define BR_SMC_PMPROT_AVLLS  (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
+#endif
+
+//! @brief Format value for bitfield SMC_PMPROT_AVLLS.
+#define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVLLS field to a new value.
+#define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0 - LLS is not allowed
+ * - 1 - LLS is allowed
+ */
+//@{
+#define BP_SMC_PMPROT_ALLS   (3U)          //!< Bit position for SMC_PMPROT_ALLS.
+#define BM_SMC_PMPROT_ALLS   (0x08U)       //!< Bit mask for SMC_PMPROT_ALLS.
+#define BS_SMC_PMPROT_ALLS   (1U)          //!< Bit field size in bits for SMC_PMPROT_ALLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMPROT_ALLS field.
+#define BR_SMC_PMPROT_ALLS   (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
+#endif
+
+//! @brief Format value for bitfield SMC_PMPROT_ALLS.
+#define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ALLS field to a new value.
+#define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 1 - VLPR, VLPW, and VLPS are allowed.
+ */
+//@{
+#define BP_SMC_PMPROT_AVLP   (5U)          //!< Bit position for SMC_PMPROT_AVLP.
+#define BM_SMC_PMPROT_AVLP   (0x20U)       //!< Bit mask for SMC_PMPROT_AVLP.
+#define BS_SMC_PMPROT_AVLP   (1U)          //!< Bit field size in bits for SMC_PMPROT_AVLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMPROT_AVLP field.
+#define BR_SMC_PMPROT_AVLP   (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
+#endif
+
+//! @brief Format value for bitfield SMC_PMPROT_AVLP.
+#define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVLP field to a new value.
+#define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_PMCTRL - Power Mode Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+typedef union _hw_smc_pmctrl
+{
+    uint8_t U;
+    struct _hw_smc_pmctrl_bitfields
+    {
+        uint8_t STOPM : 3;             //!< [2:0] Stop Mode Control
+        uint8_t STOPA : 1;             //!< [3] Stop Aborted
+        uint8_t RESERVED0 : 1;         //!< [4]
+        uint8_t RUNM : 2;              //!< [6:5] Run Mode Control
+        uint8_t LPWUI : 1;             //!< [7] Low-Power Wake Up On Interrupt
+    } B;
+} hw_smc_pmctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+//@{
+#define HW_SMC_PMCTRL_ADDR       (REGS_SMC_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_PMCTRL            (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
+#define HW_SMC_PMCTRL_RD()       (HW_SMC_PMCTRL.U)
+#define HW_SMC_PMCTRL_WR(v)      (HW_SMC_PMCTRL.U = (v))
+#define HW_SMC_PMCTRL_SET(v)     (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() |  (v)))
+#define HW_SMC_PMCTRL_CLR(v)     (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
+#define HW_SMC_PMCTRL_TOG(v)     (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 000 - Normal Stop (STOP)
+ * - 001 - Reserved
+ * - 010 - Very-Low-Power Stop (VLPS)
+ * - 011 - Low-Leakage Stop (LLS)
+ * - 100 - Very-Low-Leakage Stop (VLLSx)
+ * - 101 - Reserved
+ * - 110 - Reseved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SMC_PMCTRL_STOPM  (0U)          //!< Bit position for SMC_PMCTRL_STOPM.
+#define BM_SMC_PMCTRL_STOPM  (0x07U)       //!< Bit mask for SMC_PMCTRL_STOPM.
+#define BS_SMC_PMCTRL_STOPM  (3U)          //!< Bit field size in bits for SMC_PMCTRL_STOPM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_STOPM field.
+#define BR_SMC_PMCTRL_STOPM  (HW_SMC_PMCTRL.B.STOPM)
+#endif
+
+//! @brief Format value for bitfield SMC_PMCTRL_STOPM.
+#define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPM field to a new value.
+#define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0 - The previous stop mode entry was successsful.
+ * - 1 - The previous stop mode entry was aborted.
+ */
+//@{
+#define BP_SMC_PMCTRL_STOPA  (3U)          //!< Bit position for SMC_PMCTRL_STOPA.
+#define BM_SMC_PMCTRL_STOPA  (0x08U)       //!< Bit mask for SMC_PMCTRL_STOPA.
+#define BS_SMC_PMCTRL_STOPA  (1U)          //!< Bit field size in bits for SMC_PMCTRL_STOPA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_STOPA field.
+#define BR_SMC_PMCTRL_STOPA  (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 00 - Normal Run mode (RUN)
+ * - 01 - Reserved
+ * - 10 - Very-Low-Power Run mode (VLPR)
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SMC_PMCTRL_RUNM   (5U)          //!< Bit position for SMC_PMCTRL_RUNM.
+#define BM_SMC_PMCTRL_RUNM   (0x60U)       //!< Bit mask for SMC_PMCTRL_RUNM.
+#define BS_SMC_PMCTRL_RUNM   (2U)          //!< Bit field size in bits for SMC_PMCTRL_RUNM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_RUNM field.
+#define BR_SMC_PMCTRL_RUNM   (HW_SMC_PMCTRL.B.RUNM)
+#endif
+
+//! @brief Format value for bitfield SMC_PMCTRL_RUNM.
+#define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RUNM field to a new value.
+#define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0 - The system remains in a VLP mode on an interrupt
+ * - 1 - The system exits to Normal RUN mode on an interrupt
+ */
+//@{
+#define BP_SMC_PMCTRL_LPWUI  (7U)          //!< Bit position for SMC_PMCTRL_LPWUI.
+#define BM_SMC_PMCTRL_LPWUI  (0x80U)       //!< Bit mask for SMC_PMCTRL_LPWUI.
+#define BS_SMC_PMCTRL_LPWUI  (1U)          //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_LPWUI field.
+#define BR_SMC_PMCTRL_LPWUI  (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
+#endif
+
+//! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
+#define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPWUI field to a new value.
+#define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_VLLSCTRL - VLLS Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+typedef union _hw_smc_vllsctrl
+{
+    uint8_t U;
+    struct _hw_smc_vllsctrl_bitfields
+    {
+        uint8_t VLLSM : 3;             //!< [2:0] VLLS Mode Control
+        uint8_t RESERVED0 : 2;         //!< [4:3]
+        uint8_t PORPO : 1;             //!< [5] POR Power Option
+        uint8_t RESERVED1 : 2;         //!< [7:6]
+    } B;
+} hw_smc_vllsctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+//@{
+#define HW_SMC_VLLSCTRL_ADDR     (REGS_SMC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_VLLSCTRL          (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
+#define HW_SMC_VLLSCTRL_RD()     (HW_SMC_VLLSCTRL.U)
+#define HW_SMC_VLLSCTRL_WR(v)    (HW_SMC_VLLSCTRL.U = (v))
+#define HW_SMC_VLLSCTRL_SET(v)   (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() |  (v)))
+#define HW_SMC_VLLSCTRL_CLR(v)   (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
+#define HW_SMC_VLLSCTRL_TOG(v)   (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 000 - VLLS0
+ * - 001 - VLLS1
+ * - 010 - VLLS2
+ * - 011 - VLLS3
+ * - 100 - Reserved
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SMC_VLLSCTRL_VLLSM (0U)         //!< Bit position for SMC_VLLSCTRL_VLLSM.
+#define BM_SMC_VLLSCTRL_VLLSM (0x07U)      //!< Bit mask for SMC_VLLSCTRL_VLLSM.
+#define BS_SMC_VLLSCTRL_VLLSM (3U)         //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
+#define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
+#endif
+
+//! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
+#define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VLLSM field to a new value.
+#define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0 - POR detect circuit is enabled in VLLS0.
+ * - 1 - POR detect circuit is disabled in VLLS0.
+ */
+//@{
+#define BP_SMC_VLLSCTRL_PORPO (5U)         //!< Bit position for SMC_VLLSCTRL_PORPO.
+#define BM_SMC_VLLSCTRL_PORPO (0x20U)      //!< Bit mask for SMC_VLLSCTRL_PORPO.
+#define BS_SMC_VLLSCTRL_PORPO (1U)         //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
+#define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
+#endif
+
+//! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
+#define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORPO field to a new value.
+#define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_PMSTAT - Power Mode Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+typedef union _hw_smc_pmstat
+{
+    uint8_t U;
+    struct _hw_smc_pmstat_bitfields
+    {
+        uint8_t PMSTAT : 7;            //!< [6:0]
+        uint8_t RESERVED0 : 1;         //!< [7]
+    } B;
+} hw_smc_pmstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+//@{
+#define HW_SMC_PMSTAT_ADDR       (REGS_SMC_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_PMSTAT            (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
+#define HW_SMC_PMSTAT_RD()       (HW_SMC_PMSTAT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+//@{
+#define BP_SMC_PMSTAT_PMSTAT (0U)          //!< Bit position for SMC_PMSTAT_PMSTAT.
+#define BM_SMC_PMSTAT_PMSTAT (0x7FU)       //!< Bit mask for SMC_PMSTAT_PMSTAT.
+#define BS_SMC_PMSTAT_PMSTAT (7U)          //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
+#define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_smc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SMC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_smc
+{
+    __IO hw_smc_pmprot_t PMPROT;           //!< [0x0] Power Mode Protection register
+    __IO hw_smc_pmctrl_t PMCTRL;           //!< [0x1] Power Mode Control register
+    __IO hw_smc_vllsctrl_t VLLSCTRL;       //!< [0x2] VLLS Control register
+    __I hw_smc_pmstat_t PMSTAT;            //!< [0x3] Power Mode Status register
+} hw_smc_t;
+#pragma pack()
+
+//! @brief Macro to access all SMC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_SMC</code>.
+#define HW_SMC         (*(hw_smc_t *) REGS_SMC_BASE)
+#endif
+
+#endif // __HW_SMC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h
new file mode 100644
index 0000000000..3ed958f2f8
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h
@@ -0,0 +1,2445 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SPI_REGISTERS_H__
+#define __HW_SPI_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - HW_SPI_MCR - Module Configuration Register
+ * - HW_SPI_TCR - Transfer Count Register
+ * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
+ * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - HW_SPI_SR - Status Register
+ * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - HW_SPI_POPR - POP RX FIFO Register
+ * - HW_SPI_TXFRn - Transmit FIFO Registers
+ * - HW_SPI_RXFRn - Receive FIFO Registers
+ *
+ * - hw_spi_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SPI_BASE
+#define HW_SPI_INSTANCE_COUNT (3U) //!< Number of instances of the SPI module.
+#define HW_SPI0 (0U) //!< Instance number for SPI0.
+#define HW_SPI1 (1U) //!< Instance number for SPI1.
+#define HW_SPI2 (2U) //!< Instance number for SPI2.
+#define REGS_SPI0_BASE (0x4002C000U) //!< Base address for SPI0.
+#define REGS_SPI1_BASE (0x4002D000U) //!< Base address for SPI1.
+#define REGS_SPI2_BASE (0x400AC000U) //!< Base address for SPI2.
+
+//! @brief Table of base addresses for SPI instances.
+static const uint32_t __g_regs_SPI_base_addresses[] = {
+        REGS_SPI0_BASE,
+        REGS_SPI1_BASE,
+        REGS_SPI2_BASE,
+    };
+
+//! @brief Get the base address of SPI by instance number.
+//! @param x SPI instance number, from 0 through 2.
+#define REGS_SPI_BASE(x) (__g_regs_SPI_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of SPI.
+#define REGS_SPI_INSTANCE(b) ((b) == REGS_SPI0_BASE ? HW_SPI0 : (b) == REGS_SPI1_BASE ? HW_SPI1 : (b) == REGS_SPI2_BASE ? HW_SPI2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_MCR - Module Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+typedef union _hw_spi_mcr
+{
+    uint32_t U;
+    struct _hw_spi_mcr_bitfields
+    {
+        uint32_t HALT : 1;             //!< [0] Halt
+        uint32_t RESERVED0 : 7;        //!< [7:1]
+        uint32_t SMPL_PT : 2;          //!< [9:8] Sample Point
+        uint32_t CLR_RXF : 1;          //!< [10]
+        uint32_t CLR_TXF : 1;          //!< [11] Clear TX FIFO
+        uint32_t DIS_RXF : 1;          //!< [12] Disable Receive FIFO
+        uint32_t DIS_TXF : 1;          //!< [13] Disable Transmit FIFO
+        uint32_t MDIS : 1;             //!< [14] Module Disable
+        uint32_t DOZE : 1;             //!< [15] Doze Enable
+        uint32_t PCSIS : 6;            //!< [21:16] Peripheral Chip Select x Inactive
+                                       //! State
+        uint32_t RESERVED1 : 2;        //!< [23:22]
+        uint32_t ROOE : 1;             //!< [24] Receive FIFO Overflow Overwrite Enable
+        uint32_t PCSSE : 1;            //!< [25] Peripheral Chip Select Strobe Enable
+        uint32_t MTFE : 1;             //!< [26] Modified Timing Format Enable
+        uint32_t FRZ : 1;              //!< [27] Freeze
+        uint32_t DCONF : 2;            //!< [29:28] SPI Configuration.
+        uint32_t CONT_SCKE : 1;        //!< [30] Continuous SCK Enable
+        uint32_t MSTR : 1;             //!< [31] Master/Slave Mode Select
+    } B;
+} hw_spi_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+//@{
+#define HW_SPI_MCR_ADDR(x)       (REGS_SPI_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_MCR(x)            (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
+#define HW_SPI_MCR_RD(x)         (HW_SPI_MCR(x).U)
+#define HW_SPI_MCR_WR(x, v)      (HW_SPI_MCR(x).U = (v))
+#define HW_SPI_MCR_SET(x, v)     (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) |  (v)))
+#define HW_SPI_MCR_CLR(x, v)     (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
+#define HW_SPI_MCR_TOG(x, v)     (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0 - Start transfers.
+ * - 1 - Stop transfers.
+ */
+//@{
+#define BP_SPI_MCR_HALT      (0U)          //!< Bit position for SPI_MCR_HALT.
+#define BM_SPI_MCR_HALT      (0x00000001U) //!< Bit mask for SPI_MCR_HALT.
+#define BS_SPI_MCR_HALT      (1U)          //!< Bit field size in bits for SPI_MCR_HALT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_HALT field.
+#define BR_SPI_MCR_HALT(x)   (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_HALT.
+#define BF_SPI_MCR_HALT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_HALT), uint32_t) & BM_SPI_MCR_HALT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HALT field to a new value.
+#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SPI_MCR_SMPL_PT   (8U)          //!< Bit position for SPI_MCR_SMPL_PT.
+#define BM_SPI_MCR_SMPL_PT   (0x00000300U) //!< Bit mask for SPI_MCR_SMPL_PT.
+#define BS_SPI_MCR_SMPL_PT   (2U)          //!< Bit field size in bits for SPI_MCR_SMPL_PT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_SMPL_PT field.
+#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_SMPL_PT.
+#define BF_SPI_MCR_SMPL_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_SMPL_PT), uint32_t) & BM_SPI_MCR_SMPL_PT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMPL_PT field to a new value.
+#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0 - Do not clear the RX FIFO counter.
+ * - 1 - Clear the RX FIFO counter.
+ */
+//@{
+#define BP_SPI_MCR_CLR_RXF   (10U)         //!< Bit position for SPI_MCR_CLR_RXF.
+#define BM_SPI_MCR_CLR_RXF   (0x00000400U) //!< Bit mask for SPI_MCR_CLR_RXF.
+#define BS_SPI_MCR_CLR_RXF   (1U)          //!< Bit field size in bits for SPI_MCR_CLR_RXF.
+
+//! @brief Format value for bitfield SPI_MCR_CLR_RXF.
+#define BF_SPI_MCR_CLR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_RXF), uint32_t) & BM_SPI_MCR_CLR_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLR_RXF field to a new value.
+#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0 - Do not clear the TX FIFO counter.
+ * - 1 - Clear the TX FIFO counter.
+ */
+//@{
+#define BP_SPI_MCR_CLR_TXF   (11U)         //!< Bit position for SPI_MCR_CLR_TXF.
+#define BM_SPI_MCR_CLR_TXF   (0x00000800U) //!< Bit mask for SPI_MCR_CLR_TXF.
+#define BS_SPI_MCR_CLR_TXF   (1U)          //!< Bit field size in bits for SPI_MCR_CLR_TXF.
+
+//! @brief Format value for bitfield SPI_MCR_CLR_TXF.
+#define BF_SPI_MCR_CLR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_TXF), uint32_t) & BM_SPI_MCR_CLR_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLR_TXF field to a new value.
+#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0 - RX FIFO is enabled.
+ * - 1 - RX FIFO is disabled.
+ */
+//@{
+#define BP_SPI_MCR_DIS_RXF   (12U)         //!< Bit position for SPI_MCR_DIS_RXF.
+#define BM_SPI_MCR_DIS_RXF   (0x00001000U) //!< Bit mask for SPI_MCR_DIS_RXF.
+#define BS_SPI_MCR_DIS_RXF   (1U)          //!< Bit field size in bits for SPI_MCR_DIS_RXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DIS_RXF field.
+#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_DIS_RXF.
+#define BF_SPI_MCR_DIS_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_RXF), uint32_t) & BM_SPI_MCR_DIS_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIS_RXF field to a new value.
+#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0 - TX FIFO is enabled.
+ * - 1 - TX FIFO is disabled.
+ */
+//@{
+#define BP_SPI_MCR_DIS_TXF   (13U)         //!< Bit position for SPI_MCR_DIS_TXF.
+#define BM_SPI_MCR_DIS_TXF   (0x00002000U) //!< Bit mask for SPI_MCR_DIS_TXF.
+#define BS_SPI_MCR_DIS_TXF   (1U)          //!< Bit field size in bits for SPI_MCR_DIS_TXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DIS_TXF field.
+#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_DIS_TXF.
+#define BF_SPI_MCR_DIS_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_TXF), uint32_t) & BM_SPI_MCR_DIS_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIS_TXF field to a new value.
+#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0 - Enables the module clocks.
+ * - 1 - Allows external logic to disable the module clocks.
+ */
+//@{
+#define BP_SPI_MCR_MDIS      (14U)         //!< Bit position for SPI_MCR_MDIS.
+#define BM_SPI_MCR_MDIS      (0x00004000U) //!< Bit mask for SPI_MCR_MDIS.
+#define BS_SPI_MCR_MDIS      (1U)          //!< Bit field size in bits for SPI_MCR_MDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_MDIS field.
+#define BR_SPI_MCR_MDIS(x)   (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_MDIS.
+#define BF_SPI_MCR_MDIS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MDIS), uint32_t) & BM_SPI_MCR_MDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MDIS field to a new value.
+#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0 - Doze mode has no effect on the module.
+ * - 1 - Doze mode disables the module.
+ */
+//@{
+#define BP_SPI_MCR_DOZE      (15U)         //!< Bit position for SPI_MCR_DOZE.
+#define BM_SPI_MCR_DOZE      (0x00008000U) //!< Bit mask for SPI_MCR_DOZE.
+#define BS_SPI_MCR_DOZE      (1U)          //!< Bit field size in bits for SPI_MCR_DOZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DOZE field.
+#define BR_SPI_MCR_DOZE(x)   (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_DOZE.
+#define BF_SPI_MCR_DOZE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DOZE), uint32_t) & BM_SPI_MCR_DOZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DOZE field to a new value.
+#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0 - The inactive state of PCSx is low.
+ * - 1 - The inactive state of PCSx is high.
+ */
+//@{
+#define BP_SPI_MCR_PCSIS     (16U)         //!< Bit position for SPI_MCR_PCSIS.
+#define BM_SPI_MCR_PCSIS     (0x003F0000U) //!< Bit mask for SPI_MCR_PCSIS.
+#define BS_SPI_MCR_PCSIS     (6U)          //!< Bit field size in bits for SPI_MCR_PCSIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_PCSIS field.
+#define BR_SPI_MCR_PCSIS(x)  (HW_SPI_MCR(x).B.PCSIS)
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_PCSIS.
+#define BF_SPI_MCR_PCSIS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSIS), uint32_t) & BM_SPI_MCR_PCSIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCSIS field to a new value.
+#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0 - Incoming data is ignored.
+ * - 1 - Incoming data is shifted into the shift register.
+ */
+//@{
+#define BP_SPI_MCR_ROOE      (24U)         //!< Bit position for SPI_MCR_ROOE.
+#define BM_SPI_MCR_ROOE      (0x01000000U) //!< Bit mask for SPI_MCR_ROOE.
+#define BS_SPI_MCR_ROOE      (1U)          //!< Bit field size in bits for SPI_MCR_ROOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_ROOE field.
+#define BR_SPI_MCR_ROOE(x)   (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_ROOE.
+#define BF_SPI_MCR_ROOE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_ROOE), uint32_t) & BM_SPI_MCR_ROOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ROOE field to a new value.
+#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+//@{
+#define BP_SPI_MCR_PCSSE     (25U)         //!< Bit position for SPI_MCR_PCSSE.
+#define BM_SPI_MCR_PCSSE     (0x02000000U) //!< Bit mask for SPI_MCR_PCSSE.
+#define BS_SPI_MCR_PCSSE     (1U)          //!< Bit field size in bits for SPI_MCR_PCSSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_PCSSE field.
+#define BR_SPI_MCR_PCSSE(x)  (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_PCSSE.
+#define BF_SPI_MCR_PCSSE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSSE), uint32_t) & BM_SPI_MCR_PCSSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCSSE field to a new value.
+#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0 - Modified SPI transfer format disabled.
+ * - 1 - Modified SPI transfer format enabled.
+ */
+//@{
+#define BP_SPI_MCR_MTFE      (26U)         //!< Bit position for SPI_MCR_MTFE.
+#define BM_SPI_MCR_MTFE      (0x04000000U) //!< Bit mask for SPI_MCR_MTFE.
+#define BS_SPI_MCR_MTFE      (1U)          //!< Bit field size in bits for SPI_MCR_MTFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_MTFE field.
+#define BR_SPI_MCR_MTFE(x)   (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_MTFE.
+#define BF_SPI_MCR_MTFE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MTFE), uint32_t) & BM_SPI_MCR_MTFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTFE field to a new value.
+#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0 - Do not halt serial transfers in Debug mode.
+ * - 1 - Halt serial transfers in Debug mode.
+ */
+//@{
+#define BP_SPI_MCR_FRZ       (27U)         //!< Bit position for SPI_MCR_FRZ.
+#define BM_SPI_MCR_FRZ       (0x08000000U) //!< Bit mask for SPI_MCR_FRZ.
+#define BS_SPI_MCR_FRZ       (1U)          //!< Bit field size in bits for SPI_MCR_FRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_FRZ field.
+#define BR_SPI_MCR_FRZ(x)    (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_FRZ.
+#define BF_SPI_MCR_FRZ(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_FRZ), uint32_t) & BM_SPI_MCR_FRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRZ field to a new value.
+#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 00 - SPI
+ * - 01 - Reserved
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SPI_MCR_DCONF     (28U)         //!< Bit position for SPI_MCR_DCONF.
+#define BM_SPI_MCR_DCONF     (0x30000000U) //!< Bit mask for SPI_MCR_DCONF.
+#define BS_SPI_MCR_DCONF     (2U)          //!< Bit field size in bits for SPI_MCR_DCONF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DCONF field.
+#define BR_SPI_MCR_DCONF(x)  (HW_SPI_MCR(x).B.DCONF)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0 - Continuous SCK disabled.
+ * - 1 - Continuous SCK enabled.
+ */
+//@{
+#define BP_SPI_MCR_CONT_SCKE (30U)         //!< Bit position for SPI_MCR_CONT_SCKE.
+#define BM_SPI_MCR_CONT_SCKE (0x40000000U) //!< Bit mask for SPI_MCR_CONT_SCKE.
+#define BS_SPI_MCR_CONT_SCKE (1U)          //!< Bit field size in bits for SPI_MCR_CONT_SCKE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_CONT_SCKE field.
+#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_CONT_SCKE.
+#define BF_SPI_MCR_CONT_SCKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CONT_SCKE), uint32_t) & BM_SPI_MCR_CONT_SCKE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CONT_SCKE field to a new value.
+#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0 - Enables Slave mode
+ * - 1 - Enables Master mode
+ */
+//@{
+#define BP_SPI_MCR_MSTR      (31U)         //!< Bit position for SPI_MCR_MSTR.
+#define BM_SPI_MCR_MSTR      (0x80000000U) //!< Bit mask for SPI_MCR_MSTR.
+#define BS_SPI_MCR_MSTR      (1U)          //!< Bit field size in bits for SPI_MCR_MSTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_MSTR field.
+#define BR_SPI_MCR_MSTR(x)   (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_MSTR.
+#define BF_SPI_MCR_MSTR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MSTR), uint32_t) & BM_SPI_MCR_MSTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSTR field to a new value.
+#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_TCR - Transfer Count Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+typedef union _hw_spi_tcr
+{
+    uint32_t U;
+    struct _hw_spi_tcr_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t SPI_TCNT : 16;        //!< [31:16] SPI Transfer Counter
+    } B;
+} hw_spi_tcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+//@{
+#define HW_SPI_TCR_ADDR(x)       (REGS_SPI_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_TCR(x)            (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
+#define HW_SPI_TCR_RD(x)         (HW_SPI_TCR(x).U)
+#define HW_SPI_TCR_WR(x, v)      (HW_SPI_TCR(x).U = (v))
+#define HW_SPI_TCR_SET(x, v)     (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) |  (v)))
+#define HW_SPI_TCR_CLR(x, v)     (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
+#define HW_SPI_TCR_TOG(x, v)     (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+//@{
+#define BP_SPI_TCR_SPI_TCNT  (16U)         //!< Bit position for SPI_TCR_SPI_TCNT.
+#define BM_SPI_TCR_SPI_TCNT  (0xFFFF0000U) //!< Bit mask for SPI_TCR_SPI_TCNT.
+#define BS_SPI_TCR_SPI_TCNT  (16U)         //!< Bit field size in bits for SPI_TCR_SPI_TCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_TCR_SPI_TCNT field.
+#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
+#endif
+
+//! @brief Format value for bitfield SPI_TCR_SPI_TCNT.
+#define BF_SPI_TCR_SPI_TCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_TCR_SPI_TCNT), uint32_t) & BM_SPI_TCR_SPI_TCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI_TCNT field to a new value.
+#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+typedef union _hw_spi_ctarn
+{
+    uint32_t U;
+    struct _hw_spi_ctarn_bitfields
+    {
+        uint32_t BR : 4;               //!< [3:0] Baud Rate Scaler
+        uint32_t DT : 4;               //!< [7:4] Delay After Transfer Scaler
+        uint32_t ASC : 4;              //!< [11:8] After SCK Delay Scaler
+        uint32_t CSSCK : 4;            //!< [15:12] PCS to SCK Delay Scaler
+        uint32_t PBR : 2;              //!< [17:16] Baud Rate Prescaler
+        uint32_t PDT : 2;              //!< [19:18] Delay after Transfer Prescaler
+        uint32_t PASC : 2;             //!< [21:20] After SCK Delay Prescaler
+        uint32_t PCSSCK : 2;           //!< [23:22] PCS to SCK Delay Prescaler
+        uint32_t LSBFE : 1;            //!< [24] LSB First
+        uint32_t CPHA : 1;             //!< [25] Clock Phase
+        uint32_t CPOL : 1;             //!< [26] Clock Polarity
+        uint32_t FMSZ : 4;             //!< [30:27] Frame Size
+        uint32_t DBR : 1;              //!< [31] Double Baud Rate
+    } B;
+} hw_spi_ctarn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_CTARn register
+ */
+//@{
+#define HW_SPI_CTARn_COUNT (2U)
+
+#define HW_SPI_CTARn_ADDR(x, n)  (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_CTARn(x, n)       (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
+#define HW_SPI_CTARn_RD(x, n)    (HW_SPI_CTARn(x, n).U)
+#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
+#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) |  (v)))
+#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
+#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_CTARn bitfields
+ */
+
+/*!
+ * @name Register SPI_CTARn, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+//@{
+#define BP_SPI_CTARn_BR      (0U)          //!< Bit position for SPI_CTARn_BR.
+#define BM_SPI_CTARn_BR      (0x0000000FU) //!< Bit mask for SPI_CTARn_BR.
+#define BS_SPI_CTARn_BR      (4U)          //!< Bit field size in bits for SPI_CTARn_BR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_BR field.
+#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_BR.
+#define BF_SPI_CTARn_BR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_BR), uint32_t) & BM_SPI_CTARn_BR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BR field to a new value.
+#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+//@{
+#define BP_SPI_CTARn_DT      (4U)          //!< Bit position for SPI_CTARn_DT.
+#define BM_SPI_CTARn_DT      (0x000000F0U) //!< Bit mask for SPI_CTARn_DT.
+#define BS_SPI_CTARn_DT      (4U)          //!< Bit field size in bits for SPI_CTARn_DT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_DT field.
+#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_DT.
+#define BF_SPI_CTARn_DT(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DT), uint32_t) & BM_SPI_CTARn_DT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DT field to a new value.
+#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+//@{
+#define BP_SPI_CTARn_ASC     (8U)          //!< Bit position for SPI_CTARn_ASC.
+#define BM_SPI_CTARn_ASC     (0x00000F00U) //!< Bit mask for SPI_CTARn_ASC.
+#define BS_SPI_CTARn_ASC     (4U)          //!< Bit field size in bits for SPI_CTARn_ASC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_ASC field.
+#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_ASC.
+#define BF_SPI_CTARn_ASC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_ASC), uint32_t) & BM_SPI_CTARn_ASC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ASC field to a new value.
+#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+//@{
+#define BP_SPI_CTARn_CSSCK   (12U)         //!< Bit position for SPI_CTARn_CSSCK.
+#define BM_SPI_CTARn_CSSCK   (0x0000F000U) //!< Bit mask for SPI_CTARn_CSSCK.
+#define BS_SPI_CTARn_CSSCK   (4U)          //!< Bit field size in bits for SPI_CTARn_CSSCK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_CSSCK field.
+#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_CSSCK.
+#define BF_SPI_CTARn_CSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CSSCK), uint32_t) & BM_SPI_CTARn_CSSCK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CSSCK field to a new value.
+#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 00 - Baud Rate Prescaler value is 2.
+ * - 01 - Baud Rate Prescaler value is 3.
+ * - 10 - Baud Rate Prescaler value is 5.
+ * - 11 - Baud Rate Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PBR     (16U)         //!< Bit position for SPI_CTARn_PBR.
+#define BM_SPI_CTARn_PBR     (0x00030000U) //!< Bit mask for SPI_CTARn_PBR.
+#define BS_SPI_CTARn_PBR     (2U)          //!< Bit field size in bits for SPI_CTARn_PBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PBR field.
+#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PBR.
+#define BF_SPI_CTARn_PBR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PBR), uint32_t) & BM_SPI_CTARn_PBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PBR field to a new value.
+#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 00 - Delay after Transfer Prescaler value is 1.
+ * - 01 - Delay after Transfer Prescaler value is 3.
+ * - 10 - Delay after Transfer Prescaler value is 5.
+ * - 11 - Delay after Transfer Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PDT     (18U)         //!< Bit position for SPI_CTARn_PDT.
+#define BM_SPI_CTARn_PDT     (0x000C0000U) //!< Bit mask for SPI_CTARn_PDT.
+#define BS_SPI_CTARn_PDT     (2U)          //!< Bit field size in bits for SPI_CTARn_PDT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PDT field.
+#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PDT.
+#define BF_SPI_CTARn_PDT(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PDT), uint32_t) & BM_SPI_CTARn_PDT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDT field to a new value.
+#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 00 - Delay after Transfer Prescaler value is 1.
+ * - 01 - Delay after Transfer Prescaler value is 3.
+ * - 10 - Delay after Transfer Prescaler value is 5.
+ * - 11 - Delay after Transfer Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PASC    (20U)         //!< Bit position for SPI_CTARn_PASC.
+#define BM_SPI_CTARn_PASC    (0x00300000U) //!< Bit mask for SPI_CTARn_PASC.
+#define BS_SPI_CTARn_PASC    (2U)          //!< Bit field size in bits for SPI_CTARn_PASC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PASC field.
+#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PASC.
+#define BF_SPI_CTARn_PASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PASC), uint32_t) & BM_SPI_CTARn_PASC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PASC field to a new value.
+#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 00 - PCS to SCK Prescaler value is 1.
+ * - 01 - PCS to SCK Prescaler value is 3.
+ * - 10 - PCS to SCK Prescaler value is 5.
+ * - 11 - PCS to SCK Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PCSSCK  (22U)         //!< Bit position for SPI_CTARn_PCSSCK.
+#define BM_SPI_CTARn_PCSSCK  (0x00C00000U) //!< Bit mask for SPI_CTARn_PCSSCK.
+#define BS_SPI_CTARn_PCSSCK  (2U)          //!< Bit field size in bits for SPI_CTARn_PCSSCK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PCSSCK field.
+#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PCSSCK.
+#define BF_SPI_CTARn_PCSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PCSSCK), uint32_t) & BM_SPI_CTARn_PCSSCK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCSSCK field to a new value.
+#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0 - Data is transferred MSB first.
+ * - 1 - Data is transferred LSB first.
+ */
+//@{
+#define BP_SPI_CTARn_LSBFE   (24U)         //!< Bit position for SPI_CTARn_LSBFE.
+#define BM_SPI_CTARn_LSBFE   (0x01000000U) //!< Bit mask for SPI_CTARn_LSBFE.
+#define BS_SPI_CTARn_LSBFE   (1U)          //!< Bit field size in bits for SPI_CTARn_LSBFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_LSBFE field.
+#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_LSBFE.
+#define BF_SPI_CTARn_LSBFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_LSBFE), uint32_t) & BM_SPI_CTARn_LSBFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LSBFE field to a new value.
+#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+//@{
+#define BP_SPI_CTARn_CPHA    (25U)         //!< Bit position for SPI_CTARn_CPHA.
+#define BM_SPI_CTARn_CPHA    (0x02000000U) //!< Bit mask for SPI_CTARn_CPHA.
+#define BS_SPI_CTARn_CPHA    (1U)          //!< Bit field size in bits for SPI_CTARn_CPHA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_CPHA field.
+#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_CPHA.
+#define BF_SPI_CTARn_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPHA), uint32_t) & BM_SPI_CTARn_CPHA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPHA field to a new value.
+#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0 - The inactive state value of SCK is low.
+ * - 1 - The inactive state value of SCK is high.
+ */
+//@{
+#define BP_SPI_CTARn_CPOL    (26U)         //!< Bit position for SPI_CTARn_CPOL.
+#define BM_SPI_CTARn_CPOL    (0x04000000U) //!< Bit mask for SPI_CTARn_CPOL.
+#define BS_SPI_CTARn_CPOL    (1U)          //!< Bit field size in bits for SPI_CTARn_CPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_CPOL field.
+#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_CPOL.
+#define BF_SPI_CTARn_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPOL), uint32_t) & BM_SPI_CTARn_CPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPOL field to a new value.
+#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+//@{
+#define BP_SPI_CTARn_FMSZ    (27U)         //!< Bit position for SPI_CTARn_FMSZ.
+#define BM_SPI_CTARn_FMSZ    (0x78000000U) //!< Bit mask for SPI_CTARn_FMSZ.
+#define BS_SPI_CTARn_FMSZ    (4U)          //!< Bit field size in bits for SPI_CTARn_FMSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_FMSZ field.
+#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_FMSZ.
+#define BF_SPI_CTARn_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_FMSZ), uint32_t) & BM_SPI_CTARn_FMSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FMSZ field to a new value.
+#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
+ *     Prescaler.
+ */
+//@{
+#define BP_SPI_CTARn_DBR     (31U)         //!< Bit position for SPI_CTARn_DBR.
+#define BM_SPI_CTARn_DBR     (0x80000000U) //!< Bit mask for SPI_CTARn_DBR.
+#define BS_SPI_CTARn_DBR     (1U)          //!< Bit field size in bits for SPI_CTARn_DBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_DBR field.
+#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_DBR.
+#define BF_SPI_CTARn_DBR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DBR), uint32_t) & BM_SPI_CTARn_DBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBR field to a new value.
+#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+typedef union _hw_spi_ctarn_slave
+{
+    uint32_t U;
+    struct _hw_spi_ctarn_slave_bitfields
+    {
+        uint32_t RESERVED0 : 25;       //!< [24:0]
+        uint32_t CPHA : 1;             //!< [25] Clock Phase
+        uint32_t CPOL : 1;             //!< [26] Clock Polarity
+        uint32_t FMSZ : 5;             //!< [31:27] Frame Size
+    } B;
+} hw_spi_ctarn_slave_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_CTARn_SLAVE register
+ */
+//@{
+#define HW_SPI_CTARn_SLAVE_COUNT (1U)
+
+#define HW_SPI_CTARn_SLAVE_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
+#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
+#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
+#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) |  (v)))
+#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
+#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_CTARn_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+//@{
+#define BP_SPI_CTARn_SLAVE_CPHA (25U)      //!< Bit position for SPI_CTARn_SLAVE_CPHA.
+#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPHA.
+#define BS_SPI_CTARn_SLAVE_CPHA (1U)       //!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field.
+#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA.
+#define BF_SPI_CTARn_SLAVE_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPHA), uint32_t) & BM_SPI_CTARn_SLAVE_CPHA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPHA field to a new value.
+#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0 - The inactive state value of SCK is low.
+ * - 1 - The inactive state value of SCK is high.
+ */
+//@{
+#define BP_SPI_CTARn_SLAVE_CPOL (26U)      //!< Bit position for SPI_CTARn_SLAVE_CPOL.
+#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPOL.
+#define BS_SPI_CTARn_SLAVE_CPOL (1U)       //!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field.
+#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL.
+#define BF_SPI_CTARn_SLAVE_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPOL), uint32_t) & BM_SPI_CTARn_SLAVE_CPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPOL field to a new value.
+#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+//@{
+#define BP_SPI_CTARn_SLAVE_FMSZ (27U)      //!< Bit position for SPI_CTARn_SLAVE_FMSZ.
+#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) //!< Bit mask for SPI_CTARn_SLAVE_FMSZ.
+#define BS_SPI_CTARn_SLAVE_FMSZ (5U)       //!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field.
+#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ.
+#define BF_SPI_CTARn_SLAVE_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_FMSZ), uint32_t) & BM_SPI_CTARn_SLAVE_FMSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FMSZ field to a new value.
+#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_SR - Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+typedef union _hw_spi_sr
+{
+    uint32_t U;
+    struct _hw_spi_sr_bitfields
+    {
+        uint32_t POPNXTPTR : 4;        //!< [3:0] Pop Next Pointer
+        uint32_t RXCTR : 4;            //!< [7:4] RX FIFO Counter
+        uint32_t TXNXTPTR : 4;         //!< [11:8] Transmit Next Pointer
+        uint32_t TXCTR : 4;            //!< [15:12] TX FIFO Counter
+        uint32_t RESERVED0 : 1;        //!< [16]
+        uint32_t RFDF : 1;             //!< [17] Receive FIFO Drain Flag
+        uint32_t RESERVED1 : 1;        //!< [18]
+        uint32_t RFOF : 1;             //!< [19] Receive FIFO Overflow Flag
+        uint32_t RESERVED2 : 5;        //!< [24:20]
+        uint32_t TFFF : 1;             //!< [25] Transmit FIFO Fill Flag
+        uint32_t RESERVED3 : 1;        //!< [26]
+        uint32_t TFUF : 1;             //!< [27] Transmit FIFO Underflow Flag
+        uint32_t EOQF : 1;             //!< [28] End of Queue Flag
+        uint32_t RESERVED4 : 1;        //!< [29]
+        uint32_t TXRXS : 1;            //!< [30] TX and RX Status
+        uint32_t TCF : 1;              //!< [31] Transfer Complete Flag
+    } B;
+} hw_spi_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+//@{
+#define HW_SPI_SR_ADDR(x)        (REGS_SPI_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_SR(x)             (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
+#define HW_SPI_SR_RD(x)          (HW_SPI_SR(x).U)
+#define HW_SPI_SR_WR(x, v)       (HW_SPI_SR(x).U = (v))
+#define HW_SPI_SR_SET(x, v)      (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) |  (v)))
+#define HW_SPI_SR_CLR(x, v)      (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
+#define HW_SPI_SR_TOG(x, v)      (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+//@{
+#define BP_SPI_SR_POPNXTPTR  (0U)          //!< Bit position for SPI_SR_POPNXTPTR.
+#define BM_SPI_SR_POPNXTPTR  (0x0000000FU) //!< Bit mask for SPI_SR_POPNXTPTR.
+#define BS_SPI_SR_POPNXTPTR  (4U)          //!< Bit field size in bits for SPI_SR_POPNXTPTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_POPNXTPTR field.
+#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+//@{
+#define BP_SPI_SR_RXCTR      (4U)          //!< Bit position for SPI_SR_RXCTR.
+#define BM_SPI_SR_RXCTR      (0x000000F0U) //!< Bit mask for SPI_SR_RXCTR.
+#define BS_SPI_SR_RXCTR      (4U)          //!< Bit field size in bits for SPI_SR_RXCTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_RXCTR field.
+#define BR_SPI_SR_RXCTR(x)   (HW_SPI_SR(x).B.RXCTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+//@{
+#define BP_SPI_SR_TXNXTPTR   (8U)          //!< Bit position for SPI_SR_TXNXTPTR.
+#define BM_SPI_SR_TXNXTPTR   (0x00000F00U) //!< Bit mask for SPI_SR_TXNXTPTR.
+#define BS_SPI_SR_TXNXTPTR   (4U)          //!< Bit field size in bits for SPI_SR_TXNXTPTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TXNXTPTR field.
+#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+//@{
+#define BP_SPI_SR_TXCTR      (12U)         //!< Bit position for SPI_SR_TXCTR.
+#define BM_SPI_SR_TXCTR      (0x0000F000U) //!< Bit mask for SPI_SR_TXCTR.
+#define BS_SPI_SR_TXCTR      (4U)          //!< Bit field size in bits for SPI_SR_TXCTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TXCTR field.
+#define BR_SPI_SR_TXCTR(x)   (HW_SPI_SR(x).B.TXCTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0 - RX FIFO is empty.
+ * - 1 - RX FIFO is not empty.
+ */
+//@{
+#define BP_SPI_SR_RFDF       (17U)         //!< Bit position for SPI_SR_RFDF.
+#define BM_SPI_SR_RFDF       (0x00020000U) //!< Bit mask for SPI_SR_RFDF.
+#define BS_SPI_SR_RFDF       (1U)          //!< Bit field size in bits for SPI_SR_RFDF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_RFDF field.
+#define BR_SPI_SR_RFDF(x)    (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_RFDF.
+#define BF_SPI_SR_RFDF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFDF), uint32_t) & BM_SPI_SR_RFDF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFDF field to a new value.
+#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - No Rx FIFO overflow.
+ * - 1 - Rx FIFO overflow has occurred.
+ */
+//@{
+#define BP_SPI_SR_RFOF       (19U)         //!< Bit position for SPI_SR_RFOF.
+#define BM_SPI_SR_RFOF       (0x00080000U) //!< Bit mask for SPI_SR_RFOF.
+#define BS_SPI_SR_RFOF       (1U)          //!< Bit field size in bits for SPI_SR_RFOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_RFOF field.
+#define BR_SPI_SR_RFOF(x)    (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_RFOF.
+#define BF_SPI_SR_RFOF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFOF), uint32_t) & BM_SPI_SR_RFOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFOF field to a new value.
+#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0 - TX FIFO is full.
+ * - 1 - TX FIFO is not full.
+ */
+//@{
+#define BP_SPI_SR_TFFF       (25U)         //!< Bit position for SPI_SR_TFFF.
+#define BM_SPI_SR_TFFF       (0x02000000U) //!< Bit mask for SPI_SR_TFFF.
+#define BS_SPI_SR_TFFF       (1U)          //!< Bit field size in bits for SPI_SR_TFFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TFFF field.
+#define BR_SPI_SR_TFFF(x)    (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TFFF.
+#define BF_SPI_SR_TFFF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFFF), uint32_t) & BM_SPI_SR_TFFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFFF field to a new value.
+#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No TX FIFO underflow.
+ * - 1 - TX FIFO underflow has occurred.
+ */
+//@{
+#define BP_SPI_SR_TFUF       (27U)         //!< Bit position for SPI_SR_TFUF.
+#define BM_SPI_SR_TFUF       (0x08000000U) //!< Bit mask for SPI_SR_TFUF.
+#define BS_SPI_SR_TFUF       (1U)          //!< Bit field size in bits for SPI_SR_TFUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TFUF field.
+#define BR_SPI_SR_TFUF(x)    (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TFUF.
+#define BF_SPI_SR_TFUF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFUF), uint32_t) & BM_SPI_SR_TFUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFUF field to a new value.
+#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0 - EOQ is not set in the executing command.
+ * - 1 - EOQ is set in the executing SPI command.
+ */
+//@{
+#define BP_SPI_SR_EOQF       (28U)         //!< Bit position for SPI_SR_EOQF.
+#define BM_SPI_SR_EOQF       (0x10000000U) //!< Bit mask for SPI_SR_EOQF.
+#define BS_SPI_SR_EOQF       (1U)          //!< Bit field size in bits for SPI_SR_EOQF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_EOQF field.
+#define BR_SPI_SR_EOQF(x)    (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_EOQF.
+#define BF_SPI_SR_EOQF(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_EOQF), uint32_t) & BM_SPI_SR_EOQF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOQF field to a new value.
+#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0 - Transmit and receive operations are disabled (The module is in Stopped
+ *     state).
+ * - 1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+//@{
+#define BP_SPI_SR_TXRXS      (30U)         //!< Bit position for SPI_SR_TXRXS.
+#define BM_SPI_SR_TXRXS      (0x40000000U) //!< Bit mask for SPI_SR_TXRXS.
+#define BS_SPI_SR_TXRXS      (1U)          //!< Bit field size in bits for SPI_SR_TXRXS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TXRXS field.
+#define BR_SPI_SR_TXRXS(x)   (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TXRXS.
+#define BF_SPI_SR_TXRXS(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TXRXS), uint32_t) & BM_SPI_SR_TXRXS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXRXS field to a new value.
+#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - Transfer not complete.
+ * - 1 - Transfer complete.
+ */
+//@{
+#define BP_SPI_SR_TCF        (31U)         //!< Bit position for SPI_SR_TCF.
+#define BM_SPI_SR_TCF        (0x80000000U) //!< Bit mask for SPI_SR_TCF.
+#define BS_SPI_SR_TCF        (1U)          //!< Bit field size in bits for SPI_SR_TCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TCF field.
+#define BR_SPI_SR_TCF(x)     (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TCF.
+#define BF_SPI_SR_TCF(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TCF), uint32_t) & BM_SPI_SR_TCF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCF field to a new value.
+#define BW_SPI_SR_TCF(x, v)  (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+typedef union _hw_spi_rser
+{
+    uint32_t U;
+    struct _hw_spi_rser_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t RFDF_DIRS : 1;        //!< [16] Receive FIFO Drain DMA or Interrupt
+                                       //! Request Select
+        uint32_t RFDF_RE : 1;          //!< [17] Receive FIFO Drain Request Enable
+        uint32_t RESERVED1 : 1;        //!< [18]
+        uint32_t RFOF_RE : 1;          //!< [19] Receive FIFO Overflow Request Enable
+        uint32_t RESERVED2 : 4;        //!< [23:20]
+        uint32_t TFFF_DIRS : 1;        //!< [24] Transmit FIFO Fill DMA or Interrupt
+                                       //! Request Select
+        uint32_t TFFF_RE : 1;          //!< [25] Transmit FIFO Fill Request Enable
+        uint32_t RESERVED3 : 1;        //!< [26]
+        uint32_t TFUF_RE : 1;          //!< [27] Transmit FIFO Underflow Request Enable
+        uint32_t EOQF_RE : 1;          //!< [28] Finished Request Enable
+        uint32_t RESERVED4 : 2;        //!< [30:29]
+        uint32_t TCF_RE : 1;           //!< [31] Transmission Complete Request Enable
+    } B;
+} hw_spi_rser_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+//@{
+#define HW_SPI_RSER_ADDR(x)      (REGS_SPI_BASE(x) + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_RSER(x)           (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
+#define HW_SPI_RSER_RD(x)        (HW_SPI_RSER(x).U)
+#define HW_SPI_RSER_WR(x, v)     (HW_SPI_RSER(x).U = (v))
+#define HW_SPI_RSER_SET(x, v)    (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) |  (v)))
+#define HW_SPI_RSER_CLR(x, v)    (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
+#define HW_SPI_RSER_TOG(x, v)    (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - Interrupt request.
+ * - 1 - DMA request.
+ */
+//@{
+#define BP_SPI_RSER_RFDF_DIRS (16U)        //!< Bit position for SPI_RSER_RFDF_DIRS.
+#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) //!< Bit mask for SPI_RSER_RFDF_DIRS.
+#define BS_SPI_RSER_RFDF_DIRS (1U)         //!< Bit field size in bits for SPI_RSER_RFDF_DIRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_RFDF_DIRS field.
+#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_RFDF_DIRS.
+#define BF_SPI_RSER_RFDF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_DIRS), uint32_t) & BM_SPI_RSER_RFDF_DIRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFDF_DIRS field to a new value.
+#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - RFDF interrupt or DMA requests are disabled.
+ * - 1 - RFDF interrupt or DMA requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_RFDF_RE  (17U)         //!< Bit position for SPI_RSER_RFDF_RE.
+#define BM_SPI_RSER_RFDF_RE  (0x00020000U) //!< Bit mask for SPI_RSER_RFDF_RE.
+#define BS_SPI_RSER_RFDF_RE  (1U)          //!< Bit field size in bits for SPI_RSER_RFDF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_RFDF_RE field.
+#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_RFDF_RE.
+#define BF_SPI_RSER_RFDF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_RE), uint32_t) & BM_SPI_RSER_RFDF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFDF_RE field to a new value.
+#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - RFOF interrupt requests are disabled.
+ * - 1 - RFOF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_RFOF_RE  (19U)         //!< Bit position for SPI_RSER_RFOF_RE.
+#define BM_SPI_RSER_RFOF_RE  (0x00080000U) //!< Bit mask for SPI_RSER_RFOF_RE.
+#define BS_SPI_RSER_RFOF_RE  (1U)          //!< Bit field size in bits for SPI_RSER_RFOF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_RFOF_RE field.
+#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_RFOF_RE.
+#define BF_SPI_RSER_RFOF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFOF_RE), uint32_t) & BM_SPI_RSER_RFOF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFOF_RE field to a new value.
+#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - TFFF flag generates interrupt requests.
+ * - 1 - TFFF flag generates DMA requests.
+ */
+//@{
+#define BP_SPI_RSER_TFFF_DIRS (24U)        //!< Bit position for SPI_RSER_TFFF_DIRS.
+#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) //!< Bit mask for SPI_RSER_TFFF_DIRS.
+#define BS_SPI_RSER_TFFF_DIRS (1U)         //!< Bit field size in bits for SPI_RSER_TFFF_DIRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TFFF_DIRS field.
+#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TFFF_DIRS.
+#define BF_SPI_RSER_TFFF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_DIRS), uint32_t) & BM_SPI_RSER_TFFF_DIRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFFF_DIRS field to a new value.
+#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - TFFF interrupts or DMA requests are disabled.
+ * - 1 - TFFF interrupts or DMA requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_TFFF_RE  (25U)         //!< Bit position for SPI_RSER_TFFF_RE.
+#define BM_SPI_RSER_TFFF_RE  (0x02000000U) //!< Bit mask for SPI_RSER_TFFF_RE.
+#define BS_SPI_RSER_TFFF_RE  (1U)          //!< Bit field size in bits for SPI_RSER_TFFF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TFFF_RE field.
+#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TFFF_RE.
+#define BF_SPI_RSER_TFFF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_RE), uint32_t) & BM_SPI_RSER_TFFF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFFF_RE field to a new value.
+#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - TFUF interrupt requests are disabled.
+ * - 1 - TFUF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_TFUF_RE  (27U)         //!< Bit position for SPI_RSER_TFUF_RE.
+#define BM_SPI_RSER_TFUF_RE  (0x08000000U) //!< Bit mask for SPI_RSER_TFUF_RE.
+#define BS_SPI_RSER_TFUF_RE  (1U)          //!< Bit field size in bits for SPI_RSER_TFUF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TFUF_RE field.
+#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TFUF_RE.
+#define BF_SPI_RSER_TFUF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFUF_RE), uint32_t) & BM_SPI_RSER_TFUF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFUF_RE field to a new value.
+#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - EOQF interrupt requests are disabled.
+ * - 1 - EOQF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_EOQF_RE  (28U)         //!< Bit position for SPI_RSER_EOQF_RE.
+#define BM_SPI_RSER_EOQF_RE  (0x10000000U) //!< Bit mask for SPI_RSER_EOQF_RE.
+#define BS_SPI_RSER_EOQF_RE  (1U)          //!< Bit field size in bits for SPI_RSER_EOQF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_EOQF_RE field.
+#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_EOQF_RE.
+#define BF_SPI_RSER_EOQF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_EOQF_RE), uint32_t) & BM_SPI_RSER_EOQF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOQF_RE field to a new value.
+#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - TCF interrupt requests are disabled.
+ * - 1 - TCF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_TCF_RE   (31U)         //!< Bit position for SPI_RSER_TCF_RE.
+#define BM_SPI_RSER_TCF_RE   (0x80000000U) //!< Bit mask for SPI_RSER_TCF_RE.
+#define BS_SPI_RSER_TCF_RE   (1U)          //!< Bit field size in bits for SPI_RSER_TCF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TCF_RE field.
+#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TCF_RE.
+#define BF_SPI_RSER_TCF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TCF_RE), uint32_t) & BM_SPI_RSER_TCF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCF_RE field to a new value.
+#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+typedef union _hw_spi_pushr
+{
+    uint32_t U;
+    struct _hw_spi_pushr_bitfields
+    {
+        uint32_t TXDATA : 16;          //!< [15:0] Transmit Data
+        uint32_t PCS : 6;              //!< [21:16]
+        uint32_t RESERVED0 : 4;        //!< [25:22]
+        uint32_t CTCNT : 1;            //!< [26] Clear Transfer Counter
+        uint32_t EOQ : 1;              //!< [27] End Of Queue
+        uint32_t CTAS : 3;             //!< [30:28] Clock and Transfer Attributes Select
+        uint32_t CONT : 1;             //!< [31] Continuous Peripheral Chip Select Enable
+    } B;
+} hw_spi_pushr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+//@{
+#define HW_SPI_PUSHR_ADDR(x)     (REGS_SPI_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_PUSHR(x)          (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
+#define HW_SPI_PUSHR_RD(x)       (HW_SPI_PUSHR(x).U)
+#define HW_SPI_PUSHR_WR(x, v)    (HW_SPI_PUSHR(x).U = (v))
+#define HW_SPI_PUSHR_SET(x, v)   (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) |  (v)))
+#define HW_SPI_PUSHR_CLR(x, v)   (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
+#define HW_SPI_PUSHR_TOG(x, v)   (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+//@{
+#define BP_SPI_PUSHR_TXDATA  (0U)          //!< Bit position for SPI_PUSHR_TXDATA.
+#define BM_SPI_PUSHR_TXDATA  (0x0000FFFFU) //!< Bit mask for SPI_PUSHR_TXDATA.
+#define BS_SPI_PUSHR_TXDATA  (16U)         //!< Bit field size in bits for SPI_PUSHR_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_TXDATA field.
+#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_TXDATA.
+#define BF_SPI_PUSHR_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_TXDATA), uint32_t) & BM_SPI_PUSHR_TXDATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXDATA field to a new value.
+#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0 - Negate the PCS[x] signal.
+ * - 1 - Assert the PCS[x] signal.
+ */
+//@{
+#define BP_SPI_PUSHR_PCS     (16U)         //!< Bit position for SPI_PUSHR_PCS.
+#define BM_SPI_PUSHR_PCS     (0x003F0000U) //!< Bit mask for SPI_PUSHR_PCS.
+#define BS_SPI_PUSHR_PCS     (6U)          //!< Bit field size in bits for SPI_PUSHR_PCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_PCS field.
+#define BR_SPI_PUSHR_PCS(x)  (HW_SPI_PUSHR(x).B.PCS)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_PCS.
+#define BF_SPI_PUSHR_PCS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_PCS), uint32_t) & BM_SPI_PUSHR_PCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCS field to a new value.
+#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0 - Do not clear the TCR[TCNT] field.
+ * - 1 - Clear the TCR[TCNT] field.
+ */
+//@{
+#define BP_SPI_PUSHR_CTCNT   (26U)         //!< Bit position for SPI_PUSHR_CTCNT.
+#define BM_SPI_PUSHR_CTCNT   (0x04000000U) //!< Bit mask for SPI_PUSHR_CTCNT.
+#define BS_SPI_PUSHR_CTCNT   (1U)          //!< Bit field size in bits for SPI_PUSHR_CTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_CTCNT field.
+#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_CTCNT.
+#define BF_SPI_PUSHR_CTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTCNT), uint32_t) & BM_SPI_PUSHR_CTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTCNT field to a new value.
+#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0 - The SPI data is not the last data to transfer.
+ * - 1 - The SPI data is the last data to transfer.
+ */
+//@{
+#define BP_SPI_PUSHR_EOQ     (27U)         //!< Bit position for SPI_PUSHR_EOQ.
+#define BM_SPI_PUSHR_EOQ     (0x08000000U) //!< Bit mask for SPI_PUSHR_EOQ.
+#define BS_SPI_PUSHR_EOQ     (1U)          //!< Bit field size in bits for SPI_PUSHR_EOQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_EOQ field.
+#define BR_SPI_PUSHR_EOQ(x)  (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_EOQ.
+#define BF_SPI_PUSHR_EOQ(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_EOQ), uint32_t) & BM_SPI_PUSHR_EOQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOQ field to a new value.
+#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 000 - CTAR0
+ * - 001 - CTAR1
+ * - 010 - Reserved
+ * - 011 - Reserved
+ * - 100 - Reserved
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SPI_PUSHR_CTAS    (28U)         //!< Bit position for SPI_PUSHR_CTAS.
+#define BM_SPI_PUSHR_CTAS    (0x70000000U) //!< Bit mask for SPI_PUSHR_CTAS.
+#define BS_SPI_PUSHR_CTAS    (3U)          //!< Bit field size in bits for SPI_PUSHR_CTAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_CTAS field.
+#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_CTAS.
+#define BF_SPI_PUSHR_CTAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTAS), uint32_t) & BM_SPI_PUSHR_CTAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTAS field to a new value.
+#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0 - Return PCSn signals to their inactive state between transfers.
+ * - 1 - Keep PCSn signals asserted between transfers.
+ */
+//@{
+#define BP_SPI_PUSHR_CONT    (31U)         //!< Bit position for SPI_PUSHR_CONT.
+#define BM_SPI_PUSHR_CONT    (0x80000000U) //!< Bit mask for SPI_PUSHR_CONT.
+#define BS_SPI_PUSHR_CONT    (1U)          //!< Bit field size in bits for SPI_PUSHR_CONT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_CONT field.
+#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_CONT.
+#define BF_SPI_PUSHR_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CONT), uint32_t) & BM_SPI_PUSHR_CONT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CONT field to a new value.
+#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+typedef union _hw_spi_pushr_slave
+{
+    uint32_t U;
+    struct _hw_spi_pushr_slave_bitfields
+    {
+        uint32_t TXDATA : 32;          //!< [31:0] Transmit Data
+    } B;
+} hw_spi_pushr_slave_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+//@{
+#define HW_SPI_PUSHR_SLAVE_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_PUSHR_SLAVE(x)    (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
+#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
+#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
+#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) |  (v)))
+#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
+#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+//@{
+#define BP_SPI_PUSHR_SLAVE_TXDATA (0U)     //!< Bit position for SPI_PUSHR_SLAVE_TXDATA.
+#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_PUSHR_SLAVE_TXDATA.
+#define BS_SPI_PUSHR_SLAVE_TXDATA (32U)    //!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field.
+#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA.
+#define BF_SPI_PUSHR_SLAVE_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_SLAVE_TXDATA), uint32_t) & BM_SPI_PUSHR_SLAVE_TXDATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXDATA field to a new value.
+#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_POPR - POP RX FIFO Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+typedef union _hw_spi_popr
+{
+    uint32_t U;
+    struct _hw_spi_popr_bitfields
+    {
+        uint32_t RXDATA : 32;          //!< [31:0] Received Data
+    } B;
+} hw_spi_popr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+//@{
+#define HW_SPI_POPR_ADDR(x)      (REGS_SPI_BASE(x) + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_POPR(x)           (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
+#define HW_SPI_POPR_RD(x)        (HW_SPI_POPR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_POPR bitfields
+ */
+
+/*!
+ * @name Register SPI_POPR, field RXDATA[31:0] (RO)
+ *
+ * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
+ * Pointer points.
+ */
+//@{
+#define BP_SPI_POPR_RXDATA   (0U)          //!< Bit position for SPI_POPR_RXDATA.
+#define BM_SPI_POPR_RXDATA   (0xFFFFFFFFU) //!< Bit mask for SPI_POPR_RXDATA.
+#define BS_SPI_POPR_RXDATA   (32U)         //!< Bit field size in bits for SPI_POPR_RXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_POPR_RXDATA field.
+#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_TXFRn - Transmit FIFO Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+typedef union _hw_spi_txfrn
+{
+    uint32_t U;
+    struct _hw_spi_txfrn_bitfields
+    {
+        uint32_t TXDATA : 16;          //!< [15:0] Transmit Data
+        uint32_t TXCMD_TXDATA : 16;    //!< [31:16] Transmit Command or Transmit
+                                       //! Data
+    } B;
+} hw_spi_txfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_TXFRn register
+ */
+//@{
+#define HW_SPI_TXFRn_COUNT (4U)
+
+#define HW_SPI_TXFRn_ADDR(x, n)  (REGS_SPI_BASE(x) + 0x3CU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_TXFRn(x, n)       (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
+#define HW_SPI_TXFRn_RD(x, n)    (HW_SPI_TXFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_TXFRn bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+//@{
+#define BP_SPI_TXFRn_TXDATA  (0U)          //!< Bit position for SPI_TXFRn_TXDATA.
+#define BM_SPI_TXFRn_TXDATA  (0x0000FFFFU) //!< Bit mask for SPI_TXFRn_TXDATA.
+#define BS_SPI_TXFRn_TXDATA  (16U)         //!< Bit field size in bits for SPI_TXFRn_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_TXFRn_TXDATA field.
+#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+//@{
+#define BP_SPI_TXFRn_TXCMD_TXDATA (16U)    //!< Bit position for SPI_TXFRn_TXCMD_TXDATA.
+#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) //!< Bit mask for SPI_TXFRn_TXCMD_TXDATA.
+#define BS_SPI_TXFRn_TXCMD_TXDATA (16U)    //!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field.
+#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_RXFRn - Receive FIFO Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+typedef union _hw_spi_rxfrn
+{
+    uint32_t U;
+    struct _hw_spi_rxfrn_bitfields
+    {
+        uint32_t RXDATA : 32;          //!< [31:0] Receive Data
+    } B;
+} hw_spi_rxfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_RXFRn register
+ */
+//@{
+#define HW_SPI_RXFRn_COUNT (4U)
+
+#define HW_SPI_RXFRn_ADDR(x, n)  (REGS_SPI_BASE(x) + 0x7CU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_RXFRn(x, n)       (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
+#define HW_SPI_RXFRn_RD(x, n)    (HW_SPI_RXFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_RXFRn bitfields
+ */
+
+/*!
+ * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
+ *
+ * Contains the received SPI data.
+ */
+//@{
+#define BP_SPI_RXFRn_RXDATA  (0U)          //!< Bit position for SPI_RXFRn_RXDATA.
+#define BM_SPI_RXFRn_RXDATA  (0xFFFFFFFFU) //!< Bit mask for SPI_RXFRn_RXDATA.
+#define BS_SPI_RXFRn_RXDATA  (32U)         //!< Bit field size in bits for SPI_RXFRn_RXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RXFRn_RXDATA field.
+#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_spi_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SPI module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_spi
+{
+    __IO hw_spi_mcr_t MCR;                 //!< [0x0] Module Configuration Register
+    uint8_t _reserved0[4];
+    __IO hw_spi_tcr_t TCR;                 //!< [0x8] Transfer Count Register
+    union {
+        __IO hw_spi_ctarn_t CTARn[2];      //!< [0xC] Clock and Transfer Attributes Register (In Master Mode)
+        __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; //!< [0xC] Clock and Transfer Attributes Register (In Slave Mode)
+    };
+    uint8_t _reserved1[24];
+    __IO hw_spi_sr_t SR;                   //!< [0x2C] Status Register
+    __IO hw_spi_rser_t RSER;               //!< [0x30] DMA/Interrupt Request Select and Enable Register
+    union {
+        __IO hw_spi_pushr_t PUSHR;         //!< [0x34] PUSH TX FIFO Register In Master Mode
+        __IO hw_spi_pushr_slave_t PUSHR_SLAVE; //!< [0x34] PUSH TX FIFO Register In Slave Mode
+    };
+    __I hw_spi_popr_t POPR;                //!< [0x38] POP RX FIFO Register
+    __I hw_spi_txfrn_t TXFRn[4];           //!< [0x3C] Transmit FIFO Registers
+    uint8_t _reserved2[48];
+    __I hw_spi_rxfrn_t RXFRn[4];           //!< [0x7C] Receive FIFO Registers
+} hw_spi_t;
+#pragma pack()
+
+//! @brief Macro to access all SPI registers.
+//! @param x SPI instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_SPI(0)</code>.
+#define HW_SPI(x)      (*(hw_spi_t *) REGS_SPI_BASE(x))
+#endif
+
+#endif // __HW_SPI_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h
new file mode 100644
index 0000000000..368380bf20
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h
@@ -0,0 +1,4933 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_UART_REGISTERS_H__
+#define __HW_UART_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - HW_UART_BDH - UART Baud Rate Registers: High
+ * - HW_UART_BDL - UART Baud Rate Registers: Low
+ * - HW_UART_C1 - UART Control Register 1
+ * - HW_UART_C2 - UART Control Register 2
+ * - HW_UART_S1 - UART Status Register 1
+ * - HW_UART_S2 - UART Status Register 2
+ * - HW_UART_C3 - UART Control Register 3
+ * - HW_UART_D - UART Data Register
+ * - HW_UART_MA1 - UART Match Address Registers 1
+ * - HW_UART_MA2 - UART Match Address Registers 2
+ * - HW_UART_C4 - UART Control Register 4
+ * - HW_UART_C5 - UART Control Register 5
+ * - HW_UART_ED - UART Extended Data Register
+ * - HW_UART_MODEM - UART Modem Register
+ * - HW_UART_IR - UART Infrared Register
+ * - HW_UART_PFIFO - UART FIFO Parameters
+ * - HW_UART_CFIFO - UART FIFO Control Register
+ * - HW_UART_SFIFO - UART FIFO Status Register
+ * - HW_UART_TWFIFO - UART FIFO Transmit Watermark
+ * - HW_UART_TCFIFO - UART FIFO Transmit Count
+ * - HW_UART_RWFIFO - UART FIFO Receive Watermark
+ * - HW_UART_RCFIFO - UART FIFO Receive Count
+ * - HW_UART_C7816 - UART 7816 Control Register
+ * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - HW_UART_IS7816 - UART 7816 Interrupt Status Register
+ * - HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
+ * - HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
+ * - HW_UART_WN7816 - UART 7816 Wait N Register
+ * - HW_UART_WF7816 - UART 7816 Wait FD Register
+ * - HW_UART_ET7816 - UART 7816 Error Threshold Register
+ * - HW_UART_TL7816 - UART 7816 Transmit Length Register
+ *
+ * - hw_uart_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_UART_BASE
+#define HW_UART_INSTANCE_COUNT (6U) //!< Number of instances of the UART module.
+#define HW_UART0 (0U) //!< Instance number for UART0.
+#define HW_UART1 (1U) //!< Instance number for UART1.
+#define HW_UART2 (2U) //!< Instance number for UART2.
+#define HW_UART3 (3U) //!< Instance number for UART3.
+#define HW_UART4 (4U) //!< Instance number for UART4.
+#define HW_UART5 (5U) //!< Instance number for UART5.
+#define REGS_UART0_BASE (0x4006A000U) //!< Base address for UART0.
+#define REGS_UART1_BASE (0x4006B000U) //!< Base address for UART1.
+#define REGS_UART2_BASE (0x4006C000U) //!< Base address for UART2.
+#define REGS_UART3_BASE (0x4006D000U) //!< Base address for UART3.
+#define REGS_UART4_BASE (0x400EA000U) //!< Base address for UART4.
+#define REGS_UART5_BASE (0x400EB000U) //!< Base address for UART5.
+
+//! @brief Table of base addresses for UART instances.
+static const uint32_t __g_regs_UART_base_addresses[] = {
+        REGS_UART0_BASE,
+        REGS_UART1_BASE,
+        REGS_UART2_BASE,
+        REGS_UART3_BASE,
+        REGS_UART4_BASE,
+        REGS_UART5_BASE,
+    };
+
+//! @brief Get the base address of UART by instance number.
+//! @param x UART instance number, from 0 through 5.
+#define REGS_UART_BASE(x) (__g_regs_UART_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of UART.
+#define REGS_UART_INSTANCE(b) ((b) == REGS_UART0_BASE ? HW_UART0 : (b) == REGS_UART1_BASE ? HW_UART1 : (b) == REGS_UART2_BASE ? HW_UART2 : (b) == REGS_UART3_BASE ? HW_UART3 : (b) == REGS_UART4_BASE ? HW_UART4 : (b) == REGS_UART5_BASE ? HW_UART5 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_BDH - UART Baud Rate Registers: High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+typedef union _hw_uart_bdh
+{
+    uint8_t U;
+    struct _hw_uart_bdh_bitfields
+    {
+        uint8_t SBR : 5;               //!< [4:0] UART Baud Rate Bits
+        uint8_t SBNS : 1;              //!< [5] Stop Bit Number Select
+        uint8_t RXEDGIE : 1;           //!< [6] RxD Input Active Edge Interrupt Enable
+        uint8_t LBKDIE : 1;            //!< [7] LIN Break Detect Interrupt or DMA
+                                       //! Request Enable
+    } B;
+} hw_uart_bdh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+//@{
+#define HW_UART_BDH_ADDR(x)      (REGS_UART_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_BDH(x)           (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x))
+#define HW_UART_BDH_RD(x)        (HW_UART_BDH(x).U)
+#define HW_UART_BDH_WR(x, v)     (HW_UART_BDH(x).U = (v))
+#define HW_UART_BDH_SET(x, v)    (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) |  (v)))
+#define HW_UART_BDH_CLR(x, v)    (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
+#define HW_UART_BDH_TOG(x, v)    (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+//@{
+#define BP_UART_BDH_SBR      (0U)          //!< Bit position for UART_BDH_SBR.
+#define BM_UART_BDH_SBR      (0x1FU)       //!< Bit mask for UART_BDH_SBR.
+#define BS_UART_BDH_SBR      (5U)          //!< Bit field size in bits for UART_BDH_SBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_SBR field.
+#define BR_UART_BDH_SBR(x)   (HW_UART_BDH(x).B.SBR)
+#endif
+
+//! @brief Format value for bitfield UART_BDH_SBR.
+#define BF_UART_BDH_SBR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBR), uint8_t) & BM_UART_BDH_SBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBR field to a new value.
+#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0 - Data frame consists of a single stop bit.
+ * - 1 - Data frame consists of two stop bits.
+ */
+//@{
+#define BP_UART_BDH_SBNS     (5U)          //!< Bit position for UART_BDH_SBNS.
+#define BM_UART_BDH_SBNS     (0x20U)       //!< Bit mask for UART_BDH_SBNS.
+#define BS_UART_BDH_SBNS     (1U)          //!< Bit field size in bits for UART_BDH_SBNS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_SBNS field.
+#define BR_UART_BDH_SBNS(x)  (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
+#endif
+
+//! @brief Format value for bitfield UART_BDH_SBNS.
+#define BF_UART_BDH_SBNS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBNS), uint8_t) & BM_UART_BDH_SBNS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBNS field to a new value.
+#define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 1 - RXEDGIF interrupt request enabled.
+ */
+//@{
+#define BP_UART_BDH_RXEDGIE  (6U)          //!< Bit position for UART_BDH_RXEDGIE.
+#define BM_UART_BDH_RXEDGIE  (0x40U)       //!< Bit mask for UART_BDH_RXEDGIE.
+#define BS_UART_BDH_RXEDGIE  (1U)          //!< Bit field size in bits for UART_BDH_RXEDGIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_RXEDGIE field.
+#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
+#endif
+
+//! @brief Format value for bitfield UART_BDH_RXEDGIE.
+#define BF_UART_BDH_RXEDGIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_RXEDGIE), uint8_t) & BM_UART_BDH_RXEDGIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXEDGIE field to a new value.
+#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_BDH_LBKDIE   (7U)          //!< Bit position for UART_BDH_LBKDIE.
+#define BM_UART_BDH_LBKDIE   (0x80U)       //!< Bit mask for UART_BDH_LBKDIE.
+#define BS_UART_BDH_LBKDIE   (1U)          //!< Bit field size in bits for UART_BDH_LBKDIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_LBKDIE field.
+#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
+#endif
+
+//! @brief Format value for bitfield UART_BDH_LBKDIE.
+#define BF_UART_BDH_LBKDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_LBKDIE), uint8_t) & BM_UART_BDH_LBKDIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDIE field to a new value.
+#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_BDL - UART Baud Rate Registers: Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+typedef union _hw_uart_bdl
+{
+    uint8_t U;
+    struct _hw_uart_bdl_bitfields
+    {
+        uint8_t SBR : 8;               //!< [7:0] UART Baud Rate Bits
+    } B;
+} hw_uart_bdl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+//@{
+#define HW_UART_BDL_ADDR(x)      (REGS_UART_BASE(x) + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_BDL(x)           (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x))
+#define HW_UART_BDL_RD(x)        (HW_UART_BDL(x).U)
+#define HW_UART_BDL_WR(x, v)     (HW_UART_BDL(x).U = (v))
+#define HW_UART_BDL_SET(x, v)    (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) |  (v)))
+#define HW_UART_BDL_CLR(x, v)    (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
+#define HW_UART_BDL_TOG(x, v)    (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_BDL bitfields
+ */
+
+/*!
+ * @name Register UART_BDL, field SBR[7:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written. When
+ * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
+ * fields must be even, the least significant bit is 0. See MODEM register for more
+ * details.
+ */
+//@{
+#define BP_UART_BDL_SBR      (0U)          //!< Bit position for UART_BDL_SBR.
+#define BM_UART_BDL_SBR      (0xFFU)       //!< Bit mask for UART_BDL_SBR.
+#define BS_UART_BDL_SBR      (8U)          //!< Bit field size in bits for UART_BDL_SBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDL_SBR field.
+#define BR_UART_BDL_SBR(x)   (HW_UART_BDL(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_BDL_SBR.
+#define BF_UART_BDL_SBR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDL_SBR), uint8_t) & BM_UART_BDL_SBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBR field to a new value.
+#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C1 - UART Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+typedef union _hw_uart_c1
+{
+    uint8_t U;
+    struct _hw_uart_c1_bitfields
+    {
+        uint8_t PT : 1;                //!< [0] Parity Type
+        uint8_t PE : 1;                //!< [1] Parity Enable
+        uint8_t ILT : 1;               //!< [2] Idle Line Type Select
+        uint8_t WAKE : 1;              //!< [3] Receiver Wakeup Method Select
+        uint8_t M : 1;                 //!< [4] 9-bit or 8-bit Mode Select
+        uint8_t RSRC : 1;              //!< [5] Receiver Source Select
+        uint8_t UARTSWAI : 1;          //!< [6] UART Stops in Wait Mode
+        uint8_t LOOPS : 1;             //!< [7] Loop Mode Select
+    } B;
+} hw_uart_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+//@{
+#define HW_UART_C1_ADDR(x)       (REGS_UART_BASE(x) + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C1(x)            (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x))
+#define HW_UART_C1_RD(x)         (HW_UART_C1(x).U)
+#define HW_UART_C1_WR(x, v)      (HW_UART_C1(x).U = (v))
+#define HW_UART_C1_SET(x, v)     (HW_UART_C1_WR(x, HW_UART_C1_RD(x) |  (v)))
+#define HW_UART_C1_CLR(x, v)     (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
+#define HW_UART_C1_TOG(x, v)     (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Even parity.
+ * - 1 - Odd parity.
+ */
+//@{
+#define BP_UART_C1_PT        (0U)          //!< Bit position for UART_C1_PT.
+#define BM_UART_C1_PT        (0x01U)       //!< Bit mask for UART_C1_PT.
+#define BS_UART_C1_PT        (1U)          //!< Bit field size in bits for UART_C1_PT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_PT field.
+#define BR_UART_C1_PT(x)     (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
+#endif
+
+//! @brief Format value for bitfield UART_C1_PT.
+#define BF_UART_C1_PT(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PT), uint8_t) & BM_UART_C1_PT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PT field to a new value.
+#define BW_UART_C1_PT(x, v)  (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Parity function disabled.
+ * - 1 - Parity function enabled.
+ */
+//@{
+#define BP_UART_C1_PE        (1U)          //!< Bit position for UART_C1_PE.
+#define BM_UART_C1_PE        (0x02U)       //!< Bit mask for UART_C1_PE.
+#define BS_UART_C1_PE        (1U)          //!< Bit field size in bits for UART_C1_PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_PE field.
+#define BR_UART_C1_PE(x)     (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
+#endif
+
+//! @brief Format value for bitfield UART_C1_PE.
+#define BF_UART_C1_PE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PE), uint8_t) & BM_UART_C1_PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PE field to a new value.
+#define BW_UART_C1_PE(x, v)  (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0 - Idle character bit count starts after start bit.
+ * - 1 - Idle character bit count starts after stop bit.
+ */
+//@{
+#define BP_UART_C1_ILT       (2U)          //!< Bit position for UART_C1_ILT.
+#define BM_UART_C1_ILT       (0x04U)       //!< Bit mask for UART_C1_ILT.
+#define BS_UART_C1_ILT       (1U)          //!< Bit field size in bits for UART_C1_ILT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_ILT field.
+#define BR_UART_C1_ILT(x)    (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
+#endif
+
+//! @brief Format value for bitfield UART_C1_ILT.
+#define BF_UART_C1_ILT(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_ILT), uint8_t) & BM_UART_C1_ILT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ILT field to a new value.
+#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0 - Idle line wakeup.
+ * - 1 - Address mark wakeup.
+ */
+//@{
+#define BP_UART_C1_WAKE      (3U)          //!< Bit position for UART_C1_WAKE.
+#define BM_UART_C1_WAKE      (0x08U)       //!< Bit mask for UART_C1_WAKE.
+#define BS_UART_C1_WAKE      (1U)          //!< Bit field size in bits for UART_C1_WAKE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_WAKE field.
+#define BR_UART_C1_WAKE(x)   (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
+#endif
+
+//! @brief Format value for bitfield UART_C1_WAKE.
+#define BF_UART_C1_WAKE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_WAKE), uint8_t) & BM_UART_C1_WAKE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKE field to a new value.
+#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
+ * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+//@{
+#define BP_UART_C1_M         (4U)          //!< Bit position for UART_C1_M.
+#define BM_UART_C1_M         (0x10U)       //!< Bit mask for UART_C1_M.
+#define BS_UART_C1_M         (1U)          //!< Bit field size in bits for UART_C1_M.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_M field.
+#define BR_UART_C1_M(x)      (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
+#endif
+
+//! @brief Format value for bitfield UART_C1_M.
+#define BF_UART_C1_M(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_M), uint8_t) & BM_UART_C1_M)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M field to a new value.
+#define BW_UART_C1_M(x, v)   (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+//@{
+#define BP_UART_C1_RSRC      (5U)          //!< Bit position for UART_C1_RSRC.
+#define BM_UART_C1_RSRC      (0x20U)       //!< Bit mask for UART_C1_RSRC.
+#define BS_UART_C1_RSRC      (1U)          //!< Bit field size in bits for UART_C1_RSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_RSRC field.
+#define BR_UART_C1_RSRC(x)   (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
+#endif
+
+//! @brief Format value for bitfield UART_C1_RSRC.
+#define BF_UART_C1_RSRC(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_RSRC), uint8_t) & BM_UART_C1_RSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSRC field to a new value.
+#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0 - UART clock continues to run in Wait mode.
+ * - 1 - UART clock freezes while CPU is in Wait mode.
+ */
+//@{
+#define BP_UART_C1_UARTSWAI  (6U)          //!< Bit position for UART_C1_UARTSWAI.
+#define BM_UART_C1_UARTSWAI  (0x40U)       //!< Bit mask for UART_C1_UARTSWAI.
+#define BS_UART_C1_UARTSWAI  (1U)          //!< Bit field size in bits for UART_C1_UARTSWAI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_UARTSWAI field.
+#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
+#endif
+
+//! @brief Format value for bitfield UART_C1_UARTSWAI.
+#define BF_UART_C1_UARTSWAI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_UARTSWAI), uint8_t) & BM_UART_C1_UARTSWAI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UARTSWAI field to a new value.
+#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - Loop mode where transmitter output is internally connected to receiver
+ *     input. The receiver input is determined by RSRC.
+ */
+//@{
+#define BP_UART_C1_LOOPS     (7U)          //!< Bit position for UART_C1_LOOPS.
+#define BM_UART_C1_LOOPS     (0x80U)       //!< Bit mask for UART_C1_LOOPS.
+#define BS_UART_C1_LOOPS     (1U)          //!< Bit field size in bits for UART_C1_LOOPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_LOOPS field.
+#define BR_UART_C1_LOOPS(x)  (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
+#endif
+
+//! @brief Format value for bitfield UART_C1_LOOPS.
+#define BF_UART_C1_LOOPS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_LOOPS), uint8_t) & BM_UART_C1_LOOPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOOPS field to a new value.
+#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C2 - UART Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+typedef union _hw_uart_c2
+{
+    uint8_t U;
+    struct _hw_uart_c2_bitfields
+    {
+        uint8_t SBK : 1;               //!< [0] Send Break
+        uint8_t RWU : 1;               //!< [1] Receiver Wakeup Control
+        uint8_t RE : 1;                //!< [2] Receiver Enable
+        uint8_t TE : 1;                //!< [3] Transmitter Enable
+        uint8_t ILIE : 1;              //!< [4] Idle Line Interrupt DMA Transfer Enable
+        uint8_t RIE : 1;               //!< [5] Receiver Full Interrupt or DMA Transfer
+                                       //! Enable
+        uint8_t TCIE : 1;              //!< [6] Transmission Complete Interrupt or DMA
+                                       //! Transfer Enable
+        uint8_t TIE : 1;               //!< [7] Transmitter Interrupt or DMA Transfer
+                                       //! Enable.
+    } B;
+} hw_uart_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+//@{
+#define HW_UART_C2_ADDR(x)       (REGS_UART_BASE(x) + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C2(x)            (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x))
+#define HW_UART_C2_RD(x)         (HW_UART_C2(x).U)
+#define HW_UART_C2_WR(x, v)      (HW_UART_C2(x).U = (v))
+#define HW_UART_C2_SET(x, v)     (HW_UART_C2_WR(x, HW_UART_C2_RD(x) |  (v)))
+#define HW_UART_C2_CLR(x, v)     (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
+#define HW_UART_C2_TOG(x, v)     (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0 - Normal transmitter operation.
+ * - 1 - Queue break characters to be sent.
+ */
+//@{
+#define BP_UART_C2_SBK       (0U)          //!< Bit position for UART_C2_SBK.
+#define BM_UART_C2_SBK       (0x01U)       //!< Bit mask for UART_C2_SBK.
+#define BS_UART_C2_SBK       (1U)          //!< Bit field size in bits for UART_C2_SBK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_SBK field.
+#define BR_UART_C2_SBK(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
+#endif
+
+//! @brief Format value for bitfield UART_C2_SBK.
+#define BF_UART_C2_SBK(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_SBK), uint8_t) & BM_UART_C2_SBK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBK field to a new value.
+#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
+ *     requests. Normally, hardware wakes the receiver by automatically clearing
+ *     RWU.
+ */
+//@{
+#define BP_UART_C2_RWU       (1U)          //!< Bit position for UART_C2_RWU.
+#define BM_UART_C2_RWU       (0x02U)       //!< Bit mask for UART_C2_RWU.
+#define BS_UART_C2_RWU       (1U)          //!< Bit field size in bits for UART_C2_RWU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_RWU field.
+#define BR_UART_C2_RWU(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
+#endif
+
+//! @brief Format value for bitfield UART_C2_RWU.
+#define BF_UART_C2_RWU(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RWU), uint8_t) & BM_UART_C2_RWU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWU field to a new value.
+#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0 - Receiver off.
+ * - 1 - Receiver on.
+ */
+//@{
+#define BP_UART_C2_RE        (2U)          //!< Bit position for UART_C2_RE.
+#define BM_UART_C2_RE        (0x04U)       //!< Bit mask for UART_C2_RE.
+#define BS_UART_C2_RE        (1U)          //!< Bit field size in bits for UART_C2_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_RE field.
+#define BR_UART_C2_RE(x)     (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_RE.
+#define BF_UART_C2_RE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RE), uint8_t) & BM_UART_C2_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RE field to a new value.
+#define BW_UART_C2_RE(x, v)  (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0 - Transmitter off.
+ * - 1 - Transmitter on.
+ */
+//@{
+#define BP_UART_C2_TE        (3U)          //!< Bit position for UART_C2_TE.
+#define BM_UART_C2_TE        (0x08U)       //!< Bit mask for UART_C2_TE.
+#define BS_UART_C2_TE        (1U)          //!< Bit field size in bits for UART_C2_TE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_TE field.
+#define BR_UART_C2_TE(x)     (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_TE.
+#define BF_UART_C2_TE(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TE), uint8_t) & BM_UART_C2_TE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TE field to a new value.
+#define BW_UART_C2_TE(x, v)  (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+//@{
+#define BP_UART_C2_ILIE      (4U)          //!< Bit position for UART_C2_ILIE.
+#define BM_UART_C2_ILIE      (0x10U)       //!< Bit mask for UART_C2_ILIE.
+#define BS_UART_C2_ILIE      (1U)          //!< Bit field size in bits for UART_C2_ILIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_ILIE field.
+#define BR_UART_C2_ILIE(x)   (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_ILIE.
+#define BF_UART_C2_ILIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_ILIE), uint8_t) & BM_UART_C2_ILIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ILIE field to a new value.
+#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_C2_RIE       (5U)          //!< Bit position for UART_C2_RIE.
+#define BM_UART_C2_RIE       (0x20U)       //!< Bit mask for UART_C2_RIE.
+#define BS_UART_C2_RIE       (1U)          //!< Bit field size in bits for UART_C2_RIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_RIE field.
+#define BR_UART_C2_RIE(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_RIE.
+#define BF_UART_C2_RIE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RIE), uint8_t) & BM_UART_C2_RIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RIE field to a new value.
+#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0 - TC interrupt and DMA transfer requests disabled.
+ * - 1 - TC interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_C2_TCIE      (6U)          //!< Bit position for UART_C2_TCIE.
+#define BM_UART_C2_TCIE      (0x40U)       //!< Bit mask for UART_C2_TCIE.
+#define BS_UART_C2_TCIE      (1U)          //!< Bit field size in bits for UART_C2_TCIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_TCIE field.
+#define BR_UART_C2_TCIE(x)   (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_TCIE.
+#define BF_UART_C2_TCIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TCIE), uint8_t) & BM_UART_C2_TCIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCIE field to a new value.
+#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_C2_TIE       (7U)          //!< Bit position for UART_C2_TIE.
+#define BM_UART_C2_TIE       (0x80U)       //!< Bit mask for UART_C2_TIE.
+#define BS_UART_C2_TIE       (1U)          //!< Bit field size in bits for UART_C2_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_TIE field.
+#define BR_UART_C2_TIE(x)    (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_TIE.
+#define BF_UART_C2_TIE(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TIE), uint8_t) & BM_UART_C2_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_S1 - UART Status Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+typedef union _hw_uart_s1
+{
+    uint8_t U;
+    struct _hw_uart_s1_bitfields
+    {
+        uint8_t PF : 1;                //!< [0] Parity Error Flag
+        uint8_t FE : 1;                //!< [1] Framing Error Flag
+        uint8_t NF : 1;                //!< [2] Noise Flag
+        uint8_t OR : 1;                //!< [3] Receiver Overrun Flag
+        uint8_t IDLE : 1;              //!< [4] Idle Line Flag
+        uint8_t RDRF : 1;              //!< [5] Receive Data Register Full Flag
+        uint8_t TC : 1;                //!< [6] Transmit Complete Flag
+        uint8_t TDRE : 1;              //!< [7] Transmit Data Register Empty Flag
+    } B;
+} hw_uart_s1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+//@{
+#define HW_UART_S1_ADDR(x)       (REGS_UART_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_S1(x)            (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x))
+#define HW_UART_S1_RD(x)         (HW_UART_S1(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0 - No parity error detected since the last time this flag was cleared. If
+ *     the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+//@{
+#define BP_UART_S1_PF        (0U)          //!< Bit position for UART_S1_PF.
+#define BM_UART_S1_PF        (0x01U)       //!< Bit mask for UART_S1_PF.
+#define BS_UART_S1_PF        (1U)          //!< Bit field size in bits for UART_S1_PF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_PF field.
+#define BR_UART_S1_PF(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0 - No framing error detected.
+ * - 1 - Framing error.
+ */
+//@{
+#define BP_UART_S1_FE        (1U)          //!< Bit position for UART_S1_FE.
+#define BM_UART_S1_FE        (0x02U)       //!< Bit mask for UART_S1_FE.
+#define BS_UART_S1_FE        (1U)          //!< Bit field size in bits for UART_S1_FE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_FE field.
+#define BR_UART_S1_FE(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+//@{
+#define BP_UART_S1_NF        (2U)          //!< Bit position for UART_S1_NF.
+#define BM_UART_S1_NF        (0x04U)       //!< Bit mask for UART_S1_NF.
+#define BS_UART_S1_NF        (1U)          //!< Bit field size in bits for UART_S1_NF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_NF field.
+#define BR_UART_S1_NF(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0 - No overrun has occurred since the last time the flag was cleared.
+ * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
+ *     last overrun occured.
+ */
+//@{
+#define BP_UART_S1_OR        (3U)          //!< Bit position for UART_S1_OR.
+#define BM_UART_S1_OR        (0x08U)       //!< Bit mask for UART_S1_OR.
+#define BS_UART_S1_OR        (1U)          //!< Bit field size in bits for UART_S1_OR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_OR field.
+#define BR_UART_S1_OR(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+//@{
+#define BP_UART_S1_IDLE      (4U)          //!< Bit position for UART_S1_IDLE.
+#define BM_UART_S1_IDLE      (0x10U)       //!< Bit mask for UART_S1_IDLE.
+#define BS_UART_S1_IDLE      (1U)          //!< Bit field size in bits for UART_S1_IDLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_IDLE field.
+#define BR_UART_S1_IDLE(x)   (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+//@{
+#define BP_UART_S1_RDRF      (5U)          //!< Bit position for UART_S1_RDRF.
+#define BM_UART_S1_RDRF      (0x20U)       //!< Bit mask for UART_S1_RDRF.
+#define BS_UART_S1_RDRF      (1U)          //!< Bit field size in bits for UART_S1_RDRF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_RDRF field.
+#define BR_UART_S1_RDRF(x)   (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0 - Transmitter active (sending data, a preamble, or a break).
+ * - 1 - Transmitter idle (transmission activity complete).
+ */
+//@{
+#define BP_UART_S1_TC        (6U)          //!< Bit position for UART_S1_TC.
+#define BM_UART_S1_TC        (0x40U)       //!< Bit mask for UART_S1_TC.
+#define BS_UART_S1_TC        (1U)          //!< Bit field size in bits for UART_S1_TC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_TC field.
+#define BR_UART_S1_TC(x)     (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 1 - The amount of data in the transmit buffer is less than or equal to the
+ *     value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+//@{
+#define BP_UART_S1_TDRE      (7U)          //!< Bit position for UART_S1_TDRE.
+#define BM_UART_S1_TDRE      (0x80U)       //!< Bit mask for UART_S1_TDRE.
+#define BS_UART_S1_TDRE      (1U)          //!< Bit field size in bits for UART_S1_TDRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_TDRE field.
+#define BR_UART_S1_TDRE(x)   (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_S2 - UART Status Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+typedef union _hw_uart_s2
+{
+    uint8_t U;
+    struct _hw_uart_s2_bitfields
+    {
+        uint8_t RAF : 1;               //!< [0] Receiver Active Flag
+        uint8_t LBKDE : 1;             //!< [1] LIN Break Detection Enable
+        uint8_t BRK13 : 1;             //!< [2] Break Transmit Character Length
+        uint8_t RWUID : 1;             //!< [3] Receive Wakeup Idle Detect
+        uint8_t RXINV : 1;             //!< [4] Receive Data Inversion
+        uint8_t MSBF : 1;              //!< [5] Most Significant Bit First
+        uint8_t RXEDGIF : 1;           //!< [6] RxD Pin Active Edge Interrupt Flag
+        uint8_t LBKDIF : 1;            //!< [7] LIN Break Detect Interrupt Flag
+    } B;
+} hw_uart_s2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+//@{
+#define HW_UART_S2_ADDR(x)       (REGS_UART_BASE(x) + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_S2(x)            (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x))
+#define HW_UART_S2_RD(x)         (HW_UART_S2(x).U)
+#define HW_UART_S2_WR(x, v)      (HW_UART_S2(x).U = (v))
+#define HW_UART_S2_SET(x, v)     (HW_UART_S2_WR(x, HW_UART_S2_RD(x) |  (v)))
+#define HW_UART_S2_CLR(x, v)     (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
+#define HW_UART_S2_TOG(x, v)     (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0 - UART receiver idle/inactive waiting for a start bit.
+ * - 1 - UART receiver active, RxD input not idle.
+ */
+//@{
+#define BP_UART_S2_RAF       (0U)          //!< Bit position for UART_S2_RAF.
+#define BM_UART_S2_RAF       (0x01U)       //!< Bit mask for UART_S2_RAF.
+#define BS_UART_S2_RAF       (1U)          //!< Bit field size in bits for UART_S2_RAF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RAF field.
+#define BR_UART_S2_RAF(x)    (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0 - Break character detection is disabled.
+ * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+//@{
+#define BP_UART_S2_LBKDE     (1U)          //!< Bit position for UART_S2_LBKDE.
+#define BM_UART_S2_LBKDE     (0x02U)       //!< Bit mask for UART_S2_LBKDE.
+#define BS_UART_S2_LBKDE     (1U)          //!< Bit field size in bits for UART_S2_LBKDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_LBKDE field.
+#define BR_UART_S2_LBKDE(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
+#endif
+
+//! @brief Format value for bitfield UART_S2_LBKDE.
+#define BF_UART_S2_LBKDE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDE), uint8_t) & BM_UART_S2_LBKDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDE field to a new value.
+#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0 - Break character is 10, 11, or 12 bits long.
+ * - 1 - Break character is 13 or 14 bits long.
+ */
+//@{
+#define BP_UART_S2_BRK13     (2U)          //!< Bit position for UART_S2_BRK13.
+#define BM_UART_S2_BRK13     (0x04U)       //!< Bit mask for UART_S2_BRK13.
+#define BS_UART_S2_BRK13     (1U)          //!< Bit field size in bits for UART_S2_BRK13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_BRK13 field.
+#define BR_UART_S2_BRK13(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
+#endif
+
+//! @brief Format value for bitfield UART_S2_BRK13.
+#define BF_UART_S2_BRK13(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_BRK13), uint8_t) & BM_UART_S2_BRK13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRK13 field to a new value.
+#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 1 - S1[IDLE] is set upon detection of an idle character.
+ */
+//@{
+#define BP_UART_S2_RWUID     (3U)          //!< Bit position for UART_S2_RWUID.
+#define BM_UART_S2_RWUID     (0x08U)       //!< Bit mask for UART_S2_RWUID.
+#define BS_UART_S2_RWUID     (1U)          //!< Bit field size in bits for UART_S2_RWUID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RWUID field.
+#define BR_UART_S2_RWUID(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
+#endif
+
+//! @brief Format value for bitfield UART_S2_RWUID.
+#define BF_UART_S2_RWUID(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RWUID), uint8_t) & BM_UART_S2_RWUID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWUID field to a new value.
+#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0 - Receive data is not inverted.
+ * - 1 - Receive data is inverted.
+ */
+//@{
+#define BP_UART_S2_RXINV     (4U)          //!< Bit position for UART_S2_RXINV.
+#define BM_UART_S2_RXINV     (0x10U)       //!< Bit mask for UART_S2_RXINV.
+#define BS_UART_S2_RXINV     (1U)          //!< Bit field size in bits for UART_S2_RXINV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RXINV field.
+#define BR_UART_S2_RXINV(x)  (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
+#endif
+
+//! @brief Format value for bitfield UART_S2_RXINV.
+#define BF_UART_S2_RXINV(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXINV), uint8_t) & BM_UART_S2_RXINV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXINV field to a new value.
+#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
+ *     the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
+ *     first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+//@{
+#define BP_UART_S2_MSBF      (5U)          //!< Bit position for UART_S2_MSBF.
+#define BM_UART_S2_MSBF      (0x20U)       //!< Bit mask for UART_S2_MSBF.
+#define BS_UART_S2_MSBF      (1U)          //!< Bit field size in bits for UART_S2_MSBF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_MSBF field.
+#define BR_UART_S2_MSBF(x)   (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
+#endif
+
+//! @brief Format value for bitfield UART_S2_MSBF.
+#define BF_UART_S2_MSBF(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_MSBF), uint8_t) & BM_UART_S2_MSBF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSBF field to a new value.
+#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0 - No active edge on the receive pin has occurred.
+ * - 1 - An active edge on the receive pin has occurred.
+ */
+//@{
+#define BP_UART_S2_RXEDGIF   (6U)          //!< Bit position for UART_S2_RXEDGIF.
+#define BM_UART_S2_RXEDGIF   (0x40U)       //!< Bit mask for UART_S2_RXEDGIF.
+#define BS_UART_S2_RXEDGIF   (1U)          //!< Bit field size in bits for UART_S2_RXEDGIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RXEDGIF field.
+#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
+#endif
+
+//! @brief Format value for bitfield UART_S2_RXEDGIF.
+#define BF_UART_S2_RXEDGIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXEDGIF), uint8_t) & BM_UART_S2_RXEDGIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXEDGIF field to a new value.
+#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - No LIN break character detected.
+ * - 1 - LIN break character detected.
+ */
+//@{
+#define BP_UART_S2_LBKDIF    (7U)          //!< Bit position for UART_S2_LBKDIF.
+#define BM_UART_S2_LBKDIF    (0x80U)       //!< Bit mask for UART_S2_LBKDIF.
+#define BS_UART_S2_LBKDIF    (1U)          //!< Bit field size in bits for UART_S2_LBKDIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_LBKDIF field.
+#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
+#endif
+
+//! @brief Format value for bitfield UART_S2_LBKDIF.
+#define BF_UART_S2_LBKDIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDIF), uint8_t) & BM_UART_S2_LBKDIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDIF field to a new value.
+#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C3 - UART Control Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+typedef union _hw_uart_c3
+{
+    uint8_t U;
+    struct _hw_uart_c3_bitfields
+    {
+        uint8_t PEIE : 1;              //!< [0] Parity Error Interrupt Enable
+        uint8_t FEIE : 1;              //!< [1] Framing Error Interrupt Enable
+        uint8_t NEIE : 1;              //!< [2] Noise Error Interrupt Enable
+        uint8_t ORIE : 1;              //!< [3] Overrun Error Interrupt Enable
+        uint8_t TXINV : 1;             //!< [4] Transmit Data Inversion.
+        uint8_t TXDIR : 1;             //!< [5] Transmitter Pin Data Direction in
+                                       //! Single-Wire mode
+        uint8_t T8 : 1;                //!< [6] Transmit Bit 8
+        uint8_t R8 : 1;                //!< [7] Received Bit 8
+    } B;
+} hw_uart_c3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+//@{
+#define HW_UART_C3_ADDR(x)       (REGS_UART_BASE(x) + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C3(x)            (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x))
+#define HW_UART_C3_RD(x)         (HW_UART_C3(x).U)
+#define HW_UART_C3_WR(x, v)      (HW_UART_C3(x).U = (v))
+#define HW_UART_C3_SET(x, v)     (HW_UART_C3_WR(x, HW_UART_C3_RD(x) |  (v)))
+#define HW_UART_C3_CLR(x, v)     (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
+#define HW_UART_C3_TOG(x, v)     (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - PF interrupt requests are disabled.
+ * - 1 - PF interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_PEIE      (0U)          //!< Bit position for UART_C3_PEIE.
+#define BM_UART_C3_PEIE      (0x01U)       //!< Bit mask for UART_C3_PEIE.
+#define BS_UART_C3_PEIE      (1U)          //!< Bit field size in bits for UART_C3_PEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_PEIE field.
+#define BR_UART_C3_PEIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_PEIE.
+#define BF_UART_C3_PEIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_PEIE), uint8_t) & BM_UART_C3_PEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PEIE field to a new value.
+#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - FE interrupt requests are disabled.
+ * - 1 - FE interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_FEIE      (1U)          //!< Bit position for UART_C3_FEIE.
+#define BM_UART_C3_FEIE      (0x02U)       //!< Bit mask for UART_C3_FEIE.
+#define BS_UART_C3_FEIE      (1U)          //!< Bit field size in bits for UART_C3_FEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_FEIE field.
+#define BR_UART_C3_FEIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_FEIE.
+#define BF_UART_C3_FEIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_FEIE), uint8_t) & BM_UART_C3_FEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEIE field to a new value.
+#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - NF interrupt requests are disabled.
+ * - 1 - NF interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_NEIE      (2U)          //!< Bit position for UART_C3_NEIE.
+#define BM_UART_C3_NEIE      (0x04U)       //!< Bit mask for UART_C3_NEIE.
+#define BS_UART_C3_NEIE      (1U)          //!< Bit field size in bits for UART_C3_NEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_NEIE field.
+#define BR_UART_C3_NEIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_NEIE.
+#define BF_UART_C3_NEIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_NEIE), uint8_t) & BM_UART_C3_NEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NEIE field to a new value.
+#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - OR interrupts are disabled.
+ * - 1 - OR interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_ORIE      (3U)          //!< Bit position for UART_C3_ORIE.
+#define BM_UART_C3_ORIE      (0x08U)       //!< Bit mask for UART_C3_ORIE.
+#define BS_UART_C3_ORIE      (1U)          //!< Bit field size in bits for UART_C3_ORIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_ORIE field.
+#define BR_UART_C3_ORIE(x)   (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_ORIE.
+#define BF_UART_C3_ORIE(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_ORIE), uint8_t) & BM_UART_C3_ORIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ORIE field to a new value.
+#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0 - Transmit data is not inverted.
+ * - 1 - Transmit data is inverted.
+ */
+//@{
+#define BP_UART_C3_TXINV     (4U)          //!< Bit position for UART_C3_TXINV.
+#define BM_UART_C3_TXINV     (0x10U)       //!< Bit mask for UART_C3_TXINV.
+#define BS_UART_C3_TXINV     (1U)          //!< Bit field size in bits for UART_C3_TXINV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_TXINV field.
+#define BR_UART_C3_TXINV(x)  (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
+#endif
+
+//! @brief Format value for bitfield UART_C3_TXINV.
+#define BF_UART_C3_TXINV(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXINV), uint8_t) & BM_UART_C3_TXINV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXINV field to a new value.
+#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0 - TXD pin is an input in single wire mode.
+ * - 1 - TXD pin is an output in single wire mode.
+ */
+//@{
+#define BP_UART_C3_TXDIR     (5U)          //!< Bit position for UART_C3_TXDIR.
+#define BM_UART_C3_TXDIR     (0x20U)       //!< Bit mask for UART_C3_TXDIR.
+#define BS_UART_C3_TXDIR     (1U)          //!< Bit field size in bits for UART_C3_TXDIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_TXDIR field.
+#define BR_UART_C3_TXDIR(x)  (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
+#endif
+
+//! @brief Format value for bitfield UART_C3_TXDIR.
+#define BF_UART_C3_TXDIR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXDIR), uint8_t) & BM_UART_C3_TXDIR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXDIR field to a new value.
+#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+//@{
+#define BP_UART_C3_T8        (6U)          //!< Bit position for UART_C3_T8.
+#define BM_UART_C3_T8        (0x40U)       //!< Bit mask for UART_C3_T8.
+#define BS_UART_C3_T8        (1U)          //!< Bit field size in bits for UART_C3_T8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_T8 field.
+#define BR_UART_C3_T8(x)     (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
+#endif
+
+//! @brief Format value for bitfield UART_C3_T8.
+#define BF_UART_C3_T8(v)     (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_T8), uint8_t) & BM_UART_C3_T8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the T8 field to a new value.
+#define BW_UART_C3_T8(x, v)  (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+//@{
+#define BP_UART_C3_R8        (7U)          //!< Bit position for UART_C3_R8.
+#define BM_UART_C3_R8        (0x80U)       //!< Bit mask for UART_C3_R8.
+#define BS_UART_C3_R8        (1U)          //!< Bit field size in bits for UART_C3_R8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_R8 field.
+#define BR_UART_C3_R8(x)     (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_D - UART Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+typedef union _hw_uart_d
+{
+    uint8_t U;
+    struct _hw_uart_d_bitfields
+    {
+        uint8_t RT : 8;                //!< [7:0]
+    } B;
+} hw_uart_d_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+//@{
+#define HW_UART_D_ADDR(x)        (REGS_UART_BASE(x) + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_D(x)             (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x))
+#define HW_UART_D_RD(x)          (HW_UART_D(x).U)
+#define HW_UART_D_WR(x, v)       (HW_UART_D(x).U = (v))
+#define HW_UART_D_SET(x, v)      (HW_UART_D_WR(x, HW_UART_D_RD(x) |  (v)))
+#define HW_UART_D_CLR(x, v)      (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
+#define HW_UART_D_TOG(x, v)      (HW_UART_D_WR(x, HW_UART_D_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_D bitfields
+ */
+
+/*!
+ * @name Register UART_D, field RT[7:0] (RW)
+ *
+ * Reads return the contents of the read-only receive data register and writes
+ * go to the write-only transmit data register.
+ */
+//@{
+#define BP_UART_D_RT         (0U)          //!< Bit position for UART_D_RT.
+#define BM_UART_D_RT         (0xFFU)       //!< Bit mask for UART_D_RT.
+#define BS_UART_D_RT         (8U)          //!< Bit field size in bits for UART_D_RT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_D_RT field.
+#define BR_UART_D_RT(x)      (HW_UART_D(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_D_RT.
+#define BF_UART_D_RT(v)      (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_D_RT), uint8_t) & BM_UART_D_RT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RT field to a new value.
+#define BW_UART_D_RT(x, v)   (HW_UART_D_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_MA1 - UART Match Address Registers 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+typedef union _hw_uart_ma1
+{
+    uint8_t U;
+    struct _hw_uart_ma1_bitfields
+    {
+        uint8_t MA : 8;                //!< [7:0] Match Address
+    } B;
+} hw_uart_ma1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+//@{
+#define HW_UART_MA1_ADDR(x)      (REGS_UART_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_MA1(x)           (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x))
+#define HW_UART_MA1_RD(x)        (HW_UART_MA1(x).U)
+#define HW_UART_MA1_WR(x, v)     (HW_UART_MA1(x).U = (v))
+#define HW_UART_MA1_SET(x, v)    (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) |  (v)))
+#define HW_UART_MA1_CLR(x, v)    (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
+#define HW_UART_MA1_TOG(x, v)    (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_MA1 bitfields
+ */
+
+/*!
+ * @name Register UART_MA1, field MA[7:0] (RW)
+ */
+//@{
+#define BP_UART_MA1_MA       (0U)          //!< Bit position for UART_MA1_MA.
+#define BM_UART_MA1_MA       (0xFFU)       //!< Bit mask for UART_MA1_MA.
+#define BS_UART_MA1_MA       (8U)          //!< Bit field size in bits for UART_MA1_MA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MA1_MA field.
+#define BR_UART_MA1_MA(x)    (HW_UART_MA1(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_MA1_MA.
+#define BF_UART_MA1_MA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA1_MA), uint8_t) & BM_UART_MA1_MA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MA field to a new value.
+#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_MA2 - UART Match Address Registers 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+typedef union _hw_uart_ma2
+{
+    uint8_t U;
+    struct _hw_uart_ma2_bitfields
+    {
+        uint8_t MA : 8;                //!< [7:0] Match Address
+    } B;
+} hw_uart_ma2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+//@{
+#define HW_UART_MA2_ADDR(x)      (REGS_UART_BASE(x) + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_MA2(x)           (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x))
+#define HW_UART_MA2_RD(x)        (HW_UART_MA2(x).U)
+#define HW_UART_MA2_WR(x, v)     (HW_UART_MA2(x).U = (v))
+#define HW_UART_MA2_SET(x, v)    (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) |  (v)))
+#define HW_UART_MA2_CLR(x, v)    (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
+#define HW_UART_MA2_TOG(x, v)    (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_MA2 bitfields
+ */
+
+/*!
+ * @name Register UART_MA2, field MA[7:0] (RW)
+ */
+//@{
+#define BP_UART_MA2_MA       (0U)          //!< Bit position for UART_MA2_MA.
+#define BM_UART_MA2_MA       (0xFFU)       //!< Bit mask for UART_MA2_MA.
+#define BS_UART_MA2_MA       (8U)          //!< Bit field size in bits for UART_MA2_MA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MA2_MA field.
+#define BR_UART_MA2_MA(x)    (HW_UART_MA2(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_MA2_MA.
+#define BF_UART_MA2_MA(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA2_MA), uint8_t) & BM_UART_MA2_MA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MA field to a new value.
+#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C4 - UART Control Register 4
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_uart_c4
+{
+    uint8_t U;
+    struct _hw_uart_c4_bitfields
+    {
+        uint8_t BRFA : 5;              //!< [4:0] Baud Rate Fine Adjust
+        uint8_t M10 : 1;               //!< [5] 10-bit Mode select
+        uint8_t MAEN2 : 1;             //!< [6] Match Address Mode Enable 2
+        uint8_t MAEN1 : 1;             //!< [7] Match Address Mode Enable 1
+    } B;
+} hw_uart_c4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+//@{
+#define HW_UART_C4_ADDR(x)       (REGS_UART_BASE(x) + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C4(x)            (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x))
+#define HW_UART_C4_RD(x)         (HW_UART_C4(x).U)
+#define HW_UART_C4_WR(x, v)      (HW_UART_C4(x).U = (v))
+#define HW_UART_C4_SET(x, v)     (HW_UART_C4_WR(x, HW_UART_C4_RD(x) |  (v)))
+#define HW_UART_C4_CLR(x, v)     (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
+#define HW_UART_C4_TOG(x, v)     (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+//@{
+#define BP_UART_C4_BRFA      (0U)          //!< Bit position for UART_C4_BRFA.
+#define BM_UART_C4_BRFA      (0x1FU)       //!< Bit mask for UART_C4_BRFA.
+#define BS_UART_C4_BRFA      (5U)          //!< Bit field size in bits for UART_C4_BRFA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_BRFA field.
+#define BR_UART_C4_BRFA(x)   (HW_UART_C4(x).B.BRFA)
+#endif
+
+//! @brief Format value for bitfield UART_C4_BRFA.
+#define BF_UART_C4_BRFA(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_BRFA), uint8_t) & BM_UART_C4_BRFA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRFA field to a new value.
+#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0 - The parity bit is the ninth bit in the serial transmission.
+ * - 1 - The parity bit is the tenth bit in the serial transmission.
+ */
+//@{
+#define BP_UART_C4_M10       (5U)          //!< Bit position for UART_C4_M10.
+#define BM_UART_C4_M10       (0x20U)       //!< Bit mask for UART_C4_M10.
+#define BS_UART_C4_M10       (1U)          //!< Bit field size in bits for UART_C4_M10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_M10 field.
+#define BR_UART_C4_M10(x)    (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
+#endif
+
+//! @brief Format value for bitfield UART_C4_M10.
+#define BF_UART_C4_M10(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_M10), uint8_t) & BM_UART_C4_M10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M10 field to a new value.
+#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
+ * - 1 - All data received with the most significant bit cleared, is discarded.
+ *     All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+//@{
+#define BP_UART_C4_MAEN2     (6U)          //!< Bit position for UART_C4_MAEN2.
+#define BM_UART_C4_MAEN2     (0x40U)       //!< Bit mask for UART_C4_MAEN2.
+#define BS_UART_C4_MAEN2     (1U)          //!< Bit field size in bits for UART_C4_MAEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_MAEN2 field.
+#define BR_UART_C4_MAEN2(x)  (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
+#endif
+
+//! @brief Format value for bitfield UART_C4_MAEN2.
+#define BF_UART_C4_MAEN2(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN2), uint8_t) & BM_UART_C4_MAEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAEN2 field to a new value.
+#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
+ * - 1 - All data received with the most significant bit cleared, is discarded.
+ *     All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If match
+ *     occurs, data is transferred to the data buffer. This field must be cleared
+ *     when C7816[ISO7816E] is set/enabled.
+ */
+//@{
+#define BP_UART_C4_MAEN1     (7U)          //!< Bit position for UART_C4_MAEN1.
+#define BM_UART_C4_MAEN1     (0x80U)       //!< Bit mask for UART_C4_MAEN1.
+#define BS_UART_C4_MAEN1     (1U)          //!< Bit field size in bits for UART_C4_MAEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_MAEN1 field.
+#define BR_UART_C4_MAEN1(x)  (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
+#endif
+
+//! @brief Format value for bitfield UART_C4_MAEN1.
+#define BF_UART_C4_MAEN1(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN1), uint8_t) & BM_UART_C4_MAEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAEN1 field to a new value.
+#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C5 - UART Control Register 5
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_uart_c5
+{
+    uint8_t U;
+    struct _hw_uart_c5_bitfields
+    {
+        uint8_t RESERVED0 : 3;         //!< [2:0]
+        uint8_t LBKDDMAS : 1;          //!< [3] LIN Break Detect DMA Select Bit
+        uint8_t ILDMAS : 1;            //!< [4] Idle Line DMA Select
+        uint8_t RDMAS : 1;             //!< [5] Receiver Full DMA Select
+        uint8_t TCDMAS : 1;            //!< [6] Transmission Complete DMA Select
+        uint8_t TDMAS : 1;             //!< [7] Transmitter DMA Select
+    } B;
+} hw_uart_c5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+//@{
+#define HW_UART_C5_ADDR(x)       (REGS_UART_BASE(x) + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C5(x)            (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x))
+#define HW_UART_C5_RD(x)         (HW_UART_C5(x).U)
+#define HW_UART_C5_WR(x, v)      (HW_UART_C5(x).U = (v))
+#define HW_UART_C5_SET(x, v)     (HW_UART_C5_WR(x, HW_UART_C5_RD(x) |  (v)))
+#define HW_UART_C5_CLR(x, v)     (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
+#define HW_UART_C5_TOG(x, v)     (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_LBKDDMAS  (3U)          //!< Bit position for UART_C5_LBKDDMAS.
+#define BM_UART_C5_LBKDDMAS  (0x08U)       //!< Bit mask for UART_C5_LBKDDMAS.
+#define BS_UART_C5_LBKDDMAS  (1U)          //!< Bit field size in bits for UART_C5_LBKDDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_LBKDDMAS field.
+#define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_LBKDDMAS.
+#define BF_UART_C5_LBKDDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_LBKDDMAS), uint8_t) & BM_UART_C5_LBKDDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDDMAS field to a new value.
+#define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_ILDMAS    (4U)          //!< Bit position for UART_C5_ILDMAS.
+#define BM_UART_C5_ILDMAS    (0x10U)       //!< Bit mask for UART_C5_ILDMAS.
+#define BS_UART_C5_ILDMAS    (1U)          //!< Bit field size in bits for UART_C5_ILDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_ILDMAS field.
+#define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_ILDMAS.
+#define BF_UART_C5_ILDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_ILDMAS), uint8_t) & BM_UART_C5_ILDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ILDMAS field to a new value.
+#define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_RDMAS     (5U)          //!< Bit position for UART_C5_RDMAS.
+#define BM_UART_C5_RDMAS     (0x20U)       //!< Bit mask for UART_C5_RDMAS.
+#define BS_UART_C5_RDMAS     (1U)          //!< Bit field size in bits for UART_C5_RDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_RDMAS field.
+#define BR_UART_C5_RDMAS(x)  (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_RDMAS.
+#define BF_UART_C5_RDMAS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_RDMAS), uint8_t) & BM_UART_C5_RDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDMAS field to a new value.
+#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
+ *     signal is asserted to request an interrupt service.
+ * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_TCDMAS    (6U)          //!< Bit position for UART_C5_TCDMAS.
+#define BM_UART_C5_TCDMAS    (0x40U)       //!< Bit mask for UART_C5_TCDMAS.
+#define BS_UART_C5_TCDMAS    (1U)          //!< Bit field size in bits for UART_C5_TCDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_TCDMAS field.
+#define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_TCDMAS.
+#define BF_UART_C5_TCDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TCDMAS), uint8_t) & BM_UART_C5_TCDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCDMAS field to a new value.
+#define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_TDMAS     (7U)          //!< Bit position for UART_C5_TDMAS.
+#define BM_UART_C5_TDMAS     (0x80U)       //!< Bit mask for UART_C5_TDMAS.
+#define BS_UART_C5_TDMAS     (1U)          //!< Bit field size in bits for UART_C5_TDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_TDMAS field.
+#define BR_UART_C5_TDMAS(x)  (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_TDMAS.
+#define BF_UART_C5_TDMAS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TDMAS), uint8_t) & BM_UART_C5_TDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDMAS field to a new value.
+#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_ED - UART Extended Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+typedef union _hw_uart_ed
+{
+    uint8_t U;
+    struct _hw_uart_ed_bitfields
+    {
+        uint8_t RESERVED0 : 6;         //!< [5:0]
+        uint8_t PARITYE : 1;           //!< [6]
+        uint8_t NOISY : 1;             //!< [7]
+    } B;
+} hw_uart_ed_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+//@{
+#define HW_UART_ED_ADDR(x)       (REGS_UART_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_ED(x)            (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x))
+#define HW_UART_ED_RD(x)         (HW_UART_ED(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0 - The dataword was received without a parity error.
+ * - 1 - The dataword was received with a parity error.
+ */
+//@{
+#define BP_UART_ED_PARITYE   (6U)          //!< Bit position for UART_ED_PARITYE.
+#define BM_UART_ED_PARITYE   (0x40U)       //!< Bit mask for UART_ED_PARITYE.
+#define BS_UART_ED_PARITYE   (1U)          //!< Bit field size in bits for UART_ED_PARITYE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ED_PARITYE field.
+#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
+#endif
+//@}
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0 - The dataword was received without noise.
+ * - 1 - The data was received with noise.
+ */
+//@{
+#define BP_UART_ED_NOISY     (7U)          //!< Bit position for UART_ED_NOISY.
+#define BM_UART_ED_NOISY     (0x80U)       //!< Bit mask for UART_ED_NOISY.
+#define BS_UART_ED_NOISY     (1U)          //!< Bit field size in bits for UART_ED_NOISY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ED_NOISY field.
+#define BR_UART_ED_NOISY(x)  (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_MODEM - UART Modem Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+typedef union _hw_uart_modem
+{
+    uint8_t U;
+    struct _hw_uart_modem_bitfields
+    {
+        uint8_t TXCTSE : 1;            //!< [0] Transmitter clear-to-send enable
+        uint8_t TXRTSE : 1;            //!< [1] Transmitter request-to-send enable
+        uint8_t TXRTSPOL : 1;          //!< [2] Transmitter request-to-send polarity
+        uint8_t RXRTSE : 1;            //!< [3] Receiver request-to-send enable
+        uint8_t RESERVED0 : 4;         //!< [7:4]
+    } B;
+} hw_uart_modem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+//@{
+#define HW_UART_MODEM_ADDR(x)    (REGS_UART_BASE(x) + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_MODEM(x)         (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x))
+#define HW_UART_MODEM_RD(x)      (HW_UART_MODEM(x).U)
+#define HW_UART_MODEM_WR(x, v)   (HW_UART_MODEM(x).U = (v))
+#define HW_UART_MODEM_SET(x, v)  (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) |  (v)))
+#define HW_UART_MODEM_CLR(x, v)  (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
+#define HW_UART_MODEM_TOG(x, v)  (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0 - CTS has no effect on the transmitter.
+ * - 1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as a
+ *     character is being sent do not affect its transmission.
+ */
+//@{
+#define BP_UART_MODEM_TXCTSE (0U)          //!< Bit position for UART_MODEM_TXCTSE.
+#define BM_UART_MODEM_TXCTSE (0x01U)       //!< Bit mask for UART_MODEM_TXCTSE.
+#define BS_UART_MODEM_TXCTSE (1U)          //!< Bit field size in bits for UART_MODEM_TXCTSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_TXCTSE field.
+#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_TXCTSE.
+#define BF_UART_MODEM_TXCTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXCTSE), uint8_t) & BM_UART_MODEM_TXCTSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXCTSE field to a new value.
+#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0 - The transmitter has no effect on RTS.
+ * - 1 - When a character is placed into an empty transmitter data buffer , RTS
+ *     asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+//@{
+#define BP_UART_MODEM_TXRTSE (1U)          //!< Bit position for UART_MODEM_TXRTSE.
+#define BM_UART_MODEM_TXRTSE (0x02U)       //!< Bit mask for UART_MODEM_TXRTSE.
+#define BS_UART_MODEM_TXRTSE (1U)          //!< Bit field size in bits for UART_MODEM_TXRTSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_TXRTSE field.
+#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_TXRTSE.
+#define BF_UART_MODEM_TXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSE), uint8_t) & BM_UART_MODEM_TXRTSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXRTSE field to a new value.
+#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0 - Transmitter RTS is active low.
+ * - 1 - Transmitter RTS is active high.
+ */
+//@{
+#define BP_UART_MODEM_TXRTSPOL (2U)        //!< Bit position for UART_MODEM_TXRTSPOL.
+#define BM_UART_MODEM_TXRTSPOL (0x04U)     //!< Bit mask for UART_MODEM_TXRTSPOL.
+#define BS_UART_MODEM_TXRTSPOL (1U)        //!< Bit field size in bits for UART_MODEM_TXRTSPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_TXRTSPOL field.
+#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_TXRTSPOL.
+#define BF_UART_MODEM_TXRTSPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSPOL), uint8_t) & BM_UART_MODEM_TXRTSPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXRTSPOL field to a new value.
+#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0 - The receiver has no effect on RTS.
+ * - 1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is less
+ *     than RWFIFO[RXWATER].
+ */
+//@{
+#define BP_UART_MODEM_RXRTSE (3U)          //!< Bit position for UART_MODEM_RXRTSE.
+#define BM_UART_MODEM_RXRTSE (0x08U)       //!< Bit mask for UART_MODEM_RXRTSE.
+#define BS_UART_MODEM_RXRTSE (1U)          //!< Bit field size in bits for UART_MODEM_RXRTSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_RXRTSE field.
+#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_RXRTSE.
+#define BF_UART_MODEM_RXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_RXRTSE), uint8_t) & BM_UART_MODEM_RXRTSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXRTSE field to a new value.
+#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_IR - UART Infrared Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+typedef union _hw_uart_ir
+{
+    uint8_t U;
+    struct _hw_uart_ir_bitfields
+    {
+        uint8_t TNP : 2;               //!< [1:0] Transmitter narrow pulse
+        uint8_t IREN : 1;              //!< [2] Infrared enable
+        uint8_t RESERVED0 : 5;         //!< [7:3]
+    } B;
+} hw_uart_ir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+//@{
+#define HW_UART_IR_ADDR(x)       (REGS_UART_BASE(x) + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_IR(x)            (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x))
+#define HW_UART_IR_RD(x)         (HW_UART_IR(x).U)
+#define HW_UART_IR_WR(x, v)      (HW_UART_IR(x).U = (v))
+#define HW_UART_IR_SET(x, v)     (HW_UART_IR_WR(x, HW_UART_IR_RD(x) |  (v)))
+#define HW_UART_IR_CLR(x, v)     (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
+#define HW_UART_IR_TOG(x, v)     (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 00 - 3/16.
+ * - 01 - 1/16.
+ * - 10 - 1/32.
+ * - 11 - 1/4.
+ */
+//@{
+#define BP_UART_IR_TNP       (0U)          //!< Bit position for UART_IR_TNP.
+#define BM_UART_IR_TNP       (0x03U)       //!< Bit mask for UART_IR_TNP.
+#define BS_UART_IR_TNP       (2U)          //!< Bit field size in bits for UART_IR_TNP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IR_TNP field.
+#define BR_UART_IR_TNP(x)    (HW_UART_IR(x).B.TNP)
+#endif
+
+//! @brief Format value for bitfield UART_IR_TNP.
+#define BF_UART_IR_TNP(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_TNP), uint8_t) & BM_UART_IR_TNP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TNP field to a new value.
+#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0 - IR disabled.
+ * - 1 - IR enabled.
+ */
+//@{
+#define BP_UART_IR_IREN      (2U)          //!< Bit position for UART_IR_IREN.
+#define BM_UART_IR_IREN      (0x04U)       //!< Bit mask for UART_IR_IREN.
+#define BS_UART_IR_IREN      (1U)          //!< Bit field size in bits for UART_IR_IREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IR_IREN field.
+#define BR_UART_IR_IREN(x)   (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
+#endif
+
+//! @brief Format value for bitfield UART_IR_IREN.
+#define BF_UART_IR_IREN(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_IREN), uint8_t) & BM_UART_IR_IREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IREN field to a new value.
+#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_PFIFO - UART FIFO Parameters
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+typedef union _hw_uart_pfifo
+{
+    uint8_t U;
+    struct _hw_uart_pfifo_bitfields
+    {
+        uint8_t RXFIFOSIZE : 3;        //!< [2:0] Receive FIFO. Buffer Depth
+        uint8_t RXFE : 1;              //!< [3] Receive FIFO Enable
+        uint8_t TXFIFOSIZE : 3;        //!< [6:4] Transmit FIFO. Buffer Depth
+        uint8_t TXFE : 1;              //!< [7] Transmit FIFO Enable
+    } B;
+} hw_uart_pfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+//@{
+#define HW_UART_PFIFO_ADDR(x)    (REGS_UART_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_PFIFO(x)         (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x))
+#define HW_UART_PFIFO_RD(x)      (HW_UART_PFIFO(x).U)
+#define HW_UART_PFIFO_WR(x, v)   (HW_UART_PFIFO(x).U = (v))
+#define HW_UART_PFIFO_SET(x, v)  (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) |  (v)))
+#define HW_UART_PFIFO_CLR(x, v)  (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
+#define HW_UART_PFIFO_TOG(x, v)  (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 111 - Reserved.
+ */
+//@{
+#define BP_UART_PFIFO_RXFIFOSIZE (0U)      //!< Bit position for UART_PFIFO_RXFIFOSIZE.
+#define BM_UART_PFIFO_RXFIFOSIZE (0x07U)   //!< Bit mask for UART_PFIFO_RXFIFOSIZE.
+#define BS_UART_PFIFO_RXFIFOSIZE (3U)      //!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field.
+#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+//@{
+#define BP_UART_PFIFO_RXFE   (3U)          //!< Bit position for UART_PFIFO_RXFE.
+#define BM_UART_PFIFO_RXFE   (0x08U)       //!< Bit mask for UART_PFIFO_RXFE.
+#define BS_UART_PFIFO_RXFE   (1U)          //!< Bit field size in bits for UART_PFIFO_RXFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_RXFE field.
+#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
+#endif
+
+//! @brief Format value for bitfield UART_PFIFO_RXFE.
+#define BF_UART_PFIFO_RXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_RXFE), uint8_t) & BM_UART_PFIFO_RXFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXFE field to a new value.
+#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 111 - Reserved.
+ */
+//@{
+#define BP_UART_PFIFO_TXFIFOSIZE (4U)      //!< Bit position for UART_PFIFO_TXFIFOSIZE.
+#define BM_UART_PFIFO_TXFIFOSIZE (0x70U)   //!< Bit mask for UART_PFIFO_TXFIFOSIZE.
+#define BS_UART_PFIFO_TXFIFOSIZE (3U)      //!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field.
+#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+//@{
+#define BP_UART_PFIFO_TXFE   (7U)          //!< Bit position for UART_PFIFO_TXFE.
+#define BM_UART_PFIFO_TXFE   (0x80U)       //!< Bit mask for UART_PFIFO_TXFE.
+#define BS_UART_PFIFO_TXFE   (1U)          //!< Bit field size in bits for UART_PFIFO_TXFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_TXFE field.
+#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
+#endif
+
+//! @brief Format value for bitfield UART_PFIFO_TXFE.
+#define BF_UART_PFIFO_TXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_TXFE), uint8_t) & BM_UART_PFIFO_TXFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXFE field to a new value.
+#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_CFIFO - UART FIFO Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+typedef union _hw_uart_cfifo
+{
+    uint8_t U;
+    struct _hw_uart_cfifo_bitfields
+    {
+        uint8_t RXUFE : 1;             //!< [0] Receive FIFO Underflow Interrupt Enable
+        uint8_t TXOFE : 1;             //!< [1] Transmit FIFO Overflow Interrupt Enable
+        uint8_t RXOFE : 1;             //!< [2] Receive FIFO Overflow Interrupt Enable
+        uint8_t RESERVED0 : 3;         //!< [5:3]
+        uint8_t RXFLUSH : 1;           //!< [6] Receive FIFO/Buffer Flush
+        uint8_t TXFLUSH : 1;           //!< [7] Transmit FIFO/Buffer Flush
+    } B;
+} hw_uart_cfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+//@{
+#define HW_UART_CFIFO_ADDR(x)    (REGS_UART_BASE(x) + 0x11U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_CFIFO(x)         (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x))
+#define HW_UART_CFIFO_RD(x)      (HW_UART_CFIFO(x).U)
+#define HW_UART_CFIFO_WR(x, v)   (HW_UART_CFIFO(x).U = (v))
+#define HW_UART_CFIFO_SET(x, v)  (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) |  (v)))
+#define HW_UART_CFIFO_CLR(x, v)  (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
+#define HW_UART_CFIFO_TOG(x, v)  (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0 - RXUF flag does not generate an interrupt to the host.
+ * - 1 - RXUF flag generates an interrupt to the host.
+ */
+//@{
+#define BP_UART_CFIFO_RXUFE  (0U)          //!< Bit position for UART_CFIFO_RXUFE.
+#define BM_UART_CFIFO_RXUFE  (0x01U)       //!< Bit mask for UART_CFIFO_RXUFE.
+#define BS_UART_CFIFO_RXUFE  (1U)          //!< Bit field size in bits for UART_CFIFO_RXUFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_CFIFO_RXUFE field.
+#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
+#endif
+
+//! @brief Format value for bitfield UART_CFIFO_RXUFE.
+#define BF_UART_CFIFO_RXUFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXUFE), uint8_t) & BM_UART_CFIFO_RXUFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXUFE field to a new value.
+#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0 - TXOF flag does not generate an interrupt to the host.
+ * - 1 - TXOF flag generates an interrupt to the host.
+ */
+//@{
+#define BP_UART_CFIFO_TXOFE  (1U)          //!< Bit position for UART_CFIFO_TXOFE.
+#define BM_UART_CFIFO_TXOFE  (0x02U)       //!< Bit mask for UART_CFIFO_TXOFE.
+#define BS_UART_CFIFO_TXOFE  (1U)          //!< Bit field size in bits for UART_CFIFO_TXOFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_CFIFO_TXOFE field.
+#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
+#endif
+
+//! @brief Format value for bitfield UART_CFIFO_TXOFE.
+#define BF_UART_CFIFO_TXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXOFE), uint8_t) & BM_UART_CFIFO_TXOFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXOFE field to a new value.
+#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0 - RXOF flag does not generate an interrupt to the host.
+ * - 1 - RXOF flag generates an interrupt to the host.
+ */
+//@{
+#define BP_UART_CFIFO_RXOFE  (2U)          //!< Bit position for UART_CFIFO_RXOFE.
+#define BM_UART_CFIFO_RXOFE  (0x04U)       //!< Bit mask for UART_CFIFO_RXOFE.
+#define BS_UART_CFIFO_RXOFE  (1U)          //!< Bit field size in bits for UART_CFIFO_RXOFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_CFIFO_RXOFE field.
+#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
+#endif
+
+//! @brief Format value for bitfield UART_CFIFO_RXOFE.
+#define BF_UART_CFIFO_RXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXOFE), uint8_t) & BM_UART_CFIFO_RXOFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXOFE field to a new value.
+#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0 - No flush operation occurs.
+ * - 1 - All data in the receive FIFO/buffer is cleared out.
+ */
+//@{
+#define BP_UART_CFIFO_RXFLUSH (6U)         //!< Bit position for UART_CFIFO_RXFLUSH.
+#define BM_UART_CFIFO_RXFLUSH (0x40U)      //!< Bit mask for UART_CFIFO_RXFLUSH.
+#define BS_UART_CFIFO_RXFLUSH (1U)         //!< Bit field size in bits for UART_CFIFO_RXFLUSH.
+
+//! @brief Format value for bitfield UART_CFIFO_RXFLUSH.
+#define BF_UART_CFIFO_RXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXFLUSH), uint8_t) & BM_UART_CFIFO_RXFLUSH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXFLUSH field to a new value.
+#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0 - No flush operation occurs.
+ * - 1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+//@{
+#define BP_UART_CFIFO_TXFLUSH (7U)         //!< Bit position for UART_CFIFO_TXFLUSH.
+#define BM_UART_CFIFO_TXFLUSH (0x80U)      //!< Bit mask for UART_CFIFO_TXFLUSH.
+#define BS_UART_CFIFO_TXFLUSH (1U)         //!< Bit field size in bits for UART_CFIFO_TXFLUSH.
+
+//! @brief Format value for bitfield UART_CFIFO_TXFLUSH.
+#define BF_UART_CFIFO_TXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXFLUSH), uint8_t) & BM_UART_CFIFO_TXFLUSH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXFLUSH field to a new value.
+#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_SFIFO - UART FIFO Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+typedef union _hw_uart_sfifo
+{
+    uint8_t U;
+    struct _hw_uart_sfifo_bitfields
+    {
+        uint8_t RXUF : 1;              //!< [0] Receiver Buffer Underflow Flag
+        uint8_t TXOF : 1;              //!< [1] Transmitter Buffer Overflow Flag
+        uint8_t RXOF : 1;              //!< [2] Receiver Buffer Overflow Flag
+        uint8_t RESERVED0 : 3;         //!< [5:3]
+        uint8_t RXEMPT : 1;            //!< [6] Receive Buffer/FIFO Empty
+        uint8_t TXEMPT : 1;            //!< [7] Transmit Buffer/FIFO Empty
+    } B;
+} hw_uart_sfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+//@{
+#define HW_UART_SFIFO_ADDR(x)    (REGS_UART_BASE(x) + 0x12U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_SFIFO(x)         (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x))
+#define HW_UART_SFIFO_RD(x)      (HW_UART_SFIFO(x).U)
+#define HW_UART_SFIFO_WR(x, v)   (HW_UART_SFIFO(x).U = (v))
+#define HW_UART_SFIFO_SET(x, v)  (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) |  (v)))
+#define HW_UART_SFIFO_CLR(x, v)  (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
+#define HW_UART_SFIFO_TOG(x, v)  (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 1 - At least one receive buffer underflow has occurred since the last time
+ *     the flag was cleared.
+ */
+//@{
+#define BP_UART_SFIFO_RXUF   (0U)          //!< Bit position for UART_SFIFO_RXUF.
+#define BM_UART_SFIFO_RXUF   (0x01U)       //!< Bit mask for UART_SFIFO_RXUF.
+#define BS_UART_SFIFO_RXUF   (1U)          //!< Bit field size in bits for UART_SFIFO_RXUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_RXUF field.
+#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
+#endif
+
+//! @brief Format value for bitfield UART_SFIFO_RXUF.
+#define BF_UART_SFIFO_RXUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXUF), uint8_t) & BM_UART_SFIFO_RXUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXUF field to a new value.
+#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 1 - At least one transmit buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+//@{
+#define BP_UART_SFIFO_TXOF   (1U)          //!< Bit position for UART_SFIFO_TXOF.
+#define BM_UART_SFIFO_TXOF   (0x02U)       //!< Bit mask for UART_SFIFO_TXOF.
+#define BS_UART_SFIFO_TXOF   (1U)          //!< Bit field size in bits for UART_SFIFO_TXOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_TXOF field.
+#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
+#endif
+
+//! @brief Format value for bitfield UART_SFIFO_TXOF.
+#define BF_UART_SFIFO_TXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_TXOF), uint8_t) & BM_UART_SFIFO_TXOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXOF field to a new value.
+#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+//@{
+#define BP_UART_SFIFO_RXOF   (2U)          //!< Bit position for UART_SFIFO_RXOF.
+#define BM_UART_SFIFO_RXOF   (0x04U)       //!< Bit mask for UART_SFIFO_RXOF.
+#define BS_UART_SFIFO_RXOF   (1U)          //!< Bit field size in bits for UART_SFIFO_RXOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_RXOF field.
+#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
+#endif
+
+//! @brief Format value for bitfield UART_SFIFO_RXOF.
+#define BF_UART_SFIFO_RXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXOF), uint8_t) & BM_UART_SFIFO_RXOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXOF field to a new value.
+#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0 - Receive buffer is not empty.
+ * - 1 - Receive buffer is empty.
+ */
+//@{
+#define BP_UART_SFIFO_RXEMPT (6U)          //!< Bit position for UART_SFIFO_RXEMPT.
+#define BM_UART_SFIFO_RXEMPT (0x40U)       //!< Bit mask for UART_SFIFO_RXEMPT.
+#define BS_UART_SFIFO_RXEMPT (1U)          //!< Bit field size in bits for UART_SFIFO_RXEMPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_RXEMPT field.
+#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0 - Transmit buffer is not empty.
+ * - 1 - Transmit buffer is empty.
+ */
+//@{
+#define BP_UART_SFIFO_TXEMPT (7U)          //!< Bit position for UART_SFIFO_TXEMPT.
+#define BM_UART_SFIFO_TXEMPT (0x80U)       //!< Bit mask for UART_SFIFO_TXEMPT.
+#define BS_UART_SFIFO_TXEMPT (1U)          //!< Bit field size in bits for UART_SFIFO_TXEMPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_TXEMPT field.
+#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_TWFIFO - UART FIFO Transmit Watermark
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+typedef union _hw_uart_twfifo
+{
+    uint8_t U;
+    struct _hw_uart_twfifo_bitfields
+    {
+        uint8_t TXWATER : 8;           //!< [7:0] Transmit Watermark
+    } B;
+} hw_uart_twfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+//@{
+#define HW_UART_TWFIFO_ADDR(x)   (REGS_UART_BASE(x) + 0x13U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_TWFIFO(x)        (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x))
+#define HW_UART_TWFIFO_RD(x)     (HW_UART_TWFIFO(x).U)
+#define HW_UART_TWFIFO_WR(x, v)  (HW_UART_TWFIFO(x).U = (v))
+#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) |  (v)))
+#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
+#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_TWFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
+ *
+ * When the number of datawords in the transmit FIFO/buffer is equal to or less
+ * than the value in this register field, an interrupt via S1[TDRE] or a DMA
+ * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
+ * proper operation, the value in TXWATER must be set to be less than the size of
+ * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
+ */
+//@{
+#define BP_UART_TWFIFO_TXWATER (0U)        //!< Bit position for UART_TWFIFO_TXWATER.
+#define BM_UART_TWFIFO_TXWATER (0xFFU)     //!< Bit mask for UART_TWFIFO_TXWATER.
+#define BS_UART_TWFIFO_TXWATER (8U)        //!< Bit field size in bits for UART_TWFIFO_TXWATER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_TWFIFO_TXWATER field.
+#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_TWFIFO_TXWATER.
+#define BF_UART_TWFIFO_TXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TWFIFO_TXWATER), uint8_t) & BM_UART_TWFIFO_TXWATER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXWATER field to a new value.
+#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_TCFIFO - UART FIFO Transmit Count
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+typedef union _hw_uart_tcfifo
+{
+    uint8_t U;
+    struct _hw_uart_tcfifo_bitfields
+    {
+        uint8_t TXCOUNT : 8;           //!< [7:0] Transmit Counter
+    } B;
+} hw_uart_tcfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+//@{
+#define HW_UART_TCFIFO_ADDR(x)   (REGS_UART_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_TCFIFO(x)        (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x))
+#define HW_UART_TCFIFO_RD(x)     (HW_UART_TCFIFO(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_TCFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
+ *
+ * The value in this register indicates the number of datawords that are in the
+ * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
+ * transmit shift register, it is not included in the count. This value may be used
+ * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
+ * transmit FIFO/buffer.
+ */
+//@{
+#define BP_UART_TCFIFO_TXCOUNT (0U)        //!< Bit position for UART_TCFIFO_TXCOUNT.
+#define BM_UART_TCFIFO_TXCOUNT (0xFFU)     //!< Bit mask for UART_TCFIFO_TXCOUNT.
+#define BS_UART_TCFIFO_TXCOUNT (8U)        //!< Bit field size in bits for UART_TCFIFO_TXCOUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_TCFIFO_TXCOUNT field.
+#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_RWFIFO - UART FIFO Receive Watermark
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+typedef union _hw_uart_rwfifo
+{
+    uint8_t U;
+    struct _hw_uart_rwfifo_bitfields
+    {
+        uint8_t RXWATER : 8;           //!< [7:0] Receive Watermark
+    } B;
+} hw_uart_rwfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+//@{
+#define HW_UART_RWFIFO_ADDR(x)   (REGS_UART_BASE(x) + 0x15U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_RWFIFO(x)        (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x))
+#define HW_UART_RWFIFO_RD(x)     (HW_UART_RWFIFO(x).U)
+#define HW_UART_RWFIFO_WR(x, v)  (HW_UART_RWFIFO(x).U = (v))
+#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) |  (v)))
+#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
+#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_RWFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
+ *
+ * When the number of datawords in the receive FIFO/buffer is equal to or
+ * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
+ * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
+ * proper operation, the value in RXWATER must be set to be less than the receive
+ * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
+ * greater than 0.
+ */
+//@{
+#define BP_UART_RWFIFO_RXWATER (0U)        //!< Bit position for UART_RWFIFO_RXWATER.
+#define BM_UART_RWFIFO_RXWATER (0xFFU)     //!< Bit mask for UART_RWFIFO_RXWATER.
+#define BS_UART_RWFIFO_RXWATER (8U)        //!< Bit field size in bits for UART_RWFIFO_RXWATER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_RWFIFO_RXWATER field.
+#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_RWFIFO_RXWATER.
+#define BF_UART_RWFIFO_RXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_RWFIFO_RXWATER), uint8_t) & BM_UART_RWFIFO_RXWATER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXWATER field to a new value.
+#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_RCFIFO - UART FIFO Receive Count
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+typedef union _hw_uart_rcfifo
+{
+    uint8_t U;
+    struct _hw_uart_rcfifo_bitfields
+    {
+        uint8_t RXCOUNT : 8;           //!< [7:0] Receive Counter
+    } B;
+} hw_uart_rcfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+//@{
+#define HW_UART_RCFIFO_ADDR(x)   (REGS_UART_BASE(x) + 0x16U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_RCFIFO(x)        (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x))
+#define HW_UART_RCFIFO_RD(x)     (HW_UART_RCFIFO(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_RCFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
+ *
+ * The value in this register indicates the number of datawords that are in the
+ * receive FIFO/buffer. If a dataword is being received, that is, in the receive
+ * shift register, it is not included in the count. This value may be used in
+ * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
+ * receive FIFO/buffer.
+ */
+//@{
+#define BP_UART_RCFIFO_RXCOUNT (0U)        //!< Bit position for UART_RCFIFO_RXCOUNT.
+#define BM_UART_RCFIFO_RXCOUNT (0xFFU)     //!< Bit mask for UART_RCFIFO_RXCOUNT.
+#define BS_UART_RCFIFO_RXCOUNT (8U)        //!< Bit field size in bits for UART_RCFIFO_RXCOUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_RCFIFO_RXCOUNT field.
+#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C7816 - UART 7816 Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+typedef union _hw_uart_c7816
+{
+    uint8_t U;
+    struct _hw_uart_c7816_bitfields
+    {
+        uint8_t ISO_7816E : 1;         //!< [0] ISO-7816 Functionality Enabled
+        uint8_t TTYPE : 1;             //!< [1] Transfer Type
+        uint8_t INIT : 1;              //!< [2] Detect Initial Character
+        uint8_t ANACK : 1;             //!< [3] Generate NACK on Error
+        uint8_t ONACK : 1;             //!< [4] Generate NACK on Overflow
+        uint8_t RESERVED0 : 3;         //!< [7:5]
+    } B;
+} hw_uart_c7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+//@{
+#define HW_UART_C7816_ADDR(x)    (REGS_UART_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C7816(x)         (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x))
+#define HW_UART_C7816_RD(x)      (HW_UART_C7816(x).U)
+#define HW_UART_C7816_WR(x, v)   (HW_UART_C7816(x).U = (v))
+#define HW_UART_C7816_SET(x, v)  (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) |  (v)))
+#define HW_UART_C7816_CLR(x, v)  (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
+#define HW_UART_C7816_TOG(x, v)  (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0 - ISO-7816 functionality is turned off/not enabled.
+ * - 1 - ISO-7816 functionality is turned on/enabled.
+ */
+//@{
+#define BP_UART_C7816_ISO_7816E (0U)       //!< Bit position for UART_C7816_ISO_7816E.
+#define BM_UART_C7816_ISO_7816E (0x01U)    //!< Bit mask for UART_C7816_ISO_7816E.
+#define BS_UART_C7816_ISO_7816E (1U)       //!< Bit field size in bits for UART_C7816_ISO_7816E.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_ISO_7816E field.
+#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_ISO_7816E.
+#define BF_UART_C7816_ISO_7816E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ISO_7816E), uint8_t) & BM_UART_C7816_ISO_7816E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ISO_7816E field to a new value.
+#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0 - T = 0 per the ISO-7816 specification.
+ * - 1 - T = 1 per the ISO-7816 specification.
+ */
+//@{
+#define BP_UART_C7816_TTYPE  (1U)          //!< Bit position for UART_C7816_TTYPE.
+#define BM_UART_C7816_TTYPE  (0x02U)       //!< Bit mask for UART_C7816_TTYPE.
+#define BS_UART_C7816_TTYPE  (1U)          //!< Bit field size in bits for UART_C7816_TTYPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_TTYPE field.
+#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_TTYPE.
+#define BF_UART_C7816_TTYPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_TTYPE), uint8_t) & BM_UART_C7816_TTYPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TTYPE field to a new value.
+#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 1 - Receiver searches for initial character.
+ */
+//@{
+#define BP_UART_C7816_INIT   (2U)          //!< Bit position for UART_C7816_INIT.
+#define BM_UART_C7816_INIT   (0x04U)       //!< Bit mask for UART_C7816_INIT.
+#define BS_UART_C7816_INIT   (1U)          //!< Bit field size in bits for UART_C7816_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_INIT field.
+#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_INIT.
+#define BF_UART_C7816_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_INIT), uint8_t) & BM_UART_C7816_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INIT field to a new value.
+#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0 - No NACK is automatically generated.
+ * - 1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+//@{
+#define BP_UART_C7816_ANACK  (3U)          //!< Bit position for UART_C7816_ANACK.
+#define BM_UART_C7816_ANACK  (0x08U)       //!< Bit mask for UART_C7816_ANACK.
+#define BS_UART_C7816_ANACK  (1U)          //!< Bit field size in bits for UART_C7816_ANACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_ANACK field.
+#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_ANACK.
+#define BF_UART_C7816_ANACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ANACK), uint8_t) & BM_UART_C7816_ANACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ANACK field to a new value.
+#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0 - The received data does not generate a NACK when the receipt of the data
+ *     results in an overflow event.
+ * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+//@{
+#define BP_UART_C7816_ONACK  (4U)          //!< Bit position for UART_C7816_ONACK.
+#define BM_UART_C7816_ONACK  (0x10U)       //!< Bit mask for UART_C7816_ONACK.
+#define BS_UART_C7816_ONACK  (1U)          //!< Bit field size in bits for UART_C7816_ONACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_ONACK field.
+#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_ONACK.
+#define BF_UART_C7816_ONACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ONACK), uint8_t) & BM_UART_C7816_ONACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONACK field to a new value.
+#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_IE7816 - UART 7816 Interrupt Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+typedef union _hw_uart_ie7816
+{
+    uint8_t U;
+    struct _hw_uart_ie7816_bitfields
+    {
+        uint8_t RXTE : 1;              //!< [0] Receive Threshold Exceeded Interrupt Enable
+        uint8_t TXTE : 1;              //!< [1] Transmit Threshold Exceeded Interrupt
+                                       //! Enable
+        uint8_t GTVE : 1;              //!< [2] Guard Timer Violated Interrupt Enable
+        uint8_t RESERVED0 : 1;         //!< [3]
+        uint8_t INITDE : 1;            //!< [4] Initial Character Detected Interrupt
+                                       //! Enable
+        uint8_t BWTE : 1;              //!< [5] Block Wait Timer Interrupt Enable
+        uint8_t CWTE : 1;              //!< [6] Character Wait Timer Interrupt Enable
+        uint8_t WTE : 1;               //!< [7] Wait Timer Interrupt Enable
+    } B;
+} hw_uart_ie7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+//@{
+#define HW_UART_IE7816_ADDR(x)   (REGS_UART_BASE(x) + 0x19U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_IE7816(x)        (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x))
+#define HW_UART_IE7816_RD(x)     (HW_UART_IE7816(x).U)
+#define HW_UART_IE7816_WR(x, v)  (HW_UART_IE7816(x).U = (v))
+#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) |  (v)))
+#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
+#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_RXTE  (0U)          //!< Bit position for UART_IE7816_RXTE.
+#define BM_UART_IE7816_RXTE  (0x01U)       //!< Bit mask for UART_IE7816_RXTE.
+#define BS_UART_IE7816_RXTE  (1U)          //!< Bit field size in bits for UART_IE7816_RXTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_RXTE field.
+#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_RXTE.
+#define BF_UART_IE7816_RXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_RXTE), uint8_t) & BM_UART_IE7816_RXTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXTE field to a new value.
+#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_TXTE  (1U)          //!< Bit position for UART_IE7816_TXTE.
+#define BM_UART_IE7816_TXTE  (0x02U)       //!< Bit mask for UART_IE7816_TXTE.
+#define BS_UART_IE7816_TXTE  (1U)          //!< Bit field size in bits for UART_IE7816_TXTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_TXTE field.
+#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_TXTE.
+#define BF_UART_IE7816_TXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_TXTE), uint8_t) & BM_UART_IE7816_TXTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXTE field to a new value.
+#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_GTVE  (2U)          //!< Bit position for UART_IE7816_GTVE.
+#define BM_UART_IE7816_GTVE  (0x04U)       //!< Bit mask for UART_IE7816_GTVE.
+#define BS_UART_IE7816_GTVE  (1U)          //!< Bit field size in bits for UART_IE7816_GTVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_GTVE field.
+#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_GTVE.
+#define BF_UART_IE7816_GTVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_GTVE), uint8_t) & BM_UART_IE7816_GTVE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTVE field to a new value.
+#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+//@{
+#define BP_UART_IE7816_INITDE (4U)         //!< Bit position for UART_IE7816_INITDE.
+#define BM_UART_IE7816_INITDE (0x10U)      //!< Bit mask for UART_IE7816_INITDE.
+#define BS_UART_IE7816_INITDE (1U)         //!< Bit field size in bits for UART_IE7816_INITDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_INITDE field.
+#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_INITDE.
+#define BF_UART_IE7816_INITDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_INITDE), uint8_t) & BM_UART_IE7816_INITDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITDE field to a new value.
+#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_BWTE  (5U)          //!< Bit position for UART_IE7816_BWTE.
+#define BM_UART_IE7816_BWTE  (0x20U)       //!< Bit mask for UART_IE7816_BWTE.
+#define BS_UART_IE7816_BWTE  (1U)          //!< Bit field size in bits for UART_IE7816_BWTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_BWTE field.
+#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_BWTE.
+#define BF_UART_IE7816_BWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_BWTE), uint8_t) & BM_UART_IE7816_BWTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWTE field to a new value.
+#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_CWTE  (6U)          //!< Bit position for UART_IE7816_CWTE.
+#define BM_UART_IE7816_CWTE  (0x40U)       //!< Bit mask for UART_IE7816_CWTE.
+#define BS_UART_IE7816_CWTE  (1U)          //!< Bit field size in bits for UART_IE7816_CWTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_CWTE field.
+#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_CWTE.
+#define BF_UART_IE7816_CWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_CWTE), uint8_t) & BM_UART_IE7816_CWTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CWTE field to a new value.
+#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_WTE   (7U)          //!< Bit position for UART_IE7816_WTE.
+#define BM_UART_IE7816_WTE   (0x80U)       //!< Bit mask for UART_IE7816_WTE.
+#define BS_UART_IE7816_WTE   (1U)          //!< Bit field size in bits for UART_IE7816_WTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_WTE field.
+#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_WTE.
+#define BF_UART_IE7816_WTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_WTE), uint8_t) & BM_UART_IE7816_WTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WTE field to a new value.
+#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_IS7816 - UART 7816 Interrupt Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+typedef union _hw_uart_is7816
+{
+    uint8_t U;
+    struct _hw_uart_is7816_bitfields
+    {
+        uint8_t RXT : 1;               //!< [0] Receive Threshold Exceeded Interrupt
+        uint8_t TXT : 1;               //!< [1] Transmit Threshold Exceeded Interrupt
+        uint8_t GTV : 1;               //!< [2] Guard Timer Violated Interrupt
+        uint8_t RESERVED0 : 1;         //!< [3]
+        uint8_t INITD : 1;             //!< [4] Initial Character Detected Interrupt
+        uint8_t BWT : 1;               //!< [5] Block Wait Timer Interrupt
+        uint8_t CWT : 1;               //!< [6] Character Wait Timer Interrupt
+        uint8_t WT : 1;                //!< [7] Wait Timer Interrupt
+    } B;
+} hw_uart_is7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+//@{
+#define HW_UART_IS7816_ADDR(x)   (REGS_UART_BASE(x) + 0x1AU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_IS7816(x)        (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x))
+#define HW_UART_IS7816_RD(x)     (HW_UART_IS7816(x).U)
+#define HW_UART_IS7816_WR(x, v)  (HW_UART_IS7816(x).U = (v))
+#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) |  (v)))
+#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
+#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - The number of consecutive NACKS generated as a result of parity errors
+ *     and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 1 - The number of consecutive NACKS generated as a result of parity errors
+ *     and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+//@{
+#define BP_UART_IS7816_RXT   (0U)          //!< Bit position for UART_IS7816_RXT.
+#define BM_UART_IS7816_RXT   (0x01U)       //!< Bit mask for UART_IS7816_RXT.
+#define BS_UART_IS7816_RXT   (1U)          //!< Bit field size in bits for UART_IS7816_RXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_RXT field.
+#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_RXT.
+#define BF_UART_IS7816_RXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_RXT), uint8_t) & BM_UART_IS7816_RXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXT field to a new value.
+#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - The number of retries and corresponding NACKS does not exceed the value
+ *     in ET7816[TXTHRESHOLD].
+ * - 1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+//@{
+#define BP_UART_IS7816_TXT   (1U)          //!< Bit position for UART_IS7816_TXT.
+#define BM_UART_IS7816_TXT   (0x02U)       //!< Bit mask for UART_IS7816_TXT.
+#define BS_UART_IS7816_TXT   (1U)          //!< Bit field size in bits for UART_IS7816_TXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_TXT field.
+#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_TXT.
+#define BF_UART_IS7816_TXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_TXT), uint8_t) & BM_UART_IS7816_TXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXT field to a new value.
+#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_GTV   (2U)          //!< Bit position for UART_IS7816_GTV.
+#define BM_UART_IS7816_GTV   (0x04U)       //!< Bit mask for UART_IS7816_GTV.
+#define BS_UART_IS7816_GTV   (1U)          //!< Bit field size in bits for UART_IS7816_GTV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_GTV field.
+#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_GTV.
+#define BF_UART_IS7816_GTV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_GTV), uint8_t) & BM_UART_IS7816_GTV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTV field to a new value.
+#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0 - A valid initial character has not been received.
+ * - 1 - A valid initial character has been received.
+ */
+//@{
+#define BP_UART_IS7816_INITD (4U)          //!< Bit position for UART_IS7816_INITD.
+#define BM_UART_IS7816_INITD (0x10U)       //!< Bit mask for UART_IS7816_INITD.
+#define BS_UART_IS7816_INITD (1U)          //!< Bit field size in bits for UART_IS7816_INITD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_INITD field.
+#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_INITD.
+#define BF_UART_IS7816_INITD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_INITD), uint8_t) & BM_UART_IS7816_INITD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITD field to a new value.
+#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - Block wait time (BWT) has not been violated.
+ * - 1 - Block wait time (BWT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_BWT   (5U)          //!< Bit position for UART_IS7816_BWT.
+#define BM_UART_IS7816_BWT   (0x20U)       //!< Bit mask for UART_IS7816_BWT.
+#define BS_UART_IS7816_BWT   (1U)          //!< Bit field size in bits for UART_IS7816_BWT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_BWT field.
+#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_BWT.
+#define BF_UART_IS7816_BWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_BWT), uint8_t) & BM_UART_IS7816_BWT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWT field to a new value.
+#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0 - Character wait time (CWT) has not been violated.
+ * - 1 - Character wait time (CWT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_CWT   (6U)          //!< Bit position for UART_IS7816_CWT.
+#define BM_UART_IS7816_CWT   (0x40U)       //!< Bit mask for UART_IS7816_CWT.
+#define BS_UART_IS7816_CWT   (1U)          //!< Bit field size in bits for UART_IS7816_CWT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_CWT field.
+#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_CWT.
+#define BF_UART_IS7816_CWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_CWT), uint8_t) & BM_UART_IS7816_CWT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CWT field to a new value.
+#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - Wait time (WT) has not been violated.
+ * - 1 - Wait time (WT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_WT    (7U)          //!< Bit position for UART_IS7816_WT.
+#define BM_UART_IS7816_WT    (0x80U)       //!< Bit mask for UART_IS7816_WT.
+#define BS_UART_IS7816_WT    (1U)          //!< Bit field size in bits for UART_IS7816_WT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_WT field.
+#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_WT.
+#define BF_UART_IS7816_WT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_WT), uint8_t) & BM_UART_IS7816_WT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WT field to a new value.
+#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wp7816_t_type0
+{
+    uint8_t U;
+    struct _hw_uart_wp7816_t_type0_bitfields
+    {
+        uint8_t WI : 8;                //!< [7:0] Wait Time Integer (C7816[TTYPE] = 0)
+    } B;
+} hw_uart_wp7816_t_type0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WP7816_T_TYPE0 register
+ */
+//@{
+#define HW_UART_WP7816_T_TYPE0_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WP7816_T_TYPE0(x) (*(__IO hw_uart_wp7816_t_type0_t *) HW_UART_WP7816_T_TYPE0_ADDR(x))
+#define HW_UART_WP7816_T_TYPE0_RD(x) (HW_UART_WP7816_T_TYPE0(x).U)
+#define HW_UART_WP7816_T_TYPE0_WR(x, v) (HW_UART_WP7816_T_TYPE0(x).U = (v))
+#define HW_UART_WP7816_T_TYPE0_SET(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) |  (v)))
+#define HW_UART_WP7816_T_TYPE0_CLR(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) & ~(v)))
+#define HW_UART_WP7816_T_TYPE0_TOG(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WP7816_T_TYPE0 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816_T_TYPE0, field WI[7:0] (RW)
+ *
+ * Used to calculate the value used for the WT counter. It represents a value
+ * between 1 and 255. The value of zero is not valid. This value is used only when
+ * C7816[TTYPE] = 0. See Wait time and guard time parameters.
+ */
+//@{
+#define BP_UART_WP7816_T_TYPE0_WI (0U)     //!< Bit position for UART_WP7816_T_TYPE0_WI.
+#define BM_UART_WP7816_T_TYPE0_WI (0xFFU)  //!< Bit mask for UART_WP7816_T_TYPE0_WI.
+#define BS_UART_WP7816_T_TYPE0_WI (8U)     //!< Bit field size in bits for UART_WP7816_T_TYPE0_WI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WP7816_T_TYPE0_WI field.
+#define BR_UART_WP7816_T_TYPE0_WI(x) (HW_UART_WP7816_T_TYPE0(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_WP7816_T_TYPE0_WI.
+#define BF_UART_WP7816_T_TYPE0_WI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE0_WI), uint8_t) & BM_UART_WP7816_T_TYPE0_WI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WI field to a new value.
+#define BW_UART_WP7816_T_TYPE0_WI(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wp7816_t_type1
+{
+    uint8_t U;
+    struct _hw_uart_wp7816_t_type1_bitfields
+    {
+        uint8_t BWI : 4;               //!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
+        uint8_t CWI : 4;               //!< [7:4] Character Wait Time Integer (C7816[TTYPE]
+                                       //! = 1)
+    } B;
+} hw_uart_wp7816_t_type1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WP7816_T_TYPE1 register
+ */
+//@{
+#define HW_UART_WP7816_T_TYPE1_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WP7816_T_TYPE1(x) (*(__IO hw_uart_wp7816_t_type1_t *) HW_UART_WP7816_T_TYPE1_ADDR(x))
+#define HW_UART_WP7816_T_TYPE1_RD(x) (HW_UART_WP7816_T_TYPE1(x).U)
+#define HW_UART_WP7816_T_TYPE1_WR(x, v) (HW_UART_WP7816_T_TYPE1(x).U = (v))
+#define HW_UART_WP7816_T_TYPE1_SET(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) |  (v)))
+#define HW_UART_WP7816_T_TYPE1_CLR(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) & ~(v)))
+#define HW_UART_WP7816_T_TYPE1_TOG(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WP7816_T_TYPE1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816_T_TYPE1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+//@{
+#define BP_UART_WP7816_T_TYPE1_BWI (0U)    //!< Bit position for UART_WP7816_T_TYPE1_BWI.
+#define BM_UART_WP7816_T_TYPE1_BWI (0x0FU) //!< Bit mask for UART_WP7816_T_TYPE1_BWI.
+#define BS_UART_WP7816_T_TYPE1_BWI (4U)    //!< Bit field size in bits for UART_WP7816_T_TYPE1_BWI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WP7816_T_TYPE1_BWI field.
+#define BR_UART_WP7816_T_TYPE1_BWI(x) (HW_UART_WP7816_T_TYPE1(x).B.BWI)
+#endif
+
+//! @brief Format value for bitfield UART_WP7816_T_TYPE1_BWI.
+#define BF_UART_WP7816_T_TYPE1_BWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_BWI), uint8_t) & BM_UART_WP7816_T_TYPE1_BWI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWI field to a new value.
+#define BW_UART_WP7816_T_TYPE1_BWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_BWI) | BF_UART_WP7816_T_TYPE1_BWI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_WP7816_T_TYPE1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+//@{
+#define BP_UART_WP7816_T_TYPE1_CWI (4U)    //!< Bit position for UART_WP7816_T_TYPE1_CWI.
+#define BM_UART_WP7816_T_TYPE1_CWI (0xF0U) //!< Bit mask for UART_WP7816_T_TYPE1_CWI.
+#define BS_UART_WP7816_T_TYPE1_CWI (4U)    //!< Bit field size in bits for UART_WP7816_T_TYPE1_CWI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WP7816_T_TYPE1_CWI field.
+#define BR_UART_WP7816_T_TYPE1_CWI(x) (HW_UART_WP7816_T_TYPE1(x).B.CWI)
+#endif
+
+//! @brief Format value for bitfield UART_WP7816_T_TYPE1_CWI.
+#define BF_UART_WP7816_T_TYPE1_CWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_CWI), uint8_t) & BM_UART_WP7816_T_TYPE1_CWI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CWI field to a new value.
+#define BW_UART_WP7816_T_TYPE1_CWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_CWI) | BF_UART_WP7816_T_TYPE1_CWI(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_WN7816 - UART 7816 Wait N Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wn7816
+{
+    uint8_t U;
+    struct _hw_uart_wn7816_bitfields
+    {
+        uint8_t GTN : 8;               //!< [7:0] Guard Band N
+    } B;
+} hw_uart_wn7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+//@{
+#define HW_UART_WN7816_ADDR(x)   (REGS_UART_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WN7816(x)        (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x))
+#define HW_UART_WN7816_RD(x)     (HW_UART_WN7816(x).U)
+#define HW_UART_WN7816_WR(x, v)  (HW_UART_WN7816(x).U = (v))
+#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) |  (v)))
+#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
+#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WN7816 bitfields
+ */
+
+/*!
+ * @name Register UART_WN7816, field GTN[7:0] (RW)
+ *
+ * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
+ * value represents an integer number between 0 and 255. See Wait time and guard
+ * time parameters .
+ */
+//@{
+#define BP_UART_WN7816_GTN   (0U)          //!< Bit position for UART_WN7816_GTN.
+#define BM_UART_WN7816_GTN   (0xFFU)       //!< Bit mask for UART_WN7816_GTN.
+#define BS_UART_WN7816_GTN   (8U)          //!< Bit field size in bits for UART_WN7816_GTN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WN7816_GTN field.
+#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_WN7816_GTN.
+#define BF_UART_WN7816_GTN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WN7816_GTN), uint8_t) & BM_UART_WN7816_GTN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTN field to a new value.
+#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_WF7816 - UART 7816 Wait FD Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wf7816
+{
+    uint8_t U;
+    struct _hw_uart_wf7816_bitfields
+    {
+        uint8_t GTFD : 8;              //!< [7:0] FD Multiplier
+    } B;
+} hw_uart_wf7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+//@{
+#define HW_UART_WF7816_ADDR(x)   (REGS_UART_BASE(x) + 0x1DU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WF7816(x)        (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x))
+#define HW_UART_WF7816_RD(x)     (HW_UART_WF7816(x).U)
+#define HW_UART_WF7816_WR(x, v)  (HW_UART_WF7816(x).U = (v))
+#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) |  (v)))
+#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
+#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WF7816 bitfields
+ */
+
+/*!
+ * @name Register UART_WF7816, field GTFD[7:0] (RW)
+ *
+ * Used as another multiplier in the calculation of WT and BWT. This value
+ * represents a number between 1 and 255. The value of 0 is invalid. This value is not
+ * used in baud rate generation. See Wait time and guard time parameters and
+ * Baud rate generation .
+ */
+//@{
+#define BP_UART_WF7816_GTFD  (0U)          //!< Bit position for UART_WF7816_GTFD.
+#define BM_UART_WF7816_GTFD  (0xFFU)       //!< Bit mask for UART_WF7816_GTFD.
+#define BS_UART_WF7816_GTFD  (8U)          //!< Bit field size in bits for UART_WF7816_GTFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WF7816_GTFD field.
+#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_WF7816_GTFD.
+#define BF_UART_WF7816_GTFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WF7816_GTFD), uint8_t) & BM_UART_WF7816_GTFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTFD field to a new value.
+#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_ET7816 - UART 7816 Error Threshold Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_et7816
+{
+    uint8_t U;
+    struct _hw_uart_et7816_bitfields
+    {
+        uint8_t RXTHRESHOLD : 4;       //!< [3:0] Receive NACK Threshold
+        uint8_t TXTHRESHOLD : 4;       //!< [7:4] Transmit NACK Threshold
+    } B;
+} hw_uart_et7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+//@{
+#define HW_UART_ET7816_ADDR(x)   (REGS_UART_BASE(x) + 0x1EU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_ET7816(x)        (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x))
+#define HW_UART_ET7816_RD(x)     (HW_UART_ET7816(x).U)
+#define HW_UART_ET7816_WR(x, v)  (HW_UART_ET7816(x).U = (v))
+#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) |  (v)))
+#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
+#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+//@{
+#define BP_UART_ET7816_RXTHRESHOLD (0U)    //!< Bit position for UART_ET7816_RXTHRESHOLD.
+#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) //!< Bit mask for UART_ET7816_RXTHRESHOLD.
+#define BS_UART_ET7816_RXTHRESHOLD (4U)    //!< Bit field size in bits for UART_ET7816_RXTHRESHOLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ET7816_RXTHRESHOLD field.
+#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
+#endif
+
+//! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD.
+#define BF_UART_ET7816_RXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_RXTHRESHOLD), uint8_t) & BM_UART_ET7816_RXTHRESHOLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXTHRESHOLD field to a new value.
+#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0 - TXT asserts on the first NACK that is received.
+ * - 1 - TXT asserts on the second NACK that is received.
+ */
+//@{
+#define BP_UART_ET7816_TXTHRESHOLD (4U)    //!< Bit position for UART_ET7816_TXTHRESHOLD.
+#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) //!< Bit mask for UART_ET7816_TXTHRESHOLD.
+#define BS_UART_ET7816_TXTHRESHOLD (4U)    //!< Bit field size in bits for UART_ET7816_TXTHRESHOLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ET7816_TXTHRESHOLD field.
+#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
+#endif
+
+//! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD.
+#define BF_UART_ET7816_TXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_TXTHRESHOLD), uint8_t) & BM_UART_ET7816_TXTHRESHOLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXTHRESHOLD field to a new value.
+#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_TL7816 - UART 7816 Transmit Length Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+typedef union _hw_uart_tl7816
+{
+    uint8_t U;
+    struct _hw_uart_tl7816_bitfields
+    {
+        uint8_t TLEN : 8;              //!< [7:0] Transmit Length
+    } B;
+} hw_uart_tl7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+//@{
+#define HW_UART_TL7816_ADDR(x)   (REGS_UART_BASE(x) + 0x1FU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_TL7816(x)        (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x))
+#define HW_UART_TL7816_RD(x)     (HW_UART_TL7816(x).U)
+#define HW_UART_TL7816_WR(x, v)  (HW_UART_TL7816(x).U = (v))
+#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) |  (v)))
+#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
+#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_TL7816 bitfields
+ */
+
+/*!
+ * @name Register UART_TL7816, field TLEN[7:0] (RW)
+ *
+ * This value plus four indicates the number of characters contained in the
+ * block being transmitted. This register is automatically decremented by 1 for each
+ * character in the information field portion of the block. Additionally, this
+ * register is automatically decremented by 1 for the first character of a CRC in
+ * the epilogue field. Therefore, this register must be programmed with the number
+ * of bytes in the data packet if an LRC is being transmitted, and the number of
+ * bytes + 1 if a CRC is being transmitted. This register is not decremented for
+ * characters that are assumed to be part of the Prologue field, that is, the
+ * first three characters transmitted in a block, or the LRC or last CRC character
+ * in the Epilogue field, that is, the last character transmitted. This field
+ * must be programed or adjusted only when C2[TE] is cleared.
+ */
+//@{
+#define BP_UART_TL7816_TLEN  (0U)          //!< Bit position for UART_TL7816_TLEN.
+#define BM_UART_TL7816_TLEN  (0xFFU)       //!< Bit mask for UART_TL7816_TLEN.
+#define BS_UART_TL7816_TLEN  (8U)          //!< Bit field size in bits for UART_TL7816_TLEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_TL7816_TLEN field.
+#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_TL7816_TLEN.
+#define BF_UART_TL7816_TLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TL7816_TLEN), uint8_t) & BM_UART_TL7816_TLEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TLEN field to a new value.
+#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_uart_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All UART module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_uart
+{
+    __IO hw_uart_bdh_t BDH;                //!< [0x0] UART Baud Rate Registers: High
+    __IO hw_uart_bdl_t BDL;                //!< [0x1] UART Baud Rate Registers: Low
+    __IO hw_uart_c1_t C1;                  //!< [0x2] UART Control Register 1
+    __IO hw_uart_c2_t C2;                  //!< [0x3] UART Control Register 2
+    __I hw_uart_s1_t S1;                   //!< [0x4] UART Status Register 1
+    __IO hw_uart_s2_t S2;                  //!< [0x5] UART Status Register 2
+    __IO hw_uart_c3_t C3;                  //!< [0x6] UART Control Register 3
+    __IO hw_uart_d_t D;                    //!< [0x7] UART Data Register
+    __IO hw_uart_ma1_t MA1;                //!< [0x8] UART Match Address Registers 1
+    __IO hw_uart_ma2_t MA2;                //!< [0x9] UART Match Address Registers 2
+    __IO hw_uart_c4_t C4;                  //!< [0xA] UART Control Register 4
+    __IO hw_uart_c5_t C5;                  //!< [0xB] UART Control Register 5
+    __I hw_uart_ed_t ED;                   //!< [0xC] UART Extended Data Register
+    __IO hw_uart_modem_t MODEM;            //!< [0xD] UART Modem Register
+    __IO hw_uart_ir_t IR;                  //!< [0xE] UART Infrared Register
+    uint8_t _reserved0[1];
+    __IO hw_uart_pfifo_t PFIFO;            //!< [0x10] UART FIFO Parameters
+    __IO hw_uart_cfifo_t CFIFO;            //!< [0x11] UART FIFO Control Register
+    __IO hw_uart_sfifo_t SFIFO;            //!< [0x12] UART FIFO Status Register
+    __IO hw_uart_twfifo_t TWFIFO;          //!< [0x13] UART FIFO Transmit Watermark
+    __I hw_uart_tcfifo_t TCFIFO;           //!< [0x14] UART FIFO Transmit Count
+    __IO hw_uart_rwfifo_t RWFIFO;          //!< [0x15] UART FIFO Receive Watermark
+    __I hw_uart_rcfifo_t RCFIFO;           //!< [0x16] UART FIFO Receive Count
+    uint8_t _reserved1[1];
+    __IO hw_uart_c7816_t C7816;            //!< [0x18] UART 7816 Control Register
+    __IO hw_uart_ie7816_t IE7816;          //!< [0x19] UART 7816 Interrupt Enable Register
+    __IO hw_uart_is7816_t IS7816;          //!< [0x1A] UART 7816 Interrupt Status Register
+    union {
+        __IO hw_uart_wp7816_t_type0_t WP7816_T_TYPE0; //!< [0x1B] UART 7816 Wait Parameter Register
+        __IO hw_uart_wp7816_t_type1_t WP7816_T_TYPE1; //!< [0x1B] UART 7816 Wait Parameter Register
+    };
+    __IO hw_uart_wn7816_t WN7816;          //!< [0x1C] UART 7816 Wait N Register
+    __IO hw_uart_wf7816_t WF7816;          //!< [0x1D] UART 7816 Wait FD Register
+    __IO hw_uart_et7816_t ET7816;          //!< [0x1E] UART 7816 Error Threshold Register
+    __IO hw_uart_tl7816_t TL7816;          //!< [0x1F] UART 7816 Transmit Length Register
+} hw_uart_t;
+#pragma pack()
+
+//! @brief Macro to access all UART registers.
+//! @param x UART instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_UART(0)</code>.
+#define HW_UART(x)     (*(hw_uart_t *) REGS_UART_BASE(x))
+#endif
+
+#endif // __HW_UART_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h
new file mode 100644
index 0000000000..7d6fa9cc39
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h
@@ -0,0 +1,4276 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_USB_REGISTERS_H__
+#define __HW_USB_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - HW_USB_PERID - Peripheral ID register
+ * - HW_USB_IDCOMP - Peripheral ID Complement register
+ * - HW_USB_REV - Peripheral Revision register
+ * - HW_USB_ADDINFO - Peripheral Additional Info register
+ * - HW_USB_OTGISTAT - OTG Interrupt Status register
+ * - HW_USB_OTGICR - OTG Interrupt Control register
+ * - HW_USB_OTGSTAT - OTG Status register
+ * - HW_USB_OTGCTL - OTG Control register
+ * - HW_USB_ISTAT - Interrupt Status register
+ * - HW_USB_INTEN - Interrupt Enable register
+ * - HW_USB_ERRSTAT - Error Interrupt Status register
+ * - HW_USB_ERREN - Error Interrupt Enable register
+ * - HW_USB_STAT - Status register
+ * - HW_USB_CTL - Control register
+ * - HW_USB_ADDR - Address register
+ * - HW_USB_BDTPAGE1 - BDT Page register 1
+ * - HW_USB_FRMNUML - Frame Number register Low
+ * - HW_USB_FRMNUMH - Frame Number register High
+ * - HW_USB_TOKEN - Token register
+ * - HW_USB_SOFTHLD - SOF Threshold register
+ * - HW_USB_BDTPAGE2 - BDT Page Register 2
+ * - HW_USB_BDTPAGE3 - BDT Page Register 3
+ * - HW_USB_ENDPTn - Endpoint Control register
+ * - HW_USB_USBCTRL - USB Control register
+ * - HW_USB_OBSERVE - USB OTG Observe register
+ * - HW_USB_CONTROL - USB OTG Control register
+ * - HW_USB_USBTRC0 - USB Transceiver Control register 0
+ * - HW_USB_USBFRMADJUST - Frame Adjust Register
+ * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ *
+ * - hw_usb_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_USB_BASE
+#define HW_USB_INSTANCE_COUNT (1U) //!< Number of instances of the USB module.
+#define REGS_USB_BASE (0x40072000U) //!< Base address for USB0.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_PERID - Peripheral ID register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+typedef union _hw_usb_perid
+{
+    uint8_t U;
+    struct _hw_usb_perid_bitfields
+    {
+        uint8_t ID : 6;                //!< [5:0] Peripheral Identification
+        uint8_t RESERVED0 : 2;         //!< [7:6]
+    } B;
+} hw_usb_perid_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+//@{
+#define HW_USB_PERID_ADDR        (REGS_USB_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_PERID             (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR)
+#define HW_USB_PERID_RD()        (HW_USB_PERID.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+//@{
+#define BP_USB_PERID_ID      (0U)          //!< Bit position for USB_PERID_ID.
+#define BM_USB_PERID_ID      (0x3FU)       //!< Bit mask for USB_PERID_ID.
+#define BS_USB_PERID_ID      (6U)          //!< Bit field size in bits for USB_PERID_ID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_PERID_ID field.
+#define BR_USB_PERID_ID      (HW_USB_PERID.B.ID)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_IDCOMP - Peripheral ID Complement register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+typedef union _hw_usb_idcomp
+{
+    uint8_t U;
+    struct _hw_usb_idcomp_bitfields
+    {
+        uint8_t NID : 6;               //!< [5:0]
+        uint8_t RESERVED0 : 2;         //!< [7:6]
+    } B;
+} hw_usb_idcomp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+//@{
+#define HW_USB_IDCOMP_ADDR       (REGS_USB_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_IDCOMP            (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR)
+#define HW_USB_IDCOMP_RD()       (HW_USB_IDCOMP.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+//@{
+#define BP_USB_IDCOMP_NID    (0U)          //!< Bit position for USB_IDCOMP_NID.
+#define BM_USB_IDCOMP_NID    (0x3FU)       //!< Bit mask for USB_IDCOMP_NID.
+#define BS_USB_IDCOMP_NID    (6U)          //!< Bit field size in bits for USB_IDCOMP_NID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_IDCOMP_NID field.
+#define BR_USB_IDCOMP_NID    (HW_USB_IDCOMP.B.NID)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_REV - Peripheral Revision register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+typedef union _hw_usb_rev
+{
+    uint8_t U;
+    struct _hw_usb_rev_bitfields
+    {
+        uint8_t REV : 8;               //!< [7:0] Revision
+    } B;
+} hw_usb_rev_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+//@{
+#define HW_USB_REV_ADDR          (REGS_USB_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_REV               (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR)
+#define HW_USB_REV_RD()          (HW_USB_REV.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_REV bitfields
+ */
+
+/*!
+ * @name Register USB_REV, field REV[7:0] (RO)
+ *
+ * Indicates the revision number of the USB Core.
+ */
+//@{
+#define BP_USB_REV_REV       (0U)          //!< Bit position for USB_REV_REV.
+#define BM_USB_REV_REV       (0xFFU)       //!< Bit mask for USB_REV_REV.
+#define BS_USB_REV_REV       (8U)          //!< Bit field size in bits for USB_REV_REV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_REV_REV field.
+#define BR_USB_REV_REV       (HW_USB_REV.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ADDINFO - Peripheral Additional Info register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+typedef union _hw_usb_addinfo
+{
+    uint8_t U;
+    struct _hw_usb_addinfo_bitfields
+    {
+        uint8_t IEHOST : 1;            //!< [0]
+        uint8_t RESERVED0 : 2;         //!< [2:1]
+        uint8_t IRQNUM : 5;            //!< [7:3] Assigned Interrupt Request Number
+    } B;
+} hw_usb_addinfo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+//@{
+#define HW_USB_ADDINFO_ADDR      (REGS_USB_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ADDINFO           (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR)
+#define HW_USB_ADDINFO_RD()      (HW_USB_ADDINFO.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+//@{
+#define BP_USB_ADDINFO_IEHOST (0U)         //!< Bit position for USB_ADDINFO_IEHOST.
+#define BM_USB_ADDINFO_IEHOST (0x01U)      //!< Bit mask for USB_ADDINFO_IEHOST.
+#define BS_USB_ADDINFO_IEHOST (1U)         //!< Bit field size in bits for USB_ADDINFO_IEHOST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDINFO_IEHOST field.
+#define BR_USB_ADDINFO_IEHOST (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR, BP_USB_ADDINFO_IEHOST))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+//@{
+#define BP_USB_ADDINFO_IRQNUM (3U)         //!< Bit position for USB_ADDINFO_IRQNUM.
+#define BM_USB_ADDINFO_IRQNUM (0xF8U)      //!< Bit mask for USB_ADDINFO_IRQNUM.
+#define BS_USB_ADDINFO_IRQNUM (5U)         //!< Bit field size in bits for USB_ADDINFO_IRQNUM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDINFO_IRQNUM field.
+#define BR_USB_ADDINFO_IRQNUM (HW_USB_ADDINFO.B.IRQNUM)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGISTAT - OTG Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+typedef union _hw_usb_otgistat
+{
+    uint8_t U;
+    struct _hw_usb_otgistat_bitfields
+    {
+        uint8_t AVBUSCHG : 1;          //!< [0]
+        uint8_t RESERVED0 : 1;         //!< [1]
+        uint8_t B_SESS_CHG : 1;        //!< [2]
+        uint8_t SESSVLDCHG : 1;        //!< [3]
+        uint8_t RESERVED1 : 1;         //!< [4]
+        uint8_t LINE_STATE_CHG : 1;    //!< [5]
+        uint8_t ONEMSEC : 1;           //!< [6]
+        uint8_t IDCHG : 1;             //!< [7]
+    } B;
+} hw_usb_otgistat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+//@{
+#define HW_USB_OTGISTAT_ADDR     (REGS_USB_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGISTAT          (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR)
+#define HW_USB_OTGISTAT_RD()     (HW_USB_OTGISTAT.U)
+#define HW_USB_OTGISTAT_WR(v)    (HW_USB_OTGISTAT.U = (v))
+#define HW_USB_OTGISTAT_SET(v)   (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() |  (v)))
+#define HW_USB_OTGISTAT_CLR(v)   (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() & ~(v)))
+#define HW_USB_OTGISTAT_TOG(v)   (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+//@{
+#define BP_USB_OTGISTAT_AVBUSCHG (0U)      //!< Bit position for USB_OTGISTAT_AVBUSCHG.
+#define BM_USB_OTGISTAT_AVBUSCHG (0x01U)   //!< Bit mask for USB_OTGISTAT_AVBUSCHG.
+#define BS_USB_OTGISTAT_AVBUSCHG (1U)      //!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field.
+#define BR_USB_OTGISTAT_AVBUSCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_AVBUSCHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG.
+#define BF_USB_OTGISTAT_AVBUSCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_AVBUSCHG), uint8_t) & BM_USB_OTGISTAT_AVBUSCHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVBUSCHG field to a new value.
+#define BW_USB_OTGISTAT_AVBUSCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_AVBUSCHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+//@{
+#define BP_USB_OTGISTAT_B_SESS_CHG (2U)    //!< Bit position for USB_OTGISTAT_B_SESS_CHG.
+#define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) //!< Bit mask for USB_OTGISTAT_B_SESS_CHG.
+#define BS_USB_OTGISTAT_B_SESS_CHG (1U)    //!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field.
+#define BR_USB_OTGISTAT_B_SESS_CHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_B_SESS_CHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG.
+#define BF_USB_OTGISTAT_B_SESS_CHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_B_SESS_CHG), uint8_t) & BM_USB_OTGISTAT_B_SESS_CHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B_SESS_CHG field to a new value.
+#define BW_USB_OTGISTAT_B_SESS_CHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_B_SESS_CHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+//@{
+#define BP_USB_OTGISTAT_SESSVLDCHG (3U)    //!< Bit position for USB_OTGISTAT_SESSVLDCHG.
+#define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) //!< Bit mask for USB_OTGISTAT_SESSVLDCHG.
+#define BS_USB_OTGISTAT_SESSVLDCHG (1U)    //!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field.
+#define BR_USB_OTGISTAT_SESSVLDCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_SESSVLDCHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG.
+#define BF_USB_OTGISTAT_SESSVLDCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_SESSVLDCHG), uint8_t) & BM_USB_OTGISTAT_SESSVLDCHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SESSVLDCHG field to a new value.
+#define BW_USB_OTGISTAT_SESSVLDCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_SESSVLDCHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+//@{
+#define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) //!< Bit position for USB_OTGISTAT_LINE_STATE_CHG.
+#define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) //!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG.
+#define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) //!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field.
+#define BR_USB_OTGISTAT_LINE_STATE_CHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_LINE_STATE_CHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG.
+#define BF_USB_OTGISTAT_LINE_STATE_CHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_LINE_STATE_CHG), uint8_t) & BM_USB_OTGISTAT_LINE_STATE_CHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINE_STATE_CHG field to a new value.
+#define BW_USB_OTGISTAT_LINE_STATE_CHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_LINE_STATE_CHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+//@{
+#define BP_USB_OTGISTAT_ONEMSEC (6U)       //!< Bit position for USB_OTGISTAT_ONEMSEC.
+#define BM_USB_OTGISTAT_ONEMSEC (0x40U)    //!< Bit mask for USB_OTGISTAT_ONEMSEC.
+#define BS_USB_OTGISTAT_ONEMSEC (1U)       //!< Bit field size in bits for USB_OTGISTAT_ONEMSEC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_ONEMSEC field.
+#define BR_USB_OTGISTAT_ONEMSEC (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_ONEMSEC))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC.
+#define BF_USB_OTGISTAT_ONEMSEC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_ONEMSEC), uint8_t) & BM_USB_OTGISTAT_ONEMSEC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONEMSEC field to a new value.
+#define BW_USB_OTGISTAT_ONEMSEC(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_ONEMSEC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+//@{
+#define BP_USB_OTGISTAT_IDCHG (7U)         //!< Bit position for USB_OTGISTAT_IDCHG.
+#define BM_USB_OTGISTAT_IDCHG (0x80U)      //!< Bit mask for USB_OTGISTAT_IDCHG.
+#define BS_USB_OTGISTAT_IDCHG (1U)         //!< Bit field size in bits for USB_OTGISTAT_IDCHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_IDCHG field.
+#define BR_USB_OTGISTAT_IDCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_IDCHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_IDCHG.
+#define BF_USB_OTGISTAT_IDCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_IDCHG), uint8_t) & BM_USB_OTGISTAT_IDCHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDCHG field to a new value.
+#define BW_USB_OTGISTAT_IDCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_IDCHG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGICR - OTG Interrupt Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+typedef union _hw_usb_otgicr
+{
+    uint8_t U;
+    struct _hw_usb_otgicr_bitfields
+    {
+        uint8_t AVBUSEN : 1;           //!< [0] A VBUS Valid Interrupt Enable
+        uint8_t RESERVED0 : 1;         //!< [1]
+        uint8_t BSESSEN : 1;           //!< [2] B Session END Interrupt Enable
+        uint8_t SESSVLDEN : 1;         //!< [3] Session Valid Interrupt Enable
+        uint8_t RESERVED1 : 1;         //!< [4]
+        uint8_t LINESTATEEN : 1;       //!< [5] Line State Change Interrupt Enable
+        uint8_t ONEMSECEN : 1;         //!< [6] One Millisecond Interrupt Enable
+        uint8_t IDEN : 1;              //!< [7] ID Interrupt Enable
+    } B;
+} hw_usb_otgicr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+//@{
+#define HW_USB_OTGICR_ADDR       (REGS_USB_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGICR            (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR)
+#define HW_USB_OTGICR_RD()       (HW_USB_OTGICR.U)
+#define HW_USB_OTGICR_WR(v)      (HW_USB_OTGICR.U = (v))
+#define HW_USB_OTGICR_SET(v)     (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() |  (v)))
+#define HW_USB_OTGICR_CLR(v)     (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() & ~(v)))
+#define HW_USB_OTGICR_TOG(v)     (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the AVBUSCHG interrupt.
+ * - 1 - Enables the AVBUSCHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_AVBUSEN (0U)         //!< Bit position for USB_OTGICR_AVBUSEN.
+#define BM_USB_OTGICR_AVBUSEN (0x01U)      //!< Bit mask for USB_OTGICR_AVBUSEN.
+#define BS_USB_OTGICR_AVBUSEN (1U)         //!< Bit field size in bits for USB_OTGICR_AVBUSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_AVBUSEN field.
+#define BR_USB_OTGICR_AVBUSEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_AVBUSEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_AVBUSEN.
+#define BF_USB_OTGICR_AVBUSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_AVBUSEN), uint8_t) & BM_USB_OTGICR_AVBUSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVBUSEN field to a new value.
+#define BW_USB_OTGICR_AVBUSEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_AVBUSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disables the B_SESS_CHG interrupt.
+ * - 1 - Enables the B_SESS_CHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_BSESSEN (2U)         //!< Bit position for USB_OTGICR_BSESSEN.
+#define BM_USB_OTGICR_BSESSEN (0x04U)      //!< Bit mask for USB_OTGICR_BSESSEN.
+#define BS_USB_OTGICR_BSESSEN (1U)         //!< Bit field size in bits for USB_OTGICR_BSESSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_BSESSEN field.
+#define BR_USB_OTGICR_BSESSEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_BSESSEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_BSESSEN.
+#define BF_USB_OTGICR_BSESSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_BSESSEN), uint8_t) & BM_USB_OTGICR_BSESSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSESSEN field to a new value.
+#define BW_USB_OTGICR_BSESSEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_BSESSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the SESSVLDCHG interrupt.
+ * - 1 - Enables the SESSVLDCHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_SESSVLDEN (3U)       //!< Bit position for USB_OTGICR_SESSVLDEN.
+#define BM_USB_OTGICR_SESSVLDEN (0x08U)    //!< Bit mask for USB_OTGICR_SESSVLDEN.
+#define BS_USB_OTGICR_SESSVLDEN (1U)       //!< Bit field size in bits for USB_OTGICR_SESSVLDEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_SESSVLDEN field.
+#define BR_USB_OTGICR_SESSVLDEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_SESSVLDEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_SESSVLDEN.
+#define BF_USB_OTGICR_SESSVLDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_SESSVLDEN), uint8_t) & BM_USB_OTGICR_SESSVLDEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SESSVLDEN field to a new value.
+#define BW_USB_OTGICR_SESSVLDEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_SESSVLDEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the LINE_STAT_CHG interrupt.
+ * - 1 - Enables the LINE_STAT_CHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_LINESTATEEN (5U)     //!< Bit position for USB_OTGICR_LINESTATEEN.
+#define BM_USB_OTGICR_LINESTATEEN (0x20U)  //!< Bit mask for USB_OTGICR_LINESTATEEN.
+#define BS_USB_OTGICR_LINESTATEEN (1U)     //!< Bit field size in bits for USB_OTGICR_LINESTATEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_LINESTATEEN field.
+#define BR_USB_OTGICR_LINESTATEEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_LINESTATEEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_LINESTATEEN.
+#define BF_USB_OTGICR_LINESTATEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_LINESTATEEN), uint8_t) & BM_USB_OTGICR_LINESTATEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINESTATEEN field to a new value.
+#define BW_USB_OTGICR_LINESTATEEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_LINESTATEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Diables the 1ms timer interrupt.
+ * - 1 - Enables the 1ms timer interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_ONEMSECEN (6U)       //!< Bit position for USB_OTGICR_ONEMSECEN.
+#define BM_USB_OTGICR_ONEMSECEN (0x40U)    //!< Bit mask for USB_OTGICR_ONEMSECEN.
+#define BS_USB_OTGICR_ONEMSECEN (1U)       //!< Bit field size in bits for USB_OTGICR_ONEMSECEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_ONEMSECEN field.
+#define BR_USB_OTGICR_ONEMSECEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_ONEMSECEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_ONEMSECEN.
+#define BF_USB_OTGICR_ONEMSECEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_ONEMSECEN), uint8_t) & BM_USB_OTGICR_ONEMSECEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONEMSECEN field to a new value.
+#define BW_USB_OTGICR_ONEMSECEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_ONEMSECEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0 - The ID interrupt is disabled
+ * - 1 - The ID interrupt is enabled
+ */
+//@{
+#define BP_USB_OTGICR_IDEN   (7U)          //!< Bit position for USB_OTGICR_IDEN.
+#define BM_USB_OTGICR_IDEN   (0x80U)       //!< Bit mask for USB_OTGICR_IDEN.
+#define BS_USB_OTGICR_IDEN   (1U)          //!< Bit field size in bits for USB_OTGICR_IDEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_IDEN field.
+#define BR_USB_OTGICR_IDEN   (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_IDEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_IDEN.
+#define BF_USB_OTGICR_IDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_IDEN), uint8_t) & BM_USB_OTGICR_IDEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDEN field to a new value.
+#define BW_USB_OTGICR_IDEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_IDEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGSTAT - OTG Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+typedef union _hw_usb_otgstat
+{
+    uint8_t U;
+    struct _hw_usb_otgstat_bitfields
+    {
+        uint8_t AVBUSVLD : 1;          //!< [0] A VBUS Valid
+        uint8_t RESERVED0 : 1;         //!< [1]
+        uint8_t BSESSEND : 1;          //!< [2] B Session End
+        uint8_t SESS_VLD : 1;          //!< [3] Session Valid
+        uint8_t RESERVED1 : 1;         //!< [4]
+        uint8_t LINESTATESTABLE : 1;   //!< [5]
+        uint8_t ONEMSECEN : 1;         //!< [6]
+        uint8_t ID : 1;                //!< [7]
+    } B;
+} hw_usb_otgstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+//@{
+#define HW_USB_OTGSTAT_ADDR      (REGS_USB_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGSTAT           (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR)
+#define HW_USB_OTGSTAT_RD()      (HW_USB_OTGSTAT.U)
+#define HW_USB_OTGSTAT_WR(v)     (HW_USB_OTGSTAT.U = (v))
+#define HW_USB_OTGSTAT_SET(v)    (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() |  (v)))
+#define HW_USB_OTGSTAT_CLR(v)    (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() & ~(v)))
+#define HW_USB_OTGSTAT_TOG(v)    (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+//@{
+#define BP_USB_OTGSTAT_AVBUSVLD (0U)       //!< Bit position for USB_OTGSTAT_AVBUSVLD.
+#define BM_USB_OTGSTAT_AVBUSVLD (0x01U)    //!< Bit mask for USB_OTGSTAT_AVBUSVLD.
+#define BS_USB_OTGSTAT_AVBUSVLD (1U)       //!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field.
+#define BR_USB_OTGSTAT_AVBUSVLD (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_AVBUSVLD))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD.
+#define BF_USB_OTGSTAT_AVBUSVLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_AVBUSVLD), uint8_t) & BM_USB_OTGSTAT_AVBUSVLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVBUSVLD field to a new value.
+#define BW_USB_OTGSTAT_AVBUSVLD(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_AVBUSVLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0 - The VBUS voltage is above the B session end threshold.
+ * - 1 - The VBUS voltage is below the B session end threshold.
+ */
+//@{
+#define BP_USB_OTGSTAT_BSESSEND (2U)       //!< Bit position for USB_OTGSTAT_BSESSEND.
+#define BM_USB_OTGSTAT_BSESSEND (0x04U)    //!< Bit mask for USB_OTGSTAT_BSESSEND.
+#define BS_USB_OTGSTAT_BSESSEND (1U)       //!< Bit field size in bits for USB_OTGSTAT_BSESSEND.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_BSESSEND field.
+#define BR_USB_OTGSTAT_BSESSEND (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_BSESSEND))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_BSESSEND.
+#define BF_USB_OTGSTAT_BSESSEND(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_BSESSEND), uint8_t) & BM_USB_OTGSTAT_BSESSEND)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSESSEND field to a new value.
+#define BW_USB_OTGSTAT_BSESSEND(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_BSESSEND) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0 - The VBUS voltage is below the B session valid threshold
+ * - 1 - The VBUS voltage is above the B session valid threshold.
+ */
+//@{
+#define BP_USB_OTGSTAT_SESS_VLD (3U)       //!< Bit position for USB_OTGSTAT_SESS_VLD.
+#define BM_USB_OTGSTAT_SESS_VLD (0x08U)    //!< Bit mask for USB_OTGSTAT_SESS_VLD.
+#define BS_USB_OTGSTAT_SESS_VLD (1U)       //!< Bit field size in bits for USB_OTGSTAT_SESS_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_SESS_VLD field.
+#define BR_USB_OTGSTAT_SESS_VLD (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_SESS_VLD))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD.
+#define BF_USB_OTGSTAT_SESS_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_SESS_VLD), uint8_t) & BM_USB_OTGSTAT_SESS_VLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SESS_VLD field to a new value.
+#define BW_USB_OTGSTAT_SESS_VLD(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_SESS_VLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+//@{
+#define BP_USB_OTGSTAT_LINESTATESTABLE (5U) //!< Bit position for USB_OTGSTAT_LINESTATESTABLE.
+#define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) //!< Bit mask for USB_OTGSTAT_LINESTATESTABLE.
+#define BS_USB_OTGSTAT_LINESTATESTABLE (1U) //!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field.
+#define BR_USB_OTGSTAT_LINESTATESTABLE (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_LINESTATESTABLE))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE.
+#define BF_USB_OTGSTAT_LINESTATESTABLE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_LINESTATESTABLE), uint8_t) & BM_USB_OTGSTAT_LINESTATESTABLE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINESTATESTABLE field to a new value.
+#define BW_USB_OTGSTAT_LINESTATESTABLE(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_LINESTATESTABLE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+//@{
+#define BP_USB_OTGSTAT_ONEMSECEN (6U)      //!< Bit position for USB_OTGSTAT_ONEMSECEN.
+#define BM_USB_OTGSTAT_ONEMSECEN (0x40U)   //!< Bit mask for USB_OTGSTAT_ONEMSECEN.
+#define BS_USB_OTGSTAT_ONEMSECEN (1U)      //!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field.
+#define BR_USB_OTGSTAT_ONEMSECEN (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ONEMSECEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN.
+#define BF_USB_OTGSTAT_ONEMSECEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_ONEMSECEN), uint8_t) & BM_USB_OTGSTAT_ONEMSECEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONEMSECEN field to a new value.
+#define BW_USB_OTGSTAT_ONEMSECEN(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ONEMSECEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+//@{
+#define BP_USB_OTGSTAT_ID    (7U)          //!< Bit position for USB_OTGSTAT_ID.
+#define BM_USB_OTGSTAT_ID    (0x80U)       //!< Bit mask for USB_OTGSTAT_ID.
+#define BS_USB_OTGSTAT_ID    (1U)          //!< Bit field size in bits for USB_OTGSTAT_ID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_ID field.
+#define BR_USB_OTGSTAT_ID    (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ID))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_ID.
+#define BF_USB_OTGSTAT_ID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_ID), uint8_t) & BM_USB_OTGSTAT_ID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ID field to a new value.
+#define BW_USB_OTGSTAT_ID(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ID) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGCTL - OTG Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+typedef union _hw_usb_otgctl
+{
+    uint8_t U;
+    struct _hw_usb_otgctl_bitfields
+    {
+        uint8_t RESERVED0 : 2;         //!< [1:0]
+        uint8_t OTGEN : 1;             //!< [2] On-The-Go pullup/pulldown resistor enable
+        uint8_t RESERVED1 : 1;         //!< [3]
+        uint8_t DMLOW : 1;             //!< [4] D- Data Line pull-down resistor enable
+        uint8_t DPLOW : 1;             //!< [5] D+ Data Line pull-down resistor enable
+        uint8_t RESERVED2 : 1;         //!< [6]
+        uint8_t DPHIGH : 1;            //!< [7] D+ Data Line pullup resistor enable
+    } B;
+} hw_usb_otgctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+//@{
+#define HW_USB_OTGCTL_ADDR       (REGS_USB_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGCTL            (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR)
+#define HW_USB_OTGCTL_RD()       (HW_USB_OTGCTL.U)
+#define HW_USB_OTGCTL_WR(v)      (HW_USB_OTGCTL.U = (v))
+#define HW_USB_OTGCTL_SET(v)     (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() |  (v)))
+#define HW_USB_OTGCTL_CLR(v)     (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() & ~(v)))
+#define HW_USB_OTGCTL_TOG(v)     (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 1 - The pull-up and pull-down controls in this register are used.
+ */
+//@{
+#define BP_USB_OTGCTL_OTGEN  (2U)          //!< Bit position for USB_OTGCTL_OTGEN.
+#define BM_USB_OTGCTL_OTGEN  (0x04U)       //!< Bit mask for USB_OTGCTL_OTGEN.
+#define BS_USB_OTGCTL_OTGEN  (1U)          //!< Bit field size in bits for USB_OTGCTL_OTGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_OTGEN field.
+#define BR_USB_OTGCTL_OTGEN  (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_OTGEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_OTGEN.
+#define BF_USB_OTGCTL_OTGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_OTGEN), uint8_t) & BM_USB_OTGCTL_OTGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OTGEN field to a new value.
+#define BW_USB_OTGCTL_OTGEN(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_OTGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0 - D- pulldown resistor is not enabled.
+ * - 1 - D- pulldown resistor is enabled.
+ */
+//@{
+#define BP_USB_OTGCTL_DMLOW  (4U)          //!< Bit position for USB_OTGCTL_DMLOW.
+#define BM_USB_OTGCTL_DMLOW  (0x10U)       //!< Bit mask for USB_OTGCTL_DMLOW.
+#define BS_USB_OTGCTL_DMLOW  (1U)          //!< Bit field size in bits for USB_OTGCTL_DMLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_DMLOW field.
+#define BR_USB_OTGCTL_DMLOW  (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DMLOW))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_DMLOW.
+#define BF_USB_OTGCTL_DMLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DMLOW), uint8_t) & BM_USB_OTGCTL_DMLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMLOW field to a new value.
+#define BW_USB_OTGCTL_DMLOW(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DMLOW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0 - D+ pulldown resistor is not enabled.
+ * - 1 - D+ pulldown resistor is enabled.
+ */
+//@{
+#define BP_USB_OTGCTL_DPLOW  (5U)          //!< Bit position for USB_OTGCTL_DPLOW.
+#define BM_USB_OTGCTL_DPLOW  (0x20U)       //!< Bit mask for USB_OTGCTL_DPLOW.
+#define BS_USB_OTGCTL_DPLOW  (1U)          //!< Bit field size in bits for USB_OTGCTL_DPLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_DPLOW field.
+#define BR_USB_OTGCTL_DPLOW  (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPLOW))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_DPLOW.
+#define BF_USB_OTGCTL_DPLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DPLOW), uint8_t) & BM_USB_OTGCTL_DPLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPLOW field to a new value.
+#define BW_USB_OTGCTL_DPLOW(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPLOW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0 - D+ pullup resistor is not enabled
+ * - 1 - D+ pullup resistor is enabled
+ */
+//@{
+#define BP_USB_OTGCTL_DPHIGH (7U)          //!< Bit position for USB_OTGCTL_DPHIGH.
+#define BM_USB_OTGCTL_DPHIGH (0x80U)       //!< Bit mask for USB_OTGCTL_DPHIGH.
+#define BS_USB_OTGCTL_DPHIGH (1U)          //!< Bit field size in bits for USB_OTGCTL_DPHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_DPHIGH field.
+#define BR_USB_OTGCTL_DPHIGH (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPHIGH))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_DPHIGH.
+#define BF_USB_OTGCTL_DPHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DPHIGH), uint8_t) & BM_USB_OTGCTL_DPHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPHIGH field to a new value.
+#define BW_USB_OTGCTL_DPHIGH(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPHIGH) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ISTAT - Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_istat
+{
+    uint8_t U;
+    struct _hw_usb_istat_bitfields
+    {
+        uint8_t USBRST : 1;            //!< [0]
+        uint8_t ERROR : 1;             //!< [1]
+        uint8_t SOFTOK : 1;            //!< [2]
+        uint8_t TOKDNE : 1;            //!< [3]
+        uint8_t SLEEP : 1;             //!< [4]
+        uint8_t RESUME : 1;            //!< [5]
+        uint8_t ATTACH : 1;            //!< [6] Attach Interrupt
+        uint8_t STALL : 1;             //!< [7] Stall Interrupt
+    } B;
+} hw_usb_istat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+//@{
+#define HW_USB_ISTAT_ADDR        (REGS_USB_BASE + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ISTAT             (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR)
+#define HW_USB_ISTAT_RD()        (HW_USB_ISTAT.U)
+#define HW_USB_ISTAT_WR(v)       (HW_USB_ISTAT.U = (v))
+#define HW_USB_ISTAT_SET(v)      (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() |  (v)))
+#define HW_USB_ISTAT_CLR(v)      (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() & ~(v)))
+#define HW_USB_ISTAT_TOG(v)      (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+//@{
+#define BP_USB_ISTAT_USBRST  (0U)          //!< Bit position for USB_ISTAT_USBRST.
+#define BM_USB_ISTAT_USBRST  (0x01U)       //!< Bit mask for USB_ISTAT_USBRST.
+#define BS_USB_ISTAT_USBRST  (1U)          //!< Bit field size in bits for USB_ISTAT_USBRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_USBRST field.
+#define BR_USB_ISTAT_USBRST  (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_USBRST))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_USBRST.
+#define BF_USB_ISTAT_USBRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_USBRST), uint8_t) & BM_USB_ISTAT_USBRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBRST field to a new value.
+#define BW_USB_ISTAT_USBRST(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_USBRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+//@{
+#define BP_USB_ISTAT_ERROR   (1U)          //!< Bit position for USB_ISTAT_ERROR.
+#define BM_USB_ISTAT_ERROR   (0x02U)       //!< Bit mask for USB_ISTAT_ERROR.
+#define BS_USB_ISTAT_ERROR   (1U)          //!< Bit field size in bits for USB_ISTAT_ERROR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_ERROR field.
+#define BR_USB_ISTAT_ERROR   (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ERROR))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_ERROR.
+#define BF_USB_ISTAT_ERROR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_ERROR), uint8_t) & BM_USB_ISTAT_ERROR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERROR field to a new value.
+#define BW_USB_ISTAT_ERROR(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ERROR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+//@{
+#define BP_USB_ISTAT_SOFTOK  (2U)          //!< Bit position for USB_ISTAT_SOFTOK.
+#define BM_USB_ISTAT_SOFTOK  (0x04U)       //!< Bit mask for USB_ISTAT_SOFTOK.
+#define BS_USB_ISTAT_SOFTOK  (1U)          //!< Bit field size in bits for USB_ISTAT_SOFTOK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_SOFTOK field.
+#define BR_USB_ISTAT_SOFTOK  (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SOFTOK))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_SOFTOK.
+#define BF_USB_ISTAT_SOFTOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_SOFTOK), uint8_t) & BM_USB_ISTAT_SOFTOK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFTOK field to a new value.
+#define BW_USB_ISTAT_SOFTOK(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SOFTOK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+//@{
+#define BP_USB_ISTAT_TOKDNE  (3U)          //!< Bit position for USB_ISTAT_TOKDNE.
+#define BM_USB_ISTAT_TOKDNE  (0x08U)       //!< Bit mask for USB_ISTAT_TOKDNE.
+#define BS_USB_ISTAT_TOKDNE  (1U)          //!< Bit field size in bits for USB_ISTAT_TOKDNE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_TOKDNE field.
+#define BR_USB_ISTAT_TOKDNE  (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_TOKDNE))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_TOKDNE.
+#define BF_USB_ISTAT_TOKDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_TOKDNE), uint8_t) & BM_USB_ISTAT_TOKDNE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKDNE field to a new value.
+#define BW_USB_ISTAT_TOKDNE(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_TOKDNE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+//@{
+#define BP_USB_ISTAT_SLEEP   (4U)          //!< Bit position for USB_ISTAT_SLEEP.
+#define BM_USB_ISTAT_SLEEP   (0x10U)       //!< Bit mask for USB_ISTAT_SLEEP.
+#define BS_USB_ISTAT_SLEEP   (1U)          //!< Bit field size in bits for USB_ISTAT_SLEEP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_SLEEP field.
+#define BR_USB_ISTAT_SLEEP   (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SLEEP))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_SLEEP.
+#define BF_USB_ISTAT_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_SLEEP), uint8_t) & BM_USB_ISTAT_SLEEP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLEEP field to a new value.
+#define BW_USB_ISTAT_SLEEP(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SLEEP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+//@{
+#define BP_USB_ISTAT_RESUME  (5U)          //!< Bit position for USB_ISTAT_RESUME.
+#define BM_USB_ISTAT_RESUME  (0x20U)       //!< Bit mask for USB_ISTAT_RESUME.
+#define BS_USB_ISTAT_RESUME  (1U)          //!< Bit field size in bits for USB_ISTAT_RESUME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_RESUME field.
+#define BR_USB_ISTAT_RESUME  (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_RESUME))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_RESUME.
+#define BF_USB_ISTAT_RESUME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_RESUME), uint8_t) & BM_USB_ISTAT_RESUME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESUME field to a new value.
+#define BW_USB_ISTAT_RESUME(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_RESUME) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+//@{
+#define BP_USB_ISTAT_ATTACH  (6U)          //!< Bit position for USB_ISTAT_ATTACH.
+#define BM_USB_ISTAT_ATTACH  (0x40U)       //!< Bit mask for USB_ISTAT_ATTACH.
+#define BS_USB_ISTAT_ATTACH  (1U)          //!< Bit field size in bits for USB_ISTAT_ATTACH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_ATTACH field.
+#define BR_USB_ISTAT_ATTACH  (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ATTACH))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_ATTACH.
+#define BF_USB_ISTAT_ATTACH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_ATTACH), uint8_t) & BM_USB_ISTAT_ATTACH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATTACH field to a new value.
+#define BW_USB_ISTAT_ATTACH(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ATTACH) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+//@{
+#define BP_USB_ISTAT_STALL   (7U)          //!< Bit position for USB_ISTAT_STALL.
+#define BM_USB_ISTAT_STALL   (0x80U)       //!< Bit mask for USB_ISTAT_STALL.
+#define BS_USB_ISTAT_STALL   (1U)          //!< Bit field size in bits for USB_ISTAT_STALL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_STALL field.
+#define BR_USB_ISTAT_STALL   (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_STALL))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_STALL.
+#define BF_USB_ISTAT_STALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_STALL), uint8_t) & BM_USB_ISTAT_STALL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STALL field to a new value.
+#define BW_USB_ISTAT_STALL(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_STALL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_INTEN - Interrupt Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_inten
+{
+    uint8_t U;
+    struct _hw_usb_inten_bitfields
+    {
+        uint8_t USBRSTEN : 1;          //!< [0] USBRST Interrupt Enable
+        uint8_t ERROREN : 1;           //!< [1] ERROR Interrupt Enable
+        uint8_t SOFTOKEN : 1;          //!< [2] SOFTOK Interrupt Enable
+        uint8_t TOKDNEEN : 1;          //!< [3] TOKDNE Interrupt Enable
+        uint8_t SLEEPEN : 1;           //!< [4] SLEEP Interrupt Enable
+        uint8_t RESUMEEN : 1;          //!< [5] RESUME Interrupt Enable
+        uint8_t ATTACHEN : 1;          //!< [6] ATTACH Interrupt Enable
+        uint8_t STALLEN : 1;           //!< [7] STALL Interrupt Enable
+    } B;
+} hw_usb_inten_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+//@{
+#define HW_USB_INTEN_ADDR        (REGS_USB_BASE + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_INTEN             (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR)
+#define HW_USB_INTEN_RD()        (HW_USB_INTEN.U)
+#define HW_USB_INTEN_WR(v)       (HW_USB_INTEN.U = (v))
+#define HW_USB_INTEN_SET(v)      (HW_USB_INTEN_WR(HW_USB_INTEN_RD() |  (v)))
+#define HW_USB_INTEN_CLR(v)      (HW_USB_INTEN_WR(HW_USB_INTEN_RD() & ~(v)))
+#define HW_USB_INTEN_TOG(v)      (HW_USB_INTEN_WR(HW_USB_INTEN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the USBRST interrupt.
+ * - 1 - Enables the USBRST interrupt.
+ */
+//@{
+#define BP_USB_INTEN_USBRSTEN (0U)         //!< Bit position for USB_INTEN_USBRSTEN.
+#define BM_USB_INTEN_USBRSTEN (0x01U)      //!< Bit mask for USB_INTEN_USBRSTEN.
+#define BS_USB_INTEN_USBRSTEN (1U)         //!< Bit field size in bits for USB_INTEN_USBRSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_USBRSTEN field.
+#define BR_USB_INTEN_USBRSTEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_USBRSTEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_USBRSTEN.
+#define BF_USB_INTEN_USBRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_USBRSTEN), uint8_t) & BM_USB_INTEN_USBRSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBRSTEN field to a new value.
+#define BW_USB_INTEN_USBRSTEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_USBRSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0 - Disables the ERROR interrupt.
+ * - 1 - Enables the ERROR interrupt.
+ */
+//@{
+#define BP_USB_INTEN_ERROREN (1U)          //!< Bit position for USB_INTEN_ERROREN.
+#define BM_USB_INTEN_ERROREN (0x02U)       //!< Bit mask for USB_INTEN_ERROREN.
+#define BS_USB_INTEN_ERROREN (1U)          //!< Bit field size in bits for USB_INTEN_ERROREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_ERROREN field.
+#define BR_USB_INTEN_ERROREN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ERROREN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_ERROREN.
+#define BF_USB_INTEN_ERROREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_ERROREN), uint8_t) & BM_USB_INTEN_ERROREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERROREN field to a new value.
+#define BW_USB_INTEN_ERROREN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ERROREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disbles the SOFTOK interrupt.
+ * - 1 - Enables the SOFTOK interrupt.
+ */
+//@{
+#define BP_USB_INTEN_SOFTOKEN (2U)         //!< Bit position for USB_INTEN_SOFTOKEN.
+#define BM_USB_INTEN_SOFTOKEN (0x04U)      //!< Bit mask for USB_INTEN_SOFTOKEN.
+#define BS_USB_INTEN_SOFTOKEN (1U)         //!< Bit field size in bits for USB_INTEN_SOFTOKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_SOFTOKEN field.
+#define BR_USB_INTEN_SOFTOKEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SOFTOKEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_SOFTOKEN.
+#define BF_USB_INTEN_SOFTOKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_SOFTOKEN), uint8_t) & BM_USB_INTEN_SOFTOKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFTOKEN field to a new value.
+#define BW_USB_INTEN_SOFTOKEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SOFTOKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the TOKDNE interrupt.
+ * - 1 - Enables the TOKDNE interrupt.
+ */
+//@{
+#define BP_USB_INTEN_TOKDNEEN (3U)         //!< Bit position for USB_INTEN_TOKDNEEN.
+#define BM_USB_INTEN_TOKDNEEN (0x08U)      //!< Bit mask for USB_INTEN_TOKDNEEN.
+#define BS_USB_INTEN_TOKDNEEN (1U)         //!< Bit field size in bits for USB_INTEN_TOKDNEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_TOKDNEEN field.
+#define BR_USB_INTEN_TOKDNEEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_TOKDNEEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_TOKDNEEN.
+#define BF_USB_INTEN_TOKDNEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_TOKDNEEN), uint8_t) & BM_USB_INTEN_TOKDNEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKDNEEN field to a new value.
+#define BW_USB_INTEN_TOKDNEEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_TOKDNEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disables the SLEEP interrupt.
+ * - 1 - Enables the SLEEP interrupt.
+ */
+//@{
+#define BP_USB_INTEN_SLEEPEN (4U)          //!< Bit position for USB_INTEN_SLEEPEN.
+#define BM_USB_INTEN_SLEEPEN (0x10U)       //!< Bit mask for USB_INTEN_SLEEPEN.
+#define BS_USB_INTEN_SLEEPEN (1U)          //!< Bit field size in bits for USB_INTEN_SLEEPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_SLEEPEN field.
+#define BR_USB_INTEN_SLEEPEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SLEEPEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_SLEEPEN.
+#define BF_USB_INTEN_SLEEPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_SLEEPEN), uint8_t) & BM_USB_INTEN_SLEEPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLEEPEN field to a new value.
+#define BW_USB_INTEN_SLEEPEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SLEEPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the RESUME interrupt.
+ * - 1 - Enables the RESUME interrupt.
+ */
+//@{
+#define BP_USB_INTEN_RESUMEEN (5U)         //!< Bit position for USB_INTEN_RESUMEEN.
+#define BM_USB_INTEN_RESUMEEN (0x20U)      //!< Bit mask for USB_INTEN_RESUMEEN.
+#define BS_USB_INTEN_RESUMEEN (1U)         //!< Bit field size in bits for USB_INTEN_RESUMEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_RESUMEEN field.
+#define BR_USB_INTEN_RESUMEEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_RESUMEEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_RESUMEEN.
+#define BF_USB_INTEN_RESUMEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_RESUMEEN), uint8_t) & BM_USB_INTEN_RESUMEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESUMEEN field to a new value.
+#define BW_USB_INTEN_RESUMEEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_RESUMEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Disables the ATTACH interrupt.
+ * - 1 - Enables the ATTACH interrupt.
+ */
+//@{
+#define BP_USB_INTEN_ATTACHEN (6U)         //!< Bit position for USB_INTEN_ATTACHEN.
+#define BM_USB_INTEN_ATTACHEN (0x40U)      //!< Bit mask for USB_INTEN_ATTACHEN.
+#define BS_USB_INTEN_ATTACHEN (1U)         //!< Bit field size in bits for USB_INTEN_ATTACHEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_ATTACHEN field.
+#define BR_USB_INTEN_ATTACHEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ATTACHEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_ATTACHEN.
+#define BF_USB_INTEN_ATTACHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_ATTACHEN), uint8_t) & BM_USB_INTEN_ATTACHEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATTACHEN field to a new value.
+#define BW_USB_INTEN_ATTACHEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ATTACHEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Diasbles the STALL interrupt.
+ * - 1 - Enables the STALL interrupt.
+ */
+//@{
+#define BP_USB_INTEN_STALLEN (7U)          //!< Bit position for USB_INTEN_STALLEN.
+#define BM_USB_INTEN_STALLEN (0x80U)       //!< Bit mask for USB_INTEN_STALLEN.
+#define BS_USB_INTEN_STALLEN (1U)          //!< Bit field size in bits for USB_INTEN_STALLEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_STALLEN field.
+#define BR_USB_INTEN_STALLEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_STALLEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_STALLEN.
+#define BF_USB_INTEN_STALLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_STALLEN), uint8_t) & BM_USB_INTEN_STALLEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STALLEN field to a new value.
+#define BW_USB_INTEN_STALLEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_STALLEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ERRSTAT - Error Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_errstat
+{
+    uint8_t U;
+    struct _hw_usb_errstat_bitfields
+    {
+        uint8_t PIDERR : 1;            //!< [0]
+        uint8_t CRC5EOF : 1;           //!< [1]
+        uint8_t CRC16 : 1;             //!< [2]
+        uint8_t DFN8 : 1;              //!< [3]
+        uint8_t BTOERR : 1;            //!< [4]
+        uint8_t DMAERR : 1;            //!< [5]
+        uint8_t RESERVED0 : 1;         //!< [6]
+        uint8_t BTSERR : 1;            //!< [7]
+    } B;
+} hw_usb_errstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+//@{
+#define HW_USB_ERRSTAT_ADDR      (REGS_USB_BASE + 0x88U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ERRSTAT           (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR)
+#define HW_USB_ERRSTAT_RD()      (HW_USB_ERRSTAT.U)
+#define HW_USB_ERRSTAT_WR(v)     (HW_USB_ERRSTAT.U = (v))
+#define HW_USB_ERRSTAT_SET(v)    (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() |  (v)))
+#define HW_USB_ERRSTAT_CLR(v)    (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() & ~(v)))
+#define HW_USB_ERRSTAT_TOG(v)    (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+//@{
+#define BP_USB_ERRSTAT_PIDERR (0U)         //!< Bit position for USB_ERRSTAT_PIDERR.
+#define BM_USB_ERRSTAT_PIDERR (0x01U)      //!< Bit mask for USB_ERRSTAT_PIDERR.
+#define BS_USB_ERRSTAT_PIDERR (1U)         //!< Bit field size in bits for USB_ERRSTAT_PIDERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_PIDERR field.
+#define BR_USB_ERRSTAT_PIDERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_PIDERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_PIDERR.
+#define BF_USB_ERRSTAT_PIDERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_PIDERR), uint8_t) & BM_USB_ERRSTAT_PIDERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIDERR field to a new value.
+#define BW_USB_ERRSTAT_PIDERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_PIDERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+//@{
+#define BP_USB_ERRSTAT_CRC5EOF (1U)        //!< Bit position for USB_ERRSTAT_CRC5EOF.
+#define BM_USB_ERRSTAT_CRC5EOF (0x02U)     //!< Bit mask for USB_ERRSTAT_CRC5EOF.
+#define BS_USB_ERRSTAT_CRC5EOF (1U)        //!< Bit field size in bits for USB_ERRSTAT_CRC5EOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_CRC5EOF field.
+#define BR_USB_ERRSTAT_CRC5EOF (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC5EOF))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF.
+#define BF_USB_ERRSTAT_CRC5EOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_CRC5EOF), uint8_t) & BM_USB_ERRSTAT_CRC5EOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC5EOF field to a new value.
+#define BW_USB_ERRSTAT_CRC5EOF(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC5EOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+//@{
+#define BP_USB_ERRSTAT_CRC16 (2U)          //!< Bit position for USB_ERRSTAT_CRC16.
+#define BM_USB_ERRSTAT_CRC16 (0x04U)       //!< Bit mask for USB_ERRSTAT_CRC16.
+#define BS_USB_ERRSTAT_CRC16 (1U)          //!< Bit field size in bits for USB_ERRSTAT_CRC16.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_CRC16 field.
+#define BR_USB_ERRSTAT_CRC16 (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC16))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_CRC16.
+#define BF_USB_ERRSTAT_CRC16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_CRC16), uint8_t) & BM_USB_ERRSTAT_CRC16)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC16 field to a new value.
+#define BW_USB_ERRSTAT_CRC16(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC16) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+//@{
+#define BP_USB_ERRSTAT_DFN8  (3U)          //!< Bit position for USB_ERRSTAT_DFN8.
+#define BM_USB_ERRSTAT_DFN8  (0x08U)       //!< Bit mask for USB_ERRSTAT_DFN8.
+#define BS_USB_ERRSTAT_DFN8  (1U)          //!< Bit field size in bits for USB_ERRSTAT_DFN8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_DFN8 field.
+#define BR_USB_ERRSTAT_DFN8  (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DFN8))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_DFN8.
+#define BF_USB_ERRSTAT_DFN8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_DFN8), uint8_t) & BM_USB_ERRSTAT_DFN8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DFN8 field to a new value.
+#define BW_USB_ERRSTAT_DFN8(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DFN8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+//@{
+#define BP_USB_ERRSTAT_BTOERR (4U)         //!< Bit position for USB_ERRSTAT_BTOERR.
+#define BM_USB_ERRSTAT_BTOERR (0x10U)      //!< Bit mask for USB_ERRSTAT_BTOERR.
+#define BS_USB_ERRSTAT_BTOERR (1U)         //!< Bit field size in bits for USB_ERRSTAT_BTOERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_BTOERR field.
+#define BR_USB_ERRSTAT_BTOERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTOERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_BTOERR.
+#define BF_USB_ERRSTAT_BTOERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_BTOERR), uint8_t) & BM_USB_ERRSTAT_BTOERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTOERR field to a new value.
+#define BW_USB_ERRSTAT_BTOERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTOERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+//@{
+#define BP_USB_ERRSTAT_DMAERR (5U)         //!< Bit position for USB_ERRSTAT_DMAERR.
+#define BM_USB_ERRSTAT_DMAERR (0x20U)      //!< Bit mask for USB_ERRSTAT_DMAERR.
+#define BS_USB_ERRSTAT_DMAERR (1U)         //!< Bit field size in bits for USB_ERRSTAT_DMAERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_DMAERR field.
+#define BR_USB_ERRSTAT_DMAERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DMAERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_DMAERR.
+#define BF_USB_ERRSTAT_DMAERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_DMAERR), uint8_t) & BM_USB_ERRSTAT_DMAERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAERR field to a new value.
+#define BW_USB_ERRSTAT_DMAERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DMAERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+//@{
+#define BP_USB_ERRSTAT_BTSERR (7U)         //!< Bit position for USB_ERRSTAT_BTSERR.
+#define BM_USB_ERRSTAT_BTSERR (0x80U)      //!< Bit mask for USB_ERRSTAT_BTSERR.
+#define BS_USB_ERRSTAT_BTSERR (1U)         //!< Bit field size in bits for USB_ERRSTAT_BTSERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_BTSERR field.
+#define BR_USB_ERRSTAT_BTSERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTSERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_BTSERR.
+#define BF_USB_ERRSTAT_BTSERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_BTSERR), uint8_t) & BM_USB_ERRSTAT_BTSERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTSERR field to a new value.
+#define BW_USB_ERRSTAT_BTSERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTSERR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ERREN - Error Interrupt Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_erren
+{
+    uint8_t U;
+    struct _hw_usb_erren_bitfields
+    {
+        uint8_t PIDERREN : 1;          //!< [0] PIDERR Interrupt Enable
+        uint8_t CRC5EOFEN : 1;         //!< [1] CRC5/EOF Interrupt Enable
+        uint8_t CRC16EN : 1;           //!< [2] CRC16 Interrupt Enable
+        uint8_t DFN8EN : 1;            //!< [3] DFN8 Interrupt Enable
+        uint8_t BTOERREN : 1;          //!< [4] BTOERR Interrupt Enable
+        uint8_t DMAERREN : 1;          //!< [5] DMAERR Interrupt Enable
+        uint8_t RESERVED0 : 1;         //!< [6]
+        uint8_t BTSERREN : 1;          //!< [7] BTSERR Interrupt Enable
+    } B;
+} hw_usb_erren_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+//@{
+#define HW_USB_ERREN_ADDR        (REGS_USB_BASE + 0x8CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ERREN             (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR)
+#define HW_USB_ERREN_RD()        (HW_USB_ERREN.U)
+#define HW_USB_ERREN_WR(v)       (HW_USB_ERREN.U = (v))
+#define HW_USB_ERREN_SET(v)      (HW_USB_ERREN_WR(HW_USB_ERREN_RD() |  (v)))
+#define HW_USB_ERREN_CLR(v)      (HW_USB_ERREN_WR(HW_USB_ERREN_RD() & ~(v)))
+#define HW_USB_ERREN_TOG(v)      (HW_USB_ERREN_WR(HW_USB_ERREN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the PIDERR interrupt.
+ * - 1 - Enters the PIDERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_PIDERREN (0U)         //!< Bit position for USB_ERREN_PIDERREN.
+#define BM_USB_ERREN_PIDERREN (0x01U)      //!< Bit mask for USB_ERREN_PIDERREN.
+#define BS_USB_ERREN_PIDERREN (1U)         //!< Bit field size in bits for USB_ERREN_PIDERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_PIDERREN field.
+#define BR_USB_ERREN_PIDERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_PIDERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_PIDERREN.
+#define BF_USB_ERREN_PIDERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_PIDERREN), uint8_t) & BM_USB_ERREN_PIDERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIDERREN field to a new value.
+#define BW_USB_ERREN_PIDERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_PIDERREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Disables the CRC5/EOF interrupt.
+ * - 1 - Enables the CRC5/EOF interrupt.
+ */
+//@{
+#define BP_USB_ERREN_CRC5EOFEN (1U)        //!< Bit position for USB_ERREN_CRC5EOFEN.
+#define BM_USB_ERREN_CRC5EOFEN (0x02U)     //!< Bit mask for USB_ERREN_CRC5EOFEN.
+#define BS_USB_ERREN_CRC5EOFEN (1U)        //!< Bit field size in bits for USB_ERREN_CRC5EOFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_CRC5EOFEN field.
+#define BR_USB_ERREN_CRC5EOFEN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC5EOFEN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_CRC5EOFEN.
+#define BF_USB_ERREN_CRC5EOFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_CRC5EOFEN), uint8_t) & BM_USB_ERREN_CRC5EOFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC5EOFEN field to a new value.
+#define BW_USB_ERREN_CRC5EOFEN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC5EOFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disables the CRC16 interrupt.
+ * - 1 - Enables the CRC16 interrupt.
+ */
+//@{
+#define BP_USB_ERREN_CRC16EN (2U)          //!< Bit position for USB_ERREN_CRC16EN.
+#define BM_USB_ERREN_CRC16EN (0x04U)       //!< Bit mask for USB_ERREN_CRC16EN.
+#define BS_USB_ERREN_CRC16EN (1U)          //!< Bit field size in bits for USB_ERREN_CRC16EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_CRC16EN field.
+#define BR_USB_ERREN_CRC16EN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC16EN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_CRC16EN.
+#define BF_USB_ERREN_CRC16EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_CRC16EN), uint8_t) & BM_USB_ERREN_CRC16EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC16EN field to a new value.
+#define BW_USB_ERREN_CRC16EN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC16EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the DFN8 interrupt.
+ * - 1 - Enables the DFN8 interrupt.
+ */
+//@{
+#define BP_USB_ERREN_DFN8EN  (3U)          //!< Bit position for USB_ERREN_DFN8EN.
+#define BM_USB_ERREN_DFN8EN  (0x08U)       //!< Bit mask for USB_ERREN_DFN8EN.
+#define BS_USB_ERREN_DFN8EN  (1U)          //!< Bit field size in bits for USB_ERREN_DFN8EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_DFN8EN field.
+#define BR_USB_ERREN_DFN8EN  (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DFN8EN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_DFN8EN.
+#define BF_USB_ERREN_DFN8EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_DFN8EN), uint8_t) & BM_USB_ERREN_DFN8EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DFN8EN field to a new value.
+#define BW_USB_ERREN_DFN8EN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DFN8EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disables the BTOERR interrupt.
+ * - 1 - Enables the BTOERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_BTOERREN (4U)         //!< Bit position for USB_ERREN_BTOERREN.
+#define BM_USB_ERREN_BTOERREN (0x10U)      //!< Bit mask for USB_ERREN_BTOERREN.
+#define BS_USB_ERREN_BTOERREN (1U)         //!< Bit field size in bits for USB_ERREN_BTOERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_BTOERREN field.
+#define BR_USB_ERREN_BTOERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTOERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_BTOERREN.
+#define BF_USB_ERREN_BTOERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_BTOERREN), uint8_t) & BM_USB_ERREN_BTOERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTOERREN field to a new value.
+#define BW_USB_ERREN_BTOERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTOERREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the DMAERR interrupt.
+ * - 1 - Enables the DMAERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_DMAERREN (5U)         //!< Bit position for USB_ERREN_DMAERREN.
+#define BM_USB_ERREN_DMAERREN (0x20U)      //!< Bit mask for USB_ERREN_DMAERREN.
+#define BS_USB_ERREN_DMAERREN (1U)         //!< Bit field size in bits for USB_ERREN_DMAERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_DMAERREN field.
+#define BR_USB_ERREN_DMAERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DMAERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_DMAERREN.
+#define BF_USB_ERREN_DMAERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_DMAERREN), uint8_t) & BM_USB_ERREN_DMAERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAERREN field to a new value.
+#define BW_USB_ERREN_DMAERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DMAERREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0 - Disables the BTSERR interrupt.
+ * - 1 - Enables the BTSERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_BTSERREN (7U)         //!< Bit position for USB_ERREN_BTSERREN.
+#define BM_USB_ERREN_BTSERREN (0x80U)      //!< Bit mask for USB_ERREN_BTSERREN.
+#define BS_USB_ERREN_BTSERREN (1U)         //!< Bit field size in bits for USB_ERREN_BTSERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_BTSERREN field.
+#define BR_USB_ERREN_BTSERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTSERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_BTSERREN.
+#define BF_USB_ERREN_BTSERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_BTSERREN), uint8_t) & BM_USB_ERREN_BTSERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTSERREN field to a new value.
+#define BW_USB_ERREN_BTSERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTSERREN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_STAT - Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+typedef union _hw_usb_stat
+{
+    uint8_t U;
+    struct _hw_usb_stat_bitfields
+    {
+        uint8_t RESERVED0 : 2;         //!< [1:0]
+        uint8_t ODD : 1;               //!< [2]
+        uint8_t TX : 1;                //!< [3] Transmit Indicator
+        uint8_t ENDP : 4;              //!< [7:4]
+    } B;
+} hw_usb_stat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+//@{
+#define HW_USB_STAT_ADDR         (REGS_USB_BASE + 0x90U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_STAT              (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR)
+#define HW_USB_STAT_RD()         (HW_USB_STAT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+//@{
+#define BP_USB_STAT_ODD      (2U)          //!< Bit position for USB_STAT_ODD.
+#define BM_USB_STAT_ODD      (0x04U)       //!< Bit mask for USB_STAT_ODD.
+#define BS_USB_STAT_ODD      (1U)          //!< Bit field size in bits for USB_STAT_ODD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_STAT_ODD field.
+#define BR_USB_STAT_ODD      (BITBAND_ACCESS8(HW_USB_STAT_ADDR, BP_USB_STAT_ODD))
+#endif
+//@}
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0 - The most recent transaction was a receive operation.
+ * - 1 - The most recent transaction was a transmit operation.
+ */
+//@{
+#define BP_USB_STAT_TX       (3U)          //!< Bit position for USB_STAT_TX.
+#define BM_USB_STAT_TX       (0x08U)       //!< Bit mask for USB_STAT_TX.
+#define BS_USB_STAT_TX       (1U)          //!< Bit field size in bits for USB_STAT_TX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_STAT_TX field.
+#define BR_USB_STAT_TX       (BITBAND_ACCESS8(HW_USB_STAT_ADDR, BP_USB_STAT_TX))
+#endif
+//@}
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+//@{
+#define BP_USB_STAT_ENDP     (4U)          //!< Bit position for USB_STAT_ENDP.
+#define BM_USB_STAT_ENDP     (0xF0U)       //!< Bit mask for USB_STAT_ENDP.
+#define BS_USB_STAT_ENDP     (4U)          //!< Bit field size in bits for USB_STAT_ENDP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_STAT_ENDP field.
+#define BR_USB_STAT_ENDP     (HW_USB_STAT.B.ENDP)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CTL - Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+typedef union _hw_usb_ctl
+{
+    uint8_t U;
+    struct _hw_usb_ctl_bitfields
+    {
+        uint8_t USBENSOFEN : 1;        //!< [0] USB Enable
+        uint8_t ODDRST : 1;            //!< [1]
+        uint8_t RESUME : 1;            //!< [2]
+        uint8_t HOSTMODEEN : 1;        //!< [3]
+        uint8_t RESET : 1;             //!< [4]
+        uint8_t TXSUSPENDTOKENBUSY : 1; //!< [5]
+        uint8_t SE0 : 1;               //!< [6] Live USB Single Ended Zero signal
+        uint8_t JSTATE : 1;            //!< [7] Live USB differential receiver JSTATE
+                                       //! signal
+    } B;
+} hw_usb_ctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+//@{
+#define HW_USB_CTL_ADDR          (REGS_USB_BASE + 0x94U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CTL               (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR)
+#define HW_USB_CTL_RD()          (HW_USB_CTL.U)
+#define HW_USB_CTL_WR(v)         (HW_USB_CTL.U = (v))
+#define HW_USB_CTL_SET(v)        (HW_USB_CTL_WR(HW_USB_CTL_RD() |  (v)))
+#define HW_USB_CTL_CLR(v)        (HW_USB_CTL_WR(HW_USB_CTL_RD() & ~(v)))
+#define HW_USB_CTL_TOG(v)        (HW_USB_CTL_WR(HW_USB_CTL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0 - Disables the USB Module.
+ * - 1 - Enables the USB Module.
+ */
+//@{
+#define BP_USB_CTL_USBENSOFEN (0U)         //!< Bit position for USB_CTL_USBENSOFEN.
+#define BM_USB_CTL_USBENSOFEN (0x01U)      //!< Bit mask for USB_CTL_USBENSOFEN.
+#define BS_USB_CTL_USBENSOFEN (1U)         //!< Bit field size in bits for USB_CTL_USBENSOFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_USBENSOFEN field.
+#define BR_USB_CTL_USBENSOFEN (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_USBENSOFEN))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_USBENSOFEN.
+#define BF_USB_CTL_USBENSOFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_USBENSOFEN), uint8_t) & BM_USB_CTL_USBENSOFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBENSOFEN field to a new value.
+#define BW_USB_CTL_USBENSOFEN(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_USBENSOFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+//@{
+#define BP_USB_CTL_ODDRST    (1U)          //!< Bit position for USB_CTL_ODDRST.
+#define BM_USB_CTL_ODDRST    (0x02U)       //!< Bit mask for USB_CTL_ODDRST.
+#define BS_USB_CTL_ODDRST    (1U)          //!< Bit field size in bits for USB_CTL_ODDRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_ODDRST field.
+#define BR_USB_CTL_ODDRST    (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_ODDRST))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_ODDRST.
+#define BF_USB_CTL_ODDRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_ODDRST), uint8_t) & BM_USB_CTL_ODDRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ODDRST field to a new value.
+#define BW_USB_CTL_ODDRST(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_ODDRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+//@{
+#define BP_USB_CTL_RESUME    (2U)          //!< Bit position for USB_CTL_RESUME.
+#define BM_USB_CTL_RESUME    (0x04U)       //!< Bit mask for USB_CTL_RESUME.
+#define BS_USB_CTL_RESUME    (1U)          //!< Bit field size in bits for USB_CTL_RESUME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_RESUME field.
+#define BR_USB_CTL_RESUME    (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESUME))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_RESUME.
+#define BF_USB_CTL_RESUME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_RESUME), uint8_t) & BM_USB_CTL_RESUME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESUME field to a new value.
+#define BW_USB_CTL_RESUME(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESUME) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+//@{
+#define BP_USB_CTL_HOSTMODEEN (3U)         //!< Bit position for USB_CTL_HOSTMODEEN.
+#define BM_USB_CTL_HOSTMODEEN (0x08U)      //!< Bit mask for USB_CTL_HOSTMODEEN.
+#define BS_USB_CTL_HOSTMODEEN (1U)         //!< Bit field size in bits for USB_CTL_HOSTMODEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_HOSTMODEEN field.
+#define BR_USB_CTL_HOSTMODEEN (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_HOSTMODEEN))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_HOSTMODEEN.
+#define BF_USB_CTL_HOSTMODEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_HOSTMODEEN), uint8_t) & BM_USB_CTL_HOSTMODEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOSTMODEEN field to a new value.
+#define BW_USB_CTL_HOSTMODEEN(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_HOSTMODEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+//@{
+#define BP_USB_CTL_RESET     (4U)          //!< Bit position for USB_CTL_RESET.
+#define BM_USB_CTL_RESET     (0x10U)       //!< Bit mask for USB_CTL_RESET.
+#define BS_USB_CTL_RESET     (1U)          //!< Bit field size in bits for USB_CTL_RESET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_RESET field.
+#define BR_USB_CTL_RESET     (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESET))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_RESET.
+#define BF_USB_CTL_RESET(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_RESET), uint8_t) & BM_USB_CTL_RESET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESET field to a new value.
+#define BW_USB_CTL_RESET(v)  (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESET) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+//@{
+#define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) //!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY.
+#define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) //!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY.
+#define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) //!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field.
+#define BR_USB_CTL_TXSUSPENDTOKENBUSY (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_TXSUSPENDTOKENBUSY))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY.
+#define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_TXSUSPENDTOKENBUSY), uint8_t) & BM_USB_CTL_TXSUSPENDTOKENBUSY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXSUSPENDTOKENBUSY field to a new value.
+#define BW_USB_CTL_TXSUSPENDTOKENBUSY(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+//@{
+#define BP_USB_CTL_SE0       (6U)          //!< Bit position for USB_CTL_SE0.
+#define BM_USB_CTL_SE0       (0x40U)       //!< Bit mask for USB_CTL_SE0.
+#define BS_USB_CTL_SE0       (1U)          //!< Bit field size in bits for USB_CTL_SE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_SE0 field.
+#define BR_USB_CTL_SE0       (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_SE0))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_SE0.
+#define BF_USB_CTL_SE0(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_SE0), uint8_t) & BM_USB_CTL_SE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SE0 field to a new value.
+#define BW_USB_CTL_SE0(v)    (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_SE0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+//@{
+#define BP_USB_CTL_JSTATE    (7U)          //!< Bit position for USB_CTL_JSTATE.
+#define BM_USB_CTL_JSTATE    (0x80U)       //!< Bit mask for USB_CTL_JSTATE.
+#define BS_USB_CTL_JSTATE    (1U)          //!< Bit field size in bits for USB_CTL_JSTATE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_JSTATE field.
+#define BR_USB_CTL_JSTATE    (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_JSTATE))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_JSTATE.
+#define BF_USB_CTL_JSTATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_JSTATE), uint8_t) & BM_USB_CTL_JSTATE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the JSTATE field to a new value.
+#define BW_USB_CTL_JSTATE(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_JSTATE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ADDR - Address register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+typedef union _hw_usb_addr
+{
+    uint8_t U;
+    struct _hw_usb_addr_bitfields
+    {
+        uint8_t ADDR : 7;              //!< [6:0] USB Address
+        uint8_t LSEN : 1;              //!< [7] Low Speed Enable bit
+    } B;
+} hw_usb_addr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+//@{
+#define HW_USB_ADDR_ADDR         (REGS_USB_BASE + 0x98U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ADDR              (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR)
+#define HW_USB_ADDR_RD()         (HW_USB_ADDR.U)
+#define HW_USB_ADDR_WR(v)        (HW_USB_ADDR.U = (v))
+#define HW_USB_ADDR_SET(v)       (HW_USB_ADDR_WR(HW_USB_ADDR_RD() |  (v)))
+#define HW_USB_ADDR_CLR(v)       (HW_USB_ADDR_WR(HW_USB_ADDR_RD() & ~(v)))
+#define HW_USB_ADDR_TOG(v)       (HW_USB_ADDR_WR(HW_USB_ADDR_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+//@{
+#define BP_USB_ADDR_ADDR     (0U)          //!< Bit position for USB_ADDR_ADDR.
+#define BM_USB_ADDR_ADDR     (0x7FU)       //!< Bit mask for USB_ADDR_ADDR.
+#define BS_USB_ADDR_ADDR     (7U)          //!< Bit field size in bits for USB_ADDR_ADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDR_ADDR field.
+#define BR_USB_ADDR_ADDR     (HW_USB_ADDR.B.ADDR)
+#endif
+
+//! @brief Format value for bitfield USB_ADDR_ADDR.
+#define BF_USB_ADDR_ADDR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ADDR_ADDR), uint8_t) & BM_USB_ADDR_ADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADDR field to a new value.
+#define BW_USB_ADDR_ADDR(v)  (HW_USB_ADDR_WR((HW_USB_ADDR_RD() & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+//@{
+#define BP_USB_ADDR_LSEN     (7U)          //!< Bit position for USB_ADDR_LSEN.
+#define BM_USB_ADDR_LSEN     (0x80U)       //!< Bit mask for USB_ADDR_LSEN.
+#define BS_USB_ADDR_LSEN     (1U)          //!< Bit field size in bits for USB_ADDR_LSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDR_LSEN field.
+#define BR_USB_ADDR_LSEN     (BITBAND_ACCESS8(HW_USB_ADDR_ADDR, BP_USB_ADDR_LSEN))
+#endif
+
+//! @brief Format value for bitfield USB_ADDR_LSEN.
+#define BF_USB_ADDR_LSEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ADDR_LSEN), uint8_t) & BM_USB_ADDR_LSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LSEN field to a new value.
+#define BW_USB_ADDR_LSEN(v)  (BITBAND_ACCESS8(HW_USB_ADDR_ADDR, BP_USB_ADDR_LSEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_BDTPAGE1 - BDT Page register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+typedef union _hw_usb_bdtpage1
+{
+    uint8_t U;
+    struct _hw_usb_bdtpage1_bitfields
+    {
+        uint8_t RESERVED0 : 1;         //!< [0]
+        uint8_t BDTBA : 7;             //!< [7:1]
+    } B;
+} hw_usb_bdtpage1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+//@{
+#define HW_USB_BDTPAGE1_ADDR     (REGS_USB_BASE + 0x9CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_BDTPAGE1          (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR)
+#define HW_USB_BDTPAGE1_RD()     (HW_USB_BDTPAGE1.U)
+#define HW_USB_BDTPAGE1_WR(v)    (HW_USB_BDTPAGE1.U = (v))
+#define HW_USB_BDTPAGE1_SET(v)   (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() |  (v)))
+#define HW_USB_BDTPAGE1_CLR(v)   (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() & ~(v)))
+#define HW_USB_BDTPAGE1_TOG(v)   (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+//@{
+#define BP_USB_BDTPAGE1_BDTBA (1U)         //!< Bit position for USB_BDTPAGE1_BDTBA.
+#define BM_USB_BDTPAGE1_BDTBA (0xFEU)      //!< Bit mask for USB_BDTPAGE1_BDTBA.
+#define BS_USB_BDTPAGE1_BDTBA (7U)         //!< Bit field size in bits for USB_BDTPAGE1_BDTBA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_BDTPAGE1_BDTBA field.
+#define BR_USB_BDTPAGE1_BDTBA (HW_USB_BDTPAGE1.B.BDTBA)
+#endif
+
+//! @brief Format value for bitfield USB_BDTPAGE1_BDTBA.
+#define BF_USB_BDTPAGE1_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE1_BDTBA), uint8_t) & BM_USB_BDTPAGE1_BDTBA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDTBA field to a new value.
+#define BW_USB_BDTPAGE1_BDTBA(v) (HW_USB_BDTPAGE1_WR((HW_USB_BDTPAGE1_RD() & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_FRMNUML - Frame Number register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+typedef union _hw_usb_frmnuml
+{
+    uint8_t U;
+    struct _hw_usb_frmnuml_bitfields
+    {
+        uint8_t FRM : 8;               //!< [7:0]
+    } B;
+} hw_usb_frmnuml_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+//@{
+#define HW_USB_FRMNUML_ADDR      (REGS_USB_BASE + 0xA0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_FRMNUML           (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR)
+#define HW_USB_FRMNUML_RD()      (HW_USB_FRMNUML.U)
+#define HW_USB_FRMNUML_WR(v)     (HW_USB_FRMNUML.U = (v))
+#define HW_USB_FRMNUML_SET(v)    (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() |  (v)))
+#define HW_USB_FRMNUML_CLR(v)    (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() & ~(v)))
+#define HW_USB_FRMNUML_TOG(v)    (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_FRMNUML bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUML, field FRM[7:0] (RW)
+ *
+ * This 8-bit field and the 3-bit field in the Frame Number Register High are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+//@{
+#define BP_USB_FRMNUML_FRM   (0U)          //!< Bit position for USB_FRMNUML_FRM.
+#define BM_USB_FRMNUML_FRM   (0xFFU)       //!< Bit mask for USB_FRMNUML_FRM.
+#define BS_USB_FRMNUML_FRM   (8U)          //!< Bit field size in bits for USB_FRMNUML_FRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_FRMNUML_FRM field.
+#define BR_USB_FRMNUML_FRM   (HW_USB_FRMNUML.U)
+#endif
+
+//! @brief Format value for bitfield USB_FRMNUML_FRM.
+#define BF_USB_FRMNUML_FRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_FRMNUML_FRM), uint8_t) & BM_USB_FRMNUML_FRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRM field to a new value.
+#define BW_USB_FRMNUML_FRM(v) (HW_USB_FRMNUML_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_FRMNUMH - Frame Number register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+typedef union _hw_usb_frmnumh
+{
+    uint8_t U;
+    struct _hw_usb_frmnumh_bitfields
+    {
+        uint8_t FRM : 3;               //!< [2:0]
+        uint8_t RESERVED0 : 5;         //!< [7:3]
+    } B;
+} hw_usb_frmnumh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+//@{
+#define HW_USB_FRMNUMH_ADDR      (REGS_USB_BASE + 0xA4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_FRMNUMH           (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR)
+#define HW_USB_FRMNUMH_RD()      (HW_USB_FRMNUMH.U)
+#define HW_USB_FRMNUMH_WR(v)     (HW_USB_FRMNUMH.U = (v))
+#define HW_USB_FRMNUMH_SET(v)    (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() |  (v)))
+#define HW_USB_FRMNUMH_CLR(v)    (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() & ~(v)))
+#define HW_USB_FRMNUMH_TOG(v)    (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+//@{
+#define BP_USB_FRMNUMH_FRM   (0U)          //!< Bit position for USB_FRMNUMH_FRM.
+#define BM_USB_FRMNUMH_FRM   (0x07U)       //!< Bit mask for USB_FRMNUMH_FRM.
+#define BS_USB_FRMNUMH_FRM   (3U)          //!< Bit field size in bits for USB_FRMNUMH_FRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_FRMNUMH_FRM field.
+#define BR_USB_FRMNUMH_FRM   (HW_USB_FRMNUMH.B.FRM)
+#endif
+
+//! @brief Format value for bitfield USB_FRMNUMH_FRM.
+#define BF_USB_FRMNUMH_FRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_FRMNUMH_FRM), uint8_t) & BM_USB_FRMNUMH_FRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRM field to a new value.
+#define BW_USB_FRMNUMH_FRM(v) (HW_USB_FRMNUMH_WR((HW_USB_FRMNUMH_RD() & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_TOKEN - Token register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+typedef union _hw_usb_token
+{
+    uint8_t U;
+    struct _hw_usb_token_bitfields
+    {
+        uint8_t TOKENENDPT : 4;        //!< [3:0]
+        uint8_t TOKENPID : 4;          //!< [7:4]
+    } B;
+} hw_usb_token_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+//@{
+#define HW_USB_TOKEN_ADDR        (REGS_USB_BASE + 0xA8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_TOKEN             (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR)
+#define HW_USB_TOKEN_RD()        (HW_USB_TOKEN.U)
+#define HW_USB_TOKEN_WR(v)       (HW_USB_TOKEN.U = (v))
+#define HW_USB_TOKEN_SET(v)      (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() |  (v)))
+#define HW_USB_TOKEN_CLR(v)      (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() & ~(v)))
+#define HW_USB_TOKEN_TOG(v)      (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+//@{
+#define BP_USB_TOKEN_TOKENENDPT (0U)       //!< Bit position for USB_TOKEN_TOKENENDPT.
+#define BM_USB_TOKEN_TOKENENDPT (0x0FU)    //!< Bit mask for USB_TOKEN_TOKENENDPT.
+#define BS_USB_TOKEN_TOKENENDPT (4U)       //!< Bit field size in bits for USB_TOKEN_TOKENENDPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_TOKEN_TOKENENDPT field.
+#define BR_USB_TOKEN_TOKENENDPT (HW_USB_TOKEN.B.TOKENENDPT)
+#endif
+
+//! @brief Format value for bitfield USB_TOKEN_TOKENENDPT.
+#define BF_USB_TOKEN_TOKENENDPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_TOKEN_TOKENENDPT), uint8_t) & BM_USB_TOKEN_TOKENENDPT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKENENDPT field to a new value.
+#define BW_USB_TOKEN_TOKENENDPT(v) (HW_USB_TOKEN_WR((HW_USB_TOKEN_RD() & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+//@{
+#define BP_USB_TOKEN_TOKENPID (4U)         //!< Bit position for USB_TOKEN_TOKENPID.
+#define BM_USB_TOKEN_TOKENPID (0xF0U)      //!< Bit mask for USB_TOKEN_TOKENPID.
+#define BS_USB_TOKEN_TOKENPID (4U)         //!< Bit field size in bits for USB_TOKEN_TOKENPID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_TOKEN_TOKENPID field.
+#define BR_USB_TOKEN_TOKENPID (HW_USB_TOKEN.B.TOKENPID)
+#endif
+
+//! @brief Format value for bitfield USB_TOKEN_TOKENPID.
+#define BF_USB_TOKEN_TOKENPID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_TOKEN_TOKENPID), uint8_t) & BM_USB_TOKEN_TOKENPID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKENPID field to a new value.
+#define BW_USB_TOKEN_TOKENPID(v) (HW_USB_TOKEN_WR((HW_USB_TOKEN_RD() & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_SOFTHLD - SOF Threshold register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+typedef union _hw_usb_softhld
+{
+    uint8_t U;
+    struct _hw_usb_softhld_bitfields
+    {
+        uint8_t CNT : 8;               //!< [7:0]
+    } B;
+} hw_usb_softhld_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+//@{
+#define HW_USB_SOFTHLD_ADDR      (REGS_USB_BASE + 0xACU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_SOFTHLD           (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR)
+#define HW_USB_SOFTHLD_RD()      (HW_USB_SOFTHLD.U)
+#define HW_USB_SOFTHLD_WR(v)     (HW_USB_SOFTHLD.U = (v))
+#define HW_USB_SOFTHLD_SET(v)    (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() |  (v)))
+#define HW_USB_SOFTHLD_CLR(v)    (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() & ~(v)))
+#define HW_USB_SOFTHLD_TOG(v)    (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_SOFTHLD bitfields
+ */
+
+/*!
+ * @name Register USB_SOFTHLD, field CNT[7:0] (RW)
+ *
+ * Represents the SOF count threshold in byte times.
+ */
+//@{
+#define BP_USB_SOFTHLD_CNT   (0U)          //!< Bit position for USB_SOFTHLD_CNT.
+#define BM_USB_SOFTHLD_CNT   (0xFFU)       //!< Bit mask for USB_SOFTHLD_CNT.
+#define BS_USB_SOFTHLD_CNT   (8U)          //!< Bit field size in bits for USB_SOFTHLD_CNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_SOFTHLD_CNT field.
+#define BR_USB_SOFTHLD_CNT   (HW_USB_SOFTHLD.U)
+#endif
+
+//! @brief Format value for bitfield USB_SOFTHLD_CNT.
+#define BF_USB_SOFTHLD_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_SOFTHLD_CNT), uint8_t) & BM_USB_SOFTHLD_CNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNT field to a new value.
+#define BW_USB_SOFTHLD_CNT(v) (HW_USB_SOFTHLD_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_BDTPAGE2 - BDT Page Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+typedef union _hw_usb_bdtpage2
+{
+    uint8_t U;
+    struct _hw_usb_bdtpage2_bitfields
+    {
+        uint8_t BDTBA : 8;             //!< [7:0]
+    } B;
+} hw_usb_bdtpage2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+//@{
+#define HW_USB_BDTPAGE2_ADDR     (REGS_USB_BASE + 0xB0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_BDTPAGE2          (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR)
+#define HW_USB_BDTPAGE2_RD()     (HW_USB_BDTPAGE2.U)
+#define HW_USB_BDTPAGE2_WR(v)    (HW_USB_BDTPAGE2.U = (v))
+#define HW_USB_BDTPAGE2_SET(v)   (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() |  (v)))
+#define HW_USB_BDTPAGE2_CLR(v)   (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() & ~(v)))
+#define HW_USB_BDTPAGE2_TOG(v)   (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_BDTPAGE2 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW)
+ *
+ * Provides address bits 23 through 16 of the BDT base address that defines the
+ * location of Buffer Descriptor Table resides in system memory.
+ */
+//@{
+#define BP_USB_BDTPAGE2_BDTBA (0U)         //!< Bit position for USB_BDTPAGE2_BDTBA.
+#define BM_USB_BDTPAGE2_BDTBA (0xFFU)      //!< Bit mask for USB_BDTPAGE2_BDTBA.
+#define BS_USB_BDTPAGE2_BDTBA (8U)         //!< Bit field size in bits for USB_BDTPAGE2_BDTBA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_BDTPAGE2_BDTBA field.
+#define BR_USB_BDTPAGE2_BDTBA (HW_USB_BDTPAGE2.U)
+#endif
+
+//! @brief Format value for bitfield USB_BDTPAGE2_BDTBA.
+#define BF_USB_BDTPAGE2_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE2_BDTBA), uint8_t) & BM_USB_BDTPAGE2_BDTBA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDTBA field to a new value.
+#define BW_USB_BDTPAGE2_BDTBA(v) (HW_USB_BDTPAGE2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_BDTPAGE3 - BDT Page Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+typedef union _hw_usb_bdtpage3
+{
+    uint8_t U;
+    struct _hw_usb_bdtpage3_bitfields
+    {
+        uint8_t BDTBA : 8;             //!< [7:0]
+    } B;
+} hw_usb_bdtpage3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+//@{
+#define HW_USB_BDTPAGE3_ADDR     (REGS_USB_BASE + 0xB4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_BDTPAGE3          (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR)
+#define HW_USB_BDTPAGE3_RD()     (HW_USB_BDTPAGE3.U)
+#define HW_USB_BDTPAGE3_WR(v)    (HW_USB_BDTPAGE3.U = (v))
+#define HW_USB_BDTPAGE3_SET(v)   (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() |  (v)))
+#define HW_USB_BDTPAGE3_CLR(v)   (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() & ~(v)))
+#define HW_USB_BDTPAGE3_TOG(v)   (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_BDTPAGE3 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW)
+ *
+ * Provides address bits 31 through 24 of the BDT base address that defines the
+ * location of Buffer Descriptor Table resides in system memory.
+ */
+//@{
+#define BP_USB_BDTPAGE3_BDTBA (0U)         //!< Bit position for USB_BDTPAGE3_BDTBA.
+#define BM_USB_BDTPAGE3_BDTBA (0xFFU)      //!< Bit mask for USB_BDTPAGE3_BDTBA.
+#define BS_USB_BDTPAGE3_BDTBA (8U)         //!< Bit field size in bits for USB_BDTPAGE3_BDTBA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_BDTPAGE3_BDTBA field.
+#define BR_USB_BDTPAGE3_BDTBA (HW_USB_BDTPAGE3.U)
+#endif
+
+//! @brief Format value for bitfield USB_BDTPAGE3_BDTBA.
+#define BF_USB_BDTPAGE3_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE3_BDTBA), uint8_t) & BM_USB_BDTPAGE3_BDTBA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDTBA field to a new value.
+#define BW_USB_BDTPAGE3_BDTBA(v) (HW_USB_BDTPAGE3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ENDPTn - Endpoint Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ENDPTn - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+typedef union _hw_usb_endptn
+{
+    uint8_t U;
+    struct _hw_usb_endptn_bitfields
+    {
+        uint8_t EPHSHK : 1;            //!< [0]
+        uint8_t EPSTALL : 1;           //!< [1]
+        uint8_t EPTXEN : 1;            //!< [2]
+        uint8_t EPRXEN : 1;            //!< [3]
+        uint8_t EPCTLDIS : 1;          //!< [4]
+        uint8_t RESERVED0 : 1;         //!< [5]
+        uint8_t RETRYDIS : 1;          //!< [6]
+        uint8_t HOSTWOHUB : 1;         //!< [7]
+    } B;
+} hw_usb_endptn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ENDPTn register
+ */
+//@{
+#define HW_USB_ENDPTn_COUNT (16U)
+
+#define HW_USB_ENDPTn_ADDR(n)    (REGS_USB_BASE + 0xC0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ENDPTn(n)         (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(n))
+#define HW_USB_ENDPTn_RD(n)      (HW_USB_ENDPTn(n).U)
+#define HW_USB_ENDPTn_WR(n, v)   (HW_USB_ENDPTn(n).U = (v))
+#define HW_USB_ENDPTn_SET(n, v)  (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) |  (v)))
+#define HW_USB_ENDPTn_CLR(n, v)  (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) & ~(v)))
+#define HW_USB_ENDPTn_TOG(n, v)  (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ENDPTn bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPTn, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+//@{
+#define BP_USB_ENDPTn_EPHSHK (0U)          //!< Bit position for USB_ENDPTn_EPHSHK.
+#define BM_USB_ENDPTn_EPHSHK (0x01U)       //!< Bit mask for USB_ENDPTn_EPHSHK.
+#define BS_USB_ENDPTn_EPHSHK (1U)          //!< Bit field size in bits for USB_ENDPTn_EPHSHK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPHSHK field.
+#define BR_USB_ENDPTn_EPHSHK(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPHSHK))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPHSHK.
+#define BF_USB_ENDPTn_EPHSHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPHSHK), uint8_t) & BM_USB_ENDPTn_EPHSHK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPHSHK field to a new value.
+#define BW_USB_ENDPTn_EPHSHK(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPHSHK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+//@{
+#define BP_USB_ENDPTn_EPSTALL (1U)         //!< Bit position for USB_ENDPTn_EPSTALL.
+#define BM_USB_ENDPTn_EPSTALL (0x02U)      //!< Bit mask for USB_ENDPTn_EPSTALL.
+#define BS_USB_ENDPTn_EPSTALL (1U)         //!< Bit field size in bits for USB_ENDPTn_EPSTALL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPSTALL field.
+#define BR_USB_ENDPTn_EPSTALL(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPSTALL))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPSTALL.
+#define BF_USB_ENDPTn_EPSTALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPSTALL), uint8_t) & BM_USB_ENDPTn_EPSTALL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPSTALL field to a new value.
+#define BW_USB_ENDPTn_EPSTALL(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPSTALL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+//@{
+#define BP_USB_ENDPTn_EPTXEN (2U)          //!< Bit position for USB_ENDPTn_EPTXEN.
+#define BM_USB_ENDPTn_EPTXEN (0x04U)       //!< Bit mask for USB_ENDPTn_EPTXEN.
+#define BS_USB_ENDPTn_EPTXEN (1U)          //!< Bit field size in bits for USB_ENDPTn_EPTXEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPTXEN field.
+#define BR_USB_ENDPTn_EPTXEN(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPTXEN))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPTXEN.
+#define BF_USB_ENDPTn_EPTXEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPTXEN), uint8_t) & BM_USB_ENDPTn_EPTXEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPTXEN field to a new value.
+#define BW_USB_ENDPTn_EPTXEN(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPTXEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+//@{
+#define BP_USB_ENDPTn_EPRXEN (3U)          //!< Bit position for USB_ENDPTn_EPRXEN.
+#define BM_USB_ENDPTn_EPRXEN (0x08U)       //!< Bit mask for USB_ENDPTn_EPRXEN.
+#define BS_USB_ENDPTn_EPRXEN (1U)          //!< Bit field size in bits for USB_ENDPTn_EPRXEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPRXEN field.
+#define BR_USB_ENDPTn_EPRXEN(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPRXEN))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPRXEN.
+#define BF_USB_ENDPTn_EPRXEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPRXEN), uint8_t) & BM_USB_ENDPTn_EPRXEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPRXEN field to a new value.
+#define BW_USB_ENDPTn_EPRXEN(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPRXEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+//@{
+#define BP_USB_ENDPTn_EPCTLDIS (4U)        //!< Bit position for USB_ENDPTn_EPCTLDIS.
+#define BM_USB_ENDPTn_EPCTLDIS (0x10U)     //!< Bit mask for USB_ENDPTn_EPCTLDIS.
+#define BS_USB_ENDPTn_EPCTLDIS (1U)        //!< Bit field size in bits for USB_ENDPTn_EPCTLDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPCTLDIS field.
+#define BR_USB_ENDPTn_EPCTLDIS(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPCTLDIS))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS.
+#define BF_USB_ENDPTn_EPCTLDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPCTLDIS), uint8_t) & BM_USB_ENDPTn_EPCTLDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPCTLDIS field to a new value.
+#define BW_USB_ENDPTn_EPCTLDIS(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPCTLDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+//@{
+#define BP_USB_ENDPTn_RETRYDIS (6U)        //!< Bit position for USB_ENDPTn_RETRYDIS.
+#define BM_USB_ENDPTn_RETRYDIS (0x40U)     //!< Bit mask for USB_ENDPTn_RETRYDIS.
+#define BS_USB_ENDPTn_RETRYDIS (1U)        //!< Bit field size in bits for USB_ENDPTn_RETRYDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_RETRYDIS field.
+#define BR_USB_ENDPTn_RETRYDIS(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_RETRYDIS))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_RETRYDIS.
+#define BF_USB_ENDPTn_RETRYDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_RETRYDIS), uint8_t) & BM_USB_ENDPTn_RETRYDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RETRYDIS field to a new value.
+#define BW_USB_ENDPTn_RETRYDIS(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_RETRYDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+//@{
+#define BP_USB_ENDPTn_HOSTWOHUB (7U)       //!< Bit position for USB_ENDPTn_HOSTWOHUB.
+#define BM_USB_ENDPTn_HOSTWOHUB (0x80U)    //!< Bit mask for USB_ENDPTn_HOSTWOHUB.
+#define BS_USB_ENDPTn_HOSTWOHUB (1U)       //!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field.
+#define BR_USB_ENDPTn_HOSTWOHUB(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_HOSTWOHUB))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB.
+#define BF_USB_ENDPTn_HOSTWOHUB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_HOSTWOHUB), uint8_t) & BM_USB_ENDPTn_HOSTWOHUB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOSTWOHUB field to a new value.
+#define BW_USB_ENDPTn_HOSTWOHUB(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_HOSTWOHUB) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_USBCTRL - USB Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+typedef union _hw_usb_usbctrl
+{
+    uint8_t U;
+    struct _hw_usb_usbctrl_bitfields
+    {
+        uint8_t RESERVED0 : 6;         //!< [5:0]
+        uint8_t PDE : 1;               //!< [6]
+        uint8_t SUSP : 1;              //!< [7]
+    } B;
+} hw_usb_usbctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+//@{
+#define HW_USB_USBCTRL_ADDR      (REGS_USB_BASE + 0x100U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_USBCTRL           (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR)
+#define HW_USB_USBCTRL_RD()      (HW_USB_USBCTRL.U)
+#define HW_USB_USBCTRL_WR(v)     (HW_USB_USBCTRL.U = (v))
+#define HW_USB_USBCTRL_SET(v)    (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() |  (v)))
+#define HW_USB_USBCTRL_CLR(v)    (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() & ~(v)))
+#define HW_USB_USBCTRL_TOG(v)    (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0 - Weak pulldowns are disabled on D+ and D-.
+ * - 1 - Weak pulldowns are enabled on D+ and D-.
+ */
+//@{
+#define BP_USB_USBCTRL_PDE   (6U)          //!< Bit position for USB_USBCTRL_PDE.
+#define BM_USB_USBCTRL_PDE   (0x40U)       //!< Bit mask for USB_USBCTRL_PDE.
+#define BS_USB_USBCTRL_PDE   (1U)          //!< Bit field size in bits for USB_USBCTRL_PDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBCTRL_PDE field.
+#define BR_USB_USBCTRL_PDE   (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_PDE))
+#endif
+
+//! @brief Format value for bitfield USB_USBCTRL_PDE.
+#define BF_USB_USBCTRL_PDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBCTRL_PDE), uint8_t) & BM_USB_USBCTRL_PDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDE field to a new value.
+#define BW_USB_USBCTRL_PDE(v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_PDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0 - USB transceiver is not in suspend state.
+ * - 1 - USB transceiver is in suspend state.
+ */
+//@{
+#define BP_USB_USBCTRL_SUSP  (7U)          //!< Bit position for USB_USBCTRL_SUSP.
+#define BM_USB_USBCTRL_SUSP  (0x80U)       //!< Bit mask for USB_USBCTRL_SUSP.
+#define BS_USB_USBCTRL_SUSP  (1U)          //!< Bit field size in bits for USB_USBCTRL_SUSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBCTRL_SUSP field.
+#define BR_USB_USBCTRL_SUSP  (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_SUSP))
+#endif
+
+//! @brief Format value for bitfield USB_USBCTRL_SUSP.
+#define BF_USB_USBCTRL_SUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBCTRL_SUSP), uint8_t) & BM_USB_USBCTRL_SUSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SUSP field to a new value.
+#define BW_USB_USBCTRL_SUSP(v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_SUSP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OBSERVE - USB OTG Observe register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+typedef union _hw_usb_observe
+{
+    uint8_t U;
+    struct _hw_usb_observe_bitfields
+    {
+        uint8_t RESERVED0 : 4;         //!< [3:0]
+        uint8_t DMPD : 1;              //!< [4]
+        uint8_t RESERVED1 : 1;         //!< [5]
+        uint8_t DPPD : 1;              //!< [6]
+        uint8_t DPPU : 1;              //!< [7]
+    } B;
+} hw_usb_observe_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+//@{
+#define HW_USB_OBSERVE_ADDR      (REGS_USB_BASE + 0x104U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OBSERVE           (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR)
+#define HW_USB_OBSERVE_RD()      (HW_USB_OBSERVE.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0 - D- pulldown disabled.
+ * - 1 - D- pulldown enabled.
+ */
+//@{
+#define BP_USB_OBSERVE_DMPD  (4U)          //!< Bit position for USB_OBSERVE_DMPD.
+#define BM_USB_OBSERVE_DMPD  (0x10U)       //!< Bit mask for USB_OBSERVE_DMPD.
+#define BS_USB_OBSERVE_DMPD  (1U)          //!< Bit field size in bits for USB_OBSERVE_DMPD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OBSERVE_DMPD field.
+#define BR_USB_OBSERVE_DMPD  (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DMPD))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0 - D+ pulldown disabled.
+ * - 1 - D+ pulldown enabled.
+ */
+//@{
+#define BP_USB_OBSERVE_DPPD  (6U)          //!< Bit position for USB_OBSERVE_DPPD.
+#define BM_USB_OBSERVE_DPPD  (0x40U)       //!< Bit mask for USB_OBSERVE_DPPD.
+#define BS_USB_OBSERVE_DPPD  (1U)          //!< Bit field size in bits for USB_OBSERVE_DPPD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OBSERVE_DPPD field.
+#define BR_USB_OBSERVE_DPPD  (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DPPD))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0 - D+ pullup disabled.
+ * - 1 - D+ pullup enabled.
+ */
+//@{
+#define BP_USB_OBSERVE_DPPU  (7U)          //!< Bit position for USB_OBSERVE_DPPU.
+#define BM_USB_OBSERVE_DPPU  (0x80U)       //!< Bit mask for USB_OBSERVE_DPPU.
+#define BS_USB_OBSERVE_DPPU  (1U)          //!< Bit field size in bits for USB_OBSERVE_DPPU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OBSERVE_DPPU field.
+#define BR_USB_OBSERVE_DPPU  (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DPPU))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CONTROL - USB OTG Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_usb_control
+{
+    uint8_t U;
+    struct _hw_usb_control_bitfields
+    {
+        uint8_t RESERVED0 : 4;         //!< [3:0]
+        uint8_t DPPULLUPNONOTG : 1;    //!< [4]
+        uint8_t RESERVED1 : 3;         //!< [7:5]
+    } B;
+} hw_usb_control_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+//@{
+#define HW_USB_CONTROL_ADDR      (REGS_USB_BASE + 0x108U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CONTROL           (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR)
+#define HW_USB_CONTROL_RD()      (HW_USB_CONTROL.U)
+#define HW_USB_CONTROL_WR(v)     (HW_USB_CONTROL.U = (v))
+#define HW_USB_CONTROL_SET(v)    (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() |  (v)))
+#define HW_USB_CONTROL_CLR(v)    (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() & ~(v)))
+#define HW_USB_CONTROL_TOG(v)    (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 1 - DP Pullup in non-OTG device mode is enabled.
+ */
+//@{
+#define BP_USB_CONTROL_DPPULLUPNONOTG (4U) //!< Bit position for USB_CONTROL_DPPULLUPNONOTG.
+#define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) //!< Bit mask for USB_CONTROL_DPPULLUPNONOTG.
+#define BS_USB_CONTROL_DPPULLUPNONOTG (1U) //!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field.
+#define BR_USB_CONTROL_DPPULLUPNONOTG (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR, BP_USB_CONTROL_DPPULLUPNONOTG))
+#endif
+
+//! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG.
+#define BF_USB_CONTROL_DPPULLUPNONOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CONTROL_DPPULLUPNONOTG), uint8_t) & BM_USB_CONTROL_DPPULLUPNONOTG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPPULLUPNONOTG field to a new value.
+#define BW_USB_CONTROL_DPPULLUPNONOTG(v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR, BP_USB_CONTROL_DPPULLUPNONOTG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_USBTRC0 - USB Transceiver Control register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+typedef union _hw_usb_usbtrc0
+{
+    uint8_t U;
+    struct _hw_usb_usbtrc0_bitfields
+    {
+        uint8_t USB_RESUME_INT : 1;    //!< [0] USB Asynchronous Interrupt
+        uint8_t SYNC_DET : 1;          //!< [1] Synchronous USB Interrupt Detect
+        uint8_t USB_CLK_RECOVERY_INT : 1; //!< [2] Combined USB Clock
+                                       //! Recovery interrupt status
+        uint8_t RESERVED0 : 2;         //!< [4:3]
+        uint8_t USBRESMEN : 1;         //!< [5] Asynchronous Resume Interrupt Enable
+        uint8_t RESERVED1 : 1;         //!< [6]
+        uint8_t USBRESET : 1;          //!< [7] USB Reset
+    } B;
+} hw_usb_usbtrc0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+//@{
+#define HW_USB_USBTRC0_ADDR      (REGS_USB_BASE + 0x10CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_USBTRC0           (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR)
+#define HW_USB_USBTRC0_RD()      (HW_USB_USBTRC0.U)
+#define HW_USB_USBTRC0_WR(v)     (HW_USB_USBTRC0.U = (v))
+#define HW_USB_USBTRC0_SET(v)    (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() |  (v)))
+#define HW_USB_USBTRC0_CLR(v)    (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() & ~(v)))
+#define HW_USB_USBTRC0_TOG(v)    (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0 - No interrupt was generated.
+ * - 1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+//@{
+#define BP_USB_USBTRC0_USB_RESUME_INT (0U) //!< Bit position for USB_USBTRC0_USB_RESUME_INT.
+#define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) //!< Bit mask for USB_USBTRC0_USB_RESUME_INT.
+#define BS_USB_USBTRC0_USB_RESUME_INT (1U) //!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field.
+#define BR_USB_USBTRC0_USB_RESUME_INT (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USB_RESUME_INT))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0 - Synchronous interrupt has not been detected.
+ * - 1 - Synchronous interrupt has been detected.
+ */
+//@{
+#define BP_USB_USBTRC0_SYNC_DET (1U)       //!< Bit position for USB_USBTRC0_SYNC_DET.
+#define BM_USB_USBTRC0_SYNC_DET (0x02U)    //!< Bit mask for USB_USBTRC0_SYNC_DET.
+#define BS_USB_USBTRC0_SYNC_DET (1U)       //!< Bit field size in bits for USB_USBTRC0_SYNC_DET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_SYNC_DET field.
+#define BR_USB_USBTRC0_SYNC_DET (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_SYNC_DET))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+//@{
+#define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) //!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT.
+#define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) //!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT.
+#define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) //!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field.
+#define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USB_CLK_RECOVERY_INT))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+//@{
+#define BP_USB_USBTRC0_USBRESMEN (5U)      //!< Bit position for USB_USBTRC0_USBRESMEN.
+#define BM_USB_USBTRC0_USBRESMEN (0x20U)   //!< Bit mask for USB_USBTRC0_USBRESMEN.
+#define BS_USB_USBTRC0_USBRESMEN (1U)      //!< Bit field size in bits for USB_USBTRC0_USBRESMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_USBRESMEN field.
+#define BR_USB_USBTRC0_USBRESMEN (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USBRESMEN))
+#endif
+
+//! @brief Format value for bitfield USB_USBTRC0_USBRESMEN.
+#define BF_USB_USBTRC0_USBRESMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBTRC0_USBRESMEN), uint8_t) & BM_USB_USBTRC0_USBRESMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBRESMEN field to a new value.
+#define BW_USB_USBTRC0_USBRESMEN(v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USBRESMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0 - Normal USB module operation.
+ * - 1 - Returns the USB module to its reset state.
+ */
+//@{
+#define BP_USB_USBTRC0_USBRESET (7U)       //!< Bit position for USB_USBTRC0_USBRESET.
+#define BM_USB_USBTRC0_USBRESET (0x80U)    //!< Bit mask for USB_USBTRC0_USBRESET.
+#define BS_USB_USBTRC0_USBRESET (1U)       //!< Bit field size in bits for USB_USBTRC0_USBRESET.
+
+//! @brief Format value for bitfield USB_USBTRC0_USBRESET.
+#define BF_USB_USBTRC0_USBRESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBTRC0_USBRESET), uint8_t) & BM_USB_USBTRC0_USBRESET)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_USBFRMADJUST - Frame Adjust Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_usb_usbfrmadjust
+{
+    uint8_t U;
+    struct _hw_usb_usbfrmadjust_bitfields
+    {
+        uint8_t ADJ : 8;               //!< [7:0] Frame Adjustment
+    } B;
+} hw_usb_usbfrmadjust_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+//@{
+#define HW_USB_USBFRMADJUST_ADDR (REGS_USB_BASE + 0x114U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_USBFRMADJUST      (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR)
+#define HW_USB_USBFRMADJUST_RD() (HW_USB_USBFRMADJUST.U)
+#define HW_USB_USBFRMADJUST_WR(v) (HW_USB_USBFRMADJUST.U = (v))
+#define HW_USB_USBFRMADJUST_SET(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() |  (v)))
+#define HW_USB_USBFRMADJUST_CLR(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() & ~(v)))
+#define HW_USB_USBFRMADJUST_TOG(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_USBFRMADJUST bitfields
+ */
+
+/*!
+ * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW)
+ *
+ * In Host mode, the frame adjustment is a twos complement number that adjusts
+ * the period of each USB frame in 12-MHz clock periods. A SOF is normally
+ * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this
+ * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock.
+ * Changes to the ADJ bit take effect at the next start of the next frame.
+ */
+//@{
+#define BP_USB_USBFRMADJUST_ADJ (0U)       //!< Bit position for USB_USBFRMADJUST_ADJ.
+#define BM_USB_USBFRMADJUST_ADJ (0xFFU)    //!< Bit mask for USB_USBFRMADJUST_ADJ.
+#define BS_USB_USBFRMADJUST_ADJ (8U)       //!< Bit field size in bits for USB_USBFRMADJUST_ADJ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBFRMADJUST_ADJ field.
+#define BR_USB_USBFRMADJUST_ADJ (HW_USB_USBFRMADJUST.U)
+#endif
+
+//! @brief Format value for bitfield USB_USBFRMADJUST_ADJ.
+#define BF_USB_USBFRMADJUST_ADJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBFRMADJUST_ADJ), uint8_t) & BM_USB_USBFRMADJUST_ADJ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADJ field to a new value.
+#define BW_USB_USBFRMADJUST_ADJ(v) (HW_USB_USBFRMADJUST_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+typedef union _hw_usb_clk_recover_ctrl
+{
+    uint8_t U;
+    struct _hw_usb_clk_recover_ctrl_bitfields
+    {
+        uint8_t RESERVED0 : 5;         //!< [4:0]
+        uint8_t RESTART_IFRTRIM_EN : 1; //!< [5] Restart from IFR trim value
+        uint8_t RESET_RESUME_ROUGH_EN : 1; //!< [6] Reset/resume to rough
+                                       //! phase enable
+        uint8_t CLOCK_RECOVER_EN : 1;  //!< [7] Crystal-less USB enable
+    } B;
+} hw_usb_clk_recover_ctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+//@{
+#define HW_USB_CLK_RECOVER_CTRL_ADDR (REGS_USB_BASE + 0x140U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CLK_RECOVER_CTRL  (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR)
+#define HW_USB_CLK_RECOVER_CTRL_RD() (HW_USB_CLK_RECOVER_CTRL.U)
+#define HW_USB_CLK_RECOVER_CTRL_WR(v) (HW_USB_CLK_RECOVER_CTRL.U = (v))
+#define HW_USB_CLK_RECOVER_CTRL_SET(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() |  (v)))
+#define HW_USB_CLK_RECOVER_CTRL_CLR(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() & ~(v)))
+#define HW_USB_CLK_RECOVER_CTRL_TOG(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+//@{
+#define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) //!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+#define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) //!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+#define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field.
+#define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+#define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESTART_IFRTRIM_EN field to a new value.
+#define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+//@{
+#define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) //!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+#define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) //!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+#define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field.
+#define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+#define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESET_RESUME_ROUGH_EN field to a new value.
+#define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0 - Disable clock recovery block (default)
+ * - 1 - Enable clock recovery block
+ */
+//@{
+#define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) //!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+#define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) //!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+#define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field.
+#define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+#define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLOCK_RECOVER_EN field to a new value.
+#define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+typedef union _hw_usb_clk_recover_irc_en
+{
+    uint8_t U;
+    struct _hw_usb_clk_recover_irc_en_bitfields
+    {
+        uint8_t REG_EN : 1;            //!< [0] IRC48M regulator enable
+        uint8_t IRC_EN : 1;            //!< [1] IRC48M enable
+        uint8_t RESERVED0 : 6;         //!< [7:2]
+    } B;
+} hw_usb_clk_recover_irc_en_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+//@{
+#define HW_USB_CLK_RECOVER_IRC_EN_ADDR (REGS_USB_BASE + 0x144U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CLK_RECOVER_IRC_EN (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR)
+#define HW_USB_CLK_RECOVER_IRC_EN_RD() (HW_USB_CLK_RECOVER_IRC_EN.U)
+#define HW_USB_CLK_RECOVER_IRC_EN_WR(v) (HW_USB_CLK_RECOVER_IRC_EN.U = (v))
+#define HW_USB_CLK_RECOVER_IRC_EN_SET(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() |  (v)))
+#define HW_USB_CLK_RECOVER_IRC_EN_CLR(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() & ~(v)))
+#define HW_USB_CLK_RECOVER_IRC_EN_TOG(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0 - IRC48M local regulator is disabled
+ * - 1 - IRC48M local regulator is enabled (default)
+ */
+//@{
+#define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) //!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN.
+#define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) //!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN.
+#define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field.
+#define BR_USB_CLK_RECOVER_IRC_EN_REG_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_REG_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN.
+#define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN), uint8_t) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REG_EN field to a new value.
+#define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0 - Disable the IRC48M module (default)
+ * - 1 - Enable the IRC48M module
+ */
+//@{
+#define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) //!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN.
+#define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) //!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN.
+#define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field.
+#define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_IRC_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN.
+#define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN), uint8_t) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRC_EN field to a new value.
+#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+typedef union _hw_usb_clk_recover_int_status
+{
+    uint8_t U;
+    struct _hw_usb_clk_recover_int_status_bitfields
+    {
+        uint8_t RESERVED0 : 4;         //!< [3:0]
+        uint8_t OVF_ERROR : 1;         //!< [4]
+        uint8_t RESERVED1 : 3;         //!< [7:5]
+    } B;
+} hw_usb_clk_recover_int_status_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+//@{
+#define HW_USB_CLK_RECOVER_INT_STATUS_ADDR (REGS_USB_BASE + 0x15CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CLK_RECOVER_INT_STATUS (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR)
+#define HW_USB_CLK_RECOVER_INT_STATUS_RD() (HW_USB_CLK_RECOVER_INT_STATUS.U)
+#define HW_USB_CLK_RECOVER_INT_STATUS_WR(v) (HW_USB_CLK_RECOVER_INT_STATUS.U = (v))
+#define HW_USB_CLK_RECOVER_INT_STATUS_SET(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() |  (v)))
+#define HW_USB_CLK_RECOVER_INT_STATUS_CLR(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() & ~(v)))
+#define HW_USB_CLK_RECOVER_INT_STATUS_TOG(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0 - No interrupt is reported
+ * - 1 - Unmasked interrupt has been generated
+ */
+//@{
+#define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) //!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+#define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) //!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+#define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) //!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field.
+#define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR, BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+#define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR), uint8_t) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OVF_ERROR field to a new value.
+#define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR, BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_usb_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All USB module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_usb
+{
+    __I hw_usb_perid_t PERID;              //!< [0x0] Peripheral ID register
+    uint8_t _reserved0[3];
+    __I hw_usb_idcomp_t IDCOMP;            //!< [0x4] Peripheral ID Complement register
+    uint8_t _reserved1[3];
+    __I hw_usb_rev_t REV;                  //!< [0x8] Peripheral Revision register
+    uint8_t _reserved2[3];
+    __I hw_usb_addinfo_t ADDINFO;          //!< [0xC] Peripheral Additional Info register
+    uint8_t _reserved3[3];
+    __IO hw_usb_otgistat_t OTGISTAT;       //!< [0x10] OTG Interrupt Status register
+    uint8_t _reserved4[3];
+    __IO hw_usb_otgicr_t OTGICR;           //!< [0x14] OTG Interrupt Control register
+    uint8_t _reserved5[3];
+    __IO hw_usb_otgstat_t OTGSTAT;         //!< [0x18] OTG Status register
+    uint8_t _reserved6[3];
+    __IO hw_usb_otgctl_t OTGCTL;           //!< [0x1C] OTG Control register
+    uint8_t _reserved7[99];
+    __IO hw_usb_istat_t ISTAT;             //!< [0x80] Interrupt Status register
+    uint8_t _reserved8[3];
+    __IO hw_usb_inten_t INTEN;             //!< [0x84] Interrupt Enable register
+    uint8_t _reserved9[3];
+    __IO hw_usb_errstat_t ERRSTAT;         //!< [0x88] Error Interrupt Status register
+    uint8_t _reserved10[3];
+    __IO hw_usb_erren_t ERREN;             //!< [0x8C] Error Interrupt Enable register
+    uint8_t _reserved11[3];
+    __I hw_usb_stat_t STAT;                //!< [0x90] Status register
+    uint8_t _reserved12[3];
+    __IO hw_usb_ctl_t CTL;                 //!< [0x94] Control register
+    uint8_t _reserved13[3];
+    __IO hw_usb_addr_t ADDR;               //!< [0x98] Address register
+    uint8_t _reserved14[3];
+    __IO hw_usb_bdtpage1_t BDTPAGE1;       //!< [0x9C] BDT Page register 1
+    uint8_t _reserved15[3];
+    __IO hw_usb_frmnuml_t FRMNUML;         //!< [0xA0] Frame Number register Low
+    uint8_t _reserved16[3];
+    __IO hw_usb_frmnumh_t FRMNUMH;         //!< [0xA4] Frame Number register High
+    uint8_t _reserved17[3];
+    __IO hw_usb_token_t TOKEN;             //!< [0xA8] Token register
+    uint8_t _reserved18[3];
+    __IO hw_usb_softhld_t SOFTHLD;         //!< [0xAC] SOF Threshold register
+    uint8_t _reserved19[3];
+    __IO hw_usb_bdtpage2_t BDTPAGE2;       //!< [0xB0] BDT Page Register 2
+    uint8_t _reserved20[3];
+    __IO hw_usb_bdtpage3_t BDTPAGE3;       //!< [0xB4] BDT Page Register 3
+    uint8_t _reserved21[11];
+    struct {
+        __IO hw_usb_endptn_t ENDPTn;       //!< [0xC0] Endpoint Control register
+        uint8_t _reserved0[3];
+    } ENDPOINT[16];
+    __IO hw_usb_usbctrl_t USBCTRL;         //!< [0x100] USB Control register
+    uint8_t _reserved22[3];
+    __I hw_usb_observe_t OBSERVE;          //!< [0x104] USB OTG Observe register
+    uint8_t _reserved23[3];
+    __IO hw_usb_control_t CONTROL;         //!< [0x108] USB OTG Control register
+    uint8_t _reserved24[3];
+    __IO hw_usb_usbtrc0_t USBTRC0;         //!< [0x10C] USB Transceiver Control register 0
+    uint8_t _reserved25[7];
+    __IO hw_usb_usbfrmadjust_t USBFRMADJUST; //!< [0x114] Frame Adjust Register
+    uint8_t _reserved26[43];
+    __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; //!< [0x140] USB Clock recovery control
+    uint8_t _reserved27[3];
+    __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; //!< [0x144] IRC48M oscillator enable register
+    uint8_t _reserved28[23];
+    __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; //!< [0x15C] Clock recovery separated interrupt status
+} hw_usb_t;
+#pragma pack()
+
+//! @brief Macro to access all USB registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_USB</code>.
+#define HW_USB         (*(hw_usb_t *) REGS_USB_BASE)
+#endif
+
+#endif // __HW_USB_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h
new file mode 100644
index 0000000000..0f9a9ff611
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h
@@ -0,0 +1,957 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_USBDCD_REGISTERS_H__
+#define __HW_USBDCD_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - HW_USBDCD_CONTROL - Control register
+ * - HW_USBDCD_CLOCK - Clock register
+ * - HW_USBDCD_STATUS - Status register
+ * - HW_USBDCD_TIMER0 - TIMER0 register
+ * - HW_USBDCD_TIMER1 - TIMER1 register
+ * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ *
+ * - hw_usbdcd_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_USBDCD_BASE
+#define HW_USBDCD_INSTANCE_COUNT (1U) //!< Number of instances of the USBDCD module.
+#define HW_USBDCD0 (0U) //!< Instance number for USBDCD.
+#define REGS_USBDCD0_BASE (0x40035000U) //!< Base address for USBDCD.
+
+//! @brief Table of base addresses for USBDCD instances.
+static const uint32_t __g_regs_USBDCD_base_addresses[] = {
+        REGS_USBDCD0_BASE,
+    };
+
+//! @brief Get the base address of USBDCD by instance number.
+//! @param x USBDCD instance number, from 0 through 0.
+#define REGS_USBDCD_BASE(x) (__g_regs_USBDCD_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of USBDCD.
+#define REGS_USBDCD_INSTANCE(b) ((b) == REGS_USBDCD0_BASE ? HW_USBDCD0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_CONTROL - Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+typedef union _hw_usbdcd_control
+{
+    uint32_t U;
+    struct _hw_usbdcd_control_bitfields
+    {
+        uint32_t IACK : 1;             //!< [0] Interrupt Acknowledge
+        uint32_t RESERVED0 : 7;        //!< [7:1]
+        uint32_t IF : 1;               //!< [8] Interrupt Flag
+        uint32_t RESERVED1 : 7;        //!< [15:9]
+        uint32_t IE : 1;               //!< [16] Interrupt Enable
+        uint32_t BC12 : 1;             //!< [17]
+        uint32_t RESERVED2 : 6;        //!< [23:18]
+        uint32_t START : 1;            //!< [24] Start Change Detection Sequence
+        uint32_t SR : 1;               //!< [25] Software Reset
+        uint32_t RESERVED3 : 6;        //!< [31:26]
+    } B;
+} hw_usbdcd_control_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+//@{
+#define HW_USBDCD_CONTROL_ADDR(x) (REGS_USBDCD_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_CONTROL(x)     (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x))
+#define HW_USBDCD_CONTROL_RD(x)  (HW_USBDCD_CONTROL(x).U)
+#define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v))
+#define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) |  (v)))
+#define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v)))
+#define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0 - Do not clear the interrupt.
+ * - 1 - Clear the IF bit (interrupt flag).
+ */
+//@{
+#define BP_USBDCD_CONTROL_IACK (0U)        //!< Bit position for USBDCD_CONTROL_IACK.
+#define BM_USBDCD_CONTROL_IACK (0x00000001U) //!< Bit mask for USBDCD_CONTROL_IACK.
+#define BS_USBDCD_CONTROL_IACK (1U)        //!< Bit field size in bits for USBDCD_CONTROL_IACK.
+
+//! @brief Format value for bitfield USBDCD_CONTROL_IACK.
+#define BF_USBDCD_CONTROL_IACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IACK), uint32_t) & BM_USBDCD_CONTROL_IACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IACK field to a new value.
+#define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0 - No interrupt is pending.
+ * - 1 - An interrupt is pending.
+ */
+//@{
+#define BP_USBDCD_CONTROL_IF (8U)          //!< Bit position for USBDCD_CONTROL_IF.
+#define BM_USBDCD_CONTROL_IF (0x00000100U) //!< Bit mask for USBDCD_CONTROL_IF.
+#define BS_USBDCD_CONTROL_IF (1U)          //!< Bit field size in bits for USBDCD_CONTROL_IF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CONTROL_IF field.
+#define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0 - Disable interrupts to the system.
+ * - 1 - Enable interrupts to the system.
+ */
+//@{
+#define BP_USBDCD_CONTROL_IE (16U)         //!< Bit position for USBDCD_CONTROL_IE.
+#define BM_USBDCD_CONTROL_IE (0x00010000U) //!< Bit mask for USBDCD_CONTROL_IE.
+#define BS_USBDCD_CONTROL_IE (1U)          //!< Bit field size in bits for USBDCD_CONTROL_IE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CONTROL_IE field.
+#define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE))
+#endif
+
+//! @brief Format value for bitfield USBDCD_CONTROL_IE.
+#define BF_USBDCD_CONTROL_IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IE), uint32_t) & BM_USBDCD_CONTROL_IE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IE field to a new value.
+#define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0 - Compatible with BC1.1 (default)
+ * - 1 - Compatible with BC1.2
+ */
+//@{
+#define BP_USBDCD_CONTROL_BC12 (17U)       //!< Bit position for USBDCD_CONTROL_BC12.
+#define BM_USBDCD_CONTROL_BC12 (0x00020000U) //!< Bit mask for USBDCD_CONTROL_BC12.
+#define BS_USBDCD_CONTROL_BC12 (1U)        //!< Bit field size in bits for USBDCD_CONTROL_BC12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CONTROL_BC12 field.
+#define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12))
+#endif
+
+//! @brief Format value for bitfield USBDCD_CONTROL_BC12.
+#define BF_USBDCD_CONTROL_BC12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_BC12), uint32_t) & BM_USBDCD_CONTROL_BC12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BC12 field to a new value.
+#define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0 - Do not start the sequence. Writes of this value have no effect.
+ * - 1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+//@{
+#define BP_USBDCD_CONTROL_START (24U)      //!< Bit position for USBDCD_CONTROL_START.
+#define BM_USBDCD_CONTROL_START (0x01000000U) //!< Bit mask for USBDCD_CONTROL_START.
+#define BS_USBDCD_CONTROL_START (1U)       //!< Bit field size in bits for USBDCD_CONTROL_START.
+
+//! @brief Format value for bitfield USBDCD_CONTROL_START.
+#define BF_USBDCD_CONTROL_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_START), uint32_t) & BM_USBDCD_CONTROL_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the START field to a new value.
+#define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0 - Do not perform a software reset.
+ * - 1 - Perform a software reset.
+ */
+//@{
+#define BP_USBDCD_CONTROL_SR (25U)         //!< Bit position for USBDCD_CONTROL_SR.
+#define BM_USBDCD_CONTROL_SR (0x02000000U) //!< Bit mask for USBDCD_CONTROL_SR.
+#define BS_USBDCD_CONTROL_SR (1U)          //!< Bit field size in bits for USBDCD_CONTROL_SR.
+
+//! @brief Format value for bitfield USBDCD_CONTROL_SR.
+#define BF_USBDCD_CONTROL_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_SR), uint32_t) & BM_USBDCD_CONTROL_SR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SR field to a new value.
+#define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_CLOCK - Clock register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+typedef union _hw_usbdcd_clock
+{
+    uint32_t U;
+    struct _hw_usbdcd_clock_bitfields
+    {
+        uint32_t CLOCK_UNIT : 1;       //!< [0] Unit of Measurement Encoding for
+                                       //! Clock Speed
+        uint32_t RESERVED0 : 1;        //!< [1]
+        uint32_t CLOCK_SPEED : 10;     //!< [11:2] Numerical Value of Clock Speed
+                                       //! in Binary
+        uint32_t RESERVED1 : 20;       //!< [31:12]
+    } B;
+} hw_usbdcd_clock_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+//@{
+#define HW_USBDCD_CLOCK_ADDR(x)  (REGS_USBDCD_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_CLOCK(x)       (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x))
+#define HW_USBDCD_CLOCK_RD(x)    (HW_USBDCD_CLOCK(x).U)
+#define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v))
+#define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) |  (v)))
+#define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v)))
+#define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+//@{
+#define BP_USBDCD_CLOCK_CLOCK_UNIT (0U)    //!< Bit position for USBDCD_CLOCK_CLOCK_UNIT.
+#define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) //!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT.
+#define BS_USBDCD_CLOCK_CLOCK_UNIT (1U)    //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field.
+#define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT))
+#endif
+
+//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT.
+#define BF_USBDCD_CLOCK_CLOCK_UNIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_UNIT), uint32_t) & BM_USBDCD_CLOCK_CLOCK_UNIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLOCK_UNIT field to a new value.
+#define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+//@{
+#define BP_USBDCD_CLOCK_CLOCK_SPEED (2U)   //!< Bit position for USBDCD_CLOCK_CLOCK_SPEED.
+#define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) //!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED.
+#define BS_USBDCD_CLOCK_CLOCK_SPEED (10U)  //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field.
+#define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED)
+#endif
+
+//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED.
+#define BF_USBDCD_CLOCK_CLOCK_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_SPEED), uint32_t) & BM_USBDCD_CLOCK_CLOCK_SPEED)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLOCK_SPEED field to a new value.
+#define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_STATUS - Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+typedef union _hw_usbdcd_status
+{
+    uint32_t U;
+    struct _hw_usbdcd_status_bitfields
+    {
+        uint32_t RESERVED0 : 16;       //!< [15:0]
+        uint32_t SEQ_RES : 2;          //!< [17:16] Charger Detection Sequence Results
+        uint32_t SEQ_STAT : 2;         //!< [19:18] Charger Detection Sequence Status
+        uint32_t ERR : 1;              //!< [20] Error Flag
+        uint32_t TO : 1;               //!< [21] Timeout Flag
+        uint32_t ACTIVE : 1;           //!< [22] Active Status Indicator
+        uint32_t RESERVED1 : 9;        //!< [31:23]
+    } B;
+} hw_usbdcd_status_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+//@{
+#define HW_USBDCD_STATUS_ADDR(x) (REGS_USBDCD_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_STATUS(x)      (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x))
+#define HW_USBDCD_STATUS_RD(x)   (HW_USBDCD_STATUS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 00 - No results to report.
+ * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only
+ *     2.5 mA (max) until connected.
+ * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger type
+ *     detection has not completed. 1: Attached to a charging host. The charger
+ *     type detection has completed.
+ * - 11 - Attached to a dedicated charger.
+ */
+//@{
+#define BP_USBDCD_STATUS_SEQ_RES (16U)     //!< Bit position for USBDCD_STATUS_SEQ_RES.
+#define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) //!< Bit mask for USBDCD_STATUS_SEQ_RES.
+#define BS_USBDCD_STATUS_SEQ_RES (2U)      //!< Bit field size in bits for USBDCD_STATUS_SEQ_RES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_SEQ_RES field.
+#define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES)
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 01 - Data pin contact detection is complete.
+ * - 10 - Charging port detection is complete.
+ * - 11 - Charger type detection is complete.
+ */
+//@{
+#define BP_USBDCD_STATUS_SEQ_STAT (18U)    //!< Bit position for USBDCD_STATUS_SEQ_STAT.
+#define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) //!< Bit mask for USBDCD_STATUS_SEQ_STAT.
+#define BS_USBDCD_STATUS_SEQ_STAT (2U)     //!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field.
+#define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT)
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0 - No sequence errors.
+ * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+//@{
+#define BP_USBDCD_STATUS_ERR (20U)         //!< Bit position for USBDCD_STATUS_ERR.
+#define BM_USBDCD_STATUS_ERR (0x00100000U) //!< Bit mask for USBDCD_STATUS_ERR.
+#define BS_USBDCD_STATUS_ERR (1U)          //!< Bit field size in bits for USBDCD_STATUS_ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_ERR field.
+#define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0 - The detection sequence has not been running for over 1 s.
+ * - 1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+//@{
+#define BP_USBDCD_STATUS_TO  (21U)         //!< Bit position for USBDCD_STATUS_TO.
+#define BM_USBDCD_STATUS_TO  (0x00200000U) //!< Bit mask for USBDCD_STATUS_TO.
+#define BS_USBDCD_STATUS_TO  (1U)          //!< Bit field size in bits for USBDCD_STATUS_TO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_TO field.
+#define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0 - The sequence is not running.
+ * - 1 - The sequence is running.
+ */
+//@{
+#define BP_USBDCD_STATUS_ACTIVE (22U)      //!< Bit position for USBDCD_STATUS_ACTIVE.
+#define BM_USBDCD_STATUS_ACTIVE (0x00400000U) //!< Bit mask for USBDCD_STATUS_ACTIVE.
+#define BS_USBDCD_STATUS_ACTIVE (1U)       //!< Bit field size in bits for USBDCD_STATUS_ACTIVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_ACTIVE field.
+#define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER0 - TIMER0 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+typedef union _hw_usbdcd_timer0
+{
+    uint32_t U;
+    struct _hw_usbdcd_timer0_bitfields
+    {
+        uint32_t TUNITCON : 12;        //!< [11:0] Unit Connection Timer Elapse (in
+                                       //! ms)
+        uint32_t RESERVED0 : 4;        //!< [15:12]
+        uint32_t TSEQ_INIT : 10;       //!< [25:16] Sequence Initiation Time
+        uint32_t RESERVED1 : 6;        //!< [31:26]
+    } B;
+} hw_usbdcd_timer0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+//@{
+#define HW_USBDCD_TIMER0_ADDR(x) (REGS_USBDCD_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER0(x)      (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x))
+#define HW_USBDCD_TIMER0_RD(x)   (HW_USBDCD_TIMER0(x).U)
+#define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v))
+#define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) |  (v)))
+#define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+//@{
+#define BP_USBDCD_TIMER0_TUNITCON (0U)     //!< Bit position for USBDCD_TIMER0_TUNITCON.
+#define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) //!< Bit mask for USBDCD_TIMER0_TUNITCON.
+#define BS_USBDCD_TIMER0_TUNITCON (12U)    //!< Bit field size in bits for USBDCD_TIMER0_TUNITCON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER0_TUNITCON field.
+#define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON)
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+//@{
+#define BP_USBDCD_TIMER0_TSEQ_INIT (16U)   //!< Bit position for USBDCD_TIMER0_TSEQ_INIT.
+#define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) //!< Bit mask for USBDCD_TIMER0_TSEQ_INIT.
+#define BS_USBDCD_TIMER0_TSEQ_INIT (10U)   //!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field.
+#define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT.
+#define BF_USBDCD_TIMER0_TSEQ_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER0_TSEQ_INIT), uint32_t) & BM_USBDCD_TIMER0_TSEQ_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSEQ_INIT field to a new value.
+#define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER1 - TIMER1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+typedef union _hw_usbdcd_timer1
+{
+    uint32_t U;
+    struct _hw_usbdcd_timer1_bitfields
+    {
+        uint32_t TVDPSRC_ON : 10;      //!< [9:0] Time Period Comparator Enabled
+        uint32_t RESERVED0 : 6;        //!< [15:10]
+        uint32_t TDCD_DBNC : 10;       //!< [25:16] Time Period to Debounce D+
+                                       //! Signal
+        uint32_t RESERVED1 : 6;        //!< [31:26]
+    } B;
+} hw_usbdcd_timer1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+//@{
+#define HW_USBDCD_TIMER1_ADDR(x) (REGS_USBDCD_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER1(x)      (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x))
+#define HW_USBDCD_TIMER1_RD(x)   (HW_USBDCD_TIMER1(x).U)
+#define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v))
+#define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) |  (v)))
+#define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+//@{
+#define BP_USBDCD_TIMER1_TVDPSRC_ON (0U)   //!< Bit position for USBDCD_TIMER1_TVDPSRC_ON.
+#define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON.
+#define BS_USBDCD_TIMER1_TVDPSRC_ON (10U)  //!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field.
+#define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON.
+#define BF_USBDCD_TIMER1_TVDPSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TVDPSRC_ON), uint32_t) & BM_USBDCD_TIMER1_TVDPSRC_ON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TVDPSRC_ON field to a new value.
+#define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+//@{
+#define BP_USBDCD_TIMER1_TDCD_DBNC (16U)   //!< Bit position for USBDCD_TIMER1_TDCD_DBNC.
+#define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) //!< Bit mask for USBDCD_TIMER1_TDCD_DBNC.
+#define BS_USBDCD_TIMER1_TDCD_DBNC (10U)   //!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field.
+#define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC.
+#define BF_USBDCD_TIMER1_TDCD_DBNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TDCD_DBNC), uint32_t) & BM_USBDCD_TIMER1_TDCD_DBNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDCD_DBNC field to a new value.
+#define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+typedef union _hw_usbdcd_timer2_bc11
+{
+    uint32_t U;
+    struct _hw_usbdcd_timer2_bc11_bitfields
+    {
+        uint32_t CHECK_DM : 4;         //!< [3:0] Time Before Check of D- Line
+        uint32_t RESERVED0 : 12;       //!< [15:4]
+        uint32_t TVDPSRC_CON : 10;     //!< [25:16] Time Period Before Enabling
+                                       //! D+ Pullup
+        uint32_t RESERVED1 : 6;        //!< [31:26]
+    } B;
+} hw_usbdcd_timer2_bc11_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+//@{
+#define HW_USBDCD_TIMER2_BC11_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x))
+#define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U)
+#define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v))
+#define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) |  (v)))
+#define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) //!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM.
+#define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) //!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM.
+#define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field.
+#define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM.
+#define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_CHECK_DM), uint32_t) & BM_USBDCD_TIMER2_BC11_CHECK_DM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHECK_DM field to a new value.
+#define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) //!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON.
+#define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON.
+#define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field.
+#define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON.
+#define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON), uint32_t) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TVDPSRC_CON field to a new value.
+#define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+typedef union _hw_usbdcd_timer2_bc12
+{
+    uint32_t U;
+    struct _hw_usbdcd_timer2_bc12_bitfields
+    {
+        uint32_t TVDMSRC_ON : 10;      //!< [9:0]
+        uint32_t RESERVED0 : 6;        //!< [15:10]
+        uint32_t TWAIT_AFTER_PRD : 10; //!< [25:16]
+        uint32_t RESERVED1 : 6;        //!< [31:26]
+    } B;
+} hw_usbdcd_timer2_bc12_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+//@{
+#define HW_USBDCD_TIMER2_BC12_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x))
+#define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U)
+#define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v))
+#define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) |  (v)))
+#define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) //!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON.
+#define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON.
+#define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field.
+#define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON.
+#define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON), uint32_t) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TVDMSRC_ON field to a new value.
+#define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) //!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+#define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+#define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field.
+#define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+#define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD), uint32_t) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWAIT_AFTER_PRD field to a new value.
+#define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_usbdcd_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All USBDCD module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_usbdcd
+{
+    __IO hw_usbdcd_control_t CONTROL;      //!< [0x0] Control register
+    __IO hw_usbdcd_clock_t CLOCK;          //!< [0x4] Clock register
+    __I hw_usbdcd_status_t STATUS;         //!< [0x8] Status register
+    uint8_t _reserved0[4];
+    __IO hw_usbdcd_timer0_t TIMER0;        //!< [0x10] TIMER0 register
+    __IO hw_usbdcd_timer1_t TIMER1;        //!< [0x14] TIMER1 register
+    union {
+        __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; //!< [0x18] TIMER2_BC11 register
+        __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; //!< [0x18] TIMER2_BC12 register
+    };
+} hw_usbdcd_t;
+#pragma pack()
+
+//! @brief Macro to access all USBDCD registers.
+//! @param x USBDCD instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_USBDCD(0)</code>.
+#define HW_USBDCD(x)   (*(hw_usbdcd_t *) REGS_USBDCD_BASE(x))
+#endif
+
+#endif // __HW_USBDCD_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h
new file mode 100644
index 0000000000..4b7b0a3fe6
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_VREF_REGISTERS_H__
+#define __HW_VREF_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - HW_VREF_TRM - VREF Trim Register
+ * - HW_VREF_SC - VREF Status and Control Register
+ *
+ * - hw_vref_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_VREF_BASE
+#define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module.
+#define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_VREF_TRM - VREF Trim Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+typedef union _hw_vref_trm
+{
+    uint8_t U;
+    struct _hw_vref_trm_bitfields
+    {
+        uint8_t TRIM : 6;              //!< [5:0] Trim bits
+        uint8_t CHOPEN : 1;            //!< [6] Chop oscillator enable. When set,
+                                       //! internal chopping operation is enabled and the internal analog offset will
+                                       //! be minimized.
+        uint8_t RESERVED0 : 1;         //!< [7]
+    } B;
+} hw_vref_trm_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+//@{
+#define HW_VREF_TRM_ADDR         (REGS_VREF_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_VREF_TRM              (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR)
+#define HW_VREF_TRM_RD()         (HW_VREF_TRM.U)
+#define HW_VREF_TRM_WR(v)        (HW_VREF_TRM.U = (v))
+#define HW_VREF_TRM_SET(v)       (HW_VREF_TRM_WR(HW_VREF_TRM_RD() |  (v)))
+#define HW_VREF_TRM_CLR(v)       (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v)))
+#define HW_VREF_TRM_TOG(v)       (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 000000 - Min
+ * - 111111 - Max
+ */
+//@{
+#define BP_VREF_TRM_TRIM     (0U)          //!< Bit position for VREF_TRM_TRIM.
+#define BM_VREF_TRM_TRIM     (0x3FU)       //!< Bit mask for VREF_TRM_TRIM.
+#define BS_VREF_TRM_TRIM     (6U)          //!< Bit field size in bits for VREF_TRM_TRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_TRM_TRIM field.
+#define BR_VREF_TRM_TRIM     (HW_VREF_TRM.B.TRIM)
+#endif
+
+//! @brief Format value for bitfield VREF_TRM_TRIM.
+#define BF_VREF_TRM_TRIM(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIM field to a new value.
+#define BW_VREF_TRM_TRIM(v)  (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0 - Chop oscillator is disabled.
+ * - 1 - Chop oscillator is enabled.
+ */
+//@{
+#define BP_VREF_TRM_CHOPEN   (6U)          //!< Bit position for VREF_TRM_CHOPEN.
+#define BM_VREF_TRM_CHOPEN   (0x40U)       //!< Bit mask for VREF_TRM_CHOPEN.
+#define BS_VREF_TRM_CHOPEN   (1U)          //!< Bit field size in bits for VREF_TRM_CHOPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_TRM_CHOPEN field.
+#define BR_VREF_TRM_CHOPEN   (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN))
+#endif
+
+//! @brief Format value for bitfield VREF_TRM_CHOPEN.
+#define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHOPEN field to a new value.
+#define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_VREF_SC - VREF Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+typedef union _hw_vref_sc
+{
+    uint8_t U;
+    struct _hw_vref_sc_bitfields
+    {
+        uint8_t MODE_LV : 2;           //!< [1:0] Buffer Mode selection
+        uint8_t VREFST : 1;            //!< [2] Internal Voltage Reference stable
+        uint8_t RESERVED0 : 2;         //!< [4:3]
+        uint8_t ICOMPEN : 1;           //!< [5] Second order curvature compensation
+                                       //! enable
+        uint8_t REGEN : 1;             //!< [6] Regulator enable
+        uint8_t VREFEN : 1;            //!< [7] Internal Voltage Reference enable
+    } B;
+} hw_vref_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+//@{
+#define HW_VREF_SC_ADDR          (REGS_VREF_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_VREF_SC               (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR)
+#define HW_VREF_SC_RD()          (HW_VREF_SC.U)
+#define HW_VREF_SC_WR(v)         (HW_VREF_SC.U = (v))
+#define HW_VREF_SC_SET(v)        (HW_VREF_SC_WR(HW_VREF_SC_RD() |  (v)))
+#define HW_VREF_SC_CLR(v)        (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v)))
+#define HW_VREF_SC_TOG(v)        (HW_VREF_SC_WR(HW_VREF_SC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 00 - Bandgap on only, for stabilization and startup
+ * - 01 - High power buffer mode enabled
+ * - 10 - Low-power buffer mode enabled
+ * - 11 - Reserved
+ */
+//@{
+#define BP_VREF_SC_MODE_LV   (0U)          //!< Bit position for VREF_SC_MODE_LV.
+#define BM_VREF_SC_MODE_LV   (0x03U)       //!< Bit mask for VREF_SC_MODE_LV.
+#define BS_VREF_SC_MODE_LV   (2U)          //!< Bit field size in bits for VREF_SC_MODE_LV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_MODE_LV field.
+#define BR_VREF_SC_MODE_LV   (HW_VREF_SC.B.MODE_LV)
+#endif
+
+//! @brief Format value for bitfield VREF_SC_MODE_LV.
+#define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MODE_LV field to a new value.
+#define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0 - The module is disabled or not stable.
+ * - 1 - The module is stable.
+ */
+//@{
+#define BP_VREF_SC_VREFST    (2U)          //!< Bit position for VREF_SC_VREFST.
+#define BM_VREF_SC_VREFST    (0x04U)       //!< Bit mask for VREF_SC_VREFST.
+#define BS_VREF_SC_VREFST    (1U)          //!< Bit field size in bits for VREF_SC_VREFST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_VREFST field.
+#define BR_VREF_SC_VREFST    (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_VREF_SC_ICOMPEN   (5U)          //!< Bit position for VREF_SC_ICOMPEN.
+#define BM_VREF_SC_ICOMPEN   (0x20U)       //!< Bit mask for VREF_SC_ICOMPEN.
+#define BS_VREF_SC_ICOMPEN   (1U)          //!< Bit field size in bits for VREF_SC_ICOMPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_ICOMPEN field.
+#define BR_VREF_SC_ICOMPEN   (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN))
+#endif
+
+//! @brief Format value for bitfield VREF_SC_ICOMPEN.
+#define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ICOMPEN field to a new value.
+#define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0 - Internal 1.75 V regulator is disabled.
+ * - 1 - Internal 1.75 V regulator is enabled.
+ */
+//@{
+#define BP_VREF_SC_REGEN     (6U)          //!< Bit position for VREF_SC_REGEN.
+#define BM_VREF_SC_REGEN     (0x40U)       //!< Bit mask for VREF_SC_REGEN.
+#define BS_VREF_SC_REGEN     (1U)          //!< Bit field size in bits for VREF_SC_REGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_REGEN field.
+#define BR_VREF_SC_REGEN     (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN))
+#endif
+
+//! @brief Format value for bitfield VREF_SC_REGEN.
+#define BF_VREF_SC_REGEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REGEN field to a new value.
+#define BW_VREF_SC_REGEN(v)  (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0 - The module is disabled.
+ * - 1 - The module is enabled.
+ */
+//@{
+#define BP_VREF_SC_VREFEN    (7U)          //!< Bit position for VREF_SC_VREFEN.
+#define BM_VREF_SC_VREFEN    (0x80U)       //!< Bit mask for VREF_SC_VREFEN.
+#define BS_VREF_SC_VREFEN    (1U)          //!< Bit field size in bits for VREF_SC_VREFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_VREFEN field.
+#define BR_VREF_SC_VREFEN    (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN))
+#endif
+
+//! @brief Format value for bitfield VREF_SC_VREFEN.
+#define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VREFEN field to a new value.
+#define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_vref_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All VREF module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_vref
+{
+    __IO hw_vref_trm_t TRM;                //!< [0x0] VREF Trim Register
+    __IO hw_vref_sc_t SC;                  //!< [0x1] VREF Status and Control Register
+} hw_vref_t;
+#pragma pack()
+
+//! @brief Macro to access all VREF registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_VREF</code>.
+#define HW_VREF        (*(hw_vref_t *) REGS_VREF_BASE)
+#endif
+
+#endif // __HW_VREF_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h b/bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h
new file mode 100644
index 0000000000..5f07371b7d
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h
@@ -0,0 +1,1244 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_WDOG_REGISTERS_H__
+#define __HW_WDOG_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - HW_WDOG_WINH - Watchdog Window Register High
+ * - HW_WDOG_WINL - Watchdog Window Register Low
+ * - HW_WDOG_REFRESH - Watchdog Refresh register
+ * - HW_WDOG_UNLOCK - Watchdog Unlock register
+ * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - HW_WDOG_RSTCNT - Watchdog Reset Count register
+ * - HW_WDOG_PRESC - Watchdog Prescaler register
+ *
+ * - hw_wdog_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_WDOG_BASE
+#define HW_WDOG_INSTANCE_COUNT (1U) //!< Number of instances of the WDOG module.
+#define REGS_WDOG_BASE (0x40052000U) //!< Base address for WDOG.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_STCTRLH - Watchdog Status and Control Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+typedef union _hw_wdog_stctrlh
+{
+    uint16_t U;
+    struct _hw_wdog_stctrlh_bitfields
+    {
+        uint16_t WDOGEN : 1;           //!< [0]
+        uint16_t CLKSRC : 1;           //!< [1]
+        uint16_t IRQRSTEN : 1;         //!< [2]
+        uint16_t WINEN : 1;            //!< [3]
+        uint16_t ALLOWUPDATE : 1;      //!< [4]
+        uint16_t DBGEN : 1;            //!< [5]
+        uint16_t STOPEN : 1;           //!< [6]
+        uint16_t WAITEN : 1;           //!< [7]
+        uint16_t RESERVED0 : 2;        //!< [9:8]
+        uint16_t TESTWDOG : 1;         //!< [10]
+        uint16_t TESTSEL : 1;          //!< [11]
+        uint16_t BYTESEL : 2;          //!< [13:12]
+        uint16_t DISTESTWDOG : 1;      //!< [14]
+        uint16_t RESERVED1 : 1;        //!< [15]
+    } B;
+} hw_wdog_stctrlh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+//@{
+#define HW_WDOG_STCTRLH_ADDR     (REGS_WDOG_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_STCTRLH          (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR)
+#define HW_WDOG_STCTRLH_RD()     (HW_WDOG_STCTRLH.U)
+#define HW_WDOG_STCTRLH_WR(v)    (HW_WDOG_STCTRLH.U = (v))
+#define HW_WDOG_STCTRLH_SET(v)   (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() |  (v)))
+#define HW_WDOG_STCTRLH_CLR(v)   (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() & ~(v)))
+#define HW_WDOG_STCTRLH_TOG(v)   (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0 - WDOG is disabled.
+ * - 1 - WDOG is enabled.
+ */
+//@{
+#define BP_WDOG_STCTRLH_WDOGEN (0U)        //!< Bit position for WDOG_STCTRLH_WDOGEN.
+#define BM_WDOG_STCTRLH_WDOGEN (0x0001U)   //!< Bit mask for WDOG_STCTRLH_WDOGEN.
+#define BS_WDOG_STCTRLH_WDOGEN (1U)        //!< Bit field size in bits for WDOG_STCTRLH_WDOGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_WDOGEN field.
+#define BR_WDOG_STCTRLH_WDOGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN.
+#define BF_WDOG_STCTRLH_WDOGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WDOGEN), uint16_t) & BM_WDOG_STCTRLH_WDOGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDOGEN field to a new value.
+#define BW_WDOG_STCTRLH_WDOGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0 - WDOG clock sourced from LPO .
+ * - 1 - WDOG clock sourced from alternate clock source.
+ */
+//@{
+#define BP_WDOG_STCTRLH_CLKSRC (1U)        //!< Bit position for WDOG_STCTRLH_CLKSRC.
+#define BM_WDOG_STCTRLH_CLKSRC (0x0002U)   //!< Bit mask for WDOG_STCTRLH_CLKSRC.
+#define BS_WDOG_STCTRLH_CLKSRC (1U)        //!< Bit field size in bits for WDOG_STCTRLH_CLKSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_CLKSRC field.
+#define BR_WDOG_STCTRLH_CLKSRC (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC.
+#define BF_WDOG_STCTRLH_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_CLKSRC), uint16_t) & BM_WDOG_STCTRLH_CLKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKSRC field to a new value.
+#define BW_WDOG_STCTRLH_CLKSRC(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0 - WDOG time-out generates reset only.
+ * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
+ *     a reset.
+ */
+//@{
+#define BP_WDOG_STCTRLH_IRQRSTEN (2U)      //!< Bit position for WDOG_STCTRLH_IRQRSTEN.
+#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) //!< Bit mask for WDOG_STCTRLH_IRQRSTEN.
+#define BS_WDOG_STCTRLH_IRQRSTEN (1U)      //!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field.
+#define BR_WDOG_STCTRLH_IRQRSTEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN.
+#define BF_WDOG_STCTRLH_IRQRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_IRQRSTEN), uint16_t) & BM_WDOG_STCTRLH_IRQRSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRQRSTEN field to a new value.
+#define BW_WDOG_STCTRLH_IRQRSTEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0 - Windowing mode is disabled.
+ * - 1 - Windowing mode is enabled.
+ */
+//@{
+#define BP_WDOG_STCTRLH_WINEN (3U)         //!< Bit position for WDOG_STCTRLH_WINEN.
+#define BM_WDOG_STCTRLH_WINEN (0x0008U)    //!< Bit mask for WDOG_STCTRLH_WINEN.
+#define BS_WDOG_STCTRLH_WINEN (1U)         //!< Bit field size in bits for WDOG_STCTRLH_WINEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_WINEN field.
+#define BR_WDOG_STCTRLH_WINEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_WINEN.
+#define BF_WDOG_STCTRLH_WINEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WINEN), uint16_t) & BM_WDOG_STCTRLH_WINEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WINEN field to a new value.
+#define BW_WDOG_STCTRLH_WINEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0 - No further updates allowed to WDOG write-once registers.
+ * - 1 - WDOG write-once registers can be unlocked for updating.
+ */
+//@{
+#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U)   //!< Bit position for WDOG_STCTRLH_ALLOWUPDATE.
+#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) //!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE.
+#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U)   //!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field.
+#define BR_WDOG_STCTRLH_ALLOWUPDATE (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE.
+#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_ALLOWUPDATE), uint16_t) & BM_WDOG_STCTRLH_ALLOWUPDATE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ALLOWUPDATE field to a new value.
+#define BW_WDOG_STCTRLH_ALLOWUPDATE(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0 - WDOG is disabled in CPU Debug mode.
+ * - 1 - WDOG is enabled in CPU Debug mode.
+ */
+//@{
+#define BP_WDOG_STCTRLH_DBGEN (5U)         //!< Bit position for WDOG_STCTRLH_DBGEN.
+#define BM_WDOG_STCTRLH_DBGEN (0x0020U)    //!< Bit mask for WDOG_STCTRLH_DBGEN.
+#define BS_WDOG_STCTRLH_DBGEN (1U)         //!< Bit field size in bits for WDOG_STCTRLH_DBGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_DBGEN field.
+#define BR_WDOG_STCTRLH_DBGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_DBGEN.
+#define BF_WDOG_STCTRLH_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DBGEN), uint16_t) & BM_WDOG_STCTRLH_DBGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGEN field to a new value.
+#define BW_WDOG_STCTRLH_DBGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0 - WDOG is disabled in CPU Stop mode.
+ * - 1 - WDOG is enabled in CPU Stop mode.
+ */
+//@{
+#define BP_WDOG_STCTRLH_STOPEN (6U)        //!< Bit position for WDOG_STCTRLH_STOPEN.
+#define BM_WDOG_STCTRLH_STOPEN (0x0040U)   //!< Bit mask for WDOG_STCTRLH_STOPEN.
+#define BS_WDOG_STCTRLH_STOPEN (1U)        //!< Bit field size in bits for WDOG_STCTRLH_STOPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_STOPEN field.
+#define BR_WDOG_STCTRLH_STOPEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_STOPEN.
+#define BF_WDOG_STCTRLH_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_STOPEN), uint16_t) & BM_WDOG_STCTRLH_STOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPEN field to a new value.
+#define BW_WDOG_STCTRLH_STOPEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0 - WDOG is disabled in CPU Wait mode.
+ * - 1 - WDOG is enabled in CPU Wait mode.
+ */
+//@{
+#define BP_WDOG_STCTRLH_WAITEN (7U)        //!< Bit position for WDOG_STCTRLH_WAITEN.
+#define BM_WDOG_STCTRLH_WAITEN (0x0080U)   //!< Bit mask for WDOG_STCTRLH_WAITEN.
+#define BS_WDOG_STCTRLH_WAITEN (1U)        //!< Bit field size in bits for WDOG_STCTRLH_WAITEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_WAITEN field.
+#define BR_WDOG_STCTRLH_WAITEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_WAITEN.
+#define BF_WDOG_STCTRLH_WAITEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WAITEN), uint16_t) & BM_WDOG_STCTRLH_WAITEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAITEN field to a new value.
+#define BW_WDOG_STCTRLH_WAITEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+//@{
+#define BP_WDOG_STCTRLH_TESTWDOG (10U)     //!< Bit position for WDOG_STCTRLH_TESTWDOG.
+#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) //!< Bit mask for WDOG_STCTRLH_TESTWDOG.
+#define BS_WDOG_STCTRLH_TESTWDOG (1U)      //!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field.
+#define BR_WDOG_STCTRLH_TESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG.
+#define BF_WDOG_STCTRLH_TESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTWDOG), uint16_t) & BM_WDOG_STCTRLH_TESTWDOG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TESTWDOG field to a new value.
+#define BW_WDOG_STCTRLH_TESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
+ *     of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+//@{
+#define BP_WDOG_STCTRLH_TESTSEL (11U)      //!< Bit position for WDOG_STCTRLH_TESTSEL.
+#define BM_WDOG_STCTRLH_TESTSEL (0x0800U)  //!< Bit mask for WDOG_STCTRLH_TESTSEL.
+#define BS_WDOG_STCTRLH_TESTSEL (1U)       //!< Bit field size in bits for WDOG_STCTRLH_TESTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_TESTSEL field.
+#define BR_WDOG_STCTRLH_TESTSEL (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL.
+#define BF_WDOG_STCTRLH_TESTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTSEL), uint16_t) & BM_WDOG_STCTRLH_TESTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TESTSEL field to a new value.
+#define BW_WDOG_STCTRLH_TESTSEL(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 00 - Byte 0 selected
+ * - 01 - Byte 1 selected
+ * - 10 - Byte 2 selected
+ * - 11 - Byte 3 selected
+ */
+//@{
+#define BP_WDOG_STCTRLH_BYTESEL (12U)      //!< Bit position for WDOG_STCTRLH_BYTESEL.
+#define BM_WDOG_STCTRLH_BYTESEL (0x3000U)  //!< Bit mask for WDOG_STCTRLH_BYTESEL.
+#define BS_WDOG_STCTRLH_BYTESEL (2U)       //!< Bit field size in bits for WDOG_STCTRLH_BYTESEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_BYTESEL field.
+#define BR_WDOG_STCTRLH_BYTESEL (HW_WDOG_STCTRLH.B.BYTESEL)
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL.
+#define BF_WDOG_STCTRLH_BYTESEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_BYTESEL), uint16_t) & BM_WDOG_STCTRLH_BYTESEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BYTESEL field to a new value.
+#define BW_WDOG_STCTRLH_BYTESEL(v) (HW_WDOG_STCTRLH_WR((HW_WDOG_STCTRLH_RD() & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0 - WDOG functional test mode is not disabled.
+ * - 1 - WDOG functional test mode is disabled permanently until reset.
+ */
+//@{
+#define BP_WDOG_STCTRLH_DISTESTWDOG (14U)  //!< Bit position for WDOG_STCTRLH_DISTESTWDOG.
+#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) //!< Bit mask for WDOG_STCTRLH_DISTESTWDOG.
+#define BS_WDOG_STCTRLH_DISTESTWDOG (1U)   //!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field.
+#define BR_WDOG_STCTRLH_DISTESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG.
+#define BF_WDOG_STCTRLH_DISTESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DISTESTWDOG), uint16_t) & BM_WDOG_STCTRLH_DISTESTWDOG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DISTESTWDOG field to a new value.
+#define BW_WDOG_STCTRLH_DISTESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+typedef union _hw_wdog_stctrll
+{
+    uint16_t U;
+    struct _hw_wdog_stctrll_bitfields
+    {
+        uint16_t RESERVED0 : 15;       //!< [14:0]
+        uint16_t INTFLG : 1;           //!< [15]
+    } B;
+} hw_wdog_stctrll_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+//@{
+#define HW_WDOG_STCTRLL_ADDR     (REGS_WDOG_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_STCTRLL          (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR)
+#define HW_WDOG_STCTRLL_RD()     (HW_WDOG_STCTRLL.U)
+#define HW_WDOG_STCTRLL_WR(v)    (HW_WDOG_STCTRLL.U = (v))
+#define HW_WDOG_STCTRLL_SET(v)   (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() |  (v)))
+#define HW_WDOG_STCTRLL_CLR(v)   (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() & ~(v)))
+#define HW_WDOG_STCTRLL_TOG(v)   (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+//@{
+#define BP_WDOG_STCTRLL_INTFLG (15U)       //!< Bit position for WDOG_STCTRLL_INTFLG.
+#define BM_WDOG_STCTRLL_INTFLG (0x8000U)   //!< Bit mask for WDOG_STCTRLL_INTFLG.
+#define BS_WDOG_STCTRLL_INTFLG (1U)        //!< Bit field size in bits for WDOG_STCTRLL_INTFLG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLL_INTFLG field.
+#define BR_WDOG_STCTRLL_INTFLG (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLL_INTFLG.
+#define BF_WDOG_STCTRLL_INTFLG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLL_INTFLG), uint16_t) & BM_WDOG_STCTRLL_INTFLG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTFLG field to a new value.
+#define BW_WDOG_STCTRLL_INTFLG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TOVALH - Watchdog Time-out Value Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+typedef union _hw_wdog_tovalh
+{
+    uint16_t U;
+    struct _hw_wdog_tovalh_bitfields
+    {
+        uint16_t TOVALHIGH : 16;       //!< [15:0]
+    } B;
+} hw_wdog_tovalh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+//@{
+#define HW_WDOG_TOVALH_ADDR      (REGS_WDOG_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TOVALH           (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR)
+#define HW_WDOG_TOVALH_RD()      (HW_WDOG_TOVALH.U)
+#define HW_WDOG_TOVALH_WR(v)     (HW_WDOG_TOVALH.U = (v))
+#define HW_WDOG_TOVALH_SET(v)    (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() |  (v)))
+#define HW_WDOG_TOVALH_CLR(v)    (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() & ~(v)))
+#define HW_WDOG_TOVALH_TOG(v)    (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TOVALH bitfields
+ */
+
+/*!
+ * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
+ *
+ * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
+ * timer. It is defined in terms of cycles of the watchdog clock.
+ */
+//@{
+#define BP_WDOG_TOVALH_TOVALHIGH (0U)      //!< Bit position for WDOG_TOVALH_TOVALHIGH.
+#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) //!< Bit mask for WDOG_TOVALH_TOVALHIGH.
+#define BS_WDOG_TOVALH_TOVALHIGH (16U)     //!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field.
+#define BR_WDOG_TOVALH_TOVALHIGH (HW_WDOG_TOVALH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH.
+#define BF_WDOG_TOVALH_TOVALHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALH_TOVALHIGH), uint16_t) & BM_WDOG_TOVALH_TOVALHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOVALHIGH field to a new value.
+#define BW_WDOG_TOVALH_TOVALHIGH(v) (HW_WDOG_TOVALH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+typedef union _hw_wdog_tovall
+{
+    uint16_t U;
+    struct _hw_wdog_tovall_bitfields
+    {
+        uint16_t TOVALLOW : 16;        //!< [15:0]
+    } B;
+} hw_wdog_tovall_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+//@{
+#define HW_WDOG_TOVALL_ADDR      (REGS_WDOG_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TOVALL           (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR)
+#define HW_WDOG_TOVALL_RD()      (HW_WDOG_TOVALL.U)
+#define HW_WDOG_TOVALL_WR(v)     (HW_WDOG_TOVALL.U = (v))
+#define HW_WDOG_TOVALL_SET(v)    (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() |  (v)))
+#define HW_WDOG_TOVALL_CLR(v)    (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() & ~(v)))
+#define HW_WDOG_TOVALL_TOG(v)    (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TOVALL bitfields
+ */
+
+/*!
+ * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
+ *
+ * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
+ * timer. It is defined in terms of cycles of the watchdog clock.
+ */
+//@{
+#define BP_WDOG_TOVALL_TOVALLOW (0U)       //!< Bit position for WDOG_TOVALL_TOVALLOW.
+#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU)  //!< Bit mask for WDOG_TOVALL_TOVALLOW.
+#define BS_WDOG_TOVALL_TOVALLOW (16U)      //!< Bit field size in bits for WDOG_TOVALL_TOVALLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TOVALL_TOVALLOW field.
+#define BR_WDOG_TOVALL_TOVALLOW (HW_WDOG_TOVALL.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW.
+#define BF_WDOG_TOVALL_TOVALLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALL_TOVALLOW), uint16_t) & BM_WDOG_TOVALL_TOVALLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOVALLOW field to a new value.
+#define BW_WDOG_TOVALL_TOVALLOW(v) (HW_WDOG_TOVALL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_WINH - Watchdog Window Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+typedef union _hw_wdog_winh
+{
+    uint16_t U;
+    struct _hw_wdog_winh_bitfields
+    {
+        uint16_t WINHIGH : 16;         //!< [15:0]
+    } B;
+} hw_wdog_winh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+//@{
+#define HW_WDOG_WINH_ADDR        (REGS_WDOG_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_WINH             (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR)
+#define HW_WDOG_WINH_RD()        (HW_WDOG_WINH.U)
+#define HW_WDOG_WINH_WR(v)       (HW_WDOG_WINH.U = (v))
+#define HW_WDOG_WINH_SET(v)      (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() |  (v)))
+#define HW_WDOG_WINH_CLR(v)      (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() & ~(v)))
+#define HW_WDOG_WINH_TOG(v)      (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_WINH bitfields
+ */
+
+/*!
+ * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
+ *
+ * Defines the upper 16 bits of the 32-bit window for the windowed mode of
+ * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
+ * In this mode, the watchdog can be refreshed only when the timer has reached a
+ * value greater than or equal to this window length. A refresh outside this
+ * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
+ * system.
+ */
+//@{
+#define BP_WDOG_WINH_WINHIGH (0U)          //!< Bit position for WDOG_WINH_WINHIGH.
+#define BM_WDOG_WINH_WINHIGH (0xFFFFU)     //!< Bit mask for WDOG_WINH_WINHIGH.
+#define BS_WDOG_WINH_WINHIGH (16U)         //!< Bit field size in bits for WDOG_WINH_WINHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_WINH_WINHIGH field.
+#define BR_WDOG_WINH_WINHIGH (HW_WDOG_WINH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_WINH_WINHIGH.
+#define BF_WDOG_WINH_WINHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINH_WINHIGH), uint16_t) & BM_WDOG_WINH_WINHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WINHIGH field to a new value.
+#define BW_WDOG_WINH_WINHIGH(v) (HW_WDOG_WINH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_WINL - Watchdog Window Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+typedef union _hw_wdog_winl
+{
+    uint16_t U;
+    struct _hw_wdog_winl_bitfields
+    {
+        uint16_t WINLOW : 16;          //!< [15:0]
+    } B;
+} hw_wdog_winl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+//@{
+#define HW_WDOG_WINL_ADDR        (REGS_WDOG_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_WINL             (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR)
+#define HW_WDOG_WINL_RD()        (HW_WDOG_WINL.U)
+#define HW_WDOG_WINL_WR(v)       (HW_WDOG_WINL.U = (v))
+#define HW_WDOG_WINL_SET(v)      (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() |  (v)))
+#define HW_WDOG_WINL_CLR(v)      (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() & ~(v)))
+#define HW_WDOG_WINL_TOG(v)      (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_WINL bitfields
+ */
+
+/*!
+ * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
+ *
+ * Defines the lower 16 bits of the 32-bit window for the windowed mode of
+ * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
+ * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
+ * reaches a value greater than or equal to this window length value. A refresh
+ * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
+ * then resets the system.
+ */
+//@{
+#define BP_WDOG_WINL_WINLOW  (0U)          //!< Bit position for WDOG_WINL_WINLOW.
+#define BM_WDOG_WINL_WINLOW  (0xFFFFU)     //!< Bit mask for WDOG_WINL_WINLOW.
+#define BS_WDOG_WINL_WINLOW  (16U)         //!< Bit field size in bits for WDOG_WINL_WINLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_WINL_WINLOW field.
+#define BR_WDOG_WINL_WINLOW  (HW_WDOG_WINL.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_WINL_WINLOW.
+#define BF_WDOG_WINL_WINLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINL_WINLOW), uint16_t) & BM_WDOG_WINL_WINLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WINLOW field to a new value.
+#define BW_WDOG_WINL_WINLOW(v) (HW_WDOG_WINL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_REFRESH - Watchdog Refresh register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+typedef union _hw_wdog_refresh
+{
+    uint16_t U;
+    struct _hw_wdog_refresh_bitfields
+    {
+        uint16_t WDOGREFRESH : 16;     //!< [15:0]
+    } B;
+} hw_wdog_refresh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+//@{
+#define HW_WDOG_REFRESH_ADDR     (REGS_WDOG_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_REFRESH          (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR)
+#define HW_WDOG_REFRESH_RD()     (HW_WDOG_REFRESH.U)
+#define HW_WDOG_REFRESH_WR(v)    (HW_WDOG_REFRESH.U = (v))
+#define HW_WDOG_REFRESH_SET(v)   (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() |  (v)))
+#define HW_WDOG_REFRESH_CLR(v)   (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() & ~(v)))
+#define HW_WDOG_REFRESH_TOG(v)   (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_REFRESH bitfields
+ */
+
+/*!
+ * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
+ *
+ * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
+ * bus clock cycles written to this register refreshes the WDOG and prevents it
+ * from resetting the system. Writing a value other than the above mentioned
+ * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
+ * IRQRSTEN is set, it interrupts and then resets the system.
+ */
+//@{
+#define BP_WDOG_REFRESH_WDOGREFRESH (0U)   //!< Bit position for WDOG_REFRESH_WDOGREFRESH.
+#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) //!< Bit mask for WDOG_REFRESH_WDOGREFRESH.
+#define BS_WDOG_REFRESH_WDOGREFRESH (16U)  //!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field.
+#define BR_WDOG_REFRESH_WDOGREFRESH (HW_WDOG_REFRESH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH.
+#define BF_WDOG_REFRESH_WDOGREFRESH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_REFRESH_WDOGREFRESH), uint16_t) & BM_WDOG_REFRESH_WDOGREFRESH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDOGREFRESH field to a new value.
+#define BW_WDOG_REFRESH_WDOGREFRESH(v) (HW_WDOG_REFRESH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_UNLOCK - Watchdog Unlock register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+typedef union _hw_wdog_unlock
+{
+    uint16_t U;
+    struct _hw_wdog_unlock_bitfields
+    {
+        uint16_t WDOGUNLOCK : 16;      //!< [15:0]
+    } B;
+} hw_wdog_unlock_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+//@{
+#define HW_WDOG_UNLOCK_ADDR      (REGS_WDOG_BASE + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_UNLOCK           (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR)
+#define HW_WDOG_UNLOCK_RD()      (HW_WDOG_UNLOCK.U)
+#define HW_WDOG_UNLOCK_WR(v)     (HW_WDOG_UNLOCK.U = (v))
+#define HW_WDOG_UNLOCK_SET(v)    (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() |  (v)))
+#define HW_WDOG_UNLOCK_CLR(v)    (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() & ~(v)))
+#define HW_WDOG_UNLOCK_TOG(v)    (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_UNLOCK bitfields
+ */
+
+/*!
+ * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
+ *
+ * Writing the unlock sequence values to this register to makes the watchdog
+ * write-once registers writable again. The required unlock sequence is 0xC520
+ * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
+ * window equal in length to the WCT within which you can update the registers.
+ * Writing a value other than the above mentioned sequence or if the sequence is
+ * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
+ * and then resets the system. The unlock sequence is effective only if
+ * ALLOWUPDATE is set.
+ */
+//@{
+#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U)     //!< Bit position for WDOG_UNLOCK_WDOGUNLOCK.
+#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) //!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK.
+#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U)    //!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field.
+#define BR_WDOG_UNLOCK_WDOGUNLOCK (HW_WDOG_UNLOCK.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK.
+#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_UNLOCK_WDOGUNLOCK), uint16_t) & BM_WDOG_UNLOCK_WDOGUNLOCK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDOGUNLOCK field to a new value.
+#define BW_WDOG_UNLOCK_WDOGUNLOCK(v) (HW_WDOG_UNLOCK_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TMROUTH - Watchdog Timer Output Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_wdog_tmrouth
+{
+    uint16_t U;
+    struct _hw_wdog_tmrouth_bitfields
+    {
+        uint16_t TIMEROUTHIGH : 16;    //!< [15:0]
+    } B;
+} hw_wdog_tmrouth_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+//@{
+#define HW_WDOG_TMROUTH_ADDR     (REGS_WDOG_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TMROUTH          (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR)
+#define HW_WDOG_TMROUTH_RD()     (HW_WDOG_TMROUTH.U)
+#define HW_WDOG_TMROUTH_WR(v)    (HW_WDOG_TMROUTH.U = (v))
+#define HW_WDOG_TMROUTH_SET(v)   (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() |  (v)))
+#define HW_WDOG_TMROUTH_CLR(v)   (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() & ~(v)))
+#define HW_WDOG_TMROUTH_TOG(v)   (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TMROUTH bitfields
+ */
+
+/*!
+ * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
+ *
+ * Shows the value of the upper 16 bits of the watchdog timer.
+ */
+//@{
+#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U)  //!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH.
+#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) //!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH.
+#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) //!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field.
+#define BR_WDOG_TMROUTH_TIMEROUTHIGH (HW_WDOG_TMROUTH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH.
+#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTH_TIMEROUTHIGH), uint16_t) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMEROUTHIGH field to a new value.
+#define BW_WDOG_TMROUTH_TIMEROUTHIGH(v) (HW_WDOG_TMROUTH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+typedef union _hw_wdog_tmroutl
+{
+    uint16_t U;
+    struct _hw_wdog_tmroutl_bitfields
+    {
+        uint16_t TIMEROUTLOW : 16;     //!< [15:0]
+    } B;
+} hw_wdog_tmroutl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+//@{
+#define HW_WDOG_TMROUTL_ADDR     (REGS_WDOG_BASE + 0x12U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TMROUTL          (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR)
+#define HW_WDOG_TMROUTL_RD()     (HW_WDOG_TMROUTL.U)
+#define HW_WDOG_TMROUTL_WR(v)    (HW_WDOG_TMROUTL.U = (v))
+#define HW_WDOG_TMROUTL_SET(v)   (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() |  (v)))
+#define HW_WDOG_TMROUTL_CLR(v)   (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() & ~(v)))
+#define HW_WDOG_TMROUTL_TOG(v)   (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TMROUTL bitfields
+ */
+
+/*!
+ * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
+ *
+ * Shows the value of the lower 16 bits of the watchdog timer.
+ */
+//@{
+#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U)   //!< Bit position for WDOG_TMROUTL_TIMEROUTLOW.
+#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) //!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW.
+#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U)  //!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field.
+#define BR_WDOG_TMROUTL_TIMEROUTLOW (HW_WDOG_TMROUTL.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW.
+#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTL_TIMEROUTLOW), uint16_t) & BM_WDOG_TMROUTL_TIMEROUTLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMEROUTLOW field to a new value.
+#define BW_WDOG_TMROUTL_TIMEROUTLOW(v) (HW_WDOG_TMROUTL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_RSTCNT - Watchdog Reset Count register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_wdog_rstcnt
+{
+    uint16_t U;
+    struct _hw_wdog_rstcnt_bitfields
+    {
+        uint16_t RSTCNT : 16;          //!< [15:0]
+    } B;
+} hw_wdog_rstcnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+//@{
+#define HW_WDOG_RSTCNT_ADDR      (REGS_WDOG_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_RSTCNT           (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR)
+#define HW_WDOG_RSTCNT_RD()      (HW_WDOG_RSTCNT.U)
+#define HW_WDOG_RSTCNT_WR(v)     (HW_WDOG_RSTCNT.U = (v))
+#define HW_WDOG_RSTCNT_SET(v)    (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() |  (v)))
+#define HW_WDOG_RSTCNT_CLR(v)    (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() & ~(v)))
+#define HW_WDOG_RSTCNT_TOG(v)    (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_RSTCNT bitfields
+ */
+
+/*!
+ * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
+ *
+ * Counts the number of times the watchdog resets the system. This register is
+ * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
+ * the contents of this register.
+ */
+//@{
+#define BP_WDOG_RSTCNT_RSTCNT (0U)         //!< Bit position for WDOG_RSTCNT_RSTCNT.
+#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU)    //!< Bit mask for WDOG_RSTCNT_RSTCNT.
+#define BS_WDOG_RSTCNT_RSTCNT (16U)        //!< Bit field size in bits for WDOG_RSTCNT_RSTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_RSTCNT_RSTCNT field.
+#define BR_WDOG_RSTCNT_RSTCNT (HW_WDOG_RSTCNT.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT.
+#define BF_WDOG_RSTCNT_RSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_RSTCNT_RSTCNT), uint16_t) & BM_WDOG_RSTCNT_RSTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTCNT field to a new value.
+#define BW_WDOG_RSTCNT_RSTCNT(v) (HW_WDOG_RSTCNT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_PRESC - Watchdog Prescaler register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+typedef union _hw_wdog_presc
+{
+    uint16_t U;
+    struct _hw_wdog_presc_bitfields
+    {
+        uint16_t RESERVED0 : 8;        //!< [7:0]
+        uint16_t PRESCVAL : 3;         //!< [10:8]
+        uint16_t RESERVED1 : 5;        //!< [15:11]
+    } B;
+} hw_wdog_presc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+//@{
+#define HW_WDOG_PRESC_ADDR       (REGS_WDOG_BASE + 0x16U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_PRESC            (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR)
+#define HW_WDOG_PRESC_RD()       (HW_WDOG_PRESC.U)
+#define HW_WDOG_PRESC_WR(v)      (HW_WDOG_PRESC.U = (v))
+#define HW_WDOG_PRESC_SET(v)     (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() |  (v)))
+#define HW_WDOG_PRESC_CLR(v)     (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() & ~(v)))
+#define HW_WDOG_PRESC_TOG(v)     (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() ^  (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+//@{
+#define BP_WDOG_PRESC_PRESCVAL (8U)        //!< Bit position for WDOG_PRESC_PRESCVAL.
+#define BM_WDOG_PRESC_PRESCVAL (0x0700U)   //!< Bit mask for WDOG_PRESC_PRESCVAL.
+#define BS_WDOG_PRESC_PRESCVAL (3U)        //!< Bit field size in bits for WDOG_PRESC_PRESCVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_PRESC_PRESCVAL field.
+#define BR_WDOG_PRESC_PRESCVAL (HW_WDOG_PRESC.B.PRESCVAL)
+#endif
+
+//! @brief Format value for bitfield WDOG_PRESC_PRESCVAL.
+#define BF_WDOG_PRESC_PRESCVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_PRESC_PRESCVAL), uint16_t) & BM_WDOG_PRESC_PRESCVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCVAL field to a new value.
+#define BW_WDOG_PRESC_PRESCVAL(v) (HW_WDOG_PRESC_WR((HW_WDOG_PRESC_RD() & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_wdog_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All WDOG module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_wdog
+{
+    __IO hw_wdog_stctrlh_t STCTRLH;        //!< [0x0] Watchdog Status and Control Register High
+    __IO hw_wdog_stctrll_t STCTRLL;        //!< [0x2] Watchdog Status and Control Register Low
+    __IO hw_wdog_tovalh_t TOVALH;          //!< [0x4] Watchdog Time-out Value Register High
+    __IO hw_wdog_tovall_t TOVALL;          //!< [0x6] Watchdog Time-out Value Register Low
+    __IO hw_wdog_winh_t WINH;              //!< [0x8] Watchdog Window Register High
+    __IO hw_wdog_winl_t WINL;              //!< [0xA] Watchdog Window Register Low
+    __IO hw_wdog_refresh_t REFRESH;        //!< [0xC] Watchdog Refresh register
+    __IO hw_wdog_unlock_t UNLOCK;          //!< [0xE] Watchdog Unlock register
+    __IO hw_wdog_tmrouth_t TMROUTH;        //!< [0x10] Watchdog Timer Output Register High
+    __IO hw_wdog_tmroutl_t TMROUTL;        //!< [0x12] Watchdog Timer Output Register Low
+    __IO hw_wdog_rstcnt_t RSTCNT;          //!< [0x14] Watchdog Reset Count register
+    __IO hw_wdog_presc_t PRESC;            //!< [0x16] Watchdog Prescaler register
+} hw_wdog_t;
+#pragma pack()
+
+//! @brief Macro to access all WDOG registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_WDOG</code>.
+#define HW_WDOG        (*(hw_wdog_t *) REGS_WDOG_BASE)
+#endif
+
+#endif // __HW_WDOG_REGISTERS_H__
+// v22/130726/0.9
+// EOF
diff --git a/bsp/k64Fxxxx/device/MK64F12/regs.h b/bsp/k64Fxxxx/device/MK64F12/regs.h
new file mode 100644
index 0000000000..21951876bb
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/regs.h
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+#ifndef _REGS_H
+#define _REGS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+//
+// define base address of the register block only if it is not already
+// defined, which allows the compiler to override at build time for
+// users who've mapped their registers to locations other than the
+// physical location
+//
+
+#include <stdint.h>
+
+#ifndef REGS_BASE
+#define REGS_BASE 0x00000000
+#endif
+
+//
+// common register types
+//
+
+#ifndef __LANGUAGE_ASM__
+typedef unsigned char reg8_t;
+typedef unsigned short reg16_t;
+typedef unsigned int reg32_t;
+#endif
+
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+#define BME_AND_MASK	(1<<26)
+#define BME_OR_MASK		(1<<27)
+#define BME_XOR_MASK	(3<<26)
+#define BME_BFI_MASK(BIT,WIDTH)		(1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
+#define BME_UBFX_MASK(BIT,WIDTH)	(1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+//
+// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
+// used to simplify macro definitions in the module register headers.
+//
+#ifndef __REG_VALUE_TYPE
+    #ifndef __LANGUAGE_ASM__
+        #define __REG_VALUE_TYPE(v, t) ((t)(v))
+    #else
+        #define __REG_VALUE_TYPE(v, t) (v)
+    #endif
+#endif
+
+//
+// macros for single instance registers
+//
+
+#define BF_SET(reg, field)       HW_##reg##_SET(BM_##reg##_##field)
+#define BF_CLR(reg, field)       HW_##reg##_CLR(BM_##reg##_##field)
+#define BF_TOG(reg, field)       HW_##reg##_TOG(BM_##reg##_##field)
+
+#define BF_SETV(reg, field, v)   HW_##reg##_SET(BF_##reg##_##field(v))
+#define BF_CLRV(reg, field, v)   HW_##reg##_CLR(BF_##reg##_##field(v))
+#define BF_TOGV(reg, field, v)   HW_##reg##_TOG(BF_##reg##_##field(v))
+
+#define BV_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RD(reg, field)        HW_##reg.B.field
+#define BF_WR(reg, field, v)     BW_##reg##_##field(v)
+
+#define BF_CS1(reg, f1, v1)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1)))
+
+#define BF_CS2(reg, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BF_CS3(reg, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+//
+// macros for multiple instance registers
+//
+
+#define BF_SETn(reg, n, field)       HW_##reg##_SET(n, BM_##reg##_##field)
+#define BF_CLRn(reg, n, field)       HW_##reg##_CLR(n, BM_##reg##_##field)
+#define BF_TOGn(reg, n, field)       HW_##reg##_TOG(n, BM_##reg##_##field)
+
+#define BF_SETVn(reg, n, field, v)   HW_##reg##_SET(n, BF_##reg##_##field(v))
+#define BF_CLRVn(reg, n, field, v)   HW_##reg##_CLR(n, BF_##reg##_##field(v))
+#define BF_TOGVn(reg, n, field, v)   HW_##reg##_TOG(n, BF_##reg##_##field(v))
+
+#define BV_FLDn(reg, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VALn(reg, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RDn(reg, n, field)        HW_##reg(n).B.field
+#define BF_WRn(reg, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BF_CS1n(reg, n, f1, v1)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
+
+#define BF_CS2n(reg, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+//
+// macros for single instance MULTI-BLOCK registers
+//
+
+#define BFn_SET(reg, blk, field)       HW_##reg##_SET(blk, BM_##reg##_##field)
+#define BFn_CLR(reg, blk, field)       HW_##reg##_CLR(blk, BM_##reg##_##field)
+#define BFn_TOG(reg, blk, field)       HW_##reg##_TOG(blk, BM_##reg##_##field)
+
+#define BFn_SETV(reg, blk, field, v)   HW_##reg##_SET(blk, BF_##reg##_##field(v))
+#define BFn_CLRV(reg, blk, field, v)   HW_##reg##_CLR(blk, BF_##reg##_##field(v))
+#define BFn_TOGV(reg, blk, field, v)   HW_##reg##_TOG(blk, BF_##reg##_##field(v))
+
+#define BVn_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RD(reg, blk, field)        HW_##reg(blk).B.field
+#define BFn_WR(reg, blk, field, v)     BW_##reg##_##field(blk, v)
+
+#define BFn_CS1(reg, blk, f1, v1)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
+
+#define BFn_CS2(reg, blk, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+//
+// macros for MULTI-BLOCK multiple instance registers
+//
+
+#define BFn_SETn(reg, blk, n, field)       HW_##reg##_SET(blk, n, BM_##reg##_##field)
+#define BFn_CLRn(reg, blk, n, field)       HW_##reg##_CLR(blk, n, BM_##reg##_##field)
+#define BFn_TOGn(reg, blk, n, field)       HW_##reg##_TOG(blk, n, BM_##reg##_##field)
+
+#define BFn_SETVn(reg, blk, n, field, v)   HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
+#define BFn_CLRVn(reg, blk, n, field, v)   HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
+#define BFn_TOGVn(reg, blk, n, field, v)   HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
+
+#define BVn_FLDn(reg, blk, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VALn(reg, blk, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RDn(reg, blk, n, field)        HW_##reg(n).B.field
+#define BFn_WRn(reg, blk, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BFn_CS1n(reg, blk, n, f1, v1)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
+
+#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+#endif // _REGS_H
+
+////////////////////////////////////////////////////////////////////////////////
diff --git a/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c b/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c
new file mode 100644
index 0000000000..21d23f3ade
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c
@@ -0,0 +1,422 @@
+/*
+** ###################################################################
+**     Processor:           MK64FN1M0VMD12
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.1, July 2013
+**     Version:             rev. 2.1, 2013-10-29
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2013 Freescale, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-29)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.1
+ * @date 2013-10-29
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MK64F12.h"
+
+#define DISABLE_WDOG    1
+
+#ifndef CLOCK_SETUP
+#define CLOCK_SETUP     4
+#endif
+/* Predefined clock setups
+   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+         Default  part configuration.
+         Reference clock source for MCG module is the slow internal clock source 32.768kHz
+         Core clock = 20.97MHz, BusClock = 20.97MHz
+   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+         Maximum achievable clock frequency configuration.
+         Reference clock source for MCG module is an external clock source 50MHz
+         Core clock = 120MHz, BusClock = 60MHz
+   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
+         Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
+         The clock settings is ready for Very Low Power Run mode.
+         Core clock = 4MHz, BusClock = 4MHz
+   3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+         Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
+         The clock settings is ready for Very Low Power Run mode.
+         Core clock = 32.768kHz, BusClock = 32.768kHz
+   4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+         USB clock setup
+         USB clock divider is set for USB to receive 48MHz input clock.
+         Reference clock source for MCG module is an external clock source 50MHz
+         USB clock divider is set for USB to receive 48MHz input clock.
+         Core clock = 120MHz, BusClock = 60MHz
+*/
+
+/*----------------------------------------------------------------------------
+  Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+    #define CPU_XTAL_CLK_HZ                 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            20485760u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+    #define CPU_XTAL_CLK_HZ                 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            120000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+    #define CPU_XTAL_CLK_HZ                 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            4000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 3)
+    #define CPU_XTAL_CLK_HZ                 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            32768u /* Default System clock value */
+#elif (CLOCK_SETUP == 4)
+    #define CPU_XTAL_CLK_HZ                 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            120000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 4) */
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* Disable the WDOG module */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+
+   /*
+   * Release hold with ACKISO:  Only has an effect if recovering from VLLSx.
+   * if ACKISO is set you must clear ackiso before initializing the PLL
+   * if osc enabled in low power modes - enable it first before ack
+   */
+  if (PMC->REGSC &  PMC_REGSC_ACKISO_MASK)
+  {
+      PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
+  }
+
+#if (CLOCK_SETUP == 0)
+  /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
+                SIM_CLKDIV1_OUTDIV2(0x00) |
+                SIM_CLKDIV1_OUTDIV3(0x01) |
+                SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
+  /* SIM->SOPT2: PLLFLLSEL=0 */
+  SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
+  /* SIM->SOPT1: OSC32KSEL=3 */
+  SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
+  /* Switch to FEI Mode */
+  /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = MCG_C1_CLKS(0x00) |
+           MCG_C1_FRDIV(0x00) |
+           MCG_C1_IREFS_MASK |
+           MCG_C1_IRCLKEN_MASK;
+  /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = MCG_C2_RANGE0(0x00);
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+  /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC->CR = OSC_CR_ERCLKEN_MASK;
+  /* MCG->C7: OSCSEL=0 */
+  MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
+  /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  MCG->C5 = MCG_C5_PRDIV0(0x00);
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = MCG_C6_VDIV0(0x00);
+  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
+  }
+#elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4)
+  /* SIM->SCGC5: PORTA=1 */
+  SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
+  /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
+                SIM_CLKDIV1_OUTDIV2(0x01) |
+                SIM_CLKDIV1_OUTDIV3(0x02) |
+                SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
+  /* SIM->SOPT2: PLLFLLSEL=1 */
+  SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
+  /* SIM->SOPT1: OSC32KSEL=3 */
+  SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
+  /* PORTA->PCR[18]: ISF=0,MUX=0 */
+  PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  /* Switch to FBE Mode */
+  /* MCG->C2: LOCRE0=0,?=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = MCG_C2_RANGE0(0x02);
+  /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC->CR = OSC_CR_ERCLKEN_MASK;
+  /* MCG->C7: OSCSEL=0 */
+  MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
+  /* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x07) | MCG_C1_IRCLKEN_MASK);
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+  /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  MCG->C5 = MCG_C5_PRDIV0(0x13);
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */
+  MCG->C6 = MCG_C6_VDIV0(0x18);
+  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to PBE Mode */
+  /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18));
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+  }
+  /* Switch to PEE Mode */
+  /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);
+  while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
+  }
+  #if (CLOCK_SETUP == 4)
+  /* Set USB input clock to 48MHz  */
+  /* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */
+  SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)(
+                 SIM_CLKDIV2_USBDIV(0x03)
+                )) | (uint32_t)(
+                 SIM_CLKDIV2_USBDIV(0x04) |
+                 SIM_CLKDIV2_USBFRAC_MASK
+                ));
+  #endif
+#elif (CLOCK_SETUP == 2)
+  /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
+                SIM_CLKDIV1_OUTDIV2(0x00) |
+                SIM_CLKDIV1_OUTDIV3(0x00) |
+                SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
+  /* SIM->SOPT2: PLLFLLSEL=0 */
+  SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
+  /* SIM->SOPT1: OSC32KSEL=3 */
+  SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
+  /* MCG->SC: FCRDIV=0 */
+  MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
+  /* Switch to FBI Mode */
+  /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = MCG_C1_CLKS(0x01) |
+           MCG_C1_FRDIV(0x00) |
+           MCG_C1_IREFS_MASK |
+           MCG_C1_IRCLKEN_MASK;
+  /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
+  MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+  /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC->CR = OSC_CR_ERCLKEN_MASK;
+  /* MCG->C7: OSCSEL=0 */
+  MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
+  /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  MCG->C5 = MCG_C5_PRDIV0(0x00);
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = MCG_C6_VDIV0(0x00);
+  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x04U) {    /* Wait until internal reference clock is selected as MCG output */
+  }
+  /* Switch to BLPI Mode */
+  /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
+  MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
+  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+  }
+  while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
+  }
+#elif (CLOCK_SETUP == 3)
+  /* SIM->SCGC6: RTC=1 */
+  SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
+  if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
+    /* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+    RTC->CR &= (uint32_t)~(uint32_t)(
+               RTC_CR_SC2P_MASK |
+               RTC_CR_SC4P_MASK |
+               RTC_CR_SC8P_MASK |
+               RTC_CR_SC16P_MASK
+              );
+    /* RTC->CR: OSCE=1 */
+    RTC->CR |= RTC_CR_OSCE_MASK;
+    /* RTC->CR: CLKO=0 */
+    RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
+  }
+    /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
+                SIM_CLKDIV1_OUTDIV2(0x00) |
+                SIM_CLKDIV1_OUTDIV3(0x00) |
+                SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */
+  /* SIM->SOPT1: OSC32KSEL=2 */
+  SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)(
+               SIM_SOPT1_OSC32KSEL(0x01)
+              )) | (uint32_t)(
+               SIM_SOPT1_OSC32KSEL(0x02)
+              ));                      /* System oscillator drives 32 kHz clock for various peripherals */
+  /* Switch to FBE Mode */
+  /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = MCG_C2_RANGE0(0x00);
+  /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC->CR = OSC_CR_ERCLKEN_MASK;
+  /* MCG->C7: OSCSEL=1 */
+  MCG->C7 |= MCG_C7_OSCSEL_MASK;
+  /* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+  /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  MCG->C5 = MCG_C5_PRDIV0(0x00);
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = MCG_C6_VDIV0(0x00);
+  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to BLPE Mode */
+  /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
+  MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK);
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
+  uint8_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+        /* External reference clock is selected */
+        if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+          MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
+        } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
+        } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+        Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
+        if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+          MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
+        } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x0u:
+          MCGOUTClock *= 640u;
+          break;
+        case 0x20u:
+          MCGOUTClock *= 1280u;
+          break;
+        case 0x40u:
+          MCGOUTClock *= 1920u;
+          break;
+        case 0x60u:
+          MCGOUTClock *= 2560u;
+          break;
+        case 0x80u:
+          MCGOUTClock *= 732u;
+          break;
+        case 0xA0u:
+          MCGOUTClock *= 1464u;
+          break;
+        case 0xC0u:
+          MCGOUTClock *= 2197u;
+          break;
+        case 0xE0u:
+          MCGOUTClock *= 2929u;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+      /* PLL is selected */
+      Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
+      Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+      MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+    /* External reference clock is selected */
+    if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+      MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
+    } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
+    } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h b/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h
new file mode 100644
index 0000000000..df54846298
--- /dev/null
+++ b/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h
@@ -0,0 +1,92 @@
+/*
+** ###################################################################
+**     Processor:           MK64FN1M0VMD12
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.1, July 2013
+**     Version:             rev. 2.1, 2013-10-29
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2013 Freescale, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-29)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.1
+ * @date 2013-10-29
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/bsp/k64Fxxxx/device/SConscript b/bsp/k64Fxxxx/device/SConscript
new file mode 100644
index 0000000000..e196b1595a
--- /dev/null
+++ b/bsp/k64Fxxxx/device/SConscript
@@ -0,0 +1,24 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+
+src = Glob('MK64F12/*.c')
+
+#add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+     src = src + ['TOOLCHAIN_GCC_ARM/startup_MK64F12.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+     src = src + ['TOOLCHAIN_ARM_STD/startup_MK64F12.s']
+# elif rtconfig.CROSS_TOOL == 'iar':
+
+path = [cwd, cwd + '/MK64F12']
+
+#CPPDEFINES = ['']
+group = DefineGroup('Device', src, depend = [''], CPPPATH = path)
+#CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/k64Fxxxx/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s b/bsp/k64Fxxxx/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s
new file mode 100644
index 0000000000..3959f194d8
--- /dev/null
+++ b/bsp/k64Fxxxx/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s
@@ -0,0 +1,732 @@
+;/*****************************************************************************
+; * @file:    startup_MK70F12.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; *           MK70F12
+; * @version: 1.5
+; * @date:    2012-10-19
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     HardFault_Handler  ; Hard Fault Handler
+                DCD     MemManage_Handler  ; MPU Fault Handler
+                DCD     BusFault_Handler  ; Bus Fault Handler
+                DCD     UsageFault_Handler  ; Usage Fault Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     DebugMon_Handler  ; Debug Monitor Handler
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DMA0_IRQHandler  ; DMA Channel 0 Transfer Complete
+                DCD     DMA1_IRQHandler  ; DMA Channel 1 Transfer Complete
+                DCD     DMA2_IRQHandler  ; DMA Channel 2 Transfer Complete
+                DCD     DMA3_IRQHandler  ; DMA Channel 3 Transfer Complete
+                DCD     DMA4_IRQHandler  ; DMA Channel 4 Transfer Complete
+                DCD     DMA5_IRQHandler  ; DMA Channel 5 Transfer Complete
+                DCD     DMA6_IRQHandler  ; DMA Channel 6 Transfer Complete
+                DCD     DMA7_IRQHandler  ; DMA Channel 7 Transfer Complete
+                DCD     DMA8_IRQHandler  ; DMA Channel 8 Transfer Complete
+                DCD     DMA9_IRQHandler  ; DMA Channel 9 Transfer Complete
+                DCD     DMA10_IRQHandler  ; DMA Channel 10 Transfer Complete
+                DCD     DMA11_IRQHandler  ; DMA Channel 11 Transfer Complete
+                DCD     DMA12_IRQHandler  ; DMA Channel 12 Transfer Complete
+                DCD     DMA13_IRQHandler  ; DMA Channel 13 Transfer Complete
+                DCD     DMA14_IRQHandler  ; DMA Channel 14 Transfer Complete
+                DCD     DMA15_IRQHandler  ; DMA Channel 15 Transfer Complete
+                DCD     DMA_Error_IRQHandler  ; DMA Error Interrupt
+                DCD     MCM_IRQHandler  ; Normal Interrupt
+                DCD     FTFE_IRQHandler  ; FTFE Command complete interrupt
+                DCD     Read_Collision_IRQHandler  ; Read Collision Interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
+                DCD     Watchdog_IRQHandler  ; WDOG Interrupt
+                DCD     RNG_IRQHandler  ; RNG Interrupt
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     I2C1_IRQHandler  ; I2C1 interrupt
+                DCD     SPI0_IRQHandler  ; SPI0 Interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 Interrupt
+                DCD     I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
+                DCD     I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
+                DCD     UART0_LON_IRQHandler  ; UART0 LON interrupt
+                DCD     UART0_RX_TX_IRQHandler  ; UART0 Receive/Transmit interrupt
+                DCD     UART0_ERR_IRQHandler  ; UART0 Error interrupt
+                DCD     UART1_RX_TX_IRQHandler  ; UART1 Receive/Transmit interrupt
+                DCD     UART1_ERR_IRQHandler  ; UART1 Error interrupt
+                DCD     UART2_RX_TX_IRQHandler  ; UART2 Receive/Transmit interrupt
+                DCD     UART2_ERR_IRQHandler  ; UART2 Error interrupt
+                DCD     UART3_RX_TX_IRQHandler  ; UART3 Receive/Transmit interrupt
+                DCD     UART3_ERR_IRQHandler  ; UART3 Error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     CMP0_IRQHandler  ; CMP0 interrupt
+                DCD     CMP1_IRQHandler  ; CMP1 interrupt
+                DCD     FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
+                DCD     FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
+                DCD     FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
+                DCD     CMT_IRQHandler  ; CMT interrupt
+                DCD     RTC_IRQHandler  ; RTC interrupt
+                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
+                DCD     PIT0_IRQHandler  ; PIT timer channel 0 interrupt
+                DCD     PIT1_IRQHandler  ; PIT timer channel 1 interrupt
+                DCD     PIT2_IRQHandler  ; PIT timer channel 2 interrupt
+                DCD     PIT3_IRQHandler  ; PIT timer channel 3 interrupt
+                DCD     PDB0_IRQHandler  ; PDB0 Interrupt
+                DCD     USB0_IRQHandler  ; USB0 interrupt
+                DCD     USBDCD_IRQHandler  ; USBDCD Interrupt
+                DCD     Reserved71_IRQHandler  ; Reserved interrupt 71
+                DCD     DAC0_IRQHandler  ; DAC0 interrupt
+                DCD     MCG_IRQHandler  ; MCG Interrupt
+                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
+                DCD     PORTA_IRQHandler  ; Port A interrupt
+                DCD     PORTB_IRQHandler  ; Port B interrupt
+                DCD     PORTC_IRQHandler  ; Port C interrupt
+                DCD     PORTD_IRQHandler  ; Port D interrupt
+                DCD     PORTE_IRQHandler  ; Port E interrupt
+                DCD     SWI_IRQHandler  ; Software interrupt
+                DCD     SPI2_IRQHandler  ; SPI2 Interrupt
+                DCD     UART4_RX_TX_IRQHandler  ; UART4 Receive/Transmit interrupt
+                DCD     UART4_ERR_IRQHandler  ; UART4 Error interrupt
+                DCD     UART5_RX_TX_IRQHandler  ; UART5 Receive/Transmit interrupt
+                DCD     UART5_ERR_IRQHandler  ; UART5 Error interrupt
+                DCD     CMP2_IRQHandler  ; CMP2 interrupt
+                DCD     FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
+                DCD     DAC1_IRQHandler  ; DAC1 interrupt
+                DCD     ADC1_IRQHandler  ; ADC1 interrupt
+                DCD     I2C2_IRQHandler  ; I2C2 interrupt
+                DCD     CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
+                DCD     CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
+                DCD     CAN0_Error_IRQHandler  ; CAN0 error interrupt
+                DCD     CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
+                DCD     CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
+                DCD     CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
+                DCD     SDHC_IRQHandler  ; SDHC interrupt
+                DCD     ENET_1588_Timer_IRQHandler  ; Ethernet MAC IEEE 1588 Timer Interrupt
+                DCD     ENET_Transmit_IRQHandler  ; Ethernet MAC Transmit Interrupt
+                DCD     ENET_Receive_IRQHandler  ; Ethernet MAC Receive Interrupt
+                DCD     ENET_Error_IRQHandler  ; Ethernet MAC Error and miscelaneous Interrupt
+                DCD     DefaultISR  ; 102
+                DCD     DefaultISR  ; 103
+                DCD     DefaultISR  ; 104
+                DCD     DefaultISR  ; 105
+                DCD     DefaultISR  ; 106
+                DCD     DefaultISR  ; 107
+                DCD     DefaultISR  ; 108
+                DCD     DefaultISR  ; 109
+                DCD     DefaultISR  ; 110
+                DCD     DefaultISR  ; 111
+                DCD     DefaultISR  ; 112
+                DCD     DefaultISR  ; 113
+                DCD     DefaultISR  ; 114
+                DCD     DefaultISR  ; 115
+                DCD     DefaultISR  ; 116
+                DCD     DefaultISR  ; 117
+                DCD     DefaultISR  ; 118
+                DCD     DefaultISR  ; 119
+                DCD     DefaultISR  ; 120
+                DCD     DefaultISR  ; 121
+                DCD     DefaultISR  ; 122
+                DCD     DefaultISR  ; 123
+                DCD     DefaultISR  ; 124
+                DCD     DefaultISR  ; 125
+                DCD     DefaultISR  ; 126
+                DCD     DefaultISR  ; 127
+                DCD     DefaultISR  ; 128
+                DCD     DefaultISR  ; 129
+                DCD     DefaultISR  ; 130
+                DCD     DefaultISR  ; 131
+                DCD     DefaultISR  ; 132
+                DCD     DefaultISR  ; 133
+                DCD     DefaultISR  ; 134
+                DCD     DefaultISR  ; 135
+                DCD     DefaultISR  ; 136
+                DCD     DefaultISR  ; 137
+                DCD     DefaultISR  ; 138
+                DCD     DefaultISR  ; 139
+                DCD     DefaultISR  ; 140
+                DCD     DefaultISR  ; 141
+                DCD     DefaultISR  ; 142
+                DCD     DefaultISR  ; 143
+                DCD     DefaultISR  ; 144
+                DCD     DefaultISR  ; 145
+                DCD     DefaultISR  ; 146
+                DCD     DefaultISR  ; 147
+                DCD     DefaultISR  ; 148
+                DCD     DefaultISR  ; 149
+                DCD     DefaultISR  ; 150
+                DCD     DefaultISR  ; 151
+                DCD     DefaultISR  ; 152
+                DCD     DefaultISR  ; 153
+                DCD     DefaultISR  ; 154
+                DCD     DefaultISR  ; 155
+                DCD     DefaultISR  ; 156
+                DCD     DefaultISR  ; 157
+                DCD     DefaultISR  ; 158
+                DCD     DefaultISR  ; 159
+                DCD     DefaultISR  ; 160
+                DCD     DefaultISR  ; 161
+                DCD     DefaultISR  ; 162
+                DCD     DefaultISR  ; 163
+                DCD     DefaultISR  ; 164
+                DCD     DefaultISR  ; 165
+                DCD     DefaultISR  ; 166
+                DCD     DefaultISR  ; 167
+                DCD     DefaultISR  ; 168
+                DCD     DefaultISR  ; 169
+                DCD     DefaultISR  ; 170
+                DCD     DefaultISR  ; 171
+                DCD     DefaultISR  ; 172
+                DCD     DefaultISR  ; 173
+                DCD     DefaultISR  ; 174
+                DCD     DefaultISR  ; 175
+                DCD     DefaultISR  ; 176
+                DCD     DefaultISR  ; 177
+                DCD     DefaultISR  ; 178
+                DCD     DefaultISR  ; 179
+                DCD     DefaultISR  ; 180
+                DCD     DefaultISR  ; 181
+                DCD     DefaultISR  ; 182
+                DCD     DefaultISR  ; 183
+                DCD     DefaultISR  ; 184
+                DCD     DefaultISR  ; 185
+                DCD     DefaultISR  ; 186
+                DCD     DefaultISR  ; 187
+                DCD     DefaultISR  ; 188
+                DCD     DefaultISR  ; 189
+                DCD     DefaultISR  ; 190
+                DCD     DefaultISR  ; 191
+                DCD     DefaultISR  ; 192
+                DCD     DefaultISR  ; 193
+                DCD     DefaultISR  ; 194
+                DCD     DefaultISR  ; 195
+                DCD     DefaultISR  ; 196
+                DCD     DefaultISR  ; 197
+                DCD     DefaultISR  ; 198
+                DCD     DefaultISR  ; 199
+                DCD     DefaultISR  ; 200
+                DCD     DefaultISR  ; 201
+                DCD     DefaultISR  ; 202
+                DCD     DefaultISR  ; 203
+                DCD     DefaultISR  ; 204
+                DCD     DefaultISR  ; 205
+                DCD     DefaultISR  ; 206
+                DCD     DefaultISR  ; 207
+                DCD     DefaultISR  ; 208
+                DCD     DefaultISR  ; 209
+                DCD     DefaultISR  ; 210
+                DCD     DefaultISR  ; 211
+                DCD     DefaultISR  ; 212
+                DCD     DefaultISR  ; 213
+                DCD     DefaultISR  ; 214
+                DCD     DefaultISR  ; 215
+                DCD     DefaultISR  ; 216
+                DCD     DefaultISR  ; 217
+                DCD     DefaultISR  ; 218
+                DCD     DefaultISR  ; 219
+                DCD     DefaultISR  ; 220
+                DCD     DefaultISR  ; 221
+                DCD     DefaultISR  ; 222
+                DCD     DefaultISR  ; 223
+                DCD     DefaultISR  ; 224
+                DCD     DefaultISR  ; 225
+                DCD     DefaultISR  ; 226
+                DCD     DefaultISR  ; 227
+                DCD     DefaultISR  ; 228
+                DCD     DefaultISR  ; 229
+                DCD     DefaultISR  ; 230
+                DCD     DefaultISR  ; 231
+                DCD     DefaultISR  ; 232
+                DCD     DefaultISR  ; 233
+                DCD     DefaultISR  ; 234
+                DCD     DefaultISR  ; 235
+                DCD     DefaultISR  ; 236
+                DCD     DefaultISR  ; 237
+                DCD     DefaultISR  ; 238
+                DCD     DefaultISR  ; 239
+                DCD     DefaultISR  ; 240
+                DCD     DefaultISR  ; 241
+                DCD     DefaultISR  ; 242
+                DCD     DefaultISR  ; 243
+                DCD     DefaultISR  ; 244
+                DCD     DefaultISR  ; 245
+                DCD     DefaultISR  ; 246
+                DCD     DefaultISR  ; 247
+                DCD     DefaultISR  ; 248
+                DCD     DefaultISR  ; 249
+                DCD     DefaultISR  ; 250
+                DCD     DefaultISR  ; 251
+                DCD     DefaultISR  ; 252
+                DCD     DefaultISR  ; 253
+                DCD     DefaultISR  ; 254
+                DCD     DefaultISR  ; 255
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program flash protection bytes
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Data flash protection byte (FDPROT)
+;     <i> Each bit protects a 1/8 region of the data flash memory.
+;     <i> (Program flash only devices: Reserved)
+;     <o.0>   FDPROT.0
+;     <o.1>   FDPROT.1
+;     <o.2>   FDPROT.2
+;     <o.3>   FDPROT.3
+;     <o.4>   FDPROT.4
+;     <o.5>   FDPROT.5
+;     <o.6>   FDPROT.6
+;     <o.7>   FDPROT.7
+nFDPROT         EQU     0x00
+FDPROT          EQU     nFDPROT:EOR:0xFF
+;   </h>
+;   <h> EEPROM protection byte (FEPROT)
+;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+;     <i> (Program flash only devices: Reserved)
+;     <o.0>   FEPROT.0
+;     <o.1>   FEPROT.1
+;     <o.2>   FEPROT.2
+;     <o.3>   FEPROT.3
+;     <o.4>   FEPROT.4
+;     <o.5>   FEPROT.5
+;     <o.6>   FEPROT.6
+;     <o.7>   FEPROT.7
+nFEPROT         EQU     0x00
+FEPROT          EQU     nFEPROT:EOR:0xFF
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0>  LPBOOT
+;       <0=> Low-power boot
+;       <1=> normal boot
+;     <o.1>  EZPORT_DIS
+;       <0=> EzPort operation is enabled
+;       <1=> EzPort operation is disabled
+FOPT            EQU     0xFF
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;         <i> This bits define the security state of the MCU.
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;         <i> Mass Erase Enable Bits
+;         <i> Enables and disables mass erase capability of the FTFL module
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
+                DCB     FSEC,       FOPT,       FEPROT,     FDPROT
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT     DMA0_IRQHandler  [WEAK]
+                EXPORT     DMA1_IRQHandler  [WEAK]
+                EXPORT     DMA2_IRQHandler  [WEAK]
+                EXPORT     DMA3_IRQHandler  [WEAK]
+                EXPORT     DMA4_IRQHandler  [WEAK]
+                EXPORT     DMA5_IRQHandler  [WEAK]
+                EXPORT     DMA6_IRQHandler  [WEAK]
+                EXPORT     DMA7_IRQHandler  [WEAK]
+                EXPORT     DMA8_IRQHandler  [WEAK]
+                EXPORT     DMA9_IRQHandler  [WEAK]
+                EXPORT     DMA10_IRQHandler  [WEAK]
+                EXPORT     DMA11_IRQHandler  [WEAK]
+                EXPORT     DMA12_IRQHandler  [WEAK]
+                EXPORT     DMA13_IRQHandler  [WEAK]
+                EXPORT     DMA14_IRQHandler  [WEAK]
+                EXPORT     DMA15_IRQHandler  [WEAK]
+                EXPORT     DMA_Error_IRQHandler   [WEAK]
+                EXPORT     MCM_IRQHandler  [WEAK]
+                EXPORT     FTFE_IRQHandler     [WEAK]
+                EXPORT     Read_Collision_IRQHandler      [WEAK]
+                EXPORT     LVD_LVW_IRQHandler       [WEAK]
+                EXPORT     LLW_IRQHandler       [WEAK]
+                EXPORT     Watchdog_IRQHandler  [WEAK]
+                EXPORT     RNG_IRQHandler  [WEAK]
+                EXPORT     I2C0_IRQHandler  [WEAK]
+                EXPORT     I2C1_IRQHandler  [WEAK]
+                EXPORT     SPI0_IRQHandler  [WEAK]
+                EXPORT     SPI1_IRQHandler  [WEAK]
+                EXPORT     I2S0_Tx_IRQHandler     [WEAK]
+                EXPORT     I2S0_Rx_IRQHandler      [WEAK]
+                EXPORT     UART0_LON_IRQHandler      [WEAK]
+                EXPORT     UART0_RX_TX_IRQHandler      [WEAK]
+                EXPORT     UART0_ERR_IRQHandler      [WEAK]
+                EXPORT     UART1_RX_TX_IRQHandler      [WEAK]
+                EXPORT     UART1_ERR_IRQHandler      [WEAK]
+                EXPORT     UART2_RX_TX_IRQHandler      [WEAK]
+                EXPORT     UART2_ERR_IRQHandler      [WEAK]
+                EXPORT     UART3_RX_TX_IRQHandler      [WEAK]
+                EXPORT     UART3_ERR_IRQHandler      [WEAK]
+                EXPORT     ADC0_IRQHandler  [WEAK]
+                EXPORT     CMP0_IRQHandler  [WEAK]
+                EXPORT     CMP1_IRQHandler  [WEAK]
+                EXPORT     FTM0_IRQHandler      [WEAK]
+                EXPORT     FTM1_IRQHandler      [WEAK]
+                EXPORT     FTM2_IRQHandler      [WEAK]
+                EXPORT     CMT_IRQHandler      [WEAK]
+                EXPORT     RTC_IRQHandler      [WEAK]
+                EXPORT     RTC_Seconds_IRQHandler      [WEAK]
+                EXPORT     PIT0_IRQHandler      [WEAK]
+                EXPORT     PIT1_IRQHandler      [WEAK]
+                EXPORT     PIT2_IRQHandler      [WEAK]
+                EXPORT     PIT3_IRQHandler      [WEAK]
+                EXPORT     PDB0_IRQHandler      [WEAK]
+                EXPORT     USB0_IRQHandler  [WEAK]
+                EXPORT     USBDCD_IRQHandler  [WEAK]
+                EXPORT     Reserved71_IRQHandler      [WEAK]
+                EXPORT     DAC0_IRQHandler     [WEAK]
+                EXPORT     MCG_IRQHandler      [WEAK]
+                EXPORT     LPTimer_IRQHandler    [WEAK]
+                EXPORT     PORTA_IRQHandler      [WEAK]
+                EXPORT     PORTB_IRQHandler      [WEAK]
+                EXPORT     PORTC_IRQHandler      [WEAK]
+                EXPORT     PORTD_IRQHandler      [WEAK]
+                EXPORT     PORTE_IRQHandler      [WEAK]
+                EXPORT     SWI_IRQHandler    [WEAK]
+                EXPORT     SPI2_IRQHandler  [WEAK]
+                EXPORT     UART4_RX_TX_IRQHandler  [WEAK]
+                EXPORT     UART4_ERR_IRQHandler  [WEAK]
+                EXPORT     UART5_RX_TX_IRQHandler  [WEAK]
+                EXPORT     UART5_ERR_IRQHandler  [WEAK]
+                EXPORT     CMP2_IRQHandler  [WEAK]
+                EXPORT     FTM3_IRQHandler  [WEAK]
+                EXPORT     DAC1_IRQHandler      [WEAK]
+                EXPORT     ADC1_IRQHandler      [WEAK]
+                EXPORT     I2C2_IRQHandler      [WEAK]
+                EXPORT     CAN0_ORed_Message_buffer_IRQHandler   [WEAK]
+                EXPORT     CAN0_Bus_Off_IRQHandler      [WEAK]
+                EXPORT     CAN0_Error_IRQHandler      [WEAK]
+                EXPORT     CAN0_Tx_Warning_IRQHandler  [WEAK]
+                EXPORT     CAN0_Rx_Warning_IRQHandler  [WEAK]
+                EXPORT     CAN0_Wake_Up_IRQHandler  [WEAK]
+                EXPORT     SDHC_IRQHandler  [WEAK]
+                EXPORT     ENET_1588_Timer_IRQHandler  [WEAK]
+                EXPORT     ENET_Transmit_IRQHandler  [WEAK]
+                EXPORT     ENET_Receive_IRQHandler  [WEAK]
+                EXPORT     ENET_Error_IRQHandler  [WEAK]
+
+DMA0_IRQHandler  ; DMA Channel 0 Transfer Complete
+DMA1_IRQHandler  ; DMA Channel 1 Transfer Complete
+DMA2_IRQHandler  ; DMA Channel 2 Transfer Complete
+DMA3_IRQHandler  ; DMA Channel 3 Transfer Complete
+DMA4_IRQHandler  ; DMA Channel 4 Transfer Complete
+DMA5_IRQHandler  ; DMA Channel 5 Transfer Complete
+DMA6_IRQHandler  ; DMA Channel 6 Transfer Complete
+DMA7_IRQHandler  ; DMA Channel 7 Transfer Complete
+DMA8_IRQHandler  ; DMA Channel 8 Transfer Complete
+DMA9_IRQHandler  ; DMA Channel 9 Transfer Complete
+DMA10_IRQHandler  ; DMA Channel 10 Transfer Complete
+DMA11_IRQHandler  ; DMA Channel 11 Transfer Complete
+DMA12_IRQHandler  ; DMA Channel 12 Transfer Complete
+DMA13_IRQHandler  ; DMA Channel 13 Transfer Complete
+DMA14_IRQHandler  ; DMA Channel 14 Transfer Complete
+DMA15_IRQHandler  ; DMA Channel 15 Transfer Complete
+DMA_Error_IRQHandler  ; DMA Error Interrupt
+MCM_IRQHandler  ; Normal Interrupt
+FTFE_IRQHandler  ; FTFE Command complete interrupt
+Read_Collision_IRQHandler  ; Read Collision Interrupt
+LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+LLW_IRQHandler  ; Low Leakage Wakeup
+Watchdog_IRQHandler  ; WDOG Interrupt
+RNG_IRQHandler  ; RNG Interrupt
+I2C0_IRQHandler  ; I2C0 interrupt
+I2C1_IRQHandler  ; I2C1 interrupt
+SPI0_IRQHandler  ; SPI0 Interrupt
+SPI1_IRQHandler  ; SPI1 Interrupt
+I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
+I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
+UART0_LON_IRQHandler  ; UART0 LON interrupt
+UART0_RX_TX_IRQHandler  ; UART0 Receive/Transmit interrupt
+UART0_ERR_IRQHandler  ; UART0 Error interrupt
+UART1_RX_TX_IRQHandler  ; UART1 Receive/Transmit interrupt
+UART1_ERR_IRQHandler  ; UART1 Error interrupt
+UART2_RX_TX_IRQHandler  ; UART2 Receive/Transmit interrupt
+UART2_ERR_IRQHandler  ; UART2 Error interrupt
+UART3_RX_TX_IRQHandler  ; UART3 Receive/Transmit interrupt
+UART3_ERR_IRQHandler  ; UART3 Error interrupt
+ADC0_IRQHandler  ; ADC0 interrupt
+CMP0_IRQHandler  ; CMP0 interrupt
+CMP1_IRQHandler  ; CMP1 interrupt
+FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
+FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
+FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
+CMT_IRQHandler  ; CMT interrupt
+RTC_IRQHandler  ; RTC interrupt
+RTC_Seconds_IRQHandler  ; RTC seconds interrupt
+PIT0_IRQHandler  ; PIT timer channel 0 interrupt
+PIT1_IRQHandler  ; PIT timer channel 1 interrupt
+PIT2_IRQHandler  ; PIT timer channel 2 interrupt
+PIT3_IRQHandler  ; PIT timer channel 3 interrupt
+PDB0_IRQHandler  ; PDB0 Interrupt
+USB0_IRQHandler  ; USB0 interrupt
+USBDCD_IRQHandler  ; USBDCD Interrupt
+Reserved71_IRQHandler  ; Reserved interrupt 71
+DAC0_IRQHandler  ; DAC0 interrupt
+MCG_IRQHandler  ; MCG Interrupt
+LPTimer_IRQHandler  ; LPTimer interrupt
+PORTA_IRQHandler  ; Port A interrupt
+PORTB_IRQHandler  ; Port B interrupt
+PORTC_IRQHandler  ; Port C interrupt
+PORTD_IRQHandler  ; Port D interrupt
+PORTE_IRQHandler  ; Port E interrupt
+SWI_IRQHandler  ; Software interrupt
+SPI2_IRQHandler  ; SPI2 Interrupt
+UART4_RX_TX_IRQHandler  ; UART4 Receive/Transmit interrupt
+UART4_ERR_IRQHandler  ; UART4 Error interrupt
+UART5_RX_TX_IRQHandler  ; UART5 Receive/Transmit interrupt
+UART5_ERR_IRQHandler  ; UART5 Error interrupt
+CMP2_IRQHandler  ; CMP2 interrupt
+FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
+DAC1_IRQHandler  ; DAC1 interrupt
+ADC1_IRQHandler  ; ADC1 interrupt
+I2C2_IRQHandler  ; I2C2 interrupt
+CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
+CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
+CAN0_Error_IRQHandler  ; CAN0 error interrupt
+CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
+CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
+CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
+SDHC_IRQHandler  ; SDHC interrupt
+ENET_1588_Timer_IRQHandler  ; Ethernet MAC IEEE 1588 Timer Interrupt
+ENET_Transmit_IRQHandler  ; Ethernet MAC Transmit Interrupt
+ENET_Receive_IRQHandler  ; Ethernet MAC Receive Interrupt
+ENET_Error_IRQHandler  ; Ethernet MAC Error and miscelaneous Interrupt
+DefaultISR
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/bsp/k64Fxxxx/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/bsp/k64Fxxxx/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
new file mode 100644
index 0000000000..5978e7c444
--- /dev/null
+++ b/bsp/k64Fxxxx/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
@@ -0,0 +1,369 @@
+/* K64F startup ARM GCC
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv7-m
+    
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+
+   The STACK starts at the end of the RAM and grows downward.
+
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xC00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x400
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+    .section .vector_table,"a",%progbits
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                  /* Top of Stack */
+    .long   Reset_Handler               /* Reset Handler */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DMA0_IRQHandler  /* DMA Channel 0 Transfer Complete */
+    .long   DMA1_IRQHandler  /* DMA Channel 1 Transfer Complete */
+    .long   DMA2_IRQHandler  /* DMA Channel 2 Transfer Complete */
+    .long   DMA3_IRQHandler  /* DMA Channel 3 Transfer Complete */
+    .long   DMA4_IRQHandler  /* DMA Channel 4 Transfer Complete */
+    .long   DMA5_IRQHandler  /* DMA Channel 5 Transfer Complete */
+    .long   DMA6_IRQHandler  /* DMA Channel 6 Transfer Complete */
+    .long   DMA7_IRQHandler  /* DMA Channel 7 Transfer Complete */
+    .long   DMA8_IRQHandler  /* DMA Channel 8 Transfer Complete */
+    .long   DMA9_IRQHandler  /* DMA Channel 9 Transfer Complete */
+    .long   DMA10_IRQHandler  /* DMA Channel 10 Transfer Complete */
+    .long   DMA11_IRQHandler  /* DMA Channel 11 Transfer Complete */
+    .long   DMA12_IRQHandler  /* DMA Channel 12 Transfer Complete */
+    .long   DMA13_IRQHandler  /* DMA Channel 13 Transfer Complete */
+    .long   DMA14_IRQHandler  /* DMA Channel 14 Transfer Complete */
+    .long   DMA15_IRQHandler  /* DMA Channel 15 Transfer Complete */
+    .long   DMA_Error_IRQHandler  /* DMA Error Interrupt */
+    .long   MCM_IRQHandler  /* Normal Interrupt */
+    .long   FTFE_IRQHandler  /* FTFE Command complete interrupt */
+    .long   Read_Collision_IRQHandler  /* Read Collision Interrupt */
+    .long   LVD_LVW_IRQHandler  /* Low Voltage Detect, Low Voltage Warning */
+    .long   LLW_IRQHandler  /* Low Leakage Wakeup */
+    .long   Watchdog_IRQHandler  /* WDOG Interrupt */
+    .long   RNG_IRQHandler  /* RNG Interrupt */
+    .long   I2C0_IRQHandler  /* I2C0 interrupt */
+    .long   I2C1_IRQHandler  /* I2C1 interrupt */
+    .long   SPI0_IRQHandler  /* SPI0 Interrupt */
+    .long   SPI1_IRQHandler  /* SPI1 Interrupt */
+    .long   I2S0_Tx_IRQHandler  /* I2S0 transmit interrupt */
+    .long   I2S0_Rx_IRQHandler  /* I2S0 receive interrupt */
+    .long   UART0_LON_IRQHandler  /* UART0 LON interrupt */
+    .long   UART0_RX_TX_IRQHandler  /* UART0 Receive/Transmit interrupt */
+    .long   UART0_ERR_IRQHandler  /* UART0 Error interrupt */
+    .long   UART1_RX_TX_IRQHandler  /* UART1 Receive/Transmit interrupt */
+    .long   UART1_ERR_IRQHandler  /* UART1 Error interrupt */
+    .long   UART2_RX_TX_IRQHandler  /* UART2 Receive/Transmit interrupt */
+    .long   UART2_ERR_IRQHandler  /* UART2 Error interrupt */
+    .long   UART3_RX_TX_IRQHandler  /* UART3 Receive/Transmit interrupt */
+    .long   UART3_ERR_IRQHandler  /* UART3 Error interrupt */
+    .long   ADC0_IRQHandler  /* ADC0 interrupt */
+    .long   CMP0_IRQHandler  /* CMP0 interrupt */
+    .long   CMP1_IRQHandler  /* CMP1 interrupt */
+    .long   FTM0_IRQHandler  /* FTM0 fault, overflow and channels interrupt */
+    .long   FTM1_IRQHandler  /* FTM1 fault, overflow and channels interrupt */
+    .long   FTM2_IRQHandler  /* FTM2 fault, overflow and channels interrupt */
+    .long   CMT_IRQHandler  /* CMT interrupt */
+    .long   RTC_IRQHandler  /* RTC interrupt */
+    .long   RTC_Seconds_IRQHandler  /* RTC seconds interrupt */
+    .long   PIT0_IRQHandler  /* PIT timer channel 0 interrupt */
+    .long   PIT1_IRQHandler  /* PIT timer channel 1 interrupt */
+    .long   PIT2_IRQHandler  /* PIT timer channel 2 interrupt */
+    .long   PIT3_IRQHandler  /* PIT timer channel 3 interrupt */
+    .long   PDB0_IRQHandler  /* PDB0 Interrupt */
+    .long   USB0_IRQHandler  /* USB0 interrupt */
+    .long   USBDCD_IRQHandler  /* USBDCD Interrupt */
+    .long   Reserved71_IRQHandler  /* Reserved interrupt 71 */
+    .long   DAC0_IRQHandler  /* DAC0 interrupt */
+    .long   MCG_IRQHandler  /* MCG Interrupt */
+    .long   LPTimer_IRQHandler  /* LPTimer interrupt */
+    .long   PORTA_IRQHandler  /* Port A interrupt */
+    .long   PORTB_IRQHandler  /* Port B interrupt */
+    .long   PORTC_IRQHandler  /* Port C interrupt */
+    .long   PORTD_IRQHandler  /* Port D interrupt */
+    .long   PORTE_IRQHandler  /* Port E interrupt */
+    .long   SWI_IRQHandler  /* Software interrupt */
+    .long   SPI2_IRQHandler  /* SPI2 Interrupt */
+    .long   UART4_RX_TX_IRQHandler  /* UART4 Receive/Transmit interrupt */
+    .long   UART4_ERR_IRQHandler  /* UART4 Error interrupt */
+    .long   UART5_RX_TX_IRQHandler  /* UART5 Receive/Transmit interrupt */
+    .long   UART5_ERR_IRQHandler  /* UART5 Error interrupt */
+    .long   CMP2_IRQHandler  /* CMP2 interrupt */
+    .long   FTM3_IRQHandler  /* FTM3 fault, overflow and channels interrupt */
+    .long   DAC1_IRQHandler  /* DAC1 interrupt */
+    .long   ADC1_IRQHandler  /* ADC1 interrupt */
+    .long   I2C2_IRQHandler  /* I2C2 interrupt */
+    .long   CAN0_ORed_Message_buffer_IRQHandler  /* CAN0 OR'd message buffers interrupt */
+    .long   CAN0_Bus_Off_IRQHandler  /* CAN0 bus off interrupt */
+    .long   CAN0_Error_IRQHandler  /* CAN0 error interrupt */
+    .long   CAN0_Tx_Warning_IRQHandler  /* CAN0 Tx warning interrupt */
+    .long   CAN0_Rx_Warning_IRQHandler  /* CAN0 Rx warning interrupt */
+    .long   CAN0_Wake_Up_IRQHandler  /* CAN0 wake up interrupt */
+    .long   SDHC_IRQHandler  /* SDHC interrupt */
+    .long   ENET_1588_Timer_IRQHandler  /* Ethernet MAC IEEE 1588 Timer Interrupt */
+    .long   ENET_Transmit_IRQHandler  /* Ethernet MAC Transmit Interrupt */
+    .long   ENET_Receive_IRQHandler  /* Ethernet MAC Receive Interrupt */
+    .long   ENET_Error_IRQHandler  /* Ethernet MAC Error and miscelaneous Interrupt */
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .section .text.Reset_Handler
+    .thumb
+    .thumb_func
+    .align  2
+    .globl   Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+disable_watchdog:
+    /* unlock */
+    ldr r1, =0x4005200e
+    ldr r0, =0xc520
+    strh r0, [r1]
+    ldr r0, =0xd928
+    strh r0, [r1]
+    /* disable */
+    ldr r1, =0x40052000
+    ldr r0, =0x01d2
+    strh r0, [r1]
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs   r3, r2
+    ble    .Lflash_to_ram_loop_end
+
+    movs    r4, 0
+.Lflash_to_ram_loop:
+    ldr    r0, [r1,r4]
+    str    r0, [r2,r4]
+    adds   r4, 4
+    cmp    r4, r3
+    blt    .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+    ldr   r0, =SystemInit
+    blx   r0
+    ldr   r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+/* Exception Handlers */
+
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+    
+    .macro    def_irq_default_handler    handler_name
+    .weak     \handler_name
+    .set      \handler_name, Default_Handler
+    .endm
+
+/* IRQ Handlers */
+    def_irq_default_handler     DMA0_IRQHandler
+    def_irq_default_handler     DMA1_IRQHandler
+    def_irq_default_handler     DMA2_IRQHandler
+    def_irq_default_handler     DMA3_IRQHandler
+    def_irq_default_handler     DMA4_IRQHandler
+    def_irq_default_handler     DMA5_IRQHandler
+    def_irq_default_handler     DMA6_IRQHandler
+    def_irq_default_handler     DMA7_IRQHandler
+    def_irq_default_handler     DMA8_IRQHandler
+    def_irq_default_handler     DMA9_IRQHandler
+    def_irq_default_handler     DMA10_IRQHandler
+    def_irq_default_handler     DMA11_IRQHandler
+    def_irq_default_handler     DMA12_IRQHandler
+    def_irq_default_handler     DMA13_IRQHandler
+    def_irq_default_handler     DMA14_IRQHandler
+    def_irq_default_handler     DMA15_IRQHandler
+    def_irq_default_handler     DMA_Error_IRQHandler
+    def_irq_default_handler     MCM_IRQHandler
+    def_irq_default_handler     FTFE_IRQHandler
+    def_irq_default_handler     Read_Collision_IRQHandler
+    def_irq_default_handler     LVD_LVW_IRQHandler
+    def_irq_default_handler     LLW_IRQHandler
+    def_irq_default_handler     Watchdog_IRQHandler
+    def_irq_default_handler     RNG_IRQHandler
+    def_irq_default_handler     I2C0_IRQHandler
+    def_irq_default_handler     I2C1_IRQHandler
+    def_irq_default_handler     SPI0_IRQHandler
+    def_irq_default_handler     SPI1_IRQHandler
+    def_irq_default_handler     I2S0_Tx_IRQHandler
+    def_irq_default_handler     I2S0_Rx_IRQHandler
+    def_irq_default_handler     UART0_LON_IRQHandler
+    def_irq_default_handler     UART0_RX_TX_IRQHandler
+    def_irq_default_handler     UART0_ERR_IRQHandler
+    def_irq_default_handler     UART1_RX_TX_IRQHandler
+    def_irq_default_handler     UART1_ERR_IRQHandler
+    def_irq_default_handler     UART2_RX_TX_IRQHandler
+    def_irq_default_handler     UART2_ERR_IRQHandler
+    def_irq_default_handler     UART3_RX_TX_IRQHandler
+    def_irq_default_handler     UART3_ERR_IRQHandler
+    def_irq_default_handler     ADC0_IRQHandler
+    def_irq_default_handler     CMP0_IRQHandler
+    def_irq_default_handler     CMP1_IRQHandler
+    def_irq_default_handler     FTM0_IRQHandler
+    def_irq_default_handler     FTM1_IRQHandler
+    def_irq_default_handler     FTM2_IRQHandler
+    def_irq_default_handler     CMT_IRQHandler
+    def_irq_default_handler     RTC_IRQHandler
+    def_irq_default_handler     RTC_Seconds_IRQHandler
+    def_irq_default_handler     PIT0_IRQHandler
+    def_irq_default_handler     PIT1_IRQHandler
+    def_irq_default_handler     PIT2_IRQHandler
+    def_irq_default_handler     PIT3_IRQHandler
+    def_irq_default_handler     PDB0_IRQHandler
+    def_irq_default_handler     USB0_IRQHandler
+    def_irq_default_handler     USBDCD_IRQHandler
+    def_irq_default_handler     Reserved71_IRQHandler
+    def_irq_default_handler     DAC0_IRQHandler
+    def_irq_default_handler     MCG_IRQHandler
+    def_irq_default_handler     LPTimer_IRQHandler
+    def_irq_default_handler     PORTA_IRQHandler
+    def_irq_default_handler     PORTB_IRQHandler
+    def_irq_default_handler     PORTC_IRQHandler
+    def_irq_default_handler     PORTD_IRQHandler
+    def_irq_default_handler     PORTE_IRQHandler
+    def_irq_default_handler     SWI_IRQHandler
+    def_irq_default_handler     SPI2_IRQHandler
+    def_irq_default_handler     UART4_RX_TX_IRQHandler
+    def_irq_default_handler     UART4_ERR_IRQHandler
+    def_irq_default_handler     UART5_RX_TX_IRQHandler
+    def_irq_default_handler     UART5_ERR_IRQHandler
+    def_irq_default_handler     CMP2_IRQHandler
+    def_irq_default_handler     FTM3_IRQHandler
+    def_irq_default_handler     DAC1_IRQHandler
+    def_irq_default_handler     ADC1_IRQHandler
+    def_irq_default_handler     I2C2_IRQHandler
+    def_irq_default_handler     CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_default_handler     CAN0_Bus_Off_IRQHandler
+    def_irq_default_handler     CAN0_Error_IRQHandler
+    def_irq_default_handler     CAN0_Tx_Warning_IRQHandler
+    def_irq_default_handler     CAN0_Rx_Warning_IRQHandler
+    def_irq_default_handler     CAN0_Wake_Up_IRQHandler
+    def_irq_default_handler     SDHC_IRQHandler
+    def_irq_default_handler     ENET_1588_Timer_IRQHandler
+    def_irq_default_handler     ENET_Transmit_IRQHandler
+    def_irq_default_handler     ENET_Receive_IRQHandler
+    def_irq_default_handler     ENET_Error_IRQHandler
+    def_irq_default_handler     DefaultISR
+    
+/* Flash protection region, placed at 0x400 */
+    .text
+    .thumb
+    .align 2
+    .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+    .long 0xffffffff
+    .long 0xffffffff
+    .long 0xffffffff
+    .long 0xfffffffe
+
+    .end
diff --git a/bsp/k64Fxxxx/device/core_cm4.h b/bsp/k64Fxxxx/device/core_cm4.h
new file mode 100644
index 0000000000..d65016c714
--- /dev/null
+++ b/bsp/k64Fxxxx/device/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/k64Fxxxx/device/core_cm4_simd.h b/bsp/k64Fxxxx/device/core_cm4_simd.h
new file mode 100644
index 0000000000..83db95b5f1
--- /dev/null
+++ b/bsp/k64Fxxxx/device/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/k64Fxxxx/device/core_cmFunc.h b/bsp/k64Fxxxx/device/core_cmFunc.h
new file mode 100644
index 0000000000..0a18fafc30
--- /dev/null
+++ b/bsp/k64Fxxxx/device/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/k64Fxxxx/device/core_cmInstr.h b/bsp/k64Fxxxx/device/core_cmInstr.h
new file mode 100644
index 0000000000..d213f0eed7
--- /dev/null
+++ b/bsp/k64Fxxxx/device/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/k64Fxxxx/device/fsl_device_registers.h b/bsp/k64Fxxxx/device/fsl_device_registers.h
new file mode 100644
index 0000000000..c7bf07a20b
--- /dev/null
+++ b/bsp/k64Fxxxx/device/fsl_device_registers.h
@@ -0,0 +1,572 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK22FN512VDC12))
+    #define K22F51212_SERIES
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK22F51212/MK22F51212_adc.h"
+    #include "device/MK22F51212/MK22F51212_aips.h"
+    #include "device/MK22F51212/MK22F51212_cmp.h"
+    #include "device/MK22F51212/MK22F51212_crc.h"
+    #include "device/MK22F51212/MK22F51212_dac.h"
+    #include "device/MK22F51212/MK22F51212_dma.h"
+    #include "device/MK22F51212/MK22F51212_dmamux.h"
+    #include "device/MK22F51212/MK22F51212_ewm.h"
+    #include "device/MK22F51212/MK22F51212_fb.h"
+    #include "device/MK22F51212/MK22F51212_fmc.h"
+    #include "device/MK22F51212/MK22F51212_ftfa.h"
+    #include "device/MK22F51212/MK22F51212_ftm.h"
+    #include "device/MK22F51212/MK22F51212_gpio.h"
+    #include "device/MK22F51212/MK22F51212_i2c.h"
+    #include "device/MK22F51212/MK22F51212_i2s.h"
+    #include "device/MK22F51212/MK22F51212_llwu.h"
+    #include "device/MK22F51212/MK22F51212_lptmr.h"
+    #include "device/MK22F51212/MK22F51212_mcg.h"
+    #include "device/MK22F51212/MK22F51212_mcm.h"
+    #include "device/MK22F51212/MK22F51212_nv.h"
+    #include "device/MK22F51212/MK22F51212_osc.h"
+    #include "device/MK22F51212/MK22F51212_pdb.h"
+    #include "device/MK22F51212/MK22F51212_pit.h"
+    #include "device/MK22F51212/MK22F51212_pmc.h"
+    #include "device/MK22F51212/MK22F51212_port.h"
+    #include "device/MK22F51212/MK22F51212_rcm.h"
+    #include "device/MK22F51212/MK22F51212_rfsys.h"
+    #include "device/MK22F51212/MK22F51212_rfvbat.h"
+    #include "device/MK22F51212/MK22F51212_rng.h"
+    #include "device/MK22F51212/MK22F51212_rtc.h"
+    #include "device/MK22F51212/MK22F51212_sim.h"
+    #include "device/MK22F51212/MK22F51212_smc.h"
+    #include "device/MK22F51212/MK22F51212_spi.h"
+    #include "device/MK22F51212/MK22F51212_uart.h"
+    #include "device/MK22F51212/MK22F51212_usb.h"
+    #include "device/MK22F51212/MK22F51212_vref.h"
+    #include "device/MK22F51212/MK22F51212_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK22F51212/MK22F51212.h"
+
+#elif (defined(CPU_MK24FN1M0VLQ12))
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK24F12/MK24F12_adc.h"
+    #include "device/MK24F12/MK24F12_aips.h"
+    #include "device/MK24F12/MK24F12_axbs.h"
+    #include "device/MK24F12/MK24F12_can.h"
+    #include "device/MK24F12/MK24F12_cau.h"
+    #include "device/MK24F12/MK24F12_cmp.h"
+    #include "device/MK24F12/MK24F12_cmt.h"
+    #include "device/MK24F12/MK24F12_crc.h"
+    #include "device/MK24F12/MK24F12_dac.h"
+    #include "device/MK24F12/MK24F12_dma.h"
+    #include "device/MK24F12/MK24F12_dmamux.h"
+    #include "device/MK24F12/MK24F12_ewm.h"
+    #include "device/MK24F12/MK24F12_fb.h"
+    #include "device/MK24F12/MK24F12_fmc.h"
+    #include "device/MK24F12/MK24F12_ftfe.h"
+    #include "device/MK24F12/MK24F12_ftm.h"
+    #include "device/MK24F12/MK24F12_gpio.h"
+    #include "device/MK24F12/MK24F12_i2c.h"
+    #include "device/MK24F12/MK24F12_i2s.h"
+    #include "device/MK24F12/MK24F12_llwu.h"
+    #include "device/MK24F12/MK24F12_lptmr.h"
+    #include "device/MK24F12/MK24F12_mcg.h"
+    #include "device/MK24F12/MK24F12_mcm.h"
+    #include "device/MK24F12/MK24F12_mpu.h"
+    #include "device/MK24F12/MK24F12_nv.h"
+    #include "device/MK24F12/MK24F12_osc.h"
+    #include "device/MK24F12/MK24F12_pdb.h"
+    #include "device/MK24F12/MK24F12_pit.h"
+    #include "device/MK24F12/MK24F12_pmc.h"
+    #include "device/MK24F12/MK24F12_port.h"
+    #include "device/MK24F12/MK24F12_rcm.h"
+    #include "device/MK24F12/MK24F12_rfsys.h"
+    #include "device/MK24F12/MK24F12_rfvbat.h"
+    #include "device/MK24F12/MK24F12_rng.h"
+    #include "device/MK24F12/MK24F12_rtc.h"
+    #include "device/MK24F12/MK24F12_sdhc.h"
+    #include "device/MK24F12/MK24F12_sim.h"
+    #include "device/MK24F12/MK24F12_smc.h"
+    #include "device/MK24F12/MK24F12_spi.h"
+    #include "device/MK24F12/MK24F12_uart.h"
+    #include "device/MK24F12/MK24F12_usb.h"
+    #include "device/MK24F12/MK24F12_usbdcd.h"
+    #include "device/MK24F12/MK24F12_vref.h"
+    #include "device/MK24F12/MK24F12_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK24F12/MK24F12.h"
+
+#elif (defined(CPU_MK63FN1M0VMD12))
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK63F12/MK63F12_adc.h"
+    #include "device/MK63F12/MK63F12_aips.h"
+    #include "device/MK63F12/MK63F12_axbs.h"
+    #include "device/MK63F12/MK63F12_can.h"
+    #include "device/MK63F12/MK63F12_cau.h"
+    #include "device/MK63F12/MK63F12_cmp.h"
+    #include "device/MK63F12/MK63F12_cmt.h"
+    #include "device/MK63F12/MK63F12_crc.h"
+    #include "device/MK63F12/MK63F12_dac.h"
+    #include "device/MK63F12/MK63F12_dma.h"
+    #include "device/MK63F12/MK63F12_dmamux.h"
+    #include "device/MK63F12/MK63F12_enet.h"
+    #include "device/MK63F12/MK63F12_ewm.h"
+    #include "device/MK63F12/MK63F12_fb.h"
+    #include "device/MK63F12/MK63F12_fmc.h"
+    #include "device/MK63F12/MK63F12_ftfe.h"
+    #include "device/MK63F12/MK63F12_ftm.h"
+    #include "device/MK63F12/MK63F12_gpio.h"
+    #include "device/MK63F12/MK63F12_i2c.h"
+    #include "device/MK63F12/MK63F12_i2s.h"
+    #include "device/MK63F12/MK63F12_llwu.h"
+    #include "device/MK63F12/MK63F12_lptmr.h"
+    #include "device/MK63F12/MK63F12_mcg.h"
+    #include "device/MK63F12/MK63F12_mcm.h"
+    #include "device/MK63F12/MK63F12_mpu.h"
+    #include "device/MK63F12/MK63F12_nv.h"
+    #include "device/MK63F12/MK63F12_osc.h"
+    #include "device/MK63F12/MK63F12_pdb.h"
+    #include "device/MK63F12/MK63F12_pit.h"
+    #include "device/MK63F12/MK63F12_pmc.h"
+    #include "device/MK63F12/MK63F12_port.h"
+    #include "device/MK63F12/MK63F12_rcm.h"
+    #include "device/MK63F12/MK63F12_rfsys.h"
+    #include "device/MK63F12/MK63F12_rfvbat.h"
+    #include "device/MK63F12/MK63F12_rng.h"
+    #include "device/MK63F12/MK63F12_rtc.h"
+    #include "device/MK63F12/MK63F12_sdhc.h"
+    #include "device/MK63F12/MK63F12_sim.h"
+    #include "device/MK63F12/MK63F12_smc.h"
+    #include "device/MK63F12/MK63F12_spi.h"
+    #include "device/MK63F12/MK63F12_uart.h"
+    #include "device/MK63F12/MK63F12_usb.h"
+    #include "device/MK63F12/MK63F12_usbdcd.h"
+    #include "device/MK63F12/MK63F12_vref.h"
+    #include "device/MK63F12/MK63F12_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK63F12/MK63F12.h"
+
+#elif (defined(CPU_MK63FN1M0VMD12WS))
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK63F12WS/MK63F12WS_adc.h"
+    #include "device/MK63F12WS/MK63F12WS_aips.h"
+    #include "device/MK63F12WS/MK63F12WS_axbs.h"
+    #include "device/MK63F12WS/MK63F12WS_can.h"
+    #include "device/MK63F12WS/MK63F12WS_cau.h"
+    #include "device/MK63F12WS/MK63F12WS_cmp.h"
+    #include "device/MK63F12WS/MK63F12WS_cmt.h"
+    #include "device/MK63F12WS/MK63F12WS_crc.h"
+    #include "device/MK63F12WS/MK63F12WS_dac.h"
+    #include "device/MK63F12WS/MK63F12WS_dma.h"
+    #include "device/MK63F12WS/MK63F12WS_dmamux.h"
+    #include "device/MK63F12WS/MK63F12WS_dry.h"
+    #include "device/MK63F12WS/MK63F12WS_enet.h"
+    #include "device/MK63F12WS/MK63F12WS_ewm.h"
+    #include "device/MK63F12WS/MK63F12WS_fb.h"
+    #include "device/MK63F12WS/MK63F12WS_fmc.h"
+    #include "device/MK63F12WS/MK63F12WS_ftfe.h"
+    #include "device/MK63F12WS/MK63F12WS_ftm.h"
+    #include "device/MK63F12WS/MK63F12WS_gpio.h"
+    #include "device/MK63F12WS/MK63F12WS_i2c.h"
+    #include "device/MK63F12WS/MK63F12WS_i2s.h"
+    #include "device/MK63F12WS/MK63F12WS_llwu.h"
+    #include "device/MK63F12WS/MK63F12WS_lptmr.h"
+    #include "device/MK63F12WS/MK63F12WS_mcg.h"
+    #include "device/MK63F12WS/MK63F12WS_mcm.h"
+    #include "device/MK63F12WS/MK63F12WS_mpu.h"
+    #include "device/MK63F12WS/MK63F12WS_nv.h"
+    #include "device/MK63F12WS/MK63F12WS_osc.h"
+    #include "device/MK63F12WS/MK63F12WS_pdb.h"
+    #include "device/MK63F12WS/MK63F12WS_pit.h"
+    #include "device/MK63F12WS/MK63F12WS_pmc.h"
+    #include "device/MK63F12WS/MK63F12WS_port.h"
+    #include "device/MK63F12WS/MK63F12WS_rcm.h"
+    #include "device/MK63F12WS/MK63F12WS_rfsys.h"
+    #include "device/MK63F12WS/MK63F12WS_rfvbat.h"
+    #include "device/MK63F12WS/MK63F12WS_rng.h"
+    #include "device/MK63F12WS/MK63F12WS_rtc.h"
+    #include "device/MK63F12WS/MK63F12WS_sdhc.h"
+    #include "device/MK63F12WS/MK63F12WS_sim.h"
+    #include "device/MK63F12WS/MK63F12WS_smc.h"
+    #include "device/MK63F12WS/MK63F12WS_spi.h"
+    #include "device/MK63F12WS/MK63F12WS_uart.h"
+    #include "device/MK63F12WS/MK63F12WS_usb.h"
+    #include "device/MK63F12WS/MK63F12WS_usbdcd.h"
+    #include "device/MK63F12WS/MK63F12WS_vref.h"
+    #include "device/MK63F12WS/MK63F12WS_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK63F12WS/MK63F12WS.h"
+
+#elif (defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12))
+    #define K64F12_SERIES
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK64F12/MK64F12_adc.h"
+    #include "device/MK64F12/MK64F12_aips.h"
+    #include "device/MK64F12/MK64F12_axbs.h"
+    #include "device/MK64F12/MK64F12_can.h"
+    #include "device/MK64F12/MK64F12_cau.h"
+    #include "device/MK64F12/MK64F12_cmp.h"
+    #include "device/MK64F12/MK64F12_cmt.h"
+    #include "device/MK64F12/MK64F12_crc.h"
+    #include "device/MK64F12/MK64F12_dac.h"
+    #include "device/MK64F12/MK64F12_dma.h"
+    #include "device/MK64F12/MK64F12_dmamux.h"
+    #include "device/MK64F12/MK64F12_enet.h"
+    #include "device/MK64F12/MK64F12_ewm.h"
+    #include "device/MK64F12/MK64F12_fb.h"
+    #include "device/MK64F12/MK64F12_fmc.h"
+    #include "device/MK64F12/MK64F12_ftfe.h"
+    #include "device/MK64F12/MK64F12_ftm.h"
+    #include "device/MK64F12/MK64F12_gpio.h"
+    #include "device/MK64F12/MK64F12_i2c.h"
+    #include "device/MK64F12/MK64F12_i2s.h"
+    #include "device/MK64F12/MK64F12_llwu.h"
+    #include "device/MK64F12/MK64F12_lptmr.h"
+    #include "device/MK64F12/MK64F12_mcg.h"
+    #include "device/MK64F12/MK64F12_mcm.h"
+    #include "device/MK64F12/MK64F12_mpu.h"
+    #include "device/MK64F12/MK64F12_nv.h"
+    #include "device/MK64F12/MK64F12_osc.h"
+    #include "device/MK64F12/MK64F12_pdb.h"
+    #include "device/MK64F12/MK64F12_pit.h"
+    #include "device/MK64F12/MK64F12_pmc.h"
+    #include "device/MK64F12/MK64F12_port.h"
+    #include "device/MK64F12/MK64F12_rcm.h"
+    #include "device/MK64F12/MK64F12_rfsys.h"
+    #include "device/MK64F12/MK64F12_rfvbat.h"
+    #include "device/MK64F12/MK64F12_rng.h"
+    #include "device/MK64F12/MK64F12_rtc.h"
+    #include "device/MK64F12/MK64F12_sdhc.h"
+    #include "device/MK64F12/MK64F12_sim.h"
+    #include "device/MK64F12/MK64F12_smc.h"
+    #include "device/MK64F12/MK64F12_spi.h"
+    #include "device/MK64F12/MK64F12_uart.h"
+    #include "device/MK64F12/MK64F12_usb.h"
+    #include "device/MK64F12/MK64F12_usbdcd.h"
+    #include "device/MK64F12/MK64F12_vref.h"
+    #include "device/MK64F12/MK64F12_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK64F12/MK64F12.h"
+
+#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
+    defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
+    defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+    #define K70F12_SERIES
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK70F12/MK70F12_adc.h"
+    #include "device/MK70F12/MK70F12_aips.h"
+    #include "device/MK70F12/MK70F12_axbs.h"
+    #include "device/MK70F12/MK70F12_can.h"
+    #include "device/MK70F12/MK70F12_cau.h"
+    #include "device/MK70F12/MK70F12_cmp.h"
+    #include "device/MK70F12/MK70F12_cmt.h"
+    #include "device/MK70F12/MK70F12_crc.h"
+    #include "device/MK70F12/MK70F12_dac.h"
+    #include "device/MK70F12/MK70F12_ddr.h"
+    #include "device/MK70F12/MK70F12_dma.h"
+    #include "device/MK70F12/MK70F12_dmamux.h"
+    #include "device/MK70F12/MK70F12_enet.h"
+    #include "device/MK70F12/MK70F12_ewm.h"
+    #include "device/MK70F12/MK70F12_fb.h"
+    #include "device/MK70F12/MK70F12_fmc.h"
+    #include "device/MK70F12/MK70F12_ftfe.h"
+    #include "device/MK70F12/MK70F12_ftm.h"
+    #include "device/MK70F12/MK70F12_gpio.h"
+    #include "device/MK70F12/MK70F12_i2c.h"
+    #include "device/MK70F12/MK70F12_i2s.h"
+    #include "device/MK70F12/MK70F12_lcdc.h"
+    #include "device/MK70F12/MK70F12_llwu.h"
+    #include "device/MK70F12/MK70F12_lmem.h"
+    #include "device/MK70F12/MK70F12_lptmr.h"
+    #include "device/MK70F12/MK70F12_mcg.h"
+    #include "device/MK70F12/MK70F12_mcm.h"
+    #include "device/MK70F12/MK70F12_mpu.h"
+    #include "device/MK70F12/MK70F12_nfc.h"
+    #include "device/MK70F12/MK70F12_nv.h"
+    #include "device/MK70F12/MK70F12_osc.h"
+    #include "device/MK70F12/MK70F12_pdb.h"
+    #include "device/MK70F12/MK70F12_pit.h"
+    #include "device/MK70F12/MK70F12_pmc.h"
+    #include "device/MK70F12/MK70F12_port.h"
+    #include "device/MK70F12/MK70F12_rcm.h"
+    #include "device/MK70F12/MK70F12_rfsys.h"
+    #include "device/MK70F12/MK70F12_rfvbat.h"
+    #include "device/MK70F12/MK70F12_rng.h"
+    #include "device/MK70F12/MK70F12_rtc.h"
+    #include "device/MK70F12/MK70F12_sdhc.h"
+    #include "device/MK70F12/MK70F12_sim.h"
+    #include "device/MK70F12/MK70F12_smc.h"
+    #include "device/MK70F12/MK70F12_spi.h"
+    #include "device/MK70F12/MK70F12_tsi.h"
+    #include "device/MK70F12/MK70F12_uart.h"
+    #include "device/MK70F12/MK70F12_usb.h"
+    #include "device/MK70F12/MK70F12_usbdcd.h"
+    #include "device/MK70F12/MK70F12_usbhs.h"
+    #include "device/MK70F12/MK70F12_vref.h"
+    #include "device/MK70F12/MK70F12_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK70F12/MK70F12.h"
+
+#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
+    defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
+    defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK70F15/MK70F15_adc.h"
+    #include "device/MK70F15/MK70F15_aips.h"
+    #include "device/MK70F15/MK70F15_axbs.h"
+    #include "device/MK70F15/MK70F15_can.h"
+    #include "device/MK70F15/MK70F15_cau.h"
+    #include "device/MK70F15/MK70F15_cmp.h"
+    #include "device/MK70F15/MK70F15_cmt.h"
+    #include "device/MK70F15/MK70F15_crc.h"
+    #include "device/MK70F15/MK70F15_dac.h"
+    #include "device/MK70F15/MK70F15_ddr.h"
+    #include "device/MK70F15/MK70F15_dma.h"
+    #include "device/MK70F15/MK70F15_dmamux.h"
+    #include "device/MK70F15/MK70F15_enet.h"
+    #include "device/MK70F15/MK70F15_ewm.h"
+    #include "device/MK70F15/MK70F15_fb.h"
+    #include "device/MK70F15/MK70F15_fmc.h"
+    #include "device/MK70F15/MK70F15_ftfe.h"
+    #include "device/MK70F15/MK70F15_ftm.h"
+    #include "device/MK70F15/MK70F15_gpio.h"
+    #include "device/MK70F15/MK70F15_i2c.h"
+    #include "device/MK70F15/MK70F15_i2s.h"
+    #include "device/MK70F15/MK70F15_lcdc.h"
+    #include "device/MK70F15/MK70F15_llwu.h"
+    #include "device/MK70F15/MK70F15_lmem.h"
+    #include "device/MK70F15/MK70F15_lptmr.h"
+    #include "device/MK70F15/MK70F15_mcg.h"
+    #include "device/MK70F15/MK70F15_mcm.h"
+    #include "device/MK70F15/MK70F15_mpu.h"
+    #include "device/MK70F15/MK70F15_nfc.h"
+    #include "device/MK70F15/MK70F15_nv.h"
+    #include "device/MK70F15/MK70F15_osc.h"
+    #include "device/MK70F15/MK70F15_pdb.h"
+    #include "device/MK70F15/MK70F15_pit.h"
+    #include "device/MK70F15/MK70F15_pmc.h"
+    #include "device/MK70F15/MK70F15_port.h"
+    #include "device/MK70F15/MK70F15_rcm.h"
+    #include "device/MK70F15/MK70F15_rfsys.h"
+    #include "device/MK70F15/MK70F15_rfvbat.h"
+    #include "device/MK70F15/MK70F15_rng.h"
+    #include "device/MK70F15/MK70F15_rtc.h"
+    #include "device/MK70F15/MK70F15_sdhc.h"
+    #include "device/MK70F15/MK70F15_sim.h"
+    #include "device/MK70F15/MK70F15_smc.h"
+    #include "device/MK70F15/MK70F15_spi.h"
+    #include "device/MK70F15/MK70F15_tsi.h"
+    #include "device/MK70F15/MK70F15_uart.h"
+    #include "device/MK70F15/MK70F15_usb.h"
+    #include "device/MK70F15/MK70F15_usbdcd.h"
+    #include "device/MK70F15/MK70F15_usbhs.h"
+    #include "device/MK70F15/MK70F15_vref.h"
+    #include "device/MK70F15/MK70F15_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK70F15/MK70F15.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \
+    defined(CPU_MK70FX512VMJ15WS))
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK70F12WS/MK70F12WS_adc.h"
+    #include "device/MK70F12WS/MK70F12WS_aips.h"
+    #include "device/MK70F12WS/MK70F12WS_axbs.h"
+    #include "device/MK70F12WS/MK70F12WS_can.h"
+    #include "device/MK70F12WS/MK70F12WS_cau.h"
+    #include "device/MK70F12WS/MK70F12WS_cmp.h"
+    #include "device/MK70F12WS/MK70F12WS_cmt.h"
+    #include "device/MK70F12WS/MK70F12WS_crc.h"
+    #include "device/MK70F12WS/MK70F12WS_dac.h"
+    #include "device/MK70F12WS/MK70F12WS_ddr.h"
+    #include "device/MK70F12WS/MK70F12WS_dma.h"
+    #include "device/MK70F12WS/MK70F12WS_dmamux.h"
+    #include "device/MK70F12WS/MK70F12WS_dry.h"
+    #include "device/MK70F12WS/MK70F12WS_enet.h"
+    #include "device/MK70F12WS/MK70F12WS_ewm.h"
+    #include "device/MK70F12WS/MK70F12WS_fb.h"
+    #include "device/MK70F12WS/MK70F12WS_fmc.h"
+    #include "device/MK70F12WS/MK70F12WS_ftfe.h"
+    #include "device/MK70F12WS/MK70F12WS_ftm.h"
+    #include "device/MK70F12WS/MK70F12WS_gpio.h"
+    #include "device/MK70F12WS/MK70F12WS_i2c.h"
+    #include "device/MK70F12WS/MK70F12WS_i2s.h"
+    #include "device/MK70F12WS/MK70F12WS_lcdc.h"
+    #include "device/MK70F12WS/MK70F12WS_llwu.h"
+    #include "device/MK70F12WS/MK70F12WS_lmem.h"
+    #include "device/MK70F12WS/MK70F12WS_lptmr.h"
+    #include "device/MK70F12WS/MK70F12WS_mcg.h"
+    #include "device/MK70F12WS/MK70F12WS_mcm.h"
+    #include "device/MK70F12WS/MK70F12WS_mpu.h"
+    #include "device/MK70F12WS/MK70F12WS_nfc.h"
+    #include "device/MK70F12WS/MK70F12WS_nv.h"
+    #include "device/MK70F12WS/MK70F12WS_osc.h"
+    #include "device/MK70F12WS/MK70F12WS_pdb.h"
+    #include "device/MK70F12WS/MK70F12WS_pit.h"
+    #include "device/MK70F12WS/MK70F12WS_pmc.h"
+    #include "device/MK70F12WS/MK70F12WS_port.h"
+    #include "device/MK70F12WS/MK70F12WS_rcm.h"
+    #include "device/MK70F12WS/MK70F12WS_rfsys.h"
+    #include "device/MK70F12WS/MK70F12WS_rfvbat.h"
+    #include "device/MK70F12WS/MK70F12WS_rng.h"
+    #include "device/MK70F12WS/MK70F12WS_rtc.h"
+    #include "device/MK70F12WS/MK70F12WS_sdhc.h"
+    #include "device/MK70F12WS/MK70F12WS_sim.h"
+    #include "device/MK70F12WS/MK70F12WS_smc.h"
+    #include "device/MK70F12WS/MK70F12WS_spi.h"
+    #include "device/MK70F12WS/MK70F12WS_tsi.h"
+    #include "device/MK70F12WS/MK70F12WS_uart.h"
+    #include "device/MK70F12WS/MK70F12WS_usb.h"
+    #include "device/MK70F12WS/MK70F12WS_usbdcd.h"
+    #include "device/MK70F12WS/MK70F12WS_usbhs.h"
+    #include "device/MK70F12WS/MK70F12WS_vref.h"
+    #include "device/MK70F12WS/MK70F12WS_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK70F12WS/MK70F12WS.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \
+    defined(CPU_MK70FX512VMJ15WS))
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MK70F15WS/MK70F15WS_adc.h"
+    #include "device/MK70F15WS/MK70F15WS_aips.h"
+    #include "device/MK70F15WS/MK70F15WS_axbs.h"
+    #include "device/MK70F15WS/MK70F15WS_can.h"
+    #include "device/MK70F15WS/MK70F15WS_cau.h"
+    #include "device/MK70F15WS/MK70F15WS_cmp.h"
+    #include "device/MK70F15WS/MK70F15WS_cmt.h"
+    #include "device/MK70F15WS/MK70F15WS_crc.h"
+    #include "device/MK70F15WS/MK70F15WS_dac.h"
+    #include "device/MK70F15WS/MK70F15WS_ddr.h"
+    #include "device/MK70F15WS/MK70F15WS_dma.h"
+    #include "device/MK70F15WS/MK70F15WS_dmamux.h"
+    #include "device/MK70F15WS/MK70F15WS_dry.h"
+    #include "device/MK70F15WS/MK70F15WS_enet.h"
+    #include "device/MK70F15WS/MK70F15WS_ewm.h"
+    #include "device/MK70F15WS/MK70F15WS_fb.h"
+    #include "device/MK70F15WS/MK70F15WS_fmc.h"
+    #include "device/MK70F15WS/MK70F15WS_ftfe.h"
+    #include "device/MK70F15WS/MK70F15WS_ftm.h"
+    #include "device/MK70F15WS/MK70F15WS_gpio.h"
+    #include "device/MK70F15WS/MK70F15WS_i2c.h"
+    #include "device/MK70F15WS/MK70F15WS_i2s.h"
+    #include "device/MK70F15WS/MK70F15WS_lcdc.h"
+    #include "device/MK70F15WS/MK70F15WS_llwu.h"
+    #include "device/MK70F15WS/MK70F15WS_lmem.h"
+    #include "device/MK70F15WS/MK70F15WS_lptmr.h"
+    #include "device/MK70F15WS/MK70F15WS_mcg.h"
+    #include "device/MK70F15WS/MK70F15WS_mcm.h"
+    #include "device/MK70F15WS/MK70F15WS_mpu.h"
+    #include "device/MK70F15WS/MK70F15WS_nfc.h"
+    #include "device/MK70F15WS/MK70F15WS_nv.h"
+    #include "device/MK70F15WS/MK70F15WS_osc.h"
+    #include "device/MK70F15WS/MK70F15WS_pdb.h"
+    #include "device/MK70F15WS/MK70F15WS_pit.h"
+    #include "device/MK70F15WS/MK70F15WS_pmc.h"
+    #include "device/MK70F15WS/MK70F15WS_port.h"
+    #include "device/MK70F15WS/MK70F15WS_rcm.h"
+    #include "device/MK70F15WS/MK70F15WS_rfsys.h"
+    #include "device/MK70F15WS/MK70F15WS_rfvbat.h"
+    #include "device/MK70F15WS/MK70F15WS_rng.h"
+    #include "device/MK70F15WS/MK70F15WS_rtc.h"
+    #include "device/MK70F15WS/MK70F15WS_sdhc.h"
+    #include "device/MK70F15WS/MK70F15WS_sim.h"
+    #include "device/MK70F15WS/MK70F15WS_smc.h"
+    #include "device/MK70F15WS/MK70F15WS_spi.h"
+    #include "device/MK70F15WS/MK70F15WS_tsi.h"
+    #include "device/MK70F15WS/MK70F15WS_uart.h"
+    #include "device/MK70F15WS/MK70F15WS_usb.h"
+    #include "device/MK70F15WS/MK70F15WS_usbdcd.h"
+    #include "device/MK70F15WS/MK70F15WS_usbhs.h"
+    #include "device/MK70F15WS/MK70F15WS_vref.h"
+    #include "device/MK70F15WS/MK70F15WS_wdog.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MK70F15WS/MK70F15WS.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+    #define KL25Z4_SERIES
+    /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
+    #include "device/MKL25Z4/MKL25Z4_adc.h"
+    #include "device/MKL25Z4/MKL25Z4_cmp.h"
+    #include "device/MKL25Z4/MKL25Z4_dac.h"
+    #include "device/MKL25Z4/MKL25Z4_dma.h"
+    #include "device/MKL25Z4/MKL25Z4_dmamux.h"
+    #include "device/MKL25Z4/MKL25Z4_fgpio.h"
+    #include "device/MKL25Z4/MKL25Z4_ftfa.h"
+    #include "device/MKL25Z4/MKL25Z4_gpio.h"
+    #include "device/MKL25Z4/MKL25Z4_i2c.h"
+    #include "device/MKL25Z4/MKL25Z4_llwu.h"
+    #include "device/MKL25Z4/MKL25Z4_lptmr.h"
+    #include "device/MKL25Z4/MKL25Z4_mcg.h"
+    #include "device/MKL25Z4/MKL25Z4_mcm.h"
+    #include "device/MKL25Z4/MKL25Z4_mtb.h"
+    #include "device/MKL25Z4/MKL25Z4_mtbdwt.h"
+    #include "device/MKL25Z4/MKL25Z4_nv.h"
+    #include "device/MKL25Z4/MKL25Z4_osc.h"
+    #include "device/MKL25Z4/MKL25Z4_pit.h"
+    #include "device/MKL25Z4/MKL25Z4_pmc.h"
+    #include "device/MKL25Z4/MKL25Z4_port.h"
+    #include "device/MKL25Z4/MKL25Z4_rcm.h"
+    #include "device/MKL25Z4/MKL25Z4_rom.h"
+    #include "device/MKL25Z4/MKL25Z4_rtc.h"
+    #include "device/MKL25Z4/MKL25Z4_sim.h"
+    #include "device/MKL25Z4/MKL25Z4_smc.h"
+    #include "device/MKL25Z4/MKL25Z4_spi.h"
+    #include "device/MKL25Z4/MKL25Z4_tpm.h"
+    #include "device/MKL25Z4/MKL25Z4_tsi.h"
+    #include "device/MKL25Z4/MKL25Z4_uart.h"
+    #include "device/MKL25Z4/MKL25Z4_uart0.h"
+    #include "device/MKL25Z4/MKL25Z4_usb.h"
+
+    /* CMSIS-style register definitions*/
+    #include "device/MKL25Z4/MKL25Z4.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/bsp/k64Fxxxx/project.uvproj b/bsp/k64Fxxxx/project.uvproj
new file mode 100644
index 0000000000..dad542e65d
--- /dev/null
+++ b/bsp/k64Fxxxx/project.uvproj
@@ -0,0 +1,720 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+  <SchemaVersion>1.1</SchemaVersion>
+  <Header>### uVision Project, (C) Keil Software</Header>
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MK64FN1M0xxx12</Device>
+          <Vendor>Freescale Semiconductor</Vendor>
+          <Cpu>IRAM(0x1FFF0000-0x1FFFFFFF) IRAM2(0x20000000-0x2002FFFF) IROM(0x0-0xFFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4")  FPU2 ELITTLE</Cpu>
+          <FlashUtilSpec />
+          <StartupFile>"STARTUP\Freescale\Kinetis\startup_MK64F12.s" ("Freescale MK64Xxxxxxx12 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O2511 -S0 -C0 -FO15 -FD20000000 -FC4000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000)</FlashDriverDll>
+          <DeviceId>7425</DeviceId>
+          <RegisterFile>MK64F12.H</RegisterFile>
+          <MemoryEnv />
+          <Cmp />
+          <Asm />
+          <Linker />
+          <OHString />
+          <InfinionOptionDll />
+          <SLE66CMisc />
+          <SLE66AMisc />
+          <SLE66LinkerMisc />
+          <SFDFile>SFD\Freescale\Kinetis\MK64F12.sfr</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath />
+          <IncludePath />
+          <LibPath />
+          <RegisterFilePath>Freescale\Kinetis\</RegisterFilePath>
+          <DBRegisterFilePath>Freescale\Kinetis\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rt-thread-k64f</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString />
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument />
+          <IncludeLibraryModules />
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments />
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments />
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>13</TargetSelection>
+          <SimDlls>
+            <CpuDll />
+            <CpuDllArguments />
+            <PeripheralDll />
+            <PeripheralDllArguments />
+            <InitializationFile />
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll />
+            <CpuDllArguments />
+            <PeripheralDll />
+            <PeripheralDllArguments />
+            <InitializationFile />
+            <Driver>BIN\CMSIS_AGDI.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4 />
+          <pFcarmOut />
+          <pFcarmGrp />
+          <pFcArmRoot />
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName />
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x30000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector />
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls />
+              <Define />
+              <Undefine />
+              <IncludePath>.;..\..\components\drivers\include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;applications;board;device;device\MK64F12</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls />
+              <Define />
+              <Undefine />
+              <IncludePath />
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF0000</DataAddressRange>
+            <ScatterFile />
+            <IncludeLibs />
+            <IncludeLibsPath />
+            <Misc> --keep __fsym_* --keep __vsym_* </Misc>
+            <LinkerInputFile />
+            <DisabledWarnings />
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\application.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Board</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\drv_uart.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\led.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Device</GroupName>
+          <Files>
+            <File>
+              <FileName>system_MK64F12.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>device\MK64F12\system_MK64F12.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>startup_MK64F12.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>device\TOOLCHAIN_ARM_STD\startup_MK64F12.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M4</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+</Project>
diff --git a/bsp/k64Fxxxx/rtconfig.h b/bsp/k64Fxxxx/rtconfig.h
new file mode 100644
index 0000000000..6b676e1fe5
--- /dev/null
+++ b/bsp/k64Fxxxx/rtconfig.h
@@ -0,0 +1,156 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	8
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+#define IDLE_THREAD_STACK_SIZE     1024
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+/* "Using Device Driver Framework" default="true" */
+#define RT_USING_DEVICE
+/* Using IPC in Device Driver Framework" default="true" */
+#define RT_USING_DEVICE_IPC
+/* Using Serial Device Driver Framework" default="true" */
+#define RT_USING_SERIAL
+
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+//#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_WORD_ACCESS
+/* Reentrancy (thread safe) of the FatFs module.  */
+#define RT_DFS_ELM_REENTRANT
+/* Number of volumes (logical drives) to be used. */
+#define RT_DFS_ELM_DRIVES			2
+/* #define RT_DFS_ELM_USE_LFN			1 */
+#define RT_DFS_ELM_MAX_LFN			255
+/* Maximum sector size to be handled. */
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
+
+#define RT_USING_DFS_ROMFS
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* #define RT_USING_LWIP */
+/* LwIP uses RT-Thread Memory Management */
+#define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	201
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+/* TCP sender buffer space */
+#define RT_LWIP_TCP_SND_BUF	8192
+/* TCP receive window. */
+#define RT_LWIP_TCP_WND		8192
+
+#define CHECKSUM_CHECK_TCP              0
+#define CHECKSUM_CHECK_IP               0
+#define CHECKSUM_CHECK_UDP              0
+
+#define CHECKSUM_GEN_TCP                0
+#define CHECKSUM_GEN_IP                 0
+#define CHECKSUM_GEN_UDP                0
+
+#endif
diff --git a/bsp/k64Fxxxx/rtconfig.py b/bsp/k64Fxxxx/rtconfig.py
new file mode 100644
index 0000000000..408432b6ad
--- /dev/null
+++ b/bsp/k64Fxxxx/rtconfig.py
@@ -0,0 +1,82 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -g -Wall '
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -Wl,--gc-sections,-Map=rtthread-k64f.map,-cref,-u,Reset_Handler -T K64FN1M0xxx12.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k64f.map --scatter MK64F.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
diff --git a/bsp/k64Fxxxx/template.uvproj b/bsp/k64Fxxxx/template.uvproj
new file mode 100644
index 0000000000..e5af2fdc45
--- /dev/null
+++ b/bsp/k64Fxxxx/template.uvproj
@@ -0,0 +1,400 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MK64FN1M0xxx12</Device>
+          <Vendor>Freescale Semiconductor</Vendor>
+          <Cpu>IRAM(0x1FFF0000-0x1FFFFFFF) IRAM2(0x20000000-0x2002FFFF) IROM(0x0-0xFFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4")  FPU2 ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\Freescale\Kinetis\startup_MK64F12.s" ("Freescale MK64Xxxxxxx12 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O2511 -S0 -C0 -FO15 -FD20000000 -FC4000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000)</FlashDriverDll>
+          <DeviceId>7425</DeviceId>
+          <RegisterFile>MK64F12.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\Freescale\Kinetis\MK64F12.sfr</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Freescale\Kinetis\</RegisterFilePath>
+          <DBRegisterFilePath>Freescale\Kinetis\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rt-thread-k64f</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>13</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\CMSIS_AGDI.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x30000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF0000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>

From a16a512ebd2a5f4d2c811b3876aa5976ede25d3a Mon Sep 17 00:00:00 2001
From: geniusgogo <xeonrun@gmail.com>
Date: Sun, 29 Jun 2014 00:50:37 +0800
Subject: [PATCH 19/86] change the uart name

---
 bsp/k64Fxxxx/board/board.c | 2 +-
 bsp/k64Fxxxx/board/board.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/bsp/k64Fxxxx/board/board.c b/bsp/k64Fxxxx/board/board.c
index 05f57e35e2..cdb5fcb868 100644
--- a/bsp/k64Fxxxx/board/board.c
+++ b/bsp/k64Fxxxx/board/board.c
@@ -22,7 +22,7 @@
 
 
 /**
- * @addtogroup K60
+ * @addtogroup K64
  */
 
 /*@{*/
diff --git a/bsp/k64Fxxxx/board/board.h b/bsp/k64Fxxxx/board/board.h
index a624177887..8290a03733 100644
--- a/bsp/k64Fxxxx/board/board.h
+++ b/bsp/k64Fxxxx/board/board.h
@@ -27,7 +27,7 @@
 #define K64_SRAM_END          (0x1FFF0000 + (K64_SRAM_SIZE * 1024))
 
 //#define RT_USING_UART1
-#define RT_USING_UART5
+#define RT_USING_UART0
 //#define RT_USING_UART3
 
 // <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3

From 6b7637f3b47ecfcd8d784b03752eb1b484b30ed0 Mon Sep 17 00:00:00 2001
From: geniusgogo <xeonrun@gmail.com>
Date: Wed, 2 Jul 2014 21:23:42 +0800
Subject: [PATCH 20/86] rename frdm-k64f

---
 bsp/{k64Fxxxx => frdm-k64f}/K64FN1M0xxx12.ld                      | 0
 bsp/{k64Fxxxx => frdm-k64f}/MK64F.sct                             | 0
 bsp/{k64Fxxxx => frdm-k64f}/SConscript                            | 0
 bsp/{k64Fxxxx => frdm-k64f}/SConstruct                            | 0
 bsp/{k64Fxxxx => frdm-k64f}/applications/SConscript               | 0
 bsp/{k64Fxxxx => frdm-k64f}/applications/application.c            | 0
 bsp/{k64Fxxxx => frdm-k64f}/applications/startup.c                | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/SConscript                      | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/board.c                         | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/board.h                         | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/drv_uart.c                      | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/drv_uart.h                      | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/led.c                           | 0
 bsp/{k64Fxxxx => frdm-k64f}/board/led.h                           | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12.h              | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_adc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_aips.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_axbs.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_can.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_cau.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_cmp.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_cmt.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_crc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_dac.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_dma.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_dmamux.h       | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_enet.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_ewm.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_fb.h           | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_fmc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_ftfe.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_ftm.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_gpio.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_i2c.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_i2s.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_llwu.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_lptmr.h        | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_mcg.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_mcm.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_mpu.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_nv.h           | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_osc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_pdb.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_pit.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_pmc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_port.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rcm.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rfsys.h        | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rfvbat.h       | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rng.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rtc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_sdhc.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_sim.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_smc.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_spi.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_uart.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_usb.h          | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_usbdcd.h       | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_vref.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_wdog.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/regs.h                 | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/system_MK64F12.c       | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/system_MK64F12.h       | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/SConscript                     | 0
 .../device/TOOLCHAIN_ARM_STD/startup_MK64F12.s                    | 0
 .../device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S                    | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/core_cm4.h                     | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/core_cm4_simd.h                | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/core_cmFunc.h                  | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/core_cmInstr.h                 | 0
 bsp/{k64Fxxxx => frdm-k64f}/device/fsl_device_registers.h         | 0
 bsp/{k64Fxxxx => frdm-k64f}/project.uvproj                        | 0
 bsp/{k64Fxxxx => frdm-k64f}/rtconfig.h                            | 0
 bsp/{k64Fxxxx => frdm-k64f}/rtconfig.py                           | 0
 bsp/{k64Fxxxx => frdm-k64f}/template.uvproj                       | 0
 75 files changed, 0 insertions(+), 0 deletions(-)
 rename bsp/{k64Fxxxx => frdm-k64f}/K64FN1M0xxx12.ld (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/MK64F.sct (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/SConscript (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/SConstruct (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/applications/SConscript (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/applications/application.c (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/applications/startup.c (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/SConscript (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/board.c (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/board.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/drv_uart.c (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/drv_uart.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/led.c (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/board/led.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_adc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_aips.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_axbs.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_can.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_cau.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_cmp.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_cmt.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_crc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_dac.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_dma.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_dmamux.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_enet.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_ewm.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_fb.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_fmc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_ftfe.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_ftm.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_gpio.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_i2c.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_i2s.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_llwu.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_lptmr.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_mcg.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_mcm.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_mpu.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_nv.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_osc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_pdb.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_pit.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_pmc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_port.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rcm.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rfsys.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rfvbat.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rng.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_rtc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_sdhc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_sim.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_smc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_spi.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_uart.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_usb.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_usbdcd.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_vref.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/MK64F12_wdog.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/regs.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/system_MK64F12.c (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/MK64F12/system_MK64F12.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/SConscript (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/core_cm4.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/core_cm4_simd.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/core_cmFunc.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/core_cmInstr.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/device/fsl_device_registers.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/project.uvproj (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/rtconfig.h (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/rtconfig.py (100%)
 rename bsp/{k64Fxxxx => frdm-k64f}/template.uvproj (100%)

diff --git a/bsp/k64Fxxxx/K64FN1M0xxx12.ld b/bsp/frdm-k64f/K64FN1M0xxx12.ld
similarity index 100%
rename from bsp/k64Fxxxx/K64FN1M0xxx12.ld
rename to bsp/frdm-k64f/K64FN1M0xxx12.ld
diff --git a/bsp/k64Fxxxx/MK64F.sct b/bsp/frdm-k64f/MK64F.sct
similarity index 100%
rename from bsp/k64Fxxxx/MK64F.sct
rename to bsp/frdm-k64f/MK64F.sct
diff --git a/bsp/k64Fxxxx/SConscript b/bsp/frdm-k64f/SConscript
similarity index 100%
rename from bsp/k64Fxxxx/SConscript
rename to bsp/frdm-k64f/SConscript
diff --git a/bsp/k64Fxxxx/SConstruct b/bsp/frdm-k64f/SConstruct
similarity index 100%
rename from bsp/k64Fxxxx/SConstruct
rename to bsp/frdm-k64f/SConstruct
diff --git a/bsp/k64Fxxxx/applications/SConscript b/bsp/frdm-k64f/applications/SConscript
similarity index 100%
rename from bsp/k64Fxxxx/applications/SConscript
rename to bsp/frdm-k64f/applications/SConscript
diff --git a/bsp/k64Fxxxx/applications/application.c b/bsp/frdm-k64f/applications/application.c
similarity index 100%
rename from bsp/k64Fxxxx/applications/application.c
rename to bsp/frdm-k64f/applications/application.c
diff --git a/bsp/k64Fxxxx/applications/startup.c b/bsp/frdm-k64f/applications/startup.c
similarity index 100%
rename from bsp/k64Fxxxx/applications/startup.c
rename to bsp/frdm-k64f/applications/startup.c
diff --git a/bsp/k64Fxxxx/board/SConscript b/bsp/frdm-k64f/board/SConscript
similarity index 100%
rename from bsp/k64Fxxxx/board/SConscript
rename to bsp/frdm-k64f/board/SConscript
diff --git a/bsp/k64Fxxxx/board/board.c b/bsp/frdm-k64f/board/board.c
similarity index 100%
rename from bsp/k64Fxxxx/board/board.c
rename to bsp/frdm-k64f/board/board.c
diff --git a/bsp/k64Fxxxx/board/board.h b/bsp/frdm-k64f/board/board.h
similarity index 100%
rename from bsp/k64Fxxxx/board/board.h
rename to bsp/frdm-k64f/board/board.h
diff --git a/bsp/k64Fxxxx/board/drv_uart.c b/bsp/frdm-k64f/board/drv_uart.c
similarity index 100%
rename from bsp/k64Fxxxx/board/drv_uart.c
rename to bsp/frdm-k64f/board/drv_uart.c
diff --git a/bsp/k64Fxxxx/board/drv_uart.h b/bsp/frdm-k64f/board/drv_uart.h
similarity index 100%
rename from bsp/k64Fxxxx/board/drv_uart.h
rename to bsp/frdm-k64f/board/drv_uart.h
diff --git a/bsp/k64Fxxxx/board/led.c b/bsp/frdm-k64f/board/led.c
similarity index 100%
rename from bsp/k64Fxxxx/board/led.c
rename to bsp/frdm-k64f/board/led.c
diff --git a/bsp/k64Fxxxx/board/led.h b/bsp/frdm-k64f/board/led.h
similarity index 100%
rename from bsp/k64Fxxxx/board/led.h
rename to bsp/frdm-k64f/board/led.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12.h b/bsp/frdm-k64f/device/MK64F12/MK64F12.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_adc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_adc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_adc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_aips.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_aips.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_aips.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_axbs.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_axbs.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_axbs.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_can.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_can.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_can.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_cau.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_cau.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_cau.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_cmp.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_cmp.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_cmp.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_cmt.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_cmt.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_cmt.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_crc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_crc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_crc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_dac.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_dac.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_dac.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_dma.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_dma.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_dma.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_dmamux.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_dmamux.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_dmamux.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_enet.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_enet.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_enet.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_ewm.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_ewm.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_ewm.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_fb.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_fb.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_fb.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_fmc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_fmc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_fmc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_ftfe.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_ftfe.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_ftfe.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_ftm.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_ftm.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_ftm.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_gpio.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_gpio.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_gpio.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_i2c.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_i2c.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_i2c.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_i2s.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_i2s.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_i2s.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_llwu.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_llwu.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_llwu.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_lptmr.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_lptmr.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_lptmr.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_mcg.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_mcg.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_mcg.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_mcm.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_mcm.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_mcm.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_mpu.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_mpu.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_mpu.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_nv.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_nv.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_nv.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_osc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_osc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_osc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_pdb.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_pdb.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_pdb.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_pit.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_pit.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_pit.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_pmc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_pmc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_pmc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_port.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_port.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_port.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_rcm.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_rcm.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_rcm.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_rfsys.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_rfsys.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_rfsys.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_rfvbat.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_rfvbat.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_rfvbat.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_rng.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_rng.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_rng.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_rtc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_rtc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_rtc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_sdhc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_sdhc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_sdhc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_sim.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_sim.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_sim.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_smc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_smc.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_smc.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_spi.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_spi.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_spi.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_uart.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_uart.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_uart.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_usb.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_usb.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_usb.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_usbdcd.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_usbdcd.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_usbdcd.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_vref.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_vref.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_vref.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h b/bsp/frdm-k64f/device/MK64F12/MK64F12_wdog.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/MK64F12_wdog.h
rename to bsp/frdm-k64f/device/MK64F12/MK64F12_wdog.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/regs.h b/bsp/frdm-k64f/device/MK64F12/regs.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/regs.h
rename to bsp/frdm-k64f/device/MK64F12/regs.h
diff --git a/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c b/bsp/frdm-k64f/device/MK64F12/system_MK64F12.c
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/system_MK64F12.c
rename to bsp/frdm-k64f/device/MK64F12/system_MK64F12.c
diff --git a/bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h b/bsp/frdm-k64f/device/MK64F12/system_MK64F12.h
similarity index 100%
rename from bsp/k64Fxxxx/device/MK64F12/system_MK64F12.h
rename to bsp/frdm-k64f/device/MK64F12/system_MK64F12.h
diff --git a/bsp/k64Fxxxx/device/SConscript b/bsp/frdm-k64f/device/SConscript
similarity index 100%
rename from bsp/k64Fxxxx/device/SConscript
rename to bsp/frdm-k64f/device/SConscript
diff --git a/bsp/k64Fxxxx/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s b/bsp/frdm-k64f/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s
similarity index 100%
rename from bsp/k64Fxxxx/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s
rename to bsp/frdm-k64f/device/TOOLCHAIN_ARM_STD/startup_MK64F12.s
diff --git a/bsp/k64Fxxxx/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
similarity index 100%
rename from bsp/k64Fxxxx/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
rename to bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
diff --git a/bsp/k64Fxxxx/device/core_cm4.h b/bsp/frdm-k64f/device/core_cm4.h
similarity index 100%
rename from bsp/k64Fxxxx/device/core_cm4.h
rename to bsp/frdm-k64f/device/core_cm4.h
diff --git a/bsp/k64Fxxxx/device/core_cm4_simd.h b/bsp/frdm-k64f/device/core_cm4_simd.h
similarity index 100%
rename from bsp/k64Fxxxx/device/core_cm4_simd.h
rename to bsp/frdm-k64f/device/core_cm4_simd.h
diff --git a/bsp/k64Fxxxx/device/core_cmFunc.h b/bsp/frdm-k64f/device/core_cmFunc.h
similarity index 100%
rename from bsp/k64Fxxxx/device/core_cmFunc.h
rename to bsp/frdm-k64f/device/core_cmFunc.h
diff --git a/bsp/k64Fxxxx/device/core_cmInstr.h b/bsp/frdm-k64f/device/core_cmInstr.h
similarity index 100%
rename from bsp/k64Fxxxx/device/core_cmInstr.h
rename to bsp/frdm-k64f/device/core_cmInstr.h
diff --git a/bsp/k64Fxxxx/device/fsl_device_registers.h b/bsp/frdm-k64f/device/fsl_device_registers.h
similarity index 100%
rename from bsp/k64Fxxxx/device/fsl_device_registers.h
rename to bsp/frdm-k64f/device/fsl_device_registers.h
diff --git a/bsp/k64Fxxxx/project.uvproj b/bsp/frdm-k64f/project.uvproj
similarity index 100%
rename from bsp/k64Fxxxx/project.uvproj
rename to bsp/frdm-k64f/project.uvproj
diff --git a/bsp/k64Fxxxx/rtconfig.h b/bsp/frdm-k64f/rtconfig.h
similarity index 100%
rename from bsp/k64Fxxxx/rtconfig.h
rename to bsp/frdm-k64f/rtconfig.h
diff --git a/bsp/k64Fxxxx/rtconfig.py b/bsp/frdm-k64f/rtconfig.py
similarity index 100%
rename from bsp/k64Fxxxx/rtconfig.py
rename to bsp/frdm-k64f/rtconfig.py
diff --git a/bsp/k64Fxxxx/template.uvproj b/bsp/frdm-k64f/template.uvproj
similarity index 100%
rename from bsp/k64Fxxxx/template.uvproj
rename to bsp/frdm-k64f/template.uvproj

From 857ac7e6e696bf0d7ecf90bc2c96a97a8512f740 Mon Sep 17 00:00:00 2001
From: geniusgogo <xeonrun@gmail.com>
Date: Wed, 2 Jul 2014 22:42:29 +0800
Subject: [PATCH 21/86] rename frdm-k64f bsp, support gcc compile

---
 .../device/TOOLCHAIN_GCC_ARM/startup.c        | 61 +++++++++++++++++++
 .../device/TOOLCHAIN_GCC_ARM/startup.h        | 44 +++++++++++++
 2 files changed, 105 insertions(+)
 create mode 100644 bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.c
 create mode 100644 bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.h

diff --git a/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.c b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.c
new file mode 100644
index 0000000000..6614a149a2
--- /dev/null
+++ b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdint.h>
+#include "startup.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void init_data_bss(void)
+{
+    extern char __bss_start[];
+    extern char __bss_end[];
+
+    /* Declare a counter we'll use in all of the copy loops */
+    uint32_t n;
+
+    uint8_t * bss_start, * bss_end;
+
+	bss_start = (uint8_t *)__bss_start;
+	bss_end = (uint8_t *)__bss_end;
+
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.h b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.h
new file mode 100644
index 0000000000..9e5712ecc6
--- /dev/null
+++ b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+

From 1546274d899b5970edc674fa1767bd8403b0b417 Mon Sep 17 00:00:00 2001
From: geniusgogo <xeonrun@gmail.com>
Date: Thu, 3 Jul 2014 22:08:29 +0800
Subject: [PATCH 22/86] fixed bsp/frdm-k64f gcc compile

---
 bsp/frdm-k64f/K64FN1M0xxx12.ld                  | 17 +++++++++++++++--
 bsp/frdm-k64f/device/SConscript                 |  6 +++---
 .../device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S  |  4 +++-
 bsp/frdm-k64f/rtconfig.py                       | 10 +++++-----
 4 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/bsp/frdm-k64f/K64FN1M0xxx12.ld b/bsp/frdm-k64f/K64FN1M0xxx12.ld
index 5bf14b145e..91516c7446 100644
--- a/bsp/frdm-k64f/K64FN1M0xxx12.ld
+++ b/bsp/frdm-k64f/K64FN1M0xxx12.ld
@@ -77,6 +77,19 @@ SECTIONS
         *(.dtors)
 
         *(.rodata*)
+/* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
 
         KEEP(*(.eh_frame*))
     } > FLASH
@@ -127,7 +140,7 @@ SECTIONS
         __data_end__ = .;
 
     } > RAM
-
+    __bss_start = .;
     .bss :
     {
         __bss_start__ = .;
@@ -135,7 +148,7 @@ SECTIONS
         *(COMMON)
         __bss_end__ = .;
     } > RAM
-
+    __bss_end = .;
     .heap :
     {
         __end__ = .;
diff --git a/bsp/frdm-k64f/device/SConscript b/bsp/frdm-k64f/device/SConscript
index e196b1595a..b56031b5cf 100644
--- a/bsp/frdm-k64f/device/SConscript
+++ b/bsp/frdm-k64f/device/SConscript
@@ -5,18 +5,18 @@ from building import *
 # get current directory
 cwd = GetCurrentDir()
 
-
+path = [cwd, cwd + '/MK64F12']
 src = Glob('MK64F12/*.c')
 
 #add for startup script 
 if rtconfig.CROSS_TOOL == 'gcc':
      src = src + ['TOOLCHAIN_GCC_ARM/startup_MK64F12.S']
+     src = src + ['TOOLCHAIN_GCC_ARM/startup.c']
+     path += [cwd + 'TOOLCHAIN_GCC_ARM']
 elif rtconfig.CROSS_TOOL == 'keil':
      src = src + ['TOOLCHAIN_ARM_STD/startup_MK64F12.s']
 # elif rtconfig.CROSS_TOOL == 'iar':
 
-path = [cwd, cwd + '/MK64F12']
-
 #CPPDEFINES = ['']
 group = DefineGroup('Device', src, depend = [''], CPPPATH = path)
 #CPPDEFINES = CPPDEFINES)
diff --git a/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
index 5978e7c444..3b2fe5d214 100644
--- a/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
+++ b/bsp/frdm-k64f/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
@@ -229,7 +229,9 @@ disable_watchdog:
 
     ldr   r0, =SystemInit
     blx   r0
-    ldr   r0, =_start
+    ldr   r0, =init_data_bss
+    blx   r0    
+    ldr   r0, =main
     bx    r0
     .pool
     .size Reset_Handler, . - Reset_Handler
diff --git a/bsp/frdm-k64f/rtconfig.py b/bsp/frdm-k64f/rtconfig.py
index 408432b6ad..a40c66dcf2 100644
--- a/bsp/frdm-k64f/rtconfig.py
+++ b/bsp/frdm-k64f/rtconfig.py
@@ -12,10 +12,10 @@ if os.getenv('RTT_CC'):
 # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
 if  CROSS_TOOL == 'gcc':
 	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
+	EXEC_PATH 	= r'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
 elif CROSS_TOOL == 'keil':
 	PLATFORM 	= 'armcc'
-	EXEC_PATH 	= 'C:/Keil'
+	EXEC_PATH 	= r'C:/Keil'
 elif CROSS_TOOL == 'iar':
     print '================ERROR============================'
     print 'Not support iar yet!'
@@ -40,9 +40,9 @@ if PLATFORM == 'gcc':
     OBJCPY = PREFIX + 'objcopy'
 
     DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
-    CFLAGS = DEVICE + ' -g -Wall '
-    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -Wl,--gc-sections,-Map=rtthread-k64f.map,-cref,-u,Reset_Handler -T K64FN1M0xxx12.ld'
+    CFLAGS = DEVICE + ' -g -Wall -D__ASSEMBLY__ -D__FPU_USED'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -lm -lgcc -lc' + '  -nostartfiles -Wl,--gc-sections,-Map=rtthread-k64f.map,-cref,-u,Reset_Handler -T K64FN1M0xxx12.ld'
 
     CPATH = ''
     LPATH = ''

From d0debf9892c21f04b209e6c837b3e3d0af0598d0 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 10 Jul 2014 13:32:16 +0800
Subject: [PATCH 23/86] [Drivers] Make code cleanup in serial framework.

---
 components/drivers/include/drivers/serial.h | 6 ++++++
 components/drivers/serial/serial.c          | 3 ---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h
index 41132ed916..9655820736 100644
--- a/components/drivers/include/drivers/serial.h
+++ b/components/drivers/include/drivers/serial.h
@@ -30,9 +30,15 @@
 
 #include <rtthread.h>
 
+#define BAUD_RATE_2400                  2400
 #define BAUD_RATE_4800                  4800
 #define BAUD_RATE_9600                  9600
+#define BAUD_RATE_38400                 38400
+#define BAUD_RATE_57600                 57600
 #define BAUD_RATE_115200                115200
+#define BAUD_RATE_230400                230400
+#define BAUD_RATE_460800                460800
+#define BAUD_RATE_921600                921600
 
 #define DATA_BITS_5                     5
 #define DATA_BITS_6                     6
diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c
index 622d2cd68c..61c03fa955 100644
--- a/components/drivers/serial/serial.c
+++ b/components/drivers/serial/serial.c
@@ -162,9 +162,6 @@ static rt_err_t rt_serial_init(struct rt_device *dev)
             rt_data_queue_init(&(serial->tx_dq), RT_SERIAL_TX_DATAQUEUE_SIZE,
                                RT_SERIAL_TX_DATAQUEUE_LWM, RT_NULL);
         }
-
-        /* set activated */
-        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
     }
 
     return result;

From 1e7b0894949be4fe86c31ddf3c1bd754908459aa Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 10 Jul 2014 13:34:52 +0800
Subject: [PATCH 24/86] [Kernel] Remove rt_device_init_all implemetation.

---
 src/device.c | 39 +++------------------------------------
 1 file changed, 3 insertions(+), 36 deletions(-)

diff --git a/src/device.c b/src/device.c
index 7ee130041c..2bb3cc0f9c 100644
--- a/src/device.c
+++ b/src/device.c
@@ -79,45 +79,12 @@ RTM_EXPORT(rt_device_unregister);
  * This function initializes all registered device driver
  *
  * @return the error code, RT_EOK on successfully.
+ *
+ * @deprecated This function is not needed because the initialization 
+ *             of a device is performed when applicaiton opens it.
  */
 rt_err_t rt_device_init_all(void)
 {
-    struct rt_device *device;
-    struct rt_list_node *node;
-    struct rt_object_information *information;
-    register rt_err_t result;
-
-    extern struct rt_object_information rt_object_container[];
-
-    information = &rt_object_container[RT_Object_Class_Device];
-
-    /* for each device */
-    for (node  = information->object_list.next;
-         node != &(information->object_list);
-         node  = node->next)
-    {
-        rt_err_t (*init)(rt_device_t dev);
-        device = (struct rt_device *)rt_list_entry(node,
-                                                   struct rt_object,
-                                                   list);
-
-        /* get device init handler */
-        init = device->init;
-        if (init != RT_NULL && !(device->flag & RT_DEVICE_FLAG_ACTIVATED))
-        {
-            result = init(device);
-            if (result != RT_EOK)
-            {
-                rt_kprintf("To initialize device:%s failed. The error code is %d\n",
-                           device->parent.name, result);
-            }
-            else
-            {
-                device->flag |= RT_DEVICE_FLAG_ACTIVATED;
-            }
-        }
-    }
-
     return RT_EOK;
 }
 

From f44f6caadb13cfd88d0f45576214dc474dcedaf7 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 10 Jul 2014 13:35:28 +0800
Subject: [PATCH 25/86] [Finsh] Fix command line size issue in finsh.

---
 components/finsh/shell.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/finsh/shell.c b/components/finsh/shell.c
index 393d68713c..ae099e7e7c 100644
--- a/components/finsh/shell.c
+++ b/components/finsh/shell.c
@@ -530,6 +530,12 @@ void finsh_thread_entry(void* parameter)
             ch = 0;
             shell->line_position ++;
             shell->line_curpos++;
+			if (shell->line_position >= 80) 
+			{
+				/* clear command line */
+				shell->line_position = 0;
+				shell->line_curpos = 0;
+			}
         } /* end of device read */
     }
 }

From 0ddc739a1873a3fdb2b3045780c9528aab50a27f Mon Sep 17 00:00:00 2001
From: root <root@localhost.localdomain>
Date: Thu, 10 Jul 2014 23:18:03 -0800
Subject: [PATCH 26/86] add some comments of lwip porting

---
 bsp/mini2440/.dm9000.c.swp                    | Bin 0 -> 16384 bytes
 components/net/lwip-1.4.1/src/arch/sys_arch.c |  46 +++++++++++++++++-
 2 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 bsp/mini2440/.dm9000.c.swp

diff --git a/bsp/mini2440/.dm9000.c.swp b/bsp/mini2440/.dm9000.c.swp
new file mode 100644
index 0000000000000000000000000000000000000000..6fd20765798cdbc9ffd0811c228ec3a4c44db56a
GIT binary patch
literal 16384
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diff --git a/components/net/lwip-1.4.1/src/arch/sys_arch.c b/components/net/lwip-1.4.1/src/arch/sys_arch.c
index 356dc101cf..287c861f04 100644
--- a/components/net/lwip-1.4.1/src/arch/sys_arch.c
+++ b/components/net/lwip-1.4.1/src/arch/sys_arch.c
@@ -29,6 +29,11 @@
 
 #include <string.h>
 
+/*
+ * Initialize the network interface device
+ *
+ * @return the operation status, ERR_OK on OK, ERR_IF on error
+ */
 static err_t netif_device_init(struct netif *netif)
 {
     struct eth_device *ethif;
@@ -53,7 +58,9 @@ static err_t netif_device_init(struct netif *netif)
 
     return ERR_IF;
 }
-
+/*
+ * Initialize the ethernetif layer and set network interface device up
+ */
 static void tcpip_init_done_callback(void *arg)
 {
     rt_device_t device;
@@ -182,6 +189,11 @@ void lwip_sys_init(void)
     lwip_system_init();
 }
 
+/*
+ * Create a new semaphore
+ *
+ * @return the operation status, ERR_OK on OK; others on error
+ */
 err_t sys_sem_new(sys_sem_t *sem, u8_t count)
 {
     static unsigned short counter = 0;
@@ -204,17 +216,31 @@ err_t sys_sem_new(sys_sem_t *sem, u8_t count)
     }
 }
 
+/*
+ * Deallocate a semaphore
+ */
 void sys_sem_free(sys_sem_t *sem)
 {
     RT_DEBUG_NOT_IN_INTERRUPT;
     rt_sem_delete(*sem);
 }
 
+/*
+ * Signal a semaphore
+ */
 void sys_sem_signal(sys_sem_t *sem)
 {
     rt_sem_release(*sem);
 }
 
+/*
+ * Block the thread while waiting for the semaphore to be signaled
+ *
+ * @return If the timeout argument is non-zero, it will return the number of milliseconds
+ *         spent waiting for the semaphore to be signaled; If the semaphore isn't signaled
+ *         within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't 
+ *         wait for the semaphore, it will return zero
+ */
 u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout)
 {
     rt_err_t ret;
@@ -354,6 +380,11 @@ void sys_mutex_set_invalid(sys_mutex_t *mutex)
 
 /* ====================== Mailbox ====================== */
 
+/*
+ * Create an empty mailbox for maximum "size" elements
+ *
+ * @return the operation status, ERR_OK on OK; others on error
+ */
 err_t sys_mbox_new(sys_mbox_t *mbox, int size)
 {
     static unsigned short counter = 0;
@@ -376,6 +407,9 @@ err_t sys_mbox_new(sys_mbox_t *mbox, int size)
     return ERR_MEM;
 }
 
+/*
+ * Deallocate a mailbox
+ */
 void sys_mbox_free(sys_mbox_t *mbox)
 {
     RT_DEBUG_NOT_IN_INTERRUPT;
@@ -399,6 +433,11 @@ void sys_mbox_post(sys_mbox_t *mbox, void *msg)
     return;
 }
 
+/*
+ * Try to post the "msg" to the mailbox
+ *
+ * @return return ERR_OK if the "msg" is posted, ERR_MEM if the mailbox is full
+ */
 err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
 {
     if (rt_mb_send(*mbox, (rt_uint32_t)msg) == RT_EOK)
@@ -502,6 +541,11 @@ void sys_mbox_set_invalid(sys_mbox_t *mbox)
 
 /* ====================== System ====================== */
 
+/*
+ * Start a new thread named "name" with priority "prio" that will begin
+ * its execution in the function "thread()". The "arg" argument will be
+ * passed as an argument to the thread() function
+ */
 sys_thread_t sys_thread_new(const char    *name,
                             lwip_thread_fn thread,
                             void          *arg,

From 6b75e5372c5d33ae4f01050a2558ec8665949842 Mon Sep 17 00:00:00 2001
From: hduffddybz <ffddybz123@126.com>
Date: Thu, 10 Jul 2014 23:57:14 -0800
Subject: [PATCH 27/86] delete .dm9000.c.swp

---
 bsp/mini2440/.dm9000.c.swp | Bin 16384 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 bsp/mini2440/.dm9000.c.swp

diff --git a/bsp/mini2440/.dm9000.c.swp b/bsp/mini2440/.dm9000.c.swp
deleted file mode 100644
index 6fd20765798cdbc9ffd0811c228ec3a4c44db56a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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From 7e63d176531200a1442ec9ce748e05b3e0968ab8 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 09:28:28 +0800
Subject: [PATCH 28/86] [bsp] Change the output files directory in LPC2478.

---
 bsp/lpc2478/template.uvproj | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/bsp/lpc2478/template.uvproj b/bsp/lpc2478/template.uvproj
index 52184f7666..e32a423b91 100644
--- a/bsp/lpc2478/template.uvproj
+++ b/bsp/lpc2478/template.uvproj
@@ -30,6 +30,7 @@
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
           <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
           <IncludePath></IncludePath>
@@ -43,14 +44,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\obj\</OutputDirectory>
+          <OutputDirectory>.\build\</OutputDirectory>
           <OutputName>rtthread-lpc</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
           <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\obj\</ListingPath>
+          <ListingPath>.\build\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -61,6 +62,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -95,6 +98,7 @@
           <StopOnExitCode>3</StopOnExitCode>
           <CustomArgument></CustomArgument>
           <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
           <SimDllName>SARM.DLL</SimDllName>
@@ -128,12 +132,13 @@
           <Target>
             <UseTarget>1</UseTarget>
             <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>0</RunToMain>
+            <RunToMain>1</RunToMain>
             <RestoreBreakpoints>1</RestoreBreakpoints>
             <RestoreWatchpoints>1</RestoreWatchpoints>
             <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
             <RestoreFunctions>0</RestoreFunctions>
             <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
           </Target>
           <RunDebugAfterBuild>0</RunDebugAfterBuild>
           <TargetSelection>7</TargetSelection>
@@ -162,9 +167,14 @@
             <Capability>1</Capability>
             <DriverSelection>4096</DriverSelection>
           </Flash1>
+          <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2ARM.DLL</Flash2>
           <Flash3>"LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1)</Flash3>
           <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
           <ArmAdsMisc>
@@ -342,6 +352,7 @@
             <Rwpi>0</Rwpi>
             <wLevel>0</wLevel>
             <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
             <VariousControls>
               <MiscControls></MiscControls>
               <Define></Define>
@@ -357,6 +368,7 @@
             <SplitLS>0</SplitLS>
             <SwStkChk>0</SwStkChk>
             <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
             <VariousControls>
               <MiscControls></MiscControls>
               <Define></Define>

From 3e49b37469af6ba534db60b8e5d56a5f3a90f436 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 09:34:21 +0800
Subject: [PATCH 29/86] [build] Update travis.yml configuration file

---
 .travis.yml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index 3368e7610c..f8b847bba6 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -61,3 +61,6 @@ env:
   - RTT_BSP='xplorer4330/m4' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='frdm-k64f' RTT_ROOT_CHAIN='sourcery-arm'
+

From 5c5928f8226698113cf0111346b01b56dedcaa72 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 09:40:37 +0800
Subject: [PATCH 30/86] [bsp] Remove none-released bsp

---
 bsp/K60Fxxxx/SConscript                 |   14 -
 bsp/K60Fxxxx/SConstruct                 |   37 -
 bsp/K60Fxxxx/applications/SConscript    |   11 -
 bsp/K60Fxxxx/applications/application.c |  120 --
 bsp/K60Fxxxx/applications/startup.c     |  125 --
 bsp/K60Fxxxx/drivers/SConscript         |   12 -
 bsp/K60Fxxxx/drivers/board.c            |   88 -
 bsp/K60Fxxxx/drivers/board.h            |   58 -
 bsp/K60Fxxxx/drivers/drv_uart.c         |  257 ---
 bsp/K60Fxxxx/drivers/drv_uart.h         |   34 -
 bsp/K60Fxxxx/drivers/led.c              |   55 -
 bsp/K60Fxxxx/drivers/led.h              |   27 -
 bsp/K60Fxxxx/drivers/startup_MK60F12.s  |  774 ---------
 bsp/K60Fxxxx/drivers/system_MK60F12.c   |  366 -----
 bsp/K60Fxxxx/readme.txt                 |    8 -
 bsp/K60Fxxxx/rtconfig.h                 |  156 --
 bsp/K60Fxxxx/rtconfig.py                |   83 -
 bsp/K60Fxxxx/template.uvproj            |  394 -----
 bsp/lpc1114/application.c               |   26 -
 bsp/lpc1114/board.c                     |   66 -
 bsp/lpc1114/board.h                     |   20 -
 bsp/lpc1114/project.uvopt               | 1947 -----------------------
 bsp/lpc1114/project.uvproj              |  549 -------
 bsp/lpc1114/rtconfig.h                  |   67 -
 bsp/lpc1114/startup.c                   |  116 --
 bsp/lpc1114/uart.c                      |  266 ----
 bsp/lpc1114/uart.h                      |    6 -
 bsp/lpc122x/FLASH.ini                   |   28 -
 bsp/lpc122x/application.c               |   82 -
 bsp/lpc122x/board.c                     |   67 -
 bsp/lpc122x/board.h                     |   20 -
 bsp/lpc122x/lpc122x.uvopt               |  636 --------
 bsp/lpc122x/lpc122x.uvproj              |  562 -------
 bsp/lpc122x/rtconfig.h                  |   67 -
 bsp/lpc122x/startup.c                   |  116 --
 bsp/lpc122x/uart.c                      |  295 ----
 bsp/lpc122x/uart.h                      |    6 -
 bsp/sam7s/application.c                 |   26 -
 bsp/sam7s/board.c                       |  172 --
 bsp/sam7s/board.h                       |   69 -
 bsp/sam7s/project.Opt                   |   76 -
 bsp/sam7s/project.Uv2                   |  139 --
 bsp/sam7s/rtconfig.h                    |   84 -
 bsp/sam7s/sam7s_rom.lds                 |   48 -
 bsp/sam7s/startup.c                     |  120 --
 45 files changed, 8295 deletions(-)
 delete mode 100644 bsp/K60Fxxxx/SConscript
 delete mode 100644 bsp/K60Fxxxx/SConstruct
 delete mode 100644 bsp/K60Fxxxx/applications/SConscript
 delete mode 100644 bsp/K60Fxxxx/applications/application.c
 delete mode 100644 bsp/K60Fxxxx/applications/startup.c
 delete mode 100644 bsp/K60Fxxxx/drivers/SConscript
 delete mode 100644 bsp/K60Fxxxx/drivers/board.c
 delete mode 100644 bsp/K60Fxxxx/drivers/board.h
 delete mode 100644 bsp/K60Fxxxx/drivers/drv_uart.c
 delete mode 100644 bsp/K60Fxxxx/drivers/drv_uart.h
 delete mode 100644 bsp/K60Fxxxx/drivers/led.c
 delete mode 100644 bsp/K60Fxxxx/drivers/led.h
 delete mode 100644 bsp/K60Fxxxx/drivers/startup_MK60F12.s
 delete mode 100644 bsp/K60Fxxxx/drivers/system_MK60F12.c
 delete mode 100644 bsp/K60Fxxxx/readme.txt
 delete mode 100644 bsp/K60Fxxxx/rtconfig.h
 delete mode 100644 bsp/K60Fxxxx/rtconfig.py
 delete mode 100644 bsp/K60Fxxxx/template.uvproj
 delete mode 100644 bsp/lpc1114/application.c
 delete mode 100644 bsp/lpc1114/board.c
 delete mode 100644 bsp/lpc1114/board.h
 delete mode 100644 bsp/lpc1114/project.uvopt
 delete mode 100644 bsp/lpc1114/project.uvproj
 delete mode 100644 bsp/lpc1114/rtconfig.h
 delete mode 100644 bsp/lpc1114/startup.c
 delete mode 100644 bsp/lpc1114/uart.c
 delete mode 100644 bsp/lpc1114/uart.h
 delete mode 100644 bsp/lpc122x/FLASH.ini
 delete mode 100644 bsp/lpc122x/application.c
 delete mode 100644 bsp/lpc122x/board.c
 delete mode 100644 bsp/lpc122x/board.h
 delete mode 100644 bsp/lpc122x/lpc122x.uvopt
 delete mode 100644 bsp/lpc122x/lpc122x.uvproj
 delete mode 100644 bsp/lpc122x/rtconfig.h
 delete mode 100644 bsp/lpc122x/startup.c
 delete mode 100644 bsp/lpc122x/uart.c
 delete mode 100644 bsp/lpc122x/uart.h
 delete mode 100644 bsp/sam7s/application.c
 delete mode 100644 bsp/sam7s/board.c
 delete mode 100644 bsp/sam7s/board.h
 delete mode 100644 bsp/sam7s/project.Opt
 delete mode 100644 bsp/sam7s/project.Uv2
 delete mode 100644 bsp/sam7s/rtconfig.h
 delete mode 100644 bsp/sam7s/sam7s_rom.lds
 delete mode 100644 bsp/sam7s/startup.c

diff --git a/bsp/K60Fxxxx/SConscript b/bsp/K60Fxxxx/SConscript
deleted file mode 100644
index fe0ae941ae..0000000000
--- a/bsp/K60Fxxxx/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# for module compiling
-import os
-Import('RTT_ROOT')
-
-cwd = str(Dir('#'))
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')
diff --git a/bsp/K60Fxxxx/SConstruct b/bsp/K60Fxxxx/SConstruct
deleted file mode 100644
index c9ae47945f..0000000000
--- a/bsp/K60Fxxxx/SConstruct
+++ /dev/null
@@ -1,37 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread-k60.' + rtconfig.TARGET_EXT
-
-env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-if rtconfig.PLATFORM == 'iar':
-	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
-	env.Replace(ARFLAGS = [''])
-	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
-
-# build program 
-env.Program(TARGET, objs)
-
-# end building 
-EndBuilding(TARGET)
diff --git a/bsp/K60Fxxxx/applications/SConscript b/bsp/K60Fxxxx/applications/SConscript
deleted file mode 100644
index 01eb940dfb..0000000000
--- a/bsp/K60Fxxxx/applications/SConscript
+++ /dev/null
@@ -1,11 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/K60Fxxxx/applications/application.c b/bsp/K60Fxxxx/applications/application.c
deleted file mode 100644
index c46ad36dac..0000000000
--- a/bsp/K60Fxxxx/applications/application.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2009-01-05     Bernard      the first version
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-/**
- * @addtogroup k60
- */
-/*@{*/
-
-#include <stdio.h>
-
-#include "MK60F12.h"
-#include <board.h>
-#include <rtthread.h>
-
-#include "led.h"
-
-#ifdef RT_USING_LWIP
-#include <lwip/sys.h>
-#include <lwip/api.h>
-#include <netif/ethernetif.h>
-#include "stm32_eth.h"
-#endif
-
-void rt_init_thread_entry(void* parameter)
-{
-    /* LwIP Initialization */
-#ifdef RT_USING_LWIP
-    {
-        extern void lwip_sys_init(void);
-
-        /* register ethernetif device */
-        eth_system_device_init();
-
-        rt_hw_stm32_eth_init();
-        /* re-init device driver */
-        rt_device_init_all();
-
-        /* init lwip system */
-        lwip_sys_init();
-        rt_kprintf("TCP/IP initialized!\n");
-    }
-#endif
-
-//FS
-
-//GUI
-}
-
-float f_var1;
-float f_var2;
-float f_var3;
-float f_var4;
-
-ALIGN(RT_ALIGN_SIZE)
-static char thread_led1_stack[1024];
-struct rt_thread thread_led1;
-static void rt_thread_entry_led1(void* parameter)
-{
-    int n = 0;
-    rt_hw_led_init();
-	
-    while (1)
-    {
-        //rt_kprintf("LED\t%d\tis shining\r\n",n);
-
-        rt_hw_led_on(n);
-        rt_thread_delay(RT_TICK_PER_SECOND/2);
-        rt_hw_led_off(n);
-        rt_thread_delay(RT_TICK_PER_SECOND/2);
-
-        n++;
-
-        if(n > LED_MAX-1)
-            n = 0;
-
-    }
-}
-
-int rt_application_init()
-{
-    rt_thread_t init_thread;
-
-#if (RT_THREAD_PRIORITY_MAX == 32)
-    init_thread = rt_thread_create("init",
-                                   rt_init_thread_entry, RT_NULL,
-                                   2048, 8, 20);
-#else
-    init_thread = rt_thread_create("init",
-                                   rt_init_thread_entry, RT_NULL,
-                                   2048, 80, 20);
-#endif
-
-    if (init_thread != RT_NULL)
-        rt_thread_startup(init_thread);
-
-    //------- init led1 thread
-    rt_thread_init(&thread_led1,
-                   "led_demo",
-                   rt_thread_entry_led1,
-                   RT_NULL,
-                   &thread_led1_stack[0],
-                   sizeof(thread_led1_stack),11,5);
-    rt_thread_startup(&thread_led1);
-
-    return 0;
-}
-
-/*@}*/
diff --git a/bsp/K60Fxxxx/applications/startup.c b/bsp/K60Fxxxx/applications/startup.c
deleted file mode 100644
index 49d72cff37..0000000000
--- a/bsp/K60Fxxxx/applications/startup.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-31     Bernard      first implementation
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <MK60F12.H>
-#include "board.h"
-
-/**
- * @addtogroup k60
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-#ifdef RT_USING_FINSH
-extern void finsh_system_init(void);
-extern void finsh_set_device(const char* device);
-#endif
-
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define k60_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define k60_SRAM_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define k60_SRAM_BEGIN    (&__bss_end)
-#endif
-
-/*******************************************************************************
-* Function Name  : assert_failed
-* Description    : Reports the name of the source file and the source line number
-*                  where the assert error has occurred.
-* Input          : - file: pointer to the source file name
-*                  - line: assert error line source number
-* Output         : None
-* Return         : None
-*******************************************************************************/
-void assert_failed(rt_uint8_t* file, rt_uint32_t line)
-{
-	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
-	rt_kprintf("       file  %s\r\n", file);
-	rt_kprintf("       line  %d\r\n", line);
-
-	while (1) ;
-}
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init board */
-	rt_hw_board_init();
-
-	/* show version */
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-    rt_system_heap_init((void*)k60_SRAM_BEGIN, (void*)k60_SRAM_END);
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-	/* init all device */
-	rt_device_init_all();
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device( FINSH_DEVICE_NAME );
-#endif
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main(void)
-{
-	
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
-
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/K60Fxxxx/drivers/SConscript b/bsp/K60Fxxxx/drivers/SConscript
deleted file mode 100644
index 1b05314db1..0000000000
--- a/bsp/K60Fxxxx/drivers/SConscript
+++ /dev/null
@@ -1,12 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'drivers')
-src	= Glob('*.c')
-src	+= Glob('*.s')
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/K60Fxxxx/drivers/board.c b/bsp/K60Fxxxx/drivers/board.c
deleted file mode 100644
index 5429acf309..0000000000
--- a/bsp/K60Fxxxx/drivers/board.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <MK60F12.H>
-#include "board.h"
-
-#include "drv_uart.h"
-
-
-/**
- * @addtogroup K60
- */
-
-/*@{*/
-
-/*******************************************************************************
-* Function Name  : NVIC_Configuration
-* Description    : Configures Vector Table base location.
-* Input          : None
-* Output         : None
-* Return         : None
-*******************************************************************************/
-void NVIC_Configuration(void)
-{
-
-}
-
-/*******************************************************************************
- * Function Name  : SysTick_Configuration
- * Description    : Configures the SysTick for OS tick.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void  SysTick_Configuration(void)
-{
-    SystemCoreClockUpdate();              /* Update Core Clock Frequency        */
-    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); /* Generate interrupt each 1 ms       */
-}
-
-/**
- * This is the timer interrupt service routine.
- *
- */
-void SysTick_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_tick_increase();
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-/**
- * This function will initial Tower board.
- */
-void rt_hw_board_init()
-{
-    /* NVIC Configuration */
-    NVIC_Configuration();
-
-    /* Configure the SysTick */
-    SysTick_Configuration();
-
-    rt_hw_uart_init();
-
-#ifdef RT_USING_CONSOLE
-    rt_console_set_device(CONSOLE_DEVICE);
-#endif
-}
-
-/*@}*/
diff --git a/bsp/K60Fxxxx/drivers/board.h b/bsp/K60Fxxxx/drivers/board.h
deleted file mode 100644
index 84153388ad..0000000000
--- a/bsp/K60Fxxxx/drivers/board.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-// <<< Use Configuration Wizard in Context Menu >>>
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include <MK60F12.H>
-
-
-/* board configuration */
-
-// <o> Internal SRAM memory size[Kbytes] <8-64>
-// <i>Default: 64
-#define k60_SRAM_SIZE         128
-#define k60_SRAM_END          (0x20000000 + (k60_SRAM_SIZE * 1024)/2)
-
-//#define RT_USING_UART1
-#define RT_USING_UART5
-//#define RT_USING_UART3
-
-// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
-// <i>Default: 1
-#define k60_CONSOLE_USART        5
-
-void rt_hw_board_init(void);
-
-#if k60_CONSOLE_USART == 0
-#define CONSOLE_DEVICE "no"
-#elif k60_CONSOLE_USART == 1
-#define CONSOLE_DEVICE "uart1"
-#elif k60_CONSOLE_USART == 2
-#define CONSOLE_DEVICE "uart2"
-#elif k60_CONSOLE_USART == 3
-#define CONSOLE_DEVICE "uart3"
-#elif k60_CONSOLE_USART == 4
-#define CONSOLE_DEVICE "uart4"
-#elif k60_CONSOLE_USART == 5
-#define CONSOLE_DEVICE "uart5"
-#endif
-
-#define FINSH_DEVICE_NAME   CONSOLE_DEVICE
-
-
-#endif
-
-// <<< Use Configuration Wizard in Context Menu >>>
diff --git a/bsp/K60Fxxxx/drivers/drv_uart.c b/bsp/K60Fxxxx/drivers/drv_uart.c
deleted file mode 100644
index 5452ccb8c5..0000000000
--- a/bsp/K60Fxxxx/drivers/drv_uart.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-
-#include "drv_uart.h"
-
-static struct rt_serial_device _k60_serial;  //abstracted serial for RTT
-static struct serial_ringbuffer _k60_int_rx; //UART send buffer area
-
-struct k60_serial_device
-{
-    /* UART base address */
-    UART_Type *baseAddress;
-
-    /* UART IRQ Number */
-    int irq_num;
-
-    /* device config */
-    struct serial_configure config;
-};
-
-//hardware abstract device
-static struct k60_serial_device _k60_node =
-{
-    (UART_Type *)UART5,
-    k60_uasrt_irq_num,
-};
-
-static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2,reg_BRFA=0;
-    unsigned int cal_SBR = 0;
-    UART_Type *uart_reg;
-
-    /* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
-     * calculate baud_rate
-     */
-    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
-
-    /* calc SBR */
-    cal_SBR = 60000000 / (16 * cfg->baud_rate);
-
-    /* calc baud_rate */
-    reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
-    reg_BDL = cal_SBR & 0x00FF;
-
-    /* fractional divider */
-    reg_BRFA = ((60000*32000)/(cfg->baud_rate * 16)) - (cal_SBR * 32);
-
-    reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
-
-    /*
-     * set bit order
-     */
-    if (cfg->bit_order == BIT_ORDER_LSB)
-        reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
-    else if (cfg->bit_order == BIT_ORDER_MSB)
-        reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
-
-    /*
-     * set data_bits
-     */
-    if (cfg->data_bits == DATA_BITS_8)
-        reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
-    else if (cfg->data_bits == DATA_BITS_9)
-        reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
-
-    /*
-     * set parity
-     */
-    if (cfg->parity == PARITY_NONE)
-    {
-        reg_C1 &= ~(UART_C1_PE_MASK);
-    }
-    else
-    {
-        /* first ,set parity enable bit */
-        reg_C1 |= (UART_C1_PE_MASK);
-        
-        /* second ,determine parity odd or even*/
-        if (cfg->parity == PARITY_ODD)
-            reg_C1 |= UART_C1_PT_MASK;
-        if (cfg->parity == PARITY_EVEN)
-            reg_C1 &= ~(UART_C1_PT_MASK);
-    }
-
-    /*
-     * set stop bit
-     * not supported on Tower? need ur help!
-     */
-
-    /*
-     * set NZR mode
-     * not tested
-     */
-    if(cfg->invert != NRZ_NORMAL)
-    {
-        /* not in normal mode ,set inverted polarity */
-        reg_C3 |= UART_C3_TXINV_MASK;
-    }
-
-    switch( (int)uart_reg)
-    {
-    /* Tower board use UART5 for communication
-     * if you're using other board
-     * set clock and pin map for UARTx
-     */
-    case UART5_BASE:
-
-        //set UART5 clock
-        SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;//Enable UART gate clocking 
-        SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;//Enable PORTE gate clocking
-
-        //set UART5 pin
-        PORTE->PCR[ 8] = (3UL <<  8);      //Pin mux configured as ALT3
-        PORTE->PCR[ 9] = (3UL <<  8);      //Pin mux configured as ALT3
-        break;
-    default:
-        break;
-    }
-
-    uart_reg->BDH = reg_BDH;
-    uart_reg->BDL = reg_BDL;
-    uart_reg->C1 = reg_C1;
-    uart_reg->C4 = reg_C4;
-    uart_reg->S2 = reg_S2;
-
-    uart_reg->S2  =  0;
-    uart_reg->C3  =  0;
-
-    uart_reg->RWFIFO = UART_RWFIFO_RXWATER(1);
-    uart_reg->TWFIFO = UART_TWFIFO_TXWATER(0);
-
-    uart_reg->C2  =  UART_C2_RE_MASK |    //Receiver enable
-                     UART_C2_TE_MASK;     //Transmitter enable
-
-    return RT_EOK;
-}
-
-static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    UART_Type *uart_reg;
-    int uart_irq_num = 0;
-
-    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
-    uart_irq_num = ((struct k60_serial_device *)serial->parent.user_data)->irq_num;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        uart_reg->C2 &= ~UART_C2_RIE_MASK;
-        //disable NVIC
-        NVIC->ICER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
-        break;
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        uart_reg->C2 |= UART_C2_RIE_MASK;
-        //enable NVIC,we are sure uart's NVIC vector is in NVICICPR1
-        NVIC->ICPR[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
-        NVIC->ISER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
-        break;
-    case RT_DEVICE_CTRL_SUSPEND:
-        /* suspend device */
-        uart_reg->C2  &=  ~(UART_C2_RE_MASK |    //Receiver enable
-                            UART_C2_TE_MASK);     //Transmitter enable
-        break;
-    case RT_DEVICE_CTRL_RESUME:
-        /* resume device */
-        uart_reg->C2  =  UART_C2_RE_MASK |    //Receiver enable
-                         UART_C2_TE_MASK;     //Transmitter enable
-        break;
-    }
-
-    return RT_EOK;
-}
-
-static int _putc(struct rt_serial_device *serial, char c)
-{
-    UART_Type *uart_reg;
-    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
-
-    while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
-    uart_reg->D = (c & 0xFF);
-    return 1;
-}
-
-static int _getc(struct rt_serial_device *serial)
-{
-    UART_Type *uart_reg;
-    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
-
-    if (uart_reg->S1 & UART_S1_RDRF_MASK)
-        return (uart_reg->D);
-    else
-        return -1;
-}
-
-static const struct rt_uart_ops _k60_ops =
-{
-    _configure,
-    _control,
-    _putc,
-    _getc,
-};
-
-
-void UART5_RX_TX_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    rt_hw_serial_isr((struct rt_serial_device*)&_k60_serial);
-    rt_interrupt_leave();
-}
-
-
-void rt_hw_uart_init(void)
-{
-    struct serial_configure config;
-
-    /* fake configuration */
-    config.baud_rate = BAUD_RATE_115200;
-    config.bit_order = BIT_ORDER_LSB;
-    config.data_bits = DATA_BITS_8;
-    config.parity    = PARITY_NONE;
-    config.stop_bits = STOP_BITS_1;
-    config.invert    = NRZ_NORMAL;
-
-    _k60_serial.ops    = &_k60_ops;
-    _k60_serial.int_rx = &_k60_int_rx;
-    _k60_serial.config = config;
-
-    rt_hw_serial_register(&_k60_serial, "uart5",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          (void*)&_k60_node);
-}
-
-void rt_hw_console_output(const char *str)
-{
-    while(*str != '\0')
-    {
-        if (*str == '\n')
-            _putc(&_k60_serial,'\r');
-        _putc(&_k60_serial,*str);
-        str++;
-    }
-}
diff --git a/bsp/K60Fxxxx/drivers/drv_uart.h b/bsp/K60Fxxxx/drivers/drv_uart.h
deleted file mode 100644
index 57cc62952e..0000000000
--- a/bsp/K60Fxxxx/drivers/drv_uart.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-#ifndef DRV_UART_H
-#define DRV_UART_H
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include <MK60F12.H>
-
-#include <drivers/serial.h>
-
-
-#define k60_uasrt_irq_num   (55)
-
-void rt_hw_uart_init(void);
-
-//for kernel debug when console not registered
-void rt_hw_console_output(const char *str);
-
-#endif /* end of include guard: DRV_UART_H */
diff --git a/bsp/K60Fxxxx/drivers/led.c b/bsp/K60Fxxxx/drivers/led.c
deleted file mode 100644
index 241a87fee0..0000000000
--- a/bsp/K60Fxxxx/drivers/led.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-#include <MK60F12.H>
-#include "led.h"
-
-const rt_uint32_t led_mask[] = { 1 << 11, 1 << 28, 1 << 29, 1 << 10 };
-
-void rt_hw_led_init(void)
-{
-    SIM->SCGC5    |= (1UL <<  9);         //Enable Port A Clock
-    PORTA->PCR[10] = (1UL <<  8);         //PTA10 is GPIO pin  
-    PORTA->PCR[11] = (1UL <<  8);         //PTA11 is GPIO pin  
-    PORTA->PCR[28] = (1UL <<  8);         //PTA28 is GPIO pin  
-    PORTA->PCR[29] = (1UL <<  8);         //PTA29 is GPIO pin  
-
-    /* Switch LEDs off and enable output*/
-    PTA->PDOR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
-    PTA->PDDR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
-}
-
-void rt_hw_led_uninit(void)
-{
-    PORTA->PCR[10] = 0;                   //PTA10 is at reset state
-    PORTA->PCR[11] = 0;                   //PTA11 is at reset state
-    PORTA->PCR[28] = 0;                   //PTA28 is at reset state
-    PORTA->PCR[29] = 0;                   //PTA29 is at reset state
-}
-
-void rt_hw_led_on(rt_uint32_t n)
-{
-    if (n < LED_MAX)
-    {
-        PTA->PCOR = led_mask[n];
-    }
-}
-
-
-void rt_hw_led_off(rt_uint32_t n)
-{
-    if (n < LED_MAX) {
-        PTA->PSOR = led_mask[n];
-    }
-}
diff --git a/bsp/K60Fxxxx/drivers/led.h b/bsp/K60Fxxxx/drivers/led.h
deleted file mode 100644
index 31d1b4438b..0000000000
--- a/bsp/K60Fxxxx/drivers/led.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-11     reynolds     port to TWR-K60F120M
- */
-
-#ifndef __LED_H__
-#define __LED_H__
-
-#include <rtthread.h>
-
-#define LED_MAX  4
-
-void rt_hw_led_init(void);
-void rt_hw_led_uninit(void);
-void rt_hw_led_on(rt_uint32_t n);
-void rt_hw_led_off(rt_uint32_t n);
-
-#endif /* end  of __LED_H__ */
diff --git a/bsp/K60Fxxxx/drivers/startup_MK60F12.s b/bsp/K60Fxxxx/drivers/startup_MK60F12.s
deleted file mode 100644
index ec728276f2..0000000000
--- a/bsp/K60Fxxxx/drivers/startup_MK60F12.s
+++ /dev/null
@@ -1,774 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_MK60F12.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
-; *           MK60F12
-; * @version: 1.1
-; * @date:    2011-11-3
-; *
-; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-;*
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp  ; Top of Stack
-                DCD     Reset_Handler  ; Reset Handler
-                DCD     NMI_Handler  ; NMI Handler
-                DCD     HardFault_Handler  ; Hard Fault Handler
-                DCD     MemManage_Handler  ; MPU Fault Handler
-                DCD     BusFault_Handler  ; Bus Fault Handler
-                DCD     UsageFault_Handler  ; Usage Fault Handler
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     SVC_Handler  ; SVCall Handler
-                DCD     DebugMon_Handler  ; Debug Monitor Handler
-                DCD     0  ; Reserved
-                DCD     PendSV_Handler  ; PendSV Handler
-                DCD     SysTick_Handler  ; SysTick Handler
-
-                ; External Interrupts
-                DCD     DMA0_DMA16_IRQHandler  ; DMA channel 0/16 transfer complete interrupt
-                DCD     DMA1_DMA17_IRQHandler  ; DMA channel 1/17 transfer complete interrupt
-                DCD     DMA2_DMA18_IRQHandler  ; DMA channel 2/18 transfer complete interrupt
-                DCD     DMA3_DMA19_IRQHandler  ; DMA channel 3/19 transfer complete interrupt
-                DCD     DMA4_DMA20_IRQHandler  ; DMA channel 4/20 transfer complete interrupt
-                DCD     DMA5_DMA21_IRQHandler  ; DMA channel 5/21 transfer complete interrupt
-                DCD     DMA6_DMA22_IRQHandler  ; DMA channel 6/22 transfer complete interrupt
-                DCD     DMA7_DMA23_IRQHandler  ; DMA channel 7/23 transfer complete interrupt
-                DCD     DMA8_DMA24_IRQHandler  ; DMA channel 8/24 transfer complete interrupt
-                DCD     DMA9_DMA25_IRQHandler  ; DMA channel 9/25 transfer complete interrupt
-                DCD     DMA10_DMA26_IRQHandler  ; DMA channel 10/26 transfer complete interrupt
-                DCD     DMA11_DMA27_IRQHandler  ; DMA channel 11/27 transfer complete interrupt
-                DCD     DMA12_DMA28_IRQHandler  ; DMA channel 12/28 transfer complete interrupt
-                DCD     DMA13_DMA29_IRQHandler  ; DMA channel 13/29 transfer complete interrupt
-                DCD     DMA14_DMA30_IRQHandler  ; DMA channel 14/30 transfer complete interrupt
-                DCD     DMA15_DMA31_IRQHandler  ; DMA channel 15/31 transfer complete interrupt
-                DCD     DMA_Error_IRQHandler  ; DMA error interrupt
-                DCD     MCM_IRQHandler  ; Normal interrupt
-                DCD     FTFE_IRQHandler  ; FTFE interrupt
-                DCD     Read_Collision_IRQHandler  ; Read collision interrupt
-                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
-                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
-                DCD     Watchdog_IRQHandler  ; WDOG interrupt
-                DCD     RNG_IRQHandler  ; RNGB interrupt
-                DCD     I2C0_IRQHandler  ; I2C0 interrupt
-                DCD     I2C1_IRQHandler  ; I2C1 interrupt
-                DCD     SPI0_IRQHandler  ; SPI0 interrupt
-                DCD     SPI1_IRQHandler  ; SPI1 interrupt
-                DCD     SPI2_IRQHandler  ; SPI2 interrupt
-                DCD     CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
-                DCD     CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
-                DCD     CAN0_Error_IRQHandler  ; CAN0 error interrupt
-                DCD     CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
-                DCD     CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
-                DCD     CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
-                DCD     I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
-                DCD     I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
-                DCD     CAN1_ORed_Message_buffer_IRQHandler  ; CAN1 OR'd message buffers interrupt
-                DCD     CAN1_Bus_Off_IRQHandler  ; CAN1 bus off interrupt
-                DCD     CAN1_Error_IRQHandler  ; CAN1 error interrupt
-                DCD     CAN1_Tx_Warning_IRQHandler  ; CAN1 Tx warning interrupt
-                DCD     CAN1_Rx_Warning_IRQHandler  ; CAN1 Rx warning interrupt
-                DCD     CAN1_Wake_Up_IRQHandler  ; CAN1 wake up interrupt
-                DCD     Reserved59_IRQHandler  ; Reserved interrupt 59
-                DCD     UART0_LON_IRQHandler  ; UART0 LON interrupt
-                DCD     UART0_RX_TX_IRQHandler  ; UART0 receive/transmit interrupt
-                DCD     UART0_ERR_IRQHandler  ; UART0 error interrupt
-                DCD     UART1_RX_TX_IRQHandler  ; UART1 receive/transmit interrupt
-                DCD     UART1_ERR_IRQHandler  ; UART1 error interrupt
-                DCD     UART2_RX_TX_IRQHandler  ; UART2 receive/transmit interrupt
-                DCD     UART2_ERR_IRQHandler  ; UART2 error interrupt
-                DCD     UART3_RX_TX_IRQHandler  ; UART3 receive/transmit interrupt
-                DCD     UART3_ERR_IRQHandler  ; UART3 error interrupt
-                DCD     UART4_RX_TX_IRQHandler  ; UART4 receive/transmit interrupt
-                DCD     UART4_ERR_IRQHandler  ; UART4 error interrupt
-                DCD     UART5_RX_TX_IRQHandler  ; UART5 receive/transmit interrupt
-                DCD     UART5_ERR_IRQHandler  ; UART5 error interrupt
-                DCD     ADC0_IRQHandler  ; ADC0 interrupt
-                DCD     ADC1_IRQHandler  ; ADC1 interrupt
-                DCD     CMP0_IRQHandler  ; CMP0 interrupt
-                DCD     CMP1_IRQHandler  ; CMP1 interrupt
-                DCD     CMP2_IRQHandler  ; CMP2 interrupt
-                DCD     FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
-                DCD     FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
-                DCD     FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
-                DCD     CMT_IRQHandler  ; CMT interrupt
-                DCD     RTC_IRQHandler  ; RTC interrupt
-                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
-                DCD     PIT0_IRQHandler  ; PIT timer channel 0 interrupt
-                DCD     PIT1_IRQHandler  ; PIT timer channel 1 interrupt
-                DCD     PIT2_IRQHandler  ; PIT timer channel 2 interrupt
-                DCD     PIT3_IRQHandler  ; PIT timer channel 3 interrupt
-                DCD     PDB0_IRQHandler  ; PDB0 interrupt
-                DCD     USB0_IRQHandler  ; USB0 interrupt
-                DCD     USBDCD_IRQHandler  ; USBDCD interrupt
-                DCD     ENET_1588_Timer_IRQHandler  ; Ethernet MAC IEEE 1588 timer interrupt
-                DCD     ENET_Transmit_IRQHandler  ; Ethernet MAC transmit interrupt
-                DCD     ENET_Receive_IRQHandler  ; Ethernet MAC receive interrupt
-                DCD     ENET_Error_IRQHandler  ; Ethernet MAC error and miscelaneous interrupt
-                DCD     Reserved95_IRQHandler  ; Reserved interrupt 95
-                DCD     SDHC_IRQHandler  ; SDHC interrupt
-                DCD     DAC0_IRQHandler  ; DAC0 interrupt
-                DCD     DAC1_IRQHandler  ; DAC1 interrupt
-                DCD     TSI0_IRQHandler  ; TSI0 interrupt
-                DCD     MCG_IRQHandler  ; MCG interrupt
-                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
-                DCD     Reserved102_IRQHandler  ; Reserved interrupt 102
-                DCD     PORTA_IRQHandler  ; Port A interrupt
-                DCD     PORTB_IRQHandler  ; Port B interrupt
-                DCD     PORTC_IRQHandler  ; Port C interrupt
-                DCD     PORTD_IRQHandler  ; Port D interrupt
-                DCD     PORTE_IRQHandler  ; Port E interrupt
-                DCD     PORTF_IRQHandler  ; Port F interrupt
-                DCD     Reserved109_IRQHandler  ; Reserved interrupt 109
-                DCD     SWI_IRQHandler  ; Software interrupt
-                DCD     NFC_IRQHandler  ; NAND flash controller interrupt
-                DCD     USBHS_IRQHandler  ; USB high speed OTG interrupt
-                DCD     Reserved113_IRQHandler  ; Reserved interrupt 113
-                DCD     CMP3_IRQHandler  ; CMP3 interrupt
-                DCD     Reserved115_IRQHandler  ; Reserved interrupt 115
-                DCD     Reserved116_IRQHandler  ; Reserved interrupt 116
-                DCD     FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
-                DCD     ADC2_IRQHandler  ; ADC2 interrupt
-                DCD     ADC3_IRQHandler  ; ADC3 interrupt
-                DCD     I2S1_Tx_IRQHandler  ; I2S1 transmit interrupt
-                DCD     I2S1_Rx_IRQHandler  ; I2S1 receive interrupt
-                DCD     DefaultISR  ; 122
-                DCD     DefaultISR  ; 123
-                DCD     DefaultISR  ; 124
-                DCD     DefaultISR  ; 125
-                DCD     DefaultISR  ; 126
-                DCD     DefaultISR  ; 127
-                DCD     DefaultISR  ; 128
-                DCD     DefaultISR  ; 129
-                DCD     DefaultISR  ; 130
-                DCD     DefaultISR  ; 131
-                DCD     DefaultISR  ; 132
-                DCD     DefaultISR  ; 133
-                DCD     DefaultISR  ; 134
-                DCD     DefaultISR  ; 135
-                DCD     DefaultISR  ; 136
-                DCD     DefaultISR  ; 137
-                DCD     DefaultISR  ; 138
-                DCD     DefaultISR  ; 139
-                DCD     DefaultISR  ; 140
-                DCD     DefaultISR  ; 141
-                DCD     DefaultISR  ; 142
-                DCD     DefaultISR  ; 143
-                DCD     DefaultISR  ; 144
-                DCD     DefaultISR  ; 145
-                DCD     DefaultISR  ; 146
-                DCD     DefaultISR  ; 147
-                DCD     DefaultISR  ; 148
-                DCD     DefaultISR  ; 149
-                DCD     DefaultISR  ; 150
-                DCD     DefaultISR  ; 151
-                DCD     DefaultISR  ; 152
-                DCD     DefaultISR  ; 153
-                DCD     DefaultISR  ; 154
-                DCD     DefaultISR  ; 155
-                DCD     DefaultISR  ; 156
-                DCD     DefaultISR  ; 157
-                DCD     DefaultISR  ; 158
-                DCD     DefaultISR  ; 159
-                DCD     DefaultISR  ; 160
-                DCD     DefaultISR  ; 161
-                DCD     DefaultISR  ; 162
-                DCD     DefaultISR  ; 163
-                DCD     DefaultISR  ; 164
-                DCD     DefaultISR  ; 165
-                DCD     DefaultISR  ; 166
-                DCD     DefaultISR  ; 167
-                DCD     DefaultISR  ; 168
-                DCD     DefaultISR  ; 169
-                DCD     DefaultISR  ; 170
-                DCD     DefaultISR  ; 171
-                DCD     DefaultISR  ; 172
-                DCD     DefaultISR  ; 173
-                DCD     DefaultISR  ; 174
-                DCD     DefaultISR  ; 175
-                DCD     DefaultISR  ; 176
-                DCD     DefaultISR  ; 177
-                DCD     DefaultISR  ; 178
-                DCD     DefaultISR  ; 179
-                DCD     DefaultISR  ; 180
-                DCD     DefaultISR  ; 181
-                DCD     DefaultISR  ; 182
-                DCD     DefaultISR  ; 183
-                DCD     DefaultISR  ; 184
-                DCD     DefaultISR  ; 185
-                DCD     DefaultISR  ; 186
-                DCD     DefaultISR  ; 187
-                DCD     DefaultISR  ; 188
-                DCD     DefaultISR  ; 189
-                DCD     DefaultISR  ; 190
-                DCD     DefaultISR  ; 191
-                DCD     DefaultISR  ; 192
-                DCD     DefaultISR  ; 193
-                DCD     DefaultISR  ; 194
-                DCD     DefaultISR  ; 195
-                DCD     DefaultISR  ; 196
-                DCD     DefaultISR  ; 197
-                DCD     DefaultISR  ; 198
-                DCD     DefaultISR  ; 199
-                DCD     DefaultISR  ; 200
-                DCD     DefaultISR  ; 201
-                DCD     DefaultISR  ; 202
-                DCD     DefaultISR  ; 203
-                DCD     DefaultISR  ; 204
-                DCD     DefaultISR  ; 205
-                DCD     DefaultISR  ; 206
-                DCD     DefaultISR  ; 207
-                DCD     DefaultISR  ; 208
-                DCD     DefaultISR  ; 209
-                DCD     DefaultISR  ; 210
-                DCD     DefaultISR  ; 211
-                DCD     DefaultISR  ; 212
-                DCD     DefaultISR  ; 213
-                DCD     DefaultISR  ; 214
-                DCD     DefaultISR  ; 215
-                DCD     DefaultISR  ; 216
-                DCD     DefaultISR  ; 217
-                DCD     DefaultISR  ; 218
-                DCD     DefaultISR  ; 219
-                DCD     DefaultISR  ; 220
-                DCD     DefaultISR  ; 221
-                DCD     DefaultISR  ; 222
-                DCD     DefaultISR  ; 223
-                DCD     DefaultISR  ; 224
-                DCD     DefaultISR  ; 225
-                DCD     DefaultISR  ; 226
-                DCD     DefaultISR  ; 227
-                DCD     DefaultISR  ; 228
-                DCD     DefaultISR  ; 229
-                DCD     DefaultISR  ; 230
-                DCD     DefaultISR  ; 231
-                DCD     DefaultISR  ; 232
-                DCD     DefaultISR  ; 233
-                DCD     DefaultISR  ; 234
-                DCD     DefaultISR  ; 235
-                DCD     DefaultISR  ; 236
-                DCD     DefaultISR  ; 237
-                DCD     DefaultISR  ; 238
-                DCD     DefaultISR  ; 239
-                DCD     DefaultISR  ; 240
-                DCD     DefaultISR  ; 241
-                DCD     DefaultISR  ; 242
-                DCD     DefaultISR  ; 243
-                DCD     DefaultISR  ; 244
-                DCD     DefaultISR  ; 245
-                DCD     DefaultISR  ; 246
-                DCD     DefaultISR  ; 247
-                DCD     DefaultISR  ; 248
-                DCD     DefaultISR  ; 249
-                DCD     DefaultISR  ; 250
-                DCD     DefaultISR  ; 251
-                DCD     DefaultISR  ; 252
-                DCD     DefaultISR  ; 253
-                DCD     DefaultISR  ; 254
-                DCD     DefaultISR  ; 255
-__Vectors_End
-
-__Vectors_Size 	EQU     __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
-;   <h> Backdoor Comparison Key
-;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
-;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
-;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
-;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
-;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
-;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
-;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
-;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
-BackDoorK0      EQU     0xFF
-BackDoorK1      EQU     0xFF
-BackDoorK2      EQU     0xFF
-BackDoorK3      EQU     0xFF
-BackDoorK4      EQU     0xFF
-BackDoorK5      EQU     0xFF
-BackDoorK6      EQU     0xFF
-BackDoorK7      EQU     0xFF
-;   </h>
-;   <h> Program flash protection bytes (FPROT)
-;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-;     <i> Each bit protects a 1/32 region of the program flash memory.
-;     <h> FPROT0
-;       <i> Program flash protection bytes
-;       <i> 1/32 - 8/32 region
-;       <o.0>   FPROT0.0
-;       <o.1>   FPROT0.1
-;       <o.2>   FPROT0.2
-;       <o.3>   FPROT0.3
-;       <o.4>   FPROT0.4
-;       <o.5>   FPROT0.5
-;       <o.6>   FPROT0.6
-;       <o.7>   FPROT0.7
-nFPROT0         EQU     0x00
-FPROT0          EQU     nFPROT0:EOR:0xFF
-;     </h>
-;     <h> FPROT1
-;       <i> Program Flash Region Protect Register 1
-;       <i> 9/32 - 16/32 region
-;       <o.0>   FPROT1.0
-;       <o.1>   FPROT1.1
-;       <o.2>   FPROT1.2
-;       <o.3>   FPROT1.3
-;       <o.4>   FPROT1.4
-;       <o.5>   FPROT1.5
-;       <o.6>   FPROT1.6
-;       <o.7>   FPROT1.7
-nFPROT1         EQU     0x00
-FPROT1          EQU     nFPROT1:EOR:0xFF
-;     </h>
-;     <h> FPROT2
-;       <i> Program Flash Region Protect Register 2
-;       <i> 17/32 - 24/32 region
-;       <o.0>   FPROT2.0
-;       <o.1>   FPROT2.1
-;       <o.2>   FPROT2.2
-;       <o.3>   FPROT2.3
-;       <o.4>   FPROT2.4
-;       <o.5>   FPROT2.5
-;       <o.6>   FPROT2.6
-;       <o.7>   FPROT2.7
-nFPROT2         EQU     0x00
-FPROT2          EQU     nFPROT2:EOR:0xFF
-;     </h>
-;     <h> FPROT3
-;       <i> Program Flash Region Protect Register 3
-;       <i> 25/32 - 32/32 region
-;       <o.0>   FPROT3.0
-;       <o.1>   FPROT3.1
-;       <o.2>   FPROT3.2
-;       <o.3>   FPROT3.3
-;       <o.4>   FPROT3.4
-;       <o.5>   FPROT3.5
-;       <o.6>   FPROT3.6
-;       <o.7>   FPROT3.7
-nFPROT3         EQU     0x00
-FPROT3          EQU     nFPROT3:EOR:0xFF
-;     </h>
-;   </h>
-;   <h> Data flash protection byte (FDPROT)
-;     <i> Each bit protects a 1/8 region of the data flash memory.
-;     <i> (Program flash only devices: Reserved)
-;     <o.0>   FDPROT.0
-;     <o.1>   FDPROT.1
-;     <o.2>   FDPROT.2
-;     <o.3>   FDPROT.3
-;     <o.4>   FDPROT.4
-;     <o.5>   FDPROT.5
-;     <o.6>   FDPROT.6
-;     <o.7>   FDPROT.7
-nFDPROT         EQU     0x00
-FDPROT          EQU     nFDPROT:EOR:0xFF
-;   </h>
-;   <h> EEPROM protection byte (FEPROT)
-;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
-;     <i> (Program flash only devices: Reserved)
-;     <o.0>   FEPROT.0
-;     <o.1>   FEPROT.1
-;     <o.2>   FEPROT.2
-;     <o.3>   FEPROT.3
-;     <o.4>   FEPROT.4
-;     <o.5>   FEPROT.5
-;     <o.6>   FEPROT.6
-;     <o.7>   FEPROT.7
-nFEPROT         EQU     0x00
-FEPROT          EQU     nFEPROT:EOR:0xFF
-;   </h>
-;   <h> Flash nonvolatile option byte (FOPT)
-;     <i> Allows the user to customize the operation of the MCU at boot time.
-;     <o.0>  LPBOOT
-;       <0=> Low-power boot
-;       <1=> normal boot
-;     <o.1>  EZPORT_DIS
-;       <0=> EzPort operation is enabled
-;       <1=> EzPort operation is disabled
-FOPT            EQU     0xFF
-;   </h>
-;   <h> Flash security byte (FSEC)
-;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-;     <o.0..1> SEC
-;       <2=> MCU security status is unsecure
-;       <3=> MCU security status is secure
-;         <i> Flash Security
-;         <i> This bits define the security state of the MCU.
-;     <o.2..3> FSLACC
-;       <2=> Freescale factory access denied
-;       <3=> Freescale factory access granted
-;         <i> Freescale Failure Analysis Access Code
-;         <i> This bits define the security state of the MCU.
-;     <o.4..5> MEEN
-;       <2=> Mass erase is disabled
-;       <3=> Mass erase is enabled
-;         <i> Mass Erase Enable Bits
-;         <i> Enables and disables mass erase capability of the FTFL module
-;     <o.6..7> KEYEN
-;       <2=> Backdoor key access enabled
-;       <3=> Backdoor key access disabled
-;         <i> Backdoor key Security Enable
-;         <i> These bits enable and disable backdoor key access to the FTFL module.
-FSEC            EQU     0xFE
-;   </h>
-; </h>
-                IF      :LNOT::DEF:RAM_TARGET
-                AREA    |.ARM.__at_0x400|, CODE, READONLY
-                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
-                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
-                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
-                DCB     FSEC,       FOPT,       FEPROT,     FDPROT
-                ENDIF
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT  DMA0_DMA16_IRQHandler     [WEAK]
-                EXPORT  DMA1_DMA17_IRQHandler     [WEAK]
-                EXPORT  DMA2_DMA18_IRQHandler     [WEAK]
-                EXPORT  DMA3_DMA19_IRQHandler     [WEAK]
-                EXPORT  DMA4_DMA20_IRQHandler     [WEAK]
-                EXPORT  DMA5_DMA21_IRQHandler     [WEAK]
-                EXPORT  DMA6_DMA22_IRQHandler     [WEAK]
-                EXPORT  DMA7_DMA23_IRQHandler     [WEAK]
-                EXPORT  DMA8_DMA24_IRQHandler     [WEAK]
-                EXPORT  DMA9_DMA25_IRQHandler     [WEAK]
-                EXPORT  DMA10_DMA26_IRQHandler     [WEAK]
-                EXPORT  DMA11_DMA27_IRQHandler     [WEAK]
-                EXPORT  DMA12_DMA28_IRQHandler     [WEAK]
-                EXPORT  DMA13_DMA29_IRQHandler     [WEAK]
-                EXPORT  DMA14_DMA30_IRQHandler     [WEAK]
-                EXPORT  DMA15_DMA31_IRQHandler     [WEAK]
-                EXPORT  DMA_Error_IRQHandler     [WEAK]
-                EXPORT  MCM_IRQHandler     [WEAK]
-                EXPORT  FTFE_IRQHandler     [WEAK]
-                EXPORT  Read_Collision_IRQHandler     [WEAK]
-                EXPORT  LVD_LVW_IRQHandler     [WEAK]
-                EXPORT  LLW_IRQHandler     [WEAK]
-                EXPORT  Watchdog_IRQHandler     [WEAK]
-                EXPORT  RNG_IRQHandler     [WEAK]
-                EXPORT  I2C0_IRQHandler     [WEAK]
-                EXPORT  I2C1_IRQHandler     [WEAK]
-                EXPORT  SPI0_IRQHandler     [WEAK]
-                EXPORT  SPI1_IRQHandler     [WEAK]
-                EXPORT  SPI2_IRQHandler     [WEAK]
-                EXPORT  CAN0_ORed_Message_buffer_IRQHandler     [WEAK]
-                EXPORT  CAN0_Bus_Off_IRQHandler     [WEAK]
-                EXPORT  CAN0_Error_IRQHandler     [WEAK]
-                EXPORT  CAN0_Tx_Warning_IRQHandler     [WEAK]
-                EXPORT  CAN0_Rx_Warning_IRQHandler     [WEAK]
-                EXPORT  CAN0_Wake_Up_IRQHandler     [WEAK]
-                EXPORT  I2S0_Tx_IRQHandler     [WEAK]
-                EXPORT  I2S0_Rx_IRQHandler     [WEAK]
-                EXPORT  CAN1_ORed_Message_buffer_IRQHandler     [WEAK]
-                EXPORT  CAN1_Bus_Off_IRQHandler     [WEAK]
-                EXPORT  CAN1_Error_IRQHandler     [WEAK]
-                EXPORT  CAN1_Tx_Warning_IRQHandler     [WEAK]
-                EXPORT  CAN1_Rx_Warning_IRQHandler     [WEAK]
-                EXPORT  CAN1_Wake_Up_IRQHandler     [WEAK]
-                EXPORT  Reserved59_IRQHandler     [WEAK]
-                EXPORT  UART0_LON_IRQHandler     [WEAK]
-                EXPORT  UART0_RX_TX_IRQHandler     [WEAK]
-                EXPORT  UART0_ERR_IRQHandler     [WEAK]
-                EXPORT  UART1_RX_TX_IRQHandler     [WEAK]
-                EXPORT  UART1_ERR_IRQHandler     [WEAK]
-                EXPORT  UART2_RX_TX_IRQHandler     [WEAK]
-                EXPORT  UART2_ERR_IRQHandler     [WEAK]
-                EXPORT  UART3_RX_TX_IRQHandler     [WEAK]
-                EXPORT  UART3_ERR_IRQHandler     [WEAK]
-                EXPORT  UART4_RX_TX_IRQHandler     [WEAK]
-                EXPORT  UART4_ERR_IRQHandler     [WEAK]
-                EXPORT  UART5_RX_TX_IRQHandler     [WEAK]
-                EXPORT  UART5_ERR_IRQHandler     [WEAK]
-                EXPORT  ADC0_IRQHandler     [WEAK]
-                EXPORT  ADC1_IRQHandler     [WEAK]
-                EXPORT  CMP0_IRQHandler     [WEAK]
-                EXPORT  CMP1_IRQHandler     [WEAK]
-                EXPORT  CMP2_IRQHandler     [WEAK]
-                EXPORT  FTM0_IRQHandler     [WEAK]
-                EXPORT  FTM1_IRQHandler     [WEAK]
-                EXPORT  FTM2_IRQHandler     [WEAK]
-                EXPORT  CMT_IRQHandler     [WEAK]
-                EXPORT  RTC_IRQHandler     [WEAK]
-                EXPORT  RTC_Seconds_IRQHandler     [WEAK]
-                EXPORT  PIT0_IRQHandler     [WEAK]
-                EXPORT  PIT1_IRQHandler     [WEAK]
-                EXPORT  PIT2_IRQHandler     [WEAK]
-                EXPORT  PIT3_IRQHandler     [WEAK]
-                EXPORT  PDB0_IRQHandler     [WEAK]
-                EXPORT  USB0_IRQHandler     [WEAK]
-                EXPORT  USBDCD_IRQHandler     [WEAK]
-                EXPORT  ENET_1588_Timer_IRQHandler     [WEAK]
-                EXPORT  ENET_Transmit_IRQHandler     [WEAK]
-                EXPORT  ENET_Receive_IRQHandler     [WEAK]
-                EXPORT  ENET_Error_IRQHandler     [WEAK]
-                EXPORT  Reserved95_IRQHandler     [WEAK]
-                EXPORT  SDHC_IRQHandler     [WEAK]
-                EXPORT  DAC0_IRQHandler     [WEAK]
-                EXPORT  DAC1_IRQHandler     [WEAK]
-                EXPORT  TSI0_IRQHandler     [WEAK]
-                EXPORT  MCG_IRQHandler     [WEAK]
-                EXPORT  LPTimer_IRQHandler     [WEAK]
-                EXPORT  Reserved102_IRQHandler     [WEAK]
-                EXPORT  PORTA_IRQHandler     [WEAK]
-                EXPORT  PORTB_IRQHandler     [WEAK]
-                EXPORT  PORTC_IRQHandler     [WEAK]
-                EXPORT  PORTD_IRQHandler     [WEAK]
-                EXPORT  PORTE_IRQHandler     [WEAK]
-                EXPORT  PORTF_IRQHandler     [WEAK]
-                EXPORT  Reserved109_IRQHandler     [WEAK]
-                EXPORT  SWI_IRQHandler     [WEAK]
-                EXPORT  NFC_IRQHandler     [WEAK]
-                EXPORT  USBHS_IRQHandler     [WEAK]
-                EXPORT  Reserved113_IRQHandler     [WEAK]
-                EXPORT  CMP3_IRQHandler     [WEAK]
-                EXPORT  Reserved115_IRQHandler     [WEAK]
-                EXPORT  Reserved116_IRQHandler     [WEAK]
-                EXPORT  FTM3_IRQHandler     [WEAK]
-                EXPORT  ADC2_IRQHandler     [WEAK]
-                EXPORT  ADC3_IRQHandler     [WEAK]
-                EXPORT  I2S1_Tx_IRQHandler     [WEAK]
-                EXPORT  I2S1_Rx_IRQHandler     [WEAK]
-                EXPORT  DefaultISR                      [WEAK]
-
-DMA0_DMA16_IRQHandler
-DMA1_DMA17_IRQHandler
-DMA2_DMA18_IRQHandler
-DMA3_DMA19_IRQHandler
-DMA4_DMA20_IRQHandler
-DMA5_DMA21_IRQHandler
-DMA6_DMA22_IRQHandler
-DMA7_DMA23_IRQHandler
-DMA8_DMA24_IRQHandler
-DMA9_DMA25_IRQHandler
-DMA10_DMA26_IRQHandler
-DMA11_DMA27_IRQHandler
-DMA12_DMA28_IRQHandler
-DMA13_DMA29_IRQHandler
-DMA14_DMA30_IRQHandler
-DMA15_DMA31_IRQHandler
-DMA_Error_IRQHandler
-MCM_IRQHandler
-FTFE_IRQHandler
-Read_Collision_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-Watchdog_IRQHandler
-RNG_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-CAN0_ORed_Message_buffer_IRQHandler
-CAN0_Bus_Off_IRQHandler
-CAN0_Error_IRQHandler
-CAN0_Tx_Warning_IRQHandler
-CAN0_Rx_Warning_IRQHandler
-CAN0_Wake_Up_IRQHandler
-I2S0_Tx_IRQHandler
-I2S0_Rx_IRQHandler
-CAN1_ORed_Message_buffer_IRQHandler
-CAN1_Bus_Off_IRQHandler
-CAN1_Error_IRQHandler
-CAN1_Tx_Warning_IRQHandler
-CAN1_Rx_Warning_IRQHandler
-CAN1_Wake_Up_IRQHandler
-Reserved59_IRQHandler
-UART0_LON_IRQHandler
-UART0_RX_TX_IRQHandler
-UART0_ERR_IRQHandler
-UART1_RX_TX_IRQHandler
-UART1_ERR_IRQHandler
-UART2_RX_TX_IRQHandler
-UART2_ERR_IRQHandler
-UART3_RX_TX_IRQHandler
-UART3_ERR_IRQHandler
-UART4_RX_TX_IRQHandler
-UART4_ERR_IRQHandler
-UART5_RX_TX_IRQHandler
-UART5_ERR_IRQHandler
-ADC0_IRQHandler
-ADC1_IRQHandler
-CMP0_IRQHandler
-CMP1_IRQHandler
-CMP2_IRQHandler
-FTM0_IRQHandler
-FTM1_IRQHandler
-FTM2_IRQHandler
-CMT_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT0_IRQHandler
-PIT1_IRQHandler
-PIT2_IRQHandler
-PIT3_IRQHandler
-PDB0_IRQHandler
-USB0_IRQHandler
-USBDCD_IRQHandler
-ENET_1588_Timer_IRQHandler
-ENET_Transmit_IRQHandler
-ENET_Receive_IRQHandler
-ENET_Error_IRQHandler
-Reserved95_IRQHandler
-SDHC_IRQHandler
-DAC0_IRQHandler
-DAC1_IRQHandler
-TSI0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-Reserved102_IRQHandler
-PORTA_IRQHandler
-PORTB_IRQHandler
-PORTC_IRQHandler
-PORTD_IRQHandler
-PORTE_IRQHandler
-PORTF_IRQHandler
-Reserved109_IRQHandler
-SWI_IRQHandler
-NFC_IRQHandler
-USBHS_IRQHandler
-Reserved113_IRQHandler
-CMP3_IRQHandler
-Reserved115_IRQHandler
-Reserved116_IRQHandler
-FTM3_IRQHandler
-ADC2_IRQHandler
-ADC3_IRQHandler
-I2S1_Tx_IRQHandler
-I2S1_Rx_IRQHandler
-DefaultISR
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END
diff --git a/bsp/K60Fxxxx/drivers/system_MK60F12.c b/bsp/K60Fxxxx/drivers/system_MK60F12.c
deleted file mode 100644
index ad97c1aa16..0000000000
--- a/bsp/K60Fxxxx/drivers/system_MK60F12.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
-** ###################################################################
-**     Compilers:           ARM Compiler
-**                          Freescale C/C++ for Embedded ARM
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**
-**     Reference manual:    K60P144M150SF3RM, Rev. 2, Dec 2011
-**     Version:             rev. 1.3, 2012-04-13
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
-**
-**     Revisions:
-**     - rev. 1.0 (2011-08-24)
-**         Initial version
-**     - rev. 1.1 (2011-11-03)
-**         Registers updated according to the new reference manual revision - Rev. 1, Oct 2011
-**         Registers of the following modules have been updated - AXBS, CAN, I2S, MCG, MPU, NFC, RCM, RTC, SDHC, SIM, USBHS, WDOG
-**         The following modules have been removed - DDR, DRY
-**     - rev. 1.2 (2012-01-04)
-**         Registers updated according to the new reference manual revision - Rev. 2, Dec 2011
-**         EWM - INTEN bit in EWM_CTRL register has been added.
-**         PDB - register PDB_PO0EN renamed to PRB_POEN.
-**         PMC - BGEN bit in PMC_REGSC register has been removed.
-**         SIM - several changes in SCGC registers. Bit USBHS in SOPT2 register removed.
-**         UART - new bits RXOFE in regiter CFIFO and RXOF in register SFIFO.
-**     - rev. 1.3 (2012-04-13)
-**         Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
-**         Added new #define symbols <peripheralType>_BASE_PTRS.
-**
-** ###################################################################
-*/
-
-/**
- * @file MK60F12
- * @version 1.3
- * @date 2012-04-13
- * @brief Device specific configuration file for MK60F12 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "MK60F12.h"
-
-#define DISABLE_WDOG    1
-
-
-#define CLOCK_SETUP     1
-/* Predefined clock setups
-   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
-         Reference clock source for MCG module is the slow internal clock source 32.768kHz
-         Core clock = 41.94MHz, BusClock = 41.94MHz
-   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
-         Reference clock source for MCG module is an external reference clock source 50MHz
-         Core clock = 120MHz, BusClock = 60MHz
-   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
-         Core clock/Bus clock derived directly from an external reference clock source 50MHz with no multiplication
-         Core clock = 50MHz, BusClock = 50MHz
-*/
-
-/*----------------------------------------------------------------------------
-  Define clock source values
- *----------------------------------------------------------------------------*/
-#if (CLOCK_SETUP == 0)
-    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
-    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
-    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
-    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
-    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
-    #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
-#elif (CLOCK_SETUP == 1)
-    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
-    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
-    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
-    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
-    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
-    #define DEFAULT_SYSTEM_CLOCK            120000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 2)
-    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
-    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
-    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
-    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
-    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
-    #define DEFAULT_SYSTEM_CLOCK            50000000u  /* Default System clock value */
-#endif /* (CLOCK_SETUP == 2) */
-
-
-/* ----------------------------------------------------------------------------
-   -- Core clock
-   ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
-   -- SystemInit()
-   ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
-#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
-  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
-#if (DISABLE_WDOG)
-  /* Disable the WDOG module */
-  /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
-  WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */
-  /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
-  WDOG->UNLOCK  = (uint16_t)0xD928u;    /* Key 2 */
-  /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
-  WDOG->STCTRLH = (uint16_t)0x01D2u;
-#endif /* (DISABLE_WDOG) */
-
-  /* System clock initialization */
-#if (CLOCK_SETUP == 0)
-  /* SIM_SCGC5: PORTA=1 */
-  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
-  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
-  /* SIM_SOPT2: PLLFLLSEL=0 */
-  SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
-  /* SIM_SOPT1: OSC32KSEL=0 */
-  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
-  /* SIM_SCGC1: OSC1=1 */
-  SIM->SCGC1 |= (uint32_t)0x20UL;
-  /* PORTA_PCR18: ISF=0,MUX=0 */
-  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
-  /* Switch to FEI Mode */
-  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0x06U;
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x20U;
-  /* MCG_C4: DMX32=0,DRST_DRS=1 */
-  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
-  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC0->CR = (uint8_t)0x80U;
-  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC1->CR = (uint8_t)0x80U;
-  /* MCG_C7: OSCSEL=0 */
-  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
-  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
-  MCG->C5 = (uint8_t)0x00U;
-  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  MCG->C6 = (uint8_t)0x00U;             /* 3 */
-  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
-  MCG->C11 = (uint8_t)0x00U;            /* 3 */
-  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
-  MCG->C12 = (uint8_t)0x00U;            /* 3 */
-  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
-  }
-  while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
-  }
-#elif (CLOCK_SETUP == 1)
-  /* SIM_SCGC5: PORTA=1 */
-  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
-  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x01350000UL; /* Update system prescalers */
-  /* SIM_SOPT2: PLLFLLSEL=1 */
-  SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
-  /* SIM_SOPT1: OSC32KSEL=0 */
-  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
-  /* SIM_SCGC1: OSC1=1 */
-  SIM->SCGC1 |= (uint32_t)0x20UL;
-  /* PORTA_PCR18: ISF=0,MUX=0 */
-  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
-  /* Switch to FBE Mode */
-  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC0->CR = (uint8_t)0x80U;
-  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC1->CR = (uint8_t)0x80U;
-  /* MCG_C7: OSCSEL=0 */
-  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x20U;
-  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0xAAU;
-  /* MCG_C4: DMX32=0,DRST_DRS=0 */
-  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
-  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
-  MCG->C5 = (uint8_t)0x04U;
-  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
-  MCG->C6 = (uint8_t)0x08U;
-  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
-  MCG->C11 = (uint8_t)0x00U;
-  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
-  MCG->C12 = (uint8_t)0x00U;
-  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
-  }
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-  /* Switch to PBE Mode */
-  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
-  MCG->C6 = (uint8_t)0x48U;
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
-  }
-  /* Switch to PEE Mode */
-  /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0x2AU;
-  while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
-  }
-#elif (CLOCK_SETUP == 2)
-  /* SIM_SCGC5: PORTA=1 */
-  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
-  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
-  /* SIM_SOPT2: PLLFLLSEL=0 */
-  SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
-  /* SIM_SOPT1: OSC32KSEL=0 */
-  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
-  /* SIM_SCGC1: OSC1=1 */
-  SIM->SCGC1 |= (uint32_t)0x20UL;
-  /* PORTA_PCR18: ISF=0,MUX=0 */
-  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
-  /* Switch to FBE Mode */
-  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC0->CR = (uint8_t)0x80U;
-  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC1->CR = (uint8_t)0x80U;
-  /* MCG_C7: OSCSEL=0 */
-  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x20U;
-  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0xAAU;
-  /* MCG_C4: DMX32=0,DRST_DRS=0 */
-  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
-  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
-  MCG->C5 = (uint8_t)0x00U;
-  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  MCG->C6 = (uint8_t)0x00U;
-  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
-  MCG->C11 = (uint8_t)0x00U;
-  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
-  MCG->C12 = (uint8_t)0x00U;
-  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
-  }
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-  /* Switch to BLPE Mode */
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
-  MCG->C2 = (uint8_t)0x22U;
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-#endif /* (CLOCK_SETUP == 2) */
-
-  /* Disable MPU */
-  MPU->CESR &= ~MPU_CESR_VLD_MASK;
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemCoreClockUpdate()
-   ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
-  uint8_t Divider;
-
-  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
-    /* Output of FLL or PLL is selected */
-    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
-      /* FLL is selected */
-      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
-        /* External reference clock is selected */
-        if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
-          MCGOUTClock = CPU_XTAL0_CLK_HZ;                                       /* System oscillator 0 drives MCG clock */
-        } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
-          MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
-        } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
-        Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
-        MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
-        if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
-          MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
-        } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
-      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
-        MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
-      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
-      /* Select correct multiplier to calculate the MCG output clock  */
-      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
-        case 0x0u:
-          MCGOUTClock *= 640u;
-          break;
-        case 0x20u:
-          MCGOUTClock *= 1280u;
-          break;
-        case 0x40u:
-          MCGOUTClock *= 1920u;
-          break;
-        case 0x60u:
-          MCGOUTClock *= 2560u;
-          break;
-        case 0x80u:
-          MCGOUTClock *= 732u;
-          break;
-        case 0xA0u:
-          MCGOUTClock *= 1464u;
-          break;
-        case 0xC0u:
-          MCGOUTClock *= 2197u;
-          break;
-        case 0xE0u:
-          MCGOUTClock *= 2929u;
-          break;
-        default:
-          break;
-      }
-    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
-      /* PLL is selected */
-      if ((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u) {
-        /* PLL1 output is selected */
-        if ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u) {
-          /* OSC1 clock source used as an external reference clock */
-          MCGOUTClock = CPU_XTAL1_CLK_HZ;
-        } else { /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
-          /* OSC0 clock source used as an external reference clock */
-          MCGOUTClock = CPU_XTAL0_CLK_HZ;
-        } /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
-        Divider = (1u + (MCG->C11 & MCG_C11_PRDIV1_MASK));
-        MCGOUTClock /= Divider;                                                  /* Calculate the PLL reference clock */
-        Divider = ((MCG->C12 & MCG_C12_VDIV1_MASK) + 16u);
-        MCGOUTClock = (MCGOUTClock * Divider) / 2u;                              /* Calculate the MCG output clock */
-      } else { /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
-        /* PLL0 output is selected */
-        if ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u) {
-          /* OSC1 clock source used as an external reference clock */
-          MCGOUTClock = CPU_XTAL1_CLK_HZ;
-        } else { /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
-          /* OSC0 clock source used as an external reference clock */
-          MCGOUTClock = CPU_XTAL0_CLK_HZ;
-        } /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
-        Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
-        MCGOUTClock /= Divider;                                                  /* Calculate the PLL reference clock */
-        Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 16u);
-        MCGOUTClock = (MCGOUTClock * Divider) / 2u;                              /* Calculate the MCG output clock */
-      } /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
-    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
-  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
-    /* Internal reference clock is selected */
-    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
-      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
-    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
-      MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
-    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
-  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
-    /* External reference clock is selected */
-    if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
-      MCGOUTClock = CPU_XTAL0_CLK_HZ;                                           /* System oscillator drives MCG clock */
-    } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
-      MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
-    } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
-  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
-    /* Reserved value */
-    return;
-  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
-  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
-}
diff --git a/bsp/K60Fxxxx/readme.txt b/bsp/K60Fxxxx/readme.txt
deleted file mode 100644
index dc8a5b820b..0000000000
--- a/bsp/K60Fxxxx/readme.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-board info:
-Freescale Tower TWR-K60F120M
-http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-K60F120M
-with:
-TWR-SER
-http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-SER
-and TWR-ELEV
-http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-ELEV
\ No newline at end of file
diff --git a/bsp/K60Fxxxx/rtconfig.h b/bsp/K60Fxxxx/rtconfig.h
deleted file mode 100644
index 6b676e1fe5..0000000000
--- a/bsp/K60Fxxxx/rtconfig.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	   8
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	8
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-
-#define RT_USING_OVERFLOW_CHECK
-
-/* Using Hook */
-#define RT_USING_HOOK
-
-#define IDLE_THREAD_STACK_SIZE     1024
-
-/* Using Software Timer */
-/* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex */
-#define RT_USING_MUTEX
-
-/* Using Event */
-#define RT_USING_EVENT
-
-/* Using MailBox */
-#define RT_USING_MAILBOX
-
-/* Using Message Queue */
-#define RT_USING_MESSAGEQUEUE
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management */
-#define RT_USING_HEAP
-
-/* Using Small MM */
-#define RT_USING_SMALL_MEM
-
-/* "Using Device Driver Framework" default="true" */
-#define RT_USING_DEVICE
-/* Using IPC in Device Driver Framework" default="true" */
-#define RT_USING_DEVICE_IPC
-/* Using Serial Device Driver Framework" default="true" */
-#define RT_USING_SERIAL
-
-
-/* SECTION: Console options */
-#define RT_USING_CONSOLE
-/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-
-/* SECTION: finsh, a C-Express shell */
-#define RT_USING_FINSH
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-
-/* SECTION: device filesystem */
-/* #define RT_USING_DFS */
-//#define RT_USING_DFS_ELMFAT
-#define RT_DFS_ELM_WORD_ACCESS
-/* Reentrancy (thread safe) of the FatFs module.  */
-#define RT_DFS_ELM_REENTRANT
-/* Number of volumes (logical drives) to be used. */
-#define RT_DFS_ELM_DRIVES			2
-/* #define RT_DFS_ELM_USE_LFN			1 */
-#define RT_DFS_ELM_MAX_LFN			255
-/* Maximum sector size to be handled. */
-#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
-
-#define RT_USING_DFS_ROMFS
-
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-
-/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-/* #define RT_USING_LWIP */
-/* LwIP uses RT-Thread Memory Management */
-#define RT_LWIP_USING_RT_MEM
-/* Enable ICMP protocol*/
-#define RT_LWIP_ICMP
-/* Enable UDP protocol*/
-#define RT_LWIP_UDP
-/* Enable TCP protocol*/
-#define RT_LWIP_TCP
-/* Enable DNS */
-#define RT_LWIP_DNS
-
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
-
-/* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	201
-
-/* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
-#define RT_LWIP_GWADDR3	1
-
-/* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
-
-/* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
-
-/* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
-
-/* TCP sender buffer space */
-#define RT_LWIP_TCP_SND_BUF	8192
-/* TCP receive window. */
-#define RT_LWIP_TCP_WND		8192
-
-#define CHECKSUM_CHECK_TCP              0
-#define CHECKSUM_CHECK_IP               0
-#define CHECKSUM_CHECK_UDP              0
-
-#define CHECKSUM_GEN_TCP                0
-#define CHECKSUM_GEN_IP                 0
-#define CHECKSUM_GEN_UDP                0
-
-#endif
diff --git a/bsp/K60Fxxxx/rtconfig.py b/bsp/K60Fxxxx/rtconfig.py
deleted file mode 100644
index 9cadb65f6c..0000000000
--- a/bsp/K60Fxxxx/rtconfig.py
+++ /dev/null
@@ -1,83 +0,0 @@
-import os
-
-# toolchains options
-ARCH='arm'
-CPU='cortex-m4'
-CROSS_TOOL='keil'
-
-if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
-
-# cross_tool provides the cross compiler
-# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
-if  CROSS_TOOL == 'gcc':
-	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
-elif CROSS_TOOL == 'keil':
-	PLATFORM 	= 'armcc'
-	EXEC_PATH 	= 'C:/Keil'
-elif CROSS_TOOL == 'iar':
-    print '================ERROR============================'
-    print 'Not support iar yet!'
-    print '================================================='
-    exit(0)
-
-if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-BUILD = 'debug'
-TOWER_TYPE = 'K60FN1M0'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arm-none-eabi-'
-    CC = PREFIX + 'gcc'
-    AS = PREFIX + 'gcc'
-    AR = PREFIX + 'ar'
-    LINK = PREFIX + 'gcc'
-    TARGET_EXT = 'axf'
-    SIZE = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY = PREFIX + 'objcopy'
-
-    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
-    CFLAGS = DEVICE 
-    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T k60_rom.ld'
-
-    CPATH = ''
-    LPATH = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMSTM'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k60.map --scatter k60_rom.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
diff --git a/bsp/K60Fxxxx/template.uvproj b/bsp/K60Fxxxx/template.uvproj
deleted file mode 100644
index f67835070a..0000000000
--- a/bsp/K60Fxxxx/template.uvproj
+++ /dev/null
@@ -1,394 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>rt-thread_mk60f120m</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>MK60FN1M0xxx12</Device>
-          <Vendor>Freescale Semiconductor</Vendor>
-          <Cpu>IRAM(0x1FFF0000-0x1FFFFFFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x0-0xFFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4")  FPU2 ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"STARTUP\Freescale\Kinetis\startup_MK60F12.s" ("Freescale MK60Xxxxxxx12 Startup Code")</StartupFile>
-          <FlashDriverDll>ULP2CM3(-O2510 -S0 -C0 -FO15 -FD20000000 -FC4000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000)</FlashDriverDll>
-          <DeviceId>6123</DeviceId>
-          <RegisterFile>MK60F12.H</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>SFD\Freescale\Kinetis\MK60F12.sfr</SFDFile>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath>Freescale\Kinetis\</RegisterFilePath>
-          <DBRegisterFilePath>Freescale\Kinetis\</DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>thread-mk60f120m</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>-MPU</SimDllArguments>
-          <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments>-MPU</TargetDllArguments>
-          <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <RestoreTracepoints>1</RestoreTracepoints>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>12</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>PEMicro\Pemicro_ArmCortexInterface.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4103</DriverSelection>
-          </Flash1>
-          <bUseTDR>0</bUseTDR>
-          <Flash2>PEMicro\Pemicro_ArmCortexInterface.dll</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M4"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>2</RvdsVP>
-            <hadIRAM2>1</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>0</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x1fff0000</StartAddress>
-                <Size>0x10000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x1fff0000</StartAddress>
-                <Size>0x10000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x1FFF0000</DataAddressRange>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-    </Target>
-  </Targets>
-
-</Project>
diff --git a/bsp/lpc1114/application.c b/bsp/lpc1114/application.c
deleted file mode 100644
index 40f1fd4234..0000000000
--- a/bsp/lpc1114/application.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-/**
- * @addtogroup LPC1100
- */
-/*@{*/
-#include <rtthread.h>
-
-int rt_application_init()
-{
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/lpc1114/board.c b/bsp/lpc1114/board.c
deleted file mode 100644
index ca6d5b5379..0000000000
--- a/bsp/lpc1114/board.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "board.h"
-#include "uart.h"
-
-#include <CMSIS/LPC11xx.h>
-#include <CMSIS/core_cm0.h>
-#include <CMSIS/system_LPC11xx.h>
-
-/**
- * @addtogroup LPC1100
- */
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler()
-{
-	/* enter interrupt */
-	rt_interrupt_enter();
-
-	rt_tick_increase();
-
-	/* leave interrupt */
-	rt_interrupt_leave();
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init()
-{
-	SystemInit();
-
-	/* init systick */
-	SysTick_Config(SystemCoreClock);
-
-	/* set pend exception priority */
-	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
-	
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
-#endif
-#ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart");
-#endif
-}
-/*@}*/
diff --git a/bsp/lpc1114/board.h b/bsp/lpc1114/board.h
deleted file mode 100644
index a8f6dd9f87..0000000000
--- a/bsp/lpc1114/board.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-#endif
diff --git a/bsp/lpc1114/project.uvopt b/bsp/lpc1114/project.uvopt
deleted file mode 100644
index 642c736c20..0000000000
--- a/bsp/lpc1114/project.uvopt
+++ /dev/null
@@ -1,1947 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>RT-Thread LPC1100</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>1</RunSim>
-        <RunTarget>0</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>0</CpuCode>
-      <DllOpt>
-        <SimDllName>SARMCM3.DLL</SimDllName>
-        <SimDllArguments></SimDllArguments>
-        <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
-        <SimDlgDllArguments></SimDlgDllArguments>
-        <TargetDllName>SARMCM3.DLL</TargetDllName>
-        <TargetDllArguments></TargetDllArguments>
-        <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
-        <TargetDlgDllArguments></TargetDlgDllArguments>
-      </DllOpt>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <nTsel>11</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>..\TKScope\UL2ARM_TKSCP_DRV_ARM_for_AGDI.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>DLGDARM</Key>
-          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>DLGTARM</Key>
-          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
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diff --git a/bsp/lpc1114/project.uvproj b/bsp/lpc1114/project.uvproj
deleted file mode 100644
index c3544a9a19..0000000000
--- a/bsp/lpc1114/project.uvproj
+++ /dev/null
@@ -1,549 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
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-      <TargetName>RT-Thread LPC1100</TargetName>
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-      <ToolsetName>ARM-ADS</ToolsetName>
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-          <Vendor>NXP (founded by Philips)</Vendor>
-          <Cpu>IRAM(0x10000000-0x10001FFF) IROM(0-0x7FFF) CLOCK(50000000) CPUTYPE("Cortex-M0")</Cpu>
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-          <Asm></Asm>
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-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
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-          <DBRegisterFilePath>NXP\LPC11xx\</DBRegisterFilePath>
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-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
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-          <OutputName>rtthread-lpc1100</OutputName>
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-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
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-          </TargetDlls>
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-        <Utilities>
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-        </Utilities>
-        <TargetArmAds>
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-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
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-            <EndSel>0</EndSel>
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-              <FileType>5</FileType>
-              <FilePath>.\rtconfig.h</FilePath>
-            </File>
-            <File>
-              <FileName>board.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>.\board.h</FilePath>
-            </File>
-            <File>
-              <FileName>uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\uart.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Kernel</GroupName>
-          <Files>
-            <File>
-              <FileName>clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>device.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
-            </File>
-            <File>
-              <FileName>idle.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\idle.c</FilePath>
-            </File>
-            <File>
-              <FileName>irq.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\irq.c</FilePath>
-            </File>
-            <File>
-              <FileName>kservice.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\kservice.c</FilePath>
-            </File>
-            <File>
-              <FileName>mempool.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mempool.c</FilePath>
-            </File>
-            <File>
-              <FileName>object.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
-            </File>
-            <File>
-              <FileName>scheduler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler.c</FilePath>
-            </File>
-            <File>
-              <FileName>slab.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\slab.c</FilePath>
-            </File>
-            <File>
-              <FileName>timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
-            </File>
-            <File>
-              <FileName>thread.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
-            </File>
-            <File>
-              <FileName>mem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mem.c</FilePath>
-            </File>
-            <File>
-              <FileName>ipc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\ipc.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>LPC1100</GroupName>
-          <Files>
-            <File>
-              <FileName>cpu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\cpu.c</FilePath>
-            </File>
-            <File>
-              <FileName>fault.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\fault.c</FilePath>
-            </File>
-            <File>
-              <FileName>interrupt.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\interrupt.c</FilePath>
-            </File>
-            <File>
-              <FileName>stack.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\stack.c</FilePath>
-            </File>
-            <File>
-              <FileName>context_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\context_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>fault_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\fault_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>start_rvds.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\start_rvds.s</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>core_cm0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\CMSIS\core_cm0.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_LPC11xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc1100\CMSIS\system_LPC11xx.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-</Project>
diff --git a/bsp/lpc1114/rtconfig.h b/bsp/lpc1114/rtconfig.h
deleted file mode 100644
index ff350a752d..0000000000
--- a/bsp/lpc1114/rtconfig.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	4
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	8
-
-/* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug*/
-/* #define RT_THREAD_DEBUG */
-
-/* Using Hook*/
-/* #define RT_USING_HOOK */
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex*/
-/* #define RT_USING_MUTEX */
-
-/* Using Event*/
-/* #define RT_USING_EVENT */
-
-/* Using MailBox*/
-#define RT_USING_MAILBOX
-
-/* Using Message Queue*/
-/* #define RT_USING_MESSAGEQUEUE */
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-/* #define RT_USING_MEMPOOL */
-
-/* Using Dynamic Heap Management*/
-/* #define RT_USING_HEAP */
-
-/* Using Small MM*/
-#define RT_USING_SMALL_MEM
-#define RT_USING_TINY_SIZE
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-
-/* buffer size for UART reception */
-#define RT_UART_RX_BUFFER_SIZE	64
-
-/* Using UART */
-#define RT_USING_UART
-
-/* SECTION: Console options */
-/* use console for rt_kprintf */
-#define RT_USING_CONSOLE
-/* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	80
-
-#endif
diff --git a/bsp/lpc1114/startup.c b/bsp/lpc1114/startup.c
deleted file mode 100644
index 43f55cb3d9..0000000000
--- a/bsp/lpc1114/startup.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#ifdef RT_USING_UART
-#include "uart.h"
-#endif
-
-/**
- * @addtogroup sam7s
- */
-
-/*@{*/
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#endif
-
-#ifdef __GNUC__
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-#endif
-
-extern void rt_hw_interrupt_init(void);
-extern int  rt_application_init(void);
-#ifdef RT_USING_DEVICE
-extern rt_err_t rt_hw_serial_init(void);
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init board */
-	rt_hw_board_init();
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-#ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
-#elif __ICCARM__
-    rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
-#else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
-#endif
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_HOOK /* if the hook is used */
-	/* set idle thread hook */
-	rt_thread_idle_sethook(rt_hw_led_flash);
-#endif
-
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart1");
-#endif
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main (void)
-{
-	rt_uint32_t UNUSED level;
-
-	/* disable interrupt first */
-	level = rt_hw_interrupt_disable();
-
-	/* invoke rtthread_startup */
-	rtthread_startup();
-	
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/lpc1114/uart.c b/bsp/lpc1114/uart.c
deleted file mode 100644
index c03f0e7ea4..0000000000
--- a/bsp/lpc1114/uart.c
+++ /dev/null
@@ -1,266 +0,0 @@
-#include <rthw.h>
-#include <rtthread.h>
-#include <CMSIS/LPC11xx.h>
-
-#define IER_RBR		0x01
-#define IER_THRE	0x02
-#define IER_RLS		0x04
-
-#define IIR_PEND	0x01
-#define IIR_RLS		0x03
-#define IIR_RDA		0x02
-#define IIR_CTI		0x06
-#define IIR_THRE	0x01
-
-#define LSR_RDR		0x01
-#define LSR_OE		0x02
-#define LSR_PE		0x04
-#define LSR_FE		0x08
-#define LSR_BI		0x10
-#define LSR_THRE	0x20
-#define LSR_TEMT	0x40
-#define LSR_RXFE	0x80
-
-/**
- * @addtogroup LPC11xx
- */
-
-/*@{*/
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
-
-#define UART_BAUDRATE   115200
-struct rt_uart_lpc
-{
-	struct rt_device parent;
-
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-void UART_IRQHandler(void)
-{
-	rt_ubase_t level, iir;
-    struct rt_uart_lpc* uart = &uart_device;
-
-    /* read IIR and clear it */
-	iir = LPC_UART->IIR;
-
-	iir >>= 1;			    /* skip pending bit in IIR */
-	iir &= 0x07;			/* check bit 1~3, interrupt identification */
-
-	if (iir == IIR_RDA)	    /* Receive Data Available */
-	{
-		/* Receive Data Available */
-        uart->rx_buffer[uart->save_index] = LPC_UART->RBR;
-
-        level = rt_hw_interrupt_disable();
-		uart->save_index ++;
-        if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-            uart->save_index = 0;
-        rt_hw_interrupt_enable(level);
-
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
-                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-            else
-                length = uart->save_index - uart->read_index;
-
-            uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
-
-	return;
-}
-
-static rt_err_t rt_uart_init (rt_device_t dev)
-{
-	rt_uint32_t Fdiv;
-	rt_uint32_t regVal;
-
-	/* Init UART Hardware */
-	LPC_IOCON->PIO1_6 &= ~0x07;    /*  UART I/O config */
-	LPC_IOCON->PIO1_6 |= 0x01;     /* UART RXD */
-	LPC_IOCON->PIO1_7 &= ~0x07;
-	LPC_IOCON->PIO1_7 |= 0x01;     /* UART TXD */
-
-	/* Enable UART clock */
-	LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
-	LPC_SYSCON->UARTCLKDIV = 0x1;     /* divided by 1 */
-
-	LPC_UART->LCR = 0x83;             /* 8 bits, no Parity, 1 Stop bit */
-	regVal = LPC_SYSCON->UARTCLKDIV;
-
-    /* set baudrate */
-    regVal = LPC_SYSCON->UARTCLKDIV;
-    Fdiv = (((SystemCoreClock/LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/UART_BAUDRATE ;
-
-	LPC_UART->DLM = Fdiv / 256;
-	LPC_UART->DLL = Fdiv % 256;
-	LPC_UART->LCR = 0x03;		/* DLAB = 0 */
-	LPC_UART->FCR = 0x07;		/* Enable and reset TX and RX FIFO. */
-
-	/* Read to clear the line status. */
-	regVal = LPC_UART->LSR;
-
-	/* Ensure a clean start, no data in either TX or RX FIFO. */
-	while (( LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
-	while ( LPC_UART->LSR & LSR_RDR )
-	{
-		regVal = LPC_UART->RBR;	/* Dump data from RX FIFO */
-	}
-
-	LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS;	/* Enable UART interrupt */
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		NVIC_EnableIRQ(UART_IRQn);
-	}
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		NVIC_DisableIRQ(UART_IRQn);
-	}
-
-	return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-	rt_uint8_t* ptr;
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	RT_ASSERT(uart != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
-
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++;
-			size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-
-	return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-	char *ptr;
-	ptr = (char*)buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* THRE status, contain valid data */
-				while ( !(LPC_UART->LSR & LSR_THRE) );
-				/* write data */
-				LPC_UART->THR = '\r';
-			}
-
-			/* THRE status, contain valid data */
-			while ( !(LPC_UART->LSR & LSR_THRE) );	
-			/* write data */
-			LPC_UART->THR = *ptr;
-			
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-	while ( size != 0 )
-	{
-		/* THRE status, contain valid data */
-		while ( !(LPC_UART->LSR & LSR_THRE) );
-
-		/* write data */
-		LPC_UART->THR = *ptr;
-
-		ptr++;
-		size--;
-	}
-	}
-
-	return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-	struct rt_uart_lpc* uart;
-
-	/* get uart device */
-	uart = &uart_device;
-
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
-
-	uart->parent.rx_indicate = RT_NULL;
-	uart->parent.tx_complete = RT_NULL;
-
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
-
-	rt_device_register(&uart->parent,
-		"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
-}
-#endif /* end of UART */
-
-/*@}*/
diff --git a/bsp/lpc1114/uart.h b/bsp/lpc1114/uart.h
deleted file mode 100644
index c5ca6c70c4..0000000000
--- a/bsp/lpc1114/uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UART_H__
-#define __UART_H__
-
-void rt_hw_uart_init(void);
-
-#endif
diff --git a/bsp/lpc122x/FLASH.ini b/bsp/lpc122x/FLASH.ini
deleted file mode 100644
index bf88b04f64..0000000000
--- a/bsp/lpc122x/FLASH.ini
+++ /dev/null
@@ -1,28 +0,0 @@
-/***********************************************************************/
-/*  This file is part of the ARM Compiler package                      */
-/*  Copyright KEIL ELEKTRONIK GmbH 1992-2004                           */
-/***********************************************************************/
-/*                                                                     */
-/*  RAM.INI: RAM Initialization File                                   */
-/*                                                                     */
-/***********************************************************************/
-
-
-//*** <<< Use Configuration Wizard in Context Menu >>> *** 
-
-FUNC void Pre_Setup (void) {
-  _WDWORD(0x40048000, 0x00000002);   // MEMMAP = 2
-}
-
-FUNC void Setup (void) {
-  SP = _RDWORD(0x00000000);
-  PC = _RDWORD(0x00000004);
-}
-
-Pre_Setup();
-
-LOAD .\Obj\gpiotest.axf INCREMENTAL          // Download
-
-Setup();                                   // Setup for Running
-
-// g, main
diff --git a/bsp/lpc122x/application.c b/bsp/lpc122x/application.c
deleted file mode 100644
index 33d6bad33f..0000000000
--- a/bsp/lpc122x/application.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- *
- */
-
-/**
- * @addtogroup LPC122x
- */
-/*@{*/
-#include <rtthread.h>
-#include "tc_comm.h"
-
-/*
- * This is an example for delay thread
- */
-static struct rt_thread thread;
-static char thread_stack[THREAD_STACK_SIZE];
-static void thread_entry(void* parameter)
-{
-	rt_tick_t tick;
-	rt_kprintf("thread inited ok\n");
-
-	tick = rt_tick_get();
-	rt_kprintf("thread tick %d\n", tick);
-	rt_kprintf("thread delay 10 tick\n");
-	rt_thread_delay(10);
-	
-	if (rt_tick_get() - tick > 10)
-	{
-		tc_done(TC_STAT_FAILED);
-		return;
-	}
-
-	tick = rt_tick_get();
-	rt_kprintf("thread delay 15 tick\n");
-	rt_thread_delay(15);
-	if (rt_tick_get() - tick > 15)
-	{
-		tc_done(TC_STAT_FAILED);
-		return;
-	}
-
-	rt_kprintf("thread exit\n");
-
-	tc_done(TC_STAT_PASSED);
-}
-
-rt_err_t thread_delay_init()
-{
-	rt_err_t result;
-
-	result = rt_thread_init(&thread,
-		"test",
-		thread_entry, RT_NULL,
-		&thread_stack[0], sizeof(thread_stack),
-		THREAD_PRIORITY, 10);
-
-	if (result == RT_EOK)
-		rt_thread_startup(&thread);
-	else
-		tc_stat(TC_STAT_END | TC_STAT_FAILED);
-
-	return result;
-}
-
-int rt_application_init()
-{
-	thread_delay_init();
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/lpc122x/board.c b/bsp/lpc122x/board.c
deleted file mode 100644
index 1aa1d1ff16..0000000000
--- a/bsp/lpc122x/board.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "board.h"
-#include "uart.h"
-
-#include <CMSIS/LPC122x.h>
-#include <CMSIS/core_cm0.h>
-
-#define SYSTICK_DELAY		0x0007A11F
-
-/**
- * @addtogroup LPC122x
- */
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler()
-{
-	/* enter interrupt */
-	rt_interrupt_enter();
-
-	rt_tick_increase();
-
-	/* leave interrupt */
-	rt_interrupt_leave();
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init()
-{
-	SystemInit();
-
-	/* init systick */
-	SysTick_Config( SYSTICK_DELAY );
-
-	/* set pend exception priority */
-	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
-	
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
-#endif
-#ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart0");
-#endif
-}
-/*@}*/
diff --git a/bsp/lpc122x/board.h b/bsp/lpc122x/board.h
deleted file mode 100644
index a8f6dd9f87..0000000000
--- a/bsp/lpc122x/board.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-#endif
diff --git a/bsp/lpc122x/lpc122x.uvopt b/bsp/lpc122x/lpc122x.uvopt
deleted file mode 100644
index 23f70fbef3..0000000000
--- a/bsp/lpc122x/lpc122x.uvopt
+++ /dev/null
@@ -1,636 +0,0 @@
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index 0df9f59db5..0000000000
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-            <File>
-              <FileName>stack.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc122x\stack.c</FilePath>
-            </File>
-            <File>
-              <FileName>context_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\lpc122x\context_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>fault_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\lpc122x\fault_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>start_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\lpc122x\start_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>tc_comm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\examples\kernel\tc_comm.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>system_LPC122x.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc122x\CMSIS\system_LPC122x.c</FilePath>
-            </File>
-            <File>
-              <FileName>core_cm0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\lpc122x\CMSIS\core_cm0.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-</Project>
diff --git a/bsp/lpc122x/rtconfig.h b/bsp/lpc122x/rtconfig.h
deleted file mode 100644
index ff350a752d..0000000000
--- a/bsp/lpc122x/rtconfig.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	4
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	8
-
-/* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug*/
-/* #define RT_THREAD_DEBUG */
-
-/* Using Hook*/
-/* #define RT_USING_HOOK */
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex*/
-/* #define RT_USING_MUTEX */
-
-/* Using Event*/
-/* #define RT_USING_EVENT */
-
-/* Using MailBox*/
-#define RT_USING_MAILBOX
-
-/* Using Message Queue*/
-/* #define RT_USING_MESSAGEQUEUE */
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-/* #define RT_USING_MEMPOOL */
-
-/* Using Dynamic Heap Management*/
-/* #define RT_USING_HEAP */
-
-/* Using Small MM*/
-#define RT_USING_SMALL_MEM
-#define RT_USING_TINY_SIZE
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-
-/* buffer size for UART reception */
-#define RT_UART_RX_BUFFER_SIZE	64
-
-/* Using UART */
-#define RT_USING_UART
-
-/* SECTION: Console options */
-/* use console for rt_kprintf */
-#define RT_USING_CONSOLE
-/* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	80
-
-#endif
diff --git a/bsp/lpc122x/startup.c b/bsp/lpc122x/startup.c
deleted file mode 100644
index 43f55cb3d9..0000000000
--- a/bsp/lpc122x/startup.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#ifdef RT_USING_UART
-#include "uart.h"
-#endif
-
-/**
- * @addtogroup sam7s
- */
-
-/*@{*/
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#endif
-
-#ifdef __GNUC__
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-#endif
-
-extern void rt_hw_interrupt_init(void);
-extern int  rt_application_init(void);
-#ifdef RT_USING_DEVICE
-extern rt_err_t rt_hw_serial_init(void);
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init board */
-	rt_hw_board_init();
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-#ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
-#elif __ICCARM__
-    rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
-#else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
-#endif
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_HOOK /* if the hook is used */
-	/* set idle thread hook */
-	rt_thread_idle_sethook(rt_hw_led_flash);
-#endif
-
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart1");
-#endif
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main (void)
-{
-	rt_uint32_t UNUSED level;
-
-	/* disable interrupt first */
-	level = rt_hw_interrupt_disable();
-
-	/* invoke rtthread_startup */
-	rtthread_startup();
-	
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/lpc122x/uart.c b/bsp/lpc122x/uart.c
deleted file mode 100644
index 83d17b36f2..0000000000
--- a/bsp/lpc122x/uart.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/****************************************************************************
- *   $Id:: uart.c 3736 2010-06-24 02:07:03Z usb00423                        $
- *   Project: NXP LPC122x UART example
- *
- *   Description:
- *     This file contains UART code example which include UART 
- *     initialization, UART interrupt handler, and related APIs for 
- *     UART access.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#include <rthw.h>
-#include <rtthread.h>
-#include <CMSIS/LPC122x.h>
-
-#include "uart.h"
-
-#define IER_RBR		0x01
-#define IER_THRE	0x02
-#define IER_RLS		0x04
-
-#define IIR_PEND	0x01
-#define IIR_RLS		0x03
-#define IIR_RDA		0x02
-#define IIR_CTI		0x06
-#define IIR_THRE	0x01
-
-#define LSR_RDR		0x01
-#define LSR_OE		0x02
-#define LSR_PE		0x04
-#define LSR_FE		0x08
-#define LSR_BI		0x10
-#define LSR_THRE	0x20
-#define LSR_TEMT	0x40
-#define LSR_RXFE	0x80
-
-/**
- * @addtogroup LPC11xx
- */
-
-/*@{*/
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
-
-#define UART_BAUDRATE   115200
-
-struct rt_uart_lpc
-{
-	struct rt_device parent;
-
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-void UART0_IRQHandler(void)
-{
-	rt_ubase_t level, iir;
-	struct rt_uart_lpc* uart = &uart_device;
-
-	/* read IIR and clear it */
-	iir = LPC_UART0->IIR;
-
-	iir >>= 0x01;		/* skip pending bit in IIR */
-	iir  &= 0x07;		/* check bit 1~3, interrupt identification */
-
-	if (iir == IIR_RDA)	/* Receive Line Status */
-	{
-		/* If no error on RLS, normal ready, save into the data buffer. */
-		/* Note: read RBR will clear the interrupt */
-		uart->rx_buffer[uart->save_index] = LPC_UART0->RBR;
-		level = rt_hw_interrupt_disable();
-		uart->save_index ++;
-		if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-	   		uart->save_index = 0;
-		rt_hw_interrupt_enable(level);
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
-	            length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-	        else
-	            length = uart->save_index - uart->read_index;
-	
-	        uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
-	return;
-}
-
-/*****************************************************************************
-** Function name:		rt_uart_init
-** Descriptions:		
-** parameters:			dev
-** Returned value:		None
-*****************************************************************************/
-static rt_err_t rt_uart_init(rt_device_t dev)
-{
-	rt_uint32_t Fdiv;
-	rt_uint32_t regVal;
-
-	NVIC_DisableIRQ(UART0_IRQn);
-	
-	/* Init UART Hardware */
-	LPC_IOCON->PIO0_1  &= ~0x07;		/* UART I/O config */
-	LPC_IOCON->PIO0_1  |=  0x02;		/* UART RXD */
-	LPC_IOCON->PIO0_2  &= ~0x07;	
-	LPC_IOCON->PIO0_2  |=  0x02;		/* UART TXD */
-	
-	/* Enable UART clock */
-	LPC_SYSCON->PRESETCTRL    |= (0x1<<2);
-	LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<12);
-	LPC_SYSCON->UART0CLKDIV    =  0x1;	/* divided by 1 */
-	
-	LPC_UART0->LCR = 0x83;				/* 8 bits, no Parity, 1 Stop bit */
-	regVal = LPC_SYSCON->UART0CLKDIV;
-	Fdiv = ((SystemAHBFrequency/regVal)/16)/UART_BAUDRATE ;	/*baud rate */
-	
-	LPC_UART0->DLM = Fdiv / 256;							
-	LPC_UART0->DLL = Fdiv % 256;
-	LPC_UART0->LCR = 0x03;				/* DLAB = 0 */
-	LPC_UART0->FCR = 0x07;				/* Enable and reset TX and RX FIFO. */
-	
-	/* Read to clear the line status. */
-	regVal = LPC_UART0->LSR;
-	
-	/* Ensure a clean start, no data in either TX or RX FIFO. */
-	while ( LPC_UART0->LSR & (LSR_THRE|LSR_TEMT) != (LSR_THRE|LSR_TEMT) );
-	while ( LPC_UART0->LSR & LSR_RDR )
-	{
-		regVal = LPC_UART0->RBR;		/* Dump data from RX FIFO */
-	}
- 
-	/* Enable the UART Interrupt */
-	NVIC_EnableIRQ(UART0_IRQn);
-	
-	LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS;	/* Enable UART interrupt */
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-	RT_ASSERT(dev != RT_NULL);
-	if(dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		NVIC_EnableIRQ(UART0_IRQn);
-	}
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		NVIC_DisableIRQ(UART0_IRQn);
-	}
-
-	return RT_EOK;
-}
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-	rt_uint8_t* ptr;
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	RT_ASSERT(uart != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
-
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++;
-			size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-
-	return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-	char *ptr;
-	ptr = (char*)buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* THRE status, contain valid data */
-				while ( !(LPC_UART0->LSR & LSR_THRE) );
-				/* write data */
-				LPC_UART0->THR = '\r';
-			}
-
-			/* THRE status, contain valid data */
-			while ( !(LPC_UART0->LSR & LSR_THRE) );	
-			/* write data */
-			LPC_UART0->THR = *ptr;
-			
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-	while ( size != 0 )
-	{
-		/* THRE status, contain valid data */
-		while ( !(LPC_UART0->LSR & LSR_THRE) );
-
-		/* write data */
-		LPC_UART0->THR = *ptr;
-
-		ptr++;
-		size--;
-	}
-	}
-
-	return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-	struct rt_uart_lpc* uart;
-
-	/* get uart device */
-	uart = &uart_device;
-
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
-
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
-
-	rt_device_register(&uart->parent,
-		"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
-}
-
-#endif
-
-/******************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/bsp/lpc122x/uart.h b/bsp/lpc122x/uart.h
deleted file mode 100644
index c5ca6c70c4..0000000000
--- a/bsp/lpc122x/uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UART_H__
-#define __UART_H__
-
-void rt_hw_uart_init(void);
-
-#endif
diff --git a/bsp/sam7s/application.c b/bsp/sam7s/application.c
deleted file mode 100644
index 4a09f8b951..0000000000
--- a/bsp/sam7s/application.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-06-05     Bernard      the first version
- */
-
-/**
- * @addtogroup sam7s
- */
-/*@{*/
-#include <rtthread.h>
-
-int rt_application_init()
-{
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/sam7s/board.c b/bsp/sam7s/board.c
deleted file mode 100644
index b7f92495ca..0000000000
--- a/bsp/sam7s/board.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-23     Bernard      first implementation
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include <AT91SAM7S.h>
-#include "board.h"
-
-static void rt_hw_board_led_init(void);
-
-/**
- * @addtogroup sam7s
- */
-/*@{*/
-
-/* Periodic Interval Value */
-#define PIV  (((MCK/16)/1000)*(1000/RT_TICK_PER_SECOND))
-
-/**
- * This is the timer interrupt service routine.
- * @param vector the irq number for timer
- */
-void rt_hw_timer_handler(int vector)
-{
-	if (AT91C_PITC_PISR & 0x01)
-	{
-		/* increase a tick */
-		rt_tick_increase();
-
-		/* ack interrupt */
-		AT91C_AIC_EOICR = AT91C_PITC_PIVR;
-	}
-	else
-	{
-		/* end of interrupt */
-		AT91C_AIC_EOICR = 0;
-	}
-}
-
-						/* PIO   Flash    PA    PB   PIN */ 
-#define LED 	(1 << 8)/* PA8          & TWD  NPCS3  43 */ 
-
-/** 
- * This function will init led on the board
- */
-static void rt_hw_board_led_init()
-{
- 	/* Enable Clock for PIO */
-	AT91C_PMC_PCER = 1 << AT91C_ID_PIOA;
-
-	/* configure PIO as output for led */
-	AT91C_PIO_PER = LED;
-	AT91C_PIO_OER = LED;
-}
-
-/** 
- * This function will take the led on board on.
- *
- * @param n the number nth led
- */
-void rt_hw_board_led_on()
-{
-	AT91C_PIO_CODR = LED;
-}
-
-/** 
- * This function will take the led on board off.
- *
- * @param n the number nth led
- */
-void rt_hw_board_led_off()
-{
-	AT91C_PIO_SODR = LED;
-}
-
-void rt_hw_led_flash()
-{
-	int i;
-
-	rt_hw_board_led_off();
-	for (i = 0; i < 2000000; i ++);
-
-	rt_hw_board_led_on();
-	for (i = 0; i < 2000000; i ++);
-}
-
-/*
- * RT-Thread Console Interface, used by rt_kprintf
- */
-/**
- * This function is used to display a string on console, normally, it's
- * invoked by rt_kprintf
- *
- * @param str the displayed string
- */
-void rt_hw_console_output(const char* str)
-{
-	while (*str)
-	{
-		if (*str == '\n')
-		{
-			while (!(AT91C_US0_CSR & AT91C_US_TXRDY));
-			AT91C_US0_THR = '\r';
-		}
-		
-		/* Wait for Empty Tx Buffer */
-		while (!(AT91C_US0_CSR & AT91C_US_TXRDY));
-		/* Transmit Character */
-		AT91C_US0_THR = *str;
-		
-		str ++;
-	}
-}
-
-static void rt_hw_console_init()
-{
-	/* Enable Clock for USART0 */
-	AT91C_PMC_PCER = 1 << AT91C_ID_US0;
-	/* Enable RxD0 and TxDO Pin */
-	AT91C_PIO_PDR = (1 << 5) | (1 << 6);
-
-	AT91C_US0_CR = AT91C_US_RSTRX	|		/* Reset Receiver      */
-				AT91C_US_RSTTX		|		/* Reset Transmitter   */
-				AT91C_US_RXDIS		|		/* Receiver Disable    */
-				AT91C_US_TXDIS;				/* Transmitter Disable */
-
-	AT91C_US0_MR = AT91C_US_USMODE_NORMAL |		/* Normal Mode */
-				AT91C_US_CLKS_CLOCK		|		/* Clock = MCK */
-				AT91C_US_CHRL_8_BITS	|		/* 8-bit Data  */
-				AT91C_US_PAR_NONE		|		/* No Parity   */
-				AT91C_US_NBSTOP_1_BIT;			/* 1 Stop Bit  */
-
-	/* set baud rate divisor */
-	AT91C_US0_BRGR = BRD;
-
-	AT91C_US0_CR = AT91C_US_RXEN |	/* Receiver Enable     */
-				AT91C_US_TXEN;	/* Transmitter Enable  */
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init()
-{
-	extern void rt_serial_init(void);
-	
-	/* init hardware console */
-	rt_hw_console_init();
-
-	/* init led */
-	rt_hw_board_led_init();
-
-	/* init PITC */
-	AT91C_PITC_PIMR = (1 << 25) | (1 << 24) | PIV;
-	/* install timer handler */
-	rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL);
-	AT91C_AIC_SMR(AT91C_ID_SYS) = 0;
-	rt_hw_interrupt_umask(AT91C_ID_SYS);
-}
-/*@}*/
diff --git a/bsp/sam7s/board.h b/bsp/sam7s/board.h
deleted file mode 100644
index 2df27acc3a..0000000000
--- a/bsp/sam7s/board.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-10-08     Bernard      add board.h to this bsp
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include <AT91SAM7S.h>
-
-#define AT91C_US_RXRDY			((unsigned int) 0x1 <<  0)	/* US RXRDY Interrupt */
-#define AT91C_US_TXRDY			((unsigned int) 0x1 <<  1)	/* US TXRDY Interrupt */
-#define AT91C_US_RSTRX			((unsigned int) 0x1 <<  2)	/* US Reset Receiver */
-#define AT91C_US_RSTTX			((unsigned int) 0x1 <<  3)	/* US Reset Transmitter */
-#define AT91C_US_RXEN			((unsigned int) 0x1 <<  4)	/* US Receiver Enable */
-#define AT91C_US_RXDIS			((unsigned int) 0x1 <<  5)	/* US Receiver Disable */
-#define AT91C_US_TXEN			((unsigned int) 0x1 <<  6)	/* US Transmitter Enable */
-#define AT91C_US_TXDIS			((unsigned int) 0x1 <<  7)	/* US Transmitter Disable */
-#define AT91C_US_RSTSTA			((unsigned int) 0x1 <<  8)	/* US Reset Status Bits */
-
-#define AT91C_US_USMODE_NORMAL	((unsigned int) 0x0)		/* USAR) Normal */
-#define AT91C_US_USMODE_RS485	((unsigned int) 0x1)		/* USAR) RS485 */
-#define AT91C_US_USMODE_HWHSH	((unsigned int) 0x2)		/* USAR) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM	((unsigned int) 0x3)		/* USAR) Modem */
-#define AT91C_US_USMODE_ISO7816_0	((unsigned int) 0x4)	/* USAR) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1	((unsigned int) 0x6)	/* USAR) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA	((unsigned int) 0x8)		/* USAR) IrDA */
-#define AT91C_US_USMODE_SWHSH	((unsigned int) 0xC)		/* USAR) Software Handshaking */
-
-#define AT91C_US_CLKS_CLOCK		((unsigned int) 0x0 <<  4)	/* USAR) Clock */
-#define AT91C_US_CLKS_FDIV1		((unsigned int) 0x1 <<  4)	/* USAR) fdiv1 */
-#define AT91C_US_CLKS_SLOW		((unsigned int) 0x2 <<  4)	/* USAR) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT		((unsigned int) 0x3 <<  4)	/* USAR) External (SCK) */
-
-#define AT91C_US_CHRL_5_BITS	((unsigned int) 0x0 <<  6)	/* USAR) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS	((unsigned int) 0x1 <<  6)	/* USAR) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS	((unsigned int) 0x2 <<  6)	/* USAR) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6)	/* USAR) Character Length: 8 bits */
-
-#define AT91C_US_PAR_EVEN		((unsigned int) 0x0 <<  9)	/* DBGU Even Parity */
-#define AT91C_US_PAR_ODD		((unsigned int) 0x1 <<  9)	/* DBGU Odd Parity */
-#define AT91C_US_PAR_SPACE		((unsigned int) 0x2 <<  9)	/* DBGU Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK		((unsigned int) 0x3 <<  9)	/* DBGU Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE		((unsigned int) 0x4 <<  9)	/* DBGU No Parity */
-#define AT91C_US_PAR_MULTI_DROP	((unsigned int) 0x6 <<  9)	/* DBGU Multi-drop mode */
-
-#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12)	/* USART 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT	((unsigned int) 0x1 << 12)	/* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT	((unsigned int) 0x2 << 12)	/* USART 2 stop bits */
-
-#define MCK		48054857
-#define BR    	115200			/* Baud Rate */
-#define BRD  	(MCK/16/BR)		/* Baud Rate Divisor */
-
-void rt_hw_board_led_on(void);
-void rt_hw_board_led_off(void);
-void rt_hw_board_init(void);
-void rt_hw_led_flash(void);
-
-#endif
diff --git a/bsp/sam7s/project.Opt b/bsp/sam7s/project.Opt
deleted file mode 100644
index 0b834b0371..0000000000
--- a/bsp/sam7s/project.Opt
+++ /dev/null
@@ -1,76 +0,0 @@
-### uVision2 Project, (C) Keil Software
-### Do not modify !
-
- cExt (*.c)
- aExt (*.s*; *.src; *.a*)
- oExt (*.obj)
- lExt (*.lib)
- tExt (*.txt; *.h; *.inc)
- pExt (*.plm)
- CppX (*.cpp)
- DaveTm { 0,0,0,0,0,0,0,0 }
-
-Target (RT-Thread/AT91SAM7S), 0x0004 // Tools: 'ARM-ADS'
-GRPOPT 1,(Startup),1,0,0
-GRPOPT 2,(Kernel),0,0,0
-GRPOPT 3,(AT91SAM7S),1,0,0
-GRPOPT 4,(finsh),0,0,0
-
-OPTFFF 1,1,1,0,0,0,0,0,<.\application.c><application.c> 
-OPTFFF 1,2,1,0,0,0,0,0,<.\board.c><board.c> 
-OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c><startup.c> 
-OPTFFF 1,4,5,436207616,0,0,0,0,<.\rtconfig.h><rtconfig.h> 
-OPTFFF 2,5,1,0,0,0,0,0,<..\..\src\clock.c><clock.c> 
-OPTFFF 2,6,1,167772160,0,0,0,0,<..\..\src\idle.c><idle.c> 
-OPTFFF 2,7,1,436207616,0,0,0,0,<..\..\src\ipc.c><ipc.c> 
-OPTFFF 2,8,1,0,0,0,0,0,<..\..\src\irq.c><irq.c> 
-OPTFFF 2,9,1,385875968,0,0,0,0,<..\..\src\kservice.c><kservice.c> 
-OPTFFF 2,10,1,0,0,0,0,0,<..\..\src\mem.c><mem.c> 
-OPTFFF 2,11,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c> 
-OPTFFF 2,12,1,0,0,0,0,0,<..\..\src\object.c><object.c> 
-OPTFFF 2,13,1,0,0,0,0,0,<..\..\src\timer.c><timer.c> 
-OPTFFF 2,14,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c> 
-OPTFFF 2,15,1,0,0,0,0,0,<..\..\src\slab.c><slab.c> 
-OPTFFF 2,16,1,0,0,0,0,0,<..\..\src\thread.c><thread.c> 
-OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\device.c><device.c> 
-OPTFFF 3,18,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\cpu.c><cpu.c> 
-OPTFFF 3,19,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\interrupt.c><interrupt.c> 
-OPTFFF 3,20,1,436207616,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\serial.c><serial.c> 
-OPTFFF 3,21,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\stack.c><stack.c> 
-OPTFFF 3,22,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\trap.c><trap.c> 
-OPTFFF 3,23,2,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\context_rvds.S><context_rvds.S> 
-OPTFFF 3,24,2,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\start_rvds.S><start_rvds.S> 
-OPTFFF 4,25,1,0,0,0,0,0,<..\..\components\finsh\cmd.c><cmd.c> 
-OPTFFF 4,26,1,0,0,0,0,0,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c> 
-OPTFFF 4,27,1,0,0,0,0,0,<..\..\components\finsh\finsh_error.c><finsh_error.c> 
-OPTFFF 4,28,1,0,0,0,0,0,<..\..\components\finsh\finsh_heap.c><finsh_heap.c> 
-OPTFFF 4,29,1,0,0,0,0,0,<..\..\components\finsh\finsh_init.c><finsh_init.c> 
-OPTFFF 4,30,1,0,0,0,0,0,<..\..\components\finsh\finsh_node.c><finsh_node.c> 
-OPTFFF 4,31,1,0,0,0,0,0,<..\..\components\finsh\finsh_ops.c><finsh_ops.c> 
-OPTFFF 4,32,1,0,0,0,0,0,<..\..\components\finsh\finsh_parser.c><finsh_parser.c> 
-OPTFFF 4,33,1,0,0,0,0,0,<..\..\components\finsh\finsh_token.c><finsh_token.c> 
-OPTFFF 4,34,1,0,0,0,0,0,<..\..\components\finsh\finsh_var.c><finsh_var.c> 
-OPTFFF 4,35,1,0,0,0,0,0,<..\..\components\finsh\finsh_vm.c><finsh_vm.c> 
-OPTFFF 4,36,1,0,0,0,0,0,<..\..\components\finsh\shell.c><shell.c> 
-OPTFFF 4,37,1,0,0,0,0,0,<..\..\components\finsh\symbol.c><symbol.c> 
-
-
-TARGOPT 1, (RT-Thread/AT91SAM7S)
- ADSCLK=20000000
-  OPTTT 0,1,1,0
-  OPTHX 1,65535,0,0,0
-  OPTLX 79,66,8,<.\objs\>
-  OPTOX 16
-  OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
-  OPTXL 1,1,1,1,1,1,1,0,0
-  OPTFL 1,0,1
-  OPTAX 0
-  OPTDL (SARM.DLL)(-cAT91SAM7S)(DARMATS.DLL)(-p91SAM7S64)(SARM.DLL)()(TARMATS.DLL)(-p91SAM7S64)
-  OPTDBG 8189,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
-  OPTKEY 0,(DLGDARM)((117=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(130=150,119,741,704,0)(131=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(3010=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(3006=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0))
-  OPTKEY 0,(ARMDBGFLAGS)(-T5F)
-  OPTDF 0x90
-  OPTLE <>
-  OPTLC <>
-EndOpt
-
diff --git a/bsp/sam7s/project.Uv2 b/bsp/sam7s/project.Uv2
deleted file mode 100644
index 0dda5af97a..0000000000
--- a/bsp/sam7s/project.Uv2
+++ /dev/null
@@ -1,139 +0,0 @@
-### uVision2 Project, (C) Keil Software
-### Do not modify !
-
-Target (RT-Thread/AT91SAM7S), 0x0004 // Tools: 'ARM-ADS'
-
-Group (Startup)
-Group (Kernel)
-Group (AT91SAM7S)
-Group (finsh)
-
-File 1,1,<.\application.c><application.c>
-File 1,1,<.\board.c><board.c>
-File 1,1,<.\startup.c><startup.c>
-File 1,5,<.\rtconfig.h><rtconfig.h>
-File 2,1,<..\..\src\clock.c><clock.c>
-File 2,1,<..\..\src\idle.c><idle.c>
-File 2,1,<..\..\src\ipc.c><ipc.c>
-File 2,1,<..\..\src\irq.c><irq.c>
-File 2,1,<..\..\src\kservice.c><kservice.c>
-File 2,1,<..\..\src\mem.c><mem.c>
-File 2,1,<..\..\src\mempool.c><mempool.c>
-File 2,1,<..\..\src\object.c><object.c>
-File 2,1,<..\..\src\timer.c><timer.c>
-File 2,1,<..\..\src\scheduler.c><scheduler.c>
-File 2,1,<..\..\src\slab.c><slab.c>
-File 2,1,<..\..\src\thread.c><thread.c>
-File 2,1,<..\..\src\device.c><device.c>
-File 3,1,<..\..\libcpu\arm\AT91SAM7S\cpu.c><cpu.c>
-File 3,1,<..\..\libcpu\arm\AT91SAM7S\interrupt.c><interrupt.c>
-File 3,1,<..\..\libcpu\arm\AT91SAM7S\serial.c><serial.c>
-File 3,1,<..\..\libcpu\arm\AT91SAM7S\stack.c><stack.c>
-File 3,1,<..\..\libcpu\arm\AT91SAM7S\trap.c><trap.c>
-File 3,2,<..\..\libcpu\arm\AT91SAM7S\context_rvds.S><context_rvds.S>
-File 3,2,<..\..\libcpu\arm\AT91SAM7S\start_rvds.S><start_rvds.S>
-File 4,1,<..\..\components\finsh\cmd.c><cmd.c>
-File 4,1,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c>
-File 4,1,<..\..\components\finsh\finsh_error.c><finsh_error.c>
-File 4,1,<..\..\components\finsh\finsh_heap.c><finsh_heap.c>
-File 4,1,<..\..\components\finsh\finsh_init.c><finsh_init.c>
-File 4,1,<..\..\components\finsh\finsh_node.c><finsh_node.c>
-File 4,1,<..\..\components\finsh\finsh_ops.c><finsh_ops.c>
-File 4,1,<..\..\components\finsh\finsh_parser.c><finsh_parser.c>
-File 4,1,<..\..\components\finsh\finsh_token.c><finsh_token.c>
-File 4,1,<..\..\components\finsh\finsh_var.c><finsh_var.c>
-File 4,1,<..\..\components\finsh\finsh_vm.c><finsh_vm.c>
-File 4,1,<..\..\components\finsh\shell.c><shell.c>
-File 4,1,<..\..\components\finsh\symbol.c><symbol.c>
-
-
-Options 1,0,0  // Target 'RT-Thread/AT91SAM7S'
- Device (AT91SAM7S64)
- Vendor (Atmel)
- Cpu (IRAM(0x200000-0x203FFF) IROM(0x100000-0x10FFFF) CLOCK(20000000) CPUTYPE(ARM7TDMI))
- FlashUt ()
- StupF ("STARTUP\Atmel\SAM7.s" ("Atmel AT91SAM7 Startup Code"))
- FlashDR (UL2ARM(-U44045500 -O15 -S0 -C0 -D00(3F0F0F0F) -L00(4) -FO6 -FD200000 -FC800 -FN1 -FF0AT91SAM7_64 -FS0100000 -FL010000))
- DevID (3815)
- Rgf (AT91SAM7S64.H)
- Mem ()
- C ()
- A ()
- RL ()
- OH ()
- DBC_IFX ()
- DBC_CMS ()
- DBC_AMS ()
- DBC_LMS ()
- UseEnv=0
- EnvBin ()
- EnvInc ()
- EnvLib ()
- EnvReg (ÿAtmel\SAM7S\)
- OrgReg (ÿAtmel\SAM7S\)
- TgStat=16
- OutDir (.\objs\)
- OutName (rtthread-sam7s)
- GenApp=1
- GenLib=0
- GenHex=1
- Debug=1
- Browse=1
- LstDir (.\objs\)
- HexSel=1
- MG32K=0
- TGMORE=0
- RunUsr 0 0 <>
- RunUsr 1 0 <>
- BrunUsr 0 0 <>
- BrunUsr 1 0 <>
- CrunUsr 0 0 <>
- CrunUsr 1 0 <>
- SVCSID <>
- GLFLAGS=1790
- ADSFLGA { 242,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ACPUTYP (ARM7TDMI)
- RVDEV ()
- ADSTFLGA { 0,12,0,18,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 }
- OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- OCMADSIRAM { 0,0,0,32,0,0,64,0,0 }
- OCMADSIROM { 1,0,0,16,0,0,0,1,0 }
- OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
- OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,16,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,64,0,0,0,0,0,0,0,0,0,0,0 }
- RV_STAVEC ()
- ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ADSCMISC ()
- ADSCDEFN ()
- ADSCUDEF ()
- ADSCINCD (.;..\..\include;..\..\libcpu\arm\AT91SAM7S;..\..\components\finsh)
- ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ADSAMISC ()
- ADSADEFN ()
- ADSAUDEF ()
- ADSAINCD ()
- PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- IncBld=1
- AlwaysBuild=0
- GenAsm=0
- AsmAsm=0
- PublicsOnly=0
- StopCode=3
- CustArgs ()
- LibMods ()
- ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ADSLDTA (0x00100000)
- ADSLDDA (0x00200000)
- ADSLDSC ()
- ADSLDIB ()
- ADSLDIC ()
- ADSLDMC (--keep __fsym_* --keep __vsym_*)
- ADSLDIF ()
- ADSLDDW ()
-  OPTDL (SARM.DLL)(-cAT91SAM7S)(DARMATS.DLL)(-p91SAM7S64)(SARM.DLL)()(TARMATS.DLL)(-p91SAM7S64)
-  OPTDBG 8189,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
- FLASH1 { 9,0,0,0,1,0,0,0,4,16,0,0,0,0,0,0,0,0,0,0 }
- FLASH2 (Segger\JLTAgdi.dll)
- FLASH3 ("" ())
- FLASH4 ()
-EndOpt
-
diff --git a/bsp/sam7s/rtconfig.h b/bsp/sam7s/rtconfig.h
deleted file mode 100644
index 177e6402e0..0000000000
--- a/bsp/sam7s/rtconfig.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	32
-
-/* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug*/
-#define RT_DEBUG
-/* #define RT_THREAD_DEBUG */
-
-/* Using Hook*/
-#define RT_USING_HOOK
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex*/
-#define RT_USING_MUTEX
-
-/* Using Event*/
-#define RT_USING_EVENT
-
-/* Using MailBox*/
-#define RT_USING_MAILBOX
-
-/* Using Message Queue*/
-#define RT_USING_MESSAGEQUEUE
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management*/
-#define RT_USING_HEAP
-
-/* Using Small MM*/
-#define RT_USING_SMALL_MEM
-
-/* Using SLAB Allocator*/
-/* #define RT_USING_SLAB */
-
-/* SECTION: Device System */
-/* Using Device System*/
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-
-/* buffer size for UART reception*/
-#define RT_UART_RX_BUFFER_SIZE	64
-/* buffer size for UART transmission*/
-#define RT_UART_TX_BUFFER_SIZE	64
-
-/* Using UART1*/
-#define RT_USING_UART1
-/* Using UART2*/
-/* #define RT_USING_UART2 */
-
-/* SECTION: Console options */
-/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-
-/* SECTION: FinSH shell options */
-/* Using FinSH as Shell*/
-#define RT_USING_FINSH
-/* use symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-
-/* SECTION: a runtime libc library */
-/* a runtime libc library*/
-/* #define RT_USING_NEWLIB */
-
-#endif
diff --git a/bsp/sam7s/sam7s_rom.lds b/bsp/sam7s/sam7s_rom.lds
deleted file mode 100644
index c5d8cc1e4c..0000000000
--- a/bsp/sam7s/sam7s_rom.lds
+++ /dev/null
@@ -1,48 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-MEMORY
-{
-	CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
-	DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00004000
-}
-ENTRY(_start)
-SECTIONS
-{
-	.text :
-	{
-		*(.init)
-		*(.text)
-	} > CODE = 0
-
-	. = ALIGN(4);
-	.rodata :
-	{
-		*(.rodata .rodata.*)
-	} > CODE
-
-	_etext = . ;
-	PROVIDE (etext = .);
-
-	/* .data section which is used for initialized data */
-
-	.data : AT (_etext)
-	{
-		_data = . ;
-		*(.data)
-		SORT(CONSTRUCTORS)
-	} >DATA
-	. = ALIGN(4);
-
-	_edata = . ;
-	PROVIDE (edata = .);
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss :
-	{
-		*(.bss)
-	} > DATA
-	__bss_end = .;
-
-	_end = .;
-}
diff --git a/bsp/sam7s/startup.c b/bsp/sam7s/startup.c
deleted file mode 100644
index 09264ca468..0000000000
--- a/bsp/sam7s/startup.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-31     Bernard      first implementation
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <AT91SAM7S.h>
-#include "board.h"
-
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-extern void finsh_system_init(void);
-#endif
-
-/**
- * @addtogroup sam7s
- */
-
-/*@{*/
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#endif
-
-#ifdef __GNUC__
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-#endif
-
-extern void rt_hw_interrupt_init(void);
-extern int  rt_application_init(void);
-#ifdef RT_USING_DEVICE
-extern rt_err_t rt_hw_serial_init(void);
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-
-	/* init board */
-	rt_hw_board_init();
-	
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-#ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
-#elif __ICCARM__
-    rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
-#else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
-#endif
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_HOOK /* if the hook is used */
-	/* set idle thread hook */
-	rt_thread_idle_sethook(rt_hw_led_flash);
-#endif
-
-#ifdef RT_USING_DEVICE
-	/* init hardware serial device */
-	rt_hw_serial_init();
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart1");
-#endif
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main (void)
-{
-	/* invoke rtthread_startup */
-	rtthread_startup();
-	
-	return 0;
-}
-
-/*@}*/

From f8d2f880c31fad452e0416cd40ef22e075d59ee1 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 10:23:41 +0800
Subject: [PATCH 31/86] [bsp] Remove NUC140 porting

---
 bsp/nuc140/CMSIS/CM0/NUC1xx.h                 | 2029 ----------------
 bsp/nuc140/CMSIS/CM0/core_cm0.c               |  470 ----
 bsp/nuc140/CMSIS/CM0/core_cm0.h               |  801 -------
 .../CMSIS/CM0/startup/arm/startup_NUC1xx.s    |  381 ---
 bsp/nuc140/CMSIS/CM0/system_NUC1xx.c          |   37 -
 bsp/nuc140/CMSIS/CM0/system_NUC1xx.h          |   39 -
 bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm | 1204 ----------
 bsp/nuc140/application.c                      |   26 -
 bsp/nuc140/board.c                            |   65 -
 bsp/nuc140/board.h                            |   20 -
 bsp/nuc140/project.uvopt                      | 2096 -----------------
 bsp/nuc140/project.uvproj                     |  609 -----
 bsp/nuc140/rtconfig.h                         |   74 -
 bsp/nuc140/startup.c                          |  111 -
 bsp/nuc140/uart.c                             |  226 --
 bsp/nuc140/uart.h                             |    6 -
 16 files changed, 8194 deletions(-)
 delete mode 100644 bsp/nuc140/CMSIS/CM0/NUC1xx.h
 delete mode 100644 bsp/nuc140/CMSIS/CM0/core_cm0.c
 delete mode 100644 bsp/nuc140/CMSIS/CM0/core_cm0.h
 delete mode 100644 bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s
 delete mode 100644 bsp/nuc140/CMSIS/CM0/system_NUC1xx.c
 delete mode 100644 bsp/nuc140/CMSIS/CM0/system_NUC1xx.h
 delete mode 100644 bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm
 delete mode 100644 bsp/nuc140/application.c
 delete mode 100644 bsp/nuc140/board.c
 delete mode 100644 bsp/nuc140/board.h
 delete mode 100644 bsp/nuc140/project.uvopt
 delete mode 100644 bsp/nuc140/project.uvproj
 delete mode 100644 bsp/nuc140/rtconfig.h
 delete mode 100644 bsp/nuc140/startup.c
 delete mode 100644 bsp/nuc140/uart.c
 delete mode 100644 bsp/nuc140/uart.h

diff --git a/bsp/nuc140/CMSIS/CM0/NUC1xx.h b/bsp/nuc140/CMSIS/CM0/NUC1xx.h
deleted file mode 100644
index 18996d9250..0000000000
--- a/bsp/nuc140/CMSIS/CM0/NUC1xx.h
+++ /dev/null
@@ -1,2029 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------*/
-/*                                                                                                         */
-/* Copyright (c) Nuvoton Technology Corp. All rights reserved.                                             */
-/*                                                                                                         */
-/*---------------------------------------------------------------------------------------------------------*/
-
-#ifndef __NUC1xx_H__
-#define __NUC1xx_H__
-
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
- 
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
-  HardFault_IRQn		      = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                     */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                       */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                       */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                   */
-
-/******  ARMIKMCU Swift specific Interrupt Numbers ************************************************/
-  BOD_IRQn                  = 0,
-  WDT_IRQn                  = 1,
-  EINT0_IRQn                = 2,
-  EINT1_IRQn                = 3,
-  GPAB_IRQn                 = 4,
-  GPCDE_IRQn                = 5,
-  PWMA_IRQn                 = 6,
-  PWMB_IRQn                 = 7,
-  TMR0_IRQn                 = 8,
-  TMR1_IRQn                 = 9,
-  TMR2_IRQn                 = 10,
-  TMR3_IRQn                 = 11,
-  UART0_IRQn                = 12,
-  UART1_IRQn                = 13,
-  SPI0_IRQn                 = 14,
-  SPI1_IRQn                 = 15,
-  SPI2_IRQn                 = 16,
-  SPI3_IRQn                 = 17,
-  I2C0_IRQn                 = 18,
-  I2C1_IRQn                 = 19,
-  CAN0_IRQn                 = 20,
-  CAN1_IRQn                 = 21,
-  SD_IRQn                   = 22,
-  USBD_IRQn                 = 23,
-  PS2_IRQn                  = 24,
-  ACMP_IRQn                 = 25,
-  PDMA_IRQn                 = 26,
-  I2S_IRQn                  = 27,
-  PWRWU_IRQn                = 28,
-  ADC_IRQn                  = 29,
-  DAC_IRQn                  = 30,
-  RTC_IRQn                  = 31
-         
-                                        /*!< maximum of 32 Interrupts are possible                */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0 Processor and Core Peripherals */
-#define __MPU_PRESENT           0       /*!< armikcmu does not provide a MPU present or not       */
-#define __NVIC_PRIO_BITS        2       /*!< armikcmu Supports 2 Bits for the Priority Levels     */
-#define __Vendor_SysTickConfig  0       /*!< Set to 1 if different SysTick Config is used         */
-
-
-#include "core_cm0.h"                   /* Cortex-M0 processor and core peripherals               */
-#include "system_NUC1xx.h"              /* NUC1xx System                                          */
-// #include "System\SysInfra.h"    
-
-
-/**
- * Initialize the system clock
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system
- *         Initialize the PLL and update the SystemFrequency variable
- */
-extern void SystemInit (void);
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-/*--------------------- General Purpose Input and Ouptut ---------------------*/
-typedef struct
-{
-    __IO uint32_t PMD0:2;
-    __IO uint32_t PMD1:2;
-    __IO uint32_t PMD2:2;
-    __IO uint32_t PMD3:2;
-    __IO uint32_t PMD4:2;
-    __IO uint32_t PMD5:2;
-    __IO uint32_t PMD6:2;
-    __IO uint32_t PMD7:2;
-    __IO uint32_t PMD8:2;
-    __IO uint32_t PMD9:2;
-    __IO uint32_t PMD10:2;
-    __IO uint32_t PMD11:2;
-    __IO uint32_t PMD12:2;
-    __IO uint32_t PMD13:2;
-    __IO uint32_t PMD14:2;
-    __IO uint32_t PMD15:2;
-} GPIO_PMD_T;
-
-typedef __IO uint32_t GPIO_SCH_T;
-
-typedef __IO uint32_t GPIO_DOUT_T;
-
-typedef __IO uint32_t GPIO_DMASK_T;
-
-typedef __IO uint32_t GPIO_PIN_T;
-
-typedef __IO uint32_t GPIO_DBEN_T;
-
-typedef __IO uint32_t GPIO_IMD_T;
-
-typedef __IO uint32_t GPIO_IEN_T;
-
-typedef __IO uint32_t GPIO_ISRC_T;
-
-typedef struct
-{
-    __IO uint32_t  DBCLKSEL:4;
-    __IO uint32_t  DBCLKSRC:1;
-    __IO uint32_t  ICLK_ON:1;
-    __I  uint32_t  RESERVE:26;    
-} GPIO_DBNCECON_T;
-
-typedef struct
-{
-    GPIO_PMD_T      PMD;
-    GPIO_SCH_T      SCH;
-    GPIO_DOUT_T     DOUT;
-    GPIO_DMASK_T    DMASK;
-    GPIO_PIN_T      PIN;
-    GPIO_DBEN_T     DBEN;
-    GPIO_IMD_T      IMD;
-    GPIO_IEN_T      IEN;
-    GPIO_ISRC_T     ISRC;
-    
-} GPIO_T;
-
-
-/*------------------------- UART Interface Controller ------------------------*/
-
-typedef __IO uint32_t UART_DATA_T;
-
-
-typedef struct
-{
-    __IO uint32_t  RDA_IEN:1;
-    __IO uint32_t  THRE_IEN:1;
-    __IO uint32_t  RLS_IEN:1;
-    __IO uint32_t  MS_IEN:1;
-    __IO uint32_t  RTO_IEN:1;	  
-    __IO uint32_t  BUF_ERR_IEN:1;
-    __IO uint32_t  WAKE_IEN:1;
-    __I  uint32_t  RESERVE0:4;
-    __IO uint32_t  TOC_EN:1;      /* Time-out counter enable */
-    __IO uint32_t  AUTO_RTS_EN:1;
-    __IO uint32_t  AUTO_CTS_EN:1;
-    __IO uint32_t  DMA_TX_EN:1;
-    __IO uint32_t  DMA_RX_EN:1;
-    __I  uint32_t  RESERVE1:15;    
-    __IO uint32_t  nDEBUGACK_EN:1;
-} UART_IER_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  RFR:1;
-    __IO uint32_t  TFR:1;
-    __I  uint32_t  RESERVE1:1;
-    __IO uint32_t  RFITL:4;             /* Rx FIFO Interrupt Trigger Level */
-    __I  uint32_t  RESERVE2:8;
-    __IO uint32_t  RTS_TRIG_LEVEL:4;
-    __I  uint32_t  RESERVE3:12;
-} UART_FCR_T;
-
-typedef struct
-{
-    __IO uint32_t  WLS:2;               /* Word length select */
-    __IO uint32_t  NSB:1;               /* Number of STOP bit */
-    __IO uint32_t  PBE:1;               /* Parity bit enable  */
-    __IO uint32_t  EPE:1;               /* Even parity enable */
-    __IO uint32_t  SPE:1;               /* Stick parity enable*/
-    __IO uint32_t  BCB:1;               /* Break control bit  */
-    __I  uint32_t  RESERVE:25;
-} UART_LCR_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  RTS_INV:1;
-    __I  uint32_t  RESERVE1:2;
-    __IO uint32_t  LBME:1;
-    __I  uint32_t  RESERVE2:4;
-    __IO uint32_t  RTS_ACT_LEVEL:1;
-    __I  uint32_t  RESERVE3:3;
-    __I  uint32_t  RTS:1;               /* RTS status */
-    __I  uint32_t  RESERVE4:18;
-} UART_MCR_T;
-
-typedef struct
-{
-    __IO uint32_t  DCTS:1;
-    __I  uint32_t  RESERVE0:3;
-    __I  uint32_t  CTS:1;               /* CTS status */
-    __I  uint32_t  RESERVE1:3;
-    __IO uint32_t  CTS_ACT_LEVEL:1;
-    __I  uint32_t  RESERVE2:23;
-} UART_MSR_T;
-
-typedef struct
-{
-    __IO uint32_t  RX_OVERFLOW:1;
-    __I  uint32_t  RESERVE0:3;
-    __IO uint32_t  PEI:1;
-    __IO uint32_t  FEI:1;
-    __IO uint32_t  BII:1;
-    __I  uint32_t  RESERVE1:1;
-    __I  uint32_t  RX_POINTER:6;
-    __I  uint32_t  RX_EMPTY:1;
-    __I  uint32_t  RX_FULL:1;
-    __I  uint32_t  TX_POINTER:6;
-    __I  uint32_t  TX_EMPTY:1;
-    __I  uint32_t  TX_FULL:1;
-    __IO uint32_t  TX_OVERFLOW:1;
-    __I  uint32_t  RESERVE2:3;
-    __I  uint32_t  TE:1;                /* Transmitter empty flag */
-    __I  uint32_t  RESERVE3:3;
-} UART_FSR_T;
-
-typedef struct
-{
-    __IO uint32_t  RDA_IF:1;
-    __IO uint32_t  THRE_IF:1;
-    __IO uint32_t  RLS_IF:1;
-    __IO uint32_t  MODEM_IF:1;
-    __IO uint32_t  TOUT_IF:1;
-    __IO uint32_t  BUF_ERR_IF:1;
-    __IO uint32_t  WAKE_IF:1;
-    __IO uint32_t  SW_TX:1;
-    __IO uint32_t  RDA_INT:1;
-    __IO uint32_t  THRE_INT:1;
-    __IO uint32_t  RLS_INT:1;
-    __IO uint32_t  MODEM_INT:1;
-    __IO uint32_t  TOUT_INT:1;
-    __IO uint32_t  BUF_ERR_INT:1;
-    __IO uint32_t  WAKE_INT:1;
-    __IO uint32_t  SW_RX:1;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  HW_RLS_IF:1;
-    __IO uint32_t  HW_MODEM_IF:1;
-    __IO uint32_t  HW_TOUT_IF:1;
-    __IO uint32_t  HW_BUF_ERR_IF:1;
-    __IO uint32_t  HW_WAKE_IF:1;
-    __IO uint32_t  EDMA_TX:1;
-    __I  uint32_t  RESERVE1:2;
-    __IO uint32_t  HW_RLS_INT:1;
-    __IO uint32_t  HW_MODEM_INT:1;
-    __IO uint32_t  HW_TOUT_INT:1;
-    __IO uint32_t  HW_BUF_ERR_INT:1;
-    __IO uint32_t  HW_WAKE_INT:1;
-    __IO uint32_t  EDMA_RX:1;
-} UART_ISR_T;
-
-typedef __IO uint32_t UART_TOR_T;
-
-typedef struct
-{
-    __IO uint32_t  DIV:16;
-    __I  uint32_t  RESERVE0:8;
-    __IO uint32_t  DIVX:4;
-    __IO uint32_t  DIVX1:1;            
-    __IO uint32_t  DIVX_EN:1;            
-    __I  uint32_t  RESERVE1:2;
-} UART_BAUD_T;
-
-typedef struct
-{
-    __IO uint32_t  IrDA_EN:1;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  RX_EN:1;
-    __IO uint32_t  TX_EN:1;            
-    __IO uint32_t  TX_INV_EN:1;            
-    __IO uint32_t  RX_INV_EN:1;
-    __I  uint32_t  RESERVE1:25;
-} UART_IRCR_T;
-
-typedef struct
-{
-    __IO uint32_t  LINBCNT:4;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  LINRX_EN:1;
-    __IO uint32_t  LINTX_EN:1;            
-    __I  uint32_t  RESERVE1:24;
-} UART_LINCON_T;
-
-
-
-typedef struct
-{
-    __IO uint32_t  LIN_EN:2;
-	__IO uint32_t  IrDA_EN:2;
-    __I  uint32_t  RESERVE0:32;
-
-} UART_FUNSEL_T;
-
-
-typedef struct
-{
-    UART_DATA_T     DATA;
-    UART_IER_T      IER;
-    UART_FCR_T      FCR;
-    UART_LCR_T      LCR;
-    UART_MCR_T      MCR;
-    UART_MSR_T      MSR;
-    UART_FSR_T      FSR;
-    UART_ISR_T      ISR;
-    UART_TOR_T      TOR;
-    UART_BAUD_T     BAUD;
-    UART_IRCR_T     IRCR;
-    UART_LINCON_T   LINCON;    
-	UART_FUNSEL_T   FUNSEL;    
-} UART_T;
-
-/*----------------------------- Timer Controller -----------------------------*/
-typedef struct
-{
-    __IO uint32_t  PRESCALE:8;
-    __I  uint32_t  RESERVE0:8;
-    __IO uint32_t  TDR_EN:1;
-    __I  uint32_t  RESERVE1:8;
-    __IO uint32_t  CACT:1;
-    __IO uint32_t  CRST:1;
-    __IO uint32_t  MODE:2;
-    __IO uint32_t  IE:1;
-    __IO uint32_t  CEN:1;
-    __IO uint32_t  nDBGACK_EN:1;
-} TIMER_TCSR_T;
-
-typedef __IO uint32_t TIMER_TICR_T;
-
-typedef __IO uint32_t TIMER_TDR_T;
-
-typedef struct
-{
-    __IO uint32_t  TIF:1;
-    __I  uint32_t  RESERVE:31;
-} TIMER_TISR_T;
-
-typedef struct
-{
-    TIMER_TCSR_T     TCSR;
-    TIMER_TICR_T     TICR;
-    TIMER_TISR_T     TISR;    
-    TIMER_TDR_T      TDR;
- } TIMER_T;
-
-
-/*----------------------------- WDT Controller -----------------------------*/
-typedef struct
-{
-    __IO uint32_t  WTR:1;
-	__IO uint32_t  WTRE:1;
-	__IO uint32_t  WTRF:1;
-	__IO uint32_t  WTIF:1;
-	__I  uint32_t  RESERVE:2;
-	__IO uint32_t  WTIE:1;
-	__IO uint32_t  WTE:1;
-	__IO uint32_t  WTIS:3;
-    __I  uint32_t  RESERVE1:21;
-} WDT_WTCR_T;
-
-typedef struct
-{
-    WDT_WTCR_T     WTCR;
-    
- } WDT_T;
-
-/*------------------------- SPI Interface Controller -------------------------*/
-typedef struct
-{
-    __IO uint32_t  GO_BUSY:1;
-    __IO uint32_t  RX_NEG:1;
-    __IO uint32_t  TX_NEG:1;
-    __IO uint32_t  TX_BIT_LEN:5;
-    __IO uint32_t  TX_NUM:2;
-    __IO uint32_t  LSB:1;
-    __IO uint32_t  CLKP:1;
-    __IO uint32_t  SLEEP:4;
-    __IO uint32_t  IF:1;
-    __IO uint32_t  IE:1;
-    __IO uint32_t  SLAVE:1;
-    __IO uint32_t  BYTE_SLEEP:1;
-    __IO uint32_t  BYTE_ENDIAN:1;
-    __IO uint32_t  FOURB:1;
-    __IO uint32_t  TWOB:1;
-    __IO uint32_t  VARCLK_EN:1;
-    __I  uint32_t  RESERVE:8;
-} SPI_CNTRL_T;
-
-typedef struct
-{
-    __IO uint32_t  DIVIDER:16;
-    __IO uint32_t  DIVIDER2:16;
-} SPI_DIVIDER_T;
-
-typedef struct
-{
-    __IO uint32_t  SSR:2;
-    __IO uint32_t  SS_LVL:1;
-    __IO uint32_t  ASS:1;
-    __IO uint32_t  SS_LTRIG:1;
-    __IO uint32_t  LTRIG_FLAG:1;
-    __I  uint32_t  RESERVE:26;
-} SPI_SSR_T;
-
-
-typedef __I  uint32_t   SPI_RX_T;
-typedef __O  uint32_t   SPI_TX_T;
-
-typedef struct
-{
-    __IO uint32_t  JS:1;
-    __I  uint32_t  RESERVE0:3;
-    __IO uint32_t  JS_RW:1;
-    __IO uint32_t  CS_ACT:1;
-    __IO uint32_t  DATA_RDY:1;
-    __IO uint32_t  CS_DEACT:1;
-    __IO uint32_t  READYB:1;
-    __I  uint32_t  RESERVE1:23;
-} SPI_JS_T;
-
-typedef __IO uint32_t SPI_VARCLK_T;
-
-typedef struct
-{
-    __IO uint32_t  TX_DMA_GO:1;
-    __IO uint32_t  RX_DMA_GO:1;
-    __I  uint32_t  RESERVE:30;
-} SPI_DMA_T;
-
-typedef struct
-{
-    SPI_CNTRL_T     CNTRL;
-    SPI_DIVIDER_T   DIVIDER;
-    SPI_SSR_T       SSR;
-    uint32_t        RESERVE0;
-    SPI_RX_T        RX[2];
-    uint32_t        RESERVE1;
-    uint32_t        RESERVE2;
-    SPI_TX_T        TX[2];
-    uint32_t        RESERVE3;
-    uint32_t        RESERVE4;
-    SPI_JS_T        JS;
-    SPI_VARCLK_T    VARCLK;
-    SPI_DMA_T       DMA;
-} SPI_T;
-
-/*------------------------------ I2C Controller ------------------------------*/
-typedef struct
-{
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  AA:1;
-    __IO uint32_t  SI:1;
-    __IO uint32_t  STO:1;
-    __IO uint32_t  STA:1;
-    __IO uint32_t  ENSI:1;
-   	__IO uint32_t  EI:1;
-    __I  uint32_t  RESERVE1:24;
-} I2C_CON_T;
-
-typedef struct
-{
-    __IO uint32_t  GC:1;
-    __IO uint32_t  ADDR:7;
-    __I  uint32_t  RESERVE:24;
-} I2C_ADDR_T;
-
-typedef __IO uint32_t I2C_DATA_T;
-
-typedef __I  uint32_t I2C_STATUS_T;
-
-typedef __IO uint32_t I2C_CLK_T;
-
-typedef struct
-{
-    __IO uint32_t  TIF:1;
-    __IO uint32_t  DIV4:1;
-    __IO uint32_t  ENTI:1;
-    __I  uint32_t  RESERVE:29;
-} I2C_TOC_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  ADM:7;
-    __I  uint32_t  RESERVE1:24;
-} I2C_ADRM_T;
-
-typedef struct
-{
-    I2C_CON_T       CON;
-    I2C_ADDR_T      ADDR0;
-    I2C_DATA_T      DATA;
-    I2C_STATUS_T    STATUS;
-    I2C_CLK_T       CLK;
-    I2C_TOC_T       TOC;
-	I2C_ADDR_T	    ADDR1;
-	I2C_ADDR_T	    ADDR2;
-	I2C_ADDR_T	    ADDR3;
-	I2C_ADRM_T		ADRM0;
-	I2C_ADRM_T		ADRM1;
-	I2C_ADRM_T		ADRM2;
-	I2C_ADRM_T	    ADRM3;        
-} I2C_T;
-
-
-/*----------------------------- RTC Controller -------------------------------*/
-
-typedef __IO uint32_t RTC_INIR_T;
-
-typedef struct
-{
-    __IO uint32_t  AER:16;
-    __I  uint32_t  ENF:1;
-    __I  uint32_t  RESERVE1:15;
-} RTC_AER_T;
-
-typedef struct
-{
-    __IO uint32_t  FRACTION:6;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  INTEGER:4;
-    __I  uint32_t  RESERVE1:20;
-} RTC_FCR_T;
-
-typedef struct
-{
-    __IO uint32_t  SEC1:4;
-    __IO uint32_t  SEC10:3;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  MIN1:4;
-    __IO uint32_t  MIN10:3;
-    __I  uint32_t  RESERVE1:1;
-    __IO uint32_t  HR1:4;
-    __IO uint32_t  HR10:2;
-    __I  uint32_t  RESERVE2:10;
-} RTC_TLR_T;
-
-typedef struct
-{
-    __IO uint32_t  DAY1:4;
-    __IO uint32_t  DAY10:2;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  MON1:4;
-    __IO uint32_t  MON10:1;
-    __I  uint32_t  RESERVE1:3;
-    __IO uint32_t  YEAR1:4;
-    __IO uint32_t  YEAR10:4;
-    __I  uint32_t  RESERVE2:8;
-} RTC_CLR_T;
-
-typedef struct
-{
-    __IO uint32_t  HR24:1;
-    __I  uint32_t  RESERVE:31;
-} RTC_TSSR_T;
-
-typedef struct
-{
-    __IO uint32_t  DWR:3;
-    __I  uint32_t  RESERVE:29;
-} RTC_DWR_T;
-
-typedef RTC_TLR_T   RTC_TAR_T;
-typedef RTC_CLR_T   RTC_CAR_T;
-
-typedef struct
-{
-    __IO uint32_t  LIR:1;
-    __I  uint32_t  RESERVE:31;
-} RTC_LIR_T;
-
-typedef struct
-{
-    __IO uint32_t  AIER:1;
-    __IO uint32_t  TIER:1;
-    __I  uint32_t  RESERVE:30;
-} RTC_RIER_T;
-
-
-//typedef __IO uint32_t RTC_RIIR_T;
-
-typedef struct
-{
-    __IO uint32_t  AI:1;
-    __IO uint32_t  TI:1;
-    __I  uint32_t  RESERVE:30;
-} RTC_RIIR_T;
-
-typedef struct
-{
-    __IO uint32_t  TTR:3;
-    __I  uint32_t  RESERVE:30;
-} RTC_TTR_T;
-
-typedef struct
-{
-    __IO uint32_t  PTOUT:16;
-    __I  uint32_t  RESERVE0:7;
-    __IO uint32_t  PWROFF:1;
-    __I  uint32_t  RESERVE1:8;
-} RTC_PWRCON_T;
-
-typedef struct
-{
-    RTC_INIR_T  INIR;
-    RTC_AER_T   AER;
-    RTC_FCR_T   FCR;
-    RTC_TLR_T   TLR;
-    RTC_CLR_T   CLR;
-    RTC_TSSR_T  TSSR;
-    RTC_DWR_T   DWR;
-    RTC_TAR_T   TAR;
-    RTC_CAR_T   CAR;
-    RTC_LIR_T   LIR;
-    RTC_RIER_T  RIER;
-    RTC_RIIR_T  RIIR;
-    RTC_TTR_T   TTR;
-    RTC_PWRCON_T   PWRCON;
-} RTC_T;
-
-
-/*----------------------------- ADC Controller -------------------------------*/
-typedef struct
-{
-    __IO uint32_t  RSLT:16;
-    __IO uint32_t  OVERRUN:1;
-    __IO uint32_t  VALID:1;
-    __I  uint32_t  RESERVE1:14;
-} ADC_ADDR_T;
-
-typedef struct
-{
-    __IO uint32_t  ADEN:1;
-    __IO uint32_t  ADIE:1;
-    __IO uint32_t  ADMD:2;
-    __IO uint32_t  TRGS:2;
-    __IO uint32_t  TRGCOND:2;
-    __IO uint32_t  TRGEN:1;
-    __IO uint32_t  PTEN:1;
-    __IO uint32_t  DIFF:1;
-    __IO uint32_t  ADST:1;
-    __I  uint32_t  RESERVE0:4;
-    __IO uint32_t  ADCLKDIV:7;
-    __I  uint32_t  RESERVE1:9;
-} ADC_ADCR_T;
-
-
-
-typedef struct
-{
-    __IO uint32_t  CHEN:8;
-    __IO uint32_t  PRESEL:2;
-    __I  uint32_t  RESERVE:22;
-} ADC_ADCHER_T;
-
-
-typedef struct
-{
-    __IO uint32_t  CMPEN:1;
-    __IO uint32_t  CMPIE:1;
-    __IO uint32_t  CMPCOND:1;
-    __IO uint32_t  CMPCH:3;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  CMPMATCNT:4;
-    __I  uint32_t  RESERVE1:4;
-    __IO uint32_t  CMPD:12;
-    __I  uint32_t  RESERVE2:4;
-} ADC_ADCMPR_T;
-
-typedef struct
-{
-    __IO uint32_t  ADF:1;
-    __IO uint32_t  CMPF0:1;
-    __IO uint32_t  CMPF1:1;
-    __IO uint32_t  BUSY:1;
-    __IO uint32_t  CHANNEL:3;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  VALID:8;
-    __IO uint32_t  OVERRUN:8;
-    __I  uint32_t  RESERVE1:8;
-} ADC_ADSR_T;
-
-typedef struct
-{
-    __IO uint32_t  CALEN:1;
-    __IO uint32_t  CALDONE:1;
-    __I  uint32_t  RESERVE:30;
-} ADC_ADCALR_T;
-
-typedef struct
-{
-    ADC_ADDR_T      ADDR[8];
-    ADC_ADCR_T      ADCR;
-    ADC_ADCHER_T    ADCHER;
-    ADC_ADCMPR_T    ADCMPR[2];
-    ADC_ADSR_T      ADSR;
-    ADC_ADCALR_T    ADCALR;
-
-} ADC_T;
-
-/*---------------------- Analog Comparator Controller -------------------------*/
-typedef struct
-{
-    __IO uint32_t  CMPEN:1;
-    __IO uint32_t  CMPIE:1;
-    __IO uint32_t  CMP_HYSEN:1;
-    __IO uint32_t  CP:1;
-    __IO uint32_t  CN:1;
-    __IO uint32_t  COE:1;
-    __I  uint32_t  RESERVE:26;
-} ACMP_CMPCR_T;
-
-typedef struct
-{
-    __IO uint32_t  CMPF1:1;
-    __IO uint32_t  CMPF2:1;
-    __IO uint32_t  CO1:1;
-    __IO uint32_t  CO2:1;
-    __I  uint32_t  RESERVE:28;
-} ACMP_CMPSR_T;
-
-typedef struct
-{
-    ACMP_CMPCR_T CMPCR[2];
-    ACMP_CMPSR_T CMPSR;
-} ACMP_T;
-
-/*---------------------------- Clock Controller ------------------------------*/
-typedef struct
-{
-    __IO uint32_t  XTL12M_EN:1;
-    __IO uint32_t  XTL32K_EN:1;
-    __IO uint32_t  OSC22M_EN:1;
-    __IO uint32_t  OSC10K_EN:1;
-    __IO uint32_t  WU_DLY:1;
-    __IO uint32_t  WINT_EN:1;
-    __IO uint32_t  PD_WU_STS:1;
-    __IO uint32_t  PWR_DOWN:1;
-    __IO uint32_t  PD_WAIT_CPU:1;
-    __I  uint32_t  RESERVE:23;
-} SYSCLK_PWRCON_T;
-
-typedef struct
-{
-    __IO uint32_t  CPU_EN:1;
-    __IO uint32_t  PDMA_EN:1;
-    __IO uint32_t  ISP_EN:1;
-    __I  uint32_t  RESERVE:29;
-} SYSCLK_AHBCLK_T;
-
-typedef struct
-{
-    __IO uint32_t  WDG_EN:1;
-    __IO uint32_t  RTC_EN:1;
-    __IO uint32_t  TMR0_EN:1;
-    __IO uint32_t  TMR1_EN:1;
-    __IO uint32_t  TMR2_EN:1;
-    __IO uint32_t  TMR3_EN:1;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  I2C0_EN:1;
-    __IO uint32_t  I2C1_EN:1;
-    __I  uint32_t  RESERVE1:2;
-    __IO uint32_t  SPI0_EN:1;
-    __IO uint32_t  SPI1_EN:1;
-    __IO uint32_t  SPI2_EN:1;
-    __IO uint32_t  SPI3_EN:1;
-    __IO uint32_t  UART0_EN:1;
-    __IO uint32_t  UART1_EN:1;
-    __I  uint32_t  RESERVE2:2;
-    __IO uint32_t  PWM01_EN:1;
-    __IO uint32_t  PWM23_EN:1;
-    __I  uint32_t  RESERVE3:2;
-    __IO uint32_t  CAN0_EN:1;
-    __IO uint32_t  CAN1_EN:1;
-    __I  uint32_t  RESERVE4:1;
-    __IO uint32_t  USBD_EN:1;
-    __IO uint32_t  ADC_EN:1;
-    __I  uint32_t  RESERVE5:1;
-    __IO uint32_t  ACMP_EN:1;
-    __IO uint32_t  PS2_EN:1;
-} SYSCLK_APBCLK_T;
-
-typedef struct
-{
-    __IO uint32_t  HCLK_S:3;
-    __IO uint32_t  STCLK_S:3;
-    __I  uint32_t  RESERVE:26;
-} SYSCLK_CLKSEL0_T;
-
-
-typedef struct
-{
-    __IO uint32_t  WDG_S:2;
-    __IO uint32_t  ADC_S:2;
-    __I  uint32_t  RESERVE1:4;
-    __IO uint32_t  TMR0_S:3;
-    __I  uint32_t  RESERVE2:1;
-    __IO uint32_t  TMR1_S:3;
-    __I  uint32_t  RESERVE3:1;
-    __IO uint32_t  TMR2_S:3;
-    __I  uint32_t  RESERVE4:1;
-    __IO uint32_t  TMR3_S:3;
-    __I  uint32_t  RESERVE5:1;
-    __IO uint32_t  UART_S:2;
-    __IO uint32_t  CAN_S:2;
-    __IO uint32_t  PWM10_S:2;
-    __IO uint32_t  PWM32_S:2;
-} SYSCLK_CLKSEL1_T;
-
-typedef struct
-{
-    __IO uint32_t  HCLK_N:4;
-    __IO uint32_t  USB_N:4;
-    __IO uint32_t  UART_N:4;
-    __IO uint32_t  CAN_N:4;
-    __IO uint32_t  ADC_N:8;
-    __I  uint32_t  RESERVE:8;
-} SYSCLK_CLKDIV_T;
-
-typedef struct
-{
-    __IO uint32_t  FB_DV:9;
-    __IO uint32_t  IN_DV:5;
-    __IO uint32_t  OUT_DV:2;
-    __IO uint32_t  PD:1;
-    __IO uint32_t  BP:1;
-    __IO uint32_t  OE:1;
-    __IO uint32_t  PLL_SRC:1;
-    __I  uint32_t  RESERVE:12;
-} SYSCLK_PLLCON_T;
-
-typedef struct
-{    
-    __IO uint32_t  TEST_SEL:8;
-    __I  uint32_t  RESERVE:24;
-} SYSCLK_TREG_T;
-
-typedef struct
-{
-    SYSCLK_PWRCON_T    PWRCON;
-    SYSCLK_AHBCLK_T    AHBCLK;
-    SYSCLK_APBCLK_T    APBCLK;
-    uint32_t           RESERVED0;
-    SYSCLK_CLKSEL0_T   CLKSEL0;
-    SYSCLK_CLKSEL1_T   CLKSEL1;
-    SYSCLK_CLKDIV_T    CLKDIV;
-    uint32_t           RESERVED1;
-	SYSCLK_PLLCON_T    PLLCON;
-    
-} SYSCLK_T;
-
-/*---------------------------- Global Controller -----------------------------*/
-typedef __I uint32_t GCR_PDID_T;  
-
-typedef struct
-{
-    __IO uint32_t  RSTS_POR:1;
-	__IO uint32_t  RSTS_PAD:1;
-	__IO uint32_t  RSTS_WDG:1;
-	__IO uint32_t  RSTS_LVR:1;
-	__IO uint32_t  RSTS_BOD:1;
-	__IO uint32_t  RSTS_MCU:1;
-	__IO uint32_t  RSTS_PMU:1;    
-	__I  uint32_t  RESERVE:25;
-} GCR_RSTSRC_T;
-
-
-typedef struct
-{
-    __IO uint32_t  CHIP_RST:1;
-    __IO uint32_t  CPU_RST:1;
-    __IO uint32_t  PDMA_RST:1;
-    __I  uint32_t  RESERVE:29;
-} GCR_IPRSTC1_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  GPIO_RST:1;
-    __IO uint32_t  TMR0_RST:1;
-    __IO uint32_t  TMR1_RST:1;
-    __IO uint32_t  TMR2_RST:1;
-    __IO uint32_t  TMR3_RST:1;
-    __I  uint32_t  RESERVE1:2;
-    __IO uint32_t  I2C0_RST:1;
-    __IO uint32_t  I2C1_RST:1;
-    __I  uint32_t  RESERVE2:2;
-    __IO uint32_t  SPI0_RST:1;
-    __IO uint32_t  SPI1_RST:1;
-    __IO uint32_t  SPI2_RST:1;
-    __IO uint32_t  SPI3_RST:1;
-    __IO uint32_t  UART0_RST:1;
-    __IO uint32_t  UART1_RST:1;
-    __I  uint32_t  RESERVE3:2;
-    __IO uint32_t  PWM_RST:1;
-    __I  uint32_t  RESERVE4:1;
-    __IO uint32_t  ACMP_RST:1;
-    __IO uint32_t  PS2_RST:1;
-    __IO uint32_t  CAN0_RST:1;
-    __IO uint32_t  CAN1_RST:1;
-    __I  uint32_t  RESERVE5:1;
-    __IO uint32_t  USBD_RST:1;
-    __IO uint32_t  ADC_RST:1;
-    __I  uint32_t  RESERVE6:3;
-} GCR_IPRSTC2_T;
-
-typedef __IO uint32_t GCR_MISCR_T; 
-
-
-typedef struct
-{
-    __IO uint32_t  BOD_EN:1;
-    __IO uint32_t  BOD_VL:2;
-    __IO uint32_t  BOD_RSTEN:1;
-    __IO uint32_t  BOD_BYP_EN:1;
-    __IO uint32_t  BOD_LPM:1;
-    __IO uint32_t  BOD_OUT:1;
-	__IO uint32_t  LVR_EN:1;
-	__IO uint32_t  VTEMP_EN:1;
-	__IO uint32_t  LDO_BYP:1;
-    __I  uint32_t  RESERVE1:22;
-} GCR_BODCR_T;
-
-typedef __IO uint32_t GCR_PORCR_T; 
-
-
-typedef struct
-{
-    __IO uint32_t ADC0:1;
-    __IO uint32_t ADC1:1;
-    __IO uint32_t ADC2:1;
-    __IO uint32_t ADC3:1;
-    __IO uint32_t ADC4:1;
-    __IO uint32_t ADC5:1;
-    __IO uint32_t ADC6:1;
-    __IO uint32_t ADC7:1;
-    __IO uint32_t I2C0_SDA:1;
-    __IO uint32_t I2C0_SCL:1;
-    __IO uint32_t I2C1_SDA:1;
-    __IO uint32_t I2C1_SCL:1;
-    __IO uint32_t PWM0:1;
-    __IO uint32_t PWM1:1;
-    __IO uint32_t PWM2:1;
-    __IO uint32_t PWM3:1;
-    __IO uint32_t SCHMITT:16;    
-} GCR_GPAMFP_T;
-
-typedef struct
-{
-    __IO uint32_t UART0_RX:1;
-    __IO uint32_t UART0_TX:1;
-    __IO uint32_t UART0_nRTS:1;
-    __IO uint32_t UART0_nCTS:1;
-    __IO uint32_t UART1_RX:1;
-    __IO uint32_t UART1_TX:1;
-    __IO uint32_t UART1_nRTS:1;
-    __IO uint32_t UART1_nCTS:1;
-    __IO uint32_t TM0:1;
-    __IO uint32_t TM1:1;
-    __IO uint32_t TM2:1;
-    __IO uint32_t TM3:1;
-    __IO uint32_t CPO0:1;
-    __IO uint32_t CPO1:1;
-    __IO uint32_t INT0:1;
-    __IO uint32_t INT1:1;
-    __IO uint32_t SCHMITT:16;    
-} GCR_GPBMFP_T;
-
-typedef struct
-{
-    __IO uint32_t SPI0_SS0:1;
-    __IO uint32_t SPI0_CLK:1;
-    __IO uint32_t SPI0_MISO0:1;
-    __IO uint32_t SPI0_MOSI0:1;
-    __IO uint32_t SPI0_MISO1:1;
-    __IO uint32_t SPI0_MOSI1:1;
-    __IO uint32_t CPP0:1;
-    __IO uint32_t CPN0:1;
-    __IO uint32_t SPI1_SS0:1;
-    __IO uint32_t SPI1_CLK:1;
-    __IO uint32_t SPI1_MISO0:1;
-    __IO uint32_t SPI1_MOSI0:1;
-    __IO uint32_t SPI1_MISO1:1;
-    __IO uint32_t SPI1_MOSI1:1;
-    __IO uint32_t CPP1:1;
-    __IO uint32_t CPN1:1;
-    __IO uint32_t SCHMITT:16;    
-} GCR_GPCMFP_T;
-
-typedef struct
-{
-    __IO uint32_t SPI2_SS0:1;
-    __IO uint32_t SPI2_CLK:1;
-    __IO uint32_t SPI2_MISO0:1;
-    __IO uint32_t SPI2_MOSI0:1;
-    __IO uint32_t SPI2_MISO1:1;
-    __IO uint32_t SPI2_MOSI1:1;
-    __IO uint32_t CAN0_RX:1;
-    __IO uint32_t CAN0_TX:1;
-    __IO uint32_t SPI3_SS0:1;
-    __IO uint32_t SPI3_CLK:1;
-    __IO uint32_t SPI3_MISO0:1;
-    __IO uint32_t SPI3_MOSI0:1;
-    __IO uint32_t SPI3_MISO1:1;
-    __IO uint32_t SPI3_MOSI1:1;
-    __IO uint32_t CAN1_RX:1;
-    __IO uint32_t CAN1_TX:1;
-    __IO uint32_t SCHMITT:16;    
-} GCR_GPDMFP_T;
-
-
-typedef struct
-{
-    __I  uint32_t  RESERVE:16;
-    __IO uint32_t  SCHMITT:16;
-} GCR_GPEMFP_T;
-
-typedef struct
-{
-    __IO uint32_t  SPI0_SS1:1;  /* GPB10 */
-    __IO uint32_t  SPI1_SS1:1;  /* GPB9  */
-    __IO uint32_t  SPI2_SS1:1;  /* GPA7  */
-    __IO uint32_t  SPI3_SS1:1;  /* GPB14 */
-    __I  uint32_t  RESERVE:28;
-    
-} GCR_USPIMFP_T;
-
-typedef __IO uint32_t GCR_REGLOCK_T;
-typedef __IO uint32_t GCR_RCADJ_T;
-
-
-typedef struct
-{
-    __IO uint32_t  INTSRC:3;
-    __I  uint32_t  RESERVE:29;
-} GCR_INTSRC_T;
-
-typedef struct
-{
-    __IO uint32_t  NMISEL:5;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  INT_TEST:1;
-    __I  uint32_t  RESERVE1:24;
-} GCR_NMISEL_T;
-
-
-typedef __IO uint32_t GCR_MCUIRQ_T;
-
-typedef struct
-{
-    GCR_PDID_T      PDID;
-    GCR_RSTSRC_T    RSTSRC;
-    GCR_IPRSTC1_T   IPRSTC1;
-    GCR_IPRSTC2_T   IPRSTC2;
-    uint32_t        RESERVE0;
-	GCR_MISCR_T     MISCR;
-    GCR_BODCR_T     BODCR;
-    GCR_PORCR_T		PORCR;
-	uint32_t        RESERVE1[4];
-    GCR_GPAMFP_T    GPAMFP;
-    GCR_GPBMFP_T    GPBMFP;
-    GCR_GPCMFP_T    GPCMFP;
-    GCR_GPDMFP_T    GPDMFP;
-    GCR_GPEMFP_T    GPEMFP;
-    uint32_t        RESERVE2[3];
-	GCR_USPIMFP_T   USPIMFP;
-    uint32_t        RESERVE3[43];
-    GCR_REGLOCK_T   REGLOCK;
-	uint32_t        RESERVE4[3];
-	GCR_RCADJ_T		RCADJ;
-} GCR_T;
-
-
-
-typedef struct
-{
-    GCR_INTSRC_T    INTSRC;
-    GCR_NMISEL_T    NMISEL;
-    GCR_MCUIRQ_T    MCUIRQ;   
-} GCR_INT_T;
-
-/*-------------------------- FLASH Memory Controller -------------------------*/
-typedef struct
-{
-    __IO uint32_t  ISPEN:1;
-    __IO uint32_t  BS:1;
-    __I  uint32_t  RESERVE0:3;
-    __IO uint32_t  LDUEN:1;
-    __IO uint32_t  ISPFF:1;
-    __IO uint32_t  SWRST:1;
-    __IO uint32_t  PT:3;
-	__I  uint32_t  RESERVE1:1;
-	__IO uint32_t  ET:3;
-    __I  uint32_t  RESERVE2:17;
-
-} FMC_ISPCON_T;
-
-typedef __IO uint32_t FMC_ISPADR_T;
-typedef __IO uint32_t FMC_ISPDAT_T;
-
-typedef struct
-{
-    __IO uint32_t  FCTRL:4;
-    __IO uint32_t  FCEN:1;
-    __IO uint32_t  FOEN:1;
-    __I  uint32_t  RESERVE:26;
-} FMC_ISPCMD_T;
-
-typedef struct
-{
-    __IO uint32_t  ISPGO:1;
-    __I  uint32_t  RESERVE:31;
-} FMC_ISPTRG_T;
-
-typedef __I uint32_t FMC_DFBADR_T;
-
-typedef struct
-{
-    __IO uint32_t  FPSEN:1;
-    __IO uint32_t  FATS:3;
-    __I  uint32_t  RESERVE:28;
-} FMC_FATCON_T;
-
-typedef struct
-{
-    FMC_ISPCON_T ISPCON;
-    FMC_ISPADR_T ISPADR;
-    FMC_ISPDAT_T ISPDAT;
-    FMC_ISPCMD_T ISPCMD;
-    FMC_ISPTRG_T ISPTRG;
-    FMC_DFBADR_T DFBADR;
-    FMC_FATCON_T FATCON;
-} FMC_T;
-
-
-/*------------------------ PS2 Device Interface Controller -------------------*/
-typedef struct
-{
-    __IO uint32_t  PS2EN:1;
-    __IO uint32_t  TXINTEN:1;
-    __IO uint32_t  RXINTEN:1;
-    __IO uint32_t  TXFIFO_DEPTH:4;
-    __IO uint32_t  ACK:1;
-    __IO uint32_t  CLRFIFO:1;
-    __IO uint32_t  OVERRIDE:1;
-    __IO uint32_t  FPS2CLK:1;
-    __IO uint32_t  FPS2DAT:1;
-    __I  uint32_t  RESERVE:20;
-} PS2_CON_T;
-
-typedef __IO uint32_t PS2_DATA_T;
-
-typedef struct
-{
-    __IO uint32_t  PS2CLK:1;
-    __IO uint32_t  PS2DATA:1;
-    __IO uint32_t  FRAMERR:1;
-    __IO uint32_t  RXPARTY:1;
-    __IO uint32_t  RXBUSY:1;
-    __IO uint32_t  TXBUSY:1;
-    __IO uint32_t  RXOVF:1;
-    __IO uint32_t  TXEMPTY:1;
-    __IO uint32_t  BYTEIDX:4;
-    __I  uint32_t  RESERVE:20;
-} PS2_STATUS_T;
-
-typedef __IO uint32_t PS2_INTID_T;
-
-typedef struct
-{
-    PS2_CON_T       PS2CON;
-    PS2_DATA_T      TXDATA[4];
-    PS2_DATA_T      RXDATA;
-    PS2_STATUS_T    STATUS;
-    PS2_INTID_T     INTID;
-} PS2_T;
-
-/*---------------------------- CAN Bus Controller ----------------------------*/
-typedef struct
-{
-    __IO uint32_t  RSTM:1;
-	__IO uint32_t  LOM:1;
-    __I  uint32_t  RESERVE:30;
-    
-} CAN_OPMODE_T;
-
-typedef struct
-{
-    __IO uint32_t  TR:1;
-	__IO uint32_t  ABRT:1;
-    __I  uint32_t  RESERVE2:3;
-	__IO uint32_t  OVERFLOAD_EN:1;
-	__IO uint32_t  WAKEUP_EN:1;
-    __IO uint32_t  CAN_EN:1;
-    __I  uint32_t  RESERVE:24;
-} CAN_CMD_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:3;
-    __IO uint32_t  TCS:1;
-    __IO uint32_t  RS:1;
-    __IO uint32_t  TS:1;
-    __IO uint32_t  BS:1;
-    __IO uint32_t  BS2:1;
-    __IO uint32_t  EAS:1;
-    __IO uint32_t  EPS:1;
-    __I  uint32_t  RESERVE1:22;
-} CAN_BSR_T;
-
-typedef struct
-{
-    __IO uint32_t  RI:1;
-    __IO uint32_t  TI:1;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  WUI:1;
-    __I  uint32_t  RESERVE1:1;
-    __IO uint32_t  ALI:1;
-    __IO uint32_t  BEI:1;
-    __I  uint32_t  RESERVE2:24;
-} CAN_INTR_T;
-
-typedef struct
-{
-    __IO uint32_t  RIE:1;
-    __IO uint32_t  TIE:1;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  WUIE:1;
-    __I  uint32_t  RESERVE1:1;
-    __IO uint32_t  ALIE:1;
-    __IO uint32_t  BEIE:1;
-    __I  uint32_t  RESERVE2:24;
-} CAN_INTEN_T;
-
-typedef struct
-{
-    __IO uint32_t  BRP:4;
-    __IO uint32_t  SJW:2;
-    __IO uint32_t  TSEG1:5;
-    __IO uint32_t  TSEG2:4;
-    __IO uint32_t  SAMP:1;
-    __I  uint32_t  RESERVE2:16;
-} CAN_BTIMR_T;
-
-typedef struct
-{
-    __IO uint32_t  BIT_ERR:4;
-    __IO uint32_t  ACK_ERR:2;
-    __IO uint32_t  CRC_ERR:5;
-    __IO uint32_t  FORM_ERR:4;
-    __IO uint32_t  STUFF_ERR:1;
-    __I  uint32_t  RESERVE:16;
-} CAN_ERRCR_T;
-
-typedef struct
-{
-    __IO uint32_t  RECNT:8;
-    __I  uint32_t  RESERVE:24;
-} CAN_RECNTR_T;
-
-typedef struct
-{
-    __IO uint32_t  TECNT:8;
-    __I  uint32_t  RESERVE:24;
-} CAN_TECNTR_T;
-
-typedef struct
-{
-    __IO uint32_t  TXDLC:6;
-    __IO uint32_t  TXRTR:1;
-    __IO uint32_t  TXFF:1;
-    __I  uint32_t  RESERVE:24;
-} CAN_TXFINFO_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE:3;
-    __IO uint32_t  TXID:29;
-} CAN_TXID_T;
-
-typedef __IO uint32_t CAN_TXDATA_T;
-
-typedef struct
-{
-    __IO uint32_t  RXDLC:4;
-    __I  uint32_t  RESERVE0:2;
-    __IO uint32_t  RXRTR:1;
-    __IO uint32_t  RXIDE:1;
-    __I  uint32_t  RESERVE1:24;
-} CAN_RXFINFO_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE:3;
-    __IO uint32_t  RXID:29;
-} CAN_RXID_T;
-
-typedef __IO uint32_t CAN_RXDATA_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE:3;
-    __IO uint32_t  ACR:29;
-} CAN_ACR_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE:3;
-    __IO uint32_t  AMR:29;
-} CAN_AMR_T;
-
-
-typedef struct
-{
-    __I  uint32_t  RESERVE:32;
-} CAN_RESERVE_T;
-
-typedef struct
-{
-    CAN_OPMODE_T    OPMODE;
-    CAN_CMD_T       CMD;
-	CAN_BSR_T       BSR;    
-	CAN_INTR_T      INTR;
-
-    CAN_INTEN_T     INTEN;
-    CAN_BTIMR_T     BTIMR;
-	CAN_RESERVE_T	PROTECT[2];
-
-    CAN_ERRCR_T     ERRCR;
-	CAN_RESERVE_T	PROTECT1;
-    CAN_RECNTR_T    RECNTR;
-    CAN_TECNTR_T    TECNTR;
-
-    CAN_TXFINFO_T   TXFINFO;
-    CAN_TXID_T      TXID;
-    CAN_TXDATA_T    TXDATA[2];
-
-    CAN_RXFINFO_T   RXFINFO;
-    CAN_RXID_T      RXID;
-    CAN_RXDATA_T    RX_DATA[2];
-    CAN_ACR_T       ACR;
-    CAN_AMR_T       AMR;    
-} CAN_T;
-
-
-/*--------------------------- USB Device Controller --------------------------*/
-typedef struct
-{
-    __IO uint32_t  BUS:1;
-    __IO uint32_t  USB:1;
-    __IO uint32_t  FLD:1;
-    __IO uint32_t  WAKEUP:1;
-    __I  uint32_t  RESERVE0:4;
-    __IO uint32_t  WAKEUP_EN:1;
-    __I  uint32_t  RESERVE1:6;
-    __IO uint32_t  INNAK_EN:1;
-    __I  uint32_t  RESERVE2:16;
-} USBD_IEF_T;
-
-typedef struct
-{
-    __IO uint32_t  BUS:1;
-    __IO uint32_t  USB:1;
-    __IO uint32_t  FLD:1;
-    __IO uint32_t  WAKEUP:1;
-    __I  uint32_t  RESERVE0:12;
-    __IO uint32_t  EPTF:6;
-    __I  uint32_t  RESERVE1:9;
-    __IO uint32_t  SETUP:1;
-} USBD_EVF_T;
-
-typedef struct
-{
-    __IO uint32_t  FADDR:7;
-    __I  uint32_t  RESERVE:25;
-} USBD_FADDR_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:7;
-    __IO uint32_t  OVERRUN:1;
-    __IO uint32_t  STS0:3;
-    __IO uint32_t  STS1:3;
-    __IO uint32_t  STS2:3;
-    __IO uint32_t  STS3:3;
-    __IO uint32_t  STS4:3;
-    __IO uint32_t  STS5:3;
-    __I  uint32_t  RESERVE1:6;
-} USBD_STS_T;
-
-
-
-typedef struct
-{
-    __IO uint32_t  USBRST:1;
-    __IO uint32_t  SUSPEND:1;
-    __IO uint32_t  RESUME:1;
-    __IO uint32_t  TIMEOUT:1;
-    __IO uint32_t  PHY_EN:1;
-    __IO uint32_t  RWAKEUP:1;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  USB_EN:1;
-	__IO uint32_t  DPPU_EN:1;
-	__IO uint32_t  PDB:1;
-    __I  uint32_t  RESERVE1:22;
-} USBD_ATTR_T;
-
-
-
-typedef struct
-{
-    __IO uint32_t  FLODET:1;
-    __I  uint32_t  RESERVE:31;
-} USBD_FLODET_T;
-
-typedef struct
-{
-    __I  uint32_t  RESERVE0:3;
-    __IO uint32_t  BUFSEG:6;
-    __I  uint32_t  RESERVE:23;
-} USBD_BUFSEG_T;
-
-typedef struct
-{
-    __IO uint32_t  MXPLD:9;
-    __I  uint32_t  RESERVE:23;
-} USBD_MXPLD_T;
-
-typedef struct
-{
-    __IO uint32_t  EPT:4;
-    __IO uint32_t  ISOCH:1;
-    __IO uint32_t  STATE:2;
-    __IO uint32_t  DSQ:1;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  STALL_CTL:1;
-    __I  uint32_t  RESERVE1:22;
-} USBD_CFG_T;
-
-typedef struct
-{
-    __IO uint32_t  CFGP:1;
-    __IO uint32_t  STALL:1;
-    __I  uint32_t  RESERVE:30;
-} USBD_CFGP_T;
-
-typedef struct
-{
-    __IO uint32_t  DRVSE0:1;
-    __I  uint32_t  RESERVE:31;
-} USBD_DRVSE0_T;
-
-typedef struct
-{
-    __IO uint32_t  BISTEN:1;
-    __IO uint32_t  FINISH:1;
-    __IO uint32_t  BISTFAIL:1;
-    __I  uint32_t  RESERVE:29;
-} USBD_BIST_T;
-
-typedef struct
-{
-    __IO uint32_t  PDMA_RW:1;
-    __IO uint32_t  PDMA_EN:1;
-    __I  uint32_t  RESERVE:30;
-} USBD_PDMA_T;
-
-
-typedef struct
-{
-    USBD_BUFSEG_T   BUFSEG;
-    USBD_MXPLD_T    MXPLD;
-    USBD_CFG_T      CFG;
-    USBD_CFGP_T     CFGP;
-} USBD_EP_T;
-
-typedef struct
-{
-    USBD_IEF_T      IEF;
-    USBD_EVF_T      EVF;
-    USBD_FADDR_T    FADDR;
-    USBD_STS_T      STS;
-    USBD_ATTR_T     ATTR;
-    USBD_FLODET_T   FLODET;
-    USBD_BUFSEG_T   BUFSEG;
-    uint32_t        RESERVE0;
-	USBD_EP_T       EP[6];
-    uint32_t        RESERVE1[4];
-	USBD_DRVSE0_T   DRVSE0;
-    uint32_t        RESERVE2[3];
-	USBD_BIST_T     BIST;
-    USBD_PDMA_T     PDMA;
-} USBD_T;
-
-
-/*------------------------------ PDMA Controller -----------------------------*/
-typedef struct
-{
-    __IO uint32_t  PDMACEN:1;
-    __IO uint32_t  SW_RST:1;
-    __IO uint32_t  MODE_SEL:2;
-    __IO uint32_t  SAD_SEL:2;
-    __IO uint32_t  DAD_SEL:2;
-    __I  uint32_t  RESERVE0:4;
-    __IO uint32_t  WAR_BCR_SEL:4;
-    __I  uint32_t  RESERVE1:3;
-    __IO uint32_t  APB_TWS:2;
-    __I  uint32_t  RESERVE2:2;
-    __IO uint32_t  TRIG_EN:1;
-    __I  uint32_t  RESERVE3:8;
-} PDMA_CSR_T;
-
-typedef __IO uint32_t PDMA_SAR_T;
-typedef __IO uint32_t PDMA_DAR_T;
-
-typedef __IO uint32_t PDMA_BCR_T;
-
-typedef __IO uint32_t PDMA_CSAR_T;
-typedef __IO uint32_t PDMA_CDAR_T;
-
-typedef struct
-{
-    __IO uint32_t  CBCR:24;
-    __I  uint32_t  RESERVE:8;
-} PDMA_CBCR_T;
-
-typedef struct
-{
-    __IO uint32_t  TABORT_IE:1;
-    __IO uint32_t  BLKD_IE:1;
-    __IO uint32_t  WAR_IE:1;
-    __I  uint32_t  RESERVE:29;
-} PDMA_IER_T;
-
-//typedef __IO uint32_t PDMA_ISR_T;
-
-typedef struct
-{
-    __IO uint32_t  TABORT_IF:1;
-    __IO uint32_t  BLKD_IF:1;
-    __I  uint32_t  RESERVE:6;
-	__IO uint32_t  WAR_IF:4;
-    __I  uint32_t  RESERVE1:3;
-	__IO uint32_t  BUSY:1;
-	__I  uint32_t  RESERVE2:15;
-	__IO uint32_t  INTR:1;
-} PDMA_ISR_T;
-
-typedef __IO uint32_t PDMA_SBUF_T;
-
-typedef struct
-{
-    __IO uint32_t  PDMA_RST:1;
-    __I  uint32_t  RESERVE0:7;
-    __IO uint32_t  HCLK0_EN:1;
-    __IO uint32_t  HCLK1_EN:1;
-    __IO uint32_t  HCLK2_EN:1;
-    __IO uint32_t  HCLK3_EN:1;
-    __IO uint32_t  HCLK4_EN:1;
-    __IO uint32_t  HCLK5_EN:1;
-    __IO uint32_t  HCLK6_EN:1;
-    __IO uint32_t  HCLK7_EN:1;
-    __IO uint32_t  HCLK8_EN:1;
-    __IO uint32_t  HCLK9_EN:1;
-    __IO uint32_t  HCLK10_EN:1;
-    __IO uint32_t  HCLK11_EN:1;
-    __I  uint32_t  RESERVE1:12;
-} PDMA_GCRCSR_T;
-
-typedef struct
-{
-    __IO uint32_t  UART0_RXSEL:4;
-    __IO uint32_t  UART0_TXSEL:4;
-    __IO uint32_t  UART1_RXSEL:4;
-    __IO uint32_t  UART1_TXSEL:4;
-    __IO uint32_t  USBD_RXSEL:4;
-    __IO uint32_t  USBD_TXSEL:4;
-    __IO uint32_t  ADC_RXSEL:4;
-    __IO uint32_t  ADC_TXSEL:4;
-} PDMA_PDSSR1_T;
-                                                        
-
-typedef struct
-{
-    __IO uint32_t  SPI0_RXSEL:4;
-    __IO uint32_t  SPI0_TXSEL:4;
-    __IO uint32_t  SPI1_RXSEL:4;
-    __IO uint32_t  SPI1_TXSEL:4;
-    __IO uint32_t  SPI2_RXSEL:4;
-    __IO uint32_t  SPI2_TXSEL:4;
-    __IO uint32_t  SPI3_RXSEL:4;
-    __IO uint32_t  SPI3_TXSEL:4;
-} PDMA_PDSSR0_T;
-
-typedef __IO uint32_t PDMA_GCRISR_T;
-
-typedef struct
-{
-    PDMA_GCRCSR_T   GCRCSR;
-    PDMA_PDSSR0_T   PDSSR0;
-    PDMA_PDSSR1_T   PDSSR1;  
-    PDMA_GCRISR_T   GCRISR;  
-} PDMA_GCR_T;
-
-typedef struct 
-{
-    PDMA_CSR_T      CSR;
-    PDMA_SAR_T      SAR;
-    PDMA_DAR_T      DAR;
-    PDMA_BCR_T      BCR;
-    uint32_t        POINT;
-    PDMA_CSAR_T     CSAR;
-    PDMA_CDAR_T     CDAR;
-    PDMA_CBCR_T     CBCR;
-    PDMA_IER_T      IER;
-    PDMA_ISR_T      ISR;
-    PDMA_SBUF_T     SBUF[4];
-} PDMA_T;
-
-/*----------------------------- PWM Controller -------------------------------*/
-typedef struct
-{
-    __IO uint32_t  CP0:8;
-    __IO uint32_t  CP1:8;
-    __IO uint32_t  DZI0:8;
-    __IO uint32_t  DZI1:8;
-} PWM_PPR_T;
-
-typedef struct
-{
-    __IO uint32_t  CSR0:3;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  CSR1:3;
-    __I  uint32_t  RESERVE1:1;
-    __IO uint32_t  CSR2:3;
-    __I  uint32_t  RESERVE2:1;
-    __IO uint32_t  CSR3:3;
-    __I  uint32_t  RESERVE:17;
-} PWM_CSR_T;
-
-typedef struct
-{
-    __IO uint32_t  CH0EN:1;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  CH0INV:1;
-    __IO uint32_t  CH0MOD:1;
-    __IO uint32_t  DZEN0:1;
-    __IO uint32_t  DZEN1:1;
-    __I  uint32_t  RESERVE1:2;
-    __IO uint32_t  CH1EN:1;
-    __I  uint32_t  RESERVE2:1;
-    __IO uint32_t  CH1INV:1;
-    __IO uint32_t  CH1MOD:1;
-    __I  uint32_t  RESERVE3:4;
-    __IO uint32_t  CH2EN:1;
-    __I  uint32_t  RESERVE4:1;
-    __IO uint32_t  CH2INV:1;
-    __IO uint32_t  CH2MOD:1;
-    __I  uint32_t  RESERVE5:4;
-    __IO uint32_t  CH3EN:1;
-    __I  uint32_t  RESERVE6:1;
-    __IO uint32_t  CH3INV:1;
-    __IO uint32_t  CH3MOD:1;
-    __I  uint32_t  RESERVE7:4;   
-} PWM_PCR_T;
-
-typedef __IO uint32_t PWM_CNR_T;
-
-typedef __IO uint32_t PWM_CMR_T;
-
-typedef __IO uint32_t PWM_PDR_T;
-
-typedef struct
-{
-    __IO uint32_t  PWMIE0:1;
-    __IO uint32_t  PWMIE1:1;
-    __IO uint32_t  PWMIE2:1;
-    __IO uint32_t  PWMIE3:1;
-	__I  uint32_t  RESERVE:28;
-} PWM_PIER_T;
-
-
-typedef struct
-{
-    __IO uint32_t  PWMIF0:1;
-    __IO uint32_t  PWMIF1:1;
-    __IO uint32_t  PWMIF2:1;
-    __IO uint32_t  PWMIF3:1;
-	__I  uint32_t  RESERVE:28;
-} PWM_PIIR_T;
-
-
-typedef struct
-{
-    __IO uint32_t  INV0:1;
-    __IO uint32_t  CRL_IE0:1;
-    __IO uint32_t  CFL_IE0:1;
-    __IO uint32_t  CAPCH0EN:1;
-    __IO uint32_t  CAPIF0:1;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  CRLRI0:1;
-    __IO uint32_t  CFLRI0:1;
-    __I  uint32_t  RESERVE1:8;
-    __IO uint32_t  INV1:1;
-    __IO uint32_t  CRL_IE1:1;
-    __IO uint32_t  CFL_IE1:1;
-    __IO uint32_t  CAPCH1EN:1;
-    __IO uint32_t  CAPIF1:1;
-    __I  uint32_t  RESERVE2:1;
-    __IO uint32_t  CRLRI1:1;
-    __IO uint32_t  CFLRI1:1;
-    __I  uint32_t  RESERVE3:8;
-} PWM_CCR0_T;
-
-
-typedef struct
-{
-    __IO uint32_t  INV2:1;
-    __IO uint32_t  CRL_IE2:1;
-    __IO uint32_t  CFL_IE2:1;
-    __IO uint32_t  CAPCH2EN:1;
-    __IO uint32_t  CAPIF2:1;
-    __I  uint32_t  RESERVE0:1;
-    __IO uint32_t  CRLRI2:1;
-    __IO uint32_t  CFLRI2:1;
-    __I  uint32_t  RESERVE1:8;
-    __IO uint32_t  INV3:1;
-    __IO uint32_t  CRL_IE3:1;
-    __IO uint32_t  CFL_IE3:1;
-    __IO uint32_t  CAPCH3EN:1;
-    __IO uint32_t  CAPIF3:1;
-    __I  uint32_t  RESERVE2:1;
-    __IO uint32_t  CRLRI3:1;
-    __IO uint32_t  CFLRI3:1;
-    __I  uint32_t  RESERVE3:8;
-} PWM_CCR1_T;
-
-
-typedef __IO uint32_t PWM_CRLR_T;
-
-typedef __IO uint32_t PWM_CFLR_T;
-
-typedef __IO uint32_t PWM_CAPENR_T;
-
-typedef struct
-{
-    __IO uint32_t  PWM0:1;
-    __IO uint32_t  PWM1:1;
-    __IO uint32_t  PWM2:1;
-    __IO uint32_t  PWM3:1;
-	__I  uint32_t  RESERVE:28;
-} PWM_POE_T;
-
-
-typedef struct
-{
-    PWM_PPR_T       PPR;
-    PWM_CSR_T       CSR;
-    PWM_PCR_T       PCR;
-    PWM_CNR_T       CNR0;
-    PWM_CMR_T       CMR0;
-    PWM_PDR_T       PDR0;
-    PWM_CNR_T       CNR1;
-    PWM_CMR_T       CMR1;
-    PWM_PDR_T       PDR1;
-    PWM_CNR_T       CNR2;
-    PWM_CMR_T       CMR2;
-    PWM_PDR_T       PDR2;
-    PWM_CNR_T       CNR3;
-    PWM_CMR_T       CMR3;
-    PWM_PDR_T       PDR3;
-    __I uint32_t    RESERVE0;
-    PWM_PIER_T      PIER;
-    PWM_PIIR_T      PIIR;
-    __I uint32_t    RESERVE1[2];
-    PWM_CCR0_T      CCR0;
-    PWM_CCR1_T      CCR1;
-    PWM_CRLR_T      CRLR0;
-    PWM_CFLR_T      CFLR0;
-    PWM_CRLR_T      CRLR1;
-    PWM_CFLR_T      CFLR1;
-    PWM_CRLR_T      CRLR2;
-    PWM_CFLR_T      CFLR2;
-    PWM_CRLR_T      CRLR3;
-    PWM_CFLR_T      CFLR3;
-    PWM_CAPENR_T    CAPENR;
-    PWM_POE_T       POE;    
-        
-    
-} PWM_T;
-
-
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Peripheral and SRAM base address */
-#define FLASH_BASE          ((     uint32_t)0x00000000)
-#define SRAM_BASE           ((     uint32_t)0x20000000)
-#define AHB_BASE            ((     uint32_t)0x50000000)
-#define APB1_BASE           ((     uint32_t)0x40000000)
-#define APB2_BASE           ((     uint32_t)0x40100000)
-
-/* Peripheral memory map */
-#define GPIO_BASE           (AHB_BASE        + 0x4000)
-
-#define GPIOA_BASE          (GPIO_BASE               )
-#define GPIOB_BASE          (GPIO_BASE       + 0x0040)
-#define GPIOC_BASE          (GPIO_BASE       + 0x0080)
-#define GPIOD_BASE          (GPIO_BASE       + 0x00C0)
-#define GPIOE_BASE          (GPIO_BASE       + 0x0100)
-#define GPIO_DBNCECON_BASE  (GPIO_BASE       + 0x0180)
-
-#define UART0_BASE           (APB1_BASE      + 0x50000)
-#define UART1_BASE           (APB2_BASE      + 0x50000)
-
-#define TIMER0_BASE          (APB1_BASE      + 0x10000)  
-#define TIMER1_BASE          (APB1_BASE      + 0x10020)  
-#define TIMER2_BASE          (APB2_BASE      + 0x10000)  
-#define TIMER3_BASE          (APB2_BASE      + 0x10020)  
-
-#define WDT_BASE       	     (APB1_BASE      + 0x4000)  
-
-#define SPI0_BASE            (APB1_BASE      + 0x30000)
-#define SPI1_BASE            (APB1_BASE      + 0x34000)
-#define SPI2_BASE            (APB2_BASE      + 0x30000)
-#define SPI3_BASE            (APB2_BASE      + 0x34000)
-
-#define I2C0_BASE            (APB1_BASE      + 0x20000)
-#define I2C1_BASE            (APB2_BASE      + 0x20000)
-
-#define RTC_BASE             (APB1_BASE      + 0x08000)
-
-#define ADC_BASE             (APB1_BASE      + 0xE0000)
-#define ADC_ADSR             (ADC_BASE       + 0x30)
-
-#define ACMP_BASE            (APB1_BASE      + 0xD0000)   
-
-#define SYSCLK_BASE          (AHB_BASE       + 0x00200)
-
-#define GCR_BASE             (AHB_BASE       + 0x00000)
-
-#define INT_BASE             (AHB_BASE       + 0x00300)
-
-#define FMC_BASE             (AHB_BASE       + 0x0C000)
-
-#define PS2_BASE             (APB2_BASE      + 0x00000)
-
-#define CAN0_BASE            (APB2_BASE      + 0x80000)
-#define CAN1_BASE            (APB2_BASE      + 0x84000)
-
-#define USBD_BASE            (APB1_BASE      + 0x60000)
-
-#define PDMA0_BASE           (AHB_BASE       + 0x08000)
-#define PDMA1_BASE           (AHB_BASE       + 0x08100)
-#define PDMA2_BASE           (AHB_BASE       + 0x08200)
-#define PDMA3_BASE           (AHB_BASE       + 0x08300)
-#define PDMA4_BASE           (AHB_BASE       + 0x08400)
-#define PDMA5_BASE           (AHB_BASE       + 0x08500)
-#define PDMA6_BASE           (AHB_BASE       + 0x08600)
-#define PDMA7_BASE           (AHB_BASE       + 0x08700)
-#define PDMA8_BASE           (AHB_BASE       + 0x08800)
-#define PDMA9_BASE           (AHB_BASE       + 0x08900)
-#define PDMA10_BASE          (AHB_BASE       + 0x08A00)
-#define PDMA11_BASE          (AHB_BASE       + 0x08B00)
-#define PDMA_GCR_BASE        (AHB_BASE       + 0x08F00)
-
-#define PWM_BASE             (APB1_BASE      + 0x40000)
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define GPIOA               ((GPIO_T *) GPIOA_BASE)
-#define GPIOB               ((GPIO_T *) GPIOB_BASE)
-#define GPIOC               ((GPIO_T *) GPIOC_BASE)
-#define GPIOD               ((GPIO_T *) GPIOD_BASE)
-#define GPIOE               ((GPIO_T *) GPIOE_BASE)
-#define GPIO_DBNCECON       ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE)
-
-#define UART0               ((UART_T *) UART0_BASE)
-#define UART1               ((UART_T *) UART1_BASE)
-
-#define TIMER0              ((TIMER_T *) TIMER0_BASE)
-#define TIMER1              ((TIMER_T *) TIMER1_BASE)
-#define TIMER2              ((TIMER_T *) TIMER2_BASE)
-#define TIMER3              ((TIMER_T *) TIMER3_BASE)
-
-#define WDT                 ((WDT_T *) WDT_BASE)
-
-#define SPI0                ((SPI_T *) SPI0_BASE)
-#define SPI1                ((SPI_T *) SPI1_BASE)
-#define SPI2                ((SPI_T *) SPI2_BASE)
-#define SPI3                ((SPI_T *) SPI3_BASE)
-
-#define I2C0                ((I2C_T *) I2C0_BASE)
-#define I2C1                ((I2C_T *) I2C1_BASE)
-
-#define RTC                 ((RTC_T *) RTC_BASE)
-
-#define ADC                 ((ADC_T *) ADC_BASE)
-
-#define ACMP                ((ACMP_T *) ACMP_BASE)
-
-#define SYSCLK              ((SYSCLK_T *) SYSCLK_BASE)
-
-#define SYS                 ((GCR_T *) GCR_BASE)
-
-#define SYSINT              ((GCR_INT_T *) INT_BASE)
-
-#define FMC                 ((FMC_T *) FMC_BASE)
-
-#define PS2                 ((PS2_T *) PS2_BASE)
-
-#define CAN0                ((CAN_T *) CAN0_BASE)
-#define CAN1                ((CAN_T *) CAN1_BASE)
-
-#define USBD                ((USBD_T *) USBD_BASE)
-
-#define PDMA0               ((PDMA_T *) PDMA0_BASE)
-#define PDMA1               ((PDMA_T *) PDMA1_BASE)
-#define PDMA2               ((PDMA_T *) PDMA2_BASE)
-#define PDMA3               ((PDMA_T *) PDMA3_BASE)
-#define PDMA4               ((PDMA_T *) PDMA4_BASE)
-#define PDMA5               ((PDMA_T *) PDMA5_BASE)
-#define PDMA6               ((PDMA_T *) PDMA6_BASE)
-#define PDMA7               ((PDMA_T *) PDMA7_BASE)
-#define PDMA8               ((PDMA_T *) PDMA8_BASE)
-#define PDMA9               ((PDMA_T *) PDMA9_BASE)
-#define PDMA10              ((PDMA_T *) PDMA10_BASE)
-#define PDMA11              ((PDMA_T *) PDMA11_BASE)
-#define PDMA_GCR            ((PDMA_GCR_T *) PDMA_GCR_BASE)
-
-#define PWM                 ((PWM_T *) PWM_BASE)
-
-#define UNLOCKREG(x)        *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x88
-#define LOCKREG(x)          *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x00;     
-
-#define REGCOPY(dest, src)  *((uint32_t *)&(dest)) = *((uint32_t *)&(src))
-#define CLEAR(dest) 		*((uint32_t *)&(dest)) = 0
-
-//=============================================================================
-typedef volatile unsigned char  vu8;
-typedef volatile unsigned long  vu32;
-typedef volatile unsigned short vu16;
-#define M8(adr)  (*((vu8  *) (adr)))
-#define M16(adr) (*((vu16 *) (adr)))
-#define M32(adr) (*((vu32 *) (adr)))
-
-#define outpw(port,value)	*((volatile unsigned int *)(port))=value
-#define inpw(port)			(*((volatile unsigned int *)(port)))
-#define outpb(port,value)	*((volatile unsigned char *)(port))=value
-#define inpb(port)			(*((volatile unsigned char *)(port)))
-#define outps(port,value)	*((volatile unsigned short *)(port))=value
-#define inps(port)			(*((volatile unsigned short *)(port)))
-
-#define E_SUCCESS 	0
-#define NULL         0
-
-#define TRUE	   	1
-#define FALSE   	0
-
-#define ENABLE     1
-#define DISABLE    0
-
-// Define one bit mask
-#define BIT0	0x00000001
-#define BIT1	0x00000002
-#define BIT2	0x00000004
-#define BIT3	0x00000008
-#define BIT4	0x00000010
-#define BIT5	0x00000020
-#define BIT6	0x00000040
-#define BIT7	0x00000080
-#define BIT8	0x00000100
-#define BIT9	0x00000200
-#define BIT10	0x00000400
-#define BIT11	0x00000800
-#define BIT12	0x00001000
-#define BIT13	0x00002000
-#define BIT14	0x00004000
-#define BIT15	0x00008000
-#define BIT16	0x00010000
-#define BIT17	0x00020000
-#define BIT18	0x00040000
-#define BIT19	0x00080000
-#define BIT20	0x00100000
-#define BIT21	0x00200000
-#define BIT22	0x00400000
-#define BIT23	0x00800000
-#define BIT24	0x01000000
-#define BIT25	0x02000000
-#define BIT26	0x04000000
-#define BIT27	0x08000000
-#define BIT28	0x10000000
-#define BIT29	0x20000000
-#define BIT30	0x40000000
-#define BIT31	0x80000000
-
-#endif
-                                                                                                 
diff --git a/bsp/nuc140/CMSIS/CM0/core_cm0.c b/bsp/nuc140/CMSIS/CM0/core_cm0.c
deleted file mode 100644
index cbac38562a..0000000000
--- a/bsp/nuc140/CMSIS/CM0/core_cm0.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/******************************************************************************
- * @file:    core_cm0.c
- * @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version: V1.10
- * @date:    24. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-#include <stdint.h>
-
-
-/* define compiler specific symbols */
-#if defined   ( __CC_ARM   )
-  #define __ASM            __asm           /*!< asm keyword for armcc          */
-  #define __INLINE         __inline        /*!< inline keyword for armcc        */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm            /*!< asm keyword for iarcc           */
-  #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
-  #define __nop           __no_operation   /*!< no operation intrinsic in iarcc */
-
-#elif defined (  __GNUC__  )
-  #define __ASM             asm            /*!< asm keyword for gcc            */
-  #define __INLINE          inline         /*!< inline keyword for gcc         */
-#endif
-
-
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t  __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-#pragma diag_suppress=Pe940
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  __ASM("rev16 r0, r0");
-  __ASM("bx lr");
-}
-
-
-#pragma diag_default=Pe940
-
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, psp" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );
-}
-
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-uint32_t __get_PRIMASK(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int32_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuc140/CMSIS/CM0/core_cm0.h b/bsp/nuc140/CMSIS/CM0/core_cm0.h
deleted file mode 100644
index f4aee39cd9..0000000000
--- a/bsp/nuc140/CMSIS/CM0/core_cm0.h
+++ /dev/null
@@ -1,801 +0,0 @@
-/******************************************************************************
- * @file:    core_cm0.h
- * @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version: V1.10
- * @date:    24. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-
-#ifndef __CM0_CORE_H__
-#define __CM0_CORE_H__
-
-
-#define __CM0_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
-
-
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    2               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#define     __I     volatile const            /*!< defines 'read only' permissions      */
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-
-
-/* System Reset */
-#define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */
-#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */
-#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */
-#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */
-
-
-
-
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
-typedef struct
-{
-  __IO uint32_t ISER[1];                      /*!< Interrupt Set Enable Register            */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                      /*!< Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                      /*!< Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                      /*!< Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                        /*!< Interrupt Priority Register              */
-}  NVIC_Type;
-
-
-/* memory mapping struct for System Control Block */
-typedef struct
-{
-  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */
-  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */
-  __IO uint32_t SCR;                          /*!< System Control Register                                  */
-  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                       /*!< System Handlers Priority Registers. [0] is RESERVED      */
-  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */
-       uint32_t RESERVED2[2];
-  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */
-} SCB_Type;
-
-
-/* memory mapping struct for SysTick */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */
-} SysTick_Type;
-
-
-
-/* Core Debug Register */
-typedef struct
-{
-  __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */
-  __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */
-  __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */
-  __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */
-} CoreDebug_Type;
-
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */
-#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */
-#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */
-#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */
-#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */
-
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-  #define __NOP           __no_operation                              /*!< no operation intrinsic in IAR Compiler */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            asm                                        /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-#define __WFI                             __wfi
-#define __WFE                             __wfe
-#define __SEV                             __sev
-#define __ISB()                           __isb(0)
-#define __DSB()                           __dsb(0)
-#define __DMB()                           __dmb(0)
-#define __REV                             __rev
-
-
-  /* intrinsic void __enable_irq();     */
-  /* intrinsic void __disable_irq();    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else  /* (__ARMCC_VERSION >= 400000)  */
-
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
-
-static __INLINE  void __WFI()                     { __ASM ("wfi"); }
-static __INLINE  void __WFE()                     { __ASM ("wfe"); }
-static __INLINE  void __SEV()                     { __ASM ("sev"); }
-
-//static __INLINE  void __ISB(arg)                  { __ASM ("isb"); }
-//static __INLINE  void __DSB(arg)                  { __ASM ("dsb"); }
-//static __INLINE  void __DMB(arg)                  { __ASM ("dmb"); }
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-
-
-/* intrinsic void __set_PRIMASK();                                    */
-/* intrinsic void __get_PRIMASK();                                    */
-/* intrinsic uint32_t __REV(uint32_t value);                          */
-/* intrinsic uint32_t __REVSH(uint32_t value);                        */
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
-static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
-static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
-static __INLINE void __ISB(arg)                   { __ASM volatile ("isb"); }
-static __INLINE void __DSB(arg)                   { __ASM volatile ("dsb"); }
-static __INLINE void __DMB(arg)                   { __ASM volatile ("dmb"); }
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @param  none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @param  none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t  __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Control Register value 
- * 
- * @param  none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * Reverse byte order in signed short value with sign extension to integer
- *
- * @param  int16_t value to reverse
- * @return int32_t reversed value
- *
- * @brief  Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#endif
-
-
-
-/* ##########################   NVIC functions  #################################### */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-
-/**
- * @brief  Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param  uint32_t priority_grouping is priority grouping field
- * @return  
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field 
- * SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
-{
-  uint32_t reg_value=0;
-  
-  reg_value  = SCB->AIRCR;                                                                            /* read old register configuration    */
-  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                                                      /* clear bits to change               */
-  reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8)));                         /* Insert write key and priorty group */
-  SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn_Type IRQn specifies the interrupt number
- * @return none 
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* enable interrupt */
-}
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn_Type IRQn is the positive number of the external interrupt
- * @return  none
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* disable interrupt */
-}
-
-/**
- * @brief  Read the interrupt pending bit for a device specific interrupt source
- * 
- * @param  IRQn_Type IRQn is the number of the device specifc interrupt
- * @return IRQn_Type Number of pending interrupt or zero
- *
- * Read the pending register in NVIC and return the number of the
- * specified interrupt if its status is pending, otherwise it returns 
- * zero. The interrupt number cannot be a negative value.
- */
-static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));         /* Return Interrupt bit or 'zero' */
-}
-
-/**
- * @brief  Set the pending bit for an external interrupt
- * 
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @return  none
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* set interrupt pending */
-}
-
-/**
- * @brief  Clear the pending bit for an external interrupt
- *
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @return  none
- *
- * Clear the pending bit for the specified interrupt. 
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* Clear pending interrupt */
-}
-
-/**
- * @brief  Set the priority for an interrupt
- *
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @param  priority is the priority for the interrupt
- * @return  none
- *
- * Set the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt. \n
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] =  (NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-/**
- * @brief  Read the priority for an interrupt
- *
- * @param  IRQn_Type IRQn is the Number of the interrupt
- * @return priority is the priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)((NVIC->IP[_IP_IDX(IRQn)]  >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts    */
-}
-
-
-
-/* ##################################    SysTick function  ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/* SysTick constants */
-#define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */
-#define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */
-#define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */
-#define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */
-
-/**
- * @brief  Initialize and start the SysTick counter and its interrupt.
- *
- * @param  uint32_t ticks is the number of ticks between two interrupts
- * @return  none
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate 
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SYSTICK_MAXCOUNT)  return (1);                                                /* Reload value impossible */
-
-  SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;                                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                               /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   =  (0x00);                                                                 /* Load the SysTick Counter Value */
-  SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT);    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                                               /* Function successful */
-}
-
-#endif
-
-
-
-
-
-/* ##################################    Reset function  ############################################ */
-
-/**
- * @brief  Initiate a system reset request.
- *
- * @param   none
- * @return  none
- *
- * Initialize a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (1<<NVIC_SYSRESETREQ));                               /* Keep priority group unchanged */
-}
-
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s b/bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s
deleted file mode 100644
index d420492899..0000000000
--- a/bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s
+++ /dev/null
@@ -1,381 +0,0 @@
-;/*---------------------------------------------------------------------------------------------------------*/
-;/*                                                                                                         */
-;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved.                                         */
-;/*                                                                                                         */
-;/*---------------------------------------------------------------------------------------------------------*/
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-CLK_BA_base      EQU 0x50000200
-PWRCON			 EQU 0x00
-AHBCLK			 EQU 0x04
-APBCLK			 EQU 0x08
-CLKSEL0			 EQU 0x10
-CLKSEL1			 EQU 0x14
-CLKDIV			 EQU 0x18
-PLLCON			 EQU 0x20
-TEST_S			 EQU 0x30
-
-CLK_BA_APBCLK    EQU 0x50000208
-
-;// Define clock enable registers  
-
-ADC_COMP_CLK     EQU 0x50000208
-ADC_enable		 EQU 0x10000000
-COMP_enable      EQU 0x40000000
-
-PDMA_CLK         EQU 0x50000204 
-PDMA_enable      EQU 0x00000003
-
-;;  bit 0  CPU_EN
-;;	bit 1  PDMA_EN
-
-
-
-
-;// Define COMP registers base
-COMP_base        EQU  0x400D0000
-CMP1CR           EQU  0x00
-CMP2CR           EQU  0x04
-CMPSR            EQU  0x08
-
-;// Define ADC registers base
-ADC_base         EQU  0x400E0000
-ADDR0            EQU  0x00
-ADDR1            EQU  0x04
-ADDR2            EQU  0x08
-ADDR3            EQU  0x0c
-ADDR4            EQU  0x10
-ADDR5            EQU  0x14
-ADDR6            EQU  0x18
-ADDR7            EQU  0x1c
-ADCR             EQU  0x20
-ADCHER           EQU  0x24
-ADCMPR0          EQU  0x28
-ADCMPR1          EQU  0x2c
-ADSR             EQU  0x30
-ADCALR           EQU  0x34
-ADCFCR           EQU  0x38
-ADCALD           EQU  0x3c
-
-;// Pattern Table
-pattern_55555555 EQU  0x55555555
-pattern_aaaaaaaa EQU  0xaaaaaaaa
-pattern_00005555 EQU  0x00005555
-pattern_0000aaaa EQU  0x0000aaaa
-pattern_05550515 EQU  0x05550515
-pattern_0aaa0a2a EQU  0x0aaa0a2a
-
-;// Define PDMA regsiter base
-PDMA_BA_ch0_base        EQU  0x50008000
-PDMA_BA_ch1_base        EQU  0x50008100
-PDMA_BA_ch2_base        EQU  0x50008200
-PDMA_BA_ch3_base        EQU  0x50008300
-PDMA_BA_ch4_base        EQU  0x50008400
-PDMA_BA_ch5_base        EQU  0x50008500
-PDMA_BA_ch6_base        EQU  0x50008600
-PDMA_BA_ch7_base        EQU  0x50008700
-
-PDMA_BA_GCR             EQU 0x50008F00
-PDMA_BA_GCR_base        EQU 0x50008F00
-
-PDMA_GCRCSR		 EQU  0X00
-PDMA_PDSSR2		 EQU  0X04
-PDMA_PDSSR1		 EQU  0X08  ;; PDMA channel select   0x77000000
-PDMA_GCRISR		 EQU  0X0C
-
-PDMA_GLOBAL_enable      EQU 0x0000FF00
-
-
-PDMA_CSR         EQU  0X00
-PDMA_SAR         EQU  0X04
-PDMA_DAR         EQU  0X08
-PDMA_BCR         EQU  0X0C
-PDMA_CSAR        EQU  0X14
-PDMA_CDAR        EQU  0X18
-PDMA_CBSR        EQU  0X1C
-PDMA_IER         EQU  0X20
-PDMA_ISR         EQU  0X24
-PDMA_CTCSR       EQU  0X28
-PDMA_SASOCR		 EQU  0X2C
-PDMA_DASOCR      EQU  0X30
-PDMA_SBUF0       EQU  0X80
-PDMA_SBUF1       EQU  0X84
-PDMA_SBUF2       EQU  0X88
-PDMA_SBUF3       EQU  0X8C
-
-
-;// Define VIC control register
-VIC_base         EQU  0xFFFF0000
-VIC_SCR15        EQU  0x003c
-VIC_SVR15        EQU  0x00bc
-VIC_SCR16        EQU  0x0040
-VIC_SVR16        EQU  0x00c0
-VIC_SCR30        EQU  0x0078
-VIC_SVR30        EQU  0x00f8
-VIC_MECR         EQU  0x0318
-VIC_MDCR         EQU  0x031c
-VIC_EOSCR        EQU  0x0130
-
-;//==================================
-INT_BA_base      EQU  0x50000300
-
-
-;// Parameter table
-ADC_PDMA_CFG     EQU  0x00002980  
-ADC_PDMA_DST     EQU  0xC0000000
-ADC_PDMA_SRC     EQU  0xE0024200
-ADC_PDMA_TCBL    EQU  0x00030008
-
-;//==================================
-
-
-GPIO_base        EQU  0x50004000
-GPIOB_PMD		 EQU  0x0040
-GPIOB_OFFD		 EQU  0x0044
-GPIOB_DOUT		 EQU  0x0048
-GPIOB_DMASK		 EQU  0x004C
-GPIOB_PIN		 EQU  0x0050
-GPIOB_DBEN		 EQU  0x0054
-GPIOB_IMD		 EQU  0x0058
-GPIOB_IEN		 EQU  0x005C
-GPIOB_ISRC		 EQU  0x0060
-
-;//==================================
-
-
-GCR_base         EQU  0x50000000
-GPB_MFP          EQU  0x0034
-
-
-
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
-
-
-
-
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                                                  ; maximum of 32 External Interrupts are possible
-                DCD     BOD_IRQHandler  
-                DCD     WDT_IRQHandler  
-                DCD     EINT0_IRQHandler
-                DCD     EINT1_IRQHandler
-                DCD     GPAB_IRQHandler 
-                DCD     GPCDE_IRQHandler
-                DCD     PWMA_IRQHandler 
-                DCD     PWMB_IRQHandler 
-                DCD     TMR0_IRQHandler 
-                DCD     TMR1_IRQHandler 
-                DCD     TMR2_IRQHandler 
-                DCD     TMR3_IRQHandler 
-                DCD     UART0_IRQHandler
-                DCD     UART1_IRQHandler
-                DCD     SPI0_IRQHandler 
-                DCD     SPI1_IRQHandler 
-                DCD     SPI2_IRQHandler 
-                DCD     SPI3_IRQHandler 
-                DCD     I2C0_IRQHandler 
-                DCD     I2C1_IRQHandler 
-                DCD     CAN0_IRQHandler 
-                DCD     CAN1_IRQHandler
-                DCD     Default_Handler 
-                DCD     USBD_IRQHandler  
-                DCD     PS2_IRQHandler  
-                DCD     ACMP_IRQHandler 
-                DCD     PDMA_IRQHandler
-                DCD     Default_Handler 
-                DCD     PWRWU_IRQHandler
-                DCD     ADC_IRQHandler
-                DCD     Default_Handler  
-                DCD     RTC_IRQHandler  
-                
-                
-                
-                
-                
-                
-                
-                AREA    |.text|, CODE, READONLY
-                
-                
-                
-; Reset Handler 
-                
-                ENTRY
-                
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-                
-; Dummy Exception Handlers (infinite loops which can be modified)                
-                
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  GPAB_IRQHandler           [WEAK]
-                EXPORT  GPCDE_IRQHandler          [WEAK]
-                EXPORT  PWMA_IRQHandler           [WEAK]
-                EXPORT  PWMB_IRQHandler           [WEAK]
-                EXPORT  TMR0_IRQHandler           [WEAK]
-                EXPORT  TMR1_IRQHandler           [WEAK]
-                EXPORT  TMR2_IRQHandler           [WEAK]
-                EXPORT  TMR3_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  SPI0_IRQHandler           [WEAK]
-                EXPORT  SPI1_IRQHandler           [WEAK]
-                EXPORT  SPI2_IRQHandler           [WEAK]
-                EXPORT  SPI3_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  CAN0_IRQHandler           [WEAK]
-                EXPORT  CAN1_IRQHandler           [WEAK]
-                EXPORT  USBD_IRQHandler           [WEAK]
-                EXPORT  PS2_IRQHandler            [WEAK]
-                EXPORT  ACMP_IRQHandler           [WEAK]
-                EXPORT  PDMA_IRQHandler           [WEAK]
-                EXPORT  PWRWU_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                
-BOD_IRQHandler
-WDT_IRQHandler
-EINT0_IRQHandler
-EINT1_IRQHandler
-GPAB_IRQHandler
-GPCDE_IRQHandler
-PWMA_IRQHandler
-PWMB_IRQHandler
-TMR0_IRQHandler
-TMR1_IRQHandler
-TMR2_IRQHandler
-TMR3_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-SPI3_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-CAN0_IRQHandler
-CAN1_IRQHandler
-USBD_IRQHandler
-PS2_IRQHandler
-ACMP_IRQHandler
-PDMA_IRQHandler
-PWRWU_IRQHandler
-ADC_IRQHandler
-RTC_IRQHandler
-                B       .
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-                ELSE
-                
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, = (Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END
diff --git a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c
deleted file mode 100644
index c4e73afd63..0000000000
--- a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------*/
-/*                                                                                                         */
-/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved.                                         */
-/*                                                                                                         */
-/*---------------------------------------------------------------------------------------------------------*/
-#include <stdint.h>
-#include "NUC1xx.h"
-
-/*----------------------------------------------------------------------------
-  Define SYSCLK
- *----------------------------------------------------------------------------*/
-#define __HSI (50000000UL)
-
-/*----------------------------------------------------------------------------
-  Clock Definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemFrequency  = __HSI;   /*!< System Clock Frequency (Core Clock) */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Function: SystemInit                                                                                    */
-/*                                                                                                         */
-/* Parameters:                                                                                             */
-/*      None                                                                                               */
-/*                                                                                                         */
-/* Returns:                                                                                                */
-/*      None                                                                                               */
-/*                                                                                                         */
-/* Description:                                                                                            */
-/*      The necessary initializaiton of systerm.                                                           */
-/*                                                                                                         */
-/*---------------------------------------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-}
-
diff --git a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h
deleted file mode 100644
index f29860fabc..0000000000
--- a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/******************************************************************************
- * @file:    system_armikmcu.h
- * @purpose: CMSIS ARM Cortex-M0 Device Peripheral Access Layer Header File
- * @version: V0.01
- * @date:    17. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_ARMCM0_H
-#define __SYSTEM_ARMCM0_H
-
-extern uint32_t SystemFrequency;                   /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system
- *         Initialise GPIO directions and values
- */
-extern                   void SystemInit     (void);
-#endif
diff --git a/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm b/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm
deleted file mode 100644
index 4743909ce4..0000000000
--- a/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm
+++ /dev/null
@@ -1,1204 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html xmlns:p="urn:schemas-microsoft-com:office:powerpoint" xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office"><head>
-  
-  <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-  <meta name="ProgId" content="FrontPage.Editor.Document">
-  <style>
-<!--
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-h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; text-align: Center; margin-right: 3 }
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-    .style1 {
-	background-color: #E0E0E0;
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-.O
-	{color:#1D315B;
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-  </style></head>
-<body>
-<h1>Cortex Microcontroller Software Interface Standard</h1>
-
-<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
-<p align="center">Version: 1.10 - 24. Feb. 2009</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
-	<li>Version 1.00: initial release. </li>
-	<li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
-	<li>Version 1.02: added Cortex-M0. </li>
-	<li>Version 1.10: second review. </li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
-  <li class="LI2"><a href="#1">About</a></li>
-  <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
-  <li class="LI2"><a href="#3">CMSIS Files</a></li>
-  <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
-  <li class="LI2"><a href="#5">CMSIS Example</a></li>
-</ol>
-
-<h2><a name="1"></a>About</h2>
-
-<p>
-  The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
-  that are faced when software components are deployed to physical microcontroller devices based on a
-  Cortex-M0 / Cortex-M1 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M 
-  processor cores (the term Cortex-Mx is used to indicate that). The CMSIS is defined in close co-operation
-  with various silicon and software vendors and provides a common approach to interface to peripherals, 
-  real-time operating systems, and middleware components.
-</p>
-
-<p>ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:</p>
-<ul>
-  <li><strong>Core Peripheral Access Layer</strong>: contains name definitions, 
-    address definitions and helper functions to
-    access core registers and peripherals. It defines also an device
-    independent interface for RTOS Kernels that includes debug channel
-    definitions.</li>
-  <li><strong>Middleware Access Layer:</strong> provides common methods to
-    access peripherals for the software industry. The Middleware Access Layer
-    is adapted by the Silicon Vendor for the device specific peripherals used
-    by middleware components. The middleware access layer is currently in 
-	development and not yet part of this documentation</li>
-</ul>
-
-<p>These software layers are expanded by Silicon partners with:</p>
-<ul>
-  <li><strong>Device Peripheral Access Layer</strong>: provides definitions
-    for all device peripherals</li>
-  <li><strong>Access Functions for Peripherals (optional)</strong>: provides
-    additional helper functions for peripherals</li>
-</ul>
-
-<p>CMSIS defines for a Cortex-Mx Microcontroller System:</p>
-<ul>
-  <li style="text-align: left;">A common way to access peripheral registers
-    and a common way to define exception vectors.</li>
-  <li style="text-align: left;">The register names of the <strong>Core
-    Peripherals</strong> and<strong> </strong>the names of the <strong>Core
-    Exception Vectors</strong>.</li>
-  <li>An device independent interface for RTOS Kernels including a debug
-    channel.</li>
-  <li style="text-align: left;">Interfaces for middleware components (TCP/IP
-    Stack, Flash File System).</li>
-</ul>
-
-<p>
-  By using CMSIS compliant software components, the user can easier re-use template code. 
-  CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-</p>
-
-<h2><a name="2"></a>Coding Rules and Conventions</h2>
-
-<p>
-  The following section describes the coding rules and conventions used in the CMSIS 
-  implementation. It contains also information about data types and version number information.
-</p>
-
-<h3>Essentials</h3>
-<ul>
-  <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, 
-      there are disable and enable sequences for PC-LINT inserted.</li>
-  <li>ANSI standard data types defined in the ANSI C header file
-    <strong>&lt;stdint.h&gt;</strong> are used.</li>
-  <li>#define constants that include expressions must be enclosed by
-    parenthesis.</li>
-  <li>Variables and parameters have a complete data type.</li>
-  <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
-    re-entrant.</li>
-  <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
-    (which means that wait/query loops are done at other software layers such as 
-    the <strong>Middleware Access Layer</strong>).</li>
-  <li>For each exception/interrupt there is definition for:
-  <ul>
-    <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
-	(for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
-    <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
-    <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
-  </ul></li>
-</ul>
-
-<h3>Recommendations</h3>
-
-<p>The CMSIS recommends the following conventions for identifiers.</p>
-<ul>
-  <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
-  <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
-  <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
-  <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
-</ul>
-
-<b>Comments</b>
-
-<ul>
-  <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style 
-  (<em>// comment</em>). It is assumed that the programming tools support today 
-	consistently the C++ comment style.</li>
-  <li><strong>Function Comments</strong> provide for each function the following information:
-  <ul>
-    <li>one-line brief function overview.</li>
-    <li>detailed parameter explanation.</li>
-    <li>detailed information about return values.</li>
-    <li>detailed description of the actual function.</li>
-  </ul>
-  <p><b>Doxygen Example:</b></p>
-  <pre>
-/** 
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- * @param  IRQn  interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */</pre>
-  </li>
-</ul>
-
-<h3>Data Types and IO Type Qualifiers</h3>
-
-<p>
-  The <strong>Cortex-Mx HAL</strong> uses the standard types from the standard ANSI C header file
-  <strong>&lt;stdint.h&gt;</strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
-  to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of 
-  debug information of peripheral registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
-      <th class="kt">#define</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__I</td>
-      <td class="kt">volatile const</td>
-      <td class="kt">Read access only</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__O</td>
-      <td class="kt">volatile</td>
-      <td class="kt">Write access only</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__IO</td>
-      <td class="kt">volatile</td>
-      <td class="kt">Read and write access</td>
-    </tr>
-  </tbody>
-</table>
-
-<h3>CMSIS Version Number</h3>
-<p>
-  File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM3_CMSIS_VERSION_MAIN  (0x00)      /* [31:16] main version       */
-#define __CM3_CMSIS_VERSION_SUB   (0x03)      /* [15:0]  sub version        */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB)</pre>
-
-<p>
-  File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM0_CMSIS_VERSION_MAIN  (0x00)      /* [31:16] main version       */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)      /* [15:0]  sub version        */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM0_CMSIS_VERSION_SUB)</pre>
-
-
-<h3>CMSIS Cortex Core</h3>
-<p>
-  File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-Mx with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M                (0x03)</pre>
-
-<p>
-  File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-Mx with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M                (0x00)</pre>
-
-
-<h2><a name="3"></a>CMSIS Files</h2>
-<p>
-  This section describes the Files provided in context with the CMSIS to access the Cortex-Mx
-  hardware and peripherals.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">File</th>
-      <th class="kt">Provider</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap"><i>device.h</i></td>
-      <td class="kt">Device specific (provided by silicon partner)</td>
-      <td class="kt">Defines the peripherals for the actual device. The file may use 
-        several other include files to define the peripherals of the actual device.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm0.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm3.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm0.c</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Provides helper functions that access core registers.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm0.c</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Provides helper functions that access core registers.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
-      <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
-      <td class="kt">Provides the Cortex-Mx startup code and the complete (device specific) Interrupt Vector Table</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">system<i>_device</i></td>
-      <td class="kt">ARM (adapted by silicon partner)</td>
-      <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes 
-        typically the oscillator (PLL) that is part of the microcontroller device</td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><em>device.h</em></h3>
-
-<p>
-  The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the 
-  <u><strong>central include file</strong></u> that the application programmer is using in 
-  the C source code. This file contains:
-</p>
-<ul>
-  <li>
-	<p><strong>Interrupt Number Definition</strong>: provides interrupt numbers 
-	(IRQn) for all core and device specific exceptions and interrupts.</p>
-	</li>
-	<li>
-	<p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the 
-	actual configuration of the Cortex-Mx processor that is part of the actual 
-	device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that 
-	implements access to processor registers and core peripherals. </p>
-	</li>
-	<li>
-	<p><strong>Device Peripheral Access Layer</strong>: provides definitions
-    for all device peripherals. It contains all data structures and the address 
-	mapping for the device specific peripherals. </p>
-	</li>
-  <li><strong>Access Functions for Peripherals (optional)</strong>: provides
-    additional helper functions for peripherals that are useful for programming 
-	of these peripherals. Access Functions may be provided as inline functions 
-	or can be extern references to a device specific library provided by the 
-	silicon vendor.</li>
-</ul>
-
-
-<h4><strong>Interrupt Number Definition</strong></h4>
-
-<p>To access the device specific interrupts the device.h file defines IRQn 
-numbers for the complete device using a enum typedef as shown below:</p>
-<pre>
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
-  NonMaskableInt_IRQn             = -14,      /*!&lt; 2 Non Maskable Interrupt                              */
-  MemoryManagement_IRQn           = -12,      /*!&lt; 4 Cortex-M3 Memory Management Interrupt               */
-  BusFault_IRQn                   = -11,      /*!&lt; 5 Cortex-M3 Bus Fault Interrupt                       */
-  UsageFault_IRQn                 = -10,      /*!&lt; 6 Cortex-M3 Usage Fault Interrupt                     */
-  SVCall_IRQn                     = -5,       /*!&lt; 11 Cortex-M3 SV Call Interrupt                        */
-  DebugMonitor_IRQn               = -4,       /*!&lt; 12 Cortex-M3 Debug Monitor Interrupt                  */
-  PendSV_IRQn                     = -2,       /*!&lt; 14 Cortex-M3 Pend SV Interrupt                        */
-  SysTick_IRQn                    = -1,       /*!&lt; 15 Cortex-M3 System Tick Interrupt                    */
-/******  STM32 specific Interrupt Numbers ****************************************************************/
-  WWDG_STM_IRQn                   = 0,        /*!&lt; Window WatchDog Interrupt                             */
-  PVD_STM_IRQn                    = 1,        /*!&lt; PVD through EXTI Line detection Interrupt             */
-  :
-  :
-  } IRQn_Type;</pre>
-
-
-<h4>Configuration for core_cm0.h / core_cm3.h</h4>
-<p>
-  The Cortex-Mx core configuration options which are defined for each device implementation. Some 
-  configuration options are reflected in the CMSIS layer using the #define settings described below.
-</p>
-<p>
-  To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
-  Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be 
-  defined before <strong>#include &lt;core_cm0.h&gt;</strong> / <strong>#include &lt;core_cm3.h&gt;</strong>
-  preprocessor command.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">#define</th>
-      <th class="kt" nowrap="nowrap">File</th>
-      <th class="kt" nowrap="nowrap">Value</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
-      <td class="kt">core_cm0.h</td>
-      <td class="kt" nowrap="nowrap">(2)</td>
-      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
-      <td class="kt">core_cm3.h</td>
-      <td class="kt" nowrap="nowrap">(2 ... 8)</td>
-      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
-      <td class="kt">core_cm0.h, core_cm3.h</td>
-      <td class="kt" nowrap="nowrap">(0, 1)</td>
-      <td class="kt">Defines if an MPU is present or not</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
-      <td class="kt">core_cm0.h, core_cm3.h</td>
-      <td class="kt" nowrap="nowrap">(1)</td>
-      <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function 
-		in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em> 
-		file must contain a vendor specific implementation of this function.</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h4>Device Peripheral Access Layer</h4>
-<p>
-  Each peripheral uses a <strong>PERIPHERAL_</strong> prefix to identify peripheral registers 
-  and functions that access this specific peripheral. If more than one peripheral of the same 
-  type exists, identifiers have a postfix (digit or letter). For example:
-</p>
-<ul>
-	<li>UART_Type: defines the generic register layout for all UART channels in a device.</li>
-	<li>UART1: is a pointer to a register structure that refers to a specific UART. 
-      For example UART1-&gt;DR is the data register of UART1.</li>
-	<li>UART_SendChar(UART1, c): is a generic function that works with all UART's in the device. 
-      To communicate the UART that it accesses the first parameter is a pointer to the actual 
-      UART register structure.</li>
-	<li>UART1_SendChar(c): is an UART1 specific implementation (in this case the send function).</li>
-</ul>
-
-<h5>Minimal Requiements</h5>
-<p>
-  To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong> 
-  and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
-</p>
-<ul>
-  <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
-      Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
-      the peripheral registers. For example:
-      <pre>
-typedef struct {
-  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
-  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
-  __IO uint32_t VAL;       /* SysTick Current Value Register      */
-  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
-  } SysTick_Type;</pre>
-  </li>
-
-  <li><strong>Base Address</strong> for each peripheral (in case of multiple peripherals 
-       that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
-    <pre>
-#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */</pre>
-  </li>
-
-  <li><strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use 
-      the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. UART0, 
-      UART1). For Example:
-    <pre>
-#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */</pre>
-  </li>
-</ul>
-
-<p>
-  These definitions allow to access the peripheral registers from user code with simple assignments like:
-</p>
-<pre>SysTick-&gt;CTRL = 0;</pre>
-
-<h5>Optional Features</h5>
-<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
-<ul>
-	<li>#define constants that simplify access to the peripheral registers. 
-	These constant define bit-positions or other specific patterns are that 
-	required for the programming of the peripheral registers. The identifiers 
-	used start with the name of the <strong>PERIPERHAL_</strong>. It is 
-	recommended to use CAPITAL letters for such #define constants.</li>
-	<li>Functions that perform more complex functions with the peripheral (i.e. 
-	status query before a sending register is accessed). Again these function 
-	start with the name of the <strong>PERIPHERAL_</strong>. </li>
-</ul>
-
-<h3>core_cm0.h and core_cm0.c</h3>
-<p>
-  File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does 
-  the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers 
-  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
-  File <b>core_cm0.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
-
-<h3>core_cm3.h and core_cm3.c</h3>
-<p>
-  File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does 
-  the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers 
-  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
-  File <b>core_cm3.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
-
-<h3>startup_<em>device</em></h3>
-<p>
-  A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
-  compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific 
-  interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function 
-  to an dummy handler. Therefore the interrupt handler can be directly used in application software 
-  without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
-</p>
-<p>
-  The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-</p>
-<pre>
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler</pre>
-
-<p>
-  The following exception names are fixed and define the start of the vector table for a Cortex-M3:
-</p>
-<pre>
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler</pre>
-
-<p>
-  In the following examples for device specific interrupts are shown:
-</p>
-<pre>
-; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler         ; Tamper</pre>
-
-<p>
-  Device specific interrupts must have a dummy function that can be overwritten in user code. 
-  Below is an example for this dummy function.
-</p>
-<pre>
-Default_Handler PROC
-                EXPORT WWDG_IRQHandler   [WEAK]
-                EXPORT PVD_IRQHandler    [WEAK]
-                EXPORT TAMPER_IRQHandler [WEAK]
-                :
-                :
-                WWDG_IRQHandler
-                PVD_IRQHandler
-                TAMPER_IRQHandler
-                :
-                :
-                B .
-                ENDP</pre>
-                
-<p>
-  The user application may simply define an interrupt handler function by using the handler name
-  as shown below.
-</p>
-<pre>
-void WWDG_IRQHandler(void)
-{
-  :
-  :
-}</pre>
-
-
-<h3><a name="4"></a>system_<em>device</em>.c</h3>
-<p>
-  A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by 
-  the silicon vendor to match their actual device. As a <strong>minimum requirement</strong> 
-  this file must provide a device specific system configuration function and a global variable 
-  that contains the system frequency. It configures the device and initializes typically the 
-  oscillator (PLL) that is part of the microcontroller device.
-</p>
-<p>
-  The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
-  as a minimum requirement the SystemInit function as shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Function Definition</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
-      <td class="kt">Setup the microcontroller system. Typically this function configures the 
-                     oscillator (PLL) that is part of the microcontroller device. For systems 
-                     with variable clock speed it also updates the variable SystemFrequency.</td>
-    </tr>
-  </tbody>
-</table>
-
-<p>
-  Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> 
-  is the variable <strong>SystemFrequency</strong> which contains the current CPU clock speed shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Variable Definition</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t SystemFrequency</td>
-      <td class="kt">Contains the system frequency (which is the system clock	frequency supplied 
-                     to the SysTick timer and the processor core clock). This variable can be 
-                     used by the user application after the call to the function SystemInit() 
-                     to setup the SysTick timer or configure other parameters. It may also be 
-                     used by debugger to query the frequency of the debug timer or configure 
-                     the trace clock speed.<br><br>
-		                 This variable may also be defined in the <strong>const</strong> space. 
-		                 The compiler must be configured to avoid the removal of this variable in 
-		                 case that the application program is not using it. It is important for 
-		                 debug systems that the variable is physically present in memory so that 
-		                 it can be examined to configure the debugger.</td>
-    </tr>
-  </tbody>
-</table>
-
-<p class="Note">Note</p>
-<ul>
-  <li><p>The above definitions are the minimum requirements for the file <strong>
-	system_</strong><em><strong>device</strong></em><strong>.c</strong>. This 
-	file may export more functions or variables that provide a more flexible 
-	configuration of the microcontroller system.</p>
-  </li>
-</ul>
-
-
-<h2>Core Peripheral Access Layer</h2>
-
-<h3>Cortex-Mx Core Register Access</h3>
-<p>
-  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
-  and provide access to Cortex-Mx core registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Function Definition</th>
-      <th class="kt">Core</th>
-      <th class="kt">Core Register</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">PRIMASK = 0</td>
-      <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE 
-		i</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">PRIMASK = 1</td>
-      <td class="kt">Global Interrupt disable (using the instruction <strong>
-		CPSID i</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">PRIMASK = value</td>
-      <td class="kt">Assign value to Priority Mask Register (using the instruction 
-		<strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">return PRIMASK</td>
-      <td class="kt">Return Priority Mask Register (using the instruction 
-		<strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
-      <td class="kt">M3</td>
-      <td class="kt">FAULTMASK = 0</td>
-      <td class="kt">Global Fault exception and Interrupt enable (using the 
-		instruction <strong>CPSIE 
-		f</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
-      <td class="kt">M3</td>
-      <td class="kt">FAULTMASK = 1</td>
-      <td class="kt">Global Fault exception and Interrupt disable (using the 
-		instruction <strong>CPSID f</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
-      <td class="kt">M3</td>
-      <td class="kt">FAULTMASK = value</td>
-      <td class="kt">Assign value to Fault Mask Register (using the instruction 
-		<strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
-      <td class="kt">M3</td>
-      <td class="kt">return FAULTMASK</td>
-      <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
-      <td class="kt">M3</td>
-      <td class="kt">BASEPRI = value</td>
-      <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
-      <td class="kt">M3</td>
-      <td class="kt">return BASEPRI</td>
-      <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">CONTROL = value</td>
-      <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">return CONTROL</td>
-      <td class="kt">Return Control Register Value (using the instruction
-		<strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">PSP = TopOfProcStack</td>
-      <td class="kt">Set Process Stack Pointer value (using the instruction
-		<strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">return PSP</td>
-      <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">MSP = TopOfMainStack</td>
-      <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">return MSP</td>
-      <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-  </tbody>
-</table>
-
-<h3>Cortex-Mx Instruction Access</h3>
-<p>
-  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
-  generate specific Cortex-Mx instructions. The functions are implemented in the file 
-  <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Name</th>
-      <th class="kt">Core</th>
-      <th class="kt">Generated CPU Instruction</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __WFI (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">WFI</td>
-      <td class="kt">Wait for Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __WFE (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">WFE</td>
-      <td class="kt">Wait for Event</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __SEV (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">SEV</td>
-      <td class="kt">Set Event</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __ISB (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">ISB</td>
-      <td class="kt">Instruction Synchronization Barrier</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __DSB (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">DSB</td>
-      <td class="kt">Data Synchronization Barrier</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __DMB (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">DMB</td>
-      <td class="kt">Data Memory Barrier</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">REV</td>
-      <td class="kt">Reverse byte order in integer value.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">REV16</td>
-      <td class="kt">Reverse byte order in unsigned short value. </td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">REVSH</td>
-      <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
-      <td class="kt">M3</td>
-      <td class="kt">RBIT</td>
-      <td class="kt">Reverse bit order of value</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
-      <td class="kt">M3</td>
-      <td class="kt">LDREXB</td>
-      <td class="kt">Load exclusive byte</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
-      <td class="kt">M3</td>
-      <td class="kt">LDREXH</td>
-      <td class="kt">Load exclusive half-word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
-      <td class="kt">M3</td>
-      <td class="kt">LDREXW</td>
-      <td class="kt">Load exclusive word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
-      <td class="kt">M3</td>
-      <td class="kt">STREXB</td>
-      <td class="kt">Store exclusive byte</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
-      <td class="kt">M3</td>
-      <td class="kt">STREXH</td>
-      <td class="kt">Store exclusive half-word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
-      <td class="kt">M3</td>
-      <td class="kt">STREXW</td>
-      <td class="kt">Store exclusive word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void  __CLREX (void)</td>
-      <td class="kt">M3</td>
-      <td class="kt">CLREX</td>
-      <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h3>NVIC Access Functions</h3>
-<p>
-  The CMSIS provides access to the NVIC via the register interface structure and several helper
-  functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to 
-  identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative 
-  IRQn values are used for processor core exceptions.
-</p>
-<p>
-  For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides 
-  the following enum names.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
-      <th class="kt">Core</th>
-      <th class="kt">IRQn</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">-14</td>
-      <td class="kt">Cortex-Mx Non Maskable Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
-      <td class="kt">M3</td>
-      <td class="kt">-12</td>
-      <td class="kt">Cortex-Mx Memory Management Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
-      <td class="kt">M3</td>
-      <td class="kt">-11</td>
-      <td class="kt">Cortex-Mx Bus Fault Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
-      <td class="kt">M3</td>
-      <td class="kt">-10</td>
-      <td class="kt">Cortex-Mx Usage Fault Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">-5</td>
-      <td class="kt">Cortex-Mx SV Call Interrupt </td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
-      <td class="kt">M3</td>
-      <td class="kt">-4</td>
-      <td class="kt">Cortex-Mx Debug Monitor Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">-2</td>
-      <td class="kt">Cortex-Mx Pend SV Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">-1</td>
-      <td class="kt">Cortex-Mx System Tick Interrupt</td>
-    </tr>
-  </tbody>
-</table>
-
-<p>The following functions simplify the setup of the NVIC.
-The functions are defined as <strong>static inline</strong>.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Core</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping(uint32_t priority_grouping)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">Priority Grouping Value</td>
-      <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ(IRQn_Type IRQn)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Enable IRQn</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ(IRQn_Type IRQn)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Disable IRQn</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Return true (IRQ-Number) if IRQn is pending</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Set IRQn Pending</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Clear IRQn Pending Status</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
-      <td class="kt">M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Return the IRQn of the active interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number, Priority</td>
-      <td class="kt">Set Priority for IRQn<br>
-                     (not threadsafe for Cortex-M0)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">IRQ Number</td>
-      <td class="kt">Get Priority for IRQn</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
-      <td class="kt">M0, M3</td>
-      <td class="kt">(void)</td>
-      <td class="kt">Resets the System</td>
-    </tr>
-  </tbody>
-</table>
-<p class="Note">Note</p>
-<ul>
-  <li><p>The processor exceptions have negative enum values. Device specific interrupts 
-	have positive enum values and start with 0. The values are defined in
-    <b><em>device.h</em></b> file.</p>
-  </li>
-</ul>
-
-
-<h3>SysTick Configuration Function</h3>
-
-<p>The following function is used to configure the SysTick timer and start the 
-SysTick interrupt.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig 
-		(uint32_t ticks)</span></td>
-      <td class="kt">ticks is SysTick counter reload value</td>
-      <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this 
-		call the SysTick timer creates interrupts with the specified time 
-		interval. <br>
-		<br>
-		Return: 0 when successful, 1 on failure.<br>
-		</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h3>Cortex-M3 ITM Debug Access</h3>
-
-<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that 
-provides together with the Serial Viewer Output trace capabilities for the 
-microcontroller system. The ITM has 32 communication channels; two ITM 
-communication channels are used by CMSIS to output the following information:</p>
-<ul>
-	<li>ITM Channel 0: implements the <strong>ITM_putchar</strong> function 
-	which can be used for printf-style output via the debug interface.</li>
-	<li>ITM Channel 31: is reserved for the RTOS kernel and can be used for 
-	kernel awareness debugging.</li>
-</ul>
-<p class="Note">Note</p>
-<ul>
-  <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels 
-	may use the Privileged level for program execution. ITM 
-	channels have 4 groups with 8 channels each, whereby each group can be 
-	configured for access rights in the Unprivileged level. The ITM channel 0 
-	may be therefore enabled for the user task whereas ITM channel 31 may be 
-	accessible only in Privileged level from the RTOS kernel itself.</p>
-  </li>
-</ul>
-
-<p>The prototype of the <strong>ITM_putchar</strong> routine is shown in the 
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void uint32_t ITM_putchar(uint32_t chr)</td>
-      <td class="kt">character to output</td>
-      <td class="kt">The function outputs a character via the ITM channel 0. The 
-		                 function returns when no debugger is connected that has booked the 
-		                 output. It is blocking when a debugger is connected, but the 
-		                 previous character send is not transmitted. <br><br>
-		                 Return: the input character 'chr'.</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<p>
-  Example for the usage of the ITM Channel 31 for RTOS Kernels:
-</p>
-<pre>
-  // check if debugger connected and ITM channel enabled for tracing
-  if ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA) &amp;&amp;
-  (ITM-&gt;TCR &amp; ITM_TCR_ITMENA) &amp;&amp;
-  (ITM-&gt;TER &amp; (1UL &lt;&lt; 31))) {
-    // transmit trace data
-    while (ITM-&gt;PORT31_U32 == 0);
-    ITM-&gt;PORT[31].u8 = task_id;      // id of next task
-    while (ITM-&gt;PORT[31].u32 == 0);
-    ITM-&gt;PORT[31].u32 = task_status; // status information
-  }</pre>
-
-
-<h2><a name="5"></a>CMSIS Example</h2>
-<p>
-  The following section shows a typical example for using the CMSIS layer in user applications.
-</p>
-<pre>
-#include &lt;device.h&gt;                              // file name depends on the device used.
-
-void SysTick_Handler (void)  {                   // SysTick Interrupt Handler
-  ;
-}
-
-void TIM1_UP_IRQHandler (void)  {                // Timer Interrupt Handler
-  ;
-}
-
-void timer1_init(int frequency) {
-                                                 // set up Timer (device specific)
-  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority
-  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt
-}
-
-void main (void) {
-  SystemInit ();
-
-  if (SysTick_Config (SystemFrequency / 1000)) { // Setup SysTick Timer for 1 msec interrupts
-    :                                            // Handle Error
-    :
-    while (1);
-  }
-
-  timer1_init ();                                // device specific timer
-
-  while (1);
-}</pre>
-
-
-</body></html>
\ No newline at end of file
diff --git a/bsp/nuc140/application.c b/bsp/nuc140/application.c
deleted file mode 100644
index 40f1fd4234..0000000000
--- a/bsp/nuc140/application.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-/**
- * @addtogroup LPC1100
- */
-/*@{*/
-#include <rtthread.h>
-
-int rt_application_init()
-{
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/nuc140/board.c b/bsp/nuc140/board.c
deleted file mode 100644
index bb74ead8e9..0000000000
--- a/bsp/nuc140/board.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "board.h"
-#include "uart.h"
-
-#include "CMSIS/CM0/NUC1xx.h"
-#include "CMSIS/CM0/core_cm0.h"
-
-/**
- * @addtogroup NUC100
- */
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler()
-{
-	/* enter interrupt */
-	rt_interrupt_enter();
-
-	rt_tick_increase();
-
-	/* leave interrupt */
-	rt_interrupt_leave();
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init()
-{
-	SystemInit();
-
-	/* init systick */
-	SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1);
-
-	/* set pend exception priority */
-	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
-
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
-#endif
-#ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart1");
-#endif
-}
-/*@}*/
diff --git a/bsp/nuc140/board.h b/bsp/nuc140/board.h
deleted file mode 100644
index a8f6dd9f87..0000000000
--- a/bsp/nuc140/board.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-#endif
diff --git a/bsp/nuc140/project.uvopt b/bsp/nuc140/project.uvopt
deleted file mode 100644
index ad6dbf0745..0000000000
--- a/bsp/nuc140/project.uvopt
+++ /dev/null
@@ -1,2096 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>RT-Thread NUC100</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>1</RunSim>
-        <RunTarget>0</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
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-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
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-        <TabStop>8</TabStop>
-        <ListingPath>.\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
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-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
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-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
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-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
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-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>255</CpuCode>
-      <DllOpt>
-        <SimDllName>SARMCM3.DLL</SimDllName>
-        <SimDllArguments></SimDllArguments>
-        <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
-        <SimDlgDllArguments></SimDlgDllArguments>
-        <TargetDllName>SARMCM3.DLL</TargetDllName>
-        <TargetDllArguments></TargetDllArguments>
-        <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
-        <TargetDlgDllArguments></TargetDlgDllArguments>
-      </DllOpt>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
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-        <sDll></sDll>
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-        <tIfile></tIfile>
-        <pMon>BIN\UL2CM3.DLL</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>DLGDARM</Key>
-          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
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-          <Key>DLGTARM</Key>
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-        <SetRegEntry>
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-          <Name>-UV0704M0Z -O78 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC4000 -FN1 -FF0NUC1xx_128 -FS00 -FL020000</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
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-        <TrcWin>0</TrcWin>
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-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-    </TargetOption>
-  </Target>
-
-  <Group>
-    <GroupName>Startup</GroupName>
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diff --git a/bsp/nuc140/project.uvproj b/bsp/nuc140/project.uvproj
deleted file mode 100644
index 362158e600..0000000000
--- a/bsp/nuc140/project.uvproj
+++ /dev/null
@@ -1,609 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>RT-Thread NUC100</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>Cortex-M0</Device>
-          <Vendor>ARM</Vendor>
-          <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll></FlashDriverDll>
-          <DeviceId>4803</DeviceId>
-          <RegisterFile></RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\objs\</OutputDirectory>
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-            <UserProg1Name></UserProg1Name>
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-          <SVCSIdString></SVCSIdString>
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-          <RVCTOtherData>0</RVCTOtherData>
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-          <SimDllArguments></SimDllArguments>
-          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
-          <SimDlgDllArguments></SimDlgDllArguments>
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-          <TargetDllArguments></TargetDllArguments>
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-          <TargetDlgDllArguments></TargetDlgDllArguments>
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-          <TargetSelection>1</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
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-          <TargetDlls>
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-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>BIN\UL2CM3.DLL</Driver>
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-        </DebugOption>
-        <Utilities>
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-            <RunIndependent>0</RunIndependent>
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-            <Capability>1</Capability>
-            <DriverSelection>4097</DriverSelection>
-          </Flash1>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
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-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
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-            <ldmm>1</ldmm>
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-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>0</hadIROM>
-            <hadIRAM>0</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
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-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
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-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>5</RwSelD>
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-            <NoZi3>0</NoZi3>
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-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
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-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
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-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
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-              <Ocm3>
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-                <StartAddress>0x0</StartAddress>
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-              <Ocm4>
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-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
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-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
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-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </IRAM>
-              <IROM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
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-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x20000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x4000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>3</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath>.;..\..\include;..\..\components\finsh</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>1</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc>--entry Reset_Handler --keep __fsym_* --keep __vsym_*</Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>Startup</GroupName>
-          <Files>
-            <File>
-              <FileName>board.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\board.c</FilePath>
-            </File>
-            <File>
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-              <FileType>1</FileType>
-              <FilePath>.\startup.c</FilePath>
-            </File>
-            <File>
-              <FileName>uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\uart.c</FilePath>
-            </File>
-            <File>
-              <FileName>rtconfig.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>.\rtconfig.h</FilePath>
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-            <File>
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-              <FilePath>.\application.c</FilePath>
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-        <Group>
-          <GroupName>NUC100</GroupName>
-          <Files>
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-              <FileName>fault.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\nuc1xx\fault.c</FilePath>
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-              <FileName>interrupt.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\nuc1xx\interrupt.c</FilePath>
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-            <File>
-              <FileName>stack.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\nuc1xx\stack.c</FilePath>
-            </File>
-            <File>
-              <FileName>context_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\nuc1xx\context_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>fault_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\nuc1xx\fault_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>start_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\nuc1xx\start_rvds.S</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>system_NUC1xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\CMSIS\CM0\system_NUC1xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>core_cm0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\CMSIS\CM0\core_cm0.c</FilePath>
-            </File>
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-        </Group>
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-          <GroupName>Kernel</GroupName>
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-              <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
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-
-</Project>
diff --git a/bsp/nuc140/rtconfig.h b/bsp/nuc140/rtconfig.h
deleted file mode 100644
index 6caa08a7d7..0000000000
--- a/bsp/nuc140/rtconfig.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX		4
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	8
-
-/* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug*/
-/* #define RT_THREAD_DEBUG */
-
-/* Using Hook*/
-/* #define RT_USING_HOOK */
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex*/
-/* #define RT_USING_MUTEX */
-
-/* Using Event*/
-/* #define RT_USING_EVENT */
-
-/* Using MailBox*/
-#define RT_USING_MAILBOX
-
-/* Using Message Queue*/
-/* #define RT_USING_MESSAGEQUEUE */
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-/* #define RT_USING_MEMPOOL */
-
-/* Using Dynamic Heap Management*/
-#define RT_USING_HEAP
-
-/* Using Small MM*/
-#define RT_USING_SMALL_MEM
-#define RT_USING_TINY_SIZE
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-
-/* buffer size for UART reception */
-#define RT_UART_RX_BUFFER_SIZE	64
-
-/* Using UART */
-#define RT_USING_UART
-
-/* SECTION: Console options */
-/* use console for rt_kprintf */
-#define RT_USING_CONSOLE
-/* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	80
-
-/* SECTION: finsh, a C-Express shell */
-/* Using FinSH as Shell*/
-/* #define RT_USING_FINSH */
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-
-#endif
diff --git a/bsp/nuc140/startup.c b/bsp/nuc140/startup.c
deleted file mode 100644
index 0e3c695df3..0000000000
--- a/bsp/nuc140/startup.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#ifdef RT_USING_FINSH
-#include "finsh.h"
-extern void finsh_system_init(void);
-#endif
-
-/**
- * @addtogroup NUC100
- */
-
-/*@{*/
-#if defined(__CC_ARM)
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#elif defined(__GNUC__)
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-#endif
-
-extern int  rt_application_init(void);
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init board */
-	rt_hw_board_init();
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-#ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20004000);
-#elif __ICCARM__
-    rt_system_heap_init(__segment_end("HEAP"), (void*)0x20004000);
-#else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x20004000);
-#endif
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_HOOK /* if the hook is used */
-	/* set idle thread hook */
-	rt_thread_idle_sethook(rt_hw_led_flash);
-#endif
-
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart1");
-#endif
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main (void)
-{
-	rt_uint32_t UNUSED level;
-
-	/* disable interrupt first */
-	level = rt_hw_interrupt_disable();
-
-	/* invoke rtthread_startup */
-	rtthread_startup();
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/nuc140/uart.c b/bsp/nuc140/uart.c
deleted file mode 100644
index a7625b457e..0000000000
--- a/bsp/nuc140/uart.c
+++ /dev/null
@@ -1,226 +0,0 @@
-#include <rthw.h>
-#include <rtthread.h>
-#include "CMSIS/CM0/NUC1xx.h"
-
-/**
- * @addtogroup NUC1xx
- */
-
-/*@{*/
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
-
-#define UART_BAUDRATE   115200
-struct rt_uart_nuc
-{
-	struct rt_device parent;
-
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-void UART0_IRQHandler(void)
-{
-	rt_ubase_t level;
-    struct rt_uart_nuc* uart = &uart_device;
-
-	if (UART0->ISR.RDA_INT == 1)	    /* Receive Data Available */
-	{
-		while (UART0->ISR.RDA_IF == 1)
-		{
-			/* Receive Data Available */
-			uart->rx_buffer[uart->save_index] = UART0->DATA;
-
-			level = rt_hw_interrupt_disable();
-			uart->save_index ++;
-			if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-				uart->save_index = 0;
-			rt_hw_interrupt_enable(level);
-		}
-
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
-                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-            else
-                length = uart->save_index - uart->read_index;
-
-            uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
-
-	return;
-}
-
-static rt_err_t rt_uart_init (rt_device_t dev)
-{
-    /* Multi-Function Pin: Enable UART0:Tx Rx */
-    SYS->GPBMFP.UART0_RX = 1;
-    SYS->GPBMFP.UART0_TX = 1;
-
-    /* Configure GCR to reset UART0 */
-    SYS->IPRSTC2.UART0_RST = 1;
-    SYS->IPRSTC2.UART0_RST = 0;
-
-    /* Enable UART clock */
-    SYSCLK->APBCLK.UART0_EN = 1;
-
-    /* Select UART clock source */
-    SYSCLK->CLKSEL1.UART_S = 0;
-
-    /* Data format */
-    UART0->LCR.WLS = 3;
-
-    /* Configure the baud rate */
-    *((__IO uint32_t *)&UART0->BAUD) = 0x3F000066; /* This setting is for 115200bsp with 12Mhz clock source */
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* open receive data available interrupt */
-		UART0->IER.RDA_IEN = 1;
-
-		/* Enable the UART Interrupt */
-		NVIC_EnableIRQ(UART0_IRQn);
-	}
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		NVIC_DisableIRQ(UART0_IRQn);
-	}
-
-	return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-	rt_uint8_t* ptr;
-	struct rt_uart_nuc *uart = (struct rt_uart_nuc*)dev;
-	RT_ASSERT(uart != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
-
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++;
-			size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-
-	return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-	char *ptr;
-	ptr = (char*)buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* check whether UART is empty */
-				while (UART0->FSR.TX_EMPTY !=1);
-				/* write data */
-				UART0->DATA = '\r';
-			}
-
-			/* check whether UART is empty */
-			while (UART0->FSR.TX_EMPTY !=1);
-			/* write data */
-			UART0->DATA = *ptr;
-
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-	while ( size != 0 )
-	{
-		/* check whether UART is empty */
-		while (UART0->FSR.TX_EMPTY !=1);
-		/* write data */
-		UART0->DATA = *ptr;
-
-		ptr++;
-		size--;
-	}
-	}
-
-	return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-	struct rt_uart_nuc* uart;
-
-	/* get uart device */
-	uart = &uart_device;
-
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
-
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
-
-	rt_device_register(&uart->parent,
-		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
-}
-#endif /* end of UART */
-
-/*@}*/
diff --git a/bsp/nuc140/uart.h b/bsp/nuc140/uart.h
deleted file mode 100644
index c5ca6c70c4..0000000000
--- a/bsp/nuc140/uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UART_H__
-#define __UART_H__
-
-void rt_hw_uart_init(void);
-
-#endif

From 23686587ff344c0b60321fbfb7260bd2927f179c Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 10:39:12 +0800
Subject: [PATCH 32/86] [bsp] Fix frdm-k64f compiling issue

---
 bsp/frdm-k64f/applications/startup.c | 1 -
 bsp/frdm-k64f/board/board.c          | 1 -
 bsp/frdm-k64f/board/board.h          | 2 +-
 bsp/frdm-k64f/board/drv_uart.h       | 2 +-
 bsp/frdm-k64f/board/led.c            | 2 +-
 5 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/bsp/frdm-k64f/applications/startup.c b/bsp/frdm-k64f/applications/startup.c
index b8edf49cf5..bc477c3f76 100644
--- a/bsp/frdm-k64f/applications/startup.c
+++ b/bsp/frdm-k64f/applications/startup.c
@@ -15,7 +15,6 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#include <MK64F12.H>
 #include <board.h>
 
 /**
diff --git a/bsp/frdm-k64f/board/board.c b/bsp/frdm-k64f/board/board.c
index cdb5fcb868..78082ebf5e 100644
--- a/bsp/frdm-k64f/board/board.c
+++ b/bsp/frdm-k64f/board/board.c
@@ -15,7 +15,6 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#include <MK64F12.H>
 #include "board.h"
 
 #include "drv_uart.h"
diff --git a/bsp/frdm-k64f/board/board.h b/bsp/frdm-k64f/board/board.h
index 8290a03733..edb3281199 100644
--- a/bsp/frdm-k64f/board/board.h
+++ b/bsp/frdm-k64f/board/board.h
@@ -16,7 +16,7 @@
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
-#include <MK64F12.H>
+#include <MK64F12.h>
 
 
 /* board configuration */
diff --git a/bsp/frdm-k64f/board/drv_uart.h b/bsp/frdm-k64f/board/drv_uart.h
index fca42557fb..83580972d1 100644
--- a/bsp/frdm-k64f/board/drv_uart.h
+++ b/bsp/frdm-k64f/board/drv_uart.h
@@ -19,7 +19,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
-#include <MK64F12.H>
+#include <MK64F12.h>
 
 #include <drivers/serial.h>
 
diff --git a/bsp/frdm-k64f/board/led.c b/bsp/frdm-k64f/board/led.c
index 1a57dcc005..298ae7c4ad 100644
--- a/bsp/frdm-k64f/board/led.c
+++ b/bsp/frdm-k64f/board/led.c
@@ -12,7 +12,7 @@
  *
  */
 
-#include <MK64F12.H>
+#include <MK64F12.h>
 #include "led.h"
 
 const rt_uint32_t led_mask[] = {1 << 21, 1 << 22, 1 << 26};

From 2604440cebcd04fce1b3f67a3ac61b3c4a15cf8b Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 11:08:38 +0800
Subject: [PATCH 33/86] [bsp] Remove none-released porting

---
 bsp/dev3210/SConscript             |  13 -
 bsp/dev3210/SConstruct             |  29 ---
 bsp/dev3210/application.c          | 119 ---------
 bsp/dev3210/board.c                | 103 --------
 bsp/dev3210/board.h                |  24 --
 bsp/dev3210/dev3210_ram.lds        | 119 ---------
 bsp/dev3210/dw.txt                 |  11 -
 bsp/dev3210/lnn800x480.c           | 102 --------
 bsp/dev3210/newlib_stub.c          |  43 ----
 bsp/dev3210/rtconfig.h             | 169 -------------
 bsp/dev3210/rtconfig.py            |  59 -----
 bsp/dev3210/startup.c              |  92 -------
 bsp/dev3210/uart.c                 | 295 -----------------------
 bsp/dev3210/uart.h                 |  19 --
 bsp/jz47xx/SConscript              |  12 -
 bsp/jz47xx/SConstruct              |  29 ---
 bsp/jz47xx/application.c           |  50 ----
 bsp/jz47xx/board.c                 |  87 -------
 bsp/jz47xx/board.h                 |  23 --
 bsp/jz47xx/jz47xx_ram.lds          | 154 ------------
 bsp/jz47xx/rtconfig.h              | 153 ------------
 bsp/jz47xx/rtconfig.py             |  59 -----
 bsp/jz47xx/startup.c               |  82 -------
 bsp/jz47xx/uart.c                  | 371 -----------------------------
 bsp/jz47xx/uart.h                  |   6 -
 libcpu/mips/jz47xx/cache.c         |  93 --------
 libcpu/mips/jz47xx/cache.h         |  40 ----
 libcpu/mips/jz47xx/cache_gcc.S     |  42 ----
 libcpu/mips/jz47xx/context_gcc.S   | 146 ------------
 libcpu/mips/jz47xx/cpu.c           |  68 ------
 libcpu/mips/jz47xx/exception.c     |  65 -----
 libcpu/mips/jz47xx/interrupt.c     | 133 -----------
 libcpu/mips/jz47xx/jz4740.h        |  55 -----
 libcpu/mips/jz47xx/jz4755.h        |  83 -------
 libcpu/mips/jz47xx/jz47xx.h        | 263 --------------------
 libcpu/mips/jz47xx/mipscfg.c       |  82 -------
 libcpu/mips/jz47xx/stack.c         |  94 --------
 libcpu/mips/jz47xx/start_gcc.S     | 151 ------------
 libcpu/mips/loongson/cache.c       | 188 ---------------
 libcpu/mips/loongson/cache.h       |  47 ----
 libcpu/mips/loongson/cache.inc     |  38 ---
 libcpu/mips/loongson/cache_gcc.S   | 202 ----------------
 libcpu/mips/loongson/context_gcc.S | 141 -----------
 libcpu/mips/loongson/cpu.c         |  50 ----
 libcpu/mips/loongson/exception.c   |  83 -------
 libcpu/mips/loongson/interrupt.c   | 152 ------------
 libcpu/mips/loongson/mipscfg.c     |  82 -------
 libcpu/mips/loongson/soc3210.h     | 172 -------------
 libcpu/mips/loongson/stack.c       |  96 --------
 libcpu/mips/loongson/start_gcc.S   | 130 ----------
 50 files changed, 4919 deletions(-)
 delete mode 100644 bsp/dev3210/SConscript
 delete mode 100644 bsp/dev3210/SConstruct
 delete mode 100644 bsp/dev3210/application.c
 delete mode 100644 bsp/dev3210/board.c
 delete mode 100644 bsp/dev3210/board.h
 delete mode 100644 bsp/dev3210/dev3210_ram.lds
 delete mode 100644 bsp/dev3210/dw.txt
 delete mode 100644 bsp/dev3210/lnn800x480.c
 delete mode 100644 bsp/dev3210/newlib_stub.c
 delete mode 100644 bsp/dev3210/rtconfig.h
 delete mode 100644 bsp/dev3210/rtconfig.py
 delete mode 100644 bsp/dev3210/startup.c
 delete mode 100644 bsp/dev3210/uart.c
 delete mode 100644 bsp/dev3210/uart.h
 delete mode 100644 bsp/jz47xx/SConscript
 delete mode 100644 bsp/jz47xx/SConstruct
 delete mode 100644 bsp/jz47xx/application.c
 delete mode 100644 bsp/jz47xx/board.c
 delete mode 100644 bsp/jz47xx/board.h
 delete mode 100644 bsp/jz47xx/jz47xx_ram.lds
 delete mode 100644 bsp/jz47xx/rtconfig.h
 delete mode 100644 bsp/jz47xx/rtconfig.py
 delete mode 100644 bsp/jz47xx/startup.c
 delete mode 100644 bsp/jz47xx/uart.c
 delete mode 100644 bsp/jz47xx/uart.h
 delete mode 100644 libcpu/mips/jz47xx/cache.c
 delete mode 100644 libcpu/mips/jz47xx/cache.h
 delete mode 100644 libcpu/mips/jz47xx/cache_gcc.S
 delete mode 100644 libcpu/mips/jz47xx/context_gcc.S
 delete mode 100644 libcpu/mips/jz47xx/cpu.c
 delete mode 100644 libcpu/mips/jz47xx/exception.c
 delete mode 100644 libcpu/mips/jz47xx/interrupt.c
 delete mode 100644 libcpu/mips/jz47xx/jz4740.h
 delete mode 100644 libcpu/mips/jz47xx/jz4755.h
 delete mode 100644 libcpu/mips/jz47xx/jz47xx.h
 delete mode 100644 libcpu/mips/jz47xx/mipscfg.c
 delete mode 100644 libcpu/mips/jz47xx/stack.c
 delete mode 100644 libcpu/mips/jz47xx/start_gcc.S
 delete mode 100644 libcpu/mips/loongson/cache.c
 delete mode 100644 libcpu/mips/loongson/cache.h
 delete mode 100644 libcpu/mips/loongson/cache.inc
 delete mode 100644 libcpu/mips/loongson/cache_gcc.S
 delete mode 100644 libcpu/mips/loongson/context_gcc.S
 delete mode 100644 libcpu/mips/loongson/cpu.c
 delete mode 100644 libcpu/mips/loongson/exception.c
 delete mode 100644 libcpu/mips/loongson/interrupt.c
 delete mode 100644 libcpu/mips/loongson/mipscfg.c
 delete mode 100644 libcpu/mips/loongson/soc3210.h
 delete mode 100644 libcpu/mips/loongson/stack.c
 delete mode 100644 libcpu/mips/loongson/start_gcc.S

diff --git a/bsp/dev3210/SConscript b/bsp/dev3210/SConscript
deleted file mode 100644
index 9fd034ba58..0000000000
--- a/bsp/dev3210/SConscript
+++ /dev/null
@@ -1,13 +0,0 @@
-Import('RTT_ROOT')
-from building import *
-
-src_bsp = ['application.c', 'startup.c', 'board.c']
-if GetDepend('RT_USING_NEWLIB'):
-	src_bsp = src_bsp + ['newlib_stub.c']
-
-src_drv = ['uart.c', 'lnn800x480.c']
-src	= File(src_bsp + src_drv)
-CPPPATH = [GetCurrentDir()]
-group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/dev3210/SConstruct b/bsp/dev3210/SConstruct
deleted file mode 100644
index c885c34448..0000000000
--- a/bsp/dev3210/SConstruct
+++ /dev/null
@@ -1,29 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
-
-env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
-
-# make a building
-DoBuilding(TARGET, objs)
diff --git a/bsp/dev3210/application.c b/bsp/dev3210/application.c
deleted file mode 100644
index f5a2caf03c..0000000000
--- a/bsp/dev3210/application.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <soc3210.h>
-
-#ifdef RT_USING_DFS
-#include <dfs.h>
-#include <dfs_elm.h>
-#ifdef RT_USING_DFS_ROMFS
-#include <dfs_romfs.h>
-#endif
-#ifdef RT_USING_DFS_DEVFS
-#include <devfs.h>
-#endif
-#endif
-
-#ifdef RT_USING_RTGUI
-#include <rtgui/rtgui.h>
-#include <rtgui/event.h>
-#include <rtgui/rtgui_server.h>
-#endif
-
-void rt_init_thread_entry(void *parameter)
-{
-	/* Filesystem Initialization */
-#ifdef RT_USING_DFS
-	{
-		/* init the device filesystem */
-		dfs_init();
-
-#if defined(RT_USING_DFS_ROMFS)
-		dfs_romfs_init();
-		if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_ELMFAT)
-		/* init the elm chan FatFs filesystam*/
-		elm_init();
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/sd", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_DEVFS)
-		devfs_init();
-		if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
-			rt_kprintf("Device File System initialized!\n");
-		else
-			rt_kprintf("Device File System initialzation failed!\n");
-
-		#ifdef RT_USING_NEWLIB
-		/* init libc */
-		libc_system_init("uart");
-		rt_kprintf("libc init done\n");
-		#endif
-#endif
-	}
-#endif
-
-#ifdef RT_USING_RTGUI
-	{
-		rtgui_rect_t rect;
-
-		rtgui_system_server_init();
-
-		/* register dock panel */
-		rect.x1 = 0;
-		rect.y1 = 0;
-		rect.x2 = 400;
-		rect.y2 = 480;
-//		rtgui_panel_register("panel", &rect);
-
-		/* register main panel */
-		rect.x1 = 400;
-		rect.y1 = 0;
-		rect.x2 = 800;
-		rect.y2 = 480;
-//		rtgui_panel_register("main", &rect);
-//		rtgui_panel_set_default_focused("main");
-
-		rt_hw_lcd_init();
-	}
-#endif
-}
-
-int rt_application_init(void)
-{
-	rt_thread_t tid;
-
-	/* create initialization thread */
-	tid = rt_thread_create("init",
-							rt_init_thread_entry, RT_NULL,
-							4096, 8, 20);
-	if (tid != RT_NULL)
-		rt_thread_startup(tid);
-
-	return 0;
-}
diff --git a/bsp/dev3210/board.c b/bsp/dev3210/board.c
deleted file mode 100644
index ef8d1bf4d7..0000000000
--- a/bsp/dev3210/board.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "board.h"
-#include "uart.h"
-#include <soc3210.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler(void)
-{
-	unsigned int count;
-
-	count = read_c0_compare();
-	write_c0_compare(count);
-	write_c0_count(0);
-
-	/* increase a OS tick */
-	rt_tick_increase();
-}
-
-/**
- * This function will initial OS timer
- */
-void rt_hw_timer_init(void)
-{
-	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
-	write_c0_count(0);
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init(void)
-{
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
-#endif
-
-#ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart");
-#endif
-
-	/* init operating system timer */
-	rt_hw_timer_init();
-
-	rt_kprintf("current sr: 0x%08x\n", read_c0_status());
-}
-/*@}*/
-
-/* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
-void rt_hw_console_output(const char *ptr)
-{
-	/* stream mode */
-	while (*ptr)
-	{
-		if (*ptr == '\n')
-		{
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
-			/* write data */
-			UART_DAT(UART0_BASE) = '\r';
-		}
-
-		/* FIFO status, contain valid data */
-		while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
-		/* write data */
-		UART_DAT(UART0_BASE) = *ptr;
-
-		ptr ++;
-	}
-}
diff --git a/bsp/dev3210/board.h b/bsp/dev3210/board.h
deleted file mode 100644
index 51c083310f..0000000000
--- a/bsp/dev3210/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2010, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-/* 32M SDRAM */
-#define RT_HW_HEAP_END	(0x80000000 + 32 * 1024 * 1024)
-#define CPU_HZ			(250 * 1000000)
-
-#endif
diff --git a/bsp/dev3210/dev3210_ram.lds b/bsp/dev3210/dev3210_ram.lds
deleted file mode 100644
index 54838f28a5..0000000000
--- a/bsp/dev3210/dev3210_ram.lds
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * File      : jz47xx_ram.lds
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      move the beginning entry to 0x80200000
- */
-
-OUTPUT_ARCH(mips)
-GROUP(-lgcc -lc)
-
-ENTRY(_start)
-SECTIONS
-{
-    . = 0x80200000 ;
-
-    .start :
-    {
-        *(.start);
-    }
-
-    . = ALIGN(4);
-    .text : 
-    {
-         *(.text)
-         *(.text.*)
-         *(.rodata)
-         *(.rodata.*)
-         *(.rodata1)
-         *(.rodata1.*)
-         
-         /* section information for finsh shell */
-         . = ALIGN(4);
-         __fsymtab_start = .;
-         KEEP(*(FSymTab))
-         __fsymtab_end = .;
-         . = ALIGN(4);
-         __vsymtab_start = .;
-         KEEP(*(VSymTab))
-         __vsymtab_end = .;
-         . = ALIGN(4);
-    }
-
-    . = ALIGN(4);
-    .data : 
-    {
-         *(.data)
-         *(.data.*)
-        
-         *(.data1)
-         *(.data1.*)
-         
-         . = ALIGN(8);
-         _gp = ABSOLUTE(.);     /* Base of small data */
-         
-         *(.sdata)
-         *(.sdata.*)
-    }
-
-    .sbss : 
-    {
-        __bss_start = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.dynsbss)
-        *(.scommon)
-    }
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.dynbss)
-        *(COMMON)
-        __bss_end = .;
-    }
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
diff --git a/bsp/dev3210/dw.txt b/bsp/dev3210/dw.txt
deleted file mode 100644
index c30750a432..0000000000
--- a/bsp/dev3210/dw.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# download script for boot loader
-ifaddr dmfe0 192.168.1.100
-load tftp://192.168.1.5/boot_3210 0x80200000
-
-# download script for RT-Thread
-ifaddr dmfe0 192.168.1.100
-load tftp://192.168.1.5/rtthread.elf
-
-# burn script for RT-Thread
-ifaddr dmfe0 192.168.1.100
-devcp tftp://192.168.1.5/rtthread.elf /dev/mtd0
diff --git a/bsp/dev3210/lnn800x480.c b/bsp/dev3210/lnn800x480.c
deleted file mode 100644
index c42b71a280..0000000000
--- a/bsp/dev3210/lnn800x480.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * File      : lnn800x480.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-01     bernard      first version from QiuYi's driver
- */
-
-#include <rtthread.h>
-#include <soc3210.h>
-
-/* LCD driver for 800x480 16bit */
-#define RT_HW_LCD_WIDTH		800
-#define RT_HW_LCD_HEIGHT	480
-
-#define K1BASE				0xA0000000
-#define KSEG1(addr)			((void *)(K1BASE | (rt_uint32_t)(addr)))
-#define HW_FB_ADDR			KSEG1(_rt_framebuffer)
-#define HW_FB_PIXEL(x, y)	*(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * RT_HW_LCD_WIDTH * 2) + x * 2)
-
-ALIGN(4)
-volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
-static struct rt_device_graphic_info _lcd_info;
-
-static rt_err_t rt_lcd_init (rt_device_t dev)
-{
-	/* disable LCD controller */
-	LCD_CTRL = LCD_CTRL & 0xfffe;
-
-	/* set LCD clock */
-	HSB_MISC_REG = (HSB_MISC_REG & 0xFFFD01FF) | 
-		(0x01 << 17) | /* enable LCD */
-		(0x05 << 9);    /* clock */
-
-	LCD_VBARA = (rt_uint32_t)_rt_framebuffer - 0x80000000;
-	LCD_VBARB = (rt_uint32_t)_rt_framebuffer - 0x80000000;
-
-	LCD_HTIM  = 0x12c031f;
-	LCD_VTIM  = 0x11501df;
-	LCD_HVLEN = 0x41e0279;
-
-	LCD_CTRL = 0x8709;
-
-	rt_kprintf("VBARA 0x%08x\n", LCD_VBARA);
-	rt_kprintf("CTRL 0x%08x\n", LCD_CTRL);
-	rt_kprintf("HTIM 0x%08x\n", LCD_HTIM);
-	rt_kprintf("VTIM 0x%08x\n", LCD_VTIM);
-	rt_kprintf("HVLEN 0x%08x\n", LCD_HVLEN);
-	rt_kprintf("HSB_MISC 0x%08x\n", HSB_MISC_REG);
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_lcd_control (rt_device_t dev, rt_uint8_t cmd, void *args)
-{
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:		
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
-
-	return RT_EOK;
-}
-
-void rt_hw_lcd_init(void)
-{
-	rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-	if (lcd == RT_NULL)
-		return; /* no memory yet */
-
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
-	_lcd_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
-	_lcd_info.width = RT_HW_LCD_WIDTH;
-	_lcd_info.height = RT_HW_LCD_HEIGHT;
-
-	/* init device structure */
-	lcd->type = RT_Device_Class_Graphic;
-	lcd->init = rt_lcd_init;
-	lcd->open = RT_NULL;
-	lcd->close = RT_NULL;
-	lcd->control = rt_lcd_control;
-	lcd->user_data = (void*)&_lcd_info;
-	
-	/* register lcd device to RT-Thread */
-	rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
-}
diff --git a/bsp/dev3210/newlib_stub.c b/bsp/dev3210/newlib_stub.c
deleted file mode 100644
index a2fd71b9b8..0000000000
--- a/bsp/dev3210/newlib_stub.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * File      : newlib_stub.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#include <rtthread.h>
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/time.h>
-
-/* some newlib leaked function in CodeSourcery G++ Lite for MIPS version */
-
-int getpid(void)
-{
-	return 0;
-}
-
-int gettimeofday(struct timeval *__tp, void *__tzp)
-{
-	struct timespec tp;
-
-	if (libc_get_time(&tp) == 0)
-	{
-		if (__tp != RT_NULL)
-		{
-			__tp->tv_sec  = tp.tv_sec;
-			__tp->tv_usec = tp.tv_nsec * 1000UL;
-		}
-
-		return tp.tv_sec;
-	}
-
-	return 0;
-}
diff --git a/bsp/dev3210/rtconfig.h b/bsp/dev3210/rtconfig.h
deleted file mode 100644
index cd94adf742..0000000000
--- a/bsp/dev3210/rtconfig.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	10
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	256
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_INTERRUPT_INFO
-
-/* Using Hook */
-#define RT_USING_HOOK
-
-/* Using Software Timer */
-/* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
-
-/* SECTION: IPC */
-/* Using Semaphore */
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex */
-#define RT_USING_MUTEX
-
-/* Using Event */
-#define RT_USING_EVENT
-
-/* Using MailBox */
-#define RT_USING_MAILBOX
-
-/* Using Message Queue */
-#define RT_USING_MESSAGEQUEUE
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management */
-#define RT_USING_HEAP
-
-/* Using SLAB MM */
-#define RT_USING_SLAB
-/* #define RT_USING_SMALL_MEM */
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-#define RT_USING_UART
-#define RT_USING_UART1
-#define RT_UART_RX_BUFFER_SIZE	64
-
-/* SECTION: Console options */
-/* the buffer size of console */
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE	128
-
-/* SECTION: the runtime libc library */
-/* the runtime libc library */
-/* #define RT_USING_NEWLIB */
-/* #define RT_USING_PTHREADS */
-
-/* SECTION: finsh, a C-Express shell */
-/* Using FinSH as Shell*/
-#define RT_USING_FINSH
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_DEVICE_NAME "uart"
-
-/* SECTION: device filesystem support */
-#define RT_USING_DFS
-/* #define RT_USING_DFS_ELMFAT */
-#define RT_USING_DFS_ROMFS
-/* #define RT_USING_DFS_DEVFS */
-
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		4
-/* Using working directory */
-#define DFS_USING_WORKDIR
-
-/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-/* #define RT_USING_LWIP */
-#define RT_LWIP_USING_RT_MEM
-
-/* Enable ICMP protocol*/
-#define RT_LWIP_ICMP
-/* Enable UDP protocol*/
-#define RT_LWIP_UDP
-/* Enable TCP protocol*/
-#define RT_LWIP_TCP
-/* Enable DNS */
-#define RT_LWIP_DNS
-
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
-
-/* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	30
-
-/* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
-#define RT_LWIP_GWADDR3	1
-
-/* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
-
-/* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
-
-/* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
-
-/* SECTION: RT-Thread/GUI */
-// #define RT_USING_RTGUI
-
-#ifdef RT_USING_RTGUI
-
-/* name length of RTGUI object */
-#define RTGUI_NAME_MAX		12
-/* support 16 weight font */
-#define RTGUI_USING_FONT16
-/* support 12 weight font */
-#define RTGUI_USING_FONT12
-/* support Chinese font */
-#define RTGUI_USING_FONTHZ
-/* use DFS as file interface */
-#define RTGUI_USING_DFS_FILERW
-/* use bmp font as Chinese font */
-#define RTGUI_USING_HZ_BMP
-/* use small size in RTGUI */
-#define RTGUI_USING_SMALL_SIZE
-/* use mouse cursor */
-/* #define RTGUI_USING_MOUSE_CURSOR */
-/* default font size in RTGUI */
-#define RTGUI_DEFAULT_FONT_SIZE	16
-
-#endif // RT_USING_RTGUI
-
-#endif
diff --git a/bsp/dev3210/rtconfig.py b/bsp/dev3210/rtconfig.py
deleted file mode 100644
index 10ff9e8fdd..0000000000
--- a/bsp/dev3210/rtconfig.py
+++ /dev/null
@@ -1,59 +0,0 @@
-import os
-
-# CPU options
-ARCH='mips'
-CPU ='loongson'
-
-# toolchains options
-CROSS_TOOL  = 'gcc'
-
-if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
-
-if  CROSS_TOOL == 'gcc':
-	PLATFORM    = 'gcc'
-	EXEC_PATH   = 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_MIPS_ELF/bin'
-elif CROSS_TOOL == 'keil':
-    print '================ERROR============================'
-    print 'Not support keil yet!'
-    print '================================================='
-    exit(0)
-elif CROSS_TOOL == 'iar':
-    print '================ERROR============================'
-    print 'Not support iar yet!'
-    print '================================================='
-    exit(0)
-
-if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-BUILD       = 'debug'
-
-PREFIX = 'mips-sde-elf-'
-CC = PREFIX + 'gcc'
-AS = PREFIX + 'gcc'
-AR = PREFIX + 'ar'
-LINK = PREFIX + 'gcc'
-TARGET_EXT = 'elf'
-SIZE = PREFIX + 'size'
-OBJDUMP = PREFIX + 'objdump'
-OBJCPY = PREFIX + 'objcopy'
-READELF = PREFIX + 'readelf'
-
-DEVICE = ' -mips2'
-CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
-AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
-LFLAGS = DEVICE + ' -EL -Wl,--gc-sections,-Map=rtthread-3210.map,-cref,-u,Reset_Handler -T dev3210_ram.lds'
-
-CPATH = ''
-LPATH = ''
-
-if BUILD == 'debug':
-    CFLAGS += ' -O0 -gdwarf-2'
-    AFLAGS += ' -gdwarf-2'
-else:
-    CFLAGS += ' -O2'
-
-DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
-READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/dev3210/startup.c b/bsp/dev3210/startup.c
deleted file mode 100644
index fe679f468a..0000000000
--- a/bsp/dev3210/startup.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <cache.h>
-
-#include "board.h"
-#define A_K0BASE		0x80000000
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-
-extern int rt_application_init(void);
-
-extern void tlb_refill_exception(void);
-extern void general_exception(void);
-extern void irq_exception(void);
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init cache */
-	rt_hw_cache_init();
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-
-	/* copy vector */
-	memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
-	memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
-	memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
-
-	/* init board */
-	rt_hw_board_init();
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-	rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device(FINSH_DEVICE_NAME);
-#endif
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-/*@}*/
diff --git a/bsp/dev3210/uart.c b/bsp/dev3210/uart.c
deleted file mode 100644
index 9d638a515a..0000000000
--- a/bsp/dev3210/uart.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * File      : uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <soc3210.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
-
-/* UART interrupt enable register value */
-#define UARTIER_IME		(1 << 3)
-#define UARTIER_ILE		(1 << 2)
-#define UARTIER_ITXE	(1 << 1)
-#define UARTIER_IRXE	(1 << 0)
-
-/* UART line control register value */
-#define UARTLCR_DLAB	(1 << 7)
-#define UARTLCR_BCB		(1 << 6)
-#define UARTLCR_SPB		(1 << 5)
-#define UARTLCR_EPS		(1 << 4)
-#define UARTLCR_PE		(1 << 3)
-#define UARTLCR_SB		(1 << 2)
-
-/* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
-
-struct rt_uart_soc3210
-{
-	struct rt_device parent;
-
-	rt_uint32_t hw_base;
-	rt_uint32_t irq;
-
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-static void rt_uart_irqhandler(int irqno, void *param)
-{
-	rt_ubase_t level;
-	rt_uint8_t isr;
-	struct rt_uart_soc3210* uart = &uart_device;
-
-	/* read interrupt status and clear it */
-	isr = UART_IIR(uart->hw_base);
-	isr = (isr >> 1) & 0x3;
-
-	if (isr & 0x02) /* receive data available */
-	{
-		/* Receive Data Available */
-		while (UART_LSR(uart->hw_base) & UARTLSR_DR)
-		{
-			uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
-
-			level = rt_hw_interrupt_disable();
-			uart->save_index ++;
-			if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-				uart->save_index = 0;
-			rt_hw_interrupt_enable(level);
-		}
-
-		/* invoke callback */
-		if (uart->parent.rx_indicate != RT_NULL)
-		{
-			rt_size_t length;
-			if (uart->read_index > uart->save_index)
-				length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-			else
-				length = uart->save_index - uart->read_index;
-
-			uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
-
-	return;
-}
-
-static rt_err_t rt_uart_init (rt_device_t dev)
-{
-	rt_uint32_t baud_div;
-	struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-#if 0
-	/* init UART Hardware */
-	UART_IER(uart->hw_base) = 0; /* clear interrupt */
-	UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
-
-	/* enable UART clock */
-	/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
-	UART_LCR(uart->hw_base) = 0x3;
-
-    /* set baudrate */
-	baud_div = DEV_CLK / 16 / UART_BAUDRATE;
-	UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
-
-	UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
-	UART_LSB(uart->hw_base) = baud_div & 0xff;
-
-	UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
-
-	/* Enable UART unit, enable and clear FIFO */
-	UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
-#endif
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-	struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		UART_IER(uart->hw_base) |= UARTIER_IRXE;
-
-		/* install interrupt */
-		rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
-		rt_hw_interrupt_umask(uart->irq);
-	}
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-	struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
-	}
-
-	return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
-{
-	rt_uint8_t *ptr;
-	struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210 *)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
-
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++;
-			size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-
-	return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
-{
-	char *ptr;
-	struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210 *)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	ptr = (char *)buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* FIFO status, contain valid data */
-				while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-				/* write data */
-				UART_DAT(uart->hw_base) = '\r';
-			}
-
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-			/* write data */
-			UART_DAT(uart->hw_base) = *ptr;
-
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size != 0)
-		{
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-
-			/* write data */
-			UART_DAT(uart->hw_base) = *ptr;
-
-			ptr++;
-			size--;
-		}
-	}
-
-	return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-	struct rt_uart_soc3210 *uart;
-
-	/* get uart device */
-	uart = &uart_device;
-
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
-#if defined(RT_USING_UART1)
-	uart->hw_base = UART0_BASE;
-	uart->irq = IRQ_UART0;
-#elif defined(RT_USING_UART2)
-	uart->hw_base = UART1_BASE;
-	uart->irq = IRQ_UART1;
-#endif
-
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
-
-	rt_device_register(&uart->parent,
-		"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
-}
-#endif /* end of UART */
-
-/*@}*/
diff --git a/bsp/dev3210/uart.h b/bsp/dev3210/uart.h
deleted file mode 100644
index 2cd47d9f8a..0000000000
--- a/bsp/dev3210/uart.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * File      : uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#ifndef __UART_H__
-#define __UART_H__
-
-void rt_hw_uart_init(void);
-
-#endif
diff --git a/bsp/jz47xx/SConscript b/bsp/jz47xx/SConscript
deleted file mode 100644
index a5ba6927af..0000000000
--- a/bsp/jz47xx/SConscript
+++ /dev/null
@@ -1,12 +0,0 @@
-import rtconfig
-Import('RTT_ROOT')
-from building import *
-
-src_bsp   = ['application.c', 'startup.c', 'board.c']
-src_drv   = ['uart.c']
-
-src	= File(src_bsp + src_drv)
-CPPPATH = str(Dir('#'))
-group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/jz47xx/SConstruct b/bsp/jz47xx/SConstruct
deleted file mode 100644
index ca6bdbb5d2..0000000000
--- a/bsp/jz47xx/SConstruct
+++ /dev/null
@@ -1,29 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread-jz47xx.' + rtconfig.TARGET_EXT
-
-env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
-
-# make a building
-DoBuilding(TARGET, objs)
diff --git a/bsp/jz47xx/application.c b/bsp/jz47xx/application.c
deleted file mode 100644
index f4bf3ba65c..0000000000
--- a/bsp/jz47xx/application.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-/**
- * @addtogroup JZ47xx
- */
-/*@{*/
-#include <rtthread.h>
-
-#include <jz4755.h>
-
-static struct rt_thread thread1;
-static rt_uint8_t thread1_stack[1024];
-
-void thread_entry(void* parameter)
-{
-	while (1)
-	{
-		rt_kprintf("IPR: 0x%08x, SR : 0x%08x, CAUSE: 0x%08x\n", INTC_IPR, read_c0_status(), read_c0_cause());
-
-		rt_thread_delay(100);
-	}
-}
-
-int rt_application_init()
-{
-	rt_err_t result;
-
-	result = rt_thread_init(&thread1, "t1",
-		thread_entry, RT_NULL,
-		&thread1_stack[0], sizeof(thread1_stack),
-		200, 10);
-	if (result == RT_EOK)
-		rt_thread_startup(&thread1);
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/jz47xx/board.c b/bsp/jz47xx/board.c
deleted file mode 100644
index c742d32e7d..0000000000
--- a/bsp/jz47xx/board.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "board.h"
-#include "uart.h"
-#include <jz4755.h>
-
-/**
- * @addtogroup JZ47xx
- */
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler(int vector, void* param)
-{
-	/* increase a OS tick */
-	rt_tick_increase();
-
-	/* clear flag */
-	TCU_TFCR = TCU_TFCR_OSTFLAG;
-}
-
-/**
- * This function will initial OS timer
- */
-void rt_hw_timer_init(void)
-{
-	rt_uint32_t val;
-
-	/* disable TCU clock */
-	CPM_CLKGR &= ~CPM_CLKGR_TCU;
-	TCU_TECR = TCU_TECR_OSTCL;
-
-	/* set */
-	OST_DR = RT_TICK_PER_SECOND * 0xcffff;
-	/* clear counter */
-	OST_CNT = 0;
-
-#ifdef RTC_SRC_EXTAL
-	OST_CSR = (val | OST_TCSR_EXT_EN);
-#else
-	OST_CSR = (val | OST_TCSR_PCLK_EN);
-#endif
-
-	TCU_TFCR = TCU_TFCR_OSTFLAG;
-	TCU_TMCR = TCU_TMCR_OSTMCL;
-	TCU_TESR = TCU_TESR_OSTST;
-
-	rt_hw_interrupt_install(IRQ_TCU0, rt_hw_timer_handler, RT_NULL, "tick");
-	rt_hw_interrupt_umask  (IRQ_TCU0);
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init()
-{
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
-#endif
-
-#ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart");
-#endif
-
-	/* init operating system timer */
-	rt_hw_timer_init();
-}
-/*@}*/
diff --git a/bsp/jz47xx/board.h b/bsp/jz47xx/board.h
deleted file mode 100644
index 6218a78fde..0000000000
--- a/bsp/jz47xx/board.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-/* 32M SDRAM */
-#define RT_HW_HEAP_END	(0x80000000 + 32 * 1024 * 1024)
-
-#endif
diff --git a/bsp/jz47xx/jz47xx_ram.lds b/bsp/jz47xx/jz47xx_ram.lds
deleted file mode 100644
index 12c30135c4..0000000000
--- a/bsp/jz47xx/jz47xx_ram.lds
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * File      : jz47xx_ram.lds
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-08-23     bernard      change to jz47xx
- * 2010-09-04     bernard      move the beginning entry to 0x80100000
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-
-MEMORY
-{
-   /* 16M SDRAM */
-   DRAM : ORIGIN = 0x80100000, LENGTH = 0x01000000
-   /* 16K SRAM  */
-   IRAM : ORIGIN = 0x80000000, LENGTH = 0x00004000
-}
-
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x80100000 ;
-
-	.start :
-    {
-        *(.start);
-    } > DRAM
-
-    . = ALIGN(4);
-
-	.text : 
-    {
-     *(.text)
-     *(.text.*)
-     *(.rodata)
-     *(.rodata.*)
-     *(.rodata1)
-     *(.rodata1.*)
-     
-     /* section information for finsh shell */
-     . = ALIGN(4);
-     __fsymtab_start = .;
-     KEEP(*(FSymTab))
-     __fsymtab_end = .;
-     . = ALIGN(4);
-     __vsymtab_start = .;
-     KEEP(*(VSymTab))
-     __vsymtab_end = .;
-     . = ALIGN(4);
-    } > DRAM
-
-    . = ALIGN(4);
-
-	.data : 
-    {
-     *(.data)
-     *(.data.*)
-    
-     *(.data1)
-     *(.data1.*)
-     
-     . = ALIGN(8);
-     _gp = ABSOLUTE(.);     /* Base of small data */
-     
-     *(.sdata)
-     *(.sdata.*)
-    } > DRAM
-
-    . = ALIGN(4);
-	_iramat = .;
-
-	.iram : AT(_iramat)
-    {
-		_iramstart = .;
-        *(.vectors.1);
-        . = 0x100;
-        *(.vectors.2);
-        . = 0x180;
-        *(.vectors.3);
-        . = 0x200;
-        *(.vectors.4);
-        *(.vectors);
-
-        *(.icode);
-        *(.irodata);
-        *(.idata);
-        KEEP(*(.vectors*))
-		_iramend = .;
-    } > IRAM
-    _iramcopy = LOADADDR(.iram);
-
-	.sbss : 
-  	{
-	__bss_start = .;
-		*(.sbss)
-        *(.sbss.*)
-        *(.dynsbss)
-		*(.scommon)
- 	} > DRAM
-
- 	.bss :
- 	{
-		*(.bss)
-        *(.bss.*)
-        *(.dynbss)
-		*(COMMON)
-	__bss_end = .;
- 	} > DRAM
-	
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
diff --git a/bsp/jz47xx/rtconfig.h b/bsp/jz47xx/rtconfig.h
deleted file mode 100644
index 47f7beae7a..0000000000
--- a/bsp/jz47xx/rtconfig.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	10
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	256
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_INTERRUPT_INFO
-
-/* Using Hook */
-#define RT_USING_HOOK
-
-/* Using Software Timer */
-/* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
-
-/* SECTION: IPC */
-/* Using Semaphore */
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex */
-#define RT_USING_MUTEX
-
-/* Using Event */
-#define RT_USING_EVENT
-
-/* Using MailBox */
-#define RT_USING_MAILBOX
-
-/* Using Message Queue */
-#define RT_USING_MESSAGEQUEUE
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management */
-#define RT_USING_HEAP
-
-/* Using Small MM */
-#define RT_USING_SMALL_MEM
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-#define RT_USING_UART
-#define RT_USING_UART1
-#define RT_UART_RX_BUFFER_SIZE	64
-
-/* SECTION: Console options */
-/* the buffer size of console */
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE	128
-
-/* SECTION: finsh, a C-Express shell */
-/* Using FinSH as Shell*/
-#define RT_USING_FINSH
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_DEVICE_NAME "uart"
-
-/* SECTION: device filesystem support */
-/* #define RT_USING_DFS */
-#define RT_USING_DFS_ELMFAT
-
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		4
-
-/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-/* #define RT_USING_LWIP */
-#define RT_LWIP_USING_RT_MEM
-
-/* Enable ICMP protocol*/
-#define RT_LWIP_ICMP
-/* Enable UDP protocol*/
-#define RT_LWIP_UDP
-/* Enable TCP protocol*/
-#define RT_LWIP_TCP
-/* Enable DNS */
-#define RT_LWIP_DNS
-
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
-
-/* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	30
-
-/* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
-#define RT_LWIP_GWADDR3	1
-
-/* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
-
-/* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
-
-/* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
-
-/* SECTION: RT-Thread/GUI */
-/* #define RT_USING_RTGUI */
-
-/* name length of RTGUI object */
-#define RTGUI_NAME_MAX		12
-/* support 16 weight font */
-#define RTGUI_USING_FONT16
-/* support Chinese font */
-#define RTGUI_USING_FONTHZ
-/* use DFS as file interface */
-#define RTGUI_USING_DFS_FILERW
-/* use font file as Chinese font */
-#define RTGUI_USING_HZ_FILE
-/* use small size in RTGUI */
-#define RTGUI_USING_SMALL_SIZE
-/* use mouse cursor */
-/* #define RTGUI_USING_MOUSE_CURSOR */
-/* default font size in RTGUI */
-#define RTGUI_DEFAULT_FONT_SIZE	16
-
-#endif
diff --git a/bsp/jz47xx/rtconfig.py b/bsp/jz47xx/rtconfig.py
deleted file mode 100644
index 9812efffc3..0000000000
--- a/bsp/jz47xx/rtconfig.py
+++ /dev/null
@@ -1,59 +0,0 @@
-import os
-
-# toolchains options
-ARCH     = 'mips'
-CPU      = 'jz47xx'
-
-CROSS_TOOL  = 'gcc'
-
-if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
-
-if  CROSS_TOOL == 'gcc':
-	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= '/home/bernard/workspace/jz/mips-2011.09/bin'
-elif CROSS_TOOL == 'keil':
-    print '================ERROR============================'
-    print 'Not support keil yet!'
-    print '================================================='
-    exit(0)
-elif CROSS_TOOL == 'iar':
-    print '================ERROR============================'
-    print 'Not support iar yet!'
-    print '================================================='
-    exit(0)
-
-if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-	
-BUILD		= 'debug'
-
-# toolchains
-PREFIX = 'mips-sde-elf-'
-CC = PREFIX + 'gcc'
-AS = PREFIX + 'gcc'
-AR = PREFIX + 'ar'
-LINK = PREFIX + 'gcc'
-TARGET_EXT = 'elf'
-SIZE = PREFIX + 'size'
-OBJDUMP = PREFIX + 'objdump'
-OBJCPY = PREFIX + 'objcopy'
-
-DEVICE = ' -mips32 -msoft-float'
-CFLAGS = DEVICE + ' -EL -G0 -DRT_USING_MINILIBC -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
-AFLAGS = ' -c' + DEVICE + ' -EL -x assembler-with-cpp'
-LFLAGS = DEVICE + ' -EL -Wl,--gc-sections,-Map=rtthread-jz47xx.map,-cref,-u,Reset_Handler -T jz47xx_ram.lds'
-
-CPATH = ''
-LPATH = ''
-
-if BUILD == 'debug':
-	CFLAGS += ' -O0 -gdwarf-2'
-	AFLAGS += ' -gdwarf-2'
-else:
-	CFLAGS += ' -O2'
-
-RT_USING_MINILIBC = True
-DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
-COPY_ACTION = 'copy rtthread.bin usbboot\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/jz47xx/startup.c b/bsp/jz47xx/startup.c
deleted file mode 100644
index 67779e996b..0000000000
--- a/bsp/jz47xx/startup.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <cache.h>
-
-#include "board.h"
-
-/**
- * @addtogroup jz47xx
- */
-
-/*@{*/
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-
-extern int rt_application_init(void);
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init cache */
-	rt_hw_cache_init();
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-
-	/* init board */
-	rt_hw_board_init();
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-	rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device(FINSH_DEVICE_NAME);
-#endif
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-/*@}*/
diff --git a/bsp/jz47xx/uart.c b/bsp/jz47xx/uart.c
deleted file mode 100644
index 18edad9d67..0000000000
--- a/bsp/jz47xx/uart.c
+++ /dev/null
@@ -1,371 +0,0 @@
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <jz4755.h>
-
-/**
- * @addtogroup Jz47xx
- */
-
-/*@{*/
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
-
-#define UART_BAUDRATE   57600
-#define DEV_CLK         12000000
-
-/*
- * Define macros for UARTIER
- * UART Interrupt Enable Register
- */
-#define UARTIER_RIE	    (1 << 0)	/* 0: receive fifo "full" interrupt disable */
-#define UARTIER_TIE	    (1 << 1)	/* 0: transmit fifo "empty" interrupt disable */
-#define UARTIER_RLIE	(1 << 2)	/* 0: receive line status interrupt disable */
-#define UARTIER_MIE	    (1 << 3)	/* 0: modem status interrupt disable */
-#define UARTIER_RTIE	(1 << 4)	/* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UARTISR
- * UART Interrupt Status Register
- */
-#define UARTISR_IP	        (1 << 0)	/* 0: interrupt is pending  1: no interrupt */
-#define UARTISR_IID	        (7 << 1)	/* Source of Interrupt */
-#define UARTISR_IID_MSI		(0 << 1)	/* Modem status interrupt */
-#define UARTISR_IID_THRI	(1 << 1)	/* Transmitter holding register empty */
-#define UARTISR_IID_RDI		(2 << 1)	/* Receiver data interrupt */
-#define UARTISR_IID_RLSI	(3 << 1)	/* Receiver line status interrupt */
-#define UARTISR_FFMS	    (3 << 6)	/* FIFO mode select, set when UARTFCR.FE is set to 1 */
-#define UARTISR_FFMS_NO_FIFO	(0 << 6)
-#define UARTISR_FFMS_FIFO_MODE	(3 << 6)
-
-/*
- * Define macros for UARTFCR
- * UART FIFO Control Register
- */
-#define UARTFCR_FE	    (1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
-#define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
-#define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
-#define UARTFCR_DMS	    (1 << 3)	/* 0: disable DMA mode */
-#define UARTFCR_UUE	    (1 << 4)	/* 0: disable UART */
-#define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
-#define UARTFCR_RTRG_1	(0 << 6)
-#define UARTFCR_RTRG_4	(1 << 6)
-#define UARTFCR_RTRG_8	(2 << 6)
-#define UARTFCR_RTRG_15	(3 << 6)
-
-/*
- * Define macros for UARTLCR
- * UART Line Control Register
- */
-#define UARTLCR_WLEN	(3 << 0)	/* word length */
-#define UARTLCR_WLEN_5	(0 << 0)
-#define UARTLCR_WLEN_6	(1 << 0)
-#define UARTLCR_WLEN_7	(2 << 0)
-#define UARTLCR_WLEN_8	(3 << 0)
-#define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8
-					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UARTLCR_PE	    (1 << 3)	/* 0: parity disable */
-#define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */
-#define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */
-#define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */
-#define UARTLCR_DLAB	(1 << 7)	/* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */
-
-/*
- * Define macros for UARTLSR
- * UART Line Status Register
- */
-#define UARTLSR_DR	    (1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */
-#define UARTLSR_ORER	(1 << 1)	/* 0: no overrun error */
-#define UARTLSR_PER	    (1 << 2)	/* 0: no parity error */
-#define UARTLSR_FER	    (1 << 3)	/* 0; no framing error */
-#define UARTLSR_BRK	    (1 << 4)	/* 0: no break detected  1: receive a break signal */
-#define UARTLSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */
-#define UARTLSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */
-#define UARTLSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */
-
-/*
- * Define macros for UARTMCR
- * UART Modem Control Register
- */
-#define UARTMCR_DTR	    (1 << 0)	/* 0: DTR_ ouput high */
-#define UARTMCR_RTS	    (1 << 1)	/* 0: RTS_ output high */
-#define UARTMCR_OUT1	(1 << 2)	/* 0: UARTMSR.RI is set to 0 and RI_ input high */
-#define UARTMCR_OUT2	(1 << 3)	/* 0: UARTMSR.DCD is set to 0 and DCD_ input high */
-#define UARTMCR_LOOP	(1 << 4)	/* 0: normal  1: loopback mode */
-#define UARTMCR_MCE	    (1 << 7)	/* 0: modem function is disable */
-
-/*
- * Define macros for UARTMSR
- * UART Modem Status Register
- */
-#define UARTMSR_DCTS	(1 << 0)	/* 0: no change on CTS_ pin since last read of UARTMSR */
-#define UARTMSR_DDSR	(1 << 1)	/* 0: no change on DSR_ pin since last read of UARTMSR */
-#define UARTMSR_DRI	    (1 << 2)	/* 0: no change on RI_ pin since last read of UARTMSR */
-#define UARTMSR_DDCD	(1 << 3)	/* 0: no change on DCD_ pin since last read of UARTMSR */
-#define UARTMSR_CTS	    (1 << 4)	/* 0: CTS_ pin is high */
-#define UARTMSR_DSR	    (1 << 5)	/* 0: DSR_ pin is high */
-#define UARTMSR_RI	    (1 << 6)	/* 0: RI_ pin is high */
-#define UARTMSR_DCD	    (1 << 7)	/* 0: DCD_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE	(1 << 0)	/* 0: transmitter is in UART mode  1: IrDA mode */
-#define SIRCR_RSIRE	(1 << 1)	/* 0: receiver is in UART mode  1: IrDA mode */
-#define SIRCR_TPWS	(1 << 2)	/* 0: transmit 0 pulse width is 3/16 of bit length
-					   1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TXPL	(1 << 3)	/* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RXPL	(1 << 4)	/* 0: decoder interprets positive pulse as 0 */
-
-struct rt_uart_jz
-{
-	struct rt_device parent;
-
-	rt_uint32_t hw_base;
-	rt_uint32_t irq;
-
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-static void rt_uart_irqhandler(int vector, void* param)
-{
-	rt_ubase_t level, isr;
-    struct rt_uart_jz* uart = param;
-
-    /* read interrupt status and clear it */
-	isr = UART_ISR(uart->hw_base);
-
-	if (isr & UARTISR_IID_RDI)	    /* Receive Data Available */
-	{
-		/* Receive Data Available */
-		while (UART_LSR(uart->hw_base) & UARTLSR_DR)
-		{
-			uart->rx_buffer[uart->save_index] = UART_RDR(uart->hw_base);
-
-			level = rt_hw_interrupt_disable();
-			uart->save_index ++;
-			if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-				uart->save_index = 0;
-			rt_hw_interrupt_enable(level);
-		}
-
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-			rt_size_t length;
-			if (uart->read_index > uart->save_index)
-				length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-			else
-				length = uart->save_index - uart->read_index;
-
-			uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
-
-	return;
-}
-
-static rt_err_t rt_uart_init (rt_device_t dev)
-{
-	rt_uint32_t baud_div;
-	struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	/* Init UART Hardware */
-	UART_IER(uart->hw_base) = 0; /* clear interrupt */
-	UART_FCR(uart->hw_base) = ~UARTFCR_UUE; /* disable UART unite */
-
-	/* Enable UART clock */
-
-	/* Set both receiver and transmitter in UART mode (not SIR) */
-	UART_SIRCR(uart->hw_base) = ~(SIRCR_RSIRE | SIRCR_TSIRE);
-
-	/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
-	UART_LCR(uart->hw_base) = UARTLCR_WLEN_8;
-
-    /* set baudrate */
-	baud_div = DEV_CLK / 16 / UART_BAUDRATE;
-	UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
-
-	UART_DLHR(uart->hw_base) = (baud_div >> 8) & 0xff;
-	UART_DLLR(uart->hw_base) = baud_div & 0xff;
-
-	UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
-
-	/* Enable UART unit, enable and clear FIFO */
-	UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
-
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-	struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
-
-		/* install interrupt */
-		rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, uart, "uart");
-		rt_hw_interrupt_umask(uart->irq);
-	}
-	return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-	struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		UART_IER(uart->hw_base) &= ~(UARTIER_RIE | UARTIER_RTIE);
-	}
-
-	return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-	rt_uint8_t* ptr;
-	struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
-
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++;
-			size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-
-	return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-	char *ptr;
-	struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	ptr = (char*)buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* FIFO status, contain valid data */
-				while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
-				/* write data */
-				UART_TDR(uart->hw_base) = '\r';
-			}
-
-			/* FIFO status, contain valid data */
-			while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
-			/* write data */
-			UART_TDR(uart->hw_base) = *ptr;
-
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while ( size != 0 )
-		{
-			/* FIFO status, contain valid data */
-			while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
-
-			/* write data */
-			UART_TDR(uart->hw_base) = *ptr;
-
-			ptr++;
-			size--;
-		}
-	}
-
-	return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-	struct rt_uart_jz* uart;
-
-	/* get uart device */
-	uart = &uart_device;
-
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
-#if defined(RT_USING_UART0)
-	uart->hw_base = UART0_BASE;
-	uart->irq = IRQ_UART0;
-#elif defined(RT_USING_UART1)
-	uart->hw_base = UART1_BASE;
-	uart->irq = IRQ_UART1;
-#elif defined(RT_USING_UART2)
-	uart->hw_base = UART2_BASE;
-	uart->irq = IRQ_UART2;
-#elif defined(RT_USING_UART3)
-	uart->hw_base = UART3_BASE;
-	uart->irq = IRQ_UART3;
-#endif
-
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
-
-	rt_device_register(&uart->parent,
-		"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
-}
-#endif /* end of UART */
-
-/*@}*/
diff --git a/bsp/jz47xx/uart.h b/bsp/jz47xx/uart.h
deleted file mode 100644
index c5ca6c70c4..0000000000
--- a/bsp/jz47xx/uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UART_H__
-#define __UART_H__
-
-void rt_hw_uart_init(void);
-
-#endif
diff --git a/libcpu/mips/jz47xx/cache.c b/libcpu/mips/jz47xx/cache.c
deleted file mode 100644
index 8a502cdb12..0000000000
--- a/libcpu/mips/jz47xx/cache.c
+++ /dev/null
@@ -1,93 +0,0 @@
-#include "jz47xx.h"
-#include "cache.h"
-
-#define CACHE_SIZE		16*1024
-#define CACHE_LINE_SIZE		32
-#define KSEG0			0x80000000
-
-
-#define K0_TO_K1()				\
-do {						\
-	unsigned long __k0_addr;		\
-						\
-	__asm__ __volatile__(			\
-	"la %0, 1f\n\t"				\
-	"or	%0, %0, %1\n\t"			\
-	"jr	%0\n\t"				\
-	"nop\n\t"				\
-	"1: nop\n"				\
-	: "=&r"(__k0_addr)			\
-	: "r" (0x20000000) );			\
-} while(0)
-
-#define K1_TO_K0()				\
-do {						\
-	unsigned long __k0_addr;		\
-	__asm__ __volatile__(			\
-	"nop;nop;nop;nop;nop;nop;nop\n\t"	\
-	"la %0, 1f\n\t"				\
-	"jr	%0\n\t"				\
-	"nop\n\t"				\
-	"1:	nop\n"				\
-	: "=&r" (__k0_addr));			\
-} while (0)
-
-#define INVALIDATE_BTB()			\
-do {						\
-	unsigned long tmp;			\
-	__asm__ __volatile__(			\
-	".set mips32\n\t"			\
-	"mfc0 %0, $16, 7\n\t"			\
-	"nop\n\t"				\
-	"ori %0, 2\n\t"				\
-	"mtc0 %0, $16, 7\n\t"			\
-	"nop\n\t"				\
-	".set mips2\n\t"			\
-	: "=&r" (tmp));				\
-} while (0)
-
-#define SYNC_WB() __asm__ __volatile__ ("sync")
-
-#define cache_op(op,addr)						\
-	__asm__ __volatile__(						\
-	"	.set	noreorder		\n"			\
-	"	.set	mips32\n\t		\n"			\
-	"	cache	%0, %1			\n"			\
-	"	.set	mips0			\n"			\
-	"	.set	reorder"					\
-	:										\
-	: "i" (op), "m" (*(unsigned char *)(addr)))
-
-void __icache_invalidate_all(void)
-{
-	unsigned int i;
-
-	K0_TO_K1();
-
-	asm volatile (".set noreorder\n"
-		      ".set mips32\n\t"
-		      "mtc0\t$0,$28\n\t"
-		      "mtc0\t$0,$29\n"
-		      ".set mips0\n"
-		      ".set reorder\n");
-	for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-		cache_op(Index_Store_Tag_I, i);
-
-	K1_TO_K0();
-
-	INVALIDATE_BTB();
-}
-
-void __dcache_writeback_all(void)
-{
-	unsigned int i;
-	for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-		cache_op(Index_Writeback_Inv_D, i);
-	SYNC_WB();
-}
-
-void rt_hw_cache_init(void)
-{
-	__dcache_writeback_all();
-	__icache_invalidate_all();
-}
diff --git a/libcpu/mips/jz47xx/cache.h b/libcpu/mips/jz47xx/cache.h
deleted file mode 100644
index d1f3e25493..0000000000
--- a/libcpu/mips/jz47xx/cache.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-void rt_hw_cache_init(void);
-
-#endif
diff --git a/libcpu/mips/jz47xx/cache_gcc.S b/libcpu/mips/jz47xx/cache_gcc.S
deleted file mode 100644
index 76552698d0..0000000000
--- a/libcpu/mips/jz47xx/cache_gcc.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * File      : cache_init.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include "../common/mips.inc"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
-    .text
-    .set noreorder
-
-    .globl  cache_init
-    .ent    cache_init
-cache_init:
-    .set    noreorder
-    mtc0    zero, CP0_TAGLO
-    move    t0, a0                  // cache total size
-    move    t1, a1                  // cache line size
-    li      t2, 0x80000000
-    addu    t3, t0, t2
-
-_cache_init_loop:
-    cache   8, 0(t2)                // icache_index_store_tag
-    cache   9, 0(t2)                // dcache_index_store_tag
-    addu    t2, t1
-    bne     t2, t3, _cache_init_loop
-    nop
-
-    mfc0    t0, CP0_CONFIG
-    li      t1, 0x7
-    not     t1
-    and     t0, t0, t1
-    or      t0, 0x3                 // cacheable, noncoherent, write-back, write allocate
-    mtc0    t0, CP0_CONFIG
-
-    jr      ra
-    nop
-
-    .set    reorder
-    .end    cache_init
diff --git a/libcpu/mips/jz47xx/context_gcc.S b/libcpu/mips/jz47xx/context_gcc.S
deleted file mode 100644
index b480a10219..0000000000
--- a/libcpu/mips/jz47xx/context_gcc.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * File      : context_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Jz4755
- */
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "jz47xx.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-	.globl system_dump
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-
-    mfc0    t0, CP0_CAUSE
-    mfc0    t1, CP0_STATUS
-    and     t0, t1
-
-    andi    t0, 0xff00
-    beqz    t0, spurious_interrupt
-    nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/jz47xx/cpu.c b/libcpu/mips/jz47xx/cpu.c
deleted file mode 100644
index f44a44e020..0000000000
--- a/libcpu/mips/jz47xx/cpu.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-#include <rtthread.h>
-#include <jz4755.h>
-
-/* Watchdog definitions */
-#define	WDT_CLK_PRESCALE_CLK1			( 0x0 << 3)
-#define	WDT_CLK_PRESCALE_CLK4			( 0x1 << 3)
-#define	WDT_CLK_PRESCALE_CLK16			( 0x2 << 3)
-#define	WDT_CLK_PRESCALE_CLK64			( 0x3 << 3)
-#define	WDT_CLK_PRESCALE_CLK256			( 0x4 << 3)
-#define	WDT_CLK_PRESCALE_CLK1024		( 0x5 << 3)
-#define	WDT_CLK_PRESCALE_MASK			( 0x3F << 3)
-
-#define	WDT_CLK_EXTAL					( 0x1 << 2)
-#define	WDT_CLK_RTC						( 0x1 << 1)
-#define	WDT_CLK_PCLK					( 0x1 << 0)
-#define	WDT_CLK_MASK					( 7 )
-
-#define	WDT_ENABLE			( 1 << 0 )
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset()
-{
-	/* open the watch-dog */
-	WDT_TCSR = WDT_CLK_EXTAL;
-	WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
-	WDT_TDR  = 0x03;
-	WDT_TCNT = 0x00;
-	WDT_TCER |= WDT_ENABLE;
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/jz47xx/exception.c b/libcpu/mips/jz47xx/exception.c
deleted file mode 100644
index 6d47d3ca4e..0000000000
--- a/libcpu/mips/jz47xx/exception.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File      : exception.c
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-exception_func_t sys_exception_handlers[33];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > 32) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<33; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/jz47xx/interrupt.c b/libcpu/mips/jz47xx/interrupt.c
deleted file mode 100644
index 0ea4827ee2..0000000000
--- a/libcpu/mips/jz47xx/interrupt.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- */
-#include <rthw.h>
-#include "jz47xx.h"
-
-#define JZ47XX_MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[JZ47XX_MAX_INTR];
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-void rt_hw_interrupt_handler(int vector)
-{
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init()
-{
-	rt_int32_t index;
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-	for (index = 0; index < JZ47XX_MAX_INTR; index ++)
-	{
-		irq_handle_table[index].handler = (rt_isr_handler_t)rt_hw_interrupt_handler;
-	}
-
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-	/* mask interrupt */
-	INTC_IMSR = (1 << vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-	INTC_IMCR = (1 << vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param handler the interrupt service routine to be installed
- * @param param the interrupt service function parameter
- * @param name the interrupt name
- * @return old handler
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector,
-                             rt_isr_handler_t  handler,
-                             void *param,
-                             char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-	if (vector >= 0 && vector < JZ47XX_MAX_INTR)
-	{
-        old_handler = irq_handle_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        irq_handle_table[vector].handler = handler;
-        irq_handle_table[vector].param = param;
-	}
-
-    return old_handler;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int i;
-	rt_isr_handler_t irq_func;
-	static rt_uint32_t pending = 0;
-
-    /* the hardware interrupt */
-	pending |= INTC_IPR;
-	if (!pending) return;
-
-    for (i = JZ47XX_MAX_INTR; i > 0; --i)
-    {
-		if ((pending & (1<<i)))
-        {
-			pending &= ~(1<<i);
-			irq_func = irq_handle_table[i].handler;
-
-			/* do interrupt */
-			(*irq_func)(i, irq_handle_table[i].param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-			irq_handle_table[i].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-			/* ack interrupt */
-			INTC_IPR = (1 << i);
-		}
-	}
-}
-
-/*@}*/
diff --git a/libcpu/mips/jz47xx/jz4740.h b/libcpu/mips/jz47xx/jz4740.h
deleted file mode 100644
index a6fdd34c83..0000000000
--- a/libcpu/mips/jz47xx/jz4740.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include "jz47xx.h"
-
-#define	WDT_BASE	0xB0002000
-
-/* Watchdog */
-#define WDT_TDR		__REG16(WDT_BASE + 0x00)	/* Watchdog Timer Data Register */
-#define WDT_TCER	__REG8(WDT_BASE + 0x04)		/* Watchdog Counter Enable Register */
-#define WDT_TCNT	__REG16(WDT_BASE + 0x08)	/* Watchdog Timer Counter Register */
-#define WDT_TCSR	__REG16(WDT_BASE + 0x0C)	/* Watchdog Timer Control Register */
-
-/* Clock Gate Register Definitions */
-#define CPM_CLKGR_UART1   (1 << 15)
-#define CPM_CLKGR_UHC     (1 << 14)
-#define CPM_CLKGR_IPU     (1 << 13)
-#define CPM_CLKGR_DMAC    (1 << 12)
-#define CPM_CLKGR_UDC     (1 << 11)
-#define CPM_CLKGR_LCD     (1 << 10)
-#define CPM_CLKGR_CIM     (1 << 9)
-#define CPM_CLKGR_SADC    (1 << 8)
-#define CPM_CLKGR_MSC     (1 << 7)
-#define CPM_CLKGR_AIC1    (1 << 6)
-#define CPM_CLKGR_AIC2    (1 << 5)
-#define CPM_CLKGR_SSI     (1 << 4)
-#define CPM_CLKGR_I2C     (1 << 3)
-#define CPM_CLKGR_RTC     (1 << 2)
-#define CPM_CLKGR_TCU     (1 << 1)
-#define CPM_CLKGR_UART0   (1 << 0)
-
-/* Interrupt Definitions */
-#define IRQ_I2C		1
-#define IRQ_UHC		3
-#define IRQ_UART0	9
-#define IRQ_SADC	12
-#define IRQ_MSC		14
-#define IRQ_RTC		15
-#define IRQ_SSI		16
-#define IRQ_CIM		17
-#define IRQ_AIC		18
-#define IRQ_ETH		19
-#define IRQ_DMAC	20
-#define IRQ_TCU2	21
-#define IRQ_TCU1	22
-#define IRQ_TCU0	23
-#define IRQ_UDC		24
-#define IRQ_GPIO3	25
-#define IRQ_GPIO2	26
-#define IRQ_GPIO1	27
-#define IRQ_GPIO0	28
-#define IRQ_IPU		29
-#define IRQ_LCD		30
-
-#endif
diff --git a/libcpu/mips/jz47xx/jz4755.h b/libcpu/mips/jz47xx/jz4755.h
deleted file mode 100644
index 847f657f4e..0000000000
--- a/libcpu/mips/jz47xx/jz4755.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef __JZ4755_H__
-#define __JZ4755_H__
-
-#include "jz47xx.h"
-
-#define	WDT_BASE	0xB0002000
-#define	OST_BASE	0xB00020e0
-
-/* Watchdog */
-#define WDT_TDR		__REG16(WDT_BASE + 0x00)	/* Watchdog Timer Data Register */
-#define WDT_TCER	__REG8(WDT_BASE + 0x04)		/* Watchdog Counter Enable Register */
-#define WDT_TCNT	__REG16(WDT_BASE + 0x08)	/* Watchdog Timer Counter Register */
-#define WDT_TCSR	__REG16(WDT_BASE + 0x0C)	/* Watchdog Timer Control Register */
-
-/* OS Timer */
-#define OST_DR		__REG32(OST_BASE + 0x00)	/* OS Timer Data Register */
-#define OST_CNT		__REG32(OST_BASE + 0x08)	/* OS Timer Counter Register */
-#define OST_CSR		__REG16(OST_BASE + 0x0C)	/* OS Timer Control Register */
-
-/* OST Register Definitions */
-#define OST_TCSR_EXT_EN		( 0x1 << 2)
-#define OST_TCSR_RTC_EN		( 0x1 << 1)
-#define OST_TCSR_PCLK_EN	( 0x1 << 0)
-
-/* Clock Gate Register Definitions */
-#define CPM_CLKGR_AUX_CPU      ( 1 << 24 )
-#define CPM_CLKGR_AHB1         ( 1 << 23 )
-#define CPM_CLKGR_IDCT         ( 1 << 22 )
-#define CPM_CLKGR_DB           ( 1 << 21 )
-#define CPM_CLKGR_ME           ( 1 << 20 )
-#define CPM_CLKGR_MC           ( 1 << 19 )
-#define CPM_CLKGR_TVE          ( 1 << 18 )
-#define CPM_CLKGR_TSSI         ( 1 << 17 )
-#define CPM_CLKGR_MSC1         ( 1 << 16 )
-#define CPM_CLKGR_UART2        ( 1 << 15 )
-#define CPM_CLKGR_UART1        ( 1 << 14 )
-#define CPM_CLKGR_IPU          ( 1 << 13 )
-#define CPM_CLKGR_DMAC         ( 1 << 12 )
-#define CPM_CLKGR_BCH          ( 1 << 11 )
-#define CPM_CLKGR_UDC          ( 1 << 10 )
-#define CPM_CLKGR_LCD          ( 1 << 9 )
-#define CPM_CLKGR_CIM          ( 1 << 8 )
-#define CPM_CLKGR_SADC         ( 1 << 7 )
-#define CPM_CLKGR_MSC0         ( 1 << 6 )
-#define CPM_CLKGR_AIC          ( 1 << 5 )
-#define CPM_CLKGR_SSI1         ( 1 << 4 )
-#define CPM_CLKGR_I2C          ( 1 << 3 )
-#define CPM_CLKGR_RTC          ( 1 << 2 )
-#define CPM_CLKGR_TCU          ( 1 << 1 )
-#define CPM_CLKGR_UART0        ( 1 << 0 )
-
-/* Interrupt Definitions */
-#define IRQ_ETH		0
-#define IRQ_SFT		4
-#define IRQ_I2C		5
-#define IRQ_RTC		6
-#define IRQ_UART2	7
-#define IRQ_UART1	8
-#define IRQ_UART0	9
-#define IRQ_AIC		10
-#define IRQ_GPIO5	11
-#define IRQ_GPIO4	12
-#define IRQ_GPIO3	13
-#define IRQ_GPIO2	14
-#define IRQ_GPIO1	15
-#define IRQ_GPIO0	16
-#define IRQ_BCH		17
-#define IRQ_SADC	18
-#define IRQ_CIM		19
-#define IRQ_TSSI	20
-#define IRQ_TCU2	21
-#define IRQ_TCU1	22
-#define IRQ_TCU0	23
-#define IRQ_MSC1	24
-#define IRQ_MSC0	25
-#define IRQ_SSI		26
-#define IRQ_UDC		27
-#define IRQ_DMA1	28		/* Used for DMA channel 4-7 */
-#define IRQ_DMA0	29		/* Used for DMA channel 0-3 */
-#define IRQ_IPU		30
-#define IRQ_LCD		31
-
-#endif
diff --git a/libcpu/mips/jz47xx/jz47xx.h b/libcpu/mips/jz47xx/jz47xx.h
deleted file mode 100644
index 3d1b7cee1f..0000000000
--- a/libcpu/mips/jz47xx/jz47xx.h
+++ /dev/null
@@ -1,263 +0,0 @@
-#ifndef __JZ47XX_H__
-#define __JZ47XX_H__
-
-#include "../common/mipsregs.h"
-
-#define __REG8(addr)	*((volatile unsigned char *)(addr))
-#define __REG16(addr)	*((volatile unsigned short *)(addr))
-#define __REG32(addr)	*((volatile unsigned int *)(addr))
-
-#define	HARB_BASE	0xB3000000
-#define	EMC_BASE	0xB3010000
-#define	DMAC_BASE	0xB3020000
-#define	UHC_BASE	0xB3030000
-#define	UDC_BASE	0xB3040000
-#define	LCD_BASE	0xB3050000
-#define	CIM_BASE	0xB3060000
-#define	ETH_BASE	0xB3100000
-#define	NBM_BASE	0xB3F00000
-
-#define	CPM_BASE	0xB0000000
-#define	INTC_BASE	0xB0001000
-#define TCU_BASE	0xB0002000
-#define	RTC_BASE	0xB0003000
-#define	GPIO_BASE	0xB0010000
-#define	AIC_BASE	0xB0020000
-#define	MSC_BASE	0xB0021000
-#define	UART0_BASE	0xB0030000
-#define	UART1_BASE	0xB0031000
-#define	UART2_BASE	0xB0032000
-#define	UART3_BASE	0xB0033000
-#define	FIR_BASE	0xB0040000
-#define	SCC_BASE	0xB0041000
-#define	SCC0_BASE	0xB0041000
-#define	I2C_BASE	0xB0042000
-#define	SSI_BASE	0xB0043000
-#define	SCC1_BASE	0xB0044000
-#define	PWM0_BASE	0xB0050000
-#define	PWM1_BASE	0xB0051000
-#define	DES_BASE	0xB0060000
-#define	UPRT_BASE	0xB0061000
-#define KBC_BASE	0xB0062000
-
-/* CPM Register */
-#define CPM_CPCCR			__REG32(CPM_BASE + 0x00)	/* Clock Control Register */
-#define CPM_LCR				__REG32(CPM_BASE + 0x04)	/* Low Power Control Register */
-#define CPM_RSR				__REG32(CPM_BASE + 0x08)	/* Reset Status Register */
-#define CPM_CPPCR			__REG32(CPM_BASE + 0x10)	/* PLL Control Register */
-#define CPM_CPPSR			__REG32(CPM_BASE + 0x14)	/* PLL Switch and Status Register */
-#define CPM_CLKGR			__REG32(CPM_BASE + 0x20)	/* Clock Gate Register */
-#define CPM_OPCR			__REG32(CPM_BASE + 0x24)	/* Osillator and Power Control Register */
-#define CPM_I2SCDR			__REG32(CPM_BASE + 0x60)	/* I2S Device Clock Divider Register */
-#define CPM_LPCDR			__REG32(CPM_BASE + 0x64)	/* LCD Pixel Clock Divider Register */
-#define CPM_MSCCDR			__REG32(CPM_BASE + 0x68)	/* MSC Clock Divider Register */
-#define CPM_SSICDR			__REG32(CPM_BASE + 0x74)	/* SSI Clock Divider Register */
-#define CPM_CIMCDR			__REG32(CPM_BASE + 0x7C)	/* CIM MCLK Clock Divider Register */
-
-/* Interrupt Controller Regester */
-#define INTC_ISR			__REG32(INTC_BASE + 0x00)
-#define INTC_IMR			__REG32(INTC_BASE + 0x04)
-#define INTC_IMSR			__REG32(INTC_BASE + 0x08)
-#define INTC_IMCR			__REG32(INTC_BASE + 0x0c)
-#define INTC_IPR			__REG32(INTC_BASE + 0x10)
-
-/* TCU Register */
-#define TCU_TSTR			__REG32(TCU_BASE + 0xF0)
-#define TCU_TSTSR			__REG32(TCU_BASE + 0xF4)
-#define TCU_TSTCR			__REG32(TCU_BASE + 0xF8)
-#define TCU_TSR				__REG32(TCU_BASE + 0x1C)
-#define TCU_TSSR			__REG32(TCU_BASE + 0x2C)
-#define TCU_TSCR			__REG32(TCU_BASE + 0x3C)
-#define TCU_TER				__REG32(TCU_BASE + 0x10)
-#define TCU_TESR			__REG32(TCU_BASE + 0x14)
-#define TCU_TECR			__REG32(TCU_BASE + 0x18)
-#define TCU_TFR				__REG32(TCU_BASE + 0x20)
-#define TCU_TFSR			__REG32(TCU_BASE + 0x24)
-#define TCU_TFCR			__REG32(TCU_BASE + 0x28)
-#define TCU_TMR				__REG32(TCU_BASE + 0x30)
-#define TCU_TMSR			__REG32(TCU_BASE + 0x34)
-#define TCU_TMCR			__REG32(TCU_BASE + 0x38)
-#define TCU_TDFR0_OFFSET	0x40
-#define TCU_TDFR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
-#define TCU_TDHR0_OFFSET	0x44
-#define TCU_TDHR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
-#define TCU_TCNT0_OFFSET	0x48
-#define TCU_TCNT(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
-#define TCU_TCSR0_OFFSET	0x4C
-#define TCU_TCSR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
-
-/* TCU Register Definitions */
-#define TCU_TCSR_PWM_SD         (1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
-#define TCU_TCSR_PWM_EN         (1 << 7)
-#define TCU_TCSR_PRESCALE_BIT   3
-#define TCU_TCSR_PRESCALE_MASK  (0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1      (0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4      (0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16     (0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64     (0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256    (0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024   (0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN         (1 << 2)
-#define TCU_TCSR_RTC_EN         (1 << 1)
-#define TCU_TCSR_PCK_EN         (1 << 0)
-
-#define TCU_TER_OSTEN   (1 << 15)
-#define TCU_TER_TCEN5   (1 << 5)
-#define TCU_TER_TCEN4   (1 << 4)
-#define TCU_TER_TCEN3   (1 << 3)
-#define TCU_TER_TCEN2   (1 << 2)
-#define TCU_TER_TCEN1   (1 << 1)
-#define TCU_TER_TCEN0   (1 << 0)
-
-#define TCU_TESR_OSTST  (1 << 15)
-#define TCU_TESR_TCST5  (1 << 5)
-#define TCU_TESR_TCST4  (1 << 4)
-#define TCU_TESR_TCST3  (1 << 3)
-#define TCU_TESR_TCST2  (1 << 2)
-#define TCU_TESR_TCST1  (1 << 1)
-#define TCU_TESR_TCST0  (1 << 0)
-
-#define TCU_TECR_OSTCL  (1 << 15)
-#define TCU_TECR_TCCL5  (1 << 5)
-#define TCU_TECR_TCCL4  (1 << 4)
-#define TCU_TECR_TCCL3  (1 << 3)
-#define TCU_TECR_TCCL2  (1 << 2)
-#define TCU_TECR_TCCL1  (1 << 1)
-#define TCU_TECR_TCCL0  (1 << 0)
-
-#define TCU_TFR_HFLAG5  (1 << 21)
-#define TCU_TFR_HFLAG4  (1 << 20)
-#define TCU_TFR_HFLAG3  (1 << 19)
-#define TCU_TFR_HFLAG2  (1 << 18)
-#define TCU_TFR_HFLAG1  (1 << 17)
-#define TCU_TFR_HFLAG0  (1 << 16)
-#define TCU_TFR_FFLAG5  (1 << 5)
-#define TCU_TFR_FFLAG4  (1 << 4)
-#define TCU_TFR_FFLAG3  (1 << 3)
-#define TCU_TFR_FFLAG2  (1 << 2)
-#define TCU_TFR_FFLAG1  (1 << 1)
-#define TCU_TFR_FFLAG0  (1 << 0)
-
-#define TCU_TFSR_HFLAG5 (1 << 21)
-#define TCU_TFSR_HFLAG4 (1 << 20)
-#define TCU_TFSR_HFLAG3 (1 << 19)
-#define TCU_TFSR_HFLAG2 (1 << 18)
-#define TCU_TFSR_HFLAG1 (1 << 17)
-#define TCU_TFSR_HFLAG0 (1 << 16)
-#define TCU_TFSR_OSTFLAG (1 << 15)
-#define TCU_TFSR_FFLAG5 (1 << 5)
-#define TCU_TFSR_FFLAG4 (1 << 4)
-#define TCU_TFSR_FFLAG3 (1 << 3)
-#define TCU_TFSR_FFLAG2 (1 << 2)
-#define TCU_TFSR_FFLAG1 (1 << 1)
-#define TCU_TFSR_FFLAG0 (1 << 0)
-
-#define TCU_TFCR_HFLAG5 (1 << 21)
-#define TCU_TFCR_HFLAG4 (1 << 20)
-#define TCU_TFCR_HFLAG3 (1 << 19)
-#define TCU_TFCR_HFLAG2 (1 << 18)
-#define TCU_TFCR_HFLAG1 (1 << 17)
-#define TCU_TFCR_HFLAG0 (1 << 16)
-#define TCU_TFCR_OSTFLAG (1 << 15)
-#define TCU_TFCR_FFLAG5 (1 << 5)
-#define TCU_TFCR_FFLAG4 (1 << 4)
-#define TCU_TFCR_FFLAG3 (1 << 3)
-#define TCU_TFCR_FFLAG2 (1 << 2)
-#define TCU_TFCR_FFLAG1 (1 << 1)
-#define TCU_TFCR_FFLAG0 (1 << 0)
-
-#define TCU_TMR_HMASK5  (1 << 21)
-#define TCU_TMR_HMASK4  (1 << 20)
-#define TCU_TMR_HMASK3  (1 << 19)
-#define TCU_TMR_HMASK2  (1 << 18)
-#define TCU_TMR_HMASK1  (1 << 17)
-#define TCU_TMR_HMASK0  (1 << 16)
-#define TCU_TMR_OSTMASK (1 << 15)
-#define TCU_TMR_FMASK5  (1 << 5)
-#define TCU_TMR_FMASK4  (1 << 4)
-#define TCU_TMR_FMASK3  (1 << 3)
-#define TCU_TMR_FMASK2  (1 << 2)
-#define TCU_TMR_FMASK1  (1 << 1)
-#define TCU_TMR_FMASK0  (1 << 0)
-
-#define TCU_TMSR_HMST5  (1 << 21)
-#define TCU_TMSR_HMST4  (1 << 20)
-#define TCU_TMSR_HMST3  (1 << 19)
-#define TCU_TMSR_HMST2  (1 << 18)
-#define TCU_TMSR_HMST1  (1 << 17)
-#define TCU_TMSR_HMST0  (1 << 16)
-#define TCU_TMSR_OSTMST (1 << 15)
-#define TCU_TMSR_FMST5  (1 << 5)
-#define TCU_TMSR_FMST4  (1 << 4)
-#define TCU_TMSR_FMST3  (1 << 3)
-#define TCU_TMSR_FMST2  (1 << 2)
-#define TCU_TMSR_FMST1  (1 << 1)
-#define TCU_TMSR_FMST0  (1 << 0)
-
-#define TCU_TMCR_HMCL5  (1 << 21)
-#define TCU_TMCR_HMCL4  (1 << 20)
-#define TCU_TMCR_HMCL3  (1 << 19)
-#define TCU_TMCR_HMCL2  (1 << 18)
-#define TCU_TMCR_HMCL1  (1 << 17)
-#define TCU_TMCR_HMCL0  (1 << 16)
-#define TCU_TMCR_OSTMCL (1 << 15)
-#define TCU_TMCR_FMCL5  (1 << 5)
-#define TCU_TMCR_FMCL4  (1 << 4)
-#define TCU_TMCR_FMCL3  (1 << 3)
-#define TCU_TMCR_FMCL2  (1 << 2)
-#define TCU_TMCR_FMCL1  (1 << 1)
-#define TCU_TMCR_FMCL0  (1 << 0)
-
-#define TCU_TSR_WDTS    (1 << 16)
-#define TCU_TSR_STOP5   (1 << 5)
-#define TCU_TSR_STOP4   (1 << 4)
-#define TCU_TSR_STOP3   (1 << 3)
-#define TCU_TSR_STOP2   (1 << 2)
-#define TCU_TSR_STOP1   (1 << 1)
-#define TCU_TSR_STOP0   (1 << 0)
-
-#define TCU_TSSR_WDTSS  (1 << 16)
-#define TCU_TSSR_STPS5  (1 << 5)
-#define TCU_TSSR_STPS4  (1 << 4)
-#define TCU_TSSR_STPS3  (1 << 3)
-#define TCU_TSSR_STPS2  (1 << 2)
-#define TCU_TSSR_STPS1  (1 << 1)
-#define TCU_TSSR_STPS0  (1 << 0)
-
-#define TCU_TSSR_WDTSC  (1 << 16)
-#define TCU_TSSR_STPC5  (1 << 5)
-#define TCU_TSSR_STPC4  (1 << 4)
-#define TCU_TSSR_STPC3  (1 << 3)
-#define TCU_TSSR_STPC2  (1 << 2)
-#define TCU_TSSR_STPC1  (1 << 1)
-#define TCU_TSSR_STPC0  (1 << 0)
-
-#define OST_TCSR_CNT_MD                  ( 1 << 15 )
-#define OST_TCSR_PWM_SHUT_ABRUPT         ( 1 << 9 )
-#define OST_TCSR_PRESCALE1               ( 0x0 << 3)
-#define OST_TCSR_PRESCALE4               ( 0x1 << 3)
-#define OST_TCSR_PRESCALE16              ( 0x2 << 3)
-#define OST_TCSR_PRESCALE64              ( 0x3 << 3)
-#define OST_TCSR_PRESCALE256             ( 0x4 << 3)
-#define OST_TCSR_PRESCALE1024            ( 0x5 << 3)
-
-/* Uart Register */
-#define UART_RDR(base)		__REG8((base) + 0x00)	/* R  8b H'xx */
-#define UART_TDR(base)		__REG8((base) + 0x00)	/* W  8b H'xx */
-#define UART_DLLR(base)		__REG8((base) + 0x00)	/* RW 8b H'00 */
-#define UART_DLHR(base)		__REG8((base) + 0x04)	/* RW 8b H'00 */
-#define UART_IER(base)		__REG8((base) + 0x04)	/* RW 8b H'00 */
-#define UART_ISR(base)		__REG8((base) + 0x08)	/* R  8b H'01 */
-#define UART_FCR(base)		__REG8((base) + 0x08)	/* W  8b H'00 */
-#define UART_LCR(base)		__REG8((base) + 0x0C)	/* RW 8b H'00 */
-#define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
-#define UART_LSR(base)		__REG8((base) + 0x14)	/* R  8b H'00 */
-#define UART_MSR(base)		__REG8((base) + 0x18)	/* R  8b H'00 */
-#define UART_SPR(base)		__REG8((base) + 0x1C)	/* RW 8b H'00 */
-#define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
-#define UART_SIRCR(base)	__REG8((base) + 0x20)	/* RW 8b H'00 */
-
-#define SYSTEM_STACK          0x80003fe8		/* the kernel system stack address */
-
-#endif
diff --git a/libcpu/mips/jz47xx/mipscfg.c b/libcpu/mips/jz47xx/mipscfg.c
deleted file mode 100644
index 8a96f458ab..0000000000
--- a/libcpu/mips/jz47xx/mipscfg.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}
diff --git a/libcpu/mips/jz47xx/stack.c b/libcpu/mips/jz47xx/stack.c
deleted file mode 100644
index 1d408bbff1..0000000000
--- a/libcpu/mips/jz47xx/stack.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-07-07     Bernard      porting to Jz47xx
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x0403;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/mips/jz47xx/start_gcc.S b/libcpu/mips/jz47xx/start_gcc.S
deleted file mode 100644
index 418a68d0f8..0000000000
--- a/libcpu/mips/jz47xx/start_gcc.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * File      : start_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "jz47xx.h"
-
-    .section ".start", "ax"
-    .set noreorder
-
-    /* the program entry */
-    .globl  _start
-_start:
-    .set    noreorder
-    la      ra, _start
-
-    li	    t1, 0x00800000
-    mtc0    t1, CP0_CAUSE
-
-    /* init cp0 registers. */
-    li	    t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
-    mtc0    t0, CP0_STATUS
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-    /* init caches, assumes a 4way * 128set * 32byte I/D cache */
-    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
-    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
-    li      t0, 3            /* enable cache for kseg0 accesses */
-    mtc0    t0, CP0_CONFIG    /* CONFIG reg */
-    la      t0, 0x80000000   /* an idx op should use an unmappable address */
-    ori     t1, t0, 0x4000   /* 16kB cache */
-
-_cache_loop:
-    cache   0x8, 0(t0)       /* index store icache tag */
-    cache   0x9, 0(t0)       /* index store dcache tag */
-    bne     t0, t1, _cache_loop
-    addiu   t0, t0, 0x20     /* 32 bytes per cache line */
-    nop
-
-    /* invalidate BTB */
-    mfc0    t0, CP0_CONFIG
-    nop
-    ori     t0, 2
-    mtc0    t0, CP0_CONFIG
-    nop
-
-    /* copy IRAM section */
-    la     t0, _iramcopy
-    la     t1, _iramstart
-    la     t2, _iramend
-_iram_loop:
-    lw     t3, 0(t0)
-    sw     t3, 0(t1)
-    addiu  t1, 4
-    bne    t1, t2, _iram_loop
-    addiu  t0, 4
-
-    /* clear bss */
-    la      t0, __bss_start
-    la      t1, __bss_end
-_clr_bss_loop:
-    sw      zero, 0(t0)
-    bne     t0, t1, _clr_bss_loop
-    addiu   t0, t0, 4
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder
-
-    .globl  cp0_get_cause
-cp0_get_cause:
-    mfc0    v0, CP0_CAUSE
-    jr      ra
-    nop
-
-    .globl  cp0_get_status
-cp0_get_status:
-    mfc0    v0, CP0_STATUS
-    jr      ra
-    nop
-
-    .globl  cp0_get_hi
-cp0_get_hi:
-    mfhi    v0
-    jr      ra
-    nop
-
-    .globl  cp0_get_lo
-cp0_get_lo:
-    mflo    v0
-    jr      ra
-    nop
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-	/* 0x0 - TLB refill handler */
-    .section .vectors.1, "ax", %progbits
-    j      tlb_refill_handler
-    nop
-	
-	/* 0x100 - Cache error handler */
-    .section .vectors.2, "ax", %progbits
-    j      cache_error_handler
-    nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-    .section .vectors.3, "ax", %progbits
-    j      _general_exception_handler
-    nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-    .section .vectors.4, "ax", %progbits
-    j      _irq_handler
-    nop
-	
-    .section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-    /* general exception handler */
-_general_exception_handler:
-    .set    noreorder
-    mfc0    k1, CP0_CAUSE
-    andi    k1, k1, 0x7c
-    srl     k1, k1, 2
-    lw      k0, sys_exception_handlers(k1)
-    jr      k0
-    nop
-    .set    reorder
-
-    /* interrupt handler */
-_irq_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder
diff --git a/libcpu/mips/loongson/cache.c b/libcpu/mips/loongson/cache.c
deleted file mode 100644
index 6b3ad84b0e..0000000000
--- a/libcpu/mips/loongson/cache.c
+++ /dev/null
@@ -1,188 +0,0 @@
-#include "../common/mipsregs.h"
-#include "cache.h"
-
-#define K0BASE			0x80000000
-#define PRID_3210I 		0x4200
-
-typedef struct cacheinfo_t {
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t {
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu (void)
-{
-    unsigned int cpu_id;
-    void invalidate_cache (void);
-
-    pcacheop = &cacheop;
-    pcacheinfo = &cacheinfo;
-
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
-    cpu_id = read_c0_prid();
-    switch (cpu_id)
-	{
-	case PRID_3210I: 
-	    rt_kprintf ("CPU:SoC3210\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
-	    break;
-	default:
-	    rt_kprintf ("Unknown CPU type, system halted!\n");
-	    while (1) {}
-	    break;
-    }
-
-    return 0;
-}
-
-void probe_cache(void)
-{
-    unsigned int config = read_c0_config ();
-    unsigned int icache_size, ic_lsize;
-    unsigned int dcache_size, dc_lsize;
-
-    icache_size = 1 << (12 + ((config >> 9) & 7)); 
-    dcache_size = 1 << (12 + ((config >> 6) & 7));
-    ic_lsize = 16 << ((config >> 5) & 1);
-    dc_lsize = 16 << ((config >> 4) & 1);
-
-    rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
-	    dcache_size >> 10, dc_lsize);
-    rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
-	    icache_size >> 10, ic_lsize);
-
-    pcacheinfo->icache_size = icache_size;
-    pcacheinfo->dcache_size = dcache_size;
-    pcacheinfo->icacheline_size = ic_lsize;
-    pcacheinfo->dcacheline_size = dc_lsize;
-
-    return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	start = K0BASE;
-	while(start < end) {
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while(start <end){
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
-}
-
-
-void invalidate_icache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
-
-	while(start < end) {
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-void invalidate_dcache_all()
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while(start <end){
-		Invalidate_Dcache_Fill_Gc3210I(start);
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-//with cache disabled
-void init_dcache(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while(start < end){
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
-
-}
-
-void rt_hw_cache_init(void)
-{
-    unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
-
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
-
-    /*
-     *	2. clear CP0 taglo/taghi register;
-     */
-    pcacheop->Clear_TagLo();
-
-	/*
-     *	3. invalidate instruction cache;
-     */
-    while(start < end) {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
-    }
-
-    /*
-     *	4. invalidate data cache;
-     */
-    start = K0BASE;
-    end = (start + pcacheinfo->dcache_size);
-    while(start < end) {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
-
-	return ;
-}
diff --git a/libcpu/mips/loongson/cache.h b/libcpu/mips/loongson/cache.h
deleted file mode 100644
index 26f7649b42..0000000000
--- a/libcpu/mips/loongson/cache.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-extern void Clear_TagLo (void);
-
-extern void Invalidate_Icache_Gc3210I (unsigned int);
-extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
-extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-
-void rt_hw_cache_init(void);
-
-#endif
diff --git a/libcpu/mips/loongson/cache.inc b/libcpu/mips/loongson/cache.inc
deleted file mode 100644
index 815abb7f92..0000000000
--- a/libcpu/mips/loongson/cache.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-#endif
diff --git a/libcpu/mips/loongson/cache_gcc.S b/libcpu/mips/loongson/cache_gcc.S
deleted file mode 100644
index 00fd861eec..0000000000
--- a/libcpu/mips/loongson/cache_gcc.S
+++ /dev/null
@@ -1,202 +0,0 @@
-#include "../common/mipsregs.h"
-#include "../common/mips.inc"
-#include "../common/asm.h"
-#include "cache.inc"
-
-	.ent	cache_init
-    .global cache_init
-    .set noreorder
-cache_init:
-        move t1,ra
-####part 2####
-cache_detect_4way:
-        mfc0    t4, CP0_CONFIG
-        andi    t5, t4, 0x0e00
-        srl     t5, t5, 9     #ic
-        andi    t6, t4, 0x01c0
-        srl     t6, t6, 6     #dc
-        addiu   t8, $0, 1
-        addiu   t9, $0, 2
-                                #set dcache way
-        beq     t6, $0,  cache_d1way
-        addiu   t7, $0, 1       #1 way
-        beq     t6, t8,  cache_d2way
-        addiu   t7, $0, 2       #2 way
-        beq     $0, $0, cache_d4way
-        addiu   t7, $0, 4       #4 way
-cache_d1way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 12      #1 way
-cache_d2way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 11      #2 way
-cache_d4way:
-        addiu   t6, t6, 10      #4 way (10), 2 way(11), 1 way(12)
-1:                              #set icache way
-        beq     t5, $0,  cache_i1way
-        addiu   t3, $0, 1       #1 way
-        beq     t5, t8,  cache_i2way
-        addiu   t3, $0, 2       #2 way
-        beq     $0, $0, cache_i4way
-        addiu   t3, $0, 4       #4 way
-cache_i1way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 12
-cache_i2way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 11
-cache_i4way:
-        addiu   t5, t5, 10      #4 way (10), 2 way(11), 1 way(12)
-
-1:      addiu   t4, $0, 1
-        sllv    t6, t4, t6
-        sllv    t5, t4, t5
-#if 0
-    la	t0, memvar
-	sw	t7, 0x0(t0) #ways
-	sw	t5, 0x4(t0) #icache size
-	sw	t6, 0x8(t0) #dcache size
-#endif
-####part 3####
-	.set	mips3
-	lui	a0, 0x8000
-	addu	a1, $0, t5
-	addu	a2, $0, t6
-cache_init_d2way:
-#a0=0x80000000, a1=icache_size, a2=dcache_size
-#a3, v0 and v1 used as local registers
-	mtc0	$0, CP0_TAGHI
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	mtc0	$0, CP0_TAGLO
-	beq	t7, 1, 4f
-	cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
-	beq	t7, 2 ,4f
-	cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
-	cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
-	cache	Index_Store_Tag_D, 0x3(v0)
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_i2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a1
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t3, 1, 4f
-	cache	Index_Invalidate_I, 0x0(v0)	# 1 way
-	beq	t3, 2, 4f
-	cache	Index_Invalidate_I, 0x1(v0)	# 2 way
-	cache	Index_Invalidate_I, 0x2(v0)
-	cache	Index_Invalidate_I, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_d2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t7, 1, 4f
-	cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
-	beq	t7, 2, 4f
-	cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
-	cache	Index_Writeback_Inv_D, 0x2(v0)
-	cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_init_finish:
-	jr	t1
-    nop
-    .set reorder
-	.end cache_init
-
-###########################
-#  Enable CPU cache       #
-###########################
-
-LEAF(enable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or		t0, 0x03
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (enable_cpu_cache)
-    
-###########################
-#  disable CPU cache      #
-###########################
-
-LEAF(disable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or 		t0, 0x2
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (disable_cpu_cache)
-
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Clear_TagLo)
-	.set 	noreorder
-	mtc0	zero, CP0_TAGLO
-	nop
-	.set 	reorder
-	j		ra
-END(Clear_TagLo)
-
-    .set mips3
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Invalidate_Icache_Gc3210I)
-	.set	noreorder
-	cache	Index_Invalidate_I,0(a0)
-	cache	Index_Invalidate_I,1(a0)
-	cache	Index_Invalidate_I,2(a0)
-	cache	Index_Invalidate_I,3(a0)
-	.set	reorder
-	j		ra
-END(Invalidate_Icache_Gc3210I)
-
-/**********************************/
-/* Invalidate Data Cache		  */
-/**********************************/
-LEAF(Invalidate_Dcache_ClearTag_Gc3210I)
-	.set	noreorder
-	cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_ClearTag_Gc3210I)
-
-LEAF(Invalidate_Dcache_Fill_Gc3210I)
-	.set	noreorder
-	cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_Fill_Gc3210I)
-
-LEAF(Writeback_Invalidate_Dcache)
-	.set noreorder
-	cache	Hit_Writeback_Inv_D, (a0)
-	.set reorder
-	j	ra
-END(Writeback_Invalidate_Dcache)
-    .set mips0
diff --git a/libcpu/mips/loongson/context_gcc.S b/libcpu/mips/loongson/context_gcc.S
deleted file mode 100644
index 1bb953fe8c..0000000000
--- a/libcpu/mips/loongson/context_gcc.S
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * File      : context_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- */
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "soc3210.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-
-    mfc0    t0, CP0_CAUSE
-    and     t1, t0, 0xff
-	bnez	t1, spurious_interrupt		/* check exception */
-	nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/loongson/cpu.c b/libcpu/mips/loongson/cpu.c
deleted file mode 100644
index c459061f0a..0000000000
--- a/libcpu/mips/loongson/cpu.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-#include <rtthread.h>
-#include <soc3210.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
-	/* open the watch-dog */
-	WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
-	WD_CTRL |= 0x01;
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/loongson/exception.c b/libcpu/mips/loongson/exception.c
deleted file mode 100644
index 1c6aec53ac..0000000000
--- a/libcpu/mips/loongson/exception.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * File      : exception.c
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup SoC3210
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX	8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
-	rt_uint32_t cause;
-	rt_uint32_t index;
-
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
-
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson/interrupt.c b/libcpu/mips/loongson/interrupt.c
deleted file mode 100644
index 7e59ec950d..0000000000
--- a/libcpu/mips/loongson/interrupt.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-10-15     Bernard      first version
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include "soc3210.h"
-
-#define MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-	rt_int32_t idx;
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-	for (idx = 0; idx < MAX_INTR; idx ++)
-	{
-		irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-	}
-
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-	/* mask interrupt */
-	INT_EN &= ~(1 << vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-	INT_EN |= (1 << vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if(vector < MAX_INTR)
-    {
-        old_handler = irq_handle_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-		    rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-		    irq_handle_table[vector].handler = handler;
-            irq_handle_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int irq;
-    void *param;
-    rt_isr_handler_t irq_func;
-    static rt_uint32_t status = 0;
-    rt_uint32_t c0_status;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    if (c0_status & 0x8000)
-    {
-        rt_hw_timer_handler();
-    }
-
-    if (c0_status & 0x0400)
-    {
-        /* the hardware interrupt */
-        status |= INT_ISR;
-        if (!status) return;
-
-        for (irq = MAX_INTR; irq > 0; --irq)
-        {
-            if ((status & (1 << irq)))
-            {
-                status &= ~(1 << irq);
-
-                irq_func = irq_handle_table[irq].handler;
-                param = irq_handle_table[irq].param;
-
-                /* do interrupt */
-                (*irq_func)(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-                irq_handle_table[irq].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-                /* ack interrupt */
-                INT_CLR = (1 << irq);
-            }
-        }
-    }
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson/mipscfg.c b/libcpu/mips/loongson/mipscfg.c
deleted file mode 100644
index 8a96f458ab..0000000000
--- a/libcpu/mips/loongson/mipscfg.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}
diff --git a/libcpu/mips/loongson/soc3210.h b/libcpu/mips/loongson/soc3210.h
deleted file mode 100644
index c4d2c3926f..0000000000
--- a/libcpu/mips/loongson/soc3210.h
+++ /dev/null
@@ -1,172 +0,0 @@
-#ifndef __SOC3210_H__
-#define __SOC3210_H__
-
-#include "../common/mipsregs.h"
-
-/* registers */
-#define __REG8(addr)		*((volatile unsigned char *)(addr))
-#define __REG16(addr)		*((volatile unsigned short *)(addr))
-#define __REG32(addr)		*((volatile unsigned int *)(addr))
-
-#define EMI_BASE			0xBF000000
-#define NN_BASE				0xBF000040
-#define LCD_BASE			0xBF001000
-#define HSB_MISC_BASE		0xBF003200
-#define SPI_BASE			0xBF004000
-#define PS2_BASE			0xBF004040
-#define UART0_BASE			0xBF004080
-#define UART1_BASE			0xBF004090
-#define I2C_BASE			0xBF0040D0
-#define LPB_MISC_BASE		0xBF004100
-#define AC97_BASE			0xBF004200
-#define AC97_DMA_BASE		0xBF004280
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
-#define MAC0_BASE			0xBF005200
-#define MAC1_BASE			0xBF005300
-
-/* LCD registers */
-#define LCD_CTRL			__REG32(LCD_BASE + 0x000)
-#define LCD_STAT			__REG32(LCD_BASE + 0x004)
-#define LCD_HTIM			__REG32(LCD_BASE + 0x008)
-#define LCD_VTIM			__REG32(LCD_BASE + 0x00C)
-#define LCD_HVLEN			__REG32(LCD_BASE + 0x010)
-#define LCD_VBARA			__REG32(LCD_BASE + 0x014)
-#define LCD_VBARB			__REG32(LCD_BASE + 0x018)
-#define LCD_PCLT			__REG32(LCD_BASE + 0x800)
-
-/* HSB misc registers */
-#define HSB_MISC_REG		__REG32(HSB_MISC_BASE + 0x00)
-#define INT_EDGE			__REG32(HSB_MISC_BASE + 0x04)
-#define INT_STEER			__REG32(HSB_MISC_BASE + 0x08)
-#define INT_POL				__REG32(HSB_MISC_BASE + 0x0C)
-#define INT_SET				__REG32(HSB_MISC_BASE + 0x10)
-#define INT_CLR				__REG32(HSB_MISC_BASE + 0x14)
-#define INT_EN				__REG32(HSB_MISC_BASE + 0x18)
-#define INT_ISR				__REG32(HSB_MISC_BASE + 0x1C)
-#define GPIO_OE_60_29		__REG32(HSB_MISC_BASE + 0x20)
-#define GPIO_I_60_29		__REG32(HSB_MISC_BASE + 0x24)
-#define GPIO_O_60_29		__REG32(HSB_MISC_BASE + 0x28)
-#define HSB_ARB_CFG			__REG32(HSB_MISC_BASE + 0x2C)
-#define WD_TIMER			__REG32(HSB_MISC_BASE + 0x30)
-#define WD_CTRL				__REG32(HSB_MISC_BASE + 0x34)
-
-/* SPI registers */
-#define SPI_SPCR			__REG8(SPI_BASE + 0x00)
-#define SPI_SPSR			__REG8(SPI_BASE + 0x01)
-#define SPI_TX_FIFO			__REG8(SPI_BASE + 0x02)
-#define SPI_SPER			__REG8(SPI_BASE + 0x03)
-
-/* PS/2 registers */
-#define PS2_RIBUF			__REG8(PS2_BASE + 0x00)
-#define PS2_WOBUF			__REG8(PS2_BASE + 0x00)
-#define PS2_RSR				__REG8(PS2_BASE + 0x04)
-#define PS2_WSC				__REG8(PS2_BASE + 0x04)
-#define PS2_DLL				__REG8(PS2_BASE + 0x08)
-#define PS2_DLH				__REG8(PS2_BASE + 0x09)
-#define PS2_DL_KBD			__REG8(PS2_BASE + 0x0A)
-#define PS2_DL_AUX			__REG8(PS2_BASE + 0x0B)
-
-/* UART registers */
-#define UART_DAT(base)		__REG8(base + 0x00)
-#define UART_IER(base)		__REG8(base + 0x01)
-#define UART_IIR(base)		__REG8(base + 0x02)
-#define UART_FCR(base)		__REG8(base + 0x02)
-#define UART_LCR(base)		__REG8(base + 0x03)
-#define UART_MCR(base)		__REG8(base + 0x04)
-#define UART_LSR(base)		__REG8(base + 0x05)
-#define UART_MSR(base)		__REG8(base + 0x06)
-
-#define UART_LSB(base)		__REG8(base + 0x00)
-#define UART_MSB(base)		__REG8(base + 0x01)
-
-/* UART0 registers */
-#define UART0_DAT			__REG8(UART0_BASE + 0x00)
-#define UART0_IER			__REG8(UART0_BASE + 0x01)
-#define UART0_IIR			__REG8(UART0_BASE + 0x02)
-#define UART0_FCR			__REG8(UART0_BASE + 0x02)
-#define UART0_LCR			__REG8(UART0_BASE + 0x03)
-#define UART0_MCR			__REG8(UART0_BASE + 0x04)
-#define UART0_LSR			__REG8(UART0_BASE + 0x05)
-#define UART0_MSR			__REG8(UART0_BASE + 0x06)
-
-#define UART0_LSB			__REG8(UART0_BASE + 0x00)
-#define UART0_MSB			__REG8(UART0_BASE + 0x01)
-
-/* UART1 registers */
-#define UART1_DAT			__REG8(UART1_BASE + 0x00)
-#define UART1_IER			__REG8(UART1_BASE + 0x01)
-#define UART1_IIR			__REG8(UART1_BASE + 0x02)
-#define UART1_FCR			__REG8(UART1_BASE + 0x02)
-#define UART1_LCR			__REG8(UART1_BASE + 0x03)
-#define UART1_MCR			__REG8(UART1_BASE + 0x04)
-#define UART1_LSR			__REG8(UART1_BASE + 0x05)
-#define UART1_MSR			__REG8(UART1_BASE + 0x06)
-
-#define UART1_LSB			__REG8(UART1_BASE + 0x00)
-#define UART1_MSB			__REG8(UART1_BASE + 0x01)
-
-/* LPB misc registers */
-#define GPIO_OE_7_0			__REG8(LPB_MISC_BASE + 0x00)
-#define GPIO_OE_15_8		__REG8(LPB_MISC_BASE + 0x01)
-#define GPIO_OE_23_16		__REG8(LPB_MISC_BASE + 0x02)
-#define GPIO_OE_28_24		__REG8(LPB_MISC_BASE + 0x03)
-#define GPIO_I_7_0			__REG8(LPB_MISC_BASE + 0x10)
-#define GPIO_I_15_8			__REG8(LPB_MISC_BASE + 0x11)
-#define GPIO_I_23_16		__REG8(LPB_MISC_BASE + 0x12)
-#define GPIO_I_28_24		__REG8(LPB_MISC_BASE + 0x13)
-#define GPIO_O_7_0			__REG8(LPB_MISC_BASE + 0x20)
-#define GPIO_O_15_8			__REG8(LPB_MISC_BASE + 0x21)
-#define GPIO_O_23_16		__REG8(LPB_MISC_BASE + 0x22)
-#define GPIO_O_28_24		__REG8(LPB_MISC_BASE + 0x23)
-#define LPB_MISC_CFG		__REG8(LPB_MISC_BASE + 0x40)
-
-/* MAC0 registers */
-#define MAC0_BUS_MODE		__REG32(MAC0_BASE + 0x00)
-#define MAC0_TX_POLL_REQ	__REG32(MAC0_BASE + 0x08)
-#define MAC0_RX_POLL_REQ	__REG32(MAC0_BASE + 0x10)
-#define MAC0_RX_LIST_BASE_ADDR	__REG32(MAC0_BASE + 0x18)
-#define MAC0_TX_LIST_BASE_ADDR	__REG32(MAC0_BASE + 0x20)
-#define MAC0_STATUS			__REG32(MAC0_BASE + 0x28)
-#define MAC0_OP_MODE		__REG32(MAC0_BASE + 0x30)
-#define MAC0_INTERRUPT_EN	__REG32(MAC0_BASE + 0x38)
-#define MAC0_MISSED_FRAME_STATISTIC	__REG32(MAC0_BASE + 0x40)
-#define MAC0_SMI_EEPROM_CTL	__REG32(MAC0_BASE + 0x48)
-#define MAC0_BYTE_ALIGN		__REG32(MAC0_BASE + 0x50)
-#define MAC0_GPT_IM_CTL		__REG32(MAC0_BASE + 0x58)
-
-/* MAC1 registers */
-#define MAC1_BUS_MODE		__REG32(MAC1_BASE + 0x00)
-#define MAC1_TX_POLL_REQ	__REG32(MAC1_BASE + 0x08)
-#define MAC1_RX_POLL_REQ	__REG32(MAC1_BASE + 0x10)
-#define MAC1_RX_LIST_BASE_ADDR	__REG32(MAC1_BASE + 0x18)
-#define MAC1_TX_LIST_BASE_ADDR	__REG32(MAC1_BASE + 0x20)
-#define MAC1_STATUS			__REG32(MAC1_BASE + 0x28)
-#define MAC1_OP_MODE		__REG32(MAC1_BASE + 0x30)
-#define MAC1_INTERRUPT_EN	__REG32(MAC1_BASE + 0x38)
-#define MAC1_MISSED_FRAME_STATISTIC	__REG32(MAC1_BASE + 0x40)
-#define MAC1_SMI_EEPROM_CTL	__REG32(MAC1_BASE + 0x48)
-#define MAC1_BYTE_ALIGN		__REG32(MAC1_BASE + 0x50)
-#define MAC1_GPT_IM_CTL		__REG32(MAC1_BASE + 0x58)
-
-/* Peripheral Interrupt Number */
-#define IRQ_LCD				0
-#define IRQ_MAC1			1
-#define IRQ_MAC2			2
-#define IRQ_AC97			3
-#define IRQ_SPI				8
-#define IRQ_KEY				9
-#define IRQ_MOUSE			10
-#define IRQ_UART0			11
-#define IRQ_UART1			12
-#define IRQ_I2C				13
-#define IRQ_CAN0			14
-#define IRQ_CAN1			15
-#define IRQ_GPIO15			20
-#define IRQ_GPIO14			21
-#define IRQ_GPIO13			22
-#define IRQ_GPIO12			23
-
-#define SYSTEM_STACK		0x80003fe8		/* the kernel system stack address */
-
-#endif
diff --git a/libcpu/mips/loongson/stack.c b/libcpu/mips/loongson/stack.c
deleted file mode 100644
index dbfcf7ea91..0000000000
--- a/libcpu/mips/loongson/stack.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-07-07     Bernard      porting to Jz47xx
- */
- 
-#include <rtthread.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson/start_gcc.S b/libcpu/mips/loongson/start_gcc.S
deleted file mode 100644
index 2b0ef3a39b..0000000000
--- a/libcpu/mips/loongson/start_gcc.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * File      : start_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "soc3210.h"
-
-    .section ".start", "ax"
-    .set noreorder
-
-    /* the program entry */
-    .globl  _start
-_start:
-    .set    noreorder
-    la      ra, _start
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and		t0, 0xfffffff8
-	or		t0, 0x2			# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-    /* clear bss */
-    la      t0, __bss_start
-    la      t1, __bss_end
-_clr_bss_loop:
-    sw      zero, 0(t0)
-    bne     t0, t1, _clr_bss_loop
-    addiu   t0, t0, 4
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder
-
-    .globl  cp0_get_cause
-cp0_get_cause:
-    mfc0    v0, CP0_CAUSE
-    jr      ra
-    nop
-
-    .globl  cp0_get_status
-cp0_get_status:
-    mfc0    v0, CP0_STATUS
-    jr      ra
-    nop
-
-    .globl  cp0_get_hi
-cp0_get_hi:
-    mfhi    v0
-    jr      ra
-    nop
-
-    .globl  cp0_get_lo
-cp0_get_lo:
-    mflo    v0
-    jr      ra
-    nop
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-	/* 0x0 - TLB refill handler */
-    .section .vectors.1, "ax", %progbits
-	.global tlb_refill_exception
-	.type	tlb_refill_exception,@function
-tlb_refill_exception:
-    j      tlb_refill_handler
-    nop
-	
-	/* 0x100 - Cache error handler */
-    .section .vectors.2, "ax", %progbits
-    j      cache_error_handler
-    nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-    .section .vectors.3, "ax", %progbits
-	.global general_exception
-	.type	general_exception,@function
-general_exception:
-    j      _general_exception_handler
-    nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-    .section .vectors.4, "ax", %progbits
-	.global irq_exception
-	.type	irq_exception,@function
-irq_exception:
-    j      _irq_handler
-    nop
-	
-    .section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-    /* general exception handler */
-_general_exception_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder
-
-    /* interrupt handler */
-_irq_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder

From 6b31b07fc5f535d506cae12d0bab62fd701ef557 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 11:17:09 +0800
Subject: [PATCH 34/86] [build] Add frdm-k64f into travis-ci building

---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index f8b847bba6..37f275fe27 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -62,5 +62,5 @@ env:
   - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='frdm-k64f' RTT_ROOT_CHAIN='sourcery-arm'
+  - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
 

From 9951cb4cbc7bae1481bf580b1bae19c6e94e457d Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 11:34:14 +0800
Subject: [PATCH 35/86] [build] Remove the un-supported porting in the building

---
 .travis.yml | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 37f275fe27..2b9f998904 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -24,14 +24,10 @@ env:
   - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
 #  - RTT_BSP='bf533' # no scons
-  - RTT_BSP='dev3210' RTT_TOOL_CHAIN='sourcery-mips'
   - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='jz47xx' RTT_TOOL_CHAIN='sourcery-mips'
   - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm' 
-#  - RTT_BSP='lpc1114' # no scons
-#  - RTT_BSP='lpc122x' # no scons
   - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm' 
@@ -44,9 +40,7 @@ env:
   - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm' 
 #  - RTT_BSP='mini4020' # no scons
 #  - RTT_BSP='nios_ii' # no scons
-#  - RTT_BSP='nuc140' # no scons
 #  - RTT_BSP='pic32ethernet' # no scons
-#  - RTT_BSP='sam7s' # no scons
   - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='simulator' # x86
   - RTT_BSP='stm32f0x' RTT_TOOL_CHAIN='sourcery-arm' 
@@ -56,7 +50,6 @@ env:
   - RTT_BSP='stm32f40x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
 #  - RTT_BSP='upd70f3454' # iar
-#  - RTT_BSP='wh44b0' # no scons
 #  - RTT_BSP='x86' # x86
   - RTT_BSP='xplorer4330/m4' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'

From 7a7e3002c8fc2b4a65891db5ea84762ecdbcb66c Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 15:59:45 +0800
Subject: [PATCH 36/86] [Kernel] system does not lock scheduler when invoking
 soft-timer timeout function.

---
 src/timer.c | 29 +++++++++++++++++++++++------
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/src/timer.c b/src/timer.c
index ac8a148d8d..9785403d8b 100644
--- a/src/timer.c
+++ b/src/timer.c
@@ -28,6 +28,8 @@
  * 2010-05-12     Bernard      fix the timer check bug.
  * 2010-11-02     Charlie      re-implement tick overflow issue
  * 2012-12-15     Bernard      fix the next timeout issue in soft timer
+ * 2014-07-12     Bernard      does not lock scheduler when invoking soft-timer 
+ *                             timeout function.
  */
 
 #include <rtthread.h>
@@ -140,6 +142,7 @@ static int rt_timer_count_height(struct rt_timer *timer)
     return cnt;
 }
 
+#if RT_DEBUG_TIMER
 void rt_timer_dump(rt_list_t timer_heads[])
 {
     rt_list_t *list;
@@ -155,6 +158,7 @@ void rt_timer_dump(rt_list_t timer_heads[])
     }
     rt_kprintf("\n");
 }
+#endif
 
 /**
  * @addtogroup Clock
@@ -298,8 +302,14 @@ rt_err_t rt_timer_start(rt_timer_t timer)
 
     /* timer check */
     RT_ASSERT(timer != RT_NULL);
-    if (timer->parent.flag & RT_TIMER_FLAG_ACTIVATED)
-        return -RT_ERROR;
+
+	/* stop timer firstly */
+	level = rt_hw_interrupt_disable();
+	/* remove timer from list */
+    _rt_timer_remove(timer);
+    /* change status of timer */
+    timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
+    rt_hw_interrupt_enable(level);
 
     RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(timer->parent)));
 
@@ -560,6 +570,9 @@ void rt_soft_timer_check(void)
 
     current_tick = rt_tick_get();
 
+	/* lock scheduler */
+	rt_enter_critical();
+
     for (n = rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL-1].next;
          n != &(rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL-1]);)
     {
@@ -579,6 +592,8 @@ void rt_soft_timer_check(void)
             /* remove timer from timer list firstly */
             _rt_timer_remove(t);
 
+			/* not lock scheduler when performing timeout function */
+			rt_exit_critical();
             /* call timeout function */
             t->timeout_func(t->parameter);
 
@@ -587,6 +602,9 @@ void rt_soft_timer_check(void)
 
             RT_DEBUG_LOG(RT_DEBUG_TIMER, ("current tick: %d\n", current_tick));
 
+			/* lock scheduler */
+			rt_enter_critical();
+
             if ((t->parent.flag & RT_TIMER_FLAG_PERIODIC) &&
                 (t->parent.flag & RT_TIMER_FLAG_ACTIVATED))
             {
@@ -603,6 +621,9 @@ void rt_soft_timer_check(void)
         else break; /* not check anymore */
     }
 
+	/* unlock scheduler */
+	rt_exit_critical();
+
     RT_DEBUG_LOG(RT_DEBUG_TIMER, ("software timer check leave\n"));
 }
 
@@ -636,12 +657,8 @@ static void rt_thread_timer_entry(void *parameter)
             }
         }
 
-        /* lock scheduler */
-        rt_enter_critical();
         /* check software timer */
         rt_soft_timer_check();
-        /* unlock scheduler */
-        rt_exit_critical();
     }
 }
 #endif

From b89fd091b2968b0eca3ac947049c851b448a5aaa Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 12 Jul 2014 21:47:25 +0800
Subject: [PATCH 37/86] [Doc] Add Change log in Chinese.

---
 ChangeLog_CN.md | 1454 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 1454 insertions(+)
 create mode 100644 ChangeLog_CN.md

diff --git a/ChangeLog_CN.md b/ChangeLog_CN.md
new file mode 100644
index 0000000000..e899a685f0
--- /dev/null
+++ b/ChangeLog_CN.md
@@ -0,0 +1,1454 @@
+°æ±¾: RT-Thread 2.0.0 Alpha
+·¢²¼Ê±¼ä:2014/4/8
+	
+RT-Thread 2.0.0·ÖÖ§µÄµÚÒ»¸ö¼¼ÊõÔ¤ÀÀ°æ±¾£¬½öÓÃÓÚչʾ2.0.0·¢Õ¹·ÖÖ§µÄÑÝ»¯¶¯Ïò(°´ÕÕroadmap£¬2.0.0Õâ¸ö·ÖÖ§»áÓÐÒ»²¿·ÖRT-ThreadºÍLinux»¥²¹ÐԵļ¼Êõ£¬ÎªLinuxÔö¼Ó¸üºÃµÄʵʱÐÔ£¬ÎªRT-ThreadÔö¼Ó¸ü¶àµÄ¹¦ÄÜÐÔ£¬Õâ·Ý¼¼ÊõÔ¤ÀÀ°æÕýÊdz¯×ÅÕâ¸öÄ¿±ê¶øŬÁ¦)£¬»¶Ó­·´À¡½¨ÒéºÍÎÊÌâ¡£
+
+[×é¼þ±ä¸ü]
+* msh£º bugfix ºÍ¹¦ÄÜÐÔÔöÇ¿¡£Ð嵀 msh ÔÚµ÷ÓÃÍⲿģ¿é·½Ãæ¸ü¼Ó·½±ã¡£
+* DFS£º nfs µÄ bugfix ºÍÄÚÖÃÃüÁîµÄÔöÇ¿¡£ELM FatFS¼ÓÈë¶ÔÉÈÇø²»Æ¥ÅäÇé¿öϵÄÐÅÏ¢Êä³ö£¬ÕâÑùÄܹ»¼°Ê±¶¨Î»ÎÊÌâ¡£
+* JS£ºÐÂÌíÁËÇáÁ¿¼¶JavascriptÒýÇ棬¿ÉÒÔÔÚRT-ThreadÖÐÖ±½ÓÔËÐÐjavascript½Å±¾¡£
+* VMM£º¿ÉÒÔÔÚqemuÖÐÔËÐÐµÄ Virtual Machine Module ×é¼þ¡£ÔÝʱֻ֧³Ö realview-pb-a8 µÄ bsp¡£
+* CMSIS£º°æ±¾¸üÐÂÖÁ 3.20
+* drivers£ºUSB ЭÒéÕ»µÄÖع¹¡£ÐµĿò¼ÜÖбàдÇý¶¯±äµÃ¸ü¼ÓÈÝÒ×ÁË¡£
+
+[BSP ±ä¸ü]
+* beaglebone£º´®¿ÚÇý¶¯¸üÐÂ
+* realview-a8£ºÌí¼ÓÁË VMM ×é¼þ
+
+[±àÒë½Å±¾]
+* ¹Ì¼þ¼ÓÈëscons --target=ua -s£¬ÓÃÓÚ×¼±¸Óû§Ó¦Óû·¾³£»
+
+[·¢²¼ºó¼Ç]
+RT-Thread 2.0.0. Alpha°æ±¾Ïà±ÈÓÚRT-Thread 1.2.1£¬ÐµÄÌØÐÔÖ÷ÒªÓÐÁ½²¿·Ö£º
+- RT-Thread + Linux˫ϵͳ£¬Õⲿ·ÖÒÔRealView-A8´¦ÀíÆ÷(ARM Cortex-A8µ¥ºË)ΪÀ¶±¾£¬¸ø³öÒ»¸ö¼òµ¥µÄ˫ϵͳ²¢ÐÐÔËÐеÄdemo£»ÔÚûÓÐÓ²¼þµÄ»·¾³Ï£¬¿ÉÒÔʹÓÃQEMUÈí¼þÐéÄⷽʽµÄÖ´ÐС£Õâ¸öÁ´½ÓÖаüº¬Ò»¸ö±àÒëºÃµÄLinux¼°RT-Thread¶þ½øÖÆ°ü£¬¿ÉÒÔÖ±½ÓÏÂÔؽøÐÐÌåÑé¡£
+
+Ŀ¼ÖÐÓÐ Linux µÄÄں˾µÏñ zImage£¬ramdisk rootfs.cpio.gz¡£¿ÉÒÔÓÃ
+qemu-system-arm -M realview-pb-a8 -kernel zImage -initrd rootfs.cpio.gz -serial vc -serial vc
+À´Æô¶¯¡£Æô¶¯Ö®ºó Linux µÄ¿ØÖÆ̨ÔÚµÚÒ»¸ö´®¿ÚÉÏ(Atl + Ctrl + 3)£¬¿ÉÒÔÖ±½ÓÎÞÃÜÂëÒÔ root Óû§µÇ¼¡£µÇ¼֮ºó¼ÓÔØÄÚºËÄ£¿é£º
+insmod rtvmm.ko
+À´Æô¶¯ RT-Thread¡£RT-Thread Æô¶¯Ö®ºó¿ØÖÆ̨ÔÚµÚ¶þ¸ö´®¿ÚÉÏ(Atl + Ctrl + 4)¡£µÚÒ»¸ö´®¿ÚLinux shellÒÀÈ»¿ÉÒÔʹÓ㬵ڶþ¸ö´®¿ÚÔòÊÇRT-ThreadµÄshell¡£
+- JavaScript½âÎöÆ÷£¬Õâ¸öÊÇÓÉţͷ¸çÒÆÖ²µÄ£¬¿ÉÒÔÔÚÒ»¸ö·Ç³£Ð¡×ÊÁϵÄMCUÉÏÒÔJavaScript½Å±¾·½Ê½½øÐбà³Ì¡¢¿ª·¢¡£¸ù¾ÝÕâÖÖ·½Ê½£¬Ò²ÌṩÁËRN001JSµÄÒÔÌ«ÍøÓ²¼þÄ£¿é£ºÒÔJavaScript½Å±¾ÓïÑÔ×÷Ϊ¶þ´Î¿ª·¢£¬ÌṩÔÚÏßweb(¼´WebIDE)½øÐбà³Ì²¢ÔËÐÐJavaScript³ÌÐò¡£JavaScript×÷ΪһÃÅÇáÁ¿¼¶¡¢½âÊÍÐ͵ÄÓïÑÔ£¬¸üÈÝÒ×ÉÏÊÖ£¬ÅäºÏWebIDE¡¢¼°ÌṩµÄһЩexample¿ÉÒÔʹµÃ¿ª·¢±äµÃ·Ç³£µÄÇáËÉ£¬Ò²°üÀ¨Ò»Ð©´«¸ÐÆ÷µÄJavaScriptÀý×Ó£¬ÈÃ×öÍøÒ³µÄÈËÒ²¿ÉÒÔÍæÓ²¼þÁË£¡
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+
+°æ±¾: RT-Thread 1.2.1
+·¢²¼Ê±¼ä: 2014/4/8
+	
+ÔÚÔ­ÓеÄ1.2.0°æ±¾µÄbugÐÞÕý°æ±¾£¬Ò²ÊÇ1.2.0ϵÁеĵÚÒ»¸öÐÞÕý°æ±¾£¬Ô­ÔòÉϲ»Ìí¼ÓÈκεÄй¦ÄÜ£¬ÎÒÃǾ¡Á¿»á°´ÕÕÿ¸ö¼¾¶ÈÒ»¸öÐÞ¶©°æ±¾µÄ·½Ê½Íƽø¡£´ó¼ÒÔÚʹÓõĹý³ÌÖÐÓÐʲôÎÊÌ⻹Çë·´À¡¸øÎÒÃÇ£¬ÕâЩÎÊÌâºÜ¿ÉÄÜ»áÔÚϸö°æ±¾ÖÐÐÞÕý£¡
+
+ÒÔÏÂÊǸü¸Ä¼Ç¼£º
+[ÄÚºË]
+* Óû§Ó¦Óã¬Ôö¼ÓÓû§Ó¦ÓÃÃüÁîÐвÎÊýÖ§³Ö£»
+* ÔÚ¹ÒÆðÒ»¸öÈÎÎñʱ£¬°ÑÏàÓ¦µÄ¶¨Ê±Æ÷Ò²¹Ø±Õ£»
+
+[BSP]
+* BeagleBone£¬¼ÓÈë¸ü¶à´®¿ÚÇý¶¯Ö§³Ö£»
+* ÒƳýBSPÖÐrt_device_init_allº¯Êýµ÷Ó㬸ijɴò¿ªÉ豸ʱ×Ô¶¯½øÐгõʼ»¯£»
+* LPC176x£¬ÒƳýcomponents³õʼ»¯¹ÜÀíÆ÷£»
+* LPC4088£¬ÐÞÕýLEDÇý¶¯µÄÎÊÌ⣻
+* STM32F107£¬ÒƳýcomponents³õʼ»¯¹ÜÀíÆ÷£»
+
+[×é¼þ]
+* Îļþϵͳ£¬ELM FatFS¼ÓÈë¶ÔÉÈÇø²»Æ¥ÅäÇé¿öϵÄÐÅÏ¢Êä³ö£¬ÕâÑùÄܹ»¼°Ê±¶¨Î»ÎÊÌ⣻
+* Îļþϵͳ£¬NFSÍøÂçÎļþϵͳÐÞÕýÏà¹ØµÄһЩ±àÒ뾯¸æÐÅÏ¢£»
+* Îļþϵͳ£¬copyÃüÁî¼ÓÈëÎļþ¼Ð·½Ê½¸´Öƹ¦ÄÜ£»
+* Îļþϵͳ£¬RAMFS£¬¼ÓÈëµ½components³õʼ»¯¹ÜÀíÆ÷ÖУ»
+* Îļþϵͳ£¬ROMFS£¬ÓÃÓÚת»»ÎļþµÄ¹¤¾ßmkromfs.py£¬Ôö¼ÓLinuxÖ÷»úµÄÖ§³Ö£»
+* CMSIS¸üе½3.2.0°æ±¾£»
+* ´®¿ÚÇý¶¯¿ò¼Ü¼ÓÈëserial->ops->controlµÄµ÷Óã»
+* ÃüÁîÐÐϵͳ£¬ÓÅ»¯msh£¬Ö§³ÖÓû§Ó¦ÓõÄÃüÁîÐвÎÊý£»
+* ÃüÁîÐÐϵͳ£¬µ±Ê¹ÓÃmshʱ£¬Ä¬ÈÏʹÓÃmsh >µÄÃüÁîÐÐÌáʾ·û£»
+* TCP/IPЭÒéÕ»£¬µ¼³ö¸ü¶àµÄlwIP½Ó¿Ú¸øÓû§Ó¦Óã»
+* POSIX thread£¬ÐÞÕýÁËͬʱʹÓÃlwIP×é¼þʱµÄ±àÒ뾯¸æ£»
+* µÚÈý·½×é¼þ£¬¼ÓÈëTJPGDµÄÒÆÖ²£¬¼ÓÈëlibpngµÄÒÆÖ²£»
+
+[±àÒë½Å±¾]
+* ¹Ì¼þ¼ÓÈëscons --target=ua -s£¬ÓÃÓÚ×¼±¸Óû§Ó¦Óû·¾³£»
+
+[·¢²¼ºó¼Ç]
+* RT-ThreadЯ´øÁËÖÚ¶àµÄBSP£¬²»Ò»¶¨Äܹ»Ò»Ò»±£Ö¤Ã¿¸ö·ÖÖ§ÉÏ°ÑRT-ThreadÉÏÏàÓ¦µÄ¹¦ÄÜʹÓÃÆðÀ´¡£ËùÒÔÕë¶ÔÕâÖÖÇé¿ö£¬ÎÒÃÇÓÐÒ»¿îÆÀ¹ÀÓõÄÓ²¼þ¿ª·¢°å£ºRealBoard 4088£¬ÔÚÉÏÃæÁ¦Çó°ÑһЩÏà¹ØÀý³Ì¶¼Ìí¼ÓÉÏ£¬ÕâÑùÔÚÒ»¸ö»ù±¾µÄBSP»ù´¡ÉÏ£¬¿ÉÒÔ¶ÔÕÕ×Å°ÑÆäËûµÄ×é¼þ¡¢¹¦ÄÜÌí¼Ó½øÈ¥£»
+* RealBoard 4088ʹÓõÄRT-Thread°æ±¾Ö÷ÒªÒÔRT-Thread 1.2.1°æ±¾ÎªÖ÷¡£
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+
+°æ±¾: RT-Thread 1.2.0Õýʽ°æ±¾
+·¢²¼Ê±¼ä: 2014/1/6 
+
+ʵÏÖroadmapÖÐÌáµ½µÄ´ó²¿·ÖÄÚÈÝ
+	
+1£¬Îĵµ·½ÃæÒÑÍê³É¡¶RT-Thread±à³ÌÊֲᡷ£¬Í¬Ê±»¹ÓÐÂÛ̳ÉÏjiezhiͯЬµÄ¡¶Ò»ÆðÀ´Ñ§RT-ThreadϵÁÐÁ¬Ôؽ̡̳·
+2£¬BSP·ÖÖ§·½ÃæÐÂÔöcortext-A8(beaglebone)£¬cortext-R4(rm48x50)£¬UNITY-2(SEP6200),lpc408xµÄÒÆÖ²
+3£¬×é¼þ·½Ã棺
+- ¼ÓÈëmsh(ÀàËÆlinux shellµÄ·ç¸ñ)£¬Äܹ»Ö±½ÓÖ´ÐÐÓ¦ÓóÌÐò
+- ÐÂÔöfreemodbus 1.6.0µÄÒÆÖ²
+- ÐÂÔö¿ªÔ´µÄǶÈëʽ¹ØϵÊý¾Ý¿âSQLite 3.8.1µÄÒÆÖ²
+- ÐÂÔöYmodemЭÒé
+- ĬÈÏʹÓÃlwIP 1.4.1
+
+ÏÂÃæÊÇ×ÔRT-Thread 1.2.0 RC°æ±¾·¢²¼ÒÔÀ´¾ßÌåµÄ±ä¸üÂÄÀú£º
+Äںˣº
+* timer.c - ʹÓÃÌøÔ¾±í(skip list)ʵÏÖϵͳ¶¨Ê±Æ÷Á´±í£¬²¢ÔÚbspÖеÄstartup.cÖÐÖØмÓÈ붨ʱÆ÷³õʼ»¯º¯Êýrt_system_timer_init()
+* rtdebug.h - ÐÂÔöºê¶¨ÒåRT_DEBUG_IN_THREAD_CONTEXT
+* idle.c - ÔÚº¯Êýrt_thread_idle_excute()ÖÐÒ»´ÎÇå³ýËùÓеÄËÀÏß³Ì
+* scheduler.c - ÐÂÔöAPI rt_critical_level()·µ»Øµ÷¶ÈÆ÷ÉÏËø´ÎÊý
+
+ÒÆÖ²£º
+* cortex-m0 - ÐÞÕý cortex-m0 GCCÒÆÖ²ÖÐhardfaultµÄÎÊÌâµã
+* cortex-r4 - ÔÚstartupºóÊÍ·ÅIRQ¶ÑÕ»¿Õ¼ä
+* cortex-r4 - °´×Ö½Ú³¤¶È·ÖÅä¶ÑÕ»¿Õ¼ä
+
+BSP·ÖÖ§£º
+* ÐÂÔölpc408xÒÆÖ²
+* bsp/stm32f0x - Ôö¼ÓUSART1£¬USART2Çý¶¯£¬Ö§³Öfinsh£¬Ö§³Ö×é¼þ³õʼ»¯
+* bsp/simulator - µ±RTGUIÅäÖÃÎÞЧʱ´òÓ¡´íÎóÐÅÏ¢
+* bsp/simulator - ĬÈÏÇé¿öϹرÕRTGUIÑ¡Ïî
+* bsp/simulator - Ôö¼Ócreatedef.pyÎļþÀ´Éú³ÉVSµÄdefÎļþ
+* bsp/simulator - µ±Ê¹ÓÃVC++±àÒëʱȥ³ý_TIME_T_DEFINEDµÄ¶¨Òå
+* bsp/xplorer4330 - ÖØÃüÃûÎļþRetarget.cΪretarget.c,·ñÔòlinuxϵͳÖбàÒë»á±¨´í
+* bsp/xplorer4330 - ÐÞÕýGCC±àÒëÁ´½Óʱ¹ØÓÚENTRYµÄ¾¯¸æ
+* bsp/rm48x50 - ÐÂÔöGCCµÄÒÆÖ²
+* bsp/K60Fxxxx - ÐÞÕýÒ»¸ö±àÒë´íÎó
+
+×é¼þ£º
+* dfs - ÕýÈ·´¦ÀímkfsδʵÏÖµÄÇé¿ö
+* dfs - ʹÓÃÖ¸Õë´úÌæindex±äÁ¿
+* dfs - ÔÚº¯Êýdfs_filesystem_lookup()½«º¬ÒåÄ£ºýµÄÖ¸Õë±äÁ¿Ãû³ÆemptyÖØÃüÃûΪfs
+* dfs - ÐÞÕýdfs_unmountÎÊÌâµã
+* dfs - ÔÚÉ豸´ò¿ª´íÎóʱÁî¹ÒÔØʧ°Ü
+* dfs/elmfat - Áîelmfatfsÿ´Î¶¼¼ì²éÉÈÇø´óС
+* net - ÐÂÔöfreemodbus 1.6.0µÄÒÆÖ²
+* finsh - ÐÂÔöFINSH_USING_MSH_ONLYÑ¡Ïî
+* finsh - Ö»Óе±shellÉ豸Ϊ¿Õʱµ÷ÓÃrt_console_get_device()
+* finsh - ÐÞÕýFINSH_USING_SYMTAB䶨ÒåµÄ´íÎó
+* finsh - Öع¹control°´¼üµÄ´¦Àí
+* msh - Ôö¼ÓÎļþºÍ·¾¶Ãû³Æ×Ô¶¯²¹È«µÄ¹¦ÄÜ
+* msh - mshÄÚÔö¼ÓÖ´ÐÐmoduleµÄ¹¦ÄÜ
+* msh - mshÄÚÔö¼Ó¸ü¶àµÄÃüÁî
+* libc - ÐÞÕý _sys_read()/_sys_write()ÎÊÌâµã
+* external - Ôö¼Ó¿ªÔ´µÄǶÈëʽ¹ØϵÊý¾Ý¿âSQLite 3.8.1µÄÒÆÖ²
+* pthreads - ±ÜÃâESHUTDOWNÖظ´¶¨Òå
+* mtd_nand - ÔÚMTD nandÖÐÔö¼Ó¸ü¶àµÄµ÷ÊÔ´ëÊ©
+* mtd_nand - ÐÞÕý²Ù×÷MTD nandʱÆðʼ¿é´íÎóµÄÎÊÌâ
+* lwip-1.4.1 - ÔÚlwIPÄÚ¼ÓÈë¸ü¶àµÄRT-ThreadÑ¡ÏîÉèÖÃ
+* log_trace - ÐÞÕýº¯Êýmemmove()²ÎÊýʹÓôíÎóµÄÎÊÌâ
+* drivers/pipe - Ôö¼ÓÒ»¸öcontrolÃüÁîÀ´»ñµÃpipeÊ£ÓàµÄ¿Õ¼ä
+* drivers/serial - Èç¹û¶Áд³¤¶ÈΪ0£¬ÔòÁ¢¼´·µ»Ø
+
+Àý³Ì£º
+* examples - ÓÃrt_sem_control()ÖеÄRT_IPC_CMD_RESETÃüÁîrt_sem_trytake()À´Çå³ýÐźÅÁ¿
+* examples - ʼÖÕ´òÓ¡Êä³ö²âÊÔ½á¹û
+* examples - ÔÚËùÓеIJâÊÔ½áÊøºó´òÓ¡Êä³ö¼ò±¨
+* examples - ÔÚTCÏß³ÌÖÐÇå³ý±äÁ¿_tc_statµÄTC_STAT_RUNNING״̬
+* examples - ÖØÐÂʵÏÖloop¹¦ÄÜ£¬²¢ÐÂÔöfinshÃüÁîtc_loop
+* examples - ÔÚtc_stopÖÐÔö¼ÓÑÓʱ£¬ÓÉÔ­À´µÄÑÓʱRT_TICK_PER_SECOND/2µ÷ÕûΪ10 * RT_TICK_PER_SECOND
+* examples - ÔÚSConscriptÖÐÅжÏTCÈç¹û±»Ê¹ÄÜ£¬ÔÚCPPPATHÖÐÔö¼ÓTC·¾¶
+* examples - ÐÂÔöÒ»¸öin-mem-logµÄÀý×Ó
+* semaphore_priority.c - ÔÚcleanupʱÊÍ·ÅÐźÅÁ¿
+* heap_realloc.c - ¼ì²éµ÷ÓÃrealloc(ptr, 0)ÊÇ·ñ³É¹¦
+* thread_delete.c - tcÏ̵߳ÄÑÓʱӦ¸Ã±Ètid2µÄÑÓʱ³¤£¬±£Ö¤Æä²âÊÔ¹ý³ÌÖÐÕý³£ÔËÐÐ
+* thread_delay.c - ·Å¿í³¬Ê±ÅжÏÌõ¼þ£¬ÒòΪµ±RT_TICK_PER_SECONDΪ1000ʱ£¬ÈÝÒײúÉú1¸ötickµÄÎó²î
+* semaphore_static.c - ·Å¿í³¬Ê±ÅжÏÌõ¼þ£¬ÒòΪµ±RT_TICK_PER_SECONDΪ1000ʱ£¬ÈÝÒײúÉú1¸ötickµÄÎó²î
+* semaphore_dynamic.c - ·Å¿í³¬Ê±ÅжÏÌõ¼þ£¬ÒòΪµ±RT_TICK_PER_SECONDΪ1000ʱ£¬ÈÝÒײúÉú1¸ötickµÄÎó²î
+
+ÆäËû£º
+* ¸üÐÂREADME.md
+	
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+	
+°æ±¾: RT-Thread 1.2.0RC	
+·¢²¼Ê±¼ä: 2013/10/10/ 10:19
+	 
+Ö÷Ҫ˵Ã÷: ¸Ã°æ±¾ÐÂÔöARM Cortex-A8µÄÖ§³Ö(BeagleBone)£¬ÐÂÔöUNITY-2Äں˵ÄÖ§³Ö(SEP6200)£¬ÐÂÔöYmodemЭÒé¡£
+
+±ä¸üÂÄÀú
+========
+Äںˣº
+* ÐÞÕýrtdef.hÖеÄƴд´íÎó(_MSC_VER_ -> _MSC_VER)
+* ÐÞÕýscheduler.cÖеĵ÷ÊÔ´òÓ¡Êä³ö´íÎó
+* ipc - ÔÚº¯Êýrt_event_recv()ÖÐÔö¼Ó¶Ô²ÎÊýoptionÓÐЧÐԵļì²é
+* device - Ôö¼Óͳ¼ÆÉ豸ÒýÓôÎÊýµÄ±äÁ¿ref_count
+* memheap - ÐÞÕýÄÚ´æ¿é·Ö¸îÎÊÌâµã
+* memheap - ÓÅ»¯º¯Êýrt_memheap_realloc()
+* kservice - º¯ÊýÉùÃ÷ʹÓÃrt_vsnprintf´úÌævsnprintf
+
+×é¼þ:
+* dfs - ÐÞÕýdfs_file.cÖÐÒ»´¦±äÁ¿²ÎÊýÀàÐÍ´íÎóµÄÎÊÌâ
+* dfs - Ôö¼Ómount table
+* dfs - ÔÚbuilding½Å±¾ÖмÓÈëramfsµÄÖ§³Ö
+* dfs - ÐÞÕýramfsÖÐO_APPEND writeµÄÎÊÌâ
+* dfs/elm - ÔÚmkfsÖмÓÈëdevice_open/close
+* dfs/jffs2 - ÐÞÕýjffs2_opn/opendirÖеÄf_flag³õʼ»¯ÎÊÌâ
+* dfs/jffs2 - ÐÞÕýjffs2жÔØÎÊÌâ
+* pthread - ÐÞÕýÒ»´¦±àÒ뾯¸æ
+* drivers/pipe - Ôö¼Órt_pipe_init/rt_pipe_detach
+* drivers/pipe - Ôö¼Ó·Ç×èÈû¶ÁдºÍÇ¿ÖÆдģʽ
+* drivers/pipe - µ±»Ö¸´¶ÁµÄʱºòµ÷Óú¯Êýrx_indicate()
+* drivers/pipe - Ôö¼ÓÒ»¸öÉ豸ÀàÐÍ(pipeÀàÐÍ)
+* drivers/portal - ʵÏÖportalÉ豸ÀàÐÍ
+* drivers/ringbuffer - ÐÞ¸ÄһЩģºý²»ÇåµÄº¯ÊýÃû³Æ
+* drivers/ringbuffer - ÐÂÔöput_forceºÍputchar_force½Ó¿Úº¯Êý
+* finsh - µ±set_deviceʱÔö¼ÓÉ豸¼ì²é
+* finsh - ÔÚrx_indÖÐÔö¼Ó¶ÔshellÉ豸µÄ×Ô¶¯ÉèÖÃ
+* finsh - Ôö¼ÓpipeºÍportalÉ豸µÄÃèÊö
+* finsh - ÔÚ±äÁ¿¶¨ÒåʱʹÓñðÃû
+* finsh - µ±¹Ø±ÕÉ豸ʱעÏúrx_indicate
+* finsh - ÐÞÕýÃüÁîÐÐÌ«³¤µÄÎÊÌâ
+* finsh/msh - Ö»Óе±DFS_USING_WORKDIRʹÄÜʱ²ÅÉùÃ÷cd/pwd
+* init - ΪеÄ×é¼þ³õʼ»¯»úÖƸüÐÂÁ¬½Ó½Å±¾
+* init - Ôö¼Ó×é¼þ³õʼ»¯µ÷ÊÔ´úÂë
+* logtrace - ÕûÀí´úÂ룬ȥ³ý±àÒ뾯¸æ
+* logtrace - Ôö¼ÓLOG_TRACE_VERBOSE
+* logtrace - µ÷Õûlog values
+* logtrace - Ö»Óе±finshʹÄܵÄʱºò²ÅÉùÃ÷cmd
+* libc/minilibc - ÔÚsys/time.hÖÐÔö¼ÓgettimeofdayµÄÉùÃ÷
+* utilities - ÐÂÔöymodem
+
+¹¤¾ß:
+* building.py - Ôö¼Óclang¾²Ì¬·ì϶Æ÷µÄÖ§³Ö
+* building.py - ΪKeil MDKÔö¼Óbuildlib¹¦ÄÜ
+* building.py - ÔÚclang-analyzeÖÐÖ´ÐÐ'clang -Wall -fsyntas-only'
+* clang-analyze.py - Ôö¼ÓÒ»¸ö¶¨Öƹ¤¾ßʵÏÖclang¾²Ì¬·ÖÎö
+
+·ÖÖ§:
+* ÐÂÔöBeagleBoneµÄÒÆÖ²
+* ÐÂÔöSEP6200µÄÒÆÖ²
+* ÐÂÔöK60FxxxxµÄÒÆÖ²
+* ÐÞÕýLinuxÖеıàÒë´íÎó(lm4f232, stm32f40x, xplorer4330)
+* cortex-m3 - ¼ÓÇ¿hard faultµÄÒì³£´¦Àíº¯Êý
+* at91sam9260 - ¸üд®¿ÚÇý¶¯£¬Ê¹ÓÃ×é¼þÖеÄͨÓô®¿ÚÇý¶¯
+* at91sam9260 - ¸üй¤³ÌĿ¼½á¹¹
+* at91sam9260 - ÐÞÕý±àÒë´íÎó
+* at91sam9260 - ÄÚǶGPLv2Ðí¿É
+* stm32f10x - ɾ³ýÎÞÓõÄÎļþ
+* stm32f10x - ¸üй¤³ÌĿ¼½á¹¹
+* stm32f10x - ¸üй¤³ÌÎļþ
+* stm32f10x - ΪʹÓÃеÄ×é¼þ³õʼ»¯¸üÐÂÁ¬½Ó½Å±¾
+* stm32f10x - ΪʹÓÃеÄ×é¼þ³õʼ»¯¸üÐÂSD cardÇý¶¯
+* stm32f10x - ΪʹÓÃеÄ×é¼þ³õʼ»¯¸üÐÂDM9000Çý¶¯
+* stm32f10x - ¸üд®¿ÚÇý¶¯£¬Ê¹ÓÃ×é¼þÖеÄͨÓô®¿ÚÇý¶¯
+* stm32f10x - ÐÞÕýrtgui³õʼ»¯ÎÊÌâ
+* simulator - ΪʹÓÃеÄ×é¼þ³õʼ»¯¸üдúÂ룬ÒÔ±ãÖ§³Ömingw
+* simulator - Ö§³ÖLinuxϵͳ
+* simulator - ÐÞÕýLinuxϵͳÖеÄSDL³õʼ»¯ÎÊÌâ
+* simulator - ÔÚrt_components_initÖ®ºó³õʼ»¯SDL
+* simulator - ½«¶ÔSDLÉèÖõÄÄÚÈÝÒÆÈëdrivers/SConstruct
+* simulator - ÔÚenvÖлñµÃCORSS_TOOLºÍEXEC_PATHµÄÖµ
+* simulator - Ö§³Öclang-analyze
+* simulator - Ôö¼Ótap netif driver
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+°æ±¾: RT-Thread 1.2.0 Beta °æ±¾
+·¢²¼Ê±¼ä: 2013/6/30
+		
+½ø¹ý¿ª·¢ÈËÔ±Èý¸öÔµÄŬÁ¦£¬RT-Thread 1.2.0 Beta °æ±¾ÈçÆÚ·¢²¼¡£
+¸Ã°æ±¾Ä¬ÈϲÉÓÃlwIP 1.4.1ЭÒéÕ»£¬USB device stackÒ²½øÒ»²½ÍêÉÆ¡£¼ÓÈë log_trace ×Óϵͳ£¬¼ÓÈë×é¼þ³õʼ»¯Éý¼¶°æ±¾£¬¼ÓÈë ARM Cortex-R µÄÒÆÖ²¡£
+
+Ö÷Òª±ä»¯£º
+1£¬ÐÂÔö×é¼þ³õʼ»¯¹¦ÄÜ
+- ÏêÇéÇë¿´ÂÛ̳Ìû×Ó[й¦ÄÜ] ×é¼þ³õʼ»¯
+2£¬Ö§³ÖARM Cortex-RϵÁд¦ÀíÆ÷
+- Grissiom Íê³É ARM Cortex-R µÄÒÆÖ²£¬Ä¿Ç°BSPÖÐÒÑÓÐTI RM48x50·ÖÖ§£¨½öÖ§³ÖTI CCS¿ª·¢»·¾³£©
+3£¬ÎļþϵͳÖÐÐÂÔö RAMFS
+4£¬¼ÓÈë log_trace ×Óϵͳ
+5£¬ÓÅ»¯Cortex-M4Ïß³ÌÉÏÏÂÎÄÇл»£¬Ê¹ÓÃÁ˸¡µãÔËËãµÄÏ̲߳ű£´æ¼°»Ö¸´FPU¼Ä´æÆ÷
+- ÏêÇéÇë¿´ÂÛ̳Ìû×Ó[ÓÅ»¯]cortex-m4fÏß³ÌÇл»£¬ÓÅ»¯FPU¼Ä´æÆ÷
+6£¬ÐÂÔöAPI rt_memheap_realloc()
+7£¬ÖØÐÂʵÏÖringbuffer£¬²ÉÓþµÏñµÄ·½·¨Çø·Ö¡°Âú¡±ºÍ¡°¿Õ¡±£¬Í¬Ê±Ö§³ÖÈÎÒâ´óСµÄbuffer
+8£¬ÄÚºËÖмÓÈëRT_KERNEL_MALLOC/RT_KERNEL_FREE/RT_KERNEL_REALLOCºê¡£
+Èç¹ûÓû§Î´¶¨ÒåÕâЩºê£¬½«Ä¬ÈÏÖ¸Ïòrt_malloc/rt_free/rt_realloc¡£
+ͬʱÄں˽ö¾ÖÏÞÓÚʹÓÃÕâЩºêÀ´Ê¹Óö¯Ì¬ÄÚ´æ
+9£¬ÔÚ building.py ÖÐÐÂÔöÉú³É cscope database µÄÑ¡Ïî
+10£¬USB×é¼þÐÂÔöresetº¯Êý£¬Ö§³ÖÈȲå°Î
+11£¬scons±àÒëϵͳ֧³ÖCCS¿ª·¢»·¾³
+12£¬USB×é¼þÐÂÔö״̬ÐÅÏ¢£¨USB_STATE_NOTATTACHED£¬USB_STATE_ATTACHED£¬USB_STATE_POWERED...£©
+
+ÐÞ¸´ÎÊÌâµã£º
+1£¬USB×é¼þHOST¿ÉÒÔ¹ÒÆðendpoints
+2£¬simulator·ÖÖ§£¬ÐÞ¸´ serial_write ÎÊÌâ
+3£¬udisk¿ÉÒÔ±»µ¯³ö
+4£¬iar.pyÖÐÐÞ¸´¾ø¶Ô·¾¶µÄÎÊÌâ
+5£¬dfs_fs.hÄÚÔö¼Ódfs_mkfs()º¯ÊýµÄÉêÃ÷
+6£¬Éú³ÉMDK¹¤³ÌÎļþµÄʱºò¼ÓÈëlibraryÎļþ
+7£¬µ±PC²»ÔÙ½ÓÊÜÊý¾ÝµÄʱºò£¬ÖØÖÃVCOMÏàÓ¦µÄ״̬
+8£¬USB×é¼þ£º·µ»ØÕýÈ·µÄLangID×Ö·û´®³¤¶È¸øHOST
+9£¬Cortex-M0£¬Cortex-M3£¬Cortex-M4ÉÏÏÂÎÄÇл»Ê±£¬»ØÊÕϵͳ³õʼ»¯Ê±Óõ½µÄÕ»¿Õ¼ä
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+
+°æ±¾: RT-Thread 1.2.0 Alpha°æ±¾
+·¢²¼Ê±¼ä: 2013/4/10
+	
+×ñÑ­2013ÄêRT-Thread roadmap£¬RT-Thread 1.2.0 Alpha°æ±¾·¢²¼£¬AlphaÒâζ×Ŵ˰汾Ϊ¼¼ÊõÔ¤ÀÀ°æ£¬½öÓÃÓÚչʾRT-Thread 1.2.0δÀ´µÄ·¢Õ¹·½Ïò£¬²¢²»ÊʺÏÓÚ¿ª·¢Õýʽ²úÆ·¡£RT-Thread 1.2.0°æ±¾ÊÇ1.1.xϵÁеÄÏÂÒ»¸ö·ÖÖ§£¬Õâ¸ö·ÖÖ§Ö÷ÒªÌåÏÖµÄÊÇRT-Thread 1.xϵÁеÄÎĵµÇé¿ö¡£µ±È»Ò²ÓÐһЩ¹¦ÄÜ¡¢´úÂë·½ÃæµÄÔöÇ¿¡£
+
+°éËæ×Åа汾µÄµ½À´£¬RT-ThreadÓм¸¸öÖØ´óµÄת±ä£º
+1£¬´úÂëÍйܴÓgoogle code(SVN)ǨÒƵ½github(GIT)
+2£¬RT-ThreadÓëRTGUIÇø·Ö¿ªÀ´£¬²¢³ÉΪÁ½¸ö¶ÀÁ¢µÄ¿ª·¢·ÖÖ§
+3£¬ÖØÊÓÎĵµ£¬½«Îĵµ½¨Éè×÷Ϊ1.2.0°æ±¾µÄÊ×ÒªÈÎÎñÀ´×¥
+
+ÄÚºËÖ÷Òª±ä»¯£º
+1£¬¼ÓÈë__rt_ffsº¯ÊýÓÃÓÚʵÏÖ32λÕûÊýÖлñÈ¡µÚÒ»¸öÖÃ1µÄλ£»Í¬Ê±µ÷¶ÈÆ÷ÖÐλͼÏà¹ØËã·¨Ö±½ÓʹÓÃ__rt_ffsº¯Êý£»CPUÒÆֲʱ£¬¿É¶¨ÒåRT_USING_CPU_FFS£¬Ê¹ÓÃоƬָÁîÍê³É¡£
+
+2£¬ÐµÄÖжÏ×¢²á»úÖÆ
+weety¼ÓÈëinterrupt description¹¦ÄÜ£¬ÓÃÓÚΪinterruptÔö¼Ó¸ü¶àµÄÐÅÏ¢£¬Í¬Ê±ÖжϷþÎñÀý³ÌÒ²¿ÉÒÔЯ´øÓû§×Ô¶¨ÒåµÄ²ÎÊýÀàÐÍ¡£
+* Õⲿ·Ö¶ÔARM7¡¢ARM9¡¢MIPSµÈÓ°ÏìºÜ´ó£¬ÐèÒª¶ÔCPUÒÆÖ²×öÏàÓ¦µÄһЩÐ޸ġ£
+* Õⲿ·Ö¶ÔARM Cortex-MϵÁÐоƬûÓÐÓ°Ïì¡£
+
+3£¬µ÷Õû¶¨Ê±Æ÷²åÈëλÖã¬ÎªÏàͬ³¬Ê±¶¨Ê±µÄºóÃæ¡£
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+×é¼þÖ÷Òª±ä»¯£º
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+2£¬ÍêÉÆat91sam9260·ÖÖ§µÄÒÆÖ²¼°Çý¶¯¸üС£
+
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+1£¬¿ªÆôÊ¡ÂÔ±àÒëʱ³¤ÃüÁîÌØÐÔ£¬Èç¹ûÐèÒª²é¿´±àÒëʱÃüÁîÐУ¬¿ÉÒÔʹÓÃscons --verbose²é¿´¡£
+2£¬¼ÓÈëÉú³ÉCodeBlocks¹¤³ÌÌØÐÔ¡£
+3£¬ÐÞÕýµ±ÏµÍ³°²×°Ê¹ÓÃKeil MDK 4.6+°æ±¾µÄÎÊÌâ¡£
+
+githubÖ÷ÒªÌá½»ÂÄÀú:
+5646189b29: elm fatfsÖ§³Ömkfs£¬²¢ÇÒÎÞÐèÌáÇ°Ö´ÐÐdfs_mount; mount/umount/mkfs²Ù×÷Ò²²»»áÒýÆðreset
+22786f8817: ÔÊÐíÓû§×Ô¶¨ÒåPIDºÍVID
+0001344105: ¸üÃ÷È·µÄ¶¨Ê±Æ÷ÔËÐлúÖÆ£¬Èç¹ûÁ½¸ö¶¨Ê±Æ÷ÔÚͬһ¸öʱ¿Ì·¢Éú³¬Ê±£¬ÄÇôÏÈ¿ªÊ¼µÄ¶¨Ê±Æ÷ÏÈ´¦Àí
+5d68ef8ec1: ÐÞÕýʹÓÃ64λGCCʱ±àÒëfinsh¹ý³ÌÖз¢Éú´íÎóµÄÎÊÌâ
+a4d661dcf1: ÐÞÕýdfs_elm.cÖÐÒ»´¦ÄÚ´æй¶£¬²¢ÇÒÔÚmount fatfsʧ°ÜʱִÐÐ umount fatfs²Ù×÷
+43228aeb9c: ÐÞÕýlist_tcpsÎÊÌ⣺ipaddr_ntoa²»ÊÇ¿ÉÖØÈëµÄº¯Êý¡£
+3de4b92a68: ÐÞÕýAT91SAM9260·ÖÖ§ÖÐPHY link״̬´íÎóµÄÎÊÌâ¡£
+1abaa0492d: ÔÚkservice.cÖÐÔö¼Ó__rt_ffsµÄʵÏÖ¡£
+ec6f9e3b5a: ÐÞÕýÔÚdfs.cÖÐÒ»´¦¿ÕÖ¸ÕýµÄÎÊÌâ¡£
+92d4c1939b: ÐÞÕýat91sam9260·ÖÖ§ÉÏÏÂÎÄÇл»ÎÊÌâµã£¬±ÜÃâidleÈÎÎñ¶ÑÕ»Òç³ö¡£
+fb9ea5eada: ÔÚat91sam9260·ÖÖ§ÖÐʹÄÜMMU£¬²¢ÇÒ¸üÐÂSDIOºÍEMACÇý¶¯¡£
+009eccf640: ÐÞÕýº¯Êýlist()ÖдíÎóʹÓÃstrncpyµÄÎÊÌâµã¡£
+83751c63e3: ÔÚdlopen.cÖÐÔö¼Ó³ö´í´¦Àí¡£	
+	
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+°æ±¾: RT-Thread 1.1.1Îȶ¨°æ±¾
+·¢²¼Ê±¼ä: 2013/6/30
+
+Õâ¸ö°æ±¾ÊÇÒ»¸ö»ùÓÚRT-Thread 1.1.0Õýʽ°æµÄbugÐÞÕý°æ£¬Ïà±ÈÓÚ1.1.0°æ±¾£¬»ù±¾ÉÏûÓÐÌí¼ÓʲôÐµĹ¦ÄÜ£¬ÒÔÏÂÊÇÐ޸ļǼ£º
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+* ÄÚºËÖмÓÈëRT_KERNEL_MALLOC/RT_KERNEL_FREE/RT_KERNEL_REALLOCºê¡£Èç¹ûÓû§Î´¶¨ÒåÕâЩºê£¬½«Ä¬ÈÏÖ¸Ïòrt_malloc/rt_free/rt_realloc¡£Í¬Ê±Äں˽ö¾ÖÏÞÓÚʹÓÃÕâЩºêÀ´Ê¹Óö¯Ì¬Äڴ棻
+* ¼ÓÈëMiscellaneous DeviceÀàÐÍÉ豸£»
+* µ±Î´¶¨ÒåRT_USING_CONSOLEʱ£¬½«°Ñrt_kprintfÖÿÕÒÔ½ÚÊ¡×Ö·û´®Õ¼Óÿռ䣻
+* memheap¶ÔÏó¼ÓÈërt_memheap_reallocº¯Êý½Ó¿Ú£»
+* rt_exit_criticalº¯Êý¿ÉÒÔÔÚµ÷¶ÈÆ÷δÆô¶¯Ê±Ê¹Óã»
+* keil¹¤³ÌÎļþÉú³ÉÖÐÖ§³Ö¼ÓÈë¿âÎļþ£»
+
+×é¼þ£º
+* ÐÞÕýlwIP 1.4.0ÖÐipv4/ip.cÖÐIP_ACCEPT_LINK_LAYER_ADDRESSED_PORTºê¶¨Òå´íÎóµÄÎÊÌ⣻
+* ¼ÓÈëRAMFS£¬ÄÚ´æÎļþϵͳ£»
+* ͳһworkingĿ¼ÌØÐÔ²»Ö§³ÖµÄ×Ö·û´®Î»Öã»
+* DFSÖмÓÈëÄÚ´æ·ÖÅäʧ°ÜµÄ±£»¤£»
+* DFSÖÐdfÊä³ö¸ü¶àÓÐÒâÒåµÄÐÅÏ¢£»
+
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+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+
+°æ±¾: RT-Thread 1.1.0 Õýʽ°æ·¢²¼
+·¢²¼Ê±¼ä: 2012/12/31
+	
+2012ÄêÂêÑÅÈËÔ¤ÑÔµÄÊÀ½çÄ©ÈÕûÓе½À´£¬µ«ÊÇÎÒÃÇµÄ RT-Thread 1.1.0 Õýʽ°æÈ´ÈçÔ¼¶øÖÁ¡£
+
+¿´¿´ 1.1.0 Í»³öµÄ¸ü¸Ä¼°¸Ä½øÇé¿ö£¬Ê×ÏÈ 1.1.0 °æ±¾ÊÇ 1.0.x ϵÁеÄÒ»¸öÉý¼¶°æ±¾£¬²¢Î´°üÀ¨ÊµÖÊÐÔ¡¢´óµÄ¸Ä¶¯£¬¸Ä¶¯Ö÷ÒªÌåÏÖÔÚ£º
+ÄںˣºÇ¿»¯Ó¦ÓÃÄ£¿é¡£Í¨¹ý 1.1.0 ¿ª·¢Ê±Ö÷ҪʹÓõÄƽ̨£ºART¡¢realtouch-stm32f4£¬¶ÔÓ¦ÓÃÄ£¿é½øÐÐÏàÓ¦µÄÐÞÕý£¬²¢ÕæÕýµÄÔÚ Cortex-M ϵÁÐÉÏʹÓÃÆðÀ´¡£
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+Çý¶¯¿ò¼Ü£ºÕⲿ·ÖÊÇ 1.1.0 ·ÖÖ§ËùÖ÷ÒªÐÂÔöµÄ²¿·Ö£¬°üÀ¨£º
+=>USB device/host stack;
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+
+аæµÄ RTGUI ÈÔÐèÒªÍêÉÆ£¬´Ë´Î 1.1.0 Õýʽ°æ±¾ÖÐÔݲ»°üÀ¨£¬Ö®ºó»áÓе¥¶ÀµÄ RTGUI °æ±¾·¢²¼¡£
+Ïë»ñÈ¡¸ü¶à RTGUI ÐÅÏ¢µÄͬѧ£¬Çë¹Ø×¢ https://github.com/RT-Thread/RTGUI
+
+ÒÔÏÂÊÇ×Ô RT-Thread 1.1.0 RC °æ±¾·¢²¼ºó£¬ÏêϸµÄ¸üÐÂÄÚÈÝ£º
+Äںˣº
+=====
+- ÔÚÉ豸ע²áʱÔö¼ÓÉ豸¼ì²é²½Öè
+- ÔÚ kservice.c ÖÐÐÞÕýÒ»´¦Î´¶¨Òå compiler ʱµÄ±àÒë´íÎó
+- ÔÚ memheap.c ÖÐÔö¼Ó¶Ô heap object µÄ»¥³â²Ù×÷
+- ÖØж¨Òåºê RT_NULL ÓÉ ((void*)0) ±ä¸üΪ 0
+- ÔÚ module.c ÖÐʹÓà RT_DEBUG_LOG ´úÌæ rt_kprintf
+- Ó¦ÓÃÄ£¿éÖÐɾ³ý rt_current_module
+- Ó¦ÓÃÄ£¿éÖÐÓû§¿ÉÒÔʹÓà rt_module_unload() À´Ð¶ÔØÒ»¸öÄ£¿é
+- ÐÞÕýº¯Êý clock_time_system_init() ÖжԱäÁ¿ _timevalue.tv_usec ³õʼ»¯´íÎóµÄÎÊÌâµã
+- Èí¼þ¶¨Ê±Æ÷ÖÐÐÞÕý next timeout ´¦Àí´íÎóµÄÎÊÌâµã
+- º¯Êý rt_kprintf() ÖÐÐÞÕýÒ»´¦ÓÉ Grissiom ·¢ÏÖµÄ BUG
+- ÐÞÕýº¯Êý rt_components_init() ÖÐ¶Ô pthread ³õʼ»¯ÎÊÌâµã
+- device.c ÖУ¬Èç¹ûÉ豸²»´æÔÚÔò·µ»Ø RT_EOK
+
+Îļþϵͳ£º
+=========
+- ÍêÉÆ jffs2 ÒÆÖ²£¬Ö§³Ö GCC ±àÒëÆ÷£¨Ê¹Óà NEWLIB£©
+- ÐÞÕýº¯Êý dfs_unmount() ÖдæÔÚµÄÒ»´¦ BUG
+- ÐÞÕýº¯Êý dfs_uffs_seek() ÖдæÔÚµÄÒ»´¦ BUG
+- ÐÞÕý DFS ÖÐ O_APPEND ºÍ lseek ÎÊÌâµã
+- ÔÚ DFS ÖÐÔö¼Ó¶Ô dfs_fd µÄºÏ·¨ÐÔ¼ì²é
+- ÐÞÕý uffs ÖÐδ³õʼ»¯ËùÓÐÉ豸²Ù×÷º¯Êý
+- ¸üРuffs£¬Ö§³Ö MTD ½Ó¿Ú
+- Ôö¼Ó DFS_NFS_MAX_MTU Ñ¡ÏÐÞ¸´¶Áд NFS ʱ°ü³¤¶È³¬¹ý1¸ö mtu ³¤¶ÈµÄ bug
+- ÐÞ¸´ NFS ÖÐ seek µÄÒ»´¦ BUG
+- ÐÞ¸´Ïò NFS server ÉÏ´´½¨Îļþ/Ŀ¼ʱ·¾¶ºÍȨÏÞµÄ BUG
+
+×é¼þ£º
+=====
+- ¼ÓÈë LUA ½Å±¾µÄ¹¦ÄÜ
+- finsh ×é¼þÖÐÍêÉÆ¶Ô win32 ÒÆÖ²·ÖÖ§µÄÖ§³Ö
+- ÍêÉÆ USB device stack
+- RTC Çý¶¯¿ò¼ÜÖÐÐÂÔö¶Ô RTC alarm µÄÖ§³Ö
+- ´®¿ÚÇý¶¯¿ò¼ÜÖÐÔö¼Ó¶Ô DMA ´«ÊäµÄÖ§³Ö
+- LwIP ×é¼þÖÐÔö¼Ó¶Ô MSC ±àÒëÆ÷µÄÖ§³Ö
+- LwIP ×é¼þÖÐÔö¼Ó RT_LWIP_ALIGN_SIZE ÉèÖÃ
+- ÍøÂç½Ó¿Ú¿ÉÒÔÔÙ LwIP ³õʼ»¯ÒÔºóÔÙ½øÐгõʼ»¯
+- minilibc ÖÐÔö¼Ó¸ü¶àµÄ errno
+- newlib ÖÐÍêÉÆÄ£¿é¼ÓÔغóµÄÍ˳ö¹¦ÄÜ
+- ÐÂÔö RT_USING_MEMHEAP_AS_HEAP ¹¦ÄÜ£¬¿ÉÒÔʹÓà memheap ×÷ΪϵͳĬÈ쵀 memory heap
+
+¹¤¾ß£º
+=====
+- ÔÚ building.py ÖÐÖ§³Ö×Ô¶¯Éú³É Visual Studio ¹¤³Ì
+- ÐÂÔö SConsUI ͼÐνçÃ湤¾ß
+
+·ÖÖ§£º
+=====
+- ÐÂÔö PPC405 ·ÖÖ§
+- ÐÂÔö NXP LPC4330 ·ÖÖ§
+
+- ÐÂÔö win32 µÄ simulator ·ÖÖ§
+--ÍêÉƶԱàÒë»·¾³ Visual Studio 2005 ¼°ÒÔÉÏ°æ±¾µÄÖ§³Ö
+--Ö§³Ö finsh
+--Ö§³Ö LWIP
+--Ö§³Ö jffs2£¬elm fatfs£¬uffs
+
+- mini2440 ·ÖÖ§
+-- Ö§³Ö SDHC
+
+- efm32 ·ÖÖ§
+--ÐÞÕý ubuntu Ï GCC ±àÒëµÄ´íÎó
+
+- sam7x ·ÖÖ§
+--ÐÞÕýʹÓÃLwipºó£¬±àÒë´íÎóµÄÎÊÌâ
+
+ÒÔÏÂÊǴ˴ΰ汾·¢²¼Ê±µÄ²âÊÔ»·¾³£º
+windows 7
+ubuntu 10.04 LTS 64-bit
+python 2.7.3
+scons 2.1.0
+IAR 6.30
+MDK 4.53
+arm-2011.09-69-arm-none-eabi.exe
+mips-2011.09-86-mips-sde-elf.exe
+ÒÔÏÂÊÇ google code SVN ÖÐ×Ô RT-Thread 1.0.0 ·¢²¼ºóµÄͳ¼ÆÊý¾Ý£¬¸Ðл¸÷λͬѧ×ö³öµÄŬÁ¦£¬Ê¹µÃ RT-Thread 1.1.0 Õýʽ°æ˳Àû·¢²¼	
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.1.0 RC
+·¢²¼Ê±¼ä: 2012/10/12
+	
+Ô­¼Æ»®ÔÚ2012Äê9ÔÂ30ÈÕ·¢²¼µÄ RT-Thread 1.1.0 Beta2 °æ±¾±ä¸üΪ RT-Thread 1.1.0 RC ÏÖÔÚ·¢²¼ÁË¡£
+RC °æ±¾µÄ·¢²¼Òâζ×ÅÀë RT-Thread 1.1.0 Õýʽ°æµÄ·¢²¼ÒѾ­²»Ô¶ÁË£¬ÔÚRC°æ±¾Ö®ºó£¬½«²»ÔÙÓÐй¦ÄܼÓÈë¡£»¶Ó­´ó¼Ò²âÊÔ£¬ÈÃÎÒÃÇÒ»ÆðÓ­½Ó RT-Thread 1.1.0 Õýʽ°æµÄµ½À´¡£
+
+´Ë´Î·¢²¼Ö÷ÒªÊǼÓÈëÁË USB device stack£»RTGUI ×é¼þÓë github É쵀 RTGUI ¿ª·¢·ÖÖ§±£³Öͬ²½£»
+
+ÒÔÏÂÊÇÏêϸµÄ¸üÐÂÄÚÈÝ£º
+Äںˣº
+=====
+- ɾ³ý rtm.c Îļþ
+- ÐÞÕý timer control ÖÐ timer ±êÖ¾ÉèÖôíÎóµÄÎÊÌâµã
+- rtdef.h ÖÐÐÂÔö¶Ô Microsoft Visual C++ ±àÒëÆ÷µÄ¼ì²é
+- ÐÂÔöÉ豸¿ØÖÆÃüÁî RT_DEVICE_CTRL_BLK_SYNC
+- ÐÂÔöͼÐÎÉ豸¿ØÖÆÃüÁî RTGRAPHIC_CTRL_FILL_RECT ºÍ RTGRAPHIC_CTRL_DRAW_RECT
+- ½«Ä£¿éµÄÏß³ÌÓÅÏȼ¶´ÓÔ­À´µÄ RT_THREAD_PRIORITY_MAX - 1 ±äΪ RT_THREAD_PRIORITY_MAX - 2
+- module ÖÐÐÞÕý section ¿½±´ÎÊÌâµã
+- module ÖÐÐÞÕý Ä£¿éɾ³ýʧ°ÜµÄÎÊÌâ
+
+Îļþϵͳ£º
+=========
+- ÐÞÕý elm fatfs ÖÐ f_seekdir ´æÔÚµÄÎÊÌâ
+- dfs_elm.c ÖÐÐÂÔö½Ó¿Ú ff_memalloc() ºÍ ff_memfree()
+- ÐÞÕý dfs_elm.c Öк¯Êý dfs_elm_open() ´æÔÚµÄÄÚ´æ鶵ÄÎÊÌâ
+- ÐÞÕý dfs_elm.c Öк¯Êý dfs_elm_mount() ´æÔÚµÄδ³õʼ»¯µÄÎÊÌâ
+- ÔÚº¯Êý disk_ioctl() ÖÐÔö¼Ó¶Ô CTRL_SYNC µÄ´¦Àí
+- ÐÂÔö RT_DFS_ELM_CODE_PAGE Ñ¡Ïî
+- DFS POSIX ÖÐÔö¼Ó O_BINARY ±êÖ¾
+- ÐÞÕý ff.c Öк¯Êý mem_cpy() Ôö¼Ó¶Ô×Ö½Úδ¶ÔÆëµÄ´¦Àí
+
+×é¼þ£º
+=====
+- ÐÂÔö USB device stack
+- components_init.c ÖØÃüÃûΪ componets.c
+- components_init.h ÖØÃüÃûΪ componets.h
+- ´®¿ÚÇý¶¯¿ò¼ÜÖÐÔö¼ÓĬÈ쵀 configuration
+- ÐÞÕý serial.c Öк¯Êýrt_serial_control() Ò»´¦±äÁ¿Î´³õʼ»¯µÄÎÊÌâ
+- ɾ³ýº¯Êý rt_ringbuffer_get_datasize()
+- ÐÂÔö pipe ¶Á£¬Ð´£¬´´½¨£¬Ïú»Ù API
+- ÐÂÔö data queue µÄʵÏÖ
+- ÐÞÕý ring buffer Ô½½çÎÊÌâµã
+- ÐÞÕýº¯Êý rt_spi_release_bus() ÖжÏÑÔÅжϴíÎóµÄÎÊÌâµã
+- rtc.c ÖÐ time() º¯ÊýÔö¼Ó open ²Ù×÷
+- MTD NAND ÖÐÐÂÔö move_page ½Ó¿Ú£¬Ìí¼Ómtd_nand³ÉÔ±oob_free£¬¸ü¸Ä³ÉÔ±block_sizeΪpages_per_block
+- LWIP ÖÐÐÂÔöÁ¬½Óʧ°Üºó¹Ø±Õ sock µÄ²Ù×÷
+- USB stack ÖÐÐÂÔö ADK ЭÒéµÄʵÏÖ
+- LWIP Öк¯Êý eth_device_init() Ö屶¨Òå LWIP_DHCP ʱ£¬ÉèÖà NETIF_FLAG_DHCP ±êÖ¾£»µ±¶¨Òå LWIP_IGMP ʱ£¬ÉèÖà NETIF_FLAG_IGMP ±êÖ¾
+- minilibc ÖÐÐÂÔö½Ó¿Ú isspace() ºÍ atol()
+- ɾ³ýÁËÖظ´¶¨ÒåµÄ rt_list_entry
+
+¹¤¾ß£º
+=====
+- ÔÚ building.py ÖÐÐÂÔö MakeCopy(), GlobSubDir() ºÍ GetConfigValue() º¯Êý
+- ÐÂÔö wizard.py - ×Ô¶¯Éú³É SConscript µÄ½Å±¾
+- Ôö¼Ó --copy-header Ñ¡Ï¿½±´ RT-Thread Í·Îļþµ½±¾µØ
+- ÐÞÕý win32 ϵͳÖÐ GNU GCC ·¾¶ÉèÖôíÎóµÄÎÊÌâµã
+- Ôö¼Ó remove_components ¹¦ÄÜ
+
+·ÖÖ§£º
+=====
+- m16c62p ·ÖÖ§
+--ÐÞÕýÈÎÎñ¶ÑÕ»³õʼ»¯Ê±Î´ÉèÖÃÈÎÎñ·µ»ØµØÖ·µÄÎÊÌâ
+
+- upd70f3454 ·ÖÖ§
+--ÐÞÕýÈÎÎñ¶ÑÕ»³õʼ»¯Ê±Î´ÉèÖÃÈÎÎñ·µ»ØµØÖ·µÄÎÊÌâ
+--ÕûÀí BSP Ŀ¼½á¹¹£¬Í³Ò»»®·ÖΪ application ºÍ drivers Ŀ¼
+--Ö§³Ö scons + IAR ±àÒë
+--Ôö¼Ó IAR ¹¤³ÌÄ£°æ
+
+- stm32f0x
+--libcpu ÒÆÖ²´úÂëÖÐÔö¼Ó r8 - r11 ³öÕ»£¬ÈëÕ»²Ù×÷
+
+- mini2440
+--ʹÓÃÐ嵀 RTGUI
+
+ÒÔÏÂÊǴ˴ΰ汾·¢²¼Ê±µÄ²âÊÔ»·¾³£º
+windows 7
+ubuntu 10.04 LTS 64-bit
+python 2.7.3
+scons 2.1.0
+IAR 6.30
+MDK 4.53
+arm-2011.09-69-arm-none-eabi.exe
+mips-2011.09-86-mips-sde-elf.exe
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.1.0 Beta1
+·¢²¼Ê±¼ä: 2012/6/30	
+°´ÕÕ 2012 Äê RT-Thread roadmap£¬¾­¹ý¸÷λͬѧµÄŬÁ¦£¬RT-Thread 1.1.0 Beta1 °æ±¾°´Ê±·¢²¼ÁË£¬´Ë°æ±¾ÒÀÈ»ÊǼ¼ÊõÔ¤ÀÀ°æ£¬Õ¹Ê¾ RT-Thread δÀ´µÄ·¢Õ¹·½Ïò£¬µ«²»ÊʺÏÓÃÓÚ²úÆ·¿ª·¢¡£
+¸Ã°æ±¾Ö÷ÒªÊÇÈ«Ãæ¸üÐÂÁË RTGUI ×é¼þ£»¼ÓÈëÁËеÄÇý¶¯¿ò¼Ü£¨usb host, i2c£¬serial, rtc£©£»×é¼þÖÐÐÂÔö¹Ù·½µÄ CMSIS ¿â£»ÐÂÔö Blackfin BF533 µÄÒÆÖ²£¬³ÉΪ RT-Thread Ö§³ÖµÄµÚÒ»¸ö DSP ·ÖÖ§¡£
+
+ͬʱ¹§Ï² prife ͬѧ³ÉΪ RT-Thread DFS ÐéÄâÎļþϵͳ×齨ά»¤ÈË
+
+ÒÔÏÂÊÇÏêϸµÄ¸üÐÂÄÚÈÝ£º
+Äںˣº
+=====
+- ÐÂÔö3¸öAPI£ºrt_timer_next_timeout_tick(), rt_timer_check(), rt_system_module_init()
+- ÐÞÕý module жÔصÄÎÊÌâ
+- ɾ³ýº¯Êý rt_soft_timer_tick_increase()
+- rt_object_is_systemobject() ·µ»ØÀàÐͱä¸üΪ rt_bool_t
+
+Îļþϵͳ£º
+=========
+- ÐÞÕý fd ÒýÓÃÔ½½çÅжϴíÎóµÄÎÊÌâ
+- posix API ÖУ¬´íÎó·µ»ØʱÉèÖÃÕýÈ·µÄ errno
+
+×é¼þ£º
+=========
+- ÐÂÔö±ê×¼µÄ CMSIS ¿â£¬¿É¹© ARM CORTEX ¸÷·Ö֧ʹÓã¬ÊµÏÖͳһ
+- ÐÂÔöÉ豸Çý¶¯¿ò¼Ü£¨USB host£¬I2C£¬RTC£¬serial£©
+- ÐÂÔöÉ豸Çý¶¯µÄ IPC
+- finsh ÖÐÐÂÔö list_memheap ÃüÁî
+- finsh ÖÐÔö¼Ó×Ô¶¯²¹È«µÄ¹¦ÄÜ
+- finsh ÖÐÔö¼ÓÐÐ×¢Ê͹¦ÄÜ
+- finsh ÖÐÐÞÕýÁËÓÉ Grissiom ·¢ÏÖµÄ finsh_var_delete() ÖеÄÎÊÌâ
+- ×é¼þ³õʼ»¯ÖÐÔö¼Ó RTGUI ϵͳ·þÎñ³õʼ»¯º¯Êý rtgui_system_server_init()
+- minilibc Öнâ¾öÁË䶨Òå RT_USING_DEVICE ʱ£¬GCC ±àÒë³ö´íµÄÎÊÌâ
+- newlib Öнâ¾öÁË䶨Òå RT_USING_DEVICE ʱ£¬GCC ±àÒë³ö´íµÄÎÊÌâ
+- RTGUI ×é¼þÈ«Ãæ¸üУ¬Óë RT-Thread 1.0.x ÖÐµÄ RTGUI ²»¼æÈÝ
+
+·ÖÖ§£º
+=====
+- Ö§³Ö Blackfin DSP µÄÒÆÖ²£¬ÐÂÔö¼Ó BF533 ·ÖÖ§
+- ÐÂÔö¼Ó stm32f0x ·ÖÖ§
+
+- at91sam9260 ·ÖÖ§
+--ÐÂÔö i2c Çý¶¯
+
+- efm32 ·ÖÖ§
+--ÐÂÔö emu Çý¶¯
+--¸üРCMSIS °æ±¾µ½ 3.01
+
+- lpc176x ·ÖÖ§
+--rtconfig.h ÖÐÔö¼Ó CMSIS Ñ¡ÔñÏѡÔñʹÓà BSP ÄÚµÄ CMSIS »òÕßÊÇ RTT ×é¼þÖÐµÄ CMSIS
+--¸üРIAR ¹¤³ÌÄ£°æ
+--ÐÞÕý IAR ¹¤³ÌʹÓÃµÄ link ÎļþÄÚÈÝ
+
+- lpc178x ·ÖÖ§
+--ÐÞÕý GCC ±àÒë´íÎóµÄÎÊÌâ
+--ÅäºÏ RTGUI µÄ¸üУ¬ÔÚ application.c ÖÐ×÷ÏàÓ¦µÄµ÷Õû
+
+- ls1bdev
+--¹æ·¶ÒÆÖ²·Ö֧Ŀ¼½á¹¹£¬·ÖΪ applications ºÍ drivers Á½¸öĿ¼
+--µ÷Õû rtconfig.h£¬Ö§³Ö eclipse µÄ¿ÉÊÓ»¯ÅäÖÃ
+
+- m16c62p ·ÖÖ§
+--¹æ·¶ÒÆÖ²·Ö֧Ŀ¼½á¹¹£¬·ÖΪ applications ºÍ drivers Á½¸öĿ¼
+--Ôö¼Ó IAR ¹¤³ÌÄ£°æ
+
+- mb9bf500r ·ÖÖ§
+--ÅäºÏ RTGUI µÄ¸üУ¬ÔÚ application.c ÖÐ×÷ÏàÓ¦µÄµ÷Õû
+
+- mb9bf506r ·ÖÖ§
+--rtconfig.h ÖÐÔö¼Ó CMSIS Ñ¡ÔñÏѡÔñʹÓà BSP ÄÚµÄ CMSIS »òÕßÊÇ RTT ×é¼þÖÐµÄ CMSIS
+--¹æ·¶ÒÆÖ²·Ö֧Ŀ¼½á¹¹£¬·ÖΪ applications ºÍ drivers Á½¸öĿ¼
+
+- mini2440 ·ÖÖ§
+--¸üРkeil project
+--ÐÞÕý mini2440 ÒÆÖ²ÖУ¬ÉÏÏÂÎÄÇл»Ê±µÄ bug£¬ÓÉ yuxun2k Ìá½»²¹¶¡
+--ÅäºÏ RTGUI µÄ¸üУ¬ÔÚ application.c ÖÐ×÷ÏàÓ¦µÄµ÷Õû
+--ÅäºÏ RTGUI µÄ¸üУ¬ÔÚ calibration.c ÖÐ×÷ÏàÓ¦µÄµ÷Õû
+
+- mini4020 ·ÖÖ§
+--¹æ·¶ÒÆÖ²·Ö֧Ŀ¼½á¹¹£¬·ÖΪ applications ºÍ drivers Á½¸öĿ¼
+
+- sam7x ·ÖÖ§
+--¹æ·¶ÒÆÖ²·Ö֧Ŀ¼½á¹¹£¬·ÖΪ applications ºÍ drivers Á½¸öĿ¼
+
+- stm32f10x ·ÖÖ§
+--rtconfig.h ÖÐÔö¼Ó CMSIS Ñ¡ÔñÏѡÔñʹÓà BSP ÄÚµÄ CMSIS »òÕßÊÇ RTT ×é¼þÖÐµÄ CMSIS
+--ÅäºÏ RTGUI µÄ¸üУ¬ÔÚ application.c ÖÐ×÷ÏàÓ¦µÄµ÷Õû
+--Ôö¼Ó IAR ¹¤³ÌÄ£°å
+
+- stm32f20x ·ÖÖ§
+--¹æ·¶ÒÆÖ²·Ö֧Ŀ¼½á¹¹£¬·ÖΪ applications ºÍ drivers Á½¸öĿ¼
+
+- stm32f107 ·ÖÖ§
+--rtconfig.h ÖÐÔö¼Ó CMSIS Ñ¡ÔñÏѡÔñʹÓà BSP ÄÚµÄ CMSIS »òÕßÊÇ RTT ×é¼þÖÐµÄ CMSIS
+
+ÒÔÏÂÊǴ˴ΰ汾·¢²¼Ê±µÄ²âÊÔ»·¾³£º
+windows 7
+python 2.7.3
+scons 2.1.0
+IAR 6.30
+MDK 4.53
+arm-2011.09-69-arm-none-eabi.exe
+mips-2011.09-86-mips-sde-elf.exe	
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.1.0 Alpha
+·¢²¼Ê±¼ä:¡¡2012/4/16
+	
+°´ÕÕ 2012 Äê RT-Thread roadmap£¬RT-Thread 1.1.0 Alpha °æ±¾·¢²¼£¬´Ë°æ±¾Îª¼¼ÊõÔ¤ÀÀ°æ£¬Õ¹Ê¾ RT-Thread δÀ´µÄ·¢Õ¹·½Ïò£¬µ«²»ÊʺÏÓÃÓÚ²úÆ·¿ª·¢£¬´Ë°æ±¾Ö÷ÒªÊÇÐÂÔöÁË×é¼þ³õʼ»¯Ä£¿é£¬¼ÓÈëÁËеÄÇý¶¯¿ò¼Ü£¨SPI£¬SDIO£©£¬ÐÂÔö jffs2£¬yaffs2 ÎļþϵͳµÄÒÆÖ²£¬eclipse ¿ÉÊÓ»¯ÅäÖà rtconfig.h Ñ¡Ï¾ßÌåµÄ¸üÐÂÄÚÈÝÈçÏ£º
+Äںˣº
+=====
+- Íê³Écomponents initÄ£¿é£¬Í¨¹ý API rt_componets_init(void)£¬Í³Ò»×齨³õʼ»¯Á÷³Ì£¬²Î¿¼ lpc176x
+- src/kservice.h Òƶ¯²¢ÖØÃüÃûΪ include/rtservice.h
+- ÐÂÔört_malloc_align/rt_free_align½Ó¿ÚÓÃÓÚ·ÖÅä¡¢ÊͷŶÔÆëµÄÄÚ´æ
+- ´ò¿ªkservice.cÖеÄRT_PRINTF_PRECISIONºêÒÔÖ§³Ört_kprintfÖеĴø¾«¶È¸ñʽÊä³ö
+- ÐÂÔö memheapÓÃÓÚÔÚ¶îÍâÁ¬ÐøÄÚ´æ¿éÉϹ¹½¨Ò»¸öÄÚ´æ¶Ñ£¬ÌṩÐÂAPI rt_memheap_init()£¬rt_memheap_detach()£¬rt_memheap_alloc()£¬rt_memheap_free()
+- ÐÞÕýº¯Êý rt_mp_init() ºÍ rt_mp_create() ÖÐÄÚ´æ¶ÔÆëµÄÎÊÌâ
+- finsh/cmd.c ÖÐɾ³ýº¯Êý rt_list_isempty()£¬Í³Ò»Ê¹Óà rtservice.h
+- ÐÞÕý¶¯Ì¬¼ÓÔØÄ£¿é module.c ÖÐ module unload ÎÊÌâ
+- ÐÂÔöºê RTTHREAD_VERSION£¬°æ±¾1.1.0µÄ¸ñʽÊÇ10100
+- minilibc/stdint.h ÖУ¬ÐÂÔö int64_t ºÍ uint64_t
+- 1.1.0 °æ±¾ºóÆúÓú¯Êý rt_system_tick_init()
+- ÐÂÔö buildbot Ä£¿é£¬ÊµÏÖÅúÁ¿±àÒë scons ¹¤³Ì
+
+- Ð嵀 DeviceDriver ¿ò¼Ü£º
+* SPI BUS¼°SPI Device
+* SD¿¨¼°ÃæÏò·Ç´æ´¢ÀàÐ͵ÄSDIO¿¨
+* MTD NandÉ豸¼°MTD NorFlashÉ豸
+
+Îļþϵͳ£º
+=========
+- ÐÂÔö jffs2 ÎļþϵͳÒÆÖ²
+- ÐÂÔö yaffs2 ÎļþϵͳÒÆÖ²
+- ¸üРuffs µ½×îа汾£¬²¢Ê¹ÓÃMTD NandÉ豸½Ó¿Ú
+- ÐÞÕý tid->error ±»ÎÞ¹ÊÐ޸ĵÄÎÊÌâ
+
+ÍøÂç×é¼þ£º
+=========
+- lwip ĬÈÏʹÓà v1.4.0 Ìæ»»Ô­À´µÄ v1.3.2
+
+·ÖÖ§£º
+=====
+- Ö§³Ö FPGA ÈíºËµÄÒÆÖ²£¬ÐÂÔö¼Ó microblaze ·ÖÖ§£¬nois-ii ·ÖÖ§
+- ÐÂÔö¼Ó pic32ethernet ·ÖÖ§
+
+- at91sam9260 ·ÖÖ§
+--¸üÐÂÍøÂçÇý¶¯£¬ÐÂÔö sido Çý¶¯
+
+- efm32 ·ÖÖ§
+--ÐÂÔö key ºÍ joystick Çý¶¯£¬¸üРusart Çý¶¯
+
+- lm3s8962 ·ÖÖ§
+--¸üРethernet Çý¶¯£¬Enable reception of multicast packets
+
+- m16c62p ·ÖÖ§
+--Ö§³Ö SCONS/GCC ±àÒë
+
+- fujistu fm3 ·ÖÖ§
+--²ð·Ö fm3 ·Ö֧Ϊ mb9bf506r ºÍ mb9bf500r Á½¸ö¶ÀÁ¢µÄ·ÖÖ§
+
+- stm32f40 ·ÖÖ§
+--¸üРusart Çý¶¯£¬¸üРSTM32F4xx_StdPeriph_Driver µ½°æ±¾ V1.1.0
+
+- mini2440 ·ÖÖ§
+--ÐÂÔö keil project
+
+- x86 ·ÖÖ§
+--Ö§³Ö SCONS/GCC ±àÒë
+
+- lpc178x ·ÖÖ§
+--ÐÂÔö LCD Çý¶¯£¬Ôö¼Ó SDRAM ³õʼ»¯
+
+- lpc176x ·ÖÖ§
+--Ê÷Á¢ RT-Thread 1.1.0 BSP ʾ·¶·ÖÖ§
+--ÌṩȫÌ×±àÒë·½°¸(KEIL ¹¤³Ì£¬IAR ¹¤³Ì£¬SCONS/GCC£¬SCONS/KEIL£¬SCONS/IAR)
+--Ìṩ IAR ¹¤³ÌÄ£°åºÍ KEIL ¹¤³ÌÄ£°å£¬¿ÉÒÔͨ¹ý scons --target=iar -s ×Ô¶¯Éú³É IAR ¹¤³Ì
+--ÖØж¨Òå rtconfig.h Îļþ½á¹¹£¬ÊµÏÖ eclipse ÖпÉÊÓ»¯ÅäÖà rtconfig.h Ñ¡Ïî
+--µ÷Õû BPS Ŀ¼½á¹¹£¬Ó¦ÓÃÏà¹Ø¹éÈë applications Ŀ¼£¬Çý¶¯Ïà¹Ø¹éÈë drivers Ŀ¼£¬¿âÏà¹Ø¹éÈë CMSIS Ŀ¼
+
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+	
+°æ±¾: RT-Thread 1.0.4 
+·¢²¼Ê±¼ä: 2012/12/30
+	
+RT-Thread 1.0.4 ÊÇ 1.0.0 °æ±¾µÄ bug ÐÞÕý°æ,Ò²ÊÇ 1.0.0 ϵÁеÄ×îÖÕ°æ±¾¡£
+RT-Thread 1.0.x ×ÔÕýʽ°æ±¾·¢²¼µ½ÏÖÔÚÒѾ­Î¬»¤ÁËÒ»ÄêÕûʱ¼ä£¬Æڼ䷢²¼ÁË 4 ¸öÐÞ¶©°æ±¾£¬Ä¿Ç°ÒѾ­Ç÷ÓÚ³ÉÊì¡¢Îȶ¨£¬ÍêÈ«Âú×ãÉÌÓÃÐèÇó¡£
+ºóÐøµÄÖصãÎÒÃÇ»áתÒƵ½ RT-Thread 1.1.0 °æ±¾µÄά»¤ÒÔ¼° RT-Thread 1.2.0 °æ±¾µÄ¿ª·¢¡£
+
+1.0.4 °æ±¾½öÔÚÔ­À´µÄ»ù´¡É϶ÔÒÑÓеŦÄܽøÐÐÐÞÕý£¨Ð¹¦ÄÜ»ù±¾ÉÏûÓУ©£¬Ïà¶ÔÓÚ 1.0.3 °æ±¾µÄ¸ü¸ÄÈçÏ£º
+
+1£¬ÐÞÕý DFS ÖÐ O_APPEND ºÍ lseek ÎÊÌâµã
+2£¬ÔÚÉ豸ע²áʱÔö¼ÓÉ豸¼ì²é²½Öè
+3£¬finsh shell ÖÐÖ§³ÖÐÐ×¢ÊÍ
+4£¬ÐÞÕýº¯Êý clock_time_system_init() ÖжԱäÁ¿ _timevalue.tv_usec ³õʼ»¯´íÎóµÄÎÊÌâµã
+5£¬ÔÚº¯Êý fd_get() ÖÐÔö¼Ó¶Ô dfs_fd µÄºÏ·¨ÐÔ¼ì²é
+6£¬É¾³ý rtthread.h ÖÐ rt_sprintf() º¯ÊýµÄÖظ´ÉùÃ÷	
+	
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.0.3
+·¢²¼Ê±¼ä: 2012/10/12
+		
+RT-Thread 1.0.3 ÊÇ 1.0.0 °æ±¾µÄ bug ÐÞÕý°æ£¬½öÔÚÔ­À´µÄ»ù´¡É϶ÔÒÑÓеŦÄܽøÐÐÐÞÕý£¨Ð¹¦ÄÜ»ù±¾ÉÏûÓУ©¡£
+1.0.3 °æ±¾Ïà¶ÔÓÚ 1.0.2 °æ±¾µÄ¸ü¸Ä£º
+
+1£¬lm4f232 ·ÖÖ§¸üРrtconfig.ph
+2£¬ÐÞÕý timer control ÖÐ timer ±êÖ¾ÉèÖôíÎóµÄÎÊÌâµã
+3£¬ÐÞÕýÄ£¿é×é¼þжÔØÎÊÌâµã
+4£¬ÐÞÕýµ± multi-drivers ʹÄܺó dfs_elm_open()µ÷ÓÃʧ°Üºó´æÔÚµÄÒ»´¦ÄÚ´æй¶ÎÊÌâµã
+5£¬ÔÚ ELM FatFs ÎļþϵͳÖÐÔö¼Ó mount ¼ì²é
+6£¬ÐÞÕý f_seekdir ÖдæÔÚµÄÎÊÌâµã
+7£¬ÐÞÕý finsh_var_delete ÖеÄÎÊÌâµã
+8£¬ÐÞÕý LPC178x ·ÖÖ§ÖÐ scons ÅäºÏ armcc ±àÒëʱ·¢Éú´íÎóµÄÎÊÌâµã
+9£¬ÐÞÕý LPC176x ·ÖÖ§ÖÐ scons ÅäºÏ gcc ±àÒëʱ·¢Éú´íÎóµÄÎÊÌâµã
+10£¬LWIP Öк¯Êý eth_device_init() Ö屶¨Òå LWIP_IGMP ʱ£¬ÉèÖà NETIF_FLAG_IGMP ±êÖ¾
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.0.2
+·¢²¼Ê±¼ä: 2012/6/30		
+RT-Thread 1.0.2 ÊÇ 1.0.0 °æ±¾µÄ bug ÐÞÕý°æ£¬½öÔÚÔ­À´µÄ»ù´¡É϶ÔÒÑÓеŦÄܽøÐÐÐÞÕý£¨Ð¹¦ÄÜ»ù±¾ÉÏûÓУ©¡£
+1.0.2 °æ±¾Ïà¶ÔÓÚ 1.0.1 °æ±¾µÄ¸ü¸Ä£º
+
+1£¬DFS ×é¼þÖУ¬ÐÞÕý fd ÒýÓÃÔ½½çÅжϴíÎóµÄÎÊÌâ
+2£¬DFS posix API ÖУ¬´íÎó·µ»ØʱÉèÖÃÕýÈ·µÄ errno
+3£¬LWIP ×é¼þÖУ¬·¢ËÍ mail µ½ TCP Ị̈߳¬Óà rt_mb_send_wait() ´úÌæ rt_mb_send()
+4£¬ÔÚ rtthread.h ÖÐÐÂÔöÁ½¸ö API£ºrt_timer_check(), rt_timer_next_timeout_tick()	
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.0.1
+·¢²¼Ê±¼ä: 2012/4/16
+	
+RT-Thread 1.0.1ÊÇ1.0.0°æ±¾µÄbugÐÞÕý°æ£¬½öÔÚÔ­À´µÄ»ù´¡É϶ÔÒÑÓеŦÄܽøÐÐÐÞÕý£¨Ð¹¦ÄÜ»ù±¾ÉÏûÓУ©¡£1.0.1°æ±¾Ïà¶ÔÓÚ1.0.0°æ±¾µÄ¸ü¸Ä£º
+ÄÚºË
+- ÐÞÕýrt_sem_control/rt_event_control/rt_mb_control/rt_mq_controlÖпÉÄÜÒýÆðµÄÈÎÎñδ¼°Ê±µ÷¶ÈµÄÎÊÌ⣻
+- ÐÞÕýrt_memmoveº¯ÊýµÄÎÊÌ⣻
+- Ôö¼Órt_malloc_align/rt_free_alignµÄ½Ó¿ÚÓÃÓÚµØÖ·¶ÔÆ뷽ʽµÄ·ÖÅäºÍÊÍ·Å£»£¨Ê¹ÓÃrt_malloc_align·ÖÅäµÄÄÚ´æ¿é±ØÐëʹÓÃrt_free_align½Ó¿ÚÊÍ·Å£©
+- ÐÞÕýmemory poolÖÐÄÚ´æ¿éµØÖ·¶ÔÆëµÄÎÊÌ⣻
+- ÐÞÕýÓ¦ÓÃÄ£¿éжÔصÄÎÊÌ⣻
+
+Îļþϵͳ
+- ÐÞÕýumountʱÄÚ´æй©µÄÎÊÌ⣻
+- ÐÞÕýÎļþϵͳÖÐerrno¸³ÖµµÄÎÊÌ⣻
+
+shell
+- ÐÞÕýfinsh_sysvar_appendÌí¼Ó±äÁ¿µÄÎÊÌ⣻
+
+libc
+- minilibc
+* Ôö¼Óint64_t/uint64_tÀàÐͶ¨Ò壻
+- newlib
+* ·ÖÀënewlibÓëDFSµÄ¹ØÁª£»
+* ÐÞÕýʹÄÜlwipʱ£¬timeval½á¹¹Ì嶨Ò彫ʹÓÃnewlibÌṩµÄÀàÐÍ£»
+
+·ÖÖ§
+- Cortex-M4
+* ÐÞÕýʹÄÜFPUʱÈÎÎñÇл»µÄÎÊÌ⣻
+- MB9BF506
+* ÐÞÕýSysTickʱÖÓÖжϺ¯ÊýÃû´íÎóµÄÎÊÌ⣻
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 1.0.0Õýʽ°æ
+·¢²¼Ê±¼ä: 2011/12/31	
+
+RT-Thread´Ó2006Äêµ®Éúµ½ÏÖÔÚÒѾ­5ÄêÁË£¬Àú¾­¶à´Î°æ±¾¸üµü£¨0.2.x£¬0.3.0£¬0.3.3£¬0.4.0 beta1£¬0.4.0 beta2£¬0.4.0 RC1£©
+Äں˸üÎȶ¨£º
+ÔöÇ¿ÉÏÏÂÎļì²éµÄ¹¦ÄÜ£¬¸ü¶àµÄ´íÎó¼ì²é
+
+×é¼þ¸ü·á¸»£º
+ÓÐÎļþϵͳ£¬ÓÐRTGUI£¬Ö§³ÖTCP/IPЭÒéÕ»£¬Ö§³Ö¶¯Ì¬Ä£¿é¼ÓÔØ£¬Ö§³Öposix£¬ÔÚʹÓÃGCCʱ¿ÉÒÔ´ò¿ªnewlibÑ¡Ï֧³ÖÈ«Ì×C±ê×¼ÔËÐпâ
+
+·ÖÖ§ÒÆÖ²¸üÍêÉÆ£º
+Ö§³ÖARM7£¬ARM9£¬ARM Cortex-M3£¬ARM Cortex-M4£¬MIPS£¬AVR32£¬V850EµÈ32λMCU£¬Í¬Ê±Ò²Ö§³ÖÈðÈøµÄ16λMCU M16CϵÁÐ
+
+ËùÒÔÎÒÃǺܸßÐË¿ÉÒÔ·¢²¼RT-Thread 1.0.0°æ±¾ÁË£¬´Ë´ÎÕýʽ°æµÄ·¢²¼Àë²»¿ª¸÷λͬѧµÄÖ§³Ö£¬
+¸ÐлÀîºã·¢ÆðµÄÏßÏÂÍøÓѾۻá
+¸ÐлÉϺ£ÆÖ¶«Èí¼þƽ̨¹«Ë¾ÌṩÖ÷ÌâɳÁú³¡µØ
+¸Ðлgrissiom·­ÒëµÄcoding styleÎĵµ,¼°Ìá½»µÄRTGUIÏà¹Ø²¹¶¡
+¸Ðлonelifeά»¤EFM32·ÖÖ§
+¸Ðл¡£¡£¡£
+
+ÓëRT-Thread 0.4.0 RC1±ÈÆðÀ´£¬RT-Thread 1.0.0Ö÷ÒªÓÐÒÔϵĸüÐÂÄÚÈÝ£º
+
+Äںˣº
+=====
+- Ç¿ÖÆnewlib×é¼þÅäºÏGCCʹÓ㬷ñÔò½«ÔÚ±àÒëʱÌáʾ´íÎó
+- ÐÞÕýobjectÃû×Ö¸´ÖÆÎÊÌâ
+- ÐÂÔöRT-Thread I/O error code(RT_EIO)
+- ÐÂÔöÈý¸öÉ豸ÀàÐÍ£¨RT_Device_Class_SPIBUS, RT_Device_Class_SPIDevice, RT_Device_Class_SDIO£©
+- building.py
+---- ÐÂÔöSrcRemoveº¯Êý
+---- ÐÂÔöMergeGroupº¯Êý
+---- ÐÞÕýÔ´Îļþº¬ÓÐÖÐÎÄÃûµÄÎÊÌâµã
+- Ôö¼Ócoding style˵Ã÷Îĵµ
+
+×é¼þ£º
+=====
+- DFS
+---- ÐÞÕýelmfsÒÆÖ²ÖÐstatfsÎÊÌâ
+---- ÐÞÕýdfs_elm.cÖÐrenameÎÊÌâ
+---- ÐÞÕýdfs_file.cÖÐrenameÎÊÌâ
+---- ÐÞÕýlseekÏÂÒçÎÊÌâ
+-LWIP
+---- ¸üÐÂfinshÃüÁlist_if,set_if£©£¬Ö§³Ömultple interface
+-RTGUI
+---- ¶¨ÒåºêRTGUI_NOTEBOOK_TAB_WIDTH´úÌæÔ­ÏÈʹÓõÄħÊý
+---- ÐÞÕýack_mbÔÚ´íÎó·¢ÉúʱûÓÐdetachµÄÎÊÌâ
+---- ÐÞÕýRTGUI_USING_MOUSE_CURSORÑ¡Ïî´ò¿ªÊ±£¬±àÒë³ö´íÎÊÌâ
+---- ÓÅ»¯notebook´úÂë½á¹¹£¬Ìá¸ß_rt_notebook_ondraw()Ö´ÐÐЧÂÊ
+---- ÓÅ»¯notebook.cÖÐmouseʼþ´¦Àí
+- ÐÞÕýzmordemÒ»´¦Óï·¨´íÎó
+
+Àý³Ì£º
+=====
+---- RTGUIÀý³ÌÖÐÔö¼ÓnotebookµÄdemo
+---- ÐÂÔömem_testÀý³Ì
+---- ¸üÐÂkernel²âÊÔÀý³Ì
+
+·ÖÖ§£º
+=====
+ARM Cortex-M3ϵÁÐоƬµÄÒÆֲͳһʹÓÃ/libcpu/cortex-m3
+ARM Cortex-M4ϵÁÐоƬµÄÒÆֲͳһʹÓÃ/libcpu/cortex-m4
+
+- ÐÂÔöstm32f40x·ÖÖ§
+- ÐÂÔölm4f232·ÖÖ§
+- ÍêÉÆm16c
+---- ÔÚ»ã±àÖÐÕýȷʹÓÃBYTE²Ù×÷Ö¸Áî²Ù×÷rt_thread_switch_interrupt_flag±äÁ¿
+---- ÐÞÕýsconsÅäºÏIAR±àÒë³ö´íµÄÎÊÌâ
+- ÍêÉÆlm3s9b9x·ÖÖ§
+---- ¸üÐÂethÇý¶¯
+---- ÐÂÔösdramÇý¶¯
+- ÍêÉÆstm32·ÖÖ§
+---- ¸üÐÂenc28j60Çý¶¯£¬ÐÞÕýÎÞÏìÓ¦ÎÊÌâµã
+- ÍêÉÆstm32f10x·ÖÖ§
+---- ¸üÐÂtouchÇý¶¯
+---- ¸üÐÂethÇý¶¯
+---- ¸üÐÂrtcÇý¶¯
+---- ÐÞÕýDMA_clear_FlagÉèÖôíÎóµÄÎÊÌâ
+- ÍêÉÆstm32f20x·ÖÖ§
+---- ¸üÐÂeepromÇý¶¯
+---- ¸üÐÂRTCÇý¶¯
+---- ÐÂÔöSPI FRAMÇý¶¯
+- ÍêÉÆefm32·ÖÖ§
+---- ¸üÐÂCMSISºÍefm32libµ½2.3.2
+- ÍêÉÆlpc24xx·ÖÖ§
+---- Ôö¼ÓÒì³£´¦Àíº¯Êý
+- ÍêÉÆlpc2148·ÖÖ§
+---- ÐÞÕýscons+keil±àÒë³ö´íÎÊÌâ
+---- ÐÂÔöthumbģʽµÄÒÆÖ²´úÂë	
+	
+	
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread 0.4.0 RC1
+·¢²¼Ê±¼ä: 2011/10/1
+		
+RT-Thread¾­¹ýÈý¸öÔÂʱ¼äµÄ¿ª·¢²âÊÔ£¨SVNÓÐ100¶à´Î¸üУ©£¬RT-Thread 0.4.0 beta2˳ÀûÑݱäΪRT-Thread 0.4.0 RC1¡£
+
+RC°æ±¾µÄ·¢²¼Òâζ×ÅÀëRT-Thread 0.4.0 Õýʽ°æµÄ·¢²¼ÒѾ­²»Ô¶ÁË£¬ÔÚRC°æ±¾Ö®ºó£¬½«²»ÔÙÓÐй¦ÄܼÓÈë¡£»¶Ó­´ó¼Ò²âÊÔ£¬ÈÃÎÒÃÇÒ»ÆðÓ­½ÓRT-Thread 0.4.0 Õýʽ°æµÄµ½À´¡£
+
+¸üÐÂÂÄÀú
+Äںˣº
+=====
+* ARM cortex M3Ö§³ÖÓ¦ÓÃÄ£¿é
+* RT-ThreadÖÐʵÏÖerrno
+* ÈÎÎñ¿ªÊ¼Ê±µ÷ÓÃÈÎÎñµ÷¶Èº¯Êý
+* ÖØдӦÓÃÄ£¿éµÄmemory allocator
+* ÐÞÕýµ±Ç°ÈÎÎñ±»ÇÀռʱµ÷ÓÃrt_thread_exit()³ö´íµÄÎÊÌâ
+* ÐÞÕýº¯Êýrt_mb_send_wait()£¬½ûÖ¹Ð޸ĵ±Ç°ÈÎÎñµÄerror
+* ÐÞÕýÒ»´¦Æ´Ð´´íÎó
+-- rt_thread_switch_interrput_flag -> rt_thread_switch_interrupt_flag
+* Äں˴úÂëͳһ´úÂë·ç¸ñ
+* Äں˴úÂëͳһʹÓÃunix»»Ðзû'\n'
+
+×é¼þ£º
+=====
+* Lwip
+-- ÖØÐÂÉè¼ÆLwip 1.4.0 ethernetif½Ó¿Úº¯Êý¼°³õʼ»¯Á÷³Ì
+-- ÐÂÔöeth_device_linkchange()º¯Êý
+-- ÐÞÕýÔÚÖжϴ¦ÀíÖе÷ÓÃrt_mb_send()ʱ£¬µ±Ç°ÈÎÎñµÄerror»á±»Ð޸ĵÄÎÊÌâ
+-- ÖØдsys_arch_protect()º¯Êý£¬Ôڸú¯ÊýÄÚ¹ØÖжϲ¢Çҹص÷¶È
+-- ÐÞÕýIssue 11(http://code.google.com/p/rt-thread/issues/detail?id=11)
+-- ÓÅ»¯netio´úÂë
+-- ÐÂÔöfinsh shellÃüÁîlist_tcps()
+-- ¸üÐÂLwip 1.4.0£¬¼æÈݾɵÄÇý¶¯³ÌÐò
+
+* RT GUI
+-- ÐÞÕý»­µãʱ×ø±ê³¬³öDC»º´æµÄÎÊÌâ
+-- ÐÞÕýº¯Êýdc_buffer_fill_rect()ÖУ¬Ç°ºó±³¾°ÑÕÉ«ÏÔʾ´íÎóµÄÎÊÌâ
+-- ÐÞÕýhz×ÖÌå½â³ýÎÊÌâ
+-- ÐÞÕýÖÐÎÄ×ÖÌåÏÔʾ´íÎóÎÊÌâ
+-- ÐÞÕýlist¿Ø¼þµÄ¼üÅÌʼþ´¦ÀíÎÊÌâ
+
+* dfs
+-- ÐÞÕýdfs_romfs_lookup(), dfs_romfs_open()¼°dfs_romfs_lseek()ʵÏÖÖеÄÎÊÌâ
+
+* finsh
+-- ÐÞÕýnode·ÖÅäʧ°ÜµÄÎÊÌâ
+
+·ÖÖ§£º
+=====
+* ÐÂÔöÁúоLS1B·ÖÖ§
+-- Ö§³Öfinsh
+-- Ö§³ÖRT-Gui
+* ¸üÐÂAT91SAM9260·ÖÖ§
+-- Ö§³ÖKeil MDK±àÒë
+-- Õë¶ÔLwip APIµÄ±ä¸ü£¬ÏàÓ¦µÄ¸üÐÂÁËEMACÇý¶¯
+* ¸üÐÂstm32f107·ÖÖ§
+-- ¸üÐÂethÇý¶¯
+-- ¸üÐÂuartÇý¶¯
+* ÐÞÕýrenesas M16CÒÆÖ²
+-- ÍêÉÆÒÆÖ²´úÂë
+-- ÓÃCʵÏÖÉÏÏÂÎÄÇл»£¬ÐÞÕý»ã±à´úÂëÖеIJÎÊý´«µÝ¼Ä´æÆ÷²»È·¶¨µÄÇé¿ö
+* ÐÞÕýNEC V850EÒÆÖ²
+-- ÍêÉÆÒÆÖ²´úÂë
+-- ÓÃCʵÏÖÉÏÏÂÎÄÇл»º¯ÊýÓÃCÓïÑÔʵÏÖ´úÌæ֮ǰµÄ»ã±àʵÏÖ
+* ¸üÐÂEFM32·ÖÖ§
+-- ÐÂÔöAccelerometerÇý¶¯
+-- ÐÂÔöethernetÇý¶¯
+* ¸üÐÂmini2440
+-- ÐÂÔöx35 LCDÇý¶¯
+-- ÍêÉÆtouchÇý¶¯
+* ¸üÐÂavr32uc3b0·ÖÖ§
+-- Ö§³Öscons
+* ¸üÐÂlpc24xx·ÖÖ§
+-- Ö§³Öthumbģʽ
+* ¸üÐÂFM3·ÖÖ§
+-- Ôö¼Óscons+iarµÄ±àÒëÖ§³Ö
+* ¸üÐÂpic32ethernet·ÖÖ§
+-- ÍêÉÆÒÆÖ²´úÂë
+-- Ôö¼ÓuartÇý¶¯
+* ¸üÐÂlpc1114·ÖÖ§
+-- ÐÞÕýsystickÉèÖÃÎÊÌâ
+* ¸üÐÂstm32f20x·ÖÖ§
+-- Ôö¼ÓI2CÇý¶¯
+-- Ôö¼ÓSD¿¨Çý¶¯
+-- Ôö¼ÓRTCÖ§³Ö	
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+°æ±¾: RT-Thread 0.3.4
+·¢²¼Ê±¼ä: 2011/12/31
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+- ¸üÐÂSTM32·ÖÖ§enc28j60Çý¶¯£¬ÐÞÕýÎÞÏìÓ¦ÎÊÌâ
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+°æ±¾: RT-Thread 0.3.3
+·¢²¼Ê±¼ä: 2011/9/30
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+°æ±¾: RT-Thread 0.3.2Õýʽ°æ
+·¢²¼Ê±¼ä: 2011/7/4
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+Ìû×ÓÓÉ lgnq ? 2011Äê 7ÔÂ 4ÈÕ 15:46
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+* ÄÚºËÖÐÐÞÕýÔÚΪ¿ÕµÄmemory¿éÉϽøÐÐrt_reallocʱµÄÎÊÌ⣻
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+Ô­À´µÄbranches/rtt_0_3_2·ÖÖ§¸ü¸ÄΪbranches/rtt_0_3_3¡£
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+´úÂ룺http://code.google.com/p/rt-thread/downloads/detail?name=RT-Thread-0.3.2.zip
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+°æ±¾: RT-Thread 0.4.0 beta2
+·¢²¼Ê±¼ä: 2011/7/4
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+** stm32F20x·ÖÖ§
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+*** ¸üРSTM32F10x_StdPeriph_Lib_V3.5.0
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+** ×Ô¶¯´´½¨IAR¹¤³Ì
+** ×Ô¶¯´´½¨MDK4¹¤³Ì 
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+°æ±¾: RT-Thread 0.4.0 beta1
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+//----------------------------------------------------------------------------------------
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+·¢²¼Ê±¼ä: 2010/9/29
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+
+STM32·ÖÖ§
+---------
+Çë×¢ÒâSTM32·ÖÖ§µÄ¹¤³ÌÎļþ×éÖ¯·½Ê½ºÍ0.3.0°æ±¾ÖеIJ»Ò»Ñù£¬Ô­À´µÄ¼¸¸öĿ¼ÊDz»Ïà¶ÀÁ¢µÄ¹¤³Ì£¬¶ø0.3.1ÖÐΪÁ˱ÜÃâ»ìÏý£¬°ÑËüÃDZä³ÉÁ˶ÀÁ¢µÄ¹¤³Ì(×¢£ºÒòΪ0.3.1Óë0.3.0ÊÇÍêÈ«¼æÈݵģ¬ËùÒÔ²»Ò»¶¨Òª¸üÐÂBSPĿ¼)¡£
+
+project_107ÊÇÕë¶ÔSTM32F107оƬµÄ¹¤³Ì£¬project_valuelineÊÇÕë¶ÔSTM32F100оƬ STM32 Discovery¿ª·¢°æµÄ¹¤³Ì£¬ÆäÓàµÄоƬĬÈÏÊÇSTM32F103ZE¡£Èç¹ûÒªÐ޸ijÉ×Ô¼ºËùÐèÒªµÄоƬ£¬Çë×ñѭһϲ½Ö裺
+* ÔÚboard.hÎļþÖÐÐÞ¸ÄSTM32_SRAM_SIZEºê¶¨Ò壬ËüµÄµ¥Î»ÊÇKB£¬ËùÒÔÕë¶ÔÓÚSTM32F103VBÀàÐ͵ÄоƬ£¬Ö»ÐèÒª°ÑËü¶¨Òå³É20¼´¿É¡£
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+* ÔÚ¹¤³ÌÑ¡ÏîµÄC±àÒëÆ÷Ô¤¶¨ÒåÉÏ£¬Ð޸ijɺÍоƬƥÅäµÄÀàÐÍ£¬ÀýÈçSTM32F10X_HD¡¢STM32F10X_MDµÈ¡£
+
+ÁíÍ⣬STM32·ÖÖ§Ö§³ÖIAR±àÒëÆ÷£¬ÔÚʹÓÃIAR ARMʱ£¬Èç¹ûÄãʹÓÃÁËfinsh£¬Çë×¢Ò⣬×îºÃÔÚÁ´½ÓÅäÖÃÎļþÖмÓÈë
+keep { section FSymTab };
+keep { section VSymTab };
+ËüµÄ×÷ÓÃÊÇΪÁ˱£ÁôfinshÖÐʹÓõ½µÄ·ûºÅ±í£¬ÒòΪÕâЩ·ûºÅ±í½öÔÚÃüÁîÐб»µ÷Óã¬ËùÒÔËûÃÇ¿ÉÄÜÔÚ×îºóÉú³ÉÄ¿±êÎļþʱ±»ÓÅ»¯µô¡£
+
+¾ßÌåÇë¿´stm32f10x_flash.icfÎļþ¡£
+
+LM3S·ÖÖ§
+--------
+LM3S·Ö֧ĬÈϲÉÓÃLM3S8962оƬ£¬Õë¶ÔµÄÊÇTIÕâ´Î·¢µÄ48£¤ 8962¿ª·¢°å¡£
+
+LPC176x·ÖÖ§
+-----------
+¹¤³ÌĬÈÏ°üÀ¨finsh shell£¬Îļþϵͳ£¬ÍøÂçЭÒéÕ»µÄÖ§³Ö¡£
+
+(*) Ï£ÍûʹÓÃÐÂÌØÐԵĿª·¢ÈËÔ±Çë¹Ø×¢ºóÐø0.4.0°æ±¾µÄ·¢²¼Çé¿ö£¬0.4.0°æ±¾Ìí¼ÓÁ˺ܶàµÄÐÂÌØÐÔ£¬ÀýÈ磺16λµÄÈðÈøM16·ÖÖ§£¬´ó¶ËģʽµÄAVR32·ÖÖ§£¬ÒÔ¼°MIPS·ÖÖ§µÈ¡£	
+
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+
+°æ±¾: RT-Thread 0.3.0Õýʽ°æ
+·¢²¼Ê±¼ä: 2010/3/30
+		
+Ïà½ÏÒÔÇ°µÄRT-Thread 0.3.0 RC°æ±¾£¬ÎÞ´óµÄÐ޸ģ¨consoleµ÷ÕûΪ֧³ÖÉ豸µÄģʽ£©£¬µ«ÒÀÈ»½¨ÒéËùÓÐʹÓÃ0.2.x¡¢0.3.0 beta/rc°æµÄÓû§¶¼¿ªÊ¼Ê¹ÓÃ0.3.0Õýʽ°æ¡£µ±Ç°°æ±¾Ö§³ÖÈçÏÂÒÆÖ²·ÖÖ§£º
+- ARM Cortex-M3ϵÁУºSTM32£¨°üº¬STM32F107£©£¬LM3S£¬LPC1766
+- ARM7TDMIϵÁУºLPC2148£¬LPC2478£¬AT91SAM7X256£¬AT91SAM7S
+- ARM920TϵÁУºS3C2440£¨mini2440£©
+- IA32£ºQEMU¼°ÕæʵµÄx86»úÆ÷
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+RT-ThreadÔÚGoogle SVN·þÎñÆ÷ÉϵĿª·¢·ÖÖ§Òà×öÁËÏàÓ¦µ÷Õû£º
+Ô­À´µÄ¿ª·¢Ö÷¸É£¨trunk£©¸ü¸ÄΪbranches/rtt_0_3_1
+µ±Ç°µÄ¿ª·¢Ö÷¸É£¨trunk£©×÷Ϊµ±Ç°µÄRT-Thread 0.4.x¿ª·¢·ÖÖ§¼ÌÐøÇ°½ø¡£
+
+RT-Thread 0.3.1°æ±¾½«ÔÚÄ¿Ç°µÄ0.3.0Õýʽ°æÉϽøÐв¹¶¡ÐÞÕý£¬²¢ÇÒµ±0.4.x·Ö֧һЩÓÐÓõġ¢Îȶ¨¹¦ÄÜÒ²»áǨÒÆ»á0.3.x ·ÖÖ§¡£
+
+ºóÐø»á½Ðø¼ÓÈëһЩAppNotes¡£
+
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+STM3210·ÖÖ§
+Keil MDK¹¤³ÌÎļþλÓÚbsp\stm3210Ŀ¼Ï£¬½öÊÇ»ù±¾µÄled¹¤³Ì£»
+ϵͳĬÈϲÉÓÃSTM32F103ZEоƬ£¬ÆäËûоƬÐèÒªÐ޸ĵÄλÖãº
+- ¸ù¾ÝоƬƬÄÚSRAM´óСÐÞ¸Äboard.hÎļþ
+- Èç¹ûÊÇSTM32F107£¬ÇëÖ±½ÓʹÓÃproject_107Ŀ¼ÏµĹ¤³Ì(¼ûÏÂÃæÏêϸµÄʹÓÃ˵Ã÷)
+
+ͬʱÔÚbsp\stm3210Ŀ¼Ï»¹´æÔÚ¶à¸öÒÔproject_¿ªÍ·µÄĿ¼£¬ÕâЩÏàÓ¦µÄÕë¶Ô²»Í¬ÀàÐ͵Ť³Ì£¬ÀýÈçproject_finshÕë¶ÔÔÚRT-ThreadÖÐʹÓÃfinsh shellµÄÇé¿ö¡£µ±ÐèҪʹÓÃÕâЩ¹¤³Ìʱ£¬ÐèÒª°ÑÏàÓ¦project_xxxĿ¼ÖеÄÎļþ¶¼¸´ÖƵ½ stm3210Ŀ¼ÖÐ(Ö±½ÓͬÃû¸²¸ÇµÄ·½Ê½)£¬È»ºóÔÙÐдò¿ªstm3210Ŀ¼ÏµĹ¤³ÌÎļþ¡£
+
+LM3S·ÖÖ§
+LM3SµÄKeil MDK¹¤³ÌÎļþ·ÅÔÚbsp\lm3sĿ¼Ï£»Õë¶ÔLM3S8962оƬ(ÒòΪÕâ¸öTIË͵ÄÊÇ´øÕâ¸öоƬµÄ¿ª·¢°å)£¬ÐèÒªÔÚ board.hÖÐ
+// For lm3s8962, it should be SYSCTL_XTAL_8MHZ
+#define LM3S_XTAL_TYPE SYSCTL_XTAL_6MHZ
+
+°ÑÈçÉÏÕâ¸ö¶¨Òå¸ü¸ÄΪSYSCTL_XTAL_8MHZ£¬·ñÔòµÃ»°»áËøËÀJTAG¡£	
+	
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread/LM3S 0.3.0 RC1°æ·¢²¼
+·¢²¼Ê±¼ä: 2010/1/4
+
+ʵʱÏ̲߳Ù×÷ϵͳÊÇÒ»¿îÃæÏòʵʱÁìÓòµÄ²Ù×÷ϵͳ£¬Õâ¸öºÍͨ³£µÄͨÓòÙ×÷ϵͳÓÐןܴóµÄ²»Í¬¡£Í¨ÓòÙ×÷ϵͳͨ³£Ãæ¶ÔµÄÊÇÈÕ³£Ó¦Óã¬ÀýÈç´ò¿ªä¯ÀÀÆ÷ÉÏÍø£¬²¥·ÅÒôÀÖ£¬²ÉÓÃ×Ö´¦ÀíÈí¼þ±à¼­Îĵµ¡£
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+ʵʱϵͳºÍÕâÖÖͨÓÃϵͳÓкܴóµÄ²î±ð¡£ÊµÊ±ÏµÍ³Ö¸µÄÊÇ£¬µ±Íâ½çÓÐϵͳ¹Ø×¢µÄÏàӦʼþ·¢Éúʱ£¬ÏµÍ³Äܹ»ÔÚÖ¸¶¨µÄʱ¼äÄÚ£¨deadline£©½øÐÐÕýÈ·µÄÏìÓ¦¡£ÓÃÓÚʵʱϵͳµÄ²Ù×÷ϵͳ¾Í½Ð×öʵʱ²Ù×÷ϵͳ¡£´ÓϵͳµÄ¶¨ÒåÒ²¿ÉÒÔ¿´µÃ³ö£¬ÊµÊ±²Ù×÷ϵͳºÍͨÓòÙ×÷ϵͳÔÚÊÂÎñµÄ´¦ÀíÉÏÓÐÃ÷ÏÔµÄÇø±ð£¬ÊµÊ±²Ù×÷ϵͳÓзdz£Ç¿µÄÕë¶ÔÐÔ£¬¶ÔÏàÓ¦µÄʼþÁ¦Çó×öµ½Õâ¹Ì¶¨µÄʱ¼äÄÚ½øÐÐÏìÓ¦£»¶øͨÓòÙ×÷ϵͳÔòÐèҪŬÁ¦µØ×öµ½¸÷¸öÊÂÎñµÄ¹«Æ½ÐÔ£¨Ä³Ð©ÏµÍ³Ò²»á·Ç³£×¢ÒâÊý¾ÝµÄÍÌÍÂÁ¿£¬ÀýÈçÍøÂç·þÎñÆ÷£©¡£
+ʵʱÏ̲߳Ù×÷ϵͳ£¨Ó¢ÎÄÃûRT-Thread£©ÃæÏòµÄÕýÊÇÕâôһÀàµÄʵʱϵͳ£¬ÒòΪÆäСÐ͵ÄÌصãÒ²¿ÉÒÔ¿´³ÉÊÇÒ»¸öǶÈëʽ²Ù×÷ϵͳ£¨Ç¶Èëʽϵͳһ°ãÊÇÕë¶ÔһЩרÓÐÄ¿µÄ¶ø´æÔÚ£¬±È½ÏÁßØÄÓڳɱ¾¡£¶ø»ùÓÚרÓÐÄ¿µÄµÄÌص㣬Ҳע¶¨ÁËǶÈëʽϵͳ»ò¶à»òÉٵľßÓÐһЩʵʱÐÔµÄÌص㣩¡£ÕâÖÖϵͳ¿ÉÒÔÓÃÓÚ×Ô¶¯ÊÛƱ»ú£¬Ë°¿Ø»ú£¬Òƶ¯Í¨ÐÅÉ豸£¬mp3/mp4µÈ±ãЯʽÒôÀÖÉ豸£¬·ÉÐÐÆ÷¿ØÖÆ£¬³µÌåµ¼º½¿ØÖÆ£¬´òÓ¡»ú£¬¸´Ó¡»ú£¬¸÷Àà¼à¿ØÉ豸£¬Â·ÓÉÆ÷£¬ADSL£¬»ú¶¥ºÐµÈÍøÂçÉ豸£¬Ò½ÁÆÉ豸µÈµÈ¡£
+TIÁ÷Ã÷LM3SϵÁÐоƬÊÇ»ùÓÚARM Cortex M3 v7¹¹¼ÜµÄ32λоƬ£¬ÆäÖÐLM3S S6000£¬S8000£¬S9000ϵÁÐоƬЯ´øÍøÂ繦ÄÜ¡£RT-ThreadµÄ±ê×¼Äں˿ÉÒÔÔËÐÐÔÚ³ýLM3S S100ϵÁÐÍâµÄËùÓÐϵÁÐоƬÉÏ¡£Õâ´ÎRT-ThreadÕë¶ÔÓÚLM3S½øÐÐÒÆÖ²ÑéÖ¤²¢¾­¹ýѹÁ¦²âÊÔµÄÊÇLM3S6918оƬ£¬Ð¾Æ¬Ð¯´ø64KƬÄÚ¾²Ì¬Äڴ棬256KÉÁ´æ£¬ÆµÂÊÊÇ50MHz¡£ÔÚÕâ¸öƽ̨ÉÏ£¬RT-ThreadÖ§³ÖµÄÌØÐÔ°üÀ¨£º
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+? LwIPÇáÐÍTCP/IPЭÒéÕ»
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+? ¿ª·¢»·¾³Ö§³Ö£º
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+
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+
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+RT-Thread/LM3S
+NETIO - Network Throughput Benchmark, Version 1.26
+(C) 1997-2005 Kai Uwe Rommel
+TCP connection established.
+Packet size 1k bytes: 704 KByte/s Tx, 5131 Byte/s Rx.
+Packet size 2k bytes: 704 KByte/s Tx, 1950 KByte/s Rx.
+Packet size 4k bytes: 704 KByte/s Tx, 2197 KByte/s Rx.
+Packet size 8k bytes: 704 KByte/s Tx, 2200 KByte/s Rx.
+Packet size 16k bytes: 706 KByte/s Tx, 2196 KByte/s Rx.
+Packet size 32k bytes: 709 KByte/s Tx, 2136 KByte/s Rx.
+Done.
+
+TI/ÎÞ²Ù×÷ϵͳÇé¿öϵÄLwIP
+NETIO - Network Throughput Benchmark, Version 1.26
+(C) 1997-2005 Kai Uwe Rommel
+TCP connection established.
+Packet size 1k bytes: 870 KByte/s Tx, 5187 Byte/s Rx.
+Packet size 2k bytes: 870 KByte/s Tx, 2463 KByte/s Rx.
+Packet size 4k bytes: 870 KByte/s Tx, 3322 KByte/s Rx.
+Packet size 8k bytes: 870 KByte/s Tx, 3239 KByte/s Rx.
+
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+»ù±¾ÈÎÎñ²âÊÔ RTT/ecos 1.40±¶
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+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+	
+°æ±¾: RT-Thread RTOS v0.2.3°æ±¾
+·¢²¼Ê±¼ä: 2008/10/6
+		
+¸üмǼ
+- Ìí¼ÓslabÄÚ´æ¹ÜÀíÆ÷£»
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+- Ìí¼Ólwip×öΪRT-ThreadµÄTCP/IPЭÒéÕ» £¨0.2.3°üº¬AT91RM9200Íø¿¨Çý¶¯£¬¼°QEMU/s3c2410ÐéÄâµÄrtl8019Íø¿¨Çý¶¯£©£»
+- Ìí¼ÓC++ÌØÐÔÖ§³Ö£»
+- finshÖÐÌí¼Ó¶¯Ì¬Ìí¼Óϵͳµ÷Óü°ÏµÍ³±äÁ¿µÄAPI£»
+- ÐÞÕýrt_int*_t¶¨ÒåΪÏÔʽµÄsigned¶¨Ò壻
+- ÐÞÕýÏ̳߳¬Ê±º¯ÊýµÄÎÊÌ⣻
+- ÐÞÕýÁ´±íÖгõʼ»¯ÎÊÌ⣻
+- ÐÞÕýObjectÖе÷Óù³×Óº¯ÊýµÄÎÊÌ⣻
+
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------	
+°æ±¾: RT-Thread v0.2.2
+·¢²¼Ê±¼ä: 2008/6/12	
+RT-Thread v0.2.2µ¥ÄÚºËÕýʽ°æ·¢²¼£¬Õâ¸ö°æ±¾Ö÷ÒªÊÇÔö¼Ó¸ü¶àµÄBSPÒÆÖ²£º
+- s3c44b0µÄÒÆÖ² [Xu Xinming]
+- AT91SAM7S64µÄÒÆÖ² [Bernard Xiong£¬¸Ðлicdev.com.cnÌṩ¿ª·¢°å]
+
+ÒÔϵÄÒÆÖ²ÈÔÈ»ÊÇÊÔÑéÐÔÖʵÄ
+- NDSÕÆÉÏÓÎÏ·»úµÄÒÆÖ²[vai]
+- ia32µÄÒÆÖ²[Qiu Yi]£¬ÔÚQEMUÐéÄâ»úÖвâÊÔÍê³É
+
+ÒÔÏÂÊǸ÷¸öÒÆÖ²µÄһЩ˵Ã÷£º
+AT91SAM7S64: (ϵͳ×ÊÔ´£º16k RAM£¬64k ROM Flash)
+ΪÅäºÏСÄÚ´æÇé¿ö£¬RT-Thread 0.2.2Ö§³ÖÈÎÎñ×î´óÓÅÏȼ¶Îª32µÄÇé¿ö£¬ÒÔ±£Ö¤ÄÚ´æÕ¼ÓøüС£¨ËùÓжþ½øÖÆ´úÂëСÓÚ10k£©
+ÔÚAT91SAM7S64ÒÆÖ²ÖУ¬´®¿Ú²¢Ã»´ò¿ª£¬finshҲûÆôÓá£
+ÔÚbsp/icdevs64/buildĿ¼Ï¸½´øuVisionµÄ¹¤³ÌÎļþ£¬ÐèÒª»úÆ÷ÉÏ°²×°ÓÐkeilµÄgcc±àÒëÆ÷
+
+ia32:
+Ö§³Öi386-elf-gcc for windowsµÄ±àÒ룬linuxϵĻ¹Ã»ÊÔ£¬Ó¦¸ÃÒ²¿ÉÒÔ˳Àû±àÒë¡£
+±àÒëÍê³ÉºóÔÚbsp/qemuĿ¼ÏÂÉú³Értthread-qemu.elf
+°ÑÕâ¸öelfÎļþÅäÖõ½grubµÄÅäÖÃÎļþÖУ¬¾ßÌåµÄgrubÅäÖÃÇë²Î¿´grubÎĵµ				
\ No newline at end of file

From 005014e7d0026249078b37e718200da55990928e Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sun, 13 Jul 2014 07:27:57 +0800
Subject: [PATCH 38/86] [Drivers] Add workqueue implementation.

---
 components/drivers/include/rtdevice.h |  34 +++++++++
 components/drivers/src/workqueue.c    | 102 ++++++++++++++++++++++++++
 2 files changed, 136 insertions(+)
 create mode 100644 components/drivers/src/workqueue.c

diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h
index dac85eb716..dc9761032e 100644
--- a/components/drivers/include/rtdevice.h
+++ b/components/drivers/include/rtdevice.h
@@ -20,6 +20,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2012-01-08     bernard      first version.
+ * 2014-07-12     bernard      Add workqueue implementation.
  */
 
 #ifndef __RT_DEVICE_H__
@@ -143,6 +144,21 @@ struct rt_data_queue
     void (*evt_notify)(struct rt_data_queue *queue, rt_uint32_t event);
 };
 
+/* workqueue implementation */
+struct rt_workqueue
+{
+	rt_list_t   work_list;
+	rt_thread_t work_thread;
+};
+
+struct rt_work
+{
+	rt_list_t list;
+
+	void (*work_func)(struct rt_work* work, void* work_data);
+	void *work_data;
+};
+
 /**
  * Completion
  */
@@ -274,6 +290,24 @@ rt_err_t rt_data_queue_peak(struct rt_data_queue *queue,
                             rt_size_t            *size);
 void rt_data_queue_reset(struct rt_data_queue *queue);
 
+#ifdef RT_USING_HEAP
+/**
+ * WorkQueue for DeviceDriver
+ */
+struct rt_workqueue *rt_workqueue_create(const char* name, rt_uint16_t stack_size, rt_uint8_t priority);
+rt_err_t rt_workqueue_destroy(struct rt_workqueue* queue);
+rt_err_t rt_workqueue_dowork(struct rt_workqueue* queue, struct rt_work* work);
+rt_err_t rt_workqueue_cancel_work(struct rt_workqueue* queue, struct rt_work* work);
+
+rt_inline void rt_work_init(struct rt_work* work, void (*work_func)(struct rt_work* work, void* work_data), 
+    void* work_data)
+{
+    rt_list_init(&(work->list));
+    work->work_func = work_func;
+    work->work_data = work_data;
+}
+#endif
+
 #ifdef RT_USING_RTC
 #include "drivers/rtc.h"
 #ifdef RT_USING_ALARM
diff --git a/components/drivers/src/workqueue.c b/components/drivers/src/workqueue.c
new file mode 100644
index 0000000000..52f6002595
--- /dev/null
+++ b/components/drivers/src/workqueue.c
@@ -0,0 +1,102 @@
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef RT_USING_HEAP
+static void _workqueue_thread_entry(void* parameter)
+{
+	struct rt_work* work;
+	struct rt_workqueue* queue;
+	
+	queue = (struct rt_workqueue*) parameter;
+	RT_ASSERT(queue != RT_NULL);
+
+	while (1)
+	{
+		if (rt_list_isempty(&(queue->work_list)))
+		{
+			/* no software timer exist, suspend self. */
+			rt_thread_suspend(rt_thread_self());
+			rt_schedule();
+		}
+
+		/* we have work to do with. */
+		rt_enter_critical();
+		work = rt_list_entry(queue->work_list.next, struct rt_work, list);
+		rt_list_remove(&(work->list));
+		rt_exit_critical();
+
+		/* do work */
+		work->work_func(work, work->work_data);
+	}
+}
+
+struct rt_workqueue *rt_workqueue_create(const char* name, rt_uint16_t stack_size, rt_uint8_t priority)
+{
+	struct rt_workqueue *queue = RT_NULL;
+
+	queue = (struct rt_workqueue*)RT_KERNEL_MALLOC(sizeof(struct rt_workqueue));
+	if (queue != RT_NULL)
+	{
+        /* initialize work list */
+        rt_list_init(&(queue->work_list));
+        
+		/* create the work thread */
+		queue->work_thread = rt_thread_create(name, _workqueue_thread_entry, queue, stack_size, priority, 10);
+		if (queue->work_thread == RT_NULL)
+		{
+			RT_KERNEL_FREE(queue);
+			return RT_NULL;
+		}
+
+		rt_thread_startup(queue->work_thread);
+	}
+
+	return queue;
+}
+
+rt_err_t rt_workqueue_destroy(struct rt_workqueue* queue)
+{
+	RT_ASSERT(queue != RT_NULL);
+
+	rt_thread_delete(queue->work_thread);
+	RT_KERNEL_FREE(queue);
+
+	return RT_EOK;
+}
+
+rt_err_t rt_workqueue_dowork(struct rt_workqueue* queue, struct rt_work* work)
+{
+	RT_ASSERT(queue != RT_NULL);
+	RT_ASSERT(work != RT_NULL);
+
+	rt_enter_critical();
+	/* NOTE: the work MUST be initialized firstly */
+	rt_list_remove(&(work->list));
+
+	rt_list_insert_after(queue->work_list.prev, &(work->list));
+	if (queue->work_thread->stat != RT_THREAD_READY)
+	{
+		rt_exit_critical();
+		/* resume work thread */
+		rt_thread_resume(queue->work_thread);
+		rt_schedule();
+	}
+	else rt_exit_critical();
+
+	return RT_EOK;
+}
+
+rt_err_t rt_workqueue_cancel_work(struct rt_workqueue* queue, struct rt_work* work)
+{
+	RT_ASSERT(queue != RT_NULL);
+	RT_ASSERT(work != RT_NULL);
+
+	rt_enter_critical();
+	rt_list_remove(&(work->list));
+	rt_exit_critical();
+
+	return RT_EOK;
+}
+
+#endif
+

From e152b68e33515da64c4e4a3d5d3339d34f98018f Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@gmail.com>
Date: Sun, 13 Jul 2014 14:13:39 +0800
Subject: [PATCH 39/86] add the lpc43xx bsp support.

---
 .../CMSIS/Include/arm_common_tables.h         |    93 +
 .../Libraries/CMSIS/Include/arm_math.h        |  7306 ++++
 .../Libraries/CMSIS/Include/core_cm0.h        |   682 +
 .../Libraries/CMSIS/Include/core_cm0plus.h    |   793 +
 .../Libraries/CMSIS/Include/core_cm3.h        |  1627 +
 .../Libraries/CMSIS/Include/core_cm4.h        |  1772 +
 .../Libraries/CMSIS/Include/core_cm4_simd.h   |   673 +
 .../Libraries/CMSIS/Include/core_cmFunc.h     |   636 +
 .../Libraries/CMSIS/Include/core_cmInstr.h    |   688 +
 .../Libraries/CMSIS/Include/core_sc000.h      |   813 +
 .../Libraries/CMSIS/Include/core_sc300.h      |  1598 +
 .../Device/NXP/LPC43xx/Include/LPC43xx.h      | 34895 ++++++++++++++++
 .../Device/NXP/LPC43xx/Include/fpu_enable.h   |    33 +
 .../Device/NXP/LPC43xx/Include/fpu_init.h     |    29 +
 .../NXP/LPC43xx/Include/system_LPC43xx.h      |    50 +
 .../Source/Templates/ARM/startup_LPC43xx.s    |   339 +
 .../Source/Templates/ARM/startup_LPC43xx_M0.s |   255 +
 .../Source/Templates/GCC/cr_startup_lpc43xx.c |   502 +
 .../Templates/GCC/cr_startup_lpc43xx_m0sub.c  |   463 +
 .../Source/Templates/IAR/startup_LPC43xx.s    |   431 +
 .../Templates/IAR/startup_lpc43xx_m0sub.s     |   242 +
 .../LPC43xx/Source/Templates/system_LPC43xx.c |   892 +
 bsp/lpc43xx/Libraries/Device/SConscript       |    30 +
 bsp/lpc43xx/Libraries/SConscript              |    15 +
 bsp/lpc43xx/M0/SConscript                     |    13 +
 bsp/lpc43xx/M0/SConstruct                     |    29 +
 bsp/lpc43xx/M0/rtconfig.h                     |   230 +
 bsp/lpc43xx/M0/rtconfig.py                    |   139 +
 bsp/lpc43xx/M0/template.uvopt                 |   349 +
 bsp/lpc43xx/M0/template.uvproj                |   777 +
 bsp/lpc43xx/M4/SConscript                     |    13 +
 bsp/lpc43xx/M4/SConstruct                     |    29 +
 bsp/lpc43xx/M4/rtconfig.h                     |   230 +
 bsp/lpc43xx/M4/rtconfig.py                    |   139 +
 bsp/lpc43xx/M4/template.uvopt                 |   349 +
 bsp/lpc43xx/M4/template.uvproj                |   777 +
 bsp/lpc43xx/applications/SConscript           |    11 +
 bsp/lpc43xx/applications/application.c        |    84 +
 bsp/lpc43xx/applications/startup.c            |    74 +
 bsp/lpc43xx/drivers/SConscript                |    14 +
 bsp/lpc43xx/drivers/board.c                   |    77 +
 bsp/lpc43xx/drivers/board.h                   |    60 +
 bsp/lpc43xx/drivers/drv_emac.c                |   536 +
 bsp/lpc43xx/drivers/drv_emac.h                |   291 +
 bsp/lpc43xx/drivers/drv_led.c                 |   161 +
 bsp/lpc43xx/drivers/drv_led.h                 |    12 +
 bsp/lpc43xx/drivers/drv_uart.c                |   315 +
 bsp/lpc43xx/drivers/drv_uart.h                |   228 +
 48 files changed, 59794 insertions(+)
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0plus.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cm3.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4_simd.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cmFunc.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_cmInstr.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_sc000.h
 create mode 100644 bsp/lpc43xx/Libraries/CMSIS/Include/core_sc300.h
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
 create mode 100644 bsp/lpc43xx/Libraries/Device/SConscript
 create mode 100644 bsp/lpc43xx/Libraries/SConscript
 create mode 100644 bsp/lpc43xx/M0/SConscript
 create mode 100644 bsp/lpc43xx/M0/SConstruct
 create mode 100644 bsp/lpc43xx/M0/rtconfig.h
 create mode 100644 bsp/lpc43xx/M0/rtconfig.py
 create mode 100644 bsp/lpc43xx/M0/template.uvopt
 create mode 100644 bsp/lpc43xx/M0/template.uvproj
 create mode 100644 bsp/lpc43xx/M4/SConscript
 create mode 100644 bsp/lpc43xx/M4/SConstruct
 create mode 100644 bsp/lpc43xx/M4/rtconfig.h
 create mode 100644 bsp/lpc43xx/M4/rtconfig.py
 create mode 100644 bsp/lpc43xx/M4/template.uvopt
 create mode 100644 bsp/lpc43xx/M4/template.uvproj
 create mode 100644 bsp/lpc43xx/applications/SConscript
 create mode 100644 bsp/lpc43xx/applications/application.c
 create mode 100644 bsp/lpc43xx/applications/startup.c
 create mode 100644 bsp/lpc43xx/drivers/SConscript
 create mode 100644 bsp/lpc43xx/drivers/board.c
 create mode 100644 bsp/lpc43xx/drivers/board.h
 create mode 100644 bsp/lpc43xx/drivers/drv_emac.c
 create mode 100644 bsp/lpc43xx/drivers/drv_emac.h
 create mode 100644 bsp/lpc43xx/drivers/drv_led.c
 create mode 100644 bsp/lpc43xx/drivers/drv_led.h
 create mode 100644 bsp/lpc43xx/drivers/drv_uart.c
 create mode 100644 bsp/lpc43xx/drivers/drv_uart.h

diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..7a59b5923e
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..65304c127d
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("push")         \
+     _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT \
+     _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..ab31de0ee8
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..5cea74e9af
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm3.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..122c9aa4a8
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..d65016c714
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000..83db95b5f1
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000..0a18fafc30
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000..d213f0eed7
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_sc000.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..1a2a0f2e30
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_sc000.h
@@ -0,0 +1,813 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_sc300.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..cc34d6fc0e
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1598 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
new file mode 100644
index 0000000000..88872efab2
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
@@ -0,0 +1,34895 @@
+
+/****************************************************************************************************//**
+ * @file     LPC43xx.h
+ *
+ * @status   RELEASE
+ *
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
+ *           default LPC43xx Device Series
+ *
+ * @version  V5
+ * @date     9. December 2011
+ *
+ * @note     Generated with SVDConv V2.6 Build 6c  on Friday, 09.12.2011 13:56:08
+ *
+ *           from CMSIS SVD File 'LPC43xxv5.xml' Version 5,
+ *           created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+  * @{
+  */
+
+/** @addtogroup LPC43xx
+  * @{
+  */
+
+#ifndef __LPC43XX_H__
+#define __LPC43XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+
+
+/********************************************
+** Start of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma push
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// -------------------------  Cortex-M4 Processor Exceptions Numbers  -----------------------------
+  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
+  MemoryManagement_IRQn             = -12,  /*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+  BusFault_IRQn                     = -11,  /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn                   = -10,  /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  SVCall_IRQn                       =  -5,  /*!<  11  System Service Call via SVC instruction */
+  DebugMonitor_IRQn                 =  -4,  /*!<  12  Debug Monitor                    */
+  PendSV_IRQn                       =  -2,  /*!<  14  Pendable request for system service */
+  SysTick_IRQn                      =  -1,  /*!<  15  System Tick Timer                */
+// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
+  DAC_IRQn                          =   0,  /*!<   0  DAC                              */
+  M0CORE_IRQn                  		=   1,  /*!<   1  M0a                              */
+  DMA_IRQn                          =   2,  /*!<   2  DMA                              */
+  RESERVED1_IRQn                    =   3,  /*!<   3  EZH/EDM                          */
+  RESERVED2_IRQn                    =   4,
+  ETHERNET_IRQn                     =   5,  /*!<   5  ETHERNET                         */
+  SDIO_IRQn                         =   6,  /*!<   6  SDIO                             */
+  LCD_IRQn                          =   7,  /*!<   7  LCD                              */
+  USB0_IRQn                         =   8,  /*!<   8  USB0                             */
+  USB1_IRQn                         =   9,  /*!<   9  USB1                             */
+  SCT_IRQn                          =  10,  /*!<  10  SCT                              */
+  RITIMER_IRQn                      =  11,  /*!<  11  RITIMER                          */
+  TIMER0_IRQn                       =  12,  /*!<  12  TIMER0                           */
+  TIMER1_IRQn                       =  13,  /*!<  13  TIMER1                           */
+  TIMER2_IRQn                       =  14,  /*!<  14  TIMER2                           */
+  TIMER3_IRQn                       =  15,  /*!<  15  TIMER3                           */
+  MCPWM_IRQn                        =  16,  /*!<  16  MCPWM                            */
+  ADC0_IRQn                         =  17,  /*!<  17  ADC0                             */
+  I2C0_IRQn                         =  18,  /*!<  18  I2C0                             */
+  I2C1_IRQn                         =  19,  /*!<  19  I2C1                             */
+  SPI_INT_IRQn                      =  20,  /*!<  20  SPI_INT                          */
+  ADC1_IRQn                         =  21,  /*!<  21  ADC1                             */
+  SSP0_IRQn                         =  22,  /*!<  22  SSP0                             */
+  SSP1_IRQn                         =  23,  /*!<  23  SSP1                             */
+  USART0_IRQn                       =  24,  /*!<  24  USART0                           */
+  UART1_IRQn                        =  25,  /*!<  25  UART1                            */
+  USART2_IRQn                       =  26,  /*!<  26  USART2                           */
+  USART3_IRQn                       =  27,  /*!<  27  USART3                           */
+  I2S0_IRQn                         =  28,  /*!<  28  I2S0                             */
+  I2S1_IRQn                         =  29,  /*!<  29  I2S1                             */
+  RESERVED4_IRQn                    =  30,
+  SGPIO_IINT_IRQn                   =  31,  /*!<  31  SGPIO_IINT                       */
+  PIN_INT0_IRQn                     =  32,  /*!<  32  PIN_INT0                         */
+  PIN_INT1_IRQn                     =  33,  /*!<  33  PIN_INT1                         */
+  PIN_INT2_IRQn                     =  34,  /*!<  34  PIN_INT2                         */
+  PIN_INT3_IRQn                     =  35,  /*!<  35  PIN_INT3                         */
+  PIN_INT4_IRQn                     =  36,  /*!<  36  PIN_INT4                         */
+  PIN_INT5_IRQn                     =  37,  /*!<  37  PIN_INT5                         */
+  PIN_INT6_IRQn                     =  38,  /*!<  38  PIN_INT6                         */
+  PIN_INT7_IRQn                     =  39,  /*!<  39  PIN_INT7                         */
+  GINT0_IRQn                        =  40,  /*!<  40  GINT0                            */
+  GINT1_IRQn                        =  41,  /*!<  41  GINT1                            */
+  EVENTROUTER_IRQn                  =  42,  /*!<  42  EVENTROUTER                      */
+  C_CAN1_IRQn                       =  43,  /*!<  43  C_CAN1                           */
+  RESERVED6_IRQn                    =  44,
+  RESERVED7_IRQn                    =  45,  /*!<  45  VADC                             */
+  ATIMER_IRQn                       =  46,  /*!<  46  ATIMER                           */
+  RTC_IRQn                          =  47,  /*!<  47  RTC                              */
+  RESERVED8_IRQn                    =  48,
+  WWDT_IRQn                         =  49,  /*!<  49  WWDT                             */
+  RESERVED9_IRQn                    =  50,
+  C_CAN0_IRQn                       =  51,  /*!<  51  C_CAN0                           */
+  QEI_IRQn                          =  52,  /*!<  52  QEI                              */
+
+// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
+  M0_Reset_IRQn                     = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
+  M0_NonMaskableInt_IRQn            = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+  M0_HardFault_IRQn                 = -13,  /*!<   3  Hard Fault, all classes of Fault */
+  M0_SVCall_IRQn                    =  -5,  /*!<  11  System Service Call via SVC instruction */
+  M0_DebugMonitor_IRQn              =  -4,  /*!<  12  Debug Monitor                    */
+  M0_PendSV_IRQn                    =  -2,  /*!<  14  Pendable request for system service */
+  M0_SysTick_IRQn                   =  -1,  /*!<  15  System Tick Timer                */
+// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
+  M0_RTC_IRQn                       =   0,  /*!<   0  RTC                              */
+  M0_M4CORE_IRQn					=   1,  /*!<   1  M4                               */
+  M0_DMA_IRQn                       =   2,  /*!<   2  DMA                              */
+  M0_RESERVED0_IRQn					=   3,
+  M0_RESERVED1_IRQn					=   4,
+  M0_ETHERNET_IRQn                  =   5,  /*!<   5  ETHERNET                         */
+  M0_SDIO_IRQn                      =   6,  /*!<   6  SDIO                             */
+  M0_LCD_IRQn                       =   7,  /*!<   7  LCD                              */
+  M0_USB0_IRQn                      =   8,  /*!<   8  USB0                             */
+  M0_USB1_IRQn                      =   9,  /*!<   9  USB1                             */
+  M0_SCT_IRQn                       =  10,  /*!<  10  SCT                              */
+  M0_RITIMER_OR_WWDT_IRQn           =  11,  /*!<  11  RITIMER_OR_WWDT                  */
+  M0_TIMER0_IRQn                    =  12,  /*!<  12  TIMER0                           */
+  M0_GINT1_IRQn                     =  13,  /*!<  13  GINT1                            */
+  M0_TIMER3_IRQn                    =  15,  /*!<  15  TIMER3                           */
+  M0_RESERVED2_IRQn					=  14,
+  M0_RESERVED3_IRQn					=  15,
+  M0_MCPWM_IRQn                     =  16,  /*!<  16  MCPWM                            */
+  M0_ADC0_IRQn                      =  17,  /*!<  17  ADC0                             */
+  M0_I2C0_OR_I2C1_IRQn              =  18,  /*!<  18  I2C0_OR_I2C1                     */
+  M0_SGPIO_IRQn                     =  19,  /*!<  19  SGPIO                            */
+  M0_SPI_OR_DAC_IRQn                =  20,  /*!<  20  SPI_OR_DAC                       */
+  M0_ADC1_IRQn                      =  21,  /*!<  21  ADC1                             */
+  M0_SSP0_OR_SSP1_IRQn              =  22,  /*!<  22  SSP0_OR_SSP1                     */
+  M0_EVENTROUTER_IRQn               =  23,  /*!<  23  EVENTROUTER                      */
+  M0_USART0_IRQn                    =  24,  /*!<  24  USART0                           */
+  M0_UART1_IRQn                     =  25,  /*!<  25  UART1                            */
+  M0_USART2_OR_C_CAN1_IRQn          =  26,  /*!<  26  USART2_OR_C_CAN1                 */
+  M0_USART3_IRQn                    =  27,  /*!<  27  USART3                           */
+  M0_I2S0_OR_I2S1_OR_QEI_IRQn       =  28,  /*!<  28  I2S0_OR_I2S1_OR_QEI              */
+  M0_C_CAN0_IRQn                    =  29   /*!<  29  C_CAN0                           */
+} IRQn_Type;
+
+ /* Event Router Input (ERI) Number Definitions */
+typedef enum {
+  WAKEUP0_ERIn                      = 0,
+  WAKEUP1_ERIn                      = 1,
+  WAKEUP2_ERIn                      = 2,
+  WAKEUP3_ERIn                      = 3,
+  ATIMER_ERIn                       = 4,
+  RTC_ERIn                          = 5,
+  BOD1_ERIn                         = 6,  /* Bod trip 1 */
+  WWDT_ERIn                         = 7,
+  ETH_ERIn                          = 8,
+  USB0_ERIn                         = 9,
+  USB1_ERIn                         = 10,
+  SDIO_ERIn                         = 11,
+  CAN_ERIn                          = 12, /* CAN0/1 or'ed */
+  TIM2_ERIn                         = 13,
+  TIM6_ERIn                         = 14,
+  QEI_ERIn                          = 15,
+  TIM14_ERIn                        = 16,
+  RESERVED0_ERIn                    = 17, /* M0s */
+  RESERVED1_ERIn                    = 18, /* M3/M4 */
+  RESET_ERIn                        = 19
+}ERIn_Type;
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */
+
+#ifdef CORE_M4
+#define __CM4_REV              0x0000       /*!< Cortex-M4 Core Revision               */
+#define __MPU_PRESENT             1         /*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1         /*!< FPU present or not                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm4.h>                       /*!< Cortex-M4 processor and core peripherals */
+#else
+#ifdef CORE_M0
+#define __MPU_PRESENT             0         /*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0         /*!< FPU present or not                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm0.h>                       /*!< Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0 or CORE_M4
+#endif
+#endif
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+#include "system_LPC43xx.h"                 /*!< LPC43xx System                        */
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          SCT                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
+  */
+
+#define CONFIG_SCT_nEV   (16)            /* Number of events */
+#define CONFIG_SCT_nRG   (16)            /* Number of match/compare registers */
+#define CONFIG_SCT_nOU   (16)            /* Number of outputs */
+
+typedef struct
+{
+    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
+    union {
+        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
+        struct {
+            __IO uint16_t CTRL_L;       /* 0x004 low control register */
+            __IO uint16_t CTRL_H;       /* 0x006 high control register */
+        };
+    };
+    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
+    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
+    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
+    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
+    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
+    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
+    __IO uint16_t START_L;              /* 0x014 start register for counter L */
+    __IO uint16_t START_H;              /* 0x016 start register for counter H */
+         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
+    union {
+        __IO uint32_t COUNT_U;          /* 0x040 counter register */
+        struct {
+            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
+            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
+        };
+    };
+    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
+    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
+    __I  uint32_t INPUT;                /* 0x048 input register */
+    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
+    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
+    __IO uint32_t OUTPUT;               /* 0x050 output register */
+    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
+    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
+    __IO uint32_t DMA0REQUEST;          /* 0x05C DMA0 Request Register */
+    __IO uint32_t DMA1REQUEST;          /* 0x060 DMA1 Request Register */
+         uint32_t RESERVED2[35];        /* 0x064-0x0EC reserved */
+    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
+    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
+    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
+    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */
+
+    union {
+        __IO union {                    /* 0x100-... Match / Capture value */
+            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
+                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
+            };
+        } MATCH[CONFIG_SCT_nRG];
+        __I union {
+            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
+                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
+            };
+        } CAP[CONFIG_SCT_nRG];
+    };
+
+         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
+
+    union {
+        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
+        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
+    };
+         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
+    union {
+        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
+        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
+    };
+         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
+
+    union {
+        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
+            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
+                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
+            };
+        } MATCHREL[CONFIG_SCT_nRG];
+        __IO union {
+            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
+                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
+            };
+        } CAPCTRL[CONFIG_SCT_nRG];
+    };
+
+         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
+
+    union {
+        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
+        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
+    };
+         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
+    union {
+        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
+        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
+    };
+         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
+
+    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+        uint32_t STATE;                 /* Event State Register */
+        uint32_t CTRL;                  /* Event Control Register */
+    } EVENT[CONFIG_SCT_nEV];
+
+         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
+
+    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
+        uint32_t SET;                   /* Output n Set Register */
+        uint32_t CLR;                   /* Output n Clear Register */
+    } OUT[CONFIG_SCT_nOU];
+
+         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
+
+    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
+
+} LPC_SCT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         GPDMA                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (GPDMA)
+  */
+
+typedef struct {                            /*!< (@ 0x40002000) GPDMA Structure        */
+  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40002000) DMA Interrupt Status Register */
+  __I  uint32_t  INTTCSTAT;                 /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */
+  __O  uint32_t  INTTCCLEAR;                /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */
+  __I  uint32_t  INTERRSTAT;                /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */
+  __O  uint32_t  INTERRCLR;                 /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */
+  __I  uint32_t  RAWINTTCSTAT;              /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */
+  __I  uint32_t  RAWINTERRSTAT;             /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */
+  __I  uint32_t  ENBLDCHNS;                 /*!< (@ 0x4000201C) DMA Enabled Channel Register */
+  __IO uint32_t  SOFTBREQ;                  /*!< (@ 0x40002020) DMA Software Burst Request Register */
+  __IO uint32_t  SOFTSREQ;                  /*!< (@ 0x40002024) DMA Software Single Request Register */
+  __IO uint32_t  SOFTLBREQ;                 /*!< (@ 0x40002028) DMA Software Last Burst Request Register */
+  __IO uint32_t  SOFTLSREQ;                 /*!< (@ 0x4000202C) DMA Software Last Single Request Register */
+  __IO uint32_t  CONFIG;                    /*!< (@ 0x40002030) DMA Configuration Register */
+  __IO uint32_t  SYNC;                      /*!< (@ 0x40002034) DMA Synchronization Register */
+  __I  uint32_t  RESERVED0[50];
+  __IO uint32_t  C0SRCADDR;                 /*!< (@ 0x40002100) DMA Channel Source Address Register */
+  __IO uint32_t  C0DESTADDR;                /*!< (@ 0x40002104) DMA Channel Destination Address Register */
+  __IO uint32_t  C0LLI;                     /*!< (@ 0x40002108) DMA Channel Linked List Item Register */
+  __IO uint32_t  C0CONTROL;                 /*!< (@ 0x4000210C) DMA Channel Control Register */
+  __IO uint32_t  C0CONFIG;                  /*!< (@ 0x40002110) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED1[3];
+  __IO uint32_t  C1SRCADDR;                 /*!< (@ 0x40002120) DMA Channel Source Address Register */
+  __IO uint32_t  C1DESTADDR;                /*!< (@ 0x40002124) DMA Channel Destination Address Register */
+  __IO uint32_t  C1LLI;                     /*!< (@ 0x40002128) DMA Channel Linked List Item Register */
+  __IO uint32_t  C1CONTROL;                 /*!< (@ 0x4000212C) DMA Channel Control Register */
+  __IO uint32_t  C1CONFIG;                  /*!< (@ 0x40002130) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED2[3];
+  __IO uint32_t  C2SRCADDR;                 /*!< (@ 0x40002140) DMA Channel Source Address Register */
+  __IO uint32_t  C2DESTADDR;                /*!< (@ 0x40002144) DMA Channel Destination Address Register */
+  __IO uint32_t  C2LLI;                     /*!< (@ 0x40002148) DMA Channel Linked List Item Register */
+  __IO uint32_t  C2CONTROL;                 /*!< (@ 0x4000214C) DMA Channel Control Register */
+  __IO uint32_t  C2CONFIG;                  /*!< (@ 0x40002150) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  C3SRCADDR;                 /*!< (@ 0x40002160) DMA Channel Source Address Register */
+  __IO uint32_t  C3DESTADDR;                /*!< (@ 0x40002164) DMA Channel Destination Address Register */
+  __IO uint32_t  C3LLI;                     /*!< (@ 0x40002168) DMA Channel Linked List Item Register */
+  __IO uint32_t  C3CONTROL;                 /*!< (@ 0x4000216C) DMA Channel Control Register */
+  __IO uint32_t  C3CONFIG;                  /*!< (@ 0x40002170) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  C4SRCADDR;                 /*!< (@ 0x40002180) DMA Channel Source Address Register */
+  __IO uint32_t  C4DESTADDR;                /*!< (@ 0x40002184) DMA Channel Destination Address Register */
+  __IO uint32_t  C4LLI;                     /*!< (@ 0x40002188) DMA Channel Linked List Item Register */
+  __IO uint32_t  C4CONTROL;                 /*!< (@ 0x4000218C) DMA Channel Control Register */
+  __IO uint32_t  C4CONFIG;                  /*!< (@ 0x40002190) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  C5SRCADDR;                 /*!< (@ 0x400021A0) DMA Channel Source Address Register */
+  __IO uint32_t  C5DESTADDR;                /*!< (@ 0x400021A4) DMA Channel Destination Address Register */
+  __IO uint32_t  C5LLI;                     /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */
+  __IO uint32_t  C5CONTROL;                 /*!< (@ 0x400021AC) DMA Channel Control Register */
+  __IO uint32_t  C5CONFIG;                  /*!< (@ 0x400021B0) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  C6SRCADDR;                 /*!< (@ 0x400021C0) DMA Channel Source Address Register */
+  __IO uint32_t  C6DESTADDR;                /*!< (@ 0x400021C4) DMA Channel Destination Address Register */
+  __IO uint32_t  C6LLI;                     /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */
+  __IO uint32_t  C6CONTROL;                 /*!< (@ 0x400021CC) DMA Channel Control Register */
+  __IO uint32_t  C6CONFIG;                  /*!< (@ 0x400021D0) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  C7SRCADDR;                 /*!< (@ 0x400021E0) DMA Channel Source Address Register */
+  __IO uint32_t  C7DESTADDR;                /*!< (@ 0x400021E4) DMA Channel Destination Address Register */
+  __IO uint32_t  C7LLI;                     /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */
+  __IO uint32_t  C7CONTROL;                 /*!< (@ 0x400021EC) DMA Channel Control Register */
+  __IO uint32_t  C7CONFIG;                  /*!< (@ 0x400021F0) DMA Channel Configuration Register */
+} LPC_GPDMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SDMMC                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a  (SDMMC)
+  */
+
+typedef struct {                            /*!< (@ 0x40004000) SDMMC Structure        */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40004000) Control Register       */
+  __IO uint32_t  PWREN;                     /*!< (@ 0x40004004) Power Enable Register  */
+  __IO uint32_t  CLKDIV;                    /*!< (@ 0x40004008) Clock Divider Register */
+  __IO uint32_t  CLKSRC;                    /*!< (@ 0x4000400C) SD Clock Source Register */
+  __IO uint32_t  CLKENA;                    /*!< (@ 0x40004010) Clock Enable Register  */
+  __IO uint32_t  TMOUT;                     /*!< (@ 0x40004014) Timeout Register       */
+  __IO uint32_t  CTYPE;                     /*!< (@ 0x40004018) Card Type Register     */
+  __IO uint32_t  BLKSIZ;                    /*!< (@ 0x4000401C) Block Size Register    */
+  __IO uint32_t  BYTCNT;                    /*!< (@ 0x40004020) Byte Count Register    */
+  __IO uint32_t  INTMASK;                   /*!< (@ 0x40004024) Interrupt Mask Register */
+  __IO uint32_t  CMDARG;                    /*!< (@ 0x40004028) Command Argument Register */
+  __IO uint32_t  CMD;                       /*!< (@ 0x4000402C) Command Register       */
+  __I  uint32_t  RESP0;                     /*!< (@ 0x40004030) Response Register 0    */
+  __I  uint32_t  RESP1;                     /*!< (@ 0x40004034) Response Register 1    */
+  __I  uint32_t  RESP2;                     /*!< (@ 0x40004038) Response Register 2    */
+  __I  uint32_t  RESP3;                     /*!< (@ 0x4000403C) Response Register 3    */
+  __I  uint32_t  MINTSTS;                   /*!< (@ 0x40004040) Masked Interrupt Status Register */
+  __IO uint32_t  RINTSTS;                   /*!< (@ 0x40004044) Raw Interrupt Status Register */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40004048) Status Register        */
+  __IO uint32_t  FIFOTH;                    /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */
+  __I  uint32_t  CDETECT;                   /*!< (@ 0x40004050) Card Detect Register   */
+  __I  uint32_t  WRTPRT;                    /*!< (@ 0x40004054) Write Protect Register */
+  __IO uint32_t  GPIO;                      /*!< (@ 0x40004058) General Purpose Input/Output Register */
+  __I  uint32_t  TCBCNT;                    /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */
+  __I  uint32_t  TBBCNT;                    /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */
+  __IO uint32_t  DEBNCE;                    /*!< (@ 0x40004064) Debounce Count Register */
+  __IO uint32_t  USRID;                     /*!< (@ 0x40004068) User ID Register       */
+  __I  uint32_t  VERID;                     /*!< (@ 0x4000406C) Version ID Register    */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UHS_REG;                   /*!< (@ 0x40004074) UHS-1 Register         */
+  __IO uint32_t  RST_N;                     /*!< (@ 0x40004078) Hardware Reset         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  BMOD;                      /*!< (@ 0x40004080) Bus Mode Register      */
+  __O  uint32_t  PLDMND;                    /*!< (@ 0x40004084) Poll Demand Register   */
+  __IO uint32_t  DBADDR;                    /*!< (@ 0x40004088) Descriptor List Base Address Register */
+  __IO uint32_t  IDSTS;                     /*!< (@ 0x4000408C) Internal DMAC Status Register */
+  __IO uint32_t  IDINTEN;                   /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */
+  __I  uint32_t  DSCADDR;                   /*!< (@ 0x40004094) Current Host Descriptor Address Register */
+  __I  uint32_t  BUFADDR;                   /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */
+} LPC_SDMMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          EMC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7  (EMC)
+  */
+
+typedef struct {                            /*!< (@ 0x40005000) EMC Structure          */
+  __IO uint32_t  CONTROL;                   /*!< (@ 0x40005000) Controls operation of the memory controller. */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40005004) Provides EMC status information. */
+  __IO uint32_t  CONFIG;                    /*!< (@ 0x40005008) Configures operation of the memory controller. */
+  __I  uint32_t  RESERVED0[5];
+  __IO uint32_t  DYNAMICCONTROL;            /*!< (@ 0x40005020) Controls dynamic memory operation. */
+  __IO uint32_t  DYNAMICREFRESH;            /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */
+  __IO uint32_t  DYNAMICREADCONFIG;         /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  DYNAMICRP;                 /*!< (@ 0x40005030) Selects the precharge command period. */
+  __IO uint32_t  DYNAMICRAS;                /*!< (@ 0x40005034) Selects the active to precharge command period. */
+  __IO uint32_t  DYNAMICSREX;               /*!< (@ 0x40005038) Selects the self-refresh exit time. */
+  __IO uint32_t  DYNAMICAPR;                /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */
+  __IO uint32_t  DYNAMICDAL;                /*!< (@ 0x40005040) Selects the data-in to active command time. */
+  __IO uint32_t  DYNAMICWR;                 /*!< (@ 0x40005044) Selects the write recovery time. */
+  __IO uint32_t  DYNAMICRC;                 /*!< (@ 0x40005048) Selects the active to active command period. */
+  __IO uint32_t  DYNAMICRFC;                /*!< (@ 0x4000504C) Selects the auto-refresh period. */
+  __IO uint32_t  DYNAMICXSR;                /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */
+  __IO uint32_t  DYNAMICRRD;                /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */
+  __IO uint32_t  DYNAMICMRD;                /*!< (@ 0x40005058) Selects the load mode register to active command time. */
+  __I  uint32_t  RESERVED2[9];
+  __IO uint32_t  STATICEXTENDEDWAIT;        /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */
+  __I  uint32_t  RESERVED3[31];
+  __IO uint32_t  DYNAMICCONFIG0;            /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS0;            /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED4[6];
+  __IO uint32_t  DYNAMICCONFIG1;            /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS1;            /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED5[6];
+  __IO uint32_t  DYNAMICCONFIG2;            /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS2;            /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED6[6];
+  __IO uint32_t  DYNAMICCONFIG3;            /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS3;            /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED7[38];
+  __IO uint32_t  STATICCONFIG0;             /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN0;            /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN0;            /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD0;             /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG0;            /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR0;             /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN0;           /*!< (@ 0x40005218) Selects bus turnaround cycles */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  STATICCONFIG1;             /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN1;            /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN1;            /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD1;             /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG1;            /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR1;             /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN1;           /*!< (@ 0x40005238) Selects bus turnaround cycles */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  STATICCONFIG2;             /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN2;            /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN2;            /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD2;             /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG2;            /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR2;             /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN2;           /*!< (@ 0x40005258) Selects bus turnaround cycles */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  STATICCONFIG3;             /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN3;            /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN3;            /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD3;             /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG3;            /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR3;             /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN3;           /*!< (@ 0x40005278) Selects bus turnaround cycles */
+} LPC_EMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         USB0                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB0)
+  */
+
+typedef struct {                            /*!< (@ 0x40006000) USB0 Structure         */
+  __I  uint32_t  RESERVED0[64];
+  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40006100) Capability register length */
+  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40006104) Host controller structural parameters */
+  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40006108) Host controller capability parameters */
+  __I  uint32_t  RESERVED1[5];
+  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40006120) Device interface version number */
+  __I  uint32_t  RESERVED2[7];
+  
+  union {
+    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40006140) USB command (host mode) */
+    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40006140) USB command (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40006144) USB status (host mode) */
+    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40006144) USB status (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40006148) USB interrupt enable (host mode) */
+    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40006148) USB interrupt enable (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000614C) USB frame index (host mode) */
+    __IO uint32_t  FRINDEX_D;               /*!< (@ 0x4000614C) USB frame index (device mode) */
+  } ;
+  __I  uint32_t  RESERVED3;
+  
+  union {
+    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40006154) Frame list base address (host mode) */
+    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40006154) USB device address (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40006158) Address of endpoint list in memory */
+    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40006158) Address of endpoint list in memory */
+  } ;
+  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */
+  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40006160) Programmable burst size */
+  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40006174) Length of virtual frame */
+  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40006178) Endpoint NAK (device mode) */
+  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */
+  __I  uint32_t  RESERVED5;
+  
+  union {
+    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40006184) Port 1 status/control (host mode) */
+    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40006184) Port 1 status/control (device mode) */
+  } ;
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  OTGSC;                     /*!< (@ 0x400061A4) OTG status and control */
+  
+  union {
+    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400061A8) USB mode (host mode)   */
+    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400061A8) USB device mode (device mode) */
+  } ;
+  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400061AC) Endpoint setup status  */
+  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400061B0) Endpoint initialization */
+  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400061B4) Endpoint de-initialization */
+  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400061B8) Endpoint status        */
+  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400061BC) Endpoint complete      */
+  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400061C0) Endpoint control 0     */
+  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400061C4) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400061C8) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400061CC) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL4;                /*!< (@ 0x400061D0) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL5;                /*!< (@ 0x400061D4) Endpoint control       */
+} LPC_USB0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         USB1                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB1)
+  */
+
+typedef struct {                            /*!< (@ 0x40007000) USB1 Structure         */
+  __I  uint32_t  RESERVED0[64];
+  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40007100) Capability register length */
+  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40007104) Host controller structural parameters */
+  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40007108) Host controller capability parameters */
+  __I  uint32_t  RESERVED1[5];
+  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40007120) Device interface version number */
+  __I  uint32_t  RESERVED2[7];
+  
+  union {
+    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40007140) USB command (host mode) */
+    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40007140) USB command (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40007144) USB status (host mode) */
+    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40007144) USB status (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40007148) USB interrupt enable (host mode) */
+    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40007148) USB interrupt enable (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000714C) USB frame index (host mode) */
+    __I  uint32_t  FRINDEX_D;               /*!< (@ 0x4000714C) USB frame index (device mode) */
+  } ;
+  __I  uint32_t  RESERVED3;
+  
+  union {
+    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40007154) Frame list base address */
+    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40007154) USB device address     */
+  } ;
+  
+  union {
+    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */
+    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */
+  } ;
+  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */
+  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40007160) Programmable burst size */
+  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  ULPIVIEWPORT;              /*!< (@ 0x40007170) ULPI viewport          */
+  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40007174) Length of virtual frame */
+  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40007178) Endpoint NAK (device mode) */
+  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */
+  __I  uint32_t  RESERVED5;
+  
+  union {
+    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40007184) Port 1 status/control (host mode) */
+    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40007184) Port 1 status/control (device mode) */
+  } ;
+  __I  uint32_t  RESERVED6[8];
+  
+  union {
+    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400071A8) USB mode (host mode)   */
+    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400071A8) USB mode (device mode) */
+  } ;
+  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400071AC) Endpoint setup status  */
+  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400071B0) Endpoint initialization */
+  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400071B4) Endpoint de-initialization */
+  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400071B8) Endpoint status        */
+  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400071BC) Endpoint complete      */
+  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400071C0) Endpoint control 0     */
+  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400071C4) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400071C8) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400071CC) Endpoint control       */
+} LPC_USB1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          LCD                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7  (LCD)
+  */
+
+typedef struct {                            /*!< (@ 0x40008000) LCD Structure          */
+  __IO uint32_t  TIMH;                      /*!< (@ 0x40008000) Horizontal Timing Control register */
+  __IO uint32_t  TIMV;                      /*!< (@ 0x40008004) Vertical Timing Control register */
+  __IO uint32_t  POL;                       /*!< (@ 0x40008008) Clock and Signal Polarity Control register */
+  __IO uint32_t  LE;                        /*!< (@ 0x4000800C) Line End Control register */
+  __IO uint32_t  UPBASE;                    /*!< (@ 0x40008010) Upper Panel Frame Base Address register */
+  __IO uint32_t  LPBASE;                    /*!< (@ 0x40008014) Lower Panel Frame Base Address register */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40008018) LCD Control register   */
+  __IO uint32_t  INTMSK;                    /*!< (@ 0x4000801C) Interrupt Mask register */
+  __I  uint32_t  INTRAW;                    /*!< (@ 0x40008020) Raw Interrupt Status register */
+  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40008024) Masked Interrupt Status register */
+  __O  uint32_t  INTCLR;                    /*!< (@ 0x40008028) Interrupt Clear register */
+  __I  uint32_t  UPCURR;                    /*!< (@ 0x4000802C) Upper Panel Current Address Value register */
+  __I  uint32_t  LPCURR;                    /*!< (@ 0x40008030) Lower Panel Current Address Value register */
+  __I  uint32_t  RESERVED0[115];
+  __IO uint32_t PAL[256];					/*!< (@ 0x40008200) 256x16-bit Color Palette registers */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t CRSR_IMG[256];              /*!< (@ 0x40008800) Cursor Image registers */
+  __IO uint32_t  CRSR_CTRL;                 /*!< (@ 0x40008C00) Cursor Control register */
+  __IO uint32_t  CRSR_CFG;                  /*!< (@ 0x40008C04) Cursor Configuration register */
+  __IO uint32_t  CRSR_PAL0;                 /*!< (@ 0x40008C08) Cursor Palette register 0 */
+  __IO uint32_t  CRSR_PAL1;                 /*!< (@ 0x40008C0C) Cursor Palette register 1 */
+  __IO uint32_t  CRSR_XY;                   /*!< (@ 0x40008C10) Cursor XY Position register */
+  __IO uint32_t  CRSR_CLIP;                 /*!< (@ 0x40008C14) Cursor Clip Position register */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  CRSR_INTMSK;               /*!< (@ 0x40008C20) Cursor Interrupt Mask register */
+  __O  uint32_t  CRSR_INTCLR;               /*!< (@ 0x40008C24) Cursor Interrupt Clear register */
+  __I  uint32_t  CRSR_INTRAW;               /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */
+  __I  uint32_t  CRSR_INTSTAT;              /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */
+} LPC_LCD_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       ETHERNET                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available  (ETHERNET)
+  */
+
+typedef struct {                            /*!< (@ 0x40010000) ETHERNET Structure     */
+  __IO uint32_t  MAC_CONFIG;                /*!< (@ 0x40010000) MAC configuration register */
+  __IO uint32_t  MAC_FRAME_FILTER;          /*!< (@ 0x40010004) MAC frame filter       */
+  __IO uint32_t  MAC_HASHTABLE_HIGH;        /*!< (@ 0x40010008) Hash table high register */
+  __IO uint32_t  MAC_HASHTABLE_LOW;         /*!< (@ 0x4001000C) Hash table low register */
+  __IO uint32_t  MAC_MII_ADDR;              /*!< (@ 0x40010010) MII address register   */
+  __IO uint32_t  MAC_MII_DATA;              /*!< (@ 0x40010014) MII data register      */
+  __IO uint32_t  MAC_FLOW_CTRL;             /*!< (@ 0x40010018) Flow control register  */
+  __IO uint32_t  MAC_VLAN_TAG;              /*!< (@ 0x4001001C) VLAN tag register      */
+  __I  uint32_t  RESERVED0;
+  __I  uint32_t  MAC_DEBUG;                 /*!< (@ 0x40010024) Debug register         */
+  __IO uint32_t  MAC_RWAKE_FRFLT;           /*!< (@ 0x40010028) Remote wake-up frame filter */
+  __IO uint32_t  MAC_PMT_CTRL_STAT;         /*!< (@ 0x4001002C) PMT control and status */
+  __I  uint32_t  RESERVED1[2];
+  __I  uint32_t  MAC_INTR;                  /*!< (@ 0x40010038) Interrupt status register */
+  __IO uint32_t  MAC_INTR_MASK;             /*!< (@ 0x4001003C) Interrupt mask register */
+  __IO uint32_t  MAC_ADDR0_HIGH;            /*!< (@ 0x40010040) MAC address 0 high register */
+  __IO uint32_t  MAC_ADDR0_LOW;             /*!< (@ 0x40010044) MAC address 0 low register */
+  __I  uint32_t  RESERVED2[430];
+  __IO uint32_t  MAC_TIMESTP_CTRL;          /*!< (@ 0x40010700) Time stamp control register */
+  __IO uint32_t  SUBSECOND_INCR;            /*!< (@ 0x40010704) Sub-second increment register */
+  __I  uint32_t  SECONDS;                   /*!< (@ 0x40010708) System time seconds register */
+  __I  uint32_t  NANOSECONDS;               /*!< (@ 0x4001070C) System time nanoseconds register */
+  __IO uint32_t  SECONDSUPDATE;             /*!< (@ 0x40010710) System time seconds update register */
+  __IO uint32_t  NANOSECONDSUPDATE;         /*!< (@ 0x40010714) System time nanoseconds update register */
+  __IO uint32_t  ADDEND;                    /*!< (@ 0x40010718) Time stamp addend register */
+  __IO uint32_t  TARGETSECONDS;             /*!< (@ 0x4001071C) Target time seconds register */
+  __IO uint32_t  TARGETNANOSECONDS;         /*!< (@ 0x40010720) Target time nanoseconds register */
+  __IO uint32_t  HIGHWORD;                  /*!< (@ 0x40010724) System time higher word seconds register */
+  __I  uint32_t  TIMESTAMPSTAT;             /*!< (@ 0x40010728) Time stamp status register */
+  __IO uint32_t  PPSCTRL;                   /*!< (@ 0x4001072C) PPS control register   */
+  __I  uint32_t  AUXNANOSECONDS;            /*!< (@ 0x40010730) Auxiliary time stamp nanoseconds register */
+  __I  uint32_t  AUXSECONDS;                /*!< (@ 0x40010734) Auxiliary time stamp seconds register */
+  __I  uint32_t  RESERVED3[562];
+  __IO uint32_t  DMA_BUS_MODE;              /*!< (@ 0x40011000) Bus Mode Register      */
+  __IO uint32_t  DMA_TRANS_POLL_DEMAND;     /*!< (@ 0x40011004) Transmit poll demand register */
+  __IO uint32_t  DMA_REC_POLL_DEMAND;       /*!< (@ 0x40011008) Receive poll demand register */
+  __IO uint32_t  DMA_REC_DES_ADDR;          /*!< (@ 0x4001100C) Receive descriptor list address register */
+  __IO uint32_t  DMA_TRANS_DES_ADDR;        /*!< (@ 0x40011010) Transmit descriptor list address register */
+  __IO uint32_t  DMA_STAT;                  /*!< (@ 0x40011014) Status register        */
+  __IO uint32_t  DMA_OP_MODE;               /*!< (@ 0x40011018) Operation mode register */
+  __IO uint32_t  DMA_INT_EN;                /*!< (@ 0x4001101C) Interrupt enable register */
+  __I  uint32_t  DMA_MFRM_BUFOF;            /*!< (@ 0x40011020) Missed frame and buffer overflow register */
+  __IO uint32_t  DMA_REC_INT_WDT;           /*!< (@ 0x40011024) Receive interrupt watchdog timer register */
+  __I  uint32_t  RESERVED4[8];
+  __I  uint32_t  DMA_CURHOST_TRANS_DES;     /*!< (@ 0x40011048) Current host transmit descriptor register */
+  __I  uint32_t  DMA_CURHOST_REC_DES;       /*!< (@ 0x4001104C) Current host receive descriptor register */
+  __I  uint32_t  DMA_CURHOST_TRANS_BUF;     /*!< (@ 0x40011050) Current host transmit buffer address register */
+  __I  uint32_t  DMA_CURHOST_REC_BUF;       /*!< (@ 0x40011054) Current host receive buffer address register */
+} LPC_ETHERNET_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        ATIMER                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6  (ATIMER)
+  */
+
+typedef struct {                            /*!< (@ 0x40040000) ATIMER Structure       */
+  __IO uint32_t  DOWNCOUNTER;               /*!< (@ 0x40040000) Downcounter register   */
+  __IO uint32_t  PRESET;                    /*!< (@ 0x40040004) Preset value register  */
+  __I  uint32_t  RESERVED0[1012];
+  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40040FD8) Interrupt clear enable register */
+  __O  uint32_t  SET_EN;                    /*!< (@ 0x40040FDC) Interrupt set enable register */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40040FE0) Status register        */
+  __I  uint32_t  ENABLE;                    /*!< (@ 0x40040FE4) Enable register        */
+  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40040FE8) Clear register         */
+  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40040FEC) Set register           */
+} LPC_ATIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        REGFILE                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7  (REGFILE)
+  */
+
+typedef struct {                            /*!< (@ 0x40041000) REGFILE Structure      */
+  __IO uint32_t REGFILE[64];                /*!< (@ 0x40041000) General purpose storage register */
+} LPC_REGFILE_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          PMC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (PMC)
+  */
+
+typedef struct {                            /*!< (@ 0x40042000) PMC Structure          */
+  __IO uint32_t  PD0_SLEEP0_HW_ENA;         /*!< (@ 0x40042000) Hardware sleep event enable register */
+  __I  uint32_t  RESERVED0[6];
+  __IO uint32_t  PD0_SLEEP0_MODE;           /*!< (@ 0x4004201C) Sleep power mode register */
+} LPC_PMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         CREG                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3  (CREG)
+  */
+
+typedef struct {                            /*!< (@ 0x40043000) CREG Structure         */
+  __I  uint32_t  IRCTRM;                    /*!< (@ 0x40043000) IRC trim register      */
+  __IO uint32_t  CREG0;                     /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */
+  __I  uint32_t  RESERVED1[62];
+  __IO uint32_t  M4MEMMAP;                  /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */
+  __I  uint32_t  RESERVED2[5];
+  __IO uint32_t  CREG5;                     /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */
+  __IO uint32_t  DMAMUX;                    /*!< (@ 0x4004311C) DMA muxing control     */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  ETBCFG;                    /*!< (@ 0x40043128) ETB RAM configuration  */
+  __IO uint32_t  CREG6;                     /*!< (@ 0x4004312C) Chip configuration register 6. */
+  __IO uint32_t  M4TXEVENT;                 /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */
+  __I  uint32_t  RESERVED4[51];
+  __I  uint32_t  CHIPID;                    /*!< (@ 0x40043200) Part ID                */
+  __I  uint32_t  RESERVED5[127];
+  __IO uint32_t  M0TXEVENT;                 /*!< (@ 0x40043400) Cortex-M0 TXEV event clear */
+  __IO uint32_t  M0APPMEMMAP;               /*!< (@ 0x40043404) ARM Cortex-M0 memory mapping */
+} LPC_CREG_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                      EVENTROUTER                                     -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3  (EVENTROUTER)
+  */
+
+typedef struct {                            /*!< (@ 0x40044000) EVENTROUTER Structure  */
+  __IO uint32_t  HILO;                      /*!< (@ 0x40044000) Level configuration register */
+  __IO uint32_t  EDGE;                      /*!< (@ 0x40044004) Edge configuration     */
+  __I  uint32_t  RESERVED0[1012];
+  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40044FD8) Clear event enable register */
+  __O  uint32_t  SET_EN;                    /*!< (@ 0x40044FDC) Set event enable register */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40044FE0) Event Status register  */
+  __I  uint32_t  ENABLE;                    /*!< (@ 0x40044FE4) Event Enable register  */
+  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40044FE8) Clear event status register */
+  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40044FEC) Set event status register */
+} LPC_EVENTROUTER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          RTC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (RTC)
+  */
+
+typedef struct {                            /*!< (@ 0x40046000) RTC Structure          */
+  __O  uint32_t  ILR;                       /*!< (@ 0x40046000) Interrupt Location Register */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  CCR;                       /*!< (@ 0x40046008) Clock Control Register */
+  __IO uint32_t  CIIR;                      /*!< (@ 0x4004600C) Counter Increment Interrupt Register */
+  __IO uint32_t  AMR;                       /*!< (@ 0x40046010) Alarm Mask Register    */
+  __I  uint32_t  CTIME0;                    /*!< (@ 0x40046014) Consolidated Time Register 0 */
+  __I  uint32_t  CTIME1;                    /*!< (@ 0x40046018) Consolidated Time Register 1 */
+  __I  uint32_t  CTIME2;                    /*!< (@ 0x4004601C) Consolidated Time Register 2 */
+  __IO uint32_t  SEC;                       /*!< (@ 0x40046020) Seconds Register       */
+  __IO uint32_t  MIN;                       /*!< (@ 0x40046024) Minutes Register       */
+  __IO uint32_t  HRS;                       /*!< (@ 0x40046028) Hours Register         */
+  __IO uint32_t  DOM;                       /*!< (@ 0x4004602C) Day of Month Register  */
+  __IO uint32_t  DOW;                       /*!< (@ 0x40046030) Day of Week Register   */
+  __IO uint32_t  DOY;                       /*!< (@ 0x40046034) Day of Year Register   */
+  __IO uint32_t  MONTH;                     /*!< (@ 0x40046038) Months Register        */
+  __IO uint32_t  YEAR;                      /*!< (@ 0x4004603C) Years Register         */
+  __IO uint32_t  CALIBRATION;               /*!< (@ 0x40046040) Calibration Value Register */
+  __I  uint32_t  RESERVED1[7];
+  __IO uint32_t  ASEC;                      /*!< (@ 0x40046060) Alarm value for Seconds */
+  __IO uint32_t  AMIN;                      /*!< (@ 0x40046064) Alarm value for Minutes */
+  __IO uint32_t  AHRS;                      /*!< (@ 0x40046068) Alarm value for Hours  */
+  __IO uint32_t  ADOM;                      /*!< (@ 0x4004606C) Alarm value for Day of Month */
+  __IO uint32_t  ADOW;                      /*!< (@ 0x40046070) Alarm value for Day of Week */
+  __IO uint32_t  ADOY;                      /*!< (@ 0x40046074) Alarm value for Day of Year */
+  __IO uint32_t  AMON;                      /*!< (@ 0x40046078) Alarm value for Months */
+  __IO uint32_t  AYRS;                      /*!< (@ 0x4004607C) Alarm value for Year   */
+} LPC_RTC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          CGU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1  (CGU)
+  */
+
+typedef struct {                            /*!< (@ 0x40050000) CGU Structure          */
+  __I  uint32_t  RESERVED0[5];
+  __IO uint32_t  FREQ_MON;                  /*!< (@ 0x40050014) Frequency monitor register */
+  __IO uint32_t  XTAL_OSC_CTRL;             /*!< (@ 0x40050018) Crystal oscillator control register */
+  __I  uint32_t  PLL0USB_STAT;              /*!< (@ 0x4005001C) PLL0 (USB) status register */
+  __IO uint32_t  PLL0USB_CTRL;              /*!< (@ 0x40050020) PLL0 (USB) control register */
+  __IO uint32_t  PLL0USB_MDIV;              /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+  __IO uint32_t  PLL0USB_NP_DIV;            /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+  __I  uint32_t  PLL0AUDIO_STAT;            /*!< (@ 0x4005002C) PLL0 (audio) status register */
+  __IO uint32_t  PLL0AUDIO_CTRL;            /*!< (@ 0x40050030) PLL0 (audio) control register */
+  __IO uint32_t  PLL0AUDIO_MDIV;            /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+  __IO uint32_t  PLL0AUDIO_NP_DIV;          /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+  __IO uint32_t  PLL0AUDIO_FRAC;            /*!< (@ 0x4005003C) PLL0 (audio)           */
+  __I  uint32_t  PLL1_STAT;                 /*!< (@ 0x40050040) PLL1 status register   */
+  __IO uint32_t  PLL1_CTRL;                 /*!< (@ 0x40050044) PLL1 control register  */
+  __IO uint32_t  IDIVA_CTRL;                /*!< (@ 0x40050048) Integer divider A control register */
+  __IO uint32_t  IDIVB_CTRL;                /*!< (@ 0x4005004C) Integer divider B control register */
+  __IO uint32_t  IDIVC_CTRL;                /*!< (@ 0x40050050) Integer divider C control register */
+  __IO uint32_t  IDIVD_CTRL;                /*!< (@ 0x40050054) Integer divider D control register */
+  __IO uint32_t  IDIVE_CTRL;                /*!< (@ 0x40050058) Integer divider E control register */
+  __IO uint32_t  BASE_SAFE_CLK;             /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */
+  __IO uint32_t  BASE_USB0_CLK;             /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */
+  __IO uint32_t  BASE_PERIPH_CLK;           /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */
+  __IO uint32_t  BASE_USB1_CLK;             /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */
+  __IO uint32_t  BASE_M4_CLK;               /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */
+  __IO uint32_t  BASE_SPIFI_CLK;            /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */
+  __IO uint32_t  BASE_SPI_CLK;              /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */
+  __IO uint32_t  BASE_PHY_RX_CLK;           /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */
+  __IO uint32_t  BASE_PHY_TX_CLK;           /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */
+  __IO uint32_t  BASE_APB1_CLK;             /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */
+  __IO uint32_t  BASE_APB3_CLK;             /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */
+  __IO uint32_t  BASE_LCD_CLK;              /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  BASE_SDIO_CLK;             /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */
+  __IO uint32_t  BASE_SSP0_CLK;             /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */
+  __IO uint32_t  BASE_SSP1_CLK;             /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */
+  __IO uint32_t  BASE_UART0_CLK;            /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */
+  __IO uint32_t  BASE_UART1_CLK;            /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */
+  __IO uint32_t  BASE_UART2_CLK;            /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */
+  __IO uint32_t  BASE_UART3_CLK;            /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */
+  __IO uint32_t  BASE_OUT_CLK;              /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */
+  __I  uint32_t  RESERVED3[4];
+  __IO uint32_t  BASE_APLL_CLK;             /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */
+  __IO uint32_t  BASE_CGU_OUT0_CLK;         /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */
+  __IO uint32_t  BASE_CGU_OUT1_CLK;         /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */
+} LPC_CGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         CCU1                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1)
+  */
+
+typedef struct {                            /*!< (@ 0x40051000) CCU1 Structure         */
+  __IO uint32_t  PM;                        /*!< (@ 0x40051000) CCU1 power mode register */
+  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40051004) CCU1 base clocks status register */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  CLK_APB3_BUS_CFG;          /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */
+  __I  uint32_t  CLK_APB3_BUS_STAT;         /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */
+  __IO uint32_t  CLK_APB3_I2C1_CFG;         /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */
+  __I  uint32_t  CLK_APB3_I2C1_STAT;        /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */
+  __IO uint32_t  CLK_APB3_DAC_CFG;          /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */
+  __I  uint32_t  CLK_APB3_DAC_STAT;         /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */
+  __IO uint32_t  CLK_APB3_ADC0_CFG;         /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */
+  __I  uint32_t  CLK_APB3_ADC0_STAT;        /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */
+  __IO uint32_t  CLK_APB3_ADC1_CFG;         /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */
+  __I  uint32_t  CLK_APB3_ADC1_STAT;        /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */
+  __IO uint32_t  CLK_APB3_CAN0_CFG;         /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */
+  __I  uint32_t  CLK_APB3_CAN0_STAT;        /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  CLK_APB1_BUS_CFG;          /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */
+  __I  uint32_t  CLK_APB1_BUS_STAT;         /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */
+  __IO uint32_t  CLK_APB1_MOTOCONPWM_CFG;   /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */
+  __I  uint32_t  CLK_APB1_MOTOCONPWM_STAT;  /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */
+  __IO uint32_t  CLK_ABP1_I2C0_CFG;         /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */
+  __I  uint32_t  CLK_APB1_I2C0_STAT;        /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */
+  __IO uint32_t  CLK_APB1_I2S_CFG;          /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */
+  __I  uint32_t  CLK_APB1_I2S_STAT;         /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */
+  __IO uint32_t  CLK_APB1_CAN1_CFG;         /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */
+  __I  uint32_t  CLK_APB1_CAN1_STAT;        /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */
+  __I  uint32_t  RESERVED2[54];
+  __IO uint32_t  CLK_SPIFI_CFG;             /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */
+  __I  uint32_t  CLK_SPIFI_STAT;            /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */
+  __I  uint32_t  RESERVED3[62];
+  __IO uint32_t  CLK_M4_BUS_CFG;            /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */
+  __I  uint32_t  CLK_M4_BUS_STAT;           /*!< (@ 0x40051404) CLK_M4_BUSclock status register */
+  __IO uint32_t  CLK_M4_SPIFI_CFG;          /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */
+  __I  uint32_t  CLK_M4_SPIFI_STAT;         /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */
+  __IO uint32_t  CLK_M4_GPIO_CFG;           /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */
+  __I  uint32_t  CLK_M4_GPIO_STAT;          /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */
+  __IO uint32_t  CLK_M4_LCD_CFG;            /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */
+  __I  uint32_t  CLK_M4_LCD_STAT;           /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */
+  __IO uint32_t  CLK_M4_ETHERNET_CFG;       /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */
+  __I  uint32_t  CLK_M4_ETHERNET_STAT;      /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */
+  __IO uint32_t  CLK_M4_USB0_CFG;           /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */
+  __I  uint32_t  CLK_M4_USB0_STAT;          /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */
+  __IO uint32_t  CLK_M4_EMC_CFG;            /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */
+  __I  uint32_t  CLK_M4_EMC_STAT;           /*!< (@ 0x40051434) CLK_M4_EMC clock status register */
+  __IO uint32_t  CLK_M4_SDIO_CFG;           /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */
+  __I  uint32_t  CLK_M4_SDIO_STAT;          /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */
+  __IO uint32_t  CLK_M4_DMA_CFG;            /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */
+  __I  uint32_t  CLK_M4_DMA_STAT;           /*!< (@ 0x40051444) CLK_M4_DMA clock status register */
+  __IO uint32_t  CLK_M4_M4CORE_CFG;         /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */
+  __I  uint32_t  CLK_M4_M3CORE_STAT;        /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */
+  __I  uint32_t  RESERVED4[6];
+  __IO uint32_t  CLK_M4_SCT_CFG;            /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */
+  __I  uint32_t  CLK_M4_SCT_STAT;           /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */
+  __IO uint32_t  CLK_M4_USB1_CFG;           /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */
+  __I  uint32_t  CLK_M4_USB1_STAT;          /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */
+  __IO uint32_t  CLK_M4_EMCDIV_CFG;         /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */
+  __I  uint32_t  CLK_M4_EMCDIV_STAT;        /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  CLK_M4_M0APP_CFG;          /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */
+  __I  uint32_t  CLK_M4_M0APP_STAT;         /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */
+  __I  uint32_t  RESERVED6[26];
+  __IO uint32_t  CLK_M4_WWDT_CFG;           /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */
+  __I  uint32_t  CLK_M4_WWDT_STAT;          /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */
+  __IO uint32_t  CLK_M4_USART0_CFG;         /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */
+  __I  uint32_t  CLK_M4_USART0_STAT;        /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */
+  __IO uint32_t  CLK_M4_UART1_CFG;          /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */
+  __I  uint32_t  CLK_M4_UART1_STAT;         /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */
+  __IO uint32_t  CLK_M4_SSP0_CFG;           /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */
+  __I  uint32_t  CLK_M4_SSP0_STAT;          /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */
+  __IO uint32_t  CLK_M4_TIMER0_CFG;         /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER0_STAT;        /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */
+  __IO uint32_t  CLK_M4_TIMER1_CFG;         /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER1_STAT;        /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */
+  __IO uint32_t  CLK_M4_SCU_CFG;            /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */
+  __I  uint32_t  CLK_M4_SCU_STAT;           /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */
+  __IO uint32_t  CLK_M4_CREG_CFG;           /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */
+  __I  uint32_t  CLK_M4_CREG_STAT;          /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */
+  __I  uint32_t  RESERVED7[48];
+  __IO uint32_t  CLK_M4_RITIMER_CFG;        /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */
+  __I  uint32_t  CLK_M4_RITIMER_STAT;       /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */
+  __IO uint32_t  CLK_M4_USART2_CFG;         /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */
+  __I  uint32_t  CLK_M4_USART2_STAT;        /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */
+  __IO uint32_t  CLK_M4_USART3_CFG;         /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */
+  __I  uint32_t  CLK_M4_USART3_STAT;        /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */
+  __IO uint32_t  CLK_M4_TIMER2_CFG;         /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER2_STAT;        /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */
+  __IO uint32_t  CLK_M4_TIMER3_CFG;         /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER3_STAT;        /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */
+  __IO uint32_t  CLK_M4_SSP1_CFG;           /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */
+  __I  uint32_t  CLK_M4_SSP1_STAT;          /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */
+  __IO uint32_t  CLK_M4_QEI_CFG;            /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */
+  __I  uint32_t  CLK_M4_QEI_STAT;           /*!< (@ 0x40051634) CLK_M4_QEI clock status register */
+  __I  uint32_t  RESERVED8[50];
+  __IO uint32_t  CLK_PERIPH_BUS_CFG;        /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */
+  __I  uint32_t  CLK_PERIPH_BUS_STAT;       /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  CLK_PERIPH_CORE_CFG;       /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */
+  __I  uint32_t  CLK_PERIPH_CORE_STAT;      /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */
+  __IO uint32_t  CLK_PERIPH_SGPIO_CFG;      /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */
+  __I  uint32_t  CLK_PERIPH_SGPIO_STAT;     /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */
+  __I  uint32_t  RESERVED10[56];
+  __IO uint32_t  CLK_USB0_CFG;              /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */
+  __I  uint32_t  CLK_USB0_STAT;             /*!< (@ 0x40051804) CLK_USB0 clock status register */
+  __I  uint32_t  RESERVED11[62];
+  __IO uint32_t  CLK_USB1_CFG;              /*!< (@ 0x40051900) CLK_USB1 clock configuration register */
+  __I  uint32_t  CLK_USB1_STAT;             /*!< (@ 0x40051904) CLK_USB1 clock status register */
+  __I  uint32_t  RESERVED12[62];
+  __IO uint32_t  CLK_SPI_CFG;               /*!< (@ 0x40051A00) CLK_SPI clock configuration register */
+  __I  uint32_t  CLK_SPI_STAT;              /*!< (@ 0x40051A04) CLK_SPI clock status register */
+  __I  uint32_t  RESERVED13[62];
+  __IO uint32_t  CLK_VADC_CFG;              /*!< (@ 0x40051B00) CLK_VADC clock configuration register */
+  __I  uint32_t  CLK_VADC_STAT;             /*!< (@ 0x40051B04) CLK_VADC clock status register */
+} LPC_CCU1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         CCU2                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7  (CCU2)
+  */
+
+typedef struct {                            /*!< (@ 0x40052000) CCU2 Structure         */
+  __IO uint32_t  PM;                        /*!< (@ 0x40052000) Power mode register    */
+  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40052004) CCU base clocks status register */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  CLK_APLL_CFG;              /*!< (@ 0x40052100) CLK_APLL clock configuration register */
+  __I  uint32_t  CLK_APLL_STAT;             /*!< (@ 0x40052104) CLK_APLL clock status register */
+  __I  uint32_t  RESERVED1[62];
+  __IO uint32_t  CLK_APB2_USART3_CFG;       /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */
+  __I  uint32_t  CLK_APB2_USART3_STAT;      /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */
+  __I  uint32_t  RESERVED2[62];
+  __IO uint32_t  CLK_APB2_USART2_CFG;       /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */
+  __I  uint32_t  CLK_APB2_USART2_STAT;      /*!< (@ 0x40052304) CLK_APB2_USART clock status register */
+  __I  uint32_t  RESERVED3[62];
+  __IO uint32_t  CLK_APB0_UART1_CFG;        /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */
+  __I  uint32_t  CLK_APB0_UART1_STAT;       /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */
+  __I  uint32_t  RESERVED4[62];
+  __IO uint32_t  CLK_APB0_USART0_CFG;       /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */
+  __I  uint32_t  CLK_APB0_USART0_STAT;      /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  CLK_APB2_SSP1_CFG;         /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */
+  __I  uint32_t  CLK_APB2_SSP1_STAT;        /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */
+  __I  uint32_t  RESERVED6[62];
+  __IO uint32_t  CLK_APB0_SSP0_CFG;         /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */
+  __I  uint32_t  CLK_APB0_SSP0_STAT;        /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */
+  __I  uint32_t  RESERVED7[62];
+  __IO uint32_t  CLK_SDIO_CFG;              /*!< (@ 0x40052800) CLK_SDIO clock configuration register */
+  __I  uint32_t  CLK_SDIO_STAT;             /*!< (@ 0x40052804) CLK_SDIO clock status register */
+} LPC_CCU2_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          RGU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13  (RGU)
+  */
+
+typedef struct {                            /*!< (@ 0x40053000) RGU Structure          */
+  __I  uint32_t  RESERVED0[64];
+  __O  uint32_t  RESET_CTRL0;               /*!< (@ 0x40053100) Reset control register 0 */
+  __O  uint32_t  RESET_CTRL1;               /*!< (@ 0x40053104) Reset control register 1 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  RESET_STATUS0;             /*!< (@ 0x40053110) Reset status register 0 */
+  __IO uint32_t  RESET_STATUS1;             /*!< (@ 0x40053114) Reset status register 1 */
+  __IO uint32_t  RESET_STATUS2;             /*!< (@ 0x40053118) Reset status register 2 */
+  __IO uint32_t  RESET_STATUS3;             /*!< (@ 0x4005311C) Reset status register 3 */
+  __I  uint32_t  RESERVED2[12];
+  __I  uint32_t  RESET_ACTIVE_STATUS0;      /*!< (@ 0x40053150) Reset active status register 0 */
+  __I  uint32_t  RESET_ACTIVE_STATUS1;      /*!< (@ 0x40053154) Reset active status register 1 */
+  __I  uint32_t  RESERVED3[170];
+  __IO uint32_t  RESET_EXT_STAT0;           /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */
+  __IO uint32_t  RESET_EXT_STAT1;           /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */
+  __IO uint32_t  RESET_EXT_STAT2;           /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  RESET_EXT_STAT4;           /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */
+  __IO uint32_t  RESET_EXT_STAT5;           /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  RESET_EXT_STAT8;           /*!< (@ 0x40053420) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT9;           /*!< (@ 0x40053424) Reset external status register */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  RESET_EXT_STAT13;          /*!< (@ 0x40053434) Reset external status register */
+  __I  uint32_t  RESERVED7[2];
+  __IO uint32_t  RESET_EXT_STAT16;          /*!< (@ 0x40053440) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT17;          /*!< (@ 0x40053444) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT18;          /*!< (@ 0x40053448) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT19;          /*!< (@ 0x4005344C) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT20;          /*!< (@ 0x40053450) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT21;          /*!< (@ 0x40053454) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT22;          /*!< (@ 0x40053458) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT23;          /*!< (@ 0x4005345C) Reset external status register */
+  __I  uint32_t  RESERVED8[4];
+  __IO uint32_t  RESET_EXT_STAT28;          /*!< (@ 0x40053470) Reset external status register */
+  __I  uint32_t  RESERVED9[3];
+  __IO uint32_t  RESET_EXT_STAT32;          /*!< (@ 0x40053480) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT33;          /*!< (@ 0x40053484) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT34;          /*!< (@ 0x40053488) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT35;          /*!< (@ 0x4005348C) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT36;          /*!< (@ 0x40053490) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT37;          /*!< (@ 0x40053494) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT38;          /*!< (@ 0x40053498) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT39;          /*!< (@ 0x4005349C) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT40;          /*!< (@ 0x400534A0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT41;          /*!< (@ 0x400534A4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT42;          /*!< (@ 0x400534A8) Reset external status register */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  RESET_EXT_STAT44;          /*!< (@ 0x400534B0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT45;          /*!< (@ 0x400534B4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT46;          /*!< (@ 0x400534B8) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT47;          /*!< (@ 0x400534BC) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT48;          /*!< (@ 0x400534C0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT49;          /*!< (@ 0x400534C4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT50;          /*!< (@ 0x400534C8) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT51;          /*!< (@ 0x400534CC) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT52;          /*!< (@ 0x400534D0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT53;          /*!< (@ 0x400534D4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT54;          /*!< (@ 0x400534D8) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT55;          /*!< (@ 0x400534DC) Reset external status register */
+} LPC_RGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         WWDT                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (WWDT)
+  */
+
+typedef struct {                            /*!< (@ 0x40080000) WWDT Structure         */
+  __IO uint32_t  MOD;                       /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+  __IO uint32_t  TC;                        /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */
+  __O  uint32_t  FEED;                      /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+  __I  uint32_t  TV;                        /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  WARNINT;                   /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+  __IO uint32_t  WINDOW;                    /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        USARTn                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (USARTn)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) USARTn Structure       */
+  
+  union {
+    __IO uint32_t  DLL;                     /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+    __O  uint32_t  THR;                     /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+    __I  uint32_t  RBR;                     /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+  } ;
+  
+  union {
+    __IO uint32_t IER;                      /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+    __IO uint32_t DLM;                      /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+  } ;
+  
+  union {
+    __O  uint32_t FCR;                      /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */
+    __I  uint32_t IIR;                      /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+  } ;
+  __IO uint32_t LCR;                        /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */
+  __I  uint32_t RESERVED0[1];
+  __I  uint32_t LSR;                        /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+  __I  uint32_t RESERVED1[1];
+  __IO uint32_t SCR;                        /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */
+  __IO uint32_t ACR;                        /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+  __IO uint32_t ICR;                        /*!< (@ 0x400xx024) IrDA control register (UART3 only) */
+  __IO uint32_t FDR;                        /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+  __IO uint32_t OSR;                        /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t HDEN;                       /*!< (@ 0x400xx03C) Half-duplex enable Register */
+  __I  uint32_t RESERVED3[1];
+  __IO uint32_t SCICTRL;                    /*!< (@ 0x400xx048) Smart card interface control register */
+  __IO uint32_t RS485CTRL;                  /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+  __IO uint32_t RS485DLY;                   /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */
+  __IO uint32_t SYNCCTRL;                   /*!< (@ 0x400xx058) Synchronous mode control register. */
+  __IO uint32_t TER;                        /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+} LPC_USARTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         UART1                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (UART1)
+  */
+
+typedef struct {                            /*!< (@ 0x40082000) UART1 Structure        */
+  
+  union {
+    __IO uint32_t  DLL;                     /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+    __O  uint32_t  THR;                     /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+    __I  uint32_t  RBR;                     /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+  } ;
+  
+  union {
+    __IO uint32_t  IER;                     /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */
+    __IO uint32_t  DLM;                     /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */
+  } ;
+  
+  union {
+    __O  uint32_t  FCR;                     /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */
+    __I  uint32_t  IIR;                     /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+  } ;
+  __IO uint32_t  LCR;                       /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */
+  __IO uint32_t  MCR;                       /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */
+  __I  uint32_t  LSR;                       /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+  __I  uint32_t  MSR;                       /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */
+  __IO uint32_t  SCR;                       /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */
+  __IO uint32_t  ACR;                       /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  FDR;                       /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  TER;                       /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+  __I  uint32_t  RESERVED2[6];
+  __IO uint32_t  RS485CTRL;                 /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+  __IO uint32_t  RS485ADRMATCH;             /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+  __IO uint32_t  RS485DLY;                  /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */
+  __I  uint32_t  FIFOLVL;                   /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs.  */
+} LPC_UART1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SSPn                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (SSP0)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) SSPn Structure         */
+  __IO uint32_t CR0;                        /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+  __IO uint32_t CR1;                        /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */
+  __IO uint32_t DR;                         /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+  __I  uint32_t SR;                         /*!< (@ 0x400xx00C) Status Register        */
+  __IO uint32_t CPSR;                       /*!< (@ 0x400xx010) Clock Prescale Register */
+  __IO uint32_t IMSC;                       /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */
+  __I  uint32_t RIS;                        /*!< (@ 0x400xx018) Raw Interrupt Status Register */
+  __I  uint32_t MIS;                        /*!< (@ 0x400xx01C) Masked Interrupt Status Register */
+  __O  uint32_t ICR;                        /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */
+  __IO uint32_t DMACR;                      /*!< (@ 0x400xx024) SSPn DMA control register */
+} LPC_SSPn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        TIMERn                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (TIMERn)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) TIMERn Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  __IO uint32_t MR[4];                      /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  __IO uint32_t CCR;                        /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  __IO uint32_t CR[4];                      /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+  __IO uint32_t EMR;                        /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+  __I  uint32_t  RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMERn_Type;
+
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          SCU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10  (SCU)
+  */
+
+typedef struct {                            /*!< (@ 0x40086000) SCU Structure          */
+  __IO uint32_t  SFSP0_0;                   /*!< (@ 0x40086000) Pin configuration register for pins P0 */
+  __IO uint32_t  SFSP0_1;                   /*!< (@ 0x40086004) Pin configuration register for pins P0 */
+  __I  uint32_t  RESERVED0[30];
+  __IO uint32_t  SFSP1_0;                   /*!< (@ 0x40086080) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_1;                   /*!< (@ 0x40086084) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_2;                   /*!< (@ 0x40086088) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_3;                   /*!< (@ 0x4008608C) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_4;                   /*!< (@ 0x40086090) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_5;                   /*!< (@ 0x40086094) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_6;                   /*!< (@ 0x40086098) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_7;                   /*!< (@ 0x4008609C) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_8;                   /*!< (@ 0x400860A0) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_9;                   /*!< (@ 0x400860A4) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_10;                  /*!< (@ 0x400860A8) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_11;                  /*!< (@ 0x400860AC) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_12;                  /*!< (@ 0x400860B0) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_13;                  /*!< (@ 0x400860B4) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_14;                  /*!< (@ 0x400860B8) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_15;                  /*!< (@ 0x400860BC) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_16;                  /*!< (@ 0x400860C0) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_17;                  /*!< (@ 0x400860C4) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_18;                  /*!< (@ 0x400860C8) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_19;                  /*!< (@ 0x400860CC) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_20;                  /*!< (@ 0x400860D0) Pin configuration register for pins P1 */
+  __I  uint32_t  RESERVED1[11];
+  __IO uint32_t  SFSP2_0;                   /*!< (@ 0x40086100) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_1;                   /*!< (@ 0x40086104) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_2;                   /*!< (@ 0x40086108) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_3;                   /*!< (@ 0x4008610C) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_4;                   /*!< (@ 0x40086110) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_5;                   /*!< (@ 0x40086114) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_6;                   /*!< (@ 0x40086118) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_7;                   /*!< (@ 0x4008611C) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_8;                   /*!< (@ 0x40086120) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_9;                   /*!< (@ 0x40086124) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_10;                  /*!< (@ 0x40086128) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_11;                  /*!< (@ 0x4008612C) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_12;                  /*!< (@ 0x40086130) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_13;                  /*!< (@ 0x40086134) Pin configuration register for pins P2 */
+  __I  uint32_t  RESERVED2[18];
+  __IO uint32_t  SFSP3_0;                   /*!< (@ 0x40086180) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_1;                   /*!< (@ 0x40086184) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_2;                   /*!< (@ 0x40086188) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_3;                   /*!< (@ 0x4008618C) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_4;                   /*!< (@ 0x40086190) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_5;                   /*!< (@ 0x40086194) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_6;                   /*!< (@ 0x40086198) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_7;                   /*!< (@ 0x4008619C) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_8;                   /*!< (@ 0x400861A0) Pin configuration register for pins P3 */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  SFSP4_0;                   /*!< (@ 0x40086200) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_1;                   /*!< (@ 0x40086204) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_2;                   /*!< (@ 0x40086208) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_3;                   /*!< (@ 0x4008620C) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_4;                   /*!< (@ 0x40086210) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_5;                   /*!< (@ 0x40086214) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_6;                   /*!< (@ 0x40086218) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_7;                   /*!< (@ 0x4008621C) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_8;                   /*!< (@ 0x40086220) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_9;                   /*!< (@ 0x40086224) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_10;                  /*!< (@ 0x40086228) Pin configuration register for pins P4 */
+  __I  uint32_t  RESERVED4[21];
+  __IO uint32_t  SFSP5_0;                   /*!< (@ 0x40086280) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_1;                   /*!< (@ 0x40086284) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_2;                   /*!< (@ 0x40086288) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_3;                   /*!< (@ 0x4008628C) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_4;                   /*!< (@ 0x40086290) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_5;                   /*!< (@ 0x40086294) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_6;                   /*!< (@ 0x40086298) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_7;                   /*!< (@ 0x4008629C) Pin configuration register for pins P5 */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  SFSP6_0;                   /*!< (@ 0x40086300) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_1;                   /*!< (@ 0x40086304) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_2;                   /*!< (@ 0x40086308) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_3;                   /*!< (@ 0x4008630C) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_4;                   /*!< (@ 0x40086310) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_5;                   /*!< (@ 0x40086314) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_6;                   /*!< (@ 0x40086318) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_7;                   /*!< (@ 0x4008631C) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_8;                   /*!< (@ 0x40086320) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_9;                   /*!< (@ 0x40086324) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_10;                  /*!< (@ 0x40086328) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_11;                  /*!< (@ 0x4008632C) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_12;                  /*!< (@ 0x40086330) Pin configuration register for pins P6 */
+  __I  uint32_t  RESERVED6[19];
+  __IO uint32_t  SFSP7_0;                   /*!< (@ 0x40086380) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_1;                   /*!< (@ 0x40086384) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_2;                   /*!< (@ 0x40086388) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_3;                   /*!< (@ 0x4008638C) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_4;                   /*!< (@ 0x40086390) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_5;                   /*!< (@ 0x40086394) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_6;                   /*!< (@ 0x40086398) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_7;                   /*!< (@ 0x4008639C) Pin configuration register for pins P7 */
+  __I  uint32_t  RESERVED7[24];
+  __IO uint32_t  SFSP8_0;                   /*!< (@ 0x40086400) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_1;                   /*!< (@ 0x40086404) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_2;                   /*!< (@ 0x40086408) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_3;                   /*!< (@ 0x4008640C) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_4;                   /*!< (@ 0x40086410) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_5;                   /*!< (@ 0x40086414) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_6;                   /*!< (@ 0x40086418) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_7;                   /*!< (@ 0x4008641C) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_8;                   /*!< (@ 0x40086420) Pin configuration register for pins P8 */
+  __I  uint32_t  RESERVED8[23];
+  __IO uint32_t  SFSP9_0;                   /*!< (@ 0x40086480) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_1;                   /*!< (@ 0x40086484) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_2;                   /*!< (@ 0x40086488) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_3;                   /*!< (@ 0x4008648C) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_4;                   /*!< (@ 0x40086490) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_5;                   /*!< (@ 0x40086494) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_6;                   /*!< (@ 0x40086498) Pin configuration register for pins P9 */
+  __I  uint32_t  RESERVED9[25];
+  __IO uint32_t  SFSPA_0;                   /*!< (@ 0x40086500) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_1;                   /*!< (@ 0x40086504) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_2;                   /*!< (@ 0x40086508) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_3;                   /*!< (@ 0x4008650C) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_4;                   /*!< (@ 0x40086510) Pin configuration register for pins PA */
+  __I  uint32_t  RESERVED10[27];
+  __IO uint32_t  SFSPB_0;                   /*!< (@ 0x40086580) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_1;                   /*!< (@ 0x40086584) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_2;                   /*!< (@ 0x40086588) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_3;                   /*!< (@ 0x4008658C) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_4;                   /*!< (@ 0x40086590) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_5;                   /*!< (@ 0x40086594) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_6;                   /*!< (@ 0x40086598) Pin configuration register for pins PB */
+  __I  uint32_t  RESERVED11[25];
+  __IO uint32_t  SFSPC_0;                   /*!< (@ 0x40086600) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_1;                   /*!< (@ 0x40086604) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_2;                   /*!< (@ 0x40086608) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_3;                   /*!< (@ 0x4008660C) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_4;                   /*!< (@ 0x40086610) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_5;                   /*!< (@ 0x40086614) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_6;                   /*!< (@ 0x40086618) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_7;                   /*!< (@ 0x4008661C) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_8;                   /*!< (@ 0x40086620) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_9;                   /*!< (@ 0x40086624) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_10;                  /*!< (@ 0x40086628) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_11;                  /*!< (@ 0x4008662C) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_12;                  /*!< (@ 0x40086630) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_13;                  /*!< (@ 0x40086634) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_14;                  /*!< (@ 0x40086638) Pin configuration register for pins PC */
+  __I  uint32_t  RESERVED12[17];
+  __IO uint32_t  SFSPD_0;                   /*!< (@ 0x40086680) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_1;                   /*!< (@ 0x40086684) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_2;                   /*!< (@ 0x40086688) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_3;                   /*!< (@ 0x4008668C) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_4;                   /*!< (@ 0x40086690) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_5;                   /*!< (@ 0x40086694) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_6;                   /*!< (@ 0x40086698) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_7;                   /*!< (@ 0x4008669C) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_8;                   /*!< (@ 0x400866A0) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_9;                   /*!< (@ 0x400866A4) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_10;                  /*!< (@ 0x400866A8) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_11;                  /*!< (@ 0x400866AC) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_12;                  /*!< (@ 0x400866B0) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_13;                  /*!< (@ 0x400866B4) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_14;                  /*!< (@ 0x400866B8) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_15;                  /*!< (@ 0x400866BC) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_16;                  /*!< (@ 0x400866C0) Pin configuration register for pins PD */
+  __I  uint32_t  RESERVED13[15];
+  __IO uint32_t  SFSPE_0;                   /*!< (@ 0x40086700) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_1;                   /*!< (@ 0x40086704) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_2;                   /*!< (@ 0x40086708) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_3;                   /*!< (@ 0x4008670C) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_4;                   /*!< (@ 0x40086710) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_5;                   /*!< (@ 0x40086714) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_6;                   /*!< (@ 0x40086718) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_7;                   /*!< (@ 0x4008671C) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_8;                   /*!< (@ 0x40086720) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_9;                   /*!< (@ 0x40086724) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_10;                  /*!< (@ 0x40086728) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_11;                  /*!< (@ 0x4008672C) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_12;                  /*!< (@ 0x40086730) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_13;                  /*!< (@ 0x40086734) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_14;                  /*!< (@ 0x40086738) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_15;                  /*!< (@ 0x4008673C) Pin configuration register for pins PE */
+  __I  uint32_t  RESERVED14[16];
+  __IO uint32_t  SFSPF_0;                   /*!< (@ 0x40086780) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_1;                   /*!< (@ 0x40086784) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_2;                   /*!< (@ 0x40086788) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_3;                   /*!< (@ 0x4008678C) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_4;                   /*!< (@ 0x40086790) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_5;                   /*!< (@ 0x40086794) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_6;                   /*!< (@ 0x40086798) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_7;                   /*!< (@ 0x4008679C) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_8;                   /*!< (@ 0x400867A0) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_9;                   /*!< (@ 0x400867A4) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_10;                  /*!< (@ 0x400867A8) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_11;                  /*!< (@ 0x400867AC) Pin configuration register for pins PF */
+  __I  uint32_t  RESERVED15[276];
+  __IO uint32_t  SFSCLK_0;                  /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */
+  __IO uint32_t  SFSCLK_1;                  /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */
+  __IO uint32_t  SFSCLK_2;                  /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */
+  __IO uint32_t  SFSCLK_3;                  /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */
+  __I  uint32_t  RESERVED16[28];
+  __IO uint32_t  SFSUSB;                    /*!< (@ 0x40086C80) Pin configuration register for */
+  __IO uint32_t  SFSI2C0;                   /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */
+  __IO uint32_t  ENAIO0;                    /*!< (@ 0x40086C88) ADC0 function select register */
+  __IO uint32_t  ENAIO1;                    /*!< (@ 0x40086C8C) ADC1 function select register */
+  __IO uint32_t  ENAIO2;                    /*!< (@ 0x40086C90) Analog function select register */
+  __I  uint32_t  RESERVED17[27];
+  __IO uint32_t  EMCDELAYCLK;               /*!< (@ 0x40086D00) EMC clock delay register */
+  __I  uint32_t  RESERVED18[63];
+  __IO uint32_t  PINTSEL0;                  /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */
+  __IO uint32_t  PINTSEL1;                  /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                     GPIO_PIN_INT                                     -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief GPIO pin interrupt (GPIO_PIN_INT)
+  */
+
+typedef struct {                            /*!< (@ 0x40087000) GPIO_PIN_INT Structure */
+  __IO uint32_t  ISEL;                      /*!< (@ 0x40087000) Pin Interrupt Mode register */
+  __IO uint32_t  IENR;                      /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */
+  __O  uint32_t  SIENR;                     /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */
+  __O  uint32_t  CIENR;                     /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */
+  __IO uint32_t  IENF;                      /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */
+  __O  uint32_t  SIENF;                     /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+  __O  uint32_t  CIENF;                     /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+  __IO uint32_t  RISE;                      /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */
+  __IO uint32_t  FALL;                      /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */
+  __IO uint32_t  IST;                       /*!< (@ 0x40087024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                    GPIO_GROUP_INTn                                   -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
+  */
+
+typedef struct {                            /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40088000) GPIO grouped interrupt control register */
+  __I  uint32_t  RESERVED0[7];
+  __IO uint32_t  PORT_POL0;                 /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL1;                 /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL2;                 /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL3;                 /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL4;                 /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL5;                 /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL6;                 /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL7;                 /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_ENA0;                 /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA1;                 /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA2;                 /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA3;                 /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA4;                 /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA5;                 /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA6;                 /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA7;                 /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */
+} LPC_GPIO_GROUP_INTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         MCPWM                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7  (MCPWM)
+  */
+
+typedef struct {                            /*!< (@ 0x400A0000) MCPWM Structure        */
+  __I  uint32_t  CON;                       /*!< (@ 0x400A0000) PWM Control read address */
+  __O  uint32_t  CON_SET;                   /*!< (@ 0x400A0004) PWM Control set address */
+  __O  uint32_t  CON_CLR;                   /*!< (@ 0x400A0008) PWM Control clear address */
+  __I  uint32_t  CAPCON;                    /*!< (@ 0x400A000C) Capture Control read address */
+  __O  uint32_t  CAPCON_SET;                /*!< (@ 0x400A0010) Capture Control set address */
+  __O  uint32_t  CAPCON_CLR;                /*!< (@ 0x400A0014) Event Control clear address */
+  __IO uint32_t TC[3];                      /*!< (@ 0x400A0018) Timer Counter register */
+  __IO uint32_t LIM[3];                     /*!< (@ 0x400A0024) Limit register         */
+  __IO uint32_t MAT[3];                     /*!< (@ 0x400A0030) Match register         */
+  __IO uint32_t  DT;                        /*!< (@ 0x400A003C) Dead time register     */
+  __IO uint32_t  CCP;                       /*!< (@ 0x400A0040) Communication Pattern register */
+  __I  uint32_t CAP[3];                     /*!< (@ 0x400A0044) Capture register       */
+  __I  uint32_t  INTEN;                     /*!< (@ 0x400A0050) Interrupt Enable read address */
+  __O  uint32_t  INTEN_SET;                 /*!< (@ 0x400A0054) Interrupt Enable set address */
+  __O  uint32_t  INTEN_CLR;                 /*!< (@ 0x400A0058) Interrupt Enable clear address */
+  __I  uint32_t  CNTCON;                    /*!< (@ 0x400A005C) Count Control read address */
+  __O  uint32_t  CNTCON_SET;                /*!< (@ 0x400A0060) Count Control set address */
+  __O  uint32_t  CNTCON_CLR;                /*!< (@ 0x400A0064) Count Control clear address */
+  __I  uint32_t  INTF;                      /*!< (@ 0x400A0068) Interrupt flags read address */
+  __O  uint32_t  INTF_SET;                  /*!< (@ 0x400A006C) Interrupt flags set address */
+  __O  uint32_t  INTF_CLR;                  /*!< (@ 0x400A0070) Interrupt flags clear address */
+  __O  uint32_t  CAP_CLR;                   /*!< (@ 0x400A0074) Capture clear address  */
+} LPC_MCPWM_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         I2C0                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Cn)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) I2C0 Structure         */
+  __IO uint32_t CONSET;                     /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+  __I  uint32_t STAT;                       /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+  __IO uint32_t DAT;                        /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+  __IO uint32_t ADR0;                       /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t SCLH;                       /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+  __IO uint32_t SCLL;                       /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+  __O  uint32_t CONCLR;                     /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+  __IO uint32_t MMCTRL;                     /*!< (@ 0x400xx01C) Monitor mode control register. */
+  __IO uint32_t ADR1;                       /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t ADR2;                       /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t ADR3;                       /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+  __IO uint32_t MASK[4];                    /*!< (@ 0x400xx030) I2C Slave address mask register */
+} LPC_I2Cn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         I2Sn                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Sn)
+    0x400A2000 / 0x400A3000
+  */
+
+typedef struct {                            /*!< (@ 0x400Ax000) I2S Structure         */
+  __IO uint32_t DAO;                        /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */
+  __IO uint32_t DAI;                        /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */
+  __O  uint32_t TXFIFO;                     /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */
+  __I  uint32_t RXFIFO;                     /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */
+  __I  uint32_t STATE;                      /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */
+  __IO uint32_t DMA1;                       /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */
+  __IO uint32_t DMA2;                       /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */
+  __IO uint32_t IRQ;                        /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */
+  __IO uint32_t TXRATE;                     /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+  __IO uint32_t RXRATE;                     /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+  __IO uint32_t TXBITRATE;                  /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */
+  __IO uint32_t RXBITRATE;                  /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */
+  __IO uint32_t TXMODE;                     /*!< (@ 0x400Ax030) I2S Transmit mode control. */
+  __IO uint32_t RXMODE;                     /*!< (@ 0x400Ax034) I2S Receive mode control. */
+} LPC_I2Sn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        C_CANn                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7  (C_CANn)
+    0x400A4000 / 0x400E2000
+  */
+
+typedef struct {                            /*!< (@ 0x400E2000) C_CAN Structure       */
+  __IO uint32_t CNTL;                       /*!< (@ 0x400E2000) CAN control            */
+  __IO uint32_t STAT;                       /*!< (@ 0x400E2004) Status register        */
+  __I  uint32_t EC;                         /*!< (@ 0x400E2008) Error counter          */
+  __IO uint32_t BT;                         /*!< (@ 0x400E200C) Bit timing register    */
+  __I  uint32_t INT;                        /*!< (@ 0x400E2010) Interrupt register     */
+  __IO uint32_t TEST;                       /*!< (@ 0x400E2014) Test register          */
+  __IO uint32_t BRPE;                       /*!< (@ 0x400E2018) Baud rate prescaler extension register */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t IF1_CMDREQ;                 /*!< (@ 0x400E2020) Message interface command request  */
+  
+  union {
+    __IO uint32_t IF1_CMDMSK_R;             /*!< (@ 0x400E2024) Message interface command mask (read direction) */
+    __IO uint32_t IF1_CMDMSK_W;             /*!< (@ 0x400E2024) Message interface command mask (write direction) */
+  } ;
+  __IO uint32_t IF1_MSK1;                   /*!< (@ 0x400E2028) Message interface mask 1 */
+  __IO uint32_t IF1_MSK2;                   /*!< (@ 0x400E202C) Message interface 1 mask 2 */
+  __IO uint32_t IF1_ARB1;                   /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */
+  __IO uint32_t IF1_ARB2;                   /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */
+  __IO uint32_t IF1_MCTRL;                  /*!< (@ 0x400E2038) Message interface 1 message control */
+  __IO uint32_t IF1_DA1;                    /*!< (@ 0x400E203C) Message interface data A1 */
+  __IO uint32_t IF1_DA2;                    /*!< (@ 0x400E2040) Message interface 1 data A2 */
+  __IO uint32_t IF1_DB1;                    /*!< (@ 0x400E2044) Message interface 1 data B1 */
+  __IO uint32_t IF1_DB2;                    /*!< (@ 0x400E2048) Message interface 1 data B2 */
+  __I  uint32_t  RESERVED1[13];
+  __IO uint32_t IF2_CMDREQ;                 /*!< (@ 0x400E2080) Message interface command request  */
+  
+  union {
+    __IO uint32_t IF2_CMDMSK_R;             /*!< (@ 0x400E2084) Message interface command mask (read direction) */
+    __IO uint32_t IF2_CMDMSK_W;             /*!< (@ 0x400E2084) Message interface command mask (write direction) */
+  } ;
+  __IO uint32_t IF2_MSK1;                   /*!< (@ 0x400E2088) Message interface mask 1 */
+  __IO uint32_t IF2_MSK2;                   /*!< (@ 0x400E208C) Message interface 1 mask 2 */
+  __IO uint32_t IF2_ARB1;                   /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */
+  __IO uint32_t IF2_ARB2;                   /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */
+  __IO uint32_t IF2_MCTRL;                  /*!< (@ 0x400E2098) Message interface 1 message control */
+  __IO uint32_t IF2_DA1;                    /*!< (@ 0x400E209C) Message interface data A1 */
+  __IO uint32_t IF2_DA2;                    /*!< (@ 0x400E20A0) Message interface 1 data A2 */
+  __IO uint32_t IF2_DB1;                    /*!< (@ 0x400E20A4) Message interface 1 data B1 */
+  __IO uint32_t IF2_DB2;                    /*!< (@ 0x400E20A8) Message interface 1 data B2 */
+  __I  uint32_t  RESERVED2[21];
+  __I  uint32_t TXREQ1;                     /*!< (@ 0x400E2100) Transmission request 1 */
+  __I  uint32_t TXREQ2;                     /*!< (@ 0x400E2104) Transmission request 2 */
+  __I  uint32_t  RESERVED3[6];
+  __I  uint32_t ND1;                        /*!< (@ 0x400E2120) New data 1             */
+  __I  uint32_t ND2;                        /*!< (@ 0x400E2124) New data 2             */
+  __I  uint32_t  RESERVED4[6];
+  __I  uint32_t IR1;                        /*!< (@ 0x400E2140) Interrupt pending 1    */
+  __I  uint32_t IR2;                        /*!< (@ 0x400E2144) Interrupt pending 2    */
+  __I  uint32_t  RESERVED5[6];
+  __I  uint32_t MSGV1;                      /*!< (@ 0x400E2160) Message valid 1        */
+  __I  uint32_t MSGV2;                      /*!< (@ 0x400E2164) Message valid 2        */
+  __I  uint32_t  RESERVED6[6];
+  __IO uint32_t CLKDIV;                     /*!< (@ 0x400E2180) CAN clock divider register */
+} LPC_C_CANn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        RITIMER                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (RITIMER)
+  */
+
+typedef struct {                            /*!< (@ 0x400C0000) RITIMER Structure      */
+  __IO uint32_t  COMPVAL;                   /*!< (@ 0x400C0000) Compare register       */
+  __IO uint32_t  MASK;                      /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x400C0008) Control register.      */
+  __IO uint32_t  COUNTER;                   /*!< (@ 0x400C000C) 32-bit counter         */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          QEI                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7  (QEI)
+  */
+
+typedef struct {                            /*!< (@ 0x400C6000) QEI Structure          */
+  __O  uint32_t  CON;                       /*!< (@ 0x400C6000) Control register       */
+  __I  uint32_t  STAT;                      /*!< (@ 0x400C6004) Encoder status register */
+  __IO uint32_t  CONF;                      /*!< (@ 0x400C6008) Configuration register */
+  __I  uint32_t  POS;                       /*!< (@ 0x400C600C) Position register      */
+  __IO uint32_t  MAXPOS;                    /*!< (@ 0x400C6010) Maximum position register */
+  __IO uint32_t  CMPOS0;                    /*!< (@ 0x400C6014) position compare register 0 */
+  __IO uint32_t  CMPOS1;                    /*!< (@ 0x400C6018) position compare register 1 */
+  __IO uint32_t  CMPOS2;                    /*!< (@ 0x400C601C) position compare register 2 */
+  __I  uint32_t  INXCNT;                    /*!< (@ 0x400C6020) Index count register   */
+  __IO uint32_t  INXCMP0;                   /*!< (@ 0x400C6024) Index compare register 0 */
+  __IO uint32_t  LOAD;                      /*!< (@ 0x400C6028) Velocity timer reload register */
+  __I  uint32_t  TIME;                      /*!< (@ 0x400C602C) Velocity timer register */
+  __I  uint32_t  VEL;                       /*!< (@ 0x400C6030) Velocity counter register */
+  __I  uint32_t  CAP;                       /*!< (@ 0x400C6034) Velocity capture register */
+  __IO uint32_t  VELCOMP;                   /*!< (@ 0x400C6038) Velocity compare register */
+  __IO uint32_t  FILTERPHA;                 /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */
+  __IO uint32_t  FILTERPHB;                 /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */
+  __IO uint32_t  FILTERINX;                 /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */
+  __IO uint32_t  WINDOW;                    /*!< (@ 0x400C6048) Index acceptance window register */
+  __IO uint32_t  INXCMP1;                   /*!< (@ 0x400C604C) Index compare register 1 */
+  __IO uint32_t  INXCMP2;                   /*!< (@ 0x400C6050) Index compare register 2 */
+  __I  uint32_t  RESERVED0[993];
+  __O  uint32_t  IEC;                       /*!< (@ 0x400C6FD8) Interrupt enable clear register */
+  __O  uint32_t  IES;                       /*!< (@ 0x400C6FDC) Interrupt enable set register */
+  __I  uint32_t  INTSTAT;                   /*!< (@ 0x400C6FE0) Interrupt status register */
+  __I  uint32_t  IE;                        /*!< (@ 0x400C6FE4) Interrupt enable register */
+  __O  uint32_t  CLR;                       /*!< (@ 0x400C6FE8) Interrupt status clear register */
+  __O  uint32_t  SET;                       /*!< (@ 0x400C6FEC) Interrupt status set register */
+} LPC_QEI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         GIMA                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3  (GIMA)
+  */
+
+typedef struct {                            /*!< (@ 0x400C7000) GIMA Structure         */
+  __IO uint32_t  CAP0_0_IN;                 /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+  __IO uint32_t  CAP0_1_IN;                 /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+  __IO uint32_t  CAP0_2_IN;                 /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+  __IO uint32_t  CAP0_3_IN;                 /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+  __IO uint32_t  CAP1_0_IN;                 /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+  __IO uint32_t  CAP1_1_IN;                 /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+  __IO uint32_t  CAP1_2_IN;                 /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+  __IO uint32_t  CAP1_3_IN;                 /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+  __IO uint32_t  CAP2_0_IN;                 /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+  __IO uint32_t  CAP2_1_IN;                 /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+  __IO uint32_t  CAP2_2_IN;                 /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+  __IO uint32_t  CAP2_3_IN;                 /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+  __IO uint32_t  CAP3_0_IN;                 /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+  __IO uint32_t  CAP3_1_IN;                 /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+  __IO uint32_t  CAP3_2_IN;                 /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+  __IO uint32_t  CAP3_3_IN;                 /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+  __IO uint32_t  CTIN_0_IN;                 /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+  __IO uint32_t  CTIN_1_IN;                 /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+  __IO uint32_t  CTIN_2_IN;                 /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+  __IO uint32_t  CTIN_3_IN;                 /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+  __IO uint32_t  CTIN_4_IN;                 /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+  __IO uint32_t  CTIN_5_IN;                 /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+  __IO uint32_t  CTIN_6_IN;                 /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+  __IO uint32_t  CTIN_7_IN;                 /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+  __IO uint32_t  VADC_TRIGGER_IN;           /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */
+  __IO uint32_t  EVENTROUTER_13_IN;         /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */
+  __IO uint32_t  EVENTROUTER_14_IN;         /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */
+  __IO uint32_t  EVENTROUTER_16_IN;         /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */
+  __IO uint32_t  ADCSTART0_IN;              /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */
+  __IO uint32_t  ADCSTART1_IN;              /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */
+} LPC_GIMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          DAC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7  (DAC)
+  */
+
+typedef struct {                            /*!< (@ 0x400E1000) DAC Structure          */
+  __IO uint32_t  CR;                        /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x400E1004) DAC control register.  */
+  __IO uint32_t  CNTVAL;                    /*!< (@ 0x400E1008) DAC counter value register. */
+} LPC_DAC_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         ADCn                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7  (ADCn)
+    0x400E3000 / 0x400E4000
+  */
+
+typedef struct {                            /*!< (@ 0x400Ex000) ADCn Structure         */
+  __IO uint32_t CR;                         /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+  __I  uint32_t GDR;                        /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t INTEN;                      /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+  __I  uint32_t DR[8];                      /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+  __I  uint32_t STAT;                       /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADCn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       GPIO_PORT                                      -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief GPIO port  (GPIO_PORT)
+  */
+
+typedef struct {                            /*!< (@ 0x400F4000) GPIO_PORT Structure    */
+  __IO uint8_t B[256];                      /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
+  __I  uint32_t  RESERVED0[960];
+  __IO uint32_t W[256];                     /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */
+  __I  uint32_t  RESERVED1[768];
+  __IO uint32_t DIR[8];                     /*!< (@ 0x400F6000) Direction registers port n */
+  __I  uint32_t  RESERVED2[24];
+  __IO uint32_t MASK[8];                    /*!< (@ 0x400F6080) Mask register port n   */
+  __I  uint32_t  RESERVED3[24];
+  __IO uint32_t PIN[8];                     /*!< (@ 0x400F6100) Portpin register port n */
+  __I  uint32_t  RESERVED4[24];
+  __IO uint32_t MPIN[8];                    /*!< (@ 0x400F6180) Masked port register port n */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t SET[8];                     /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */
+  __I  uint32_t  RESERVED6[24];
+  __O  uint32_t CLR[8];                     /*!< (@ 0x400F6280) Clear port n           */
+  __I  uint32_t  RESERVED7[24];
+  __O  uint32_t NOT[8];                     /*!< (@ 0x400F6300) Toggle port n          */
+} LPC_GPIO_PORT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          SPI                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3  (SPI)
+  */
+
+typedef struct {                            /*!< (@ 0x40100000) SPI Structure          */
+  __IO uint32_t  CR;                        /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */
+  __I  uint32_t  SR;                        /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */
+  __IO uint32_t  DR;                        /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
+  __IO uint32_t  CCR;                       /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+  __IO uint32_t  TCR;                       /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */
+  __IO uint32_t  TSR;                       /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  INT;                       /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+} LPC_SPI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SGPIO                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3  (SGPIO)
+  */
+
+typedef struct {                            /*!< (@ 0x40101000) SGPIO Structure        */
+  __IO uint32_t  OUT_MUX_CFG[16];              /*!< (@ 0x40101000) Pin multiplexer configurationregisters. */
+  __IO uint32_t  SGPIO_MUX_CFG[16];            /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */
+  __IO uint32_t  SLICE_MUX_CFG[16];            /*!< (@ 0x40101080) Slice multiplexer configuration registers. */
+  __IO uint32_t  REG[16];                      /*!< (@ 0x401010C0) Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
+  __IO uint32_t  REG_SS[16];                   /*!< (@ 0x40101100) Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
+  __IO uint32_t  PRESET[16];                   /*!< (@ 0x40101140) Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
+  __IO uint32_t  COUNT[16];                    /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */
+  __IO uint32_t  POS[16];                      /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 */
+  __IO uint32_t  MASK_A;                    /*!< (@ 0x40101200) Mask for pattern match function of slice A */
+  __IO uint32_t  MASK_H;                    /*!< (@ 0x40101204) Mask for pattern match function of slice H */
+  __IO uint32_t  MASK_I;                    /*!< (@ 0x40101208) Mask for pattern match function of slice I */
+  __IO uint32_t  MASK_P;                    /*!< (@ 0x4010120C) Mask for pattern match function of slice P */
+  __I  uint32_t  GPIO_INREG;                /*!< (@ 0x40101210) GPIO input status register */
+  __IO uint32_t  GPIO_OUTREG;               /*!< (@ 0x40101214) GPIO output control register */
+  __IO uint32_t  GPIO_OENREG;               /*!< (@ 0x40101218) GPIO OE control register */
+  __IO uint32_t  CTRL_ENABLED;              /*!< (@ 0x4010121C) Enables the slice COUNT counter */
+  __IO uint32_t  CTRL_DISABLED;             /*!< (@ 0x40101220) Disables the slice COUNT counter */
+  __I  uint32_t  RESERVED0[823];
+  __O  uint32_t  CLR_EN_0;                  /*!< (@ 0x40101F00) Shift clock interrupt clear mask */
+  __O  uint32_t  SET_EN_0;                  /*!< (@ 0x40101F04) Shift clock interrupt set mask */
+  __I  uint32_t  ENABLE_0;                  /*!< (@ 0x40101F08) Shift clock interrupt enable */
+  __I  uint32_t  STATUS_0;                  /*!< (@ 0x40101F0C) Shift clock interrupt status */
+  __O  uint32_t  CTR_STATUS_0;              /*!< (@ 0x40101F10) Shift clock interrupt clear status */
+  __O  uint32_t  SET_STATUS_0;              /*!< (@ 0x40101F14) Shift clock interrupt set status */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  CLR_EN_1;                  /*!< (@ 0x40101F20) Capture clock interrupt clear mask */
+  __O  uint32_t  SET_EN_1;                  /*!< (@ 0x40101F24) Capture clock interrupt set mask */
+  __I  uint32_t  ENABLE_1;                  /*!< (@ 0x40101F28) Capture clock interrupt enable */
+  __I  uint32_t  STATUS_1;                  /*!< (@ 0x40101F2C) Capture clock interrupt status */
+  __O  uint32_t  CTR_STATUS_1;              /*!< (@ 0x40101F30) Capture clock interrupt clear status */
+  __O  uint32_t  SET_STATUS_1;              /*!< (@ 0x40101F34) Capture clock interrupt set status */
+  __I  uint32_t  RESERVED2[2];
+  __O  uint32_t  CLR_EN_2;                  /*!< (@ 0x40101F40) Pattern match interrupt clear mask */
+  __O  uint32_t  SET_EN_2;                  /*!< (@ 0x40101F44) Pattern match interrupt set mask */
+  __I  uint32_t  ENABLE_2;                  /*!< (@ 0x40101F48) Pattern match interrupt enable */
+  __I  uint32_t  STATUS_2;                  /*!< (@ 0x40101F4C) Pattern match interrupt status */
+  __O  uint32_t  CTR_STATUS_2;              /*!< (@ 0x40101F50) Pattern match interrupt clear status */
+  __O  uint32_t  SET_STATUS_2;              /*!< (@ 0x40101F54) Pattern match interrupt set status */
+  __I  uint32_t  RESERVED3[2];
+  __O  uint32_t  CLR_EN_3;                  /*!< (@ 0x40101F60) Input interrupt clear mask */
+  __O  uint32_t  SET_EN_3;                  /*!< (@ 0x40101F64) Input bit match interrupt set mask */
+  __I  uint32_t  ENABLE_3;                  /*!< (@ 0x40101F68) Input bit match interrupt enable */
+  __I  uint32_t  STATUS_3;                  /*!< (@ 0x40101F6C) Input bit match interrupt status */
+  __O  uint32_t  CTR_STATUS_3;              /*!< (@ 0x40101F70) Input bit match interrupt clear status */
+  __O  uint32_t  SET_STATUS_3;              /*!< (@ 0x40101F74) Shift clock interrupt set status */
+} LPC_SGPIO_Type;
+
+
+
+/********************************************
+** End of section using anonymous unions   **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma pop
+#else
+  #error Not supported compiler type
+#endif
+
+
+#ifdef CMSIS_BITPOSITIONS
+// ------------------------------------------------------------------------------------------------
+// -----                                  SCT Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  SCT_CONFIG  -------------------------------------------
+#define SCT_CONFIG_UNIFY_Pos                                  0                                                         /*!< SCT CONFIG: UNIFY Position          */
+#define SCT_CONFIG_UNIFY_Msk                                  (0x01UL << SCT_CONFIG_UNIFY_Pos)                          /*!< SCT CONFIG: UNIFY Mask              */
+#define SCT_CONFIG_CLKMODE_Pos                                1                                                         /*!< SCT CONFIG: CLKMODE Position        */
+#define SCT_CONFIG_CLKMODE_Msk                                (0x03UL << SCT_CONFIG_CLKMODE_Pos)                        /*!< SCT CONFIG: CLKMODE Mask            */
+#define SCT_CONFIG_CLKSEL_Pos                                 3                                                         /*!< SCT CONFIG: CLKSEL Position         */
+#define SCT_CONFIG_CLKSEL_Msk                                 (0x0fUL << SCT_CONFIG_CLKSEL_Pos)                         /*!< SCT CONFIG: CLKSEL Mask             */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Pos                    7                                                         /*!< SCT CONFIG: NORELAODL_NORELOADU Position */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Msk                    (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos)            /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */
+#define SCT_CONFIG_NORELOADH_Pos                              8                                                         /*!< SCT CONFIG: NORELOADH Position      */
+#define SCT_CONFIG_NORELOADH_Msk                              (0x01UL << SCT_CONFIG_NORELOADH_Pos)                      /*!< SCT CONFIG: NORELOADH Mask          */
+#define SCT_CONFIG_INSYNCn_Pos                                9                                                         /*!< SCT CONFIG: INSYNCn Position        */
+#define SCT_CONFIG_INSYNCn_Msk                                (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos)                  /*!< SCT CONFIG: INSYNCn Mask            */
+
+// ----------------------------------------  SCT_CTRL  --------------------------------------------
+#define SCT_CTRL_DOWN_L_Pos                                   0                                                         /*!< SCT CTRL: DOWN_L Position           */
+#define SCT_CTRL_DOWN_L_Msk                                   (0x01UL << SCT_CTRL_DOWN_L_Pos)                           /*!< SCT CTRL: DOWN_L Mask               */
+#define SCT_CTRL_STOP_L_Pos                                   1                                                         /*!< SCT CTRL: STOP_L Position           */
+#define SCT_CTRL_STOP_L_Msk                                   (0x01UL << SCT_CTRL_STOP_L_Pos)                           /*!< SCT CTRL: STOP_L Mask               */
+#define SCT_CTRL_HALT_L_Pos                                   2                                                         /*!< SCT CTRL: HALT_L Position           */
+#define SCT_CTRL_HALT_L_Msk                                   (0x01UL << SCT_CTRL_HALT_L_Pos)                           /*!< SCT CTRL: HALT_L Mask               */
+#define SCT_CTRL_CLRCTR_L_Pos                                 3                                                         /*!< SCT CTRL: CLRCTR_L Position         */
+#define SCT_CTRL_CLRCTR_L_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_L_Pos)                         /*!< SCT CTRL: CLRCTR_L Mask             */
+#define SCT_CTRL_BIDIR_L_Pos                                  4                                                         /*!< SCT CTRL: BIDIR_L Position          */
+#define SCT_CTRL_BIDIR_L_Msk                                  (0x01UL << SCT_CTRL_BIDIR_L_Pos)                          /*!< SCT CTRL: BIDIR_L Mask              */
+#define SCT_CTRL_PRE_L_Pos                                    5                                                         /*!< SCT CTRL: PRE_L Position            */
+#define SCT_CTRL_PRE_L_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_L_Pos)                      /*!< SCT CTRL: PRE_L Mask                */
+#define SCT_CTRL_DOWN_H_Pos                                   16                                                        /*!< SCT CTRL: DOWN_H Position           */
+#define SCT_CTRL_DOWN_H_Msk                                   (0x01UL << SCT_CTRL_DOWN_H_Pos)                           /*!< SCT CTRL: DOWN_H Mask               */
+#define SCT_CTRL_STOP_H_Pos                                   17                                                        /*!< SCT CTRL: STOP_H Position           */
+#define SCT_CTRL_STOP_H_Msk                                   (0x01UL << SCT_CTRL_STOP_H_Pos)                           /*!< SCT CTRL: STOP_H Mask               */
+#define SCT_CTRL_HALT_H_Pos                                   18                                                        /*!< SCT CTRL: HALT_H Position           */
+#define SCT_CTRL_HALT_H_Msk                                   (0x01UL << SCT_CTRL_HALT_H_Pos)                           /*!< SCT CTRL: HALT_H Mask               */
+#define SCT_CTRL_CLRCTR_H_Pos                                 19                                                        /*!< SCT CTRL: CLRCTR_H Position         */
+#define SCT_CTRL_CLRCTR_H_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_H_Pos)                         /*!< SCT CTRL: CLRCTR_H Mask             */
+#define SCT_CTRL_BIDIR_H_Pos                                  20                                                        /*!< SCT CTRL: BIDIR_H Position          */
+#define SCT_CTRL_BIDIR_H_Msk                                  (0x01UL << SCT_CTRL_BIDIR_H_Pos)                          /*!< SCT CTRL: BIDIR_H Mask              */
+#define SCT_CTRL_PRE_H_Pos                                    21                                                        /*!< SCT CTRL: PRE_H Position            */
+#define SCT_CTRL_PRE_H_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_H_Pos)                      /*!< SCT CTRL: PRE_H Mask                */
+
+// ----------------------------------------  SCT_LIMIT  -------------------------------------------
+#define SCT_LIMIT_LIMMSK_L_Pos                                0                                                         /*!< SCT LIMIT: LIMMSK_L Position        */
+#define SCT_LIMIT_LIMMSK_L_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos)                  /*!< SCT LIMIT: LIMMSK_L Mask            */
+#define SCT_LIMIT_LIMMSK_H_Pos                                16                                                        /*!< SCT LIMIT: LIMMSK_H Position        */
+#define SCT_LIMIT_LIMMSK_H_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos)                  /*!< SCT LIMIT: LIMMSK_H Mask            */
+
+// ----------------------------------------  SCT_HALT  --------------------------------------------
+#define SCT_HALT_HALTMSK_L_Pos                                0                                                         /*!< SCT HALT: HALTMSK_L Position        */
+#define SCT_HALT_HALTMSK_L_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos)                  /*!< SCT HALT: HALTMSK_L Mask            */
+#define SCT_HALT_HALTMSK_H_Pos                                16                                                        /*!< SCT HALT: HALTMSK_H Position        */
+#define SCT_HALT_HALTMSK_H_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos)                  /*!< SCT HALT: HALTMSK_H Mask            */
+
+// ----------------------------------------  SCT_STOP  --------------------------------------------
+#define SCT_STOP_STOPMSK_L_Pos                                0                                                         /*!< SCT STOP: STOPMSK_L Position        */
+#define SCT_STOP_STOPMSK_L_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos)                  /*!< SCT STOP: STOPMSK_L Mask            */
+#define SCT_STOP_STOPMSK_H_Pos                                16                                                        /*!< SCT STOP: STOPMSK_H Position        */
+#define SCT_STOP_STOPMSK_H_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos)                  /*!< SCT STOP: STOPMSK_H Mask            */
+
+// ----------------------------------------  SCT_START  -------------------------------------------
+#define SCT_START_STARTMSK_L_Pos                              0                                                         /*!< SCT START: STARTMSK_L Position      */
+#define SCT_START_STARTMSK_L_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_L_Pos)                /*!< SCT START: STARTMSK_L Mask          */
+#define SCT_START_STARTMSK_H_Pos                              16                                                        /*!< SCT START: STARTMSK_H Position      */
+#define SCT_START_STARTMSK_H_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_H_Pos)                /*!< SCT START: STARTMSK_H Mask          */
+
+// ----------------------------------------  SCT_COUNT  -------------------------------------------
+#define SCT_COUNT_CTR_L_Pos                                   0                                                         /*!< SCT COUNT: CTR_L Position           */
+#define SCT_COUNT_CTR_L_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_L_Pos)                     /*!< SCT COUNT: CTR_L Mask               */
+#define SCT_COUNT_CTR_H_Pos                                   16                                                        /*!< SCT COUNT: CTR_H Position           */
+#define SCT_COUNT_CTR_H_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_H_Pos)                     /*!< SCT COUNT: CTR_H Mask               */
+
+// ----------------------------------------  SCT_STATE  -------------------------------------------
+#define SCT_STATE_STATE_L_Pos                                 0                                                         /*!< SCT STATE: STATE_L Position         */
+#define SCT_STATE_STATE_L_Msk                                 (0x1fUL << SCT_STATE_STATE_L_Pos)                         /*!< SCT STATE: STATE_L Mask             */
+#define SCT_STATE_STATE_H_Pos                                 16                                                        /*!< SCT STATE: STATE_H Position         */
+#define SCT_STATE_STATE_H_Msk                                 (0x1fUL << SCT_STATE_STATE_H_Pos)                         /*!< SCT STATE: STATE_H Mask             */
+
+// ----------------------------------------  SCT_INPUT  -------------------------------------------
+#define SCT_INPUT_AIN0_Pos                                    0                                                         /*!< SCT INPUT: AIN0 Position            */
+#define SCT_INPUT_AIN0_Msk                                    (0x01UL << SCT_INPUT_AIN0_Pos)                            /*!< SCT INPUT: AIN0 Mask                */
+#define SCT_INPUT_AIN1_Pos                                    1                                                         /*!< SCT INPUT: AIN1 Position            */
+#define SCT_INPUT_AIN1_Msk                                    (0x01UL << SCT_INPUT_AIN1_Pos)                            /*!< SCT INPUT: AIN1 Mask                */
+#define SCT_INPUT_AIN2_Pos                                    2                                                         /*!< SCT INPUT: AIN2 Position            */
+#define SCT_INPUT_AIN2_Msk                                    (0x01UL << SCT_INPUT_AIN2_Pos)                            /*!< SCT INPUT: AIN2 Mask                */
+#define SCT_INPUT_AIN3_Pos                                    3                                                         /*!< SCT INPUT: AIN3 Position            */
+#define SCT_INPUT_AIN3_Msk                                    (0x01UL << SCT_INPUT_AIN3_Pos)                            /*!< SCT INPUT: AIN3 Mask                */
+#define SCT_INPUT_AIN4_Pos                                    4                                                         /*!< SCT INPUT: AIN4 Position            */
+#define SCT_INPUT_AIN4_Msk                                    (0x01UL << SCT_INPUT_AIN4_Pos)                            /*!< SCT INPUT: AIN4 Mask                */
+#define SCT_INPUT_AIN5_Pos                                    5                                                         /*!< SCT INPUT: AIN5 Position            */
+#define SCT_INPUT_AIN5_Msk                                    (0x01UL << SCT_INPUT_AIN5_Pos)                            /*!< SCT INPUT: AIN5 Mask                */
+#define SCT_INPUT_AIN6_Pos                                    6                                                         /*!< SCT INPUT: AIN6 Position            */
+#define SCT_INPUT_AIN6_Msk                                    (0x01UL << SCT_INPUT_AIN6_Pos)                            /*!< SCT INPUT: AIN6 Mask                */
+#define SCT_INPUT_AIN7_Pos                                    7                                                         /*!< SCT INPUT: AIN7 Position            */
+#define SCT_INPUT_AIN7_Msk                                    (0x01UL << SCT_INPUT_AIN7_Pos)                            /*!< SCT INPUT: AIN7 Mask                */
+#define SCT_INPUT_SIN0_Pos                                    16                                                        /*!< SCT INPUT: SIN0 Position            */
+#define SCT_INPUT_SIN0_Msk                                    (0x01UL << SCT_INPUT_SIN0_Pos)                            /*!< SCT INPUT: SIN0 Mask                */
+#define SCT_INPUT_SIN1_Pos                                    17                                                        /*!< SCT INPUT: SIN1 Position            */
+#define SCT_INPUT_SIN1_Msk                                    (0x01UL << SCT_INPUT_SIN1_Pos)                            /*!< SCT INPUT: SIN1 Mask                */
+#define SCT_INPUT_SIN2_Pos                                    18                                                        /*!< SCT INPUT: SIN2 Position            */
+#define SCT_INPUT_SIN2_Msk                                    (0x01UL << SCT_INPUT_SIN2_Pos)                            /*!< SCT INPUT: SIN2 Mask                */
+#define SCT_INPUT_SIN3_Pos                                    19                                                        /*!< SCT INPUT: SIN3 Position            */
+#define SCT_INPUT_SIN3_Msk                                    (0x01UL << SCT_INPUT_SIN3_Pos)                            /*!< SCT INPUT: SIN3 Mask                */
+#define SCT_INPUT_SIN4_Pos                                    20                                                        /*!< SCT INPUT: SIN4 Position            */
+#define SCT_INPUT_SIN4_Msk                                    (0x01UL << SCT_INPUT_SIN4_Pos)                            /*!< SCT INPUT: SIN4 Mask                */
+#define SCT_INPUT_SIN5_Pos                                    21                                                        /*!< SCT INPUT: SIN5 Position            */
+#define SCT_INPUT_SIN5_Msk                                    (0x01UL << SCT_INPUT_SIN5_Pos)                            /*!< SCT INPUT: SIN5 Mask                */
+#define SCT_INPUT_SIN6_Pos                                    22                                                        /*!< SCT INPUT: SIN6 Position            */
+#define SCT_INPUT_SIN6_Msk                                    (0x01UL << SCT_INPUT_SIN6_Pos)                            /*!< SCT INPUT: SIN6 Mask                */
+#define SCT_INPUT_SIN7_Pos                                    23                                                        /*!< SCT INPUT: SIN7 Position            */
+#define SCT_INPUT_SIN7_Msk                                    (0x01UL << SCT_INPUT_SIN7_Pos)                            /*!< SCT INPUT: SIN7 Mask                */
+
+// ---------------------------------------  SCT_REGMODE  ------------------------------------------
+#define SCT_REGMODE_REGMOD_L0_Pos                             0                                                         /*!< SCT REGMODE: REGMOD_L0 Position     */
+#define SCT_REGMODE_REGMOD_L0_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L0_Pos)                     /*!< SCT REGMODE: REGMOD_L0 Mask         */
+#define SCT_REGMODE_REGMOD_L1_Pos                             1                                                         /*!< SCT REGMODE: REGMOD_L1 Position     */
+#define SCT_REGMODE_REGMOD_L1_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L1_Pos)                     /*!< SCT REGMODE: REGMOD_L1 Mask         */
+#define SCT_REGMODE_REGMOD_L2_Pos                             2                                                         /*!< SCT REGMODE: REGMOD_L2 Position     */
+#define SCT_REGMODE_REGMOD_L2_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L2_Pos)                     /*!< SCT REGMODE: REGMOD_L2 Mask         */
+#define SCT_REGMODE_REGMOD_L3_Pos                             3                                                         /*!< SCT REGMODE: REGMOD_L3 Position     */
+#define SCT_REGMODE_REGMOD_L3_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L3_Pos)                     /*!< SCT REGMODE: REGMOD_L3 Mask         */
+#define SCT_REGMODE_REGMOD_L4_Pos                             4                                                         /*!< SCT REGMODE: REGMOD_L4 Position     */
+#define SCT_REGMODE_REGMOD_L4_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L4_Pos)                     /*!< SCT REGMODE: REGMOD_L4 Mask         */
+#define SCT_REGMODE_REGMOD_L5_Pos                             5                                                         /*!< SCT REGMODE: REGMOD_L5 Position     */
+#define SCT_REGMODE_REGMOD_L5_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L5_Pos)                     /*!< SCT REGMODE: REGMOD_L5 Mask         */
+#define SCT_REGMODE_REGMOD_L6_Pos                             6                                                         /*!< SCT REGMODE: REGMOD_L6 Position     */
+#define SCT_REGMODE_REGMOD_L6_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L6_Pos)                     /*!< SCT REGMODE: REGMOD_L6 Mask         */
+#define SCT_REGMODE_REGMOD_L7_Pos                             7                                                         /*!< SCT REGMODE: REGMOD_L7 Position     */
+#define SCT_REGMODE_REGMOD_L7_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L7_Pos)                     /*!< SCT REGMODE: REGMOD_L7 Mask         */
+#define SCT_REGMODE_REGMOD_L8_Pos                             8                                                         /*!< SCT REGMODE: REGMOD_L8 Position     */
+#define SCT_REGMODE_REGMOD_L8_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L8_Pos)                     /*!< SCT REGMODE: REGMOD_L8 Mask         */
+#define SCT_REGMODE_REGMOD_L9_Pos                             9                                                         /*!< SCT REGMODE: REGMOD_L9 Position     */
+#define SCT_REGMODE_REGMOD_L9_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L9_Pos)                     /*!< SCT REGMODE: REGMOD_L9 Mask         */
+#define SCT_REGMODE_REGMOD_L10_Pos                            10                                                        /*!< SCT REGMODE: REGMOD_L10 Position    */
+#define SCT_REGMODE_REGMOD_L10_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L10_Pos)                    /*!< SCT REGMODE: REGMOD_L10 Mask        */
+#define SCT_REGMODE_REGMOD_L11_Pos                            11                                                        /*!< SCT REGMODE: REGMOD_L11 Position    */
+#define SCT_REGMODE_REGMOD_L11_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L11_Pos)                    /*!< SCT REGMODE: REGMOD_L11 Mask        */
+#define SCT_REGMODE_REGMOD_L12_Pos                            12                                                        /*!< SCT REGMODE: REGMOD_L12 Position    */
+#define SCT_REGMODE_REGMOD_L12_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L12_Pos)                    /*!< SCT REGMODE: REGMOD_L12 Mask        */
+#define SCT_REGMODE_REGMOD_L13_Pos                            13                                                        /*!< SCT REGMODE: REGMOD_L13 Position    */
+#define SCT_REGMODE_REGMOD_L13_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L13_Pos)                    /*!< SCT REGMODE: REGMOD_L13 Mask        */
+#define SCT_REGMODE_REGMOD_L14_Pos                            14                                                        /*!< SCT REGMODE: REGMOD_L14 Position    */
+#define SCT_REGMODE_REGMOD_L14_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L14_Pos)                    /*!< SCT REGMODE: REGMOD_L14 Mask        */
+#define SCT_REGMODE_REGMOD_L15_Pos                            15                                                        /*!< SCT REGMODE: REGMOD_L15 Position    */
+#define SCT_REGMODE_REGMOD_L15_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L15_Pos)                    /*!< SCT REGMODE: REGMOD_L15 Mask        */
+#define SCT_REGMODE_REGMOD_H16_Pos                            16                                                        /*!< SCT REGMODE: REGMOD_H16 Position    */
+#define SCT_REGMODE_REGMOD_H16_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H16_Pos)                    /*!< SCT REGMODE: REGMOD_H16 Mask        */
+#define SCT_REGMODE_REGMOD_H17_Pos                            17                                                        /*!< SCT REGMODE: REGMOD_H17 Position    */
+#define SCT_REGMODE_REGMOD_H17_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H17_Pos)                    /*!< SCT REGMODE: REGMOD_H17 Mask        */
+#define SCT_REGMODE_REGMOD_H18_Pos                            18                                                        /*!< SCT REGMODE: REGMOD_H18 Position    */
+#define SCT_REGMODE_REGMOD_H18_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H18_Pos)                    /*!< SCT REGMODE: REGMOD_H18 Mask        */
+#define SCT_REGMODE_REGMOD_H19_Pos                            19                                                        /*!< SCT REGMODE: REGMOD_H19 Position    */
+#define SCT_REGMODE_REGMOD_H19_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H19_Pos)                    /*!< SCT REGMODE: REGMOD_H19 Mask        */
+#define SCT_REGMODE_REGMOD_H20_Pos                            20                                                        /*!< SCT REGMODE: REGMOD_H20 Position    */
+#define SCT_REGMODE_REGMOD_H20_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H20_Pos)                    /*!< SCT REGMODE: REGMOD_H20 Mask        */
+#define SCT_REGMODE_REGMOD_H21_Pos                            21                                                        /*!< SCT REGMODE: REGMOD_H21 Position    */
+#define SCT_REGMODE_REGMOD_H21_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H21_Pos)                    /*!< SCT REGMODE: REGMOD_H21 Mask        */
+#define SCT_REGMODE_REGMOD_H22_Pos                            22                                                        /*!< SCT REGMODE: REGMOD_H22 Position    */
+#define SCT_REGMODE_REGMOD_H22_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H22_Pos)                    /*!< SCT REGMODE: REGMOD_H22 Mask        */
+#define SCT_REGMODE_REGMOD_H23_Pos                            23                                                        /*!< SCT REGMODE: REGMOD_H23 Position    */
+#define SCT_REGMODE_REGMOD_H23_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H23_Pos)                    /*!< SCT REGMODE: REGMOD_H23 Mask        */
+#define SCT_REGMODE_REGMOD_H24_Pos                            24                                                        /*!< SCT REGMODE: REGMOD_H24 Position    */
+#define SCT_REGMODE_REGMOD_H24_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H24_Pos)                    /*!< SCT REGMODE: REGMOD_H24 Mask        */
+#define SCT_REGMODE_REGMOD_H25_Pos                            25                                                        /*!< SCT REGMODE: REGMOD_H25 Position    */
+#define SCT_REGMODE_REGMOD_H25_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H25_Pos)                    /*!< SCT REGMODE: REGMOD_H25 Mask        */
+#define SCT_REGMODE_REGMOD_H26_Pos                            26                                                        /*!< SCT REGMODE: REGMOD_H26 Position    */
+#define SCT_REGMODE_REGMOD_H26_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H26_Pos)                    /*!< SCT REGMODE: REGMOD_H26 Mask        */
+#define SCT_REGMODE_REGMOD_H27_Pos                            27                                                        /*!< SCT REGMODE: REGMOD_H27 Position    */
+#define SCT_REGMODE_REGMOD_H27_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H27_Pos)                    /*!< SCT REGMODE: REGMOD_H27 Mask        */
+#define SCT_REGMODE_REGMOD_H28_Pos                            28                                                        /*!< SCT REGMODE: REGMOD_H28 Position    */
+#define SCT_REGMODE_REGMOD_H28_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H28_Pos)                    /*!< SCT REGMODE: REGMOD_H28 Mask        */
+#define SCT_REGMODE_REGMOD_H29_Pos                            29                                                        /*!< SCT REGMODE: REGMOD_H29 Position    */
+#define SCT_REGMODE_REGMOD_H29_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H29_Pos)                    /*!< SCT REGMODE: REGMOD_H29 Mask        */
+#define SCT_REGMODE_REGMOD_H30_Pos                            30                                                        /*!< SCT REGMODE: REGMOD_H30 Position    */
+#define SCT_REGMODE_REGMOD_H30_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H30_Pos)                    /*!< SCT REGMODE: REGMOD_H30 Mask        */
+#define SCT_REGMODE_REGMOD_H31_Pos                            31                                                        /*!< SCT REGMODE: REGMOD_H31 Position    */
+#define SCT_REGMODE_REGMOD_H31_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H31_Pos)                    /*!< SCT REGMODE: REGMOD_H31 Mask        */
+
+// ---------------------------------------  SCT_OUTPUT  -------------------------------------------
+#define SCT_OUTPUT_OUT0_Pos                                   0                                                         /*!< SCT OUTPUT: OUT0 Position           */
+#define SCT_OUTPUT_OUT0_Msk                                   (0x01UL << SCT_OUTPUT_OUT0_Pos)                           /*!< SCT OUTPUT: OUT0 Mask               */
+#define SCT_OUTPUT_OUT1_Pos                                   1                                                         /*!< SCT OUTPUT: OUT1 Position           */
+#define SCT_OUTPUT_OUT1_Msk                                   (0x01UL << SCT_OUTPUT_OUT1_Pos)                           /*!< SCT OUTPUT: OUT1 Mask               */
+#define SCT_OUTPUT_OUT2_Pos                                   2                                                         /*!< SCT OUTPUT: OUT2 Position           */
+#define SCT_OUTPUT_OUT2_Msk                                   (0x01UL << SCT_OUTPUT_OUT2_Pos)                           /*!< SCT OUTPUT: OUT2 Mask               */
+#define SCT_OUTPUT_OUT3_Pos                                   3                                                         /*!< SCT OUTPUT: OUT3 Position           */
+#define SCT_OUTPUT_OUT3_Msk                                   (0x01UL << SCT_OUTPUT_OUT3_Pos)                           /*!< SCT OUTPUT: OUT3 Mask               */
+#define SCT_OUTPUT_OUT4_Pos                                   4                                                         /*!< SCT OUTPUT: OUT4 Position           */
+#define SCT_OUTPUT_OUT4_Msk                                   (0x01UL << SCT_OUTPUT_OUT4_Pos)                           /*!< SCT OUTPUT: OUT4 Mask               */
+#define SCT_OUTPUT_OUT5_Pos                                   5                                                         /*!< SCT OUTPUT: OUT5 Position           */
+#define SCT_OUTPUT_OUT5_Msk                                   (0x01UL << SCT_OUTPUT_OUT5_Pos)                           /*!< SCT OUTPUT: OUT5 Mask               */
+#define SCT_OUTPUT_OUT6_Pos                                   6                                                         /*!< SCT OUTPUT: OUT6 Position           */
+#define SCT_OUTPUT_OUT6_Msk                                   (0x01UL << SCT_OUTPUT_OUT6_Pos)                           /*!< SCT OUTPUT: OUT6 Mask               */
+#define SCT_OUTPUT_OUT7_Pos                                   7                                                         /*!< SCT OUTPUT: OUT7 Position           */
+#define SCT_OUTPUT_OUT7_Msk                                   (0x01UL << SCT_OUTPUT_OUT7_Pos)                           /*!< SCT OUTPUT: OUT7 Mask               */
+#define SCT_OUTPUT_OUT8_Pos                                   8                                                         /*!< SCT OUTPUT: OUT8 Position           */
+#define SCT_OUTPUT_OUT8_Msk                                   (0x01UL << SCT_OUTPUT_OUT8_Pos)                           /*!< SCT OUTPUT: OUT8 Mask               */
+#define SCT_OUTPUT_OUT9_Pos                                   9                                                         /*!< SCT OUTPUT: OUT9 Position           */
+#define SCT_OUTPUT_OUT9_Msk                                   (0x01UL << SCT_OUTPUT_OUT9_Pos)                           /*!< SCT OUTPUT: OUT9 Mask               */
+#define SCT_OUTPUT_OUT10_Pos                                  10                                                        /*!< SCT OUTPUT: OUT10 Position          */
+#define SCT_OUTPUT_OUT10_Msk                                  (0x01UL << SCT_OUTPUT_OUT10_Pos)                          /*!< SCT OUTPUT: OUT10 Mask              */
+#define SCT_OUTPUT_OUT11_Pos                                  11                                                        /*!< SCT OUTPUT: OUT11 Position          */
+#define SCT_OUTPUT_OUT11_Msk                                  (0x01UL << SCT_OUTPUT_OUT11_Pos)                          /*!< SCT OUTPUT: OUT11 Mask              */
+#define SCT_OUTPUT_OUT12_Pos                                  12                                                        /*!< SCT OUTPUT: OUT12 Position          */
+#define SCT_OUTPUT_OUT12_Msk                                  (0x01UL << SCT_OUTPUT_OUT12_Pos)                          /*!< SCT OUTPUT: OUT12 Mask              */
+#define SCT_OUTPUT_OUT13_Pos                                  13                                                        /*!< SCT OUTPUT: OUT13 Position          */
+#define SCT_OUTPUT_OUT13_Msk                                  (0x01UL << SCT_OUTPUT_OUT13_Pos)                          /*!< SCT OUTPUT: OUT13 Mask              */
+#define SCT_OUTPUT_OUT14_Pos                                  14                                                        /*!< SCT OUTPUT: OUT14 Position          */
+#define SCT_OUTPUT_OUT14_Msk                                  (0x01UL << SCT_OUTPUT_OUT14_Pos)                          /*!< SCT OUTPUT: OUT14 Mask              */
+#define SCT_OUTPUT_OUT15_Pos                                  15                                                        /*!< SCT OUTPUT: OUT15 Position          */
+#define SCT_OUTPUT_OUT15_Msk                                  (0x01UL << SCT_OUTPUT_OUT15_Pos)                          /*!< SCT OUTPUT: OUT15 Mask              */
+
+// ------------------------------------  SCT_OUTPUTDIRCTRL  ---------------------------------------
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos                         0                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos                         2                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos                         4                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos                         6                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos                         8                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos                         10                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos                         12                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos                         14                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos                         16                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos                         18                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos                        20                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos                        22                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos                        24                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos                        26                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos                        28                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos                        30                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask    */
+
+// -----------------------------------------  SCT_RES  --------------------------------------------
+#define SCT_RES_O0RES_Pos                                     0                                                         /*!< SCT RES: O0RES Position             */
+#define SCT_RES_O0RES_Msk                                     (0x03UL << SCT_RES_O0RES_Pos)                             /*!< SCT RES: O0RES Mask                 */
+#define SCT_RES_O1RES_Pos                                     2                                                         /*!< SCT RES: O1RES Position             */
+#define SCT_RES_O1RES_Msk                                     (0x03UL << SCT_RES_O1RES_Pos)                             /*!< SCT RES: O1RES Mask                 */
+#define SCT_RES_O2RES_Pos                                     4                                                         /*!< SCT RES: O2RES Position             */
+#define SCT_RES_O2RES_Msk                                     (0x03UL << SCT_RES_O2RES_Pos)                             /*!< SCT RES: O2RES Mask                 */
+#define SCT_RES_O3RES_Pos                                     6                                                         /*!< SCT RES: O3RES Position             */
+#define SCT_RES_O3RES_Msk                                     (0x03UL << SCT_RES_O3RES_Pos)                             /*!< SCT RES: O3RES Mask                 */
+#define SCT_RES_O4RES_Pos                                     8                                                         /*!< SCT RES: O4RES Position             */
+#define SCT_RES_O4RES_Msk                                     (0x03UL << SCT_RES_O4RES_Pos)                             /*!< SCT RES: O4RES Mask                 */
+#define SCT_RES_O5RES_Pos                                     10                                                        /*!< SCT RES: O5RES Position             */
+#define SCT_RES_O5RES_Msk                                     (0x03UL << SCT_RES_O5RES_Pos)                             /*!< SCT RES: O5RES Mask                 */
+#define SCT_RES_O6RES_Pos                                     12                                                        /*!< SCT RES: O6RES Position             */
+#define SCT_RES_O6RES_Msk                                     (0x03UL << SCT_RES_O6RES_Pos)                             /*!< SCT RES: O6RES Mask                 */
+#define SCT_RES_O7RES_Pos                                     14                                                        /*!< SCT RES: O7RES Position             */
+#define SCT_RES_O7RES_Msk                                     (0x03UL << SCT_RES_O7RES_Pos)                             /*!< SCT RES: O7RES Mask                 */
+#define SCT_RES_O8RES_Pos                                     16                                                        /*!< SCT RES: O8RES Position             */
+#define SCT_RES_O8RES_Msk                                     (0x03UL << SCT_RES_O8RES_Pos)                             /*!< SCT RES: O8RES Mask                 */
+#define SCT_RES_O9RES_Pos                                     18                                                        /*!< SCT RES: O9RES Position             */
+#define SCT_RES_O9RES_Msk                                     (0x03UL << SCT_RES_O9RES_Pos)                             /*!< SCT RES: O9RES Mask                 */
+#define SCT_RES_O10RES_Pos                                    20                                                        /*!< SCT RES: O10RES Position            */
+#define SCT_RES_O10RES_Msk                                    (0x03UL << SCT_RES_O10RES_Pos)                            /*!< SCT RES: O10RES Mask                */
+#define SCT_RES_O11RES_Pos                                    22                                                        /*!< SCT RES: O11RES Position            */
+#define SCT_RES_O11RES_Msk                                    (0x03UL << SCT_RES_O11RES_Pos)                            /*!< SCT RES: O11RES Mask                */
+#define SCT_RES_O12RES_Pos                                    24                                                        /*!< SCT RES: O12RES Position            */
+#define SCT_RES_O12RES_Msk                                    (0x03UL << SCT_RES_O12RES_Pos)                            /*!< SCT RES: O12RES Mask                */
+#define SCT_RES_O13RES_Pos                                    26                                                        /*!< SCT RES: O13RES Position            */
+#define SCT_RES_O13RES_Msk                                    (0x03UL << SCT_RES_O13RES_Pos)                            /*!< SCT RES: O13RES Mask                */
+#define SCT_RES_O14RES_Pos                                    28                                                        /*!< SCT RES: O14RES Position            */
+#define SCT_RES_O14RES_Msk                                    (0x03UL << SCT_RES_O14RES_Pos)                            /*!< SCT RES: O14RES Mask                */
+#define SCT_RES_O15RES_Pos                                    30                                                        /*!< SCT RES: O15RES Position            */
+#define SCT_RES_O15RES_Msk                                    (0x03UL << SCT_RES_O15RES_Pos)                            /*!< SCT RES: O15RES Mask                */
+
+// ---------------------------------------  SCT_DMAREQ0  ------------------------------------------
+#define SCT_DMAREQ0_DEV_0_0_Pos                               0                                                         /*!< SCT DMAREQ0: DEV_0_0 Position       */
+#define SCT_DMAREQ0_DEV_0_0_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos)                       /*!< SCT DMAREQ0: DEV_0_0 Mask           */
+#define SCT_DMAREQ0_DEV_0_1_Pos                               1                                                         /*!< SCT DMAREQ0: DEV_0_1 Position       */
+#define SCT_DMAREQ0_DEV_0_1_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos)                       /*!< SCT DMAREQ0: DEV_0_1 Mask           */
+#define SCT_DMAREQ0_DEV_0_2_Pos                               2                                                         /*!< SCT DMAREQ0: DEV_0_2 Position       */
+#define SCT_DMAREQ0_DEV_0_2_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos)                       /*!< SCT DMAREQ0: DEV_0_2 Mask           */
+#define SCT_DMAREQ0_DEV_0_3_Pos                               3                                                         /*!< SCT DMAREQ0: DEV_0_3 Position       */
+#define SCT_DMAREQ0_DEV_0_3_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos)                       /*!< SCT DMAREQ0: DEV_0_3 Mask           */
+#define SCT_DMAREQ0_DEV_0_4_Pos                               4                                                         /*!< SCT DMAREQ0: DEV_0_4 Position       */
+#define SCT_DMAREQ0_DEV_0_4_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos)                       /*!< SCT DMAREQ0: DEV_0_4 Mask           */
+#define SCT_DMAREQ0_DEV_0_5_Pos                               5                                                         /*!< SCT DMAREQ0: DEV_0_5 Position       */
+#define SCT_DMAREQ0_DEV_0_5_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos)                       /*!< SCT DMAREQ0: DEV_0_5 Mask           */
+#define SCT_DMAREQ0_DEV_0_6_Pos                               6                                                         /*!< SCT DMAREQ0: DEV_0_6 Position       */
+#define SCT_DMAREQ0_DEV_0_6_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos)                       /*!< SCT DMAREQ0: DEV_0_6 Mask           */
+#define SCT_DMAREQ0_DEV_0_7_Pos                               7                                                         /*!< SCT DMAREQ0: DEV_0_7 Position       */
+#define SCT_DMAREQ0_DEV_0_7_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos)                       /*!< SCT DMAREQ0: DEV_0_7 Mask           */
+#define SCT_DMAREQ0_DEV_0_8_Pos                               8                                                         /*!< SCT DMAREQ0: DEV_0_8 Position       */
+#define SCT_DMAREQ0_DEV_0_8_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos)                       /*!< SCT DMAREQ0: DEV_0_8 Mask           */
+#define SCT_DMAREQ0_DEV_0_9_Pos                               9                                                         /*!< SCT DMAREQ0: DEV_0_9 Position       */
+#define SCT_DMAREQ0_DEV_0_9_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos)                       /*!< SCT DMAREQ0: DEV_0_9 Mask           */
+#define SCT_DMAREQ0_DEV_0_10_Pos                              10                                                        /*!< SCT DMAREQ0: DEV_0_10 Position      */
+#define SCT_DMAREQ0_DEV_0_10_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos)                      /*!< SCT DMAREQ0: DEV_0_10 Mask          */
+#define SCT_DMAREQ0_DEV_0_11_Pos                              11                                                        /*!< SCT DMAREQ0: DEV_0_11 Position      */
+#define SCT_DMAREQ0_DEV_0_11_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos)                      /*!< SCT DMAREQ0: DEV_0_11 Mask          */
+#define SCT_DMAREQ0_DEV_0_12_Pos                              12                                                        /*!< SCT DMAREQ0: DEV_0_12 Position      */
+#define SCT_DMAREQ0_DEV_0_12_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos)                      /*!< SCT DMAREQ0: DEV_0_12 Mask          */
+#define SCT_DMAREQ0_DEV_0_13_Pos                              13                                                        /*!< SCT DMAREQ0: DEV_0_13 Position      */
+#define SCT_DMAREQ0_DEV_0_13_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos)                      /*!< SCT DMAREQ0: DEV_0_13 Mask          */
+#define SCT_DMAREQ0_DEV_0_14_Pos                              14                                                        /*!< SCT DMAREQ0: DEV_0_14 Position      */
+#define SCT_DMAREQ0_DEV_0_14_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos)                      /*!< SCT DMAREQ0: DEV_0_14 Mask          */
+#define SCT_DMAREQ0_DEV_0_15_Pos                              15                                                        /*!< SCT DMAREQ0: DEV_0_15 Position      */
+#define SCT_DMAREQ0_DEV_0_15_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos)                      /*!< SCT DMAREQ0: DEV_0_15 Mask          */
+#define SCT_DMAREQ0_DRL0_Pos                                  30                                                        /*!< SCT DMAREQ0: DRL0 Position          */
+#define SCT_DMAREQ0_DRL0_Msk                                  (0x01UL << SCT_DMAREQ0_DRL0_Pos)                          /*!< SCT DMAREQ0: DRL0 Mask              */
+#define SCT_DMAREQ0_DRQ0_Pos                                  31                                                        /*!< SCT DMAREQ0: DRQ0 Position          */
+#define SCT_DMAREQ0_DRQ0_Msk                                  (0x01UL << SCT_DMAREQ0_DRQ0_Pos)                          /*!< SCT DMAREQ0: DRQ0 Mask              */
+
+// ---------------------------------------  SCT_DMAREQ1  ------------------------------------------
+#define SCT_DMAREQ1_DEV_1_0_Pos                               0                                                         /*!< SCT DMAREQ1: DEV_1_0 Position       */
+#define SCT_DMAREQ1_DEV_1_0_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos)                       /*!< SCT DMAREQ1: DEV_1_0 Mask           */
+#define SCT_DMAREQ1_DEV_1_1_Pos                               1                                                         /*!< SCT DMAREQ1: DEV_1_1 Position       */
+#define SCT_DMAREQ1_DEV_1_1_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos)                       /*!< SCT DMAREQ1: DEV_1_1 Mask           */
+#define SCT_DMAREQ1_DEV_1_2_Pos                               2                                                         /*!< SCT DMAREQ1: DEV_1_2 Position       */
+#define SCT_DMAREQ1_DEV_1_2_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos)                       /*!< SCT DMAREQ1: DEV_1_2 Mask           */
+#define SCT_DMAREQ1_DEV_1_3_Pos                               3                                                         /*!< SCT DMAREQ1: DEV_1_3 Position       */
+#define SCT_DMAREQ1_DEV_1_3_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos)                       /*!< SCT DMAREQ1: DEV_1_3 Mask           */
+#define SCT_DMAREQ1_DEV_1_4_Pos                               4                                                         /*!< SCT DMAREQ1: DEV_1_4 Position       */
+#define SCT_DMAREQ1_DEV_1_4_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos)                       /*!< SCT DMAREQ1: DEV_1_4 Mask           */
+#define SCT_DMAREQ1_DEV_1_5_Pos                               5                                                         /*!< SCT DMAREQ1: DEV_1_5 Position       */
+#define SCT_DMAREQ1_DEV_1_5_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos)                       /*!< SCT DMAREQ1: DEV_1_5 Mask           */
+#define SCT_DMAREQ1_DEV_1_6_Pos                               6                                                         /*!< SCT DMAREQ1: DEV_1_6 Position       */
+#define SCT_DMAREQ1_DEV_1_6_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos)                       /*!< SCT DMAREQ1: DEV_1_6 Mask           */
+#define SCT_DMAREQ1_DEV_1_7_Pos                               7                                                         /*!< SCT DMAREQ1: DEV_1_7 Position       */
+#define SCT_DMAREQ1_DEV_1_7_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos)                       /*!< SCT DMAREQ1: DEV_1_7 Mask           */
+#define SCT_DMAREQ1_DEV_1_8_Pos                               8                                                         /*!< SCT DMAREQ1: DEV_1_8 Position       */
+#define SCT_DMAREQ1_DEV_1_8_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos)                       /*!< SCT DMAREQ1: DEV_1_8 Mask           */
+#define SCT_DMAREQ1_DEV_1_9_Pos                               9                                                         /*!< SCT DMAREQ1: DEV_1_9 Position       */
+#define SCT_DMAREQ1_DEV_1_9_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos)                       /*!< SCT DMAREQ1: DEV_1_9 Mask           */
+#define SCT_DMAREQ1_DEV_1_10_Pos                              10                                                        /*!< SCT DMAREQ1: DEV_1_10 Position      */
+#define SCT_DMAREQ1_DEV_1_10_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos)                      /*!< SCT DMAREQ1: DEV_1_10 Mask          */
+#define SCT_DMAREQ1_DEV_1_11_Pos                              11                                                        /*!< SCT DMAREQ1: DEV_1_11 Position      */
+#define SCT_DMAREQ1_DEV_1_11_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos)                      /*!< SCT DMAREQ1: DEV_1_11 Mask          */
+#define SCT_DMAREQ1_DEV_1_12_Pos                              12                                                        /*!< SCT DMAREQ1: DEV_1_12 Position      */
+#define SCT_DMAREQ1_DEV_1_12_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos)                      /*!< SCT DMAREQ1: DEV_1_12 Mask          */
+#define SCT_DMAREQ1_DEV_1_13_Pos                              13                                                        /*!< SCT DMAREQ1: DEV_1_13 Position      */
+#define SCT_DMAREQ1_DEV_1_13_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos)                      /*!< SCT DMAREQ1: DEV_1_13 Mask          */
+#define SCT_DMAREQ1_DEV_1_14_Pos                              14                                                        /*!< SCT DMAREQ1: DEV_1_14 Position      */
+#define SCT_DMAREQ1_DEV_1_14_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos)                      /*!< SCT DMAREQ1: DEV_1_14 Mask          */
+#define SCT_DMAREQ1_DEV_1_15_Pos                              15                                                        /*!< SCT DMAREQ1: DEV_1_15 Position      */
+#define SCT_DMAREQ1_DEV_1_15_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos)                      /*!< SCT DMAREQ1: DEV_1_15 Mask          */
+#define SCT_DMAREQ1_DRL1_Pos                                  30                                                        /*!< SCT DMAREQ1: DRL1 Position          */
+#define SCT_DMAREQ1_DRL1_Msk                                  (0x01UL << SCT_DMAREQ1_DRL1_Pos)                          /*!< SCT DMAREQ1: DRL1 Mask              */
+#define SCT_DMAREQ1_DRQ1_Pos                                  31                                                        /*!< SCT DMAREQ1: DRQ1 Position          */
+#define SCT_DMAREQ1_DRQ1_Msk                                  (0x01UL << SCT_DMAREQ1_DRQ1_Pos)                          /*!< SCT DMAREQ1: DRQ1 Mask              */
+
+// ----------------------------------------  SCT_EVEN  --------------------------------------------
+#define SCT_EVEN_IEN0_Pos                                     0                                                         /*!< SCT EVEN: IEN0 Position             */
+#define SCT_EVEN_IEN0_Msk                                     (0x01UL << SCT_EVEN_IEN0_Pos)                             /*!< SCT EVEN: IEN0 Mask                 */
+#define SCT_EVEN_IEN1_Pos                                     1                                                         /*!< SCT EVEN: IEN1 Position             */
+#define SCT_EVEN_IEN1_Msk                                     (0x01UL << SCT_EVEN_IEN1_Pos)                             /*!< SCT EVEN: IEN1 Mask                 */
+#define SCT_EVEN_IEN2_Pos                                     2                                                         /*!< SCT EVEN: IEN2 Position             */
+#define SCT_EVEN_IEN2_Msk                                     (0x01UL << SCT_EVEN_IEN2_Pos)                             /*!< SCT EVEN: IEN2 Mask                 */
+#define SCT_EVEN_IEN3_Pos                                     3                                                         /*!< SCT EVEN: IEN3 Position             */
+#define SCT_EVEN_IEN3_Msk                                     (0x01UL << SCT_EVEN_IEN3_Pos)                             /*!< SCT EVEN: IEN3 Mask                 */
+#define SCT_EVEN_IEN4_Pos                                     4                                                         /*!< SCT EVEN: IEN4 Position             */
+#define SCT_EVEN_IEN4_Msk                                     (0x01UL << SCT_EVEN_IEN4_Pos)                             /*!< SCT EVEN: IEN4 Mask                 */
+#define SCT_EVEN_IEN5_Pos                                     5                                                         /*!< SCT EVEN: IEN5 Position             */
+#define SCT_EVEN_IEN5_Msk                                     (0x01UL << SCT_EVEN_IEN5_Pos)                             /*!< SCT EVEN: IEN5 Mask                 */
+#define SCT_EVEN_IEN6_Pos                                     6                                                         /*!< SCT EVEN: IEN6 Position             */
+#define SCT_EVEN_IEN6_Msk                                     (0x01UL << SCT_EVEN_IEN6_Pos)                             /*!< SCT EVEN: IEN6 Mask                 */
+#define SCT_EVEN_IEN7_Pos                                     7                                                         /*!< SCT EVEN: IEN7 Position             */
+#define SCT_EVEN_IEN7_Msk                                     (0x01UL << SCT_EVEN_IEN7_Pos)                             /*!< SCT EVEN: IEN7 Mask                 */
+#define SCT_EVEN_IEN8_Pos                                     8                                                         /*!< SCT EVEN: IEN8 Position             */
+#define SCT_EVEN_IEN8_Msk                                     (0x01UL << SCT_EVEN_IEN8_Pos)                             /*!< SCT EVEN: IEN8 Mask                 */
+#define SCT_EVEN_IEN9_Pos                                     9                                                         /*!< SCT EVEN: IEN9 Position             */
+#define SCT_EVEN_IEN9_Msk                                     (0x01UL << SCT_EVEN_IEN9_Pos)                             /*!< SCT EVEN: IEN9 Mask                 */
+#define SCT_EVEN_IEN10_Pos                                    10                                                        /*!< SCT EVEN: IEN10 Position            */
+#define SCT_EVEN_IEN10_Msk                                    (0x01UL << SCT_EVEN_IEN10_Pos)                            /*!< SCT EVEN: IEN10 Mask                */
+#define SCT_EVEN_IEN11_Pos                                    11                                                        /*!< SCT EVEN: IEN11 Position            */
+#define SCT_EVEN_IEN11_Msk                                    (0x01UL << SCT_EVEN_IEN11_Pos)                            /*!< SCT EVEN: IEN11 Mask                */
+#define SCT_EVEN_IEN12_Pos                                    12                                                        /*!< SCT EVEN: IEN12 Position            */
+#define SCT_EVEN_IEN12_Msk                                    (0x01UL << SCT_EVEN_IEN12_Pos)                            /*!< SCT EVEN: IEN12 Mask                */
+#define SCT_EVEN_IEN13_Pos                                    13                                                        /*!< SCT EVEN: IEN13 Position            */
+#define SCT_EVEN_IEN13_Msk                                    (0x01UL << SCT_EVEN_IEN13_Pos)                            /*!< SCT EVEN: IEN13 Mask                */
+#define SCT_EVEN_IEN14_Pos                                    14                                                        /*!< SCT EVEN: IEN14 Position            */
+#define SCT_EVEN_IEN14_Msk                                    (0x01UL << SCT_EVEN_IEN14_Pos)                            /*!< SCT EVEN: IEN14 Mask                */
+#define SCT_EVEN_IEN15_Pos                                    15                                                        /*!< SCT EVEN: IEN15 Position            */
+#define SCT_EVEN_IEN15_Msk                                    (0x01UL << SCT_EVEN_IEN15_Pos)                            /*!< SCT EVEN: IEN15 Mask                */
+
+// ---------------------------------------  SCT_EVFLAG  -------------------------------------------
+#define SCT_EVFLAG_FLAG0_Pos                                  0                                                         /*!< SCT EVFLAG: FLAG0 Position          */
+#define SCT_EVFLAG_FLAG0_Msk                                  (0x01UL << SCT_EVFLAG_FLAG0_Pos)                          /*!< SCT EVFLAG: FLAG0 Mask              */
+#define SCT_EVFLAG_FLAG1_Pos                                  1                                                         /*!< SCT EVFLAG: FLAG1 Position          */
+#define SCT_EVFLAG_FLAG1_Msk                                  (0x01UL << SCT_EVFLAG_FLAG1_Pos)                          /*!< SCT EVFLAG: FLAG1 Mask              */
+#define SCT_EVFLAG_FLAG2_Pos                                  2                                                         /*!< SCT EVFLAG: FLAG2 Position          */
+#define SCT_EVFLAG_FLAG2_Msk                                  (0x01UL << SCT_EVFLAG_FLAG2_Pos)                          /*!< SCT EVFLAG: FLAG2 Mask              */
+#define SCT_EVFLAG_FLAG3_Pos                                  3                                                         /*!< SCT EVFLAG: FLAG3 Position          */
+#define SCT_EVFLAG_FLAG3_Msk                                  (0x01UL << SCT_EVFLAG_FLAG3_Pos)                          /*!< SCT EVFLAG: FLAG3 Mask              */
+#define SCT_EVFLAG_FLAG4_Pos                                  4                                                         /*!< SCT EVFLAG: FLAG4 Position          */
+#define SCT_EVFLAG_FLAG4_Msk                                  (0x01UL << SCT_EVFLAG_FLAG4_Pos)                          /*!< SCT EVFLAG: FLAG4 Mask              */
+#define SCT_EVFLAG_FLAG5_Pos                                  5                                                         /*!< SCT EVFLAG: FLAG5 Position          */
+#define SCT_EVFLAG_FLAG5_Msk                                  (0x01UL << SCT_EVFLAG_FLAG5_Pos)                          /*!< SCT EVFLAG: FLAG5 Mask              */
+#define SCT_EVFLAG_FLAG6_Pos                                  6                                                         /*!< SCT EVFLAG: FLAG6 Position          */
+#define SCT_EVFLAG_FLAG6_Msk                                  (0x01UL << SCT_EVFLAG_FLAG6_Pos)                          /*!< SCT EVFLAG: FLAG6 Mask              */
+#define SCT_EVFLAG_FLAG7_Pos                                  7                                                         /*!< SCT EVFLAG: FLAG7 Position          */
+#define SCT_EVFLAG_FLAG7_Msk                                  (0x01UL << SCT_EVFLAG_FLAG7_Pos)                          /*!< SCT EVFLAG: FLAG7 Mask              */
+#define SCT_EVFLAG_FLAG8_Pos                                  8                                                         /*!< SCT EVFLAG: FLAG8 Position          */
+#define SCT_EVFLAG_FLAG8_Msk                                  (0x01UL << SCT_EVFLAG_FLAG8_Pos)                          /*!< SCT EVFLAG: FLAG8 Mask              */
+#define SCT_EVFLAG_FLAG9_Pos                                  9                                                         /*!< SCT EVFLAG: FLAG9 Position          */
+#define SCT_EVFLAG_FLAG9_Msk                                  (0x01UL << SCT_EVFLAG_FLAG9_Pos)                          /*!< SCT EVFLAG: FLAG9 Mask              */
+#define SCT_EVFLAG_FLAG10_Pos                                 10                                                        /*!< SCT EVFLAG: FLAG10 Position         */
+#define SCT_EVFLAG_FLAG10_Msk                                 (0x01UL << SCT_EVFLAG_FLAG10_Pos)                         /*!< SCT EVFLAG: FLAG10 Mask             */
+#define SCT_EVFLAG_FLAG11_Pos                                 11                                                        /*!< SCT EVFLAG: FLAG11 Position         */
+#define SCT_EVFLAG_FLAG11_Msk                                 (0x01UL << SCT_EVFLAG_FLAG11_Pos)                         /*!< SCT EVFLAG: FLAG11 Mask             */
+#define SCT_EVFLAG_FLAG12_Pos                                 12                                                        /*!< SCT EVFLAG: FLAG12 Position         */
+#define SCT_EVFLAG_FLAG12_Msk                                 (0x01UL << SCT_EVFLAG_FLAG12_Pos)                         /*!< SCT EVFLAG: FLAG12 Mask             */
+#define SCT_EVFLAG_FLAG13_Pos                                 13                                                        /*!< SCT EVFLAG: FLAG13 Position         */
+#define SCT_EVFLAG_FLAG13_Msk                                 (0x01UL << SCT_EVFLAG_FLAG13_Pos)                         /*!< SCT EVFLAG: FLAG13 Mask             */
+#define SCT_EVFLAG_FLAG14_Pos                                 14                                                        /*!< SCT EVFLAG: FLAG14 Position         */
+#define SCT_EVFLAG_FLAG14_Msk                                 (0x01UL << SCT_EVFLAG_FLAG14_Pos)                         /*!< SCT EVFLAG: FLAG14 Mask             */
+#define SCT_EVFLAG_FLAG15_Pos                                 15                                                        /*!< SCT EVFLAG: FLAG15 Position         */
+#define SCT_EVFLAG_FLAG15_Msk                                 (0x01UL << SCT_EVFLAG_FLAG15_Pos)                         /*!< SCT EVFLAG: FLAG15 Mask             */
+
+// ----------------------------------------  SCT_CONEN  -------------------------------------------
+#define SCT_CONEN_NCEN0_Pos                                   0                                                         /*!< SCT CONEN: NCEN0 Position           */
+#define SCT_CONEN_NCEN0_Msk                                   (0x01UL << SCT_CONEN_NCEN0_Pos)                           /*!< SCT CONEN: NCEN0 Mask               */
+#define SCT_CONEN_NCEN1_Pos                                   1                                                         /*!< SCT CONEN: NCEN1 Position           */
+#define SCT_CONEN_NCEN1_Msk                                   (0x01UL << SCT_CONEN_NCEN1_Pos)                           /*!< SCT CONEN: NCEN1 Mask               */
+#define SCT_CONEN_NCEN2_Pos                                   2                                                         /*!< SCT CONEN: NCEN2 Position           */
+#define SCT_CONEN_NCEN2_Msk                                   (0x01UL << SCT_CONEN_NCEN2_Pos)                           /*!< SCT CONEN: NCEN2 Mask               */
+#define SCT_CONEN_NCEN3_Pos                                   3                                                         /*!< SCT CONEN: NCEN3 Position           */
+#define SCT_CONEN_NCEN3_Msk                                   (0x01UL << SCT_CONEN_NCEN3_Pos)                           /*!< SCT CONEN: NCEN3 Mask               */
+#define SCT_CONEN_NCEN4_Pos                                   4                                                         /*!< SCT CONEN: NCEN4 Position           */
+#define SCT_CONEN_NCEN4_Msk                                   (0x01UL << SCT_CONEN_NCEN4_Pos)                           /*!< SCT CONEN: NCEN4 Mask               */
+#define SCT_CONEN_NCEN5_Pos                                   5                                                         /*!< SCT CONEN: NCEN5 Position           */
+#define SCT_CONEN_NCEN5_Msk                                   (0x01UL << SCT_CONEN_NCEN5_Pos)                           /*!< SCT CONEN: NCEN5 Mask               */
+#define SCT_CONEN_NCEN6_Pos                                   6                                                         /*!< SCT CONEN: NCEN6 Position           */
+#define SCT_CONEN_NCEN6_Msk                                   (0x01UL << SCT_CONEN_NCEN6_Pos)                           /*!< SCT CONEN: NCEN6 Mask               */
+#define SCT_CONEN_NCEN7_Pos                                   7                                                         /*!< SCT CONEN: NCEN7 Position           */
+#define SCT_CONEN_NCEN7_Msk                                   (0x01UL << SCT_CONEN_NCEN7_Pos)                           /*!< SCT CONEN: NCEN7 Mask               */
+#define SCT_CONEN_NCEN8_Pos                                   8                                                         /*!< SCT CONEN: NCEN8 Position           */
+#define SCT_CONEN_NCEN8_Msk                                   (0x01UL << SCT_CONEN_NCEN8_Pos)                           /*!< SCT CONEN: NCEN8 Mask               */
+#define SCT_CONEN_NCEN9_Pos                                   9                                                         /*!< SCT CONEN: NCEN9 Position           */
+#define SCT_CONEN_NCEN9_Msk                                   (0x01UL << SCT_CONEN_NCEN9_Pos)                           /*!< SCT CONEN: NCEN9 Mask               */
+#define SCT_CONEN_NCEN10_Pos                                  10                                                        /*!< SCT CONEN: NCEN10 Position          */
+#define SCT_CONEN_NCEN10_Msk                                  (0x01UL << SCT_CONEN_NCEN10_Pos)                          /*!< SCT CONEN: NCEN10 Mask              */
+#define SCT_CONEN_NCEN11_Pos                                  11                                                        /*!< SCT CONEN: NCEN11 Position          */
+#define SCT_CONEN_NCEN11_Msk                                  (0x01UL << SCT_CONEN_NCEN11_Pos)                          /*!< SCT CONEN: NCEN11 Mask              */
+#define SCT_CONEN_NCEN12_Pos                                  12                                                        /*!< SCT CONEN: NCEN12 Position          */
+#define SCT_CONEN_NCEN12_Msk                                  (0x01UL << SCT_CONEN_NCEN12_Pos)                          /*!< SCT CONEN: NCEN12 Mask              */
+#define SCT_CONEN_NCEN13_Pos                                  13                                                        /*!< SCT CONEN: NCEN13 Position          */
+#define SCT_CONEN_NCEN13_Msk                                  (0x01UL << SCT_CONEN_NCEN13_Pos)                          /*!< SCT CONEN: NCEN13 Mask              */
+#define SCT_CONEN_NCEN14_Pos                                  14                                                        /*!< SCT CONEN: NCEN14 Position          */
+#define SCT_CONEN_NCEN14_Msk                                  (0x01UL << SCT_CONEN_NCEN14_Pos)                          /*!< SCT CONEN: NCEN14 Mask              */
+#define SCT_CONEN_NCEN15_Pos                                  15                                                        /*!< SCT CONEN: NCEN15 Position          */
+#define SCT_CONEN_NCEN15_Msk                                  (0x01UL << SCT_CONEN_NCEN15_Pos)                          /*!< SCT CONEN: NCEN15 Mask              */
+
+// ---------------------------------------  SCT_CONFLAG  ------------------------------------------
+#define SCT_CONFLAG_NCFLAG0_Pos                               0                                                         /*!< SCT CONFLAG: NCFLAG0 Position       */
+#define SCT_CONFLAG_NCFLAG0_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG0_Pos)                       /*!< SCT CONFLAG: NCFLAG0 Mask           */
+#define SCT_CONFLAG_NCFLAG1_Pos                               1                                                         /*!< SCT CONFLAG: NCFLAG1 Position       */
+#define SCT_CONFLAG_NCFLAG1_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG1_Pos)                       /*!< SCT CONFLAG: NCFLAG1 Mask           */
+#define SCT_CONFLAG_NCFLAG2_Pos                               2                                                         /*!< SCT CONFLAG: NCFLAG2 Position       */
+#define SCT_CONFLAG_NCFLAG2_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG2_Pos)                       /*!< SCT CONFLAG: NCFLAG2 Mask           */
+#define SCT_CONFLAG_NCFLAG3_Pos                               3                                                         /*!< SCT CONFLAG: NCFLAG3 Position       */
+#define SCT_CONFLAG_NCFLAG3_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG3_Pos)                       /*!< SCT CONFLAG: NCFLAG3 Mask           */
+#define SCT_CONFLAG_NCFLAG4_Pos                               4                                                         /*!< SCT CONFLAG: NCFLAG4 Position       */
+#define SCT_CONFLAG_NCFLAG4_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG4_Pos)                       /*!< SCT CONFLAG: NCFLAG4 Mask           */
+#define SCT_CONFLAG_NCFLAG5_Pos                               5                                                         /*!< SCT CONFLAG: NCFLAG5 Position       */
+#define SCT_CONFLAG_NCFLAG5_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG5_Pos)                       /*!< SCT CONFLAG: NCFLAG5 Mask           */
+#define SCT_CONFLAG_NCFLAG6_Pos                               6                                                         /*!< SCT CONFLAG: NCFLAG6 Position       */
+#define SCT_CONFLAG_NCFLAG6_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG6_Pos)                       /*!< SCT CONFLAG: NCFLAG6 Mask           */
+#define SCT_CONFLAG_NCFLAG7_Pos                               7                                                         /*!< SCT CONFLAG: NCFLAG7 Position       */
+#define SCT_CONFLAG_NCFLAG7_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG7_Pos)                       /*!< SCT CONFLAG: NCFLAG7 Mask           */
+#define SCT_CONFLAG_NCFLAG8_Pos                               8                                                         /*!< SCT CONFLAG: NCFLAG8 Position       */
+#define SCT_CONFLAG_NCFLAG8_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG8_Pos)                       /*!< SCT CONFLAG: NCFLAG8 Mask           */
+#define SCT_CONFLAG_NCFLAG9_Pos                               9                                                         /*!< SCT CONFLAG: NCFLAG9 Position       */
+#define SCT_CONFLAG_NCFLAG9_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG9_Pos)                       /*!< SCT CONFLAG: NCFLAG9 Mask           */
+#define SCT_CONFLAG_NCFLAG10_Pos                              10                                                        /*!< SCT CONFLAG: NCFLAG10 Position      */
+#define SCT_CONFLAG_NCFLAG10_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG10_Pos)                      /*!< SCT CONFLAG: NCFLAG10 Mask          */
+#define SCT_CONFLAG_NCFLAG11_Pos                              11                                                        /*!< SCT CONFLAG: NCFLAG11 Position      */
+#define SCT_CONFLAG_NCFLAG11_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG11_Pos)                      /*!< SCT CONFLAG: NCFLAG11 Mask          */
+#define SCT_CONFLAG_NCFLAG12_Pos                              12                                                        /*!< SCT CONFLAG: NCFLAG12 Position      */
+#define SCT_CONFLAG_NCFLAG12_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG12_Pos)                      /*!< SCT CONFLAG: NCFLAG12 Mask          */
+#define SCT_CONFLAG_NCFLAG13_Pos                              13                                                        /*!< SCT CONFLAG: NCFLAG13 Position      */
+#define SCT_CONFLAG_NCFLAG13_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG13_Pos)                      /*!< SCT CONFLAG: NCFLAG13 Mask          */
+#define SCT_CONFLAG_NCFLAG14_Pos                              14                                                        /*!< SCT CONFLAG: NCFLAG14 Position      */
+#define SCT_CONFLAG_NCFLAG14_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG14_Pos)                      /*!< SCT CONFLAG: NCFLAG14 Mask          */
+#define SCT_CONFLAG_NCFLAG15_Pos                              15                                                        /*!< SCT CONFLAG: NCFLAG15 Position      */
+#define SCT_CONFLAG_NCFLAG15_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG15_Pos)                      /*!< SCT CONFLAG: NCFLAG15 Mask          */
+#define SCT_CONFLAG_BUSERRL_Pos                               30                                                        /*!< SCT CONFLAG: BUSERRL Position       */
+#define SCT_CONFLAG_BUSERRL_Msk                               (0x01UL << SCT_CONFLAG_BUSERRL_Pos)                       /*!< SCT CONFLAG: BUSERRL Mask           */
+#define SCT_CONFLAG_BUSERRH_Pos                               31                                                        /*!< SCT CONFLAG: BUSERRH Position       */
+#define SCT_CONFLAG_BUSERRH_Msk                               (0x01UL << SCT_CONFLAG_BUSERRH_Pos)                       /*!< SCT CONFLAG: BUSERRH Mask           */
+
+// ---------------------------------------  SCT_MATCH0  -------------------------------------------
+#define SCT_MATCH0_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH0: MATCHn_L Position       */
+#define SCT_MATCH0_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos)                 /*!< SCT MATCH0: MATCHn_L Mask           */
+#define SCT_MATCH0_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH0: MATCHn_H Position       */
+#define SCT_MATCH0_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos)                 /*!< SCT MATCH0: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP0  --------------------------------------------
+#define SCT_CAP0_CAPn_L_Pos                                   0                                                         /*!< SCT CAP0: CAPn_L Position           */
+#define SCT_CAP0_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos)                     /*!< SCT CAP0: CAPn_L Mask               */
+#define SCT_CAP0_CAPn_H_Pos                                   16                                                        /*!< SCT CAP0: CAPn_H Position           */
+#define SCT_CAP0_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos)                     /*!< SCT CAP0: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH1  -------------------------------------------
+#define SCT_MATCH1_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH1: MATCHn_L Position       */
+#define SCT_MATCH1_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos)                 /*!< SCT MATCH1: MATCHn_L Mask           */
+#define SCT_MATCH1_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH1: MATCHn_H Position       */
+#define SCT_MATCH1_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos)                 /*!< SCT MATCH1: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP1  --------------------------------------------
+#define SCT_CAP1_CAPn_L_Pos                                   0                                                         /*!< SCT CAP1: CAPn_L Position           */
+#define SCT_CAP1_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos)                     /*!< SCT CAP1: CAPn_L Mask               */
+#define SCT_CAP1_CAPn_H_Pos                                   16                                                        /*!< SCT CAP1: CAPn_H Position           */
+#define SCT_CAP1_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos)                     /*!< SCT CAP1: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH2  -------------------------------------------
+#define SCT_MATCH2_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH2: MATCHn_L Position       */
+#define SCT_MATCH2_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos)                 /*!< SCT MATCH2: MATCHn_L Mask           */
+#define SCT_MATCH2_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH2: MATCHn_H Position       */
+#define SCT_MATCH2_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos)                 /*!< SCT MATCH2: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP2  --------------------------------------------
+#define SCT_CAP2_CAPn_L_Pos                                   0                                                         /*!< SCT CAP2: CAPn_L Position           */
+#define SCT_CAP2_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos)                     /*!< SCT CAP2: CAPn_L Mask               */
+#define SCT_CAP2_CAPn_H_Pos                                   16                                                        /*!< SCT CAP2: CAPn_H Position           */
+#define SCT_CAP2_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos)                     /*!< SCT CAP2: CAPn_H Mask               */
+
+// ----------------------------------------  SCT_CAP3  --------------------------------------------
+#define SCT_CAP3_CAPn_L_Pos                                   0                                                         /*!< SCT CAP3: CAPn_L Position           */
+#define SCT_CAP3_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos)                     /*!< SCT CAP3: CAPn_L Mask               */
+#define SCT_CAP3_CAPn_H_Pos                                   16                                                        /*!< SCT CAP3: CAPn_H Position           */
+#define SCT_CAP3_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos)                     /*!< SCT CAP3: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH3  -------------------------------------------
+#define SCT_MATCH3_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH3: MATCHn_L Position       */
+#define SCT_MATCH3_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos)                 /*!< SCT MATCH3: MATCHn_L Mask           */
+#define SCT_MATCH3_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH3: MATCHn_H Position       */
+#define SCT_MATCH3_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos)                 /*!< SCT MATCH3: MATCHn_H Mask           */
+
+// ---------------------------------------  SCT_MATCH4  -------------------------------------------
+#define SCT_MATCH4_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH4: MATCHn_L Position       */
+#define SCT_MATCH4_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos)                 /*!< SCT MATCH4: MATCHn_L Mask           */
+#define SCT_MATCH4_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH4: MATCHn_H Position       */
+#define SCT_MATCH4_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos)                 /*!< SCT MATCH4: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP4  --------------------------------------------
+#define SCT_CAP4_CAPn_L_Pos                                   0                                                         /*!< SCT CAP4: CAPn_L Position           */
+#define SCT_CAP4_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos)                     /*!< SCT CAP4: CAPn_L Mask               */
+#define SCT_CAP4_CAPn_H_Pos                                   16                                                        /*!< SCT CAP4: CAPn_H Position           */
+#define SCT_CAP4_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos)                     /*!< SCT CAP4: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH5  -------------------------------------------
+#define SCT_MATCH5_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH5: MATCHn_L Position       */
+#define SCT_MATCH5_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos)                 /*!< SCT MATCH5: MATCHn_L Mask           */
+#define SCT_MATCH5_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH5: MATCHn_H Position       */
+#define SCT_MATCH5_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos)                 /*!< SCT MATCH5: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP5  --------------------------------------------
+#define SCT_CAP5_CAPn_L_Pos                                   0                                                         /*!< SCT CAP5: CAPn_L Position           */
+#define SCT_CAP5_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos)                     /*!< SCT CAP5: CAPn_L Mask               */
+#define SCT_CAP5_CAPn_H_Pos                                   16                                                        /*!< SCT CAP5: CAPn_H Position           */
+#define SCT_CAP5_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos)                     /*!< SCT CAP5: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH6  -------------------------------------------
+#define SCT_MATCH6_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH6: MATCHn_L Position       */
+#define SCT_MATCH6_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos)                 /*!< SCT MATCH6: MATCHn_L Mask           */
+#define SCT_MATCH6_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH6: MATCHn_H Position       */
+#define SCT_MATCH6_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos)                 /*!< SCT MATCH6: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP6  --------------------------------------------
+#define SCT_CAP6_CAPn_L_Pos                                   0                                                         /*!< SCT CAP6: CAPn_L Position           */
+#define SCT_CAP6_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos)                     /*!< SCT CAP6: CAPn_L Mask               */
+#define SCT_CAP6_CAPn_H_Pos                                   16                                                        /*!< SCT CAP6: CAPn_H Position           */
+#define SCT_CAP6_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos)                     /*!< SCT CAP6: CAPn_H Mask               */
+
+// ----------------------------------------  SCT_CAP7  --------------------------------------------
+#define SCT_CAP7_CAPn_L_Pos                                   0                                                         /*!< SCT CAP7: CAPn_L Position           */
+#define SCT_CAP7_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos)                     /*!< SCT CAP7: CAPn_L Mask               */
+#define SCT_CAP7_CAPn_H_Pos                                   16                                                        /*!< SCT CAP7: CAPn_H Position           */
+#define SCT_CAP7_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos)                     /*!< SCT CAP7: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH7  -------------------------------------------
+#define SCT_MATCH7_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH7: MATCHn_L Position       */
+#define SCT_MATCH7_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos)                 /*!< SCT MATCH7: MATCHn_L Mask           */
+#define SCT_MATCH7_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH7: MATCHn_H Position       */
+#define SCT_MATCH7_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos)                 /*!< SCT MATCH7: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP8  --------------------------------------------
+#define SCT_CAP8_CAPn_L_Pos                                   0                                                         /*!< SCT CAP8: CAPn_L Position           */
+#define SCT_CAP8_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos)                     /*!< SCT CAP8: CAPn_L Mask               */
+#define SCT_CAP8_CAPn_H_Pos                                   16                                                        /*!< SCT CAP8: CAPn_H Position           */
+#define SCT_CAP8_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos)                     /*!< SCT CAP8: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH8  -------------------------------------------
+#define SCT_MATCH8_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH8: MATCHn_L Position       */
+#define SCT_MATCH8_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos)                 /*!< SCT MATCH8: MATCHn_L Mask           */
+#define SCT_MATCH8_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH8: MATCHn_H Position       */
+#define SCT_MATCH8_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos)                 /*!< SCT MATCH8: MATCHn_H Mask           */
+
+// ---------------------------------------  SCT_MATCH9  -------------------------------------------
+#define SCT_MATCH9_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH9: MATCHn_L Position       */
+#define SCT_MATCH9_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos)                 /*!< SCT MATCH9: MATCHn_L Mask           */
+#define SCT_MATCH9_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH9: MATCHn_H Position       */
+#define SCT_MATCH9_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos)                 /*!< SCT MATCH9: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP9  --------------------------------------------
+#define SCT_CAP9_CAPn_L_Pos                                   0                                                         /*!< SCT CAP9: CAPn_L Position           */
+#define SCT_CAP9_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos)                     /*!< SCT CAP9: CAPn_L Mask               */
+#define SCT_CAP9_CAPn_H_Pos                                   16                                                        /*!< SCT CAP9: CAPn_H Position           */
+#define SCT_CAP9_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos)                     /*!< SCT CAP9: CAPn_H Mask               */
+
+// ----------------------------------------  SCT_CAP10  -------------------------------------------
+#define SCT_CAP10_CAPn_L_Pos                                  0                                                         /*!< SCT CAP10: CAPn_L Position          */
+#define SCT_CAP10_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos)                    /*!< SCT CAP10: CAPn_L Mask              */
+#define SCT_CAP10_CAPn_H_Pos                                  16                                                        /*!< SCT CAP10: CAPn_H Position          */
+#define SCT_CAP10_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos)                    /*!< SCT CAP10: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH10  ------------------------------------------
+#define SCT_MATCH10_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH10: MATCHn_L Position      */
+#define SCT_MATCH10_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos)                /*!< SCT MATCH10: MATCHn_L Mask          */
+#define SCT_MATCH10_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH10: MATCHn_H Position      */
+#define SCT_MATCH10_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos)                /*!< SCT MATCH10: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP11  -------------------------------------------
+#define SCT_CAP11_CAPn_L_Pos                                  0                                                         /*!< SCT CAP11: CAPn_L Position          */
+#define SCT_CAP11_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos)                    /*!< SCT CAP11: CAPn_L Mask              */
+#define SCT_CAP11_CAPn_H_Pos                                  16                                                        /*!< SCT CAP11: CAPn_H Position          */
+#define SCT_CAP11_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos)                    /*!< SCT CAP11: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH11  ------------------------------------------
+#define SCT_MATCH11_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH11: MATCHn_L Position      */
+#define SCT_MATCH11_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos)                /*!< SCT MATCH11: MATCHn_L Mask          */
+#define SCT_MATCH11_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH11: MATCHn_H Position      */
+#define SCT_MATCH11_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos)                /*!< SCT MATCH11: MATCHn_H Mask          */
+
+// ---------------------------------------  SCT_MATCH12  ------------------------------------------
+#define SCT_MATCH12_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH12: MATCHn_L Position      */
+#define SCT_MATCH12_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos)                /*!< SCT MATCH12: MATCHn_L Mask          */
+#define SCT_MATCH12_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH12: MATCHn_H Position      */
+#define SCT_MATCH12_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos)                /*!< SCT MATCH12: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP12  -------------------------------------------
+#define SCT_CAP12_CAPn_L_Pos                                  0                                                         /*!< SCT CAP12: CAPn_L Position          */
+#define SCT_CAP12_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos)                    /*!< SCT CAP12: CAPn_L Mask              */
+#define SCT_CAP12_CAPn_H_Pos                                  16                                                        /*!< SCT CAP12: CAPn_H Position          */
+#define SCT_CAP12_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos)                    /*!< SCT CAP12: CAPn_H Mask              */
+
+// ----------------------------------------  SCT_CAP13  -------------------------------------------
+#define SCT_CAP13_CAPn_L_Pos                                  0                                                         /*!< SCT CAP13: CAPn_L Position          */
+#define SCT_CAP13_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos)                    /*!< SCT CAP13: CAPn_L Mask              */
+#define SCT_CAP13_CAPn_H_Pos                                  16                                                        /*!< SCT CAP13: CAPn_H Position          */
+#define SCT_CAP13_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos)                    /*!< SCT CAP13: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH13  ------------------------------------------
+#define SCT_MATCH13_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH13: MATCHn_L Position      */
+#define SCT_MATCH13_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos)                /*!< SCT MATCH13: MATCHn_L Mask          */
+#define SCT_MATCH13_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH13: MATCHn_H Position      */
+#define SCT_MATCH13_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos)                /*!< SCT MATCH13: MATCHn_H Mask          */
+
+// ---------------------------------------  SCT_MATCH14  ------------------------------------------
+#define SCT_MATCH14_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH14: MATCHn_L Position      */
+#define SCT_MATCH14_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos)                /*!< SCT MATCH14: MATCHn_L Mask          */
+#define SCT_MATCH14_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH14: MATCHn_H Position      */
+#define SCT_MATCH14_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos)                /*!< SCT MATCH14: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP14  -------------------------------------------
+#define SCT_CAP14_CAPn_L_Pos                                  0                                                         /*!< SCT CAP14: CAPn_L Position          */
+#define SCT_CAP14_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos)                    /*!< SCT CAP14: CAPn_L Mask              */
+#define SCT_CAP14_CAPn_H_Pos                                  16                                                        /*!< SCT CAP14: CAPn_H Position          */
+#define SCT_CAP14_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos)                    /*!< SCT CAP14: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH15  ------------------------------------------
+#define SCT_MATCH15_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH15: MATCHn_L Position      */
+#define SCT_MATCH15_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos)                /*!< SCT MATCH15: MATCHn_L Mask          */
+#define SCT_MATCH15_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH15: MATCHn_H Position      */
+#define SCT_MATCH15_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos)                /*!< SCT MATCH15: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP15  -------------------------------------------
+#define SCT_CAP15_CAPn_L_Pos                                  0                                                         /*!< SCT CAP15: CAPn_L Position          */
+#define SCT_CAP15_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos)                    /*!< SCT CAP15: CAPn_L Mask              */
+#define SCT_CAP15_CAPn_H_Pos                                  16                                                        /*!< SCT CAP15: CAPn_H Position          */
+#define SCT_CAP15_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos)                    /*!< SCT CAP15: CAPn_H Mask              */
+
+// --------------------------------------  SCT_MATCHREL0  -----------------------------------------
+#define SCT_MATCHREL0_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL0: RELOADn_L Position   */
+#define SCT_MATCHREL0_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos)             /*!< SCT MATCHREL0: RELOADn_L Mask       */
+#define SCT_MATCHREL0_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL0: RELOADn_H Position   */
+#define SCT_MATCHREL0_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos)             /*!< SCT MATCHREL0: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL0  ------------------------------------------
+#define SCT_CAPCTRL0_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL0: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL0: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL0: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL0: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL0: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL0: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL0: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL0: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL0: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL0: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL0: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL0: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL0: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL0: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL0: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL0: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL0: CAPCONn_H Position    */
+#define SCT_CAPCTRL0_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos)              /*!< SCT CAPCTRL0: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL1  -----------------------------------------
+#define SCT_MATCHREL1_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL1: RELOADn_L Position   */
+#define SCT_MATCHREL1_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos)             /*!< SCT MATCHREL1: RELOADn_L Mask       */
+#define SCT_MATCHREL1_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL1: RELOADn_H Position   */
+#define SCT_MATCHREL1_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos)             /*!< SCT MATCHREL1: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL1  ------------------------------------------
+#define SCT_CAPCTRL1_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL1: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL1: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL1: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL1: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL1: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL1: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL1: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL1: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL1: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL1: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL1: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL1: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL1: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL1: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL1: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL1: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL1: CAPCONn_H Position    */
+#define SCT_CAPCTRL1_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos)              /*!< SCT CAPCTRL1: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL2  -----------------------------------------
+#define SCT_MATCHREL2_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL2: RELOADn_L Position   */
+#define SCT_MATCHREL2_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos)             /*!< SCT MATCHREL2: RELOADn_L Mask       */
+#define SCT_MATCHREL2_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL2: RELOADn_H Position   */
+#define SCT_MATCHREL2_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos)             /*!< SCT MATCHREL2: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL2  ------------------------------------------
+#define SCT_CAPCTRL2_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL2: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL2: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL2: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL2: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL2: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL2: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL2: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL2: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL2: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL2: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL2: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL2: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL2: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL2: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL2: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL2: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL2: CAPCONn_H Position    */
+#define SCT_CAPCTRL2_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos)              /*!< SCT CAPCTRL2: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL3  -----------------------------------------
+#define SCT_MATCHREL3_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL3: RELOADn_L Position   */
+#define SCT_MATCHREL3_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos)             /*!< SCT MATCHREL3: RELOADn_L Mask       */
+#define SCT_MATCHREL3_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL3: RELOADn_H Position   */
+#define SCT_MATCHREL3_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos)             /*!< SCT MATCHREL3: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL3  ------------------------------------------
+#define SCT_CAPCTRL3_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL3: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL3: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL3: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL3: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL3: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL3: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL3: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL3: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL3: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL3: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL3: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL3: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL3: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL3: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL3: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL3: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL3: CAPCONn_H Position    */
+#define SCT_CAPCTRL3_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos)              /*!< SCT CAPCTRL3: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_CAPCTRL4  ------------------------------------------
+#define SCT_CAPCTRL4_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL4: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL4: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL4: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL4: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL4: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL4: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL4: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL4: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL4: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL4: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL4: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL4: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL4: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL4: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL4: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL4: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL4: CAPCONn_H Position    */
+#define SCT_CAPCTRL4_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos)              /*!< SCT CAPCTRL4: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL4  -----------------------------------------
+#define SCT_MATCHREL4_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL4: RELOADn_L Position   */
+#define SCT_MATCHREL4_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos)             /*!< SCT MATCHREL4: RELOADn_L Mask       */
+#define SCT_MATCHREL4_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL4: RELOADn_H Position   */
+#define SCT_MATCHREL4_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos)             /*!< SCT MATCHREL4: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL5  ------------------------------------------
+#define SCT_CAPCTRL5_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL5: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL5: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL5: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL5: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL5: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL5: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL5: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL5: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL5: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL5: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL5: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL5: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL5: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL5: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL5: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL5: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL5: CAPCONn_H Position    */
+#define SCT_CAPCTRL5_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos)              /*!< SCT CAPCTRL5: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL5  -----------------------------------------
+#define SCT_MATCHREL5_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL5: RELOADn_L Position   */
+#define SCT_MATCHREL5_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos)             /*!< SCT MATCHREL5: RELOADn_L Mask       */
+#define SCT_MATCHREL5_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL5: RELOADn_H Position   */
+#define SCT_MATCHREL5_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos)             /*!< SCT MATCHREL5: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_MATCHREL6  -----------------------------------------
+#define SCT_MATCHREL6_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL6: RELOADn_L Position   */
+#define SCT_MATCHREL6_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos)             /*!< SCT MATCHREL6: RELOADn_L Mask       */
+#define SCT_MATCHREL6_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL6: RELOADn_H Position   */
+#define SCT_MATCHREL6_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos)             /*!< SCT MATCHREL6: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL6  ------------------------------------------
+#define SCT_CAPCTRL6_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL6: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL6: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL6: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL6: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL6: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL6: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL6: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL6: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL6: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL6: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL6: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL6: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL6: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL6: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL6: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL6: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL6: CAPCONn_H Position    */
+#define SCT_CAPCTRL6_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos)              /*!< SCT CAPCTRL6: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_CAPCTRL7  ------------------------------------------
+#define SCT_CAPCTRL7_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL7: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL7: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL7: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL7: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL7: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL7: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL7: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL7: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL7: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL7: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL7: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL7: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL7: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL7: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL7: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL7: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL7: CAPCONn_H Position    */
+#define SCT_CAPCTRL7_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos)              /*!< SCT CAPCTRL7: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL7  -----------------------------------------
+#define SCT_MATCHREL7_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL7: RELOADn_L Position   */
+#define SCT_MATCHREL7_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos)             /*!< SCT MATCHREL7: RELOADn_L Mask       */
+#define SCT_MATCHREL7_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL7: RELOADn_H Position   */
+#define SCT_MATCHREL7_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos)             /*!< SCT MATCHREL7: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL8  ------------------------------------------
+#define SCT_CAPCTRL8_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL8: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL8: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL8: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL8: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL8: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL8: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL8: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL8: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL8: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL8: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL8: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL8: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL8: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL8: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL8: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL8: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL8: CAPCONn_H Position    */
+#define SCT_CAPCTRL8_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos)              /*!< SCT CAPCTRL8: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL8  -----------------------------------------
+#define SCT_MATCHREL8_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL8: RELOADn_L Position   */
+#define SCT_MATCHREL8_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos)             /*!< SCT MATCHREL8: RELOADn_L Mask       */
+#define SCT_MATCHREL8_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL8: RELOADn_H Position   */
+#define SCT_MATCHREL8_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos)             /*!< SCT MATCHREL8: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_MATCHREL9  -----------------------------------------
+#define SCT_MATCHREL9_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL9: RELOADn_L Position   */
+#define SCT_MATCHREL9_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos)             /*!< SCT MATCHREL9: RELOADn_L Mask       */
+#define SCT_MATCHREL9_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL9: RELOADn_H Position   */
+#define SCT_MATCHREL9_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos)             /*!< SCT MATCHREL9: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL9  ------------------------------------------
+#define SCT_CAPCTRL9_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL9: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL9: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL9: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL9: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL9: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL9: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL9: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL9: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL9: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL9: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL9: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL9: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL9: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL9: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL9: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL9: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL9: CAPCONn_H Position    */
+#define SCT_CAPCTRL9_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos)              /*!< SCT CAPCTRL9: CAPCONn_H Mask        */
+
+// -------------------------------------  SCT_MATCHREL10  -----------------------------------------
+#define SCT_MATCHREL10_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL10: RELOADn_L Position  */
+#define SCT_MATCHREL10_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos)            /*!< SCT MATCHREL10: RELOADn_L Mask      */
+#define SCT_MATCHREL10_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL10: RELOADn_H Position  */
+#define SCT_MATCHREL10_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos)            /*!< SCT MATCHREL10: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL10  -----------------------------------------
+#define SCT_CAPCTRL10_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL10: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL10: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL10: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL10: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL10: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL10: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL10: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL10: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL10: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL10: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL10: CAPCONn_L10 Position */
+#define SCT_CAPCTRL10_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL10: CAPCONn_L11 Position */
+#define SCT_CAPCTRL10_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL10: CAPCONn_L12 Position */
+#define SCT_CAPCTRL10_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL10: CAPCONn_L13 Position */
+#define SCT_CAPCTRL10_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL10: CAPCONn_L14 Position */
+#define SCT_CAPCTRL10_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL10: CAPCONn_L15 Position */
+#define SCT_CAPCTRL10_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL10: CAPCONn_H Position   */
+#define SCT_CAPCTRL10_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos)             /*!< SCT CAPCTRL10: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL11  -----------------------------------------
+#define SCT_MATCHREL11_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL11: RELOADn_L Position  */
+#define SCT_MATCHREL11_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos)            /*!< SCT MATCHREL11: RELOADn_L Mask      */
+#define SCT_MATCHREL11_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL11: RELOADn_H Position  */
+#define SCT_MATCHREL11_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos)            /*!< SCT MATCHREL11: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL11  -----------------------------------------
+#define SCT_CAPCTRL11_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL11: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL11: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL11: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL11: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL11: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL11: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL11: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL11: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL11: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL11: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL11: CAPCONn_L10 Position */
+#define SCT_CAPCTRL11_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL11: CAPCONn_L11 Position */
+#define SCT_CAPCTRL11_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL11: CAPCONn_L12 Position */
+#define SCT_CAPCTRL11_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL11: CAPCONn_L13 Position */
+#define SCT_CAPCTRL11_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL11: CAPCONn_L14 Position */
+#define SCT_CAPCTRL11_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL11: CAPCONn_L15 Position */
+#define SCT_CAPCTRL11_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL11: CAPCONn_H Position   */
+#define SCT_CAPCTRL11_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos)             /*!< SCT CAPCTRL11: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL12  -----------------------------------------
+#define SCT_MATCHREL12_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL12: RELOADn_L Position  */
+#define SCT_MATCHREL12_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos)            /*!< SCT MATCHREL12: RELOADn_L Mask      */
+#define SCT_MATCHREL12_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL12: RELOADn_H Position  */
+#define SCT_MATCHREL12_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos)            /*!< SCT MATCHREL12: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL12  -----------------------------------------
+#define SCT_CAPCTRL12_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL12: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL12: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL12: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL12: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL12: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL12: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL12: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL12: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL12: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL12: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL12: CAPCONn_L10 Position */
+#define SCT_CAPCTRL12_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL12: CAPCONn_L11 Position */
+#define SCT_CAPCTRL12_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL12: CAPCONn_L12 Position */
+#define SCT_CAPCTRL12_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL12: CAPCONn_L13 Position */
+#define SCT_CAPCTRL12_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL12: CAPCONn_L14 Position */
+#define SCT_CAPCTRL12_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL12: CAPCONn_L15 Position */
+#define SCT_CAPCTRL12_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL12: CAPCONn_H Position   */
+#define SCT_CAPCTRL12_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos)             /*!< SCT CAPCTRL12: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL13  -----------------------------------------
+#define SCT_MATCHREL13_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL13: RELOADn_L Position  */
+#define SCT_MATCHREL13_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos)            /*!< SCT MATCHREL13: RELOADn_L Mask      */
+#define SCT_MATCHREL13_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL13: RELOADn_H Position  */
+#define SCT_MATCHREL13_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos)            /*!< SCT MATCHREL13: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL13  -----------------------------------------
+#define SCT_CAPCTRL13_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL13: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL13: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL13: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL13: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL13: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL13: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL13: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL13: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL13: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL13: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL13: CAPCONn_L10 Position */
+#define SCT_CAPCTRL13_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL13: CAPCONn_L11 Position */
+#define SCT_CAPCTRL13_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL13: CAPCONn_L12 Position */
+#define SCT_CAPCTRL13_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL13: CAPCONn_L13 Position */
+#define SCT_CAPCTRL13_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL13: CAPCONn_L14 Position */
+#define SCT_CAPCTRL13_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL13: CAPCONn_L15 Position */
+#define SCT_CAPCTRL13_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL13: CAPCONn_H Position   */
+#define SCT_CAPCTRL13_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos)             /*!< SCT CAPCTRL13: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL14  -----------------------------------------
+#define SCT_MATCHREL14_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL14: RELOADn_L Position  */
+#define SCT_MATCHREL14_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos)            /*!< SCT MATCHREL14: RELOADn_L Mask      */
+#define SCT_MATCHREL14_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL14: RELOADn_H Position  */
+#define SCT_MATCHREL14_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos)            /*!< SCT MATCHREL14: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL14  -----------------------------------------
+#define SCT_CAPCTRL14_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL14: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL14: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL14: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL14: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL14: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL14: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL14: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL14: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL14: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL14: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL14: CAPCONn_L10 Position */
+#define SCT_CAPCTRL14_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL14: CAPCONn_L11 Position */
+#define SCT_CAPCTRL14_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL14: CAPCONn_L12 Position */
+#define SCT_CAPCTRL14_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL14: CAPCONn_L13 Position */
+#define SCT_CAPCTRL14_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL14: CAPCONn_L14 Position */
+#define SCT_CAPCTRL14_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL14: CAPCONn_L15 Position */
+#define SCT_CAPCTRL14_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL14: CAPCONn_H Position   */
+#define SCT_CAPCTRL14_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos)             /*!< SCT CAPCTRL14: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL15  -----------------------------------------
+#define SCT_MATCHREL15_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL15: RELOADn_L Position  */
+#define SCT_MATCHREL15_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos)            /*!< SCT MATCHREL15: RELOADn_L Mask      */
+#define SCT_MATCHREL15_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL15: RELOADn_H Position  */
+#define SCT_MATCHREL15_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos)            /*!< SCT MATCHREL15: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL15  -----------------------------------------
+#define SCT_CAPCTRL15_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL15: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL15: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL15: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL15: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL15: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL15: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL15: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL15: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL15: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL15: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL15: CAPCONn_L10 Position */
+#define SCT_CAPCTRL15_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL15: CAPCONn_L11 Position */
+#define SCT_CAPCTRL15_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL15: CAPCONn_L12 Position */
+#define SCT_CAPCTRL15_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL15: CAPCONn_L13 Position */
+#define SCT_CAPCTRL15_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL15: CAPCONn_L14 Position */
+#define SCT_CAPCTRL15_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL15: CAPCONn_L15 Position */
+#define SCT_CAPCTRL15_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL15: CAPCONn_H Position   */
+#define SCT_CAPCTRL15_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos)             /*!< SCT CAPCTRL15: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_EVSTATEMSK0  ----------------------------------------
+#define SCT_EVSTATEMSK0_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL0  ------------------------------------------
+#define SCT_EVCTRL0_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL0: MATCHSEL Position      */
+#define SCT_EVCTRL0_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos)                      /*!< SCT EVCTRL0: MATCHSEL Mask          */
+#define SCT_EVCTRL0_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL0: HEVENT Position        */
+#define SCT_EVCTRL0_HEVENT_Msk                                (0x01UL << SCT_EVCTRL0_HEVENT_Pos)                        /*!< SCT EVCTRL0: HEVENT Mask            */
+#define SCT_EVCTRL0_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL0: OUTSEL Position        */
+#define SCT_EVCTRL0_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL0_OUTSEL_Pos)                        /*!< SCT EVCTRL0: OUTSEL Mask            */
+#define SCT_EVCTRL0_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL0: IOSEL Position         */
+#define SCT_EVCTRL0_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL0_IOSEL_Pos)                         /*!< SCT EVCTRL0: IOSEL Mask             */
+#define SCT_EVCTRL0_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL0: IOCOND Position        */
+#define SCT_EVCTRL0_IOCOND_Msk                                (0x03UL << SCT_EVCTRL0_IOCOND_Pos)                        /*!< SCT EVCTRL0: IOCOND Mask            */
+#define SCT_EVCTRL0_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL0: COMBMODE Position      */
+#define SCT_EVCTRL0_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL0_COMBMODE_Pos)                      /*!< SCT EVCTRL0: COMBMODE Mask          */
+#define SCT_EVCTRL0_STATELD_Pos                               14                                                        /*!< SCT EVCTRL0: STATELD Position       */
+#define SCT_EVCTRL0_STATELD_Msk                               (0x01UL << SCT_EVCTRL0_STATELD_Pos)                       /*!< SCT EVCTRL0: STATELD Mask           */
+#define SCT_EVCTRL0_STATEV_Pos                                15                                                        /*!< SCT EVCTRL0: STATEV Position        */
+#define SCT_EVCTRL0_STATEV_Msk                                (0x1fUL << SCT_EVCTRL0_STATEV_Pos)                        /*!< SCT EVCTRL0: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK1  ----------------------------------------
+#define SCT_EVSTATEMSK1_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL1  ------------------------------------------
+#define SCT_EVCTRL1_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL1: MATCHSEL Position      */
+#define SCT_EVCTRL1_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos)                      /*!< SCT EVCTRL1: MATCHSEL Mask          */
+#define SCT_EVCTRL1_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL1: HEVENT Position        */
+#define SCT_EVCTRL1_HEVENT_Msk                                (0x01UL << SCT_EVCTRL1_HEVENT_Pos)                        /*!< SCT EVCTRL1: HEVENT Mask            */
+#define SCT_EVCTRL1_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL1: OUTSEL Position        */
+#define SCT_EVCTRL1_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL1_OUTSEL_Pos)                        /*!< SCT EVCTRL1: OUTSEL Mask            */
+#define SCT_EVCTRL1_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL1: IOSEL Position         */
+#define SCT_EVCTRL1_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL1_IOSEL_Pos)                         /*!< SCT EVCTRL1: IOSEL Mask             */
+#define SCT_EVCTRL1_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL1: IOCOND Position        */
+#define SCT_EVCTRL1_IOCOND_Msk                                (0x03UL << SCT_EVCTRL1_IOCOND_Pos)                        /*!< SCT EVCTRL1: IOCOND Mask            */
+#define SCT_EVCTRL1_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL1: COMBMODE Position      */
+#define SCT_EVCTRL1_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL1_COMBMODE_Pos)                      /*!< SCT EVCTRL1: COMBMODE Mask          */
+#define SCT_EVCTRL1_STATELD_Pos                               14                                                        /*!< SCT EVCTRL1: STATELD Position       */
+#define SCT_EVCTRL1_STATELD_Msk                               (0x01UL << SCT_EVCTRL1_STATELD_Pos)                       /*!< SCT EVCTRL1: STATELD Mask           */
+#define SCT_EVCTRL1_STATEV_Pos                                15                                                        /*!< SCT EVCTRL1: STATEV Position        */
+#define SCT_EVCTRL1_STATEV_Msk                                (0x1fUL << SCT_EVCTRL1_STATEV_Pos)                        /*!< SCT EVCTRL1: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK2  ----------------------------------------
+#define SCT_EVSTATEMSK2_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL2  ------------------------------------------
+#define SCT_EVCTRL2_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL2: MATCHSEL Position      */
+#define SCT_EVCTRL2_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos)                      /*!< SCT EVCTRL2: MATCHSEL Mask          */
+#define SCT_EVCTRL2_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL2: HEVENT Position        */
+#define SCT_EVCTRL2_HEVENT_Msk                                (0x01UL << SCT_EVCTRL2_HEVENT_Pos)                        /*!< SCT EVCTRL2: HEVENT Mask            */
+#define SCT_EVCTRL2_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL2: OUTSEL Position        */
+#define SCT_EVCTRL2_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL2_OUTSEL_Pos)                        /*!< SCT EVCTRL2: OUTSEL Mask            */
+#define SCT_EVCTRL2_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL2: IOSEL Position         */
+#define SCT_EVCTRL2_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL2_IOSEL_Pos)                         /*!< SCT EVCTRL2: IOSEL Mask             */
+#define SCT_EVCTRL2_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL2: IOCOND Position        */
+#define SCT_EVCTRL2_IOCOND_Msk                                (0x03UL << SCT_EVCTRL2_IOCOND_Pos)                        /*!< SCT EVCTRL2: IOCOND Mask            */
+#define SCT_EVCTRL2_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL2: COMBMODE Position      */
+#define SCT_EVCTRL2_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL2_COMBMODE_Pos)                      /*!< SCT EVCTRL2: COMBMODE Mask          */
+#define SCT_EVCTRL2_STATELD_Pos                               14                                                        /*!< SCT EVCTRL2: STATELD Position       */
+#define SCT_EVCTRL2_STATELD_Msk                               (0x01UL << SCT_EVCTRL2_STATELD_Pos)                       /*!< SCT EVCTRL2: STATELD Mask           */
+#define SCT_EVCTRL2_STATEV_Pos                                15                                                        /*!< SCT EVCTRL2: STATEV Position        */
+#define SCT_EVCTRL2_STATEV_Msk                                (0x1fUL << SCT_EVCTRL2_STATEV_Pos)                        /*!< SCT EVCTRL2: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK3  ----------------------------------------
+#define SCT_EVSTATEMSK3_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL3  ------------------------------------------
+#define SCT_EVCTRL3_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL3: MATCHSEL Position      */
+#define SCT_EVCTRL3_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos)                      /*!< SCT EVCTRL3: MATCHSEL Mask          */
+#define SCT_EVCTRL3_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL3: HEVENT Position        */
+#define SCT_EVCTRL3_HEVENT_Msk                                (0x01UL << SCT_EVCTRL3_HEVENT_Pos)                        /*!< SCT EVCTRL3: HEVENT Mask            */
+#define SCT_EVCTRL3_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL3: OUTSEL Position        */
+#define SCT_EVCTRL3_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL3_OUTSEL_Pos)                        /*!< SCT EVCTRL3: OUTSEL Mask            */
+#define SCT_EVCTRL3_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL3: IOSEL Position         */
+#define SCT_EVCTRL3_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL3_IOSEL_Pos)                         /*!< SCT EVCTRL3: IOSEL Mask             */
+#define SCT_EVCTRL3_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL3: IOCOND Position        */
+#define SCT_EVCTRL3_IOCOND_Msk                                (0x03UL << SCT_EVCTRL3_IOCOND_Pos)                        /*!< SCT EVCTRL3: IOCOND Mask            */
+#define SCT_EVCTRL3_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL3: COMBMODE Position      */
+#define SCT_EVCTRL3_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL3_COMBMODE_Pos)                      /*!< SCT EVCTRL3: COMBMODE Mask          */
+#define SCT_EVCTRL3_STATELD_Pos                               14                                                        /*!< SCT EVCTRL3: STATELD Position       */
+#define SCT_EVCTRL3_STATELD_Msk                               (0x01UL << SCT_EVCTRL3_STATELD_Pos)                       /*!< SCT EVCTRL3: STATELD Mask           */
+#define SCT_EVCTRL3_STATEV_Pos                                15                                                        /*!< SCT EVCTRL3: STATEV Position        */
+#define SCT_EVCTRL3_STATEV_Msk                                (0x1fUL << SCT_EVCTRL3_STATEV_Pos)                        /*!< SCT EVCTRL3: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK4  ----------------------------------------
+#define SCT_EVSTATEMSK4_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL4  ------------------------------------------
+#define SCT_EVCTRL4_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL4: MATCHSEL Position      */
+#define SCT_EVCTRL4_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos)                      /*!< SCT EVCTRL4: MATCHSEL Mask          */
+#define SCT_EVCTRL4_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL4: HEVENT Position        */
+#define SCT_EVCTRL4_HEVENT_Msk                                (0x01UL << SCT_EVCTRL4_HEVENT_Pos)                        /*!< SCT EVCTRL4: HEVENT Mask            */
+#define SCT_EVCTRL4_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL4: OUTSEL Position        */
+#define SCT_EVCTRL4_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL4_OUTSEL_Pos)                        /*!< SCT EVCTRL4: OUTSEL Mask            */
+#define SCT_EVCTRL4_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL4: IOSEL Position         */
+#define SCT_EVCTRL4_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL4_IOSEL_Pos)                         /*!< SCT EVCTRL4: IOSEL Mask             */
+#define SCT_EVCTRL4_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL4: IOCOND Position        */
+#define SCT_EVCTRL4_IOCOND_Msk                                (0x03UL << SCT_EVCTRL4_IOCOND_Pos)                        /*!< SCT EVCTRL4: IOCOND Mask            */
+#define SCT_EVCTRL4_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL4: COMBMODE Position      */
+#define SCT_EVCTRL4_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL4_COMBMODE_Pos)                      /*!< SCT EVCTRL4: COMBMODE Mask          */
+#define SCT_EVCTRL4_STATELD_Pos                               14                                                        /*!< SCT EVCTRL4: STATELD Position       */
+#define SCT_EVCTRL4_STATELD_Msk                               (0x01UL << SCT_EVCTRL4_STATELD_Pos)                       /*!< SCT EVCTRL4: STATELD Mask           */
+#define SCT_EVCTRL4_STATEV_Pos                                15                                                        /*!< SCT EVCTRL4: STATEV Position        */
+#define SCT_EVCTRL4_STATEV_Msk                                (0x1fUL << SCT_EVCTRL4_STATEV_Pos)                        /*!< SCT EVCTRL4: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK5  ----------------------------------------
+#define SCT_EVSTATEMSK5_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL5  ------------------------------------------
+#define SCT_EVCTRL5_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL5: MATCHSEL Position      */
+#define SCT_EVCTRL5_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos)                      /*!< SCT EVCTRL5: MATCHSEL Mask          */
+#define SCT_EVCTRL5_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL5: HEVENT Position        */
+#define SCT_EVCTRL5_HEVENT_Msk                                (0x01UL << SCT_EVCTRL5_HEVENT_Pos)                        /*!< SCT EVCTRL5: HEVENT Mask            */
+#define SCT_EVCTRL5_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL5: OUTSEL Position        */
+#define SCT_EVCTRL5_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL5_OUTSEL_Pos)                        /*!< SCT EVCTRL5: OUTSEL Mask            */
+#define SCT_EVCTRL5_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL5: IOSEL Position         */
+#define SCT_EVCTRL5_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL5_IOSEL_Pos)                         /*!< SCT EVCTRL5: IOSEL Mask             */
+#define SCT_EVCTRL5_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL5: IOCOND Position        */
+#define SCT_EVCTRL5_IOCOND_Msk                                (0x03UL << SCT_EVCTRL5_IOCOND_Pos)                        /*!< SCT EVCTRL5: IOCOND Mask            */
+#define SCT_EVCTRL5_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL5: COMBMODE Position      */
+#define SCT_EVCTRL5_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL5_COMBMODE_Pos)                      /*!< SCT EVCTRL5: COMBMODE Mask          */
+#define SCT_EVCTRL5_STATELD_Pos                               14                                                        /*!< SCT EVCTRL5: STATELD Position       */
+#define SCT_EVCTRL5_STATELD_Msk                               (0x01UL << SCT_EVCTRL5_STATELD_Pos)                       /*!< SCT EVCTRL5: STATELD Mask           */
+#define SCT_EVCTRL5_STATEV_Pos                                15                                                        /*!< SCT EVCTRL5: STATEV Position        */
+#define SCT_EVCTRL5_STATEV_Msk                                (0x1fUL << SCT_EVCTRL5_STATEV_Pos)                        /*!< SCT EVCTRL5: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK6  ----------------------------------------
+#define SCT_EVSTATEMSK6_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL6  ------------------------------------------
+#define SCT_EVCTRL6_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL6: MATCHSEL Position      */
+#define SCT_EVCTRL6_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos)                      /*!< SCT EVCTRL6: MATCHSEL Mask          */
+#define SCT_EVCTRL6_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL6: HEVENT Position        */
+#define SCT_EVCTRL6_HEVENT_Msk                                (0x01UL << SCT_EVCTRL6_HEVENT_Pos)                        /*!< SCT EVCTRL6: HEVENT Mask            */
+#define SCT_EVCTRL6_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL6: OUTSEL Position        */
+#define SCT_EVCTRL6_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL6_OUTSEL_Pos)                        /*!< SCT EVCTRL6: OUTSEL Mask            */
+#define SCT_EVCTRL6_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL6: IOSEL Position         */
+#define SCT_EVCTRL6_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL6_IOSEL_Pos)                         /*!< SCT EVCTRL6: IOSEL Mask             */
+#define SCT_EVCTRL6_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL6: IOCOND Position        */
+#define SCT_EVCTRL6_IOCOND_Msk                                (0x03UL << SCT_EVCTRL6_IOCOND_Pos)                        /*!< SCT EVCTRL6: IOCOND Mask            */
+#define SCT_EVCTRL6_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL6: COMBMODE Position      */
+#define SCT_EVCTRL6_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL6_COMBMODE_Pos)                      /*!< SCT EVCTRL6: COMBMODE Mask          */
+#define SCT_EVCTRL6_STATELD_Pos                               14                                                        /*!< SCT EVCTRL6: STATELD Position       */
+#define SCT_EVCTRL6_STATELD_Msk                               (0x01UL << SCT_EVCTRL6_STATELD_Pos)                       /*!< SCT EVCTRL6: STATELD Mask           */
+#define SCT_EVCTRL6_STATEV_Pos                                15                                                        /*!< SCT EVCTRL6: STATEV Position        */
+#define SCT_EVCTRL6_STATEV_Msk                                (0x1fUL << SCT_EVCTRL6_STATEV_Pos)                        /*!< SCT EVCTRL6: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK7  ----------------------------------------
+#define SCT_EVSTATEMSK7_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL7  ------------------------------------------
+#define SCT_EVCTRL7_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL7: MATCHSEL Position      */
+#define SCT_EVCTRL7_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos)                      /*!< SCT EVCTRL7: MATCHSEL Mask          */
+#define SCT_EVCTRL7_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL7: HEVENT Position        */
+#define SCT_EVCTRL7_HEVENT_Msk                                (0x01UL << SCT_EVCTRL7_HEVENT_Pos)                        /*!< SCT EVCTRL7: HEVENT Mask            */
+#define SCT_EVCTRL7_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL7: OUTSEL Position        */
+#define SCT_EVCTRL7_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL7_OUTSEL_Pos)                        /*!< SCT EVCTRL7: OUTSEL Mask            */
+#define SCT_EVCTRL7_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL7: IOSEL Position         */
+#define SCT_EVCTRL7_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL7_IOSEL_Pos)                         /*!< SCT EVCTRL7: IOSEL Mask             */
+#define SCT_EVCTRL7_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL7: IOCOND Position        */
+#define SCT_EVCTRL7_IOCOND_Msk                                (0x03UL << SCT_EVCTRL7_IOCOND_Pos)                        /*!< SCT EVCTRL7: IOCOND Mask            */
+#define SCT_EVCTRL7_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL7: COMBMODE Position      */
+#define SCT_EVCTRL7_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL7_COMBMODE_Pos)                      /*!< SCT EVCTRL7: COMBMODE Mask          */
+#define SCT_EVCTRL7_STATELD_Pos                               14                                                        /*!< SCT EVCTRL7: STATELD Position       */
+#define SCT_EVCTRL7_STATELD_Msk                               (0x01UL << SCT_EVCTRL7_STATELD_Pos)                       /*!< SCT EVCTRL7: STATELD Mask           */
+#define SCT_EVCTRL7_STATEV_Pos                                15                                                        /*!< SCT EVCTRL7: STATEV Position        */
+#define SCT_EVCTRL7_STATEV_Msk                                (0x1fUL << SCT_EVCTRL7_STATEV_Pos)                        /*!< SCT EVCTRL7: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK8  ----------------------------------------
+#define SCT_EVSTATEMSK8_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL8  ------------------------------------------
+#define SCT_EVCTRL8_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL8: MATCHSEL Position      */
+#define SCT_EVCTRL8_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos)                      /*!< SCT EVCTRL8: MATCHSEL Mask          */
+#define SCT_EVCTRL8_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL8: HEVENT Position        */
+#define SCT_EVCTRL8_HEVENT_Msk                                (0x01UL << SCT_EVCTRL8_HEVENT_Pos)                        /*!< SCT EVCTRL8: HEVENT Mask            */
+#define SCT_EVCTRL8_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL8: OUTSEL Position        */
+#define SCT_EVCTRL8_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL8_OUTSEL_Pos)                        /*!< SCT EVCTRL8: OUTSEL Mask            */
+#define SCT_EVCTRL8_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL8: IOSEL Position         */
+#define SCT_EVCTRL8_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL8_IOSEL_Pos)                         /*!< SCT EVCTRL8: IOSEL Mask             */
+#define SCT_EVCTRL8_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL8: IOCOND Position        */
+#define SCT_EVCTRL8_IOCOND_Msk                                (0x03UL << SCT_EVCTRL8_IOCOND_Pos)                        /*!< SCT EVCTRL8: IOCOND Mask            */
+#define SCT_EVCTRL8_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL8: COMBMODE Position      */
+#define SCT_EVCTRL8_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL8_COMBMODE_Pos)                      /*!< SCT EVCTRL8: COMBMODE Mask          */
+#define SCT_EVCTRL8_STATELD_Pos                               14                                                        /*!< SCT EVCTRL8: STATELD Position       */
+#define SCT_EVCTRL8_STATELD_Msk                               (0x01UL << SCT_EVCTRL8_STATELD_Pos)                       /*!< SCT EVCTRL8: STATELD Mask           */
+#define SCT_EVCTRL8_STATEV_Pos                                15                                                        /*!< SCT EVCTRL8: STATEV Position        */
+#define SCT_EVCTRL8_STATEV_Msk                                (0x1fUL << SCT_EVCTRL8_STATEV_Pos)                        /*!< SCT EVCTRL8: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK9  ----------------------------------------
+#define SCT_EVSTATEMSK9_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL9  ------------------------------------------
+#define SCT_EVCTRL9_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL9: MATCHSEL Position      */
+#define SCT_EVCTRL9_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos)                      /*!< SCT EVCTRL9: MATCHSEL Mask          */
+#define SCT_EVCTRL9_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL9: HEVENT Position        */
+#define SCT_EVCTRL9_HEVENT_Msk                                (0x01UL << SCT_EVCTRL9_HEVENT_Pos)                        /*!< SCT EVCTRL9: HEVENT Mask            */
+#define SCT_EVCTRL9_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL9: OUTSEL Position        */
+#define SCT_EVCTRL9_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL9_OUTSEL_Pos)                        /*!< SCT EVCTRL9: OUTSEL Mask            */
+#define SCT_EVCTRL9_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL9: IOSEL Position         */
+#define SCT_EVCTRL9_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL9_IOSEL_Pos)                         /*!< SCT EVCTRL9: IOSEL Mask             */
+#define SCT_EVCTRL9_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL9: IOCOND Position        */
+#define SCT_EVCTRL9_IOCOND_Msk                                (0x03UL << SCT_EVCTRL9_IOCOND_Pos)                        /*!< SCT EVCTRL9: IOCOND Mask            */
+#define SCT_EVCTRL9_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL9: COMBMODE Position      */
+#define SCT_EVCTRL9_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL9_COMBMODE_Pos)                      /*!< SCT EVCTRL9: COMBMODE Mask          */
+#define SCT_EVCTRL9_STATELD_Pos                               14                                                        /*!< SCT EVCTRL9: STATELD Position       */
+#define SCT_EVCTRL9_STATELD_Msk                               (0x01UL << SCT_EVCTRL9_STATELD_Pos)                       /*!< SCT EVCTRL9: STATELD Mask           */
+#define SCT_EVCTRL9_STATEV_Pos                                15                                                        /*!< SCT EVCTRL9: STATEV Position        */
+#define SCT_EVCTRL9_STATEV_Msk                                (0x1fUL << SCT_EVCTRL9_STATEV_Pos)                        /*!< SCT EVCTRL9: STATEV Mask            */
+
+// ------------------------------------  SCT_EVSTATEMSK10  ----------------------------------------
+#define SCT_EVSTATEMSK10_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL10  ------------------------------------------
+#define SCT_EVCTRL10_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL10: MATCHSEL Position     */
+#define SCT_EVCTRL10_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos)                     /*!< SCT EVCTRL10: MATCHSEL Mask         */
+#define SCT_EVCTRL10_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL10: HEVENT Position       */
+#define SCT_EVCTRL10_HEVENT_Msk                               (0x01UL << SCT_EVCTRL10_HEVENT_Pos)                       /*!< SCT EVCTRL10: HEVENT Mask           */
+#define SCT_EVCTRL10_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL10: OUTSEL Position       */
+#define SCT_EVCTRL10_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL10_OUTSEL_Pos)                       /*!< SCT EVCTRL10: OUTSEL Mask           */
+#define SCT_EVCTRL10_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL10: IOSEL Position        */
+#define SCT_EVCTRL10_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL10_IOSEL_Pos)                        /*!< SCT EVCTRL10: IOSEL Mask            */
+#define SCT_EVCTRL10_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL10: IOCOND Position       */
+#define SCT_EVCTRL10_IOCOND_Msk                               (0x03UL << SCT_EVCTRL10_IOCOND_Pos)                       /*!< SCT EVCTRL10: IOCOND Mask           */
+#define SCT_EVCTRL10_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL10: COMBMODE Position     */
+#define SCT_EVCTRL10_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL10_COMBMODE_Pos)                     /*!< SCT EVCTRL10: COMBMODE Mask         */
+#define SCT_EVCTRL10_STATELD_Pos                              14                                                        /*!< SCT EVCTRL10: STATELD Position      */
+#define SCT_EVCTRL10_STATELD_Msk                              (0x01UL << SCT_EVCTRL10_STATELD_Pos)                      /*!< SCT EVCTRL10: STATELD Mask          */
+#define SCT_EVCTRL10_STATEV_Pos                               15                                                        /*!< SCT EVCTRL10: STATEV Position       */
+#define SCT_EVCTRL10_STATEV_Msk                               (0x1fUL << SCT_EVCTRL10_STATEV_Pos)                       /*!< SCT EVCTRL10: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK11  ----------------------------------------
+#define SCT_EVSTATEMSK11_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL11  ------------------------------------------
+#define SCT_EVCTRL11_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL11: MATCHSEL Position     */
+#define SCT_EVCTRL11_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos)                     /*!< SCT EVCTRL11: MATCHSEL Mask         */
+#define SCT_EVCTRL11_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL11: HEVENT Position       */
+#define SCT_EVCTRL11_HEVENT_Msk                               (0x01UL << SCT_EVCTRL11_HEVENT_Pos)                       /*!< SCT EVCTRL11: HEVENT Mask           */
+#define SCT_EVCTRL11_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL11: OUTSEL Position       */
+#define SCT_EVCTRL11_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL11_OUTSEL_Pos)                       /*!< SCT EVCTRL11: OUTSEL Mask           */
+#define SCT_EVCTRL11_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL11: IOSEL Position        */
+#define SCT_EVCTRL11_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL11_IOSEL_Pos)                        /*!< SCT EVCTRL11: IOSEL Mask            */
+#define SCT_EVCTRL11_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL11: IOCOND Position       */
+#define SCT_EVCTRL11_IOCOND_Msk                               (0x03UL << SCT_EVCTRL11_IOCOND_Pos)                       /*!< SCT EVCTRL11: IOCOND Mask           */
+#define SCT_EVCTRL11_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL11: COMBMODE Position     */
+#define SCT_EVCTRL11_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL11_COMBMODE_Pos)                     /*!< SCT EVCTRL11: COMBMODE Mask         */
+#define SCT_EVCTRL11_STATELD_Pos                              14                                                        /*!< SCT EVCTRL11: STATELD Position      */
+#define SCT_EVCTRL11_STATELD_Msk                              (0x01UL << SCT_EVCTRL11_STATELD_Pos)                      /*!< SCT EVCTRL11: STATELD Mask          */
+#define SCT_EVCTRL11_STATEV_Pos                               15                                                        /*!< SCT EVCTRL11: STATEV Position       */
+#define SCT_EVCTRL11_STATEV_Msk                               (0x1fUL << SCT_EVCTRL11_STATEV_Pos)                       /*!< SCT EVCTRL11: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK12  ----------------------------------------
+#define SCT_EVSTATEMSK12_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL12  ------------------------------------------
+#define SCT_EVCTRL12_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL12: MATCHSEL Position     */
+#define SCT_EVCTRL12_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos)                     /*!< SCT EVCTRL12: MATCHSEL Mask         */
+#define SCT_EVCTRL12_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL12: HEVENT Position       */
+#define SCT_EVCTRL12_HEVENT_Msk                               (0x01UL << SCT_EVCTRL12_HEVENT_Pos)                       /*!< SCT EVCTRL12: HEVENT Mask           */
+#define SCT_EVCTRL12_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL12: OUTSEL Position       */
+#define SCT_EVCTRL12_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL12_OUTSEL_Pos)                       /*!< SCT EVCTRL12: OUTSEL Mask           */
+#define SCT_EVCTRL12_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL12: IOSEL Position        */
+#define SCT_EVCTRL12_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL12_IOSEL_Pos)                        /*!< SCT EVCTRL12: IOSEL Mask            */
+#define SCT_EVCTRL12_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL12: IOCOND Position       */
+#define SCT_EVCTRL12_IOCOND_Msk                               (0x03UL << SCT_EVCTRL12_IOCOND_Pos)                       /*!< SCT EVCTRL12: IOCOND Mask           */
+#define SCT_EVCTRL12_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL12: COMBMODE Position     */
+#define SCT_EVCTRL12_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL12_COMBMODE_Pos)                     /*!< SCT EVCTRL12: COMBMODE Mask         */
+#define SCT_EVCTRL12_STATELD_Pos                              14                                                        /*!< SCT EVCTRL12: STATELD Position      */
+#define SCT_EVCTRL12_STATELD_Msk                              (0x01UL << SCT_EVCTRL12_STATELD_Pos)                      /*!< SCT EVCTRL12: STATELD Mask          */
+#define SCT_EVCTRL12_STATEV_Pos                               15                                                        /*!< SCT EVCTRL12: STATEV Position       */
+#define SCT_EVCTRL12_STATEV_Msk                               (0x1fUL << SCT_EVCTRL12_STATEV_Pos)                       /*!< SCT EVCTRL12: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK13  ----------------------------------------
+#define SCT_EVSTATEMSK13_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL13  ------------------------------------------
+#define SCT_EVCTRL13_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL13: MATCHSEL Position     */
+#define SCT_EVCTRL13_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos)                     /*!< SCT EVCTRL13: MATCHSEL Mask         */
+#define SCT_EVCTRL13_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL13: HEVENT Position       */
+#define SCT_EVCTRL13_HEVENT_Msk                               (0x01UL << SCT_EVCTRL13_HEVENT_Pos)                       /*!< SCT EVCTRL13: HEVENT Mask           */
+#define SCT_EVCTRL13_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL13: OUTSEL Position       */
+#define SCT_EVCTRL13_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL13_OUTSEL_Pos)                       /*!< SCT EVCTRL13: OUTSEL Mask           */
+#define SCT_EVCTRL13_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL13: IOSEL Position        */
+#define SCT_EVCTRL13_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL13_IOSEL_Pos)                        /*!< SCT EVCTRL13: IOSEL Mask            */
+#define SCT_EVCTRL13_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL13: IOCOND Position       */
+#define SCT_EVCTRL13_IOCOND_Msk                               (0x03UL << SCT_EVCTRL13_IOCOND_Pos)                       /*!< SCT EVCTRL13: IOCOND Mask           */
+#define SCT_EVCTRL13_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL13: COMBMODE Position     */
+#define SCT_EVCTRL13_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL13_COMBMODE_Pos)                     /*!< SCT EVCTRL13: COMBMODE Mask         */
+#define SCT_EVCTRL13_STATELD_Pos                              14                                                        /*!< SCT EVCTRL13: STATELD Position      */
+#define SCT_EVCTRL13_STATELD_Msk                              (0x01UL << SCT_EVCTRL13_STATELD_Pos)                      /*!< SCT EVCTRL13: STATELD Mask          */
+#define SCT_EVCTRL13_STATEV_Pos                               15                                                        /*!< SCT EVCTRL13: STATEV Position       */
+#define SCT_EVCTRL13_STATEV_Msk                               (0x1fUL << SCT_EVCTRL13_STATEV_Pos)                       /*!< SCT EVCTRL13: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK14  ----------------------------------------
+#define SCT_EVSTATEMSK14_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL14  ------------------------------------------
+#define SCT_EVCTRL14_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL14: MATCHSEL Position     */
+#define SCT_EVCTRL14_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos)                     /*!< SCT EVCTRL14: MATCHSEL Mask         */
+#define SCT_EVCTRL14_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL14: HEVENT Position       */
+#define SCT_EVCTRL14_HEVENT_Msk                               (0x01UL << SCT_EVCTRL14_HEVENT_Pos)                       /*!< SCT EVCTRL14: HEVENT Mask           */
+#define SCT_EVCTRL14_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL14: OUTSEL Position       */
+#define SCT_EVCTRL14_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL14_OUTSEL_Pos)                       /*!< SCT EVCTRL14: OUTSEL Mask           */
+#define SCT_EVCTRL14_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL14: IOSEL Position        */
+#define SCT_EVCTRL14_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL14_IOSEL_Pos)                        /*!< SCT EVCTRL14: IOSEL Mask            */
+#define SCT_EVCTRL14_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL14: IOCOND Position       */
+#define SCT_EVCTRL14_IOCOND_Msk                               (0x03UL << SCT_EVCTRL14_IOCOND_Pos)                       /*!< SCT EVCTRL14: IOCOND Mask           */
+#define SCT_EVCTRL14_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL14: COMBMODE Position     */
+#define SCT_EVCTRL14_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL14_COMBMODE_Pos)                     /*!< SCT EVCTRL14: COMBMODE Mask         */
+#define SCT_EVCTRL14_STATELD_Pos                              14                                                        /*!< SCT EVCTRL14: STATELD Position      */
+#define SCT_EVCTRL14_STATELD_Msk                              (0x01UL << SCT_EVCTRL14_STATELD_Pos)                      /*!< SCT EVCTRL14: STATELD Mask          */
+#define SCT_EVCTRL14_STATEV_Pos                               15                                                        /*!< SCT EVCTRL14: STATEV Position       */
+#define SCT_EVCTRL14_STATEV_Msk                               (0x1fUL << SCT_EVCTRL14_STATEV_Pos)                       /*!< SCT EVCTRL14: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK15  ----------------------------------------
+#define SCT_EVSTATEMSK15_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL15  ------------------------------------------
+#define SCT_EVCTRL15_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL15: MATCHSEL Position     */
+#define SCT_EVCTRL15_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos)                     /*!< SCT EVCTRL15: MATCHSEL Mask         */
+#define SCT_EVCTRL15_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL15: HEVENT Position       */
+#define SCT_EVCTRL15_HEVENT_Msk                               (0x01UL << SCT_EVCTRL15_HEVENT_Pos)                       /*!< SCT EVCTRL15: HEVENT Mask           */
+#define SCT_EVCTRL15_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL15: OUTSEL Position       */
+#define SCT_EVCTRL15_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL15_OUTSEL_Pos)                       /*!< SCT EVCTRL15: OUTSEL Mask           */
+#define SCT_EVCTRL15_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL15: IOSEL Position        */
+#define SCT_EVCTRL15_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL15_IOSEL_Pos)                        /*!< SCT EVCTRL15: IOSEL Mask            */
+#define SCT_EVCTRL15_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL15: IOCOND Position       */
+#define SCT_EVCTRL15_IOCOND_Msk                               (0x03UL << SCT_EVCTRL15_IOCOND_Pos)                       /*!< SCT EVCTRL15: IOCOND Mask           */
+#define SCT_EVCTRL15_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL15: COMBMODE Position     */
+#define SCT_EVCTRL15_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL15_COMBMODE_Pos)                     /*!< SCT EVCTRL15: COMBMODE Mask         */
+#define SCT_EVCTRL15_STATELD_Pos                              14                                                        /*!< SCT EVCTRL15: STATELD Position      */
+#define SCT_EVCTRL15_STATELD_Msk                              (0x01UL << SCT_EVCTRL15_STATELD_Pos)                      /*!< SCT EVCTRL15: STATELD Mask          */
+#define SCT_EVCTRL15_STATEV_Pos                               15                                                        /*!< SCT EVCTRL15: STATEV Position       */
+#define SCT_EVCTRL15_STATEV_Msk                               (0x1fUL << SCT_EVCTRL15_STATEV_Pos)                       /*!< SCT EVCTRL15: STATEV Mask           */
+
+// -------------------------------------  SCT_OUTPUTSET0  -----------------------------------------
+#define SCT_OUTPUTSET0_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET0: SETn0 Position      */
+#define SCT_OUTPUTSET0_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn0_Pos)                      /*!< SCT OUTPUTSET0: SETn0 Mask          */
+#define SCT_OUTPUTSET0_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET0: SETn1 Position      */
+#define SCT_OUTPUTSET0_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn1_Pos)                      /*!< SCT OUTPUTSET0: SETn1 Mask          */
+#define SCT_OUTPUTSET0_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET0: SETn2 Position      */
+#define SCT_OUTPUTSET0_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn2_Pos)                      /*!< SCT OUTPUTSET0: SETn2 Mask          */
+#define SCT_OUTPUTSET0_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET0: SETn3 Position      */
+#define SCT_OUTPUTSET0_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn3_Pos)                      /*!< SCT OUTPUTSET0: SETn3 Mask          */
+#define SCT_OUTPUTSET0_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET0: SETn4 Position      */
+#define SCT_OUTPUTSET0_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn4_Pos)                      /*!< SCT OUTPUTSET0: SETn4 Mask          */
+#define SCT_OUTPUTSET0_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET0: SETn5 Position      */
+#define SCT_OUTPUTSET0_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn5_Pos)                      /*!< SCT OUTPUTSET0: SETn5 Mask          */
+#define SCT_OUTPUTSET0_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET0: SETn6 Position      */
+#define SCT_OUTPUTSET0_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn6_Pos)                      /*!< SCT OUTPUTSET0: SETn6 Mask          */
+#define SCT_OUTPUTSET0_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET0: SETn7 Position      */
+#define SCT_OUTPUTSET0_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn7_Pos)                      /*!< SCT OUTPUTSET0: SETn7 Mask          */
+#define SCT_OUTPUTSET0_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET0: SETn8 Position      */
+#define SCT_OUTPUTSET0_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn8_Pos)                      /*!< SCT OUTPUTSET0: SETn8 Mask          */
+#define SCT_OUTPUTSET0_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET0: SETn9 Position      */
+#define SCT_OUTPUTSET0_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn9_Pos)                      /*!< SCT OUTPUTSET0: SETn9 Mask          */
+#define SCT_OUTPUTSET0_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET0: SETn10 Position     */
+#define SCT_OUTPUTSET0_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn10_Pos)                     /*!< SCT OUTPUTSET0: SETn10 Mask         */
+#define SCT_OUTPUTSET0_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET0: SETn11 Position     */
+#define SCT_OUTPUTSET0_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn11_Pos)                     /*!< SCT OUTPUTSET0: SETn11 Mask         */
+#define SCT_OUTPUTSET0_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET0: SETn12 Position     */
+#define SCT_OUTPUTSET0_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn12_Pos)                     /*!< SCT OUTPUTSET0: SETn12 Mask         */
+#define SCT_OUTPUTSET0_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET0: SETn13 Position     */
+#define SCT_OUTPUTSET0_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn13_Pos)                     /*!< SCT OUTPUTSET0: SETn13 Mask         */
+#define SCT_OUTPUTSET0_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET0: SETn14 Position     */
+#define SCT_OUTPUTSET0_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn14_Pos)                     /*!< SCT OUTPUTSET0: SETn14 Mask         */
+#define SCT_OUTPUTSET0_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET0: SETn15 Position     */
+#define SCT_OUTPUTSET0_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn15_Pos)                     /*!< SCT OUTPUTSET0: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR0  -----------------------------------------
+#define SCT_OUTPUTCLR0_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR0: CLRn0 Position      */
+#define SCT_OUTPUTCLR0_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos)                      /*!< SCT OUTPUTCLR0: CLRn0 Mask          */
+#define SCT_OUTPUTCLR0_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR0: CLRn1 Position      */
+#define SCT_OUTPUTCLR0_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos)                      /*!< SCT OUTPUTCLR0: CLRn1 Mask          */
+#define SCT_OUTPUTCLR0_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR0: CLRn2 Position      */
+#define SCT_OUTPUTCLR0_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos)                      /*!< SCT OUTPUTCLR0: CLRn2 Mask          */
+#define SCT_OUTPUTCLR0_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR0: CLRn3 Position      */
+#define SCT_OUTPUTCLR0_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos)                      /*!< SCT OUTPUTCLR0: CLRn3 Mask          */
+#define SCT_OUTPUTCLR0_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR0: CLRn4 Position      */
+#define SCT_OUTPUTCLR0_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos)                      /*!< SCT OUTPUTCLR0: CLRn4 Mask          */
+#define SCT_OUTPUTCLR0_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR0: CLRn5 Position      */
+#define SCT_OUTPUTCLR0_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos)                      /*!< SCT OUTPUTCLR0: CLRn5 Mask          */
+#define SCT_OUTPUTCLR0_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR0: CLRn6 Position      */
+#define SCT_OUTPUTCLR0_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos)                      /*!< SCT OUTPUTCLR0: CLRn6 Mask          */
+#define SCT_OUTPUTCLR0_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR0: CLRn7 Position      */
+#define SCT_OUTPUTCLR0_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos)                      /*!< SCT OUTPUTCLR0: CLRn7 Mask          */
+#define SCT_OUTPUTCLR0_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR0: CLRn8 Position      */
+#define SCT_OUTPUTCLR0_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos)                      /*!< SCT OUTPUTCLR0: CLRn8 Mask          */
+#define SCT_OUTPUTCLR0_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR0: CLRn9 Position      */
+#define SCT_OUTPUTCLR0_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos)                      /*!< SCT OUTPUTCLR0: CLRn9 Mask          */
+#define SCT_OUTPUTCLR0_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR0: CLRn10 Position     */
+#define SCT_OUTPUTCLR0_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos)                     /*!< SCT OUTPUTCLR0: CLRn10 Mask         */
+#define SCT_OUTPUTCLR0_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR0: CLRn11 Position     */
+#define SCT_OUTPUTCLR0_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos)                     /*!< SCT OUTPUTCLR0: CLRn11 Mask         */
+#define SCT_OUTPUTCLR0_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR0: CLRn12 Position     */
+#define SCT_OUTPUTCLR0_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos)                     /*!< SCT OUTPUTCLR0: CLRn12 Mask         */
+#define SCT_OUTPUTCLR0_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR0: CLRn13 Position     */
+#define SCT_OUTPUTCLR0_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos)                     /*!< SCT OUTPUTCLR0: CLRn13 Mask         */
+#define SCT_OUTPUTCLR0_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR0: CLRn14 Position     */
+#define SCT_OUTPUTCLR0_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos)                     /*!< SCT OUTPUTCLR0: CLRn14 Mask         */
+#define SCT_OUTPUTCLR0_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR0: CLRn15 Position     */
+#define SCT_OUTPUTCLR0_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos)                     /*!< SCT OUTPUTCLR0: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET1  -----------------------------------------
+#define SCT_OUTPUTSET1_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET1: SETn0 Position      */
+#define SCT_OUTPUTSET1_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn0_Pos)                      /*!< SCT OUTPUTSET1: SETn0 Mask          */
+#define SCT_OUTPUTSET1_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET1: SETn1 Position      */
+#define SCT_OUTPUTSET1_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn1_Pos)                      /*!< SCT OUTPUTSET1: SETn1 Mask          */
+#define SCT_OUTPUTSET1_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET1: SETn2 Position      */
+#define SCT_OUTPUTSET1_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn2_Pos)                      /*!< SCT OUTPUTSET1: SETn2 Mask          */
+#define SCT_OUTPUTSET1_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET1: SETn3 Position      */
+#define SCT_OUTPUTSET1_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn3_Pos)                      /*!< SCT OUTPUTSET1: SETn3 Mask          */
+#define SCT_OUTPUTSET1_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET1: SETn4 Position      */
+#define SCT_OUTPUTSET1_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn4_Pos)                      /*!< SCT OUTPUTSET1: SETn4 Mask          */
+#define SCT_OUTPUTSET1_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET1: SETn5 Position      */
+#define SCT_OUTPUTSET1_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn5_Pos)                      /*!< SCT OUTPUTSET1: SETn5 Mask          */
+#define SCT_OUTPUTSET1_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET1: SETn6 Position      */
+#define SCT_OUTPUTSET1_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn6_Pos)                      /*!< SCT OUTPUTSET1: SETn6 Mask          */
+#define SCT_OUTPUTSET1_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET1: SETn7 Position      */
+#define SCT_OUTPUTSET1_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn7_Pos)                      /*!< SCT OUTPUTSET1: SETn7 Mask          */
+#define SCT_OUTPUTSET1_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET1: SETn8 Position      */
+#define SCT_OUTPUTSET1_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn8_Pos)                      /*!< SCT OUTPUTSET1: SETn8 Mask          */
+#define SCT_OUTPUTSET1_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET1: SETn9 Position      */
+#define SCT_OUTPUTSET1_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn9_Pos)                      /*!< SCT OUTPUTSET1: SETn9 Mask          */
+#define SCT_OUTPUTSET1_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET1: SETn10 Position     */
+#define SCT_OUTPUTSET1_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn10_Pos)                     /*!< SCT OUTPUTSET1: SETn10 Mask         */
+#define SCT_OUTPUTSET1_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET1: SETn11 Position     */
+#define SCT_OUTPUTSET1_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn11_Pos)                     /*!< SCT OUTPUTSET1: SETn11 Mask         */
+#define SCT_OUTPUTSET1_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET1: SETn12 Position     */
+#define SCT_OUTPUTSET1_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn12_Pos)                     /*!< SCT OUTPUTSET1: SETn12 Mask         */
+#define SCT_OUTPUTSET1_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET1: SETn13 Position     */
+#define SCT_OUTPUTSET1_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn13_Pos)                     /*!< SCT OUTPUTSET1: SETn13 Mask         */
+#define SCT_OUTPUTSET1_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET1: SETn14 Position     */
+#define SCT_OUTPUTSET1_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn14_Pos)                     /*!< SCT OUTPUTSET1: SETn14 Mask         */
+#define SCT_OUTPUTSET1_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET1: SETn15 Position     */
+#define SCT_OUTPUTSET1_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn15_Pos)                     /*!< SCT OUTPUTSET1: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR1  -----------------------------------------
+#define SCT_OUTPUTCLR1_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR1: CLRn0 Position      */
+#define SCT_OUTPUTCLR1_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos)                      /*!< SCT OUTPUTCLR1: CLRn0 Mask          */
+#define SCT_OUTPUTCLR1_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR1: CLRn1 Position      */
+#define SCT_OUTPUTCLR1_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos)                      /*!< SCT OUTPUTCLR1: CLRn1 Mask          */
+#define SCT_OUTPUTCLR1_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR1: CLRn2 Position      */
+#define SCT_OUTPUTCLR1_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos)                      /*!< SCT OUTPUTCLR1: CLRn2 Mask          */
+#define SCT_OUTPUTCLR1_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR1: CLRn3 Position      */
+#define SCT_OUTPUTCLR1_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos)                      /*!< SCT OUTPUTCLR1: CLRn3 Mask          */
+#define SCT_OUTPUTCLR1_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR1: CLRn4 Position      */
+#define SCT_OUTPUTCLR1_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos)                      /*!< SCT OUTPUTCLR1: CLRn4 Mask          */
+#define SCT_OUTPUTCLR1_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR1: CLRn5 Position      */
+#define SCT_OUTPUTCLR1_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos)                      /*!< SCT OUTPUTCLR1: CLRn5 Mask          */
+#define SCT_OUTPUTCLR1_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR1: CLRn6 Position      */
+#define SCT_OUTPUTCLR1_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos)                      /*!< SCT OUTPUTCLR1: CLRn6 Mask          */
+#define SCT_OUTPUTCLR1_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR1: CLRn7 Position      */
+#define SCT_OUTPUTCLR1_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos)                      /*!< SCT OUTPUTCLR1: CLRn7 Mask          */
+#define SCT_OUTPUTCLR1_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR1: CLRn8 Position      */
+#define SCT_OUTPUTCLR1_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos)                      /*!< SCT OUTPUTCLR1: CLRn8 Mask          */
+#define SCT_OUTPUTCLR1_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR1: CLRn9 Position      */
+#define SCT_OUTPUTCLR1_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos)                      /*!< SCT OUTPUTCLR1: CLRn9 Mask          */
+#define SCT_OUTPUTCLR1_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR1: CLRn10 Position     */
+#define SCT_OUTPUTCLR1_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos)                     /*!< SCT OUTPUTCLR1: CLRn10 Mask         */
+#define SCT_OUTPUTCLR1_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR1: CLRn11 Position     */
+#define SCT_OUTPUTCLR1_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos)                     /*!< SCT OUTPUTCLR1: CLRn11 Mask         */
+#define SCT_OUTPUTCLR1_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR1: CLRn12 Position     */
+#define SCT_OUTPUTCLR1_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos)                     /*!< SCT OUTPUTCLR1: CLRn12 Mask         */
+#define SCT_OUTPUTCLR1_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR1: CLRn13 Position     */
+#define SCT_OUTPUTCLR1_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos)                     /*!< SCT OUTPUTCLR1: CLRn13 Mask         */
+#define SCT_OUTPUTCLR1_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR1: CLRn14 Position     */
+#define SCT_OUTPUTCLR1_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos)                     /*!< SCT OUTPUTCLR1: CLRn14 Mask         */
+#define SCT_OUTPUTCLR1_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR1: CLRn15 Position     */
+#define SCT_OUTPUTCLR1_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos)                     /*!< SCT OUTPUTCLR1: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET2  -----------------------------------------
+#define SCT_OUTPUTSET2_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET2: SETn0 Position      */
+#define SCT_OUTPUTSET2_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn0_Pos)                      /*!< SCT OUTPUTSET2: SETn0 Mask          */
+#define SCT_OUTPUTSET2_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET2: SETn1 Position      */
+#define SCT_OUTPUTSET2_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn1_Pos)                      /*!< SCT OUTPUTSET2: SETn1 Mask          */
+#define SCT_OUTPUTSET2_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET2: SETn2 Position      */
+#define SCT_OUTPUTSET2_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn2_Pos)                      /*!< SCT OUTPUTSET2: SETn2 Mask          */
+#define SCT_OUTPUTSET2_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET2: SETn3 Position      */
+#define SCT_OUTPUTSET2_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn3_Pos)                      /*!< SCT OUTPUTSET2: SETn3 Mask          */
+#define SCT_OUTPUTSET2_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET2: SETn4 Position      */
+#define SCT_OUTPUTSET2_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn4_Pos)                      /*!< SCT OUTPUTSET2: SETn4 Mask          */
+#define SCT_OUTPUTSET2_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET2: SETn5 Position      */
+#define SCT_OUTPUTSET2_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn5_Pos)                      /*!< SCT OUTPUTSET2: SETn5 Mask          */
+#define SCT_OUTPUTSET2_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET2: SETn6 Position      */
+#define SCT_OUTPUTSET2_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn6_Pos)                      /*!< SCT OUTPUTSET2: SETn6 Mask          */
+#define SCT_OUTPUTSET2_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET2: SETn7 Position      */
+#define SCT_OUTPUTSET2_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn7_Pos)                      /*!< SCT OUTPUTSET2: SETn7 Mask          */
+#define SCT_OUTPUTSET2_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET2: SETn8 Position      */
+#define SCT_OUTPUTSET2_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn8_Pos)                      /*!< SCT OUTPUTSET2: SETn8 Mask          */
+#define SCT_OUTPUTSET2_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET2: SETn9 Position      */
+#define SCT_OUTPUTSET2_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn9_Pos)                      /*!< SCT OUTPUTSET2: SETn9 Mask          */
+#define SCT_OUTPUTSET2_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET2: SETn10 Position     */
+#define SCT_OUTPUTSET2_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn10_Pos)                     /*!< SCT OUTPUTSET2: SETn10 Mask         */
+#define SCT_OUTPUTSET2_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET2: SETn11 Position     */
+#define SCT_OUTPUTSET2_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn11_Pos)                     /*!< SCT OUTPUTSET2: SETn11 Mask         */
+#define SCT_OUTPUTSET2_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET2: SETn12 Position     */
+#define SCT_OUTPUTSET2_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn12_Pos)                     /*!< SCT OUTPUTSET2: SETn12 Mask         */
+#define SCT_OUTPUTSET2_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET2: SETn13 Position     */
+#define SCT_OUTPUTSET2_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn13_Pos)                     /*!< SCT OUTPUTSET2: SETn13 Mask         */
+#define SCT_OUTPUTSET2_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET2: SETn14 Position     */
+#define SCT_OUTPUTSET2_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn14_Pos)                     /*!< SCT OUTPUTSET2: SETn14 Mask         */
+#define SCT_OUTPUTSET2_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET2: SETn15 Position     */
+#define SCT_OUTPUTSET2_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn15_Pos)                     /*!< SCT OUTPUTSET2: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR2  -----------------------------------------
+#define SCT_OUTPUTCLR2_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR2: CLRn0 Position      */
+#define SCT_OUTPUTCLR2_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos)                      /*!< SCT OUTPUTCLR2: CLRn0 Mask          */
+#define SCT_OUTPUTCLR2_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR2: CLRn1 Position      */
+#define SCT_OUTPUTCLR2_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos)                      /*!< SCT OUTPUTCLR2: CLRn1 Mask          */
+#define SCT_OUTPUTCLR2_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR2: CLRn2 Position      */
+#define SCT_OUTPUTCLR2_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos)                      /*!< SCT OUTPUTCLR2: CLRn2 Mask          */
+#define SCT_OUTPUTCLR2_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR2: CLRn3 Position      */
+#define SCT_OUTPUTCLR2_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos)                      /*!< SCT OUTPUTCLR2: CLRn3 Mask          */
+#define SCT_OUTPUTCLR2_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR2: CLRn4 Position      */
+#define SCT_OUTPUTCLR2_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos)                      /*!< SCT OUTPUTCLR2: CLRn4 Mask          */
+#define SCT_OUTPUTCLR2_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR2: CLRn5 Position      */
+#define SCT_OUTPUTCLR2_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos)                      /*!< SCT OUTPUTCLR2: CLRn5 Mask          */
+#define SCT_OUTPUTCLR2_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR2: CLRn6 Position      */
+#define SCT_OUTPUTCLR2_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos)                      /*!< SCT OUTPUTCLR2: CLRn6 Mask          */
+#define SCT_OUTPUTCLR2_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR2: CLRn7 Position      */
+#define SCT_OUTPUTCLR2_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos)                      /*!< SCT OUTPUTCLR2: CLRn7 Mask          */
+#define SCT_OUTPUTCLR2_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR2: CLRn8 Position      */
+#define SCT_OUTPUTCLR2_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos)                      /*!< SCT OUTPUTCLR2: CLRn8 Mask          */
+#define SCT_OUTPUTCLR2_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR2: CLRn9 Position      */
+#define SCT_OUTPUTCLR2_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos)                      /*!< SCT OUTPUTCLR2: CLRn9 Mask          */
+#define SCT_OUTPUTCLR2_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR2: CLRn10 Position     */
+#define SCT_OUTPUTCLR2_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos)                     /*!< SCT OUTPUTCLR2: CLRn10 Mask         */
+#define SCT_OUTPUTCLR2_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR2: CLRn11 Position     */
+#define SCT_OUTPUTCLR2_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos)                     /*!< SCT OUTPUTCLR2: CLRn11 Mask         */
+#define SCT_OUTPUTCLR2_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR2: CLRn12 Position     */
+#define SCT_OUTPUTCLR2_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos)                     /*!< SCT OUTPUTCLR2: CLRn12 Mask         */
+#define SCT_OUTPUTCLR2_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR2: CLRn13 Position     */
+#define SCT_OUTPUTCLR2_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos)                     /*!< SCT OUTPUTCLR2: CLRn13 Mask         */
+#define SCT_OUTPUTCLR2_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR2: CLRn14 Position     */
+#define SCT_OUTPUTCLR2_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos)                     /*!< SCT OUTPUTCLR2: CLRn14 Mask         */
+#define SCT_OUTPUTCLR2_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR2: CLRn15 Position     */
+#define SCT_OUTPUTCLR2_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos)                     /*!< SCT OUTPUTCLR2: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET3  -----------------------------------------
+#define SCT_OUTPUTSET3_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET3: SETn0 Position      */
+#define SCT_OUTPUTSET3_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn0_Pos)                      /*!< SCT OUTPUTSET3: SETn0 Mask          */
+#define SCT_OUTPUTSET3_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET3: SETn1 Position      */
+#define SCT_OUTPUTSET3_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn1_Pos)                      /*!< SCT OUTPUTSET3: SETn1 Mask          */
+#define SCT_OUTPUTSET3_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET3: SETn2 Position      */
+#define SCT_OUTPUTSET3_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn2_Pos)                      /*!< SCT OUTPUTSET3: SETn2 Mask          */
+#define SCT_OUTPUTSET3_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET3: SETn3 Position      */
+#define SCT_OUTPUTSET3_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn3_Pos)                      /*!< SCT OUTPUTSET3: SETn3 Mask          */
+#define SCT_OUTPUTSET3_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET3: SETn4 Position      */
+#define SCT_OUTPUTSET3_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn4_Pos)                      /*!< SCT OUTPUTSET3: SETn4 Mask          */
+#define SCT_OUTPUTSET3_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET3: SETn5 Position      */
+#define SCT_OUTPUTSET3_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn5_Pos)                      /*!< SCT OUTPUTSET3: SETn5 Mask          */
+#define SCT_OUTPUTSET3_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET3: SETn6 Position      */
+#define SCT_OUTPUTSET3_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn6_Pos)                      /*!< SCT OUTPUTSET3: SETn6 Mask          */
+#define SCT_OUTPUTSET3_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET3: SETn7 Position      */
+#define SCT_OUTPUTSET3_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn7_Pos)                      /*!< SCT OUTPUTSET3: SETn7 Mask          */
+#define SCT_OUTPUTSET3_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET3: SETn8 Position      */
+#define SCT_OUTPUTSET3_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn8_Pos)                      /*!< SCT OUTPUTSET3: SETn8 Mask          */
+#define SCT_OUTPUTSET3_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET3: SETn9 Position      */
+#define SCT_OUTPUTSET3_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn9_Pos)                      /*!< SCT OUTPUTSET3: SETn9 Mask          */
+#define SCT_OUTPUTSET3_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET3: SETn10 Position     */
+#define SCT_OUTPUTSET3_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn10_Pos)                     /*!< SCT OUTPUTSET3: SETn10 Mask         */
+#define SCT_OUTPUTSET3_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET3: SETn11 Position     */
+#define SCT_OUTPUTSET3_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn11_Pos)                     /*!< SCT OUTPUTSET3: SETn11 Mask         */
+#define SCT_OUTPUTSET3_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET3: SETn12 Position     */
+#define SCT_OUTPUTSET3_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn12_Pos)                     /*!< SCT OUTPUTSET3: SETn12 Mask         */
+#define SCT_OUTPUTSET3_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET3: SETn13 Position     */
+#define SCT_OUTPUTSET3_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn13_Pos)                     /*!< SCT OUTPUTSET3: SETn13 Mask         */
+#define SCT_OUTPUTSET3_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET3: SETn14 Position     */
+#define SCT_OUTPUTSET3_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn14_Pos)                     /*!< SCT OUTPUTSET3: SETn14 Mask         */
+#define SCT_OUTPUTSET3_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET3: SETn15 Position     */
+#define SCT_OUTPUTSET3_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn15_Pos)                     /*!< SCT OUTPUTSET3: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR3  -----------------------------------------
+#define SCT_OUTPUTCLR3_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR3: CLRn0 Position      */
+#define SCT_OUTPUTCLR3_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos)                      /*!< SCT OUTPUTCLR3: CLRn0 Mask          */
+#define SCT_OUTPUTCLR3_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR3: CLRn1 Position      */
+#define SCT_OUTPUTCLR3_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos)                      /*!< SCT OUTPUTCLR3: CLRn1 Mask          */
+#define SCT_OUTPUTCLR3_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR3: CLRn2 Position      */
+#define SCT_OUTPUTCLR3_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos)                      /*!< SCT OUTPUTCLR3: CLRn2 Mask          */
+#define SCT_OUTPUTCLR3_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR3: CLRn3 Position      */
+#define SCT_OUTPUTCLR3_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos)                      /*!< SCT OUTPUTCLR3: CLRn3 Mask          */
+#define SCT_OUTPUTCLR3_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR3: CLRn4 Position      */
+#define SCT_OUTPUTCLR3_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos)                      /*!< SCT OUTPUTCLR3: CLRn4 Mask          */
+#define SCT_OUTPUTCLR3_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR3: CLRn5 Position      */
+#define SCT_OUTPUTCLR3_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos)                      /*!< SCT OUTPUTCLR3: CLRn5 Mask          */
+#define SCT_OUTPUTCLR3_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR3: CLRn6 Position      */
+#define SCT_OUTPUTCLR3_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos)                      /*!< SCT OUTPUTCLR3: CLRn6 Mask          */
+#define SCT_OUTPUTCLR3_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR3: CLRn7 Position      */
+#define SCT_OUTPUTCLR3_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos)                      /*!< SCT OUTPUTCLR3: CLRn7 Mask          */
+#define SCT_OUTPUTCLR3_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR3: CLRn8 Position      */
+#define SCT_OUTPUTCLR3_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos)                      /*!< SCT OUTPUTCLR3: CLRn8 Mask          */
+#define SCT_OUTPUTCLR3_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR3: CLRn9 Position      */
+#define SCT_OUTPUTCLR3_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos)                      /*!< SCT OUTPUTCLR3: CLRn9 Mask          */
+#define SCT_OUTPUTCLR3_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR3: CLRn10 Position     */
+#define SCT_OUTPUTCLR3_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos)                     /*!< SCT OUTPUTCLR3: CLRn10 Mask         */
+#define SCT_OUTPUTCLR3_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR3: CLRn11 Position     */
+#define SCT_OUTPUTCLR3_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos)                     /*!< SCT OUTPUTCLR3: CLRn11 Mask         */
+#define SCT_OUTPUTCLR3_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR3: CLRn12 Position     */
+#define SCT_OUTPUTCLR3_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos)                     /*!< SCT OUTPUTCLR3: CLRn12 Mask         */
+#define SCT_OUTPUTCLR3_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR3: CLRn13 Position     */
+#define SCT_OUTPUTCLR3_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos)                     /*!< SCT OUTPUTCLR3: CLRn13 Mask         */
+#define SCT_OUTPUTCLR3_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR3: CLRn14 Position     */
+#define SCT_OUTPUTCLR3_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos)                     /*!< SCT OUTPUTCLR3: CLRn14 Mask         */
+#define SCT_OUTPUTCLR3_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR3: CLRn15 Position     */
+#define SCT_OUTPUTCLR3_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos)                     /*!< SCT OUTPUTCLR3: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET4  -----------------------------------------
+#define SCT_OUTPUTSET4_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET4: SETn0 Position      */
+#define SCT_OUTPUTSET4_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn0_Pos)                      /*!< SCT OUTPUTSET4: SETn0 Mask          */
+#define SCT_OUTPUTSET4_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET4: SETn1 Position      */
+#define SCT_OUTPUTSET4_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn1_Pos)                      /*!< SCT OUTPUTSET4: SETn1 Mask          */
+#define SCT_OUTPUTSET4_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET4: SETn2 Position      */
+#define SCT_OUTPUTSET4_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn2_Pos)                      /*!< SCT OUTPUTSET4: SETn2 Mask          */
+#define SCT_OUTPUTSET4_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET4: SETn3 Position      */
+#define SCT_OUTPUTSET4_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn3_Pos)                      /*!< SCT OUTPUTSET4: SETn3 Mask          */
+#define SCT_OUTPUTSET4_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET4: SETn4 Position      */
+#define SCT_OUTPUTSET4_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn4_Pos)                      /*!< SCT OUTPUTSET4: SETn4 Mask          */
+#define SCT_OUTPUTSET4_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET4: SETn5 Position      */
+#define SCT_OUTPUTSET4_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn5_Pos)                      /*!< SCT OUTPUTSET4: SETn5 Mask          */
+#define SCT_OUTPUTSET4_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET4: SETn6 Position      */
+#define SCT_OUTPUTSET4_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn6_Pos)                      /*!< SCT OUTPUTSET4: SETn6 Mask          */
+#define SCT_OUTPUTSET4_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET4: SETn7 Position      */
+#define SCT_OUTPUTSET4_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn7_Pos)                      /*!< SCT OUTPUTSET4: SETn7 Mask          */
+#define SCT_OUTPUTSET4_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET4: SETn8 Position      */
+#define SCT_OUTPUTSET4_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn8_Pos)                      /*!< SCT OUTPUTSET4: SETn8 Mask          */
+#define SCT_OUTPUTSET4_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET4: SETn9 Position      */
+#define SCT_OUTPUTSET4_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn9_Pos)                      /*!< SCT OUTPUTSET4: SETn9 Mask          */
+#define SCT_OUTPUTSET4_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET4: SETn10 Position     */
+#define SCT_OUTPUTSET4_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn10_Pos)                     /*!< SCT OUTPUTSET4: SETn10 Mask         */
+#define SCT_OUTPUTSET4_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET4: SETn11 Position     */
+#define SCT_OUTPUTSET4_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn11_Pos)                     /*!< SCT OUTPUTSET4: SETn11 Mask         */
+#define SCT_OUTPUTSET4_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET4: SETn12 Position     */
+#define SCT_OUTPUTSET4_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn12_Pos)                     /*!< SCT OUTPUTSET4: SETn12 Mask         */
+#define SCT_OUTPUTSET4_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET4: SETn13 Position     */
+#define SCT_OUTPUTSET4_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn13_Pos)                     /*!< SCT OUTPUTSET4: SETn13 Mask         */
+#define SCT_OUTPUTSET4_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET4: SETn14 Position     */
+#define SCT_OUTPUTSET4_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn14_Pos)                     /*!< SCT OUTPUTSET4: SETn14 Mask         */
+#define SCT_OUTPUTSET4_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET4: SETn15 Position     */
+#define SCT_OUTPUTSET4_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn15_Pos)                     /*!< SCT OUTPUTSET4: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR4  -----------------------------------------
+#define SCT_OUTPUTCLR4_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR4: CLRn0 Position      */
+#define SCT_OUTPUTCLR4_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos)                      /*!< SCT OUTPUTCLR4: CLRn0 Mask          */
+#define SCT_OUTPUTCLR4_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR4: CLRn1 Position      */
+#define SCT_OUTPUTCLR4_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos)                      /*!< SCT OUTPUTCLR4: CLRn1 Mask          */
+#define SCT_OUTPUTCLR4_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR4: CLRn2 Position      */
+#define SCT_OUTPUTCLR4_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos)                      /*!< SCT OUTPUTCLR4: CLRn2 Mask          */
+#define SCT_OUTPUTCLR4_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR4: CLRn3 Position      */
+#define SCT_OUTPUTCLR4_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos)                      /*!< SCT OUTPUTCLR4: CLRn3 Mask          */
+#define SCT_OUTPUTCLR4_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR4: CLRn4 Position      */
+#define SCT_OUTPUTCLR4_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos)                      /*!< SCT OUTPUTCLR4: CLRn4 Mask          */
+#define SCT_OUTPUTCLR4_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR4: CLRn5 Position      */
+#define SCT_OUTPUTCLR4_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos)                      /*!< SCT OUTPUTCLR4: CLRn5 Mask          */
+#define SCT_OUTPUTCLR4_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR4: CLRn6 Position      */
+#define SCT_OUTPUTCLR4_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos)                      /*!< SCT OUTPUTCLR4: CLRn6 Mask          */
+#define SCT_OUTPUTCLR4_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR4: CLRn7 Position      */
+#define SCT_OUTPUTCLR4_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos)                      /*!< SCT OUTPUTCLR4: CLRn7 Mask          */
+#define SCT_OUTPUTCLR4_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR4: CLRn8 Position      */
+#define SCT_OUTPUTCLR4_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos)                      /*!< SCT OUTPUTCLR4: CLRn8 Mask          */
+#define SCT_OUTPUTCLR4_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR4: CLRn9 Position      */
+#define SCT_OUTPUTCLR4_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos)                      /*!< SCT OUTPUTCLR4: CLRn9 Mask          */
+#define SCT_OUTPUTCLR4_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR4: CLRn10 Position     */
+#define SCT_OUTPUTCLR4_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos)                     /*!< SCT OUTPUTCLR4: CLRn10 Mask         */
+#define SCT_OUTPUTCLR4_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR4: CLRn11 Position     */
+#define SCT_OUTPUTCLR4_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos)                     /*!< SCT OUTPUTCLR4: CLRn11 Mask         */
+#define SCT_OUTPUTCLR4_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR4: CLRn12 Position     */
+#define SCT_OUTPUTCLR4_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos)                     /*!< SCT OUTPUTCLR4: CLRn12 Mask         */
+#define SCT_OUTPUTCLR4_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR4: CLRn13 Position     */
+#define SCT_OUTPUTCLR4_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos)                     /*!< SCT OUTPUTCLR4: CLRn13 Mask         */
+#define SCT_OUTPUTCLR4_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR4: CLRn14 Position     */
+#define SCT_OUTPUTCLR4_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos)                     /*!< SCT OUTPUTCLR4: CLRn14 Mask         */
+#define SCT_OUTPUTCLR4_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR4: CLRn15 Position     */
+#define SCT_OUTPUTCLR4_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos)                     /*!< SCT OUTPUTCLR4: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET5  -----------------------------------------
+#define SCT_OUTPUTSET5_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET5: SETn0 Position      */
+#define SCT_OUTPUTSET5_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn0_Pos)                      /*!< SCT OUTPUTSET5: SETn0 Mask          */
+#define SCT_OUTPUTSET5_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET5: SETn1 Position      */
+#define SCT_OUTPUTSET5_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn1_Pos)                      /*!< SCT OUTPUTSET5: SETn1 Mask          */
+#define SCT_OUTPUTSET5_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET5: SETn2 Position      */
+#define SCT_OUTPUTSET5_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn2_Pos)                      /*!< SCT OUTPUTSET5: SETn2 Mask          */
+#define SCT_OUTPUTSET5_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET5: SETn3 Position      */
+#define SCT_OUTPUTSET5_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn3_Pos)                      /*!< SCT OUTPUTSET5: SETn3 Mask          */
+#define SCT_OUTPUTSET5_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET5: SETn4 Position      */
+#define SCT_OUTPUTSET5_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn4_Pos)                      /*!< SCT OUTPUTSET5: SETn4 Mask          */
+#define SCT_OUTPUTSET5_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET5: SETn5 Position      */
+#define SCT_OUTPUTSET5_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn5_Pos)                      /*!< SCT OUTPUTSET5: SETn5 Mask          */
+#define SCT_OUTPUTSET5_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET5: SETn6 Position      */
+#define SCT_OUTPUTSET5_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn6_Pos)                      /*!< SCT OUTPUTSET5: SETn6 Mask          */
+#define SCT_OUTPUTSET5_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET5: SETn7 Position      */
+#define SCT_OUTPUTSET5_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn7_Pos)                      /*!< SCT OUTPUTSET5: SETn7 Mask          */
+#define SCT_OUTPUTSET5_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET5: SETn8 Position      */
+#define SCT_OUTPUTSET5_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn8_Pos)                      /*!< SCT OUTPUTSET5: SETn8 Mask          */
+#define SCT_OUTPUTSET5_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET5: SETn9 Position      */
+#define SCT_OUTPUTSET5_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn9_Pos)                      /*!< SCT OUTPUTSET5: SETn9 Mask          */
+#define SCT_OUTPUTSET5_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET5: SETn10 Position     */
+#define SCT_OUTPUTSET5_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn10_Pos)                     /*!< SCT OUTPUTSET5: SETn10 Mask         */
+#define SCT_OUTPUTSET5_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET5: SETn11 Position     */
+#define SCT_OUTPUTSET5_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn11_Pos)                     /*!< SCT OUTPUTSET5: SETn11 Mask         */
+#define SCT_OUTPUTSET5_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET5: SETn12 Position     */
+#define SCT_OUTPUTSET5_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn12_Pos)                     /*!< SCT OUTPUTSET5: SETn12 Mask         */
+#define SCT_OUTPUTSET5_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET5: SETn13 Position     */
+#define SCT_OUTPUTSET5_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn13_Pos)                     /*!< SCT OUTPUTSET5: SETn13 Mask         */
+#define SCT_OUTPUTSET5_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET5: SETn14 Position     */
+#define SCT_OUTPUTSET5_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn14_Pos)                     /*!< SCT OUTPUTSET5: SETn14 Mask         */
+#define SCT_OUTPUTSET5_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET5: SETn15 Position     */
+#define SCT_OUTPUTSET5_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn15_Pos)                     /*!< SCT OUTPUTSET5: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR5  -----------------------------------------
+#define SCT_OUTPUTCLR5_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR5: CLRn0 Position      */
+#define SCT_OUTPUTCLR5_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos)                      /*!< SCT OUTPUTCLR5: CLRn0 Mask          */
+#define SCT_OUTPUTCLR5_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR5: CLRn1 Position      */
+#define SCT_OUTPUTCLR5_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos)                      /*!< SCT OUTPUTCLR5: CLRn1 Mask          */
+#define SCT_OUTPUTCLR5_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR5: CLRn2 Position      */
+#define SCT_OUTPUTCLR5_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos)                      /*!< SCT OUTPUTCLR5: CLRn2 Mask          */
+#define SCT_OUTPUTCLR5_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR5: CLRn3 Position      */
+#define SCT_OUTPUTCLR5_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos)                      /*!< SCT OUTPUTCLR5: CLRn3 Mask          */
+#define SCT_OUTPUTCLR5_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR5: CLRn4 Position      */
+#define SCT_OUTPUTCLR5_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos)                      /*!< SCT OUTPUTCLR5: CLRn4 Mask          */
+#define SCT_OUTPUTCLR5_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR5: CLRn5 Position      */
+#define SCT_OUTPUTCLR5_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos)                      /*!< SCT OUTPUTCLR5: CLRn5 Mask          */
+#define SCT_OUTPUTCLR5_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR5: CLRn6 Position      */
+#define SCT_OUTPUTCLR5_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos)                      /*!< SCT OUTPUTCLR5: CLRn6 Mask          */
+#define SCT_OUTPUTCLR5_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR5: CLRn7 Position      */
+#define SCT_OUTPUTCLR5_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos)                      /*!< SCT OUTPUTCLR5: CLRn7 Mask          */
+#define SCT_OUTPUTCLR5_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR5: CLRn8 Position      */
+#define SCT_OUTPUTCLR5_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos)                      /*!< SCT OUTPUTCLR5: CLRn8 Mask          */
+#define SCT_OUTPUTCLR5_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR5: CLRn9 Position      */
+#define SCT_OUTPUTCLR5_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos)                      /*!< SCT OUTPUTCLR5: CLRn9 Mask          */
+#define SCT_OUTPUTCLR5_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR5: CLRn10 Position     */
+#define SCT_OUTPUTCLR5_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos)                     /*!< SCT OUTPUTCLR5: CLRn10 Mask         */
+#define SCT_OUTPUTCLR5_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR5: CLRn11 Position     */
+#define SCT_OUTPUTCLR5_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos)                     /*!< SCT OUTPUTCLR5: CLRn11 Mask         */
+#define SCT_OUTPUTCLR5_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR5: CLRn12 Position     */
+#define SCT_OUTPUTCLR5_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos)                     /*!< SCT OUTPUTCLR5: CLRn12 Mask         */
+#define SCT_OUTPUTCLR5_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR5: CLRn13 Position     */
+#define SCT_OUTPUTCLR5_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos)                     /*!< SCT OUTPUTCLR5: CLRn13 Mask         */
+#define SCT_OUTPUTCLR5_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR5: CLRn14 Position     */
+#define SCT_OUTPUTCLR5_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos)                     /*!< SCT OUTPUTCLR5: CLRn14 Mask         */
+#define SCT_OUTPUTCLR5_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR5: CLRn15 Position     */
+#define SCT_OUTPUTCLR5_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos)                     /*!< SCT OUTPUTCLR5: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET6  -----------------------------------------
+#define SCT_OUTPUTSET6_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET6: SETn0 Position      */
+#define SCT_OUTPUTSET6_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn0_Pos)                      /*!< SCT OUTPUTSET6: SETn0 Mask          */
+#define SCT_OUTPUTSET6_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET6: SETn1 Position      */
+#define SCT_OUTPUTSET6_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn1_Pos)                      /*!< SCT OUTPUTSET6: SETn1 Mask          */
+#define SCT_OUTPUTSET6_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET6: SETn2 Position      */
+#define SCT_OUTPUTSET6_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn2_Pos)                      /*!< SCT OUTPUTSET6: SETn2 Mask          */
+#define SCT_OUTPUTSET6_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET6: SETn3 Position      */
+#define SCT_OUTPUTSET6_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn3_Pos)                      /*!< SCT OUTPUTSET6: SETn3 Mask          */
+#define SCT_OUTPUTSET6_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET6: SETn4 Position      */
+#define SCT_OUTPUTSET6_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn4_Pos)                      /*!< SCT OUTPUTSET6: SETn4 Mask          */
+#define SCT_OUTPUTSET6_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET6: SETn5 Position      */
+#define SCT_OUTPUTSET6_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn5_Pos)                      /*!< SCT OUTPUTSET6: SETn5 Mask          */
+#define SCT_OUTPUTSET6_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET6: SETn6 Position      */
+#define SCT_OUTPUTSET6_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn6_Pos)                      /*!< SCT OUTPUTSET6: SETn6 Mask          */
+#define SCT_OUTPUTSET6_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET6: SETn7 Position      */
+#define SCT_OUTPUTSET6_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn7_Pos)                      /*!< SCT OUTPUTSET6: SETn7 Mask          */
+#define SCT_OUTPUTSET6_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET6: SETn8 Position      */
+#define SCT_OUTPUTSET6_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn8_Pos)                      /*!< SCT OUTPUTSET6: SETn8 Mask          */
+#define SCT_OUTPUTSET6_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET6: SETn9 Position      */
+#define SCT_OUTPUTSET6_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn9_Pos)                      /*!< SCT OUTPUTSET6: SETn9 Mask          */
+#define SCT_OUTPUTSET6_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET6: SETn10 Position     */
+#define SCT_OUTPUTSET6_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn10_Pos)                     /*!< SCT OUTPUTSET6: SETn10 Mask         */
+#define SCT_OUTPUTSET6_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET6: SETn11 Position     */
+#define SCT_OUTPUTSET6_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn11_Pos)                     /*!< SCT OUTPUTSET6: SETn11 Mask         */
+#define SCT_OUTPUTSET6_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET6: SETn12 Position     */
+#define SCT_OUTPUTSET6_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn12_Pos)                     /*!< SCT OUTPUTSET6: SETn12 Mask         */
+#define SCT_OUTPUTSET6_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET6: SETn13 Position     */
+#define SCT_OUTPUTSET6_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn13_Pos)                     /*!< SCT OUTPUTSET6: SETn13 Mask         */
+#define SCT_OUTPUTSET6_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET6: SETn14 Position     */
+#define SCT_OUTPUTSET6_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn14_Pos)                     /*!< SCT OUTPUTSET6: SETn14 Mask         */
+#define SCT_OUTPUTSET6_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET6: SETn15 Position     */
+#define SCT_OUTPUTSET6_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn15_Pos)                     /*!< SCT OUTPUTSET6: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR6  -----------------------------------------
+#define SCT_OUTPUTCLR6_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR6: CLRn0 Position      */
+#define SCT_OUTPUTCLR6_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos)                      /*!< SCT OUTPUTCLR6: CLRn0 Mask          */
+#define SCT_OUTPUTCLR6_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR6: CLRn1 Position      */
+#define SCT_OUTPUTCLR6_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos)                      /*!< SCT OUTPUTCLR6: CLRn1 Mask          */
+#define SCT_OUTPUTCLR6_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR6: CLRn2 Position      */
+#define SCT_OUTPUTCLR6_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos)                      /*!< SCT OUTPUTCLR6: CLRn2 Mask          */
+#define SCT_OUTPUTCLR6_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR6: CLRn3 Position      */
+#define SCT_OUTPUTCLR6_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos)                      /*!< SCT OUTPUTCLR6: CLRn3 Mask          */
+#define SCT_OUTPUTCLR6_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR6: CLRn4 Position      */
+#define SCT_OUTPUTCLR6_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos)                      /*!< SCT OUTPUTCLR6: CLRn4 Mask          */
+#define SCT_OUTPUTCLR6_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR6: CLRn5 Position      */
+#define SCT_OUTPUTCLR6_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos)                      /*!< SCT OUTPUTCLR6: CLRn5 Mask          */
+#define SCT_OUTPUTCLR6_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR6: CLRn6 Position      */
+#define SCT_OUTPUTCLR6_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos)                      /*!< SCT OUTPUTCLR6: CLRn6 Mask          */
+#define SCT_OUTPUTCLR6_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR6: CLRn7 Position      */
+#define SCT_OUTPUTCLR6_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos)                      /*!< SCT OUTPUTCLR6: CLRn7 Mask          */
+#define SCT_OUTPUTCLR6_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR6: CLRn8 Position      */
+#define SCT_OUTPUTCLR6_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos)                      /*!< SCT OUTPUTCLR6: CLRn8 Mask          */
+#define SCT_OUTPUTCLR6_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR6: CLRn9 Position      */
+#define SCT_OUTPUTCLR6_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos)                      /*!< SCT OUTPUTCLR6: CLRn9 Mask          */
+#define SCT_OUTPUTCLR6_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR6: CLRn10 Position     */
+#define SCT_OUTPUTCLR6_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos)                     /*!< SCT OUTPUTCLR6: CLRn10 Mask         */
+#define SCT_OUTPUTCLR6_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR6: CLRn11 Position     */
+#define SCT_OUTPUTCLR6_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos)                     /*!< SCT OUTPUTCLR6: CLRn11 Mask         */
+#define SCT_OUTPUTCLR6_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR6: CLRn12 Position     */
+#define SCT_OUTPUTCLR6_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos)                     /*!< SCT OUTPUTCLR6: CLRn12 Mask         */
+#define SCT_OUTPUTCLR6_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR6: CLRn13 Position     */
+#define SCT_OUTPUTCLR6_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos)                     /*!< SCT OUTPUTCLR6: CLRn13 Mask         */
+#define SCT_OUTPUTCLR6_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR6: CLRn14 Position     */
+#define SCT_OUTPUTCLR6_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos)                     /*!< SCT OUTPUTCLR6: CLRn14 Mask         */
+#define SCT_OUTPUTCLR6_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR6: CLRn15 Position     */
+#define SCT_OUTPUTCLR6_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos)                     /*!< SCT OUTPUTCLR6: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET7  -----------------------------------------
+#define SCT_OUTPUTSET7_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET7: SETn0 Position      */
+#define SCT_OUTPUTSET7_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn0_Pos)                      /*!< SCT OUTPUTSET7: SETn0 Mask          */
+#define SCT_OUTPUTSET7_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET7: SETn1 Position      */
+#define SCT_OUTPUTSET7_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn1_Pos)                      /*!< SCT OUTPUTSET7: SETn1 Mask          */
+#define SCT_OUTPUTSET7_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET7: SETn2 Position      */
+#define SCT_OUTPUTSET7_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn2_Pos)                      /*!< SCT OUTPUTSET7: SETn2 Mask          */
+#define SCT_OUTPUTSET7_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET7: SETn3 Position      */
+#define SCT_OUTPUTSET7_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn3_Pos)                      /*!< SCT OUTPUTSET7: SETn3 Mask          */
+#define SCT_OUTPUTSET7_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET7: SETn4 Position      */
+#define SCT_OUTPUTSET7_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn4_Pos)                      /*!< SCT OUTPUTSET7: SETn4 Mask          */
+#define SCT_OUTPUTSET7_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET7: SETn5 Position      */
+#define SCT_OUTPUTSET7_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn5_Pos)                      /*!< SCT OUTPUTSET7: SETn5 Mask          */
+#define SCT_OUTPUTSET7_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET7: SETn6 Position      */
+#define SCT_OUTPUTSET7_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn6_Pos)                      /*!< SCT OUTPUTSET7: SETn6 Mask          */
+#define SCT_OUTPUTSET7_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET7: SETn7 Position      */
+#define SCT_OUTPUTSET7_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn7_Pos)                      /*!< SCT OUTPUTSET7: SETn7 Mask          */
+#define SCT_OUTPUTSET7_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET7: SETn8 Position      */
+#define SCT_OUTPUTSET7_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn8_Pos)                      /*!< SCT OUTPUTSET7: SETn8 Mask          */
+#define SCT_OUTPUTSET7_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET7: SETn9 Position      */
+#define SCT_OUTPUTSET7_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn9_Pos)                      /*!< SCT OUTPUTSET7: SETn9 Mask          */
+#define SCT_OUTPUTSET7_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET7: SETn10 Position     */
+#define SCT_OUTPUTSET7_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn10_Pos)                     /*!< SCT OUTPUTSET7: SETn10 Mask         */
+#define SCT_OUTPUTSET7_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET7: SETn11 Position     */
+#define SCT_OUTPUTSET7_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn11_Pos)                     /*!< SCT OUTPUTSET7: SETn11 Mask         */
+#define SCT_OUTPUTSET7_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET7: SETn12 Position     */
+#define SCT_OUTPUTSET7_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn12_Pos)                     /*!< SCT OUTPUTSET7: SETn12 Mask         */
+#define SCT_OUTPUTSET7_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET7: SETn13 Position     */
+#define SCT_OUTPUTSET7_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn13_Pos)                     /*!< SCT OUTPUTSET7: SETn13 Mask         */
+#define SCT_OUTPUTSET7_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET7: SETn14 Position     */
+#define SCT_OUTPUTSET7_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn14_Pos)                     /*!< SCT OUTPUTSET7: SETn14 Mask         */
+#define SCT_OUTPUTSET7_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET7: SETn15 Position     */
+#define SCT_OUTPUTSET7_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn15_Pos)                     /*!< SCT OUTPUTSET7: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR7  -----------------------------------------
+#define SCT_OUTPUTCLR7_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR7: CLRn0 Position      */
+#define SCT_OUTPUTCLR7_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos)                      /*!< SCT OUTPUTCLR7: CLRn0 Mask          */
+#define SCT_OUTPUTCLR7_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR7: CLRn1 Position      */
+#define SCT_OUTPUTCLR7_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos)                      /*!< SCT OUTPUTCLR7: CLRn1 Mask          */
+#define SCT_OUTPUTCLR7_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR7: CLRn2 Position      */
+#define SCT_OUTPUTCLR7_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos)                      /*!< SCT OUTPUTCLR7: CLRn2 Mask          */
+#define SCT_OUTPUTCLR7_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR7: CLRn3 Position      */
+#define SCT_OUTPUTCLR7_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos)                      /*!< SCT OUTPUTCLR7: CLRn3 Mask          */
+#define SCT_OUTPUTCLR7_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR7: CLRn4 Position      */
+#define SCT_OUTPUTCLR7_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos)                      /*!< SCT OUTPUTCLR7: CLRn4 Mask          */
+#define SCT_OUTPUTCLR7_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR7: CLRn5 Position      */
+#define SCT_OUTPUTCLR7_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos)                      /*!< SCT OUTPUTCLR7: CLRn5 Mask          */
+#define SCT_OUTPUTCLR7_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR7: CLRn6 Position      */
+#define SCT_OUTPUTCLR7_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos)                      /*!< SCT OUTPUTCLR7: CLRn6 Mask          */
+#define SCT_OUTPUTCLR7_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR7: CLRn7 Position      */
+#define SCT_OUTPUTCLR7_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos)                      /*!< SCT OUTPUTCLR7: CLRn7 Mask          */
+#define SCT_OUTPUTCLR7_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR7: CLRn8 Position      */
+#define SCT_OUTPUTCLR7_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos)                      /*!< SCT OUTPUTCLR7: CLRn8 Mask          */
+#define SCT_OUTPUTCLR7_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR7: CLRn9 Position      */
+#define SCT_OUTPUTCLR7_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos)                      /*!< SCT OUTPUTCLR7: CLRn9 Mask          */
+#define SCT_OUTPUTCLR7_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR7: CLRn10 Position     */
+#define SCT_OUTPUTCLR7_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos)                     /*!< SCT OUTPUTCLR7: CLRn10 Mask         */
+#define SCT_OUTPUTCLR7_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR7: CLRn11 Position     */
+#define SCT_OUTPUTCLR7_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos)                     /*!< SCT OUTPUTCLR7: CLRn11 Mask         */
+#define SCT_OUTPUTCLR7_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR7: CLRn12 Position     */
+#define SCT_OUTPUTCLR7_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos)                     /*!< SCT OUTPUTCLR7: CLRn12 Mask         */
+#define SCT_OUTPUTCLR7_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR7: CLRn13 Position     */
+#define SCT_OUTPUTCLR7_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos)                     /*!< SCT OUTPUTCLR7: CLRn13 Mask         */
+#define SCT_OUTPUTCLR7_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR7: CLRn14 Position     */
+#define SCT_OUTPUTCLR7_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos)                     /*!< SCT OUTPUTCLR7: CLRn14 Mask         */
+#define SCT_OUTPUTCLR7_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR7: CLRn15 Position     */
+#define SCT_OUTPUTCLR7_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos)                     /*!< SCT OUTPUTCLR7: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET8  -----------------------------------------
+#define SCT_OUTPUTSET8_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET8: SETn0 Position      */
+#define SCT_OUTPUTSET8_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn0_Pos)                      /*!< SCT OUTPUTSET8: SETn0 Mask          */
+#define SCT_OUTPUTSET8_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET8: SETn1 Position      */
+#define SCT_OUTPUTSET8_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn1_Pos)                      /*!< SCT OUTPUTSET8: SETn1 Mask          */
+#define SCT_OUTPUTSET8_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET8: SETn2 Position      */
+#define SCT_OUTPUTSET8_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn2_Pos)                      /*!< SCT OUTPUTSET8: SETn2 Mask          */
+#define SCT_OUTPUTSET8_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET8: SETn3 Position      */
+#define SCT_OUTPUTSET8_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn3_Pos)                      /*!< SCT OUTPUTSET8: SETn3 Mask          */
+#define SCT_OUTPUTSET8_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET8: SETn4 Position      */
+#define SCT_OUTPUTSET8_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn4_Pos)                      /*!< SCT OUTPUTSET8: SETn4 Mask          */
+#define SCT_OUTPUTSET8_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET8: SETn5 Position      */
+#define SCT_OUTPUTSET8_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn5_Pos)                      /*!< SCT OUTPUTSET8: SETn5 Mask          */
+#define SCT_OUTPUTSET8_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET8: SETn6 Position      */
+#define SCT_OUTPUTSET8_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn6_Pos)                      /*!< SCT OUTPUTSET8: SETn6 Mask          */
+#define SCT_OUTPUTSET8_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET8: SETn7 Position      */
+#define SCT_OUTPUTSET8_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn7_Pos)                      /*!< SCT OUTPUTSET8: SETn7 Mask          */
+#define SCT_OUTPUTSET8_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET8: SETn8 Position      */
+#define SCT_OUTPUTSET8_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn8_Pos)                      /*!< SCT OUTPUTSET8: SETn8 Mask          */
+#define SCT_OUTPUTSET8_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET8: SETn9 Position      */
+#define SCT_OUTPUTSET8_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn9_Pos)                      /*!< SCT OUTPUTSET8: SETn9 Mask          */
+#define SCT_OUTPUTSET8_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET8: SETn10 Position     */
+#define SCT_OUTPUTSET8_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn10_Pos)                     /*!< SCT OUTPUTSET8: SETn10 Mask         */
+#define SCT_OUTPUTSET8_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET8: SETn11 Position     */
+#define SCT_OUTPUTSET8_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn11_Pos)                     /*!< SCT OUTPUTSET8: SETn11 Mask         */
+#define SCT_OUTPUTSET8_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET8: SETn12 Position     */
+#define SCT_OUTPUTSET8_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn12_Pos)                     /*!< SCT OUTPUTSET8: SETn12 Mask         */
+#define SCT_OUTPUTSET8_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET8: SETn13 Position     */
+#define SCT_OUTPUTSET8_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn13_Pos)                     /*!< SCT OUTPUTSET8: SETn13 Mask         */
+#define SCT_OUTPUTSET8_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET8: SETn14 Position     */
+#define SCT_OUTPUTSET8_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn14_Pos)                     /*!< SCT OUTPUTSET8: SETn14 Mask         */
+#define SCT_OUTPUTSET8_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET8: SETn15 Position     */
+#define SCT_OUTPUTSET8_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn15_Pos)                     /*!< SCT OUTPUTSET8: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR8  -----------------------------------------
+#define SCT_OUTPUTCLR8_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR8: CLRn0 Position      */
+#define SCT_OUTPUTCLR8_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos)                      /*!< SCT OUTPUTCLR8: CLRn0 Mask          */
+#define SCT_OUTPUTCLR8_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR8: CLRn1 Position      */
+#define SCT_OUTPUTCLR8_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos)                      /*!< SCT OUTPUTCLR8: CLRn1 Mask          */
+#define SCT_OUTPUTCLR8_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR8: CLRn2 Position      */
+#define SCT_OUTPUTCLR8_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos)                      /*!< SCT OUTPUTCLR8: CLRn2 Mask          */
+#define SCT_OUTPUTCLR8_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR8: CLRn3 Position      */
+#define SCT_OUTPUTCLR8_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos)                      /*!< SCT OUTPUTCLR8: CLRn3 Mask          */
+#define SCT_OUTPUTCLR8_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR8: CLRn4 Position      */
+#define SCT_OUTPUTCLR8_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos)                      /*!< SCT OUTPUTCLR8: CLRn4 Mask          */
+#define SCT_OUTPUTCLR8_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR8: CLRn5 Position      */
+#define SCT_OUTPUTCLR8_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos)                      /*!< SCT OUTPUTCLR8: CLRn5 Mask          */
+#define SCT_OUTPUTCLR8_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR8: CLRn6 Position      */
+#define SCT_OUTPUTCLR8_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos)                      /*!< SCT OUTPUTCLR8: CLRn6 Mask          */
+#define SCT_OUTPUTCLR8_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR8: CLRn7 Position      */
+#define SCT_OUTPUTCLR8_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos)                      /*!< SCT OUTPUTCLR8: CLRn7 Mask          */
+#define SCT_OUTPUTCLR8_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR8: CLRn8 Position      */
+#define SCT_OUTPUTCLR8_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos)                      /*!< SCT OUTPUTCLR8: CLRn8 Mask          */
+#define SCT_OUTPUTCLR8_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR8: CLRn9 Position      */
+#define SCT_OUTPUTCLR8_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos)                      /*!< SCT OUTPUTCLR8: CLRn9 Mask          */
+#define SCT_OUTPUTCLR8_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR8: CLRn10 Position     */
+#define SCT_OUTPUTCLR8_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos)                     /*!< SCT OUTPUTCLR8: CLRn10 Mask         */
+#define SCT_OUTPUTCLR8_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR8: CLRn11 Position     */
+#define SCT_OUTPUTCLR8_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos)                     /*!< SCT OUTPUTCLR8: CLRn11 Mask         */
+#define SCT_OUTPUTCLR8_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR8: CLRn12 Position     */
+#define SCT_OUTPUTCLR8_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos)                     /*!< SCT OUTPUTCLR8: CLRn12 Mask         */
+#define SCT_OUTPUTCLR8_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR8: CLRn13 Position     */
+#define SCT_OUTPUTCLR8_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos)                     /*!< SCT OUTPUTCLR8: CLRn13 Mask         */
+#define SCT_OUTPUTCLR8_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR8: CLRn14 Position     */
+#define SCT_OUTPUTCLR8_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos)                     /*!< SCT OUTPUTCLR8: CLRn14 Mask         */
+#define SCT_OUTPUTCLR8_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR8: CLRn15 Position     */
+#define SCT_OUTPUTCLR8_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos)                     /*!< SCT OUTPUTCLR8: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET9  -----------------------------------------
+#define SCT_OUTPUTSET9_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET9: SETn0 Position      */
+#define SCT_OUTPUTSET9_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn0_Pos)                      /*!< SCT OUTPUTSET9: SETn0 Mask          */
+#define SCT_OUTPUTSET9_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET9: SETn1 Position      */
+#define SCT_OUTPUTSET9_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn1_Pos)                      /*!< SCT OUTPUTSET9: SETn1 Mask          */
+#define SCT_OUTPUTSET9_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET9: SETn2 Position      */
+#define SCT_OUTPUTSET9_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn2_Pos)                      /*!< SCT OUTPUTSET9: SETn2 Mask          */
+#define SCT_OUTPUTSET9_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET9: SETn3 Position      */
+#define SCT_OUTPUTSET9_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn3_Pos)                      /*!< SCT OUTPUTSET9: SETn3 Mask          */
+#define SCT_OUTPUTSET9_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET9: SETn4 Position      */
+#define SCT_OUTPUTSET9_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn4_Pos)                      /*!< SCT OUTPUTSET9: SETn4 Mask          */
+#define SCT_OUTPUTSET9_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET9: SETn5 Position      */
+#define SCT_OUTPUTSET9_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn5_Pos)                      /*!< SCT OUTPUTSET9: SETn5 Mask          */
+#define SCT_OUTPUTSET9_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET9: SETn6 Position      */
+#define SCT_OUTPUTSET9_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn6_Pos)                      /*!< SCT OUTPUTSET9: SETn6 Mask          */
+#define SCT_OUTPUTSET9_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET9: SETn7 Position      */
+#define SCT_OUTPUTSET9_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn7_Pos)                      /*!< SCT OUTPUTSET9: SETn7 Mask          */
+#define SCT_OUTPUTSET9_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET9: SETn8 Position      */
+#define SCT_OUTPUTSET9_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn8_Pos)                      /*!< SCT OUTPUTSET9: SETn8 Mask          */
+#define SCT_OUTPUTSET9_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET9: SETn9 Position      */
+#define SCT_OUTPUTSET9_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn9_Pos)                      /*!< SCT OUTPUTSET9: SETn9 Mask          */
+#define SCT_OUTPUTSET9_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET9: SETn10 Position     */
+#define SCT_OUTPUTSET9_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn10_Pos)                     /*!< SCT OUTPUTSET9: SETn10 Mask         */
+#define SCT_OUTPUTSET9_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET9: SETn11 Position     */
+#define SCT_OUTPUTSET9_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn11_Pos)                     /*!< SCT OUTPUTSET9: SETn11 Mask         */
+#define SCT_OUTPUTSET9_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET9: SETn12 Position     */
+#define SCT_OUTPUTSET9_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn12_Pos)                     /*!< SCT OUTPUTSET9: SETn12 Mask         */
+#define SCT_OUTPUTSET9_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET9: SETn13 Position     */
+#define SCT_OUTPUTSET9_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn13_Pos)                     /*!< SCT OUTPUTSET9: SETn13 Mask         */
+#define SCT_OUTPUTSET9_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET9: SETn14 Position     */
+#define SCT_OUTPUTSET9_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn14_Pos)                     /*!< SCT OUTPUTSET9: SETn14 Mask         */
+#define SCT_OUTPUTSET9_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET9: SETn15 Position     */
+#define SCT_OUTPUTSET9_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn15_Pos)                     /*!< SCT OUTPUTSET9: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR9  -----------------------------------------
+#define SCT_OUTPUTCLR9_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR9: CLRn0 Position      */
+#define SCT_OUTPUTCLR9_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos)                      /*!< SCT OUTPUTCLR9: CLRn0 Mask          */
+#define SCT_OUTPUTCLR9_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR9: CLRn1 Position      */
+#define SCT_OUTPUTCLR9_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos)                      /*!< SCT OUTPUTCLR9: CLRn1 Mask          */
+#define SCT_OUTPUTCLR9_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR9: CLRn2 Position      */
+#define SCT_OUTPUTCLR9_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos)                      /*!< SCT OUTPUTCLR9: CLRn2 Mask          */
+#define SCT_OUTPUTCLR9_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR9: CLRn3 Position      */
+#define SCT_OUTPUTCLR9_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos)                      /*!< SCT OUTPUTCLR9: CLRn3 Mask          */
+#define SCT_OUTPUTCLR9_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR9: CLRn4 Position      */
+#define SCT_OUTPUTCLR9_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos)                      /*!< SCT OUTPUTCLR9: CLRn4 Mask          */
+#define SCT_OUTPUTCLR9_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR9: CLRn5 Position      */
+#define SCT_OUTPUTCLR9_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos)                      /*!< SCT OUTPUTCLR9: CLRn5 Mask          */
+#define SCT_OUTPUTCLR9_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR9: CLRn6 Position      */
+#define SCT_OUTPUTCLR9_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos)                      /*!< SCT OUTPUTCLR9: CLRn6 Mask          */
+#define SCT_OUTPUTCLR9_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR9: CLRn7 Position      */
+#define SCT_OUTPUTCLR9_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos)                      /*!< SCT OUTPUTCLR9: CLRn7 Mask          */
+#define SCT_OUTPUTCLR9_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR9: CLRn8 Position      */
+#define SCT_OUTPUTCLR9_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos)                      /*!< SCT OUTPUTCLR9: CLRn8 Mask          */
+#define SCT_OUTPUTCLR9_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR9: CLRn9 Position      */
+#define SCT_OUTPUTCLR9_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos)                      /*!< SCT OUTPUTCLR9: CLRn9 Mask          */
+#define SCT_OUTPUTCLR9_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR9: CLRn10 Position     */
+#define SCT_OUTPUTCLR9_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos)                     /*!< SCT OUTPUTCLR9: CLRn10 Mask         */
+#define SCT_OUTPUTCLR9_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR9: CLRn11 Position     */
+#define SCT_OUTPUTCLR9_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos)                     /*!< SCT OUTPUTCLR9: CLRn11 Mask         */
+#define SCT_OUTPUTCLR9_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR9: CLRn12 Position     */
+#define SCT_OUTPUTCLR9_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos)                     /*!< SCT OUTPUTCLR9: CLRn12 Mask         */
+#define SCT_OUTPUTCLR9_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR9: CLRn13 Position     */
+#define SCT_OUTPUTCLR9_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos)                     /*!< SCT OUTPUTCLR9: CLRn13 Mask         */
+#define SCT_OUTPUTCLR9_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR9: CLRn14 Position     */
+#define SCT_OUTPUTCLR9_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos)                     /*!< SCT OUTPUTCLR9: CLRn14 Mask         */
+#define SCT_OUTPUTCLR9_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR9: CLRn15 Position     */
+#define SCT_OUTPUTCLR9_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos)                     /*!< SCT OUTPUTCLR9: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET10  ----------------------------------------
+#define SCT_OUTPUTSET10_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET10: SETn0 Position     */
+#define SCT_OUTPUTSET10_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn0_Pos)                     /*!< SCT OUTPUTSET10: SETn0 Mask         */
+#define SCT_OUTPUTSET10_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET10: SETn1 Position     */
+#define SCT_OUTPUTSET10_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn1_Pos)                     /*!< SCT OUTPUTSET10: SETn1 Mask         */
+#define SCT_OUTPUTSET10_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET10: SETn2 Position     */
+#define SCT_OUTPUTSET10_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn2_Pos)                     /*!< SCT OUTPUTSET10: SETn2 Mask         */
+#define SCT_OUTPUTSET10_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET10: SETn3 Position     */
+#define SCT_OUTPUTSET10_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn3_Pos)                     /*!< SCT OUTPUTSET10: SETn3 Mask         */
+#define SCT_OUTPUTSET10_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET10: SETn4 Position     */
+#define SCT_OUTPUTSET10_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn4_Pos)                     /*!< SCT OUTPUTSET10: SETn4 Mask         */
+#define SCT_OUTPUTSET10_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET10: SETn5 Position     */
+#define SCT_OUTPUTSET10_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn5_Pos)                     /*!< SCT OUTPUTSET10: SETn5 Mask         */
+#define SCT_OUTPUTSET10_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET10: SETn6 Position     */
+#define SCT_OUTPUTSET10_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn6_Pos)                     /*!< SCT OUTPUTSET10: SETn6 Mask         */
+#define SCT_OUTPUTSET10_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET10: SETn7 Position     */
+#define SCT_OUTPUTSET10_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn7_Pos)                     /*!< SCT OUTPUTSET10: SETn7 Mask         */
+#define SCT_OUTPUTSET10_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET10: SETn8 Position     */
+#define SCT_OUTPUTSET10_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn8_Pos)                     /*!< SCT OUTPUTSET10: SETn8 Mask         */
+#define SCT_OUTPUTSET10_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET10: SETn9 Position     */
+#define SCT_OUTPUTSET10_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn9_Pos)                     /*!< SCT OUTPUTSET10: SETn9 Mask         */
+#define SCT_OUTPUTSET10_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET10: SETn10 Position    */
+#define SCT_OUTPUTSET10_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn10_Pos)                    /*!< SCT OUTPUTSET10: SETn10 Mask        */
+#define SCT_OUTPUTSET10_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET10: SETn11 Position    */
+#define SCT_OUTPUTSET10_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn11_Pos)                    /*!< SCT OUTPUTSET10: SETn11 Mask        */
+#define SCT_OUTPUTSET10_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET10: SETn12 Position    */
+#define SCT_OUTPUTSET10_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn12_Pos)                    /*!< SCT OUTPUTSET10: SETn12 Mask        */
+#define SCT_OUTPUTSET10_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET10: SETn13 Position    */
+#define SCT_OUTPUTSET10_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn13_Pos)                    /*!< SCT OUTPUTSET10: SETn13 Mask        */
+#define SCT_OUTPUTSET10_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET10: SETn14 Position    */
+#define SCT_OUTPUTSET10_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn14_Pos)                    /*!< SCT OUTPUTSET10: SETn14 Mask        */
+#define SCT_OUTPUTSET10_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET10: SETn15 Position    */
+#define SCT_OUTPUTSET10_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn15_Pos)                    /*!< SCT OUTPUTSET10: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR10  ----------------------------------------
+#define SCT_OUTPUTCLR10_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR10: CLRn0 Position     */
+#define SCT_OUTPUTCLR10_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos)                     /*!< SCT OUTPUTCLR10: CLRn0 Mask         */
+#define SCT_OUTPUTCLR10_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR10: CLRn1 Position     */
+#define SCT_OUTPUTCLR10_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos)                     /*!< SCT OUTPUTCLR10: CLRn1 Mask         */
+#define SCT_OUTPUTCLR10_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR10: CLRn2 Position     */
+#define SCT_OUTPUTCLR10_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos)                     /*!< SCT OUTPUTCLR10: CLRn2 Mask         */
+#define SCT_OUTPUTCLR10_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR10: CLRn3 Position     */
+#define SCT_OUTPUTCLR10_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos)                     /*!< SCT OUTPUTCLR10: CLRn3 Mask         */
+#define SCT_OUTPUTCLR10_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR10: CLRn4 Position     */
+#define SCT_OUTPUTCLR10_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos)                     /*!< SCT OUTPUTCLR10: CLRn4 Mask         */
+#define SCT_OUTPUTCLR10_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR10: CLRn5 Position     */
+#define SCT_OUTPUTCLR10_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos)                     /*!< SCT OUTPUTCLR10: CLRn5 Mask         */
+#define SCT_OUTPUTCLR10_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR10: CLRn6 Position     */
+#define SCT_OUTPUTCLR10_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos)                     /*!< SCT OUTPUTCLR10: CLRn6 Mask         */
+#define SCT_OUTPUTCLR10_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR10: CLRn7 Position     */
+#define SCT_OUTPUTCLR10_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos)                     /*!< SCT OUTPUTCLR10: CLRn7 Mask         */
+#define SCT_OUTPUTCLR10_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR10: CLRn8 Position     */
+#define SCT_OUTPUTCLR10_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos)                     /*!< SCT OUTPUTCLR10: CLRn8 Mask         */
+#define SCT_OUTPUTCLR10_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR10: CLRn9 Position     */
+#define SCT_OUTPUTCLR10_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos)                     /*!< SCT OUTPUTCLR10: CLRn9 Mask         */
+#define SCT_OUTPUTCLR10_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR10: CLRn10 Position    */
+#define SCT_OUTPUTCLR10_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos)                    /*!< SCT OUTPUTCLR10: CLRn10 Mask        */
+#define SCT_OUTPUTCLR10_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR10: CLRn11 Position    */
+#define SCT_OUTPUTCLR10_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos)                    /*!< SCT OUTPUTCLR10: CLRn11 Mask        */
+#define SCT_OUTPUTCLR10_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR10: CLRn12 Position    */
+#define SCT_OUTPUTCLR10_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos)                    /*!< SCT OUTPUTCLR10: CLRn12 Mask        */
+#define SCT_OUTPUTCLR10_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR10: CLRn13 Position    */
+#define SCT_OUTPUTCLR10_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos)                    /*!< SCT OUTPUTCLR10: CLRn13 Mask        */
+#define SCT_OUTPUTCLR10_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR10: CLRn14 Position    */
+#define SCT_OUTPUTCLR10_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos)                    /*!< SCT OUTPUTCLR10: CLRn14 Mask        */
+#define SCT_OUTPUTCLR10_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR10: CLRn15 Position    */
+#define SCT_OUTPUTCLR10_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos)                    /*!< SCT OUTPUTCLR10: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET11  ----------------------------------------
+#define SCT_OUTPUTSET11_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET11: SETn0 Position     */
+#define SCT_OUTPUTSET11_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn0_Pos)                     /*!< SCT OUTPUTSET11: SETn0 Mask         */
+#define SCT_OUTPUTSET11_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET11: SETn1 Position     */
+#define SCT_OUTPUTSET11_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn1_Pos)                     /*!< SCT OUTPUTSET11: SETn1 Mask         */
+#define SCT_OUTPUTSET11_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET11: SETn2 Position     */
+#define SCT_OUTPUTSET11_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn2_Pos)                     /*!< SCT OUTPUTSET11: SETn2 Mask         */
+#define SCT_OUTPUTSET11_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET11: SETn3 Position     */
+#define SCT_OUTPUTSET11_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn3_Pos)                     /*!< SCT OUTPUTSET11: SETn3 Mask         */
+#define SCT_OUTPUTSET11_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET11: SETn4 Position     */
+#define SCT_OUTPUTSET11_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn4_Pos)                     /*!< SCT OUTPUTSET11: SETn4 Mask         */
+#define SCT_OUTPUTSET11_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET11: SETn5 Position     */
+#define SCT_OUTPUTSET11_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn5_Pos)                     /*!< SCT OUTPUTSET11: SETn5 Mask         */
+#define SCT_OUTPUTSET11_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET11: SETn6 Position     */
+#define SCT_OUTPUTSET11_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn6_Pos)                     /*!< SCT OUTPUTSET11: SETn6 Mask         */
+#define SCT_OUTPUTSET11_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET11: SETn7 Position     */
+#define SCT_OUTPUTSET11_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn7_Pos)                     /*!< SCT OUTPUTSET11: SETn7 Mask         */
+#define SCT_OUTPUTSET11_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET11: SETn8 Position     */
+#define SCT_OUTPUTSET11_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn8_Pos)                     /*!< SCT OUTPUTSET11: SETn8 Mask         */
+#define SCT_OUTPUTSET11_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET11: SETn9 Position     */
+#define SCT_OUTPUTSET11_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn9_Pos)                     /*!< SCT OUTPUTSET11: SETn9 Mask         */
+#define SCT_OUTPUTSET11_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET11: SETn10 Position    */
+#define SCT_OUTPUTSET11_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn10_Pos)                    /*!< SCT OUTPUTSET11: SETn10 Mask        */
+#define SCT_OUTPUTSET11_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET11: SETn11 Position    */
+#define SCT_OUTPUTSET11_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn11_Pos)                    /*!< SCT OUTPUTSET11: SETn11 Mask        */
+#define SCT_OUTPUTSET11_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET11: SETn12 Position    */
+#define SCT_OUTPUTSET11_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn12_Pos)                    /*!< SCT OUTPUTSET11: SETn12 Mask        */
+#define SCT_OUTPUTSET11_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET11: SETn13 Position    */
+#define SCT_OUTPUTSET11_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn13_Pos)                    /*!< SCT OUTPUTSET11: SETn13 Mask        */
+#define SCT_OUTPUTSET11_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET11: SETn14 Position    */
+#define SCT_OUTPUTSET11_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn14_Pos)                    /*!< SCT OUTPUTSET11: SETn14 Mask        */
+#define SCT_OUTPUTSET11_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET11: SETn15 Position    */
+#define SCT_OUTPUTSET11_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn15_Pos)                    /*!< SCT OUTPUTSET11: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR11  ----------------------------------------
+#define SCT_OUTPUTCLR11_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR11: CLRn0 Position     */
+#define SCT_OUTPUTCLR11_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos)                     /*!< SCT OUTPUTCLR11: CLRn0 Mask         */
+#define SCT_OUTPUTCLR11_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR11: CLRn1 Position     */
+#define SCT_OUTPUTCLR11_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos)                     /*!< SCT OUTPUTCLR11: CLRn1 Mask         */
+#define SCT_OUTPUTCLR11_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR11: CLRn2 Position     */
+#define SCT_OUTPUTCLR11_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos)                     /*!< SCT OUTPUTCLR11: CLRn2 Mask         */
+#define SCT_OUTPUTCLR11_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR11: CLRn3 Position     */
+#define SCT_OUTPUTCLR11_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos)                     /*!< SCT OUTPUTCLR11: CLRn3 Mask         */
+#define SCT_OUTPUTCLR11_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR11: CLRn4 Position     */
+#define SCT_OUTPUTCLR11_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos)                     /*!< SCT OUTPUTCLR11: CLRn4 Mask         */
+#define SCT_OUTPUTCLR11_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR11: CLRn5 Position     */
+#define SCT_OUTPUTCLR11_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos)                     /*!< SCT OUTPUTCLR11: CLRn5 Mask         */
+#define SCT_OUTPUTCLR11_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR11: CLRn6 Position     */
+#define SCT_OUTPUTCLR11_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos)                     /*!< SCT OUTPUTCLR11: CLRn6 Mask         */
+#define SCT_OUTPUTCLR11_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR11: CLRn7 Position     */
+#define SCT_OUTPUTCLR11_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos)                     /*!< SCT OUTPUTCLR11: CLRn7 Mask         */
+#define SCT_OUTPUTCLR11_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR11: CLRn8 Position     */
+#define SCT_OUTPUTCLR11_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos)                     /*!< SCT OUTPUTCLR11: CLRn8 Mask         */
+#define SCT_OUTPUTCLR11_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR11: CLRn9 Position     */
+#define SCT_OUTPUTCLR11_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos)                     /*!< SCT OUTPUTCLR11: CLRn9 Mask         */
+#define SCT_OUTPUTCLR11_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR11: CLRn10 Position    */
+#define SCT_OUTPUTCLR11_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos)                    /*!< SCT OUTPUTCLR11: CLRn10 Mask        */
+#define SCT_OUTPUTCLR11_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR11: CLRn11 Position    */
+#define SCT_OUTPUTCLR11_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos)                    /*!< SCT OUTPUTCLR11: CLRn11 Mask        */
+#define SCT_OUTPUTCLR11_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR11: CLRn12 Position    */
+#define SCT_OUTPUTCLR11_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos)                    /*!< SCT OUTPUTCLR11: CLRn12 Mask        */
+#define SCT_OUTPUTCLR11_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR11: CLRn13 Position    */
+#define SCT_OUTPUTCLR11_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos)                    /*!< SCT OUTPUTCLR11: CLRn13 Mask        */
+#define SCT_OUTPUTCLR11_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR11: CLRn14 Position    */
+#define SCT_OUTPUTCLR11_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos)                    /*!< SCT OUTPUTCLR11: CLRn14 Mask        */
+#define SCT_OUTPUTCLR11_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR11: CLRn15 Position    */
+#define SCT_OUTPUTCLR11_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos)                    /*!< SCT OUTPUTCLR11: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET12  ----------------------------------------
+#define SCT_OUTPUTSET12_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET12: SETn0 Position     */
+#define SCT_OUTPUTSET12_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn0_Pos)                     /*!< SCT OUTPUTSET12: SETn0 Mask         */
+#define SCT_OUTPUTSET12_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET12: SETn1 Position     */
+#define SCT_OUTPUTSET12_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn1_Pos)                     /*!< SCT OUTPUTSET12: SETn1 Mask         */
+#define SCT_OUTPUTSET12_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET12: SETn2 Position     */
+#define SCT_OUTPUTSET12_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn2_Pos)                     /*!< SCT OUTPUTSET12: SETn2 Mask         */
+#define SCT_OUTPUTSET12_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET12: SETn3 Position     */
+#define SCT_OUTPUTSET12_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn3_Pos)                     /*!< SCT OUTPUTSET12: SETn3 Mask         */
+#define SCT_OUTPUTSET12_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET12: SETn4 Position     */
+#define SCT_OUTPUTSET12_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn4_Pos)                     /*!< SCT OUTPUTSET12: SETn4 Mask         */
+#define SCT_OUTPUTSET12_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET12: SETn5 Position     */
+#define SCT_OUTPUTSET12_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn5_Pos)                     /*!< SCT OUTPUTSET12: SETn5 Mask         */
+#define SCT_OUTPUTSET12_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET12: SETn6 Position     */
+#define SCT_OUTPUTSET12_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn6_Pos)                     /*!< SCT OUTPUTSET12: SETn6 Mask         */
+#define SCT_OUTPUTSET12_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET12: SETn7 Position     */
+#define SCT_OUTPUTSET12_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn7_Pos)                     /*!< SCT OUTPUTSET12: SETn7 Mask         */
+#define SCT_OUTPUTSET12_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET12: SETn8 Position     */
+#define SCT_OUTPUTSET12_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn8_Pos)                     /*!< SCT OUTPUTSET12: SETn8 Mask         */
+#define SCT_OUTPUTSET12_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET12: SETn9 Position     */
+#define SCT_OUTPUTSET12_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn9_Pos)                     /*!< SCT OUTPUTSET12: SETn9 Mask         */
+#define SCT_OUTPUTSET12_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET12: SETn10 Position    */
+#define SCT_OUTPUTSET12_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn10_Pos)                    /*!< SCT OUTPUTSET12: SETn10 Mask        */
+#define SCT_OUTPUTSET12_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET12: SETn11 Position    */
+#define SCT_OUTPUTSET12_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn11_Pos)                    /*!< SCT OUTPUTSET12: SETn11 Mask        */
+#define SCT_OUTPUTSET12_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET12: SETn12 Position    */
+#define SCT_OUTPUTSET12_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn12_Pos)                    /*!< SCT OUTPUTSET12: SETn12 Mask        */
+#define SCT_OUTPUTSET12_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET12: SETn13 Position    */
+#define SCT_OUTPUTSET12_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn13_Pos)                    /*!< SCT OUTPUTSET12: SETn13 Mask        */
+#define SCT_OUTPUTSET12_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET12: SETn14 Position    */
+#define SCT_OUTPUTSET12_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn14_Pos)                    /*!< SCT OUTPUTSET12: SETn14 Mask        */
+#define SCT_OUTPUTSET12_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET12: SETn15 Position    */
+#define SCT_OUTPUTSET12_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn15_Pos)                    /*!< SCT OUTPUTSET12: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR12  ----------------------------------------
+#define SCT_OUTPUTCLR12_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR12: CLRn0 Position     */
+#define SCT_OUTPUTCLR12_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos)                     /*!< SCT OUTPUTCLR12: CLRn0 Mask         */
+#define SCT_OUTPUTCLR12_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR12: CLRn1 Position     */
+#define SCT_OUTPUTCLR12_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos)                     /*!< SCT OUTPUTCLR12: CLRn1 Mask         */
+#define SCT_OUTPUTCLR12_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR12: CLRn2 Position     */
+#define SCT_OUTPUTCLR12_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos)                     /*!< SCT OUTPUTCLR12: CLRn2 Mask         */
+#define SCT_OUTPUTCLR12_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR12: CLRn3 Position     */
+#define SCT_OUTPUTCLR12_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos)                     /*!< SCT OUTPUTCLR12: CLRn3 Mask         */
+#define SCT_OUTPUTCLR12_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR12: CLRn4 Position     */
+#define SCT_OUTPUTCLR12_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos)                     /*!< SCT OUTPUTCLR12: CLRn4 Mask         */
+#define SCT_OUTPUTCLR12_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR12: CLRn5 Position     */
+#define SCT_OUTPUTCLR12_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos)                     /*!< SCT OUTPUTCLR12: CLRn5 Mask         */
+#define SCT_OUTPUTCLR12_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR12: CLRn6 Position     */
+#define SCT_OUTPUTCLR12_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos)                     /*!< SCT OUTPUTCLR12: CLRn6 Mask         */
+#define SCT_OUTPUTCLR12_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR12: CLRn7 Position     */
+#define SCT_OUTPUTCLR12_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos)                     /*!< SCT OUTPUTCLR12: CLRn7 Mask         */
+#define SCT_OUTPUTCLR12_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR12: CLRn8 Position     */
+#define SCT_OUTPUTCLR12_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos)                     /*!< SCT OUTPUTCLR12: CLRn8 Mask         */
+#define SCT_OUTPUTCLR12_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR12: CLRn9 Position     */
+#define SCT_OUTPUTCLR12_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos)                     /*!< SCT OUTPUTCLR12: CLRn9 Mask         */
+#define SCT_OUTPUTCLR12_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR12: CLRn10 Position    */
+#define SCT_OUTPUTCLR12_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos)                    /*!< SCT OUTPUTCLR12: CLRn10 Mask        */
+#define SCT_OUTPUTCLR12_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR12: CLRn11 Position    */
+#define SCT_OUTPUTCLR12_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos)                    /*!< SCT OUTPUTCLR12: CLRn11 Mask        */
+#define SCT_OUTPUTCLR12_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR12: CLRn12 Position    */
+#define SCT_OUTPUTCLR12_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos)                    /*!< SCT OUTPUTCLR12: CLRn12 Mask        */
+#define SCT_OUTPUTCLR12_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR12: CLRn13 Position    */
+#define SCT_OUTPUTCLR12_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos)                    /*!< SCT OUTPUTCLR12: CLRn13 Mask        */
+#define SCT_OUTPUTCLR12_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR12: CLRn14 Position    */
+#define SCT_OUTPUTCLR12_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos)                    /*!< SCT OUTPUTCLR12: CLRn14 Mask        */
+#define SCT_OUTPUTCLR12_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR12: CLRn15 Position    */
+#define SCT_OUTPUTCLR12_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos)                    /*!< SCT OUTPUTCLR12: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET13  ----------------------------------------
+#define SCT_OUTPUTSET13_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET13: SETn0 Position     */
+#define SCT_OUTPUTSET13_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn0_Pos)                     /*!< SCT OUTPUTSET13: SETn0 Mask         */
+#define SCT_OUTPUTSET13_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET13: SETn1 Position     */
+#define SCT_OUTPUTSET13_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn1_Pos)                     /*!< SCT OUTPUTSET13: SETn1 Mask         */
+#define SCT_OUTPUTSET13_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET13: SETn2 Position     */
+#define SCT_OUTPUTSET13_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn2_Pos)                     /*!< SCT OUTPUTSET13: SETn2 Mask         */
+#define SCT_OUTPUTSET13_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET13: SETn3 Position     */
+#define SCT_OUTPUTSET13_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn3_Pos)                     /*!< SCT OUTPUTSET13: SETn3 Mask         */
+#define SCT_OUTPUTSET13_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET13: SETn4 Position     */
+#define SCT_OUTPUTSET13_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn4_Pos)                     /*!< SCT OUTPUTSET13: SETn4 Mask         */
+#define SCT_OUTPUTSET13_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET13: SETn5 Position     */
+#define SCT_OUTPUTSET13_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn5_Pos)                     /*!< SCT OUTPUTSET13: SETn5 Mask         */
+#define SCT_OUTPUTSET13_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET13: SETn6 Position     */
+#define SCT_OUTPUTSET13_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn6_Pos)                     /*!< SCT OUTPUTSET13: SETn6 Mask         */
+#define SCT_OUTPUTSET13_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET13: SETn7 Position     */
+#define SCT_OUTPUTSET13_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn7_Pos)                     /*!< SCT OUTPUTSET13: SETn7 Mask         */
+#define SCT_OUTPUTSET13_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET13: SETn8 Position     */
+#define SCT_OUTPUTSET13_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn8_Pos)                     /*!< SCT OUTPUTSET13: SETn8 Mask         */
+#define SCT_OUTPUTSET13_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET13: SETn9 Position     */
+#define SCT_OUTPUTSET13_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn9_Pos)                     /*!< SCT OUTPUTSET13: SETn9 Mask         */
+#define SCT_OUTPUTSET13_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET13: SETn10 Position    */
+#define SCT_OUTPUTSET13_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn10_Pos)                    /*!< SCT OUTPUTSET13: SETn10 Mask        */
+#define SCT_OUTPUTSET13_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET13: SETn11 Position    */
+#define SCT_OUTPUTSET13_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn11_Pos)                    /*!< SCT OUTPUTSET13: SETn11 Mask        */
+#define SCT_OUTPUTSET13_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET13: SETn12 Position    */
+#define SCT_OUTPUTSET13_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn12_Pos)                    /*!< SCT OUTPUTSET13: SETn12 Mask        */
+#define SCT_OUTPUTSET13_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET13: SETn13 Position    */
+#define SCT_OUTPUTSET13_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn13_Pos)                    /*!< SCT OUTPUTSET13: SETn13 Mask        */
+#define SCT_OUTPUTSET13_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET13: SETn14 Position    */
+#define SCT_OUTPUTSET13_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn14_Pos)                    /*!< SCT OUTPUTSET13: SETn14 Mask        */
+#define SCT_OUTPUTSET13_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET13: SETn15 Position    */
+#define SCT_OUTPUTSET13_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn15_Pos)                    /*!< SCT OUTPUTSET13: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR13  ----------------------------------------
+#define SCT_OUTPUTCLR13_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR13: CLRn0 Position     */
+#define SCT_OUTPUTCLR13_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos)                     /*!< SCT OUTPUTCLR13: CLRn0 Mask         */
+#define SCT_OUTPUTCLR13_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR13: CLRn1 Position     */
+#define SCT_OUTPUTCLR13_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos)                     /*!< SCT OUTPUTCLR13: CLRn1 Mask         */
+#define SCT_OUTPUTCLR13_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR13: CLRn2 Position     */
+#define SCT_OUTPUTCLR13_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos)                     /*!< SCT OUTPUTCLR13: CLRn2 Mask         */
+#define SCT_OUTPUTCLR13_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR13: CLRn3 Position     */
+#define SCT_OUTPUTCLR13_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos)                     /*!< SCT OUTPUTCLR13: CLRn3 Mask         */
+#define SCT_OUTPUTCLR13_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR13: CLRn4 Position     */
+#define SCT_OUTPUTCLR13_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos)                     /*!< SCT OUTPUTCLR13: CLRn4 Mask         */
+#define SCT_OUTPUTCLR13_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR13: CLRn5 Position     */
+#define SCT_OUTPUTCLR13_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos)                     /*!< SCT OUTPUTCLR13: CLRn5 Mask         */
+#define SCT_OUTPUTCLR13_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR13: CLRn6 Position     */
+#define SCT_OUTPUTCLR13_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos)                     /*!< SCT OUTPUTCLR13: CLRn6 Mask         */
+#define SCT_OUTPUTCLR13_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR13: CLRn7 Position     */
+#define SCT_OUTPUTCLR13_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos)                     /*!< SCT OUTPUTCLR13: CLRn7 Mask         */
+#define SCT_OUTPUTCLR13_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR13: CLRn8 Position     */
+#define SCT_OUTPUTCLR13_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos)                     /*!< SCT OUTPUTCLR13: CLRn8 Mask         */
+#define SCT_OUTPUTCLR13_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR13: CLRn9 Position     */
+#define SCT_OUTPUTCLR13_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos)                     /*!< SCT OUTPUTCLR13: CLRn9 Mask         */
+#define SCT_OUTPUTCLR13_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR13: CLRn10 Position    */
+#define SCT_OUTPUTCLR13_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos)                    /*!< SCT OUTPUTCLR13: CLRn10 Mask        */
+#define SCT_OUTPUTCLR13_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR13: CLRn11 Position    */
+#define SCT_OUTPUTCLR13_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos)                    /*!< SCT OUTPUTCLR13: CLRn11 Mask        */
+#define SCT_OUTPUTCLR13_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR13: CLRn12 Position    */
+#define SCT_OUTPUTCLR13_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos)                    /*!< SCT OUTPUTCLR13: CLRn12 Mask        */
+#define SCT_OUTPUTCLR13_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR13: CLRn13 Position    */
+#define SCT_OUTPUTCLR13_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos)                    /*!< SCT OUTPUTCLR13: CLRn13 Mask        */
+#define SCT_OUTPUTCLR13_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR13: CLRn14 Position    */
+#define SCT_OUTPUTCLR13_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos)                    /*!< SCT OUTPUTCLR13: CLRn14 Mask        */
+#define SCT_OUTPUTCLR13_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR13: CLRn15 Position    */
+#define SCT_OUTPUTCLR13_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos)                    /*!< SCT OUTPUTCLR13: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET14  ----------------------------------------
+#define SCT_OUTPUTSET14_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET14: SETn0 Position     */
+#define SCT_OUTPUTSET14_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn0_Pos)                     /*!< SCT OUTPUTSET14: SETn0 Mask         */
+#define SCT_OUTPUTSET14_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET14: SETn1 Position     */
+#define SCT_OUTPUTSET14_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn1_Pos)                     /*!< SCT OUTPUTSET14: SETn1 Mask         */
+#define SCT_OUTPUTSET14_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET14: SETn2 Position     */
+#define SCT_OUTPUTSET14_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn2_Pos)                     /*!< SCT OUTPUTSET14: SETn2 Mask         */
+#define SCT_OUTPUTSET14_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET14: SETn3 Position     */
+#define SCT_OUTPUTSET14_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn3_Pos)                     /*!< SCT OUTPUTSET14: SETn3 Mask         */
+#define SCT_OUTPUTSET14_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET14: SETn4 Position     */
+#define SCT_OUTPUTSET14_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn4_Pos)                     /*!< SCT OUTPUTSET14: SETn4 Mask         */
+#define SCT_OUTPUTSET14_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET14: SETn5 Position     */
+#define SCT_OUTPUTSET14_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn5_Pos)                     /*!< SCT OUTPUTSET14: SETn5 Mask         */
+#define SCT_OUTPUTSET14_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET14: SETn6 Position     */
+#define SCT_OUTPUTSET14_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn6_Pos)                     /*!< SCT OUTPUTSET14: SETn6 Mask         */
+#define SCT_OUTPUTSET14_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET14: SETn7 Position     */
+#define SCT_OUTPUTSET14_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn7_Pos)                     /*!< SCT OUTPUTSET14: SETn7 Mask         */
+#define SCT_OUTPUTSET14_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET14: SETn8 Position     */
+#define SCT_OUTPUTSET14_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn8_Pos)                     /*!< SCT OUTPUTSET14: SETn8 Mask         */
+#define SCT_OUTPUTSET14_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET14: SETn9 Position     */
+#define SCT_OUTPUTSET14_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn9_Pos)                     /*!< SCT OUTPUTSET14: SETn9 Mask         */
+#define SCT_OUTPUTSET14_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET14: SETn10 Position    */
+#define SCT_OUTPUTSET14_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn10_Pos)                    /*!< SCT OUTPUTSET14: SETn10 Mask        */
+#define SCT_OUTPUTSET14_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET14: SETn11 Position    */
+#define SCT_OUTPUTSET14_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn11_Pos)                    /*!< SCT OUTPUTSET14: SETn11 Mask        */
+#define SCT_OUTPUTSET14_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET14: SETn12 Position    */
+#define SCT_OUTPUTSET14_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn12_Pos)                    /*!< SCT OUTPUTSET14: SETn12 Mask        */
+#define SCT_OUTPUTSET14_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET14: SETn13 Position    */
+#define SCT_OUTPUTSET14_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn13_Pos)                    /*!< SCT OUTPUTSET14: SETn13 Mask        */
+#define SCT_OUTPUTSET14_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET14: SETn14 Position    */
+#define SCT_OUTPUTSET14_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn14_Pos)                    /*!< SCT OUTPUTSET14: SETn14 Mask        */
+#define SCT_OUTPUTSET14_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET14: SETn15 Position    */
+#define SCT_OUTPUTSET14_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn15_Pos)                    /*!< SCT OUTPUTSET14: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR14  ----------------------------------------
+#define SCT_OUTPUTCLR14_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR14: CLRn0 Position     */
+#define SCT_OUTPUTCLR14_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos)                     /*!< SCT OUTPUTCLR14: CLRn0 Mask         */
+#define SCT_OUTPUTCLR14_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR14: CLRn1 Position     */
+#define SCT_OUTPUTCLR14_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos)                     /*!< SCT OUTPUTCLR14: CLRn1 Mask         */
+#define SCT_OUTPUTCLR14_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR14: CLRn2 Position     */
+#define SCT_OUTPUTCLR14_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos)                     /*!< SCT OUTPUTCLR14: CLRn2 Mask         */
+#define SCT_OUTPUTCLR14_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR14: CLRn3 Position     */
+#define SCT_OUTPUTCLR14_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos)                     /*!< SCT OUTPUTCLR14: CLRn3 Mask         */
+#define SCT_OUTPUTCLR14_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR14: CLRn4 Position     */
+#define SCT_OUTPUTCLR14_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos)                     /*!< SCT OUTPUTCLR14: CLRn4 Mask         */
+#define SCT_OUTPUTCLR14_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR14: CLRn5 Position     */
+#define SCT_OUTPUTCLR14_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos)                     /*!< SCT OUTPUTCLR14: CLRn5 Mask         */
+#define SCT_OUTPUTCLR14_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR14: CLRn6 Position     */
+#define SCT_OUTPUTCLR14_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos)                     /*!< SCT OUTPUTCLR14: CLRn6 Mask         */
+#define SCT_OUTPUTCLR14_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR14: CLRn7 Position     */
+#define SCT_OUTPUTCLR14_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos)                     /*!< SCT OUTPUTCLR14: CLRn7 Mask         */
+#define SCT_OUTPUTCLR14_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR14: CLRn8 Position     */
+#define SCT_OUTPUTCLR14_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos)                     /*!< SCT OUTPUTCLR14: CLRn8 Mask         */
+#define SCT_OUTPUTCLR14_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR14: CLRn9 Position     */
+#define SCT_OUTPUTCLR14_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos)                     /*!< SCT OUTPUTCLR14: CLRn9 Mask         */
+#define SCT_OUTPUTCLR14_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR14: CLRn10 Position    */
+#define SCT_OUTPUTCLR14_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos)                    /*!< SCT OUTPUTCLR14: CLRn10 Mask        */
+#define SCT_OUTPUTCLR14_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR14: CLRn11 Position    */
+#define SCT_OUTPUTCLR14_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos)                    /*!< SCT OUTPUTCLR14: CLRn11 Mask        */
+#define SCT_OUTPUTCLR14_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR14: CLRn12 Position    */
+#define SCT_OUTPUTCLR14_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos)                    /*!< SCT OUTPUTCLR14: CLRn12 Mask        */
+#define SCT_OUTPUTCLR14_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR14: CLRn13 Position    */
+#define SCT_OUTPUTCLR14_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos)                    /*!< SCT OUTPUTCLR14: CLRn13 Mask        */
+#define SCT_OUTPUTCLR14_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR14: CLRn14 Position    */
+#define SCT_OUTPUTCLR14_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos)                    /*!< SCT OUTPUTCLR14: CLRn14 Mask        */
+#define SCT_OUTPUTCLR14_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR14: CLRn15 Position    */
+#define SCT_OUTPUTCLR14_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos)                    /*!< SCT OUTPUTCLR14: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET15  ----------------------------------------
+#define SCT_OUTPUTSET15_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET15: SETn0 Position     */
+#define SCT_OUTPUTSET15_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn0_Pos)                     /*!< SCT OUTPUTSET15: SETn0 Mask         */
+#define SCT_OUTPUTSET15_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET15: SETn1 Position     */
+#define SCT_OUTPUTSET15_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn1_Pos)                     /*!< SCT OUTPUTSET15: SETn1 Mask         */
+#define SCT_OUTPUTSET15_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET15: SETn2 Position     */
+#define SCT_OUTPUTSET15_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn2_Pos)                     /*!< SCT OUTPUTSET15: SETn2 Mask         */
+#define SCT_OUTPUTSET15_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET15: SETn3 Position     */
+#define SCT_OUTPUTSET15_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn3_Pos)                     /*!< SCT OUTPUTSET15: SETn3 Mask         */
+#define SCT_OUTPUTSET15_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET15: SETn4 Position     */
+#define SCT_OUTPUTSET15_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn4_Pos)                     /*!< SCT OUTPUTSET15: SETn4 Mask         */
+#define SCT_OUTPUTSET15_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET15: SETn5 Position     */
+#define SCT_OUTPUTSET15_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn5_Pos)                     /*!< SCT OUTPUTSET15: SETn5 Mask         */
+#define SCT_OUTPUTSET15_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET15: SETn6 Position     */
+#define SCT_OUTPUTSET15_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn6_Pos)                     /*!< SCT OUTPUTSET15: SETn6 Mask         */
+#define SCT_OUTPUTSET15_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET15: SETn7 Position     */
+#define SCT_OUTPUTSET15_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn7_Pos)                     /*!< SCT OUTPUTSET15: SETn7 Mask         */
+#define SCT_OUTPUTSET15_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET15: SETn8 Position     */
+#define SCT_OUTPUTSET15_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn8_Pos)                     /*!< SCT OUTPUTSET15: SETn8 Mask         */
+#define SCT_OUTPUTSET15_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET15: SETn9 Position     */
+#define SCT_OUTPUTSET15_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn9_Pos)                     /*!< SCT OUTPUTSET15: SETn9 Mask         */
+#define SCT_OUTPUTSET15_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET15: SETn10 Position    */
+#define SCT_OUTPUTSET15_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn10_Pos)                    /*!< SCT OUTPUTSET15: SETn10 Mask        */
+#define SCT_OUTPUTSET15_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET15: SETn11 Position    */
+#define SCT_OUTPUTSET15_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn11_Pos)                    /*!< SCT OUTPUTSET15: SETn11 Mask        */
+#define SCT_OUTPUTSET15_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET15: SETn12 Position    */
+#define SCT_OUTPUTSET15_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn12_Pos)                    /*!< SCT OUTPUTSET15: SETn12 Mask        */
+#define SCT_OUTPUTSET15_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET15: SETn13 Position    */
+#define SCT_OUTPUTSET15_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn13_Pos)                    /*!< SCT OUTPUTSET15: SETn13 Mask        */
+#define SCT_OUTPUTSET15_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET15: SETn14 Position    */
+#define SCT_OUTPUTSET15_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn14_Pos)                    /*!< SCT OUTPUTSET15: SETn14 Mask        */
+#define SCT_OUTPUTSET15_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET15: SETn15 Position    */
+#define SCT_OUTPUTSET15_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn15_Pos)                    /*!< SCT OUTPUTSET15: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR15  ----------------------------------------
+#define SCT_OUTPUTCLR15_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR15: CLRn0 Position     */
+#define SCT_OUTPUTCLR15_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos)                     /*!< SCT OUTPUTCLR15: CLRn0 Mask         */
+#define SCT_OUTPUTCLR15_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR15: CLRn1 Position     */
+#define SCT_OUTPUTCLR15_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos)                     /*!< SCT OUTPUTCLR15: CLRn1 Mask         */
+#define SCT_OUTPUTCLR15_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR15: CLRn2 Position     */
+#define SCT_OUTPUTCLR15_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos)                     /*!< SCT OUTPUTCLR15: CLRn2 Mask         */
+#define SCT_OUTPUTCLR15_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR15: CLRn3 Position     */
+#define SCT_OUTPUTCLR15_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos)                     /*!< SCT OUTPUTCLR15: CLRn3 Mask         */
+#define SCT_OUTPUTCLR15_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR15: CLRn4 Position     */
+#define SCT_OUTPUTCLR15_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos)                     /*!< SCT OUTPUTCLR15: CLRn4 Mask         */
+#define SCT_OUTPUTCLR15_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR15: CLRn5 Position     */
+#define SCT_OUTPUTCLR15_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos)                     /*!< SCT OUTPUTCLR15: CLRn5 Mask         */
+#define SCT_OUTPUTCLR15_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR15: CLRn6 Position     */
+#define SCT_OUTPUTCLR15_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos)                     /*!< SCT OUTPUTCLR15: CLRn6 Mask         */
+#define SCT_OUTPUTCLR15_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR15: CLRn7 Position     */
+#define SCT_OUTPUTCLR15_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos)                     /*!< SCT OUTPUTCLR15: CLRn7 Mask         */
+#define SCT_OUTPUTCLR15_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR15: CLRn8 Position     */
+#define SCT_OUTPUTCLR15_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos)                     /*!< SCT OUTPUTCLR15: CLRn8 Mask         */
+#define SCT_OUTPUTCLR15_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR15: CLRn9 Position     */
+#define SCT_OUTPUTCLR15_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos)                     /*!< SCT OUTPUTCLR15: CLRn9 Mask         */
+#define SCT_OUTPUTCLR15_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR15: CLRn10 Position    */
+#define SCT_OUTPUTCLR15_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos)                    /*!< SCT OUTPUTCLR15: CLRn10 Mask        */
+#define SCT_OUTPUTCLR15_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR15: CLRn11 Position    */
+#define SCT_OUTPUTCLR15_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos)                    /*!< SCT OUTPUTCLR15: CLRn11 Mask        */
+#define SCT_OUTPUTCLR15_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR15: CLRn12 Position    */
+#define SCT_OUTPUTCLR15_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos)                    /*!< SCT OUTPUTCLR15: CLRn12 Mask        */
+#define SCT_OUTPUTCLR15_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR15: CLRn13 Position    */
+#define SCT_OUTPUTCLR15_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos)                    /*!< SCT OUTPUTCLR15: CLRn13 Mask        */
+#define SCT_OUTPUTCLR15_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR15: CLRn14 Position    */
+#define SCT_OUTPUTCLR15_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos)                    /*!< SCT OUTPUTCLR15: CLRn14 Mask        */
+#define SCT_OUTPUTCLR15_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR15: CLRn15 Position    */
+#define SCT_OUTPUTCLR15_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos)                    /*!< SCT OUTPUTCLR15: CLRn15 Mask        */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 GPDMA Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------  GPDMA_INTSTAT  -----------------------------------------
+#define GPDMA_INTSTAT_INTSTAT0_Pos                            0                                                         /*!< GPDMA INTSTAT: INTSTAT0 Position    */
+#define GPDMA_INTSTAT_INTSTAT0_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos)                    /*!< GPDMA INTSTAT: INTSTAT0 Mask        */
+#define GPDMA_INTSTAT_INTSTAT1_Pos                            1                                                         /*!< GPDMA INTSTAT: INTSTAT1 Position    */
+#define GPDMA_INTSTAT_INTSTAT1_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos)                    /*!< GPDMA INTSTAT: INTSTAT1 Mask        */
+#define GPDMA_INTSTAT_INTSTAT2_Pos                            2                                                         /*!< GPDMA INTSTAT: INTSTAT2 Position    */
+#define GPDMA_INTSTAT_INTSTAT2_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos)                    /*!< GPDMA INTSTAT: INTSTAT2 Mask        */
+#define GPDMA_INTSTAT_INTSTAT3_Pos                            3                                                         /*!< GPDMA INTSTAT: INTSTAT3 Position    */
+#define GPDMA_INTSTAT_INTSTAT3_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos)                    /*!< GPDMA INTSTAT: INTSTAT3 Mask        */
+#define GPDMA_INTSTAT_INTSTAT4_Pos                            4                                                         /*!< GPDMA INTSTAT: INTSTAT4 Position    */
+#define GPDMA_INTSTAT_INTSTAT4_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos)                    /*!< GPDMA INTSTAT: INTSTAT4 Mask        */
+#define GPDMA_INTSTAT_INTSTAT5_Pos                            5                                                         /*!< GPDMA INTSTAT: INTSTAT5 Position    */
+#define GPDMA_INTSTAT_INTSTAT5_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos)                    /*!< GPDMA INTSTAT: INTSTAT5 Mask        */
+#define GPDMA_INTSTAT_INTSTAT6_Pos                            6                                                         /*!< GPDMA INTSTAT: INTSTAT6 Position    */
+#define GPDMA_INTSTAT_INTSTAT6_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos)                    /*!< GPDMA INTSTAT: INTSTAT6 Mask        */
+#define GPDMA_INTSTAT_INTSTAT7_Pos                            7                                                         /*!< GPDMA INTSTAT: INTSTAT7 Position    */
+#define GPDMA_INTSTAT_INTSTAT7_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos)                    /*!< GPDMA INTSTAT: INTSTAT7 Mask        */
+
+// -------------------------------------  GPDMA_INTTCSTAT  ----------------------------------------
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos                        0                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos                        1                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos                        2                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos                        3                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos                        4                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos                        5                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos                        6                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos                        7                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask    */
+
+// ------------------------------------  GPDMA_INTTCCLEAR  ----------------------------------------
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos                      0                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos                      1                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos                      2                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos                      3                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos                      4                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos                      5                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos                      6                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos                      7                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask  */
+
+// ------------------------------------  GPDMA_INTERRSTAT  ----------------------------------------
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos                      0                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos                      1                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos                      2                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos                      3                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos                      4                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos                      5                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos                      6                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos                      7                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask  */
+
+// -------------------------------------  GPDMA_INTERRCLR  ----------------------------------------
+#define GPDMA_INTERRCLR_INTERRCLR0_Pos                        0                                                         /*!< GPDMA INTERRCLR: INTERRCLR0 Position */
+#define GPDMA_INTERRCLR_INTERRCLR0_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR0 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR1_Pos                        1                                                         /*!< GPDMA INTERRCLR: INTERRCLR1 Position */
+#define GPDMA_INTERRCLR_INTERRCLR1_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR1 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR2_Pos                        2                                                         /*!< GPDMA INTERRCLR: INTERRCLR2 Position */
+#define GPDMA_INTERRCLR_INTERRCLR2_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR2 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR3_Pos                        3                                                         /*!< GPDMA INTERRCLR: INTERRCLR3 Position */
+#define GPDMA_INTERRCLR_INTERRCLR3_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR3 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR4_Pos                        4                                                         /*!< GPDMA INTERRCLR: INTERRCLR4 Position */
+#define GPDMA_INTERRCLR_INTERRCLR4_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR4 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR5_Pos                        5                                                         /*!< GPDMA INTERRCLR: INTERRCLR5 Position */
+#define GPDMA_INTERRCLR_INTERRCLR5_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR5 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR6_Pos                        6                                                         /*!< GPDMA INTERRCLR: INTERRCLR6 Position */
+#define GPDMA_INTERRCLR_INTERRCLR6_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR6 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR7_Pos                        7                                                         /*!< GPDMA INTERRCLR: INTERRCLR7 Position */
+#define GPDMA_INTERRCLR_INTERRCLR7_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR7 Mask    */
+
+// -----------------------------------  GPDMA_RAWINTTCSTAT  ---------------------------------------
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos                  0                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos                  1                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos                  2                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos                  3                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos                  4                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos                  5                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos                  6                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos                  7                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */
+
+// -----------------------------------  GPDMA_RAWINTERRSTAT  --------------------------------------
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos                0                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos                1                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos                2                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos                3                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos                4                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos                5                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos                6                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos                7                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */
+
+// -------------------------------------  GPDMA_ENBLDCHNS  ----------------------------------------
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos                  0                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos                  1                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos                  2                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos                  3                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos                  4                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos                  5                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos                  6                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos                  7                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */
+
+// -------------------------------------  GPDMA_SOFTBREQ  -----------------------------------------
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos                          0                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos                          1                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos                          2                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos                          3                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos                          4                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos                          5                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos                          6                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos                          7                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos                          8                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos                          9                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos                         10                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos                         11                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos                         12                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos                         13                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos                         14                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos                         15                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask     */
+
+// -------------------------------------  GPDMA_SOFTSREQ  -----------------------------------------
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos                          0                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos                          1                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos                          2                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos                          3                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos                          4                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos                          5                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos                          6                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos                          7                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos                          8                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos                          9                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos                         10                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos                         11                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos                         12                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos                         13                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos                         14                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos                         15                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask     */
+
+// -------------------------------------  GPDMA_SOFTLBREQ  ----------------------------------------
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos                        0                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos                        1                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos                        2                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos                        3                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos                        4                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos                        5                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos                        6                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos                        7                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos                        8                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos                        9                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos                       10                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos                       11                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos                       12                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos                       13                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos                       14                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos                       15                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask   */
+
+// -------------------------------------  GPDMA_SOFTLSREQ  ----------------------------------------
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos                        0                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos                        1                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos                        2                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos                        3                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos                        4                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos                        5                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos                        6                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos                        7                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos                        8                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos                        9                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos                       10                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos                       11                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos                       12                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos                       13                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos                       14                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos                       15                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask   */
+
+// --------------------------------------  GPDMA_CONFIG  ------------------------------------------
+#define GPDMA_CONFIG_E_Pos                                    0                                                         /*!< GPDMA CONFIG: E Position            */
+#define GPDMA_CONFIG_E_Msk                                    (0x01UL << GPDMA_CONFIG_E_Pos)                            /*!< GPDMA CONFIG: E Mask                */
+#define GPDMA_CONFIG_M0_Pos                                   1                                                         /*!< GPDMA CONFIG: M0 Position           */
+#define GPDMA_CONFIG_M0_Msk                                   (0x01UL << GPDMA_CONFIG_M0_Pos)                           /*!< GPDMA CONFIG: M0 Mask               */
+#define GPDMA_CONFIG_M1_Pos                                   2                                                         /*!< GPDMA CONFIG: M1 Position           */
+#define GPDMA_CONFIG_M1_Msk                                   (0x01UL << GPDMA_CONFIG_M1_Pos)                           /*!< GPDMA CONFIG: M1 Mask               */
+
+// ---------------------------------------  GPDMA_SYNC  -------------------------------------------
+#define GPDMA_SYNC_DMACSYNC0_Pos                              0                                                         /*!< GPDMA SYNC: DMACSYNC0 Position      */
+#define GPDMA_SYNC_DMACSYNC0_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos)                      /*!< GPDMA SYNC: DMACSYNC0 Mask          */
+#define GPDMA_SYNC_DMACSYNC1_Pos                              1                                                         /*!< GPDMA SYNC: DMACSYNC1 Position      */
+#define GPDMA_SYNC_DMACSYNC1_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos)                      /*!< GPDMA SYNC: DMACSYNC1 Mask          */
+#define GPDMA_SYNC_DMACSYNC2_Pos                              2                                                         /*!< GPDMA SYNC: DMACSYNC2 Position      */
+#define GPDMA_SYNC_DMACSYNC2_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos)                      /*!< GPDMA SYNC: DMACSYNC2 Mask          */
+#define GPDMA_SYNC_DMACSYNC3_Pos                              3                                                         /*!< GPDMA SYNC: DMACSYNC3 Position      */
+#define GPDMA_SYNC_DMACSYNC3_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos)                      /*!< GPDMA SYNC: DMACSYNC3 Mask          */
+#define GPDMA_SYNC_DMACSYNC4_Pos                              4                                                         /*!< GPDMA SYNC: DMACSYNC4 Position      */
+#define GPDMA_SYNC_DMACSYNC4_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos)                      /*!< GPDMA SYNC: DMACSYNC4 Mask          */
+#define GPDMA_SYNC_DMACSYNC5_Pos                              5                                                         /*!< GPDMA SYNC: DMACSYNC5 Position      */
+#define GPDMA_SYNC_DMACSYNC5_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos)                      /*!< GPDMA SYNC: DMACSYNC5 Mask          */
+#define GPDMA_SYNC_DMACSYNC6_Pos                              6                                                         /*!< GPDMA SYNC: DMACSYNC6 Position      */
+#define GPDMA_SYNC_DMACSYNC6_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos)                      /*!< GPDMA SYNC: DMACSYNC6 Mask          */
+#define GPDMA_SYNC_DMACSYNC7_Pos                              7                                                         /*!< GPDMA SYNC: DMACSYNC7 Position      */
+#define GPDMA_SYNC_DMACSYNC7_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos)                      /*!< GPDMA SYNC: DMACSYNC7 Mask          */
+#define GPDMA_SYNC_DMACSYNC8_Pos                              8                                                         /*!< GPDMA SYNC: DMACSYNC8 Position      */
+#define GPDMA_SYNC_DMACSYNC8_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos)                      /*!< GPDMA SYNC: DMACSYNC8 Mask          */
+#define GPDMA_SYNC_DMACSYNC9_Pos                              9                                                         /*!< GPDMA SYNC: DMACSYNC9 Position      */
+#define GPDMA_SYNC_DMACSYNC9_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos)                      /*!< GPDMA SYNC: DMACSYNC9 Mask          */
+#define GPDMA_SYNC_DMACSYNC10_Pos                             10                                                        /*!< GPDMA SYNC: DMACSYNC10 Position     */
+#define GPDMA_SYNC_DMACSYNC10_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos)                     /*!< GPDMA SYNC: DMACSYNC10 Mask         */
+#define GPDMA_SYNC_DMACSYNC11_Pos                             11                                                        /*!< GPDMA SYNC: DMACSYNC11 Position     */
+#define GPDMA_SYNC_DMACSYNC11_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos)                     /*!< GPDMA SYNC: DMACSYNC11 Mask         */
+#define GPDMA_SYNC_DMACSYNC12_Pos                             12                                                        /*!< GPDMA SYNC: DMACSYNC12 Position     */
+#define GPDMA_SYNC_DMACSYNC12_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos)                     /*!< GPDMA SYNC: DMACSYNC12 Mask         */
+#define GPDMA_SYNC_DMACSYNC13_Pos                             13                                                        /*!< GPDMA SYNC: DMACSYNC13 Position     */
+#define GPDMA_SYNC_DMACSYNC13_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos)                     /*!< GPDMA SYNC: DMACSYNC13 Mask         */
+#define GPDMA_SYNC_DMACSYNC14_Pos                             14                                                        /*!< GPDMA SYNC: DMACSYNC14 Position     */
+#define GPDMA_SYNC_DMACSYNC14_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos)                     /*!< GPDMA SYNC: DMACSYNC14 Mask         */
+#define GPDMA_SYNC_DMACSYNC15_Pos                             15                                                        /*!< GPDMA SYNC: DMACSYNC15 Position     */
+#define GPDMA_SYNC_DMACSYNC15_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos)                     /*!< GPDMA SYNC: DMACSYNC15 Mask         */
+
+// -------------------------------------  GPDMA_C0SRCADDR  ----------------------------------------
+#define GPDMA_C0SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C0SRCADDR: SRCADDR Position   */
+#define GPDMA_C0SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos)             /*!< GPDMA C0SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C0DESTADDR  ----------------------------------------
+#define GPDMA_C0DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C0DESTADDR: DESTADDR Position */
+#define GPDMA_C0DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos)           /*!< GPDMA C0DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C0LLI  ------------------------------------------
+#define GPDMA_C0LLI_LM_Pos                                    0                                                         /*!< GPDMA C0LLI: LM Position            */
+#define GPDMA_C0LLI_LM_Msk                                    (0x01UL << GPDMA_C0LLI_LM_Pos)                            /*!< GPDMA C0LLI: LM Mask                */
+#define GPDMA_C0LLI_R_Pos                                     1                                                         /*!< GPDMA C0LLI: R Position             */
+#define GPDMA_C0LLI_R_Msk                                     (0x01UL << GPDMA_C0LLI_R_Pos)                             /*!< GPDMA C0LLI: R Mask                 */
+#define GPDMA_C0LLI_LLI_Pos                                   2                                                         /*!< GPDMA C0LLI: LLI Position           */
+#define GPDMA_C0LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos)                     /*!< GPDMA C0LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C0CONTROL  ----------------------------------------
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C0CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C0CONTROL: SBSIZE Position    */
+#define GPDMA_C0CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos)                    /*!< GPDMA C0CONTROL: SBSIZE Mask        */
+#define GPDMA_C0CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C0CONTROL: DBSIZE Position    */
+#define GPDMA_C0CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos)                    /*!< GPDMA C0CONTROL: DBSIZE Mask        */
+#define GPDMA_C0CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C0CONTROL: SWIDTH Position    */
+#define GPDMA_C0CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos)                    /*!< GPDMA C0CONTROL: SWIDTH Mask        */
+#define GPDMA_C0CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C0CONTROL: DWIDTH Position    */
+#define GPDMA_C0CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos)                    /*!< GPDMA C0CONTROL: DWIDTH Mask        */
+#define GPDMA_C0CONTROL_S_Pos                                 24                                                        /*!< GPDMA C0CONTROL: S Position         */
+#define GPDMA_C0CONTROL_S_Msk                                 (0x01UL << GPDMA_C0CONTROL_S_Pos)                         /*!< GPDMA C0CONTROL: S Mask             */
+#define GPDMA_C0CONTROL_D_Pos                                 25                                                        /*!< GPDMA C0CONTROL: D Position         */
+#define GPDMA_C0CONTROL_D_Msk                                 (0x01UL << GPDMA_C0CONTROL_D_Pos)                         /*!< GPDMA C0CONTROL: D Mask             */
+#define GPDMA_C0CONTROL_SI_Pos                                26                                                        /*!< GPDMA C0CONTROL: SI Position        */
+#define GPDMA_C0CONTROL_SI_Msk                                (0x01UL << GPDMA_C0CONTROL_SI_Pos)                        /*!< GPDMA C0CONTROL: SI Mask            */
+#define GPDMA_C0CONTROL_DI_Pos                                27                                                        /*!< GPDMA C0CONTROL: DI Position        */
+#define GPDMA_C0CONTROL_DI_Msk                                (0x01UL << GPDMA_C0CONTROL_DI_Pos)                        /*!< GPDMA C0CONTROL: DI Mask            */
+#define GPDMA_C0CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C0CONTROL: PROT1 Position     */
+#define GPDMA_C0CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT1_Pos)                     /*!< GPDMA C0CONTROL: PROT1 Mask         */
+#define GPDMA_C0CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C0CONTROL: PROT2 Position     */
+#define GPDMA_C0CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT2_Pos)                     /*!< GPDMA C0CONTROL: PROT2 Mask         */
+#define GPDMA_C0CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C0CONTROL: PROT3 Position     */
+#define GPDMA_C0CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT3_Pos)                     /*!< GPDMA C0CONTROL: PROT3 Mask         */
+#define GPDMA_C0CONTROL_I_Pos                                 31                                                        /*!< GPDMA C0CONTROL: I Position         */
+#define GPDMA_C0CONTROL_I_Msk                                 (0x01UL << GPDMA_C0CONTROL_I_Pos)                         /*!< GPDMA C0CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C0CONFIG  -----------------------------------------
+#define GPDMA_C0CONFIG_E_Pos                                  0                                                         /*!< GPDMA C0CONFIG: E Position          */
+#define GPDMA_C0CONFIG_E_Msk                                  (0x01UL << GPDMA_C0CONFIG_E_Pos)                          /*!< GPDMA C0CONFIG: E Mask              */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C0CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C0CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C0CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C0CONFIG: IE Position         */
+#define GPDMA_C0CONFIG_IE_Msk                                 (0x01UL << GPDMA_C0CONFIG_IE_Pos)                         /*!< GPDMA C0CONFIG: IE Mask             */
+#define GPDMA_C0CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C0CONFIG: ITC Position        */
+#define GPDMA_C0CONFIG_ITC_Msk                                (0x01UL << GPDMA_C0CONFIG_ITC_Pos)                        /*!< GPDMA C0CONFIG: ITC Mask            */
+#define GPDMA_C0CONFIG_L_Pos                                  16                                                        /*!< GPDMA C0CONFIG: L Position          */
+#define GPDMA_C0CONFIG_L_Msk                                  (0x01UL << GPDMA_C0CONFIG_L_Pos)                          /*!< GPDMA C0CONFIG: L Mask              */
+#define GPDMA_C0CONFIG_A_Pos                                  17                                                        /*!< GPDMA C0CONFIG: A Position          */
+#define GPDMA_C0CONFIG_A_Msk                                  (0x01UL << GPDMA_C0CONFIG_A_Pos)                          /*!< GPDMA C0CONFIG: A Mask              */
+#define GPDMA_C0CONFIG_H_Pos                                  18                                                        /*!< GPDMA C0CONFIG: H Position          */
+#define GPDMA_C0CONFIG_H_Msk                                  (0x01UL << GPDMA_C0CONFIG_H_Pos)                          /*!< GPDMA C0CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C1SRCADDR  ----------------------------------------
+#define GPDMA_C1SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C1SRCADDR: SRCADDR Position   */
+#define GPDMA_C1SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos)             /*!< GPDMA C1SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C1DESTADDR  ----------------------------------------
+#define GPDMA_C1DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C1DESTADDR: DESTADDR Position */
+#define GPDMA_C1DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos)           /*!< GPDMA C1DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C1LLI  ------------------------------------------
+#define GPDMA_C1LLI_LM_Pos                                    0                                                         /*!< GPDMA C1LLI: LM Position            */
+#define GPDMA_C1LLI_LM_Msk                                    (0x01UL << GPDMA_C1LLI_LM_Pos)                            /*!< GPDMA C1LLI: LM Mask                */
+#define GPDMA_C1LLI_R_Pos                                     1                                                         /*!< GPDMA C1LLI: R Position             */
+#define GPDMA_C1LLI_R_Msk                                     (0x01UL << GPDMA_C1LLI_R_Pos)                             /*!< GPDMA C1LLI: R Mask                 */
+#define GPDMA_C1LLI_LLI_Pos                                   2                                                         /*!< GPDMA C1LLI: LLI Position           */
+#define GPDMA_C1LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos)                     /*!< GPDMA C1LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C1CONTROL  ----------------------------------------
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C1CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C1CONTROL: SBSIZE Position    */
+#define GPDMA_C1CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos)                    /*!< GPDMA C1CONTROL: SBSIZE Mask        */
+#define GPDMA_C1CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C1CONTROL: DBSIZE Position    */
+#define GPDMA_C1CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos)                    /*!< GPDMA C1CONTROL: DBSIZE Mask        */
+#define GPDMA_C1CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C1CONTROL: SWIDTH Position    */
+#define GPDMA_C1CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos)                    /*!< GPDMA C1CONTROL: SWIDTH Mask        */
+#define GPDMA_C1CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C1CONTROL: DWIDTH Position    */
+#define GPDMA_C1CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos)                    /*!< GPDMA C1CONTROL: DWIDTH Mask        */
+#define GPDMA_C1CONTROL_S_Pos                                 24                                                        /*!< GPDMA C1CONTROL: S Position         */
+#define GPDMA_C1CONTROL_S_Msk                                 (0x01UL << GPDMA_C1CONTROL_S_Pos)                         /*!< GPDMA C1CONTROL: S Mask             */
+#define GPDMA_C1CONTROL_D_Pos                                 25                                                        /*!< GPDMA C1CONTROL: D Position         */
+#define GPDMA_C1CONTROL_D_Msk                                 (0x01UL << GPDMA_C1CONTROL_D_Pos)                         /*!< GPDMA C1CONTROL: D Mask             */
+#define GPDMA_C1CONTROL_SI_Pos                                26                                                        /*!< GPDMA C1CONTROL: SI Position        */
+#define GPDMA_C1CONTROL_SI_Msk                                (0x01UL << GPDMA_C1CONTROL_SI_Pos)                        /*!< GPDMA C1CONTROL: SI Mask            */
+#define GPDMA_C1CONTROL_DI_Pos                                27                                                        /*!< GPDMA C1CONTROL: DI Position        */
+#define GPDMA_C1CONTROL_DI_Msk                                (0x01UL << GPDMA_C1CONTROL_DI_Pos)                        /*!< GPDMA C1CONTROL: DI Mask            */
+#define GPDMA_C1CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C1CONTROL: PROT1 Position     */
+#define GPDMA_C1CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT1_Pos)                     /*!< GPDMA C1CONTROL: PROT1 Mask         */
+#define GPDMA_C1CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C1CONTROL: PROT2 Position     */
+#define GPDMA_C1CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT2_Pos)                     /*!< GPDMA C1CONTROL: PROT2 Mask         */
+#define GPDMA_C1CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C1CONTROL: PROT3 Position     */
+#define GPDMA_C1CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT3_Pos)                     /*!< GPDMA C1CONTROL: PROT3 Mask         */
+#define GPDMA_C1CONTROL_I_Pos                                 31                                                        /*!< GPDMA C1CONTROL: I Position         */
+#define GPDMA_C1CONTROL_I_Msk                                 (0x01UL << GPDMA_C1CONTROL_I_Pos)                         /*!< GPDMA C1CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C1CONFIG  -----------------------------------------
+#define GPDMA_C1CONFIG_E_Pos                                  0                                                         /*!< GPDMA C1CONFIG: E Position          */
+#define GPDMA_C1CONFIG_E_Msk                                  (0x01UL << GPDMA_C1CONFIG_E_Pos)                          /*!< GPDMA C1CONFIG: E Mask              */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C1CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C1CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C1CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C1CONFIG: IE Position         */
+#define GPDMA_C1CONFIG_IE_Msk                                 (0x01UL << GPDMA_C1CONFIG_IE_Pos)                         /*!< GPDMA C1CONFIG: IE Mask             */
+#define GPDMA_C1CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C1CONFIG: ITC Position        */
+#define GPDMA_C1CONFIG_ITC_Msk                                (0x01UL << GPDMA_C1CONFIG_ITC_Pos)                        /*!< GPDMA C1CONFIG: ITC Mask            */
+#define GPDMA_C1CONFIG_L_Pos                                  16                                                        /*!< GPDMA C1CONFIG: L Position          */
+#define GPDMA_C1CONFIG_L_Msk                                  (0x01UL << GPDMA_C1CONFIG_L_Pos)                          /*!< GPDMA C1CONFIG: L Mask              */
+#define GPDMA_C1CONFIG_A_Pos                                  17                                                        /*!< GPDMA C1CONFIG: A Position          */
+#define GPDMA_C1CONFIG_A_Msk                                  (0x01UL << GPDMA_C1CONFIG_A_Pos)                          /*!< GPDMA C1CONFIG: A Mask              */
+#define GPDMA_C1CONFIG_H_Pos                                  18                                                        /*!< GPDMA C1CONFIG: H Position          */
+#define GPDMA_C1CONFIG_H_Msk                                  (0x01UL << GPDMA_C1CONFIG_H_Pos)                          /*!< GPDMA C1CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C2SRCADDR  ----------------------------------------
+#define GPDMA_C2SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C2SRCADDR: SRCADDR Position   */
+#define GPDMA_C2SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos)             /*!< GPDMA C2SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C2DESTADDR  ----------------------------------------
+#define GPDMA_C2DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C2DESTADDR: DESTADDR Position */
+#define GPDMA_C2DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos)           /*!< GPDMA C2DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C2LLI  ------------------------------------------
+#define GPDMA_C2LLI_LM_Pos                                    0                                                         /*!< GPDMA C2LLI: LM Position            */
+#define GPDMA_C2LLI_LM_Msk                                    (0x01UL << GPDMA_C2LLI_LM_Pos)                            /*!< GPDMA C2LLI: LM Mask                */
+#define GPDMA_C2LLI_R_Pos                                     1                                                         /*!< GPDMA C2LLI: R Position             */
+#define GPDMA_C2LLI_R_Msk                                     (0x01UL << GPDMA_C2LLI_R_Pos)                             /*!< GPDMA C2LLI: R Mask                 */
+#define GPDMA_C2LLI_LLI_Pos                                   2                                                         /*!< GPDMA C2LLI: LLI Position           */
+#define GPDMA_C2LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos)                     /*!< GPDMA C2LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C2CONTROL  ----------------------------------------
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C2CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C2CONTROL: SBSIZE Position    */
+#define GPDMA_C2CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos)                    /*!< GPDMA C2CONTROL: SBSIZE Mask        */
+#define GPDMA_C2CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C2CONTROL: DBSIZE Position    */
+#define GPDMA_C2CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos)                    /*!< GPDMA C2CONTROL: DBSIZE Mask        */
+#define GPDMA_C2CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C2CONTROL: SWIDTH Position    */
+#define GPDMA_C2CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos)                    /*!< GPDMA C2CONTROL: SWIDTH Mask        */
+#define GPDMA_C2CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C2CONTROL: DWIDTH Position    */
+#define GPDMA_C2CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos)                    /*!< GPDMA C2CONTROL: DWIDTH Mask        */
+#define GPDMA_C2CONTROL_S_Pos                                 24                                                        /*!< GPDMA C2CONTROL: S Position         */
+#define GPDMA_C2CONTROL_S_Msk                                 (0x01UL << GPDMA_C2CONTROL_S_Pos)                         /*!< GPDMA C2CONTROL: S Mask             */
+#define GPDMA_C2CONTROL_D_Pos                                 25                                                        /*!< GPDMA C2CONTROL: D Position         */
+#define GPDMA_C2CONTROL_D_Msk                                 (0x01UL << GPDMA_C2CONTROL_D_Pos)                         /*!< GPDMA C2CONTROL: D Mask             */
+#define GPDMA_C2CONTROL_SI_Pos                                26                                                        /*!< GPDMA C2CONTROL: SI Position        */
+#define GPDMA_C2CONTROL_SI_Msk                                (0x01UL << GPDMA_C2CONTROL_SI_Pos)                        /*!< GPDMA C2CONTROL: SI Mask            */
+#define GPDMA_C2CONTROL_DI_Pos                                27                                                        /*!< GPDMA C2CONTROL: DI Position        */
+#define GPDMA_C2CONTROL_DI_Msk                                (0x01UL << GPDMA_C2CONTROL_DI_Pos)                        /*!< GPDMA C2CONTROL: DI Mask            */
+#define GPDMA_C2CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C2CONTROL: PROT1 Position     */
+#define GPDMA_C2CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT1_Pos)                     /*!< GPDMA C2CONTROL: PROT1 Mask         */
+#define GPDMA_C2CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C2CONTROL: PROT2 Position     */
+#define GPDMA_C2CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT2_Pos)                     /*!< GPDMA C2CONTROL: PROT2 Mask         */
+#define GPDMA_C2CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C2CONTROL: PROT3 Position     */
+#define GPDMA_C2CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT3_Pos)                     /*!< GPDMA C2CONTROL: PROT3 Mask         */
+#define GPDMA_C2CONTROL_I_Pos                                 31                                                        /*!< GPDMA C2CONTROL: I Position         */
+#define GPDMA_C2CONTROL_I_Msk                                 (0x01UL << GPDMA_C2CONTROL_I_Pos)                         /*!< GPDMA C2CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C2CONFIG  -----------------------------------------
+#define GPDMA_C2CONFIG_E_Pos                                  0                                                         /*!< GPDMA C2CONFIG: E Position          */
+#define GPDMA_C2CONFIG_E_Msk                                  (0x01UL << GPDMA_C2CONFIG_E_Pos)                          /*!< GPDMA C2CONFIG: E Mask              */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C2CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C2CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C2CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C2CONFIG: IE Position         */
+#define GPDMA_C2CONFIG_IE_Msk                                 (0x01UL << GPDMA_C2CONFIG_IE_Pos)                         /*!< GPDMA C2CONFIG: IE Mask             */
+#define GPDMA_C2CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C2CONFIG: ITC Position        */
+#define GPDMA_C2CONFIG_ITC_Msk                                (0x01UL << GPDMA_C2CONFIG_ITC_Pos)                        /*!< GPDMA C2CONFIG: ITC Mask            */
+#define GPDMA_C2CONFIG_L_Pos                                  16                                                        /*!< GPDMA C2CONFIG: L Position          */
+#define GPDMA_C2CONFIG_L_Msk                                  (0x01UL << GPDMA_C2CONFIG_L_Pos)                          /*!< GPDMA C2CONFIG: L Mask              */
+#define GPDMA_C2CONFIG_A_Pos                                  17                                                        /*!< GPDMA C2CONFIG: A Position          */
+#define GPDMA_C2CONFIG_A_Msk                                  (0x01UL << GPDMA_C2CONFIG_A_Pos)                          /*!< GPDMA C2CONFIG: A Mask              */
+#define GPDMA_C2CONFIG_H_Pos                                  18                                                        /*!< GPDMA C2CONFIG: H Position          */
+#define GPDMA_C2CONFIG_H_Msk                                  (0x01UL << GPDMA_C2CONFIG_H_Pos)                          /*!< GPDMA C2CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C3SRCADDR  ----------------------------------------
+#define GPDMA_C3SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C3SRCADDR: SRCADDR Position   */
+#define GPDMA_C3SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos)             /*!< GPDMA C3SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C3DESTADDR  ----------------------------------------
+#define GPDMA_C3DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C3DESTADDR: DESTADDR Position */
+#define GPDMA_C3DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos)           /*!< GPDMA C3DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C3LLI  ------------------------------------------
+#define GPDMA_C3LLI_LM_Pos                                    0                                                         /*!< GPDMA C3LLI: LM Position            */
+#define GPDMA_C3LLI_LM_Msk                                    (0x01UL << GPDMA_C3LLI_LM_Pos)                            /*!< GPDMA C3LLI: LM Mask                */
+#define GPDMA_C3LLI_R_Pos                                     1                                                         /*!< GPDMA C3LLI: R Position             */
+#define GPDMA_C3LLI_R_Msk                                     (0x01UL << GPDMA_C3LLI_R_Pos)                             /*!< GPDMA C3LLI: R Mask                 */
+#define GPDMA_C3LLI_LLI_Pos                                   2                                                         /*!< GPDMA C3LLI: LLI Position           */
+#define GPDMA_C3LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos)                     /*!< GPDMA C3LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C3CONTROL  ----------------------------------------
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C3CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C3CONTROL: SBSIZE Position    */
+#define GPDMA_C3CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos)                    /*!< GPDMA C3CONTROL: SBSIZE Mask        */
+#define GPDMA_C3CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C3CONTROL: DBSIZE Position    */
+#define GPDMA_C3CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos)                    /*!< GPDMA C3CONTROL: DBSIZE Mask        */
+#define GPDMA_C3CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C3CONTROL: SWIDTH Position    */
+#define GPDMA_C3CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos)                    /*!< GPDMA C3CONTROL: SWIDTH Mask        */
+#define GPDMA_C3CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C3CONTROL: DWIDTH Position    */
+#define GPDMA_C3CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos)                    /*!< GPDMA C3CONTROL: DWIDTH Mask        */
+#define GPDMA_C3CONTROL_S_Pos                                 24                                                        /*!< GPDMA C3CONTROL: S Position         */
+#define GPDMA_C3CONTROL_S_Msk                                 (0x01UL << GPDMA_C3CONTROL_S_Pos)                         /*!< GPDMA C3CONTROL: S Mask             */
+#define GPDMA_C3CONTROL_D_Pos                                 25                                                        /*!< GPDMA C3CONTROL: D Position         */
+#define GPDMA_C3CONTROL_D_Msk                                 (0x01UL << GPDMA_C3CONTROL_D_Pos)                         /*!< GPDMA C3CONTROL: D Mask             */
+#define GPDMA_C3CONTROL_SI_Pos                                26                                                        /*!< GPDMA C3CONTROL: SI Position        */
+#define GPDMA_C3CONTROL_SI_Msk                                (0x01UL << GPDMA_C3CONTROL_SI_Pos)                        /*!< GPDMA C3CONTROL: SI Mask            */
+#define GPDMA_C3CONTROL_DI_Pos                                27                                                        /*!< GPDMA C3CONTROL: DI Position        */
+#define GPDMA_C3CONTROL_DI_Msk                                (0x01UL << GPDMA_C3CONTROL_DI_Pos)                        /*!< GPDMA C3CONTROL: DI Mask            */
+#define GPDMA_C3CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C3CONTROL: PROT1 Position     */
+#define GPDMA_C3CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT1_Pos)                     /*!< GPDMA C3CONTROL: PROT1 Mask         */
+#define GPDMA_C3CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C3CONTROL: PROT2 Position     */
+#define GPDMA_C3CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT2_Pos)                     /*!< GPDMA C3CONTROL: PROT2 Mask         */
+#define GPDMA_C3CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C3CONTROL: PROT3 Position     */
+#define GPDMA_C3CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT3_Pos)                     /*!< GPDMA C3CONTROL: PROT3 Mask         */
+#define GPDMA_C3CONTROL_I_Pos                                 31                                                        /*!< GPDMA C3CONTROL: I Position         */
+#define GPDMA_C3CONTROL_I_Msk                                 (0x01UL << GPDMA_C3CONTROL_I_Pos)                         /*!< GPDMA C3CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C3CONFIG  -----------------------------------------
+#define GPDMA_C3CONFIG_E_Pos                                  0                                                         /*!< GPDMA C3CONFIG: E Position          */
+#define GPDMA_C3CONFIG_E_Msk                                  (0x01UL << GPDMA_C3CONFIG_E_Pos)                          /*!< GPDMA C3CONFIG: E Mask              */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C3CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C3CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C3CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C3CONFIG: IE Position         */
+#define GPDMA_C3CONFIG_IE_Msk                                 (0x01UL << GPDMA_C3CONFIG_IE_Pos)                         /*!< GPDMA C3CONFIG: IE Mask             */
+#define GPDMA_C3CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C3CONFIG: ITC Position        */
+#define GPDMA_C3CONFIG_ITC_Msk                                (0x01UL << GPDMA_C3CONFIG_ITC_Pos)                        /*!< GPDMA C3CONFIG: ITC Mask            */
+#define GPDMA_C3CONFIG_L_Pos                                  16                                                        /*!< GPDMA C3CONFIG: L Position          */
+#define GPDMA_C3CONFIG_L_Msk                                  (0x01UL << GPDMA_C3CONFIG_L_Pos)                          /*!< GPDMA C3CONFIG: L Mask              */
+#define GPDMA_C3CONFIG_A_Pos                                  17                                                        /*!< GPDMA C3CONFIG: A Position          */
+#define GPDMA_C3CONFIG_A_Msk                                  (0x01UL << GPDMA_C3CONFIG_A_Pos)                          /*!< GPDMA C3CONFIG: A Mask              */
+#define GPDMA_C3CONFIG_H_Pos                                  18                                                        /*!< GPDMA C3CONFIG: H Position          */
+#define GPDMA_C3CONFIG_H_Msk                                  (0x01UL << GPDMA_C3CONFIG_H_Pos)                          /*!< GPDMA C3CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C4SRCADDR  ----------------------------------------
+#define GPDMA_C4SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C4SRCADDR: SRCADDR Position   */
+#define GPDMA_C4SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos)             /*!< GPDMA C4SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C4DESTADDR  ----------------------------------------
+#define GPDMA_C4DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C4DESTADDR: DESTADDR Position */
+#define GPDMA_C4DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos)           /*!< GPDMA C4DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C4LLI  ------------------------------------------
+#define GPDMA_C4LLI_LM_Pos                                    0                                                         /*!< GPDMA C4LLI: LM Position            */
+#define GPDMA_C4LLI_LM_Msk                                    (0x01UL << GPDMA_C4LLI_LM_Pos)                            /*!< GPDMA C4LLI: LM Mask                */
+#define GPDMA_C4LLI_R_Pos                                     1                                                         /*!< GPDMA C4LLI: R Position             */
+#define GPDMA_C4LLI_R_Msk                                     (0x01UL << GPDMA_C4LLI_R_Pos)                             /*!< GPDMA C4LLI: R Mask                 */
+#define GPDMA_C4LLI_LLI_Pos                                   2                                                         /*!< GPDMA C4LLI: LLI Position           */
+#define GPDMA_C4LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos)                     /*!< GPDMA C4LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C4CONTROL  ----------------------------------------
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C4CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C4CONTROL: SBSIZE Position    */
+#define GPDMA_C4CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos)                    /*!< GPDMA C4CONTROL: SBSIZE Mask        */
+#define GPDMA_C4CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C4CONTROL: DBSIZE Position    */
+#define GPDMA_C4CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos)                    /*!< GPDMA C4CONTROL: DBSIZE Mask        */
+#define GPDMA_C4CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C4CONTROL: SWIDTH Position    */
+#define GPDMA_C4CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos)                    /*!< GPDMA C4CONTROL: SWIDTH Mask        */
+#define GPDMA_C4CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C4CONTROL: DWIDTH Position    */
+#define GPDMA_C4CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos)                    /*!< GPDMA C4CONTROL: DWIDTH Mask        */
+#define GPDMA_C4CONTROL_S_Pos                                 24                                                        /*!< GPDMA C4CONTROL: S Position         */
+#define GPDMA_C4CONTROL_S_Msk                                 (0x01UL << GPDMA_C4CONTROL_S_Pos)                         /*!< GPDMA C4CONTROL: S Mask             */
+#define GPDMA_C4CONTROL_D_Pos                                 25                                                        /*!< GPDMA C4CONTROL: D Position         */
+#define GPDMA_C4CONTROL_D_Msk                                 (0x01UL << GPDMA_C4CONTROL_D_Pos)                         /*!< GPDMA C4CONTROL: D Mask             */
+#define GPDMA_C4CONTROL_SI_Pos                                26                                                        /*!< GPDMA C4CONTROL: SI Position        */
+#define GPDMA_C4CONTROL_SI_Msk                                (0x01UL << GPDMA_C4CONTROL_SI_Pos)                        /*!< GPDMA C4CONTROL: SI Mask            */
+#define GPDMA_C4CONTROL_DI_Pos                                27                                                        /*!< GPDMA C4CONTROL: DI Position        */
+#define GPDMA_C4CONTROL_DI_Msk                                (0x01UL << GPDMA_C4CONTROL_DI_Pos)                        /*!< GPDMA C4CONTROL: DI Mask            */
+#define GPDMA_C4CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C4CONTROL: PROT1 Position     */
+#define GPDMA_C4CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT1_Pos)                     /*!< GPDMA C4CONTROL: PROT1 Mask         */
+#define GPDMA_C4CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C4CONTROL: PROT2 Position     */
+#define GPDMA_C4CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT2_Pos)                     /*!< GPDMA C4CONTROL: PROT2 Mask         */
+#define GPDMA_C4CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C4CONTROL: PROT3 Position     */
+#define GPDMA_C4CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT3_Pos)                     /*!< GPDMA C4CONTROL: PROT3 Mask         */
+#define GPDMA_C4CONTROL_I_Pos                                 31                                                        /*!< GPDMA C4CONTROL: I Position         */
+#define GPDMA_C4CONTROL_I_Msk                                 (0x01UL << GPDMA_C4CONTROL_I_Pos)                         /*!< GPDMA C4CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C4CONFIG  -----------------------------------------
+#define GPDMA_C4CONFIG_E_Pos                                  0                                                         /*!< GPDMA C4CONFIG: E Position          */
+#define GPDMA_C4CONFIG_E_Msk                                  (0x01UL << GPDMA_C4CONFIG_E_Pos)                          /*!< GPDMA C4CONFIG: E Mask              */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C4CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C4CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C4CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C4CONFIG: IE Position         */
+#define GPDMA_C4CONFIG_IE_Msk                                 (0x01UL << GPDMA_C4CONFIG_IE_Pos)                         /*!< GPDMA C4CONFIG: IE Mask             */
+#define GPDMA_C4CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C4CONFIG: ITC Position        */
+#define GPDMA_C4CONFIG_ITC_Msk                                (0x01UL << GPDMA_C4CONFIG_ITC_Pos)                        /*!< GPDMA C4CONFIG: ITC Mask            */
+#define GPDMA_C4CONFIG_L_Pos                                  16                                                        /*!< GPDMA C4CONFIG: L Position          */
+#define GPDMA_C4CONFIG_L_Msk                                  (0x01UL << GPDMA_C4CONFIG_L_Pos)                          /*!< GPDMA C4CONFIG: L Mask              */
+#define GPDMA_C4CONFIG_A_Pos                                  17                                                        /*!< GPDMA C4CONFIG: A Position          */
+#define GPDMA_C4CONFIG_A_Msk                                  (0x01UL << GPDMA_C4CONFIG_A_Pos)                          /*!< GPDMA C4CONFIG: A Mask              */
+#define GPDMA_C4CONFIG_H_Pos                                  18                                                        /*!< GPDMA C4CONFIG: H Position          */
+#define GPDMA_C4CONFIG_H_Msk                                  (0x01UL << GPDMA_C4CONFIG_H_Pos)                          /*!< GPDMA C4CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C5SRCADDR  ----------------------------------------
+#define GPDMA_C5SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C5SRCADDR: SRCADDR Position   */
+#define GPDMA_C5SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos)             /*!< GPDMA C5SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C5DESTADDR  ----------------------------------------
+#define GPDMA_C5DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C5DESTADDR: DESTADDR Position */
+#define GPDMA_C5DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos)           /*!< GPDMA C5DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C5LLI  ------------------------------------------
+#define GPDMA_C5LLI_LM_Pos                                    0                                                         /*!< GPDMA C5LLI: LM Position            */
+#define GPDMA_C5LLI_LM_Msk                                    (0x01UL << GPDMA_C5LLI_LM_Pos)                            /*!< GPDMA C5LLI: LM Mask                */
+#define GPDMA_C5LLI_R_Pos                                     1                                                         /*!< GPDMA C5LLI: R Position             */
+#define GPDMA_C5LLI_R_Msk                                     (0x01UL << GPDMA_C5LLI_R_Pos)                             /*!< GPDMA C5LLI: R Mask                 */
+#define GPDMA_C5LLI_LLI_Pos                                   2                                                         /*!< GPDMA C5LLI: LLI Position           */
+#define GPDMA_C5LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos)                     /*!< GPDMA C5LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C5CONTROL  ----------------------------------------
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C5CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C5CONTROL: SBSIZE Position    */
+#define GPDMA_C5CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos)                    /*!< GPDMA C5CONTROL: SBSIZE Mask        */
+#define GPDMA_C5CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C5CONTROL: DBSIZE Position    */
+#define GPDMA_C5CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos)                    /*!< GPDMA C5CONTROL: DBSIZE Mask        */
+#define GPDMA_C5CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C5CONTROL: SWIDTH Position    */
+#define GPDMA_C5CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos)                    /*!< GPDMA C5CONTROL: SWIDTH Mask        */
+#define GPDMA_C5CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C5CONTROL: DWIDTH Position    */
+#define GPDMA_C5CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos)                    /*!< GPDMA C5CONTROL: DWIDTH Mask        */
+#define GPDMA_C5CONTROL_S_Pos                                 24                                                        /*!< GPDMA C5CONTROL: S Position         */
+#define GPDMA_C5CONTROL_S_Msk                                 (0x01UL << GPDMA_C5CONTROL_S_Pos)                         /*!< GPDMA C5CONTROL: S Mask             */
+#define GPDMA_C5CONTROL_D_Pos                                 25                                                        /*!< GPDMA C5CONTROL: D Position         */
+#define GPDMA_C5CONTROL_D_Msk                                 (0x01UL << GPDMA_C5CONTROL_D_Pos)                         /*!< GPDMA C5CONTROL: D Mask             */
+#define GPDMA_C5CONTROL_SI_Pos                                26                                                        /*!< GPDMA C5CONTROL: SI Position        */
+#define GPDMA_C5CONTROL_SI_Msk                                (0x01UL << GPDMA_C5CONTROL_SI_Pos)                        /*!< GPDMA C5CONTROL: SI Mask            */
+#define GPDMA_C5CONTROL_DI_Pos                                27                                                        /*!< GPDMA C5CONTROL: DI Position        */
+#define GPDMA_C5CONTROL_DI_Msk                                (0x01UL << GPDMA_C5CONTROL_DI_Pos)                        /*!< GPDMA C5CONTROL: DI Mask            */
+#define GPDMA_C5CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C5CONTROL: PROT1 Position     */
+#define GPDMA_C5CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT1_Pos)                     /*!< GPDMA C5CONTROL: PROT1 Mask         */
+#define GPDMA_C5CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C5CONTROL: PROT2 Position     */
+#define GPDMA_C5CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT2_Pos)                     /*!< GPDMA C5CONTROL: PROT2 Mask         */
+#define GPDMA_C5CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C5CONTROL: PROT3 Position     */
+#define GPDMA_C5CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT3_Pos)                     /*!< GPDMA C5CONTROL: PROT3 Mask         */
+#define GPDMA_C5CONTROL_I_Pos                                 31                                                        /*!< GPDMA C5CONTROL: I Position         */
+#define GPDMA_C5CONTROL_I_Msk                                 (0x01UL << GPDMA_C5CONTROL_I_Pos)                         /*!< GPDMA C5CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C5CONFIG  -----------------------------------------
+#define GPDMA_C5CONFIG_E_Pos                                  0                                                         /*!< GPDMA C5CONFIG: E Position          */
+#define GPDMA_C5CONFIG_E_Msk                                  (0x01UL << GPDMA_C5CONFIG_E_Pos)                          /*!< GPDMA C5CONFIG: E Mask              */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C5CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C5CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C5CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C5CONFIG: IE Position         */
+#define GPDMA_C5CONFIG_IE_Msk                                 (0x01UL << GPDMA_C5CONFIG_IE_Pos)                         /*!< GPDMA C5CONFIG: IE Mask             */
+#define GPDMA_C5CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C5CONFIG: ITC Position        */
+#define GPDMA_C5CONFIG_ITC_Msk                                (0x01UL << GPDMA_C5CONFIG_ITC_Pos)                        /*!< GPDMA C5CONFIG: ITC Mask            */
+#define GPDMA_C5CONFIG_L_Pos                                  16                                                        /*!< GPDMA C5CONFIG: L Position          */
+#define GPDMA_C5CONFIG_L_Msk                                  (0x01UL << GPDMA_C5CONFIG_L_Pos)                          /*!< GPDMA C5CONFIG: L Mask              */
+#define GPDMA_C5CONFIG_A_Pos                                  17                                                        /*!< GPDMA C5CONFIG: A Position          */
+#define GPDMA_C5CONFIG_A_Msk                                  (0x01UL << GPDMA_C5CONFIG_A_Pos)                          /*!< GPDMA C5CONFIG: A Mask              */
+#define GPDMA_C5CONFIG_H_Pos                                  18                                                        /*!< GPDMA C5CONFIG: H Position          */
+#define GPDMA_C5CONFIG_H_Msk                                  (0x01UL << GPDMA_C5CONFIG_H_Pos)                          /*!< GPDMA C5CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C6SRCADDR  ----------------------------------------
+#define GPDMA_C6SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C6SRCADDR: SRCADDR Position   */
+#define GPDMA_C6SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos)             /*!< GPDMA C6SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C6DESTADDR  ----------------------------------------
+#define GPDMA_C6DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C6DESTADDR: DESTADDR Position */
+#define GPDMA_C6DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos)           /*!< GPDMA C6DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C6LLI  ------------------------------------------
+#define GPDMA_C6LLI_LM_Pos                                    0                                                         /*!< GPDMA C6LLI: LM Position            */
+#define GPDMA_C6LLI_LM_Msk                                    (0x01UL << GPDMA_C6LLI_LM_Pos)                            /*!< GPDMA C6LLI: LM Mask                */
+#define GPDMA_C6LLI_R_Pos                                     1                                                         /*!< GPDMA C6LLI: R Position             */
+#define GPDMA_C6LLI_R_Msk                                     (0x01UL << GPDMA_C6LLI_R_Pos)                             /*!< GPDMA C6LLI: R Mask                 */
+#define GPDMA_C6LLI_LLI_Pos                                   2                                                         /*!< GPDMA C6LLI: LLI Position           */
+#define GPDMA_C6LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos)                     /*!< GPDMA C6LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C6CONTROL  ----------------------------------------
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C6CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C6CONTROL: SBSIZE Position    */
+#define GPDMA_C6CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos)                    /*!< GPDMA C6CONTROL: SBSIZE Mask        */
+#define GPDMA_C6CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C6CONTROL: DBSIZE Position    */
+#define GPDMA_C6CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos)                    /*!< GPDMA C6CONTROL: DBSIZE Mask        */
+#define GPDMA_C6CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C6CONTROL: SWIDTH Position    */
+#define GPDMA_C6CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos)                    /*!< GPDMA C6CONTROL: SWIDTH Mask        */
+#define GPDMA_C6CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C6CONTROL: DWIDTH Position    */
+#define GPDMA_C6CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos)                    /*!< GPDMA C6CONTROL: DWIDTH Mask        */
+#define GPDMA_C6CONTROL_S_Pos                                 24                                                        /*!< GPDMA C6CONTROL: S Position         */
+#define GPDMA_C6CONTROL_S_Msk                                 (0x01UL << GPDMA_C6CONTROL_S_Pos)                         /*!< GPDMA C6CONTROL: S Mask             */
+#define GPDMA_C6CONTROL_D_Pos                                 25                                                        /*!< GPDMA C6CONTROL: D Position         */
+#define GPDMA_C6CONTROL_D_Msk                                 (0x01UL << GPDMA_C6CONTROL_D_Pos)                         /*!< GPDMA C6CONTROL: D Mask             */
+#define GPDMA_C6CONTROL_SI_Pos                                26                                                        /*!< GPDMA C6CONTROL: SI Position        */
+#define GPDMA_C6CONTROL_SI_Msk                                (0x01UL << GPDMA_C6CONTROL_SI_Pos)                        /*!< GPDMA C6CONTROL: SI Mask            */
+#define GPDMA_C6CONTROL_DI_Pos                                27                                                        /*!< GPDMA C6CONTROL: DI Position        */
+#define GPDMA_C6CONTROL_DI_Msk                                (0x01UL << GPDMA_C6CONTROL_DI_Pos)                        /*!< GPDMA C6CONTROL: DI Mask            */
+#define GPDMA_C6CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C6CONTROL: PROT1 Position     */
+#define GPDMA_C6CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT1_Pos)                     /*!< GPDMA C6CONTROL: PROT1 Mask         */
+#define GPDMA_C6CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C6CONTROL: PROT2 Position     */
+#define GPDMA_C6CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT2_Pos)                     /*!< GPDMA C6CONTROL: PROT2 Mask         */
+#define GPDMA_C6CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C6CONTROL: PROT3 Position     */
+#define GPDMA_C6CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT3_Pos)                     /*!< GPDMA C6CONTROL: PROT3 Mask         */
+#define GPDMA_C6CONTROL_I_Pos                                 31                                                        /*!< GPDMA C6CONTROL: I Position         */
+#define GPDMA_C6CONTROL_I_Msk                                 (0x01UL << GPDMA_C6CONTROL_I_Pos)                         /*!< GPDMA C6CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C6CONFIG  -----------------------------------------
+#define GPDMA_C6CONFIG_E_Pos                                  0                                                         /*!< GPDMA C6CONFIG: E Position          */
+#define GPDMA_C6CONFIG_E_Msk                                  (0x01UL << GPDMA_C6CONFIG_E_Pos)                          /*!< GPDMA C6CONFIG: E Mask              */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C6CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C6CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C6CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C6CONFIG: IE Position         */
+#define GPDMA_C6CONFIG_IE_Msk                                 (0x01UL << GPDMA_C6CONFIG_IE_Pos)                         /*!< GPDMA C6CONFIG: IE Mask             */
+#define GPDMA_C6CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C6CONFIG: ITC Position        */
+#define GPDMA_C6CONFIG_ITC_Msk                                (0x01UL << GPDMA_C6CONFIG_ITC_Pos)                        /*!< GPDMA C6CONFIG: ITC Mask            */
+#define GPDMA_C6CONFIG_L_Pos                                  16                                                        /*!< GPDMA C6CONFIG: L Position          */
+#define GPDMA_C6CONFIG_L_Msk                                  (0x01UL << GPDMA_C6CONFIG_L_Pos)                          /*!< GPDMA C6CONFIG: L Mask              */
+#define GPDMA_C6CONFIG_A_Pos                                  17                                                        /*!< GPDMA C6CONFIG: A Position          */
+#define GPDMA_C6CONFIG_A_Msk                                  (0x01UL << GPDMA_C6CONFIG_A_Pos)                          /*!< GPDMA C6CONFIG: A Mask              */
+#define GPDMA_C6CONFIG_H_Pos                                  18                                                        /*!< GPDMA C6CONFIG: H Position          */
+#define GPDMA_C6CONFIG_H_Msk                                  (0x01UL << GPDMA_C6CONFIG_H_Pos)                          /*!< GPDMA C6CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C7SRCADDR  ----------------------------------------
+#define GPDMA_C7SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C7SRCADDR: SRCADDR Position   */
+#define GPDMA_C7SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos)             /*!< GPDMA C7SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C7DESTADDR  ----------------------------------------
+#define GPDMA_C7DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C7DESTADDR: DESTADDR Position */
+#define GPDMA_C7DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos)           /*!< GPDMA C7DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C7LLI  ------------------------------------------
+#define GPDMA_C7LLI_LM_Pos                                    0                                                         /*!< GPDMA C7LLI: LM Position            */
+#define GPDMA_C7LLI_LM_Msk                                    (0x01UL << GPDMA_C7LLI_LM_Pos)                            /*!< GPDMA C7LLI: LM Mask                */
+#define GPDMA_C7LLI_R_Pos                                     1                                                         /*!< GPDMA C7LLI: R Position             */
+#define GPDMA_C7LLI_R_Msk                                     (0x01UL << GPDMA_C7LLI_R_Pos)                             /*!< GPDMA C7LLI: R Mask                 */
+#define GPDMA_C7LLI_LLI_Pos                                   2                                                         /*!< GPDMA C7LLI: LLI Position           */
+#define GPDMA_C7LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos)                     /*!< GPDMA C7LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C7CONTROL  ----------------------------------------
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C7CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C7CONTROL: SBSIZE Position    */
+#define GPDMA_C7CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos)                    /*!< GPDMA C7CONTROL: SBSIZE Mask        */
+#define GPDMA_C7CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C7CONTROL: DBSIZE Position    */
+#define GPDMA_C7CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos)                    /*!< GPDMA C7CONTROL: DBSIZE Mask        */
+#define GPDMA_C7CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C7CONTROL: SWIDTH Position    */
+#define GPDMA_C7CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos)                    /*!< GPDMA C7CONTROL: SWIDTH Mask        */
+#define GPDMA_C7CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C7CONTROL: DWIDTH Position    */
+#define GPDMA_C7CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos)                    /*!< GPDMA C7CONTROL: DWIDTH Mask        */
+#define GPDMA_C7CONTROL_S_Pos                                 24                                                        /*!< GPDMA C7CONTROL: S Position         */
+#define GPDMA_C7CONTROL_S_Msk                                 (0x01UL << GPDMA_C7CONTROL_S_Pos)                         /*!< GPDMA C7CONTROL: S Mask             */
+#define GPDMA_C7CONTROL_D_Pos                                 25                                                        /*!< GPDMA C7CONTROL: D Position         */
+#define GPDMA_C7CONTROL_D_Msk                                 (0x01UL << GPDMA_C7CONTROL_D_Pos)                         /*!< GPDMA C7CONTROL: D Mask             */
+#define GPDMA_C7CONTROL_SI_Pos                                26                                                        /*!< GPDMA C7CONTROL: SI Position        */
+#define GPDMA_C7CONTROL_SI_Msk                                (0x01UL << GPDMA_C7CONTROL_SI_Pos)                        /*!< GPDMA C7CONTROL: SI Mask            */
+#define GPDMA_C7CONTROL_DI_Pos                                27                                                        /*!< GPDMA C7CONTROL: DI Position        */
+#define GPDMA_C7CONTROL_DI_Msk                                (0x01UL << GPDMA_C7CONTROL_DI_Pos)                        /*!< GPDMA C7CONTROL: DI Mask            */
+#define GPDMA_C7CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C7CONTROL: PROT1 Position     */
+#define GPDMA_C7CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT1_Pos)                     /*!< GPDMA C7CONTROL: PROT1 Mask         */
+#define GPDMA_C7CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C7CONTROL: PROT2 Position     */
+#define GPDMA_C7CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT2_Pos)                     /*!< GPDMA C7CONTROL: PROT2 Mask         */
+#define GPDMA_C7CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C7CONTROL: PROT3 Position     */
+#define GPDMA_C7CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT3_Pos)                     /*!< GPDMA C7CONTROL: PROT3 Mask         */
+#define GPDMA_C7CONTROL_I_Pos                                 31                                                        /*!< GPDMA C7CONTROL: I Position         */
+#define GPDMA_C7CONTROL_I_Msk                                 (0x01UL << GPDMA_C7CONTROL_I_Pos)                         /*!< GPDMA C7CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C7CONFIG  -----------------------------------------
+#define GPDMA_C7CONFIG_E_Pos                                  0                                                         /*!< GPDMA C7CONFIG: E Position          */
+#define GPDMA_C7CONFIG_E_Msk                                  (0x01UL << GPDMA_C7CONFIG_E_Pos)                          /*!< GPDMA C7CONFIG: E Mask              */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C7CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C7CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C7CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C7CONFIG: IE Position         */
+#define GPDMA_C7CONFIG_IE_Msk                                 (0x01UL << GPDMA_C7CONFIG_IE_Pos)                         /*!< GPDMA C7CONFIG: IE Mask             */
+#define GPDMA_C7CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C7CONFIG: ITC Position        */
+#define GPDMA_C7CONFIG_ITC_Msk                                (0x01UL << GPDMA_C7CONFIG_ITC_Pos)                        /*!< GPDMA C7CONFIG: ITC Mask            */
+#define GPDMA_C7CONFIG_L_Pos                                  16                                                        /*!< GPDMA C7CONFIG: L Position          */
+#define GPDMA_C7CONFIG_L_Msk                                  (0x01UL << GPDMA_C7CONFIG_L_Pos)                          /*!< GPDMA C7CONFIG: L Mask              */
+#define GPDMA_C7CONFIG_A_Pos                                  17                                                        /*!< GPDMA C7CONFIG: A Position          */
+#define GPDMA_C7CONFIG_A_Msk                                  (0x01UL << GPDMA_C7CONFIG_A_Pos)                          /*!< GPDMA C7CONFIG: A Mask              */
+#define GPDMA_C7CONFIG_H_Pos                                  18                                                        /*!< GPDMA C7CONFIG: H Position          */
+#define GPDMA_C7CONFIG_H_Msk                                  (0x01UL << GPDMA_C7CONFIG_H_Pos)                          /*!< GPDMA C7CONFIG: H Mask              */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SDMMC Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  SDMMC_CTRL  -------------------------------------------
+#define SDMMC_CTRL_CONTROLLER_RESET_Pos                       0                                                         /*!< SDMMC CTRL: CONTROLLER_RESET Position */
+#define SDMMC_CTRL_CONTROLLER_RESET_Msk                       (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos)               /*!< SDMMC CTRL: CONTROLLER_RESET Mask   */
+#define SDMMC_CTRL_FIFO_RESET_Pos                             1                                                         /*!< SDMMC CTRL: FIFO_RESET Position     */
+#define SDMMC_CTRL_FIFO_RESET_Msk                             (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos)                     /*!< SDMMC CTRL: FIFO_RESET Mask         */
+#define SDMMC_CTRL_DMA_RESET_Pos                              2                                                         /*!< SDMMC CTRL: DMA_RESET Position      */
+#define SDMMC_CTRL_DMA_RESET_Msk                              (0x01UL << SDMMC_CTRL_DMA_RESET_Pos)                      /*!< SDMMC CTRL: DMA_RESET Mask          */
+#define SDMMC_CTRL_INT_ENABLE_Pos                             4                                                         /*!< SDMMC CTRL: INT_ENABLE Position     */
+#define SDMMC_CTRL_INT_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos)                     /*!< SDMMC CTRL: INT_ENABLE Mask         */
+#define SDMMC_CTRL_DMA_ENABLE_Pos                             5                                                         /*!< SDMMC CTRL: DMA_ENABLE Position     */
+#define SDMMC_CTRL_DMA_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos)                     /*!< SDMMC CTRL: DMA_ENABLE Mask         */
+#define SDMMC_CTRL_READ_WAIT_Pos                              6                                                         /*!< SDMMC CTRL: READ_WAIT Position      */
+#define SDMMC_CTRL_READ_WAIT_Msk                              (0x01UL << SDMMC_CTRL_READ_WAIT_Pos)                      /*!< SDMMC CTRL: READ_WAIT Mask          */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos                      7                                                         /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk                      (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos)              /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask  */
+#define SDMMC_CTRL_ABORT_READ_DATA_Pos                        8                                                         /*!< SDMMC CTRL: ABORT_READ_DATA Position */
+#define SDMMC_CTRL_ABORT_READ_DATA_Msk                        (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos)                /*!< SDMMC CTRL: ABORT_READ_DATA Mask    */
+#define SDMMC_CTRL_SEND_CCSD_Pos                              9                                                         /*!< SDMMC CTRL: SEND_CCSD Position      */
+#define SDMMC_CTRL_SEND_CCSD_Msk                              (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos)                      /*!< SDMMC CTRL: SEND_CCSD Mask          */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos                    10                                                        /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk                    (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos)            /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos          11                                                        /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk          (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)  /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos                         16                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask     */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos                         20                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask     */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos                       24                                                        /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk                       (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos)               /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask   */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos                      25                                                        /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk                      (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos)              /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask  */
+
+// ---------------------------------------  SDMMC_PWREN  ------------------------------------------
+#define SDMMC_PWREN_POWER_ENABLE_Pos                          0                                                         /*!< SDMMC PWREN: POWER_ENABLE Position  */
+#define SDMMC_PWREN_POWER_ENABLE_Msk                          (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos)            /*!< SDMMC PWREN: POWER_ENABLE Mask      */
+
+// --------------------------------------  SDMMC_CLKDIV  ------------------------------------------
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos                         0                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask     */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos                         8                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask     */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos                         16                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask     */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos                         24                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask     */
+
+// --------------------------------------  SDMMC_CLKSRC  ------------------------------------------
+#define SDMMC_CLKSRC_CLK_SOURCE_Pos                           0                                                         /*!< SDMMC CLKSRC: CLK_SOURCE Position   */
+#define SDMMC_CLKSRC_CLK_SOURCE_Msk                           (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos)             /*!< SDMMC CLKSRC: CLK_SOURCE Mask       */
+
+// --------------------------------------  SDMMC_CLKENA  ------------------------------------------
+#define SDMMC_CLKENA_CCLK_ENABLE_Pos                          0                                                         /*!< SDMMC CLKENA: CCLK_ENABLE Position  */
+#define SDMMC_CLKENA_CCLK_ENABLE_Msk                          (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos)            /*!< SDMMC CLKENA: CCLK_ENABLE Mask      */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos                       16                                                        /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk                       (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos)         /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask   */
+
+// ---------------------------------------  SDMMC_TMOUT  ------------------------------------------
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos                      0                                                         /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk                      (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos)        /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask  */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Pos                          8                                                         /*!< SDMMC TMOUT: DATA_TIMEOUT Position  */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Msk                          (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos)            /*!< SDMMC TMOUT: DATA_TIMEOUT Mask      */
+
+// ---------------------------------------  SDMMC_CTYPE  ------------------------------------------
+#define SDMMC_CTYPE_CARD_WIDTH0_Pos                           0                                                         /*!< SDMMC CTYPE: CARD_WIDTH0 Position   */
+#define SDMMC_CTYPE_CARD_WIDTH0_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH0 Mask       */
+#define SDMMC_CTYPE_CARD_WIDTH1_Pos                           16                                                        /*!< SDMMC CTYPE: CARD_WIDTH1 Position   */
+#define SDMMC_CTYPE_CARD_WIDTH1_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH1 Mask       */
+
+// --------------------------------------  SDMMC_BLKSIZ  ------------------------------------------
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos                           0                                                         /*!< SDMMC BLKSIZ: BLOCK_SIZE Position   */
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk                           (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos)             /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask       */
+
+// --------------------------------------  SDMMC_BYTCNT  ------------------------------------------
+#define SDMMC_BYTCNT_BYTE_COUNT_Pos                           0                                                         /*!< SDMMC BYTCNT: BYTE_COUNT Position   */
+#define SDMMC_BYTCNT_BYTE_COUNT_Msk                           (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos)             /*!< SDMMC BYTCNT: BYTE_COUNT Mask       */
+
+// --------------------------------------  SDMMC_INTMASK  -----------------------------------------
+#define SDMMC_INTMASK_CDET_Pos                                0                                                         /*!< SDMMC INTMASK: CDET Position        */
+#define SDMMC_INTMASK_CDET_Msk                                (0x01UL << SDMMC_INTMASK_CDET_Pos)                        /*!< SDMMC INTMASK: CDET Mask            */
+#define SDMMC_INTMASK_RE_Pos                                  1                                                         /*!< SDMMC INTMASK: RE Position          */
+#define SDMMC_INTMASK_RE_Msk                                  (0x01UL << SDMMC_INTMASK_RE_Pos)                          /*!< SDMMC INTMASK: RE Mask              */
+#define SDMMC_INTMASK_CDONE_Pos                               2                                                         /*!< SDMMC INTMASK: CDONE Position       */
+#define SDMMC_INTMASK_CDONE_Msk                               (0x01UL << SDMMC_INTMASK_CDONE_Pos)                       /*!< SDMMC INTMASK: CDONE Mask           */
+#define SDMMC_INTMASK_DTO_Pos                                 3                                                         /*!< SDMMC INTMASK: DTO Position         */
+#define SDMMC_INTMASK_DTO_Msk                                 (0x01UL << SDMMC_INTMASK_DTO_Pos)                         /*!< SDMMC INTMASK: DTO Mask             */
+#define SDMMC_INTMASK_TXDR_Pos                                4                                                         /*!< SDMMC INTMASK: TXDR Position        */
+#define SDMMC_INTMASK_TXDR_Msk                                (0x01UL << SDMMC_INTMASK_TXDR_Pos)                        /*!< SDMMC INTMASK: TXDR Mask            */
+#define SDMMC_INTMASK_RXDR_Pos                                5                                                         /*!< SDMMC INTMASK: RXDR Position        */
+#define SDMMC_INTMASK_RXDR_Msk                                (0x01UL << SDMMC_INTMASK_RXDR_Pos)                        /*!< SDMMC INTMASK: RXDR Mask            */
+#define SDMMC_INTMASK_RCRC_Pos                                6                                                         /*!< SDMMC INTMASK: RCRC Position        */
+#define SDMMC_INTMASK_RCRC_Msk                                (0x01UL << SDMMC_INTMASK_RCRC_Pos)                        /*!< SDMMC INTMASK: RCRC Mask            */
+#define SDMMC_INTMASK_DCRC_Pos                                7                                                         /*!< SDMMC INTMASK: DCRC Position        */
+#define SDMMC_INTMASK_DCRC_Msk                                (0x01UL << SDMMC_INTMASK_DCRC_Pos)                        /*!< SDMMC INTMASK: DCRC Mask            */
+#define SDMMC_INTMASK_RTO_Pos                                 8                                                         /*!< SDMMC INTMASK: RTO Position         */
+#define SDMMC_INTMASK_RTO_Msk                                 (0x01UL << SDMMC_INTMASK_RTO_Pos)                         /*!< SDMMC INTMASK: RTO Mask             */
+#define SDMMC_INTMASK_DRTO_Pos                                9                                                         /*!< SDMMC INTMASK: DRTO Position        */
+#define SDMMC_INTMASK_DRTO_Msk                                (0x01UL << SDMMC_INTMASK_DRTO_Pos)                        /*!< SDMMC INTMASK: DRTO Mask            */
+#define SDMMC_INTMASK_HTO_Pos                                 10                                                        /*!< SDMMC INTMASK: HTO Position         */
+#define SDMMC_INTMASK_HTO_Msk                                 (0x01UL << SDMMC_INTMASK_HTO_Pos)                         /*!< SDMMC INTMASK: HTO Mask             */
+#define SDMMC_INTMASK_FRUN_Pos                                11                                                        /*!< SDMMC INTMASK: FRUN Position        */
+#define SDMMC_INTMASK_FRUN_Msk                                (0x01UL << SDMMC_INTMASK_FRUN_Pos)                        /*!< SDMMC INTMASK: FRUN Mask            */
+#define SDMMC_INTMASK_HLE_Pos                                 12                                                        /*!< SDMMC INTMASK: HLE Position         */
+#define SDMMC_INTMASK_HLE_Msk                                 (0x01UL << SDMMC_INTMASK_HLE_Pos)                         /*!< SDMMC INTMASK: HLE Mask             */
+#define SDMMC_INTMASK_SBE_Pos                                 13                                                        /*!< SDMMC INTMASK: SBE Position         */
+#define SDMMC_INTMASK_SBE_Msk                                 (0x01UL << SDMMC_INTMASK_SBE_Pos)                         /*!< SDMMC INTMASK: SBE Mask             */
+#define SDMMC_INTMASK_ACD_Pos                                 14                                                        /*!< SDMMC INTMASK: ACD Position         */
+#define SDMMC_INTMASK_ACD_Msk                                 (0x01UL << SDMMC_INTMASK_ACD_Pos)                         /*!< SDMMC INTMASK: ACD Mask             */
+#define SDMMC_INTMASK_EBE_Pos                                 15                                                        /*!< SDMMC INTMASK: EBE Position         */
+#define SDMMC_INTMASK_EBE_Msk                                 (0x01UL << SDMMC_INTMASK_EBE_Pos)                         /*!< SDMMC INTMASK: EBE Mask             */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Pos                       16                                                        /*!< SDMMC INTMASK: SDIO_INT_MASK Position */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Msk                       (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos)         /*!< SDMMC INTMASK: SDIO_INT_MASK Mask   */
+
+// --------------------------------------  SDMMC_CMDARG  ------------------------------------------
+#define SDMMC_CMDARG_CMD_ARG_Pos                              0                                                         /*!< SDMMC CMDARG: CMD_ARG Position      */
+#define SDMMC_CMDARG_CMD_ARG_Msk                              (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos)                /*!< SDMMC CMDARG: CMD_ARG Mask          */
+
+// ----------------------------------------  SDMMC_CMD  -------------------------------------------
+#define SDMMC_CMD_CMD_INDEX_Pos                               0                                                         /*!< SDMMC CMD: CMD_INDEX Position       */
+#define SDMMC_CMD_CMD_INDEX_Msk                               (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos)                       /*!< SDMMC CMD: CMD_INDEX Mask           */
+#define SDMMC_CMD_RESPONSE_EXPECT_Pos                         6                                                         /*!< SDMMC CMD: RESPONSE_EXPECT Position */
+#define SDMMC_CMD_RESPONSE_EXPECT_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos)                 /*!< SDMMC CMD: RESPONSE_EXPECT Mask     */
+#define SDMMC_CMD_RESPONSE_LENGTH_Pos                         7                                                         /*!< SDMMC CMD: RESPONSE_LENGTH Position */
+#define SDMMC_CMD_RESPONSE_LENGTH_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos)                 /*!< SDMMC CMD: RESPONSE_LENGTH Mask     */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos                      8                                                         /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk                      (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos)              /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask  */
+#define SDMMC_CMD_DATA_EXPECTED_Pos                           9                                                         /*!< SDMMC CMD: DATA_EXPECTED Position   */
+#define SDMMC_CMD_DATA_EXPECTED_Msk                           (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos)                   /*!< SDMMC CMD: DATA_EXPECTED Mask       */
+#define SDMMC_CMD_READ_WRITE_Pos                              10                                                        /*!< SDMMC CMD: READ_WRITE Position      */
+#define SDMMC_CMD_READ_WRITE_Msk                              (0x01UL << SDMMC_CMD_READ_WRITE_Pos)                      /*!< SDMMC CMD: READ_WRITE Mask          */
+#define SDMMC_CMD_TRANSFER_MODE_Pos                           11                                                        /*!< SDMMC CMD: TRANSFER_MODE Position   */
+#define SDMMC_CMD_TRANSFER_MODE_Msk                           (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos)                   /*!< SDMMC CMD: TRANSFER_MODE Mask       */
+#define SDMMC_CMD_SEND_AUTO_STOP_Pos                          12                                                        /*!< SDMMC CMD: SEND_AUTO_STOP Position  */
+#define SDMMC_CMD_SEND_AUTO_STOP_Msk                          (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos)                  /*!< SDMMC CMD: SEND_AUTO_STOP Mask      */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos                   13                                                        /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk                   (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos)           /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */
+#define SDMMC_CMD_STOP_ABORT_CMd_Pos                          14                                                        /*!< SDMMC CMD: STOP_ABORT_CMd Position  */
+#define SDMMC_CMD_STOP_ABORT_CMd_Msk                          (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos)                  /*!< SDMMC CMD: STOP_ABORT_CMd Mask      */
+#define SDMMC_CMD_SEND_INITIALIZATION_Pos                     15                                                        /*!< SDMMC CMD: SEND_INITIALIZATION Position */
+#define SDMMC_CMD_SEND_INITIALIZATION_Msk                     (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos)             /*!< SDMMC CMD: SEND_INITIALIZATION Mask */
+#define SDMMC_CMD_CARD_NUMBER_Pos                             16                                                        /*!< SDMMC CMD: CARD_NUMBER Position     */
+#define SDMMC_CMD_CARD_NUMBER_Msk                             (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos)                     /*!< SDMMC CMD: CARD_NUMBER Mask         */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos             21                                                        /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk             (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)     /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Pos                       22                                                        /*!< SDMMC CMD: READ_CEATA_DEVICE Position */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Msk                       (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos)               /*!< SDMMC CMD: READ_CEATA_DEVICE Mask   */
+#define SDMMC_CMD_CCS_EXPECTED_Pos                            23                                                        /*!< SDMMC CMD: CCS_EXPECTED Position    */
+#define SDMMC_CMD_CCS_EXPECTED_Msk                            (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos)                    /*!< SDMMC CMD: CCS_EXPECTED Mask        */
+#define SDMMC_CMD_ENABLE_BOOT_Pos                             24                                                        /*!< SDMMC CMD: ENABLE_BOOT Position     */
+#define SDMMC_CMD_ENABLE_BOOT_Msk                             (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos)                     /*!< SDMMC CMD: ENABLE_BOOT Mask         */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos                         25                                                        /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk                         (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos)                 /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask     */
+#define SDMMC_CMD_DISABLE_BOOT_Pos                            26                                                        /*!< SDMMC CMD: DISABLE_BOOT Position    */
+#define SDMMC_CMD_DISABLE_BOOT_Msk                            (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos)                    /*!< SDMMC CMD: DISABLE_BOOT Mask        */
+#define SDMMC_CMD_BOOT_MODE_Pos                               27                                                        /*!< SDMMC CMD: BOOT_MODE Position       */
+#define SDMMC_CMD_BOOT_MODE_Msk                               (0x01UL << SDMMC_CMD_BOOT_MODE_Pos)                       /*!< SDMMC CMD: BOOT_MODE Mask           */
+#define SDMMC_CMD_VOLT_SWITCH_Pos                             28                                                        /*!< SDMMC CMD: VOLT_SWITCH Position     */
+#define SDMMC_CMD_VOLT_SWITCH_Msk                             (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos)                     /*!< SDMMC CMD: VOLT_SWITCH Mask         */
+#define SDMMC_CMD_START_CMD_Pos                               31                                                        /*!< SDMMC CMD: START_CMD Position       */
+#define SDMMC_CMD_START_CMD_Msk                               (0x01UL << SDMMC_CMD_START_CMD_Pos)                       /*!< SDMMC CMD: START_CMD Mask           */
+
+// ---------------------------------------  SDMMC_RESP0  ------------------------------------------
+#define SDMMC_RESP0_RESPONSE0_Pos                             0                                                         /*!< SDMMC RESP0: RESPONSE0 Position     */
+#define SDMMC_RESP0_RESPONSE0_Msk                             (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos)               /*!< SDMMC RESP0: RESPONSE0 Mask         */
+
+// ---------------------------------------  SDMMC_RESP1  ------------------------------------------
+#define SDMMC_RESP1_RESPONSE1_Pos                             0                                                         /*!< SDMMC RESP1: RESPONSE1 Position     */
+#define SDMMC_RESP1_RESPONSE1_Msk                             (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos)               /*!< SDMMC RESP1: RESPONSE1 Mask         */
+
+// ---------------------------------------  SDMMC_RESP2  ------------------------------------------
+#define SDMMC_RESP2_RESPONSE2_Pos                             0                                                         /*!< SDMMC RESP2: RESPONSE2 Position     */
+#define SDMMC_RESP2_RESPONSE2_Msk                             (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos)               /*!< SDMMC RESP2: RESPONSE2 Mask         */
+
+// ---------------------------------------  SDMMC_RESP3  ------------------------------------------
+#define SDMMC_RESP3_RESPONSE3_Pos                             0                                                         /*!< SDMMC RESP3: RESPONSE3 Position     */
+#define SDMMC_RESP3_RESPONSE3_Msk                             (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos)               /*!< SDMMC RESP3: RESPONSE3 Mask         */
+
+// --------------------------------------  SDMMC_MINTSTS  -----------------------------------------
+#define SDMMC_MINTSTS_CDET_Pos                                0                                                         /*!< SDMMC MINTSTS: CDET Position        */
+#define SDMMC_MINTSTS_CDET_Msk                                (0x01UL << SDMMC_MINTSTS_CDET_Pos)                        /*!< SDMMC MINTSTS: CDET Mask            */
+#define SDMMC_MINTSTS_RE_Pos                                  1                                                         /*!< SDMMC MINTSTS: RE Position          */
+#define SDMMC_MINTSTS_RE_Msk                                  (0x01UL << SDMMC_MINTSTS_RE_Pos)                          /*!< SDMMC MINTSTS: RE Mask              */
+#define SDMMC_MINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC MINTSTS: CDONE Position       */
+#define SDMMC_MINTSTS_CDONE_Msk                               (0x01UL << SDMMC_MINTSTS_CDONE_Pos)                       /*!< SDMMC MINTSTS: CDONE Mask           */
+#define SDMMC_MINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC MINTSTS: DTO Position         */
+#define SDMMC_MINTSTS_DTO_Msk                                 (0x01UL << SDMMC_MINTSTS_DTO_Pos)                         /*!< SDMMC MINTSTS: DTO Mask             */
+#define SDMMC_MINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC MINTSTS: TXDR Position        */
+#define SDMMC_MINTSTS_TXDR_Msk                                (0x01UL << SDMMC_MINTSTS_TXDR_Pos)                        /*!< SDMMC MINTSTS: TXDR Mask            */
+#define SDMMC_MINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC MINTSTS: RXDR Position        */
+#define SDMMC_MINTSTS_RXDR_Msk                                (0x01UL << SDMMC_MINTSTS_RXDR_Pos)                        /*!< SDMMC MINTSTS: RXDR Mask            */
+#define SDMMC_MINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC MINTSTS: RCRC Position        */
+#define SDMMC_MINTSTS_RCRC_Msk                                (0x01UL << SDMMC_MINTSTS_RCRC_Pos)                        /*!< SDMMC MINTSTS: RCRC Mask            */
+#define SDMMC_MINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC MINTSTS: DCRC Position        */
+#define SDMMC_MINTSTS_DCRC_Msk                                (0x01UL << SDMMC_MINTSTS_DCRC_Pos)                        /*!< SDMMC MINTSTS: DCRC Mask            */
+#define SDMMC_MINTSTS_RTO_Pos                                 8                                                         /*!< SDMMC MINTSTS: RTO Position         */
+#define SDMMC_MINTSTS_RTO_Msk                                 (0x01UL << SDMMC_MINTSTS_RTO_Pos)                         /*!< SDMMC MINTSTS: RTO Mask             */
+#define SDMMC_MINTSTS_DRTO_Pos                                9                                                         /*!< SDMMC MINTSTS: DRTO Position        */
+#define SDMMC_MINTSTS_DRTO_Msk                                (0x01UL << SDMMC_MINTSTS_DRTO_Pos)                        /*!< SDMMC MINTSTS: DRTO Mask            */
+#define SDMMC_MINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC MINTSTS: HTO Position         */
+#define SDMMC_MINTSTS_HTO_Msk                                 (0x01UL << SDMMC_MINTSTS_HTO_Pos)                         /*!< SDMMC MINTSTS: HTO Mask             */
+#define SDMMC_MINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC MINTSTS: FRUN Position        */
+#define SDMMC_MINTSTS_FRUN_Msk                                (0x01UL << SDMMC_MINTSTS_FRUN_Pos)                        /*!< SDMMC MINTSTS: FRUN Mask            */
+#define SDMMC_MINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC MINTSTS: HLE Position         */
+#define SDMMC_MINTSTS_HLE_Msk                                 (0x01UL << SDMMC_MINTSTS_HLE_Pos)                         /*!< SDMMC MINTSTS: HLE Mask             */
+#define SDMMC_MINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC MINTSTS: SBE Position         */
+#define SDMMC_MINTSTS_SBE_Msk                                 (0x01UL << SDMMC_MINTSTS_SBE_Pos)                         /*!< SDMMC MINTSTS: SBE Mask             */
+#define SDMMC_MINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC MINTSTS: ACD Position         */
+#define SDMMC_MINTSTS_ACD_Msk                                 (0x01UL << SDMMC_MINTSTS_ACD_Pos)                         /*!< SDMMC MINTSTS: ACD Mask             */
+#define SDMMC_MINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC MINTSTS: EBE Position         */
+#define SDMMC_MINTSTS_EBE_Msk                                 (0x01UL << SDMMC_MINTSTS_EBE_Pos)                         /*!< SDMMC MINTSTS: EBE Mask             */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask  */
+
+// --------------------------------------  SDMMC_RINTSTS  -----------------------------------------
+#define SDMMC_RINTSTS_CDET_Pos                                0                                                         /*!< SDMMC RINTSTS: CDET Position        */
+#define SDMMC_RINTSTS_CDET_Msk                                (0x01UL << SDMMC_RINTSTS_CDET_Pos)                        /*!< SDMMC RINTSTS: CDET Mask            */
+#define SDMMC_RINTSTS_RE_Pos                                  1                                                         /*!< SDMMC RINTSTS: RE Position          */
+#define SDMMC_RINTSTS_RE_Msk                                  (0x01UL << SDMMC_RINTSTS_RE_Pos)                          /*!< SDMMC RINTSTS: RE Mask              */
+#define SDMMC_RINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC RINTSTS: CDONE Position       */
+#define SDMMC_RINTSTS_CDONE_Msk                               (0x01UL << SDMMC_RINTSTS_CDONE_Pos)                       /*!< SDMMC RINTSTS: CDONE Mask           */
+#define SDMMC_RINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC RINTSTS: DTO Position         */
+#define SDMMC_RINTSTS_DTO_Msk                                 (0x01UL << SDMMC_RINTSTS_DTO_Pos)                         /*!< SDMMC RINTSTS: DTO Mask             */
+#define SDMMC_RINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC RINTSTS: TXDR Position        */
+#define SDMMC_RINTSTS_TXDR_Msk                                (0x01UL << SDMMC_RINTSTS_TXDR_Pos)                        /*!< SDMMC RINTSTS: TXDR Mask            */
+#define SDMMC_RINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC RINTSTS: RXDR Position        */
+#define SDMMC_RINTSTS_RXDR_Msk                                (0x01UL << SDMMC_RINTSTS_RXDR_Pos)                        /*!< SDMMC RINTSTS: RXDR Mask            */
+#define SDMMC_RINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC RINTSTS: RCRC Position        */
+#define SDMMC_RINTSTS_RCRC_Msk                                (0x01UL << SDMMC_RINTSTS_RCRC_Pos)                        /*!< SDMMC RINTSTS: RCRC Mask            */
+#define SDMMC_RINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC RINTSTS: DCRC Position        */
+#define SDMMC_RINTSTS_DCRC_Msk                                (0x01UL << SDMMC_RINTSTS_DCRC_Pos)                        /*!< SDMMC RINTSTS: DCRC Mask            */
+#define SDMMC_RINTSTS_RTO_BAR_Pos                             8                                                         /*!< SDMMC RINTSTS: RTO_BAR Position     */
+#define SDMMC_RINTSTS_RTO_BAR_Msk                             (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos)                     /*!< SDMMC RINTSTS: RTO_BAR Mask         */
+#define SDMMC_RINTSTS_DRTO_BDS_Pos                            9                                                         /*!< SDMMC RINTSTS: DRTO_BDS Position    */
+#define SDMMC_RINTSTS_DRTO_BDS_Msk                            (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos)                    /*!< SDMMC RINTSTS: DRTO_BDS Mask        */
+#define SDMMC_RINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC RINTSTS: HTO Position         */
+#define SDMMC_RINTSTS_HTO_Msk                                 (0x01UL << SDMMC_RINTSTS_HTO_Pos)                         /*!< SDMMC RINTSTS: HTO Mask             */
+#define SDMMC_RINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC RINTSTS: FRUN Position        */
+#define SDMMC_RINTSTS_FRUN_Msk                                (0x01UL << SDMMC_RINTSTS_FRUN_Pos)                        /*!< SDMMC RINTSTS: FRUN Mask            */
+#define SDMMC_RINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC RINTSTS: HLE Position         */
+#define SDMMC_RINTSTS_HLE_Msk                                 (0x01UL << SDMMC_RINTSTS_HLE_Pos)                         /*!< SDMMC RINTSTS: HLE Mask             */
+#define SDMMC_RINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC RINTSTS: SBE Position         */
+#define SDMMC_RINTSTS_SBE_Msk                                 (0x01UL << SDMMC_RINTSTS_SBE_Pos)                         /*!< SDMMC RINTSTS: SBE Mask             */
+#define SDMMC_RINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC RINTSTS: ACD Position         */
+#define SDMMC_RINTSTS_ACD_Msk                                 (0x01UL << SDMMC_RINTSTS_ACD_Pos)                         /*!< SDMMC RINTSTS: ACD Mask             */
+#define SDMMC_RINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC RINTSTS: EBE Position         */
+#define SDMMC_RINTSTS_EBE_Msk                                 (0x01UL << SDMMC_RINTSTS_EBE_Pos)                         /*!< SDMMC RINTSTS: EBE Mask             */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask  */
+
+// --------------------------------------  SDMMC_STATUS  ------------------------------------------
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos                    0                                                         /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos                    1                                                         /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_EMPTY_Pos                           2                                                         /*!< SDMMC STATUS: FIFO_EMPTY Position   */
+#define SDMMC_STATUS_FIFO_EMPTY_Msk                           (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos)                   /*!< SDMMC STATUS: FIFO_EMPTY Mask       */
+#define SDMMC_STATUS_FIFO_FULL_Pos                            3                                                         /*!< SDMMC STATUS: FIFO_FULL Position    */
+#define SDMMC_STATUS_FIFO_FULL_Msk                            (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos)                    /*!< SDMMC STATUS: FIFO_FULL Mask        */
+#define SDMMC_STATUS_CMDFSMSTATES_Pos                         4                                                         /*!< SDMMC STATUS: CMDFSMSTATES Position */
+#define SDMMC_STATUS_CMDFSMSTATES_Msk                         (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos)                 /*!< SDMMC STATUS: CMDFSMSTATES Mask     */
+#define SDMMC_STATUS_DATA_3_STATUS_Pos                        8                                                         /*!< SDMMC STATUS: DATA_3_STATUS Position */
+#define SDMMC_STATUS_DATA_3_STATUS_Msk                        (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos)                /*!< SDMMC STATUS: DATA_3_STATUS Mask    */
+#define SDMMC_STATUS_DATA_BUSY_Pos                            9                                                         /*!< SDMMC STATUS: DATA_BUSY Position    */
+#define SDMMC_STATUS_DATA_BUSY_Msk                            (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos)                    /*!< SDMMC STATUS: DATA_BUSY Mask        */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos                   10                                                        /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk                   (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos)           /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */
+#define SDMMC_STATUS_RESPONSE_INDEX_Pos                       11                                                        /*!< SDMMC STATUS: RESPONSE_INDEX Position */
+#define SDMMC_STATUS_RESPONSE_INDEX_Msk                       (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos)               /*!< SDMMC STATUS: RESPONSE_INDEX Mask   */
+#define SDMMC_STATUS_FIFO_COUNT_Pos                           17                                                        /*!< SDMMC STATUS: FIFO_COUNT Position   */
+#define SDMMC_STATUS_FIFO_COUNT_Msk                           (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos)             /*!< SDMMC STATUS: FIFO_COUNT Mask       */
+#define SDMMC_STATUS_DMA_ACK_Pos                              30                                                        /*!< SDMMC STATUS: DMA_ACK Position      */
+#define SDMMC_STATUS_DMA_ACK_Msk                              (0x01UL << SDMMC_STATUS_DMA_ACK_Pos)                      /*!< SDMMC STATUS: DMA_ACK Mask          */
+#define SDMMC_STATUS_DMA_REQ_Pos                              31                                                        /*!< SDMMC STATUS: DMA_REQ Position      */
+#define SDMMC_STATUS_DMA_REQ_Msk                              (0x01UL << SDMMC_STATUS_DMA_REQ_Pos)                      /*!< SDMMC STATUS: DMA_REQ Mask          */
+
+// --------------------------------------  SDMMC_FIFOTH  ------------------------------------------
+#define SDMMC_FIFOTH_TX_WMARK_Pos                             0                                                         /*!< SDMMC FIFOTH: TX_WMARK Position     */
+#define SDMMC_FIFOTH_TX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos)               /*!< SDMMC FIFOTH: TX_WMARK Mask         */
+#define SDMMC_FIFOTH_RX_WMARK_Pos                             16                                                        /*!< SDMMC FIFOTH: RX_WMARK Position     */
+#define SDMMC_FIFOTH_RX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos)               /*!< SDMMC FIFOTH: RX_WMARK Mask         */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos      28                                                        /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk      (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */
+
+// --------------------------------------  SDMMC_CDETECT  -----------------------------------------
+#define SDMMC_CDETECT_CARD_DETECT_N_Pos                       0                                                         /*!< SDMMC CDETECT: CARD_DETECT_N Position */
+#define SDMMC_CDETECT_CARD_DETECT_N_Msk                       (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos)         /*!< SDMMC CDETECT: CARD_DETECT_N Mask   */
+
+// --------------------------------------  SDMMC_WRTPRT  ------------------------------------------
+#define SDMMC_WRTPRT_WRITE_PROTECT_Pos                        0                                                         /*!< SDMMC WRTPRT: WRITE_PROTECT Position */
+#define SDMMC_WRTPRT_WRITE_PROTECT_Msk                        (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos)          /*!< SDMMC WRTPRT: WRITE_PROTECT Mask    */
+
+// ---------------------------------------  SDMMC_GPIO  -------------------------------------------
+#define SDMMC_GPIO_GPI_Pos                                    0                                                         /*!< SDMMC GPIO: GPI Position            */
+#define SDMMC_GPIO_GPI_Msk                                    (0x000000ffUL << SDMMC_GPIO_GPI_Pos)                      /*!< SDMMC GPIO: GPI Mask                */
+#define SDMMC_GPIO_GPO_Pos                                    8                                                         /*!< SDMMC GPIO: GPO Position            */
+#define SDMMC_GPIO_GPO_Msk                                    (0x0000ffffUL << SDMMC_GPIO_GPO_Pos)                      /*!< SDMMC GPIO: GPO Mask                */
+
+// --------------------------------------  SDMMC_TCBCNT  ------------------------------------------
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)  /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */
+
+// --------------------------------------  SDMMC_TBBCNT  ------------------------------------------
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)  /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */
+
+// --------------------------------------  SDMMC_DEBNCE  ------------------------------------------
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos                       0                                                         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk                       (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos)         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask   */
+
+// ---------------------------------------  SDMMC_USRID  ------------------------------------------
+#define SDMMC_USRID_USRID_Pos                                 0                                                         /*!< SDMMC USRID: USRID Position         */
+#define SDMMC_USRID_USRID_Msk                                 (0xffffffffUL << SDMMC_USRID_USRID_Pos)                   /*!< SDMMC USRID: USRID Mask             */
+
+// ---------------------------------------  SDMMC_VERID  ------------------------------------------
+#define SDMMC_VERID_VERID_Pos                                 0                                                         /*!< SDMMC VERID: VERID Position         */
+#define SDMMC_VERID_VERID_Msk                                 (0xffffffffUL << SDMMC_VERID_VERID_Pos)                   /*!< SDMMC VERID: VERID Mask             */
+
+// --------------------------------------  SDMMC_UHS_REG  -----------------------------------------
+#define SDMMC_UHS_REG_VOLT_REG_Pos                            0                                                         /*!< SDMMC UHS_REG: VOLT_REG Position    */
+#define SDMMC_UHS_REG_VOLT_REG_Msk                            (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos)              /*!< SDMMC UHS_REG: VOLT_REG Mask        */
+#define SDMMC_UHS_REG_DDR_REG_Pos                             16                                                        /*!< SDMMC UHS_REG: DDR_REG Position     */
+#define SDMMC_UHS_REG_DDR_REG_Msk                             (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos)               /*!< SDMMC UHS_REG: DDR_REG Mask         */
+
+// ---------------------------------------  SDMMC_RST_N  ------------------------------------------
+#define SDMMC_RST_N_CARD_RESET_Pos                            0                                                         /*!< SDMMC RST_N: CARD_RESET Position    */
+#define SDMMC_RST_N_CARD_RESET_Msk                            (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos)              /*!< SDMMC RST_N: CARD_RESET Mask        */
+
+// ---------------------------------------  SDMMC_BMOD  -------------------------------------------
+#define SDMMC_BMOD_SWR_Pos                                    0                                                         /*!< SDMMC BMOD: SWR Position            */
+#define SDMMC_BMOD_SWR_Msk                                    (0x01UL << SDMMC_BMOD_SWR_Pos)                            /*!< SDMMC BMOD: SWR Mask                */
+#define SDMMC_BMOD_FB_Pos                                     1                                                         /*!< SDMMC BMOD: FB Position             */
+#define SDMMC_BMOD_FB_Msk                                     (0x01UL << SDMMC_BMOD_FB_Pos)                             /*!< SDMMC BMOD: FB Mask                 */
+#define SDMMC_BMOD_DSL_Pos                                    2                                                         /*!< SDMMC BMOD: DSL Position            */
+#define SDMMC_BMOD_DSL_Msk                                    (0x1fUL << SDMMC_BMOD_DSL_Pos)                            /*!< SDMMC BMOD: DSL Mask                */
+#define SDMMC_BMOD_DE_Pos                                     7                                                         /*!< SDMMC BMOD: DE Position             */
+#define SDMMC_BMOD_DE_Msk                                     (0x01UL << SDMMC_BMOD_DE_Pos)                             /*!< SDMMC BMOD: DE Mask                 */
+#define SDMMC_BMOD_PBL_Pos                                    8                                                         /*!< SDMMC BMOD: PBL Position            */
+#define SDMMC_BMOD_PBL_Msk                                    (0x07UL << SDMMC_BMOD_PBL_Pos)                            /*!< SDMMC BMOD: PBL Mask                */
+
+// --------------------------------------  SDMMC_PLDMND  ------------------------------------------
+#define SDMMC_PLDMND_PD_Pos                                   0                                                         /*!< SDMMC PLDMND: PD Position           */
+#define SDMMC_PLDMND_PD_Msk                                   (0xffffffffUL << SDMMC_PLDMND_PD_Pos)                     /*!< SDMMC PLDMND: PD Mask               */
+
+// --------------------------------------  SDMMC_DBADDR  ------------------------------------------
+#define SDMMC_DBADDR_SDL_Pos                                  0                                                         /*!< SDMMC DBADDR: SDL Position          */
+#define SDMMC_DBADDR_SDL_Msk                                  (0xffffffffUL << SDMMC_DBADDR_SDL_Pos)                    /*!< SDMMC DBADDR: SDL Mask              */
+
+// ---------------------------------------  SDMMC_IDSTS  ------------------------------------------
+#define SDMMC_IDSTS_TI_Pos                                    0                                                         /*!< SDMMC IDSTS: TI Position            */
+#define SDMMC_IDSTS_TI_Msk                                    (0x01UL << SDMMC_IDSTS_TI_Pos)                            /*!< SDMMC IDSTS: TI Mask                */
+#define SDMMC_IDSTS_RI_Pos                                    1                                                         /*!< SDMMC IDSTS: RI Position            */
+#define SDMMC_IDSTS_RI_Msk                                    (0x01UL << SDMMC_IDSTS_RI_Pos)                            /*!< SDMMC IDSTS: RI Mask                */
+#define SDMMC_IDSTS_FBE_Pos                                   2                                                         /*!< SDMMC IDSTS: FBE Position           */
+#define SDMMC_IDSTS_FBE_Msk                                   (0x01UL << SDMMC_IDSTS_FBE_Pos)                           /*!< SDMMC IDSTS: FBE Mask               */
+#define SDMMC_IDSTS_DU_Pos                                    4                                                         /*!< SDMMC IDSTS: DU Position            */
+#define SDMMC_IDSTS_DU_Msk                                    (0x01UL << SDMMC_IDSTS_DU_Pos)                            /*!< SDMMC IDSTS: DU Mask                */
+#define SDMMC_IDSTS_CES_Pos                                   5                                                         /*!< SDMMC IDSTS: CES Position           */
+#define SDMMC_IDSTS_CES_Msk                                   (0x01UL << SDMMC_IDSTS_CES_Pos)                           /*!< SDMMC IDSTS: CES Mask               */
+#define SDMMC_IDSTS_NIS_Pos                                   8                                                         /*!< SDMMC IDSTS: NIS Position           */
+#define SDMMC_IDSTS_NIS_Msk                                   (0x01UL << SDMMC_IDSTS_NIS_Pos)                           /*!< SDMMC IDSTS: NIS Mask               */
+#define SDMMC_IDSTS_AIS_Pos                                   9                                                         /*!< SDMMC IDSTS: AIS Position           */
+#define SDMMC_IDSTS_AIS_Msk                                   (0x01UL << SDMMC_IDSTS_AIS_Pos)                           /*!< SDMMC IDSTS: AIS Mask               */
+#define SDMMC_IDSTS_EB_Pos                                    10                                                        /*!< SDMMC IDSTS: EB Position            */
+#define SDMMC_IDSTS_EB_Msk                                    (0x07UL << SDMMC_IDSTS_EB_Pos)                            /*!< SDMMC IDSTS: EB Mask                */
+#define SDMMC_IDSTS_FSM_Pos                                   13                                                        /*!< SDMMC IDSTS: FSM Position           */
+#define SDMMC_IDSTS_FSM_Msk                                   (0x0fUL << SDMMC_IDSTS_FSM_Pos)                           /*!< SDMMC IDSTS: FSM Mask               */
+
+// --------------------------------------  SDMMC_IDINTEN  -----------------------------------------
+#define SDMMC_IDINTEN_TI_Pos                                  0                                                         /*!< SDMMC IDINTEN: TI Position          */
+#define SDMMC_IDINTEN_TI_Msk                                  (0x01UL << SDMMC_IDINTEN_TI_Pos)                          /*!< SDMMC IDINTEN: TI Mask              */
+#define SDMMC_IDINTEN_RI_Pos                                  1                                                         /*!< SDMMC IDINTEN: RI Position          */
+#define SDMMC_IDINTEN_RI_Msk                                  (0x01UL << SDMMC_IDINTEN_RI_Pos)                          /*!< SDMMC IDINTEN: RI Mask              */
+#define SDMMC_IDINTEN_FBE_Pos                                 2                                                         /*!< SDMMC IDINTEN: FBE Position         */
+#define SDMMC_IDINTEN_FBE_Msk                                 (0x01UL << SDMMC_IDINTEN_FBE_Pos)                         /*!< SDMMC IDINTEN: FBE Mask             */
+#define SDMMC_IDINTEN_DU_Pos                                  4                                                         /*!< SDMMC IDINTEN: DU Position          */
+#define SDMMC_IDINTEN_DU_Msk                                  (0x01UL << SDMMC_IDINTEN_DU_Pos)                          /*!< SDMMC IDINTEN: DU Mask              */
+#define SDMMC_IDINTEN_CES_Pos                                 5                                                         /*!< SDMMC IDINTEN: CES Position         */
+#define SDMMC_IDINTEN_CES_Msk                                 (0x01UL << SDMMC_IDINTEN_CES_Pos)                         /*!< SDMMC IDINTEN: CES Mask             */
+#define SDMMC_IDINTEN_NIS_Pos                                 8                                                         /*!< SDMMC IDINTEN: NIS Position         */
+#define SDMMC_IDINTEN_NIS_Msk                                 (0x01UL << SDMMC_IDINTEN_NIS_Pos)                         /*!< SDMMC IDINTEN: NIS Mask             */
+#define SDMMC_IDINTEN_AIS_Pos                                 9                                                         /*!< SDMMC IDINTEN: AIS Position         */
+#define SDMMC_IDINTEN_AIS_Msk                                 (0x01UL << SDMMC_IDINTEN_AIS_Pos)                         /*!< SDMMC IDINTEN: AIS Mask             */
+
+// --------------------------------------  SDMMC_DSCADDR  -----------------------------------------
+#define SDMMC_DSCADDR_HDA_Pos                                 0                                                         /*!< SDMMC DSCADDR: HDA Position         */
+#define SDMMC_DSCADDR_HDA_Msk                                 (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos)                   /*!< SDMMC DSCADDR: HDA Mask             */
+
+// --------------------------------------  SDMMC_BUFADDR  -----------------------------------------
+#define SDMMC_BUFADDR_HBA_Pos                                 0                                                         /*!< SDMMC BUFADDR: HBA Position         */
+#define SDMMC_BUFADDR_HBA_Msk                                 (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos)                   /*!< SDMMC BUFADDR: HBA Mask             */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  EMC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  EMC_CONTROL  ------------------------------------------
+#define EMC_CONTROL_E_Pos                                     0                                                         /*!< EMC CONTROL: E Position             */
+#define EMC_CONTROL_E_Msk                                     (0x01UL << EMC_CONTROL_E_Pos)                             /*!< EMC CONTROL: E Mask                 */
+#define EMC_CONTROL_M_Pos                                     1                                                         /*!< EMC CONTROL: M Position             */
+#define EMC_CONTROL_M_Msk                                     (0x01UL << EMC_CONTROL_M_Pos)                             /*!< EMC CONTROL: M Mask                 */
+#define EMC_CONTROL_L_Pos                                     2                                                         /*!< EMC CONTROL: L Position             */
+#define EMC_CONTROL_L_Msk                                     (0x01UL << EMC_CONTROL_L_Pos)                             /*!< EMC CONTROL: L Mask                 */
+
+// ---------------------------------------  EMC_STATUS  -------------------------------------------
+#define EMC_STATUS_B_Pos                                      0                                                         /*!< EMC STATUS: B Position              */
+#define EMC_STATUS_B_Msk                                      (0x01UL << EMC_STATUS_B_Pos)                              /*!< EMC STATUS: B Mask                  */
+#define EMC_STATUS_S_Pos                                      1                                                         /*!< EMC STATUS: S Position              */
+#define EMC_STATUS_S_Msk                                      (0x01UL << EMC_STATUS_S_Pos)                              /*!< EMC STATUS: S Mask                  */
+#define EMC_STATUS_SA_Pos                                     2                                                         /*!< EMC STATUS: SA Position             */
+#define EMC_STATUS_SA_Msk                                     (0x01UL << EMC_STATUS_SA_Pos)                             /*!< EMC STATUS: SA Mask                 */
+
+// ---------------------------------------  EMC_CONFIG  -------------------------------------------
+#define EMC_CONFIG_EM_Pos                                     0                                                         /*!< EMC CONFIG: EM Position             */
+#define EMC_CONFIG_EM_Msk                                     (0x01UL << EMC_CONFIG_EM_Pos)                             /*!< EMC CONFIG: EM Mask                 */
+#define EMC_CONFIG_CR_Pos                                     8                                                         /*!< EMC CONFIG: CR Position             */
+#define EMC_CONFIG_CR_Msk                                     (0x01UL << EMC_CONFIG_CR_Pos)                             /*!< EMC CONFIG: CR Mask                 */
+
+// -----------------------------------  EMC_DYNAMICCONTROL  ---------------------------------------
+#define EMC_DYNAMICCONTROL_CE_Pos                             0                                                         /*!< EMC DYNAMICCONTROL: CE Position     */
+#define EMC_DYNAMICCONTROL_CE_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CE_Pos)                     /*!< EMC DYNAMICCONTROL: CE Mask         */
+#define EMC_DYNAMICCONTROL_CS_Pos                             1                                                         /*!< EMC DYNAMICCONTROL: CS Position     */
+#define EMC_DYNAMICCONTROL_CS_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CS_Pos)                     /*!< EMC DYNAMICCONTROL: CS Mask         */
+#define EMC_DYNAMICCONTROL_SR_Pos                             2                                                         /*!< EMC DYNAMICCONTROL: SR Position     */
+#define EMC_DYNAMICCONTROL_SR_Msk                             (0x01UL << EMC_DYNAMICCONTROL_SR_Pos)                     /*!< EMC DYNAMICCONTROL: SR Mask         */
+#define EMC_DYNAMICCONTROL_MMC_Pos                            5                                                         /*!< EMC DYNAMICCONTROL: MMC Position    */
+#define EMC_DYNAMICCONTROL_MMC_Msk                            (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos)                    /*!< EMC DYNAMICCONTROL: MMC Mask        */
+#define EMC_DYNAMICCONTROL_I_Pos                              7                                                         /*!< EMC DYNAMICCONTROL: I Position      */
+#define EMC_DYNAMICCONTROL_I_Msk                              (0x03UL << EMC_DYNAMICCONTROL_I_Pos)                      /*!< EMC DYNAMICCONTROL: I Mask          */
+#define EMC_DYNAMICCONTROL_DP_Pos                             13                                                        /*!< EMC DYNAMICCONTROL: DP Position     */
+#define EMC_DYNAMICCONTROL_DP_Msk                             (0x01UL << EMC_DYNAMICCONTROL_DP_Pos)                     /*!< EMC DYNAMICCONTROL: DP Mask         */
+
+// -----------------------------------  EMC_DYNAMICREFRESH  ---------------------------------------
+#define EMC_DYNAMICREFRESH_REFRESH_Pos                        0                                                         /*!< EMC DYNAMICREFRESH: REFRESH Position */
+#define EMC_DYNAMICREFRESH_REFRESH_Msk                        (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos)          /*!< EMC DYNAMICREFRESH: REFRESH Mask    */
+
+// ----------------------------------  EMC_DYNAMICREADCONFIG  -------------------------------------
+#define EMC_DYNAMICREADCONFIG_RD_Pos                          0                                                         /*!< EMC DYNAMICREADCONFIG: RD Position  */
+#define EMC_DYNAMICREADCONFIG_RD_Msk                          (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos)                  /*!< EMC DYNAMICREADCONFIG: RD Mask      */
+
+// --------------------------------------  EMC_DYNAMICRP  -----------------------------------------
+#define EMC_DYNAMICRP_tRP_Pos                                 0                                                         /*!< EMC DYNAMICRP: tRP Position         */
+#define EMC_DYNAMICRP_tRP_Msk                                 (0x0fUL << EMC_DYNAMICRP_tRP_Pos)                         /*!< EMC DYNAMICRP: tRP Mask             */
+
+// -------------------------------------  EMC_DYNAMICRAS  -----------------------------------------
+#define EMC_DYNAMICRAS_tRAS_Pos                               0                                                         /*!< EMC DYNAMICRAS: tRAS Position       */
+#define EMC_DYNAMICRAS_tRAS_Msk                               (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos)                       /*!< EMC DYNAMICRAS: tRAS Mask           */
+
+// -------------------------------------  EMC_DYNAMICSREX  ----------------------------------------
+#define EMC_DYNAMICSREX_tSREX_Pos                             0                                                         /*!< EMC DYNAMICSREX: tSREX Position     */
+#define EMC_DYNAMICSREX_tSREX_Msk                             (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos)                     /*!< EMC DYNAMICSREX: tSREX Mask         */
+
+// -------------------------------------  EMC_DYNAMICAPR  -----------------------------------------
+#define EMC_DYNAMICAPR_tAPR_Pos                               0                                                         /*!< EMC DYNAMICAPR: tAPR Position       */
+#define EMC_DYNAMICAPR_tAPR_Msk                               (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos)                       /*!< EMC DYNAMICAPR: tAPR Mask           */
+
+// -------------------------------------  EMC_DYNAMICDAL  -----------------------------------------
+#define EMC_DYNAMICDAL_tDAL_Pos                               0                                                         /*!< EMC DYNAMICDAL: tDAL Position       */
+#define EMC_DYNAMICDAL_tDAL_Msk                               (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos)                       /*!< EMC DYNAMICDAL: tDAL Mask           */
+
+// --------------------------------------  EMC_DYNAMICWR  -----------------------------------------
+#define EMC_DYNAMICWR_tWR_Pos                                 0                                                         /*!< EMC DYNAMICWR: tWR Position         */
+#define EMC_DYNAMICWR_tWR_Msk                                 (0x0fUL << EMC_DYNAMICWR_tWR_Pos)                         /*!< EMC DYNAMICWR: tWR Mask             */
+
+// --------------------------------------  EMC_DYNAMICRC  -----------------------------------------
+#define EMC_DYNAMICRC_tRC_Pos                                 0                                                         /*!< EMC DYNAMICRC: tRC Position         */
+#define EMC_DYNAMICRC_tRC_Msk                                 (0x1fUL << EMC_DYNAMICRC_tRC_Pos)                         /*!< EMC DYNAMICRC: tRC Mask             */
+
+// -------------------------------------  EMC_DYNAMICRFC  -----------------------------------------
+#define EMC_DYNAMICRFC_tRFC_Pos                               0                                                         /*!< EMC DYNAMICRFC: tRFC Position       */
+#define EMC_DYNAMICRFC_tRFC_Msk                               (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos)                       /*!< EMC DYNAMICRFC: tRFC Mask           */
+
+// -------------------------------------  EMC_DYNAMICXSR  -----------------------------------------
+#define EMC_DYNAMICXSR_tXSR_Pos                               0                                                         /*!< EMC DYNAMICXSR: tXSR Position       */
+#define EMC_DYNAMICXSR_tXSR_Msk                               (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos)                       /*!< EMC DYNAMICXSR: tXSR Mask           */
+
+// -------------------------------------  EMC_DYNAMICRRD  -----------------------------------------
+#define EMC_DYNAMICRRD_tRRD_Pos                               0                                                         /*!< EMC DYNAMICRRD: tRRD Position       */
+#define EMC_DYNAMICRRD_tRRD_Msk                               (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos)                       /*!< EMC DYNAMICRRD: tRRD Mask           */
+
+// -------------------------------------  EMC_DYNAMICMRD  -----------------------------------------
+#define EMC_DYNAMICMRD_tMRD_Pos                               0                                                         /*!< EMC DYNAMICMRD: tMRD Position       */
+#define EMC_DYNAMICMRD_tMRD_Msk                               (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos)                       /*!< EMC DYNAMICMRD: tMRD Mask           */
+
+// ---------------------------------  EMC_STATICEXTENDEDWAIT  -------------------------------------
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos               0                                                         /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk               (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */
+
+// -----------------------------------  EMC_DYNAMICCONFIG0  ---------------------------------------
+#define EMC_DYNAMICCONFIG0_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG0: MD Position     */
+#define EMC_DYNAMICCONFIG0_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos)                     /*!< EMC DYNAMICCONFIG0: MD Mask         */
+#define EMC_DYNAMICCONFIG0_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG0: AM0 Position    */
+#define EMC_DYNAMICCONFIG0_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos)                    /*!< EMC DYNAMICCONFIG0: AM0 Mask        */
+#define EMC_DYNAMICCONFIG0_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG0: AM1 Position    */
+#define EMC_DYNAMICCONFIG0_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos)                    /*!< EMC DYNAMICCONFIG0: AM1 Mask        */
+#define EMC_DYNAMICCONFIG0_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG0: B Position      */
+#define EMC_DYNAMICCONFIG0_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_B_Pos)                      /*!< EMC DYNAMICCONFIG0: B Mask          */
+#define EMC_DYNAMICCONFIG0_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG0: P Position      */
+#define EMC_DYNAMICCONFIG0_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_P_Pos)                      /*!< EMC DYNAMICCONFIG0: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS0  ---------------------------------------
+#define EMC_DYNAMICRASCAS0_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS0: RAS Position    */
+#define EMC_DYNAMICRASCAS0_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos)                    /*!< EMC DYNAMICRASCAS0: RAS Mask        */
+#define EMC_DYNAMICRASCAS0_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS0: CAS Position    */
+#define EMC_DYNAMICRASCAS0_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos)                    /*!< EMC DYNAMICRASCAS0: CAS Mask        */
+
+// -----------------------------------  EMC_DYNAMICCONFIG1  ---------------------------------------
+#define EMC_DYNAMICCONFIG1_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG1: MD Position     */
+#define EMC_DYNAMICCONFIG1_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos)                     /*!< EMC DYNAMICCONFIG1: MD Mask         */
+#define EMC_DYNAMICCONFIG1_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG1: AM0 Position    */
+#define EMC_DYNAMICCONFIG1_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos)                    /*!< EMC DYNAMICCONFIG1: AM0 Mask        */
+#define EMC_DYNAMICCONFIG1_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG1: AM1 Position    */
+#define EMC_DYNAMICCONFIG1_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos)                    /*!< EMC DYNAMICCONFIG1: AM1 Mask        */
+#define EMC_DYNAMICCONFIG1_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG1: B Position      */
+#define EMC_DYNAMICCONFIG1_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_B_Pos)                      /*!< EMC DYNAMICCONFIG1: B Mask          */
+#define EMC_DYNAMICCONFIG1_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG1: P Position      */
+#define EMC_DYNAMICCONFIG1_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_P_Pos)                      /*!< EMC DYNAMICCONFIG1: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS1  ---------------------------------------
+#define EMC_DYNAMICRASCAS1_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS1: RAS Position    */
+#define EMC_DYNAMICRASCAS1_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos)                    /*!< EMC DYNAMICRASCAS1: RAS Mask        */
+#define EMC_DYNAMICRASCAS1_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS1: CAS Position    */
+#define EMC_DYNAMICRASCAS1_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos)                    /*!< EMC DYNAMICRASCAS1: CAS Mask        */
+
+// -----------------------------------  EMC_DYNAMICCONFIG2  ---------------------------------------
+#define EMC_DYNAMICCONFIG2_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG2: MD Position     */
+#define EMC_DYNAMICCONFIG2_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos)                     /*!< EMC DYNAMICCONFIG2: MD Mask         */
+#define EMC_DYNAMICCONFIG2_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG2: AM0 Position    */
+#define EMC_DYNAMICCONFIG2_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos)                    /*!< EMC DYNAMICCONFIG2: AM0 Mask        */
+#define EMC_DYNAMICCONFIG2_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG2: AM1 Position    */
+#define EMC_DYNAMICCONFIG2_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos)                    /*!< EMC DYNAMICCONFIG2: AM1 Mask        */
+#define EMC_DYNAMICCONFIG2_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG2: B Position      */
+#define EMC_DYNAMICCONFIG2_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_B_Pos)                      /*!< EMC DYNAMICCONFIG2: B Mask          */
+#define EMC_DYNAMICCONFIG2_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG2: P Position      */
+#define EMC_DYNAMICCONFIG2_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_P_Pos)                      /*!< EMC DYNAMICCONFIG2: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS2  ---------------------------------------
+#define EMC_DYNAMICRASCAS2_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS2: RAS Position    */
+#define EMC_DYNAMICRASCAS2_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos)                    /*!< EMC DYNAMICRASCAS2: RAS Mask        */
+#define EMC_DYNAMICRASCAS2_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS2: CAS Position    */
+#define EMC_DYNAMICRASCAS2_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos)                    /*!< EMC DYNAMICRASCAS2: CAS Mask        */
+
+// -----------------------------------  EMC_DYNAMICCONFIG3  ---------------------------------------
+#define EMC_DYNAMICCONFIG3_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG3: MD Position     */
+#define EMC_DYNAMICCONFIG3_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos)                     /*!< EMC DYNAMICCONFIG3: MD Mask         */
+#define EMC_DYNAMICCONFIG3_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG3: AM0 Position    */
+#define EMC_DYNAMICCONFIG3_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos)                    /*!< EMC DYNAMICCONFIG3: AM0 Mask        */
+#define EMC_DYNAMICCONFIG3_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG3: AM1 Position    */
+#define EMC_DYNAMICCONFIG3_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos)                    /*!< EMC DYNAMICCONFIG3: AM1 Mask        */
+#define EMC_DYNAMICCONFIG3_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG3: B Position      */
+#define EMC_DYNAMICCONFIG3_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_B_Pos)                      /*!< EMC DYNAMICCONFIG3: B Mask          */
+#define EMC_DYNAMICCONFIG3_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG3: P Position      */
+#define EMC_DYNAMICCONFIG3_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_P_Pos)                      /*!< EMC DYNAMICCONFIG3: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS3  ---------------------------------------
+#define EMC_DYNAMICRASCAS3_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS3: RAS Position    */
+#define EMC_DYNAMICRASCAS3_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos)                    /*!< EMC DYNAMICRASCAS3: RAS Mask        */
+#define EMC_DYNAMICRASCAS3_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS3: CAS Position    */
+#define EMC_DYNAMICRASCAS3_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos)                    /*!< EMC DYNAMICRASCAS3: CAS Mask        */
+
+// ------------------------------------  EMC_STATICCONFIG0  ---------------------------------------
+#define EMC_STATICCONFIG0_MW_Pos                              0                                                         /*!< EMC STATICCONFIG0: MW Position      */
+#define EMC_STATICCONFIG0_MW_Msk                              (0x03UL << EMC_STATICCONFIG0_MW_Pos)                      /*!< EMC STATICCONFIG0: MW Mask          */
+#define EMC_STATICCONFIG0_PM_Pos                              3                                                         /*!< EMC STATICCONFIG0: PM Position      */
+#define EMC_STATICCONFIG0_PM_Msk                              (0x01UL << EMC_STATICCONFIG0_PM_Pos)                      /*!< EMC STATICCONFIG0: PM Mask          */
+#define EMC_STATICCONFIG0_PC_Pos                              6                                                         /*!< EMC STATICCONFIG0: PC Position      */
+#define EMC_STATICCONFIG0_PC_Msk                              (0x01UL << EMC_STATICCONFIG0_PC_Pos)                      /*!< EMC STATICCONFIG0: PC Mask          */
+#define EMC_STATICCONFIG0_PB_Pos                              7                                                         /*!< EMC STATICCONFIG0: PB Position      */
+#define EMC_STATICCONFIG0_PB_Msk                              (0x01UL << EMC_STATICCONFIG0_PB_Pos)                      /*!< EMC STATICCONFIG0: PB Mask          */
+#define EMC_STATICCONFIG0_EW_Pos                              8                                                         /*!< EMC STATICCONFIG0: EW Position      */
+#define EMC_STATICCONFIG0_EW_Msk                              (0x01UL << EMC_STATICCONFIG0_EW_Pos)                      /*!< EMC STATICCONFIG0: EW Mask          */
+#define EMC_STATICCONFIG0_B_Pos                               19                                                        /*!< EMC STATICCONFIG0: B Position       */
+#define EMC_STATICCONFIG0_B_Msk                               (0x01UL << EMC_STATICCONFIG0_B_Pos)                       /*!< EMC STATICCONFIG0: B Mask           */
+#define EMC_STATICCONFIG0_P_Pos                               20                                                        /*!< EMC STATICCONFIG0: P Position       */
+#define EMC_STATICCONFIG0_P_Msk                               (0x01UL << EMC_STATICCONFIG0_P_Pos)                       /*!< EMC STATICCONFIG0: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN0  ---------------------------------------
+#define EMC_STATICWAITWEN0_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN0: WAITWEN Position */
+#define EMC_STATICWAITWEN0_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos)                /*!< EMC STATICWAITWEN0: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN0  ---------------------------------------
+#define EMC_STATICWAITOEN0_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN0: WAITOEN Position */
+#define EMC_STATICWAITOEN0_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos)                /*!< EMC STATICWAITOEN0: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD0  ---------------------------------------
+#define EMC_STATICWAITRD0_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD0: WAITRD Position  */
+#define EMC_STATICWAITRD0_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos)                  /*!< EMC STATICWAITRD0: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG0  ---------------------------------------
+#define EMC_STATICWAITPAG0_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG0: WAITPAGE Position */
+#define EMC_STATICWAITPAG0_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG0: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR0  ---------------------------------------
+#define EMC_STATICWAITWR0_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR0: WAITWR Position  */
+#define EMC_STATICWAITWR0_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos)                  /*!< EMC STATICWAITWR0: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN0  --------------------------------------
+#define EMC_STATICWAITTURN0_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN0: WAITTURN Position */
+#define EMC_STATICWAITTURN0_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos)              /*!< EMC STATICWAITTURN0: WAITTURN Mask  */
+
+// ------------------------------------  EMC_STATICCONFIG1  ---------------------------------------
+#define EMC_STATICCONFIG1_MW_Pos                              0                                                         /*!< EMC STATICCONFIG1: MW Position      */
+#define EMC_STATICCONFIG1_MW_Msk                              (0x03UL << EMC_STATICCONFIG1_MW_Pos)                      /*!< EMC STATICCONFIG1: MW Mask          */
+#define EMC_STATICCONFIG1_PM_Pos                              3                                                         /*!< EMC STATICCONFIG1: PM Position      */
+#define EMC_STATICCONFIG1_PM_Msk                              (0x01UL << EMC_STATICCONFIG1_PM_Pos)                      /*!< EMC STATICCONFIG1: PM Mask          */
+#define EMC_STATICCONFIG1_PC_Pos                              6                                                         /*!< EMC STATICCONFIG1: PC Position      */
+#define EMC_STATICCONFIG1_PC_Msk                              (0x01UL << EMC_STATICCONFIG1_PC_Pos)                      /*!< EMC STATICCONFIG1: PC Mask          */
+#define EMC_STATICCONFIG1_PB_Pos                              7                                                         /*!< EMC STATICCONFIG1: PB Position      */
+#define EMC_STATICCONFIG1_PB_Msk                              (0x01UL << EMC_STATICCONFIG1_PB_Pos)                      /*!< EMC STATICCONFIG1: PB Mask          */
+#define EMC_STATICCONFIG1_EW_Pos                              8                                                         /*!< EMC STATICCONFIG1: EW Position      */
+#define EMC_STATICCONFIG1_EW_Msk                              (0x01UL << EMC_STATICCONFIG1_EW_Pos)                      /*!< EMC STATICCONFIG1: EW Mask          */
+#define EMC_STATICCONFIG1_B_Pos                               19                                                        /*!< EMC STATICCONFIG1: B Position       */
+#define EMC_STATICCONFIG1_B_Msk                               (0x01UL << EMC_STATICCONFIG1_B_Pos)                       /*!< EMC STATICCONFIG1: B Mask           */
+#define EMC_STATICCONFIG1_P_Pos                               20                                                        /*!< EMC STATICCONFIG1: P Position       */
+#define EMC_STATICCONFIG1_P_Msk                               (0x01UL << EMC_STATICCONFIG1_P_Pos)                       /*!< EMC STATICCONFIG1: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN1  ---------------------------------------
+#define EMC_STATICWAITWEN1_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN1: WAITWEN Position */
+#define EMC_STATICWAITWEN1_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos)                /*!< EMC STATICWAITWEN1: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN1  ---------------------------------------
+#define EMC_STATICWAITOEN1_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN1: WAITOEN Position */
+#define EMC_STATICWAITOEN1_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos)                /*!< EMC STATICWAITOEN1: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD1  ---------------------------------------
+#define EMC_STATICWAITRD1_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD1: WAITRD Position  */
+#define EMC_STATICWAITRD1_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos)                  /*!< EMC STATICWAITRD1: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG1  ---------------------------------------
+#define EMC_STATICWAITPAG1_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG1: WAITPAGE Position */
+#define EMC_STATICWAITPAG1_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG1: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR1  ---------------------------------------
+#define EMC_STATICWAITWR1_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR1: WAITWR Position  */
+#define EMC_STATICWAITWR1_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos)                  /*!< EMC STATICWAITWR1: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN1  --------------------------------------
+#define EMC_STATICWAITTURN1_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN1: WAITTURN Position */
+#define EMC_STATICWAITTURN1_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos)              /*!< EMC STATICWAITTURN1: WAITTURN Mask  */
+
+// ------------------------------------  EMC_STATICCONFIG2  ---------------------------------------
+#define EMC_STATICCONFIG2_MW_Pos                              0                                                         /*!< EMC STATICCONFIG2: MW Position      */
+#define EMC_STATICCONFIG2_MW_Msk                              (0x03UL << EMC_STATICCONFIG2_MW_Pos)                      /*!< EMC STATICCONFIG2: MW Mask          */
+#define EMC_STATICCONFIG2_PM_Pos                              3                                                         /*!< EMC STATICCONFIG2: PM Position      */
+#define EMC_STATICCONFIG2_PM_Msk                              (0x01UL << EMC_STATICCONFIG2_PM_Pos)                      /*!< EMC STATICCONFIG2: PM Mask          */
+#define EMC_STATICCONFIG2_PC_Pos                              6                                                         /*!< EMC STATICCONFIG2: PC Position      */
+#define EMC_STATICCONFIG2_PC_Msk                              (0x01UL << EMC_STATICCONFIG2_PC_Pos)                      /*!< EMC STATICCONFIG2: PC Mask          */
+#define EMC_STATICCONFIG2_PB_Pos                              7                                                         /*!< EMC STATICCONFIG2: PB Position      */
+#define EMC_STATICCONFIG2_PB_Msk                              (0x01UL << EMC_STATICCONFIG2_PB_Pos)                      /*!< EMC STATICCONFIG2: PB Mask          */
+#define EMC_STATICCONFIG2_EW_Pos                              8                                                         /*!< EMC STATICCONFIG2: EW Position      */
+#define EMC_STATICCONFIG2_EW_Msk                              (0x01UL << EMC_STATICCONFIG2_EW_Pos)                      /*!< EMC STATICCONFIG2: EW Mask          */
+#define EMC_STATICCONFIG2_B_Pos                               19                                                        /*!< EMC STATICCONFIG2: B Position       */
+#define EMC_STATICCONFIG2_B_Msk                               (0x01UL << EMC_STATICCONFIG2_B_Pos)                       /*!< EMC STATICCONFIG2: B Mask           */
+#define EMC_STATICCONFIG2_P_Pos                               20                                                        /*!< EMC STATICCONFIG2: P Position       */
+#define EMC_STATICCONFIG2_P_Msk                               (0x01UL << EMC_STATICCONFIG2_P_Pos)                       /*!< EMC STATICCONFIG2: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN2  ---------------------------------------
+#define EMC_STATICWAITWEN2_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN2: WAITWEN Position */
+#define EMC_STATICWAITWEN2_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos)                /*!< EMC STATICWAITWEN2: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN2  ---------------------------------------
+#define EMC_STATICWAITOEN2_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN2: WAITOEN Position */
+#define EMC_STATICWAITOEN2_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos)                /*!< EMC STATICWAITOEN2: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD2  ---------------------------------------
+#define EMC_STATICWAITRD2_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD2: WAITRD Position  */
+#define EMC_STATICWAITRD2_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos)                  /*!< EMC STATICWAITRD2: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG2  ---------------------------------------
+#define EMC_STATICWAITPAG2_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG2: WAITPAGE Position */
+#define EMC_STATICWAITPAG2_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG2: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR2  ---------------------------------------
+#define EMC_STATICWAITWR2_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR2: WAITWR Position  */
+#define EMC_STATICWAITWR2_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos)                  /*!< EMC STATICWAITWR2: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN2  --------------------------------------
+#define EMC_STATICWAITTURN2_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN2: WAITTURN Position */
+#define EMC_STATICWAITTURN2_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos)              /*!< EMC STATICWAITTURN2: WAITTURN Mask  */
+
+// ------------------------------------  EMC_STATICCONFIG3  ---------------------------------------
+#define EMC_STATICCONFIG3_MW_Pos                              0                                                         /*!< EMC STATICCONFIG3: MW Position      */
+#define EMC_STATICCONFIG3_MW_Msk                              (0x03UL << EMC_STATICCONFIG3_MW_Pos)                      /*!< EMC STATICCONFIG3: MW Mask          */
+#define EMC_STATICCONFIG3_PM_Pos                              3                                                         /*!< EMC STATICCONFIG3: PM Position      */
+#define EMC_STATICCONFIG3_PM_Msk                              (0x01UL << EMC_STATICCONFIG3_PM_Pos)                      /*!< EMC STATICCONFIG3: PM Mask          */
+#define EMC_STATICCONFIG3_PC_Pos                              6                                                         /*!< EMC STATICCONFIG3: PC Position      */
+#define EMC_STATICCONFIG3_PC_Msk                              (0x01UL << EMC_STATICCONFIG3_PC_Pos)                      /*!< EMC STATICCONFIG3: PC Mask          */
+#define EMC_STATICCONFIG3_PB_Pos                              7                                                         /*!< EMC STATICCONFIG3: PB Position      */
+#define EMC_STATICCONFIG3_PB_Msk                              (0x01UL << EMC_STATICCONFIG3_PB_Pos)                      /*!< EMC STATICCONFIG3: PB Mask          */
+#define EMC_STATICCONFIG3_EW_Pos                              8                                                         /*!< EMC STATICCONFIG3: EW Position      */
+#define EMC_STATICCONFIG3_EW_Msk                              (0x01UL << EMC_STATICCONFIG3_EW_Pos)                      /*!< EMC STATICCONFIG3: EW Mask          */
+#define EMC_STATICCONFIG3_B_Pos                               19                                                        /*!< EMC STATICCONFIG3: B Position       */
+#define EMC_STATICCONFIG3_B_Msk                               (0x01UL << EMC_STATICCONFIG3_B_Pos)                       /*!< EMC STATICCONFIG3: B Mask           */
+#define EMC_STATICCONFIG3_P_Pos                               20                                                        /*!< EMC STATICCONFIG3: P Position       */
+#define EMC_STATICCONFIG3_P_Msk                               (0x01UL << EMC_STATICCONFIG3_P_Pos)                       /*!< EMC STATICCONFIG3: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN3  ---------------------------------------
+#define EMC_STATICWAITWEN3_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN3: WAITWEN Position */
+#define EMC_STATICWAITWEN3_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos)                /*!< EMC STATICWAITWEN3: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN3  ---------------------------------------
+#define EMC_STATICWAITOEN3_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN3: WAITOEN Position */
+#define EMC_STATICWAITOEN3_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos)                /*!< EMC STATICWAITOEN3: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD3  ---------------------------------------
+#define EMC_STATICWAITRD3_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD3: WAITRD Position  */
+#define EMC_STATICWAITRD3_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos)                  /*!< EMC STATICWAITRD3: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG3  ---------------------------------------
+#define EMC_STATICWAITPAG3_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG3: WAITPAGE Position */
+#define EMC_STATICWAITPAG3_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG3: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR3  ---------------------------------------
+#define EMC_STATICWAITWR3_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR3: WAITWR Position  */
+#define EMC_STATICWAITWR3_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos)                  /*!< EMC STATICWAITWR3: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN3  --------------------------------------
+#define EMC_STATICWAITTURN3_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN3: WAITTURN Position */
+#define EMC_STATICWAITTURN3_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos)              /*!< EMC STATICWAITTURN3: WAITTURN Mask  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 USB0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  USB0_CAPLENGTH  -----------------------------------------
+#define USB0_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB0 CAPLENGTH: CAPLENGTH Position  */
+#define USB0_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB0 CAPLENGTH: CAPLENGTH Mask      */
+#define USB0_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB0 CAPLENGTH: HCIVERSION Position */
+#define USB0_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos)           /*!< USB0 CAPLENGTH: HCIVERSION Mask     */
+
+// -------------------------------------  USB0_HCSPARAMS  -----------------------------------------
+#define USB0_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB0 HCSPARAMS: N_PORTS Position    */
+#define USB0_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos)                    /*!< USB0 HCSPARAMS: N_PORTS Mask        */
+#define USB0_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB0 HCSPARAMS: PPC Position        */
+#define USB0_HCSPARAMS_PPC_Msk                                (0x01UL << USB0_HCSPARAMS_PPC_Pos)                        /*!< USB0 HCSPARAMS: PPC Mask            */
+#define USB0_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB0 HCSPARAMS: N_PCC Position      */
+#define USB0_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos)                      /*!< USB0 HCSPARAMS: N_PCC Mask          */
+#define USB0_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB0 HCSPARAMS: N_CC Position       */
+#define USB0_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB0_HCSPARAMS_N_CC_Pos)                       /*!< USB0 HCSPARAMS: N_CC Mask           */
+#define USB0_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB0 HCSPARAMS: PI Position         */
+#define USB0_HCSPARAMS_PI_Msk                                 (0x01UL << USB0_HCSPARAMS_PI_Pos)                         /*!< USB0 HCSPARAMS: PI Mask             */
+#define USB0_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB0 HCSPARAMS: N_PTT Position      */
+#define USB0_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos)                      /*!< USB0 HCSPARAMS: N_PTT Mask          */
+#define USB0_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB0 HCSPARAMS: N_TT Position       */
+#define USB0_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB0_HCSPARAMS_N_TT_Pos)                       /*!< USB0 HCSPARAMS: N_TT Mask           */
+
+// -------------------------------------  USB0_HCCPARAMS  -----------------------------------------
+#define USB0_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB0 HCCPARAMS: ADC Position        */
+#define USB0_HCCPARAMS_ADC_Msk                                (0x01UL << USB0_HCCPARAMS_ADC_Pos)                        /*!< USB0 HCCPARAMS: ADC Mask            */
+#define USB0_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB0 HCCPARAMS: PFL Position        */
+#define USB0_HCCPARAMS_PFL_Msk                                (0x01UL << USB0_HCCPARAMS_PFL_Pos)                        /*!< USB0 HCCPARAMS: PFL Mask            */
+#define USB0_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB0 HCCPARAMS: ASP Position        */
+#define USB0_HCCPARAMS_ASP_Msk                                (0x01UL << USB0_HCCPARAMS_ASP_Pos)                        /*!< USB0 HCCPARAMS: ASP Mask            */
+#define USB0_HCCPARAMS_IST_Pos                                4                                                         /*!< USB0 HCCPARAMS: IST Position        */
+#define USB0_HCCPARAMS_IST_Msk                                (0x0fUL << USB0_HCCPARAMS_IST_Pos)                        /*!< USB0 HCCPARAMS: IST Mask            */
+#define USB0_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB0 HCCPARAMS: EECP Position       */
+#define USB0_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos)                 /*!< USB0 HCCPARAMS: EECP Mask           */
+
+// -------------------------------------  USB0_DCIVERSION  ----------------------------------------
+#define USB0_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB0 DCIVERSION: DCIVERSION Position */
+#define USB0_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos)          /*!< USB0 DCIVERSION: DCIVERSION Mask    */
+
+// --------------------------------------  USB0_USBCMD_D  -----------------------------------------
+#define USB0_USBCMD_D_RS_Pos                                  0                                                         /*!< USB0 USBCMD_D: RS Position          */
+#define USB0_USBCMD_D_RS_Msk                                  (0x01UL << USB0_USBCMD_D_RS_Pos)                          /*!< USB0 USBCMD_D: RS Mask              */
+#define USB0_USBCMD_D_RST_Pos                                 1                                                         /*!< USB0 USBCMD_D: RST Position         */
+#define USB0_USBCMD_D_RST_Msk                                 (0x01UL << USB0_USBCMD_D_RST_Pos)                         /*!< USB0 USBCMD_D: RST Mask             */
+#define USB0_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB0 USBCMD_D: SUTW Position        */
+#define USB0_USBCMD_D_SUTW_Msk                                (0x01UL << USB0_USBCMD_D_SUTW_Pos)                        /*!< USB0 USBCMD_D: SUTW Mask            */
+#define USB0_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB0 USBCMD_D: ATDTW Position       */
+#define USB0_USBCMD_D_ATDTW_Msk                               (0x01UL << USB0_USBCMD_D_ATDTW_Pos)                       /*!< USB0 USBCMD_D: ATDTW Mask           */
+#define USB0_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_D: ITC Position         */
+#define USB0_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_D_ITC_Pos)                   /*!< USB0 USBCMD_D: ITC Mask             */
+
+// --------------------------------------  USB0_USBCMD_H  -----------------------------------------
+#define USB0_USBCMD_H_RS_Pos                                  0                                                         /*!< USB0 USBCMD_H: RS Position          */
+#define USB0_USBCMD_H_RS_Msk                                  (0x01UL << USB0_USBCMD_H_RS_Pos)                          /*!< USB0 USBCMD_H: RS Mask              */
+#define USB0_USBCMD_H_RST_Pos                                 1                                                         /*!< USB0 USBCMD_H: RST Position         */
+#define USB0_USBCMD_H_RST_Msk                                 (0x01UL << USB0_USBCMD_H_RST_Pos)                         /*!< USB0 USBCMD_H: RST Mask             */
+#define USB0_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB0 USBCMD_H: FS0 Position         */
+#define USB0_USBCMD_H_FS0_Msk                                 (0x01UL << USB0_USBCMD_H_FS0_Pos)                         /*!< USB0 USBCMD_H: FS0 Mask             */
+#define USB0_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB0 USBCMD_H: FS1 Position         */
+#define USB0_USBCMD_H_FS1_Msk                                 (0x01UL << USB0_USBCMD_H_FS1_Pos)                         /*!< USB0 USBCMD_H: FS1 Mask             */
+#define USB0_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB0 USBCMD_H: PSE Position         */
+#define USB0_USBCMD_H_PSE_Msk                                 (0x01UL << USB0_USBCMD_H_PSE_Pos)                         /*!< USB0 USBCMD_H: PSE Mask             */
+#define USB0_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB0 USBCMD_H: ASE Position         */
+#define USB0_USBCMD_H_ASE_Msk                                 (0x01UL << USB0_USBCMD_H_ASE_Pos)                         /*!< USB0 USBCMD_H: ASE Mask             */
+#define USB0_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB0 USBCMD_H: IAA Position         */
+#define USB0_USBCMD_H_IAA_Msk                                 (0x01UL << USB0_USBCMD_H_IAA_Pos)                         /*!< USB0 USBCMD_H: IAA Mask             */
+#define USB0_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB0 USBCMD_H: ASP1_0 Position      */
+#define USB0_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB0_USBCMD_H_ASP1_0_Pos)                      /*!< USB0 USBCMD_H: ASP1_0 Mask          */
+#define USB0_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB0 USBCMD_H: ASPE Position        */
+#define USB0_USBCMD_H_ASPE_Msk                                (0x01UL << USB0_USBCMD_H_ASPE_Pos)                        /*!< USB0 USBCMD_H: ASPE Mask            */
+#define USB0_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB0 USBCMD_H: FS2 Position         */
+#define USB0_USBCMD_H_FS2_Msk                                 (0x01UL << USB0_USBCMD_H_FS2_Pos)                         /*!< USB0 USBCMD_H: FS2 Mask             */
+#define USB0_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_H: ITC Position         */
+#define USB0_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_H_ITC_Pos)                   /*!< USB0 USBCMD_H: ITC Mask             */
+
+// --------------------------------------  USB0_USBSTS_D  -----------------------------------------
+#define USB0_USBSTS_D_UI_Pos                                  0                                                         /*!< USB0 USBSTS_D: UI Position          */
+#define USB0_USBSTS_D_UI_Msk                                  (0x01UL << USB0_USBSTS_D_UI_Pos)                          /*!< USB0 USBSTS_D: UI Mask              */
+#define USB0_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_D: UEI Position         */
+#define USB0_USBSTS_D_UEI_Msk                                 (0x01UL << USB0_USBSTS_D_UEI_Pos)                         /*!< USB0 USBSTS_D: UEI Mask             */
+#define USB0_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_D: PCI Position         */
+#define USB0_USBSTS_D_PCI_Msk                                 (0x01UL << USB0_USBSTS_D_PCI_Pos)                         /*!< USB0 USBSTS_D: PCI Mask             */
+#define USB0_USBSTS_D_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_D: AAI Position         */
+#define USB0_USBSTS_D_AAI_Msk                                 (0x01UL << USB0_USBSTS_D_AAI_Pos)                         /*!< USB0 USBSTS_D: AAI Mask             */
+#define USB0_USBSTS_D_URI_Pos                                 6                                                         /*!< USB0 USBSTS_D: URI Position         */
+#define USB0_USBSTS_D_URI_Msk                                 (0x01UL << USB0_USBSTS_D_URI_Pos)                         /*!< USB0 USBSTS_D: URI Mask             */
+#define USB0_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_D: SRI Position         */
+#define USB0_USBSTS_D_SRI_Msk                                 (0x01UL << USB0_USBSTS_D_SRI_Pos)                         /*!< USB0 USBSTS_D: SRI Mask             */
+#define USB0_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB0 USBSTS_D: SLI Position         */
+#define USB0_USBSTS_D_SLI_Msk                                 (0x01UL << USB0_USBSTS_D_SLI_Pos)                         /*!< USB0 USBSTS_D: SLI Mask             */
+#define USB0_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB0 USBSTS_D: NAKI Position        */
+#define USB0_USBSTS_D_NAKI_Msk                                (0x01UL << USB0_USBSTS_D_NAKI_Pos)                        /*!< USB0 USBSTS_D: NAKI Mask            */
+
+// --------------------------------------  USB0_USBSTS_H  -----------------------------------------
+#define USB0_USBSTS_H_UI_Pos                                  0                                                         /*!< USB0 USBSTS_H: UI Position          */
+#define USB0_USBSTS_H_UI_Msk                                  (0x01UL << USB0_USBSTS_H_UI_Pos)                          /*!< USB0 USBSTS_H: UI Mask              */
+#define USB0_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_H: UEI Position         */
+#define USB0_USBSTS_H_UEI_Msk                                 (0x01UL << USB0_USBSTS_H_UEI_Pos)                         /*!< USB0 USBSTS_H: UEI Mask             */
+#define USB0_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_H: PCI Position         */
+#define USB0_USBSTS_H_PCI_Msk                                 (0x01UL << USB0_USBSTS_H_PCI_Pos)                         /*!< USB0 USBSTS_H: PCI Mask             */
+#define USB0_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB0 USBSTS_H: FRI Position         */
+#define USB0_USBSTS_H_FRI_Msk                                 (0x01UL << USB0_USBSTS_H_FRI_Pos)                         /*!< USB0 USBSTS_H: FRI Mask             */
+#define USB0_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_H: AAI Position         */
+#define USB0_USBSTS_H_AAI_Msk                                 (0x01UL << USB0_USBSTS_H_AAI_Pos)                         /*!< USB0 USBSTS_H: AAI Mask             */
+#define USB0_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_H: SRI Position         */
+#define USB0_USBSTS_H_SRI_Msk                                 (0x01UL << USB0_USBSTS_H_SRI_Pos)                         /*!< USB0 USBSTS_H: SRI Mask             */
+#define USB0_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB0 USBSTS_H: HCH Position         */
+#define USB0_USBSTS_H_HCH_Msk                                 (0x01UL << USB0_USBSTS_H_HCH_Pos)                         /*!< USB0 USBSTS_H: HCH Mask             */
+#define USB0_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB0 USBSTS_H: RCL Position         */
+#define USB0_USBSTS_H_RCL_Msk                                 (0x01UL << USB0_USBSTS_H_RCL_Pos)                         /*!< USB0 USBSTS_H: RCL Mask             */
+#define USB0_USBSTS_H_PS_Pos                                  14                                                        /*!< USB0 USBSTS_H: PS Position          */
+#define USB0_USBSTS_H_PS_Msk                                  (0x01UL << USB0_USBSTS_H_PS_Pos)                          /*!< USB0 USBSTS_H: PS Mask              */
+#define USB0_USBSTS_H_AS_Pos                                  15                                                        /*!< USB0 USBSTS_H: AS Position          */
+#define USB0_USBSTS_H_AS_Msk                                  (0x01UL << USB0_USBSTS_H_AS_Pos)                          /*!< USB0 USBSTS_H: AS Mask              */
+#define USB0_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB0 USBSTS_H: UAI Position         */
+#define USB0_USBSTS_H_UAI_Msk                                 (0x01UL << USB0_USBSTS_H_UAI_Pos)                         /*!< USB0 USBSTS_H: UAI Mask             */
+#define USB0_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB0 USBSTS_H: UPI Position         */
+#define USB0_USBSTS_H_UPI_Msk                                 (0x01UL << USB0_USBSTS_H_UPI_Pos)                         /*!< USB0 USBSTS_H: UPI Mask             */
+
+// -------------------------------------  USB0_USBINTR_D  -----------------------------------------
+#define USB0_USBINTR_D_UE_Pos                                 0                                                         /*!< USB0 USBINTR_D: UE Position         */
+#define USB0_USBINTR_D_UE_Msk                                 (0x01UL << USB0_USBINTR_D_UE_Pos)                         /*!< USB0 USBINTR_D: UE Mask             */
+#define USB0_USBINTR_D_UEE_Pos                                1                                                         /*!< USB0 USBINTR_D: UEE Position        */
+#define USB0_USBINTR_D_UEE_Msk                                (0x01UL << USB0_USBINTR_D_UEE_Pos)                        /*!< USB0 USBINTR_D: UEE Mask            */
+#define USB0_USBINTR_D_PCE_Pos                                2                                                         /*!< USB0 USBINTR_D: PCE Position        */
+#define USB0_USBINTR_D_PCE_Msk                                (0x01UL << USB0_USBINTR_D_PCE_Pos)                        /*!< USB0 USBINTR_D: PCE Mask            */
+#define USB0_USBINTR_D_URE_Pos                                6                                                         /*!< USB0 USBINTR_D: URE Position        */
+#define USB0_USBINTR_D_URE_Msk                                (0x01UL << USB0_USBINTR_D_URE_Pos)                        /*!< USB0 USBINTR_D: URE Mask            */
+#define USB0_USBINTR_D_SRE_Pos                                7                                                         /*!< USB0 USBINTR_D: SRE Position        */
+#define USB0_USBINTR_D_SRE_Msk                                (0x01UL << USB0_USBINTR_D_SRE_Pos)                        /*!< USB0 USBINTR_D: SRE Mask            */
+#define USB0_USBINTR_D_SLE_Pos                                8                                                         /*!< USB0 USBINTR_D: SLE Position        */
+#define USB0_USBINTR_D_SLE_Msk                                (0x01UL << USB0_USBINTR_D_SLE_Pos)                        /*!< USB0 USBINTR_D: SLE Mask            */
+#define USB0_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB0 USBINTR_D: NAKE Position       */
+#define USB0_USBINTR_D_NAKE_Msk                               (0x01UL << USB0_USBINTR_D_NAKE_Pos)                       /*!< USB0 USBINTR_D: NAKE Mask           */
+
+// -------------------------------------  USB0_USBINTR_H  -----------------------------------------
+#define USB0_USBINTR_H_UE_Pos                                 0                                                         /*!< USB0 USBINTR_H: UE Position         */
+#define USB0_USBINTR_H_UE_Msk                                 (0x01UL << USB0_USBINTR_H_UE_Pos)                         /*!< USB0 USBINTR_H: UE Mask             */
+#define USB0_USBINTR_H_UEE_Pos                                1                                                         /*!< USB0 USBINTR_H: UEE Position        */
+#define USB0_USBINTR_H_UEE_Msk                                (0x01UL << USB0_USBINTR_H_UEE_Pos)                        /*!< USB0 USBINTR_H: UEE Mask            */
+#define USB0_USBINTR_H_PCE_Pos                                2                                                         /*!< USB0 USBINTR_H: PCE Position        */
+#define USB0_USBINTR_H_PCE_Msk                                (0x01UL << USB0_USBINTR_H_PCE_Pos)                        /*!< USB0 USBINTR_H: PCE Mask            */
+#define USB0_USBINTR_H_FRE_Pos                                3                                                         /*!< USB0 USBINTR_H: FRE Position        */
+#define USB0_USBINTR_H_FRE_Msk                                (0x01UL << USB0_USBINTR_H_FRE_Pos)                        /*!< USB0 USBINTR_H: FRE Mask            */
+#define USB0_USBINTR_H_AAE_Pos                                5                                                         /*!< USB0 USBINTR_H: AAE Position        */
+#define USB0_USBINTR_H_AAE_Msk                                (0x01UL << USB0_USBINTR_H_AAE_Pos)                        /*!< USB0 USBINTR_H: AAE Mask            */
+#define USB0_USBINTR_H_SRE_Pos                                7                                                         /*!< USB0 USBINTR_H: SRE Position        */
+#define USB0_USBINTR_H_SRE_Msk                                (0x01UL << USB0_USBINTR_H_SRE_Pos)                        /*!< USB0 USBINTR_H: SRE Mask            */
+#define USB0_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB0 USBINTR_H: UAIE Position       */
+#define USB0_USBINTR_H_UAIE_Msk                               (0x01UL << USB0_USBINTR_H_UAIE_Pos)                       /*!< USB0 USBINTR_H: UAIE Mask           */
+#define USB0_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB0 USBINTR_H: UPIA Position       */
+#define USB0_USBINTR_H_UPIA_Msk                               (0x01UL << USB0_USBINTR_H_UPIA_Pos)                       /*!< USB0 USBINTR_H: UPIA Mask           */
+
+// -------------------------------------  USB0_FRINDEX_D  -----------------------------------------
+#define USB0_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */
+#define USB0_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask     */
+#define USB0_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */
+#define USB0_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask    */
+
+// -------------------------------------  USB0_FRINDEX_H  -----------------------------------------
+#define USB0_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */
+#define USB0_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask     */
+#define USB0_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */
+#define USB0_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask    */
+
+// -------------------------------------  USB0_DEVICEADDR  ----------------------------------------
+#define USB0_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB0 DEVICEADDR: USBADRA Position   */
+#define USB0_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB0_DEVICEADDR_USBADRA_Pos)                   /*!< USB0 DEVICEADDR: USBADRA Mask       */
+#define USB0_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB0 DEVICEADDR: USBADR Position    */
+#define USB0_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB0_DEVICEADDR_USBADR_Pos)                    /*!< USB0 DEVICEADDR: USBADR Mask        */
+
+// ----------------------------------  USB0_PERIODICLISTBASE  -------------------------------------
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ----------------------------------  USB0_ENDPOINTLISTADDR  -------------------------------------
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// -----------------------------------  USB0_ASYNCLISTADDR  ---------------------------------------
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// ---------------------------------------  USB0_TTCTRL  ------------------------------------------
+#define USB0_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB0 TTCTRL: TTHA Position          */
+#define USB0_TTCTRL_TTHA_Msk                                  (0x7fUL << USB0_TTCTRL_TTHA_Pos)                          /*!< USB0 TTCTRL: TTHA Mask              */
+
+// -------------------------------------  USB0_BURSTSIZE  -----------------------------------------
+#define USB0_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB0 BURSTSIZE: RXPBURST Position   */
+#define USB0_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos)             /*!< USB0 BURSTSIZE: RXPBURST Mask       */
+#define USB0_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB0 BURSTSIZE: TXPBURST Position   */
+#define USB0_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos)             /*!< USB0 BURSTSIZE: TXPBURST Mask       */
+
+// ------------------------------------  USB0_TXFILLTUNING  ---------------------------------------
+#define USB0_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB0 TXFILLTUNING: TXSCHOH Position */
+#define USB0_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB0 TXFILLTUNING: TXSCHOH Mask     */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// -------------------------------------  USB0_BINTERVAL  -----------------------------------------
+#define USB0_BINTERVAL_BINT_Pos                               0                                                         /*!< USB0 BINTERVAL: BINT Position       */
+#define USB0_BINTERVAL_BINT_Msk                               (0x0fUL << USB0_BINTERVAL_BINT_Pos)                       /*!< USB0 BINTERVAL: BINT Mask           */
+
+// --------------------------------------  USB0_ENDPTNAK  -----------------------------------------
+#define USB0_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB0 ENDPTNAK: EPRN0 Position       */
+#define USB0_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN0_Pos)                       /*!< USB0 ENDPTNAK: EPRN0 Mask           */
+#define USB0_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB0 ENDPTNAK: EPRN1 Position       */
+#define USB0_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN1_Pos)                       /*!< USB0 ENDPTNAK: EPRN1 Mask           */
+#define USB0_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB0 ENDPTNAK: EPRN2 Position       */
+#define USB0_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN2_Pos)                       /*!< USB0 ENDPTNAK: EPRN2 Mask           */
+#define USB0_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB0 ENDPTNAK: EPRN3 Position       */
+#define USB0_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN3_Pos)                       /*!< USB0 ENDPTNAK: EPRN3 Mask           */
+#define USB0_ENDPTNAK_EPRN4_Pos                               4                                                         /*!< USB0 ENDPTNAK: EPRN4 Position       */
+#define USB0_ENDPTNAK_EPRN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN4_Pos)                       /*!< USB0 ENDPTNAK: EPRN4 Mask           */
+#define USB0_ENDPTNAK_EPRN5_Pos                               5                                                         /*!< USB0 ENDPTNAK: EPRN5 Position       */
+#define USB0_ENDPTNAK_EPRN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN5_Pos)                       /*!< USB0 ENDPTNAK: EPRN5 Mask           */
+#define USB0_ENDPTNAK_EPTN0_Pos                               16                                                        /*!< USB0 ENDPTNAK: EPTN0 Position       */
+#define USB0_ENDPTNAK_EPTN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN0_Pos)                       /*!< USB0 ENDPTNAK: EPTN0 Mask           */
+#define USB0_ENDPTNAK_EPTN1_Pos                               17                                                        /*!< USB0 ENDPTNAK: EPTN1 Position       */
+#define USB0_ENDPTNAK_EPTN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN1_Pos)                       /*!< USB0 ENDPTNAK: EPTN1 Mask           */
+#define USB0_ENDPTNAK_EPTN2_Pos                               18                                                        /*!< USB0 ENDPTNAK: EPTN2 Position       */
+#define USB0_ENDPTNAK_EPTN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN2_Pos)                       /*!< USB0 ENDPTNAK: EPTN2 Mask           */
+#define USB0_ENDPTNAK_EPTN3_Pos                               19                                                        /*!< USB0 ENDPTNAK: EPTN3 Position       */
+#define USB0_ENDPTNAK_EPTN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN3_Pos)                       /*!< USB0 ENDPTNAK: EPTN3 Mask           */
+#define USB0_ENDPTNAK_EPTN4_Pos                               20                                                        /*!< USB0 ENDPTNAK: EPTN4 Position       */
+#define USB0_ENDPTNAK_EPTN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN4_Pos)                       /*!< USB0 ENDPTNAK: EPTN4 Mask           */
+#define USB0_ENDPTNAK_EPTN5_Pos                               21                                                        /*!< USB0 ENDPTNAK: EPTN5 Position       */
+#define USB0_ENDPTNAK_EPTN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN5_Pos)                       /*!< USB0 ENDPTNAK: EPTN5 Mask           */
+
+// -------------------------------------  USB0_ENDPTNAKEN  ----------------------------------------
+#define USB0_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB0 ENDPTNAKEN: EPRNE0 Position    */
+#define USB0_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE0 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB0 ENDPTNAKEN: EPRNE1 Position    */
+#define USB0_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE1 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB0 ENDPTNAKEN: EPRNE2 Position    */
+#define USB0_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE2 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB0 ENDPTNAKEN: EPRNE3 Position    */
+#define USB0_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE3 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE4_Pos                            4                                                         /*!< USB0 ENDPTNAKEN: EPRNE4 Position    */
+#define USB0_ENDPTNAKEN_EPRNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE4 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE5_Pos                            5                                                         /*!< USB0 ENDPTNAKEN: EPRNE5 Position    */
+#define USB0_ENDPTNAKEN_EPRNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE5 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE0_Pos                            16                                                        /*!< USB0 ENDPTNAKEN: EPTNE0 Position    */
+#define USB0_ENDPTNAKEN_EPTNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE0 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE1_Pos                            17                                                        /*!< USB0 ENDPTNAKEN: EPTNE1 Position    */
+#define USB0_ENDPTNAKEN_EPTNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE1 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE2_Pos                            18                                                        /*!< USB0 ENDPTNAKEN: EPTNE2 Position    */
+#define USB0_ENDPTNAKEN_EPTNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE2 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE3_Pos                            19                                                        /*!< USB0 ENDPTNAKEN: EPTNE3 Position    */
+#define USB0_ENDPTNAKEN_EPTNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE3 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE4_Pos                            20                                                        /*!< USB0 ENDPTNAKEN: EPTNE4 Position    */
+#define USB0_ENDPTNAKEN_EPTNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE4 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE5_Pos                            21                                                        /*!< USB0 ENDPTNAKEN: EPTNE5 Position    */
+#define USB0_ENDPTNAKEN_EPTNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE5 Mask        */
+
+// -------------------------------------  USB0_PORTSC1_D  -----------------------------------------
+#define USB0_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_D: CCS Position        */
+#define USB0_PORTSC1_D_CCS_Msk                                (0x01UL << USB0_PORTSC1_D_CCS_Pos)                        /*!< USB0 PORTSC1_D: CCS Mask            */
+#define USB0_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_D: PE Position         */
+#define USB0_PORTSC1_D_PE_Msk                                 (0x01UL << USB0_PORTSC1_D_PE_Pos)                         /*!< USB0 PORTSC1_D: PE Mask             */
+#define USB0_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_D: PEC Position        */
+#define USB0_PORTSC1_D_PEC_Msk                                (0x01UL << USB0_PORTSC1_D_PEC_Pos)                        /*!< USB0 PORTSC1_D: PEC Mask            */
+#define USB0_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_D: FPR Position        */
+#define USB0_PORTSC1_D_FPR_Msk                                (0x01UL << USB0_PORTSC1_D_FPR_Pos)                        /*!< USB0 PORTSC1_D: FPR Mask            */
+#define USB0_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_D: SUSP Position       */
+#define USB0_PORTSC1_D_SUSP_Msk                               (0x01UL << USB0_PORTSC1_D_SUSP_Pos)                       /*!< USB0 PORTSC1_D: SUSP Mask           */
+#define USB0_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_D: PR Position         */
+#define USB0_PORTSC1_D_PR_Msk                                 (0x01UL << USB0_PORTSC1_D_PR_Pos)                         /*!< USB0 PORTSC1_D: PR Mask             */
+#define USB0_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_D: HSP Position        */
+#define USB0_PORTSC1_D_HSP_Msk                                (0x01UL << USB0_PORTSC1_D_HSP_Pos)                        /*!< USB0 PORTSC1_D: HSP Mask            */
+#define USB0_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_D: PIC1_0 Position     */
+#define USB0_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos)                     /*!< USB0 PORTSC1_D: PIC1_0 Mask         */
+#define USB0_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_D: PTC3_0 Position     */
+#define USB0_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos)                     /*!< USB0 PORTSC1_D: PTC3_0 Mask         */
+#define USB0_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_D: PHCD Position       */
+#define USB0_PORTSC1_D_PHCD_Msk                               (0x01UL << USB0_PORTSC1_D_PHCD_Pos)                       /*!< USB0 PORTSC1_D: PHCD Mask           */
+#define USB0_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_D: PFSC Position       */
+#define USB0_PORTSC1_D_PFSC_Msk                               (0x01UL << USB0_PORTSC1_D_PFSC_Pos)                       /*!< USB0 PORTSC1_D: PFSC Mask           */
+#define USB0_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_D: PSPD Position       */
+#define USB0_PORTSC1_D_PSPD_Msk                               (0x03UL << USB0_PORTSC1_D_PSPD_Pos)                       /*!< USB0 PORTSC1_D: PSPD Mask           */
+
+// -------------------------------------  USB0_PORTSC1_H  -----------------------------------------
+#define USB0_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_H: CCS Position        */
+#define USB0_PORTSC1_H_CCS_Msk                                (0x01UL << USB0_PORTSC1_H_CCS_Pos)                        /*!< USB0 PORTSC1_H: CCS Mask            */
+#define USB0_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB0 PORTSC1_H: CSC Position        */
+#define USB0_PORTSC1_H_CSC_Msk                                (0x01UL << USB0_PORTSC1_H_CSC_Pos)                        /*!< USB0 PORTSC1_H: CSC Mask            */
+#define USB0_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_H: PE Position         */
+#define USB0_PORTSC1_H_PE_Msk                                 (0x01UL << USB0_PORTSC1_H_PE_Pos)                         /*!< USB0 PORTSC1_H: PE Mask             */
+#define USB0_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_H: PEC Position        */
+#define USB0_PORTSC1_H_PEC_Msk                                (0x01UL << USB0_PORTSC1_H_PEC_Pos)                        /*!< USB0 PORTSC1_H: PEC Mask            */
+#define USB0_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB0 PORTSC1_H: OCA Position        */
+#define USB0_PORTSC1_H_OCA_Msk                                (0x01UL << USB0_PORTSC1_H_OCA_Pos)                        /*!< USB0 PORTSC1_H: OCA Mask            */
+#define USB0_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB0 PORTSC1_H: OCC Position        */
+#define USB0_PORTSC1_H_OCC_Msk                                (0x01UL << USB0_PORTSC1_H_OCC_Pos)                        /*!< USB0 PORTSC1_H: OCC Mask            */
+#define USB0_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_H: FPR Position        */
+#define USB0_PORTSC1_H_FPR_Msk                                (0x01UL << USB0_PORTSC1_H_FPR_Pos)                        /*!< USB0 PORTSC1_H: FPR Mask            */
+#define USB0_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_H: SUSP Position       */
+#define USB0_PORTSC1_H_SUSP_Msk                               (0x01UL << USB0_PORTSC1_H_SUSP_Pos)                       /*!< USB0 PORTSC1_H: SUSP Mask           */
+#define USB0_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_H: PR Position         */
+#define USB0_PORTSC1_H_PR_Msk                                 (0x01UL << USB0_PORTSC1_H_PR_Pos)                         /*!< USB0 PORTSC1_H: PR Mask             */
+#define USB0_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_H: HSP Position        */
+#define USB0_PORTSC1_H_HSP_Msk                                (0x01UL << USB0_PORTSC1_H_HSP_Pos)                        /*!< USB0 PORTSC1_H: HSP Mask            */
+#define USB0_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB0 PORTSC1_H: LS Position         */
+#define USB0_PORTSC1_H_LS_Msk                                 (0x03UL << USB0_PORTSC1_H_LS_Pos)                         /*!< USB0 PORTSC1_H: LS Mask             */
+#define USB0_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB0 PORTSC1_H: PP Position         */
+#define USB0_PORTSC1_H_PP_Msk                                 (0x01UL << USB0_PORTSC1_H_PP_Pos)                         /*!< USB0 PORTSC1_H: PP Mask             */
+#define USB0_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_H: PIC1_0 Position     */
+#define USB0_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos)                     /*!< USB0 PORTSC1_H: PIC1_0 Mask         */
+#define USB0_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_H: PTC3_0 Position     */
+#define USB0_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos)                     /*!< USB0 PORTSC1_H: PTC3_0 Mask         */
+#define USB0_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB0 PORTSC1_H: WKCN Position       */
+#define USB0_PORTSC1_H_WKCN_Msk                               (0x01UL << USB0_PORTSC1_H_WKCN_Pos)                       /*!< USB0 PORTSC1_H: WKCN Mask           */
+#define USB0_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB0 PORTSC1_H: WKDC Position       */
+#define USB0_PORTSC1_H_WKDC_Msk                               (0x01UL << USB0_PORTSC1_H_WKDC_Pos)                       /*!< USB0 PORTSC1_H: WKDC Mask           */
+#define USB0_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB0 PORTSC1_H: WKOC Position       */
+#define USB0_PORTSC1_H_WKOC_Msk                               (0x01UL << USB0_PORTSC1_H_WKOC_Pos)                       /*!< USB0 PORTSC1_H: WKOC Mask           */
+#define USB0_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_H: PHCD Position       */
+#define USB0_PORTSC1_H_PHCD_Msk                               (0x01UL << USB0_PORTSC1_H_PHCD_Pos)                       /*!< USB0 PORTSC1_H: PHCD Mask           */
+#define USB0_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_H: PFSC Position       */
+#define USB0_PORTSC1_H_PFSC_Msk                               (0x01UL << USB0_PORTSC1_H_PFSC_Pos)                       /*!< USB0 PORTSC1_H: PFSC Mask           */
+#define USB0_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_H: PSPD Position       */
+#define USB0_PORTSC1_H_PSPD_Msk                               (0x03UL << USB0_PORTSC1_H_PSPD_Pos)                       /*!< USB0 PORTSC1_H: PSPD Mask           */
+
+// ---------------------------------------  USB0_OTGSC  -------------------------------------------
+#define USB0_OTGSC_VD_Pos                                     0                                                         /*!< USB0 OTGSC: VD Position             */
+#define USB0_OTGSC_VD_Msk                                     (0x01UL << USB0_OTGSC_VD_Pos)                             /*!< USB0 OTGSC: VD Mask                 */
+#define USB0_OTGSC_VC_Pos                                     1                                                         /*!< USB0 OTGSC: VC Position             */
+#define USB0_OTGSC_VC_Msk                                     (0x01UL << USB0_OTGSC_VC_Pos)                             /*!< USB0 OTGSC: VC Mask                 */
+#define USB0_OTGSC_HAAR_Pos                                   2                                                         /*!< USB0 OTGSC: HAAR Position           */
+#define USB0_OTGSC_HAAR_Msk                                   (0x01UL << USB0_OTGSC_HAAR_Pos)                           /*!< USB0 OTGSC: HAAR Mask               */
+#define USB0_OTGSC_OT_Pos                                     3                                                         /*!< USB0 OTGSC: OT Position             */
+#define USB0_OTGSC_OT_Msk                                     (0x01UL << USB0_OTGSC_OT_Pos)                             /*!< USB0 OTGSC: OT Mask                 */
+#define USB0_OTGSC_DP_Pos                                     4                                                         /*!< USB0 OTGSC: DP Position             */
+#define USB0_OTGSC_DP_Msk                                     (0x01UL << USB0_OTGSC_DP_Pos)                             /*!< USB0 OTGSC: DP Mask                 */
+#define USB0_OTGSC_IDPU_Pos                                   5                                                         /*!< USB0 OTGSC: IDPU Position           */
+#define USB0_OTGSC_IDPU_Msk                                   (0x01UL << USB0_OTGSC_IDPU_Pos)                           /*!< USB0 OTGSC: IDPU Mask               */
+#define USB0_OTGSC_HADP_Pos                                   6                                                         /*!< USB0 OTGSC: HADP Position           */
+#define USB0_OTGSC_HADP_Msk                                   (0x01UL << USB0_OTGSC_HADP_Pos)                           /*!< USB0 OTGSC: HADP Mask               */
+#define USB0_OTGSC_HABA_Pos                                   7                                                         /*!< USB0 OTGSC: HABA Position           */
+#define USB0_OTGSC_HABA_Msk                                   (0x01UL << USB0_OTGSC_HABA_Pos)                           /*!< USB0 OTGSC: HABA Mask               */
+#define USB0_OTGSC_ID_Pos                                     8                                                         /*!< USB0 OTGSC: ID Position             */
+#define USB0_OTGSC_ID_Msk                                     (0x01UL << USB0_OTGSC_ID_Pos)                             /*!< USB0 OTGSC: ID Mask                 */
+#define USB0_OTGSC_AVV_Pos                                    9                                                         /*!< USB0 OTGSC: AVV Position            */
+#define USB0_OTGSC_AVV_Msk                                    (0x01UL << USB0_OTGSC_AVV_Pos)                            /*!< USB0 OTGSC: AVV Mask                */
+#define USB0_OTGSC_ASV_Pos                                    10                                                        /*!< USB0 OTGSC: ASV Position            */
+#define USB0_OTGSC_ASV_Msk                                    (0x01UL << USB0_OTGSC_ASV_Pos)                            /*!< USB0 OTGSC: ASV Mask                */
+#define USB0_OTGSC_BSV_Pos                                    11                                                        /*!< USB0 OTGSC: BSV Position            */
+#define USB0_OTGSC_BSV_Msk                                    (0x01UL << USB0_OTGSC_BSV_Pos)                            /*!< USB0 OTGSC: BSV Mask                */
+#define USB0_OTGSC_BSE_Pos                                    12                                                        /*!< USB0 OTGSC: BSE Position            */
+#define USB0_OTGSC_BSE_Msk                                    (0x01UL << USB0_OTGSC_BSE_Pos)                            /*!< USB0 OTGSC: BSE Mask                */
+#define USB0_OTGSC_MS1T_Pos                                   13                                                        /*!< USB0 OTGSC: MS1T Position           */
+#define USB0_OTGSC_MS1T_Msk                                   (0x01UL << USB0_OTGSC_MS1T_Pos)                           /*!< USB0 OTGSC: MS1T Mask               */
+#define USB0_OTGSC_DPS_Pos                                    14                                                        /*!< USB0 OTGSC: DPS Position            */
+#define USB0_OTGSC_DPS_Msk                                    (0x01UL << USB0_OTGSC_DPS_Pos)                            /*!< USB0 OTGSC: DPS Mask                */
+#define USB0_OTGSC_IDIS_Pos                                   16                                                        /*!< USB0 OTGSC: IDIS Position           */
+#define USB0_OTGSC_IDIS_Msk                                   (0x01UL << USB0_OTGSC_IDIS_Pos)                           /*!< USB0 OTGSC: IDIS Mask               */
+#define USB0_OTGSC_AVVIS_Pos                                  17                                                        /*!< USB0 OTGSC: AVVIS Position          */
+#define USB0_OTGSC_AVVIS_Msk                                  (0x01UL << USB0_OTGSC_AVVIS_Pos)                          /*!< USB0 OTGSC: AVVIS Mask              */
+#define USB0_OTGSC_ASVIS_Pos                                  18                                                        /*!< USB0 OTGSC: ASVIS Position          */
+#define USB0_OTGSC_ASVIS_Msk                                  (0x01UL << USB0_OTGSC_ASVIS_Pos)                          /*!< USB0 OTGSC: ASVIS Mask              */
+#define USB0_OTGSC_BSVIS_Pos                                  19                                                        /*!< USB0 OTGSC: BSVIS Position          */
+#define USB0_OTGSC_BSVIS_Msk                                  (0x01UL << USB0_OTGSC_BSVIS_Pos)                          /*!< USB0 OTGSC: BSVIS Mask              */
+#define USB0_OTGSC_BSEIS_Pos                                  20                                                        /*!< USB0 OTGSC: BSEIS Position          */
+#define USB0_OTGSC_BSEIS_Msk                                  (0x01UL << USB0_OTGSC_BSEIS_Pos)                          /*!< USB0 OTGSC: BSEIS Mask              */
+#define USB0_OTGSC_ms1S_Pos                                   21                                                        /*!< USB0 OTGSC: ms1S Position           */
+#define USB0_OTGSC_ms1S_Msk                                   (0x01UL << USB0_OTGSC_ms1S_Pos)                           /*!< USB0 OTGSC: ms1S Mask               */
+#define USB0_OTGSC_DPIS_Pos                                   22                                                        /*!< USB0 OTGSC: DPIS Position           */
+#define USB0_OTGSC_DPIS_Msk                                   (0x01UL << USB0_OTGSC_DPIS_Pos)                           /*!< USB0 OTGSC: DPIS Mask               */
+#define USB0_OTGSC_IDIE_Pos                                   24                                                        /*!< USB0 OTGSC: IDIE Position           */
+#define USB0_OTGSC_IDIE_Msk                                   (0x01UL << USB0_OTGSC_IDIE_Pos)                           /*!< USB0 OTGSC: IDIE Mask               */
+#define USB0_OTGSC_AVVIE_Pos                                  25                                                        /*!< USB0 OTGSC: AVVIE Position          */
+#define USB0_OTGSC_AVVIE_Msk                                  (0x01UL << USB0_OTGSC_AVVIE_Pos)                          /*!< USB0 OTGSC: AVVIE Mask              */
+#define USB0_OTGSC_ASVIE_Pos                                  26                                                        /*!< USB0 OTGSC: ASVIE Position          */
+#define USB0_OTGSC_ASVIE_Msk                                  (0x01UL << USB0_OTGSC_ASVIE_Pos)                          /*!< USB0 OTGSC: ASVIE Mask              */
+#define USB0_OTGSC_BSVIE_Pos                                  27                                                        /*!< USB0 OTGSC: BSVIE Position          */
+#define USB0_OTGSC_BSVIE_Msk                                  (0x01UL << USB0_OTGSC_BSVIE_Pos)                          /*!< USB0 OTGSC: BSVIE Mask              */
+#define USB0_OTGSC_BSEIE_Pos                                  28                                                        /*!< USB0 OTGSC: BSEIE Position          */
+#define USB0_OTGSC_BSEIE_Msk                                  (0x01UL << USB0_OTGSC_BSEIE_Pos)                          /*!< USB0 OTGSC: BSEIE Mask              */
+#define USB0_OTGSC_MS1E_Pos                                   29                                                        /*!< USB0 OTGSC: MS1E Position           */
+#define USB0_OTGSC_MS1E_Msk                                   (0x01UL << USB0_OTGSC_MS1E_Pos)                           /*!< USB0 OTGSC: MS1E Mask               */
+#define USB0_OTGSC_DPIE_Pos                                   30                                                        /*!< USB0 OTGSC: DPIE Position           */
+#define USB0_OTGSC_DPIE_Msk                                   (0x01UL << USB0_OTGSC_DPIE_Pos)                           /*!< USB0 OTGSC: DPIE Mask               */
+
+// -------------------------------------  USB0_USBMODE_D  -----------------------------------------
+#define USB0_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB0 USBMODE_D: CM1_0 Position      */
+#define USB0_USBMODE_D_CM1_0_Msk                              (0x03UL << USB0_USBMODE_D_CM1_0_Pos)                      /*!< USB0 USBMODE_D: CM1_0 Mask          */
+#define USB0_USBMODE_D_ES_Pos                                 2                                                         /*!< USB0 USBMODE_D: ES Position         */
+#define USB0_USBMODE_D_ES_Msk                                 (0x01UL << USB0_USBMODE_D_ES_Pos)                         /*!< USB0 USBMODE_D: ES Mask             */
+#define USB0_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB0 USBMODE_D: SLOM Position       */
+#define USB0_USBMODE_D_SLOM_Msk                               (0x01UL << USB0_USBMODE_D_SLOM_Pos)                       /*!< USB0 USBMODE_D: SLOM Mask           */
+#define USB0_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_D: SDIS Position       */
+#define USB0_USBMODE_D_SDIS_Msk                               (0x01UL << USB0_USBMODE_D_SDIS_Pos)                       /*!< USB0 USBMODE_D: SDIS Mask           */
+
+// -------------------------------------  USB0_USBMODE_H  -----------------------------------------
+#define USB0_USBMODE_H_CM_Pos                                 0                                                         /*!< USB0 USBMODE_H: CM Position         */
+#define USB0_USBMODE_H_CM_Msk                                 (0x03UL << USB0_USBMODE_H_CM_Pos)                         /*!< USB0 USBMODE_H: CM Mask             */
+#define USB0_USBMODE_H_ES_Pos                                 2                                                         /*!< USB0 USBMODE_H: ES Position         */
+#define USB0_USBMODE_H_ES_Msk                                 (0x01UL << USB0_USBMODE_H_ES_Pos)                         /*!< USB0 USBMODE_H: ES Mask             */
+#define USB0_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_H: SDIS Position       */
+#define USB0_USBMODE_H_SDIS_Msk                               (0x01UL << USB0_USBMODE_H_SDIS_Pos)                       /*!< USB0 USBMODE_H: SDIS Mask           */
+#define USB0_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB0 USBMODE_H: VBPS Position       */
+#define USB0_USBMODE_H_VBPS_Msk                               (0x01UL << USB0_USBMODE_H_VBPS_Pos)                       /*!< USB0 USBMODE_H: VBPS Mask           */
+
+// -----------------------------------  USB0_ENDPTSETUPSTAT  --------------------------------------
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos               4                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos               5                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */
+
+// -------------------------------------  USB0_ENDPTPRIME  ----------------------------------------
+#define USB0_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB0 ENDPTPRIME: PERB0 Position     */
+#define USB0_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB0_Pos)                     /*!< USB0 ENDPTPRIME: PERB0 Mask         */
+#define USB0_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB0 ENDPTPRIME: PERB1 Position     */
+#define USB0_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB1_Pos)                     /*!< USB0 ENDPTPRIME: PERB1 Mask         */
+#define USB0_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB0 ENDPTPRIME: PERB2 Position     */
+#define USB0_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB2_Pos)                     /*!< USB0 ENDPTPRIME: PERB2 Mask         */
+#define USB0_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB0 ENDPTPRIME: PERB3 Position     */
+#define USB0_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB3_Pos)                     /*!< USB0 ENDPTPRIME: PERB3 Mask         */
+#define USB0_ENDPTPRIME_PERB4_Pos                             4                                                         /*!< USB0 ENDPTPRIME: PERB4 Position     */
+#define USB0_ENDPTPRIME_PERB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB4_Pos)                     /*!< USB0 ENDPTPRIME: PERB4 Mask         */
+#define USB0_ENDPTPRIME_PERB5_Pos                             5                                                         /*!< USB0 ENDPTPRIME: PERB5 Position     */
+#define USB0_ENDPTPRIME_PERB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB5_Pos)                     /*!< USB0 ENDPTPRIME: PERB5 Mask         */
+#define USB0_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB0 ENDPTPRIME: PETB0 Position     */
+#define USB0_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB0_Pos)                     /*!< USB0 ENDPTPRIME: PETB0 Mask         */
+#define USB0_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB0 ENDPTPRIME: PETB1 Position     */
+#define USB0_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB1_Pos)                     /*!< USB0 ENDPTPRIME: PETB1 Mask         */
+#define USB0_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB0 ENDPTPRIME: PETB2 Position     */
+#define USB0_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB2_Pos)                     /*!< USB0 ENDPTPRIME: PETB2 Mask         */
+#define USB0_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB0 ENDPTPRIME: PETB3 Position     */
+#define USB0_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB3_Pos)                     /*!< USB0 ENDPTPRIME: PETB3 Mask         */
+#define USB0_ENDPTPRIME_PETB4_Pos                             20                                                        /*!< USB0 ENDPTPRIME: PETB4 Position     */
+#define USB0_ENDPTPRIME_PETB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB4_Pos)                     /*!< USB0 ENDPTPRIME: PETB4 Mask         */
+#define USB0_ENDPTPRIME_PETB5_Pos                             21                                                        /*!< USB0 ENDPTPRIME: PETB5 Position     */
+#define USB0_ENDPTPRIME_PETB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB5_Pos)                     /*!< USB0 ENDPTPRIME: PETB5 Mask         */
+
+// -------------------------------------  USB0_ENDPTFLUSH  ----------------------------------------
+#define USB0_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB0 ENDPTFLUSH: FERB0 Position     */
+#define USB0_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos)                     /*!< USB0 ENDPTFLUSH: FERB0 Mask         */
+#define USB0_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB0 ENDPTFLUSH: FERB1 Position     */
+#define USB0_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos)                     /*!< USB0 ENDPTFLUSH: FERB1 Mask         */
+#define USB0_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB0 ENDPTFLUSH: FERB2 Position     */
+#define USB0_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos)                     /*!< USB0 ENDPTFLUSH: FERB2 Mask         */
+#define USB0_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB0 ENDPTFLUSH: FERB3 Position     */
+#define USB0_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos)                     /*!< USB0 ENDPTFLUSH: FERB3 Mask         */
+#define USB0_ENDPTFLUSH_FERB4_Pos                             4                                                         /*!< USB0 ENDPTFLUSH: FERB4 Position     */
+#define USB0_ENDPTFLUSH_FERB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos)                     /*!< USB0 ENDPTFLUSH: FERB4 Mask         */
+#define USB0_ENDPTFLUSH_FERB5_Pos                             5                                                         /*!< USB0 ENDPTFLUSH: FERB5 Position     */
+#define USB0_ENDPTFLUSH_FERB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos)                     /*!< USB0 ENDPTFLUSH: FERB5 Mask         */
+#define USB0_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB0 ENDPTFLUSH: FETB0 Position     */
+#define USB0_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos)                     /*!< USB0 ENDPTFLUSH: FETB0 Mask         */
+#define USB0_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB0 ENDPTFLUSH: FETB1 Position     */
+#define USB0_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos)                     /*!< USB0 ENDPTFLUSH: FETB1 Mask         */
+#define USB0_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB0 ENDPTFLUSH: FETB2 Position     */
+#define USB0_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos)                     /*!< USB0 ENDPTFLUSH: FETB2 Mask         */
+#define USB0_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB0 ENDPTFLUSH: FETB3 Position     */
+#define USB0_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos)                     /*!< USB0 ENDPTFLUSH: FETB3 Mask         */
+#define USB0_ENDPTFLUSH_FETB4_Pos                             20                                                        /*!< USB0 ENDPTFLUSH: FETB4 Position     */
+#define USB0_ENDPTFLUSH_FETB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos)                     /*!< USB0 ENDPTFLUSH: FETB4 Mask         */
+#define USB0_ENDPTFLUSH_FETB5_Pos                             21                                                        /*!< USB0 ENDPTFLUSH: FETB5 Position     */
+#define USB0_ENDPTFLUSH_FETB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos)                     /*!< USB0 ENDPTFLUSH: FETB5 Mask         */
+
+// -------------------------------------  USB0_ENDPTSTAT  -----------------------------------------
+#define USB0_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB0 ENDPTSTAT: ERBR0 Position      */
+#define USB0_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos)                      /*!< USB0 ENDPTSTAT: ERBR0 Mask          */
+#define USB0_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB0 ENDPTSTAT: ERBR1 Position      */
+#define USB0_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos)                      /*!< USB0 ENDPTSTAT: ERBR1 Mask          */
+#define USB0_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB0 ENDPTSTAT: ERBR2 Position      */
+#define USB0_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos)                      /*!< USB0 ENDPTSTAT: ERBR2 Mask          */
+#define USB0_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB0 ENDPTSTAT: ERBR3 Position      */
+#define USB0_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos)                      /*!< USB0 ENDPTSTAT: ERBR3 Mask          */
+#define USB0_ENDPTSTAT_ERBR4_Pos                              4                                                         /*!< USB0 ENDPTSTAT: ERBR4 Position      */
+#define USB0_ENDPTSTAT_ERBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos)                      /*!< USB0 ENDPTSTAT: ERBR4 Mask          */
+#define USB0_ENDPTSTAT_ERBR5_Pos                              5                                                         /*!< USB0 ENDPTSTAT: ERBR5 Position      */
+#define USB0_ENDPTSTAT_ERBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos)                      /*!< USB0 ENDPTSTAT: ERBR5 Mask          */
+#define USB0_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB0 ENDPTSTAT: ETBR0 Position      */
+#define USB0_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos)                      /*!< USB0 ENDPTSTAT: ETBR0 Mask          */
+#define USB0_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB0 ENDPTSTAT: ETBR1 Position      */
+#define USB0_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos)                      /*!< USB0 ENDPTSTAT: ETBR1 Mask          */
+#define USB0_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB0 ENDPTSTAT: ETBR2 Position      */
+#define USB0_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos)                      /*!< USB0 ENDPTSTAT: ETBR2 Mask          */
+#define USB0_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB0 ENDPTSTAT: ETBR3 Position      */
+#define USB0_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos)                      /*!< USB0 ENDPTSTAT: ETBR3 Mask          */
+#define USB0_ENDPTSTAT_ETBR4_Pos                              20                                                        /*!< USB0 ENDPTSTAT: ETBR4 Position      */
+#define USB0_ENDPTSTAT_ETBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos)                      /*!< USB0 ENDPTSTAT: ETBR4 Mask          */
+#define USB0_ENDPTSTAT_ETBR5_Pos                              21                                                        /*!< USB0 ENDPTSTAT: ETBR5 Position      */
+#define USB0_ENDPTSTAT_ETBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos)                      /*!< USB0 ENDPTSTAT: ETBR5 Mask          */
+
+// -----------------------------------  USB0_ENDPTCOMPLETE  ---------------------------------------
+#define USB0_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB0 ENDPTCOMPLETE: ERCE0 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB0 ENDPTCOMPLETE: ERCE1 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB0 ENDPTCOMPLETE: ERCE2 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB0 ENDPTCOMPLETE: ERCE3 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE4_Pos                          4                                                         /*!< USB0 ENDPTCOMPLETE: ERCE4 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE5_Pos                          5                                                         /*!< USB0 ENDPTCOMPLETE: ERCE5 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB0 ENDPTCOMPLETE: ETCE0 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB0 ENDPTCOMPLETE: ETCE1 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB0 ENDPTCOMPLETE: ETCE2 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB0 ENDPTCOMPLETE: ETCE3 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE4_Pos                          20                                                        /*!< USB0 ENDPTCOMPLETE: ETCE4 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE5_Pos                          21                                                        /*!< USB0 ENDPTCOMPLETE: ETCE5 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask      */
+
+// -------------------------------------  USB0_ENDPTCTRL0  ----------------------------------------
+#define USB0_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL0: RXS Position       */
+#define USB0_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXS_Pos)                       /*!< USB0 ENDPTCTRL0: RXS Mask           */
+#define USB0_ENDPTCTRL0_RXT1_0_Pos                            2                                                         /*!< USB0 ENDPTCTRL0: RXT1_0 Position    */
+#define USB0_ENDPTCTRL0_RXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: RXT1_0 Mask        */
+#define USB0_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL0: RXE Position       */
+#define USB0_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXE_Pos)                       /*!< USB0 ENDPTCTRL0: RXE Mask           */
+#define USB0_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL0: TXS Position       */
+#define USB0_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXS_Pos)                       /*!< USB0 ENDPTCTRL0: TXS Mask           */
+#define USB0_ENDPTCTRL0_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL0: TXT1_0 Position    */
+#define USB0_ENDPTCTRL0_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL0: TXE Position       */
+#define USB0_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXE_Pos)                       /*!< USB0 ENDPTCTRL0: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL1  ----------------------------------------
+#define USB0_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL1: RXS Position       */
+#define USB0_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXS_Pos)                       /*!< USB0 ENDPTCTRL1: RXS Mask           */
+#define USB0_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL1: RXT Position       */
+#define USB0_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL1_RXT_Pos)                       /*!< USB0 ENDPTCTRL1: RXT Mask           */
+#define USB0_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL1: RXI Position       */
+#define USB0_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXI_Pos)                       /*!< USB0 ENDPTCTRL1: RXI Mask           */
+#define USB0_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL1: RXR Position       */
+#define USB0_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXR_Pos)                       /*!< USB0 ENDPTCTRL1: RXR Mask           */
+#define USB0_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL1: RXE Position       */
+#define USB0_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXE_Pos)                       /*!< USB0 ENDPTCTRL1: RXE Mask           */
+#define USB0_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL1: TXS Position       */
+#define USB0_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXS_Pos)                       /*!< USB0 ENDPTCTRL1: TXS Mask           */
+#define USB0_ENDPTCTRL1_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL1: TXT1_0 Position    */
+#define USB0_ENDPTCTRL1_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL1: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL1: TXI Position       */
+#define USB0_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXI_Pos)                       /*!< USB0 ENDPTCTRL1: TXI Mask           */
+#define USB0_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL1: TXR Position       */
+#define USB0_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXR_Pos)                       /*!< USB0 ENDPTCTRL1: TXR Mask           */
+#define USB0_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL1: TXE Position       */
+#define USB0_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXE_Pos)                       /*!< USB0 ENDPTCTRL1: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL2  ----------------------------------------
+#define USB0_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL2: RXS Position       */
+#define USB0_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXS_Pos)                       /*!< USB0 ENDPTCTRL2: RXS Mask           */
+#define USB0_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL2: RXT Position       */
+#define USB0_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL2_RXT_Pos)                       /*!< USB0 ENDPTCTRL2: RXT Mask           */
+#define USB0_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL2: RXI Position       */
+#define USB0_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXI_Pos)                       /*!< USB0 ENDPTCTRL2: RXI Mask           */
+#define USB0_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL2: RXR Position       */
+#define USB0_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXR_Pos)                       /*!< USB0 ENDPTCTRL2: RXR Mask           */
+#define USB0_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL2: RXE Position       */
+#define USB0_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXE_Pos)                       /*!< USB0 ENDPTCTRL2: RXE Mask           */
+#define USB0_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL2: TXS Position       */
+#define USB0_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXS_Pos)                       /*!< USB0 ENDPTCTRL2: TXS Mask           */
+#define USB0_ENDPTCTRL2_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL2: TXT1_0 Position    */
+#define USB0_ENDPTCTRL2_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL2: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL2: TXI Position       */
+#define USB0_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXI_Pos)                       /*!< USB0 ENDPTCTRL2: TXI Mask           */
+#define USB0_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL2: TXR Position       */
+#define USB0_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXR_Pos)                       /*!< USB0 ENDPTCTRL2: TXR Mask           */
+#define USB0_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL2: TXE Position       */
+#define USB0_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXE_Pos)                       /*!< USB0 ENDPTCTRL2: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL3  ----------------------------------------
+#define USB0_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL3: RXS Position       */
+#define USB0_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXS_Pos)                       /*!< USB0 ENDPTCTRL3: RXS Mask           */
+#define USB0_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL3: RXT Position       */
+#define USB0_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL3_RXT_Pos)                       /*!< USB0 ENDPTCTRL3: RXT Mask           */
+#define USB0_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL3: RXI Position       */
+#define USB0_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXI_Pos)                       /*!< USB0 ENDPTCTRL3: RXI Mask           */
+#define USB0_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL3: RXR Position       */
+#define USB0_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXR_Pos)                       /*!< USB0 ENDPTCTRL3: RXR Mask           */
+#define USB0_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL3: RXE Position       */
+#define USB0_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXE_Pos)                       /*!< USB0 ENDPTCTRL3: RXE Mask           */
+#define USB0_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL3: TXS Position       */
+#define USB0_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXS_Pos)                       /*!< USB0 ENDPTCTRL3: TXS Mask           */
+#define USB0_ENDPTCTRL3_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL3: TXT1_0 Position    */
+#define USB0_ENDPTCTRL3_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL3: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL3: TXI Position       */
+#define USB0_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXI_Pos)                       /*!< USB0 ENDPTCTRL3: TXI Mask           */
+#define USB0_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL3: TXR Position       */
+#define USB0_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXR_Pos)                       /*!< USB0 ENDPTCTRL3: TXR Mask           */
+#define USB0_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL3: TXE Position       */
+#define USB0_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXE_Pos)                       /*!< USB0 ENDPTCTRL3: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL4  ----------------------------------------
+#define USB0_ENDPTCTRL4_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL4: RXS Position       */
+#define USB0_ENDPTCTRL4_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXS_Pos)                       /*!< USB0 ENDPTCTRL4: RXS Mask           */
+#define USB0_ENDPTCTRL4_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL4: RXT Position       */
+#define USB0_ENDPTCTRL4_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL4_RXT_Pos)                       /*!< USB0 ENDPTCTRL4: RXT Mask           */
+#define USB0_ENDPTCTRL4_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL4: RXI Position       */
+#define USB0_ENDPTCTRL4_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXI_Pos)                       /*!< USB0 ENDPTCTRL4: RXI Mask           */
+#define USB0_ENDPTCTRL4_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL4: RXR Position       */
+#define USB0_ENDPTCTRL4_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXR_Pos)                       /*!< USB0 ENDPTCTRL4: RXR Mask           */
+#define USB0_ENDPTCTRL4_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL4: RXE Position       */
+#define USB0_ENDPTCTRL4_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXE_Pos)                       /*!< USB0 ENDPTCTRL4: RXE Mask           */
+#define USB0_ENDPTCTRL4_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL4: TXS Position       */
+#define USB0_ENDPTCTRL4_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXS_Pos)                       /*!< USB0 ENDPTCTRL4: TXS Mask           */
+#define USB0_ENDPTCTRL4_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL4: TXT1_0 Position    */
+#define USB0_ENDPTCTRL4_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL4: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL4_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL4: TXI Position       */
+#define USB0_ENDPTCTRL4_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXI_Pos)                       /*!< USB0 ENDPTCTRL4: TXI Mask           */
+#define USB0_ENDPTCTRL4_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL4: TXR Position       */
+#define USB0_ENDPTCTRL4_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXR_Pos)                       /*!< USB0 ENDPTCTRL4: TXR Mask           */
+#define USB0_ENDPTCTRL4_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL4: TXE Position       */
+#define USB0_ENDPTCTRL4_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXE_Pos)                       /*!< USB0 ENDPTCTRL4: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL5  ----------------------------------------
+#define USB0_ENDPTCTRL5_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL5: RXS Position       */
+#define USB0_ENDPTCTRL5_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXS_Pos)                       /*!< USB0 ENDPTCTRL5: RXS Mask           */
+#define USB0_ENDPTCTRL5_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL5: RXT Position       */
+#define USB0_ENDPTCTRL5_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL5_RXT_Pos)                       /*!< USB0 ENDPTCTRL5: RXT Mask           */
+#define USB0_ENDPTCTRL5_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL5: RXI Position       */
+#define USB0_ENDPTCTRL5_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXI_Pos)                       /*!< USB0 ENDPTCTRL5: RXI Mask           */
+#define USB0_ENDPTCTRL5_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL5: RXR Position       */
+#define USB0_ENDPTCTRL5_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXR_Pos)                       /*!< USB0 ENDPTCTRL5: RXR Mask           */
+#define USB0_ENDPTCTRL5_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL5: RXE Position       */
+#define USB0_ENDPTCTRL5_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXE_Pos)                       /*!< USB0 ENDPTCTRL5: RXE Mask           */
+#define USB0_ENDPTCTRL5_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL5: TXS Position       */
+#define USB0_ENDPTCTRL5_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXS_Pos)                       /*!< USB0 ENDPTCTRL5: TXS Mask           */
+#define USB0_ENDPTCTRL5_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL5: TXT1_0 Position    */
+#define USB0_ENDPTCTRL5_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL5: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL5_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL5: TXI Position       */
+#define USB0_ENDPTCTRL5_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXI_Pos)                       /*!< USB0 ENDPTCTRL5: TXI Mask           */
+#define USB0_ENDPTCTRL5_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL5: TXR Position       */
+#define USB0_ENDPTCTRL5_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXR_Pos)                       /*!< USB0 ENDPTCTRL5: TXR Mask           */
+#define USB0_ENDPTCTRL5_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL5: TXE Position       */
+#define USB0_ENDPTCTRL5_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXE_Pos)                       /*!< USB0 ENDPTCTRL5: TXE Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 USB1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  USB1_CAPLENGTH  -----------------------------------------
+#define USB1_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB1 CAPLENGTH: CAPLENGTH Position  */
+#define USB1_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB1 CAPLENGTH: CAPLENGTH Mask      */
+#define USB1_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB1 CAPLENGTH: HCIVERSION Position */
+#define USB1_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos)           /*!< USB1 CAPLENGTH: HCIVERSION Mask     */
+
+// -------------------------------------  USB1_HCSPARAMS  -----------------------------------------
+#define USB1_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB1 HCSPARAMS: N_PORTS Position    */
+#define USB1_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos)                    /*!< USB1 HCSPARAMS: N_PORTS Mask        */
+#define USB1_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB1 HCSPARAMS: PPC Position        */
+#define USB1_HCSPARAMS_PPC_Msk                                (0x01UL << USB1_HCSPARAMS_PPC_Pos)                        /*!< USB1 HCSPARAMS: PPC Mask            */
+#define USB1_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB1 HCSPARAMS: N_PCC Position      */
+#define USB1_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos)                      /*!< USB1 HCSPARAMS: N_PCC Mask          */
+#define USB1_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB1 HCSPARAMS: N_CC Position       */
+#define USB1_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB1_HCSPARAMS_N_CC_Pos)                       /*!< USB1 HCSPARAMS: N_CC Mask           */
+#define USB1_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB1 HCSPARAMS: PI Position         */
+#define USB1_HCSPARAMS_PI_Msk                                 (0x01UL << USB1_HCSPARAMS_PI_Pos)                         /*!< USB1 HCSPARAMS: PI Mask             */
+#define USB1_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB1 HCSPARAMS: N_PTT Position      */
+#define USB1_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos)                      /*!< USB1 HCSPARAMS: N_PTT Mask          */
+#define USB1_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB1 HCSPARAMS: N_TT Position       */
+#define USB1_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB1_HCSPARAMS_N_TT_Pos)                       /*!< USB1 HCSPARAMS: N_TT Mask           */
+
+// -------------------------------------  USB1_HCCPARAMS  -----------------------------------------
+#define USB1_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB1 HCCPARAMS: ADC Position        */
+#define USB1_HCCPARAMS_ADC_Msk                                (0x01UL << USB1_HCCPARAMS_ADC_Pos)                        /*!< USB1 HCCPARAMS: ADC Mask            */
+#define USB1_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB1 HCCPARAMS: PFL Position        */
+#define USB1_HCCPARAMS_PFL_Msk                                (0x01UL << USB1_HCCPARAMS_PFL_Pos)                        /*!< USB1 HCCPARAMS: PFL Mask            */
+#define USB1_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB1 HCCPARAMS: ASP Position        */
+#define USB1_HCCPARAMS_ASP_Msk                                (0x01UL << USB1_HCCPARAMS_ASP_Pos)                        /*!< USB1 HCCPARAMS: ASP Mask            */
+#define USB1_HCCPARAMS_IST_Pos                                4                                                         /*!< USB1 HCCPARAMS: IST Position        */
+#define USB1_HCCPARAMS_IST_Msk                                (0x0fUL << USB1_HCCPARAMS_IST_Pos)                        /*!< USB1 HCCPARAMS: IST Mask            */
+#define USB1_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB1 HCCPARAMS: EECP Position       */
+#define USB1_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos)                 /*!< USB1 HCCPARAMS: EECP Mask           */
+
+// -------------------------------------  USB1_DCIVERSION  ----------------------------------------
+#define USB1_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB1 DCIVERSION: DCIVERSION Position */
+#define USB1_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos)          /*!< USB1 DCIVERSION: DCIVERSION Mask    */
+
+// --------------------------------------  USB1_USBCMD_D  -----------------------------------------
+#define USB1_USBCMD_D_RS_Pos                                  0                                                         /*!< USB1 USBCMD_D: RS Position          */
+#define USB1_USBCMD_D_RS_Msk                                  (0x01UL << USB1_USBCMD_D_RS_Pos)                          /*!< USB1 USBCMD_D: RS Mask              */
+#define USB1_USBCMD_D_RST_Pos                                 1                                                         /*!< USB1 USBCMD_D: RST Position         */
+#define USB1_USBCMD_D_RST_Msk                                 (0x01UL << USB1_USBCMD_D_RST_Pos)                         /*!< USB1 USBCMD_D: RST Mask             */
+#define USB1_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB1 USBCMD_D: SUTW Position        */
+#define USB1_USBCMD_D_SUTW_Msk                                (0x01UL << USB1_USBCMD_D_SUTW_Pos)                        /*!< USB1 USBCMD_D: SUTW Mask            */
+#define USB1_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB1 USBCMD_D: ATDTW Position       */
+#define USB1_USBCMD_D_ATDTW_Msk                               (0x01UL << USB1_USBCMD_D_ATDTW_Pos)                       /*!< USB1 USBCMD_D: ATDTW Mask           */
+#define USB1_USBCMD_D_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_D: FS2 Position         */
+#define USB1_USBCMD_D_FS2_Msk                                 (0x01UL << USB1_USBCMD_D_FS2_Pos)                         /*!< USB1 USBCMD_D: FS2 Mask             */
+#define USB1_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_D: ITC Position         */
+#define USB1_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_D_ITC_Pos)                   /*!< USB1 USBCMD_D: ITC Mask             */
+
+// --------------------------------------  USB1_USBCMD_H  -----------------------------------------
+#define USB1_USBCMD_H_RS_Pos                                  0                                                         /*!< USB1 USBCMD_H: RS Position          */
+#define USB1_USBCMD_H_RS_Msk                                  (0x01UL << USB1_USBCMD_H_RS_Pos)                          /*!< USB1 USBCMD_H: RS Mask              */
+#define USB1_USBCMD_H_RST_Pos                                 1                                                         /*!< USB1 USBCMD_H: RST Position         */
+#define USB1_USBCMD_H_RST_Msk                                 (0x01UL << USB1_USBCMD_H_RST_Pos)                         /*!< USB1 USBCMD_H: RST Mask             */
+#define USB1_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB1 USBCMD_H: FS0 Position         */
+#define USB1_USBCMD_H_FS0_Msk                                 (0x01UL << USB1_USBCMD_H_FS0_Pos)                         /*!< USB1 USBCMD_H: FS0 Mask             */
+#define USB1_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB1 USBCMD_H: FS1 Position         */
+#define USB1_USBCMD_H_FS1_Msk                                 (0x01UL << USB1_USBCMD_H_FS1_Pos)                         /*!< USB1 USBCMD_H: FS1 Mask             */
+#define USB1_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB1 USBCMD_H: PSE Position         */
+#define USB1_USBCMD_H_PSE_Msk                                 (0x01UL << USB1_USBCMD_H_PSE_Pos)                         /*!< USB1 USBCMD_H: PSE Mask             */
+#define USB1_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB1 USBCMD_H: ASE Position         */
+#define USB1_USBCMD_H_ASE_Msk                                 (0x01UL << USB1_USBCMD_H_ASE_Pos)                         /*!< USB1 USBCMD_H: ASE Mask             */
+#define USB1_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB1 USBCMD_H: IAA Position         */
+#define USB1_USBCMD_H_IAA_Msk                                 (0x01UL << USB1_USBCMD_H_IAA_Pos)                         /*!< USB1 USBCMD_H: IAA Mask             */
+#define USB1_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB1 USBCMD_H: ASP1_0 Position      */
+#define USB1_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB1_USBCMD_H_ASP1_0_Pos)                      /*!< USB1 USBCMD_H: ASP1_0 Mask          */
+#define USB1_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB1 USBCMD_H: ASPE Position        */
+#define USB1_USBCMD_H_ASPE_Msk                                (0x01UL << USB1_USBCMD_H_ASPE_Pos)                        /*!< USB1 USBCMD_H: ASPE Mask            */
+#define USB1_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_H: FS2 Position         */
+#define USB1_USBCMD_H_FS2_Msk                                 (0x01UL << USB1_USBCMD_H_FS2_Pos)                         /*!< USB1 USBCMD_H: FS2 Mask             */
+#define USB1_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_H: ITC Position         */
+#define USB1_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_H_ITC_Pos)                   /*!< USB1 USBCMD_H: ITC Mask             */
+
+// --------------------------------------  USB1_USBSTS_D  -----------------------------------------
+#define USB1_USBSTS_D_UI_Pos                                  0                                                         /*!< USB1 USBSTS_D: UI Position          */
+#define USB1_USBSTS_D_UI_Msk                                  (0x01UL << USB1_USBSTS_D_UI_Pos)                          /*!< USB1 USBSTS_D: UI Mask              */
+#define USB1_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_D: UEI Position         */
+#define USB1_USBSTS_D_UEI_Msk                                 (0x01UL << USB1_USBSTS_D_UEI_Pos)                         /*!< USB1 USBSTS_D: UEI Mask             */
+#define USB1_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_D: PCI Position         */
+#define USB1_USBSTS_D_PCI_Msk                                 (0x01UL << USB1_USBSTS_D_PCI_Pos)                         /*!< USB1 USBSTS_D: PCI Mask             */
+#define USB1_USBSTS_D_URI_Pos                                 6                                                         /*!< USB1 USBSTS_D: URI Position         */
+#define USB1_USBSTS_D_URI_Msk                                 (0x01UL << USB1_USBSTS_D_URI_Pos)                         /*!< USB1 USBSTS_D: URI Mask             */
+#define USB1_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_D: SRI Position         */
+#define USB1_USBSTS_D_SRI_Msk                                 (0x01UL << USB1_USBSTS_D_SRI_Pos)                         /*!< USB1 USBSTS_D: SRI Mask             */
+#define USB1_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_D: SLI Position         */
+#define USB1_USBSTS_D_SLI_Msk                                 (0x01UL << USB1_USBSTS_D_SLI_Pos)                         /*!< USB1 USBSTS_D: SLI Mask             */
+#define USB1_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB1 USBSTS_D: NAKI Position        */
+#define USB1_USBSTS_D_NAKI_Msk                                (0x01UL << USB1_USBSTS_D_NAKI_Pos)                        /*!< USB1 USBSTS_D: NAKI Mask            */
+
+// --------------------------------------  USB1_USBSTS_H  -----------------------------------------
+#define USB1_USBSTS_H_UI_Pos                                  0                                                         /*!< USB1 USBSTS_H: UI Position          */
+#define USB1_USBSTS_H_UI_Msk                                  (0x01UL << USB1_USBSTS_H_UI_Pos)                          /*!< USB1 USBSTS_H: UI Mask              */
+#define USB1_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_H: UEI Position         */
+#define USB1_USBSTS_H_UEI_Msk                                 (0x01UL << USB1_USBSTS_H_UEI_Pos)                         /*!< USB1 USBSTS_H: UEI Mask             */
+#define USB1_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_H: PCI Position         */
+#define USB1_USBSTS_H_PCI_Msk                                 (0x01UL << USB1_USBSTS_H_PCI_Pos)                         /*!< USB1 USBSTS_H: PCI Mask             */
+#define USB1_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB1 USBSTS_H: FRI Position         */
+#define USB1_USBSTS_H_FRI_Msk                                 (0x01UL << USB1_USBSTS_H_FRI_Pos)                         /*!< USB1 USBSTS_H: FRI Mask             */
+#define USB1_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB1 USBSTS_H: AAI Position         */
+#define USB1_USBSTS_H_AAI_Msk                                 (0x01UL << USB1_USBSTS_H_AAI_Pos)                         /*!< USB1 USBSTS_H: AAI Mask             */
+#define USB1_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_H: SRI Position         */
+#define USB1_USBSTS_H_SRI_Msk                                 (0x01UL << USB1_USBSTS_H_SRI_Pos)                         /*!< USB1 USBSTS_H: SRI Mask             */
+#define USB1_USBSTS_H_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_H: SLI Position         */
+#define USB1_USBSTS_H_SLI_Msk                                 (0x01UL << USB1_USBSTS_H_SLI_Pos)                         /*!< USB1 USBSTS_H: SLI Mask             */
+#define USB1_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB1 USBSTS_H: HCH Position         */
+#define USB1_USBSTS_H_HCH_Msk                                 (0x01UL << USB1_USBSTS_H_HCH_Pos)                         /*!< USB1 USBSTS_H: HCH Mask             */
+#define USB1_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB1 USBSTS_H: RCL Position         */
+#define USB1_USBSTS_H_RCL_Msk                                 (0x01UL << USB1_USBSTS_H_RCL_Pos)                         /*!< USB1 USBSTS_H: RCL Mask             */
+#define USB1_USBSTS_H_PS_Pos                                  14                                                        /*!< USB1 USBSTS_H: PS Position          */
+#define USB1_USBSTS_H_PS_Msk                                  (0x01UL << USB1_USBSTS_H_PS_Pos)                          /*!< USB1 USBSTS_H: PS Mask              */
+#define USB1_USBSTS_H_AS_Pos                                  15                                                        /*!< USB1 USBSTS_H: AS Position          */
+#define USB1_USBSTS_H_AS_Msk                                  (0x01UL << USB1_USBSTS_H_AS_Pos)                          /*!< USB1 USBSTS_H: AS Mask              */
+#define USB1_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB1 USBSTS_H: UAI Position         */
+#define USB1_USBSTS_H_UAI_Msk                                 (0x01UL << USB1_USBSTS_H_UAI_Pos)                         /*!< USB1 USBSTS_H: UAI Mask             */
+#define USB1_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB1 USBSTS_H: UPI Position         */
+#define USB1_USBSTS_H_UPI_Msk                                 (0x01UL << USB1_USBSTS_H_UPI_Pos)                         /*!< USB1 USBSTS_H: UPI Mask             */
+
+// -------------------------------------  USB1_USBINTR_D  -----------------------------------------
+#define USB1_USBINTR_D_UE_Pos                                 0                                                         /*!< USB1 USBINTR_D: UE Position         */
+#define USB1_USBINTR_D_UE_Msk                                 (0x01UL << USB1_USBINTR_D_UE_Pos)                         /*!< USB1 USBINTR_D: UE Mask             */
+#define USB1_USBINTR_D_UEE_Pos                                1                                                         /*!< USB1 USBINTR_D: UEE Position        */
+#define USB1_USBINTR_D_UEE_Msk                                (0x01UL << USB1_USBINTR_D_UEE_Pos)                        /*!< USB1 USBINTR_D: UEE Mask            */
+#define USB1_USBINTR_D_PCE_Pos                                2                                                         /*!< USB1 USBINTR_D: PCE Position        */
+#define USB1_USBINTR_D_PCE_Msk                                (0x01UL << USB1_USBINTR_D_PCE_Pos)                        /*!< USB1 USBINTR_D: PCE Mask            */
+#define USB1_USBINTR_D_URE_Pos                                6                                                         /*!< USB1 USBINTR_D: URE Position        */
+#define USB1_USBINTR_D_URE_Msk                                (0x01UL << USB1_USBINTR_D_URE_Pos)                        /*!< USB1 USBINTR_D: URE Mask            */
+#define USB1_USBINTR_D_SRE_Pos                                7                                                         /*!< USB1 USBINTR_D: SRE Position        */
+#define USB1_USBINTR_D_SRE_Msk                                (0x01UL << USB1_USBINTR_D_SRE_Pos)                        /*!< USB1 USBINTR_D: SRE Mask            */
+#define USB1_USBINTR_D_SLE_Pos                                8                                                         /*!< USB1 USBINTR_D: SLE Position        */
+#define USB1_USBINTR_D_SLE_Msk                                (0x01UL << USB1_USBINTR_D_SLE_Pos)                        /*!< USB1 USBINTR_D: SLE Mask            */
+#define USB1_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB1 USBINTR_D: NAKE Position       */
+#define USB1_USBINTR_D_NAKE_Msk                               (0x01UL << USB1_USBINTR_D_NAKE_Pos)                       /*!< USB1 USBINTR_D: NAKE Mask           */
+#define USB1_USBINTR_D_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_D: UAIE Position       */
+#define USB1_USBINTR_D_UAIE_Msk                               (0x01UL << USB1_USBINTR_D_UAIE_Pos)                       /*!< USB1 USBINTR_D: UAIE Mask           */
+#define USB1_USBINTR_D_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_D: UPIA Position       */
+#define USB1_USBINTR_D_UPIA_Msk                               (0x01UL << USB1_USBINTR_D_UPIA_Pos)                       /*!< USB1 USBINTR_D: UPIA Mask           */
+
+// -------------------------------------  USB1_USBINTR_H  -----------------------------------------
+#define USB1_USBINTR_H_UE_Pos                                 0                                                         /*!< USB1 USBINTR_H: UE Position         */
+#define USB1_USBINTR_H_UE_Msk                                 (0x01UL << USB1_USBINTR_H_UE_Pos)                         /*!< USB1 USBINTR_H: UE Mask             */
+#define USB1_USBINTR_H_UEE_Pos                                1                                                         /*!< USB1 USBINTR_H: UEE Position        */
+#define USB1_USBINTR_H_UEE_Msk                                (0x01UL << USB1_USBINTR_H_UEE_Pos)                        /*!< USB1 USBINTR_H: UEE Mask            */
+#define USB1_USBINTR_H_PCE_Pos                                2                                                         /*!< USB1 USBINTR_H: PCE Position        */
+#define USB1_USBINTR_H_PCE_Msk                                (0x01UL << USB1_USBINTR_H_PCE_Pos)                        /*!< USB1 USBINTR_H: PCE Mask            */
+#define USB1_USBINTR_H_FRE_Pos                                3                                                         /*!< USB1 USBINTR_H: FRE Position        */
+#define USB1_USBINTR_H_FRE_Msk                                (0x01UL << USB1_USBINTR_H_FRE_Pos)                        /*!< USB1 USBINTR_H: FRE Mask            */
+#define USB1_USBINTR_H_AAE_Pos                                5                                                         /*!< USB1 USBINTR_H: AAE Position        */
+#define USB1_USBINTR_H_AAE_Msk                                (0x01UL << USB1_USBINTR_H_AAE_Pos)                        /*!< USB1 USBINTR_H: AAE Mask            */
+#define USB1_USBINTR_H_SRE_Pos                                7                                                         /*!< USB1 USBINTR_H: SRE Position        */
+#define USB1_USBINTR_H_SRE_Msk                                (0x01UL << USB1_USBINTR_H_SRE_Pos)                        /*!< USB1 USBINTR_H: SRE Mask            */
+#define USB1_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_H: UAIE Position       */
+#define USB1_USBINTR_H_UAIE_Msk                               (0x01UL << USB1_USBINTR_H_UAIE_Pos)                       /*!< USB1 USBINTR_H: UAIE Mask           */
+#define USB1_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_H: UPIA Position       */
+#define USB1_USBINTR_H_UPIA_Msk                               (0x01UL << USB1_USBINTR_H_UPIA_Pos)                       /*!< USB1 USBINTR_H: UPIA Mask           */
+
+// -------------------------------------  USB1_FRINDEX_D  -----------------------------------------
+#define USB1_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */
+#define USB1_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask     */
+#define USB1_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */
+#define USB1_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask    */
+
+// -------------------------------------  USB1_FRINDEX_H  -----------------------------------------
+#define USB1_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */
+#define USB1_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask     */
+#define USB1_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */
+#define USB1_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask    */
+
+// -------------------------------------  USB1_DEVICEADDR  ----------------------------------------
+#define USB1_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB1 DEVICEADDR: USBADRA Position   */
+#define USB1_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB1_DEVICEADDR_USBADRA_Pos)                   /*!< USB1 DEVICEADDR: USBADRA Mask       */
+#define USB1_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB1 DEVICEADDR: USBADR Position    */
+#define USB1_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB1_DEVICEADDR_USBADR_Pos)                    /*!< USB1 DEVICEADDR: USBADR Mask        */
+
+// ----------------------------------  USB1_PERIODICLISTBASE  -------------------------------------
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ----------------------------------  USB1_ENDPOINTLISTADDR  -------------------------------------
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// -----------------------------------  USB1_ASYNCLISTADDR  ---------------------------------------
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// ---------------------------------------  USB1_TTCTRL  ------------------------------------------
+#define USB1_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB1 TTCTRL: TTHA Position          */
+#define USB1_TTCTRL_TTHA_Msk                                  (0x7fUL << USB1_TTCTRL_TTHA_Pos)                          /*!< USB1 TTCTRL: TTHA Mask              */
+
+// -------------------------------------  USB1_BURSTSIZE  -----------------------------------------
+#define USB1_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB1 BURSTSIZE: RXPBURST Position   */
+#define USB1_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos)             /*!< USB1 BURSTSIZE: RXPBURST Mask       */
+#define USB1_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB1 BURSTSIZE: TXPBURST Position   */
+#define USB1_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos)             /*!< USB1 BURSTSIZE: TXPBURST Mask       */
+
+// ------------------------------------  USB1_TXFILLTUNING  ---------------------------------------
+#define USB1_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB1 TXFILLTUNING: TXSCHOH Position */
+#define USB1_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB1 TXFILLTUNING: TXSCHOH Mask     */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// ------------------------------------  USB1_ULPIVIEWPORT  ---------------------------------------
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos                       0                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask   */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos                       8                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask   */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Pos                        16                                                        /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Msk                        (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos)          /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask    */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Pos                        24                                                        /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Msk                        (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos)                /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask    */
+#define USB1_ULPIVIEWPORT_ULPISS_Pos                          27                                                        /*!< USB1 ULPIVIEWPORT: ULPISS Position  */
+#define USB1_ULPIVIEWPORT_ULPISS_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPISS Mask      */
+#define USB1_ULPIVIEWPORT_ULPIRW_Pos                          29                                                        /*!< USB1 ULPIVIEWPORT: ULPIRW Position  */
+#define USB1_ULPIVIEWPORT_ULPIRW_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIRW Mask      */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Pos                         30                                                        /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Msk                         (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos)                 /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask     */
+#define USB1_ULPIVIEWPORT_ULPIWU_Pos                          31                                                        /*!< USB1 ULPIVIEWPORT: ULPIWU Position  */
+#define USB1_ULPIVIEWPORT_ULPIWU_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIWU Mask      */
+
+// -------------------------------------  USB1_BINTERVAL  -----------------------------------------
+#define USB1_BINTERVAL_BINT_Pos                               0                                                         /*!< USB1 BINTERVAL: BINT Position       */
+#define USB1_BINTERVAL_BINT_Msk                               (0x0fUL << USB1_BINTERVAL_BINT_Pos)                       /*!< USB1 BINTERVAL: BINT Mask           */
+
+// --------------------------------------  USB1_ENDPTNAK  -----------------------------------------
+#define USB1_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB1 ENDPTNAK: EPRN0 Position       */
+#define USB1_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN0_Pos)                       /*!< USB1 ENDPTNAK: EPRN0 Mask           */
+#define USB1_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB1 ENDPTNAK: EPRN1 Position       */
+#define USB1_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN1_Pos)                       /*!< USB1 ENDPTNAK: EPRN1 Mask           */
+#define USB1_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB1 ENDPTNAK: EPRN2 Position       */
+#define USB1_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN2_Pos)                       /*!< USB1 ENDPTNAK: EPRN2 Mask           */
+#define USB1_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB1 ENDPTNAK: EPRN3 Position       */
+#define USB1_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN3_Pos)                       /*!< USB1 ENDPTNAK: EPRN3 Mask           */
+#define USB1_ENDPTNAK_EPTN16_Pos                              16                                                        /*!< USB1 ENDPTNAK: EPTN16 Position      */
+#define USB1_ENDPTNAK_EPTN16_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN16_Pos)                      /*!< USB1 ENDPTNAK: EPTN16 Mask          */
+#define USB1_ENDPTNAK_EPTN17_Pos                              17                                                        /*!< USB1 ENDPTNAK: EPTN17 Position      */
+#define USB1_ENDPTNAK_EPTN17_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN17_Pos)                      /*!< USB1 ENDPTNAK: EPTN17 Mask          */
+#define USB1_ENDPTNAK_EPTN18_Pos                              18                                                        /*!< USB1 ENDPTNAK: EPTN18 Position      */
+#define USB1_ENDPTNAK_EPTN18_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN18_Pos)                      /*!< USB1 ENDPTNAK: EPTN18 Mask          */
+#define USB1_ENDPTNAK_EPTN19_Pos                              19                                                        /*!< USB1 ENDPTNAK: EPTN19 Position      */
+#define USB1_ENDPTNAK_EPTN19_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN19_Pos)                      /*!< USB1 ENDPTNAK: EPTN19 Mask          */
+
+// -------------------------------------  USB1_ENDPTNAKEN  ----------------------------------------
+#define USB1_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB1 ENDPTNAKEN: EPRNE0 Position    */
+#define USB1_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE0 Mask        */
+#define USB1_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB1 ENDPTNAKEN: EPRNE1 Position    */
+#define USB1_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE1 Mask        */
+#define USB1_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB1 ENDPTNAKEN: EPRNE2 Position    */
+#define USB1_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE2 Mask        */
+#define USB1_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB1 ENDPTNAKEN: EPRNE3 Position    */
+#define USB1_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE3 Mask        */
+#define USB1_ENDPTNAKEN_EPTNE16_Pos                           16                                                        /*!< USB1 ENDPTNAKEN: EPTNE16 Position   */
+#define USB1_ENDPTNAKEN_EPTNE16_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE16 Mask       */
+#define USB1_ENDPTNAKEN_EPTNE17_Pos                           17                                                        /*!< USB1 ENDPTNAKEN: EPTNE17 Position   */
+#define USB1_ENDPTNAKEN_EPTNE17_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE17 Mask       */
+#define USB1_ENDPTNAKEN_EPTNE18_Pos                           18                                                        /*!< USB1 ENDPTNAKEN: EPTNE18 Position   */
+#define USB1_ENDPTNAKEN_EPTNE18_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE18 Mask       */
+#define USB1_ENDPTNAKEN_EPTNE19_Pos                           19                                                        /*!< USB1 ENDPTNAKEN: EPTNE19 Position   */
+#define USB1_ENDPTNAKEN_EPTNE19_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE19 Mask       */
+
+// -------------------------------------  USB1_PORTSC1_D  -----------------------------------------
+#define USB1_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_D: CCS Position        */
+#define USB1_PORTSC1_D_CCS_Msk                                (0x01UL << USB1_PORTSC1_D_CCS_Pos)                        /*!< USB1 PORTSC1_D: CCS Mask            */
+#define USB1_PORTSC1_D_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_D: CSC Position        */
+#define USB1_PORTSC1_D_CSC_Msk                                (0x01UL << USB1_PORTSC1_D_CSC_Pos)                        /*!< USB1 PORTSC1_D: CSC Mask            */
+#define USB1_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_D: PE Position         */
+#define USB1_PORTSC1_D_PE_Msk                                 (0x01UL << USB1_PORTSC1_D_PE_Pos)                         /*!< USB1 PORTSC1_D: PE Mask             */
+#define USB1_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_D: PEC Position        */
+#define USB1_PORTSC1_D_PEC_Msk                                (0x01UL << USB1_PORTSC1_D_PEC_Pos)                        /*!< USB1 PORTSC1_D: PEC Mask            */
+#define USB1_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_D: FPR Position        */
+#define USB1_PORTSC1_D_FPR_Msk                                (0x01UL << USB1_PORTSC1_D_FPR_Pos)                        /*!< USB1 PORTSC1_D: FPR Mask            */
+#define USB1_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_D: SUSP Position       */
+#define USB1_PORTSC1_D_SUSP_Msk                               (0x01UL << USB1_PORTSC1_D_SUSP_Pos)                       /*!< USB1 PORTSC1_D: SUSP Mask           */
+#define USB1_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_D: PR Position         */
+#define USB1_PORTSC1_D_PR_Msk                                 (0x01UL << USB1_PORTSC1_D_PR_Pos)                         /*!< USB1 PORTSC1_D: PR Mask             */
+#define USB1_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_D: HSP Position        */
+#define USB1_PORTSC1_D_HSP_Msk                                (0x01UL << USB1_PORTSC1_D_HSP_Pos)                        /*!< USB1 PORTSC1_D: HSP Mask            */
+#define USB1_PORTSC1_D_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_D: LS Position         */
+#define USB1_PORTSC1_D_LS_Msk                                 (0x03UL << USB1_PORTSC1_D_LS_Pos)                         /*!< USB1 PORTSC1_D: LS Mask             */
+#define USB1_PORTSC1_D_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_D: PP Position         */
+#define USB1_PORTSC1_D_PP_Msk                                 (0x01UL << USB1_PORTSC1_D_PP_Pos)                         /*!< USB1 PORTSC1_D: PP Mask             */
+#define USB1_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_D: PIC1_0 Position     */
+#define USB1_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos)                     /*!< USB1 PORTSC1_D: PIC1_0 Mask         */
+#define USB1_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_D: PTC3_0 Position     */
+#define USB1_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos)                     /*!< USB1 PORTSC1_D: PTC3_0 Mask         */
+#define USB1_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_D: PHCD Position       */
+#define USB1_PORTSC1_D_PHCD_Msk                               (0x01UL << USB1_PORTSC1_D_PHCD_Pos)                       /*!< USB1 PORTSC1_D: PHCD Mask           */
+#define USB1_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_D: PFSC Position       */
+#define USB1_PORTSC1_D_PFSC_Msk                               (0x01UL << USB1_PORTSC1_D_PFSC_Pos)                       /*!< USB1 PORTSC1_D: PFSC Mask           */
+#define USB1_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_D: PSPD Position       */
+#define USB1_PORTSC1_D_PSPD_Msk                               (0x03UL << USB1_PORTSC1_D_PSPD_Pos)                       /*!< USB1 PORTSC1_D: PSPD Mask           */
+#define USB1_PORTSC1_D_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_D: PTS Position        */
+#define USB1_PORTSC1_D_PTS_Msk                                (0x03UL << USB1_PORTSC1_D_PTS_Pos)                        /*!< USB1 PORTSC1_D: PTS Mask            */
+
+// -------------------------------------  USB1_PORTSC1_H  -----------------------------------------
+#define USB1_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_H: CCS Position        */
+#define USB1_PORTSC1_H_CCS_Msk                                (0x01UL << USB1_PORTSC1_H_CCS_Pos)                        /*!< USB1 PORTSC1_H: CCS Mask            */
+#define USB1_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_H: CSC Position        */
+#define USB1_PORTSC1_H_CSC_Msk                                (0x01UL << USB1_PORTSC1_H_CSC_Pos)                        /*!< USB1 PORTSC1_H: CSC Mask            */
+#define USB1_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_H: PE Position         */
+#define USB1_PORTSC1_H_PE_Msk                                 (0x01UL << USB1_PORTSC1_H_PE_Pos)                         /*!< USB1 PORTSC1_H: PE Mask             */
+#define USB1_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_H: PEC Position        */
+#define USB1_PORTSC1_H_PEC_Msk                                (0x01UL << USB1_PORTSC1_H_PEC_Pos)                        /*!< USB1 PORTSC1_H: PEC Mask            */
+#define USB1_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB1 PORTSC1_H: OCA Position        */
+#define USB1_PORTSC1_H_OCA_Msk                                (0x01UL << USB1_PORTSC1_H_OCA_Pos)                        /*!< USB1 PORTSC1_H: OCA Mask            */
+#define USB1_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB1 PORTSC1_H: OCC Position        */
+#define USB1_PORTSC1_H_OCC_Msk                                (0x01UL << USB1_PORTSC1_H_OCC_Pos)                        /*!< USB1 PORTSC1_H: OCC Mask            */
+#define USB1_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_H: FPR Position        */
+#define USB1_PORTSC1_H_FPR_Msk                                (0x01UL << USB1_PORTSC1_H_FPR_Pos)                        /*!< USB1 PORTSC1_H: FPR Mask            */
+#define USB1_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_H: SUSP Position       */
+#define USB1_PORTSC1_H_SUSP_Msk                               (0x01UL << USB1_PORTSC1_H_SUSP_Pos)                       /*!< USB1 PORTSC1_H: SUSP Mask           */
+#define USB1_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_H: PR Position         */
+#define USB1_PORTSC1_H_PR_Msk                                 (0x01UL << USB1_PORTSC1_H_PR_Pos)                         /*!< USB1 PORTSC1_H: PR Mask             */
+#define USB1_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_H: HSP Position        */
+#define USB1_PORTSC1_H_HSP_Msk                                (0x01UL << USB1_PORTSC1_H_HSP_Pos)                        /*!< USB1 PORTSC1_H: HSP Mask            */
+#define USB1_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_H: LS Position         */
+#define USB1_PORTSC1_H_LS_Msk                                 (0x03UL << USB1_PORTSC1_H_LS_Pos)                         /*!< USB1 PORTSC1_H: LS Mask             */
+#define USB1_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_H: PP Position         */
+#define USB1_PORTSC1_H_PP_Msk                                 (0x01UL << USB1_PORTSC1_H_PP_Pos)                         /*!< USB1 PORTSC1_H: PP Mask             */
+#define USB1_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_H: PIC1_0 Position     */
+#define USB1_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos)                     /*!< USB1 PORTSC1_H: PIC1_0 Mask         */
+#define USB1_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_H: PTC3_0 Position     */
+#define USB1_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos)                     /*!< USB1 PORTSC1_H: PTC3_0 Mask         */
+#define USB1_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB1 PORTSC1_H: WKCN Position       */
+#define USB1_PORTSC1_H_WKCN_Msk                               (0x01UL << USB1_PORTSC1_H_WKCN_Pos)                       /*!< USB1 PORTSC1_H: WKCN Mask           */
+#define USB1_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB1 PORTSC1_H: WKDC Position       */
+#define USB1_PORTSC1_H_WKDC_Msk                               (0x01UL << USB1_PORTSC1_H_WKDC_Pos)                       /*!< USB1 PORTSC1_H: WKDC Mask           */
+#define USB1_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB1 PORTSC1_H: WKOC Position       */
+#define USB1_PORTSC1_H_WKOC_Msk                               (0x01UL << USB1_PORTSC1_H_WKOC_Pos)                       /*!< USB1 PORTSC1_H: WKOC Mask           */
+#define USB1_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_H: PHCD Position       */
+#define USB1_PORTSC1_H_PHCD_Msk                               (0x01UL << USB1_PORTSC1_H_PHCD_Pos)                       /*!< USB1 PORTSC1_H: PHCD Mask           */
+#define USB1_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_H: PFSC Position       */
+#define USB1_PORTSC1_H_PFSC_Msk                               (0x01UL << USB1_PORTSC1_H_PFSC_Pos)                       /*!< USB1 PORTSC1_H: PFSC Mask           */
+#define USB1_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_H: PSPD Position       */
+#define USB1_PORTSC1_H_PSPD_Msk                               (0x03UL << USB1_PORTSC1_H_PSPD_Pos)                       /*!< USB1 PORTSC1_H: PSPD Mask           */
+#define USB1_PORTSC1_H_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_H: PTS Position        */
+#define USB1_PORTSC1_H_PTS_Msk                                (0x03UL << USB1_PORTSC1_H_PTS_Pos)                        /*!< USB1 PORTSC1_H: PTS Mask            */
+
+// -------------------------------------  USB1_USBMODE_D  -----------------------------------------
+#define USB1_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_D: CM1_0 Position      */
+#define USB1_USBMODE_D_CM1_0_Msk                              (0x03UL << USB1_USBMODE_D_CM1_0_Pos)                      /*!< USB1 USBMODE_D: CM1_0 Mask          */
+#define USB1_USBMODE_D_ES_Pos                                 2                                                         /*!< USB1 USBMODE_D: ES Position         */
+#define USB1_USBMODE_D_ES_Msk                                 (0x01UL << USB1_USBMODE_D_ES_Pos)                         /*!< USB1 USBMODE_D: ES Mask             */
+#define USB1_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB1 USBMODE_D: SLOM Position       */
+#define USB1_USBMODE_D_SLOM_Msk                               (0x01UL << USB1_USBMODE_D_SLOM_Pos)                       /*!< USB1 USBMODE_D: SLOM Mask           */
+#define USB1_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_D: SDIS Position       */
+#define USB1_USBMODE_D_SDIS_Msk                               (0x01UL << USB1_USBMODE_D_SDIS_Pos)                       /*!< USB1 USBMODE_D: SDIS Mask           */
+
+// -------------------------------------  USB1_USBMODE_H  -----------------------------------------
+#define USB1_USBMODE_H_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_H: CM1_0 Position      */
+#define USB1_USBMODE_H_CM1_0_Msk                              (0x03UL << USB1_USBMODE_H_CM1_0_Pos)                      /*!< USB1 USBMODE_H: CM1_0 Mask          */
+#define USB1_USBMODE_H_ES_Pos                                 2                                                         /*!< USB1 USBMODE_H: ES Position         */
+#define USB1_USBMODE_H_ES_Msk                                 (0x01UL << USB1_USBMODE_H_ES_Pos)                         /*!< USB1 USBMODE_H: ES Mask             */
+#define USB1_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_H: SDIS Position       */
+#define USB1_USBMODE_H_SDIS_Msk                               (0x01UL << USB1_USBMODE_H_SDIS_Pos)                       /*!< USB1 USBMODE_H: SDIS Mask           */
+#define USB1_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB1 USBMODE_H: VBPS Position       */
+#define USB1_USBMODE_H_VBPS_Msk                               (0x01UL << USB1_USBMODE_H_VBPS_Pos)                       /*!< USB1 USBMODE_H: VBPS Mask           */
+
+// -----------------------------------  USB1_ENDPTSETUPSTAT  --------------------------------------
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+
+// -------------------------------------  USB1_ENDPTPRIME  ----------------------------------------
+#define USB1_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB1 ENDPTPRIME: PERB0 Position     */
+#define USB1_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB0_Pos)                     /*!< USB1 ENDPTPRIME: PERB0 Mask         */
+#define USB1_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB1 ENDPTPRIME: PERB1 Position     */
+#define USB1_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB1_Pos)                     /*!< USB1 ENDPTPRIME: PERB1 Mask         */
+#define USB1_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB1 ENDPTPRIME: PERB2 Position     */
+#define USB1_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB2_Pos)                     /*!< USB1 ENDPTPRIME: PERB2 Mask         */
+#define USB1_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB1 ENDPTPRIME: PERB3 Position     */
+#define USB1_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB3_Pos)                     /*!< USB1 ENDPTPRIME: PERB3 Mask         */
+#define USB1_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB1 ENDPTPRIME: PETB0 Position     */
+#define USB1_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB0_Pos)                     /*!< USB1 ENDPTPRIME: PETB0 Mask         */
+#define USB1_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB1 ENDPTPRIME: PETB1 Position     */
+#define USB1_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB1_Pos)                     /*!< USB1 ENDPTPRIME: PETB1 Mask         */
+#define USB1_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB1 ENDPTPRIME: PETB2 Position     */
+#define USB1_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB2_Pos)                     /*!< USB1 ENDPTPRIME: PETB2 Mask         */
+#define USB1_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB1 ENDPTPRIME: PETB3 Position     */
+#define USB1_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB3_Pos)                     /*!< USB1 ENDPTPRIME: PETB3 Mask         */
+
+// -------------------------------------  USB1_ENDPTFLUSH  ----------------------------------------
+#define USB1_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB1 ENDPTFLUSH: FERB0 Position     */
+#define USB1_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos)                     /*!< USB1 ENDPTFLUSH: FERB0 Mask         */
+#define USB1_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB1 ENDPTFLUSH: FERB1 Position     */
+#define USB1_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos)                     /*!< USB1 ENDPTFLUSH: FERB1 Mask         */
+#define USB1_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB1 ENDPTFLUSH: FERB2 Position     */
+#define USB1_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos)                     /*!< USB1 ENDPTFLUSH: FERB2 Mask         */
+#define USB1_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB1 ENDPTFLUSH: FERB3 Position     */
+#define USB1_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos)                     /*!< USB1 ENDPTFLUSH: FERB3 Mask         */
+#define USB1_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB1 ENDPTFLUSH: FETB0 Position     */
+#define USB1_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos)                     /*!< USB1 ENDPTFLUSH: FETB0 Mask         */
+#define USB1_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB1 ENDPTFLUSH: FETB1 Position     */
+#define USB1_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos)                     /*!< USB1 ENDPTFLUSH: FETB1 Mask         */
+#define USB1_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB1 ENDPTFLUSH: FETB2 Position     */
+#define USB1_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos)                     /*!< USB1 ENDPTFLUSH: FETB2 Mask         */
+#define USB1_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB1 ENDPTFLUSH: FETB3 Position     */
+#define USB1_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos)                     /*!< USB1 ENDPTFLUSH: FETB3 Mask         */
+
+// -------------------------------------  USB1_ENDPTSTAT  -----------------------------------------
+#define USB1_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB1 ENDPTSTAT: ERBR0 Position      */
+#define USB1_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos)                      /*!< USB1 ENDPTSTAT: ERBR0 Mask          */
+#define USB1_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB1 ENDPTSTAT: ERBR1 Position      */
+#define USB1_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos)                      /*!< USB1 ENDPTSTAT: ERBR1 Mask          */
+#define USB1_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB1 ENDPTSTAT: ERBR2 Position      */
+#define USB1_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos)                      /*!< USB1 ENDPTSTAT: ERBR2 Mask          */
+#define USB1_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB1 ENDPTSTAT: ERBR3 Position      */
+#define USB1_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos)                      /*!< USB1 ENDPTSTAT: ERBR3 Mask          */
+#define USB1_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB1 ENDPTSTAT: ETBR0 Position      */
+#define USB1_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos)                      /*!< USB1 ENDPTSTAT: ETBR0 Mask          */
+#define USB1_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB1 ENDPTSTAT: ETBR1 Position      */
+#define USB1_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos)                      /*!< USB1 ENDPTSTAT: ETBR1 Mask          */
+#define USB1_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB1 ENDPTSTAT: ETBR2 Position      */
+#define USB1_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos)                      /*!< USB1 ENDPTSTAT: ETBR2 Mask          */
+#define USB1_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB1 ENDPTSTAT: ETBR3 Position      */
+#define USB1_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos)                      /*!< USB1 ENDPTSTAT: ETBR3 Mask          */
+
+// -----------------------------------  USB1_ENDPTCOMPLETE  ---------------------------------------
+#define USB1_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB1 ENDPTCOMPLETE: ERCE0 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask      */
+#define USB1_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB1 ENDPTCOMPLETE: ERCE1 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask      */
+#define USB1_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB1 ENDPTCOMPLETE: ERCE2 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask      */
+#define USB1_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB1 ENDPTCOMPLETE: ERCE3 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB1 ENDPTCOMPLETE: ETCE0 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB1 ENDPTCOMPLETE: ETCE1 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB1 ENDPTCOMPLETE: ETCE2 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB1 ENDPTCOMPLETE: ETCE3 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask      */
+
+// -------------------------------------  USB1_ENDPTCTRL0  ----------------------------------------
+#define USB1_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL0: RXS Position       */
+#define USB1_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXS_Pos)                       /*!< USB1 ENDPTCTRL0: RXS Mask           */
+#define USB1_ENDPTCTRL0_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL0: RXT Position       */
+#define USB1_ENDPTCTRL0_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_RXT_Pos)                       /*!< USB1 ENDPTCTRL0: RXT Mask           */
+#define USB1_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL0: RXE Position       */
+#define USB1_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXE_Pos)                       /*!< USB1 ENDPTCTRL0: RXE Mask           */
+#define USB1_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL0: TXS Position       */
+#define USB1_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXS_Pos)                       /*!< USB1 ENDPTCTRL0: TXS Mask           */
+#define USB1_ENDPTCTRL0_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL0: TXT Position       */
+#define USB1_ENDPTCTRL0_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_TXT_Pos)                       /*!< USB1 ENDPTCTRL0: TXT Mask           */
+#define USB1_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL0: TXE Position       */
+#define USB1_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXE_Pos)                       /*!< USB1 ENDPTCTRL0: TXE Mask           */
+
+// -------------------------------------  USB1_ENDPTCTRL1  ----------------------------------------
+#define USB1_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL1: RXS Position       */
+#define USB1_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXS_Pos)                       /*!< USB1 ENDPTCTRL1: RXS Mask           */
+#define USB1_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL1: RXT Position       */
+#define USB1_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_RXT_Pos)                       /*!< USB1 ENDPTCTRL1: RXT Mask           */
+#define USB1_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL1: RXI Position       */
+#define USB1_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXI_Pos)                       /*!< USB1 ENDPTCTRL1: RXI Mask           */
+#define USB1_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL1: RXR Position       */
+#define USB1_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXR_Pos)                       /*!< USB1 ENDPTCTRL1: RXR Mask           */
+#define USB1_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL1: RXE Position       */
+#define USB1_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXE_Pos)                       /*!< USB1 ENDPTCTRL1: RXE Mask           */
+#define USB1_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL1: TXS Position       */
+#define USB1_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXS_Pos)                       /*!< USB1 ENDPTCTRL1: TXS Mask           */
+#define USB1_ENDPTCTRL1_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL1: TXT Position       */
+#define USB1_ENDPTCTRL1_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_TXT_Pos)                       /*!< USB1 ENDPTCTRL1: TXT Mask           */
+#define USB1_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL1: TXI Position       */
+#define USB1_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXI_Pos)                       /*!< USB1 ENDPTCTRL1: TXI Mask           */
+#define USB1_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL1: TXR Position       */
+#define USB1_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXR_Pos)                       /*!< USB1 ENDPTCTRL1: TXR Mask           */
+#define USB1_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL1: TXE Position       */
+#define USB1_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXE_Pos)                       /*!< USB1 ENDPTCTRL1: TXE Mask           */
+
+// -------------------------------------  USB1_ENDPTCTRL2  ----------------------------------------
+#define USB1_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL2: RXS Position       */
+#define USB1_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXS_Pos)                       /*!< USB1 ENDPTCTRL2: RXS Mask           */
+#define USB1_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL2: RXT Position       */
+#define USB1_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_RXT_Pos)                       /*!< USB1 ENDPTCTRL2: RXT Mask           */
+#define USB1_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL2: RXI Position       */
+#define USB1_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXI_Pos)                       /*!< USB1 ENDPTCTRL2: RXI Mask           */
+#define USB1_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL2: RXR Position       */
+#define USB1_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXR_Pos)                       /*!< USB1 ENDPTCTRL2: RXR Mask           */
+#define USB1_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL2: RXE Position       */
+#define USB1_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXE_Pos)                       /*!< USB1 ENDPTCTRL2: RXE Mask           */
+#define USB1_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL2: TXS Position       */
+#define USB1_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXS_Pos)                       /*!< USB1 ENDPTCTRL2: TXS Mask           */
+#define USB1_ENDPTCTRL2_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL2: TXT Position       */
+#define USB1_ENDPTCTRL2_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_TXT_Pos)                       /*!< USB1 ENDPTCTRL2: TXT Mask           */
+#define USB1_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL2: TXI Position       */
+#define USB1_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXI_Pos)                       /*!< USB1 ENDPTCTRL2: TXI Mask           */
+#define USB1_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL2: TXR Position       */
+#define USB1_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXR_Pos)                       /*!< USB1 ENDPTCTRL2: TXR Mask           */
+#define USB1_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL2: TXE Position       */
+#define USB1_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXE_Pos)                       /*!< USB1 ENDPTCTRL2: TXE Mask           */
+
+// -------------------------------------  USB1_ENDPTCTRL3  ----------------------------------------
+#define USB1_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL3: RXS Position       */
+#define USB1_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXS_Pos)                       /*!< USB1 ENDPTCTRL3: RXS Mask           */
+#define USB1_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL3: RXT Position       */
+#define USB1_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_RXT_Pos)                       /*!< USB1 ENDPTCTRL3: RXT Mask           */
+#define USB1_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL3: RXI Position       */
+#define USB1_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXI_Pos)                       /*!< USB1 ENDPTCTRL3: RXI Mask           */
+#define USB1_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL3: RXR Position       */
+#define USB1_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXR_Pos)                       /*!< USB1 ENDPTCTRL3: RXR Mask           */
+#define USB1_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL3: RXE Position       */
+#define USB1_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXE_Pos)                       /*!< USB1 ENDPTCTRL3: RXE Mask           */
+#define USB1_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL3: TXS Position       */
+#define USB1_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXS_Pos)                       /*!< USB1 ENDPTCTRL3: TXS Mask           */
+#define USB1_ENDPTCTRL3_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL3: TXT Position       */
+#define USB1_ENDPTCTRL3_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_TXT_Pos)                       /*!< USB1 ENDPTCTRL3: TXT Mask           */
+#define USB1_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL3: TXI Position       */
+#define USB1_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXI_Pos)                       /*!< USB1 ENDPTCTRL3: TXI Mask           */
+#define USB1_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL3: TXR Position       */
+#define USB1_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXR_Pos)                       /*!< USB1 ENDPTCTRL3: TXR Mask           */
+#define USB1_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL3: TXE Position       */
+#define USB1_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXE_Pos)                       /*!< USB1 ENDPTCTRL3: TXE Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  LCD Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  LCD_TIMH  --------------------------------------------
+#define LCD_TIMH_PPL_Pos                                      2                                                         /*!< LCD TIMH: PPL Position              */
+#define LCD_TIMH_PPL_Msk                                      (0x3fUL << LCD_TIMH_PPL_Pos)                              /*!< LCD TIMH: PPL Mask                  */
+#define LCD_TIMH_HSW_Pos                                      8                                                         /*!< LCD TIMH: HSW Position              */
+#define LCD_TIMH_HSW_Msk                                      (0x000000ffUL << LCD_TIMH_HSW_Pos)                        /*!< LCD TIMH: HSW Mask                  */
+#define LCD_TIMH_HFP_Pos                                      16                                                        /*!< LCD TIMH: HFP Position              */
+#define LCD_TIMH_HFP_Msk                                      (0x000000ffUL << LCD_TIMH_HFP_Pos)                        /*!< LCD TIMH: HFP Mask                  */
+#define LCD_TIMH_HBP_Pos                                      24                                                        /*!< LCD TIMH: HBP Position              */
+#define LCD_TIMH_HBP_Msk                                      (0x000000ffUL << LCD_TIMH_HBP_Pos)                        /*!< LCD TIMH: HBP Mask                  */
+
+// ----------------------------------------  LCD_TIMV  --------------------------------------------
+#define LCD_TIMV_LPP_Pos                                      0                                                         /*!< LCD TIMV: LPP Position              */
+#define LCD_TIMV_LPP_Msk                                      (0x000003ffUL << LCD_TIMV_LPP_Pos)                        /*!< LCD TIMV: LPP Mask                  */
+#define LCD_TIMV_VSW_Pos                                      10                                                        /*!< LCD TIMV: VSW Position              */
+#define LCD_TIMV_VSW_Msk                                      (0x3fUL << LCD_TIMV_VSW_Pos)                              /*!< LCD TIMV: VSW Mask                  */
+#define LCD_TIMV_VFP_Pos                                      16                                                        /*!< LCD TIMV: VFP Position              */
+#define LCD_TIMV_VFP_Msk                                      (0x000000ffUL << LCD_TIMV_VFP_Pos)                        /*!< LCD TIMV: VFP Mask                  */
+#define LCD_TIMV_VBP_Pos                                      24                                                        /*!< LCD TIMV: VBP Position              */
+#define LCD_TIMV_VBP_Msk                                      (0x000000ffUL << LCD_TIMV_VBP_Pos)                        /*!< LCD TIMV: VBP Mask                  */
+
+// -----------------------------------------  LCD_POL  --------------------------------------------
+#define LCD_POL_PCD_LO_Pos                                    0                                                         /*!< LCD POL: PCD_LO Position            */
+#define LCD_POL_PCD_LO_Msk                                    (0x1fUL << LCD_POL_PCD_LO_Pos)                            /*!< LCD POL: PCD_LO Mask                */
+#define LCD_POL_CLKSEL_Pos                                    5                                                         /*!< LCD POL: CLKSEL Position            */
+#define LCD_POL_CLKSEL_Msk                                    (0x01UL << LCD_POL_CLKSEL_Pos)                            /*!< LCD POL: CLKSEL Mask                */
+#define LCD_POL_ACB_Pos                                       6                                                         /*!< LCD POL: ACB Position               */
+#define LCD_POL_ACB_Msk                                       (0x1fUL << LCD_POL_ACB_Pos)                               /*!< LCD POL: ACB Mask                   */
+#define LCD_POL_IVS_Pos                                       11                                                        /*!< LCD POL: IVS Position               */
+#define LCD_POL_IVS_Msk                                       (0x01UL << LCD_POL_IVS_Pos)                               /*!< LCD POL: IVS Mask                   */
+#define LCD_POL_IHS_Pos                                       12                                                        /*!< LCD POL: IHS Position               */
+#define LCD_POL_IHS_Msk                                       (0x01UL << LCD_POL_IHS_Pos)                               /*!< LCD POL: IHS Mask                   */
+#define LCD_POL_IPC_Pos                                       13                                                        /*!< LCD POL: IPC Position               */
+#define LCD_POL_IPC_Msk                                       (0x01UL << LCD_POL_IPC_Pos)                               /*!< LCD POL: IPC Mask                   */
+#define LCD_POL_IOE_Pos                                       14                                                        /*!< LCD POL: IOE Position               */
+#define LCD_POL_IOE_Msk                                       (0x01UL << LCD_POL_IOE_Pos)                               /*!< LCD POL: IOE Mask                   */
+#define LCD_POL_CPL_Pos                                       16                                                        /*!< LCD POL: CPL Position               */
+#define LCD_POL_CPL_Msk                                       (0x000003ffUL << LCD_POL_CPL_Pos)                         /*!< LCD POL: CPL Mask                   */
+#define LCD_POL_BCD_Pos                                       26                                                        /*!< LCD POL: BCD Position               */
+#define LCD_POL_BCD_Msk                                       (0x01UL << LCD_POL_BCD_Pos)                               /*!< LCD POL: BCD Mask                   */
+#define LCD_POL_PCD_HI_Pos                                    27                                                        /*!< LCD POL: PCD_HI Position            */
+#define LCD_POL_PCD_HI_Msk                                    (0x1fUL << LCD_POL_PCD_HI_Pos)                            /*!< LCD POL: PCD_HI Mask                */
+
+// -----------------------------------------  LCD_LE  ---------------------------------------------
+#define LCD_LE_LED_Pos                                        0                                                         /*!< LCD LE: LED Position                */
+#define LCD_LE_LED_Msk                                        (0x7fUL << LCD_LE_LED_Pos)                                /*!< LCD LE: LED Mask                    */
+#define LCD_LE_LEE_Pos                                        16                                                        /*!< LCD LE: LEE Position                */
+#define LCD_LE_LEE_Msk                                        (0x01UL << LCD_LE_LEE_Pos)                                /*!< LCD LE: LEE Mask                    */
+
+// ---------------------------------------  LCD_UPBASE  -------------------------------------------
+#define LCD_UPBASE_LCDUPBASE_Pos                              3                                                         /*!< LCD UPBASE: LCDUPBASE Position      */
+#define LCD_UPBASE_LCDUPBASE_Msk                              (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos)                /*!< LCD UPBASE: LCDUPBASE Mask          */
+
+// ---------------------------------------  LCD_LPBASE  -------------------------------------------
+#define LCD_LPBASE_LCDLPBASE_Pos                              3                                                         /*!< LCD LPBASE: LCDLPBASE Position      */
+#define LCD_LPBASE_LCDLPBASE_Msk                              (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos)                /*!< LCD LPBASE: LCDLPBASE Mask          */
+
+// ----------------------------------------  LCD_CTRL  --------------------------------------------
+#define LCD_CTRL_LCDEN_Pos                                    0                                                         /*!< LCD CTRL: LCDEN Position            */
+#define LCD_CTRL_LCDEN_Msk                                    (0x01UL << LCD_CTRL_LCDEN_Pos)                            /*!< LCD CTRL: LCDEN Mask                */
+#define LCD_CTRL_LCDBPP_Pos                                   1                                                         /*!< LCD CTRL: LCDBPP Position           */
+#define LCD_CTRL_LCDBPP_Msk                                   (0x07UL << LCD_CTRL_LCDBPP_Pos)                           /*!< LCD CTRL: LCDBPP Mask               */
+#define LCD_CTRL_LCDBW_Pos                                    4                                                         /*!< LCD CTRL: LCDBW Position            */
+#define LCD_CTRL_LCDBW_Msk                                    (0x01UL << LCD_CTRL_LCDBW_Pos)                            /*!< LCD CTRL: LCDBW Mask                */
+#define LCD_CTRL_LCDTFT_Pos                                   5                                                         /*!< LCD CTRL: LCDTFT Position           */
+#define LCD_CTRL_LCDTFT_Msk                                   (0x01UL << LCD_CTRL_LCDTFT_Pos)                           /*!< LCD CTRL: LCDTFT Mask               */
+#define LCD_CTRL_LCDMONO8_Pos                                 6                                                         /*!< LCD CTRL: LCDMONO8 Position         */
+#define LCD_CTRL_LCDMONO8_Msk                                 (0x01UL << LCD_CTRL_LCDMONO8_Pos)                         /*!< LCD CTRL: LCDMONO8 Mask             */
+#define LCD_CTRL_LCDDUAL_Pos                                  7                                                         /*!< LCD CTRL: LCDDUAL Position          */
+#define LCD_CTRL_LCDDUAL_Msk                                  (0x01UL << LCD_CTRL_LCDDUAL_Pos)                          /*!< LCD CTRL: LCDDUAL Mask              */
+#define LCD_CTRL_BGR_Pos                                      8                                                         /*!< LCD CTRL: BGR Position              */
+#define LCD_CTRL_BGR_Msk                                      (0x01UL << LCD_CTRL_BGR_Pos)                              /*!< LCD CTRL: BGR Mask                  */
+#define LCD_CTRL_BEBO_Pos                                     9                                                         /*!< LCD CTRL: BEBO Position             */
+#define LCD_CTRL_BEBO_Msk                                     (0x01UL << LCD_CTRL_BEBO_Pos)                             /*!< LCD CTRL: BEBO Mask                 */
+#define LCD_CTRL_BEPO_Pos                                     10                                                        /*!< LCD CTRL: BEPO Position             */
+#define LCD_CTRL_BEPO_Msk                                     (0x01UL << LCD_CTRL_BEPO_Pos)                             /*!< LCD CTRL: BEPO Mask                 */
+#define LCD_CTRL_LCDPWR_Pos                                   11                                                        /*!< LCD CTRL: LCDPWR Position           */
+#define LCD_CTRL_LCDPWR_Msk                                   (0x01UL << LCD_CTRL_LCDPWR_Pos)                           /*!< LCD CTRL: LCDPWR Mask               */
+#define LCD_CTRL_LCDVCOMP_Pos                                 12                                                        /*!< LCD CTRL: LCDVCOMP Position         */
+#define LCD_CTRL_LCDVCOMP_Msk                                 (0x03UL << LCD_CTRL_LCDVCOMP_Pos)                         /*!< LCD CTRL: LCDVCOMP Mask             */
+#define LCD_CTRL_WATERMARK_Pos                                16                                                        /*!< LCD CTRL: WATERMARK Position        */
+#define LCD_CTRL_WATERMARK_Msk                                (0x01UL << LCD_CTRL_WATERMARK_Pos)                        /*!< LCD CTRL: WATERMARK Mask            */
+
+// ---------------------------------------  LCD_INTMSK  -------------------------------------------
+#define LCD_INTMSK_FUFIM_Pos                                  1                                                         /*!< LCD INTMSK: FUFIM Position          */
+#define LCD_INTMSK_FUFIM_Msk                                  (0x01UL << LCD_INTMSK_FUFIM_Pos)                          /*!< LCD INTMSK: FUFIM Mask              */
+#define LCD_INTMSK_LNBUIM_Pos                                 2                                                         /*!< LCD INTMSK: LNBUIM Position         */
+#define LCD_INTMSK_LNBUIM_Msk                                 (0x01UL << LCD_INTMSK_LNBUIM_Pos)                         /*!< LCD INTMSK: LNBUIM Mask             */
+#define LCD_INTMSK_VCOMPIM_Pos                                3                                                         /*!< LCD INTMSK: VCOMPIM Position        */
+#define LCD_INTMSK_VCOMPIM_Msk                                (0x01UL << LCD_INTMSK_VCOMPIM_Pos)                        /*!< LCD INTMSK: VCOMPIM Mask            */
+#define LCD_INTMSK_BERIM_Pos                                  4                                                         /*!< LCD INTMSK: BERIM Position          */
+#define LCD_INTMSK_BERIM_Msk                                  (0x01UL << LCD_INTMSK_BERIM_Pos)                          /*!< LCD INTMSK: BERIM Mask              */
+
+// ---------------------------------------  LCD_INTRAW  -------------------------------------------
+#define LCD_INTRAW_FUFRIS_Pos                                 1                                                         /*!< LCD INTRAW: FUFRIS Position         */
+#define LCD_INTRAW_FUFRIS_Msk                                 (0x01UL << LCD_INTRAW_FUFRIS_Pos)                         /*!< LCD INTRAW: FUFRIS Mask             */
+#define LCD_INTRAW_LNBURIS_Pos                                2                                                         /*!< LCD INTRAW: LNBURIS Position        */
+#define LCD_INTRAW_LNBURIS_Msk                                (0x01UL << LCD_INTRAW_LNBURIS_Pos)                        /*!< LCD INTRAW: LNBURIS Mask            */
+#define LCD_INTRAW_VCOMPRIS_Pos                               3                                                         /*!< LCD INTRAW: VCOMPRIS Position       */
+#define LCD_INTRAW_VCOMPRIS_Msk                               (0x01UL << LCD_INTRAW_VCOMPRIS_Pos)                       /*!< LCD INTRAW: VCOMPRIS Mask           */
+#define LCD_INTRAW_BERRAW_Pos                                 4                                                         /*!< LCD INTRAW: BERRAW Position         */
+#define LCD_INTRAW_BERRAW_Msk                                 (0x01UL << LCD_INTRAW_BERRAW_Pos)                         /*!< LCD INTRAW: BERRAW Mask             */
+
+// ---------------------------------------  LCD_INTSTAT  ------------------------------------------
+#define LCD_INTSTAT_FUFMIS_Pos                                1                                                         /*!< LCD INTSTAT: FUFMIS Position        */
+#define LCD_INTSTAT_FUFMIS_Msk                                (0x01UL << LCD_INTSTAT_FUFMIS_Pos)                        /*!< LCD INTSTAT: FUFMIS Mask            */
+#define LCD_INTSTAT_LNBUMIS_Pos                               2                                                         /*!< LCD INTSTAT: LNBUMIS Position       */
+#define LCD_INTSTAT_LNBUMIS_Msk                               (0x01UL << LCD_INTSTAT_LNBUMIS_Pos)                       /*!< LCD INTSTAT: LNBUMIS Mask           */
+#define LCD_INTSTAT_VCOMPMIS_Pos                              3                                                         /*!< LCD INTSTAT: VCOMPMIS Position      */
+#define LCD_INTSTAT_VCOMPMIS_Msk                              (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos)                      /*!< LCD INTSTAT: VCOMPMIS Mask          */
+#define LCD_INTSTAT_BERMIS_Pos                                4                                                         /*!< LCD INTSTAT: BERMIS Position        */
+#define LCD_INTSTAT_BERMIS_Msk                                (0x01UL << LCD_INTSTAT_BERMIS_Pos)                        /*!< LCD INTSTAT: BERMIS Mask            */
+
+// ---------------------------------------  LCD_INTCLR  -------------------------------------------
+#define LCD_INTCLR_FUFIC_Pos                                  1                                                         /*!< LCD INTCLR: FUFIC Position          */
+#define LCD_INTCLR_FUFIC_Msk                                  (0x01UL << LCD_INTCLR_FUFIC_Pos)                          /*!< LCD INTCLR: FUFIC Mask              */
+#define LCD_INTCLR_LNBUIC_Pos                                 2                                                         /*!< LCD INTCLR: LNBUIC Position         */
+#define LCD_INTCLR_LNBUIC_Msk                                 (0x01UL << LCD_INTCLR_LNBUIC_Pos)                         /*!< LCD INTCLR: LNBUIC Mask             */
+#define LCD_INTCLR_VCOMPIC_Pos                                3                                                         /*!< LCD INTCLR: VCOMPIC Position        */
+#define LCD_INTCLR_VCOMPIC_Msk                                (0x01UL << LCD_INTCLR_VCOMPIC_Pos)                        /*!< LCD INTCLR: VCOMPIC Mask            */
+#define LCD_INTCLR_BERIC_Pos                                  4                                                         /*!< LCD INTCLR: BERIC Position          */
+#define LCD_INTCLR_BERIC_Msk                                  (0x01UL << LCD_INTCLR_BERIC_Pos)                          /*!< LCD INTCLR: BERIC Mask              */
+
+// ---------------------------------------  LCD_UPCURR  -------------------------------------------
+#define LCD_UPCURR_LCDUPCURR_Pos                              0                                                         /*!< LCD UPCURR: LCDUPCURR Position      */
+#define LCD_UPCURR_LCDUPCURR_Msk                              (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos)                /*!< LCD UPCURR: LCDUPCURR Mask          */
+
+// ---------------------------------------  LCD_LPCURR  -------------------------------------------
+#define LCD_LPCURR_LCDLPCURR_Pos                              0                                                         /*!< LCD LPCURR: LCDLPCURR Position      */
+#define LCD_LPCURR_LCDLPCURR_Msk                              (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos)                /*!< LCD LPCURR: LCDLPCURR Mask          */
+
+// ----------------------------------------  LCD_PAL0  --------------------------------------------
+#define LCD_PAL0_R04_0_Pos                                    0                                                         /*!< LCD PAL0: R04_0 Position            */
+#define LCD_PAL0_R04_0_Msk                                    (0x1fUL << LCD_PAL0_R04_0_Pos)                            /*!< LCD PAL0: R04_0 Mask                */
+#define LCD_PAL0_G04_0_Pos                                    5                                                         /*!< LCD PAL0: G04_0 Position            */
+#define LCD_PAL0_G04_0_Msk                                    (0x1fUL << LCD_PAL0_G04_0_Pos)                            /*!< LCD PAL0: G04_0 Mask                */
+#define LCD_PAL0_B04_0_Pos                                    10                                                        /*!< LCD PAL0: B04_0 Position            */
+#define LCD_PAL0_B04_0_Msk                                    (0x1fUL << LCD_PAL0_B04_0_Pos)                            /*!< LCD PAL0: B04_0 Mask                */
+#define LCD_PAL0_I0_Pos                                       15                                                        /*!< LCD PAL0: I0 Position               */
+#define LCD_PAL0_I0_Msk                                       (0x01UL << LCD_PAL0_I0_Pos)                               /*!< LCD PAL0: I0 Mask                   */
+#define LCD_PAL0_R14_0_Pos                                    16                                                        /*!< LCD PAL0: R14_0 Position            */
+#define LCD_PAL0_R14_0_Msk                                    (0x1fUL << LCD_PAL0_R14_0_Pos)                            /*!< LCD PAL0: R14_0 Mask                */
+#define LCD_PAL0_G14_0_Pos                                    21                                                        /*!< LCD PAL0: G14_0 Position            */
+#define LCD_PAL0_G14_0_Msk                                    (0x1fUL << LCD_PAL0_G14_0_Pos)                            /*!< LCD PAL0: G14_0 Mask                */
+#define LCD_PAL0_B14_0_Pos                                    26                                                        /*!< LCD PAL0: B14_0 Position            */
+#define LCD_PAL0_B14_0_Msk                                    (0x1fUL << LCD_PAL0_B14_0_Pos)                            /*!< LCD PAL0: B14_0 Mask                */
+#define LCD_PAL0_I1_Pos                                       31                                                        /*!< LCD PAL0: I1 Position               */
+#define LCD_PAL0_I1_Msk                                       (0x01UL << LCD_PAL0_I1_Pos)                               /*!< LCD PAL0: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL1  --------------------------------------------
+#define LCD_PAL1_R04_0_Pos                                    0                                                         /*!< LCD PAL1: R04_0 Position            */
+#define LCD_PAL1_R04_0_Msk                                    (0x1fUL << LCD_PAL1_R04_0_Pos)                            /*!< LCD PAL1: R04_0 Mask                */
+#define LCD_PAL1_G04_0_Pos                                    5                                                         /*!< LCD PAL1: G04_0 Position            */
+#define LCD_PAL1_G04_0_Msk                                    (0x1fUL << LCD_PAL1_G04_0_Pos)                            /*!< LCD PAL1: G04_0 Mask                */
+#define LCD_PAL1_B04_0_Pos                                    10                                                        /*!< LCD PAL1: B04_0 Position            */
+#define LCD_PAL1_B04_0_Msk                                    (0x1fUL << LCD_PAL1_B04_0_Pos)                            /*!< LCD PAL1: B04_0 Mask                */
+#define LCD_PAL1_I0_Pos                                       15                                                        /*!< LCD PAL1: I0 Position               */
+#define LCD_PAL1_I0_Msk                                       (0x01UL << LCD_PAL1_I0_Pos)                               /*!< LCD PAL1: I0 Mask                   */
+#define LCD_PAL1_R14_0_Pos                                    16                                                        /*!< LCD PAL1: R14_0 Position            */
+#define LCD_PAL1_R14_0_Msk                                    (0x1fUL << LCD_PAL1_R14_0_Pos)                            /*!< LCD PAL1: R14_0 Mask                */
+#define LCD_PAL1_G14_0_Pos                                    21                                                        /*!< LCD PAL1: G14_0 Position            */
+#define LCD_PAL1_G14_0_Msk                                    (0x1fUL << LCD_PAL1_G14_0_Pos)                            /*!< LCD PAL1: G14_0 Mask                */
+#define LCD_PAL1_B14_0_Pos                                    26                                                        /*!< LCD PAL1: B14_0 Position            */
+#define LCD_PAL1_B14_0_Msk                                    (0x1fUL << LCD_PAL1_B14_0_Pos)                            /*!< LCD PAL1: B14_0 Mask                */
+#define LCD_PAL1_I1_Pos                                       31                                                        /*!< LCD PAL1: I1 Position               */
+#define LCD_PAL1_I1_Msk                                       (0x01UL << LCD_PAL1_I1_Pos)                               /*!< LCD PAL1: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL2  --------------------------------------------
+#define LCD_PAL2_R04_0_Pos                                    0                                                         /*!< LCD PAL2: R04_0 Position            */
+#define LCD_PAL2_R04_0_Msk                                    (0x1fUL << LCD_PAL2_R04_0_Pos)                            /*!< LCD PAL2: R04_0 Mask                */
+#define LCD_PAL2_G04_0_Pos                                    5                                                         /*!< LCD PAL2: G04_0 Position            */
+#define LCD_PAL2_G04_0_Msk                                    (0x1fUL << LCD_PAL2_G04_0_Pos)                            /*!< LCD PAL2: G04_0 Mask                */
+#define LCD_PAL2_B04_0_Pos                                    10                                                        /*!< LCD PAL2: B04_0 Position            */
+#define LCD_PAL2_B04_0_Msk                                    (0x1fUL << LCD_PAL2_B04_0_Pos)                            /*!< LCD PAL2: B04_0 Mask                */
+#define LCD_PAL2_I0_Pos                                       15                                                        /*!< LCD PAL2: I0 Position               */
+#define LCD_PAL2_I0_Msk                                       (0x01UL << LCD_PAL2_I0_Pos)                               /*!< LCD PAL2: I0 Mask                   */
+#define LCD_PAL2_R14_0_Pos                                    16                                                        /*!< LCD PAL2: R14_0 Position            */
+#define LCD_PAL2_R14_0_Msk                                    (0x1fUL << LCD_PAL2_R14_0_Pos)                            /*!< LCD PAL2: R14_0 Mask                */
+#define LCD_PAL2_G14_0_Pos                                    21                                                        /*!< LCD PAL2: G14_0 Position            */
+#define LCD_PAL2_G14_0_Msk                                    (0x1fUL << LCD_PAL2_G14_0_Pos)                            /*!< LCD PAL2: G14_0 Mask                */
+#define LCD_PAL2_B14_0_Pos                                    26                                                        /*!< LCD PAL2: B14_0 Position            */
+#define LCD_PAL2_B14_0_Msk                                    (0x1fUL << LCD_PAL2_B14_0_Pos)                            /*!< LCD PAL2: B14_0 Mask                */
+#define LCD_PAL2_I1_Pos                                       31                                                        /*!< LCD PAL2: I1 Position               */
+#define LCD_PAL2_I1_Msk                                       (0x01UL << LCD_PAL2_I1_Pos)                               /*!< LCD PAL2: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL3  --------------------------------------------
+#define LCD_PAL3_R04_0_Pos                                    0                                                         /*!< LCD PAL3: R04_0 Position            */
+#define LCD_PAL3_R04_0_Msk                                    (0x1fUL << LCD_PAL3_R04_0_Pos)                            /*!< LCD PAL3: R04_0 Mask                */
+#define LCD_PAL3_G04_0_Pos                                    5                                                         /*!< LCD PAL3: G04_0 Position            */
+#define LCD_PAL3_G04_0_Msk                                    (0x1fUL << LCD_PAL3_G04_0_Pos)                            /*!< LCD PAL3: G04_0 Mask                */
+#define LCD_PAL3_B04_0_Pos                                    10                                                        /*!< LCD PAL3: B04_0 Position            */
+#define LCD_PAL3_B04_0_Msk                                    (0x1fUL << LCD_PAL3_B04_0_Pos)                            /*!< LCD PAL3: B04_0 Mask                */
+#define LCD_PAL3_I0_Pos                                       15                                                        /*!< LCD PAL3: I0 Position               */
+#define LCD_PAL3_I0_Msk                                       (0x01UL << LCD_PAL3_I0_Pos)                               /*!< LCD PAL3: I0 Mask                   */
+#define LCD_PAL3_R14_0_Pos                                    16                                                        /*!< LCD PAL3: R14_0 Position            */
+#define LCD_PAL3_R14_0_Msk                                    (0x1fUL << LCD_PAL3_R14_0_Pos)                            /*!< LCD PAL3: R14_0 Mask                */
+#define LCD_PAL3_G14_0_Pos                                    21                                                        /*!< LCD PAL3: G14_0 Position            */
+#define LCD_PAL3_G14_0_Msk                                    (0x1fUL << LCD_PAL3_G14_0_Pos)                            /*!< LCD PAL3: G14_0 Mask                */
+#define LCD_PAL3_B14_0_Pos                                    26                                                        /*!< LCD PAL3: B14_0 Position            */
+#define LCD_PAL3_B14_0_Msk                                    (0x1fUL << LCD_PAL3_B14_0_Pos)                            /*!< LCD PAL3: B14_0 Mask                */
+#define LCD_PAL3_I1_Pos                                       31                                                        /*!< LCD PAL3: I1 Position               */
+#define LCD_PAL3_I1_Msk                                       (0x01UL << LCD_PAL3_I1_Pos)                               /*!< LCD PAL3: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL4  --------------------------------------------
+#define LCD_PAL4_R04_0_Pos                                    0                                                         /*!< LCD PAL4: R04_0 Position            */
+#define LCD_PAL4_R04_0_Msk                                    (0x1fUL << LCD_PAL4_R04_0_Pos)                            /*!< LCD PAL4: R04_0 Mask                */
+#define LCD_PAL4_G04_0_Pos                                    5                                                         /*!< LCD PAL4: G04_0 Position            */
+#define LCD_PAL4_G04_0_Msk                                    (0x1fUL << LCD_PAL4_G04_0_Pos)                            /*!< LCD PAL4: G04_0 Mask                */
+#define LCD_PAL4_B04_0_Pos                                    10                                                        /*!< LCD PAL4: B04_0 Position            */
+#define LCD_PAL4_B04_0_Msk                                    (0x1fUL << LCD_PAL4_B04_0_Pos)                            /*!< LCD PAL4: B04_0 Mask                */
+#define LCD_PAL4_I0_Pos                                       15                                                        /*!< LCD PAL4: I0 Position               */
+#define LCD_PAL4_I0_Msk                                       (0x01UL << LCD_PAL4_I0_Pos)                               /*!< LCD PAL4: I0 Mask                   */
+#define LCD_PAL4_R14_0_Pos                                    16                                                        /*!< LCD PAL4: R14_0 Position            */
+#define LCD_PAL4_R14_0_Msk                                    (0x1fUL << LCD_PAL4_R14_0_Pos)                            /*!< LCD PAL4: R14_0 Mask                */
+#define LCD_PAL4_G14_0_Pos                                    21                                                        /*!< LCD PAL4: G14_0 Position            */
+#define LCD_PAL4_G14_0_Msk                                    (0x1fUL << LCD_PAL4_G14_0_Pos)                            /*!< LCD PAL4: G14_0 Mask                */
+#define LCD_PAL4_B14_0_Pos                                    26                                                        /*!< LCD PAL4: B14_0 Position            */
+#define LCD_PAL4_B14_0_Msk                                    (0x1fUL << LCD_PAL4_B14_0_Pos)                            /*!< LCD PAL4: B14_0 Mask                */
+#define LCD_PAL4_I1_Pos                                       31                                                        /*!< LCD PAL4: I1 Position               */
+#define LCD_PAL4_I1_Msk                                       (0x01UL << LCD_PAL4_I1_Pos)                               /*!< LCD PAL4: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL5  --------------------------------------------
+#define LCD_PAL5_R04_0_Pos                                    0                                                         /*!< LCD PAL5: R04_0 Position            */
+#define LCD_PAL5_R04_0_Msk                                    (0x1fUL << LCD_PAL5_R04_0_Pos)                            /*!< LCD PAL5: R04_0 Mask                */
+#define LCD_PAL5_G04_0_Pos                                    5                                                         /*!< LCD PAL5: G04_0 Position            */
+#define LCD_PAL5_G04_0_Msk                                    (0x1fUL << LCD_PAL5_G04_0_Pos)                            /*!< LCD PAL5: G04_0 Mask                */
+#define LCD_PAL5_B04_0_Pos                                    10                                                        /*!< LCD PAL5: B04_0 Position            */
+#define LCD_PAL5_B04_0_Msk                                    (0x1fUL << LCD_PAL5_B04_0_Pos)                            /*!< LCD PAL5: B04_0 Mask                */
+#define LCD_PAL5_I0_Pos                                       15                                                        /*!< LCD PAL5: I0 Position               */
+#define LCD_PAL5_I0_Msk                                       (0x01UL << LCD_PAL5_I0_Pos)                               /*!< LCD PAL5: I0 Mask                   */
+#define LCD_PAL5_R14_0_Pos                                    16                                                        /*!< LCD PAL5: R14_0 Position            */
+#define LCD_PAL5_R14_0_Msk                                    (0x1fUL << LCD_PAL5_R14_0_Pos)                            /*!< LCD PAL5: R14_0 Mask                */
+#define LCD_PAL5_G14_0_Pos                                    21                                                        /*!< LCD PAL5: G14_0 Position            */
+#define LCD_PAL5_G14_0_Msk                                    (0x1fUL << LCD_PAL5_G14_0_Pos)                            /*!< LCD PAL5: G14_0 Mask                */
+#define LCD_PAL5_B14_0_Pos                                    26                                                        /*!< LCD PAL5: B14_0 Position            */
+#define LCD_PAL5_B14_0_Msk                                    (0x1fUL << LCD_PAL5_B14_0_Pos)                            /*!< LCD PAL5: B14_0 Mask                */
+#define LCD_PAL5_I1_Pos                                       31                                                        /*!< LCD PAL5: I1 Position               */
+#define LCD_PAL5_I1_Msk                                       (0x01UL << LCD_PAL5_I1_Pos)                               /*!< LCD PAL5: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL6  --------------------------------------------
+#define LCD_PAL6_R04_0_Pos                                    0                                                         /*!< LCD PAL6: R04_0 Position            */
+#define LCD_PAL6_R04_0_Msk                                    (0x1fUL << LCD_PAL6_R04_0_Pos)                            /*!< LCD PAL6: R04_0 Mask                */
+#define LCD_PAL6_G04_0_Pos                                    5                                                         /*!< LCD PAL6: G04_0 Position            */
+#define LCD_PAL6_G04_0_Msk                                    (0x1fUL << LCD_PAL6_G04_0_Pos)                            /*!< LCD PAL6: G04_0 Mask                */
+#define LCD_PAL6_B04_0_Pos                                    10                                                        /*!< LCD PAL6: B04_0 Position            */
+#define LCD_PAL6_B04_0_Msk                                    (0x1fUL << LCD_PAL6_B04_0_Pos)                            /*!< LCD PAL6: B04_0 Mask                */
+#define LCD_PAL6_I0_Pos                                       15                                                        /*!< LCD PAL6: I0 Position               */
+#define LCD_PAL6_I0_Msk                                       (0x01UL << LCD_PAL6_I0_Pos)                               /*!< LCD PAL6: I0 Mask                   */
+#define LCD_PAL6_R14_0_Pos                                    16                                                        /*!< LCD PAL6: R14_0 Position            */
+#define LCD_PAL6_R14_0_Msk                                    (0x1fUL << LCD_PAL6_R14_0_Pos)                            /*!< LCD PAL6: R14_0 Mask                */
+#define LCD_PAL6_G14_0_Pos                                    21                                                        /*!< LCD PAL6: G14_0 Position            */
+#define LCD_PAL6_G14_0_Msk                                    (0x1fUL << LCD_PAL6_G14_0_Pos)                            /*!< LCD PAL6: G14_0 Mask                */
+#define LCD_PAL6_B14_0_Pos                                    26                                                        /*!< LCD PAL6: B14_0 Position            */
+#define LCD_PAL6_B14_0_Msk                                    (0x1fUL << LCD_PAL6_B14_0_Pos)                            /*!< LCD PAL6: B14_0 Mask                */
+#define LCD_PAL6_I1_Pos                                       31                                                        /*!< LCD PAL6: I1 Position               */
+#define LCD_PAL6_I1_Msk                                       (0x01UL << LCD_PAL6_I1_Pos)                               /*!< LCD PAL6: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL7  --------------------------------------------
+#define LCD_PAL7_R04_0_Pos                                    0                                                         /*!< LCD PAL7: R04_0 Position            */
+#define LCD_PAL7_R04_0_Msk                                    (0x1fUL << LCD_PAL7_R04_0_Pos)                            /*!< LCD PAL7: R04_0 Mask                */
+#define LCD_PAL7_G04_0_Pos                                    5                                                         /*!< LCD PAL7: G04_0 Position            */
+#define LCD_PAL7_G04_0_Msk                                    (0x1fUL << LCD_PAL7_G04_0_Pos)                            /*!< LCD PAL7: G04_0 Mask                */
+#define LCD_PAL7_B04_0_Pos                                    10                                                        /*!< LCD PAL7: B04_0 Position            */
+#define LCD_PAL7_B04_0_Msk                                    (0x1fUL << LCD_PAL7_B04_0_Pos)                            /*!< LCD PAL7: B04_0 Mask                */
+#define LCD_PAL7_I0_Pos                                       15                                                        /*!< LCD PAL7: I0 Position               */
+#define LCD_PAL7_I0_Msk                                       (0x01UL << LCD_PAL7_I0_Pos)                               /*!< LCD PAL7: I0 Mask                   */
+#define LCD_PAL7_R14_0_Pos                                    16                                                        /*!< LCD PAL7: R14_0 Position            */
+#define LCD_PAL7_R14_0_Msk                                    (0x1fUL << LCD_PAL7_R14_0_Pos)                            /*!< LCD PAL7: R14_0 Mask                */
+#define LCD_PAL7_G14_0_Pos                                    21                                                        /*!< LCD PAL7: G14_0 Position            */
+#define LCD_PAL7_G14_0_Msk                                    (0x1fUL << LCD_PAL7_G14_0_Pos)                            /*!< LCD PAL7: G14_0 Mask                */
+#define LCD_PAL7_B14_0_Pos                                    26                                                        /*!< LCD PAL7: B14_0 Position            */
+#define LCD_PAL7_B14_0_Msk                                    (0x1fUL << LCD_PAL7_B14_0_Pos)                            /*!< LCD PAL7: B14_0 Mask                */
+#define LCD_PAL7_I1_Pos                                       31                                                        /*!< LCD PAL7: I1 Position               */
+#define LCD_PAL7_I1_Msk                                       (0x01UL << LCD_PAL7_I1_Pos)                               /*!< LCD PAL7: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL8  --------------------------------------------
+#define LCD_PAL8_R04_0_Pos                                    0                                                         /*!< LCD PAL8: R04_0 Position            */
+#define LCD_PAL8_R04_0_Msk                                    (0x1fUL << LCD_PAL8_R04_0_Pos)                            /*!< LCD PAL8: R04_0 Mask                */
+#define LCD_PAL8_G04_0_Pos                                    5                                                         /*!< LCD PAL8: G04_0 Position            */
+#define LCD_PAL8_G04_0_Msk                                    (0x1fUL << LCD_PAL8_G04_0_Pos)                            /*!< LCD PAL8: G04_0 Mask                */
+#define LCD_PAL8_B04_0_Pos                                    10                                                        /*!< LCD PAL8: B04_0 Position            */
+#define LCD_PAL8_B04_0_Msk                                    (0x1fUL << LCD_PAL8_B04_0_Pos)                            /*!< LCD PAL8: B04_0 Mask                */
+#define LCD_PAL8_I0_Pos                                       15                                                        /*!< LCD PAL8: I0 Position               */
+#define LCD_PAL8_I0_Msk                                       (0x01UL << LCD_PAL8_I0_Pos)                               /*!< LCD PAL8: I0 Mask                   */
+#define LCD_PAL8_R14_0_Pos                                    16                                                        /*!< LCD PAL8: R14_0 Position            */
+#define LCD_PAL8_R14_0_Msk                                    (0x1fUL << LCD_PAL8_R14_0_Pos)                            /*!< LCD PAL8: R14_0 Mask                */
+#define LCD_PAL8_G14_0_Pos                                    21                                                        /*!< LCD PAL8: G14_0 Position            */
+#define LCD_PAL8_G14_0_Msk                                    (0x1fUL << LCD_PAL8_G14_0_Pos)                            /*!< LCD PAL8: G14_0 Mask                */
+#define LCD_PAL8_B14_0_Pos                                    26                                                        /*!< LCD PAL8: B14_0 Position            */
+#define LCD_PAL8_B14_0_Msk                                    (0x1fUL << LCD_PAL8_B14_0_Pos)                            /*!< LCD PAL8: B14_0 Mask                */
+#define LCD_PAL8_I1_Pos                                       31                                                        /*!< LCD PAL8: I1 Position               */
+#define LCD_PAL8_I1_Msk                                       (0x01UL << LCD_PAL8_I1_Pos)                               /*!< LCD PAL8: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL9  --------------------------------------------
+#define LCD_PAL9_R04_0_Pos                                    0                                                         /*!< LCD PAL9: R04_0 Position            */
+#define LCD_PAL9_R04_0_Msk                                    (0x1fUL << LCD_PAL9_R04_0_Pos)                            /*!< LCD PAL9: R04_0 Mask                */
+#define LCD_PAL9_G04_0_Pos                                    5                                                         /*!< LCD PAL9: G04_0 Position            */
+#define LCD_PAL9_G04_0_Msk                                    (0x1fUL << LCD_PAL9_G04_0_Pos)                            /*!< LCD PAL9: G04_0 Mask                */
+#define LCD_PAL9_B04_0_Pos                                    10                                                        /*!< LCD PAL9: B04_0 Position            */
+#define LCD_PAL9_B04_0_Msk                                    (0x1fUL << LCD_PAL9_B04_0_Pos)                            /*!< LCD PAL9: B04_0 Mask                */
+#define LCD_PAL9_I0_Pos                                       15                                                        /*!< LCD PAL9: I0 Position               */
+#define LCD_PAL9_I0_Msk                                       (0x01UL << LCD_PAL9_I0_Pos)                               /*!< LCD PAL9: I0 Mask                   */
+#define LCD_PAL9_R14_0_Pos                                    16                                                        /*!< LCD PAL9: R14_0 Position            */
+#define LCD_PAL9_R14_0_Msk                                    (0x1fUL << LCD_PAL9_R14_0_Pos)                            /*!< LCD PAL9: R14_0 Mask                */
+#define LCD_PAL9_G14_0_Pos                                    21                                                        /*!< LCD PAL9: G14_0 Position            */
+#define LCD_PAL9_G14_0_Msk                                    (0x1fUL << LCD_PAL9_G14_0_Pos)                            /*!< LCD PAL9: G14_0 Mask                */
+#define LCD_PAL9_B14_0_Pos                                    26                                                        /*!< LCD PAL9: B14_0 Position            */
+#define LCD_PAL9_B14_0_Msk                                    (0x1fUL << LCD_PAL9_B14_0_Pos)                            /*!< LCD PAL9: B14_0 Mask                */
+#define LCD_PAL9_I1_Pos                                       31                                                        /*!< LCD PAL9: I1 Position               */
+#define LCD_PAL9_I1_Msk                                       (0x01UL << LCD_PAL9_I1_Pos)                               /*!< LCD PAL9: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL10  -------------------------------------------
+#define LCD_PAL10_R04_0_Pos                                   0                                                         /*!< LCD PAL10: R04_0 Position           */
+#define LCD_PAL10_R04_0_Msk                                   (0x1fUL << LCD_PAL10_R04_0_Pos)                           /*!< LCD PAL10: R04_0 Mask               */
+#define LCD_PAL10_G04_0_Pos                                   5                                                         /*!< LCD PAL10: G04_0 Position           */
+#define LCD_PAL10_G04_0_Msk                                   (0x1fUL << LCD_PAL10_G04_0_Pos)                           /*!< LCD PAL10: G04_0 Mask               */
+#define LCD_PAL10_B04_0_Pos                                   10                                                        /*!< LCD PAL10: B04_0 Position           */
+#define LCD_PAL10_B04_0_Msk                                   (0x1fUL << LCD_PAL10_B04_0_Pos)                           /*!< LCD PAL10: B04_0 Mask               */
+#define LCD_PAL10_I0_Pos                                      15                                                        /*!< LCD PAL10: I0 Position              */
+#define LCD_PAL10_I0_Msk                                      (0x01UL << LCD_PAL10_I0_Pos)                              /*!< LCD PAL10: I0 Mask                  */
+#define LCD_PAL10_R14_0_Pos                                   16                                                        /*!< LCD PAL10: R14_0 Position           */
+#define LCD_PAL10_R14_0_Msk                                   (0x1fUL << LCD_PAL10_R14_0_Pos)                           /*!< LCD PAL10: R14_0 Mask               */
+#define LCD_PAL10_G14_0_Pos                                   21                                                        /*!< LCD PAL10: G14_0 Position           */
+#define LCD_PAL10_G14_0_Msk                                   (0x1fUL << LCD_PAL10_G14_0_Pos)                           /*!< LCD PAL10: G14_0 Mask               */
+#define LCD_PAL10_B14_0_Pos                                   26                                                        /*!< LCD PAL10: B14_0 Position           */
+#define LCD_PAL10_B14_0_Msk                                   (0x1fUL << LCD_PAL10_B14_0_Pos)                           /*!< LCD PAL10: B14_0 Mask               */
+#define LCD_PAL10_I1_Pos                                      31                                                        /*!< LCD PAL10: I1 Position              */
+#define LCD_PAL10_I1_Msk                                      (0x01UL << LCD_PAL10_I1_Pos)                              /*!< LCD PAL10: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL11  -------------------------------------------
+#define LCD_PAL11_R04_0_Pos                                   0                                                         /*!< LCD PAL11: R04_0 Position           */
+#define LCD_PAL11_R04_0_Msk                                   (0x1fUL << LCD_PAL11_R04_0_Pos)                           /*!< LCD PAL11: R04_0 Mask               */
+#define LCD_PAL11_G04_0_Pos                                   5                                                         /*!< LCD PAL11: G04_0 Position           */
+#define LCD_PAL11_G04_0_Msk                                   (0x1fUL << LCD_PAL11_G04_0_Pos)                           /*!< LCD PAL11: G04_0 Mask               */
+#define LCD_PAL11_B04_0_Pos                                   10                                                        /*!< LCD PAL11: B04_0 Position           */
+#define LCD_PAL11_B04_0_Msk                                   (0x1fUL << LCD_PAL11_B04_0_Pos)                           /*!< LCD PAL11: B04_0 Mask               */
+#define LCD_PAL11_I0_Pos                                      15                                                        /*!< LCD PAL11: I0 Position              */
+#define LCD_PAL11_I0_Msk                                      (0x01UL << LCD_PAL11_I0_Pos)                              /*!< LCD PAL11: I0 Mask                  */
+#define LCD_PAL11_R14_0_Pos                                   16                                                        /*!< LCD PAL11: R14_0 Position           */
+#define LCD_PAL11_R14_0_Msk                                   (0x1fUL << LCD_PAL11_R14_0_Pos)                           /*!< LCD PAL11: R14_0 Mask               */
+#define LCD_PAL11_G14_0_Pos                                   21                                                        /*!< LCD PAL11: G14_0 Position           */
+#define LCD_PAL11_G14_0_Msk                                   (0x1fUL << LCD_PAL11_G14_0_Pos)                           /*!< LCD PAL11: G14_0 Mask               */
+#define LCD_PAL11_B14_0_Pos                                   26                                                        /*!< LCD PAL11: B14_0 Position           */
+#define LCD_PAL11_B14_0_Msk                                   (0x1fUL << LCD_PAL11_B14_0_Pos)                           /*!< LCD PAL11: B14_0 Mask               */
+#define LCD_PAL11_I1_Pos                                      31                                                        /*!< LCD PAL11: I1 Position              */
+#define LCD_PAL11_I1_Msk                                      (0x01UL << LCD_PAL11_I1_Pos)                              /*!< LCD PAL11: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL12  -------------------------------------------
+#define LCD_PAL12_R04_0_Pos                                   0                                                         /*!< LCD PAL12: R04_0 Position           */
+#define LCD_PAL12_R04_0_Msk                                   (0x1fUL << LCD_PAL12_R04_0_Pos)                           /*!< LCD PAL12: R04_0 Mask               */
+#define LCD_PAL12_G04_0_Pos                                   5                                                         /*!< LCD PAL12: G04_0 Position           */
+#define LCD_PAL12_G04_0_Msk                                   (0x1fUL << LCD_PAL12_G04_0_Pos)                           /*!< LCD PAL12: G04_0 Mask               */
+#define LCD_PAL12_B04_0_Pos                                   10                                                        /*!< LCD PAL12: B04_0 Position           */
+#define LCD_PAL12_B04_0_Msk                                   (0x1fUL << LCD_PAL12_B04_0_Pos)                           /*!< LCD PAL12: B04_0 Mask               */
+#define LCD_PAL12_I0_Pos                                      15                                                        /*!< LCD PAL12: I0 Position              */
+#define LCD_PAL12_I0_Msk                                      (0x01UL << LCD_PAL12_I0_Pos)                              /*!< LCD PAL12: I0 Mask                  */
+#define LCD_PAL12_R14_0_Pos                                   16                                                        /*!< LCD PAL12: R14_0 Position           */
+#define LCD_PAL12_R14_0_Msk                                   (0x1fUL << LCD_PAL12_R14_0_Pos)                           /*!< LCD PAL12: R14_0 Mask               */
+#define LCD_PAL12_G14_0_Pos                                   21                                                        /*!< LCD PAL12: G14_0 Position           */
+#define LCD_PAL12_G14_0_Msk                                   (0x1fUL << LCD_PAL12_G14_0_Pos)                           /*!< LCD PAL12: G14_0 Mask               */
+#define LCD_PAL12_B14_0_Pos                                   26                                                        /*!< LCD PAL12: B14_0 Position           */
+#define LCD_PAL12_B14_0_Msk                                   (0x1fUL << LCD_PAL12_B14_0_Pos)                           /*!< LCD PAL12: B14_0 Mask               */
+#define LCD_PAL12_I1_Pos                                      31                                                        /*!< LCD PAL12: I1 Position              */
+#define LCD_PAL12_I1_Msk                                      (0x01UL << LCD_PAL12_I1_Pos)                              /*!< LCD PAL12: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL13  -------------------------------------------
+#define LCD_PAL13_R04_0_Pos                                   0                                                         /*!< LCD PAL13: R04_0 Position           */
+#define LCD_PAL13_R04_0_Msk                                   (0x1fUL << LCD_PAL13_R04_0_Pos)                           /*!< LCD PAL13: R04_0 Mask               */
+#define LCD_PAL13_G04_0_Pos                                   5                                                         /*!< LCD PAL13: G04_0 Position           */
+#define LCD_PAL13_G04_0_Msk                                   (0x1fUL << LCD_PAL13_G04_0_Pos)                           /*!< LCD PAL13: G04_0 Mask               */
+#define LCD_PAL13_B04_0_Pos                                   10                                                        /*!< LCD PAL13: B04_0 Position           */
+#define LCD_PAL13_B04_0_Msk                                   (0x1fUL << LCD_PAL13_B04_0_Pos)                           /*!< LCD PAL13: B04_0 Mask               */
+#define LCD_PAL13_I0_Pos                                      15                                                        /*!< LCD PAL13: I0 Position              */
+#define LCD_PAL13_I0_Msk                                      (0x01UL << LCD_PAL13_I0_Pos)                              /*!< LCD PAL13: I0 Mask                  */
+#define LCD_PAL13_R14_0_Pos                                   16                                                        /*!< LCD PAL13: R14_0 Position           */
+#define LCD_PAL13_R14_0_Msk                                   (0x1fUL << LCD_PAL13_R14_0_Pos)                           /*!< LCD PAL13: R14_0 Mask               */
+#define LCD_PAL13_G14_0_Pos                                   21                                                        /*!< LCD PAL13: G14_0 Position           */
+#define LCD_PAL13_G14_0_Msk                                   (0x1fUL << LCD_PAL13_G14_0_Pos)                           /*!< LCD PAL13: G14_0 Mask               */
+#define LCD_PAL13_B14_0_Pos                                   26                                                        /*!< LCD PAL13: B14_0 Position           */
+#define LCD_PAL13_B14_0_Msk                                   (0x1fUL << LCD_PAL13_B14_0_Pos)                           /*!< LCD PAL13: B14_0 Mask               */
+#define LCD_PAL13_I1_Pos                                      31                                                        /*!< LCD PAL13: I1 Position              */
+#define LCD_PAL13_I1_Msk                                      (0x01UL << LCD_PAL13_I1_Pos)                              /*!< LCD PAL13: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL14  -------------------------------------------
+#define LCD_PAL14_R04_0_Pos                                   0                                                         /*!< LCD PAL14: R04_0 Position           */
+#define LCD_PAL14_R04_0_Msk                                   (0x1fUL << LCD_PAL14_R04_0_Pos)                           /*!< LCD PAL14: R04_0 Mask               */
+#define LCD_PAL14_G04_0_Pos                                   5                                                         /*!< LCD PAL14: G04_0 Position           */
+#define LCD_PAL14_G04_0_Msk                                   (0x1fUL << LCD_PAL14_G04_0_Pos)                           /*!< LCD PAL14: G04_0 Mask               */
+#define LCD_PAL14_B04_0_Pos                                   10                                                        /*!< LCD PAL14: B04_0 Position           */
+#define LCD_PAL14_B04_0_Msk                                   (0x1fUL << LCD_PAL14_B04_0_Pos)                           /*!< LCD PAL14: B04_0 Mask               */
+#define LCD_PAL14_I0_Pos                                      15                                                        /*!< LCD PAL14: I0 Position              */
+#define LCD_PAL14_I0_Msk                                      (0x01UL << LCD_PAL14_I0_Pos)                              /*!< LCD PAL14: I0 Mask                  */
+#define LCD_PAL14_R14_0_Pos                                   16                                                        /*!< LCD PAL14: R14_0 Position           */
+#define LCD_PAL14_R14_0_Msk                                   (0x1fUL << LCD_PAL14_R14_0_Pos)                           /*!< LCD PAL14: R14_0 Mask               */
+#define LCD_PAL14_G14_0_Pos                                   21                                                        /*!< LCD PAL14: G14_0 Position           */
+#define LCD_PAL14_G14_0_Msk                                   (0x1fUL << LCD_PAL14_G14_0_Pos)                           /*!< LCD PAL14: G14_0 Mask               */
+#define LCD_PAL14_B14_0_Pos                                   26                                                        /*!< LCD PAL14: B14_0 Position           */
+#define LCD_PAL14_B14_0_Msk                                   (0x1fUL << LCD_PAL14_B14_0_Pos)                           /*!< LCD PAL14: B14_0 Mask               */
+#define LCD_PAL14_I1_Pos                                      31                                                        /*!< LCD PAL14: I1 Position              */
+#define LCD_PAL14_I1_Msk                                      (0x01UL << LCD_PAL14_I1_Pos)                              /*!< LCD PAL14: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL15  -------------------------------------------
+#define LCD_PAL15_R04_0_Pos                                   0                                                         /*!< LCD PAL15: R04_0 Position           */
+#define LCD_PAL15_R04_0_Msk                                   (0x1fUL << LCD_PAL15_R04_0_Pos)                           /*!< LCD PAL15: R04_0 Mask               */
+#define LCD_PAL15_G04_0_Pos                                   5                                                         /*!< LCD PAL15: G04_0 Position           */
+#define LCD_PAL15_G04_0_Msk                                   (0x1fUL << LCD_PAL15_G04_0_Pos)                           /*!< LCD PAL15: G04_0 Mask               */
+#define LCD_PAL15_B04_0_Pos                                   10                                                        /*!< LCD PAL15: B04_0 Position           */
+#define LCD_PAL15_B04_0_Msk                                   (0x1fUL << LCD_PAL15_B04_0_Pos)                           /*!< LCD PAL15: B04_0 Mask               */
+#define LCD_PAL15_I0_Pos                                      15                                                        /*!< LCD PAL15: I0 Position              */
+#define LCD_PAL15_I0_Msk                                      (0x01UL << LCD_PAL15_I0_Pos)                              /*!< LCD PAL15: I0 Mask                  */
+#define LCD_PAL15_R14_0_Pos                                   16                                                        /*!< LCD PAL15: R14_0 Position           */
+#define LCD_PAL15_R14_0_Msk                                   (0x1fUL << LCD_PAL15_R14_0_Pos)                           /*!< LCD PAL15: R14_0 Mask               */
+#define LCD_PAL15_G14_0_Pos                                   21                                                        /*!< LCD PAL15: G14_0 Position           */
+#define LCD_PAL15_G14_0_Msk                                   (0x1fUL << LCD_PAL15_G14_0_Pos)                           /*!< LCD PAL15: G14_0 Mask               */
+#define LCD_PAL15_B14_0_Pos                                   26                                                        /*!< LCD PAL15: B14_0 Position           */
+#define LCD_PAL15_B14_0_Msk                                   (0x1fUL << LCD_PAL15_B14_0_Pos)                           /*!< LCD PAL15: B14_0 Mask               */
+#define LCD_PAL15_I1_Pos                                      31                                                        /*!< LCD PAL15: I1 Position              */
+#define LCD_PAL15_I1_Msk                                      (0x01UL << LCD_PAL15_I1_Pos)                              /*!< LCD PAL15: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL16  -------------------------------------------
+#define LCD_PAL16_R04_0_Pos                                   0                                                         /*!< LCD PAL16: R04_0 Position           */
+#define LCD_PAL16_R04_0_Msk                                   (0x1fUL << LCD_PAL16_R04_0_Pos)                           /*!< LCD PAL16: R04_0 Mask               */
+#define LCD_PAL16_G04_0_Pos                                   5                                                         /*!< LCD PAL16: G04_0 Position           */
+#define LCD_PAL16_G04_0_Msk                                   (0x1fUL << LCD_PAL16_G04_0_Pos)                           /*!< LCD PAL16: G04_0 Mask               */
+#define LCD_PAL16_B04_0_Pos                                   10                                                        /*!< LCD PAL16: B04_0 Position           */
+#define LCD_PAL16_B04_0_Msk                                   (0x1fUL << LCD_PAL16_B04_0_Pos)                           /*!< LCD PAL16: B04_0 Mask               */
+#define LCD_PAL16_I0_Pos                                      15                                                        /*!< LCD PAL16: I0 Position              */
+#define LCD_PAL16_I0_Msk                                      (0x01UL << LCD_PAL16_I0_Pos)                              /*!< LCD PAL16: I0 Mask                  */
+#define LCD_PAL16_R14_0_Pos                                   16                                                        /*!< LCD PAL16: R14_0 Position           */
+#define LCD_PAL16_R14_0_Msk                                   (0x1fUL << LCD_PAL16_R14_0_Pos)                           /*!< LCD PAL16: R14_0 Mask               */
+#define LCD_PAL16_G14_0_Pos                                   21                                                        /*!< LCD PAL16: G14_0 Position           */
+#define LCD_PAL16_G14_0_Msk                                   (0x1fUL << LCD_PAL16_G14_0_Pos)                           /*!< LCD PAL16: G14_0 Mask               */
+#define LCD_PAL16_B14_0_Pos                                   26                                                        /*!< LCD PAL16: B14_0 Position           */
+#define LCD_PAL16_B14_0_Msk                                   (0x1fUL << LCD_PAL16_B14_0_Pos)                           /*!< LCD PAL16: B14_0 Mask               */
+#define LCD_PAL16_I1_Pos                                      31                                                        /*!< LCD PAL16: I1 Position              */
+#define LCD_PAL16_I1_Msk                                      (0x01UL << LCD_PAL16_I1_Pos)                              /*!< LCD PAL16: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL17  -------------------------------------------
+#define LCD_PAL17_R04_0_Pos                                   0                                                         /*!< LCD PAL17: R04_0 Position           */
+#define LCD_PAL17_R04_0_Msk                                   (0x1fUL << LCD_PAL17_R04_0_Pos)                           /*!< LCD PAL17: R04_0 Mask               */
+#define LCD_PAL17_G04_0_Pos                                   5                                                         /*!< LCD PAL17: G04_0 Position           */
+#define LCD_PAL17_G04_0_Msk                                   (0x1fUL << LCD_PAL17_G04_0_Pos)                           /*!< LCD PAL17: G04_0 Mask               */
+#define LCD_PAL17_B04_0_Pos                                   10                                                        /*!< LCD PAL17: B04_0 Position           */
+#define LCD_PAL17_B04_0_Msk                                   (0x1fUL << LCD_PAL17_B04_0_Pos)                           /*!< LCD PAL17: B04_0 Mask               */
+#define LCD_PAL17_I0_Pos                                      15                                                        /*!< LCD PAL17: I0 Position              */
+#define LCD_PAL17_I0_Msk                                      (0x01UL << LCD_PAL17_I0_Pos)                              /*!< LCD PAL17: I0 Mask                  */
+#define LCD_PAL17_R14_0_Pos                                   16                                                        /*!< LCD PAL17: R14_0 Position           */
+#define LCD_PAL17_R14_0_Msk                                   (0x1fUL << LCD_PAL17_R14_0_Pos)                           /*!< LCD PAL17: R14_0 Mask               */
+#define LCD_PAL17_G14_0_Pos                                   21                                                        /*!< LCD PAL17: G14_0 Position           */
+#define LCD_PAL17_G14_0_Msk                                   (0x1fUL << LCD_PAL17_G14_0_Pos)                           /*!< LCD PAL17: G14_0 Mask               */
+#define LCD_PAL17_B14_0_Pos                                   26                                                        /*!< LCD PAL17: B14_0 Position           */
+#define LCD_PAL17_B14_0_Msk                                   (0x1fUL << LCD_PAL17_B14_0_Pos)                           /*!< LCD PAL17: B14_0 Mask               */
+#define LCD_PAL17_I1_Pos                                      31                                                        /*!< LCD PAL17: I1 Position              */
+#define LCD_PAL17_I1_Msk                                      (0x01UL << LCD_PAL17_I1_Pos)                              /*!< LCD PAL17: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL18  -------------------------------------------
+#define LCD_PAL18_R04_0_Pos                                   0                                                         /*!< LCD PAL18: R04_0 Position           */
+#define LCD_PAL18_R04_0_Msk                                   (0x1fUL << LCD_PAL18_R04_0_Pos)                           /*!< LCD PAL18: R04_0 Mask               */
+#define LCD_PAL18_G04_0_Pos                                   5                                                         /*!< LCD PAL18: G04_0 Position           */
+#define LCD_PAL18_G04_0_Msk                                   (0x1fUL << LCD_PAL18_G04_0_Pos)                           /*!< LCD PAL18: G04_0 Mask               */
+#define LCD_PAL18_B04_0_Pos                                   10                                                        /*!< LCD PAL18: B04_0 Position           */
+#define LCD_PAL18_B04_0_Msk                                   (0x1fUL << LCD_PAL18_B04_0_Pos)                           /*!< LCD PAL18: B04_0 Mask               */
+#define LCD_PAL18_I0_Pos                                      15                                                        /*!< LCD PAL18: I0 Position              */
+#define LCD_PAL18_I0_Msk                                      (0x01UL << LCD_PAL18_I0_Pos)                              /*!< LCD PAL18: I0 Mask                  */
+#define LCD_PAL18_R14_0_Pos                                   16                                                        /*!< LCD PAL18: R14_0 Position           */
+#define LCD_PAL18_R14_0_Msk                                   (0x1fUL << LCD_PAL18_R14_0_Pos)                           /*!< LCD PAL18: R14_0 Mask               */
+#define LCD_PAL18_G14_0_Pos                                   21                                                        /*!< LCD PAL18: G14_0 Position           */
+#define LCD_PAL18_G14_0_Msk                                   (0x1fUL << LCD_PAL18_G14_0_Pos)                           /*!< LCD PAL18: G14_0 Mask               */
+#define LCD_PAL18_B14_0_Pos                                   26                                                        /*!< LCD PAL18: B14_0 Position           */
+#define LCD_PAL18_B14_0_Msk                                   (0x1fUL << LCD_PAL18_B14_0_Pos)                           /*!< LCD PAL18: B14_0 Mask               */
+#define LCD_PAL18_I1_Pos                                      31                                                        /*!< LCD PAL18: I1 Position              */
+#define LCD_PAL18_I1_Msk                                      (0x01UL << LCD_PAL18_I1_Pos)                              /*!< LCD PAL18: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL19  -------------------------------------------
+#define LCD_PAL19_R04_0_Pos                                   0                                                         /*!< LCD PAL19: R04_0 Position           */
+#define LCD_PAL19_R04_0_Msk                                   (0x1fUL << LCD_PAL19_R04_0_Pos)                           /*!< LCD PAL19: R04_0 Mask               */
+#define LCD_PAL19_G04_0_Pos                                   5                                                         /*!< LCD PAL19: G04_0 Position           */
+#define LCD_PAL19_G04_0_Msk                                   (0x1fUL << LCD_PAL19_G04_0_Pos)                           /*!< LCD PAL19: G04_0 Mask               */
+#define LCD_PAL19_B04_0_Pos                                   10                                                        /*!< LCD PAL19: B04_0 Position           */
+#define LCD_PAL19_B04_0_Msk                                   (0x1fUL << LCD_PAL19_B04_0_Pos)                           /*!< LCD PAL19: B04_0 Mask               */
+#define LCD_PAL19_I0_Pos                                      15                                                        /*!< LCD PAL19: I0 Position              */
+#define LCD_PAL19_I0_Msk                                      (0x01UL << LCD_PAL19_I0_Pos)                              /*!< LCD PAL19: I0 Mask                  */
+#define LCD_PAL19_R14_0_Pos                                   16                                                        /*!< LCD PAL19: R14_0 Position           */
+#define LCD_PAL19_R14_0_Msk                                   (0x1fUL << LCD_PAL19_R14_0_Pos)                           /*!< LCD PAL19: R14_0 Mask               */
+#define LCD_PAL19_G14_0_Pos                                   21                                                        /*!< LCD PAL19: G14_0 Position           */
+#define LCD_PAL19_G14_0_Msk                                   (0x1fUL << LCD_PAL19_G14_0_Pos)                           /*!< LCD PAL19: G14_0 Mask               */
+#define LCD_PAL19_B14_0_Pos                                   26                                                        /*!< LCD PAL19: B14_0 Position           */
+#define LCD_PAL19_B14_0_Msk                                   (0x1fUL << LCD_PAL19_B14_0_Pos)                           /*!< LCD PAL19: B14_0 Mask               */
+#define LCD_PAL19_I1_Pos                                      31                                                        /*!< LCD PAL19: I1 Position              */
+#define LCD_PAL19_I1_Msk                                      (0x01UL << LCD_PAL19_I1_Pos)                              /*!< LCD PAL19: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL20  -------------------------------------------
+#define LCD_PAL20_R04_0_Pos                                   0                                                         /*!< LCD PAL20: R04_0 Position           */
+#define LCD_PAL20_R04_0_Msk                                   (0x1fUL << LCD_PAL20_R04_0_Pos)                           /*!< LCD PAL20: R04_0 Mask               */
+#define LCD_PAL20_G04_0_Pos                                   5                                                         /*!< LCD PAL20: G04_0 Position           */
+#define LCD_PAL20_G04_0_Msk                                   (0x1fUL << LCD_PAL20_G04_0_Pos)                           /*!< LCD PAL20: G04_0 Mask               */
+#define LCD_PAL20_B04_0_Pos                                   10                                                        /*!< LCD PAL20: B04_0 Position           */
+#define LCD_PAL20_B04_0_Msk                                   (0x1fUL << LCD_PAL20_B04_0_Pos)                           /*!< LCD PAL20: B04_0 Mask               */
+#define LCD_PAL20_I0_Pos                                      15                                                        /*!< LCD PAL20: I0 Position              */
+#define LCD_PAL20_I0_Msk                                      (0x01UL << LCD_PAL20_I0_Pos)                              /*!< LCD PAL20: I0 Mask                  */
+#define LCD_PAL20_R14_0_Pos                                   16                                                        /*!< LCD PAL20: R14_0 Position           */
+#define LCD_PAL20_R14_0_Msk                                   (0x1fUL << LCD_PAL20_R14_0_Pos)                           /*!< LCD PAL20: R14_0 Mask               */
+#define LCD_PAL20_G14_0_Pos                                   21                                                        /*!< LCD PAL20: G14_0 Position           */
+#define LCD_PAL20_G14_0_Msk                                   (0x1fUL << LCD_PAL20_G14_0_Pos)                           /*!< LCD PAL20: G14_0 Mask               */
+#define LCD_PAL20_B14_0_Pos                                   26                                                        /*!< LCD PAL20: B14_0 Position           */
+#define LCD_PAL20_B14_0_Msk                                   (0x1fUL << LCD_PAL20_B14_0_Pos)                           /*!< LCD PAL20: B14_0 Mask               */
+#define LCD_PAL20_I1_Pos                                      31                                                        /*!< LCD PAL20: I1 Position              */
+#define LCD_PAL20_I1_Msk                                      (0x01UL << LCD_PAL20_I1_Pos)                              /*!< LCD PAL20: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL21  -------------------------------------------
+#define LCD_PAL21_R04_0_Pos                                   0                                                         /*!< LCD PAL21: R04_0 Position           */
+#define LCD_PAL21_R04_0_Msk                                   (0x1fUL << LCD_PAL21_R04_0_Pos)                           /*!< LCD PAL21: R04_0 Mask               */
+#define LCD_PAL21_G04_0_Pos                                   5                                                         /*!< LCD PAL21: G04_0 Position           */
+#define LCD_PAL21_G04_0_Msk                                   (0x1fUL << LCD_PAL21_G04_0_Pos)                           /*!< LCD PAL21: G04_0 Mask               */
+#define LCD_PAL21_B04_0_Pos                                   10                                                        /*!< LCD PAL21: B04_0 Position           */
+#define LCD_PAL21_B04_0_Msk                                   (0x1fUL << LCD_PAL21_B04_0_Pos)                           /*!< LCD PAL21: B04_0 Mask               */
+#define LCD_PAL21_I0_Pos                                      15                                                        /*!< LCD PAL21: I0 Position              */
+#define LCD_PAL21_I0_Msk                                      (0x01UL << LCD_PAL21_I0_Pos)                              /*!< LCD PAL21: I0 Mask                  */
+#define LCD_PAL21_R14_0_Pos                                   16                                                        /*!< LCD PAL21: R14_0 Position           */
+#define LCD_PAL21_R14_0_Msk                                   (0x1fUL << LCD_PAL21_R14_0_Pos)                           /*!< LCD PAL21: R14_0 Mask               */
+#define LCD_PAL21_G14_0_Pos                                   21                                                        /*!< LCD PAL21: G14_0 Position           */
+#define LCD_PAL21_G14_0_Msk                                   (0x1fUL << LCD_PAL21_G14_0_Pos)                           /*!< LCD PAL21: G14_0 Mask               */
+#define LCD_PAL21_B14_0_Pos                                   26                                                        /*!< LCD PAL21: B14_0 Position           */
+#define LCD_PAL21_B14_0_Msk                                   (0x1fUL << LCD_PAL21_B14_0_Pos)                           /*!< LCD PAL21: B14_0 Mask               */
+#define LCD_PAL21_I1_Pos                                      31                                                        /*!< LCD PAL21: I1 Position              */
+#define LCD_PAL21_I1_Msk                                      (0x01UL << LCD_PAL21_I1_Pos)                              /*!< LCD PAL21: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL22  -------------------------------------------
+#define LCD_PAL22_R04_0_Pos                                   0                                                         /*!< LCD PAL22: R04_0 Position           */
+#define LCD_PAL22_R04_0_Msk                                   (0x1fUL << LCD_PAL22_R04_0_Pos)                           /*!< LCD PAL22: R04_0 Mask               */
+#define LCD_PAL22_G04_0_Pos                                   5                                                         /*!< LCD PAL22: G04_0 Position           */
+#define LCD_PAL22_G04_0_Msk                                   (0x1fUL << LCD_PAL22_G04_0_Pos)                           /*!< LCD PAL22: G04_0 Mask               */
+#define LCD_PAL22_B04_0_Pos                                   10                                                        /*!< LCD PAL22: B04_0 Position           */
+#define LCD_PAL22_B04_0_Msk                                   (0x1fUL << LCD_PAL22_B04_0_Pos)                           /*!< LCD PAL22: B04_0 Mask               */
+#define LCD_PAL22_I0_Pos                                      15                                                        /*!< LCD PAL22: I0 Position              */
+#define LCD_PAL22_I0_Msk                                      (0x01UL << LCD_PAL22_I0_Pos)                              /*!< LCD PAL22: I0 Mask                  */
+#define LCD_PAL22_R14_0_Pos                                   16                                                        /*!< LCD PAL22: R14_0 Position           */
+#define LCD_PAL22_R14_0_Msk                                   (0x1fUL << LCD_PAL22_R14_0_Pos)                           /*!< LCD PAL22: R14_0 Mask               */
+#define LCD_PAL22_G14_0_Pos                                   21                                                        /*!< LCD PAL22: G14_0 Position           */
+#define LCD_PAL22_G14_0_Msk                                   (0x1fUL << LCD_PAL22_G14_0_Pos)                           /*!< LCD PAL22: G14_0 Mask               */
+#define LCD_PAL22_B14_0_Pos                                   26                                                        /*!< LCD PAL22: B14_0 Position           */
+#define LCD_PAL22_B14_0_Msk                                   (0x1fUL << LCD_PAL22_B14_0_Pos)                           /*!< LCD PAL22: B14_0 Mask               */
+#define LCD_PAL22_I1_Pos                                      31                                                        /*!< LCD PAL22: I1 Position              */
+#define LCD_PAL22_I1_Msk                                      (0x01UL << LCD_PAL22_I1_Pos)                              /*!< LCD PAL22: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL23  -------------------------------------------
+#define LCD_PAL23_R04_0_Pos                                   0                                                         /*!< LCD PAL23: R04_0 Position           */
+#define LCD_PAL23_R04_0_Msk                                   (0x1fUL << LCD_PAL23_R04_0_Pos)                           /*!< LCD PAL23: R04_0 Mask               */
+#define LCD_PAL23_G04_0_Pos                                   5                                                         /*!< LCD PAL23: G04_0 Position           */
+#define LCD_PAL23_G04_0_Msk                                   (0x1fUL << LCD_PAL23_G04_0_Pos)                           /*!< LCD PAL23: G04_0 Mask               */
+#define LCD_PAL23_B04_0_Pos                                   10                                                        /*!< LCD PAL23: B04_0 Position           */
+#define LCD_PAL23_B04_0_Msk                                   (0x1fUL << LCD_PAL23_B04_0_Pos)                           /*!< LCD PAL23: B04_0 Mask               */
+#define LCD_PAL23_I0_Pos                                      15                                                        /*!< LCD PAL23: I0 Position              */
+#define LCD_PAL23_I0_Msk                                      (0x01UL << LCD_PAL23_I0_Pos)                              /*!< LCD PAL23: I0 Mask                  */
+#define LCD_PAL23_R14_0_Pos                                   16                                                        /*!< LCD PAL23: R14_0 Position           */
+#define LCD_PAL23_R14_0_Msk                                   (0x1fUL << LCD_PAL23_R14_0_Pos)                           /*!< LCD PAL23: R14_0 Mask               */
+#define LCD_PAL23_G14_0_Pos                                   21                                                        /*!< LCD PAL23: G14_0 Position           */
+#define LCD_PAL23_G14_0_Msk                                   (0x1fUL << LCD_PAL23_G14_0_Pos)                           /*!< LCD PAL23: G14_0 Mask               */
+#define LCD_PAL23_B14_0_Pos                                   26                                                        /*!< LCD PAL23: B14_0 Position           */
+#define LCD_PAL23_B14_0_Msk                                   (0x1fUL << LCD_PAL23_B14_0_Pos)                           /*!< LCD PAL23: B14_0 Mask               */
+#define LCD_PAL23_I1_Pos                                      31                                                        /*!< LCD PAL23: I1 Position              */
+#define LCD_PAL23_I1_Msk                                      (0x01UL << LCD_PAL23_I1_Pos)                              /*!< LCD PAL23: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL24  -------------------------------------------
+#define LCD_PAL24_R04_0_Pos                                   0                                                         /*!< LCD PAL24: R04_0 Position           */
+#define LCD_PAL24_R04_0_Msk                                   (0x1fUL << LCD_PAL24_R04_0_Pos)                           /*!< LCD PAL24: R04_0 Mask               */
+#define LCD_PAL24_G04_0_Pos                                   5                                                         /*!< LCD PAL24: G04_0 Position           */
+#define LCD_PAL24_G04_0_Msk                                   (0x1fUL << LCD_PAL24_G04_0_Pos)                           /*!< LCD PAL24: G04_0 Mask               */
+#define LCD_PAL24_B04_0_Pos                                   10                                                        /*!< LCD PAL24: B04_0 Position           */
+#define LCD_PAL24_B04_0_Msk                                   (0x1fUL << LCD_PAL24_B04_0_Pos)                           /*!< LCD PAL24: B04_0 Mask               */
+#define LCD_PAL24_I0_Pos                                      15                                                        /*!< LCD PAL24: I0 Position              */
+#define LCD_PAL24_I0_Msk                                      (0x01UL << LCD_PAL24_I0_Pos)                              /*!< LCD PAL24: I0 Mask                  */
+#define LCD_PAL24_R14_0_Pos                                   16                                                        /*!< LCD PAL24: R14_0 Position           */
+#define LCD_PAL24_R14_0_Msk                                   (0x1fUL << LCD_PAL24_R14_0_Pos)                           /*!< LCD PAL24: R14_0 Mask               */
+#define LCD_PAL24_G14_0_Pos                                   21                                                        /*!< LCD PAL24: G14_0 Position           */
+#define LCD_PAL24_G14_0_Msk                                   (0x1fUL << LCD_PAL24_G14_0_Pos)                           /*!< LCD PAL24: G14_0 Mask               */
+#define LCD_PAL24_B14_0_Pos                                   26                                                        /*!< LCD PAL24: B14_0 Position           */
+#define LCD_PAL24_B14_0_Msk                                   (0x1fUL << LCD_PAL24_B14_0_Pos)                           /*!< LCD PAL24: B14_0 Mask               */
+#define LCD_PAL24_I1_Pos                                      31                                                        /*!< LCD PAL24: I1 Position              */
+#define LCD_PAL24_I1_Msk                                      (0x01UL << LCD_PAL24_I1_Pos)                              /*!< LCD PAL24: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL25  -------------------------------------------
+#define LCD_PAL25_R04_0_Pos                                   0                                                         /*!< LCD PAL25: R04_0 Position           */
+#define LCD_PAL25_R04_0_Msk                                   (0x1fUL << LCD_PAL25_R04_0_Pos)                           /*!< LCD PAL25: R04_0 Mask               */
+#define LCD_PAL25_G04_0_Pos                                   5                                                         /*!< LCD PAL25: G04_0 Position           */
+#define LCD_PAL25_G04_0_Msk                                   (0x1fUL << LCD_PAL25_G04_0_Pos)                           /*!< LCD PAL25: G04_0 Mask               */
+#define LCD_PAL25_B04_0_Pos                                   10                                                        /*!< LCD PAL25: B04_0 Position           */
+#define LCD_PAL25_B04_0_Msk                                   (0x1fUL << LCD_PAL25_B04_0_Pos)                           /*!< LCD PAL25: B04_0 Mask               */
+#define LCD_PAL25_I0_Pos                                      15                                                        /*!< LCD PAL25: I0 Position              */
+#define LCD_PAL25_I0_Msk                                      (0x01UL << LCD_PAL25_I0_Pos)                              /*!< LCD PAL25: I0 Mask                  */
+#define LCD_PAL25_R14_0_Pos                                   16                                                        /*!< LCD PAL25: R14_0 Position           */
+#define LCD_PAL25_R14_0_Msk                                   (0x1fUL << LCD_PAL25_R14_0_Pos)                           /*!< LCD PAL25: R14_0 Mask               */
+#define LCD_PAL25_G14_0_Pos                                   21                                                        /*!< LCD PAL25: G14_0 Position           */
+#define LCD_PAL25_G14_0_Msk                                   (0x1fUL << LCD_PAL25_G14_0_Pos)                           /*!< LCD PAL25: G14_0 Mask               */
+#define LCD_PAL25_B14_0_Pos                                   26                                                        /*!< LCD PAL25: B14_0 Position           */
+#define LCD_PAL25_B14_0_Msk                                   (0x1fUL << LCD_PAL25_B14_0_Pos)                           /*!< LCD PAL25: B14_0 Mask               */
+#define LCD_PAL25_I1_Pos                                      31                                                        /*!< LCD PAL25: I1 Position              */
+#define LCD_PAL25_I1_Msk                                      (0x01UL << LCD_PAL25_I1_Pos)                              /*!< LCD PAL25: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL26  -------------------------------------------
+#define LCD_PAL26_R04_0_Pos                                   0                                                         /*!< LCD PAL26: R04_0 Position           */
+#define LCD_PAL26_R04_0_Msk                                   (0x1fUL << LCD_PAL26_R04_0_Pos)                           /*!< LCD PAL26: R04_0 Mask               */
+#define LCD_PAL26_G04_0_Pos                                   5                                                         /*!< LCD PAL26: G04_0 Position           */
+#define LCD_PAL26_G04_0_Msk                                   (0x1fUL << LCD_PAL26_G04_0_Pos)                           /*!< LCD PAL26: G04_0 Mask               */
+#define LCD_PAL26_B04_0_Pos                                   10                                                        /*!< LCD PAL26: B04_0 Position           */
+#define LCD_PAL26_B04_0_Msk                                   (0x1fUL << LCD_PAL26_B04_0_Pos)                           /*!< LCD PAL26: B04_0 Mask               */
+#define LCD_PAL26_I0_Pos                                      15                                                        /*!< LCD PAL26: I0 Position              */
+#define LCD_PAL26_I0_Msk                                      (0x01UL << LCD_PAL26_I0_Pos)                              /*!< LCD PAL26: I0 Mask                  */
+#define LCD_PAL26_R14_0_Pos                                   16                                                        /*!< LCD PAL26: R14_0 Position           */
+#define LCD_PAL26_R14_0_Msk                                   (0x1fUL << LCD_PAL26_R14_0_Pos)                           /*!< LCD PAL26: R14_0 Mask               */
+#define LCD_PAL26_G14_0_Pos                                   21                                                        /*!< LCD PAL26: G14_0 Position           */
+#define LCD_PAL26_G14_0_Msk                                   (0x1fUL << LCD_PAL26_G14_0_Pos)                           /*!< LCD PAL26: G14_0 Mask               */
+#define LCD_PAL26_B14_0_Pos                                   26                                                        /*!< LCD PAL26: B14_0 Position           */
+#define LCD_PAL26_B14_0_Msk                                   (0x1fUL << LCD_PAL26_B14_0_Pos)                           /*!< LCD PAL26: B14_0 Mask               */
+#define LCD_PAL26_I1_Pos                                      31                                                        /*!< LCD PAL26: I1 Position              */
+#define LCD_PAL26_I1_Msk                                      (0x01UL << LCD_PAL26_I1_Pos)                              /*!< LCD PAL26: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL27  -------------------------------------------
+#define LCD_PAL27_R04_0_Pos                                   0                                                         /*!< LCD PAL27: R04_0 Position           */
+#define LCD_PAL27_R04_0_Msk                                   (0x1fUL << LCD_PAL27_R04_0_Pos)                           /*!< LCD PAL27: R04_0 Mask               */
+#define LCD_PAL27_G04_0_Pos                                   5                                                         /*!< LCD PAL27: G04_0 Position           */
+#define LCD_PAL27_G04_0_Msk                                   (0x1fUL << LCD_PAL27_G04_0_Pos)                           /*!< LCD PAL27: G04_0 Mask               */
+#define LCD_PAL27_B04_0_Pos                                   10                                                        /*!< LCD PAL27: B04_0 Position           */
+#define LCD_PAL27_B04_0_Msk                                   (0x1fUL << LCD_PAL27_B04_0_Pos)                           /*!< LCD PAL27: B04_0 Mask               */
+#define LCD_PAL27_I0_Pos                                      15                                                        /*!< LCD PAL27: I0 Position              */
+#define LCD_PAL27_I0_Msk                                      (0x01UL << LCD_PAL27_I0_Pos)                              /*!< LCD PAL27: I0 Mask                  */
+#define LCD_PAL27_R14_0_Pos                                   16                                                        /*!< LCD PAL27: R14_0 Position           */
+#define LCD_PAL27_R14_0_Msk                                   (0x1fUL << LCD_PAL27_R14_0_Pos)                           /*!< LCD PAL27: R14_0 Mask               */
+#define LCD_PAL27_G14_0_Pos                                   21                                                        /*!< LCD PAL27: G14_0 Position           */
+#define LCD_PAL27_G14_0_Msk                                   (0x1fUL << LCD_PAL27_G14_0_Pos)                           /*!< LCD PAL27: G14_0 Mask               */
+#define LCD_PAL27_B14_0_Pos                                   26                                                        /*!< LCD PAL27: B14_0 Position           */
+#define LCD_PAL27_B14_0_Msk                                   (0x1fUL << LCD_PAL27_B14_0_Pos)                           /*!< LCD PAL27: B14_0 Mask               */
+#define LCD_PAL27_I1_Pos                                      31                                                        /*!< LCD PAL27: I1 Position              */
+#define LCD_PAL27_I1_Msk                                      (0x01UL << LCD_PAL27_I1_Pos)                              /*!< LCD PAL27: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL28  -------------------------------------------
+#define LCD_PAL28_R04_0_Pos                                   0                                                         /*!< LCD PAL28: R04_0 Position           */
+#define LCD_PAL28_R04_0_Msk                                   (0x1fUL << LCD_PAL28_R04_0_Pos)                           /*!< LCD PAL28: R04_0 Mask               */
+#define LCD_PAL28_G04_0_Pos                                   5                                                         /*!< LCD PAL28: G04_0 Position           */
+#define LCD_PAL28_G04_0_Msk                                   (0x1fUL << LCD_PAL28_G04_0_Pos)                           /*!< LCD PAL28: G04_0 Mask               */
+#define LCD_PAL28_B04_0_Pos                                   10                                                        /*!< LCD PAL28: B04_0 Position           */
+#define LCD_PAL28_B04_0_Msk                                   (0x1fUL << LCD_PAL28_B04_0_Pos)                           /*!< LCD PAL28: B04_0 Mask               */
+#define LCD_PAL28_I0_Pos                                      15                                                        /*!< LCD PAL28: I0 Position              */
+#define LCD_PAL28_I0_Msk                                      (0x01UL << LCD_PAL28_I0_Pos)                              /*!< LCD PAL28: I0 Mask                  */
+#define LCD_PAL28_R14_0_Pos                                   16                                                        /*!< LCD PAL28: R14_0 Position           */
+#define LCD_PAL28_R14_0_Msk                                   (0x1fUL << LCD_PAL28_R14_0_Pos)                           /*!< LCD PAL28: R14_0 Mask               */
+#define LCD_PAL28_G14_0_Pos                                   21                                                        /*!< LCD PAL28: G14_0 Position           */
+#define LCD_PAL28_G14_0_Msk                                   (0x1fUL << LCD_PAL28_G14_0_Pos)                           /*!< LCD PAL28: G14_0 Mask               */
+#define LCD_PAL28_B14_0_Pos                                   26                                                        /*!< LCD PAL28: B14_0 Position           */
+#define LCD_PAL28_B14_0_Msk                                   (0x1fUL << LCD_PAL28_B14_0_Pos)                           /*!< LCD PAL28: B14_0 Mask               */
+#define LCD_PAL28_I1_Pos                                      31                                                        /*!< LCD PAL28: I1 Position              */
+#define LCD_PAL28_I1_Msk                                      (0x01UL << LCD_PAL28_I1_Pos)                              /*!< LCD PAL28: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL29  -------------------------------------------
+#define LCD_PAL29_R04_0_Pos                                   0                                                         /*!< LCD PAL29: R04_0 Position           */
+#define LCD_PAL29_R04_0_Msk                                   (0x1fUL << LCD_PAL29_R04_0_Pos)                           /*!< LCD PAL29: R04_0 Mask               */
+#define LCD_PAL29_G04_0_Pos                                   5                                                         /*!< LCD PAL29: G04_0 Position           */
+#define LCD_PAL29_G04_0_Msk                                   (0x1fUL << LCD_PAL29_G04_0_Pos)                           /*!< LCD PAL29: G04_0 Mask               */
+#define LCD_PAL29_B04_0_Pos                                   10                                                        /*!< LCD PAL29: B04_0 Position           */
+#define LCD_PAL29_B04_0_Msk                                   (0x1fUL << LCD_PAL29_B04_0_Pos)                           /*!< LCD PAL29: B04_0 Mask               */
+#define LCD_PAL29_I0_Pos                                      15                                                        /*!< LCD PAL29: I0 Position              */
+#define LCD_PAL29_I0_Msk                                      (0x01UL << LCD_PAL29_I0_Pos)                              /*!< LCD PAL29: I0 Mask                  */
+#define LCD_PAL29_R14_0_Pos                                   16                                                        /*!< LCD PAL29: R14_0 Position           */
+#define LCD_PAL29_R14_0_Msk                                   (0x1fUL << LCD_PAL29_R14_0_Pos)                           /*!< LCD PAL29: R14_0 Mask               */
+#define LCD_PAL29_G14_0_Pos                                   21                                                        /*!< LCD PAL29: G14_0 Position           */
+#define LCD_PAL29_G14_0_Msk                                   (0x1fUL << LCD_PAL29_G14_0_Pos)                           /*!< LCD PAL29: G14_0 Mask               */
+#define LCD_PAL29_B14_0_Pos                                   26                                                        /*!< LCD PAL29: B14_0 Position           */
+#define LCD_PAL29_B14_0_Msk                                   (0x1fUL << LCD_PAL29_B14_0_Pos)                           /*!< LCD PAL29: B14_0 Mask               */
+#define LCD_PAL29_I1_Pos                                      31                                                        /*!< LCD PAL29: I1 Position              */
+#define LCD_PAL29_I1_Msk                                      (0x01UL << LCD_PAL29_I1_Pos)                              /*!< LCD PAL29: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL30  -------------------------------------------
+#define LCD_PAL30_R04_0_Pos                                   0                                                         /*!< LCD PAL30: R04_0 Position           */
+#define LCD_PAL30_R04_0_Msk                                   (0x1fUL << LCD_PAL30_R04_0_Pos)                           /*!< LCD PAL30: R04_0 Mask               */
+#define LCD_PAL30_G04_0_Pos                                   5                                                         /*!< LCD PAL30: G04_0 Position           */
+#define LCD_PAL30_G04_0_Msk                                   (0x1fUL << LCD_PAL30_G04_0_Pos)                           /*!< LCD PAL30: G04_0 Mask               */
+#define LCD_PAL30_B04_0_Pos                                   10                                                        /*!< LCD PAL30: B04_0 Position           */
+#define LCD_PAL30_B04_0_Msk                                   (0x1fUL << LCD_PAL30_B04_0_Pos)                           /*!< LCD PAL30: B04_0 Mask               */
+#define LCD_PAL30_I0_Pos                                      15                                                        /*!< LCD PAL30: I0 Position              */
+#define LCD_PAL30_I0_Msk                                      (0x01UL << LCD_PAL30_I0_Pos)                              /*!< LCD PAL30: I0 Mask                  */
+#define LCD_PAL30_R14_0_Pos                                   16                                                        /*!< LCD PAL30: R14_0 Position           */
+#define LCD_PAL30_R14_0_Msk                                   (0x1fUL << LCD_PAL30_R14_0_Pos)                           /*!< LCD PAL30: R14_0 Mask               */
+#define LCD_PAL30_G14_0_Pos                                   21                                                        /*!< LCD PAL30: G14_0 Position           */
+#define LCD_PAL30_G14_0_Msk                                   (0x1fUL << LCD_PAL30_G14_0_Pos)                           /*!< LCD PAL30: G14_0 Mask               */
+#define LCD_PAL30_B14_0_Pos                                   26                                                        /*!< LCD PAL30: B14_0 Position           */
+#define LCD_PAL30_B14_0_Msk                                   (0x1fUL << LCD_PAL30_B14_0_Pos)                           /*!< LCD PAL30: B14_0 Mask               */
+#define LCD_PAL30_I1_Pos                                      31                                                        /*!< LCD PAL30: I1 Position              */
+#define LCD_PAL30_I1_Msk                                      (0x01UL << LCD_PAL30_I1_Pos)                              /*!< LCD PAL30: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL31  -------------------------------------------
+#define LCD_PAL31_R04_0_Pos                                   0                                                         /*!< LCD PAL31: R04_0 Position           */
+#define LCD_PAL31_R04_0_Msk                                   (0x1fUL << LCD_PAL31_R04_0_Pos)                           /*!< LCD PAL31: R04_0 Mask               */
+#define LCD_PAL31_G04_0_Pos                                   5                                                         /*!< LCD PAL31: G04_0 Position           */
+#define LCD_PAL31_G04_0_Msk                                   (0x1fUL << LCD_PAL31_G04_0_Pos)                           /*!< LCD PAL31: G04_0 Mask               */
+#define LCD_PAL31_B04_0_Pos                                   10                                                        /*!< LCD PAL31: B04_0 Position           */
+#define LCD_PAL31_B04_0_Msk                                   (0x1fUL << LCD_PAL31_B04_0_Pos)                           /*!< LCD PAL31: B04_0 Mask               */
+#define LCD_PAL31_I0_Pos                                      15                                                        /*!< LCD PAL31: I0 Position              */
+#define LCD_PAL31_I0_Msk                                      (0x01UL << LCD_PAL31_I0_Pos)                              /*!< LCD PAL31: I0 Mask                  */
+#define LCD_PAL31_R14_0_Pos                                   16                                                        /*!< LCD PAL31: R14_0 Position           */
+#define LCD_PAL31_R14_0_Msk                                   (0x1fUL << LCD_PAL31_R14_0_Pos)                           /*!< LCD PAL31: R14_0 Mask               */
+#define LCD_PAL31_G14_0_Pos                                   21                                                        /*!< LCD PAL31: G14_0 Position           */
+#define LCD_PAL31_G14_0_Msk                                   (0x1fUL << LCD_PAL31_G14_0_Pos)                           /*!< LCD PAL31: G14_0 Mask               */
+#define LCD_PAL31_B14_0_Pos                                   26                                                        /*!< LCD PAL31: B14_0 Position           */
+#define LCD_PAL31_B14_0_Msk                                   (0x1fUL << LCD_PAL31_B14_0_Pos)                           /*!< LCD PAL31: B14_0 Mask               */
+#define LCD_PAL31_I1_Pos                                      31                                                        /*!< LCD PAL31: I1 Position              */
+#define LCD_PAL31_I1_Msk                                      (0x01UL << LCD_PAL31_I1_Pos)                              /*!< LCD PAL31: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL32  -------------------------------------------
+#define LCD_PAL32_R04_0_Pos                                   0                                                         /*!< LCD PAL32: R04_0 Position           */
+#define LCD_PAL32_R04_0_Msk                                   (0x1fUL << LCD_PAL32_R04_0_Pos)                           /*!< LCD PAL32: R04_0 Mask               */
+#define LCD_PAL32_G04_0_Pos                                   5                                                         /*!< LCD PAL32: G04_0 Position           */
+#define LCD_PAL32_G04_0_Msk                                   (0x1fUL << LCD_PAL32_G04_0_Pos)                           /*!< LCD PAL32: G04_0 Mask               */
+#define LCD_PAL32_B04_0_Pos                                   10                                                        /*!< LCD PAL32: B04_0 Position           */
+#define LCD_PAL32_B04_0_Msk                                   (0x1fUL << LCD_PAL32_B04_0_Pos)                           /*!< LCD PAL32: B04_0 Mask               */
+#define LCD_PAL32_I0_Pos                                      15                                                        /*!< LCD PAL32: I0 Position              */
+#define LCD_PAL32_I0_Msk                                      (0x01UL << LCD_PAL32_I0_Pos)                              /*!< LCD PAL32: I0 Mask                  */
+#define LCD_PAL32_R14_0_Pos                                   16                                                        /*!< LCD PAL32: R14_0 Position           */
+#define LCD_PAL32_R14_0_Msk                                   (0x1fUL << LCD_PAL32_R14_0_Pos)                           /*!< LCD PAL32: R14_0 Mask               */
+#define LCD_PAL32_G14_0_Pos                                   21                                                        /*!< LCD PAL32: G14_0 Position           */
+#define LCD_PAL32_G14_0_Msk                                   (0x1fUL << LCD_PAL32_G14_0_Pos)                           /*!< LCD PAL32: G14_0 Mask               */
+#define LCD_PAL32_B14_0_Pos                                   26                                                        /*!< LCD PAL32: B14_0 Position           */
+#define LCD_PAL32_B14_0_Msk                                   (0x1fUL << LCD_PAL32_B14_0_Pos)                           /*!< LCD PAL32: B14_0 Mask               */
+#define LCD_PAL32_I1_Pos                                      31                                                        /*!< LCD PAL32: I1 Position              */
+#define LCD_PAL32_I1_Msk                                      (0x01UL << LCD_PAL32_I1_Pos)                              /*!< LCD PAL32: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL33  -------------------------------------------
+#define LCD_PAL33_R04_0_Pos                                   0                                                         /*!< LCD PAL33: R04_0 Position           */
+#define LCD_PAL33_R04_0_Msk                                   (0x1fUL << LCD_PAL33_R04_0_Pos)                           /*!< LCD PAL33: R04_0 Mask               */
+#define LCD_PAL33_G04_0_Pos                                   5                                                         /*!< LCD PAL33: G04_0 Position           */
+#define LCD_PAL33_G04_0_Msk                                   (0x1fUL << LCD_PAL33_G04_0_Pos)                           /*!< LCD PAL33: G04_0 Mask               */
+#define LCD_PAL33_B04_0_Pos                                   10                                                        /*!< LCD PAL33: B04_0 Position           */
+#define LCD_PAL33_B04_0_Msk                                   (0x1fUL << LCD_PAL33_B04_0_Pos)                           /*!< LCD PAL33: B04_0 Mask               */
+#define LCD_PAL33_I0_Pos                                      15                                                        /*!< LCD PAL33: I0 Position              */
+#define LCD_PAL33_I0_Msk                                      (0x01UL << LCD_PAL33_I0_Pos)                              /*!< LCD PAL33: I0 Mask                  */
+#define LCD_PAL33_R14_0_Pos                                   16                                                        /*!< LCD PAL33: R14_0 Position           */
+#define LCD_PAL33_R14_0_Msk                                   (0x1fUL << LCD_PAL33_R14_0_Pos)                           /*!< LCD PAL33: R14_0 Mask               */
+#define LCD_PAL33_G14_0_Pos                                   21                                                        /*!< LCD PAL33: G14_0 Position           */
+#define LCD_PAL33_G14_0_Msk                                   (0x1fUL << LCD_PAL33_G14_0_Pos)                           /*!< LCD PAL33: G14_0 Mask               */
+#define LCD_PAL33_B14_0_Pos                                   26                                                        /*!< LCD PAL33: B14_0 Position           */
+#define LCD_PAL33_B14_0_Msk                                   (0x1fUL << LCD_PAL33_B14_0_Pos)                           /*!< LCD PAL33: B14_0 Mask               */
+#define LCD_PAL33_I1_Pos                                      31                                                        /*!< LCD PAL33: I1 Position              */
+#define LCD_PAL33_I1_Msk                                      (0x01UL << LCD_PAL33_I1_Pos)                              /*!< LCD PAL33: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL34  -------------------------------------------
+#define LCD_PAL34_R04_0_Pos                                   0                                                         /*!< LCD PAL34: R04_0 Position           */
+#define LCD_PAL34_R04_0_Msk                                   (0x1fUL << LCD_PAL34_R04_0_Pos)                           /*!< LCD PAL34: R04_0 Mask               */
+#define LCD_PAL34_G04_0_Pos                                   5                                                         /*!< LCD PAL34: G04_0 Position           */
+#define LCD_PAL34_G04_0_Msk                                   (0x1fUL << LCD_PAL34_G04_0_Pos)                           /*!< LCD PAL34: G04_0 Mask               */
+#define LCD_PAL34_B04_0_Pos                                   10                                                        /*!< LCD PAL34: B04_0 Position           */
+#define LCD_PAL34_B04_0_Msk                                   (0x1fUL << LCD_PAL34_B04_0_Pos)                           /*!< LCD PAL34: B04_0 Mask               */
+#define LCD_PAL34_I0_Pos                                      15                                                        /*!< LCD PAL34: I0 Position              */
+#define LCD_PAL34_I0_Msk                                      (0x01UL << LCD_PAL34_I0_Pos)                              /*!< LCD PAL34: I0 Mask                  */
+#define LCD_PAL34_R14_0_Pos                                   16                                                        /*!< LCD PAL34: R14_0 Position           */
+#define LCD_PAL34_R14_0_Msk                                   (0x1fUL << LCD_PAL34_R14_0_Pos)                           /*!< LCD PAL34: R14_0 Mask               */
+#define LCD_PAL34_G14_0_Pos                                   21                                                        /*!< LCD PAL34: G14_0 Position           */
+#define LCD_PAL34_G14_0_Msk                                   (0x1fUL << LCD_PAL34_G14_0_Pos)                           /*!< LCD PAL34: G14_0 Mask               */
+#define LCD_PAL34_B14_0_Pos                                   26                                                        /*!< LCD PAL34: B14_0 Position           */
+#define LCD_PAL34_B14_0_Msk                                   (0x1fUL << LCD_PAL34_B14_0_Pos)                           /*!< LCD PAL34: B14_0 Mask               */
+#define LCD_PAL34_I1_Pos                                      31                                                        /*!< LCD PAL34: I1 Position              */
+#define LCD_PAL34_I1_Msk                                      (0x01UL << LCD_PAL34_I1_Pos)                              /*!< LCD PAL34: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL35  -------------------------------------------
+#define LCD_PAL35_R04_0_Pos                                   0                                                         /*!< LCD PAL35: R04_0 Position           */
+#define LCD_PAL35_R04_0_Msk                                   (0x1fUL << LCD_PAL35_R04_0_Pos)                           /*!< LCD PAL35: R04_0 Mask               */
+#define LCD_PAL35_G04_0_Pos                                   5                                                         /*!< LCD PAL35: G04_0 Position           */
+#define LCD_PAL35_G04_0_Msk                                   (0x1fUL << LCD_PAL35_G04_0_Pos)                           /*!< LCD PAL35: G04_0 Mask               */
+#define LCD_PAL35_B04_0_Pos                                   10                                                        /*!< LCD PAL35: B04_0 Position           */
+#define LCD_PAL35_B04_0_Msk                                   (0x1fUL << LCD_PAL35_B04_0_Pos)                           /*!< LCD PAL35: B04_0 Mask               */
+#define LCD_PAL35_I0_Pos                                      15                                                        /*!< LCD PAL35: I0 Position              */
+#define LCD_PAL35_I0_Msk                                      (0x01UL << LCD_PAL35_I0_Pos)                              /*!< LCD PAL35: I0 Mask                  */
+#define LCD_PAL35_R14_0_Pos                                   16                                                        /*!< LCD PAL35: R14_0 Position           */
+#define LCD_PAL35_R14_0_Msk                                   (0x1fUL << LCD_PAL35_R14_0_Pos)                           /*!< LCD PAL35: R14_0 Mask               */
+#define LCD_PAL35_G14_0_Pos                                   21                                                        /*!< LCD PAL35: G14_0 Position           */
+#define LCD_PAL35_G14_0_Msk                                   (0x1fUL << LCD_PAL35_G14_0_Pos)                           /*!< LCD PAL35: G14_0 Mask               */
+#define LCD_PAL35_B14_0_Pos                                   26                                                        /*!< LCD PAL35: B14_0 Position           */
+#define LCD_PAL35_B14_0_Msk                                   (0x1fUL << LCD_PAL35_B14_0_Pos)                           /*!< LCD PAL35: B14_0 Mask               */
+#define LCD_PAL35_I1_Pos                                      31                                                        /*!< LCD PAL35: I1 Position              */
+#define LCD_PAL35_I1_Msk                                      (0x01UL << LCD_PAL35_I1_Pos)                              /*!< LCD PAL35: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL36  -------------------------------------------
+#define LCD_PAL36_R04_0_Pos                                   0                                                         /*!< LCD PAL36: R04_0 Position           */
+#define LCD_PAL36_R04_0_Msk                                   (0x1fUL << LCD_PAL36_R04_0_Pos)                           /*!< LCD PAL36: R04_0 Mask               */
+#define LCD_PAL36_G04_0_Pos                                   5                                                         /*!< LCD PAL36: G04_0 Position           */
+#define LCD_PAL36_G04_0_Msk                                   (0x1fUL << LCD_PAL36_G04_0_Pos)                           /*!< LCD PAL36: G04_0 Mask               */
+#define LCD_PAL36_B04_0_Pos                                   10                                                        /*!< LCD PAL36: B04_0 Position           */
+#define LCD_PAL36_B04_0_Msk                                   (0x1fUL << LCD_PAL36_B04_0_Pos)                           /*!< LCD PAL36: B04_0 Mask               */
+#define LCD_PAL36_I0_Pos                                      15                                                        /*!< LCD PAL36: I0 Position              */
+#define LCD_PAL36_I0_Msk                                      (0x01UL << LCD_PAL36_I0_Pos)                              /*!< LCD PAL36: I0 Mask                  */
+#define LCD_PAL36_R14_0_Pos                                   16                                                        /*!< LCD PAL36: R14_0 Position           */
+#define LCD_PAL36_R14_0_Msk                                   (0x1fUL << LCD_PAL36_R14_0_Pos)                           /*!< LCD PAL36: R14_0 Mask               */
+#define LCD_PAL36_G14_0_Pos                                   21                                                        /*!< LCD PAL36: G14_0 Position           */
+#define LCD_PAL36_G14_0_Msk                                   (0x1fUL << LCD_PAL36_G14_0_Pos)                           /*!< LCD PAL36: G14_0 Mask               */
+#define LCD_PAL36_B14_0_Pos                                   26                                                        /*!< LCD PAL36: B14_0 Position           */
+#define LCD_PAL36_B14_0_Msk                                   (0x1fUL << LCD_PAL36_B14_0_Pos)                           /*!< LCD PAL36: B14_0 Mask               */
+#define LCD_PAL36_I1_Pos                                      31                                                        /*!< LCD PAL36: I1 Position              */
+#define LCD_PAL36_I1_Msk                                      (0x01UL << LCD_PAL36_I1_Pos)                              /*!< LCD PAL36: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL37  -------------------------------------------
+#define LCD_PAL37_R04_0_Pos                                   0                                                         /*!< LCD PAL37: R04_0 Position           */
+#define LCD_PAL37_R04_0_Msk                                   (0x1fUL << LCD_PAL37_R04_0_Pos)                           /*!< LCD PAL37: R04_0 Mask               */
+#define LCD_PAL37_G04_0_Pos                                   5                                                         /*!< LCD PAL37: G04_0 Position           */
+#define LCD_PAL37_G04_0_Msk                                   (0x1fUL << LCD_PAL37_G04_0_Pos)                           /*!< LCD PAL37: G04_0 Mask               */
+#define LCD_PAL37_B04_0_Pos                                   10                                                        /*!< LCD PAL37: B04_0 Position           */
+#define LCD_PAL37_B04_0_Msk                                   (0x1fUL << LCD_PAL37_B04_0_Pos)                           /*!< LCD PAL37: B04_0 Mask               */
+#define LCD_PAL37_I0_Pos                                      15                                                        /*!< LCD PAL37: I0 Position              */
+#define LCD_PAL37_I0_Msk                                      (0x01UL << LCD_PAL37_I0_Pos)                              /*!< LCD PAL37: I0 Mask                  */
+#define LCD_PAL37_R14_0_Pos                                   16                                                        /*!< LCD PAL37: R14_0 Position           */
+#define LCD_PAL37_R14_0_Msk                                   (0x1fUL << LCD_PAL37_R14_0_Pos)                           /*!< LCD PAL37: R14_0 Mask               */
+#define LCD_PAL37_G14_0_Pos                                   21                                                        /*!< LCD PAL37: G14_0 Position           */
+#define LCD_PAL37_G14_0_Msk                                   (0x1fUL << LCD_PAL37_G14_0_Pos)                           /*!< LCD PAL37: G14_0 Mask               */
+#define LCD_PAL37_B14_0_Pos                                   26                                                        /*!< LCD PAL37: B14_0 Position           */
+#define LCD_PAL37_B14_0_Msk                                   (0x1fUL << LCD_PAL37_B14_0_Pos)                           /*!< LCD PAL37: B14_0 Mask               */
+#define LCD_PAL37_I1_Pos                                      31                                                        /*!< LCD PAL37: I1 Position              */
+#define LCD_PAL37_I1_Msk                                      (0x01UL << LCD_PAL37_I1_Pos)                              /*!< LCD PAL37: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL38  -------------------------------------------
+#define LCD_PAL38_R04_0_Pos                                   0                                                         /*!< LCD PAL38: R04_0 Position           */
+#define LCD_PAL38_R04_0_Msk                                   (0x1fUL << LCD_PAL38_R04_0_Pos)                           /*!< LCD PAL38: R04_0 Mask               */
+#define LCD_PAL38_G04_0_Pos                                   5                                                         /*!< LCD PAL38: G04_0 Position           */
+#define LCD_PAL38_G04_0_Msk                                   (0x1fUL << LCD_PAL38_G04_0_Pos)                           /*!< LCD PAL38: G04_0 Mask               */
+#define LCD_PAL38_B04_0_Pos                                   10                                                        /*!< LCD PAL38: B04_0 Position           */
+#define LCD_PAL38_B04_0_Msk                                   (0x1fUL << LCD_PAL38_B04_0_Pos)                           /*!< LCD PAL38: B04_0 Mask               */
+#define LCD_PAL38_I0_Pos                                      15                                                        /*!< LCD PAL38: I0 Position              */
+#define LCD_PAL38_I0_Msk                                      (0x01UL << LCD_PAL38_I0_Pos)                              /*!< LCD PAL38: I0 Mask                  */
+#define LCD_PAL38_R14_0_Pos                                   16                                                        /*!< LCD PAL38: R14_0 Position           */
+#define LCD_PAL38_R14_0_Msk                                   (0x1fUL << LCD_PAL38_R14_0_Pos)                           /*!< LCD PAL38: R14_0 Mask               */
+#define LCD_PAL38_G14_0_Pos                                   21                                                        /*!< LCD PAL38: G14_0 Position           */
+#define LCD_PAL38_G14_0_Msk                                   (0x1fUL << LCD_PAL38_G14_0_Pos)                           /*!< LCD PAL38: G14_0 Mask               */
+#define LCD_PAL38_B14_0_Pos                                   26                                                        /*!< LCD PAL38: B14_0 Position           */
+#define LCD_PAL38_B14_0_Msk                                   (0x1fUL << LCD_PAL38_B14_0_Pos)                           /*!< LCD PAL38: B14_0 Mask               */
+#define LCD_PAL38_I1_Pos                                      31                                                        /*!< LCD PAL38: I1 Position              */
+#define LCD_PAL38_I1_Msk                                      (0x01UL << LCD_PAL38_I1_Pos)                              /*!< LCD PAL38: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL39  -------------------------------------------
+#define LCD_PAL39_R04_0_Pos                                   0                                                         /*!< LCD PAL39: R04_0 Position           */
+#define LCD_PAL39_R04_0_Msk                                   (0x1fUL << LCD_PAL39_R04_0_Pos)                           /*!< LCD PAL39: R04_0 Mask               */
+#define LCD_PAL39_G04_0_Pos                                   5                                                         /*!< LCD PAL39: G04_0 Position           */
+#define LCD_PAL39_G04_0_Msk                                   (0x1fUL << LCD_PAL39_G04_0_Pos)                           /*!< LCD PAL39: G04_0 Mask               */
+#define LCD_PAL39_B04_0_Pos                                   10                                                        /*!< LCD PAL39: B04_0 Position           */
+#define LCD_PAL39_B04_0_Msk                                   (0x1fUL << LCD_PAL39_B04_0_Pos)                           /*!< LCD PAL39: B04_0 Mask               */
+#define LCD_PAL39_I0_Pos                                      15                                                        /*!< LCD PAL39: I0 Position              */
+#define LCD_PAL39_I0_Msk                                      (0x01UL << LCD_PAL39_I0_Pos)                              /*!< LCD PAL39: I0 Mask                  */
+#define LCD_PAL39_R14_0_Pos                                   16                                                        /*!< LCD PAL39: R14_0 Position           */
+#define LCD_PAL39_R14_0_Msk                                   (0x1fUL << LCD_PAL39_R14_0_Pos)                           /*!< LCD PAL39: R14_0 Mask               */
+#define LCD_PAL39_G14_0_Pos                                   21                                                        /*!< LCD PAL39: G14_0 Position           */
+#define LCD_PAL39_G14_0_Msk                                   (0x1fUL << LCD_PAL39_G14_0_Pos)                           /*!< LCD PAL39: G14_0 Mask               */
+#define LCD_PAL39_B14_0_Pos                                   26                                                        /*!< LCD PAL39: B14_0 Position           */
+#define LCD_PAL39_B14_0_Msk                                   (0x1fUL << LCD_PAL39_B14_0_Pos)                           /*!< LCD PAL39: B14_0 Mask               */
+#define LCD_PAL39_I1_Pos                                      31                                                        /*!< LCD PAL39: I1 Position              */
+#define LCD_PAL39_I1_Msk                                      (0x01UL << LCD_PAL39_I1_Pos)                              /*!< LCD PAL39: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL40  -------------------------------------------
+#define LCD_PAL40_R04_0_Pos                                   0                                                         /*!< LCD PAL40: R04_0 Position           */
+#define LCD_PAL40_R04_0_Msk                                   (0x1fUL << LCD_PAL40_R04_0_Pos)                           /*!< LCD PAL40: R04_0 Mask               */
+#define LCD_PAL40_G04_0_Pos                                   5                                                         /*!< LCD PAL40: G04_0 Position           */
+#define LCD_PAL40_G04_0_Msk                                   (0x1fUL << LCD_PAL40_G04_0_Pos)                           /*!< LCD PAL40: G04_0 Mask               */
+#define LCD_PAL40_B04_0_Pos                                   10                                                        /*!< LCD PAL40: B04_0 Position           */
+#define LCD_PAL40_B04_0_Msk                                   (0x1fUL << LCD_PAL40_B04_0_Pos)                           /*!< LCD PAL40: B04_0 Mask               */
+#define LCD_PAL40_I0_Pos                                      15                                                        /*!< LCD PAL40: I0 Position              */
+#define LCD_PAL40_I0_Msk                                      (0x01UL << LCD_PAL40_I0_Pos)                              /*!< LCD PAL40: I0 Mask                  */
+#define LCD_PAL40_R14_0_Pos                                   16                                                        /*!< LCD PAL40: R14_0 Position           */
+#define LCD_PAL40_R14_0_Msk                                   (0x1fUL << LCD_PAL40_R14_0_Pos)                           /*!< LCD PAL40: R14_0 Mask               */
+#define LCD_PAL40_G14_0_Pos                                   21                                                        /*!< LCD PAL40: G14_0 Position           */
+#define LCD_PAL40_G14_0_Msk                                   (0x1fUL << LCD_PAL40_G14_0_Pos)                           /*!< LCD PAL40: G14_0 Mask               */
+#define LCD_PAL40_B14_0_Pos                                   26                                                        /*!< LCD PAL40: B14_0 Position           */
+#define LCD_PAL40_B14_0_Msk                                   (0x1fUL << LCD_PAL40_B14_0_Pos)                           /*!< LCD PAL40: B14_0 Mask               */
+#define LCD_PAL40_I1_Pos                                      31                                                        /*!< LCD PAL40: I1 Position              */
+#define LCD_PAL40_I1_Msk                                      (0x01UL << LCD_PAL40_I1_Pos)                              /*!< LCD PAL40: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL41  -------------------------------------------
+#define LCD_PAL41_R04_0_Pos                                   0                                                         /*!< LCD PAL41: R04_0 Position           */
+#define LCD_PAL41_R04_0_Msk                                   (0x1fUL << LCD_PAL41_R04_0_Pos)                           /*!< LCD PAL41: R04_0 Mask               */
+#define LCD_PAL41_G04_0_Pos                                   5                                                         /*!< LCD PAL41: G04_0 Position           */
+#define LCD_PAL41_G04_0_Msk                                   (0x1fUL << LCD_PAL41_G04_0_Pos)                           /*!< LCD PAL41: G04_0 Mask               */
+#define LCD_PAL41_B04_0_Pos                                   10                                                        /*!< LCD PAL41: B04_0 Position           */
+#define LCD_PAL41_B04_0_Msk                                   (0x1fUL << LCD_PAL41_B04_0_Pos)                           /*!< LCD PAL41: B04_0 Mask               */
+#define LCD_PAL41_I0_Pos                                      15                                                        /*!< LCD PAL41: I0 Position              */
+#define LCD_PAL41_I0_Msk                                      (0x01UL << LCD_PAL41_I0_Pos)                              /*!< LCD PAL41: I0 Mask                  */
+#define LCD_PAL41_R14_0_Pos                                   16                                                        /*!< LCD PAL41: R14_0 Position           */
+#define LCD_PAL41_R14_0_Msk                                   (0x1fUL << LCD_PAL41_R14_0_Pos)                           /*!< LCD PAL41: R14_0 Mask               */
+#define LCD_PAL41_G14_0_Pos                                   21                                                        /*!< LCD PAL41: G14_0 Position           */
+#define LCD_PAL41_G14_0_Msk                                   (0x1fUL << LCD_PAL41_G14_0_Pos)                           /*!< LCD PAL41: G14_0 Mask               */
+#define LCD_PAL41_B14_0_Pos                                   26                                                        /*!< LCD PAL41: B14_0 Position           */
+#define LCD_PAL41_B14_0_Msk                                   (0x1fUL << LCD_PAL41_B14_0_Pos)                           /*!< LCD PAL41: B14_0 Mask               */
+#define LCD_PAL41_I1_Pos                                      31                                                        /*!< LCD PAL41: I1 Position              */
+#define LCD_PAL41_I1_Msk                                      (0x01UL << LCD_PAL41_I1_Pos)                              /*!< LCD PAL41: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL42  -------------------------------------------
+#define LCD_PAL42_R04_0_Pos                                   0                                                         /*!< LCD PAL42: R04_0 Position           */
+#define LCD_PAL42_R04_0_Msk                                   (0x1fUL << LCD_PAL42_R04_0_Pos)                           /*!< LCD PAL42: R04_0 Mask               */
+#define LCD_PAL42_G04_0_Pos                                   5                                                         /*!< LCD PAL42: G04_0 Position           */
+#define LCD_PAL42_G04_0_Msk                                   (0x1fUL << LCD_PAL42_G04_0_Pos)                           /*!< LCD PAL42: G04_0 Mask               */
+#define LCD_PAL42_B04_0_Pos                                   10                                                        /*!< LCD PAL42: B04_0 Position           */
+#define LCD_PAL42_B04_0_Msk                                   (0x1fUL << LCD_PAL42_B04_0_Pos)                           /*!< LCD PAL42: B04_0 Mask               */
+#define LCD_PAL42_I0_Pos                                      15                                                        /*!< LCD PAL42: I0 Position              */
+#define LCD_PAL42_I0_Msk                                      (0x01UL << LCD_PAL42_I0_Pos)                              /*!< LCD PAL42: I0 Mask                  */
+#define LCD_PAL42_R14_0_Pos                                   16                                                        /*!< LCD PAL42: R14_0 Position           */
+#define LCD_PAL42_R14_0_Msk                                   (0x1fUL << LCD_PAL42_R14_0_Pos)                           /*!< LCD PAL42: R14_0 Mask               */
+#define LCD_PAL42_G14_0_Pos                                   21                                                        /*!< LCD PAL42: G14_0 Position           */
+#define LCD_PAL42_G14_0_Msk                                   (0x1fUL << LCD_PAL42_G14_0_Pos)                           /*!< LCD PAL42: G14_0 Mask               */
+#define LCD_PAL42_B14_0_Pos                                   26                                                        /*!< LCD PAL42: B14_0 Position           */
+#define LCD_PAL42_B14_0_Msk                                   (0x1fUL << LCD_PAL42_B14_0_Pos)                           /*!< LCD PAL42: B14_0 Mask               */
+#define LCD_PAL42_I1_Pos                                      31                                                        /*!< LCD PAL42: I1 Position              */
+#define LCD_PAL42_I1_Msk                                      (0x01UL << LCD_PAL42_I1_Pos)                              /*!< LCD PAL42: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL43  -------------------------------------------
+#define LCD_PAL43_R04_0_Pos                                   0                                                         /*!< LCD PAL43: R04_0 Position           */
+#define LCD_PAL43_R04_0_Msk                                   (0x1fUL << LCD_PAL43_R04_0_Pos)                           /*!< LCD PAL43: R04_0 Mask               */
+#define LCD_PAL43_G04_0_Pos                                   5                                                         /*!< LCD PAL43: G04_0 Position           */
+#define LCD_PAL43_G04_0_Msk                                   (0x1fUL << LCD_PAL43_G04_0_Pos)                           /*!< LCD PAL43: G04_0 Mask               */
+#define LCD_PAL43_B04_0_Pos                                   10                                                        /*!< LCD PAL43: B04_0 Position           */
+#define LCD_PAL43_B04_0_Msk                                   (0x1fUL << LCD_PAL43_B04_0_Pos)                           /*!< LCD PAL43: B04_0 Mask               */
+#define LCD_PAL43_I0_Pos                                      15                                                        /*!< LCD PAL43: I0 Position              */
+#define LCD_PAL43_I0_Msk                                      (0x01UL << LCD_PAL43_I0_Pos)                              /*!< LCD PAL43: I0 Mask                  */
+#define LCD_PAL43_R14_0_Pos                                   16                                                        /*!< LCD PAL43: R14_0 Position           */
+#define LCD_PAL43_R14_0_Msk                                   (0x1fUL << LCD_PAL43_R14_0_Pos)                           /*!< LCD PAL43: R14_0 Mask               */
+#define LCD_PAL43_G14_0_Pos                                   21                                                        /*!< LCD PAL43: G14_0 Position           */
+#define LCD_PAL43_G14_0_Msk                                   (0x1fUL << LCD_PAL43_G14_0_Pos)                           /*!< LCD PAL43: G14_0 Mask               */
+#define LCD_PAL43_B14_0_Pos                                   26                                                        /*!< LCD PAL43: B14_0 Position           */
+#define LCD_PAL43_B14_0_Msk                                   (0x1fUL << LCD_PAL43_B14_0_Pos)                           /*!< LCD PAL43: B14_0 Mask               */
+#define LCD_PAL43_I1_Pos                                      31                                                        /*!< LCD PAL43: I1 Position              */
+#define LCD_PAL43_I1_Msk                                      (0x01UL << LCD_PAL43_I1_Pos)                              /*!< LCD PAL43: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL44  -------------------------------------------
+#define LCD_PAL44_R04_0_Pos                                   0                                                         /*!< LCD PAL44: R04_0 Position           */
+#define LCD_PAL44_R04_0_Msk                                   (0x1fUL << LCD_PAL44_R04_0_Pos)                           /*!< LCD PAL44: R04_0 Mask               */
+#define LCD_PAL44_G04_0_Pos                                   5                                                         /*!< LCD PAL44: G04_0 Position           */
+#define LCD_PAL44_G04_0_Msk                                   (0x1fUL << LCD_PAL44_G04_0_Pos)                           /*!< LCD PAL44: G04_0 Mask               */
+#define LCD_PAL44_B04_0_Pos                                   10                                                        /*!< LCD PAL44: B04_0 Position           */
+#define LCD_PAL44_B04_0_Msk                                   (0x1fUL << LCD_PAL44_B04_0_Pos)                           /*!< LCD PAL44: B04_0 Mask               */
+#define LCD_PAL44_I0_Pos                                      15                                                        /*!< LCD PAL44: I0 Position              */
+#define LCD_PAL44_I0_Msk                                      (0x01UL << LCD_PAL44_I0_Pos)                              /*!< LCD PAL44: I0 Mask                  */
+#define LCD_PAL44_R14_0_Pos                                   16                                                        /*!< LCD PAL44: R14_0 Position           */
+#define LCD_PAL44_R14_0_Msk                                   (0x1fUL << LCD_PAL44_R14_0_Pos)                           /*!< LCD PAL44: R14_0 Mask               */
+#define LCD_PAL44_G14_0_Pos                                   21                                                        /*!< LCD PAL44: G14_0 Position           */
+#define LCD_PAL44_G14_0_Msk                                   (0x1fUL << LCD_PAL44_G14_0_Pos)                           /*!< LCD PAL44: G14_0 Mask               */
+#define LCD_PAL44_B14_0_Pos                                   26                                                        /*!< LCD PAL44: B14_0 Position           */
+#define LCD_PAL44_B14_0_Msk                                   (0x1fUL << LCD_PAL44_B14_0_Pos)                           /*!< LCD PAL44: B14_0 Mask               */
+#define LCD_PAL44_I1_Pos                                      31                                                        /*!< LCD PAL44: I1 Position              */
+#define LCD_PAL44_I1_Msk                                      (0x01UL << LCD_PAL44_I1_Pos)                              /*!< LCD PAL44: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL45  -------------------------------------------
+#define LCD_PAL45_R04_0_Pos                                   0                                                         /*!< LCD PAL45: R04_0 Position           */
+#define LCD_PAL45_R04_0_Msk                                   (0x1fUL << LCD_PAL45_R04_0_Pos)                           /*!< LCD PAL45: R04_0 Mask               */
+#define LCD_PAL45_G04_0_Pos                                   5                                                         /*!< LCD PAL45: G04_0 Position           */
+#define LCD_PAL45_G04_0_Msk                                   (0x1fUL << LCD_PAL45_G04_0_Pos)                           /*!< LCD PAL45: G04_0 Mask               */
+#define LCD_PAL45_B04_0_Pos                                   10                                                        /*!< LCD PAL45: B04_0 Position           */
+#define LCD_PAL45_B04_0_Msk                                   (0x1fUL << LCD_PAL45_B04_0_Pos)                           /*!< LCD PAL45: B04_0 Mask               */
+#define LCD_PAL45_I0_Pos                                      15                                                        /*!< LCD PAL45: I0 Position              */
+#define LCD_PAL45_I0_Msk                                      (0x01UL << LCD_PAL45_I0_Pos)                              /*!< LCD PAL45: I0 Mask                  */
+#define LCD_PAL45_R14_0_Pos                                   16                                                        /*!< LCD PAL45: R14_0 Position           */
+#define LCD_PAL45_R14_0_Msk                                   (0x1fUL << LCD_PAL45_R14_0_Pos)                           /*!< LCD PAL45: R14_0 Mask               */
+#define LCD_PAL45_G14_0_Pos                                   21                                                        /*!< LCD PAL45: G14_0 Position           */
+#define LCD_PAL45_G14_0_Msk                                   (0x1fUL << LCD_PAL45_G14_0_Pos)                           /*!< LCD PAL45: G14_0 Mask               */
+#define LCD_PAL45_B14_0_Pos                                   26                                                        /*!< LCD PAL45: B14_0 Position           */
+#define LCD_PAL45_B14_0_Msk                                   (0x1fUL << LCD_PAL45_B14_0_Pos)                           /*!< LCD PAL45: B14_0 Mask               */
+#define LCD_PAL45_I1_Pos                                      31                                                        /*!< LCD PAL45: I1 Position              */
+#define LCD_PAL45_I1_Msk                                      (0x01UL << LCD_PAL45_I1_Pos)                              /*!< LCD PAL45: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL46  -------------------------------------------
+#define LCD_PAL46_R04_0_Pos                                   0                                                         /*!< LCD PAL46: R04_0 Position           */
+#define LCD_PAL46_R04_0_Msk                                   (0x1fUL << LCD_PAL46_R04_0_Pos)                           /*!< LCD PAL46: R04_0 Mask               */
+#define LCD_PAL46_G04_0_Pos                                   5                                                         /*!< LCD PAL46: G04_0 Position           */
+#define LCD_PAL46_G04_0_Msk                                   (0x1fUL << LCD_PAL46_G04_0_Pos)                           /*!< LCD PAL46: G04_0 Mask               */
+#define LCD_PAL46_B04_0_Pos                                   10                                                        /*!< LCD PAL46: B04_0 Position           */
+#define LCD_PAL46_B04_0_Msk                                   (0x1fUL << LCD_PAL46_B04_0_Pos)                           /*!< LCD PAL46: B04_0 Mask               */
+#define LCD_PAL46_I0_Pos                                      15                                                        /*!< LCD PAL46: I0 Position              */
+#define LCD_PAL46_I0_Msk                                      (0x01UL << LCD_PAL46_I0_Pos)                              /*!< LCD PAL46: I0 Mask                  */
+#define LCD_PAL46_R14_0_Pos                                   16                                                        /*!< LCD PAL46: R14_0 Position           */
+#define LCD_PAL46_R14_0_Msk                                   (0x1fUL << LCD_PAL46_R14_0_Pos)                           /*!< LCD PAL46: R14_0 Mask               */
+#define LCD_PAL46_G14_0_Pos                                   21                                                        /*!< LCD PAL46: G14_0 Position           */
+#define LCD_PAL46_G14_0_Msk                                   (0x1fUL << LCD_PAL46_G14_0_Pos)                           /*!< LCD PAL46: G14_0 Mask               */
+#define LCD_PAL46_B14_0_Pos                                   26                                                        /*!< LCD PAL46: B14_0 Position           */
+#define LCD_PAL46_B14_0_Msk                                   (0x1fUL << LCD_PAL46_B14_0_Pos)                           /*!< LCD PAL46: B14_0 Mask               */
+#define LCD_PAL46_I1_Pos                                      31                                                        /*!< LCD PAL46: I1 Position              */
+#define LCD_PAL46_I1_Msk                                      (0x01UL << LCD_PAL46_I1_Pos)                              /*!< LCD PAL46: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL47  -------------------------------------------
+#define LCD_PAL47_R04_0_Pos                                   0                                                         /*!< LCD PAL47: R04_0 Position           */
+#define LCD_PAL47_R04_0_Msk                                   (0x1fUL << LCD_PAL47_R04_0_Pos)                           /*!< LCD PAL47: R04_0 Mask               */
+#define LCD_PAL47_G04_0_Pos                                   5                                                         /*!< LCD PAL47: G04_0 Position           */
+#define LCD_PAL47_G04_0_Msk                                   (0x1fUL << LCD_PAL47_G04_0_Pos)                           /*!< LCD PAL47: G04_0 Mask               */
+#define LCD_PAL47_B04_0_Pos                                   10                                                        /*!< LCD PAL47: B04_0 Position           */
+#define LCD_PAL47_B04_0_Msk                                   (0x1fUL << LCD_PAL47_B04_0_Pos)                           /*!< LCD PAL47: B04_0 Mask               */
+#define LCD_PAL47_I0_Pos                                      15                                                        /*!< LCD PAL47: I0 Position              */
+#define LCD_PAL47_I0_Msk                                      (0x01UL << LCD_PAL47_I0_Pos)                              /*!< LCD PAL47: I0 Mask                  */
+#define LCD_PAL47_R14_0_Pos                                   16                                                        /*!< LCD PAL47: R14_0 Position           */
+#define LCD_PAL47_R14_0_Msk                                   (0x1fUL << LCD_PAL47_R14_0_Pos)                           /*!< LCD PAL47: R14_0 Mask               */
+#define LCD_PAL47_G14_0_Pos                                   21                                                        /*!< LCD PAL47: G14_0 Position           */
+#define LCD_PAL47_G14_0_Msk                                   (0x1fUL << LCD_PAL47_G14_0_Pos)                           /*!< LCD PAL47: G14_0 Mask               */
+#define LCD_PAL47_B14_0_Pos                                   26                                                        /*!< LCD PAL47: B14_0 Position           */
+#define LCD_PAL47_B14_0_Msk                                   (0x1fUL << LCD_PAL47_B14_0_Pos)                           /*!< LCD PAL47: B14_0 Mask               */
+#define LCD_PAL47_I1_Pos                                      31                                                        /*!< LCD PAL47: I1 Position              */
+#define LCD_PAL47_I1_Msk                                      (0x01UL << LCD_PAL47_I1_Pos)                              /*!< LCD PAL47: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL48  -------------------------------------------
+#define LCD_PAL48_R04_0_Pos                                   0                                                         /*!< LCD PAL48: R04_0 Position           */
+#define LCD_PAL48_R04_0_Msk                                   (0x1fUL << LCD_PAL48_R04_0_Pos)                           /*!< LCD PAL48: R04_0 Mask               */
+#define LCD_PAL48_G04_0_Pos                                   5                                                         /*!< LCD PAL48: G04_0 Position           */
+#define LCD_PAL48_G04_0_Msk                                   (0x1fUL << LCD_PAL48_G04_0_Pos)                           /*!< LCD PAL48: G04_0 Mask               */
+#define LCD_PAL48_B04_0_Pos                                   10                                                        /*!< LCD PAL48: B04_0 Position           */
+#define LCD_PAL48_B04_0_Msk                                   (0x1fUL << LCD_PAL48_B04_0_Pos)                           /*!< LCD PAL48: B04_0 Mask               */
+#define LCD_PAL48_I0_Pos                                      15                                                        /*!< LCD PAL48: I0 Position              */
+#define LCD_PAL48_I0_Msk                                      (0x01UL << LCD_PAL48_I0_Pos)                              /*!< LCD PAL48: I0 Mask                  */
+#define LCD_PAL48_R14_0_Pos                                   16                                                        /*!< LCD PAL48: R14_0 Position           */
+#define LCD_PAL48_R14_0_Msk                                   (0x1fUL << LCD_PAL48_R14_0_Pos)                           /*!< LCD PAL48: R14_0 Mask               */
+#define LCD_PAL48_G14_0_Pos                                   21                                                        /*!< LCD PAL48: G14_0 Position           */
+#define LCD_PAL48_G14_0_Msk                                   (0x1fUL << LCD_PAL48_G14_0_Pos)                           /*!< LCD PAL48: G14_0 Mask               */
+#define LCD_PAL48_B14_0_Pos                                   26                                                        /*!< LCD PAL48: B14_0 Position           */
+#define LCD_PAL48_B14_0_Msk                                   (0x1fUL << LCD_PAL48_B14_0_Pos)                           /*!< LCD PAL48: B14_0 Mask               */
+#define LCD_PAL48_I1_Pos                                      31                                                        /*!< LCD PAL48: I1 Position              */
+#define LCD_PAL48_I1_Msk                                      (0x01UL << LCD_PAL48_I1_Pos)                              /*!< LCD PAL48: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL49  -------------------------------------------
+#define LCD_PAL49_R04_0_Pos                                   0                                                         /*!< LCD PAL49: R04_0 Position           */
+#define LCD_PAL49_R04_0_Msk                                   (0x1fUL << LCD_PAL49_R04_0_Pos)                           /*!< LCD PAL49: R04_0 Mask               */
+#define LCD_PAL49_G04_0_Pos                                   5                                                         /*!< LCD PAL49: G04_0 Position           */
+#define LCD_PAL49_G04_0_Msk                                   (0x1fUL << LCD_PAL49_G04_0_Pos)                           /*!< LCD PAL49: G04_0 Mask               */
+#define LCD_PAL49_B04_0_Pos                                   10                                                        /*!< LCD PAL49: B04_0 Position           */
+#define LCD_PAL49_B04_0_Msk                                   (0x1fUL << LCD_PAL49_B04_0_Pos)                           /*!< LCD PAL49: B04_0 Mask               */
+#define LCD_PAL49_I0_Pos                                      15                                                        /*!< LCD PAL49: I0 Position              */
+#define LCD_PAL49_I0_Msk                                      (0x01UL << LCD_PAL49_I0_Pos)                              /*!< LCD PAL49: I0 Mask                  */
+#define LCD_PAL49_R14_0_Pos                                   16                                                        /*!< LCD PAL49: R14_0 Position           */
+#define LCD_PAL49_R14_0_Msk                                   (0x1fUL << LCD_PAL49_R14_0_Pos)                           /*!< LCD PAL49: R14_0 Mask               */
+#define LCD_PAL49_G14_0_Pos                                   21                                                        /*!< LCD PAL49: G14_0 Position           */
+#define LCD_PAL49_G14_0_Msk                                   (0x1fUL << LCD_PAL49_G14_0_Pos)                           /*!< LCD PAL49: G14_0 Mask               */
+#define LCD_PAL49_B14_0_Pos                                   26                                                        /*!< LCD PAL49: B14_0 Position           */
+#define LCD_PAL49_B14_0_Msk                                   (0x1fUL << LCD_PAL49_B14_0_Pos)                           /*!< LCD PAL49: B14_0 Mask               */
+#define LCD_PAL49_I1_Pos                                      31                                                        /*!< LCD PAL49: I1 Position              */
+#define LCD_PAL49_I1_Msk                                      (0x01UL << LCD_PAL49_I1_Pos)                              /*!< LCD PAL49: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL50  -------------------------------------------
+#define LCD_PAL50_R04_0_Pos                                   0                                                         /*!< LCD PAL50: R04_0 Position           */
+#define LCD_PAL50_R04_0_Msk                                   (0x1fUL << LCD_PAL50_R04_0_Pos)                           /*!< LCD PAL50: R04_0 Mask               */
+#define LCD_PAL50_G04_0_Pos                                   5                                                         /*!< LCD PAL50: G04_0 Position           */
+#define LCD_PAL50_G04_0_Msk                                   (0x1fUL << LCD_PAL50_G04_0_Pos)                           /*!< LCD PAL50: G04_0 Mask               */
+#define LCD_PAL50_B04_0_Pos                                   10                                                        /*!< LCD PAL50: B04_0 Position           */
+#define LCD_PAL50_B04_0_Msk                                   (0x1fUL << LCD_PAL50_B04_0_Pos)                           /*!< LCD PAL50: B04_0 Mask               */
+#define LCD_PAL50_I0_Pos                                      15                                                        /*!< LCD PAL50: I0 Position              */
+#define LCD_PAL50_I0_Msk                                      (0x01UL << LCD_PAL50_I0_Pos)                              /*!< LCD PAL50: I0 Mask                  */
+#define LCD_PAL50_R14_0_Pos                                   16                                                        /*!< LCD PAL50: R14_0 Position           */
+#define LCD_PAL50_R14_0_Msk                                   (0x1fUL << LCD_PAL50_R14_0_Pos)                           /*!< LCD PAL50: R14_0 Mask               */
+#define LCD_PAL50_G14_0_Pos                                   21                                                        /*!< LCD PAL50: G14_0 Position           */
+#define LCD_PAL50_G14_0_Msk                                   (0x1fUL << LCD_PAL50_G14_0_Pos)                           /*!< LCD PAL50: G14_0 Mask               */
+#define LCD_PAL50_B14_0_Pos                                   26                                                        /*!< LCD PAL50: B14_0 Position           */
+#define LCD_PAL50_B14_0_Msk                                   (0x1fUL << LCD_PAL50_B14_0_Pos)                           /*!< LCD PAL50: B14_0 Mask               */
+#define LCD_PAL50_I1_Pos                                      31                                                        /*!< LCD PAL50: I1 Position              */
+#define LCD_PAL50_I1_Msk                                      (0x01UL << LCD_PAL50_I1_Pos)                              /*!< LCD PAL50: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL51  -------------------------------------------
+#define LCD_PAL51_R04_0_Pos                                   0                                                         /*!< LCD PAL51: R04_0 Position           */
+#define LCD_PAL51_R04_0_Msk                                   (0x1fUL << LCD_PAL51_R04_0_Pos)                           /*!< LCD PAL51: R04_0 Mask               */
+#define LCD_PAL51_G04_0_Pos                                   5                                                         /*!< LCD PAL51: G04_0 Position           */
+#define LCD_PAL51_G04_0_Msk                                   (0x1fUL << LCD_PAL51_G04_0_Pos)                           /*!< LCD PAL51: G04_0 Mask               */
+#define LCD_PAL51_B04_0_Pos                                   10                                                        /*!< LCD PAL51: B04_0 Position           */
+#define LCD_PAL51_B04_0_Msk                                   (0x1fUL << LCD_PAL51_B04_0_Pos)                           /*!< LCD PAL51: B04_0 Mask               */
+#define LCD_PAL51_I0_Pos                                      15                                                        /*!< LCD PAL51: I0 Position              */
+#define LCD_PAL51_I0_Msk                                      (0x01UL << LCD_PAL51_I0_Pos)                              /*!< LCD PAL51: I0 Mask                  */
+#define LCD_PAL51_R14_0_Pos                                   16                                                        /*!< LCD PAL51: R14_0 Position           */
+#define LCD_PAL51_R14_0_Msk                                   (0x1fUL << LCD_PAL51_R14_0_Pos)                           /*!< LCD PAL51: R14_0 Mask               */
+#define LCD_PAL51_G14_0_Pos                                   21                                                        /*!< LCD PAL51: G14_0 Position           */
+#define LCD_PAL51_G14_0_Msk                                   (0x1fUL << LCD_PAL51_G14_0_Pos)                           /*!< LCD PAL51: G14_0 Mask               */
+#define LCD_PAL51_B14_0_Pos                                   26                                                        /*!< LCD PAL51: B14_0 Position           */
+#define LCD_PAL51_B14_0_Msk                                   (0x1fUL << LCD_PAL51_B14_0_Pos)                           /*!< LCD PAL51: B14_0 Mask               */
+#define LCD_PAL51_I1_Pos                                      31                                                        /*!< LCD PAL51: I1 Position              */
+#define LCD_PAL51_I1_Msk                                      (0x01UL << LCD_PAL51_I1_Pos)                              /*!< LCD PAL51: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL52  -------------------------------------------
+#define LCD_PAL52_R04_0_Pos                                   0                                                         /*!< LCD PAL52: R04_0 Position           */
+#define LCD_PAL52_R04_0_Msk                                   (0x1fUL << LCD_PAL52_R04_0_Pos)                           /*!< LCD PAL52: R04_0 Mask               */
+#define LCD_PAL52_G04_0_Pos                                   5                                                         /*!< LCD PAL52: G04_0 Position           */
+#define LCD_PAL52_G04_0_Msk                                   (0x1fUL << LCD_PAL52_G04_0_Pos)                           /*!< LCD PAL52: G04_0 Mask               */
+#define LCD_PAL52_B04_0_Pos                                   10                                                        /*!< LCD PAL52: B04_0 Position           */
+#define LCD_PAL52_B04_0_Msk                                   (0x1fUL << LCD_PAL52_B04_0_Pos)                           /*!< LCD PAL52: B04_0 Mask               */
+#define LCD_PAL52_I0_Pos                                      15                                                        /*!< LCD PAL52: I0 Position              */
+#define LCD_PAL52_I0_Msk                                      (0x01UL << LCD_PAL52_I0_Pos)                              /*!< LCD PAL52: I0 Mask                  */
+#define LCD_PAL52_R14_0_Pos                                   16                                                        /*!< LCD PAL52: R14_0 Position           */
+#define LCD_PAL52_R14_0_Msk                                   (0x1fUL << LCD_PAL52_R14_0_Pos)                           /*!< LCD PAL52: R14_0 Mask               */
+#define LCD_PAL52_G14_0_Pos                                   21                                                        /*!< LCD PAL52: G14_0 Position           */
+#define LCD_PAL52_G14_0_Msk                                   (0x1fUL << LCD_PAL52_G14_0_Pos)                           /*!< LCD PAL52: G14_0 Mask               */
+#define LCD_PAL52_B14_0_Pos                                   26                                                        /*!< LCD PAL52: B14_0 Position           */
+#define LCD_PAL52_B14_0_Msk                                   (0x1fUL << LCD_PAL52_B14_0_Pos)                           /*!< LCD PAL52: B14_0 Mask               */
+#define LCD_PAL52_I1_Pos                                      31                                                        /*!< LCD PAL52: I1 Position              */
+#define LCD_PAL52_I1_Msk                                      (0x01UL << LCD_PAL52_I1_Pos)                              /*!< LCD PAL52: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL53  -------------------------------------------
+#define LCD_PAL53_R04_0_Pos                                   0                                                         /*!< LCD PAL53: R04_0 Position           */
+#define LCD_PAL53_R04_0_Msk                                   (0x1fUL << LCD_PAL53_R04_0_Pos)                           /*!< LCD PAL53: R04_0 Mask               */
+#define LCD_PAL53_G04_0_Pos                                   5                                                         /*!< LCD PAL53: G04_0 Position           */
+#define LCD_PAL53_G04_0_Msk                                   (0x1fUL << LCD_PAL53_G04_0_Pos)                           /*!< LCD PAL53: G04_0 Mask               */
+#define LCD_PAL53_B04_0_Pos                                   10                                                        /*!< LCD PAL53: B04_0 Position           */
+#define LCD_PAL53_B04_0_Msk                                   (0x1fUL << LCD_PAL53_B04_0_Pos)                           /*!< LCD PAL53: B04_0 Mask               */
+#define LCD_PAL53_I0_Pos                                      15                                                        /*!< LCD PAL53: I0 Position              */
+#define LCD_PAL53_I0_Msk                                      (0x01UL << LCD_PAL53_I0_Pos)                              /*!< LCD PAL53: I0 Mask                  */
+#define LCD_PAL53_R14_0_Pos                                   16                                                        /*!< LCD PAL53: R14_0 Position           */
+#define LCD_PAL53_R14_0_Msk                                   (0x1fUL << LCD_PAL53_R14_0_Pos)                           /*!< LCD PAL53: R14_0 Mask               */
+#define LCD_PAL53_G14_0_Pos                                   21                                                        /*!< LCD PAL53: G14_0 Position           */
+#define LCD_PAL53_G14_0_Msk                                   (0x1fUL << LCD_PAL53_G14_0_Pos)                           /*!< LCD PAL53: G14_0 Mask               */
+#define LCD_PAL53_B14_0_Pos                                   26                                                        /*!< LCD PAL53: B14_0 Position           */
+#define LCD_PAL53_B14_0_Msk                                   (0x1fUL << LCD_PAL53_B14_0_Pos)                           /*!< LCD PAL53: B14_0 Mask               */
+#define LCD_PAL53_I1_Pos                                      31                                                        /*!< LCD PAL53: I1 Position              */
+#define LCD_PAL53_I1_Msk                                      (0x01UL << LCD_PAL53_I1_Pos)                              /*!< LCD PAL53: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL54  -------------------------------------------
+#define LCD_PAL54_R04_0_Pos                                   0                                                         /*!< LCD PAL54: R04_0 Position           */
+#define LCD_PAL54_R04_0_Msk                                   (0x1fUL << LCD_PAL54_R04_0_Pos)                           /*!< LCD PAL54: R04_0 Mask               */
+#define LCD_PAL54_G04_0_Pos                                   5                                                         /*!< LCD PAL54: G04_0 Position           */
+#define LCD_PAL54_G04_0_Msk                                   (0x1fUL << LCD_PAL54_G04_0_Pos)                           /*!< LCD PAL54: G04_0 Mask               */
+#define LCD_PAL54_B04_0_Pos                                   10                                                        /*!< LCD PAL54: B04_0 Position           */
+#define LCD_PAL54_B04_0_Msk                                   (0x1fUL << LCD_PAL54_B04_0_Pos)                           /*!< LCD PAL54: B04_0 Mask               */
+#define LCD_PAL54_I0_Pos                                      15                                                        /*!< LCD PAL54: I0 Position              */
+#define LCD_PAL54_I0_Msk                                      (0x01UL << LCD_PAL54_I0_Pos)                              /*!< LCD PAL54: I0 Mask                  */
+#define LCD_PAL54_R14_0_Pos                                   16                                                        /*!< LCD PAL54: R14_0 Position           */
+#define LCD_PAL54_R14_0_Msk                                   (0x1fUL << LCD_PAL54_R14_0_Pos)                           /*!< LCD PAL54: R14_0 Mask               */
+#define LCD_PAL54_G14_0_Pos                                   21                                                        /*!< LCD PAL54: G14_0 Position           */
+#define LCD_PAL54_G14_0_Msk                                   (0x1fUL << LCD_PAL54_G14_0_Pos)                           /*!< LCD PAL54: G14_0 Mask               */
+#define LCD_PAL54_B14_0_Pos                                   26                                                        /*!< LCD PAL54: B14_0 Position           */
+#define LCD_PAL54_B14_0_Msk                                   (0x1fUL << LCD_PAL54_B14_0_Pos)                           /*!< LCD PAL54: B14_0 Mask               */
+#define LCD_PAL54_I1_Pos                                      31                                                        /*!< LCD PAL54: I1 Position              */
+#define LCD_PAL54_I1_Msk                                      (0x01UL << LCD_PAL54_I1_Pos)                              /*!< LCD PAL54: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL55  -------------------------------------------
+#define LCD_PAL55_R04_0_Pos                                   0                                                         /*!< LCD PAL55: R04_0 Position           */
+#define LCD_PAL55_R04_0_Msk                                   (0x1fUL << LCD_PAL55_R04_0_Pos)                           /*!< LCD PAL55: R04_0 Mask               */
+#define LCD_PAL55_G04_0_Pos                                   5                                                         /*!< LCD PAL55: G04_0 Position           */
+#define LCD_PAL55_G04_0_Msk                                   (0x1fUL << LCD_PAL55_G04_0_Pos)                           /*!< LCD PAL55: G04_0 Mask               */
+#define LCD_PAL55_B04_0_Pos                                   10                                                        /*!< LCD PAL55: B04_0 Position           */
+#define LCD_PAL55_B04_0_Msk                                   (0x1fUL << LCD_PAL55_B04_0_Pos)                           /*!< LCD PAL55: B04_0 Mask               */
+#define LCD_PAL55_I0_Pos                                      15                                                        /*!< LCD PAL55: I0 Position              */
+#define LCD_PAL55_I0_Msk                                      (0x01UL << LCD_PAL55_I0_Pos)                              /*!< LCD PAL55: I0 Mask                  */
+#define LCD_PAL55_R14_0_Pos                                   16                                                        /*!< LCD PAL55: R14_0 Position           */
+#define LCD_PAL55_R14_0_Msk                                   (0x1fUL << LCD_PAL55_R14_0_Pos)                           /*!< LCD PAL55: R14_0 Mask               */
+#define LCD_PAL55_G14_0_Pos                                   21                                                        /*!< LCD PAL55: G14_0 Position           */
+#define LCD_PAL55_G14_0_Msk                                   (0x1fUL << LCD_PAL55_G14_0_Pos)                           /*!< LCD PAL55: G14_0 Mask               */
+#define LCD_PAL55_B14_0_Pos                                   26                                                        /*!< LCD PAL55: B14_0 Position           */
+#define LCD_PAL55_B14_0_Msk                                   (0x1fUL << LCD_PAL55_B14_0_Pos)                           /*!< LCD PAL55: B14_0 Mask               */
+#define LCD_PAL55_I1_Pos                                      31                                                        /*!< LCD PAL55: I1 Position              */
+#define LCD_PAL55_I1_Msk                                      (0x01UL << LCD_PAL55_I1_Pos)                              /*!< LCD PAL55: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL56  -------------------------------------------
+#define LCD_PAL56_R04_0_Pos                                   0                                                         /*!< LCD PAL56: R04_0 Position           */
+#define LCD_PAL56_R04_0_Msk                                   (0x1fUL << LCD_PAL56_R04_0_Pos)                           /*!< LCD PAL56: R04_0 Mask               */
+#define LCD_PAL56_G04_0_Pos                                   5                                                         /*!< LCD PAL56: G04_0 Position           */
+#define LCD_PAL56_G04_0_Msk                                   (0x1fUL << LCD_PAL56_G04_0_Pos)                           /*!< LCD PAL56: G04_0 Mask               */
+#define LCD_PAL56_B04_0_Pos                                   10                                                        /*!< LCD PAL56: B04_0 Position           */
+#define LCD_PAL56_B04_0_Msk                                   (0x1fUL << LCD_PAL56_B04_0_Pos)                           /*!< LCD PAL56: B04_0 Mask               */
+#define LCD_PAL56_I0_Pos                                      15                                                        /*!< LCD PAL56: I0 Position              */
+#define LCD_PAL56_I0_Msk                                      (0x01UL << LCD_PAL56_I0_Pos)                              /*!< LCD PAL56: I0 Mask                  */
+#define LCD_PAL56_R14_0_Pos                                   16                                                        /*!< LCD PAL56: R14_0 Position           */
+#define LCD_PAL56_R14_0_Msk                                   (0x1fUL << LCD_PAL56_R14_0_Pos)                           /*!< LCD PAL56: R14_0 Mask               */
+#define LCD_PAL56_G14_0_Pos                                   21                                                        /*!< LCD PAL56: G14_0 Position           */
+#define LCD_PAL56_G14_0_Msk                                   (0x1fUL << LCD_PAL56_G14_0_Pos)                           /*!< LCD PAL56: G14_0 Mask               */
+#define LCD_PAL56_B14_0_Pos                                   26                                                        /*!< LCD PAL56: B14_0 Position           */
+#define LCD_PAL56_B14_0_Msk                                   (0x1fUL << LCD_PAL56_B14_0_Pos)                           /*!< LCD PAL56: B14_0 Mask               */
+#define LCD_PAL56_I1_Pos                                      31                                                        /*!< LCD PAL56: I1 Position              */
+#define LCD_PAL56_I1_Msk                                      (0x01UL << LCD_PAL56_I1_Pos)                              /*!< LCD PAL56: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL57  -------------------------------------------
+#define LCD_PAL57_R04_0_Pos                                   0                                                         /*!< LCD PAL57: R04_0 Position           */
+#define LCD_PAL57_R04_0_Msk                                   (0x1fUL << LCD_PAL57_R04_0_Pos)                           /*!< LCD PAL57: R04_0 Mask               */
+#define LCD_PAL57_G04_0_Pos                                   5                                                         /*!< LCD PAL57: G04_0 Position           */
+#define LCD_PAL57_G04_0_Msk                                   (0x1fUL << LCD_PAL57_G04_0_Pos)                           /*!< LCD PAL57: G04_0 Mask               */
+#define LCD_PAL57_B04_0_Pos                                   10                                                        /*!< LCD PAL57: B04_0 Position           */
+#define LCD_PAL57_B04_0_Msk                                   (0x1fUL << LCD_PAL57_B04_0_Pos)                           /*!< LCD PAL57: B04_0 Mask               */
+#define LCD_PAL57_I0_Pos                                      15                                                        /*!< LCD PAL57: I0 Position              */
+#define LCD_PAL57_I0_Msk                                      (0x01UL << LCD_PAL57_I0_Pos)                              /*!< LCD PAL57: I0 Mask                  */
+#define LCD_PAL57_R14_0_Pos                                   16                                                        /*!< LCD PAL57: R14_0 Position           */
+#define LCD_PAL57_R14_0_Msk                                   (0x1fUL << LCD_PAL57_R14_0_Pos)                           /*!< LCD PAL57: R14_0 Mask               */
+#define LCD_PAL57_G14_0_Pos                                   21                                                        /*!< LCD PAL57: G14_0 Position           */
+#define LCD_PAL57_G14_0_Msk                                   (0x1fUL << LCD_PAL57_G14_0_Pos)                           /*!< LCD PAL57: G14_0 Mask               */
+#define LCD_PAL57_B14_0_Pos                                   26                                                        /*!< LCD PAL57: B14_0 Position           */
+#define LCD_PAL57_B14_0_Msk                                   (0x1fUL << LCD_PAL57_B14_0_Pos)                           /*!< LCD PAL57: B14_0 Mask               */
+#define LCD_PAL57_I1_Pos                                      31                                                        /*!< LCD PAL57: I1 Position              */
+#define LCD_PAL57_I1_Msk                                      (0x01UL << LCD_PAL57_I1_Pos)                              /*!< LCD PAL57: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL58  -------------------------------------------
+#define LCD_PAL58_R04_0_Pos                                   0                                                         /*!< LCD PAL58: R04_0 Position           */
+#define LCD_PAL58_R04_0_Msk                                   (0x1fUL << LCD_PAL58_R04_0_Pos)                           /*!< LCD PAL58: R04_0 Mask               */
+#define LCD_PAL58_G04_0_Pos                                   5                                                         /*!< LCD PAL58: G04_0 Position           */
+#define LCD_PAL58_G04_0_Msk                                   (0x1fUL << LCD_PAL58_G04_0_Pos)                           /*!< LCD PAL58: G04_0 Mask               */
+#define LCD_PAL58_B04_0_Pos                                   10                                                        /*!< LCD PAL58: B04_0 Position           */
+#define LCD_PAL58_B04_0_Msk                                   (0x1fUL << LCD_PAL58_B04_0_Pos)                           /*!< LCD PAL58: B04_0 Mask               */
+#define LCD_PAL58_I0_Pos                                      15                                                        /*!< LCD PAL58: I0 Position              */
+#define LCD_PAL58_I0_Msk                                      (0x01UL << LCD_PAL58_I0_Pos)                              /*!< LCD PAL58: I0 Mask                  */
+#define LCD_PAL58_R14_0_Pos                                   16                                                        /*!< LCD PAL58: R14_0 Position           */
+#define LCD_PAL58_R14_0_Msk                                   (0x1fUL << LCD_PAL58_R14_0_Pos)                           /*!< LCD PAL58: R14_0 Mask               */
+#define LCD_PAL58_G14_0_Pos                                   21                                                        /*!< LCD PAL58: G14_0 Position           */
+#define LCD_PAL58_G14_0_Msk                                   (0x1fUL << LCD_PAL58_G14_0_Pos)                           /*!< LCD PAL58: G14_0 Mask               */
+#define LCD_PAL58_B14_0_Pos                                   26                                                        /*!< LCD PAL58: B14_0 Position           */
+#define LCD_PAL58_B14_0_Msk                                   (0x1fUL << LCD_PAL58_B14_0_Pos)                           /*!< LCD PAL58: B14_0 Mask               */
+#define LCD_PAL58_I1_Pos                                      31                                                        /*!< LCD PAL58: I1 Position              */
+#define LCD_PAL58_I1_Msk                                      (0x01UL << LCD_PAL58_I1_Pos)                              /*!< LCD PAL58: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL59  -------------------------------------------
+#define LCD_PAL59_R04_0_Pos                                   0                                                         /*!< LCD PAL59: R04_0 Position           */
+#define LCD_PAL59_R04_0_Msk                                   (0x1fUL << LCD_PAL59_R04_0_Pos)                           /*!< LCD PAL59: R04_0 Mask               */
+#define LCD_PAL59_G04_0_Pos                                   5                                                         /*!< LCD PAL59: G04_0 Position           */
+#define LCD_PAL59_G04_0_Msk                                   (0x1fUL << LCD_PAL59_G04_0_Pos)                           /*!< LCD PAL59: G04_0 Mask               */
+#define LCD_PAL59_B04_0_Pos                                   10                                                        /*!< LCD PAL59: B04_0 Position           */
+#define LCD_PAL59_B04_0_Msk                                   (0x1fUL << LCD_PAL59_B04_0_Pos)                           /*!< LCD PAL59: B04_0 Mask               */
+#define LCD_PAL59_I0_Pos                                      15                                                        /*!< LCD PAL59: I0 Position              */
+#define LCD_PAL59_I0_Msk                                      (0x01UL << LCD_PAL59_I0_Pos)                              /*!< LCD PAL59: I0 Mask                  */
+#define LCD_PAL59_R14_0_Pos                                   16                                                        /*!< LCD PAL59: R14_0 Position           */
+#define LCD_PAL59_R14_0_Msk                                   (0x1fUL << LCD_PAL59_R14_0_Pos)                           /*!< LCD PAL59: R14_0 Mask               */
+#define LCD_PAL59_G14_0_Pos                                   21                                                        /*!< LCD PAL59: G14_0 Position           */
+#define LCD_PAL59_G14_0_Msk                                   (0x1fUL << LCD_PAL59_G14_0_Pos)                           /*!< LCD PAL59: G14_0 Mask               */
+#define LCD_PAL59_B14_0_Pos                                   26                                                        /*!< LCD PAL59: B14_0 Position           */
+#define LCD_PAL59_B14_0_Msk                                   (0x1fUL << LCD_PAL59_B14_0_Pos)                           /*!< LCD PAL59: B14_0 Mask               */
+#define LCD_PAL59_I1_Pos                                      31                                                        /*!< LCD PAL59: I1 Position              */
+#define LCD_PAL59_I1_Msk                                      (0x01UL << LCD_PAL59_I1_Pos)                              /*!< LCD PAL59: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL60  -------------------------------------------
+#define LCD_PAL60_R04_0_Pos                                   0                                                         /*!< LCD PAL60: R04_0 Position           */
+#define LCD_PAL60_R04_0_Msk                                   (0x1fUL << LCD_PAL60_R04_0_Pos)                           /*!< LCD PAL60: R04_0 Mask               */
+#define LCD_PAL60_G04_0_Pos                                   5                                                         /*!< LCD PAL60: G04_0 Position           */
+#define LCD_PAL60_G04_0_Msk                                   (0x1fUL << LCD_PAL60_G04_0_Pos)                           /*!< LCD PAL60: G04_0 Mask               */
+#define LCD_PAL60_B04_0_Pos                                   10                                                        /*!< LCD PAL60: B04_0 Position           */
+#define LCD_PAL60_B04_0_Msk                                   (0x1fUL << LCD_PAL60_B04_0_Pos)                           /*!< LCD PAL60: B04_0 Mask               */
+#define LCD_PAL60_I0_Pos                                      15                                                        /*!< LCD PAL60: I0 Position              */
+#define LCD_PAL60_I0_Msk                                      (0x01UL << LCD_PAL60_I0_Pos)                              /*!< LCD PAL60: I0 Mask                  */
+#define LCD_PAL60_R14_0_Pos                                   16                                                        /*!< LCD PAL60: R14_0 Position           */
+#define LCD_PAL60_R14_0_Msk                                   (0x1fUL << LCD_PAL60_R14_0_Pos)                           /*!< LCD PAL60: R14_0 Mask               */
+#define LCD_PAL60_G14_0_Pos                                   21                                                        /*!< LCD PAL60: G14_0 Position           */
+#define LCD_PAL60_G14_0_Msk                                   (0x1fUL << LCD_PAL60_G14_0_Pos)                           /*!< LCD PAL60: G14_0 Mask               */
+#define LCD_PAL60_B14_0_Pos                                   26                                                        /*!< LCD PAL60: B14_0 Position           */
+#define LCD_PAL60_B14_0_Msk                                   (0x1fUL << LCD_PAL60_B14_0_Pos)                           /*!< LCD PAL60: B14_0 Mask               */
+#define LCD_PAL60_I1_Pos                                      31                                                        /*!< LCD PAL60: I1 Position              */
+#define LCD_PAL60_I1_Msk                                      (0x01UL << LCD_PAL60_I1_Pos)                              /*!< LCD PAL60: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL61  -------------------------------------------
+#define LCD_PAL61_R04_0_Pos                                   0                                                         /*!< LCD PAL61: R04_0 Position           */
+#define LCD_PAL61_R04_0_Msk                                   (0x1fUL << LCD_PAL61_R04_0_Pos)                           /*!< LCD PAL61: R04_0 Mask               */
+#define LCD_PAL61_G04_0_Pos                                   5                                                         /*!< LCD PAL61: G04_0 Position           */
+#define LCD_PAL61_G04_0_Msk                                   (0x1fUL << LCD_PAL61_G04_0_Pos)                           /*!< LCD PAL61: G04_0 Mask               */
+#define LCD_PAL61_B04_0_Pos                                   10                                                        /*!< LCD PAL61: B04_0 Position           */
+#define LCD_PAL61_B04_0_Msk                                   (0x1fUL << LCD_PAL61_B04_0_Pos)                           /*!< LCD PAL61: B04_0 Mask               */
+#define LCD_PAL61_I0_Pos                                      15                                                        /*!< LCD PAL61: I0 Position              */
+#define LCD_PAL61_I0_Msk                                      (0x01UL << LCD_PAL61_I0_Pos)                              /*!< LCD PAL61: I0 Mask                  */
+#define LCD_PAL61_R14_0_Pos                                   16                                                        /*!< LCD PAL61: R14_0 Position           */
+#define LCD_PAL61_R14_0_Msk                                   (0x1fUL << LCD_PAL61_R14_0_Pos)                           /*!< LCD PAL61: R14_0 Mask               */
+#define LCD_PAL61_G14_0_Pos                                   21                                                        /*!< LCD PAL61: G14_0 Position           */
+#define LCD_PAL61_G14_0_Msk                                   (0x1fUL << LCD_PAL61_G14_0_Pos)                           /*!< LCD PAL61: G14_0 Mask               */
+#define LCD_PAL61_B14_0_Pos                                   26                                                        /*!< LCD PAL61: B14_0 Position           */
+#define LCD_PAL61_B14_0_Msk                                   (0x1fUL << LCD_PAL61_B14_0_Pos)                           /*!< LCD PAL61: B14_0 Mask               */
+#define LCD_PAL61_I1_Pos                                      31                                                        /*!< LCD PAL61: I1 Position              */
+#define LCD_PAL61_I1_Msk                                      (0x01UL << LCD_PAL61_I1_Pos)                              /*!< LCD PAL61: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL62  -------------------------------------------
+#define LCD_PAL62_R04_0_Pos                                   0                                                         /*!< LCD PAL62: R04_0 Position           */
+#define LCD_PAL62_R04_0_Msk                                   (0x1fUL << LCD_PAL62_R04_0_Pos)                           /*!< LCD PAL62: R04_0 Mask               */
+#define LCD_PAL62_G04_0_Pos                                   5                                                         /*!< LCD PAL62: G04_0 Position           */
+#define LCD_PAL62_G04_0_Msk                                   (0x1fUL << LCD_PAL62_G04_0_Pos)                           /*!< LCD PAL62: G04_0 Mask               */
+#define LCD_PAL62_B04_0_Pos                                   10                                                        /*!< LCD PAL62: B04_0 Position           */
+#define LCD_PAL62_B04_0_Msk                                   (0x1fUL << LCD_PAL62_B04_0_Pos)                           /*!< LCD PAL62: B04_0 Mask               */
+#define LCD_PAL62_I0_Pos                                      15                                                        /*!< LCD PAL62: I0 Position              */
+#define LCD_PAL62_I0_Msk                                      (0x01UL << LCD_PAL62_I0_Pos)                              /*!< LCD PAL62: I0 Mask                  */
+#define LCD_PAL62_R14_0_Pos                                   16                                                        /*!< LCD PAL62: R14_0 Position           */
+#define LCD_PAL62_R14_0_Msk                                   (0x1fUL << LCD_PAL62_R14_0_Pos)                           /*!< LCD PAL62: R14_0 Mask               */
+#define LCD_PAL62_G14_0_Pos                                   21                                                        /*!< LCD PAL62: G14_0 Position           */
+#define LCD_PAL62_G14_0_Msk                                   (0x1fUL << LCD_PAL62_G14_0_Pos)                           /*!< LCD PAL62: G14_0 Mask               */
+#define LCD_PAL62_B14_0_Pos                                   26                                                        /*!< LCD PAL62: B14_0 Position           */
+#define LCD_PAL62_B14_0_Msk                                   (0x1fUL << LCD_PAL62_B14_0_Pos)                           /*!< LCD PAL62: B14_0 Mask               */
+#define LCD_PAL62_I1_Pos                                      31                                                        /*!< LCD PAL62: I1 Position              */
+#define LCD_PAL62_I1_Msk                                      (0x01UL << LCD_PAL62_I1_Pos)                              /*!< LCD PAL62: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL63  -------------------------------------------
+#define LCD_PAL63_R04_0_Pos                                   0                                                         /*!< LCD PAL63: R04_0 Position           */
+#define LCD_PAL63_R04_0_Msk                                   (0x1fUL << LCD_PAL63_R04_0_Pos)                           /*!< LCD PAL63: R04_0 Mask               */
+#define LCD_PAL63_G04_0_Pos                                   5                                                         /*!< LCD PAL63: G04_0 Position           */
+#define LCD_PAL63_G04_0_Msk                                   (0x1fUL << LCD_PAL63_G04_0_Pos)                           /*!< LCD PAL63: G04_0 Mask               */
+#define LCD_PAL63_B04_0_Pos                                   10                                                        /*!< LCD PAL63: B04_0 Position           */
+#define LCD_PAL63_B04_0_Msk                                   (0x1fUL << LCD_PAL63_B04_0_Pos)                           /*!< LCD PAL63: B04_0 Mask               */
+#define LCD_PAL63_I0_Pos                                      15                                                        /*!< LCD PAL63: I0 Position              */
+#define LCD_PAL63_I0_Msk                                      (0x01UL << LCD_PAL63_I0_Pos)                              /*!< LCD PAL63: I0 Mask                  */
+#define LCD_PAL63_R14_0_Pos                                   16                                                        /*!< LCD PAL63: R14_0 Position           */
+#define LCD_PAL63_R14_0_Msk                                   (0x1fUL << LCD_PAL63_R14_0_Pos)                           /*!< LCD PAL63: R14_0 Mask               */
+#define LCD_PAL63_G14_0_Pos                                   21                                                        /*!< LCD PAL63: G14_0 Position           */
+#define LCD_PAL63_G14_0_Msk                                   (0x1fUL << LCD_PAL63_G14_0_Pos)                           /*!< LCD PAL63: G14_0 Mask               */
+#define LCD_PAL63_B14_0_Pos                                   26                                                        /*!< LCD PAL63: B14_0 Position           */
+#define LCD_PAL63_B14_0_Msk                                   (0x1fUL << LCD_PAL63_B14_0_Pos)                           /*!< LCD PAL63: B14_0 Mask               */
+#define LCD_PAL63_I1_Pos                                      31                                                        /*!< LCD PAL63: I1 Position              */
+#define LCD_PAL63_I1_Msk                                      (0x01UL << LCD_PAL63_I1_Pos)                              /*!< LCD PAL63: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL64  -------------------------------------------
+#define LCD_PAL64_R04_0_Pos                                   0                                                         /*!< LCD PAL64: R04_0 Position           */
+#define LCD_PAL64_R04_0_Msk                                   (0x1fUL << LCD_PAL64_R04_0_Pos)                           /*!< LCD PAL64: R04_0 Mask               */
+#define LCD_PAL64_G04_0_Pos                                   5                                                         /*!< LCD PAL64: G04_0 Position           */
+#define LCD_PAL64_G04_0_Msk                                   (0x1fUL << LCD_PAL64_G04_0_Pos)                           /*!< LCD PAL64: G04_0 Mask               */
+#define LCD_PAL64_B04_0_Pos                                   10                                                        /*!< LCD PAL64: B04_0 Position           */
+#define LCD_PAL64_B04_0_Msk                                   (0x1fUL << LCD_PAL64_B04_0_Pos)                           /*!< LCD PAL64: B04_0 Mask               */
+#define LCD_PAL64_I0_Pos                                      15                                                        /*!< LCD PAL64: I0 Position              */
+#define LCD_PAL64_I0_Msk                                      (0x01UL << LCD_PAL64_I0_Pos)                              /*!< LCD PAL64: I0 Mask                  */
+#define LCD_PAL64_R14_0_Pos                                   16                                                        /*!< LCD PAL64: R14_0 Position           */
+#define LCD_PAL64_R14_0_Msk                                   (0x1fUL << LCD_PAL64_R14_0_Pos)                           /*!< LCD PAL64: R14_0 Mask               */
+#define LCD_PAL64_G14_0_Pos                                   21                                                        /*!< LCD PAL64: G14_0 Position           */
+#define LCD_PAL64_G14_0_Msk                                   (0x1fUL << LCD_PAL64_G14_0_Pos)                           /*!< LCD PAL64: G14_0 Mask               */
+#define LCD_PAL64_B14_0_Pos                                   26                                                        /*!< LCD PAL64: B14_0 Position           */
+#define LCD_PAL64_B14_0_Msk                                   (0x1fUL << LCD_PAL64_B14_0_Pos)                           /*!< LCD PAL64: B14_0 Mask               */
+#define LCD_PAL64_I1_Pos                                      31                                                        /*!< LCD PAL64: I1 Position              */
+#define LCD_PAL64_I1_Msk                                      (0x01UL << LCD_PAL64_I1_Pos)                              /*!< LCD PAL64: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL65  -------------------------------------------
+#define LCD_PAL65_R04_0_Pos                                   0                                                         /*!< LCD PAL65: R04_0 Position           */
+#define LCD_PAL65_R04_0_Msk                                   (0x1fUL << LCD_PAL65_R04_0_Pos)                           /*!< LCD PAL65: R04_0 Mask               */
+#define LCD_PAL65_G04_0_Pos                                   5                                                         /*!< LCD PAL65: G04_0 Position           */
+#define LCD_PAL65_G04_0_Msk                                   (0x1fUL << LCD_PAL65_G04_0_Pos)                           /*!< LCD PAL65: G04_0 Mask               */
+#define LCD_PAL65_B04_0_Pos                                   10                                                        /*!< LCD PAL65: B04_0 Position           */
+#define LCD_PAL65_B04_0_Msk                                   (0x1fUL << LCD_PAL65_B04_0_Pos)                           /*!< LCD PAL65: B04_0 Mask               */
+#define LCD_PAL65_I0_Pos                                      15                                                        /*!< LCD PAL65: I0 Position              */
+#define LCD_PAL65_I0_Msk                                      (0x01UL << LCD_PAL65_I0_Pos)                              /*!< LCD PAL65: I0 Mask                  */
+#define LCD_PAL65_R14_0_Pos                                   16                                                        /*!< LCD PAL65: R14_0 Position           */
+#define LCD_PAL65_R14_0_Msk                                   (0x1fUL << LCD_PAL65_R14_0_Pos)                           /*!< LCD PAL65: R14_0 Mask               */
+#define LCD_PAL65_G14_0_Pos                                   21                                                        /*!< LCD PAL65: G14_0 Position           */
+#define LCD_PAL65_G14_0_Msk                                   (0x1fUL << LCD_PAL65_G14_0_Pos)                           /*!< LCD PAL65: G14_0 Mask               */
+#define LCD_PAL65_B14_0_Pos                                   26                                                        /*!< LCD PAL65: B14_0 Position           */
+#define LCD_PAL65_B14_0_Msk                                   (0x1fUL << LCD_PAL65_B14_0_Pos)                           /*!< LCD PAL65: B14_0 Mask               */
+#define LCD_PAL65_I1_Pos                                      31                                                        /*!< LCD PAL65: I1 Position              */
+#define LCD_PAL65_I1_Msk                                      (0x01UL << LCD_PAL65_I1_Pos)                              /*!< LCD PAL65: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL66  -------------------------------------------
+#define LCD_PAL66_R04_0_Pos                                   0                                                         /*!< LCD PAL66: R04_0 Position           */
+#define LCD_PAL66_R04_0_Msk                                   (0x1fUL << LCD_PAL66_R04_0_Pos)                           /*!< LCD PAL66: R04_0 Mask               */
+#define LCD_PAL66_G04_0_Pos                                   5                                                         /*!< LCD PAL66: G04_0 Position           */
+#define LCD_PAL66_G04_0_Msk                                   (0x1fUL << LCD_PAL66_G04_0_Pos)                           /*!< LCD PAL66: G04_0 Mask               */
+#define LCD_PAL66_B04_0_Pos                                   10                                                        /*!< LCD PAL66: B04_0 Position           */
+#define LCD_PAL66_B04_0_Msk                                   (0x1fUL << LCD_PAL66_B04_0_Pos)                           /*!< LCD PAL66: B04_0 Mask               */
+#define LCD_PAL66_I0_Pos                                      15                                                        /*!< LCD PAL66: I0 Position              */
+#define LCD_PAL66_I0_Msk                                      (0x01UL << LCD_PAL66_I0_Pos)                              /*!< LCD PAL66: I0 Mask                  */
+#define LCD_PAL66_R14_0_Pos                                   16                                                        /*!< LCD PAL66: R14_0 Position           */
+#define LCD_PAL66_R14_0_Msk                                   (0x1fUL << LCD_PAL66_R14_0_Pos)                           /*!< LCD PAL66: R14_0 Mask               */
+#define LCD_PAL66_G14_0_Pos                                   21                                                        /*!< LCD PAL66: G14_0 Position           */
+#define LCD_PAL66_G14_0_Msk                                   (0x1fUL << LCD_PAL66_G14_0_Pos)                           /*!< LCD PAL66: G14_0 Mask               */
+#define LCD_PAL66_B14_0_Pos                                   26                                                        /*!< LCD PAL66: B14_0 Position           */
+#define LCD_PAL66_B14_0_Msk                                   (0x1fUL << LCD_PAL66_B14_0_Pos)                           /*!< LCD PAL66: B14_0 Mask               */
+#define LCD_PAL66_I1_Pos                                      31                                                        /*!< LCD PAL66: I1 Position              */
+#define LCD_PAL66_I1_Msk                                      (0x01UL << LCD_PAL66_I1_Pos)                              /*!< LCD PAL66: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL67  -------------------------------------------
+#define LCD_PAL67_R04_0_Pos                                   0                                                         /*!< LCD PAL67: R04_0 Position           */
+#define LCD_PAL67_R04_0_Msk                                   (0x1fUL << LCD_PAL67_R04_0_Pos)                           /*!< LCD PAL67: R04_0 Mask               */
+#define LCD_PAL67_G04_0_Pos                                   5                                                         /*!< LCD PAL67: G04_0 Position           */
+#define LCD_PAL67_G04_0_Msk                                   (0x1fUL << LCD_PAL67_G04_0_Pos)                           /*!< LCD PAL67: G04_0 Mask               */
+#define LCD_PAL67_B04_0_Pos                                   10                                                        /*!< LCD PAL67: B04_0 Position           */
+#define LCD_PAL67_B04_0_Msk                                   (0x1fUL << LCD_PAL67_B04_0_Pos)                           /*!< LCD PAL67: B04_0 Mask               */
+#define LCD_PAL67_I0_Pos                                      15                                                        /*!< LCD PAL67: I0 Position              */
+#define LCD_PAL67_I0_Msk                                      (0x01UL << LCD_PAL67_I0_Pos)                              /*!< LCD PAL67: I0 Mask                  */
+#define LCD_PAL67_R14_0_Pos                                   16                                                        /*!< LCD PAL67: R14_0 Position           */
+#define LCD_PAL67_R14_0_Msk                                   (0x1fUL << LCD_PAL67_R14_0_Pos)                           /*!< LCD PAL67: R14_0 Mask               */
+#define LCD_PAL67_G14_0_Pos                                   21                                                        /*!< LCD PAL67: G14_0 Position           */
+#define LCD_PAL67_G14_0_Msk                                   (0x1fUL << LCD_PAL67_G14_0_Pos)                           /*!< LCD PAL67: G14_0 Mask               */
+#define LCD_PAL67_B14_0_Pos                                   26                                                        /*!< LCD PAL67: B14_0 Position           */
+#define LCD_PAL67_B14_0_Msk                                   (0x1fUL << LCD_PAL67_B14_0_Pos)                           /*!< LCD PAL67: B14_0 Mask               */
+#define LCD_PAL67_I1_Pos                                      31                                                        /*!< LCD PAL67: I1 Position              */
+#define LCD_PAL67_I1_Msk                                      (0x01UL << LCD_PAL67_I1_Pos)                              /*!< LCD PAL67: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL68  -------------------------------------------
+#define LCD_PAL68_R04_0_Pos                                   0                                                         /*!< LCD PAL68: R04_0 Position           */
+#define LCD_PAL68_R04_0_Msk                                   (0x1fUL << LCD_PAL68_R04_0_Pos)                           /*!< LCD PAL68: R04_0 Mask               */
+#define LCD_PAL68_G04_0_Pos                                   5                                                         /*!< LCD PAL68: G04_0 Position           */
+#define LCD_PAL68_G04_0_Msk                                   (0x1fUL << LCD_PAL68_G04_0_Pos)                           /*!< LCD PAL68: G04_0 Mask               */
+#define LCD_PAL68_B04_0_Pos                                   10                                                        /*!< LCD PAL68: B04_0 Position           */
+#define LCD_PAL68_B04_0_Msk                                   (0x1fUL << LCD_PAL68_B04_0_Pos)                           /*!< LCD PAL68: B04_0 Mask               */
+#define LCD_PAL68_I0_Pos                                      15                                                        /*!< LCD PAL68: I0 Position              */
+#define LCD_PAL68_I0_Msk                                      (0x01UL << LCD_PAL68_I0_Pos)                              /*!< LCD PAL68: I0 Mask                  */
+#define LCD_PAL68_R14_0_Pos                                   16                                                        /*!< LCD PAL68: R14_0 Position           */
+#define LCD_PAL68_R14_0_Msk                                   (0x1fUL << LCD_PAL68_R14_0_Pos)                           /*!< LCD PAL68: R14_0 Mask               */
+#define LCD_PAL68_G14_0_Pos                                   21                                                        /*!< LCD PAL68: G14_0 Position           */
+#define LCD_PAL68_G14_0_Msk                                   (0x1fUL << LCD_PAL68_G14_0_Pos)                           /*!< LCD PAL68: G14_0 Mask               */
+#define LCD_PAL68_B14_0_Pos                                   26                                                        /*!< LCD PAL68: B14_0 Position           */
+#define LCD_PAL68_B14_0_Msk                                   (0x1fUL << LCD_PAL68_B14_0_Pos)                           /*!< LCD PAL68: B14_0 Mask               */
+#define LCD_PAL68_I1_Pos                                      31                                                        /*!< LCD PAL68: I1 Position              */
+#define LCD_PAL68_I1_Msk                                      (0x01UL << LCD_PAL68_I1_Pos)                              /*!< LCD PAL68: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL69  -------------------------------------------
+#define LCD_PAL69_R04_0_Pos                                   0                                                         /*!< LCD PAL69: R04_0 Position           */
+#define LCD_PAL69_R04_0_Msk                                   (0x1fUL << LCD_PAL69_R04_0_Pos)                           /*!< LCD PAL69: R04_0 Mask               */
+#define LCD_PAL69_G04_0_Pos                                   5                                                         /*!< LCD PAL69: G04_0 Position           */
+#define LCD_PAL69_G04_0_Msk                                   (0x1fUL << LCD_PAL69_G04_0_Pos)                           /*!< LCD PAL69: G04_0 Mask               */
+#define LCD_PAL69_B04_0_Pos                                   10                                                        /*!< LCD PAL69: B04_0 Position           */
+#define LCD_PAL69_B04_0_Msk                                   (0x1fUL << LCD_PAL69_B04_0_Pos)                           /*!< LCD PAL69: B04_0 Mask               */
+#define LCD_PAL69_I0_Pos                                      15                                                        /*!< LCD PAL69: I0 Position              */
+#define LCD_PAL69_I0_Msk                                      (0x01UL << LCD_PAL69_I0_Pos)                              /*!< LCD PAL69: I0 Mask                  */
+#define LCD_PAL69_R14_0_Pos                                   16                                                        /*!< LCD PAL69: R14_0 Position           */
+#define LCD_PAL69_R14_0_Msk                                   (0x1fUL << LCD_PAL69_R14_0_Pos)                           /*!< LCD PAL69: R14_0 Mask               */
+#define LCD_PAL69_G14_0_Pos                                   21                                                        /*!< LCD PAL69: G14_0 Position           */
+#define LCD_PAL69_G14_0_Msk                                   (0x1fUL << LCD_PAL69_G14_0_Pos)                           /*!< LCD PAL69: G14_0 Mask               */
+#define LCD_PAL69_B14_0_Pos                                   26                                                        /*!< LCD PAL69: B14_0 Position           */
+#define LCD_PAL69_B14_0_Msk                                   (0x1fUL << LCD_PAL69_B14_0_Pos)                           /*!< LCD PAL69: B14_0 Mask               */
+#define LCD_PAL69_I1_Pos                                      31                                                        /*!< LCD PAL69: I1 Position              */
+#define LCD_PAL69_I1_Msk                                      (0x01UL << LCD_PAL69_I1_Pos)                              /*!< LCD PAL69: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL70  -------------------------------------------
+#define LCD_PAL70_R04_0_Pos                                   0                                                         /*!< LCD PAL70: R04_0 Position           */
+#define LCD_PAL70_R04_0_Msk                                   (0x1fUL << LCD_PAL70_R04_0_Pos)                           /*!< LCD PAL70: R04_0 Mask               */
+#define LCD_PAL70_G04_0_Pos                                   5                                                         /*!< LCD PAL70: G04_0 Position           */
+#define LCD_PAL70_G04_0_Msk                                   (0x1fUL << LCD_PAL70_G04_0_Pos)                           /*!< LCD PAL70: G04_0 Mask               */
+#define LCD_PAL70_B04_0_Pos                                   10                                                        /*!< LCD PAL70: B04_0 Position           */
+#define LCD_PAL70_B04_0_Msk                                   (0x1fUL << LCD_PAL70_B04_0_Pos)                           /*!< LCD PAL70: B04_0 Mask               */
+#define LCD_PAL70_I0_Pos                                      15                                                        /*!< LCD PAL70: I0 Position              */
+#define LCD_PAL70_I0_Msk                                      (0x01UL << LCD_PAL70_I0_Pos)                              /*!< LCD PAL70: I0 Mask                  */
+#define LCD_PAL70_R14_0_Pos                                   16                                                        /*!< LCD PAL70: R14_0 Position           */
+#define LCD_PAL70_R14_0_Msk                                   (0x1fUL << LCD_PAL70_R14_0_Pos)                           /*!< LCD PAL70: R14_0 Mask               */
+#define LCD_PAL70_G14_0_Pos                                   21                                                        /*!< LCD PAL70: G14_0 Position           */
+#define LCD_PAL70_G14_0_Msk                                   (0x1fUL << LCD_PAL70_G14_0_Pos)                           /*!< LCD PAL70: G14_0 Mask               */
+#define LCD_PAL70_B14_0_Pos                                   26                                                        /*!< LCD PAL70: B14_0 Position           */
+#define LCD_PAL70_B14_0_Msk                                   (0x1fUL << LCD_PAL70_B14_0_Pos)                           /*!< LCD PAL70: B14_0 Mask               */
+#define LCD_PAL70_I1_Pos                                      31                                                        /*!< LCD PAL70: I1 Position              */
+#define LCD_PAL70_I1_Msk                                      (0x01UL << LCD_PAL70_I1_Pos)                              /*!< LCD PAL70: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL71  -------------------------------------------
+#define LCD_PAL71_R04_0_Pos                                   0                                                         /*!< LCD PAL71: R04_0 Position           */
+#define LCD_PAL71_R04_0_Msk                                   (0x1fUL << LCD_PAL71_R04_0_Pos)                           /*!< LCD PAL71: R04_0 Mask               */
+#define LCD_PAL71_G04_0_Pos                                   5                                                         /*!< LCD PAL71: G04_0 Position           */
+#define LCD_PAL71_G04_0_Msk                                   (0x1fUL << LCD_PAL71_G04_0_Pos)                           /*!< LCD PAL71: G04_0 Mask               */
+#define LCD_PAL71_B04_0_Pos                                   10                                                        /*!< LCD PAL71: B04_0 Position           */
+#define LCD_PAL71_B04_0_Msk                                   (0x1fUL << LCD_PAL71_B04_0_Pos)                           /*!< LCD PAL71: B04_0 Mask               */
+#define LCD_PAL71_I0_Pos                                      15                                                        /*!< LCD PAL71: I0 Position              */
+#define LCD_PAL71_I0_Msk                                      (0x01UL << LCD_PAL71_I0_Pos)                              /*!< LCD PAL71: I0 Mask                  */
+#define LCD_PAL71_R14_0_Pos                                   16                                                        /*!< LCD PAL71: R14_0 Position           */
+#define LCD_PAL71_R14_0_Msk                                   (0x1fUL << LCD_PAL71_R14_0_Pos)                           /*!< LCD PAL71: R14_0 Mask               */
+#define LCD_PAL71_G14_0_Pos                                   21                                                        /*!< LCD PAL71: G14_0 Position           */
+#define LCD_PAL71_G14_0_Msk                                   (0x1fUL << LCD_PAL71_G14_0_Pos)                           /*!< LCD PAL71: G14_0 Mask               */
+#define LCD_PAL71_B14_0_Pos                                   26                                                        /*!< LCD PAL71: B14_0 Position           */
+#define LCD_PAL71_B14_0_Msk                                   (0x1fUL << LCD_PAL71_B14_0_Pos)                           /*!< LCD PAL71: B14_0 Mask               */
+#define LCD_PAL71_I1_Pos                                      31                                                        /*!< LCD PAL71: I1 Position              */
+#define LCD_PAL71_I1_Msk                                      (0x01UL << LCD_PAL71_I1_Pos)                              /*!< LCD PAL71: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL72  -------------------------------------------
+#define LCD_PAL72_R04_0_Pos                                   0                                                         /*!< LCD PAL72: R04_0 Position           */
+#define LCD_PAL72_R04_0_Msk                                   (0x1fUL << LCD_PAL72_R04_0_Pos)                           /*!< LCD PAL72: R04_0 Mask               */
+#define LCD_PAL72_G04_0_Pos                                   5                                                         /*!< LCD PAL72: G04_0 Position           */
+#define LCD_PAL72_G04_0_Msk                                   (0x1fUL << LCD_PAL72_G04_0_Pos)                           /*!< LCD PAL72: G04_0 Mask               */
+#define LCD_PAL72_B04_0_Pos                                   10                                                        /*!< LCD PAL72: B04_0 Position           */
+#define LCD_PAL72_B04_0_Msk                                   (0x1fUL << LCD_PAL72_B04_0_Pos)                           /*!< LCD PAL72: B04_0 Mask               */
+#define LCD_PAL72_I0_Pos                                      15                                                        /*!< LCD PAL72: I0 Position              */
+#define LCD_PAL72_I0_Msk                                      (0x01UL << LCD_PAL72_I0_Pos)                              /*!< LCD PAL72: I0 Mask                  */
+#define LCD_PAL72_R14_0_Pos                                   16                                                        /*!< LCD PAL72: R14_0 Position           */
+#define LCD_PAL72_R14_0_Msk                                   (0x1fUL << LCD_PAL72_R14_0_Pos)                           /*!< LCD PAL72: R14_0 Mask               */
+#define LCD_PAL72_G14_0_Pos                                   21                                                        /*!< LCD PAL72: G14_0 Position           */
+#define LCD_PAL72_G14_0_Msk                                   (0x1fUL << LCD_PAL72_G14_0_Pos)                           /*!< LCD PAL72: G14_0 Mask               */
+#define LCD_PAL72_B14_0_Pos                                   26                                                        /*!< LCD PAL72: B14_0 Position           */
+#define LCD_PAL72_B14_0_Msk                                   (0x1fUL << LCD_PAL72_B14_0_Pos)                           /*!< LCD PAL72: B14_0 Mask               */
+#define LCD_PAL72_I1_Pos                                      31                                                        /*!< LCD PAL72: I1 Position              */
+#define LCD_PAL72_I1_Msk                                      (0x01UL << LCD_PAL72_I1_Pos)                              /*!< LCD PAL72: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL73  -------------------------------------------
+#define LCD_PAL73_R04_0_Pos                                   0                                                         /*!< LCD PAL73: R04_0 Position           */
+#define LCD_PAL73_R04_0_Msk                                   (0x1fUL << LCD_PAL73_R04_0_Pos)                           /*!< LCD PAL73: R04_0 Mask               */
+#define LCD_PAL73_G04_0_Pos                                   5                                                         /*!< LCD PAL73: G04_0 Position           */
+#define LCD_PAL73_G04_0_Msk                                   (0x1fUL << LCD_PAL73_G04_0_Pos)                           /*!< LCD PAL73: G04_0 Mask               */
+#define LCD_PAL73_B04_0_Pos                                   10                                                        /*!< LCD PAL73: B04_0 Position           */
+#define LCD_PAL73_B04_0_Msk                                   (0x1fUL << LCD_PAL73_B04_0_Pos)                           /*!< LCD PAL73: B04_0 Mask               */
+#define LCD_PAL73_I0_Pos                                      15                                                        /*!< LCD PAL73: I0 Position              */
+#define LCD_PAL73_I0_Msk                                      (0x01UL << LCD_PAL73_I0_Pos)                              /*!< LCD PAL73: I0 Mask                  */
+#define LCD_PAL73_R14_0_Pos                                   16                                                        /*!< LCD PAL73: R14_0 Position           */
+#define LCD_PAL73_R14_0_Msk                                   (0x1fUL << LCD_PAL73_R14_0_Pos)                           /*!< LCD PAL73: R14_0 Mask               */
+#define LCD_PAL73_G14_0_Pos                                   21                                                        /*!< LCD PAL73: G14_0 Position           */
+#define LCD_PAL73_G14_0_Msk                                   (0x1fUL << LCD_PAL73_G14_0_Pos)                           /*!< LCD PAL73: G14_0 Mask               */
+#define LCD_PAL73_B14_0_Pos                                   26                                                        /*!< LCD PAL73: B14_0 Position           */
+#define LCD_PAL73_B14_0_Msk                                   (0x1fUL << LCD_PAL73_B14_0_Pos)                           /*!< LCD PAL73: B14_0 Mask               */
+#define LCD_PAL73_I1_Pos                                      31                                                        /*!< LCD PAL73: I1 Position              */
+#define LCD_PAL73_I1_Msk                                      (0x01UL << LCD_PAL73_I1_Pos)                              /*!< LCD PAL73: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL74  -------------------------------------------
+#define LCD_PAL74_R04_0_Pos                                   0                                                         /*!< LCD PAL74: R04_0 Position           */
+#define LCD_PAL74_R04_0_Msk                                   (0x1fUL << LCD_PAL74_R04_0_Pos)                           /*!< LCD PAL74: R04_0 Mask               */
+#define LCD_PAL74_G04_0_Pos                                   5                                                         /*!< LCD PAL74: G04_0 Position           */
+#define LCD_PAL74_G04_0_Msk                                   (0x1fUL << LCD_PAL74_G04_0_Pos)                           /*!< LCD PAL74: G04_0 Mask               */
+#define LCD_PAL74_B04_0_Pos                                   10                                                        /*!< LCD PAL74: B04_0 Position           */
+#define LCD_PAL74_B04_0_Msk                                   (0x1fUL << LCD_PAL74_B04_0_Pos)                           /*!< LCD PAL74: B04_0 Mask               */
+#define LCD_PAL74_I0_Pos                                      15                                                        /*!< LCD PAL74: I0 Position              */
+#define LCD_PAL74_I0_Msk                                      (0x01UL << LCD_PAL74_I0_Pos)                              /*!< LCD PAL74: I0 Mask                  */
+#define LCD_PAL74_R14_0_Pos                                   16                                                        /*!< LCD PAL74: R14_0 Position           */
+#define LCD_PAL74_R14_0_Msk                                   (0x1fUL << LCD_PAL74_R14_0_Pos)                           /*!< LCD PAL74: R14_0 Mask               */
+#define LCD_PAL74_G14_0_Pos                                   21                                                        /*!< LCD PAL74: G14_0 Position           */
+#define LCD_PAL74_G14_0_Msk                                   (0x1fUL << LCD_PAL74_G14_0_Pos)                           /*!< LCD PAL74: G14_0 Mask               */
+#define LCD_PAL74_B14_0_Pos                                   26                                                        /*!< LCD PAL74: B14_0 Position           */
+#define LCD_PAL74_B14_0_Msk                                   (0x1fUL << LCD_PAL74_B14_0_Pos)                           /*!< LCD PAL74: B14_0 Mask               */
+#define LCD_PAL74_I1_Pos                                      31                                                        /*!< LCD PAL74: I1 Position              */
+#define LCD_PAL74_I1_Msk                                      (0x01UL << LCD_PAL74_I1_Pos)                              /*!< LCD PAL74: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL75  -------------------------------------------
+#define LCD_PAL75_R04_0_Pos                                   0                                                         /*!< LCD PAL75: R04_0 Position           */
+#define LCD_PAL75_R04_0_Msk                                   (0x1fUL << LCD_PAL75_R04_0_Pos)                           /*!< LCD PAL75: R04_0 Mask               */
+#define LCD_PAL75_G04_0_Pos                                   5                                                         /*!< LCD PAL75: G04_0 Position           */
+#define LCD_PAL75_G04_0_Msk                                   (0x1fUL << LCD_PAL75_G04_0_Pos)                           /*!< LCD PAL75: G04_0 Mask               */
+#define LCD_PAL75_B04_0_Pos                                   10                                                        /*!< LCD PAL75: B04_0 Position           */
+#define LCD_PAL75_B04_0_Msk                                   (0x1fUL << LCD_PAL75_B04_0_Pos)                           /*!< LCD PAL75: B04_0 Mask               */
+#define LCD_PAL75_I0_Pos                                      15                                                        /*!< LCD PAL75: I0 Position              */
+#define LCD_PAL75_I0_Msk                                      (0x01UL << LCD_PAL75_I0_Pos)                              /*!< LCD PAL75: I0 Mask                  */
+#define LCD_PAL75_R14_0_Pos                                   16                                                        /*!< LCD PAL75: R14_0 Position           */
+#define LCD_PAL75_R14_0_Msk                                   (0x1fUL << LCD_PAL75_R14_0_Pos)                           /*!< LCD PAL75: R14_0 Mask               */
+#define LCD_PAL75_G14_0_Pos                                   21                                                        /*!< LCD PAL75: G14_0 Position           */
+#define LCD_PAL75_G14_0_Msk                                   (0x1fUL << LCD_PAL75_G14_0_Pos)                           /*!< LCD PAL75: G14_0 Mask               */
+#define LCD_PAL75_B14_0_Pos                                   26                                                        /*!< LCD PAL75: B14_0 Position           */
+#define LCD_PAL75_B14_0_Msk                                   (0x1fUL << LCD_PAL75_B14_0_Pos)                           /*!< LCD PAL75: B14_0 Mask               */
+#define LCD_PAL75_I1_Pos                                      31                                                        /*!< LCD PAL75: I1 Position              */
+#define LCD_PAL75_I1_Msk                                      (0x01UL << LCD_PAL75_I1_Pos)                              /*!< LCD PAL75: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL76  -------------------------------------------
+#define LCD_PAL76_R04_0_Pos                                   0                                                         /*!< LCD PAL76: R04_0 Position           */
+#define LCD_PAL76_R04_0_Msk                                   (0x1fUL << LCD_PAL76_R04_0_Pos)                           /*!< LCD PAL76: R04_0 Mask               */
+#define LCD_PAL76_G04_0_Pos                                   5                                                         /*!< LCD PAL76: G04_0 Position           */
+#define LCD_PAL76_G04_0_Msk                                   (0x1fUL << LCD_PAL76_G04_0_Pos)                           /*!< LCD PAL76: G04_0 Mask               */
+#define LCD_PAL76_B04_0_Pos                                   10                                                        /*!< LCD PAL76: B04_0 Position           */
+#define LCD_PAL76_B04_0_Msk                                   (0x1fUL << LCD_PAL76_B04_0_Pos)                           /*!< LCD PAL76: B04_0 Mask               */
+#define LCD_PAL76_I0_Pos                                      15                                                        /*!< LCD PAL76: I0 Position              */
+#define LCD_PAL76_I0_Msk                                      (0x01UL << LCD_PAL76_I0_Pos)                              /*!< LCD PAL76: I0 Mask                  */
+#define LCD_PAL76_R14_0_Pos                                   16                                                        /*!< LCD PAL76: R14_0 Position           */
+#define LCD_PAL76_R14_0_Msk                                   (0x1fUL << LCD_PAL76_R14_0_Pos)                           /*!< LCD PAL76: R14_0 Mask               */
+#define LCD_PAL76_G14_0_Pos                                   21                                                        /*!< LCD PAL76: G14_0 Position           */
+#define LCD_PAL76_G14_0_Msk                                   (0x1fUL << LCD_PAL76_G14_0_Pos)                           /*!< LCD PAL76: G14_0 Mask               */
+#define LCD_PAL76_B14_0_Pos                                   26                                                        /*!< LCD PAL76: B14_0 Position           */
+#define LCD_PAL76_B14_0_Msk                                   (0x1fUL << LCD_PAL76_B14_0_Pos)                           /*!< LCD PAL76: B14_0 Mask               */
+#define LCD_PAL76_I1_Pos                                      31                                                        /*!< LCD PAL76: I1 Position              */
+#define LCD_PAL76_I1_Msk                                      (0x01UL << LCD_PAL76_I1_Pos)                              /*!< LCD PAL76: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL77  -------------------------------------------
+#define LCD_PAL77_R04_0_Pos                                   0                                                         /*!< LCD PAL77: R04_0 Position           */
+#define LCD_PAL77_R04_0_Msk                                   (0x1fUL << LCD_PAL77_R04_0_Pos)                           /*!< LCD PAL77: R04_0 Mask               */
+#define LCD_PAL77_G04_0_Pos                                   5                                                         /*!< LCD PAL77: G04_0 Position           */
+#define LCD_PAL77_G04_0_Msk                                   (0x1fUL << LCD_PAL77_G04_0_Pos)                           /*!< LCD PAL77: G04_0 Mask               */
+#define LCD_PAL77_B04_0_Pos                                   10                                                        /*!< LCD PAL77: B04_0 Position           */
+#define LCD_PAL77_B04_0_Msk                                   (0x1fUL << LCD_PAL77_B04_0_Pos)                           /*!< LCD PAL77: B04_0 Mask               */
+#define LCD_PAL77_I0_Pos                                      15                                                        /*!< LCD PAL77: I0 Position              */
+#define LCD_PAL77_I0_Msk                                      (0x01UL << LCD_PAL77_I0_Pos)                              /*!< LCD PAL77: I0 Mask                  */
+#define LCD_PAL77_R14_0_Pos                                   16                                                        /*!< LCD PAL77: R14_0 Position           */
+#define LCD_PAL77_R14_0_Msk                                   (0x1fUL << LCD_PAL77_R14_0_Pos)                           /*!< LCD PAL77: R14_0 Mask               */
+#define LCD_PAL77_G14_0_Pos                                   21                                                        /*!< LCD PAL77: G14_0 Position           */
+#define LCD_PAL77_G14_0_Msk                                   (0x1fUL << LCD_PAL77_G14_0_Pos)                           /*!< LCD PAL77: G14_0 Mask               */
+#define LCD_PAL77_B14_0_Pos                                   26                                                        /*!< LCD PAL77: B14_0 Position           */
+#define LCD_PAL77_B14_0_Msk                                   (0x1fUL << LCD_PAL77_B14_0_Pos)                           /*!< LCD PAL77: B14_0 Mask               */
+#define LCD_PAL77_I1_Pos                                      31                                                        /*!< LCD PAL77: I1 Position              */
+#define LCD_PAL77_I1_Msk                                      (0x01UL << LCD_PAL77_I1_Pos)                              /*!< LCD PAL77: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL78  -------------------------------------------
+#define LCD_PAL78_R04_0_Pos                                   0                                                         /*!< LCD PAL78: R04_0 Position           */
+#define LCD_PAL78_R04_0_Msk                                   (0x1fUL << LCD_PAL78_R04_0_Pos)                           /*!< LCD PAL78: R04_0 Mask               */
+#define LCD_PAL78_G04_0_Pos                                   5                                                         /*!< LCD PAL78: G04_0 Position           */
+#define LCD_PAL78_G04_0_Msk                                   (0x1fUL << LCD_PAL78_G04_0_Pos)                           /*!< LCD PAL78: G04_0 Mask               */
+#define LCD_PAL78_B04_0_Pos                                   10                                                        /*!< LCD PAL78: B04_0 Position           */
+#define LCD_PAL78_B04_0_Msk                                   (0x1fUL << LCD_PAL78_B04_0_Pos)                           /*!< LCD PAL78: B04_0 Mask               */
+#define LCD_PAL78_I0_Pos                                      15                                                        /*!< LCD PAL78: I0 Position              */
+#define LCD_PAL78_I0_Msk                                      (0x01UL << LCD_PAL78_I0_Pos)                              /*!< LCD PAL78: I0 Mask                  */
+#define LCD_PAL78_R14_0_Pos                                   16                                                        /*!< LCD PAL78: R14_0 Position           */
+#define LCD_PAL78_R14_0_Msk                                   (0x1fUL << LCD_PAL78_R14_0_Pos)                           /*!< LCD PAL78: R14_0 Mask               */
+#define LCD_PAL78_G14_0_Pos                                   21                                                        /*!< LCD PAL78: G14_0 Position           */
+#define LCD_PAL78_G14_0_Msk                                   (0x1fUL << LCD_PAL78_G14_0_Pos)                           /*!< LCD PAL78: G14_0 Mask               */
+#define LCD_PAL78_B14_0_Pos                                   26                                                        /*!< LCD PAL78: B14_0 Position           */
+#define LCD_PAL78_B14_0_Msk                                   (0x1fUL << LCD_PAL78_B14_0_Pos)                           /*!< LCD PAL78: B14_0 Mask               */
+#define LCD_PAL78_I1_Pos                                      31                                                        /*!< LCD PAL78: I1 Position              */
+#define LCD_PAL78_I1_Msk                                      (0x01UL << LCD_PAL78_I1_Pos)                              /*!< LCD PAL78: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL79  -------------------------------------------
+#define LCD_PAL79_R04_0_Pos                                   0                                                         /*!< LCD PAL79: R04_0 Position           */
+#define LCD_PAL79_R04_0_Msk                                   (0x1fUL << LCD_PAL79_R04_0_Pos)                           /*!< LCD PAL79: R04_0 Mask               */
+#define LCD_PAL79_G04_0_Pos                                   5                                                         /*!< LCD PAL79: G04_0 Position           */
+#define LCD_PAL79_G04_0_Msk                                   (0x1fUL << LCD_PAL79_G04_0_Pos)                           /*!< LCD PAL79: G04_0 Mask               */
+#define LCD_PAL79_B04_0_Pos                                   10                                                        /*!< LCD PAL79: B04_0 Position           */
+#define LCD_PAL79_B04_0_Msk                                   (0x1fUL << LCD_PAL79_B04_0_Pos)                           /*!< LCD PAL79: B04_0 Mask               */
+#define LCD_PAL79_I0_Pos                                      15                                                        /*!< LCD PAL79: I0 Position              */
+#define LCD_PAL79_I0_Msk                                      (0x01UL << LCD_PAL79_I0_Pos)                              /*!< LCD PAL79: I0 Mask                  */
+#define LCD_PAL79_R14_0_Pos                                   16                                                        /*!< LCD PAL79: R14_0 Position           */
+#define LCD_PAL79_R14_0_Msk                                   (0x1fUL << LCD_PAL79_R14_0_Pos)                           /*!< LCD PAL79: R14_0 Mask               */
+#define LCD_PAL79_G14_0_Pos                                   21                                                        /*!< LCD PAL79: G14_0 Position           */
+#define LCD_PAL79_G14_0_Msk                                   (0x1fUL << LCD_PAL79_G14_0_Pos)                           /*!< LCD PAL79: G14_0 Mask               */
+#define LCD_PAL79_B14_0_Pos                                   26                                                        /*!< LCD PAL79: B14_0 Position           */
+#define LCD_PAL79_B14_0_Msk                                   (0x1fUL << LCD_PAL79_B14_0_Pos)                           /*!< LCD PAL79: B14_0 Mask               */
+#define LCD_PAL79_I1_Pos                                      31                                                        /*!< LCD PAL79: I1 Position              */
+#define LCD_PAL79_I1_Msk                                      (0x01UL << LCD_PAL79_I1_Pos)                              /*!< LCD PAL79: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL80  -------------------------------------------
+#define LCD_PAL80_R04_0_Pos                                   0                                                         /*!< LCD PAL80: R04_0 Position           */
+#define LCD_PAL80_R04_0_Msk                                   (0x1fUL << LCD_PAL80_R04_0_Pos)                           /*!< LCD PAL80: R04_0 Mask               */
+#define LCD_PAL80_G04_0_Pos                                   5                                                         /*!< LCD PAL80: G04_0 Position           */
+#define LCD_PAL80_G04_0_Msk                                   (0x1fUL << LCD_PAL80_G04_0_Pos)                           /*!< LCD PAL80: G04_0 Mask               */
+#define LCD_PAL80_B04_0_Pos                                   10                                                        /*!< LCD PAL80: B04_0 Position           */
+#define LCD_PAL80_B04_0_Msk                                   (0x1fUL << LCD_PAL80_B04_0_Pos)                           /*!< LCD PAL80: B04_0 Mask               */
+#define LCD_PAL80_I0_Pos                                      15                                                        /*!< LCD PAL80: I0 Position              */
+#define LCD_PAL80_I0_Msk                                      (0x01UL << LCD_PAL80_I0_Pos)                              /*!< LCD PAL80: I0 Mask                  */
+#define LCD_PAL80_R14_0_Pos                                   16                                                        /*!< LCD PAL80: R14_0 Position           */
+#define LCD_PAL80_R14_0_Msk                                   (0x1fUL << LCD_PAL80_R14_0_Pos)                           /*!< LCD PAL80: R14_0 Mask               */
+#define LCD_PAL80_G14_0_Pos                                   21                                                        /*!< LCD PAL80: G14_0 Position           */
+#define LCD_PAL80_G14_0_Msk                                   (0x1fUL << LCD_PAL80_G14_0_Pos)                           /*!< LCD PAL80: G14_0 Mask               */
+#define LCD_PAL80_B14_0_Pos                                   26                                                        /*!< LCD PAL80: B14_0 Position           */
+#define LCD_PAL80_B14_0_Msk                                   (0x1fUL << LCD_PAL80_B14_0_Pos)                           /*!< LCD PAL80: B14_0 Mask               */
+#define LCD_PAL80_I1_Pos                                      31                                                        /*!< LCD PAL80: I1 Position              */
+#define LCD_PAL80_I1_Msk                                      (0x01UL << LCD_PAL80_I1_Pos)                              /*!< LCD PAL80: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL81  -------------------------------------------
+#define LCD_PAL81_R04_0_Pos                                   0                                                         /*!< LCD PAL81: R04_0 Position           */
+#define LCD_PAL81_R04_0_Msk                                   (0x1fUL << LCD_PAL81_R04_0_Pos)                           /*!< LCD PAL81: R04_0 Mask               */
+#define LCD_PAL81_G04_0_Pos                                   5                                                         /*!< LCD PAL81: G04_0 Position           */
+#define LCD_PAL81_G04_0_Msk                                   (0x1fUL << LCD_PAL81_G04_0_Pos)                           /*!< LCD PAL81: G04_0 Mask               */
+#define LCD_PAL81_B04_0_Pos                                   10                                                        /*!< LCD PAL81: B04_0 Position           */
+#define LCD_PAL81_B04_0_Msk                                   (0x1fUL << LCD_PAL81_B04_0_Pos)                           /*!< LCD PAL81: B04_0 Mask               */
+#define LCD_PAL81_I0_Pos                                      15                                                        /*!< LCD PAL81: I0 Position              */
+#define LCD_PAL81_I0_Msk                                      (0x01UL << LCD_PAL81_I0_Pos)                              /*!< LCD PAL81: I0 Mask                  */
+#define LCD_PAL81_R14_0_Pos                                   16                                                        /*!< LCD PAL81: R14_0 Position           */
+#define LCD_PAL81_R14_0_Msk                                   (0x1fUL << LCD_PAL81_R14_0_Pos)                           /*!< LCD PAL81: R14_0 Mask               */
+#define LCD_PAL81_G14_0_Pos                                   21                                                        /*!< LCD PAL81: G14_0 Position           */
+#define LCD_PAL81_G14_0_Msk                                   (0x1fUL << LCD_PAL81_G14_0_Pos)                           /*!< LCD PAL81: G14_0 Mask               */
+#define LCD_PAL81_B14_0_Pos                                   26                                                        /*!< LCD PAL81: B14_0 Position           */
+#define LCD_PAL81_B14_0_Msk                                   (0x1fUL << LCD_PAL81_B14_0_Pos)                           /*!< LCD PAL81: B14_0 Mask               */
+#define LCD_PAL81_I1_Pos                                      31                                                        /*!< LCD PAL81: I1 Position              */
+#define LCD_PAL81_I1_Msk                                      (0x01UL << LCD_PAL81_I1_Pos)                              /*!< LCD PAL81: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL82  -------------------------------------------
+#define LCD_PAL82_R04_0_Pos                                   0                                                         /*!< LCD PAL82: R04_0 Position           */
+#define LCD_PAL82_R04_0_Msk                                   (0x1fUL << LCD_PAL82_R04_0_Pos)                           /*!< LCD PAL82: R04_0 Mask               */
+#define LCD_PAL82_G04_0_Pos                                   5                                                         /*!< LCD PAL82: G04_0 Position           */
+#define LCD_PAL82_G04_0_Msk                                   (0x1fUL << LCD_PAL82_G04_0_Pos)                           /*!< LCD PAL82: G04_0 Mask               */
+#define LCD_PAL82_B04_0_Pos                                   10                                                        /*!< LCD PAL82: B04_0 Position           */
+#define LCD_PAL82_B04_0_Msk                                   (0x1fUL << LCD_PAL82_B04_0_Pos)                           /*!< LCD PAL82: B04_0 Mask               */
+#define LCD_PAL82_I0_Pos                                      15                                                        /*!< LCD PAL82: I0 Position              */
+#define LCD_PAL82_I0_Msk                                      (0x01UL << LCD_PAL82_I0_Pos)                              /*!< LCD PAL82: I0 Mask                  */
+#define LCD_PAL82_R14_0_Pos                                   16                                                        /*!< LCD PAL82: R14_0 Position           */
+#define LCD_PAL82_R14_0_Msk                                   (0x1fUL << LCD_PAL82_R14_0_Pos)                           /*!< LCD PAL82: R14_0 Mask               */
+#define LCD_PAL82_G14_0_Pos                                   21                                                        /*!< LCD PAL82: G14_0 Position           */
+#define LCD_PAL82_G14_0_Msk                                   (0x1fUL << LCD_PAL82_G14_0_Pos)                           /*!< LCD PAL82: G14_0 Mask               */
+#define LCD_PAL82_B14_0_Pos                                   26                                                        /*!< LCD PAL82: B14_0 Position           */
+#define LCD_PAL82_B14_0_Msk                                   (0x1fUL << LCD_PAL82_B14_0_Pos)                           /*!< LCD PAL82: B14_0 Mask               */
+#define LCD_PAL82_I1_Pos                                      31                                                        /*!< LCD PAL82: I1 Position              */
+#define LCD_PAL82_I1_Msk                                      (0x01UL << LCD_PAL82_I1_Pos)                              /*!< LCD PAL82: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL83  -------------------------------------------
+#define LCD_PAL83_R04_0_Pos                                   0                                                         /*!< LCD PAL83: R04_0 Position           */
+#define LCD_PAL83_R04_0_Msk                                   (0x1fUL << LCD_PAL83_R04_0_Pos)                           /*!< LCD PAL83: R04_0 Mask               */
+#define LCD_PAL83_G04_0_Pos                                   5                                                         /*!< LCD PAL83: G04_0 Position           */
+#define LCD_PAL83_G04_0_Msk                                   (0x1fUL << LCD_PAL83_G04_0_Pos)                           /*!< LCD PAL83: G04_0 Mask               */
+#define LCD_PAL83_B04_0_Pos                                   10                                                        /*!< LCD PAL83: B04_0 Position           */
+#define LCD_PAL83_B04_0_Msk                                   (0x1fUL << LCD_PAL83_B04_0_Pos)                           /*!< LCD PAL83: B04_0 Mask               */
+#define LCD_PAL83_I0_Pos                                      15                                                        /*!< LCD PAL83: I0 Position              */
+#define LCD_PAL83_I0_Msk                                      (0x01UL << LCD_PAL83_I0_Pos)                              /*!< LCD PAL83: I0 Mask                  */
+#define LCD_PAL83_R14_0_Pos                                   16                                                        /*!< LCD PAL83: R14_0 Position           */
+#define LCD_PAL83_R14_0_Msk                                   (0x1fUL << LCD_PAL83_R14_0_Pos)                           /*!< LCD PAL83: R14_0 Mask               */
+#define LCD_PAL83_G14_0_Pos                                   21                                                        /*!< LCD PAL83: G14_0 Position           */
+#define LCD_PAL83_G14_0_Msk                                   (0x1fUL << LCD_PAL83_G14_0_Pos)                           /*!< LCD PAL83: G14_0 Mask               */
+#define LCD_PAL83_B14_0_Pos                                   26                                                        /*!< LCD PAL83: B14_0 Position           */
+#define LCD_PAL83_B14_0_Msk                                   (0x1fUL << LCD_PAL83_B14_0_Pos)                           /*!< LCD PAL83: B14_0 Mask               */
+#define LCD_PAL83_I1_Pos                                      31                                                        /*!< LCD PAL83: I1 Position              */
+#define LCD_PAL83_I1_Msk                                      (0x01UL << LCD_PAL83_I1_Pos)                              /*!< LCD PAL83: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL84  -------------------------------------------
+#define LCD_PAL84_R04_0_Pos                                   0                                                         /*!< LCD PAL84: R04_0 Position           */
+#define LCD_PAL84_R04_0_Msk                                   (0x1fUL << LCD_PAL84_R04_0_Pos)                           /*!< LCD PAL84: R04_0 Mask               */
+#define LCD_PAL84_G04_0_Pos                                   5                                                         /*!< LCD PAL84: G04_0 Position           */
+#define LCD_PAL84_G04_0_Msk                                   (0x1fUL << LCD_PAL84_G04_0_Pos)                           /*!< LCD PAL84: G04_0 Mask               */
+#define LCD_PAL84_B04_0_Pos                                   10                                                        /*!< LCD PAL84: B04_0 Position           */
+#define LCD_PAL84_B04_0_Msk                                   (0x1fUL << LCD_PAL84_B04_0_Pos)                           /*!< LCD PAL84: B04_0 Mask               */
+#define LCD_PAL84_I0_Pos                                      15                                                        /*!< LCD PAL84: I0 Position              */
+#define LCD_PAL84_I0_Msk                                      (0x01UL << LCD_PAL84_I0_Pos)                              /*!< LCD PAL84: I0 Mask                  */
+#define LCD_PAL84_R14_0_Pos                                   16                                                        /*!< LCD PAL84: R14_0 Position           */
+#define LCD_PAL84_R14_0_Msk                                   (0x1fUL << LCD_PAL84_R14_0_Pos)                           /*!< LCD PAL84: R14_0 Mask               */
+#define LCD_PAL84_G14_0_Pos                                   21                                                        /*!< LCD PAL84: G14_0 Position           */
+#define LCD_PAL84_G14_0_Msk                                   (0x1fUL << LCD_PAL84_G14_0_Pos)                           /*!< LCD PAL84: G14_0 Mask               */
+#define LCD_PAL84_B14_0_Pos                                   26                                                        /*!< LCD PAL84: B14_0 Position           */
+#define LCD_PAL84_B14_0_Msk                                   (0x1fUL << LCD_PAL84_B14_0_Pos)                           /*!< LCD PAL84: B14_0 Mask               */
+#define LCD_PAL84_I1_Pos                                      31                                                        /*!< LCD PAL84: I1 Position              */
+#define LCD_PAL84_I1_Msk                                      (0x01UL << LCD_PAL84_I1_Pos)                              /*!< LCD PAL84: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL85  -------------------------------------------
+#define LCD_PAL85_R04_0_Pos                                   0                                                         /*!< LCD PAL85: R04_0 Position           */
+#define LCD_PAL85_R04_0_Msk                                   (0x1fUL << LCD_PAL85_R04_0_Pos)                           /*!< LCD PAL85: R04_0 Mask               */
+#define LCD_PAL85_G04_0_Pos                                   5                                                         /*!< LCD PAL85: G04_0 Position           */
+#define LCD_PAL85_G04_0_Msk                                   (0x1fUL << LCD_PAL85_G04_0_Pos)                           /*!< LCD PAL85: G04_0 Mask               */
+#define LCD_PAL85_B04_0_Pos                                   10                                                        /*!< LCD PAL85: B04_0 Position           */
+#define LCD_PAL85_B04_0_Msk                                   (0x1fUL << LCD_PAL85_B04_0_Pos)                           /*!< LCD PAL85: B04_0 Mask               */
+#define LCD_PAL85_I0_Pos                                      15                                                        /*!< LCD PAL85: I0 Position              */
+#define LCD_PAL85_I0_Msk                                      (0x01UL << LCD_PAL85_I0_Pos)                              /*!< LCD PAL85: I0 Mask                  */
+#define LCD_PAL85_R14_0_Pos                                   16                                                        /*!< LCD PAL85: R14_0 Position           */
+#define LCD_PAL85_R14_0_Msk                                   (0x1fUL << LCD_PAL85_R14_0_Pos)                           /*!< LCD PAL85: R14_0 Mask               */
+#define LCD_PAL85_G14_0_Pos                                   21                                                        /*!< LCD PAL85: G14_0 Position           */
+#define LCD_PAL85_G14_0_Msk                                   (0x1fUL << LCD_PAL85_G14_0_Pos)                           /*!< LCD PAL85: G14_0 Mask               */
+#define LCD_PAL85_B14_0_Pos                                   26                                                        /*!< LCD PAL85: B14_0 Position           */
+#define LCD_PAL85_B14_0_Msk                                   (0x1fUL << LCD_PAL85_B14_0_Pos)                           /*!< LCD PAL85: B14_0 Mask               */
+#define LCD_PAL85_I1_Pos                                      31                                                        /*!< LCD PAL85: I1 Position              */
+#define LCD_PAL85_I1_Msk                                      (0x01UL << LCD_PAL85_I1_Pos)                              /*!< LCD PAL85: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL86  -------------------------------------------
+#define LCD_PAL86_R04_0_Pos                                   0                                                         /*!< LCD PAL86: R04_0 Position           */
+#define LCD_PAL86_R04_0_Msk                                   (0x1fUL << LCD_PAL86_R04_0_Pos)                           /*!< LCD PAL86: R04_0 Mask               */
+#define LCD_PAL86_G04_0_Pos                                   5                                                         /*!< LCD PAL86: G04_0 Position           */
+#define LCD_PAL86_G04_0_Msk                                   (0x1fUL << LCD_PAL86_G04_0_Pos)                           /*!< LCD PAL86: G04_0 Mask               */
+#define LCD_PAL86_B04_0_Pos                                   10                                                        /*!< LCD PAL86: B04_0 Position           */
+#define LCD_PAL86_B04_0_Msk                                   (0x1fUL << LCD_PAL86_B04_0_Pos)                           /*!< LCD PAL86: B04_0 Mask               */
+#define LCD_PAL86_I0_Pos                                      15                                                        /*!< LCD PAL86: I0 Position              */
+#define LCD_PAL86_I0_Msk                                      (0x01UL << LCD_PAL86_I0_Pos)                              /*!< LCD PAL86: I0 Mask                  */
+#define LCD_PAL86_R14_0_Pos                                   16                                                        /*!< LCD PAL86: R14_0 Position           */
+#define LCD_PAL86_R14_0_Msk                                   (0x1fUL << LCD_PAL86_R14_0_Pos)                           /*!< LCD PAL86: R14_0 Mask               */
+#define LCD_PAL86_G14_0_Pos                                   21                                                        /*!< LCD PAL86: G14_0 Position           */
+#define LCD_PAL86_G14_0_Msk                                   (0x1fUL << LCD_PAL86_G14_0_Pos)                           /*!< LCD PAL86: G14_0 Mask               */
+#define LCD_PAL86_B14_0_Pos                                   26                                                        /*!< LCD PAL86: B14_0 Position           */
+#define LCD_PAL86_B14_0_Msk                                   (0x1fUL << LCD_PAL86_B14_0_Pos)                           /*!< LCD PAL86: B14_0 Mask               */
+#define LCD_PAL86_I1_Pos                                      31                                                        /*!< LCD PAL86: I1 Position              */
+#define LCD_PAL86_I1_Msk                                      (0x01UL << LCD_PAL86_I1_Pos)                              /*!< LCD PAL86: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL87  -------------------------------------------
+#define LCD_PAL87_R04_0_Pos                                   0                                                         /*!< LCD PAL87: R04_0 Position           */
+#define LCD_PAL87_R04_0_Msk                                   (0x1fUL << LCD_PAL87_R04_0_Pos)                           /*!< LCD PAL87: R04_0 Mask               */
+#define LCD_PAL87_G04_0_Pos                                   5                                                         /*!< LCD PAL87: G04_0 Position           */
+#define LCD_PAL87_G04_0_Msk                                   (0x1fUL << LCD_PAL87_G04_0_Pos)                           /*!< LCD PAL87: G04_0 Mask               */
+#define LCD_PAL87_B04_0_Pos                                   10                                                        /*!< LCD PAL87: B04_0 Position           */
+#define LCD_PAL87_B04_0_Msk                                   (0x1fUL << LCD_PAL87_B04_0_Pos)                           /*!< LCD PAL87: B04_0 Mask               */
+#define LCD_PAL87_I0_Pos                                      15                                                        /*!< LCD PAL87: I0 Position              */
+#define LCD_PAL87_I0_Msk                                      (0x01UL << LCD_PAL87_I0_Pos)                              /*!< LCD PAL87: I0 Mask                  */
+#define LCD_PAL87_R14_0_Pos                                   16                                                        /*!< LCD PAL87: R14_0 Position           */
+#define LCD_PAL87_R14_0_Msk                                   (0x1fUL << LCD_PAL87_R14_0_Pos)                           /*!< LCD PAL87: R14_0 Mask               */
+#define LCD_PAL87_G14_0_Pos                                   21                                                        /*!< LCD PAL87: G14_0 Position           */
+#define LCD_PAL87_G14_0_Msk                                   (0x1fUL << LCD_PAL87_G14_0_Pos)                           /*!< LCD PAL87: G14_0 Mask               */
+#define LCD_PAL87_B14_0_Pos                                   26                                                        /*!< LCD PAL87: B14_0 Position           */
+#define LCD_PAL87_B14_0_Msk                                   (0x1fUL << LCD_PAL87_B14_0_Pos)                           /*!< LCD PAL87: B14_0 Mask               */
+#define LCD_PAL87_I1_Pos                                      31                                                        /*!< LCD PAL87: I1 Position              */
+#define LCD_PAL87_I1_Msk                                      (0x01UL << LCD_PAL87_I1_Pos)                              /*!< LCD PAL87: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL88  -------------------------------------------
+#define LCD_PAL88_R04_0_Pos                                   0                                                         /*!< LCD PAL88: R04_0 Position           */
+#define LCD_PAL88_R04_0_Msk                                   (0x1fUL << LCD_PAL88_R04_0_Pos)                           /*!< LCD PAL88: R04_0 Mask               */
+#define LCD_PAL88_G04_0_Pos                                   5                                                         /*!< LCD PAL88: G04_0 Position           */
+#define LCD_PAL88_G04_0_Msk                                   (0x1fUL << LCD_PAL88_G04_0_Pos)                           /*!< LCD PAL88: G04_0 Mask               */
+#define LCD_PAL88_B04_0_Pos                                   10                                                        /*!< LCD PAL88: B04_0 Position           */
+#define LCD_PAL88_B04_0_Msk                                   (0x1fUL << LCD_PAL88_B04_0_Pos)                           /*!< LCD PAL88: B04_0 Mask               */
+#define LCD_PAL88_I0_Pos                                      15                                                        /*!< LCD PAL88: I0 Position              */
+#define LCD_PAL88_I0_Msk                                      (0x01UL << LCD_PAL88_I0_Pos)                              /*!< LCD PAL88: I0 Mask                  */
+#define LCD_PAL88_R14_0_Pos                                   16                                                        /*!< LCD PAL88: R14_0 Position           */
+#define LCD_PAL88_R14_0_Msk                                   (0x1fUL << LCD_PAL88_R14_0_Pos)                           /*!< LCD PAL88: R14_0 Mask               */
+#define LCD_PAL88_G14_0_Pos                                   21                                                        /*!< LCD PAL88: G14_0 Position           */
+#define LCD_PAL88_G14_0_Msk                                   (0x1fUL << LCD_PAL88_G14_0_Pos)                           /*!< LCD PAL88: G14_0 Mask               */
+#define LCD_PAL88_B14_0_Pos                                   26                                                        /*!< LCD PAL88: B14_0 Position           */
+#define LCD_PAL88_B14_0_Msk                                   (0x1fUL << LCD_PAL88_B14_0_Pos)                           /*!< LCD PAL88: B14_0 Mask               */
+#define LCD_PAL88_I1_Pos                                      31                                                        /*!< LCD PAL88: I1 Position              */
+#define LCD_PAL88_I1_Msk                                      (0x01UL << LCD_PAL88_I1_Pos)                              /*!< LCD PAL88: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL89  -------------------------------------------
+#define LCD_PAL89_R04_0_Pos                                   0                                                         /*!< LCD PAL89: R04_0 Position           */
+#define LCD_PAL89_R04_0_Msk                                   (0x1fUL << LCD_PAL89_R04_0_Pos)                           /*!< LCD PAL89: R04_0 Mask               */
+#define LCD_PAL89_G04_0_Pos                                   5                                                         /*!< LCD PAL89: G04_0 Position           */
+#define LCD_PAL89_G04_0_Msk                                   (0x1fUL << LCD_PAL89_G04_0_Pos)                           /*!< LCD PAL89: G04_0 Mask               */
+#define LCD_PAL89_B04_0_Pos                                   10                                                        /*!< LCD PAL89: B04_0 Position           */
+#define LCD_PAL89_B04_0_Msk                                   (0x1fUL << LCD_PAL89_B04_0_Pos)                           /*!< LCD PAL89: B04_0 Mask               */
+#define LCD_PAL89_I0_Pos                                      15                                                        /*!< LCD PAL89: I0 Position              */
+#define LCD_PAL89_I0_Msk                                      (0x01UL << LCD_PAL89_I0_Pos)                              /*!< LCD PAL89: I0 Mask                  */
+#define LCD_PAL89_R14_0_Pos                                   16                                                        /*!< LCD PAL89: R14_0 Position           */
+#define LCD_PAL89_R14_0_Msk                                   (0x1fUL << LCD_PAL89_R14_0_Pos)                           /*!< LCD PAL89: R14_0 Mask               */
+#define LCD_PAL89_G14_0_Pos                                   21                                                        /*!< LCD PAL89: G14_0 Position           */
+#define LCD_PAL89_G14_0_Msk                                   (0x1fUL << LCD_PAL89_G14_0_Pos)                           /*!< LCD PAL89: G14_0 Mask               */
+#define LCD_PAL89_B14_0_Pos                                   26                                                        /*!< LCD PAL89: B14_0 Position           */
+#define LCD_PAL89_B14_0_Msk                                   (0x1fUL << LCD_PAL89_B14_0_Pos)                           /*!< LCD PAL89: B14_0 Mask               */
+#define LCD_PAL89_I1_Pos                                      31                                                        /*!< LCD PAL89: I1 Position              */
+#define LCD_PAL89_I1_Msk                                      (0x01UL << LCD_PAL89_I1_Pos)                              /*!< LCD PAL89: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL90  -------------------------------------------
+#define LCD_PAL90_R04_0_Pos                                   0                                                         /*!< LCD PAL90: R04_0 Position           */
+#define LCD_PAL90_R04_0_Msk                                   (0x1fUL << LCD_PAL90_R04_0_Pos)                           /*!< LCD PAL90: R04_0 Mask               */
+#define LCD_PAL90_G04_0_Pos                                   5                                                         /*!< LCD PAL90: G04_0 Position           */
+#define LCD_PAL90_G04_0_Msk                                   (0x1fUL << LCD_PAL90_G04_0_Pos)                           /*!< LCD PAL90: G04_0 Mask               */
+#define LCD_PAL90_B04_0_Pos                                   10                                                        /*!< LCD PAL90: B04_0 Position           */
+#define LCD_PAL90_B04_0_Msk                                   (0x1fUL << LCD_PAL90_B04_0_Pos)                           /*!< LCD PAL90: B04_0 Mask               */
+#define LCD_PAL90_I0_Pos                                      15                                                        /*!< LCD PAL90: I0 Position              */
+#define LCD_PAL90_I0_Msk                                      (0x01UL << LCD_PAL90_I0_Pos)                              /*!< LCD PAL90: I0 Mask                  */
+#define LCD_PAL90_R14_0_Pos                                   16                                                        /*!< LCD PAL90: R14_0 Position           */
+#define LCD_PAL90_R14_0_Msk                                   (0x1fUL << LCD_PAL90_R14_0_Pos)                           /*!< LCD PAL90: R14_0 Mask               */
+#define LCD_PAL90_G14_0_Pos                                   21                                                        /*!< LCD PAL90: G14_0 Position           */
+#define LCD_PAL90_G14_0_Msk                                   (0x1fUL << LCD_PAL90_G14_0_Pos)                           /*!< LCD PAL90: G14_0 Mask               */
+#define LCD_PAL90_B14_0_Pos                                   26                                                        /*!< LCD PAL90: B14_0 Position           */
+#define LCD_PAL90_B14_0_Msk                                   (0x1fUL << LCD_PAL90_B14_0_Pos)                           /*!< LCD PAL90: B14_0 Mask               */
+#define LCD_PAL90_I1_Pos                                      31                                                        /*!< LCD PAL90: I1 Position              */
+#define LCD_PAL90_I1_Msk                                      (0x01UL << LCD_PAL90_I1_Pos)                              /*!< LCD PAL90: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL91  -------------------------------------------
+#define LCD_PAL91_R04_0_Pos                                   0                                                         /*!< LCD PAL91: R04_0 Position           */
+#define LCD_PAL91_R04_0_Msk                                   (0x1fUL << LCD_PAL91_R04_0_Pos)                           /*!< LCD PAL91: R04_0 Mask               */
+#define LCD_PAL91_G04_0_Pos                                   5                                                         /*!< LCD PAL91: G04_0 Position           */
+#define LCD_PAL91_G04_0_Msk                                   (0x1fUL << LCD_PAL91_G04_0_Pos)                           /*!< LCD PAL91: G04_0 Mask               */
+#define LCD_PAL91_B04_0_Pos                                   10                                                        /*!< LCD PAL91: B04_0 Position           */
+#define LCD_PAL91_B04_0_Msk                                   (0x1fUL << LCD_PAL91_B04_0_Pos)                           /*!< LCD PAL91: B04_0 Mask               */
+#define LCD_PAL91_I0_Pos                                      15                                                        /*!< LCD PAL91: I0 Position              */
+#define LCD_PAL91_I0_Msk                                      (0x01UL << LCD_PAL91_I0_Pos)                              /*!< LCD PAL91: I0 Mask                  */
+#define LCD_PAL91_R14_0_Pos                                   16                                                        /*!< LCD PAL91: R14_0 Position           */
+#define LCD_PAL91_R14_0_Msk                                   (0x1fUL << LCD_PAL91_R14_0_Pos)                           /*!< LCD PAL91: R14_0 Mask               */
+#define LCD_PAL91_G14_0_Pos                                   21                                                        /*!< LCD PAL91: G14_0 Position           */
+#define LCD_PAL91_G14_0_Msk                                   (0x1fUL << LCD_PAL91_G14_0_Pos)                           /*!< LCD PAL91: G14_0 Mask               */
+#define LCD_PAL91_B14_0_Pos                                   26                                                        /*!< LCD PAL91: B14_0 Position           */
+#define LCD_PAL91_B14_0_Msk                                   (0x1fUL << LCD_PAL91_B14_0_Pos)                           /*!< LCD PAL91: B14_0 Mask               */
+#define LCD_PAL91_I1_Pos                                      31                                                        /*!< LCD PAL91: I1 Position              */
+#define LCD_PAL91_I1_Msk                                      (0x01UL << LCD_PAL91_I1_Pos)                              /*!< LCD PAL91: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL92  -------------------------------------------
+#define LCD_PAL92_R04_0_Pos                                   0                                                         /*!< LCD PAL92: R04_0 Position           */
+#define LCD_PAL92_R04_0_Msk                                   (0x1fUL << LCD_PAL92_R04_0_Pos)                           /*!< LCD PAL92: R04_0 Mask               */
+#define LCD_PAL92_G04_0_Pos                                   5                                                         /*!< LCD PAL92: G04_0 Position           */
+#define LCD_PAL92_G04_0_Msk                                   (0x1fUL << LCD_PAL92_G04_0_Pos)                           /*!< LCD PAL92: G04_0 Mask               */
+#define LCD_PAL92_B04_0_Pos                                   10                                                        /*!< LCD PAL92: B04_0 Position           */
+#define LCD_PAL92_B04_0_Msk                                   (0x1fUL << LCD_PAL92_B04_0_Pos)                           /*!< LCD PAL92: B04_0 Mask               */
+#define LCD_PAL92_I0_Pos                                      15                                                        /*!< LCD PAL92: I0 Position              */
+#define LCD_PAL92_I0_Msk                                      (0x01UL << LCD_PAL92_I0_Pos)                              /*!< LCD PAL92: I0 Mask                  */
+#define LCD_PAL92_R14_0_Pos                                   16                                                        /*!< LCD PAL92: R14_0 Position           */
+#define LCD_PAL92_R14_0_Msk                                   (0x1fUL << LCD_PAL92_R14_0_Pos)                           /*!< LCD PAL92: R14_0 Mask               */
+#define LCD_PAL92_G14_0_Pos                                   21                                                        /*!< LCD PAL92: G14_0 Position           */
+#define LCD_PAL92_G14_0_Msk                                   (0x1fUL << LCD_PAL92_G14_0_Pos)                           /*!< LCD PAL92: G14_0 Mask               */
+#define LCD_PAL92_B14_0_Pos                                   26                                                        /*!< LCD PAL92: B14_0 Position           */
+#define LCD_PAL92_B14_0_Msk                                   (0x1fUL << LCD_PAL92_B14_0_Pos)                           /*!< LCD PAL92: B14_0 Mask               */
+#define LCD_PAL92_I1_Pos                                      31                                                        /*!< LCD PAL92: I1 Position              */
+#define LCD_PAL92_I1_Msk                                      (0x01UL << LCD_PAL92_I1_Pos)                              /*!< LCD PAL92: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL93  -------------------------------------------
+#define LCD_PAL93_R04_0_Pos                                   0                                                         /*!< LCD PAL93: R04_0 Position           */
+#define LCD_PAL93_R04_0_Msk                                   (0x1fUL << LCD_PAL93_R04_0_Pos)                           /*!< LCD PAL93: R04_0 Mask               */
+#define LCD_PAL93_G04_0_Pos                                   5                                                         /*!< LCD PAL93: G04_0 Position           */
+#define LCD_PAL93_G04_0_Msk                                   (0x1fUL << LCD_PAL93_G04_0_Pos)                           /*!< LCD PAL93: G04_0 Mask               */
+#define LCD_PAL93_B04_0_Pos                                   10                                                        /*!< LCD PAL93: B04_0 Position           */
+#define LCD_PAL93_B04_0_Msk                                   (0x1fUL << LCD_PAL93_B04_0_Pos)                           /*!< LCD PAL93: B04_0 Mask               */
+#define LCD_PAL93_I0_Pos                                      15                                                        /*!< LCD PAL93: I0 Position              */
+#define LCD_PAL93_I0_Msk                                      (0x01UL << LCD_PAL93_I0_Pos)                              /*!< LCD PAL93: I0 Mask                  */
+#define LCD_PAL93_R14_0_Pos                                   16                                                        /*!< LCD PAL93: R14_0 Position           */
+#define LCD_PAL93_R14_0_Msk                                   (0x1fUL << LCD_PAL93_R14_0_Pos)                           /*!< LCD PAL93: R14_0 Mask               */
+#define LCD_PAL93_G14_0_Pos                                   21                                                        /*!< LCD PAL93: G14_0 Position           */
+#define LCD_PAL93_G14_0_Msk                                   (0x1fUL << LCD_PAL93_G14_0_Pos)                           /*!< LCD PAL93: G14_0 Mask               */
+#define LCD_PAL93_B14_0_Pos                                   26                                                        /*!< LCD PAL93: B14_0 Position           */
+#define LCD_PAL93_B14_0_Msk                                   (0x1fUL << LCD_PAL93_B14_0_Pos)                           /*!< LCD PAL93: B14_0 Mask               */
+#define LCD_PAL93_I1_Pos                                      31                                                        /*!< LCD PAL93: I1 Position              */
+#define LCD_PAL93_I1_Msk                                      (0x01UL << LCD_PAL93_I1_Pos)                              /*!< LCD PAL93: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL94  -------------------------------------------
+#define LCD_PAL94_R04_0_Pos                                   0                                                         /*!< LCD PAL94: R04_0 Position           */
+#define LCD_PAL94_R04_0_Msk                                   (0x1fUL << LCD_PAL94_R04_0_Pos)                           /*!< LCD PAL94: R04_0 Mask               */
+#define LCD_PAL94_G04_0_Pos                                   5                                                         /*!< LCD PAL94: G04_0 Position           */
+#define LCD_PAL94_G04_0_Msk                                   (0x1fUL << LCD_PAL94_G04_0_Pos)                           /*!< LCD PAL94: G04_0 Mask               */
+#define LCD_PAL94_B04_0_Pos                                   10                                                        /*!< LCD PAL94: B04_0 Position           */
+#define LCD_PAL94_B04_0_Msk                                   (0x1fUL << LCD_PAL94_B04_0_Pos)                           /*!< LCD PAL94: B04_0 Mask               */
+#define LCD_PAL94_I0_Pos                                      15                                                        /*!< LCD PAL94: I0 Position              */
+#define LCD_PAL94_I0_Msk                                      (0x01UL << LCD_PAL94_I0_Pos)                              /*!< LCD PAL94: I0 Mask                  */
+#define LCD_PAL94_R14_0_Pos                                   16                                                        /*!< LCD PAL94: R14_0 Position           */
+#define LCD_PAL94_R14_0_Msk                                   (0x1fUL << LCD_PAL94_R14_0_Pos)                           /*!< LCD PAL94: R14_0 Mask               */
+#define LCD_PAL94_G14_0_Pos                                   21                                                        /*!< LCD PAL94: G14_0 Position           */
+#define LCD_PAL94_G14_0_Msk                                   (0x1fUL << LCD_PAL94_G14_0_Pos)                           /*!< LCD PAL94: G14_0 Mask               */
+#define LCD_PAL94_B14_0_Pos                                   26                                                        /*!< LCD PAL94: B14_0 Position           */
+#define LCD_PAL94_B14_0_Msk                                   (0x1fUL << LCD_PAL94_B14_0_Pos)                           /*!< LCD PAL94: B14_0 Mask               */
+#define LCD_PAL94_I1_Pos                                      31                                                        /*!< LCD PAL94: I1 Position              */
+#define LCD_PAL94_I1_Msk                                      (0x01UL << LCD_PAL94_I1_Pos)                              /*!< LCD PAL94: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL95  -------------------------------------------
+#define LCD_PAL95_R04_0_Pos                                   0                                                         /*!< LCD PAL95: R04_0 Position           */
+#define LCD_PAL95_R04_0_Msk                                   (0x1fUL << LCD_PAL95_R04_0_Pos)                           /*!< LCD PAL95: R04_0 Mask               */
+#define LCD_PAL95_G04_0_Pos                                   5                                                         /*!< LCD PAL95: G04_0 Position           */
+#define LCD_PAL95_G04_0_Msk                                   (0x1fUL << LCD_PAL95_G04_0_Pos)                           /*!< LCD PAL95: G04_0 Mask               */
+#define LCD_PAL95_B04_0_Pos                                   10                                                        /*!< LCD PAL95: B04_0 Position           */
+#define LCD_PAL95_B04_0_Msk                                   (0x1fUL << LCD_PAL95_B04_0_Pos)                           /*!< LCD PAL95: B04_0 Mask               */
+#define LCD_PAL95_I0_Pos                                      15                                                        /*!< LCD PAL95: I0 Position              */
+#define LCD_PAL95_I0_Msk                                      (0x01UL << LCD_PAL95_I0_Pos)                              /*!< LCD PAL95: I0 Mask                  */
+#define LCD_PAL95_R14_0_Pos                                   16                                                        /*!< LCD PAL95: R14_0 Position           */
+#define LCD_PAL95_R14_0_Msk                                   (0x1fUL << LCD_PAL95_R14_0_Pos)                           /*!< LCD PAL95: R14_0 Mask               */
+#define LCD_PAL95_G14_0_Pos                                   21                                                        /*!< LCD PAL95: G14_0 Position           */
+#define LCD_PAL95_G14_0_Msk                                   (0x1fUL << LCD_PAL95_G14_0_Pos)                           /*!< LCD PAL95: G14_0 Mask               */
+#define LCD_PAL95_B14_0_Pos                                   26                                                        /*!< LCD PAL95: B14_0 Position           */
+#define LCD_PAL95_B14_0_Msk                                   (0x1fUL << LCD_PAL95_B14_0_Pos)                           /*!< LCD PAL95: B14_0 Mask               */
+#define LCD_PAL95_I1_Pos                                      31                                                        /*!< LCD PAL95: I1 Position              */
+#define LCD_PAL95_I1_Msk                                      (0x01UL << LCD_PAL95_I1_Pos)                              /*!< LCD PAL95: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL96  -------------------------------------------
+#define LCD_PAL96_R04_0_Pos                                   0                                                         /*!< LCD PAL96: R04_0 Position           */
+#define LCD_PAL96_R04_0_Msk                                   (0x1fUL << LCD_PAL96_R04_0_Pos)                           /*!< LCD PAL96: R04_0 Mask               */
+#define LCD_PAL96_G04_0_Pos                                   5                                                         /*!< LCD PAL96: G04_0 Position           */
+#define LCD_PAL96_G04_0_Msk                                   (0x1fUL << LCD_PAL96_G04_0_Pos)                           /*!< LCD PAL96: G04_0 Mask               */
+#define LCD_PAL96_B04_0_Pos                                   10                                                        /*!< LCD PAL96: B04_0 Position           */
+#define LCD_PAL96_B04_0_Msk                                   (0x1fUL << LCD_PAL96_B04_0_Pos)                           /*!< LCD PAL96: B04_0 Mask               */
+#define LCD_PAL96_I0_Pos                                      15                                                        /*!< LCD PAL96: I0 Position              */
+#define LCD_PAL96_I0_Msk                                      (0x01UL << LCD_PAL96_I0_Pos)                              /*!< LCD PAL96: I0 Mask                  */
+#define LCD_PAL96_R14_0_Pos                                   16                                                        /*!< LCD PAL96: R14_0 Position           */
+#define LCD_PAL96_R14_0_Msk                                   (0x1fUL << LCD_PAL96_R14_0_Pos)                           /*!< LCD PAL96: R14_0 Mask               */
+#define LCD_PAL96_G14_0_Pos                                   21                                                        /*!< LCD PAL96: G14_0 Position           */
+#define LCD_PAL96_G14_0_Msk                                   (0x1fUL << LCD_PAL96_G14_0_Pos)                           /*!< LCD PAL96: G14_0 Mask               */
+#define LCD_PAL96_B14_0_Pos                                   26                                                        /*!< LCD PAL96: B14_0 Position           */
+#define LCD_PAL96_B14_0_Msk                                   (0x1fUL << LCD_PAL96_B14_0_Pos)                           /*!< LCD PAL96: B14_0 Mask               */
+#define LCD_PAL96_I1_Pos                                      31                                                        /*!< LCD PAL96: I1 Position              */
+#define LCD_PAL96_I1_Msk                                      (0x01UL << LCD_PAL96_I1_Pos)                              /*!< LCD PAL96: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL97  -------------------------------------------
+#define LCD_PAL97_R04_0_Pos                                   0                                                         /*!< LCD PAL97: R04_0 Position           */
+#define LCD_PAL97_R04_0_Msk                                   (0x1fUL << LCD_PAL97_R04_0_Pos)                           /*!< LCD PAL97: R04_0 Mask               */
+#define LCD_PAL97_G04_0_Pos                                   5                                                         /*!< LCD PAL97: G04_0 Position           */
+#define LCD_PAL97_G04_0_Msk                                   (0x1fUL << LCD_PAL97_G04_0_Pos)                           /*!< LCD PAL97: G04_0 Mask               */
+#define LCD_PAL97_B04_0_Pos                                   10                                                        /*!< LCD PAL97: B04_0 Position           */
+#define LCD_PAL97_B04_0_Msk                                   (0x1fUL << LCD_PAL97_B04_0_Pos)                           /*!< LCD PAL97: B04_0 Mask               */
+#define LCD_PAL97_I0_Pos                                      15                                                        /*!< LCD PAL97: I0 Position              */
+#define LCD_PAL97_I0_Msk                                      (0x01UL << LCD_PAL97_I0_Pos)                              /*!< LCD PAL97: I0 Mask                  */
+#define LCD_PAL97_R14_0_Pos                                   16                                                        /*!< LCD PAL97: R14_0 Position           */
+#define LCD_PAL97_R14_0_Msk                                   (0x1fUL << LCD_PAL97_R14_0_Pos)                           /*!< LCD PAL97: R14_0 Mask               */
+#define LCD_PAL97_G14_0_Pos                                   21                                                        /*!< LCD PAL97: G14_0 Position           */
+#define LCD_PAL97_G14_0_Msk                                   (0x1fUL << LCD_PAL97_G14_0_Pos)                           /*!< LCD PAL97: G14_0 Mask               */
+#define LCD_PAL97_B14_0_Pos                                   26                                                        /*!< LCD PAL97: B14_0 Position           */
+#define LCD_PAL97_B14_0_Msk                                   (0x1fUL << LCD_PAL97_B14_0_Pos)                           /*!< LCD PAL97: B14_0 Mask               */
+#define LCD_PAL97_I1_Pos                                      31                                                        /*!< LCD PAL97: I1 Position              */
+#define LCD_PAL97_I1_Msk                                      (0x01UL << LCD_PAL97_I1_Pos)                              /*!< LCD PAL97: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL98  -------------------------------------------
+#define LCD_PAL98_R04_0_Pos                                   0                                                         /*!< LCD PAL98: R04_0 Position           */
+#define LCD_PAL98_R04_0_Msk                                   (0x1fUL << LCD_PAL98_R04_0_Pos)                           /*!< LCD PAL98: R04_0 Mask               */
+#define LCD_PAL98_G04_0_Pos                                   5                                                         /*!< LCD PAL98: G04_0 Position           */
+#define LCD_PAL98_G04_0_Msk                                   (0x1fUL << LCD_PAL98_G04_0_Pos)                           /*!< LCD PAL98: G04_0 Mask               */
+#define LCD_PAL98_B04_0_Pos                                   10                                                        /*!< LCD PAL98: B04_0 Position           */
+#define LCD_PAL98_B04_0_Msk                                   (0x1fUL << LCD_PAL98_B04_0_Pos)                           /*!< LCD PAL98: B04_0 Mask               */
+#define LCD_PAL98_I0_Pos                                      15                                                        /*!< LCD PAL98: I0 Position              */
+#define LCD_PAL98_I0_Msk                                      (0x01UL << LCD_PAL98_I0_Pos)                              /*!< LCD PAL98: I0 Mask                  */
+#define LCD_PAL98_R14_0_Pos                                   16                                                        /*!< LCD PAL98: R14_0 Position           */
+#define LCD_PAL98_R14_0_Msk                                   (0x1fUL << LCD_PAL98_R14_0_Pos)                           /*!< LCD PAL98: R14_0 Mask               */
+#define LCD_PAL98_G14_0_Pos                                   21                                                        /*!< LCD PAL98: G14_0 Position           */
+#define LCD_PAL98_G14_0_Msk                                   (0x1fUL << LCD_PAL98_G14_0_Pos)                           /*!< LCD PAL98: G14_0 Mask               */
+#define LCD_PAL98_B14_0_Pos                                   26                                                        /*!< LCD PAL98: B14_0 Position           */
+#define LCD_PAL98_B14_0_Msk                                   (0x1fUL << LCD_PAL98_B14_0_Pos)                           /*!< LCD PAL98: B14_0 Mask               */
+#define LCD_PAL98_I1_Pos                                      31                                                        /*!< LCD PAL98: I1 Position              */
+#define LCD_PAL98_I1_Msk                                      (0x01UL << LCD_PAL98_I1_Pos)                              /*!< LCD PAL98: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL99  -------------------------------------------
+#define LCD_PAL99_R04_0_Pos                                   0                                                         /*!< LCD PAL99: R04_0 Position           */
+#define LCD_PAL99_R04_0_Msk                                   (0x1fUL << LCD_PAL99_R04_0_Pos)                           /*!< LCD PAL99: R04_0 Mask               */
+#define LCD_PAL99_G04_0_Pos                                   5                                                         /*!< LCD PAL99: G04_0 Position           */
+#define LCD_PAL99_G04_0_Msk                                   (0x1fUL << LCD_PAL99_G04_0_Pos)                           /*!< LCD PAL99: G04_0 Mask               */
+#define LCD_PAL99_B04_0_Pos                                   10                                                        /*!< LCD PAL99: B04_0 Position           */
+#define LCD_PAL99_B04_0_Msk                                   (0x1fUL << LCD_PAL99_B04_0_Pos)                           /*!< LCD PAL99: B04_0 Mask               */
+#define LCD_PAL99_I0_Pos                                      15                                                        /*!< LCD PAL99: I0 Position              */
+#define LCD_PAL99_I0_Msk                                      (0x01UL << LCD_PAL99_I0_Pos)                              /*!< LCD PAL99: I0 Mask                  */
+#define LCD_PAL99_R14_0_Pos                                   16                                                        /*!< LCD PAL99: R14_0 Position           */
+#define LCD_PAL99_R14_0_Msk                                   (0x1fUL << LCD_PAL99_R14_0_Pos)                           /*!< LCD PAL99: R14_0 Mask               */
+#define LCD_PAL99_G14_0_Pos                                   21                                                        /*!< LCD PAL99: G14_0 Position           */
+#define LCD_PAL99_G14_0_Msk                                   (0x1fUL << LCD_PAL99_G14_0_Pos)                           /*!< LCD PAL99: G14_0 Mask               */
+#define LCD_PAL99_B14_0_Pos                                   26                                                        /*!< LCD PAL99: B14_0 Position           */
+#define LCD_PAL99_B14_0_Msk                                   (0x1fUL << LCD_PAL99_B14_0_Pos)                           /*!< LCD PAL99: B14_0 Mask               */
+#define LCD_PAL99_I1_Pos                                      31                                                        /*!< LCD PAL99: I1 Position              */
+#define LCD_PAL99_I1_Msk                                      (0x01UL << LCD_PAL99_I1_Pos)                              /*!< LCD PAL99: I1 Mask                  */
+
+// ---------------------------------------  LCD_PAL100  -------------------------------------------
+#define LCD_PAL100_R04_0_Pos                                  0                                                         /*!< LCD PAL100: R04_0 Position          */
+#define LCD_PAL100_R04_0_Msk                                  (0x1fUL << LCD_PAL100_R04_0_Pos)                          /*!< LCD PAL100: R04_0 Mask              */
+#define LCD_PAL100_G04_0_Pos                                  5                                                         /*!< LCD PAL100: G04_0 Position          */
+#define LCD_PAL100_G04_0_Msk                                  (0x1fUL << LCD_PAL100_G04_0_Pos)                          /*!< LCD PAL100: G04_0 Mask              */
+#define LCD_PAL100_B04_0_Pos                                  10                                                        /*!< LCD PAL100: B04_0 Position          */
+#define LCD_PAL100_B04_0_Msk                                  (0x1fUL << LCD_PAL100_B04_0_Pos)                          /*!< LCD PAL100: B04_0 Mask              */
+#define LCD_PAL100_I0_Pos                                     15                                                        /*!< LCD PAL100: I0 Position             */
+#define LCD_PAL100_I0_Msk                                     (0x01UL << LCD_PAL100_I0_Pos)                             /*!< LCD PAL100: I0 Mask                 */
+#define LCD_PAL100_R14_0_Pos                                  16                                                        /*!< LCD PAL100: R14_0 Position          */
+#define LCD_PAL100_R14_0_Msk                                  (0x1fUL << LCD_PAL100_R14_0_Pos)                          /*!< LCD PAL100: R14_0 Mask              */
+#define LCD_PAL100_G14_0_Pos                                  21                                                        /*!< LCD PAL100: G14_0 Position          */
+#define LCD_PAL100_G14_0_Msk                                  (0x1fUL << LCD_PAL100_G14_0_Pos)                          /*!< LCD PAL100: G14_0 Mask              */
+#define LCD_PAL100_B14_0_Pos                                  26                                                        /*!< LCD PAL100: B14_0 Position          */
+#define LCD_PAL100_B14_0_Msk                                  (0x1fUL << LCD_PAL100_B14_0_Pos)                          /*!< LCD PAL100: B14_0 Mask              */
+#define LCD_PAL100_I1_Pos                                     31                                                        /*!< LCD PAL100: I1 Position             */
+#define LCD_PAL100_I1_Msk                                     (0x01UL << LCD_PAL100_I1_Pos)                             /*!< LCD PAL100: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL101  -------------------------------------------
+#define LCD_PAL101_R04_0_Pos                                  0                                                         /*!< LCD PAL101: R04_0 Position          */
+#define LCD_PAL101_R04_0_Msk                                  (0x1fUL << LCD_PAL101_R04_0_Pos)                          /*!< LCD PAL101: R04_0 Mask              */
+#define LCD_PAL101_G04_0_Pos                                  5                                                         /*!< LCD PAL101: G04_0 Position          */
+#define LCD_PAL101_G04_0_Msk                                  (0x1fUL << LCD_PAL101_G04_0_Pos)                          /*!< LCD PAL101: G04_0 Mask              */
+#define LCD_PAL101_B04_0_Pos                                  10                                                        /*!< LCD PAL101: B04_0 Position          */
+#define LCD_PAL101_B04_0_Msk                                  (0x1fUL << LCD_PAL101_B04_0_Pos)                          /*!< LCD PAL101: B04_0 Mask              */
+#define LCD_PAL101_I0_Pos                                     15                                                        /*!< LCD PAL101: I0 Position             */
+#define LCD_PAL101_I0_Msk                                     (0x01UL << LCD_PAL101_I0_Pos)                             /*!< LCD PAL101: I0 Mask                 */
+#define LCD_PAL101_R14_0_Pos                                  16                                                        /*!< LCD PAL101: R14_0 Position          */
+#define LCD_PAL101_R14_0_Msk                                  (0x1fUL << LCD_PAL101_R14_0_Pos)                          /*!< LCD PAL101: R14_0 Mask              */
+#define LCD_PAL101_G14_0_Pos                                  21                                                        /*!< LCD PAL101: G14_0 Position          */
+#define LCD_PAL101_G14_0_Msk                                  (0x1fUL << LCD_PAL101_G14_0_Pos)                          /*!< LCD PAL101: G14_0 Mask              */
+#define LCD_PAL101_B14_0_Pos                                  26                                                        /*!< LCD PAL101: B14_0 Position          */
+#define LCD_PAL101_B14_0_Msk                                  (0x1fUL << LCD_PAL101_B14_0_Pos)                          /*!< LCD PAL101: B14_0 Mask              */
+#define LCD_PAL101_I1_Pos                                     31                                                        /*!< LCD PAL101: I1 Position             */
+#define LCD_PAL101_I1_Msk                                     (0x01UL << LCD_PAL101_I1_Pos)                             /*!< LCD PAL101: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL102  -------------------------------------------
+#define LCD_PAL102_R04_0_Pos                                  0                                                         /*!< LCD PAL102: R04_0 Position          */
+#define LCD_PAL102_R04_0_Msk                                  (0x1fUL << LCD_PAL102_R04_0_Pos)                          /*!< LCD PAL102: R04_0 Mask              */
+#define LCD_PAL102_G04_0_Pos                                  5                                                         /*!< LCD PAL102: G04_0 Position          */
+#define LCD_PAL102_G04_0_Msk                                  (0x1fUL << LCD_PAL102_G04_0_Pos)                          /*!< LCD PAL102: G04_0 Mask              */
+#define LCD_PAL102_B04_0_Pos                                  10                                                        /*!< LCD PAL102: B04_0 Position          */
+#define LCD_PAL102_B04_0_Msk                                  (0x1fUL << LCD_PAL102_B04_0_Pos)                          /*!< LCD PAL102: B04_0 Mask              */
+#define LCD_PAL102_I0_Pos                                     15                                                        /*!< LCD PAL102: I0 Position             */
+#define LCD_PAL102_I0_Msk                                     (0x01UL << LCD_PAL102_I0_Pos)                             /*!< LCD PAL102: I0 Mask                 */
+#define LCD_PAL102_R14_0_Pos                                  16                                                        /*!< LCD PAL102: R14_0 Position          */
+#define LCD_PAL102_R14_0_Msk                                  (0x1fUL << LCD_PAL102_R14_0_Pos)                          /*!< LCD PAL102: R14_0 Mask              */
+#define LCD_PAL102_G14_0_Pos                                  21                                                        /*!< LCD PAL102: G14_0 Position          */
+#define LCD_PAL102_G14_0_Msk                                  (0x1fUL << LCD_PAL102_G14_0_Pos)                          /*!< LCD PAL102: G14_0 Mask              */
+#define LCD_PAL102_B14_0_Pos                                  26                                                        /*!< LCD PAL102: B14_0 Position          */
+#define LCD_PAL102_B14_0_Msk                                  (0x1fUL << LCD_PAL102_B14_0_Pos)                          /*!< LCD PAL102: B14_0 Mask              */
+#define LCD_PAL102_I1_Pos                                     31                                                        /*!< LCD PAL102: I1 Position             */
+#define LCD_PAL102_I1_Msk                                     (0x01UL << LCD_PAL102_I1_Pos)                             /*!< LCD PAL102: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL103  -------------------------------------------
+#define LCD_PAL103_R04_0_Pos                                  0                                                         /*!< LCD PAL103: R04_0 Position          */
+#define LCD_PAL103_R04_0_Msk                                  (0x1fUL << LCD_PAL103_R04_0_Pos)                          /*!< LCD PAL103: R04_0 Mask              */
+#define LCD_PAL103_G04_0_Pos                                  5                                                         /*!< LCD PAL103: G04_0 Position          */
+#define LCD_PAL103_G04_0_Msk                                  (0x1fUL << LCD_PAL103_G04_0_Pos)                          /*!< LCD PAL103: G04_0 Mask              */
+#define LCD_PAL103_B04_0_Pos                                  10                                                        /*!< LCD PAL103: B04_0 Position          */
+#define LCD_PAL103_B04_0_Msk                                  (0x1fUL << LCD_PAL103_B04_0_Pos)                          /*!< LCD PAL103: B04_0 Mask              */
+#define LCD_PAL103_I0_Pos                                     15                                                        /*!< LCD PAL103: I0 Position             */
+#define LCD_PAL103_I0_Msk                                     (0x01UL << LCD_PAL103_I0_Pos)                             /*!< LCD PAL103: I0 Mask                 */
+#define LCD_PAL103_R14_0_Pos                                  16                                                        /*!< LCD PAL103: R14_0 Position          */
+#define LCD_PAL103_R14_0_Msk                                  (0x1fUL << LCD_PAL103_R14_0_Pos)                          /*!< LCD PAL103: R14_0 Mask              */
+#define LCD_PAL103_G14_0_Pos                                  21                                                        /*!< LCD PAL103: G14_0 Position          */
+#define LCD_PAL103_G14_0_Msk                                  (0x1fUL << LCD_PAL103_G14_0_Pos)                          /*!< LCD PAL103: G14_0 Mask              */
+#define LCD_PAL103_B14_0_Pos                                  26                                                        /*!< LCD PAL103: B14_0 Position          */
+#define LCD_PAL103_B14_0_Msk                                  (0x1fUL << LCD_PAL103_B14_0_Pos)                          /*!< LCD PAL103: B14_0 Mask              */
+#define LCD_PAL103_I1_Pos                                     31                                                        /*!< LCD PAL103: I1 Position             */
+#define LCD_PAL103_I1_Msk                                     (0x01UL << LCD_PAL103_I1_Pos)                             /*!< LCD PAL103: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL104  -------------------------------------------
+#define LCD_PAL104_R04_0_Pos                                  0                                                         /*!< LCD PAL104: R04_0 Position          */
+#define LCD_PAL104_R04_0_Msk                                  (0x1fUL << LCD_PAL104_R04_0_Pos)                          /*!< LCD PAL104: R04_0 Mask              */
+#define LCD_PAL104_G04_0_Pos                                  5                                                         /*!< LCD PAL104: G04_0 Position          */
+#define LCD_PAL104_G04_0_Msk                                  (0x1fUL << LCD_PAL104_G04_0_Pos)                          /*!< LCD PAL104: G04_0 Mask              */
+#define LCD_PAL104_B04_0_Pos                                  10                                                        /*!< LCD PAL104: B04_0 Position          */
+#define LCD_PAL104_B04_0_Msk                                  (0x1fUL << LCD_PAL104_B04_0_Pos)                          /*!< LCD PAL104: B04_0 Mask              */
+#define LCD_PAL104_I0_Pos                                     15                                                        /*!< LCD PAL104: I0 Position             */
+#define LCD_PAL104_I0_Msk                                     (0x01UL << LCD_PAL104_I0_Pos)                             /*!< LCD PAL104: I0 Mask                 */
+#define LCD_PAL104_R14_0_Pos                                  16                                                        /*!< LCD PAL104: R14_0 Position          */
+#define LCD_PAL104_R14_0_Msk                                  (0x1fUL << LCD_PAL104_R14_0_Pos)                          /*!< LCD PAL104: R14_0 Mask              */
+#define LCD_PAL104_G14_0_Pos                                  21                                                        /*!< LCD PAL104: G14_0 Position          */
+#define LCD_PAL104_G14_0_Msk                                  (0x1fUL << LCD_PAL104_G14_0_Pos)                          /*!< LCD PAL104: G14_0 Mask              */
+#define LCD_PAL104_B14_0_Pos                                  26                                                        /*!< LCD PAL104: B14_0 Position          */
+#define LCD_PAL104_B14_0_Msk                                  (0x1fUL << LCD_PAL104_B14_0_Pos)                          /*!< LCD PAL104: B14_0 Mask              */
+#define LCD_PAL104_I1_Pos                                     31                                                        /*!< LCD PAL104: I1 Position             */
+#define LCD_PAL104_I1_Msk                                     (0x01UL << LCD_PAL104_I1_Pos)                             /*!< LCD PAL104: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL105  -------------------------------------------
+#define LCD_PAL105_R04_0_Pos                                  0                                                         /*!< LCD PAL105: R04_0 Position          */
+#define LCD_PAL105_R04_0_Msk                                  (0x1fUL << LCD_PAL105_R04_0_Pos)                          /*!< LCD PAL105: R04_0 Mask              */
+#define LCD_PAL105_G04_0_Pos                                  5                                                         /*!< LCD PAL105: G04_0 Position          */
+#define LCD_PAL105_G04_0_Msk                                  (0x1fUL << LCD_PAL105_G04_0_Pos)                          /*!< LCD PAL105: G04_0 Mask              */
+#define LCD_PAL105_B04_0_Pos                                  10                                                        /*!< LCD PAL105: B04_0 Position          */
+#define LCD_PAL105_B04_0_Msk                                  (0x1fUL << LCD_PAL105_B04_0_Pos)                          /*!< LCD PAL105: B04_0 Mask              */
+#define LCD_PAL105_I0_Pos                                     15                                                        /*!< LCD PAL105: I0 Position             */
+#define LCD_PAL105_I0_Msk                                     (0x01UL << LCD_PAL105_I0_Pos)                             /*!< LCD PAL105: I0 Mask                 */
+#define LCD_PAL105_R14_0_Pos                                  16                                                        /*!< LCD PAL105: R14_0 Position          */
+#define LCD_PAL105_R14_0_Msk                                  (0x1fUL << LCD_PAL105_R14_0_Pos)                          /*!< LCD PAL105: R14_0 Mask              */
+#define LCD_PAL105_G14_0_Pos                                  21                                                        /*!< LCD PAL105: G14_0 Position          */
+#define LCD_PAL105_G14_0_Msk                                  (0x1fUL << LCD_PAL105_G14_0_Pos)                          /*!< LCD PAL105: G14_0 Mask              */
+#define LCD_PAL105_B14_0_Pos                                  26                                                        /*!< LCD PAL105: B14_0 Position          */
+#define LCD_PAL105_B14_0_Msk                                  (0x1fUL << LCD_PAL105_B14_0_Pos)                          /*!< LCD PAL105: B14_0 Mask              */
+#define LCD_PAL105_I1_Pos                                     31                                                        /*!< LCD PAL105: I1 Position             */
+#define LCD_PAL105_I1_Msk                                     (0x01UL << LCD_PAL105_I1_Pos)                             /*!< LCD PAL105: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL106  -------------------------------------------
+#define LCD_PAL106_R04_0_Pos                                  0                                                         /*!< LCD PAL106: R04_0 Position          */
+#define LCD_PAL106_R04_0_Msk                                  (0x1fUL << LCD_PAL106_R04_0_Pos)                          /*!< LCD PAL106: R04_0 Mask              */
+#define LCD_PAL106_G04_0_Pos                                  5                                                         /*!< LCD PAL106: G04_0 Position          */
+#define LCD_PAL106_G04_0_Msk                                  (0x1fUL << LCD_PAL106_G04_0_Pos)                          /*!< LCD PAL106: G04_0 Mask              */
+#define LCD_PAL106_B04_0_Pos                                  10                                                        /*!< LCD PAL106: B04_0 Position          */
+#define LCD_PAL106_B04_0_Msk                                  (0x1fUL << LCD_PAL106_B04_0_Pos)                          /*!< LCD PAL106: B04_0 Mask              */
+#define LCD_PAL106_I0_Pos                                     15                                                        /*!< LCD PAL106: I0 Position             */
+#define LCD_PAL106_I0_Msk                                     (0x01UL << LCD_PAL106_I0_Pos)                             /*!< LCD PAL106: I0 Mask                 */
+#define LCD_PAL106_R14_0_Pos                                  16                                                        /*!< LCD PAL106: R14_0 Position          */
+#define LCD_PAL106_R14_0_Msk                                  (0x1fUL << LCD_PAL106_R14_0_Pos)                          /*!< LCD PAL106: R14_0 Mask              */
+#define LCD_PAL106_G14_0_Pos                                  21                                                        /*!< LCD PAL106: G14_0 Position          */
+#define LCD_PAL106_G14_0_Msk                                  (0x1fUL << LCD_PAL106_G14_0_Pos)                          /*!< LCD PAL106: G14_0 Mask              */
+#define LCD_PAL106_B14_0_Pos                                  26                                                        /*!< LCD PAL106: B14_0 Position          */
+#define LCD_PAL106_B14_0_Msk                                  (0x1fUL << LCD_PAL106_B14_0_Pos)                          /*!< LCD PAL106: B14_0 Mask              */
+#define LCD_PAL106_I1_Pos                                     31                                                        /*!< LCD PAL106: I1 Position             */
+#define LCD_PAL106_I1_Msk                                     (0x01UL << LCD_PAL106_I1_Pos)                             /*!< LCD PAL106: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL107  -------------------------------------------
+#define LCD_PAL107_R04_0_Pos                                  0                                                         /*!< LCD PAL107: R04_0 Position          */
+#define LCD_PAL107_R04_0_Msk                                  (0x1fUL << LCD_PAL107_R04_0_Pos)                          /*!< LCD PAL107: R04_0 Mask              */
+#define LCD_PAL107_G04_0_Pos                                  5                                                         /*!< LCD PAL107: G04_0 Position          */
+#define LCD_PAL107_G04_0_Msk                                  (0x1fUL << LCD_PAL107_G04_0_Pos)                          /*!< LCD PAL107: G04_0 Mask              */
+#define LCD_PAL107_B04_0_Pos                                  10                                                        /*!< LCD PAL107: B04_0 Position          */
+#define LCD_PAL107_B04_0_Msk                                  (0x1fUL << LCD_PAL107_B04_0_Pos)                          /*!< LCD PAL107: B04_0 Mask              */
+#define LCD_PAL107_I0_Pos                                     15                                                        /*!< LCD PAL107: I0 Position             */
+#define LCD_PAL107_I0_Msk                                     (0x01UL << LCD_PAL107_I0_Pos)                             /*!< LCD PAL107: I0 Mask                 */
+#define LCD_PAL107_R14_0_Pos                                  16                                                        /*!< LCD PAL107: R14_0 Position          */
+#define LCD_PAL107_R14_0_Msk                                  (0x1fUL << LCD_PAL107_R14_0_Pos)                          /*!< LCD PAL107: R14_0 Mask              */
+#define LCD_PAL107_G14_0_Pos                                  21                                                        /*!< LCD PAL107: G14_0 Position          */
+#define LCD_PAL107_G14_0_Msk                                  (0x1fUL << LCD_PAL107_G14_0_Pos)                          /*!< LCD PAL107: G14_0 Mask              */
+#define LCD_PAL107_B14_0_Pos                                  26                                                        /*!< LCD PAL107: B14_0 Position          */
+#define LCD_PAL107_B14_0_Msk                                  (0x1fUL << LCD_PAL107_B14_0_Pos)                          /*!< LCD PAL107: B14_0 Mask              */
+#define LCD_PAL107_I1_Pos                                     31                                                        /*!< LCD PAL107: I1 Position             */
+#define LCD_PAL107_I1_Msk                                     (0x01UL << LCD_PAL107_I1_Pos)                             /*!< LCD PAL107: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL108  -------------------------------------------
+#define LCD_PAL108_R04_0_Pos                                  0                                                         /*!< LCD PAL108: R04_0 Position          */
+#define LCD_PAL108_R04_0_Msk                                  (0x1fUL << LCD_PAL108_R04_0_Pos)                          /*!< LCD PAL108: R04_0 Mask              */
+#define LCD_PAL108_G04_0_Pos                                  5                                                         /*!< LCD PAL108: G04_0 Position          */
+#define LCD_PAL108_G04_0_Msk                                  (0x1fUL << LCD_PAL108_G04_0_Pos)                          /*!< LCD PAL108: G04_0 Mask              */
+#define LCD_PAL108_B04_0_Pos                                  10                                                        /*!< LCD PAL108: B04_0 Position          */
+#define LCD_PAL108_B04_0_Msk                                  (0x1fUL << LCD_PAL108_B04_0_Pos)                          /*!< LCD PAL108: B04_0 Mask              */
+#define LCD_PAL108_I0_Pos                                     15                                                        /*!< LCD PAL108: I0 Position             */
+#define LCD_PAL108_I0_Msk                                     (0x01UL << LCD_PAL108_I0_Pos)                             /*!< LCD PAL108: I0 Mask                 */
+#define LCD_PAL108_R14_0_Pos                                  16                                                        /*!< LCD PAL108: R14_0 Position          */
+#define LCD_PAL108_R14_0_Msk                                  (0x1fUL << LCD_PAL108_R14_0_Pos)                          /*!< LCD PAL108: R14_0 Mask              */
+#define LCD_PAL108_G14_0_Pos                                  21                                                        /*!< LCD PAL108: G14_0 Position          */
+#define LCD_PAL108_G14_0_Msk                                  (0x1fUL << LCD_PAL108_G14_0_Pos)                          /*!< LCD PAL108: G14_0 Mask              */
+#define LCD_PAL108_B14_0_Pos                                  26                                                        /*!< LCD PAL108: B14_0 Position          */
+#define LCD_PAL108_B14_0_Msk                                  (0x1fUL << LCD_PAL108_B14_0_Pos)                          /*!< LCD PAL108: B14_0 Mask              */
+#define LCD_PAL108_I1_Pos                                     31                                                        /*!< LCD PAL108: I1 Position             */
+#define LCD_PAL108_I1_Msk                                     (0x01UL << LCD_PAL108_I1_Pos)                             /*!< LCD PAL108: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL109  -------------------------------------------
+#define LCD_PAL109_R04_0_Pos                                  0                                                         /*!< LCD PAL109: R04_0 Position          */
+#define LCD_PAL109_R04_0_Msk                                  (0x1fUL << LCD_PAL109_R04_0_Pos)                          /*!< LCD PAL109: R04_0 Mask              */
+#define LCD_PAL109_G04_0_Pos                                  5                                                         /*!< LCD PAL109: G04_0 Position          */
+#define LCD_PAL109_G04_0_Msk                                  (0x1fUL << LCD_PAL109_G04_0_Pos)                          /*!< LCD PAL109: G04_0 Mask              */
+#define LCD_PAL109_B04_0_Pos                                  10                                                        /*!< LCD PAL109: B04_0 Position          */
+#define LCD_PAL109_B04_0_Msk                                  (0x1fUL << LCD_PAL109_B04_0_Pos)                          /*!< LCD PAL109: B04_0 Mask              */
+#define LCD_PAL109_I0_Pos                                     15                                                        /*!< LCD PAL109: I0 Position             */
+#define LCD_PAL109_I0_Msk                                     (0x01UL << LCD_PAL109_I0_Pos)                             /*!< LCD PAL109: I0 Mask                 */
+#define LCD_PAL109_R14_0_Pos                                  16                                                        /*!< LCD PAL109: R14_0 Position          */
+#define LCD_PAL109_R14_0_Msk                                  (0x1fUL << LCD_PAL109_R14_0_Pos)                          /*!< LCD PAL109: R14_0 Mask              */
+#define LCD_PAL109_G14_0_Pos                                  21                                                        /*!< LCD PAL109: G14_0 Position          */
+#define LCD_PAL109_G14_0_Msk                                  (0x1fUL << LCD_PAL109_G14_0_Pos)                          /*!< LCD PAL109: G14_0 Mask              */
+#define LCD_PAL109_B14_0_Pos                                  26                                                        /*!< LCD PAL109: B14_0 Position          */
+#define LCD_PAL109_B14_0_Msk                                  (0x1fUL << LCD_PAL109_B14_0_Pos)                          /*!< LCD PAL109: B14_0 Mask              */
+#define LCD_PAL109_I1_Pos                                     31                                                        /*!< LCD PAL109: I1 Position             */
+#define LCD_PAL109_I1_Msk                                     (0x01UL << LCD_PAL109_I1_Pos)                             /*!< LCD PAL109: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL110  -------------------------------------------
+#define LCD_PAL110_R04_0_Pos                                  0                                                         /*!< LCD PAL110: R04_0 Position          */
+#define LCD_PAL110_R04_0_Msk                                  (0x1fUL << LCD_PAL110_R04_0_Pos)                          /*!< LCD PAL110: R04_0 Mask              */
+#define LCD_PAL110_G04_0_Pos                                  5                                                         /*!< LCD PAL110: G04_0 Position          */
+#define LCD_PAL110_G04_0_Msk                                  (0x1fUL << LCD_PAL110_G04_0_Pos)                          /*!< LCD PAL110: G04_0 Mask              */
+#define LCD_PAL110_B04_0_Pos                                  10                                                        /*!< LCD PAL110: B04_0 Position          */
+#define LCD_PAL110_B04_0_Msk                                  (0x1fUL << LCD_PAL110_B04_0_Pos)                          /*!< LCD PAL110: B04_0 Mask              */
+#define LCD_PAL110_I0_Pos                                     15                                                        /*!< LCD PAL110: I0 Position             */
+#define LCD_PAL110_I0_Msk                                     (0x01UL << LCD_PAL110_I0_Pos)                             /*!< LCD PAL110: I0 Mask                 */
+#define LCD_PAL110_R14_0_Pos                                  16                                                        /*!< LCD PAL110: R14_0 Position          */
+#define LCD_PAL110_R14_0_Msk                                  (0x1fUL << LCD_PAL110_R14_0_Pos)                          /*!< LCD PAL110: R14_0 Mask              */
+#define LCD_PAL110_G14_0_Pos                                  21                                                        /*!< LCD PAL110: G14_0 Position          */
+#define LCD_PAL110_G14_0_Msk                                  (0x1fUL << LCD_PAL110_G14_0_Pos)                          /*!< LCD PAL110: G14_0 Mask              */
+#define LCD_PAL110_B14_0_Pos                                  26                                                        /*!< LCD PAL110: B14_0 Position          */
+#define LCD_PAL110_B14_0_Msk                                  (0x1fUL << LCD_PAL110_B14_0_Pos)                          /*!< LCD PAL110: B14_0 Mask              */
+#define LCD_PAL110_I1_Pos                                     31                                                        /*!< LCD PAL110: I1 Position             */
+#define LCD_PAL110_I1_Msk                                     (0x01UL << LCD_PAL110_I1_Pos)                             /*!< LCD PAL110: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL111  -------------------------------------------
+#define LCD_PAL111_R04_0_Pos                                  0                                                         /*!< LCD PAL111: R04_0 Position          */
+#define LCD_PAL111_R04_0_Msk                                  (0x1fUL << LCD_PAL111_R04_0_Pos)                          /*!< LCD PAL111: R04_0 Mask              */
+#define LCD_PAL111_G04_0_Pos                                  5                                                         /*!< LCD PAL111: G04_0 Position          */
+#define LCD_PAL111_G04_0_Msk                                  (0x1fUL << LCD_PAL111_G04_0_Pos)                          /*!< LCD PAL111: G04_0 Mask              */
+#define LCD_PAL111_B04_0_Pos                                  10                                                        /*!< LCD PAL111: B04_0 Position          */
+#define LCD_PAL111_B04_0_Msk                                  (0x1fUL << LCD_PAL111_B04_0_Pos)                          /*!< LCD PAL111: B04_0 Mask              */
+#define LCD_PAL111_I0_Pos                                     15                                                        /*!< LCD PAL111: I0 Position             */
+#define LCD_PAL111_I0_Msk                                     (0x01UL << LCD_PAL111_I0_Pos)                             /*!< LCD PAL111: I0 Mask                 */
+#define LCD_PAL111_R14_0_Pos                                  16                                                        /*!< LCD PAL111: R14_0 Position          */
+#define LCD_PAL111_R14_0_Msk                                  (0x1fUL << LCD_PAL111_R14_0_Pos)                          /*!< LCD PAL111: R14_0 Mask              */
+#define LCD_PAL111_G14_0_Pos                                  21                                                        /*!< LCD PAL111: G14_0 Position          */
+#define LCD_PAL111_G14_0_Msk                                  (0x1fUL << LCD_PAL111_G14_0_Pos)                          /*!< LCD PAL111: G14_0 Mask              */
+#define LCD_PAL111_B14_0_Pos                                  26                                                        /*!< LCD PAL111: B14_0 Position          */
+#define LCD_PAL111_B14_0_Msk                                  (0x1fUL << LCD_PAL111_B14_0_Pos)                          /*!< LCD PAL111: B14_0 Mask              */
+#define LCD_PAL111_I1_Pos                                     31                                                        /*!< LCD PAL111: I1 Position             */
+#define LCD_PAL111_I1_Msk                                     (0x01UL << LCD_PAL111_I1_Pos)                             /*!< LCD PAL111: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL112  -------------------------------------------
+#define LCD_PAL112_R04_0_Pos                                  0                                                         /*!< LCD PAL112: R04_0 Position          */
+#define LCD_PAL112_R04_0_Msk                                  (0x1fUL << LCD_PAL112_R04_0_Pos)                          /*!< LCD PAL112: R04_0 Mask              */
+#define LCD_PAL112_G04_0_Pos                                  5                                                         /*!< LCD PAL112: G04_0 Position          */
+#define LCD_PAL112_G04_0_Msk                                  (0x1fUL << LCD_PAL112_G04_0_Pos)                          /*!< LCD PAL112: G04_0 Mask              */
+#define LCD_PAL112_B04_0_Pos                                  10                                                        /*!< LCD PAL112: B04_0 Position          */
+#define LCD_PAL112_B04_0_Msk                                  (0x1fUL << LCD_PAL112_B04_0_Pos)                          /*!< LCD PAL112: B04_0 Mask              */
+#define LCD_PAL112_I0_Pos                                     15                                                        /*!< LCD PAL112: I0 Position             */
+#define LCD_PAL112_I0_Msk                                     (0x01UL << LCD_PAL112_I0_Pos)                             /*!< LCD PAL112: I0 Mask                 */
+#define LCD_PAL112_R14_0_Pos                                  16                                                        /*!< LCD PAL112: R14_0 Position          */
+#define LCD_PAL112_R14_0_Msk                                  (0x1fUL << LCD_PAL112_R14_0_Pos)                          /*!< LCD PAL112: R14_0 Mask              */
+#define LCD_PAL112_G14_0_Pos                                  21                                                        /*!< LCD PAL112: G14_0 Position          */
+#define LCD_PAL112_G14_0_Msk                                  (0x1fUL << LCD_PAL112_G14_0_Pos)                          /*!< LCD PAL112: G14_0 Mask              */
+#define LCD_PAL112_B14_0_Pos                                  26                                                        /*!< LCD PAL112: B14_0 Position          */
+#define LCD_PAL112_B14_0_Msk                                  (0x1fUL << LCD_PAL112_B14_0_Pos)                          /*!< LCD PAL112: B14_0 Mask              */
+#define LCD_PAL112_I1_Pos                                     31                                                        /*!< LCD PAL112: I1 Position             */
+#define LCD_PAL112_I1_Msk                                     (0x01UL << LCD_PAL112_I1_Pos)                             /*!< LCD PAL112: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL113  -------------------------------------------
+#define LCD_PAL113_R04_0_Pos                                  0                                                         /*!< LCD PAL113: R04_0 Position          */
+#define LCD_PAL113_R04_0_Msk                                  (0x1fUL << LCD_PAL113_R04_0_Pos)                          /*!< LCD PAL113: R04_0 Mask              */
+#define LCD_PAL113_G04_0_Pos                                  5                                                         /*!< LCD PAL113: G04_0 Position          */
+#define LCD_PAL113_G04_0_Msk                                  (0x1fUL << LCD_PAL113_G04_0_Pos)                          /*!< LCD PAL113: G04_0 Mask              */
+#define LCD_PAL113_B04_0_Pos                                  10                                                        /*!< LCD PAL113: B04_0 Position          */
+#define LCD_PAL113_B04_0_Msk                                  (0x1fUL << LCD_PAL113_B04_0_Pos)                          /*!< LCD PAL113: B04_0 Mask              */
+#define LCD_PAL113_I0_Pos                                     15                                                        /*!< LCD PAL113: I0 Position             */
+#define LCD_PAL113_I0_Msk                                     (0x01UL << LCD_PAL113_I0_Pos)                             /*!< LCD PAL113: I0 Mask                 */
+#define LCD_PAL113_R14_0_Pos                                  16                                                        /*!< LCD PAL113: R14_0 Position          */
+#define LCD_PAL113_R14_0_Msk                                  (0x1fUL << LCD_PAL113_R14_0_Pos)                          /*!< LCD PAL113: R14_0 Mask              */
+#define LCD_PAL113_G14_0_Pos                                  21                                                        /*!< LCD PAL113: G14_0 Position          */
+#define LCD_PAL113_G14_0_Msk                                  (0x1fUL << LCD_PAL113_G14_0_Pos)                          /*!< LCD PAL113: G14_0 Mask              */
+#define LCD_PAL113_B14_0_Pos                                  26                                                        /*!< LCD PAL113: B14_0 Position          */
+#define LCD_PAL113_B14_0_Msk                                  (0x1fUL << LCD_PAL113_B14_0_Pos)                          /*!< LCD PAL113: B14_0 Mask              */
+#define LCD_PAL113_I1_Pos                                     31                                                        /*!< LCD PAL113: I1 Position             */
+#define LCD_PAL113_I1_Msk                                     (0x01UL << LCD_PAL113_I1_Pos)                             /*!< LCD PAL113: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL114  -------------------------------------------
+#define LCD_PAL114_R04_0_Pos                                  0                                                         /*!< LCD PAL114: R04_0 Position          */
+#define LCD_PAL114_R04_0_Msk                                  (0x1fUL << LCD_PAL114_R04_0_Pos)                          /*!< LCD PAL114: R04_0 Mask              */
+#define LCD_PAL114_G04_0_Pos                                  5                                                         /*!< LCD PAL114: G04_0 Position          */
+#define LCD_PAL114_G04_0_Msk                                  (0x1fUL << LCD_PAL114_G04_0_Pos)                          /*!< LCD PAL114: G04_0 Mask              */
+#define LCD_PAL114_B04_0_Pos                                  10                                                        /*!< LCD PAL114: B04_0 Position          */
+#define LCD_PAL114_B04_0_Msk                                  (0x1fUL << LCD_PAL114_B04_0_Pos)                          /*!< LCD PAL114: B04_0 Mask              */
+#define LCD_PAL114_I0_Pos                                     15                                                        /*!< LCD PAL114: I0 Position             */
+#define LCD_PAL114_I0_Msk                                     (0x01UL << LCD_PAL114_I0_Pos)                             /*!< LCD PAL114: I0 Mask                 */
+#define LCD_PAL114_R14_0_Pos                                  16                                                        /*!< LCD PAL114: R14_0 Position          */
+#define LCD_PAL114_R14_0_Msk                                  (0x1fUL << LCD_PAL114_R14_0_Pos)                          /*!< LCD PAL114: R14_0 Mask              */
+#define LCD_PAL114_G14_0_Pos                                  21                                                        /*!< LCD PAL114: G14_0 Position          */
+#define LCD_PAL114_G14_0_Msk                                  (0x1fUL << LCD_PAL114_G14_0_Pos)                          /*!< LCD PAL114: G14_0 Mask              */
+#define LCD_PAL114_B14_0_Pos                                  26                                                        /*!< LCD PAL114: B14_0 Position          */
+#define LCD_PAL114_B14_0_Msk                                  (0x1fUL << LCD_PAL114_B14_0_Pos)                          /*!< LCD PAL114: B14_0 Mask              */
+#define LCD_PAL114_I1_Pos                                     31                                                        /*!< LCD PAL114: I1 Position             */
+#define LCD_PAL114_I1_Msk                                     (0x01UL << LCD_PAL114_I1_Pos)                             /*!< LCD PAL114: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL115  -------------------------------------------
+#define LCD_PAL115_R04_0_Pos                                  0                                                         /*!< LCD PAL115: R04_0 Position          */
+#define LCD_PAL115_R04_0_Msk                                  (0x1fUL << LCD_PAL115_R04_0_Pos)                          /*!< LCD PAL115: R04_0 Mask              */
+#define LCD_PAL115_G04_0_Pos                                  5                                                         /*!< LCD PAL115: G04_0 Position          */
+#define LCD_PAL115_G04_0_Msk                                  (0x1fUL << LCD_PAL115_G04_0_Pos)                          /*!< LCD PAL115: G04_0 Mask              */
+#define LCD_PAL115_B04_0_Pos                                  10                                                        /*!< LCD PAL115: B04_0 Position          */
+#define LCD_PAL115_B04_0_Msk                                  (0x1fUL << LCD_PAL115_B04_0_Pos)                          /*!< LCD PAL115: B04_0 Mask              */
+#define LCD_PAL115_I0_Pos                                     15                                                        /*!< LCD PAL115: I0 Position             */
+#define LCD_PAL115_I0_Msk                                     (0x01UL << LCD_PAL115_I0_Pos)                             /*!< LCD PAL115: I0 Mask                 */
+#define LCD_PAL115_R14_0_Pos                                  16                                                        /*!< LCD PAL115: R14_0 Position          */
+#define LCD_PAL115_R14_0_Msk                                  (0x1fUL << LCD_PAL115_R14_0_Pos)                          /*!< LCD PAL115: R14_0 Mask              */
+#define LCD_PAL115_G14_0_Pos                                  21                                                        /*!< LCD PAL115: G14_0 Position          */
+#define LCD_PAL115_G14_0_Msk                                  (0x1fUL << LCD_PAL115_G14_0_Pos)                          /*!< LCD PAL115: G14_0 Mask              */
+#define LCD_PAL115_B14_0_Pos                                  26                                                        /*!< LCD PAL115: B14_0 Position          */
+#define LCD_PAL115_B14_0_Msk                                  (0x1fUL << LCD_PAL115_B14_0_Pos)                          /*!< LCD PAL115: B14_0 Mask              */
+#define LCD_PAL115_I1_Pos                                     31                                                        /*!< LCD PAL115: I1 Position             */
+#define LCD_PAL115_I1_Msk                                     (0x01UL << LCD_PAL115_I1_Pos)                             /*!< LCD PAL115: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL116  -------------------------------------------
+#define LCD_PAL116_R04_0_Pos                                  0                                                         /*!< LCD PAL116: R04_0 Position          */
+#define LCD_PAL116_R04_0_Msk                                  (0x1fUL << LCD_PAL116_R04_0_Pos)                          /*!< LCD PAL116: R04_0 Mask              */
+#define LCD_PAL116_G04_0_Pos                                  5                                                         /*!< LCD PAL116: G04_0 Position          */
+#define LCD_PAL116_G04_0_Msk                                  (0x1fUL << LCD_PAL116_G04_0_Pos)                          /*!< LCD PAL116: G04_0 Mask              */
+#define LCD_PAL116_B04_0_Pos                                  10                                                        /*!< LCD PAL116: B04_0 Position          */
+#define LCD_PAL116_B04_0_Msk                                  (0x1fUL << LCD_PAL116_B04_0_Pos)                          /*!< LCD PAL116: B04_0 Mask              */
+#define LCD_PAL116_I0_Pos                                     15                                                        /*!< LCD PAL116: I0 Position             */
+#define LCD_PAL116_I0_Msk                                     (0x01UL << LCD_PAL116_I0_Pos)                             /*!< LCD PAL116: I0 Mask                 */
+#define LCD_PAL116_R14_0_Pos                                  16                                                        /*!< LCD PAL116: R14_0 Position          */
+#define LCD_PAL116_R14_0_Msk                                  (0x1fUL << LCD_PAL116_R14_0_Pos)                          /*!< LCD PAL116: R14_0 Mask              */
+#define LCD_PAL116_G14_0_Pos                                  21                                                        /*!< LCD PAL116: G14_0 Position          */
+#define LCD_PAL116_G14_0_Msk                                  (0x1fUL << LCD_PAL116_G14_0_Pos)                          /*!< LCD PAL116: G14_0 Mask              */
+#define LCD_PAL116_B14_0_Pos                                  26                                                        /*!< LCD PAL116: B14_0 Position          */
+#define LCD_PAL116_B14_0_Msk                                  (0x1fUL << LCD_PAL116_B14_0_Pos)                          /*!< LCD PAL116: B14_0 Mask              */
+#define LCD_PAL116_I1_Pos                                     31                                                        /*!< LCD PAL116: I1 Position             */
+#define LCD_PAL116_I1_Msk                                     (0x01UL << LCD_PAL116_I1_Pos)                             /*!< LCD PAL116: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL117  -------------------------------------------
+#define LCD_PAL117_R04_0_Pos                                  0                                                         /*!< LCD PAL117: R04_0 Position          */
+#define LCD_PAL117_R04_0_Msk                                  (0x1fUL << LCD_PAL117_R04_0_Pos)                          /*!< LCD PAL117: R04_0 Mask              */
+#define LCD_PAL117_G04_0_Pos                                  5                                                         /*!< LCD PAL117: G04_0 Position          */
+#define LCD_PAL117_G04_0_Msk                                  (0x1fUL << LCD_PAL117_G04_0_Pos)                          /*!< LCD PAL117: G04_0 Mask              */
+#define LCD_PAL117_B04_0_Pos                                  10                                                        /*!< LCD PAL117: B04_0 Position          */
+#define LCD_PAL117_B04_0_Msk                                  (0x1fUL << LCD_PAL117_B04_0_Pos)                          /*!< LCD PAL117: B04_0 Mask              */
+#define LCD_PAL117_I0_Pos                                     15                                                        /*!< LCD PAL117: I0 Position             */
+#define LCD_PAL117_I0_Msk                                     (0x01UL << LCD_PAL117_I0_Pos)                             /*!< LCD PAL117: I0 Mask                 */
+#define LCD_PAL117_R14_0_Pos                                  16                                                        /*!< LCD PAL117: R14_0 Position          */
+#define LCD_PAL117_R14_0_Msk                                  (0x1fUL << LCD_PAL117_R14_0_Pos)                          /*!< LCD PAL117: R14_0 Mask              */
+#define LCD_PAL117_G14_0_Pos                                  21                                                        /*!< LCD PAL117: G14_0 Position          */
+#define LCD_PAL117_G14_0_Msk                                  (0x1fUL << LCD_PAL117_G14_0_Pos)                          /*!< LCD PAL117: G14_0 Mask              */
+#define LCD_PAL117_B14_0_Pos                                  26                                                        /*!< LCD PAL117: B14_0 Position          */
+#define LCD_PAL117_B14_0_Msk                                  (0x1fUL << LCD_PAL117_B14_0_Pos)                          /*!< LCD PAL117: B14_0 Mask              */
+#define LCD_PAL117_I1_Pos                                     31                                                        /*!< LCD PAL117: I1 Position             */
+#define LCD_PAL117_I1_Msk                                     (0x01UL << LCD_PAL117_I1_Pos)                             /*!< LCD PAL117: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL118  -------------------------------------------
+#define LCD_PAL118_R04_0_Pos                                  0                                                         /*!< LCD PAL118: R04_0 Position          */
+#define LCD_PAL118_R04_0_Msk                                  (0x1fUL << LCD_PAL118_R04_0_Pos)                          /*!< LCD PAL118: R04_0 Mask              */
+#define LCD_PAL118_G04_0_Pos                                  5                                                         /*!< LCD PAL118: G04_0 Position          */
+#define LCD_PAL118_G04_0_Msk                                  (0x1fUL << LCD_PAL118_G04_0_Pos)                          /*!< LCD PAL118: G04_0 Mask              */
+#define LCD_PAL118_B04_0_Pos                                  10                                                        /*!< LCD PAL118: B04_0 Position          */
+#define LCD_PAL118_B04_0_Msk                                  (0x1fUL << LCD_PAL118_B04_0_Pos)                          /*!< LCD PAL118: B04_0 Mask              */
+#define LCD_PAL118_I0_Pos                                     15                                                        /*!< LCD PAL118: I0 Position             */
+#define LCD_PAL118_I0_Msk                                     (0x01UL << LCD_PAL118_I0_Pos)                             /*!< LCD PAL118: I0 Mask                 */
+#define LCD_PAL118_R14_0_Pos                                  16                                                        /*!< LCD PAL118: R14_0 Position          */
+#define LCD_PAL118_R14_0_Msk                                  (0x1fUL << LCD_PAL118_R14_0_Pos)                          /*!< LCD PAL118: R14_0 Mask              */
+#define LCD_PAL118_G14_0_Pos                                  21                                                        /*!< LCD PAL118: G14_0 Position          */
+#define LCD_PAL118_G14_0_Msk                                  (0x1fUL << LCD_PAL118_G14_0_Pos)                          /*!< LCD PAL118: G14_0 Mask              */
+#define LCD_PAL118_B14_0_Pos                                  26                                                        /*!< LCD PAL118: B14_0 Position          */
+#define LCD_PAL118_B14_0_Msk                                  (0x1fUL << LCD_PAL118_B14_0_Pos)                          /*!< LCD PAL118: B14_0 Mask              */
+#define LCD_PAL118_I1_Pos                                     31                                                        /*!< LCD PAL118: I1 Position             */
+#define LCD_PAL118_I1_Msk                                     (0x01UL << LCD_PAL118_I1_Pos)                             /*!< LCD PAL118: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL119  -------------------------------------------
+#define LCD_PAL119_R04_0_Pos                                  0                                                         /*!< LCD PAL119: R04_0 Position          */
+#define LCD_PAL119_R04_0_Msk                                  (0x1fUL << LCD_PAL119_R04_0_Pos)                          /*!< LCD PAL119: R04_0 Mask              */
+#define LCD_PAL119_G04_0_Pos                                  5                                                         /*!< LCD PAL119: G04_0 Position          */
+#define LCD_PAL119_G04_0_Msk                                  (0x1fUL << LCD_PAL119_G04_0_Pos)                          /*!< LCD PAL119: G04_0 Mask              */
+#define LCD_PAL119_B04_0_Pos                                  10                                                        /*!< LCD PAL119: B04_0 Position          */
+#define LCD_PAL119_B04_0_Msk                                  (0x1fUL << LCD_PAL119_B04_0_Pos)                          /*!< LCD PAL119: B04_0 Mask              */
+#define LCD_PAL119_I0_Pos                                     15                                                        /*!< LCD PAL119: I0 Position             */
+#define LCD_PAL119_I0_Msk                                     (0x01UL << LCD_PAL119_I0_Pos)                             /*!< LCD PAL119: I0 Mask                 */
+#define LCD_PAL119_R14_0_Pos                                  16                                                        /*!< LCD PAL119: R14_0 Position          */
+#define LCD_PAL119_R14_0_Msk                                  (0x1fUL << LCD_PAL119_R14_0_Pos)                          /*!< LCD PAL119: R14_0 Mask              */
+#define LCD_PAL119_G14_0_Pos                                  21                                                        /*!< LCD PAL119: G14_0 Position          */
+#define LCD_PAL119_G14_0_Msk                                  (0x1fUL << LCD_PAL119_G14_0_Pos)                          /*!< LCD PAL119: G14_0 Mask              */
+#define LCD_PAL119_B14_0_Pos                                  26                                                        /*!< LCD PAL119: B14_0 Position          */
+#define LCD_PAL119_B14_0_Msk                                  (0x1fUL << LCD_PAL119_B14_0_Pos)                          /*!< LCD PAL119: B14_0 Mask              */
+#define LCD_PAL119_I1_Pos                                     31                                                        /*!< LCD PAL119: I1 Position             */
+#define LCD_PAL119_I1_Msk                                     (0x01UL << LCD_PAL119_I1_Pos)                             /*!< LCD PAL119: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL120  -------------------------------------------
+#define LCD_PAL120_R04_0_Pos                                  0                                                         /*!< LCD PAL120: R04_0 Position          */
+#define LCD_PAL120_R04_0_Msk                                  (0x1fUL << LCD_PAL120_R04_0_Pos)                          /*!< LCD PAL120: R04_0 Mask              */
+#define LCD_PAL120_G04_0_Pos                                  5                                                         /*!< LCD PAL120: G04_0 Position          */
+#define LCD_PAL120_G04_0_Msk                                  (0x1fUL << LCD_PAL120_G04_0_Pos)                          /*!< LCD PAL120: G04_0 Mask              */
+#define LCD_PAL120_B04_0_Pos                                  10                                                        /*!< LCD PAL120: B04_0 Position          */
+#define LCD_PAL120_B04_0_Msk                                  (0x1fUL << LCD_PAL120_B04_0_Pos)                          /*!< LCD PAL120: B04_0 Mask              */
+#define LCD_PAL120_I0_Pos                                     15                                                        /*!< LCD PAL120: I0 Position             */
+#define LCD_PAL120_I0_Msk                                     (0x01UL << LCD_PAL120_I0_Pos)                             /*!< LCD PAL120: I0 Mask                 */
+#define LCD_PAL120_R14_0_Pos                                  16                                                        /*!< LCD PAL120: R14_0 Position          */
+#define LCD_PAL120_R14_0_Msk                                  (0x1fUL << LCD_PAL120_R14_0_Pos)                          /*!< LCD PAL120: R14_0 Mask              */
+#define LCD_PAL120_G14_0_Pos                                  21                                                        /*!< LCD PAL120: G14_0 Position          */
+#define LCD_PAL120_G14_0_Msk                                  (0x1fUL << LCD_PAL120_G14_0_Pos)                          /*!< LCD PAL120: G14_0 Mask              */
+#define LCD_PAL120_B14_0_Pos                                  26                                                        /*!< LCD PAL120: B14_0 Position          */
+#define LCD_PAL120_B14_0_Msk                                  (0x1fUL << LCD_PAL120_B14_0_Pos)                          /*!< LCD PAL120: B14_0 Mask              */
+#define LCD_PAL120_I1_Pos                                     31                                                        /*!< LCD PAL120: I1 Position             */
+#define LCD_PAL120_I1_Msk                                     (0x01UL << LCD_PAL120_I1_Pos)                             /*!< LCD PAL120: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL121  -------------------------------------------
+#define LCD_PAL121_R04_0_Pos                                  0                                                         /*!< LCD PAL121: R04_0 Position          */
+#define LCD_PAL121_R04_0_Msk                                  (0x1fUL << LCD_PAL121_R04_0_Pos)                          /*!< LCD PAL121: R04_0 Mask              */
+#define LCD_PAL121_G04_0_Pos                                  5                                                         /*!< LCD PAL121: G04_0 Position          */
+#define LCD_PAL121_G04_0_Msk                                  (0x1fUL << LCD_PAL121_G04_0_Pos)                          /*!< LCD PAL121: G04_0 Mask              */
+#define LCD_PAL121_B04_0_Pos                                  10                                                        /*!< LCD PAL121: B04_0 Position          */
+#define LCD_PAL121_B04_0_Msk                                  (0x1fUL << LCD_PAL121_B04_0_Pos)                          /*!< LCD PAL121: B04_0 Mask              */
+#define LCD_PAL121_I0_Pos                                     15                                                        /*!< LCD PAL121: I0 Position             */
+#define LCD_PAL121_I0_Msk                                     (0x01UL << LCD_PAL121_I0_Pos)                             /*!< LCD PAL121: I0 Mask                 */
+#define LCD_PAL121_R14_0_Pos                                  16                                                        /*!< LCD PAL121: R14_0 Position          */
+#define LCD_PAL121_R14_0_Msk                                  (0x1fUL << LCD_PAL121_R14_0_Pos)                          /*!< LCD PAL121: R14_0 Mask              */
+#define LCD_PAL121_G14_0_Pos                                  21                                                        /*!< LCD PAL121: G14_0 Position          */
+#define LCD_PAL121_G14_0_Msk                                  (0x1fUL << LCD_PAL121_G14_0_Pos)                          /*!< LCD PAL121: G14_0 Mask              */
+#define LCD_PAL121_B14_0_Pos                                  26                                                        /*!< LCD PAL121: B14_0 Position          */
+#define LCD_PAL121_B14_0_Msk                                  (0x1fUL << LCD_PAL121_B14_0_Pos)                          /*!< LCD PAL121: B14_0 Mask              */
+#define LCD_PAL121_I1_Pos                                     31                                                        /*!< LCD PAL121: I1 Position             */
+#define LCD_PAL121_I1_Msk                                     (0x01UL << LCD_PAL121_I1_Pos)                             /*!< LCD PAL121: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL122  -------------------------------------------
+#define LCD_PAL122_R04_0_Pos                                  0                                                         /*!< LCD PAL122: R04_0 Position          */
+#define LCD_PAL122_R04_0_Msk                                  (0x1fUL << LCD_PAL122_R04_0_Pos)                          /*!< LCD PAL122: R04_0 Mask              */
+#define LCD_PAL122_G04_0_Pos                                  5                                                         /*!< LCD PAL122: G04_0 Position          */
+#define LCD_PAL122_G04_0_Msk                                  (0x1fUL << LCD_PAL122_G04_0_Pos)                          /*!< LCD PAL122: G04_0 Mask              */
+#define LCD_PAL122_B04_0_Pos                                  10                                                        /*!< LCD PAL122: B04_0 Position          */
+#define LCD_PAL122_B04_0_Msk                                  (0x1fUL << LCD_PAL122_B04_0_Pos)                          /*!< LCD PAL122: B04_0 Mask              */
+#define LCD_PAL122_I0_Pos                                     15                                                        /*!< LCD PAL122: I0 Position             */
+#define LCD_PAL122_I0_Msk                                     (0x01UL << LCD_PAL122_I0_Pos)                             /*!< LCD PAL122: I0 Mask                 */
+#define LCD_PAL122_R14_0_Pos                                  16                                                        /*!< LCD PAL122: R14_0 Position          */
+#define LCD_PAL122_R14_0_Msk                                  (0x1fUL << LCD_PAL122_R14_0_Pos)                          /*!< LCD PAL122: R14_0 Mask              */
+#define LCD_PAL122_G14_0_Pos                                  21                                                        /*!< LCD PAL122: G14_0 Position          */
+#define LCD_PAL122_G14_0_Msk                                  (0x1fUL << LCD_PAL122_G14_0_Pos)                          /*!< LCD PAL122: G14_0 Mask              */
+#define LCD_PAL122_B14_0_Pos                                  26                                                        /*!< LCD PAL122: B14_0 Position          */
+#define LCD_PAL122_B14_0_Msk                                  (0x1fUL << LCD_PAL122_B14_0_Pos)                          /*!< LCD PAL122: B14_0 Mask              */
+#define LCD_PAL122_I1_Pos                                     31                                                        /*!< LCD PAL122: I1 Position             */
+#define LCD_PAL122_I1_Msk                                     (0x01UL << LCD_PAL122_I1_Pos)                             /*!< LCD PAL122: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL123  -------------------------------------------
+#define LCD_PAL123_R04_0_Pos                                  0                                                         /*!< LCD PAL123: R04_0 Position          */
+#define LCD_PAL123_R04_0_Msk                                  (0x1fUL << LCD_PAL123_R04_0_Pos)                          /*!< LCD PAL123: R04_0 Mask              */
+#define LCD_PAL123_G04_0_Pos                                  5                                                         /*!< LCD PAL123: G04_0 Position          */
+#define LCD_PAL123_G04_0_Msk                                  (0x1fUL << LCD_PAL123_G04_0_Pos)                          /*!< LCD PAL123: G04_0 Mask              */
+#define LCD_PAL123_B04_0_Pos                                  10                                                        /*!< LCD PAL123: B04_0 Position          */
+#define LCD_PAL123_B04_0_Msk                                  (0x1fUL << LCD_PAL123_B04_0_Pos)                          /*!< LCD PAL123: B04_0 Mask              */
+#define LCD_PAL123_I0_Pos                                     15                                                        /*!< LCD PAL123: I0 Position             */
+#define LCD_PAL123_I0_Msk                                     (0x01UL << LCD_PAL123_I0_Pos)                             /*!< LCD PAL123: I0 Mask                 */
+#define LCD_PAL123_R14_0_Pos                                  16                                                        /*!< LCD PAL123: R14_0 Position          */
+#define LCD_PAL123_R14_0_Msk                                  (0x1fUL << LCD_PAL123_R14_0_Pos)                          /*!< LCD PAL123: R14_0 Mask              */
+#define LCD_PAL123_G14_0_Pos                                  21                                                        /*!< LCD PAL123: G14_0 Position          */
+#define LCD_PAL123_G14_0_Msk                                  (0x1fUL << LCD_PAL123_G14_0_Pos)                          /*!< LCD PAL123: G14_0 Mask              */
+#define LCD_PAL123_B14_0_Pos                                  26                                                        /*!< LCD PAL123: B14_0 Position          */
+#define LCD_PAL123_B14_0_Msk                                  (0x1fUL << LCD_PAL123_B14_0_Pos)                          /*!< LCD PAL123: B14_0 Mask              */
+#define LCD_PAL123_I1_Pos                                     31                                                        /*!< LCD PAL123: I1 Position             */
+#define LCD_PAL123_I1_Msk                                     (0x01UL << LCD_PAL123_I1_Pos)                             /*!< LCD PAL123: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL124  -------------------------------------------
+#define LCD_PAL124_R04_0_Pos                                  0                                                         /*!< LCD PAL124: R04_0 Position          */
+#define LCD_PAL124_R04_0_Msk                                  (0x1fUL << LCD_PAL124_R04_0_Pos)                          /*!< LCD PAL124: R04_0 Mask              */
+#define LCD_PAL124_G04_0_Pos                                  5                                                         /*!< LCD PAL124: G04_0 Position          */
+#define LCD_PAL124_G04_0_Msk                                  (0x1fUL << LCD_PAL124_G04_0_Pos)                          /*!< LCD PAL124: G04_0 Mask              */
+#define LCD_PAL124_B04_0_Pos                                  10                                                        /*!< LCD PAL124: B04_0 Position          */
+#define LCD_PAL124_B04_0_Msk                                  (0x1fUL << LCD_PAL124_B04_0_Pos)                          /*!< LCD PAL124: B04_0 Mask              */
+#define LCD_PAL124_I0_Pos                                     15                                                        /*!< LCD PAL124: I0 Position             */
+#define LCD_PAL124_I0_Msk                                     (0x01UL << LCD_PAL124_I0_Pos)                             /*!< LCD PAL124: I0 Mask                 */
+#define LCD_PAL124_R14_0_Pos                                  16                                                        /*!< LCD PAL124: R14_0 Position          */
+#define LCD_PAL124_R14_0_Msk                                  (0x1fUL << LCD_PAL124_R14_0_Pos)                          /*!< LCD PAL124: R14_0 Mask              */
+#define LCD_PAL124_G14_0_Pos                                  21                                                        /*!< LCD PAL124: G14_0 Position          */
+#define LCD_PAL124_G14_0_Msk                                  (0x1fUL << LCD_PAL124_G14_0_Pos)                          /*!< LCD PAL124: G14_0 Mask              */
+#define LCD_PAL124_B14_0_Pos                                  26                                                        /*!< LCD PAL124: B14_0 Position          */
+#define LCD_PAL124_B14_0_Msk                                  (0x1fUL << LCD_PAL124_B14_0_Pos)                          /*!< LCD PAL124: B14_0 Mask              */
+#define LCD_PAL124_I1_Pos                                     31                                                        /*!< LCD PAL124: I1 Position             */
+#define LCD_PAL124_I1_Msk                                     (0x01UL << LCD_PAL124_I1_Pos)                             /*!< LCD PAL124: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL125  -------------------------------------------
+#define LCD_PAL125_R04_0_Pos                                  0                                                         /*!< LCD PAL125: R04_0 Position          */
+#define LCD_PAL125_R04_0_Msk                                  (0x1fUL << LCD_PAL125_R04_0_Pos)                          /*!< LCD PAL125: R04_0 Mask              */
+#define LCD_PAL125_G04_0_Pos                                  5                                                         /*!< LCD PAL125: G04_0 Position          */
+#define LCD_PAL125_G04_0_Msk                                  (0x1fUL << LCD_PAL125_G04_0_Pos)                          /*!< LCD PAL125: G04_0 Mask              */
+#define LCD_PAL125_B04_0_Pos                                  10                                                        /*!< LCD PAL125: B04_0 Position          */
+#define LCD_PAL125_B04_0_Msk                                  (0x1fUL << LCD_PAL125_B04_0_Pos)                          /*!< LCD PAL125: B04_0 Mask              */
+#define LCD_PAL125_I0_Pos                                     15                                                        /*!< LCD PAL125: I0 Position             */
+#define LCD_PAL125_I0_Msk                                     (0x01UL << LCD_PAL125_I0_Pos)                             /*!< LCD PAL125: I0 Mask                 */
+#define LCD_PAL125_R14_0_Pos                                  16                                                        /*!< LCD PAL125: R14_0 Position          */
+#define LCD_PAL125_R14_0_Msk                                  (0x1fUL << LCD_PAL125_R14_0_Pos)                          /*!< LCD PAL125: R14_0 Mask              */
+#define LCD_PAL125_G14_0_Pos                                  21                                                        /*!< LCD PAL125: G14_0 Position          */
+#define LCD_PAL125_G14_0_Msk                                  (0x1fUL << LCD_PAL125_G14_0_Pos)                          /*!< LCD PAL125: G14_0 Mask              */
+#define LCD_PAL125_B14_0_Pos                                  26                                                        /*!< LCD PAL125: B14_0 Position          */
+#define LCD_PAL125_B14_0_Msk                                  (0x1fUL << LCD_PAL125_B14_0_Pos)                          /*!< LCD PAL125: B14_0 Mask              */
+#define LCD_PAL125_I1_Pos                                     31                                                        /*!< LCD PAL125: I1 Position             */
+#define LCD_PAL125_I1_Msk                                     (0x01UL << LCD_PAL125_I1_Pos)                             /*!< LCD PAL125: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL126  -------------------------------------------
+#define LCD_PAL126_R04_0_Pos                                  0                                                         /*!< LCD PAL126: R04_0 Position          */
+#define LCD_PAL126_R04_0_Msk                                  (0x1fUL << LCD_PAL126_R04_0_Pos)                          /*!< LCD PAL126: R04_0 Mask              */
+#define LCD_PAL126_G04_0_Pos                                  5                                                         /*!< LCD PAL126: G04_0 Position          */
+#define LCD_PAL126_G04_0_Msk                                  (0x1fUL << LCD_PAL126_G04_0_Pos)                          /*!< LCD PAL126: G04_0 Mask              */
+#define LCD_PAL126_B04_0_Pos                                  10                                                        /*!< LCD PAL126: B04_0 Position          */
+#define LCD_PAL126_B04_0_Msk                                  (0x1fUL << LCD_PAL126_B04_0_Pos)                          /*!< LCD PAL126: B04_0 Mask              */
+#define LCD_PAL126_I0_Pos                                     15                                                        /*!< LCD PAL126: I0 Position             */
+#define LCD_PAL126_I0_Msk                                     (0x01UL << LCD_PAL126_I0_Pos)                             /*!< LCD PAL126: I0 Mask                 */
+#define LCD_PAL126_R14_0_Pos                                  16                                                        /*!< LCD PAL126: R14_0 Position          */
+#define LCD_PAL126_R14_0_Msk                                  (0x1fUL << LCD_PAL126_R14_0_Pos)                          /*!< LCD PAL126: R14_0 Mask              */
+#define LCD_PAL126_G14_0_Pos                                  21                                                        /*!< LCD PAL126: G14_0 Position          */
+#define LCD_PAL126_G14_0_Msk                                  (0x1fUL << LCD_PAL126_G14_0_Pos)                          /*!< LCD PAL126: G14_0 Mask              */
+#define LCD_PAL126_B14_0_Pos                                  26                                                        /*!< LCD PAL126: B14_0 Position          */
+#define LCD_PAL126_B14_0_Msk                                  (0x1fUL << LCD_PAL126_B14_0_Pos)                          /*!< LCD PAL126: B14_0 Mask              */
+#define LCD_PAL126_I1_Pos                                     31                                                        /*!< LCD PAL126: I1 Position             */
+#define LCD_PAL126_I1_Msk                                     (0x01UL << LCD_PAL126_I1_Pos)                             /*!< LCD PAL126: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL127  -------------------------------------------
+#define LCD_PAL127_R04_0_Pos                                  0                                                         /*!< LCD PAL127: R04_0 Position          */
+#define LCD_PAL127_R04_0_Msk                                  (0x1fUL << LCD_PAL127_R04_0_Pos)                          /*!< LCD PAL127: R04_0 Mask              */
+#define LCD_PAL127_G04_0_Pos                                  5                                                         /*!< LCD PAL127: G04_0 Position          */
+#define LCD_PAL127_G04_0_Msk                                  (0x1fUL << LCD_PAL127_G04_0_Pos)                          /*!< LCD PAL127: G04_0 Mask              */
+#define LCD_PAL127_B04_0_Pos                                  10                                                        /*!< LCD PAL127: B04_0 Position          */
+#define LCD_PAL127_B04_0_Msk                                  (0x1fUL << LCD_PAL127_B04_0_Pos)                          /*!< LCD PAL127: B04_0 Mask              */
+#define LCD_PAL127_I0_Pos                                     15                                                        /*!< LCD PAL127: I0 Position             */
+#define LCD_PAL127_I0_Msk                                     (0x01UL << LCD_PAL127_I0_Pos)                             /*!< LCD PAL127: I0 Mask                 */
+#define LCD_PAL127_R14_0_Pos                                  16                                                        /*!< LCD PAL127: R14_0 Position          */
+#define LCD_PAL127_R14_0_Msk                                  (0x1fUL << LCD_PAL127_R14_0_Pos)                          /*!< LCD PAL127: R14_0 Mask              */
+#define LCD_PAL127_G14_0_Pos                                  21                                                        /*!< LCD PAL127: G14_0 Position          */
+#define LCD_PAL127_G14_0_Msk                                  (0x1fUL << LCD_PAL127_G14_0_Pos)                          /*!< LCD PAL127: G14_0 Mask              */
+#define LCD_PAL127_B14_0_Pos                                  26                                                        /*!< LCD PAL127: B14_0 Position          */
+#define LCD_PAL127_B14_0_Msk                                  (0x1fUL << LCD_PAL127_B14_0_Pos)                          /*!< LCD PAL127: B14_0 Mask              */
+#define LCD_PAL127_I1_Pos                                     31                                                        /*!< LCD PAL127: I1 Position             */
+#define LCD_PAL127_I1_Msk                                     (0x01UL << LCD_PAL127_I1_Pos)                             /*!< LCD PAL127: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL128  -------------------------------------------
+#define LCD_PAL128_R04_0_Pos                                  0                                                         /*!< LCD PAL128: R04_0 Position          */
+#define LCD_PAL128_R04_0_Msk                                  (0x1fUL << LCD_PAL128_R04_0_Pos)                          /*!< LCD PAL128: R04_0 Mask              */
+#define LCD_PAL128_G04_0_Pos                                  5                                                         /*!< LCD PAL128: G04_0 Position          */
+#define LCD_PAL128_G04_0_Msk                                  (0x1fUL << LCD_PAL128_G04_0_Pos)                          /*!< LCD PAL128: G04_0 Mask              */
+#define LCD_PAL128_B04_0_Pos                                  10                                                        /*!< LCD PAL128: B04_0 Position          */
+#define LCD_PAL128_B04_0_Msk                                  (0x1fUL << LCD_PAL128_B04_0_Pos)                          /*!< LCD PAL128: B04_0 Mask              */
+#define LCD_PAL128_I0_Pos                                     15                                                        /*!< LCD PAL128: I0 Position             */
+#define LCD_PAL128_I0_Msk                                     (0x01UL << LCD_PAL128_I0_Pos)                             /*!< LCD PAL128: I0 Mask                 */
+#define LCD_PAL128_R14_0_Pos                                  16                                                        /*!< LCD PAL128: R14_0 Position          */
+#define LCD_PAL128_R14_0_Msk                                  (0x1fUL << LCD_PAL128_R14_0_Pos)                          /*!< LCD PAL128: R14_0 Mask              */
+#define LCD_PAL128_G14_0_Pos                                  21                                                        /*!< LCD PAL128: G14_0 Position          */
+#define LCD_PAL128_G14_0_Msk                                  (0x1fUL << LCD_PAL128_G14_0_Pos)                          /*!< LCD PAL128: G14_0 Mask              */
+#define LCD_PAL128_B14_0_Pos                                  26                                                        /*!< LCD PAL128: B14_0 Position          */
+#define LCD_PAL128_B14_0_Msk                                  (0x1fUL << LCD_PAL128_B14_0_Pos)                          /*!< LCD PAL128: B14_0 Mask              */
+#define LCD_PAL128_I1_Pos                                     31                                                        /*!< LCD PAL128: I1 Position             */
+#define LCD_PAL128_I1_Msk                                     (0x01UL << LCD_PAL128_I1_Pos)                             /*!< LCD PAL128: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL129  -------------------------------------------
+#define LCD_PAL129_R04_0_Pos                                  0                                                         /*!< LCD PAL129: R04_0 Position          */
+#define LCD_PAL129_R04_0_Msk                                  (0x1fUL << LCD_PAL129_R04_0_Pos)                          /*!< LCD PAL129: R04_0 Mask              */
+#define LCD_PAL129_G04_0_Pos                                  5                                                         /*!< LCD PAL129: G04_0 Position          */
+#define LCD_PAL129_G04_0_Msk                                  (0x1fUL << LCD_PAL129_G04_0_Pos)                          /*!< LCD PAL129: G04_0 Mask              */
+#define LCD_PAL129_B04_0_Pos                                  10                                                        /*!< LCD PAL129: B04_0 Position          */
+#define LCD_PAL129_B04_0_Msk                                  (0x1fUL << LCD_PAL129_B04_0_Pos)                          /*!< LCD PAL129: B04_0 Mask              */
+#define LCD_PAL129_I0_Pos                                     15                                                        /*!< LCD PAL129: I0 Position             */
+#define LCD_PAL129_I0_Msk                                     (0x01UL << LCD_PAL129_I0_Pos)                             /*!< LCD PAL129: I0 Mask                 */
+#define LCD_PAL129_R14_0_Pos                                  16                                                        /*!< LCD PAL129: R14_0 Position          */
+#define LCD_PAL129_R14_0_Msk                                  (0x1fUL << LCD_PAL129_R14_0_Pos)                          /*!< LCD PAL129: R14_0 Mask              */
+#define LCD_PAL129_G14_0_Pos                                  21                                                        /*!< LCD PAL129: G14_0 Position          */
+#define LCD_PAL129_G14_0_Msk                                  (0x1fUL << LCD_PAL129_G14_0_Pos)                          /*!< LCD PAL129: G14_0 Mask              */
+#define LCD_PAL129_B14_0_Pos                                  26                                                        /*!< LCD PAL129: B14_0 Position          */
+#define LCD_PAL129_B14_0_Msk                                  (0x1fUL << LCD_PAL129_B14_0_Pos)                          /*!< LCD PAL129: B14_0 Mask              */
+#define LCD_PAL129_I1_Pos                                     31                                                        /*!< LCD PAL129: I1 Position             */
+#define LCD_PAL129_I1_Msk                                     (0x01UL << LCD_PAL129_I1_Pos)                             /*!< LCD PAL129: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL130  -------------------------------------------
+#define LCD_PAL130_R04_0_Pos                                  0                                                         /*!< LCD PAL130: R04_0 Position          */
+#define LCD_PAL130_R04_0_Msk                                  (0x1fUL << LCD_PAL130_R04_0_Pos)                          /*!< LCD PAL130: R04_0 Mask              */
+#define LCD_PAL130_G04_0_Pos                                  5                                                         /*!< LCD PAL130: G04_0 Position          */
+#define LCD_PAL130_G04_0_Msk                                  (0x1fUL << LCD_PAL130_G04_0_Pos)                          /*!< LCD PAL130: G04_0 Mask              */
+#define LCD_PAL130_B04_0_Pos                                  10                                                        /*!< LCD PAL130: B04_0 Position          */
+#define LCD_PAL130_B04_0_Msk                                  (0x1fUL << LCD_PAL130_B04_0_Pos)                          /*!< LCD PAL130: B04_0 Mask              */
+#define LCD_PAL130_I0_Pos                                     15                                                        /*!< LCD PAL130: I0 Position             */
+#define LCD_PAL130_I0_Msk                                     (0x01UL << LCD_PAL130_I0_Pos)                             /*!< LCD PAL130: I0 Mask                 */
+#define LCD_PAL130_R14_0_Pos                                  16                                                        /*!< LCD PAL130: R14_0 Position          */
+#define LCD_PAL130_R14_0_Msk                                  (0x1fUL << LCD_PAL130_R14_0_Pos)                          /*!< LCD PAL130: R14_0 Mask              */
+#define LCD_PAL130_G14_0_Pos                                  21                                                        /*!< LCD PAL130: G14_0 Position          */
+#define LCD_PAL130_G14_0_Msk                                  (0x1fUL << LCD_PAL130_G14_0_Pos)                          /*!< LCD PAL130: G14_0 Mask              */
+#define LCD_PAL130_B14_0_Pos                                  26                                                        /*!< LCD PAL130: B14_0 Position          */
+#define LCD_PAL130_B14_0_Msk                                  (0x1fUL << LCD_PAL130_B14_0_Pos)                          /*!< LCD PAL130: B14_0 Mask              */
+#define LCD_PAL130_I1_Pos                                     31                                                        /*!< LCD PAL130: I1 Position             */
+#define LCD_PAL130_I1_Msk                                     (0x01UL << LCD_PAL130_I1_Pos)                             /*!< LCD PAL130: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL131  -------------------------------------------
+#define LCD_PAL131_R04_0_Pos                                  0                                                         /*!< LCD PAL131: R04_0 Position          */
+#define LCD_PAL131_R04_0_Msk                                  (0x1fUL << LCD_PAL131_R04_0_Pos)                          /*!< LCD PAL131: R04_0 Mask              */
+#define LCD_PAL131_G04_0_Pos                                  5                                                         /*!< LCD PAL131: G04_0 Position          */
+#define LCD_PAL131_G04_0_Msk                                  (0x1fUL << LCD_PAL131_G04_0_Pos)                          /*!< LCD PAL131: G04_0 Mask              */
+#define LCD_PAL131_B04_0_Pos                                  10                                                        /*!< LCD PAL131: B04_0 Position          */
+#define LCD_PAL131_B04_0_Msk                                  (0x1fUL << LCD_PAL131_B04_0_Pos)                          /*!< LCD PAL131: B04_0 Mask              */
+#define LCD_PAL131_I0_Pos                                     15                                                        /*!< LCD PAL131: I0 Position             */
+#define LCD_PAL131_I0_Msk                                     (0x01UL << LCD_PAL131_I0_Pos)                             /*!< LCD PAL131: I0 Mask                 */
+#define LCD_PAL131_R14_0_Pos                                  16                                                        /*!< LCD PAL131: R14_0 Position          */
+#define LCD_PAL131_R14_0_Msk                                  (0x1fUL << LCD_PAL131_R14_0_Pos)                          /*!< LCD PAL131: R14_0 Mask              */
+#define LCD_PAL131_G14_0_Pos                                  21                                                        /*!< LCD PAL131: G14_0 Position          */
+#define LCD_PAL131_G14_0_Msk                                  (0x1fUL << LCD_PAL131_G14_0_Pos)                          /*!< LCD PAL131: G14_0 Mask              */
+#define LCD_PAL131_B14_0_Pos                                  26                                                        /*!< LCD PAL131: B14_0 Position          */
+#define LCD_PAL131_B14_0_Msk                                  (0x1fUL << LCD_PAL131_B14_0_Pos)                          /*!< LCD PAL131: B14_0 Mask              */
+#define LCD_PAL131_I1_Pos                                     31                                                        /*!< LCD PAL131: I1 Position             */
+#define LCD_PAL131_I1_Msk                                     (0x01UL << LCD_PAL131_I1_Pos)                             /*!< LCD PAL131: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL132  -------------------------------------------
+#define LCD_PAL132_R04_0_Pos                                  0                                                         /*!< LCD PAL132: R04_0 Position          */
+#define LCD_PAL132_R04_0_Msk                                  (0x1fUL << LCD_PAL132_R04_0_Pos)                          /*!< LCD PAL132: R04_0 Mask              */
+#define LCD_PAL132_G04_0_Pos                                  5                                                         /*!< LCD PAL132: G04_0 Position          */
+#define LCD_PAL132_G04_0_Msk                                  (0x1fUL << LCD_PAL132_G04_0_Pos)                          /*!< LCD PAL132: G04_0 Mask              */
+#define LCD_PAL132_B04_0_Pos                                  10                                                        /*!< LCD PAL132: B04_0 Position          */
+#define LCD_PAL132_B04_0_Msk                                  (0x1fUL << LCD_PAL132_B04_0_Pos)                          /*!< LCD PAL132: B04_0 Mask              */
+#define LCD_PAL132_I0_Pos                                     15                                                        /*!< LCD PAL132: I0 Position             */
+#define LCD_PAL132_I0_Msk                                     (0x01UL << LCD_PAL132_I0_Pos)                             /*!< LCD PAL132: I0 Mask                 */
+#define LCD_PAL132_R14_0_Pos                                  16                                                        /*!< LCD PAL132: R14_0 Position          */
+#define LCD_PAL132_R14_0_Msk                                  (0x1fUL << LCD_PAL132_R14_0_Pos)                          /*!< LCD PAL132: R14_0 Mask              */
+#define LCD_PAL132_G14_0_Pos                                  21                                                        /*!< LCD PAL132: G14_0 Position          */
+#define LCD_PAL132_G14_0_Msk                                  (0x1fUL << LCD_PAL132_G14_0_Pos)                          /*!< LCD PAL132: G14_0 Mask              */
+#define LCD_PAL132_B14_0_Pos                                  26                                                        /*!< LCD PAL132: B14_0 Position          */
+#define LCD_PAL132_B14_0_Msk                                  (0x1fUL << LCD_PAL132_B14_0_Pos)                          /*!< LCD PAL132: B14_0 Mask              */
+#define LCD_PAL132_I1_Pos                                     31                                                        /*!< LCD PAL132: I1 Position             */
+#define LCD_PAL132_I1_Msk                                     (0x01UL << LCD_PAL132_I1_Pos)                             /*!< LCD PAL132: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL133  -------------------------------------------
+#define LCD_PAL133_R04_0_Pos                                  0                                                         /*!< LCD PAL133: R04_0 Position          */
+#define LCD_PAL133_R04_0_Msk                                  (0x1fUL << LCD_PAL133_R04_0_Pos)                          /*!< LCD PAL133: R04_0 Mask              */
+#define LCD_PAL133_G04_0_Pos                                  5                                                         /*!< LCD PAL133: G04_0 Position          */
+#define LCD_PAL133_G04_0_Msk                                  (0x1fUL << LCD_PAL133_G04_0_Pos)                          /*!< LCD PAL133: G04_0 Mask              */
+#define LCD_PAL133_B04_0_Pos                                  10                                                        /*!< LCD PAL133: B04_0 Position          */
+#define LCD_PAL133_B04_0_Msk                                  (0x1fUL << LCD_PAL133_B04_0_Pos)                          /*!< LCD PAL133: B04_0 Mask              */
+#define LCD_PAL133_I0_Pos                                     15                                                        /*!< LCD PAL133: I0 Position             */
+#define LCD_PAL133_I0_Msk                                     (0x01UL << LCD_PAL133_I0_Pos)                             /*!< LCD PAL133: I0 Mask                 */
+#define LCD_PAL133_R14_0_Pos                                  16                                                        /*!< LCD PAL133: R14_0 Position          */
+#define LCD_PAL133_R14_0_Msk                                  (0x1fUL << LCD_PAL133_R14_0_Pos)                          /*!< LCD PAL133: R14_0 Mask              */
+#define LCD_PAL133_G14_0_Pos                                  21                                                        /*!< LCD PAL133: G14_0 Position          */
+#define LCD_PAL133_G14_0_Msk                                  (0x1fUL << LCD_PAL133_G14_0_Pos)                          /*!< LCD PAL133: G14_0 Mask              */
+#define LCD_PAL133_B14_0_Pos                                  26                                                        /*!< LCD PAL133: B14_0 Position          */
+#define LCD_PAL133_B14_0_Msk                                  (0x1fUL << LCD_PAL133_B14_0_Pos)                          /*!< LCD PAL133: B14_0 Mask              */
+#define LCD_PAL133_I1_Pos                                     31                                                        /*!< LCD PAL133: I1 Position             */
+#define LCD_PAL133_I1_Msk                                     (0x01UL << LCD_PAL133_I1_Pos)                             /*!< LCD PAL133: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL134  -------------------------------------------
+#define LCD_PAL134_R04_0_Pos                                  0                                                         /*!< LCD PAL134: R04_0 Position          */
+#define LCD_PAL134_R04_0_Msk                                  (0x1fUL << LCD_PAL134_R04_0_Pos)                          /*!< LCD PAL134: R04_0 Mask              */
+#define LCD_PAL134_G04_0_Pos                                  5                                                         /*!< LCD PAL134: G04_0 Position          */
+#define LCD_PAL134_G04_0_Msk                                  (0x1fUL << LCD_PAL134_G04_0_Pos)                          /*!< LCD PAL134: G04_0 Mask              */
+#define LCD_PAL134_B04_0_Pos                                  10                                                        /*!< LCD PAL134: B04_0 Position          */
+#define LCD_PAL134_B04_0_Msk                                  (0x1fUL << LCD_PAL134_B04_0_Pos)                          /*!< LCD PAL134: B04_0 Mask              */
+#define LCD_PAL134_I0_Pos                                     15                                                        /*!< LCD PAL134: I0 Position             */
+#define LCD_PAL134_I0_Msk                                     (0x01UL << LCD_PAL134_I0_Pos)                             /*!< LCD PAL134: I0 Mask                 */
+#define LCD_PAL134_R14_0_Pos                                  16                                                        /*!< LCD PAL134: R14_0 Position          */
+#define LCD_PAL134_R14_0_Msk                                  (0x1fUL << LCD_PAL134_R14_0_Pos)                          /*!< LCD PAL134: R14_0 Mask              */
+#define LCD_PAL134_G14_0_Pos                                  21                                                        /*!< LCD PAL134: G14_0 Position          */
+#define LCD_PAL134_G14_0_Msk                                  (0x1fUL << LCD_PAL134_G14_0_Pos)                          /*!< LCD PAL134: G14_0 Mask              */
+#define LCD_PAL134_B14_0_Pos                                  26                                                        /*!< LCD PAL134: B14_0 Position          */
+#define LCD_PAL134_B14_0_Msk                                  (0x1fUL << LCD_PAL134_B14_0_Pos)                          /*!< LCD PAL134: B14_0 Mask              */
+#define LCD_PAL134_I1_Pos                                     31                                                        /*!< LCD PAL134: I1 Position             */
+#define LCD_PAL134_I1_Msk                                     (0x01UL << LCD_PAL134_I1_Pos)                             /*!< LCD PAL134: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL135  -------------------------------------------
+#define LCD_PAL135_R04_0_Pos                                  0                                                         /*!< LCD PAL135: R04_0 Position          */
+#define LCD_PAL135_R04_0_Msk                                  (0x1fUL << LCD_PAL135_R04_0_Pos)                          /*!< LCD PAL135: R04_0 Mask              */
+#define LCD_PAL135_G04_0_Pos                                  5                                                         /*!< LCD PAL135: G04_0 Position          */
+#define LCD_PAL135_G04_0_Msk                                  (0x1fUL << LCD_PAL135_G04_0_Pos)                          /*!< LCD PAL135: G04_0 Mask              */
+#define LCD_PAL135_B04_0_Pos                                  10                                                        /*!< LCD PAL135: B04_0 Position          */
+#define LCD_PAL135_B04_0_Msk                                  (0x1fUL << LCD_PAL135_B04_0_Pos)                          /*!< LCD PAL135: B04_0 Mask              */
+#define LCD_PAL135_I0_Pos                                     15                                                        /*!< LCD PAL135: I0 Position             */
+#define LCD_PAL135_I0_Msk                                     (0x01UL << LCD_PAL135_I0_Pos)                             /*!< LCD PAL135: I0 Mask                 */
+#define LCD_PAL135_R14_0_Pos                                  16                                                        /*!< LCD PAL135: R14_0 Position          */
+#define LCD_PAL135_R14_0_Msk                                  (0x1fUL << LCD_PAL135_R14_0_Pos)                          /*!< LCD PAL135: R14_0 Mask              */
+#define LCD_PAL135_G14_0_Pos                                  21                                                        /*!< LCD PAL135: G14_0 Position          */
+#define LCD_PAL135_G14_0_Msk                                  (0x1fUL << LCD_PAL135_G14_0_Pos)                          /*!< LCD PAL135: G14_0 Mask              */
+#define LCD_PAL135_B14_0_Pos                                  26                                                        /*!< LCD PAL135: B14_0 Position          */
+#define LCD_PAL135_B14_0_Msk                                  (0x1fUL << LCD_PAL135_B14_0_Pos)                          /*!< LCD PAL135: B14_0 Mask              */
+#define LCD_PAL135_I1_Pos                                     31                                                        /*!< LCD PAL135: I1 Position             */
+#define LCD_PAL135_I1_Msk                                     (0x01UL << LCD_PAL135_I1_Pos)                             /*!< LCD PAL135: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL136  -------------------------------------------
+#define LCD_PAL136_R04_0_Pos                                  0                                                         /*!< LCD PAL136: R04_0 Position          */
+#define LCD_PAL136_R04_0_Msk                                  (0x1fUL << LCD_PAL136_R04_0_Pos)                          /*!< LCD PAL136: R04_0 Mask              */
+#define LCD_PAL136_G04_0_Pos                                  5                                                         /*!< LCD PAL136: G04_0 Position          */
+#define LCD_PAL136_G04_0_Msk                                  (0x1fUL << LCD_PAL136_G04_0_Pos)                          /*!< LCD PAL136: G04_0 Mask              */
+#define LCD_PAL136_B04_0_Pos                                  10                                                        /*!< LCD PAL136: B04_0 Position          */
+#define LCD_PAL136_B04_0_Msk                                  (0x1fUL << LCD_PAL136_B04_0_Pos)                          /*!< LCD PAL136: B04_0 Mask              */
+#define LCD_PAL136_I0_Pos                                     15                                                        /*!< LCD PAL136: I0 Position             */
+#define LCD_PAL136_I0_Msk                                     (0x01UL << LCD_PAL136_I0_Pos)                             /*!< LCD PAL136: I0 Mask                 */
+#define LCD_PAL136_R14_0_Pos                                  16                                                        /*!< LCD PAL136: R14_0 Position          */
+#define LCD_PAL136_R14_0_Msk                                  (0x1fUL << LCD_PAL136_R14_0_Pos)                          /*!< LCD PAL136: R14_0 Mask              */
+#define LCD_PAL136_G14_0_Pos                                  21                                                        /*!< LCD PAL136: G14_0 Position          */
+#define LCD_PAL136_G14_0_Msk                                  (0x1fUL << LCD_PAL136_G14_0_Pos)                          /*!< LCD PAL136: G14_0 Mask              */
+#define LCD_PAL136_B14_0_Pos                                  26                                                        /*!< LCD PAL136: B14_0 Position          */
+#define LCD_PAL136_B14_0_Msk                                  (0x1fUL << LCD_PAL136_B14_0_Pos)                          /*!< LCD PAL136: B14_0 Mask              */
+#define LCD_PAL136_I1_Pos                                     31                                                        /*!< LCD PAL136: I1 Position             */
+#define LCD_PAL136_I1_Msk                                     (0x01UL << LCD_PAL136_I1_Pos)                             /*!< LCD PAL136: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL137  -------------------------------------------
+#define LCD_PAL137_R04_0_Pos                                  0                                                         /*!< LCD PAL137: R04_0 Position          */
+#define LCD_PAL137_R04_0_Msk                                  (0x1fUL << LCD_PAL137_R04_0_Pos)                          /*!< LCD PAL137: R04_0 Mask              */
+#define LCD_PAL137_G04_0_Pos                                  5                                                         /*!< LCD PAL137: G04_0 Position          */
+#define LCD_PAL137_G04_0_Msk                                  (0x1fUL << LCD_PAL137_G04_0_Pos)                          /*!< LCD PAL137: G04_0 Mask              */
+#define LCD_PAL137_B04_0_Pos                                  10                                                        /*!< LCD PAL137: B04_0 Position          */
+#define LCD_PAL137_B04_0_Msk                                  (0x1fUL << LCD_PAL137_B04_0_Pos)                          /*!< LCD PAL137: B04_0 Mask              */
+#define LCD_PAL137_I0_Pos                                     15                                                        /*!< LCD PAL137: I0 Position             */
+#define LCD_PAL137_I0_Msk                                     (0x01UL << LCD_PAL137_I0_Pos)                             /*!< LCD PAL137: I0 Mask                 */
+#define LCD_PAL137_R14_0_Pos                                  16                                                        /*!< LCD PAL137: R14_0 Position          */
+#define LCD_PAL137_R14_0_Msk                                  (0x1fUL << LCD_PAL137_R14_0_Pos)                          /*!< LCD PAL137: R14_0 Mask              */
+#define LCD_PAL137_G14_0_Pos                                  21                                                        /*!< LCD PAL137: G14_0 Position          */
+#define LCD_PAL137_G14_0_Msk                                  (0x1fUL << LCD_PAL137_G14_0_Pos)                          /*!< LCD PAL137: G14_0 Mask              */
+#define LCD_PAL137_B14_0_Pos                                  26                                                        /*!< LCD PAL137: B14_0 Position          */
+#define LCD_PAL137_B14_0_Msk                                  (0x1fUL << LCD_PAL137_B14_0_Pos)                          /*!< LCD PAL137: B14_0 Mask              */
+#define LCD_PAL137_I1_Pos                                     31                                                        /*!< LCD PAL137: I1 Position             */
+#define LCD_PAL137_I1_Msk                                     (0x01UL << LCD_PAL137_I1_Pos)                             /*!< LCD PAL137: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL138  -------------------------------------------
+#define LCD_PAL138_R04_0_Pos                                  0                                                         /*!< LCD PAL138: R04_0 Position          */
+#define LCD_PAL138_R04_0_Msk                                  (0x1fUL << LCD_PAL138_R04_0_Pos)                          /*!< LCD PAL138: R04_0 Mask              */
+#define LCD_PAL138_G04_0_Pos                                  5                                                         /*!< LCD PAL138: G04_0 Position          */
+#define LCD_PAL138_G04_0_Msk                                  (0x1fUL << LCD_PAL138_G04_0_Pos)                          /*!< LCD PAL138: G04_0 Mask              */
+#define LCD_PAL138_B04_0_Pos                                  10                                                        /*!< LCD PAL138: B04_0 Position          */
+#define LCD_PAL138_B04_0_Msk                                  (0x1fUL << LCD_PAL138_B04_0_Pos)                          /*!< LCD PAL138: B04_0 Mask              */
+#define LCD_PAL138_I0_Pos                                     15                                                        /*!< LCD PAL138: I0 Position             */
+#define LCD_PAL138_I0_Msk                                     (0x01UL << LCD_PAL138_I0_Pos)                             /*!< LCD PAL138: I0 Mask                 */
+#define LCD_PAL138_R14_0_Pos                                  16                                                        /*!< LCD PAL138: R14_0 Position          */
+#define LCD_PAL138_R14_0_Msk                                  (0x1fUL << LCD_PAL138_R14_0_Pos)                          /*!< LCD PAL138: R14_0 Mask              */
+#define LCD_PAL138_G14_0_Pos                                  21                                                        /*!< LCD PAL138: G14_0 Position          */
+#define LCD_PAL138_G14_0_Msk                                  (0x1fUL << LCD_PAL138_G14_0_Pos)                          /*!< LCD PAL138: G14_0 Mask              */
+#define LCD_PAL138_B14_0_Pos                                  26                                                        /*!< LCD PAL138: B14_0 Position          */
+#define LCD_PAL138_B14_0_Msk                                  (0x1fUL << LCD_PAL138_B14_0_Pos)                          /*!< LCD PAL138: B14_0 Mask              */
+#define LCD_PAL138_I1_Pos                                     31                                                        /*!< LCD PAL138: I1 Position             */
+#define LCD_PAL138_I1_Msk                                     (0x01UL << LCD_PAL138_I1_Pos)                             /*!< LCD PAL138: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL139  -------------------------------------------
+#define LCD_PAL139_R04_0_Pos                                  0                                                         /*!< LCD PAL139: R04_0 Position          */
+#define LCD_PAL139_R04_0_Msk                                  (0x1fUL << LCD_PAL139_R04_0_Pos)                          /*!< LCD PAL139: R04_0 Mask              */
+#define LCD_PAL139_G04_0_Pos                                  5                                                         /*!< LCD PAL139: G04_0 Position          */
+#define LCD_PAL139_G04_0_Msk                                  (0x1fUL << LCD_PAL139_G04_0_Pos)                          /*!< LCD PAL139: G04_0 Mask              */
+#define LCD_PAL139_B04_0_Pos                                  10                                                        /*!< LCD PAL139: B04_0 Position          */
+#define LCD_PAL139_B04_0_Msk                                  (0x1fUL << LCD_PAL139_B04_0_Pos)                          /*!< LCD PAL139: B04_0 Mask              */
+#define LCD_PAL139_I0_Pos                                     15                                                        /*!< LCD PAL139: I0 Position             */
+#define LCD_PAL139_I0_Msk                                     (0x01UL << LCD_PAL139_I0_Pos)                             /*!< LCD PAL139: I0 Mask                 */
+#define LCD_PAL139_R14_0_Pos                                  16                                                        /*!< LCD PAL139: R14_0 Position          */
+#define LCD_PAL139_R14_0_Msk                                  (0x1fUL << LCD_PAL139_R14_0_Pos)                          /*!< LCD PAL139: R14_0 Mask              */
+#define LCD_PAL139_G14_0_Pos                                  21                                                        /*!< LCD PAL139: G14_0 Position          */
+#define LCD_PAL139_G14_0_Msk                                  (0x1fUL << LCD_PAL139_G14_0_Pos)                          /*!< LCD PAL139: G14_0 Mask              */
+#define LCD_PAL139_B14_0_Pos                                  26                                                        /*!< LCD PAL139: B14_0 Position          */
+#define LCD_PAL139_B14_0_Msk                                  (0x1fUL << LCD_PAL139_B14_0_Pos)                          /*!< LCD PAL139: B14_0 Mask              */
+#define LCD_PAL139_I1_Pos                                     31                                                        /*!< LCD PAL139: I1 Position             */
+#define LCD_PAL139_I1_Msk                                     (0x01UL << LCD_PAL139_I1_Pos)                             /*!< LCD PAL139: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL140  -------------------------------------------
+#define LCD_PAL140_R04_0_Pos                                  0                                                         /*!< LCD PAL140: R04_0 Position          */
+#define LCD_PAL140_R04_0_Msk                                  (0x1fUL << LCD_PAL140_R04_0_Pos)                          /*!< LCD PAL140: R04_0 Mask              */
+#define LCD_PAL140_G04_0_Pos                                  5                                                         /*!< LCD PAL140: G04_0 Position          */
+#define LCD_PAL140_G04_0_Msk                                  (0x1fUL << LCD_PAL140_G04_0_Pos)                          /*!< LCD PAL140: G04_0 Mask              */
+#define LCD_PAL140_B04_0_Pos                                  10                                                        /*!< LCD PAL140: B04_0 Position          */
+#define LCD_PAL140_B04_0_Msk                                  (0x1fUL << LCD_PAL140_B04_0_Pos)                          /*!< LCD PAL140: B04_0 Mask              */
+#define LCD_PAL140_I0_Pos                                     15                                                        /*!< LCD PAL140: I0 Position             */
+#define LCD_PAL140_I0_Msk                                     (0x01UL << LCD_PAL140_I0_Pos)                             /*!< LCD PAL140: I0 Mask                 */
+#define LCD_PAL140_R14_0_Pos                                  16                                                        /*!< LCD PAL140: R14_0 Position          */
+#define LCD_PAL140_R14_0_Msk                                  (0x1fUL << LCD_PAL140_R14_0_Pos)                          /*!< LCD PAL140: R14_0 Mask              */
+#define LCD_PAL140_G14_0_Pos                                  21                                                        /*!< LCD PAL140: G14_0 Position          */
+#define LCD_PAL140_G14_0_Msk                                  (0x1fUL << LCD_PAL140_G14_0_Pos)                          /*!< LCD PAL140: G14_0 Mask              */
+#define LCD_PAL140_B14_0_Pos                                  26                                                        /*!< LCD PAL140: B14_0 Position          */
+#define LCD_PAL140_B14_0_Msk                                  (0x1fUL << LCD_PAL140_B14_0_Pos)                          /*!< LCD PAL140: B14_0 Mask              */
+#define LCD_PAL140_I1_Pos                                     31                                                        /*!< LCD PAL140: I1 Position             */
+#define LCD_PAL140_I1_Msk                                     (0x01UL << LCD_PAL140_I1_Pos)                             /*!< LCD PAL140: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL141  -------------------------------------------
+#define LCD_PAL141_R04_0_Pos                                  0                                                         /*!< LCD PAL141: R04_0 Position          */
+#define LCD_PAL141_R04_0_Msk                                  (0x1fUL << LCD_PAL141_R04_0_Pos)                          /*!< LCD PAL141: R04_0 Mask              */
+#define LCD_PAL141_G04_0_Pos                                  5                                                         /*!< LCD PAL141: G04_0 Position          */
+#define LCD_PAL141_G04_0_Msk                                  (0x1fUL << LCD_PAL141_G04_0_Pos)                          /*!< LCD PAL141: G04_0 Mask              */
+#define LCD_PAL141_B04_0_Pos                                  10                                                        /*!< LCD PAL141: B04_0 Position          */
+#define LCD_PAL141_B04_0_Msk                                  (0x1fUL << LCD_PAL141_B04_0_Pos)                          /*!< LCD PAL141: B04_0 Mask              */
+#define LCD_PAL141_I0_Pos                                     15                                                        /*!< LCD PAL141: I0 Position             */
+#define LCD_PAL141_I0_Msk                                     (0x01UL << LCD_PAL141_I0_Pos)                             /*!< LCD PAL141: I0 Mask                 */
+#define LCD_PAL141_R14_0_Pos                                  16                                                        /*!< LCD PAL141: R14_0 Position          */
+#define LCD_PAL141_R14_0_Msk                                  (0x1fUL << LCD_PAL141_R14_0_Pos)                          /*!< LCD PAL141: R14_0 Mask              */
+#define LCD_PAL141_G14_0_Pos                                  21                                                        /*!< LCD PAL141: G14_0 Position          */
+#define LCD_PAL141_G14_0_Msk                                  (0x1fUL << LCD_PAL141_G14_0_Pos)                          /*!< LCD PAL141: G14_0 Mask              */
+#define LCD_PAL141_B14_0_Pos                                  26                                                        /*!< LCD PAL141: B14_0 Position          */
+#define LCD_PAL141_B14_0_Msk                                  (0x1fUL << LCD_PAL141_B14_0_Pos)                          /*!< LCD PAL141: B14_0 Mask              */
+#define LCD_PAL141_I1_Pos                                     31                                                        /*!< LCD PAL141: I1 Position             */
+#define LCD_PAL141_I1_Msk                                     (0x01UL << LCD_PAL141_I1_Pos)                             /*!< LCD PAL141: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL142  -------------------------------------------
+#define LCD_PAL142_R04_0_Pos                                  0                                                         /*!< LCD PAL142: R04_0 Position          */
+#define LCD_PAL142_R04_0_Msk                                  (0x1fUL << LCD_PAL142_R04_0_Pos)                          /*!< LCD PAL142: R04_0 Mask              */
+#define LCD_PAL142_G04_0_Pos                                  5                                                         /*!< LCD PAL142: G04_0 Position          */
+#define LCD_PAL142_G04_0_Msk                                  (0x1fUL << LCD_PAL142_G04_0_Pos)                          /*!< LCD PAL142: G04_0 Mask              */
+#define LCD_PAL142_B04_0_Pos                                  10                                                        /*!< LCD PAL142: B04_0 Position          */
+#define LCD_PAL142_B04_0_Msk                                  (0x1fUL << LCD_PAL142_B04_0_Pos)                          /*!< LCD PAL142: B04_0 Mask              */
+#define LCD_PAL142_I0_Pos                                     15                                                        /*!< LCD PAL142: I0 Position             */
+#define LCD_PAL142_I0_Msk                                     (0x01UL << LCD_PAL142_I0_Pos)                             /*!< LCD PAL142: I0 Mask                 */
+#define LCD_PAL142_R14_0_Pos                                  16                                                        /*!< LCD PAL142: R14_0 Position          */
+#define LCD_PAL142_R14_0_Msk                                  (0x1fUL << LCD_PAL142_R14_0_Pos)                          /*!< LCD PAL142: R14_0 Mask              */
+#define LCD_PAL142_G14_0_Pos                                  21                                                        /*!< LCD PAL142: G14_0 Position          */
+#define LCD_PAL142_G14_0_Msk                                  (0x1fUL << LCD_PAL142_G14_0_Pos)                          /*!< LCD PAL142: G14_0 Mask              */
+#define LCD_PAL142_B14_0_Pos                                  26                                                        /*!< LCD PAL142: B14_0 Position          */
+#define LCD_PAL142_B14_0_Msk                                  (0x1fUL << LCD_PAL142_B14_0_Pos)                          /*!< LCD PAL142: B14_0 Mask              */
+#define LCD_PAL142_I1_Pos                                     31                                                        /*!< LCD PAL142: I1 Position             */
+#define LCD_PAL142_I1_Msk                                     (0x01UL << LCD_PAL142_I1_Pos)                             /*!< LCD PAL142: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL143  -------------------------------------------
+#define LCD_PAL143_R04_0_Pos                                  0                                                         /*!< LCD PAL143: R04_0 Position          */
+#define LCD_PAL143_R04_0_Msk                                  (0x1fUL << LCD_PAL143_R04_0_Pos)                          /*!< LCD PAL143: R04_0 Mask              */
+#define LCD_PAL143_G04_0_Pos                                  5                                                         /*!< LCD PAL143: G04_0 Position          */
+#define LCD_PAL143_G04_0_Msk                                  (0x1fUL << LCD_PAL143_G04_0_Pos)                          /*!< LCD PAL143: G04_0 Mask              */
+#define LCD_PAL143_B04_0_Pos                                  10                                                        /*!< LCD PAL143: B04_0 Position          */
+#define LCD_PAL143_B04_0_Msk                                  (0x1fUL << LCD_PAL143_B04_0_Pos)                          /*!< LCD PAL143: B04_0 Mask              */
+#define LCD_PAL143_I0_Pos                                     15                                                        /*!< LCD PAL143: I0 Position             */
+#define LCD_PAL143_I0_Msk                                     (0x01UL << LCD_PAL143_I0_Pos)                             /*!< LCD PAL143: I0 Mask                 */
+#define LCD_PAL143_R14_0_Pos                                  16                                                        /*!< LCD PAL143: R14_0 Position          */
+#define LCD_PAL143_R14_0_Msk                                  (0x1fUL << LCD_PAL143_R14_0_Pos)                          /*!< LCD PAL143: R14_0 Mask              */
+#define LCD_PAL143_G14_0_Pos                                  21                                                        /*!< LCD PAL143: G14_0 Position          */
+#define LCD_PAL143_G14_0_Msk                                  (0x1fUL << LCD_PAL143_G14_0_Pos)                          /*!< LCD PAL143: G14_0 Mask              */
+#define LCD_PAL143_B14_0_Pos                                  26                                                        /*!< LCD PAL143: B14_0 Position          */
+#define LCD_PAL143_B14_0_Msk                                  (0x1fUL << LCD_PAL143_B14_0_Pos)                          /*!< LCD PAL143: B14_0 Mask              */
+#define LCD_PAL143_I1_Pos                                     31                                                        /*!< LCD PAL143: I1 Position             */
+#define LCD_PAL143_I1_Msk                                     (0x01UL << LCD_PAL143_I1_Pos)                             /*!< LCD PAL143: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL144  -------------------------------------------
+#define LCD_PAL144_R04_0_Pos                                  0                                                         /*!< LCD PAL144: R04_0 Position          */
+#define LCD_PAL144_R04_0_Msk                                  (0x1fUL << LCD_PAL144_R04_0_Pos)                          /*!< LCD PAL144: R04_0 Mask              */
+#define LCD_PAL144_G04_0_Pos                                  5                                                         /*!< LCD PAL144: G04_0 Position          */
+#define LCD_PAL144_G04_0_Msk                                  (0x1fUL << LCD_PAL144_G04_0_Pos)                          /*!< LCD PAL144: G04_0 Mask              */
+#define LCD_PAL144_B04_0_Pos                                  10                                                        /*!< LCD PAL144: B04_0 Position          */
+#define LCD_PAL144_B04_0_Msk                                  (0x1fUL << LCD_PAL144_B04_0_Pos)                          /*!< LCD PAL144: B04_0 Mask              */
+#define LCD_PAL144_I0_Pos                                     15                                                        /*!< LCD PAL144: I0 Position             */
+#define LCD_PAL144_I0_Msk                                     (0x01UL << LCD_PAL144_I0_Pos)                             /*!< LCD PAL144: I0 Mask                 */
+#define LCD_PAL144_R14_0_Pos                                  16                                                        /*!< LCD PAL144: R14_0 Position          */
+#define LCD_PAL144_R14_0_Msk                                  (0x1fUL << LCD_PAL144_R14_0_Pos)                          /*!< LCD PAL144: R14_0 Mask              */
+#define LCD_PAL144_G14_0_Pos                                  21                                                        /*!< LCD PAL144: G14_0 Position          */
+#define LCD_PAL144_G14_0_Msk                                  (0x1fUL << LCD_PAL144_G14_0_Pos)                          /*!< LCD PAL144: G14_0 Mask              */
+#define LCD_PAL144_B14_0_Pos                                  26                                                        /*!< LCD PAL144: B14_0 Position          */
+#define LCD_PAL144_B14_0_Msk                                  (0x1fUL << LCD_PAL144_B14_0_Pos)                          /*!< LCD PAL144: B14_0 Mask              */
+#define LCD_PAL144_I1_Pos                                     31                                                        /*!< LCD PAL144: I1 Position             */
+#define LCD_PAL144_I1_Msk                                     (0x01UL << LCD_PAL144_I1_Pos)                             /*!< LCD PAL144: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL145  -------------------------------------------
+#define LCD_PAL145_R04_0_Pos                                  0                                                         /*!< LCD PAL145: R04_0 Position          */
+#define LCD_PAL145_R04_0_Msk                                  (0x1fUL << LCD_PAL145_R04_0_Pos)                          /*!< LCD PAL145: R04_0 Mask              */
+#define LCD_PAL145_G04_0_Pos                                  5                                                         /*!< LCD PAL145: G04_0 Position          */
+#define LCD_PAL145_G04_0_Msk                                  (0x1fUL << LCD_PAL145_G04_0_Pos)                          /*!< LCD PAL145: G04_0 Mask              */
+#define LCD_PAL145_B04_0_Pos                                  10                                                        /*!< LCD PAL145: B04_0 Position          */
+#define LCD_PAL145_B04_0_Msk                                  (0x1fUL << LCD_PAL145_B04_0_Pos)                          /*!< LCD PAL145: B04_0 Mask              */
+#define LCD_PAL145_I0_Pos                                     15                                                        /*!< LCD PAL145: I0 Position             */
+#define LCD_PAL145_I0_Msk                                     (0x01UL << LCD_PAL145_I0_Pos)                             /*!< LCD PAL145: I0 Mask                 */
+#define LCD_PAL145_R14_0_Pos                                  16                                                        /*!< LCD PAL145: R14_0 Position          */
+#define LCD_PAL145_R14_0_Msk                                  (0x1fUL << LCD_PAL145_R14_0_Pos)                          /*!< LCD PAL145: R14_0 Mask              */
+#define LCD_PAL145_G14_0_Pos                                  21                                                        /*!< LCD PAL145: G14_0 Position          */
+#define LCD_PAL145_G14_0_Msk                                  (0x1fUL << LCD_PAL145_G14_0_Pos)                          /*!< LCD PAL145: G14_0 Mask              */
+#define LCD_PAL145_B14_0_Pos                                  26                                                        /*!< LCD PAL145: B14_0 Position          */
+#define LCD_PAL145_B14_0_Msk                                  (0x1fUL << LCD_PAL145_B14_0_Pos)                          /*!< LCD PAL145: B14_0 Mask              */
+#define LCD_PAL145_I1_Pos                                     31                                                        /*!< LCD PAL145: I1 Position             */
+#define LCD_PAL145_I1_Msk                                     (0x01UL << LCD_PAL145_I1_Pos)                             /*!< LCD PAL145: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL146  -------------------------------------------
+#define LCD_PAL146_R04_0_Pos                                  0                                                         /*!< LCD PAL146: R04_0 Position          */
+#define LCD_PAL146_R04_0_Msk                                  (0x1fUL << LCD_PAL146_R04_0_Pos)                          /*!< LCD PAL146: R04_0 Mask              */
+#define LCD_PAL146_G04_0_Pos                                  5                                                         /*!< LCD PAL146: G04_0 Position          */
+#define LCD_PAL146_G04_0_Msk                                  (0x1fUL << LCD_PAL146_G04_0_Pos)                          /*!< LCD PAL146: G04_0 Mask              */
+#define LCD_PAL146_B04_0_Pos                                  10                                                        /*!< LCD PAL146: B04_0 Position          */
+#define LCD_PAL146_B04_0_Msk                                  (0x1fUL << LCD_PAL146_B04_0_Pos)                          /*!< LCD PAL146: B04_0 Mask              */
+#define LCD_PAL146_I0_Pos                                     15                                                        /*!< LCD PAL146: I0 Position             */
+#define LCD_PAL146_I0_Msk                                     (0x01UL << LCD_PAL146_I0_Pos)                             /*!< LCD PAL146: I0 Mask                 */
+#define LCD_PAL146_R14_0_Pos                                  16                                                        /*!< LCD PAL146: R14_0 Position          */
+#define LCD_PAL146_R14_0_Msk                                  (0x1fUL << LCD_PAL146_R14_0_Pos)                          /*!< LCD PAL146: R14_0 Mask              */
+#define LCD_PAL146_G14_0_Pos                                  21                                                        /*!< LCD PAL146: G14_0 Position          */
+#define LCD_PAL146_G14_0_Msk                                  (0x1fUL << LCD_PAL146_G14_0_Pos)                          /*!< LCD PAL146: G14_0 Mask              */
+#define LCD_PAL146_B14_0_Pos                                  26                                                        /*!< LCD PAL146: B14_0 Position          */
+#define LCD_PAL146_B14_0_Msk                                  (0x1fUL << LCD_PAL146_B14_0_Pos)                          /*!< LCD PAL146: B14_0 Mask              */
+#define LCD_PAL146_I1_Pos                                     31                                                        /*!< LCD PAL146: I1 Position             */
+#define LCD_PAL146_I1_Msk                                     (0x01UL << LCD_PAL146_I1_Pos)                             /*!< LCD PAL146: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL147  -------------------------------------------
+#define LCD_PAL147_R04_0_Pos                                  0                                                         /*!< LCD PAL147: R04_0 Position          */
+#define LCD_PAL147_R04_0_Msk                                  (0x1fUL << LCD_PAL147_R04_0_Pos)                          /*!< LCD PAL147: R04_0 Mask              */
+#define LCD_PAL147_G04_0_Pos                                  5                                                         /*!< LCD PAL147: G04_0 Position          */
+#define LCD_PAL147_G04_0_Msk                                  (0x1fUL << LCD_PAL147_G04_0_Pos)                          /*!< LCD PAL147: G04_0 Mask              */
+#define LCD_PAL147_B04_0_Pos                                  10                                                        /*!< LCD PAL147: B04_0 Position          */
+#define LCD_PAL147_B04_0_Msk                                  (0x1fUL << LCD_PAL147_B04_0_Pos)                          /*!< LCD PAL147: B04_0 Mask              */
+#define LCD_PAL147_I0_Pos                                     15                                                        /*!< LCD PAL147: I0 Position             */
+#define LCD_PAL147_I0_Msk                                     (0x01UL << LCD_PAL147_I0_Pos)                             /*!< LCD PAL147: I0 Mask                 */
+#define LCD_PAL147_R14_0_Pos                                  16                                                        /*!< LCD PAL147: R14_0 Position          */
+#define LCD_PAL147_R14_0_Msk                                  (0x1fUL << LCD_PAL147_R14_0_Pos)                          /*!< LCD PAL147: R14_0 Mask              */
+#define LCD_PAL147_G14_0_Pos                                  21                                                        /*!< LCD PAL147: G14_0 Position          */
+#define LCD_PAL147_G14_0_Msk                                  (0x1fUL << LCD_PAL147_G14_0_Pos)                          /*!< LCD PAL147: G14_0 Mask              */
+#define LCD_PAL147_B14_0_Pos                                  26                                                        /*!< LCD PAL147: B14_0 Position          */
+#define LCD_PAL147_B14_0_Msk                                  (0x1fUL << LCD_PAL147_B14_0_Pos)                          /*!< LCD PAL147: B14_0 Mask              */
+#define LCD_PAL147_I1_Pos                                     31                                                        /*!< LCD PAL147: I1 Position             */
+#define LCD_PAL147_I1_Msk                                     (0x01UL << LCD_PAL147_I1_Pos)                             /*!< LCD PAL147: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL148  -------------------------------------------
+#define LCD_PAL148_R04_0_Pos                                  0                                                         /*!< LCD PAL148: R04_0 Position          */
+#define LCD_PAL148_R04_0_Msk                                  (0x1fUL << LCD_PAL148_R04_0_Pos)                          /*!< LCD PAL148: R04_0 Mask              */
+#define LCD_PAL148_G04_0_Pos                                  5                                                         /*!< LCD PAL148: G04_0 Position          */
+#define LCD_PAL148_G04_0_Msk                                  (0x1fUL << LCD_PAL148_G04_0_Pos)                          /*!< LCD PAL148: G04_0 Mask              */
+#define LCD_PAL148_B04_0_Pos                                  10                                                        /*!< LCD PAL148: B04_0 Position          */
+#define LCD_PAL148_B04_0_Msk                                  (0x1fUL << LCD_PAL148_B04_0_Pos)                          /*!< LCD PAL148: B04_0 Mask              */
+#define LCD_PAL148_I0_Pos                                     15                                                        /*!< LCD PAL148: I0 Position             */
+#define LCD_PAL148_I0_Msk                                     (0x01UL << LCD_PAL148_I0_Pos)                             /*!< LCD PAL148: I0 Mask                 */
+#define LCD_PAL148_R14_0_Pos                                  16                                                        /*!< LCD PAL148: R14_0 Position          */
+#define LCD_PAL148_R14_0_Msk                                  (0x1fUL << LCD_PAL148_R14_0_Pos)                          /*!< LCD PAL148: R14_0 Mask              */
+#define LCD_PAL148_G14_0_Pos                                  21                                                        /*!< LCD PAL148: G14_0 Position          */
+#define LCD_PAL148_G14_0_Msk                                  (0x1fUL << LCD_PAL148_G14_0_Pos)                          /*!< LCD PAL148: G14_0 Mask              */
+#define LCD_PAL148_B14_0_Pos                                  26                                                        /*!< LCD PAL148: B14_0 Position          */
+#define LCD_PAL148_B14_0_Msk                                  (0x1fUL << LCD_PAL148_B14_0_Pos)                          /*!< LCD PAL148: B14_0 Mask              */
+#define LCD_PAL148_I1_Pos                                     31                                                        /*!< LCD PAL148: I1 Position             */
+#define LCD_PAL148_I1_Msk                                     (0x01UL << LCD_PAL148_I1_Pos)                             /*!< LCD PAL148: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL149  -------------------------------------------
+#define LCD_PAL149_R04_0_Pos                                  0                                                         /*!< LCD PAL149: R04_0 Position          */
+#define LCD_PAL149_R04_0_Msk                                  (0x1fUL << LCD_PAL149_R04_0_Pos)                          /*!< LCD PAL149: R04_0 Mask              */
+#define LCD_PAL149_G04_0_Pos                                  5                                                         /*!< LCD PAL149: G04_0 Position          */
+#define LCD_PAL149_G04_0_Msk                                  (0x1fUL << LCD_PAL149_G04_0_Pos)                          /*!< LCD PAL149: G04_0 Mask              */
+#define LCD_PAL149_B04_0_Pos                                  10                                                        /*!< LCD PAL149: B04_0 Position          */
+#define LCD_PAL149_B04_0_Msk                                  (0x1fUL << LCD_PAL149_B04_0_Pos)                          /*!< LCD PAL149: B04_0 Mask              */
+#define LCD_PAL149_I0_Pos                                     15                                                        /*!< LCD PAL149: I0 Position             */
+#define LCD_PAL149_I0_Msk                                     (0x01UL << LCD_PAL149_I0_Pos)                             /*!< LCD PAL149: I0 Mask                 */
+#define LCD_PAL149_R14_0_Pos                                  16                                                        /*!< LCD PAL149: R14_0 Position          */
+#define LCD_PAL149_R14_0_Msk                                  (0x1fUL << LCD_PAL149_R14_0_Pos)                          /*!< LCD PAL149: R14_0 Mask              */
+#define LCD_PAL149_G14_0_Pos                                  21                                                        /*!< LCD PAL149: G14_0 Position          */
+#define LCD_PAL149_G14_0_Msk                                  (0x1fUL << LCD_PAL149_G14_0_Pos)                          /*!< LCD PAL149: G14_0 Mask              */
+#define LCD_PAL149_B14_0_Pos                                  26                                                        /*!< LCD PAL149: B14_0 Position          */
+#define LCD_PAL149_B14_0_Msk                                  (0x1fUL << LCD_PAL149_B14_0_Pos)                          /*!< LCD PAL149: B14_0 Mask              */
+#define LCD_PAL149_I1_Pos                                     31                                                        /*!< LCD PAL149: I1 Position             */
+#define LCD_PAL149_I1_Msk                                     (0x01UL << LCD_PAL149_I1_Pos)                             /*!< LCD PAL149: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL150  -------------------------------------------
+#define LCD_PAL150_R04_0_Pos                                  0                                                         /*!< LCD PAL150: R04_0 Position          */
+#define LCD_PAL150_R04_0_Msk                                  (0x1fUL << LCD_PAL150_R04_0_Pos)                          /*!< LCD PAL150: R04_0 Mask              */
+#define LCD_PAL150_G04_0_Pos                                  5                                                         /*!< LCD PAL150: G04_0 Position          */
+#define LCD_PAL150_G04_0_Msk                                  (0x1fUL << LCD_PAL150_G04_0_Pos)                          /*!< LCD PAL150: G04_0 Mask              */
+#define LCD_PAL150_B04_0_Pos                                  10                                                        /*!< LCD PAL150: B04_0 Position          */
+#define LCD_PAL150_B04_0_Msk                                  (0x1fUL << LCD_PAL150_B04_0_Pos)                          /*!< LCD PAL150: B04_0 Mask              */
+#define LCD_PAL150_I0_Pos                                     15                                                        /*!< LCD PAL150: I0 Position             */
+#define LCD_PAL150_I0_Msk                                     (0x01UL << LCD_PAL150_I0_Pos)                             /*!< LCD PAL150: I0 Mask                 */
+#define LCD_PAL150_R14_0_Pos                                  16                                                        /*!< LCD PAL150: R14_0 Position          */
+#define LCD_PAL150_R14_0_Msk                                  (0x1fUL << LCD_PAL150_R14_0_Pos)                          /*!< LCD PAL150: R14_0 Mask              */
+#define LCD_PAL150_G14_0_Pos                                  21                                                        /*!< LCD PAL150: G14_0 Position          */
+#define LCD_PAL150_G14_0_Msk                                  (0x1fUL << LCD_PAL150_G14_0_Pos)                          /*!< LCD PAL150: G14_0 Mask              */
+#define LCD_PAL150_B14_0_Pos                                  26                                                        /*!< LCD PAL150: B14_0 Position          */
+#define LCD_PAL150_B14_0_Msk                                  (0x1fUL << LCD_PAL150_B14_0_Pos)                          /*!< LCD PAL150: B14_0 Mask              */
+#define LCD_PAL150_I1_Pos                                     31                                                        /*!< LCD PAL150: I1 Position             */
+#define LCD_PAL150_I1_Msk                                     (0x01UL << LCD_PAL150_I1_Pos)                             /*!< LCD PAL150: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL151  -------------------------------------------
+#define LCD_PAL151_R04_0_Pos                                  0                                                         /*!< LCD PAL151: R04_0 Position          */
+#define LCD_PAL151_R04_0_Msk                                  (0x1fUL << LCD_PAL151_R04_0_Pos)                          /*!< LCD PAL151: R04_0 Mask              */
+#define LCD_PAL151_G04_0_Pos                                  5                                                         /*!< LCD PAL151: G04_0 Position          */
+#define LCD_PAL151_G04_0_Msk                                  (0x1fUL << LCD_PAL151_G04_0_Pos)                          /*!< LCD PAL151: G04_0 Mask              */
+#define LCD_PAL151_B04_0_Pos                                  10                                                        /*!< LCD PAL151: B04_0 Position          */
+#define LCD_PAL151_B04_0_Msk                                  (0x1fUL << LCD_PAL151_B04_0_Pos)                          /*!< LCD PAL151: B04_0 Mask              */
+#define LCD_PAL151_I0_Pos                                     15                                                        /*!< LCD PAL151: I0 Position             */
+#define LCD_PAL151_I0_Msk                                     (0x01UL << LCD_PAL151_I0_Pos)                             /*!< LCD PAL151: I0 Mask                 */
+#define LCD_PAL151_R14_0_Pos                                  16                                                        /*!< LCD PAL151: R14_0 Position          */
+#define LCD_PAL151_R14_0_Msk                                  (0x1fUL << LCD_PAL151_R14_0_Pos)                          /*!< LCD PAL151: R14_0 Mask              */
+#define LCD_PAL151_G14_0_Pos                                  21                                                        /*!< LCD PAL151: G14_0 Position          */
+#define LCD_PAL151_G14_0_Msk                                  (0x1fUL << LCD_PAL151_G14_0_Pos)                          /*!< LCD PAL151: G14_0 Mask              */
+#define LCD_PAL151_B14_0_Pos                                  26                                                        /*!< LCD PAL151: B14_0 Position          */
+#define LCD_PAL151_B14_0_Msk                                  (0x1fUL << LCD_PAL151_B14_0_Pos)                          /*!< LCD PAL151: B14_0 Mask              */
+#define LCD_PAL151_I1_Pos                                     31                                                        /*!< LCD PAL151: I1 Position             */
+#define LCD_PAL151_I1_Msk                                     (0x01UL << LCD_PAL151_I1_Pos)                             /*!< LCD PAL151: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL152  -------------------------------------------
+#define LCD_PAL152_R04_0_Pos                                  0                                                         /*!< LCD PAL152: R04_0 Position          */
+#define LCD_PAL152_R04_0_Msk                                  (0x1fUL << LCD_PAL152_R04_0_Pos)                          /*!< LCD PAL152: R04_0 Mask              */
+#define LCD_PAL152_G04_0_Pos                                  5                                                         /*!< LCD PAL152: G04_0 Position          */
+#define LCD_PAL152_G04_0_Msk                                  (0x1fUL << LCD_PAL152_G04_0_Pos)                          /*!< LCD PAL152: G04_0 Mask              */
+#define LCD_PAL152_B04_0_Pos                                  10                                                        /*!< LCD PAL152: B04_0 Position          */
+#define LCD_PAL152_B04_0_Msk                                  (0x1fUL << LCD_PAL152_B04_0_Pos)                          /*!< LCD PAL152: B04_0 Mask              */
+#define LCD_PAL152_I0_Pos                                     15                                                        /*!< LCD PAL152: I0 Position             */
+#define LCD_PAL152_I0_Msk                                     (0x01UL << LCD_PAL152_I0_Pos)                             /*!< LCD PAL152: I0 Mask                 */
+#define LCD_PAL152_R14_0_Pos                                  16                                                        /*!< LCD PAL152: R14_0 Position          */
+#define LCD_PAL152_R14_0_Msk                                  (0x1fUL << LCD_PAL152_R14_0_Pos)                          /*!< LCD PAL152: R14_0 Mask              */
+#define LCD_PAL152_G14_0_Pos                                  21                                                        /*!< LCD PAL152: G14_0 Position          */
+#define LCD_PAL152_G14_0_Msk                                  (0x1fUL << LCD_PAL152_G14_0_Pos)                          /*!< LCD PAL152: G14_0 Mask              */
+#define LCD_PAL152_B14_0_Pos                                  26                                                        /*!< LCD PAL152: B14_0 Position          */
+#define LCD_PAL152_B14_0_Msk                                  (0x1fUL << LCD_PAL152_B14_0_Pos)                          /*!< LCD PAL152: B14_0 Mask              */
+#define LCD_PAL152_I1_Pos                                     31                                                        /*!< LCD PAL152: I1 Position             */
+#define LCD_PAL152_I1_Msk                                     (0x01UL << LCD_PAL152_I1_Pos)                             /*!< LCD PAL152: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL153  -------------------------------------------
+#define LCD_PAL153_R04_0_Pos                                  0                                                         /*!< LCD PAL153: R04_0 Position          */
+#define LCD_PAL153_R04_0_Msk                                  (0x1fUL << LCD_PAL153_R04_0_Pos)                          /*!< LCD PAL153: R04_0 Mask              */
+#define LCD_PAL153_G04_0_Pos                                  5                                                         /*!< LCD PAL153: G04_0 Position          */
+#define LCD_PAL153_G04_0_Msk                                  (0x1fUL << LCD_PAL153_G04_0_Pos)                          /*!< LCD PAL153: G04_0 Mask              */
+#define LCD_PAL153_B04_0_Pos                                  10                                                        /*!< LCD PAL153: B04_0 Position          */
+#define LCD_PAL153_B04_0_Msk                                  (0x1fUL << LCD_PAL153_B04_0_Pos)                          /*!< LCD PAL153: B04_0 Mask              */
+#define LCD_PAL153_I0_Pos                                     15                                                        /*!< LCD PAL153: I0 Position             */
+#define LCD_PAL153_I0_Msk                                     (0x01UL << LCD_PAL153_I0_Pos)                             /*!< LCD PAL153: I0 Mask                 */
+#define LCD_PAL153_R14_0_Pos                                  16                                                        /*!< LCD PAL153: R14_0 Position          */
+#define LCD_PAL153_R14_0_Msk                                  (0x1fUL << LCD_PAL153_R14_0_Pos)                          /*!< LCD PAL153: R14_0 Mask              */
+#define LCD_PAL153_G14_0_Pos                                  21                                                        /*!< LCD PAL153: G14_0 Position          */
+#define LCD_PAL153_G14_0_Msk                                  (0x1fUL << LCD_PAL153_G14_0_Pos)                          /*!< LCD PAL153: G14_0 Mask              */
+#define LCD_PAL153_B14_0_Pos                                  26                                                        /*!< LCD PAL153: B14_0 Position          */
+#define LCD_PAL153_B14_0_Msk                                  (0x1fUL << LCD_PAL153_B14_0_Pos)                          /*!< LCD PAL153: B14_0 Mask              */
+#define LCD_PAL153_I1_Pos                                     31                                                        /*!< LCD PAL153: I1 Position             */
+#define LCD_PAL153_I1_Msk                                     (0x01UL << LCD_PAL153_I1_Pos)                             /*!< LCD PAL153: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL154  -------------------------------------------
+#define LCD_PAL154_R04_0_Pos                                  0                                                         /*!< LCD PAL154: R04_0 Position          */
+#define LCD_PAL154_R04_0_Msk                                  (0x1fUL << LCD_PAL154_R04_0_Pos)                          /*!< LCD PAL154: R04_0 Mask              */
+#define LCD_PAL154_G04_0_Pos                                  5                                                         /*!< LCD PAL154: G04_0 Position          */
+#define LCD_PAL154_G04_0_Msk                                  (0x1fUL << LCD_PAL154_G04_0_Pos)                          /*!< LCD PAL154: G04_0 Mask              */
+#define LCD_PAL154_B04_0_Pos                                  10                                                        /*!< LCD PAL154: B04_0 Position          */
+#define LCD_PAL154_B04_0_Msk                                  (0x1fUL << LCD_PAL154_B04_0_Pos)                          /*!< LCD PAL154: B04_0 Mask              */
+#define LCD_PAL154_I0_Pos                                     15                                                        /*!< LCD PAL154: I0 Position             */
+#define LCD_PAL154_I0_Msk                                     (0x01UL << LCD_PAL154_I0_Pos)                             /*!< LCD PAL154: I0 Mask                 */
+#define LCD_PAL154_R14_0_Pos                                  16                                                        /*!< LCD PAL154: R14_0 Position          */
+#define LCD_PAL154_R14_0_Msk                                  (0x1fUL << LCD_PAL154_R14_0_Pos)                          /*!< LCD PAL154: R14_0 Mask              */
+#define LCD_PAL154_G14_0_Pos                                  21                                                        /*!< LCD PAL154: G14_0 Position          */
+#define LCD_PAL154_G14_0_Msk                                  (0x1fUL << LCD_PAL154_G14_0_Pos)                          /*!< LCD PAL154: G14_0 Mask              */
+#define LCD_PAL154_B14_0_Pos                                  26                                                        /*!< LCD PAL154: B14_0 Position          */
+#define LCD_PAL154_B14_0_Msk                                  (0x1fUL << LCD_PAL154_B14_0_Pos)                          /*!< LCD PAL154: B14_0 Mask              */
+#define LCD_PAL154_I1_Pos                                     31                                                        /*!< LCD PAL154: I1 Position             */
+#define LCD_PAL154_I1_Msk                                     (0x01UL << LCD_PAL154_I1_Pos)                             /*!< LCD PAL154: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL155  -------------------------------------------
+#define LCD_PAL155_R04_0_Pos                                  0                                                         /*!< LCD PAL155: R04_0 Position          */
+#define LCD_PAL155_R04_0_Msk                                  (0x1fUL << LCD_PAL155_R04_0_Pos)                          /*!< LCD PAL155: R04_0 Mask              */
+#define LCD_PAL155_G04_0_Pos                                  5                                                         /*!< LCD PAL155: G04_0 Position          */
+#define LCD_PAL155_G04_0_Msk                                  (0x1fUL << LCD_PAL155_G04_0_Pos)                          /*!< LCD PAL155: G04_0 Mask              */
+#define LCD_PAL155_B04_0_Pos                                  10                                                        /*!< LCD PAL155: B04_0 Position          */
+#define LCD_PAL155_B04_0_Msk                                  (0x1fUL << LCD_PAL155_B04_0_Pos)                          /*!< LCD PAL155: B04_0 Mask              */
+#define LCD_PAL155_I0_Pos                                     15                                                        /*!< LCD PAL155: I0 Position             */
+#define LCD_PAL155_I0_Msk                                     (0x01UL << LCD_PAL155_I0_Pos)                             /*!< LCD PAL155: I0 Mask                 */
+#define LCD_PAL155_R14_0_Pos                                  16                                                        /*!< LCD PAL155: R14_0 Position          */
+#define LCD_PAL155_R14_0_Msk                                  (0x1fUL << LCD_PAL155_R14_0_Pos)                          /*!< LCD PAL155: R14_0 Mask              */
+#define LCD_PAL155_G14_0_Pos                                  21                                                        /*!< LCD PAL155: G14_0 Position          */
+#define LCD_PAL155_G14_0_Msk                                  (0x1fUL << LCD_PAL155_G14_0_Pos)                          /*!< LCD PAL155: G14_0 Mask              */
+#define LCD_PAL155_B14_0_Pos                                  26                                                        /*!< LCD PAL155: B14_0 Position          */
+#define LCD_PAL155_B14_0_Msk                                  (0x1fUL << LCD_PAL155_B14_0_Pos)                          /*!< LCD PAL155: B14_0 Mask              */
+#define LCD_PAL155_I1_Pos                                     31                                                        /*!< LCD PAL155: I1 Position             */
+#define LCD_PAL155_I1_Msk                                     (0x01UL << LCD_PAL155_I1_Pos)                             /*!< LCD PAL155: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL156  -------------------------------------------
+#define LCD_PAL156_R04_0_Pos                                  0                                                         /*!< LCD PAL156: R04_0 Position          */
+#define LCD_PAL156_R04_0_Msk                                  (0x1fUL << LCD_PAL156_R04_0_Pos)                          /*!< LCD PAL156: R04_0 Mask              */
+#define LCD_PAL156_G04_0_Pos                                  5                                                         /*!< LCD PAL156: G04_0 Position          */
+#define LCD_PAL156_G04_0_Msk                                  (0x1fUL << LCD_PAL156_G04_0_Pos)                          /*!< LCD PAL156: G04_0 Mask              */
+#define LCD_PAL156_B04_0_Pos                                  10                                                        /*!< LCD PAL156: B04_0 Position          */
+#define LCD_PAL156_B04_0_Msk                                  (0x1fUL << LCD_PAL156_B04_0_Pos)                          /*!< LCD PAL156: B04_0 Mask              */
+#define LCD_PAL156_I0_Pos                                     15                                                        /*!< LCD PAL156: I0 Position             */
+#define LCD_PAL156_I0_Msk                                     (0x01UL << LCD_PAL156_I0_Pos)                             /*!< LCD PAL156: I0 Mask                 */
+#define LCD_PAL156_R14_0_Pos                                  16                                                        /*!< LCD PAL156: R14_0 Position          */
+#define LCD_PAL156_R14_0_Msk                                  (0x1fUL << LCD_PAL156_R14_0_Pos)                          /*!< LCD PAL156: R14_0 Mask              */
+#define LCD_PAL156_G14_0_Pos                                  21                                                        /*!< LCD PAL156: G14_0 Position          */
+#define LCD_PAL156_G14_0_Msk                                  (0x1fUL << LCD_PAL156_G14_0_Pos)                          /*!< LCD PAL156: G14_0 Mask              */
+#define LCD_PAL156_B14_0_Pos                                  26                                                        /*!< LCD PAL156: B14_0 Position          */
+#define LCD_PAL156_B14_0_Msk                                  (0x1fUL << LCD_PAL156_B14_0_Pos)                          /*!< LCD PAL156: B14_0 Mask              */
+#define LCD_PAL156_I1_Pos                                     31                                                        /*!< LCD PAL156: I1 Position             */
+#define LCD_PAL156_I1_Msk                                     (0x01UL << LCD_PAL156_I1_Pos)                             /*!< LCD PAL156: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL157  -------------------------------------------
+#define LCD_PAL157_R04_0_Pos                                  0                                                         /*!< LCD PAL157: R04_0 Position          */
+#define LCD_PAL157_R04_0_Msk                                  (0x1fUL << LCD_PAL157_R04_0_Pos)                          /*!< LCD PAL157: R04_0 Mask              */
+#define LCD_PAL157_G04_0_Pos                                  5                                                         /*!< LCD PAL157: G04_0 Position          */
+#define LCD_PAL157_G04_0_Msk                                  (0x1fUL << LCD_PAL157_G04_0_Pos)                          /*!< LCD PAL157: G04_0 Mask              */
+#define LCD_PAL157_B04_0_Pos                                  10                                                        /*!< LCD PAL157: B04_0 Position          */
+#define LCD_PAL157_B04_0_Msk                                  (0x1fUL << LCD_PAL157_B04_0_Pos)                          /*!< LCD PAL157: B04_0 Mask              */
+#define LCD_PAL157_I0_Pos                                     15                                                        /*!< LCD PAL157: I0 Position             */
+#define LCD_PAL157_I0_Msk                                     (0x01UL << LCD_PAL157_I0_Pos)                             /*!< LCD PAL157: I0 Mask                 */
+#define LCD_PAL157_R14_0_Pos                                  16                                                        /*!< LCD PAL157: R14_0 Position          */
+#define LCD_PAL157_R14_0_Msk                                  (0x1fUL << LCD_PAL157_R14_0_Pos)                          /*!< LCD PAL157: R14_0 Mask              */
+#define LCD_PAL157_G14_0_Pos                                  21                                                        /*!< LCD PAL157: G14_0 Position          */
+#define LCD_PAL157_G14_0_Msk                                  (0x1fUL << LCD_PAL157_G14_0_Pos)                          /*!< LCD PAL157: G14_0 Mask              */
+#define LCD_PAL157_B14_0_Pos                                  26                                                        /*!< LCD PAL157: B14_0 Position          */
+#define LCD_PAL157_B14_0_Msk                                  (0x1fUL << LCD_PAL157_B14_0_Pos)                          /*!< LCD PAL157: B14_0 Mask              */
+#define LCD_PAL157_I1_Pos                                     31                                                        /*!< LCD PAL157: I1 Position             */
+#define LCD_PAL157_I1_Msk                                     (0x01UL << LCD_PAL157_I1_Pos)                             /*!< LCD PAL157: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL158  -------------------------------------------
+#define LCD_PAL158_R04_0_Pos                                  0                                                         /*!< LCD PAL158: R04_0 Position          */
+#define LCD_PAL158_R04_0_Msk                                  (0x1fUL << LCD_PAL158_R04_0_Pos)                          /*!< LCD PAL158: R04_0 Mask              */
+#define LCD_PAL158_G04_0_Pos                                  5                                                         /*!< LCD PAL158: G04_0 Position          */
+#define LCD_PAL158_G04_0_Msk                                  (0x1fUL << LCD_PAL158_G04_0_Pos)                          /*!< LCD PAL158: G04_0 Mask              */
+#define LCD_PAL158_B04_0_Pos                                  10                                                        /*!< LCD PAL158: B04_0 Position          */
+#define LCD_PAL158_B04_0_Msk                                  (0x1fUL << LCD_PAL158_B04_0_Pos)                          /*!< LCD PAL158: B04_0 Mask              */
+#define LCD_PAL158_I0_Pos                                     15                                                        /*!< LCD PAL158: I0 Position             */
+#define LCD_PAL158_I0_Msk                                     (0x01UL << LCD_PAL158_I0_Pos)                             /*!< LCD PAL158: I0 Mask                 */
+#define LCD_PAL158_R14_0_Pos                                  16                                                        /*!< LCD PAL158: R14_0 Position          */
+#define LCD_PAL158_R14_0_Msk                                  (0x1fUL << LCD_PAL158_R14_0_Pos)                          /*!< LCD PAL158: R14_0 Mask              */
+#define LCD_PAL158_G14_0_Pos                                  21                                                        /*!< LCD PAL158: G14_0 Position          */
+#define LCD_PAL158_G14_0_Msk                                  (0x1fUL << LCD_PAL158_G14_0_Pos)                          /*!< LCD PAL158: G14_0 Mask              */
+#define LCD_PAL158_B14_0_Pos                                  26                                                        /*!< LCD PAL158: B14_0 Position          */
+#define LCD_PAL158_B14_0_Msk                                  (0x1fUL << LCD_PAL158_B14_0_Pos)                          /*!< LCD PAL158: B14_0 Mask              */
+#define LCD_PAL158_I1_Pos                                     31                                                        /*!< LCD PAL158: I1 Position             */
+#define LCD_PAL158_I1_Msk                                     (0x01UL << LCD_PAL158_I1_Pos)                             /*!< LCD PAL158: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL159  -------------------------------------------
+#define LCD_PAL159_R04_0_Pos                                  0                                                         /*!< LCD PAL159: R04_0 Position          */
+#define LCD_PAL159_R04_0_Msk                                  (0x1fUL << LCD_PAL159_R04_0_Pos)                          /*!< LCD PAL159: R04_0 Mask              */
+#define LCD_PAL159_G04_0_Pos                                  5                                                         /*!< LCD PAL159: G04_0 Position          */
+#define LCD_PAL159_G04_0_Msk                                  (0x1fUL << LCD_PAL159_G04_0_Pos)                          /*!< LCD PAL159: G04_0 Mask              */
+#define LCD_PAL159_B04_0_Pos                                  10                                                        /*!< LCD PAL159: B04_0 Position          */
+#define LCD_PAL159_B04_0_Msk                                  (0x1fUL << LCD_PAL159_B04_0_Pos)                          /*!< LCD PAL159: B04_0 Mask              */
+#define LCD_PAL159_I0_Pos                                     15                                                        /*!< LCD PAL159: I0 Position             */
+#define LCD_PAL159_I0_Msk                                     (0x01UL << LCD_PAL159_I0_Pos)                             /*!< LCD PAL159: I0 Mask                 */
+#define LCD_PAL159_R14_0_Pos                                  16                                                        /*!< LCD PAL159: R14_0 Position          */
+#define LCD_PAL159_R14_0_Msk                                  (0x1fUL << LCD_PAL159_R14_0_Pos)                          /*!< LCD PAL159: R14_0 Mask              */
+#define LCD_PAL159_G14_0_Pos                                  21                                                        /*!< LCD PAL159: G14_0 Position          */
+#define LCD_PAL159_G14_0_Msk                                  (0x1fUL << LCD_PAL159_G14_0_Pos)                          /*!< LCD PAL159: G14_0 Mask              */
+#define LCD_PAL159_B14_0_Pos                                  26                                                        /*!< LCD PAL159: B14_0 Position          */
+#define LCD_PAL159_B14_0_Msk                                  (0x1fUL << LCD_PAL159_B14_0_Pos)                          /*!< LCD PAL159: B14_0 Mask              */
+#define LCD_PAL159_I1_Pos                                     31                                                        /*!< LCD PAL159: I1 Position             */
+#define LCD_PAL159_I1_Msk                                     (0x01UL << LCD_PAL159_I1_Pos)                             /*!< LCD PAL159: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL160  -------------------------------------------
+#define LCD_PAL160_R04_0_Pos                                  0                                                         /*!< LCD PAL160: R04_0 Position          */
+#define LCD_PAL160_R04_0_Msk                                  (0x1fUL << LCD_PAL160_R04_0_Pos)                          /*!< LCD PAL160: R04_0 Mask              */
+#define LCD_PAL160_G04_0_Pos                                  5                                                         /*!< LCD PAL160: G04_0 Position          */
+#define LCD_PAL160_G04_0_Msk                                  (0x1fUL << LCD_PAL160_G04_0_Pos)                          /*!< LCD PAL160: G04_0 Mask              */
+#define LCD_PAL160_B04_0_Pos                                  10                                                        /*!< LCD PAL160: B04_0 Position          */
+#define LCD_PAL160_B04_0_Msk                                  (0x1fUL << LCD_PAL160_B04_0_Pos)                          /*!< LCD PAL160: B04_0 Mask              */
+#define LCD_PAL160_I0_Pos                                     15                                                        /*!< LCD PAL160: I0 Position             */
+#define LCD_PAL160_I0_Msk                                     (0x01UL << LCD_PAL160_I0_Pos)                             /*!< LCD PAL160: I0 Mask                 */
+#define LCD_PAL160_R14_0_Pos                                  16                                                        /*!< LCD PAL160: R14_0 Position          */
+#define LCD_PAL160_R14_0_Msk                                  (0x1fUL << LCD_PAL160_R14_0_Pos)                          /*!< LCD PAL160: R14_0 Mask              */
+#define LCD_PAL160_G14_0_Pos                                  21                                                        /*!< LCD PAL160: G14_0 Position          */
+#define LCD_PAL160_G14_0_Msk                                  (0x1fUL << LCD_PAL160_G14_0_Pos)                          /*!< LCD PAL160: G14_0 Mask              */
+#define LCD_PAL160_B14_0_Pos                                  26                                                        /*!< LCD PAL160: B14_0 Position          */
+#define LCD_PAL160_B14_0_Msk                                  (0x1fUL << LCD_PAL160_B14_0_Pos)                          /*!< LCD PAL160: B14_0 Mask              */
+#define LCD_PAL160_I1_Pos                                     31                                                        /*!< LCD PAL160: I1 Position             */
+#define LCD_PAL160_I1_Msk                                     (0x01UL << LCD_PAL160_I1_Pos)                             /*!< LCD PAL160: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL161  -------------------------------------------
+#define LCD_PAL161_R04_0_Pos                                  0                                                         /*!< LCD PAL161: R04_0 Position          */
+#define LCD_PAL161_R04_0_Msk                                  (0x1fUL << LCD_PAL161_R04_0_Pos)                          /*!< LCD PAL161: R04_0 Mask              */
+#define LCD_PAL161_G04_0_Pos                                  5                                                         /*!< LCD PAL161: G04_0 Position          */
+#define LCD_PAL161_G04_0_Msk                                  (0x1fUL << LCD_PAL161_G04_0_Pos)                          /*!< LCD PAL161: G04_0 Mask              */
+#define LCD_PAL161_B04_0_Pos                                  10                                                        /*!< LCD PAL161: B04_0 Position          */
+#define LCD_PAL161_B04_0_Msk                                  (0x1fUL << LCD_PAL161_B04_0_Pos)                          /*!< LCD PAL161: B04_0 Mask              */
+#define LCD_PAL161_I0_Pos                                     15                                                        /*!< LCD PAL161: I0 Position             */
+#define LCD_PAL161_I0_Msk                                     (0x01UL << LCD_PAL161_I0_Pos)                             /*!< LCD PAL161: I0 Mask                 */
+#define LCD_PAL161_R14_0_Pos                                  16                                                        /*!< LCD PAL161: R14_0 Position          */
+#define LCD_PAL161_R14_0_Msk                                  (0x1fUL << LCD_PAL161_R14_0_Pos)                          /*!< LCD PAL161: R14_0 Mask              */
+#define LCD_PAL161_G14_0_Pos                                  21                                                        /*!< LCD PAL161: G14_0 Position          */
+#define LCD_PAL161_G14_0_Msk                                  (0x1fUL << LCD_PAL161_G14_0_Pos)                          /*!< LCD PAL161: G14_0 Mask              */
+#define LCD_PAL161_B14_0_Pos                                  26                                                        /*!< LCD PAL161: B14_0 Position          */
+#define LCD_PAL161_B14_0_Msk                                  (0x1fUL << LCD_PAL161_B14_0_Pos)                          /*!< LCD PAL161: B14_0 Mask              */
+#define LCD_PAL161_I1_Pos                                     31                                                        /*!< LCD PAL161: I1 Position             */
+#define LCD_PAL161_I1_Msk                                     (0x01UL << LCD_PAL161_I1_Pos)                             /*!< LCD PAL161: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL162  -------------------------------------------
+#define LCD_PAL162_R04_0_Pos                                  0                                                         /*!< LCD PAL162: R04_0 Position          */
+#define LCD_PAL162_R04_0_Msk                                  (0x1fUL << LCD_PAL162_R04_0_Pos)                          /*!< LCD PAL162: R04_0 Mask              */
+#define LCD_PAL162_G04_0_Pos                                  5                                                         /*!< LCD PAL162: G04_0 Position          */
+#define LCD_PAL162_G04_0_Msk                                  (0x1fUL << LCD_PAL162_G04_0_Pos)                          /*!< LCD PAL162: G04_0 Mask              */
+#define LCD_PAL162_B04_0_Pos                                  10                                                        /*!< LCD PAL162: B04_0 Position          */
+#define LCD_PAL162_B04_0_Msk                                  (0x1fUL << LCD_PAL162_B04_0_Pos)                          /*!< LCD PAL162: B04_0 Mask              */
+#define LCD_PAL162_I0_Pos                                     15                                                        /*!< LCD PAL162: I0 Position             */
+#define LCD_PAL162_I0_Msk                                     (0x01UL << LCD_PAL162_I0_Pos)                             /*!< LCD PAL162: I0 Mask                 */
+#define LCD_PAL162_R14_0_Pos                                  16                                                        /*!< LCD PAL162: R14_0 Position          */
+#define LCD_PAL162_R14_0_Msk                                  (0x1fUL << LCD_PAL162_R14_0_Pos)                          /*!< LCD PAL162: R14_0 Mask              */
+#define LCD_PAL162_G14_0_Pos                                  21                                                        /*!< LCD PAL162: G14_0 Position          */
+#define LCD_PAL162_G14_0_Msk                                  (0x1fUL << LCD_PAL162_G14_0_Pos)                          /*!< LCD PAL162: G14_0 Mask              */
+#define LCD_PAL162_B14_0_Pos                                  26                                                        /*!< LCD PAL162: B14_0 Position          */
+#define LCD_PAL162_B14_0_Msk                                  (0x1fUL << LCD_PAL162_B14_0_Pos)                          /*!< LCD PAL162: B14_0 Mask              */
+#define LCD_PAL162_I1_Pos                                     31                                                        /*!< LCD PAL162: I1 Position             */
+#define LCD_PAL162_I1_Msk                                     (0x01UL << LCD_PAL162_I1_Pos)                             /*!< LCD PAL162: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL163  -------------------------------------------
+#define LCD_PAL163_R04_0_Pos                                  0                                                         /*!< LCD PAL163: R04_0 Position          */
+#define LCD_PAL163_R04_0_Msk                                  (0x1fUL << LCD_PAL163_R04_0_Pos)                          /*!< LCD PAL163: R04_0 Mask              */
+#define LCD_PAL163_G04_0_Pos                                  5                                                         /*!< LCD PAL163: G04_0 Position          */
+#define LCD_PAL163_G04_0_Msk                                  (0x1fUL << LCD_PAL163_G04_0_Pos)                          /*!< LCD PAL163: G04_0 Mask              */
+#define LCD_PAL163_B04_0_Pos                                  10                                                        /*!< LCD PAL163: B04_0 Position          */
+#define LCD_PAL163_B04_0_Msk                                  (0x1fUL << LCD_PAL163_B04_0_Pos)                          /*!< LCD PAL163: B04_0 Mask              */
+#define LCD_PAL163_I0_Pos                                     15                                                        /*!< LCD PAL163: I0 Position             */
+#define LCD_PAL163_I0_Msk                                     (0x01UL << LCD_PAL163_I0_Pos)                             /*!< LCD PAL163: I0 Mask                 */
+#define LCD_PAL163_R14_0_Pos                                  16                                                        /*!< LCD PAL163: R14_0 Position          */
+#define LCD_PAL163_R14_0_Msk                                  (0x1fUL << LCD_PAL163_R14_0_Pos)                          /*!< LCD PAL163: R14_0 Mask              */
+#define LCD_PAL163_G14_0_Pos                                  21                                                        /*!< LCD PAL163: G14_0 Position          */
+#define LCD_PAL163_G14_0_Msk                                  (0x1fUL << LCD_PAL163_G14_0_Pos)                          /*!< LCD PAL163: G14_0 Mask              */
+#define LCD_PAL163_B14_0_Pos                                  26                                                        /*!< LCD PAL163: B14_0 Position          */
+#define LCD_PAL163_B14_0_Msk                                  (0x1fUL << LCD_PAL163_B14_0_Pos)                          /*!< LCD PAL163: B14_0 Mask              */
+#define LCD_PAL163_I1_Pos                                     31                                                        /*!< LCD PAL163: I1 Position             */
+#define LCD_PAL163_I1_Msk                                     (0x01UL << LCD_PAL163_I1_Pos)                             /*!< LCD PAL163: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL164  -------------------------------------------
+#define LCD_PAL164_R04_0_Pos                                  0                                                         /*!< LCD PAL164: R04_0 Position          */
+#define LCD_PAL164_R04_0_Msk                                  (0x1fUL << LCD_PAL164_R04_0_Pos)                          /*!< LCD PAL164: R04_0 Mask              */
+#define LCD_PAL164_G04_0_Pos                                  5                                                         /*!< LCD PAL164: G04_0 Position          */
+#define LCD_PAL164_G04_0_Msk                                  (0x1fUL << LCD_PAL164_G04_0_Pos)                          /*!< LCD PAL164: G04_0 Mask              */
+#define LCD_PAL164_B04_0_Pos                                  10                                                        /*!< LCD PAL164: B04_0 Position          */
+#define LCD_PAL164_B04_0_Msk                                  (0x1fUL << LCD_PAL164_B04_0_Pos)                          /*!< LCD PAL164: B04_0 Mask              */
+#define LCD_PAL164_I0_Pos                                     15                                                        /*!< LCD PAL164: I0 Position             */
+#define LCD_PAL164_I0_Msk                                     (0x01UL << LCD_PAL164_I0_Pos)                             /*!< LCD PAL164: I0 Mask                 */
+#define LCD_PAL164_R14_0_Pos                                  16                                                        /*!< LCD PAL164: R14_0 Position          */
+#define LCD_PAL164_R14_0_Msk                                  (0x1fUL << LCD_PAL164_R14_0_Pos)                          /*!< LCD PAL164: R14_0 Mask              */
+#define LCD_PAL164_G14_0_Pos                                  21                                                        /*!< LCD PAL164: G14_0 Position          */
+#define LCD_PAL164_G14_0_Msk                                  (0x1fUL << LCD_PAL164_G14_0_Pos)                          /*!< LCD PAL164: G14_0 Mask              */
+#define LCD_PAL164_B14_0_Pos                                  26                                                        /*!< LCD PAL164: B14_0 Position          */
+#define LCD_PAL164_B14_0_Msk                                  (0x1fUL << LCD_PAL164_B14_0_Pos)                          /*!< LCD PAL164: B14_0 Mask              */
+#define LCD_PAL164_I1_Pos                                     31                                                        /*!< LCD PAL164: I1 Position             */
+#define LCD_PAL164_I1_Msk                                     (0x01UL << LCD_PAL164_I1_Pos)                             /*!< LCD PAL164: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL165  -------------------------------------------
+#define LCD_PAL165_R04_0_Pos                                  0                                                         /*!< LCD PAL165: R04_0 Position          */
+#define LCD_PAL165_R04_0_Msk                                  (0x1fUL << LCD_PAL165_R04_0_Pos)                          /*!< LCD PAL165: R04_0 Mask              */
+#define LCD_PAL165_G04_0_Pos                                  5                                                         /*!< LCD PAL165: G04_0 Position          */
+#define LCD_PAL165_G04_0_Msk                                  (0x1fUL << LCD_PAL165_G04_0_Pos)                          /*!< LCD PAL165: G04_0 Mask              */
+#define LCD_PAL165_B04_0_Pos                                  10                                                        /*!< LCD PAL165: B04_0 Position          */
+#define LCD_PAL165_B04_0_Msk                                  (0x1fUL << LCD_PAL165_B04_0_Pos)                          /*!< LCD PAL165: B04_0 Mask              */
+#define LCD_PAL165_I0_Pos                                     15                                                        /*!< LCD PAL165: I0 Position             */
+#define LCD_PAL165_I0_Msk                                     (0x01UL << LCD_PAL165_I0_Pos)                             /*!< LCD PAL165: I0 Mask                 */
+#define LCD_PAL165_R14_0_Pos                                  16                                                        /*!< LCD PAL165: R14_0 Position          */
+#define LCD_PAL165_R14_0_Msk                                  (0x1fUL << LCD_PAL165_R14_0_Pos)                          /*!< LCD PAL165: R14_0 Mask              */
+#define LCD_PAL165_G14_0_Pos                                  21                                                        /*!< LCD PAL165: G14_0 Position          */
+#define LCD_PAL165_G14_0_Msk                                  (0x1fUL << LCD_PAL165_G14_0_Pos)                          /*!< LCD PAL165: G14_0 Mask              */
+#define LCD_PAL165_B14_0_Pos                                  26                                                        /*!< LCD PAL165: B14_0 Position          */
+#define LCD_PAL165_B14_0_Msk                                  (0x1fUL << LCD_PAL165_B14_0_Pos)                          /*!< LCD PAL165: B14_0 Mask              */
+#define LCD_PAL165_I1_Pos                                     31                                                        /*!< LCD PAL165: I1 Position             */
+#define LCD_PAL165_I1_Msk                                     (0x01UL << LCD_PAL165_I1_Pos)                             /*!< LCD PAL165: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL166  -------------------------------------------
+#define LCD_PAL166_R04_0_Pos                                  0                                                         /*!< LCD PAL166: R04_0 Position          */
+#define LCD_PAL166_R04_0_Msk                                  (0x1fUL << LCD_PAL166_R04_0_Pos)                          /*!< LCD PAL166: R04_0 Mask              */
+#define LCD_PAL166_G04_0_Pos                                  5                                                         /*!< LCD PAL166: G04_0 Position          */
+#define LCD_PAL166_G04_0_Msk                                  (0x1fUL << LCD_PAL166_G04_0_Pos)                          /*!< LCD PAL166: G04_0 Mask              */
+#define LCD_PAL166_B04_0_Pos                                  10                                                        /*!< LCD PAL166: B04_0 Position          */
+#define LCD_PAL166_B04_0_Msk                                  (0x1fUL << LCD_PAL166_B04_0_Pos)                          /*!< LCD PAL166: B04_0 Mask              */
+#define LCD_PAL166_I0_Pos                                     15                                                        /*!< LCD PAL166: I0 Position             */
+#define LCD_PAL166_I0_Msk                                     (0x01UL << LCD_PAL166_I0_Pos)                             /*!< LCD PAL166: I0 Mask                 */
+#define LCD_PAL166_R14_0_Pos                                  16                                                        /*!< LCD PAL166: R14_0 Position          */
+#define LCD_PAL166_R14_0_Msk                                  (0x1fUL << LCD_PAL166_R14_0_Pos)                          /*!< LCD PAL166: R14_0 Mask              */
+#define LCD_PAL166_G14_0_Pos                                  21                                                        /*!< LCD PAL166: G14_0 Position          */
+#define LCD_PAL166_G14_0_Msk                                  (0x1fUL << LCD_PAL166_G14_0_Pos)                          /*!< LCD PAL166: G14_0 Mask              */
+#define LCD_PAL166_B14_0_Pos                                  26                                                        /*!< LCD PAL166: B14_0 Position          */
+#define LCD_PAL166_B14_0_Msk                                  (0x1fUL << LCD_PAL166_B14_0_Pos)                          /*!< LCD PAL166: B14_0 Mask              */
+#define LCD_PAL166_I1_Pos                                     31                                                        /*!< LCD PAL166: I1 Position             */
+#define LCD_PAL166_I1_Msk                                     (0x01UL << LCD_PAL166_I1_Pos)                             /*!< LCD PAL166: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL167  -------------------------------------------
+#define LCD_PAL167_R04_0_Pos                                  0                                                         /*!< LCD PAL167: R04_0 Position          */
+#define LCD_PAL167_R04_0_Msk                                  (0x1fUL << LCD_PAL167_R04_0_Pos)                          /*!< LCD PAL167: R04_0 Mask              */
+#define LCD_PAL167_G04_0_Pos                                  5                                                         /*!< LCD PAL167: G04_0 Position          */
+#define LCD_PAL167_G04_0_Msk                                  (0x1fUL << LCD_PAL167_G04_0_Pos)                          /*!< LCD PAL167: G04_0 Mask              */
+#define LCD_PAL167_B04_0_Pos                                  10                                                        /*!< LCD PAL167: B04_0 Position          */
+#define LCD_PAL167_B04_0_Msk                                  (0x1fUL << LCD_PAL167_B04_0_Pos)                          /*!< LCD PAL167: B04_0 Mask              */
+#define LCD_PAL167_I0_Pos                                     15                                                        /*!< LCD PAL167: I0 Position             */
+#define LCD_PAL167_I0_Msk                                     (0x01UL << LCD_PAL167_I0_Pos)                             /*!< LCD PAL167: I0 Mask                 */
+#define LCD_PAL167_R14_0_Pos                                  16                                                        /*!< LCD PAL167: R14_0 Position          */
+#define LCD_PAL167_R14_0_Msk                                  (0x1fUL << LCD_PAL167_R14_0_Pos)                          /*!< LCD PAL167: R14_0 Mask              */
+#define LCD_PAL167_G14_0_Pos                                  21                                                        /*!< LCD PAL167: G14_0 Position          */
+#define LCD_PAL167_G14_0_Msk                                  (0x1fUL << LCD_PAL167_G14_0_Pos)                          /*!< LCD PAL167: G14_0 Mask              */
+#define LCD_PAL167_B14_0_Pos                                  26                                                        /*!< LCD PAL167: B14_0 Position          */
+#define LCD_PAL167_B14_0_Msk                                  (0x1fUL << LCD_PAL167_B14_0_Pos)                          /*!< LCD PAL167: B14_0 Mask              */
+#define LCD_PAL167_I1_Pos                                     31                                                        /*!< LCD PAL167: I1 Position             */
+#define LCD_PAL167_I1_Msk                                     (0x01UL << LCD_PAL167_I1_Pos)                             /*!< LCD PAL167: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL168  -------------------------------------------
+#define LCD_PAL168_R04_0_Pos                                  0                                                         /*!< LCD PAL168: R04_0 Position          */
+#define LCD_PAL168_R04_0_Msk                                  (0x1fUL << LCD_PAL168_R04_0_Pos)                          /*!< LCD PAL168: R04_0 Mask              */
+#define LCD_PAL168_G04_0_Pos                                  5                                                         /*!< LCD PAL168: G04_0 Position          */
+#define LCD_PAL168_G04_0_Msk                                  (0x1fUL << LCD_PAL168_G04_0_Pos)                          /*!< LCD PAL168: G04_0 Mask              */
+#define LCD_PAL168_B04_0_Pos                                  10                                                        /*!< LCD PAL168: B04_0 Position          */
+#define LCD_PAL168_B04_0_Msk                                  (0x1fUL << LCD_PAL168_B04_0_Pos)                          /*!< LCD PAL168: B04_0 Mask              */
+#define LCD_PAL168_I0_Pos                                     15                                                        /*!< LCD PAL168: I0 Position             */
+#define LCD_PAL168_I0_Msk                                     (0x01UL << LCD_PAL168_I0_Pos)                             /*!< LCD PAL168: I0 Mask                 */
+#define LCD_PAL168_R14_0_Pos                                  16                                                        /*!< LCD PAL168: R14_0 Position          */
+#define LCD_PAL168_R14_0_Msk                                  (0x1fUL << LCD_PAL168_R14_0_Pos)                          /*!< LCD PAL168: R14_0 Mask              */
+#define LCD_PAL168_G14_0_Pos                                  21                                                        /*!< LCD PAL168: G14_0 Position          */
+#define LCD_PAL168_G14_0_Msk                                  (0x1fUL << LCD_PAL168_G14_0_Pos)                          /*!< LCD PAL168: G14_0 Mask              */
+#define LCD_PAL168_B14_0_Pos                                  26                                                        /*!< LCD PAL168: B14_0 Position          */
+#define LCD_PAL168_B14_0_Msk                                  (0x1fUL << LCD_PAL168_B14_0_Pos)                          /*!< LCD PAL168: B14_0 Mask              */
+#define LCD_PAL168_I1_Pos                                     31                                                        /*!< LCD PAL168: I1 Position             */
+#define LCD_PAL168_I1_Msk                                     (0x01UL << LCD_PAL168_I1_Pos)                             /*!< LCD PAL168: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL169  -------------------------------------------
+#define LCD_PAL169_R04_0_Pos                                  0                                                         /*!< LCD PAL169: R04_0 Position          */
+#define LCD_PAL169_R04_0_Msk                                  (0x1fUL << LCD_PAL169_R04_0_Pos)                          /*!< LCD PAL169: R04_0 Mask              */
+#define LCD_PAL169_G04_0_Pos                                  5                                                         /*!< LCD PAL169: G04_0 Position          */
+#define LCD_PAL169_G04_0_Msk                                  (0x1fUL << LCD_PAL169_G04_0_Pos)                          /*!< LCD PAL169: G04_0 Mask              */
+#define LCD_PAL169_B04_0_Pos                                  10                                                        /*!< LCD PAL169: B04_0 Position          */
+#define LCD_PAL169_B04_0_Msk                                  (0x1fUL << LCD_PAL169_B04_0_Pos)                          /*!< LCD PAL169: B04_0 Mask              */
+#define LCD_PAL169_I0_Pos                                     15                                                        /*!< LCD PAL169: I0 Position             */
+#define LCD_PAL169_I0_Msk                                     (0x01UL << LCD_PAL169_I0_Pos)                             /*!< LCD PAL169: I0 Mask                 */
+#define LCD_PAL169_R14_0_Pos                                  16                                                        /*!< LCD PAL169: R14_0 Position          */
+#define LCD_PAL169_R14_0_Msk                                  (0x1fUL << LCD_PAL169_R14_0_Pos)                          /*!< LCD PAL169: R14_0 Mask              */
+#define LCD_PAL169_G14_0_Pos                                  21                                                        /*!< LCD PAL169: G14_0 Position          */
+#define LCD_PAL169_G14_0_Msk                                  (0x1fUL << LCD_PAL169_G14_0_Pos)                          /*!< LCD PAL169: G14_0 Mask              */
+#define LCD_PAL169_B14_0_Pos                                  26                                                        /*!< LCD PAL169: B14_0 Position          */
+#define LCD_PAL169_B14_0_Msk                                  (0x1fUL << LCD_PAL169_B14_0_Pos)                          /*!< LCD PAL169: B14_0 Mask              */
+#define LCD_PAL169_I1_Pos                                     31                                                        /*!< LCD PAL169: I1 Position             */
+#define LCD_PAL169_I1_Msk                                     (0x01UL << LCD_PAL169_I1_Pos)                             /*!< LCD PAL169: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL170  -------------------------------------------
+#define LCD_PAL170_R04_0_Pos                                  0                                                         /*!< LCD PAL170: R04_0 Position          */
+#define LCD_PAL170_R04_0_Msk                                  (0x1fUL << LCD_PAL170_R04_0_Pos)                          /*!< LCD PAL170: R04_0 Mask              */
+#define LCD_PAL170_G04_0_Pos                                  5                                                         /*!< LCD PAL170: G04_0 Position          */
+#define LCD_PAL170_G04_0_Msk                                  (0x1fUL << LCD_PAL170_G04_0_Pos)                          /*!< LCD PAL170: G04_0 Mask              */
+#define LCD_PAL170_B04_0_Pos                                  10                                                        /*!< LCD PAL170: B04_0 Position          */
+#define LCD_PAL170_B04_0_Msk                                  (0x1fUL << LCD_PAL170_B04_0_Pos)                          /*!< LCD PAL170: B04_0 Mask              */
+#define LCD_PAL170_I0_Pos                                     15                                                        /*!< LCD PAL170: I0 Position             */
+#define LCD_PAL170_I0_Msk                                     (0x01UL << LCD_PAL170_I0_Pos)                             /*!< LCD PAL170: I0 Mask                 */
+#define LCD_PAL170_R14_0_Pos                                  16                                                        /*!< LCD PAL170: R14_0 Position          */
+#define LCD_PAL170_R14_0_Msk                                  (0x1fUL << LCD_PAL170_R14_0_Pos)                          /*!< LCD PAL170: R14_0 Mask              */
+#define LCD_PAL170_G14_0_Pos                                  21                                                        /*!< LCD PAL170: G14_0 Position          */
+#define LCD_PAL170_G14_0_Msk                                  (0x1fUL << LCD_PAL170_G14_0_Pos)                          /*!< LCD PAL170: G14_0 Mask              */
+#define LCD_PAL170_B14_0_Pos                                  26                                                        /*!< LCD PAL170: B14_0 Position          */
+#define LCD_PAL170_B14_0_Msk                                  (0x1fUL << LCD_PAL170_B14_0_Pos)                          /*!< LCD PAL170: B14_0 Mask              */
+#define LCD_PAL170_I1_Pos                                     31                                                        /*!< LCD PAL170: I1 Position             */
+#define LCD_PAL170_I1_Msk                                     (0x01UL << LCD_PAL170_I1_Pos)                             /*!< LCD PAL170: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL171  -------------------------------------------
+#define LCD_PAL171_R04_0_Pos                                  0                                                         /*!< LCD PAL171: R04_0 Position          */
+#define LCD_PAL171_R04_0_Msk                                  (0x1fUL << LCD_PAL171_R04_0_Pos)                          /*!< LCD PAL171: R04_0 Mask              */
+#define LCD_PAL171_G04_0_Pos                                  5                                                         /*!< LCD PAL171: G04_0 Position          */
+#define LCD_PAL171_G04_0_Msk                                  (0x1fUL << LCD_PAL171_G04_0_Pos)                          /*!< LCD PAL171: G04_0 Mask              */
+#define LCD_PAL171_B04_0_Pos                                  10                                                        /*!< LCD PAL171: B04_0 Position          */
+#define LCD_PAL171_B04_0_Msk                                  (0x1fUL << LCD_PAL171_B04_0_Pos)                          /*!< LCD PAL171: B04_0 Mask              */
+#define LCD_PAL171_I0_Pos                                     15                                                        /*!< LCD PAL171: I0 Position             */
+#define LCD_PAL171_I0_Msk                                     (0x01UL << LCD_PAL171_I0_Pos)                             /*!< LCD PAL171: I0 Mask                 */
+#define LCD_PAL171_R14_0_Pos                                  16                                                        /*!< LCD PAL171: R14_0 Position          */
+#define LCD_PAL171_R14_0_Msk                                  (0x1fUL << LCD_PAL171_R14_0_Pos)                          /*!< LCD PAL171: R14_0 Mask              */
+#define LCD_PAL171_G14_0_Pos                                  21                                                        /*!< LCD PAL171: G14_0 Position          */
+#define LCD_PAL171_G14_0_Msk                                  (0x1fUL << LCD_PAL171_G14_0_Pos)                          /*!< LCD PAL171: G14_0 Mask              */
+#define LCD_PAL171_B14_0_Pos                                  26                                                        /*!< LCD PAL171: B14_0 Position          */
+#define LCD_PAL171_B14_0_Msk                                  (0x1fUL << LCD_PAL171_B14_0_Pos)                          /*!< LCD PAL171: B14_0 Mask              */
+#define LCD_PAL171_I1_Pos                                     31                                                        /*!< LCD PAL171: I1 Position             */
+#define LCD_PAL171_I1_Msk                                     (0x01UL << LCD_PAL171_I1_Pos)                             /*!< LCD PAL171: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL172  -------------------------------------------
+#define LCD_PAL172_R04_0_Pos                                  0                                                         /*!< LCD PAL172: R04_0 Position          */
+#define LCD_PAL172_R04_0_Msk                                  (0x1fUL << LCD_PAL172_R04_0_Pos)                          /*!< LCD PAL172: R04_0 Mask              */
+#define LCD_PAL172_G04_0_Pos                                  5                                                         /*!< LCD PAL172: G04_0 Position          */
+#define LCD_PAL172_G04_0_Msk                                  (0x1fUL << LCD_PAL172_G04_0_Pos)                          /*!< LCD PAL172: G04_0 Mask              */
+#define LCD_PAL172_B04_0_Pos                                  10                                                        /*!< LCD PAL172: B04_0 Position          */
+#define LCD_PAL172_B04_0_Msk                                  (0x1fUL << LCD_PAL172_B04_0_Pos)                          /*!< LCD PAL172: B04_0 Mask              */
+#define LCD_PAL172_I0_Pos                                     15                                                        /*!< LCD PAL172: I0 Position             */
+#define LCD_PAL172_I0_Msk                                     (0x01UL << LCD_PAL172_I0_Pos)                             /*!< LCD PAL172: I0 Mask                 */
+#define LCD_PAL172_R14_0_Pos                                  16                                                        /*!< LCD PAL172: R14_0 Position          */
+#define LCD_PAL172_R14_0_Msk                                  (0x1fUL << LCD_PAL172_R14_0_Pos)                          /*!< LCD PAL172: R14_0 Mask              */
+#define LCD_PAL172_G14_0_Pos                                  21                                                        /*!< LCD PAL172: G14_0 Position          */
+#define LCD_PAL172_G14_0_Msk                                  (0x1fUL << LCD_PAL172_G14_0_Pos)                          /*!< LCD PAL172: G14_0 Mask              */
+#define LCD_PAL172_B14_0_Pos                                  26                                                        /*!< LCD PAL172: B14_0 Position          */
+#define LCD_PAL172_B14_0_Msk                                  (0x1fUL << LCD_PAL172_B14_0_Pos)                          /*!< LCD PAL172: B14_0 Mask              */
+#define LCD_PAL172_I1_Pos                                     31                                                        /*!< LCD PAL172: I1 Position             */
+#define LCD_PAL172_I1_Msk                                     (0x01UL << LCD_PAL172_I1_Pos)                             /*!< LCD PAL172: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL173  -------------------------------------------
+#define LCD_PAL173_R04_0_Pos                                  0                                                         /*!< LCD PAL173: R04_0 Position          */
+#define LCD_PAL173_R04_0_Msk                                  (0x1fUL << LCD_PAL173_R04_0_Pos)                          /*!< LCD PAL173: R04_0 Mask              */
+#define LCD_PAL173_G04_0_Pos                                  5                                                         /*!< LCD PAL173: G04_0 Position          */
+#define LCD_PAL173_G04_0_Msk                                  (0x1fUL << LCD_PAL173_G04_0_Pos)                          /*!< LCD PAL173: G04_0 Mask              */
+#define LCD_PAL173_B04_0_Pos                                  10                                                        /*!< LCD PAL173: B04_0 Position          */
+#define LCD_PAL173_B04_0_Msk                                  (0x1fUL << LCD_PAL173_B04_0_Pos)                          /*!< LCD PAL173: B04_0 Mask              */
+#define LCD_PAL173_I0_Pos                                     15                                                        /*!< LCD PAL173: I0 Position             */
+#define LCD_PAL173_I0_Msk                                     (0x01UL << LCD_PAL173_I0_Pos)                             /*!< LCD PAL173: I0 Mask                 */
+#define LCD_PAL173_R14_0_Pos                                  16                                                        /*!< LCD PAL173: R14_0 Position          */
+#define LCD_PAL173_R14_0_Msk                                  (0x1fUL << LCD_PAL173_R14_0_Pos)                          /*!< LCD PAL173: R14_0 Mask              */
+#define LCD_PAL173_G14_0_Pos                                  21                                                        /*!< LCD PAL173: G14_0 Position          */
+#define LCD_PAL173_G14_0_Msk                                  (0x1fUL << LCD_PAL173_G14_0_Pos)                          /*!< LCD PAL173: G14_0 Mask              */
+#define LCD_PAL173_B14_0_Pos                                  26                                                        /*!< LCD PAL173: B14_0 Position          */
+#define LCD_PAL173_B14_0_Msk                                  (0x1fUL << LCD_PAL173_B14_0_Pos)                          /*!< LCD PAL173: B14_0 Mask              */
+#define LCD_PAL173_I1_Pos                                     31                                                        /*!< LCD PAL173: I1 Position             */
+#define LCD_PAL173_I1_Msk                                     (0x01UL << LCD_PAL173_I1_Pos)                             /*!< LCD PAL173: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL174  -------------------------------------------
+#define LCD_PAL174_R04_0_Pos                                  0                                                         /*!< LCD PAL174: R04_0 Position          */
+#define LCD_PAL174_R04_0_Msk                                  (0x1fUL << LCD_PAL174_R04_0_Pos)                          /*!< LCD PAL174: R04_0 Mask              */
+#define LCD_PAL174_G04_0_Pos                                  5                                                         /*!< LCD PAL174: G04_0 Position          */
+#define LCD_PAL174_G04_0_Msk                                  (0x1fUL << LCD_PAL174_G04_0_Pos)                          /*!< LCD PAL174: G04_0 Mask              */
+#define LCD_PAL174_B04_0_Pos                                  10                                                        /*!< LCD PAL174: B04_0 Position          */
+#define LCD_PAL174_B04_0_Msk                                  (0x1fUL << LCD_PAL174_B04_0_Pos)                          /*!< LCD PAL174: B04_0 Mask              */
+#define LCD_PAL174_I0_Pos                                     15                                                        /*!< LCD PAL174: I0 Position             */
+#define LCD_PAL174_I0_Msk                                     (0x01UL << LCD_PAL174_I0_Pos)                             /*!< LCD PAL174: I0 Mask                 */
+#define LCD_PAL174_R14_0_Pos                                  16                                                        /*!< LCD PAL174: R14_0 Position          */
+#define LCD_PAL174_R14_0_Msk                                  (0x1fUL << LCD_PAL174_R14_0_Pos)                          /*!< LCD PAL174: R14_0 Mask              */
+#define LCD_PAL174_G14_0_Pos                                  21                                                        /*!< LCD PAL174: G14_0 Position          */
+#define LCD_PAL174_G14_0_Msk                                  (0x1fUL << LCD_PAL174_G14_0_Pos)                          /*!< LCD PAL174: G14_0 Mask              */
+#define LCD_PAL174_B14_0_Pos                                  26                                                        /*!< LCD PAL174: B14_0 Position          */
+#define LCD_PAL174_B14_0_Msk                                  (0x1fUL << LCD_PAL174_B14_0_Pos)                          /*!< LCD PAL174: B14_0 Mask              */
+#define LCD_PAL174_I1_Pos                                     31                                                        /*!< LCD PAL174: I1 Position             */
+#define LCD_PAL174_I1_Msk                                     (0x01UL << LCD_PAL174_I1_Pos)                             /*!< LCD PAL174: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL175  -------------------------------------------
+#define LCD_PAL175_R04_0_Pos                                  0                                                         /*!< LCD PAL175: R04_0 Position          */
+#define LCD_PAL175_R04_0_Msk                                  (0x1fUL << LCD_PAL175_R04_0_Pos)                          /*!< LCD PAL175: R04_0 Mask              */
+#define LCD_PAL175_G04_0_Pos                                  5                                                         /*!< LCD PAL175: G04_0 Position          */
+#define LCD_PAL175_G04_0_Msk                                  (0x1fUL << LCD_PAL175_G04_0_Pos)                          /*!< LCD PAL175: G04_0 Mask              */
+#define LCD_PAL175_B04_0_Pos                                  10                                                        /*!< LCD PAL175: B04_0 Position          */
+#define LCD_PAL175_B04_0_Msk                                  (0x1fUL << LCD_PAL175_B04_0_Pos)                          /*!< LCD PAL175: B04_0 Mask              */
+#define LCD_PAL175_I0_Pos                                     15                                                        /*!< LCD PAL175: I0 Position             */
+#define LCD_PAL175_I0_Msk                                     (0x01UL << LCD_PAL175_I0_Pos)                             /*!< LCD PAL175: I0 Mask                 */
+#define LCD_PAL175_R14_0_Pos                                  16                                                        /*!< LCD PAL175: R14_0 Position          */
+#define LCD_PAL175_R14_0_Msk                                  (0x1fUL << LCD_PAL175_R14_0_Pos)                          /*!< LCD PAL175: R14_0 Mask              */
+#define LCD_PAL175_G14_0_Pos                                  21                                                        /*!< LCD PAL175: G14_0 Position          */
+#define LCD_PAL175_G14_0_Msk                                  (0x1fUL << LCD_PAL175_G14_0_Pos)                          /*!< LCD PAL175: G14_0 Mask              */
+#define LCD_PAL175_B14_0_Pos                                  26                                                        /*!< LCD PAL175: B14_0 Position          */
+#define LCD_PAL175_B14_0_Msk                                  (0x1fUL << LCD_PAL175_B14_0_Pos)                          /*!< LCD PAL175: B14_0 Mask              */
+#define LCD_PAL175_I1_Pos                                     31                                                        /*!< LCD PAL175: I1 Position             */
+#define LCD_PAL175_I1_Msk                                     (0x01UL << LCD_PAL175_I1_Pos)                             /*!< LCD PAL175: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL176  -------------------------------------------
+#define LCD_PAL176_R04_0_Pos                                  0                                                         /*!< LCD PAL176: R04_0 Position          */
+#define LCD_PAL176_R04_0_Msk                                  (0x1fUL << LCD_PAL176_R04_0_Pos)                          /*!< LCD PAL176: R04_0 Mask              */
+#define LCD_PAL176_G04_0_Pos                                  5                                                         /*!< LCD PAL176: G04_0 Position          */
+#define LCD_PAL176_G04_0_Msk                                  (0x1fUL << LCD_PAL176_G04_0_Pos)                          /*!< LCD PAL176: G04_0 Mask              */
+#define LCD_PAL176_B04_0_Pos                                  10                                                        /*!< LCD PAL176: B04_0 Position          */
+#define LCD_PAL176_B04_0_Msk                                  (0x1fUL << LCD_PAL176_B04_0_Pos)                          /*!< LCD PAL176: B04_0 Mask              */
+#define LCD_PAL176_I0_Pos                                     15                                                        /*!< LCD PAL176: I0 Position             */
+#define LCD_PAL176_I0_Msk                                     (0x01UL << LCD_PAL176_I0_Pos)                             /*!< LCD PAL176: I0 Mask                 */
+#define LCD_PAL176_R14_0_Pos                                  16                                                        /*!< LCD PAL176: R14_0 Position          */
+#define LCD_PAL176_R14_0_Msk                                  (0x1fUL << LCD_PAL176_R14_0_Pos)                          /*!< LCD PAL176: R14_0 Mask              */
+#define LCD_PAL176_G14_0_Pos                                  21                                                        /*!< LCD PAL176: G14_0 Position          */
+#define LCD_PAL176_G14_0_Msk                                  (0x1fUL << LCD_PAL176_G14_0_Pos)                          /*!< LCD PAL176: G14_0 Mask              */
+#define LCD_PAL176_B14_0_Pos                                  26                                                        /*!< LCD PAL176: B14_0 Position          */
+#define LCD_PAL176_B14_0_Msk                                  (0x1fUL << LCD_PAL176_B14_0_Pos)                          /*!< LCD PAL176: B14_0 Mask              */
+#define LCD_PAL176_I1_Pos                                     31                                                        /*!< LCD PAL176: I1 Position             */
+#define LCD_PAL176_I1_Msk                                     (0x01UL << LCD_PAL176_I1_Pos)                             /*!< LCD PAL176: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL177  -------------------------------------------
+#define LCD_PAL177_R04_0_Pos                                  0                                                         /*!< LCD PAL177: R04_0 Position          */
+#define LCD_PAL177_R04_0_Msk                                  (0x1fUL << LCD_PAL177_R04_0_Pos)                          /*!< LCD PAL177: R04_0 Mask              */
+#define LCD_PAL177_G04_0_Pos                                  5                                                         /*!< LCD PAL177: G04_0 Position          */
+#define LCD_PAL177_G04_0_Msk                                  (0x1fUL << LCD_PAL177_G04_0_Pos)                          /*!< LCD PAL177: G04_0 Mask              */
+#define LCD_PAL177_B04_0_Pos                                  10                                                        /*!< LCD PAL177: B04_0 Position          */
+#define LCD_PAL177_B04_0_Msk                                  (0x1fUL << LCD_PAL177_B04_0_Pos)                          /*!< LCD PAL177: B04_0 Mask              */
+#define LCD_PAL177_I0_Pos                                     15                                                        /*!< LCD PAL177: I0 Position             */
+#define LCD_PAL177_I0_Msk                                     (0x01UL << LCD_PAL177_I0_Pos)                             /*!< LCD PAL177: I0 Mask                 */
+#define LCD_PAL177_R14_0_Pos                                  16                                                        /*!< LCD PAL177: R14_0 Position          */
+#define LCD_PAL177_R14_0_Msk                                  (0x1fUL << LCD_PAL177_R14_0_Pos)                          /*!< LCD PAL177: R14_0 Mask              */
+#define LCD_PAL177_G14_0_Pos                                  21                                                        /*!< LCD PAL177: G14_0 Position          */
+#define LCD_PAL177_G14_0_Msk                                  (0x1fUL << LCD_PAL177_G14_0_Pos)                          /*!< LCD PAL177: G14_0 Mask              */
+#define LCD_PAL177_B14_0_Pos                                  26                                                        /*!< LCD PAL177: B14_0 Position          */
+#define LCD_PAL177_B14_0_Msk                                  (0x1fUL << LCD_PAL177_B14_0_Pos)                          /*!< LCD PAL177: B14_0 Mask              */
+#define LCD_PAL177_I1_Pos                                     31                                                        /*!< LCD PAL177: I1 Position             */
+#define LCD_PAL177_I1_Msk                                     (0x01UL << LCD_PAL177_I1_Pos)                             /*!< LCD PAL177: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL178  -------------------------------------------
+#define LCD_PAL178_R04_0_Pos                                  0                                                         /*!< LCD PAL178: R04_0 Position          */
+#define LCD_PAL178_R04_0_Msk                                  (0x1fUL << LCD_PAL178_R04_0_Pos)                          /*!< LCD PAL178: R04_0 Mask              */
+#define LCD_PAL178_G04_0_Pos                                  5                                                         /*!< LCD PAL178: G04_0 Position          */
+#define LCD_PAL178_G04_0_Msk                                  (0x1fUL << LCD_PAL178_G04_0_Pos)                          /*!< LCD PAL178: G04_0 Mask              */
+#define LCD_PAL178_B04_0_Pos                                  10                                                        /*!< LCD PAL178: B04_0 Position          */
+#define LCD_PAL178_B04_0_Msk                                  (0x1fUL << LCD_PAL178_B04_0_Pos)                          /*!< LCD PAL178: B04_0 Mask              */
+#define LCD_PAL178_I0_Pos                                     15                                                        /*!< LCD PAL178: I0 Position             */
+#define LCD_PAL178_I0_Msk                                     (0x01UL << LCD_PAL178_I0_Pos)                             /*!< LCD PAL178: I0 Mask                 */
+#define LCD_PAL178_R14_0_Pos                                  16                                                        /*!< LCD PAL178: R14_0 Position          */
+#define LCD_PAL178_R14_0_Msk                                  (0x1fUL << LCD_PAL178_R14_0_Pos)                          /*!< LCD PAL178: R14_0 Mask              */
+#define LCD_PAL178_G14_0_Pos                                  21                                                        /*!< LCD PAL178: G14_0 Position          */
+#define LCD_PAL178_G14_0_Msk                                  (0x1fUL << LCD_PAL178_G14_0_Pos)                          /*!< LCD PAL178: G14_0 Mask              */
+#define LCD_PAL178_B14_0_Pos                                  26                                                        /*!< LCD PAL178: B14_0 Position          */
+#define LCD_PAL178_B14_0_Msk                                  (0x1fUL << LCD_PAL178_B14_0_Pos)                          /*!< LCD PAL178: B14_0 Mask              */
+#define LCD_PAL178_I1_Pos                                     31                                                        /*!< LCD PAL178: I1 Position             */
+#define LCD_PAL178_I1_Msk                                     (0x01UL << LCD_PAL178_I1_Pos)                             /*!< LCD PAL178: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL179  -------------------------------------------
+#define LCD_PAL179_R04_0_Pos                                  0                                                         /*!< LCD PAL179: R04_0 Position          */
+#define LCD_PAL179_R04_0_Msk                                  (0x1fUL << LCD_PAL179_R04_0_Pos)                          /*!< LCD PAL179: R04_0 Mask              */
+#define LCD_PAL179_G04_0_Pos                                  5                                                         /*!< LCD PAL179: G04_0 Position          */
+#define LCD_PAL179_G04_0_Msk                                  (0x1fUL << LCD_PAL179_G04_0_Pos)                          /*!< LCD PAL179: G04_0 Mask              */
+#define LCD_PAL179_B04_0_Pos                                  10                                                        /*!< LCD PAL179: B04_0 Position          */
+#define LCD_PAL179_B04_0_Msk                                  (0x1fUL << LCD_PAL179_B04_0_Pos)                          /*!< LCD PAL179: B04_0 Mask              */
+#define LCD_PAL179_I0_Pos                                     15                                                        /*!< LCD PAL179: I0 Position             */
+#define LCD_PAL179_I0_Msk                                     (0x01UL << LCD_PAL179_I0_Pos)                             /*!< LCD PAL179: I0 Mask                 */
+#define LCD_PAL179_R14_0_Pos                                  16                                                        /*!< LCD PAL179: R14_0 Position          */
+#define LCD_PAL179_R14_0_Msk                                  (0x1fUL << LCD_PAL179_R14_0_Pos)                          /*!< LCD PAL179: R14_0 Mask              */
+#define LCD_PAL179_G14_0_Pos                                  21                                                        /*!< LCD PAL179: G14_0 Position          */
+#define LCD_PAL179_G14_0_Msk                                  (0x1fUL << LCD_PAL179_G14_0_Pos)                          /*!< LCD PAL179: G14_0 Mask              */
+#define LCD_PAL179_B14_0_Pos                                  26                                                        /*!< LCD PAL179: B14_0 Position          */
+#define LCD_PAL179_B14_0_Msk                                  (0x1fUL << LCD_PAL179_B14_0_Pos)                          /*!< LCD PAL179: B14_0 Mask              */
+#define LCD_PAL179_I1_Pos                                     31                                                        /*!< LCD PAL179: I1 Position             */
+#define LCD_PAL179_I1_Msk                                     (0x01UL << LCD_PAL179_I1_Pos)                             /*!< LCD PAL179: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL180  -------------------------------------------
+#define LCD_PAL180_R04_0_Pos                                  0                                                         /*!< LCD PAL180: R04_0 Position          */
+#define LCD_PAL180_R04_0_Msk                                  (0x1fUL << LCD_PAL180_R04_0_Pos)                          /*!< LCD PAL180: R04_0 Mask              */
+#define LCD_PAL180_G04_0_Pos                                  5                                                         /*!< LCD PAL180: G04_0 Position          */
+#define LCD_PAL180_G04_0_Msk                                  (0x1fUL << LCD_PAL180_G04_0_Pos)                          /*!< LCD PAL180: G04_0 Mask              */
+#define LCD_PAL180_B04_0_Pos                                  10                                                        /*!< LCD PAL180: B04_0 Position          */
+#define LCD_PAL180_B04_0_Msk                                  (0x1fUL << LCD_PAL180_B04_0_Pos)                          /*!< LCD PAL180: B04_0 Mask              */
+#define LCD_PAL180_I0_Pos                                     15                                                        /*!< LCD PAL180: I0 Position             */
+#define LCD_PAL180_I0_Msk                                     (0x01UL << LCD_PAL180_I0_Pos)                             /*!< LCD PAL180: I0 Mask                 */
+#define LCD_PAL180_R14_0_Pos                                  16                                                        /*!< LCD PAL180: R14_0 Position          */
+#define LCD_PAL180_R14_0_Msk                                  (0x1fUL << LCD_PAL180_R14_0_Pos)                          /*!< LCD PAL180: R14_0 Mask              */
+#define LCD_PAL180_G14_0_Pos                                  21                                                        /*!< LCD PAL180: G14_0 Position          */
+#define LCD_PAL180_G14_0_Msk                                  (0x1fUL << LCD_PAL180_G14_0_Pos)                          /*!< LCD PAL180: G14_0 Mask              */
+#define LCD_PAL180_B14_0_Pos                                  26                                                        /*!< LCD PAL180: B14_0 Position          */
+#define LCD_PAL180_B14_0_Msk                                  (0x1fUL << LCD_PAL180_B14_0_Pos)                          /*!< LCD PAL180: B14_0 Mask              */
+#define LCD_PAL180_I1_Pos                                     31                                                        /*!< LCD PAL180: I1 Position             */
+#define LCD_PAL180_I1_Msk                                     (0x01UL << LCD_PAL180_I1_Pos)                             /*!< LCD PAL180: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL181  -------------------------------------------
+#define LCD_PAL181_R04_0_Pos                                  0                                                         /*!< LCD PAL181: R04_0 Position          */
+#define LCD_PAL181_R04_0_Msk                                  (0x1fUL << LCD_PAL181_R04_0_Pos)                          /*!< LCD PAL181: R04_0 Mask              */
+#define LCD_PAL181_G04_0_Pos                                  5                                                         /*!< LCD PAL181: G04_0 Position          */
+#define LCD_PAL181_G04_0_Msk                                  (0x1fUL << LCD_PAL181_G04_0_Pos)                          /*!< LCD PAL181: G04_0 Mask              */
+#define LCD_PAL181_B04_0_Pos                                  10                                                        /*!< LCD PAL181: B04_0 Position          */
+#define LCD_PAL181_B04_0_Msk                                  (0x1fUL << LCD_PAL181_B04_0_Pos)                          /*!< LCD PAL181: B04_0 Mask              */
+#define LCD_PAL181_I0_Pos                                     15                                                        /*!< LCD PAL181: I0 Position             */
+#define LCD_PAL181_I0_Msk                                     (0x01UL << LCD_PAL181_I0_Pos)                             /*!< LCD PAL181: I0 Mask                 */
+#define LCD_PAL181_R14_0_Pos                                  16                                                        /*!< LCD PAL181: R14_0 Position          */
+#define LCD_PAL181_R14_0_Msk                                  (0x1fUL << LCD_PAL181_R14_0_Pos)                          /*!< LCD PAL181: R14_0 Mask              */
+#define LCD_PAL181_G14_0_Pos                                  21                                                        /*!< LCD PAL181: G14_0 Position          */
+#define LCD_PAL181_G14_0_Msk                                  (0x1fUL << LCD_PAL181_G14_0_Pos)                          /*!< LCD PAL181: G14_0 Mask              */
+#define LCD_PAL181_B14_0_Pos                                  26                                                        /*!< LCD PAL181: B14_0 Position          */
+#define LCD_PAL181_B14_0_Msk                                  (0x1fUL << LCD_PAL181_B14_0_Pos)                          /*!< LCD PAL181: B14_0 Mask              */
+#define LCD_PAL181_I1_Pos                                     31                                                        /*!< LCD PAL181: I1 Position             */
+#define LCD_PAL181_I1_Msk                                     (0x01UL << LCD_PAL181_I1_Pos)                             /*!< LCD PAL181: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL182  -------------------------------------------
+#define LCD_PAL182_R04_0_Pos                                  0                                                         /*!< LCD PAL182: R04_0 Position          */
+#define LCD_PAL182_R04_0_Msk                                  (0x1fUL << LCD_PAL182_R04_0_Pos)                          /*!< LCD PAL182: R04_0 Mask              */
+#define LCD_PAL182_G04_0_Pos                                  5                                                         /*!< LCD PAL182: G04_0 Position          */
+#define LCD_PAL182_G04_0_Msk                                  (0x1fUL << LCD_PAL182_G04_0_Pos)                          /*!< LCD PAL182: G04_0 Mask              */
+#define LCD_PAL182_B04_0_Pos                                  10                                                        /*!< LCD PAL182: B04_0 Position          */
+#define LCD_PAL182_B04_0_Msk                                  (0x1fUL << LCD_PAL182_B04_0_Pos)                          /*!< LCD PAL182: B04_0 Mask              */
+#define LCD_PAL182_I0_Pos                                     15                                                        /*!< LCD PAL182: I0 Position             */
+#define LCD_PAL182_I0_Msk                                     (0x01UL << LCD_PAL182_I0_Pos)                             /*!< LCD PAL182: I0 Mask                 */
+#define LCD_PAL182_R14_0_Pos                                  16                                                        /*!< LCD PAL182: R14_0 Position          */
+#define LCD_PAL182_R14_0_Msk                                  (0x1fUL << LCD_PAL182_R14_0_Pos)                          /*!< LCD PAL182: R14_0 Mask              */
+#define LCD_PAL182_G14_0_Pos                                  21                                                        /*!< LCD PAL182: G14_0 Position          */
+#define LCD_PAL182_G14_0_Msk                                  (0x1fUL << LCD_PAL182_G14_0_Pos)                          /*!< LCD PAL182: G14_0 Mask              */
+#define LCD_PAL182_B14_0_Pos                                  26                                                        /*!< LCD PAL182: B14_0 Position          */
+#define LCD_PAL182_B14_0_Msk                                  (0x1fUL << LCD_PAL182_B14_0_Pos)                          /*!< LCD PAL182: B14_0 Mask              */
+#define LCD_PAL182_I1_Pos                                     31                                                        /*!< LCD PAL182: I1 Position             */
+#define LCD_PAL182_I1_Msk                                     (0x01UL << LCD_PAL182_I1_Pos)                             /*!< LCD PAL182: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL183  -------------------------------------------
+#define LCD_PAL183_R04_0_Pos                                  0                                                         /*!< LCD PAL183: R04_0 Position          */
+#define LCD_PAL183_R04_0_Msk                                  (0x1fUL << LCD_PAL183_R04_0_Pos)                          /*!< LCD PAL183: R04_0 Mask              */
+#define LCD_PAL183_G04_0_Pos                                  5                                                         /*!< LCD PAL183: G04_0 Position          */
+#define LCD_PAL183_G04_0_Msk                                  (0x1fUL << LCD_PAL183_G04_0_Pos)                          /*!< LCD PAL183: G04_0 Mask              */
+#define LCD_PAL183_B04_0_Pos                                  10                                                        /*!< LCD PAL183: B04_0 Position          */
+#define LCD_PAL183_B04_0_Msk                                  (0x1fUL << LCD_PAL183_B04_0_Pos)                          /*!< LCD PAL183: B04_0 Mask              */
+#define LCD_PAL183_I0_Pos                                     15                                                        /*!< LCD PAL183: I0 Position             */
+#define LCD_PAL183_I0_Msk                                     (0x01UL << LCD_PAL183_I0_Pos)                             /*!< LCD PAL183: I0 Mask                 */
+#define LCD_PAL183_R14_0_Pos                                  16                                                        /*!< LCD PAL183: R14_0 Position          */
+#define LCD_PAL183_R14_0_Msk                                  (0x1fUL << LCD_PAL183_R14_0_Pos)                          /*!< LCD PAL183: R14_0 Mask              */
+#define LCD_PAL183_G14_0_Pos                                  21                                                        /*!< LCD PAL183: G14_0 Position          */
+#define LCD_PAL183_G14_0_Msk                                  (0x1fUL << LCD_PAL183_G14_0_Pos)                          /*!< LCD PAL183: G14_0 Mask              */
+#define LCD_PAL183_B14_0_Pos                                  26                                                        /*!< LCD PAL183: B14_0 Position          */
+#define LCD_PAL183_B14_0_Msk                                  (0x1fUL << LCD_PAL183_B14_0_Pos)                          /*!< LCD PAL183: B14_0 Mask              */
+#define LCD_PAL183_I1_Pos                                     31                                                        /*!< LCD PAL183: I1 Position             */
+#define LCD_PAL183_I1_Msk                                     (0x01UL << LCD_PAL183_I1_Pos)                             /*!< LCD PAL183: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL184  -------------------------------------------
+#define LCD_PAL184_R04_0_Pos                                  0                                                         /*!< LCD PAL184: R04_0 Position          */
+#define LCD_PAL184_R04_0_Msk                                  (0x1fUL << LCD_PAL184_R04_0_Pos)                          /*!< LCD PAL184: R04_0 Mask              */
+#define LCD_PAL184_G04_0_Pos                                  5                                                         /*!< LCD PAL184: G04_0 Position          */
+#define LCD_PAL184_G04_0_Msk                                  (0x1fUL << LCD_PAL184_G04_0_Pos)                          /*!< LCD PAL184: G04_0 Mask              */
+#define LCD_PAL184_B04_0_Pos                                  10                                                        /*!< LCD PAL184: B04_0 Position          */
+#define LCD_PAL184_B04_0_Msk                                  (0x1fUL << LCD_PAL184_B04_0_Pos)                          /*!< LCD PAL184: B04_0 Mask              */
+#define LCD_PAL184_I0_Pos                                     15                                                        /*!< LCD PAL184: I0 Position             */
+#define LCD_PAL184_I0_Msk                                     (0x01UL << LCD_PAL184_I0_Pos)                             /*!< LCD PAL184: I0 Mask                 */
+#define LCD_PAL184_R14_0_Pos                                  16                                                        /*!< LCD PAL184: R14_0 Position          */
+#define LCD_PAL184_R14_0_Msk                                  (0x1fUL << LCD_PAL184_R14_0_Pos)                          /*!< LCD PAL184: R14_0 Mask              */
+#define LCD_PAL184_G14_0_Pos                                  21                                                        /*!< LCD PAL184: G14_0 Position          */
+#define LCD_PAL184_G14_0_Msk                                  (0x1fUL << LCD_PAL184_G14_0_Pos)                          /*!< LCD PAL184: G14_0 Mask              */
+#define LCD_PAL184_B14_0_Pos                                  26                                                        /*!< LCD PAL184: B14_0 Position          */
+#define LCD_PAL184_B14_0_Msk                                  (0x1fUL << LCD_PAL184_B14_0_Pos)                          /*!< LCD PAL184: B14_0 Mask              */
+#define LCD_PAL184_I1_Pos                                     31                                                        /*!< LCD PAL184: I1 Position             */
+#define LCD_PAL184_I1_Msk                                     (0x01UL << LCD_PAL184_I1_Pos)                             /*!< LCD PAL184: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL185  -------------------------------------------
+#define LCD_PAL185_R04_0_Pos                                  0                                                         /*!< LCD PAL185: R04_0 Position          */
+#define LCD_PAL185_R04_0_Msk                                  (0x1fUL << LCD_PAL185_R04_0_Pos)                          /*!< LCD PAL185: R04_0 Mask              */
+#define LCD_PAL185_G04_0_Pos                                  5                                                         /*!< LCD PAL185: G04_0 Position          */
+#define LCD_PAL185_G04_0_Msk                                  (0x1fUL << LCD_PAL185_G04_0_Pos)                          /*!< LCD PAL185: G04_0 Mask              */
+#define LCD_PAL185_B04_0_Pos                                  10                                                        /*!< LCD PAL185: B04_0 Position          */
+#define LCD_PAL185_B04_0_Msk                                  (0x1fUL << LCD_PAL185_B04_0_Pos)                          /*!< LCD PAL185: B04_0 Mask              */
+#define LCD_PAL185_I0_Pos                                     15                                                        /*!< LCD PAL185: I0 Position             */
+#define LCD_PAL185_I0_Msk                                     (0x01UL << LCD_PAL185_I0_Pos)                             /*!< LCD PAL185: I0 Mask                 */
+#define LCD_PAL185_R14_0_Pos                                  16                                                        /*!< LCD PAL185: R14_0 Position          */
+#define LCD_PAL185_R14_0_Msk                                  (0x1fUL << LCD_PAL185_R14_0_Pos)                          /*!< LCD PAL185: R14_0 Mask              */
+#define LCD_PAL185_G14_0_Pos                                  21                                                        /*!< LCD PAL185: G14_0 Position          */
+#define LCD_PAL185_G14_0_Msk                                  (0x1fUL << LCD_PAL185_G14_0_Pos)                          /*!< LCD PAL185: G14_0 Mask              */
+#define LCD_PAL185_B14_0_Pos                                  26                                                        /*!< LCD PAL185: B14_0 Position          */
+#define LCD_PAL185_B14_0_Msk                                  (0x1fUL << LCD_PAL185_B14_0_Pos)                          /*!< LCD PAL185: B14_0 Mask              */
+#define LCD_PAL185_I1_Pos                                     31                                                        /*!< LCD PAL185: I1 Position             */
+#define LCD_PAL185_I1_Msk                                     (0x01UL << LCD_PAL185_I1_Pos)                             /*!< LCD PAL185: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL186  -------------------------------------------
+#define LCD_PAL186_R04_0_Pos                                  0                                                         /*!< LCD PAL186: R04_0 Position          */
+#define LCD_PAL186_R04_0_Msk                                  (0x1fUL << LCD_PAL186_R04_0_Pos)                          /*!< LCD PAL186: R04_0 Mask              */
+#define LCD_PAL186_G04_0_Pos                                  5                                                         /*!< LCD PAL186: G04_0 Position          */
+#define LCD_PAL186_G04_0_Msk                                  (0x1fUL << LCD_PAL186_G04_0_Pos)                          /*!< LCD PAL186: G04_0 Mask              */
+#define LCD_PAL186_B04_0_Pos                                  10                                                        /*!< LCD PAL186: B04_0 Position          */
+#define LCD_PAL186_B04_0_Msk                                  (0x1fUL << LCD_PAL186_B04_0_Pos)                          /*!< LCD PAL186: B04_0 Mask              */
+#define LCD_PAL186_I0_Pos                                     15                                                        /*!< LCD PAL186: I0 Position             */
+#define LCD_PAL186_I0_Msk                                     (0x01UL << LCD_PAL186_I0_Pos)                             /*!< LCD PAL186: I0 Mask                 */
+#define LCD_PAL186_R14_0_Pos                                  16                                                        /*!< LCD PAL186: R14_0 Position          */
+#define LCD_PAL186_R14_0_Msk                                  (0x1fUL << LCD_PAL186_R14_0_Pos)                          /*!< LCD PAL186: R14_0 Mask              */
+#define LCD_PAL186_G14_0_Pos                                  21                                                        /*!< LCD PAL186: G14_0 Position          */
+#define LCD_PAL186_G14_0_Msk                                  (0x1fUL << LCD_PAL186_G14_0_Pos)                          /*!< LCD PAL186: G14_0 Mask              */
+#define LCD_PAL186_B14_0_Pos                                  26                                                        /*!< LCD PAL186: B14_0 Position          */
+#define LCD_PAL186_B14_0_Msk                                  (0x1fUL << LCD_PAL186_B14_0_Pos)                          /*!< LCD PAL186: B14_0 Mask              */
+#define LCD_PAL186_I1_Pos                                     31                                                        /*!< LCD PAL186: I1 Position             */
+#define LCD_PAL186_I1_Msk                                     (0x01UL << LCD_PAL186_I1_Pos)                             /*!< LCD PAL186: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL187  -------------------------------------------
+#define LCD_PAL187_R04_0_Pos                                  0                                                         /*!< LCD PAL187: R04_0 Position          */
+#define LCD_PAL187_R04_0_Msk                                  (0x1fUL << LCD_PAL187_R04_0_Pos)                          /*!< LCD PAL187: R04_0 Mask              */
+#define LCD_PAL187_G04_0_Pos                                  5                                                         /*!< LCD PAL187: G04_0 Position          */
+#define LCD_PAL187_G04_0_Msk                                  (0x1fUL << LCD_PAL187_G04_0_Pos)                          /*!< LCD PAL187: G04_0 Mask              */
+#define LCD_PAL187_B04_0_Pos                                  10                                                        /*!< LCD PAL187: B04_0 Position          */
+#define LCD_PAL187_B04_0_Msk                                  (0x1fUL << LCD_PAL187_B04_0_Pos)                          /*!< LCD PAL187: B04_0 Mask              */
+#define LCD_PAL187_I0_Pos                                     15                                                        /*!< LCD PAL187: I0 Position             */
+#define LCD_PAL187_I0_Msk                                     (0x01UL << LCD_PAL187_I0_Pos)                             /*!< LCD PAL187: I0 Mask                 */
+#define LCD_PAL187_R14_0_Pos                                  16                                                        /*!< LCD PAL187: R14_0 Position          */
+#define LCD_PAL187_R14_0_Msk                                  (0x1fUL << LCD_PAL187_R14_0_Pos)                          /*!< LCD PAL187: R14_0 Mask              */
+#define LCD_PAL187_G14_0_Pos                                  21                                                        /*!< LCD PAL187: G14_0 Position          */
+#define LCD_PAL187_G14_0_Msk                                  (0x1fUL << LCD_PAL187_G14_0_Pos)                          /*!< LCD PAL187: G14_0 Mask              */
+#define LCD_PAL187_B14_0_Pos                                  26                                                        /*!< LCD PAL187: B14_0 Position          */
+#define LCD_PAL187_B14_0_Msk                                  (0x1fUL << LCD_PAL187_B14_0_Pos)                          /*!< LCD PAL187: B14_0 Mask              */
+#define LCD_PAL187_I1_Pos                                     31                                                        /*!< LCD PAL187: I1 Position             */
+#define LCD_PAL187_I1_Msk                                     (0x01UL << LCD_PAL187_I1_Pos)                             /*!< LCD PAL187: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL188  -------------------------------------------
+#define LCD_PAL188_R04_0_Pos                                  0                                                         /*!< LCD PAL188: R04_0 Position          */
+#define LCD_PAL188_R04_0_Msk                                  (0x1fUL << LCD_PAL188_R04_0_Pos)                          /*!< LCD PAL188: R04_0 Mask              */
+#define LCD_PAL188_G04_0_Pos                                  5                                                         /*!< LCD PAL188: G04_0 Position          */
+#define LCD_PAL188_G04_0_Msk                                  (0x1fUL << LCD_PAL188_G04_0_Pos)                          /*!< LCD PAL188: G04_0 Mask              */
+#define LCD_PAL188_B04_0_Pos                                  10                                                        /*!< LCD PAL188: B04_0 Position          */
+#define LCD_PAL188_B04_0_Msk                                  (0x1fUL << LCD_PAL188_B04_0_Pos)                          /*!< LCD PAL188: B04_0 Mask              */
+#define LCD_PAL188_I0_Pos                                     15                                                        /*!< LCD PAL188: I0 Position             */
+#define LCD_PAL188_I0_Msk                                     (0x01UL << LCD_PAL188_I0_Pos)                             /*!< LCD PAL188: I0 Mask                 */
+#define LCD_PAL188_R14_0_Pos                                  16                                                        /*!< LCD PAL188: R14_0 Position          */
+#define LCD_PAL188_R14_0_Msk                                  (0x1fUL << LCD_PAL188_R14_0_Pos)                          /*!< LCD PAL188: R14_0 Mask              */
+#define LCD_PAL188_G14_0_Pos                                  21                                                        /*!< LCD PAL188: G14_0 Position          */
+#define LCD_PAL188_G14_0_Msk                                  (0x1fUL << LCD_PAL188_G14_0_Pos)                          /*!< LCD PAL188: G14_0 Mask              */
+#define LCD_PAL188_B14_0_Pos                                  26                                                        /*!< LCD PAL188: B14_0 Position          */
+#define LCD_PAL188_B14_0_Msk                                  (0x1fUL << LCD_PAL188_B14_0_Pos)                          /*!< LCD PAL188: B14_0 Mask              */
+#define LCD_PAL188_I1_Pos                                     31                                                        /*!< LCD PAL188: I1 Position             */
+#define LCD_PAL188_I1_Msk                                     (0x01UL << LCD_PAL188_I1_Pos)                             /*!< LCD PAL188: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL189  -------------------------------------------
+#define LCD_PAL189_R04_0_Pos                                  0                                                         /*!< LCD PAL189: R04_0 Position          */
+#define LCD_PAL189_R04_0_Msk                                  (0x1fUL << LCD_PAL189_R04_0_Pos)                          /*!< LCD PAL189: R04_0 Mask              */
+#define LCD_PAL189_G04_0_Pos                                  5                                                         /*!< LCD PAL189: G04_0 Position          */
+#define LCD_PAL189_G04_0_Msk                                  (0x1fUL << LCD_PAL189_G04_0_Pos)                          /*!< LCD PAL189: G04_0 Mask              */
+#define LCD_PAL189_B04_0_Pos                                  10                                                        /*!< LCD PAL189: B04_0 Position          */
+#define LCD_PAL189_B04_0_Msk                                  (0x1fUL << LCD_PAL189_B04_0_Pos)                          /*!< LCD PAL189: B04_0 Mask              */
+#define LCD_PAL189_I0_Pos                                     15                                                        /*!< LCD PAL189: I0 Position             */
+#define LCD_PAL189_I0_Msk                                     (0x01UL << LCD_PAL189_I0_Pos)                             /*!< LCD PAL189: I0 Mask                 */
+#define LCD_PAL189_R14_0_Pos                                  16                                                        /*!< LCD PAL189: R14_0 Position          */
+#define LCD_PAL189_R14_0_Msk                                  (0x1fUL << LCD_PAL189_R14_0_Pos)                          /*!< LCD PAL189: R14_0 Mask              */
+#define LCD_PAL189_G14_0_Pos                                  21                                                        /*!< LCD PAL189: G14_0 Position          */
+#define LCD_PAL189_G14_0_Msk                                  (0x1fUL << LCD_PAL189_G14_0_Pos)                          /*!< LCD PAL189: G14_0 Mask              */
+#define LCD_PAL189_B14_0_Pos                                  26                                                        /*!< LCD PAL189: B14_0 Position          */
+#define LCD_PAL189_B14_0_Msk                                  (0x1fUL << LCD_PAL189_B14_0_Pos)                          /*!< LCD PAL189: B14_0 Mask              */
+#define LCD_PAL189_I1_Pos                                     31                                                        /*!< LCD PAL189: I1 Position             */
+#define LCD_PAL189_I1_Msk                                     (0x01UL << LCD_PAL189_I1_Pos)                             /*!< LCD PAL189: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL190  -------------------------------------------
+#define LCD_PAL190_R04_0_Pos                                  0                                                         /*!< LCD PAL190: R04_0 Position          */
+#define LCD_PAL190_R04_0_Msk                                  (0x1fUL << LCD_PAL190_R04_0_Pos)                          /*!< LCD PAL190: R04_0 Mask              */
+#define LCD_PAL190_G04_0_Pos                                  5                                                         /*!< LCD PAL190: G04_0 Position          */
+#define LCD_PAL190_G04_0_Msk                                  (0x1fUL << LCD_PAL190_G04_0_Pos)                          /*!< LCD PAL190: G04_0 Mask              */
+#define LCD_PAL190_B04_0_Pos                                  10                                                        /*!< LCD PAL190: B04_0 Position          */
+#define LCD_PAL190_B04_0_Msk                                  (0x1fUL << LCD_PAL190_B04_0_Pos)                          /*!< LCD PAL190: B04_0 Mask              */
+#define LCD_PAL190_I0_Pos                                     15                                                        /*!< LCD PAL190: I0 Position             */
+#define LCD_PAL190_I0_Msk                                     (0x01UL << LCD_PAL190_I0_Pos)                             /*!< LCD PAL190: I0 Mask                 */
+#define LCD_PAL190_R14_0_Pos                                  16                                                        /*!< LCD PAL190: R14_0 Position          */
+#define LCD_PAL190_R14_0_Msk                                  (0x1fUL << LCD_PAL190_R14_0_Pos)                          /*!< LCD PAL190: R14_0 Mask              */
+#define LCD_PAL190_G14_0_Pos                                  21                                                        /*!< LCD PAL190: G14_0 Position          */
+#define LCD_PAL190_G14_0_Msk                                  (0x1fUL << LCD_PAL190_G14_0_Pos)                          /*!< LCD PAL190: G14_0 Mask              */
+#define LCD_PAL190_B14_0_Pos                                  26                                                        /*!< LCD PAL190: B14_0 Position          */
+#define LCD_PAL190_B14_0_Msk                                  (0x1fUL << LCD_PAL190_B14_0_Pos)                          /*!< LCD PAL190: B14_0 Mask              */
+#define LCD_PAL190_I1_Pos                                     31                                                        /*!< LCD PAL190: I1 Position             */
+#define LCD_PAL190_I1_Msk                                     (0x01UL << LCD_PAL190_I1_Pos)                             /*!< LCD PAL190: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL191  -------------------------------------------
+#define LCD_PAL191_R04_0_Pos                                  0                                                         /*!< LCD PAL191: R04_0 Position          */
+#define LCD_PAL191_R04_0_Msk                                  (0x1fUL << LCD_PAL191_R04_0_Pos)                          /*!< LCD PAL191: R04_0 Mask              */
+#define LCD_PAL191_G04_0_Pos                                  5                                                         /*!< LCD PAL191: G04_0 Position          */
+#define LCD_PAL191_G04_0_Msk                                  (0x1fUL << LCD_PAL191_G04_0_Pos)                          /*!< LCD PAL191: G04_0 Mask              */
+#define LCD_PAL191_B04_0_Pos                                  10                                                        /*!< LCD PAL191: B04_0 Position          */
+#define LCD_PAL191_B04_0_Msk                                  (0x1fUL << LCD_PAL191_B04_0_Pos)                          /*!< LCD PAL191: B04_0 Mask              */
+#define LCD_PAL191_I0_Pos                                     15                                                        /*!< LCD PAL191: I0 Position             */
+#define LCD_PAL191_I0_Msk                                     (0x01UL << LCD_PAL191_I0_Pos)                             /*!< LCD PAL191: I0 Mask                 */
+#define LCD_PAL191_R14_0_Pos                                  16                                                        /*!< LCD PAL191: R14_0 Position          */
+#define LCD_PAL191_R14_0_Msk                                  (0x1fUL << LCD_PAL191_R14_0_Pos)                          /*!< LCD PAL191: R14_0 Mask              */
+#define LCD_PAL191_G14_0_Pos                                  21                                                        /*!< LCD PAL191: G14_0 Position          */
+#define LCD_PAL191_G14_0_Msk                                  (0x1fUL << LCD_PAL191_G14_0_Pos)                          /*!< LCD PAL191: G14_0 Mask              */
+#define LCD_PAL191_B14_0_Pos                                  26                                                        /*!< LCD PAL191: B14_0 Position          */
+#define LCD_PAL191_B14_0_Msk                                  (0x1fUL << LCD_PAL191_B14_0_Pos)                          /*!< LCD PAL191: B14_0 Mask              */
+#define LCD_PAL191_I1_Pos                                     31                                                        /*!< LCD PAL191: I1 Position             */
+#define LCD_PAL191_I1_Msk                                     (0x01UL << LCD_PAL191_I1_Pos)                             /*!< LCD PAL191: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL192  -------------------------------------------
+#define LCD_PAL192_R04_0_Pos                                  0                                                         /*!< LCD PAL192: R04_0 Position          */
+#define LCD_PAL192_R04_0_Msk                                  (0x1fUL << LCD_PAL192_R04_0_Pos)                          /*!< LCD PAL192: R04_0 Mask              */
+#define LCD_PAL192_G04_0_Pos                                  5                                                         /*!< LCD PAL192: G04_0 Position          */
+#define LCD_PAL192_G04_0_Msk                                  (0x1fUL << LCD_PAL192_G04_0_Pos)                          /*!< LCD PAL192: G04_0 Mask              */
+#define LCD_PAL192_B04_0_Pos                                  10                                                        /*!< LCD PAL192: B04_0 Position          */
+#define LCD_PAL192_B04_0_Msk                                  (0x1fUL << LCD_PAL192_B04_0_Pos)                          /*!< LCD PAL192: B04_0 Mask              */
+#define LCD_PAL192_I0_Pos                                     15                                                        /*!< LCD PAL192: I0 Position             */
+#define LCD_PAL192_I0_Msk                                     (0x01UL << LCD_PAL192_I0_Pos)                             /*!< LCD PAL192: I0 Mask                 */
+#define LCD_PAL192_R14_0_Pos                                  16                                                        /*!< LCD PAL192: R14_0 Position          */
+#define LCD_PAL192_R14_0_Msk                                  (0x1fUL << LCD_PAL192_R14_0_Pos)                          /*!< LCD PAL192: R14_0 Mask              */
+#define LCD_PAL192_G14_0_Pos                                  21                                                        /*!< LCD PAL192: G14_0 Position          */
+#define LCD_PAL192_G14_0_Msk                                  (0x1fUL << LCD_PAL192_G14_0_Pos)                          /*!< LCD PAL192: G14_0 Mask              */
+#define LCD_PAL192_B14_0_Pos                                  26                                                        /*!< LCD PAL192: B14_0 Position          */
+#define LCD_PAL192_B14_0_Msk                                  (0x1fUL << LCD_PAL192_B14_0_Pos)                          /*!< LCD PAL192: B14_0 Mask              */
+#define LCD_PAL192_I1_Pos                                     31                                                        /*!< LCD PAL192: I1 Position             */
+#define LCD_PAL192_I1_Msk                                     (0x01UL << LCD_PAL192_I1_Pos)                             /*!< LCD PAL192: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL193  -------------------------------------------
+#define LCD_PAL193_R04_0_Pos                                  0                                                         /*!< LCD PAL193: R04_0 Position          */
+#define LCD_PAL193_R04_0_Msk                                  (0x1fUL << LCD_PAL193_R04_0_Pos)                          /*!< LCD PAL193: R04_0 Mask              */
+#define LCD_PAL193_G04_0_Pos                                  5                                                         /*!< LCD PAL193: G04_0 Position          */
+#define LCD_PAL193_G04_0_Msk                                  (0x1fUL << LCD_PAL193_G04_0_Pos)                          /*!< LCD PAL193: G04_0 Mask              */
+#define LCD_PAL193_B04_0_Pos                                  10                                                        /*!< LCD PAL193: B04_0 Position          */
+#define LCD_PAL193_B04_0_Msk                                  (0x1fUL << LCD_PAL193_B04_0_Pos)                          /*!< LCD PAL193: B04_0 Mask              */
+#define LCD_PAL193_I0_Pos                                     15                                                        /*!< LCD PAL193: I0 Position             */
+#define LCD_PAL193_I0_Msk                                     (0x01UL << LCD_PAL193_I0_Pos)                             /*!< LCD PAL193: I0 Mask                 */
+#define LCD_PAL193_R14_0_Pos                                  16                                                        /*!< LCD PAL193: R14_0 Position          */
+#define LCD_PAL193_R14_0_Msk                                  (0x1fUL << LCD_PAL193_R14_0_Pos)                          /*!< LCD PAL193: R14_0 Mask              */
+#define LCD_PAL193_G14_0_Pos                                  21                                                        /*!< LCD PAL193: G14_0 Position          */
+#define LCD_PAL193_G14_0_Msk                                  (0x1fUL << LCD_PAL193_G14_0_Pos)                          /*!< LCD PAL193: G14_0 Mask              */
+#define LCD_PAL193_B14_0_Pos                                  26                                                        /*!< LCD PAL193: B14_0 Position          */
+#define LCD_PAL193_B14_0_Msk                                  (0x1fUL << LCD_PAL193_B14_0_Pos)                          /*!< LCD PAL193: B14_0 Mask              */
+#define LCD_PAL193_I1_Pos                                     31                                                        /*!< LCD PAL193: I1 Position             */
+#define LCD_PAL193_I1_Msk                                     (0x01UL << LCD_PAL193_I1_Pos)                             /*!< LCD PAL193: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL194  -------------------------------------------
+#define LCD_PAL194_R04_0_Pos                                  0                                                         /*!< LCD PAL194: R04_0 Position          */
+#define LCD_PAL194_R04_0_Msk                                  (0x1fUL << LCD_PAL194_R04_0_Pos)                          /*!< LCD PAL194: R04_0 Mask              */
+#define LCD_PAL194_G04_0_Pos                                  5                                                         /*!< LCD PAL194: G04_0 Position          */
+#define LCD_PAL194_G04_0_Msk                                  (0x1fUL << LCD_PAL194_G04_0_Pos)                          /*!< LCD PAL194: G04_0 Mask              */
+#define LCD_PAL194_B04_0_Pos                                  10                                                        /*!< LCD PAL194: B04_0 Position          */
+#define LCD_PAL194_B04_0_Msk                                  (0x1fUL << LCD_PAL194_B04_0_Pos)                          /*!< LCD PAL194: B04_0 Mask              */
+#define LCD_PAL194_I0_Pos                                     15                                                        /*!< LCD PAL194: I0 Position             */
+#define LCD_PAL194_I0_Msk                                     (0x01UL << LCD_PAL194_I0_Pos)                             /*!< LCD PAL194: I0 Mask                 */
+#define LCD_PAL194_R14_0_Pos                                  16                                                        /*!< LCD PAL194: R14_0 Position          */
+#define LCD_PAL194_R14_0_Msk                                  (0x1fUL << LCD_PAL194_R14_0_Pos)                          /*!< LCD PAL194: R14_0 Mask              */
+#define LCD_PAL194_G14_0_Pos                                  21                                                        /*!< LCD PAL194: G14_0 Position          */
+#define LCD_PAL194_G14_0_Msk                                  (0x1fUL << LCD_PAL194_G14_0_Pos)                          /*!< LCD PAL194: G14_0 Mask              */
+#define LCD_PAL194_B14_0_Pos                                  26                                                        /*!< LCD PAL194: B14_0 Position          */
+#define LCD_PAL194_B14_0_Msk                                  (0x1fUL << LCD_PAL194_B14_0_Pos)                          /*!< LCD PAL194: B14_0 Mask              */
+#define LCD_PAL194_I1_Pos                                     31                                                        /*!< LCD PAL194: I1 Position             */
+#define LCD_PAL194_I1_Msk                                     (0x01UL << LCD_PAL194_I1_Pos)                             /*!< LCD PAL194: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL195  -------------------------------------------
+#define LCD_PAL195_R04_0_Pos                                  0                                                         /*!< LCD PAL195: R04_0 Position          */
+#define LCD_PAL195_R04_0_Msk                                  (0x1fUL << LCD_PAL195_R04_0_Pos)                          /*!< LCD PAL195: R04_0 Mask              */
+#define LCD_PAL195_G04_0_Pos                                  5                                                         /*!< LCD PAL195: G04_0 Position          */
+#define LCD_PAL195_G04_0_Msk                                  (0x1fUL << LCD_PAL195_G04_0_Pos)                          /*!< LCD PAL195: G04_0 Mask              */
+#define LCD_PAL195_B04_0_Pos                                  10                                                        /*!< LCD PAL195: B04_0 Position          */
+#define LCD_PAL195_B04_0_Msk                                  (0x1fUL << LCD_PAL195_B04_0_Pos)                          /*!< LCD PAL195: B04_0 Mask              */
+#define LCD_PAL195_I0_Pos                                     15                                                        /*!< LCD PAL195: I0 Position             */
+#define LCD_PAL195_I0_Msk                                     (0x01UL << LCD_PAL195_I0_Pos)                             /*!< LCD PAL195: I0 Mask                 */
+#define LCD_PAL195_R14_0_Pos                                  16                                                        /*!< LCD PAL195: R14_0 Position          */
+#define LCD_PAL195_R14_0_Msk                                  (0x1fUL << LCD_PAL195_R14_0_Pos)                          /*!< LCD PAL195: R14_0 Mask              */
+#define LCD_PAL195_G14_0_Pos                                  21                                                        /*!< LCD PAL195: G14_0 Position          */
+#define LCD_PAL195_G14_0_Msk                                  (0x1fUL << LCD_PAL195_G14_0_Pos)                          /*!< LCD PAL195: G14_0 Mask              */
+#define LCD_PAL195_B14_0_Pos                                  26                                                        /*!< LCD PAL195: B14_0 Position          */
+#define LCD_PAL195_B14_0_Msk                                  (0x1fUL << LCD_PAL195_B14_0_Pos)                          /*!< LCD PAL195: B14_0 Mask              */
+#define LCD_PAL195_I1_Pos                                     31                                                        /*!< LCD PAL195: I1 Position             */
+#define LCD_PAL195_I1_Msk                                     (0x01UL << LCD_PAL195_I1_Pos)                             /*!< LCD PAL195: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL196  -------------------------------------------
+#define LCD_PAL196_R04_0_Pos                                  0                                                         /*!< LCD PAL196: R04_0 Position          */
+#define LCD_PAL196_R04_0_Msk                                  (0x1fUL << LCD_PAL196_R04_0_Pos)                          /*!< LCD PAL196: R04_0 Mask              */
+#define LCD_PAL196_G04_0_Pos                                  5                                                         /*!< LCD PAL196: G04_0 Position          */
+#define LCD_PAL196_G04_0_Msk                                  (0x1fUL << LCD_PAL196_G04_0_Pos)                          /*!< LCD PAL196: G04_0 Mask              */
+#define LCD_PAL196_B04_0_Pos                                  10                                                        /*!< LCD PAL196: B04_0 Position          */
+#define LCD_PAL196_B04_0_Msk                                  (0x1fUL << LCD_PAL196_B04_0_Pos)                          /*!< LCD PAL196: B04_0 Mask              */
+#define LCD_PAL196_I0_Pos                                     15                                                        /*!< LCD PAL196: I0 Position             */
+#define LCD_PAL196_I0_Msk                                     (0x01UL << LCD_PAL196_I0_Pos)                             /*!< LCD PAL196: I0 Mask                 */
+#define LCD_PAL196_R14_0_Pos                                  16                                                        /*!< LCD PAL196: R14_0 Position          */
+#define LCD_PAL196_R14_0_Msk                                  (0x1fUL << LCD_PAL196_R14_0_Pos)                          /*!< LCD PAL196: R14_0 Mask              */
+#define LCD_PAL196_G14_0_Pos                                  21                                                        /*!< LCD PAL196: G14_0 Position          */
+#define LCD_PAL196_G14_0_Msk                                  (0x1fUL << LCD_PAL196_G14_0_Pos)                          /*!< LCD PAL196: G14_0 Mask              */
+#define LCD_PAL196_B14_0_Pos                                  26                                                        /*!< LCD PAL196: B14_0 Position          */
+#define LCD_PAL196_B14_0_Msk                                  (0x1fUL << LCD_PAL196_B14_0_Pos)                          /*!< LCD PAL196: B14_0 Mask              */
+#define LCD_PAL196_I1_Pos                                     31                                                        /*!< LCD PAL196: I1 Position             */
+#define LCD_PAL196_I1_Msk                                     (0x01UL << LCD_PAL196_I1_Pos)                             /*!< LCD PAL196: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL197  -------------------------------------------
+#define LCD_PAL197_R04_0_Pos                                  0                                                         /*!< LCD PAL197: R04_0 Position          */
+#define LCD_PAL197_R04_0_Msk                                  (0x1fUL << LCD_PAL197_R04_0_Pos)                          /*!< LCD PAL197: R04_0 Mask              */
+#define LCD_PAL197_G04_0_Pos                                  5                                                         /*!< LCD PAL197: G04_0 Position          */
+#define LCD_PAL197_G04_0_Msk                                  (0x1fUL << LCD_PAL197_G04_0_Pos)                          /*!< LCD PAL197: G04_0 Mask              */
+#define LCD_PAL197_B04_0_Pos                                  10                                                        /*!< LCD PAL197: B04_0 Position          */
+#define LCD_PAL197_B04_0_Msk                                  (0x1fUL << LCD_PAL197_B04_0_Pos)                          /*!< LCD PAL197: B04_0 Mask              */
+#define LCD_PAL197_I0_Pos                                     15                                                        /*!< LCD PAL197: I0 Position             */
+#define LCD_PAL197_I0_Msk                                     (0x01UL << LCD_PAL197_I0_Pos)                             /*!< LCD PAL197: I0 Mask                 */
+#define LCD_PAL197_R14_0_Pos                                  16                                                        /*!< LCD PAL197: R14_0 Position          */
+#define LCD_PAL197_R14_0_Msk                                  (0x1fUL << LCD_PAL197_R14_0_Pos)                          /*!< LCD PAL197: R14_0 Mask              */
+#define LCD_PAL197_G14_0_Pos                                  21                                                        /*!< LCD PAL197: G14_0 Position          */
+#define LCD_PAL197_G14_0_Msk                                  (0x1fUL << LCD_PAL197_G14_0_Pos)                          /*!< LCD PAL197: G14_0 Mask              */
+#define LCD_PAL197_B14_0_Pos                                  26                                                        /*!< LCD PAL197: B14_0 Position          */
+#define LCD_PAL197_B14_0_Msk                                  (0x1fUL << LCD_PAL197_B14_0_Pos)                          /*!< LCD PAL197: B14_0 Mask              */
+#define LCD_PAL197_I1_Pos                                     31                                                        /*!< LCD PAL197: I1 Position             */
+#define LCD_PAL197_I1_Msk                                     (0x01UL << LCD_PAL197_I1_Pos)                             /*!< LCD PAL197: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL198  -------------------------------------------
+#define LCD_PAL198_R04_0_Pos                                  0                                                         /*!< LCD PAL198: R04_0 Position          */
+#define LCD_PAL198_R04_0_Msk                                  (0x1fUL << LCD_PAL198_R04_0_Pos)                          /*!< LCD PAL198: R04_0 Mask              */
+#define LCD_PAL198_G04_0_Pos                                  5                                                         /*!< LCD PAL198: G04_0 Position          */
+#define LCD_PAL198_G04_0_Msk                                  (0x1fUL << LCD_PAL198_G04_0_Pos)                          /*!< LCD PAL198: G04_0 Mask              */
+#define LCD_PAL198_B04_0_Pos                                  10                                                        /*!< LCD PAL198: B04_0 Position          */
+#define LCD_PAL198_B04_0_Msk                                  (0x1fUL << LCD_PAL198_B04_0_Pos)                          /*!< LCD PAL198: B04_0 Mask              */
+#define LCD_PAL198_I0_Pos                                     15                                                        /*!< LCD PAL198: I0 Position             */
+#define LCD_PAL198_I0_Msk                                     (0x01UL << LCD_PAL198_I0_Pos)                             /*!< LCD PAL198: I0 Mask                 */
+#define LCD_PAL198_R14_0_Pos                                  16                                                        /*!< LCD PAL198: R14_0 Position          */
+#define LCD_PAL198_R14_0_Msk                                  (0x1fUL << LCD_PAL198_R14_0_Pos)                          /*!< LCD PAL198: R14_0 Mask              */
+#define LCD_PAL198_G14_0_Pos                                  21                                                        /*!< LCD PAL198: G14_0 Position          */
+#define LCD_PAL198_G14_0_Msk                                  (0x1fUL << LCD_PAL198_G14_0_Pos)                          /*!< LCD PAL198: G14_0 Mask              */
+#define LCD_PAL198_B14_0_Pos                                  26                                                        /*!< LCD PAL198: B14_0 Position          */
+#define LCD_PAL198_B14_0_Msk                                  (0x1fUL << LCD_PAL198_B14_0_Pos)                          /*!< LCD PAL198: B14_0 Mask              */
+#define LCD_PAL198_I1_Pos                                     31                                                        /*!< LCD PAL198: I1 Position             */
+#define LCD_PAL198_I1_Msk                                     (0x01UL << LCD_PAL198_I1_Pos)                             /*!< LCD PAL198: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL199  -------------------------------------------
+#define LCD_PAL199_R04_0_Pos                                  0                                                         /*!< LCD PAL199: R04_0 Position          */
+#define LCD_PAL199_R04_0_Msk                                  (0x1fUL << LCD_PAL199_R04_0_Pos)                          /*!< LCD PAL199: R04_0 Mask              */
+#define LCD_PAL199_G04_0_Pos                                  5                                                         /*!< LCD PAL199: G04_0 Position          */
+#define LCD_PAL199_G04_0_Msk                                  (0x1fUL << LCD_PAL199_G04_0_Pos)                          /*!< LCD PAL199: G04_0 Mask              */
+#define LCD_PAL199_B04_0_Pos                                  10                                                        /*!< LCD PAL199: B04_0 Position          */
+#define LCD_PAL199_B04_0_Msk                                  (0x1fUL << LCD_PAL199_B04_0_Pos)                          /*!< LCD PAL199: B04_0 Mask              */
+#define LCD_PAL199_I0_Pos                                     15                                                        /*!< LCD PAL199: I0 Position             */
+#define LCD_PAL199_I0_Msk                                     (0x01UL << LCD_PAL199_I0_Pos)                             /*!< LCD PAL199: I0 Mask                 */
+#define LCD_PAL199_R14_0_Pos                                  16                                                        /*!< LCD PAL199: R14_0 Position          */
+#define LCD_PAL199_R14_0_Msk                                  (0x1fUL << LCD_PAL199_R14_0_Pos)                          /*!< LCD PAL199: R14_0 Mask              */
+#define LCD_PAL199_G14_0_Pos                                  21                                                        /*!< LCD PAL199: G14_0 Position          */
+#define LCD_PAL199_G14_0_Msk                                  (0x1fUL << LCD_PAL199_G14_0_Pos)                          /*!< LCD PAL199: G14_0 Mask              */
+#define LCD_PAL199_B14_0_Pos                                  26                                                        /*!< LCD PAL199: B14_0 Position          */
+#define LCD_PAL199_B14_0_Msk                                  (0x1fUL << LCD_PAL199_B14_0_Pos)                          /*!< LCD PAL199: B14_0 Mask              */
+#define LCD_PAL199_I1_Pos                                     31                                                        /*!< LCD PAL199: I1 Position             */
+#define LCD_PAL199_I1_Msk                                     (0x01UL << LCD_PAL199_I1_Pos)                             /*!< LCD PAL199: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL200  -------------------------------------------
+#define LCD_PAL200_R04_0_Pos                                  0                                                         /*!< LCD PAL200: R04_0 Position          */
+#define LCD_PAL200_R04_0_Msk                                  (0x1fUL << LCD_PAL200_R04_0_Pos)                          /*!< LCD PAL200: R04_0 Mask              */
+#define LCD_PAL200_G04_0_Pos                                  5                                                         /*!< LCD PAL200: G04_0 Position          */
+#define LCD_PAL200_G04_0_Msk                                  (0x1fUL << LCD_PAL200_G04_0_Pos)                          /*!< LCD PAL200: G04_0 Mask              */
+#define LCD_PAL200_B04_0_Pos                                  10                                                        /*!< LCD PAL200: B04_0 Position          */
+#define LCD_PAL200_B04_0_Msk                                  (0x1fUL << LCD_PAL200_B04_0_Pos)                          /*!< LCD PAL200: B04_0 Mask              */
+#define LCD_PAL200_I0_Pos                                     15                                                        /*!< LCD PAL200: I0 Position             */
+#define LCD_PAL200_I0_Msk                                     (0x01UL << LCD_PAL200_I0_Pos)                             /*!< LCD PAL200: I0 Mask                 */
+#define LCD_PAL200_R14_0_Pos                                  16                                                        /*!< LCD PAL200: R14_0 Position          */
+#define LCD_PAL200_R14_0_Msk                                  (0x1fUL << LCD_PAL200_R14_0_Pos)                          /*!< LCD PAL200: R14_0 Mask              */
+#define LCD_PAL200_G14_0_Pos                                  21                                                        /*!< LCD PAL200: G14_0 Position          */
+#define LCD_PAL200_G14_0_Msk                                  (0x1fUL << LCD_PAL200_G14_0_Pos)                          /*!< LCD PAL200: G14_0 Mask              */
+#define LCD_PAL200_B14_0_Pos                                  26                                                        /*!< LCD PAL200: B14_0 Position          */
+#define LCD_PAL200_B14_0_Msk                                  (0x1fUL << LCD_PAL200_B14_0_Pos)                          /*!< LCD PAL200: B14_0 Mask              */
+#define LCD_PAL200_I1_Pos                                     31                                                        /*!< LCD PAL200: I1 Position             */
+#define LCD_PAL200_I1_Msk                                     (0x01UL << LCD_PAL200_I1_Pos)                             /*!< LCD PAL200: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL201  -------------------------------------------
+#define LCD_PAL201_R04_0_Pos                                  0                                                         /*!< LCD PAL201: R04_0 Position          */
+#define LCD_PAL201_R04_0_Msk                                  (0x1fUL << LCD_PAL201_R04_0_Pos)                          /*!< LCD PAL201: R04_0 Mask              */
+#define LCD_PAL201_G04_0_Pos                                  5                                                         /*!< LCD PAL201: G04_0 Position          */
+#define LCD_PAL201_G04_0_Msk                                  (0x1fUL << LCD_PAL201_G04_0_Pos)                          /*!< LCD PAL201: G04_0 Mask              */
+#define LCD_PAL201_B04_0_Pos                                  10                                                        /*!< LCD PAL201: B04_0 Position          */
+#define LCD_PAL201_B04_0_Msk                                  (0x1fUL << LCD_PAL201_B04_0_Pos)                          /*!< LCD PAL201: B04_0 Mask              */
+#define LCD_PAL201_I0_Pos                                     15                                                        /*!< LCD PAL201: I0 Position             */
+#define LCD_PAL201_I0_Msk                                     (0x01UL << LCD_PAL201_I0_Pos)                             /*!< LCD PAL201: I0 Mask                 */
+#define LCD_PAL201_R14_0_Pos                                  16                                                        /*!< LCD PAL201: R14_0 Position          */
+#define LCD_PAL201_R14_0_Msk                                  (0x1fUL << LCD_PAL201_R14_0_Pos)                          /*!< LCD PAL201: R14_0 Mask              */
+#define LCD_PAL201_G14_0_Pos                                  21                                                        /*!< LCD PAL201: G14_0 Position          */
+#define LCD_PAL201_G14_0_Msk                                  (0x1fUL << LCD_PAL201_G14_0_Pos)                          /*!< LCD PAL201: G14_0 Mask              */
+#define LCD_PAL201_B14_0_Pos                                  26                                                        /*!< LCD PAL201: B14_0 Position          */
+#define LCD_PAL201_B14_0_Msk                                  (0x1fUL << LCD_PAL201_B14_0_Pos)                          /*!< LCD PAL201: B14_0 Mask              */
+#define LCD_PAL201_I1_Pos                                     31                                                        /*!< LCD PAL201: I1 Position             */
+#define LCD_PAL201_I1_Msk                                     (0x01UL << LCD_PAL201_I1_Pos)                             /*!< LCD PAL201: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL202  -------------------------------------------
+#define LCD_PAL202_R04_0_Pos                                  0                                                         /*!< LCD PAL202: R04_0 Position          */
+#define LCD_PAL202_R04_0_Msk                                  (0x1fUL << LCD_PAL202_R04_0_Pos)                          /*!< LCD PAL202: R04_0 Mask              */
+#define LCD_PAL202_G04_0_Pos                                  5                                                         /*!< LCD PAL202: G04_0 Position          */
+#define LCD_PAL202_G04_0_Msk                                  (0x1fUL << LCD_PAL202_G04_0_Pos)                          /*!< LCD PAL202: G04_0 Mask              */
+#define LCD_PAL202_B04_0_Pos                                  10                                                        /*!< LCD PAL202: B04_0 Position          */
+#define LCD_PAL202_B04_0_Msk                                  (0x1fUL << LCD_PAL202_B04_0_Pos)                          /*!< LCD PAL202: B04_0 Mask              */
+#define LCD_PAL202_I0_Pos                                     15                                                        /*!< LCD PAL202: I0 Position             */
+#define LCD_PAL202_I0_Msk                                     (0x01UL << LCD_PAL202_I0_Pos)                             /*!< LCD PAL202: I0 Mask                 */
+#define LCD_PAL202_R14_0_Pos                                  16                                                        /*!< LCD PAL202: R14_0 Position          */
+#define LCD_PAL202_R14_0_Msk                                  (0x1fUL << LCD_PAL202_R14_0_Pos)                          /*!< LCD PAL202: R14_0 Mask              */
+#define LCD_PAL202_G14_0_Pos                                  21                                                        /*!< LCD PAL202: G14_0 Position          */
+#define LCD_PAL202_G14_0_Msk                                  (0x1fUL << LCD_PAL202_G14_0_Pos)                          /*!< LCD PAL202: G14_0 Mask              */
+#define LCD_PAL202_B14_0_Pos                                  26                                                        /*!< LCD PAL202: B14_0 Position          */
+#define LCD_PAL202_B14_0_Msk                                  (0x1fUL << LCD_PAL202_B14_0_Pos)                          /*!< LCD PAL202: B14_0 Mask              */
+#define LCD_PAL202_I1_Pos                                     31                                                        /*!< LCD PAL202: I1 Position             */
+#define LCD_PAL202_I1_Msk                                     (0x01UL << LCD_PAL202_I1_Pos)                             /*!< LCD PAL202: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL203  -------------------------------------------
+#define LCD_PAL203_R04_0_Pos                                  0                                                         /*!< LCD PAL203: R04_0 Position          */
+#define LCD_PAL203_R04_0_Msk                                  (0x1fUL << LCD_PAL203_R04_0_Pos)                          /*!< LCD PAL203: R04_0 Mask              */
+#define LCD_PAL203_G04_0_Pos                                  5                                                         /*!< LCD PAL203: G04_0 Position          */
+#define LCD_PAL203_G04_0_Msk                                  (0x1fUL << LCD_PAL203_G04_0_Pos)                          /*!< LCD PAL203: G04_0 Mask              */
+#define LCD_PAL203_B04_0_Pos                                  10                                                        /*!< LCD PAL203: B04_0 Position          */
+#define LCD_PAL203_B04_0_Msk                                  (0x1fUL << LCD_PAL203_B04_0_Pos)                          /*!< LCD PAL203: B04_0 Mask              */
+#define LCD_PAL203_I0_Pos                                     15                                                        /*!< LCD PAL203: I0 Position             */
+#define LCD_PAL203_I0_Msk                                     (0x01UL << LCD_PAL203_I0_Pos)                             /*!< LCD PAL203: I0 Mask                 */
+#define LCD_PAL203_R14_0_Pos                                  16                                                        /*!< LCD PAL203: R14_0 Position          */
+#define LCD_PAL203_R14_0_Msk                                  (0x1fUL << LCD_PAL203_R14_0_Pos)                          /*!< LCD PAL203: R14_0 Mask              */
+#define LCD_PAL203_G14_0_Pos                                  21                                                        /*!< LCD PAL203: G14_0 Position          */
+#define LCD_PAL203_G14_0_Msk                                  (0x1fUL << LCD_PAL203_G14_0_Pos)                          /*!< LCD PAL203: G14_0 Mask              */
+#define LCD_PAL203_B14_0_Pos                                  26                                                        /*!< LCD PAL203: B14_0 Position          */
+#define LCD_PAL203_B14_0_Msk                                  (0x1fUL << LCD_PAL203_B14_0_Pos)                          /*!< LCD PAL203: B14_0 Mask              */
+#define LCD_PAL203_I1_Pos                                     31                                                        /*!< LCD PAL203: I1 Position             */
+#define LCD_PAL203_I1_Msk                                     (0x01UL << LCD_PAL203_I1_Pos)                             /*!< LCD PAL203: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL204  -------------------------------------------
+#define LCD_PAL204_R04_0_Pos                                  0                                                         /*!< LCD PAL204: R04_0 Position          */
+#define LCD_PAL204_R04_0_Msk                                  (0x1fUL << LCD_PAL204_R04_0_Pos)                          /*!< LCD PAL204: R04_0 Mask              */
+#define LCD_PAL204_G04_0_Pos                                  5                                                         /*!< LCD PAL204: G04_0 Position          */
+#define LCD_PAL204_G04_0_Msk                                  (0x1fUL << LCD_PAL204_G04_0_Pos)                          /*!< LCD PAL204: G04_0 Mask              */
+#define LCD_PAL204_B04_0_Pos                                  10                                                        /*!< LCD PAL204: B04_0 Position          */
+#define LCD_PAL204_B04_0_Msk                                  (0x1fUL << LCD_PAL204_B04_0_Pos)                          /*!< LCD PAL204: B04_0 Mask              */
+#define LCD_PAL204_I0_Pos                                     15                                                        /*!< LCD PAL204: I0 Position             */
+#define LCD_PAL204_I0_Msk                                     (0x01UL << LCD_PAL204_I0_Pos)                             /*!< LCD PAL204: I0 Mask                 */
+#define LCD_PAL204_R14_0_Pos                                  16                                                        /*!< LCD PAL204: R14_0 Position          */
+#define LCD_PAL204_R14_0_Msk                                  (0x1fUL << LCD_PAL204_R14_0_Pos)                          /*!< LCD PAL204: R14_0 Mask              */
+#define LCD_PAL204_G14_0_Pos                                  21                                                        /*!< LCD PAL204: G14_0 Position          */
+#define LCD_PAL204_G14_0_Msk                                  (0x1fUL << LCD_PAL204_G14_0_Pos)                          /*!< LCD PAL204: G14_0 Mask              */
+#define LCD_PAL204_B14_0_Pos                                  26                                                        /*!< LCD PAL204: B14_0 Position          */
+#define LCD_PAL204_B14_0_Msk                                  (0x1fUL << LCD_PAL204_B14_0_Pos)                          /*!< LCD PAL204: B14_0 Mask              */
+#define LCD_PAL204_I1_Pos                                     31                                                        /*!< LCD PAL204: I1 Position             */
+#define LCD_PAL204_I1_Msk                                     (0x01UL << LCD_PAL204_I1_Pos)                             /*!< LCD PAL204: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL205  -------------------------------------------
+#define LCD_PAL205_R04_0_Pos                                  0                                                         /*!< LCD PAL205: R04_0 Position          */
+#define LCD_PAL205_R04_0_Msk                                  (0x1fUL << LCD_PAL205_R04_0_Pos)                          /*!< LCD PAL205: R04_0 Mask              */
+#define LCD_PAL205_G04_0_Pos                                  5                                                         /*!< LCD PAL205: G04_0 Position          */
+#define LCD_PAL205_G04_0_Msk                                  (0x1fUL << LCD_PAL205_G04_0_Pos)                          /*!< LCD PAL205: G04_0 Mask              */
+#define LCD_PAL205_B04_0_Pos                                  10                                                        /*!< LCD PAL205: B04_0 Position          */
+#define LCD_PAL205_B04_0_Msk                                  (0x1fUL << LCD_PAL205_B04_0_Pos)                          /*!< LCD PAL205: B04_0 Mask              */
+#define LCD_PAL205_I0_Pos                                     15                                                        /*!< LCD PAL205: I0 Position             */
+#define LCD_PAL205_I0_Msk                                     (0x01UL << LCD_PAL205_I0_Pos)                             /*!< LCD PAL205: I0 Mask                 */
+#define LCD_PAL205_R14_0_Pos                                  16                                                        /*!< LCD PAL205: R14_0 Position          */
+#define LCD_PAL205_R14_0_Msk                                  (0x1fUL << LCD_PAL205_R14_0_Pos)                          /*!< LCD PAL205: R14_0 Mask              */
+#define LCD_PAL205_G14_0_Pos                                  21                                                        /*!< LCD PAL205: G14_0 Position          */
+#define LCD_PAL205_G14_0_Msk                                  (0x1fUL << LCD_PAL205_G14_0_Pos)                          /*!< LCD PAL205: G14_0 Mask              */
+#define LCD_PAL205_B14_0_Pos                                  26                                                        /*!< LCD PAL205: B14_0 Position          */
+#define LCD_PAL205_B14_0_Msk                                  (0x1fUL << LCD_PAL205_B14_0_Pos)                          /*!< LCD PAL205: B14_0 Mask              */
+#define LCD_PAL205_I1_Pos                                     31                                                        /*!< LCD PAL205: I1 Position             */
+#define LCD_PAL205_I1_Msk                                     (0x01UL << LCD_PAL205_I1_Pos)                             /*!< LCD PAL205: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL206  -------------------------------------------
+#define LCD_PAL206_R04_0_Pos                                  0                                                         /*!< LCD PAL206: R04_0 Position          */
+#define LCD_PAL206_R04_0_Msk                                  (0x1fUL << LCD_PAL206_R04_0_Pos)                          /*!< LCD PAL206: R04_0 Mask              */
+#define LCD_PAL206_G04_0_Pos                                  5                                                         /*!< LCD PAL206: G04_0 Position          */
+#define LCD_PAL206_G04_0_Msk                                  (0x1fUL << LCD_PAL206_G04_0_Pos)                          /*!< LCD PAL206: G04_0 Mask              */
+#define LCD_PAL206_B04_0_Pos                                  10                                                        /*!< LCD PAL206: B04_0 Position          */
+#define LCD_PAL206_B04_0_Msk                                  (0x1fUL << LCD_PAL206_B04_0_Pos)                          /*!< LCD PAL206: B04_0 Mask              */
+#define LCD_PAL206_I0_Pos                                     15                                                        /*!< LCD PAL206: I0 Position             */
+#define LCD_PAL206_I0_Msk                                     (0x01UL << LCD_PAL206_I0_Pos)                             /*!< LCD PAL206: I0 Mask                 */
+#define LCD_PAL206_R14_0_Pos                                  16                                                        /*!< LCD PAL206: R14_0 Position          */
+#define LCD_PAL206_R14_0_Msk                                  (0x1fUL << LCD_PAL206_R14_0_Pos)                          /*!< LCD PAL206: R14_0 Mask              */
+#define LCD_PAL206_G14_0_Pos                                  21                                                        /*!< LCD PAL206: G14_0 Position          */
+#define LCD_PAL206_G14_0_Msk                                  (0x1fUL << LCD_PAL206_G14_0_Pos)                          /*!< LCD PAL206: G14_0 Mask              */
+#define LCD_PAL206_B14_0_Pos                                  26                                                        /*!< LCD PAL206: B14_0 Position          */
+#define LCD_PAL206_B14_0_Msk                                  (0x1fUL << LCD_PAL206_B14_0_Pos)                          /*!< LCD PAL206: B14_0 Mask              */
+#define LCD_PAL206_I1_Pos                                     31                                                        /*!< LCD PAL206: I1 Position             */
+#define LCD_PAL206_I1_Msk                                     (0x01UL << LCD_PAL206_I1_Pos)                             /*!< LCD PAL206: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL207  -------------------------------------------
+#define LCD_PAL207_R04_0_Pos                                  0                                                         /*!< LCD PAL207: R04_0 Position          */
+#define LCD_PAL207_R04_0_Msk                                  (0x1fUL << LCD_PAL207_R04_0_Pos)                          /*!< LCD PAL207: R04_0 Mask              */
+#define LCD_PAL207_G04_0_Pos                                  5                                                         /*!< LCD PAL207: G04_0 Position          */
+#define LCD_PAL207_G04_0_Msk                                  (0x1fUL << LCD_PAL207_G04_0_Pos)                          /*!< LCD PAL207: G04_0 Mask              */
+#define LCD_PAL207_B04_0_Pos                                  10                                                        /*!< LCD PAL207: B04_0 Position          */
+#define LCD_PAL207_B04_0_Msk                                  (0x1fUL << LCD_PAL207_B04_0_Pos)                          /*!< LCD PAL207: B04_0 Mask              */
+#define LCD_PAL207_I0_Pos                                     15                                                        /*!< LCD PAL207: I0 Position             */
+#define LCD_PAL207_I0_Msk                                     (0x01UL << LCD_PAL207_I0_Pos)                             /*!< LCD PAL207: I0 Mask                 */
+#define LCD_PAL207_R14_0_Pos                                  16                                                        /*!< LCD PAL207: R14_0 Position          */
+#define LCD_PAL207_R14_0_Msk                                  (0x1fUL << LCD_PAL207_R14_0_Pos)                          /*!< LCD PAL207: R14_0 Mask              */
+#define LCD_PAL207_G14_0_Pos                                  21                                                        /*!< LCD PAL207: G14_0 Position          */
+#define LCD_PAL207_G14_0_Msk                                  (0x1fUL << LCD_PAL207_G14_0_Pos)                          /*!< LCD PAL207: G14_0 Mask              */
+#define LCD_PAL207_B14_0_Pos                                  26                                                        /*!< LCD PAL207: B14_0 Position          */
+#define LCD_PAL207_B14_0_Msk                                  (0x1fUL << LCD_PAL207_B14_0_Pos)                          /*!< LCD PAL207: B14_0 Mask              */
+#define LCD_PAL207_I1_Pos                                     31                                                        /*!< LCD PAL207: I1 Position             */
+#define LCD_PAL207_I1_Msk                                     (0x01UL << LCD_PAL207_I1_Pos)                             /*!< LCD PAL207: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL208  -------------------------------------------
+#define LCD_PAL208_R04_0_Pos                                  0                                                         /*!< LCD PAL208: R04_0 Position          */
+#define LCD_PAL208_R04_0_Msk                                  (0x1fUL << LCD_PAL208_R04_0_Pos)                          /*!< LCD PAL208: R04_0 Mask              */
+#define LCD_PAL208_G04_0_Pos                                  5                                                         /*!< LCD PAL208: G04_0 Position          */
+#define LCD_PAL208_G04_0_Msk                                  (0x1fUL << LCD_PAL208_G04_0_Pos)                          /*!< LCD PAL208: G04_0 Mask              */
+#define LCD_PAL208_B04_0_Pos                                  10                                                        /*!< LCD PAL208: B04_0 Position          */
+#define LCD_PAL208_B04_0_Msk                                  (0x1fUL << LCD_PAL208_B04_0_Pos)                          /*!< LCD PAL208: B04_0 Mask              */
+#define LCD_PAL208_I0_Pos                                     15                                                        /*!< LCD PAL208: I0 Position             */
+#define LCD_PAL208_I0_Msk                                     (0x01UL << LCD_PAL208_I0_Pos)                             /*!< LCD PAL208: I0 Mask                 */
+#define LCD_PAL208_R14_0_Pos                                  16                                                        /*!< LCD PAL208: R14_0 Position          */
+#define LCD_PAL208_R14_0_Msk                                  (0x1fUL << LCD_PAL208_R14_0_Pos)                          /*!< LCD PAL208: R14_0 Mask              */
+#define LCD_PAL208_G14_0_Pos                                  21                                                        /*!< LCD PAL208: G14_0 Position          */
+#define LCD_PAL208_G14_0_Msk                                  (0x1fUL << LCD_PAL208_G14_0_Pos)                          /*!< LCD PAL208: G14_0 Mask              */
+#define LCD_PAL208_B14_0_Pos                                  26                                                        /*!< LCD PAL208: B14_0 Position          */
+#define LCD_PAL208_B14_0_Msk                                  (0x1fUL << LCD_PAL208_B14_0_Pos)                          /*!< LCD PAL208: B14_0 Mask              */
+#define LCD_PAL208_I1_Pos                                     31                                                        /*!< LCD PAL208: I1 Position             */
+#define LCD_PAL208_I1_Msk                                     (0x01UL << LCD_PAL208_I1_Pos)                             /*!< LCD PAL208: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL209  -------------------------------------------
+#define LCD_PAL209_R04_0_Pos                                  0                                                         /*!< LCD PAL209: R04_0 Position          */
+#define LCD_PAL209_R04_0_Msk                                  (0x1fUL << LCD_PAL209_R04_0_Pos)                          /*!< LCD PAL209: R04_0 Mask              */
+#define LCD_PAL209_G04_0_Pos                                  5                                                         /*!< LCD PAL209: G04_0 Position          */
+#define LCD_PAL209_G04_0_Msk                                  (0x1fUL << LCD_PAL209_G04_0_Pos)                          /*!< LCD PAL209: G04_0 Mask              */
+#define LCD_PAL209_B04_0_Pos                                  10                                                        /*!< LCD PAL209: B04_0 Position          */
+#define LCD_PAL209_B04_0_Msk                                  (0x1fUL << LCD_PAL209_B04_0_Pos)                          /*!< LCD PAL209: B04_0 Mask              */
+#define LCD_PAL209_I0_Pos                                     15                                                        /*!< LCD PAL209: I0 Position             */
+#define LCD_PAL209_I0_Msk                                     (0x01UL << LCD_PAL209_I0_Pos)                             /*!< LCD PAL209: I0 Mask                 */
+#define LCD_PAL209_R14_0_Pos                                  16                                                        /*!< LCD PAL209: R14_0 Position          */
+#define LCD_PAL209_R14_0_Msk                                  (0x1fUL << LCD_PAL209_R14_0_Pos)                          /*!< LCD PAL209: R14_0 Mask              */
+#define LCD_PAL209_G14_0_Pos                                  21                                                        /*!< LCD PAL209: G14_0 Position          */
+#define LCD_PAL209_G14_0_Msk                                  (0x1fUL << LCD_PAL209_G14_0_Pos)                          /*!< LCD PAL209: G14_0 Mask              */
+#define LCD_PAL209_B14_0_Pos                                  26                                                        /*!< LCD PAL209: B14_0 Position          */
+#define LCD_PAL209_B14_0_Msk                                  (0x1fUL << LCD_PAL209_B14_0_Pos)                          /*!< LCD PAL209: B14_0 Mask              */
+#define LCD_PAL209_I1_Pos                                     31                                                        /*!< LCD PAL209: I1 Position             */
+#define LCD_PAL209_I1_Msk                                     (0x01UL << LCD_PAL209_I1_Pos)                             /*!< LCD PAL209: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL210  -------------------------------------------
+#define LCD_PAL210_R04_0_Pos                                  0                                                         /*!< LCD PAL210: R04_0 Position          */
+#define LCD_PAL210_R04_0_Msk                                  (0x1fUL << LCD_PAL210_R04_0_Pos)                          /*!< LCD PAL210: R04_0 Mask              */
+#define LCD_PAL210_G04_0_Pos                                  5                                                         /*!< LCD PAL210: G04_0 Position          */
+#define LCD_PAL210_G04_0_Msk                                  (0x1fUL << LCD_PAL210_G04_0_Pos)                          /*!< LCD PAL210: G04_0 Mask              */
+#define LCD_PAL210_B04_0_Pos                                  10                                                        /*!< LCD PAL210: B04_0 Position          */
+#define LCD_PAL210_B04_0_Msk                                  (0x1fUL << LCD_PAL210_B04_0_Pos)                          /*!< LCD PAL210: B04_0 Mask              */
+#define LCD_PAL210_I0_Pos                                     15                                                        /*!< LCD PAL210: I0 Position             */
+#define LCD_PAL210_I0_Msk                                     (0x01UL << LCD_PAL210_I0_Pos)                             /*!< LCD PAL210: I0 Mask                 */
+#define LCD_PAL210_R14_0_Pos                                  16                                                        /*!< LCD PAL210: R14_0 Position          */
+#define LCD_PAL210_R14_0_Msk                                  (0x1fUL << LCD_PAL210_R14_0_Pos)                          /*!< LCD PAL210: R14_0 Mask              */
+#define LCD_PAL210_G14_0_Pos                                  21                                                        /*!< LCD PAL210: G14_0 Position          */
+#define LCD_PAL210_G14_0_Msk                                  (0x1fUL << LCD_PAL210_G14_0_Pos)                          /*!< LCD PAL210: G14_0 Mask              */
+#define LCD_PAL210_B14_0_Pos                                  26                                                        /*!< LCD PAL210: B14_0 Position          */
+#define LCD_PAL210_B14_0_Msk                                  (0x1fUL << LCD_PAL210_B14_0_Pos)                          /*!< LCD PAL210: B14_0 Mask              */
+#define LCD_PAL210_I1_Pos                                     31                                                        /*!< LCD PAL210: I1 Position             */
+#define LCD_PAL210_I1_Msk                                     (0x01UL << LCD_PAL210_I1_Pos)                             /*!< LCD PAL210: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL211  -------------------------------------------
+#define LCD_PAL211_R04_0_Pos                                  0                                                         /*!< LCD PAL211: R04_0 Position          */
+#define LCD_PAL211_R04_0_Msk                                  (0x1fUL << LCD_PAL211_R04_0_Pos)                          /*!< LCD PAL211: R04_0 Mask              */
+#define LCD_PAL211_G04_0_Pos                                  5                                                         /*!< LCD PAL211: G04_0 Position          */
+#define LCD_PAL211_G04_0_Msk                                  (0x1fUL << LCD_PAL211_G04_0_Pos)                          /*!< LCD PAL211: G04_0 Mask              */
+#define LCD_PAL211_B04_0_Pos                                  10                                                        /*!< LCD PAL211: B04_0 Position          */
+#define LCD_PAL211_B04_0_Msk                                  (0x1fUL << LCD_PAL211_B04_0_Pos)                          /*!< LCD PAL211: B04_0 Mask              */
+#define LCD_PAL211_I0_Pos                                     15                                                        /*!< LCD PAL211: I0 Position             */
+#define LCD_PAL211_I0_Msk                                     (0x01UL << LCD_PAL211_I0_Pos)                             /*!< LCD PAL211: I0 Mask                 */
+#define LCD_PAL211_R14_0_Pos                                  16                                                        /*!< LCD PAL211: R14_0 Position          */
+#define LCD_PAL211_R14_0_Msk                                  (0x1fUL << LCD_PAL211_R14_0_Pos)                          /*!< LCD PAL211: R14_0 Mask              */
+#define LCD_PAL211_G14_0_Pos                                  21                                                        /*!< LCD PAL211: G14_0 Position          */
+#define LCD_PAL211_G14_0_Msk                                  (0x1fUL << LCD_PAL211_G14_0_Pos)                          /*!< LCD PAL211: G14_0 Mask              */
+#define LCD_PAL211_B14_0_Pos                                  26                                                        /*!< LCD PAL211: B14_0 Position          */
+#define LCD_PAL211_B14_0_Msk                                  (0x1fUL << LCD_PAL211_B14_0_Pos)                          /*!< LCD PAL211: B14_0 Mask              */
+#define LCD_PAL211_I1_Pos                                     31                                                        /*!< LCD PAL211: I1 Position             */
+#define LCD_PAL211_I1_Msk                                     (0x01UL << LCD_PAL211_I1_Pos)                             /*!< LCD PAL211: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL212  -------------------------------------------
+#define LCD_PAL212_R04_0_Pos                                  0                                                         /*!< LCD PAL212: R04_0 Position          */
+#define LCD_PAL212_R04_0_Msk                                  (0x1fUL << LCD_PAL212_R04_0_Pos)                          /*!< LCD PAL212: R04_0 Mask              */
+#define LCD_PAL212_G04_0_Pos                                  5                                                         /*!< LCD PAL212: G04_0 Position          */
+#define LCD_PAL212_G04_0_Msk                                  (0x1fUL << LCD_PAL212_G04_0_Pos)                          /*!< LCD PAL212: G04_0 Mask              */
+#define LCD_PAL212_B04_0_Pos                                  10                                                        /*!< LCD PAL212: B04_0 Position          */
+#define LCD_PAL212_B04_0_Msk                                  (0x1fUL << LCD_PAL212_B04_0_Pos)                          /*!< LCD PAL212: B04_0 Mask              */
+#define LCD_PAL212_I0_Pos                                     15                                                        /*!< LCD PAL212: I0 Position             */
+#define LCD_PAL212_I0_Msk                                     (0x01UL << LCD_PAL212_I0_Pos)                             /*!< LCD PAL212: I0 Mask                 */
+#define LCD_PAL212_R14_0_Pos                                  16                                                        /*!< LCD PAL212: R14_0 Position          */
+#define LCD_PAL212_R14_0_Msk                                  (0x1fUL << LCD_PAL212_R14_0_Pos)                          /*!< LCD PAL212: R14_0 Mask              */
+#define LCD_PAL212_G14_0_Pos                                  21                                                        /*!< LCD PAL212: G14_0 Position          */
+#define LCD_PAL212_G14_0_Msk                                  (0x1fUL << LCD_PAL212_G14_0_Pos)                          /*!< LCD PAL212: G14_0 Mask              */
+#define LCD_PAL212_B14_0_Pos                                  26                                                        /*!< LCD PAL212: B14_0 Position          */
+#define LCD_PAL212_B14_0_Msk                                  (0x1fUL << LCD_PAL212_B14_0_Pos)                          /*!< LCD PAL212: B14_0 Mask              */
+#define LCD_PAL212_I1_Pos                                     31                                                        /*!< LCD PAL212: I1 Position             */
+#define LCD_PAL212_I1_Msk                                     (0x01UL << LCD_PAL212_I1_Pos)                             /*!< LCD PAL212: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL213  -------------------------------------------
+#define LCD_PAL213_R04_0_Pos                                  0                                                         /*!< LCD PAL213: R04_0 Position          */
+#define LCD_PAL213_R04_0_Msk                                  (0x1fUL << LCD_PAL213_R04_0_Pos)                          /*!< LCD PAL213: R04_0 Mask              */
+#define LCD_PAL213_G04_0_Pos                                  5                                                         /*!< LCD PAL213: G04_0 Position          */
+#define LCD_PAL213_G04_0_Msk                                  (0x1fUL << LCD_PAL213_G04_0_Pos)                          /*!< LCD PAL213: G04_0 Mask              */
+#define LCD_PAL213_B04_0_Pos                                  10                                                        /*!< LCD PAL213: B04_0 Position          */
+#define LCD_PAL213_B04_0_Msk                                  (0x1fUL << LCD_PAL213_B04_0_Pos)                          /*!< LCD PAL213: B04_0 Mask              */
+#define LCD_PAL213_I0_Pos                                     15                                                        /*!< LCD PAL213: I0 Position             */
+#define LCD_PAL213_I0_Msk                                     (0x01UL << LCD_PAL213_I0_Pos)                             /*!< LCD PAL213: I0 Mask                 */
+#define LCD_PAL213_R14_0_Pos                                  16                                                        /*!< LCD PAL213: R14_0 Position          */
+#define LCD_PAL213_R14_0_Msk                                  (0x1fUL << LCD_PAL213_R14_0_Pos)                          /*!< LCD PAL213: R14_0 Mask              */
+#define LCD_PAL213_G14_0_Pos                                  21                                                        /*!< LCD PAL213: G14_0 Position          */
+#define LCD_PAL213_G14_0_Msk                                  (0x1fUL << LCD_PAL213_G14_0_Pos)                          /*!< LCD PAL213: G14_0 Mask              */
+#define LCD_PAL213_B14_0_Pos                                  26                                                        /*!< LCD PAL213: B14_0 Position          */
+#define LCD_PAL213_B14_0_Msk                                  (0x1fUL << LCD_PAL213_B14_0_Pos)                          /*!< LCD PAL213: B14_0 Mask              */
+#define LCD_PAL213_I1_Pos                                     31                                                        /*!< LCD PAL213: I1 Position             */
+#define LCD_PAL213_I1_Msk                                     (0x01UL << LCD_PAL213_I1_Pos)                             /*!< LCD PAL213: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL214  -------------------------------------------
+#define LCD_PAL214_R04_0_Pos                                  0                                                         /*!< LCD PAL214: R04_0 Position          */
+#define LCD_PAL214_R04_0_Msk                                  (0x1fUL << LCD_PAL214_R04_0_Pos)                          /*!< LCD PAL214: R04_0 Mask              */
+#define LCD_PAL214_G04_0_Pos                                  5                                                         /*!< LCD PAL214: G04_0 Position          */
+#define LCD_PAL214_G04_0_Msk                                  (0x1fUL << LCD_PAL214_G04_0_Pos)                          /*!< LCD PAL214: G04_0 Mask              */
+#define LCD_PAL214_B04_0_Pos                                  10                                                        /*!< LCD PAL214: B04_0 Position          */
+#define LCD_PAL214_B04_0_Msk                                  (0x1fUL << LCD_PAL214_B04_0_Pos)                          /*!< LCD PAL214: B04_0 Mask              */
+#define LCD_PAL214_I0_Pos                                     15                                                        /*!< LCD PAL214: I0 Position             */
+#define LCD_PAL214_I0_Msk                                     (0x01UL << LCD_PAL214_I0_Pos)                             /*!< LCD PAL214: I0 Mask                 */
+#define LCD_PAL214_R14_0_Pos                                  16                                                        /*!< LCD PAL214: R14_0 Position          */
+#define LCD_PAL214_R14_0_Msk                                  (0x1fUL << LCD_PAL214_R14_0_Pos)                          /*!< LCD PAL214: R14_0 Mask              */
+#define LCD_PAL214_G14_0_Pos                                  21                                                        /*!< LCD PAL214: G14_0 Position          */
+#define LCD_PAL214_G14_0_Msk                                  (0x1fUL << LCD_PAL214_G14_0_Pos)                          /*!< LCD PAL214: G14_0 Mask              */
+#define LCD_PAL214_B14_0_Pos                                  26                                                        /*!< LCD PAL214: B14_0 Position          */
+#define LCD_PAL214_B14_0_Msk                                  (0x1fUL << LCD_PAL214_B14_0_Pos)                          /*!< LCD PAL214: B14_0 Mask              */
+#define LCD_PAL214_I1_Pos                                     31                                                        /*!< LCD PAL214: I1 Position             */
+#define LCD_PAL214_I1_Msk                                     (0x01UL << LCD_PAL214_I1_Pos)                             /*!< LCD PAL214: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL215  -------------------------------------------
+#define LCD_PAL215_R04_0_Pos                                  0                                                         /*!< LCD PAL215: R04_0 Position          */
+#define LCD_PAL215_R04_0_Msk                                  (0x1fUL << LCD_PAL215_R04_0_Pos)                          /*!< LCD PAL215: R04_0 Mask              */
+#define LCD_PAL215_G04_0_Pos                                  5                                                         /*!< LCD PAL215: G04_0 Position          */
+#define LCD_PAL215_G04_0_Msk                                  (0x1fUL << LCD_PAL215_G04_0_Pos)                          /*!< LCD PAL215: G04_0 Mask              */
+#define LCD_PAL215_B04_0_Pos                                  10                                                        /*!< LCD PAL215: B04_0 Position          */
+#define LCD_PAL215_B04_0_Msk                                  (0x1fUL << LCD_PAL215_B04_0_Pos)                          /*!< LCD PAL215: B04_0 Mask              */
+#define LCD_PAL215_I0_Pos                                     15                                                        /*!< LCD PAL215: I0 Position             */
+#define LCD_PAL215_I0_Msk                                     (0x01UL << LCD_PAL215_I0_Pos)                             /*!< LCD PAL215: I0 Mask                 */
+#define LCD_PAL215_R14_0_Pos                                  16                                                        /*!< LCD PAL215: R14_0 Position          */
+#define LCD_PAL215_R14_0_Msk                                  (0x1fUL << LCD_PAL215_R14_0_Pos)                          /*!< LCD PAL215: R14_0 Mask              */
+#define LCD_PAL215_G14_0_Pos                                  21                                                        /*!< LCD PAL215: G14_0 Position          */
+#define LCD_PAL215_G14_0_Msk                                  (0x1fUL << LCD_PAL215_G14_0_Pos)                          /*!< LCD PAL215: G14_0 Mask              */
+#define LCD_PAL215_B14_0_Pos                                  26                                                        /*!< LCD PAL215: B14_0 Position          */
+#define LCD_PAL215_B14_0_Msk                                  (0x1fUL << LCD_PAL215_B14_0_Pos)                          /*!< LCD PAL215: B14_0 Mask              */
+#define LCD_PAL215_I1_Pos                                     31                                                        /*!< LCD PAL215: I1 Position             */
+#define LCD_PAL215_I1_Msk                                     (0x01UL << LCD_PAL215_I1_Pos)                             /*!< LCD PAL215: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL216  -------------------------------------------
+#define LCD_PAL216_R04_0_Pos                                  0                                                         /*!< LCD PAL216: R04_0 Position          */
+#define LCD_PAL216_R04_0_Msk                                  (0x1fUL << LCD_PAL216_R04_0_Pos)                          /*!< LCD PAL216: R04_0 Mask              */
+#define LCD_PAL216_G04_0_Pos                                  5                                                         /*!< LCD PAL216: G04_0 Position          */
+#define LCD_PAL216_G04_0_Msk                                  (0x1fUL << LCD_PAL216_G04_0_Pos)                          /*!< LCD PAL216: G04_0 Mask              */
+#define LCD_PAL216_B04_0_Pos                                  10                                                        /*!< LCD PAL216: B04_0 Position          */
+#define LCD_PAL216_B04_0_Msk                                  (0x1fUL << LCD_PAL216_B04_0_Pos)                          /*!< LCD PAL216: B04_0 Mask              */
+#define LCD_PAL216_I0_Pos                                     15                                                        /*!< LCD PAL216: I0 Position             */
+#define LCD_PAL216_I0_Msk                                     (0x01UL << LCD_PAL216_I0_Pos)                             /*!< LCD PAL216: I0 Mask                 */
+#define LCD_PAL216_R14_0_Pos                                  16                                                        /*!< LCD PAL216: R14_0 Position          */
+#define LCD_PAL216_R14_0_Msk                                  (0x1fUL << LCD_PAL216_R14_0_Pos)                          /*!< LCD PAL216: R14_0 Mask              */
+#define LCD_PAL216_G14_0_Pos                                  21                                                        /*!< LCD PAL216: G14_0 Position          */
+#define LCD_PAL216_G14_0_Msk                                  (0x1fUL << LCD_PAL216_G14_0_Pos)                          /*!< LCD PAL216: G14_0 Mask              */
+#define LCD_PAL216_B14_0_Pos                                  26                                                        /*!< LCD PAL216: B14_0 Position          */
+#define LCD_PAL216_B14_0_Msk                                  (0x1fUL << LCD_PAL216_B14_0_Pos)                          /*!< LCD PAL216: B14_0 Mask              */
+#define LCD_PAL216_I1_Pos                                     31                                                        /*!< LCD PAL216: I1 Position             */
+#define LCD_PAL216_I1_Msk                                     (0x01UL << LCD_PAL216_I1_Pos)                             /*!< LCD PAL216: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL217  -------------------------------------------
+#define LCD_PAL217_R04_0_Pos                                  0                                                         /*!< LCD PAL217: R04_0 Position          */
+#define LCD_PAL217_R04_0_Msk                                  (0x1fUL << LCD_PAL217_R04_0_Pos)                          /*!< LCD PAL217: R04_0 Mask              */
+#define LCD_PAL217_G04_0_Pos                                  5                                                         /*!< LCD PAL217: G04_0 Position          */
+#define LCD_PAL217_G04_0_Msk                                  (0x1fUL << LCD_PAL217_G04_0_Pos)                          /*!< LCD PAL217: G04_0 Mask              */
+#define LCD_PAL217_B04_0_Pos                                  10                                                        /*!< LCD PAL217: B04_0 Position          */
+#define LCD_PAL217_B04_0_Msk                                  (0x1fUL << LCD_PAL217_B04_0_Pos)                          /*!< LCD PAL217: B04_0 Mask              */
+#define LCD_PAL217_I0_Pos                                     15                                                        /*!< LCD PAL217: I0 Position             */
+#define LCD_PAL217_I0_Msk                                     (0x01UL << LCD_PAL217_I0_Pos)                             /*!< LCD PAL217: I0 Mask                 */
+#define LCD_PAL217_R14_0_Pos                                  16                                                        /*!< LCD PAL217: R14_0 Position          */
+#define LCD_PAL217_R14_0_Msk                                  (0x1fUL << LCD_PAL217_R14_0_Pos)                          /*!< LCD PAL217: R14_0 Mask              */
+#define LCD_PAL217_G14_0_Pos                                  21                                                        /*!< LCD PAL217: G14_0 Position          */
+#define LCD_PAL217_G14_0_Msk                                  (0x1fUL << LCD_PAL217_G14_0_Pos)                          /*!< LCD PAL217: G14_0 Mask              */
+#define LCD_PAL217_B14_0_Pos                                  26                                                        /*!< LCD PAL217: B14_0 Position          */
+#define LCD_PAL217_B14_0_Msk                                  (0x1fUL << LCD_PAL217_B14_0_Pos)                          /*!< LCD PAL217: B14_0 Mask              */
+#define LCD_PAL217_I1_Pos                                     31                                                        /*!< LCD PAL217: I1 Position             */
+#define LCD_PAL217_I1_Msk                                     (0x01UL << LCD_PAL217_I1_Pos)                             /*!< LCD PAL217: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL218  -------------------------------------------
+#define LCD_PAL218_R04_0_Pos                                  0                                                         /*!< LCD PAL218: R04_0 Position          */
+#define LCD_PAL218_R04_0_Msk                                  (0x1fUL << LCD_PAL218_R04_0_Pos)                          /*!< LCD PAL218: R04_0 Mask              */
+#define LCD_PAL218_G04_0_Pos                                  5                                                         /*!< LCD PAL218: G04_0 Position          */
+#define LCD_PAL218_G04_0_Msk                                  (0x1fUL << LCD_PAL218_G04_0_Pos)                          /*!< LCD PAL218: G04_0 Mask              */
+#define LCD_PAL218_B04_0_Pos                                  10                                                        /*!< LCD PAL218: B04_0 Position          */
+#define LCD_PAL218_B04_0_Msk                                  (0x1fUL << LCD_PAL218_B04_0_Pos)                          /*!< LCD PAL218: B04_0 Mask              */
+#define LCD_PAL218_I0_Pos                                     15                                                        /*!< LCD PAL218: I0 Position             */
+#define LCD_PAL218_I0_Msk                                     (0x01UL << LCD_PAL218_I0_Pos)                             /*!< LCD PAL218: I0 Mask                 */
+#define LCD_PAL218_R14_0_Pos                                  16                                                        /*!< LCD PAL218: R14_0 Position          */
+#define LCD_PAL218_R14_0_Msk                                  (0x1fUL << LCD_PAL218_R14_0_Pos)                          /*!< LCD PAL218: R14_0 Mask              */
+#define LCD_PAL218_G14_0_Pos                                  21                                                        /*!< LCD PAL218: G14_0 Position          */
+#define LCD_PAL218_G14_0_Msk                                  (0x1fUL << LCD_PAL218_G14_0_Pos)                          /*!< LCD PAL218: G14_0 Mask              */
+#define LCD_PAL218_B14_0_Pos                                  26                                                        /*!< LCD PAL218: B14_0 Position          */
+#define LCD_PAL218_B14_0_Msk                                  (0x1fUL << LCD_PAL218_B14_0_Pos)                          /*!< LCD PAL218: B14_0 Mask              */
+#define LCD_PAL218_I1_Pos                                     31                                                        /*!< LCD PAL218: I1 Position             */
+#define LCD_PAL218_I1_Msk                                     (0x01UL << LCD_PAL218_I1_Pos)                             /*!< LCD PAL218: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL219  -------------------------------------------
+#define LCD_PAL219_R04_0_Pos                                  0                                                         /*!< LCD PAL219: R04_0 Position          */
+#define LCD_PAL219_R04_0_Msk                                  (0x1fUL << LCD_PAL219_R04_0_Pos)                          /*!< LCD PAL219: R04_0 Mask              */
+#define LCD_PAL219_G04_0_Pos                                  5                                                         /*!< LCD PAL219: G04_0 Position          */
+#define LCD_PAL219_G04_0_Msk                                  (0x1fUL << LCD_PAL219_G04_0_Pos)                          /*!< LCD PAL219: G04_0 Mask              */
+#define LCD_PAL219_B04_0_Pos                                  10                                                        /*!< LCD PAL219: B04_0 Position          */
+#define LCD_PAL219_B04_0_Msk                                  (0x1fUL << LCD_PAL219_B04_0_Pos)                          /*!< LCD PAL219: B04_0 Mask              */
+#define LCD_PAL219_I0_Pos                                     15                                                        /*!< LCD PAL219: I0 Position             */
+#define LCD_PAL219_I0_Msk                                     (0x01UL << LCD_PAL219_I0_Pos)                             /*!< LCD PAL219: I0 Mask                 */
+#define LCD_PAL219_R14_0_Pos                                  16                                                        /*!< LCD PAL219: R14_0 Position          */
+#define LCD_PAL219_R14_0_Msk                                  (0x1fUL << LCD_PAL219_R14_0_Pos)                          /*!< LCD PAL219: R14_0 Mask              */
+#define LCD_PAL219_G14_0_Pos                                  21                                                        /*!< LCD PAL219: G14_0 Position          */
+#define LCD_PAL219_G14_0_Msk                                  (0x1fUL << LCD_PAL219_G14_0_Pos)                          /*!< LCD PAL219: G14_0 Mask              */
+#define LCD_PAL219_B14_0_Pos                                  26                                                        /*!< LCD PAL219: B14_0 Position          */
+#define LCD_PAL219_B14_0_Msk                                  (0x1fUL << LCD_PAL219_B14_0_Pos)                          /*!< LCD PAL219: B14_0 Mask              */
+#define LCD_PAL219_I1_Pos                                     31                                                        /*!< LCD PAL219: I1 Position             */
+#define LCD_PAL219_I1_Msk                                     (0x01UL << LCD_PAL219_I1_Pos)                             /*!< LCD PAL219: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL220  -------------------------------------------
+#define LCD_PAL220_R04_0_Pos                                  0                                                         /*!< LCD PAL220: R04_0 Position          */
+#define LCD_PAL220_R04_0_Msk                                  (0x1fUL << LCD_PAL220_R04_0_Pos)                          /*!< LCD PAL220: R04_0 Mask              */
+#define LCD_PAL220_G04_0_Pos                                  5                                                         /*!< LCD PAL220: G04_0 Position          */
+#define LCD_PAL220_G04_0_Msk                                  (0x1fUL << LCD_PAL220_G04_0_Pos)                          /*!< LCD PAL220: G04_0 Mask              */
+#define LCD_PAL220_B04_0_Pos                                  10                                                        /*!< LCD PAL220: B04_0 Position          */
+#define LCD_PAL220_B04_0_Msk                                  (0x1fUL << LCD_PAL220_B04_0_Pos)                          /*!< LCD PAL220: B04_0 Mask              */
+#define LCD_PAL220_I0_Pos                                     15                                                        /*!< LCD PAL220: I0 Position             */
+#define LCD_PAL220_I0_Msk                                     (0x01UL << LCD_PAL220_I0_Pos)                             /*!< LCD PAL220: I0 Mask                 */
+#define LCD_PAL220_R14_0_Pos                                  16                                                        /*!< LCD PAL220: R14_0 Position          */
+#define LCD_PAL220_R14_0_Msk                                  (0x1fUL << LCD_PAL220_R14_0_Pos)                          /*!< LCD PAL220: R14_0 Mask              */
+#define LCD_PAL220_G14_0_Pos                                  21                                                        /*!< LCD PAL220: G14_0 Position          */
+#define LCD_PAL220_G14_0_Msk                                  (0x1fUL << LCD_PAL220_G14_0_Pos)                          /*!< LCD PAL220: G14_0 Mask              */
+#define LCD_PAL220_B14_0_Pos                                  26                                                        /*!< LCD PAL220: B14_0 Position          */
+#define LCD_PAL220_B14_0_Msk                                  (0x1fUL << LCD_PAL220_B14_0_Pos)                          /*!< LCD PAL220: B14_0 Mask              */
+#define LCD_PAL220_I1_Pos                                     31                                                        /*!< LCD PAL220: I1 Position             */
+#define LCD_PAL220_I1_Msk                                     (0x01UL << LCD_PAL220_I1_Pos)                             /*!< LCD PAL220: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL221  -------------------------------------------
+#define LCD_PAL221_R04_0_Pos                                  0                                                         /*!< LCD PAL221: R04_0 Position          */
+#define LCD_PAL221_R04_0_Msk                                  (0x1fUL << LCD_PAL221_R04_0_Pos)                          /*!< LCD PAL221: R04_0 Mask              */
+#define LCD_PAL221_G04_0_Pos                                  5                                                         /*!< LCD PAL221: G04_0 Position          */
+#define LCD_PAL221_G04_0_Msk                                  (0x1fUL << LCD_PAL221_G04_0_Pos)                          /*!< LCD PAL221: G04_0 Mask              */
+#define LCD_PAL221_B04_0_Pos                                  10                                                        /*!< LCD PAL221: B04_0 Position          */
+#define LCD_PAL221_B04_0_Msk                                  (0x1fUL << LCD_PAL221_B04_0_Pos)                          /*!< LCD PAL221: B04_0 Mask              */
+#define LCD_PAL221_I0_Pos                                     15                                                        /*!< LCD PAL221: I0 Position             */
+#define LCD_PAL221_I0_Msk                                     (0x01UL << LCD_PAL221_I0_Pos)                             /*!< LCD PAL221: I0 Mask                 */
+#define LCD_PAL221_R14_0_Pos                                  16                                                        /*!< LCD PAL221: R14_0 Position          */
+#define LCD_PAL221_R14_0_Msk                                  (0x1fUL << LCD_PAL221_R14_0_Pos)                          /*!< LCD PAL221: R14_0 Mask              */
+#define LCD_PAL221_G14_0_Pos                                  21                                                        /*!< LCD PAL221: G14_0 Position          */
+#define LCD_PAL221_G14_0_Msk                                  (0x1fUL << LCD_PAL221_G14_0_Pos)                          /*!< LCD PAL221: G14_0 Mask              */
+#define LCD_PAL221_B14_0_Pos                                  26                                                        /*!< LCD PAL221: B14_0 Position          */
+#define LCD_PAL221_B14_0_Msk                                  (0x1fUL << LCD_PAL221_B14_0_Pos)                          /*!< LCD PAL221: B14_0 Mask              */
+#define LCD_PAL221_I1_Pos                                     31                                                        /*!< LCD PAL221: I1 Position             */
+#define LCD_PAL221_I1_Msk                                     (0x01UL << LCD_PAL221_I1_Pos)                             /*!< LCD PAL221: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL222  -------------------------------------------
+#define LCD_PAL222_R04_0_Pos                                  0                                                         /*!< LCD PAL222: R04_0 Position          */
+#define LCD_PAL222_R04_0_Msk                                  (0x1fUL << LCD_PAL222_R04_0_Pos)                          /*!< LCD PAL222: R04_0 Mask              */
+#define LCD_PAL222_G04_0_Pos                                  5                                                         /*!< LCD PAL222: G04_0 Position          */
+#define LCD_PAL222_G04_0_Msk                                  (0x1fUL << LCD_PAL222_G04_0_Pos)                          /*!< LCD PAL222: G04_0 Mask              */
+#define LCD_PAL222_B04_0_Pos                                  10                                                        /*!< LCD PAL222: B04_0 Position          */
+#define LCD_PAL222_B04_0_Msk                                  (0x1fUL << LCD_PAL222_B04_0_Pos)                          /*!< LCD PAL222: B04_0 Mask              */
+#define LCD_PAL222_I0_Pos                                     15                                                        /*!< LCD PAL222: I0 Position             */
+#define LCD_PAL222_I0_Msk                                     (0x01UL << LCD_PAL222_I0_Pos)                             /*!< LCD PAL222: I0 Mask                 */
+#define LCD_PAL222_R14_0_Pos                                  16                                                        /*!< LCD PAL222: R14_0 Position          */
+#define LCD_PAL222_R14_0_Msk                                  (0x1fUL << LCD_PAL222_R14_0_Pos)                          /*!< LCD PAL222: R14_0 Mask              */
+#define LCD_PAL222_G14_0_Pos                                  21                                                        /*!< LCD PAL222: G14_0 Position          */
+#define LCD_PAL222_G14_0_Msk                                  (0x1fUL << LCD_PAL222_G14_0_Pos)                          /*!< LCD PAL222: G14_0 Mask              */
+#define LCD_PAL222_B14_0_Pos                                  26                                                        /*!< LCD PAL222: B14_0 Position          */
+#define LCD_PAL222_B14_0_Msk                                  (0x1fUL << LCD_PAL222_B14_0_Pos)                          /*!< LCD PAL222: B14_0 Mask              */
+#define LCD_PAL222_I1_Pos                                     31                                                        /*!< LCD PAL222: I1 Position             */
+#define LCD_PAL222_I1_Msk                                     (0x01UL << LCD_PAL222_I1_Pos)                             /*!< LCD PAL222: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL223  -------------------------------------------
+#define LCD_PAL223_R04_0_Pos                                  0                                                         /*!< LCD PAL223: R04_0 Position          */
+#define LCD_PAL223_R04_0_Msk                                  (0x1fUL << LCD_PAL223_R04_0_Pos)                          /*!< LCD PAL223: R04_0 Mask              */
+#define LCD_PAL223_G04_0_Pos                                  5                                                         /*!< LCD PAL223: G04_0 Position          */
+#define LCD_PAL223_G04_0_Msk                                  (0x1fUL << LCD_PAL223_G04_0_Pos)                          /*!< LCD PAL223: G04_0 Mask              */
+#define LCD_PAL223_B04_0_Pos                                  10                                                        /*!< LCD PAL223: B04_0 Position          */
+#define LCD_PAL223_B04_0_Msk                                  (0x1fUL << LCD_PAL223_B04_0_Pos)                          /*!< LCD PAL223: B04_0 Mask              */
+#define LCD_PAL223_I0_Pos                                     15                                                        /*!< LCD PAL223: I0 Position             */
+#define LCD_PAL223_I0_Msk                                     (0x01UL << LCD_PAL223_I0_Pos)                             /*!< LCD PAL223: I0 Mask                 */
+#define LCD_PAL223_R14_0_Pos                                  16                                                        /*!< LCD PAL223: R14_0 Position          */
+#define LCD_PAL223_R14_0_Msk                                  (0x1fUL << LCD_PAL223_R14_0_Pos)                          /*!< LCD PAL223: R14_0 Mask              */
+#define LCD_PAL223_G14_0_Pos                                  21                                                        /*!< LCD PAL223: G14_0 Position          */
+#define LCD_PAL223_G14_0_Msk                                  (0x1fUL << LCD_PAL223_G14_0_Pos)                          /*!< LCD PAL223: G14_0 Mask              */
+#define LCD_PAL223_B14_0_Pos                                  26                                                        /*!< LCD PAL223: B14_0 Position          */
+#define LCD_PAL223_B14_0_Msk                                  (0x1fUL << LCD_PAL223_B14_0_Pos)                          /*!< LCD PAL223: B14_0 Mask              */
+#define LCD_PAL223_I1_Pos                                     31                                                        /*!< LCD PAL223: I1 Position             */
+#define LCD_PAL223_I1_Msk                                     (0x01UL << LCD_PAL223_I1_Pos)                             /*!< LCD PAL223: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL224  -------------------------------------------
+#define LCD_PAL224_R04_0_Pos                                  0                                                         /*!< LCD PAL224: R04_0 Position          */
+#define LCD_PAL224_R04_0_Msk                                  (0x1fUL << LCD_PAL224_R04_0_Pos)                          /*!< LCD PAL224: R04_0 Mask              */
+#define LCD_PAL224_G04_0_Pos                                  5                                                         /*!< LCD PAL224: G04_0 Position          */
+#define LCD_PAL224_G04_0_Msk                                  (0x1fUL << LCD_PAL224_G04_0_Pos)                          /*!< LCD PAL224: G04_0 Mask              */
+#define LCD_PAL224_B04_0_Pos                                  10                                                        /*!< LCD PAL224: B04_0 Position          */
+#define LCD_PAL224_B04_0_Msk                                  (0x1fUL << LCD_PAL224_B04_0_Pos)                          /*!< LCD PAL224: B04_0 Mask              */
+#define LCD_PAL224_I0_Pos                                     15                                                        /*!< LCD PAL224: I0 Position             */
+#define LCD_PAL224_I0_Msk                                     (0x01UL << LCD_PAL224_I0_Pos)                             /*!< LCD PAL224: I0 Mask                 */
+#define LCD_PAL224_R14_0_Pos                                  16                                                        /*!< LCD PAL224: R14_0 Position          */
+#define LCD_PAL224_R14_0_Msk                                  (0x1fUL << LCD_PAL224_R14_0_Pos)                          /*!< LCD PAL224: R14_0 Mask              */
+#define LCD_PAL224_G14_0_Pos                                  21                                                        /*!< LCD PAL224: G14_0 Position          */
+#define LCD_PAL224_G14_0_Msk                                  (0x1fUL << LCD_PAL224_G14_0_Pos)                          /*!< LCD PAL224: G14_0 Mask              */
+#define LCD_PAL224_B14_0_Pos                                  26                                                        /*!< LCD PAL224: B14_0 Position          */
+#define LCD_PAL224_B14_0_Msk                                  (0x1fUL << LCD_PAL224_B14_0_Pos)                          /*!< LCD PAL224: B14_0 Mask              */
+#define LCD_PAL224_I1_Pos                                     31                                                        /*!< LCD PAL224: I1 Position             */
+#define LCD_PAL224_I1_Msk                                     (0x01UL << LCD_PAL224_I1_Pos)                             /*!< LCD PAL224: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL225  -------------------------------------------
+#define LCD_PAL225_R04_0_Pos                                  0                                                         /*!< LCD PAL225: R04_0 Position          */
+#define LCD_PAL225_R04_0_Msk                                  (0x1fUL << LCD_PAL225_R04_0_Pos)                          /*!< LCD PAL225: R04_0 Mask              */
+#define LCD_PAL225_G04_0_Pos                                  5                                                         /*!< LCD PAL225: G04_0 Position          */
+#define LCD_PAL225_G04_0_Msk                                  (0x1fUL << LCD_PAL225_G04_0_Pos)                          /*!< LCD PAL225: G04_0 Mask              */
+#define LCD_PAL225_B04_0_Pos                                  10                                                        /*!< LCD PAL225: B04_0 Position          */
+#define LCD_PAL225_B04_0_Msk                                  (0x1fUL << LCD_PAL225_B04_0_Pos)                          /*!< LCD PAL225: B04_0 Mask              */
+#define LCD_PAL225_I0_Pos                                     15                                                        /*!< LCD PAL225: I0 Position             */
+#define LCD_PAL225_I0_Msk                                     (0x01UL << LCD_PAL225_I0_Pos)                             /*!< LCD PAL225: I0 Mask                 */
+#define LCD_PAL225_R14_0_Pos                                  16                                                        /*!< LCD PAL225: R14_0 Position          */
+#define LCD_PAL225_R14_0_Msk                                  (0x1fUL << LCD_PAL225_R14_0_Pos)                          /*!< LCD PAL225: R14_0 Mask              */
+#define LCD_PAL225_G14_0_Pos                                  21                                                        /*!< LCD PAL225: G14_0 Position          */
+#define LCD_PAL225_G14_0_Msk                                  (0x1fUL << LCD_PAL225_G14_0_Pos)                          /*!< LCD PAL225: G14_0 Mask              */
+#define LCD_PAL225_B14_0_Pos                                  26                                                        /*!< LCD PAL225: B14_0 Position          */
+#define LCD_PAL225_B14_0_Msk                                  (0x1fUL << LCD_PAL225_B14_0_Pos)                          /*!< LCD PAL225: B14_0 Mask              */
+#define LCD_PAL225_I1_Pos                                     31                                                        /*!< LCD PAL225: I1 Position             */
+#define LCD_PAL225_I1_Msk                                     (0x01UL << LCD_PAL225_I1_Pos)                             /*!< LCD PAL225: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL226  -------------------------------------------
+#define LCD_PAL226_R04_0_Pos                                  0                                                         /*!< LCD PAL226: R04_0 Position          */
+#define LCD_PAL226_R04_0_Msk                                  (0x1fUL << LCD_PAL226_R04_0_Pos)                          /*!< LCD PAL226: R04_0 Mask              */
+#define LCD_PAL226_G04_0_Pos                                  5                                                         /*!< LCD PAL226: G04_0 Position          */
+#define LCD_PAL226_G04_0_Msk                                  (0x1fUL << LCD_PAL226_G04_0_Pos)                          /*!< LCD PAL226: G04_0 Mask              */
+#define LCD_PAL226_B04_0_Pos                                  10                                                        /*!< LCD PAL226: B04_0 Position          */
+#define LCD_PAL226_B04_0_Msk                                  (0x1fUL << LCD_PAL226_B04_0_Pos)                          /*!< LCD PAL226: B04_0 Mask              */
+#define LCD_PAL226_I0_Pos                                     15                                                        /*!< LCD PAL226: I0 Position             */
+#define LCD_PAL226_I0_Msk                                     (0x01UL << LCD_PAL226_I0_Pos)                             /*!< LCD PAL226: I0 Mask                 */
+#define LCD_PAL226_R14_0_Pos                                  16                                                        /*!< LCD PAL226: R14_0 Position          */
+#define LCD_PAL226_R14_0_Msk                                  (0x1fUL << LCD_PAL226_R14_0_Pos)                          /*!< LCD PAL226: R14_0 Mask              */
+#define LCD_PAL226_G14_0_Pos                                  21                                                        /*!< LCD PAL226: G14_0 Position          */
+#define LCD_PAL226_G14_0_Msk                                  (0x1fUL << LCD_PAL226_G14_0_Pos)                          /*!< LCD PAL226: G14_0 Mask              */
+#define LCD_PAL226_B14_0_Pos                                  26                                                        /*!< LCD PAL226: B14_0 Position          */
+#define LCD_PAL226_B14_0_Msk                                  (0x1fUL << LCD_PAL226_B14_0_Pos)                          /*!< LCD PAL226: B14_0 Mask              */
+#define LCD_PAL226_I1_Pos                                     31                                                        /*!< LCD PAL226: I1 Position             */
+#define LCD_PAL226_I1_Msk                                     (0x01UL << LCD_PAL226_I1_Pos)                             /*!< LCD PAL226: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL227  -------------------------------------------
+#define LCD_PAL227_R04_0_Pos                                  0                                                         /*!< LCD PAL227: R04_0 Position          */
+#define LCD_PAL227_R04_0_Msk                                  (0x1fUL << LCD_PAL227_R04_0_Pos)                          /*!< LCD PAL227: R04_0 Mask              */
+#define LCD_PAL227_G04_0_Pos                                  5                                                         /*!< LCD PAL227: G04_0 Position          */
+#define LCD_PAL227_G04_0_Msk                                  (0x1fUL << LCD_PAL227_G04_0_Pos)                          /*!< LCD PAL227: G04_0 Mask              */
+#define LCD_PAL227_B04_0_Pos                                  10                                                        /*!< LCD PAL227: B04_0 Position          */
+#define LCD_PAL227_B04_0_Msk                                  (0x1fUL << LCD_PAL227_B04_0_Pos)                          /*!< LCD PAL227: B04_0 Mask              */
+#define LCD_PAL227_I0_Pos                                     15                                                        /*!< LCD PAL227: I0 Position             */
+#define LCD_PAL227_I0_Msk                                     (0x01UL << LCD_PAL227_I0_Pos)                             /*!< LCD PAL227: I0 Mask                 */
+#define LCD_PAL227_R14_0_Pos                                  16                                                        /*!< LCD PAL227: R14_0 Position          */
+#define LCD_PAL227_R14_0_Msk                                  (0x1fUL << LCD_PAL227_R14_0_Pos)                          /*!< LCD PAL227: R14_0 Mask              */
+#define LCD_PAL227_G14_0_Pos                                  21                                                        /*!< LCD PAL227: G14_0 Position          */
+#define LCD_PAL227_G14_0_Msk                                  (0x1fUL << LCD_PAL227_G14_0_Pos)                          /*!< LCD PAL227: G14_0 Mask              */
+#define LCD_PAL227_B14_0_Pos                                  26                                                        /*!< LCD PAL227: B14_0 Position          */
+#define LCD_PAL227_B14_0_Msk                                  (0x1fUL << LCD_PAL227_B14_0_Pos)                          /*!< LCD PAL227: B14_0 Mask              */
+#define LCD_PAL227_I1_Pos                                     31                                                        /*!< LCD PAL227: I1 Position             */
+#define LCD_PAL227_I1_Msk                                     (0x01UL << LCD_PAL227_I1_Pos)                             /*!< LCD PAL227: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL228  -------------------------------------------
+#define LCD_PAL228_R04_0_Pos                                  0                                                         /*!< LCD PAL228: R04_0 Position          */
+#define LCD_PAL228_R04_0_Msk                                  (0x1fUL << LCD_PAL228_R04_0_Pos)                          /*!< LCD PAL228: R04_0 Mask              */
+#define LCD_PAL228_G04_0_Pos                                  5                                                         /*!< LCD PAL228: G04_0 Position          */
+#define LCD_PAL228_G04_0_Msk                                  (0x1fUL << LCD_PAL228_G04_0_Pos)                          /*!< LCD PAL228: G04_0 Mask              */
+#define LCD_PAL228_B04_0_Pos                                  10                                                        /*!< LCD PAL228: B04_0 Position          */
+#define LCD_PAL228_B04_0_Msk                                  (0x1fUL << LCD_PAL228_B04_0_Pos)                          /*!< LCD PAL228: B04_0 Mask              */
+#define LCD_PAL228_I0_Pos                                     15                                                        /*!< LCD PAL228: I0 Position             */
+#define LCD_PAL228_I0_Msk                                     (0x01UL << LCD_PAL228_I0_Pos)                             /*!< LCD PAL228: I0 Mask                 */
+#define LCD_PAL228_R14_0_Pos                                  16                                                        /*!< LCD PAL228: R14_0 Position          */
+#define LCD_PAL228_R14_0_Msk                                  (0x1fUL << LCD_PAL228_R14_0_Pos)                          /*!< LCD PAL228: R14_0 Mask              */
+#define LCD_PAL228_G14_0_Pos                                  21                                                        /*!< LCD PAL228: G14_0 Position          */
+#define LCD_PAL228_G14_0_Msk                                  (0x1fUL << LCD_PAL228_G14_0_Pos)                          /*!< LCD PAL228: G14_0 Mask              */
+#define LCD_PAL228_B14_0_Pos                                  26                                                        /*!< LCD PAL228: B14_0 Position          */
+#define LCD_PAL228_B14_0_Msk                                  (0x1fUL << LCD_PAL228_B14_0_Pos)                          /*!< LCD PAL228: B14_0 Mask              */
+#define LCD_PAL228_I1_Pos                                     31                                                        /*!< LCD PAL228: I1 Position             */
+#define LCD_PAL228_I1_Msk                                     (0x01UL << LCD_PAL228_I1_Pos)                             /*!< LCD PAL228: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL229  -------------------------------------------
+#define LCD_PAL229_R04_0_Pos                                  0                                                         /*!< LCD PAL229: R04_0 Position          */
+#define LCD_PAL229_R04_0_Msk                                  (0x1fUL << LCD_PAL229_R04_0_Pos)                          /*!< LCD PAL229: R04_0 Mask              */
+#define LCD_PAL229_G04_0_Pos                                  5                                                         /*!< LCD PAL229: G04_0 Position          */
+#define LCD_PAL229_G04_0_Msk                                  (0x1fUL << LCD_PAL229_G04_0_Pos)                          /*!< LCD PAL229: G04_0 Mask              */
+#define LCD_PAL229_B04_0_Pos                                  10                                                        /*!< LCD PAL229: B04_0 Position          */
+#define LCD_PAL229_B04_0_Msk                                  (0x1fUL << LCD_PAL229_B04_0_Pos)                          /*!< LCD PAL229: B04_0 Mask              */
+#define LCD_PAL229_I0_Pos                                     15                                                        /*!< LCD PAL229: I0 Position             */
+#define LCD_PAL229_I0_Msk                                     (0x01UL << LCD_PAL229_I0_Pos)                             /*!< LCD PAL229: I0 Mask                 */
+#define LCD_PAL229_R14_0_Pos                                  16                                                        /*!< LCD PAL229: R14_0 Position          */
+#define LCD_PAL229_R14_0_Msk                                  (0x1fUL << LCD_PAL229_R14_0_Pos)                          /*!< LCD PAL229: R14_0 Mask              */
+#define LCD_PAL229_G14_0_Pos                                  21                                                        /*!< LCD PAL229: G14_0 Position          */
+#define LCD_PAL229_G14_0_Msk                                  (0x1fUL << LCD_PAL229_G14_0_Pos)                          /*!< LCD PAL229: G14_0 Mask              */
+#define LCD_PAL229_B14_0_Pos                                  26                                                        /*!< LCD PAL229: B14_0 Position          */
+#define LCD_PAL229_B14_0_Msk                                  (0x1fUL << LCD_PAL229_B14_0_Pos)                          /*!< LCD PAL229: B14_0 Mask              */
+#define LCD_PAL229_I1_Pos                                     31                                                        /*!< LCD PAL229: I1 Position             */
+#define LCD_PAL229_I1_Msk                                     (0x01UL << LCD_PAL229_I1_Pos)                             /*!< LCD PAL229: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL230  -------------------------------------------
+#define LCD_PAL230_R04_0_Pos                                  0                                                         /*!< LCD PAL230: R04_0 Position          */
+#define LCD_PAL230_R04_0_Msk                                  (0x1fUL << LCD_PAL230_R04_0_Pos)                          /*!< LCD PAL230: R04_0 Mask              */
+#define LCD_PAL230_G04_0_Pos                                  5                                                         /*!< LCD PAL230: G04_0 Position          */
+#define LCD_PAL230_G04_0_Msk                                  (0x1fUL << LCD_PAL230_G04_0_Pos)                          /*!< LCD PAL230: G04_0 Mask              */
+#define LCD_PAL230_B04_0_Pos                                  10                                                        /*!< LCD PAL230: B04_0 Position          */
+#define LCD_PAL230_B04_0_Msk                                  (0x1fUL << LCD_PAL230_B04_0_Pos)                          /*!< LCD PAL230: B04_0 Mask              */
+#define LCD_PAL230_I0_Pos                                     15                                                        /*!< LCD PAL230: I0 Position             */
+#define LCD_PAL230_I0_Msk                                     (0x01UL << LCD_PAL230_I0_Pos)                             /*!< LCD PAL230: I0 Mask                 */
+#define LCD_PAL230_R14_0_Pos                                  16                                                        /*!< LCD PAL230: R14_0 Position          */
+#define LCD_PAL230_R14_0_Msk                                  (0x1fUL << LCD_PAL230_R14_0_Pos)                          /*!< LCD PAL230: R14_0 Mask              */
+#define LCD_PAL230_G14_0_Pos                                  21                                                        /*!< LCD PAL230: G14_0 Position          */
+#define LCD_PAL230_G14_0_Msk                                  (0x1fUL << LCD_PAL230_G14_0_Pos)                          /*!< LCD PAL230: G14_0 Mask              */
+#define LCD_PAL230_B14_0_Pos                                  26                                                        /*!< LCD PAL230: B14_0 Position          */
+#define LCD_PAL230_B14_0_Msk                                  (0x1fUL << LCD_PAL230_B14_0_Pos)                          /*!< LCD PAL230: B14_0 Mask              */
+#define LCD_PAL230_I1_Pos                                     31                                                        /*!< LCD PAL230: I1 Position             */
+#define LCD_PAL230_I1_Msk                                     (0x01UL << LCD_PAL230_I1_Pos)                             /*!< LCD PAL230: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL231  -------------------------------------------
+#define LCD_PAL231_R04_0_Pos                                  0                                                         /*!< LCD PAL231: R04_0 Position          */
+#define LCD_PAL231_R04_0_Msk                                  (0x1fUL << LCD_PAL231_R04_0_Pos)                          /*!< LCD PAL231: R04_0 Mask              */
+#define LCD_PAL231_G04_0_Pos                                  5                                                         /*!< LCD PAL231: G04_0 Position          */
+#define LCD_PAL231_G04_0_Msk                                  (0x1fUL << LCD_PAL231_G04_0_Pos)                          /*!< LCD PAL231: G04_0 Mask              */
+#define LCD_PAL231_B04_0_Pos                                  10                                                        /*!< LCD PAL231: B04_0 Position          */
+#define LCD_PAL231_B04_0_Msk                                  (0x1fUL << LCD_PAL231_B04_0_Pos)                          /*!< LCD PAL231: B04_0 Mask              */
+#define LCD_PAL231_I0_Pos                                     15                                                        /*!< LCD PAL231: I0 Position             */
+#define LCD_PAL231_I0_Msk                                     (0x01UL << LCD_PAL231_I0_Pos)                             /*!< LCD PAL231: I0 Mask                 */
+#define LCD_PAL231_R14_0_Pos                                  16                                                        /*!< LCD PAL231: R14_0 Position          */
+#define LCD_PAL231_R14_0_Msk                                  (0x1fUL << LCD_PAL231_R14_0_Pos)                          /*!< LCD PAL231: R14_0 Mask              */
+#define LCD_PAL231_G14_0_Pos                                  21                                                        /*!< LCD PAL231: G14_0 Position          */
+#define LCD_PAL231_G14_0_Msk                                  (0x1fUL << LCD_PAL231_G14_0_Pos)                          /*!< LCD PAL231: G14_0 Mask              */
+#define LCD_PAL231_B14_0_Pos                                  26                                                        /*!< LCD PAL231: B14_0 Position          */
+#define LCD_PAL231_B14_0_Msk                                  (0x1fUL << LCD_PAL231_B14_0_Pos)                          /*!< LCD PAL231: B14_0 Mask              */
+#define LCD_PAL231_I1_Pos                                     31                                                        /*!< LCD PAL231: I1 Position             */
+#define LCD_PAL231_I1_Msk                                     (0x01UL << LCD_PAL231_I1_Pos)                             /*!< LCD PAL231: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL232  -------------------------------------------
+#define LCD_PAL232_R04_0_Pos                                  0                                                         /*!< LCD PAL232: R04_0 Position          */
+#define LCD_PAL232_R04_0_Msk                                  (0x1fUL << LCD_PAL232_R04_0_Pos)                          /*!< LCD PAL232: R04_0 Mask              */
+#define LCD_PAL232_G04_0_Pos                                  5                                                         /*!< LCD PAL232: G04_0 Position          */
+#define LCD_PAL232_G04_0_Msk                                  (0x1fUL << LCD_PAL232_G04_0_Pos)                          /*!< LCD PAL232: G04_0 Mask              */
+#define LCD_PAL232_B04_0_Pos                                  10                                                        /*!< LCD PAL232: B04_0 Position          */
+#define LCD_PAL232_B04_0_Msk                                  (0x1fUL << LCD_PAL232_B04_0_Pos)                          /*!< LCD PAL232: B04_0 Mask              */
+#define LCD_PAL232_I0_Pos                                     15                                                        /*!< LCD PAL232: I0 Position             */
+#define LCD_PAL232_I0_Msk                                     (0x01UL << LCD_PAL232_I0_Pos)                             /*!< LCD PAL232: I0 Mask                 */
+#define LCD_PAL232_R14_0_Pos                                  16                                                        /*!< LCD PAL232: R14_0 Position          */
+#define LCD_PAL232_R14_0_Msk                                  (0x1fUL << LCD_PAL232_R14_0_Pos)                          /*!< LCD PAL232: R14_0 Mask              */
+#define LCD_PAL232_G14_0_Pos                                  21                                                        /*!< LCD PAL232: G14_0 Position          */
+#define LCD_PAL232_G14_0_Msk                                  (0x1fUL << LCD_PAL232_G14_0_Pos)                          /*!< LCD PAL232: G14_0 Mask              */
+#define LCD_PAL232_B14_0_Pos                                  26                                                        /*!< LCD PAL232: B14_0 Position          */
+#define LCD_PAL232_B14_0_Msk                                  (0x1fUL << LCD_PAL232_B14_0_Pos)                          /*!< LCD PAL232: B14_0 Mask              */
+#define LCD_PAL232_I1_Pos                                     31                                                        /*!< LCD PAL232: I1 Position             */
+#define LCD_PAL232_I1_Msk                                     (0x01UL << LCD_PAL232_I1_Pos)                             /*!< LCD PAL232: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL233  -------------------------------------------
+#define LCD_PAL233_R04_0_Pos                                  0                                                         /*!< LCD PAL233: R04_0 Position          */
+#define LCD_PAL233_R04_0_Msk                                  (0x1fUL << LCD_PAL233_R04_0_Pos)                          /*!< LCD PAL233: R04_0 Mask              */
+#define LCD_PAL233_G04_0_Pos                                  5                                                         /*!< LCD PAL233: G04_0 Position          */
+#define LCD_PAL233_G04_0_Msk                                  (0x1fUL << LCD_PAL233_G04_0_Pos)                          /*!< LCD PAL233: G04_0 Mask              */
+#define LCD_PAL233_B04_0_Pos                                  10                                                        /*!< LCD PAL233: B04_0 Position          */
+#define LCD_PAL233_B04_0_Msk                                  (0x1fUL << LCD_PAL233_B04_0_Pos)                          /*!< LCD PAL233: B04_0 Mask              */
+#define LCD_PAL233_I0_Pos                                     15                                                        /*!< LCD PAL233: I0 Position             */
+#define LCD_PAL233_I0_Msk                                     (0x01UL << LCD_PAL233_I0_Pos)                             /*!< LCD PAL233: I0 Mask                 */
+#define LCD_PAL233_R14_0_Pos                                  16                                                        /*!< LCD PAL233: R14_0 Position          */
+#define LCD_PAL233_R14_0_Msk                                  (0x1fUL << LCD_PAL233_R14_0_Pos)                          /*!< LCD PAL233: R14_0 Mask              */
+#define LCD_PAL233_G14_0_Pos                                  21                                                        /*!< LCD PAL233: G14_0 Position          */
+#define LCD_PAL233_G14_0_Msk                                  (0x1fUL << LCD_PAL233_G14_0_Pos)                          /*!< LCD PAL233: G14_0 Mask              */
+#define LCD_PAL233_B14_0_Pos                                  26                                                        /*!< LCD PAL233: B14_0 Position          */
+#define LCD_PAL233_B14_0_Msk                                  (0x1fUL << LCD_PAL233_B14_0_Pos)                          /*!< LCD PAL233: B14_0 Mask              */
+#define LCD_PAL233_I1_Pos                                     31                                                        /*!< LCD PAL233: I1 Position             */
+#define LCD_PAL233_I1_Msk                                     (0x01UL << LCD_PAL233_I1_Pos)                             /*!< LCD PAL233: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL234  -------------------------------------------
+#define LCD_PAL234_R04_0_Pos                                  0                                                         /*!< LCD PAL234: R04_0 Position          */
+#define LCD_PAL234_R04_0_Msk                                  (0x1fUL << LCD_PAL234_R04_0_Pos)                          /*!< LCD PAL234: R04_0 Mask              */
+#define LCD_PAL234_G04_0_Pos                                  5                                                         /*!< LCD PAL234: G04_0 Position          */
+#define LCD_PAL234_G04_0_Msk                                  (0x1fUL << LCD_PAL234_G04_0_Pos)                          /*!< LCD PAL234: G04_0 Mask              */
+#define LCD_PAL234_B04_0_Pos                                  10                                                        /*!< LCD PAL234: B04_0 Position          */
+#define LCD_PAL234_B04_0_Msk                                  (0x1fUL << LCD_PAL234_B04_0_Pos)                          /*!< LCD PAL234: B04_0 Mask              */
+#define LCD_PAL234_I0_Pos                                     15                                                        /*!< LCD PAL234: I0 Position             */
+#define LCD_PAL234_I0_Msk                                     (0x01UL << LCD_PAL234_I0_Pos)                             /*!< LCD PAL234: I0 Mask                 */
+#define LCD_PAL234_R14_0_Pos                                  16                                                        /*!< LCD PAL234: R14_0 Position          */
+#define LCD_PAL234_R14_0_Msk                                  (0x1fUL << LCD_PAL234_R14_0_Pos)                          /*!< LCD PAL234: R14_0 Mask              */
+#define LCD_PAL234_G14_0_Pos                                  21                                                        /*!< LCD PAL234: G14_0 Position          */
+#define LCD_PAL234_G14_0_Msk                                  (0x1fUL << LCD_PAL234_G14_0_Pos)                          /*!< LCD PAL234: G14_0 Mask              */
+#define LCD_PAL234_B14_0_Pos                                  26                                                        /*!< LCD PAL234: B14_0 Position          */
+#define LCD_PAL234_B14_0_Msk                                  (0x1fUL << LCD_PAL234_B14_0_Pos)                          /*!< LCD PAL234: B14_0 Mask              */
+#define LCD_PAL234_I1_Pos                                     31                                                        /*!< LCD PAL234: I1 Position             */
+#define LCD_PAL234_I1_Msk                                     (0x01UL << LCD_PAL234_I1_Pos)                             /*!< LCD PAL234: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL235  -------------------------------------------
+#define LCD_PAL235_R04_0_Pos                                  0                                                         /*!< LCD PAL235: R04_0 Position          */
+#define LCD_PAL235_R04_0_Msk                                  (0x1fUL << LCD_PAL235_R04_0_Pos)                          /*!< LCD PAL235: R04_0 Mask              */
+#define LCD_PAL235_G04_0_Pos                                  5                                                         /*!< LCD PAL235: G04_0 Position          */
+#define LCD_PAL235_G04_0_Msk                                  (0x1fUL << LCD_PAL235_G04_0_Pos)                          /*!< LCD PAL235: G04_0 Mask              */
+#define LCD_PAL235_B04_0_Pos                                  10                                                        /*!< LCD PAL235: B04_0 Position          */
+#define LCD_PAL235_B04_0_Msk                                  (0x1fUL << LCD_PAL235_B04_0_Pos)                          /*!< LCD PAL235: B04_0 Mask              */
+#define LCD_PAL235_I0_Pos                                     15                                                        /*!< LCD PAL235: I0 Position             */
+#define LCD_PAL235_I0_Msk                                     (0x01UL << LCD_PAL235_I0_Pos)                             /*!< LCD PAL235: I0 Mask                 */
+#define LCD_PAL235_R14_0_Pos                                  16                                                        /*!< LCD PAL235: R14_0 Position          */
+#define LCD_PAL235_R14_0_Msk                                  (0x1fUL << LCD_PAL235_R14_0_Pos)                          /*!< LCD PAL235: R14_0 Mask              */
+#define LCD_PAL235_G14_0_Pos                                  21                                                        /*!< LCD PAL235: G14_0 Position          */
+#define LCD_PAL235_G14_0_Msk                                  (0x1fUL << LCD_PAL235_G14_0_Pos)                          /*!< LCD PAL235: G14_0 Mask              */
+#define LCD_PAL235_B14_0_Pos                                  26                                                        /*!< LCD PAL235: B14_0 Position          */
+#define LCD_PAL235_B14_0_Msk                                  (0x1fUL << LCD_PAL235_B14_0_Pos)                          /*!< LCD PAL235: B14_0 Mask              */
+#define LCD_PAL235_I1_Pos                                     31                                                        /*!< LCD PAL235: I1 Position             */
+#define LCD_PAL235_I1_Msk                                     (0x01UL << LCD_PAL235_I1_Pos)                             /*!< LCD PAL235: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL236  -------------------------------------------
+#define LCD_PAL236_R04_0_Pos                                  0                                                         /*!< LCD PAL236: R04_0 Position          */
+#define LCD_PAL236_R04_0_Msk                                  (0x1fUL << LCD_PAL236_R04_0_Pos)                          /*!< LCD PAL236: R04_0 Mask              */
+#define LCD_PAL236_G04_0_Pos                                  5                                                         /*!< LCD PAL236: G04_0 Position          */
+#define LCD_PAL236_G04_0_Msk                                  (0x1fUL << LCD_PAL236_G04_0_Pos)                          /*!< LCD PAL236: G04_0 Mask              */
+#define LCD_PAL236_B04_0_Pos                                  10                                                        /*!< LCD PAL236: B04_0 Position          */
+#define LCD_PAL236_B04_0_Msk                                  (0x1fUL << LCD_PAL236_B04_0_Pos)                          /*!< LCD PAL236: B04_0 Mask              */
+#define LCD_PAL236_I0_Pos                                     15                                                        /*!< LCD PAL236: I0 Position             */
+#define LCD_PAL236_I0_Msk                                     (0x01UL << LCD_PAL236_I0_Pos)                             /*!< LCD PAL236: I0 Mask                 */
+#define LCD_PAL236_R14_0_Pos                                  16                                                        /*!< LCD PAL236: R14_0 Position          */
+#define LCD_PAL236_R14_0_Msk                                  (0x1fUL << LCD_PAL236_R14_0_Pos)                          /*!< LCD PAL236: R14_0 Mask              */
+#define LCD_PAL236_G14_0_Pos                                  21                                                        /*!< LCD PAL236: G14_0 Position          */
+#define LCD_PAL236_G14_0_Msk                                  (0x1fUL << LCD_PAL236_G14_0_Pos)                          /*!< LCD PAL236: G14_0 Mask              */
+#define LCD_PAL236_B14_0_Pos                                  26                                                        /*!< LCD PAL236: B14_0 Position          */
+#define LCD_PAL236_B14_0_Msk                                  (0x1fUL << LCD_PAL236_B14_0_Pos)                          /*!< LCD PAL236: B14_0 Mask              */
+#define LCD_PAL236_I1_Pos                                     31                                                        /*!< LCD PAL236: I1 Position             */
+#define LCD_PAL236_I1_Msk                                     (0x01UL << LCD_PAL236_I1_Pos)                             /*!< LCD PAL236: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL237  -------------------------------------------
+#define LCD_PAL237_R04_0_Pos                                  0                                                         /*!< LCD PAL237: R04_0 Position          */
+#define LCD_PAL237_R04_0_Msk                                  (0x1fUL << LCD_PAL237_R04_0_Pos)                          /*!< LCD PAL237: R04_0 Mask              */
+#define LCD_PAL237_G04_0_Pos                                  5                                                         /*!< LCD PAL237: G04_0 Position          */
+#define LCD_PAL237_G04_0_Msk                                  (0x1fUL << LCD_PAL237_G04_0_Pos)                          /*!< LCD PAL237: G04_0 Mask              */
+#define LCD_PAL237_B04_0_Pos                                  10                                                        /*!< LCD PAL237: B04_0 Position          */
+#define LCD_PAL237_B04_0_Msk                                  (0x1fUL << LCD_PAL237_B04_0_Pos)                          /*!< LCD PAL237: B04_0 Mask              */
+#define LCD_PAL237_I0_Pos                                     15                                                        /*!< LCD PAL237: I0 Position             */
+#define LCD_PAL237_I0_Msk                                     (0x01UL << LCD_PAL237_I0_Pos)                             /*!< LCD PAL237: I0 Mask                 */
+#define LCD_PAL237_R14_0_Pos                                  16                                                        /*!< LCD PAL237: R14_0 Position          */
+#define LCD_PAL237_R14_0_Msk                                  (0x1fUL << LCD_PAL237_R14_0_Pos)                          /*!< LCD PAL237: R14_0 Mask              */
+#define LCD_PAL237_G14_0_Pos                                  21                                                        /*!< LCD PAL237: G14_0 Position          */
+#define LCD_PAL237_G14_0_Msk                                  (0x1fUL << LCD_PAL237_G14_0_Pos)                          /*!< LCD PAL237: G14_0 Mask              */
+#define LCD_PAL237_B14_0_Pos                                  26                                                        /*!< LCD PAL237: B14_0 Position          */
+#define LCD_PAL237_B14_0_Msk                                  (0x1fUL << LCD_PAL237_B14_0_Pos)                          /*!< LCD PAL237: B14_0 Mask              */
+#define LCD_PAL237_I1_Pos                                     31                                                        /*!< LCD PAL237: I1 Position             */
+#define LCD_PAL237_I1_Msk                                     (0x01UL << LCD_PAL237_I1_Pos)                             /*!< LCD PAL237: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL238  -------------------------------------------
+#define LCD_PAL238_R04_0_Pos                                  0                                                         /*!< LCD PAL238: R04_0 Position          */
+#define LCD_PAL238_R04_0_Msk                                  (0x1fUL << LCD_PAL238_R04_0_Pos)                          /*!< LCD PAL238: R04_0 Mask              */
+#define LCD_PAL238_G04_0_Pos                                  5                                                         /*!< LCD PAL238: G04_0 Position          */
+#define LCD_PAL238_G04_0_Msk                                  (0x1fUL << LCD_PAL238_G04_0_Pos)                          /*!< LCD PAL238: G04_0 Mask              */
+#define LCD_PAL238_B04_0_Pos                                  10                                                        /*!< LCD PAL238: B04_0 Position          */
+#define LCD_PAL238_B04_0_Msk                                  (0x1fUL << LCD_PAL238_B04_0_Pos)                          /*!< LCD PAL238: B04_0 Mask              */
+#define LCD_PAL238_I0_Pos                                     15                                                        /*!< LCD PAL238: I0 Position             */
+#define LCD_PAL238_I0_Msk                                     (0x01UL << LCD_PAL238_I0_Pos)                             /*!< LCD PAL238: I0 Mask                 */
+#define LCD_PAL238_R14_0_Pos                                  16                                                        /*!< LCD PAL238: R14_0 Position          */
+#define LCD_PAL238_R14_0_Msk                                  (0x1fUL << LCD_PAL238_R14_0_Pos)                          /*!< LCD PAL238: R14_0 Mask              */
+#define LCD_PAL238_G14_0_Pos                                  21                                                        /*!< LCD PAL238: G14_0 Position          */
+#define LCD_PAL238_G14_0_Msk                                  (0x1fUL << LCD_PAL238_G14_0_Pos)                          /*!< LCD PAL238: G14_0 Mask              */
+#define LCD_PAL238_B14_0_Pos                                  26                                                        /*!< LCD PAL238: B14_0 Position          */
+#define LCD_PAL238_B14_0_Msk                                  (0x1fUL << LCD_PAL238_B14_0_Pos)                          /*!< LCD PAL238: B14_0 Mask              */
+#define LCD_PAL238_I1_Pos                                     31                                                        /*!< LCD PAL238: I1 Position             */
+#define LCD_PAL238_I1_Msk                                     (0x01UL << LCD_PAL238_I1_Pos)                             /*!< LCD PAL238: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL239  -------------------------------------------
+#define LCD_PAL239_R04_0_Pos                                  0                                                         /*!< LCD PAL239: R04_0 Position          */
+#define LCD_PAL239_R04_0_Msk                                  (0x1fUL << LCD_PAL239_R04_0_Pos)                          /*!< LCD PAL239: R04_0 Mask              */
+#define LCD_PAL239_G04_0_Pos                                  5                                                         /*!< LCD PAL239: G04_0 Position          */
+#define LCD_PAL239_G04_0_Msk                                  (0x1fUL << LCD_PAL239_G04_0_Pos)                          /*!< LCD PAL239: G04_0 Mask              */
+#define LCD_PAL239_B04_0_Pos                                  10                                                        /*!< LCD PAL239: B04_0 Position          */
+#define LCD_PAL239_B04_0_Msk                                  (0x1fUL << LCD_PAL239_B04_0_Pos)                          /*!< LCD PAL239: B04_0 Mask              */
+#define LCD_PAL239_I0_Pos                                     15                                                        /*!< LCD PAL239: I0 Position             */
+#define LCD_PAL239_I0_Msk                                     (0x01UL << LCD_PAL239_I0_Pos)                             /*!< LCD PAL239: I0 Mask                 */
+#define LCD_PAL239_R14_0_Pos                                  16                                                        /*!< LCD PAL239: R14_0 Position          */
+#define LCD_PAL239_R14_0_Msk                                  (0x1fUL << LCD_PAL239_R14_0_Pos)                          /*!< LCD PAL239: R14_0 Mask              */
+#define LCD_PAL239_G14_0_Pos                                  21                                                        /*!< LCD PAL239: G14_0 Position          */
+#define LCD_PAL239_G14_0_Msk                                  (0x1fUL << LCD_PAL239_G14_0_Pos)                          /*!< LCD PAL239: G14_0 Mask              */
+#define LCD_PAL239_B14_0_Pos                                  26                                                        /*!< LCD PAL239: B14_0 Position          */
+#define LCD_PAL239_B14_0_Msk                                  (0x1fUL << LCD_PAL239_B14_0_Pos)                          /*!< LCD PAL239: B14_0 Mask              */
+#define LCD_PAL239_I1_Pos                                     31                                                        /*!< LCD PAL239: I1 Position             */
+#define LCD_PAL239_I1_Msk                                     (0x01UL << LCD_PAL239_I1_Pos)                             /*!< LCD PAL239: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL240  -------------------------------------------
+#define LCD_PAL240_R04_0_Pos                                  0                                                         /*!< LCD PAL240: R04_0 Position          */
+#define LCD_PAL240_R04_0_Msk                                  (0x1fUL << LCD_PAL240_R04_0_Pos)                          /*!< LCD PAL240: R04_0 Mask              */
+#define LCD_PAL240_G04_0_Pos                                  5                                                         /*!< LCD PAL240: G04_0 Position          */
+#define LCD_PAL240_G04_0_Msk                                  (0x1fUL << LCD_PAL240_G04_0_Pos)                          /*!< LCD PAL240: G04_0 Mask              */
+#define LCD_PAL240_B04_0_Pos                                  10                                                        /*!< LCD PAL240: B04_0 Position          */
+#define LCD_PAL240_B04_0_Msk                                  (0x1fUL << LCD_PAL240_B04_0_Pos)                          /*!< LCD PAL240: B04_0 Mask              */
+#define LCD_PAL240_I0_Pos                                     15                                                        /*!< LCD PAL240: I0 Position             */
+#define LCD_PAL240_I0_Msk                                     (0x01UL << LCD_PAL240_I0_Pos)                             /*!< LCD PAL240: I0 Mask                 */
+#define LCD_PAL240_R14_0_Pos                                  16                                                        /*!< LCD PAL240: R14_0 Position          */
+#define LCD_PAL240_R14_0_Msk                                  (0x1fUL << LCD_PAL240_R14_0_Pos)                          /*!< LCD PAL240: R14_0 Mask              */
+#define LCD_PAL240_G14_0_Pos                                  21                                                        /*!< LCD PAL240: G14_0 Position          */
+#define LCD_PAL240_G14_0_Msk                                  (0x1fUL << LCD_PAL240_G14_0_Pos)                          /*!< LCD PAL240: G14_0 Mask              */
+#define LCD_PAL240_B14_0_Pos                                  26                                                        /*!< LCD PAL240: B14_0 Position          */
+#define LCD_PAL240_B14_0_Msk                                  (0x1fUL << LCD_PAL240_B14_0_Pos)                          /*!< LCD PAL240: B14_0 Mask              */
+#define LCD_PAL240_I1_Pos                                     31                                                        /*!< LCD PAL240: I1 Position             */
+#define LCD_PAL240_I1_Msk                                     (0x01UL << LCD_PAL240_I1_Pos)                             /*!< LCD PAL240: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL241  -------------------------------------------
+#define LCD_PAL241_R04_0_Pos                                  0                                                         /*!< LCD PAL241: R04_0 Position          */
+#define LCD_PAL241_R04_0_Msk                                  (0x1fUL << LCD_PAL241_R04_0_Pos)                          /*!< LCD PAL241: R04_0 Mask              */
+#define LCD_PAL241_G04_0_Pos                                  5                                                         /*!< LCD PAL241: G04_0 Position          */
+#define LCD_PAL241_G04_0_Msk                                  (0x1fUL << LCD_PAL241_G04_0_Pos)                          /*!< LCD PAL241: G04_0 Mask              */
+#define LCD_PAL241_B04_0_Pos                                  10                                                        /*!< LCD PAL241: B04_0 Position          */
+#define LCD_PAL241_B04_0_Msk                                  (0x1fUL << LCD_PAL241_B04_0_Pos)                          /*!< LCD PAL241: B04_0 Mask              */
+#define LCD_PAL241_I0_Pos                                     15                                                        /*!< LCD PAL241: I0 Position             */
+#define LCD_PAL241_I0_Msk                                     (0x01UL << LCD_PAL241_I0_Pos)                             /*!< LCD PAL241: I0 Mask                 */
+#define LCD_PAL241_R14_0_Pos                                  16                                                        /*!< LCD PAL241: R14_0 Position          */
+#define LCD_PAL241_R14_0_Msk                                  (0x1fUL << LCD_PAL241_R14_0_Pos)                          /*!< LCD PAL241: R14_0 Mask              */
+#define LCD_PAL241_G14_0_Pos                                  21                                                        /*!< LCD PAL241: G14_0 Position          */
+#define LCD_PAL241_G14_0_Msk                                  (0x1fUL << LCD_PAL241_G14_0_Pos)                          /*!< LCD PAL241: G14_0 Mask              */
+#define LCD_PAL241_B14_0_Pos                                  26                                                        /*!< LCD PAL241: B14_0 Position          */
+#define LCD_PAL241_B14_0_Msk                                  (0x1fUL << LCD_PAL241_B14_0_Pos)                          /*!< LCD PAL241: B14_0 Mask              */
+#define LCD_PAL241_I1_Pos                                     31                                                        /*!< LCD PAL241: I1 Position             */
+#define LCD_PAL241_I1_Msk                                     (0x01UL << LCD_PAL241_I1_Pos)                             /*!< LCD PAL241: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL242  -------------------------------------------
+#define LCD_PAL242_R04_0_Pos                                  0                                                         /*!< LCD PAL242: R04_0 Position          */
+#define LCD_PAL242_R04_0_Msk                                  (0x1fUL << LCD_PAL242_R04_0_Pos)                          /*!< LCD PAL242: R04_0 Mask              */
+#define LCD_PAL242_G04_0_Pos                                  5                                                         /*!< LCD PAL242: G04_0 Position          */
+#define LCD_PAL242_G04_0_Msk                                  (0x1fUL << LCD_PAL242_G04_0_Pos)                          /*!< LCD PAL242: G04_0 Mask              */
+#define LCD_PAL242_B04_0_Pos                                  10                                                        /*!< LCD PAL242: B04_0 Position          */
+#define LCD_PAL242_B04_0_Msk                                  (0x1fUL << LCD_PAL242_B04_0_Pos)                          /*!< LCD PAL242: B04_0 Mask              */
+#define LCD_PAL242_I0_Pos                                     15                                                        /*!< LCD PAL242: I0 Position             */
+#define LCD_PAL242_I0_Msk                                     (0x01UL << LCD_PAL242_I0_Pos)                             /*!< LCD PAL242: I0 Mask                 */
+#define LCD_PAL242_R14_0_Pos                                  16                                                        /*!< LCD PAL242: R14_0 Position          */
+#define LCD_PAL242_R14_0_Msk                                  (0x1fUL << LCD_PAL242_R14_0_Pos)                          /*!< LCD PAL242: R14_0 Mask              */
+#define LCD_PAL242_G14_0_Pos                                  21                                                        /*!< LCD PAL242: G14_0 Position          */
+#define LCD_PAL242_G14_0_Msk                                  (0x1fUL << LCD_PAL242_G14_0_Pos)                          /*!< LCD PAL242: G14_0 Mask              */
+#define LCD_PAL242_B14_0_Pos                                  26                                                        /*!< LCD PAL242: B14_0 Position          */
+#define LCD_PAL242_B14_0_Msk                                  (0x1fUL << LCD_PAL242_B14_0_Pos)                          /*!< LCD PAL242: B14_0 Mask              */
+#define LCD_PAL242_I1_Pos                                     31                                                        /*!< LCD PAL242: I1 Position             */
+#define LCD_PAL242_I1_Msk                                     (0x01UL << LCD_PAL242_I1_Pos)                             /*!< LCD PAL242: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL243  -------------------------------------------
+#define LCD_PAL243_R04_0_Pos                                  0                                                         /*!< LCD PAL243: R04_0 Position          */
+#define LCD_PAL243_R04_0_Msk                                  (0x1fUL << LCD_PAL243_R04_0_Pos)                          /*!< LCD PAL243: R04_0 Mask              */
+#define LCD_PAL243_G04_0_Pos                                  5                                                         /*!< LCD PAL243: G04_0 Position          */
+#define LCD_PAL243_G04_0_Msk                                  (0x1fUL << LCD_PAL243_G04_0_Pos)                          /*!< LCD PAL243: G04_0 Mask              */
+#define LCD_PAL243_B04_0_Pos                                  10                                                        /*!< LCD PAL243: B04_0 Position          */
+#define LCD_PAL243_B04_0_Msk                                  (0x1fUL << LCD_PAL243_B04_0_Pos)                          /*!< LCD PAL243: B04_0 Mask              */
+#define LCD_PAL243_I0_Pos                                     15                                                        /*!< LCD PAL243: I0 Position             */
+#define LCD_PAL243_I0_Msk                                     (0x01UL << LCD_PAL243_I0_Pos)                             /*!< LCD PAL243: I0 Mask                 */
+#define LCD_PAL243_R14_0_Pos                                  16                                                        /*!< LCD PAL243: R14_0 Position          */
+#define LCD_PAL243_R14_0_Msk                                  (0x1fUL << LCD_PAL243_R14_0_Pos)                          /*!< LCD PAL243: R14_0 Mask              */
+#define LCD_PAL243_G14_0_Pos                                  21                                                        /*!< LCD PAL243: G14_0 Position          */
+#define LCD_PAL243_G14_0_Msk                                  (0x1fUL << LCD_PAL243_G14_0_Pos)                          /*!< LCD PAL243: G14_0 Mask              */
+#define LCD_PAL243_B14_0_Pos                                  26                                                        /*!< LCD PAL243: B14_0 Position          */
+#define LCD_PAL243_B14_0_Msk                                  (0x1fUL << LCD_PAL243_B14_0_Pos)                          /*!< LCD PAL243: B14_0 Mask              */
+#define LCD_PAL243_I1_Pos                                     31                                                        /*!< LCD PAL243: I1 Position             */
+#define LCD_PAL243_I1_Msk                                     (0x01UL << LCD_PAL243_I1_Pos)                             /*!< LCD PAL243: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL244  -------------------------------------------
+#define LCD_PAL244_R04_0_Pos                                  0                                                         /*!< LCD PAL244: R04_0 Position          */
+#define LCD_PAL244_R04_0_Msk                                  (0x1fUL << LCD_PAL244_R04_0_Pos)                          /*!< LCD PAL244: R04_0 Mask              */
+#define LCD_PAL244_G04_0_Pos                                  5                                                         /*!< LCD PAL244: G04_0 Position          */
+#define LCD_PAL244_G04_0_Msk                                  (0x1fUL << LCD_PAL244_G04_0_Pos)                          /*!< LCD PAL244: G04_0 Mask              */
+#define LCD_PAL244_B04_0_Pos                                  10                                                        /*!< LCD PAL244: B04_0 Position          */
+#define LCD_PAL244_B04_0_Msk                                  (0x1fUL << LCD_PAL244_B04_0_Pos)                          /*!< LCD PAL244: B04_0 Mask              */
+#define LCD_PAL244_I0_Pos                                     15                                                        /*!< LCD PAL244: I0 Position             */
+#define LCD_PAL244_I0_Msk                                     (0x01UL << LCD_PAL244_I0_Pos)                             /*!< LCD PAL244: I0 Mask                 */
+#define LCD_PAL244_R14_0_Pos                                  16                                                        /*!< LCD PAL244: R14_0 Position          */
+#define LCD_PAL244_R14_0_Msk                                  (0x1fUL << LCD_PAL244_R14_0_Pos)                          /*!< LCD PAL244: R14_0 Mask              */
+#define LCD_PAL244_G14_0_Pos                                  21                                                        /*!< LCD PAL244: G14_0 Position          */
+#define LCD_PAL244_G14_0_Msk                                  (0x1fUL << LCD_PAL244_G14_0_Pos)                          /*!< LCD PAL244: G14_0 Mask              */
+#define LCD_PAL244_B14_0_Pos                                  26                                                        /*!< LCD PAL244: B14_0 Position          */
+#define LCD_PAL244_B14_0_Msk                                  (0x1fUL << LCD_PAL244_B14_0_Pos)                          /*!< LCD PAL244: B14_0 Mask              */
+#define LCD_PAL244_I1_Pos                                     31                                                        /*!< LCD PAL244: I1 Position             */
+#define LCD_PAL244_I1_Msk                                     (0x01UL << LCD_PAL244_I1_Pos)                             /*!< LCD PAL244: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL245  -------------------------------------------
+#define LCD_PAL245_R04_0_Pos                                  0                                                         /*!< LCD PAL245: R04_0 Position          */
+#define LCD_PAL245_R04_0_Msk                                  (0x1fUL << LCD_PAL245_R04_0_Pos)                          /*!< LCD PAL245: R04_0 Mask              */
+#define LCD_PAL245_G04_0_Pos                                  5                                                         /*!< LCD PAL245: G04_0 Position          */
+#define LCD_PAL245_G04_0_Msk                                  (0x1fUL << LCD_PAL245_G04_0_Pos)                          /*!< LCD PAL245: G04_0 Mask              */
+#define LCD_PAL245_B04_0_Pos                                  10                                                        /*!< LCD PAL245: B04_0 Position          */
+#define LCD_PAL245_B04_0_Msk                                  (0x1fUL << LCD_PAL245_B04_0_Pos)                          /*!< LCD PAL245: B04_0 Mask              */
+#define LCD_PAL245_I0_Pos                                     15                                                        /*!< LCD PAL245: I0 Position             */
+#define LCD_PAL245_I0_Msk                                     (0x01UL << LCD_PAL245_I0_Pos)                             /*!< LCD PAL245: I0 Mask                 */
+#define LCD_PAL245_R14_0_Pos                                  16                                                        /*!< LCD PAL245: R14_0 Position          */
+#define LCD_PAL245_R14_0_Msk                                  (0x1fUL << LCD_PAL245_R14_0_Pos)                          /*!< LCD PAL245: R14_0 Mask              */
+#define LCD_PAL245_G14_0_Pos                                  21                                                        /*!< LCD PAL245: G14_0 Position          */
+#define LCD_PAL245_G14_0_Msk                                  (0x1fUL << LCD_PAL245_G14_0_Pos)                          /*!< LCD PAL245: G14_0 Mask              */
+#define LCD_PAL245_B14_0_Pos                                  26                                                        /*!< LCD PAL245: B14_0 Position          */
+#define LCD_PAL245_B14_0_Msk                                  (0x1fUL << LCD_PAL245_B14_0_Pos)                          /*!< LCD PAL245: B14_0 Mask              */
+#define LCD_PAL245_I1_Pos                                     31                                                        /*!< LCD PAL245: I1 Position             */
+#define LCD_PAL245_I1_Msk                                     (0x01UL << LCD_PAL245_I1_Pos)                             /*!< LCD PAL245: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL246  -------------------------------------------
+#define LCD_PAL246_R04_0_Pos                                  0                                                         /*!< LCD PAL246: R04_0 Position          */
+#define LCD_PAL246_R04_0_Msk                                  (0x1fUL << LCD_PAL246_R04_0_Pos)                          /*!< LCD PAL246: R04_0 Mask              */
+#define LCD_PAL246_G04_0_Pos                                  5                                                         /*!< LCD PAL246: G04_0 Position          */
+#define LCD_PAL246_G04_0_Msk                                  (0x1fUL << LCD_PAL246_G04_0_Pos)                          /*!< LCD PAL246: G04_0 Mask              */
+#define LCD_PAL246_B04_0_Pos                                  10                                                        /*!< LCD PAL246: B04_0 Position          */
+#define LCD_PAL246_B04_0_Msk                                  (0x1fUL << LCD_PAL246_B04_0_Pos)                          /*!< LCD PAL246: B04_0 Mask              */
+#define LCD_PAL246_I0_Pos                                     15                                                        /*!< LCD PAL246: I0 Position             */
+#define LCD_PAL246_I0_Msk                                     (0x01UL << LCD_PAL246_I0_Pos)                             /*!< LCD PAL246: I0 Mask                 */
+#define LCD_PAL246_R14_0_Pos                                  16                                                        /*!< LCD PAL246: R14_0 Position          */
+#define LCD_PAL246_R14_0_Msk                                  (0x1fUL << LCD_PAL246_R14_0_Pos)                          /*!< LCD PAL246: R14_0 Mask              */
+#define LCD_PAL246_G14_0_Pos                                  21                                                        /*!< LCD PAL246: G14_0 Position          */
+#define LCD_PAL246_G14_0_Msk                                  (0x1fUL << LCD_PAL246_G14_0_Pos)                          /*!< LCD PAL246: G14_0 Mask              */
+#define LCD_PAL246_B14_0_Pos                                  26                                                        /*!< LCD PAL246: B14_0 Position          */
+#define LCD_PAL246_B14_0_Msk                                  (0x1fUL << LCD_PAL246_B14_0_Pos)                          /*!< LCD PAL246: B14_0 Mask              */
+#define LCD_PAL246_I1_Pos                                     31                                                        /*!< LCD PAL246: I1 Position             */
+#define LCD_PAL246_I1_Msk                                     (0x01UL << LCD_PAL246_I1_Pos)                             /*!< LCD PAL246: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL247  -------------------------------------------
+#define LCD_PAL247_R04_0_Pos                                  0                                                         /*!< LCD PAL247: R04_0 Position          */
+#define LCD_PAL247_R04_0_Msk                                  (0x1fUL << LCD_PAL247_R04_0_Pos)                          /*!< LCD PAL247: R04_0 Mask              */
+#define LCD_PAL247_G04_0_Pos                                  5                                                         /*!< LCD PAL247: G04_0 Position          */
+#define LCD_PAL247_G04_0_Msk                                  (0x1fUL << LCD_PAL247_G04_0_Pos)                          /*!< LCD PAL247: G04_0 Mask              */
+#define LCD_PAL247_B04_0_Pos                                  10                                                        /*!< LCD PAL247: B04_0 Position          */
+#define LCD_PAL247_B04_0_Msk                                  (0x1fUL << LCD_PAL247_B04_0_Pos)                          /*!< LCD PAL247: B04_0 Mask              */
+#define LCD_PAL247_I0_Pos                                     15                                                        /*!< LCD PAL247: I0 Position             */
+#define LCD_PAL247_I0_Msk                                     (0x01UL << LCD_PAL247_I0_Pos)                             /*!< LCD PAL247: I0 Mask                 */
+#define LCD_PAL247_R14_0_Pos                                  16                                                        /*!< LCD PAL247: R14_0 Position          */
+#define LCD_PAL247_R14_0_Msk                                  (0x1fUL << LCD_PAL247_R14_0_Pos)                          /*!< LCD PAL247: R14_0 Mask              */
+#define LCD_PAL247_G14_0_Pos                                  21                                                        /*!< LCD PAL247: G14_0 Position          */
+#define LCD_PAL247_G14_0_Msk                                  (0x1fUL << LCD_PAL247_G14_0_Pos)                          /*!< LCD PAL247: G14_0 Mask              */
+#define LCD_PAL247_B14_0_Pos                                  26                                                        /*!< LCD PAL247: B14_0 Position          */
+#define LCD_PAL247_B14_0_Msk                                  (0x1fUL << LCD_PAL247_B14_0_Pos)                          /*!< LCD PAL247: B14_0 Mask              */
+#define LCD_PAL247_I1_Pos                                     31                                                        /*!< LCD PAL247: I1 Position             */
+#define LCD_PAL247_I1_Msk                                     (0x01UL << LCD_PAL247_I1_Pos)                             /*!< LCD PAL247: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL248  -------------------------------------------
+#define LCD_PAL248_R04_0_Pos                                  0                                                         /*!< LCD PAL248: R04_0 Position          */
+#define LCD_PAL248_R04_0_Msk                                  (0x1fUL << LCD_PAL248_R04_0_Pos)                          /*!< LCD PAL248: R04_0 Mask              */
+#define LCD_PAL248_G04_0_Pos                                  5                                                         /*!< LCD PAL248: G04_0 Position          */
+#define LCD_PAL248_G04_0_Msk                                  (0x1fUL << LCD_PAL248_G04_0_Pos)                          /*!< LCD PAL248: G04_0 Mask              */
+#define LCD_PAL248_B04_0_Pos                                  10                                                        /*!< LCD PAL248: B04_0 Position          */
+#define LCD_PAL248_B04_0_Msk                                  (0x1fUL << LCD_PAL248_B04_0_Pos)                          /*!< LCD PAL248: B04_0 Mask              */
+#define LCD_PAL248_I0_Pos                                     15                                                        /*!< LCD PAL248: I0 Position             */
+#define LCD_PAL248_I0_Msk                                     (0x01UL << LCD_PAL248_I0_Pos)                             /*!< LCD PAL248: I0 Mask                 */
+#define LCD_PAL248_R14_0_Pos                                  16                                                        /*!< LCD PAL248: R14_0 Position          */
+#define LCD_PAL248_R14_0_Msk                                  (0x1fUL << LCD_PAL248_R14_0_Pos)                          /*!< LCD PAL248: R14_0 Mask              */
+#define LCD_PAL248_G14_0_Pos                                  21                                                        /*!< LCD PAL248: G14_0 Position          */
+#define LCD_PAL248_G14_0_Msk                                  (0x1fUL << LCD_PAL248_G14_0_Pos)                          /*!< LCD PAL248: G14_0 Mask              */
+#define LCD_PAL248_B14_0_Pos                                  26                                                        /*!< LCD PAL248: B14_0 Position          */
+#define LCD_PAL248_B14_0_Msk                                  (0x1fUL << LCD_PAL248_B14_0_Pos)                          /*!< LCD PAL248: B14_0 Mask              */
+#define LCD_PAL248_I1_Pos                                     31                                                        /*!< LCD PAL248: I1 Position             */
+#define LCD_PAL248_I1_Msk                                     (0x01UL << LCD_PAL248_I1_Pos)                             /*!< LCD PAL248: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL249  -------------------------------------------
+#define LCD_PAL249_R04_0_Pos                                  0                                                         /*!< LCD PAL249: R04_0 Position          */
+#define LCD_PAL249_R04_0_Msk                                  (0x1fUL << LCD_PAL249_R04_0_Pos)                          /*!< LCD PAL249: R04_0 Mask              */
+#define LCD_PAL249_G04_0_Pos                                  5                                                         /*!< LCD PAL249: G04_0 Position          */
+#define LCD_PAL249_G04_0_Msk                                  (0x1fUL << LCD_PAL249_G04_0_Pos)                          /*!< LCD PAL249: G04_0 Mask              */
+#define LCD_PAL249_B04_0_Pos                                  10                                                        /*!< LCD PAL249: B04_0 Position          */
+#define LCD_PAL249_B04_0_Msk                                  (0x1fUL << LCD_PAL249_B04_0_Pos)                          /*!< LCD PAL249: B04_0 Mask              */
+#define LCD_PAL249_I0_Pos                                     15                                                        /*!< LCD PAL249: I0 Position             */
+#define LCD_PAL249_I0_Msk                                     (0x01UL << LCD_PAL249_I0_Pos)                             /*!< LCD PAL249: I0 Mask                 */
+#define LCD_PAL249_R14_0_Pos                                  16                                                        /*!< LCD PAL249: R14_0 Position          */
+#define LCD_PAL249_R14_0_Msk                                  (0x1fUL << LCD_PAL249_R14_0_Pos)                          /*!< LCD PAL249: R14_0 Mask              */
+#define LCD_PAL249_G14_0_Pos                                  21                                                        /*!< LCD PAL249: G14_0 Position          */
+#define LCD_PAL249_G14_0_Msk                                  (0x1fUL << LCD_PAL249_G14_0_Pos)                          /*!< LCD PAL249: G14_0 Mask              */
+#define LCD_PAL249_B14_0_Pos                                  26                                                        /*!< LCD PAL249: B14_0 Position          */
+#define LCD_PAL249_B14_0_Msk                                  (0x1fUL << LCD_PAL249_B14_0_Pos)                          /*!< LCD PAL249: B14_0 Mask              */
+#define LCD_PAL249_I1_Pos                                     31                                                        /*!< LCD PAL249: I1 Position             */
+#define LCD_PAL249_I1_Msk                                     (0x01UL << LCD_PAL249_I1_Pos)                             /*!< LCD PAL249: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL250  -------------------------------------------
+#define LCD_PAL250_R04_0_Pos                                  0                                                         /*!< LCD PAL250: R04_0 Position          */
+#define LCD_PAL250_R04_0_Msk                                  (0x1fUL << LCD_PAL250_R04_0_Pos)                          /*!< LCD PAL250: R04_0 Mask              */
+#define LCD_PAL250_G04_0_Pos                                  5                                                         /*!< LCD PAL250: G04_0 Position          */
+#define LCD_PAL250_G04_0_Msk                                  (0x1fUL << LCD_PAL250_G04_0_Pos)                          /*!< LCD PAL250: G04_0 Mask              */
+#define LCD_PAL250_B04_0_Pos                                  10                                                        /*!< LCD PAL250: B04_0 Position          */
+#define LCD_PAL250_B04_0_Msk                                  (0x1fUL << LCD_PAL250_B04_0_Pos)                          /*!< LCD PAL250: B04_0 Mask              */
+#define LCD_PAL250_I0_Pos                                     15                                                        /*!< LCD PAL250: I0 Position             */
+#define LCD_PAL250_I0_Msk                                     (0x01UL << LCD_PAL250_I0_Pos)                             /*!< LCD PAL250: I0 Mask                 */
+#define LCD_PAL250_R14_0_Pos                                  16                                                        /*!< LCD PAL250: R14_0 Position          */
+#define LCD_PAL250_R14_0_Msk                                  (0x1fUL << LCD_PAL250_R14_0_Pos)                          /*!< LCD PAL250: R14_0 Mask              */
+#define LCD_PAL250_G14_0_Pos                                  21                                                        /*!< LCD PAL250: G14_0 Position          */
+#define LCD_PAL250_G14_0_Msk                                  (0x1fUL << LCD_PAL250_G14_0_Pos)                          /*!< LCD PAL250: G14_0 Mask              */
+#define LCD_PAL250_B14_0_Pos                                  26                                                        /*!< LCD PAL250: B14_0 Position          */
+#define LCD_PAL250_B14_0_Msk                                  (0x1fUL << LCD_PAL250_B14_0_Pos)                          /*!< LCD PAL250: B14_0 Mask              */
+#define LCD_PAL250_I1_Pos                                     31                                                        /*!< LCD PAL250: I1 Position             */
+#define LCD_PAL250_I1_Msk                                     (0x01UL << LCD_PAL250_I1_Pos)                             /*!< LCD PAL250: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL251  -------------------------------------------
+#define LCD_PAL251_R04_0_Pos                                  0                                                         /*!< LCD PAL251: R04_0 Position          */
+#define LCD_PAL251_R04_0_Msk                                  (0x1fUL << LCD_PAL251_R04_0_Pos)                          /*!< LCD PAL251: R04_0 Mask              */
+#define LCD_PAL251_G04_0_Pos                                  5                                                         /*!< LCD PAL251: G04_0 Position          */
+#define LCD_PAL251_G04_0_Msk                                  (0x1fUL << LCD_PAL251_G04_0_Pos)                          /*!< LCD PAL251: G04_0 Mask              */
+#define LCD_PAL251_B04_0_Pos                                  10                                                        /*!< LCD PAL251: B04_0 Position          */
+#define LCD_PAL251_B04_0_Msk                                  (0x1fUL << LCD_PAL251_B04_0_Pos)                          /*!< LCD PAL251: B04_0 Mask              */
+#define LCD_PAL251_I0_Pos                                     15                                                        /*!< LCD PAL251: I0 Position             */
+#define LCD_PAL251_I0_Msk                                     (0x01UL << LCD_PAL251_I0_Pos)                             /*!< LCD PAL251: I0 Mask                 */
+#define LCD_PAL251_R14_0_Pos                                  16                                                        /*!< LCD PAL251: R14_0 Position          */
+#define LCD_PAL251_R14_0_Msk                                  (0x1fUL << LCD_PAL251_R14_0_Pos)                          /*!< LCD PAL251: R14_0 Mask              */
+#define LCD_PAL251_G14_0_Pos                                  21                                                        /*!< LCD PAL251: G14_0 Position          */
+#define LCD_PAL251_G14_0_Msk                                  (0x1fUL << LCD_PAL251_G14_0_Pos)                          /*!< LCD PAL251: G14_0 Mask              */
+#define LCD_PAL251_B14_0_Pos                                  26                                                        /*!< LCD PAL251: B14_0 Position          */
+#define LCD_PAL251_B14_0_Msk                                  (0x1fUL << LCD_PAL251_B14_0_Pos)                          /*!< LCD PAL251: B14_0 Mask              */
+#define LCD_PAL251_I1_Pos                                     31                                                        /*!< LCD PAL251: I1 Position             */
+#define LCD_PAL251_I1_Msk                                     (0x01UL << LCD_PAL251_I1_Pos)                             /*!< LCD PAL251: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL252  -------------------------------------------
+#define LCD_PAL252_R04_0_Pos                                  0                                                         /*!< LCD PAL252: R04_0 Position          */
+#define LCD_PAL252_R04_0_Msk                                  (0x1fUL << LCD_PAL252_R04_0_Pos)                          /*!< LCD PAL252: R04_0 Mask              */
+#define LCD_PAL252_G04_0_Pos                                  5                                                         /*!< LCD PAL252: G04_0 Position          */
+#define LCD_PAL252_G04_0_Msk                                  (0x1fUL << LCD_PAL252_G04_0_Pos)                          /*!< LCD PAL252: G04_0 Mask              */
+#define LCD_PAL252_B04_0_Pos                                  10                                                        /*!< LCD PAL252: B04_0 Position          */
+#define LCD_PAL252_B04_0_Msk                                  (0x1fUL << LCD_PAL252_B04_0_Pos)                          /*!< LCD PAL252: B04_0 Mask              */
+#define LCD_PAL252_I0_Pos                                     15                                                        /*!< LCD PAL252: I0 Position             */
+#define LCD_PAL252_I0_Msk                                     (0x01UL << LCD_PAL252_I0_Pos)                             /*!< LCD PAL252: I0 Mask                 */
+#define LCD_PAL252_R14_0_Pos                                  16                                                        /*!< LCD PAL252: R14_0 Position          */
+#define LCD_PAL252_R14_0_Msk                                  (0x1fUL << LCD_PAL252_R14_0_Pos)                          /*!< LCD PAL252: R14_0 Mask              */
+#define LCD_PAL252_G14_0_Pos                                  21                                                        /*!< LCD PAL252: G14_0 Position          */
+#define LCD_PAL252_G14_0_Msk                                  (0x1fUL << LCD_PAL252_G14_0_Pos)                          /*!< LCD PAL252: G14_0 Mask              */
+#define LCD_PAL252_B14_0_Pos                                  26                                                        /*!< LCD PAL252: B14_0 Position          */
+#define LCD_PAL252_B14_0_Msk                                  (0x1fUL << LCD_PAL252_B14_0_Pos)                          /*!< LCD PAL252: B14_0 Mask              */
+#define LCD_PAL252_I1_Pos                                     31                                                        /*!< LCD PAL252: I1 Position             */
+#define LCD_PAL252_I1_Msk                                     (0x01UL << LCD_PAL252_I1_Pos)                             /*!< LCD PAL252: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL253  -------------------------------------------
+#define LCD_PAL253_R04_0_Pos                                  0                                                         /*!< LCD PAL253: R04_0 Position          */
+#define LCD_PAL253_R04_0_Msk                                  (0x1fUL << LCD_PAL253_R04_0_Pos)                          /*!< LCD PAL253: R04_0 Mask              */
+#define LCD_PAL253_G04_0_Pos                                  5                                                         /*!< LCD PAL253: G04_0 Position          */
+#define LCD_PAL253_G04_0_Msk                                  (0x1fUL << LCD_PAL253_G04_0_Pos)                          /*!< LCD PAL253: G04_0 Mask              */
+#define LCD_PAL253_B04_0_Pos                                  10                                                        /*!< LCD PAL253: B04_0 Position          */
+#define LCD_PAL253_B04_0_Msk                                  (0x1fUL << LCD_PAL253_B04_0_Pos)                          /*!< LCD PAL253: B04_0 Mask              */
+#define LCD_PAL253_I0_Pos                                     15                                                        /*!< LCD PAL253: I0 Position             */
+#define LCD_PAL253_I0_Msk                                     (0x01UL << LCD_PAL253_I0_Pos)                             /*!< LCD PAL253: I0 Mask                 */
+#define LCD_PAL253_R14_0_Pos                                  16                                                        /*!< LCD PAL253: R14_0 Position          */
+#define LCD_PAL253_R14_0_Msk                                  (0x1fUL << LCD_PAL253_R14_0_Pos)                          /*!< LCD PAL253: R14_0 Mask              */
+#define LCD_PAL253_G14_0_Pos                                  21                                                        /*!< LCD PAL253: G14_0 Position          */
+#define LCD_PAL253_G14_0_Msk                                  (0x1fUL << LCD_PAL253_G14_0_Pos)                          /*!< LCD PAL253: G14_0 Mask              */
+#define LCD_PAL253_B14_0_Pos                                  26                                                        /*!< LCD PAL253: B14_0 Position          */
+#define LCD_PAL253_B14_0_Msk                                  (0x1fUL << LCD_PAL253_B14_0_Pos)                          /*!< LCD PAL253: B14_0 Mask              */
+#define LCD_PAL253_I1_Pos                                     31                                                        /*!< LCD PAL253: I1 Position             */
+#define LCD_PAL253_I1_Msk                                     (0x01UL << LCD_PAL253_I1_Pos)                             /*!< LCD PAL253: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL254  -------------------------------------------
+#define LCD_PAL254_R04_0_Pos                                  0                                                         /*!< LCD PAL254: R04_0 Position          */
+#define LCD_PAL254_R04_0_Msk                                  (0x1fUL << LCD_PAL254_R04_0_Pos)                          /*!< LCD PAL254: R04_0 Mask              */
+#define LCD_PAL254_G04_0_Pos                                  5                                                         /*!< LCD PAL254: G04_0 Position          */
+#define LCD_PAL254_G04_0_Msk                                  (0x1fUL << LCD_PAL254_G04_0_Pos)                          /*!< LCD PAL254: G04_0 Mask              */
+#define LCD_PAL254_B04_0_Pos                                  10                                                        /*!< LCD PAL254: B04_0 Position          */
+#define LCD_PAL254_B04_0_Msk                                  (0x1fUL << LCD_PAL254_B04_0_Pos)                          /*!< LCD PAL254: B04_0 Mask              */
+#define LCD_PAL254_I0_Pos                                     15                                                        /*!< LCD PAL254: I0 Position             */
+#define LCD_PAL254_I0_Msk                                     (0x01UL << LCD_PAL254_I0_Pos)                             /*!< LCD PAL254: I0 Mask                 */
+#define LCD_PAL254_R14_0_Pos                                  16                                                        /*!< LCD PAL254: R14_0 Position          */
+#define LCD_PAL254_R14_0_Msk                                  (0x1fUL << LCD_PAL254_R14_0_Pos)                          /*!< LCD PAL254: R14_0 Mask              */
+#define LCD_PAL254_G14_0_Pos                                  21                                                        /*!< LCD PAL254: G14_0 Position          */
+#define LCD_PAL254_G14_0_Msk                                  (0x1fUL << LCD_PAL254_G14_0_Pos)                          /*!< LCD PAL254: G14_0 Mask              */
+#define LCD_PAL254_B14_0_Pos                                  26                                                        /*!< LCD PAL254: B14_0 Position          */
+#define LCD_PAL254_B14_0_Msk                                  (0x1fUL << LCD_PAL254_B14_0_Pos)                          /*!< LCD PAL254: B14_0 Mask              */
+#define LCD_PAL254_I1_Pos                                     31                                                        /*!< LCD PAL254: I1 Position             */
+#define LCD_PAL254_I1_Msk                                     (0x01UL << LCD_PAL254_I1_Pos)                             /*!< LCD PAL254: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL255  -------------------------------------------
+#define LCD_PAL255_R04_0_Pos                                  0                                                         /*!< LCD PAL255: R04_0 Position          */
+#define LCD_PAL255_R04_0_Msk                                  (0x1fUL << LCD_PAL255_R04_0_Pos)                          /*!< LCD PAL255: R04_0 Mask              */
+#define LCD_PAL255_G04_0_Pos                                  5                                                         /*!< LCD PAL255: G04_0 Position          */
+#define LCD_PAL255_G04_0_Msk                                  (0x1fUL << LCD_PAL255_G04_0_Pos)                          /*!< LCD PAL255: G04_0 Mask              */
+#define LCD_PAL255_B04_0_Pos                                  10                                                        /*!< LCD PAL255: B04_0 Position          */
+#define LCD_PAL255_B04_0_Msk                                  (0x1fUL << LCD_PAL255_B04_0_Pos)                          /*!< LCD PAL255: B04_0 Mask              */
+#define LCD_PAL255_I0_Pos                                     15                                                        /*!< LCD PAL255: I0 Position             */
+#define LCD_PAL255_I0_Msk                                     (0x01UL << LCD_PAL255_I0_Pos)                             /*!< LCD PAL255: I0 Mask                 */
+#define LCD_PAL255_R14_0_Pos                                  16                                                        /*!< LCD PAL255: R14_0 Position          */
+#define LCD_PAL255_R14_0_Msk                                  (0x1fUL << LCD_PAL255_R14_0_Pos)                          /*!< LCD PAL255: R14_0 Mask              */
+#define LCD_PAL255_G14_0_Pos                                  21                                                        /*!< LCD PAL255: G14_0 Position          */
+#define LCD_PAL255_G14_0_Msk                                  (0x1fUL << LCD_PAL255_G14_0_Pos)                          /*!< LCD PAL255: G14_0 Mask              */
+#define LCD_PAL255_B14_0_Pos                                  26                                                        /*!< LCD PAL255: B14_0 Position          */
+#define LCD_PAL255_B14_0_Msk                                  (0x1fUL << LCD_PAL255_B14_0_Pos)                          /*!< LCD PAL255: B14_0 Mask              */
+#define LCD_PAL255_I1_Pos                                     31                                                        /*!< LCD PAL255: I1 Position             */
+#define LCD_PAL255_I1_Msk                                     (0x01UL << LCD_PAL255_I1_Pos)                             /*!< LCD PAL255: I1 Mask                 */
+
+// --------------------------------------  LCD_CRSR_IMG0  -----------------------------------------
+#define LCD_CRSR_IMG0_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG0: CRSR_IMG Position    */
+#define LCD_CRSR_IMG0_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG0: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG1  -----------------------------------------
+#define LCD_CRSR_IMG1_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG1: CRSR_IMG Position    */
+#define LCD_CRSR_IMG1_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG1: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG2  -----------------------------------------
+#define LCD_CRSR_IMG2_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG2: CRSR_IMG Position    */
+#define LCD_CRSR_IMG2_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG2: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG3  -----------------------------------------
+#define LCD_CRSR_IMG3_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG3: CRSR_IMG Position    */
+#define LCD_CRSR_IMG3_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG3: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG4  -----------------------------------------
+#define LCD_CRSR_IMG4_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG4: CRSR_IMG Position    */
+#define LCD_CRSR_IMG4_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG4: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG5  -----------------------------------------
+#define LCD_CRSR_IMG5_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG5: CRSR_IMG Position    */
+#define LCD_CRSR_IMG5_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG5: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG6  -----------------------------------------
+#define LCD_CRSR_IMG6_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG6: CRSR_IMG Position    */
+#define LCD_CRSR_IMG6_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG6: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG7  -----------------------------------------
+#define LCD_CRSR_IMG7_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG7: CRSR_IMG Position    */
+#define LCD_CRSR_IMG7_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG7: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG8  -----------------------------------------
+#define LCD_CRSR_IMG8_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG8: CRSR_IMG Position    */
+#define LCD_CRSR_IMG8_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG8: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG9  -----------------------------------------
+#define LCD_CRSR_IMG9_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG9: CRSR_IMG Position    */
+#define LCD_CRSR_IMG9_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG9: CRSR_IMG Mask        */
+
+// -------------------------------------  LCD_CRSR_IMG10  -----------------------------------------
+#define LCD_CRSR_IMG10_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG10: CRSR_IMG Position   */
+#define LCD_CRSR_IMG10_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG10: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG11  -----------------------------------------
+#define LCD_CRSR_IMG11_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG11: CRSR_IMG Position   */
+#define LCD_CRSR_IMG11_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG11: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG12  -----------------------------------------
+#define LCD_CRSR_IMG12_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG12: CRSR_IMG Position   */
+#define LCD_CRSR_IMG12_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG12: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG13  -----------------------------------------
+#define LCD_CRSR_IMG13_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG13: CRSR_IMG Position   */
+#define LCD_CRSR_IMG13_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG13: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG14  -----------------------------------------
+#define LCD_CRSR_IMG14_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG14: CRSR_IMG Position   */
+#define LCD_CRSR_IMG14_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG14: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG15  -----------------------------------------
+#define LCD_CRSR_IMG15_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG15: CRSR_IMG Position   */
+#define LCD_CRSR_IMG15_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG15: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG16  -----------------------------------------
+#define LCD_CRSR_IMG16_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG16: CRSR_IMG Position   */
+#define LCD_CRSR_IMG16_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG16: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG17  -----------------------------------------
+#define LCD_CRSR_IMG17_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG17: CRSR_IMG Position   */
+#define LCD_CRSR_IMG17_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG17: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG18  -----------------------------------------
+#define LCD_CRSR_IMG18_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG18: CRSR_IMG Position   */
+#define LCD_CRSR_IMG18_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG18: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG19  -----------------------------------------
+#define LCD_CRSR_IMG19_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG19: CRSR_IMG Position   */
+#define LCD_CRSR_IMG19_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG19: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG20  -----------------------------------------
+#define LCD_CRSR_IMG20_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG20: CRSR_IMG Position   */
+#define LCD_CRSR_IMG20_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG20: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG21  -----------------------------------------
+#define LCD_CRSR_IMG21_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG21: CRSR_IMG Position   */
+#define LCD_CRSR_IMG21_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG21: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG22  -----------------------------------------
+#define LCD_CRSR_IMG22_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG22: CRSR_IMG Position   */
+#define LCD_CRSR_IMG22_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG22: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG23  -----------------------------------------
+#define LCD_CRSR_IMG23_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG23: CRSR_IMG Position   */
+#define LCD_CRSR_IMG23_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG23: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG24  -----------------------------------------
+#define LCD_CRSR_IMG24_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG24: CRSR_IMG Position   */
+#define LCD_CRSR_IMG24_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG24: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG25  -----------------------------------------
+#define LCD_CRSR_IMG25_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG25: CRSR_IMG Position   */
+#define LCD_CRSR_IMG25_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG25: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG26  -----------------------------------------
+#define LCD_CRSR_IMG26_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG26: CRSR_IMG Position   */
+#define LCD_CRSR_IMG26_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG26: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG27  -----------------------------------------
+#define LCD_CRSR_IMG27_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG27: CRSR_IMG Position   */
+#define LCD_CRSR_IMG27_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG27: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG28  -----------------------------------------
+#define LCD_CRSR_IMG28_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG28: CRSR_IMG Position   */
+#define LCD_CRSR_IMG28_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG28: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG29  -----------------------------------------
+#define LCD_CRSR_IMG29_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG29: CRSR_IMG Position   */
+#define LCD_CRSR_IMG29_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG29: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG30  -----------------------------------------
+#define LCD_CRSR_IMG30_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG30: CRSR_IMG Position   */
+#define LCD_CRSR_IMG30_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG30: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG31  -----------------------------------------
+#define LCD_CRSR_IMG31_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG31: CRSR_IMG Position   */
+#define LCD_CRSR_IMG31_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG31: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG32  -----------------------------------------
+#define LCD_CRSR_IMG32_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG32: CRSR_IMG Position   */
+#define LCD_CRSR_IMG32_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG32: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG33  -----------------------------------------
+#define LCD_CRSR_IMG33_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG33: CRSR_IMG Position   */
+#define LCD_CRSR_IMG33_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG33: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG34  -----------------------------------------
+#define LCD_CRSR_IMG34_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG34: CRSR_IMG Position   */
+#define LCD_CRSR_IMG34_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG34: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG35  -----------------------------------------
+#define LCD_CRSR_IMG35_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG35: CRSR_IMG Position   */
+#define LCD_CRSR_IMG35_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG35: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG36  -----------------------------------------
+#define LCD_CRSR_IMG36_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG36: CRSR_IMG Position   */
+#define LCD_CRSR_IMG36_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG36: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG37  -----------------------------------------
+#define LCD_CRSR_IMG37_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG37: CRSR_IMG Position   */
+#define LCD_CRSR_IMG37_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG37: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG38  -----------------------------------------
+#define LCD_CRSR_IMG38_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG38: CRSR_IMG Position   */
+#define LCD_CRSR_IMG38_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG38: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG39  -----------------------------------------
+#define LCD_CRSR_IMG39_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG39: CRSR_IMG Position   */
+#define LCD_CRSR_IMG39_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG39: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG40  -----------------------------------------
+#define LCD_CRSR_IMG40_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG40: CRSR_IMG Position   */
+#define LCD_CRSR_IMG40_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG40: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG41  -----------------------------------------
+#define LCD_CRSR_IMG41_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG41: CRSR_IMG Position   */
+#define LCD_CRSR_IMG41_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG41: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG42  -----------------------------------------
+#define LCD_CRSR_IMG42_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG42: CRSR_IMG Position   */
+#define LCD_CRSR_IMG42_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG42: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG43  -----------------------------------------
+#define LCD_CRSR_IMG43_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG43: CRSR_IMG Position   */
+#define LCD_CRSR_IMG43_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG43: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG44  -----------------------------------------
+#define LCD_CRSR_IMG44_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG44: CRSR_IMG Position   */
+#define LCD_CRSR_IMG44_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG44: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG45  -----------------------------------------
+#define LCD_CRSR_IMG45_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG45: CRSR_IMG Position   */
+#define LCD_CRSR_IMG45_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG45: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG46  -----------------------------------------
+#define LCD_CRSR_IMG46_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG46: CRSR_IMG Position   */
+#define LCD_CRSR_IMG46_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG46: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG47  -----------------------------------------
+#define LCD_CRSR_IMG47_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG47: CRSR_IMG Position   */
+#define LCD_CRSR_IMG47_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG47: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG48  -----------------------------------------
+#define LCD_CRSR_IMG48_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG48: CRSR_IMG Position   */
+#define LCD_CRSR_IMG48_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG48: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG49  -----------------------------------------
+#define LCD_CRSR_IMG49_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG49: CRSR_IMG Position   */
+#define LCD_CRSR_IMG49_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG49: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG50  -----------------------------------------
+#define LCD_CRSR_IMG50_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG50: CRSR_IMG Position   */
+#define LCD_CRSR_IMG50_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG50: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG51  -----------------------------------------
+#define LCD_CRSR_IMG51_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG51: CRSR_IMG Position   */
+#define LCD_CRSR_IMG51_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG51: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG52  -----------------------------------------
+#define LCD_CRSR_IMG52_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG52: CRSR_IMG Position   */
+#define LCD_CRSR_IMG52_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG52: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG53  -----------------------------------------
+#define LCD_CRSR_IMG53_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG53: CRSR_IMG Position   */
+#define LCD_CRSR_IMG53_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG53: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG54  -----------------------------------------
+#define LCD_CRSR_IMG54_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG54: CRSR_IMG Position   */
+#define LCD_CRSR_IMG54_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG54: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG55  -----------------------------------------
+#define LCD_CRSR_IMG55_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG55: CRSR_IMG Position   */
+#define LCD_CRSR_IMG55_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG55: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG56  -----------------------------------------
+#define LCD_CRSR_IMG56_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG56: CRSR_IMG Position   */
+#define LCD_CRSR_IMG56_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG56: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG57  -----------------------------------------
+#define LCD_CRSR_IMG57_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG57: CRSR_IMG Position   */
+#define LCD_CRSR_IMG57_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG57: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG58  -----------------------------------------
+#define LCD_CRSR_IMG58_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG58: CRSR_IMG Position   */
+#define LCD_CRSR_IMG58_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG58: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG59  -----------------------------------------
+#define LCD_CRSR_IMG59_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG59: CRSR_IMG Position   */
+#define LCD_CRSR_IMG59_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG59: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG60  -----------------------------------------
+#define LCD_CRSR_IMG60_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG60: CRSR_IMG Position   */
+#define LCD_CRSR_IMG60_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG60: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG61  -----------------------------------------
+#define LCD_CRSR_IMG61_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG61: CRSR_IMG Position   */
+#define LCD_CRSR_IMG61_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG61: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG62  -----------------------------------------
+#define LCD_CRSR_IMG62_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG62: CRSR_IMG Position   */
+#define LCD_CRSR_IMG62_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG62: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG63  -----------------------------------------
+#define LCD_CRSR_IMG63_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG63: CRSR_IMG Position   */
+#define LCD_CRSR_IMG63_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG63: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG64  -----------------------------------------
+#define LCD_CRSR_IMG64_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG64: CRSR_IMG Position   */
+#define LCD_CRSR_IMG64_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG64: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG65  -----------------------------------------
+#define LCD_CRSR_IMG65_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG65: CRSR_IMG Position   */
+#define LCD_CRSR_IMG65_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG65: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG66  -----------------------------------------
+#define LCD_CRSR_IMG66_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG66: CRSR_IMG Position   */
+#define LCD_CRSR_IMG66_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG66: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG67  -----------------------------------------
+#define LCD_CRSR_IMG67_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG67: CRSR_IMG Position   */
+#define LCD_CRSR_IMG67_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG67: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG68  -----------------------------------------
+#define LCD_CRSR_IMG68_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG68: CRSR_IMG Position   */
+#define LCD_CRSR_IMG68_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG68: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG69  -----------------------------------------
+#define LCD_CRSR_IMG69_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG69: CRSR_IMG Position   */
+#define LCD_CRSR_IMG69_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG69: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG70  -----------------------------------------
+#define LCD_CRSR_IMG70_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG70: CRSR_IMG Position   */
+#define LCD_CRSR_IMG70_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG70: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG71  -----------------------------------------
+#define LCD_CRSR_IMG71_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG71: CRSR_IMG Position   */
+#define LCD_CRSR_IMG71_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG71: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG72  -----------------------------------------
+#define LCD_CRSR_IMG72_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG72: CRSR_IMG Position   */
+#define LCD_CRSR_IMG72_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG72: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG73  -----------------------------------------
+#define LCD_CRSR_IMG73_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG73: CRSR_IMG Position   */
+#define LCD_CRSR_IMG73_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG73: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG74  -----------------------------------------
+#define LCD_CRSR_IMG74_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG74: CRSR_IMG Position   */
+#define LCD_CRSR_IMG74_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG74: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG75  -----------------------------------------
+#define LCD_CRSR_IMG75_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG75: CRSR_IMG Position   */
+#define LCD_CRSR_IMG75_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG75: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG76  -----------------------------------------
+#define LCD_CRSR_IMG76_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG76: CRSR_IMG Position   */
+#define LCD_CRSR_IMG76_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG76: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG77  -----------------------------------------
+#define LCD_CRSR_IMG77_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG77: CRSR_IMG Position   */
+#define LCD_CRSR_IMG77_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG77: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG78  -----------------------------------------
+#define LCD_CRSR_IMG78_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG78: CRSR_IMG Position   */
+#define LCD_CRSR_IMG78_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG78: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG79  -----------------------------------------
+#define LCD_CRSR_IMG79_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG79: CRSR_IMG Position   */
+#define LCD_CRSR_IMG79_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG79: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG80  -----------------------------------------
+#define LCD_CRSR_IMG80_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG80: CRSR_IMG Position   */
+#define LCD_CRSR_IMG80_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG80: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG81  -----------------------------------------
+#define LCD_CRSR_IMG81_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG81: CRSR_IMG Position   */
+#define LCD_CRSR_IMG81_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG81: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG82  -----------------------------------------
+#define LCD_CRSR_IMG82_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG82: CRSR_IMG Position   */
+#define LCD_CRSR_IMG82_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG82: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG83  -----------------------------------------
+#define LCD_CRSR_IMG83_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG83: CRSR_IMG Position   */
+#define LCD_CRSR_IMG83_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG83: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG84  -----------------------------------------
+#define LCD_CRSR_IMG84_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG84: CRSR_IMG Position   */
+#define LCD_CRSR_IMG84_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG84: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG85  -----------------------------------------
+#define LCD_CRSR_IMG85_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG85: CRSR_IMG Position   */
+#define LCD_CRSR_IMG85_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG85: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG86  -----------------------------------------
+#define LCD_CRSR_IMG86_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG86: CRSR_IMG Position   */
+#define LCD_CRSR_IMG86_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG86: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG87  -----------------------------------------
+#define LCD_CRSR_IMG87_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG87: CRSR_IMG Position   */
+#define LCD_CRSR_IMG87_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG87: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG88  -----------------------------------------
+#define LCD_CRSR_IMG88_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG88: CRSR_IMG Position   */
+#define LCD_CRSR_IMG88_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG88: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG89  -----------------------------------------
+#define LCD_CRSR_IMG89_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG89: CRSR_IMG Position   */
+#define LCD_CRSR_IMG89_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG89: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG90  -----------------------------------------
+#define LCD_CRSR_IMG90_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG90: CRSR_IMG Position   */
+#define LCD_CRSR_IMG90_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG90: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG91  -----------------------------------------
+#define LCD_CRSR_IMG91_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG91: CRSR_IMG Position   */
+#define LCD_CRSR_IMG91_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG91: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG92  -----------------------------------------
+#define LCD_CRSR_IMG92_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG92: CRSR_IMG Position   */
+#define LCD_CRSR_IMG92_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG92: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG93  -----------------------------------------
+#define LCD_CRSR_IMG93_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG93: CRSR_IMG Position   */
+#define LCD_CRSR_IMG93_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG93: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG94  -----------------------------------------
+#define LCD_CRSR_IMG94_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG94: CRSR_IMG Position   */
+#define LCD_CRSR_IMG94_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG94: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG95  -----------------------------------------
+#define LCD_CRSR_IMG95_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG95: CRSR_IMG Position   */
+#define LCD_CRSR_IMG95_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG95: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG96  -----------------------------------------
+#define LCD_CRSR_IMG96_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG96: CRSR_IMG Position   */
+#define LCD_CRSR_IMG96_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG96: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG97  -----------------------------------------
+#define LCD_CRSR_IMG97_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG97: CRSR_IMG Position   */
+#define LCD_CRSR_IMG97_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG97: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG98  -----------------------------------------
+#define LCD_CRSR_IMG98_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG98: CRSR_IMG Position   */
+#define LCD_CRSR_IMG98_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG98: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG99  -----------------------------------------
+#define LCD_CRSR_IMG99_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG99: CRSR_IMG Position   */
+#define LCD_CRSR_IMG99_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG99: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG100  ----------------------------------------
+#define LCD_CRSR_IMG100_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG100: CRSR_IMG Position  */
+#define LCD_CRSR_IMG100_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG100: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG101  ----------------------------------------
+#define LCD_CRSR_IMG101_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG101: CRSR_IMG Position  */
+#define LCD_CRSR_IMG101_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG101: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG102  ----------------------------------------
+#define LCD_CRSR_IMG102_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG102: CRSR_IMG Position  */
+#define LCD_CRSR_IMG102_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG102: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG103  ----------------------------------------
+#define LCD_CRSR_IMG103_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG103: CRSR_IMG Position  */
+#define LCD_CRSR_IMG103_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG103: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG104  ----------------------------------------
+#define LCD_CRSR_IMG104_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG104: CRSR_IMG Position  */
+#define LCD_CRSR_IMG104_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG104: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG105  ----------------------------------------
+#define LCD_CRSR_IMG105_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG105: CRSR_IMG Position  */
+#define LCD_CRSR_IMG105_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG105: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG106  ----------------------------------------
+#define LCD_CRSR_IMG106_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG106: CRSR_IMG Position  */
+#define LCD_CRSR_IMG106_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG106: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG107  ----------------------------------------
+#define LCD_CRSR_IMG107_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG107: CRSR_IMG Position  */
+#define LCD_CRSR_IMG107_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG107: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG108  ----------------------------------------
+#define LCD_CRSR_IMG108_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG108: CRSR_IMG Position  */
+#define LCD_CRSR_IMG108_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG108: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG109  ----------------------------------------
+#define LCD_CRSR_IMG109_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG109: CRSR_IMG Position  */
+#define LCD_CRSR_IMG109_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG109: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG110  ----------------------------------------
+#define LCD_CRSR_IMG110_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG110: CRSR_IMG Position  */
+#define LCD_CRSR_IMG110_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG110: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG111  ----------------------------------------
+#define LCD_CRSR_IMG111_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG111: CRSR_IMG Position  */
+#define LCD_CRSR_IMG111_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG111: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG112  ----------------------------------------
+#define LCD_CRSR_IMG112_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG112: CRSR_IMG Position  */
+#define LCD_CRSR_IMG112_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG112: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG113  ----------------------------------------
+#define LCD_CRSR_IMG113_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG113: CRSR_IMG Position  */
+#define LCD_CRSR_IMG113_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG113: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG114  ----------------------------------------
+#define LCD_CRSR_IMG114_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG114: CRSR_IMG Position  */
+#define LCD_CRSR_IMG114_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG114: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG115  ----------------------------------------
+#define LCD_CRSR_IMG115_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG115: CRSR_IMG Position  */
+#define LCD_CRSR_IMG115_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG115: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG116  ----------------------------------------
+#define LCD_CRSR_IMG116_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG116: CRSR_IMG Position  */
+#define LCD_CRSR_IMG116_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG116: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG117  ----------------------------------------
+#define LCD_CRSR_IMG117_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG117: CRSR_IMG Position  */
+#define LCD_CRSR_IMG117_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG117: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG118  ----------------------------------------
+#define LCD_CRSR_IMG118_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG118: CRSR_IMG Position  */
+#define LCD_CRSR_IMG118_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG118: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG119  ----------------------------------------
+#define LCD_CRSR_IMG119_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG119: CRSR_IMG Position  */
+#define LCD_CRSR_IMG119_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG119: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG120  ----------------------------------------
+#define LCD_CRSR_IMG120_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG120: CRSR_IMG Position  */
+#define LCD_CRSR_IMG120_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG120: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG121  ----------------------------------------
+#define LCD_CRSR_IMG121_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG121: CRSR_IMG Position  */
+#define LCD_CRSR_IMG121_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG121: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG122  ----------------------------------------
+#define LCD_CRSR_IMG122_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG122: CRSR_IMG Position  */
+#define LCD_CRSR_IMG122_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG122: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG123  ----------------------------------------
+#define LCD_CRSR_IMG123_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG123: CRSR_IMG Position  */
+#define LCD_CRSR_IMG123_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG123: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG124  ----------------------------------------
+#define LCD_CRSR_IMG124_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG124: CRSR_IMG Position  */
+#define LCD_CRSR_IMG124_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG124: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG125  ----------------------------------------
+#define LCD_CRSR_IMG125_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG125: CRSR_IMG Position  */
+#define LCD_CRSR_IMG125_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG125: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG126  ----------------------------------------
+#define LCD_CRSR_IMG126_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG126: CRSR_IMG Position  */
+#define LCD_CRSR_IMG126_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG126: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG127  ----------------------------------------
+#define LCD_CRSR_IMG127_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG127: CRSR_IMG Position  */
+#define LCD_CRSR_IMG127_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG127: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG128  ----------------------------------------
+#define LCD_CRSR_IMG128_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG128: CRSR_IMG Position  */
+#define LCD_CRSR_IMG128_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG128: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG129  ----------------------------------------
+#define LCD_CRSR_IMG129_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG129: CRSR_IMG Position  */
+#define LCD_CRSR_IMG129_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG129: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG130  ----------------------------------------
+#define LCD_CRSR_IMG130_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG130: CRSR_IMG Position  */
+#define LCD_CRSR_IMG130_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG130: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG131  ----------------------------------------
+#define LCD_CRSR_IMG131_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG131: CRSR_IMG Position  */
+#define LCD_CRSR_IMG131_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG131: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG132  ----------------------------------------
+#define LCD_CRSR_IMG132_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG132: CRSR_IMG Position  */
+#define LCD_CRSR_IMG132_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG132: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG133  ----------------------------------------
+#define LCD_CRSR_IMG133_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG133: CRSR_IMG Position  */
+#define LCD_CRSR_IMG133_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG133: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG134  ----------------------------------------
+#define LCD_CRSR_IMG134_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG134: CRSR_IMG Position  */
+#define LCD_CRSR_IMG134_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG134: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG135  ----------------------------------------
+#define LCD_CRSR_IMG135_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG135: CRSR_IMG Position  */
+#define LCD_CRSR_IMG135_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG135: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG136  ----------------------------------------
+#define LCD_CRSR_IMG136_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG136: CRSR_IMG Position  */
+#define LCD_CRSR_IMG136_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG136: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG137  ----------------------------------------
+#define LCD_CRSR_IMG137_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG137: CRSR_IMG Position  */
+#define LCD_CRSR_IMG137_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG137: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG138  ----------------------------------------
+#define LCD_CRSR_IMG138_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG138: CRSR_IMG Position  */
+#define LCD_CRSR_IMG138_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG138: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG139  ----------------------------------------
+#define LCD_CRSR_IMG139_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG139: CRSR_IMG Position  */
+#define LCD_CRSR_IMG139_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG139: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG140  ----------------------------------------
+#define LCD_CRSR_IMG140_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG140: CRSR_IMG Position  */
+#define LCD_CRSR_IMG140_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG140: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG141  ----------------------------------------
+#define LCD_CRSR_IMG141_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG141: CRSR_IMG Position  */
+#define LCD_CRSR_IMG141_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG141: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG142  ----------------------------------------
+#define LCD_CRSR_IMG142_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG142: CRSR_IMG Position  */
+#define LCD_CRSR_IMG142_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG142: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG143  ----------------------------------------
+#define LCD_CRSR_IMG143_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG143: CRSR_IMG Position  */
+#define LCD_CRSR_IMG143_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG143: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG144  ----------------------------------------
+#define LCD_CRSR_IMG144_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG144: CRSR_IMG Position  */
+#define LCD_CRSR_IMG144_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG144: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG145  ----------------------------------------
+#define LCD_CRSR_IMG145_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG145: CRSR_IMG Position  */
+#define LCD_CRSR_IMG145_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG145: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG146  ----------------------------------------
+#define LCD_CRSR_IMG146_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG146: CRSR_IMG Position  */
+#define LCD_CRSR_IMG146_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG146: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG147  ----------------------------------------
+#define LCD_CRSR_IMG147_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG147: CRSR_IMG Position  */
+#define LCD_CRSR_IMG147_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG147: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG148  ----------------------------------------
+#define LCD_CRSR_IMG148_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG148: CRSR_IMG Position  */
+#define LCD_CRSR_IMG148_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG148: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG149  ----------------------------------------
+#define LCD_CRSR_IMG149_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG149: CRSR_IMG Position  */
+#define LCD_CRSR_IMG149_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG149: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG150  ----------------------------------------
+#define LCD_CRSR_IMG150_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG150: CRSR_IMG Position  */
+#define LCD_CRSR_IMG150_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG150: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG151  ----------------------------------------
+#define LCD_CRSR_IMG151_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG151: CRSR_IMG Position  */
+#define LCD_CRSR_IMG151_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG151: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG152  ----------------------------------------
+#define LCD_CRSR_IMG152_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG152: CRSR_IMG Position  */
+#define LCD_CRSR_IMG152_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG152: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG153  ----------------------------------------
+#define LCD_CRSR_IMG153_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG153: CRSR_IMG Position  */
+#define LCD_CRSR_IMG153_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG153: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG154  ----------------------------------------
+#define LCD_CRSR_IMG154_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG154: CRSR_IMG Position  */
+#define LCD_CRSR_IMG154_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG154: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG155  ----------------------------------------
+#define LCD_CRSR_IMG155_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG155: CRSR_IMG Position  */
+#define LCD_CRSR_IMG155_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG155: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG156  ----------------------------------------
+#define LCD_CRSR_IMG156_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG156: CRSR_IMG Position  */
+#define LCD_CRSR_IMG156_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG156: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG157  ----------------------------------------
+#define LCD_CRSR_IMG157_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG157: CRSR_IMG Position  */
+#define LCD_CRSR_IMG157_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG157: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG158  ----------------------------------------
+#define LCD_CRSR_IMG158_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG158: CRSR_IMG Position  */
+#define LCD_CRSR_IMG158_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG158: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG159  ----------------------------------------
+#define LCD_CRSR_IMG159_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG159: CRSR_IMG Position  */
+#define LCD_CRSR_IMG159_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG159: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG160  ----------------------------------------
+#define LCD_CRSR_IMG160_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG160: CRSR_IMG Position  */
+#define LCD_CRSR_IMG160_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG160: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG161  ----------------------------------------
+#define LCD_CRSR_IMG161_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG161: CRSR_IMG Position  */
+#define LCD_CRSR_IMG161_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG161: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG162  ----------------------------------------
+#define LCD_CRSR_IMG162_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG162: CRSR_IMG Position  */
+#define LCD_CRSR_IMG162_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG162: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG163  ----------------------------------------
+#define LCD_CRSR_IMG163_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG163: CRSR_IMG Position  */
+#define LCD_CRSR_IMG163_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG163: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG164  ----------------------------------------
+#define LCD_CRSR_IMG164_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG164: CRSR_IMG Position  */
+#define LCD_CRSR_IMG164_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG164: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG165  ----------------------------------------
+#define LCD_CRSR_IMG165_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG165: CRSR_IMG Position  */
+#define LCD_CRSR_IMG165_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG165: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG166  ----------------------------------------
+#define LCD_CRSR_IMG166_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG166: CRSR_IMG Position  */
+#define LCD_CRSR_IMG166_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG166: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG167  ----------------------------------------
+#define LCD_CRSR_IMG167_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG167: CRSR_IMG Position  */
+#define LCD_CRSR_IMG167_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG167: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG168  ----------------------------------------
+#define LCD_CRSR_IMG168_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG168: CRSR_IMG Position  */
+#define LCD_CRSR_IMG168_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG168: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG169  ----------------------------------------
+#define LCD_CRSR_IMG169_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG169: CRSR_IMG Position  */
+#define LCD_CRSR_IMG169_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG169: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG170  ----------------------------------------
+#define LCD_CRSR_IMG170_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG170: CRSR_IMG Position  */
+#define LCD_CRSR_IMG170_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG170: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG171  ----------------------------------------
+#define LCD_CRSR_IMG171_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG171: CRSR_IMG Position  */
+#define LCD_CRSR_IMG171_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG171: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG172  ----------------------------------------
+#define LCD_CRSR_IMG172_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG172: CRSR_IMG Position  */
+#define LCD_CRSR_IMG172_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG172: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG173  ----------------------------------------
+#define LCD_CRSR_IMG173_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG173: CRSR_IMG Position  */
+#define LCD_CRSR_IMG173_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG173: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG174  ----------------------------------------
+#define LCD_CRSR_IMG174_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG174: CRSR_IMG Position  */
+#define LCD_CRSR_IMG174_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG174: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG175  ----------------------------------------
+#define LCD_CRSR_IMG175_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG175: CRSR_IMG Position  */
+#define LCD_CRSR_IMG175_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG175: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG176  ----------------------------------------
+#define LCD_CRSR_IMG176_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG176: CRSR_IMG Position  */
+#define LCD_CRSR_IMG176_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG176: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG177  ----------------------------------------
+#define LCD_CRSR_IMG177_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG177: CRSR_IMG Position  */
+#define LCD_CRSR_IMG177_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG177: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG178  ----------------------------------------
+#define LCD_CRSR_IMG178_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG178: CRSR_IMG Position  */
+#define LCD_CRSR_IMG178_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG178: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG179  ----------------------------------------
+#define LCD_CRSR_IMG179_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG179: CRSR_IMG Position  */
+#define LCD_CRSR_IMG179_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG179: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG180  ----------------------------------------
+#define LCD_CRSR_IMG180_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG180: CRSR_IMG Position  */
+#define LCD_CRSR_IMG180_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG180: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG181  ----------------------------------------
+#define LCD_CRSR_IMG181_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG181: CRSR_IMG Position  */
+#define LCD_CRSR_IMG181_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG181: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG182  ----------------------------------------
+#define LCD_CRSR_IMG182_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG182: CRSR_IMG Position  */
+#define LCD_CRSR_IMG182_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG182: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG183  ----------------------------------------
+#define LCD_CRSR_IMG183_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG183: CRSR_IMG Position  */
+#define LCD_CRSR_IMG183_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG183: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG184  ----------------------------------------
+#define LCD_CRSR_IMG184_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG184: CRSR_IMG Position  */
+#define LCD_CRSR_IMG184_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG184: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG185  ----------------------------------------
+#define LCD_CRSR_IMG185_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG185: CRSR_IMG Position  */
+#define LCD_CRSR_IMG185_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG185: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG186  ----------------------------------------
+#define LCD_CRSR_IMG186_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG186: CRSR_IMG Position  */
+#define LCD_CRSR_IMG186_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG186: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG187  ----------------------------------------
+#define LCD_CRSR_IMG187_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG187: CRSR_IMG Position  */
+#define LCD_CRSR_IMG187_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG187: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG188  ----------------------------------------
+#define LCD_CRSR_IMG188_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG188: CRSR_IMG Position  */
+#define LCD_CRSR_IMG188_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG188: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG189  ----------------------------------------
+#define LCD_CRSR_IMG189_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG189: CRSR_IMG Position  */
+#define LCD_CRSR_IMG189_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG189: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG190  ----------------------------------------
+#define LCD_CRSR_IMG190_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG190: CRSR_IMG Position  */
+#define LCD_CRSR_IMG190_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG190: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG191  ----------------------------------------
+#define LCD_CRSR_IMG191_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG191: CRSR_IMG Position  */
+#define LCD_CRSR_IMG191_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG191: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG192  ----------------------------------------
+#define LCD_CRSR_IMG192_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG192: CRSR_IMG Position  */
+#define LCD_CRSR_IMG192_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG192: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG193  ----------------------------------------
+#define LCD_CRSR_IMG193_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG193: CRSR_IMG Position  */
+#define LCD_CRSR_IMG193_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG193: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG194  ----------------------------------------
+#define LCD_CRSR_IMG194_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG194: CRSR_IMG Position  */
+#define LCD_CRSR_IMG194_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG194: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG195  ----------------------------------------
+#define LCD_CRSR_IMG195_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG195: CRSR_IMG Position  */
+#define LCD_CRSR_IMG195_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG195: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG196  ----------------------------------------
+#define LCD_CRSR_IMG196_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG196: CRSR_IMG Position  */
+#define LCD_CRSR_IMG196_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG196: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG197  ----------------------------------------
+#define LCD_CRSR_IMG197_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG197: CRSR_IMG Position  */
+#define LCD_CRSR_IMG197_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG197: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG198  ----------------------------------------
+#define LCD_CRSR_IMG198_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG198: CRSR_IMG Position  */
+#define LCD_CRSR_IMG198_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG198: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG199  ----------------------------------------
+#define LCD_CRSR_IMG199_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG199: CRSR_IMG Position  */
+#define LCD_CRSR_IMG199_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG199: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG200  ----------------------------------------
+#define LCD_CRSR_IMG200_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG200: CRSR_IMG Position  */
+#define LCD_CRSR_IMG200_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG200: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG201  ----------------------------------------
+#define LCD_CRSR_IMG201_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG201: CRSR_IMG Position  */
+#define LCD_CRSR_IMG201_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG201: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG202  ----------------------------------------
+#define LCD_CRSR_IMG202_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG202: CRSR_IMG Position  */
+#define LCD_CRSR_IMG202_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG202: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG203  ----------------------------------------
+#define LCD_CRSR_IMG203_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG203: CRSR_IMG Position  */
+#define LCD_CRSR_IMG203_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG203: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG204  ----------------------------------------
+#define LCD_CRSR_IMG204_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG204: CRSR_IMG Position  */
+#define LCD_CRSR_IMG204_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG204: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG205  ----------------------------------------
+#define LCD_CRSR_IMG205_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG205: CRSR_IMG Position  */
+#define LCD_CRSR_IMG205_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG205: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG206  ----------------------------------------
+#define LCD_CRSR_IMG206_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG206: CRSR_IMG Position  */
+#define LCD_CRSR_IMG206_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG206: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG207  ----------------------------------------
+#define LCD_CRSR_IMG207_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG207: CRSR_IMG Position  */
+#define LCD_CRSR_IMG207_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG207: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG208  ----------------------------------------
+#define LCD_CRSR_IMG208_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG208: CRSR_IMG Position  */
+#define LCD_CRSR_IMG208_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG208: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG209  ----------------------------------------
+#define LCD_CRSR_IMG209_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG209: CRSR_IMG Position  */
+#define LCD_CRSR_IMG209_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG209: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG210  ----------------------------------------
+#define LCD_CRSR_IMG210_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG210: CRSR_IMG Position  */
+#define LCD_CRSR_IMG210_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG210: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG211  ----------------------------------------
+#define LCD_CRSR_IMG211_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG211: CRSR_IMG Position  */
+#define LCD_CRSR_IMG211_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG211: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG212  ----------------------------------------
+#define LCD_CRSR_IMG212_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG212: CRSR_IMG Position  */
+#define LCD_CRSR_IMG212_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG212: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG213  ----------------------------------------
+#define LCD_CRSR_IMG213_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG213: CRSR_IMG Position  */
+#define LCD_CRSR_IMG213_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG213: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG214  ----------------------------------------
+#define LCD_CRSR_IMG214_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG214: CRSR_IMG Position  */
+#define LCD_CRSR_IMG214_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG214: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG215  ----------------------------------------
+#define LCD_CRSR_IMG215_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG215: CRSR_IMG Position  */
+#define LCD_CRSR_IMG215_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG215: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG216  ----------------------------------------
+#define LCD_CRSR_IMG216_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG216: CRSR_IMG Position  */
+#define LCD_CRSR_IMG216_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG216: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG217  ----------------------------------------
+#define LCD_CRSR_IMG217_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG217: CRSR_IMG Position  */
+#define LCD_CRSR_IMG217_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG217: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG218  ----------------------------------------
+#define LCD_CRSR_IMG218_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG218: CRSR_IMG Position  */
+#define LCD_CRSR_IMG218_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG218: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG219  ----------------------------------------
+#define LCD_CRSR_IMG219_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG219: CRSR_IMG Position  */
+#define LCD_CRSR_IMG219_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG219: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG220  ----------------------------------------
+#define LCD_CRSR_IMG220_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG220: CRSR_IMG Position  */
+#define LCD_CRSR_IMG220_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG220: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG221  ----------------------------------------
+#define LCD_CRSR_IMG221_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG221: CRSR_IMG Position  */
+#define LCD_CRSR_IMG221_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG221: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG222  ----------------------------------------
+#define LCD_CRSR_IMG222_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG222: CRSR_IMG Position  */
+#define LCD_CRSR_IMG222_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG222: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG223  ----------------------------------------
+#define LCD_CRSR_IMG223_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG223: CRSR_IMG Position  */
+#define LCD_CRSR_IMG223_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG223: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG224  ----------------------------------------
+#define LCD_CRSR_IMG224_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG224: CRSR_IMG Position  */
+#define LCD_CRSR_IMG224_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG224: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG225  ----------------------------------------
+#define LCD_CRSR_IMG225_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG225: CRSR_IMG Position  */
+#define LCD_CRSR_IMG225_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG225: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG226  ----------------------------------------
+#define LCD_CRSR_IMG226_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG226: CRSR_IMG Position  */
+#define LCD_CRSR_IMG226_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG226: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG227  ----------------------------------------
+#define LCD_CRSR_IMG227_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG227: CRSR_IMG Position  */
+#define LCD_CRSR_IMG227_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG227: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG228  ----------------------------------------
+#define LCD_CRSR_IMG228_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG228: CRSR_IMG Position  */
+#define LCD_CRSR_IMG228_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG228: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG229  ----------------------------------------
+#define LCD_CRSR_IMG229_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG229: CRSR_IMG Position  */
+#define LCD_CRSR_IMG229_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG229: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG230  ----------------------------------------
+#define LCD_CRSR_IMG230_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG230: CRSR_IMG Position  */
+#define LCD_CRSR_IMG230_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG230: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG231  ----------------------------------------
+#define LCD_CRSR_IMG231_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG231: CRSR_IMG Position  */
+#define LCD_CRSR_IMG231_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG231: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG232  ----------------------------------------
+#define LCD_CRSR_IMG232_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG232: CRSR_IMG Position  */
+#define LCD_CRSR_IMG232_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG232: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG233  ----------------------------------------
+#define LCD_CRSR_IMG233_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG233: CRSR_IMG Position  */
+#define LCD_CRSR_IMG233_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG233: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG234  ----------------------------------------
+#define LCD_CRSR_IMG234_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG234: CRSR_IMG Position  */
+#define LCD_CRSR_IMG234_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG234: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG235  ----------------------------------------
+#define LCD_CRSR_IMG235_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG235: CRSR_IMG Position  */
+#define LCD_CRSR_IMG235_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG235: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG236  ----------------------------------------
+#define LCD_CRSR_IMG236_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG236: CRSR_IMG Position  */
+#define LCD_CRSR_IMG236_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG236: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG237  ----------------------------------------
+#define LCD_CRSR_IMG237_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG237: CRSR_IMG Position  */
+#define LCD_CRSR_IMG237_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG237: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG238  ----------------------------------------
+#define LCD_CRSR_IMG238_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG238: CRSR_IMG Position  */
+#define LCD_CRSR_IMG238_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG238: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG239  ----------------------------------------
+#define LCD_CRSR_IMG239_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG239: CRSR_IMG Position  */
+#define LCD_CRSR_IMG239_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG239: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG240  ----------------------------------------
+#define LCD_CRSR_IMG240_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG240: CRSR_IMG Position  */
+#define LCD_CRSR_IMG240_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG240: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG241  ----------------------------------------
+#define LCD_CRSR_IMG241_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG241: CRSR_IMG Position  */
+#define LCD_CRSR_IMG241_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG241: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG242  ----------------------------------------
+#define LCD_CRSR_IMG242_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG242: CRSR_IMG Position  */
+#define LCD_CRSR_IMG242_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG242: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG243  ----------------------------------------
+#define LCD_CRSR_IMG243_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG243: CRSR_IMG Position  */
+#define LCD_CRSR_IMG243_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG243: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG244  ----------------------------------------
+#define LCD_CRSR_IMG244_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG244: CRSR_IMG Position  */
+#define LCD_CRSR_IMG244_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG244: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG245  ----------------------------------------
+#define LCD_CRSR_IMG245_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG245: CRSR_IMG Position  */
+#define LCD_CRSR_IMG245_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG245: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG246  ----------------------------------------
+#define LCD_CRSR_IMG246_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG246: CRSR_IMG Position  */
+#define LCD_CRSR_IMG246_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG246: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG247  ----------------------------------------
+#define LCD_CRSR_IMG247_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG247: CRSR_IMG Position  */
+#define LCD_CRSR_IMG247_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG247: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG248  ----------------------------------------
+#define LCD_CRSR_IMG248_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG248: CRSR_IMG Position  */
+#define LCD_CRSR_IMG248_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG248: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG249  ----------------------------------------
+#define LCD_CRSR_IMG249_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG249: CRSR_IMG Position  */
+#define LCD_CRSR_IMG249_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG249: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG250  ----------------------------------------
+#define LCD_CRSR_IMG250_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG250: CRSR_IMG Position  */
+#define LCD_CRSR_IMG250_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG250: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG251  ----------------------------------------
+#define LCD_CRSR_IMG251_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG251: CRSR_IMG Position  */
+#define LCD_CRSR_IMG251_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG251: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG252  ----------------------------------------
+#define LCD_CRSR_IMG252_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG252: CRSR_IMG Position  */
+#define LCD_CRSR_IMG252_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG252: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG253  ----------------------------------------
+#define LCD_CRSR_IMG253_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG253: CRSR_IMG Position  */
+#define LCD_CRSR_IMG253_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG253: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG254  ----------------------------------------
+#define LCD_CRSR_IMG254_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG254: CRSR_IMG Position  */
+#define LCD_CRSR_IMG254_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG254: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG255  ----------------------------------------
+#define LCD_CRSR_IMG255_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG255: CRSR_IMG Position  */
+#define LCD_CRSR_IMG255_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG255: CRSR_IMG Mask      */
+
+// --------------------------------------  LCD_CRSR_CTRL  -----------------------------------------
+#define LCD_CRSR_CTRL_CrsrOn_Pos                              0                                                         /*!< LCD CRSR_CTRL: CrsrOn Position      */
+#define LCD_CRSR_CTRL_CrsrOn_Msk                              (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos)                      /*!< LCD CRSR_CTRL: CrsrOn Mask          */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos                          4                                                         /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position  */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk                          (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos)                  /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask      */
+
+// --------------------------------------  LCD_CRSR_CFG  ------------------------------------------
+#define LCD_CRSR_CFG_CrsrSize_Pos                             0                                                         /*!< LCD CRSR_CFG: CrsrSize Position     */
+#define LCD_CRSR_CFG_CrsrSize_Msk                             (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos)                     /*!< LCD CRSR_CFG: CrsrSize Mask         */
+#define LCD_CRSR_CFG_FRAMESYNC_Pos                            1                                                         /*!< LCD CRSR_CFG: FRAMESYNC Position    */
+#define LCD_CRSR_CFG_FRAMESYNC_Msk                            (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos)                    /*!< LCD CRSR_CFG: FRAMESYNC Mask        */
+
+// --------------------------------------  LCD_CRSR_PAL0  -----------------------------------------
+#define LCD_CRSR_PAL0_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL0: RED Position         */
+#define LCD_CRSR_PAL0_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos)                   /*!< LCD CRSR_PAL0: RED Mask             */
+#define LCD_CRSR_PAL0_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL0: GREEN Position       */
+#define LCD_CRSR_PAL0_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos)                 /*!< LCD CRSR_PAL0: GREEN Mask           */
+#define LCD_CRSR_PAL0_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL0: BLUE Position        */
+#define LCD_CRSR_PAL0_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos)                  /*!< LCD CRSR_PAL0: BLUE Mask            */
+
+// --------------------------------------  LCD_CRSR_PAL1  -----------------------------------------
+#define LCD_CRSR_PAL1_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL1: RED Position         */
+#define LCD_CRSR_PAL1_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos)                   /*!< LCD CRSR_PAL1: RED Mask             */
+#define LCD_CRSR_PAL1_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL1: GREEN Position       */
+#define LCD_CRSR_PAL1_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos)                 /*!< LCD CRSR_PAL1: GREEN Mask           */
+#define LCD_CRSR_PAL1_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL1: BLUE Position        */
+#define LCD_CRSR_PAL1_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos)                  /*!< LCD CRSR_PAL1: BLUE Mask            */
+
+// ---------------------------------------  LCD_CRSR_XY  ------------------------------------------
+#define LCD_CRSR_XY_CRSRX_Pos                                 0                                                         /*!< LCD CRSR_XY: CRSRX Position         */
+#define LCD_CRSR_XY_CRSRX_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos)                   /*!< LCD CRSR_XY: CRSRX Mask             */
+#define LCD_CRSR_XY_CRSRY_Pos                                 16                                                        /*!< LCD CRSR_XY: CRSRY Position         */
+#define LCD_CRSR_XY_CRSRY_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos)                   /*!< LCD CRSR_XY: CRSRY Mask             */
+
+// --------------------------------------  LCD_CRSR_CLIP  -----------------------------------------
+#define LCD_CRSR_CLIP_CRSRCLIPX_Pos                           0                                                         /*!< LCD CRSR_CLIP: CRSRCLIPX Position   */
+#define LCD_CRSR_CLIP_CRSRCLIPX_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPX Mask       */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Pos                           8                                                         /*!< LCD CRSR_CLIP: CRSRCLIPY Position   */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPY Mask       */
+
+// -------------------------------------  LCD_CRSR_INTMSK  ----------------------------------------
+#define LCD_CRSR_INTMSK_CRSRIM_Pos                            0                                                         /*!< LCD CRSR_INTMSK: CRSRIM Position    */
+#define LCD_CRSR_INTMSK_CRSRIM_Msk                            (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos)                    /*!< LCD CRSR_INTMSK: CRSRIM Mask        */
+
+// -------------------------------------  LCD_CRSR_INTCLR  ----------------------------------------
+#define LCD_CRSR_INTCLR_CRSRIC_Pos                            0                                                         /*!< LCD CRSR_INTCLR: CRSRIC Position    */
+#define LCD_CRSR_INTCLR_CRSRIC_Msk                            (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos)                    /*!< LCD CRSR_INTCLR: CRSRIC Mask        */
+
+// -------------------------------------  LCD_CRSR_INTRAW  ----------------------------------------
+#define LCD_CRSR_INTRAW_CRSRRIS_Pos                           0                                                         /*!< LCD CRSR_INTRAW: CRSRRIS Position   */
+#define LCD_CRSR_INTRAW_CRSRRIS_Msk                           (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos)                   /*!< LCD CRSR_INTRAW: CRSRRIS Mask       */
+
+// ------------------------------------  LCD_CRSR_INTSTAT  ----------------------------------------
+#define LCD_CRSR_INTSTAT_CRSRMIS_Pos                          0                                                         /*!< LCD CRSR_INTSTAT: CRSRMIS Position  */
+#define LCD_CRSR_INTSTAT_CRSRMIS_Msk                          (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos)                  /*!< LCD CRSR_INTSTAT: CRSRMIS Mask      */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                               ETHERNET Position & Mask                               -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------  ETHERNET_MAC_CONFIG  --------------------------------------
+#define ETHERNET_MAC_CONFIG_RE_Pos                            2                                                         /*!< ETHERNET MAC_CONFIG: RE Position    */
+#define ETHERNET_MAC_CONFIG_RE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos)                    /*!< ETHERNET MAC_CONFIG: RE Mask        */
+#define ETHERNET_MAC_CONFIG_TE_Pos                            3                                                         /*!< ETHERNET MAC_CONFIG: TE Position    */
+#define ETHERNET_MAC_CONFIG_TE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos)                    /*!< ETHERNET MAC_CONFIG: TE Mask        */
+#define ETHERNET_MAC_CONFIG_DF_Pos                            4                                                         /*!< ETHERNET MAC_CONFIG: DF Position    */
+#define ETHERNET_MAC_CONFIG_DF_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos)                    /*!< ETHERNET MAC_CONFIG: DF Mask        */
+#define ETHERNET_MAC_CONFIG_BL_Pos                            5                                                         /*!< ETHERNET MAC_CONFIG: BL Position    */
+#define ETHERNET_MAC_CONFIG_BL_Msk                            (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos)                    /*!< ETHERNET MAC_CONFIG: BL Mask        */
+#define ETHERNET_MAC_CONFIG_ACS_Pos                           7                                                         /*!< ETHERNET MAC_CONFIG: ACS Position   */
+#define ETHERNET_MAC_CONFIG_ACS_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos)                   /*!< ETHERNET MAC_CONFIG: ACS Mask       */
+#define ETHERNET_MAC_CONFIG_DR_Pos                            9                                                         /*!< ETHERNET MAC_CONFIG: DR Position    */
+#define ETHERNET_MAC_CONFIG_DR_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos)                    /*!< ETHERNET MAC_CONFIG: DR Mask        */
+#define ETHERNET_MAC_CONFIG_IPC_Pos                           10                                                        /*!< ETHERNET MAC_CONFIG: IPC Position   */
+#define ETHERNET_MAC_CONFIG_IPC_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos)                   /*!< ETHERNET MAC_CONFIG: IPC Mask       */
+#define ETHERNET_MAC_CONFIG_DM_Pos                            11                                                        /*!< ETHERNET MAC_CONFIG: DM Position    */
+#define ETHERNET_MAC_CONFIG_DM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos)                    /*!< ETHERNET MAC_CONFIG: DM Mask        */
+#define ETHERNET_MAC_CONFIG_LM_Pos                            12                                                        /*!< ETHERNET MAC_CONFIG: LM Position    */
+#define ETHERNET_MAC_CONFIG_LM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos)                    /*!< ETHERNET MAC_CONFIG: LM Mask        */
+#define ETHERNET_MAC_CONFIG_DO_Pos                            13                                                        /*!< ETHERNET MAC_CONFIG: DO Position    */
+#define ETHERNET_MAC_CONFIG_DO_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos)                    /*!< ETHERNET MAC_CONFIG: DO Mask        */
+#define ETHERNET_MAC_CONFIG_FES_Pos                           14                                                        /*!< ETHERNET MAC_CONFIG: FES Position   */
+#define ETHERNET_MAC_CONFIG_FES_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos)                   /*!< ETHERNET MAC_CONFIG: FES Mask       */
+#define ETHERNET_MAC_CONFIG_PS_Pos                            15                                                        /*!< ETHERNET MAC_CONFIG: PS Position    */
+#define ETHERNET_MAC_CONFIG_PS_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos)                    /*!< ETHERNET MAC_CONFIG: PS Mask        */
+#define ETHERNET_MAC_CONFIG_DCRS_Pos                          16                                                        /*!< ETHERNET MAC_CONFIG: DCRS Position  */
+#define ETHERNET_MAC_CONFIG_DCRS_Msk                          (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos)                  /*!< ETHERNET MAC_CONFIG: DCRS Mask      */
+#define ETHERNET_MAC_CONFIG_IFG_Pos                           17                                                        /*!< ETHERNET MAC_CONFIG: IFG Position   */
+#define ETHERNET_MAC_CONFIG_IFG_Msk                           (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos)                   /*!< ETHERNET MAC_CONFIG: IFG Mask       */
+#define ETHERNET_MAC_CONFIG_JE_Pos                            20                                                        /*!< ETHERNET MAC_CONFIG: JE Position    */
+#define ETHERNET_MAC_CONFIG_JE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos)                    /*!< ETHERNET MAC_CONFIG: JE Mask        */
+#define ETHERNET_MAC_CONFIG_JD_Pos                            22                                                        /*!< ETHERNET MAC_CONFIG: JD Position    */
+#define ETHERNET_MAC_CONFIG_JD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos)                    /*!< ETHERNET MAC_CONFIG: JD Mask        */
+#define ETHERNET_MAC_CONFIG_WD_Pos                            23                                                        /*!< ETHERNET MAC_CONFIG: WD Position    */
+#define ETHERNET_MAC_CONFIG_WD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos)                    /*!< ETHERNET MAC_CONFIG: WD Mask        */
+
+// --------------------------------  ETHERNET_MAC_FRAME_FILTER  -----------------------------------
+#define ETHERNET_MAC_FRAME_FILTER_PR_Pos                      0                                                         /*!< ETHERNET MAC_FRAME_FILTER: PR Position */
+#define ETHERNET_MAC_FRAME_FILTER_PR_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PR Mask  */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos                    3                                                         /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Pos                      4                                                         /*!< ETHERNET MAC_FRAME_FILTER: PM Position */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PM Mask  */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos                     5                                                         /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos                     6                                                         /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk                     (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos                    8                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos                     9                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Pos                      31                                                        /*!< ETHERNET MAC_FRAME_FILTER: RA Position */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: RA Mask  */
+
+// -------------------------------  ETHERNET_MAC_HASHTABLE_HIGH  ----------------------------------
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos                   0                                                         /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk                   (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos)     /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */
+
+// -------------------------------  ETHERNET_MAC_HASHTABLE_LOW  -----------------------------------
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos                    0                                                         /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk                    (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos)      /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */
+
+// ----------------------------------  ETHERNET_MAC_MII_ADDR  -------------------------------------
+#define ETHERNET_MAC_MII_ADDR_GB_Pos                          0                                                         /*!< ETHERNET MAC_MII_ADDR: GB Position  */
+#define ETHERNET_MAC_MII_ADDR_GB_Msk                          (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GB Mask      */
+#define ETHERNET_MAC_MII_ADDR_W_Pos                           1                                                         /*!< ETHERNET MAC_MII_ADDR: W Position   */
+#define ETHERNET_MAC_MII_ADDR_W_Msk                           (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos)                   /*!< ETHERNET MAC_MII_ADDR: W Mask       */
+#define ETHERNET_MAC_MII_ADDR_CR_Pos                          2                                                         /*!< ETHERNET MAC_MII_ADDR: CR Position  */
+#define ETHERNET_MAC_MII_ADDR_CR_Msk                          (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: CR Mask      */
+#define ETHERNET_MAC_MII_ADDR_GR_Pos                          6                                                         /*!< ETHERNET MAC_MII_ADDR: GR Position  */
+#define ETHERNET_MAC_MII_ADDR_GR_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GR Mask      */
+#define ETHERNET_MAC_MII_ADDR_PA_Pos                          11                                                        /*!< ETHERNET MAC_MII_ADDR: PA Position  */
+#define ETHERNET_MAC_MII_ADDR_PA_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos)                  /*!< ETHERNET MAC_MII_ADDR: PA Mask      */
+
+// ----------------------------------  ETHERNET_MAC_MII_DATA  -------------------------------------
+#define ETHERNET_MAC_MII_DATA_GD_Pos                          0                                                         /*!< ETHERNET MAC_MII_DATA: GD Position  */
+#define ETHERNET_MAC_MII_DATA_GD_Msk                          (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos)            /*!< ETHERNET MAC_MII_DATA: GD Mask      */
+
+// ---------------------------------  ETHERNET_MAC_FLOW_CTRL  -------------------------------------
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos                        0                                                         /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos                        1                                                         /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos                        2                                                         /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Pos                         3                                                         /*!< ETHERNET MAC_FLOW_CTRL: UP Position */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Msk                         (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos)                 /*!< ETHERNET MAC_FLOW_CTRL: UP Mask     */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos                        4                                                         /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk                        (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos                       7                                                         /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk                       (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos)               /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask   */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Pos                         16                                                        /*!< ETHERNET MAC_FLOW_CTRL: PT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Msk                         (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos)           /*!< ETHERNET MAC_FLOW_CTRL: PT Mask     */
+
+// ----------------------------------  ETHERNET_MAC_VLAN_TAG  -------------------------------------
+#define ETHERNET_MAC_VLAN_TAG_VL_Pos                          0                                                         /*!< ETHERNET MAC_VLAN_TAG: VL Position  */
+#define ETHERNET_MAC_VLAN_TAG_VL_Msk                          (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos)            /*!< ETHERNET MAC_VLAN_TAG: VL Mask      */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Pos                         16                                                        /*!< ETHERNET MAC_VLAN_TAG: ETV Position */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Msk                         (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos)                 /*!< ETHERNET MAC_VLAN_TAG: ETV Mask     */
+
+// -----------------------------------  ETHERNET_MAC_DEBUG  ---------------------------------------
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos                     0                                                         /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos                      1                                                         /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos)              /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask  */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos                    4                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos                     5                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos                      8                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask  */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos                     16                                                        /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Pos                         17                                                        /*!< ETHERNET MAC_DEBUG: TXSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Msk                         (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos)                 /*!< ETHERNET MAC_DEBUG: TXSTAT Mask     */
+#define ETHERNET_MAC_DEBUG_PAUSE_Pos                          19                                                        /*!< ETHERNET MAC_DEBUG: PAUSE Position  */
+#define ETHERNET_MAC_DEBUG_PAUSE_Msk                          (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos)                  /*!< ETHERNET MAC_DEBUG: PAUSE Mask      */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos                     20                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos                    22                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos                      24                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk                      (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask  */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos                     25                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */
+
+// --------------------------------  ETHERNET_MAC_RWAKE_FRFLT  ------------------------------------
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos                     0                                                         /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk                     (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos)       /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */
+
+// -------------------------------  ETHERNET_MAC_PMT_CTRL_STAT  -----------------------------------
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos                     0                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos                    1                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos                    2                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos                    5                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos                    6                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos                     9                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos                 31                                                        /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk                 (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos)         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */
+
+// ---------------------------------  ETHERNET_MAC_INTR_MASK  -------------------------------------
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos                     3                                                         /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk                     (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos)             /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */
+
+// ---------------------------------  ETHERNET_MAC_ADDR0_HIGH  ------------------------------------
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos                    0                                                         /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk                    (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos)      /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos                        31                                                        /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk                        (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos)                /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask    */
+
+// ---------------------------------  ETHERNET_MAC_ADDR0_LOW  -------------------------------------
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos                      0                                                         /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk                      (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos)        /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask  */
+
+// --------------------------------  ETHERNET_MAC_TIMESTP_CTRL  -----------------------------------
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos                   0                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk                   (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos)           /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos                1                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos                  2                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos                  3                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos                  4                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos                5                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos                 8                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos               9                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos               10                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos                 11                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos               12                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos               13                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos               14                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos               15                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos               16                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk               (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos             18                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk             (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)     /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */
+
+// ---------------------------------  ETHERNET_SUBSECOND_INCR  ------------------------------------
+#define ETHERNET_SUBSECOND_INCR_SSINC_Pos                     0                                                         /*!< ETHERNET SUBSECOND_INCR: SSINC Position */
+#define ETHERNET_SUBSECOND_INCR_SSINC_Msk                     (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos)       /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */
+
+// ------------------------------------  ETHERNET_SECONDS  ----------------------------------------
+#define ETHERNET_SECONDS_TSS_Pos                              0                                                         /*!< ETHERNET SECONDS: TSS Position      */
+#define ETHERNET_SECONDS_TSS_Msk                              (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos)                /*!< ETHERNET SECONDS: TSS Mask          */
+
+// ----------------------------------  ETHERNET_NANOSECONDS  --------------------------------------
+#define ETHERNET_NANOSECONDS_TSSS_Pos                         0                                                         /*!< ETHERNET NANOSECONDS: TSSS Position */
+#define ETHERNET_NANOSECONDS_TSSS_Msk                         (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos)           /*!< ETHERNET NANOSECONDS: TSSS Mask     */
+#define ETHERNET_NANOSECONDS_PSNT_Pos                         31                                                        /*!< ETHERNET NANOSECONDS: PSNT Position */
+#define ETHERNET_NANOSECONDS_PSNT_Msk                         (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos)                 /*!< ETHERNET NANOSECONDS: PSNT Mask     */
+
+// ---------------------------------  ETHERNET_SECONDSUPDATE  -------------------------------------
+#define ETHERNET_SECONDSUPDATE_TSS_Pos                        0                                                         /*!< ETHERNET SECONDSUPDATE: TSS Position */
+#define ETHERNET_SECONDSUPDATE_TSS_Msk                        (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos)          /*!< ETHERNET SECONDSUPDATE: TSS Mask    */
+
+// -------------------------------  ETHERNET_NANOSECONDSUPDATE  -----------------------------------
+#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos                   0                                                         /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */
+#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk                   (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos)     /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */
+#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos                 31                                                        /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */
+#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk                 (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos)         /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */
+
+// -------------------------------------  ETHERNET_ADDEND  ----------------------------------------
+#define ETHERNET_ADDEND_TSAR_Pos                              0                                                         /*!< ETHERNET ADDEND: TSAR Position      */
+#define ETHERNET_ADDEND_TSAR_Msk                              (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos)                /*!< ETHERNET ADDEND: TSAR Mask          */
+
+// ---------------------------------  ETHERNET_TARGETSECONDS  -------------------------------------
+#define ETHERNET_TARGETSECONDS_TSTR_Pos                       0                                                         /*!< ETHERNET TARGETSECONDS: TSTR Position */
+#define ETHERNET_TARGETSECONDS_TSTR_Msk                       (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos)         /*!< ETHERNET TARGETSECONDS: TSTR Mask   */
+
+// -------------------------------  ETHERNET_TARGETNANOSECONDS  -----------------------------------
+#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos                   0                                                         /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */
+#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk                   (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos)     /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */
+
+// ------------------------------------  ETHERNET_HIGHWORD  ---------------------------------------
+#define ETHERNET_HIGHWORD_TSHWR_Pos                           0                                                         /*!< ETHERNET HIGHWORD: TSHWR Position   */
+#define ETHERNET_HIGHWORD_TSHWR_Msk                           (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos)             /*!< ETHERNET HIGHWORD: TSHWR Mask       */
+
+// ---------------------------------  ETHERNET_TIMESTAMPSTAT  -------------------------------------
+#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos                     0                                                         /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */
+#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos)             /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */
+#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos                    1                                                         /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */
+#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk                    (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos)            /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */
+#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos                      2                                                         /*!< ETHERNET TIMESTAMPSTAT: AUXSS Position */
+#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk                      (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: AUXSS Mask  */
+#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos                     24                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Position */
+#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos)             /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Mask */
+#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos                      25                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSNS Position */
+#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk                      (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: ATSNS Mask  */
+
+// ------------------------------------  ETHERNET_PPSCTRL  ----------------------------------------
+#define ETHERNET_PPSCTRL_PPSCTRL_Pos                          0                                                         /*!< ETHERNET PPSCTRL: PPSCTRL Position  */
+#define ETHERNET_PPSCTRL_PPSCTRL_Msk                          (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos)                  /*!< ETHERNET PPSCTRL: PPSCTRL Mask      */
+
+// ---------------------------------  ETHERNET_AUXNANOSECONDS  ------------------------------------
+#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos                     0                                                         /*!< ETHERNET AUXNANOSECONDS: AUXNS Position */
+#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk                     (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos)       /*!< ETHERNET AUXNANOSECONDS: AUXNS Mask */
+
+// -----------------------------------  ETHERNET_AUXSECONDS  --------------------------------------
+#define ETHERNET_AUXSECONDS_AUXS_Pos                          0                                                         /*!< ETHERNET AUXSECONDS: AUXS Position  */
+#define ETHERNET_AUXSECONDS_AUXS_Msk                          (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos)            /*!< ETHERNET AUXSECONDS: AUXS Mask      */
+
+// ----------------------------------  ETHERNET_DMA_BUS_MODE  -------------------------------------
+#define ETHERNET_DMA_BUS_MODE_SWR_Pos                         0                                                         /*!< ETHERNET DMA_BUS_MODE: SWR Position */
+#define ETHERNET_DMA_BUS_MODE_SWR_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos)                 /*!< ETHERNET DMA_BUS_MODE: SWR Mask     */
+#define ETHERNET_DMA_BUS_MODE_DA_Pos                          1                                                         /*!< ETHERNET DMA_BUS_MODE: DA Position  */
+#define ETHERNET_DMA_BUS_MODE_DA_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos)                  /*!< ETHERNET DMA_BUS_MODE: DA Mask      */
+#define ETHERNET_DMA_BUS_MODE_DSL_Pos                         2                                                         /*!< ETHERNET DMA_BUS_MODE: DSL Position */
+#define ETHERNET_DMA_BUS_MODE_DSL_Msk                         (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: DSL Mask     */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Pos                        7                                                         /*!< ETHERNET DMA_BUS_MODE: ATDS Position */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos)                /*!< ETHERNET DMA_BUS_MODE: ATDS Mask    */
+#define ETHERNET_DMA_BUS_MODE_PBL_Pos                         8                                                         /*!< ETHERNET DMA_BUS_MODE: PBL Position */
+#define ETHERNET_DMA_BUS_MODE_PBL_Msk                         (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: PBL Mask     */
+#define ETHERNET_DMA_BUS_MODE_PR_Pos                          14                                                        /*!< ETHERNET DMA_BUS_MODE: PR Position  */
+#define ETHERNET_DMA_BUS_MODE_PR_Msk                          (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos)                  /*!< ETHERNET DMA_BUS_MODE: PR Mask      */
+#define ETHERNET_DMA_BUS_MODE_FB_Pos                          16                                                        /*!< ETHERNET DMA_BUS_MODE: FB Position  */
+#define ETHERNET_DMA_BUS_MODE_FB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: FB Mask      */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Pos                        17                                                        /*!< ETHERNET DMA_BUS_MODE: RPBL Position */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Msk                        (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos)                /*!< ETHERNET DMA_BUS_MODE: RPBL Mask    */
+#define ETHERNET_DMA_BUS_MODE_USP_Pos                         23                                                        /*!< ETHERNET DMA_BUS_MODE: USP Position */
+#define ETHERNET_DMA_BUS_MODE_USP_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos)                 /*!< ETHERNET DMA_BUS_MODE: USP Mask     */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos                       24                                                        /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk                       (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos)               /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask   */
+#define ETHERNET_DMA_BUS_MODE_AAL_Pos                         25                                                        /*!< ETHERNET DMA_BUS_MODE: AAL Position */
+#define ETHERNET_DMA_BUS_MODE_AAL_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: AAL Mask     */
+#define ETHERNET_DMA_BUS_MODE_MB_Pos                          26                                                        /*!< ETHERNET DMA_BUS_MODE: MB Position  */
+#define ETHERNET_DMA_BUS_MODE_MB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: MB Mask      */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Pos                        27                                                        /*!< ETHERNET DMA_BUS_MODE: TXPR Position */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos)                /*!< ETHERNET DMA_BUS_MODE: TXPR Mask    */
+
+// -----------------------------  ETHERNET_DMA_TRANS_POLL_DEMAND  ---------------------------------
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos                0                                                         /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk                (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)  /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */
+
+// ------------------------------  ETHERNET_DMA_REC_POLL_DEMAND  ----------------------------------
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos                  0                                                         /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk                  (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos)    /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */
+
+// --------------------------------  ETHERNET_DMA_REC_DES_ADDR  -----------------------------------
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos                     0                                                         /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk                     (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos)       /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */
+
+// -------------------------------  ETHERNET_DMA_TRANS_DES_ADDR  ----------------------------------
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos                   0                                                         /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk                   (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos)     /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */
+
+// ------------------------------------  ETHERNET_DMA_STAT  ---------------------------------------
+#define ETHERNET_DMA_STAT_TI_Pos                              0                                                         /*!< ETHERNET DMA_STAT: TI Position      */
+#define ETHERNET_DMA_STAT_TI_Msk                              (0x01UL << ETHERNET_DMA_STAT_TI_Pos)                      /*!< ETHERNET DMA_STAT: TI Mask          */
+#define ETHERNET_DMA_STAT_TPS_Pos                             1                                                         /*!< ETHERNET DMA_STAT: TPS Position     */
+#define ETHERNET_DMA_STAT_TPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_TPS_Pos)                     /*!< ETHERNET DMA_STAT: TPS Mask         */
+#define ETHERNET_DMA_STAT_TU_Pos                              2                                                         /*!< ETHERNET DMA_STAT: TU Position      */
+#define ETHERNET_DMA_STAT_TU_Msk                              (0x01UL << ETHERNET_DMA_STAT_TU_Pos)                      /*!< ETHERNET DMA_STAT: TU Mask          */
+#define ETHERNET_DMA_STAT_TJT_Pos                             3                                                         /*!< ETHERNET DMA_STAT: TJT Position     */
+#define ETHERNET_DMA_STAT_TJT_Msk                             (0x01UL << ETHERNET_DMA_STAT_TJT_Pos)                     /*!< ETHERNET DMA_STAT: TJT Mask         */
+#define ETHERNET_DMA_STAT_OVF_Pos                             4                                                         /*!< ETHERNET DMA_STAT: OVF Position     */
+#define ETHERNET_DMA_STAT_OVF_Msk                             (0x01UL << ETHERNET_DMA_STAT_OVF_Pos)                     /*!< ETHERNET DMA_STAT: OVF Mask         */
+#define ETHERNET_DMA_STAT_UNF_Pos                             5                                                         /*!< ETHERNET DMA_STAT: UNF Position     */
+#define ETHERNET_DMA_STAT_UNF_Msk                             (0x01UL << ETHERNET_DMA_STAT_UNF_Pos)                     /*!< ETHERNET DMA_STAT: UNF Mask         */
+#define ETHERNET_DMA_STAT_RI_Pos                              6                                                         /*!< ETHERNET DMA_STAT: RI Position      */
+#define ETHERNET_DMA_STAT_RI_Msk                              (0x01UL << ETHERNET_DMA_STAT_RI_Pos)                      /*!< ETHERNET DMA_STAT: RI Mask          */
+#define ETHERNET_DMA_STAT_RU_Pos                              7                                                         /*!< ETHERNET DMA_STAT: RU Position      */
+#define ETHERNET_DMA_STAT_RU_Msk                              (0x01UL << ETHERNET_DMA_STAT_RU_Pos)                      /*!< ETHERNET DMA_STAT: RU Mask          */
+#define ETHERNET_DMA_STAT_RPS_Pos                             8                                                         /*!< ETHERNET DMA_STAT: RPS Position     */
+#define ETHERNET_DMA_STAT_RPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_RPS_Pos)                     /*!< ETHERNET DMA_STAT: RPS Mask         */
+#define ETHERNET_DMA_STAT_RWT_Pos                             9                                                         /*!< ETHERNET DMA_STAT: RWT Position     */
+#define ETHERNET_DMA_STAT_RWT_Msk                             (0x01UL << ETHERNET_DMA_STAT_RWT_Pos)                     /*!< ETHERNET DMA_STAT: RWT Mask         */
+#define ETHERNET_DMA_STAT_ETI_Pos                             10                                                        /*!< ETHERNET DMA_STAT: ETI Position     */
+#define ETHERNET_DMA_STAT_ETI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ETI_Pos)                     /*!< ETHERNET DMA_STAT: ETI Mask         */
+#define ETHERNET_DMA_STAT_FBI_Pos                             13                                                        /*!< ETHERNET DMA_STAT: FBI Position     */
+#define ETHERNET_DMA_STAT_FBI_Msk                             (0x01UL << ETHERNET_DMA_STAT_FBI_Pos)                     /*!< ETHERNET DMA_STAT: FBI Mask         */
+#define ETHERNET_DMA_STAT_ERI_Pos                             14                                                        /*!< ETHERNET DMA_STAT: ERI Position     */
+#define ETHERNET_DMA_STAT_ERI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ERI_Pos)                     /*!< ETHERNET DMA_STAT: ERI Mask         */
+#define ETHERNET_DMA_STAT_AIE_Pos                             15                                                        /*!< ETHERNET DMA_STAT: AIE Position     */
+#define ETHERNET_DMA_STAT_AIE_Msk                             (0x01UL << ETHERNET_DMA_STAT_AIE_Pos)                     /*!< ETHERNET DMA_STAT: AIE Mask         */
+#define ETHERNET_DMA_STAT_NIS_Pos                             16                                                        /*!< ETHERNET DMA_STAT: NIS Position     */
+#define ETHERNET_DMA_STAT_NIS_Msk                             (0x01UL << ETHERNET_DMA_STAT_NIS_Pos)                     /*!< ETHERNET DMA_STAT: NIS Mask         */
+
+// ----------------------------------  ETHERNET_DMA_OP_MODE  --------------------------------------
+#define ETHERNET_DMA_OP_MODE_SR_Pos                           1                                                         /*!< ETHERNET DMA_OP_MODE: SR Position   */
+#define ETHERNET_DMA_OP_MODE_SR_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos)                   /*!< ETHERNET DMA_OP_MODE: SR Mask       */
+#define ETHERNET_DMA_OP_MODE_OSF_Pos                          2                                                         /*!< ETHERNET DMA_OP_MODE: OSF Position  */
+#define ETHERNET_DMA_OP_MODE_OSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: OSF Mask      */
+#define ETHERNET_DMA_OP_MODE_RTC_Pos                          3                                                         /*!< ETHERNET DMA_OP_MODE: RTC Position  */
+#define ETHERNET_DMA_OP_MODE_RTC_Msk                          (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: RTC Mask      */
+#define ETHERNET_DMA_OP_MODE_FUF_Pos                          6                                                         /*!< ETHERNET DMA_OP_MODE: FUF Position  */
+#define ETHERNET_DMA_OP_MODE_FUF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FUF Mask      */
+#define ETHERNET_DMA_OP_MODE_FEF_Pos                          7                                                         /*!< ETHERNET DMA_OP_MODE: FEF Position  */
+#define ETHERNET_DMA_OP_MODE_FEF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FEF Mask      */
+#define ETHERNET_DMA_OP_MODE_ST_Pos                           13                                                        /*!< ETHERNET DMA_OP_MODE: ST Position   */
+#define ETHERNET_DMA_OP_MODE_ST_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos)                   /*!< ETHERNET DMA_OP_MODE: ST Mask       */
+#define ETHERNET_DMA_OP_MODE_TTC_Pos                          14                                                        /*!< ETHERNET DMA_OP_MODE: TTC Position  */
+#define ETHERNET_DMA_OP_MODE_TTC_Msk                          (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: TTC Mask      */
+#define ETHERNET_DMA_OP_MODE_FTF_Pos                          20                                                        /*!< ETHERNET DMA_OP_MODE: FTF Position  */
+#define ETHERNET_DMA_OP_MODE_FTF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FTF Mask      */
+#define ETHERNET_DMA_OP_MODE_TSF_Pos                          21                                                        /*!< ETHERNET DMA_OP_MODE: TSF Position  */
+#define ETHERNET_DMA_OP_MODE_TSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: TSF Mask      */
+#define ETHERNET_DMA_OP_MODE_DFF_Pos                          24                                                        /*!< ETHERNET DMA_OP_MODE: DFF Position  */
+#define ETHERNET_DMA_OP_MODE_DFF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos)                  /*!< ETHERNET DMA_OP_MODE: DFF Mask      */
+#define ETHERNET_DMA_OP_MODE_RSF_Pos                          25                                                        /*!< ETHERNET DMA_OP_MODE: RSF Position  */
+#define ETHERNET_DMA_OP_MODE_RSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: RSF Mask      */
+#define ETHERNET_DMA_OP_MODE_DT_Pos                           26                                                        /*!< ETHERNET DMA_OP_MODE: DT Position   */
+#define ETHERNET_DMA_OP_MODE_DT_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos)                   /*!< ETHERNET DMA_OP_MODE: DT Mask       */
+
+// -----------------------------------  ETHERNET_DMA_INT_EN  --------------------------------------
+#define ETHERNET_DMA_INT_EN_TIE_Pos                           0                                                         /*!< ETHERNET DMA_INT_EN: TIE Position   */
+#define ETHERNET_DMA_INT_EN_TIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos)                   /*!< ETHERNET DMA_INT_EN: TIE Mask       */
+#define ETHERNET_DMA_INT_EN_TSE_Pos                           1                                                         /*!< ETHERNET DMA_INT_EN: TSE Position   */
+#define ETHERNET_DMA_INT_EN_TSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos)                   /*!< ETHERNET DMA_INT_EN: TSE Mask       */
+#define ETHERNET_DMA_INT_EN_TUE_Pos                           2                                                         /*!< ETHERNET DMA_INT_EN: TUE Position   */
+#define ETHERNET_DMA_INT_EN_TUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos)                   /*!< ETHERNET DMA_INT_EN: TUE Mask       */
+#define ETHERNET_DMA_INT_EN_TJE_Pos                           3                                                         /*!< ETHERNET DMA_INT_EN: TJE Position   */
+#define ETHERNET_DMA_INT_EN_TJE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos)                   /*!< ETHERNET DMA_INT_EN: TJE Mask       */
+#define ETHERNET_DMA_INT_EN_OVE_Pos                           4                                                         /*!< ETHERNET DMA_INT_EN: OVE Position   */
+#define ETHERNET_DMA_INT_EN_OVE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos)                   /*!< ETHERNET DMA_INT_EN: OVE Mask       */
+#define ETHERNET_DMA_INT_EN_UNE_Pos                           5                                                         /*!< ETHERNET DMA_INT_EN: UNE Position   */
+#define ETHERNET_DMA_INT_EN_UNE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos)                   /*!< ETHERNET DMA_INT_EN: UNE Mask       */
+#define ETHERNET_DMA_INT_EN_RIE_Pos                           6                                                         /*!< ETHERNET DMA_INT_EN: RIE Position   */
+#define ETHERNET_DMA_INT_EN_RIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos)                   /*!< ETHERNET DMA_INT_EN: RIE Mask       */
+#define ETHERNET_DMA_INT_EN_RUE_Pos                           7                                                         /*!< ETHERNET DMA_INT_EN: RUE Position   */
+#define ETHERNET_DMA_INT_EN_RUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos)                   /*!< ETHERNET DMA_INT_EN: RUE Mask       */
+#define ETHERNET_DMA_INT_EN_RSE_Pos                           8                                                         /*!< ETHERNET DMA_INT_EN: RSE Position   */
+#define ETHERNET_DMA_INT_EN_RSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos)                   /*!< ETHERNET DMA_INT_EN: RSE Mask       */
+#define ETHERNET_DMA_INT_EN_RWE_Pos                           9                                                         /*!< ETHERNET DMA_INT_EN: RWE Position   */
+#define ETHERNET_DMA_INT_EN_RWE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos)                   /*!< ETHERNET DMA_INT_EN: RWE Mask       */
+#define ETHERNET_DMA_INT_EN_ETE_Pos                           10                                                        /*!< ETHERNET DMA_INT_EN: ETE Position   */
+#define ETHERNET_DMA_INT_EN_ETE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos)                   /*!< ETHERNET DMA_INT_EN: ETE Mask       */
+#define ETHERNET_DMA_INT_EN_FBE_Pos                           13                                                        /*!< ETHERNET DMA_INT_EN: FBE Position   */
+#define ETHERNET_DMA_INT_EN_FBE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos)                   /*!< ETHERNET DMA_INT_EN: FBE Mask       */
+#define ETHERNET_DMA_INT_EN_ERE_Pos                           14                                                        /*!< ETHERNET DMA_INT_EN: ERE Position   */
+#define ETHERNET_DMA_INT_EN_ERE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos)                   /*!< ETHERNET DMA_INT_EN: ERE Mask       */
+#define ETHERNET_DMA_INT_EN_AIE_Pos                           15                                                        /*!< ETHERNET DMA_INT_EN: AIE Position   */
+#define ETHERNET_DMA_INT_EN_AIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos)                   /*!< ETHERNET DMA_INT_EN: AIE Mask       */
+#define ETHERNET_DMA_INT_EN_NIE_Pos                           16                                                        /*!< ETHERNET DMA_INT_EN: NIE Position   */
+#define ETHERNET_DMA_INT_EN_NIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos)                   /*!< ETHERNET DMA_INT_EN: NIE Mask       */
+
+// ---------------------------------  ETHERNET_DMA_MFRM_BUFOF  ------------------------------------
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos                       0                                                         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk                       (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask   */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos                        16                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask    */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos                       17                                                        /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk                       (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask   */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos                        28                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask    */
+
+// --------------------------------  ETHERNET_DMA_REC_INT_WDT  ------------------------------------
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos                     0                                                         /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk                     (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos)       /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */
+
+// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_DES  ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */
+
+// ------------------------------  ETHERNET_DMA_CURHOST_REC_DES  ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos)    /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */
+
+// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_BUF  ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */
+
+// ------------------------------  ETHERNET_DMA_CURHOST_REC_BUF  ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos)    /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                ATIMER Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------  ATIMER_DOWNCOUNTER  ---------------------------------------
+#define ATIMER_DOWNCOUNTER_CVAL_Pos                           0                                                         /*!< ATIMER DOWNCOUNTER: CVAL Position   */
+#define ATIMER_DOWNCOUNTER_CVAL_Msk                           (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos)             /*!< ATIMER DOWNCOUNTER: CVAL Mask       */
+
+// --------------------------------------  ATIMER_PRESET  -----------------------------------------
+#define ATIMER_PRESET_PRESETVAL_Pos                           0                                                         /*!< ATIMER PRESET: PRESETVAL Position   */
+#define ATIMER_PRESET_PRESETVAL_Msk                           (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos)             /*!< ATIMER PRESET: PRESETVAL Mask       */
+
+// --------------------------------------  ATIMER_CLR_EN  -----------------------------------------
+#define ATIMER_CLR_EN_CLR_EN_Pos                              0                                                         /*!< ATIMER CLR_EN: CLR_EN Position      */
+#define ATIMER_CLR_EN_CLR_EN_Msk                              (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos)                      /*!< ATIMER CLR_EN: CLR_EN Mask          */
+
+// --------------------------------------  ATIMER_SET_EN  -----------------------------------------
+#define ATIMER_SET_EN_SET_EN_Pos                              0                                                         /*!< ATIMER SET_EN: SET_EN Position      */
+#define ATIMER_SET_EN_SET_EN_Msk                              (0x01UL << ATIMER_SET_EN_SET_EN_Pos)                      /*!< ATIMER SET_EN: SET_EN Mask          */
+
+// --------------------------------------  ATIMER_STATUS  -----------------------------------------
+#define ATIMER_STATUS_STAT_Pos                                0                                                         /*!< ATIMER STATUS: STAT Position        */
+#define ATIMER_STATUS_STAT_Msk                                (0x01UL << ATIMER_STATUS_STAT_Pos)                        /*!< ATIMER STATUS: STAT Mask            */
+
+// --------------------------------------  ATIMER_ENABLE  -----------------------------------------
+#define ATIMER_ENABLE_EN_Pos                                  0                                                         /*!< ATIMER ENABLE: EN Position          */
+#define ATIMER_ENABLE_EN_Msk                                  (0x01UL << ATIMER_ENABLE_EN_Pos)                          /*!< ATIMER ENABLE: EN Mask              */
+
+// -------------------------------------  ATIMER_CLR_STAT  ----------------------------------------
+#define ATIMER_CLR_STAT_CSTAT_Pos                             0                                                         /*!< ATIMER CLR_STAT: CSTAT Position     */
+#define ATIMER_CLR_STAT_CSTAT_Msk                             (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos)                     /*!< ATIMER CLR_STAT: CSTAT Mask         */
+
+// -------------------------------------  ATIMER_SET_STAT  ----------------------------------------
+#define ATIMER_SET_STAT_SSTAT_Pos                             0                                                         /*!< ATIMER SET_STAT: SSTAT Position     */
+#define ATIMER_SET_STAT_SSTAT_Msk                             (0x01UL << ATIMER_SET_STAT_SSTAT_Pos)                     /*!< ATIMER SET_STAT: SSTAT Mask         */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                REGFILE Position & Mask                               -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------  REGFILE_REGFILE0  ----------------------------------------
+#define REGFILE_REGFILE0_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE0: REGVAL Position   */
+#define REGFILE_REGFILE0_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos)             /*!< REGFILE REGFILE0: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE1  ----------------------------------------
+#define REGFILE_REGFILE1_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE1: REGVAL Position   */
+#define REGFILE_REGFILE1_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos)             /*!< REGFILE REGFILE1: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE2  ----------------------------------------
+#define REGFILE_REGFILE2_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE2: REGVAL Position   */
+#define REGFILE_REGFILE2_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos)             /*!< REGFILE REGFILE2: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE3  ----------------------------------------
+#define REGFILE_REGFILE3_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE3: REGVAL Position   */
+#define REGFILE_REGFILE3_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos)             /*!< REGFILE REGFILE3: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE4  ----------------------------------------
+#define REGFILE_REGFILE4_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE4: REGVAL Position   */
+#define REGFILE_REGFILE4_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos)             /*!< REGFILE REGFILE4: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE5  ----------------------------------------
+#define REGFILE_REGFILE5_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE5: REGVAL Position   */
+#define REGFILE_REGFILE5_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos)             /*!< REGFILE REGFILE5: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE6  ----------------------------------------
+#define REGFILE_REGFILE6_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE6: REGVAL Position   */
+#define REGFILE_REGFILE6_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos)             /*!< REGFILE REGFILE6: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE7  ----------------------------------------
+#define REGFILE_REGFILE7_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE7: REGVAL Position   */
+#define REGFILE_REGFILE7_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos)             /*!< REGFILE REGFILE7: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE8  ----------------------------------------
+#define REGFILE_REGFILE8_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE8: REGVAL Position   */
+#define REGFILE_REGFILE8_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos)             /*!< REGFILE REGFILE8: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE9  ----------------------------------------
+#define REGFILE_REGFILE9_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE9: REGVAL Position   */
+#define REGFILE_REGFILE9_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos)             /*!< REGFILE REGFILE9: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE10  ---------------------------------------
+#define REGFILE_REGFILE10_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE10: REGVAL Position  */
+#define REGFILE_REGFILE10_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos)            /*!< REGFILE REGFILE10: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE11  ---------------------------------------
+#define REGFILE_REGFILE11_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE11: REGVAL Position  */
+#define REGFILE_REGFILE11_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos)            /*!< REGFILE REGFILE11: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE12  ---------------------------------------
+#define REGFILE_REGFILE12_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE12: REGVAL Position  */
+#define REGFILE_REGFILE12_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos)            /*!< REGFILE REGFILE12: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE13  ---------------------------------------
+#define REGFILE_REGFILE13_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE13: REGVAL Position  */
+#define REGFILE_REGFILE13_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos)            /*!< REGFILE REGFILE13: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE14  ---------------------------------------
+#define REGFILE_REGFILE14_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE14: REGVAL Position  */
+#define REGFILE_REGFILE14_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos)            /*!< REGFILE REGFILE14: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE15  ---------------------------------------
+#define REGFILE_REGFILE15_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE15: REGVAL Position  */
+#define REGFILE_REGFILE15_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos)            /*!< REGFILE REGFILE15: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE16  ---------------------------------------
+#define REGFILE_REGFILE16_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE16: REGVAL Position  */
+#define REGFILE_REGFILE16_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos)            /*!< REGFILE REGFILE16: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE17  ---------------------------------------
+#define REGFILE_REGFILE17_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE17: REGVAL Position  */
+#define REGFILE_REGFILE17_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos)            /*!< REGFILE REGFILE17: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE18  ---------------------------------------
+#define REGFILE_REGFILE18_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE18: REGVAL Position  */
+#define REGFILE_REGFILE18_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos)            /*!< REGFILE REGFILE18: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE19  ---------------------------------------
+#define REGFILE_REGFILE19_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE19: REGVAL Position  */
+#define REGFILE_REGFILE19_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos)            /*!< REGFILE REGFILE19: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE20  ---------------------------------------
+#define REGFILE_REGFILE20_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE20: REGVAL Position  */
+#define REGFILE_REGFILE20_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos)            /*!< REGFILE REGFILE20: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE21  ---------------------------------------
+#define REGFILE_REGFILE21_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE21: REGVAL Position  */
+#define REGFILE_REGFILE21_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos)            /*!< REGFILE REGFILE21: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE22  ---------------------------------------
+#define REGFILE_REGFILE22_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE22: REGVAL Position  */
+#define REGFILE_REGFILE22_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos)            /*!< REGFILE REGFILE22: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE23  ---------------------------------------
+#define REGFILE_REGFILE23_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE23: REGVAL Position  */
+#define REGFILE_REGFILE23_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos)            /*!< REGFILE REGFILE23: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE24  ---------------------------------------
+#define REGFILE_REGFILE24_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE24: REGVAL Position  */
+#define REGFILE_REGFILE24_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos)            /*!< REGFILE REGFILE24: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE25  ---------------------------------------
+#define REGFILE_REGFILE25_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE25: REGVAL Position  */
+#define REGFILE_REGFILE25_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos)            /*!< REGFILE REGFILE25: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE26  ---------------------------------------
+#define REGFILE_REGFILE26_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE26: REGVAL Position  */
+#define REGFILE_REGFILE26_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos)            /*!< REGFILE REGFILE26: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE27  ---------------------------------------
+#define REGFILE_REGFILE27_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE27: REGVAL Position  */
+#define REGFILE_REGFILE27_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos)            /*!< REGFILE REGFILE27: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE28  ---------------------------------------
+#define REGFILE_REGFILE28_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE28: REGVAL Position  */
+#define REGFILE_REGFILE28_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos)            /*!< REGFILE REGFILE28: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE29  ---------------------------------------
+#define REGFILE_REGFILE29_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE29: REGVAL Position  */
+#define REGFILE_REGFILE29_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos)            /*!< REGFILE REGFILE29: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE30  ---------------------------------------
+#define REGFILE_REGFILE30_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE30: REGVAL Position  */
+#define REGFILE_REGFILE30_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos)            /*!< REGFILE REGFILE30: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE31  ---------------------------------------
+#define REGFILE_REGFILE31_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE31: REGVAL Position  */
+#define REGFILE_REGFILE31_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos)            /*!< REGFILE REGFILE31: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE32  ---------------------------------------
+#define REGFILE_REGFILE32_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE32: REGVAL Position  */
+#define REGFILE_REGFILE32_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos)            /*!< REGFILE REGFILE32: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE33  ---------------------------------------
+#define REGFILE_REGFILE33_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE33: REGVAL Position  */
+#define REGFILE_REGFILE33_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos)            /*!< REGFILE REGFILE33: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE34  ---------------------------------------
+#define REGFILE_REGFILE34_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE34: REGVAL Position  */
+#define REGFILE_REGFILE34_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos)            /*!< REGFILE REGFILE34: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE35  ---------------------------------------
+#define REGFILE_REGFILE35_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE35: REGVAL Position  */
+#define REGFILE_REGFILE35_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos)            /*!< REGFILE REGFILE35: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE36  ---------------------------------------
+#define REGFILE_REGFILE36_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE36: REGVAL Position  */
+#define REGFILE_REGFILE36_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos)            /*!< REGFILE REGFILE36: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE37  ---------------------------------------
+#define REGFILE_REGFILE37_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE37: REGVAL Position  */
+#define REGFILE_REGFILE37_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos)            /*!< REGFILE REGFILE37: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE38  ---------------------------------------
+#define REGFILE_REGFILE38_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE38: REGVAL Position  */
+#define REGFILE_REGFILE38_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos)            /*!< REGFILE REGFILE38: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE39  ---------------------------------------
+#define REGFILE_REGFILE39_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE39: REGVAL Position  */
+#define REGFILE_REGFILE39_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos)            /*!< REGFILE REGFILE39: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE40  ---------------------------------------
+#define REGFILE_REGFILE40_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE40: REGVAL Position  */
+#define REGFILE_REGFILE40_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos)            /*!< REGFILE REGFILE40: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE41  ---------------------------------------
+#define REGFILE_REGFILE41_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE41: REGVAL Position  */
+#define REGFILE_REGFILE41_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos)            /*!< REGFILE REGFILE41: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE42  ---------------------------------------
+#define REGFILE_REGFILE42_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE42: REGVAL Position  */
+#define REGFILE_REGFILE42_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos)            /*!< REGFILE REGFILE42: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE43  ---------------------------------------
+#define REGFILE_REGFILE43_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE43: REGVAL Position  */
+#define REGFILE_REGFILE43_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos)            /*!< REGFILE REGFILE43: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE44  ---------------------------------------
+#define REGFILE_REGFILE44_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE44: REGVAL Position  */
+#define REGFILE_REGFILE44_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos)            /*!< REGFILE REGFILE44: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE45  ---------------------------------------
+#define REGFILE_REGFILE45_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE45: REGVAL Position  */
+#define REGFILE_REGFILE45_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos)            /*!< REGFILE REGFILE45: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE46  ---------------------------------------
+#define REGFILE_REGFILE46_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE46: REGVAL Position  */
+#define REGFILE_REGFILE46_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos)            /*!< REGFILE REGFILE46: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE47  ---------------------------------------
+#define REGFILE_REGFILE47_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE47: REGVAL Position  */
+#define REGFILE_REGFILE47_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos)            /*!< REGFILE REGFILE47: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE48  ---------------------------------------
+#define REGFILE_REGFILE48_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE48: REGVAL Position  */
+#define REGFILE_REGFILE48_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos)            /*!< REGFILE REGFILE48: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE49  ---------------------------------------
+#define REGFILE_REGFILE49_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE49: REGVAL Position  */
+#define REGFILE_REGFILE49_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos)            /*!< REGFILE REGFILE49: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE50  ---------------------------------------
+#define REGFILE_REGFILE50_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE50: REGVAL Position  */
+#define REGFILE_REGFILE50_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos)            /*!< REGFILE REGFILE50: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE51  ---------------------------------------
+#define REGFILE_REGFILE51_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE51: REGVAL Position  */
+#define REGFILE_REGFILE51_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos)            /*!< REGFILE REGFILE51: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE52  ---------------------------------------
+#define REGFILE_REGFILE52_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE52: REGVAL Position  */
+#define REGFILE_REGFILE52_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos)            /*!< REGFILE REGFILE52: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE53  ---------------------------------------
+#define REGFILE_REGFILE53_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE53: REGVAL Position  */
+#define REGFILE_REGFILE53_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos)            /*!< REGFILE REGFILE53: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE54  ---------------------------------------
+#define REGFILE_REGFILE54_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE54: REGVAL Position  */
+#define REGFILE_REGFILE54_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos)            /*!< REGFILE REGFILE54: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE55  ---------------------------------------
+#define REGFILE_REGFILE55_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE55: REGVAL Position  */
+#define REGFILE_REGFILE55_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos)            /*!< REGFILE REGFILE55: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE56  ---------------------------------------
+#define REGFILE_REGFILE56_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE56: REGVAL Position  */
+#define REGFILE_REGFILE56_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos)            /*!< REGFILE REGFILE56: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE57  ---------------------------------------
+#define REGFILE_REGFILE57_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE57: REGVAL Position  */
+#define REGFILE_REGFILE57_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos)            /*!< REGFILE REGFILE57: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE58  ---------------------------------------
+#define REGFILE_REGFILE58_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE58: REGVAL Position  */
+#define REGFILE_REGFILE58_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos)            /*!< REGFILE REGFILE58: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE59  ---------------------------------------
+#define REGFILE_REGFILE59_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE59: REGVAL Position  */
+#define REGFILE_REGFILE59_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos)            /*!< REGFILE REGFILE59: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE60  ---------------------------------------
+#define REGFILE_REGFILE60_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE60: REGVAL Position  */
+#define REGFILE_REGFILE60_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos)            /*!< REGFILE REGFILE60: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE61  ---------------------------------------
+#define REGFILE_REGFILE61_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE61: REGVAL Position  */
+#define REGFILE_REGFILE61_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos)            /*!< REGFILE REGFILE61: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE62  ---------------------------------------
+#define REGFILE_REGFILE62_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE62: REGVAL Position  */
+#define REGFILE_REGFILE62_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos)            /*!< REGFILE REGFILE62: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE63  ---------------------------------------
+#define REGFILE_REGFILE63_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE63: REGVAL Position  */
+#define REGFILE_REGFILE63_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos)            /*!< REGFILE REGFILE63: REGVAL Mask      */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  PMC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------  PMC_PD0_SLEEP0_HW_ENA  -------------------------------------
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos                  0                                                         /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk                  (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos)          /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */
+
+// -----------------------------------  PMC_PD0_SLEEP0_MODE  --------------------------------------
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos                     0                                                         /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk                     (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos)       /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 CREG Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  CREG_IRCTRM  ------------------------------------------
+#define CREG_IRCTRM_TRM_Pos                                   0                                                         /*!< CREG IRCTRM: TRM Position           */
+#define CREG_IRCTRM_TRM_Msk                                   (0x00000fffUL << CREG_IRCTRM_TRM_Pos)                     /*!< CREG IRCTRM: TRM Mask               */
+
+// ---------------------------------------  CREG_CREG0  -------------------------------------------
+#define CREG_CREG0_EN1KHZ_Pos                                 0                                                         /*!< CREG CREG0: EN1KHZ Position         */
+#define CREG_CREG0_EN1KHZ_Msk                                 (0x01UL << CREG_CREG0_EN1KHZ_Pos)                         /*!< CREG CREG0: EN1KHZ Mask             */
+#define CREG_CREG0_EN32KHZ_Pos                                1                                                         /*!< CREG CREG0: EN32KHZ Position        */
+#define CREG_CREG0_EN32KHZ_Msk                                (0x01UL << CREG_CREG0_EN32KHZ_Pos)                        /*!< CREG CREG0: EN32KHZ Mask            */
+#define CREG_CREG0_RESET32KHZ_Pos                             2                                                         /*!< CREG CREG0: RESET32KHZ Position     */
+#define CREG_CREG0_RESET32KHZ_Msk                             (0x01UL << CREG_CREG0_RESET32KHZ_Pos)                     /*!< CREG CREG0: RESET32KHZ Mask         */
+#define CREG_CREG0_32KHZPD_Pos                                3                                                         /*!< CREG CREG0: 32KHZPD Position        */
+#define CREG_CREG0_32KHZPD_Msk                                (0x01UL << CREG_CREG0_32KHZPD_Pos)                        /*!< CREG CREG0: 32KHZPD Mask            */
+#define CREG_CREG0_USB0PHY_Pos                                5                                                         /*!< CREG CREG0: USB0PHY Position        */
+#define CREG_CREG0_USB0PHY_Msk                                (0x01UL << CREG_CREG0_USB0PHY_Pos)                        /*!< CREG CREG0: USB0PHY Mask            */
+#define CREG_CREG0_ALARMCTRL_Pos                              6                                                         /*!< CREG CREG0: ALARMCTRL Position      */
+#define CREG_CREG0_ALARMCTRL_Msk                              (0x03UL << CREG_CREG0_ALARMCTRL_Pos)                      /*!< CREG CREG0: ALARMCTRL Mask          */
+#define CREG_CREG0_BODLVL1_Pos                                8                                                         /*!< CREG CREG0: BODLVL1 Position        */
+#define CREG_CREG0_BODLVL1_Msk                                (0x03UL << CREG_CREG0_BODLVL1_Pos)                        /*!< CREG CREG0: BODLVL1 Mask            */
+#define CREG_CREG0_BODLVL2_Pos                                10                                                        /*!< CREG CREG0: BODLVL2 Position        */
+#define CREG_CREG0_BODLVL2_Msk                                (0x03UL << CREG_CREG0_BODLVL2_Pos)                        /*!< CREG CREG0: BODLVL2 Mask            */
+#define CREG_CREG0_WAKEUP0CTRL_Pos                            14                                                        /*!< CREG CREG0: WAKEUP0CTRL Position    */
+#define CREG_CREG0_WAKEUP0CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos)                    /*!< CREG CREG0: WAKEUP0CTRL Mask        */
+#define CREG_CREG0_WAKEUP1CTRL_Pos                            16                                                        /*!< CREG CREG0: WAKEUP1CTRL Position    */
+#define CREG_CREG0_WAKEUP1CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos)                    /*!< CREG CREG0: WAKEUP1CTRL Mask        */
+
+// --------------------------------------  CREG_M4MEMMAP  -----------------------------------------
+#define CREG_M4MEMMAP_M4MAP_Pos                               12                                                        /*!< CREG M4MEMMAP: M4MAP Position       */
+#define CREG_M4MEMMAP_M4MAP_Msk                               (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos)                 /*!< CREG M4MEMMAP: M4MAP Mask           */
+
+// ---------------------------------------  CREG_CREG5  -------------------------------------------
+#define CREG_CREG5_M4TAPSEL_Pos                               6                                                         /*!< CREG CREG5: M4TAPSEL Position       */
+#define CREG_CREG5_M4TAPSEL_Msk                               (0x01UL << CREG_CREG5_M4TAPSEL_Pos)                       /*!< CREG CREG5: M4TAPSEL Mask           */
+
+// ---------------------------------------  CREG_DMAMUX  ------------------------------------------
+#define CREG_DMAMUX_DMAMUXCH0_Pos                             0                                                         /*!< CREG DMAMUX: DMAMUXCH0 Position     */
+#define CREG_DMAMUX_DMAMUXCH0_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos)                     /*!< CREG DMAMUX: DMAMUXCH0 Mask         */
+#define CREG_DMAMUX_DMAMUXCH1_Pos                             2                                                         /*!< CREG DMAMUX: DMAMUXCH1 Position     */
+#define CREG_DMAMUX_DMAMUXCH1_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos)                     /*!< CREG DMAMUX: DMAMUXCH1 Mask         */
+#define CREG_DMAMUX_DMAMUXCH2_Pos                             4                                                         /*!< CREG DMAMUX: DMAMUXCH2 Position     */
+#define CREG_DMAMUX_DMAMUXCH2_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos)                     /*!< CREG DMAMUX: DMAMUXCH2 Mask         */
+#define CREG_DMAMUX_DMAMUXCH3_Pos                             6                                                         /*!< CREG DMAMUX: DMAMUXCH3 Position     */
+#define CREG_DMAMUX_DMAMUXCH3_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos)                     /*!< CREG DMAMUX: DMAMUXCH3 Mask         */
+#define CREG_DMAMUX_DMAMUXCH4_Pos                             8                                                         /*!< CREG DMAMUX: DMAMUXCH4 Position     */
+#define CREG_DMAMUX_DMAMUXCH4_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos)                     /*!< CREG DMAMUX: DMAMUXCH4 Mask         */
+#define CREG_DMAMUX_DMAMUXCH5_Pos                             10                                                        /*!< CREG DMAMUX: DMAMUXCH5 Position     */
+#define CREG_DMAMUX_DMAMUXCH5_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos)                     /*!< CREG DMAMUX: DMAMUXCH5 Mask         */
+#define CREG_DMAMUX_DMAMUXCH6_Pos                             12                                                        /*!< CREG DMAMUX: DMAMUXCH6 Position     */
+#define CREG_DMAMUX_DMAMUXCH6_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos)                     /*!< CREG DMAMUX: DMAMUXCH6 Mask         */
+#define CREG_DMAMUX_DMAMUXCH7_Pos                             14                                                        /*!< CREG DMAMUX: DMAMUXCH7 Position     */
+#define CREG_DMAMUX_DMAMUXCH7_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos)                     /*!< CREG DMAMUX: DMAMUXCH7 Mask         */
+#define CREG_DMAMUX_DMAMUXCH8_Pos                             16                                                        /*!< CREG DMAMUX: DMAMUXCH8 Position     */
+#define CREG_DMAMUX_DMAMUXCH8_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos)                     /*!< CREG DMAMUX: DMAMUXCH8 Mask         */
+#define CREG_DMAMUX_DMAMUXCH9_Pos                             18                                                        /*!< CREG DMAMUX: DMAMUXCH9 Position     */
+#define CREG_DMAMUX_DMAMUXCH9_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos)                     /*!< CREG DMAMUX: DMAMUXCH9 Mask         */
+#define CREG_DMAMUX_DMAMUXCH10_Pos                            20                                                        /*!< CREG DMAMUX: DMAMUXCH10 Position    */
+#define CREG_DMAMUX_DMAMUXCH10_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos)                    /*!< CREG DMAMUX: DMAMUXCH10 Mask        */
+#define CREG_DMAMUX_DMAMUXCH11_Pos                            22                                                        /*!< CREG DMAMUX: DMAMUXCH11 Position    */
+#define CREG_DMAMUX_DMAMUXCH11_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos)                    /*!< CREG DMAMUX: DMAMUXCH11 Mask        */
+#define CREG_DMAMUX_DMAMUXCH12_Pos                            24                                                        /*!< CREG DMAMUX: DMAMUXCH12 Position    */
+#define CREG_DMAMUX_DMAMUXCH12_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos)                    /*!< CREG DMAMUX: DMAMUXCH12 Mask        */
+#define CREG_DMAMUX_DMAMUXCH13_Pos                            26                                                        /*!< CREG DMAMUX: DMAMUXCH13 Position    */
+#define CREG_DMAMUX_DMAMUXCH13_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos)                    /*!< CREG DMAMUX: DMAMUXCH13 Mask        */
+#define CREG_DMAMUX_DMAMUXCH14_Pos                            28                                                        /*!< CREG DMAMUX: DMAMUXCH14 Position    */
+#define CREG_DMAMUX_DMAMUXCH14_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos)                    /*!< CREG DMAMUX: DMAMUXCH14 Mask        */
+#define CREG_DMAMUX_DMAMUXCH15_Pos                            30                                                        /*!< CREG DMAMUX: DMAMUXCH15 Position    */
+#define CREG_DMAMUX_DMAMUXCH15_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos)                    /*!< CREG DMAMUX: DMAMUXCH15 Mask        */
+
+// ---------------------------------------  CREG_ETBCFG  ------------------------------------------
+#define CREG_ETBCFG_ETB_Pos                                   0                                                         /*!< CREG ETBCFG: ETB Position           */
+#define CREG_ETBCFG_ETB_Msk                                   (0x01UL << CREG_ETBCFG_ETB_Pos)                           /*!< CREG ETBCFG: ETB Mask               */
+
+// ---------------------------------------  CREG_CREG6  -------------------------------------------
+#define CREG_CREG6_ETHMODE_Pos                                0                                                         /*!< CREG CREG6: ETHMODE Position        */
+#define CREG_CREG6_ETHMODE_Msk                                (0x07UL << CREG_CREG6_ETHMODE_Pos)                        /*!< CREG CREG6: ETHMODE Mask            */
+#define CREG_CREG6_TIMCTRL_Pos                                4                                                         /*!< CREG CREG6: TIMCTRL Position        */
+#define CREG_CREG6_TIMCTRL_Msk                                (0x01UL << CREG_CREG6_TIMCTRL_Pos)                        /*!< CREG CREG6: TIMCTRL Mask            */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos                     12                                                        /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos                     13                                                        /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos                     14                                                        /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos                     15                                                        /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_EMC_CLK_SEL_Pos                            16                                                        /*!< CREG CREG6: EMC_CLK_SEL Position    */
+#define CREG_CREG6_EMC_CLK_SEL_Msk                            (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos)                    /*!< CREG CREG6: EMC_CLK_SEL Mask        */
+
+// -------------------------------------  CREG_M4TXEVENT  -----------------------------------------
+#define CREG_M4TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M4TXEVENT: TXEVCLR Position    */
+#define CREG_M4TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos)                    /*!< CREG M4TXEVENT: TXEVCLR Mask        */
+
+// ---------------------------------------  CREG_CHIPID  ------------------------------------------
+#define CREG_CHIPID_ID_Pos                                    0                                                         /*!< CREG CHIPID: ID Position            */
+#define CREG_CHIPID_ID_Msk                                    (0xffffffffUL << CREG_CHIPID_ID_Pos)                      /*!< CREG CHIPID: ID Mask                */
+
+// -------------------------------------  CREG_M0TXEVENT  -----------------------------------------
+#define CREG_M0TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M0TXEVENT: TXEVCLR Position    */
+#define CREG_M0TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos)                    /*!< CREG M0TXEVENT: TXEVCLR Mask        */
+
+// ------------------------------------  CREG_M0APPMEMMAP  ----------------------------------------
+#define CREG_M0APPMEMMAP_M0APPMAP_Pos                         12                                                        /*!< CREG M0APPMEMMAP: M0APPMAP Position */
+#define CREG_M0APPMEMMAP_M0APPMAP_Msk                         (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos)           /*!< CREG M0APPMEMMAP: M0APPMAP Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                              EVENTROUTER Position & Mask                             -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------  EVENTROUTER_HILO  ----------------------------------------
+#define EVENTROUTER_HILO_WAKEUP0_L_Pos                        0                                                         /*!< EVENTROUTER HILO: WAKEUP0_L Position */
+#define EVENTROUTER_HILO_WAKEUP0_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP0_L Mask    */
+#define EVENTROUTER_HILO_WAKEUP1_L_Pos                        1                                                         /*!< EVENTROUTER HILO: WAKEUP1_L Position */
+#define EVENTROUTER_HILO_WAKEUP1_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP1_L Mask    */
+#define EVENTROUTER_HILO_WAKEUP2_L_Pos                        2                                                         /*!< EVENTROUTER HILO: WAKEUP2_L Position */
+#define EVENTROUTER_HILO_WAKEUP2_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP2_L Mask    */
+#define EVENTROUTER_HILO_WAKEUP3_L_Pos                        3                                                         /*!< EVENTROUTER HILO: WAKEUP3_L Position */
+#define EVENTROUTER_HILO_WAKEUP3_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP3_L Mask    */
+#define EVENTROUTER_HILO_ATIMER_L_Pos                         4                                                         /*!< EVENTROUTER HILO: ATIMER_L Position */
+#define EVENTROUTER_HILO_ATIMER_L_Msk                         (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos)                 /*!< EVENTROUTER HILO: ATIMER_L Mask     */
+#define EVENTROUTER_HILO_RTC_L_Pos                            5                                                         /*!< EVENTROUTER HILO: RTC_L Position    */
+#define EVENTROUTER_HILO_RTC_L_Msk                            (0x01UL << EVENTROUTER_HILO_RTC_L_Pos)                    /*!< EVENTROUTER HILO: RTC_L Mask        */
+#define EVENTROUTER_HILO_BOD_L_Pos                            6                                                         /*!< EVENTROUTER HILO: BOD_L Position    */
+#define EVENTROUTER_HILO_BOD_L_Msk                            (0x01UL << EVENTROUTER_HILO_BOD_L_Pos)                    /*!< EVENTROUTER HILO: BOD_L Mask        */
+#define EVENTROUTER_HILO_WWDT_L_Pos                           7                                                         /*!< EVENTROUTER HILO: WWDT_L Position   */
+#define EVENTROUTER_HILO_WWDT_L_Msk                           (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos)                   /*!< EVENTROUTER HILO: WWDT_L Mask       */
+#define EVENTROUTER_HILO_ETH_L_Pos                            8                                                         /*!< EVENTROUTER HILO: ETH_L Position    */
+#define EVENTROUTER_HILO_ETH_L_Msk                            (0x01UL << EVENTROUTER_HILO_ETH_L_Pos)                    /*!< EVENTROUTER HILO: ETH_L Mask        */
+#define EVENTROUTER_HILO_USB0_L_Pos                           9                                                         /*!< EVENTROUTER HILO: USB0_L Position   */
+#define EVENTROUTER_HILO_USB0_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB0_L_Pos)                   /*!< EVENTROUTER HILO: USB0_L Mask       */
+#define EVENTROUTER_HILO_USB1_L_Pos                           10                                                        /*!< EVENTROUTER HILO: USB1_L Position   */
+#define EVENTROUTER_HILO_USB1_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB1_L_Pos)                   /*!< EVENTROUTER HILO: USB1_L Mask       */
+#define EVENTROUTER_HILO_SDMMC_L_Pos                          11                                                        /*!< EVENTROUTER HILO: SDMMC_L Position  */
+#define EVENTROUTER_HILO_SDMMC_L_Msk                          (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos)                  /*!< EVENTROUTER HILO: SDMMC_L Mask      */
+#define EVENTROUTER_HILO_CAN_L_Pos                            12                                                        /*!< EVENTROUTER HILO: CAN_L Position    */
+#define EVENTROUTER_HILO_CAN_L_Msk                            (0x01UL << EVENTROUTER_HILO_CAN_L_Pos)                    /*!< EVENTROUTER HILO: CAN_L Mask        */
+#define EVENTROUTER_HILO_TIM2_L_Pos                           13                                                        /*!< EVENTROUTER HILO: TIM2_L Position   */
+#define EVENTROUTER_HILO_TIM2_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos)                   /*!< EVENTROUTER HILO: TIM2_L Mask       */
+#define EVENTROUTER_HILO_TIM6_L_Pos                           14                                                        /*!< EVENTROUTER HILO: TIM6_L Position   */
+#define EVENTROUTER_HILO_TIM6_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos)                   /*!< EVENTROUTER HILO: TIM6_L Mask       */
+#define EVENTROUTER_HILO_QEI_L_Pos                            15                                                        /*!< EVENTROUTER HILO: QEI_L Position    */
+#define EVENTROUTER_HILO_QEI_L_Msk                            (0x01UL << EVENTROUTER_HILO_QEI_L_Pos)                    /*!< EVENTROUTER HILO: QEI_L Mask        */
+#define EVENTROUTER_HILO_TIM14_L_Pos                          16                                                        /*!< EVENTROUTER HILO: TIM14_L Position  */
+#define EVENTROUTER_HILO_TIM14_L_Msk                          (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos)                  /*!< EVENTROUTER HILO: TIM14_L Mask      */
+#define EVENTROUTER_HILO_RESET_L_Pos                          19                                                        /*!< EVENTROUTER HILO: RESET_L Position  */
+#define EVENTROUTER_HILO_RESET_L_Msk                          (0x01UL << EVENTROUTER_HILO_RESET_L_Pos)                  /*!< EVENTROUTER HILO: RESET_L Mask      */
+
+// ------------------------------------  EVENTROUTER_EDGE  ----------------------------------------
+#define EVENTROUTER_EDGE_WAKEUP0_E_Pos                        0                                                         /*!< EVENTROUTER EDGE: WAKEUP0_E Position */
+#define EVENTROUTER_EDGE_WAKEUP0_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP0_E Mask    */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Pos                        1                                                         /*!< EVENTROUTER EDGE: WAKEUP1_E Position */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP1_E Mask    */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Pos                        2                                                         /*!< EVENTROUTER EDGE: WAKEUP2_E Position */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP2_E Mask    */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Pos                        3                                                         /*!< EVENTROUTER EDGE: WAKEUP3_E Position */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP3_E Mask    */
+#define EVENTROUTER_EDGE_ATIMER_E_Pos                         4                                                         /*!< EVENTROUTER EDGE: ATIMER_E Position */
+#define EVENTROUTER_EDGE_ATIMER_E_Msk                         (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos)                 /*!< EVENTROUTER EDGE: ATIMER_E Mask     */
+#define EVENTROUTER_EDGE_RTC_E_Pos                            5                                                         /*!< EVENTROUTER EDGE: RTC_E Position    */
+#define EVENTROUTER_EDGE_RTC_E_Msk                            (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos)                    /*!< EVENTROUTER EDGE: RTC_E Mask        */
+#define EVENTROUTER_EDGE_BOD_E_Pos                            6                                                         /*!< EVENTROUTER EDGE: BOD_E Position    */
+#define EVENTROUTER_EDGE_BOD_E_Msk                            (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos)                    /*!< EVENTROUTER EDGE: BOD_E Mask        */
+#define EVENTROUTER_EDGE_WWDT_E_Pos                           7                                                         /*!< EVENTROUTER EDGE: WWDT_E Position   */
+#define EVENTROUTER_EDGE_WWDT_E_Msk                           (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos)                   /*!< EVENTROUTER EDGE: WWDT_E Mask       */
+#define EVENTROUTER_EDGE_ETH_E_Pos                            8                                                         /*!< EVENTROUTER EDGE: ETH_E Position    */
+#define EVENTROUTER_EDGE_ETH_E_Msk                            (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos)                    /*!< EVENTROUTER EDGE: ETH_E Mask        */
+#define EVENTROUTER_EDGE_USB0_E_Pos                           9                                                         /*!< EVENTROUTER EDGE: USB0_E Position   */
+#define EVENTROUTER_EDGE_USB0_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos)                   /*!< EVENTROUTER EDGE: USB0_E Mask       */
+#define EVENTROUTER_EDGE_USB1_E_Pos                           10                                                        /*!< EVENTROUTER EDGE: USB1_E Position   */
+#define EVENTROUTER_EDGE_USB1_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos)                   /*!< EVENTROUTER EDGE: USB1_E Mask       */
+#define EVENTROUTER_EDGE_SDMMC_E_Pos                          11                                                        /*!< EVENTROUTER EDGE: SDMMC_E Position  */
+#define EVENTROUTER_EDGE_SDMMC_E_Msk                          (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos)                  /*!< EVENTROUTER EDGE: SDMMC_E Mask      */
+#define EVENTROUTER_EDGE_CAN_E_Pos                            12                                                        /*!< EVENTROUTER EDGE: CAN_E Position    */
+#define EVENTROUTER_EDGE_CAN_E_Msk                            (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos)                    /*!< EVENTROUTER EDGE: CAN_E Mask        */
+#define EVENTROUTER_EDGE_TIM2_E_Pos                           13                                                        /*!< EVENTROUTER EDGE: TIM2_E Position   */
+#define EVENTROUTER_EDGE_TIM2_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos)                   /*!< EVENTROUTER EDGE: TIM2_E Mask       */
+#define EVENTROUTER_EDGE_TIM6_E_Pos                           14                                                        /*!< EVENTROUTER EDGE: TIM6_E Position   */
+#define EVENTROUTER_EDGE_TIM6_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos)                   /*!< EVENTROUTER EDGE: TIM6_E Mask       */
+#define EVENTROUTER_EDGE_QEI_E_Pos                            15                                                        /*!< EVENTROUTER EDGE: QEI_E Position    */
+#define EVENTROUTER_EDGE_QEI_E_Msk                            (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos)                    /*!< EVENTROUTER EDGE: QEI_E Mask        */
+#define EVENTROUTER_EDGE_TIM14_E_Pos                          16                                                        /*!< EVENTROUTER EDGE: TIM14_E Position  */
+#define EVENTROUTER_EDGE_TIM14_E_Msk                          (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos)                  /*!< EVENTROUTER EDGE: TIM14_E Mask      */
+#define EVENTROUTER_EDGE_RESET_E_Pos                          19                                                        /*!< EVENTROUTER EDGE: RESET_E Position  */
+#define EVENTROUTER_EDGE_RESET_E_Msk                          (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos)                  /*!< EVENTROUTER EDGE: RESET_E Mask      */
+
+// -----------------------------------  EVENTROUTER_CLR_EN  ---------------------------------------
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos                  0                                                         /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos                  1                                                         /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos                  2                                                         /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos                  3                                                         /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos                   4                                                         /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk                   (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos)           /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos                      5                                                         /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos                      6                                                         /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos                     7                                                         /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos                      8                                                         /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos                     9                                                         /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos                     10                                                        /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos                    11                                                        /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos                      12                                                        /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos                     13                                                        /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos                     14                                                        /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos                      15                                                        /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos                    16                                                        /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos                    19                                                        /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */
+
+// -----------------------------------  EVENTROUTER_SET_EN  ---------------------------------------
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos                  0                                                         /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos                  1                                                         /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos                  2                                                         /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos                  3                                                         /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos                   4                                                         /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk                   (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos)           /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Pos                      5                                                         /*!< EVENTROUTER SET_EN: RTC_SETEN Position */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos)              /*!< EVENTROUTER SET_EN: RTC_SETEN Mask  */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Pos                      6                                                         /*!< EVENTROUTER SET_EN: BOD_SETEN Position */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos)              /*!< EVENTROUTER SET_EN: BOD_SETEN Mask  */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos                     7                                                         /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos)             /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Pos                      8                                                         /*!< EVENTROUTER SET_EN: ETH_SETEN Position */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos)              /*!< EVENTROUTER SET_EN: ETH_SETEN Mask  */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Pos                     9                                                         /*!< EVENTROUTER SET_EN: USB0_SETEN Position */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Pos                     10                                                        /*!< EVENTROUTER SET_EN: USB1_SETEN Position */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos                    11                                                        /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos)            /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Pos                      12                                                        /*!< EVENTROUTER SET_EN: CAN_SETEN Position */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos)              /*!< EVENTROUTER SET_EN: CAN_SETEN Mask  */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos                     13                                                        /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos                     14                                                        /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Pos                      15                                                        /*!< EVENTROUTER SET_EN: QEI_SETEN Position */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos)              /*!< EVENTROUTER SET_EN: QEI_SETEN Mask  */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos                    16                                                        /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos)            /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Pos                    19                                                        /*!< EVENTROUTER SET_EN: RESET_SETEN Position */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos)            /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */
+
+// -----------------------------------  EVENTROUTER_STATUS  ---------------------------------------
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos                     0                                                         /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos                     1                                                         /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos                     2                                                         /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos                     3                                                         /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */
+#define EVENTROUTER_STATUS_ATIMER_ST_Pos                      4                                                         /*!< EVENTROUTER STATUS: ATIMER_ST Position */
+#define EVENTROUTER_STATUS_ATIMER_ST_Msk                      (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos)              /*!< EVENTROUTER STATUS: ATIMER_ST Mask  */
+#define EVENTROUTER_STATUS_RTC_ST_Pos                         5                                                         /*!< EVENTROUTER STATUS: RTC_ST Position */
+#define EVENTROUTER_STATUS_RTC_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos)                 /*!< EVENTROUTER STATUS: RTC_ST Mask     */
+#define EVENTROUTER_STATUS_BOD_ST_Pos                         6                                                         /*!< EVENTROUTER STATUS: BOD_ST Position */
+#define EVENTROUTER_STATUS_BOD_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos)                 /*!< EVENTROUTER STATUS: BOD_ST Mask     */
+#define EVENTROUTER_STATUS_WWDT_ST_Pos                        7                                                         /*!< EVENTROUTER STATUS: WWDT_ST Position */
+#define EVENTROUTER_STATUS_WWDT_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos)                /*!< EVENTROUTER STATUS: WWDT_ST Mask    */
+#define EVENTROUTER_STATUS_ETH_ST_Pos                         8                                                         /*!< EVENTROUTER STATUS: ETH_ST Position */
+#define EVENTROUTER_STATUS_ETH_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos)                 /*!< EVENTROUTER STATUS: ETH_ST Mask     */
+#define EVENTROUTER_STATUS_USB0_ST_Pos                        9                                                         /*!< EVENTROUTER STATUS: USB0_ST Position */
+#define EVENTROUTER_STATUS_USB0_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos)                /*!< EVENTROUTER STATUS: USB0_ST Mask    */
+#define EVENTROUTER_STATUS_USB1_ST_Pos                        10                                                        /*!< EVENTROUTER STATUS: USB1_ST Position */
+#define EVENTROUTER_STATUS_USB1_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos)                /*!< EVENTROUTER STATUS: USB1_ST Mask    */
+#define EVENTROUTER_STATUS_SDMMC_ST_Pos                       11                                                        /*!< EVENTROUTER STATUS: SDMMC_ST Position */
+#define EVENTROUTER_STATUS_SDMMC_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos)               /*!< EVENTROUTER STATUS: SDMMC_ST Mask   */
+#define EVENTROUTER_STATUS_CAN_ST_Pos                         12                                                        /*!< EVENTROUTER STATUS: CAN_ST Position */
+#define EVENTROUTER_STATUS_CAN_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos)                 /*!< EVENTROUTER STATUS: CAN_ST Mask     */
+#define EVENTROUTER_STATUS_TIM2_ST_Pos                        13                                                        /*!< EVENTROUTER STATUS: TIM2_ST Position */
+#define EVENTROUTER_STATUS_TIM2_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos)                /*!< EVENTROUTER STATUS: TIM2_ST Mask    */
+#define EVENTROUTER_STATUS_TIM6_ST_Pos                        14                                                        /*!< EVENTROUTER STATUS: TIM6_ST Position */
+#define EVENTROUTER_STATUS_TIM6_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos)                /*!< EVENTROUTER STATUS: TIM6_ST Mask    */
+#define EVENTROUTER_STATUS_QEI_ST_Pos                         15                                                        /*!< EVENTROUTER STATUS: QEI_ST Position */
+#define EVENTROUTER_STATUS_QEI_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos)                 /*!< EVENTROUTER STATUS: QEI_ST Mask     */
+#define EVENTROUTER_STATUS_TIM14_ST_Pos                       16                                                        /*!< EVENTROUTER STATUS: TIM14_ST Position */
+#define EVENTROUTER_STATUS_TIM14_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos)               /*!< EVENTROUTER STATUS: TIM14_ST Mask   */
+#define EVENTROUTER_STATUS_RESET_ST_Pos                       19                                                        /*!< EVENTROUTER STATUS: RESET_ST Position */
+#define EVENTROUTER_STATUS_RESET_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos)               /*!< EVENTROUTER STATUS: RESET_ST Mask   */
+
+// -----------------------------------  EVENTROUTER_ENABLE  ---------------------------------------
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos                     0                                                         /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos                     1                                                         /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos                     2                                                         /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos                     3                                                         /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Pos                      4                                                         /*!< EVENTROUTER ENABLE: ATIMER_EN Position */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Msk                      (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos)              /*!< EVENTROUTER ENABLE: ATIMER_EN Mask  */
+#define EVENTROUTER_ENABLE_RTC_EN_Pos                         5                                                         /*!< EVENTROUTER ENABLE: RTC_EN Position */
+#define EVENTROUTER_ENABLE_RTC_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos)                 /*!< EVENTROUTER ENABLE: RTC_EN Mask     */
+#define EVENTROUTER_ENABLE_BOD_EN_Pos                         6                                                         /*!< EVENTROUTER ENABLE: BOD_EN Position */
+#define EVENTROUTER_ENABLE_BOD_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos)                 /*!< EVENTROUTER ENABLE: BOD_EN Mask     */
+#define EVENTROUTER_ENABLE_WWDT_EN_Pos                        7                                                         /*!< EVENTROUTER ENABLE: WWDT_EN Position */
+#define EVENTROUTER_ENABLE_WWDT_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos)                /*!< EVENTROUTER ENABLE: WWDT_EN Mask    */
+#define EVENTROUTER_ENABLE_ETH_EN_Pos                         8                                                         /*!< EVENTROUTER ENABLE: ETH_EN Position */
+#define EVENTROUTER_ENABLE_ETH_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos)                 /*!< EVENTROUTER ENABLE: ETH_EN Mask     */
+#define EVENTROUTER_ENABLE_USB0_EN_Pos                        9                                                         /*!< EVENTROUTER ENABLE: USB0_EN Position */
+#define EVENTROUTER_ENABLE_USB0_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos)                /*!< EVENTROUTER ENABLE: USB0_EN Mask    */
+#define EVENTROUTER_ENABLE_USB1_EN_Pos                        10                                                        /*!< EVENTROUTER ENABLE: USB1_EN Position */
+#define EVENTROUTER_ENABLE_USB1_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos)                /*!< EVENTROUTER ENABLE: USB1_EN Mask    */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Pos                       11                                                        /*!< EVENTROUTER ENABLE: SDMMC_EN Position */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos)               /*!< EVENTROUTER ENABLE: SDMMC_EN Mask   */
+#define EVENTROUTER_ENABLE_CAN_EN_Pos                         12                                                        /*!< EVENTROUTER ENABLE: CAN_EN Position */
+#define EVENTROUTER_ENABLE_CAN_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos)                 /*!< EVENTROUTER ENABLE: CAN_EN Mask     */
+#define EVENTROUTER_ENABLE_TIM2_EN_Pos                        13                                                        /*!< EVENTROUTER ENABLE: TIM2_EN Position */
+#define EVENTROUTER_ENABLE_TIM2_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM2_EN Mask    */
+#define EVENTROUTER_ENABLE_TIM6_EN_Pos                        14                                                        /*!< EVENTROUTER ENABLE: TIM6_EN Position */
+#define EVENTROUTER_ENABLE_TIM6_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM6_EN Mask    */
+#define EVENTROUTER_ENABLE_QEI_EN_Pos                         15                                                        /*!< EVENTROUTER ENABLE: QEI_EN Position */
+#define EVENTROUTER_ENABLE_QEI_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos)                 /*!< EVENTROUTER ENABLE: QEI_EN Mask     */
+#define EVENTROUTER_ENABLE_TIM14_EN_Pos                       16                                                        /*!< EVENTROUTER ENABLE: TIM14_EN Position */
+#define EVENTROUTER_ENABLE_TIM14_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos)               /*!< EVENTROUTER ENABLE: TIM14_EN Mask   */
+#define EVENTROUTER_ENABLE_RESET_EN_Pos                       19                                                        /*!< EVENTROUTER ENABLE: RESET_EN Position */
+#define EVENTROUTER_ENABLE_RESET_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos)               /*!< EVENTROUTER ENABLE: RESET_EN Mask   */
+
+// ----------------------------------  EVENTROUTER_CLR_STAT  --------------------------------------
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos                0                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos                1                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos                2                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos                3                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos                 4                                                         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk                 (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos)         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos                    5                                                         /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos                    6                                                         /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos                   7                                                         /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos                    8                                                         /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos                   9                                                         /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos                   10                                                        /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos                  11                                                        /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos                    12                                                        /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos                   13                                                        /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos                   14                                                        /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos                    15                                                        /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos                  16                                                        /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos                  19                                                        /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */
+
+// ----------------------------------  EVENTROUTER_SET_STAT  --------------------------------------
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos                0                                                         /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos                1                                                         /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos                2                                                         /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos                3                                                         /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos                 4                                                         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk                 (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos)         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Pos                    5                                                         /*!< EVENTROUTER SET_STAT: RTC_SETST Position */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos)            /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Pos                    6                                                         /*!< EVENTROUTER SET_STAT: BOD_SETST Position */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos)            /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos                   7                                                         /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos)           /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Pos                    8                                                         /*!< EVENTROUTER SET_STAT: ETH_SETST Position */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos)            /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Pos                   9                                                         /*!< EVENTROUTER SET_STAT: USB0_SETST Position */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Pos                   10                                                        /*!< EVENTROUTER SET_STAT: USB1_SETST Position */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos                  11                                                        /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos)          /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Pos                    12                                                        /*!< EVENTROUTER SET_STAT: CAN_SETST Position */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos)            /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos                   13                                                        /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos                   14                                                        /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Pos                    15                                                        /*!< EVENTROUTER SET_STAT: QEI_SETST Position */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos)            /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos                  16                                                        /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos)          /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Pos                  19                                                        /*!< EVENTROUTER SET_STAT: RESET_SETST Position */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos)          /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  RTC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  RTC_ILR  --------------------------------------------
+#define RTC_ILR_RTCCIF_Pos                                    0                                                         /*!< RTC ILR: RTCCIF Position            */
+#define RTC_ILR_RTCCIF_Msk                                    (0x01UL << RTC_ILR_RTCCIF_Pos)                            /*!< RTC ILR: RTCCIF Mask                */
+#define RTC_ILR_RTCALF_Pos                                    1                                                         /*!< RTC ILR: RTCALF Position            */
+#define RTC_ILR_RTCALF_Msk                                    (0x01UL << RTC_ILR_RTCALF_Pos)                            /*!< RTC ILR: RTCALF Mask                */
+
+// -----------------------------------------  RTC_CCR  --------------------------------------------
+#define RTC_CCR_CLKEN_Pos                                     0                                                         /*!< RTC CCR: CLKEN Position             */
+#define RTC_CCR_CLKEN_Msk                                     (0x01UL << RTC_CCR_CLKEN_Pos)                             /*!< RTC CCR: CLKEN Mask                 */
+#define RTC_CCR_CTCRST_Pos                                    1                                                         /*!< RTC CCR: CTCRST Position            */
+#define RTC_CCR_CTCRST_Msk                                    (0x01UL << RTC_CCR_CTCRST_Pos)                            /*!< RTC CCR: CTCRST Mask                */
+#define RTC_CCR_CCALEN_Pos                                    4                                                         /*!< RTC CCR: CCALEN Position            */
+#define RTC_CCR_CCALEN_Msk                                    (0x01UL << RTC_CCR_CCALEN_Pos)                            /*!< RTC CCR: CCALEN Mask                */
+
+// ----------------------------------------  RTC_CIIR  --------------------------------------------
+#define RTC_CIIR_IMSEC_Pos                                    0                                                         /*!< RTC CIIR: IMSEC Position            */
+#define RTC_CIIR_IMSEC_Msk                                    (0x01UL << RTC_CIIR_IMSEC_Pos)                            /*!< RTC CIIR: IMSEC Mask                */
+#define RTC_CIIR_IMMIN_Pos                                    1                                                         /*!< RTC CIIR: IMMIN Position            */
+#define RTC_CIIR_IMMIN_Msk                                    (0x01UL << RTC_CIIR_IMMIN_Pos)                            /*!< RTC CIIR: IMMIN Mask                */
+#define RTC_CIIR_IMHOUR_Pos                                   2                                                         /*!< RTC CIIR: IMHOUR Position           */
+#define RTC_CIIR_IMHOUR_Msk                                   (0x01UL << RTC_CIIR_IMHOUR_Pos)                           /*!< RTC CIIR: IMHOUR Mask               */
+#define RTC_CIIR_IMDOM_Pos                                    3                                                         /*!< RTC CIIR: IMDOM Position            */
+#define RTC_CIIR_IMDOM_Msk                                    (0x01UL << RTC_CIIR_IMDOM_Pos)                            /*!< RTC CIIR: IMDOM Mask                */
+#define RTC_CIIR_IMDOW_Pos                                    4                                                         /*!< RTC CIIR: IMDOW Position            */
+#define RTC_CIIR_IMDOW_Msk                                    (0x01UL << RTC_CIIR_IMDOW_Pos)                            /*!< RTC CIIR: IMDOW Mask                */
+#define RTC_CIIR_IMDOY_Pos                                    5                                                         /*!< RTC CIIR: IMDOY Position            */
+#define RTC_CIIR_IMDOY_Msk                                    (0x01UL << RTC_CIIR_IMDOY_Pos)                            /*!< RTC CIIR: IMDOY Mask                */
+#define RTC_CIIR_IMMON_Pos                                    6                                                         /*!< RTC CIIR: IMMON Position            */
+#define RTC_CIIR_IMMON_Msk                                    (0x01UL << RTC_CIIR_IMMON_Pos)                            /*!< RTC CIIR: IMMON Mask                */
+#define RTC_CIIR_IMYEAR_Pos                                   7                                                         /*!< RTC CIIR: IMYEAR Position           */
+#define RTC_CIIR_IMYEAR_Msk                                   (0x01UL << RTC_CIIR_IMYEAR_Pos)                           /*!< RTC CIIR: IMYEAR Mask               */
+
+// -----------------------------------------  RTC_AMR  --------------------------------------------
+#define RTC_AMR_AMRSEC_Pos                                    0                                                         /*!< RTC AMR: AMRSEC Position            */
+#define RTC_AMR_AMRSEC_Msk                                    (0x01UL << RTC_AMR_AMRSEC_Pos)                            /*!< RTC AMR: AMRSEC Mask                */
+#define RTC_AMR_AMRMIN_Pos                                    1                                                         /*!< RTC AMR: AMRMIN Position            */
+#define RTC_AMR_AMRMIN_Msk                                    (0x01UL << RTC_AMR_AMRMIN_Pos)                            /*!< RTC AMR: AMRMIN Mask                */
+#define RTC_AMR_AMRHOUR_Pos                                   2                                                         /*!< RTC AMR: AMRHOUR Position           */
+#define RTC_AMR_AMRHOUR_Msk                                   (0x01UL << RTC_AMR_AMRHOUR_Pos)                           /*!< RTC AMR: AMRHOUR Mask               */
+#define RTC_AMR_AMRDOM_Pos                                    3                                                         /*!< RTC AMR: AMRDOM Position            */
+#define RTC_AMR_AMRDOM_Msk                                    (0x01UL << RTC_AMR_AMRDOM_Pos)                            /*!< RTC AMR: AMRDOM Mask                */
+#define RTC_AMR_AMRDOW_Pos                                    4                                                         /*!< RTC AMR: AMRDOW Position            */
+#define RTC_AMR_AMRDOW_Msk                                    (0x01UL << RTC_AMR_AMRDOW_Pos)                            /*!< RTC AMR: AMRDOW Mask                */
+#define RTC_AMR_AMRDOY_Pos                                    5                                                         /*!< RTC AMR: AMRDOY Position            */
+#define RTC_AMR_AMRDOY_Msk                                    (0x01UL << RTC_AMR_AMRDOY_Pos)                            /*!< RTC AMR: AMRDOY Mask                */
+#define RTC_AMR_AMRMON_Pos                                    6                                                         /*!< RTC AMR: AMRMON Position            */
+#define RTC_AMR_AMRMON_Msk                                    (0x01UL << RTC_AMR_AMRMON_Pos)                            /*!< RTC AMR: AMRMON Mask                */
+#define RTC_AMR_AMRYEAR_Pos                                   7                                                         /*!< RTC AMR: AMRYEAR Position           */
+#define RTC_AMR_AMRYEAR_Msk                                   (0x01UL << RTC_AMR_AMRYEAR_Pos)                           /*!< RTC AMR: AMRYEAR Mask               */
+
+// ---------------------------------------  RTC_CTIME0  -------------------------------------------
+#define RTC_CTIME0_SECONDS_Pos                                0                                                         /*!< RTC CTIME0: SECONDS Position        */
+#define RTC_CTIME0_SECONDS_Msk                                (0x3fUL << RTC_CTIME0_SECONDS_Pos)                        /*!< RTC CTIME0: SECONDS Mask            */
+#define RTC_CTIME0_MINUTES_Pos                                8                                                         /*!< RTC CTIME0: MINUTES Position        */
+#define RTC_CTIME0_MINUTES_Msk                                (0x3fUL << RTC_CTIME0_MINUTES_Pos)                        /*!< RTC CTIME0: MINUTES Mask            */
+#define RTC_CTIME0_HOURS_Pos                                  16                                                        /*!< RTC CTIME0: HOURS Position          */
+#define RTC_CTIME0_HOURS_Msk                                  (0x1fUL << RTC_CTIME0_HOURS_Pos)                          /*!< RTC CTIME0: HOURS Mask              */
+#define RTC_CTIME0_DOW_Pos                                    24                                                        /*!< RTC CTIME0: DOW Position            */
+#define RTC_CTIME0_DOW_Msk                                    (0x07UL << RTC_CTIME0_DOW_Pos)                            /*!< RTC CTIME0: DOW Mask                */
+
+// ---------------------------------------  RTC_CTIME1  -------------------------------------------
+#define RTC_CTIME1_DOM_Pos                                    0                                                         /*!< RTC CTIME1: DOM Position            */
+#define RTC_CTIME1_DOM_Msk                                    (0x1fUL << RTC_CTIME1_DOM_Pos)                            /*!< RTC CTIME1: DOM Mask                */
+#define RTC_CTIME1_MONTH_Pos                                  8                                                         /*!< RTC CTIME1: MONTH Position          */
+#define RTC_CTIME1_MONTH_Msk                                  (0x0fUL << RTC_CTIME1_MONTH_Pos)                          /*!< RTC CTIME1: MONTH Mask              */
+#define RTC_CTIME1_YEAR_Pos                                   16                                                        /*!< RTC CTIME1: YEAR Position           */
+#define RTC_CTIME1_YEAR_Msk                                   (0x00000fffUL << RTC_CTIME1_YEAR_Pos)                     /*!< RTC CTIME1: YEAR Mask               */
+
+// ---------------------------------------  RTC_CTIME2  -------------------------------------------
+#define RTC_CTIME2_DOY_Pos                                    0                                                         /*!< RTC CTIME2: DOY Position            */
+#define RTC_CTIME2_DOY_Msk                                    (0x00000fffUL << RTC_CTIME2_DOY_Pos)                      /*!< RTC CTIME2: DOY Mask                */
+
+// -----------------------------------------  RTC_SEC  --------------------------------------------
+#define RTC_SEC_SECONDS_Pos                                   0                                                         /*!< RTC SEC: SECONDS Position           */
+#define RTC_SEC_SECONDS_Msk                                   (0x3fUL << RTC_SEC_SECONDS_Pos)                           /*!< RTC SEC: SECONDS Mask               */
+
+// -----------------------------------------  RTC_MIN  --------------------------------------------
+#define RTC_MIN_MINUTES_Pos                                   0                                                         /*!< RTC MIN: MINUTES Position           */
+#define RTC_MIN_MINUTES_Msk                                   (0x3fUL << RTC_MIN_MINUTES_Pos)                           /*!< RTC MIN: MINUTES Mask               */
+
+// -----------------------------------------  RTC_HRS  --------------------------------------------
+#define RTC_HRS_HOURS_Pos                                     0                                                         /*!< RTC HRS: HOURS Position             */
+#define RTC_HRS_HOURS_Msk                                     (0x1fUL << RTC_HRS_HOURS_Pos)                             /*!< RTC HRS: HOURS Mask                 */
+
+// -----------------------------------------  RTC_DOM  --------------------------------------------
+#define RTC_DOM_DOM_Pos                                       0                                                         /*!< RTC DOM: DOM Position               */
+#define RTC_DOM_DOM_Msk                                       (0x1fUL << RTC_DOM_DOM_Pos)                               /*!< RTC DOM: DOM Mask                   */
+
+// -----------------------------------------  RTC_DOW  --------------------------------------------
+#define RTC_DOW_DOW_Pos                                       0                                                         /*!< RTC DOW: DOW Position               */
+#define RTC_DOW_DOW_Msk                                       (0x07UL << RTC_DOW_DOW_Pos)                               /*!< RTC DOW: DOW Mask                   */
+
+// -----------------------------------------  RTC_DOY  --------------------------------------------
+#define RTC_DOY_DOY_Pos                                       0                                                         /*!< RTC DOY: DOY Position               */
+#define RTC_DOY_DOY_Msk                                       (0x000001ffUL << RTC_DOY_DOY_Pos)                         /*!< RTC DOY: DOY Mask                   */
+
+// ----------------------------------------  RTC_MONTH  -------------------------------------------
+#define RTC_MONTH_MONTH_Pos                                   0                                                         /*!< RTC MONTH: MONTH Position           */
+#define RTC_MONTH_MONTH_Msk                                   (0x0fUL << RTC_MONTH_MONTH_Pos)                           /*!< RTC MONTH: MONTH Mask               */
+
+// ----------------------------------------  RTC_YEAR  --------------------------------------------
+#define RTC_YEAR_YEAR_Pos                                     0                                                         /*!< RTC YEAR: YEAR Position             */
+#define RTC_YEAR_YEAR_Msk                                     (0x00000fffUL << RTC_YEAR_YEAR_Pos)                       /*!< RTC YEAR: YEAR Mask                 */
+
+// -------------------------------------  RTC_CALIBRATION  ----------------------------------------
+#define RTC_CALIBRATION_CALVAL_Pos                            0                                                         /*!< RTC CALIBRATION: CALVAL Position    */
+#define RTC_CALIBRATION_CALVAL_Msk                            (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos)              /*!< RTC CALIBRATION: CALVAL Mask        */
+#define RTC_CALIBRATION_CALDIR_Pos                            17                                                        /*!< RTC CALIBRATION: CALDIR Position    */
+#define RTC_CALIBRATION_CALDIR_Msk                            (0x01UL << RTC_CALIBRATION_CALDIR_Pos)                    /*!< RTC CALIBRATION: CALDIR Mask        */
+
+// ----------------------------------------  RTC_ASEC  --------------------------------------------
+#define RTC_ASEC_SECONDS_Pos                                  0                                                         /*!< RTC ASEC: SECONDS Position          */
+#define RTC_ASEC_SECONDS_Msk                                  (0x3fUL << RTC_ASEC_SECONDS_Pos)                          /*!< RTC ASEC: SECONDS Mask              */
+
+// ----------------------------------------  RTC_AMIN  --------------------------------------------
+#define RTC_AMIN_MINUTES_Pos                                  0                                                         /*!< RTC AMIN: MINUTES Position          */
+#define RTC_AMIN_MINUTES_Msk                                  (0x3fUL << RTC_AMIN_MINUTES_Pos)                          /*!< RTC AMIN: MINUTES Mask              */
+
+// ----------------------------------------  RTC_AHRS  --------------------------------------------
+#define RTC_AHRS_HOURS_Pos                                    0                                                         /*!< RTC AHRS: HOURS Position            */
+#define RTC_AHRS_HOURS_Msk                                    (0x1fUL << RTC_AHRS_HOURS_Pos)                            /*!< RTC AHRS: HOURS Mask                */
+
+// ----------------------------------------  RTC_ADOM  --------------------------------------------
+#define RTC_ADOM_DOM_Pos                                      0                                                         /*!< RTC ADOM: DOM Position              */
+#define RTC_ADOM_DOM_Msk                                      (0x1fUL << RTC_ADOM_DOM_Pos)                              /*!< RTC ADOM: DOM Mask                  */
+
+// ----------------------------------------  RTC_ADOW  --------------------------------------------
+#define RTC_ADOW_DOW_Pos                                      0                                                         /*!< RTC ADOW: DOW Position              */
+#define RTC_ADOW_DOW_Msk                                      (0x07UL << RTC_ADOW_DOW_Pos)                              /*!< RTC ADOW: DOW Mask                  */
+
+// ----------------------------------------  RTC_ADOY  --------------------------------------------
+#define RTC_ADOY_DOY_Pos                                      0                                                         /*!< RTC ADOY: DOY Position              */
+#define RTC_ADOY_DOY_Msk                                      (0x000001ffUL << RTC_ADOY_DOY_Pos)                        /*!< RTC ADOY: DOY Mask                  */
+
+// ----------------------------------------  RTC_AMON  --------------------------------------------
+#define RTC_AMON_MONTH_Pos                                    0                                                         /*!< RTC AMON: MONTH Position            */
+#define RTC_AMON_MONTH_Msk                                    (0x0fUL << RTC_AMON_MONTH_Pos)                            /*!< RTC AMON: MONTH Mask                */
+
+// ----------------------------------------  RTC_AYRS  --------------------------------------------
+#define RTC_AYRS_YEAR_Pos                                     0                                                         /*!< RTC AYRS: YEAR Position             */
+#define RTC_AYRS_YEAR_Msk                                     (0x00000fffUL << RTC_AYRS_YEAR_Pos)                       /*!< RTC AYRS: YEAR Mask                 */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  CGU Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------  CGU_FREQ_MON  ------------------------------------------
+#define CGU_FREQ_MON_RCNT_Pos                                 0                                                         /*!< CGU FREQ_MON: RCNT Position         */
+#define CGU_FREQ_MON_RCNT_Msk                                 (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos)                   /*!< CGU FREQ_MON: RCNT Mask             */
+#define CGU_FREQ_MON_FCNT_Pos                                 9                                                         /*!< CGU FREQ_MON: FCNT Position         */
+#define CGU_FREQ_MON_FCNT_Msk                                 (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos)                   /*!< CGU FREQ_MON: FCNT Mask             */
+#define CGU_FREQ_MON_MEAS_Pos                                 23                                                        /*!< CGU FREQ_MON: MEAS Position         */
+#define CGU_FREQ_MON_MEAS_Msk                                 (0x01UL << CGU_FREQ_MON_MEAS_Pos)                         /*!< CGU FREQ_MON: MEAS Mask             */
+#define CGU_FREQ_MON_CLK_SEL_Pos                              24                                                        /*!< CGU FREQ_MON: CLK_SEL Position      */
+#define CGU_FREQ_MON_CLK_SEL_Msk                              (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos)                      /*!< CGU FREQ_MON: CLK_SEL Mask          */
+
+// ------------------------------------  CGU_XTAL_OSC_CTRL  ---------------------------------------
+#define CGU_XTAL_OSC_CTRL_ENABLE_Pos                          0                                                         /*!< CGU XTAL_OSC_CTRL: ENABLE Position  */
+#define CGU_XTAL_OSC_CTRL_ENABLE_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos)                  /*!< CGU XTAL_OSC_CTRL: ENABLE Mask      */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Pos                          1                                                         /*!< CGU XTAL_OSC_CTRL: BYPASS Position  */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos)                  /*!< CGU XTAL_OSC_CTRL: BYPASS Mask      */
+#define CGU_XTAL_OSC_CTRL_HF_Pos                              2                                                         /*!< CGU XTAL_OSC_CTRL: HF Position      */
+#define CGU_XTAL_OSC_CTRL_HF_Msk                              (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos)                      /*!< CGU XTAL_OSC_CTRL: HF Mask          */
+
+// ------------------------------------  CGU_PLL0USB_STAT  ----------------------------------------
+#define CGU_PLL0USB_STAT_LOCK_Pos                             0                                                         /*!< CGU PLL0USB_STAT: LOCK Position     */
+#define CGU_PLL0USB_STAT_LOCK_Msk                             (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos)                     /*!< CGU PLL0USB_STAT: LOCK Mask         */
+#define CGU_PLL0USB_STAT_FR_Pos                               1                                                         /*!< CGU PLL0USB_STAT: FR Position       */
+#define CGU_PLL0USB_STAT_FR_Msk                               (0x01UL << CGU_PLL0USB_STAT_FR_Pos)                       /*!< CGU PLL0USB_STAT: FR Mask           */
+
+// ------------------------------------  CGU_PLL0USB_CTRL  ----------------------------------------
+#define CGU_PLL0USB_CTRL_PD_Pos                               0                                                         /*!< CGU PLL0USB_CTRL: PD Position       */
+#define CGU_PLL0USB_CTRL_PD_Msk                               (0x01UL << CGU_PLL0USB_CTRL_PD_Pos)                       /*!< CGU PLL0USB_CTRL: PD Mask           */
+#define CGU_PLL0USB_CTRL_BYPASS_Pos                           1                                                         /*!< CGU PLL0USB_CTRL: BYPASS Position   */
+#define CGU_PLL0USB_CTRL_BYPASS_Msk                           (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos)                   /*!< CGU PLL0USB_CTRL: BYPASS Mask       */
+#define CGU_PLL0USB_CTRL_DIRECTI_Pos                          2                                                         /*!< CGU PLL0USB_CTRL: DIRECTI Position  */
+#define CGU_PLL0USB_CTRL_DIRECTI_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTI Mask      */
+#define CGU_PLL0USB_CTRL_DIRECTO_Pos                          3                                                         /*!< CGU PLL0USB_CTRL: DIRECTO Position  */
+#define CGU_PLL0USB_CTRL_DIRECTO_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTO Mask      */
+#define CGU_PLL0USB_CTRL_CLKEN_Pos                            4                                                         /*!< CGU PLL0USB_CTRL: CLKEN Position    */
+#define CGU_PLL0USB_CTRL_CLKEN_Msk                            (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos)                    /*!< CGU PLL0USB_CTRL: CLKEN Mask        */
+#define CGU_PLL0USB_CTRL_FRM_Pos                              6                                                         /*!< CGU PLL0USB_CTRL: FRM Position      */
+#define CGU_PLL0USB_CTRL_FRM_Msk                              (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos)                      /*!< CGU PLL0USB_CTRL: FRM Mask          */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos                        11                                                        /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk                        (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos)                /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask    */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Pos                          24                                                        /*!< CGU PLL0USB_CTRL: CLK_SEL Position  */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Msk                          (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos)                  /*!< CGU PLL0USB_CTRL: CLK_SEL Mask      */
+
+// ------------------------------------  CGU_PLL0USB_MDIV  ----------------------------------------
+#define CGU_PLL0USB_MDIV_MDEC_Pos                             0                                                         /*!< CGU PLL0USB_MDIV: MDEC Position     */
+#define CGU_PLL0USB_MDIV_MDEC_Msk                             (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos)               /*!< CGU PLL0USB_MDIV: MDEC Mask         */
+#define CGU_PLL0USB_MDIV_SELP_Pos                             17                                                        /*!< CGU PLL0USB_MDIV: SELP Position     */
+#define CGU_PLL0USB_MDIV_SELP_Msk                             (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos)                     /*!< CGU PLL0USB_MDIV: SELP Mask         */
+#define CGU_PLL0USB_MDIV_SELI_Pos                             22                                                        /*!< CGU PLL0USB_MDIV: SELI Position     */
+#define CGU_PLL0USB_MDIV_SELI_Msk                             (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos)                     /*!< CGU PLL0USB_MDIV: SELI Mask         */
+#define CGU_PLL0USB_MDIV_SELR_Pos                             28                                                        /*!< CGU PLL0USB_MDIV: SELR Position     */
+#define CGU_PLL0USB_MDIV_SELR_Msk                             (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos)                     /*!< CGU PLL0USB_MDIV: SELR Mask         */
+
+// -----------------------------------  CGU_PLL0USB_NP_DIV  ---------------------------------------
+#define CGU_PLL0USB_NP_DIV_PDEC_Pos                           0                                                         /*!< CGU PLL0USB_NP_DIV: PDEC Position   */
+#define CGU_PLL0USB_NP_DIV_PDEC_Msk                           (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos)                   /*!< CGU PLL0USB_NP_DIV: PDEC Mask       */
+#define CGU_PLL0USB_NP_DIV_NDEC_Pos                           12                                                        /*!< CGU PLL0USB_NP_DIV: NDEC Position   */
+#define CGU_PLL0USB_NP_DIV_NDEC_Msk                           (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos)             /*!< CGU PLL0USB_NP_DIV: NDEC Mask       */
+
+// -----------------------------------  CGU_PLL0AUDIO_STAT  ---------------------------------------
+#define CGU_PLL0AUDIO_STAT_LOCK_Pos                           0                                                         /*!< CGU PLL0AUDIO_STAT: LOCK Position   */
+#define CGU_PLL0AUDIO_STAT_LOCK_Msk                           (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos)                   /*!< CGU PLL0AUDIO_STAT: LOCK Mask       */
+#define CGU_PLL0AUDIO_STAT_FR_Pos                             1                                                         /*!< CGU PLL0AUDIO_STAT: FR Position     */
+#define CGU_PLL0AUDIO_STAT_FR_Msk                             (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos)                     /*!< CGU PLL0AUDIO_STAT: FR Mask         */
+
+// -----------------------------------  CGU_PLL0AUDIO_CTRL  ---------------------------------------
+#define CGU_PLL0AUDIO_CTRL_PD_Pos                             0                                                         /*!< CGU PLL0AUDIO_CTRL: PD Position     */
+#define CGU_PLL0AUDIO_CTRL_PD_Msk                             (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos)                     /*!< CGU PLL0AUDIO_CTRL: PD Mask         */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos                         1                                                         /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos)                 /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask     */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos                        2                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask    */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos                        3                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask    */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos                          4                                                         /*!< CGU PLL0AUDIO_CTRL: CLKEN Position  */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk                          (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos)                  /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask      */
+#define CGU_PLL0AUDIO_CTRL_FRM_Pos                            6                                                         /*!< CGU PLL0AUDIO_CTRL: FRM Position    */
+#define CGU_PLL0AUDIO_CTRL_FRM_Msk                            (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos)                    /*!< CGU PLL0AUDIO_CTRL: FRM Mask        */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos                      11                                                        /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk                      (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos)              /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask  */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos                    12                                                        /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk                    (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos)            /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos                        13                                                        /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos)                /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask    */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos                         14                                                        /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos)                 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask     */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos                        24                                                        /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk                        (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos)                /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_PLL0AUDIO_MDIV  ---------------------------------------
+#define CGU_PLL0AUDIO_MDIV_MDEC_Pos                           0                                                         /*!< CGU PLL0AUDIO_MDIV: MDEC Position   */
+#define CGU_PLL0AUDIO_MDIV_MDEC_Msk                           (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos)             /*!< CGU PLL0AUDIO_MDIV: MDEC Mask       */
+
+// ----------------------------------  CGU_PLL0AUDIO_NP_DIV  --------------------------------------
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos                         0                                                         /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk                         (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos)                 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask     */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos                         12                                                        /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk                         (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos)           /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask     */
+
+// -----------------------------------  CGU_PLL0AUDIO_FRAC  ---------------------------------------
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos                  0                                                         /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk                  (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos)    /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */
+
+// --------------------------------------  CGU_PLL1_STAT  -----------------------------------------
+#define CGU_PLL1_STAT_LOCK_Pos                                0                                                         /*!< CGU PLL1_STAT: LOCK Position        */
+#define CGU_PLL1_STAT_LOCK_Msk                                (0x01UL << CGU_PLL1_STAT_LOCK_Pos)                        /*!< CGU PLL1_STAT: LOCK Mask            */
+
+// --------------------------------------  CGU_PLL1_CTRL  -----------------------------------------
+#define CGU_PLL1_CTRL_PD_Pos                                  0                                                         /*!< CGU PLL1_CTRL: PD Position          */
+#define CGU_PLL1_CTRL_PD_Msk                                  (0x01UL << CGU_PLL1_CTRL_PD_Pos)                          /*!< CGU PLL1_CTRL: PD Mask              */
+#define CGU_PLL1_CTRL_BYPASS_Pos                              1                                                         /*!< CGU PLL1_CTRL: BYPASS Position      */
+#define CGU_PLL1_CTRL_BYPASS_Msk                              (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos)                      /*!< CGU PLL1_CTRL: BYPASS Mask          */
+#define CGU_PLL1_CTRL_FBSEL_Pos                               6                                                         /*!< CGU PLL1_CTRL: FBSEL Position       */
+#define CGU_PLL1_CTRL_FBSEL_Msk                               (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos)                       /*!< CGU PLL1_CTRL: FBSEL Mask           */
+#define CGU_PLL1_CTRL_DIRECT_Pos                              7                                                         /*!< CGU PLL1_CTRL: DIRECT Position      */
+#define CGU_PLL1_CTRL_DIRECT_Msk                              (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos)                      /*!< CGU PLL1_CTRL: DIRECT Mask          */
+#define CGU_PLL1_CTRL_PSEL_Pos                                8                                                         /*!< CGU PLL1_CTRL: PSEL Position        */
+#define CGU_PLL1_CTRL_PSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_PSEL_Pos)                        /*!< CGU PLL1_CTRL: PSEL Mask            */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Pos                           11                                                        /*!< CGU PLL1_CTRL: AUTOBLOCK Position   */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Msk                           (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos)                   /*!< CGU PLL1_CTRL: AUTOBLOCK Mask       */
+#define CGU_PLL1_CTRL_NSEL_Pos                                12                                                        /*!< CGU PLL1_CTRL: NSEL Position        */
+#define CGU_PLL1_CTRL_NSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_NSEL_Pos)                        /*!< CGU PLL1_CTRL: NSEL Mask            */
+#define CGU_PLL1_CTRL_MSEL_Pos                                16                                                        /*!< CGU PLL1_CTRL: MSEL Position        */
+#define CGU_PLL1_CTRL_MSEL_Msk                                (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos)                  /*!< CGU PLL1_CTRL: MSEL Mask            */
+#define CGU_PLL1_CTRL_CLK_SEL_Pos                             24                                                        /*!< CGU PLL1_CTRL: CLK_SEL Position     */
+#define CGU_PLL1_CTRL_CLK_SEL_Msk                             (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos)                     /*!< CGU PLL1_CTRL: CLK_SEL Mask         */
+
+// -------------------------------------  CGU_IDIVA_CTRL  -----------------------------------------
+#define CGU_IDIVA_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVA_CTRL: PD Position         */
+#define CGU_IDIVA_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVA_CTRL_PD_Pos)                         /*!< CGU IDIVA_CTRL: PD Mask             */
+#define CGU_IDIVA_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVA_CTRL: IDIV Position       */
+#define CGU_IDIVA_CTRL_IDIV_Msk                               (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos)                       /*!< CGU IDIVA_CTRL: IDIV Mask           */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVA_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVA_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVA_CTRL: CLK_SEL Position    */
+#define CGU_IDIVA_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVA_CTRL: CLK_SEL Mask        */
+
+// -------------------------------------  CGU_IDIVB_CTRL  -----------------------------------------
+#define CGU_IDIVB_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVB_CTRL: PD Position         */
+#define CGU_IDIVB_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVB_CTRL_PD_Pos)                         /*!< CGU IDIVB_CTRL: PD Mask             */
+#define CGU_IDIVB_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVB_CTRL: IDIV Position       */
+#define CGU_IDIVB_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos)                       /*!< CGU IDIVB_CTRL: IDIV Mask           */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVB_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVB_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVB_CTRL: CLK_SEL Position    */
+#define CGU_IDIVB_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVB_CTRL: CLK_SEL Mask        */
+
+// -------------------------------------  CGU_IDIVE_CTRL  -----------------------------------------
+#define CGU_IDIVE_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVE_CTRL: PD Position         */
+#define CGU_IDIVE_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVE_CTRL_PD_Pos)                         /*!< CGU IDIVE_CTRL: PD Mask             */
+#define CGU_IDIVE_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVE_CTRL: IDIV Position       */
+#define CGU_IDIVE_CTRL_IDIV_Msk                               (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos)                 /*!< CGU IDIVE_CTRL: IDIV Mask           */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVE_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVE_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVE_CTRL: CLK_SEL Position    */
+#define CGU_IDIVE_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVE_CTRL: CLK_SEL Mask        */
+
+// ------------------------------------  CGU_BASE_SAFE_CLK  ---------------------------------------
+#define CGU_BASE_SAFE_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SAFE_CLK: PD Position      */
+#define CGU_BASE_SAFE_CLK_PD_Msk                              (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos)                      /*!< CGU BASE_SAFE_CLK: PD Mask          */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_USB0_CLK  ---------------------------------------
+#define CGU_BASE_USB0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB0_CLK: PD Position      */
+#define CGU_BASE_USB0_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB0_CLK_PD_Pos)                      /*!< CGU BASE_USB0_CLK: PD Mask          */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB0_CLK: CLK_SEL Position */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB0_CLK: CLK_SEL Mask     */
+
+// -----------------------------------  CGU_BASE_PERIPH_CLK  --------------------------------------
+#define CGU_BASE_PERIPH_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PERIPH_CLK: PD Position    */
+#define CGU_BASE_PERIPH_CLK_PD_Msk                            (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos)                    /*!< CGU BASE_PERIPH_CLK: PD Mask        */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask   */
+
+// ------------------------------------  CGU_BASE_USB1_CLK  ---------------------------------------
+#define CGU_BASE_USB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB1_CLK: PD Position      */
+#define CGU_BASE_USB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB1_CLK_PD_Pos)                      /*!< CGU BASE_USB1_CLK: PD Mask          */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB1_CLK: CLK_SEL Position */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB1_CLK: CLK_SEL Mask     */
+
+// -------------------------------------  CGU_BASE_M4_CLK  ----------------------------------------
+#define CGU_BASE_M4_CLK_PD_Pos                                0                                                         /*!< CGU BASE_M4_CLK: PD Position        */
+#define CGU_BASE_M4_CLK_PD_Msk                                (0x01UL << CGU_BASE_M4_CLK_PD_Pos)                        /*!< CGU BASE_M4_CLK: PD Mask            */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos                         11                                                        /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk                         (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos)                 /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask     */
+#define CGU_BASE_M4_CLK_CLK_SEL_Pos                           24                                                        /*!< CGU BASE_M4_CLK: CLK_SEL Position   */
+#define CGU_BASE_M4_CLK_CLK_SEL_Msk                           (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos)                   /*!< CGU BASE_M4_CLK: CLK_SEL Mask       */
+
+// -----------------------------------  CGU_BASE_SPIFI_CLK  ---------------------------------------
+#define CGU_BASE_SPIFI_CLK_PD_Pos                             0                                                         /*!< CGU BASE_SPIFI_CLK: PD Position     */
+#define CGU_BASE_SPIFI_CLK_PD_Msk                             (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos)                     /*!< CGU BASE_SPIFI_CLK: PD Mask         */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos)                /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask    */
+
+// ------------------------------------  CGU_BASE_SPI_CLK  ----------------------------------------
+#define CGU_BASE_SPI_CLK_PD_Pos                               0                                                         /*!< CGU BASE_SPI_CLK: PD Position       */
+#define CGU_BASE_SPI_CLK_PD_Msk                               (0x01UL << CGU_BASE_SPI_CLK_PD_Pos)                       /*!< CGU BASE_SPI_CLK: PD Mask           */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask    */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_SPI_CLK: CLK_SEL Position  */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_SPI_CLK: CLK_SEL Mask      */
+
+// -----------------------------------  CGU_BASE_PHY_RX_CLK  --------------------------------------
+#define CGU_BASE_PHY_RX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_RX_CLK: PD Position    */
+#define CGU_BASE_PHY_RX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_RX_CLK: PD Mask        */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask   */
+
+// -----------------------------------  CGU_BASE_PHY_TX_CLK  --------------------------------------
+#define CGU_BASE_PHY_TX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_TX_CLK: PD Position    */
+#define CGU_BASE_PHY_TX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_TX_CLK: PD Mask        */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask   */
+
+// ------------------------------------  CGU_BASE_APB1_CLK  ---------------------------------------
+#define CGU_BASE_APB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB1_CLK: PD Position      */
+#define CGU_BASE_APB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB1_CLK_PD_Pos)                      /*!< CGU BASE_APB1_CLK: PD Mask          */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB1_CLK: CLK_SEL Position */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB1_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_APB3_CLK  ---------------------------------------
+#define CGU_BASE_APB3_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB3_CLK: PD Position      */
+#define CGU_BASE_APB3_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB3_CLK_PD_Pos)                      /*!< CGU BASE_APB3_CLK: PD Mask          */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB3_CLK: CLK_SEL Position */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB3_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_LCD_CLK  ----------------------------------------
+#define CGU_BASE_LCD_CLK_PD_Pos                               0                                                         /*!< CGU BASE_LCD_CLK: PD Position       */
+#define CGU_BASE_LCD_CLK_PD_Msk                               (0x01UL << CGU_BASE_LCD_CLK_PD_Pos)                       /*!< CGU BASE_LCD_CLK: PD Mask           */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask    */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_LCD_CLK: CLK_SEL Position  */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_LCD_CLK: CLK_SEL Mask      */
+
+// ------------------------------------  CGU_BASE_SDIO_CLK  ---------------------------------------
+#define CGU_BASE_SDIO_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SDIO_CLK: PD Position      */
+#define CGU_BASE_SDIO_CLK_PD_Msk                              (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos)                      /*!< CGU BASE_SDIO_CLK: PD Mask          */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_SSP0_CLK  ---------------------------------------
+#define CGU_BASE_SSP0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP0_CLK: PD Position      */
+#define CGU_BASE_SSP0_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos)                      /*!< CGU BASE_SSP0_CLK: PD Mask          */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_SSP1_CLK  ---------------------------------------
+#define CGU_BASE_SSP1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP1_CLK: PD Position      */
+#define CGU_BASE_SSP1_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos)                      /*!< CGU BASE_SSP1_CLK: PD Mask          */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask     */
+
+// -----------------------------------  CGU_BASE_UART0_CLK  ---------------------------------------
+#define CGU_BASE_UART0_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART0_CLK: PD Position     */
+#define CGU_BASE_UART0_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART0_CLK_PD_Pos)                     /*!< CGU BASE_UART0_CLK: PD Mask         */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART0_CLK: CLK_SEL Position */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART0_CLK: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_BASE_UART1_CLK  ---------------------------------------
+#define CGU_BASE_UART1_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART1_CLK: PD Position     */
+#define CGU_BASE_UART1_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART1_CLK_PD_Pos)                     /*!< CGU BASE_UART1_CLK: PD Mask         */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART1_CLK: CLK_SEL Position */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART1_CLK: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_BASE_UART2_CLK  ---------------------------------------
+#define CGU_BASE_UART2_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART2_CLK: PD Position     */
+#define CGU_BASE_UART2_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART2_CLK_PD_Pos)                     /*!< CGU BASE_UART2_CLK: PD Mask         */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART2_CLK: CLK_SEL Position */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART2_CLK: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_BASE_UART3_CLK  ---------------------------------------
+#define CGU_BASE_UART3_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART3_CLK: PD Position     */
+#define CGU_BASE_UART3_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART3_CLK_PD_Pos)                     /*!< CGU BASE_UART3_CLK: PD Mask         */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART3_CLK: CLK_SEL Position */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART3_CLK: CLK_SEL Mask    */
+
+// ------------------------------------  CGU_BASE_OUT_CLK  ----------------------------------------
+#define CGU_BASE_OUT_CLK_PD_Pos                               0                                                         /*!< CGU BASE_OUT_CLK: PD Position       */
+#define CGU_BASE_OUT_CLK_PD_Msk                               (0x01UL << CGU_BASE_OUT_CLK_PD_Pos)                       /*!< CGU BASE_OUT_CLK: PD Mask           */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask    */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_OUT_CLK: CLK_SEL Position  */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_OUT_CLK: CLK_SEL Mask      */
+
+// ------------------------------------  CGU_BASE_APLL_CLK  ---------------------------------------
+#define CGU_BASE_APLL_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APLL_CLK: PD Position      */
+#define CGU_BASE_APLL_CLK_PD_Msk                              (0x01UL << CGU_BASE_APLL_CLK_PD_Pos)                      /*!< CGU BASE_APLL_CLK: PD Mask          */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APLL_CLK: CLK_SEL Position */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APLL_CLK: CLK_SEL Mask     */
+
+// ----------------------------------  CGU_BASE_CGU_OUT0_CLK  -------------------------------------
+#define CGU_BASE_CGU_OUT0_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT0_CLK: PD Position  */
+#define CGU_BASE_CGU_OUT0_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT0_CLK: PD Mask      */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */
+
+// ----------------------------------  CGU_BASE_CGU_OUT1_CLK  -------------------------------------
+#define CGU_BASE_CGU_OUT1_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT1_CLK: PD Position  */
+#define CGU_BASE_CGU_OUT1_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT1_CLK: PD Mask      */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */
+
+// -------------------------------------  CGU_IDIVC_CTRL  -----------------------------------------
+#define CGU_IDIVC_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVC_CTRL: PD Position         */
+#define CGU_IDIVC_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVC_CTRL_PD_Pos)                         /*!< CGU IDIVC_CTRL: PD Mask             */
+#define CGU_IDIVC_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVC_CTRL: IDIV Position       */
+#define CGU_IDIVC_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos)                       /*!< CGU IDIVC_CTRL: IDIV Mask           */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVC_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVC_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVC_CTRL: CLK_SEL Position    */
+#define CGU_IDIVC_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVC_CTRL: CLK_SEL Mask        */
+
+// -------------------------------------  CGU_IDIVD_CTRL  -----------------------------------------
+#define CGU_IDIVD_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVD_CTRL: PD Position         */
+#define CGU_IDIVD_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVD_CTRL_PD_Pos)                         /*!< CGU IDIVD_CTRL: PD Mask             */
+#define CGU_IDIVD_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVD_CTRL: IDIV Position       */
+#define CGU_IDIVD_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos)                       /*!< CGU IDIVD_CTRL: IDIV Mask           */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVD_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVD_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVD_CTRL: CLK_SEL Position    */
+#define CGU_IDIVD_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVD_CTRL: CLK_SEL Mask        */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 CCU1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  CCU1_PM  --------------------------------------------
+#define CCU1_PM_PD_Pos                                        0                                                         /*!< CCU1 PM: PD Position                */
+#define CCU1_PM_PD_Msk                                        (0x01UL << CCU1_PM_PD_Pos)                                /*!< CCU1 PM: PD Mask                    */
+
+// -------------------------------------  CCU1_BASE_STAT  -----------------------------------------
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos                  0                                                         /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos                  1                                                         /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos                 2                                                         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk                 (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos)         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos                    3                                                         /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk                    (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos)            /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos                  7                                                         /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos                  8                                                         /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */
+
+// ----------------------------------  CCU1_CLK_APB3_BUS_CFG  -------------------------------------
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask     */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask    */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB3_BUS_STAT  -------------------------------------
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask    */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask   */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_I2C1_CFG  -------------------------------------
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_I2C1_STAT  ------------------------------------
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_APB3_DAC_CFG  -------------------------------------
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask     */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask    */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB3_DAC_STAT  -------------------------------------
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask    */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask   */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC0_CFG  -------------------------------------
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC0_STAT  ------------------------------------
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC1_CFG  -------------------------------------
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC1_STAT  ------------------------------------
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_CAN0_CFG  -------------------------------------
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_CAN0_STAT  ------------------------------------
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_APB1_BUS_CFG  -------------------------------------
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask     */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask    */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB1_BUS_STAT  -------------------------------------
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask    */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask   */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */
+
+// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_CFG  ----------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos                  0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk                  (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos)          /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos                 1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos               2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk               (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos)       /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */
+
+// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_STAT  ---------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos                 0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos                1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk                (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos)        /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos              2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk              (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos)      /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_ABP1_I2C0_CFG  -------------------------------------
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos)                /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask    */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos)               /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask   */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB1_I2C0_STAT  ------------------------------------
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask   */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask  */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_APB1_I2S_CFG  -------------------------------------
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask     */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask    */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB1_I2S_STAT  -------------------------------------
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask    */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask   */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB1_CAN1_CFG  -------------------------------------
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask    */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask   */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB1_CAN1_STAT  ------------------------------------
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask   */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask  */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */
+
+// -----------------------------------  CCU1_CLK_SPIFI_CFG  ---------------------------------------
+#define CCU1_CLK_SPIFI_CFG_RUN_Pos                            0                                                         /*!< CCU1 CLK_SPIFI_CFG: RUN Position    */
+#define CCU1_CLK_SPIFI_CFG_RUN_Msk                            (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos)                    /*!< CCU1 CLK_SPIFI_CFG: RUN Mask        */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Pos                           1                                                         /*!< CCU1 CLK_SPIFI_CFG: AUTO Position   */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Msk                           (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos)                   /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask       */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk                         (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos)                 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask     */
+
+// -----------------------------------  CCU1_CLK_SPIFI_STAT  --------------------------------------
+#define CCU1_CLK_SPIFI_STAT_RUN_Pos                           0                                                         /*!< CCU1 CLK_SPIFI_STAT: RUN Position   */
+#define CCU1_CLK_SPIFI_STAT_RUN_Msk                           (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos)                   /*!< CCU1 CLK_SPIFI_STAT: RUN Mask       */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Pos                          1                                                         /*!< CCU1 CLK_SPIFI_STAT: AUTO Position  */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Msk                          (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos)                  /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask      */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk                        (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos)                /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask    */
+
+// -----------------------------------  CCU1_CLK_M4_BUS_CFG  --------------------------------------
+#define CCU1_CLK_M4_BUS_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_BUS_CFG: RUN Position   */
+#define CCU1_CLK_M4_BUS_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask       */
+#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position  */
+#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_BUS_STAT  --------------------------------------
+#define CCU1_CLK_M4_BUS_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_BUS_STAT: RUN Position  */
+#define CCU1_CLK_M4_BUS_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask      */
+#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */
+#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SPIFI_CFG  -------------------------------------
+#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */
+#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask     */
+#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */
+#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask    */
+#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_SPIFI_STAT  -------------------------------------
+#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */
+#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask    */
+#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */
+#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask   */
+#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_GPIO_CFG  --------------------------------------
+#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position  */
+#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask      */
+#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */
+#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_GPIO_STAT  -------------------------------------
+#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */
+#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask     */
+#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */
+#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_LCD_CFG  --------------------------------------
+#define CCU1_CLK_M4_LCD_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_LCD_CFG: RUN Position   */
+#define CCU1_CLK_M4_LCD_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask       */
+#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position  */
+#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_LCD_STAT  --------------------------------------
+#define CCU1_CLK_M4_LCD_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_LCD_STAT: RUN Position  */
+#define CCU1_CLK_M4_LCD_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask      */
+#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */
+#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask   */
+
+// --------------------------------  CCU1_CLK_M4_ETHERNET_CFG  ------------------------------------
+#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos)              /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask  */
+#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos)             /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */
+#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_M4_ETHERNET_STAT  -----------------------------------
+#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos)             /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */
+#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos)            /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */
+#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_USB0_CFG  --------------------------------------
+#define CCU1_CLK_M4_USB0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB0_CFG: RUN Position  */
+#define CCU1_CLK_M4_USB0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask      */
+#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */
+#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_USB0_STAT  -------------------------------------
+#define CCU1_CLK_M4_USB0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */
+#define CCU1_CLK_M4_USB0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask     */
+#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */
+#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_EMC_CFG  --------------------------------------
+#define CCU1_CLK_M4_EMC_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_EMC_CFG: RUN Position   */
+#define CCU1_CLK_M4_EMC_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask       */
+#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position  */
+#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_EMC_STAT  --------------------------------------
+#define CCU1_CLK_M4_EMC_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_EMC_STAT: RUN Position  */
+#define CCU1_CLK_M4_EMC_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask      */
+#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */
+#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SDIO_CFG  --------------------------------------
+#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position  */
+#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask      */
+#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */
+#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SDIO_STAT  -------------------------------------
+#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */
+#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask     */
+#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */
+#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_DMA_CFG  --------------------------------------
+#define CCU1_CLK_M4_DMA_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_DMA_CFG: RUN Position   */
+#define CCU1_CLK_M4_DMA_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask       */
+#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position  */
+#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_DMA_STAT  --------------------------------------
+#define CCU1_CLK_M4_DMA_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_DMA_STAT: RUN Position  */
+#define CCU1_CLK_M4_DMA_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask      */
+#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */
+#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask   */
+
+// ---------------------------------  CCU1_CLK_M4_M4CORE_CFG  -------------------------------------
+#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */
+#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask    */
+#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */
+#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_M3CORE_STAT  ------------------------------------
+#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Position */
+#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Mask   */
+#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Position */
+#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Mask */
+
+// -----------------------------------  CCU1_CLK_M4_SCT_CFG  --------------------------------------
+#define CCU1_CLK_M4_SCT_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCT_CFG: RUN Position   */
+#define CCU1_CLK_M4_SCT_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask       */
+#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position  */
+#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_SCT_STAT  --------------------------------------
+#define CCU1_CLK_M4_SCT_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCT_STAT: RUN Position  */
+#define CCU1_CLK_M4_SCT_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask      */
+#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */
+#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_USB1_CFG  --------------------------------------
+#define CCU1_CLK_M4_USB1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB1_CFG: RUN Position  */
+#define CCU1_CLK_M4_USB1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask      */
+#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */
+#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_USB1_STAT  -------------------------------------
+#define CCU1_CLK_M4_USB1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */
+#define CCU1_CLK_M4_USB1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask     */
+#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */
+#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_EMCDIV_CFG  -------------------------------------
+#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask    */
+#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_EMCDIV_STAT  ------------------------------------
+#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask   */
+#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_M0APP_CFG  -------------------------------------
+#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */
+#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask     */
+#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */
+#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask    */
+#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_M0APP_STAT  -------------------------------------
+#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */
+#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask    */
+#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */
+#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask   */
+#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_WWDT_CFG  --------------------------------------
+#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position  */
+#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask      */
+#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */
+#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_WWDT_STAT  -------------------------------------
+#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */
+#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask     */
+#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */
+#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_USART0_CFG  -------------------------------------
+#define CCU1_CLK_M4_USART0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */
+#define CCU1_CLK_M4_USART0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask    */
+#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART0_STAT  ------------------------------------
+#define CCU1_CLK_M4_USART0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */
+#define CCU1_CLK_M4_USART0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask   */
+#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_UART1_CFG  -------------------------------------
+#define CCU1_CLK_M4_UART1_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */
+#define CCU1_CLK_M4_UART1_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask     */
+#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */
+#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask    */
+#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_UART1_STAT  -------------------------------------
+#define CCU1_CLK_M4_UART1_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */
+#define CCU1_CLK_M4_UART1_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask    */
+#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */
+#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask   */
+#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_SSP0_CFG  --------------------------------------
+#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position  */
+#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask      */
+#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */
+#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SSP0_STAT  -------------------------------------
+#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */
+#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask     */
+#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */
+#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER0_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER0_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER1_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER1_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */
+
+// -----------------------------------  CCU1_CLK_M4_SCU_CFG  --------------------------------------
+#define CCU1_CLK_M4_SCU_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCU_CFG: RUN Position   */
+#define CCU1_CLK_M4_SCU_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask       */
+#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position  */
+#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_SCU_STAT  --------------------------------------
+#define CCU1_CLK_M4_SCU_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCU_STAT: RUN Position  */
+#define CCU1_CLK_M4_SCU_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask      */
+#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */
+#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_CREG_CFG  --------------------------------------
+#define CCU1_CLK_M4_CREG_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_CREG_CFG: RUN Position  */
+#define CCU1_CLK_M4_CREG_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask      */
+#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */
+#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_CREG_STAT  -------------------------------------
+#define CCU1_CLK_M4_CREG_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */
+#define CCU1_CLK_M4_CREG_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask     */
+#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */
+#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_RITIMER_CFG  ------------------------------------
+#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */
+#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos)               /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask   */
+#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */
+#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos)              /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask  */
+#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_M4_RITIMER_STAT  ------------------------------------
+#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */
+#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos)              /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask  */
+#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */
+#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos)             /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */
+#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART2_CFG  -------------------------------------
+#define CCU1_CLK_M4_USART2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */
+#define CCU1_CLK_M4_USART2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask    */
+#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART2_STAT  ------------------------------------
+#define CCU1_CLK_M4_USART2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */
+#define CCU1_CLK_M4_USART2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask   */
+#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART3_CFG  -------------------------------------
+#define CCU1_CLK_M4_USART3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */
+#define CCU1_CLK_M4_USART3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask    */
+#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART3_STAT  ------------------------------------
+#define CCU1_CLK_M4_USART3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */
+#define CCU1_CLK_M4_USART3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask   */
+#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER2_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER2_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER3_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER3_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_SSP1_CFG  --------------------------------------
+#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position  */
+#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask      */
+#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */
+#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SSP1_STAT  -------------------------------------
+#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */
+#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask     */
+#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */
+#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_QEI_CFG  --------------------------------------
+#define CCU1_CLK_M4_QEI_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_QEI_CFG: RUN Position   */
+#define CCU1_CLK_M4_QEI_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask       */
+#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position  */
+#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_QEI_STAT  --------------------------------------
+#define CCU1_CLK_M4_QEI_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_QEI_STAT: RUN Position  */
+#define CCU1_CLK_M4_QEI_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask      */
+#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */
+#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask   */
+
+// ---------------------------------  CCU1_CLK_PERIPH_BUS_CFG  ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos)               /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask   */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos)              /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask  */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_BUS_STAT  ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos)              /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask  */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_CORE_CFG  ------------------------------------
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos)              /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask  */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_CORE_STAT  -----------------------------------
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos)             /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_SGPIO_CFG  -----------------------------------
+#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos)             /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */
+
+// -------------------------------  CCU1_CLK_PERIPH_SGPIO_STAT  -----------------------------------
+#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos                    0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos                   1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk                   (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos)           /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos                 2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk                 (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos)         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */
+
+// ------------------------------------  CCU1_CLK_USB0_CFG  ---------------------------------------
+#define CCU1_CLK_USB0_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB0_CFG: RUN Position     */
+#define CCU1_CLK_USB0_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB0_CFG: RUN Mask         */
+#define CCU1_CLK_USB0_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB0_CFG: AUTO Position    */
+#define CCU1_CLK_USB0_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB0_CFG: AUTO Mask        */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB0_CFG: WAKEUP Position  */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU1_CLK_USB0_STAT  ---------------------------------------
+#define CCU1_CLK_USB0_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB0_STAT: RUN Position    */
+#define CCU1_CLK_USB0_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB0_STAT: RUN Mask        */
+#define CCU1_CLK_USB0_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB0_STAT: AUTO Position   */
+#define CCU1_CLK_USB0_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB0_STAT: AUTO Mask       */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask     */
+
+// ------------------------------------  CCU1_CLK_USB1_CFG  ---------------------------------------
+#define CCU1_CLK_USB1_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB1_CFG: RUN Position     */
+#define CCU1_CLK_USB1_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB1_CFG: RUN Mask         */
+#define CCU1_CLK_USB1_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB1_CFG: AUTO Position    */
+#define CCU1_CLK_USB1_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB1_CFG: AUTO Mask        */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB1_CFG: WAKEUP Position  */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU1_CLK_USB1_STAT  ---------------------------------------
+#define CCU1_CLK_USB1_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB1_STAT: RUN Position    */
+#define CCU1_CLK_USB1_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB1_STAT: RUN Mask        */
+#define CCU1_CLK_USB1_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB1_STAT: AUTO Position   */
+#define CCU1_CLK_USB1_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB1_STAT: AUTO Mask       */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask     */
+
+// ------------------------------------  CCU1_CLK_SPI_CFG  ----------------------------------------
+#define CCU1_CLK_SPI_CFG_RUN_Pos                              0                                                         /*!< CCU1 CLK_SPI_CFG: RUN Position      */
+#define CCU1_CLK_SPI_CFG_RUN_Msk                              (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos)                      /*!< CCU1 CLK_SPI_CFG: RUN Mask          */
+#define CCU1_CLK_SPI_CFG_AUTO_Pos                             1                                                         /*!< CCU1 CLK_SPI_CFG: AUTO Position     */
+#define CCU1_CLK_SPI_CFG_AUTO_Msk                             (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos)                     /*!< CCU1 CLK_SPI_CFG: AUTO Mask         */
+#define CCU1_CLK_SPI_CFG_WAKEUP_Pos                           2                                                         /*!< CCU1 CLK_SPI_CFG: WAKEUP Position   */
+#define CCU1_CLK_SPI_CFG_WAKEUP_Msk                           (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos)                   /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask       */
+
+// ------------------------------------  CCU1_CLK_SPI_STAT  ---------------------------------------
+#define CCU1_CLK_SPI_STAT_RUN_Pos                             0                                                         /*!< CCU1 CLK_SPI_STAT: RUN Position     */
+#define CCU1_CLK_SPI_STAT_RUN_Msk                             (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos)                     /*!< CCU1 CLK_SPI_STAT: RUN Mask         */
+#define CCU1_CLK_SPI_STAT_AUTO_Pos                            1                                                         /*!< CCU1 CLK_SPI_STAT: AUTO Position    */
+#define CCU1_CLK_SPI_STAT_AUTO_Msk                            (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos)                    /*!< CCU1 CLK_SPI_STAT: AUTO Mask        */
+#define CCU1_CLK_SPI_STAT_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_SPI_STAT: WAKEUP Position  */
+#define CCU1_CLK_SPI_STAT_WAKEUP_Msk                          (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos)                  /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask      */
+
+// ------------------------------------  CCU1_CLK_VADC_CFG  ---------------------------------------
+#define CCU1_CLK_VADC_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_VADC_CFG: RUN Position     */
+#define CCU1_CLK_VADC_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos)                     /*!< CCU1 CLK_VADC_CFG: RUN Mask         */
+#define CCU1_CLK_VADC_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_VADC_CFG: AUTO Position    */
+#define CCU1_CLK_VADC_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos)                    /*!< CCU1 CLK_VADC_CFG: AUTO Mask        */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_VADC_CFG: WAKEUP Position  */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU1_CLK_VADC_STAT  ---------------------------------------
+#define CCU1_CLK_VADC_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_VADC_STAT: RUN Position    */
+#define CCU1_CLK_VADC_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos)                    /*!< CCU1 CLK_VADC_STAT: RUN Mask        */
+#define CCU1_CLK_VADC_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_VADC_STAT: AUTO Position   */
+#define CCU1_CLK_VADC_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos)                   /*!< CCU1 CLK_VADC_STAT: AUTO Mask       */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 CCU2 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  CCU2_PM  --------------------------------------------
+#define CCU2_PM_PD_Pos                                        0                                                         /*!< CCU2 PM: PD Position                */
+#define CCU2_PM_PD_Msk                                        (0x01UL << CCU2_PM_PD_Pos)                                /*!< CCU2 PM: PD Mask                    */
+
+// -------------------------------------  CCU2_BASE_STAT  -----------------------------------------
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos                     1                                                         /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos                     2                                                         /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos                     3                                                         /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos                     4                                                         /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos                      5                                                         /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask  */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos                      6                                                         /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask  */
+
+// ------------------------------------  CCU2_CLK_APLL_CFG  ---------------------------------------
+#define CCU2_CLK_APLL_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_APLL_CFG: RUN Position     */
+#define CCU2_CLK_APLL_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos)                     /*!< CCU2 CLK_APLL_CFG: RUN Mask         */
+#define CCU2_CLK_APLL_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_APLL_CFG: AUTO Position    */
+#define CCU2_CLK_APLL_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos)                    /*!< CCU2 CLK_APLL_CFG: AUTO Mask        */
+#define CCU2_CLK_APLL_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_APLL_CFG: WAKEUP Position  */
+#define CCU2_CLK_APLL_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_APLL_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU2_CLK_APLL_STAT  ---------------------------------------
+#define CCU2_CLK_APLL_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_APLL_STAT: RUN Position    */
+#define CCU2_CLK_APLL_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos)                    /*!< CCU2 CLK_APLL_STAT: RUN Mask        */
+#define CCU2_CLK_APLL_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_APLL_STAT: AUTO Position   */
+#define CCU2_CLK_APLL_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos)                   /*!< CCU2 CLK_APLL_STAT: AUTO Mask       */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask     */
+
+// --------------------------------  CCU2_CLK_APB2_USART3_CFG  ------------------------------------
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask  */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB2_USART3_STAT  -----------------------------------
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB2_USART2_CFG  ------------------------------------
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask  */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB2_USART2_STAT  -----------------------------------
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */
+
+// -------------------------------  CCU2_CLK_APB0_UART1_BUS_CFG  ----------------------------------
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos                   0                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos)           /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos                  1                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk                  (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos)          /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos                2                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk                (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos)        /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB0_UART1_STAT  ------------------------------------
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos)              /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask  */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos)             /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB0_USART0_CFG  ------------------------------------
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos)              /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask  */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB0_USART0_STAT  -----------------------------------
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos)             /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB2_SSP1_CFG  -------------------------------------
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos)                /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask    */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask   */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB2_SSP1_STAT  ------------------------------------
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos)               /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask   */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask  */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB0_SSP0_CFG  -------------------------------------
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos)                /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask    */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask   */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB0_SSP0_STAT  ------------------------------------
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos)               /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask   */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask  */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */
+
+// ------------------------------------  CCU2_CLK_SDIO_CFG  ---------------------------------------
+#define CCU2_CLK_SDIO_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_SDIO_CFG: RUN Position     */
+#define CCU2_CLK_SDIO_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos)                     /*!< CCU2 CLK_SDIO_CFG: RUN Mask         */
+#define CCU2_CLK_SDIO_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_SDIO_CFG: AUTO Position    */
+#define CCU2_CLK_SDIO_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos)                    /*!< CCU2 CLK_SDIO_CFG: AUTO Mask        */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position  */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU2_CLK_SDIO_STAT  ---------------------------------------
+#define CCU2_CLK_SDIO_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_SDIO_STAT: RUN Position    */
+#define CCU2_CLK_SDIO_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos)                    /*!< CCU2 CLK_SDIO_STAT: RUN Mask        */
+#define CCU2_CLK_SDIO_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_SDIO_STAT: AUTO Position   */
+#define CCU2_CLK_SDIO_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos)                   /*!< CCU2 CLK_SDIO_STAT: AUTO Mask       */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  RGU Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  RGU_RESET_CTRL0  ----------------------------------------
+#define RGU_RESET_CTRL0_CORE_RST_Pos                          0                                                         /*!< RGU RESET_CTRL0: CORE_RST Position  */
+#define RGU_RESET_CTRL0_CORE_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos)                  /*!< RGU RESET_CTRL0: CORE_RST Mask      */
+#define RGU_RESET_CTRL0_PERIPH_RST_Pos                        1                                                         /*!< RGU RESET_CTRL0: PERIPH_RST Position */
+#define RGU_RESET_CTRL0_PERIPH_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos)                /*!< RGU RESET_CTRL0: PERIPH_RST Mask    */
+#define RGU_RESET_CTRL0_MASTER_RST_Pos                        2                                                         /*!< RGU RESET_CTRL0: MASTER_RST Position */
+#define RGU_RESET_CTRL0_MASTER_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos)                /*!< RGU RESET_CTRL0: MASTER_RST Mask    */
+#define RGU_RESET_CTRL0_WWDT_RST_Pos                          4                                                         /*!< RGU RESET_CTRL0: WWDT_RST Position  */
+#define RGU_RESET_CTRL0_WWDT_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos)                  /*!< RGU RESET_CTRL0: WWDT_RST Mask      */
+#define RGU_RESET_CTRL0_CREG_RST_Pos                          5                                                         /*!< RGU RESET_CTRL0: CREG_RST Position  */
+#define RGU_RESET_CTRL0_CREG_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos)                  /*!< RGU RESET_CTRL0: CREG_RST Mask      */
+#define RGU_RESET_CTRL0_BUS_RST_Pos                           8                                                         /*!< RGU RESET_CTRL0: BUS_RST Position   */
+#define RGU_RESET_CTRL0_BUS_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos)                   /*!< RGU RESET_CTRL0: BUS_RST Mask       */
+#define RGU_RESET_CTRL0_SCU_RST_Pos                           9                                                         /*!< RGU RESET_CTRL0: SCU_RST Position   */
+#define RGU_RESET_CTRL0_SCU_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos)                   /*!< RGU RESET_CTRL0: SCU_RST Mask       */
+#define RGU_RESET_CTRL0_PINMUX_RST_Pos                        10                                                        /*!< RGU RESET_CTRL0: PINMUX_RST Position */
+#define RGU_RESET_CTRL0_PINMUX_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos)                /*!< RGU RESET_CTRL0: PINMUX_RST Mask    */
+#define RGU_RESET_CTRL0_M4_RST_Pos                            13                                                        /*!< RGU RESET_CTRL0: M4_RST Position    */
+#define RGU_RESET_CTRL0_M4_RST_Msk                            (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos)                    /*!< RGU RESET_CTRL0: M4_RST Mask        */
+#define RGU_RESET_CTRL0_LCD_RST_Pos                           16                                                        /*!< RGU RESET_CTRL0: LCD_RST Position   */
+#define RGU_RESET_CTRL0_LCD_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos)                   /*!< RGU RESET_CTRL0: LCD_RST Mask       */
+#define RGU_RESET_CTRL0_USB0_RST_Pos                          17                                                        /*!< RGU RESET_CTRL0: USB0_RST Position  */
+#define RGU_RESET_CTRL0_USB0_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos)                  /*!< RGU RESET_CTRL0: USB0_RST Mask      */
+#define RGU_RESET_CTRL0_USB1_RST_Pos                          18                                                        /*!< RGU RESET_CTRL0: USB1_RST Position  */
+#define RGU_RESET_CTRL0_USB1_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos)                  /*!< RGU RESET_CTRL0: USB1_RST Mask      */
+#define RGU_RESET_CTRL0_DMA_RST_Pos                           19                                                        /*!< RGU RESET_CTRL0: DMA_RST Position   */
+#define RGU_RESET_CTRL0_DMA_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos)                   /*!< RGU RESET_CTRL0: DMA_RST Mask       */
+#define RGU_RESET_CTRL0_SDIO_RST_Pos                          20                                                        /*!< RGU RESET_CTRL0: SDIO_RST Position  */
+#define RGU_RESET_CTRL0_SDIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos)                  /*!< RGU RESET_CTRL0: SDIO_RST Mask      */
+#define RGU_RESET_CTRL0_EMC_RST_Pos                           21                                                        /*!< RGU RESET_CTRL0: EMC_RST Position   */
+#define RGU_RESET_CTRL0_EMC_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos)                   /*!< RGU RESET_CTRL0: EMC_RST Mask       */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Pos                      22                                                        /*!< RGU RESET_CTRL0: ETHERNET_RST Position */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Msk                      (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos)              /*!< RGU RESET_CTRL0: ETHERNET_RST Mask  */
+#define RGU_RESET_CTRL0_GPIO_RST_Pos                          28                                                        /*!< RGU RESET_CTRL0: GPIO_RST Position  */
+#define RGU_RESET_CTRL0_GPIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos)                  /*!< RGU RESET_CTRL0: GPIO_RST Mask      */
+
+// -------------------------------------  RGU_RESET_CTRL1  ----------------------------------------
+#define RGU_RESET_CTRL1_TIMER0_RST_Pos                        0                                                         /*!< RGU RESET_CTRL1: TIMER0_RST Position */
+#define RGU_RESET_CTRL1_TIMER0_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER0_RST Mask    */
+#define RGU_RESET_CTRL1_TIMER1_RST_Pos                        1                                                         /*!< RGU RESET_CTRL1: TIMER1_RST Position */
+#define RGU_RESET_CTRL1_TIMER1_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER1_RST Mask    */
+#define RGU_RESET_CTRL1_TIMER2_RST_Pos                        2                                                         /*!< RGU RESET_CTRL1: TIMER2_RST Position */
+#define RGU_RESET_CTRL1_TIMER2_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER2_RST Mask    */
+#define RGU_RESET_CTRL1_TIMER3_RST_Pos                        3                                                         /*!< RGU RESET_CTRL1: TIMER3_RST Position */
+#define RGU_RESET_CTRL1_TIMER3_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER3_RST Mask    */
+#define RGU_RESET_CTRL1_RITIMER_RST_Pos                       4                                                         /*!< RGU RESET_CTRL1: RITIMER_RST Position */
+#define RGU_RESET_CTRL1_RITIMER_RST_Msk                       (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos)               /*!< RGU RESET_CTRL1: RITIMER_RST Mask   */
+#define RGU_RESET_CTRL1_SCT_RST_Pos                           5                                                         /*!< RGU RESET_CTRL1: SCT_RST Position   */
+#define RGU_RESET_CTRL1_SCT_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos)                   /*!< RGU RESET_CTRL1: SCT_RST Mask       */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos                    6                                                         /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk                    (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos)            /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_CTRL1_QEI_RST_Pos                           7                                                         /*!< RGU RESET_CTRL1: QEI_RST Position   */
+#define RGU_RESET_CTRL1_QEI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos)                   /*!< RGU RESET_CTRL1: QEI_RST Mask       */
+#define RGU_RESET_CTRL1_ADC0_RST_Pos                          8                                                         /*!< RGU RESET_CTRL1: ADC0_RST Position  */
+#define RGU_RESET_CTRL1_ADC0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC0_RST Mask      */
+#define RGU_RESET_CTRL1_ADC1_RST_Pos                          9                                                         /*!< RGU RESET_CTRL1: ADC1_RST Position  */
+#define RGU_RESET_CTRL1_ADC1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC1_RST Mask      */
+#define RGU_RESET_CTRL1_DAC_RST_Pos                           10                                                        /*!< RGU RESET_CTRL1: DAC_RST Position   */
+#define RGU_RESET_CTRL1_DAC_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos)                   /*!< RGU RESET_CTRL1: DAC_RST Mask       */
+#define RGU_RESET_CTRL1_UART0_RST_Pos                         12                                                        /*!< RGU RESET_CTRL1: UART0_RST Position */
+#define RGU_RESET_CTRL1_UART0_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos)                 /*!< RGU RESET_CTRL1: UART0_RST Mask     */
+#define RGU_RESET_CTRL1_UART1_RST_Pos                         13                                                        /*!< RGU RESET_CTRL1: UART1_RST Position */
+#define RGU_RESET_CTRL1_UART1_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos)                 /*!< RGU RESET_CTRL1: UART1_RST Mask     */
+#define RGU_RESET_CTRL1_UART2_RST_Pos                         14                                                        /*!< RGU RESET_CTRL1: UART2_RST Position */
+#define RGU_RESET_CTRL1_UART2_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos)                 /*!< RGU RESET_CTRL1: UART2_RST Mask     */
+#define RGU_RESET_CTRL1_UART3_RST_Pos                         15                                                        /*!< RGU RESET_CTRL1: UART3_RST Position */
+#define RGU_RESET_CTRL1_UART3_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos)                 /*!< RGU RESET_CTRL1: UART3_RST Mask     */
+#define RGU_RESET_CTRL1_I2C0_RST_Pos                          16                                                        /*!< RGU RESET_CTRL1: I2C0_RST Position  */
+#define RGU_RESET_CTRL1_I2C0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C0_RST Mask      */
+#define RGU_RESET_CTRL1_I2C1_RST_Pos                          17                                                        /*!< RGU RESET_CTRL1: I2C1_RST Position  */
+#define RGU_RESET_CTRL1_I2C1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C1_RST Mask      */
+#define RGU_RESET_CTRL1_SSP0_RST_Pos                          18                                                        /*!< RGU RESET_CTRL1: SSP0_RST Position  */
+#define RGU_RESET_CTRL1_SSP0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP0_RST Mask      */
+#define RGU_RESET_CTRL1_SSP1_RST_Pos                          19                                                        /*!< RGU RESET_CTRL1: SSP1_RST Position  */
+#define RGU_RESET_CTRL1_SSP1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP1_RST Mask      */
+#define RGU_RESET_CTRL1_I2S_RST_Pos                           20                                                        /*!< RGU RESET_CTRL1: I2S_RST Position   */
+#define RGU_RESET_CTRL1_I2S_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos)                   /*!< RGU RESET_CTRL1: I2S_RST Mask       */
+#define RGU_RESET_CTRL1_SPIFI_RST_Pos                         21                                                        /*!< RGU RESET_CTRL1: SPIFI_RST Position */
+#define RGU_RESET_CTRL1_SPIFI_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos)                 /*!< RGU RESET_CTRL1: SPIFI_RST Mask     */
+#define RGU_RESET_CTRL1_CAN1_RST_Pos                          22                                                        /*!< RGU RESET_CTRL1: CAN1_RST Position  */
+#define RGU_RESET_CTRL1_CAN1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN1_RST Mask      */
+#define RGU_RESET_CTRL1_CAN0_RST_Pos                          23                                                        /*!< RGU RESET_CTRL1: CAN0_RST Position  */
+#define RGU_RESET_CTRL1_CAN0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN0_RST Mask      */
+#define RGU_RESET_CTRL1_M0APP_RST_Pos                         24                                                        /*!< RGU RESET_CTRL1: M0APP_RST Position */
+#define RGU_RESET_CTRL1_M0APP_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos)                 /*!< RGU RESET_CTRL1: M0APP_RST Mask     */
+#define RGU_RESET_CTRL1_SGPIO_RST_Pos                         25                                                        /*!< RGU RESET_CTRL1: SGPIO_RST Position */
+#define RGU_RESET_CTRL1_SGPIO_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos)                 /*!< RGU RESET_CTRL1: SGPIO_RST Mask     */
+#define RGU_RESET_CTRL1_SPI_RST_Pos                           26                                                        /*!< RGU RESET_CTRL1: SPI_RST Position   */
+#define RGU_RESET_CTRL1_SPI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos)                   /*!< RGU RESET_CTRL1: SPI_RST Mask       */
+
+// ------------------------------------  RGU_RESET_STATUS0  ---------------------------------------
+#define RGU_RESET_STATUS0_CORE_RST_Pos                        0                                                         /*!< RGU RESET_STATUS0: CORE_RST Position */
+#define RGU_RESET_STATUS0_CORE_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos)                /*!< RGU RESET_STATUS0: CORE_RST Mask    */
+#define RGU_RESET_STATUS0_PERIPH_RST_Pos                      2                                                         /*!< RGU RESET_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_STATUS0_PERIPH_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos)              /*!< RGU RESET_STATUS0: PERIPH_RST Mask  */
+#define RGU_RESET_STATUS0_MASTER_RST_Pos                      4                                                         /*!< RGU RESET_STATUS0: MASTER_RST Position */
+#define RGU_RESET_STATUS0_MASTER_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos)              /*!< RGU RESET_STATUS0: MASTER_RST Mask  */
+#define RGU_RESET_STATUS0_WWDT_RST_Pos                        8                                                         /*!< RGU RESET_STATUS0: WWDT_RST Position */
+#define RGU_RESET_STATUS0_WWDT_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos)                /*!< RGU RESET_STATUS0: WWDT_RST Mask    */
+#define RGU_RESET_STATUS0_CREG_RST_Pos                        10                                                        /*!< RGU RESET_STATUS0: CREG_RST Position */
+#define RGU_RESET_STATUS0_CREG_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos)                /*!< RGU RESET_STATUS0: CREG_RST Mask    */
+#define RGU_RESET_STATUS0_BUS_RST_Pos                         16                                                        /*!< RGU RESET_STATUS0: BUS_RST Position */
+#define RGU_RESET_STATUS0_BUS_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos)                 /*!< RGU RESET_STATUS0: BUS_RST Mask     */
+#define RGU_RESET_STATUS0_SCU_RST_Pos                         18                                                        /*!< RGU RESET_STATUS0: SCU_RST Position */
+#define RGU_RESET_STATUS0_SCU_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos)                 /*!< RGU RESET_STATUS0: SCU_RST Mask     */
+#define RGU_RESET_STATUS0_M4_RST_Pos                          26                                                        /*!< RGU RESET_STATUS0: M4_RST Position  */
+#define RGU_RESET_STATUS0_M4_RST_Msk                          (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos)                  /*!< RGU RESET_STATUS0: M4_RST Mask      */
+
+// ------------------------------------  RGU_RESET_STATUS1  ---------------------------------------
+#define RGU_RESET_STATUS1_LCD_RST_Pos                         0                                                         /*!< RGU RESET_STATUS1: LCD_RST Position */
+#define RGU_RESET_STATUS1_LCD_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos)                 /*!< RGU RESET_STATUS1: LCD_RST Mask     */
+#define RGU_RESET_STATUS1_USB0_RST_Pos                        2                                                         /*!< RGU RESET_STATUS1: USB0_RST Position */
+#define RGU_RESET_STATUS1_USB0_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos)                /*!< RGU RESET_STATUS1: USB0_RST Mask    */
+#define RGU_RESET_STATUS1_USB1_RST_Pos                        4                                                         /*!< RGU RESET_STATUS1: USB1_RST Position */
+#define RGU_RESET_STATUS1_USB1_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos)                /*!< RGU RESET_STATUS1: USB1_RST Mask    */
+#define RGU_RESET_STATUS1_DMA_RST_Pos                         6                                                         /*!< RGU RESET_STATUS1: DMA_RST Position */
+#define RGU_RESET_STATUS1_DMA_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos)                 /*!< RGU RESET_STATUS1: DMA_RST Mask     */
+#define RGU_RESET_STATUS1_SDIO_RST_Pos                        8                                                         /*!< RGU RESET_STATUS1: SDIO_RST Position */
+#define RGU_RESET_STATUS1_SDIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos)                /*!< RGU RESET_STATUS1: SDIO_RST Mask    */
+#define RGU_RESET_STATUS1_EMC_RST_Pos                         10                                                        /*!< RGU RESET_STATUS1: EMC_RST Position */
+#define RGU_RESET_STATUS1_EMC_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos)                 /*!< RGU RESET_STATUS1: EMC_RST Mask     */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Pos                    12                                                        /*!< RGU RESET_STATUS1: ETHERNET_RST Position */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Msk                    (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos)            /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */
+#define RGU_RESET_STATUS1_GPIO_RST_Pos                        24                                                        /*!< RGU RESET_STATUS1: GPIO_RST Position */
+#define RGU_RESET_STATUS1_GPIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos)                /*!< RGU RESET_STATUS1: GPIO_RST Mask    */
+
+// ------------------------------------  RGU_RESET_STATUS2  ---------------------------------------
+#define RGU_RESET_STATUS2_TIMER0_RST_Pos                      0                                                         /*!< RGU RESET_STATUS2: TIMER0_RST Position */
+#define RGU_RESET_STATUS2_TIMER0_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER0_RST Mask  */
+#define RGU_RESET_STATUS2_TIMER1_RST_Pos                      2                                                         /*!< RGU RESET_STATUS2: TIMER1_RST Position */
+#define RGU_RESET_STATUS2_TIMER1_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER1_RST Mask  */
+#define RGU_RESET_STATUS2_TIMER2_RST_Pos                      4                                                         /*!< RGU RESET_STATUS2: TIMER2_RST Position */
+#define RGU_RESET_STATUS2_TIMER2_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER2_RST Mask  */
+#define RGU_RESET_STATUS2_TIMER3_RST_Pos                      6                                                         /*!< RGU RESET_STATUS2: TIMER3_RST Position */
+#define RGU_RESET_STATUS2_TIMER3_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER3_RST Mask  */
+#define RGU_RESET_STATUS2_RITIMER_RST_Pos                     8                                                         /*!< RGU RESET_STATUS2: RITIMER_RST Position */
+#define RGU_RESET_STATUS2_RITIMER_RST_Msk                     (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos)             /*!< RGU RESET_STATUS2: RITIMER_RST Mask */
+#define RGU_RESET_STATUS2_SCT_RST_Pos                         10                                                        /*!< RGU RESET_STATUS2: SCT_RST Position */
+#define RGU_RESET_STATUS2_SCT_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos)                 /*!< RGU RESET_STATUS2: SCT_RST Mask     */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos                  12                                                        /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk                  (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos)          /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */
+#define RGU_RESET_STATUS2_QEI_RST_Pos                         14                                                        /*!< RGU RESET_STATUS2: QEI_RST Position */
+#define RGU_RESET_STATUS2_QEI_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos)                 /*!< RGU RESET_STATUS2: QEI_RST Mask     */
+#define RGU_RESET_STATUS2_ADC0_RST_Pos                        16                                                        /*!< RGU RESET_STATUS2: ADC0_RST Position */
+#define RGU_RESET_STATUS2_ADC0_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos)                /*!< RGU RESET_STATUS2: ADC0_RST Mask    */
+#define RGU_RESET_STATUS2_ADC1_RST_Pos                        18                                                        /*!< RGU RESET_STATUS2: ADC1_RST Position */
+#define RGU_RESET_STATUS2_ADC1_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos)                /*!< RGU RESET_STATUS2: ADC1_RST Mask    */
+#define RGU_RESET_STATUS2_DAC_RST_Pos                         20                                                        /*!< RGU RESET_STATUS2: DAC_RST Position */
+#define RGU_RESET_STATUS2_DAC_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos)                 /*!< RGU RESET_STATUS2: DAC_RST Mask     */
+#define RGU_RESET_STATUS2_UART0_RST_Pos                       24                                                        /*!< RGU RESET_STATUS2: UART0_RST Position */
+#define RGU_RESET_STATUS2_UART0_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos)               /*!< RGU RESET_STATUS2: UART0_RST Mask   */
+#define RGU_RESET_STATUS2_UART1_RST_Pos                       26                                                        /*!< RGU RESET_STATUS2: UART1_RST Position */
+#define RGU_RESET_STATUS2_UART1_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos)               /*!< RGU RESET_STATUS2: UART1_RST Mask   */
+#define RGU_RESET_STATUS2_UART2_RST_Pos                       28                                                        /*!< RGU RESET_STATUS2: UART2_RST Position */
+#define RGU_RESET_STATUS2_UART2_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos)               /*!< RGU RESET_STATUS2: UART2_RST Mask   */
+#define RGU_RESET_STATUS2_UART3_RST_Pos                       30                                                        /*!< RGU RESET_STATUS2: UART3_RST Position */
+#define RGU_RESET_STATUS2_UART3_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos)               /*!< RGU RESET_STATUS2: UART3_RST Mask   */
+
+// ------------------------------------  RGU_RESET_STATUS3  ---------------------------------------
+#define RGU_RESET_STATUS3_I2C0_RST_Pos                        0                                                         /*!< RGU RESET_STATUS3: I2C0_RST Position */
+#define RGU_RESET_STATUS3_I2C0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos)                /*!< RGU RESET_STATUS3: I2C0_RST Mask    */
+#define RGU_RESET_STATUS3_I2C1_RST_Pos                        2                                                         /*!< RGU RESET_STATUS3: I2C1_RST Position */
+#define RGU_RESET_STATUS3_I2C1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos)                /*!< RGU RESET_STATUS3: I2C1_RST Mask    */
+#define RGU_RESET_STATUS3_SSP0_RST_Pos                        4                                                         /*!< RGU RESET_STATUS3: SSP0_RST Position */
+#define RGU_RESET_STATUS3_SSP0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos)                /*!< RGU RESET_STATUS3: SSP0_RST Mask    */
+#define RGU_RESET_STATUS3_SSP1_RST_Pos                        6                                                         /*!< RGU RESET_STATUS3: SSP1_RST Position */
+#define RGU_RESET_STATUS3_SSP1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos)                /*!< RGU RESET_STATUS3: SSP1_RST Mask    */
+#define RGU_RESET_STATUS3_I2S_RST_Pos                         8                                                         /*!< RGU RESET_STATUS3: I2S_RST Position */
+#define RGU_RESET_STATUS3_I2S_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos)                 /*!< RGU RESET_STATUS3: I2S_RST Mask     */
+#define RGU_RESET_STATUS3_SPIFI_RST_Pos                       10                                                        /*!< RGU RESET_STATUS3: SPIFI_RST Position */
+#define RGU_RESET_STATUS3_SPIFI_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos)               /*!< RGU RESET_STATUS3: SPIFI_RST Mask   */
+#define RGU_RESET_STATUS3_CAN1_RST_Pos                        12                                                        /*!< RGU RESET_STATUS3: CAN1_RST Position */
+#define RGU_RESET_STATUS3_CAN1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos)                /*!< RGU RESET_STATUS3: CAN1_RST Mask    */
+#define RGU_RESET_STATUS3_CAN0_RST_Pos                        14                                                        /*!< RGU RESET_STATUS3: CAN0_RST Position */
+#define RGU_RESET_STATUS3_CAN0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos)                /*!< RGU RESET_STATUS3: CAN0_RST Mask    */
+#define RGU_RESET_STATUS3_M0APP_RST_Pos                       16                                                        /*!< RGU RESET_STATUS3: M0APP_RST Position */
+#define RGU_RESET_STATUS3_M0APP_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos)               /*!< RGU RESET_STATUS3: M0APP_RST Mask   */
+#define RGU_RESET_STATUS3_SGPIO_RST_Pos                       18                                                        /*!< RGU RESET_STATUS3: SGPIO_RST Position */
+#define RGU_RESET_STATUS3_SGPIO_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos)               /*!< RGU RESET_STATUS3: SGPIO_RST Mask   */
+#define RGU_RESET_STATUS3_SPI_RST_Pos                         20                                                        /*!< RGU RESET_STATUS3: SPI_RST Position */
+#define RGU_RESET_STATUS3_SPI_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos)                 /*!< RGU RESET_STATUS3: SPI_RST Mask     */
+
+// --------------------------------  RGU_RESET_ACTIVE_STATUS0  ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos                 0                                                         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos                 4                                                         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos                 5                                                         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos                  8                                                         /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos                  9                                                         /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos               10                                                        /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos                   13                                                        /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk                   (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos)           /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos                  16                                                        /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos                  19                                                        /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos                 20                                                        /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos                  21                                                        /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos             22                                                        /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk             (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)     /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos                 28                                                        /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */
+
+// --------------------------------  RGU_RESET_ACTIVE_STATUS1  ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos               0                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos               3                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos              4                                                         /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk              (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos)      /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos                  5                                                         /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos           6                                                         /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk           (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)   /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos                  7                                                         /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos                 8                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos                 9                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos                  10                                                        /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos                12                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos                13                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos                14                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos                15                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos                 16                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos                 19                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos                  20                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos                21                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos                 22                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos                 23                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos                24                                                        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos                25                                                        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos                  26                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT0  --------------------------------------
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos                     0                                                         /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos                     4                                                         /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos                    5                                                         /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos)            /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT1  --------------------------------------
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT2  --------------------------------------
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT4  --------------------------------------
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT5  --------------------------------------
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT8  --------------------------------------
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT9  --------------------------------------
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT13  --------------------------------------
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT16  --------------------------------------
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT17  --------------------------------------
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT18  --------------------------------------
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT19  --------------------------------------
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT20  --------------------------------------
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT21  --------------------------------------
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT22  --------------------------------------
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT23  --------------------------------------
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT28  --------------------------------------
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT32  --------------------------------------
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT33  --------------------------------------
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT34  --------------------------------------
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT35  --------------------------------------
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT36  --------------------------------------
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT37  --------------------------------------
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT38  --------------------------------------
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT39  --------------------------------------
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT40  --------------------------------------
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT41  --------------------------------------
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT42  --------------------------------------
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT44  --------------------------------------
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT45  --------------------------------------
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT46  --------------------------------------
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT47  --------------------------------------
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT48  --------------------------------------
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT49  --------------------------------------
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT50  --------------------------------------
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT51  --------------------------------------
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT52  --------------------------------------
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT53  --------------------------------------
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT54  --------------------------------------
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT55  --------------------------------------
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 WWDT Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  WWDT_MOD  --------------------------------------------
+#define WWDT_MOD_WDEN_Pos                                     0                                                         /*!< WWDT MOD: WDEN Position             */
+#define WWDT_MOD_WDEN_Msk                                     (0x01UL << WWDT_MOD_WDEN_Pos)                             /*!< WWDT MOD: WDEN Mask                 */
+#define WWDT_MOD_WDRESET_Pos                                  1                                                         /*!< WWDT MOD: WDRESET Position          */
+#define WWDT_MOD_WDRESET_Msk                                  (0x01UL << WWDT_MOD_WDRESET_Pos)                          /*!< WWDT MOD: WDRESET Mask              */
+#define WWDT_MOD_WDTOF_Pos                                    2                                                         /*!< WWDT MOD: WDTOF Position            */
+#define WWDT_MOD_WDTOF_Msk                                    (0x01UL << WWDT_MOD_WDTOF_Pos)                            /*!< WWDT MOD: WDTOF Mask                */
+#define WWDT_MOD_WDINT_Pos                                    3                                                         /*!< WWDT MOD: WDINT Position            */
+#define WWDT_MOD_WDINT_Msk                                    (0x01UL << WWDT_MOD_WDINT_Pos)                            /*!< WWDT MOD: WDINT Mask                */
+#define WWDT_MOD_WDPROTECT_Pos                                4                                                         /*!< WWDT MOD: WDPROTECT Position        */
+#define WWDT_MOD_WDPROTECT_Msk                                (0x01UL << WWDT_MOD_WDPROTECT_Pos)                        /*!< WWDT MOD: WDPROTECT Mask            */
+
+// -----------------------------------------  WWDT_TC  --------------------------------------------
+#define WWDT_TC_WDTC_Pos                                      0                                                         /*!< WWDT TC: WDTC Position              */
+#define WWDT_TC_WDTC_Msk                                      (0x00ffffffUL << WWDT_TC_WDTC_Pos)                        /*!< WWDT TC: WDTC Mask                  */
+
+// ----------------------------------------  WWDT_FEED  -------------------------------------------
+#define WWDT_FEED_Feed_Pos                                    0                                                         /*!< WWDT FEED: Feed Position            */
+#define WWDT_FEED_Feed_Msk                                    (0x000000ffUL << WWDT_FEED_Feed_Pos)                      /*!< WWDT FEED: Feed Mask                */
+
+// -----------------------------------------  WWDT_TV  --------------------------------------------
+#define WWDT_TV_Count_Pos                                     0                                                         /*!< WWDT TV: Count Position             */
+#define WWDT_TV_Count_Msk                                     (0x00ffffffUL << WWDT_TV_Count_Pos)                       /*!< WWDT TV: Count Mask                 */
+
+// --------------------------------------  WWDT_WARNINT  ------------------------------------------
+#define WWDT_WARNINT_WDWARNINT_Pos                            0                                                         /*!< WWDT WARNINT: WDWARNINT Position    */
+#define WWDT_WARNINT_WDWARNINT_Msk                            (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos)              /*!< WWDT WARNINT: WDWARNINT Mask        */
+
+// ---------------------------------------  WWDT_WINDOW  ------------------------------------------
+#define WWDT_WINDOW_WDWINDOW_Pos                              0                                                         /*!< WWDT WINDOW: WDWINDOW Position      */
+#define WWDT_WINDOW_WDWINDOW_Msk                              (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos)                /*!< WWDT WINDOW: WDWINDOW Mask          */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                USART0 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  USART0_RBR  -------------------------------------------
+#define USART0_RBR_RBR_Pos                                    0                                                         /*!< USART0 RBR: RBR Position            */
+#define USART0_RBR_RBR_Msk                                    (0x000000ffUL << USART0_RBR_RBR_Pos)                      /*!< USART0 RBR: RBR Mask                */
+
+// ---------------------------------------  USART0_THR  -------------------------------------------
+#define USART0_THR_THR_Pos                                    0                                                         /*!< USART0 THR: THR Position            */
+#define USART0_THR_THR_Msk                                    (0x000000ffUL << USART0_THR_THR_Pos)                      /*!< USART0 THR: THR Mask                */
+
+// ---------------------------------------  USART0_DLL  -------------------------------------------
+#define USART0_DLL_DLLSB_Pos                                  0                                                         /*!< USART0 DLL: DLLSB Position          */
+#define USART0_DLL_DLLSB_Msk                                  (0x000000ffUL << USART0_DLL_DLLSB_Pos)                    /*!< USART0 DLL: DLLSB Mask              */
+
+// ---------------------------------------  USART0_DLM  -------------------------------------------
+#define USART0_DLM_DLMSB_Pos                                  0                                                         /*!< USART0 DLM: DLMSB Position          */
+#define USART0_DLM_DLMSB_Msk                                  (0x000000ffUL << USART0_DLM_DLMSB_Pos)                    /*!< USART0 DLM: DLMSB Mask              */
+
+// ---------------------------------------  USART0_IER  -------------------------------------------
+#define USART0_IER_RBRIE_Pos                                  0                                                         /*!< USART0 IER: RBRIE Position          */
+#define USART0_IER_RBRIE_Msk                                  (0x01UL << USART0_IER_RBRIE_Pos)                          /*!< USART0 IER: RBRIE Mask              */
+#define USART0_IER_THREIE_Pos                                 1                                                         /*!< USART0 IER: THREIE Position         */
+#define USART0_IER_THREIE_Msk                                 (0x01UL << USART0_IER_THREIE_Pos)                         /*!< USART0 IER: THREIE Mask             */
+#define USART0_IER_RXIE_Pos                                   2                                                         /*!< USART0 IER: RXIE Position           */
+#define USART0_IER_RXIE_Msk                                   (0x01UL << USART0_IER_RXIE_Pos)                           /*!< USART0 IER: RXIE Mask               */
+#define USART0_IER_ABEOINTEN_Pos                              8                                                         /*!< USART0 IER: ABEOINTEN Position      */
+#define USART0_IER_ABEOINTEN_Msk                              (0x01UL << USART0_IER_ABEOINTEN_Pos)                      /*!< USART0 IER: ABEOINTEN Mask          */
+#define USART0_IER_ABTOINTEN_Pos                              9                                                         /*!< USART0 IER: ABTOINTEN Position      */
+#define USART0_IER_ABTOINTEN_Msk                              (0x01UL << USART0_IER_ABTOINTEN_Pos)                      /*!< USART0 IER: ABTOINTEN Mask          */
+
+// ---------------------------------------  USART0_IIR  -------------------------------------------
+#define USART0_IIR_INTSTATUS_Pos                              0                                                         /*!< USART0 IIR: INTSTATUS Position      */
+#define USART0_IIR_INTSTATUS_Msk                              (0x01UL << USART0_IIR_INTSTATUS_Pos)                      /*!< USART0 IIR: INTSTATUS Mask          */
+#define USART0_IIR_INTID_Pos                                  1                                                         /*!< USART0 IIR: INTID Position          */
+#define USART0_IIR_INTID_Msk                                  (0x07UL << USART0_IIR_INTID_Pos)                          /*!< USART0 IIR: INTID Mask              */
+#define USART0_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART0 IIR: FIFOENABLE Position     */
+#define USART0_IIR_FIFOENABLE_Msk                             (0x03UL << USART0_IIR_FIFOENABLE_Pos)                     /*!< USART0 IIR: FIFOENABLE Mask         */
+#define USART0_IIR_ABEOINT_Pos                                8                                                         /*!< USART0 IIR: ABEOINT Position        */
+#define USART0_IIR_ABEOINT_Msk                                (0x01UL << USART0_IIR_ABEOINT_Pos)                        /*!< USART0 IIR: ABEOINT Mask            */
+#define USART0_IIR_ABTOINT_Pos                                9                                                         /*!< USART0 IIR: ABTOINT Position        */
+#define USART0_IIR_ABTOINT_Msk                                (0x01UL << USART0_IIR_ABTOINT_Pos)                        /*!< USART0 IIR: ABTOINT Mask            */
+
+// ---------------------------------------  USART0_FCR  -------------------------------------------
+#define USART0_FCR_FIFOEN_Pos                                 0                                                         /*!< USART0 FCR: FIFOEN Position         */
+#define USART0_FCR_FIFOEN_Msk                                 (0x01UL << USART0_FCR_FIFOEN_Pos)                         /*!< USART0 FCR: FIFOEN Mask             */
+#define USART0_FCR_RXFIFORES_Pos                              1                                                         /*!< USART0 FCR: RXFIFORES Position      */
+#define USART0_FCR_RXFIFORES_Msk                              (0x01UL << USART0_FCR_RXFIFORES_Pos)                      /*!< USART0 FCR: RXFIFORES Mask          */
+#define USART0_FCR_TXFIFORES_Pos                              2                                                         /*!< USART0 FCR: TXFIFORES Position      */
+#define USART0_FCR_TXFIFORES_Msk                              (0x01UL << USART0_FCR_TXFIFORES_Pos)                      /*!< USART0 FCR: TXFIFORES Mask          */
+#define USART0_FCR_DMAMODE_Pos                                3                                                         /*!< USART0 FCR: DMAMODE Position        */
+#define USART0_FCR_DMAMODE_Msk                                (0x01UL << USART0_FCR_DMAMODE_Pos)                        /*!< USART0 FCR: DMAMODE Mask            */
+#define USART0_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART0 FCR: RXTRIGLVL Position      */
+#define USART0_FCR_RXTRIGLVL_Msk                              (0x03UL << USART0_FCR_RXTRIGLVL_Pos)                      /*!< USART0 FCR: RXTRIGLVL Mask          */
+
+// ---------------------------------------  USART0_LCR  -------------------------------------------
+#define USART0_LCR_WLS_Pos                                    0                                                         /*!< USART0 LCR: WLS Position            */
+#define USART0_LCR_WLS_Msk                                    (0x03UL << USART0_LCR_WLS_Pos)                            /*!< USART0 LCR: WLS Mask                */
+#define USART0_LCR_SBS_Pos                                    2                                                         /*!< USART0 LCR: SBS Position            */
+#define USART0_LCR_SBS_Msk                                    (0x01UL << USART0_LCR_SBS_Pos)                            /*!< USART0 LCR: SBS Mask                */
+#define USART0_LCR_PE_Pos                                     3                                                         /*!< USART0 LCR: PE Position             */
+#define USART0_LCR_PE_Msk                                     (0x01UL << USART0_LCR_PE_Pos)                             /*!< USART0 LCR: PE Mask                 */
+#define USART0_LCR_PS_Pos                                     4                                                         /*!< USART0 LCR: PS Position             */
+#define USART0_LCR_PS_Msk                                     (0x03UL << USART0_LCR_PS_Pos)                             /*!< USART0 LCR: PS Mask                 */
+#define USART0_LCR_BC_Pos                                     6                                                         /*!< USART0 LCR: BC Position             */
+#define USART0_LCR_BC_Msk                                     (0x01UL << USART0_LCR_BC_Pos)                             /*!< USART0 LCR: BC Mask                 */
+#define USART0_LCR_DLAB_Pos                                   7                                                         /*!< USART0 LCR: DLAB Position           */
+#define USART0_LCR_DLAB_Msk                                   (0x01UL << USART0_LCR_DLAB_Pos)                           /*!< USART0 LCR: DLAB Mask               */
+
+// ---------------------------------------  USART0_LSR  -------------------------------------------
+#define USART0_LSR_RDR_Pos                                    0                                                         /*!< USART0 LSR: RDR Position            */
+#define USART0_LSR_RDR_Msk                                    (0x01UL << USART0_LSR_RDR_Pos)                            /*!< USART0 LSR: RDR Mask                */
+#define USART0_LSR_OE_Pos                                     1                                                         /*!< USART0 LSR: OE Position             */
+#define USART0_LSR_OE_Msk                                     (0x01UL << USART0_LSR_OE_Pos)                             /*!< USART0 LSR: OE Mask                 */
+#define USART0_LSR_PE_Pos                                     2                                                         /*!< USART0 LSR: PE Position             */
+#define USART0_LSR_PE_Msk                                     (0x01UL << USART0_LSR_PE_Pos)                             /*!< USART0 LSR: PE Mask                 */
+#define USART0_LSR_FE_Pos                                     3                                                         /*!< USART0 LSR: FE Position             */
+#define USART0_LSR_FE_Msk                                     (0x01UL << USART0_LSR_FE_Pos)                             /*!< USART0 LSR: FE Mask                 */
+#define USART0_LSR_BI_Pos                                     4                                                         /*!< USART0 LSR: BI Position             */
+#define USART0_LSR_BI_Msk                                     (0x01UL << USART0_LSR_BI_Pos)                             /*!< USART0 LSR: BI Mask                 */
+#define USART0_LSR_THRE_Pos                                   5                                                         /*!< USART0 LSR: THRE Position           */
+#define USART0_LSR_THRE_Msk                                   (0x01UL << USART0_LSR_THRE_Pos)                           /*!< USART0 LSR: THRE Mask               */
+#define USART0_LSR_TEMT_Pos                                   6                                                         /*!< USART0 LSR: TEMT Position           */
+#define USART0_LSR_TEMT_Msk                                   (0x01UL << USART0_LSR_TEMT_Pos)                           /*!< USART0 LSR: TEMT Mask               */
+#define USART0_LSR_RXFE_Pos                                   7                                                         /*!< USART0 LSR: RXFE Position           */
+#define USART0_LSR_RXFE_Msk                                   (0x01UL << USART0_LSR_RXFE_Pos)                           /*!< USART0 LSR: RXFE Mask               */
+#define USART0_LSR_TXERR_Pos                                  8                                                         /*!< USART0 LSR: TXERR Position          */
+#define USART0_LSR_TXERR_Msk                                  (0x01UL << USART0_LSR_TXERR_Pos)                          /*!< USART0 LSR: TXERR Mask              */
+
+// ---------------------------------------  USART0_SCR  -------------------------------------------
+#define USART0_SCR_PAD_Pos                                    0                                                         /*!< USART0 SCR: PAD Position            */
+#define USART0_SCR_PAD_Msk                                    (0x000000ffUL << USART0_SCR_PAD_Pos)                      /*!< USART0 SCR: PAD Mask                */
+
+// ---------------------------------------  USART0_ACR  -------------------------------------------
+#define USART0_ACR_START_Pos                                  0                                                         /*!< USART0 ACR: START Position          */
+#define USART0_ACR_START_Msk                                  (0x01UL << USART0_ACR_START_Pos)                          /*!< USART0 ACR: START Mask              */
+#define USART0_ACR_MODE_Pos                                   1                                                         /*!< USART0 ACR: MODE Position           */
+#define USART0_ACR_MODE_Msk                                   (0x01UL << USART0_ACR_MODE_Pos)                           /*!< USART0 ACR: MODE Mask               */
+#define USART0_ACR_AUTORESTART_Pos                            2                                                         /*!< USART0 ACR: AUTORESTART Position    */
+#define USART0_ACR_AUTORESTART_Msk                            (0x01UL << USART0_ACR_AUTORESTART_Pos)                    /*!< USART0 ACR: AUTORESTART Mask        */
+#define USART0_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART0 ACR: ABEOINTCLR Position     */
+#define USART0_ACR_ABEOINTCLR_Msk                             (0x01UL << USART0_ACR_ABEOINTCLR_Pos)                     /*!< USART0 ACR: ABEOINTCLR Mask         */
+#define USART0_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART0 ACR: ABTOINTCLR Position     */
+#define USART0_ACR_ABTOINTCLR_Msk                             (0x01UL << USART0_ACR_ABTOINTCLR_Pos)                     /*!< USART0 ACR: ABTOINTCLR Mask         */
+
+// ---------------------------------------  USART0_ICR  -------------------------------------------
+#define USART0_ICR_IRDAEN_Pos                                 0                                                         /*!< USART0 ICR: IRDAEN Position         */
+#define USART0_ICR_IRDAEN_Msk                                 (0x01UL << USART0_ICR_IRDAEN_Pos)                         /*!< USART0 ICR: IRDAEN Mask             */
+#define USART0_ICR_IRDAINV_Pos                                1                                                         /*!< USART0 ICR: IRDAINV Position        */
+#define USART0_ICR_IRDAINV_Msk                                (0x01UL << USART0_ICR_IRDAINV_Pos)                        /*!< USART0 ICR: IRDAINV Mask            */
+#define USART0_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART0 ICR: FIXPULSEEN Position     */
+#define USART0_ICR_FIXPULSEEN_Msk                             (0x01UL << USART0_ICR_FIXPULSEEN_Pos)                     /*!< USART0 ICR: FIXPULSEEN Mask         */
+#define USART0_ICR_PULSEDIV_Pos                               3                                                         /*!< USART0 ICR: PULSEDIV Position       */
+#define USART0_ICR_PULSEDIV_Msk                               (0x07UL << USART0_ICR_PULSEDIV_Pos)                       /*!< USART0 ICR: PULSEDIV Mask           */
+
+// ---------------------------------------  USART0_FDR  -------------------------------------------
+#define USART0_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART0 FDR: DIVADDVAL Position      */
+#define USART0_FDR_DIVADDVAL_Msk                              (0x0fUL << USART0_FDR_DIVADDVAL_Pos)                      /*!< USART0 FDR: DIVADDVAL Mask          */
+#define USART0_FDR_MULVAL_Pos                                 4                                                         /*!< USART0 FDR: MULVAL Position         */
+#define USART0_FDR_MULVAL_Msk                                 (0x0fUL << USART0_FDR_MULVAL_Pos)                         /*!< USART0 FDR: MULVAL Mask             */
+
+// ---------------------------------------  USART0_OSR  -------------------------------------------
+#define USART0_OSR_OSFRAC_Pos                                 1                                                         /*!< USART0 OSR: OSFRAC Position         */
+#define USART0_OSR_OSFRAC_Msk                                 (0x07UL << USART0_OSR_OSFRAC_Pos)                         /*!< USART0 OSR: OSFRAC Mask             */
+#define USART0_OSR_OSINT_Pos                                  4                                                         /*!< USART0 OSR: OSINT Position          */
+#define USART0_OSR_OSINT_Msk                                  (0x0fUL << USART0_OSR_OSINT_Pos)                          /*!< USART0 OSR: OSINT Mask              */
+#define USART0_OSR_FDINT_Pos                                  8                                                         /*!< USART0 OSR: FDINT Position          */
+#define USART0_OSR_FDINT_Msk                                  (0x7fUL << USART0_OSR_FDINT_Pos)                          /*!< USART0 OSR: FDINT Mask              */
+
+// ---------------------------------------  USART0_HDEN  ------------------------------------------
+#define USART0_HDEN_HDEN_Pos                                  0                                                         /*!< USART0 HDEN: HDEN Position          */
+#define USART0_HDEN_HDEN_Msk                                  (0x01UL << USART0_HDEN_HDEN_Pos)                          /*!< USART0 HDEN: HDEN Mask              */
+
+// -------------------------------------  USART0_SCICTRL  -----------------------------------------
+#define USART0_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART0 SCICTRL: SCIEN Position      */
+#define USART0_SCICTRL_SCIEN_Msk                              (0x01UL << USART0_SCICTRL_SCIEN_Pos)                      /*!< USART0 SCICTRL: SCIEN Mask          */
+#define USART0_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART0 SCICTRL: NACKDIS Position    */
+#define USART0_SCICTRL_NACKDIS_Msk                            (0x01UL << USART0_SCICTRL_NACKDIS_Pos)                    /*!< USART0 SCICTRL: NACKDIS Mask        */
+#define USART0_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART0 SCICTRL: PROTSEL Position    */
+#define USART0_SCICTRL_PROTSEL_Msk                            (0x01UL << USART0_SCICTRL_PROTSEL_Pos)                    /*!< USART0 SCICTRL: PROTSEL Mask        */
+#define USART0_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART0 SCICTRL: TXRETRY Position    */
+#define USART0_SCICTRL_TXRETRY_Msk                            (0x07UL << USART0_SCICTRL_TXRETRY_Pos)                    /*!< USART0 SCICTRL: TXRETRY Mask        */
+#define USART0_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART0 SCICTRL: GUARDTIME Position  */
+#define USART0_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos)            /*!< USART0 SCICTRL: GUARDTIME Mask      */
+
+// ------------------------------------  USART0_RS485CTRL  ----------------------------------------
+#define USART0_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART0 RS485CTRL: NMMEN Position    */
+#define USART0_RS485CTRL_NMMEN_Msk                            (0x01UL << USART0_RS485CTRL_NMMEN_Pos)                    /*!< USART0 RS485CTRL: NMMEN Mask        */
+#define USART0_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART0 RS485CTRL: RXDIS Position    */
+#define USART0_RS485CTRL_RXDIS_Msk                            (0x01UL << USART0_RS485CTRL_RXDIS_Pos)                    /*!< USART0 RS485CTRL: RXDIS Mask        */
+#define USART0_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART0 RS485CTRL: AADEN Position    */
+#define USART0_RS485CTRL_AADEN_Msk                            (0x01UL << USART0_RS485CTRL_AADEN_Pos)                    /*!< USART0 RS485CTRL: AADEN Mask        */
+#define USART0_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART0 RS485CTRL: DCTRL Position    */
+#define USART0_RS485CTRL_DCTRL_Msk                            (0x01UL << USART0_RS485CTRL_DCTRL_Pos)                    /*!< USART0 RS485CTRL: DCTRL Mask        */
+#define USART0_RS485CTRL_OINV_Pos                             5                                                         /*!< USART0 RS485CTRL: OINV Position     */
+#define USART0_RS485CTRL_OINV_Msk                             (0x01UL << USART0_RS485CTRL_OINV_Pos)                     /*!< USART0 RS485CTRL: OINV Mask         */
+
+// ----------------------------------  USART0_RS485ADRMATCH  --------------------------------------
+#define USART0_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART0 RS485ADRMATCH: ADRMATCH Position */
+#define USART0_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */
+
+// -------------------------------------  USART0_RS485DLY  ----------------------------------------
+#define USART0_RS485DLY_DLY_Pos                               0                                                         /*!< USART0 RS485DLY: DLY Position       */
+#define USART0_RS485DLY_DLY_Msk                               (0x000000ffUL << USART0_RS485DLY_DLY_Pos)                 /*!< USART0 RS485DLY: DLY Mask           */
+
+// -------------------------------------  USART0_SYNCCTRL  ----------------------------------------
+#define USART0_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART0 SYNCCTRL: SYNC Position      */
+#define USART0_SYNCCTRL_SYNC_Msk                              (0x01UL << USART0_SYNCCTRL_SYNC_Pos)                      /*!< USART0 SYNCCTRL: SYNC Mask          */
+#define USART0_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART0 SYNCCTRL: CSRC Position      */
+#define USART0_SYNCCTRL_CSRC_Msk                              (0x01UL << USART0_SYNCCTRL_CSRC_Pos)                      /*!< USART0 SYNCCTRL: CSRC Mask          */
+#define USART0_SYNCCTRL_FES_Pos                               2                                                         /*!< USART0 SYNCCTRL: FES Position       */
+#define USART0_SYNCCTRL_FES_Msk                               (0x01UL << USART0_SYNCCTRL_FES_Pos)                       /*!< USART0 SYNCCTRL: FES Mask           */
+#define USART0_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART0 SYNCCTRL: TSBYPASS Position  */
+#define USART0_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART0 SYNCCTRL: TSBYPASS Mask      */
+#define USART0_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART0 SYNCCTRL: CSCEN Position     */
+#define USART0_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART0_SYNCCTRL_CSCEN_Pos)                     /*!< USART0 SYNCCTRL: CSCEN Mask         */
+#define USART0_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART0 SYNCCTRL: SSSDIS Position    */
+#define USART0_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos)                    /*!< USART0 SYNCCTRL: SSSDIS Mask        */
+#define USART0_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART0 SYNCCTRL: CCCLR Position     */
+#define USART0_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART0_SYNCCTRL_CCCLR_Pos)                     /*!< USART0 SYNCCTRL: CCCLR Mask         */
+
+// ---------------------------------------  USART0_TER  -------------------------------------------
+#define USART0_TER_TXEN_Pos                                   0                                                         /*!< USART0 TER: TXEN Position           */
+#define USART0_TER_TXEN_Msk                                   (0x01UL << USART0_TER_TXEN_Pos)                           /*!< USART0 TER: TXEN Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                USART2 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  USART2_DLL  -------------------------------------------
+#define USART2_DLL_DLLSB_Pos                                  0                                                         /*!< USART2 DLL: DLLSB Position          */
+#define USART2_DLL_DLLSB_Msk                                  (0x000000ffUL << USART2_DLL_DLLSB_Pos)                    /*!< USART2 DLL: DLLSB Mask              */
+
+// ---------------------------------------  USART2_THR  -------------------------------------------
+#define USART2_THR_THR_Pos                                    0                                                         /*!< USART2 THR: THR Position            */
+#define USART2_THR_THR_Msk                                    (0x000000ffUL << USART2_THR_THR_Pos)                      /*!< USART2 THR: THR Mask                */
+
+// ---------------------------------------  USART2_RBR  -------------------------------------------
+#define USART2_RBR_RBR_Pos                                    0                                                         /*!< USART2 RBR: RBR Position            */
+#define USART2_RBR_RBR_Msk                                    (0x000000ffUL << USART2_RBR_RBR_Pos)                      /*!< USART2 RBR: RBR Mask                */
+
+// ---------------------------------------  USART2_IER  -------------------------------------------
+#define USART2_IER_RBRIE_Pos                                  0                                                         /*!< USART2 IER: RBRIE Position          */
+#define USART2_IER_RBRIE_Msk                                  (0x01UL << USART2_IER_RBRIE_Pos)                          /*!< USART2 IER: RBRIE Mask              */
+#define USART2_IER_THREIE_Pos                                 1                                                         /*!< USART2 IER: THREIE Position         */
+#define USART2_IER_THREIE_Msk                                 (0x01UL << USART2_IER_THREIE_Pos)                         /*!< USART2 IER: THREIE Mask             */
+#define USART2_IER_RXIE_Pos                                   2                                                         /*!< USART2 IER: RXIE Position           */
+#define USART2_IER_RXIE_Msk                                   (0x01UL << USART2_IER_RXIE_Pos)                           /*!< USART2 IER: RXIE Mask               */
+#define USART2_IER_ABEOINTEN_Pos                              8                                                         /*!< USART2 IER: ABEOINTEN Position      */
+#define USART2_IER_ABEOINTEN_Msk                              (0x01UL << USART2_IER_ABEOINTEN_Pos)                      /*!< USART2 IER: ABEOINTEN Mask          */
+#define USART2_IER_ABTOINTEN_Pos                              9                                                         /*!< USART2 IER: ABTOINTEN Position      */
+#define USART2_IER_ABTOINTEN_Msk                              (0x01UL << USART2_IER_ABTOINTEN_Pos)                      /*!< USART2 IER: ABTOINTEN Mask          */
+
+// ---------------------------------------  USART2_DLM  -------------------------------------------
+#define USART2_DLM_DLMSB_Pos                                  0                                                         /*!< USART2 DLM: DLMSB Position          */
+#define USART2_DLM_DLMSB_Msk                                  (0x000000ffUL << USART2_DLM_DLMSB_Pos)                    /*!< USART2 DLM: DLMSB Mask              */
+
+// ---------------------------------------  USART2_FCR  -------------------------------------------
+#define USART2_FCR_FIFOEN_Pos                                 0                                                         /*!< USART2 FCR: FIFOEN Position         */
+#define USART2_FCR_FIFOEN_Msk                                 (0x01UL << USART2_FCR_FIFOEN_Pos)                         /*!< USART2 FCR: FIFOEN Mask             */
+#define USART2_FCR_RXFIFORES_Pos                              1                                                         /*!< USART2 FCR: RXFIFORES Position      */
+#define USART2_FCR_RXFIFORES_Msk                              (0x01UL << USART2_FCR_RXFIFORES_Pos)                      /*!< USART2 FCR: RXFIFORES Mask          */
+#define USART2_FCR_TXFIFORES_Pos                              2                                                         /*!< USART2 FCR: TXFIFORES Position      */
+#define USART2_FCR_TXFIFORES_Msk                              (0x01UL << USART2_FCR_TXFIFORES_Pos)                      /*!< USART2 FCR: TXFIFORES Mask          */
+#define USART2_FCR_DMAMODE_Pos                                3                                                         /*!< USART2 FCR: DMAMODE Position        */
+#define USART2_FCR_DMAMODE_Msk                                (0x01UL << USART2_FCR_DMAMODE_Pos)                        /*!< USART2 FCR: DMAMODE Mask            */
+#define USART2_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART2 FCR: RXTRIGLVL Position      */
+#define USART2_FCR_RXTRIGLVL_Msk                              (0x03UL << USART2_FCR_RXTRIGLVL_Pos)                      /*!< USART2 FCR: RXTRIGLVL Mask          */
+
+// ---------------------------------------  USART2_IIR  -------------------------------------------
+#define USART2_IIR_INTSTATUS_Pos                              0                                                         /*!< USART2 IIR: INTSTATUS Position      */
+#define USART2_IIR_INTSTATUS_Msk                              (0x01UL << USART2_IIR_INTSTATUS_Pos)                      /*!< USART2 IIR: INTSTATUS Mask          */
+#define USART2_IIR_INTID_Pos                                  1                                                         /*!< USART2 IIR: INTID Position          */
+#define USART2_IIR_INTID_Msk                                  (0x07UL << USART2_IIR_INTID_Pos)                          /*!< USART2 IIR: INTID Mask              */
+#define USART2_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART2 IIR: FIFOENABLE Position     */
+#define USART2_IIR_FIFOENABLE_Msk                             (0x03UL << USART2_IIR_FIFOENABLE_Pos)                     /*!< USART2 IIR: FIFOENABLE Mask         */
+#define USART2_IIR_ABEOINT_Pos                                8                                                         /*!< USART2 IIR: ABEOINT Position        */
+#define USART2_IIR_ABEOINT_Msk                                (0x01UL << USART2_IIR_ABEOINT_Pos)                        /*!< USART2 IIR: ABEOINT Mask            */
+#define USART2_IIR_ABTOINT_Pos                                9                                                         /*!< USART2 IIR: ABTOINT Position        */
+#define USART2_IIR_ABTOINT_Msk                                (0x01UL << USART2_IIR_ABTOINT_Pos)                        /*!< USART2 IIR: ABTOINT Mask            */
+
+// ---------------------------------------  USART2_LCR  -------------------------------------------
+#define USART2_LCR_WLS_Pos                                    0                                                         /*!< USART2 LCR: WLS Position            */
+#define USART2_LCR_WLS_Msk                                    (0x03UL << USART2_LCR_WLS_Pos)                            /*!< USART2 LCR: WLS Mask                */
+#define USART2_LCR_SBS_Pos                                    2                                                         /*!< USART2 LCR: SBS Position            */
+#define USART2_LCR_SBS_Msk                                    (0x01UL << USART2_LCR_SBS_Pos)                            /*!< USART2 LCR: SBS Mask                */
+#define USART2_LCR_PE_Pos                                     3                                                         /*!< USART2 LCR: PE Position             */
+#define USART2_LCR_PE_Msk                                     (0x01UL << USART2_LCR_PE_Pos)                             /*!< USART2 LCR: PE Mask                 */
+#define USART2_LCR_PS_Pos                                     4                                                         /*!< USART2 LCR: PS Position             */
+#define USART2_LCR_PS_Msk                                     (0x03UL << USART2_LCR_PS_Pos)                             /*!< USART2 LCR: PS Mask                 */
+#define USART2_LCR_BC_Pos                                     6                                                         /*!< USART2 LCR: BC Position             */
+#define USART2_LCR_BC_Msk                                     (0x01UL << USART2_LCR_BC_Pos)                             /*!< USART2 LCR: BC Mask                 */
+#define USART2_LCR_DLAB_Pos                                   7                                                         /*!< USART2 LCR: DLAB Position           */
+#define USART2_LCR_DLAB_Msk                                   (0x01UL << USART2_LCR_DLAB_Pos)                           /*!< USART2 LCR: DLAB Mask               */
+
+// ---------------------------------------  USART2_LSR  -------------------------------------------
+#define USART2_LSR_RDR_Pos                                    0                                                         /*!< USART2 LSR: RDR Position            */
+#define USART2_LSR_RDR_Msk                                    (0x01UL << USART2_LSR_RDR_Pos)                            /*!< USART2 LSR: RDR Mask                */
+#define USART2_LSR_OE_Pos                                     1                                                         /*!< USART2 LSR: OE Position             */
+#define USART2_LSR_OE_Msk                                     (0x01UL << USART2_LSR_OE_Pos)                             /*!< USART2 LSR: OE Mask                 */
+#define USART2_LSR_PE_Pos                                     2                                                         /*!< USART2 LSR: PE Position             */
+#define USART2_LSR_PE_Msk                                     (0x01UL << USART2_LSR_PE_Pos)                             /*!< USART2 LSR: PE Mask                 */
+#define USART2_LSR_FE_Pos                                     3                                                         /*!< USART2 LSR: FE Position             */
+#define USART2_LSR_FE_Msk                                     (0x01UL << USART2_LSR_FE_Pos)                             /*!< USART2 LSR: FE Mask                 */
+#define USART2_LSR_BI_Pos                                     4                                                         /*!< USART2 LSR: BI Position             */
+#define USART2_LSR_BI_Msk                                     (0x01UL << USART2_LSR_BI_Pos)                             /*!< USART2 LSR: BI Mask                 */
+#define USART2_LSR_THRE_Pos                                   5                                                         /*!< USART2 LSR: THRE Position           */
+#define USART2_LSR_THRE_Msk                                   (0x01UL << USART2_LSR_THRE_Pos)                           /*!< USART2 LSR: THRE Mask               */
+#define USART2_LSR_TEMT_Pos                                   6                                                         /*!< USART2 LSR: TEMT Position           */
+#define USART2_LSR_TEMT_Msk                                   (0x01UL << USART2_LSR_TEMT_Pos)                           /*!< USART2 LSR: TEMT Mask               */
+#define USART2_LSR_RXFE_Pos                                   7                                                         /*!< USART2 LSR: RXFE Position           */
+#define USART2_LSR_RXFE_Msk                                   (0x01UL << USART2_LSR_RXFE_Pos)                           /*!< USART2 LSR: RXFE Mask               */
+#define USART2_LSR_TXERR_Pos                                  8                                                         /*!< USART2 LSR: TXERR Position          */
+#define USART2_LSR_TXERR_Msk                                  (0x01UL << USART2_LSR_TXERR_Pos)                          /*!< USART2 LSR: TXERR Mask              */
+
+// ---------------------------------------  USART2_SCR  -------------------------------------------
+#define USART2_SCR_PAD_Pos                                    0                                                         /*!< USART2 SCR: PAD Position            */
+#define USART2_SCR_PAD_Msk                                    (0x000000ffUL << USART2_SCR_PAD_Pos)                      /*!< USART2 SCR: PAD Mask                */
+
+// ---------------------------------------  USART2_ACR  -------------------------------------------
+#define USART2_ACR_START_Pos                                  0                                                         /*!< USART2 ACR: START Position          */
+#define USART2_ACR_START_Msk                                  (0x01UL << USART2_ACR_START_Pos)                          /*!< USART2 ACR: START Mask              */
+#define USART2_ACR_MODE_Pos                                   1                                                         /*!< USART2 ACR: MODE Position           */
+#define USART2_ACR_MODE_Msk                                   (0x01UL << USART2_ACR_MODE_Pos)                           /*!< USART2 ACR: MODE Mask               */
+#define USART2_ACR_AUTORESTART_Pos                            2                                                         /*!< USART2 ACR: AUTORESTART Position    */
+#define USART2_ACR_AUTORESTART_Msk                            (0x01UL << USART2_ACR_AUTORESTART_Pos)                    /*!< USART2 ACR: AUTORESTART Mask        */
+#define USART2_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART2 ACR: ABEOINTCLR Position     */
+#define USART2_ACR_ABEOINTCLR_Msk                             (0x01UL << USART2_ACR_ABEOINTCLR_Pos)                     /*!< USART2 ACR: ABEOINTCLR Mask         */
+#define USART2_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART2 ACR: ABTOINTCLR Position     */
+#define USART2_ACR_ABTOINTCLR_Msk                             (0x01UL << USART2_ACR_ABTOINTCLR_Pos)                     /*!< USART2 ACR: ABTOINTCLR Mask         */
+
+// ---------------------------------------  USART2_ICR  -------------------------------------------
+#define USART2_ICR_IRDAEN_Pos                                 0                                                         /*!< USART2 ICR: IRDAEN Position         */
+#define USART2_ICR_IRDAEN_Msk                                 (0x01UL << USART2_ICR_IRDAEN_Pos)                         /*!< USART2 ICR: IRDAEN Mask             */
+#define USART2_ICR_IRDAINV_Pos                                1                                                         /*!< USART2 ICR: IRDAINV Position        */
+#define USART2_ICR_IRDAINV_Msk                                (0x01UL << USART2_ICR_IRDAINV_Pos)                        /*!< USART2 ICR: IRDAINV Mask            */
+#define USART2_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART2 ICR: FIXPULSEEN Position     */
+#define USART2_ICR_FIXPULSEEN_Msk                             (0x01UL << USART2_ICR_FIXPULSEEN_Pos)                     /*!< USART2 ICR: FIXPULSEEN Mask         */
+#define USART2_ICR_PULSEDIV_Pos                               3                                                         /*!< USART2 ICR: PULSEDIV Position       */
+#define USART2_ICR_PULSEDIV_Msk                               (0x07UL << USART2_ICR_PULSEDIV_Pos)                       /*!< USART2 ICR: PULSEDIV Mask           */
+
+// ---------------------------------------  USART2_FDR  -------------------------------------------
+#define USART2_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART2 FDR: DIVADDVAL Position      */
+#define USART2_FDR_DIVADDVAL_Msk                              (0x0fUL << USART2_FDR_DIVADDVAL_Pos)                      /*!< USART2 FDR: DIVADDVAL Mask          */
+#define USART2_FDR_MULVAL_Pos                                 4                                                         /*!< USART2 FDR: MULVAL Position         */
+#define USART2_FDR_MULVAL_Msk                                 (0x0fUL << USART2_FDR_MULVAL_Pos)                         /*!< USART2 FDR: MULVAL Mask             */
+
+// ---------------------------------------  USART2_OSR  -------------------------------------------
+#define USART2_OSR_OSFRAC_Pos                                 1                                                         /*!< USART2 OSR: OSFRAC Position         */
+#define USART2_OSR_OSFRAC_Msk                                 (0x07UL << USART2_OSR_OSFRAC_Pos)                         /*!< USART2 OSR: OSFRAC Mask             */
+#define USART2_OSR_OSINT_Pos                                  4                                                         /*!< USART2 OSR: OSINT Position          */
+#define USART2_OSR_OSINT_Msk                                  (0x0fUL << USART2_OSR_OSINT_Pos)                          /*!< USART2 OSR: OSINT Mask              */
+#define USART2_OSR_FDINT_Pos                                  8                                                         /*!< USART2 OSR: FDINT Position          */
+#define USART2_OSR_FDINT_Msk                                  (0x7fUL << USART2_OSR_FDINT_Pos)                          /*!< USART2 OSR: FDINT Mask              */
+
+// ---------------------------------------  USART2_HDEN  ------------------------------------------
+#define USART2_HDEN_HDEN_Pos                                  0                                                         /*!< USART2 HDEN: HDEN Position          */
+#define USART2_HDEN_HDEN_Msk                                  (0x01UL << USART2_HDEN_HDEN_Pos)                          /*!< USART2 HDEN: HDEN Mask              */
+
+// -------------------------------------  USART2_SCICTRL  -----------------------------------------
+#define USART2_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART2 SCICTRL: SCIEN Position      */
+#define USART2_SCICTRL_SCIEN_Msk                              (0x01UL << USART2_SCICTRL_SCIEN_Pos)                      /*!< USART2 SCICTRL: SCIEN Mask          */
+#define USART2_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART2 SCICTRL: NACKDIS Position    */
+#define USART2_SCICTRL_NACKDIS_Msk                            (0x01UL << USART2_SCICTRL_NACKDIS_Pos)                    /*!< USART2 SCICTRL: NACKDIS Mask        */
+#define USART2_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART2 SCICTRL: PROTSEL Position    */
+#define USART2_SCICTRL_PROTSEL_Msk                            (0x01UL << USART2_SCICTRL_PROTSEL_Pos)                    /*!< USART2 SCICTRL: PROTSEL Mask        */
+#define USART2_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART2 SCICTRL: TXRETRY Position    */
+#define USART2_SCICTRL_TXRETRY_Msk                            (0x07UL << USART2_SCICTRL_TXRETRY_Pos)                    /*!< USART2 SCICTRL: TXRETRY Mask        */
+#define USART2_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART2 SCICTRL: GUARDTIME Position  */
+#define USART2_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos)            /*!< USART2 SCICTRL: GUARDTIME Mask      */
+
+// ------------------------------------  USART2_RS485CTRL  ----------------------------------------
+#define USART2_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART2 RS485CTRL: NMMEN Position    */
+#define USART2_RS485CTRL_NMMEN_Msk                            (0x01UL << USART2_RS485CTRL_NMMEN_Pos)                    /*!< USART2 RS485CTRL: NMMEN Mask        */
+#define USART2_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART2 RS485CTRL: RXDIS Position    */
+#define USART2_RS485CTRL_RXDIS_Msk                            (0x01UL << USART2_RS485CTRL_RXDIS_Pos)                    /*!< USART2 RS485CTRL: RXDIS Mask        */
+#define USART2_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART2 RS485CTRL: AADEN Position    */
+#define USART2_RS485CTRL_AADEN_Msk                            (0x01UL << USART2_RS485CTRL_AADEN_Pos)                    /*!< USART2 RS485CTRL: AADEN Mask        */
+#define USART2_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART2 RS485CTRL: DCTRL Position    */
+#define USART2_RS485CTRL_DCTRL_Msk                            (0x01UL << USART2_RS485CTRL_DCTRL_Pos)                    /*!< USART2 RS485CTRL: DCTRL Mask        */
+#define USART2_RS485CTRL_OINV_Pos                             5                                                         /*!< USART2 RS485CTRL: OINV Position     */
+#define USART2_RS485CTRL_OINV_Msk                             (0x01UL << USART2_RS485CTRL_OINV_Pos)                     /*!< USART2 RS485CTRL: OINV Mask         */
+
+// ----------------------------------  USART2_RS485ADRMATCH  --------------------------------------
+#define USART2_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART2 RS485ADRMATCH: ADRMATCH Position */
+#define USART2_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */
+
+// -------------------------------------  USART2_RS485DLY  ----------------------------------------
+#define USART2_RS485DLY_DLY_Pos                               0                                                         /*!< USART2 RS485DLY: DLY Position       */
+#define USART2_RS485DLY_DLY_Msk                               (0x000000ffUL << USART2_RS485DLY_DLY_Pos)                 /*!< USART2 RS485DLY: DLY Mask           */
+
+// -------------------------------------  USART2_SYNCCTRL  ----------------------------------------
+#define USART2_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART2 SYNCCTRL: SYNC Position      */
+#define USART2_SYNCCTRL_SYNC_Msk                              (0x01UL << USART2_SYNCCTRL_SYNC_Pos)                      /*!< USART2 SYNCCTRL: SYNC Mask          */
+#define USART2_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART2 SYNCCTRL: CSRC Position      */
+#define USART2_SYNCCTRL_CSRC_Msk                              (0x01UL << USART2_SYNCCTRL_CSRC_Pos)                      /*!< USART2 SYNCCTRL: CSRC Mask          */
+#define USART2_SYNCCTRL_FES_Pos                               2                                                         /*!< USART2 SYNCCTRL: FES Position       */
+#define USART2_SYNCCTRL_FES_Msk                               (0x01UL << USART2_SYNCCTRL_FES_Pos)                       /*!< USART2 SYNCCTRL: FES Mask           */
+#define USART2_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART2 SYNCCTRL: TSBYPASS Position  */
+#define USART2_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART2 SYNCCTRL: TSBYPASS Mask      */
+#define USART2_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART2 SYNCCTRL: CSCEN Position     */
+#define USART2_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART2_SYNCCTRL_CSCEN_Pos)                     /*!< USART2 SYNCCTRL: CSCEN Mask         */
+#define USART2_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART2 SYNCCTRL: SSSDIS Position    */
+#define USART2_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos)                    /*!< USART2 SYNCCTRL: SSSDIS Mask        */
+#define USART2_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART2 SYNCCTRL: CCCLR Position     */
+#define USART2_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART2_SYNCCTRL_CCCLR_Pos)                     /*!< USART2 SYNCCTRL: CCCLR Mask         */
+
+// ---------------------------------------  USART2_TER  -------------------------------------------
+#define USART2_TER_TXEN_Pos                                   0                                                         /*!< USART2 TER: TXEN Position           */
+#define USART2_TER_TXEN_Msk                                   (0x01UL << USART2_TER_TXEN_Pos)                           /*!< USART2 TER: TXEN Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                USART3 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  USART3_DLL  -------------------------------------------
+#define USART3_DLL_DLLSB_Pos                                  0                                                         /*!< USART3 DLL: DLLSB Position          */
+#define USART3_DLL_DLLSB_Msk                                  (0x000000ffUL << USART3_DLL_DLLSB_Pos)                    /*!< USART3 DLL: DLLSB Mask              */
+
+// ---------------------------------------  USART3_THR  -------------------------------------------
+#define USART3_THR_THR_Pos                                    0                                                         /*!< USART3 THR: THR Position            */
+#define USART3_THR_THR_Msk                                    (0x000000ffUL << USART3_THR_THR_Pos)                      /*!< USART3 THR: THR Mask                */
+
+// ---------------------------------------  USART3_RBR  -------------------------------------------
+#define USART3_RBR_RBR_Pos                                    0                                                         /*!< USART3 RBR: RBR Position            */
+#define USART3_RBR_RBR_Msk                                    (0x000000ffUL << USART3_RBR_RBR_Pos)                      /*!< USART3 RBR: RBR Mask                */
+
+// ---------------------------------------  USART3_IER  -------------------------------------------
+#define USART3_IER_RBRIE_Pos                                  0                                                         /*!< USART3 IER: RBRIE Position          */
+#define USART3_IER_RBRIE_Msk                                  (0x01UL << USART3_IER_RBRIE_Pos)                          /*!< USART3 IER: RBRIE Mask              */
+#define USART3_IER_THREIE_Pos                                 1                                                         /*!< USART3 IER: THREIE Position         */
+#define USART3_IER_THREIE_Msk                                 (0x01UL << USART3_IER_THREIE_Pos)                         /*!< USART3 IER: THREIE Mask             */
+#define USART3_IER_RXIE_Pos                                   2                                                         /*!< USART3 IER: RXIE Position           */
+#define USART3_IER_RXIE_Msk                                   (0x01UL << USART3_IER_RXIE_Pos)                           /*!< USART3 IER: RXIE Mask               */
+#define USART3_IER_ABEOINTEN_Pos                              8                                                         /*!< USART3 IER: ABEOINTEN Position      */
+#define USART3_IER_ABEOINTEN_Msk                              (0x01UL << USART3_IER_ABEOINTEN_Pos)                      /*!< USART3 IER: ABEOINTEN Mask          */
+#define USART3_IER_ABTOINTEN_Pos                              9                                                         /*!< USART3 IER: ABTOINTEN Position      */
+#define USART3_IER_ABTOINTEN_Msk                              (0x01UL << USART3_IER_ABTOINTEN_Pos)                      /*!< USART3 IER: ABTOINTEN Mask          */
+
+// ---------------------------------------  USART3_DLM  -------------------------------------------
+#define USART3_DLM_DLMSB_Pos                                  0                                                         /*!< USART3 DLM: DLMSB Position          */
+#define USART3_DLM_DLMSB_Msk                                  (0x000000ffUL << USART3_DLM_DLMSB_Pos)                    /*!< USART3 DLM: DLMSB Mask              */
+
+// ---------------------------------------  USART3_FCR  -------------------------------------------
+#define USART3_FCR_FIFOEN_Pos                                 0                                                         /*!< USART3 FCR: FIFOEN Position         */
+#define USART3_FCR_FIFOEN_Msk                                 (0x01UL << USART3_FCR_FIFOEN_Pos)                         /*!< USART3 FCR: FIFOEN Mask             */
+#define USART3_FCR_RXFIFORES_Pos                              1                                                         /*!< USART3 FCR: RXFIFORES Position      */
+#define USART3_FCR_RXFIFORES_Msk                              (0x01UL << USART3_FCR_RXFIFORES_Pos)                      /*!< USART3 FCR: RXFIFORES Mask          */
+#define USART3_FCR_TXFIFORES_Pos                              2                                                         /*!< USART3 FCR: TXFIFORES Position      */
+#define USART3_FCR_TXFIFORES_Msk                              (0x01UL << USART3_FCR_TXFIFORES_Pos)                      /*!< USART3 FCR: TXFIFORES Mask          */
+#define USART3_FCR_DMAMODE_Pos                                3                                                         /*!< USART3 FCR: DMAMODE Position        */
+#define USART3_FCR_DMAMODE_Msk                                (0x01UL << USART3_FCR_DMAMODE_Pos)                        /*!< USART3 FCR: DMAMODE Mask            */
+#define USART3_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART3 FCR: RXTRIGLVL Position      */
+#define USART3_FCR_RXTRIGLVL_Msk                              (0x03UL << USART3_FCR_RXTRIGLVL_Pos)                      /*!< USART3 FCR: RXTRIGLVL Mask          */
+
+// ---------------------------------------  USART3_IIR  -------------------------------------------
+#define USART3_IIR_INTSTATUS_Pos                              0                                                         /*!< USART3 IIR: INTSTATUS Position      */
+#define USART3_IIR_INTSTATUS_Msk                              (0x01UL << USART3_IIR_INTSTATUS_Pos)                      /*!< USART3 IIR: INTSTATUS Mask          */
+#define USART3_IIR_INTID_Pos                                  1                                                         /*!< USART3 IIR: INTID Position          */
+#define USART3_IIR_INTID_Msk                                  (0x07UL << USART3_IIR_INTID_Pos)                          /*!< USART3 IIR: INTID Mask              */
+#define USART3_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART3 IIR: FIFOENABLE Position     */
+#define USART3_IIR_FIFOENABLE_Msk                             (0x03UL << USART3_IIR_FIFOENABLE_Pos)                     /*!< USART3 IIR: FIFOENABLE Mask         */
+#define USART3_IIR_ABEOINT_Pos                                8                                                         /*!< USART3 IIR: ABEOINT Position        */
+#define USART3_IIR_ABEOINT_Msk                                (0x01UL << USART3_IIR_ABEOINT_Pos)                        /*!< USART3 IIR: ABEOINT Mask            */
+#define USART3_IIR_ABTOINT_Pos                                9                                                         /*!< USART3 IIR: ABTOINT Position        */
+#define USART3_IIR_ABTOINT_Msk                                (0x01UL << USART3_IIR_ABTOINT_Pos)                        /*!< USART3 IIR: ABTOINT Mask            */
+
+// ---------------------------------------  USART3_LCR  -------------------------------------------
+#define USART3_LCR_WLS_Pos                                    0                                                         /*!< USART3 LCR: WLS Position            */
+#define USART3_LCR_WLS_Msk                                    (0x03UL << USART3_LCR_WLS_Pos)                            /*!< USART3 LCR: WLS Mask                */
+#define USART3_LCR_SBS_Pos                                    2                                                         /*!< USART3 LCR: SBS Position            */
+#define USART3_LCR_SBS_Msk                                    (0x01UL << USART3_LCR_SBS_Pos)                            /*!< USART3 LCR: SBS Mask                */
+#define USART3_LCR_PE_Pos                                     3                                                         /*!< USART3 LCR: PE Position             */
+#define USART3_LCR_PE_Msk                                     (0x01UL << USART3_LCR_PE_Pos)                             /*!< USART3 LCR: PE Mask                 */
+#define USART3_LCR_PS_Pos                                     4                                                         /*!< USART3 LCR: PS Position             */
+#define USART3_LCR_PS_Msk                                     (0x03UL << USART3_LCR_PS_Pos)                             /*!< USART3 LCR: PS Mask                 */
+#define USART3_LCR_BC_Pos                                     6                                                         /*!< USART3 LCR: BC Position             */
+#define USART3_LCR_BC_Msk                                     (0x01UL << USART3_LCR_BC_Pos)                             /*!< USART3 LCR: BC Mask                 */
+#define USART3_LCR_DLAB_Pos                                   7                                                         /*!< USART3 LCR: DLAB Position           */
+#define USART3_LCR_DLAB_Msk                                   (0x01UL << USART3_LCR_DLAB_Pos)                           /*!< USART3 LCR: DLAB Mask               */
+
+// ---------------------------------------  USART3_LSR  -------------------------------------------
+#define USART3_LSR_RDR_Pos                                    0                                                         /*!< USART3 LSR: RDR Position            */
+#define USART3_LSR_RDR_Msk                                    (0x01UL << USART3_LSR_RDR_Pos)                            /*!< USART3 LSR: RDR Mask                */
+#define USART3_LSR_OE_Pos                                     1                                                         /*!< USART3 LSR: OE Position             */
+#define USART3_LSR_OE_Msk                                     (0x01UL << USART3_LSR_OE_Pos)                             /*!< USART3 LSR: OE Mask                 */
+#define USART3_LSR_PE_Pos                                     2                                                         /*!< USART3 LSR: PE Position             */
+#define USART3_LSR_PE_Msk                                     (0x01UL << USART3_LSR_PE_Pos)                             /*!< USART3 LSR: PE Mask                 */
+#define USART3_LSR_FE_Pos                                     3                                                         /*!< USART3 LSR: FE Position             */
+#define USART3_LSR_FE_Msk                                     (0x01UL << USART3_LSR_FE_Pos)                             /*!< USART3 LSR: FE Mask                 */
+#define USART3_LSR_BI_Pos                                     4                                                         /*!< USART3 LSR: BI Position             */
+#define USART3_LSR_BI_Msk                                     (0x01UL << USART3_LSR_BI_Pos)                             /*!< USART3 LSR: BI Mask                 */
+#define USART3_LSR_THRE_Pos                                   5                                                         /*!< USART3 LSR: THRE Position           */
+#define USART3_LSR_THRE_Msk                                   (0x01UL << USART3_LSR_THRE_Pos)                           /*!< USART3 LSR: THRE Mask               */
+#define USART3_LSR_TEMT_Pos                                   6                                                         /*!< USART3 LSR: TEMT Position           */
+#define USART3_LSR_TEMT_Msk                                   (0x01UL << USART3_LSR_TEMT_Pos)                           /*!< USART3 LSR: TEMT Mask               */
+#define USART3_LSR_RXFE_Pos                                   7                                                         /*!< USART3 LSR: RXFE Position           */
+#define USART3_LSR_RXFE_Msk                                   (0x01UL << USART3_LSR_RXFE_Pos)                           /*!< USART3 LSR: RXFE Mask               */
+#define USART3_LSR_TXERR_Pos                                  8                                                         /*!< USART3 LSR: TXERR Position          */
+#define USART3_LSR_TXERR_Msk                                  (0x01UL << USART3_LSR_TXERR_Pos)                          /*!< USART3 LSR: TXERR Mask              */
+
+// ---------------------------------------  USART3_SCR  -------------------------------------------
+#define USART3_SCR_PAD_Pos                                    0                                                         /*!< USART3 SCR: PAD Position            */
+#define USART3_SCR_PAD_Msk                                    (0x000000ffUL << USART3_SCR_PAD_Pos)                      /*!< USART3 SCR: PAD Mask                */
+
+// ---------------------------------------  USART3_ACR  -------------------------------------------
+#define USART3_ACR_START_Pos                                  0                                                         /*!< USART3 ACR: START Position          */
+#define USART3_ACR_START_Msk                                  (0x01UL << USART3_ACR_START_Pos)                          /*!< USART3 ACR: START Mask              */
+#define USART3_ACR_MODE_Pos                                   1                                                         /*!< USART3 ACR: MODE Position           */
+#define USART3_ACR_MODE_Msk                                   (0x01UL << USART3_ACR_MODE_Pos)                           /*!< USART3 ACR: MODE Mask               */
+#define USART3_ACR_AUTORESTART_Pos                            2                                                         /*!< USART3 ACR: AUTORESTART Position    */
+#define USART3_ACR_AUTORESTART_Msk                            (0x01UL << USART3_ACR_AUTORESTART_Pos)                    /*!< USART3 ACR: AUTORESTART Mask        */
+#define USART3_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART3 ACR: ABEOINTCLR Position     */
+#define USART3_ACR_ABEOINTCLR_Msk                             (0x01UL << USART3_ACR_ABEOINTCLR_Pos)                     /*!< USART3 ACR: ABEOINTCLR Mask         */
+#define USART3_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART3 ACR: ABTOINTCLR Position     */
+#define USART3_ACR_ABTOINTCLR_Msk                             (0x01UL << USART3_ACR_ABTOINTCLR_Pos)                     /*!< USART3 ACR: ABTOINTCLR Mask         */
+
+// ---------------------------------------  USART3_ICR  -------------------------------------------
+#define USART3_ICR_IRDAEN_Pos                                 0                                                         /*!< USART3 ICR: IRDAEN Position         */
+#define USART3_ICR_IRDAEN_Msk                                 (0x01UL << USART3_ICR_IRDAEN_Pos)                         /*!< USART3 ICR: IRDAEN Mask             */
+#define USART3_ICR_IRDAINV_Pos                                1                                                         /*!< USART3 ICR: IRDAINV Position        */
+#define USART3_ICR_IRDAINV_Msk                                (0x01UL << USART3_ICR_IRDAINV_Pos)                        /*!< USART3 ICR: IRDAINV Mask            */
+#define USART3_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART3 ICR: FIXPULSEEN Position     */
+#define USART3_ICR_FIXPULSEEN_Msk                             (0x01UL << USART3_ICR_FIXPULSEEN_Pos)                     /*!< USART3 ICR: FIXPULSEEN Mask         */
+#define USART3_ICR_PULSEDIV_Pos                               3                                                         /*!< USART3 ICR: PULSEDIV Position       */
+#define USART3_ICR_PULSEDIV_Msk                               (0x07UL << USART3_ICR_PULSEDIV_Pos)                       /*!< USART3 ICR: PULSEDIV Mask           */
+
+// ---------------------------------------  USART3_FDR  -------------------------------------------
+#define USART3_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART3 FDR: DIVADDVAL Position      */
+#define USART3_FDR_DIVADDVAL_Msk                              (0x0fUL << USART3_FDR_DIVADDVAL_Pos)                      /*!< USART3 FDR: DIVADDVAL Mask          */
+#define USART3_FDR_MULVAL_Pos                                 4                                                         /*!< USART3 FDR: MULVAL Position         */
+#define USART3_FDR_MULVAL_Msk                                 (0x0fUL << USART3_FDR_MULVAL_Pos)                         /*!< USART3 FDR: MULVAL Mask             */
+
+// ---------------------------------------  USART3_OSR  -------------------------------------------
+#define USART3_OSR_OSFRAC_Pos                                 1                                                         /*!< USART3 OSR: OSFRAC Position         */
+#define USART3_OSR_OSFRAC_Msk                                 (0x07UL << USART3_OSR_OSFRAC_Pos)                         /*!< USART3 OSR: OSFRAC Mask             */
+#define USART3_OSR_OSINT_Pos                                  4                                                         /*!< USART3 OSR: OSINT Position          */
+#define USART3_OSR_OSINT_Msk                                  (0x0fUL << USART3_OSR_OSINT_Pos)                          /*!< USART3 OSR: OSINT Mask              */
+#define USART3_OSR_FDINT_Pos                                  8                                                         /*!< USART3 OSR: FDINT Position          */
+#define USART3_OSR_FDINT_Msk                                  (0x7fUL << USART3_OSR_FDINT_Pos)                          /*!< USART3 OSR: FDINT Mask              */
+
+// ---------------------------------------  USART3_HDEN  ------------------------------------------
+#define USART3_HDEN_HDEN_Pos                                  0                                                         /*!< USART3 HDEN: HDEN Position          */
+#define USART3_HDEN_HDEN_Msk                                  (0x01UL << USART3_HDEN_HDEN_Pos)                          /*!< USART3 HDEN: HDEN Mask              */
+
+// -------------------------------------  USART3_SCICTRL  -----------------------------------------
+#define USART3_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART3 SCICTRL: SCIEN Position      */
+#define USART3_SCICTRL_SCIEN_Msk                              (0x01UL << USART3_SCICTRL_SCIEN_Pos)                      /*!< USART3 SCICTRL: SCIEN Mask          */
+#define USART3_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART3 SCICTRL: NACKDIS Position    */
+#define USART3_SCICTRL_NACKDIS_Msk                            (0x01UL << USART3_SCICTRL_NACKDIS_Pos)                    /*!< USART3 SCICTRL: NACKDIS Mask        */
+#define USART3_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART3 SCICTRL: PROTSEL Position    */
+#define USART3_SCICTRL_PROTSEL_Msk                            (0x01UL << USART3_SCICTRL_PROTSEL_Pos)                    /*!< USART3 SCICTRL: PROTSEL Mask        */
+#define USART3_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART3 SCICTRL: TXRETRY Position    */
+#define USART3_SCICTRL_TXRETRY_Msk                            (0x07UL << USART3_SCICTRL_TXRETRY_Pos)                    /*!< USART3 SCICTRL: TXRETRY Mask        */
+#define USART3_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART3 SCICTRL: GUARDTIME Position  */
+#define USART3_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos)            /*!< USART3 SCICTRL: GUARDTIME Mask      */
+
+// ------------------------------------  USART3_RS485CTRL  ----------------------------------------
+#define USART3_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART3 RS485CTRL: NMMEN Position    */
+#define USART3_RS485CTRL_NMMEN_Msk                            (0x01UL << USART3_RS485CTRL_NMMEN_Pos)                    /*!< USART3 RS485CTRL: NMMEN Mask        */
+#define USART3_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART3 RS485CTRL: RXDIS Position    */
+#define USART3_RS485CTRL_RXDIS_Msk                            (0x01UL << USART3_RS485CTRL_RXDIS_Pos)                    /*!< USART3 RS485CTRL: RXDIS Mask        */
+#define USART3_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART3 RS485CTRL: AADEN Position    */
+#define USART3_RS485CTRL_AADEN_Msk                            (0x01UL << USART3_RS485CTRL_AADEN_Pos)                    /*!< USART3 RS485CTRL: AADEN Mask        */
+#define USART3_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART3 RS485CTRL: DCTRL Position    */
+#define USART3_RS485CTRL_DCTRL_Msk                            (0x01UL << USART3_RS485CTRL_DCTRL_Pos)                    /*!< USART3 RS485CTRL: DCTRL Mask        */
+#define USART3_RS485CTRL_OINV_Pos                             5                                                         /*!< USART3 RS485CTRL: OINV Position     */
+#define USART3_RS485CTRL_OINV_Msk                             (0x01UL << USART3_RS485CTRL_OINV_Pos)                     /*!< USART3 RS485CTRL: OINV Mask         */
+
+// ----------------------------------  USART3_RS485ADRMATCH  --------------------------------------
+#define USART3_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART3 RS485ADRMATCH: ADRMATCH Position */
+#define USART3_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */
+
+// -------------------------------------  USART3_RS485DLY  ----------------------------------------
+#define USART3_RS485DLY_DLY_Pos                               0                                                         /*!< USART3 RS485DLY: DLY Position       */
+#define USART3_RS485DLY_DLY_Msk                               (0x000000ffUL << USART3_RS485DLY_DLY_Pos)                 /*!< USART3 RS485DLY: DLY Mask           */
+
+// -------------------------------------  USART3_SYNCCTRL  ----------------------------------------
+#define USART3_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART3 SYNCCTRL: SYNC Position      */
+#define USART3_SYNCCTRL_SYNC_Msk                              (0x01UL << USART3_SYNCCTRL_SYNC_Pos)                      /*!< USART3 SYNCCTRL: SYNC Mask          */
+#define USART3_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART3 SYNCCTRL: CSRC Position      */
+#define USART3_SYNCCTRL_CSRC_Msk                              (0x01UL << USART3_SYNCCTRL_CSRC_Pos)                      /*!< USART3 SYNCCTRL: CSRC Mask          */
+#define USART3_SYNCCTRL_FES_Pos                               2                                                         /*!< USART3 SYNCCTRL: FES Position       */
+#define USART3_SYNCCTRL_FES_Msk                               (0x01UL << USART3_SYNCCTRL_FES_Pos)                       /*!< USART3 SYNCCTRL: FES Mask           */
+#define USART3_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART3 SYNCCTRL: TSBYPASS Position  */
+#define USART3_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART3 SYNCCTRL: TSBYPASS Mask      */
+#define USART3_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART3 SYNCCTRL: CSCEN Position     */
+#define USART3_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART3_SYNCCTRL_CSCEN_Pos)                     /*!< USART3 SYNCCTRL: CSCEN Mask         */
+#define USART3_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART3 SYNCCTRL: SSSDIS Position    */
+#define USART3_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos)                    /*!< USART3 SYNCCTRL: SSSDIS Mask        */
+#define USART3_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART3 SYNCCTRL: CCCLR Position     */
+#define USART3_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART3_SYNCCTRL_CCCLR_Pos)                     /*!< USART3 SYNCCTRL: CCCLR Mask         */
+
+// ---------------------------------------  USART3_TER  -------------------------------------------
+#define USART3_TER_TXEN_Pos                                   0                                                         /*!< USART3 TER: TXEN Position           */
+#define USART3_TER_TXEN_Msk                                   (0x01UL << USART3_TER_TXEN_Pos)                           /*!< USART3 TER: TXEN Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 UART1 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  UART1_RBR  -------------------------------------------
+#define UART1_RBR_RBR_Pos                                     0                                                         /*!< UART1 RBR: RBR Position             */
+#define UART1_RBR_RBR_Msk                                     (0x000000ffUL << UART1_RBR_RBR_Pos)                       /*!< UART1 RBR: RBR Mask                 */
+
+// ----------------------------------------  UART1_THR  -------------------------------------------
+#define UART1_THR_THR_Pos                                     0                                                         /*!< UART1 THR: THR Position             */
+#define UART1_THR_THR_Msk                                     (0x000000ffUL << UART1_THR_THR_Pos)                       /*!< UART1 THR: THR Mask                 */
+
+// ----------------------------------------  UART1_DLL  -------------------------------------------
+#define UART1_DLL_DLLSB_Pos                                   0                                                         /*!< UART1 DLL: DLLSB Position           */
+#define UART1_DLL_DLLSB_Msk                                   (0x000000ffUL << UART1_DLL_DLLSB_Pos)                     /*!< UART1 DLL: DLLSB Mask               */
+
+// ----------------------------------------  UART1_DLM  -------------------------------------------
+#define UART1_DLM_DLMSB_Pos                                   0                                                         /*!< UART1 DLM: DLMSB Position           */
+#define UART1_DLM_DLMSB_Msk                                   (0x000000ffUL << UART1_DLM_DLMSB_Pos)                     /*!< UART1 DLM: DLMSB Mask               */
+
+// ----------------------------------------  UART1_IER  -------------------------------------------
+#define UART1_IER_RBRIE_Pos                                   0                                                         /*!< UART1 IER: RBRIE Position           */
+#define UART1_IER_RBRIE_Msk                                   (0x01UL << UART1_IER_RBRIE_Pos)                           /*!< UART1 IER: RBRIE Mask               */
+#define UART1_IER_THREIE_Pos                                  1                                                         /*!< UART1 IER: THREIE Position          */
+#define UART1_IER_THREIE_Msk                                  (0x01UL << UART1_IER_THREIE_Pos)                          /*!< UART1 IER: THREIE Mask              */
+#define UART1_IER_RXIE_Pos                                    2                                                         /*!< UART1 IER: RXIE Position            */
+#define UART1_IER_RXIE_Msk                                    (0x01UL << UART1_IER_RXIE_Pos)                            /*!< UART1 IER: RXIE Mask                */
+#define UART1_IER_MSIE_Pos                                    3                                                         /*!< UART1 IER: MSIE Position            */
+#define UART1_IER_MSIE_Msk                                    (0x01UL << UART1_IER_MSIE_Pos)                            /*!< UART1 IER: MSIE Mask                */
+#define UART1_IER_CTSIE_Pos                                   7                                                         /*!< UART1 IER: CTSIE Position           */
+#define UART1_IER_CTSIE_Msk                                   (0x01UL << UART1_IER_CTSIE_Pos)                           /*!< UART1 IER: CTSIE Mask               */
+#define UART1_IER_ABEOIE_Pos                                  8                                                         /*!< UART1 IER: ABEOIE Position          */
+#define UART1_IER_ABEOIE_Msk                                  (0x01UL << UART1_IER_ABEOIE_Pos)                          /*!< UART1 IER: ABEOIE Mask              */
+#define UART1_IER_ABTOIE_Pos                                  9                                                         /*!< UART1 IER: ABTOIE Position          */
+#define UART1_IER_ABTOIE_Msk                                  (0x01UL << UART1_IER_ABTOIE_Pos)                          /*!< UART1 IER: ABTOIE Mask              */
+
+// ----------------------------------------  UART1_IIR  -------------------------------------------
+#define UART1_IIR_INTSTATUS_Pos                               0                                                         /*!< UART1 IIR: INTSTATUS Position       */
+#define UART1_IIR_INTSTATUS_Msk                               (0x01UL << UART1_IIR_INTSTATUS_Pos)                       /*!< UART1 IIR: INTSTATUS Mask           */
+#define UART1_IIR_INTID_Pos                                   1                                                         /*!< UART1 IIR: INTID Position           */
+#define UART1_IIR_INTID_Msk                                   (0x07UL << UART1_IIR_INTID_Pos)                           /*!< UART1 IIR: INTID Mask               */
+#define UART1_IIR_FIFOENABLE_Pos                              6                                                         /*!< UART1 IIR: FIFOENABLE Position      */
+#define UART1_IIR_FIFOENABLE_Msk                              (0x03UL << UART1_IIR_FIFOENABLE_Pos)                      /*!< UART1 IIR: FIFOENABLE Mask          */
+#define UART1_IIR_ABEOINT_Pos                                 8                                                         /*!< UART1 IIR: ABEOINT Position         */
+#define UART1_IIR_ABEOINT_Msk                                 (0x01UL << UART1_IIR_ABEOINT_Pos)                         /*!< UART1 IIR: ABEOINT Mask             */
+#define UART1_IIR_ABTOINT_Pos                                 9                                                         /*!< UART1 IIR: ABTOINT Position         */
+#define UART1_IIR_ABTOINT_Msk                                 (0x01UL << UART1_IIR_ABTOINT_Pos)                         /*!< UART1 IIR: ABTOINT Mask             */
+
+// ----------------------------------------  UART1_FCR  -------------------------------------------
+#define UART1_FCR_FIFOEN_Pos                                  0                                                         /*!< UART1 FCR: FIFOEN Position          */
+#define UART1_FCR_FIFOEN_Msk                                  (0x01UL << UART1_FCR_FIFOEN_Pos)                          /*!< UART1 FCR: FIFOEN Mask              */
+#define UART1_FCR_RXFIFORES_Pos                               1                                                         /*!< UART1 FCR: RXFIFORES Position       */
+#define UART1_FCR_RXFIFORES_Msk                               (0x01UL << UART1_FCR_RXFIFORES_Pos)                       /*!< UART1 FCR: RXFIFORES Mask           */
+#define UART1_FCR_TXFIFORES_Pos                               2                                                         /*!< UART1 FCR: TXFIFORES Position       */
+#define UART1_FCR_TXFIFORES_Msk                               (0x01UL << UART1_FCR_TXFIFORES_Pos)                       /*!< UART1 FCR: TXFIFORES Mask           */
+#define UART1_FCR_DMAMODE_Pos                                 3                                                         /*!< UART1 FCR: DMAMODE Position         */
+#define UART1_FCR_DMAMODE_Msk                                 (0x01UL << UART1_FCR_DMAMODE_Pos)                         /*!< UART1 FCR: DMAMODE Mask             */
+#define UART1_FCR_RXTRIGLVL_Pos                               6                                                         /*!< UART1 FCR: RXTRIGLVL Position       */
+#define UART1_FCR_RXTRIGLVL_Msk                               (0x03UL << UART1_FCR_RXTRIGLVL_Pos)                       /*!< UART1 FCR: RXTRIGLVL Mask           */
+
+// ----------------------------------------  UART1_LCR  -------------------------------------------
+#define UART1_LCR_WLS_Pos                                     0                                                         /*!< UART1 LCR: WLS Position             */
+#define UART1_LCR_WLS_Msk                                     (0x03UL << UART1_LCR_WLS_Pos)                             /*!< UART1 LCR: WLS Mask                 */
+#define UART1_LCR_SBS_Pos                                     2                                                         /*!< UART1 LCR: SBS Position             */
+#define UART1_LCR_SBS_Msk                                     (0x01UL << UART1_LCR_SBS_Pos)                             /*!< UART1 LCR: SBS Mask                 */
+#define UART1_LCR_PE_Pos                                      3                                                         /*!< UART1 LCR: PE Position              */
+#define UART1_LCR_PE_Msk                                      (0x01UL << UART1_LCR_PE_Pos)                              /*!< UART1 LCR: PE Mask                  */
+#define UART1_LCR_PS_Pos                                      4                                                         /*!< UART1 LCR: PS Position              */
+#define UART1_LCR_PS_Msk                                      (0x03UL << UART1_LCR_PS_Pos)                              /*!< UART1 LCR: PS Mask                  */
+#define UART1_LCR_BC_Pos                                      6                                                         /*!< UART1 LCR: BC Position              */
+#define UART1_LCR_BC_Msk                                      (0x01UL << UART1_LCR_BC_Pos)                              /*!< UART1 LCR: BC Mask                  */
+#define UART1_LCR_DLAB_Pos                                    7                                                         /*!< UART1 LCR: DLAB Position            */
+#define UART1_LCR_DLAB_Msk                                    (0x01UL << UART1_LCR_DLAB_Pos)                            /*!< UART1 LCR: DLAB Mask                */
+
+// ----------------------------------------  UART1_MCR  -------------------------------------------
+#define UART1_MCR_DTRCTRL_Pos                                 0                                                         /*!< UART1 MCR: DTRCTRL Position         */
+#define UART1_MCR_DTRCTRL_Msk                                 (0x01UL << UART1_MCR_DTRCTRL_Pos)                         /*!< UART1 MCR: DTRCTRL Mask             */
+#define UART1_MCR_RTSCTRL_Pos                                 1                                                         /*!< UART1 MCR: RTSCTRL Position         */
+#define UART1_MCR_RTSCTRL_Msk                                 (0x01UL << UART1_MCR_RTSCTRL_Pos)                         /*!< UART1 MCR: RTSCTRL Mask             */
+#define UART1_MCR_LMS_Pos                                     4                                                         /*!< UART1 MCR: LMS Position             */
+#define UART1_MCR_LMS_Msk                                     (0x01UL << UART1_MCR_LMS_Pos)                             /*!< UART1 MCR: LMS Mask                 */
+#define UART1_MCR_RTSEN_Pos                                   6                                                         /*!< UART1 MCR: RTSEN Position           */
+#define UART1_MCR_RTSEN_Msk                                   (0x01UL << UART1_MCR_RTSEN_Pos)                           /*!< UART1 MCR: RTSEN Mask               */
+#define UART1_MCR_CTSEN_Pos                                   7                                                         /*!< UART1 MCR: CTSEN Position           */
+#define UART1_MCR_CTSEN_Msk                                   (0x01UL << UART1_MCR_CTSEN_Pos)                           /*!< UART1 MCR: CTSEN Mask               */
+
+// ----------------------------------------  UART1_LSR  -------------------------------------------
+#define UART1_LSR_RDR_Pos                                     0                                                         /*!< UART1 LSR: RDR Position             */
+#define UART1_LSR_RDR_Msk                                     (0x01UL << UART1_LSR_RDR_Pos)                             /*!< UART1 LSR: RDR Mask                 */
+#define UART1_LSR_OE_Pos                                      1                                                         /*!< UART1 LSR: OE Position              */
+#define UART1_LSR_OE_Msk                                      (0x01UL << UART1_LSR_OE_Pos)                              /*!< UART1 LSR: OE Mask                  */
+#define UART1_LSR_PE_Pos                                      2                                                         /*!< UART1 LSR: PE Position              */
+#define UART1_LSR_PE_Msk                                      (0x01UL << UART1_LSR_PE_Pos)                              /*!< UART1 LSR: PE Mask                  */
+#define UART1_LSR_FE_Pos                                      3                                                         /*!< UART1 LSR: FE Position              */
+#define UART1_LSR_FE_Msk                                      (0x01UL << UART1_LSR_FE_Pos)                              /*!< UART1 LSR: FE Mask                  */
+#define UART1_LSR_BI_Pos                                      4                                                         /*!< UART1 LSR: BI Position              */
+#define UART1_LSR_BI_Msk                                      (0x01UL << UART1_LSR_BI_Pos)                              /*!< UART1 LSR: BI Mask                  */
+#define UART1_LSR_THRE_Pos                                    5                                                         /*!< UART1 LSR: THRE Position            */
+#define UART1_LSR_THRE_Msk                                    (0x01UL << UART1_LSR_THRE_Pos)                            /*!< UART1 LSR: THRE Mask                */
+#define UART1_LSR_TEMT_Pos                                    6                                                         /*!< UART1 LSR: TEMT Position            */
+#define UART1_LSR_TEMT_Msk                                    (0x01UL << UART1_LSR_TEMT_Pos)                            /*!< UART1 LSR: TEMT Mask                */
+#define UART1_LSR_RXFE_Pos                                    7                                                         /*!< UART1 LSR: RXFE Position            */
+#define UART1_LSR_RXFE_Msk                                    (0x01UL << UART1_LSR_RXFE_Pos)                            /*!< UART1 LSR: RXFE Mask                */
+
+// ----------------------------------------  UART1_MSR  -------------------------------------------
+#define UART1_MSR_DCTS_Pos                                    0                                                         /*!< UART1 MSR: DCTS Position            */
+#define UART1_MSR_DCTS_Msk                                    (0x01UL << UART1_MSR_DCTS_Pos)                            /*!< UART1 MSR: DCTS Mask                */
+#define UART1_MSR_DDSR_Pos                                    1                                                         /*!< UART1 MSR: DDSR Position            */
+#define UART1_MSR_DDSR_Msk                                    (0x01UL << UART1_MSR_DDSR_Pos)                            /*!< UART1 MSR: DDSR Mask                */
+#define UART1_MSR_TERI_Pos                                    2                                                         /*!< UART1 MSR: TERI Position            */
+#define UART1_MSR_TERI_Msk                                    (0x01UL << UART1_MSR_TERI_Pos)                            /*!< UART1 MSR: TERI Mask                */
+#define UART1_MSR_DDCD_Pos                                    3                                                         /*!< UART1 MSR: DDCD Position            */
+#define UART1_MSR_DDCD_Msk                                    (0x01UL << UART1_MSR_DDCD_Pos)                            /*!< UART1 MSR: DDCD Mask                */
+#define UART1_MSR_CTS_Pos                                     4                                                         /*!< UART1 MSR: CTS Position             */
+#define UART1_MSR_CTS_Msk                                     (0x01UL << UART1_MSR_CTS_Pos)                             /*!< UART1 MSR: CTS Mask                 */
+#define UART1_MSR_DSR_Pos                                     5                                                         /*!< UART1 MSR: DSR Position             */
+#define UART1_MSR_DSR_Msk                                     (0x01UL << UART1_MSR_DSR_Pos)                             /*!< UART1 MSR: DSR Mask                 */
+#define UART1_MSR_RI_Pos                                      6                                                         /*!< UART1 MSR: RI Position              */
+#define UART1_MSR_RI_Msk                                      (0x01UL << UART1_MSR_RI_Pos)                              /*!< UART1 MSR: RI Mask                  */
+#define UART1_MSR_DCD_Pos                                     7                                                         /*!< UART1 MSR: DCD Position             */
+#define UART1_MSR_DCD_Msk                                     (0x01UL << UART1_MSR_DCD_Pos)                             /*!< UART1 MSR: DCD Mask                 */
+
+// ----------------------------------------  UART1_SCR  -------------------------------------------
+#define UART1_SCR_Pad_Pos                                     0                                                         /*!< UART1 SCR: Pad Position             */
+#define UART1_SCR_Pad_Msk                                     (0x000000ffUL << UART1_SCR_Pad_Pos)                       /*!< UART1 SCR: Pad Mask                 */
+
+// ----------------------------------------  UART1_ACR  -------------------------------------------
+#define UART1_ACR_START_Pos                                   0                                                         /*!< UART1 ACR: START Position           */
+#define UART1_ACR_START_Msk                                   (0x01UL << UART1_ACR_START_Pos)                           /*!< UART1 ACR: START Mask               */
+#define UART1_ACR_MODE_Pos                                    1                                                         /*!< UART1 ACR: MODE Position            */
+#define UART1_ACR_MODE_Msk                                    (0x01UL << UART1_ACR_MODE_Pos)                            /*!< UART1 ACR: MODE Mask                */
+#define UART1_ACR_AUTORESTART_Pos                             2                                                         /*!< UART1 ACR: AUTORESTART Position     */
+#define UART1_ACR_AUTORESTART_Msk                             (0x01UL << UART1_ACR_AUTORESTART_Pos)                     /*!< UART1 ACR: AUTORESTART Mask         */
+#define UART1_ACR_ABEOINTCLR_Pos                              8                                                         /*!< UART1 ACR: ABEOINTCLR Position      */
+#define UART1_ACR_ABEOINTCLR_Msk                              (0x01UL << UART1_ACR_ABEOINTCLR_Pos)                      /*!< UART1 ACR: ABEOINTCLR Mask          */
+#define UART1_ACR_ABTOINTCLR_Pos                              9                                                         /*!< UART1 ACR: ABTOINTCLR Position      */
+#define UART1_ACR_ABTOINTCLR_Msk                              (0x01UL << UART1_ACR_ABTOINTCLR_Pos)                      /*!< UART1 ACR: ABTOINTCLR Mask          */
+
+// ----------------------------------------  UART1_FDR  -------------------------------------------
+#define UART1_FDR_DIVADDVAL_Pos                               0                                                         /*!< UART1 FDR: DIVADDVAL Position       */
+#define UART1_FDR_DIVADDVAL_Msk                               (0x0fUL << UART1_FDR_DIVADDVAL_Pos)                       /*!< UART1 FDR: DIVADDVAL Mask           */
+#define UART1_FDR_MULVAL_Pos                                  4                                                         /*!< UART1 FDR: MULVAL Position          */
+#define UART1_FDR_MULVAL_Msk                                  (0x0fUL << UART1_FDR_MULVAL_Pos)                          /*!< UART1 FDR: MULVAL Mask              */
+
+// ----------------------------------------  UART1_TER  -------------------------------------------
+#define UART1_TER_TXEN_Pos                                    7                                                         /*!< UART1 TER: TXEN Position            */
+#define UART1_TER_TXEN_Msk                                    (0x01UL << UART1_TER_TXEN_Pos)                            /*!< UART1 TER: TXEN Mask                */
+
+// -------------------------------------  UART1_RS485CTRL  ----------------------------------------
+#define UART1_RS485CTRL_NMMEN_Pos                             0                                                         /*!< UART1 RS485CTRL: NMMEN Position     */
+#define UART1_RS485CTRL_NMMEN_Msk                             (0x01UL << UART1_RS485CTRL_NMMEN_Pos)                     /*!< UART1 RS485CTRL: NMMEN Mask         */
+#define UART1_RS485CTRL_RXDIS_Pos                             1                                                         /*!< UART1 RS485CTRL: RXDIS Position     */
+#define UART1_RS485CTRL_RXDIS_Msk                             (0x01UL << UART1_RS485CTRL_RXDIS_Pos)                     /*!< UART1 RS485CTRL: RXDIS Mask         */
+#define UART1_RS485CTRL_AADEN_Pos                             2                                                         /*!< UART1 RS485CTRL: AADEN Position     */
+#define UART1_RS485CTRL_AADEN_Msk                             (0x01UL << UART1_RS485CTRL_AADEN_Pos)                     /*!< UART1 RS485CTRL: AADEN Mask         */
+#define UART1_RS485CTRL_SEL_Pos                               3                                                         /*!< UART1 RS485CTRL: SEL Position       */
+#define UART1_RS485CTRL_SEL_Msk                               (0x01UL << UART1_RS485CTRL_SEL_Pos)                       /*!< UART1 RS485CTRL: SEL Mask           */
+#define UART1_RS485CTRL_DCTRL_Pos                             4                                                         /*!< UART1 RS485CTRL: DCTRL Position     */
+#define UART1_RS485CTRL_DCTRL_Msk                             (0x01UL << UART1_RS485CTRL_DCTRL_Pos)                     /*!< UART1 RS485CTRL: DCTRL Mask         */
+#define UART1_RS485CTRL_OINV_Pos                              5                                                         /*!< UART1 RS485CTRL: OINV Position      */
+#define UART1_RS485CTRL_OINV_Msk                              (0x01UL << UART1_RS485CTRL_OINV_Pos)                      /*!< UART1 RS485CTRL: OINV Mask          */
+
+// -----------------------------------  UART1_RS485ADRMATCH  --------------------------------------
+#define UART1_RS485ADRMATCH_ADRMATCH_Pos                      0                                                         /*!< UART1 RS485ADRMATCH: ADRMATCH Position */
+#define UART1_RS485ADRMATCH_ADRMATCH_Msk                      (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos)        /*!< UART1 RS485ADRMATCH: ADRMATCH Mask  */
+
+// -------------------------------------  UART1_RS485DLY  -----------------------------------------
+#define UART1_RS485DLY_DLY_Pos                                0                                                         /*!< UART1 RS485DLY: DLY Position        */
+#define UART1_RS485DLY_DLY_Msk                                (0x000000ffUL << UART1_RS485DLY_DLY_Pos)                  /*!< UART1 RS485DLY: DLY Mask            */
+
+// --------------------------------------  UART1_FIFOLVL  -----------------------------------------
+#define UART1_FIFOLVL_RXFIFILVL_Pos                           0                                                         /*!< UART1 FIFOLVL: RXFIFILVL Position   */
+#define UART1_FIFOLVL_RXFIFILVL_Msk                           (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos)                   /*!< UART1 FIFOLVL: RXFIFILVL Mask       */
+#define UART1_FIFOLVL_TXFIFOLVL_Pos                           8                                                         /*!< UART1 FIFOLVL: TXFIFOLVL Position   */
+#define UART1_FIFOLVL_TXFIFOLVL_Msk                           (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos)                   /*!< UART1 FIFOLVL: TXFIFOLVL Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SSP0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  SSP0_CR0  --------------------------------------------
+#define SSP0_CR0_DSS_Pos                                      0                                                         /*!< SSP0 CR0: DSS Position              */
+#define SSP0_CR0_DSS_Msk                                      (0x0fUL << SSP0_CR0_DSS_Pos)                              /*!< SSP0 CR0: DSS Mask                  */
+#define SSP0_CR0_FRF_Pos                                      4                                                         /*!< SSP0 CR0: FRF Position              */
+#define SSP0_CR0_FRF_Msk                                      (0x03UL << SSP0_CR0_FRF_Pos)                              /*!< SSP0 CR0: FRF Mask                  */
+#define SSP0_CR0_CPOL_Pos                                     6                                                         /*!< SSP0 CR0: CPOL Position             */
+#define SSP0_CR0_CPOL_Msk                                     (0x01UL << SSP0_CR0_CPOL_Pos)                             /*!< SSP0 CR0: CPOL Mask                 */
+#define SSP0_CR0_CPHA_Pos                                     7                                                         /*!< SSP0 CR0: CPHA Position             */
+#define SSP0_CR0_CPHA_Msk                                     (0x01UL << SSP0_CR0_CPHA_Pos)                             /*!< SSP0 CR0: CPHA Mask                 */
+#define SSP0_CR0_SCR_Pos                                      8                                                         /*!< SSP0 CR0: SCR Position              */
+#define SSP0_CR0_SCR_Msk                                      (0x000000ffUL << SSP0_CR0_SCR_Pos)                        /*!< SSP0 CR0: SCR Mask                  */
+
+// ----------------------------------------  SSP0_CR1  --------------------------------------------
+#define SSP0_CR1_LBM_Pos                                      0                                                         /*!< SSP0 CR1: LBM Position              */
+#define SSP0_CR1_LBM_Msk                                      (0x01UL << SSP0_CR1_LBM_Pos)                              /*!< SSP0 CR1: LBM Mask                  */
+#define SSP0_CR1_SSE_Pos                                      1                                                         /*!< SSP0 CR1: SSE Position              */
+#define SSP0_CR1_SSE_Msk                                      (0x01UL << SSP0_CR1_SSE_Pos)                              /*!< SSP0 CR1: SSE Mask                  */
+#define SSP0_CR1_MS_Pos                                       2                                                         /*!< SSP0 CR1: MS Position               */
+#define SSP0_CR1_MS_Msk                                       (0x01UL << SSP0_CR1_MS_Pos)                               /*!< SSP0 CR1: MS Mask                   */
+#define SSP0_CR1_SOD_Pos                                      3                                                         /*!< SSP0 CR1: SOD Position              */
+#define SSP0_CR1_SOD_Msk                                      (0x01UL << SSP0_CR1_SOD_Pos)                              /*!< SSP0 CR1: SOD Mask                  */
+
+// -----------------------------------------  SSP0_DR  --------------------------------------------
+#define SSP0_DR_DATA_Pos                                      0                                                         /*!< SSP0 DR: DATA Position              */
+#define SSP0_DR_DATA_Msk                                      (0x0000ffffUL << SSP0_DR_DATA_Pos)                        /*!< SSP0 DR: DATA Mask                  */
+
+// -----------------------------------------  SSP0_SR  --------------------------------------------
+#define SSP0_SR_TFE_Pos                                       0                                                         /*!< SSP0 SR: TFE Position               */
+#define SSP0_SR_TFE_Msk                                       (0x01UL << SSP0_SR_TFE_Pos)                               /*!< SSP0 SR: TFE Mask                   */
+#define SSP0_SR_TNF_Pos                                       1                                                         /*!< SSP0 SR: TNF Position               */
+#define SSP0_SR_TNF_Msk                                       (0x01UL << SSP0_SR_TNF_Pos)                               /*!< SSP0 SR: TNF Mask                   */
+#define SSP0_SR_RNE_Pos                                       2                                                         /*!< SSP0 SR: RNE Position               */
+#define SSP0_SR_RNE_Msk                                       (0x01UL << SSP0_SR_RNE_Pos)                               /*!< SSP0 SR: RNE Mask                   */
+#define SSP0_SR_RFF_Pos                                       3                                                         /*!< SSP0 SR: RFF Position               */
+#define SSP0_SR_RFF_Msk                                       (0x01UL << SSP0_SR_RFF_Pos)                               /*!< SSP0 SR: RFF Mask                   */
+#define SSP0_SR_BSY_Pos                                       4                                                         /*!< SSP0 SR: BSY Position               */
+#define SSP0_SR_BSY_Msk                                       (0x01UL << SSP0_SR_BSY_Pos)                               /*!< SSP0 SR: BSY Mask                   */
+
+// ----------------------------------------  SSP0_CPSR  -------------------------------------------
+#define SSP0_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP0 CPSR: CPSDVSR Position         */
+#define SSP0_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos)                   /*!< SSP0 CPSR: CPSDVSR Mask             */
+
+// ----------------------------------------  SSP0_IMSC  -------------------------------------------
+#define SSP0_IMSC_RORIM_Pos                                   0                                                         /*!< SSP0 IMSC: RORIM Position           */
+#define SSP0_IMSC_RORIM_Msk                                   (0x01UL << SSP0_IMSC_RORIM_Pos)                           /*!< SSP0 IMSC: RORIM Mask               */
+#define SSP0_IMSC_RTIM_Pos                                    1                                                         /*!< SSP0 IMSC: RTIM Position            */
+#define SSP0_IMSC_RTIM_Msk                                    (0x01UL << SSP0_IMSC_RTIM_Pos)                            /*!< SSP0 IMSC: RTIM Mask                */
+#define SSP0_IMSC_RXIM_Pos                                    2                                                         /*!< SSP0 IMSC: RXIM Position            */
+#define SSP0_IMSC_RXIM_Msk                                    (0x01UL << SSP0_IMSC_RXIM_Pos)                            /*!< SSP0 IMSC: RXIM Mask                */
+#define SSP0_IMSC_TXIM_Pos                                    3                                                         /*!< SSP0 IMSC: TXIM Position            */
+#define SSP0_IMSC_TXIM_Msk                                    (0x01UL << SSP0_IMSC_TXIM_Pos)                            /*!< SSP0 IMSC: TXIM Mask                */
+
+// ----------------------------------------  SSP0_RIS  --------------------------------------------
+#define SSP0_RIS_RORRIS_Pos                                   0                                                         /*!< SSP0 RIS: RORRIS Position           */
+#define SSP0_RIS_RORRIS_Msk                                   (0x01UL << SSP0_RIS_RORRIS_Pos)                           /*!< SSP0 RIS: RORRIS Mask               */
+#define SSP0_RIS_RTRIS_Pos                                    1                                                         /*!< SSP0 RIS: RTRIS Position            */
+#define SSP0_RIS_RTRIS_Msk                                    (0x01UL << SSP0_RIS_RTRIS_Pos)                            /*!< SSP0 RIS: RTRIS Mask                */
+#define SSP0_RIS_RXRIS_Pos                                    2                                                         /*!< SSP0 RIS: RXRIS Position            */
+#define SSP0_RIS_RXRIS_Msk                                    (0x01UL << SSP0_RIS_RXRIS_Pos)                            /*!< SSP0 RIS: RXRIS Mask                */
+#define SSP0_RIS_TXRIS_Pos                                    3                                                         /*!< SSP0 RIS: TXRIS Position            */
+#define SSP0_RIS_TXRIS_Msk                                    (0x01UL << SSP0_RIS_TXRIS_Pos)                            /*!< SSP0 RIS: TXRIS Mask                */
+
+// ----------------------------------------  SSP0_MIS  --------------------------------------------
+#define SSP0_MIS_RORMIS_Pos                                   0                                                         /*!< SSP0 MIS: RORMIS Position           */
+#define SSP0_MIS_RORMIS_Msk                                   (0x01UL << SSP0_MIS_RORMIS_Pos)                           /*!< SSP0 MIS: RORMIS Mask               */
+#define SSP0_MIS_RTMIS_Pos                                    1                                                         /*!< SSP0 MIS: RTMIS Position            */
+#define SSP0_MIS_RTMIS_Msk                                    (0x01UL << SSP0_MIS_RTMIS_Pos)                            /*!< SSP0 MIS: RTMIS Mask                */
+#define SSP0_MIS_RXMIS_Pos                                    2                                                         /*!< SSP0 MIS: RXMIS Position            */
+#define SSP0_MIS_RXMIS_Msk                                    (0x01UL << SSP0_MIS_RXMIS_Pos)                            /*!< SSP0 MIS: RXMIS Mask                */
+#define SSP0_MIS_TXMIS_Pos                                    3                                                         /*!< SSP0 MIS: TXMIS Position            */
+#define SSP0_MIS_TXMIS_Msk                                    (0x01UL << SSP0_MIS_TXMIS_Pos)                            /*!< SSP0 MIS: TXMIS Mask                */
+
+// ----------------------------------------  SSP0_ICR  --------------------------------------------
+#define SSP0_ICR_RORIC_Pos                                    0                                                         /*!< SSP0 ICR: RORIC Position            */
+#define SSP0_ICR_RORIC_Msk                                    (0x01UL << SSP0_ICR_RORIC_Pos)                            /*!< SSP0 ICR: RORIC Mask                */
+#define SSP0_ICR_RTIC_Pos                                     1                                                         /*!< SSP0 ICR: RTIC Position             */
+#define SSP0_ICR_RTIC_Msk                                     (0x01UL << SSP0_ICR_RTIC_Pos)                             /*!< SSP0 ICR: RTIC Mask                 */
+
+// ---------------------------------------  SSP0_DMACR  -------------------------------------------
+#define SSP0_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP0 DMACR: RXDMAE Position         */
+#define SSP0_DMACR_RXDMAE_Msk                                 (0x01UL << SSP0_DMACR_RXDMAE_Pos)                         /*!< SSP0 DMACR: RXDMAE Mask             */
+#define SSP0_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP0 DMACR: TXDMAE Position         */
+#define SSP0_DMACR_TXDMAE_Msk                                 (0x01UL << SSP0_DMACR_TXDMAE_Pos)                         /*!< SSP0 DMACR: TXDMAE Mask             */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SSP1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  SSP1_CR0  --------------------------------------------
+#define SSP1_CR0_DSS_Pos                                      0                                                         /*!< SSP1 CR0: DSS Position              */
+#define SSP1_CR0_DSS_Msk                                      (0x0fUL << SSP1_CR0_DSS_Pos)                              /*!< SSP1 CR0: DSS Mask                  */
+#define SSP1_CR0_FRF_Pos                                      4                                                         /*!< SSP1 CR0: FRF Position              */
+#define SSP1_CR0_FRF_Msk                                      (0x03UL << SSP1_CR0_FRF_Pos)                              /*!< SSP1 CR0: FRF Mask                  */
+#define SSP1_CR0_CPOL_Pos                                     6                                                         /*!< SSP1 CR0: CPOL Position             */
+#define SSP1_CR0_CPOL_Msk                                     (0x01UL << SSP1_CR0_CPOL_Pos)                             /*!< SSP1 CR0: CPOL Mask                 */
+#define SSP1_CR0_CPHA_Pos                                     7                                                         /*!< SSP1 CR0: CPHA Position             */
+#define SSP1_CR0_CPHA_Msk                                     (0x01UL << SSP1_CR0_CPHA_Pos)                             /*!< SSP1 CR0: CPHA Mask                 */
+#define SSP1_CR0_SCR_Pos                                      8                                                         /*!< SSP1 CR0: SCR Position              */
+#define SSP1_CR0_SCR_Msk                                      (0x000000ffUL << SSP1_CR0_SCR_Pos)                        /*!< SSP1 CR0: SCR Mask                  */
+
+// ----------------------------------------  SSP1_CR1  --------------------------------------------
+#define SSP1_CR1_LBM_Pos                                      0                                                         /*!< SSP1 CR1: LBM Position              */
+#define SSP1_CR1_LBM_Msk                                      (0x01UL << SSP1_CR1_LBM_Pos)                              /*!< SSP1 CR1: LBM Mask                  */
+#define SSP1_CR1_SSE_Pos                                      1                                                         /*!< SSP1 CR1: SSE Position              */
+#define SSP1_CR1_SSE_Msk                                      (0x01UL << SSP1_CR1_SSE_Pos)                              /*!< SSP1 CR1: SSE Mask                  */
+#define SSP1_CR1_MS_Pos                                       2                                                         /*!< SSP1 CR1: MS Position               */
+#define SSP1_CR1_MS_Msk                                       (0x01UL << SSP1_CR1_MS_Pos)                               /*!< SSP1 CR1: MS Mask                   */
+#define SSP1_CR1_SOD_Pos                                      3                                                         /*!< SSP1 CR1: SOD Position              */
+#define SSP1_CR1_SOD_Msk                                      (0x01UL << SSP1_CR1_SOD_Pos)                              /*!< SSP1 CR1: SOD Mask                  */
+
+// -----------------------------------------  SSP1_DR  --------------------------------------------
+#define SSP1_DR_DATA_Pos                                      0                                                         /*!< SSP1 DR: DATA Position              */
+#define SSP1_DR_DATA_Msk                                      (0x0000ffffUL << SSP1_DR_DATA_Pos)                        /*!< SSP1 DR: DATA Mask                  */
+
+// -----------------------------------------  SSP1_SR  --------------------------------------------
+#define SSP1_SR_TFE_Pos                                       0                                                         /*!< SSP1 SR: TFE Position               */
+#define SSP1_SR_TFE_Msk                                       (0x01UL << SSP1_SR_TFE_Pos)                               /*!< SSP1 SR: TFE Mask                   */
+#define SSP1_SR_TNF_Pos                                       1                                                         /*!< SSP1 SR: TNF Position               */
+#define SSP1_SR_TNF_Msk                                       (0x01UL << SSP1_SR_TNF_Pos)                               /*!< SSP1 SR: TNF Mask                   */
+#define SSP1_SR_RNE_Pos                                       2                                                         /*!< SSP1 SR: RNE Position               */
+#define SSP1_SR_RNE_Msk                                       (0x01UL << SSP1_SR_RNE_Pos)                               /*!< SSP1 SR: RNE Mask                   */
+#define SSP1_SR_RFF_Pos                                       3                                                         /*!< SSP1 SR: RFF Position               */
+#define SSP1_SR_RFF_Msk                                       (0x01UL << SSP1_SR_RFF_Pos)                               /*!< SSP1 SR: RFF Mask                   */
+#define SSP1_SR_BSY_Pos                                       4                                                         /*!< SSP1 SR: BSY Position               */
+#define SSP1_SR_BSY_Msk                                       (0x01UL << SSP1_SR_BSY_Pos)                               /*!< SSP1 SR: BSY Mask                   */
+
+// ----------------------------------------  SSP1_CPSR  -------------------------------------------
+#define SSP1_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP1 CPSR: CPSDVSR Position         */
+#define SSP1_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos)                   /*!< SSP1 CPSR: CPSDVSR Mask             */
+
+// ----------------------------------------  SSP1_IMSC  -------------------------------------------
+#define SSP1_IMSC_RORIM_Pos                                   0                                                         /*!< SSP1 IMSC: RORIM Position           */
+#define SSP1_IMSC_RORIM_Msk                                   (0x01UL << SSP1_IMSC_RORIM_Pos)                           /*!< SSP1 IMSC: RORIM Mask               */
+#define SSP1_IMSC_RTIM_Pos                                    1                                                         /*!< SSP1 IMSC: RTIM Position            */
+#define SSP1_IMSC_RTIM_Msk                                    (0x01UL << SSP1_IMSC_RTIM_Pos)                            /*!< SSP1 IMSC: RTIM Mask                */
+#define SSP1_IMSC_RXIM_Pos                                    2                                                         /*!< SSP1 IMSC: RXIM Position            */
+#define SSP1_IMSC_RXIM_Msk                                    (0x01UL << SSP1_IMSC_RXIM_Pos)                            /*!< SSP1 IMSC: RXIM Mask                */
+#define SSP1_IMSC_TXIM_Pos                                    3                                                         /*!< SSP1 IMSC: TXIM Position            */
+#define SSP1_IMSC_TXIM_Msk                                    (0x01UL << SSP1_IMSC_TXIM_Pos)                            /*!< SSP1 IMSC: TXIM Mask                */
+
+// ----------------------------------------  SSP1_RIS  --------------------------------------------
+#define SSP1_RIS_RORRIS_Pos                                   0                                                         /*!< SSP1 RIS: RORRIS Position           */
+#define SSP1_RIS_RORRIS_Msk                                   (0x01UL << SSP1_RIS_RORRIS_Pos)                           /*!< SSP1 RIS: RORRIS Mask               */
+#define SSP1_RIS_RTRIS_Pos                                    1                                                         /*!< SSP1 RIS: RTRIS Position            */
+#define SSP1_RIS_RTRIS_Msk                                    (0x01UL << SSP1_RIS_RTRIS_Pos)                            /*!< SSP1 RIS: RTRIS Mask                */
+#define SSP1_RIS_RXRIS_Pos                                    2                                                         /*!< SSP1 RIS: RXRIS Position            */
+#define SSP1_RIS_RXRIS_Msk                                    (0x01UL << SSP1_RIS_RXRIS_Pos)                            /*!< SSP1 RIS: RXRIS Mask                */
+#define SSP1_RIS_TXRIS_Pos                                    3                                                         /*!< SSP1 RIS: TXRIS Position            */
+#define SSP1_RIS_TXRIS_Msk                                    (0x01UL << SSP1_RIS_TXRIS_Pos)                            /*!< SSP1 RIS: TXRIS Mask                */
+
+// ----------------------------------------  SSP1_MIS  --------------------------------------------
+#define SSP1_MIS_RORMIS_Pos                                   0                                                         /*!< SSP1 MIS: RORMIS Position           */
+#define SSP1_MIS_RORMIS_Msk                                   (0x01UL << SSP1_MIS_RORMIS_Pos)                           /*!< SSP1 MIS: RORMIS Mask               */
+#define SSP1_MIS_RTMIS_Pos                                    1                                                         /*!< SSP1 MIS: RTMIS Position            */
+#define SSP1_MIS_RTMIS_Msk                                    (0x01UL << SSP1_MIS_RTMIS_Pos)                            /*!< SSP1 MIS: RTMIS Mask                */
+#define SSP1_MIS_RXMIS_Pos                                    2                                                         /*!< SSP1 MIS: RXMIS Position            */
+#define SSP1_MIS_RXMIS_Msk                                    (0x01UL << SSP1_MIS_RXMIS_Pos)                            /*!< SSP1 MIS: RXMIS Mask                */
+#define SSP1_MIS_TXMIS_Pos                                    3                                                         /*!< SSP1 MIS: TXMIS Position            */
+#define SSP1_MIS_TXMIS_Msk                                    (0x01UL << SSP1_MIS_TXMIS_Pos)                            /*!< SSP1 MIS: TXMIS Mask                */
+
+// ----------------------------------------  SSP1_ICR  --------------------------------------------
+#define SSP1_ICR_RORIC_Pos                                    0                                                         /*!< SSP1 ICR: RORIC Position            */
+#define SSP1_ICR_RORIC_Msk                                    (0x01UL << SSP1_ICR_RORIC_Pos)                            /*!< SSP1 ICR: RORIC Mask                */
+#define SSP1_ICR_RTIC_Pos                                     1                                                         /*!< SSP1 ICR: RTIC Position             */
+#define SSP1_ICR_RTIC_Msk                                     (0x01UL << SSP1_ICR_RTIC_Pos)                             /*!< SSP1 ICR: RTIC Mask                 */
+
+// ---------------------------------------  SSP1_DMACR  -------------------------------------------
+#define SSP1_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP1 DMACR: RXDMAE Position         */
+#define SSP1_DMACR_RXDMAE_Msk                                 (0x01UL << SSP1_DMACR_RXDMAE_Pos)                         /*!< SSP1 DMACR: RXDMAE Mask             */
+#define SSP1_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP1 DMACR: TXDMAE Position         */
+#define SSP1_DMACR_TXDMAE_Msk                                 (0x01UL << SSP1_DMACR_TXDMAE_Pos)                         /*!< SSP1 DMACR: TXDMAE Mask             */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER0 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER0_IR  -------------------------------------------
+#define TIMER0_IR_MR0INT_Pos                                  0                                                         /*!< TIMER0 IR: MR0INT Position          */
+#define TIMER0_IR_MR0INT_Msk                                  (0x01UL << TIMER0_IR_MR0INT_Pos)                          /*!< TIMER0 IR: MR0INT Mask              */
+#define TIMER0_IR_MR1INT_Pos                                  1                                                         /*!< TIMER0 IR: MR1INT Position          */
+#define TIMER0_IR_MR1INT_Msk                                  (0x01UL << TIMER0_IR_MR1INT_Pos)                          /*!< TIMER0 IR: MR1INT Mask              */
+#define TIMER0_IR_MR2INT_Pos                                  2                                                         /*!< TIMER0 IR: MR2INT Position          */
+#define TIMER0_IR_MR2INT_Msk                                  (0x01UL << TIMER0_IR_MR2INT_Pos)                          /*!< TIMER0 IR: MR2INT Mask              */
+#define TIMER0_IR_MR3INT_Pos                                  3                                                         /*!< TIMER0 IR: MR3INT Position          */
+#define TIMER0_IR_MR3INT_Msk                                  (0x01UL << TIMER0_IR_MR3INT_Pos)                          /*!< TIMER0 IR: MR3INT Mask              */
+#define TIMER0_IR_CR0INT_Pos                                  4                                                         /*!< TIMER0 IR: CR0INT Position          */
+#define TIMER0_IR_CR0INT_Msk                                  (0x01UL << TIMER0_IR_CR0INT_Pos)                          /*!< TIMER0 IR: CR0INT Mask              */
+#define TIMER0_IR_CR1INT_Pos                                  5                                                         /*!< TIMER0 IR: CR1INT Position          */
+#define TIMER0_IR_CR1INT_Msk                                  (0x01UL << TIMER0_IR_CR1INT_Pos)                          /*!< TIMER0 IR: CR1INT Mask              */
+#define TIMER0_IR_CR2INT_Pos                                  6                                                         /*!< TIMER0 IR: CR2INT Position          */
+#define TIMER0_IR_CR2INT_Msk                                  (0x01UL << TIMER0_IR_CR2INT_Pos)                          /*!< TIMER0 IR: CR2INT Mask              */
+#define TIMER0_IR_CR3INT_Pos                                  7                                                         /*!< TIMER0 IR: CR3INT Position          */
+#define TIMER0_IR_CR3INT_Msk                                  (0x01UL << TIMER0_IR_CR3INT_Pos)                          /*!< TIMER0 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER0_TCR  -------------------------------------------
+#define TIMER0_TCR_CEN_Pos                                    0                                                         /*!< TIMER0 TCR: CEN Position            */
+#define TIMER0_TCR_CEN_Msk                                    (0x01UL << TIMER0_TCR_CEN_Pos)                            /*!< TIMER0 TCR: CEN Mask                */
+#define TIMER0_TCR_CRST_Pos                                   1                                                         /*!< TIMER0 TCR: CRST Position           */
+#define TIMER0_TCR_CRST_Msk                                   (0x01UL << TIMER0_TCR_CRST_Pos)                           /*!< TIMER0 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER0_TC  -------------------------------------------
+#define TIMER0_TC_TC_Pos                                      0                                                         /*!< TIMER0 TC: TC Position              */
+#define TIMER0_TC_TC_Msk                                      (0xffffffffUL << TIMER0_TC_TC_Pos)                        /*!< TIMER0 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER0_PR  -------------------------------------------
+#define TIMER0_PR_PM_Pos                                      0                                                         /*!< TIMER0 PR: PM Position              */
+#define TIMER0_PR_PM_Msk                                      (0xffffffffUL << TIMER0_PR_PM_Pos)                        /*!< TIMER0 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER0_PC  -------------------------------------------
+#define TIMER0_PC_PC_Pos                                      0                                                         /*!< TIMER0 PC: PC Position              */
+#define TIMER0_PC_PC_Msk                                      (0xffffffffUL << TIMER0_PC_PC_Pos)                        /*!< TIMER0 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER0_MCR  -------------------------------------------
+#define TIMER0_MCR_MR0I_Pos                                   0                                                         /*!< TIMER0 MCR: MR0I Position           */
+#define TIMER0_MCR_MR0I_Msk                                   (0x01UL << TIMER0_MCR_MR0I_Pos)                           /*!< TIMER0 MCR: MR0I Mask               */
+#define TIMER0_MCR_MR0R_Pos                                   1                                                         /*!< TIMER0 MCR: MR0R Position           */
+#define TIMER0_MCR_MR0R_Msk                                   (0x01UL << TIMER0_MCR_MR0R_Pos)                           /*!< TIMER0 MCR: MR0R Mask               */
+#define TIMER0_MCR_MR0S_Pos                                   2                                                         /*!< TIMER0 MCR: MR0S Position           */
+#define TIMER0_MCR_MR0S_Msk                                   (0x01UL << TIMER0_MCR_MR0S_Pos)                           /*!< TIMER0 MCR: MR0S Mask               */
+#define TIMER0_MCR_MR1I_Pos                                   3                                                         /*!< TIMER0 MCR: MR1I Position           */
+#define TIMER0_MCR_MR1I_Msk                                   (0x01UL << TIMER0_MCR_MR1I_Pos)                           /*!< TIMER0 MCR: MR1I Mask               */
+#define TIMER0_MCR_MR1R_Pos                                   4                                                         /*!< TIMER0 MCR: MR1R Position           */
+#define TIMER0_MCR_MR1R_Msk                                   (0x01UL << TIMER0_MCR_MR1R_Pos)                           /*!< TIMER0 MCR: MR1R Mask               */
+#define TIMER0_MCR_MR1S_Pos                                   5                                                         /*!< TIMER0 MCR: MR1S Position           */
+#define TIMER0_MCR_MR1S_Msk                                   (0x01UL << TIMER0_MCR_MR1S_Pos)                           /*!< TIMER0 MCR: MR1S Mask               */
+#define TIMER0_MCR_MR2I_Pos                                   6                                                         /*!< TIMER0 MCR: MR2I Position           */
+#define TIMER0_MCR_MR2I_Msk                                   (0x01UL << TIMER0_MCR_MR2I_Pos)                           /*!< TIMER0 MCR: MR2I Mask               */
+#define TIMER0_MCR_MR2R_Pos                                   7                                                         /*!< TIMER0 MCR: MR2R Position           */
+#define TIMER0_MCR_MR2R_Msk                                   (0x01UL << TIMER0_MCR_MR2R_Pos)                           /*!< TIMER0 MCR: MR2R Mask               */
+#define TIMER0_MCR_MR2S_Pos                                   8                                                         /*!< TIMER0 MCR: MR2S Position           */
+#define TIMER0_MCR_MR2S_Msk                                   (0x01UL << TIMER0_MCR_MR2S_Pos)                           /*!< TIMER0 MCR: MR2S Mask               */
+#define TIMER0_MCR_MR3I_Pos                                   9                                                         /*!< TIMER0 MCR: MR3I Position           */
+#define TIMER0_MCR_MR3I_Msk                                   (0x01UL << TIMER0_MCR_MR3I_Pos)                           /*!< TIMER0 MCR: MR3I Mask               */
+#define TIMER0_MCR_MR3R_Pos                                   10                                                        /*!< TIMER0 MCR: MR3R Position           */
+#define TIMER0_MCR_MR3R_Msk                                   (0x01UL << TIMER0_MCR_MR3R_Pos)                           /*!< TIMER0 MCR: MR3R Mask               */
+#define TIMER0_MCR_MR3S_Pos                                   11                                                        /*!< TIMER0 MCR: MR3S Position           */
+#define TIMER0_MCR_MR3S_Msk                                   (0x01UL << TIMER0_MCR_MR3S_Pos)                           /*!< TIMER0 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER0_MR0  -------------------------------------------
+#define TIMER0_MR0_MATCH_Pos                                  0                                                         /*!< TIMER0 MR0: MATCH Position          */
+#define TIMER0_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR0_MATCH_Pos)                    /*!< TIMER0 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_MR1  -------------------------------------------
+#define TIMER0_MR1_MATCH_Pos                                  0                                                         /*!< TIMER0 MR1: MATCH Position          */
+#define TIMER0_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR1_MATCH_Pos)                    /*!< TIMER0 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_MR2  -------------------------------------------
+#define TIMER0_MR2_MATCH_Pos                                  0                                                         /*!< TIMER0 MR2: MATCH Position          */
+#define TIMER0_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR2_MATCH_Pos)                    /*!< TIMER0 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_MR3  -------------------------------------------
+#define TIMER0_MR3_MATCH_Pos                                  0                                                         /*!< TIMER0 MR3: MATCH Position          */
+#define TIMER0_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR3_MATCH_Pos)                    /*!< TIMER0 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_CCR  -------------------------------------------
+#define TIMER0_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER0 CCR: CAP0RE Position         */
+#define TIMER0_CCR_CAP0RE_Msk                                 (0x01UL << TIMER0_CCR_CAP0RE_Pos)                         /*!< TIMER0 CCR: CAP0RE Mask             */
+#define TIMER0_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER0 CCR: CAP0FE Position         */
+#define TIMER0_CCR_CAP0FE_Msk                                 (0x01UL << TIMER0_CCR_CAP0FE_Pos)                         /*!< TIMER0 CCR: CAP0FE Mask             */
+#define TIMER0_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER0 CCR: CAP0I Position          */
+#define TIMER0_CCR_CAP0I_Msk                                  (0x01UL << TIMER0_CCR_CAP0I_Pos)                          /*!< TIMER0 CCR: CAP0I Mask              */
+#define TIMER0_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER0 CCR: CAP1RE Position         */
+#define TIMER0_CCR_CAP1RE_Msk                                 (0x01UL << TIMER0_CCR_CAP1RE_Pos)                         /*!< TIMER0 CCR: CAP1RE Mask             */
+#define TIMER0_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER0 CCR: CAP1FE Position         */
+#define TIMER0_CCR_CAP1FE_Msk                                 (0x01UL << TIMER0_CCR_CAP1FE_Pos)                         /*!< TIMER0 CCR: CAP1FE Mask             */
+#define TIMER0_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER0 CCR: CAP1I Position          */
+#define TIMER0_CCR_CAP1I_Msk                                  (0x01UL << TIMER0_CCR_CAP1I_Pos)                          /*!< TIMER0 CCR: CAP1I Mask              */
+#define TIMER0_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER0 CCR: CAP2RE Position         */
+#define TIMER0_CCR_CAP2RE_Msk                                 (0x01UL << TIMER0_CCR_CAP2RE_Pos)                         /*!< TIMER0 CCR: CAP2RE Mask             */
+#define TIMER0_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER0 CCR: CAP2FE Position         */
+#define TIMER0_CCR_CAP2FE_Msk                                 (0x01UL << TIMER0_CCR_CAP2FE_Pos)                         /*!< TIMER0 CCR: CAP2FE Mask             */
+#define TIMER0_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER0 CCR: CAP2I Position          */
+#define TIMER0_CCR_CAP2I_Msk                                  (0x01UL << TIMER0_CCR_CAP2I_Pos)                          /*!< TIMER0 CCR: CAP2I Mask              */
+#define TIMER0_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER0 CCR: CAP3RE Position         */
+#define TIMER0_CCR_CAP3RE_Msk                                 (0x01UL << TIMER0_CCR_CAP3RE_Pos)                         /*!< TIMER0 CCR: CAP3RE Mask             */
+#define TIMER0_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER0 CCR: CAP3FE Position         */
+#define TIMER0_CCR_CAP3FE_Msk                                 (0x01UL << TIMER0_CCR_CAP3FE_Pos)                         /*!< TIMER0 CCR: CAP3FE Mask             */
+#define TIMER0_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER0 CCR: CAP3I Position          */
+#define TIMER0_CCR_CAP3I_Msk                                  (0x01UL << TIMER0_CCR_CAP3I_Pos)                          /*!< TIMER0 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER0_CR0  -------------------------------------------
+#define TIMER0_CR0_CAP_Pos                                    0                                                         /*!< TIMER0 CR0: CAP Position            */
+#define TIMER0_CR0_CAP_Msk                                    (0xffffffffUL << TIMER0_CR0_CAP_Pos)                      /*!< TIMER0 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER0_CR1  -------------------------------------------
+#define TIMER0_CR1_CAP_Pos                                    0                                                         /*!< TIMER0 CR1: CAP Position            */
+#define TIMER0_CR1_CAP_Msk                                    (0xffffffffUL << TIMER0_CR1_CAP_Pos)                      /*!< TIMER0 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER0_CR2  -------------------------------------------
+#define TIMER0_CR2_CAP_Pos                                    0                                                         /*!< TIMER0 CR2: CAP Position            */
+#define TIMER0_CR2_CAP_Msk                                    (0xffffffffUL << TIMER0_CR2_CAP_Pos)                      /*!< TIMER0 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER0_CR3  -------------------------------------------
+#define TIMER0_CR3_CAP_Pos                                    0                                                         /*!< TIMER0 CR3: CAP Position            */
+#define TIMER0_CR3_CAP_Msk                                    (0xffffffffUL << TIMER0_CR3_CAP_Pos)                      /*!< TIMER0 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER0_EMR  -------------------------------------------
+#define TIMER0_EMR_EM0_Pos                                    0                                                         /*!< TIMER0 EMR: EM0 Position            */
+#define TIMER0_EMR_EM0_Msk                                    (0x01UL << TIMER0_EMR_EM0_Pos)                            /*!< TIMER0 EMR: EM0 Mask                */
+#define TIMER0_EMR_EM1_Pos                                    1                                                         /*!< TIMER0 EMR: EM1 Position            */
+#define TIMER0_EMR_EM1_Msk                                    (0x01UL << TIMER0_EMR_EM1_Pos)                            /*!< TIMER0 EMR: EM1 Mask                */
+#define TIMER0_EMR_EM2_Pos                                    2                                                         /*!< TIMER0 EMR: EM2 Position            */
+#define TIMER0_EMR_EM2_Msk                                    (0x01UL << TIMER0_EMR_EM2_Pos)                            /*!< TIMER0 EMR: EM2 Mask                */
+#define TIMER0_EMR_EM3_Pos                                    3                                                         /*!< TIMER0 EMR: EM3 Position            */
+#define TIMER0_EMR_EM3_Msk                                    (0x01UL << TIMER0_EMR_EM3_Pos)                            /*!< TIMER0 EMR: EM3 Mask                */
+#define TIMER0_EMR_EMC0_Pos                                   4                                                         /*!< TIMER0 EMR: EMC0 Position           */
+#define TIMER0_EMR_EMC0_Msk                                   (0x03UL << TIMER0_EMR_EMC0_Pos)                           /*!< TIMER0 EMR: EMC0 Mask               */
+#define TIMER0_EMR_EMC1_Pos                                   6                                                         /*!< TIMER0 EMR: EMC1 Position           */
+#define TIMER0_EMR_EMC1_Msk                                   (0x03UL << TIMER0_EMR_EMC1_Pos)                           /*!< TIMER0 EMR: EMC1 Mask               */
+#define TIMER0_EMR_EMC2_Pos                                   8                                                         /*!< TIMER0 EMR: EMC2 Position           */
+#define TIMER0_EMR_EMC2_Msk                                   (0x03UL << TIMER0_EMR_EMC2_Pos)                           /*!< TIMER0 EMR: EMC2 Mask               */
+#define TIMER0_EMR_EMC3_Pos                                   10                                                        /*!< TIMER0 EMR: EMC3 Position           */
+#define TIMER0_EMR_EMC3_Msk                                   (0x03UL << TIMER0_EMR_EMC3_Pos)                           /*!< TIMER0 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER0_CTCR  ------------------------------------------
+#define TIMER0_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER0 CTCR: CTMODE Position        */
+#define TIMER0_CTCR_CTMODE_Msk                                (0x03UL << TIMER0_CTCR_CTMODE_Pos)                        /*!< TIMER0 CTCR: CTMODE Mask            */
+#define TIMER0_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER0 CTCR: CINSEL Position        */
+#define TIMER0_CTCR_CINSEL_Msk                                (0x03UL << TIMER0_CTCR_CINSEL_Pos)                        /*!< TIMER0 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER1 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER1_IR  -------------------------------------------
+#define TIMER1_IR_MR0INT_Pos                                  0                                                         /*!< TIMER1 IR: MR0INT Position          */
+#define TIMER1_IR_MR0INT_Msk                                  (0x01UL << TIMER1_IR_MR0INT_Pos)                          /*!< TIMER1 IR: MR0INT Mask              */
+#define TIMER1_IR_MR1INT_Pos                                  1                                                         /*!< TIMER1 IR: MR1INT Position          */
+#define TIMER1_IR_MR1INT_Msk                                  (0x01UL << TIMER1_IR_MR1INT_Pos)                          /*!< TIMER1 IR: MR1INT Mask              */
+#define TIMER1_IR_MR2INT_Pos                                  2                                                         /*!< TIMER1 IR: MR2INT Position          */
+#define TIMER1_IR_MR2INT_Msk                                  (0x01UL << TIMER1_IR_MR2INT_Pos)                          /*!< TIMER1 IR: MR2INT Mask              */
+#define TIMER1_IR_MR3INT_Pos                                  3                                                         /*!< TIMER1 IR: MR3INT Position          */
+#define TIMER1_IR_MR3INT_Msk                                  (0x01UL << TIMER1_IR_MR3INT_Pos)                          /*!< TIMER1 IR: MR3INT Mask              */
+#define TIMER1_IR_CR0INT_Pos                                  4                                                         /*!< TIMER1 IR: CR0INT Position          */
+#define TIMER1_IR_CR0INT_Msk                                  (0x01UL << TIMER1_IR_CR0INT_Pos)                          /*!< TIMER1 IR: CR0INT Mask              */
+#define TIMER1_IR_CR1INT_Pos                                  5                                                         /*!< TIMER1 IR: CR1INT Position          */
+#define TIMER1_IR_CR1INT_Msk                                  (0x01UL << TIMER1_IR_CR1INT_Pos)                          /*!< TIMER1 IR: CR1INT Mask              */
+#define TIMER1_IR_CR2INT_Pos                                  6                                                         /*!< TIMER1 IR: CR2INT Position          */
+#define TIMER1_IR_CR2INT_Msk                                  (0x01UL << TIMER1_IR_CR2INT_Pos)                          /*!< TIMER1 IR: CR2INT Mask              */
+#define TIMER1_IR_CR3INT_Pos                                  7                                                         /*!< TIMER1 IR: CR3INT Position          */
+#define TIMER1_IR_CR3INT_Msk                                  (0x01UL << TIMER1_IR_CR3INT_Pos)                          /*!< TIMER1 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER1_TCR  -------------------------------------------
+#define TIMER1_TCR_CEN_Pos                                    0                                                         /*!< TIMER1 TCR: CEN Position            */
+#define TIMER1_TCR_CEN_Msk                                    (0x01UL << TIMER1_TCR_CEN_Pos)                            /*!< TIMER1 TCR: CEN Mask                */
+#define TIMER1_TCR_CRST_Pos                                   1                                                         /*!< TIMER1 TCR: CRST Position           */
+#define TIMER1_TCR_CRST_Msk                                   (0x01UL << TIMER1_TCR_CRST_Pos)                           /*!< TIMER1 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER1_TC  -------------------------------------------
+#define TIMER1_TC_TC_Pos                                      0                                                         /*!< TIMER1 TC: TC Position              */
+#define TIMER1_TC_TC_Msk                                      (0xffffffffUL << TIMER1_TC_TC_Pos)                        /*!< TIMER1 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER1_PR  -------------------------------------------
+#define TIMER1_PR_PM_Pos                                      0                                                         /*!< TIMER1 PR: PM Position              */
+#define TIMER1_PR_PM_Msk                                      (0xffffffffUL << TIMER1_PR_PM_Pos)                        /*!< TIMER1 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER1_PC  -------------------------------------------
+#define TIMER1_PC_PC_Pos                                      0                                                         /*!< TIMER1 PC: PC Position              */
+#define TIMER1_PC_PC_Msk                                      (0xffffffffUL << TIMER1_PC_PC_Pos)                        /*!< TIMER1 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER1_MCR  -------------------------------------------
+#define TIMER1_MCR_MR0I_Pos                                   0                                                         /*!< TIMER1 MCR: MR0I Position           */
+#define TIMER1_MCR_MR0I_Msk                                   (0x01UL << TIMER1_MCR_MR0I_Pos)                           /*!< TIMER1 MCR: MR0I Mask               */
+#define TIMER1_MCR_MR0R_Pos                                   1                                                         /*!< TIMER1 MCR: MR0R Position           */
+#define TIMER1_MCR_MR0R_Msk                                   (0x01UL << TIMER1_MCR_MR0R_Pos)                           /*!< TIMER1 MCR: MR0R Mask               */
+#define TIMER1_MCR_MR0S_Pos                                   2                                                         /*!< TIMER1 MCR: MR0S Position           */
+#define TIMER1_MCR_MR0S_Msk                                   (0x01UL << TIMER1_MCR_MR0S_Pos)                           /*!< TIMER1 MCR: MR0S Mask               */
+#define TIMER1_MCR_MR1I_Pos                                   3                                                         /*!< TIMER1 MCR: MR1I Position           */
+#define TIMER1_MCR_MR1I_Msk                                   (0x01UL << TIMER1_MCR_MR1I_Pos)                           /*!< TIMER1 MCR: MR1I Mask               */
+#define TIMER1_MCR_MR1R_Pos                                   4                                                         /*!< TIMER1 MCR: MR1R Position           */
+#define TIMER1_MCR_MR1R_Msk                                   (0x01UL << TIMER1_MCR_MR1R_Pos)                           /*!< TIMER1 MCR: MR1R Mask               */
+#define TIMER1_MCR_MR1S_Pos                                   5                                                         /*!< TIMER1 MCR: MR1S Position           */
+#define TIMER1_MCR_MR1S_Msk                                   (0x01UL << TIMER1_MCR_MR1S_Pos)                           /*!< TIMER1 MCR: MR1S Mask               */
+#define TIMER1_MCR_MR2I_Pos                                   6                                                         /*!< TIMER1 MCR: MR2I Position           */
+#define TIMER1_MCR_MR2I_Msk                                   (0x01UL << TIMER1_MCR_MR2I_Pos)                           /*!< TIMER1 MCR: MR2I Mask               */
+#define TIMER1_MCR_MR2R_Pos                                   7                                                         /*!< TIMER1 MCR: MR2R Position           */
+#define TIMER1_MCR_MR2R_Msk                                   (0x01UL << TIMER1_MCR_MR2R_Pos)                           /*!< TIMER1 MCR: MR2R Mask               */
+#define TIMER1_MCR_MR2S_Pos                                   8                                                         /*!< TIMER1 MCR: MR2S Position           */
+#define TIMER1_MCR_MR2S_Msk                                   (0x01UL << TIMER1_MCR_MR2S_Pos)                           /*!< TIMER1 MCR: MR2S Mask               */
+#define TIMER1_MCR_MR3I_Pos                                   9                                                         /*!< TIMER1 MCR: MR3I Position           */
+#define TIMER1_MCR_MR3I_Msk                                   (0x01UL << TIMER1_MCR_MR3I_Pos)                           /*!< TIMER1 MCR: MR3I Mask               */
+#define TIMER1_MCR_MR3R_Pos                                   10                                                        /*!< TIMER1 MCR: MR3R Position           */
+#define TIMER1_MCR_MR3R_Msk                                   (0x01UL << TIMER1_MCR_MR3R_Pos)                           /*!< TIMER1 MCR: MR3R Mask               */
+#define TIMER1_MCR_MR3S_Pos                                   11                                                        /*!< TIMER1 MCR: MR3S Position           */
+#define TIMER1_MCR_MR3S_Msk                                   (0x01UL << TIMER1_MCR_MR3S_Pos)                           /*!< TIMER1 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER1_MR0  -------------------------------------------
+#define TIMER1_MR0_MATCH_Pos                                  0                                                         /*!< TIMER1 MR0: MATCH Position          */
+#define TIMER1_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR0_MATCH_Pos)                    /*!< TIMER1 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_MR1  -------------------------------------------
+#define TIMER1_MR1_MATCH_Pos                                  0                                                         /*!< TIMER1 MR1: MATCH Position          */
+#define TIMER1_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR1_MATCH_Pos)                    /*!< TIMER1 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_MR2  -------------------------------------------
+#define TIMER1_MR2_MATCH_Pos                                  0                                                         /*!< TIMER1 MR2: MATCH Position          */
+#define TIMER1_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR2_MATCH_Pos)                    /*!< TIMER1 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_MR3  -------------------------------------------
+#define TIMER1_MR3_MATCH_Pos                                  0                                                         /*!< TIMER1 MR3: MATCH Position          */
+#define TIMER1_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR3_MATCH_Pos)                    /*!< TIMER1 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_CCR  -------------------------------------------
+#define TIMER1_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER1 CCR: CAP0RE Position         */
+#define TIMER1_CCR_CAP0RE_Msk                                 (0x01UL << TIMER1_CCR_CAP0RE_Pos)                         /*!< TIMER1 CCR: CAP0RE Mask             */
+#define TIMER1_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER1 CCR: CAP0FE Position         */
+#define TIMER1_CCR_CAP0FE_Msk                                 (0x01UL << TIMER1_CCR_CAP0FE_Pos)                         /*!< TIMER1 CCR: CAP0FE Mask             */
+#define TIMER1_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER1 CCR: CAP0I Position          */
+#define TIMER1_CCR_CAP0I_Msk                                  (0x01UL << TIMER1_CCR_CAP0I_Pos)                          /*!< TIMER1 CCR: CAP0I Mask              */
+#define TIMER1_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER1 CCR: CAP1RE Position         */
+#define TIMER1_CCR_CAP1RE_Msk                                 (0x01UL << TIMER1_CCR_CAP1RE_Pos)                         /*!< TIMER1 CCR: CAP1RE Mask             */
+#define TIMER1_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER1 CCR: CAP1FE Position         */
+#define TIMER1_CCR_CAP1FE_Msk                                 (0x01UL << TIMER1_CCR_CAP1FE_Pos)                         /*!< TIMER1 CCR: CAP1FE Mask             */
+#define TIMER1_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER1 CCR: CAP1I Position          */
+#define TIMER1_CCR_CAP1I_Msk                                  (0x01UL << TIMER1_CCR_CAP1I_Pos)                          /*!< TIMER1 CCR: CAP1I Mask              */
+#define TIMER1_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER1 CCR: CAP2RE Position         */
+#define TIMER1_CCR_CAP2RE_Msk                                 (0x01UL << TIMER1_CCR_CAP2RE_Pos)                         /*!< TIMER1 CCR: CAP2RE Mask             */
+#define TIMER1_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER1 CCR: CAP2FE Position         */
+#define TIMER1_CCR_CAP2FE_Msk                                 (0x01UL << TIMER1_CCR_CAP2FE_Pos)                         /*!< TIMER1 CCR: CAP2FE Mask             */
+#define TIMER1_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER1 CCR: CAP2I Position          */
+#define TIMER1_CCR_CAP2I_Msk                                  (0x01UL << TIMER1_CCR_CAP2I_Pos)                          /*!< TIMER1 CCR: CAP2I Mask              */
+#define TIMER1_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER1 CCR: CAP3RE Position         */
+#define TIMER1_CCR_CAP3RE_Msk                                 (0x01UL << TIMER1_CCR_CAP3RE_Pos)                         /*!< TIMER1 CCR: CAP3RE Mask             */
+#define TIMER1_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER1 CCR: CAP3FE Position         */
+#define TIMER1_CCR_CAP3FE_Msk                                 (0x01UL << TIMER1_CCR_CAP3FE_Pos)                         /*!< TIMER1 CCR: CAP3FE Mask             */
+#define TIMER1_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER1 CCR: CAP3I Position          */
+#define TIMER1_CCR_CAP3I_Msk                                  (0x01UL << TIMER1_CCR_CAP3I_Pos)                          /*!< TIMER1 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER1_CR0  -------------------------------------------
+#define TIMER1_CR0_CAP_Pos                                    0                                                         /*!< TIMER1 CR0: CAP Position            */
+#define TIMER1_CR0_CAP_Msk                                    (0xffffffffUL << TIMER1_CR0_CAP_Pos)                      /*!< TIMER1 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER1_CR1  -------------------------------------------
+#define TIMER1_CR1_CAP_Pos                                    0                                                         /*!< TIMER1 CR1: CAP Position            */
+#define TIMER1_CR1_CAP_Msk                                    (0xffffffffUL << TIMER1_CR1_CAP_Pos)                      /*!< TIMER1 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER1_CR2  -------------------------------------------
+#define TIMER1_CR2_CAP_Pos                                    0                                                         /*!< TIMER1 CR2: CAP Position            */
+#define TIMER1_CR2_CAP_Msk                                    (0xffffffffUL << TIMER1_CR2_CAP_Pos)                      /*!< TIMER1 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER1_CR3  -------------------------------------------
+#define TIMER1_CR3_CAP_Pos                                    0                                                         /*!< TIMER1 CR3: CAP Position            */
+#define TIMER1_CR3_CAP_Msk                                    (0xffffffffUL << TIMER1_CR3_CAP_Pos)                      /*!< TIMER1 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER1_EMR  -------------------------------------------
+#define TIMER1_EMR_EM0_Pos                                    0                                                         /*!< TIMER1 EMR: EM0 Position            */
+#define TIMER1_EMR_EM0_Msk                                    (0x01UL << TIMER1_EMR_EM0_Pos)                            /*!< TIMER1 EMR: EM0 Mask                */
+#define TIMER1_EMR_EM1_Pos                                    1                                                         /*!< TIMER1 EMR: EM1 Position            */
+#define TIMER1_EMR_EM1_Msk                                    (0x01UL << TIMER1_EMR_EM1_Pos)                            /*!< TIMER1 EMR: EM1 Mask                */
+#define TIMER1_EMR_EM2_Pos                                    2                                                         /*!< TIMER1 EMR: EM2 Position            */
+#define TIMER1_EMR_EM2_Msk                                    (0x01UL << TIMER1_EMR_EM2_Pos)                            /*!< TIMER1 EMR: EM2 Mask                */
+#define TIMER1_EMR_EM3_Pos                                    3                                                         /*!< TIMER1 EMR: EM3 Position            */
+#define TIMER1_EMR_EM3_Msk                                    (0x01UL << TIMER1_EMR_EM3_Pos)                            /*!< TIMER1 EMR: EM3 Mask                */
+#define TIMER1_EMR_EMC0_Pos                                   4                                                         /*!< TIMER1 EMR: EMC0 Position           */
+#define TIMER1_EMR_EMC0_Msk                                   (0x03UL << TIMER1_EMR_EMC0_Pos)                           /*!< TIMER1 EMR: EMC0 Mask               */
+#define TIMER1_EMR_EMC1_Pos                                   6                                                         /*!< TIMER1 EMR: EMC1 Position           */
+#define TIMER1_EMR_EMC1_Msk                                   (0x03UL << TIMER1_EMR_EMC1_Pos)                           /*!< TIMER1 EMR: EMC1 Mask               */
+#define TIMER1_EMR_EMC2_Pos                                   8                                                         /*!< TIMER1 EMR: EMC2 Position           */
+#define TIMER1_EMR_EMC2_Msk                                   (0x03UL << TIMER1_EMR_EMC2_Pos)                           /*!< TIMER1 EMR: EMC2 Mask               */
+#define TIMER1_EMR_EMC3_Pos                                   10                                                        /*!< TIMER1 EMR: EMC3 Position           */
+#define TIMER1_EMR_EMC3_Msk                                   (0x03UL << TIMER1_EMR_EMC3_Pos)                           /*!< TIMER1 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER1_CTCR  ------------------------------------------
+#define TIMER1_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER1 CTCR: CTMODE Position        */
+#define TIMER1_CTCR_CTMODE_Msk                                (0x03UL << TIMER1_CTCR_CTMODE_Pos)                        /*!< TIMER1 CTCR: CTMODE Mask            */
+#define TIMER1_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER1 CTCR: CINSEL Position        */
+#define TIMER1_CTCR_CINSEL_Msk                                (0x03UL << TIMER1_CTCR_CINSEL_Pos)                        /*!< TIMER1 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER2 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER2_IR  -------------------------------------------
+#define TIMER2_IR_MR0INT_Pos                                  0                                                         /*!< TIMER2 IR: MR0INT Position          */
+#define TIMER2_IR_MR0INT_Msk                                  (0x01UL << TIMER2_IR_MR0INT_Pos)                          /*!< TIMER2 IR: MR0INT Mask              */
+#define TIMER2_IR_MR1INT_Pos                                  1                                                         /*!< TIMER2 IR: MR1INT Position          */
+#define TIMER2_IR_MR1INT_Msk                                  (0x01UL << TIMER2_IR_MR1INT_Pos)                          /*!< TIMER2 IR: MR1INT Mask              */
+#define TIMER2_IR_MR2INT_Pos                                  2                                                         /*!< TIMER2 IR: MR2INT Position          */
+#define TIMER2_IR_MR2INT_Msk                                  (0x01UL << TIMER2_IR_MR2INT_Pos)                          /*!< TIMER2 IR: MR2INT Mask              */
+#define TIMER2_IR_MR3INT_Pos                                  3                                                         /*!< TIMER2 IR: MR3INT Position          */
+#define TIMER2_IR_MR3INT_Msk                                  (0x01UL << TIMER2_IR_MR3INT_Pos)                          /*!< TIMER2 IR: MR3INT Mask              */
+#define TIMER2_IR_CR0INT_Pos                                  4                                                         /*!< TIMER2 IR: CR0INT Position          */
+#define TIMER2_IR_CR0INT_Msk                                  (0x01UL << TIMER2_IR_CR0INT_Pos)                          /*!< TIMER2 IR: CR0INT Mask              */
+#define TIMER2_IR_CR1INT_Pos                                  5                                                         /*!< TIMER2 IR: CR1INT Position          */
+#define TIMER2_IR_CR1INT_Msk                                  (0x01UL << TIMER2_IR_CR1INT_Pos)                          /*!< TIMER2 IR: CR1INT Mask              */
+#define TIMER2_IR_CR2INT_Pos                                  6                                                         /*!< TIMER2 IR: CR2INT Position          */
+#define TIMER2_IR_CR2INT_Msk                                  (0x01UL << TIMER2_IR_CR2INT_Pos)                          /*!< TIMER2 IR: CR2INT Mask              */
+#define TIMER2_IR_CR3INT_Pos                                  7                                                         /*!< TIMER2 IR: CR3INT Position          */
+#define TIMER2_IR_CR3INT_Msk                                  (0x01UL << TIMER2_IR_CR3INT_Pos)                          /*!< TIMER2 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER2_TCR  -------------------------------------------
+#define TIMER2_TCR_CEN_Pos                                    0                                                         /*!< TIMER2 TCR: CEN Position            */
+#define TIMER2_TCR_CEN_Msk                                    (0x01UL << TIMER2_TCR_CEN_Pos)                            /*!< TIMER2 TCR: CEN Mask                */
+#define TIMER2_TCR_CRST_Pos                                   1                                                         /*!< TIMER2 TCR: CRST Position           */
+#define TIMER2_TCR_CRST_Msk                                   (0x01UL << TIMER2_TCR_CRST_Pos)                           /*!< TIMER2 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER2_TC  -------------------------------------------
+#define TIMER2_TC_TC_Pos                                      0                                                         /*!< TIMER2 TC: TC Position              */
+#define TIMER2_TC_TC_Msk                                      (0xffffffffUL << TIMER2_TC_TC_Pos)                        /*!< TIMER2 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER2_PR  -------------------------------------------
+#define TIMER2_PR_PM_Pos                                      0                                                         /*!< TIMER2 PR: PM Position              */
+#define TIMER2_PR_PM_Msk                                      (0xffffffffUL << TIMER2_PR_PM_Pos)                        /*!< TIMER2 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER2_PC  -------------------------------------------
+#define TIMER2_PC_PC_Pos                                      0                                                         /*!< TIMER2 PC: PC Position              */
+#define TIMER2_PC_PC_Msk                                      (0xffffffffUL << TIMER2_PC_PC_Pos)                        /*!< TIMER2 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER2_MCR  -------------------------------------------
+#define TIMER2_MCR_MR0I_Pos                                   0                                                         /*!< TIMER2 MCR: MR0I Position           */
+#define TIMER2_MCR_MR0I_Msk                                   (0x01UL << TIMER2_MCR_MR0I_Pos)                           /*!< TIMER2 MCR: MR0I Mask               */
+#define TIMER2_MCR_MR0R_Pos                                   1                                                         /*!< TIMER2 MCR: MR0R Position           */
+#define TIMER2_MCR_MR0R_Msk                                   (0x01UL << TIMER2_MCR_MR0R_Pos)                           /*!< TIMER2 MCR: MR0R Mask               */
+#define TIMER2_MCR_MR0S_Pos                                   2                                                         /*!< TIMER2 MCR: MR0S Position           */
+#define TIMER2_MCR_MR0S_Msk                                   (0x01UL << TIMER2_MCR_MR0S_Pos)                           /*!< TIMER2 MCR: MR0S Mask               */
+#define TIMER2_MCR_MR1I_Pos                                   3                                                         /*!< TIMER2 MCR: MR1I Position           */
+#define TIMER2_MCR_MR1I_Msk                                   (0x01UL << TIMER2_MCR_MR1I_Pos)                           /*!< TIMER2 MCR: MR1I Mask               */
+#define TIMER2_MCR_MR1R_Pos                                   4                                                         /*!< TIMER2 MCR: MR1R Position           */
+#define TIMER2_MCR_MR1R_Msk                                   (0x01UL << TIMER2_MCR_MR1R_Pos)                           /*!< TIMER2 MCR: MR1R Mask               */
+#define TIMER2_MCR_MR1S_Pos                                   5                                                         /*!< TIMER2 MCR: MR1S Position           */
+#define TIMER2_MCR_MR1S_Msk                                   (0x01UL << TIMER2_MCR_MR1S_Pos)                           /*!< TIMER2 MCR: MR1S Mask               */
+#define TIMER2_MCR_MR2I_Pos                                   6                                                         /*!< TIMER2 MCR: MR2I Position           */
+#define TIMER2_MCR_MR2I_Msk                                   (0x01UL << TIMER2_MCR_MR2I_Pos)                           /*!< TIMER2 MCR: MR2I Mask               */
+#define TIMER2_MCR_MR2R_Pos                                   7                                                         /*!< TIMER2 MCR: MR2R Position           */
+#define TIMER2_MCR_MR2R_Msk                                   (0x01UL << TIMER2_MCR_MR2R_Pos)                           /*!< TIMER2 MCR: MR2R Mask               */
+#define TIMER2_MCR_MR2S_Pos                                   8                                                         /*!< TIMER2 MCR: MR2S Position           */
+#define TIMER2_MCR_MR2S_Msk                                   (0x01UL << TIMER2_MCR_MR2S_Pos)                           /*!< TIMER2 MCR: MR2S Mask               */
+#define TIMER2_MCR_MR3I_Pos                                   9                                                         /*!< TIMER2 MCR: MR3I Position           */
+#define TIMER2_MCR_MR3I_Msk                                   (0x01UL << TIMER2_MCR_MR3I_Pos)                           /*!< TIMER2 MCR: MR3I Mask               */
+#define TIMER2_MCR_MR3R_Pos                                   10                                                        /*!< TIMER2 MCR: MR3R Position           */
+#define TIMER2_MCR_MR3R_Msk                                   (0x01UL << TIMER2_MCR_MR3R_Pos)                           /*!< TIMER2 MCR: MR3R Mask               */
+#define TIMER2_MCR_MR3S_Pos                                   11                                                        /*!< TIMER2 MCR: MR3S Position           */
+#define TIMER2_MCR_MR3S_Msk                                   (0x01UL << TIMER2_MCR_MR3S_Pos)                           /*!< TIMER2 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER2_MR0  -------------------------------------------
+#define TIMER2_MR0_MATCH_Pos                                  0                                                         /*!< TIMER2 MR0: MATCH Position          */
+#define TIMER2_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR0_MATCH_Pos)                    /*!< TIMER2 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_MR1  -------------------------------------------
+#define TIMER2_MR1_MATCH_Pos                                  0                                                         /*!< TIMER2 MR1: MATCH Position          */
+#define TIMER2_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR1_MATCH_Pos)                    /*!< TIMER2 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_MR2  -------------------------------------------
+#define TIMER2_MR2_MATCH_Pos                                  0                                                         /*!< TIMER2 MR2: MATCH Position          */
+#define TIMER2_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR2_MATCH_Pos)                    /*!< TIMER2 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_MR3  -------------------------------------------
+#define TIMER2_MR3_MATCH_Pos                                  0                                                         /*!< TIMER2 MR3: MATCH Position          */
+#define TIMER2_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR3_MATCH_Pos)                    /*!< TIMER2 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_CCR  -------------------------------------------
+#define TIMER2_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER2 CCR: CAP0RE Position         */
+#define TIMER2_CCR_CAP0RE_Msk                                 (0x01UL << TIMER2_CCR_CAP0RE_Pos)                         /*!< TIMER2 CCR: CAP0RE Mask             */
+#define TIMER2_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER2 CCR: CAP0FE Position         */
+#define TIMER2_CCR_CAP0FE_Msk                                 (0x01UL << TIMER2_CCR_CAP0FE_Pos)                         /*!< TIMER2 CCR: CAP0FE Mask             */
+#define TIMER2_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER2 CCR: CAP0I Position          */
+#define TIMER2_CCR_CAP0I_Msk                                  (0x01UL << TIMER2_CCR_CAP0I_Pos)                          /*!< TIMER2 CCR: CAP0I Mask              */
+#define TIMER2_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER2 CCR: CAP1RE Position         */
+#define TIMER2_CCR_CAP1RE_Msk                                 (0x01UL << TIMER2_CCR_CAP1RE_Pos)                         /*!< TIMER2 CCR: CAP1RE Mask             */
+#define TIMER2_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER2 CCR: CAP1FE Position         */
+#define TIMER2_CCR_CAP1FE_Msk                                 (0x01UL << TIMER2_CCR_CAP1FE_Pos)                         /*!< TIMER2 CCR: CAP1FE Mask             */
+#define TIMER2_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER2 CCR: CAP1I Position          */
+#define TIMER2_CCR_CAP1I_Msk                                  (0x01UL << TIMER2_CCR_CAP1I_Pos)                          /*!< TIMER2 CCR: CAP1I Mask              */
+#define TIMER2_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER2 CCR: CAP2RE Position         */
+#define TIMER2_CCR_CAP2RE_Msk                                 (0x01UL << TIMER2_CCR_CAP2RE_Pos)                         /*!< TIMER2 CCR: CAP2RE Mask             */
+#define TIMER2_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER2 CCR: CAP2FE Position         */
+#define TIMER2_CCR_CAP2FE_Msk                                 (0x01UL << TIMER2_CCR_CAP2FE_Pos)                         /*!< TIMER2 CCR: CAP2FE Mask             */
+#define TIMER2_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER2 CCR: CAP2I Position          */
+#define TIMER2_CCR_CAP2I_Msk                                  (0x01UL << TIMER2_CCR_CAP2I_Pos)                          /*!< TIMER2 CCR: CAP2I Mask              */
+#define TIMER2_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER2 CCR: CAP3RE Position         */
+#define TIMER2_CCR_CAP3RE_Msk                                 (0x01UL << TIMER2_CCR_CAP3RE_Pos)                         /*!< TIMER2 CCR: CAP3RE Mask             */
+#define TIMER2_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER2 CCR: CAP3FE Position         */
+#define TIMER2_CCR_CAP3FE_Msk                                 (0x01UL << TIMER2_CCR_CAP3FE_Pos)                         /*!< TIMER2 CCR: CAP3FE Mask             */
+#define TIMER2_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER2 CCR: CAP3I Position          */
+#define TIMER2_CCR_CAP3I_Msk                                  (0x01UL << TIMER2_CCR_CAP3I_Pos)                          /*!< TIMER2 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER2_CR0  -------------------------------------------
+#define TIMER2_CR0_CAP_Pos                                    0                                                         /*!< TIMER2 CR0: CAP Position            */
+#define TIMER2_CR0_CAP_Msk                                    (0xffffffffUL << TIMER2_CR0_CAP_Pos)                      /*!< TIMER2 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER2_CR1  -------------------------------------------
+#define TIMER2_CR1_CAP_Pos                                    0                                                         /*!< TIMER2 CR1: CAP Position            */
+#define TIMER2_CR1_CAP_Msk                                    (0xffffffffUL << TIMER2_CR1_CAP_Pos)                      /*!< TIMER2 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER2_CR2  -------------------------------------------
+#define TIMER2_CR2_CAP_Pos                                    0                                                         /*!< TIMER2 CR2: CAP Position            */
+#define TIMER2_CR2_CAP_Msk                                    (0xffffffffUL << TIMER2_CR2_CAP_Pos)                      /*!< TIMER2 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER2_CR3  -------------------------------------------
+#define TIMER2_CR3_CAP_Pos                                    0                                                         /*!< TIMER2 CR3: CAP Position            */
+#define TIMER2_CR3_CAP_Msk                                    (0xffffffffUL << TIMER2_CR3_CAP_Pos)                      /*!< TIMER2 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER2_EMR  -------------------------------------------
+#define TIMER2_EMR_EM0_Pos                                    0                                                         /*!< TIMER2 EMR: EM0 Position            */
+#define TIMER2_EMR_EM0_Msk                                    (0x01UL << TIMER2_EMR_EM0_Pos)                            /*!< TIMER2 EMR: EM0 Mask                */
+#define TIMER2_EMR_EM1_Pos                                    1                                                         /*!< TIMER2 EMR: EM1 Position            */
+#define TIMER2_EMR_EM1_Msk                                    (0x01UL << TIMER2_EMR_EM1_Pos)                            /*!< TIMER2 EMR: EM1 Mask                */
+#define TIMER2_EMR_EM2_Pos                                    2                                                         /*!< TIMER2 EMR: EM2 Position            */
+#define TIMER2_EMR_EM2_Msk                                    (0x01UL << TIMER2_EMR_EM2_Pos)                            /*!< TIMER2 EMR: EM2 Mask                */
+#define TIMER2_EMR_EM3_Pos                                    3                                                         /*!< TIMER2 EMR: EM3 Position            */
+#define TIMER2_EMR_EM3_Msk                                    (0x01UL << TIMER2_EMR_EM3_Pos)                            /*!< TIMER2 EMR: EM3 Mask                */
+#define TIMER2_EMR_EMC0_Pos                                   4                                                         /*!< TIMER2 EMR: EMC0 Position           */
+#define TIMER2_EMR_EMC0_Msk                                   (0x03UL << TIMER2_EMR_EMC0_Pos)                           /*!< TIMER2 EMR: EMC0 Mask               */
+#define TIMER2_EMR_EMC1_Pos                                   6                                                         /*!< TIMER2 EMR: EMC1 Position           */
+#define TIMER2_EMR_EMC1_Msk                                   (0x03UL << TIMER2_EMR_EMC1_Pos)                           /*!< TIMER2 EMR: EMC1 Mask               */
+#define TIMER2_EMR_EMC2_Pos                                   8                                                         /*!< TIMER2 EMR: EMC2 Position           */
+#define TIMER2_EMR_EMC2_Msk                                   (0x03UL << TIMER2_EMR_EMC2_Pos)                           /*!< TIMER2 EMR: EMC2 Mask               */
+#define TIMER2_EMR_EMC3_Pos                                   10                                                        /*!< TIMER2 EMR: EMC3 Position           */
+#define TIMER2_EMR_EMC3_Msk                                   (0x03UL << TIMER2_EMR_EMC3_Pos)                           /*!< TIMER2 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER2_CTCR  ------------------------------------------
+#define TIMER2_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER2 CTCR: CTMODE Position        */
+#define TIMER2_CTCR_CTMODE_Msk                                (0x03UL << TIMER2_CTCR_CTMODE_Pos)                        /*!< TIMER2 CTCR: CTMODE Mask            */
+#define TIMER2_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER2 CTCR: CINSEL Position        */
+#define TIMER2_CTCR_CINSEL_Msk                                (0x03UL << TIMER2_CTCR_CINSEL_Pos)                        /*!< TIMER2 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER3 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER3_IR  -------------------------------------------
+#define TIMER3_IR_MR0INT_Pos                                  0                                                         /*!< TIMER3 IR: MR0INT Position          */
+#define TIMER3_IR_MR0INT_Msk                                  (0x01UL << TIMER3_IR_MR0INT_Pos)                          /*!< TIMER3 IR: MR0INT Mask              */
+#define TIMER3_IR_MR1INT_Pos                                  1                                                         /*!< TIMER3 IR: MR1INT Position          */
+#define TIMER3_IR_MR1INT_Msk                                  (0x01UL << TIMER3_IR_MR1INT_Pos)                          /*!< TIMER3 IR: MR1INT Mask              */
+#define TIMER3_IR_MR2INT_Pos                                  2                                                         /*!< TIMER3 IR: MR2INT Position          */
+#define TIMER3_IR_MR2INT_Msk                                  (0x01UL << TIMER3_IR_MR2INT_Pos)                          /*!< TIMER3 IR: MR2INT Mask              */
+#define TIMER3_IR_MR3INT_Pos                                  3                                                         /*!< TIMER3 IR: MR3INT Position          */
+#define TIMER3_IR_MR3INT_Msk                                  (0x01UL << TIMER3_IR_MR3INT_Pos)                          /*!< TIMER3 IR: MR3INT Mask              */
+#define TIMER3_IR_CR0INT_Pos                                  4                                                         /*!< TIMER3 IR: CR0INT Position          */
+#define TIMER3_IR_CR0INT_Msk                                  (0x01UL << TIMER3_IR_CR0INT_Pos)                          /*!< TIMER3 IR: CR0INT Mask              */
+#define TIMER3_IR_CR1INT_Pos                                  5                                                         /*!< TIMER3 IR: CR1INT Position          */
+#define TIMER3_IR_CR1INT_Msk                                  (0x01UL << TIMER3_IR_CR1INT_Pos)                          /*!< TIMER3 IR: CR1INT Mask              */
+#define TIMER3_IR_CR2INT_Pos                                  6                                                         /*!< TIMER3 IR: CR2INT Position          */
+#define TIMER3_IR_CR2INT_Msk                                  (0x01UL << TIMER3_IR_CR2INT_Pos)                          /*!< TIMER3 IR: CR2INT Mask              */
+#define TIMER3_IR_CR3INT_Pos                                  7                                                         /*!< TIMER3 IR: CR3INT Position          */
+#define TIMER3_IR_CR3INT_Msk                                  (0x01UL << TIMER3_IR_CR3INT_Pos)                          /*!< TIMER3 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER3_TCR  -------------------------------------------
+#define TIMER3_TCR_CEN_Pos                                    0                                                         /*!< TIMER3 TCR: CEN Position            */
+#define TIMER3_TCR_CEN_Msk                                    (0x01UL << TIMER3_TCR_CEN_Pos)                            /*!< TIMER3 TCR: CEN Mask                */
+#define TIMER3_TCR_CRST_Pos                                   1                                                         /*!< TIMER3 TCR: CRST Position           */
+#define TIMER3_TCR_CRST_Msk                                   (0x01UL << TIMER3_TCR_CRST_Pos)                           /*!< TIMER3 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER3_TC  -------------------------------------------
+#define TIMER3_TC_TC_Pos                                      0                                                         /*!< TIMER3 TC: TC Position              */
+#define TIMER3_TC_TC_Msk                                      (0xffffffffUL << TIMER3_TC_TC_Pos)                        /*!< TIMER3 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER3_PR  -------------------------------------------
+#define TIMER3_PR_PM_Pos                                      0                                                         /*!< TIMER3 PR: PM Position              */
+#define TIMER3_PR_PM_Msk                                      (0xffffffffUL << TIMER3_PR_PM_Pos)                        /*!< TIMER3 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER3_PC  -------------------------------------------
+#define TIMER3_PC_PC_Pos                                      0                                                         /*!< TIMER3 PC: PC Position              */
+#define TIMER3_PC_PC_Msk                                      (0xffffffffUL << TIMER3_PC_PC_Pos)                        /*!< TIMER3 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER3_MCR  -------------------------------------------
+#define TIMER3_MCR_MR0I_Pos                                   0                                                         /*!< TIMER3 MCR: MR0I Position           */
+#define TIMER3_MCR_MR0I_Msk                                   (0x01UL << TIMER3_MCR_MR0I_Pos)                           /*!< TIMER3 MCR: MR0I Mask               */
+#define TIMER3_MCR_MR0R_Pos                                   1                                                         /*!< TIMER3 MCR: MR0R Position           */
+#define TIMER3_MCR_MR0R_Msk                                   (0x01UL << TIMER3_MCR_MR0R_Pos)                           /*!< TIMER3 MCR: MR0R Mask               */
+#define TIMER3_MCR_MR0S_Pos                                   2                                                         /*!< TIMER3 MCR: MR0S Position           */
+#define TIMER3_MCR_MR0S_Msk                                   (0x01UL << TIMER3_MCR_MR0S_Pos)                           /*!< TIMER3 MCR: MR0S Mask               */
+#define TIMER3_MCR_MR1I_Pos                                   3                                                         /*!< TIMER3 MCR: MR1I Position           */
+#define TIMER3_MCR_MR1I_Msk                                   (0x01UL << TIMER3_MCR_MR1I_Pos)                           /*!< TIMER3 MCR: MR1I Mask               */
+#define TIMER3_MCR_MR1R_Pos                                   4                                                         /*!< TIMER3 MCR: MR1R Position           */
+#define TIMER3_MCR_MR1R_Msk                                   (0x01UL << TIMER3_MCR_MR1R_Pos)                           /*!< TIMER3 MCR: MR1R Mask               */
+#define TIMER3_MCR_MR1S_Pos                                   5                                                         /*!< TIMER3 MCR: MR1S Position           */
+#define TIMER3_MCR_MR1S_Msk                                   (0x01UL << TIMER3_MCR_MR1S_Pos)                           /*!< TIMER3 MCR: MR1S Mask               */
+#define TIMER3_MCR_MR2I_Pos                                   6                                                         /*!< TIMER3 MCR: MR2I Position           */
+#define TIMER3_MCR_MR2I_Msk                                   (0x01UL << TIMER3_MCR_MR2I_Pos)                           /*!< TIMER3 MCR: MR2I Mask               */
+#define TIMER3_MCR_MR2R_Pos                                   7                                                         /*!< TIMER3 MCR: MR2R Position           */
+#define TIMER3_MCR_MR2R_Msk                                   (0x01UL << TIMER3_MCR_MR2R_Pos)                           /*!< TIMER3 MCR: MR2R Mask               */
+#define TIMER3_MCR_MR2S_Pos                                   8                                                         /*!< TIMER3 MCR: MR2S Position           */
+#define TIMER3_MCR_MR2S_Msk                                   (0x01UL << TIMER3_MCR_MR2S_Pos)                           /*!< TIMER3 MCR: MR2S Mask               */
+#define TIMER3_MCR_MR3I_Pos                                   9                                                         /*!< TIMER3 MCR: MR3I Position           */
+#define TIMER3_MCR_MR3I_Msk                                   (0x01UL << TIMER3_MCR_MR3I_Pos)                           /*!< TIMER3 MCR: MR3I Mask               */
+#define TIMER3_MCR_MR3R_Pos                                   10                                                        /*!< TIMER3 MCR: MR3R Position           */
+#define TIMER3_MCR_MR3R_Msk                                   (0x01UL << TIMER3_MCR_MR3R_Pos)                           /*!< TIMER3 MCR: MR3R Mask               */
+#define TIMER3_MCR_MR3S_Pos                                   11                                                        /*!< TIMER3 MCR: MR3S Position           */
+#define TIMER3_MCR_MR3S_Msk                                   (0x01UL << TIMER3_MCR_MR3S_Pos)                           /*!< TIMER3 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER3_MR0  -------------------------------------------
+#define TIMER3_MR0_MATCH_Pos                                  0                                                         /*!< TIMER3 MR0: MATCH Position          */
+#define TIMER3_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR0_MATCH_Pos)                    /*!< TIMER3 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_MR1  -------------------------------------------
+#define TIMER3_MR1_MATCH_Pos                                  0                                                         /*!< TIMER3 MR1: MATCH Position          */
+#define TIMER3_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR1_MATCH_Pos)                    /*!< TIMER3 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_MR2  -------------------------------------------
+#define TIMER3_MR2_MATCH_Pos                                  0                                                         /*!< TIMER3 MR2: MATCH Position          */
+#define TIMER3_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR2_MATCH_Pos)                    /*!< TIMER3 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_MR3  -------------------------------------------
+#define TIMER3_MR3_MATCH_Pos                                  0                                                         /*!< TIMER3 MR3: MATCH Position          */
+#define TIMER3_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR3_MATCH_Pos)                    /*!< TIMER3 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_CCR  -------------------------------------------
+#define TIMER3_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER3 CCR: CAP0RE Position         */
+#define TIMER3_CCR_CAP0RE_Msk                                 (0x01UL << TIMER3_CCR_CAP0RE_Pos)                         /*!< TIMER3 CCR: CAP0RE Mask             */
+#define TIMER3_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER3 CCR: CAP0FE Position         */
+#define TIMER3_CCR_CAP0FE_Msk                                 (0x01UL << TIMER3_CCR_CAP0FE_Pos)                         /*!< TIMER3 CCR: CAP0FE Mask             */
+#define TIMER3_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER3 CCR: CAP0I Position          */
+#define TIMER3_CCR_CAP0I_Msk                                  (0x01UL << TIMER3_CCR_CAP0I_Pos)                          /*!< TIMER3 CCR: CAP0I Mask              */
+#define TIMER3_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER3 CCR: CAP1RE Position         */
+#define TIMER3_CCR_CAP1RE_Msk                                 (0x01UL << TIMER3_CCR_CAP1RE_Pos)                         /*!< TIMER3 CCR: CAP1RE Mask             */
+#define TIMER3_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER3 CCR: CAP1FE Position         */
+#define TIMER3_CCR_CAP1FE_Msk                                 (0x01UL << TIMER3_CCR_CAP1FE_Pos)                         /*!< TIMER3 CCR: CAP1FE Mask             */
+#define TIMER3_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER3 CCR: CAP1I Position          */
+#define TIMER3_CCR_CAP1I_Msk                                  (0x01UL << TIMER3_CCR_CAP1I_Pos)                          /*!< TIMER3 CCR: CAP1I Mask              */
+#define TIMER3_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER3 CCR: CAP2RE Position         */
+#define TIMER3_CCR_CAP2RE_Msk                                 (0x01UL << TIMER3_CCR_CAP2RE_Pos)                         /*!< TIMER3 CCR: CAP2RE Mask             */
+#define TIMER3_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER3 CCR: CAP2FE Position         */
+#define TIMER3_CCR_CAP2FE_Msk                                 (0x01UL << TIMER3_CCR_CAP2FE_Pos)                         /*!< TIMER3 CCR: CAP2FE Mask             */
+#define TIMER3_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER3 CCR: CAP2I Position          */
+#define TIMER3_CCR_CAP2I_Msk                                  (0x01UL << TIMER3_CCR_CAP2I_Pos)                          /*!< TIMER3 CCR: CAP2I Mask              */
+#define TIMER3_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER3 CCR: CAP3RE Position         */
+#define TIMER3_CCR_CAP3RE_Msk                                 (0x01UL << TIMER3_CCR_CAP3RE_Pos)                         /*!< TIMER3 CCR: CAP3RE Mask             */
+#define TIMER3_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER3 CCR: CAP3FE Position         */
+#define TIMER3_CCR_CAP3FE_Msk                                 (0x01UL << TIMER3_CCR_CAP3FE_Pos)                         /*!< TIMER3 CCR: CAP3FE Mask             */
+#define TIMER3_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER3 CCR: CAP3I Position          */
+#define TIMER3_CCR_CAP3I_Msk                                  (0x01UL << TIMER3_CCR_CAP3I_Pos)                          /*!< TIMER3 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER3_CR0  -------------------------------------------
+#define TIMER3_CR0_CAP_Pos                                    0                                                         /*!< TIMER3 CR0: CAP Position            */
+#define TIMER3_CR0_CAP_Msk                                    (0xffffffffUL << TIMER3_CR0_CAP_Pos)                      /*!< TIMER3 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER3_CR1  -------------------------------------------
+#define TIMER3_CR1_CAP_Pos                                    0                                                         /*!< TIMER3 CR1: CAP Position            */
+#define TIMER3_CR1_CAP_Msk                                    (0xffffffffUL << TIMER3_CR1_CAP_Pos)                      /*!< TIMER3 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER3_CR2  -------------------------------------------
+#define TIMER3_CR2_CAP_Pos                                    0                                                         /*!< TIMER3 CR2: CAP Position            */
+#define TIMER3_CR2_CAP_Msk                                    (0xffffffffUL << TIMER3_CR2_CAP_Pos)                      /*!< TIMER3 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER3_CR3  -------------------------------------------
+#define TIMER3_CR3_CAP_Pos                                    0                                                         /*!< TIMER3 CR3: CAP Position            */
+#define TIMER3_CR3_CAP_Msk                                    (0xffffffffUL << TIMER3_CR3_CAP_Pos)                      /*!< TIMER3 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER3_EMR  -------------------------------------------
+#define TIMER3_EMR_EM0_Pos                                    0                                                         /*!< TIMER3 EMR: EM0 Position            */
+#define TIMER3_EMR_EM0_Msk                                    (0x01UL << TIMER3_EMR_EM0_Pos)                            /*!< TIMER3 EMR: EM0 Mask                */
+#define TIMER3_EMR_EM1_Pos                                    1                                                         /*!< TIMER3 EMR: EM1 Position            */
+#define TIMER3_EMR_EM1_Msk                                    (0x01UL << TIMER3_EMR_EM1_Pos)                            /*!< TIMER3 EMR: EM1 Mask                */
+#define TIMER3_EMR_EM2_Pos                                    2                                                         /*!< TIMER3 EMR: EM2 Position            */
+#define TIMER3_EMR_EM2_Msk                                    (0x01UL << TIMER3_EMR_EM2_Pos)                            /*!< TIMER3 EMR: EM2 Mask                */
+#define TIMER3_EMR_EM3_Pos                                    3                                                         /*!< TIMER3 EMR: EM3 Position            */
+#define TIMER3_EMR_EM3_Msk                                    (0x01UL << TIMER3_EMR_EM3_Pos)                            /*!< TIMER3 EMR: EM3 Mask                */
+#define TIMER3_EMR_EMC0_Pos                                   4                                                         /*!< TIMER3 EMR: EMC0 Position           */
+#define TIMER3_EMR_EMC0_Msk                                   (0x03UL << TIMER3_EMR_EMC0_Pos)                           /*!< TIMER3 EMR: EMC0 Mask               */
+#define TIMER3_EMR_EMC1_Pos                                   6                                                         /*!< TIMER3 EMR: EMC1 Position           */
+#define TIMER3_EMR_EMC1_Msk                                   (0x03UL << TIMER3_EMR_EMC1_Pos)                           /*!< TIMER3 EMR: EMC1 Mask               */
+#define TIMER3_EMR_EMC2_Pos                                   8                                                         /*!< TIMER3 EMR: EMC2 Position           */
+#define TIMER3_EMR_EMC2_Msk                                   (0x03UL << TIMER3_EMR_EMC2_Pos)                           /*!< TIMER3 EMR: EMC2 Mask               */
+#define TIMER3_EMR_EMC3_Pos                                   10                                                        /*!< TIMER3 EMR: EMC3 Position           */
+#define TIMER3_EMR_EMC3_Msk                                   (0x03UL << TIMER3_EMR_EMC3_Pos)                           /*!< TIMER3 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER3_CTCR  ------------------------------------------
+#define TIMER3_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER3 CTCR: CTMODE Position        */
+#define TIMER3_CTCR_CTMODE_Msk                                (0x03UL << TIMER3_CTCR_CTMODE_Pos)                        /*!< TIMER3 CTCR: CTMODE Mask            */
+#define TIMER3_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER3 CTCR: CINSEL Position        */
+#define TIMER3_CTCR_CINSEL_Msk                                (0x03UL << TIMER3_CTCR_CINSEL_Pos)                        /*!< TIMER3 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  SCU Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  SCU_SFSP0_0  ------------------------------------------
+#define SCU_SFSP0_0_MODE_Pos                                  0                                                         /*!< SCU SFSP0_0: MODE Position          */
+#define SCU_SFSP0_0_MODE_Msk                                  (0x07UL << SCU_SFSP0_0_MODE_Pos)                          /*!< SCU SFSP0_0: MODE Mask              */
+#define SCU_SFSP0_0_EPD_Pos                                   3                                                         /*!< SCU SFSP0_0: EPD Position           */
+#define SCU_SFSP0_0_EPD_Msk                                   (0x01UL << SCU_SFSP0_0_EPD_Pos)                           /*!< SCU SFSP0_0: EPD Mask               */
+#define SCU_SFSP0_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_0: EPUN Position          */
+#define SCU_SFSP0_0_EPUN_Msk                                  (0x01UL << SCU_SFSP0_0_EPUN_Pos)                          /*!< SCU SFSP0_0: EPUN Mask              */
+#define SCU_SFSP0_0_EHS_Pos                                   5                                                         /*!< SCU SFSP0_0: EHS Position           */
+#define SCU_SFSP0_0_EHS_Msk                                   (0x01UL << SCU_SFSP0_0_EHS_Pos)                           /*!< SCU SFSP0_0: EHS Mask               */
+#define SCU_SFSP0_0_EZI_Pos                                   6                                                         /*!< SCU SFSP0_0: EZI Position           */
+#define SCU_SFSP0_0_EZI_Msk                                   (0x01UL << SCU_SFSP0_0_EZI_Pos)                           /*!< SCU SFSP0_0: EZI Mask               */
+
+// ---------------------------------------  SCU_SFSP0_1  ------------------------------------------
+#define SCU_SFSP0_1_MODE_Pos                                  0                                                         /*!< SCU SFSP0_1: MODE Position          */
+#define SCU_SFSP0_1_MODE_Msk                                  (0x07UL << SCU_SFSP0_1_MODE_Pos)                          /*!< SCU SFSP0_1: MODE Mask              */
+#define SCU_SFSP0_1_EPD_Pos                                   3                                                         /*!< SCU SFSP0_1: EPD Position           */
+#define SCU_SFSP0_1_EPD_Msk                                   (0x01UL << SCU_SFSP0_1_EPD_Pos)                           /*!< SCU SFSP0_1: EPD Mask               */
+#define SCU_SFSP0_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_1: EPUN Position          */
+#define SCU_SFSP0_1_EPUN_Msk                                  (0x01UL << SCU_SFSP0_1_EPUN_Pos)                          /*!< SCU SFSP0_1: EPUN Mask              */
+#define SCU_SFSP0_1_EHS_Pos                                   5                                                         /*!< SCU SFSP0_1: EHS Position           */
+#define SCU_SFSP0_1_EHS_Msk                                   (0x01UL << SCU_SFSP0_1_EHS_Pos)                           /*!< SCU SFSP0_1: EHS Mask               */
+#define SCU_SFSP0_1_EZI_Pos                                   6                                                         /*!< SCU SFSP0_1: EZI Position           */
+#define SCU_SFSP0_1_EZI_Msk                                   (0x01UL << SCU_SFSP0_1_EZI_Pos)                           /*!< SCU SFSP0_1: EZI Mask               */
+
+// ---------------------------------------  SCU_SFSP1_0  ------------------------------------------
+#define SCU_SFSP1_0_MODE_Pos                                  0                                                         /*!< SCU SFSP1_0: MODE Position          */
+#define SCU_SFSP1_0_MODE_Msk                                  (0x07UL << SCU_SFSP1_0_MODE_Pos)                          /*!< SCU SFSP1_0: MODE Mask              */
+#define SCU_SFSP1_0_EPD_Pos                                   3                                                         /*!< SCU SFSP1_0: EPD Position           */
+#define SCU_SFSP1_0_EPD_Msk                                   (0x01UL << SCU_SFSP1_0_EPD_Pos)                           /*!< SCU SFSP1_0: EPD Mask               */
+#define SCU_SFSP1_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_0: EPUN Position          */
+#define SCU_SFSP1_0_EPUN_Msk                                  (0x01UL << SCU_SFSP1_0_EPUN_Pos)                          /*!< SCU SFSP1_0: EPUN Mask              */
+#define SCU_SFSP1_0_EHS_Pos                                   5                                                         /*!< SCU SFSP1_0: EHS Position           */
+#define SCU_SFSP1_0_EHS_Msk                                   (0x01UL << SCU_SFSP1_0_EHS_Pos)                           /*!< SCU SFSP1_0: EHS Mask               */
+#define SCU_SFSP1_0_EZI_Pos                                   6                                                         /*!< SCU SFSP1_0: EZI Position           */
+#define SCU_SFSP1_0_EZI_Msk                                   (0x01UL << SCU_SFSP1_0_EZI_Pos)                           /*!< SCU SFSP1_0: EZI Mask               */
+#define SCU_SFSP1_0_EHD_Pos                                   8                                                         /*!< SCU SFSP1_0: EHD Position           */
+#define SCU_SFSP1_0_EHD_Msk                                   (0x03UL << SCU_SFSP1_0_EHD_Pos)                           /*!< SCU SFSP1_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_1  ------------------------------------------
+#define SCU_SFSP1_1_MODE_Pos                                  0                                                         /*!< SCU SFSP1_1: MODE Position          */
+#define SCU_SFSP1_1_MODE_Msk                                  (0x07UL << SCU_SFSP1_1_MODE_Pos)                          /*!< SCU SFSP1_1: MODE Mask              */
+#define SCU_SFSP1_1_EPD_Pos                                   3                                                         /*!< SCU SFSP1_1: EPD Position           */
+#define SCU_SFSP1_1_EPD_Msk                                   (0x01UL << SCU_SFSP1_1_EPD_Pos)                           /*!< SCU SFSP1_1: EPD Mask               */
+#define SCU_SFSP1_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_1: EPUN Position          */
+#define SCU_SFSP1_1_EPUN_Msk                                  (0x01UL << SCU_SFSP1_1_EPUN_Pos)                          /*!< SCU SFSP1_1: EPUN Mask              */
+#define SCU_SFSP1_1_EHS_Pos                                   5                                                         /*!< SCU SFSP1_1: EHS Position           */
+#define SCU_SFSP1_1_EHS_Msk                                   (0x01UL << SCU_SFSP1_1_EHS_Pos)                           /*!< SCU SFSP1_1: EHS Mask               */
+#define SCU_SFSP1_1_EZI_Pos                                   6                                                         /*!< SCU SFSP1_1: EZI Position           */
+#define SCU_SFSP1_1_EZI_Msk                                   (0x01UL << SCU_SFSP1_1_EZI_Pos)                           /*!< SCU SFSP1_1: EZI Mask               */
+#define SCU_SFSP1_1_EHD_Pos                                   8                                                         /*!< SCU SFSP1_1: EHD Position           */
+#define SCU_SFSP1_1_EHD_Msk                                   (0x03UL << SCU_SFSP1_1_EHD_Pos)                           /*!< SCU SFSP1_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_2  ------------------------------------------
+#define SCU_SFSP1_2_MODE_Pos                                  0                                                         /*!< SCU SFSP1_2: MODE Position          */
+#define SCU_SFSP1_2_MODE_Msk                                  (0x07UL << SCU_SFSP1_2_MODE_Pos)                          /*!< SCU SFSP1_2: MODE Mask              */
+#define SCU_SFSP1_2_EPD_Pos                                   3                                                         /*!< SCU SFSP1_2: EPD Position           */
+#define SCU_SFSP1_2_EPD_Msk                                   (0x01UL << SCU_SFSP1_2_EPD_Pos)                           /*!< SCU SFSP1_2: EPD Mask               */
+#define SCU_SFSP1_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_2: EPUN Position          */
+#define SCU_SFSP1_2_EPUN_Msk                                  (0x01UL << SCU_SFSP1_2_EPUN_Pos)                          /*!< SCU SFSP1_2: EPUN Mask              */
+#define SCU_SFSP1_2_EHS_Pos                                   5                                                         /*!< SCU SFSP1_2: EHS Position           */
+#define SCU_SFSP1_2_EHS_Msk                                   (0x01UL << SCU_SFSP1_2_EHS_Pos)                           /*!< SCU SFSP1_2: EHS Mask               */
+#define SCU_SFSP1_2_EZI_Pos                                   6                                                         /*!< SCU SFSP1_2: EZI Position           */
+#define SCU_SFSP1_2_EZI_Msk                                   (0x01UL << SCU_SFSP1_2_EZI_Pos)                           /*!< SCU SFSP1_2: EZI Mask               */
+#define SCU_SFSP1_2_EHD_Pos                                   8                                                         /*!< SCU SFSP1_2: EHD Position           */
+#define SCU_SFSP1_2_EHD_Msk                                   (0x03UL << SCU_SFSP1_2_EHD_Pos)                           /*!< SCU SFSP1_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_3  ------------------------------------------
+#define SCU_SFSP1_3_MODE_Pos                                  0                                                         /*!< SCU SFSP1_3: MODE Position          */
+#define SCU_SFSP1_3_MODE_Msk                                  (0x07UL << SCU_SFSP1_3_MODE_Pos)                          /*!< SCU SFSP1_3: MODE Mask              */
+#define SCU_SFSP1_3_EPD_Pos                                   3                                                         /*!< SCU SFSP1_3: EPD Position           */
+#define SCU_SFSP1_3_EPD_Msk                                   (0x01UL << SCU_SFSP1_3_EPD_Pos)                           /*!< SCU SFSP1_3: EPD Mask               */
+#define SCU_SFSP1_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_3: EPUN Position          */
+#define SCU_SFSP1_3_EPUN_Msk                                  (0x01UL << SCU_SFSP1_3_EPUN_Pos)                          /*!< SCU SFSP1_3: EPUN Mask              */
+#define SCU_SFSP1_3_EHS_Pos                                   5                                                         /*!< SCU SFSP1_3: EHS Position           */
+#define SCU_SFSP1_3_EHS_Msk                                   (0x01UL << SCU_SFSP1_3_EHS_Pos)                           /*!< SCU SFSP1_3: EHS Mask               */
+#define SCU_SFSP1_3_EZI_Pos                                   6                                                         /*!< SCU SFSP1_3: EZI Position           */
+#define SCU_SFSP1_3_EZI_Msk                                   (0x01UL << SCU_SFSP1_3_EZI_Pos)                           /*!< SCU SFSP1_3: EZI Mask               */
+#define SCU_SFSP1_3_EHD_Pos                                   8                                                         /*!< SCU SFSP1_3: EHD Position           */
+#define SCU_SFSP1_3_EHD_Msk                                   (0x03UL << SCU_SFSP1_3_EHD_Pos)                           /*!< SCU SFSP1_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_4  ------------------------------------------
+#define SCU_SFSP1_4_MODE_Pos                                  0                                                         /*!< SCU SFSP1_4: MODE Position          */
+#define SCU_SFSP1_4_MODE_Msk                                  (0x07UL << SCU_SFSP1_4_MODE_Pos)                          /*!< SCU SFSP1_4: MODE Mask              */
+#define SCU_SFSP1_4_EPD_Pos                                   3                                                         /*!< SCU SFSP1_4: EPD Position           */
+#define SCU_SFSP1_4_EPD_Msk                                   (0x01UL << SCU_SFSP1_4_EPD_Pos)                           /*!< SCU SFSP1_4: EPD Mask               */
+#define SCU_SFSP1_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_4: EPUN Position          */
+#define SCU_SFSP1_4_EPUN_Msk                                  (0x01UL << SCU_SFSP1_4_EPUN_Pos)                          /*!< SCU SFSP1_4: EPUN Mask              */
+#define SCU_SFSP1_4_EHS_Pos                                   5                                                         /*!< SCU SFSP1_4: EHS Position           */
+#define SCU_SFSP1_4_EHS_Msk                                   (0x01UL << SCU_SFSP1_4_EHS_Pos)                           /*!< SCU SFSP1_4: EHS Mask               */
+#define SCU_SFSP1_4_EZI_Pos                                   6                                                         /*!< SCU SFSP1_4: EZI Position           */
+#define SCU_SFSP1_4_EZI_Msk                                   (0x01UL << SCU_SFSP1_4_EZI_Pos)                           /*!< SCU SFSP1_4: EZI Mask               */
+#define SCU_SFSP1_4_EHD_Pos                                   8                                                         /*!< SCU SFSP1_4: EHD Position           */
+#define SCU_SFSP1_4_EHD_Msk                                   (0x03UL << SCU_SFSP1_4_EHD_Pos)                           /*!< SCU SFSP1_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_5  ------------------------------------------
+#define SCU_SFSP1_5_MODE_Pos                                  0                                                         /*!< SCU SFSP1_5: MODE Position          */
+#define SCU_SFSP1_5_MODE_Msk                                  (0x07UL << SCU_SFSP1_5_MODE_Pos)                          /*!< SCU SFSP1_5: MODE Mask              */
+#define SCU_SFSP1_5_EPD_Pos                                   3                                                         /*!< SCU SFSP1_5: EPD Position           */
+#define SCU_SFSP1_5_EPD_Msk                                   (0x01UL << SCU_SFSP1_5_EPD_Pos)                           /*!< SCU SFSP1_5: EPD Mask               */
+#define SCU_SFSP1_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_5: EPUN Position          */
+#define SCU_SFSP1_5_EPUN_Msk                                  (0x01UL << SCU_SFSP1_5_EPUN_Pos)                          /*!< SCU SFSP1_5: EPUN Mask              */
+#define SCU_SFSP1_5_EHS_Pos                                   5                                                         /*!< SCU SFSP1_5: EHS Position           */
+#define SCU_SFSP1_5_EHS_Msk                                   (0x01UL << SCU_SFSP1_5_EHS_Pos)                           /*!< SCU SFSP1_5: EHS Mask               */
+#define SCU_SFSP1_5_EZI_Pos                                   6                                                         /*!< SCU SFSP1_5: EZI Position           */
+#define SCU_SFSP1_5_EZI_Msk                                   (0x01UL << SCU_SFSP1_5_EZI_Pos)                           /*!< SCU SFSP1_5: EZI Mask               */
+#define SCU_SFSP1_5_EHD_Pos                                   8                                                         /*!< SCU SFSP1_5: EHD Position           */
+#define SCU_SFSP1_5_EHD_Msk                                   (0x03UL << SCU_SFSP1_5_EHD_Pos)                           /*!< SCU SFSP1_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_6  ------------------------------------------
+#define SCU_SFSP1_6_MODE_Pos                                  0                                                         /*!< SCU SFSP1_6: MODE Position          */
+#define SCU_SFSP1_6_MODE_Msk                                  (0x07UL << SCU_SFSP1_6_MODE_Pos)                          /*!< SCU SFSP1_6: MODE Mask              */
+#define SCU_SFSP1_6_EPD_Pos                                   3                                                         /*!< SCU SFSP1_6: EPD Position           */
+#define SCU_SFSP1_6_EPD_Msk                                   (0x01UL << SCU_SFSP1_6_EPD_Pos)                           /*!< SCU SFSP1_6: EPD Mask               */
+#define SCU_SFSP1_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_6: EPUN Position          */
+#define SCU_SFSP1_6_EPUN_Msk                                  (0x01UL << SCU_SFSP1_6_EPUN_Pos)                          /*!< SCU SFSP1_6: EPUN Mask              */
+#define SCU_SFSP1_6_EHS_Pos                                   5                                                         /*!< SCU SFSP1_6: EHS Position           */
+#define SCU_SFSP1_6_EHS_Msk                                   (0x01UL << SCU_SFSP1_6_EHS_Pos)                           /*!< SCU SFSP1_6: EHS Mask               */
+#define SCU_SFSP1_6_EZI_Pos                                   6                                                         /*!< SCU SFSP1_6: EZI Position           */
+#define SCU_SFSP1_6_EZI_Msk                                   (0x01UL << SCU_SFSP1_6_EZI_Pos)                           /*!< SCU SFSP1_6: EZI Mask               */
+#define SCU_SFSP1_6_EHD_Pos                                   8                                                         /*!< SCU SFSP1_6: EHD Position           */
+#define SCU_SFSP1_6_EHD_Msk                                   (0x03UL << SCU_SFSP1_6_EHD_Pos)                           /*!< SCU SFSP1_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_7  ------------------------------------------
+#define SCU_SFSP1_7_MODE_Pos                                  0                                                         /*!< SCU SFSP1_7: MODE Position          */
+#define SCU_SFSP1_7_MODE_Msk                                  (0x07UL << SCU_SFSP1_7_MODE_Pos)                          /*!< SCU SFSP1_7: MODE Mask              */
+#define SCU_SFSP1_7_EPD_Pos                                   3                                                         /*!< SCU SFSP1_7: EPD Position           */
+#define SCU_SFSP1_7_EPD_Msk                                   (0x01UL << SCU_SFSP1_7_EPD_Pos)                           /*!< SCU SFSP1_7: EPD Mask               */
+#define SCU_SFSP1_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_7: EPUN Position          */
+#define SCU_SFSP1_7_EPUN_Msk                                  (0x01UL << SCU_SFSP1_7_EPUN_Pos)                          /*!< SCU SFSP1_7: EPUN Mask              */
+#define SCU_SFSP1_7_EHS_Pos                                   5                                                         /*!< SCU SFSP1_7: EHS Position           */
+#define SCU_SFSP1_7_EHS_Msk                                   (0x01UL << SCU_SFSP1_7_EHS_Pos)                           /*!< SCU SFSP1_7: EHS Mask               */
+#define SCU_SFSP1_7_EZI_Pos                                   6                                                         /*!< SCU SFSP1_7: EZI Position           */
+#define SCU_SFSP1_7_EZI_Msk                                   (0x01UL << SCU_SFSP1_7_EZI_Pos)                           /*!< SCU SFSP1_7: EZI Mask               */
+#define SCU_SFSP1_7_EHD_Pos                                   8                                                         /*!< SCU SFSP1_7: EHD Position           */
+#define SCU_SFSP1_7_EHD_Msk                                   (0x03UL << SCU_SFSP1_7_EHD_Pos)                           /*!< SCU SFSP1_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_8  ------------------------------------------
+#define SCU_SFSP1_8_MODE_Pos                                  0                                                         /*!< SCU SFSP1_8: MODE Position          */
+#define SCU_SFSP1_8_MODE_Msk                                  (0x07UL << SCU_SFSP1_8_MODE_Pos)                          /*!< SCU SFSP1_8: MODE Mask              */
+#define SCU_SFSP1_8_EPD_Pos                                   3                                                         /*!< SCU SFSP1_8: EPD Position           */
+#define SCU_SFSP1_8_EPD_Msk                                   (0x01UL << SCU_SFSP1_8_EPD_Pos)                           /*!< SCU SFSP1_8: EPD Mask               */
+#define SCU_SFSP1_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_8: EPUN Position          */
+#define SCU_SFSP1_8_EPUN_Msk                                  (0x01UL << SCU_SFSP1_8_EPUN_Pos)                          /*!< SCU SFSP1_8: EPUN Mask              */
+#define SCU_SFSP1_8_EHS_Pos                                   5                                                         /*!< SCU SFSP1_8: EHS Position           */
+#define SCU_SFSP1_8_EHS_Msk                                   (0x01UL << SCU_SFSP1_8_EHS_Pos)                           /*!< SCU SFSP1_8: EHS Mask               */
+#define SCU_SFSP1_8_EZI_Pos                                   6                                                         /*!< SCU SFSP1_8: EZI Position           */
+#define SCU_SFSP1_8_EZI_Msk                                   (0x01UL << SCU_SFSP1_8_EZI_Pos)                           /*!< SCU SFSP1_8: EZI Mask               */
+#define SCU_SFSP1_8_EHD_Pos                                   8                                                         /*!< SCU SFSP1_8: EHD Position           */
+#define SCU_SFSP1_8_EHD_Msk                                   (0x03UL << SCU_SFSP1_8_EHD_Pos)                           /*!< SCU SFSP1_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_9  ------------------------------------------
+#define SCU_SFSP1_9_MODE_Pos                                  0                                                         /*!< SCU SFSP1_9: MODE Position          */
+#define SCU_SFSP1_9_MODE_Msk                                  (0x07UL << SCU_SFSP1_9_MODE_Pos)                          /*!< SCU SFSP1_9: MODE Mask              */
+#define SCU_SFSP1_9_EPD_Pos                                   3                                                         /*!< SCU SFSP1_9: EPD Position           */
+#define SCU_SFSP1_9_EPD_Msk                                   (0x01UL << SCU_SFSP1_9_EPD_Pos)                           /*!< SCU SFSP1_9: EPD Mask               */
+#define SCU_SFSP1_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_9: EPUN Position          */
+#define SCU_SFSP1_9_EPUN_Msk                                  (0x01UL << SCU_SFSP1_9_EPUN_Pos)                          /*!< SCU SFSP1_9: EPUN Mask              */
+#define SCU_SFSP1_9_EHS_Pos                                   5                                                         /*!< SCU SFSP1_9: EHS Position           */
+#define SCU_SFSP1_9_EHS_Msk                                   (0x01UL << SCU_SFSP1_9_EHS_Pos)                           /*!< SCU SFSP1_9: EHS Mask               */
+#define SCU_SFSP1_9_EZI_Pos                                   6                                                         /*!< SCU SFSP1_9: EZI Position           */
+#define SCU_SFSP1_9_EZI_Msk                                   (0x01UL << SCU_SFSP1_9_EZI_Pos)                           /*!< SCU SFSP1_9: EZI Mask               */
+#define SCU_SFSP1_9_EHD_Pos                                   8                                                         /*!< SCU SFSP1_9: EHD Position           */
+#define SCU_SFSP1_9_EHD_Msk                                   (0x03UL << SCU_SFSP1_9_EHD_Pos)                           /*!< SCU SFSP1_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP1_10  ------------------------------------------
+#define SCU_SFSP1_10_MODE_Pos                                 0                                                         /*!< SCU SFSP1_10: MODE Position         */
+#define SCU_SFSP1_10_MODE_Msk                                 (0x07UL << SCU_SFSP1_10_MODE_Pos)                         /*!< SCU SFSP1_10: MODE Mask             */
+#define SCU_SFSP1_10_EPD_Pos                                  3                                                         /*!< SCU SFSP1_10: EPD Position          */
+#define SCU_SFSP1_10_EPD_Msk                                  (0x01UL << SCU_SFSP1_10_EPD_Pos)                          /*!< SCU SFSP1_10: EPD Mask              */
+#define SCU_SFSP1_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_10: EPUN Position         */
+#define SCU_SFSP1_10_EPUN_Msk                                 (0x01UL << SCU_SFSP1_10_EPUN_Pos)                         /*!< SCU SFSP1_10: EPUN Mask             */
+#define SCU_SFSP1_10_EHS_Pos                                  5                                                         /*!< SCU SFSP1_10: EHS Position          */
+#define SCU_SFSP1_10_EHS_Msk                                  (0x01UL << SCU_SFSP1_10_EHS_Pos)                          /*!< SCU SFSP1_10: EHS Mask              */
+#define SCU_SFSP1_10_EZI_Pos                                  6                                                         /*!< SCU SFSP1_10: EZI Position          */
+#define SCU_SFSP1_10_EZI_Msk                                  (0x01UL << SCU_SFSP1_10_EZI_Pos)                          /*!< SCU SFSP1_10: EZI Mask              */
+#define SCU_SFSP1_10_EHD_Pos                                  8                                                         /*!< SCU SFSP1_10: EHD Position          */
+#define SCU_SFSP1_10_EHD_Msk                                  (0x03UL << SCU_SFSP1_10_EHD_Pos)                          /*!< SCU SFSP1_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_11  ------------------------------------------
+#define SCU_SFSP1_11_MODE_Pos                                 0                                                         /*!< SCU SFSP1_11: MODE Position         */
+#define SCU_SFSP1_11_MODE_Msk                                 (0x07UL << SCU_SFSP1_11_MODE_Pos)                         /*!< SCU SFSP1_11: MODE Mask             */
+#define SCU_SFSP1_11_EPD_Pos                                  3                                                         /*!< SCU SFSP1_11: EPD Position          */
+#define SCU_SFSP1_11_EPD_Msk                                  (0x01UL << SCU_SFSP1_11_EPD_Pos)                          /*!< SCU SFSP1_11: EPD Mask              */
+#define SCU_SFSP1_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_11: EPUN Position         */
+#define SCU_SFSP1_11_EPUN_Msk                                 (0x01UL << SCU_SFSP1_11_EPUN_Pos)                         /*!< SCU SFSP1_11: EPUN Mask             */
+#define SCU_SFSP1_11_EHS_Pos                                  5                                                         /*!< SCU SFSP1_11: EHS Position          */
+#define SCU_SFSP1_11_EHS_Msk                                  (0x01UL << SCU_SFSP1_11_EHS_Pos)                          /*!< SCU SFSP1_11: EHS Mask              */
+#define SCU_SFSP1_11_EZI_Pos                                  6                                                         /*!< SCU SFSP1_11: EZI Position          */
+#define SCU_SFSP1_11_EZI_Msk                                  (0x01UL << SCU_SFSP1_11_EZI_Pos)                          /*!< SCU SFSP1_11: EZI Mask              */
+#define SCU_SFSP1_11_EHD_Pos                                  8                                                         /*!< SCU SFSP1_11: EHD Position          */
+#define SCU_SFSP1_11_EHD_Msk                                  (0x03UL << SCU_SFSP1_11_EHD_Pos)                          /*!< SCU SFSP1_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_12  ------------------------------------------
+#define SCU_SFSP1_12_MODE_Pos                                 0                                                         /*!< SCU SFSP1_12: MODE Position         */
+#define SCU_SFSP1_12_MODE_Msk                                 (0x07UL << SCU_SFSP1_12_MODE_Pos)                         /*!< SCU SFSP1_12: MODE Mask             */
+#define SCU_SFSP1_12_EPD_Pos                                  3                                                         /*!< SCU SFSP1_12: EPD Position          */
+#define SCU_SFSP1_12_EPD_Msk                                  (0x01UL << SCU_SFSP1_12_EPD_Pos)                          /*!< SCU SFSP1_12: EPD Mask              */
+#define SCU_SFSP1_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_12: EPUN Position         */
+#define SCU_SFSP1_12_EPUN_Msk                                 (0x01UL << SCU_SFSP1_12_EPUN_Pos)                         /*!< SCU SFSP1_12: EPUN Mask             */
+#define SCU_SFSP1_12_EHS_Pos                                  5                                                         /*!< SCU SFSP1_12: EHS Position          */
+#define SCU_SFSP1_12_EHS_Msk                                  (0x01UL << SCU_SFSP1_12_EHS_Pos)                          /*!< SCU SFSP1_12: EHS Mask              */
+#define SCU_SFSP1_12_EZI_Pos                                  6                                                         /*!< SCU SFSP1_12: EZI Position          */
+#define SCU_SFSP1_12_EZI_Msk                                  (0x01UL << SCU_SFSP1_12_EZI_Pos)                          /*!< SCU SFSP1_12: EZI Mask              */
+#define SCU_SFSP1_12_EHD_Pos                                  8                                                         /*!< SCU SFSP1_12: EHD Position          */
+#define SCU_SFSP1_12_EHD_Msk                                  (0x03UL << SCU_SFSP1_12_EHD_Pos)                          /*!< SCU SFSP1_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_13  ------------------------------------------
+#define SCU_SFSP1_13_MODE_Pos                                 0                                                         /*!< SCU SFSP1_13: MODE Position         */
+#define SCU_SFSP1_13_MODE_Msk                                 (0x07UL << SCU_SFSP1_13_MODE_Pos)                         /*!< SCU SFSP1_13: MODE Mask             */
+#define SCU_SFSP1_13_EPD_Pos                                  3                                                         /*!< SCU SFSP1_13: EPD Position          */
+#define SCU_SFSP1_13_EPD_Msk                                  (0x01UL << SCU_SFSP1_13_EPD_Pos)                          /*!< SCU SFSP1_13: EPD Mask              */
+#define SCU_SFSP1_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_13: EPUN Position         */
+#define SCU_SFSP1_13_EPUN_Msk                                 (0x01UL << SCU_SFSP1_13_EPUN_Pos)                         /*!< SCU SFSP1_13: EPUN Mask             */
+#define SCU_SFSP1_13_EHS_Pos                                  5                                                         /*!< SCU SFSP1_13: EHS Position          */
+#define SCU_SFSP1_13_EHS_Msk                                  (0x01UL << SCU_SFSP1_13_EHS_Pos)                          /*!< SCU SFSP1_13: EHS Mask              */
+#define SCU_SFSP1_13_EZI_Pos                                  6                                                         /*!< SCU SFSP1_13: EZI Position          */
+#define SCU_SFSP1_13_EZI_Msk                                  (0x01UL << SCU_SFSP1_13_EZI_Pos)                          /*!< SCU SFSP1_13: EZI Mask              */
+#define SCU_SFSP1_13_EHD_Pos                                  8                                                         /*!< SCU SFSP1_13: EHD Position          */
+#define SCU_SFSP1_13_EHD_Msk                                  (0x03UL << SCU_SFSP1_13_EHD_Pos)                          /*!< SCU SFSP1_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_14  ------------------------------------------
+#define SCU_SFSP1_14_MODE_Pos                                 0                                                         /*!< SCU SFSP1_14: MODE Position         */
+#define SCU_SFSP1_14_MODE_Msk                                 (0x07UL << SCU_SFSP1_14_MODE_Pos)                         /*!< SCU SFSP1_14: MODE Mask             */
+#define SCU_SFSP1_14_EPD_Pos                                  3                                                         /*!< SCU SFSP1_14: EPD Position          */
+#define SCU_SFSP1_14_EPD_Msk                                  (0x01UL << SCU_SFSP1_14_EPD_Pos)                          /*!< SCU SFSP1_14: EPD Mask              */
+#define SCU_SFSP1_14_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_14: EPUN Position         */
+#define SCU_SFSP1_14_EPUN_Msk                                 (0x01UL << SCU_SFSP1_14_EPUN_Pos)                         /*!< SCU SFSP1_14: EPUN Mask             */
+#define SCU_SFSP1_14_EHS_Pos                                  5                                                         /*!< SCU SFSP1_14: EHS Position          */
+#define SCU_SFSP1_14_EHS_Msk                                  (0x01UL << SCU_SFSP1_14_EHS_Pos)                          /*!< SCU SFSP1_14: EHS Mask              */
+#define SCU_SFSP1_14_EZI_Pos                                  6                                                         /*!< SCU SFSP1_14: EZI Position          */
+#define SCU_SFSP1_14_EZI_Msk                                  (0x01UL << SCU_SFSP1_14_EZI_Pos)                          /*!< SCU SFSP1_14: EZI Mask              */
+#define SCU_SFSP1_14_EHD_Pos                                  8                                                         /*!< SCU SFSP1_14: EHD Position          */
+#define SCU_SFSP1_14_EHD_Msk                                  (0x03UL << SCU_SFSP1_14_EHD_Pos)                          /*!< SCU SFSP1_14: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_15  ------------------------------------------
+#define SCU_SFSP1_15_MODE_Pos                                 0                                                         /*!< SCU SFSP1_15: MODE Position         */
+#define SCU_SFSP1_15_MODE_Msk                                 (0x07UL << SCU_SFSP1_15_MODE_Pos)                         /*!< SCU SFSP1_15: MODE Mask             */
+#define SCU_SFSP1_15_EPD_Pos                                  3                                                         /*!< SCU SFSP1_15: EPD Position          */
+#define SCU_SFSP1_15_EPD_Msk                                  (0x01UL << SCU_SFSP1_15_EPD_Pos)                          /*!< SCU SFSP1_15: EPD Mask              */
+#define SCU_SFSP1_15_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_15: EPUN Position         */
+#define SCU_SFSP1_15_EPUN_Msk                                 (0x01UL << SCU_SFSP1_15_EPUN_Pos)                         /*!< SCU SFSP1_15: EPUN Mask             */
+#define SCU_SFSP1_15_EHS_Pos                                  5                                                         /*!< SCU SFSP1_15: EHS Position          */
+#define SCU_SFSP1_15_EHS_Msk                                  (0x01UL << SCU_SFSP1_15_EHS_Pos)                          /*!< SCU SFSP1_15: EHS Mask              */
+#define SCU_SFSP1_15_EZI_Pos                                  6                                                         /*!< SCU SFSP1_15: EZI Position          */
+#define SCU_SFSP1_15_EZI_Msk                                  (0x01UL << SCU_SFSP1_15_EZI_Pos)                          /*!< SCU SFSP1_15: EZI Mask              */
+#define SCU_SFSP1_15_EHD_Pos                                  8                                                         /*!< SCU SFSP1_15: EHD Position          */
+#define SCU_SFSP1_15_EHD_Msk                                  (0x03UL << SCU_SFSP1_15_EHD_Pos)                          /*!< SCU SFSP1_15: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_16  ------------------------------------------
+#define SCU_SFSP1_16_MODE_Pos                                 0                                                         /*!< SCU SFSP1_16: MODE Position         */
+#define SCU_SFSP1_16_MODE_Msk                                 (0x07UL << SCU_SFSP1_16_MODE_Pos)                         /*!< SCU SFSP1_16: MODE Mask             */
+#define SCU_SFSP1_16_EPD_Pos                                  3                                                         /*!< SCU SFSP1_16: EPD Position          */
+#define SCU_SFSP1_16_EPD_Msk                                  (0x01UL << SCU_SFSP1_16_EPD_Pos)                          /*!< SCU SFSP1_16: EPD Mask              */
+#define SCU_SFSP1_16_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_16: EPUN Position         */
+#define SCU_SFSP1_16_EPUN_Msk                                 (0x01UL << SCU_SFSP1_16_EPUN_Pos)                         /*!< SCU SFSP1_16: EPUN Mask             */
+#define SCU_SFSP1_16_EHS_Pos                                  5                                                         /*!< SCU SFSP1_16: EHS Position          */
+#define SCU_SFSP1_16_EHS_Msk                                  (0x01UL << SCU_SFSP1_16_EHS_Pos)                          /*!< SCU SFSP1_16: EHS Mask              */
+#define SCU_SFSP1_16_EZI_Pos                                  6                                                         /*!< SCU SFSP1_16: EZI Position          */
+#define SCU_SFSP1_16_EZI_Msk                                  (0x01UL << SCU_SFSP1_16_EZI_Pos)                          /*!< SCU SFSP1_16: EZI Mask              */
+#define SCU_SFSP1_16_EHD_Pos                                  8                                                         /*!< SCU SFSP1_16: EHD Position          */
+#define SCU_SFSP1_16_EHD_Msk                                  (0x03UL << SCU_SFSP1_16_EHD_Pos)                          /*!< SCU SFSP1_16: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_17  ------------------------------------------
+#define SCU_SFSP1_17_MODE_Pos                                 0                                                         /*!< SCU SFSP1_17: MODE Position         */
+#define SCU_SFSP1_17_MODE_Msk                                 (0x07UL << SCU_SFSP1_17_MODE_Pos)                         /*!< SCU SFSP1_17: MODE Mask             */
+#define SCU_SFSP1_17_EPD_Pos                                  3                                                         /*!< SCU SFSP1_17: EPD Position          */
+#define SCU_SFSP1_17_EPD_Msk                                  (0x01UL << SCU_SFSP1_17_EPD_Pos)                          /*!< SCU SFSP1_17: EPD Mask              */
+#define SCU_SFSP1_17_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_17: EPUN Position         */
+#define SCU_SFSP1_17_EPUN_Msk                                 (0x01UL << SCU_SFSP1_17_EPUN_Pos)                         /*!< SCU SFSP1_17: EPUN Mask             */
+#define SCU_SFSP1_17_EHS_Pos                                  5                                                         /*!< SCU SFSP1_17: EHS Position          */
+#define SCU_SFSP1_17_EHS_Msk                                  (0x01UL << SCU_SFSP1_17_EHS_Pos)                          /*!< SCU SFSP1_17: EHS Mask              */
+#define SCU_SFSP1_17_EZI_Pos                                  6                                                         /*!< SCU SFSP1_17: EZI Position          */
+#define SCU_SFSP1_17_EZI_Msk                                  (0x01UL << SCU_SFSP1_17_EZI_Pos)                          /*!< SCU SFSP1_17: EZI Mask              */
+#define SCU_SFSP1_17_EHD_Pos                                  8                                                         /*!< SCU SFSP1_17: EHD Position          */
+#define SCU_SFSP1_17_EHD_Msk                                  (0x03UL << SCU_SFSP1_17_EHD_Pos)                          /*!< SCU SFSP1_17: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_18  ------------------------------------------
+#define SCU_SFSP1_18_MODE_Pos                                 0                                                         /*!< SCU SFSP1_18: MODE Position         */
+#define SCU_SFSP1_18_MODE_Msk                                 (0x07UL << SCU_SFSP1_18_MODE_Pos)                         /*!< SCU SFSP1_18: MODE Mask             */
+#define SCU_SFSP1_18_EPD_Pos                                  3                                                         /*!< SCU SFSP1_18: EPD Position          */
+#define SCU_SFSP1_18_EPD_Msk                                  (0x01UL << SCU_SFSP1_18_EPD_Pos)                          /*!< SCU SFSP1_18: EPD Mask              */
+#define SCU_SFSP1_18_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_18: EPUN Position         */
+#define SCU_SFSP1_18_EPUN_Msk                                 (0x01UL << SCU_SFSP1_18_EPUN_Pos)                         /*!< SCU SFSP1_18: EPUN Mask             */
+#define SCU_SFSP1_18_EHS_Pos                                  5                                                         /*!< SCU SFSP1_18: EHS Position          */
+#define SCU_SFSP1_18_EHS_Msk                                  (0x01UL << SCU_SFSP1_18_EHS_Pos)                          /*!< SCU SFSP1_18: EHS Mask              */
+#define SCU_SFSP1_18_EZI_Pos                                  6                                                         /*!< SCU SFSP1_18: EZI Position          */
+#define SCU_SFSP1_18_EZI_Msk                                  (0x01UL << SCU_SFSP1_18_EZI_Pos)                          /*!< SCU SFSP1_18: EZI Mask              */
+#define SCU_SFSP1_18_EHD_Pos                                  8                                                         /*!< SCU SFSP1_18: EHD Position          */
+#define SCU_SFSP1_18_EHD_Msk                                  (0x03UL << SCU_SFSP1_18_EHD_Pos)                          /*!< SCU SFSP1_18: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_19  ------------------------------------------
+#define SCU_SFSP1_19_MODE_Pos                                 0                                                         /*!< SCU SFSP1_19: MODE Position         */
+#define SCU_SFSP1_19_MODE_Msk                                 (0x07UL << SCU_SFSP1_19_MODE_Pos)                         /*!< SCU SFSP1_19: MODE Mask             */
+#define SCU_SFSP1_19_EPD_Pos                                  3                                                         /*!< SCU SFSP1_19: EPD Position          */
+#define SCU_SFSP1_19_EPD_Msk                                  (0x01UL << SCU_SFSP1_19_EPD_Pos)                          /*!< SCU SFSP1_19: EPD Mask              */
+#define SCU_SFSP1_19_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_19: EPUN Position         */
+#define SCU_SFSP1_19_EPUN_Msk                                 (0x01UL << SCU_SFSP1_19_EPUN_Pos)                         /*!< SCU SFSP1_19: EPUN Mask             */
+#define SCU_SFSP1_19_EHS_Pos                                  5                                                         /*!< SCU SFSP1_19: EHS Position          */
+#define SCU_SFSP1_19_EHS_Msk                                  (0x01UL << SCU_SFSP1_19_EHS_Pos)                          /*!< SCU SFSP1_19: EHS Mask              */
+#define SCU_SFSP1_19_EZI_Pos                                  6                                                         /*!< SCU SFSP1_19: EZI Position          */
+#define SCU_SFSP1_19_EZI_Msk                                  (0x01UL << SCU_SFSP1_19_EZI_Pos)                          /*!< SCU SFSP1_19: EZI Mask              */
+#define SCU_SFSP1_19_EHD_Pos                                  8                                                         /*!< SCU SFSP1_19: EHD Position          */
+#define SCU_SFSP1_19_EHD_Msk                                  (0x03UL << SCU_SFSP1_19_EHD_Pos)                          /*!< SCU SFSP1_19: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_20  ------------------------------------------
+#define SCU_SFSP1_20_MODE_Pos                                 0                                                         /*!< SCU SFSP1_20: MODE Position         */
+#define SCU_SFSP1_20_MODE_Msk                                 (0x07UL << SCU_SFSP1_20_MODE_Pos)                         /*!< SCU SFSP1_20: MODE Mask             */
+#define SCU_SFSP1_20_EPD_Pos                                  3                                                         /*!< SCU SFSP1_20: EPD Position          */
+#define SCU_SFSP1_20_EPD_Msk                                  (0x01UL << SCU_SFSP1_20_EPD_Pos)                          /*!< SCU SFSP1_20: EPD Mask              */
+#define SCU_SFSP1_20_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_20: EPUN Position         */
+#define SCU_SFSP1_20_EPUN_Msk                                 (0x01UL << SCU_SFSP1_20_EPUN_Pos)                         /*!< SCU SFSP1_20: EPUN Mask             */
+#define SCU_SFSP1_20_EHS_Pos                                  5                                                         /*!< SCU SFSP1_20: EHS Position          */
+#define SCU_SFSP1_20_EHS_Msk                                  (0x01UL << SCU_SFSP1_20_EHS_Pos)                          /*!< SCU SFSP1_20: EHS Mask              */
+#define SCU_SFSP1_20_EZI_Pos                                  6                                                         /*!< SCU SFSP1_20: EZI Position          */
+#define SCU_SFSP1_20_EZI_Msk                                  (0x01UL << SCU_SFSP1_20_EZI_Pos)                          /*!< SCU SFSP1_20: EZI Mask              */
+#define SCU_SFSP1_20_EHD_Pos                                  8                                                         /*!< SCU SFSP1_20: EHD Position          */
+#define SCU_SFSP1_20_EHD_Msk                                  (0x03UL << SCU_SFSP1_20_EHD_Pos)                          /*!< SCU SFSP1_20: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP2_0  ------------------------------------------
+#define SCU_SFSP2_0_MODE_Pos                                  0                                                         /*!< SCU SFSP2_0: MODE Position          */
+#define SCU_SFSP2_0_MODE_Msk                                  (0x07UL << SCU_SFSP2_0_MODE_Pos)                          /*!< SCU SFSP2_0: MODE Mask              */
+#define SCU_SFSP2_0_EPD_Pos                                   3                                                         /*!< SCU SFSP2_0: EPD Position           */
+#define SCU_SFSP2_0_EPD_Msk                                   (0x01UL << SCU_SFSP2_0_EPD_Pos)                           /*!< SCU SFSP2_0: EPD Mask               */
+#define SCU_SFSP2_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_0: EPUN Position          */
+#define SCU_SFSP2_0_EPUN_Msk                                  (0x01UL << SCU_SFSP2_0_EPUN_Pos)                          /*!< SCU SFSP2_0: EPUN Mask              */
+#define SCU_SFSP2_0_EHS_Pos                                   5                                                         /*!< SCU SFSP2_0: EHS Position           */
+#define SCU_SFSP2_0_EHS_Msk                                   (0x01UL << SCU_SFSP2_0_EHS_Pos)                           /*!< SCU SFSP2_0: EHS Mask               */
+#define SCU_SFSP2_0_EZI_Pos                                   6                                                         /*!< SCU SFSP2_0: EZI Position           */
+#define SCU_SFSP2_0_EZI_Msk                                   (0x01UL << SCU_SFSP2_0_EZI_Pos)                           /*!< SCU SFSP2_0: EZI Mask               */
+#define SCU_SFSP2_0_EHD_Pos                                   8                                                         /*!< SCU SFSP2_0: EHD Position           */
+#define SCU_SFSP2_0_EHD_Msk                                   (0x03UL << SCU_SFSP2_0_EHD_Pos)                           /*!< SCU SFSP2_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_1  ------------------------------------------
+#define SCU_SFSP2_1_MODE_Pos                                  0                                                         /*!< SCU SFSP2_1: MODE Position          */
+#define SCU_SFSP2_1_MODE_Msk                                  (0x07UL << SCU_SFSP2_1_MODE_Pos)                          /*!< SCU SFSP2_1: MODE Mask              */
+#define SCU_SFSP2_1_EPD_Pos                                   3                                                         /*!< SCU SFSP2_1: EPD Position           */
+#define SCU_SFSP2_1_EPD_Msk                                   (0x01UL << SCU_SFSP2_1_EPD_Pos)                           /*!< SCU SFSP2_1: EPD Mask               */
+#define SCU_SFSP2_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_1: EPUN Position          */
+#define SCU_SFSP2_1_EPUN_Msk                                  (0x01UL << SCU_SFSP2_1_EPUN_Pos)                          /*!< SCU SFSP2_1: EPUN Mask              */
+#define SCU_SFSP2_1_EHS_Pos                                   5                                                         /*!< SCU SFSP2_1: EHS Position           */
+#define SCU_SFSP2_1_EHS_Msk                                   (0x01UL << SCU_SFSP2_1_EHS_Pos)                           /*!< SCU SFSP2_1: EHS Mask               */
+#define SCU_SFSP2_1_EZI_Pos                                   6                                                         /*!< SCU SFSP2_1: EZI Position           */
+#define SCU_SFSP2_1_EZI_Msk                                   (0x01UL << SCU_SFSP2_1_EZI_Pos)                           /*!< SCU SFSP2_1: EZI Mask               */
+#define SCU_SFSP2_1_EHD_Pos                                   8                                                         /*!< SCU SFSP2_1: EHD Position           */
+#define SCU_SFSP2_1_EHD_Msk                                   (0x03UL << SCU_SFSP2_1_EHD_Pos)                           /*!< SCU SFSP2_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_2  ------------------------------------------
+#define SCU_SFSP2_2_MODE_Pos                                  0                                                         /*!< SCU SFSP2_2: MODE Position          */
+#define SCU_SFSP2_2_MODE_Msk                                  (0x07UL << SCU_SFSP2_2_MODE_Pos)                          /*!< SCU SFSP2_2: MODE Mask              */
+#define SCU_SFSP2_2_EPD_Pos                                   3                                                         /*!< SCU SFSP2_2: EPD Position           */
+#define SCU_SFSP2_2_EPD_Msk                                   (0x01UL << SCU_SFSP2_2_EPD_Pos)                           /*!< SCU SFSP2_2: EPD Mask               */
+#define SCU_SFSP2_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_2: EPUN Position          */
+#define SCU_SFSP2_2_EPUN_Msk                                  (0x01UL << SCU_SFSP2_2_EPUN_Pos)                          /*!< SCU SFSP2_2: EPUN Mask              */
+#define SCU_SFSP2_2_EHS_Pos                                   5                                                         /*!< SCU SFSP2_2: EHS Position           */
+#define SCU_SFSP2_2_EHS_Msk                                   (0x01UL << SCU_SFSP2_2_EHS_Pos)                           /*!< SCU SFSP2_2: EHS Mask               */
+#define SCU_SFSP2_2_EZI_Pos                                   6                                                         /*!< SCU SFSP2_2: EZI Position           */
+#define SCU_SFSP2_2_EZI_Msk                                   (0x01UL << SCU_SFSP2_2_EZI_Pos)                           /*!< SCU SFSP2_2: EZI Mask               */
+#define SCU_SFSP2_2_EHD_Pos                                   8                                                         /*!< SCU SFSP2_2: EHD Position           */
+#define SCU_SFSP2_2_EHD_Msk                                   (0x03UL << SCU_SFSP2_2_EHD_Pos)                           /*!< SCU SFSP2_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_3  ------------------------------------------
+#define SCU_SFSP2_3_MODE_Pos                                  0                                                         /*!< SCU SFSP2_3: MODE Position          */
+#define SCU_SFSP2_3_MODE_Msk                                  (0x07UL << SCU_SFSP2_3_MODE_Pos)                          /*!< SCU SFSP2_3: MODE Mask              */
+#define SCU_SFSP2_3_EPD_Pos                                   3                                                         /*!< SCU SFSP2_3: EPD Position           */
+#define SCU_SFSP2_3_EPD_Msk                                   (0x01UL << SCU_SFSP2_3_EPD_Pos)                           /*!< SCU SFSP2_3: EPD Mask               */
+#define SCU_SFSP2_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_3: EPUN Position          */
+#define SCU_SFSP2_3_EPUN_Msk                                  (0x01UL << SCU_SFSP2_3_EPUN_Pos)                          /*!< SCU SFSP2_3: EPUN Mask              */
+#define SCU_SFSP2_3_EHS_Pos                                   5                                                         /*!< SCU SFSP2_3: EHS Position           */
+#define SCU_SFSP2_3_EHS_Msk                                   (0x01UL << SCU_SFSP2_3_EHS_Pos)                           /*!< SCU SFSP2_3: EHS Mask               */
+#define SCU_SFSP2_3_EZI_Pos                                   6                                                         /*!< SCU SFSP2_3: EZI Position           */
+#define SCU_SFSP2_3_EZI_Msk                                   (0x01UL << SCU_SFSP2_3_EZI_Pos)                           /*!< SCU SFSP2_3: EZI Mask               */
+#define SCU_SFSP2_3_EHD_Pos                                   8                                                         /*!< SCU SFSP2_3: EHD Position           */
+#define SCU_SFSP2_3_EHD_Msk                                   (0x03UL << SCU_SFSP2_3_EHD_Pos)                           /*!< SCU SFSP2_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_4  ------------------------------------------
+#define SCU_SFSP2_4_MODE_Pos                                  0                                                         /*!< SCU SFSP2_4: MODE Position          */
+#define SCU_SFSP2_4_MODE_Msk                                  (0x07UL << SCU_SFSP2_4_MODE_Pos)                          /*!< SCU SFSP2_4: MODE Mask              */
+#define SCU_SFSP2_4_EPD_Pos                                   3                                                         /*!< SCU SFSP2_4: EPD Position           */
+#define SCU_SFSP2_4_EPD_Msk                                   (0x01UL << SCU_SFSP2_4_EPD_Pos)                           /*!< SCU SFSP2_4: EPD Mask               */
+#define SCU_SFSP2_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_4: EPUN Position          */
+#define SCU_SFSP2_4_EPUN_Msk                                  (0x01UL << SCU_SFSP2_4_EPUN_Pos)                          /*!< SCU SFSP2_4: EPUN Mask              */
+#define SCU_SFSP2_4_EHS_Pos                                   5                                                         /*!< SCU SFSP2_4: EHS Position           */
+#define SCU_SFSP2_4_EHS_Msk                                   (0x01UL << SCU_SFSP2_4_EHS_Pos)                           /*!< SCU SFSP2_4: EHS Mask               */
+#define SCU_SFSP2_4_EZI_Pos                                   6                                                         /*!< SCU SFSP2_4: EZI Position           */
+#define SCU_SFSP2_4_EZI_Msk                                   (0x01UL << SCU_SFSP2_4_EZI_Pos)                           /*!< SCU SFSP2_4: EZI Mask               */
+#define SCU_SFSP2_4_EHD_Pos                                   8                                                         /*!< SCU SFSP2_4: EHD Position           */
+#define SCU_SFSP2_4_EHD_Msk                                   (0x03UL << SCU_SFSP2_4_EHD_Pos)                           /*!< SCU SFSP2_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_5  ------------------------------------------
+#define SCU_SFSP2_5_MODE_Pos                                  0                                                         /*!< SCU SFSP2_5: MODE Position          */
+#define SCU_SFSP2_5_MODE_Msk                                  (0x07UL << SCU_SFSP2_5_MODE_Pos)                          /*!< SCU SFSP2_5: MODE Mask              */
+#define SCU_SFSP2_5_EPD_Pos                                   3                                                         /*!< SCU SFSP2_5: EPD Position           */
+#define SCU_SFSP2_5_EPD_Msk                                   (0x01UL << SCU_SFSP2_5_EPD_Pos)                           /*!< SCU SFSP2_5: EPD Mask               */
+#define SCU_SFSP2_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_5: EPUN Position          */
+#define SCU_SFSP2_5_EPUN_Msk                                  (0x01UL << SCU_SFSP2_5_EPUN_Pos)                          /*!< SCU SFSP2_5: EPUN Mask              */
+#define SCU_SFSP2_5_EHS_Pos                                   5                                                         /*!< SCU SFSP2_5: EHS Position           */
+#define SCU_SFSP2_5_EHS_Msk                                   (0x01UL << SCU_SFSP2_5_EHS_Pos)                           /*!< SCU SFSP2_5: EHS Mask               */
+#define SCU_SFSP2_5_EZI_Pos                                   6                                                         /*!< SCU SFSP2_5: EZI Position           */
+#define SCU_SFSP2_5_EZI_Msk                                   (0x01UL << SCU_SFSP2_5_EZI_Pos)                           /*!< SCU SFSP2_5: EZI Mask               */
+#define SCU_SFSP2_5_EHD_Pos                                   8                                                         /*!< SCU SFSP2_5: EHD Position           */
+#define SCU_SFSP2_5_EHD_Msk                                   (0x03UL << SCU_SFSP2_5_EHD_Pos)                           /*!< SCU SFSP2_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_6  ------------------------------------------
+#define SCU_SFSP2_6_MODE_Pos                                  0                                                         /*!< SCU SFSP2_6: MODE Position          */
+#define SCU_SFSP2_6_MODE_Msk                                  (0x07UL << SCU_SFSP2_6_MODE_Pos)                          /*!< SCU SFSP2_6: MODE Mask              */
+#define SCU_SFSP2_6_EPD_Pos                                   3                                                         /*!< SCU SFSP2_6: EPD Position           */
+#define SCU_SFSP2_6_EPD_Msk                                   (0x01UL << SCU_SFSP2_6_EPD_Pos)                           /*!< SCU SFSP2_6: EPD Mask               */
+#define SCU_SFSP2_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_6: EPUN Position          */
+#define SCU_SFSP2_6_EPUN_Msk                                  (0x01UL << SCU_SFSP2_6_EPUN_Pos)                          /*!< SCU SFSP2_6: EPUN Mask              */
+#define SCU_SFSP2_6_EHS_Pos                                   5                                                         /*!< SCU SFSP2_6: EHS Position           */
+#define SCU_SFSP2_6_EHS_Msk                                   (0x01UL << SCU_SFSP2_6_EHS_Pos)                           /*!< SCU SFSP2_6: EHS Mask               */
+#define SCU_SFSP2_6_EZI_Pos                                   6                                                         /*!< SCU SFSP2_6: EZI Position           */
+#define SCU_SFSP2_6_EZI_Msk                                   (0x01UL << SCU_SFSP2_6_EZI_Pos)                           /*!< SCU SFSP2_6: EZI Mask               */
+#define SCU_SFSP2_6_EHD_Pos                                   8                                                         /*!< SCU SFSP2_6: EHD Position           */
+#define SCU_SFSP2_6_EHD_Msk                                   (0x03UL << SCU_SFSP2_6_EHD_Pos)                           /*!< SCU SFSP2_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_7  ------------------------------------------
+#define SCU_SFSP2_7_MODE_Pos                                  0                                                         /*!< SCU SFSP2_7: MODE Position          */
+#define SCU_SFSP2_7_MODE_Msk                                  (0x07UL << SCU_SFSP2_7_MODE_Pos)                          /*!< SCU SFSP2_7: MODE Mask              */
+#define SCU_SFSP2_7_EPD_Pos                                   3                                                         /*!< SCU SFSP2_7: EPD Position           */
+#define SCU_SFSP2_7_EPD_Msk                                   (0x01UL << SCU_SFSP2_7_EPD_Pos)                           /*!< SCU SFSP2_7: EPD Mask               */
+#define SCU_SFSP2_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_7: EPUN Position          */
+#define SCU_SFSP2_7_EPUN_Msk                                  (0x01UL << SCU_SFSP2_7_EPUN_Pos)                          /*!< SCU SFSP2_7: EPUN Mask              */
+#define SCU_SFSP2_7_EHS_Pos                                   5                                                         /*!< SCU SFSP2_7: EHS Position           */
+#define SCU_SFSP2_7_EHS_Msk                                   (0x01UL << SCU_SFSP2_7_EHS_Pos)                           /*!< SCU SFSP2_7: EHS Mask               */
+#define SCU_SFSP2_7_EZI_Pos                                   6                                                         /*!< SCU SFSP2_7: EZI Position           */
+#define SCU_SFSP2_7_EZI_Msk                                   (0x01UL << SCU_SFSP2_7_EZI_Pos)                           /*!< SCU SFSP2_7: EZI Mask               */
+#define SCU_SFSP2_7_EHD_Pos                                   8                                                         /*!< SCU SFSP2_7: EHD Position           */
+#define SCU_SFSP2_7_EHD_Msk                                   (0x03UL << SCU_SFSP2_7_EHD_Pos)                           /*!< SCU SFSP2_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_8  ------------------------------------------
+#define SCU_SFSP2_8_MODE_Pos                                  0                                                         /*!< SCU SFSP2_8: MODE Position          */
+#define SCU_SFSP2_8_MODE_Msk                                  (0x07UL << SCU_SFSP2_8_MODE_Pos)                          /*!< SCU SFSP2_8: MODE Mask              */
+#define SCU_SFSP2_8_EPD_Pos                                   3                                                         /*!< SCU SFSP2_8: EPD Position           */
+#define SCU_SFSP2_8_EPD_Msk                                   (0x01UL << SCU_SFSP2_8_EPD_Pos)                           /*!< SCU SFSP2_8: EPD Mask               */
+#define SCU_SFSP2_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_8: EPUN Position          */
+#define SCU_SFSP2_8_EPUN_Msk                                  (0x01UL << SCU_SFSP2_8_EPUN_Pos)                          /*!< SCU SFSP2_8: EPUN Mask              */
+#define SCU_SFSP2_8_EHS_Pos                                   5                                                         /*!< SCU SFSP2_8: EHS Position           */
+#define SCU_SFSP2_8_EHS_Msk                                   (0x01UL << SCU_SFSP2_8_EHS_Pos)                           /*!< SCU SFSP2_8: EHS Mask               */
+#define SCU_SFSP2_8_EZI_Pos                                   6                                                         /*!< SCU SFSP2_8: EZI Position           */
+#define SCU_SFSP2_8_EZI_Msk                                   (0x01UL << SCU_SFSP2_8_EZI_Pos)                           /*!< SCU SFSP2_8: EZI Mask               */
+#define SCU_SFSP2_8_EHD_Pos                                   8                                                         /*!< SCU SFSP2_8: EHD Position           */
+#define SCU_SFSP2_8_EHD_Msk                                   (0x03UL << SCU_SFSP2_8_EHD_Pos)                           /*!< SCU SFSP2_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_9  ------------------------------------------
+#define SCU_SFSP2_9_MODE_Pos                                  0                                                         /*!< SCU SFSP2_9: MODE Position          */
+#define SCU_SFSP2_9_MODE_Msk                                  (0x07UL << SCU_SFSP2_9_MODE_Pos)                          /*!< SCU SFSP2_9: MODE Mask              */
+#define SCU_SFSP2_9_EPD_Pos                                   3                                                         /*!< SCU SFSP2_9: EPD Position           */
+#define SCU_SFSP2_9_EPD_Msk                                   (0x01UL << SCU_SFSP2_9_EPD_Pos)                           /*!< SCU SFSP2_9: EPD Mask               */
+#define SCU_SFSP2_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_9: EPUN Position          */
+#define SCU_SFSP2_9_EPUN_Msk                                  (0x01UL << SCU_SFSP2_9_EPUN_Pos)                          /*!< SCU SFSP2_9: EPUN Mask              */
+#define SCU_SFSP2_9_EHS_Pos                                   5                                                         /*!< SCU SFSP2_9: EHS Position           */
+#define SCU_SFSP2_9_EHS_Msk                                   (0x01UL << SCU_SFSP2_9_EHS_Pos)                           /*!< SCU SFSP2_9: EHS Mask               */
+#define SCU_SFSP2_9_EZI_Pos                                   6                                                         /*!< SCU SFSP2_9: EZI Position           */
+#define SCU_SFSP2_9_EZI_Msk                                   (0x01UL << SCU_SFSP2_9_EZI_Pos)                           /*!< SCU SFSP2_9: EZI Mask               */
+#define SCU_SFSP2_9_EHD_Pos                                   8                                                         /*!< SCU SFSP2_9: EHD Position           */
+#define SCU_SFSP2_9_EHD_Msk                                   (0x03UL << SCU_SFSP2_9_EHD_Pos)                           /*!< SCU SFSP2_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP2_10  ------------------------------------------
+#define SCU_SFSP2_10_MODE_Pos                                 0                                                         /*!< SCU SFSP2_10: MODE Position         */
+#define SCU_SFSP2_10_MODE_Msk                                 (0x07UL << SCU_SFSP2_10_MODE_Pos)                         /*!< SCU SFSP2_10: MODE Mask             */
+#define SCU_SFSP2_10_EPD_Pos                                  3                                                         /*!< SCU SFSP2_10: EPD Position          */
+#define SCU_SFSP2_10_EPD_Msk                                  (0x01UL << SCU_SFSP2_10_EPD_Pos)                          /*!< SCU SFSP2_10: EPD Mask              */
+#define SCU_SFSP2_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_10: EPUN Position         */
+#define SCU_SFSP2_10_EPUN_Msk                                 (0x01UL << SCU_SFSP2_10_EPUN_Pos)                         /*!< SCU SFSP2_10: EPUN Mask             */
+#define SCU_SFSP2_10_EHS_Pos                                  5                                                         /*!< SCU SFSP2_10: EHS Position          */
+#define SCU_SFSP2_10_EHS_Msk                                  (0x01UL << SCU_SFSP2_10_EHS_Pos)                          /*!< SCU SFSP2_10: EHS Mask              */
+#define SCU_SFSP2_10_EZI_Pos                                  6                                                         /*!< SCU SFSP2_10: EZI Position          */
+#define SCU_SFSP2_10_EZI_Msk                                  (0x01UL << SCU_SFSP2_10_EZI_Pos)                          /*!< SCU SFSP2_10: EZI Mask              */
+#define SCU_SFSP2_10_EHD_Pos                                  8                                                         /*!< SCU SFSP2_10: EHD Position          */
+#define SCU_SFSP2_10_EHD_Msk                                  (0x03UL << SCU_SFSP2_10_EHD_Pos)                          /*!< SCU SFSP2_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP2_11  ------------------------------------------
+#define SCU_SFSP2_11_MODE_Pos                                 0                                                         /*!< SCU SFSP2_11: MODE Position         */
+#define SCU_SFSP2_11_MODE_Msk                                 (0x07UL << SCU_SFSP2_11_MODE_Pos)                         /*!< SCU SFSP2_11: MODE Mask             */
+#define SCU_SFSP2_11_EPD_Pos                                  3                                                         /*!< SCU SFSP2_11: EPD Position          */
+#define SCU_SFSP2_11_EPD_Msk                                  (0x01UL << SCU_SFSP2_11_EPD_Pos)                          /*!< SCU SFSP2_11: EPD Mask              */
+#define SCU_SFSP2_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_11: EPUN Position         */
+#define SCU_SFSP2_11_EPUN_Msk                                 (0x01UL << SCU_SFSP2_11_EPUN_Pos)                         /*!< SCU SFSP2_11: EPUN Mask             */
+#define SCU_SFSP2_11_EHS_Pos                                  5                                                         /*!< SCU SFSP2_11: EHS Position          */
+#define SCU_SFSP2_11_EHS_Msk                                  (0x01UL << SCU_SFSP2_11_EHS_Pos)                          /*!< SCU SFSP2_11: EHS Mask              */
+#define SCU_SFSP2_11_EZI_Pos                                  6                                                         /*!< SCU SFSP2_11: EZI Position          */
+#define SCU_SFSP2_11_EZI_Msk                                  (0x01UL << SCU_SFSP2_11_EZI_Pos)                          /*!< SCU SFSP2_11: EZI Mask              */
+#define SCU_SFSP2_11_EHD_Pos                                  8                                                         /*!< SCU SFSP2_11: EHD Position          */
+#define SCU_SFSP2_11_EHD_Msk                                  (0x03UL << SCU_SFSP2_11_EHD_Pos)                          /*!< SCU SFSP2_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP2_12  ------------------------------------------
+#define SCU_SFSP2_12_MODE_Pos                                 0                                                         /*!< SCU SFSP2_12: MODE Position         */
+#define SCU_SFSP2_12_MODE_Msk                                 (0x07UL << SCU_SFSP2_12_MODE_Pos)                         /*!< SCU SFSP2_12: MODE Mask             */
+#define SCU_SFSP2_12_EPD_Pos                                  3                                                         /*!< SCU SFSP2_12: EPD Position          */
+#define SCU_SFSP2_12_EPD_Msk                                  (0x01UL << SCU_SFSP2_12_EPD_Pos)                          /*!< SCU SFSP2_12: EPD Mask              */
+#define SCU_SFSP2_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_12: EPUN Position         */
+#define SCU_SFSP2_12_EPUN_Msk                                 (0x01UL << SCU_SFSP2_12_EPUN_Pos)                         /*!< SCU SFSP2_12: EPUN Mask             */
+#define SCU_SFSP2_12_EHS_Pos                                  5                                                         /*!< SCU SFSP2_12: EHS Position          */
+#define SCU_SFSP2_12_EHS_Msk                                  (0x01UL << SCU_SFSP2_12_EHS_Pos)                          /*!< SCU SFSP2_12: EHS Mask              */
+#define SCU_SFSP2_12_EZI_Pos                                  6                                                         /*!< SCU SFSP2_12: EZI Position          */
+#define SCU_SFSP2_12_EZI_Msk                                  (0x01UL << SCU_SFSP2_12_EZI_Pos)                          /*!< SCU SFSP2_12: EZI Mask              */
+#define SCU_SFSP2_12_EHD_Pos                                  8                                                         /*!< SCU SFSP2_12: EHD Position          */
+#define SCU_SFSP2_12_EHD_Msk                                  (0x03UL << SCU_SFSP2_12_EHD_Pos)                          /*!< SCU SFSP2_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP2_13  ------------------------------------------
+#define SCU_SFSP2_13_MODE_Pos                                 0                                                         /*!< SCU SFSP2_13: MODE Position         */
+#define SCU_SFSP2_13_MODE_Msk                                 (0x07UL << SCU_SFSP2_13_MODE_Pos)                         /*!< SCU SFSP2_13: MODE Mask             */
+#define SCU_SFSP2_13_EPD_Pos                                  3                                                         /*!< SCU SFSP2_13: EPD Position          */
+#define SCU_SFSP2_13_EPD_Msk                                  (0x01UL << SCU_SFSP2_13_EPD_Pos)                          /*!< SCU SFSP2_13: EPD Mask              */
+#define SCU_SFSP2_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_13: EPUN Position         */
+#define SCU_SFSP2_13_EPUN_Msk                                 (0x01UL << SCU_SFSP2_13_EPUN_Pos)                         /*!< SCU SFSP2_13: EPUN Mask             */
+#define SCU_SFSP2_13_EHS_Pos                                  5                                                         /*!< SCU SFSP2_13: EHS Position          */
+#define SCU_SFSP2_13_EHS_Msk                                  (0x01UL << SCU_SFSP2_13_EHS_Pos)                          /*!< SCU SFSP2_13: EHS Mask              */
+#define SCU_SFSP2_13_EZI_Pos                                  6                                                         /*!< SCU SFSP2_13: EZI Position          */
+#define SCU_SFSP2_13_EZI_Msk                                  (0x01UL << SCU_SFSP2_13_EZI_Pos)                          /*!< SCU SFSP2_13: EZI Mask              */
+#define SCU_SFSP2_13_EHD_Pos                                  8                                                         /*!< SCU SFSP2_13: EHD Position          */
+#define SCU_SFSP2_13_EHD_Msk                                  (0x03UL << SCU_SFSP2_13_EHD_Pos)                          /*!< SCU SFSP2_13: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP3_0  ------------------------------------------
+#define SCU_SFSP3_0_MODE_Pos                                  0                                                         /*!< SCU SFSP3_0: MODE Position          */
+#define SCU_SFSP3_0_MODE_Msk                                  (0x07UL << SCU_SFSP3_0_MODE_Pos)                          /*!< SCU SFSP3_0: MODE Mask              */
+#define SCU_SFSP3_0_EPD_Pos                                   3                                                         /*!< SCU SFSP3_0: EPD Position           */
+#define SCU_SFSP3_0_EPD_Msk                                   (0x01UL << SCU_SFSP3_0_EPD_Pos)                           /*!< SCU SFSP3_0: EPD Mask               */
+#define SCU_SFSP3_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_0: EPUN Position          */
+#define SCU_SFSP3_0_EPUN_Msk                                  (0x01UL << SCU_SFSP3_0_EPUN_Pos)                          /*!< SCU SFSP3_0: EPUN Mask              */
+#define SCU_SFSP3_0_EHS_Pos                                   5                                                         /*!< SCU SFSP3_0: EHS Position           */
+#define SCU_SFSP3_0_EHS_Msk                                   (0x01UL << SCU_SFSP3_0_EHS_Pos)                           /*!< SCU SFSP3_0: EHS Mask               */
+#define SCU_SFSP3_0_EZI_Pos                                   6                                                         /*!< SCU SFSP3_0: EZI Position           */
+#define SCU_SFSP3_0_EZI_Msk                                   (0x01UL << SCU_SFSP3_0_EZI_Pos)                           /*!< SCU SFSP3_0: EZI Mask               */
+#define SCU_SFSP3_0_EHD_Pos                                   8                                                         /*!< SCU SFSP3_0: EHD Position           */
+#define SCU_SFSP3_0_EHD_Msk                                   (0x03UL << SCU_SFSP3_0_EHD_Pos)                           /*!< SCU SFSP3_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_1  ------------------------------------------
+#define SCU_SFSP3_1_MODE_Pos                                  0                                                         /*!< SCU SFSP3_1: MODE Position          */
+#define SCU_SFSP3_1_MODE_Msk                                  (0x07UL << SCU_SFSP3_1_MODE_Pos)                          /*!< SCU SFSP3_1: MODE Mask              */
+#define SCU_SFSP3_1_EPD_Pos                                   3                                                         /*!< SCU SFSP3_1: EPD Position           */
+#define SCU_SFSP3_1_EPD_Msk                                   (0x01UL << SCU_SFSP3_1_EPD_Pos)                           /*!< SCU SFSP3_1: EPD Mask               */
+#define SCU_SFSP3_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_1: EPUN Position          */
+#define SCU_SFSP3_1_EPUN_Msk                                  (0x01UL << SCU_SFSP3_1_EPUN_Pos)                          /*!< SCU SFSP3_1: EPUN Mask              */
+#define SCU_SFSP3_1_EHS_Pos                                   5                                                         /*!< SCU SFSP3_1: EHS Position           */
+#define SCU_SFSP3_1_EHS_Msk                                   (0x01UL << SCU_SFSP3_1_EHS_Pos)                           /*!< SCU SFSP3_1: EHS Mask               */
+#define SCU_SFSP3_1_EZI_Pos                                   6                                                         /*!< SCU SFSP3_1: EZI Position           */
+#define SCU_SFSP3_1_EZI_Msk                                   (0x01UL << SCU_SFSP3_1_EZI_Pos)                           /*!< SCU SFSP3_1: EZI Mask               */
+#define SCU_SFSP3_1_EHD_Pos                                   8                                                         /*!< SCU SFSP3_1: EHD Position           */
+#define SCU_SFSP3_1_EHD_Msk                                   (0x03UL << SCU_SFSP3_1_EHD_Pos)                           /*!< SCU SFSP3_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_2  ------------------------------------------
+#define SCU_SFSP3_2_MODE_Pos                                  0                                                         /*!< SCU SFSP3_2: MODE Position          */
+#define SCU_SFSP3_2_MODE_Msk                                  (0x07UL << SCU_SFSP3_2_MODE_Pos)                          /*!< SCU SFSP3_2: MODE Mask              */
+#define SCU_SFSP3_2_EPD_Pos                                   3                                                         /*!< SCU SFSP3_2: EPD Position           */
+#define SCU_SFSP3_2_EPD_Msk                                   (0x01UL << SCU_SFSP3_2_EPD_Pos)                           /*!< SCU SFSP3_2: EPD Mask               */
+#define SCU_SFSP3_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_2: EPUN Position          */
+#define SCU_SFSP3_2_EPUN_Msk                                  (0x01UL << SCU_SFSP3_2_EPUN_Pos)                          /*!< SCU SFSP3_2: EPUN Mask              */
+#define SCU_SFSP3_2_EHS_Pos                                   5                                                         /*!< SCU SFSP3_2: EHS Position           */
+#define SCU_SFSP3_2_EHS_Msk                                   (0x01UL << SCU_SFSP3_2_EHS_Pos)                           /*!< SCU SFSP3_2: EHS Mask               */
+#define SCU_SFSP3_2_EZI_Pos                                   6                                                         /*!< SCU SFSP3_2: EZI Position           */
+#define SCU_SFSP3_2_EZI_Msk                                   (0x01UL << SCU_SFSP3_2_EZI_Pos)                           /*!< SCU SFSP3_2: EZI Mask               */
+#define SCU_SFSP3_2_EHD_Pos                                   8                                                         /*!< SCU SFSP3_2: EHD Position           */
+#define SCU_SFSP3_2_EHD_Msk                                   (0x03UL << SCU_SFSP3_2_EHD_Pos)                           /*!< SCU SFSP3_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_3  ------------------------------------------
+#define SCU_SFSP3_3_MODE_Pos                                  0                                                         /*!< SCU SFSP3_3: MODE Position          */
+#define SCU_SFSP3_3_MODE_Msk                                  (0x07UL << SCU_SFSP3_3_MODE_Pos)                          /*!< SCU SFSP3_3: MODE Mask              */
+#define SCU_SFSP3_3_EPD_Pos                                   3                                                         /*!< SCU SFSP3_3: EPD Position           */
+#define SCU_SFSP3_3_EPD_Msk                                   (0x01UL << SCU_SFSP3_3_EPD_Pos)                           /*!< SCU SFSP3_3: EPD Mask               */
+#define SCU_SFSP3_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_3: EPUN Position          */
+#define SCU_SFSP3_3_EPUN_Msk                                  (0x01UL << SCU_SFSP3_3_EPUN_Pos)                          /*!< SCU SFSP3_3: EPUN Mask              */
+#define SCU_SFSP3_3_EHS_Pos                                   5                                                         /*!< SCU SFSP3_3: EHS Position           */
+#define SCU_SFSP3_3_EHS_Msk                                   (0x01UL << SCU_SFSP3_3_EHS_Pos)                           /*!< SCU SFSP3_3: EHS Mask               */
+#define SCU_SFSP3_3_EZI_Pos                                   6                                                         /*!< SCU SFSP3_3: EZI Position           */
+#define SCU_SFSP3_3_EZI_Msk                                   (0x01UL << SCU_SFSP3_3_EZI_Pos)                           /*!< SCU SFSP3_3: EZI Mask               */
+#define SCU_SFSP3_3_EHD_Pos                                   8                                                         /*!< SCU SFSP3_3: EHD Position           */
+#define SCU_SFSP3_3_EHD_Msk                                   (0x03UL << SCU_SFSP3_3_EHD_Pos)                           /*!< SCU SFSP3_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_4  ------------------------------------------
+#define SCU_SFSP3_4_MODE_Pos                                  0                                                         /*!< SCU SFSP3_4: MODE Position          */
+#define SCU_SFSP3_4_MODE_Msk                                  (0x07UL << SCU_SFSP3_4_MODE_Pos)                          /*!< SCU SFSP3_4: MODE Mask              */
+#define SCU_SFSP3_4_EPD_Pos                                   3                                                         /*!< SCU SFSP3_4: EPD Position           */
+#define SCU_SFSP3_4_EPD_Msk                                   (0x01UL << SCU_SFSP3_4_EPD_Pos)                           /*!< SCU SFSP3_4: EPD Mask               */
+#define SCU_SFSP3_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_4: EPUN Position          */
+#define SCU_SFSP3_4_EPUN_Msk                                  (0x01UL << SCU_SFSP3_4_EPUN_Pos)                          /*!< SCU SFSP3_4: EPUN Mask              */
+#define SCU_SFSP3_4_EHS_Pos                                   5                                                         /*!< SCU SFSP3_4: EHS Position           */
+#define SCU_SFSP3_4_EHS_Msk                                   (0x01UL << SCU_SFSP3_4_EHS_Pos)                           /*!< SCU SFSP3_4: EHS Mask               */
+#define SCU_SFSP3_4_EZI_Pos                                   6                                                         /*!< SCU SFSP3_4: EZI Position           */
+#define SCU_SFSP3_4_EZI_Msk                                   (0x01UL << SCU_SFSP3_4_EZI_Pos)                           /*!< SCU SFSP3_4: EZI Mask               */
+#define SCU_SFSP3_4_EHD_Pos                                   8                                                         /*!< SCU SFSP3_4: EHD Position           */
+#define SCU_SFSP3_4_EHD_Msk                                   (0x03UL << SCU_SFSP3_4_EHD_Pos)                           /*!< SCU SFSP3_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_5  ------------------------------------------
+#define SCU_SFSP3_5_MODE_Pos                                  0                                                         /*!< SCU SFSP3_5: MODE Position          */
+#define SCU_SFSP3_5_MODE_Msk                                  (0x07UL << SCU_SFSP3_5_MODE_Pos)                          /*!< SCU SFSP3_5: MODE Mask              */
+#define SCU_SFSP3_5_EPD_Pos                                   3                                                         /*!< SCU SFSP3_5: EPD Position           */
+#define SCU_SFSP3_5_EPD_Msk                                   (0x01UL << SCU_SFSP3_5_EPD_Pos)                           /*!< SCU SFSP3_5: EPD Mask               */
+#define SCU_SFSP3_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_5: EPUN Position          */
+#define SCU_SFSP3_5_EPUN_Msk                                  (0x01UL << SCU_SFSP3_5_EPUN_Pos)                          /*!< SCU SFSP3_5: EPUN Mask              */
+#define SCU_SFSP3_5_EHS_Pos                                   5                                                         /*!< SCU SFSP3_5: EHS Position           */
+#define SCU_SFSP3_5_EHS_Msk                                   (0x01UL << SCU_SFSP3_5_EHS_Pos)                           /*!< SCU SFSP3_5: EHS Mask               */
+#define SCU_SFSP3_5_EZI_Pos                                   6                                                         /*!< SCU SFSP3_5: EZI Position           */
+#define SCU_SFSP3_5_EZI_Msk                                   (0x01UL << SCU_SFSP3_5_EZI_Pos)                           /*!< SCU SFSP3_5: EZI Mask               */
+#define SCU_SFSP3_5_EHD_Pos                                   8                                                         /*!< SCU SFSP3_5: EHD Position           */
+#define SCU_SFSP3_5_EHD_Msk                                   (0x03UL << SCU_SFSP3_5_EHD_Pos)                           /*!< SCU SFSP3_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_6  ------------------------------------------
+#define SCU_SFSP3_6_MODE_Pos                                  0                                                         /*!< SCU SFSP3_6: MODE Position          */
+#define SCU_SFSP3_6_MODE_Msk                                  (0x07UL << SCU_SFSP3_6_MODE_Pos)                          /*!< SCU SFSP3_6: MODE Mask              */
+#define SCU_SFSP3_6_EPD_Pos                                   3                                                         /*!< SCU SFSP3_6: EPD Position           */
+#define SCU_SFSP3_6_EPD_Msk                                   (0x01UL << SCU_SFSP3_6_EPD_Pos)                           /*!< SCU SFSP3_6: EPD Mask               */
+#define SCU_SFSP3_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_6: EPUN Position          */
+#define SCU_SFSP3_6_EPUN_Msk                                  (0x01UL << SCU_SFSP3_6_EPUN_Pos)                          /*!< SCU SFSP3_6: EPUN Mask              */
+#define SCU_SFSP3_6_EHS_Pos                                   5                                                         /*!< SCU SFSP3_6: EHS Position           */
+#define SCU_SFSP3_6_EHS_Msk                                   (0x01UL << SCU_SFSP3_6_EHS_Pos)                           /*!< SCU SFSP3_6: EHS Mask               */
+#define SCU_SFSP3_6_EZI_Pos                                   6                                                         /*!< SCU SFSP3_6: EZI Position           */
+#define SCU_SFSP3_6_EZI_Msk                                   (0x01UL << SCU_SFSP3_6_EZI_Pos)                           /*!< SCU SFSP3_6: EZI Mask               */
+#define SCU_SFSP3_6_EHD_Pos                                   8                                                         /*!< SCU SFSP3_6: EHD Position           */
+#define SCU_SFSP3_6_EHD_Msk                                   (0x03UL << SCU_SFSP3_6_EHD_Pos)                           /*!< SCU SFSP3_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_7  ------------------------------------------
+#define SCU_SFSP3_7_MODE_Pos                                  0                                                         /*!< SCU SFSP3_7: MODE Position          */
+#define SCU_SFSP3_7_MODE_Msk                                  (0x07UL << SCU_SFSP3_7_MODE_Pos)                          /*!< SCU SFSP3_7: MODE Mask              */
+#define SCU_SFSP3_7_EPD_Pos                                   3                                                         /*!< SCU SFSP3_7: EPD Position           */
+#define SCU_SFSP3_7_EPD_Msk                                   (0x01UL << SCU_SFSP3_7_EPD_Pos)                           /*!< SCU SFSP3_7: EPD Mask               */
+#define SCU_SFSP3_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_7: EPUN Position          */
+#define SCU_SFSP3_7_EPUN_Msk                                  (0x01UL << SCU_SFSP3_7_EPUN_Pos)                          /*!< SCU SFSP3_7: EPUN Mask              */
+#define SCU_SFSP3_7_EHS_Pos                                   5                                                         /*!< SCU SFSP3_7: EHS Position           */
+#define SCU_SFSP3_7_EHS_Msk                                   (0x01UL << SCU_SFSP3_7_EHS_Pos)                           /*!< SCU SFSP3_7: EHS Mask               */
+#define SCU_SFSP3_7_EZI_Pos                                   6                                                         /*!< SCU SFSP3_7: EZI Position           */
+#define SCU_SFSP3_7_EZI_Msk                                   (0x01UL << SCU_SFSP3_7_EZI_Pos)                           /*!< SCU SFSP3_7: EZI Mask               */
+#define SCU_SFSP3_7_EHD_Pos                                   8                                                         /*!< SCU SFSP3_7: EHD Position           */
+#define SCU_SFSP3_7_EHD_Msk                                   (0x03UL << SCU_SFSP3_7_EHD_Pos)                           /*!< SCU SFSP3_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_8  ------------------------------------------
+#define SCU_SFSP3_8_MODE_Pos                                  0                                                         /*!< SCU SFSP3_8: MODE Position          */
+#define SCU_SFSP3_8_MODE_Msk                                  (0x07UL << SCU_SFSP3_8_MODE_Pos)                          /*!< SCU SFSP3_8: MODE Mask              */
+#define SCU_SFSP3_8_EPD_Pos                                   3                                                         /*!< SCU SFSP3_8: EPD Position           */
+#define SCU_SFSP3_8_EPD_Msk                                   (0x01UL << SCU_SFSP3_8_EPD_Pos)                           /*!< SCU SFSP3_8: EPD Mask               */
+#define SCU_SFSP3_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_8: EPUN Position          */
+#define SCU_SFSP3_8_EPUN_Msk                                  (0x01UL << SCU_SFSP3_8_EPUN_Pos)                          /*!< SCU SFSP3_8: EPUN Mask              */
+#define SCU_SFSP3_8_EHS_Pos                                   5                                                         /*!< SCU SFSP3_8: EHS Position           */
+#define SCU_SFSP3_8_EHS_Msk                                   (0x01UL << SCU_SFSP3_8_EHS_Pos)                           /*!< SCU SFSP3_8: EHS Mask               */
+#define SCU_SFSP3_8_EZI_Pos                                   6                                                         /*!< SCU SFSP3_8: EZI Position           */
+#define SCU_SFSP3_8_EZI_Msk                                   (0x01UL << SCU_SFSP3_8_EZI_Pos)                           /*!< SCU SFSP3_8: EZI Mask               */
+#define SCU_SFSP3_8_EHD_Pos                                   8                                                         /*!< SCU SFSP3_8: EHD Position           */
+#define SCU_SFSP3_8_EHD_Msk                                   (0x03UL << SCU_SFSP3_8_EHD_Pos)                           /*!< SCU SFSP3_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_0  ------------------------------------------
+#define SCU_SFSP4_0_MODE_Pos                                  0                                                         /*!< SCU SFSP4_0: MODE Position          */
+#define SCU_SFSP4_0_MODE_Msk                                  (0x07UL << SCU_SFSP4_0_MODE_Pos)                          /*!< SCU SFSP4_0: MODE Mask              */
+#define SCU_SFSP4_0_EPD_Pos                                   3                                                         /*!< SCU SFSP4_0: EPD Position           */
+#define SCU_SFSP4_0_EPD_Msk                                   (0x01UL << SCU_SFSP4_0_EPD_Pos)                           /*!< SCU SFSP4_0: EPD Mask               */
+#define SCU_SFSP4_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_0: EPUN Position          */
+#define SCU_SFSP4_0_EPUN_Msk                                  (0x01UL << SCU_SFSP4_0_EPUN_Pos)                          /*!< SCU SFSP4_0: EPUN Mask              */
+#define SCU_SFSP4_0_EHS_Pos                                   5                                                         /*!< SCU SFSP4_0: EHS Position           */
+#define SCU_SFSP4_0_EHS_Msk                                   (0x01UL << SCU_SFSP4_0_EHS_Pos)                           /*!< SCU SFSP4_0: EHS Mask               */
+#define SCU_SFSP4_0_EZI_Pos                                   6                                                         /*!< SCU SFSP4_0: EZI Position           */
+#define SCU_SFSP4_0_EZI_Msk                                   (0x01UL << SCU_SFSP4_0_EZI_Pos)                           /*!< SCU SFSP4_0: EZI Mask               */
+#define SCU_SFSP4_0_EHD_Pos                                   8                                                         /*!< SCU SFSP4_0: EHD Position           */
+#define SCU_SFSP4_0_EHD_Msk                                   (0x03UL << SCU_SFSP4_0_EHD_Pos)                           /*!< SCU SFSP4_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_1  ------------------------------------------
+#define SCU_SFSP4_1_MODE_Pos                                  0                                                         /*!< SCU SFSP4_1: MODE Position          */
+#define SCU_SFSP4_1_MODE_Msk                                  (0x07UL << SCU_SFSP4_1_MODE_Pos)                          /*!< SCU SFSP4_1: MODE Mask              */
+#define SCU_SFSP4_1_EPD_Pos                                   3                                                         /*!< SCU SFSP4_1: EPD Position           */
+#define SCU_SFSP4_1_EPD_Msk                                   (0x01UL << SCU_SFSP4_1_EPD_Pos)                           /*!< SCU SFSP4_1: EPD Mask               */
+#define SCU_SFSP4_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_1: EPUN Position          */
+#define SCU_SFSP4_1_EPUN_Msk                                  (0x01UL << SCU_SFSP4_1_EPUN_Pos)                          /*!< SCU SFSP4_1: EPUN Mask              */
+#define SCU_SFSP4_1_EHS_Pos                                   5                                                         /*!< SCU SFSP4_1: EHS Position           */
+#define SCU_SFSP4_1_EHS_Msk                                   (0x01UL << SCU_SFSP4_1_EHS_Pos)                           /*!< SCU SFSP4_1: EHS Mask               */
+#define SCU_SFSP4_1_EZI_Pos                                   6                                                         /*!< SCU SFSP4_1: EZI Position           */
+#define SCU_SFSP4_1_EZI_Msk                                   (0x01UL << SCU_SFSP4_1_EZI_Pos)                           /*!< SCU SFSP4_1: EZI Mask               */
+#define SCU_SFSP4_1_EHD_Pos                                   8                                                         /*!< SCU SFSP4_1: EHD Position           */
+#define SCU_SFSP4_1_EHD_Msk                                   (0x03UL << SCU_SFSP4_1_EHD_Pos)                           /*!< SCU SFSP4_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_2  ------------------------------------------
+#define SCU_SFSP4_2_MODE_Pos                                  0                                                         /*!< SCU SFSP4_2: MODE Position          */
+#define SCU_SFSP4_2_MODE_Msk                                  (0x07UL << SCU_SFSP4_2_MODE_Pos)                          /*!< SCU SFSP4_2: MODE Mask              */
+#define SCU_SFSP4_2_EPD_Pos                                   3                                                         /*!< SCU SFSP4_2: EPD Position           */
+#define SCU_SFSP4_2_EPD_Msk                                   (0x01UL << SCU_SFSP4_2_EPD_Pos)                           /*!< SCU SFSP4_2: EPD Mask               */
+#define SCU_SFSP4_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_2: EPUN Position          */
+#define SCU_SFSP4_2_EPUN_Msk                                  (0x01UL << SCU_SFSP4_2_EPUN_Pos)                          /*!< SCU SFSP4_2: EPUN Mask              */
+#define SCU_SFSP4_2_EHS_Pos                                   5                                                         /*!< SCU SFSP4_2: EHS Position           */
+#define SCU_SFSP4_2_EHS_Msk                                   (0x01UL << SCU_SFSP4_2_EHS_Pos)                           /*!< SCU SFSP4_2: EHS Mask               */
+#define SCU_SFSP4_2_EZI_Pos                                   6                                                         /*!< SCU SFSP4_2: EZI Position           */
+#define SCU_SFSP4_2_EZI_Msk                                   (0x01UL << SCU_SFSP4_2_EZI_Pos)                           /*!< SCU SFSP4_2: EZI Mask               */
+#define SCU_SFSP4_2_EHD_Pos                                   8                                                         /*!< SCU SFSP4_2: EHD Position           */
+#define SCU_SFSP4_2_EHD_Msk                                   (0x03UL << SCU_SFSP4_2_EHD_Pos)                           /*!< SCU SFSP4_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_3  ------------------------------------------
+#define SCU_SFSP4_3_MODE_Pos                                  0                                                         /*!< SCU SFSP4_3: MODE Position          */
+#define SCU_SFSP4_3_MODE_Msk                                  (0x07UL << SCU_SFSP4_3_MODE_Pos)                          /*!< SCU SFSP4_3: MODE Mask              */
+#define SCU_SFSP4_3_EPD_Pos                                   3                                                         /*!< SCU SFSP4_3: EPD Position           */
+#define SCU_SFSP4_3_EPD_Msk                                   (0x01UL << SCU_SFSP4_3_EPD_Pos)                           /*!< SCU SFSP4_3: EPD Mask               */
+#define SCU_SFSP4_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_3: EPUN Position          */
+#define SCU_SFSP4_3_EPUN_Msk                                  (0x01UL << SCU_SFSP4_3_EPUN_Pos)                          /*!< SCU SFSP4_3: EPUN Mask              */
+#define SCU_SFSP4_3_EHS_Pos                                   5                                                         /*!< SCU SFSP4_3: EHS Position           */
+#define SCU_SFSP4_3_EHS_Msk                                   (0x01UL << SCU_SFSP4_3_EHS_Pos)                           /*!< SCU SFSP4_3: EHS Mask               */
+#define SCU_SFSP4_3_EZI_Pos                                   6                                                         /*!< SCU SFSP4_3: EZI Position           */
+#define SCU_SFSP4_3_EZI_Msk                                   (0x01UL << SCU_SFSP4_3_EZI_Pos)                           /*!< SCU SFSP4_3: EZI Mask               */
+#define SCU_SFSP4_3_EHD_Pos                                   8                                                         /*!< SCU SFSP4_3: EHD Position           */
+#define SCU_SFSP4_3_EHD_Msk                                   (0x03UL << SCU_SFSP4_3_EHD_Pos)                           /*!< SCU SFSP4_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_4  ------------------------------------------
+#define SCU_SFSP4_4_MODE_Pos                                  0                                                         /*!< SCU SFSP4_4: MODE Position          */
+#define SCU_SFSP4_4_MODE_Msk                                  (0x07UL << SCU_SFSP4_4_MODE_Pos)                          /*!< SCU SFSP4_4: MODE Mask              */
+#define SCU_SFSP4_4_EPD_Pos                                   3                                                         /*!< SCU SFSP4_4: EPD Position           */
+#define SCU_SFSP4_4_EPD_Msk                                   (0x01UL << SCU_SFSP4_4_EPD_Pos)                           /*!< SCU SFSP4_4: EPD Mask               */
+#define SCU_SFSP4_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_4: EPUN Position          */
+#define SCU_SFSP4_4_EPUN_Msk                                  (0x01UL << SCU_SFSP4_4_EPUN_Pos)                          /*!< SCU SFSP4_4: EPUN Mask              */
+#define SCU_SFSP4_4_EHS_Pos                                   5                                                         /*!< SCU SFSP4_4: EHS Position           */
+#define SCU_SFSP4_4_EHS_Msk                                   (0x01UL << SCU_SFSP4_4_EHS_Pos)                           /*!< SCU SFSP4_4: EHS Mask               */
+#define SCU_SFSP4_4_EZI_Pos                                   6                                                         /*!< SCU SFSP4_4: EZI Position           */
+#define SCU_SFSP4_4_EZI_Msk                                   (0x01UL << SCU_SFSP4_4_EZI_Pos)                           /*!< SCU SFSP4_4: EZI Mask               */
+#define SCU_SFSP4_4_EHD_Pos                                   8                                                         /*!< SCU SFSP4_4: EHD Position           */
+#define SCU_SFSP4_4_EHD_Msk                                   (0x03UL << SCU_SFSP4_4_EHD_Pos)                           /*!< SCU SFSP4_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_5  ------------------------------------------
+#define SCU_SFSP4_5_MODE_Pos                                  0                                                         /*!< SCU SFSP4_5: MODE Position          */
+#define SCU_SFSP4_5_MODE_Msk                                  (0x07UL << SCU_SFSP4_5_MODE_Pos)                          /*!< SCU SFSP4_5: MODE Mask              */
+#define SCU_SFSP4_5_EPD_Pos                                   3                                                         /*!< SCU SFSP4_5: EPD Position           */
+#define SCU_SFSP4_5_EPD_Msk                                   (0x01UL << SCU_SFSP4_5_EPD_Pos)                           /*!< SCU SFSP4_5: EPD Mask               */
+#define SCU_SFSP4_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_5: EPUN Position          */
+#define SCU_SFSP4_5_EPUN_Msk                                  (0x01UL << SCU_SFSP4_5_EPUN_Pos)                          /*!< SCU SFSP4_5: EPUN Mask              */
+#define SCU_SFSP4_5_EHS_Pos                                   5                                                         /*!< SCU SFSP4_5: EHS Position           */
+#define SCU_SFSP4_5_EHS_Msk                                   (0x01UL << SCU_SFSP4_5_EHS_Pos)                           /*!< SCU SFSP4_5: EHS Mask               */
+#define SCU_SFSP4_5_EZI_Pos                                   6                                                         /*!< SCU SFSP4_5: EZI Position           */
+#define SCU_SFSP4_5_EZI_Msk                                   (0x01UL << SCU_SFSP4_5_EZI_Pos)                           /*!< SCU SFSP4_5: EZI Mask               */
+#define SCU_SFSP4_5_EHD_Pos                                   8                                                         /*!< SCU SFSP4_5: EHD Position           */
+#define SCU_SFSP4_5_EHD_Msk                                   (0x03UL << SCU_SFSP4_5_EHD_Pos)                           /*!< SCU SFSP4_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_6  ------------------------------------------
+#define SCU_SFSP4_6_MODE_Pos                                  0                                                         /*!< SCU SFSP4_6: MODE Position          */
+#define SCU_SFSP4_6_MODE_Msk                                  (0x07UL << SCU_SFSP4_6_MODE_Pos)                          /*!< SCU SFSP4_6: MODE Mask              */
+#define SCU_SFSP4_6_EPD_Pos                                   3                                                         /*!< SCU SFSP4_6: EPD Position           */
+#define SCU_SFSP4_6_EPD_Msk                                   (0x01UL << SCU_SFSP4_6_EPD_Pos)                           /*!< SCU SFSP4_6: EPD Mask               */
+#define SCU_SFSP4_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_6: EPUN Position          */
+#define SCU_SFSP4_6_EPUN_Msk                                  (0x01UL << SCU_SFSP4_6_EPUN_Pos)                          /*!< SCU SFSP4_6: EPUN Mask              */
+#define SCU_SFSP4_6_EHS_Pos                                   5                                                         /*!< SCU SFSP4_6: EHS Position           */
+#define SCU_SFSP4_6_EHS_Msk                                   (0x01UL << SCU_SFSP4_6_EHS_Pos)                           /*!< SCU SFSP4_6: EHS Mask               */
+#define SCU_SFSP4_6_EZI_Pos                                   6                                                         /*!< SCU SFSP4_6: EZI Position           */
+#define SCU_SFSP4_6_EZI_Msk                                   (0x01UL << SCU_SFSP4_6_EZI_Pos)                           /*!< SCU SFSP4_6: EZI Mask               */
+#define SCU_SFSP4_6_EHD_Pos                                   8                                                         /*!< SCU SFSP4_6: EHD Position           */
+#define SCU_SFSP4_6_EHD_Msk                                   (0x03UL << SCU_SFSP4_6_EHD_Pos)                           /*!< SCU SFSP4_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_7  ------------------------------------------
+#define SCU_SFSP4_7_MODE_Pos                                  0                                                         /*!< SCU SFSP4_7: MODE Position          */
+#define SCU_SFSP4_7_MODE_Msk                                  (0x07UL << SCU_SFSP4_7_MODE_Pos)                          /*!< SCU SFSP4_7: MODE Mask              */
+#define SCU_SFSP4_7_EPD_Pos                                   3                                                         /*!< SCU SFSP4_7: EPD Position           */
+#define SCU_SFSP4_7_EPD_Msk                                   (0x01UL << SCU_SFSP4_7_EPD_Pos)                           /*!< SCU SFSP4_7: EPD Mask               */
+#define SCU_SFSP4_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_7: EPUN Position          */
+#define SCU_SFSP4_7_EPUN_Msk                                  (0x01UL << SCU_SFSP4_7_EPUN_Pos)                          /*!< SCU SFSP4_7: EPUN Mask              */
+#define SCU_SFSP4_7_EHS_Pos                                   5                                                         /*!< SCU SFSP4_7: EHS Position           */
+#define SCU_SFSP4_7_EHS_Msk                                   (0x01UL << SCU_SFSP4_7_EHS_Pos)                           /*!< SCU SFSP4_7: EHS Mask               */
+#define SCU_SFSP4_7_EZI_Pos                                   6                                                         /*!< SCU SFSP4_7: EZI Position           */
+#define SCU_SFSP4_7_EZI_Msk                                   (0x01UL << SCU_SFSP4_7_EZI_Pos)                           /*!< SCU SFSP4_7: EZI Mask               */
+#define SCU_SFSP4_7_EHD_Pos                                   8                                                         /*!< SCU SFSP4_7: EHD Position           */
+#define SCU_SFSP4_7_EHD_Msk                                   (0x03UL << SCU_SFSP4_7_EHD_Pos)                           /*!< SCU SFSP4_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_8  ------------------------------------------
+#define SCU_SFSP4_8_MODE_Pos                                  0                                                         /*!< SCU SFSP4_8: MODE Position          */
+#define SCU_SFSP4_8_MODE_Msk                                  (0x07UL << SCU_SFSP4_8_MODE_Pos)                          /*!< SCU SFSP4_8: MODE Mask              */
+#define SCU_SFSP4_8_EPD_Pos                                   3                                                         /*!< SCU SFSP4_8: EPD Position           */
+#define SCU_SFSP4_8_EPD_Msk                                   (0x01UL << SCU_SFSP4_8_EPD_Pos)                           /*!< SCU SFSP4_8: EPD Mask               */
+#define SCU_SFSP4_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_8: EPUN Position          */
+#define SCU_SFSP4_8_EPUN_Msk                                  (0x01UL << SCU_SFSP4_8_EPUN_Pos)                          /*!< SCU SFSP4_8: EPUN Mask              */
+#define SCU_SFSP4_8_EHS_Pos                                   5                                                         /*!< SCU SFSP4_8: EHS Position           */
+#define SCU_SFSP4_8_EHS_Msk                                   (0x01UL << SCU_SFSP4_8_EHS_Pos)                           /*!< SCU SFSP4_8: EHS Mask               */
+#define SCU_SFSP4_8_EZI_Pos                                   6                                                         /*!< SCU SFSP4_8: EZI Position           */
+#define SCU_SFSP4_8_EZI_Msk                                   (0x01UL << SCU_SFSP4_8_EZI_Pos)                           /*!< SCU SFSP4_8: EZI Mask               */
+#define SCU_SFSP4_8_EHD_Pos                                   8                                                         /*!< SCU SFSP4_8: EHD Position           */
+#define SCU_SFSP4_8_EHD_Msk                                   (0x03UL << SCU_SFSP4_8_EHD_Pos)                           /*!< SCU SFSP4_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_9  ------------------------------------------
+#define SCU_SFSP4_9_MODE_Pos                                  0                                                         /*!< SCU SFSP4_9: MODE Position          */
+#define SCU_SFSP4_9_MODE_Msk                                  (0x07UL << SCU_SFSP4_9_MODE_Pos)                          /*!< SCU SFSP4_9: MODE Mask              */
+#define SCU_SFSP4_9_EPD_Pos                                   3                                                         /*!< SCU SFSP4_9: EPD Position           */
+#define SCU_SFSP4_9_EPD_Msk                                   (0x01UL << SCU_SFSP4_9_EPD_Pos)                           /*!< SCU SFSP4_9: EPD Mask               */
+#define SCU_SFSP4_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_9: EPUN Position          */
+#define SCU_SFSP4_9_EPUN_Msk                                  (0x01UL << SCU_SFSP4_9_EPUN_Pos)                          /*!< SCU SFSP4_9: EPUN Mask              */
+#define SCU_SFSP4_9_EHS_Pos                                   5                                                         /*!< SCU SFSP4_9: EHS Position           */
+#define SCU_SFSP4_9_EHS_Msk                                   (0x01UL << SCU_SFSP4_9_EHS_Pos)                           /*!< SCU SFSP4_9: EHS Mask               */
+#define SCU_SFSP4_9_EZI_Pos                                   6                                                         /*!< SCU SFSP4_9: EZI Position           */
+#define SCU_SFSP4_9_EZI_Msk                                   (0x01UL << SCU_SFSP4_9_EZI_Pos)                           /*!< SCU SFSP4_9: EZI Mask               */
+#define SCU_SFSP4_9_EHD_Pos                                   8                                                         /*!< SCU SFSP4_9: EHD Position           */
+#define SCU_SFSP4_9_EHD_Msk                                   (0x03UL << SCU_SFSP4_9_EHD_Pos)                           /*!< SCU SFSP4_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP4_10  ------------------------------------------
+#define SCU_SFSP4_10_MODE_Pos                                 0                                                         /*!< SCU SFSP4_10: MODE Position         */
+#define SCU_SFSP4_10_MODE_Msk                                 (0x07UL << SCU_SFSP4_10_MODE_Pos)                         /*!< SCU SFSP4_10: MODE Mask             */
+#define SCU_SFSP4_10_EPD_Pos                                  3                                                         /*!< SCU SFSP4_10: EPD Position          */
+#define SCU_SFSP4_10_EPD_Msk                                  (0x01UL << SCU_SFSP4_10_EPD_Pos)                          /*!< SCU SFSP4_10: EPD Mask              */
+#define SCU_SFSP4_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP4_10: EPUN Position         */
+#define SCU_SFSP4_10_EPUN_Msk                                 (0x01UL << SCU_SFSP4_10_EPUN_Pos)                         /*!< SCU SFSP4_10: EPUN Mask             */
+#define SCU_SFSP4_10_EHS_Pos                                  5                                                         /*!< SCU SFSP4_10: EHS Position          */
+#define SCU_SFSP4_10_EHS_Msk                                  (0x01UL << SCU_SFSP4_10_EHS_Pos)                          /*!< SCU SFSP4_10: EHS Mask              */
+#define SCU_SFSP4_10_EZI_Pos                                  6                                                         /*!< SCU SFSP4_10: EZI Position          */
+#define SCU_SFSP4_10_EZI_Msk                                  (0x01UL << SCU_SFSP4_10_EZI_Pos)                          /*!< SCU SFSP4_10: EZI Mask              */
+#define SCU_SFSP4_10_EHD_Pos                                  8                                                         /*!< SCU SFSP4_10: EHD Position          */
+#define SCU_SFSP4_10_EHD_Msk                                  (0x03UL << SCU_SFSP4_10_EHD_Pos)                          /*!< SCU SFSP4_10: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP5_0  ------------------------------------------
+#define SCU_SFSP5_0_MODE_Pos                                  0                                                         /*!< SCU SFSP5_0: MODE Position          */
+#define SCU_SFSP5_0_MODE_Msk                                  (0x07UL << SCU_SFSP5_0_MODE_Pos)                          /*!< SCU SFSP5_0: MODE Mask              */
+#define SCU_SFSP5_0_EPD_Pos                                   3                                                         /*!< SCU SFSP5_0: EPD Position           */
+#define SCU_SFSP5_0_EPD_Msk                                   (0x01UL << SCU_SFSP5_0_EPD_Pos)                           /*!< SCU SFSP5_0: EPD Mask               */
+#define SCU_SFSP5_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_0: EPUN Position          */
+#define SCU_SFSP5_0_EPUN_Msk                                  (0x01UL << SCU_SFSP5_0_EPUN_Pos)                          /*!< SCU SFSP5_0: EPUN Mask              */
+#define SCU_SFSP5_0_EHS_Pos                                   5                                                         /*!< SCU SFSP5_0: EHS Position           */
+#define SCU_SFSP5_0_EHS_Msk                                   (0x01UL << SCU_SFSP5_0_EHS_Pos)                           /*!< SCU SFSP5_0: EHS Mask               */
+#define SCU_SFSP5_0_EZI_Pos                                   6                                                         /*!< SCU SFSP5_0: EZI Position           */
+#define SCU_SFSP5_0_EZI_Msk                                   (0x01UL << SCU_SFSP5_0_EZI_Pos)                           /*!< SCU SFSP5_0: EZI Mask               */
+#define SCU_SFSP5_0_EHD_Pos                                   8                                                         /*!< SCU SFSP5_0: EHD Position           */
+#define SCU_SFSP5_0_EHD_Msk                                   (0x03UL << SCU_SFSP5_0_EHD_Pos)                           /*!< SCU SFSP5_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_1  ------------------------------------------
+#define SCU_SFSP5_1_MODE_Pos                                  0                                                         /*!< SCU SFSP5_1: MODE Position          */
+#define SCU_SFSP5_1_MODE_Msk                                  (0x07UL << SCU_SFSP5_1_MODE_Pos)                          /*!< SCU SFSP5_1: MODE Mask              */
+#define SCU_SFSP5_1_EPD_Pos                                   3                                                         /*!< SCU SFSP5_1: EPD Position           */
+#define SCU_SFSP5_1_EPD_Msk                                   (0x01UL << SCU_SFSP5_1_EPD_Pos)                           /*!< SCU SFSP5_1: EPD Mask               */
+#define SCU_SFSP5_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_1: EPUN Position          */
+#define SCU_SFSP5_1_EPUN_Msk                                  (0x01UL << SCU_SFSP5_1_EPUN_Pos)                          /*!< SCU SFSP5_1: EPUN Mask              */
+#define SCU_SFSP5_1_EHS_Pos                                   5                                                         /*!< SCU SFSP5_1: EHS Position           */
+#define SCU_SFSP5_1_EHS_Msk                                   (0x01UL << SCU_SFSP5_1_EHS_Pos)                           /*!< SCU SFSP5_1: EHS Mask               */
+#define SCU_SFSP5_1_EZI_Pos                                   6                                                         /*!< SCU SFSP5_1: EZI Position           */
+#define SCU_SFSP5_1_EZI_Msk                                   (0x01UL << SCU_SFSP5_1_EZI_Pos)                           /*!< SCU SFSP5_1: EZI Mask               */
+#define SCU_SFSP5_1_EHD_Pos                                   8                                                         /*!< SCU SFSP5_1: EHD Position           */
+#define SCU_SFSP5_1_EHD_Msk                                   (0x03UL << SCU_SFSP5_1_EHD_Pos)                           /*!< SCU SFSP5_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_2  ------------------------------------------
+#define SCU_SFSP5_2_MODE_Pos                                  0                                                         /*!< SCU SFSP5_2: MODE Position          */
+#define SCU_SFSP5_2_MODE_Msk                                  (0x07UL << SCU_SFSP5_2_MODE_Pos)                          /*!< SCU SFSP5_2: MODE Mask              */
+#define SCU_SFSP5_2_EPD_Pos                                   3                                                         /*!< SCU SFSP5_2: EPD Position           */
+#define SCU_SFSP5_2_EPD_Msk                                   (0x01UL << SCU_SFSP5_2_EPD_Pos)                           /*!< SCU SFSP5_2: EPD Mask               */
+#define SCU_SFSP5_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_2: EPUN Position          */
+#define SCU_SFSP5_2_EPUN_Msk                                  (0x01UL << SCU_SFSP5_2_EPUN_Pos)                          /*!< SCU SFSP5_2: EPUN Mask              */
+#define SCU_SFSP5_2_EHS_Pos                                   5                                                         /*!< SCU SFSP5_2: EHS Position           */
+#define SCU_SFSP5_2_EHS_Msk                                   (0x01UL << SCU_SFSP5_2_EHS_Pos)                           /*!< SCU SFSP5_2: EHS Mask               */
+#define SCU_SFSP5_2_EZI_Pos                                   6                                                         /*!< SCU SFSP5_2: EZI Position           */
+#define SCU_SFSP5_2_EZI_Msk                                   (0x01UL << SCU_SFSP5_2_EZI_Pos)                           /*!< SCU SFSP5_2: EZI Mask               */
+#define SCU_SFSP5_2_EHD_Pos                                   8                                                         /*!< SCU SFSP5_2: EHD Position           */
+#define SCU_SFSP5_2_EHD_Msk                                   (0x03UL << SCU_SFSP5_2_EHD_Pos)                           /*!< SCU SFSP5_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_3  ------------------------------------------
+#define SCU_SFSP5_3_MODE_Pos                                  0                                                         /*!< SCU SFSP5_3: MODE Position          */
+#define SCU_SFSP5_3_MODE_Msk                                  (0x07UL << SCU_SFSP5_3_MODE_Pos)                          /*!< SCU SFSP5_3: MODE Mask              */
+#define SCU_SFSP5_3_EPD_Pos                                   3                                                         /*!< SCU SFSP5_3: EPD Position           */
+#define SCU_SFSP5_3_EPD_Msk                                   (0x01UL << SCU_SFSP5_3_EPD_Pos)                           /*!< SCU SFSP5_3: EPD Mask               */
+#define SCU_SFSP5_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_3: EPUN Position          */
+#define SCU_SFSP5_3_EPUN_Msk                                  (0x01UL << SCU_SFSP5_3_EPUN_Pos)                          /*!< SCU SFSP5_3: EPUN Mask              */
+#define SCU_SFSP5_3_EHS_Pos                                   5                                                         /*!< SCU SFSP5_3: EHS Position           */
+#define SCU_SFSP5_3_EHS_Msk                                   (0x01UL << SCU_SFSP5_3_EHS_Pos)                           /*!< SCU SFSP5_3: EHS Mask               */
+#define SCU_SFSP5_3_EZI_Pos                                   6                                                         /*!< SCU SFSP5_3: EZI Position           */
+#define SCU_SFSP5_3_EZI_Msk                                   (0x01UL << SCU_SFSP5_3_EZI_Pos)                           /*!< SCU SFSP5_3: EZI Mask               */
+#define SCU_SFSP5_3_EHD_Pos                                   8                                                         /*!< SCU SFSP5_3: EHD Position           */
+#define SCU_SFSP5_3_EHD_Msk                                   (0x03UL << SCU_SFSP5_3_EHD_Pos)                           /*!< SCU SFSP5_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_4  ------------------------------------------
+#define SCU_SFSP5_4_MODE_Pos                                  0                                                         /*!< SCU SFSP5_4: MODE Position          */
+#define SCU_SFSP5_4_MODE_Msk                                  (0x07UL << SCU_SFSP5_4_MODE_Pos)                          /*!< SCU SFSP5_4: MODE Mask              */
+#define SCU_SFSP5_4_EPD_Pos                                   3                                                         /*!< SCU SFSP5_4: EPD Position           */
+#define SCU_SFSP5_4_EPD_Msk                                   (0x01UL << SCU_SFSP5_4_EPD_Pos)                           /*!< SCU SFSP5_4: EPD Mask               */
+#define SCU_SFSP5_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_4: EPUN Position          */
+#define SCU_SFSP5_4_EPUN_Msk                                  (0x01UL << SCU_SFSP5_4_EPUN_Pos)                          /*!< SCU SFSP5_4: EPUN Mask              */
+#define SCU_SFSP5_4_EHS_Pos                                   5                                                         /*!< SCU SFSP5_4: EHS Position           */
+#define SCU_SFSP5_4_EHS_Msk                                   (0x01UL << SCU_SFSP5_4_EHS_Pos)                           /*!< SCU SFSP5_4: EHS Mask               */
+#define SCU_SFSP5_4_EZI_Pos                                   6                                                         /*!< SCU SFSP5_4: EZI Position           */
+#define SCU_SFSP5_4_EZI_Msk                                   (0x01UL << SCU_SFSP5_4_EZI_Pos)                           /*!< SCU SFSP5_4: EZI Mask               */
+#define SCU_SFSP5_4_EHD_Pos                                   8                                                         /*!< SCU SFSP5_4: EHD Position           */
+#define SCU_SFSP5_4_EHD_Msk                                   (0x03UL << SCU_SFSP5_4_EHD_Pos)                           /*!< SCU SFSP5_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_5  ------------------------------------------
+#define SCU_SFSP5_5_MODE_Pos                                  0                                                         /*!< SCU SFSP5_5: MODE Position          */
+#define SCU_SFSP5_5_MODE_Msk                                  (0x07UL << SCU_SFSP5_5_MODE_Pos)                          /*!< SCU SFSP5_5: MODE Mask              */
+#define SCU_SFSP5_5_EPD_Pos                                   3                                                         /*!< SCU SFSP5_5: EPD Position           */
+#define SCU_SFSP5_5_EPD_Msk                                   (0x01UL << SCU_SFSP5_5_EPD_Pos)                           /*!< SCU SFSP5_5: EPD Mask               */
+#define SCU_SFSP5_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_5: EPUN Position          */
+#define SCU_SFSP5_5_EPUN_Msk                                  (0x01UL << SCU_SFSP5_5_EPUN_Pos)                          /*!< SCU SFSP5_5: EPUN Mask              */
+#define SCU_SFSP5_5_EHS_Pos                                   5                                                         /*!< SCU SFSP5_5: EHS Position           */
+#define SCU_SFSP5_5_EHS_Msk                                   (0x01UL << SCU_SFSP5_5_EHS_Pos)                           /*!< SCU SFSP5_5: EHS Mask               */
+#define SCU_SFSP5_5_EZI_Pos                                   6                                                         /*!< SCU SFSP5_5: EZI Position           */
+#define SCU_SFSP5_5_EZI_Msk                                   (0x01UL << SCU_SFSP5_5_EZI_Pos)                           /*!< SCU SFSP5_5: EZI Mask               */
+#define SCU_SFSP5_5_EHD_Pos                                   8                                                         /*!< SCU SFSP5_5: EHD Position           */
+#define SCU_SFSP5_5_EHD_Msk                                   (0x03UL << SCU_SFSP5_5_EHD_Pos)                           /*!< SCU SFSP5_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_6  ------------------------------------------
+#define SCU_SFSP5_6_MODE_Pos                                  0                                                         /*!< SCU SFSP5_6: MODE Position          */
+#define SCU_SFSP5_6_MODE_Msk                                  (0x07UL << SCU_SFSP5_6_MODE_Pos)                          /*!< SCU SFSP5_6: MODE Mask              */
+#define SCU_SFSP5_6_EPD_Pos                                   3                                                         /*!< SCU SFSP5_6: EPD Position           */
+#define SCU_SFSP5_6_EPD_Msk                                   (0x01UL << SCU_SFSP5_6_EPD_Pos)                           /*!< SCU SFSP5_6: EPD Mask               */
+#define SCU_SFSP5_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_6: EPUN Position          */
+#define SCU_SFSP5_6_EPUN_Msk                                  (0x01UL << SCU_SFSP5_6_EPUN_Pos)                          /*!< SCU SFSP5_6: EPUN Mask              */
+#define SCU_SFSP5_6_EHS_Pos                                   5                                                         /*!< SCU SFSP5_6: EHS Position           */
+#define SCU_SFSP5_6_EHS_Msk                                   (0x01UL << SCU_SFSP5_6_EHS_Pos)                           /*!< SCU SFSP5_6: EHS Mask               */
+#define SCU_SFSP5_6_EZI_Pos                                   6                                                         /*!< SCU SFSP5_6: EZI Position           */
+#define SCU_SFSP5_6_EZI_Msk                                   (0x01UL << SCU_SFSP5_6_EZI_Pos)                           /*!< SCU SFSP5_6: EZI Mask               */
+#define SCU_SFSP5_6_EHD_Pos                                   8                                                         /*!< SCU SFSP5_6: EHD Position           */
+#define SCU_SFSP5_6_EHD_Msk                                   (0x03UL << SCU_SFSP5_6_EHD_Pos)                           /*!< SCU SFSP5_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_7  ------------------------------------------
+#define SCU_SFSP5_7_MODE_Pos                                  0                                                         /*!< SCU SFSP5_7: MODE Position          */
+#define SCU_SFSP5_7_MODE_Msk                                  (0x07UL << SCU_SFSP5_7_MODE_Pos)                          /*!< SCU SFSP5_7: MODE Mask              */
+#define SCU_SFSP5_7_EPD_Pos                                   3                                                         /*!< SCU SFSP5_7: EPD Position           */
+#define SCU_SFSP5_7_EPD_Msk                                   (0x01UL << SCU_SFSP5_7_EPD_Pos)                           /*!< SCU SFSP5_7: EPD Mask               */
+#define SCU_SFSP5_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_7: EPUN Position          */
+#define SCU_SFSP5_7_EPUN_Msk                                  (0x01UL << SCU_SFSP5_7_EPUN_Pos)                          /*!< SCU SFSP5_7: EPUN Mask              */
+#define SCU_SFSP5_7_EHS_Pos                                   5                                                         /*!< SCU SFSP5_7: EHS Position           */
+#define SCU_SFSP5_7_EHS_Msk                                   (0x01UL << SCU_SFSP5_7_EHS_Pos)                           /*!< SCU SFSP5_7: EHS Mask               */
+#define SCU_SFSP5_7_EZI_Pos                                   6                                                         /*!< SCU SFSP5_7: EZI Position           */
+#define SCU_SFSP5_7_EZI_Msk                                   (0x01UL << SCU_SFSP5_7_EZI_Pos)                           /*!< SCU SFSP5_7: EZI Mask               */
+#define SCU_SFSP5_7_EHD_Pos                                   8                                                         /*!< SCU SFSP5_7: EHD Position           */
+#define SCU_SFSP5_7_EHD_Msk                                   (0x03UL << SCU_SFSP5_7_EHD_Pos)                           /*!< SCU SFSP5_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_0  ------------------------------------------
+#define SCU_SFSP6_0_MODE_Pos                                  0                                                         /*!< SCU SFSP6_0: MODE Position          */
+#define SCU_SFSP6_0_MODE_Msk                                  (0x07UL << SCU_SFSP6_0_MODE_Pos)                          /*!< SCU SFSP6_0: MODE Mask              */
+#define SCU_SFSP6_0_EPD_Pos                                   3                                                         /*!< SCU SFSP6_0: EPD Position           */
+#define SCU_SFSP6_0_EPD_Msk                                   (0x01UL << SCU_SFSP6_0_EPD_Pos)                           /*!< SCU SFSP6_0: EPD Mask               */
+#define SCU_SFSP6_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_0: EPUN Position          */
+#define SCU_SFSP6_0_EPUN_Msk                                  (0x01UL << SCU_SFSP6_0_EPUN_Pos)                          /*!< SCU SFSP6_0: EPUN Mask              */
+#define SCU_SFSP6_0_EHS_Pos                                   5                                                         /*!< SCU SFSP6_0: EHS Position           */
+#define SCU_SFSP6_0_EHS_Msk                                   (0x01UL << SCU_SFSP6_0_EHS_Pos)                           /*!< SCU SFSP6_0: EHS Mask               */
+#define SCU_SFSP6_0_EZI_Pos                                   6                                                         /*!< SCU SFSP6_0: EZI Position           */
+#define SCU_SFSP6_0_EZI_Msk                                   (0x01UL << SCU_SFSP6_0_EZI_Pos)                           /*!< SCU SFSP6_0: EZI Mask               */
+#define SCU_SFSP6_0_EHD_Pos                                   8                                                         /*!< SCU SFSP6_0: EHD Position           */
+#define SCU_SFSP6_0_EHD_Msk                                   (0x03UL << SCU_SFSP6_0_EHD_Pos)                           /*!< SCU SFSP6_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_1  ------------------------------------------
+#define SCU_SFSP6_1_MODE_Pos                                  0                                                         /*!< SCU SFSP6_1: MODE Position          */
+#define SCU_SFSP6_1_MODE_Msk                                  (0x07UL << SCU_SFSP6_1_MODE_Pos)                          /*!< SCU SFSP6_1: MODE Mask              */
+#define SCU_SFSP6_1_EPD_Pos                                   3                                                         /*!< SCU SFSP6_1: EPD Position           */
+#define SCU_SFSP6_1_EPD_Msk                                   (0x01UL << SCU_SFSP6_1_EPD_Pos)                           /*!< SCU SFSP6_1: EPD Mask               */
+#define SCU_SFSP6_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_1: EPUN Position          */
+#define SCU_SFSP6_1_EPUN_Msk                                  (0x01UL << SCU_SFSP6_1_EPUN_Pos)                          /*!< SCU SFSP6_1: EPUN Mask              */
+#define SCU_SFSP6_1_EHS_Pos                                   5                                                         /*!< SCU SFSP6_1: EHS Position           */
+#define SCU_SFSP6_1_EHS_Msk                                   (0x01UL << SCU_SFSP6_1_EHS_Pos)                           /*!< SCU SFSP6_1: EHS Mask               */
+#define SCU_SFSP6_1_EZI_Pos                                   6                                                         /*!< SCU SFSP6_1: EZI Position           */
+#define SCU_SFSP6_1_EZI_Msk                                   (0x01UL << SCU_SFSP6_1_EZI_Pos)                           /*!< SCU SFSP6_1: EZI Mask               */
+#define SCU_SFSP6_1_EHD_Pos                                   8                                                         /*!< SCU SFSP6_1: EHD Position           */
+#define SCU_SFSP6_1_EHD_Msk                                   (0x03UL << SCU_SFSP6_1_EHD_Pos)                           /*!< SCU SFSP6_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_2  ------------------------------------------
+#define SCU_SFSP6_2_MODE_Pos                                  0                                                         /*!< SCU SFSP6_2: MODE Position          */
+#define SCU_SFSP6_2_MODE_Msk                                  (0x07UL << SCU_SFSP6_2_MODE_Pos)                          /*!< SCU SFSP6_2: MODE Mask              */
+#define SCU_SFSP6_2_EPD_Pos                                   3                                                         /*!< SCU SFSP6_2: EPD Position           */
+#define SCU_SFSP6_2_EPD_Msk                                   (0x01UL << SCU_SFSP6_2_EPD_Pos)                           /*!< SCU SFSP6_2: EPD Mask               */
+#define SCU_SFSP6_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_2: EPUN Position          */
+#define SCU_SFSP6_2_EPUN_Msk                                  (0x01UL << SCU_SFSP6_2_EPUN_Pos)                          /*!< SCU SFSP6_2: EPUN Mask              */
+#define SCU_SFSP6_2_EHS_Pos                                   5                                                         /*!< SCU SFSP6_2: EHS Position           */
+#define SCU_SFSP6_2_EHS_Msk                                   (0x01UL << SCU_SFSP6_2_EHS_Pos)                           /*!< SCU SFSP6_2: EHS Mask               */
+#define SCU_SFSP6_2_EZI_Pos                                   6                                                         /*!< SCU SFSP6_2: EZI Position           */
+#define SCU_SFSP6_2_EZI_Msk                                   (0x01UL << SCU_SFSP6_2_EZI_Pos)                           /*!< SCU SFSP6_2: EZI Mask               */
+#define SCU_SFSP6_2_EHD_Pos                                   8                                                         /*!< SCU SFSP6_2: EHD Position           */
+#define SCU_SFSP6_2_EHD_Msk                                   (0x03UL << SCU_SFSP6_2_EHD_Pos)                           /*!< SCU SFSP6_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_3  ------------------------------------------
+#define SCU_SFSP6_3_MODE_Pos                                  0                                                         /*!< SCU SFSP6_3: MODE Position          */
+#define SCU_SFSP6_3_MODE_Msk                                  (0x07UL << SCU_SFSP6_3_MODE_Pos)                          /*!< SCU SFSP6_3: MODE Mask              */
+#define SCU_SFSP6_3_EPD_Pos                                   3                                                         /*!< SCU SFSP6_3: EPD Position           */
+#define SCU_SFSP6_3_EPD_Msk                                   (0x01UL << SCU_SFSP6_3_EPD_Pos)                           /*!< SCU SFSP6_3: EPD Mask               */
+#define SCU_SFSP6_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_3: EPUN Position          */
+#define SCU_SFSP6_3_EPUN_Msk                                  (0x01UL << SCU_SFSP6_3_EPUN_Pos)                          /*!< SCU SFSP6_3: EPUN Mask              */
+#define SCU_SFSP6_3_EHS_Pos                                   5                                                         /*!< SCU SFSP6_3: EHS Position           */
+#define SCU_SFSP6_3_EHS_Msk                                   (0x01UL << SCU_SFSP6_3_EHS_Pos)                           /*!< SCU SFSP6_3: EHS Mask               */
+#define SCU_SFSP6_3_EZI_Pos                                   6                                                         /*!< SCU SFSP6_3: EZI Position           */
+#define SCU_SFSP6_3_EZI_Msk                                   (0x01UL << SCU_SFSP6_3_EZI_Pos)                           /*!< SCU SFSP6_3: EZI Mask               */
+#define SCU_SFSP6_3_EHD_Pos                                   8                                                         /*!< SCU SFSP6_3: EHD Position           */
+#define SCU_SFSP6_3_EHD_Msk                                   (0x03UL << SCU_SFSP6_3_EHD_Pos)                           /*!< SCU SFSP6_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_4  ------------------------------------------
+#define SCU_SFSP6_4_MODE_Pos                                  0                                                         /*!< SCU SFSP6_4: MODE Position          */
+#define SCU_SFSP6_4_MODE_Msk                                  (0x07UL << SCU_SFSP6_4_MODE_Pos)                          /*!< SCU SFSP6_4: MODE Mask              */
+#define SCU_SFSP6_4_EPD_Pos                                   3                                                         /*!< SCU SFSP6_4: EPD Position           */
+#define SCU_SFSP6_4_EPD_Msk                                   (0x01UL << SCU_SFSP6_4_EPD_Pos)                           /*!< SCU SFSP6_4: EPD Mask               */
+#define SCU_SFSP6_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_4: EPUN Position          */
+#define SCU_SFSP6_4_EPUN_Msk                                  (0x01UL << SCU_SFSP6_4_EPUN_Pos)                          /*!< SCU SFSP6_4: EPUN Mask              */
+#define SCU_SFSP6_4_EHS_Pos                                   5                                                         /*!< SCU SFSP6_4: EHS Position           */
+#define SCU_SFSP6_4_EHS_Msk                                   (0x01UL << SCU_SFSP6_4_EHS_Pos)                           /*!< SCU SFSP6_4: EHS Mask               */
+#define SCU_SFSP6_4_EZI_Pos                                   6                                                         /*!< SCU SFSP6_4: EZI Position           */
+#define SCU_SFSP6_4_EZI_Msk                                   (0x01UL << SCU_SFSP6_4_EZI_Pos)                           /*!< SCU SFSP6_4: EZI Mask               */
+#define SCU_SFSP6_4_EHD_Pos                                   8                                                         /*!< SCU SFSP6_4: EHD Position           */
+#define SCU_SFSP6_4_EHD_Msk                                   (0x03UL << SCU_SFSP6_4_EHD_Pos)                           /*!< SCU SFSP6_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_5  ------------------------------------------
+#define SCU_SFSP6_5_MODE_Pos                                  0                                                         /*!< SCU SFSP6_5: MODE Position          */
+#define SCU_SFSP6_5_MODE_Msk                                  (0x07UL << SCU_SFSP6_5_MODE_Pos)                          /*!< SCU SFSP6_5: MODE Mask              */
+#define SCU_SFSP6_5_EPD_Pos                                   3                                                         /*!< SCU SFSP6_5: EPD Position           */
+#define SCU_SFSP6_5_EPD_Msk                                   (0x01UL << SCU_SFSP6_5_EPD_Pos)                           /*!< SCU SFSP6_5: EPD Mask               */
+#define SCU_SFSP6_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_5: EPUN Position          */
+#define SCU_SFSP6_5_EPUN_Msk                                  (0x01UL << SCU_SFSP6_5_EPUN_Pos)                          /*!< SCU SFSP6_5: EPUN Mask              */
+#define SCU_SFSP6_5_EHS_Pos                                   5                                                         /*!< SCU SFSP6_5: EHS Position           */
+#define SCU_SFSP6_5_EHS_Msk                                   (0x01UL << SCU_SFSP6_5_EHS_Pos)                           /*!< SCU SFSP6_5: EHS Mask               */
+#define SCU_SFSP6_5_EZI_Pos                                   6                                                         /*!< SCU SFSP6_5: EZI Position           */
+#define SCU_SFSP6_5_EZI_Msk                                   (0x01UL << SCU_SFSP6_5_EZI_Pos)                           /*!< SCU SFSP6_5: EZI Mask               */
+#define SCU_SFSP6_5_EHD_Pos                                   8                                                         /*!< SCU SFSP6_5: EHD Position           */
+#define SCU_SFSP6_5_EHD_Msk                                   (0x03UL << SCU_SFSP6_5_EHD_Pos)                           /*!< SCU SFSP6_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_6  ------------------------------------------
+#define SCU_SFSP6_6_MODE_Pos                                  0                                                         /*!< SCU SFSP6_6: MODE Position          */
+#define SCU_SFSP6_6_MODE_Msk                                  (0x07UL << SCU_SFSP6_6_MODE_Pos)                          /*!< SCU SFSP6_6: MODE Mask              */
+#define SCU_SFSP6_6_EPD_Pos                                   3                                                         /*!< SCU SFSP6_6: EPD Position           */
+#define SCU_SFSP6_6_EPD_Msk                                   (0x01UL << SCU_SFSP6_6_EPD_Pos)                           /*!< SCU SFSP6_6: EPD Mask               */
+#define SCU_SFSP6_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_6: EPUN Position          */
+#define SCU_SFSP6_6_EPUN_Msk                                  (0x01UL << SCU_SFSP6_6_EPUN_Pos)                          /*!< SCU SFSP6_6: EPUN Mask              */
+#define SCU_SFSP6_6_EHS_Pos                                   5                                                         /*!< SCU SFSP6_6: EHS Position           */
+#define SCU_SFSP6_6_EHS_Msk                                   (0x01UL << SCU_SFSP6_6_EHS_Pos)                           /*!< SCU SFSP6_6: EHS Mask               */
+#define SCU_SFSP6_6_EZI_Pos                                   6                                                         /*!< SCU SFSP6_6: EZI Position           */
+#define SCU_SFSP6_6_EZI_Msk                                   (0x01UL << SCU_SFSP6_6_EZI_Pos)                           /*!< SCU SFSP6_6: EZI Mask               */
+#define SCU_SFSP6_6_EHD_Pos                                   8                                                         /*!< SCU SFSP6_6: EHD Position           */
+#define SCU_SFSP6_6_EHD_Msk                                   (0x03UL << SCU_SFSP6_6_EHD_Pos)                           /*!< SCU SFSP6_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_7  ------------------------------------------
+#define SCU_SFSP6_7_MODE_Pos                                  0                                                         /*!< SCU SFSP6_7: MODE Position          */
+#define SCU_SFSP6_7_MODE_Msk                                  (0x07UL << SCU_SFSP6_7_MODE_Pos)                          /*!< SCU SFSP6_7: MODE Mask              */
+#define SCU_SFSP6_7_EPD_Pos                                   3                                                         /*!< SCU SFSP6_7: EPD Position           */
+#define SCU_SFSP6_7_EPD_Msk                                   (0x01UL << SCU_SFSP6_7_EPD_Pos)                           /*!< SCU SFSP6_7: EPD Mask               */
+#define SCU_SFSP6_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_7: EPUN Position          */
+#define SCU_SFSP6_7_EPUN_Msk                                  (0x01UL << SCU_SFSP6_7_EPUN_Pos)                          /*!< SCU SFSP6_7: EPUN Mask              */
+#define SCU_SFSP6_7_EHS_Pos                                   5                                                         /*!< SCU SFSP6_7: EHS Position           */
+#define SCU_SFSP6_7_EHS_Msk                                   (0x01UL << SCU_SFSP6_7_EHS_Pos)                           /*!< SCU SFSP6_7: EHS Mask               */
+#define SCU_SFSP6_7_EZI_Pos                                   6                                                         /*!< SCU SFSP6_7: EZI Position           */
+#define SCU_SFSP6_7_EZI_Msk                                   (0x01UL << SCU_SFSP6_7_EZI_Pos)                           /*!< SCU SFSP6_7: EZI Mask               */
+#define SCU_SFSP6_7_EHD_Pos                                   8                                                         /*!< SCU SFSP6_7: EHD Position           */
+#define SCU_SFSP6_7_EHD_Msk                                   (0x03UL << SCU_SFSP6_7_EHD_Pos)                           /*!< SCU SFSP6_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_8  ------------------------------------------
+#define SCU_SFSP6_8_MODE_Pos                                  0                                                         /*!< SCU SFSP6_8: MODE Position          */
+#define SCU_SFSP6_8_MODE_Msk                                  (0x07UL << SCU_SFSP6_8_MODE_Pos)                          /*!< SCU SFSP6_8: MODE Mask              */
+#define SCU_SFSP6_8_EPD_Pos                                   3                                                         /*!< SCU SFSP6_8: EPD Position           */
+#define SCU_SFSP6_8_EPD_Msk                                   (0x01UL << SCU_SFSP6_8_EPD_Pos)                           /*!< SCU SFSP6_8: EPD Mask               */
+#define SCU_SFSP6_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_8: EPUN Position          */
+#define SCU_SFSP6_8_EPUN_Msk                                  (0x01UL << SCU_SFSP6_8_EPUN_Pos)                          /*!< SCU SFSP6_8: EPUN Mask              */
+#define SCU_SFSP6_8_EHS_Pos                                   5                                                         /*!< SCU SFSP6_8: EHS Position           */
+#define SCU_SFSP6_8_EHS_Msk                                   (0x01UL << SCU_SFSP6_8_EHS_Pos)                           /*!< SCU SFSP6_8: EHS Mask               */
+#define SCU_SFSP6_8_EZI_Pos                                   6                                                         /*!< SCU SFSP6_8: EZI Position           */
+#define SCU_SFSP6_8_EZI_Msk                                   (0x01UL << SCU_SFSP6_8_EZI_Pos)                           /*!< SCU SFSP6_8: EZI Mask               */
+#define SCU_SFSP6_8_EHD_Pos                                   8                                                         /*!< SCU SFSP6_8: EHD Position           */
+#define SCU_SFSP6_8_EHD_Msk                                   (0x03UL << SCU_SFSP6_8_EHD_Pos)                           /*!< SCU SFSP6_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_9  ------------------------------------------
+#define SCU_SFSP6_9_MODE_Pos                                  0                                                         /*!< SCU SFSP6_9: MODE Position          */
+#define SCU_SFSP6_9_MODE_Msk                                  (0x07UL << SCU_SFSP6_9_MODE_Pos)                          /*!< SCU SFSP6_9: MODE Mask              */
+#define SCU_SFSP6_9_EPD_Pos                                   3                                                         /*!< SCU SFSP6_9: EPD Position           */
+#define SCU_SFSP6_9_EPD_Msk                                   (0x01UL << SCU_SFSP6_9_EPD_Pos)                           /*!< SCU SFSP6_9: EPD Mask               */
+#define SCU_SFSP6_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_9: EPUN Position          */
+#define SCU_SFSP6_9_EPUN_Msk                                  (0x01UL << SCU_SFSP6_9_EPUN_Pos)                          /*!< SCU SFSP6_9: EPUN Mask              */
+#define SCU_SFSP6_9_EHS_Pos                                   5                                                         /*!< SCU SFSP6_9: EHS Position           */
+#define SCU_SFSP6_9_EHS_Msk                                   (0x01UL << SCU_SFSP6_9_EHS_Pos)                           /*!< SCU SFSP6_9: EHS Mask               */
+#define SCU_SFSP6_9_EZI_Pos                                   6                                                         /*!< SCU SFSP6_9: EZI Position           */
+#define SCU_SFSP6_9_EZI_Msk                                   (0x01UL << SCU_SFSP6_9_EZI_Pos)                           /*!< SCU SFSP6_9: EZI Mask               */
+#define SCU_SFSP6_9_EHD_Pos                                   8                                                         /*!< SCU SFSP6_9: EHD Position           */
+#define SCU_SFSP6_9_EHD_Msk                                   (0x03UL << SCU_SFSP6_9_EHD_Pos)                           /*!< SCU SFSP6_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP6_10  ------------------------------------------
+#define SCU_SFSP6_10_MODE_Pos                                 0                                                         /*!< SCU SFSP6_10: MODE Position         */
+#define SCU_SFSP6_10_MODE_Msk                                 (0x07UL << SCU_SFSP6_10_MODE_Pos)                         /*!< SCU SFSP6_10: MODE Mask             */
+#define SCU_SFSP6_10_EPD_Pos                                  3                                                         /*!< SCU SFSP6_10: EPD Position          */
+#define SCU_SFSP6_10_EPD_Msk                                  (0x01UL << SCU_SFSP6_10_EPD_Pos)                          /*!< SCU SFSP6_10: EPD Mask              */
+#define SCU_SFSP6_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_10: EPUN Position         */
+#define SCU_SFSP6_10_EPUN_Msk                                 (0x01UL << SCU_SFSP6_10_EPUN_Pos)                         /*!< SCU SFSP6_10: EPUN Mask             */
+#define SCU_SFSP6_10_EHS_Pos                                  5                                                         /*!< SCU SFSP6_10: EHS Position          */
+#define SCU_SFSP6_10_EHS_Msk                                  (0x01UL << SCU_SFSP6_10_EHS_Pos)                          /*!< SCU SFSP6_10: EHS Mask              */
+#define SCU_SFSP6_10_EZI_Pos                                  6                                                         /*!< SCU SFSP6_10: EZI Position          */
+#define SCU_SFSP6_10_EZI_Msk                                  (0x01UL << SCU_SFSP6_10_EZI_Pos)                          /*!< SCU SFSP6_10: EZI Mask              */
+#define SCU_SFSP6_10_EHD_Pos                                  8                                                         /*!< SCU SFSP6_10: EHD Position          */
+#define SCU_SFSP6_10_EHD_Msk                                  (0x03UL << SCU_SFSP6_10_EHD_Pos)                          /*!< SCU SFSP6_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP6_11  ------------------------------------------
+#define SCU_SFSP6_11_MODE_Pos                                 0                                                         /*!< SCU SFSP6_11: MODE Position         */
+#define SCU_SFSP6_11_MODE_Msk                                 (0x07UL << SCU_SFSP6_11_MODE_Pos)                         /*!< SCU SFSP6_11: MODE Mask             */
+#define SCU_SFSP6_11_EPD_Pos                                  3                                                         /*!< SCU SFSP6_11: EPD Position          */
+#define SCU_SFSP6_11_EPD_Msk                                  (0x01UL << SCU_SFSP6_11_EPD_Pos)                          /*!< SCU SFSP6_11: EPD Mask              */
+#define SCU_SFSP6_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_11: EPUN Position         */
+#define SCU_SFSP6_11_EPUN_Msk                                 (0x01UL << SCU_SFSP6_11_EPUN_Pos)                         /*!< SCU SFSP6_11: EPUN Mask             */
+#define SCU_SFSP6_11_EHS_Pos                                  5                                                         /*!< SCU SFSP6_11: EHS Position          */
+#define SCU_SFSP6_11_EHS_Msk                                  (0x01UL << SCU_SFSP6_11_EHS_Pos)                          /*!< SCU SFSP6_11: EHS Mask              */
+#define SCU_SFSP6_11_EZI_Pos                                  6                                                         /*!< SCU SFSP6_11: EZI Position          */
+#define SCU_SFSP6_11_EZI_Msk                                  (0x01UL << SCU_SFSP6_11_EZI_Pos)                          /*!< SCU SFSP6_11: EZI Mask              */
+#define SCU_SFSP6_11_EHD_Pos                                  8                                                         /*!< SCU SFSP6_11: EHD Position          */
+#define SCU_SFSP6_11_EHD_Msk                                  (0x03UL << SCU_SFSP6_11_EHD_Pos)                          /*!< SCU SFSP6_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP6_12  ------------------------------------------
+#define SCU_SFSP6_12_MODE_Pos                                 0                                                         /*!< SCU SFSP6_12: MODE Position         */
+#define SCU_SFSP6_12_MODE_Msk                                 (0x07UL << SCU_SFSP6_12_MODE_Pos)                         /*!< SCU SFSP6_12: MODE Mask             */
+#define SCU_SFSP6_12_EPD_Pos                                  3                                                         /*!< SCU SFSP6_12: EPD Position          */
+#define SCU_SFSP6_12_EPD_Msk                                  (0x01UL << SCU_SFSP6_12_EPD_Pos)                          /*!< SCU SFSP6_12: EPD Mask              */
+#define SCU_SFSP6_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_12: EPUN Position         */
+#define SCU_SFSP6_12_EPUN_Msk                                 (0x01UL << SCU_SFSP6_12_EPUN_Pos)                         /*!< SCU SFSP6_12: EPUN Mask             */
+#define SCU_SFSP6_12_EHS_Pos                                  5                                                         /*!< SCU SFSP6_12: EHS Position          */
+#define SCU_SFSP6_12_EHS_Msk                                  (0x01UL << SCU_SFSP6_12_EHS_Pos)                          /*!< SCU SFSP6_12: EHS Mask              */
+#define SCU_SFSP6_12_EZI_Pos                                  6                                                         /*!< SCU SFSP6_12: EZI Position          */
+#define SCU_SFSP6_12_EZI_Msk                                  (0x01UL << SCU_SFSP6_12_EZI_Pos)                          /*!< SCU SFSP6_12: EZI Mask              */
+#define SCU_SFSP6_12_EHD_Pos                                  8                                                         /*!< SCU SFSP6_12: EHD Position          */
+#define SCU_SFSP6_12_EHD_Msk                                  (0x03UL << SCU_SFSP6_12_EHD_Pos)                          /*!< SCU SFSP6_12: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP7_0  ------------------------------------------
+#define SCU_SFSP7_0_MODE_Pos                                  0                                                         /*!< SCU SFSP7_0: MODE Position          */
+#define SCU_SFSP7_0_MODE_Msk                                  (0x07UL << SCU_SFSP7_0_MODE_Pos)                          /*!< SCU SFSP7_0: MODE Mask              */
+#define SCU_SFSP7_0_EPD_Pos                                   3                                                         /*!< SCU SFSP7_0: EPD Position           */
+#define SCU_SFSP7_0_EPD_Msk                                   (0x01UL << SCU_SFSP7_0_EPD_Pos)                           /*!< SCU SFSP7_0: EPD Mask               */
+#define SCU_SFSP7_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_0: EPUN Position          */
+#define SCU_SFSP7_0_EPUN_Msk                                  (0x01UL << SCU_SFSP7_0_EPUN_Pos)                          /*!< SCU SFSP7_0: EPUN Mask              */
+#define SCU_SFSP7_0_EHS_Pos                                   5                                                         /*!< SCU SFSP7_0: EHS Position           */
+#define SCU_SFSP7_0_EHS_Msk                                   (0x01UL << SCU_SFSP7_0_EHS_Pos)                           /*!< SCU SFSP7_0: EHS Mask               */
+#define SCU_SFSP7_0_EZI_Pos                                   6                                                         /*!< SCU SFSP7_0: EZI Position           */
+#define SCU_SFSP7_0_EZI_Msk                                   (0x01UL << SCU_SFSP7_0_EZI_Pos)                           /*!< SCU SFSP7_0: EZI Mask               */
+#define SCU_SFSP7_0_EHD_Pos                                   8                                                         /*!< SCU SFSP7_0: EHD Position           */
+#define SCU_SFSP7_0_EHD_Msk                                   (0x03UL << SCU_SFSP7_0_EHD_Pos)                           /*!< SCU SFSP7_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_1  ------------------------------------------
+#define SCU_SFSP7_1_MODE_Pos                                  0                                                         /*!< SCU SFSP7_1: MODE Position          */
+#define SCU_SFSP7_1_MODE_Msk                                  (0x07UL << SCU_SFSP7_1_MODE_Pos)                          /*!< SCU SFSP7_1: MODE Mask              */
+#define SCU_SFSP7_1_EPD_Pos                                   3                                                         /*!< SCU SFSP7_1: EPD Position           */
+#define SCU_SFSP7_1_EPD_Msk                                   (0x01UL << SCU_SFSP7_1_EPD_Pos)                           /*!< SCU SFSP7_1: EPD Mask               */
+#define SCU_SFSP7_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_1: EPUN Position          */
+#define SCU_SFSP7_1_EPUN_Msk                                  (0x01UL << SCU_SFSP7_1_EPUN_Pos)                          /*!< SCU SFSP7_1: EPUN Mask              */
+#define SCU_SFSP7_1_EHS_Pos                                   5                                                         /*!< SCU SFSP7_1: EHS Position           */
+#define SCU_SFSP7_1_EHS_Msk                                   (0x01UL << SCU_SFSP7_1_EHS_Pos)                           /*!< SCU SFSP7_1: EHS Mask               */
+#define SCU_SFSP7_1_EZI_Pos                                   6                                                         /*!< SCU SFSP7_1: EZI Position           */
+#define SCU_SFSP7_1_EZI_Msk                                   (0x01UL << SCU_SFSP7_1_EZI_Pos)                           /*!< SCU SFSP7_1: EZI Mask               */
+#define SCU_SFSP7_1_EHD_Pos                                   8                                                         /*!< SCU SFSP7_1: EHD Position           */
+#define SCU_SFSP7_1_EHD_Msk                                   (0x03UL << SCU_SFSP7_1_EHD_Pos)                           /*!< SCU SFSP7_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_2  ------------------------------------------
+#define SCU_SFSP7_2_MODE_Pos                                  0                                                         /*!< SCU SFSP7_2: MODE Position          */
+#define SCU_SFSP7_2_MODE_Msk                                  (0x07UL << SCU_SFSP7_2_MODE_Pos)                          /*!< SCU SFSP7_2: MODE Mask              */
+#define SCU_SFSP7_2_EPD_Pos                                   3                                                         /*!< SCU SFSP7_2: EPD Position           */
+#define SCU_SFSP7_2_EPD_Msk                                   (0x01UL << SCU_SFSP7_2_EPD_Pos)                           /*!< SCU SFSP7_2: EPD Mask               */
+#define SCU_SFSP7_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_2: EPUN Position          */
+#define SCU_SFSP7_2_EPUN_Msk                                  (0x01UL << SCU_SFSP7_2_EPUN_Pos)                          /*!< SCU SFSP7_2: EPUN Mask              */
+#define SCU_SFSP7_2_EHS_Pos                                   5                                                         /*!< SCU SFSP7_2: EHS Position           */
+#define SCU_SFSP7_2_EHS_Msk                                   (0x01UL << SCU_SFSP7_2_EHS_Pos)                           /*!< SCU SFSP7_2: EHS Mask               */
+#define SCU_SFSP7_2_EZI_Pos                                   6                                                         /*!< SCU SFSP7_2: EZI Position           */
+#define SCU_SFSP7_2_EZI_Msk                                   (0x01UL << SCU_SFSP7_2_EZI_Pos)                           /*!< SCU SFSP7_2: EZI Mask               */
+#define SCU_SFSP7_2_EHD_Pos                                   8                                                         /*!< SCU SFSP7_2: EHD Position           */
+#define SCU_SFSP7_2_EHD_Msk                                   (0x03UL << SCU_SFSP7_2_EHD_Pos)                           /*!< SCU SFSP7_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_3  ------------------------------------------
+#define SCU_SFSP7_3_MODE_Pos                                  0                                                         /*!< SCU SFSP7_3: MODE Position          */
+#define SCU_SFSP7_3_MODE_Msk                                  (0x07UL << SCU_SFSP7_3_MODE_Pos)                          /*!< SCU SFSP7_3: MODE Mask              */
+#define SCU_SFSP7_3_EPD_Pos                                   3                                                         /*!< SCU SFSP7_3: EPD Position           */
+#define SCU_SFSP7_3_EPD_Msk                                   (0x01UL << SCU_SFSP7_3_EPD_Pos)                           /*!< SCU SFSP7_3: EPD Mask               */
+#define SCU_SFSP7_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_3: EPUN Position          */
+#define SCU_SFSP7_3_EPUN_Msk                                  (0x01UL << SCU_SFSP7_3_EPUN_Pos)                          /*!< SCU SFSP7_3: EPUN Mask              */
+#define SCU_SFSP7_3_EHS_Pos                                   5                                                         /*!< SCU SFSP7_3: EHS Position           */
+#define SCU_SFSP7_3_EHS_Msk                                   (0x01UL << SCU_SFSP7_3_EHS_Pos)                           /*!< SCU SFSP7_3: EHS Mask               */
+#define SCU_SFSP7_3_EZI_Pos                                   6                                                         /*!< SCU SFSP7_3: EZI Position           */
+#define SCU_SFSP7_3_EZI_Msk                                   (0x01UL << SCU_SFSP7_3_EZI_Pos)                           /*!< SCU SFSP7_3: EZI Mask               */
+#define SCU_SFSP7_3_EHD_Pos                                   8                                                         /*!< SCU SFSP7_3: EHD Position           */
+#define SCU_SFSP7_3_EHD_Msk                                   (0x03UL << SCU_SFSP7_3_EHD_Pos)                           /*!< SCU SFSP7_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_4  ------------------------------------------
+#define SCU_SFSP7_4_MODE_Pos                                  0                                                         /*!< SCU SFSP7_4: MODE Position          */
+#define SCU_SFSP7_4_MODE_Msk                                  (0x07UL << SCU_SFSP7_4_MODE_Pos)                          /*!< SCU SFSP7_4: MODE Mask              */
+#define SCU_SFSP7_4_EPD_Pos                                   3                                                         /*!< SCU SFSP7_4: EPD Position           */
+#define SCU_SFSP7_4_EPD_Msk                                   (0x01UL << SCU_SFSP7_4_EPD_Pos)                           /*!< SCU SFSP7_4: EPD Mask               */
+#define SCU_SFSP7_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_4: EPUN Position          */
+#define SCU_SFSP7_4_EPUN_Msk                                  (0x01UL << SCU_SFSP7_4_EPUN_Pos)                          /*!< SCU SFSP7_4: EPUN Mask              */
+#define SCU_SFSP7_4_EHS_Pos                                   5                                                         /*!< SCU SFSP7_4: EHS Position           */
+#define SCU_SFSP7_4_EHS_Msk                                   (0x01UL << SCU_SFSP7_4_EHS_Pos)                           /*!< SCU SFSP7_4: EHS Mask               */
+#define SCU_SFSP7_4_EZI_Pos                                   6                                                         /*!< SCU SFSP7_4: EZI Position           */
+#define SCU_SFSP7_4_EZI_Msk                                   (0x01UL << SCU_SFSP7_4_EZI_Pos)                           /*!< SCU SFSP7_4: EZI Mask               */
+#define SCU_SFSP7_4_EHD_Pos                                   8                                                         /*!< SCU SFSP7_4: EHD Position           */
+#define SCU_SFSP7_4_EHD_Msk                                   (0x03UL << SCU_SFSP7_4_EHD_Pos)                           /*!< SCU SFSP7_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_5  ------------------------------------------
+#define SCU_SFSP7_5_MODE_Pos                                  0                                                         /*!< SCU SFSP7_5: MODE Position          */
+#define SCU_SFSP7_5_MODE_Msk                                  (0x07UL << SCU_SFSP7_5_MODE_Pos)                          /*!< SCU SFSP7_5: MODE Mask              */
+#define SCU_SFSP7_5_EPD_Pos                                   3                                                         /*!< SCU SFSP7_5: EPD Position           */
+#define SCU_SFSP7_5_EPD_Msk                                   (0x01UL << SCU_SFSP7_5_EPD_Pos)                           /*!< SCU SFSP7_5: EPD Mask               */
+#define SCU_SFSP7_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_5: EPUN Position          */
+#define SCU_SFSP7_5_EPUN_Msk                                  (0x01UL << SCU_SFSP7_5_EPUN_Pos)                          /*!< SCU SFSP7_5: EPUN Mask              */
+#define SCU_SFSP7_5_EHS_Pos                                   5                                                         /*!< SCU SFSP7_5: EHS Position           */
+#define SCU_SFSP7_5_EHS_Msk                                   (0x01UL << SCU_SFSP7_5_EHS_Pos)                           /*!< SCU SFSP7_5: EHS Mask               */
+#define SCU_SFSP7_5_EZI_Pos                                   6                                                         /*!< SCU SFSP7_5: EZI Position           */
+#define SCU_SFSP7_5_EZI_Msk                                   (0x01UL << SCU_SFSP7_5_EZI_Pos)                           /*!< SCU SFSP7_5: EZI Mask               */
+#define SCU_SFSP7_5_EHD_Pos                                   8                                                         /*!< SCU SFSP7_5: EHD Position           */
+#define SCU_SFSP7_5_EHD_Msk                                   (0x03UL << SCU_SFSP7_5_EHD_Pos)                           /*!< SCU SFSP7_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_6  ------------------------------------------
+#define SCU_SFSP7_6_MODE_Pos                                  0                                                         /*!< SCU SFSP7_6: MODE Position          */
+#define SCU_SFSP7_6_MODE_Msk                                  (0x07UL << SCU_SFSP7_6_MODE_Pos)                          /*!< SCU SFSP7_6: MODE Mask              */
+#define SCU_SFSP7_6_EPD_Pos                                   3                                                         /*!< SCU SFSP7_6: EPD Position           */
+#define SCU_SFSP7_6_EPD_Msk                                   (0x01UL << SCU_SFSP7_6_EPD_Pos)                           /*!< SCU SFSP7_6: EPD Mask               */
+#define SCU_SFSP7_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_6: EPUN Position          */
+#define SCU_SFSP7_6_EPUN_Msk                                  (0x01UL << SCU_SFSP7_6_EPUN_Pos)                          /*!< SCU SFSP7_6: EPUN Mask              */
+#define SCU_SFSP7_6_EHS_Pos                                   5                                                         /*!< SCU SFSP7_6: EHS Position           */
+#define SCU_SFSP7_6_EHS_Msk                                   (0x01UL << SCU_SFSP7_6_EHS_Pos)                           /*!< SCU SFSP7_6: EHS Mask               */
+#define SCU_SFSP7_6_EZI_Pos                                   6                                                         /*!< SCU SFSP7_6: EZI Position           */
+#define SCU_SFSP7_6_EZI_Msk                                   (0x01UL << SCU_SFSP7_6_EZI_Pos)                           /*!< SCU SFSP7_6: EZI Mask               */
+#define SCU_SFSP7_6_EHD_Pos                                   8                                                         /*!< SCU SFSP7_6: EHD Position           */
+#define SCU_SFSP7_6_EHD_Msk                                   (0x03UL << SCU_SFSP7_6_EHD_Pos)                           /*!< SCU SFSP7_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_7  ------------------------------------------
+#define SCU_SFSP7_7_MODE_Pos                                  0                                                         /*!< SCU SFSP7_7: MODE Position          */
+#define SCU_SFSP7_7_MODE_Msk                                  (0x07UL << SCU_SFSP7_7_MODE_Pos)                          /*!< SCU SFSP7_7: MODE Mask              */
+#define SCU_SFSP7_7_EPD_Pos                                   3                                                         /*!< SCU SFSP7_7: EPD Position           */
+#define SCU_SFSP7_7_EPD_Msk                                   (0x01UL << SCU_SFSP7_7_EPD_Pos)                           /*!< SCU SFSP7_7: EPD Mask               */
+#define SCU_SFSP7_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_7: EPUN Position          */
+#define SCU_SFSP7_7_EPUN_Msk                                  (0x01UL << SCU_SFSP7_7_EPUN_Pos)                          /*!< SCU SFSP7_7: EPUN Mask              */
+#define SCU_SFSP7_7_EHS_Pos                                   5                                                         /*!< SCU SFSP7_7: EHS Position           */
+#define SCU_SFSP7_7_EHS_Msk                                   (0x01UL << SCU_SFSP7_7_EHS_Pos)                           /*!< SCU SFSP7_7: EHS Mask               */
+#define SCU_SFSP7_7_EZI_Pos                                   6                                                         /*!< SCU SFSP7_7: EZI Position           */
+#define SCU_SFSP7_7_EZI_Msk                                   (0x01UL << SCU_SFSP7_7_EZI_Pos)                           /*!< SCU SFSP7_7: EZI Mask               */
+#define SCU_SFSP7_7_EHD_Pos                                   8                                                         /*!< SCU SFSP7_7: EHD Position           */
+#define SCU_SFSP7_7_EHD_Msk                                   (0x03UL << SCU_SFSP7_7_EHD_Pos)                           /*!< SCU SFSP7_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_0  ------------------------------------------
+#define SCU_SFSP8_0_MODE_Pos                                  0                                                         /*!< SCU SFSP8_0: MODE Position          */
+#define SCU_SFSP8_0_MODE_Msk                                  (0x07UL << SCU_SFSP8_0_MODE_Pos)                          /*!< SCU SFSP8_0: MODE Mask              */
+#define SCU_SFSP8_0_EPD_Pos                                   3                                                         /*!< SCU SFSP8_0: EPD Position           */
+#define SCU_SFSP8_0_EPD_Msk                                   (0x01UL << SCU_SFSP8_0_EPD_Pos)                           /*!< SCU SFSP8_0: EPD Mask               */
+#define SCU_SFSP8_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_0: EPUN Position          */
+#define SCU_SFSP8_0_EPUN_Msk                                  (0x01UL << SCU_SFSP8_0_EPUN_Pos)                          /*!< SCU SFSP8_0: EPUN Mask              */
+#define SCU_SFSP8_0_EHS_Pos                                   5                                                         /*!< SCU SFSP8_0: EHS Position           */
+#define SCU_SFSP8_0_EHS_Msk                                   (0x01UL << SCU_SFSP8_0_EHS_Pos)                           /*!< SCU SFSP8_0: EHS Mask               */
+#define SCU_SFSP8_0_EZI_Pos                                   6                                                         /*!< SCU SFSP8_0: EZI Position           */
+#define SCU_SFSP8_0_EZI_Msk                                   (0x01UL << SCU_SFSP8_0_EZI_Pos)                           /*!< SCU SFSP8_0: EZI Mask               */
+#define SCU_SFSP8_0_EHD_Pos                                   8                                                         /*!< SCU SFSP8_0: EHD Position           */
+#define SCU_SFSP8_0_EHD_Msk                                   (0x03UL << SCU_SFSP8_0_EHD_Pos)                           /*!< SCU SFSP8_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_1  ------------------------------------------
+#define SCU_SFSP8_1_MODE_Pos                                  0                                                         /*!< SCU SFSP8_1: MODE Position          */
+#define SCU_SFSP8_1_MODE_Msk                                  (0x07UL << SCU_SFSP8_1_MODE_Pos)                          /*!< SCU SFSP8_1: MODE Mask              */
+#define SCU_SFSP8_1_EPD_Pos                                   3                                                         /*!< SCU SFSP8_1: EPD Position           */
+#define SCU_SFSP8_1_EPD_Msk                                   (0x01UL << SCU_SFSP8_1_EPD_Pos)                           /*!< SCU SFSP8_1: EPD Mask               */
+#define SCU_SFSP8_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_1: EPUN Position          */
+#define SCU_SFSP8_1_EPUN_Msk                                  (0x01UL << SCU_SFSP8_1_EPUN_Pos)                          /*!< SCU SFSP8_1: EPUN Mask              */
+#define SCU_SFSP8_1_EHS_Pos                                   5                                                         /*!< SCU SFSP8_1: EHS Position           */
+#define SCU_SFSP8_1_EHS_Msk                                   (0x01UL << SCU_SFSP8_1_EHS_Pos)                           /*!< SCU SFSP8_1: EHS Mask               */
+#define SCU_SFSP8_1_EZI_Pos                                   6                                                         /*!< SCU SFSP8_1: EZI Position           */
+#define SCU_SFSP8_1_EZI_Msk                                   (0x01UL << SCU_SFSP8_1_EZI_Pos)                           /*!< SCU SFSP8_1: EZI Mask               */
+#define SCU_SFSP8_1_EHD_Pos                                   8                                                         /*!< SCU SFSP8_1: EHD Position           */
+#define SCU_SFSP8_1_EHD_Msk                                   (0x03UL << SCU_SFSP8_1_EHD_Pos)                           /*!< SCU SFSP8_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_2  ------------------------------------------
+#define SCU_SFSP8_2_MODE_Pos                                  0                                                         /*!< SCU SFSP8_2: MODE Position          */
+#define SCU_SFSP8_2_MODE_Msk                                  (0x07UL << SCU_SFSP8_2_MODE_Pos)                          /*!< SCU SFSP8_2: MODE Mask              */
+#define SCU_SFSP8_2_EPD_Pos                                   3                                                         /*!< SCU SFSP8_2: EPD Position           */
+#define SCU_SFSP8_2_EPD_Msk                                   (0x01UL << SCU_SFSP8_2_EPD_Pos)                           /*!< SCU SFSP8_2: EPD Mask               */
+#define SCU_SFSP8_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_2: EPUN Position          */
+#define SCU_SFSP8_2_EPUN_Msk                                  (0x01UL << SCU_SFSP8_2_EPUN_Pos)                          /*!< SCU SFSP8_2: EPUN Mask              */
+#define SCU_SFSP8_2_EHS_Pos                                   5                                                         /*!< SCU SFSP8_2: EHS Position           */
+#define SCU_SFSP8_2_EHS_Msk                                   (0x01UL << SCU_SFSP8_2_EHS_Pos)                           /*!< SCU SFSP8_2: EHS Mask               */
+#define SCU_SFSP8_2_EZI_Pos                                   6                                                         /*!< SCU SFSP8_2: EZI Position           */
+#define SCU_SFSP8_2_EZI_Msk                                   (0x01UL << SCU_SFSP8_2_EZI_Pos)                           /*!< SCU SFSP8_2: EZI Mask               */
+#define SCU_SFSP8_2_EHD_Pos                                   8                                                         /*!< SCU SFSP8_2: EHD Position           */
+#define SCU_SFSP8_2_EHD_Msk                                   (0x03UL << SCU_SFSP8_2_EHD_Pos)                           /*!< SCU SFSP8_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_3  ------------------------------------------
+#define SCU_SFSP8_3_MODE_Pos                                  0                                                         /*!< SCU SFSP8_3: MODE Position          */
+#define SCU_SFSP8_3_MODE_Msk                                  (0x07UL << SCU_SFSP8_3_MODE_Pos)                          /*!< SCU SFSP8_3: MODE Mask              */
+#define SCU_SFSP8_3_EPD_Pos                                   3                                                         /*!< SCU SFSP8_3: EPD Position           */
+#define SCU_SFSP8_3_EPD_Msk                                   (0x01UL << SCU_SFSP8_3_EPD_Pos)                           /*!< SCU SFSP8_3: EPD Mask               */
+#define SCU_SFSP8_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_3: EPUN Position          */
+#define SCU_SFSP8_3_EPUN_Msk                                  (0x01UL << SCU_SFSP8_3_EPUN_Pos)                          /*!< SCU SFSP8_3: EPUN Mask              */
+#define SCU_SFSP8_3_EHS_Pos                                   5                                                         /*!< SCU SFSP8_3: EHS Position           */
+#define SCU_SFSP8_3_EHS_Msk                                   (0x01UL << SCU_SFSP8_3_EHS_Pos)                           /*!< SCU SFSP8_3: EHS Mask               */
+#define SCU_SFSP8_3_EZI_Pos                                   6                                                         /*!< SCU SFSP8_3: EZI Position           */
+#define SCU_SFSP8_3_EZI_Msk                                   (0x01UL << SCU_SFSP8_3_EZI_Pos)                           /*!< SCU SFSP8_3: EZI Mask               */
+#define SCU_SFSP8_3_EHD_Pos                                   8                                                         /*!< SCU SFSP8_3: EHD Position           */
+#define SCU_SFSP8_3_EHD_Msk                                   (0x03UL << SCU_SFSP8_3_EHD_Pos)                           /*!< SCU SFSP8_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_4  ------------------------------------------
+#define SCU_SFSP8_4_MODE_Pos                                  0                                                         /*!< SCU SFSP8_4: MODE Position          */
+#define SCU_SFSP8_4_MODE_Msk                                  (0x07UL << SCU_SFSP8_4_MODE_Pos)                          /*!< SCU SFSP8_4: MODE Mask              */
+#define SCU_SFSP8_4_EPD_Pos                                   3                                                         /*!< SCU SFSP8_4: EPD Position           */
+#define SCU_SFSP8_4_EPD_Msk                                   (0x01UL << SCU_SFSP8_4_EPD_Pos)                           /*!< SCU SFSP8_4: EPD Mask               */
+#define SCU_SFSP8_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_4: EPUN Position          */
+#define SCU_SFSP8_4_EPUN_Msk                                  (0x01UL << SCU_SFSP8_4_EPUN_Pos)                          /*!< SCU SFSP8_4: EPUN Mask              */
+#define SCU_SFSP8_4_EHS_Pos                                   5                                                         /*!< SCU SFSP8_4: EHS Position           */
+#define SCU_SFSP8_4_EHS_Msk                                   (0x01UL << SCU_SFSP8_4_EHS_Pos)                           /*!< SCU SFSP8_4: EHS Mask               */
+#define SCU_SFSP8_4_EZI_Pos                                   6                                                         /*!< SCU SFSP8_4: EZI Position           */
+#define SCU_SFSP8_4_EZI_Msk                                   (0x01UL << SCU_SFSP8_4_EZI_Pos)                           /*!< SCU SFSP8_4: EZI Mask               */
+#define SCU_SFSP8_4_EHD_Pos                                   8                                                         /*!< SCU SFSP8_4: EHD Position           */
+#define SCU_SFSP8_4_EHD_Msk                                   (0x03UL << SCU_SFSP8_4_EHD_Pos)                           /*!< SCU SFSP8_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_5  ------------------------------------------
+#define SCU_SFSP8_5_MODE_Pos                                  0                                                         /*!< SCU SFSP8_5: MODE Position          */
+#define SCU_SFSP8_5_MODE_Msk                                  (0x07UL << SCU_SFSP8_5_MODE_Pos)                          /*!< SCU SFSP8_5: MODE Mask              */
+#define SCU_SFSP8_5_EPD_Pos                                   3                                                         /*!< SCU SFSP8_5: EPD Position           */
+#define SCU_SFSP8_5_EPD_Msk                                   (0x01UL << SCU_SFSP8_5_EPD_Pos)                           /*!< SCU SFSP8_5: EPD Mask               */
+#define SCU_SFSP8_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_5: EPUN Position          */
+#define SCU_SFSP8_5_EPUN_Msk                                  (0x01UL << SCU_SFSP8_5_EPUN_Pos)                          /*!< SCU SFSP8_5: EPUN Mask              */
+#define SCU_SFSP8_5_EHS_Pos                                   5                                                         /*!< SCU SFSP8_5: EHS Position           */
+#define SCU_SFSP8_5_EHS_Msk                                   (0x01UL << SCU_SFSP8_5_EHS_Pos)                           /*!< SCU SFSP8_5: EHS Mask               */
+#define SCU_SFSP8_5_EZI_Pos                                   6                                                         /*!< SCU SFSP8_5: EZI Position           */
+#define SCU_SFSP8_5_EZI_Msk                                   (0x01UL << SCU_SFSP8_5_EZI_Pos)                           /*!< SCU SFSP8_5: EZI Mask               */
+#define SCU_SFSP8_5_EHD_Pos                                   8                                                         /*!< SCU SFSP8_5: EHD Position           */
+#define SCU_SFSP8_5_EHD_Msk                                   (0x03UL << SCU_SFSP8_5_EHD_Pos)                           /*!< SCU SFSP8_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_6  ------------------------------------------
+#define SCU_SFSP8_6_MODE_Pos                                  0                                                         /*!< SCU SFSP8_6: MODE Position          */
+#define SCU_SFSP8_6_MODE_Msk                                  (0x07UL << SCU_SFSP8_6_MODE_Pos)                          /*!< SCU SFSP8_6: MODE Mask              */
+#define SCU_SFSP8_6_EPD_Pos                                   3                                                         /*!< SCU SFSP8_6: EPD Position           */
+#define SCU_SFSP8_6_EPD_Msk                                   (0x01UL << SCU_SFSP8_6_EPD_Pos)                           /*!< SCU SFSP8_6: EPD Mask               */
+#define SCU_SFSP8_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_6: EPUN Position          */
+#define SCU_SFSP8_6_EPUN_Msk                                  (0x01UL << SCU_SFSP8_6_EPUN_Pos)                          /*!< SCU SFSP8_6: EPUN Mask              */
+#define SCU_SFSP8_6_EHS_Pos                                   5                                                         /*!< SCU SFSP8_6: EHS Position           */
+#define SCU_SFSP8_6_EHS_Msk                                   (0x01UL << SCU_SFSP8_6_EHS_Pos)                           /*!< SCU SFSP8_6: EHS Mask               */
+#define SCU_SFSP8_6_EZI_Pos                                   6                                                         /*!< SCU SFSP8_6: EZI Position           */
+#define SCU_SFSP8_6_EZI_Msk                                   (0x01UL << SCU_SFSP8_6_EZI_Pos)                           /*!< SCU SFSP8_6: EZI Mask               */
+#define SCU_SFSP8_6_EHD_Pos                                   8                                                         /*!< SCU SFSP8_6: EHD Position           */
+#define SCU_SFSP8_6_EHD_Msk                                   (0x03UL << SCU_SFSP8_6_EHD_Pos)                           /*!< SCU SFSP8_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_7  ------------------------------------------
+#define SCU_SFSP8_7_MODE_Pos                                  0                                                         /*!< SCU SFSP8_7: MODE Position          */
+#define SCU_SFSP8_7_MODE_Msk                                  (0x07UL << SCU_SFSP8_7_MODE_Pos)                          /*!< SCU SFSP8_7: MODE Mask              */
+#define SCU_SFSP8_7_EPD_Pos                                   3                                                         /*!< SCU SFSP8_7: EPD Position           */
+#define SCU_SFSP8_7_EPD_Msk                                   (0x01UL << SCU_SFSP8_7_EPD_Pos)                           /*!< SCU SFSP8_7: EPD Mask               */
+#define SCU_SFSP8_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_7: EPUN Position          */
+#define SCU_SFSP8_7_EPUN_Msk                                  (0x01UL << SCU_SFSP8_7_EPUN_Pos)                          /*!< SCU SFSP8_7: EPUN Mask              */
+#define SCU_SFSP8_7_EHS_Pos                                   5                                                         /*!< SCU SFSP8_7: EHS Position           */
+#define SCU_SFSP8_7_EHS_Msk                                   (0x01UL << SCU_SFSP8_7_EHS_Pos)                           /*!< SCU SFSP8_7: EHS Mask               */
+#define SCU_SFSP8_7_EZI_Pos                                   6                                                         /*!< SCU SFSP8_7: EZI Position           */
+#define SCU_SFSP8_7_EZI_Msk                                   (0x01UL << SCU_SFSP8_7_EZI_Pos)                           /*!< SCU SFSP8_7: EZI Mask               */
+#define SCU_SFSP8_7_EHD_Pos                                   8                                                         /*!< SCU SFSP8_7: EHD Position           */
+#define SCU_SFSP8_7_EHD_Msk                                   (0x03UL << SCU_SFSP8_7_EHD_Pos)                           /*!< SCU SFSP8_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_8  ------------------------------------------
+#define SCU_SFSP8_8_MODE_Pos                                  0                                                         /*!< SCU SFSP8_8: MODE Position          */
+#define SCU_SFSP8_8_MODE_Msk                                  (0x07UL << SCU_SFSP8_8_MODE_Pos)                          /*!< SCU SFSP8_8: MODE Mask              */
+#define SCU_SFSP8_8_EPD_Pos                                   3                                                         /*!< SCU SFSP8_8: EPD Position           */
+#define SCU_SFSP8_8_EPD_Msk                                   (0x01UL << SCU_SFSP8_8_EPD_Pos)                           /*!< SCU SFSP8_8: EPD Mask               */
+#define SCU_SFSP8_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_8: EPUN Position          */
+#define SCU_SFSP8_8_EPUN_Msk                                  (0x01UL << SCU_SFSP8_8_EPUN_Pos)                          /*!< SCU SFSP8_8: EPUN Mask              */
+#define SCU_SFSP8_8_EHS_Pos                                   5                                                         /*!< SCU SFSP8_8: EHS Position           */
+#define SCU_SFSP8_8_EHS_Msk                                   (0x01UL << SCU_SFSP8_8_EHS_Pos)                           /*!< SCU SFSP8_8: EHS Mask               */
+#define SCU_SFSP8_8_EZI_Pos                                   6                                                         /*!< SCU SFSP8_8: EZI Position           */
+#define SCU_SFSP8_8_EZI_Msk                                   (0x01UL << SCU_SFSP8_8_EZI_Pos)                           /*!< SCU SFSP8_8: EZI Mask               */
+#define SCU_SFSP8_8_EHD_Pos                                   8                                                         /*!< SCU SFSP8_8: EHD Position           */
+#define SCU_SFSP8_8_EHD_Msk                                   (0x03UL << SCU_SFSP8_8_EHD_Pos)                           /*!< SCU SFSP8_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_0  ------------------------------------------
+#define SCU_SFSP9_0_MODE_Pos                                  0                                                         /*!< SCU SFSP9_0: MODE Position          */
+#define SCU_SFSP9_0_MODE_Msk                                  (0x07UL << SCU_SFSP9_0_MODE_Pos)                          /*!< SCU SFSP9_0: MODE Mask              */
+#define SCU_SFSP9_0_EPD_Pos                                   3                                                         /*!< SCU SFSP9_0: EPD Position           */
+#define SCU_SFSP9_0_EPD_Msk                                   (0x01UL << SCU_SFSP9_0_EPD_Pos)                           /*!< SCU SFSP9_0: EPD Mask               */
+#define SCU_SFSP9_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_0: EPUN Position          */
+#define SCU_SFSP9_0_EPUN_Msk                                  (0x01UL << SCU_SFSP9_0_EPUN_Pos)                          /*!< SCU SFSP9_0: EPUN Mask              */
+#define SCU_SFSP9_0_EHS_Pos                                   5                                                         /*!< SCU SFSP9_0: EHS Position           */
+#define SCU_SFSP9_0_EHS_Msk                                   (0x01UL << SCU_SFSP9_0_EHS_Pos)                           /*!< SCU SFSP9_0: EHS Mask               */
+#define SCU_SFSP9_0_EZI_Pos                                   6                                                         /*!< SCU SFSP9_0: EZI Position           */
+#define SCU_SFSP9_0_EZI_Msk                                   (0x01UL << SCU_SFSP9_0_EZI_Pos)                           /*!< SCU SFSP9_0: EZI Mask               */
+#define SCU_SFSP9_0_EHD_Pos                                   8                                                         /*!< SCU SFSP9_0: EHD Position           */
+#define SCU_SFSP9_0_EHD_Msk                                   (0x03UL << SCU_SFSP9_0_EHD_Pos)                           /*!< SCU SFSP9_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_1  ------------------------------------------
+#define SCU_SFSP9_1_MODE_Pos                                  0                                                         /*!< SCU SFSP9_1: MODE Position          */
+#define SCU_SFSP9_1_MODE_Msk                                  (0x07UL << SCU_SFSP9_1_MODE_Pos)                          /*!< SCU SFSP9_1: MODE Mask              */
+#define SCU_SFSP9_1_EPD_Pos                                   3                                                         /*!< SCU SFSP9_1: EPD Position           */
+#define SCU_SFSP9_1_EPD_Msk                                   (0x01UL << SCU_SFSP9_1_EPD_Pos)                           /*!< SCU SFSP9_1: EPD Mask               */
+#define SCU_SFSP9_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_1: EPUN Position          */
+#define SCU_SFSP9_1_EPUN_Msk                                  (0x01UL << SCU_SFSP9_1_EPUN_Pos)                          /*!< SCU SFSP9_1: EPUN Mask              */
+#define SCU_SFSP9_1_EHS_Pos                                   5                                                         /*!< SCU SFSP9_1: EHS Position           */
+#define SCU_SFSP9_1_EHS_Msk                                   (0x01UL << SCU_SFSP9_1_EHS_Pos)                           /*!< SCU SFSP9_1: EHS Mask               */
+#define SCU_SFSP9_1_EZI_Pos                                   6                                                         /*!< SCU SFSP9_1: EZI Position           */
+#define SCU_SFSP9_1_EZI_Msk                                   (0x01UL << SCU_SFSP9_1_EZI_Pos)                           /*!< SCU SFSP9_1: EZI Mask               */
+#define SCU_SFSP9_1_EHD_Pos                                   8                                                         /*!< SCU SFSP9_1: EHD Position           */
+#define SCU_SFSP9_1_EHD_Msk                                   (0x03UL << SCU_SFSP9_1_EHD_Pos)                           /*!< SCU SFSP9_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_2  ------------------------------------------
+#define SCU_SFSP9_2_MODE_Pos                                  0                                                         /*!< SCU SFSP9_2: MODE Position          */
+#define SCU_SFSP9_2_MODE_Msk                                  (0x07UL << SCU_SFSP9_2_MODE_Pos)                          /*!< SCU SFSP9_2: MODE Mask              */
+#define SCU_SFSP9_2_EPD_Pos                                   3                                                         /*!< SCU SFSP9_2: EPD Position           */
+#define SCU_SFSP9_2_EPD_Msk                                   (0x01UL << SCU_SFSP9_2_EPD_Pos)                           /*!< SCU SFSP9_2: EPD Mask               */
+#define SCU_SFSP9_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_2: EPUN Position          */
+#define SCU_SFSP9_2_EPUN_Msk                                  (0x01UL << SCU_SFSP9_2_EPUN_Pos)                          /*!< SCU SFSP9_2: EPUN Mask              */
+#define SCU_SFSP9_2_EHS_Pos                                   5                                                         /*!< SCU SFSP9_2: EHS Position           */
+#define SCU_SFSP9_2_EHS_Msk                                   (0x01UL << SCU_SFSP9_2_EHS_Pos)                           /*!< SCU SFSP9_2: EHS Mask               */
+#define SCU_SFSP9_2_EZI_Pos                                   6                                                         /*!< SCU SFSP9_2: EZI Position           */
+#define SCU_SFSP9_2_EZI_Msk                                   (0x01UL << SCU_SFSP9_2_EZI_Pos)                           /*!< SCU SFSP9_2: EZI Mask               */
+#define SCU_SFSP9_2_EHD_Pos                                   8                                                         /*!< SCU SFSP9_2: EHD Position           */
+#define SCU_SFSP9_2_EHD_Msk                                   (0x03UL << SCU_SFSP9_2_EHD_Pos)                           /*!< SCU SFSP9_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_3  ------------------------------------------
+#define SCU_SFSP9_3_MODE_Pos                                  0                                                         /*!< SCU SFSP9_3: MODE Position          */
+#define SCU_SFSP9_3_MODE_Msk                                  (0x07UL << SCU_SFSP9_3_MODE_Pos)                          /*!< SCU SFSP9_3: MODE Mask              */
+#define SCU_SFSP9_3_EPD_Pos                                   3                                                         /*!< SCU SFSP9_3: EPD Position           */
+#define SCU_SFSP9_3_EPD_Msk                                   (0x01UL << SCU_SFSP9_3_EPD_Pos)                           /*!< SCU SFSP9_3: EPD Mask               */
+#define SCU_SFSP9_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_3: EPUN Position          */
+#define SCU_SFSP9_3_EPUN_Msk                                  (0x01UL << SCU_SFSP9_3_EPUN_Pos)                          /*!< SCU SFSP9_3: EPUN Mask              */
+#define SCU_SFSP9_3_EHS_Pos                                   5                                                         /*!< SCU SFSP9_3: EHS Position           */
+#define SCU_SFSP9_3_EHS_Msk                                   (0x01UL << SCU_SFSP9_3_EHS_Pos)                           /*!< SCU SFSP9_3: EHS Mask               */
+#define SCU_SFSP9_3_EZI_Pos                                   6                                                         /*!< SCU SFSP9_3: EZI Position           */
+#define SCU_SFSP9_3_EZI_Msk                                   (0x01UL << SCU_SFSP9_3_EZI_Pos)                           /*!< SCU SFSP9_3: EZI Mask               */
+#define SCU_SFSP9_3_EHD_Pos                                   8                                                         /*!< SCU SFSP9_3: EHD Position           */
+#define SCU_SFSP9_3_EHD_Msk                                   (0x03UL << SCU_SFSP9_3_EHD_Pos)                           /*!< SCU SFSP9_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_4  ------------------------------------------
+#define SCU_SFSP9_4_MODE_Pos                                  0                                                         /*!< SCU SFSP9_4: MODE Position          */
+#define SCU_SFSP9_4_MODE_Msk                                  (0x07UL << SCU_SFSP9_4_MODE_Pos)                          /*!< SCU SFSP9_4: MODE Mask              */
+#define SCU_SFSP9_4_EPD_Pos                                   3                                                         /*!< SCU SFSP9_4: EPD Position           */
+#define SCU_SFSP9_4_EPD_Msk                                   (0x01UL << SCU_SFSP9_4_EPD_Pos)                           /*!< SCU SFSP9_4: EPD Mask               */
+#define SCU_SFSP9_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_4: EPUN Position          */
+#define SCU_SFSP9_4_EPUN_Msk                                  (0x01UL << SCU_SFSP9_4_EPUN_Pos)                          /*!< SCU SFSP9_4: EPUN Mask              */
+#define SCU_SFSP9_4_EHS_Pos                                   5                                                         /*!< SCU SFSP9_4: EHS Position           */
+#define SCU_SFSP9_4_EHS_Msk                                   (0x01UL << SCU_SFSP9_4_EHS_Pos)                           /*!< SCU SFSP9_4: EHS Mask               */
+#define SCU_SFSP9_4_EZI_Pos                                   6                                                         /*!< SCU SFSP9_4: EZI Position           */
+#define SCU_SFSP9_4_EZI_Msk                                   (0x01UL << SCU_SFSP9_4_EZI_Pos)                           /*!< SCU SFSP9_4: EZI Mask               */
+#define SCU_SFSP9_4_EHD_Pos                                   8                                                         /*!< SCU SFSP9_4: EHD Position           */
+#define SCU_SFSP9_4_EHD_Msk                                   (0x03UL << SCU_SFSP9_4_EHD_Pos)                           /*!< SCU SFSP9_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_5  ------------------------------------------
+#define SCU_SFSP9_5_MODE_Pos                                  0                                                         /*!< SCU SFSP9_5: MODE Position          */
+#define SCU_SFSP9_5_MODE_Msk                                  (0x07UL << SCU_SFSP9_5_MODE_Pos)                          /*!< SCU SFSP9_5: MODE Mask              */
+#define SCU_SFSP9_5_EPD_Pos                                   3                                                         /*!< SCU SFSP9_5: EPD Position           */
+#define SCU_SFSP9_5_EPD_Msk                                   (0x01UL << SCU_SFSP9_5_EPD_Pos)                           /*!< SCU SFSP9_5: EPD Mask               */
+#define SCU_SFSP9_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_5: EPUN Position          */
+#define SCU_SFSP9_5_EPUN_Msk                                  (0x01UL << SCU_SFSP9_5_EPUN_Pos)                          /*!< SCU SFSP9_5: EPUN Mask              */
+#define SCU_SFSP9_5_EHS_Pos                                   5                                                         /*!< SCU SFSP9_5: EHS Position           */
+#define SCU_SFSP9_5_EHS_Msk                                   (0x01UL << SCU_SFSP9_5_EHS_Pos)                           /*!< SCU SFSP9_5: EHS Mask               */
+#define SCU_SFSP9_5_EZI_Pos                                   6                                                         /*!< SCU SFSP9_5: EZI Position           */
+#define SCU_SFSP9_5_EZI_Msk                                   (0x01UL << SCU_SFSP9_5_EZI_Pos)                           /*!< SCU SFSP9_5: EZI Mask               */
+#define SCU_SFSP9_5_EHD_Pos                                   8                                                         /*!< SCU SFSP9_5: EHD Position           */
+#define SCU_SFSP9_5_EHD_Msk                                   (0x03UL << SCU_SFSP9_5_EHD_Pos)                           /*!< SCU SFSP9_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_6  ------------------------------------------
+#define SCU_SFSP9_6_MODE_Pos                                  0                                                         /*!< SCU SFSP9_6: MODE Position          */
+#define SCU_SFSP9_6_MODE_Msk                                  (0x07UL << SCU_SFSP9_6_MODE_Pos)                          /*!< SCU SFSP9_6: MODE Mask              */
+#define SCU_SFSP9_6_EPD_Pos                                   3                                                         /*!< SCU SFSP9_6: EPD Position           */
+#define SCU_SFSP9_6_EPD_Msk                                   (0x01UL << SCU_SFSP9_6_EPD_Pos)                           /*!< SCU SFSP9_6: EPD Mask               */
+#define SCU_SFSP9_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_6: EPUN Position          */
+#define SCU_SFSP9_6_EPUN_Msk                                  (0x01UL << SCU_SFSP9_6_EPUN_Pos)                          /*!< SCU SFSP9_6: EPUN Mask              */
+#define SCU_SFSP9_6_EHS_Pos                                   5                                                         /*!< SCU SFSP9_6: EHS Position           */
+#define SCU_SFSP9_6_EHS_Msk                                   (0x01UL << SCU_SFSP9_6_EHS_Pos)                           /*!< SCU SFSP9_6: EHS Mask               */
+#define SCU_SFSP9_6_EZI_Pos                                   6                                                         /*!< SCU SFSP9_6: EZI Position           */
+#define SCU_SFSP9_6_EZI_Msk                                   (0x01UL << SCU_SFSP9_6_EZI_Pos)                           /*!< SCU SFSP9_6: EZI Mask               */
+#define SCU_SFSP9_6_EHD_Pos                                   8                                                         /*!< SCU SFSP9_6: EHD Position           */
+#define SCU_SFSP9_6_EHD_Msk                                   (0x03UL << SCU_SFSP9_6_EHD_Pos)                           /*!< SCU SFSP9_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_0  ------------------------------------------
+#define SCU_SFSPA_0_MODE_Pos                                  0                                                         /*!< SCU SFSPA_0: MODE Position          */
+#define SCU_SFSPA_0_MODE_Msk                                  (0x07UL << SCU_SFSPA_0_MODE_Pos)                          /*!< SCU SFSPA_0: MODE Mask              */
+#define SCU_SFSPA_0_EPD_Pos                                   3                                                         /*!< SCU SFSPA_0: EPD Position           */
+#define SCU_SFSPA_0_EPD_Msk                                   (0x01UL << SCU_SFSPA_0_EPD_Pos)                           /*!< SCU SFSPA_0: EPD Mask               */
+#define SCU_SFSPA_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_0: EPUN Position          */
+#define SCU_SFSPA_0_EPUN_Msk                                  (0x01UL << SCU_SFSPA_0_EPUN_Pos)                          /*!< SCU SFSPA_0: EPUN Mask              */
+#define SCU_SFSPA_0_EHS_Pos                                   5                                                         /*!< SCU SFSPA_0: EHS Position           */
+#define SCU_SFSPA_0_EHS_Msk                                   (0x01UL << SCU_SFSPA_0_EHS_Pos)                           /*!< SCU SFSPA_0: EHS Mask               */
+#define SCU_SFSPA_0_EZI_Pos                                   6                                                         /*!< SCU SFSPA_0: EZI Position           */
+#define SCU_SFSPA_0_EZI_Msk                                   (0x01UL << SCU_SFSPA_0_EZI_Pos)                           /*!< SCU SFSPA_0: EZI Mask               */
+#define SCU_SFSPA_0_EHD_Pos                                   8                                                         /*!< SCU SFSPA_0: EHD Position           */
+#define SCU_SFSPA_0_EHD_Msk                                   (0x03UL << SCU_SFSPA_0_EHD_Pos)                           /*!< SCU SFSPA_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_1  ------------------------------------------
+#define SCU_SFSPA_1_MODE_Pos                                  0                                                         /*!< SCU SFSPA_1: MODE Position          */
+#define SCU_SFSPA_1_MODE_Msk                                  (0x07UL << SCU_SFSPA_1_MODE_Pos)                          /*!< SCU SFSPA_1: MODE Mask              */
+#define SCU_SFSPA_1_EPD_Pos                                   3                                                         /*!< SCU SFSPA_1: EPD Position           */
+#define SCU_SFSPA_1_EPD_Msk                                   (0x01UL << SCU_SFSPA_1_EPD_Pos)                           /*!< SCU SFSPA_1: EPD Mask               */
+#define SCU_SFSPA_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_1: EPUN Position          */
+#define SCU_SFSPA_1_EPUN_Msk                                  (0x01UL << SCU_SFSPA_1_EPUN_Pos)                          /*!< SCU SFSPA_1: EPUN Mask              */
+#define SCU_SFSPA_1_EHS_Pos                                   5                                                         /*!< SCU SFSPA_1: EHS Position           */
+#define SCU_SFSPA_1_EHS_Msk                                   (0x01UL << SCU_SFSPA_1_EHS_Pos)                           /*!< SCU SFSPA_1: EHS Mask               */
+#define SCU_SFSPA_1_EZI_Pos                                   6                                                         /*!< SCU SFSPA_1: EZI Position           */
+#define SCU_SFSPA_1_EZI_Msk                                   (0x01UL << SCU_SFSPA_1_EZI_Pos)                           /*!< SCU SFSPA_1: EZI Mask               */
+#define SCU_SFSPA_1_EHD_Pos                                   8                                                         /*!< SCU SFSPA_1: EHD Position           */
+#define SCU_SFSPA_1_EHD_Msk                                   (0x03UL << SCU_SFSPA_1_EHD_Pos)                           /*!< SCU SFSPA_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_2  ------------------------------------------
+#define SCU_SFSPA_2_MODE_Pos                                  0                                                         /*!< SCU SFSPA_2: MODE Position          */
+#define SCU_SFSPA_2_MODE_Msk                                  (0x07UL << SCU_SFSPA_2_MODE_Pos)                          /*!< SCU SFSPA_2: MODE Mask              */
+#define SCU_SFSPA_2_EPD_Pos                                   3                                                         /*!< SCU SFSPA_2: EPD Position           */
+#define SCU_SFSPA_2_EPD_Msk                                   (0x01UL << SCU_SFSPA_2_EPD_Pos)                           /*!< SCU SFSPA_2: EPD Mask               */
+#define SCU_SFSPA_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_2: EPUN Position          */
+#define SCU_SFSPA_2_EPUN_Msk                                  (0x01UL << SCU_SFSPA_2_EPUN_Pos)                          /*!< SCU SFSPA_2: EPUN Mask              */
+#define SCU_SFSPA_2_EHS_Pos                                   5                                                         /*!< SCU SFSPA_2: EHS Position           */
+#define SCU_SFSPA_2_EHS_Msk                                   (0x01UL << SCU_SFSPA_2_EHS_Pos)                           /*!< SCU SFSPA_2: EHS Mask               */
+#define SCU_SFSPA_2_EZI_Pos                                   6                                                         /*!< SCU SFSPA_2: EZI Position           */
+#define SCU_SFSPA_2_EZI_Msk                                   (0x01UL << SCU_SFSPA_2_EZI_Pos)                           /*!< SCU SFSPA_2: EZI Mask               */
+#define SCU_SFSPA_2_EHD_Pos                                   8                                                         /*!< SCU SFSPA_2: EHD Position           */
+#define SCU_SFSPA_2_EHD_Msk                                   (0x03UL << SCU_SFSPA_2_EHD_Pos)                           /*!< SCU SFSPA_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_3  ------------------------------------------
+#define SCU_SFSPA_3_MODE_Pos                                  0                                                         /*!< SCU SFSPA_3: MODE Position          */
+#define SCU_SFSPA_3_MODE_Msk                                  (0x07UL << SCU_SFSPA_3_MODE_Pos)                          /*!< SCU SFSPA_3: MODE Mask              */
+#define SCU_SFSPA_3_EPD_Pos                                   3                                                         /*!< SCU SFSPA_3: EPD Position           */
+#define SCU_SFSPA_3_EPD_Msk                                   (0x01UL << SCU_SFSPA_3_EPD_Pos)                           /*!< SCU SFSPA_3: EPD Mask               */
+#define SCU_SFSPA_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_3: EPUN Position          */
+#define SCU_SFSPA_3_EPUN_Msk                                  (0x01UL << SCU_SFSPA_3_EPUN_Pos)                          /*!< SCU SFSPA_3: EPUN Mask              */
+#define SCU_SFSPA_3_EHS_Pos                                   5                                                         /*!< SCU SFSPA_3: EHS Position           */
+#define SCU_SFSPA_3_EHS_Msk                                   (0x01UL << SCU_SFSPA_3_EHS_Pos)                           /*!< SCU SFSPA_3: EHS Mask               */
+#define SCU_SFSPA_3_EZI_Pos                                   6                                                         /*!< SCU SFSPA_3: EZI Position           */
+#define SCU_SFSPA_3_EZI_Msk                                   (0x01UL << SCU_SFSPA_3_EZI_Pos)                           /*!< SCU SFSPA_3: EZI Mask               */
+#define SCU_SFSPA_3_EHD_Pos                                   8                                                         /*!< SCU SFSPA_3: EHD Position           */
+#define SCU_SFSPA_3_EHD_Msk                                   (0x03UL << SCU_SFSPA_3_EHD_Pos)                           /*!< SCU SFSPA_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_4  ------------------------------------------
+#define SCU_SFSPA_4_MODE_Pos                                  0                                                         /*!< SCU SFSPA_4: MODE Position          */
+#define SCU_SFSPA_4_MODE_Msk                                  (0x07UL << SCU_SFSPA_4_MODE_Pos)                          /*!< SCU SFSPA_4: MODE Mask              */
+#define SCU_SFSPA_4_EPD_Pos                                   3                                                         /*!< SCU SFSPA_4: EPD Position           */
+#define SCU_SFSPA_4_EPD_Msk                                   (0x01UL << SCU_SFSPA_4_EPD_Pos)                           /*!< SCU SFSPA_4: EPD Mask               */
+#define SCU_SFSPA_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_4: EPUN Position          */
+#define SCU_SFSPA_4_EPUN_Msk                                  (0x01UL << SCU_SFSPA_4_EPUN_Pos)                          /*!< SCU SFSPA_4: EPUN Mask              */
+#define SCU_SFSPA_4_EHS_Pos                                   5                                                         /*!< SCU SFSPA_4: EHS Position           */
+#define SCU_SFSPA_4_EHS_Msk                                   (0x01UL << SCU_SFSPA_4_EHS_Pos)                           /*!< SCU SFSPA_4: EHS Mask               */
+#define SCU_SFSPA_4_EZI_Pos                                   6                                                         /*!< SCU SFSPA_4: EZI Position           */
+#define SCU_SFSPA_4_EZI_Msk                                   (0x01UL << SCU_SFSPA_4_EZI_Pos)                           /*!< SCU SFSPA_4: EZI Mask               */
+#define SCU_SFSPA_4_EHD_Pos                                   8                                                         /*!< SCU SFSPA_4: EHD Position           */
+#define SCU_SFSPA_4_EHD_Msk                                   (0x03UL << SCU_SFSPA_4_EHD_Pos)                           /*!< SCU SFSPA_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_0  ------------------------------------------
+#define SCU_SFSPB_0_MODE_Pos                                  0                                                         /*!< SCU SFSPB_0: MODE Position          */
+#define SCU_SFSPB_0_MODE_Msk                                  (0x07UL << SCU_SFSPB_0_MODE_Pos)                          /*!< SCU SFSPB_0: MODE Mask              */
+#define SCU_SFSPB_0_EPD_Pos                                   3                                                         /*!< SCU SFSPB_0: EPD Position           */
+#define SCU_SFSPB_0_EPD_Msk                                   (0x01UL << SCU_SFSPB_0_EPD_Pos)                           /*!< SCU SFSPB_0: EPD Mask               */
+#define SCU_SFSPB_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_0: EPUN Position          */
+#define SCU_SFSPB_0_EPUN_Msk                                  (0x01UL << SCU_SFSPB_0_EPUN_Pos)                          /*!< SCU SFSPB_0: EPUN Mask              */
+#define SCU_SFSPB_0_EHS_Pos                                   5                                                         /*!< SCU SFSPB_0: EHS Position           */
+#define SCU_SFSPB_0_EHS_Msk                                   (0x01UL << SCU_SFSPB_0_EHS_Pos)                           /*!< SCU SFSPB_0: EHS Mask               */
+#define SCU_SFSPB_0_EZI_Pos                                   6                                                         /*!< SCU SFSPB_0: EZI Position           */
+#define SCU_SFSPB_0_EZI_Msk                                   (0x01UL << SCU_SFSPB_0_EZI_Pos)                           /*!< SCU SFSPB_0: EZI Mask               */
+#define SCU_SFSPB_0_EHD_Pos                                   8                                                         /*!< SCU SFSPB_0: EHD Position           */
+#define SCU_SFSPB_0_EHD_Msk                                   (0x03UL << SCU_SFSPB_0_EHD_Pos)                           /*!< SCU SFSPB_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_1  ------------------------------------------
+#define SCU_SFSPB_1_MODE_Pos                                  0                                                         /*!< SCU SFSPB_1: MODE Position          */
+#define SCU_SFSPB_1_MODE_Msk                                  (0x07UL << SCU_SFSPB_1_MODE_Pos)                          /*!< SCU SFSPB_1: MODE Mask              */
+#define SCU_SFSPB_1_EPD_Pos                                   3                                                         /*!< SCU SFSPB_1: EPD Position           */
+#define SCU_SFSPB_1_EPD_Msk                                   (0x01UL << SCU_SFSPB_1_EPD_Pos)                           /*!< SCU SFSPB_1: EPD Mask               */
+#define SCU_SFSPB_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_1: EPUN Position          */
+#define SCU_SFSPB_1_EPUN_Msk                                  (0x01UL << SCU_SFSPB_1_EPUN_Pos)                          /*!< SCU SFSPB_1: EPUN Mask              */
+#define SCU_SFSPB_1_EHS_Pos                                   5                                                         /*!< SCU SFSPB_1: EHS Position           */
+#define SCU_SFSPB_1_EHS_Msk                                   (0x01UL << SCU_SFSPB_1_EHS_Pos)                           /*!< SCU SFSPB_1: EHS Mask               */
+#define SCU_SFSPB_1_EZI_Pos                                   6                                                         /*!< SCU SFSPB_1: EZI Position           */
+#define SCU_SFSPB_1_EZI_Msk                                   (0x01UL << SCU_SFSPB_1_EZI_Pos)                           /*!< SCU SFSPB_1: EZI Mask               */
+#define SCU_SFSPB_1_EHD_Pos                                   8                                                         /*!< SCU SFSPB_1: EHD Position           */
+#define SCU_SFSPB_1_EHD_Msk                                   (0x03UL << SCU_SFSPB_1_EHD_Pos)                           /*!< SCU SFSPB_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_2  ------------------------------------------
+#define SCU_SFSPB_2_MODE_Pos                                  0                                                         /*!< SCU SFSPB_2: MODE Position          */
+#define SCU_SFSPB_2_MODE_Msk                                  (0x07UL << SCU_SFSPB_2_MODE_Pos)                          /*!< SCU SFSPB_2: MODE Mask              */
+#define SCU_SFSPB_2_EPD_Pos                                   3                                                         /*!< SCU SFSPB_2: EPD Position           */
+#define SCU_SFSPB_2_EPD_Msk                                   (0x01UL << SCU_SFSPB_2_EPD_Pos)                           /*!< SCU SFSPB_2: EPD Mask               */
+#define SCU_SFSPB_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_2: EPUN Position          */
+#define SCU_SFSPB_2_EPUN_Msk                                  (0x01UL << SCU_SFSPB_2_EPUN_Pos)                          /*!< SCU SFSPB_2: EPUN Mask              */
+#define SCU_SFSPB_2_EHS_Pos                                   5                                                         /*!< SCU SFSPB_2: EHS Position           */
+#define SCU_SFSPB_2_EHS_Msk                                   (0x01UL << SCU_SFSPB_2_EHS_Pos)                           /*!< SCU SFSPB_2: EHS Mask               */
+#define SCU_SFSPB_2_EZI_Pos                                   6                                                         /*!< SCU SFSPB_2: EZI Position           */
+#define SCU_SFSPB_2_EZI_Msk                                   (0x01UL << SCU_SFSPB_2_EZI_Pos)                           /*!< SCU SFSPB_2: EZI Mask               */
+#define SCU_SFSPB_2_EHD_Pos                                   8                                                         /*!< SCU SFSPB_2: EHD Position           */
+#define SCU_SFSPB_2_EHD_Msk                                   (0x03UL << SCU_SFSPB_2_EHD_Pos)                           /*!< SCU SFSPB_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_3  ------------------------------------------
+#define SCU_SFSPB_3_MODE_Pos                                  0                                                         /*!< SCU SFSPB_3: MODE Position          */
+#define SCU_SFSPB_3_MODE_Msk                                  (0x07UL << SCU_SFSPB_3_MODE_Pos)                          /*!< SCU SFSPB_3: MODE Mask              */
+#define SCU_SFSPB_3_EPD_Pos                                   3                                                         /*!< SCU SFSPB_3: EPD Position           */
+#define SCU_SFSPB_3_EPD_Msk                                   (0x01UL << SCU_SFSPB_3_EPD_Pos)                           /*!< SCU SFSPB_3: EPD Mask               */
+#define SCU_SFSPB_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_3: EPUN Position          */
+#define SCU_SFSPB_3_EPUN_Msk                                  (0x01UL << SCU_SFSPB_3_EPUN_Pos)                          /*!< SCU SFSPB_3: EPUN Mask              */
+#define SCU_SFSPB_3_EHS_Pos                                   5                                                         /*!< SCU SFSPB_3: EHS Position           */
+#define SCU_SFSPB_3_EHS_Msk                                   (0x01UL << SCU_SFSPB_3_EHS_Pos)                           /*!< SCU SFSPB_3: EHS Mask               */
+#define SCU_SFSPB_3_EZI_Pos                                   6                                                         /*!< SCU SFSPB_3: EZI Position           */
+#define SCU_SFSPB_3_EZI_Msk                                   (0x01UL << SCU_SFSPB_3_EZI_Pos)                           /*!< SCU SFSPB_3: EZI Mask               */
+#define SCU_SFSPB_3_EHD_Pos                                   8                                                         /*!< SCU SFSPB_3: EHD Position           */
+#define SCU_SFSPB_3_EHD_Msk                                   (0x03UL << SCU_SFSPB_3_EHD_Pos)                           /*!< SCU SFSPB_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_4  ------------------------------------------
+#define SCU_SFSPB_4_MODE_Pos                                  0                                                         /*!< SCU SFSPB_4: MODE Position          */
+#define SCU_SFSPB_4_MODE_Msk                                  (0x07UL << SCU_SFSPB_4_MODE_Pos)                          /*!< SCU SFSPB_4: MODE Mask              */
+#define SCU_SFSPB_4_EPD_Pos                                   3                                                         /*!< SCU SFSPB_4: EPD Position           */
+#define SCU_SFSPB_4_EPD_Msk                                   (0x01UL << SCU_SFSPB_4_EPD_Pos)                           /*!< SCU SFSPB_4: EPD Mask               */
+#define SCU_SFSPB_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_4: EPUN Position          */
+#define SCU_SFSPB_4_EPUN_Msk                                  (0x01UL << SCU_SFSPB_4_EPUN_Pos)                          /*!< SCU SFSPB_4: EPUN Mask              */
+#define SCU_SFSPB_4_EHS_Pos                                   5                                                         /*!< SCU SFSPB_4: EHS Position           */
+#define SCU_SFSPB_4_EHS_Msk                                   (0x01UL << SCU_SFSPB_4_EHS_Pos)                           /*!< SCU SFSPB_4: EHS Mask               */
+#define SCU_SFSPB_4_EZI_Pos                                   6                                                         /*!< SCU SFSPB_4: EZI Position           */
+#define SCU_SFSPB_4_EZI_Msk                                   (0x01UL << SCU_SFSPB_4_EZI_Pos)                           /*!< SCU SFSPB_4: EZI Mask               */
+#define SCU_SFSPB_4_EHD_Pos                                   8                                                         /*!< SCU SFSPB_4: EHD Position           */
+#define SCU_SFSPB_4_EHD_Msk                                   (0x03UL << SCU_SFSPB_4_EHD_Pos)                           /*!< SCU SFSPB_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_5  ------------------------------------------
+#define SCU_SFSPB_5_MODE_Pos                                  0                                                         /*!< SCU SFSPB_5: MODE Position          */
+#define SCU_SFSPB_5_MODE_Msk                                  (0x07UL << SCU_SFSPB_5_MODE_Pos)                          /*!< SCU SFSPB_5: MODE Mask              */
+#define SCU_SFSPB_5_EPD_Pos                                   3                                                         /*!< SCU SFSPB_5: EPD Position           */
+#define SCU_SFSPB_5_EPD_Msk                                   (0x01UL << SCU_SFSPB_5_EPD_Pos)                           /*!< SCU SFSPB_5: EPD Mask               */
+#define SCU_SFSPB_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_5: EPUN Position          */
+#define SCU_SFSPB_5_EPUN_Msk                                  (0x01UL << SCU_SFSPB_5_EPUN_Pos)                          /*!< SCU SFSPB_5: EPUN Mask              */
+#define SCU_SFSPB_5_EHS_Pos                                   5                                                         /*!< SCU SFSPB_5: EHS Position           */
+#define SCU_SFSPB_5_EHS_Msk                                   (0x01UL << SCU_SFSPB_5_EHS_Pos)                           /*!< SCU SFSPB_5: EHS Mask               */
+#define SCU_SFSPB_5_EZI_Pos                                   6                                                         /*!< SCU SFSPB_5: EZI Position           */
+#define SCU_SFSPB_5_EZI_Msk                                   (0x01UL << SCU_SFSPB_5_EZI_Pos)                           /*!< SCU SFSPB_5: EZI Mask               */
+#define SCU_SFSPB_5_EHD_Pos                                   8                                                         /*!< SCU SFSPB_5: EHD Position           */
+#define SCU_SFSPB_5_EHD_Msk                                   (0x03UL << SCU_SFSPB_5_EHD_Pos)                           /*!< SCU SFSPB_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_6  ------------------------------------------
+#define SCU_SFSPB_6_MODE_Pos                                  0                                                         /*!< SCU SFSPB_6: MODE Position          */
+#define SCU_SFSPB_6_MODE_Msk                                  (0x07UL << SCU_SFSPB_6_MODE_Pos)                          /*!< SCU SFSPB_6: MODE Mask              */
+#define SCU_SFSPB_6_EPD_Pos                                   3                                                         /*!< SCU SFSPB_6: EPD Position           */
+#define SCU_SFSPB_6_EPD_Msk                                   (0x01UL << SCU_SFSPB_6_EPD_Pos)                           /*!< SCU SFSPB_6: EPD Mask               */
+#define SCU_SFSPB_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_6: EPUN Position          */
+#define SCU_SFSPB_6_EPUN_Msk                                  (0x01UL << SCU_SFSPB_6_EPUN_Pos)                          /*!< SCU SFSPB_6: EPUN Mask              */
+#define SCU_SFSPB_6_EHS_Pos                                   5                                                         /*!< SCU SFSPB_6: EHS Position           */
+#define SCU_SFSPB_6_EHS_Msk                                   (0x01UL << SCU_SFSPB_6_EHS_Pos)                           /*!< SCU SFSPB_6: EHS Mask               */
+#define SCU_SFSPB_6_EZI_Pos                                   6                                                         /*!< SCU SFSPB_6: EZI Position           */
+#define SCU_SFSPB_6_EZI_Msk                                   (0x01UL << SCU_SFSPB_6_EZI_Pos)                           /*!< SCU SFSPB_6: EZI Mask               */
+#define SCU_SFSPB_6_EHD_Pos                                   8                                                         /*!< SCU SFSPB_6: EHD Position           */
+#define SCU_SFSPB_6_EHD_Msk                                   (0x03UL << SCU_SFSPB_6_EHD_Pos)                           /*!< SCU SFSPB_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_0  ------------------------------------------
+#define SCU_SFSPC_0_MODE_Pos                                  0                                                         /*!< SCU SFSPC_0: MODE Position          */
+#define SCU_SFSPC_0_MODE_Msk                                  (0x07UL << SCU_SFSPC_0_MODE_Pos)                          /*!< SCU SFSPC_0: MODE Mask              */
+#define SCU_SFSPC_0_EPD_Pos                                   3                                                         /*!< SCU SFSPC_0: EPD Position           */
+#define SCU_SFSPC_0_EPD_Msk                                   (0x01UL << SCU_SFSPC_0_EPD_Pos)                           /*!< SCU SFSPC_0: EPD Mask               */
+#define SCU_SFSPC_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_0: EPUN Position          */
+#define SCU_SFSPC_0_EPUN_Msk                                  (0x01UL << SCU_SFSPC_0_EPUN_Pos)                          /*!< SCU SFSPC_0: EPUN Mask              */
+#define SCU_SFSPC_0_EHS_Pos                                   5                                                         /*!< SCU SFSPC_0: EHS Position           */
+#define SCU_SFSPC_0_EHS_Msk                                   (0x01UL << SCU_SFSPC_0_EHS_Pos)                           /*!< SCU SFSPC_0: EHS Mask               */
+#define SCU_SFSPC_0_EZI_Pos                                   6                                                         /*!< SCU SFSPC_0: EZI Position           */
+#define SCU_SFSPC_0_EZI_Msk                                   (0x01UL << SCU_SFSPC_0_EZI_Pos)                           /*!< SCU SFSPC_0: EZI Mask               */
+#define SCU_SFSPC_0_EHD_Pos                                   8                                                         /*!< SCU SFSPC_0: EHD Position           */
+#define SCU_SFSPC_0_EHD_Msk                                   (0x03UL << SCU_SFSPC_0_EHD_Pos)                           /*!< SCU SFSPC_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_1  ------------------------------------------
+#define SCU_SFSPC_1_MODE_Pos                                  0                                                         /*!< SCU SFSPC_1: MODE Position          */
+#define SCU_SFSPC_1_MODE_Msk                                  (0x07UL << SCU_SFSPC_1_MODE_Pos)                          /*!< SCU SFSPC_1: MODE Mask              */
+#define SCU_SFSPC_1_EPD_Pos                                   3                                                         /*!< SCU SFSPC_1: EPD Position           */
+#define SCU_SFSPC_1_EPD_Msk                                   (0x01UL << SCU_SFSPC_1_EPD_Pos)                           /*!< SCU SFSPC_1: EPD Mask               */
+#define SCU_SFSPC_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_1: EPUN Position          */
+#define SCU_SFSPC_1_EPUN_Msk                                  (0x01UL << SCU_SFSPC_1_EPUN_Pos)                          /*!< SCU SFSPC_1: EPUN Mask              */
+#define SCU_SFSPC_1_EHS_Pos                                   5                                                         /*!< SCU SFSPC_1: EHS Position           */
+#define SCU_SFSPC_1_EHS_Msk                                   (0x01UL << SCU_SFSPC_1_EHS_Pos)                           /*!< SCU SFSPC_1: EHS Mask               */
+#define SCU_SFSPC_1_EZI_Pos                                   6                                                         /*!< SCU SFSPC_1: EZI Position           */
+#define SCU_SFSPC_1_EZI_Msk                                   (0x01UL << SCU_SFSPC_1_EZI_Pos)                           /*!< SCU SFSPC_1: EZI Mask               */
+#define SCU_SFSPC_1_EHD_Pos                                   8                                                         /*!< SCU SFSPC_1: EHD Position           */
+#define SCU_SFSPC_1_EHD_Msk                                   (0x03UL << SCU_SFSPC_1_EHD_Pos)                           /*!< SCU SFSPC_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_2  ------------------------------------------
+#define SCU_SFSPC_2_MODE_Pos                                  0                                                         /*!< SCU SFSPC_2: MODE Position          */
+#define SCU_SFSPC_2_MODE_Msk                                  (0x07UL << SCU_SFSPC_2_MODE_Pos)                          /*!< SCU SFSPC_2: MODE Mask              */
+#define SCU_SFSPC_2_EPD_Pos                                   3                                                         /*!< SCU SFSPC_2: EPD Position           */
+#define SCU_SFSPC_2_EPD_Msk                                   (0x01UL << SCU_SFSPC_2_EPD_Pos)                           /*!< SCU SFSPC_2: EPD Mask               */
+#define SCU_SFSPC_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_2: EPUN Position          */
+#define SCU_SFSPC_2_EPUN_Msk                                  (0x01UL << SCU_SFSPC_2_EPUN_Pos)                          /*!< SCU SFSPC_2: EPUN Mask              */
+#define SCU_SFSPC_2_EHS_Pos                                   5                                                         /*!< SCU SFSPC_2: EHS Position           */
+#define SCU_SFSPC_2_EHS_Msk                                   (0x01UL << SCU_SFSPC_2_EHS_Pos)                           /*!< SCU SFSPC_2: EHS Mask               */
+#define SCU_SFSPC_2_EZI_Pos                                   6                                                         /*!< SCU SFSPC_2: EZI Position           */
+#define SCU_SFSPC_2_EZI_Msk                                   (0x01UL << SCU_SFSPC_2_EZI_Pos)                           /*!< SCU SFSPC_2: EZI Mask               */
+#define SCU_SFSPC_2_EHD_Pos                                   8                                                         /*!< SCU SFSPC_2: EHD Position           */
+#define SCU_SFSPC_2_EHD_Msk                                   (0x03UL << SCU_SFSPC_2_EHD_Pos)                           /*!< SCU SFSPC_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_3  ------------------------------------------
+#define SCU_SFSPC_3_MODE_Pos                                  0                                                         /*!< SCU SFSPC_3: MODE Position          */
+#define SCU_SFSPC_3_MODE_Msk                                  (0x07UL << SCU_SFSPC_3_MODE_Pos)                          /*!< SCU SFSPC_3: MODE Mask              */
+#define SCU_SFSPC_3_EPD_Pos                                   3                                                         /*!< SCU SFSPC_3: EPD Position           */
+#define SCU_SFSPC_3_EPD_Msk                                   (0x01UL << SCU_SFSPC_3_EPD_Pos)                           /*!< SCU SFSPC_3: EPD Mask               */
+#define SCU_SFSPC_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_3: EPUN Position          */
+#define SCU_SFSPC_3_EPUN_Msk                                  (0x01UL << SCU_SFSPC_3_EPUN_Pos)                          /*!< SCU SFSPC_3: EPUN Mask              */
+#define SCU_SFSPC_3_EHS_Pos                                   5                                                         /*!< SCU SFSPC_3: EHS Position           */
+#define SCU_SFSPC_3_EHS_Msk                                   (0x01UL << SCU_SFSPC_3_EHS_Pos)                           /*!< SCU SFSPC_3: EHS Mask               */
+#define SCU_SFSPC_3_EZI_Pos                                   6                                                         /*!< SCU SFSPC_3: EZI Position           */
+#define SCU_SFSPC_3_EZI_Msk                                   (0x01UL << SCU_SFSPC_3_EZI_Pos)                           /*!< SCU SFSPC_3: EZI Mask               */
+#define SCU_SFSPC_3_EHD_Pos                                   8                                                         /*!< SCU SFSPC_3: EHD Position           */
+#define SCU_SFSPC_3_EHD_Msk                                   (0x03UL << SCU_SFSPC_3_EHD_Pos)                           /*!< SCU SFSPC_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_4  ------------------------------------------
+#define SCU_SFSPC_4_MODE_Pos                                  0                                                         /*!< SCU SFSPC_4: MODE Position          */
+#define SCU_SFSPC_4_MODE_Msk                                  (0x07UL << SCU_SFSPC_4_MODE_Pos)                          /*!< SCU SFSPC_4: MODE Mask              */
+#define SCU_SFSPC_4_EPD_Pos                                   3                                                         /*!< SCU SFSPC_4: EPD Position           */
+#define SCU_SFSPC_4_EPD_Msk                                   (0x01UL << SCU_SFSPC_4_EPD_Pos)                           /*!< SCU SFSPC_4: EPD Mask               */
+#define SCU_SFSPC_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_4: EPUN Position          */
+#define SCU_SFSPC_4_EPUN_Msk                                  (0x01UL << SCU_SFSPC_4_EPUN_Pos)                          /*!< SCU SFSPC_4: EPUN Mask              */
+#define SCU_SFSPC_4_EHS_Pos                                   5                                                         /*!< SCU SFSPC_4: EHS Position           */
+#define SCU_SFSPC_4_EHS_Msk                                   (0x01UL << SCU_SFSPC_4_EHS_Pos)                           /*!< SCU SFSPC_4: EHS Mask               */
+#define SCU_SFSPC_4_EZI_Pos                                   6                                                         /*!< SCU SFSPC_4: EZI Position           */
+#define SCU_SFSPC_4_EZI_Msk                                   (0x01UL << SCU_SFSPC_4_EZI_Pos)                           /*!< SCU SFSPC_4: EZI Mask               */
+#define SCU_SFSPC_4_EHD_Pos                                   8                                                         /*!< SCU SFSPC_4: EHD Position           */
+#define SCU_SFSPC_4_EHD_Msk                                   (0x03UL << SCU_SFSPC_4_EHD_Pos)                           /*!< SCU SFSPC_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_5  ------------------------------------------
+#define SCU_SFSPC_5_MODE_Pos                                  0                                                         /*!< SCU SFSPC_5: MODE Position          */
+#define SCU_SFSPC_5_MODE_Msk                                  (0x07UL << SCU_SFSPC_5_MODE_Pos)                          /*!< SCU SFSPC_5: MODE Mask              */
+#define SCU_SFSPC_5_EPD_Pos                                   3                                                         /*!< SCU SFSPC_5: EPD Position           */
+#define SCU_SFSPC_5_EPD_Msk                                   (0x01UL << SCU_SFSPC_5_EPD_Pos)                           /*!< SCU SFSPC_5: EPD Mask               */
+#define SCU_SFSPC_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_5: EPUN Position          */
+#define SCU_SFSPC_5_EPUN_Msk                                  (0x01UL << SCU_SFSPC_5_EPUN_Pos)                          /*!< SCU SFSPC_5: EPUN Mask              */
+#define SCU_SFSPC_5_EHS_Pos                                   5                                                         /*!< SCU SFSPC_5: EHS Position           */
+#define SCU_SFSPC_5_EHS_Msk                                   (0x01UL << SCU_SFSPC_5_EHS_Pos)                           /*!< SCU SFSPC_5: EHS Mask               */
+#define SCU_SFSPC_5_EZI_Pos                                   6                                                         /*!< SCU SFSPC_5: EZI Position           */
+#define SCU_SFSPC_5_EZI_Msk                                   (0x01UL << SCU_SFSPC_5_EZI_Pos)                           /*!< SCU SFSPC_5: EZI Mask               */
+#define SCU_SFSPC_5_EHD_Pos                                   8                                                         /*!< SCU SFSPC_5: EHD Position           */
+#define SCU_SFSPC_5_EHD_Msk                                   (0x03UL << SCU_SFSPC_5_EHD_Pos)                           /*!< SCU SFSPC_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_6  ------------------------------------------
+#define SCU_SFSPC_6_MODE_Pos                                  0                                                         /*!< SCU SFSPC_6: MODE Position          */
+#define SCU_SFSPC_6_MODE_Msk                                  (0x07UL << SCU_SFSPC_6_MODE_Pos)                          /*!< SCU SFSPC_6: MODE Mask              */
+#define SCU_SFSPC_6_EPD_Pos                                   3                                                         /*!< SCU SFSPC_6: EPD Position           */
+#define SCU_SFSPC_6_EPD_Msk                                   (0x01UL << SCU_SFSPC_6_EPD_Pos)                           /*!< SCU SFSPC_6: EPD Mask               */
+#define SCU_SFSPC_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_6: EPUN Position          */
+#define SCU_SFSPC_6_EPUN_Msk                                  (0x01UL << SCU_SFSPC_6_EPUN_Pos)                          /*!< SCU SFSPC_6: EPUN Mask              */
+#define SCU_SFSPC_6_EHS_Pos                                   5                                                         /*!< SCU SFSPC_6: EHS Position           */
+#define SCU_SFSPC_6_EHS_Msk                                   (0x01UL << SCU_SFSPC_6_EHS_Pos)                           /*!< SCU SFSPC_6: EHS Mask               */
+#define SCU_SFSPC_6_EZI_Pos                                   6                                                         /*!< SCU SFSPC_6: EZI Position           */
+#define SCU_SFSPC_6_EZI_Msk                                   (0x01UL << SCU_SFSPC_6_EZI_Pos)                           /*!< SCU SFSPC_6: EZI Mask               */
+#define SCU_SFSPC_6_EHD_Pos                                   8                                                         /*!< SCU SFSPC_6: EHD Position           */
+#define SCU_SFSPC_6_EHD_Msk                                   (0x03UL << SCU_SFSPC_6_EHD_Pos)                           /*!< SCU SFSPC_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_7  ------------------------------------------
+#define SCU_SFSPC_7_MODE_Pos                                  0                                                         /*!< SCU SFSPC_7: MODE Position          */
+#define SCU_SFSPC_7_MODE_Msk                                  (0x07UL << SCU_SFSPC_7_MODE_Pos)                          /*!< SCU SFSPC_7: MODE Mask              */
+#define SCU_SFSPC_7_EPD_Pos                                   3                                                         /*!< SCU SFSPC_7: EPD Position           */
+#define SCU_SFSPC_7_EPD_Msk                                   (0x01UL << SCU_SFSPC_7_EPD_Pos)                           /*!< SCU SFSPC_7: EPD Mask               */
+#define SCU_SFSPC_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_7: EPUN Position          */
+#define SCU_SFSPC_7_EPUN_Msk                                  (0x01UL << SCU_SFSPC_7_EPUN_Pos)                          /*!< SCU SFSPC_7: EPUN Mask              */
+#define SCU_SFSPC_7_EHS_Pos                                   5                                                         /*!< SCU SFSPC_7: EHS Position           */
+#define SCU_SFSPC_7_EHS_Msk                                   (0x01UL << SCU_SFSPC_7_EHS_Pos)                           /*!< SCU SFSPC_7: EHS Mask               */
+#define SCU_SFSPC_7_EZI_Pos                                   6                                                         /*!< SCU SFSPC_7: EZI Position           */
+#define SCU_SFSPC_7_EZI_Msk                                   (0x01UL << SCU_SFSPC_7_EZI_Pos)                           /*!< SCU SFSPC_7: EZI Mask               */
+#define SCU_SFSPC_7_EHD_Pos                                   8                                                         /*!< SCU SFSPC_7: EHD Position           */
+#define SCU_SFSPC_7_EHD_Msk                                   (0x03UL << SCU_SFSPC_7_EHD_Pos)                           /*!< SCU SFSPC_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_8  ------------------------------------------
+#define SCU_SFSPC_8_MODE_Pos                                  0                                                         /*!< SCU SFSPC_8: MODE Position          */
+#define SCU_SFSPC_8_MODE_Msk                                  (0x07UL << SCU_SFSPC_8_MODE_Pos)                          /*!< SCU SFSPC_8: MODE Mask              */
+#define SCU_SFSPC_8_EPD_Pos                                   3                                                         /*!< SCU SFSPC_8: EPD Position           */
+#define SCU_SFSPC_8_EPD_Msk                                   (0x01UL << SCU_SFSPC_8_EPD_Pos)                           /*!< SCU SFSPC_8: EPD Mask               */
+#define SCU_SFSPC_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_8: EPUN Position          */
+#define SCU_SFSPC_8_EPUN_Msk                                  (0x01UL << SCU_SFSPC_8_EPUN_Pos)                          /*!< SCU SFSPC_8: EPUN Mask              */
+#define SCU_SFSPC_8_EHS_Pos                                   5                                                         /*!< SCU SFSPC_8: EHS Position           */
+#define SCU_SFSPC_8_EHS_Msk                                   (0x01UL << SCU_SFSPC_8_EHS_Pos)                           /*!< SCU SFSPC_8: EHS Mask               */
+#define SCU_SFSPC_8_EZI_Pos                                   6                                                         /*!< SCU SFSPC_8: EZI Position           */
+#define SCU_SFSPC_8_EZI_Msk                                   (0x01UL << SCU_SFSPC_8_EZI_Pos)                           /*!< SCU SFSPC_8: EZI Mask               */
+#define SCU_SFSPC_8_EHD_Pos                                   8                                                         /*!< SCU SFSPC_8: EHD Position           */
+#define SCU_SFSPC_8_EHD_Msk                                   (0x03UL << SCU_SFSPC_8_EHD_Pos)                           /*!< SCU SFSPC_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_9  ------------------------------------------
+#define SCU_SFSPC_9_MODE_Pos                                  0                                                         /*!< SCU SFSPC_9: MODE Position          */
+#define SCU_SFSPC_9_MODE_Msk                                  (0x07UL << SCU_SFSPC_9_MODE_Pos)                          /*!< SCU SFSPC_9: MODE Mask              */
+#define SCU_SFSPC_9_EPD_Pos                                   3                                                         /*!< SCU SFSPC_9: EPD Position           */
+#define SCU_SFSPC_9_EPD_Msk                                   (0x01UL << SCU_SFSPC_9_EPD_Pos)                           /*!< SCU SFSPC_9: EPD Mask               */
+#define SCU_SFSPC_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_9: EPUN Position          */
+#define SCU_SFSPC_9_EPUN_Msk                                  (0x01UL << SCU_SFSPC_9_EPUN_Pos)                          /*!< SCU SFSPC_9: EPUN Mask              */
+#define SCU_SFSPC_9_EHS_Pos                                   5                                                         /*!< SCU SFSPC_9: EHS Position           */
+#define SCU_SFSPC_9_EHS_Msk                                   (0x01UL << SCU_SFSPC_9_EHS_Pos)                           /*!< SCU SFSPC_9: EHS Mask               */
+#define SCU_SFSPC_9_EZI_Pos                                   6                                                         /*!< SCU SFSPC_9: EZI Position           */
+#define SCU_SFSPC_9_EZI_Msk                                   (0x01UL << SCU_SFSPC_9_EZI_Pos)                           /*!< SCU SFSPC_9: EZI Mask               */
+#define SCU_SFSPC_9_EHD_Pos                                   8                                                         /*!< SCU SFSPC_9: EHD Position           */
+#define SCU_SFSPC_9_EHD_Msk                                   (0x03UL << SCU_SFSPC_9_EHD_Pos)                           /*!< SCU SFSPC_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPC_10  ------------------------------------------
+#define SCU_SFSPC_10_MODE_Pos                                 0                                                         /*!< SCU SFSPC_10: MODE Position         */
+#define SCU_SFSPC_10_MODE_Msk                                 (0x07UL << SCU_SFSPC_10_MODE_Pos)                         /*!< SCU SFSPC_10: MODE Mask             */
+#define SCU_SFSPC_10_EPD_Pos                                  3                                                         /*!< SCU SFSPC_10: EPD Position          */
+#define SCU_SFSPC_10_EPD_Msk                                  (0x01UL << SCU_SFSPC_10_EPD_Pos)                          /*!< SCU SFSPC_10: EPD Mask              */
+#define SCU_SFSPC_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_10: EPUN Position         */
+#define SCU_SFSPC_10_EPUN_Msk                                 (0x01UL << SCU_SFSPC_10_EPUN_Pos)                         /*!< SCU SFSPC_10: EPUN Mask             */
+#define SCU_SFSPC_10_EHS_Pos                                  5                                                         /*!< SCU SFSPC_10: EHS Position          */
+#define SCU_SFSPC_10_EHS_Msk                                  (0x01UL << SCU_SFSPC_10_EHS_Pos)                          /*!< SCU SFSPC_10: EHS Mask              */
+#define SCU_SFSPC_10_EZI_Pos                                  6                                                         /*!< SCU SFSPC_10: EZI Position          */
+#define SCU_SFSPC_10_EZI_Msk                                  (0x01UL << SCU_SFSPC_10_EZI_Pos)                          /*!< SCU SFSPC_10: EZI Mask              */
+#define SCU_SFSPC_10_EHD_Pos                                  8                                                         /*!< SCU SFSPC_10: EHD Position          */
+#define SCU_SFSPC_10_EHD_Msk                                  (0x03UL << SCU_SFSPC_10_EHD_Pos)                          /*!< SCU SFSPC_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_11  ------------------------------------------
+#define SCU_SFSPC_11_MODE_Pos                                 0                                                         /*!< SCU SFSPC_11: MODE Position         */
+#define SCU_SFSPC_11_MODE_Msk                                 (0x07UL << SCU_SFSPC_11_MODE_Pos)                         /*!< SCU SFSPC_11: MODE Mask             */
+#define SCU_SFSPC_11_EPD_Pos                                  3                                                         /*!< SCU SFSPC_11: EPD Position          */
+#define SCU_SFSPC_11_EPD_Msk                                  (0x01UL << SCU_SFSPC_11_EPD_Pos)                          /*!< SCU SFSPC_11: EPD Mask              */
+#define SCU_SFSPC_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_11: EPUN Position         */
+#define SCU_SFSPC_11_EPUN_Msk                                 (0x01UL << SCU_SFSPC_11_EPUN_Pos)                         /*!< SCU SFSPC_11: EPUN Mask             */
+#define SCU_SFSPC_11_EHS_Pos                                  5                                                         /*!< SCU SFSPC_11: EHS Position          */
+#define SCU_SFSPC_11_EHS_Msk                                  (0x01UL << SCU_SFSPC_11_EHS_Pos)                          /*!< SCU SFSPC_11: EHS Mask              */
+#define SCU_SFSPC_11_EZI_Pos                                  6                                                         /*!< SCU SFSPC_11: EZI Position          */
+#define SCU_SFSPC_11_EZI_Msk                                  (0x01UL << SCU_SFSPC_11_EZI_Pos)                          /*!< SCU SFSPC_11: EZI Mask              */
+#define SCU_SFSPC_11_EHD_Pos                                  8                                                         /*!< SCU SFSPC_11: EHD Position          */
+#define SCU_SFSPC_11_EHD_Msk                                  (0x03UL << SCU_SFSPC_11_EHD_Pos)                          /*!< SCU SFSPC_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_12  ------------------------------------------
+#define SCU_SFSPC_12_MODE_Pos                                 0                                                         /*!< SCU SFSPC_12: MODE Position         */
+#define SCU_SFSPC_12_MODE_Msk                                 (0x07UL << SCU_SFSPC_12_MODE_Pos)                         /*!< SCU SFSPC_12: MODE Mask             */
+#define SCU_SFSPC_12_EPD_Pos                                  3                                                         /*!< SCU SFSPC_12: EPD Position          */
+#define SCU_SFSPC_12_EPD_Msk                                  (0x01UL << SCU_SFSPC_12_EPD_Pos)                          /*!< SCU SFSPC_12: EPD Mask              */
+#define SCU_SFSPC_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_12: EPUN Position         */
+#define SCU_SFSPC_12_EPUN_Msk                                 (0x01UL << SCU_SFSPC_12_EPUN_Pos)                         /*!< SCU SFSPC_12: EPUN Mask             */
+#define SCU_SFSPC_12_EHS_Pos                                  5                                                         /*!< SCU SFSPC_12: EHS Position          */
+#define SCU_SFSPC_12_EHS_Msk                                  (0x01UL << SCU_SFSPC_12_EHS_Pos)                          /*!< SCU SFSPC_12: EHS Mask              */
+#define SCU_SFSPC_12_EZI_Pos                                  6                                                         /*!< SCU SFSPC_12: EZI Position          */
+#define SCU_SFSPC_12_EZI_Msk                                  (0x01UL << SCU_SFSPC_12_EZI_Pos)                          /*!< SCU SFSPC_12: EZI Mask              */
+#define SCU_SFSPC_12_EHD_Pos                                  8                                                         /*!< SCU SFSPC_12: EHD Position          */
+#define SCU_SFSPC_12_EHD_Msk                                  (0x03UL << SCU_SFSPC_12_EHD_Pos)                          /*!< SCU SFSPC_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_13  ------------------------------------------
+#define SCU_SFSPC_13_MODE_Pos                                 0                                                         /*!< SCU SFSPC_13: MODE Position         */
+#define SCU_SFSPC_13_MODE_Msk                                 (0x07UL << SCU_SFSPC_13_MODE_Pos)                         /*!< SCU SFSPC_13: MODE Mask             */
+#define SCU_SFSPC_13_EPD_Pos                                  3                                                         /*!< SCU SFSPC_13: EPD Position          */
+#define SCU_SFSPC_13_EPD_Msk                                  (0x01UL << SCU_SFSPC_13_EPD_Pos)                          /*!< SCU SFSPC_13: EPD Mask              */
+#define SCU_SFSPC_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_13: EPUN Position         */
+#define SCU_SFSPC_13_EPUN_Msk                                 (0x01UL << SCU_SFSPC_13_EPUN_Pos)                         /*!< SCU SFSPC_13: EPUN Mask             */
+#define SCU_SFSPC_13_EHS_Pos                                  5                                                         /*!< SCU SFSPC_13: EHS Position          */
+#define SCU_SFSPC_13_EHS_Msk                                  (0x01UL << SCU_SFSPC_13_EHS_Pos)                          /*!< SCU SFSPC_13: EHS Mask              */
+#define SCU_SFSPC_13_EZI_Pos                                  6                                                         /*!< SCU SFSPC_13: EZI Position          */
+#define SCU_SFSPC_13_EZI_Msk                                  (0x01UL << SCU_SFSPC_13_EZI_Pos)                          /*!< SCU SFSPC_13: EZI Mask              */
+#define SCU_SFSPC_13_EHD_Pos                                  8                                                         /*!< SCU SFSPC_13: EHD Position          */
+#define SCU_SFSPC_13_EHD_Msk                                  (0x03UL << SCU_SFSPC_13_EHD_Pos)                          /*!< SCU SFSPC_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_14  ------------------------------------------
+#define SCU_SFSPC_14_MODE_Pos                                 0                                                         /*!< SCU SFSPC_14: MODE Position         */
+#define SCU_SFSPC_14_MODE_Msk                                 (0x07UL << SCU_SFSPC_14_MODE_Pos)                         /*!< SCU SFSPC_14: MODE Mask             */
+#define SCU_SFSPC_14_EPD_Pos                                  3                                                         /*!< SCU SFSPC_14: EPD Position          */
+#define SCU_SFSPC_14_EPD_Msk                                  (0x01UL << SCU_SFSPC_14_EPD_Pos)                          /*!< SCU SFSPC_14: EPD Mask              */
+#define SCU_SFSPC_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_14: EPUN Position         */
+#define SCU_SFSPC_14_EPUN_Msk                                 (0x01UL << SCU_SFSPC_14_EPUN_Pos)                         /*!< SCU SFSPC_14: EPUN Mask             */
+#define SCU_SFSPC_14_EHS_Pos                                  5                                                         /*!< SCU SFSPC_14: EHS Position          */
+#define SCU_SFSPC_14_EHS_Msk                                  (0x01UL << SCU_SFSPC_14_EHS_Pos)                          /*!< SCU SFSPC_14: EHS Mask              */
+#define SCU_SFSPC_14_EZI_Pos                                  6                                                         /*!< SCU SFSPC_14: EZI Position          */
+#define SCU_SFSPC_14_EZI_Msk                                  (0x01UL << SCU_SFSPC_14_EZI_Pos)                          /*!< SCU SFSPC_14: EZI Mask              */
+#define SCU_SFSPC_14_EHD_Pos                                  8                                                         /*!< SCU SFSPC_14: EHD Position          */
+#define SCU_SFSPC_14_EHD_Msk                                  (0x03UL << SCU_SFSPC_14_EHD_Pos)                          /*!< SCU SFSPC_14: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSPD_0  ------------------------------------------
+#define SCU_SFSPD_0_MODE_Pos                                  0                                                         /*!< SCU SFSPD_0: MODE Position          */
+#define SCU_SFSPD_0_MODE_Msk                                  (0x07UL << SCU_SFSPD_0_MODE_Pos)                          /*!< SCU SFSPD_0: MODE Mask              */
+#define SCU_SFSPD_0_EPD_Pos                                   3                                                         /*!< SCU SFSPD_0: EPD Position           */
+#define SCU_SFSPD_0_EPD_Msk                                   (0x01UL << SCU_SFSPD_0_EPD_Pos)                           /*!< SCU SFSPD_0: EPD Mask               */
+#define SCU_SFSPD_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_0: EPUN Position          */
+#define SCU_SFSPD_0_EPUN_Msk                                  (0x01UL << SCU_SFSPD_0_EPUN_Pos)                          /*!< SCU SFSPD_0: EPUN Mask              */
+#define SCU_SFSPD_0_EHS_Pos                                   5                                                         /*!< SCU SFSPD_0: EHS Position           */
+#define SCU_SFSPD_0_EHS_Msk                                   (0x01UL << SCU_SFSPD_0_EHS_Pos)                           /*!< SCU SFSPD_0: EHS Mask               */
+#define SCU_SFSPD_0_EZI_Pos                                   6                                                         /*!< SCU SFSPD_0: EZI Position           */
+#define SCU_SFSPD_0_EZI_Msk                                   (0x01UL << SCU_SFSPD_0_EZI_Pos)                           /*!< SCU SFSPD_0: EZI Mask               */
+#define SCU_SFSPD_0_EHD_Pos                                   8                                                         /*!< SCU SFSPD_0: EHD Position           */
+#define SCU_SFSPD_0_EHD_Msk                                   (0x03UL << SCU_SFSPD_0_EHD_Pos)                           /*!< SCU SFSPD_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_1  ------------------------------------------
+#define SCU_SFSPD_1_MODE_Pos                                  0                                                         /*!< SCU SFSPD_1: MODE Position          */
+#define SCU_SFSPD_1_MODE_Msk                                  (0x07UL << SCU_SFSPD_1_MODE_Pos)                          /*!< SCU SFSPD_1: MODE Mask              */
+#define SCU_SFSPD_1_EPD_Pos                                   3                                                         /*!< SCU SFSPD_1: EPD Position           */
+#define SCU_SFSPD_1_EPD_Msk                                   (0x01UL << SCU_SFSPD_1_EPD_Pos)                           /*!< SCU SFSPD_1: EPD Mask               */
+#define SCU_SFSPD_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_1: EPUN Position          */
+#define SCU_SFSPD_1_EPUN_Msk                                  (0x01UL << SCU_SFSPD_1_EPUN_Pos)                          /*!< SCU SFSPD_1: EPUN Mask              */
+#define SCU_SFSPD_1_EHS_Pos                                   5                                                         /*!< SCU SFSPD_1: EHS Position           */
+#define SCU_SFSPD_1_EHS_Msk                                   (0x01UL << SCU_SFSPD_1_EHS_Pos)                           /*!< SCU SFSPD_1: EHS Mask               */
+#define SCU_SFSPD_1_EZI_Pos                                   6                                                         /*!< SCU SFSPD_1: EZI Position           */
+#define SCU_SFSPD_1_EZI_Msk                                   (0x01UL << SCU_SFSPD_1_EZI_Pos)                           /*!< SCU SFSPD_1: EZI Mask               */
+#define SCU_SFSPD_1_EHD_Pos                                   8                                                         /*!< SCU SFSPD_1: EHD Position           */
+#define SCU_SFSPD_1_EHD_Msk                                   (0x03UL << SCU_SFSPD_1_EHD_Pos)                           /*!< SCU SFSPD_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_2  ------------------------------------------
+#define SCU_SFSPD_2_MODE_Pos                                  0                                                         /*!< SCU SFSPD_2: MODE Position          */
+#define SCU_SFSPD_2_MODE_Msk                                  (0x07UL << SCU_SFSPD_2_MODE_Pos)                          /*!< SCU SFSPD_2: MODE Mask              */
+#define SCU_SFSPD_2_EPD_Pos                                   3                                                         /*!< SCU SFSPD_2: EPD Position           */
+#define SCU_SFSPD_2_EPD_Msk                                   (0x01UL << SCU_SFSPD_2_EPD_Pos)                           /*!< SCU SFSPD_2: EPD Mask               */
+#define SCU_SFSPD_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_2: EPUN Position          */
+#define SCU_SFSPD_2_EPUN_Msk                                  (0x01UL << SCU_SFSPD_2_EPUN_Pos)                          /*!< SCU SFSPD_2: EPUN Mask              */
+#define SCU_SFSPD_2_EHS_Pos                                   5                                                         /*!< SCU SFSPD_2: EHS Position           */
+#define SCU_SFSPD_2_EHS_Msk                                   (0x01UL << SCU_SFSPD_2_EHS_Pos)                           /*!< SCU SFSPD_2: EHS Mask               */
+#define SCU_SFSPD_2_EZI_Pos                                   6                                                         /*!< SCU SFSPD_2: EZI Position           */
+#define SCU_SFSPD_2_EZI_Msk                                   (0x01UL << SCU_SFSPD_2_EZI_Pos)                           /*!< SCU SFSPD_2: EZI Mask               */
+#define SCU_SFSPD_2_EHD_Pos                                   8                                                         /*!< SCU SFSPD_2: EHD Position           */
+#define SCU_SFSPD_2_EHD_Msk                                   (0x03UL << SCU_SFSPD_2_EHD_Pos)                           /*!< SCU SFSPD_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_3  ------------------------------------------
+#define SCU_SFSPD_3_MODE_Pos                                  0                                                         /*!< SCU SFSPD_3: MODE Position          */
+#define SCU_SFSPD_3_MODE_Msk                                  (0x07UL << SCU_SFSPD_3_MODE_Pos)                          /*!< SCU SFSPD_3: MODE Mask              */
+#define SCU_SFSPD_3_EPD_Pos                                   3                                                         /*!< SCU SFSPD_3: EPD Position           */
+#define SCU_SFSPD_3_EPD_Msk                                   (0x01UL << SCU_SFSPD_3_EPD_Pos)                           /*!< SCU SFSPD_3: EPD Mask               */
+#define SCU_SFSPD_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_3: EPUN Position          */
+#define SCU_SFSPD_3_EPUN_Msk                                  (0x01UL << SCU_SFSPD_3_EPUN_Pos)                          /*!< SCU SFSPD_3: EPUN Mask              */
+#define SCU_SFSPD_3_EHS_Pos                                   5                                                         /*!< SCU SFSPD_3: EHS Position           */
+#define SCU_SFSPD_3_EHS_Msk                                   (0x01UL << SCU_SFSPD_3_EHS_Pos)                           /*!< SCU SFSPD_3: EHS Mask               */
+#define SCU_SFSPD_3_EZI_Pos                                   6                                                         /*!< SCU SFSPD_3: EZI Position           */
+#define SCU_SFSPD_3_EZI_Msk                                   (0x01UL << SCU_SFSPD_3_EZI_Pos)                           /*!< SCU SFSPD_3: EZI Mask               */
+#define SCU_SFSPD_3_EHD_Pos                                   8                                                         /*!< SCU SFSPD_3: EHD Position           */
+#define SCU_SFSPD_3_EHD_Msk                                   (0x03UL << SCU_SFSPD_3_EHD_Pos)                           /*!< SCU SFSPD_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_4  ------------------------------------------
+#define SCU_SFSPD_4_MODE_Pos                                  0                                                         /*!< SCU SFSPD_4: MODE Position          */
+#define SCU_SFSPD_4_MODE_Msk                                  (0x07UL << SCU_SFSPD_4_MODE_Pos)                          /*!< SCU SFSPD_4: MODE Mask              */
+#define SCU_SFSPD_4_EPD_Pos                                   3                                                         /*!< SCU SFSPD_4: EPD Position           */
+#define SCU_SFSPD_4_EPD_Msk                                   (0x01UL << SCU_SFSPD_4_EPD_Pos)                           /*!< SCU SFSPD_4: EPD Mask               */
+#define SCU_SFSPD_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_4: EPUN Position          */
+#define SCU_SFSPD_4_EPUN_Msk                                  (0x01UL << SCU_SFSPD_4_EPUN_Pos)                          /*!< SCU SFSPD_4: EPUN Mask              */
+#define SCU_SFSPD_4_EHS_Pos                                   5                                                         /*!< SCU SFSPD_4: EHS Position           */
+#define SCU_SFSPD_4_EHS_Msk                                   (0x01UL << SCU_SFSPD_4_EHS_Pos)                           /*!< SCU SFSPD_4: EHS Mask               */
+#define SCU_SFSPD_4_EZI_Pos                                   6                                                         /*!< SCU SFSPD_4: EZI Position           */
+#define SCU_SFSPD_4_EZI_Msk                                   (0x01UL << SCU_SFSPD_4_EZI_Pos)                           /*!< SCU SFSPD_4: EZI Mask               */
+#define SCU_SFSPD_4_EHD_Pos                                   8                                                         /*!< SCU SFSPD_4: EHD Position           */
+#define SCU_SFSPD_4_EHD_Msk                                   (0x03UL << SCU_SFSPD_4_EHD_Pos)                           /*!< SCU SFSPD_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_5  ------------------------------------------
+#define SCU_SFSPD_5_MODE_Pos                                  0                                                         /*!< SCU SFSPD_5: MODE Position          */
+#define SCU_SFSPD_5_MODE_Msk                                  (0x07UL << SCU_SFSPD_5_MODE_Pos)                          /*!< SCU SFSPD_5: MODE Mask              */
+#define SCU_SFSPD_5_EPD_Pos                                   3                                                         /*!< SCU SFSPD_5: EPD Position           */
+#define SCU_SFSPD_5_EPD_Msk                                   (0x01UL << SCU_SFSPD_5_EPD_Pos)                           /*!< SCU SFSPD_5: EPD Mask               */
+#define SCU_SFSPD_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_5: EPUN Position          */
+#define SCU_SFSPD_5_EPUN_Msk                                  (0x01UL << SCU_SFSPD_5_EPUN_Pos)                          /*!< SCU SFSPD_5: EPUN Mask              */
+#define SCU_SFSPD_5_EHS_Pos                                   5                                                         /*!< SCU SFSPD_5: EHS Position           */
+#define SCU_SFSPD_5_EHS_Msk                                   (0x01UL << SCU_SFSPD_5_EHS_Pos)                           /*!< SCU SFSPD_5: EHS Mask               */
+#define SCU_SFSPD_5_EZI_Pos                                   6                                                         /*!< SCU SFSPD_5: EZI Position           */
+#define SCU_SFSPD_5_EZI_Msk                                   (0x01UL << SCU_SFSPD_5_EZI_Pos)                           /*!< SCU SFSPD_5: EZI Mask               */
+#define SCU_SFSPD_5_EHD_Pos                                   8                                                         /*!< SCU SFSPD_5: EHD Position           */
+#define SCU_SFSPD_5_EHD_Msk                                   (0x03UL << SCU_SFSPD_5_EHD_Pos)                           /*!< SCU SFSPD_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_6  ------------------------------------------
+#define SCU_SFSPD_6_MODE_Pos                                  0                                                         /*!< SCU SFSPD_6: MODE Position          */
+#define SCU_SFSPD_6_MODE_Msk                                  (0x07UL << SCU_SFSPD_6_MODE_Pos)                          /*!< SCU SFSPD_6: MODE Mask              */
+#define SCU_SFSPD_6_EPD_Pos                                   3                                                         /*!< SCU SFSPD_6: EPD Position           */
+#define SCU_SFSPD_6_EPD_Msk                                   (0x01UL << SCU_SFSPD_6_EPD_Pos)                           /*!< SCU SFSPD_6: EPD Mask               */
+#define SCU_SFSPD_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_6: EPUN Position          */
+#define SCU_SFSPD_6_EPUN_Msk                                  (0x01UL << SCU_SFSPD_6_EPUN_Pos)                          /*!< SCU SFSPD_6: EPUN Mask              */
+#define SCU_SFSPD_6_EHS_Pos                                   5                                                         /*!< SCU SFSPD_6: EHS Position           */
+#define SCU_SFSPD_6_EHS_Msk                                   (0x01UL << SCU_SFSPD_6_EHS_Pos)                           /*!< SCU SFSPD_6: EHS Mask               */
+#define SCU_SFSPD_6_EZI_Pos                                   6                                                         /*!< SCU SFSPD_6: EZI Position           */
+#define SCU_SFSPD_6_EZI_Msk                                   (0x01UL << SCU_SFSPD_6_EZI_Pos)                           /*!< SCU SFSPD_6: EZI Mask               */
+#define SCU_SFSPD_6_EHD_Pos                                   8                                                         /*!< SCU SFSPD_6: EHD Position           */
+#define SCU_SFSPD_6_EHD_Msk                                   (0x03UL << SCU_SFSPD_6_EHD_Pos)                           /*!< SCU SFSPD_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_7  ------------------------------------------
+#define SCU_SFSPD_7_MODE_Pos                                  0                                                         /*!< SCU SFSPD_7: MODE Position          */
+#define SCU_SFSPD_7_MODE_Msk                                  (0x07UL << SCU_SFSPD_7_MODE_Pos)                          /*!< SCU SFSPD_7: MODE Mask              */
+#define SCU_SFSPD_7_EPD_Pos                                   3                                                         /*!< SCU SFSPD_7: EPD Position           */
+#define SCU_SFSPD_7_EPD_Msk                                   (0x01UL << SCU_SFSPD_7_EPD_Pos)                           /*!< SCU SFSPD_7: EPD Mask               */
+#define SCU_SFSPD_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_7: EPUN Position          */
+#define SCU_SFSPD_7_EPUN_Msk                                  (0x01UL << SCU_SFSPD_7_EPUN_Pos)                          /*!< SCU SFSPD_7: EPUN Mask              */
+#define SCU_SFSPD_7_EHS_Pos                                   5                                                         /*!< SCU SFSPD_7: EHS Position           */
+#define SCU_SFSPD_7_EHS_Msk                                   (0x01UL << SCU_SFSPD_7_EHS_Pos)                           /*!< SCU SFSPD_7: EHS Mask               */
+#define SCU_SFSPD_7_EZI_Pos                                   6                                                         /*!< SCU SFSPD_7: EZI Position           */
+#define SCU_SFSPD_7_EZI_Msk                                   (0x01UL << SCU_SFSPD_7_EZI_Pos)                           /*!< SCU SFSPD_7: EZI Mask               */
+#define SCU_SFSPD_7_EHD_Pos                                   8                                                         /*!< SCU SFSPD_7: EHD Position           */
+#define SCU_SFSPD_7_EHD_Msk                                   (0x03UL << SCU_SFSPD_7_EHD_Pos)                           /*!< SCU SFSPD_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_8  ------------------------------------------
+#define SCU_SFSPD_8_MODE_Pos                                  0                                                         /*!< SCU SFSPD_8: MODE Position          */
+#define SCU_SFSPD_8_MODE_Msk                                  (0x07UL << SCU_SFSPD_8_MODE_Pos)                          /*!< SCU SFSPD_8: MODE Mask              */
+#define SCU_SFSPD_8_EPD_Pos                                   3                                                         /*!< SCU SFSPD_8: EPD Position           */
+#define SCU_SFSPD_8_EPD_Msk                                   (0x01UL << SCU_SFSPD_8_EPD_Pos)                           /*!< SCU SFSPD_8: EPD Mask               */
+#define SCU_SFSPD_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_8: EPUN Position          */
+#define SCU_SFSPD_8_EPUN_Msk                                  (0x01UL << SCU_SFSPD_8_EPUN_Pos)                          /*!< SCU SFSPD_8: EPUN Mask              */
+#define SCU_SFSPD_8_EHS_Pos                                   5                                                         /*!< SCU SFSPD_8: EHS Position           */
+#define SCU_SFSPD_8_EHS_Msk                                   (0x01UL << SCU_SFSPD_8_EHS_Pos)                           /*!< SCU SFSPD_8: EHS Mask               */
+#define SCU_SFSPD_8_EZI_Pos                                   6                                                         /*!< SCU SFSPD_8: EZI Position           */
+#define SCU_SFSPD_8_EZI_Msk                                   (0x01UL << SCU_SFSPD_8_EZI_Pos)                           /*!< SCU SFSPD_8: EZI Mask               */
+#define SCU_SFSPD_8_EHD_Pos                                   8                                                         /*!< SCU SFSPD_8: EHD Position           */
+#define SCU_SFSPD_8_EHD_Msk                                   (0x03UL << SCU_SFSPD_8_EHD_Pos)                           /*!< SCU SFSPD_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_9  ------------------------------------------
+#define SCU_SFSPD_9_MODE_Pos                                  0                                                         /*!< SCU SFSPD_9: MODE Position          */
+#define SCU_SFSPD_9_MODE_Msk                                  (0x07UL << SCU_SFSPD_9_MODE_Pos)                          /*!< SCU SFSPD_9: MODE Mask              */
+#define SCU_SFSPD_9_EPD_Pos                                   3                                                         /*!< SCU SFSPD_9: EPD Position           */
+#define SCU_SFSPD_9_EPD_Msk                                   (0x01UL << SCU_SFSPD_9_EPD_Pos)                           /*!< SCU SFSPD_9: EPD Mask               */
+#define SCU_SFSPD_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_9: EPUN Position          */
+#define SCU_SFSPD_9_EPUN_Msk                                  (0x01UL << SCU_SFSPD_9_EPUN_Pos)                          /*!< SCU SFSPD_9: EPUN Mask              */
+#define SCU_SFSPD_9_EHS_Pos                                   5                                                         /*!< SCU SFSPD_9: EHS Position           */
+#define SCU_SFSPD_9_EHS_Msk                                   (0x01UL << SCU_SFSPD_9_EHS_Pos)                           /*!< SCU SFSPD_9: EHS Mask               */
+#define SCU_SFSPD_9_EZI_Pos                                   6                                                         /*!< SCU SFSPD_9: EZI Position           */
+#define SCU_SFSPD_9_EZI_Msk                                   (0x01UL << SCU_SFSPD_9_EZI_Pos)                           /*!< SCU SFSPD_9: EZI Mask               */
+#define SCU_SFSPD_9_EHD_Pos                                   8                                                         /*!< SCU SFSPD_9: EHD Position           */
+#define SCU_SFSPD_9_EHD_Msk                                   (0x03UL << SCU_SFSPD_9_EHD_Pos)                           /*!< SCU SFSPD_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPD_10  ------------------------------------------
+#define SCU_SFSPD_10_MODE_Pos                                 0                                                         /*!< SCU SFSPD_10: MODE Position         */
+#define SCU_SFSPD_10_MODE_Msk                                 (0x07UL << SCU_SFSPD_10_MODE_Pos)                         /*!< SCU SFSPD_10: MODE Mask             */
+#define SCU_SFSPD_10_EPD_Pos                                  3                                                         /*!< SCU SFSPD_10: EPD Position          */
+#define SCU_SFSPD_10_EPD_Msk                                  (0x01UL << SCU_SFSPD_10_EPD_Pos)                          /*!< SCU SFSPD_10: EPD Mask              */
+#define SCU_SFSPD_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_10: EPUN Position         */
+#define SCU_SFSPD_10_EPUN_Msk                                 (0x01UL << SCU_SFSPD_10_EPUN_Pos)                         /*!< SCU SFSPD_10: EPUN Mask             */
+#define SCU_SFSPD_10_EHS_Pos                                  5                                                         /*!< SCU SFSPD_10: EHS Position          */
+#define SCU_SFSPD_10_EHS_Msk                                  (0x01UL << SCU_SFSPD_10_EHS_Pos)                          /*!< SCU SFSPD_10: EHS Mask              */
+#define SCU_SFSPD_10_EZI_Pos                                  6                                                         /*!< SCU SFSPD_10: EZI Position          */
+#define SCU_SFSPD_10_EZI_Msk                                  (0x01UL << SCU_SFSPD_10_EZI_Pos)                          /*!< SCU SFSPD_10: EZI Mask              */
+#define SCU_SFSPD_10_EHD_Pos                                  8                                                         /*!< SCU SFSPD_10: EHD Position          */
+#define SCU_SFSPD_10_EHD_Msk                                  (0x03UL << SCU_SFSPD_10_EHD_Pos)                          /*!< SCU SFSPD_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_11  ------------------------------------------
+#define SCU_SFSPD_11_MODE_Pos                                 0                                                         /*!< SCU SFSPD_11: MODE Position         */
+#define SCU_SFSPD_11_MODE_Msk                                 (0x07UL << SCU_SFSPD_11_MODE_Pos)                         /*!< SCU SFSPD_11: MODE Mask             */
+#define SCU_SFSPD_11_EPD_Pos                                  3                                                         /*!< SCU SFSPD_11: EPD Position          */
+#define SCU_SFSPD_11_EPD_Msk                                  (0x01UL << SCU_SFSPD_11_EPD_Pos)                          /*!< SCU SFSPD_11: EPD Mask              */
+#define SCU_SFSPD_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_11: EPUN Position         */
+#define SCU_SFSPD_11_EPUN_Msk                                 (0x01UL << SCU_SFSPD_11_EPUN_Pos)                         /*!< SCU SFSPD_11: EPUN Mask             */
+#define SCU_SFSPD_11_EHS_Pos                                  5                                                         /*!< SCU SFSPD_11: EHS Position          */
+#define SCU_SFSPD_11_EHS_Msk                                  (0x01UL << SCU_SFSPD_11_EHS_Pos)                          /*!< SCU SFSPD_11: EHS Mask              */
+#define SCU_SFSPD_11_EZI_Pos                                  6                                                         /*!< SCU SFSPD_11: EZI Position          */
+#define SCU_SFSPD_11_EZI_Msk                                  (0x01UL << SCU_SFSPD_11_EZI_Pos)                          /*!< SCU SFSPD_11: EZI Mask              */
+#define SCU_SFSPD_11_EHD_Pos                                  8                                                         /*!< SCU SFSPD_11: EHD Position          */
+#define SCU_SFSPD_11_EHD_Msk                                  (0x03UL << SCU_SFSPD_11_EHD_Pos)                          /*!< SCU SFSPD_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_12  ------------------------------------------
+#define SCU_SFSPD_12_MODE_Pos                                 0                                                         /*!< SCU SFSPD_12: MODE Position         */
+#define SCU_SFSPD_12_MODE_Msk                                 (0x07UL << SCU_SFSPD_12_MODE_Pos)                         /*!< SCU SFSPD_12: MODE Mask             */
+#define SCU_SFSPD_12_EPD_Pos                                  3                                                         /*!< SCU SFSPD_12: EPD Position          */
+#define SCU_SFSPD_12_EPD_Msk                                  (0x01UL << SCU_SFSPD_12_EPD_Pos)                          /*!< SCU SFSPD_12: EPD Mask              */
+#define SCU_SFSPD_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_12: EPUN Position         */
+#define SCU_SFSPD_12_EPUN_Msk                                 (0x01UL << SCU_SFSPD_12_EPUN_Pos)                         /*!< SCU SFSPD_12: EPUN Mask             */
+#define SCU_SFSPD_12_EHS_Pos                                  5                                                         /*!< SCU SFSPD_12: EHS Position          */
+#define SCU_SFSPD_12_EHS_Msk                                  (0x01UL << SCU_SFSPD_12_EHS_Pos)                          /*!< SCU SFSPD_12: EHS Mask              */
+#define SCU_SFSPD_12_EZI_Pos                                  6                                                         /*!< SCU SFSPD_12: EZI Position          */
+#define SCU_SFSPD_12_EZI_Msk                                  (0x01UL << SCU_SFSPD_12_EZI_Pos)                          /*!< SCU SFSPD_12: EZI Mask              */
+#define SCU_SFSPD_12_EHD_Pos                                  8                                                         /*!< SCU SFSPD_12: EHD Position          */
+#define SCU_SFSPD_12_EHD_Msk                                  (0x03UL << SCU_SFSPD_12_EHD_Pos)                          /*!< SCU SFSPD_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_13  ------------------------------------------
+#define SCU_SFSPD_13_MODE_Pos                                 0                                                         /*!< SCU SFSPD_13: MODE Position         */
+#define SCU_SFSPD_13_MODE_Msk                                 (0x07UL << SCU_SFSPD_13_MODE_Pos)                         /*!< SCU SFSPD_13: MODE Mask             */
+#define SCU_SFSPD_13_EPD_Pos                                  3                                                         /*!< SCU SFSPD_13: EPD Position          */
+#define SCU_SFSPD_13_EPD_Msk                                  (0x01UL << SCU_SFSPD_13_EPD_Pos)                          /*!< SCU SFSPD_13: EPD Mask              */
+#define SCU_SFSPD_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_13: EPUN Position         */
+#define SCU_SFSPD_13_EPUN_Msk                                 (0x01UL << SCU_SFSPD_13_EPUN_Pos)                         /*!< SCU SFSPD_13: EPUN Mask             */
+#define SCU_SFSPD_13_EHS_Pos                                  5                                                         /*!< SCU SFSPD_13: EHS Position          */
+#define SCU_SFSPD_13_EHS_Msk                                  (0x01UL << SCU_SFSPD_13_EHS_Pos)                          /*!< SCU SFSPD_13: EHS Mask              */
+#define SCU_SFSPD_13_EZI_Pos                                  6                                                         /*!< SCU SFSPD_13: EZI Position          */
+#define SCU_SFSPD_13_EZI_Msk                                  (0x01UL << SCU_SFSPD_13_EZI_Pos)                          /*!< SCU SFSPD_13: EZI Mask              */
+#define SCU_SFSPD_13_EHD_Pos                                  8                                                         /*!< SCU SFSPD_13: EHD Position          */
+#define SCU_SFSPD_13_EHD_Msk                                  (0x03UL << SCU_SFSPD_13_EHD_Pos)                          /*!< SCU SFSPD_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_14  ------------------------------------------
+#define SCU_SFSPD_14_MODE_Pos                                 0                                                         /*!< SCU SFSPD_14: MODE Position         */
+#define SCU_SFSPD_14_MODE_Msk                                 (0x07UL << SCU_SFSPD_14_MODE_Pos)                         /*!< SCU SFSPD_14: MODE Mask             */
+#define SCU_SFSPD_14_EPD_Pos                                  3                                                         /*!< SCU SFSPD_14: EPD Position          */
+#define SCU_SFSPD_14_EPD_Msk                                  (0x01UL << SCU_SFSPD_14_EPD_Pos)                          /*!< SCU SFSPD_14: EPD Mask              */
+#define SCU_SFSPD_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_14: EPUN Position         */
+#define SCU_SFSPD_14_EPUN_Msk                                 (0x01UL << SCU_SFSPD_14_EPUN_Pos)                         /*!< SCU SFSPD_14: EPUN Mask             */
+#define SCU_SFSPD_14_EHS_Pos                                  5                                                         /*!< SCU SFSPD_14: EHS Position          */
+#define SCU_SFSPD_14_EHS_Msk                                  (0x01UL << SCU_SFSPD_14_EHS_Pos)                          /*!< SCU SFSPD_14: EHS Mask              */
+#define SCU_SFSPD_14_EZI_Pos                                  6                                                         /*!< SCU SFSPD_14: EZI Position          */
+#define SCU_SFSPD_14_EZI_Msk                                  (0x01UL << SCU_SFSPD_14_EZI_Pos)                          /*!< SCU SFSPD_14: EZI Mask              */
+#define SCU_SFSPD_14_EHD_Pos                                  8                                                         /*!< SCU SFSPD_14: EHD Position          */
+#define SCU_SFSPD_14_EHD_Msk                                  (0x03UL << SCU_SFSPD_14_EHD_Pos)                          /*!< SCU SFSPD_14: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_15  ------------------------------------------
+#define SCU_SFSPD_15_MODE_Pos                                 0                                                         /*!< SCU SFSPD_15: MODE Position         */
+#define SCU_SFSPD_15_MODE_Msk                                 (0x07UL << SCU_SFSPD_15_MODE_Pos)                         /*!< SCU SFSPD_15: MODE Mask             */
+#define SCU_SFSPD_15_EPD_Pos                                  3                                                         /*!< SCU SFSPD_15: EPD Position          */
+#define SCU_SFSPD_15_EPD_Msk                                  (0x01UL << SCU_SFSPD_15_EPD_Pos)                          /*!< SCU SFSPD_15: EPD Mask              */
+#define SCU_SFSPD_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_15: EPUN Position         */
+#define SCU_SFSPD_15_EPUN_Msk                                 (0x01UL << SCU_SFSPD_15_EPUN_Pos)                         /*!< SCU SFSPD_15: EPUN Mask             */
+#define SCU_SFSPD_15_EHS_Pos                                  5                                                         /*!< SCU SFSPD_15: EHS Position          */
+#define SCU_SFSPD_15_EHS_Msk                                  (0x01UL << SCU_SFSPD_15_EHS_Pos)                          /*!< SCU SFSPD_15: EHS Mask              */
+#define SCU_SFSPD_15_EZI_Pos                                  6                                                         /*!< SCU SFSPD_15: EZI Position          */
+#define SCU_SFSPD_15_EZI_Msk                                  (0x01UL << SCU_SFSPD_15_EZI_Pos)                          /*!< SCU SFSPD_15: EZI Mask              */
+#define SCU_SFSPD_15_EHD_Pos                                  8                                                         /*!< SCU SFSPD_15: EHD Position          */
+#define SCU_SFSPD_15_EHD_Msk                                  (0x03UL << SCU_SFSPD_15_EHD_Pos)                          /*!< SCU SFSPD_15: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_16  ------------------------------------------
+#define SCU_SFSPD_16_MODE_Pos                                 0                                                         /*!< SCU SFSPD_16: MODE Position         */
+#define SCU_SFSPD_16_MODE_Msk                                 (0x07UL << SCU_SFSPD_16_MODE_Pos)                         /*!< SCU SFSPD_16: MODE Mask             */
+#define SCU_SFSPD_16_EPD_Pos                                  3                                                         /*!< SCU SFSPD_16: EPD Position          */
+#define SCU_SFSPD_16_EPD_Msk                                  (0x01UL << SCU_SFSPD_16_EPD_Pos)                          /*!< SCU SFSPD_16: EPD Mask              */
+#define SCU_SFSPD_16_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_16: EPUN Position         */
+#define SCU_SFSPD_16_EPUN_Msk                                 (0x01UL << SCU_SFSPD_16_EPUN_Pos)                         /*!< SCU SFSPD_16: EPUN Mask             */
+#define SCU_SFSPD_16_EHS_Pos                                  5                                                         /*!< SCU SFSPD_16: EHS Position          */
+#define SCU_SFSPD_16_EHS_Msk                                  (0x01UL << SCU_SFSPD_16_EHS_Pos)                          /*!< SCU SFSPD_16: EHS Mask              */
+#define SCU_SFSPD_16_EZI_Pos                                  6                                                         /*!< SCU SFSPD_16: EZI Position          */
+#define SCU_SFSPD_16_EZI_Msk                                  (0x01UL << SCU_SFSPD_16_EZI_Pos)                          /*!< SCU SFSPD_16: EZI Mask              */
+#define SCU_SFSPD_16_EHD_Pos                                  8                                                         /*!< SCU SFSPD_16: EHD Position          */
+#define SCU_SFSPD_16_EHD_Msk                                  (0x03UL << SCU_SFSPD_16_EHD_Pos)                          /*!< SCU SFSPD_16: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSPE_0  ------------------------------------------
+#define SCU_SFSPE_0_MODE_Pos                                  0                                                         /*!< SCU SFSPE_0: MODE Position          */
+#define SCU_SFSPE_0_MODE_Msk                                  (0x07UL << SCU_SFSPE_0_MODE_Pos)                          /*!< SCU SFSPE_0: MODE Mask              */
+#define SCU_SFSPE_0_EPD_Pos                                   3                                                         /*!< SCU SFSPE_0: EPD Position           */
+#define SCU_SFSPE_0_EPD_Msk                                   (0x01UL << SCU_SFSPE_0_EPD_Pos)                           /*!< SCU SFSPE_0: EPD Mask               */
+#define SCU_SFSPE_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_0: EPUN Position          */
+#define SCU_SFSPE_0_EPUN_Msk                                  (0x01UL << SCU_SFSPE_0_EPUN_Pos)                          /*!< SCU SFSPE_0: EPUN Mask              */
+#define SCU_SFSPE_0_EHS_Pos                                   5                                                         /*!< SCU SFSPE_0: EHS Position           */
+#define SCU_SFSPE_0_EHS_Msk                                   (0x01UL << SCU_SFSPE_0_EHS_Pos)                           /*!< SCU SFSPE_0: EHS Mask               */
+#define SCU_SFSPE_0_EZI_Pos                                   6                                                         /*!< SCU SFSPE_0: EZI Position           */
+#define SCU_SFSPE_0_EZI_Msk                                   (0x01UL << SCU_SFSPE_0_EZI_Pos)                           /*!< SCU SFSPE_0: EZI Mask               */
+#define SCU_SFSPE_0_EHD_Pos                                   8                                                         /*!< SCU SFSPE_0: EHD Position           */
+#define SCU_SFSPE_0_EHD_Msk                                   (0x03UL << SCU_SFSPE_0_EHD_Pos)                           /*!< SCU SFSPE_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_1  ------------------------------------------
+#define SCU_SFSPE_1_MODE_Pos                                  0                                                         /*!< SCU SFSPE_1: MODE Position          */
+#define SCU_SFSPE_1_MODE_Msk                                  (0x07UL << SCU_SFSPE_1_MODE_Pos)                          /*!< SCU SFSPE_1: MODE Mask              */
+#define SCU_SFSPE_1_EPD_Pos                                   3                                                         /*!< SCU SFSPE_1: EPD Position           */
+#define SCU_SFSPE_1_EPD_Msk                                   (0x01UL << SCU_SFSPE_1_EPD_Pos)                           /*!< SCU SFSPE_1: EPD Mask               */
+#define SCU_SFSPE_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_1: EPUN Position          */
+#define SCU_SFSPE_1_EPUN_Msk                                  (0x01UL << SCU_SFSPE_1_EPUN_Pos)                          /*!< SCU SFSPE_1: EPUN Mask              */
+#define SCU_SFSPE_1_EHS_Pos                                   5                                                         /*!< SCU SFSPE_1: EHS Position           */
+#define SCU_SFSPE_1_EHS_Msk                                   (0x01UL << SCU_SFSPE_1_EHS_Pos)                           /*!< SCU SFSPE_1: EHS Mask               */
+#define SCU_SFSPE_1_EZI_Pos                                   6                                                         /*!< SCU SFSPE_1: EZI Position           */
+#define SCU_SFSPE_1_EZI_Msk                                   (0x01UL << SCU_SFSPE_1_EZI_Pos)                           /*!< SCU SFSPE_1: EZI Mask               */
+#define SCU_SFSPE_1_EHD_Pos                                   8                                                         /*!< SCU SFSPE_1: EHD Position           */
+#define SCU_SFSPE_1_EHD_Msk                                   (0x03UL << SCU_SFSPE_1_EHD_Pos)                           /*!< SCU SFSPE_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_2  ------------------------------------------
+#define SCU_SFSPE_2_MODE_Pos                                  0                                                         /*!< SCU SFSPE_2: MODE Position          */
+#define SCU_SFSPE_2_MODE_Msk                                  (0x07UL << SCU_SFSPE_2_MODE_Pos)                          /*!< SCU SFSPE_2: MODE Mask              */
+#define SCU_SFSPE_2_EPD_Pos                                   3                                                         /*!< SCU SFSPE_2: EPD Position           */
+#define SCU_SFSPE_2_EPD_Msk                                   (0x01UL << SCU_SFSPE_2_EPD_Pos)                           /*!< SCU SFSPE_2: EPD Mask               */
+#define SCU_SFSPE_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_2: EPUN Position          */
+#define SCU_SFSPE_2_EPUN_Msk                                  (0x01UL << SCU_SFSPE_2_EPUN_Pos)                          /*!< SCU SFSPE_2: EPUN Mask              */
+#define SCU_SFSPE_2_EHS_Pos                                   5                                                         /*!< SCU SFSPE_2: EHS Position           */
+#define SCU_SFSPE_2_EHS_Msk                                   (0x01UL << SCU_SFSPE_2_EHS_Pos)                           /*!< SCU SFSPE_2: EHS Mask               */
+#define SCU_SFSPE_2_EZI_Pos                                   6                                                         /*!< SCU SFSPE_2: EZI Position           */
+#define SCU_SFSPE_2_EZI_Msk                                   (0x01UL << SCU_SFSPE_2_EZI_Pos)                           /*!< SCU SFSPE_2: EZI Mask               */
+#define SCU_SFSPE_2_EHD_Pos                                   8                                                         /*!< SCU SFSPE_2: EHD Position           */
+#define SCU_SFSPE_2_EHD_Msk                                   (0x03UL << SCU_SFSPE_2_EHD_Pos)                           /*!< SCU SFSPE_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_3  ------------------------------------------
+#define SCU_SFSPE_3_MODE_Pos                                  0                                                         /*!< SCU SFSPE_3: MODE Position          */
+#define SCU_SFSPE_3_MODE_Msk                                  (0x07UL << SCU_SFSPE_3_MODE_Pos)                          /*!< SCU SFSPE_3: MODE Mask              */
+#define SCU_SFSPE_3_EPD_Pos                                   3                                                         /*!< SCU SFSPE_3: EPD Position           */
+#define SCU_SFSPE_3_EPD_Msk                                   (0x01UL << SCU_SFSPE_3_EPD_Pos)                           /*!< SCU SFSPE_3: EPD Mask               */
+#define SCU_SFSPE_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_3: EPUN Position          */
+#define SCU_SFSPE_3_EPUN_Msk                                  (0x01UL << SCU_SFSPE_3_EPUN_Pos)                          /*!< SCU SFSPE_3: EPUN Mask              */
+#define SCU_SFSPE_3_EHS_Pos                                   5                                                         /*!< SCU SFSPE_3: EHS Position           */
+#define SCU_SFSPE_3_EHS_Msk                                   (0x01UL << SCU_SFSPE_3_EHS_Pos)                           /*!< SCU SFSPE_3: EHS Mask               */
+#define SCU_SFSPE_3_EZI_Pos                                   6                                                         /*!< SCU SFSPE_3: EZI Position           */
+#define SCU_SFSPE_3_EZI_Msk                                   (0x01UL << SCU_SFSPE_3_EZI_Pos)                           /*!< SCU SFSPE_3: EZI Mask               */
+#define SCU_SFSPE_3_EHD_Pos                                   8                                                         /*!< SCU SFSPE_3: EHD Position           */
+#define SCU_SFSPE_3_EHD_Msk                                   (0x03UL << SCU_SFSPE_3_EHD_Pos)                           /*!< SCU SFSPE_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_4  ------------------------------------------
+#define SCU_SFSPE_4_MODE_Pos                                  0                                                         /*!< SCU SFSPE_4: MODE Position          */
+#define SCU_SFSPE_4_MODE_Msk                                  (0x07UL << SCU_SFSPE_4_MODE_Pos)                          /*!< SCU SFSPE_4: MODE Mask              */
+#define SCU_SFSPE_4_EPD_Pos                                   3                                                         /*!< SCU SFSPE_4: EPD Position           */
+#define SCU_SFSPE_4_EPD_Msk                                   (0x01UL << SCU_SFSPE_4_EPD_Pos)                           /*!< SCU SFSPE_4: EPD Mask               */
+#define SCU_SFSPE_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_4: EPUN Position          */
+#define SCU_SFSPE_4_EPUN_Msk                                  (0x01UL << SCU_SFSPE_4_EPUN_Pos)                          /*!< SCU SFSPE_4: EPUN Mask              */
+#define SCU_SFSPE_4_EHS_Pos                                   5                                                         /*!< SCU SFSPE_4: EHS Position           */
+#define SCU_SFSPE_4_EHS_Msk                                   (0x01UL << SCU_SFSPE_4_EHS_Pos)                           /*!< SCU SFSPE_4: EHS Mask               */
+#define SCU_SFSPE_4_EZI_Pos                                   6                                                         /*!< SCU SFSPE_4: EZI Position           */
+#define SCU_SFSPE_4_EZI_Msk                                   (0x01UL << SCU_SFSPE_4_EZI_Pos)                           /*!< SCU SFSPE_4: EZI Mask               */
+#define SCU_SFSPE_4_EHD_Pos                                   8                                                         /*!< SCU SFSPE_4: EHD Position           */
+#define SCU_SFSPE_4_EHD_Msk                                   (0x03UL << SCU_SFSPE_4_EHD_Pos)                           /*!< SCU SFSPE_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_5  ------------------------------------------
+#define SCU_SFSPE_5_MODE_Pos                                  0                                                         /*!< SCU SFSPE_5: MODE Position          */
+#define SCU_SFSPE_5_MODE_Msk                                  (0x07UL << SCU_SFSPE_5_MODE_Pos)                          /*!< SCU SFSPE_5: MODE Mask              */
+#define SCU_SFSPE_5_EPD_Pos                                   3                                                         /*!< SCU SFSPE_5: EPD Position           */
+#define SCU_SFSPE_5_EPD_Msk                                   (0x01UL << SCU_SFSPE_5_EPD_Pos)                           /*!< SCU SFSPE_5: EPD Mask               */
+#define SCU_SFSPE_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_5: EPUN Position          */
+#define SCU_SFSPE_5_EPUN_Msk                                  (0x01UL << SCU_SFSPE_5_EPUN_Pos)                          /*!< SCU SFSPE_5: EPUN Mask              */
+#define SCU_SFSPE_5_EHS_Pos                                   5                                                         /*!< SCU SFSPE_5: EHS Position           */
+#define SCU_SFSPE_5_EHS_Msk                                   (0x01UL << SCU_SFSPE_5_EHS_Pos)                           /*!< SCU SFSPE_5: EHS Mask               */
+#define SCU_SFSPE_5_EZI_Pos                                   6                                                         /*!< SCU SFSPE_5: EZI Position           */
+#define SCU_SFSPE_5_EZI_Msk                                   (0x01UL << SCU_SFSPE_5_EZI_Pos)                           /*!< SCU SFSPE_5: EZI Mask               */
+#define SCU_SFSPE_5_EHD_Pos                                   8                                                         /*!< SCU SFSPE_5: EHD Position           */
+#define SCU_SFSPE_5_EHD_Msk                                   (0x03UL << SCU_SFSPE_5_EHD_Pos)                           /*!< SCU SFSPE_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_6  ------------------------------------------
+#define SCU_SFSPE_6_MODE_Pos                                  0                                                         /*!< SCU SFSPE_6: MODE Position          */
+#define SCU_SFSPE_6_MODE_Msk                                  (0x07UL << SCU_SFSPE_6_MODE_Pos)                          /*!< SCU SFSPE_6: MODE Mask              */
+#define SCU_SFSPE_6_EPD_Pos                                   3                                                         /*!< SCU SFSPE_6: EPD Position           */
+#define SCU_SFSPE_6_EPD_Msk                                   (0x01UL << SCU_SFSPE_6_EPD_Pos)                           /*!< SCU SFSPE_6: EPD Mask               */
+#define SCU_SFSPE_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_6: EPUN Position          */
+#define SCU_SFSPE_6_EPUN_Msk                                  (0x01UL << SCU_SFSPE_6_EPUN_Pos)                          /*!< SCU SFSPE_6: EPUN Mask              */
+#define SCU_SFSPE_6_EHS_Pos                                   5                                                         /*!< SCU SFSPE_6: EHS Position           */
+#define SCU_SFSPE_6_EHS_Msk                                   (0x01UL << SCU_SFSPE_6_EHS_Pos)                           /*!< SCU SFSPE_6: EHS Mask               */
+#define SCU_SFSPE_6_EZI_Pos                                   6                                                         /*!< SCU SFSPE_6: EZI Position           */
+#define SCU_SFSPE_6_EZI_Msk                                   (0x01UL << SCU_SFSPE_6_EZI_Pos)                           /*!< SCU SFSPE_6: EZI Mask               */
+#define SCU_SFSPE_6_EHD_Pos                                   8                                                         /*!< SCU SFSPE_6: EHD Position           */
+#define SCU_SFSPE_6_EHD_Msk                                   (0x03UL << SCU_SFSPE_6_EHD_Pos)                           /*!< SCU SFSPE_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_7  ------------------------------------------
+#define SCU_SFSPE_7_MODE_Pos                                  0                                                         /*!< SCU SFSPE_7: MODE Position          */
+#define SCU_SFSPE_7_MODE_Msk                                  (0x07UL << SCU_SFSPE_7_MODE_Pos)                          /*!< SCU SFSPE_7: MODE Mask              */
+#define SCU_SFSPE_7_EPD_Pos                                   3                                                         /*!< SCU SFSPE_7: EPD Position           */
+#define SCU_SFSPE_7_EPD_Msk                                   (0x01UL << SCU_SFSPE_7_EPD_Pos)                           /*!< SCU SFSPE_7: EPD Mask               */
+#define SCU_SFSPE_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_7: EPUN Position          */
+#define SCU_SFSPE_7_EPUN_Msk                                  (0x01UL << SCU_SFSPE_7_EPUN_Pos)                          /*!< SCU SFSPE_7: EPUN Mask              */
+#define SCU_SFSPE_7_EHS_Pos                                   5                                                         /*!< SCU SFSPE_7: EHS Position           */
+#define SCU_SFSPE_7_EHS_Msk                                   (0x01UL << SCU_SFSPE_7_EHS_Pos)                           /*!< SCU SFSPE_7: EHS Mask               */
+#define SCU_SFSPE_7_EZI_Pos                                   6                                                         /*!< SCU SFSPE_7: EZI Position           */
+#define SCU_SFSPE_7_EZI_Msk                                   (0x01UL << SCU_SFSPE_7_EZI_Pos)                           /*!< SCU SFSPE_7: EZI Mask               */
+#define SCU_SFSPE_7_EHD_Pos                                   8                                                         /*!< SCU SFSPE_7: EHD Position           */
+#define SCU_SFSPE_7_EHD_Msk                                   (0x03UL << SCU_SFSPE_7_EHD_Pos)                           /*!< SCU SFSPE_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_8  ------------------------------------------
+#define SCU_SFSPE_8_MODE_Pos                                  0                                                         /*!< SCU SFSPE_8: MODE Position          */
+#define SCU_SFSPE_8_MODE_Msk                                  (0x07UL << SCU_SFSPE_8_MODE_Pos)                          /*!< SCU SFSPE_8: MODE Mask              */
+#define SCU_SFSPE_8_EPD_Pos                                   3                                                         /*!< SCU SFSPE_8: EPD Position           */
+#define SCU_SFSPE_8_EPD_Msk                                   (0x01UL << SCU_SFSPE_8_EPD_Pos)                           /*!< SCU SFSPE_8: EPD Mask               */
+#define SCU_SFSPE_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_8: EPUN Position          */
+#define SCU_SFSPE_8_EPUN_Msk                                  (0x01UL << SCU_SFSPE_8_EPUN_Pos)                          /*!< SCU SFSPE_8: EPUN Mask              */
+#define SCU_SFSPE_8_EHS_Pos                                   5                                                         /*!< SCU SFSPE_8: EHS Position           */
+#define SCU_SFSPE_8_EHS_Msk                                   (0x01UL << SCU_SFSPE_8_EHS_Pos)                           /*!< SCU SFSPE_8: EHS Mask               */
+#define SCU_SFSPE_8_EZI_Pos                                   6                                                         /*!< SCU SFSPE_8: EZI Position           */
+#define SCU_SFSPE_8_EZI_Msk                                   (0x01UL << SCU_SFSPE_8_EZI_Pos)                           /*!< SCU SFSPE_8: EZI Mask               */
+#define SCU_SFSPE_8_EHD_Pos                                   8                                                         /*!< SCU SFSPE_8: EHD Position           */
+#define SCU_SFSPE_8_EHD_Msk                                   (0x03UL << SCU_SFSPE_8_EHD_Pos)                           /*!< SCU SFSPE_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_9  ------------------------------------------
+#define SCU_SFSPE_9_MODE_Pos                                  0                                                         /*!< SCU SFSPE_9: MODE Position          */
+#define SCU_SFSPE_9_MODE_Msk                                  (0x07UL << SCU_SFSPE_9_MODE_Pos)                          /*!< SCU SFSPE_9: MODE Mask              */
+#define SCU_SFSPE_9_EPD_Pos                                   3                                                         /*!< SCU SFSPE_9: EPD Position           */
+#define SCU_SFSPE_9_EPD_Msk                                   (0x01UL << SCU_SFSPE_9_EPD_Pos)                           /*!< SCU SFSPE_9: EPD Mask               */
+#define SCU_SFSPE_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_9: EPUN Position          */
+#define SCU_SFSPE_9_EPUN_Msk                                  (0x01UL << SCU_SFSPE_9_EPUN_Pos)                          /*!< SCU SFSPE_9: EPUN Mask              */
+#define SCU_SFSPE_9_EHS_Pos                                   5                                                         /*!< SCU SFSPE_9: EHS Position           */
+#define SCU_SFSPE_9_EHS_Msk                                   (0x01UL << SCU_SFSPE_9_EHS_Pos)                           /*!< SCU SFSPE_9: EHS Mask               */
+#define SCU_SFSPE_9_EZI_Pos                                   6                                                         /*!< SCU SFSPE_9: EZI Position           */
+#define SCU_SFSPE_9_EZI_Msk                                   (0x01UL << SCU_SFSPE_9_EZI_Pos)                           /*!< SCU SFSPE_9: EZI Mask               */
+#define SCU_SFSPE_9_EHD_Pos                                   8                                                         /*!< SCU SFSPE_9: EHD Position           */
+#define SCU_SFSPE_9_EHD_Msk                                   (0x03UL << SCU_SFSPE_9_EHD_Pos)                           /*!< SCU SFSPE_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPE_10  ------------------------------------------
+#define SCU_SFSPE_10_MODE_Pos                                 0                                                         /*!< SCU SFSPE_10: MODE Position         */
+#define SCU_SFSPE_10_MODE_Msk                                 (0x07UL << SCU_SFSPE_10_MODE_Pos)                         /*!< SCU SFSPE_10: MODE Mask             */
+#define SCU_SFSPE_10_EPD_Pos                                  3                                                         /*!< SCU SFSPE_10: EPD Position          */
+#define SCU_SFSPE_10_EPD_Msk                                  (0x01UL << SCU_SFSPE_10_EPD_Pos)                          /*!< SCU SFSPE_10: EPD Mask              */
+#define SCU_SFSPE_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_10: EPUN Position         */
+#define SCU_SFSPE_10_EPUN_Msk                                 (0x01UL << SCU_SFSPE_10_EPUN_Pos)                         /*!< SCU SFSPE_10: EPUN Mask             */
+#define SCU_SFSPE_10_EHS_Pos                                  5                                                         /*!< SCU SFSPE_10: EHS Position          */
+#define SCU_SFSPE_10_EHS_Msk                                  (0x01UL << SCU_SFSPE_10_EHS_Pos)                          /*!< SCU SFSPE_10: EHS Mask              */
+#define SCU_SFSPE_10_EZI_Pos                                  6                                                         /*!< SCU SFSPE_10: EZI Position          */
+#define SCU_SFSPE_10_EZI_Msk                                  (0x01UL << SCU_SFSPE_10_EZI_Pos)                          /*!< SCU SFSPE_10: EZI Mask              */
+#define SCU_SFSPE_10_EHD_Pos                                  8                                                         /*!< SCU SFSPE_10: EHD Position          */
+#define SCU_SFSPE_10_EHD_Msk                                  (0x03UL << SCU_SFSPE_10_EHD_Pos)                          /*!< SCU SFSPE_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_11  ------------------------------------------
+#define SCU_SFSPE_11_MODE_Pos                                 0                                                         /*!< SCU SFSPE_11: MODE Position         */
+#define SCU_SFSPE_11_MODE_Msk                                 (0x07UL << SCU_SFSPE_11_MODE_Pos)                         /*!< SCU SFSPE_11: MODE Mask             */
+#define SCU_SFSPE_11_EPD_Pos                                  3                                                         /*!< SCU SFSPE_11: EPD Position          */
+#define SCU_SFSPE_11_EPD_Msk                                  (0x01UL << SCU_SFSPE_11_EPD_Pos)                          /*!< SCU SFSPE_11: EPD Mask              */
+#define SCU_SFSPE_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_11: EPUN Position         */
+#define SCU_SFSPE_11_EPUN_Msk                                 (0x01UL << SCU_SFSPE_11_EPUN_Pos)                         /*!< SCU SFSPE_11: EPUN Mask             */
+#define SCU_SFSPE_11_EHS_Pos                                  5                                                         /*!< SCU SFSPE_11: EHS Position          */
+#define SCU_SFSPE_11_EHS_Msk                                  (0x01UL << SCU_SFSPE_11_EHS_Pos)                          /*!< SCU SFSPE_11: EHS Mask              */
+#define SCU_SFSPE_11_EZI_Pos                                  6                                                         /*!< SCU SFSPE_11: EZI Position          */
+#define SCU_SFSPE_11_EZI_Msk                                  (0x01UL << SCU_SFSPE_11_EZI_Pos)                          /*!< SCU SFSPE_11: EZI Mask              */
+#define SCU_SFSPE_11_EHD_Pos                                  8                                                         /*!< SCU SFSPE_11: EHD Position          */
+#define SCU_SFSPE_11_EHD_Msk                                  (0x03UL << SCU_SFSPE_11_EHD_Pos)                          /*!< SCU SFSPE_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_12  ------------------------------------------
+#define SCU_SFSPE_12_MODE_Pos                                 0                                                         /*!< SCU SFSPE_12: MODE Position         */
+#define SCU_SFSPE_12_MODE_Msk                                 (0x07UL << SCU_SFSPE_12_MODE_Pos)                         /*!< SCU SFSPE_12: MODE Mask             */
+#define SCU_SFSPE_12_EPD_Pos                                  3                                                         /*!< SCU SFSPE_12: EPD Position          */
+#define SCU_SFSPE_12_EPD_Msk                                  (0x01UL << SCU_SFSPE_12_EPD_Pos)                          /*!< SCU SFSPE_12: EPD Mask              */
+#define SCU_SFSPE_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_12: EPUN Position         */
+#define SCU_SFSPE_12_EPUN_Msk                                 (0x01UL << SCU_SFSPE_12_EPUN_Pos)                         /*!< SCU SFSPE_12: EPUN Mask             */
+#define SCU_SFSPE_12_EHS_Pos                                  5                                                         /*!< SCU SFSPE_12: EHS Position          */
+#define SCU_SFSPE_12_EHS_Msk                                  (0x01UL << SCU_SFSPE_12_EHS_Pos)                          /*!< SCU SFSPE_12: EHS Mask              */
+#define SCU_SFSPE_12_EZI_Pos                                  6                                                         /*!< SCU SFSPE_12: EZI Position          */
+#define SCU_SFSPE_12_EZI_Msk                                  (0x01UL << SCU_SFSPE_12_EZI_Pos)                          /*!< SCU SFSPE_12: EZI Mask              */
+#define SCU_SFSPE_12_EHD_Pos                                  8                                                         /*!< SCU SFSPE_12: EHD Position          */
+#define SCU_SFSPE_12_EHD_Msk                                  (0x03UL << SCU_SFSPE_12_EHD_Pos)                          /*!< SCU SFSPE_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_13  ------------------------------------------
+#define SCU_SFSPE_13_MODE_Pos                                 0                                                         /*!< SCU SFSPE_13: MODE Position         */
+#define SCU_SFSPE_13_MODE_Msk                                 (0x07UL << SCU_SFSPE_13_MODE_Pos)                         /*!< SCU SFSPE_13: MODE Mask             */
+#define SCU_SFSPE_13_EPD_Pos                                  3                                                         /*!< SCU SFSPE_13: EPD Position          */
+#define SCU_SFSPE_13_EPD_Msk                                  (0x01UL << SCU_SFSPE_13_EPD_Pos)                          /*!< SCU SFSPE_13: EPD Mask              */
+#define SCU_SFSPE_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_13: EPUN Position         */
+#define SCU_SFSPE_13_EPUN_Msk                                 (0x01UL << SCU_SFSPE_13_EPUN_Pos)                         /*!< SCU SFSPE_13: EPUN Mask             */
+#define SCU_SFSPE_13_EHS_Pos                                  5                                                         /*!< SCU SFSPE_13: EHS Position          */
+#define SCU_SFSPE_13_EHS_Msk                                  (0x01UL << SCU_SFSPE_13_EHS_Pos)                          /*!< SCU SFSPE_13: EHS Mask              */
+#define SCU_SFSPE_13_EZI_Pos                                  6                                                         /*!< SCU SFSPE_13: EZI Position          */
+#define SCU_SFSPE_13_EZI_Msk                                  (0x01UL << SCU_SFSPE_13_EZI_Pos)                          /*!< SCU SFSPE_13: EZI Mask              */
+#define SCU_SFSPE_13_EHD_Pos                                  8                                                         /*!< SCU SFSPE_13: EHD Position          */
+#define SCU_SFSPE_13_EHD_Msk                                  (0x03UL << SCU_SFSPE_13_EHD_Pos)                          /*!< SCU SFSPE_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_14  ------------------------------------------
+#define SCU_SFSPE_14_MODE_Pos                                 0                                                         /*!< SCU SFSPE_14: MODE Position         */
+#define SCU_SFSPE_14_MODE_Msk                                 (0x07UL << SCU_SFSPE_14_MODE_Pos)                         /*!< SCU SFSPE_14: MODE Mask             */
+#define SCU_SFSPE_14_EPD_Pos                                  3                                                         /*!< SCU SFSPE_14: EPD Position          */
+#define SCU_SFSPE_14_EPD_Msk                                  (0x01UL << SCU_SFSPE_14_EPD_Pos)                          /*!< SCU SFSPE_14: EPD Mask              */
+#define SCU_SFSPE_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_14: EPUN Position         */
+#define SCU_SFSPE_14_EPUN_Msk                                 (0x01UL << SCU_SFSPE_14_EPUN_Pos)                         /*!< SCU SFSPE_14: EPUN Mask             */
+#define SCU_SFSPE_14_EHS_Pos                                  5                                                         /*!< SCU SFSPE_14: EHS Position          */
+#define SCU_SFSPE_14_EHS_Msk                                  (0x01UL << SCU_SFSPE_14_EHS_Pos)                          /*!< SCU SFSPE_14: EHS Mask              */
+#define SCU_SFSPE_14_EZI_Pos                                  6                                                         /*!< SCU SFSPE_14: EZI Position          */
+#define SCU_SFSPE_14_EZI_Msk                                  (0x01UL << SCU_SFSPE_14_EZI_Pos)                          /*!< SCU SFSPE_14: EZI Mask              */
+#define SCU_SFSPE_14_EHD_Pos                                  8                                                         /*!< SCU SFSPE_14: EHD Position          */
+#define SCU_SFSPE_14_EHD_Msk                                  (0x03UL << SCU_SFSPE_14_EHD_Pos)                          /*!< SCU SFSPE_14: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_15  ------------------------------------------
+#define SCU_SFSPE_15_MODE_Pos                                 0                                                         /*!< SCU SFSPE_15: MODE Position         */
+#define SCU_SFSPE_15_MODE_Msk                                 (0x07UL << SCU_SFSPE_15_MODE_Pos)                         /*!< SCU SFSPE_15: MODE Mask             */
+#define SCU_SFSPE_15_EPD_Pos                                  3                                                         /*!< SCU SFSPE_15: EPD Position          */
+#define SCU_SFSPE_15_EPD_Msk                                  (0x01UL << SCU_SFSPE_15_EPD_Pos)                          /*!< SCU SFSPE_15: EPD Mask              */
+#define SCU_SFSPE_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_15: EPUN Position         */
+#define SCU_SFSPE_15_EPUN_Msk                                 (0x01UL << SCU_SFSPE_15_EPUN_Pos)                         /*!< SCU SFSPE_15: EPUN Mask             */
+#define SCU_SFSPE_15_EHS_Pos                                  5                                                         /*!< SCU SFSPE_15: EHS Position          */
+#define SCU_SFSPE_15_EHS_Msk                                  (0x01UL << SCU_SFSPE_15_EHS_Pos)                          /*!< SCU SFSPE_15: EHS Mask              */
+#define SCU_SFSPE_15_EZI_Pos                                  6                                                         /*!< SCU SFSPE_15: EZI Position          */
+#define SCU_SFSPE_15_EZI_Msk                                  (0x01UL << SCU_SFSPE_15_EZI_Pos)                          /*!< SCU SFSPE_15: EZI Mask              */
+#define SCU_SFSPE_15_EHD_Pos                                  8                                                         /*!< SCU SFSPE_15: EHD Position          */
+#define SCU_SFSPE_15_EHD_Msk                                  (0x03UL << SCU_SFSPE_15_EHD_Pos)                          /*!< SCU SFSPE_15: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSPF_0  ------------------------------------------
+#define SCU_SFSPF_0_MODE_Pos                                  0                                                         /*!< SCU SFSPF_0: MODE Position          */
+#define SCU_SFSPF_0_MODE_Msk                                  (0x07UL << SCU_SFSPF_0_MODE_Pos)                          /*!< SCU SFSPF_0: MODE Mask              */
+#define SCU_SFSPF_0_EPD_Pos                                   3                                                         /*!< SCU SFSPF_0: EPD Position           */
+#define SCU_SFSPF_0_EPD_Msk                                   (0x01UL << SCU_SFSPF_0_EPD_Pos)                           /*!< SCU SFSPF_0: EPD Mask               */
+#define SCU_SFSPF_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_0: EPUN Position          */
+#define SCU_SFSPF_0_EPUN_Msk                                  (0x01UL << SCU_SFSPF_0_EPUN_Pos)                          /*!< SCU SFSPF_0: EPUN Mask              */
+#define SCU_SFSPF_0_EHS_Pos                                   5                                                         /*!< SCU SFSPF_0: EHS Position           */
+#define SCU_SFSPF_0_EHS_Msk                                   (0x01UL << SCU_SFSPF_0_EHS_Pos)                           /*!< SCU SFSPF_0: EHS Mask               */
+#define SCU_SFSPF_0_EZI_Pos                                   6                                                         /*!< SCU SFSPF_0: EZI Position           */
+#define SCU_SFSPF_0_EZI_Msk                                   (0x01UL << SCU_SFSPF_0_EZI_Pos)                           /*!< SCU SFSPF_0: EZI Mask               */
+#define SCU_SFSPF_0_EHD_Pos                                   8                                                         /*!< SCU SFSPF_0: EHD Position           */
+#define SCU_SFSPF_0_EHD_Msk                                   (0x03UL << SCU_SFSPF_0_EHD_Pos)                           /*!< SCU SFSPF_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_1  ------------------------------------------
+#define SCU_SFSPF_1_MODE_Pos                                  0                                                         /*!< SCU SFSPF_1: MODE Position          */
+#define SCU_SFSPF_1_MODE_Msk                                  (0x07UL << SCU_SFSPF_1_MODE_Pos)                          /*!< SCU SFSPF_1: MODE Mask              */
+#define SCU_SFSPF_1_EPD_Pos                                   3                                                         /*!< SCU SFSPF_1: EPD Position           */
+#define SCU_SFSPF_1_EPD_Msk                                   (0x01UL << SCU_SFSPF_1_EPD_Pos)                           /*!< SCU SFSPF_1: EPD Mask               */
+#define SCU_SFSPF_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_1: EPUN Position          */
+#define SCU_SFSPF_1_EPUN_Msk                                  (0x01UL << SCU_SFSPF_1_EPUN_Pos)                          /*!< SCU SFSPF_1: EPUN Mask              */
+#define SCU_SFSPF_1_EHS_Pos                                   5                                                         /*!< SCU SFSPF_1: EHS Position           */
+#define SCU_SFSPF_1_EHS_Msk                                   (0x01UL << SCU_SFSPF_1_EHS_Pos)                           /*!< SCU SFSPF_1: EHS Mask               */
+#define SCU_SFSPF_1_EZI_Pos                                   6                                                         /*!< SCU SFSPF_1: EZI Position           */
+#define SCU_SFSPF_1_EZI_Msk                                   (0x01UL << SCU_SFSPF_1_EZI_Pos)                           /*!< SCU SFSPF_1: EZI Mask               */
+#define SCU_SFSPF_1_EHD_Pos                                   8                                                         /*!< SCU SFSPF_1: EHD Position           */
+#define SCU_SFSPF_1_EHD_Msk                                   (0x03UL << SCU_SFSPF_1_EHD_Pos)                           /*!< SCU SFSPF_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_2  ------------------------------------------
+#define SCU_SFSPF_2_MODE_Pos                                  0                                                         /*!< SCU SFSPF_2: MODE Position          */
+#define SCU_SFSPF_2_MODE_Msk                                  (0x07UL << SCU_SFSPF_2_MODE_Pos)                          /*!< SCU SFSPF_2: MODE Mask              */
+#define SCU_SFSPF_2_EPD_Pos                                   3                                                         /*!< SCU SFSPF_2: EPD Position           */
+#define SCU_SFSPF_2_EPD_Msk                                   (0x01UL << SCU_SFSPF_2_EPD_Pos)                           /*!< SCU SFSPF_2: EPD Mask               */
+#define SCU_SFSPF_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_2: EPUN Position          */
+#define SCU_SFSPF_2_EPUN_Msk                                  (0x01UL << SCU_SFSPF_2_EPUN_Pos)                          /*!< SCU SFSPF_2: EPUN Mask              */
+#define SCU_SFSPF_2_EHS_Pos                                   5                                                         /*!< SCU SFSPF_2: EHS Position           */
+#define SCU_SFSPF_2_EHS_Msk                                   (0x01UL << SCU_SFSPF_2_EHS_Pos)                           /*!< SCU SFSPF_2: EHS Mask               */
+#define SCU_SFSPF_2_EZI_Pos                                   6                                                         /*!< SCU SFSPF_2: EZI Position           */
+#define SCU_SFSPF_2_EZI_Msk                                   (0x01UL << SCU_SFSPF_2_EZI_Pos)                           /*!< SCU SFSPF_2: EZI Mask               */
+#define SCU_SFSPF_2_EHD_Pos                                   8                                                         /*!< SCU SFSPF_2: EHD Position           */
+#define SCU_SFSPF_2_EHD_Msk                                   (0x03UL << SCU_SFSPF_2_EHD_Pos)                           /*!< SCU SFSPF_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_3  ------------------------------------------
+#define SCU_SFSPF_3_MODE_Pos                                  0                                                         /*!< SCU SFSPF_3: MODE Position          */
+#define SCU_SFSPF_3_MODE_Msk                                  (0x07UL << SCU_SFSPF_3_MODE_Pos)                          /*!< SCU SFSPF_3: MODE Mask              */
+#define SCU_SFSPF_3_EPD_Pos                                   3                                                         /*!< SCU SFSPF_3: EPD Position           */
+#define SCU_SFSPF_3_EPD_Msk                                   (0x01UL << SCU_SFSPF_3_EPD_Pos)                           /*!< SCU SFSPF_3: EPD Mask               */
+#define SCU_SFSPF_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_3: EPUN Position          */
+#define SCU_SFSPF_3_EPUN_Msk                                  (0x01UL << SCU_SFSPF_3_EPUN_Pos)                          /*!< SCU SFSPF_3: EPUN Mask              */
+#define SCU_SFSPF_3_EHS_Pos                                   5                                                         /*!< SCU SFSPF_3: EHS Position           */
+#define SCU_SFSPF_3_EHS_Msk                                   (0x01UL << SCU_SFSPF_3_EHS_Pos)                           /*!< SCU SFSPF_3: EHS Mask               */
+#define SCU_SFSPF_3_EZI_Pos                                   6                                                         /*!< SCU SFSPF_3: EZI Position           */
+#define SCU_SFSPF_3_EZI_Msk                                   (0x01UL << SCU_SFSPF_3_EZI_Pos)                           /*!< SCU SFSPF_3: EZI Mask               */
+#define SCU_SFSPF_3_EHD_Pos                                   8                                                         /*!< SCU SFSPF_3: EHD Position           */
+#define SCU_SFSPF_3_EHD_Msk                                   (0x03UL << SCU_SFSPF_3_EHD_Pos)                           /*!< SCU SFSPF_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_4  ------------------------------------------
+#define SCU_SFSPF_4_MODE_Pos                                  0                                                         /*!< SCU SFSPF_4: MODE Position          */
+#define SCU_SFSPF_4_MODE_Msk                                  (0x07UL << SCU_SFSPF_4_MODE_Pos)                          /*!< SCU SFSPF_4: MODE Mask              */
+#define SCU_SFSPF_4_EPD_Pos                                   3                                                         /*!< SCU SFSPF_4: EPD Position           */
+#define SCU_SFSPF_4_EPD_Msk                                   (0x01UL << SCU_SFSPF_4_EPD_Pos)                           /*!< SCU SFSPF_4: EPD Mask               */
+#define SCU_SFSPF_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_4: EPUN Position          */
+#define SCU_SFSPF_4_EPUN_Msk                                  (0x01UL << SCU_SFSPF_4_EPUN_Pos)                          /*!< SCU SFSPF_4: EPUN Mask              */
+#define SCU_SFSPF_4_EHS_Pos                                   5                                                         /*!< SCU SFSPF_4: EHS Position           */
+#define SCU_SFSPF_4_EHS_Msk                                   (0x01UL << SCU_SFSPF_4_EHS_Pos)                           /*!< SCU SFSPF_4: EHS Mask               */
+#define SCU_SFSPF_4_EZI_Pos                                   6                                                         /*!< SCU SFSPF_4: EZI Position           */
+#define SCU_SFSPF_4_EZI_Msk                                   (0x01UL << SCU_SFSPF_4_EZI_Pos)                           /*!< SCU SFSPF_4: EZI Mask               */
+#define SCU_SFSPF_4_EHD_Pos                                   8                                                         /*!< SCU SFSPF_4: EHD Position           */
+#define SCU_SFSPF_4_EHD_Msk                                   (0x03UL << SCU_SFSPF_4_EHD_Pos)                           /*!< SCU SFSPF_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_5  ------------------------------------------
+#define SCU_SFSPF_5_MODE_Pos                                  0                                                         /*!< SCU SFSPF_5: MODE Position          */
+#define SCU_SFSPF_5_MODE_Msk                                  (0x07UL << SCU_SFSPF_5_MODE_Pos)                          /*!< SCU SFSPF_5: MODE Mask              */
+#define SCU_SFSPF_5_EPD_Pos                                   3                                                         /*!< SCU SFSPF_5: EPD Position           */
+#define SCU_SFSPF_5_EPD_Msk                                   (0x01UL << SCU_SFSPF_5_EPD_Pos)                           /*!< SCU SFSPF_5: EPD Mask               */
+#define SCU_SFSPF_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_5: EPUN Position          */
+#define SCU_SFSPF_5_EPUN_Msk                                  (0x01UL << SCU_SFSPF_5_EPUN_Pos)                          /*!< SCU SFSPF_5: EPUN Mask              */
+#define SCU_SFSPF_5_EHS_Pos                                   5                                                         /*!< SCU SFSPF_5: EHS Position           */
+#define SCU_SFSPF_5_EHS_Msk                                   (0x01UL << SCU_SFSPF_5_EHS_Pos)                           /*!< SCU SFSPF_5: EHS Mask               */
+#define SCU_SFSPF_5_EZI_Pos                                   6                                                         /*!< SCU SFSPF_5: EZI Position           */
+#define SCU_SFSPF_5_EZI_Msk                                   (0x01UL << SCU_SFSPF_5_EZI_Pos)                           /*!< SCU SFSPF_5: EZI Mask               */
+#define SCU_SFSPF_5_EHD_Pos                                   8                                                         /*!< SCU SFSPF_5: EHD Position           */
+#define SCU_SFSPF_5_EHD_Msk                                   (0x03UL << SCU_SFSPF_5_EHD_Pos)                           /*!< SCU SFSPF_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_6  ------------------------------------------
+#define SCU_SFSPF_6_MODE_Pos                                  0                                                         /*!< SCU SFSPF_6: MODE Position          */
+#define SCU_SFSPF_6_MODE_Msk                                  (0x07UL << SCU_SFSPF_6_MODE_Pos)                          /*!< SCU SFSPF_6: MODE Mask              */
+#define SCU_SFSPF_6_EPD_Pos                                   3                                                         /*!< SCU SFSPF_6: EPD Position           */
+#define SCU_SFSPF_6_EPD_Msk                                   (0x01UL << SCU_SFSPF_6_EPD_Pos)                           /*!< SCU SFSPF_6: EPD Mask               */
+#define SCU_SFSPF_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_6: EPUN Position          */
+#define SCU_SFSPF_6_EPUN_Msk                                  (0x01UL << SCU_SFSPF_6_EPUN_Pos)                          /*!< SCU SFSPF_6: EPUN Mask              */
+#define SCU_SFSPF_6_EHS_Pos                                   5                                                         /*!< SCU SFSPF_6: EHS Position           */
+#define SCU_SFSPF_6_EHS_Msk                                   (0x01UL << SCU_SFSPF_6_EHS_Pos)                           /*!< SCU SFSPF_6: EHS Mask               */
+#define SCU_SFSPF_6_EZI_Pos                                   6                                                         /*!< SCU SFSPF_6: EZI Position           */
+#define SCU_SFSPF_6_EZI_Msk                                   (0x01UL << SCU_SFSPF_6_EZI_Pos)                           /*!< SCU SFSPF_6: EZI Mask               */
+#define SCU_SFSPF_6_EHD_Pos                                   8                                                         /*!< SCU SFSPF_6: EHD Position           */
+#define SCU_SFSPF_6_EHD_Msk                                   (0x03UL << SCU_SFSPF_6_EHD_Pos)                           /*!< SCU SFSPF_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_7  ------------------------------------------
+#define SCU_SFSPF_7_MODE_Pos                                  0                                                         /*!< SCU SFSPF_7: MODE Position          */
+#define SCU_SFSPF_7_MODE_Msk                                  (0x07UL << SCU_SFSPF_7_MODE_Pos)                          /*!< SCU SFSPF_7: MODE Mask              */
+#define SCU_SFSPF_7_EPD_Pos                                   3                                                         /*!< SCU SFSPF_7: EPD Position           */
+#define SCU_SFSPF_7_EPD_Msk                                   (0x01UL << SCU_SFSPF_7_EPD_Pos)                           /*!< SCU SFSPF_7: EPD Mask               */
+#define SCU_SFSPF_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_7: EPUN Position          */
+#define SCU_SFSPF_7_EPUN_Msk                                  (0x01UL << SCU_SFSPF_7_EPUN_Pos)                          /*!< SCU SFSPF_7: EPUN Mask              */
+#define SCU_SFSPF_7_EHS_Pos                                   5                                                         /*!< SCU SFSPF_7: EHS Position           */
+#define SCU_SFSPF_7_EHS_Msk                                   (0x01UL << SCU_SFSPF_7_EHS_Pos)                           /*!< SCU SFSPF_7: EHS Mask               */
+#define SCU_SFSPF_7_EZI_Pos                                   6                                                         /*!< SCU SFSPF_7: EZI Position           */
+#define SCU_SFSPF_7_EZI_Msk                                   (0x01UL << SCU_SFSPF_7_EZI_Pos)                           /*!< SCU SFSPF_7: EZI Mask               */
+#define SCU_SFSPF_7_EHD_Pos                                   8                                                         /*!< SCU SFSPF_7: EHD Position           */
+#define SCU_SFSPF_7_EHD_Msk                                   (0x03UL << SCU_SFSPF_7_EHD_Pos)                           /*!< SCU SFSPF_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_8  ------------------------------------------
+#define SCU_SFSPF_8_MODE_Pos                                  0                                                         /*!< SCU SFSPF_8: MODE Position          */
+#define SCU_SFSPF_8_MODE_Msk                                  (0x07UL << SCU_SFSPF_8_MODE_Pos)                          /*!< SCU SFSPF_8: MODE Mask              */
+#define SCU_SFSPF_8_EPD_Pos                                   3                                                         /*!< SCU SFSPF_8: EPD Position           */
+#define SCU_SFSPF_8_EPD_Msk                                   (0x01UL << SCU_SFSPF_8_EPD_Pos)                           /*!< SCU SFSPF_8: EPD Mask               */
+#define SCU_SFSPF_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_8: EPUN Position          */
+#define SCU_SFSPF_8_EPUN_Msk                                  (0x01UL << SCU_SFSPF_8_EPUN_Pos)                          /*!< SCU SFSPF_8: EPUN Mask              */
+#define SCU_SFSPF_8_EHS_Pos                                   5                                                         /*!< SCU SFSPF_8: EHS Position           */
+#define SCU_SFSPF_8_EHS_Msk                                   (0x01UL << SCU_SFSPF_8_EHS_Pos)                           /*!< SCU SFSPF_8: EHS Mask               */
+#define SCU_SFSPF_8_EZI_Pos                                   6                                                         /*!< SCU SFSPF_8: EZI Position           */
+#define SCU_SFSPF_8_EZI_Msk                                   (0x01UL << SCU_SFSPF_8_EZI_Pos)                           /*!< SCU SFSPF_8: EZI Mask               */
+#define SCU_SFSPF_8_EHD_Pos                                   8                                                         /*!< SCU SFSPF_8: EHD Position           */
+#define SCU_SFSPF_8_EHD_Msk                                   (0x03UL << SCU_SFSPF_8_EHD_Pos)                           /*!< SCU SFSPF_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_9  ------------------------------------------
+#define SCU_SFSPF_9_MODE_Pos                                  0                                                         /*!< SCU SFSPF_9: MODE Position          */
+#define SCU_SFSPF_9_MODE_Msk                                  (0x07UL << SCU_SFSPF_9_MODE_Pos)                          /*!< SCU SFSPF_9: MODE Mask              */
+#define SCU_SFSPF_9_EPD_Pos                                   3                                                         /*!< SCU SFSPF_9: EPD Position           */
+#define SCU_SFSPF_9_EPD_Msk                                   (0x01UL << SCU_SFSPF_9_EPD_Pos)                           /*!< SCU SFSPF_9: EPD Mask               */
+#define SCU_SFSPF_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_9: EPUN Position          */
+#define SCU_SFSPF_9_EPUN_Msk                                  (0x01UL << SCU_SFSPF_9_EPUN_Pos)                          /*!< SCU SFSPF_9: EPUN Mask              */
+#define SCU_SFSPF_9_EHS_Pos                                   5                                                         /*!< SCU SFSPF_9: EHS Position           */
+#define SCU_SFSPF_9_EHS_Msk                                   (0x01UL << SCU_SFSPF_9_EHS_Pos)                           /*!< SCU SFSPF_9: EHS Mask               */
+#define SCU_SFSPF_9_EZI_Pos                                   6                                                         /*!< SCU SFSPF_9: EZI Position           */
+#define SCU_SFSPF_9_EZI_Msk                                   (0x01UL << SCU_SFSPF_9_EZI_Pos)                           /*!< SCU SFSPF_9: EZI Mask               */
+#define SCU_SFSPF_9_EHD_Pos                                   8                                                         /*!< SCU SFSPF_9: EHD Position           */
+#define SCU_SFSPF_9_EHD_Msk                                   (0x03UL << SCU_SFSPF_9_EHD_Pos)                           /*!< SCU SFSPF_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPF_10  ------------------------------------------
+#define SCU_SFSPF_10_MODE_Pos                                 0                                                         /*!< SCU SFSPF_10: MODE Position         */
+#define SCU_SFSPF_10_MODE_Msk                                 (0x07UL << SCU_SFSPF_10_MODE_Pos)                         /*!< SCU SFSPF_10: MODE Mask             */
+#define SCU_SFSPF_10_EPD_Pos                                  3                                                         /*!< SCU SFSPF_10: EPD Position          */
+#define SCU_SFSPF_10_EPD_Msk                                  (0x01UL << SCU_SFSPF_10_EPD_Pos)                          /*!< SCU SFSPF_10: EPD Mask              */
+#define SCU_SFSPF_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_10: EPUN Position         */
+#define SCU_SFSPF_10_EPUN_Msk                                 (0x01UL << SCU_SFSPF_10_EPUN_Pos)                         /*!< SCU SFSPF_10: EPUN Mask             */
+#define SCU_SFSPF_10_EHS_Pos                                  5                                                         /*!< SCU SFSPF_10: EHS Position          */
+#define SCU_SFSPF_10_EHS_Msk                                  (0x01UL << SCU_SFSPF_10_EHS_Pos)                          /*!< SCU SFSPF_10: EHS Mask              */
+#define SCU_SFSPF_10_EZI_Pos                                  6                                                         /*!< SCU SFSPF_10: EZI Position          */
+#define SCU_SFSPF_10_EZI_Msk                                  (0x01UL << SCU_SFSPF_10_EZI_Pos)                          /*!< SCU SFSPF_10: EZI Mask              */
+#define SCU_SFSPF_10_EHD_Pos                                  8                                                         /*!< SCU SFSPF_10: EHD Position          */
+#define SCU_SFSPF_10_EHD_Msk                                  (0x03UL << SCU_SFSPF_10_EHD_Pos)                          /*!< SCU SFSPF_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPF_11  ------------------------------------------
+#define SCU_SFSPF_11_MODE_Pos                                 0                                                         /*!< SCU SFSPF_11: MODE Position         */
+#define SCU_SFSPF_11_MODE_Msk                                 (0x07UL << SCU_SFSPF_11_MODE_Pos)                         /*!< SCU SFSPF_11: MODE Mask             */
+#define SCU_SFSPF_11_EPD_Pos                                  3                                                         /*!< SCU SFSPF_11: EPD Position          */
+#define SCU_SFSPF_11_EPD_Msk                                  (0x01UL << SCU_SFSPF_11_EPD_Pos)                          /*!< SCU SFSPF_11: EPD Mask              */
+#define SCU_SFSPF_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_11: EPUN Position         */
+#define SCU_SFSPF_11_EPUN_Msk                                 (0x01UL << SCU_SFSPF_11_EPUN_Pos)                         /*!< SCU SFSPF_11: EPUN Mask             */
+#define SCU_SFSPF_11_EHS_Pos                                  5                                                         /*!< SCU SFSPF_11: EHS Position          */
+#define SCU_SFSPF_11_EHS_Msk                                  (0x01UL << SCU_SFSPF_11_EHS_Pos)                          /*!< SCU SFSPF_11: EHS Mask              */
+#define SCU_SFSPF_11_EZI_Pos                                  6                                                         /*!< SCU SFSPF_11: EZI Position          */
+#define SCU_SFSPF_11_EZI_Msk                                  (0x01UL << SCU_SFSPF_11_EZI_Pos)                          /*!< SCU SFSPF_11: EZI Mask              */
+#define SCU_SFSPF_11_EHD_Pos                                  8                                                         /*!< SCU SFSPF_11: EHD Position          */
+#define SCU_SFSPF_11_EHD_Msk                                  (0x03UL << SCU_SFSPF_11_EHD_Pos)                          /*!< SCU SFSPF_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_0  ------------------------------------------
+#define SCU_SFSCLK_0_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_0: MODE Position         */
+#define SCU_SFSCLK_0_MODE_Msk                                 (0x07UL << SCU_SFSCLK_0_MODE_Pos)                         /*!< SCU SFSCLK_0: MODE Mask             */
+#define SCU_SFSCLK_0_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_0: EPD Position          */
+#define SCU_SFSCLK_0_EPD_Msk                                  (0x01UL << SCU_SFSCLK_0_EPD_Pos)                          /*!< SCU SFSCLK_0: EPD Mask              */
+#define SCU_SFSCLK_0_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_0: EPUN Position         */
+#define SCU_SFSCLK_0_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_0_EPUN_Pos)                         /*!< SCU SFSCLK_0: EPUN Mask             */
+#define SCU_SFSCLK_0_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_0: EHS Position          */
+#define SCU_SFSCLK_0_EHS_Msk                                  (0x01UL << SCU_SFSCLK_0_EHS_Pos)                          /*!< SCU SFSCLK_0: EHS Mask              */
+#define SCU_SFSCLK_0_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_0: EZI Position          */
+#define SCU_SFSCLK_0_EZI_Msk                                  (0x01UL << SCU_SFSCLK_0_EZI_Pos)                          /*!< SCU SFSCLK_0: EZI Mask              */
+#define SCU_SFSCLK_0_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_0: EHD Position          */
+#define SCU_SFSCLK_0_EHD_Msk                                  (0x03UL << SCU_SFSCLK_0_EHD_Pos)                          /*!< SCU SFSCLK_0: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_1  ------------------------------------------
+#define SCU_SFSCLK_1_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_1: MODE Position         */
+#define SCU_SFSCLK_1_MODE_Msk                                 (0x07UL << SCU_SFSCLK_1_MODE_Pos)                         /*!< SCU SFSCLK_1: MODE Mask             */
+#define SCU_SFSCLK_1_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_1: EPD Position          */
+#define SCU_SFSCLK_1_EPD_Msk                                  (0x01UL << SCU_SFSCLK_1_EPD_Pos)                          /*!< SCU SFSCLK_1: EPD Mask              */
+#define SCU_SFSCLK_1_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_1: EPUN Position         */
+#define SCU_SFSCLK_1_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_1_EPUN_Pos)                         /*!< SCU SFSCLK_1: EPUN Mask             */
+#define SCU_SFSCLK_1_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_1: EHS Position          */
+#define SCU_SFSCLK_1_EHS_Msk                                  (0x01UL << SCU_SFSCLK_1_EHS_Pos)                          /*!< SCU SFSCLK_1: EHS Mask              */
+#define SCU_SFSCLK_1_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_1: EZI Position          */
+#define SCU_SFSCLK_1_EZI_Msk                                  (0x01UL << SCU_SFSCLK_1_EZI_Pos)                          /*!< SCU SFSCLK_1: EZI Mask              */
+#define SCU_SFSCLK_1_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_1: EHD Position          */
+#define SCU_SFSCLK_1_EHD_Msk                                  (0x03UL << SCU_SFSCLK_1_EHD_Pos)                          /*!< SCU SFSCLK_1: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_2  ------------------------------------------
+#define SCU_SFSCLK_2_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_2: MODE Position         */
+#define SCU_SFSCLK_2_MODE_Msk                                 (0x07UL << SCU_SFSCLK_2_MODE_Pos)                         /*!< SCU SFSCLK_2: MODE Mask             */
+#define SCU_SFSCLK_2_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_2: EPD Position          */
+#define SCU_SFSCLK_2_EPD_Msk                                  (0x01UL << SCU_SFSCLK_2_EPD_Pos)                          /*!< SCU SFSCLK_2: EPD Mask              */
+#define SCU_SFSCLK_2_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_2: EPUN Position         */
+#define SCU_SFSCLK_2_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_2_EPUN_Pos)                         /*!< SCU SFSCLK_2: EPUN Mask             */
+#define SCU_SFSCLK_2_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_2: EHS Position          */
+#define SCU_SFSCLK_2_EHS_Msk                                  (0x01UL << SCU_SFSCLK_2_EHS_Pos)                          /*!< SCU SFSCLK_2: EHS Mask              */
+#define SCU_SFSCLK_2_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_2: EZI Position          */
+#define SCU_SFSCLK_2_EZI_Msk                                  (0x01UL << SCU_SFSCLK_2_EZI_Pos)                          /*!< SCU SFSCLK_2: EZI Mask              */
+#define SCU_SFSCLK_2_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_2: EHD Position          */
+#define SCU_SFSCLK_2_EHD_Msk                                  (0x03UL << SCU_SFSCLK_2_EHD_Pos)                          /*!< SCU SFSCLK_2: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_3  ------------------------------------------
+#define SCU_SFSCLK_3_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_3: MODE Position         */
+#define SCU_SFSCLK_3_MODE_Msk                                 (0x07UL << SCU_SFSCLK_3_MODE_Pos)                         /*!< SCU SFSCLK_3: MODE Mask             */
+#define SCU_SFSCLK_3_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_3: EPD Position          */
+#define SCU_SFSCLK_3_EPD_Msk                                  (0x01UL << SCU_SFSCLK_3_EPD_Pos)                          /*!< SCU SFSCLK_3: EPD Mask              */
+#define SCU_SFSCLK_3_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_3: EPUN Position         */
+#define SCU_SFSCLK_3_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_3_EPUN_Pos)                         /*!< SCU SFSCLK_3: EPUN Mask             */
+#define SCU_SFSCLK_3_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_3: EHS Position          */
+#define SCU_SFSCLK_3_EHS_Msk                                  (0x01UL << SCU_SFSCLK_3_EHS_Pos)                          /*!< SCU SFSCLK_3: EHS Mask              */
+#define SCU_SFSCLK_3_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_3: EZI Position          */
+#define SCU_SFSCLK_3_EZI_Msk                                  (0x01UL << SCU_SFSCLK_3_EZI_Pos)                          /*!< SCU SFSCLK_3: EZI Mask              */
+#define SCU_SFSCLK_3_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_3: EHD Position          */
+#define SCU_SFSCLK_3_EHD_Msk                                  (0x03UL << SCU_SFSCLK_3_EHD_Pos)                          /*!< SCU SFSCLK_3: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSUSB  -------------------------------------------
+#define SCU_SFSUSB_USB_AIM_Pos                                0                                                         /*!< SCU SFSUSB: USB_AIM Position        */
+#define SCU_SFSUSB_USB_AIM_Msk                                (0x01UL << SCU_SFSUSB_USB_AIM_Pos)                        /*!< SCU SFSUSB: USB_AIM Mask            */
+#define SCU_SFSUSB_USB_ESEA_Pos                               1                                                         /*!< SCU SFSUSB: USB_ESEA Position       */
+#define SCU_SFSUSB_USB_ESEA_Msk                               (0x01UL << SCU_SFSUSB_USB_ESEA_Pos)                       /*!< SCU SFSUSB: USB_ESEA Mask           */
+
+// ---------------------------------------  SCU_SFSI2C0  ------------------------------------------
+#define SCU_SFSI2C0_SDA_EHS_Pos                               0                                                         /*!< SCU SFSI2C0: SDA_EHS Position       */
+#define SCU_SFSI2C0_SDA_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos)                       /*!< SCU SFSI2C0: SDA_EHS Mask           */
+#define SCU_SFSI2C0_SCL_EHS_Pos                               1                                                         /*!< SCU SFSI2C0: SCL_EHS Position       */
+#define SCU_SFSI2C0_SCL_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos)                       /*!< SCU SFSI2C0: SCL_EHS Mask           */
+#define SCU_SFSI2C0_SCL_ECS_Pos                               2                                                         /*!< SCU SFSI2C0: SCL_ECS Position       */
+#define SCU_SFSI2C0_SCL_ECS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos)                       /*!< SCU SFSI2C0: SCL_ECS Mask           */
+
+// ---------------------------------------  SCU_ENAIO0  -------------------------------------------
+#define SCU_ENAIO0_ADC0_0_Pos                                 0                                                         /*!< SCU ENAIO0: ADC0_0 Position         */
+#define SCU_ENAIO0_ADC0_0_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_0_Pos)                         /*!< SCU ENAIO0: ADC0_0 Mask             */
+#define SCU_ENAIO0_ADC0_1_Pos                                 1                                                         /*!< SCU ENAIO0: ADC0_1 Position         */
+#define SCU_ENAIO0_ADC0_1_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_1_Pos)                         /*!< SCU ENAIO0: ADC0_1 Mask             */
+#define SCU_ENAIO0_ADC0_2_Pos                                 2                                                         /*!< SCU ENAIO0: ADC0_2 Position         */
+#define SCU_ENAIO0_ADC0_2_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_2_Pos)                         /*!< SCU ENAIO0: ADC0_2 Mask             */
+#define SCU_ENAIO0_ADC0_3_Pos                                 3                                                         /*!< SCU ENAIO0: ADC0_3 Position         */
+#define SCU_ENAIO0_ADC0_3_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_3_Pos)                         /*!< SCU ENAIO0: ADC0_3 Mask             */
+#define SCU_ENAIO0_ADC0_4_Pos                                 4                                                         /*!< SCU ENAIO0: ADC0_4 Position         */
+#define SCU_ENAIO0_ADC0_4_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_4_Pos)                         /*!< SCU ENAIO0: ADC0_4 Mask             */
+#define SCU_ENAIO0_ADC0_5_Pos                                 5                                                         /*!< SCU ENAIO0: ADC0_5 Position         */
+#define SCU_ENAIO0_ADC0_5_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_5_Pos)                         /*!< SCU ENAIO0: ADC0_5 Mask             */
+#define SCU_ENAIO0_ADC0_6_Pos                                 6                                                         /*!< SCU ENAIO0: ADC0_6 Position         */
+#define SCU_ENAIO0_ADC0_6_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_6_Pos)                         /*!< SCU ENAIO0: ADC0_6 Mask             */
+
+// ---------------------------------------  SCU_ENAIO1  -------------------------------------------
+#define SCU_ENAIO1_ADC1_0_Pos                                 0                                                         /*!< SCU ENAIO1: ADC1_0 Position         */
+#define SCU_ENAIO1_ADC1_0_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_0_Pos)                         /*!< SCU ENAIO1: ADC1_0 Mask             */
+#define SCU_ENAIO1_ADC1_1_Pos                                 1                                                         /*!< SCU ENAIO1: ADC1_1 Position         */
+#define SCU_ENAIO1_ADC1_1_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_1_Pos)                         /*!< SCU ENAIO1: ADC1_1 Mask             */
+#define SCU_ENAIO1_ADC1_2_Pos                                 2                                                         /*!< SCU ENAIO1: ADC1_2 Position         */
+#define SCU_ENAIO1_ADC1_2_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_2_Pos)                         /*!< SCU ENAIO1: ADC1_2 Mask             */
+#define SCU_ENAIO1_ADC1_3_Pos                                 3                                                         /*!< SCU ENAIO1: ADC1_3 Position         */
+#define SCU_ENAIO1_ADC1_3_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_3_Pos)                         /*!< SCU ENAIO1: ADC1_3 Mask             */
+#define SCU_ENAIO1_ADC1_4_Pos                                 4                                                         /*!< SCU ENAIO1: ADC1_4 Position         */
+#define SCU_ENAIO1_ADC1_4_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_4_Pos)                         /*!< SCU ENAIO1: ADC1_4 Mask             */
+#define SCU_ENAIO1_ADC1_5_Pos                                 5                                                         /*!< SCU ENAIO1: ADC1_5 Position         */
+#define SCU_ENAIO1_ADC1_5_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_5_Pos)                         /*!< SCU ENAIO1: ADC1_5 Mask             */
+#define SCU_ENAIO1_ADC1_6_Pos                                 6                                                         /*!< SCU ENAIO1: ADC1_6 Position         */
+#define SCU_ENAIO1_ADC1_6_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_6_Pos)                         /*!< SCU ENAIO1: ADC1_6 Mask             */
+#define SCU_ENAIO1_ADC1_7_Pos                                 7                                                         /*!< SCU ENAIO1: ADC1_7 Position         */
+#define SCU_ENAIO1_ADC1_7_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_7_Pos)                         /*!< SCU ENAIO1: ADC1_7 Mask             */
+
+// ---------------------------------------  SCU_ENAIO2  -------------------------------------------
+#define SCU_ENAIO2_DAC_Pos                                    0                                                         /*!< SCU ENAIO2: DAC Position            */
+#define SCU_ENAIO2_DAC_Msk                                    (0x01UL << SCU_ENAIO2_DAC_Pos)                            /*!< SCU ENAIO2: DAC Mask                */
+#define SCU_ENAIO2_BG_Pos                                     4                                                         /*!< SCU ENAIO2: BG Position             */
+#define SCU_ENAIO2_BG_Msk                                     (0x01UL << SCU_ENAIO2_BG_Pos)                             /*!< SCU ENAIO2: BG Mask                 */
+
+// -------------------------------------  SCU_EMCDELAYCLK  ----------------------------------------
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos                        0                                                         /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos                        4                                                         /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos                        8                                                         /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos                        12                                                        /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos                        16                                                        /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos                        20                                                        /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos                        24                                                        /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos                        28                                                        /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask    */
+
+// --------------------------------------  SCU_PINTSEL0  ------------------------------------------
+#define SCU_PINTSEL0_INTPIN0_Pos                              0                                                         /*!< SCU PINTSEL0: INTPIN0 Position      */
+#define SCU_PINTSEL0_INTPIN0_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos)                      /*!< SCU PINTSEL0: INTPIN0 Mask          */
+#define SCU_PINTSEL0_PORTSEL0_Pos                             5                                                         /*!< SCU PINTSEL0: PORTSEL0 Position     */
+#define SCU_PINTSEL0_PORTSEL0_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos)                     /*!< SCU PINTSEL0: PORTSEL0 Mask         */
+#define SCU_PINTSEL0_INTPIN1_Pos                              8                                                         /*!< SCU PINTSEL0: INTPIN1 Position      */
+#define SCU_PINTSEL0_INTPIN1_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos)                      /*!< SCU PINTSEL0: INTPIN1 Mask          */
+#define SCU_PINTSEL0_PORTSEL1_Pos                             13                                                        /*!< SCU PINTSEL0: PORTSEL1 Position     */
+#define SCU_PINTSEL0_PORTSEL1_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos)                     /*!< SCU PINTSEL0: PORTSEL1 Mask         */
+#define SCU_PINTSEL0_INTPIN2_Pos                              16                                                        /*!< SCU PINTSEL0: INTPIN2 Position      */
+#define SCU_PINTSEL0_INTPIN2_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos)                      /*!< SCU PINTSEL0: INTPIN2 Mask          */
+#define SCU_PINTSEL0_PORTSEL2_Pos                             21                                                        /*!< SCU PINTSEL0: PORTSEL2 Position     */
+#define SCU_PINTSEL0_PORTSEL2_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos)                     /*!< SCU PINTSEL0: PORTSEL2 Mask         */
+#define SCU_PINTSEL0_INTPIN3_Pos                              24                                                        /*!< SCU PINTSEL0: INTPIN3 Position      */
+#define SCU_PINTSEL0_INTPIN3_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos)                      /*!< SCU PINTSEL0: INTPIN3 Mask          */
+#define SCU_PINTSEL0_PORTSEL3_Pos                             29                                                        /*!< SCU PINTSEL0: PORTSEL3 Position     */
+#define SCU_PINTSEL0_PORTSEL3_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos)                     /*!< SCU PINTSEL0: PORTSEL3 Mask         */
+
+// --------------------------------------  SCU_PINTSEL1  ------------------------------------------
+#define SCU_PINTSEL1_INTPIN4_Pos                              0                                                         /*!< SCU PINTSEL1: INTPIN4 Position      */
+#define SCU_PINTSEL1_INTPIN4_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos)                      /*!< SCU PINTSEL1: INTPIN4 Mask          */
+#define SCU_PINTSEL1_PORTSEL4_Pos                             5                                                         /*!< SCU PINTSEL1: PORTSEL4 Position     */
+#define SCU_PINTSEL1_PORTSEL4_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos)                     /*!< SCU PINTSEL1: PORTSEL4 Mask         */
+#define SCU_PINTSEL1_INTPIN5_Pos                              8                                                         /*!< SCU PINTSEL1: INTPIN5 Position      */
+#define SCU_PINTSEL1_INTPIN5_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos)                      /*!< SCU PINTSEL1: INTPIN5 Mask          */
+#define SCU_PINTSEL1_PORTSEL5_Pos                             13                                                        /*!< SCU PINTSEL1: PORTSEL5 Position     */
+#define SCU_PINTSEL1_PORTSEL5_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos)                     /*!< SCU PINTSEL1: PORTSEL5 Mask         */
+#define SCU_PINTSEL1_INTPIN6_Pos                              16                                                        /*!< SCU PINTSEL1: INTPIN6 Position      */
+#define SCU_PINTSEL1_INTPIN6_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos)                      /*!< SCU PINTSEL1: INTPIN6 Mask          */
+#define SCU_PINTSEL1_PORTSEL6_Pos                             21                                                        /*!< SCU PINTSEL1: PORTSEL6 Position     */
+#define SCU_PINTSEL1_PORTSEL6_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos)                     /*!< SCU PINTSEL1: PORTSEL6 Mask         */
+#define SCU_PINTSEL1_INTPIN7_Pos                              24                                                        /*!< SCU PINTSEL1: INTPIN7 Position      */
+#define SCU_PINTSEL1_INTPIN7_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos)                      /*!< SCU PINTSEL1: INTPIN7 Mask          */
+#define SCU_PINTSEL1_PORTSEL7_Pos                             29                                                        /*!< SCU PINTSEL1: PORTSEL7 Position     */
+#define SCU_PINTSEL1_PORTSEL7_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos)                     /*!< SCU PINTSEL1: PORTSEL7 Mask         */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                             GPIO_PIN_INT Position & Mask                             -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------  GPIO_PIN_INT_ISEL  ---------------------------------------
+#define GPIO_PIN_INT_ISEL_PMODE0_Pos                          0                                                         /*!< GPIO_PIN_INT ISEL: PMODE0 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE0_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE0 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE1_Pos                          1                                                         /*!< GPIO_PIN_INT ISEL: PMODE1 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE1_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE1 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE2_Pos                          2                                                         /*!< GPIO_PIN_INT ISEL: PMODE2 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE2_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE2 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE3_Pos                          3                                                         /*!< GPIO_PIN_INT ISEL: PMODE3 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE3_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE3 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE4_Pos                          4                                                         /*!< GPIO_PIN_INT ISEL: PMODE4 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE4_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE4 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE5_Pos                          5                                                         /*!< GPIO_PIN_INT ISEL: PMODE5 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE5_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE5 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE6_Pos                          6                                                         /*!< GPIO_PIN_INT ISEL: PMODE6 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE6_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE6 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE7_Pos                          7                                                         /*!< GPIO_PIN_INT ISEL: PMODE7 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE7_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE7 Mask      */
+
+// ------------------------------------  GPIO_PIN_INT_IENR  ---------------------------------------
+#define GPIO_PIN_INT_IENR_ENRL0_Pos                           0                                                         /*!< GPIO_PIN_INT IENR: ENRL0 Position   */
+#define GPIO_PIN_INT_IENR_ENRL0_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL0 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL1_Pos                           1                                                         /*!< GPIO_PIN_INT IENR: ENRL1 Position   */
+#define GPIO_PIN_INT_IENR_ENRL1_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL1 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL2_Pos                           2                                                         /*!< GPIO_PIN_INT IENR: ENRL2 Position   */
+#define GPIO_PIN_INT_IENR_ENRL2_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL2 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL3_Pos                           3                                                         /*!< GPIO_PIN_INT IENR: ENRL3 Position   */
+#define GPIO_PIN_INT_IENR_ENRL3_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL3 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL4_Pos                           4                                                         /*!< GPIO_PIN_INT IENR: ENRL4 Position   */
+#define GPIO_PIN_INT_IENR_ENRL4_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL4 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL5_Pos                           5                                                         /*!< GPIO_PIN_INT IENR: ENRL5 Position   */
+#define GPIO_PIN_INT_IENR_ENRL5_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL5 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL6_Pos                           6                                                         /*!< GPIO_PIN_INT IENR: ENRL6 Position   */
+#define GPIO_PIN_INT_IENR_ENRL6_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL6 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL7_Pos                           7                                                         /*!< GPIO_PIN_INT IENR: ENRL7 Position   */
+#define GPIO_PIN_INT_IENR_ENRL7_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL7 Mask       */
+
+// -----------------------------------  GPIO_PIN_INT_SIENR  ---------------------------------------
+#define GPIO_PIN_INT_SIENR_SETENRL0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL0_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask   */
+
+// -----------------------------------  GPIO_PIN_INT_CIENR  ---------------------------------------
+#define GPIO_PIN_INT_CIENR_CENRL0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENR: CENRL0 Position */
+#define GPIO_PIN_INT_CIENR_CENRL0_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL0 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENR: CENRL1 Position */
+#define GPIO_PIN_INT_CIENR_CENRL1_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL1 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENR: CENRL2 Position */
+#define GPIO_PIN_INT_CIENR_CENRL2_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL2 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENR: CENRL3 Position */
+#define GPIO_PIN_INT_CIENR_CENRL3_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL3 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENR: CENRL4 Position */
+#define GPIO_PIN_INT_CIENR_CENRL4_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL4 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENR: CENRL5 Position */
+#define GPIO_PIN_INT_CIENR_CENRL5_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL5 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENR: CENRL6 Position */
+#define GPIO_PIN_INT_CIENR_CENRL6_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL6 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENR: CENRL7 Position */
+#define GPIO_PIN_INT_CIENR_CENRL7_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL7 Mask     */
+
+// ------------------------------------  GPIO_PIN_INT_IENF  ---------------------------------------
+#define GPIO_PIN_INT_IENF_ENAF0_Pos                           0                                                         /*!< GPIO_PIN_INT IENF: ENAF0 Position   */
+#define GPIO_PIN_INT_IENF_ENAF0_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF0 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF1_Pos                           1                                                         /*!< GPIO_PIN_INT IENF: ENAF1 Position   */
+#define GPIO_PIN_INT_IENF_ENAF1_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF1 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF2_Pos                           2                                                         /*!< GPIO_PIN_INT IENF: ENAF2 Position   */
+#define GPIO_PIN_INT_IENF_ENAF2_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF2 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF3_Pos                           3                                                         /*!< GPIO_PIN_INT IENF: ENAF3 Position   */
+#define GPIO_PIN_INT_IENF_ENAF3_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF3 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF4_Pos                           4                                                         /*!< GPIO_PIN_INT IENF: ENAF4 Position   */
+#define GPIO_PIN_INT_IENF_ENAF4_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF4 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF5_Pos                           5                                                         /*!< GPIO_PIN_INT IENF: ENAF5 Position   */
+#define GPIO_PIN_INT_IENF_ENAF5_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF5 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF6_Pos                           6                                                         /*!< GPIO_PIN_INT IENF: ENAF6 Position   */
+#define GPIO_PIN_INT_IENF_ENAF6_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF6 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF7_Pos                           7                                                         /*!< GPIO_PIN_INT IENF: ENAF7 Position   */
+#define GPIO_PIN_INT_IENF_ENAF7_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF7 Mask       */
+
+// -----------------------------------  GPIO_PIN_INT_SIENF  ---------------------------------------
+#define GPIO_PIN_INT_SIENF_SETENAF0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF0_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask   */
+
+// -----------------------------------  GPIO_PIN_INT_CIENF  ---------------------------------------
+#define GPIO_PIN_INT_CIENF_CENAF0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENF: CENAF0 Position */
+#define GPIO_PIN_INT_CIENF_CENAF0_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF0 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENF: CENAF1 Position */
+#define GPIO_PIN_INT_CIENF_CENAF1_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF1 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENF: CENAF2 Position */
+#define GPIO_PIN_INT_CIENF_CENAF2_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF2 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENF: CENAF3 Position */
+#define GPIO_PIN_INT_CIENF_CENAF3_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF3 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENF: CENAF4 Position */
+#define GPIO_PIN_INT_CIENF_CENAF4_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF4 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENF: CENAF5 Position */
+#define GPIO_PIN_INT_CIENF_CENAF5_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF5 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENF: CENAF6 Position */
+#define GPIO_PIN_INT_CIENF_CENAF6_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF6 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENF: CENAF7 Position */
+#define GPIO_PIN_INT_CIENF_CENAF7_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF7 Mask     */
+
+// ------------------------------------  GPIO_PIN_INT_RISE  ---------------------------------------
+#define GPIO_PIN_INT_RISE_RDET0_Pos                           0                                                         /*!< GPIO_PIN_INT RISE: RDET0 Position   */
+#define GPIO_PIN_INT_RISE_RDET0_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos)                   /*!< GPIO_PIN_INT RISE: RDET0 Mask       */
+#define GPIO_PIN_INT_RISE_RDET1_Pos                           1                                                         /*!< GPIO_PIN_INT RISE: RDET1 Position   */
+#define GPIO_PIN_INT_RISE_RDET1_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos)                   /*!< GPIO_PIN_INT RISE: RDET1 Mask       */
+#define GPIO_PIN_INT_RISE_RDET2_Pos                           2                                                         /*!< GPIO_PIN_INT RISE: RDET2 Position   */
+#define GPIO_PIN_INT_RISE_RDET2_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos)                   /*!< GPIO_PIN_INT RISE: RDET2 Mask       */
+#define GPIO_PIN_INT_RISE_RDET3_Pos                           3                                                         /*!< GPIO_PIN_INT RISE: RDET3 Position   */
+#define GPIO_PIN_INT_RISE_RDET3_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos)                   /*!< GPIO_PIN_INT RISE: RDET3 Mask       */
+#define GPIO_PIN_INT_RISE_RDET4_Pos                           4                                                         /*!< GPIO_PIN_INT RISE: RDET4 Position   */
+#define GPIO_PIN_INT_RISE_RDET4_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos)                   /*!< GPIO_PIN_INT RISE: RDET4 Mask       */
+#define GPIO_PIN_INT_RISE_RDET5_Pos                           5                                                         /*!< GPIO_PIN_INT RISE: RDET5 Position   */
+#define GPIO_PIN_INT_RISE_RDET5_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos)                   /*!< GPIO_PIN_INT RISE: RDET5 Mask       */
+#define GPIO_PIN_INT_RISE_RDET6_Pos                           6                                                         /*!< GPIO_PIN_INT RISE: RDET6 Position   */
+#define GPIO_PIN_INT_RISE_RDET6_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos)                   /*!< GPIO_PIN_INT RISE: RDET6 Mask       */
+#define GPIO_PIN_INT_RISE_RDET7_Pos                           7                                                         /*!< GPIO_PIN_INT RISE: RDET7 Position   */
+#define GPIO_PIN_INT_RISE_RDET7_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos)                   /*!< GPIO_PIN_INT RISE: RDET7 Mask       */
+
+// ------------------------------------  GPIO_PIN_INT_FALL  ---------------------------------------
+#define GPIO_PIN_INT_FALL_FDET0_Pos                           0                                                         /*!< GPIO_PIN_INT FALL: FDET0 Position   */
+#define GPIO_PIN_INT_FALL_FDET0_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos)                   /*!< GPIO_PIN_INT FALL: FDET0 Mask       */
+#define GPIO_PIN_INT_FALL_FDET1_Pos                           1                                                         /*!< GPIO_PIN_INT FALL: FDET1 Position   */
+#define GPIO_PIN_INT_FALL_FDET1_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos)                   /*!< GPIO_PIN_INT FALL: FDET1 Mask       */
+#define GPIO_PIN_INT_FALL_FDET2_Pos                           2                                                         /*!< GPIO_PIN_INT FALL: FDET2 Position   */
+#define GPIO_PIN_INT_FALL_FDET2_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos)                   /*!< GPIO_PIN_INT FALL: FDET2 Mask       */
+#define GPIO_PIN_INT_FALL_FDET3_Pos                           3                                                         /*!< GPIO_PIN_INT FALL: FDET3 Position   */
+#define GPIO_PIN_INT_FALL_FDET3_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos)                   /*!< GPIO_PIN_INT FALL: FDET3 Mask       */
+#define GPIO_PIN_INT_FALL_FDET4_Pos                           4                                                         /*!< GPIO_PIN_INT FALL: FDET4 Position   */
+#define GPIO_PIN_INT_FALL_FDET4_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos)                   /*!< GPIO_PIN_INT FALL: FDET4 Mask       */
+#define GPIO_PIN_INT_FALL_FDET5_Pos                           5                                                         /*!< GPIO_PIN_INT FALL: FDET5 Position   */
+#define GPIO_PIN_INT_FALL_FDET5_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos)                   /*!< GPIO_PIN_INT FALL: FDET5 Mask       */
+#define GPIO_PIN_INT_FALL_FDET6_Pos                           6                                                         /*!< GPIO_PIN_INT FALL: FDET6 Position   */
+#define GPIO_PIN_INT_FALL_FDET6_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos)                   /*!< GPIO_PIN_INT FALL: FDET6 Mask       */
+#define GPIO_PIN_INT_FALL_FDET7_Pos                           7                                                         /*!< GPIO_PIN_INT FALL: FDET7 Position   */
+#define GPIO_PIN_INT_FALL_FDET7_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos)                   /*!< GPIO_PIN_INT FALL: FDET7 Mask       */
+
+// ------------------------------------  GPIO_PIN_INT_IST  ----------------------------------------
+#define GPIO_PIN_INT_IST_PSTAT0_Pos                           0                                                         /*!< GPIO_PIN_INT IST: PSTAT0 Position   */
+#define GPIO_PIN_INT_IST_PSTAT0_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT0 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT1_Pos                           1                                                         /*!< GPIO_PIN_INT IST: PSTAT1 Position   */
+#define GPIO_PIN_INT_IST_PSTAT1_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT1 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT2_Pos                           2                                                         /*!< GPIO_PIN_INT IST: PSTAT2 Position   */
+#define GPIO_PIN_INT_IST_PSTAT2_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT2 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT3_Pos                           3                                                         /*!< GPIO_PIN_INT IST: PSTAT3 Position   */
+#define GPIO_PIN_INT_IST_PSTAT3_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT3 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT4_Pos                           4                                                         /*!< GPIO_PIN_INT IST: PSTAT4 Position   */
+#define GPIO_PIN_INT_IST_PSTAT4_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT4 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT5_Pos                           5                                                         /*!< GPIO_PIN_INT IST: PSTAT5 Position   */
+#define GPIO_PIN_INT_IST_PSTAT5_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT5 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT6_Pos                           6                                                         /*!< GPIO_PIN_INT IST: PSTAT6 Position   */
+#define GPIO_PIN_INT_IST_PSTAT6_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT6 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT7_Pos                           7                                                         /*!< GPIO_PIN_INT IST: PSTAT7 Position   */
+#define GPIO_PIN_INT_IST_PSTAT7_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT7 Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                            GPIO_GROUP_INTn Position & Mask                           -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------  GPIO_GROUP_INTn_CTRL  --------------------------------------
+#define GPIO_GROUP_INTn_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INTn CTRL: INT Position  */
+#define GPIO_GROUP_INTn_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INTn CTRL: INT Mask      */
+#define GPIO_GROUP_INTn_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INTn CTRL: COMB Position */
+#define GPIO_GROUP_INTn_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INTn CTRL: COMB Mask     */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INTn CTRL: TRIG Position */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INTn CTRL: TRIG Mask     */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL0  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL1  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL2  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL3  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL4  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL5  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL6  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL7  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA0  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA1  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA2  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA3  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA4  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA5  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA6  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA7  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                            GPIO_GROUP_INT1 Position & Mask                           -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------  GPIO_GROUP_INT1_CTRL  --------------------------------------
+#define GPIO_GROUP_INT1_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INT1 CTRL: INT Position  */
+#define GPIO_GROUP_INT1_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INT1 CTRL: INT Mask      */
+#define GPIO_GROUP_INT1_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INT1 CTRL: COMB Position */
+#define GPIO_GROUP_INT1_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: COMB Mask     */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask     */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL0  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL1  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL2  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL3  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL4  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL5  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL6  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL7  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA0  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA1  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA2  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA3  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA4  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA5  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA6  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA7  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 MCPWM Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  MCPWM_CON  -------------------------------------------
+#define MCPWM_CON_RUN0_Pos                                    0                                                         /*!< MCPWM CON: RUN0 Position            */
+#define MCPWM_CON_RUN0_Msk                                    (0x01UL << MCPWM_CON_RUN0_Pos)                            /*!< MCPWM CON: RUN0 Mask                */
+#define MCPWM_CON_CENTER0_Pos                                 1                                                         /*!< MCPWM CON: CENTER0 Position         */
+#define MCPWM_CON_CENTER0_Msk                                 (0x01UL << MCPWM_CON_CENTER0_Pos)                         /*!< MCPWM CON: CENTER0 Mask             */
+#define MCPWM_CON_POLA0_Pos                                   2                                                         /*!< MCPWM CON: POLA0 Position           */
+#define MCPWM_CON_POLA0_Msk                                   (0x01UL << MCPWM_CON_POLA0_Pos)                           /*!< MCPWM CON: POLA0 Mask               */
+#define MCPWM_CON_DTE0_Pos                                    3                                                         /*!< MCPWM CON: DTE0 Position            */
+#define MCPWM_CON_DTE0_Msk                                    (0x01UL << MCPWM_CON_DTE0_Pos)                            /*!< MCPWM CON: DTE0 Mask                */
+#define MCPWM_CON_DISUP0_Pos                                  4                                                         /*!< MCPWM CON: DISUP0 Position          */
+#define MCPWM_CON_DISUP0_Msk                                  (0x01UL << MCPWM_CON_DISUP0_Pos)                          /*!< MCPWM CON: DISUP0 Mask              */
+#define MCPWM_CON_RUN1_Pos                                    8                                                         /*!< MCPWM CON: RUN1 Position            */
+#define MCPWM_CON_RUN1_Msk                                    (0x01UL << MCPWM_CON_RUN1_Pos)                            /*!< MCPWM CON: RUN1 Mask                */
+#define MCPWM_CON_CENTER1_Pos                                 9                                                         /*!< MCPWM CON: CENTER1 Position         */
+#define MCPWM_CON_CENTER1_Msk                                 (0x01UL << MCPWM_CON_CENTER1_Pos)                         /*!< MCPWM CON: CENTER1 Mask             */
+#define MCPWM_CON_POLA1_Pos                                   10                                                        /*!< MCPWM CON: POLA1 Position           */
+#define MCPWM_CON_POLA1_Msk                                   (0x01UL << MCPWM_CON_POLA1_Pos)                           /*!< MCPWM CON: POLA1 Mask               */
+#define MCPWM_CON_DTE1_Pos                                    11                                                        /*!< MCPWM CON: DTE1 Position            */
+#define MCPWM_CON_DTE1_Msk                                    (0x01UL << MCPWM_CON_DTE1_Pos)                            /*!< MCPWM CON: DTE1 Mask                */
+#define MCPWM_CON_DISUP1_Pos                                  12                                                        /*!< MCPWM CON: DISUP1 Position          */
+#define MCPWM_CON_DISUP1_Msk                                  (0x01UL << MCPWM_CON_DISUP1_Pos)                          /*!< MCPWM CON: DISUP1 Mask              */
+#define MCPWM_CON_RUN2_Pos                                    16                                                        /*!< MCPWM CON: RUN2 Position            */
+#define MCPWM_CON_RUN2_Msk                                    (0x01UL << MCPWM_CON_RUN2_Pos)                            /*!< MCPWM CON: RUN2 Mask                */
+#define MCPWM_CON_CENTER2_Pos                                 17                                                        /*!< MCPWM CON: CENTER2 Position         */
+#define MCPWM_CON_CENTER2_Msk                                 (0x01UL << MCPWM_CON_CENTER2_Pos)                         /*!< MCPWM CON: CENTER2 Mask             */
+#define MCPWM_CON_POLA2_Pos                                   18                                                        /*!< MCPWM CON: POLA2 Position           */
+#define MCPWM_CON_POLA2_Msk                                   (0x01UL << MCPWM_CON_POLA2_Pos)                           /*!< MCPWM CON: POLA2 Mask               */
+#define MCPWM_CON_DTE2_Pos                                    19                                                        /*!< MCPWM CON: DTE2 Position            */
+#define MCPWM_CON_DTE2_Msk                                    (0x01UL << MCPWM_CON_DTE2_Pos)                            /*!< MCPWM CON: DTE2 Mask                */
+#define MCPWM_CON_DISUP2_Pos                                  20                                                        /*!< MCPWM CON: DISUP2 Position          */
+#define MCPWM_CON_DISUP2_Msk                                  (0x01UL << MCPWM_CON_DISUP2_Pos)                          /*!< MCPWM CON: DISUP2 Mask              */
+#define MCPWM_CON_INVBDC_Pos                                  29                                                        /*!< MCPWM CON: INVBDC Position          */
+#define MCPWM_CON_INVBDC_Msk                                  (0x01UL << MCPWM_CON_INVBDC_Pos)                          /*!< MCPWM CON: INVBDC Mask              */
+#define MCPWM_CON_ACMODE_Pos                                  30                                                        /*!< MCPWM CON: ACMODE Position          */
+#define MCPWM_CON_ACMODE_Msk                                  (0x01UL << MCPWM_CON_ACMODE_Pos)                          /*!< MCPWM CON: ACMODE Mask              */
+#define MCPWM_CON_DCMODE_Pos                                  31                                                        /*!< MCPWM CON: DCMODE Position          */
+#define MCPWM_CON_DCMODE_Msk                                  (0x01UL << MCPWM_CON_DCMODE_Pos)                          /*!< MCPWM CON: DCMODE Mask              */
+
+// --------------------------------------  MCPWM_CON_SET  -----------------------------------------
+#define MCPWM_CON_SET_RUN0_SET_Pos                            0                                                         /*!< MCPWM CON_SET: RUN0_SET Position    */
+#define MCPWM_CON_SET_RUN0_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos)                    /*!< MCPWM CON_SET: RUN0_SET Mask        */
+#define MCPWM_CON_SET_CENTER0_SET_Pos                         1                                                         /*!< MCPWM CON_SET: CENTER0_SET Position */
+#define MCPWM_CON_SET_CENTER0_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos)                 /*!< MCPWM CON_SET: CENTER0_SET Mask     */
+#define MCPWM_CON_SET_POLA0_SET_Pos                           2                                                         /*!< MCPWM CON_SET: POLA0_SET Position   */
+#define MCPWM_CON_SET_POLA0_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos)                   /*!< MCPWM CON_SET: POLA0_SET Mask       */
+#define MCPWM_CON_SET_DTE0_SET_Pos                            3                                                         /*!< MCPWM CON_SET: DTE0_SET Position    */
+#define MCPWM_CON_SET_DTE0_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos)                    /*!< MCPWM CON_SET: DTE0_SET Mask        */
+#define MCPWM_CON_SET_DISUP0_SET_Pos                          4                                                         /*!< MCPWM CON_SET: DISUP0_SET Position  */
+#define MCPWM_CON_SET_DISUP0_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos)                  /*!< MCPWM CON_SET: DISUP0_SET Mask      */
+#define MCPWM_CON_SET_RUN1_SET_Pos                            8                                                         /*!< MCPWM CON_SET: RUN1_SET Position    */
+#define MCPWM_CON_SET_RUN1_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos)                    /*!< MCPWM CON_SET: RUN1_SET Mask        */
+#define MCPWM_CON_SET_CENTER1_SET_Pos                         9                                                         /*!< MCPWM CON_SET: CENTER1_SET Position */
+#define MCPWM_CON_SET_CENTER1_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos)                 /*!< MCPWM CON_SET: CENTER1_SET Mask     */
+#define MCPWM_CON_SET_POLA1_SET_Pos                           10                                                        /*!< MCPWM CON_SET: POLA1_SET Position   */
+#define MCPWM_CON_SET_POLA1_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos)                   /*!< MCPWM CON_SET: POLA1_SET Mask       */
+#define MCPWM_CON_SET_DTE1_SET_Pos                            11                                                        /*!< MCPWM CON_SET: DTE1_SET Position    */
+#define MCPWM_CON_SET_DTE1_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos)                    /*!< MCPWM CON_SET: DTE1_SET Mask        */
+#define MCPWM_CON_SET_DISUP1_SET_Pos                          12                                                        /*!< MCPWM CON_SET: DISUP1_SET Position  */
+#define MCPWM_CON_SET_DISUP1_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos)                  /*!< MCPWM CON_SET: DISUP1_SET Mask      */
+#define MCPWM_CON_SET_RUN2_SET_Pos                            16                                                        /*!< MCPWM CON_SET: RUN2_SET Position    */
+#define MCPWM_CON_SET_RUN2_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos)                    /*!< MCPWM CON_SET: RUN2_SET Mask        */
+#define MCPWM_CON_SET_CENTER2_SET_Pos                         17                                                        /*!< MCPWM CON_SET: CENTER2_SET Position */
+#define MCPWM_CON_SET_CENTER2_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos)                 /*!< MCPWM CON_SET: CENTER2_SET Mask     */
+#define MCPWM_CON_SET_POLA2_SET_Pos                           18                                                        /*!< MCPWM CON_SET: POLA2_SET Position   */
+#define MCPWM_CON_SET_POLA2_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos)                   /*!< MCPWM CON_SET: POLA2_SET Mask       */
+#define MCPWM_CON_SET_DTE2_SET_Pos                            19                                                        /*!< MCPWM CON_SET: DTE2_SET Position    */
+#define MCPWM_CON_SET_DTE2_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos)                    /*!< MCPWM CON_SET: DTE2_SET Mask        */
+#define MCPWM_CON_SET_DISUP2_SET_Pos                          20                                                        /*!< MCPWM CON_SET: DISUP2_SET Position  */
+#define MCPWM_CON_SET_DISUP2_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos)                  /*!< MCPWM CON_SET: DISUP2_SET Mask      */
+#define MCPWM_CON_SET_INVBDC_SET_Pos                          29                                                        /*!< MCPWM CON_SET: INVBDC_SET Position  */
+#define MCPWM_CON_SET_INVBDC_SET_Msk                          (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos)                  /*!< MCPWM CON_SET: INVBDC_SET Mask      */
+#define MCPWM_CON_SET_ACMODE_SET_Pos                          30                                                        /*!< MCPWM CON_SET: ACMODE_SET Position  */
+#define MCPWM_CON_SET_ACMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos)                  /*!< MCPWM CON_SET: ACMODE_SET Mask      */
+#define MCPWM_CON_SET_DCMODE_SET_Pos                          31                                                        /*!< MCPWM CON_SET: DCMODE_SET Position  */
+#define MCPWM_CON_SET_DCMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos)                  /*!< MCPWM CON_SET: DCMODE_SET Mask      */
+
+// --------------------------------------  MCPWM_CON_CLR  -----------------------------------------
+#define MCPWM_CON_CLR_RUN0_CLR_Pos                            0                                                         /*!< MCPWM CON_CLR: RUN0_CLR Position    */
+#define MCPWM_CON_CLR_RUN0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN0_CLR Mask        */
+#define MCPWM_CON_CLR_CENTER0_CLR_Pos                         1                                                         /*!< MCPWM CON_CLR: CENTER0_CLR Position */
+#define MCPWM_CON_CLR_CENTER0_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER0_CLR Mask     */
+#define MCPWM_CON_CLR_POLA0_CLR_Pos                           2                                                         /*!< MCPWM CON_CLR: POLA0_CLR Position   */
+#define MCPWM_CON_CLR_POLA0_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA0_CLR Mask       */
+#define MCPWM_CON_CLR_DTE0_CLR_Pos                            3                                                         /*!< MCPWM CON_CLR: DTE0_CLR Position    */
+#define MCPWM_CON_CLR_DTE0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE0_CLR Mask        */
+#define MCPWM_CON_CLR_DISUP0_CLR_Pos                          4                                                         /*!< MCPWM CON_CLR: DISUP0_CLR Position  */
+#define MCPWM_CON_CLR_DISUP0_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP0_CLR Mask      */
+#define MCPWM_CON_CLR_RUN1_CLR_Pos                            8                                                         /*!< MCPWM CON_CLR: RUN1_CLR Position    */
+#define MCPWM_CON_CLR_RUN1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN1_CLR Mask        */
+#define MCPWM_CON_CLR_CENTER1_CLR_Pos                         9                                                         /*!< MCPWM CON_CLR: CENTER1_CLR Position */
+#define MCPWM_CON_CLR_CENTER1_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER1_CLR Mask     */
+#define MCPWM_CON_CLR_POLA1_CLR_Pos                           10                                                        /*!< MCPWM CON_CLR: POLA1_CLR Position   */
+#define MCPWM_CON_CLR_POLA1_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA1_CLR Mask       */
+#define MCPWM_CON_CLR_DTE1_CLR_Pos                            11                                                        /*!< MCPWM CON_CLR: DTE1_CLR Position    */
+#define MCPWM_CON_CLR_DTE1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE1_CLR Mask        */
+#define MCPWM_CON_CLR_DISUP1_CLR_Pos                          12                                                        /*!< MCPWM CON_CLR: DISUP1_CLR Position  */
+#define MCPWM_CON_CLR_DISUP1_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP1_CLR Mask      */
+#define MCPWM_CON_CLR_RUN2_CLR_Pos                            16                                                        /*!< MCPWM CON_CLR: RUN2_CLR Position    */
+#define MCPWM_CON_CLR_RUN2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN2_CLR Mask        */
+#define MCPWM_CON_CLR_CENTER2_CLR_Pos                         17                                                        /*!< MCPWM CON_CLR: CENTER2_CLR Position */
+#define MCPWM_CON_CLR_CENTER2_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER2_CLR Mask     */
+#define MCPWM_CON_CLR_POLA2_CLR_Pos                           18                                                        /*!< MCPWM CON_CLR: POLA2_CLR Position   */
+#define MCPWM_CON_CLR_POLA2_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA2_CLR Mask       */
+#define MCPWM_CON_CLR_DTE2_CLR_Pos                            19                                                        /*!< MCPWM CON_CLR: DTE2_CLR Position    */
+#define MCPWM_CON_CLR_DTE2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE2_CLR Mask        */
+#define MCPWM_CON_CLR_DISUP2_CLR_Pos                          20                                                        /*!< MCPWM CON_CLR: DISUP2_CLR Position  */
+#define MCPWM_CON_CLR_DISUP2_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP2_CLR Mask      */
+#define MCPWM_CON_CLR_INVBDC_CLR_Pos                          29                                                        /*!< MCPWM CON_CLR: INVBDC_CLR Position  */
+#define MCPWM_CON_CLR_INVBDC_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos)                  /*!< MCPWM CON_CLR: INVBDC_CLR Mask      */
+#define MCPWM_CON_CLR_ACMOD_CLR_Pos                           30                                                        /*!< MCPWM CON_CLR: ACMOD_CLR Position   */
+#define MCPWM_CON_CLR_ACMOD_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos)                   /*!< MCPWM CON_CLR: ACMOD_CLR Mask       */
+#define MCPWM_CON_CLR_DCMODE_CLR_Pos                          31                                                        /*!< MCPWM CON_CLR: DCMODE_CLR Position  */
+#define MCPWM_CON_CLR_DCMODE_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos)                  /*!< MCPWM CON_CLR: DCMODE_CLR Mask      */
+
+// --------------------------------------  MCPWM_CAPCON  ------------------------------------------
+#define MCPWM_CAPCON_CAP0MCI0_RE_Pos                          0                                                         /*!< MCPWM CAPCON: CAP0MCI0_RE Position  */
+#define MCPWM_CAPCON_CAP0MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_RE Mask      */
+#define MCPWM_CAPCON_CAP0MCI0_FE_Pos                          1                                                         /*!< MCPWM CAPCON: CAP0MCI0_FE Position  */
+#define MCPWM_CAPCON_CAP0MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_FE Mask      */
+#define MCPWM_CAPCON_CAP0MCI1_RE_Pos                          2                                                         /*!< MCPWM CAPCON: CAP0MCI1_RE Position  */
+#define MCPWM_CAPCON_CAP0MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_RE Mask      */
+#define MCPWM_CAPCON_CAP0MCI1_FE_Pos                          3                                                         /*!< MCPWM CAPCON: CAP0MCI1_FE Position  */
+#define MCPWM_CAPCON_CAP0MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_FE Mask      */
+#define MCPWM_CAPCON_CAP0MCI2_RE_Pos                          4                                                         /*!< MCPWM CAPCON: CAP0MCI2_RE Position  */
+#define MCPWM_CAPCON_CAP0MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_RE Mask      */
+#define MCPWM_CAPCON_CAP0MCI2_FE_Pos                          5                                                         /*!< MCPWM CAPCON: CAP0MCI2_FE Position  */
+#define MCPWM_CAPCON_CAP0MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_FE Mask      */
+#define MCPWM_CAPCON_CAP1MCI0_RE_Pos                          6                                                         /*!< MCPWM CAPCON: CAP1MCI0_RE Position  */
+#define MCPWM_CAPCON_CAP1MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_RE Mask      */
+#define MCPWM_CAPCON_CAP1MCI0_FE_Pos                          7                                                         /*!< MCPWM CAPCON: CAP1MCI0_FE Position  */
+#define MCPWM_CAPCON_CAP1MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_FE Mask      */
+#define MCPWM_CAPCON_CAP1MCI1_RE_Pos                          8                                                         /*!< MCPWM CAPCON: CAP1MCI1_RE Position  */
+#define MCPWM_CAPCON_CAP1MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_RE Mask      */
+#define MCPWM_CAPCON_CAP1MCI1_FE_Pos                          9                                                         /*!< MCPWM CAPCON: CAP1MCI1_FE Position  */
+#define MCPWM_CAPCON_CAP1MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_FE Mask      */
+#define MCPWM_CAPCON_CAP1MCI2_RE_Pos                          10                                                        /*!< MCPWM CAPCON: CAP1MCI2_RE Position  */
+#define MCPWM_CAPCON_CAP1MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_RE Mask      */
+#define MCPWM_CAPCON_CAP1MCI2_FE_Pos                          11                                                        /*!< MCPWM CAPCON: CAP1MCI2_FE Position  */
+#define MCPWM_CAPCON_CAP1MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_FE Mask      */
+#define MCPWM_CAPCON_CAP2MCI0_RE_Pos                          12                                                        /*!< MCPWM CAPCON: CAP2MCI0_RE Position  */
+#define MCPWM_CAPCON_CAP2MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_RE Mask      */
+#define MCPWM_CAPCON_CAP2MCI0_FE_Pos                          13                                                        /*!< MCPWM CAPCON: CAP2MCI0_FE Position  */
+#define MCPWM_CAPCON_CAP2MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_FE Mask      */
+#define MCPWM_CAPCON_CAP2MCI1_RE_Pos                          14                                                        /*!< MCPWM CAPCON: CAP2MCI1_RE Position  */
+#define MCPWM_CAPCON_CAP2MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_RE Mask      */
+#define MCPWM_CAPCON_CAP2MCI1_FE_Pos                          15                                                        /*!< MCPWM CAPCON: CAP2MCI1_FE Position  */
+#define MCPWM_CAPCON_CAP2MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_FE Mask      */
+#define MCPWM_CAPCON_CAP2MCI2_RE_Pos                          16                                                        /*!< MCPWM CAPCON: CAP2MCI2_RE Position  */
+#define MCPWM_CAPCON_CAP2MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_RE Mask      */
+#define MCPWM_CAPCON_CAP2MCI2_FE_Pos                          17                                                        /*!< MCPWM CAPCON: CAP2MCI2_FE Position  */
+#define MCPWM_CAPCON_CAP2MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_FE Mask      */
+#define MCPWM_CAPCON_RT0_Pos                                  18                                                        /*!< MCPWM CAPCON: RT0 Position          */
+#define MCPWM_CAPCON_RT0_Msk                                  (0x01UL << MCPWM_CAPCON_RT0_Pos)                          /*!< MCPWM CAPCON: RT0 Mask              */
+#define MCPWM_CAPCON_RT1_Pos                                  19                                                        /*!< MCPWM CAPCON: RT1 Position          */
+#define MCPWM_CAPCON_RT1_Msk                                  (0x01UL << MCPWM_CAPCON_RT1_Pos)                          /*!< MCPWM CAPCON: RT1 Mask              */
+#define MCPWM_CAPCON_RT2_Pos                                  20                                                        /*!< MCPWM CAPCON: RT2 Position          */
+#define MCPWM_CAPCON_RT2_Msk                                  (0x01UL << MCPWM_CAPCON_RT2_Pos)                          /*!< MCPWM CAPCON: RT2 Mask              */
+#define MCPWM_CAPCON_HNFCAP0_Pos                              21                                                        /*!< MCPWM CAPCON: HNFCAP0 Position      */
+#define MCPWM_CAPCON_HNFCAP0_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos)                      /*!< MCPWM CAPCON: HNFCAP0 Mask          */
+#define MCPWM_CAPCON_HNFCAP1_Pos                              22                                                        /*!< MCPWM CAPCON: HNFCAP1 Position      */
+#define MCPWM_CAPCON_HNFCAP1_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos)                      /*!< MCPWM CAPCON: HNFCAP1 Mask          */
+#define MCPWM_CAPCON_HNFCAP2_Pos                              23                                                        /*!< MCPWM CAPCON: HNFCAP2 Position      */
+#define MCPWM_CAPCON_HNFCAP2_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos)                      /*!< MCPWM CAPCON: HNFCAP2 Mask          */
+
+// ------------------------------------  MCPWM_CAPCON_SET  ----------------------------------------
+#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos                  0                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos                  1                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos                  2                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos                  3                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos                  4                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos                  5                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos                  6                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos                  7                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos                  8                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos                  9                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos                  10                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos                  11                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos                  12                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos                  13                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos                  14                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos                  15                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos                  16                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos                  17                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_RT0_SET_Pos                          18                                                        /*!< MCPWM CAPCON_SET: RT0_SET Position  */
+#define MCPWM_CAPCON_SET_RT0_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT0_SET Mask      */
+#define MCPWM_CAPCON_SET_RT1_SET_Pos                          19                                                        /*!< MCPWM CAPCON_SET: RT1_SET Position  */
+#define MCPWM_CAPCON_SET_RT1_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT1_SET Mask      */
+#define MCPWM_CAPCON_SET_RT2_SET_Pos                          20                                                        /*!< MCPWM CAPCON_SET: RT2_SET Position  */
+#define MCPWM_CAPCON_SET_RT2_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT2_SET Mask      */
+#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos                      21                                                        /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask  */
+#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos                      22                                                        /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask  */
+#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos                      23                                                        /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask  */
+
+// ------------------------------------  MCPWM_CAPCON_CLR  ----------------------------------------
+#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos                  0                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos                  1                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos                  2                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos                  3                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos                  4                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos                  5                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos                  6                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos                  7                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos                  8                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos                  9                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos                  10                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos                  11                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos                  12                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos                  13                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos                  14                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos                  15                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos                  16                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos                  17                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_RT0_CLR_Pos                          18                                                        /*!< MCPWM CAPCON_CLR: RT0_CLR Position  */
+#define MCPWM_CAPCON_CLR_RT0_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT0_CLR Mask      */
+#define MCPWM_CAPCON_CLR_RT1_CLR_Pos                          19                                                        /*!< MCPWM CAPCON_CLR: RT1_CLR Position  */
+#define MCPWM_CAPCON_CLR_RT1_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT1_CLR Mask      */
+#define MCPWM_CAPCON_CLR_RT2_CLR_Pos                          20                                                        /*!< MCPWM CAPCON_CLR: RT2_CLR Position  */
+#define MCPWM_CAPCON_CLR_RT2_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT2_CLR Mask      */
+#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos                      21                                                        /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask  */
+#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos                      22                                                        /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask  */
+#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos                      23                                                        /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask  */
+
+// ----------------------------------------  MCPWM_TC0  -------------------------------------------
+#define MCPWM_TC0_MCTC_Pos                                    0                                                         /*!< MCPWM TC0: MCTC Position            */
+#define MCPWM_TC0_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC0_MCTC_Pos)                      /*!< MCPWM TC0: MCTC Mask                */
+
+// ----------------------------------------  MCPWM_TC1  -------------------------------------------
+#define MCPWM_TC1_MCTC_Pos                                    0                                                         /*!< MCPWM TC1: MCTC Position            */
+#define MCPWM_TC1_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC1_MCTC_Pos)                      /*!< MCPWM TC1: MCTC Mask                */
+
+// ----------------------------------------  MCPWM_TC2  -------------------------------------------
+#define MCPWM_TC2_MCTC_Pos                                    0                                                         /*!< MCPWM TC2: MCTC Position            */
+#define MCPWM_TC2_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC2_MCTC_Pos)                      /*!< MCPWM TC2: MCTC Mask                */
+
+// ---------------------------------------  MCPWM_LIM0  -------------------------------------------
+#define MCPWM_LIM0_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM0: MCLIM Position          */
+#define MCPWM_LIM0_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos)                    /*!< MCPWM LIM0: MCLIM Mask              */
+
+// ---------------------------------------  MCPWM_LIM1  -------------------------------------------
+#define MCPWM_LIM1_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM1: MCLIM Position          */
+#define MCPWM_LIM1_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos)                    /*!< MCPWM LIM1: MCLIM Mask              */
+
+// ---------------------------------------  MCPWM_LIM2  -------------------------------------------
+#define MCPWM_LIM2_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM2: MCLIM Position          */
+#define MCPWM_LIM2_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos)                    /*!< MCPWM LIM2: MCLIM Mask              */
+
+// ---------------------------------------  MCPWM_MAT0  -------------------------------------------
+#define MCPWM_MAT0_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT0: MCMAT Position          */
+#define MCPWM_MAT0_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos)                    /*!< MCPWM MAT0: MCMAT Mask              */
+
+// ---------------------------------------  MCPWM_MAT1  -------------------------------------------
+#define MCPWM_MAT1_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT1: MCMAT Position          */
+#define MCPWM_MAT1_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos)                    /*!< MCPWM MAT1: MCMAT Mask              */
+
+// ---------------------------------------  MCPWM_MAT2  -------------------------------------------
+#define MCPWM_MAT2_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT2: MCMAT Position          */
+#define MCPWM_MAT2_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos)                    /*!< MCPWM MAT2: MCMAT Mask              */
+
+// ----------------------------------------  MCPWM_DT  --------------------------------------------
+#define MCPWM_DT_DT0_Pos                                      0                                                         /*!< MCPWM DT: DT0 Position              */
+#define MCPWM_DT_DT0_Msk                                      (0x000003ffUL << MCPWM_DT_DT0_Pos)                        /*!< MCPWM DT: DT0 Mask                  */
+#define MCPWM_DT_DT1_Pos                                      10                                                        /*!< MCPWM DT: DT1 Position              */
+#define MCPWM_DT_DT1_Msk                                      (0x000003ffUL << MCPWM_DT_DT1_Pos)                        /*!< MCPWM DT: DT1 Mask                  */
+#define MCPWM_DT_DT2_Pos                                      20                                                        /*!< MCPWM DT: DT2 Position              */
+#define MCPWM_DT_DT2_Msk                                      (0x000003ffUL << MCPWM_DT_DT2_Pos)                        /*!< MCPWM DT: DT2 Mask                  */
+
+// ----------------------------------------  MCPWM_CCP  -------------------------------------------
+#define MCPWM_CCP_CCPA0_Pos                                   0                                                         /*!< MCPWM CCP: CCPA0 Position           */
+#define MCPWM_CCP_CCPA0_Msk                                   (0x01UL << MCPWM_CCP_CCPA0_Pos)                           /*!< MCPWM CCP: CCPA0 Mask               */
+#define MCPWM_CCP_CCPB0_Pos                                   1                                                         /*!< MCPWM CCP: CCPB0 Position           */
+#define MCPWM_CCP_CCPB0_Msk                                   (0x01UL << MCPWM_CCP_CCPB0_Pos)                           /*!< MCPWM CCP: CCPB0 Mask               */
+#define MCPWM_CCP_CCPA1_Pos                                   2                                                         /*!< MCPWM CCP: CCPA1 Position           */
+#define MCPWM_CCP_CCPA1_Msk                                   (0x01UL << MCPWM_CCP_CCPA1_Pos)                           /*!< MCPWM CCP: CCPA1 Mask               */
+#define MCPWM_CCP_CCPB1_Pos                                   3                                                         /*!< MCPWM CCP: CCPB1 Position           */
+#define MCPWM_CCP_CCPB1_Msk                                   (0x01UL << MCPWM_CCP_CCPB1_Pos)                           /*!< MCPWM CCP: CCPB1 Mask               */
+#define MCPWM_CCP_CCPA2_Pos                                   4                                                         /*!< MCPWM CCP: CCPA2 Position           */
+#define MCPWM_CCP_CCPA2_Msk                                   (0x01UL << MCPWM_CCP_CCPA2_Pos)                           /*!< MCPWM CCP: CCPA2 Mask               */
+#define MCPWM_CCP_CCPB2_Pos                                   5                                                         /*!< MCPWM CCP: CCPB2 Position           */
+#define MCPWM_CCP_CCPB2_Msk                                   (0x01UL << MCPWM_CCP_CCPB2_Pos)                           /*!< MCPWM CCP: CCPB2 Mask               */
+
+// ---------------------------------------  MCPWM_CAP0  -------------------------------------------
+#define MCPWM_CAP0_CAP_Pos                                    0                                                         /*!< MCPWM CAP0: CAP Position            */
+#define MCPWM_CAP0_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP0_CAP_Pos)                      /*!< MCPWM CAP0: CAP Mask                */
+
+// ---------------------------------------  MCPWM_CAP1  -------------------------------------------
+#define MCPWM_CAP1_CAP_Pos                                    0                                                         /*!< MCPWM CAP1: CAP Position            */
+#define MCPWM_CAP1_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP1_CAP_Pos)                      /*!< MCPWM CAP1: CAP Mask                */
+
+// ---------------------------------------  MCPWM_CAP2  -------------------------------------------
+#define MCPWM_CAP2_CAP_Pos                                    0                                                         /*!< MCPWM CAP2: CAP Position            */
+#define MCPWM_CAP2_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP2_CAP_Pos)                      /*!< MCPWM CAP2: CAP Mask                */
+
+// ---------------------------------------  MCPWM_INTEN  ------------------------------------------
+#define MCPWM_INTEN_ILIM0_Pos                                 0                                                         /*!< MCPWM INTEN: ILIM0 Position         */
+#define MCPWM_INTEN_ILIM0_Msk                                 (0x01UL << MCPWM_INTEN_ILIM0_Pos)                         /*!< MCPWM INTEN: ILIM0 Mask             */
+#define MCPWM_INTEN_IMAT0_Pos                                 1                                                         /*!< MCPWM INTEN: IMAT0 Position         */
+#define MCPWM_INTEN_IMAT0_Msk                                 (0x01UL << MCPWM_INTEN_IMAT0_Pos)                         /*!< MCPWM INTEN: IMAT0 Mask             */
+#define MCPWM_INTEN_ICAP0_Pos                                 2                                                         /*!< MCPWM INTEN: ICAP0 Position         */
+#define MCPWM_INTEN_ICAP0_Msk                                 (0x01UL << MCPWM_INTEN_ICAP0_Pos)                         /*!< MCPWM INTEN: ICAP0 Mask             */
+#define MCPWM_INTEN_ILIM1_Pos                                 4                                                         /*!< MCPWM INTEN: ILIM1 Position         */
+#define MCPWM_INTEN_ILIM1_Msk                                 (0x01UL << MCPWM_INTEN_ILIM1_Pos)                         /*!< MCPWM INTEN: ILIM1 Mask             */
+#define MCPWM_INTEN_IMAT1_Pos                                 5                                                         /*!< MCPWM INTEN: IMAT1 Position         */
+#define MCPWM_INTEN_IMAT1_Msk                                 (0x01UL << MCPWM_INTEN_IMAT1_Pos)                         /*!< MCPWM INTEN: IMAT1 Mask             */
+#define MCPWM_INTEN_ICAP1_Pos                                 6                                                         /*!< MCPWM INTEN: ICAP1 Position         */
+#define MCPWM_INTEN_ICAP1_Msk                                 (0x01UL << MCPWM_INTEN_ICAP1_Pos)                         /*!< MCPWM INTEN: ICAP1 Mask             */
+#define MCPWM_INTEN_ILIM2_Pos                                 8                                                         /*!< MCPWM INTEN: ILIM2 Position         */
+#define MCPWM_INTEN_ILIM2_Msk                                 (0x01UL << MCPWM_INTEN_ILIM2_Pos)                         /*!< MCPWM INTEN: ILIM2 Mask             */
+#define MCPWM_INTEN_IMAT2_Pos                                 9                                                         /*!< MCPWM INTEN: IMAT2 Position         */
+#define MCPWM_INTEN_IMAT2_Msk                                 (0x01UL << MCPWM_INTEN_IMAT2_Pos)                         /*!< MCPWM INTEN: IMAT2 Mask             */
+#define MCPWM_INTEN_ICAP2_Pos                                 10                                                        /*!< MCPWM INTEN: ICAP2 Position         */
+#define MCPWM_INTEN_ICAP2_Msk                                 (0x01UL << MCPWM_INTEN_ICAP2_Pos)                         /*!< MCPWM INTEN: ICAP2 Mask             */
+#define MCPWM_INTEN_ABORT_Pos                                 15                                                        /*!< MCPWM INTEN: ABORT Position         */
+#define MCPWM_INTEN_ABORT_Msk                                 (0x01UL << MCPWM_INTEN_ABORT_Pos)                         /*!< MCPWM INTEN: ABORT Mask             */
+
+// -------------------------------------  MCPWM_INTEN_SET  ----------------------------------------
+#define MCPWM_INTEN_SET_ILIM0_SET_Pos                         0                                                         /*!< MCPWM INTEN_SET: ILIM0_SET Position */
+#define MCPWM_INTEN_SET_ILIM0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM0_SET Mask     */
+#define MCPWM_INTEN_SET_IMAT0_SET_Pos                         1                                                         /*!< MCPWM INTEN_SET: IMAT0_SET Position */
+#define MCPWM_INTEN_SET_IMAT0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT0_SET Mask     */
+#define MCPWM_INTEN_SET_ICAP0_SET_Pos                         2                                                         /*!< MCPWM INTEN_SET: ICAP0_SET Position */
+#define MCPWM_INTEN_SET_ICAP0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP0_SET Mask     */
+#define MCPWM_INTEN_SET_ILIM1_SET_Pos                         4                                                         /*!< MCPWM INTEN_SET: ILIM1_SET Position */
+#define MCPWM_INTEN_SET_ILIM1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM1_SET Mask     */
+#define MCPWM_INTEN_SET_IMAT1_SET_Pos                         5                                                         /*!< MCPWM INTEN_SET: IMAT1_SET Position */
+#define MCPWM_INTEN_SET_IMAT1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT1_SET Mask     */
+#define MCPWM_INTEN_SET_ICAP1_SET_Pos                         6                                                         /*!< MCPWM INTEN_SET: ICAP1_SET Position */
+#define MCPWM_INTEN_SET_ICAP1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP1_SET Mask     */
+#define MCPWM_INTEN_SET_ILIM2_SET_Pos                         9                                                         /*!< MCPWM INTEN_SET: ILIM2_SET Position */
+#define MCPWM_INTEN_SET_ILIM2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM2_SET Mask     */
+#define MCPWM_INTEN_SET_IMAT2_SET_Pos                         10                                                        /*!< MCPWM INTEN_SET: IMAT2_SET Position */
+#define MCPWM_INTEN_SET_IMAT2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT2_SET Mask     */
+#define MCPWM_INTEN_SET_ICAP2_SET_Pos                         11                                                        /*!< MCPWM INTEN_SET: ICAP2_SET Position */
+#define MCPWM_INTEN_SET_ICAP2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP2_SET Mask     */
+#define MCPWM_INTEN_SET_ABORT_SET_Pos                         15                                                        /*!< MCPWM INTEN_SET: ABORT_SET Position */
+#define MCPWM_INTEN_SET_ABORT_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos)                 /*!< MCPWM INTEN_SET: ABORT_SET Mask     */
+
+// -------------------------------------  MCPWM_INTEN_CLR  ----------------------------------------
+#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos                         0                                                         /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask     */
+#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos                         1                                                         /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask     */
+#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos                         2                                                         /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask     */
+#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos                         4                                                         /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask     */
+#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos                         5                                                         /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask     */
+#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos                         6                                                         /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask     */
+#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos                         8                                                         /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask     */
+#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos                         9                                                         /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask     */
+#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos                         10                                                        /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask     */
+#define MCPWM_INTEN_CLR_ABORT_CLR_Pos                         15                                                        /*!< MCPWM INTEN_CLR: ABORT_CLR Position */
+#define MCPWM_INTEN_CLR_ABORT_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ABORT_CLR Mask     */
+
+// --------------------------------------  MCPWM_CNTCON  ------------------------------------------
+#define MCPWM_CNTCON_TC0MCI0_RE_Pos                           0                                                         /*!< MCPWM CNTCON: TC0MCI0_RE Position   */
+#define MCPWM_CNTCON_TC0MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_RE Mask       */
+#define MCPWM_CNTCON_TC0MCI0_FE_Pos                           1                                                         /*!< MCPWM CNTCON: TC0MCI0_FE Position   */
+#define MCPWM_CNTCON_TC0MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_FE Mask       */
+#define MCPWM_CNTCON_TC0MCI1_RE_Pos                           2                                                         /*!< MCPWM CNTCON: TC0MCI1_RE Position   */
+#define MCPWM_CNTCON_TC0MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_RE Mask       */
+#define MCPWM_CNTCON_TC0MCI1_FE_Pos                           3                                                         /*!< MCPWM CNTCON: TC0MCI1_FE Position   */
+#define MCPWM_CNTCON_TC0MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_FE Mask       */
+#define MCPWM_CNTCON_TC0MCI2_RE_Pos                           4                                                         /*!< MCPWM CNTCON: TC0MCI2_RE Position   */
+#define MCPWM_CNTCON_TC0MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_RE Mask       */
+#define MCPWM_CNTCON_TC0MCI2_FE_Pos                           5                                                         /*!< MCPWM CNTCON: TC0MCI2_FE Position   */
+#define MCPWM_CNTCON_TC0MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_FE Mask       */
+#define MCPWM_CNTCON_TC1MCI0_RE_Pos                           6                                                         /*!< MCPWM CNTCON: TC1MCI0_RE Position   */
+#define MCPWM_CNTCON_TC1MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_RE Mask       */
+#define MCPWM_CNTCON_TC1MCI0_FE_Pos                           7                                                         /*!< MCPWM CNTCON: TC1MCI0_FE Position   */
+#define MCPWM_CNTCON_TC1MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_FE Mask       */
+#define MCPWM_CNTCON_TC1MCI1_RE_Pos                           8                                                         /*!< MCPWM CNTCON: TC1MCI1_RE Position   */
+#define MCPWM_CNTCON_TC1MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_RE Mask       */
+#define MCPWM_CNTCON_TC1MCI1_FE_Pos                           9                                                         /*!< MCPWM CNTCON: TC1MCI1_FE Position   */
+#define MCPWM_CNTCON_TC1MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_FE Mask       */
+#define MCPWM_CNTCON_TC1MCI2_RE_Pos                           10                                                        /*!< MCPWM CNTCON: TC1MCI2_RE Position   */
+#define MCPWM_CNTCON_TC1MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_RE Mask       */
+#define MCPWM_CNTCON_TC1MCI2_FE_Pos                           11                                                        /*!< MCPWM CNTCON: TC1MCI2_FE Position   */
+#define MCPWM_CNTCON_TC1MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_FE Mask       */
+#define MCPWM_CNTCON_TC2MCI0_RE_Pos                           12                                                        /*!< MCPWM CNTCON: TC2MCI0_RE Position   */
+#define MCPWM_CNTCON_TC2MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_RE Mask       */
+#define MCPWM_CNTCON_TC2MCI0_FE_Pos                           13                                                        /*!< MCPWM CNTCON: TC2MCI0_FE Position   */
+#define MCPWM_CNTCON_TC2MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_FE Mask       */
+#define MCPWM_CNTCON_TC2MCI1_RE_Pos                           14                                                        /*!< MCPWM CNTCON: TC2MCI1_RE Position   */
+#define MCPWM_CNTCON_TC2MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_RE Mask       */
+#define MCPWM_CNTCON_TC2MCI1_FE_Pos                           15                                                        /*!< MCPWM CNTCON: TC2MCI1_FE Position   */
+#define MCPWM_CNTCON_TC2MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_FE Mask       */
+#define MCPWM_CNTCON_TC2MCI2_RE_Pos                           16                                                        /*!< MCPWM CNTCON: TC2MCI2_RE Position   */
+#define MCPWM_CNTCON_TC2MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_RE Mask       */
+#define MCPWM_CNTCON_TC2MCI2_FE_Pos                           17                                                        /*!< MCPWM CNTCON: TC2MCI2_FE Position   */
+#define MCPWM_CNTCON_TC2MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_FE Mask       */
+#define MCPWM_CNTCON_CNTR0_Pos                                29                                                        /*!< MCPWM CNTCON: CNTR0 Position        */
+#define MCPWM_CNTCON_CNTR0_Msk                                (0x01UL << MCPWM_CNTCON_CNTR0_Pos)                        /*!< MCPWM CNTCON: CNTR0 Mask            */
+#define MCPWM_CNTCON_CNTR1_Pos                                30                                                        /*!< MCPWM CNTCON: CNTR1 Position        */
+#define MCPWM_CNTCON_CNTR1_Msk                                (0x01UL << MCPWM_CNTCON_CNTR1_Pos)                        /*!< MCPWM CNTCON: CNTR1 Mask            */
+#define MCPWM_CNTCON_CNTR2_Pos                                31                                                        /*!< MCPWM CNTCON: CNTR2 Position        */
+#define MCPWM_CNTCON_CNTR2_Msk                                (0x01UL << MCPWM_CNTCON_CNTR2_Pos)                        /*!< MCPWM CNTCON: CNTR2 Mask            */
+
+// ------------------------------------  MCPWM_CNTCON_SET  ----------------------------------------
+#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos                   0                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos                   1                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos                   2                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos                   3                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos                   4                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos                   5                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos                   6                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos                   7                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos                   8                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos                   9                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos                   10                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos                   11                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos                   12                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos                   13                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos                   14                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos                   15                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos                   16                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos                   17                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_CNTR0_SET_Pos                        29                                                        /*!< MCPWM CNTCON_SET: CNTR0_SET Position */
+#define MCPWM_CNTCON_SET_CNTR0_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR0_SET Mask    */
+#define MCPWM_CNTCON_SET_CNTR1_SET_Pos                        30                                                        /*!< MCPWM CNTCON_SET: CNTR1_SET Position */
+#define MCPWM_CNTCON_SET_CNTR1_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR1_SET Mask    */
+#define MCPWM_CNTCON_SET_CNTR2_SET_Pos                        31                                                        /*!< MCPWM CNTCON_SET: CNTR2_SET Position */
+#define MCPWM_CNTCON_SET_CNTR2_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR2_SET Mask    */
+
+// ------------------------------------  MCPWM_CNTCON_CLR  ----------------------------------------
+#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos                   0                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos                   1                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos                   2                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos                   3                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos                       4                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */
+#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk                       (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos)               /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask   */
+#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos                   5                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos                   6                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos                   7                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos                   8                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos                   9                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos                   10                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos                   11                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos                   12                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos                   13                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos                   14                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos                   15                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos                   16                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos                   17                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos                        29                                                        /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask    */
+#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos                        30                                                        /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask    */
+#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos                        31                                                        /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask    */
+
+// ---------------------------------------  MCPWM_INTF  -------------------------------------------
+#define MCPWM_INTF_ILIM0_F_Pos                                0                                                         /*!< MCPWM INTF: ILIM0_F Position        */
+#define MCPWM_INTF_ILIM0_F_Msk                                (0x01UL << MCPWM_INTF_ILIM0_F_Pos)                        /*!< MCPWM INTF: ILIM0_F Mask            */
+#define MCPWM_INTF_IMAT0_F_Pos                                1                                                         /*!< MCPWM INTF: IMAT0_F Position        */
+#define MCPWM_INTF_IMAT0_F_Msk                                (0x01UL << MCPWM_INTF_IMAT0_F_Pos)                        /*!< MCPWM INTF: IMAT0_F Mask            */
+#define MCPWM_INTF_ICAP0_F_Pos                                2                                                         /*!< MCPWM INTF: ICAP0_F Position        */
+#define MCPWM_INTF_ICAP0_F_Msk                                (0x01UL << MCPWM_INTF_ICAP0_F_Pos)                        /*!< MCPWM INTF: ICAP0_F Mask            */
+#define MCPWM_INTF_ILIM1_F_Pos                                4                                                         /*!< MCPWM INTF: ILIM1_F Position        */
+#define MCPWM_INTF_ILIM1_F_Msk                                (0x01UL << MCPWM_INTF_ILIM1_F_Pos)                        /*!< MCPWM INTF: ILIM1_F Mask            */
+#define MCPWM_INTF_IMAT1_F_Pos                                5                                                         /*!< MCPWM INTF: IMAT1_F Position        */
+#define MCPWM_INTF_IMAT1_F_Msk                                (0x01UL << MCPWM_INTF_IMAT1_F_Pos)                        /*!< MCPWM INTF: IMAT1_F Mask            */
+#define MCPWM_INTF_ICAP1_F_Pos                                6                                                         /*!< MCPWM INTF: ICAP1_F Position        */
+#define MCPWM_INTF_ICAP1_F_Msk                                (0x01UL << MCPWM_INTF_ICAP1_F_Pos)                        /*!< MCPWM INTF: ICAP1_F Mask            */
+#define MCPWM_INTF_ILIM2_F_Pos                                8                                                         /*!< MCPWM INTF: ILIM2_F Position        */
+#define MCPWM_INTF_ILIM2_F_Msk                                (0x01UL << MCPWM_INTF_ILIM2_F_Pos)                        /*!< MCPWM INTF: ILIM2_F Mask            */
+#define MCPWM_INTF_IMAT2_F_Pos                                9                                                         /*!< MCPWM INTF: IMAT2_F Position        */
+#define MCPWM_INTF_IMAT2_F_Msk                                (0x01UL << MCPWM_INTF_IMAT2_F_Pos)                        /*!< MCPWM INTF: IMAT2_F Mask            */
+#define MCPWM_INTF_ICAP2_F_Pos                                10                                                        /*!< MCPWM INTF: ICAP2_F Position        */
+#define MCPWM_INTF_ICAP2_F_Msk                                (0x01UL << MCPWM_INTF_ICAP2_F_Pos)                        /*!< MCPWM INTF: ICAP2_F Mask            */
+#define MCPWM_INTF_ABORT_F_Pos                                15                                                        /*!< MCPWM INTF: ABORT_F Position        */
+#define MCPWM_INTF_ABORT_F_Msk                                (0x01UL << MCPWM_INTF_ABORT_F_Pos)                        /*!< MCPWM INTF: ABORT_F Mask            */
+
+// -------------------------------------  MCPWM_INTF_SET  -----------------------------------------
+#define MCPWM_INTF_SET_ILIM0_F_SET_Pos                        0                                                         /*!< MCPWM INTF_SET: ILIM0_F_SET Position */
+#define MCPWM_INTF_SET_ILIM0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM0_F_SET Mask    */
+#define MCPWM_INTF_SET_IMAT0_F_SET_Pos                        1                                                         /*!< MCPWM INTF_SET: IMAT0_F_SET Position */
+#define MCPWM_INTF_SET_IMAT0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT0_F_SET Mask    */
+#define MCPWM_INTF_SET_ICAP0_F_SET_Pos                        2                                                         /*!< MCPWM INTF_SET: ICAP0_F_SET Position */
+#define MCPWM_INTF_SET_ICAP0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP0_F_SET Mask    */
+#define MCPWM_INTF_SET_ILIM1_F_SET_Pos                        4                                                         /*!< MCPWM INTF_SET: ILIM1_F_SET Position */
+#define MCPWM_INTF_SET_ILIM1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM1_F_SET Mask    */
+#define MCPWM_INTF_SET_IMAT1_F_SET_Pos                        5                                                         /*!< MCPWM INTF_SET: IMAT1_F_SET Position */
+#define MCPWM_INTF_SET_IMAT1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT1_F_SET Mask    */
+#define MCPWM_INTF_SET_ICAP1_F_SET_Pos                        6                                                         /*!< MCPWM INTF_SET: ICAP1_F_SET Position */
+#define MCPWM_INTF_SET_ICAP1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP1_F_SET Mask    */
+#define MCPWM_INTF_SET_ILIM2_F_SET_Pos                        8                                                         /*!< MCPWM INTF_SET: ILIM2_F_SET Position */
+#define MCPWM_INTF_SET_ILIM2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM2_F_SET Mask    */
+#define MCPWM_INTF_SET_IMAT2_F_SET_Pos                        9                                                         /*!< MCPWM INTF_SET: IMAT2_F_SET Position */
+#define MCPWM_INTF_SET_IMAT2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT2_F_SET Mask    */
+#define MCPWM_INTF_SET_ICAP2_F_SET_Pos                        10                                                        /*!< MCPWM INTF_SET: ICAP2_F_SET Position */
+#define MCPWM_INTF_SET_ICAP2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP2_F_SET Mask    */
+#define MCPWM_INTF_SET_ABORT_F_SET_Pos                        15                                                        /*!< MCPWM INTF_SET: ABORT_F_SET Position */
+#define MCPWM_INTF_SET_ABORT_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos)                /*!< MCPWM INTF_SET: ABORT_F_SET Mask    */
+
+// -------------------------------------  MCPWM_INTF_CLR  -----------------------------------------
+#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos                        0                                                         /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask    */
+#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos                        1                                                         /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos                        2                                                         /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos                        4                                                         /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask    */
+#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos                        5                                                         /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos                        6                                                         /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos                        8                                                         /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask    */
+#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos                        9                                                         /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos                        10                                                        /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos                        15                                                        /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */
+#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask    */
+
+// --------------------------------------  MCPWM_CAP_CLR  -----------------------------------------
+#define MCPWM_CAP_CLR_CAP_CLR0_Pos                            0                                                         /*!< MCPWM CAP_CLR: CAP_CLR0 Position    */
+#define MCPWM_CAP_CLR_CAP_CLR0_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR0 Mask        */
+#define MCPWM_CAP_CLR_CAP_CLR1_Pos                            1                                                         /*!< MCPWM CAP_CLR: CAP_CLR1 Position    */
+#define MCPWM_CAP_CLR_CAP_CLR1_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR1 Mask        */
+#define MCPWM_CAP_CLR_CAP_CLR2_Pos                            2                                                         /*!< MCPWM CAP_CLR: CAP_CLR2 Position    */
+#define MCPWM_CAP_CLR_CAP_CLR2_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR2 Mask        */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2C0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  I2C0_CONSET  ------------------------------------------
+#define I2C0_CONSET_AA_Pos                                    2                                                         /*!< I2C0 CONSET: AA Position            */
+#define I2C0_CONSET_AA_Msk                                    (0x01UL << I2C0_CONSET_AA_Pos)                            /*!< I2C0 CONSET: AA Mask                */
+#define I2C0_CONSET_SI_Pos                                    3                                                         /*!< I2C0 CONSET: SI Position            */
+#define I2C0_CONSET_SI_Msk                                    (0x01UL << I2C0_CONSET_SI_Pos)                            /*!< I2C0 CONSET: SI Mask                */
+#define I2C0_CONSET_STO_Pos                                   4                                                         /*!< I2C0 CONSET: STO Position           */
+#define I2C0_CONSET_STO_Msk                                   (0x01UL << I2C0_CONSET_STO_Pos)                           /*!< I2C0 CONSET: STO Mask               */
+#define I2C0_CONSET_STA_Pos                                   5                                                         /*!< I2C0 CONSET: STA Position           */
+#define I2C0_CONSET_STA_Msk                                   (0x01UL << I2C0_CONSET_STA_Pos)                           /*!< I2C0 CONSET: STA Mask               */
+#define I2C0_CONSET_I2EN_Pos                                  6                                                         /*!< I2C0 CONSET: I2EN Position          */
+#define I2C0_CONSET_I2EN_Msk                                  (0x01UL << I2C0_CONSET_I2EN_Pos)                          /*!< I2C0 CONSET: I2EN Mask              */
+
+// ----------------------------------------  I2C0_STAT  -------------------------------------------
+#define I2C0_STAT_Status_Pos                                  3                                                         /*!< I2C0 STAT: Status Position          */
+#define I2C0_STAT_Status_Msk                                  (0x1fUL << I2C0_STAT_Status_Pos)                          /*!< I2C0 STAT: Status Mask              */
+
+// ----------------------------------------  I2C0_DAT  --------------------------------------------
+#define I2C0_DAT_Data_Pos                                     0                                                         /*!< I2C0 DAT: Data Position             */
+#define I2C0_DAT_Data_Msk                                     (0x000000ffUL << I2C0_DAT_Data_Pos)                       /*!< I2C0 DAT: Data Mask                 */
+
+// ----------------------------------------  I2C0_ADR0  -------------------------------------------
+#define I2C0_ADR0_GC_Pos                                      0                                                         /*!< I2C0 ADR0: GC Position              */
+#define I2C0_ADR0_GC_Msk                                      (0x01UL << I2C0_ADR0_GC_Pos)                              /*!< I2C0 ADR0: GC Mask                  */
+#define I2C0_ADR0_Address_Pos                                 1                                                         /*!< I2C0 ADR0: Address Position         */
+#define I2C0_ADR0_Address_Msk                                 (0x7fUL << I2C0_ADR0_Address_Pos)                         /*!< I2C0 ADR0: Address Mask             */
+
+// ----------------------------------------  I2C0_SCLH  -------------------------------------------
+#define I2C0_SCLH_SCLH_Pos                                    0                                                         /*!< I2C0 SCLH: SCLH Position            */
+#define I2C0_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C0_SCLH_SCLH_Pos)                      /*!< I2C0 SCLH: SCLH Mask                */
+
+// ----------------------------------------  I2C0_SCLL  -------------------------------------------
+#define I2C0_SCLL_SCLL_Pos                                    0                                                         /*!< I2C0 SCLL: SCLL Position            */
+#define I2C0_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C0_SCLL_SCLL_Pos)                      /*!< I2C0 SCLL: SCLL Mask                */
+
+// ---------------------------------------  I2C0_CONCLR  ------------------------------------------
+#define I2C0_CONCLR_AAC_Pos                                   2                                                         /*!< I2C0 CONCLR: AAC Position           */
+#define I2C0_CONCLR_AAC_Msk                                   (0x01UL << I2C0_CONCLR_AAC_Pos)                           /*!< I2C0 CONCLR: AAC Mask               */
+#define I2C0_CONCLR_SIC_Pos                                   3                                                         /*!< I2C0 CONCLR: SIC Position           */
+#define I2C0_CONCLR_SIC_Msk                                   (0x01UL << I2C0_CONCLR_SIC_Pos)                           /*!< I2C0 CONCLR: SIC Mask               */
+#define I2C0_CONCLR_STAC_Pos                                  5                                                         /*!< I2C0 CONCLR: STAC Position          */
+#define I2C0_CONCLR_STAC_Msk                                  (0x01UL << I2C0_CONCLR_STAC_Pos)                          /*!< I2C0 CONCLR: STAC Mask              */
+#define I2C0_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C0 CONCLR: I2ENC Position         */
+#define I2C0_CONCLR_I2ENC_Msk                                 (0x01UL << I2C0_CONCLR_I2ENC_Pos)                         /*!< I2C0 CONCLR: I2ENC Mask             */
+
+// ---------------------------------------  I2C0_MMCTRL  ------------------------------------------
+#define I2C0_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C0 MMCTRL: MM_ENA Position        */
+#define I2C0_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C0_MMCTRL_MM_ENA_Pos)                        /*!< I2C0 MMCTRL: MM_ENA Mask            */
+#define I2C0_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C0 MMCTRL: ENA_SCL Position       */
+#define I2C0_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos)                       /*!< I2C0 MMCTRL: ENA_SCL Mask           */
+#define I2C0_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C0 MMCTRL: MATCH_ALL Position     */
+#define I2C0_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C0 MMCTRL: MATCH_ALL Mask         */
+
+// ----------------------------------------  I2C0_ADR1  -------------------------------------------
+#define I2C0_ADR1_GC_Pos                                      0                                                         /*!< I2C0 ADR1: GC Position              */
+#define I2C0_ADR1_GC_Msk                                      (0x01UL << I2C0_ADR1_GC_Pos)                              /*!< I2C0 ADR1: GC Mask                  */
+#define I2C0_ADR1_Address_Pos                                 1                                                         /*!< I2C0 ADR1: Address Position         */
+#define I2C0_ADR1_Address_Msk                                 (0x7fUL << I2C0_ADR1_Address_Pos)                         /*!< I2C0 ADR1: Address Mask             */
+
+// ----------------------------------------  I2C0_ADR2  -------------------------------------------
+#define I2C0_ADR2_GC_Pos                                      0                                                         /*!< I2C0 ADR2: GC Position              */
+#define I2C0_ADR2_GC_Msk                                      (0x01UL << I2C0_ADR2_GC_Pos)                              /*!< I2C0 ADR2: GC Mask                  */
+#define I2C0_ADR2_Address_Pos                                 1                                                         /*!< I2C0 ADR2: Address Position         */
+#define I2C0_ADR2_Address_Msk                                 (0x7fUL << I2C0_ADR2_Address_Pos)                         /*!< I2C0 ADR2: Address Mask             */
+
+// ----------------------------------------  I2C0_ADR3  -------------------------------------------
+#define I2C0_ADR3_GC_Pos                                      0                                                         /*!< I2C0 ADR3: GC Position              */
+#define I2C0_ADR3_GC_Msk                                      (0x01UL << I2C0_ADR3_GC_Pos)                              /*!< I2C0 ADR3: GC Mask                  */
+#define I2C0_ADR3_Address_Pos                                 1                                                         /*!< I2C0 ADR3: Address Position         */
+#define I2C0_ADR3_Address_Msk                                 (0x7fUL << I2C0_ADR3_Address_Pos)                         /*!< I2C0 ADR3: Address Mask             */
+
+// ------------------------------------  I2C0_DATA_BUFFER  ----------------------------------------
+#define I2C0_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C0 DATA_BUFFER: Data Position     */
+#define I2C0_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos)               /*!< I2C0 DATA_BUFFER: Data Mask         */
+
+// ---------------------------------------  I2C0_MASK0  -------------------------------------------
+#define I2C0_MASK0_MASK_Pos                                   1                                                         /*!< I2C0 MASK0: MASK Position           */
+#define I2C0_MASK0_MASK_Msk                                   (0x7fUL << I2C0_MASK0_MASK_Pos)                           /*!< I2C0 MASK0: MASK Mask               */
+
+// ---------------------------------------  I2C0_MASK1  -------------------------------------------
+#define I2C0_MASK1_MASK_Pos                                   1                                                         /*!< I2C0 MASK1: MASK Position           */
+#define I2C0_MASK1_MASK_Msk                                   (0x7fUL << I2C0_MASK1_MASK_Pos)                           /*!< I2C0 MASK1: MASK Mask               */
+
+// ---------------------------------------  I2C0_MASK2  -------------------------------------------
+#define I2C0_MASK2_MASK_Pos                                   1                                                         /*!< I2C0 MASK2: MASK Position           */
+#define I2C0_MASK2_MASK_Msk                                   (0x7fUL << I2C0_MASK2_MASK_Pos)                           /*!< I2C0 MASK2: MASK Mask               */
+
+// ---------------------------------------  I2C0_MASK3  -------------------------------------------
+#define I2C0_MASK3_MASK_Pos                                   1                                                         /*!< I2C0 MASK3: MASK Position           */
+#define I2C0_MASK3_MASK_Msk                                   (0x7fUL << I2C0_MASK3_MASK_Pos)                           /*!< I2C0 MASK3: MASK Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2C1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  I2C1_CONSET  ------------------------------------------
+#define I2C1_CONSET_AA_Pos                                    2                                                         /*!< I2C1 CONSET: AA Position            */
+#define I2C1_CONSET_AA_Msk                                    (0x01UL << I2C1_CONSET_AA_Pos)                            /*!< I2C1 CONSET: AA Mask                */
+#define I2C1_CONSET_SI_Pos                                    3                                                         /*!< I2C1 CONSET: SI Position            */
+#define I2C1_CONSET_SI_Msk                                    (0x01UL << I2C1_CONSET_SI_Pos)                            /*!< I2C1 CONSET: SI Mask                */
+#define I2C1_CONSET_STO_Pos                                   4                                                         /*!< I2C1 CONSET: STO Position           */
+#define I2C1_CONSET_STO_Msk                                   (0x01UL << I2C1_CONSET_STO_Pos)                           /*!< I2C1 CONSET: STO Mask               */
+#define I2C1_CONSET_STA_Pos                                   5                                                         /*!< I2C1 CONSET: STA Position           */
+#define I2C1_CONSET_STA_Msk                                   (0x01UL << I2C1_CONSET_STA_Pos)                           /*!< I2C1 CONSET: STA Mask               */
+#define I2C1_CONSET_I2EN_Pos                                  6                                                         /*!< I2C1 CONSET: I2EN Position          */
+#define I2C1_CONSET_I2EN_Msk                                  (0x01UL << I2C1_CONSET_I2EN_Pos)                          /*!< I2C1 CONSET: I2EN Mask              */
+
+// ----------------------------------------  I2C1_STAT  -------------------------------------------
+#define I2C1_STAT_Status_Pos                                  3                                                         /*!< I2C1 STAT: Status Position          */
+#define I2C1_STAT_Status_Msk                                  (0x1fUL << I2C1_STAT_Status_Pos)                          /*!< I2C1 STAT: Status Mask              */
+
+// ----------------------------------------  I2C1_DAT  --------------------------------------------
+#define I2C1_DAT_Data_Pos                                     0                                                         /*!< I2C1 DAT: Data Position             */
+#define I2C1_DAT_Data_Msk                                     (0x000000ffUL << I2C1_DAT_Data_Pos)                       /*!< I2C1 DAT: Data Mask                 */
+
+// ----------------------------------------  I2C1_ADR0  -------------------------------------------
+#define I2C1_ADR0_GC_Pos                                      0                                                         /*!< I2C1 ADR0: GC Position              */
+#define I2C1_ADR0_GC_Msk                                      (0x01UL << I2C1_ADR0_GC_Pos)                              /*!< I2C1 ADR0: GC Mask                  */
+#define I2C1_ADR0_Address_Pos                                 1                                                         /*!< I2C1 ADR0: Address Position         */
+#define I2C1_ADR0_Address_Msk                                 (0x7fUL << I2C1_ADR0_Address_Pos)                         /*!< I2C1 ADR0: Address Mask             */
+
+// ----------------------------------------  I2C1_SCLH  -------------------------------------------
+#define I2C1_SCLH_SCLH_Pos                                    0                                                         /*!< I2C1 SCLH: SCLH Position            */
+#define I2C1_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C1_SCLH_SCLH_Pos)                      /*!< I2C1 SCLH: SCLH Mask                */
+
+// ----------------------------------------  I2C1_SCLL  -------------------------------------------
+#define I2C1_SCLL_SCLL_Pos                                    0                                                         /*!< I2C1 SCLL: SCLL Position            */
+#define I2C1_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C1_SCLL_SCLL_Pos)                      /*!< I2C1 SCLL: SCLL Mask                */
+
+// ---------------------------------------  I2C1_CONCLR  ------------------------------------------
+#define I2C1_CONCLR_AAC_Pos                                   2                                                         /*!< I2C1 CONCLR: AAC Position           */
+#define I2C1_CONCLR_AAC_Msk                                   (0x01UL << I2C1_CONCLR_AAC_Pos)                           /*!< I2C1 CONCLR: AAC Mask               */
+#define I2C1_CONCLR_SIC_Pos                                   3                                                         /*!< I2C1 CONCLR: SIC Position           */
+#define I2C1_CONCLR_SIC_Msk                                   (0x01UL << I2C1_CONCLR_SIC_Pos)                           /*!< I2C1 CONCLR: SIC Mask               */
+#define I2C1_CONCLR_STAC_Pos                                  5                                                         /*!< I2C1 CONCLR: STAC Position          */
+#define I2C1_CONCLR_STAC_Msk                                  (0x01UL << I2C1_CONCLR_STAC_Pos)                          /*!< I2C1 CONCLR: STAC Mask              */
+#define I2C1_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C1 CONCLR: I2ENC Position         */
+#define I2C1_CONCLR_I2ENC_Msk                                 (0x01UL << I2C1_CONCLR_I2ENC_Pos)                         /*!< I2C1 CONCLR: I2ENC Mask             */
+
+// ---------------------------------------  I2C1_MMCTRL  ------------------------------------------
+#define I2C1_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C1 MMCTRL: MM_ENA Position        */
+#define I2C1_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C1_MMCTRL_MM_ENA_Pos)                        /*!< I2C1 MMCTRL: MM_ENA Mask            */
+#define I2C1_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C1 MMCTRL: ENA_SCL Position       */
+#define I2C1_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos)                       /*!< I2C1 MMCTRL: ENA_SCL Mask           */
+#define I2C1_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C1 MMCTRL: MATCH_ALL Position     */
+#define I2C1_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C1 MMCTRL: MATCH_ALL Mask         */
+
+// ----------------------------------------  I2C1_ADR1  -------------------------------------------
+#define I2C1_ADR1_GC_Pos                                      0                                                         /*!< I2C1 ADR1: GC Position              */
+#define I2C1_ADR1_GC_Msk                                      (0x01UL << I2C1_ADR1_GC_Pos)                              /*!< I2C1 ADR1: GC Mask                  */
+#define I2C1_ADR1_Address_Pos                                 1                                                         /*!< I2C1 ADR1: Address Position         */
+#define I2C1_ADR1_Address_Msk                                 (0x7fUL << I2C1_ADR1_Address_Pos)                         /*!< I2C1 ADR1: Address Mask             */
+
+// ----------------------------------------  I2C1_ADR2  -------------------------------------------
+#define I2C1_ADR2_GC_Pos                                      0                                                         /*!< I2C1 ADR2: GC Position              */
+#define I2C1_ADR2_GC_Msk                                      (0x01UL << I2C1_ADR2_GC_Pos)                              /*!< I2C1 ADR2: GC Mask                  */
+#define I2C1_ADR2_Address_Pos                                 1                                                         /*!< I2C1 ADR2: Address Position         */
+#define I2C1_ADR2_Address_Msk                                 (0x7fUL << I2C1_ADR2_Address_Pos)                         /*!< I2C1 ADR2: Address Mask             */
+
+// ----------------------------------------  I2C1_ADR3  -------------------------------------------
+#define I2C1_ADR3_GC_Pos                                      0                                                         /*!< I2C1 ADR3: GC Position              */
+#define I2C1_ADR3_GC_Msk                                      (0x01UL << I2C1_ADR3_GC_Pos)                              /*!< I2C1 ADR3: GC Mask                  */
+#define I2C1_ADR3_Address_Pos                                 1                                                         /*!< I2C1 ADR3: Address Position         */
+#define I2C1_ADR3_Address_Msk                                 (0x7fUL << I2C1_ADR3_Address_Pos)                         /*!< I2C1 ADR3: Address Mask             */
+
+// ------------------------------------  I2C1_DATA_BUFFER  ----------------------------------------
+#define I2C1_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C1 DATA_BUFFER: Data Position     */
+#define I2C1_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos)               /*!< I2C1 DATA_BUFFER: Data Mask         */
+
+// ---------------------------------------  I2C1_MASK0  -------------------------------------------
+#define I2C1_MASK0_MASK_Pos                                   1                                                         /*!< I2C1 MASK0: MASK Position           */
+#define I2C1_MASK0_MASK_Msk                                   (0x7fUL << I2C1_MASK0_MASK_Pos)                           /*!< I2C1 MASK0: MASK Mask               */
+
+// ---------------------------------------  I2C1_MASK1  -------------------------------------------
+#define I2C1_MASK1_MASK_Pos                                   1                                                         /*!< I2C1 MASK1: MASK Position           */
+#define I2C1_MASK1_MASK_Msk                                   (0x7fUL << I2C1_MASK1_MASK_Pos)                           /*!< I2C1 MASK1: MASK Mask               */
+
+// ---------------------------------------  I2C1_MASK2  -------------------------------------------
+#define I2C1_MASK2_MASK_Pos                                   1                                                         /*!< I2C1 MASK2: MASK Position           */
+#define I2C1_MASK2_MASK_Msk                                   (0x7fUL << I2C1_MASK2_MASK_Pos)                           /*!< I2C1 MASK2: MASK Mask               */
+
+// ---------------------------------------  I2C1_MASK3  -------------------------------------------
+#define I2C1_MASK3_MASK_Pos                                   1                                                         /*!< I2C1 MASK3: MASK Position           */
+#define I2C1_MASK3_MASK_Msk                                   (0x7fUL << I2C1_MASK3_MASK_Pos)                           /*!< I2C1 MASK3: MASK Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2S0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  I2S0_DAO  --------------------------------------------
+#define I2S0_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAO: WORDWIDTH Position        */
+#define I2S0_DAO_WORDWIDTH_Msk                                (0x03UL << I2S0_DAO_WORDWIDTH_Pos)                        /*!< I2S0 DAO: WORDWIDTH Mask            */
+#define I2S0_DAO_MONO_Pos                                     2                                                         /*!< I2S0 DAO: MONO Position             */
+#define I2S0_DAO_MONO_Msk                                     (0x01UL << I2S0_DAO_MONO_Pos)                             /*!< I2S0 DAO: MONO Mask                 */
+#define I2S0_DAO_STOP_Pos                                     3                                                         /*!< I2S0 DAO: STOP Position             */
+#define I2S0_DAO_STOP_Msk                                     (0x01UL << I2S0_DAO_STOP_Pos)                             /*!< I2S0 DAO: STOP Mask                 */
+#define I2S0_DAO_RESET_Pos                                    4                                                         /*!< I2S0 DAO: RESET Position            */
+#define I2S0_DAO_RESET_Msk                                    (0x01UL << I2S0_DAO_RESET_Pos)                            /*!< I2S0 DAO: RESET Mask                */
+#define I2S0_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAO: WS_SEL Position           */
+#define I2S0_DAO_WS_SEL_Msk                                   (0x01UL << I2S0_DAO_WS_SEL_Pos)                           /*!< I2S0 DAO: WS_SEL Mask               */
+#define I2S0_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAO: WS_HALFPERIOD Position    */
+#define I2S0_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos)              /*!< I2S0 DAO: WS_HALFPERIOD Mask        */
+#define I2S0_DAO_MUTE_Pos                                     15                                                        /*!< I2S0 DAO: MUTE Position             */
+#define I2S0_DAO_MUTE_Msk                                     (0x01UL << I2S0_DAO_MUTE_Pos)                             /*!< I2S0 DAO: MUTE Mask                 */
+
+// ----------------------------------------  I2S0_DAI  --------------------------------------------
+#define I2S0_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAI: WORDWIDTH Position        */
+#define I2S0_DAI_WORDWIDTH_Msk                                (0x03UL << I2S0_DAI_WORDWIDTH_Pos)                        /*!< I2S0 DAI: WORDWIDTH Mask            */
+#define I2S0_DAI_MONO_Pos                                     2                                                         /*!< I2S0 DAI: MONO Position             */
+#define I2S0_DAI_MONO_Msk                                     (0x01UL << I2S0_DAI_MONO_Pos)                             /*!< I2S0 DAI: MONO Mask                 */
+#define I2S0_DAI_STOP_Pos                                     3                                                         /*!< I2S0 DAI: STOP Position             */
+#define I2S0_DAI_STOP_Msk                                     (0x01UL << I2S0_DAI_STOP_Pos)                             /*!< I2S0 DAI: STOP Mask                 */
+#define I2S0_DAI_RESET_Pos                                    4                                                         /*!< I2S0 DAI: RESET Position            */
+#define I2S0_DAI_RESET_Msk                                    (0x01UL << I2S0_DAI_RESET_Pos)                            /*!< I2S0 DAI: RESET Mask                */
+#define I2S0_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAI: WS_SEL Position           */
+#define I2S0_DAI_WS_SEL_Msk                                   (0x01UL << I2S0_DAI_WS_SEL_Pos)                           /*!< I2S0 DAI: WS_SEL Mask               */
+#define I2S0_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAI: WS_HALFPERIOD Position    */
+#define I2S0_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos)              /*!< I2S0 DAI: WS_HALFPERIOD Mask        */
+
+// ---------------------------------------  I2S0_TXFIFO  ------------------------------------------
+#define I2S0_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S0 TXFIFO: I2STXFIFO Position     */
+#define I2S0_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos)               /*!< I2S0 TXFIFO: I2STXFIFO Mask         */
+
+// ---------------------------------------  I2S0_RXFIFO  ------------------------------------------
+#define I2S0_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S0 RXFIFO: I2SRXFIFO Position     */
+#define I2S0_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S0 RXFIFO: I2SRXFIFO Mask         */
+
+// ---------------------------------------  I2S0_STATE  -------------------------------------------
+#define I2S0_STATE_IRQ_Pos                                    0                                                         /*!< I2S0 STATE: IRQ Position            */
+#define I2S0_STATE_IRQ_Msk                                    (0x01UL << I2S0_STATE_IRQ_Pos)                            /*!< I2S0 STATE: IRQ Mask                */
+#define I2S0_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S0 STATE: DMAREQ1 Position        */
+#define I2S0_STATE_DMAREQ1_Msk                                (0x01UL << I2S0_STATE_DMAREQ1_Pos)                        /*!< I2S0 STATE: DMAREQ1 Mask            */
+#define I2S0_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S0 STATE: DMAREQ2 Position        */
+#define I2S0_STATE_DMAREQ2_Msk                                (0x01UL << I2S0_STATE_DMAREQ2_Pos)                        /*!< I2S0 STATE: DMAREQ2 Mask            */
+#define I2S0_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S0 STATE: RX_LEVEL Position       */
+#define I2S0_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_RX_LEVEL_Pos)                       /*!< I2S0 STATE: RX_LEVEL Mask           */
+#define I2S0_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S0 STATE: TX_LEVEL Position       */
+#define I2S0_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_TX_LEVEL_Pos)                       /*!< I2S0 STATE: TX_LEVEL Mask           */
+
+// ----------------------------------------  I2S0_DMA1  -------------------------------------------
+#define I2S0_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S0 DMA1: RX_DMA1_ENABLE Position  */
+#define I2S0_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask      */
+#define I2S0_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S0 DMA1: TX_DMA1_ENABLE Position  */
+#define I2S0_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask      */
+#define I2S0_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position   */
+#define I2S0_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask       */
+#define I2S0_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position   */
+#define I2S0_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask       */
+
+// ----------------------------------------  I2S0_DMA2  -------------------------------------------
+#define I2S0_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S0 DMA2: RX_DMA2_ENABLE Position  */
+#define I2S0_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask      */
+#define I2S0_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S0 DMA2: TX_DMA2_ENABLE Position  */
+#define I2S0_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask      */
+#define I2S0_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position   */
+#define I2S0_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask       */
+#define I2S0_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position   */
+#define I2S0_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask       */
+
+// ----------------------------------------  I2S0_IRQ  --------------------------------------------
+#define I2S0_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S0 IRQ: RX_IRQ_ENABLE Position    */
+#define I2S0_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask        */
+#define I2S0_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S0 IRQ: TX_IRQ_ENABLE Position    */
+#define I2S0_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask        */
+#define I2S0_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S0 IRQ: RX_DEPTH_IRQ Position     */
+#define I2S0_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask         */
+#define I2S0_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S0 IRQ: TX_DEPTH_IRQ Position     */
+#define I2S0_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask         */
+
+// ---------------------------------------  I2S0_TXRATE  ------------------------------------------
+#define I2S0_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 TXRATE: Y_DIVIDER Position     */
+#define I2S0_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos)               /*!< I2S0 TXRATE: Y_DIVIDER Mask         */
+#define I2S0_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 TXRATE: X_DIVIDER Position     */
+#define I2S0_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos)               /*!< I2S0 TXRATE: X_DIVIDER Mask         */
+
+// ---------------------------------------  I2S0_RXRATE  ------------------------------------------
+#define I2S0_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 RXRATE: Y_DIVIDER Position     */
+#define I2S0_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos)               /*!< I2S0 RXRATE: Y_DIVIDER Mask         */
+#define I2S0_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 RXRATE: X_DIVIDER Position     */
+#define I2S0_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos)               /*!< I2S0 RXRATE: X_DIVIDER Mask         */
+
+// -------------------------------------  I2S0_TXBITRATE  -----------------------------------------
+#define I2S0_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S0 TXBITRATE: TX_BITRATE Position */
+#define I2S0_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S0 TXBITRATE: TX_BITRATE Mask     */
+
+// -------------------------------------  I2S0_RXBITRATE  -----------------------------------------
+#define I2S0_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S0 RXBITRATE: RX_BITRATE Position */
+#define I2S0_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S0 RXBITRATE: RX_BITRATE Mask     */
+
+// ---------------------------------------  I2S0_TXMODE  ------------------------------------------
+#define I2S0_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S0 TXMODE: TXCLKSEL Position      */
+#define I2S0_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos)                      /*!< I2S0 TXMODE: TXCLKSEL Mask          */
+#define I2S0_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S0 TXMODE: TX4PIN Position        */
+#define I2S0_TXMODE_TX4PIN_Msk                                (0x01UL << I2S0_TXMODE_TX4PIN_Pos)                        /*!< I2S0 TXMODE: TX4PIN Mask            */
+#define I2S0_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S0 TXMODE: TXMCENA Position       */
+#define I2S0_TXMODE_TXMCENA_Msk                               (0x01UL << I2S0_TXMODE_TXMCENA_Pos)                       /*!< I2S0 TXMODE: TXMCENA Mask           */
+
+// ---------------------------------------  I2S0_RXMODE  ------------------------------------------
+#define I2S0_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S0 RXMODE: RXCLKSEL Position      */
+#define I2S0_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos)                      /*!< I2S0 RXMODE: RXCLKSEL Mask          */
+#define I2S0_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S0 RXMODE: RX4PIN Position        */
+#define I2S0_RXMODE_RX4PIN_Msk                                (0x01UL << I2S0_RXMODE_RX4PIN_Pos)                        /*!< I2S0 RXMODE: RX4PIN Mask            */
+#define I2S0_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S0 RXMODE: RXMCENA Position       */
+#define I2S0_RXMODE_RXMCENA_Msk                               (0x01UL << I2S0_RXMODE_RXMCENA_Pos)                       /*!< I2S0 RXMODE: RXMCENA Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2S1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  I2S1_DAO  --------------------------------------------
+#define I2S1_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAO: WORDWIDTH Position        */
+#define I2S1_DAO_WORDWIDTH_Msk                                (0x03UL << I2S1_DAO_WORDWIDTH_Pos)                        /*!< I2S1 DAO: WORDWIDTH Mask            */
+#define I2S1_DAO_MONO_Pos                                     2                                                         /*!< I2S1 DAO: MONO Position             */
+#define I2S1_DAO_MONO_Msk                                     (0x01UL << I2S1_DAO_MONO_Pos)                             /*!< I2S1 DAO: MONO Mask                 */
+#define I2S1_DAO_STOP_Pos                                     3                                                         /*!< I2S1 DAO: STOP Position             */
+#define I2S1_DAO_STOP_Msk                                     (0x01UL << I2S1_DAO_STOP_Pos)                             /*!< I2S1 DAO: STOP Mask                 */
+#define I2S1_DAO_RESET_Pos                                    4                                                         /*!< I2S1 DAO: RESET Position            */
+#define I2S1_DAO_RESET_Msk                                    (0x01UL << I2S1_DAO_RESET_Pos)                            /*!< I2S1 DAO: RESET Mask                */
+#define I2S1_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAO: WS_SEL Position           */
+#define I2S1_DAO_WS_SEL_Msk                                   (0x01UL << I2S1_DAO_WS_SEL_Pos)                           /*!< I2S1 DAO: WS_SEL Mask               */
+#define I2S1_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAO: WS_HALFPERIOD Position    */
+#define I2S1_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos)              /*!< I2S1 DAO: WS_HALFPERIOD Mask        */
+#define I2S1_DAO_MUTE_Pos                                     15                                                        /*!< I2S1 DAO: MUTE Position             */
+#define I2S1_DAO_MUTE_Msk                                     (0x01UL << I2S1_DAO_MUTE_Pos)                             /*!< I2S1 DAO: MUTE Mask                 */
+
+// ----------------------------------------  I2S1_DAI  --------------------------------------------
+#define I2S1_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAI: WORDWIDTH Position        */
+#define I2S1_DAI_WORDWIDTH_Msk                                (0x03UL << I2S1_DAI_WORDWIDTH_Pos)                        /*!< I2S1 DAI: WORDWIDTH Mask            */
+#define I2S1_DAI_MONO_Pos                                     2                                                         /*!< I2S1 DAI: MONO Position             */
+#define I2S1_DAI_MONO_Msk                                     (0x01UL << I2S1_DAI_MONO_Pos)                             /*!< I2S1 DAI: MONO Mask                 */
+#define I2S1_DAI_STOP_Pos                                     3                                                         /*!< I2S1 DAI: STOP Position             */
+#define I2S1_DAI_STOP_Msk                                     (0x01UL << I2S1_DAI_STOP_Pos)                             /*!< I2S1 DAI: STOP Mask                 */
+#define I2S1_DAI_RESET_Pos                                    4                                                         /*!< I2S1 DAI: RESET Position            */
+#define I2S1_DAI_RESET_Msk                                    (0x01UL << I2S1_DAI_RESET_Pos)                            /*!< I2S1 DAI: RESET Mask                */
+#define I2S1_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAI: WS_SEL Position           */
+#define I2S1_DAI_WS_SEL_Msk                                   (0x01UL << I2S1_DAI_WS_SEL_Pos)                           /*!< I2S1 DAI: WS_SEL Mask               */
+#define I2S1_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAI: WS_HALFPERIOD Position    */
+#define I2S1_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos)              /*!< I2S1 DAI: WS_HALFPERIOD Mask        */
+
+// ---------------------------------------  I2S1_TXFIFO  ------------------------------------------
+#define I2S1_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S1 TXFIFO: I2STXFIFO Position     */
+#define I2S1_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos)               /*!< I2S1 TXFIFO: I2STXFIFO Mask         */
+
+// ---------------------------------------  I2S1_RXFIFO  ------------------------------------------
+#define I2S1_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S1 RXFIFO: I2SRXFIFO Position     */
+#define I2S1_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S1 RXFIFO: I2SRXFIFO Mask         */
+
+// ---------------------------------------  I2S1_STATE  -------------------------------------------
+#define I2S1_STATE_IRQ_Pos                                    0                                                         /*!< I2S1 STATE: IRQ Position            */
+#define I2S1_STATE_IRQ_Msk                                    (0x01UL << I2S1_STATE_IRQ_Pos)                            /*!< I2S1 STATE: IRQ Mask                */
+#define I2S1_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S1 STATE: DMAREQ1 Position        */
+#define I2S1_STATE_DMAREQ1_Msk                                (0x01UL << I2S1_STATE_DMAREQ1_Pos)                        /*!< I2S1 STATE: DMAREQ1 Mask            */
+#define I2S1_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S1 STATE: DMAREQ2 Position        */
+#define I2S1_STATE_DMAREQ2_Msk                                (0x01UL << I2S1_STATE_DMAREQ2_Pos)                        /*!< I2S1 STATE: DMAREQ2 Mask            */
+#define I2S1_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S1 STATE: RX_LEVEL Position       */
+#define I2S1_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_RX_LEVEL_Pos)                       /*!< I2S1 STATE: RX_LEVEL Mask           */
+#define I2S1_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S1 STATE: TX_LEVEL Position       */
+#define I2S1_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_TX_LEVEL_Pos)                       /*!< I2S1 STATE: TX_LEVEL Mask           */
+
+// ----------------------------------------  I2S1_DMA1  -------------------------------------------
+#define I2S1_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S1 DMA1: RX_DMA1_ENABLE Position  */
+#define I2S1_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask      */
+#define I2S1_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S1 DMA1: TX_DMA1_ENABLE Position  */
+#define I2S1_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask      */
+#define I2S1_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position   */
+#define I2S1_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask       */
+#define I2S1_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position   */
+#define I2S1_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask       */
+
+// ----------------------------------------  I2S1_DMA2  -------------------------------------------
+#define I2S1_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S1 DMA2: RX_DMA2_ENABLE Position  */
+#define I2S1_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask      */
+#define I2S1_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S1 DMA2: TX_DMA2_ENABLE Position  */
+#define I2S1_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask      */
+#define I2S1_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position   */
+#define I2S1_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask       */
+#define I2S1_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position   */
+#define I2S1_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask       */
+
+// ----------------------------------------  I2S1_IRQ  --------------------------------------------
+#define I2S1_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S1 IRQ: RX_IRQ_ENABLE Position    */
+#define I2S1_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask        */
+#define I2S1_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S1 IRQ: TX_IRQ_ENABLE Position    */
+#define I2S1_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask        */
+#define I2S1_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S1 IRQ: RX_DEPTH_IRQ Position     */
+#define I2S1_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask         */
+#define I2S1_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S1 IRQ: TX_DEPTH_IRQ Position     */
+#define I2S1_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask         */
+
+// ---------------------------------------  I2S1_TXRATE  ------------------------------------------
+#define I2S1_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 TXRATE: Y_DIVIDER Position     */
+#define I2S1_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos)               /*!< I2S1 TXRATE: Y_DIVIDER Mask         */
+#define I2S1_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 TXRATE: X_DIVIDER Position     */
+#define I2S1_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos)               /*!< I2S1 TXRATE: X_DIVIDER Mask         */
+
+// ---------------------------------------  I2S1_RXRATE  ------------------------------------------
+#define I2S1_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 RXRATE: Y_DIVIDER Position     */
+#define I2S1_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos)               /*!< I2S1 RXRATE: Y_DIVIDER Mask         */
+#define I2S1_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 RXRATE: X_DIVIDER Position     */
+#define I2S1_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos)               /*!< I2S1 RXRATE: X_DIVIDER Mask         */
+
+// -------------------------------------  I2S1_TXBITRATE  -----------------------------------------
+#define I2S1_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S1 TXBITRATE: TX_BITRATE Position */
+#define I2S1_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S1 TXBITRATE: TX_BITRATE Mask     */
+
+// -------------------------------------  I2S1_RXBITRATE  -----------------------------------------
+#define I2S1_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S1 RXBITRATE: RX_BITRATE Position */
+#define I2S1_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S1 RXBITRATE: RX_BITRATE Mask     */
+
+// ---------------------------------------  I2S1_TXMODE  ------------------------------------------
+#define I2S1_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S1 TXMODE: TXCLKSEL Position      */
+#define I2S1_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos)                      /*!< I2S1 TXMODE: TXCLKSEL Mask          */
+#define I2S1_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S1 TXMODE: TX4PIN Position        */
+#define I2S1_TXMODE_TX4PIN_Msk                                (0x01UL << I2S1_TXMODE_TX4PIN_Pos)                        /*!< I2S1 TXMODE: TX4PIN Mask            */
+#define I2S1_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S1 TXMODE: TXMCENA Position       */
+#define I2S1_TXMODE_TXMCENA_Msk                               (0x01UL << I2S1_TXMODE_TXMCENA_Pos)                       /*!< I2S1 TXMODE: TXMCENA Mask           */
+
+// ---------------------------------------  I2S1_RXMODE  ------------------------------------------
+#define I2S1_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S1 RXMODE: RXCLKSEL Position      */
+#define I2S1_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos)                      /*!< I2S1 RXMODE: RXCLKSEL Mask          */
+#define I2S1_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S1 RXMODE: RX4PIN Position        */
+#define I2S1_RXMODE_RX4PIN_Msk                                (0x01UL << I2S1_RXMODE_RX4PIN_Pos)                        /*!< I2S1 RXMODE: RX4PIN Mask            */
+#define I2S1_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S1 RXMODE: RXMCENA Position       */
+#define I2S1_RXMODE_RXMCENA_Msk                               (0x01UL << I2S1_RXMODE_RXMCENA_Pos)                       /*!< I2S1 RXMODE: RXMCENA Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                C_CAN1 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  C_CAN1_CNTL  ------------------------------------------
+#define C_CAN1_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN1 CNTL: INIT Position          */
+#define C_CAN1_CNTL_INIT_Msk                                  (0x01UL << C_CAN1_CNTL_INIT_Pos)                          /*!< C_CAN1 CNTL: INIT Mask              */
+#define C_CAN1_CNTL_IE_Pos                                    1                                                         /*!< C_CAN1 CNTL: IE Position            */
+#define C_CAN1_CNTL_IE_Msk                                    (0x01UL << C_CAN1_CNTL_IE_Pos)                            /*!< C_CAN1 CNTL: IE Mask                */
+#define C_CAN1_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN1 CNTL: SIE Position           */
+#define C_CAN1_CNTL_SIE_Msk                                   (0x01UL << C_CAN1_CNTL_SIE_Pos)                           /*!< C_CAN1 CNTL: SIE Mask               */
+#define C_CAN1_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN1 CNTL: EIE Position           */
+#define C_CAN1_CNTL_EIE_Msk                                   (0x01UL << C_CAN1_CNTL_EIE_Pos)                           /*!< C_CAN1 CNTL: EIE Mask               */
+#define C_CAN1_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN1 CNTL: DAR Position           */
+#define C_CAN1_CNTL_DAR_Msk                                   (0x01UL << C_CAN1_CNTL_DAR_Pos)                           /*!< C_CAN1 CNTL: DAR Mask               */
+#define C_CAN1_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN1 CNTL: CCE Position           */
+#define C_CAN1_CNTL_CCE_Msk                                   (0x01UL << C_CAN1_CNTL_CCE_Pos)                           /*!< C_CAN1 CNTL: CCE Mask               */
+#define C_CAN1_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN1 CNTL: TEST Position          */
+#define C_CAN1_CNTL_TEST_Msk                                  (0x01UL << C_CAN1_CNTL_TEST_Pos)                          /*!< C_CAN1 CNTL: TEST Mask              */
+
+// ---------------------------------------  C_CAN1_STAT  ------------------------------------------
+#define C_CAN1_STAT_LEC_Pos                                   0                                                         /*!< C_CAN1 STAT: LEC Position           */
+#define C_CAN1_STAT_LEC_Msk                                   (0x07UL << C_CAN1_STAT_LEC_Pos)                           /*!< C_CAN1 STAT: LEC Mask               */
+#define C_CAN1_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN1 STAT: TXOK Position          */
+#define C_CAN1_STAT_TXOK_Msk                                  (0x01UL << C_CAN1_STAT_TXOK_Pos)                          /*!< C_CAN1 STAT: TXOK Mask              */
+#define C_CAN1_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN1 STAT: RXOK Position          */
+#define C_CAN1_STAT_RXOK_Msk                                  (0x01UL << C_CAN1_STAT_RXOK_Pos)                          /*!< C_CAN1 STAT: RXOK Mask              */
+#define C_CAN1_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN1 STAT: EPASS Position         */
+#define C_CAN1_STAT_EPASS_Msk                                 (0x01UL << C_CAN1_STAT_EPASS_Pos)                         /*!< C_CAN1 STAT: EPASS Mask             */
+#define C_CAN1_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN1 STAT: EWARN Position         */
+#define C_CAN1_STAT_EWARN_Msk                                 (0x01UL << C_CAN1_STAT_EWARN_Pos)                         /*!< C_CAN1 STAT: EWARN Mask             */
+#define C_CAN1_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN1 STAT: BOFF Position          */
+#define C_CAN1_STAT_BOFF_Msk                                  (0x01UL << C_CAN1_STAT_BOFF_Pos)                          /*!< C_CAN1 STAT: BOFF Mask              */
+
+// ----------------------------------------  C_CAN1_EC  -------------------------------------------
+#define C_CAN1_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN1 EC: TEC_7_0 Position         */
+#define C_CAN1_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos)                   /*!< C_CAN1 EC: TEC_7_0 Mask             */
+#define C_CAN1_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN1 EC: REC_6_0 Position         */
+#define C_CAN1_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN1_EC_REC_6_0_Pos)                         /*!< C_CAN1 EC: REC_6_0 Mask             */
+#define C_CAN1_EC_RP_Pos                                      15                                                        /*!< C_CAN1 EC: RP Position              */
+#define C_CAN1_EC_RP_Msk                                      (0x01UL << C_CAN1_EC_RP_Pos)                              /*!< C_CAN1 EC: RP Mask                  */
+
+// ----------------------------------------  C_CAN1_BT  -------------------------------------------
+#define C_CAN1_BT_BRP_Pos                                     0                                                         /*!< C_CAN1 BT: BRP Position             */
+#define C_CAN1_BT_BRP_Msk                                     (0x3fUL << C_CAN1_BT_BRP_Pos)                             /*!< C_CAN1 BT: BRP Mask                 */
+#define C_CAN1_BT_SJW_Pos                                     6                                                         /*!< C_CAN1 BT: SJW Position             */
+#define C_CAN1_BT_SJW_Msk                                     (0x03UL << C_CAN1_BT_SJW_Pos)                             /*!< C_CAN1 BT: SJW Mask                 */
+#define C_CAN1_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN1 BT: TSEG1 Position           */
+#define C_CAN1_BT_TSEG1_Msk                                   (0x0fUL << C_CAN1_BT_TSEG1_Pos)                           /*!< C_CAN1 BT: TSEG1 Mask               */
+#define C_CAN1_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN1 BT: TSEG2 Position           */
+#define C_CAN1_BT_TSEG2_Msk                                   (0x07UL << C_CAN1_BT_TSEG2_Pos)                           /*!< C_CAN1 BT: TSEG2 Mask               */
+
+// ---------------------------------------  C_CAN1_INT  -------------------------------------------
+#define C_CAN1_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN1 INT: INTID15_0 Position      */
+#define C_CAN1_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos)                /*!< C_CAN1 INT: INTID15_0 Mask          */
+
+// ---------------------------------------  C_CAN1_TEST  ------------------------------------------
+#define C_CAN1_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN1 TEST: BASIC Position         */
+#define C_CAN1_TEST_BASIC_Msk                                 (0x01UL << C_CAN1_TEST_BASIC_Pos)                         /*!< C_CAN1 TEST: BASIC Mask             */
+#define C_CAN1_TEST_SILENT_Pos                                3                                                         /*!< C_CAN1 TEST: SILENT Position        */
+#define C_CAN1_TEST_SILENT_Msk                                (0x01UL << C_CAN1_TEST_SILENT_Pos)                        /*!< C_CAN1 TEST: SILENT Mask            */
+#define C_CAN1_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN1 TEST: LBACK Position         */
+#define C_CAN1_TEST_LBACK_Msk                                 (0x01UL << C_CAN1_TEST_LBACK_Pos)                         /*!< C_CAN1 TEST: LBACK Mask             */
+#define C_CAN1_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN1 TEST: TX1_0 Position         */
+#define C_CAN1_TEST_TX1_0_Msk                                 (0x03UL << C_CAN1_TEST_TX1_0_Pos)                         /*!< C_CAN1 TEST: TX1_0 Mask             */
+#define C_CAN1_TEST_RX_Pos                                    7                                                         /*!< C_CAN1 TEST: RX Position            */
+#define C_CAN1_TEST_RX_Msk                                    (0x01UL << C_CAN1_TEST_RX_Pos)                            /*!< C_CAN1 TEST: RX Mask                */
+
+// ---------------------------------------  C_CAN1_BRPE  ------------------------------------------
+#define C_CAN1_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN1 BRPE: BRPE Position          */
+#define C_CAN1_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN1_BRPE_BRPE_Pos)                          /*!< C_CAN1 BRPE: BRPE Mask              */
+
+// ------------------------------------  C_CAN1_IF1_CMDREQ  ---------------------------------------
+#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */
+#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask     */
+#define C_CAN1_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF1_CMDREQ: BUSY Position    */
+#define C_CAN1_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF1_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN1_IF1_CMDMSK_W  --------------------------------------
+#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */
+#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask    */
+#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */
+#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask    */
+#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */
+#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask    */
+#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */
+#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position  */
+#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask      */
+#define C_CAN1_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_W: ARB Position   */
+#define C_CAN1_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask       */
+#define C_CAN1_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_W: MASK Position  */
+#define C_CAN1_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask      */
+#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */
+#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask     */
+
+// -----------------------------------  C_CAN1_IF1_CMDMSK_R  --------------------------------------
+#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */
+#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask    */
+#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */
+#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask    */
+#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */
+#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */
+#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position  */
+#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask      */
+#define C_CAN1_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_R: ARB Position   */
+#define C_CAN1_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask       */
+#define C_CAN1_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_R: MASK Position  */
+#define C_CAN1_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask      */
+#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */
+#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask     */
+
+// -------------------------------------  C_CAN1_IF1_MSK1  ----------------------------------------
+#define C_CAN1_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF1_MSK1: MSK15_0 Position   */
+#define C_CAN1_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN1_IF1_MSK2  ----------------------------------------
+#define C_CAN1_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF1_MSK2: MSK28_16 Position  */
+#define C_CAN1_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask      */
+#define C_CAN1_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF1_MSK2: MDIR Position      */
+#define C_CAN1_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF1_MSK2: MDIR Mask          */
+#define C_CAN1_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF1_MSK2: MXTD Position      */
+#define C_CAN1_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF1_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN1_IF1_ARB1  ----------------------------------------
+#define C_CAN1_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF1_ARB1: ID15_0 Position    */
+#define C_CAN1_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF1_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN1_IF1_ARB2  ----------------------------------------
+#define C_CAN1_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF1_ARB2: ID28_16 Position   */
+#define C_CAN1_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF1_ARB2: ID28_16 Mask       */
+#define C_CAN1_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF1_ARB2: DIR Position       */
+#define C_CAN1_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos)                       /*!< C_CAN1 IF1_ARB2: DIR Mask           */
+#define C_CAN1_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF1_ARB2: XTD Position       */
+#define C_CAN1_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos)                       /*!< C_CAN1 IF1_ARB2: XTD Mask           */
+#define C_CAN1_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF1_ARB2: MSGVAL Position    */
+#define C_CAN1_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF1_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN1_IF1_MCTRL  ----------------------------------------
+#define C_CAN1_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position   */
+#define C_CAN1_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask       */
+#define C_CAN1_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF1_MCTRL: EOB Position      */
+#define C_CAN1_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF1_MCTRL: EOB Mask          */
+#define C_CAN1_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF1_MCTRL: TXRQST Position   */
+#define C_CAN1_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF1_MCTRL: TXRQST Mask       */
+#define C_CAN1_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF1_MCTRL: RMTEN Position    */
+#define C_CAN1_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF1_MCTRL: RMTEN Mask        */
+#define C_CAN1_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF1_MCTRL: RXIE Position     */
+#define C_CAN1_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: RXIE Mask         */
+#define C_CAN1_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF1_MCTRL: TXIE Position     */
+#define C_CAN1_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: TXIE Mask         */
+#define C_CAN1_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF1_MCTRL: UMASK Position    */
+#define C_CAN1_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF1_MCTRL: UMASK Mask        */
+#define C_CAN1_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF1_MCTRL: INTPND Position   */
+#define C_CAN1_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF1_MCTRL: INTPND Mask       */
+#define C_CAN1_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF1_MCTRL: MSGLST Position   */
+#define C_CAN1_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF1_MCTRL: MSGLST Mask       */
+#define C_CAN1_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF1_MCTRL: NEWDAT Position   */
+#define C_CAN1_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN1_IF1_DA1  -----------------------------------------
+#define C_CAN1_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF1_DA1: DATA0 Position      */
+#define C_CAN1_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos)                /*!< C_CAN1 IF1_DA1: DATA0 Mask          */
+#define C_CAN1_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF1_DA1: DATA1 Position      */
+#define C_CAN1_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos)                /*!< C_CAN1 IF1_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN1_IF1_DA2  -----------------------------------------
+#define C_CAN1_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF1_DA2: DATA2 Position      */
+#define C_CAN1_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos)                /*!< C_CAN1 IF1_DA2: DATA2 Mask          */
+#define C_CAN1_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF1_DA2: DATA3 Position      */
+#define C_CAN1_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos)                /*!< C_CAN1 IF1_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN1_IF1_DB1  -----------------------------------------
+#define C_CAN1_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF1_DB1: DATA4 Position      */
+#define C_CAN1_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos)                /*!< C_CAN1 IF1_DB1: DATA4 Mask          */
+#define C_CAN1_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF1_DB1: DATA5 Position      */
+#define C_CAN1_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos)                /*!< C_CAN1 IF1_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN1_IF1_DB2  -----------------------------------------
+#define C_CAN1_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF1_DB2: DATA6 Position      */
+#define C_CAN1_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos)                /*!< C_CAN1 IF1_DB2: DATA6 Mask          */
+#define C_CAN1_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF1_DB2: DATA7 Position      */
+#define C_CAN1_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos)                /*!< C_CAN1 IF1_DB2: DATA7 Mask          */
+
+// ------------------------------------  C_CAN1_IF2_CMDREQ  ---------------------------------------
+#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */
+#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask     */
+#define C_CAN1_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF2_CMDREQ: BUSY Position    */
+#define C_CAN1_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF2_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN1_IF2_CMDMSK_W  --------------------------------------
+#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */
+#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask    */
+#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */
+#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask    */
+#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */
+#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask    */
+#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */
+#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position  */
+#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask      */
+#define C_CAN1_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_W: ARB Position   */
+#define C_CAN1_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask       */
+#define C_CAN1_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_W: MASK Position  */
+#define C_CAN1_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask      */
+#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */
+#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask     */
+
+// -----------------------------------  C_CAN1_IF2_CMDMSK_R  --------------------------------------
+#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */
+#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask    */
+#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */
+#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask    */
+#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */
+#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */
+#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position  */
+#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask      */
+#define C_CAN1_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_R: ARB Position   */
+#define C_CAN1_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask       */
+#define C_CAN1_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_R: MASK Position  */
+#define C_CAN1_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask      */
+#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */
+#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask     */
+
+// -------------------------------------  C_CAN1_IF2_MSK1  ----------------------------------------
+#define C_CAN1_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF2_MSK1: MSK15_0 Position   */
+#define C_CAN1_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN1_IF2_MSK2  ----------------------------------------
+#define C_CAN1_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF2_MSK2: MSK28_16 Position  */
+#define C_CAN1_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask      */
+#define C_CAN1_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF2_MSK2: MDIR Position      */
+#define C_CAN1_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF2_MSK2: MDIR Mask          */
+#define C_CAN1_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF2_MSK2: MXTD Position      */
+#define C_CAN1_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF2_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN1_IF2_ARB1  ----------------------------------------
+#define C_CAN1_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF2_ARB1: ID15_0 Position    */
+#define C_CAN1_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF2_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN1_IF2_ARB2  ----------------------------------------
+#define C_CAN1_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF2_ARB2: ID28_16 Position   */
+#define C_CAN1_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF2_ARB2: ID28_16 Mask       */
+#define C_CAN1_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF2_ARB2: DIR Position       */
+#define C_CAN1_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos)                       /*!< C_CAN1 IF2_ARB2: DIR Mask           */
+#define C_CAN1_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF2_ARB2: XTD Position       */
+#define C_CAN1_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos)                       /*!< C_CAN1 IF2_ARB2: XTD Mask           */
+#define C_CAN1_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF2_ARB2: MSGVAL Position    */
+#define C_CAN1_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF2_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN1_IF2_MCTRL  ----------------------------------------
+#define C_CAN1_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position   */
+#define C_CAN1_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask       */
+#define C_CAN1_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF2_MCTRL: EOB Position      */
+#define C_CAN1_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF2_MCTRL: EOB Mask          */
+#define C_CAN1_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF2_MCTRL: TXRQST Position   */
+#define C_CAN1_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF2_MCTRL: TXRQST Mask       */
+#define C_CAN1_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF2_MCTRL: RMTEN Position    */
+#define C_CAN1_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF2_MCTRL: RMTEN Mask        */
+#define C_CAN1_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF2_MCTRL: RXIE Position     */
+#define C_CAN1_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: RXIE Mask         */
+#define C_CAN1_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF2_MCTRL: TXIE Position     */
+#define C_CAN1_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: TXIE Mask         */
+#define C_CAN1_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF2_MCTRL: UMASK Position    */
+#define C_CAN1_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF2_MCTRL: UMASK Mask        */
+#define C_CAN1_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF2_MCTRL: INTPND Position   */
+#define C_CAN1_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF2_MCTRL: INTPND Mask       */
+#define C_CAN1_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF2_MCTRL: MSGLST Position   */
+#define C_CAN1_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF2_MCTRL: MSGLST Mask       */
+#define C_CAN1_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF2_MCTRL: NEWDAT Position   */
+#define C_CAN1_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN1_IF2_DA1  -----------------------------------------
+#define C_CAN1_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF2_DA1: DATA0 Position      */
+#define C_CAN1_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos)                /*!< C_CAN1 IF2_DA1: DATA0 Mask          */
+#define C_CAN1_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF2_DA1: DATA1 Position      */
+#define C_CAN1_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos)                /*!< C_CAN1 IF2_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN1_IF2_DA2  -----------------------------------------
+#define C_CAN1_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF2_DA2: DATA2 Position      */
+#define C_CAN1_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos)                /*!< C_CAN1 IF2_DA2: DATA2 Mask          */
+#define C_CAN1_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF2_DA2: DATA3 Position      */
+#define C_CAN1_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos)                /*!< C_CAN1 IF2_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN1_IF2_DB1  -----------------------------------------
+#define C_CAN1_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF2_DB1: DATA4 Position      */
+#define C_CAN1_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos)                /*!< C_CAN1 IF2_DB1: DATA4 Mask          */
+#define C_CAN1_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF2_DB1: DATA5 Position      */
+#define C_CAN1_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos)                /*!< C_CAN1 IF2_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN1_IF2_DB2  -----------------------------------------
+#define C_CAN1_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF2_DB2: DATA6 Position      */
+#define C_CAN1_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos)                /*!< C_CAN1 IF2_DB2: DATA6 Mask          */
+#define C_CAN1_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF2_DB2: DATA7 Position      */
+#define C_CAN1_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos)                /*!< C_CAN1 IF2_DB2: DATA7 Mask          */
+
+// --------------------------------------  C_CAN1_TXREQ1  -----------------------------------------
+#define C_CAN1_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN1 TXREQ1: TXRQST16_1 Position  */
+#define C_CAN1_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask      */
+
+// --------------------------------------  C_CAN1_TXREQ2  -----------------------------------------
+#define C_CAN1_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */
+#define C_CAN1_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask     */
+
+// ---------------------------------------  C_CAN1_ND1  -------------------------------------------
+#define C_CAN1_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN1 ND1: NEWDAT16_1 Position     */
+#define C_CAN1_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos)               /*!< C_CAN1 ND1: NEWDAT16_1 Mask         */
+
+// ---------------------------------------  C_CAN1_ND2  -------------------------------------------
+#define C_CAN1_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN1 ND2: NEWDAT32_17 Position    */
+#define C_CAN1_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos)              /*!< C_CAN1 ND2: NEWDAT32_17 Mask        */
+
+// ---------------------------------------  C_CAN1_IR1  -------------------------------------------
+#define C_CAN1_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN1 IR1: INTPND16_1 Position     */
+#define C_CAN1_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos)               /*!< C_CAN1 IR1: INTPND16_1 Mask         */
+
+// ---------------------------------------  C_CAN1_IR2  -------------------------------------------
+#define C_CAN1_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN1 IR2: INTPND32_17 Position    */
+#define C_CAN1_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos)              /*!< C_CAN1 IR2: INTPND32_17 Mask        */
+
+// --------------------------------------  C_CAN1_MSGV1  ------------------------------------------
+#define C_CAN1_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN1 MSGV1: MSGVAL16_1 Position   */
+#define C_CAN1_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask       */
+
+// --------------------------------------  C_CAN1_MSGV2  ------------------------------------------
+#define C_CAN1_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN1 MSGV2: MSGVAL32_17 Position  */
+#define C_CAN1_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask      */
+
+// --------------------------------------  C_CAN1_CLKDIV  -----------------------------------------
+#define C_CAN1_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN1 CLKDIV: CLKDIVVAL Position   */
+#define C_CAN1_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                RITIMER Position & Mask                               -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  RITIMER_COMPVAL  ----------------------------------------
+#define RITIMER_COMPVAL_RICOMP_Pos                            0                                                         /*!< RITIMER COMPVAL: RICOMP Position    */
+#define RITIMER_COMPVAL_RICOMP_Msk                            (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos)              /*!< RITIMER COMPVAL: RICOMP Mask        */
+
+// --------------------------------------  RITIMER_MASK  ------------------------------------------
+#define RITIMER_MASK_RIMASK_Pos                               0                                                         /*!< RITIMER MASK: RIMASK Position       */
+#define RITIMER_MASK_RIMASK_Msk                               (0xffffffffUL << RITIMER_MASK_RIMASK_Pos)                 /*!< RITIMER MASK: RIMASK Mask           */
+
+// --------------------------------------  RITIMER_CTRL  ------------------------------------------
+#define RITIMER_CTRL_RITINT_Pos                               0                                                         /*!< RITIMER CTRL: RITINT Position       */
+#define RITIMER_CTRL_RITINT_Msk                               (0x01UL << RITIMER_CTRL_RITINT_Pos)                       /*!< RITIMER CTRL: RITINT Mask           */
+#define RITIMER_CTRL_RITENCLR_Pos                             1                                                         /*!< RITIMER CTRL: RITENCLR Position     */
+#define RITIMER_CTRL_RITENCLR_Msk                             (0x01UL << RITIMER_CTRL_RITENCLR_Pos)                     /*!< RITIMER CTRL: RITENCLR Mask         */
+#define RITIMER_CTRL_RITENBR_Pos                              2                                                         /*!< RITIMER CTRL: RITENBR Position      */
+#define RITIMER_CTRL_RITENBR_Msk                              (0x01UL << RITIMER_CTRL_RITENBR_Pos)                      /*!< RITIMER CTRL: RITENBR Mask          */
+#define RITIMER_CTRL_RITEN_Pos                                3                                                         /*!< RITIMER CTRL: RITEN Position        */
+#define RITIMER_CTRL_RITEN_Msk                                (0x01UL << RITIMER_CTRL_RITEN_Pos)                        /*!< RITIMER CTRL: RITEN Mask            */
+
+// -------------------------------------  RITIMER_COUNTER  ----------------------------------------
+#define RITIMER_COUNTER_RICOUNTER_Pos                         0                                                         /*!< RITIMER COUNTER: RICOUNTER Position */
+#define RITIMER_COUNTER_RICOUNTER_Msk                         (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos)           /*!< RITIMER COUNTER: RICOUNTER Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  QEI Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  QEI_CON  --------------------------------------------
+#define QEI_CON_RESP_Pos                                      0                                                         /*!< QEI CON: RESP Position              */
+#define QEI_CON_RESP_Msk                                      (0x01UL << QEI_CON_RESP_Pos)                              /*!< QEI CON: RESP Mask                  */
+#define QEI_CON_RESPI_Pos                                     1                                                         /*!< QEI CON: RESPI Position             */
+#define QEI_CON_RESPI_Msk                                     (0x01UL << QEI_CON_RESPI_Pos)                             /*!< QEI CON: RESPI Mask                 */
+#define QEI_CON_RESV_Pos                                      2                                                         /*!< QEI CON: RESV Position              */
+#define QEI_CON_RESV_Msk                                      (0x01UL << QEI_CON_RESV_Pos)                              /*!< QEI CON: RESV Mask                  */
+#define QEI_CON_RESI_Pos                                      3                                                         /*!< QEI CON: RESI Position              */
+#define QEI_CON_RESI_Msk                                      (0x01UL << QEI_CON_RESI_Pos)                              /*!< QEI CON: RESI Mask                  */
+
+// ----------------------------------------  QEI_STAT  --------------------------------------------
+#define QEI_STAT_DIR_Pos                                      0                                                         /*!< QEI STAT: DIR Position              */
+#define QEI_STAT_DIR_Msk                                      (0x01UL << QEI_STAT_DIR_Pos)                              /*!< QEI STAT: DIR Mask                  */
+
+// ----------------------------------------  QEI_CONF  --------------------------------------------
+#define QEI_CONF_DIRINV_Pos                                   0                                                         /*!< QEI CONF: DIRINV Position           */
+#define QEI_CONF_DIRINV_Msk                                   (0x01UL << QEI_CONF_DIRINV_Pos)                           /*!< QEI CONF: DIRINV Mask               */
+#define QEI_CONF_SIGMODE_Pos                                  1                                                         /*!< QEI CONF: SIGMODE Position          */
+#define QEI_CONF_SIGMODE_Msk                                  (0x01UL << QEI_CONF_SIGMODE_Pos)                          /*!< QEI CONF: SIGMODE Mask              */
+#define QEI_CONF_CAPMODE_Pos                                  2                                                         /*!< QEI CONF: CAPMODE Position          */
+#define QEI_CONF_CAPMODE_Msk                                  (0x01UL << QEI_CONF_CAPMODE_Pos)                          /*!< QEI CONF: CAPMODE Mask              */
+#define QEI_CONF_INVINX_Pos                                   3                                                         /*!< QEI CONF: INVINX Position           */
+#define QEI_CONF_INVINX_Msk                                   (0x01UL << QEI_CONF_INVINX_Pos)                           /*!< QEI CONF: INVINX Mask               */
+#define QEI_CONF_CRESPI_Pos                                   4                                                         /*!< QEI CONF: CRESPI Position           */
+#define QEI_CONF_CRESPI_Msk                                   (0x01UL << QEI_CONF_CRESPI_Pos)                           /*!< QEI CONF: CRESPI Mask               */
+#define QEI_CONF_INXGATE_Pos                                  16                                                        /*!< QEI CONF: INXGATE Position          */
+#define QEI_CONF_INXGATE_Msk                                  (0x0fUL << QEI_CONF_INXGATE_Pos)                          /*!< QEI CONF: INXGATE Mask              */
+
+// -----------------------------------------  QEI_POS  --------------------------------------------
+#define QEI_POS_POS_Pos                                       0                                                         /*!< QEI POS: POS Position               */
+#define QEI_POS_POS_Msk                                       (0xffffffffUL << QEI_POS_POS_Pos)                         /*!< QEI POS: POS Mask                   */
+
+// ---------------------------------------  QEI_MAXPOS  -------------------------------------------
+#define QEI_MAXPOS_MAXPOS_Pos                                 0                                                         /*!< QEI MAXPOS: MAXPOS Position         */
+#define QEI_MAXPOS_MAXPOS_Msk                                 (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos)                   /*!< QEI MAXPOS: MAXPOS Mask             */
+
+// ---------------------------------------  QEI_CMPOS0  -------------------------------------------
+#define QEI_CMPOS0_PCMP0_Pos                                  0                                                         /*!< QEI CMPOS0: PCMP0 Position          */
+#define QEI_CMPOS0_PCMP0_Msk                                  (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos)                    /*!< QEI CMPOS0: PCMP0 Mask              */
+
+// ---------------------------------------  QEI_CMPOS1  -------------------------------------------
+#define QEI_CMPOS1_PCMP1_Pos                                  0                                                         /*!< QEI CMPOS1: PCMP1 Position          */
+#define QEI_CMPOS1_PCMP1_Msk                                  (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos)                    /*!< QEI CMPOS1: PCMP1 Mask              */
+
+// ---------------------------------------  QEI_CMPOS2  -------------------------------------------
+#define QEI_CMPOS2_PCMP2_Pos                                  0                                                         /*!< QEI CMPOS2: PCMP2 Position          */
+#define QEI_CMPOS2_PCMP2_Msk                                  (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos)                    /*!< QEI CMPOS2: PCMP2 Mask              */
+
+// ---------------------------------------  QEI_INXCNT  -------------------------------------------
+#define QEI_INXCNT_ENCPOS_Pos                                 0                                                         /*!< QEI INXCNT: ENCPOS Position         */
+#define QEI_INXCNT_ENCPOS_Msk                                 (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos)                   /*!< QEI INXCNT: ENCPOS Mask             */
+
+// ---------------------------------------  QEI_INXCMP0  ------------------------------------------
+#define QEI_INXCMP0_ICMP0_Pos                                 0                                                         /*!< QEI INXCMP0: ICMP0 Position         */
+#define QEI_INXCMP0_ICMP0_Msk                                 (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos)                   /*!< QEI INXCMP0: ICMP0 Mask             */
+
+// ----------------------------------------  QEI_LOAD  --------------------------------------------
+#define QEI_LOAD_VELLOAD_Pos                                  0                                                         /*!< QEI LOAD: VELLOAD Position          */
+#define QEI_LOAD_VELLOAD_Msk                                  (0xffffffffUL << QEI_LOAD_VELLOAD_Pos)                    /*!< QEI LOAD: VELLOAD Mask              */
+
+// ----------------------------------------  QEI_TIME  --------------------------------------------
+#define QEI_TIME_VELVAL_Pos                                   0                                                         /*!< QEI TIME: VELVAL Position           */
+#define QEI_TIME_VELVAL_Msk                                   (0xffffffffUL << QEI_TIME_VELVAL_Pos)                     /*!< QEI TIME: VELVAL Mask               */
+
+// -----------------------------------------  QEI_VEL  --------------------------------------------
+#define QEI_VEL_VELPC_Pos                                     0                                                         /*!< QEI VEL: VELPC Position             */
+#define QEI_VEL_VELPC_Msk                                     (0xffffffffUL << QEI_VEL_VELPC_Pos)                       /*!< QEI VEL: VELPC Mask                 */
+
+// -----------------------------------------  QEI_CAP  --------------------------------------------
+#define QEI_CAP_VELCAP_Pos                                    0                                                         /*!< QEI CAP: VELCAP Position            */
+#define QEI_CAP_VELCAP_Msk                                    (0xffffffffUL << QEI_CAP_VELCAP_Pos)                      /*!< QEI CAP: VELCAP Mask                */
+
+// ---------------------------------------  QEI_VELCOMP  ------------------------------------------
+#define QEI_VELCOMP_VELCMP_Pos                                0                                                         /*!< QEI VELCOMP: VELCMP Position        */
+#define QEI_VELCOMP_VELCMP_Msk                                (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos)                  /*!< QEI VELCOMP: VELCMP Mask            */
+
+// --------------------------------------  QEI_FILTERPHA  -----------------------------------------
+#define QEI_FILTERPHA_FILTA_Pos                               0                                                         /*!< QEI FILTERPHA: FILTA Position       */
+#define QEI_FILTERPHA_FILTA_Msk                               (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos)                 /*!< QEI FILTERPHA: FILTA Mask           */
+
+// --------------------------------------  QEI_FILTERPHB  -----------------------------------------
+#define QEI_FILTERPHB_FILTB_Pos                               0                                                         /*!< QEI FILTERPHB: FILTB Position       */
+#define QEI_FILTERPHB_FILTB_Msk                               (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos)                 /*!< QEI FILTERPHB: FILTB Mask           */
+
+// --------------------------------------  QEI_FILTERINX  -----------------------------------------
+#define QEI_FILTERINX_FITLINX_Pos                             0                                                         /*!< QEI FILTERINX: FITLINX Position     */
+#define QEI_FILTERINX_FITLINX_Msk                             (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos)               /*!< QEI FILTERINX: FITLINX Mask         */
+
+// ---------------------------------------  QEI_WINDOW  -------------------------------------------
+#define QEI_WINDOW_WINDOW_Pos                                 0                                                         /*!< QEI WINDOW: WINDOW Position         */
+#define QEI_WINDOW_WINDOW_Msk                                 (0xffffffffUL << QEI_WINDOW_WINDOW_Pos)                   /*!< QEI WINDOW: WINDOW Mask             */
+
+// ---------------------------------------  QEI_INXCMP1  ------------------------------------------
+#define QEI_INXCMP1_ICMP1_Pos                                 0                                                         /*!< QEI INXCMP1: ICMP1 Position         */
+#define QEI_INXCMP1_ICMP1_Msk                                 (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos)                   /*!< QEI INXCMP1: ICMP1 Mask             */
+
+// ---------------------------------------  QEI_INXCMP2  ------------------------------------------
+#define QEI_INXCMP2_ICMP2_Pos                                 0                                                         /*!< QEI INXCMP2: ICMP2 Position         */
+#define QEI_INXCMP2_ICMP2_Msk                                 (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos)                   /*!< QEI INXCMP2: ICMP2 Mask             */
+
+// -----------------------------------------  QEI_IEC  --------------------------------------------
+#define QEI_IEC_INX_EN_Pos                                    0                                                         /*!< QEI IEC: INX_EN Position            */
+#define QEI_IEC_INX_EN_Msk                                    (0x01UL << QEI_IEC_INX_EN_Pos)                            /*!< QEI IEC: INX_EN Mask                */
+#define QEI_IEC_TIM_EN_Pos                                    1                                                         /*!< QEI IEC: TIM_EN Position            */
+#define QEI_IEC_TIM_EN_Msk                                    (0x01UL << QEI_IEC_TIM_EN_Pos)                            /*!< QEI IEC: TIM_EN Mask                */
+#define QEI_IEC_VELC_EN_Pos                                   2                                                         /*!< QEI IEC: VELC_EN Position           */
+#define QEI_IEC_VELC_EN_Msk                                   (0x01UL << QEI_IEC_VELC_EN_Pos)                           /*!< QEI IEC: VELC_EN Mask               */
+#define QEI_IEC_DIR_EN_Pos                                    3                                                         /*!< QEI IEC: DIR_EN Position            */
+#define QEI_IEC_DIR_EN_Msk                                    (0x01UL << QEI_IEC_DIR_EN_Pos)                            /*!< QEI IEC: DIR_EN Mask                */
+#define QEI_IEC_ERR_EN_Pos                                    4                                                         /*!< QEI IEC: ERR_EN Position            */
+#define QEI_IEC_ERR_EN_Msk                                    (0x01UL << QEI_IEC_ERR_EN_Pos)                            /*!< QEI IEC: ERR_EN Mask                */
+#define QEI_IEC_ENCLK_EN_Pos                                  5                                                         /*!< QEI IEC: ENCLK_EN Position          */
+#define QEI_IEC_ENCLK_EN_Msk                                  (0x01UL << QEI_IEC_ENCLK_EN_Pos)                          /*!< QEI IEC: ENCLK_EN Mask              */
+#define QEI_IEC_POS0_Int_Pos                                  6                                                         /*!< QEI IEC: POS0_Int Position          */
+#define QEI_IEC_POS0_Int_Msk                                  (0x01UL << QEI_IEC_POS0_Int_Pos)                          /*!< QEI IEC: POS0_Int Mask              */
+#define QEI_IEC_POS1_Int_Pos                                  7                                                         /*!< QEI IEC: POS1_Int Position          */
+#define QEI_IEC_POS1_Int_Msk                                  (0x01UL << QEI_IEC_POS1_Int_Pos)                          /*!< QEI IEC: POS1_Int Mask              */
+#define QEI_IEC_POS2_Int_Pos                                  8                                                         /*!< QEI IEC: POS2_Int Position          */
+#define QEI_IEC_POS2_Int_Msk                                  (0x01UL << QEI_IEC_POS2_Int_Pos)                          /*!< QEI IEC: POS2_Int Mask              */
+#define QEI_IEC_REV_Int_Pos                                   9                                                         /*!< QEI IEC: REV_Int Position           */
+#define QEI_IEC_REV_Int_Msk                                   (0x01UL << QEI_IEC_REV_Int_Pos)                           /*!< QEI IEC: REV_Int Mask               */
+#define QEI_IEC_POS0REV_Int_Pos                               10                                                        /*!< QEI IEC: POS0REV_Int Position       */
+#define QEI_IEC_POS0REV_Int_Msk                               (0x01UL << QEI_IEC_POS0REV_Int_Pos)                       /*!< QEI IEC: POS0REV_Int Mask           */
+#define QEI_IEC_POS1REV_Int_Pos                               11                                                        /*!< QEI IEC: POS1REV_Int Position       */
+#define QEI_IEC_POS1REV_Int_Msk                               (0x01UL << QEI_IEC_POS1REV_Int_Pos)                       /*!< QEI IEC: POS1REV_Int Mask           */
+#define QEI_IEC_POS2REV_Int_Pos                               12                                                        /*!< QEI IEC: POS2REV_Int Position       */
+#define QEI_IEC_POS2REV_Int_Msk                               (0x01UL << QEI_IEC_POS2REV_Int_Pos)                       /*!< QEI IEC: POS2REV_Int Mask           */
+#define QEI_IEC_REV1_Int_Pos                                  13                                                        /*!< QEI IEC: REV1_Int Position          */
+#define QEI_IEC_REV1_Int_Msk                                  (0x01UL << QEI_IEC_REV1_Int_Pos)                          /*!< QEI IEC: REV1_Int Mask              */
+#define QEI_IEC_REV2_Int_Pos                                  14                                                        /*!< QEI IEC: REV2_Int Position          */
+#define QEI_IEC_REV2_Int_Msk                                  (0x01UL << QEI_IEC_REV2_Int_Pos)                          /*!< QEI IEC: REV2_Int Mask              */
+#define QEI_IEC_MAXPOS_Int_Pos                                15                                                        /*!< QEI IEC: MAXPOS_Int Position        */
+#define QEI_IEC_MAXPOS_Int_Msk                                (0x01UL << QEI_IEC_MAXPOS_Int_Pos)                        /*!< QEI IEC: MAXPOS_Int Mask            */
+
+// -----------------------------------------  QEI_IES  --------------------------------------------
+#define QEI_IES_INX_EN_Pos                                    0                                                         /*!< QEI IES: INX_EN Position            */
+#define QEI_IES_INX_EN_Msk                                    (0x01UL << QEI_IES_INX_EN_Pos)                            /*!< QEI IES: INX_EN Mask                */
+#define QEI_IES_TIM_EN_Pos                                    1                                                         /*!< QEI IES: TIM_EN Position            */
+#define QEI_IES_TIM_EN_Msk                                    (0x01UL << QEI_IES_TIM_EN_Pos)                            /*!< QEI IES: TIM_EN Mask                */
+#define QEI_IES_VELC_EN_Pos                                   2                                                         /*!< QEI IES: VELC_EN Position           */
+#define QEI_IES_VELC_EN_Msk                                   (0x01UL << QEI_IES_VELC_EN_Pos)                           /*!< QEI IES: VELC_EN Mask               */
+#define QEI_IES_DIR_EN_Pos                                    3                                                         /*!< QEI IES: DIR_EN Position            */
+#define QEI_IES_DIR_EN_Msk                                    (0x01UL << QEI_IES_DIR_EN_Pos)                            /*!< QEI IES: DIR_EN Mask                */
+#define QEI_IES_ERR_EN_Pos                                    4                                                         /*!< QEI IES: ERR_EN Position            */
+#define QEI_IES_ERR_EN_Msk                                    (0x01UL << QEI_IES_ERR_EN_Pos)                            /*!< QEI IES: ERR_EN Mask                */
+#define QEI_IES_ENCLK_EN_Pos                                  5                                                         /*!< QEI IES: ENCLK_EN Position          */
+#define QEI_IES_ENCLK_EN_Msk                                  (0x01UL << QEI_IES_ENCLK_EN_Pos)                          /*!< QEI IES: ENCLK_EN Mask              */
+#define QEI_IES_POS0_Int_Pos                                  6                                                         /*!< QEI IES: POS0_Int Position          */
+#define QEI_IES_POS0_Int_Msk                                  (0x01UL << QEI_IES_POS0_Int_Pos)                          /*!< QEI IES: POS0_Int Mask              */
+#define QEI_IES_POS1_Int_Pos                                  7                                                         /*!< QEI IES: POS1_Int Position          */
+#define QEI_IES_POS1_Int_Msk                                  (0x01UL << QEI_IES_POS1_Int_Pos)                          /*!< QEI IES: POS1_Int Mask              */
+#define QEI_IES_POS2_Int_Pos                                  8                                                         /*!< QEI IES: POS2_Int Position          */
+#define QEI_IES_POS2_Int_Msk                                  (0x01UL << QEI_IES_POS2_Int_Pos)                          /*!< QEI IES: POS2_Int Mask              */
+#define QEI_IES_REV_Int_Pos                                   9                                                         /*!< QEI IES: REV_Int Position           */
+#define QEI_IES_REV_Int_Msk                                   (0x01UL << QEI_IES_REV_Int_Pos)                           /*!< QEI IES: REV_Int Mask               */
+#define QEI_IES_POS0REV_Int_Pos                               10                                                        /*!< QEI IES: POS0REV_Int Position       */
+#define QEI_IES_POS0REV_Int_Msk                               (0x01UL << QEI_IES_POS0REV_Int_Pos)                       /*!< QEI IES: POS0REV_Int Mask           */
+#define QEI_IES_POS1REV_Int_Pos                               11                                                        /*!< QEI IES: POS1REV_Int Position       */
+#define QEI_IES_POS1REV_Int_Msk                               (0x01UL << QEI_IES_POS1REV_Int_Pos)                       /*!< QEI IES: POS1REV_Int Mask           */
+#define QEI_IES_POS2REV_Int_Pos                               12                                                        /*!< QEI IES: POS2REV_Int Position       */
+#define QEI_IES_POS2REV_Int_Msk                               (0x01UL << QEI_IES_POS2REV_Int_Pos)                       /*!< QEI IES: POS2REV_Int Mask           */
+#define QEI_IES_REV1_Int_Pos                                  13                                                        /*!< QEI IES: REV1_Int Position          */
+#define QEI_IES_REV1_Int_Msk                                  (0x01UL << QEI_IES_REV1_Int_Pos)                          /*!< QEI IES: REV1_Int Mask              */
+#define QEI_IES_REV2_Int_Pos                                  14                                                        /*!< QEI IES: REV2_Int Position          */
+#define QEI_IES_REV2_Int_Msk                                  (0x01UL << QEI_IES_REV2_Int_Pos)                          /*!< QEI IES: REV2_Int Mask              */
+#define QEI_IES_MAXPOS_Int_Pos                                15                                                        /*!< QEI IES: MAXPOS_Int Position        */
+#define QEI_IES_MAXPOS_Int_Msk                                (0x01UL << QEI_IES_MAXPOS_Int_Pos)                        /*!< QEI IES: MAXPOS_Int Mask            */
+
+// ---------------------------------------  QEI_INTSTAT  ------------------------------------------
+#define QEI_INTSTAT_INX_Int_Pos                               0                                                         /*!< QEI INTSTAT: INX_Int Position       */
+#define QEI_INTSTAT_INX_Int_Msk                               (0x01UL << QEI_INTSTAT_INX_Int_Pos)                       /*!< QEI INTSTAT: INX_Int Mask           */
+#define QEI_INTSTAT_TIM_Int_Pos                               1                                                         /*!< QEI INTSTAT: TIM_Int Position       */
+#define QEI_INTSTAT_TIM_Int_Msk                               (0x01UL << QEI_INTSTAT_TIM_Int_Pos)                       /*!< QEI INTSTAT: TIM_Int Mask           */
+#define QEI_INTSTAT_VELC_Int_Pos                              2                                                         /*!< QEI INTSTAT: VELC_Int Position      */
+#define QEI_INTSTAT_VELC_Int_Msk                              (0x01UL << QEI_INTSTAT_VELC_Int_Pos)                      /*!< QEI INTSTAT: VELC_Int Mask          */
+#define QEI_INTSTAT_DIR_Int_Pos                               3                                                         /*!< QEI INTSTAT: DIR_Int Position       */
+#define QEI_INTSTAT_DIR_Int_Msk                               (0x01UL << QEI_INTSTAT_DIR_Int_Pos)                       /*!< QEI INTSTAT: DIR_Int Mask           */
+#define QEI_INTSTAT_ERR_Int_Pos                               4                                                         /*!< QEI INTSTAT: ERR_Int Position       */
+#define QEI_INTSTAT_ERR_Int_Msk                               (0x01UL << QEI_INTSTAT_ERR_Int_Pos)                       /*!< QEI INTSTAT: ERR_Int Mask           */
+#define QEI_INTSTAT_ENCLK_Int_Pos                             5                                                         /*!< QEI INTSTAT: ENCLK_Int Position     */
+#define QEI_INTSTAT_ENCLK_Int_Msk                             (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos)                     /*!< QEI INTSTAT: ENCLK_Int Mask         */
+#define QEI_INTSTAT_POS0_Int_Pos                              6                                                         /*!< QEI INTSTAT: POS0_Int Position      */
+#define QEI_INTSTAT_POS0_Int_Msk                              (0x01UL << QEI_INTSTAT_POS0_Int_Pos)                      /*!< QEI INTSTAT: POS0_Int Mask          */
+#define QEI_INTSTAT_POS1_Int_Pos                              7                                                         /*!< QEI INTSTAT: POS1_Int Position      */
+#define QEI_INTSTAT_POS1_Int_Msk                              (0x01UL << QEI_INTSTAT_POS1_Int_Pos)                      /*!< QEI INTSTAT: POS1_Int Mask          */
+#define QEI_INTSTAT_POS2_Int_Pos                              8                                                         /*!< QEI INTSTAT: POS2_Int Position      */
+#define QEI_INTSTAT_POS2_Int_Msk                              (0x01UL << QEI_INTSTAT_POS2_Int_Pos)                      /*!< QEI INTSTAT: POS2_Int Mask          */
+#define QEI_INTSTAT_REV_Int_Pos                               9                                                         /*!< QEI INTSTAT: REV_Int Position       */
+#define QEI_INTSTAT_REV_Int_Msk                               (0x01UL << QEI_INTSTAT_REV_Int_Pos)                       /*!< QEI INTSTAT: REV_Int Mask           */
+#define QEI_INTSTAT_POS0REV_Int_Pos                           10                                                        /*!< QEI INTSTAT: POS0REV_Int Position   */
+#define QEI_INTSTAT_POS0REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos)                   /*!< QEI INTSTAT: POS0REV_Int Mask       */
+#define QEI_INTSTAT_POS1REV_Int_Pos                           11                                                        /*!< QEI INTSTAT: POS1REV_Int Position   */
+#define QEI_INTSTAT_POS1REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos)                   /*!< QEI INTSTAT: POS1REV_Int Mask       */
+#define QEI_INTSTAT_POS2REV_Int_Pos                           12                                                        /*!< QEI INTSTAT: POS2REV_Int Position   */
+#define QEI_INTSTAT_POS2REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos)                   /*!< QEI INTSTAT: POS2REV_Int Mask       */
+#define QEI_INTSTAT_REV1_Int_Pos                              13                                                        /*!< QEI INTSTAT: REV1_Int Position      */
+#define QEI_INTSTAT_REV1_Int_Msk                              (0x01UL << QEI_INTSTAT_REV1_Int_Pos)                      /*!< QEI INTSTAT: REV1_Int Mask          */
+#define QEI_INTSTAT_REV2_Int_Pos                              14                                                        /*!< QEI INTSTAT: REV2_Int Position      */
+#define QEI_INTSTAT_REV2_Int_Msk                              (0x01UL << QEI_INTSTAT_REV2_Int_Pos)                      /*!< QEI INTSTAT: REV2_Int Mask          */
+#define QEI_INTSTAT_MAXPOS_Int_Pos                            15                                                        /*!< QEI INTSTAT: MAXPOS_Int Position    */
+#define QEI_INTSTAT_MAXPOS_Int_Msk                            (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos)                    /*!< QEI INTSTAT: MAXPOS_Int Mask        */
+
+// -----------------------------------------  QEI_IE  ---------------------------------------------
+#define QEI_IE_INX_Int_Pos                                    0                                                         /*!< QEI IE: INX_Int Position            */
+#define QEI_IE_INX_Int_Msk                                    (0x01UL << QEI_IE_INX_Int_Pos)                            /*!< QEI IE: INX_Int Mask                */
+#define QEI_IE_TIM_Int_Pos                                    1                                                         /*!< QEI IE: TIM_Int Position            */
+#define QEI_IE_TIM_Int_Msk                                    (0x01UL << QEI_IE_TIM_Int_Pos)                            /*!< QEI IE: TIM_Int Mask                */
+#define QEI_IE_VELC_Int_Pos                                   2                                                         /*!< QEI IE: VELC_Int Position           */
+#define QEI_IE_VELC_Int_Msk                                   (0x01UL << QEI_IE_VELC_Int_Pos)                           /*!< QEI IE: VELC_Int Mask               */
+#define QEI_IE_DIR_Int_Pos                                    3                                                         /*!< QEI IE: DIR_Int Position            */
+#define QEI_IE_DIR_Int_Msk                                    (0x01UL << QEI_IE_DIR_Int_Pos)                            /*!< QEI IE: DIR_Int Mask                */
+#define QEI_IE_ERR_Int_Pos                                    4                                                         /*!< QEI IE: ERR_Int Position            */
+#define QEI_IE_ERR_Int_Msk                                    (0x01UL << QEI_IE_ERR_Int_Pos)                            /*!< QEI IE: ERR_Int Mask                */
+#define QEI_IE_ENCLK_Int_Pos                                  5                                                         /*!< QEI IE: ENCLK_Int Position          */
+#define QEI_IE_ENCLK_Int_Msk                                  (0x01UL << QEI_IE_ENCLK_Int_Pos)                          /*!< QEI IE: ENCLK_Int Mask              */
+#define QEI_IE_POS0_Int_Pos                                   6                                                         /*!< QEI IE: POS0_Int Position           */
+#define QEI_IE_POS0_Int_Msk                                   (0x01UL << QEI_IE_POS0_Int_Pos)                           /*!< QEI IE: POS0_Int Mask               */
+#define QEI_IE_POS1_Int_Pos                                   7                                                         /*!< QEI IE: POS1_Int Position           */
+#define QEI_IE_POS1_Int_Msk                                   (0x01UL << QEI_IE_POS1_Int_Pos)                           /*!< QEI IE: POS1_Int Mask               */
+#define QEI_IE_POS2_Int_Pos                                   8                                                         /*!< QEI IE: POS2_Int Position           */
+#define QEI_IE_POS2_Int_Msk                                   (0x01UL << QEI_IE_POS2_Int_Pos)                           /*!< QEI IE: POS2_Int Mask               */
+#define QEI_IE_REV_Int_Pos                                    9                                                         /*!< QEI IE: REV_Int Position            */
+#define QEI_IE_REV_Int_Msk                                    (0x01UL << QEI_IE_REV_Int_Pos)                            /*!< QEI IE: REV_Int Mask                */
+#define QEI_IE_POS0REV_Int_Pos                                10                                                        /*!< QEI IE: POS0REV_Int Position        */
+#define QEI_IE_POS0REV_Int_Msk                                (0x01UL << QEI_IE_POS0REV_Int_Pos)                        /*!< QEI IE: POS0REV_Int Mask            */
+#define QEI_IE_POS1REV_Int_Pos                                11                                                        /*!< QEI IE: POS1REV_Int Position        */
+#define QEI_IE_POS1REV_Int_Msk                                (0x01UL << QEI_IE_POS1REV_Int_Pos)                        /*!< QEI IE: POS1REV_Int Mask            */
+#define QEI_IE_POS2REV_Int_Pos                                12                                                        /*!< QEI IE: POS2REV_Int Position        */
+#define QEI_IE_POS2REV_Int_Msk                                (0x01UL << QEI_IE_POS2REV_Int_Pos)                        /*!< QEI IE: POS2REV_Int Mask            */
+#define QEI_IE_REV1_Int_Pos                                   13                                                        /*!< QEI IE: REV1_Int Position           */
+#define QEI_IE_REV1_Int_Msk                                   (0x01UL << QEI_IE_REV1_Int_Pos)                           /*!< QEI IE: REV1_Int Mask               */
+#define QEI_IE_REV2_Int_Pos                                   14                                                        /*!< QEI IE: REV2_Int Position           */
+#define QEI_IE_REV2_Int_Msk                                   (0x01UL << QEI_IE_REV2_Int_Pos)                           /*!< QEI IE: REV2_Int Mask               */
+#define QEI_IE_MAXPOS_Int_Pos                                 15                                                        /*!< QEI IE: MAXPOS_Int Position         */
+#define QEI_IE_MAXPOS_Int_Msk                                 (0x01UL << QEI_IE_MAXPOS_Int_Pos)                         /*!< QEI IE: MAXPOS_Int Mask             */
+
+// -----------------------------------------  QEI_CLR  --------------------------------------------
+#define QEI_CLR_INX_Int_Pos                                   0                                                         /*!< QEI CLR: INX_Int Position           */
+#define QEI_CLR_INX_Int_Msk                                   (0x01UL << QEI_CLR_INX_Int_Pos)                           /*!< QEI CLR: INX_Int Mask               */
+#define QEI_CLR_TIM_Int_Pos                                   1                                                         /*!< QEI CLR: TIM_Int Position           */
+#define QEI_CLR_TIM_Int_Msk                                   (0x01UL << QEI_CLR_TIM_Int_Pos)                           /*!< QEI CLR: TIM_Int Mask               */
+#define QEI_CLR_VELC_Int_Pos                                  2                                                         /*!< QEI CLR: VELC_Int Position          */
+#define QEI_CLR_VELC_Int_Msk                                  (0x01UL << QEI_CLR_VELC_Int_Pos)                          /*!< QEI CLR: VELC_Int Mask              */
+#define QEI_CLR_DIR_Int_Pos                                   3                                                         /*!< QEI CLR: DIR_Int Position           */
+#define QEI_CLR_DIR_Int_Msk                                   (0x01UL << QEI_CLR_DIR_Int_Pos)                           /*!< QEI CLR: DIR_Int Mask               */
+#define QEI_CLR_ERR_Int_Pos                                   4                                                         /*!< QEI CLR: ERR_Int Position           */
+#define QEI_CLR_ERR_Int_Msk                                   (0x01UL << QEI_CLR_ERR_Int_Pos)                           /*!< QEI CLR: ERR_Int Mask               */
+#define QEI_CLR_ENCLK_Int_Pos                                 5                                                         /*!< QEI CLR: ENCLK_Int Position         */
+#define QEI_CLR_ENCLK_Int_Msk                                 (0x01UL << QEI_CLR_ENCLK_Int_Pos)                         /*!< QEI CLR: ENCLK_Int Mask             */
+#define QEI_CLR_POS0_Int_Pos                                  6                                                         /*!< QEI CLR: POS0_Int Position          */
+#define QEI_CLR_POS0_Int_Msk                                  (0x01UL << QEI_CLR_POS0_Int_Pos)                          /*!< QEI CLR: POS0_Int Mask              */
+#define QEI_CLR_POS1_Int_Pos                                  7                                                         /*!< QEI CLR: POS1_Int Position          */
+#define QEI_CLR_POS1_Int_Msk                                  (0x01UL << QEI_CLR_POS1_Int_Pos)                          /*!< QEI CLR: POS1_Int Mask              */
+#define QEI_CLR_POS2_Int_Pos                                  8                                                         /*!< QEI CLR: POS2_Int Position          */
+#define QEI_CLR_POS2_Int_Msk                                  (0x01UL << QEI_CLR_POS2_Int_Pos)                          /*!< QEI CLR: POS2_Int Mask              */
+#define QEI_CLR_REV_Int_Pos                                   9                                                         /*!< QEI CLR: REV_Int Position           */
+#define QEI_CLR_REV_Int_Msk                                   (0x01UL << QEI_CLR_REV_Int_Pos)                           /*!< QEI CLR: REV_Int Mask               */
+#define QEI_CLR_POS0REV_Int_Pos                               10                                                        /*!< QEI CLR: POS0REV_Int Position       */
+#define QEI_CLR_POS0REV_Int_Msk                               (0x01UL << QEI_CLR_POS0REV_Int_Pos)                       /*!< QEI CLR: POS0REV_Int Mask           */
+#define QEI_CLR_POS1REV_Int_Pos                               11                                                        /*!< QEI CLR: POS1REV_Int Position       */
+#define QEI_CLR_POS1REV_Int_Msk                               (0x01UL << QEI_CLR_POS1REV_Int_Pos)                       /*!< QEI CLR: POS1REV_Int Mask           */
+#define QEI_CLR_REV1_Int_Pos                                  13                                                        /*!< QEI CLR: REV1_Int Position          */
+#define QEI_CLR_REV1_Int_Msk                                  (0x01UL << QEI_CLR_REV1_Int_Pos)                          /*!< QEI CLR: REV1_Int Mask              */
+#define QEI_CLR_REV2_Int_Pos                                  14                                                        /*!< QEI CLR: REV2_Int Position          */
+#define QEI_CLR_REV2_Int_Msk                                  (0x01UL << QEI_CLR_REV2_Int_Pos)                          /*!< QEI CLR: REV2_Int Mask              */
+#define QEI_CLR_MAXPOS_Int_Pos                                15                                                        /*!< QEI CLR: MAXPOS_Int Position        */
+#define QEI_CLR_MAXPOS_Int_Msk                                (0x01UL << QEI_CLR_MAXPOS_Int_Pos)                        /*!< QEI CLR: MAXPOS_Int Mask            */
+
+// -----------------------------------------  QEI_SET  --------------------------------------------
+#define QEI_SET_INX_Int_Pos                                   0                                                         /*!< QEI SET: INX_Int Position           */
+#define QEI_SET_INX_Int_Msk                                   (0x01UL << QEI_SET_INX_Int_Pos)                           /*!< QEI SET: INX_Int Mask               */
+#define QEI_SET_TIM_Int_Pos                                   1                                                         /*!< QEI SET: TIM_Int Position           */
+#define QEI_SET_TIM_Int_Msk                                   (0x01UL << QEI_SET_TIM_Int_Pos)                           /*!< QEI SET: TIM_Int Mask               */
+#define QEI_SET_VELC_Int_Pos                                  2                                                         /*!< QEI SET: VELC_Int Position          */
+#define QEI_SET_VELC_Int_Msk                                  (0x01UL << QEI_SET_VELC_Int_Pos)                          /*!< QEI SET: VELC_Int Mask              */
+#define QEI_SET_DIR_Int_Pos                                   3                                                         /*!< QEI SET: DIR_Int Position           */
+#define QEI_SET_DIR_Int_Msk                                   (0x01UL << QEI_SET_DIR_Int_Pos)                           /*!< QEI SET: DIR_Int Mask               */
+#define QEI_SET_ERR_Int_Pos                                   4                                                         /*!< QEI SET: ERR_Int Position           */
+#define QEI_SET_ERR_Int_Msk                                   (0x01UL << QEI_SET_ERR_Int_Pos)                           /*!< QEI SET: ERR_Int Mask               */
+#define QEI_SET_ENCLK_Int_Pos                                 5                                                         /*!< QEI SET: ENCLK_Int Position         */
+#define QEI_SET_ENCLK_Int_Msk                                 (0x01UL << QEI_SET_ENCLK_Int_Pos)                         /*!< QEI SET: ENCLK_Int Mask             */
+#define QEI_SET_POS0_Int_Pos                                  6                                                         /*!< QEI SET: POS0_Int Position          */
+#define QEI_SET_POS0_Int_Msk                                  (0x01UL << QEI_SET_POS0_Int_Pos)                          /*!< QEI SET: POS0_Int Mask              */
+#define QEI_SET_POS1_Int_Pos                                  7                                                         /*!< QEI SET: POS1_Int Position          */
+#define QEI_SET_POS1_Int_Msk                                  (0x01UL << QEI_SET_POS1_Int_Pos)                          /*!< QEI SET: POS1_Int Mask              */
+#define QEI_SET_POS2_Int_Pos                                  8                                                         /*!< QEI SET: POS2_Int Position          */
+#define QEI_SET_POS2_Int_Msk                                  (0x01UL << QEI_SET_POS2_Int_Pos)                          /*!< QEI SET: POS2_Int Mask              */
+#define QEI_SET_REV_Int_Pos                                   9                                                         /*!< QEI SET: REV_Int Position           */
+#define QEI_SET_REV_Int_Msk                                   (0x01UL << QEI_SET_REV_Int_Pos)                           /*!< QEI SET: REV_Int Mask               */
+#define QEI_SET_POS0REV_Int_Pos                               10                                                        /*!< QEI SET: POS0REV_Int Position       */
+#define QEI_SET_POS0REV_Int_Msk                               (0x01UL << QEI_SET_POS0REV_Int_Pos)                       /*!< QEI SET: POS0REV_Int Mask           */
+#define QEI_SET_POS1REV_Int_Pos                               11                                                        /*!< QEI SET: POS1REV_Int Position       */
+#define QEI_SET_POS1REV_Int_Msk                               (0x01UL << QEI_SET_POS1REV_Int_Pos)                       /*!< QEI SET: POS1REV_Int Mask           */
+#define QEI_SET_POS2REV_Int_Pos                               12                                                        /*!< QEI SET: POS2REV_Int Position       */
+#define QEI_SET_POS2REV_Int_Msk                               (0x01UL << QEI_SET_POS2REV_Int_Pos)                       /*!< QEI SET: POS2REV_Int Mask           */
+#define QEI_SET_REV1_Int_Pos                                  13                                                        /*!< QEI SET: REV1_Int Position          */
+#define QEI_SET_REV1_Int_Msk                                  (0x01UL << QEI_SET_REV1_Int_Pos)                          /*!< QEI SET: REV1_Int Mask              */
+#define QEI_SET_REV2_Int_Pos                                  14                                                        /*!< QEI SET: REV2_Int Position          */
+#define QEI_SET_REV2_Int_Msk                                  (0x01UL << QEI_SET_REV2_Int_Pos)                          /*!< QEI SET: REV2_Int Mask              */
+#define QEI_SET_MAXPOS_Int_Pos                                15                                                        /*!< QEI SET: MAXPOS_Int Position        */
+#define QEI_SET_MAXPOS_Int_Msk                                (0x01UL << QEI_SET_MAXPOS_Int_Pos)                        /*!< QEI SET: MAXPOS_Int Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 GIMA Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  GIMA_CAP0_0_IN  -----------------------------------------
+#define GIMA_CAP0_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_0_IN: INV Position        */
+#define GIMA_CAP0_0_IN_INV_Msk                                (0x01UL << GIMA_CAP0_0_IN_INV_Pos)                        /*!< GIMA CAP0_0_IN: INV Mask            */
+#define GIMA_CAP0_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_0_IN: EDGE Position       */
+#define GIMA_CAP0_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos)                       /*!< GIMA CAP0_0_IN: EDGE Mask           */
+#define GIMA_CAP0_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_0_IN: SYNCH Position      */
+#define GIMA_CAP0_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos)                      /*!< GIMA CAP0_0_IN: SYNCH Mask          */
+#define GIMA_CAP0_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_0_IN: PULSE Position      */
+#define GIMA_CAP0_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos)                      /*!< GIMA CAP0_0_IN: PULSE Mask          */
+#define GIMA_CAP0_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_0_IN: SELECT Position     */
+#define GIMA_CAP0_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos)                     /*!< GIMA CAP0_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP0_1_IN  -----------------------------------------
+#define GIMA_CAP0_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_1_IN: INV Position        */
+#define GIMA_CAP0_1_IN_INV_Msk                                (0x01UL << GIMA_CAP0_1_IN_INV_Pos)                        /*!< GIMA CAP0_1_IN: INV Mask            */
+#define GIMA_CAP0_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_1_IN: EDGE Position       */
+#define GIMA_CAP0_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos)                       /*!< GIMA CAP0_1_IN: EDGE Mask           */
+#define GIMA_CAP0_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_1_IN: SYNCH Position      */
+#define GIMA_CAP0_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos)                      /*!< GIMA CAP0_1_IN: SYNCH Mask          */
+#define GIMA_CAP0_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_1_IN: PULSE Position      */
+#define GIMA_CAP0_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos)                      /*!< GIMA CAP0_1_IN: PULSE Mask          */
+#define GIMA_CAP0_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_1_IN: SELECT Position     */
+#define GIMA_CAP0_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos)                     /*!< GIMA CAP0_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP0_2_IN  -----------------------------------------
+#define GIMA_CAP0_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_2_IN: INV Position        */
+#define GIMA_CAP0_2_IN_INV_Msk                                (0x01UL << GIMA_CAP0_2_IN_INV_Pos)                        /*!< GIMA CAP0_2_IN: INV Mask            */
+#define GIMA_CAP0_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_2_IN: EDGE Position       */
+#define GIMA_CAP0_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos)                       /*!< GIMA CAP0_2_IN: EDGE Mask           */
+#define GIMA_CAP0_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_2_IN: SYNCH Position      */
+#define GIMA_CAP0_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos)                      /*!< GIMA CAP0_2_IN: SYNCH Mask          */
+#define GIMA_CAP0_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_2_IN: PULSE Position      */
+#define GIMA_CAP0_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos)                      /*!< GIMA CAP0_2_IN: PULSE Mask          */
+#define GIMA_CAP0_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_2_IN: SELECT Position     */
+#define GIMA_CAP0_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos)                     /*!< GIMA CAP0_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP0_3_IN  -----------------------------------------
+#define GIMA_CAP0_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_3_IN: INV Position        */
+#define GIMA_CAP0_3_IN_INV_Msk                                (0x01UL << GIMA_CAP0_3_IN_INV_Pos)                        /*!< GIMA CAP0_3_IN: INV Mask            */
+#define GIMA_CAP0_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_3_IN: EDGE Position       */
+#define GIMA_CAP0_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos)                       /*!< GIMA CAP0_3_IN: EDGE Mask           */
+#define GIMA_CAP0_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_3_IN: SYNCH Position      */
+#define GIMA_CAP0_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos)                      /*!< GIMA CAP0_3_IN: SYNCH Mask          */
+#define GIMA_CAP0_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_3_IN: PULSE Position      */
+#define GIMA_CAP0_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos)                      /*!< GIMA CAP0_3_IN: PULSE Mask          */
+#define GIMA_CAP0_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_3_IN: SELECT Position     */
+#define GIMA_CAP0_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos)                     /*!< GIMA CAP0_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_0_IN  -----------------------------------------
+#define GIMA_CAP1_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_0_IN: INV Position        */
+#define GIMA_CAP1_0_IN_INV_Msk                                (0x01UL << GIMA_CAP1_0_IN_INV_Pos)                        /*!< GIMA CAP1_0_IN: INV Mask            */
+#define GIMA_CAP1_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_0_IN: EDGE Position       */
+#define GIMA_CAP1_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos)                       /*!< GIMA CAP1_0_IN: EDGE Mask           */
+#define GIMA_CAP1_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_0_IN: SYNCH Position      */
+#define GIMA_CAP1_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos)                      /*!< GIMA CAP1_0_IN: SYNCH Mask          */
+#define GIMA_CAP1_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_0_IN: PULSE Position      */
+#define GIMA_CAP1_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos)                      /*!< GIMA CAP1_0_IN: PULSE Mask          */
+#define GIMA_CAP1_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_0_IN: SELECT Position     */
+#define GIMA_CAP1_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos)                     /*!< GIMA CAP1_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_1_IN  -----------------------------------------
+#define GIMA_CAP1_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_1_IN: INV Position        */
+#define GIMA_CAP1_1_IN_INV_Msk                                (0x01UL << GIMA_CAP1_1_IN_INV_Pos)                        /*!< GIMA CAP1_1_IN: INV Mask            */
+#define GIMA_CAP1_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_1_IN: EDGE Position       */
+#define GIMA_CAP1_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos)                       /*!< GIMA CAP1_1_IN: EDGE Mask           */
+#define GIMA_CAP1_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_1_IN: SYNCH Position      */
+#define GIMA_CAP1_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos)                      /*!< GIMA CAP1_1_IN: SYNCH Mask          */
+#define GIMA_CAP1_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_1_IN: PULSE Position      */
+#define GIMA_CAP1_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos)                      /*!< GIMA CAP1_1_IN: PULSE Mask          */
+#define GIMA_CAP1_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_1_IN: SELECT Position     */
+#define GIMA_CAP1_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos)                     /*!< GIMA CAP1_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_2_IN  -----------------------------------------
+#define GIMA_CAP1_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_2_IN: INV Position        */
+#define GIMA_CAP1_2_IN_INV_Msk                                (0x01UL << GIMA_CAP1_2_IN_INV_Pos)                        /*!< GIMA CAP1_2_IN: INV Mask            */
+#define GIMA_CAP1_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_2_IN: EDGE Position       */
+#define GIMA_CAP1_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos)                       /*!< GIMA CAP1_2_IN: EDGE Mask           */
+#define GIMA_CAP1_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_2_IN: SYNCH Position      */
+#define GIMA_CAP1_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos)                      /*!< GIMA CAP1_2_IN: SYNCH Mask          */
+#define GIMA_CAP1_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_2_IN: PULSE Position      */
+#define GIMA_CAP1_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos)                      /*!< GIMA CAP1_2_IN: PULSE Mask          */
+#define GIMA_CAP1_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_2_IN: SELECT Position     */
+#define GIMA_CAP1_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos)                     /*!< GIMA CAP1_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_3_IN  -----------------------------------------
+#define GIMA_CAP1_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_3_IN: INV Position        */
+#define GIMA_CAP1_3_IN_INV_Msk                                (0x01UL << GIMA_CAP1_3_IN_INV_Pos)                        /*!< GIMA CAP1_3_IN: INV Mask            */
+#define GIMA_CAP1_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_3_IN: EDGE Position       */
+#define GIMA_CAP1_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos)                       /*!< GIMA CAP1_3_IN: EDGE Mask           */
+#define GIMA_CAP1_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_3_IN: SYNCH Position      */
+#define GIMA_CAP1_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos)                      /*!< GIMA CAP1_3_IN: SYNCH Mask          */
+#define GIMA_CAP1_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_3_IN: PULSE Position      */
+#define GIMA_CAP1_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos)                      /*!< GIMA CAP1_3_IN: PULSE Mask          */
+#define GIMA_CAP1_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_3_IN: SELECT Position     */
+#define GIMA_CAP1_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos)                     /*!< GIMA CAP1_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_0_IN  -----------------------------------------
+#define GIMA_CAP2_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_0_IN: INV Position        */
+#define GIMA_CAP2_0_IN_INV_Msk                                (0x01UL << GIMA_CAP2_0_IN_INV_Pos)                        /*!< GIMA CAP2_0_IN: INV Mask            */
+#define GIMA_CAP2_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_0_IN: EDGE Position       */
+#define GIMA_CAP2_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos)                       /*!< GIMA CAP2_0_IN: EDGE Mask           */
+#define GIMA_CAP2_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_0_IN: SYNCH Position      */
+#define GIMA_CAP2_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos)                      /*!< GIMA CAP2_0_IN: SYNCH Mask          */
+#define GIMA_CAP2_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_0_IN: PULSE Position      */
+#define GIMA_CAP2_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos)                      /*!< GIMA CAP2_0_IN: PULSE Mask          */
+#define GIMA_CAP2_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_0_IN: SELECT Position     */
+#define GIMA_CAP2_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos)                     /*!< GIMA CAP2_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_1_IN  -----------------------------------------
+#define GIMA_CAP2_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_1_IN: INV Position        */
+#define GIMA_CAP2_1_IN_INV_Msk                                (0x01UL << GIMA_CAP2_1_IN_INV_Pos)                        /*!< GIMA CAP2_1_IN: INV Mask            */
+#define GIMA_CAP2_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_1_IN: EDGE Position       */
+#define GIMA_CAP2_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos)                       /*!< GIMA CAP2_1_IN: EDGE Mask           */
+#define GIMA_CAP2_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_1_IN: SYNCH Position      */
+#define GIMA_CAP2_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos)                      /*!< GIMA CAP2_1_IN: SYNCH Mask          */
+#define GIMA_CAP2_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_1_IN: PULSE Position      */
+#define GIMA_CAP2_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos)                      /*!< GIMA CAP2_1_IN: PULSE Mask          */
+#define GIMA_CAP2_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_1_IN: SELECT Position     */
+#define GIMA_CAP2_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos)                     /*!< GIMA CAP2_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_2_IN  -----------------------------------------
+#define GIMA_CAP2_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_2_IN: INV Position        */
+#define GIMA_CAP2_2_IN_INV_Msk                                (0x01UL << GIMA_CAP2_2_IN_INV_Pos)                        /*!< GIMA CAP2_2_IN: INV Mask            */
+#define GIMA_CAP2_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_2_IN: EDGE Position       */
+#define GIMA_CAP2_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos)                       /*!< GIMA CAP2_2_IN: EDGE Mask           */
+#define GIMA_CAP2_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_2_IN: SYNCH Position      */
+#define GIMA_CAP2_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos)                      /*!< GIMA CAP2_2_IN: SYNCH Mask          */
+#define GIMA_CAP2_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_2_IN: PULSE Position      */
+#define GIMA_CAP2_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos)                      /*!< GIMA CAP2_2_IN: PULSE Mask          */
+#define GIMA_CAP2_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_2_IN: SELECT Position     */
+#define GIMA_CAP2_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos)                     /*!< GIMA CAP2_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_3_IN  -----------------------------------------
+#define GIMA_CAP2_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_3_IN: INV Position        */
+#define GIMA_CAP2_3_IN_INV_Msk                                (0x01UL << GIMA_CAP2_3_IN_INV_Pos)                        /*!< GIMA CAP2_3_IN: INV Mask            */
+#define GIMA_CAP2_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_3_IN: EDGE Position       */
+#define GIMA_CAP2_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos)                       /*!< GIMA CAP2_3_IN: EDGE Mask           */
+#define GIMA_CAP2_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_3_IN: SYNCH Position      */
+#define GIMA_CAP2_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos)                      /*!< GIMA CAP2_3_IN: SYNCH Mask          */
+#define GIMA_CAP2_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_3_IN: PULSE Position      */
+#define GIMA_CAP2_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos)                      /*!< GIMA CAP2_3_IN: PULSE Mask          */
+#define GIMA_CAP2_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_3_IN: SELECT Position     */
+#define GIMA_CAP2_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos)                     /*!< GIMA CAP2_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_0_IN  -----------------------------------------
+#define GIMA_CAP3_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_0_IN: INV Position        */
+#define GIMA_CAP3_0_IN_INV_Msk                                (0x01UL << GIMA_CAP3_0_IN_INV_Pos)                        /*!< GIMA CAP3_0_IN: INV Mask            */
+#define GIMA_CAP3_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_0_IN: EDGE Position       */
+#define GIMA_CAP3_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos)                       /*!< GIMA CAP3_0_IN: EDGE Mask           */
+#define GIMA_CAP3_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_0_IN: SYNCH Position      */
+#define GIMA_CAP3_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos)                      /*!< GIMA CAP3_0_IN: SYNCH Mask          */
+#define GIMA_CAP3_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_0_IN: PULSE Position      */
+#define GIMA_CAP3_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos)                      /*!< GIMA CAP3_0_IN: PULSE Mask          */
+#define GIMA_CAP3_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_0_IN: SELECT Position     */
+#define GIMA_CAP3_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos)                     /*!< GIMA CAP3_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_1_IN  -----------------------------------------
+#define GIMA_CAP3_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_1_IN: INV Position        */
+#define GIMA_CAP3_1_IN_INV_Msk                                (0x01UL << GIMA_CAP3_1_IN_INV_Pos)                        /*!< GIMA CAP3_1_IN: INV Mask            */
+#define GIMA_CAP3_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_1_IN: EDGE Position       */
+#define GIMA_CAP3_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos)                       /*!< GIMA CAP3_1_IN: EDGE Mask           */
+#define GIMA_CAP3_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_1_IN: SYNCH Position      */
+#define GIMA_CAP3_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos)                      /*!< GIMA CAP3_1_IN: SYNCH Mask          */
+#define GIMA_CAP3_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_1_IN: PULSE Position      */
+#define GIMA_CAP3_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos)                      /*!< GIMA CAP3_1_IN: PULSE Mask          */
+#define GIMA_CAP3_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_1_IN: SELECT Position     */
+#define GIMA_CAP3_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos)                     /*!< GIMA CAP3_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_2_IN  -----------------------------------------
+#define GIMA_CAP3_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_2_IN: INV Position        */
+#define GIMA_CAP3_2_IN_INV_Msk                                (0x01UL << GIMA_CAP3_2_IN_INV_Pos)                        /*!< GIMA CAP3_2_IN: INV Mask            */
+#define GIMA_CAP3_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_2_IN: EDGE Position       */
+#define GIMA_CAP3_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos)                       /*!< GIMA CAP3_2_IN: EDGE Mask           */
+#define GIMA_CAP3_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_2_IN: SYNCH Position      */
+#define GIMA_CAP3_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos)                      /*!< GIMA CAP3_2_IN: SYNCH Mask          */
+#define GIMA_CAP3_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_2_IN: PULSE Position      */
+#define GIMA_CAP3_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos)                      /*!< GIMA CAP3_2_IN: PULSE Mask          */
+#define GIMA_CAP3_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_2_IN: SELECT Position     */
+#define GIMA_CAP3_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos)                     /*!< GIMA CAP3_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_3_IN  -----------------------------------------
+#define GIMA_CAP3_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_3_IN: INV Position        */
+#define GIMA_CAP3_3_IN_INV_Msk                                (0x01UL << GIMA_CAP3_3_IN_INV_Pos)                        /*!< GIMA CAP3_3_IN: INV Mask            */
+#define GIMA_CAP3_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_3_IN: EDGE Position       */
+#define GIMA_CAP3_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos)                       /*!< GIMA CAP3_3_IN: EDGE Mask           */
+#define GIMA_CAP3_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_3_IN: SYNCH Position      */
+#define GIMA_CAP3_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos)                      /*!< GIMA CAP3_3_IN: SYNCH Mask          */
+#define GIMA_CAP3_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_3_IN: PULSE Position      */
+#define GIMA_CAP3_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos)                      /*!< GIMA CAP3_3_IN: PULSE Mask          */
+#define GIMA_CAP3_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_3_IN: SELECT Position     */
+#define GIMA_CAP3_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos)                     /*!< GIMA CAP3_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_0_IN  -----------------------------------------
+#define GIMA_CTIN_0_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_0_IN: INV Position        */
+#define GIMA_CTIN_0_IN_INV_Msk                                (0x01UL << GIMA_CTIN_0_IN_INV_Pos)                        /*!< GIMA CTIN_0_IN: INV Mask            */
+#define GIMA_CTIN_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_0_IN: EDGE Position       */
+#define GIMA_CTIN_0_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos)                       /*!< GIMA CTIN_0_IN: EDGE Mask           */
+#define GIMA_CTIN_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_0_IN: SYNCH Position      */
+#define GIMA_CTIN_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos)                      /*!< GIMA CTIN_0_IN: SYNCH Mask          */
+#define GIMA_CTIN_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_0_IN: PULSE Position      */
+#define GIMA_CTIN_0_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos)                      /*!< GIMA CTIN_0_IN: PULSE Mask          */
+#define GIMA_CTIN_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_0_IN: SELECT Position     */
+#define GIMA_CTIN_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos)                     /*!< GIMA CTIN_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_1_IN  -----------------------------------------
+#define GIMA_CTIN_1_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_1_IN: INV Position        */
+#define GIMA_CTIN_1_IN_INV_Msk                                (0x01UL << GIMA_CTIN_1_IN_INV_Pos)                        /*!< GIMA CTIN_1_IN: INV Mask            */
+#define GIMA_CTIN_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_1_IN: EDGE Position       */
+#define GIMA_CTIN_1_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos)                       /*!< GIMA CTIN_1_IN: EDGE Mask           */
+#define GIMA_CTIN_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_1_IN: SYNCH Position      */
+#define GIMA_CTIN_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos)                      /*!< GIMA CTIN_1_IN: SYNCH Mask          */
+#define GIMA_CTIN_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_1_IN: PULSE Position      */
+#define GIMA_CTIN_1_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos)                      /*!< GIMA CTIN_1_IN: PULSE Mask          */
+#define GIMA_CTIN_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_1_IN: SELECT Position     */
+#define GIMA_CTIN_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos)                     /*!< GIMA CTIN_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_2_IN  -----------------------------------------
+#define GIMA_CTIN_2_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_2_IN: INV Position        */
+#define GIMA_CTIN_2_IN_INV_Msk                                (0x01UL << GIMA_CTIN_2_IN_INV_Pos)                        /*!< GIMA CTIN_2_IN: INV Mask            */
+#define GIMA_CTIN_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_2_IN: EDGE Position       */
+#define GIMA_CTIN_2_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos)                       /*!< GIMA CTIN_2_IN: EDGE Mask           */
+#define GIMA_CTIN_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_2_IN: SYNCH Position      */
+#define GIMA_CTIN_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos)                      /*!< GIMA CTIN_2_IN: SYNCH Mask          */
+#define GIMA_CTIN_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_2_IN: PULSE Position      */
+#define GIMA_CTIN_2_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos)                      /*!< GIMA CTIN_2_IN: PULSE Mask          */
+#define GIMA_CTIN_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_2_IN: SELECT Position     */
+#define GIMA_CTIN_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos)                     /*!< GIMA CTIN_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_3_IN  -----------------------------------------
+#define GIMA_CTIN_3_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_3_IN: INV Position        */
+#define GIMA_CTIN_3_IN_INV_Msk                                (0x01UL << GIMA_CTIN_3_IN_INV_Pos)                        /*!< GIMA CTIN_3_IN: INV Mask            */
+#define GIMA_CTIN_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_3_IN: EDGE Position       */
+#define GIMA_CTIN_3_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos)                       /*!< GIMA CTIN_3_IN: EDGE Mask           */
+#define GIMA_CTIN_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_3_IN: SYNCH Position      */
+#define GIMA_CTIN_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos)                      /*!< GIMA CTIN_3_IN: SYNCH Mask          */
+#define GIMA_CTIN_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_3_IN: PULSE Position      */
+#define GIMA_CTIN_3_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos)                      /*!< GIMA CTIN_3_IN: PULSE Mask          */
+#define GIMA_CTIN_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_3_IN: SELECT Position     */
+#define GIMA_CTIN_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos)                     /*!< GIMA CTIN_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_4_IN  -----------------------------------------
+#define GIMA_CTIN_4_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_4_IN: INV Position        */
+#define GIMA_CTIN_4_IN_INV_Msk                                (0x01UL << GIMA_CTIN_4_IN_INV_Pos)                        /*!< GIMA CTIN_4_IN: INV Mask            */
+#define GIMA_CTIN_4_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_4_IN: EDGE Position       */
+#define GIMA_CTIN_4_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos)                       /*!< GIMA CTIN_4_IN: EDGE Mask           */
+#define GIMA_CTIN_4_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_4_IN: SYNCH Position      */
+#define GIMA_CTIN_4_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos)                      /*!< GIMA CTIN_4_IN: SYNCH Mask          */
+#define GIMA_CTIN_4_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_4_IN: PULSE Position      */
+#define GIMA_CTIN_4_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos)                      /*!< GIMA CTIN_4_IN: PULSE Mask          */
+#define GIMA_CTIN_4_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_4_IN: SELECT Position     */
+#define GIMA_CTIN_4_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos)                     /*!< GIMA CTIN_4_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_5_IN  -----------------------------------------
+#define GIMA_CTIN_5_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_5_IN: INV Position        */
+#define GIMA_CTIN_5_IN_INV_Msk                                (0x01UL << GIMA_CTIN_5_IN_INV_Pos)                        /*!< GIMA CTIN_5_IN: INV Mask            */
+#define GIMA_CTIN_5_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_5_IN: EDGE Position       */
+#define GIMA_CTIN_5_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos)                       /*!< GIMA CTIN_5_IN: EDGE Mask           */
+#define GIMA_CTIN_5_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_5_IN: SYNCH Position      */
+#define GIMA_CTIN_5_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos)                      /*!< GIMA CTIN_5_IN: SYNCH Mask          */
+#define GIMA_CTIN_5_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_5_IN: PULSE Position      */
+#define GIMA_CTIN_5_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos)                      /*!< GIMA CTIN_5_IN: PULSE Mask          */
+#define GIMA_CTIN_5_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_5_IN: SELECT Position     */
+#define GIMA_CTIN_5_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos)                     /*!< GIMA CTIN_5_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_6_IN  -----------------------------------------
+#define GIMA_CTIN_6_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_6_IN: INV Position        */
+#define GIMA_CTIN_6_IN_INV_Msk                                (0x01UL << GIMA_CTIN_6_IN_INV_Pos)                        /*!< GIMA CTIN_6_IN: INV Mask            */
+#define GIMA_CTIN_6_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_6_IN: EDGE Position       */
+#define GIMA_CTIN_6_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos)                       /*!< GIMA CTIN_6_IN: EDGE Mask           */
+#define GIMA_CTIN_6_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_6_IN: SYNCH Position      */
+#define GIMA_CTIN_6_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos)                      /*!< GIMA CTIN_6_IN: SYNCH Mask          */
+#define GIMA_CTIN_6_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_6_IN: PULSE Position      */
+#define GIMA_CTIN_6_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos)                      /*!< GIMA CTIN_6_IN: PULSE Mask          */
+#define GIMA_CTIN_6_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_6_IN: SELECT Position     */
+#define GIMA_CTIN_6_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos)                     /*!< GIMA CTIN_6_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_7_IN  -----------------------------------------
+#define GIMA_CTIN_7_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_7_IN: INV Position        */
+#define GIMA_CTIN_7_IN_INV_Msk                                (0x01UL << GIMA_CTIN_7_IN_INV_Pos)                        /*!< GIMA CTIN_7_IN: INV Mask            */
+#define GIMA_CTIN_7_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_7_IN: EDGE Position       */
+#define GIMA_CTIN_7_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos)                       /*!< GIMA CTIN_7_IN: EDGE Mask           */
+#define GIMA_CTIN_7_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_7_IN: SYNCH Position      */
+#define GIMA_CTIN_7_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos)                      /*!< GIMA CTIN_7_IN: SYNCH Mask          */
+#define GIMA_CTIN_7_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_7_IN: PULSE Position      */
+#define GIMA_CTIN_7_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos)                      /*!< GIMA CTIN_7_IN: PULSE Mask          */
+#define GIMA_CTIN_7_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_7_IN: SELECT Position     */
+#define GIMA_CTIN_7_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos)                     /*!< GIMA CTIN_7_IN: SELECT Mask         */
+
+// ----------------------------------  GIMA_VADC_TRIGGER_IN  --------------------------------------
+#define GIMA_VADC_TRIGGER_IN_INV_Pos                          0                                                         /*!< GIMA VADC_TRIGGER_IN: INV Position  */
+#define GIMA_VADC_TRIGGER_IN_INV_Msk                          (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos)                  /*!< GIMA VADC_TRIGGER_IN: INV Mask      */
+#define GIMA_VADC_TRIGGER_IN_EDGE_Pos                         1                                                         /*!< GIMA VADC_TRIGGER_IN: EDGE Position */
+#define GIMA_VADC_TRIGGER_IN_EDGE_Msk                         (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos)                 /*!< GIMA VADC_TRIGGER_IN: EDGE Mask     */
+#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos                        2                                                         /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */
+#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos)                /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask    */
+#define GIMA_VADC_TRIGGER_IN_PULSE_Pos                        3                                                         /*!< GIMA VADC_TRIGGER_IN: PULSE Position */
+#define GIMA_VADC_TRIGGER_IN_PULSE_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos)                /*!< GIMA VADC_TRIGGER_IN: PULSE Mask    */
+#define GIMA_VADC_TRIGGER_IN_SELECT_Pos                       4                                                         /*!< GIMA VADC_TRIGGER_IN: SELECT Position */
+#define GIMA_VADC_TRIGGER_IN_SELECT_Msk                       (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos)               /*!< GIMA VADC_TRIGGER_IN: SELECT Mask   */
+
+// ---------------------------------  GIMA_EVENTROUTER_13_IN  -------------------------------------
+#define GIMA_EVENTROUTER_13_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_13_IN: INV Position */
+#define GIMA_EVENTROUTER_13_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos)                /*!< GIMA EVENTROUTER_13_IN: INV Mask    */
+#define GIMA_EVENTROUTER_13_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_13_IN: EDGE Position */
+#define GIMA_EVENTROUTER_13_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_13_IN: EDGE Mask   */
+#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask  */
+#define GIMA_EVENTROUTER_13_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_13_IN: PULSE Position */
+#define GIMA_EVENTROUTER_13_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_13_IN: PULSE Mask  */
+#define GIMA_EVENTROUTER_13_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_13_IN: SELECT Position */
+#define GIMA_EVENTROUTER_13_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */
+
+// ---------------------------------  GIMA_EVENTROUTER_14_IN  -------------------------------------
+#define GIMA_EVENTROUTER_14_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_14_IN: INV Position */
+#define GIMA_EVENTROUTER_14_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos)                /*!< GIMA EVENTROUTER_14_IN: INV Mask    */
+#define GIMA_EVENTROUTER_14_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_14_IN: EDGE Position */
+#define GIMA_EVENTROUTER_14_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_14_IN: EDGE Mask   */
+#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask  */
+#define GIMA_EVENTROUTER_14_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_14_IN: PULSE Position */
+#define GIMA_EVENTROUTER_14_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_14_IN: PULSE Mask  */
+#define GIMA_EVENTROUTER_14_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_14_IN: SELECT Position */
+#define GIMA_EVENTROUTER_14_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */
+
+// ---------------------------------  GIMA_EVENTROUTER_16_IN  -------------------------------------
+#define GIMA_EVENTROUTER_16_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_16_IN: INV Position */
+#define GIMA_EVENTROUTER_16_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos)                /*!< GIMA EVENTROUTER_16_IN: INV Mask    */
+#define GIMA_EVENTROUTER_16_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_16_IN: EDGE Position */
+#define GIMA_EVENTROUTER_16_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_16_IN: EDGE Mask   */
+#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask  */
+#define GIMA_EVENTROUTER_16_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_16_IN: PULSE Position */
+#define GIMA_EVENTROUTER_16_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_16_IN: PULSE Mask  */
+#define GIMA_EVENTROUTER_16_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_16_IN: SELECT Position */
+#define GIMA_EVENTROUTER_16_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */
+
+// ------------------------------------  GIMA_ADCSTART0_IN  ---------------------------------------
+#define GIMA_ADCSTART0_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART0_IN: INV Position     */
+#define GIMA_ADCSTART0_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART0_IN_INV_Pos)                     /*!< GIMA ADCSTART0_IN: INV Mask         */
+#define GIMA_ADCSTART0_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART0_IN: EDGE Position    */
+#define GIMA_ADCSTART0_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos)                    /*!< GIMA ADCSTART0_IN: EDGE Mask        */
+#define GIMA_ADCSTART0_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART0_IN: SYNCH Position   */
+#define GIMA_ADCSTART0_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART0_IN: SYNCH Mask       */
+#define GIMA_ADCSTART0_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART0_IN: PULSE Position   */
+#define GIMA_ADCSTART0_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos)                   /*!< GIMA ADCSTART0_IN: PULSE Mask       */
+#define GIMA_ADCSTART0_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART0_IN: SELECT Position  */
+#define GIMA_ADCSTART0_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos)                  /*!< GIMA ADCSTART0_IN: SELECT Mask      */
+
+// ------------------------------------  GIMA_ADCSTART1_IN  ---------------------------------------
+#define GIMA_ADCSTART1_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART1_IN: INV Position     */
+#define GIMA_ADCSTART1_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART1_IN_INV_Pos)                     /*!< GIMA ADCSTART1_IN: INV Mask         */
+#define GIMA_ADCSTART1_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART1_IN: EDGE Position    */
+#define GIMA_ADCSTART1_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos)                    /*!< GIMA ADCSTART1_IN: EDGE Mask        */
+#define GIMA_ADCSTART1_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART1_IN: SYNCH Position   */
+#define GIMA_ADCSTART1_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART1_IN: SYNCH Mask       */
+#define GIMA_ADCSTART1_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART1_IN: PULSE Position   */
+#define GIMA_ADCSTART1_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos)                   /*!< GIMA ADCSTART1_IN: PULSE Mask       */
+#define GIMA_ADCSTART1_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART1_IN: SELECT Position  */
+#define GIMA_ADCSTART1_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos)                  /*!< GIMA ADCSTART1_IN: SELECT Mask      */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  DAC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  DAC_CR  ---------------------------------------------
+#define DAC_CR_VALUE_Pos                                      6                                                         /*!< DAC CR: VALUE Position              */
+#define DAC_CR_VALUE_Msk                                      (0x000003ffUL << DAC_CR_VALUE_Pos)                        /*!< DAC CR: VALUE Mask                  */
+#define DAC_CR_BIAS_Pos                                       16                                                        /*!< DAC CR: BIAS Position               */
+#define DAC_CR_BIAS_Msk                                       (0x01UL << DAC_CR_BIAS_Pos)                               /*!< DAC CR: BIAS Mask                   */
+
+// ----------------------------------------  DAC_CTRL  --------------------------------------------
+#define DAC_CTRL_INT_DMA_REQ_Pos                              0                                                         /*!< DAC CTRL: INT_DMA_REQ Position      */
+#define DAC_CTRL_INT_DMA_REQ_Msk                              (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos)                      /*!< DAC CTRL: INT_DMA_REQ Mask          */
+#define DAC_CTRL_DBLBUF_ENA_Pos                               1                                                         /*!< DAC CTRL: DBLBUF_ENA Position       */
+#define DAC_CTRL_DBLBUF_ENA_Msk                               (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos)                       /*!< DAC CTRL: DBLBUF_ENA Mask           */
+#define DAC_CTRL_CNT_ENA_Pos                                  2                                                         /*!< DAC CTRL: CNT_ENA Position          */
+#define DAC_CTRL_CNT_ENA_Msk                                  (0x01UL << DAC_CTRL_CNT_ENA_Pos)                          /*!< DAC CTRL: CNT_ENA Mask              */
+#define DAC_CTRL_DMA_ENA_Pos                                  3                                                         /*!< DAC CTRL: DMA_ENA Position          */
+#define DAC_CTRL_DMA_ENA_Msk                                  (0x01UL << DAC_CTRL_DMA_ENA_Pos)                          /*!< DAC CTRL: DMA_ENA Mask              */
+
+// ---------------------------------------  DAC_CNTVAL  -------------------------------------------
+#define DAC_CNTVAL_VALUE_Pos                                  0                                                         /*!< DAC CNTVAL: VALUE Position          */
+#define DAC_CNTVAL_VALUE_Msk                                  (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos)                    /*!< DAC CNTVAL: VALUE Mask              */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                C_CAN0 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  C_CAN0_CNTL  ------------------------------------------
+#define C_CAN0_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN0 CNTL: INIT Position          */
+#define C_CAN0_CNTL_INIT_Msk                                  (0x01UL << C_CAN0_CNTL_INIT_Pos)                          /*!< C_CAN0 CNTL: INIT Mask              */
+#define C_CAN0_CNTL_IE_Pos                                    1                                                         /*!< C_CAN0 CNTL: IE Position            */
+#define C_CAN0_CNTL_IE_Msk                                    (0x01UL << C_CAN0_CNTL_IE_Pos)                            /*!< C_CAN0 CNTL: IE Mask                */
+#define C_CAN0_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN0 CNTL: SIE Position           */
+#define C_CAN0_CNTL_SIE_Msk                                   (0x01UL << C_CAN0_CNTL_SIE_Pos)                           /*!< C_CAN0 CNTL: SIE Mask               */
+#define C_CAN0_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN0 CNTL: EIE Position           */
+#define C_CAN0_CNTL_EIE_Msk                                   (0x01UL << C_CAN0_CNTL_EIE_Pos)                           /*!< C_CAN0 CNTL: EIE Mask               */
+#define C_CAN0_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN0 CNTL: DAR Position           */
+#define C_CAN0_CNTL_DAR_Msk                                   (0x01UL << C_CAN0_CNTL_DAR_Pos)                           /*!< C_CAN0 CNTL: DAR Mask               */
+#define C_CAN0_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN0 CNTL: CCE Position           */
+#define C_CAN0_CNTL_CCE_Msk                                   (0x01UL << C_CAN0_CNTL_CCE_Pos)                           /*!< C_CAN0 CNTL: CCE Mask               */
+#define C_CAN0_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN0 CNTL: TEST Position          */
+#define C_CAN0_CNTL_TEST_Msk                                  (0x01UL << C_CAN0_CNTL_TEST_Pos)                          /*!< C_CAN0 CNTL: TEST Mask              */
+
+// ---------------------------------------  C_CAN0_STAT  ------------------------------------------
+#define C_CAN0_STAT_LEC_Pos                                   0                                                         /*!< C_CAN0 STAT: LEC Position           */
+#define C_CAN0_STAT_LEC_Msk                                   (0x07UL << C_CAN0_STAT_LEC_Pos)                           /*!< C_CAN0 STAT: LEC Mask               */
+#define C_CAN0_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN0 STAT: TXOK Position          */
+#define C_CAN0_STAT_TXOK_Msk                                  (0x01UL << C_CAN0_STAT_TXOK_Pos)                          /*!< C_CAN0 STAT: TXOK Mask              */
+#define C_CAN0_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN0 STAT: RXOK Position          */
+#define C_CAN0_STAT_RXOK_Msk                                  (0x01UL << C_CAN0_STAT_RXOK_Pos)                          /*!< C_CAN0 STAT: RXOK Mask              */
+#define C_CAN0_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN0 STAT: EPASS Position         */
+#define C_CAN0_STAT_EPASS_Msk                                 (0x01UL << C_CAN0_STAT_EPASS_Pos)                         /*!< C_CAN0 STAT: EPASS Mask             */
+#define C_CAN0_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN0 STAT: EWARN Position         */
+#define C_CAN0_STAT_EWARN_Msk                                 (0x01UL << C_CAN0_STAT_EWARN_Pos)                         /*!< C_CAN0 STAT: EWARN Mask             */
+#define C_CAN0_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN0 STAT: BOFF Position          */
+#define C_CAN0_STAT_BOFF_Msk                                  (0x01UL << C_CAN0_STAT_BOFF_Pos)                          /*!< C_CAN0 STAT: BOFF Mask              */
+
+// ----------------------------------------  C_CAN0_EC  -------------------------------------------
+#define C_CAN0_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN0 EC: TEC_7_0 Position         */
+#define C_CAN0_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos)                   /*!< C_CAN0 EC: TEC_7_0 Mask             */
+#define C_CAN0_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN0 EC: REC_6_0 Position         */
+#define C_CAN0_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN0_EC_REC_6_0_Pos)                         /*!< C_CAN0 EC: REC_6_0 Mask             */
+#define C_CAN0_EC_RP_Pos                                      15                                                        /*!< C_CAN0 EC: RP Position              */
+#define C_CAN0_EC_RP_Msk                                      (0x01UL << C_CAN0_EC_RP_Pos)                              /*!< C_CAN0 EC: RP Mask                  */
+
+// ----------------------------------------  C_CAN0_BT  -------------------------------------------
+#define C_CAN0_BT_BRP_Pos                                     0                                                         /*!< C_CAN0 BT: BRP Position             */
+#define C_CAN0_BT_BRP_Msk                                     (0x3fUL << C_CAN0_BT_BRP_Pos)                             /*!< C_CAN0 BT: BRP Mask                 */
+#define C_CAN0_BT_SJW_Pos                                     6                                                         /*!< C_CAN0 BT: SJW Position             */
+#define C_CAN0_BT_SJW_Msk                                     (0x03UL << C_CAN0_BT_SJW_Pos)                             /*!< C_CAN0 BT: SJW Mask                 */
+#define C_CAN0_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN0 BT: TSEG1 Position           */
+#define C_CAN0_BT_TSEG1_Msk                                   (0x0fUL << C_CAN0_BT_TSEG1_Pos)                           /*!< C_CAN0 BT: TSEG1 Mask               */
+#define C_CAN0_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN0 BT: TSEG2 Position           */
+#define C_CAN0_BT_TSEG2_Msk                                   (0x07UL << C_CAN0_BT_TSEG2_Pos)                           /*!< C_CAN0 BT: TSEG2 Mask               */
+
+// ---------------------------------------  C_CAN0_INT  -------------------------------------------
+#define C_CAN0_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN0 INT: INTID15_0 Position      */
+#define C_CAN0_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos)                /*!< C_CAN0 INT: INTID15_0 Mask          */
+
+// ---------------------------------------  C_CAN0_TEST  ------------------------------------------
+#define C_CAN0_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN0 TEST: BASIC Position         */
+#define C_CAN0_TEST_BASIC_Msk                                 (0x01UL << C_CAN0_TEST_BASIC_Pos)                         /*!< C_CAN0 TEST: BASIC Mask             */
+#define C_CAN0_TEST_SILENT_Pos                                3                                                         /*!< C_CAN0 TEST: SILENT Position        */
+#define C_CAN0_TEST_SILENT_Msk                                (0x01UL << C_CAN0_TEST_SILENT_Pos)                        /*!< C_CAN0 TEST: SILENT Mask            */
+#define C_CAN0_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN0 TEST: LBACK Position         */
+#define C_CAN0_TEST_LBACK_Msk                                 (0x01UL << C_CAN0_TEST_LBACK_Pos)                         /*!< C_CAN0 TEST: LBACK Mask             */
+#define C_CAN0_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN0 TEST: TX1_0 Position         */
+#define C_CAN0_TEST_TX1_0_Msk                                 (0x03UL << C_CAN0_TEST_TX1_0_Pos)                         /*!< C_CAN0 TEST: TX1_0 Mask             */
+#define C_CAN0_TEST_RX_Pos                                    7                                                         /*!< C_CAN0 TEST: RX Position            */
+#define C_CAN0_TEST_RX_Msk                                    (0x01UL << C_CAN0_TEST_RX_Pos)                            /*!< C_CAN0 TEST: RX Mask                */
+
+// ---------------------------------------  C_CAN0_BRPE  ------------------------------------------
+#define C_CAN0_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN0 BRPE: BRPE Position          */
+#define C_CAN0_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN0_BRPE_BRPE_Pos)                          /*!< C_CAN0 BRPE: BRPE Mask              */
+
+// ------------------------------------  C_CAN0_IF1_CMDREQ  ---------------------------------------
+#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */
+#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask     */
+#define C_CAN0_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF1_CMDREQ: BUSY Position    */
+#define C_CAN0_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF1_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN0_IF1_CMDMSK_R  --------------------------------------
+#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */
+#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask    */
+#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */
+#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask    */
+#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */
+#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */
+#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position  */
+#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask      */
+#define C_CAN0_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_R: ARB Position   */
+#define C_CAN0_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask       */
+#define C_CAN0_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_R: MASK Position  */
+#define C_CAN0_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask      */
+#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */
+#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask     */
+
+// -----------------------------------  C_CAN0_IF1_CMDMSK_W  --------------------------------------
+#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */
+#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask    */
+#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */
+#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask    */
+#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */
+#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask    */
+#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */
+#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position  */
+#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask      */
+#define C_CAN0_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_W: ARB Position   */
+#define C_CAN0_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask       */
+#define C_CAN0_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_W: MASK Position  */
+#define C_CAN0_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask      */
+#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */
+#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask     */
+
+// -------------------------------------  C_CAN0_IF1_MSK1  ----------------------------------------
+#define C_CAN0_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF1_MSK1: MSK15_0 Position   */
+#define C_CAN0_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN0_IF1_MSK2  ----------------------------------------
+#define C_CAN0_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF1_MSK2: MSK28_16 Position  */
+#define C_CAN0_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask      */
+#define C_CAN0_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF1_MSK2: MDIR Position      */
+#define C_CAN0_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF1_MSK2: MDIR Mask          */
+#define C_CAN0_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF1_MSK2: MXTD Position      */
+#define C_CAN0_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF1_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN0_IF1_ARB1  ----------------------------------------
+#define C_CAN0_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF1_ARB1: ID15_0 Position    */
+#define C_CAN0_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF1_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN0_IF1_ARB2  ----------------------------------------
+#define C_CAN0_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF1_ARB2: ID28_16 Position   */
+#define C_CAN0_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF1_ARB2: ID28_16 Mask       */
+#define C_CAN0_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF1_ARB2: DIR Position       */
+#define C_CAN0_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos)                       /*!< C_CAN0 IF1_ARB2: DIR Mask           */
+#define C_CAN0_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF1_ARB2: XTD Position       */
+#define C_CAN0_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos)                       /*!< C_CAN0 IF1_ARB2: XTD Mask           */
+#define C_CAN0_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF1_ARB2: MSGVAL Position    */
+#define C_CAN0_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF1_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN0_IF1_MCTRL  ----------------------------------------
+#define C_CAN0_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position   */
+#define C_CAN0_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask       */
+#define C_CAN0_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF1_MCTRL: EOB Position      */
+#define C_CAN0_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF1_MCTRL: EOB Mask          */
+#define C_CAN0_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF1_MCTRL: TXRQST Position   */
+#define C_CAN0_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF1_MCTRL: TXRQST Mask       */
+#define C_CAN0_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF1_MCTRL: RMTEN Position    */
+#define C_CAN0_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF1_MCTRL: RMTEN Mask        */
+#define C_CAN0_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF1_MCTRL: RXIE Position     */
+#define C_CAN0_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: RXIE Mask         */
+#define C_CAN0_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF1_MCTRL: TXIE Position     */
+#define C_CAN0_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: TXIE Mask         */
+#define C_CAN0_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF1_MCTRL: UMASK Position    */
+#define C_CAN0_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF1_MCTRL: UMASK Mask        */
+#define C_CAN0_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF1_MCTRL: INTPND Position   */
+#define C_CAN0_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF1_MCTRL: INTPND Mask       */
+#define C_CAN0_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF1_MCTRL: MSGLST Position   */
+#define C_CAN0_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF1_MCTRL: MSGLST Mask       */
+#define C_CAN0_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF1_MCTRL: NEWDAT Position   */
+#define C_CAN0_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN0_IF1_DA1  -----------------------------------------
+#define C_CAN0_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF1_DA1: DATA0 Position      */
+#define C_CAN0_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos)                /*!< C_CAN0 IF1_DA1: DATA0 Mask          */
+#define C_CAN0_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF1_DA1: DATA1 Position      */
+#define C_CAN0_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos)                /*!< C_CAN0 IF1_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN0_IF1_DA2  -----------------------------------------
+#define C_CAN0_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF1_DA2: DATA2 Position      */
+#define C_CAN0_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos)                /*!< C_CAN0 IF1_DA2: DATA2 Mask          */
+#define C_CAN0_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF1_DA2: DATA3 Position      */
+#define C_CAN0_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos)                /*!< C_CAN0 IF1_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN0_IF1_DB1  -----------------------------------------
+#define C_CAN0_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF1_DB1: DATA4 Position      */
+#define C_CAN0_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos)                /*!< C_CAN0 IF1_DB1: DATA4 Mask          */
+#define C_CAN0_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF1_DB1: DATA5 Position      */
+#define C_CAN0_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos)                /*!< C_CAN0 IF1_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN0_IF1_DB2  -----------------------------------------
+#define C_CAN0_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF1_DB2: DATA6 Position      */
+#define C_CAN0_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos)                /*!< C_CAN0 IF1_DB2: DATA6 Mask          */
+#define C_CAN0_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF1_DB2: DATA7 Position      */
+#define C_CAN0_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos)                /*!< C_CAN0 IF1_DB2: DATA7 Mask          */
+
+// ------------------------------------  C_CAN0_IF2_CMDREQ  ---------------------------------------
+#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */
+#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask     */
+#define C_CAN0_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF2_CMDREQ: BUSY Position    */
+#define C_CAN0_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF2_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN0_IF2_CMDMSK_R  --------------------------------------
+#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */
+#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask    */
+#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */
+#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask    */
+#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */
+#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */
+#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position  */
+#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask      */
+#define C_CAN0_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_R: ARB Position   */
+#define C_CAN0_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask       */
+#define C_CAN0_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_R: MASK Position  */
+#define C_CAN0_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask      */
+#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */
+#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask     */
+
+// -----------------------------------  C_CAN0_IF2_CMDMSK_W  --------------------------------------
+#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */
+#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask    */
+#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */
+#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask    */
+#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */
+#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask    */
+#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */
+#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position  */
+#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask      */
+#define C_CAN0_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_W: ARB Position   */
+#define C_CAN0_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask       */
+#define C_CAN0_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_W: MASK Position  */
+#define C_CAN0_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask      */
+#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */
+#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask     */
+
+// -------------------------------------  C_CAN0_IF2_MSK1  ----------------------------------------
+#define C_CAN0_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF2_MSK1: MSK15_0 Position   */
+#define C_CAN0_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN0_IF2_MSK2  ----------------------------------------
+#define C_CAN0_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF2_MSK2: MSK28_16 Position  */
+#define C_CAN0_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask      */
+#define C_CAN0_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF2_MSK2: MDIR Position      */
+#define C_CAN0_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF2_MSK2: MDIR Mask          */
+#define C_CAN0_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF2_MSK2: MXTD Position      */
+#define C_CAN0_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF2_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN0_IF2_ARB1  ----------------------------------------
+#define C_CAN0_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF2_ARB1: ID15_0 Position    */
+#define C_CAN0_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF2_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN0_IF2_ARB2  ----------------------------------------
+#define C_CAN0_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF2_ARB2: ID28_16 Position   */
+#define C_CAN0_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF2_ARB2: ID28_16 Mask       */
+#define C_CAN0_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF2_ARB2: DIR Position       */
+#define C_CAN0_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos)                       /*!< C_CAN0 IF2_ARB2: DIR Mask           */
+#define C_CAN0_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF2_ARB2: XTD Position       */
+#define C_CAN0_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos)                       /*!< C_CAN0 IF2_ARB2: XTD Mask           */
+#define C_CAN0_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF2_ARB2: MSGVAL Position    */
+#define C_CAN0_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF2_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN0_IF2_MCTRL  ----------------------------------------
+#define C_CAN0_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position   */
+#define C_CAN0_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask       */
+#define C_CAN0_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF2_MCTRL: EOB Position      */
+#define C_CAN0_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF2_MCTRL: EOB Mask          */
+#define C_CAN0_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF2_MCTRL: TXRQST Position   */
+#define C_CAN0_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF2_MCTRL: TXRQST Mask       */
+#define C_CAN0_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF2_MCTRL: RMTEN Position    */
+#define C_CAN0_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF2_MCTRL: RMTEN Mask        */
+#define C_CAN0_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF2_MCTRL: RXIE Position     */
+#define C_CAN0_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: RXIE Mask         */
+#define C_CAN0_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF2_MCTRL: TXIE Position     */
+#define C_CAN0_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: TXIE Mask         */
+#define C_CAN0_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF2_MCTRL: UMASK Position    */
+#define C_CAN0_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF2_MCTRL: UMASK Mask        */
+#define C_CAN0_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF2_MCTRL: INTPND Position   */
+#define C_CAN0_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF2_MCTRL: INTPND Mask       */
+#define C_CAN0_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF2_MCTRL: MSGLST Position   */
+#define C_CAN0_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF2_MCTRL: MSGLST Mask       */
+#define C_CAN0_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF2_MCTRL: NEWDAT Position   */
+#define C_CAN0_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN0_IF2_DA1  -----------------------------------------
+#define C_CAN0_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF2_DA1: DATA0 Position      */
+#define C_CAN0_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos)                /*!< C_CAN0 IF2_DA1: DATA0 Mask          */
+#define C_CAN0_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF2_DA1: DATA1 Position      */
+#define C_CAN0_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos)                /*!< C_CAN0 IF2_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN0_IF2_DA2  -----------------------------------------
+#define C_CAN0_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF2_DA2: DATA2 Position      */
+#define C_CAN0_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos)                /*!< C_CAN0 IF2_DA2: DATA2 Mask          */
+#define C_CAN0_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF2_DA2: DATA3 Position      */
+#define C_CAN0_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos)                /*!< C_CAN0 IF2_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN0_IF2_DB1  -----------------------------------------
+#define C_CAN0_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF2_DB1: DATA4 Position      */
+#define C_CAN0_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos)                /*!< C_CAN0 IF2_DB1: DATA4 Mask          */
+#define C_CAN0_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF2_DB1: DATA5 Position      */
+#define C_CAN0_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos)                /*!< C_CAN0 IF2_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN0_IF2_DB2  -----------------------------------------
+#define C_CAN0_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF2_DB2: DATA6 Position      */
+#define C_CAN0_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos)                /*!< C_CAN0 IF2_DB2: DATA6 Mask          */
+#define C_CAN0_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF2_DB2: DATA7 Position      */
+#define C_CAN0_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos)                /*!< C_CAN0 IF2_DB2: DATA7 Mask          */
+
+// --------------------------------------  C_CAN0_TXREQ1  -----------------------------------------
+#define C_CAN0_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN0 TXREQ1: TXRQST16_1 Position  */
+#define C_CAN0_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask      */
+
+// --------------------------------------  C_CAN0_TXREQ2  -----------------------------------------
+#define C_CAN0_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */
+#define C_CAN0_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask     */
+
+// ---------------------------------------  C_CAN0_ND1  -------------------------------------------
+#define C_CAN0_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN0 ND1: NEWDAT16_1 Position     */
+#define C_CAN0_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos)               /*!< C_CAN0 ND1: NEWDAT16_1 Mask         */
+
+// ---------------------------------------  C_CAN0_ND2  -------------------------------------------
+#define C_CAN0_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN0 ND2: NEWDAT32_17 Position    */
+#define C_CAN0_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos)              /*!< C_CAN0 ND2: NEWDAT32_17 Mask        */
+
+// ---------------------------------------  C_CAN0_IR1  -------------------------------------------
+#define C_CAN0_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN0 IR1: INTPND16_1 Position     */
+#define C_CAN0_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos)               /*!< C_CAN0 IR1: INTPND16_1 Mask         */
+
+// ---------------------------------------  C_CAN0_IR2  -------------------------------------------
+#define C_CAN0_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN0 IR2: INTPND32_17 Position    */
+#define C_CAN0_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos)              /*!< C_CAN0 IR2: INTPND32_17 Mask        */
+
+// --------------------------------------  C_CAN0_MSGV1  ------------------------------------------
+#define C_CAN0_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN0 MSGV1: MSGVAL16_1 Position   */
+#define C_CAN0_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask       */
+
+// --------------------------------------  C_CAN0_MSGV2  ------------------------------------------
+#define C_CAN0_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN0 MSGV2: MSGVAL32_17 Position  */
+#define C_CAN0_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask      */
+
+// --------------------------------------  C_CAN0_CLKDIV  -----------------------------------------
+#define C_CAN0_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN0 CLKDIV: CLKDIVVAL Position   */
+#define C_CAN0_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 ADC0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  ADC0_CR  --------------------------------------------
+#define ADC0_CR_SEL_Pos                                       0                                                         /*!< ADC0 CR: SEL Position               */
+#define ADC0_CR_SEL_Msk                                       (0x000000ffUL << ADC0_CR_SEL_Pos)                         /*!< ADC0 CR: SEL Mask                   */
+#define ADC0_CR_CLKDIV_Pos                                    8                                                         /*!< ADC0 CR: CLKDIV Position            */
+#define ADC0_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC0_CR_CLKDIV_Pos)                      /*!< ADC0 CR: CLKDIV Mask                */
+#define ADC0_CR_BURST_Pos                                     16                                                        /*!< ADC0 CR: BURST Position             */
+#define ADC0_CR_BURST_Msk                                     (0x01UL << ADC0_CR_BURST_Pos)                             /*!< ADC0 CR: BURST Mask                 */
+#define ADC0_CR_CLKS_Pos                                      17                                                        /*!< ADC0 CR: CLKS Position              */
+#define ADC0_CR_CLKS_Msk                                      (0x07UL << ADC0_CR_CLKS_Pos)                              /*!< ADC0 CR: CLKS Mask                  */
+#define ADC0_CR_PDN_Pos                                       21                                                        /*!< ADC0 CR: PDN Position               */
+#define ADC0_CR_PDN_Msk                                       (0x01UL << ADC0_CR_PDN_Pos)                               /*!< ADC0 CR: PDN Mask                   */
+#define ADC0_CR_START_Pos                                     24                                                        /*!< ADC0 CR: START Position             */
+#define ADC0_CR_START_Msk                                     (0x07UL << ADC0_CR_START_Pos)                             /*!< ADC0 CR: START Mask                 */
+#define ADC0_CR_EDGE_Pos                                      27                                                        /*!< ADC0 CR: EDGE Position              */
+#define ADC0_CR_EDGE_Msk                                      (0x01UL << ADC0_CR_EDGE_Pos)                              /*!< ADC0 CR: EDGE Mask                  */
+
+// ----------------------------------------  ADC0_GDR  --------------------------------------------
+#define ADC0_GDR_V_VREF_Pos                                   6                                                         /*!< ADC0 GDR: V_VREF Position           */
+#define ADC0_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC0_GDR_V_VREF_Pos)                     /*!< ADC0 GDR: V_VREF Mask               */
+#define ADC0_GDR_CHN_Pos                                      24                                                        /*!< ADC0 GDR: CHN Position              */
+#define ADC0_GDR_CHN_Msk                                      (0x07UL << ADC0_GDR_CHN_Pos)                              /*!< ADC0 GDR: CHN Mask                  */
+#define ADC0_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC0 GDR: OVERRUN Position          */
+#define ADC0_GDR_OVERRUN_Msk                                  (0x01UL << ADC0_GDR_OVERRUN_Pos)                          /*!< ADC0 GDR: OVERRUN Mask              */
+#define ADC0_GDR_DONE_Pos                                     31                                                        /*!< ADC0 GDR: DONE Position             */
+#define ADC0_GDR_DONE_Msk                                     (0x01UL << ADC0_GDR_DONE_Pos)                             /*!< ADC0 GDR: DONE Mask                 */
+
+// ---------------------------------------  ADC0_INTEN  -------------------------------------------
+#define ADC0_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC0 INTEN: ADINTEN Position        */
+#define ADC0_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos)                  /*!< ADC0 INTEN: ADINTEN Mask            */
+#define ADC0_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC0 INTEN: ADGINTEN Position       */
+#define ADC0_INTEN_ADGINTEN_Msk                               (0x01UL << ADC0_INTEN_ADGINTEN_Pos)                       /*!< ADC0 INTEN: ADGINTEN Mask           */
+
+// ----------------------------------------  ADC0_DR0  --------------------------------------------
+#define ADC0_DR0_V_VREF_Pos                                   6                                                         /*!< ADC0 DR0: V_VREF Position           */
+#define ADC0_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR0_V_VREF_Pos)                     /*!< ADC0 DR0: V_VREF Mask               */
+#define ADC0_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR0: OVERRUN Position          */
+#define ADC0_DR0_OVERRUN_Msk                                  (0x01UL << ADC0_DR0_OVERRUN_Pos)                          /*!< ADC0 DR0: OVERRUN Mask              */
+#define ADC0_DR0_DONE_Pos                                     31                                                        /*!< ADC0 DR0: DONE Position             */
+#define ADC0_DR0_DONE_Msk                                     (0x01UL << ADC0_DR0_DONE_Pos)                             /*!< ADC0 DR0: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR1  --------------------------------------------
+#define ADC0_DR1_V_VREF_Pos                                   6                                                         /*!< ADC0 DR1: V_VREF Position           */
+#define ADC0_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR1_V_VREF_Pos)                     /*!< ADC0 DR1: V_VREF Mask               */
+#define ADC0_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR1: OVERRUN Position          */
+#define ADC0_DR1_OVERRUN_Msk                                  (0x01UL << ADC0_DR1_OVERRUN_Pos)                          /*!< ADC0 DR1: OVERRUN Mask              */
+#define ADC0_DR1_DONE_Pos                                     31                                                        /*!< ADC0 DR1: DONE Position             */
+#define ADC0_DR1_DONE_Msk                                     (0x01UL << ADC0_DR1_DONE_Pos)                             /*!< ADC0 DR1: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR2  --------------------------------------------
+#define ADC0_DR2_V_VREF_Pos                                   6                                                         /*!< ADC0 DR2: V_VREF Position           */
+#define ADC0_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR2_V_VREF_Pos)                     /*!< ADC0 DR2: V_VREF Mask               */
+#define ADC0_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR2: OVERRUN Position          */
+#define ADC0_DR2_OVERRUN_Msk                                  (0x01UL << ADC0_DR2_OVERRUN_Pos)                          /*!< ADC0 DR2: OVERRUN Mask              */
+#define ADC0_DR2_DONE_Pos                                     31                                                        /*!< ADC0 DR2: DONE Position             */
+#define ADC0_DR2_DONE_Msk                                     (0x01UL << ADC0_DR2_DONE_Pos)                             /*!< ADC0 DR2: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR3  --------------------------------------------
+#define ADC0_DR3_V_VREF_Pos                                   6                                                         /*!< ADC0 DR3: V_VREF Position           */
+#define ADC0_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR3_V_VREF_Pos)                     /*!< ADC0 DR3: V_VREF Mask               */
+#define ADC0_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR3: OVERRUN Position          */
+#define ADC0_DR3_OVERRUN_Msk                                  (0x01UL << ADC0_DR3_OVERRUN_Pos)                          /*!< ADC0 DR3: OVERRUN Mask              */
+#define ADC0_DR3_DONE_Pos                                     31                                                        /*!< ADC0 DR3: DONE Position             */
+#define ADC0_DR3_DONE_Msk                                     (0x01UL << ADC0_DR3_DONE_Pos)                             /*!< ADC0 DR3: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR4  --------------------------------------------
+#define ADC0_DR4_V_VREF_Pos                                   6                                                         /*!< ADC0 DR4: V_VREF Position           */
+#define ADC0_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR4_V_VREF_Pos)                     /*!< ADC0 DR4: V_VREF Mask               */
+#define ADC0_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR4: OVERRUN Position          */
+#define ADC0_DR4_OVERRUN_Msk                                  (0x01UL << ADC0_DR4_OVERRUN_Pos)                          /*!< ADC0 DR4: OVERRUN Mask              */
+#define ADC0_DR4_DONE_Pos                                     31                                                        /*!< ADC0 DR4: DONE Position             */
+#define ADC0_DR4_DONE_Msk                                     (0x01UL << ADC0_DR4_DONE_Pos)                             /*!< ADC0 DR4: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR5  --------------------------------------------
+#define ADC0_DR5_V_VREF_Pos                                   6                                                         /*!< ADC0 DR5: V_VREF Position           */
+#define ADC0_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR5_V_VREF_Pos)                     /*!< ADC0 DR5: V_VREF Mask               */
+#define ADC0_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR5: OVERRUN Position          */
+#define ADC0_DR5_OVERRUN_Msk                                  (0x01UL << ADC0_DR5_OVERRUN_Pos)                          /*!< ADC0 DR5: OVERRUN Mask              */
+#define ADC0_DR5_DONE_Pos                                     31                                                        /*!< ADC0 DR5: DONE Position             */
+#define ADC0_DR5_DONE_Msk                                     (0x01UL << ADC0_DR5_DONE_Pos)                             /*!< ADC0 DR5: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR6  --------------------------------------------
+#define ADC0_DR6_V_VREF_Pos                                   6                                                         /*!< ADC0 DR6: V_VREF Position           */
+#define ADC0_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR6_V_VREF_Pos)                     /*!< ADC0 DR6: V_VREF Mask               */
+#define ADC0_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR6: OVERRUN Position          */
+#define ADC0_DR6_OVERRUN_Msk                                  (0x01UL << ADC0_DR6_OVERRUN_Pos)                          /*!< ADC0 DR6: OVERRUN Mask              */
+#define ADC0_DR6_DONE_Pos                                     31                                                        /*!< ADC0 DR6: DONE Position             */
+#define ADC0_DR6_DONE_Msk                                     (0x01UL << ADC0_DR6_DONE_Pos)                             /*!< ADC0 DR6: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR7  --------------------------------------------
+#define ADC0_DR7_V_VREF_Pos                                   6                                                         /*!< ADC0 DR7: V_VREF Position           */
+#define ADC0_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR7_V_VREF_Pos)                     /*!< ADC0 DR7: V_VREF Mask               */
+#define ADC0_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR7: OVERRUN Position          */
+#define ADC0_DR7_OVERRUN_Msk                                  (0x01UL << ADC0_DR7_OVERRUN_Pos)                          /*!< ADC0 DR7: OVERRUN Mask              */
+#define ADC0_DR7_DONE_Pos                                     31                                                        /*!< ADC0 DR7: DONE Position             */
+#define ADC0_DR7_DONE_Msk                                     (0x01UL << ADC0_DR7_DONE_Pos)                             /*!< ADC0 DR7: DONE Mask                 */
+
+// ----------------------------------------  ADC0_STAT  -------------------------------------------
+#define ADC0_STAT_DONE_Pos                                    0                                                         /*!< ADC0 STAT: DONE Position            */
+#define ADC0_STAT_DONE_Msk                                    (0x000000ffUL << ADC0_STAT_DONE_Pos)                      /*!< ADC0 STAT: DONE Mask                */
+#define ADC0_STAT_OVERUN_Pos                                  8                                                         /*!< ADC0 STAT: OVERUN Position          */
+#define ADC0_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC0_STAT_OVERUN_Pos)                    /*!< ADC0 STAT: OVERUN Mask              */
+#define ADC0_STAT_ADINT_Pos                                   16                                                        /*!< ADC0 STAT: ADINT Position           */
+#define ADC0_STAT_ADINT_Msk                                   (0x01UL << ADC0_STAT_ADINT_Pos)                           /*!< ADC0 STAT: ADINT Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 ADC1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  ADC1_CR  --------------------------------------------
+#define ADC1_CR_SEL_Pos                                       0                                                         /*!< ADC1 CR: SEL Position               */
+#define ADC1_CR_SEL_Msk                                       (0x000000ffUL << ADC1_CR_SEL_Pos)                         /*!< ADC1 CR: SEL Mask                   */
+#define ADC1_CR_CLKDIV_Pos                                    8                                                         /*!< ADC1 CR: CLKDIV Position            */
+#define ADC1_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC1_CR_CLKDIV_Pos)                      /*!< ADC1 CR: CLKDIV Mask                */
+#define ADC1_CR_BURST_Pos                                     16                                                        /*!< ADC1 CR: BURST Position             */
+#define ADC1_CR_BURST_Msk                                     (0x01UL << ADC1_CR_BURST_Pos)                             /*!< ADC1 CR: BURST Mask                 */
+#define ADC1_CR_CLKS_Pos                                      17                                                        /*!< ADC1 CR: CLKS Position              */
+#define ADC1_CR_CLKS_Msk                                      (0x07UL << ADC1_CR_CLKS_Pos)                              /*!< ADC1 CR: CLKS Mask                  */
+#define ADC1_CR_PDN_Pos                                       21                                                        /*!< ADC1 CR: PDN Position               */
+#define ADC1_CR_PDN_Msk                                       (0x01UL << ADC1_CR_PDN_Pos)                               /*!< ADC1 CR: PDN Mask                   */
+#define ADC1_CR_START_Pos                                     24                                                        /*!< ADC1 CR: START Position             */
+#define ADC1_CR_START_Msk                                     (0x07UL << ADC1_CR_START_Pos)                             /*!< ADC1 CR: START Mask                 */
+#define ADC1_CR_EDGE_Pos                                      27                                                        /*!< ADC1 CR: EDGE Position              */
+#define ADC1_CR_EDGE_Msk                                      (0x01UL << ADC1_CR_EDGE_Pos)                              /*!< ADC1 CR: EDGE Mask                  */
+
+// ----------------------------------------  ADC1_GDR  --------------------------------------------
+#define ADC1_GDR_V_VREF_Pos                                   6                                                         /*!< ADC1 GDR: V_VREF Position           */
+#define ADC1_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC1_GDR_V_VREF_Pos)                     /*!< ADC1 GDR: V_VREF Mask               */
+#define ADC1_GDR_CHN_Pos                                      24                                                        /*!< ADC1 GDR: CHN Position              */
+#define ADC1_GDR_CHN_Msk                                      (0x07UL << ADC1_GDR_CHN_Pos)                              /*!< ADC1 GDR: CHN Mask                  */
+#define ADC1_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC1 GDR: OVERRUN Position          */
+#define ADC1_GDR_OVERRUN_Msk                                  (0x01UL << ADC1_GDR_OVERRUN_Pos)                          /*!< ADC1 GDR: OVERRUN Mask              */
+#define ADC1_GDR_DONE_Pos                                     31                                                        /*!< ADC1 GDR: DONE Position             */
+#define ADC1_GDR_DONE_Msk                                     (0x01UL << ADC1_GDR_DONE_Pos)                             /*!< ADC1 GDR: DONE Mask                 */
+
+// ---------------------------------------  ADC1_INTEN  -------------------------------------------
+#define ADC1_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC1 INTEN: ADINTEN Position        */
+#define ADC1_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos)                  /*!< ADC1 INTEN: ADINTEN Mask            */
+#define ADC1_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC1 INTEN: ADGINTEN Position       */
+#define ADC1_INTEN_ADGINTEN_Msk                               (0x01UL << ADC1_INTEN_ADGINTEN_Pos)                       /*!< ADC1 INTEN: ADGINTEN Mask           */
+
+// ----------------------------------------  ADC1_DR0  --------------------------------------------
+#define ADC1_DR0_V_VREF_Pos                                   6                                                         /*!< ADC1 DR0: V_VREF Position           */
+#define ADC1_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR0_V_VREF_Pos)                     /*!< ADC1 DR0: V_VREF Mask               */
+#define ADC1_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR0: OVERRUN Position          */
+#define ADC1_DR0_OVERRUN_Msk                                  (0x01UL << ADC1_DR0_OVERRUN_Pos)                          /*!< ADC1 DR0: OVERRUN Mask              */
+#define ADC1_DR0_DONE_Pos                                     31                                                        /*!< ADC1 DR0: DONE Position             */
+#define ADC1_DR0_DONE_Msk                                     (0x01UL << ADC1_DR0_DONE_Pos)                             /*!< ADC1 DR0: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR1  --------------------------------------------
+#define ADC1_DR1_V_VREF_Pos                                   6                                                         /*!< ADC1 DR1: V_VREF Position           */
+#define ADC1_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR1_V_VREF_Pos)                     /*!< ADC1 DR1: V_VREF Mask               */
+#define ADC1_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR1: OVERRUN Position          */
+#define ADC1_DR1_OVERRUN_Msk                                  (0x01UL << ADC1_DR1_OVERRUN_Pos)                          /*!< ADC1 DR1: OVERRUN Mask              */
+#define ADC1_DR1_DONE_Pos                                     31                                                        /*!< ADC1 DR1: DONE Position             */
+#define ADC1_DR1_DONE_Msk                                     (0x01UL << ADC1_DR1_DONE_Pos)                             /*!< ADC1 DR1: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR2  --------------------------------------------
+#define ADC1_DR2_V_VREF_Pos                                   6                                                         /*!< ADC1 DR2: V_VREF Position           */
+#define ADC1_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR2_V_VREF_Pos)                     /*!< ADC1 DR2: V_VREF Mask               */
+#define ADC1_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR2: OVERRUN Position          */
+#define ADC1_DR2_OVERRUN_Msk                                  (0x01UL << ADC1_DR2_OVERRUN_Pos)                          /*!< ADC1 DR2: OVERRUN Mask              */
+#define ADC1_DR2_DONE_Pos                                     31                                                        /*!< ADC1 DR2: DONE Position             */
+#define ADC1_DR2_DONE_Msk                                     (0x01UL << ADC1_DR2_DONE_Pos)                             /*!< ADC1 DR2: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR3  --------------------------------------------
+#define ADC1_DR3_V_VREF_Pos                                   6                                                         /*!< ADC1 DR3: V_VREF Position           */
+#define ADC1_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR3_V_VREF_Pos)                     /*!< ADC1 DR3: V_VREF Mask               */
+#define ADC1_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR3: OVERRUN Position          */
+#define ADC1_DR3_OVERRUN_Msk                                  (0x01UL << ADC1_DR3_OVERRUN_Pos)                          /*!< ADC1 DR3: OVERRUN Mask              */
+#define ADC1_DR3_DONE_Pos                                     31                                                        /*!< ADC1 DR3: DONE Position             */
+#define ADC1_DR3_DONE_Msk                                     (0x01UL << ADC1_DR3_DONE_Pos)                             /*!< ADC1 DR3: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR4  --------------------------------------------
+#define ADC1_DR4_V_VREF_Pos                                   6                                                         /*!< ADC1 DR4: V_VREF Position           */
+#define ADC1_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR4_V_VREF_Pos)                     /*!< ADC1 DR4: V_VREF Mask               */
+#define ADC1_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR4: OVERRUN Position          */
+#define ADC1_DR4_OVERRUN_Msk                                  (0x01UL << ADC1_DR4_OVERRUN_Pos)                          /*!< ADC1 DR4: OVERRUN Mask              */
+#define ADC1_DR4_DONE_Pos                                     31                                                        /*!< ADC1 DR4: DONE Position             */
+#define ADC1_DR4_DONE_Msk                                     (0x01UL << ADC1_DR4_DONE_Pos)                             /*!< ADC1 DR4: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR5  --------------------------------------------
+#define ADC1_DR5_V_VREF_Pos                                   6                                                         /*!< ADC1 DR5: V_VREF Position           */
+#define ADC1_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR5_V_VREF_Pos)                     /*!< ADC1 DR5: V_VREF Mask               */
+#define ADC1_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR5: OVERRUN Position          */
+#define ADC1_DR5_OVERRUN_Msk                                  (0x01UL << ADC1_DR5_OVERRUN_Pos)                          /*!< ADC1 DR5: OVERRUN Mask              */
+#define ADC1_DR5_DONE_Pos                                     31                                                        /*!< ADC1 DR5: DONE Position             */
+#define ADC1_DR5_DONE_Msk                                     (0x01UL << ADC1_DR5_DONE_Pos)                             /*!< ADC1 DR5: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR6  --------------------------------------------
+#define ADC1_DR6_V_VREF_Pos                                   6                                                         /*!< ADC1 DR6: V_VREF Position           */
+#define ADC1_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR6_V_VREF_Pos)                     /*!< ADC1 DR6: V_VREF Mask               */
+#define ADC1_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR6: OVERRUN Position          */
+#define ADC1_DR6_OVERRUN_Msk                                  (0x01UL << ADC1_DR6_OVERRUN_Pos)                          /*!< ADC1 DR6: OVERRUN Mask              */
+#define ADC1_DR6_DONE_Pos                                     31                                                        /*!< ADC1 DR6: DONE Position             */
+#define ADC1_DR6_DONE_Msk                                     (0x01UL << ADC1_DR6_DONE_Pos)                             /*!< ADC1 DR6: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR7  --------------------------------------------
+#define ADC1_DR7_V_VREF_Pos                                   6                                                         /*!< ADC1 DR7: V_VREF Position           */
+#define ADC1_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR7_V_VREF_Pos)                     /*!< ADC1 DR7: V_VREF Mask               */
+#define ADC1_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR7: OVERRUN Position          */
+#define ADC1_DR7_OVERRUN_Msk                                  (0x01UL << ADC1_DR7_OVERRUN_Pos)                          /*!< ADC1 DR7: OVERRUN Mask              */
+#define ADC1_DR7_DONE_Pos                                     31                                                        /*!< ADC1 DR7: DONE Position             */
+#define ADC1_DR7_DONE_Msk                                     (0x01UL << ADC1_DR7_DONE_Pos)                             /*!< ADC1 DR7: DONE Mask                 */
+
+// ----------------------------------------  ADC1_STAT  -------------------------------------------
+#define ADC1_STAT_DONE_Pos                                    0                                                         /*!< ADC1 STAT: DONE Position            */
+#define ADC1_STAT_DONE_Msk                                    (0x000000ffUL << ADC1_STAT_DONE_Pos)                      /*!< ADC1 STAT: DONE Mask                */
+#define ADC1_STAT_OVERUN_Pos                                  8                                                         /*!< ADC1 STAT: OVERUN Position          */
+#define ADC1_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC1_STAT_OVERUN_Pos)                    /*!< ADC1 STAT: OVERUN Mask              */
+#define ADC1_STAT_ADINT_Pos                                   16                                                        /*!< ADC1 STAT: ADINT Position           */
+#define ADC1_STAT_ADINT_Msk                                   (0x01UL << ADC1_STAT_ADINT_Pos)                           /*!< ADC1 STAT: ADINT Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                               GPIO_PORT Position & Mask                              -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------  GPIO_PORT_B0  ------------------------------------------
+#define GPIO_PORT_B0_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B0: PBYTE Position        */
+#define GPIO_PORT_B0_PBYTE_Msk                                (0x01UL << GPIO_PORT_B0_PBYTE_Pos)                        /*!< GPIO_PORT B0: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B1  ------------------------------------------
+#define GPIO_PORT_B1_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B1: PBYTE Position        */
+#define GPIO_PORT_B1_PBYTE_Msk                                (0x01UL << GPIO_PORT_B1_PBYTE_Pos)                        /*!< GPIO_PORT B1: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B2  ------------------------------------------
+#define GPIO_PORT_B2_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B2: PBYTE Position        */
+#define GPIO_PORT_B2_PBYTE_Msk                                (0x01UL << GPIO_PORT_B2_PBYTE_Pos)                        /*!< GPIO_PORT B2: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B3  ------------------------------------------
+#define GPIO_PORT_B3_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B3: PBYTE Position        */
+#define GPIO_PORT_B3_PBYTE_Msk                                (0x01UL << GPIO_PORT_B3_PBYTE_Pos)                        /*!< GPIO_PORT B3: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B4  ------------------------------------------
+#define GPIO_PORT_B4_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B4: PBYTE Position        */
+#define GPIO_PORT_B4_PBYTE_Msk                                (0x01UL << GPIO_PORT_B4_PBYTE_Pos)                        /*!< GPIO_PORT B4: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B5  ------------------------------------------
+#define GPIO_PORT_B5_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B5: PBYTE Position        */
+#define GPIO_PORT_B5_PBYTE_Msk                                (0x01UL << GPIO_PORT_B5_PBYTE_Pos)                        /*!< GPIO_PORT B5: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B6  ------------------------------------------
+#define GPIO_PORT_B6_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B6: PBYTE Position        */
+#define GPIO_PORT_B6_PBYTE_Msk                                (0x01UL << GPIO_PORT_B6_PBYTE_Pos)                        /*!< GPIO_PORT B6: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B7  ------------------------------------------
+#define GPIO_PORT_B7_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B7: PBYTE Position        */
+#define GPIO_PORT_B7_PBYTE_Msk                                (0x01UL << GPIO_PORT_B7_PBYTE_Pos)                        /*!< GPIO_PORT B7: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B8  ------------------------------------------
+#define GPIO_PORT_B8_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B8: PBYTE Position        */
+#define GPIO_PORT_B8_PBYTE_Msk                                (0x01UL << GPIO_PORT_B8_PBYTE_Pos)                        /*!< GPIO_PORT B8: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B9  ------------------------------------------
+#define GPIO_PORT_B9_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B9: PBYTE Position        */
+#define GPIO_PORT_B9_PBYTE_Msk                                (0x01UL << GPIO_PORT_B9_PBYTE_Pos)                        /*!< GPIO_PORT B9: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B10  -----------------------------------------
+#define GPIO_PORT_B10_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B10: PBYTE Position       */
+#define GPIO_PORT_B10_PBYTE_Msk                               (0x01UL << GPIO_PORT_B10_PBYTE_Pos)                       /*!< GPIO_PORT B10: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B11  -----------------------------------------
+#define GPIO_PORT_B11_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B11: PBYTE Position       */
+#define GPIO_PORT_B11_PBYTE_Msk                               (0x01UL << GPIO_PORT_B11_PBYTE_Pos)                       /*!< GPIO_PORT B11: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B12  -----------------------------------------
+#define GPIO_PORT_B12_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B12: PBYTE Position       */
+#define GPIO_PORT_B12_PBYTE_Msk                               (0x01UL << GPIO_PORT_B12_PBYTE_Pos)                       /*!< GPIO_PORT B12: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B13  -----------------------------------------
+#define GPIO_PORT_B13_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B13: PBYTE Position       */
+#define GPIO_PORT_B13_PBYTE_Msk                               (0x01UL << GPIO_PORT_B13_PBYTE_Pos)                       /*!< GPIO_PORT B13: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B14  -----------------------------------------
+#define GPIO_PORT_B14_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B14: PBYTE Position       */
+#define GPIO_PORT_B14_PBYTE_Msk                               (0x01UL << GPIO_PORT_B14_PBYTE_Pos)                       /*!< GPIO_PORT B14: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B15  -----------------------------------------
+#define GPIO_PORT_B15_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B15: PBYTE Position       */
+#define GPIO_PORT_B15_PBYTE_Msk                               (0x01UL << GPIO_PORT_B15_PBYTE_Pos)                       /*!< GPIO_PORT B15: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B16  -----------------------------------------
+#define GPIO_PORT_B16_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B16: PBYTE Position       */
+#define GPIO_PORT_B16_PBYTE_Msk                               (0x01UL << GPIO_PORT_B16_PBYTE_Pos)                       /*!< GPIO_PORT B16: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B17  -----------------------------------------
+#define GPIO_PORT_B17_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B17: PBYTE Position       */
+#define GPIO_PORT_B17_PBYTE_Msk                               (0x01UL << GPIO_PORT_B17_PBYTE_Pos)                       /*!< GPIO_PORT B17: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B18  -----------------------------------------
+#define GPIO_PORT_B18_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B18: PBYTE Position       */
+#define GPIO_PORT_B18_PBYTE_Msk                               (0x01UL << GPIO_PORT_B18_PBYTE_Pos)                       /*!< GPIO_PORT B18: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B19  -----------------------------------------
+#define GPIO_PORT_B19_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B19: PBYTE Position       */
+#define GPIO_PORT_B19_PBYTE_Msk                               (0x01UL << GPIO_PORT_B19_PBYTE_Pos)                       /*!< GPIO_PORT B19: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B20  -----------------------------------------
+#define GPIO_PORT_B20_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B20: PBYTE Position       */
+#define GPIO_PORT_B20_PBYTE_Msk                               (0x01UL << GPIO_PORT_B20_PBYTE_Pos)                       /*!< GPIO_PORT B20: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B21  -----------------------------------------
+#define GPIO_PORT_B21_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B21: PBYTE Position       */
+#define GPIO_PORT_B21_PBYTE_Msk                               (0x01UL << GPIO_PORT_B21_PBYTE_Pos)                       /*!< GPIO_PORT B21: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B22  -----------------------------------------
+#define GPIO_PORT_B22_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B22: PBYTE Position       */
+#define GPIO_PORT_B22_PBYTE_Msk                               (0x01UL << GPIO_PORT_B22_PBYTE_Pos)                       /*!< GPIO_PORT B22: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B23  -----------------------------------------
+#define GPIO_PORT_B23_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B23: PBYTE Position       */
+#define GPIO_PORT_B23_PBYTE_Msk                               (0x01UL << GPIO_PORT_B23_PBYTE_Pos)                       /*!< GPIO_PORT B23: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B24  -----------------------------------------
+#define GPIO_PORT_B24_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B24: PBYTE Position       */
+#define GPIO_PORT_B24_PBYTE_Msk                               (0x01UL << GPIO_PORT_B24_PBYTE_Pos)                       /*!< GPIO_PORT B24: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B25  -----------------------------------------
+#define GPIO_PORT_B25_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B25: PBYTE Position       */
+#define GPIO_PORT_B25_PBYTE_Msk                               (0x01UL << GPIO_PORT_B25_PBYTE_Pos)                       /*!< GPIO_PORT B25: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B26  -----------------------------------------
+#define GPIO_PORT_B26_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B26: PBYTE Position       */
+#define GPIO_PORT_B26_PBYTE_Msk                               (0x01UL << GPIO_PORT_B26_PBYTE_Pos)                       /*!< GPIO_PORT B26: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B27  -----------------------------------------
+#define GPIO_PORT_B27_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B27: PBYTE Position       */
+#define GPIO_PORT_B27_PBYTE_Msk                               (0x01UL << GPIO_PORT_B27_PBYTE_Pos)                       /*!< GPIO_PORT B27: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B28  -----------------------------------------
+#define GPIO_PORT_B28_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B28: PBYTE Position       */
+#define GPIO_PORT_B28_PBYTE_Msk                               (0x01UL << GPIO_PORT_B28_PBYTE_Pos)                       /*!< GPIO_PORT B28: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B29  -----------------------------------------
+#define GPIO_PORT_B29_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B29: PBYTE Position       */
+#define GPIO_PORT_B29_PBYTE_Msk                               (0x01UL << GPIO_PORT_B29_PBYTE_Pos)                       /*!< GPIO_PORT B29: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B30  -----------------------------------------
+#define GPIO_PORT_B30_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B30: PBYTE Position       */
+#define GPIO_PORT_B30_PBYTE_Msk                               (0x01UL << GPIO_PORT_B30_PBYTE_Pos)                       /*!< GPIO_PORT B30: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B31  -----------------------------------------
+#define GPIO_PORT_B31_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B31: PBYTE Position       */
+#define GPIO_PORT_B31_PBYTE_Msk                               (0x01UL << GPIO_PORT_B31_PBYTE_Pos)                       /*!< GPIO_PORT B31: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B32  -----------------------------------------
+#define GPIO_PORT_B32_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B32: PBYTE Position       */
+#define GPIO_PORT_B32_PBYTE_Msk                               (0x01UL << GPIO_PORT_B32_PBYTE_Pos)                       /*!< GPIO_PORT B32: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B33  -----------------------------------------
+#define GPIO_PORT_B33_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B33: PBYTE Position       */
+#define GPIO_PORT_B33_PBYTE_Msk                               (0x01UL << GPIO_PORT_B33_PBYTE_Pos)                       /*!< GPIO_PORT B33: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B34  -----------------------------------------
+#define GPIO_PORT_B34_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B34: PBYTE Position       */
+#define GPIO_PORT_B34_PBYTE_Msk                               (0x01UL << GPIO_PORT_B34_PBYTE_Pos)                       /*!< GPIO_PORT B34: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B35  -----------------------------------------
+#define GPIO_PORT_B35_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B35: PBYTE Position       */
+#define GPIO_PORT_B35_PBYTE_Msk                               (0x01UL << GPIO_PORT_B35_PBYTE_Pos)                       /*!< GPIO_PORT B35: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B36  -----------------------------------------
+#define GPIO_PORT_B36_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B36: PBYTE Position       */
+#define GPIO_PORT_B36_PBYTE_Msk                               (0x01UL << GPIO_PORT_B36_PBYTE_Pos)                       /*!< GPIO_PORT B36: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B37  -----------------------------------------
+#define GPIO_PORT_B37_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B37: PBYTE Position       */
+#define GPIO_PORT_B37_PBYTE_Msk                               (0x01UL << GPIO_PORT_B37_PBYTE_Pos)                       /*!< GPIO_PORT B37: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B38  -----------------------------------------
+#define GPIO_PORT_B38_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B38: PBYTE Position       */
+#define GPIO_PORT_B38_PBYTE_Msk                               (0x01UL << GPIO_PORT_B38_PBYTE_Pos)                       /*!< GPIO_PORT B38: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B39  -----------------------------------------
+#define GPIO_PORT_B39_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B39: PBYTE Position       */
+#define GPIO_PORT_B39_PBYTE_Msk                               (0x01UL << GPIO_PORT_B39_PBYTE_Pos)                       /*!< GPIO_PORT B39: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B40  -----------------------------------------
+#define GPIO_PORT_B40_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B40: PBYTE Position       */
+#define GPIO_PORT_B40_PBYTE_Msk                               (0x01UL << GPIO_PORT_B40_PBYTE_Pos)                       /*!< GPIO_PORT B40: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B41  -----------------------------------------
+#define GPIO_PORT_B41_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B41: PBYTE Position       */
+#define GPIO_PORT_B41_PBYTE_Msk                               (0x01UL << GPIO_PORT_B41_PBYTE_Pos)                       /*!< GPIO_PORT B41: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B42  -----------------------------------------
+#define GPIO_PORT_B42_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B42: PBYTE Position       */
+#define GPIO_PORT_B42_PBYTE_Msk                               (0x01UL << GPIO_PORT_B42_PBYTE_Pos)                       /*!< GPIO_PORT B42: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B43  -----------------------------------------
+#define GPIO_PORT_B43_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B43: PBYTE Position       */
+#define GPIO_PORT_B43_PBYTE_Msk                               (0x01UL << GPIO_PORT_B43_PBYTE_Pos)                       /*!< GPIO_PORT B43: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B44  -----------------------------------------
+#define GPIO_PORT_B44_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B44: PBYTE Position       */
+#define GPIO_PORT_B44_PBYTE_Msk                               (0x01UL << GPIO_PORT_B44_PBYTE_Pos)                       /*!< GPIO_PORT B44: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B45  -----------------------------------------
+#define GPIO_PORT_B45_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B45: PBYTE Position       */
+#define GPIO_PORT_B45_PBYTE_Msk                               (0x01UL << GPIO_PORT_B45_PBYTE_Pos)                       /*!< GPIO_PORT B45: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B46  -----------------------------------------
+#define GPIO_PORT_B46_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B46: PBYTE Position       */
+#define GPIO_PORT_B46_PBYTE_Msk                               (0x01UL << GPIO_PORT_B46_PBYTE_Pos)                       /*!< GPIO_PORT B46: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B47  -----------------------------------------
+#define GPIO_PORT_B47_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B47: PBYTE Position       */
+#define GPIO_PORT_B47_PBYTE_Msk                               (0x01UL << GPIO_PORT_B47_PBYTE_Pos)                       /*!< GPIO_PORT B47: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B48  -----------------------------------------
+#define GPIO_PORT_B48_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B48: PBYTE Position       */
+#define GPIO_PORT_B48_PBYTE_Msk                               (0x01UL << GPIO_PORT_B48_PBYTE_Pos)                       /*!< GPIO_PORT B48: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B49  -----------------------------------------
+#define GPIO_PORT_B49_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B49: PBYTE Position       */
+#define GPIO_PORT_B49_PBYTE_Msk                               (0x01UL << GPIO_PORT_B49_PBYTE_Pos)                       /*!< GPIO_PORT B49: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B50  -----------------------------------------
+#define GPIO_PORT_B50_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B50: PBYTE Position       */
+#define GPIO_PORT_B50_PBYTE_Msk                               (0x01UL << GPIO_PORT_B50_PBYTE_Pos)                       /*!< GPIO_PORT B50: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B51  -----------------------------------------
+#define GPIO_PORT_B51_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B51: PBYTE Position       */
+#define GPIO_PORT_B51_PBYTE_Msk                               (0x01UL << GPIO_PORT_B51_PBYTE_Pos)                       /*!< GPIO_PORT B51: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B52  -----------------------------------------
+#define GPIO_PORT_B52_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B52: PBYTE Position       */
+#define GPIO_PORT_B52_PBYTE_Msk                               (0x01UL << GPIO_PORT_B52_PBYTE_Pos)                       /*!< GPIO_PORT B52: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B53  -----------------------------------------
+#define GPIO_PORT_B53_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B53: PBYTE Position       */
+#define GPIO_PORT_B53_PBYTE_Msk                               (0x01UL << GPIO_PORT_B53_PBYTE_Pos)                       /*!< GPIO_PORT B53: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B54  -----------------------------------------
+#define GPIO_PORT_B54_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B54: PBYTE Position       */
+#define GPIO_PORT_B54_PBYTE_Msk                               (0x01UL << GPIO_PORT_B54_PBYTE_Pos)                       /*!< GPIO_PORT B54: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B55  -----------------------------------------
+#define GPIO_PORT_B55_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B55: PBYTE Position       */
+#define GPIO_PORT_B55_PBYTE_Msk                               (0x01UL << GPIO_PORT_B55_PBYTE_Pos)                       /*!< GPIO_PORT B55: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B56  -----------------------------------------
+#define GPIO_PORT_B56_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B56: PBYTE Position       */
+#define GPIO_PORT_B56_PBYTE_Msk                               (0x01UL << GPIO_PORT_B56_PBYTE_Pos)                       /*!< GPIO_PORT B56: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B57  -----------------------------------------
+#define GPIO_PORT_B57_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B57: PBYTE Position       */
+#define GPIO_PORT_B57_PBYTE_Msk                               (0x01UL << GPIO_PORT_B57_PBYTE_Pos)                       /*!< GPIO_PORT B57: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B58  -----------------------------------------
+#define GPIO_PORT_B58_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B58: PBYTE Position       */
+#define GPIO_PORT_B58_PBYTE_Msk                               (0x01UL << GPIO_PORT_B58_PBYTE_Pos)                       /*!< GPIO_PORT B58: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B59  -----------------------------------------
+#define GPIO_PORT_B59_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B59: PBYTE Position       */
+#define GPIO_PORT_B59_PBYTE_Msk                               (0x01UL << GPIO_PORT_B59_PBYTE_Pos)                       /*!< GPIO_PORT B59: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B60  -----------------------------------------
+#define GPIO_PORT_B60_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B60: PBYTE Position       */
+#define GPIO_PORT_B60_PBYTE_Msk                               (0x01UL << GPIO_PORT_B60_PBYTE_Pos)                       /*!< GPIO_PORT B60: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B61  -----------------------------------------
+#define GPIO_PORT_B61_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B61: PBYTE Position       */
+#define GPIO_PORT_B61_PBYTE_Msk                               (0x01UL << GPIO_PORT_B61_PBYTE_Pos)                       /*!< GPIO_PORT B61: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B62  -----------------------------------------
+#define GPIO_PORT_B62_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B62: PBYTE Position       */
+#define GPIO_PORT_B62_PBYTE_Msk                               (0x01UL << GPIO_PORT_B62_PBYTE_Pos)                       /*!< GPIO_PORT B62: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B63  -----------------------------------------
+#define GPIO_PORT_B63_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B63: PBYTE Position       */
+#define GPIO_PORT_B63_PBYTE_Msk                               (0x01UL << GPIO_PORT_B63_PBYTE_Pos)                       /*!< GPIO_PORT B63: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B64  -----------------------------------------
+#define GPIO_PORT_B64_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B64: PBYTE Position       */
+#define GPIO_PORT_B64_PBYTE_Msk                               (0x01UL << GPIO_PORT_B64_PBYTE_Pos)                       /*!< GPIO_PORT B64: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B65  -----------------------------------------
+#define GPIO_PORT_B65_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B65: PBYTE Position       */
+#define GPIO_PORT_B65_PBYTE_Msk                               (0x01UL << GPIO_PORT_B65_PBYTE_Pos)                       /*!< GPIO_PORT B65: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B66  -----------------------------------------
+#define GPIO_PORT_B66_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B66: PBYTE Position       */
+#define GPIO_PORT_B66_PBYTE_Msk                               (0x01UL << GPIO_PORT_B66_PBYTE_Pos)                       /*!< GPIO_PORT B66: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B67  -----------------------------------------
+#define GPIO_PORT_B67_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B67: PBYTE Position       */
+#define GPIO_PORT_B67_PBYTE_Msk                               (0x01UL << GPIO_PORT_B67_PBYTE_Pos)                       /*!< GPIO_PORT B67: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B68  -----------------------------------------
+#define GPIO_PORT_B68_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B68: PBYTE Position       */
+#define GPIO_PORT_B68_PBYTE_Msk                               (0x01UL << GPIO_PORT_B68_PBYTE_Pos)                       /*!< GPIO_PORT B68: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B69  -----------------------------------------
+#define GPIO_PORT_B69_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B69: PBYTE Position       */
+#define GPIO_PORT_B69_PBYTE_Msk                               (0x01UL << GPIO_PORT_B69_PBYTE_Pos)                       /*!< GPIO_PORT B69: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B70  -----------------------------------------
+#define GPIO_PORT_B70_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B70: PBYTE Position       */
+#define GPIO_PORT_B70_PBYTE_Msk                               (0x01UL << GPIO_PORT_B70_PBYTE_Pos)                       /*!< GPIO_PORT B70: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B71  -----------------------------------------
+#define GPIO_PORT_B71_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B71: PBYTE Position       */
+#define GPIO_PORT_B71_PBYTE_Msk                               (0x01UL << GPIO_PORT_B71_PBYTE_Pos)                       /*!< GPIO_PORT B71: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B72  -----------------------------------------
+#define GPIO_PORT_B72_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B72: PBYTE Position       */
+#define GPIO_PORT_B72_PBYTE_Msk                               (0x01UL << GPIO_PORT_B72_PBYTE_Pos)                       /*!< GPIO_PORT B72: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B73  -----------------------------------------
+#define GPIO_PORT_B73_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B73: PBYTE Position       */
+#define GPIO_PORT_B73_PBYTE_Msk                               (0x01UL << GPIO_PORT_B73_PBYTE_Pos)                       /*!< GPIO_PORT B73: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B74  -----------------------------------------
+#define GPIO_PORT_B74_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B74: PBYTE Position       */
+#define GPIO_PORT_B74_PBYTE_Msk                               (0x01UL << GPIO_PORT_B74_PBYTE_Pos)                       /*!< GPIO_PORT B74: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B75  -----------------------------------------
+#define GPIO_PORT_B75_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B75: PBYTE Position       */
+#define GPIO_PORT_B75_PBYTE_Msk                               (0x01UL << GPIO_PORT_B75_PBYTE_Pos)                       /*!< GPIO_PORT B75: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B76  -----------------------------------------
+#define GPIO_PORT_B76_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B76: PBYTE Position       */
+#define GPIO_PORT_B76_PBYTE_Msk                               (0x01UL << GPIO_PORT_B76_PBYTE_Pos)                       /*!< GPIO_PORT B76: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B77  -----------------------------------------
+#define GPIO_PORT_B77_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B77: PBYTE Position       */
+#define GPIO_PORT_B77_PBYTE_Msk                               (0x01UL << GPIO_PORT_B77_PBYTE_Pos)                       /*!< GPIO_PORT B77: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B78  -----------------------------------------
+#define GPIO_PORT_B78_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B78: PBYTE Position       */
+#define GPIO_PORT_B78_PBYTE_Msk                               (0x01UL << GPIO_PORT_B78_PBYTE_Pos)                       /*!< GPIO_PORT B78: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B79  -----------------------------------------
+#define GPIO_PORT_B79_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B79: PBYTE Position       */
+#define GPIO_PORT_B79_PBYTE_Msk                               (0x01UL << GPIO_PORT_B79_PBYTE_Pos)                       /*!< GPIO_PORT B79: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B80  -----------------------------------------
+#define GPIO_PORT_B80_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B80: PBYTE Position       */
+#define GPIO_PORT_B80_PBYTE_Msk                               (0x01UL << GPIO_PORT_B80_PBYTE_Pos)                       /*!< GPIO_PORT B80: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B81  -----------------------------------------
+#define GPIO_PORT_B81_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B81: PBYTE Position       */
+#define GPIO_PORT_B81_PBYTE_Msk                               (0x01UL << GPIO_PORT_B81_PBYTE_Pos)                       /*!< GPIO_PORT B81: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B82  -----------------------------------------
+#define GPIO_PORT_B82_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B82: PBYTE Position       */
+#define GPIO_PORT_B82_PBYTE_Msk                               (0x01UL << GPIO_PORT_B82_PBYTE_Pos)                       /*!< GPIO_PORT B82: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B83  -----------------------------------------
+#define GPIO_PORT_B83_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B83: PBYTE Position       */
+#define GPIO_PORT_B83_PBYTE_Msk                               (0x01UL << GPIO_PORT_B83_PBYTE_Pos)                       /*!< GPIO_PORT B83: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B84  -----------------------------------------
+#define GPIO_PORT_B84_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B84: PBYTE Position       */
+#define GPIO_PORT_B84_PBYTE_Msk                               (0x01UL << GPIO_PORT_B84_PBYTE_Pos)                       /*!< GPIO_PORT B84: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B85  -----------------------------------------
+#define GPIO_PORT_B85_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B85: PBYTE Position       */
+#define GPIO_PORT_B85_PBYTE_Msk                               (0x01UL << GPIO_PORT_B85_PBYTE_Pos)                       /*!< GPIO_PORT B85: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B86  -----------------------------------------
+#define GPIO_PORT_B86_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B86: PBYTE Position       */
+#define GPIO_PORT_B86_PBYTE_Msk                               (0x01UL << GPIO_PORT_B86_PBYTE_Pos)                       /*!< GPIO_PORT B86: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B87  -----------------------------------------
+#define GPIO_PORT_B87_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B87: PBYTE Position       */
+#define GPIO_PORT_B87_PBYTE_Msk                               (0x01UL << GPIO_PORT_B87_PBYTE_Pos)                       /*!< GPIO_PORT B87: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B88  -----------------------------------------
+#define GPIO_PORT_B88_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B88: PBYTE Position       */
+#define GPIO_PORT_B88_PBYTE_Msk                               (0x01UL << GPIO_PORT_B88_PBYTE_Pos)                       /*!< GPIO_PORT B88: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B89  -----------------------------------------
+#define GPIO_PORT_B89_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B89: PBYTE Position       */
+#define GPIO_PORT_B89_PBYTE_Msk                               (0x01UL << GPIO_PORT_B89_PBYTE_Pos)                       /*!< GPIO_PORT B89: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B90  -----------------------------------------
+#define GPIO_PORT_B90_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B90: PBYTE Position       */
+#define GPIO_PORT_B90_PBYTE_Msk                               (0x01UL << GPIO_PORT_B90_PBYTE_Pos)                       /*!< GPIO_PORT B90: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B91  -----------------------------------------
+#define GPIO_PORT_B91_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B91: PBYTE Position       */
+#define GPIO_PORT_B91_PBYTE_Msk                               (0x01UL << GPIO_PORT_B91_PBYTE_Pos)                       /*!< GPIO_PORT B91: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B92  -----------------------------------------
+#define GPIO_PORT_B92_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B92: PBYTE Position       */
+#define GPIO_PORT_B92_PBYTE_Msk                               (0x01UL << GPIO_PORT_B92_PBYTE_Pos)                       /*!< GPIO_PORT B92: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B93  -----------------------------------------
+#define GPIO_PORT_B93_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B93: PBYTE Position       */
+#define GPIO_PORT_B93_PBYTE_Msk                               (0x01UL << GPIO_PORT_B93_PBYTE_Pos)                       /*!< GPIO_PORT B93: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B94  -----------------------------------------
+#define GPIO_PORT_B94_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B94: PBYTE Position       */
+#define GPIO_PORT_B94_PBYTE_Msk                               (0x01UL << GPIO_PORT_B94_PBYTE_Pos)                       /*!< GPIO_PORT B94: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B95  -----------------------------------------
+#define GPIO_PORT_B95_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B95: PBYTE Position       */
+#define GPIO_PORT_B95_PBYTE_Msk                               (0x01UL << GPIO_PORT_B95_PBYTE_Pos)                       /*!< GPIO_PORT B95: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B96  -----------------------------------------
+#define GPIO_PORT_B96_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B96: PBYTE Position       */
+#define GPIO_PORT_B96_PBYTE_Msk                               (0x01UL << GPIO_PORT_B96_PBYTE_Pos)                       /*!< GPIO_PORT B96: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B97  -----------------------------------------
+#define GPIO_PORT_B97_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B97: PBYTE Position       */
+#define GPIO_PORT_B97_PBYTE_Msk                               (0x01UL << GPIO_PORT_B97_PBYTE_Pos)                       /*!< GPIO_PORT B97: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B98  -----------------------------------------
+#define GPIO_PORT_B98_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B98: PBYTE Position       */
+#define GPIO_PORT_B98_PBYTE_Msk                               (0x01UL << GPIO_PORT_B98_PBYTE_Pos)                       /*!< GPIO_PORT B98: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B99  -----------------------------------------
+#define GPIO_PORT_B99_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B99: PBYTE Position       */
+#define GPIO_PORT_B99_PBYTE_Msk                               (0x01UL << GPIO_PORT_B99_PBYTE_Pos)                       /*!< GPIO_PORT B99: PBYTE Mask           */
+
+// -------------------------------------  GPIO_PORT_B100  -----------------------------------------
+#define GPIO_PORT_B100_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B100: PBYTE Position      */
+#define GPIO_PORT_B100_PBYTE_Msk                              (0x01UL << GPIO_PORT_B100_PBYTE_Pos)                      /*!< GPIO_PORT B100: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B101  -----------------------------------------
+#define GPIO_PORT_B101_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B101: PBYTE Position      */
+#define GPIO_PORT_B101_PBYTE_Msk                              (0x01UL << GPIO_PORT_B101_PBYTE_Pos)                      /*!< GPIO_PORT B101: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B102  -----------------------------------------
+#define GPIO_PORT_B102_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B102: PBYTE Position      */
+#define GPIO_PORT_B102_PBYTE_Msk                              (0x01UL << GPIO_PORT_B102_PBYTE_Pos)                      /*!< GPIO_PORT B102: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B103  -----------------------------------------
+#define GPIO_PORT_B103_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B103: PBYTE Position      */
+#define GPIO_PORT_B103_PBYTE_Msk                              (0x01UL << GPIO_PORT_B103_PBYTE_Pos)                      /*!< GPIO_PORT B103: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B104  -----------------------------------------
+#define GPIO_PORT_B104_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B104: PBYTE Position      */
+#define GPIO_PORT_B104_PBYTE_Msk                              (0x01UL << GPIO_PORT_B104_PBYTE_Pos)                      /*!< GPIO_PORT B104: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B105  -----------------------------------------
+#define GPIO_PORT_B105_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B105: PBYTE Position      */
+#define GPIO_PORT_B105_PBYTE_Msk                              (0x01UL << GPIO_PORT_B105_PBYTE_Pos)                      /*!< GPIO_PORT B105: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B106  -----------------------------------------
+#define GPIO_PORT_B106_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B106: PBYTE Position      */
+#define GPIO_PORT_B106_PBYTE_Msk                              (0x01UL << GPIO_PORT_B106_PBYTE_Pos)                      /*!< GPIO_PORT B106: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B107  -----------------------------------------
+#define GPIO_PORT_B107_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B107: PBYTE Position      */
+#define GPIO_PORT_B107_PBYTE_Msk                              (0x01UL << GPIO_PORT_B107_PBYTE_Pos)                      /*!< GPIO_PORT B107: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B108  -----------------------------------------
+#define GPIO_PORT_B108_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B108: PBYTE Position      */
+#define GPIO_PORT_B108_PBYTE_Msk                              (0x01UL << GPIO_PORT_B108_PBYTE_Pos)                      /*!< GPIO_PORT B108: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B109  -----------------------------------------
+#define GPIO_PORT_B109_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B109: PBYTE Position      */
+#define GPIO_PORT_B109_PBYTE_Msk                              (0x01UL << GPIO_PORT_B109_PBYTE_Pos)                      /*!< GPIO_PORT B109: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B110  -----------------------------------------
+#define GPIO_PORT_B110_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B110: PBYTE Position      */
+#define GPIO_PORT_B110_PBYTE_Msk                              (0x01UL << GPIO_PORT_B110_PBYTE_Pos)                      /*!< GPIO_PORT B110: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B111  -----------------------------------------
+#define GPIO_PORT_B111_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B111: PBYTE Position      */
+#define GPIO_PORT_B111_PBYTE_Msk                              (0x01UL << GPIO_PORT_B111_PBYTE_Pos)                      /*!< GPIO_PORT B111: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B112  -----------------------------------------
+#define GPIO_PORT_B112_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B112: PBYTE Position      */
+#define GPIO_PORT_B112_PBYTE_Msk                              (0x01UL << GPIO_PORT_B112_PBYTE_Pos)                      /*!< GPIO_PORT B112: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B113  -----------------------------------------
+#define GPIO_PORT_B113_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B113: PBYTE Position      */
+#define GPIO_PORT_B113_PBYTE_Msk                              (0x01UL << GPIO_PORT_B113_PBYTE_Pos)                      /*!< GPIO_PORT B113: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B114  -----------------------------------------
+#define GPIO_PORT_B114_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B114: PBYTE Position      */
+#define GPIO_PORT_B114_PBYTE_Msk                              (0x01UL << GPIO_PORT_B114_PBYTE_Pos)                      /*!< GPIO_PORT B114: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B115  -----------------------------------------
+#define GPIO_PORT_B115_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B115: PBYTE Position      */
+#define GPIO_PORT_B115_PBYTE_Msk                              (0x01UL << GPIO_PORT_B115_PBYTE_Pos)                      /*!< GPIO_PORT B115: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B116  -----------------------------------------
+#define GPIO_PORT_B116_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B116: PBYTE Position      */
+#define GPIO_PORT_B116_PBYTE_Msk                              (0x01UL << GPIO_PORT_B116_PBYTE_Pos)                      /*!< GPIO_PORT B116: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B117  -----------------------------------------
+#define GPIO_PORT_B117_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B117: PBYTE Position      */
+#define GPIO_PORT_B117_PBYTE_Msk                              (0x01UL << GPIO_PORT_B117_PBYTE_Pos)                      /*!< GPIO_PORT B117: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B118  -----------------------------------------
+#define GPIO_PORT_B118_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B118: PBYTE Position      */
+#define GPIO_PORT_B118_PBYTE_Msk                              (0x01UL << GPIO_PORT_B118_PBYTE_Pos)                      /*!< GPIO_PORT B118: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B119  -----------------------------------------
+#define GPIO_PORT_B119_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B119: PBYTE Position      */
+#define GPIO_PORT_B119_PBYTE_Msk                              (0x01UL << GPIO_PORT_B119_PBYTE_Pos)                      /*!< GPIO_PORT B119: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B120  -----------------------------------------
+#define GPIO_PORT_B120_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B120: PBYTE Position      */
+#define GPIO_PORT_B120_PBYTE_Msk                              (0x01UL << GPIO_PORT_B120_PBYTE_Pos)                      /*!< GPIO_PORT B120: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B121  -----------------------------------------
+#define GPIO_PORT_B121_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B121: PBYTE Position      */
+#define GPIO_PORT_B121_PBYTE_Msk                              (0x01UL << GPIO_PORT_B121_PBYTE_Pos)                      /*!< GPIO_PORT B121: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B122  -----------------------------------------
+#define GPIO_PORT_B122_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B122: PBYTE Position      */
+#define GPIO_PORT_B122_PBYTE_Msk                              (0x01UL << GPIO_PORT_B122_PBYTE_Pos)                      /*!< GPIO_PORT B122: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B123  -----------------------------------------
+#define GPIO_PORT_B123_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B123: PBYTE Position      */
+#define GPIO_PORT_B123_PBYTE_Msk                              (0x01UL << GPIO_PORT_B123_PBYTE_Pos)                      /*!< GPIO_PORT B123: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B124  -----------------------------------------
+#define GPIO_PORT_B124_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B124: PBYTE Position      */
+#define GPIO_PORT_B124_PBYTE_Msk                              (0x01UL << GPIO_PORT_B124_PBYTE_Pos)                      /*!< GPIO_PORT B124: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B125  -----------------------------------------
+#define GPIO_PORT_B125_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B125: PBYTE Position      */
+#define GPIO_PORT_B125_PBYTE_Msk                              (0x01UL << GPIO_PORT_B125_PBYTE_Pos)                      /*!< GPIO_PORT B125: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B126  -----------------------------------------
+#define GPIO_PORT_B126_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B126: PBYTE Position      */
+#define GPIO_PORT_B126_PBYTE_Msk                              (0x01UL << GPIO_PORT_B126_PBYTE_Pos)                      /*!< GPIO_PORT B126: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B127  -----------------------------------------
+#define GPIO_PORT_B127_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B127: PBYTE Position      */
+#define GPIO_PORT_B127_PBYTE_Msk                              (0x01UL << GPIO_PORT_B127_PBYTE_Pos)                      /*!< GPIO_PORT B127: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B128  -----------------------------------------
+#define GPIO_PORT_B128_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B128: PBYTE Position      */
+#define GPIO_PORT_B128_PBYTE_Msk                              (0x01UL << GPIO_PORT_B128_PBYTE_Pos)                      /*!< GPIO_PORT B128: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B129  -----------------------------------------
+#define GPIO_PORT_B129_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B129: PBYTE Position      */
+#define GPIO_PORT_B129_PBYTE_Msk                              (0x01UL << GPIO_PORT_B129_PBYTE_Pos)                      /*!< GPIO_PORT B129: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B130  -----------------------------------------
+#define GPIO_PORT_B130_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B130: PBYTE Position      */
+#define GPIO_PORT_B130_PBYTE_Msk                              (0x01UL << GPIO_PORT_B130_PBYTE_Pos)                      /*!< GPIO_PORT B130: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B131  -----------------------------------------
+#define GPIO_PORT_B131_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B131: PBYTE Position      */
+#define GPIO_PORT_B131_PBYTE_Msk                              (0x01UL << GPIO_PORT_B131_PBYTE_Pos)                      /*!< GPIO_PORT B131: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B132  -----------------------------------------
+#define GPIO_PORT_B132_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B132: PBYTE Position      */
+#define GPIO_PORT_B132_PBYTE_Msk                              (0x01UL << GPIO_PORT_B132_PBYTE_Pos)                      /*!< GPIO_PORT B132: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B133  -----------------------------------------
+#define GPIO_PORT_B133_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B133: PBYTE Position      */
+#define GPIO_PORT_B133_PBYTE_Msk                              (0x01UL << GPIO_PORT_B133_PBYTE_Pos)                      /*!< GPIO_PORT B133: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B134  -----------------------------------------
+#define GPIO_PORT_B134_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B134: PBYTE Position      */
+#define GPIO_PORT_B134_PBYTE_Msk                              (0x01UL << GPIO_PORT_B134_PBYTE_Pos)                      /*!< GPIO_PORT B134: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B135  -----------------------------------------
+#define GPIO_PORT_B135_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B135: PBYTE Position      */
+#define GPIO_PORT_B135_PBYTE_Msk                              (0x01UL << GPIO_PORT_B135_PBYTE_Pos)                      /*!< GPIO_PORT B135: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B136  -----------------------------------------
+#define GPIO_PORT_B136_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B136: PBYTE Position      */
+#define GPIO_PORT_B136_PBYTE_Msk                              (0x01UL << GPIO_PORT_B136_PBYTE_Pos)                      /*!< GPIO_PORT B136: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B137  -----------------------------------------
+#define GPIO_PORT_B137_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B137: PBYTE Position      */
+#define GPIO_PORT_B137_PBYTE_Msk                              (0x01UL << GPIO_PORT_B137_PBYTE_Pos)                      /*!< GPIO_PORT B137: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B138  -----------------------------------------
+#define GPIO_PORT_B138_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B138: PBYTE Position      */
+#define GPIO_PORT_B138_PBYTE_Msk                              (0x01UL << GPIO_PORT_B138_PBYTE_Pos)                      /*!< GPIO_PORT B138: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B139  -----------------------------------------
+#define GPIO_PORT_B139_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B139: PBYTE Position      */
+#define GPIO_PORT_B139_PBYTE_Msk                              (0x01UL << GPIO_PORT_B139_PBYTE_Pos)                      /*!< GPIO_PORT B139: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B140  -----------------------------------------
+#define GPIO_PORT_B140_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B140: PBYTE Position      */
+#define GPIO_PORT_B140_PBYTE_Msk                              (0x01UL << GPIO_PORT_B140_PBYTE_Pos)                      /*!< GPIO_PORT B140: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B141  -----------------------------------------
+#define GPIO_PORT_B141_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B141: PBYTE Position      */
+#define GPIO_PORT_B141_PBYTE_Msk                              (0x01UL << GPIO_PORT_B141_PBYTE_Pos)                      /*!< GPIO_PORT B141: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B142  -----------------------------------------
+#define GPIO_PORT_B142_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B142: PBYTE Position      */
+#define GPIO_PORT_B142_PBYTE_Msk                              (0x01UL << GPIO_PORT_B142_PBYTE_Pos)                      /*!< GPIO_PORT B142: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B143  -----------------------------------------
+#define GPIO_PORT_B143_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B143: PBYTE Position      */
+#define GPIO_PORT_B143_PBYTE_Msk                              (0x01UL << GPIO_PORT_B143_PBYTE_Pos)                      /*!< GPIO_PORT B143: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B144  -----------------------------------------
+#define GPIO_PORT_B144_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B144: PBYTE Position      */
+#define GPIO_PORT_B144_PBYTE_Msk                              (0x01UL << GPIO_PORT_B144_PBYTE_Pos)                      /*!< GPIO_PORT B144: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B145  -----------------------------------------
+#define GPIO_PORT_B145_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B145: PBYTE Position      */
+#define GPIO_PORT_B145_PBYTE_Msk                              (0x01UL << GPIO_PORT_B145_PBYTE_Pos)                      /*!< GPIO_PORT B145: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B146  -----------------------------------------
+#define GPIO_PORT_B146_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B146: PBYTE Position      */
+#define GPIO_PORT_B146_PBYTE_Msk                              (0x01UL << GPIO_PORT_B146_PBYTE_Pos)                      /*!< GPIO_PORT B146: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B147  -----------------------------------------
+#define GPIO_PORT_B147_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B147: PBYTE Position      */
+#define GPIO_PORT_B147_PBYTE_Msk                              (0x01UL << GPIO_PORT_B147_PBYTE_Pos)                      /*!< GPIO_PORT B147: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B148  -----------------------------------------
+#define GPIO_PORT_B148_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B148: PBYTE Position      */
+#define GPIO_PORT_B148_PBYTE_Msk                              (0x01UL << GPIO_PORT_B148_PBYTE_Pos)                      /*!< GPIO_PORT B148: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B149  -----------------------------------------
+#define GPIO_PORT_B149_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B149: PBYTE Position      */
+#define GPIO_PORT_B149_PBYTE_Msk                              (0x01UL << GPIO_PORT_B149_PBYTE_Pos)                      /*!< GPIO_PORT B149: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B150  -----------------------------------------
+#define GPIO_PORT_B150_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B150: PBYTE Position      */
+#define GPIO_PORT_B150_PBYTE_Msk                              (0x01UL << GPIO_PORT_B150_PBYTE_Pos)                      /*!< GPIO_PORT B150: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B151  -----------------------------------------
+#define GPIO_PORT_B151_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B151: PBYTE Position      */
+#define GPIO_PORT_B151_PBYTE_Msk                              (0x01UL << GPIO_PORT_B151_PBYTE_Pos)                      /*!< GPIO_PORT B151: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B152  -----------------------------------------
+#define GPIO_PORT_B152_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B152: PBYTE Position      */
+#define GPIO_PORT_B152_PBYTE_Msk                              (0x01UL << GPIO_PORT_B152_PBYTE_Pos)                      /*!< GPIO_PORT B152: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B153  -----------------------------------------
+#define GPIO_PORT_B153_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B153: PBYTE Position      */
+#define GPIO_PORT_B153_PBYTE_Msk                              (0x01UL << GPIO_PORT_B153_PBYTE_Pos)                      /*!< GPIO_PORT B153: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B154  -----------------------------------------
+#define GPIO_PORT_B154_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B154: PBYTE Position      */
+#define GPIO_PORT_B154_PBYTE_Msk                              (0x01UL << GPIO_PORT_B154_PBYTE_Pos)                      /*!< GPIO_PORT B154: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B155  -----------------------------------------
+#define GPIO_PORT_B155_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B155: PBYTE Position      */
+#define GPIO_PORT_B155_PBYTE_Msk                              (0x01UL << GPIO_PORT_B155_PBYTE_Pos)                      /*!< GPIO_PORT B155: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B156  -----------------------------------------
+#define GPIO_PORT_B156_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B156: PBYTE Position      */
+#define GPIO_PORT_B156_PBYTE_Msk                              (0x01UL << GPIO_PORT_B156_PBYTE_Pos)                      /*!< GPIO_PORT B156: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B157  -----------------------------------------
+#define GPIO_PORT_B157_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B157: PBYTE Position      */
+#define GPIO_PORT_B157_PBYTE_Msk                              (0x01UL << GPIO_PORT_B157_PBYTE_Pos)                      /*!< GPIO_PORT B157: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B158  -----------------------------------------
+#define GPIO_PORT_B158_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B158: PBYTE Position      */
+#define GPIO_PORT_B158_PBYTE_Msk                              (0x01UL << GPIO_PORT_B158_PBYTE_Pos)                      /*!< GPIO_PORT B158: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B159  -----------------------------------------
+#define GPIO_PORT_B159_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B159: PBYTE Position      */
+#define GPIO_PORT_B159_PBYTE_Msk                              (0x01UL << GPIO_PORT_B159_PBYTE_Pos)                      /*!< GPIO_PORT B159: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B160  -----------------------------------------
+#define GPIO_PORT_B160_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B160: PBYTE Position      */
+#define GPIO_PORT_B160_PBYTE_Msk                              (0x01UL << GPIO_PORT_B160_PBYTE_Pos)                      /*!< GPIO_PORT B160: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B161  -----------------------------------------
+#define GPIO_PORT_B161_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B161: PBYTE Position      */
+#define GPIO_PORT_B161_PBYTE_Msk                              (0x01UL << GPIO_PORT_B161_PBYTE_Pos)                      /*!< GPIO_PORT B161: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B162  -----------------------------------------
+#define GPIO_PORT_B162_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B162: PBYTE Position      */
+#define GPIO_PORT_B162_PBYTE_Msk                              (0x01UL << GPIO_PORT_B162_PBYTE_Pos)                      /*!< GPIO_PORT B162: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B163  -----------------------------------------
+#define GPIO_PORT_B163_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B163: PBYTE Position      */
+#define GPIO_PORT_B163_PBYTE_Msk                              (0x01UL << GPIO_PORT_B163_PBYTE_Pos)                      /*!< GPIO_PORT B163: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B164  -----------------------------------------
+#define GPIO_PORT_B164_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B164: PBYTE Position      */
+#define GPIO_PORT_B164_PBYTE_Msk                              (0x01UL << GPIO_PORT_B164_PBYTE_Pos)                      /*!< GPIO_PORT B164: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B165  -----------------------------------------
+#define GPIO_PORT_B165_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B165: PBYTE Position      */
+#define GPIO_PORT_B165_PBYTE_Msk                              (0x01UL << GPIO_PORT_B165_PBYTE_Pos)                      /*!< GPIO_PORT B165: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B166  -----------------------------------------
+#define GPIO_PORT_B166_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B166: PBYTE Position      */
+#define GPIO_PORT_B166_PBYTE_Msk                              (0x01UL << GPIO_PORT_B166_PBYTE_Pos)                      /*!< GPIO_PORT B166: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B167  -----------------------------------------
+#define GPIO_PORT_B167_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B167: PBYTE Position      */
+#define GPIO_PORT_B167_PBYTE_Msk                              (0x01UL << GPIO_PORT_B167_PBYTE_Pos)                      /*!< GPIO_PORT B167: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B168  -----------------------------------------
+#define GPIO_PORT_B168_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B168: PBYTE Position      */
+#define GPIO_PORT_B168_PBYTE_Msk                              (0x01UL << GPIO_PORT_B168_PBYTE_Pos)                      /*!< GPIO_PORT B168: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B169  -----------------------------------------
+#define GPIO_PORT_B169_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B169: PBYTE Position      */
+#define GPIO_PORT_B169_PBYTE_Msk                              (0x01UL << GPIO_PORT_B169_PBYTE_Pos)                      /*!< GPIO_PORT B169: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B170  -----------------------------------------
+#define GPIO_PORT_B170_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B170: PBYTE Position      */
+#define GPIO_PORT_B170_PBYTE_Msk                              (0x01UL << GPIO_PORT_B170_PBYTE_Pos)                      /*!< GPIO_PORT B170: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B171  -----------------------------------------
+#define GPIO_PORT_B171_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B171: PBYTE Position      */
+#define GPIO_PORT_B171_PBYTE_Msk                              (0x01UL << GPIO_PORT_B171_PBYTE_Pos)                      /*!< GPIO_PORT B171: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B172  -----------------------------------------
+#define GPIO_PORT_B172_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B172: PBYTE Position      */
+#define GPIO_PORT_B172_PBYTE_Msk                              (0x01UL << GPIO_PORT_B172_PBYTE_Pos)                      /*!< GPIO_PORT B172: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B173  -----------------------------------------
+#define GPIO_PORT_B173_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B173: PBYTE Position      */
+#define GPIO_PORT_B173_PBYTE_Msk                              (0x01UL << GPIO_PORT_B173_PBYTE_Pos)                      /*!< GPIO_PORT B173: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B174  -----------------------------------------
+#define GPIO_PORT_B174_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B174: PBYTE Position      */
+#define GPIO_PORT_B174_PBYTE_Msk                              (0x01UL << GPIO_PORT_B174_PBYTE_Pos)                      /*!< GPIO_PORT B174: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B175  -----------------------------------------
+#define GPIO_PORT_B175_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B175: PBYTE Position      */
+#define GPIO_PORT_B175_PBYTE_Msk                              (0x01UL << GPIO_PORT_B175_PBYTE_Pos)                      /*!< GPIO_PORT B175: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B176  -----------------------------------------
+#define GPIO_PORT_B176_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B176: PBYTE Position      */
+#define GPIO_PORT_B176_PBYTE_Msk                              (0x01UL << GPIO_PORT_B176_PBYTE_Pos)                      /*!< GPIO_PORT B176: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B177  -----------------------------------------
+#define GPIO_PORT_B177_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B177: PBYTE Position      */
+#define GPIO_PORT_B177_PBYTE_Msk                              (0x01UL << GPIO_PORT_B177_PBYTE_Pos)                      /*!< GPIO_PORT B177: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B178  -----------------------------------------
+#define GPIO_PORT_B178_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B178: PBYTE Position      */
+#define GPIO_PORT_B178_PBYTE_Msk                              (0x01UL << GPIO_PORT_B178_PBYTE_Pos)                      /*!< GPIO_PORT B178: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B179  -----------------------------------------
+#define GPIO_PORT_B179_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B179: PBYTE Position      */
+#define GPIO_PORT_B179_PBYTE_Msk                              (0x01UL << GPIO_PORT_B179_PBYTE_Pos)                      /*!< GPIO_PORT B179: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B180  -----------------------------------------
+#define GPIO_PORT_B180_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B180: PBYTE Position      */
+#define GPIO_PORT_B180_PBYTE_Msk                              (0x01UL << GPIO_PORT_B180_PBYTE_Pos)                      /*!< GPIO_PORT B180: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B181  -----------------------------------------
+#define GPIO_PORT_B181_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B181: PBYTE Position      */
+#define GPIO_PORT_B181_PBYTE_Msk                              (0x01UL << GPIO_PORT_B181_PBYTE_Pos)                      /*!< GPIO_PORT B181: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B182  -----------------------------------------
+#define GPIO_PORT_B182_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B182: PBYTE Position      */
+#define GPIO_PORT_B182_PBYTE_Msk                              (0x01UL << GPIO_PORT_B182_PBYTE_Pos)                      /*!< GPIO_PORT B182: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B183  -----------------------------------------
+#define GPIO_PORT_B183_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B183: PBYTE Position      */
+#define GPIO_PORT_B183_PBYTE_Msk                              (0x01UL << GPIO_PORT_B183_PBYTE_Pos)                      /*!< GPIO_PORT B183: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B184  -----------------------------------------
+#define GPIO_PORT_B184_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B184: PBYTE Position      */
+#define GPIO_PORT_B184_PBYTE_Msk                              (0x01UL << GPIO_PORT_B184_PBYTE_Pos)                      /*!< GPIO_PORT B184: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B185  -----------------------------------------
+#define GPIO_PORT_B185_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B185: PBYTE Position      */
+#define GPIO_PORT_B185_PBYTE_Msk                              (0x01UL << GPIO_PORT_B185_PBYTE_Pos)                      /*!< GPIO_PORT B185: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B186  -----------------------------------------
+#define GPIO_PORT_B186_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B186: PBYTE Position      */
+#define GPIO_PORT_B186_PBYTE_Msk                              (0x01UL << GPIO_PORT_B186_PBYTE_Pos)                      /*!< GPIO_PORT B186: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B187  -----------------------------------------
+#define GPIO_PORT_B187_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B187: PBYTE Position      */
+#define GPIO_PORT_B187_PBYTE_Msk                              (0x01UL << GPIO_PORT_B187_PBYTE_Pos)                      /*!< GPIO_PORT B187: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B188  -----------------------------------------
+#define GPIO_PORT_B188_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B188: PBYTE Position      */
+#define GPIO_PORT_B188_PBYTE_Msk                              (0x01UL << GPIO_PORT_B188_PBYTE_Pos)                      /*!< GPIO_PORT B188: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B189  -----------------------------------------
+#define GPIO_PORT_B189_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B189: PBYTE Position      */
+#define GPIO_PORT_B189_PBYTE_Msk                              (0x01UL << GPIO_PORT_B189_PBYTE_Pos)                      /*!< GPIO_PORT B189: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B190  -----------------------------------------
+#define GPIO_PORT_B190_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B190: PBYTE Position      */
+#define GPIO_PORT_B190_PBYTE_Msk                              (0x01UL << GPIO_PORT_B190_PBYTE_Pos)                      /*!< GPIO_PORT B190: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B191  -----------------------------------------
+#define GPIO_PORT_B191_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B191: PBYTE Position      */
+#define GPIO_PORT_B191_PBYTE_Msk                              (0x01UL << GPIO_PORT_B191_PBYTE_Pos)                      /*!< GPIO_PORT B191: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B192  -----------------------------------------
+#define GPIO_PORT_B192_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B192: PBYTE Position      */
+#define GPIO_PORT_B192_PBYTE_Msk                              (0x01UL << GPIO_PORT_B192_PBYTE_Pos)                      /*!< GPIO_PORT B192: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B193  -----------------------------------------
+#define GPIO_PORT_B193_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B193: PBYTE Position      */
+#define GPIO_PORT_B193_PBYTE_Msk                              (0x01UL << GPIO_PORT_B193_PBYTE_Pos)                      /*!< GPIO_PORT B193: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B194  -----------------------------------------
+#define GPIO_PORT_B194_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B194: PBYTE Position      */
+#define GPIO_PORT_B194_PBYTE_Msk                              (0x01UL << GPIO_PORT_B194_PBYTE_Pos)                      /*!< GPIO_PORT B194: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B195  -----------------------------------------
+#define GPIO_PORT_B195_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B195: PBYTE Position      */
+#define GPIO_PORT_B195_PBYTE_Msk                              (0x01UL << GPIO_PORT_B195_PBYTE_Pos)                      /*!< GPIO_PORT B195: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B196  -----------------------------------------
+#define GPIO_PORT_B196_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B196: PBYTE Position      */
+#define GPIO_PORT_B196_PBYTE_Msk                              (0x01UL << GPIO_PORT_B196_PBYTE_Pos)                      /*!< GPIO_PORT B196: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B197  -----------------------------------------
+#define GPIO_PORT_B197_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B197: PBYTE Position      */
+#define GPIO_PORT_B197_PBYTE_Msk                              (0x01UL << GPIO_PORT_B197_PBYTE_Pos)                      /*!< GPIO_PORT B197: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B198  -----------------------------------------
+#define GPIO_PORT_B198_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B198: PBYTE Position      */
+#define GPIO_PORT_B198_PBYTE_Msk                              (0x01UL << GPIO_PORT_B198_PBYTE_Pos)                      /*!< GPIO_PORT B198: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B199  -----------------------------------------
+#define GPIO_PORT_B199_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B199: PBYTE Position      */
+#define GPIO_PORT_B199_PBYTE_Msk                              (0x01UL << GPIO_PORT_B199_PBYTE_Pos)                      /*!< GPIO_PORT B199: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B200  -----------------------------------------
+#define GPIO_PORT_B200_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B200: PBYTE Position      */
+#define GPIO_PORT_B200_PBYTE_Msk                              (0x01UL << GPIO_PORT_B200_PBYTE_Pos)                      /*!< GPIO_PORT B200: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B201  -----------------------------------------
+#define GPIO_PORT_B201_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B201: PBYTE Position      */
+#define GPIO_PORT_B201_PBYTE_Msk                              (0x01UL << GPIO_PORT_B201_PBYTE_Pos)                      /*!< GPIO_PORT B201: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B202  -----------------------------------------
+#define GPIO_PORT_B202_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B202: PBYTE Position      */
+#define GPIO_PORT_B202_PBYTE_Msk                              (0x01UL << GPIO_PORT_B202_PBYTE_Pos)                      /*!< GPIO_PORT B202: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B203  -----------------------------------------
+#define GPIO_PORT_B203_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B203: PBYTE Position      */
+#define GPIO_PORT_B203_PBYTE_Msk                              (0x01UL << GPIO_PORT_B203_PBYTE_Pos)                      /*!< GPIO_PORT B203: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B204  -----------------------------------------
+#define GPIO_PORT_B204_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B204: PBYTE Position      */
+#define GPIO_PORT_B204_PBYTE_Msk                              (0x01UL << GPIO_PORT_B204_PBYTE_Pos)                      /*!< GPIO_PORT B204: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B205  -----------------------------------------
+#define GPIO_PORT_B205_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B205: PBYTE Position      */
+#define GPIO_PORT_B205_PBYTE_Msk                              (0x01UL << GPIO_PORT_B205_PBYTE_Pos)                      /*!< GPIO_PORT B205: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B206  -----------------------------------------
+#define GPIO_PORT_B206_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B206: PBYTE Position      */
+#define GPIO_PORT_B206_PBYTE_Msk                              (0x01UL << GPIO_PORT_B206_PBYTE_Pos)                      /*!< GPIO_PORT B206: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B207  -----------------------------------------
+#define GPIO_PORT_B207_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B207: PBYTE Position      */
+#define GPIO_PORT_B207_PBYTE_Msk                              (0x01UL << GPIO_PORT_B207_PBYTE_Pos)                      /*!< GPIO_PORT B207: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B208  -----------------------------------------
+#define GPIO_PORT_B208_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B208: PBYTE Position      */
+#define GPIO_PORT_B208_PBYTE_Msk                              (0x01UL << GPIO_PORT_B208_PBYTE_Pos)                      /*!< GPIO_PORT B208: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B209  -----------------------------------------
+#define GPIO_PORT_B209_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B209: PBYTE Position      */
+#define GPIO_PORT_B209_PBYTE_Msk                              (0x01UL << GPIO_PORT_B209_PBYTE_Pos)                      /*!< GPIO_PORT B209: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B210  -----------------------------------------
+#define GPIO_PORT_B210_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B210: PBYTE Position      */
+#define GPIO_PORT_B210_PBYTE_Msk                              (0x01UL << GPIO_PORT_B210_PBYTE_Pos)                      /*!< GPIO_PORT B210: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B211  -----------------------------------------
+#define GPIO_PORT_B211_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B211: PBYTE Position      */
+#define GPIO_PORT_B211_PBYTE_Msk                              (0x01UL << GPIO_PORT_B211_PBYTE_Pos)                      /*!< GPIO_PORT B211: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B212  -----------------------------------------
+#define GPIO_PORT_B212_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B212: PBYTE Position      */
+#define GPIO_PORT_B212_PBYTE_Msk                              (0x01UL << GPIO_PORT_B212_PBYTE_Pos)                      /*!< GPIO_PORT B212: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B213  -----------------------------------------
+#define GPIO_PORT_B213_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B213: PBYTE Position      */
+#define GPIO_PORT_B213_PBYTE_Msk                              (0x01UL << GPIO_PORT_B213_PBYTE_Pos)                      /*!< GPIO_PORT B213: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B214  -----------------------------------------
+#define GPIO_PORT_B214_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B214: PBYTE Position      */
+#define GPIO_PORT_B214_PBYTE_Msk                              (0x01UL << GPIO_PORT_B214_PBYTE_Pos)                      /*!< GPIO_PORT B214: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B215  -----------------------------------------
+#define GPIO_PORT_B215_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B215: PBYTE Position      */
+#define GPIO_PORT_B215_PBYTE_Msk                              (0x01UL << GPIO_PORT_B215_PBYTE_Pos)                      /*!< GPIO_PORT B215: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B216  -----------------------------------------
+#define GPIO_PORT_B216_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B216: PBYTE Position      */
+#define GPIO_PORT_B216_PBYTE_Msk                              (0x01UL << GPIO_PORT_B216_PBYTE_Pos)                      /*!< GPIO_PORT B216: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B217  -----------------------------------------
+#define GPIO_PORT_B217_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B217: PBYTE Position      */
+#define GPIO_PORT_B217_PBYTE_Msk                              (0x01UL << GPIO_PORT_B217_PBYTE_Pos)                      /*!< GPIO_PORT B217: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B218  -----------------------------------------
+#define GPIO_PORT_B218_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B218: PBYTE Position      */
+#define GPIO_PORT_B218_PBYTE_Msk                              (0x01UL << GPIO_PORT_B218_PBYTE_Pos)                      /*!< GPIO_PORT B218: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B219  -----------------------------------------
+#define GPIO_PORT_B219_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B219: PBYTE Position      */
+#define GPIO_PORT_B219_PBYTE_Msk                              (0x01UL << GPIO_PORT_B219_PBYTE_Pos)                      /*!< GPIO_PORT B219: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B220  -----------------------------------------
+#define GPIO_PORT_B220_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B220: PBYTE Position      */
+#define GPIO_PORT_B220_PBYTE_Msk                              (0x01UL << GPIO_PORT_B220_PBYTE_Pos)                      /*!< GPIO_PORT B220: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B221  -----------------------------------------
+#define GPIO_PORT_B221_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B221: PBYTE Position      */
+#define GPIO_PORT_B221_PBYTE_Msk                              (0x01UL << GPIO_PORT_B221_PBYTE_Pos)                      /*!< GPIO_PORT B221: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B222  -----------------------------------------
+#define GPIO_PORT_B222_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B222: PBYTE Position      */
+#define GPIO_PORT_B222_PBYTE_Msk                              (0x01UL << GPIO_PORT_B222_PBYTE_Pos)                      /*!< GPIO_PORT B222: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B223  -----------------------------------------
+#define GPIO_PORT_B223_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B223: PBYTE Position      */
+#define GPIO_PORT_B223_PBYTE_Msk                              (0x01UL << GPIO_PORT_B223_PBYTE_Pos)                      /*!< GPIO_PORT B223: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B224  -----------------------------------------
+#define GPIO_PORT_B224_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B224: PBYTE Position      */
+#define GPIO_PORT_B224_PBYTE_Msk                              (0x01UL << GPIO_PORT_B224_PBYTE_Pos)                      /*!< GPIO_PORT B224: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B225  -----------------------------------------
+#define GPIO_PORT_B225_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B225: PBYTE Position      */
+#define GPIO_PORT_B225_PBYTE_Msk                              (0x01UL << GPIO_PORT_B225_PBYTE_Pos)                      /*!< GPIO_PORT B225: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B226  -----------------------------------------
+#define GPIO_PORT_B226_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B226: PBYTE Position      */
+#define GPIO_PORT_B226_PBYTE_Msk                              (0x01UL << GPIO_PORT_B226_PBYTE_Pos)                      /*!< GPIO_PORT B226: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B227  -----------------------------------------
+#define GPIO_PORT_B227_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B227: PBYTE Position      */
+#define GPIO_PORT_B227_PBYTE_Msk                              (0x01UL << GPIO_PORT_B227_PBYTE_Pos)                      /*!< GPIO_PORT B227: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B228  -----------------------------------------
+#define GPIO_PORT_B228_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B228: PBYTE Position      */
+#define GPIO_PORT_B228_PBYTE_Msk                              (0x01UL << GPIO_PORT_B228_PBYTE_Pos)                      /*!< GPIO_PORT B228: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B229  -----------------------------------------
+#define GPIO_PORT_B229_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B229: PBYTE Position      */
+#define GPIO_PORT_B229_PBYTE_Msk                              (0x01UL << GPIO_PORT_B229_PBYTE_Pos)                      /*!< GPIO_PORT B229: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B230  -----------------------------------------
+#define GPIO_PORT_B230_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B230: PBYTE Position      */
+#define GPIO_PORT_B230_PBYTE_Msk                              (0x01UL << GPIO_PORT_B230_PBYTE_Pos)                      /*!< GPIO_PORT B230: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B231  -----------------------------------------
+#define GPIO_PORT_B231_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B231: PBYTE Position      */
+#define GPIO_PORT_B231_PBYTE_Msk                              (0x01UL << GPIO_PORT_B231_PBYTE_Pos)                      /*!< GPIO_PORT B231: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B232  -----------------------------------------
+#define GPIO_PORT_B232_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B232: PBYTE Position      */
+#define GPIO_PORT_B232_PBYTE_Msk                              (0x01UL << GPIO_PORT_B232_PBYTE_Pos)                      /*!< GPIO_PORT B232: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B233  -----------------------------------------
+#define GPIO_PORT_B233_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B233: PBYTE Position      */
+#define GPIO_PORT_B233_PBYTE_Msk                              (0x01UL << GPIO_PORT_B233_PBYTE_Pos)                      /*!< GPIO_PORT B233: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B234  -----------------------------------------
+#define GPIO_PORT_B234_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B234: PBYTE Position      */
+#define GPIO_PORT_B234_PBYTE_Msk                              (0x01UL << GPIO_PORT_B234_PBYTE_Pos)                      /*!< GPIO_PORT B234: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B235  -----------------------------------------
+#define GPIO_PORT_B235_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B235: PBYTE Position      */
+#define GPIO_PORT_B235_PBYTE_Msk                              (0x01UL << GPIO_PORT_B235_PBYTE_Pos)                      /*!< GPIO_PORT B235: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B236  -----------------------------------------
+#define GPIO_PORT_B236_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B236: PBYTE Position      */
+#define GPIO_PORT_B236_PBYTE_Msk                              (0x01UL << GPIO_PORT_B236_PBYTE_Pos)                      /*!< GPIO_PORT B236: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B237  -----------------------------------------
+#define GPIO_PORT_B237_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B237: PBYTE Position      */
+#define GPIO_PORT_B237_PBYTE_Msk                              (0x01UL << GPIO_PORT_B237_PBYTE_Pos)                      /*!< GPIO_PORT B237: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B238  -----------------------------------------
+#define GPIO_PORT_B238_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B238: PBYTE Position      */
+#define GPIO_PORT_B238_PBYTE_Msk                              (0x01UL << GPIO_PORT_B238_PBYTE_Pos)                      /*!< GPIO_PORT B238: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B239  -----------------------------------------
+#define GPIO_PORT_B239_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B239: PBYTE Position      */
+#define GPIO_PORT_B239_PBYTE_Msk                              (0x01UL << GPIO_PORT_B239_PBYTE_Pos)                      /*!< GPIO_PORT B239: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B240  -----------------------------------------
+#define GPIO_PORT_B240_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B240: PBYTE Position      */
+#define GPIO_PORT_B240_PBYTE_Msk                              (0x01UL << GPIO_PORT_B240_PBYTE_Pos)                      /*!< GPIO_PORT B240: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B241  -----------------------------------------
+#define GPIO_PORT_B241_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B241: PBYTE Position      */
+#define GPIO_PORT_B241_PBYTE_Msk                              (0x01UL << GPIO_PORT_B241_PBYTE_Pos)                      /*!< GPIO_PORT B241: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B242  -----------------------------------------
+#define GPIO_PORT_B242_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B242: PBYTE Position      */
+#define GPIO_PORT_B242_PBYTE_Msk                              (0x01UL << GPIO_PORT_B242_PBYTE_Pos)                      /*!< GPIO_PORT B242: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B243  -----------------------------------------
+#define GPIO_PORT_B243_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B243: PBYTE Position      */
+#define GPIO_PORT_B243_PBYTE_Msk                              (0x01UL << GPIO_PORT_B243_PBYTE_Pos)                      /*!< GPIO_PORT B243: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B244  -----------------------------------------
+#define GPIO_PORT_B244_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B244: PBYTE Position      */
+#define GPIO_PORT_B244_PBYTE_Msk                              (0x01UL << GPIO_PORT_B244_PBYTE_Pos)                      /*!< GPIO_PORT B244: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B245  -----------------------------------------
+#define GPIO_PORT_B245_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B245: PBYTE Position      */
+#define GPIO_PORT_B245_PBYTE_Msk                              (0x01UL << GPIO_PORT_B245_PBYTE_Pos)                      /*!< GPIO_PORT B245: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B246  -----------------------------------------
+#define GPIO_PORT_B246_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B246: PBYTE Position      */
+#define GPIO_PORT_B246_PBYTE_Msk                              (0x01UL << GPIO_PORT_B246_PBYTE_Pos)                      /*!< GPIO_PORT B246: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B247  -----------------------------------------
+#define GPIO_PORT_B247_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B247: PBYTE Position      */
+#define GPIO_PORT_B247_PBYTE_Msk                              (0x01UL << GPIO_PORT_B247_PBYTE_Pos)                      /*!< GPIO_PORT B247: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B248  -----------------------------------------
+#define GPIO_PORT_B248_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B248: PBYTE Position      */
+#define GPIO_PORT_B248_PBYTE_Msk                              (0x01UL << GPIO_PORT_B248_PBYTE_Pos)                      /*!< GPIO_PORT B248: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B249  -----------------------------------------
+#define GPIO_PORT_B249_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B249: PBYTE Position      */
+#define GPIO_PORT_B249_PBYTE_Msk                              (0x01UL << GPIO_PORT_B249_PBYTE_Pos)                      /*!< GPIO_PORT B249: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B250  -----------------------------------------
+#define GPIO_PORT_B250_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B250: PBYTE Position      */
+#define GPIO_PORT_B250_PBYTE_Msk                              (0x01UL << GPIO_PORT_B250_PBYTE_Pos)                      /*!< GPIO_PORT B250: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B251  -----------------------------------------
+#define GPIO_PORT_B251_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B251: PBYTE Position      */
+#define GPIO_PORT_B251_PBYTE_Msk                              (0x01UL << GPIO_PORT_B251_PBYTE_Pos)                      /*!< GPIO_PORT B251: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B252  -----------------------------------------
+#define GPIO_PORT_B252_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B252: PBYTE Position      */
+#define GPIO_PORT_B252_PBYTE_Msk                              (0x01UL << GPIO_PORT_B252_PBYTE_Pos)                      /*!< GPIO_PORT B252: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B253  -----------------------------------------
+#define GPIO_PORT_B253_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B253: PBYTE Position      */
+#define GPIO_PORT_B253_PBYTE_Msk                              (0x01UL << GPIO_PORT_B253_PBYTE_Pos)                      /*!< GPIO_PORT B253: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B254  -----------------------------------------
+#define GPIO_PORT_B254_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B254: PBYTE Position      */
+#define GPIO_PORT_B254_PBYTE_Msk                              (0x01UL << GPIO_PORT_B254_PBYTE_Pos)                      /*!< GPIO_PORT B254: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B255  -----------------------------------------
+#define GPIO_PORT_B255_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B255: PBYTE Position      */
+#define GPIO_PORT_B255_PBYTE_Msk                              (0x01UL << GPIO_PORT_B255_PBYTE_Pos)                      /*!< GPIO_PORT B255: PBYTE Mask          */
+
+// --------------------------------------  GPIO_PORT_W0  ------------------------------------------
+#define GPIO_PORT_W0_PWORD_Pos                                0                                                         /*!< GPIO_PORT W0: PWORD Position        */
+#define GPIO_PORT_W0_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos)                  /*!< GPIO_PORT W0: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W1  ------------------------------------------
+#define GPIO_PORT_W1_PWORD_Pos                                0                                                         /*!< GPIO_PORT W1: PWORD Position        */
+#define GPIO_PORT_W1_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos)                  /*!< GPIO_PORT W1: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W2  ------------------------------------------
+#define GPIO_PORT_W2_PWORD_Pos                                0                                                         /*!< GPIO_PORT W2: PWORD Position        */
+#define GPIO_PORT_W2_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos)                  /*!< GPIO_PORT W2: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W3  ------------------------------------------
+#define GPIO_PORT_W3_PWORD_Pos                                0                                                         /*!< GPIO_PORT W3: PWORD Position        */
+#define GPIO_PORT_W3_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos)                  /*!< GPIO_PORT W3: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W4  ------------------------------------------
+#define GPIO_PORT_W4_PWORD_Pos                                0                                                         /*!< GPIO_PORT W4: PWORD Position        */
+#define GPIO_PORT_W4_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos)                  /*!< GPIO_PORT W4: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W5  ------------------------------------------
+#define GPIO_PORT_W5_PWORD_Pos                                0                                                         /*!< GPIO_PORT W5: PWORD Position        */
+#define GPIO_PORT_W5_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos)                  /*!< GPIO_PORT W5: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W6  ------------------------------------------
+#define GPIO_PORT_W6_PWORD_Pos                                0                                                         /*!< GPIO_PORT W6: PWORD Position        */
+#define GPIO_PORT_W6_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos)                  /*!< GPIO_PORT W6: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W7  ------------------------------------------
+#define GPIO_PORT_W7_PWORD_Pos                                0                                                         /*!< GPIO_PORT W7: PWORD Position        */
+#define GPIO_PORT_W7_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos)                  /*!< GPIO_PORT W7: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W8  ------------------------------------------
+#define GPIO_PORT_W8_PWORD_Pos                                0                                                         /*!< GPIO_PORT W8: PWORD Position        */
+#define GPIO_PORT_W8_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos)                  /*!< GPIO_PORT W8: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W9  ------------------------------------------
+#define GPIO_PORT_W9_PWORD_Pos                                0                                                         /*!< GPIO_PORT W9: PWORD Position        */
+#define GPIO_PORT_W9_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos)                  /*!< GPIO_PORT W9: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W10  -----------------------------------------
+#define GPIO_PORT_W10_PWORD_Pos                               0                                                         /*!< GPIO_PORT W10: PWORD Position       */
+#define GPIO_PORT_W10_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos)                 /*!< GPIO_PORT W10: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W11  -----------------------------------------
+#define GPIO_PORT_W11_PWORD_Pos                               0                                                         /*!< GPIO_PORT W11: PWORD Position       */
+#define GPIO_PORT_W11_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos)                 /*!< GPIO_PORT W11: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W12  -----------------------------------------
+#define GPIO_PORT_W12_PWORD_Pos                               0                                                         /*!< GPIO_PORT W12: PWORD Position       */
+#define GPIO_PORT_W12_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos)                 /*!< GPIO_PORT W12: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W13  -----------------------------------------
+#define GPIO_PORT_W13_PWORD_Pos                               0                                                         /*!< GPIO_PORT W13: PWORD Position       */
+#define GPIO_PORT_W13_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos)                 /*!< GPIO_PORT W13: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W14  -----------------------------------------
+#define GPIO_PORT_W14_PWORD_Pos                               0                                                         /*!< GPIO_PORT W14: PWORD Position       */
+#define GPIO_PORT_W14_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos)                 /*!< GPIO_PORT W14: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W15  -----------------------------------------
+#define GPIO_PORT_W15_PWORD_Pos                               0                                                         /*!< GPIO_PORT W15: PWORD Position       */
+#define GPIO_PORT_W15_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos)                 /*!< GPIO_PORT W15: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W16  -----------------------------------------
+#define GPIO_PORT_W16_PWORD_Pos                               0                                                         /*!< GPIO_PORT W16: PWORD Position       */
+#define GPIO_PORT_W16_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos)                 /*!< GPIO_PORT W16: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W17  -----------------------------------------
+#define GPIO_PORT_W17_PWORD_Pos                               0                                                         /*!< GPIO_PORT W17: PWORD Position       */
+#define GPIO_PORT_W17_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos)                 /*!< GPIO_PORT W17: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W18  -----------------------------------------
+#define GPIO_PORT_W18_PWORD_Pos                               0                                                         /*!< GPIO_PORT W18: PWORD Position       */
+#define GPIO_PORT_W18_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos)                 /*!< GPIO_PORT W18: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W19  -----------------------------------------
+#define GPIO_PORT_W19_PWORD_Pos                               0                                                         /*!< GPIO_PORT W19: PWORD Position       */
+#define GPIO_PORT_W19_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos)                 /*!< GPIO_PORT W19: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W20  -----------------------------------------
+#define GPIO_PORT_W20_PWORD_Pos                               0                                                         /*!< GPIO_PORT W20: PWORD Position       */
+#define GPIO_PORT_W20_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos)                 /*!< GPIO_PORT W20: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W21  -----------------------------------------
+#define GPIO_PORT_W21_PWORD_Pos                               0                                                         /*!< GPIO_PORT W21: PWORD Position       */
+#define GPIO_PORT_W21_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos)                 /*!< GPIO_PORT W21: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W22  -----------------------------------------
+#define GPIO_PORT_W22_PWORD_Pos                               0                                                         /*!< GPIO_PORT W22: PWORD Position       */
+#define GPIO_PORT_W22_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos)                 /*!< GPIO_PORT W22: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W23  -----------------------------------------
+#define GPIO_PORT_W23_PWORD_Pos                               0                                                         /*!< GPIO_PORT W23: PWORD Position       */
+#define GPIO_PORT_W23_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos)                 /*!< GPIO_PORT W23: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W24  -----------------------------------------
+#define GPIO_PORT_W24_PWORD_Pos                               0                                                         /*!< GPIO_PORT W24: PWORD Position       */
+#define GPIO_PORT_W24_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos)                 /*!< GPIO_PORT W24: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W25  -----------------------------------------
+#define GPIO_PORT_W25_PWORD_Pos                               0                                                         /*!< GPIO_PORT W25: PWORD Position       */
+#define GPIO_PORT_W25_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos)                 /*!< GPIO_PORT W25: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W26  -----------------------------------------
+#define GPIO_PORT_W26_PWORD_Pos                               0                                                         /*!< GPIO_PORT W26: PWORD Position       */
+#define GPIO_PORT_W26_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos)                 /*!< GPIO_PORT W26: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W27  -----------------------------------------
+#define GPIO_PORT_W27_PWORD_Pos                               0                                                         /*!< GPIO_PORT W27: PWORD Position       */
+#define GPIO_PORT_W27_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos)                 /*!< GPIO_PORT W27: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W28  -----------------------------------------
+#define GPIO_PORT_W28_PWORD_Pos                               0                                                         /*!< GPIO_PORT W28: PWORD Position       */
+#define GPIO_PORT_W28_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos)                 /*!< GPIO_PORT W28: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W29  -----------------------------------------
+#define GPIO_PORT_W29_PWORD_Pos                               0                                                         /*!< GPIO_PORT W29: PWORD Position       */
+#define GPIO_PORT_W29_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos)                 /*!< GPIO_PORT W29: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W30  -----------------------------------------
+#define GPIO_PORT_W30_PWORD_Pos                               0                                                         /*!< GPIO_PORT W30: PWORD Position       */
+#define GPIO_PORT_W30_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos)                 /*!< GPIO_PORT W30: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W31  -----------------------------------------
+#define GPIO_PORT_W31_PWORD_Pos                               0                                                         /*!< GPIO_PORT W31: PWORD Position       */
+#define GPIO_PORT_W31_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos)                 /*!< GPIO_PORT W31: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W32  -----------------------------------------
+#define GPIO_PORT_W32_PWORD_Pos                               0                                                         /*!< GPIO_PORT W32: PWORD Position       */
+#define GPIO_PORT_W32_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos)                 /*!< GPIO_PORT W32: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W33  -----------------------------------------
+#define GPIO_PORT_W33_PWORD_Pos                               0                                                         /*!< GPIO_PORT W33: PWORD Position       */
+#define GPIO_PORT_W33_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos)                 /*!< GPIO_PORT W33: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W34  -----------------------------------------
+#define GPIO_PORT_W34_PWORD_Pos                               0                                                         /*!< GPIO_PORT W34: PWORD Position       */
+#define GPIO_PORT_W34_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos)                 /*!< GPIO_PORT W34: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W35  -----------------------------------------
+#define GPIO_PORT_W35_PWORD_Pos                               0                                                         /*!< GPIO_PORT W35: PWORD Position       */
+#define GPIO_PORT_W35_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos)                 /*!< GPIO_PORT W35: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W36  -----------------------------------------
+#define GPIO_PORT_W36_PWORD_Pos                               0                                                         /*!< GPIO_PORT W36: PWORD Position       */
+#define GPIO_PORT_W36_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos)                 /*!< GPIO_PORT W36: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W37  -----------------------------------------
+#define GPIO_PORT_W37_PWORD_Pos                               0                                                         /*!< GPIO_PORT W37: PWORD Position       */
+#define GPIO_PORT_W37_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos)                 /*!< GPIO_PORT W37: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W38  -----------------------------------------
+#define GPIO_PORT_W38_PWORD_Pos                               0                                                         /*!< GPIO_PORT W38: PWORD Position       */
+#define GPIO_PORT_W38_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos)                 /*!< GPIO_PORT W38: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W39  -----------------------------------------
+#define GPIO_PORT_W39_PWORD_Pos                               0                                                         /*!< GPIO_PORT W39: PWORD Position       */
+#define GPIO_PORT_W39_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos)                 /*!< GPIO_PORT W39: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W40  -----------------------------------------
+#define GPIO_PORT_W40_PWORD_Pos                               0                                                         /*!< GPIO_PORT W40: PWORD Position       */
+#define GPIO_PORT_W40_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos)                 /*!< GPIO_PORT W40: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W41  -----------------------------------------
+#define GPIO_PORT_W41_PWORD_Pos                               0                                                         /*!< GPIO_PORT W41: PWORD Position       */
+#define GPIO_PORT_W41_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos)                 /*!< GPIO_PORT W41: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W42  -----------------------------------------
+#define GPIO_PORT_W42_PWORD_Pos                               0                                                         /*!< GPIO_PORT W42: PWORD Position       */
+#define GPIO_PORT_W42_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos)                 /*!< GPIO_PORT W42: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W43  -----------------------------------------
+#define GPIO_PORT_W43_PWORD_Pos                               0                                                         /*!< GPIO_PORT W43: PWORD Position       */
+#define GPIO_PORT_W43_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos)                 /*!< GPIO_PORT W43: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W44  -----------------------------------------
+#define GPIO_PORT_W44_PWORD_Pos                               0                                                         /*!< GPIO_PORT W44: PWORD Position       */
+#define GPIO_PORT_W44_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos)                 /*!< GPIO_PORT W44: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W45  -----------------------------------------
+#define GPIO_PORT_W45_PWORD_Pos                               0                                                         /*!< GPIO_PORT W45: PWORD Position       */
+#define GPIO_PORT_W45_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos)                 /*!< GPIO_PORT W45: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W46  -----------------------------------------
+#define GPIO_PORT_W46_PWORD_Pos                               0                                                         /*!< GPIO_PORT W46: PWORD Position       */
+#define GPIO_PORT_W46_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos)                 /*!< GPIO_PORT W46: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W47  -----------------------------------------
+#define GPIO_PORT_W47_PWORD_Pos                               0                                                         /*!< GPIO_PORT W47: PWORD Position       */
+#define GPIO_PORT_W47_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos)                 /*!< GPIO_PORT W47: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W48  -----------------------------------------
+#define GPIO_PORT_W48_PWORD_Pos                               0                                                         /*!< GPIO_PORT W48: PWORD Position       */
+#define GPIO_PORT_W48_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos)                 /*!< GPIO_PORT W48: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W49  -----------------------------------------
+#define GPIO_PORT_W49_PWORD_Pos                               0                                                         /*!< GPIO_PORT W49: PWORD Position       */
+#define GPIO_PORT_W49_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos)                 /*!< GPIO_PORT W49: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W50  -----------------------------------------
+#define GPIO_PORT_W50_PWORD_Pos                               0                                                         /*!< GPIO_PORT W50: PWORD Position       */
+#define GPIO_PORT_W50_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos)                 /*!< GPIO_PORT W50: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W51  -----------------------------------------
+#define GPIO_PORT_W51_PWORD_Pos                               0                                                         /*!< GPIO_PORT W51: PWORD Position       */
+#define GPIO_PORT_W51_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos)                 /*!< GPIO_PORT W51: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W52  -----------------------------------------
+#define GPIO_PORT_W52_PWORD_Pos                               0                                                         /*!< GPIO_PORT W52: PWORD Position       */
+#define GPIO_PORT_W52_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos)                 /*!< GPIO_PORT W52: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W53  -----------------------------------------
+#define GPIO_PORT_W53_PWORD_Pos                               0                                                         /*!< GPIO_PORT W53: PWORD Position       */
+#define GPIO_PORT_W53_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos)                 /*!< GPIO_PORT W53: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W54  -----------------------------------------
+#define GPIO_PORT_W54_PWORD_Pos                               0                                                         /*!< GPIO_PORT W54: PWORD Position       */
+#define GPIO_PORT_W54_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos)                 /*!< GPIO_PORT W54: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W55  -----------------------------------------
+#define GPIO_PORT_W55_PWORD_Pos                               0                                                         /*!< GPIO_PORT W55: PWORD Position       */
+#define GPIO_PORT_W55_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos)                 /*!< GPIO_PORT W55: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W56  -----------------------------------------
+#define GPIO_PORT_W56_PWORD_Pos                               0                                                         /*!< GPIO_PORT W56: PWORD Position       */
+#define GPIO_PORT_W56_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos)                 /*!< GPIO_PORT W56: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W57  -----------------------------------------
+#define GPIO_PORT_W57_PWORD_Pos                               0                                                         /*!< GPIO_PORT W57: PWORD Position       */
+#define GPIO_PORT_W57_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos)                 /*!< GPIO_PORT W57: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W58  -----------------------------------------
+#define GPIO_PORT_W58_PWORD_Pos                               0                                                         /*!< GPIO_PORT W58: PWORD Position       */
+#define GPIO_PORT_W58_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos)                 /*!< GPIO_PORT W58: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W59  -----------------------------------------
+#define GPIO_PORT_W59_PWORD_Pos                               0                                                         /*!< GPIO_PORT W59: PWORD Position       */
+#define GPIO_PORT_W59_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos)                 /*!< GPIO_PORT W59: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W60  -----------------------------------------
+#define GPIO_PORT_W60_PWORD_Pos                               0                                                         /*!< GPIO_PORT W60: PWORD Position       */
+#define GPIO_PORT_W60_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos)                 /*!< GPIO_PORT W60: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W61  -----------------------------------------
+#define GPIO_PORT_W61_PWORD_Pos                               0                                                         /*!< GPIO_PORT W61: PWORD Position       */
+#define GPIO_PORT_W61_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos)                 /*!< GPIO_PORT W61: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W62  -----------------------------------------
+#define GPIO_PORT_W62_PWORD_Pos                               0                                                         /*!< GPIO_PORT W62: PWORD Position       */
+#define GPIO_PORT_W62_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos)                 /*!< GPIO_PORT W62: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W63  -----------------------------------------
+#define GPIO_PORT_W63_PWORD_Pos                               0                                                         /*!< GPIO_PORT W63: PWORD Position       */
+#define GPIO_PORT_W63_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos)                 /*!< GPIO_PORT W63: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W64  -----------------------------------------
+#define GPIO_PORT_W64_PWORD_Pos                               0                                                         /*!< GPIO_PORT W64: PWORD Position       */
+#define GPIO_PORT_W64_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos)                 /*!< GPIO_PORT W64: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W65  -----------------------------------------
+#define GPIO_PORT_W65_PWORD_Pos                               0                                                         /*!< GPIO_PORT W65: PWORD Position       */
+#define GPIO_PORT_W65_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos)                 /*!< GPIO_PORT W65: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W66  -----------------------------------------
+#define GPIO_PORT_W66_PWORD_Pos                               0                                                         /*!< GPIO_PORT W66: PWORD Position       */
+#define GPIO_PORT_W66_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos)                 /*!< GPIO_PORT W66: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W67  -----------------------------------------
+#define GPIO_PORT_W67_PWORD_Pos                               0                                                         /*!< GPIO_PORT W67: PWORD Position       */
+#define GPIO_PORT_W67_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos)                 /*!< GPIO_PORT W67: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W68  -----------------------------------------
+#define GPIO_PORT_W68_PWORD_Pos                               0                                                         /*!< GPIO_PORT W68: PWORD Position       */
+#define GPIO_PORT_W68_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos)                 /*!< GPIO_PORT W68: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W69  -----------------------------------------
+#define GPIO_PORT_W69_PWORD_Pos                               0                                                         /*!< GPIO_PORT W69: PWORD Position       */
+#define GPIO_PORT_W69_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos)                 /*!< GPIO_PORT W69: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W70  -----------------------------------------
+#define GPIO_PORT_W70_PWORD_Pos                               0                                                         /*!< GPIO_PORT W70: PWORD Position       */
+#define GPIO_PORT_W70_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos)                 /*!< GPIO_PORT W70: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W71  -----------------------------------------
+#define GPIO_PORT_W71_PWORD_Pos                               0                                                         /*!< GPIO_PORT W71: PWORD Position       */
+#define GPIO_PORT_W71_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos)                 /*!< GPIO_PORT W71: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W72  -----------------------------------------
+#define GPIO_PORT_W72_PWORD_Pos                               0                                                         /*!< GPIO_PORT W72: PWORD Position       */
+#define GPIO_PORT_W72_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos)                 /*!< GPIO_PORT W72: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W73  -----------------------------------------
+#define GPIO_PORT_W73_PWORD_Pos                               0                                                         /*!< GPIO_PORT W73: PWORD Position       */
+#define GPIO_PORT_W73_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos)                 /*!< GPIO_PORT W73: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W74  -----------------------------------------
+#define GPIO_PORT_W74_PWORD_Pos                               0                                                         /*!< GPIO_PORT W74: PWORD Position       */
+#define GPIO_PORT_W74_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos)                 /*!< GPIO_PORT W74: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W75  -----------------------------------------
+#define GPIO_PORT_W75_PWORD_Pos                               0                                                         /*!< GPIO_PORT W75: PWORD Position       */
+#define GPIO_PORT_W75_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos)                 /*!< GPIO_PORT W75: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W76  -----------------------------------------
+#define GPIO_PORT_W76_PWORD_Pos                               0                                                         /*!< GPIO_PORT W76: PWORD Position       */
+#define GPIO_PORT_W76_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos)                 /*!< GPIO_PORT W76: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W77  -----------------------------------------
+#define GPIO_PORT_W77_PWORD_Pos                               0                                                         /*!< GPIO_PORT W77: PWORD Position       */
+#define GPIO_PORT_W77_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos)                 /*!< GPIO_PORT W77: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W78  -----------------------------------------
+#define GPIO_PORT_W78_PWORD_Pos                               0                                                         /*!< GPIO_PORT W78: PWORD Position       */
+#define GPIO_PORT_W78_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos)                 /*!< GPIO_PORT W78: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W79  -----------------------------------------
+#define GPIO_PORT_W79_PWORD_Pos                               0                                                         /*!< GPIO_PORT W79: PWORD Position       */
+#define GPIO_PORT_W79_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos)                 /*!< GPIO_PORT W79: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W80  -----------------------------------------
+#define GPIO_PORT_W80_PWORD_Pos                               0                                                         /*!< GPIO_PORT W80: PWORD Position       */
+#define GPIO_PORT_W80_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos)                 /*!< GPIO_PORT W80: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W81  -----------------------------------------
+#define GPIO_PORT_W81_PWORD_Pos                               0                                                         /*!< GPIO_PORT W81: PWORD Position       */
+#define GPIO_PORT_W81_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos)                 /*!< GPIO_PORT W81: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W82  -----------------------------------------
+#define GPIO_PORT_W82_PWORD_Pos                               0                                                         /*!< GPIO_PORT W82: PWORD Position       */
+#define GPIO_PORT_W82_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos)                 /*!< GPIO_PORT W82: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W83  -----------------------------------------
+#define GPIO_PORT_W83_PWORD_Pos                               0                                                         /*!< GPIO_PORT W83: PWORD Position       */
+#define GPIO_PORT_W83_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos)                 /*!< GPIO_PORT W83: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W84  -----------------------------------------
+#define GPIO_PORT_W84_PWORD_Pos                               0                                                         /*!< GPIO_PORT W84: PWORD Position       */
+#define GPIO_PORT_W84_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos)                 /*!< GPIO_PORT W84: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W85  -----------------------------------------
+#define GPIO_PORT_W85_PWORD_Pos                               0                                                         /*!< GPIO_PORT W85: PWORD Position       */
+#define GPIO_PORT_W85_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos)                 /*!< GPIO_PORT W85: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W86  -----------------------------------------
+#define GPIO_PORT_W86_PWORD_Pos                               0                                                         /*!< GPIO_PORT W86: PWORD Position       */
+#define GPIO_PORT_W86_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos)                 /*!< GPIO_PORT W86: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W87  -----------------------------------------
+#define GPIO_PORT_W87_PWORD_Pos                               0                                                         /*!< GPIO_PORT W87: PWORD Position       */
+#define GPIO_PORT_W87_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos)                 /*!< GPIO_PORT W87: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W88  -----------------------------------------
+#define GPIO_PORT_W88_PWORD_Pos                               0                                                         /*!< GPIO_PORT W88: PWORD Position       */
+#define GPIO_PORT_W88_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos)                 /*!< GPIO_PORT W88: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W89  -----------------------------------------
+#define GPIO_PORT_W89_PWORD_Pos                               0                                                         /*!< GPIO_PORT W89: PWORD Position       */
+#define GPIO_PORT_W89_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos)                 /*!< GPIO_PORT W89: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W90  -----------------------------------------
+#define GPIO_PORT_W90_PWORD_Pos                               0                                                         /*!< GPIO_PORT W90: PWORD Position       */
+#define GPIO_PORT_W90_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos)                 /*!< GPIO_PORT W90: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W91  -----------------------------------------
+#define GPIO_PORT_W91_PWORD_Pos                               0                                                         /*!< GPIO_PORT W91: PWORD Position       */
+#define GPIO_PORT_W91_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos)                 /*!< GPIO_PORT W91: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W92  -----------------------------------------
+#define GPIO_PORT_W92_PWORD_Pos                               0                                                         /*!< GPIO_PORT W92: PWORD Position       */
+#define GPIO_PORT_W92_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos)                 /*!< GPIO_PORT W92: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W93  -----------------------------------------
+#define GPIO_PORT_W93_PWORD_Pos                               0                                                         /*!< GPIO_PORT W93: PWORD Position       */
+#define GPIO_PORT_W93_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos)                 /*!< GPIO_PORT W93: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W94  -----------------------------------------
+#define GPIO_PORT_W94_PWORD_Pos                               0                                                         /*!< GPIO_PORT W94: PWORD Position       */
+#define GPIO_PORT_W94_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos)                 /*!< GPIO_PORT W94: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W95  -----------------------------------------
+#define GPIO_PORT_W95_PWORD_Pos                               0                                                         /*!< GPIO_PORT W95: PWORD Position       */
+#define GPIO_PORT_W95_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos)                 /*!< GPIO_PORT W95: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W96  -----------------------------------------
+#define GPIO_PORT_W96_PWORD_Pos                               0                                                         /*!< GPIO_PORT W96: PWORD Position       */
+#define GPIO_PORT_W96_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos)                 /*!< GPIO_PORT W96: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W97  -----------------------------------------
+#define GPIO_PORT_W97_PWORD_Pos                               0                                                         /*!< GPIO_PORT W97: PWORD Position       */
+#define GPIO_PORT_W97_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos)                 /*!< GPIO_PORT W97: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W98  -----------------------------------------
+#define GPIO_PORT_W98_PWORD_Pos                               0                                                         /*!< GPIO_PORT W98: PWORD Position       */
+#define GPIO_PORT_W98_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos)                 /*!< GPIO_PORT W98: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W99  -----------------------------------------
+#define GPIO_PORT_W99_PWORD_Pos                               0                                                         /*!< GPIO_PORT W99: PWORD Position       */
+#define GPIO_PORT_W99_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos)                 /*!< GPIO_PORT W99: PWORD Mask           */
+
+// -------------------------------------  GPIO_PORT_W100  -----------------------------------------
+#define GPIO_PORT_W100_PWORD_Pos                              0                                                         /*!< GPIO_PORT W100: PWORD Position      */
+#define GPIO_PORT_W100_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos)                /*!< GPIO_PORT W100: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W101  -----------------------------------------
+#define GPIO_PORT_W101_PWORD_Pos                              0                                                         /*!< GPIO_PORT W101: PWORD Position      */
+#define GPIO_PORT_W101_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos)                /*!< GPIO_PORT W101: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W102  -----------------------------------------
+#define GPIO_PORT_W102_PWORD_Pos                              0                                                         /*!< GPIO_PORT W102: PWORD Position      */
+#define GPIO_PORT_W102_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos)                /*!< GPIO_PORT W102: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W103  -----------------------------------------
+#define GPIO_PORT_W103_PWORD_Pos                              0                                                         /*!< GPIO_PORT W103: PWORD Position      */
+#define GPIO_PORT_W103_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos)                /*!< GPIO_PORT W103: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W104  -----------------------------------------
+#define GPIO_PORT_W104_PWORD_Pos                              0                                                         /*!< GPIO_PORT W104: PWORD Position      */
+#define GPIO_PORT_W104_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos)                /*!< GPIO_PORT W104: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W105  -----------------------------------------
+#define GPIO_PORT_W105_PWORD_Pos                              0                                                         /*!< GPIO_PORT W105: PWORD Position      */
+#define GPIO_PORT_W105_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos)                /*!< GPIO_PORT W105: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W106  -----------------------------------------
+#define GPIO_PORT_W106_PWORD_Pos                              0                                                         /*!< GPIO_PORT W106: PWORD Position      */
+#define GPIO_PORT_W106_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos)                /*!< GPIO_PORT W106: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W107  -----------------------------------------
+#define GPIO_PORT_W107_PWORD_Pos                              0                                                         /*!< GPIO_PORT W107: PWORD Position      */
+#define GPIO_PORT_W107_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos)                /*!< GPIO_PORT W107: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W108  -----------------------------------------
+#define GPIO_PORT_W108_PWORD_Pos                              0                                                         /*!< GPIO_PORT W108: PWORD Position      */
+#define GPIO_PORT_W108_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos)                /*!< GPIO_PORT W108: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W109  -----------------------------------------
+#define GPIO_PORT_W109_PWORD_Pos                              0                                                         /*!< GPIO_PORT W109: PWORD Position      */
+#define GPIO_PORT_W109_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos)                /*!< GPIO_PORT W109: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W110  -----------------------------------------
+#define GPIO_PORT_W110_PWORD_Pos                              0                                                         /*!< GPIO_PORT W110: PWORD Position      */
+#define GPIO_PORT_W110_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos)                /*!< GPIO_PORT W110: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W111  -----------------------------------------
+#define GPIO_PORT_W111_PWORD_Pos                              0                                                         /*!< GPIO_PORT W111: PWORD Position      */
+#define GPIO_PORT_W111_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos)                /*!< GPIO_PORT W111: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W112  -----------------------------------------
+#define GPIO_PORT_W112_PWORD_Pos                              0                                                         /*!< GPIO_PORT W112: PWORD Position      */
+#define GPIO_PORT_W112_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos)                /*!< GPIO_PORT W112: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W113  -----------------------------------------
+#define GPIO_PORT_W113_PWORD_Pos                              0                                                         /*!< GPIO_PORT W113: PWORD Position      */
+#define GPIO_PORT_W113_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos)                /*!< GPIO_PORT W113: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W114  -----------------------------------------
+#define GPIO_PORT_W114_PWORD_Pos                              0                                                         /*!< GPIO_PORT W114: PWORD Position      */
+#define GPIO_PORT_W114_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos)                /*!< GPIO_PORT W114: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W115  -----------------------------------------
+#define GPIO_PORT_W115_PWORD_Pos                              0                                                         /*!< GPIO_PORT W115: PWORD Position      */
+#define GPIO_PORT_W115_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos)                /*!< GPIO_PORT W115: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W116  -----------------------------------------
+#define GPIO_PORT_W116_PWORD_Pos                              0                                                         /*!< GPIO_PORT W116: PWORD Position      */
+#define GPIO_PORT_W116_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos)                /*!< GPIO_PORT W116: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W117  -----------------------------------------
+#define GPIO_PORT_W117_PWORD_Pos                              0                                                         /*!< GPIO_PORT W117: PWORD Position      */
+#define GPIO_PORT_W117_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos)                /*!< GPIO_PORT W117: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W118  -----------------------------------------
+#define GPIO_PORT_W118_PWORD_Pos                              0                                                         /*!< GPIO_PORT W118: PWORD Position      */
+#define GPIO_PORT_W118_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos)                /*!< GPIO_PORT W118: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W119  -----------------------------------------
+#define GPIO_PORT_W119_PWORD_Pos                              0                                                         /*!< GPIO_PORT W119: PWORD Position      */
+#define GPIO_PORT_W119_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos)                /*!< GPIO_PORT W119: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W120  -----------------------------------------
+#define GPIO_PORT_W120_PWORD_Pos                              0                                                         /*!< GPIO_PORT W120: PWORD Position      */
+#define GPIO_PORT_W120_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos)                /*!< GPIO_PORT W120: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W121  -----------------------------------------
+#define GPIO_PORT_W121_PWORD_Pos                              0                                                         /*!< GPIO_PORT W121: PWORD Position      */
+#define GPIO_PORT_W121_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos)                /*!< GPIO_PORT W121: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W122  -----------------------------------------
+#define GPIO_PORT_W122_PWORD_Pos                              0                                                         /*!< GPIO_PORT W122: PWORD Position      */
+#define GPIO_PORT_W122_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos)                /*!< GPIO_PORT W122: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W123  -----------------------------------------
+#define GPIO_PORT_W123_PWORD_Pos                              0                                                         /*!< GPIO_PORT W123: PWORD Position      */
+#define GPIO_PORT_W123_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos)                /*!< GPIO_PORT W123: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W124  -----------------------------------------
+#define GPIO_PORT_W124_PWORD_Pos                              0                                                         /*!< GPIO_PORT W124: PWORD Position      */
+#define GPIO_PORT_W124_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos)                /*!< GPIO_PORT W124: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W125  -----------------------------------------
+#define GPIO_PORT_W125_PWORD_Pos                              0                                                         /*!< GPIO_PORT W125: PWORD Position      */
+#define GPIO_PORT_W125_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos)                /*!< GPIO_PORT W125: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W126  -----------------------------------------
+#define GPIO_PORT_W126_PWORD_Pos                              0                                                         /*!< GPIO_PORT W126: PWORD Position      */
+#define GPIO_PORT_W126_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos)                /*!< GPIO_PORT W126: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W127  -----------------------------------------
+#define GPIO_PORT_W127_PWORD_Pos                              0                                                         /*!< GPIO_PORT W127: PWORD Position      */
+#define GPIO_PORT_W127_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos)                /*!< GPIO_PORT W127: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W128  -----------------------------------------
+#define GPIO_PORT_W128_PWORD_Pos                              0                                                         /*!< GPIO_PORT W128: PWORD Position      */
+#define GPIO_PORT_W128_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos)                /*!< GPIO_PORT W128: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W129  -----------------------------------------
+#define GPIO_PORT_W129_PWORD_Pos                              0                                                         /*!< GPIO_PORT W129: PWORD Position      */
+#define GPIO_PORT_W129_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos)                /*!< GPIO_PORT W129: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W130  -----------------------------------------
+#define GPIO_PORT_W130_PWORD_Pos                              0                                                         /*!< GPIO_PORT W130: PWORD Position      */
+#define GPIO_PORT_W130_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos)                /*!< GPIO_PORT W130: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W131  -----------------------------------------
+#define GPIO_PORT_W131_PWORD_Pos                              0                                                         /*!< GPIO_PORT W131: PWORD Position      */
+#define GPIO_PORT_W131_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos)                /*!< GPIO_PORT W131: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W132  -----------------------------------------
+#define GPIO_PORT_W132_PWORD_Pos                              0                                                         /*!< GPIO_PORT W132: PWORD Position      */
+#define GPIO_PORT_W132_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos)                /*!< GPIO_PORT W132: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W133  -----------------------------------------
+#define GPIO_PORT_W133_PWORD_Pos                              0                                                         /*!< GPIO_PORT W133: PWORD Position      */
+#define GPIO_PORT_W133_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos)                /*!< GPIO_PORT W133: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W134  -----------------------------------------
+#define GPIO_PORT_W134_PWORD_Pos                              0                                                         /*!< GPIO_PORT W134: PWORD Position      */
+#define GPIO_PORT_W134_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos)                /*!< GPIO_PORT W134: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W135  -----------------------------------------
+#define GPIO_PORT_W135_PWORD_Pos                              0                                                         /*!< GPIO_PORT W135: PWORD Position      */
+#define GPIO_PORT_W135_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos)                /*!< GPIO_PORT W135: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W136  -----------------------------------------
+#define GPIO_PORT_W136_PWORD_Pos                              0                                                         /*!< GPIO_PORT W136: PWORD Position      */
+#define GPIO_PORT_W136_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos)                /*!< GPIO_PORT W136: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W137  -----------------------------------------
+#define GPIO_PORT_W137_PWORD_Pos                              0                                                         /*!< GPIO_PORT W137: PWORD Position      */
+#define GPIO_PORT_W137_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos)                /*!< GPIO_PORT W137: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W138  -----------------------------------------
+#define GPIO_PORT_W138_PWORD_Pos                              0                                                         /*!< GPIO_PORT W138: PWORD Position      */
+#define GPIO_PORT_W138_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos)                /*!< GPIO_PORT W138: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W139  -----------------------------------------
+#define GPIO_PORT_W139_PWORD_Pos                              0                                                         /*!< GPIO_PORT W139: PWORD Position      */
+#define GPIO_PORT_W139_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos)                /*!< GPIO_PORT W139: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W140  -----------------------------------------
+#define GPIO_PORT_W140_PWORD_Pos                              0                                                         /*!< GPIO_PORT W140: PWORD Position      */
+#define GPIO_PORT_W140_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos)                /*!< GPIO_PORT W140: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W141  -----------------------------------------
+#define GPIO_PORT_W141_PWORD_Pos                              0                                                         /*!< GPIO_PORT W141: PWORD Position      */
+#define GPIO_PORT_W141_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos)                /*!< GPIO_PORT W141: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W142  -----------------------------------------
+#define GPIO_PORT_W142_PWORD_Pos                              0                                                         /*!< GPIO_PORT W142: PWORD Position      */
+#define GPIO_PORT_W142_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos)                /*!< GPIO_PORT W142: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W143  -----------------------------------------
+#define GPIO_PORT_W143_PWORD_Pos                              0                                                         /*!< GPIO_PORT W143: PWORD Position      */
+#define GPIO_PORT_W143_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos)                /*!< GPIO_PORT W143: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W144  -----------------------------------------
+#define GPIO_PORT_W144_PWORD_Pos                              0                                                         /*!< GPIO_PORT W144: PWORD Position      */
+#define GPIO_PORT_W144_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos)                /*!< GPIO_PORT W144: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W145  -----------------------------------------
+#define GPIO_PORT_W145_PWORD_Pos                              0                                                         /*!< GPIO_PORT W145: PWORD Position      */
+#define GPIO_PORT_W145_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos)                /*!< GPIO_PORT W145: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W146  -----------------------------------------
+#define GPIO_PORT_W146_PWORD_Pos                              0                                                         /*!< GPIO_PORT W146: PWORD Position      */
+#define GPIO_PORT_W146_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos)                /*!< GPIO_PORT W146: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W147  -----------------------------------------
+#define GPIO_PORT_W147_PWORD_Pos                              0                                                         /*!< GPIO_PORT W147: PWORD Position      */
+#define GPIO_PORT_W147_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos)                /*!< GPIO_PORT W147: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W148  -----------------------------------------
+#define GPIO_PORT_W148_PWORD_Pos                              0                                                         /*!< GPIO_PORT W148: PWORD Position      */
+#define GPIO_PORT_W148_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos)                /*!< GPIO_PORT W148: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W149  -----------------------------------------
+#define GPIO_PORT_W149_PWORD_Pos                              0                                                         /*!< GPIO_PORT W149: PWORD Position      */
+#define GPIO_PORT_W149_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos)                /*!< GPIO_PORT W149: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W150  -----------------------------------------
+#define GPIO_PORT_W150_PWORD_Pos                              0                                                         /*!< GPIO_PORT W150: PWORD Position      */
+#define GPIO_PORT_W150_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos)                /*!< GPIO_PORT W150: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W151  -----------------------------------------
+#define GPIO_PORT_W151_PWORD_Pos                              0                                                         /*!< GPIO_PORT W151: PWORD Position      */
+#define GPIO_PORT_W151_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos)                /*!< GPIO_PORT W151: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W152  -----------------------------------------
+#define GPIO_PORT_W152_PWORD_Pos                              0                                                         /*!< GPIO_PORT W152: PWORD Position      */
+#define GPIO_PORT_W152_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos)                /*!< GPIO_PORT W152: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W153  -----------------------------------------
+#define GPIO_PORT_W153_PWORD_Pos                              0                                                         /*!< GPIO_PORT W153: PWORD Position      */
+#define GPIO_PORT_W153_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos)                /*!< GPIO_PORT W153: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W154  -----------------------------------------
+#define GPIO_PORT_W154_PWORD_Pos                              0                                                         /*!< GPIO_PORT W154: PWORD Position      */
+#define GPIO_PORT_W154_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos)                /*!< GPIO_PORT W154: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W155  -----------------------------------------
+#define GPIO_PORT_W155_PWORD_Pos                              0                                                         /*!< GPIO_PORT W155: PWORD Position      */
+#define GPIO_PORT_W155_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos)                /*!< GPIO_PORT W155: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W156  -----------------------------------------
+#define GPIO_PORT_W156_PWORD_Pos                              0                                                         /*!< GPIO_PORT W156: PWORD Position      */
+#define GPIO_PORT_W156_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos)                /*!< GPIO_PORT W156: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W157  -----------------------------------------
+#define GPIO_PORT_W157_PWORD_Pos                              0                                                         /*!< GPIO_PORT W157: PWORD Position      */
+#define GPIO_PORT_W157_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos)                /*!< GPIO_PORT W157: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W158  -----------------------------------------
+#define GPIO_PORT_W158_PWORD_Pos                              0                                                         /*!< GPIO_PORT W158: PWORD Position      */
+#define GPIO_PORT_W158_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos)                /*!< GPIO_PORT W158: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W159  -----------------------------------------
+#define GPIO_PORT_W159_PWORD_Pos                              0                                                         /*!< GPIO_PORT W159: PWORD Position      */
+#define GPIO_PORT_W159_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos)                /*!< GPIO_PORT W159: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W160  -----------------------------------------
+#define GPIO_PORT_W160_PWORD_Pos                              0                                                         /*!< GPIO_PORT W160: PWORD Position      */
+#define GPIO_PORT_W160_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos)                /*!< GPIO_PORT W160: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W161  -----------------------------------------
+#define GPIO_PORT_W161_PWORD_Pos                              0                                                         /*!< GPIO_PORT W161: PWORD Position      */
+#define GPIO_PORT_W161_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos)                /*!< GPIO_PORT W161: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W162  -----------------------------------------
+#define GPIO_PORT_W162_PWORD_Pos                              0                                                         /*!< GPIO_PORT W162: PWORD Position      */
+#define GPIO_PORT_W162_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos)                /*!< GPIO_PORT W162: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W163  -----------------------------------------
+#define GPIO_PORT_W163_PWORD_Pos                              0                                                         /*!< GPIO_PORT W163: PWORD Position      */
+#define GPIO_PORT_W163_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos)                /*!< GPIO_PORT W163: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W164  -----------------------------------------
+#define GPIO_PORT_W164_PWORD_Pos                              0                                                         /*!< GPIO_PORT W164: PWORD Position      */
+#define GPIO_PORT_W164_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos)                /*!< GPIO_PORT W164: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W165  -----------------------------------------
+#define GPIO_PORT_W165_PWORD_Pos                              0                                                         /*!< GPIO_PORT W165: PWORD Position      */
+#define GPIO_PORT_W165_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos)                /*!< GPIO_PORT W165: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W166  -----------------------------------------
+#define GPIO_PORT_W166_PWORD_Pos                              0                                                         /*!< GPIO_PORT W166: PWORD Position      */
+#define GPIO_PORT_W166_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos)                /*!< GPIO_PORT W166: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W167  -----------------------------------------
+#define GPIO_PORT_W167_PWORD_Pos                              0                                                         /*!< GPIO_PORT W167: PWORD Position      */
+#define GPIO_PORT_W167_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos)                /*!< GPIO_PORT W167: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W168  -----------------------------------------
+#define GPIO_PORT_W168_PWORD_Pos                              0                                                         /*!< GPIO_PORT W168: PWORD Position      */
+#define GPIO_PORT_W168_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos)                /*!< GPIO_PORT W168: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W169  -----------------------------------------
+#define GPIO_PORT_W169_PWORD_Pos                              0                                                         /*!< GPIO_PORT W169: PWORD Position      */
+#define GPIO_PORT_W169_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos)                /*!< GPIO_PORT W169: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W170  -----------------------------------------
+#define GPIO_PORT_W170_PWORD_Pos                              0                                                         /*!< GPIO_PORT W170: PWORD Position      */
+#define GPIO_PORT_W170_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos)                /*!< GPIO_PORT W170: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W171  -----------------------------------------
+#define GPIO_PORT_W171_PWORD_Pos                              0                                                         /*!< GPIO_PORT W171: PWORD Position      */
+#define GPIO_PORT_W171_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos)                /*!< GPIO_PORT W171: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W172  -----------------------------------------
+#define GPIO_PORT_W172_PWORD_Pos                              0                                                         /*!< GPIO_PORT W172: PWORD Position      */
+#define GPIO_PORT_W172_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos)                /*!< GPIO_PORT W172: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W173  -----------------------------------------
+#define GPIO_PORT_W173_PWORD_Pos                              0                                                         /*!< GPIO_PORT W173: PWORD Position      */
+#define GPIO_PORT_W173_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos)                /*!< GPIO_PORT W173: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W174  -----------------------------------------
+#define GPIO_PORT_W174_PWORD_Pos                              0                                                         /*!< GPIO_PORT W174: PWORD Position      */
+#define GPIO_PORT_W174_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos)                /*!< GPIO_PORT W174: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W175  -----------------------------------------
+#define GPIO_PORT_W175_PWORD_Pos                              0                                                         /*!< GPIO_PORT W175: PWORD Position      */
+#define GPIO_PORT_W175_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos)                /*!< GPIO_PORT W175: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W176  -----------------------------------------
+#define GPIO_PORT_W176_PWORD_Pos                              0                                                         /*!< GPIO_PORT W176: PWORD Position      */
+#define GPIO_PORT_W176_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos)                /*!< GPIO_PORT W176: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W177  -----------------------------------------
+#define GPIO_PORT_W177_PWORD_Pos                              0                                                         /*!< GPIO_PORT W177: PWORD Position      */
+#define GPIO_PORT_W177_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos)                /*!< GPIO_PORT W177: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W178  -----------------------------------------
+#define GPIO_PORT_W178_PWORD_Pos                              0                                                         /*!< GPIO_PORT W178: PWORD Position      */
+#define GPIO_PORT_W178_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos)                /*!< GPIO_PORT W178: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W179  -----------------------------------------
+#define GPIO_PORT_W179_PWORD_Pos                              0                                                         /*!< GPIO_PORT W179: PWORD Position      */
+#define GPIO_PORT_W179_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos)                /*!< GPIO_PORT W179: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W180  -----------------------------------------
+#define GPIO_PORT_W180_PWORD_Pos                              0                                                         /*!< GPIO_PORT W180: PWORD Position      */
+#define GPIO_PORT_W180_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos)                /*!< GPIO_PORT W180: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W181  -----------------------------------------
+#define GPIO_PORT_W181_PWORD_Pos                              0                                                         /*!< GPIO_PORT W181: PWORD Position      */
+#define GPIO_PORT_W181_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos)                /*!< GPIO_PORT W181: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W182  -----------------------------------------
+#define GPIO_PORT_W182_PWORD_Pos                              0                                                         /*!< GPIO_PORT W182: PWORD Position      */
+#define GPIO_PORT_W182_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos)                /*!< GPIO_PORT W182: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W183  -----------------------------------------
+#define GPIO_PORT_W183_PWORD_Pos                              0                                                         /*!< GPIO_PORT W183: PWORD Position      */
+#define GPIO_PORT_W183_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos)                /*!< GPIO_PORT W183: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W184  -----------------------------------------
+#define GPIO_PORT_W184_PWORD_Pos                              0                                                         /*!< GPIO_PORT W184: PWORD Position      */
+#define GPIO_PORT_W184_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos)                /*!< GPIO_PORT W184: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W185  -----------------------------------------
+#define GPIO_PORT_W185_PWORD_Pos                              0                                                         /*!< GPIO_PORT W185: PWORD Position      */
+#define GPIO_PORT_W185_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos)                /*!< GPIO_PORT W185: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W186  -----------------------------------------
+#define GPIO_PORT_W186_PWORD_Pos                              0                                                         /*!< GPIO_PORT W186: PWORD Position      */
+#define GPIO_PORT_W186_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos)                /*!< GPIO_PORT W186: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W187  -----------------------------------------
+#define GPIO_PORT_W187_PWORD_Pos                              0                                                         /*!< GPIO_PORT W187: PWORD Position      */
+#define GPIO_PORT_W187_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos)                /*!< GPIO_PORT W187: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W188  -----------------------------------------
+#define GPIO_PORT_W188_PWORD_Pos                              0                                                         /*!< GPIO_PORT W188: PWORD Position      */
+#define GPIO_PORT_W188_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos)                /*!< GPIO_PORT W188: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W189  -----------------------------------------
+#define GPIO_PORT_W189_PWORD_Pos                              0                                                         /*!< GPIO_PORT W189: PWORD Position      */
+#define GPIO_PORT_W189_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos)                /*!< GPIO_PORT W189: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W190  -----------------------------------------
+#define GPIO_PORT_W190_PWORD_Pos                              0                                                         /*!< GPIO_PORT W190: PWORD Position      */
+#define GPIO_PORT_W190_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos)                /*!< GPIO_PORT W190: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W191  -----------------------------------------
+#define GPIO_PORT_W191_PWORD_Pos                              0                                                         /*!< GPIO_PORT W191: PWORD Position      */
+#define GPIO_PORT_W191_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos)                /*!< GPIO_PORT W191: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W192  -----------------------------------------
+#define GPIO_PORT_W192_PWORD_Pos                              0                                                         /*!< GPIO_PORT W192: PWORD Position      */
+#define GPIO_PORT_W192_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos)                /*!< GPIO_PORT W192: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W193  -----------------------------------------
+#define GPIO_PORT_W193_PWORD_Pos                              0                                                         /*!< GPIO_PORT W193: PWORD Position      */
+#define GPIO_PORT_W193_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos)                /*!< GPIO_PORT W193: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W194  -----------------------------------------
+#define GPIO_PORT_W194_PWORD_Pos                              0                                                         /*!< GPIO_PORT W194: PWORD Position      */
+#define GPIO_PORT_W194_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos)                /*!< GPIO_PORT W194: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W195  -----------------------------------------
+#define GPIO_PORT_W195_PWORD_Pos                              0                                                         /*!< GPIO_PORT W195: PWORD Position      */
+#define GPIO_PORT_W195_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos)                /*!< GPIO_PORT W195: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W196  -----------------------------------------
+#define GPIO_PORT_W196_PWORD_Pos                              0                                                         /*!< GPIO_PORT W196: PWORD Position      */
+#define GPIO_PORT_W196_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos)                /*!< GPIO_PORT W196: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W197  -----------------------------------------
+#define GPIO_PORT_W197_PWORD_Pos                              0                                                         /*!< GPIO_PORT W197: PWORD Position      */
+#define GPIO_PORT_W197_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos)                /*!< GPIO_PORT W197: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W198  -----------------------------------------
+#define GPIO_PORT_W198_PWORD_Pos                              0                                                         /*!< GPIO_PORT W198: PWORD Position      */
+#define GPIO_PORT_W198_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos)                /*!< GPIO_PORT W198: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W199  -----------------------------------------
+#define GPIO_PORT_W199_PWORD_Pos                              0                                                         /*!< GPIO_PORT W199: PWORD Position      */
+#define GPIO_PORT_W199_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos)                /*!< GPIO_PORT W199: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W200  -----------------------------------------
+#define GPIO_PORT_W200_PWORD_Pos                              0                                                         /*!< GPIO_PORT W200: PWORD Position      */
+#define GPIO_PORT_W200_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos)                /*!< GPIO_PORT W200: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W201  -----------------------------------------
+#define GPIO_PORT_W201_PWORD_Pos                              0                                                         /*!< GPIO_PORT W201: PWORD Position      */
+#define GPIO_PORT_W201_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos)                /*!< GPIO_PORT W201: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W202  -----------------------------------------
+#define GPIO_PORT_W202_PWORD_Pos                              0                                                         /*!< GPIO_PORT W202: PWORD Position      */
+#define GPIO_PORT_W202_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos)                /*!< GPIO_PORT W202: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W203  -----------------------------------------
+#define GPIO_PORT_W203_PWORD_Pos                              0                                                         /*!< GPIO_PORT W203: PWORD Position      */
+#define GPIO_PORT_W203_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos)                /*!< GPIO_PORT W203: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W204  -----------------------------------------
+#define GPIO_PORT_W204_PWORD_Pos                              0                                                         /*!< GPIO_PORT W204: PWORD Position      */
+#define GPIO_PORT_W204_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos)                /*!< GPIO_PORT W204: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W205  -----------------------------------------
+#define GPIO_PORT_W205_PWORD_Pos                              0                                                         /*!< GPIO_PORT W205: PWORD Position      */
+#define GPIO_PORT_W205_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos)                /*!< GPIO_PORT W205: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W206  -----------------------------------------
+#define GPIO_PORT_W206_PWORD_Pos                              0                                                         /*!< GPIO_PORT W206: PWORD Position      */
+#define GPIO_PORT_W206_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos)                /*!< GPIO_PORT W206: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W207  -----------------------------------------
+#define GPIO_PORT_W207_PWORD_Pos                              0                                                         /*!< GPIO_PORT W207: PWORD Position      */
+#define GPIO_PORT_W207_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos)                /*!< GPIO_PORT W207: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W208  -----------------------------------------
+#define GPIO_PORT_W208_PWORD_Pos                              0                                                         /*!< GPIO_PORT W208: PWORD Position      */
+#define GPIO_PORT_W208_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos)                /*!< GPIO_PORT W208: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W209  -----------------------------------------
+#define GPIO_PORT_W209_PWORD_Pos                              0                                                         /*!< GPIO_PORT W209: PWORD Position      */
+#define GPIO_PORT_W209_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos)                /*!< GPIO_PORT W209: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W210  -----------------------------------------
+#define GPIO_PORT_W210_PWORD_Pos                              0                                                         /*!< GPIO_PORT W210: PWORD Position      */
+#define GPIO_PORT_W210_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos)                /*!< GPIO_PORT W210: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W211  -----------------------------------------
+#define GPIO_PORT_W211_PWORD_Pos                              0                                                         /*!< GPIO_PORT W211: PWORD Position      */
+#define GPIO_PORT_W211_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos)                /*!< GPIO_PORT W211: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W212  -----------------------------------------
+#define GPIO_PORT_W212_PWORD_Pos                              0                                                         /*!< GPIO_PORT W212: PWORD Position      */
+#define GPIO_PORT_W212_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos)                /*!< GPIO_PORT W212: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W213  -----------------------------------------
+#define GPIO_PORT_W213_PWORD_Pos                              0                                                         /*!< GPIO_PORT W213: PWORD Position      */
+#define GPIO_PORT_W213_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos)                /*!< GPIO_PORT W213: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W214  -----------------------------------------
+#define GPIO_PORT_W214_PWORD_Pos                              0                                                         /*!< GPIO_PORT W214: PWORD Position      */
+#define GPIO_PORT_W214_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos)                /*!< GPIO_PORT W214: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W215  -----------------------------------------
+#define GPIO_PORT_W215_PWORD_Pos                              0                                                         /*!< GPIO_PORT W215: PWORD Position      */
+#define GPIO_PORT_W215_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos)                /*!< GPIO_PORT W215: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W216  -----------------------------------------
+#define GPIO_PORT_W216_PWORD_Pos                              0                                                         /*!< GPIO_PORT W216: PWORD Position      */
+#define GPIO_PORT_W216_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos)                /*!< GPIO_PORT W216: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W217  -----------------------------------------
+#define GPIO_PORT_W217_PWORD_Pos                              0                                                         /*!< GPIO_PORT W217: PWORD Position      */
+#define GPIO_PORT_W217_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos)                /*!< GPIO_PORT W217: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W218  -----------------------------------------
+#define GPIO_PORT_W218_PWORD_Pos                              0                                                         /*!< GPIO_PORT W218: PWORD Position      */
+#define GPIO_PORT_W218_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos)                /*!< GPIO_PORT W218: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W219  -----------------------------------------
+#define GPIO_PORT_W219_PWORD_Pos                              0                                                         /*!< GPIO_PORT W219: PWORD Position      */
+#define GPIO_PORT_W219_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos)                /*!< GPIO_PORT W219: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W220  -----------------------------------------
+#define GPIO_PORT_W220_PWORD_Pos                              0                                                         /*!< GPIO_PORT W220: PWORD Position      */
+#define GPIO_PORT_W220_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos)                /*!< GPIO_PORT W220: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W221  -----------------------------------------
+#define GPIO_PORT_W221_PWORD_Pos                              0                                                         /*!< GPIO_PORT W221: PWORD Position      */
+#define GPIO_PORT_W221_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos)                /*!< GPIO_PORT W221: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W222  -----------------------------------------
+#define GPIO_PORT_W222_PWORD_Pos                              0                                                         /*!< GPIO_PORT W222: PWORD Position      */
+#define GPIO_PORT_W222_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos)                /*!< GPIO_PORT W222: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W223  -----------------------------------------
+#define GPIO_PORT_W223_PWORD_Pos                              0                                                         /*!< GPIO_PORT W223: PWORD Position      */
+#define GPIO_PORT_W223_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos)                /*!< GPIO_PORT W223: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W224  -----------------------------------------
+#define GPIO_PORT_W224_PWORD_Pos                              0                                                         /*!< GPIO_PORT W224: PWORD Position      */
+#define GPIO_PORT_W224_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos)                /*!< GPIO_PORT W224: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W225  -----------------------------------------
+#define GPIO_PORT_W225_PWORD_Pos                              0                                                         /*!< GPIO_PORT W225: PWORD Position      */
+#define GPIO_PORT_W225_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos)                /*!< GPIO_PORT W225: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W226  -----------------------------------------
+#define GPIO_PORT_W226_PWORD_Pos                              0                                                         /*!< GPIO_PORT W226: PWORD Position      */
+#define GPIO_PORT_W226_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos)                /*!< GPIO_PORT W226: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W227  -----------------------------------------
+#define GPIO_PORT_W227_PWORD_Pos                              0                                                         /*!< GPIO_PORT W227: PWORD Position      */
+#define GPIO_PORT_W227_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos)                /*!< GPIO_PORT W227: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W228  -----------------------------------------
+#define GPIO_PORT_W228_PWORD_Pos                              0                                                         /*!< GPIO_PORT W228: PWORD Position      */
+#define GPIO_PORT_W228_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos)                /*!< GPIO_PORT W228: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W229  -----------------------------------------
+#define GPIO_PORT_W229_PWORD_Pos                              0                                                         /*!< GPIO_PORT W229: PWORD Position      */
+#define GPIO_PORT_W229_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos)                /*!< GPIO_PORT W229: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W230  -----------------------------------------
+#define GPIO_PORT_W230_PWORD_Pos                              0                                                         /*!< GPIO_PORT W230: PWORD Position      */
+#define GPIO_PORT_W230_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos)                /*!< GPIO_PORT W230: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W231  -----------------------------------------
+#define GPIO_PORT_W231_PWORD_Pos                              0                                                         /*!< GPIO_PORT W231: PWORD Position      */
+#define GPIO_PORT_W231_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos)                /*!< GPIO_PORT W231: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W232  -----------------------------------------
+#define GPIO_PORT_W232_PWORD_Pos                              0                                                         /*!< GPIO_PORT W232: PWORD Position      */
+#define GPIO_PORT_W232_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos)                /*!< GPIO_PORT W232: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W233  -----------------------------------------
+#define GPIO_PORT_W233_PWORD_Pos                              0                                                         /*!< GPIO_PORT W233: PWORD Position      */
+#define GPIO_PORT_W233_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos)                /*!< GPIO_PORT W233: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W234  -----------------------------------------
+#define GPIO_PORT_W234_PWORD_Pos                              0                                                         /*!< GPIO_PORT W234: PWORD Position      */
+#define GPIO_PORT_W234_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos)                /*!< GPIO_PORT W234: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W235  -----------------------------------------
+#define GPIO_PORT_W235_PWORD_Pos                              0                                                         /*!< GPIO_PORT W235: PWORD Position      */
+#define GPIO_PORT_W235_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos)                /*!< GPIO_PORT W235: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W236  -----------------------------------------
+#define GPIO_PORT_W236_PWORD_Pos                              0                                                         /*!< GPIO_PORT W236: PWORD Position      */
+#define GPIO_PORT_W236_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos)                /*!< GPIO_PORT W236: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W237  -----------------------------------------
+#define GPIO_PORT_W237_PWORD_Pos                              0                                                         /*!< GPIO_PORT W237: PWORD Position      */
+#define GPIO_PORT_W237_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos)                /*!< GPIO_PORT W237: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W238  -----------------------------------------
+#define GPIO_PORT_W238_PWORD_Pos                              0                                                         /*!< GPIO_PORT W238: PWORD Position      */
+#define GPIO_PORT_W238_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos)                /*!< GPIO_PORT W238: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W239  -----------------------------------------
+#define GPIO_PORT_W239_PWORD_Pos                              0                                                         /*!< GPIO_PORT W239: PWORD Position      */
+#define GPIO_PORT_W239_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos)                /*!< GPIO_PORT W239: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W240  -----------------------------------------
+#define GPIO_PORT_W240_PWORD_Pos                              0                                                         /*!< GPIO_PORT W240: PWORD Position      */
+#define GPIO_PORT_W240_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos)                /*!< GPIO_PORT W240: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W241  -----------------------------------------
+#define GPIO_PORT_W241_PWORD_Pos                              0                                                         /*!< GPIO_PORT W241: PWORD Position      */
+#define GPIO_PORT_W241_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos)                /*!< GPIO_PORT W241: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W242  -----------------------------------------
+#define GPIO_PORT_W242_PWORD_Pos                              0                                                         /*!< GPIO_PORT W242: PWORD Position      */
+#define GPIO_PORT_W242_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos)                /*!< GPIO_PORT W242: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W243  -----------------------------------------
+#define GPIO_PORT_W243_PWORD_Pos                              0                                                         /*!< GPIO_PORT W243: PWORD Position      */
+#define GPIO_PORT_W243_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos)                /*!< GPIO_PORT W243: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W244  -----------------------------------------
+#define GPIO_PORT_W244_PWORD_Pos                              0                                                         /*!< GPIO_PORT W244: PWORD Position      */
+#define GPIO_PORT_W244_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos)                /*!< GPIO_PORT W244: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W245  -----------------------------------------
+#define GPIO_PORT_W245_PWORD_Pos                              0                                                         /*!< GPIO_PORT W245: PWORD Position      */
+#define GPIO_PORT_W245_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos)                /*!< GPIO_PORT W245: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W246  -----------------------------------------
+#define GPIO_PORT_W246_PWORD_Pos                              0                                                         /*!< GPIO_PORT W246: PWORD Position      */
+#define GPIO_PORT_W246_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos)                /*!< GPIO_PORT W246: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W247  -----------------------------------------
+#define GPIO_PORT_W247_PWORD_Pos                              0                                                         /*!< GPIO_PORT W247: PWORD Position      */
+#define GPIO_PORT_W247_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos)                /*!< GPIO_PORT W247: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W248  -----------------------------------------
+#define GPIO_PORT_W248_PWORD_Pos                              0                                                         /*!< GPIO_PORT W248: PWORD Position      */
+#define GPIO_PORT_W248_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos)                /*!< GPIO_PORT W248: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W249  -----------------------------------------
+#define GPIO_PORT_W249_PWORD_Pos                              0                                                         /*!< GPIO_PORT W249: PWORD Position      */
+#define GPIO_PORT_W249_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos)                /*!< GPIO_PORT W249: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W250  -----------------------------------------
+#define GPIO_PORT_W250_PWORD_Pos                              0                                                         /*!< GPIO_PORT W250: PWORD Position      */
+#define GPIO_PORT_W250_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos)                /*!< GPIO_PORT W250: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W251  -----------------------------------------
+#define GPIO_PORT_W251_PWORD_Pos                              0                                                         /*!< GPIO_PORT W251: PWORD Position      */
+#define GPIO_PORT_W251_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos)                /*!< GPIO_PORT W251: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W252  -----------------------------------------
+#define GPIO_PORT_W252_PWORD_Pos                              0                                                         /*!< GPIO_PORT W252: PWORD Position      */
+#define GPIO_PORT_W252_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos)                /*!< GPIO_PORT W252: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W253  -----------------------------------------
+#define GPIO_PORT_W253_PWORD_Pos                              0                                                         /*!< GPIO_PORT W253: PWORD Position      */
+#define GPIO_PORT_W253_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos)                /*!< GPIO_PORT W253: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W254  -----------------------------------------
+#define GPIO_PORT_W254_PWORD_Pos                              0                                                         /*!< GPIO_PORT W254: PWORD Position      */
+#define GPIO_PORT_W254_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos)                /*!< GPIO_PORT W254: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W255  -----------------------------------------
+#define GPIO_PORT_W255_PWORD_Pos                              0                                                         /*!< GPIO_PORT W255: PWORD Position      */
+#define GPIO_PORT_W255_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos)                /*!< GPIO_PORT W255: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_DIR0  -----------------------------------------
+#define GPIO_PORT_DIR0_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR0: DIRP0 Position      */
+#define GPIO_PORT_DIR0_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos)                      /*!< GPIO_PORT DIR0: DIRP0 Mask          */
+#define GPIO_PORT_DIR0_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR0: DIRP1 Position      */
+#define GPIO_PORT_DIR0_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos)                      /*!< GPIO_PORT DIR0: DIRP1 Mask          */
+#define GPIO_PORT_DIR0_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR0: DIRP2 Position      */
+#define GPIO_PORT_DIR0_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos)                      /*!< GPIO_PORT DIR0: DIRP2 Mask          */
+#define GPIO_PORT_DIR0_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR0: DIRP3 Position      */
+#define GPIO_PORT_DIR0_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos)                      /*!< GPIO_PORT DIR0: DIRP3 Mask          */
+#define GPIO_PORT_DIR0_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR0: DIRP4 Position      */
+#define GPIO_PORT_DIR0_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos)                      /*!< GPIO_PORT DIR0: DIRP4 Mask          */
+#define GPIO_PORT_DIR0_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR0: DIRP5 Position      */
+#define GPIO_PORT_DIR0_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos)                      /*!< GPIO_PORT DIR0: DIRP5 Mask          */
+#define GPIO_PORT_DIR0_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR0: DIRP6 Position      */
+#define GPIO_PORT_DIR0_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos)                      /*!< GPIO_PORT DIR0: DIRP6 Mask          */
+#define GPIO_PORT_DIR0_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR0: DIRP7 Position      */
+#define GPIO_PORT_DIR0_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos)                      /*!< GPIO_PORT DIR0: DIRP7 Mask          */
+#define GPIO_PORT_DIR0_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR0: DIRP8 Position      */
+#define GPIO_PORT_DIR0_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos)                      /*!< GPIO_PORT DIR0: DIRP8 Mask          */
+#define GPIO_PORT_DIR0_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR0: DIRP9 Position      */
+#define GPIO_PORT_DIR0_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos)                      /*!< GPIO_PORT DIR0: DIRP9 Mask          */
+#define GPIO_PORT_DIR0_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR0: DIRP10 Position     */
+#define GPIO_PORT_DIR0_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos)                     /*!< GPIO_PORT DIR0: DIRP10 Mask         */
+#define GPIO_PORT_DIR0_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR0: DIRP11 Position     */
+#define GPIO_PORT_DIR0_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos)                     /*!< GPIO_PORT DIR0: DIRP11 Mask         */
+#define GPIO_PORT_DIR0_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR0: DIRP12 Position     */
+#define GPIO_PORT_DIR0_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos)                     /*!< GPIO_PORT DIR0: DIRP12 Mask         */
+#define GPIO_PORT_DIR0_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR0: DIRP13 Position     */
+#define GPIO_PORT_DIR0_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos)                     /*!< GPIO_PORT DIR0: DIRP13 Mask         */
+#define GPIO_PORT_DIR0_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR0: DIRP14 Position     */
+#define GPIO_PORT_DIR0_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos)                     /*!< GPIO_PORT DIR0: DIRP14 Mask         */
+#define GPIO_PORT_DIR0_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR0: DIRP15 Position     */
+#define GPIO_PORT_DIR0_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos)                     /*!< GPIO_PORT DIR0: DIRP15 Mask         */
+#define GPIO_PORT_DIR0_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR0: DIRP16 Position     */
+#define GPIO_PORT_DIR0_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos)                     /*!< GPIO_PORT DIR0: DIRP16 Mask         */
+#define GPIO_PORT_DIR0_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR0: DIRP17 Position     */
+#define GPIO_PORT_DIR0_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos)                     /*!< GPIO_PORT DIR0: DIRP17 Mask         */
+#define GPIO_PORT_DIR0_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR0: DIRP18 Position     */
+#define GPIO_PORT_DIR0_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos)                     /*!< GPIO_PORT DIR0: DIRP18 Mask         */
+#define GPIO_PORT_DIR0_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR0: DIRP19 Position     */
+#define GPIO_PORT_DIR0_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos)                     /*!< GPIO_PORT DIR0: DIRP19 Mask         */
+#define GPIO_PORT_DIR0_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR0: DIRP20 Position     */
+#define GPIO_PORT_DIR0_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos)                     /*!< GPIO_PORT DIR0: DIRP20 Mask         */
+#define GPIO_PORT_DIR0_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR0: DIRP21 Position     */
+#define GPIO_PORT_DIR0_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos)                     /*!< GPIO_PORT DIR0: DIRP21 Mask         */
+#define GPIO_PORT_DIR0_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR0: DIRP22 Position     */
+#define GPIO_PORT_DIR0_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos)                     /*!< GPIO_PORT DIR0: DIRP22 Mask         */
+#define GPIO_PORT_DIR0_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR0: DIRP23 Position     */
+#define GPIO_PORT_DIR0_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos)                     /*!< GPIO_PORT DIR0: DIRP23 Mask         */
+#define GPIO_PORT_DIR0_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR0: DIRP24 Position     */
+#define GPIO_PORT_DIR0_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos)                     /*!< GPIO_PORT DIR0: DIRP24 Mask         */
+#define GPIO_PORT_DIR0_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR0: DIRP25 Position     */
+#define GPIO_PORT_DIR0_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos)                     /*!< GPIO_PORT DIR0: DIRP25 Mask         */
+#define GPIO_PORT_DIR0_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR0: DIRP26 Position     */
+#define GPIO_PORT_DIR0_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos)                     /*!< GPIO_PORT DIR0: DIRP26 Mask         */
+#define GPIO_PORT_DIR0_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR0: DIRP27 Position     */
+#define GPIO_PORT_DIR0_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos)                     /*!< GPIO_PORT DIR0: DIRP27 Mask         */
+#define GPIO_PORT_DIR0_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR0: DIRP28 Position     */
+#define GPIO_PORT_DIR0_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos)                     /*!< GPIO_PORT DIR0: DIRP28 Mask         */
+#define GPIO_PORT_DIR0_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR0: DIRP29 Position     */
+#define GPIO_PORT_DIR0_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos)                     /*!< GPIO_PORT DIR0: DIRP29 Mask         */
+#define GPIO_PORT_DIR0_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR0: DIRP30 Position     */
+#define GPIO_PORT_DIR0_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos)                     /*!< GPIO_PORT DIR0: DIRP30 Mask         */
+#define GPIO_PORT_DIR0_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR0: DIRP31 Position     */
+#define GPIO_PORT_DIR0_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos)                     /*!< GPIO_PORT DIR0: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR1  -----------------------------------------
+#define GPIO_PORT_DIR1_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR1: DIRP0 Position      */
+#define GPIO_PORT_DIR1_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos)                      /*!< GPIO_PORT DIR1: DIRP0 Mask          */
+#define GPIO_PORT_DIR1_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR1: DIRP1 Position      */
+#define GPIO_PORT_DIR1_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos)                      /*!< GPIO_PORT DIR1: DIRP1 Mask          */
+#define GPIO_PORT_DIR1_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR1: DIRP2 Position      */
+#define GPIO_PORT_DIR1_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos)                      /*!< GPIO_PORT DIR1: DIRP2 Mask          */
+#define GPIO_PORT_DIR1_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR1: DIRP3 Position      */
+#define GPIO_PORT_DIR1_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos)                      /*!< GPIO_PORT DIR1: DIRP3 Mask          */
+#define GPIO_PORT_DIR1_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR1: DIRP4 Position      */
+#define GPIO_PORT_DIR1_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos)                      /*!< GPIO_PORT DIR1: DIRP4 Mask          */
+#define GPIO_PORT_DIR1_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR1: DIRP5 Position      */
+#define GPIO_PORT_DIR1_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos)                      /*!< GPIO_PORT DIR1: DIRP5 Mask          */
+#define GPIO_PORT_DIR1_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR1: DIRP6 Position      */
+#define GPIO_PORT_DIR1_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos)                      /*!< GPIO_PORT DIR1: DIRP6 Mask          */
+#define GPIO_PORT_DIR1_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR1: DIRP7 Position      */
+#define GPIO_PORT_DIR1_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos)                      /*!< GPIO_PORT DIR1: DIRP7 Mask          */
+#define GPIO_PORT_DIR1_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR1: DIRP8 Position      */
+#define GPIO_PORT_DIR1_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos)                      /*!< GPIO_PORT DIR1: DIRP8 Mask          */
+#define GPIO_PORT_DIR1_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR1: DIRP9 Position      */
+#define GPIO_PORT_DIR1_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos)                      /*!< GPIO_PORT DIR1: DIRP9 Mask          */
+#define GPIO_PORT_DIR1_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR1: DIRP10 Position     */
+#define GPIO_PORT_DIR1_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos)                     /*!< GPIO_PORT DIR1: DIRP10 Mask         */
+#define GPIO_PORT_DIR1_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR1: DIRP11 Position     */
+#define GPIO_PORT_DIR1_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos)                     /*!< GPIO_PORT DIR1: DIRP11 Mask         */
+#define GPIO_PORT_DIR1_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR1: DIRP12 Position     */
+#define GPIO_PORT_DIR1_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos)                     /*!< GPIO_PORT DIR1: DIRP12 Mask         */
+#define GPIO_PORT_DIR1_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR1: DIRP13 Position     */
+#define GPIO_PORT_DIR1_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos)                     /*!< GPIO_PORT DIR1: DIRP13 Mask         */
+#define GPIO_PORT_DIR1_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR1: DIRP14 Position     */
+#define GPIO_PORT_DIR1_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos)                     /*!< GPIO_PORT DIR1: DIRP14 Mask         */
+#define GPIO_PORT_DIR1_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR1: DIRP15 Position     */
+#define GPIO_PORT_DIR1_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos)                     /*!< GPIO_PORT DIR1: DIRP15 Mask         */
+#define GPIO_PORT_DIR1_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR1: DIRP16 Position     */
+#define GPIO_PORT_DIR1_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos)                     /*!< GPIO_PORT DIR1: DIRP16 Mask         */
+#define GPIO_PORT_DIR1_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR1: DIRP17 Position     */
+#define GPIO_PORT_DIR1_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos)                     /*!< GPIO_PORT DIR1: DIRP17 Mask         */
+#define GPIO_PORT_DIR1_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR1: DIRP18 Position     */
+#define GPIO_PORT_DIR1_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos)                     /*!< GPIO_PORT DIR1: DIRP18 Mask         */
+#define GPIO_PORT_DIR1_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR1: DIRP19 Position     */
+#define GPIO_PORT_DIR1_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos)                     /*!< GPIO_PORT DIR1: DIRP19 Mask         */
+#define GPIO_PORT_DIR1_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR1: DIRP20 Position     */
+#define GPIO_PORT_DIR1_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos)                     /*!< GPIO_PORT DIR1: DIRP20 Mask         */
+#define GPIO_PORT_DIR1_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR1: DIRP21 Position     */
+#define GPIO_PORT_DIR1_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos)                     /*!< GPIO_PORT DIR1: DIRP21 Mask         */
+#define GPIO_PORT_DIR1_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR1: DIRP22 Position     */
+#define GPIO_PORT_DIR1_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos)                     /*!< GPIO_PORT DIR1: DIRP22 Mask         */
+#define GPIO_PORT_DIR1_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR1: DIRP23 Position     */
+#define GPIO_PORT_DIR1_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos)                     /*!< GPIO_PORT DIR1: DIRP23 Mask         */
+#define GPIO_PORT_DIR1_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR1: DIRP24 Position     */
+#define GPIO_PORT_DIR1_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos)                     /*!< GPIO_PORT DIR1: DIRP24 Mask         */
+#define GPIO_PORT_DIR1_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR1: DIRP25 Position     */
+#define GPIO_PORT_DIR1_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos)                     /*!< GPIO_PORT DIR1: DIRP25 Mask         */
+#define GPIO_PORT_DIR1_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR1: DIRP26 Position     */
+#define GPIO_PORT_DIR1_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos)                     /*!< GPIO_PORT DIR1: DIRP26 Mask         */
+#define GPIO_PORT_DIR1_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR1: DIRP27 Position     */
+#define GPIO_PORT_DIR1_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos)                     /*!< GPIO_PORT DIR1: DIRP27 Mask         */
+#define GPIO_PORT_DIR1_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR1: DIRP28 Position     */
+#define GPIO_PORT_DIR1_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos)                     /*!< GPIO_PORT DIR1: DIRP28 Mask         */
+#define GPIO_PORT_DIR1_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR1: DIRP29 Position     */
+#define GPIO_PORT_DIR1_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos)                     /*!< GPIO_PORT DIR1: DIRP29 Mask         */
+#define GPIO_PORT_DIR1_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR1: DIRP30 Position     */
+#define GPIO_PORT_DIR1_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos)                     /*!< GPIO_PORT DIR1: DIRP30 Mask         */
+#define GPIO_PORT_DIR1_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR1: DIRP31 Position     */
+#define GPIO_PORT_DIR1_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos)                     /*!< GPIO_PORT DIR1: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR2  -----------------------------------------
+#define GPIO_PORT_DIR2_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR2: DIRP0 Position      */
+#define GPIO_PORT_DIR2_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos)                      /*!< GPIO_PORT DIR2: DIRP0 Mask          */
+#define GPIO_PORT_DIR2_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR2: DIRP1 Position      */
+#define GPIO_PORT_DIR2_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos)                      /*!< GPIO_PORT DIR2: DIRP1 Mask          */
+#define GPIO_PORT_DIR2_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR2: DIRP2 Position      */
+#define GPIO_PORT_DIR2_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos)                      /*!< GPIO_PORT DIR2: DIRP2 Mask          */
+#define GPIO_PORT_DIR2_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR2: DIRP3 Position      */
+#define GPIO_PORT_DIR2_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos)                      /*!< GPIO_PORT DIR2: DIRP3 Mask          */
+#define GPIO_PORT_DIR2_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR2: DIRP4 Position      */
+#define GPIO_PORT_DIR2_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos)                      /*!< GPIO_PORT DIR2: DIRP4 Mask          */
+#define GPIO_PORT_DIR2_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR2: DIRP5 Position      */
+#define GPIO_PORT_DIR2_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos)                      /*!< GPIO_PORT DIR2: DIRP5 Mask          */
+#define GPIO_PORT_DIR2_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR2: DIRP6 Position      */
+#define GPIO_PORT_DIR2_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos)                      /*!< GPIO_PORT DIR2: DIRP6 Mask          */
+#define GPIO_PORT_DIR2_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR2: DIRP7 Position      */
+#define GPIO_PORT_DIR2_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos)                      /*!< GPIO_PORT DIR2: DIRP7 Mask          */
+#define GPIO_PORT_DIR2_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR2: DIRP8 Position      */
+#define GPIO_PORT_DIR2_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos)                      /*!< GPIO_PORT DIR2: DIRP8 Mask          */
+#define GPIO_PORT_DIR2_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR2: DIRP9 Position      */
+#define GPIO_PORT_DIR2_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos)                      /*!< GPIO_PORT DIR2: DIRP9 Mask          */
+#define GPIO_PORT_DIR2_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR2: DIRP10 Position     */
+#define GPIO_PORT_DIR2_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos)                     /*!< GPIO_PORT DIR2: DIRP10 Mask         */
+#define GPIO_PORT_DIR2_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR2: DIRP11 Position     */
+#define GPIO_PORT_DIR2_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos)                     /*!< GPIO_PORT DIR2: DIRP11 Mask         */
+#define GPIO_PORT_DIR2_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR2: DIRP12 Position     */
+#define GPIO_PORT_DIR2_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos)                     /*!< GPIO_PORT DIR2: DIRP12 Mask         */
+#define GPIO_PORT_DIR2_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR2: DIRP13 Position     */
+#define GPIO_PORT_DIR2_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos)                     /*!< GPIO_PORT DIR2: DIRP13 Mask         */
+#define GPIO_PORT_DIR2_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR2: DIRP14 Position     */
+#define GPIO_PORT_DIR2_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos)                     /*!< GPIO_PORT DIR2: DIRP14 Mask         */
+#define GPIO_PORT_DIR2_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR2: DIRP15 Position     */
+#define GPIO_PORT_DIR2_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos)                     /*!< GPIO_PORT DIR2: DIRP15 Mask         */
+#define GPIO_PORT_DIR2_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR2: DIRP16 Position     */
+#define GPIO_PORT_DIR2_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos)                     /*!< GPIO_PORT DIR2: DIRP16 Mask         */
+#define GPIO_PORT_DIR2_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR2: DIRP17 Position     */
+#define GPIO_PORT_DIR2_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos)                     /*!< GPIO_PORT DIR2: DIRP17 Mask         */
+#define GPIO_PORT_DIR2_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR2: DIRP18 Position     */
+#define GPIO_PORT_DIR2_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos)                     /*!< GPIO_PORT DIR2: DIRP18 Mask         */
+#define GPIO_PORT_DIR2_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR2: DIRP19 Position     */
+#define GPIO_PORT_DIR2_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos)                     /*!< GPIO_PORT DIR2: DIRP19 Mask         */
+#define GPIO_PORT_DIR2_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR2: DIRP20 Position     */
+#define GPIO_PORT_DIR2_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos)                     /*!< GPIO_PORT DIR2: DIRP20 Mask         */
+#define GPIO_PORT_DIR2_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR2: DIRP21 Position     */
+#define GPIO_PORT_DIR2_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos)                     /*!< GPIO_PORT DIR2: DIRP21 Mask         */
+#define GPIO_PORT_DIR2_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR2: DIRP22 Position     */
+#define GPIO_PORT_DIR2_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos)                     /*!< GPIO_PORT DIR2: DIRP22 Mask         */
+#define GPIO_PORT_DIR2_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR2: DIRP23 Position     */
+#define GPIO_PORT_DIR2_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos)                     /*!< GPIO_PORT DIR2: DIRP23 Mask         */
+#define GPIO_PORT_DIR2_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR2: DIRP24 Position     */
+#define GPIO_PORT_DIR2_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos)                     /*!< GPIO_PORT DIR2: DIRP24 Mask         */
+#define GPIO_PORT_DIR2_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR2: DIRP25 Position     */
+#define GPIO_PORT_DIR2_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos)                     /*!< GPIO_PORT DIR2: DIRP25 Mask         */
+#define GPIO_PORT_DIR2_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR2: DIRP26 Position     */
+#define GPIO_PORT_DIR2_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos)                     /*!< GPIO_PORT DIR2: DIRP26 Mask         */
+#define GPIO_PORT_DIR2_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR2: DIRP27 Position     */
+#define GPIO_PORT_DIR2_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos)                     /*!< GPIO_PORT DIR2: DIRP27 Mask         */
+#define GPIO_PORT_DIR2_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR2: DIRP28 Position     */
+#define GPIO_PORT_DIR2_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos)                     /*!< GPIO_PORT DIR2: DIRP28 Mask         */
+#define GPIO_PORT_DIR2_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR2: DIRP29 Position     */
+#define GPIO_PORT_DIR2_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos)                     /*!< GPIO_PORT DIR2: DIRP29 Mask         */
+#define GPIO_PORT_DIR2_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR2: DIRP30 Position     */
+#define GPIO_PORT_DIR2_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos)                     /*!< GPIO_PORT DIR2: DIRP30 Mask         */
+#define GPIO_PORT_DIR2_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR2: DIRP31 Position     */
+#define GPIO_PORT_DIR2_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos)                     /*!< GPIO_PORT DIR2: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR3  -----------------------------------------
+#define GPIO_PORT_DIR3_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR3: DIRP0 Position      */
+#define GPIO_PORT_DIR3_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos)                      /*!< GPIO_PORT DIR3: DIRP0 Mask          */
+#define GPIO_PORT_DIR3_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR3: DIRP1 Position      */
+#define GPIO_PORT_DIR3_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos)                      /*!< GPIO_PORT DIR3: DIRP1 Mask          */
+#define GPIO_PORT_DIR3_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR3: DIRP2 Position      */
+#define GPIO_PORT_DIR3_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos)                      /*!< GPIO_PORT DIR3: DIRP2 Mask          */
+#define GPIO_PORT_DIR3_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR3: DIRP3 Position      */
+#define GPIO_PORT_DIR3_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos)                      /*!< GPIO_PORT DIR3: DIRP3 Mask          */
+#define GPIO_PORT_DIR3_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR3: DIRP4 Position      */
+#define GPIO_PORT_DIR3_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos)                      /*!< GPIO_PORT DIR3: DIRP4 Mask          */
+#define GPIO_PORT_DIR3_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR3: DIRP5 Position      */
+#define GPIO_PORT_DIR3_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos)                      /*!< GPIO_PORT DIR3: DIRP5 Mask          */
+#define GPIO_PORT_DIR3_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR3: DIRP6 Position      */
+#define GPIO_PORT_DIR3_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos)                      /*!< GPIO_PORT DIR3: DIRP6 Mask          */
+#define GPIO_PORT_DIR3_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR3: DIRP7 Position      */
+#define GPIO_PORT_DIR3_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos)                      /*!< GPIO_PORT DIR3: DIRP7 Mask          */
+#define GPIO_PORT_DIR3_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR3: DIRP8 Position      */
+#define GPIO_PORT_DIR3_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos)                      /*!< GPIO_PORT DIR3: DIRP8 Mask          */
+#define GPIO_PORT_DIR3_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR3: DIRP9 Position      */
+#define GPIO_PORT_DIR3_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos)                      /*!< GPIO_PORT DIR3: DIRP9 Mask          */
+#define GPIO_PORT_DIR3_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR3: DIRP10 Position     */
+#define GPIO_PORT_DIR3_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos)                     /*!< GPIO_PORT DIR3: DIRP10 Mask         */
+#define GPIO_PORT_DIR3_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR3: DIRP11 Position     */
+#define GPIO_PORT_DIR3_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos)                     /*!< GPIO_PORT DIR3: DIRP11 Mask         */
+#define GPIO_PORT_DIR3_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR3: DIRP12 Position     */
+#define GPIO_PORT_DIR3_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos)                     /*!< GPIO_PORT DIR3: DIRP12 Mask         */
+#define GPIO_PORT_DIR3_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR3: DIRP13 Position     */
+#define GPIO_PORT_DIR3_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos)                     /*!< GPIO_PORT DIR3: DIRP13 Mask         */
+#define GPIO_PORT_DIR3_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR3: DIRP14 Position     */
+#define GPIO_PORT_DIR3_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos)                     /*!< GPIO_PORT DIR3: DIRP14 Mask         */
+#define GPIO_PORT_DIR3_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR3: DIRP15 Position     */
+#define GPIO_PORT_DIR3_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos)                     /*!< GPIO_PORT DIR3: DIRP15 Mask         */
+#define GPIO_PORT_DIR3_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR3: DIRP16 Position     */
+#define GPIO_PORT_DIR3_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos)                     /*!< GPIO_PORT DIR3: DIRP16 Mask         */
+#define GPIO_PORT_DIR3_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR3: DIRP17 Position     */
+#define GPIO_PORT_DIR3_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos)                     /*!< GPIO_PORT DIR3: DIRP17 Mask         */
+#define GPIO_PORT_DIR3_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR3: DIRP18 Position     */
+#define GPIO_PORT_DIR3_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos)                     /*!< GPIO_PORT DIR3: DIRP18 Mask         */
+#define GPIO_PORT_DIR3_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR3: DIRP19 Position     */
+#define GPIO_PORT_DIR3_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos)                     /*!< GPIO_PORT DIR3: DIRP19 Mask         */
+#define GPIO_PORT_DIR3_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR3: DIRP20 Position     */
+#define GPIO_PORT_DIR3_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos)                     /*!< GPIO_PORT DIR3: DIRP20 Mask         */
+#define GPIO_PORT_DIR3_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR3: DIRP21 Position     */
+#define GPIO_PORT_DIR3_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos)                     /*!< GPIO_PORT DIR3: DIRP21 Mask         */
+#define GPIO_PORT_DIR3_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR3: DIRP22 Position     */
+#define GPIO_PORT_DIR3_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos)                     /*!< GPIO_PORT DIR3: DIRP22 Mask         */
+#define GPIO_PORT_DIR3_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR3: DIRP23 Position     */
+#define GPIO_PORT_DIR3_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos)                     /*!< GPIO_PORT DIR3: DIRP23 Mask         */
+#define GPIO_PORT_DIR3_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR3: DIRP24 Position     */
+#define GPIO_PORT_DIR3_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos)                     /*!< GPIO_PORT DIR3: DIRP24 Mask         */
+#define GPIO_PORT_DIR3_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR3: DIRP25 Position     */
+#define GPIO_PORT_DIR3_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos)                     /*!< GPIO_PORT DIR3: DIRP25 Mask         */
+#define GPIO_PORT_DIR3_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR3: DIRP26 Position     */
+#define GPIO_PORT_DIR3_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos)                     /*!< GPIO_PORT DIR3: DIRP26 Mask         */
+#define GPIO_PORT_DIR3_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR3: DIRP27 Position     */
+#define GPIO_PORT_DIR3_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos)                     /*!< GPIO_PORT DIR3: DIRP27 Mask         */
+#define GPIO_PORT_DIR3_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR3: DIRP28 Position     */
+#define GPIO_PORT_DIR3_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos)                     /*!< GPIO_PORT DIR3: DIRP28 Mask         */
+#define GPIO_PORT_DIR3_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR3: DIRP29 Position     */
+#define GPIO_PORT_DIR3_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos)                     /*!< GPIO_PORT DIR3: DIRP29 Mask         */
+#define GPIO_PORT_DIR3_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR3: DIRP30 Position     */
+#define GPIO_PORT_DIR3_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos)                     /*!< GPIO_PORT DIR3: DIRP30 Mask         */
+#define GPIO_PORT_DIR3_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR3: DIRP31 Position     */
+#define GPIO_PORT_DIR3_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos)                     /*!< GPIO_PORT DIR3: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR4  -----------------------------------------
+#define GPIO_PORT_DIR4_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR4: DIRP0 Position      */
+#define GPIO_PORT_DIR4_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos)                      /*!< GPIO_PORT DIR4: DIRP0 Mask          */
+#define GPIO_PORT_DIR4_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR4: DIRP1 Position      */
+#define GPIO_PORT_DIR4_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos)                      /*!< GPIO_PORT DIR4: DIRP1 Mask          */
+#define GPIO_PORT_DIR4_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR4: DIRP2 Position      */
+#define GPIO_PORT_DIR4_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos)                      /*!< GPIO_PORT DIR4: DIRP2 Mask          */
+#define GPIO_PORT_DIR4_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR4: DIRP3 Position      */
+#define GPIO_PORT_DIR4_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos)                      /*!< GPIO_PORT DIR4: DIRP3 Mask          */
+#define GPIO_PORT_DIR4_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR4: DIRP4 Position      */
+#define GPIO_PORT_DIR4_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos)                      /*!< GPIO_PORT DIR4: DIRP4 Mask          */
+#define GPIO_PORT_DIR4_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR4: DIRP5 Position      */
+#define GPIO_PORT_DIR4_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos)                      /*!< GPIO_PORT DIR4: DIRP5 Mask          */
+#define GPIO_PORT_DIR4_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR4: DIRP6 Position      */
+#define GPIO_PORT_DIR4_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos)                      /*!< GPIO_PORT DIR4: DIRP6 Mask          */
+#define GPIO_PORT_DIR4_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR4: DIRP7 Position      */
+#define GPIO_PORT_DIR4_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos)                      /*!< GPIO_PORT DIR4: DIRP7 Mask          */
+#define GPIO_PORT_DIR4_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR4: DIRP8 Position      */
+#define GPIO_PORT_DIR4_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos)                      /*!< GPIO_PORT DIR4: DIRP8 Mask          */
+#define GPIO_PORT_DIR4_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR4: DIRP9 Position      */
+#define GPIO_PORT_DIR4_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos)                      /*!< GPIO_PORT DIR4: DIRP9 Mask          */
+#define GPIO_PORT_DIR4_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR4: DIRP10 Position     */
+#define GPIO_PORT_DIR4_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos)                     /*!< GPIO_PORT DIR4: DIRP10 Mask         */
+#define GPIO_PORT_DIR4_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR4: DIRP11 Position     */
+#define GPIO_PORT_DIR4_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos)                     /*!< GPIO_PORT DIR4: DIRP11 Mask         */
+#define GPIO_PORT_DIR4_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR4: DIRP12 Position     */
+#define GPIO_PORT_DIR4_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos)                     /*!< GPIO_PORT DIR4: DIRP12 Mask         */
+#define GPIO_PORT_DIR4_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR4: DIRP13 Position     */
+#define GPIO_PORT_DIR4_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos)                     /*!< GPIO_PORT DIR4: DIRP13 Mask         */
+#define GPIO_PORT_DIR4_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR4: DIRP14 Position     */
+#define GPIO_PORT_DIR4_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos)                     /*!< GPIO_PORT DIR4: DIRP14 Mask         */
+#define GPIO_PORT_DIR4_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR4: DIRP15 Position     */
+#define GPIO_PORT_DIR4_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos)                     /*!< GPIO_PORT DIR4: DIRP15 Mask         */
+#define GPIO_PORT_DIR4_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR4: DIRP16 Position     */
+#define GPIO_PORT_DIR4_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos)                     /*!< GPIO_PORT DIR4: DIRP16 Mask         */
+#define GPIO_PORT_DIR4_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR4: DIRP17 Position     */
+#define GPIO_PORT_DIR4_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos)                     /*!< GPIO_PORT DIR4: DIRP17 Mask         */
+#define GPIO_PORT_DIR4_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR4: DIRP18 Position     */
+#define GPIO_PORT_DIR4_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos)                     /*!< GPIO_PORT DIR4: DIRP18 Mask         */
+#define GPIO_PORT_DIR4_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR4: DIRP19 Position     */
+#define GPIO_PORT_DIR4_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos)                     /*!< GPIO_PORT DIR4: DIRP19 Mask         */
+#define GPIO_PORT_DIR4_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR4: DIRP20 Position     */
+#define GPIO_PORT_DIR4_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos)                     /*!< GPIO_PORT DIR4: DIRP20 Mask         */
+#define GPIO_PORT_DIR4_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR4: DIRP21 Position     */
+#define GPIO_PORT_DIR4_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos)                     /*!< GPIO_PORT DIR4: DIRP21 Mask         */
+#define GPIO_PORT_DIR4_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR4: DIRP22 Position     */
+#define GPIO_PORT_DIR4_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos)                     /*!< GPIO_PORT DIR4: DIRP22 Mask         */
+#define GPIO_PORT_DIR4_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR4: DIRP23 Position     */
+#define GPIO_PORT_DIR4_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos)                     /*!< GPIO_PORT DIR4: DIRP23 Mask         */
+#define GPIO_PORT_DIR4_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR4: DIRP24 Position     */
+#define GPIO_PORT_DIR4_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos)                     /*!< GPIO_PORT DIR4: DIRP24 Mask         */
+#define GPIO_PORT_DIR4_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR4: DIRP25 Position     */
+#define GPIO_PORT_DIR4_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos)                     /*!< GPIO_PORT DIR4: DIRP25 Mask         */
+#define GPIO_PORT_DIR4_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR4: DIRP26 Position     */
+#define GPIO_PORT_DIR4_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos)                     /*!< GPIO_PORT DIR4: DIRP26 Mask         */
+#define GPIO_PORT_DIR4_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR4: DIRP27 Position     */
+#define GPIO_PORT_DIR4_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos)                     /*!< GPIO_PORT DIR4: DIRP27 Mask         */
+#define GPIO_PORT_DIR4_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR4: DIRP28 Position     */
+#define GPIO_PORT_DIR4_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos)                     /*!< GPIO_PORT DIR4: DIRP28 Mask         */
+#define GPIO_PORT_DIR4_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR4: DIRP29 Position     */
+#define GPIO_PORT_DIR4_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos)                     /*!< GPIO_PORT DIR4: DIRP29 Mask         */
+#define GPIO_PORT_DIR4_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR4: DIRP30 Position     */
+#define GPIO_PORT_DIR4_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos)                     /*!< GPIO_PORT DIR4: DIRP30 Mask         */
+#define GPIO_PORT_DIR4_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR4: DIRP31 Position     */
+#define GPIO_PORT_DIR4_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos)                     /*!< GPIO_PORT DIR4: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR5  -----------------------------------------
+#define GPIO_PORT_DIR5_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR5: DIRP0 Position      */
+#define GPIO_PORT_DIR5_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos)                      /*!< GPIO_PORT DIR5: DIRP0 Mask          */
+#define GPIO_PORT_DIR5_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR5: DIRP1 Position      */
+#define GPIO_PORT_DIR5_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos)                      /*!< GPIO_PORT DIR5: DIRP1 Mask          */
+#define GPIO_PORT_DIR5_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR5: DIRP2 Position      */
+#define GPIO_PORT_DIR5_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos)                      /*!< GPIO_PORT DIR5: DIRP2 Mask          */
+#define GPIO_PORT_DIR5_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR5: DIRP3 Position      */
+#define GPIO_PORT_DIR5_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos)                      /*!< GPIO_PORT DIR5: DIRP3 Mask          */
+#define GPIO_PORT_DIR5_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR5: DIRP4 Position      */
+#define GPIO_PORT_DIR5_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos)                      /*!< GPIO_PORT DIR5: DIRP4 Mask          */
+#define GPIO_PORT_DIR5_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR5: DIRP5 Position      */
+#define GPIO_PORT_DIR5_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos)                      /*!< GPIO_PORT DIR5: DIRP5 Mask          */
+#define GPIO_PORT_DIR5_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR5: DIRP6 Position      */
+#define GPIO_PORT_DIR5_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos)                      /*!< GPIO_PORT DIR5: DIRP6 Mask          */
+#define GPIO_PORT_DIR5_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR5: DIRP7 Position      */
+#define GPIO_PORT_DIR5_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos)                      /*!< GPIO_PORT DIR5: DIRP7 Mask          */
+#define GPIO_PORT_DIR5_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR5: DIRP8 Position      */
+#define GPIO_PORT_DIR5_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos)                      /*!< GPIO_PORT DIR5: DIRP8 Mask          */
+#define GPIO_PORT_DIR5_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR5: DIRP9 Position      */
+#define GPIO_PORT_DIR5_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos)                      /*!< GPIO_PORT DIR5: DIRP9 Mask          */
+#define GPIO_PORT_DIR5_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR5: DIRP10 Position     */
+#define GPIO_PORT_DIR5_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos)                     /*!< GPIO_PORT DIR5: DIRP10 Mask         */
+#define GPIO_PORT_DIR5_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR5: DIRP11 Position     */
+#define GPIO_PORT_DIR5_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos)                     /*!< GPIO_PORT DIR5: DIRP11 Mask         */
+#define GPIO_PORT_DIR5_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR5: DIRP12 Position     */
+#define GPIO_PORT_DIR5_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos)                     /*!< GPIO_PORT DIR5: DIRP12 Mask         */
+#define GPIO_PORT_DIR5_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR5: DIRP13 Position     */
+#define GPIO_PORT_DIR5_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos)                     /*!< GPIO_PORT DIR5: DIRP13 Mask         */
+#define GPIO_PORT_DIR5_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR5: DIRP14 Position     */
+#define GPIO_PORT_DIR5_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos)                     /*!< GPIO_PORT DIR5: DIRP14 Mask         */
+#define GPIO_PORT_DIR5_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR5: DIRP15 Position     */
+#define GPIO_PORT_DIR5_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos)                     /*!< GPIO_PORT DIR5: DIRP15 Mask         */
+#define GPIO_PORT_DIR5_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR5: DIRP16 Position     */
+#define GPIO_PORT_DIR5_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos)                     /*!< GPIO_PORT DIR5: DIRP16 Mask         */
+#define GPIO_PORT_DIR5_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR5: DIRP17 Position     */
+#define GPIO_PORT_DIR5_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos)                     /*!< GPIO_PORT DIR5: DIRP17 Mask         */
+#define GPIO_PORT_DIR5_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR5: DIRP18 Position     */
+#define GPIO_PORT_DIR5_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos)                     /*!< GPIO_PORT DIR5: DIRP18 Mask         */
+#define GPIO_PORT_DIR5_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR5: DIRP19 Position     */
+#define GPIO_PORT_DIR5_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos)                     /*!< GPIO_PORT DIR5: DIRP19 Mask         */
+#define GPIO_PORT_DIR5_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR5: DIRP20 Position     */
+#define GPIO_PORT_DIR5_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos)                     /*!< GPIO_PORT DIR5: DIRP20 Mask         */
+#define GPIO_PORT_DIR5_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR5: DIRP21 Position     */
+#define GPIO_PORT_DIR5_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos)                     /*!< GPIO_PORT DIR5: DIRP21 Mask         */
+#define GPIO_PORT_DIR5_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR5: DIRP22 Position     */
+#define GPIO_PORT_DIR5_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos)                     /*!< GPIO_PORT DIR5: DIRP22 Mask         */
+#define GPIO_PORT_DIR5_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR5: DIRP23 Position     */
+#define GPIO_PORT_DIR5_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos)                     /*!< GPIO_PORT DIR5: DIRP23 Mask         */
+#define GPIO_PORT_DIR5_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR5: DIRP24 Position     */
+#define GPIO_PORT_DIR5_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos)                     /*!< GPIO_PORT DIR5: DIRP24 Mask         */
+#define GPIO_PORT_DIR5_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR5: DIRP25 Position     */
+#define GPIO_PORT_DIR5_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos)                     /*!< GPIO_PORT DIR5: DIRP25 Mask         */
+#define GPIO_PORT_DIR5_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR5: DIRP26 Position     */
+#define GPIO_PORT_DIR5_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos)                     /*!< GPIO_PORT DIR5: DIRP26 Mask         */
+#define GPIO_PORT_DIR5_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR5: DIRP27 Position     */
+#define GPIO_PORT_DIR5_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos)                     /*!< GPIO_PORT DIR5: DIRP27 Mask         */
+#define GPIO_PORT_DIR5_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR5: DIRP28 Position     */
+#define GPIO_PORT_DIR5_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos)                     /*!< GPIO_PORT DIR5: DIRP28 Mask         */
+#define GPIO_PORT_DIR5_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR5: DIRP29 Position     */
+#define GPIO_PORT_DIR5_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos)                     /*!< GPIO_PORT DIR5: DIRP29 Mask         */
+#define GPIO_PORT_DIR5_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR5: DIRP30 Position     */
+#define GPIO_PORT_DIR5_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos)                     /*!< GPIO_PORT DIR5: DIRP30 Mask         */
+#define GPIO_PORT_DIR5_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR5: DIRP31 Position     */
+#define GPIO_PORT_DIR5_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos)                     /*!< GPIO_PORT DIR5: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR6  -----------------------------------------
+#define GPIO_PORT_DIR6_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR6: DIRP0 Position      */
+#define GPIO_PORT_DIR6_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos)                      /*!< GPIO_PORT DIR6: DIRP0 Mask          */
+#define GPIO_PORT_DIR6_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR6: DIRP1 Position      */
+#define GPIO_PORT_DIR6_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos)                      /*!< GPIO_PORT DIR6: DIRP1 Mask          */
+#define GPIO_PORT_DIR6_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR6: DIRP2 Position      */
+#define GPIO_PORT_DIR6_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos)                      /*!< GPIO_PORT DIR6: DIRP2 Mask          */
+#define GPIO_PORT_DIR6_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR6: DIRP3 Position      */
+#define GPIO_PORT_DIR6_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos)                      /*!< GPIO_PORT DIR6: DIRP3 Mask          */
+#define GPIO_PORT_DIR6_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR6: DIRP4 Position      */
+#define GPIO_PORT_DIR6_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos)                      /*!< GPIO_PORT DIR6: DIRP4 Mask          */
+#define GPIO_PORT_DIR6_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR6: DIRP5 Position      */
+#define GPIO_PORT_DIR6_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos)                      /*!< GPIO_PORT DIR6: DIRP5 Mask          */
+#define GPIO_PORT_DIR6_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR6: DIRP6 Position      */
+#define GPIO_PORT_DIR6_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos)                      /*!< GPIO_PORT DIR6: DIRP6 Mask          */
+#define GPIO_PORT_DIR6_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR6: DIRP7 Position      */
+#define GPIO_PORT_DIR6_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos)                      /*!< GPIO_PORT DIR6: DIRP7 Mask          */
+#define GPIO_PORT_DIR6_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR6: DIRP8 Position      */
+#define GPIO_PORT_DIR6_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos)                      /*!< GPIO_PORT DIR6: DIRP8 Mask          */
+#define GPIO_PORT_DIR6_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR6: DIRP9 Position      */
+#define GPIO_PORT_DIR6_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos)                      /*!< GPIO_PORT DIR6: DIRP9 Mask          */
+#define GPIO_PORT_DIR6_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR6: DIRP10 Position     */
+#define GPIO_PORT_DIR6_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos)                     /*!< GPIO_PORT DIR6: DIRP10 Mask         */
+#define GPIO_PORT_DIR6_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR6: DIRP11 Position     */
+#define GPIO_PORT_DIR6_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos)                     /*!< GPIO_PORT DIR6: DIRP11 Mask         */
+#define GPIO_PORT_DIR6_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR6: DIRP12 Position     */
+#define GPIO_PORT_DIR6_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos)                     /*!< GPIO_PORT DIR6: DIRP12 Mask         */
+#define GPIO_PORT_DIR6_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR6: DIRP13 Position     */
+#define GPIO_PORT_DIR6_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos)                     /*!< GPIO_PORT DIR6: DIRP13 Mask         */
+#define GPIO_PORT_DIR6_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR6: DIRP14 Position     */
+#define GPIO_PORT_DIR6_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos)                     /*!< GPIO_PORT DIR6: DIRP14 Mask         */
+#define GPIO_PORT_DIR6_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR6: DIRP15 Position     */
+#define GPIO_PORT_DIR6_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos)                     /*!< GPIO_PORT DIR6: DIRP15 Mask         */
+#define GPIO_PORT_DIR6_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR6: DIRP16 Position     */
+#define GPIO_PORT_DIR6_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos)                     /*!< GPIO_PORT DIR6: DIRP16 Mask         */
+#define GPIO_PORT_DIR6_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR6: DIRP17 Position     */
+#define GPIO_PORT_DIR6_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos)                     /*!< GPIO_PORT DIR6: DIRP17 Mask         */
+#define GPIO_PORT_DIR6_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR6: DIRP18 Position     */
+#define GPIO_PORT_DIR6_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos)                     /*!< GPIO_PORT DIR6: DIRP18 Mask         */
+#define GPIO_PORT_DIR6_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR6: DIRP19 Position     */
+#define GPIO_PORT_DIR6_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos)                     /*!< GPIO_PORT DIR6: DIRP19 Mask         */
+#define GPIO_PORT_DIR6_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR6: DIRP20 Position     */
+#define GPIO_PORT_DIR6_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos)                     /*!< GPIO_PORT DIR6: DIRP20 Mask         */
+#define GPIO_PORT_DIR6_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR6: DIRP21 Position     */
+#define GPIO_PORT_DIR6_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos)                     /*!< GPIO_PORT DIR6: DIRP21 Mask         */
+#define GPIO_PORT_DIR6_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR6: DIRP22 Position     */
+#define GPIO_PORT_DIR6_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos)                     /*!< GPIO_PORT DIR6: DIRP22 Mask         */
+#define GPIO_PORT_DIR6_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR6: DIRP23 Position     */
+#define GPIO_PORT_DIR6_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos)                     /*!< GPIO_PORT DIR6: DIRP23 Mask         */
+#define GPIO_PORT_DIR6_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR6: DIRP24 Position     */
+#define GPIO_PORT_DIR6_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos)                     /*!< GPIO_PORT DIR6: DIRP24 Mask         */
+#define GPIO_PORT_DIR6_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR6: DIRP25 Position     */
+#define GPIO_PORT_DIR6_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos)                     /*!< GPIO_PORT DIR6: DIRP25 Mask         */
+#define GPIO_PORT_DIR6_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR6: DIRP26 Position     */
+#define GPIO_PORT_DIR6_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos)                     /*!< GPIO_PORT DIR6: DIRP26 Mask         */
+#define GPIO_PORT_DIR6_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR6: DIRP27 Position     */
+#define GPIO_PORT_DIR6_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos)                     /*!< GPIO_PORT DIR6: DIRP27 Mask         */
+#define GPIO_PORT_DIR6_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR6: DIRP28 Position     */
+#define GPIO_PORT_DIR6_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos)                     /*!< GPIO_PORT DIR6: DIRP28 Mask         */
+#define GPIO_PORT_DIR6_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR6: DIRP29 Position     */
+#define GPIO_PORT_DIR6_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos)                     /*!< GPIO_PORT DIR6: DIRP29 Mask         */
+#define GPIO_PORT_DIR6_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR6: DIRP30 Position     */
+#define GPIO_PORT_DIR6_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos)                     /*!< GPIO_PORT DIR6: DIRP30 Mask         */
+#define GPIO_PORT_DIR6_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR6: DIRP31 Position     */
+#define GPIO_PORT_DIR6_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos)                     /*!< GPIO_PORT DIR6: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR7  -----------------------------------------
+#define GPIO_PORT_DIR7_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR7: DIRP0 Position      */
+#define GPIO_PORT_DIR7_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos)                      /*!< GPIO_PORT DIR7: DIRP0 Mask          */
+#define GPIO_PORT_DIR7_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR7: DIRP1 Position      */
+#define GPIO_PORT_DIR7_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos)                      /*!< GPIO_PORT DIR7: DIRP1 Mask          */
+#define GPIO_PORT_DIR7_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR7: DIRP2 Position      */
+#define GPIO_PORT_DIR7_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos)                      /*!< GPIO_PORT DIR7: DIRP2 Mask          */
+#define GPIO_PORT_DIR7_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR7: DIRP3 Position      */
+#define GPIO_PORT_DIR7_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos)                      /*!< GPIO_PORT DIR7: DIRP3 Mask          */
+#define GPIO_PORT_DIR7_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR7: DIRP4 Position      */
+#define GPIO_PORT_DIR7_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos)                      /*!< GPIO_PORT DIR7: DIRP4 Mask          */
+#define GPIO_PORT_DIR7_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR7: DIRP5 Position      */
+#define GPIO_PORT_DIR7_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos)                      /*!< GPIO_PORT DIR7: DIRP5 Mask          */
+#define GPIO_PORT_DIR7_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR7: DIRP6 Position      */
+#define GPIO_PORT_DIR7_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos)                      /*!< GPIO_PORT DIR7: DIRP6 Mask          */
+#define GPIO_PORT_DIR7_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR7: DIRP7 Position      */
+#define GPIO_PORT_DIR7_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos)                      /*!< GPIO_PORT DIR7: DIRP7 Mask          */
+#define GPIO_PORT_DIR7_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR7: DIRP8 Position      */
+#define GPIO_PORT_DIR7_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos)                      /*!< GPIO_PORT DIR7: DIRP8 Mask          */
+#define GPIO_PORT_DIR7_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR7: DIRP9 Position      */
+#define GPIO_PORT_DIR7_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos)                      /*!< GPIO_PORT DIR7: DIRP9 Mask          */
+#define GPIO_PORT_DIR7_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR7: DIRP10 Position     */
+#define GPIO_PORT_DIR7_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos)                     /*!< GPIO_PORT DIR7: DIRP10 Mask         */
+#define GPIO_PORT_DIR7_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR7: DIRP11 Position     */
+#define GPIO_PORT_DIR7_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos)                     /*!< GPIO_PORT DIR7: DIRP11 Mask         */
+#define GPIO_PORT_DIR7_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR7: DIRP12 Position     */
+#define GPIO_PORT_DIR7_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos)                     /*!< GPIO_PORT DIR7: DIRP12 Mask         */
+#define GPIO_PORT_DIR7_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR7: DIRP13 Position     */
+#define GPIO_PORT_DIR7_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos)                     /*!< GPIO_PORT DIR7: DIRP13 Mask         */
+#define GPIO_PORT_DIR7_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR7: DIRP14 Position     */
+#define GPIO_PORT_DIR7_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos)                     /*!< GPIO_PORT DIR7: DIRP14 Mask         */
+#define GPIO_PORT_DIR7_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR7: DIRP15 Position     */
+#define GPIO_PORT_DIR7_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos)                     /*!< GPIO_PORT DIR7: DIRP15 Mask         */
+#define GPIO_PORT_DIR7_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR7: DIRP16 Position     */
+#define GPIO_PORT_DIR7_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos)                     /*!< GPIO_PORT DIR7: DIRP16 Mask         */
+#define GPIO_PORT_DIR7_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR7: DIRP17 Position     */
+#define GPIO_PORT_DIR7_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos)                     /*!< GPIO_PORT DIR7: DIRP17 Mask         */
+#define GPIO_PORT_DIR7_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR7: DIRP18 Position     */
+#define GPIO_PORT_DIR7_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos)                     /*!< GPIO_PORT DIR7: DIRP18 Mask         */
+#define GPIO_PORT_DIR7_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR7: DIRP19 Position     */
+#define GPIO_PORT_DIR7_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos)                     /*!< GPIO_PORT DIR7: DIRP19 Mask         */
+#define GPIO_PORT_DIR7_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR7: DIRP20 Position     */
+#define GPIO_PORT_DIR7_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos)                     /*!< GPIO_PORT DIR7: DIRP20 Mask         */
+#define GPIO_PORT_DIR7_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR7: DIRP21 Position     */
+#define GPIO_PORT_DIR7_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos)                     /*!< GPIO_PORT DIR7: DIRP21 Mask         */
+#define GPIO_PORT_DIR7_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR7: DIRP22 Position     */
+#define GPIO_PORT_DIR7_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos)                     /*!< GPIO_PORT DIR7: DIRP22 Mask         */
+#define GPIO_PORT_DIR7_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR7: DIRP23 Position     */
+#define GPIO_PORT_DIR7_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos)                     /*!< GPIO_PORT DIR7: DIRP23 Mask         */
+#define GPIO_PORT_DIR7_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR7: DIRP24 Position     */
+#define GPIO_PORT_DIR7_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos)                     /*!< GPIO_PORT DIR7: DIRP24 Mask         */
+#define GPIO_PORT_DIR7_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR7: DIRP25 Position     */
+#define GPIO_PORT_DIR7_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos)                     /*!< GPIO_PORT DIR7: DIRP25 Mask         */
+#define GPIO_PORT_DIR7_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR7: DIRP26 Position     */
+#define GPIO_PORT_DIR7_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos)                     /*!< GPIO_PORT DIR7: DIRP26 Mask         */
+#define GPIO_PORT_DIR7_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR7: DIRP27 Position     */
+#define GPIO_PORT_DIR7_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos)                     /*!< GPIO_PORT DIR7: DIRP27 Mask         */
+#define GPIO_PORT_DIR7_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR7: DIRP28 Position     */
+#define GPIO_PORT_DIR7_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos)                     /*!< GPIO_PORT DIR7: DIRP28 Mask         */
+#define GPIO_PORT_DIR7_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR7: DIRP29 Position     */
+#define GPIO_PORT_DIR7_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos)                     /*!< GPIO_PORT DIR7: DIRP29 Mask         */
+#define GPIO_PORT_DIR7_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR7: DIRP30 Position     */
+#define GPIO_PORT_DIR7_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos)                     /*!< GPIO_PORT DIR7: DIRP30 Mask         */
+#define GPIO_PORT_DIR7_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR7: DIRP31 Position     */
+#define GPIO_PORT_DIR7_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos)                     /*!< GPIO_PORT DIR7: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_MASK0  ----------------------------------------
+#define GPIO_PORT_MASK0_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK0: MASKP0 Position    */
+#define GPIO_PORT_MASK0_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos)                    /*!< GPIO_PORT MASK0: MASKP0 Mask        */
+#define GPIO_PORT_MASK0_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK0: MASKP1 Position    */
+#define GPIO_PORT_MASK0_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos)                    /*!< GPIO_PORT MASK0: MASKP1 Mask        */
+#define GPIO_PORT_MASK0_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK0: MASKP2 Position    */
+#define GPIO_PORT_MASK0_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos)                    /*!< GPIO_PORT MASK0: MASKP2 Mask        */
+#define GPIO_PORT_MASK0_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK0: MASKP3 Position    */
+#define GPIO_PORT_MASK0_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos)                    /*!< GPIO_PORT MASK0: MASKP3 Mask        */
+#define GPIO_PORT_MASK0_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK0: MASKP4 Position    */
+#define GPIO_PORT_MASK0_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos)                    /*!< GPIO_PORT MASK0: MASKP4 Mask        */
+#define GPIO_PORT_MASK0_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK0: MASKP5 Position    */
+#define GPIO_PORT_MASK0_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos)                    /*!< GPIO_PORT MASK0: MASKP5 Mask        */
+#define GPIO_PORT_MASK0_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK0: MASKP6 Position    */
+#define GPIO_PORT_MASK0_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos)                    /*!< GPIO_PORT MASK0: MASKP6 Mask        */
+#define GPIO_PORT_MASK0_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK0: MASKP7 Position    */
+#define GPIO_PORT_MASK0_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos)                    /*!< GPIO_PORT MASK0: MASKP7 Mask        */
+#define GPIO_PORT_MASK0_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK0: MASKP8 Position    */
+#define GPIO_PORT_MASK0_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos)                    /*!< GPIO_PORT MASK0: MASKP8 Mask        */
+#define GPIO_PORT_MASK0_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK0: MASKP9 Position    */
+#define GPIO_PORT_MASK0_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos)                    /*!< GPIO_PORT MASK0: MASKP9 Mask        */
+#define GPIO_PORT_MASK0_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK0: MASKP10 Position   */
+#define GPIO_PORT_MASK0_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos)                   /*!< GPIO_PORT MASK0: MASKP10 Mask       */
+#define GPIO_PORT_MASK0_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK0: MASKP11 Position   */
+#define GPIO_PORT_MASK0_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos)                   /*!< GPIO_PORT MASK0: MASKP11 Mask       */
+#define GPIO_PORT_MASK0_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK0: MASKP12 Position   */
+#define GPIO_PORT_MASK0_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos)                   /*!< GPIO_PORT MASK0: MASKP12 Mask       */
+#define GPIO_PORT_MASK0_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK0: MASKP13 Position   */
+#define GPIO_PORT_MASK0_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos)                   /*!< GPIO_PORT MASK0: MASKP13 Mask       */
+#define GPIO_PORT_MASK0_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK0: MASKP14 Position   */
+#define GPIO_PORT_MASK0_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos)                   /*!< GPIO_PORT MASK0: MASKP14 Mask       */
+#define GPIO_PORT_MASK0_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK0: MASKP15 Position   */
+#define GPIO_PORT_MASK0_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos)                   /*!< GPIO_PORT MASK0: MASKP15 Mask       */
+#define GPIO_PORT_MASK0_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK0: MASKP16 Position   */
+#define GPIO_PORT_MASK0_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos)                   /*!< GPIO_PORT MASK0: MASKP16 Mask       */
+#define GPIO_PORT_MASK0_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK0: MASKP17 Position   */
+#define GPIO_PORT_MASK0_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos)                   /*!< GPIO_PORT MASK0: MASKP17 Mask       */
+#define GPIO_PORT_MASK0_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK0: MASKP18 Position   */
+#define GPIO_PORT_MASK0_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos)                   /*!< GPIO_PORT MASK0: MASKP18 Mask       */
+#define GPIO_PORT_MASK0_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK0: MASKP19 Position   */
+#define GPIO_PORT_MASK0_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos)                   /*!< GPIO_PORT MASK0: MASKP19 Mask       */
+#define GPIO_PORT_MASK0_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK0: MASKP20 Position   */
+#define GPIO_PORT_MASK0_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos)                   /*!< GPIO_PORT MASK0: MASKP20 Mask       */
+#define GPIO_PORT_MASK0_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK0: MASKP21 Position   */
+#define GPIO_PORT_MASK0_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos)                   /*!< GPIO_PORT MASK0: MASKP21 Mask       */
+#define GPIO_PORT_MASK0_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK0: MASKP22 Position   */
+#define GPIO_PORT_MASK0_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos)                   /*!< GPIO_PORT MASK0: MASKP22 Mask       */
+#define GPIO_PORT_MASK0_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK0: MASKP23 Position   */
+#define GPIO_PORT_MASK0_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos)                   /*!< GPIO_PORT MASK0: MASKP23 Mask       */
+#define GPIO_PORT_MASK0_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK0: MASKP24 Position   */
+#define GPIO_PORT_MASK0_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos)                   /*!< GPIO_PORT MASK0: MASKP24 Mask       */
+#define GPIO_PORT_MASK0_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK0: MASKP25 Position   */
+#define GPIO_PORT_MASK0_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos)                   /*!< GPIO_PORT MASK0: MASKP25 Mask       */
+#define GPIO_PORT_MASK0_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK0: MASKP26 Position   */
+#define GPIO_PORT_MASK0_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos)                   /*!< GPIO_PORT MASK0: MASKP26 Mask       */
+#define GPIO_PORT_MASK0_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK0: MASKP27 Position   */
+#define GPIO_PORT_MASK0_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos)                   /*!< GPIO_PORT MASK0: MASKP27 Mask       */
+#define GPIO_PORT_MASK0_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK0: MASKP28 Position   */
+#define GPIO_PORT_MASK0_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos)                   /*!< GPIO_PORT MASK0: MASKP28 Mask       */
+#define GPIO_PORT_MASK0_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK0: MASKP29 Position   */
+#define GPIO_PORT_MASK0_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos)                   /*!< GPIO_PORT MASK0: MASKP29 Mask       */
+#define GPIO_PORT_MASK0_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK0: MASKP30 Position   */
+#define GPIO_PORT_MASK0_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos)                   /*!< GPIO_PORT MASK0: MASKP30 Mask       */
+#define GPIO_PORT_MASK0_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK0: MASKP31 Position   */
+#define GPIO_PORT_MASK0_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos)                   /*!< GPIO_PORT MASK0: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK1  ----------------------------------------
+#define GPIO_PORT_MASK1_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK1: MASKP0 Position    */
+#define GPIO_PORT_MASK1_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos)                    /*!< GPIO_PORT MASK1: MASKP0 Mask        */
+#define GPIO_PORT_MASK1_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK1: MASKP1 Position    */
+#define GPIO_PORT_MASK1_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos)                    /*!< GPIO_PORT MASK1: MASKP1 Mask        */
+#define GPIO_PORT_MASK1_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK1: MASKP2 Position    */
+#define GPIO_PORT_MASK1_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos)                    /*!< GPIO_PORT MASK1: MASKP2 Mask        */
+#define GPIO_PORT_MASK1_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK1: MASKP3 Position    */
+#define GPIO_PORT_MASK1_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos)                    /*!< GPIO_PORT MASK1: MASKP3 Mask        */
+#define GPIO_PORT_MASK1_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK1: MASKP4 Position    */
+#define GPIO_PORT_MASK1_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos)                    /*!< GPIO_PORT MASK1: MASKP4 Mask        */
+#define GPIO_PORT_MASK1_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK1: MASKP5 Position    */
+#define GPIO_PORT_MASK1_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos)                    /*!< GPIO_PORT MASK1: MASKP5 Mask        */
+#define GPIO_PORT_MASK1_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK1: MASKP6 Position    */
+#define GPIO_PORT_MASK1_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos)                    /*!< GPIO_PORT MASK1: MASKP6 Mask        */
+#define GPIO_PORT_MASK1_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK1: MASKP7 Position    */
+#define GPIO_PORT_MASK1_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos)                    /*!< GPIO_PORT MASK1: MASKP7 Mask        */
+#define GPIO_PORT_MASK1_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK1: MASKP8 Position    */
+#define GPIO_PORT_MASK1_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos)                    /*!< GPIO_PORT MASK1: MASKP8 Mask        */
+#define GPIO_PORT_MASK1_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK1: MASKP9 Position    */
+#define GPIO_PORT_MASK1_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos)                    /*!< GPIO_PORT MASK1: MASKP9 Mask        */
+#define GPIO_PORT_MASK1_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK1: MASKP10 Position   */
+#define GPIO_PORT_MASK1_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos)                   /*!< GPIO_PORT MASK1: MASKP10 Mask       */
+#define GPIO_PORT_MASK1_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK1: MASKP11 Position   */
+#define GPIO_PORT_MASK1_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos)                   /*!< GPIO_PORT MASK1: MASKP11 Mask       */
+#define GPIO_PORT_MASK1_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK1: MASKP12 Position   */
+#define GPIO_PORT_MASK1_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos)                   /*!< GPIO_PORT MASK1: MASKP12 Mask       */
+#define GPIO_PORT_MASK1_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK1: MASKP13 Position   */
+#define GPIO_PORT_MASK1_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos)                   /*!< GPIO_PORT MASK1: MASKP13 Mask       */
+#define GPIO_PORT_MASK1_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK1: MASKP14 Position   */
+#define GPIO_PORT_MASK1_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos)                   /*!< GPIO_PORT MASK1: MASKP14 Mask       */
+#define GPIO_PORT_MASK1_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK1: MASKP15 Position   */
+#define GPIO_PORT_MASK1_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos)                   /*!< GPIO_PORT MASK1: MASKP15 Mask       */
+#define GPIO_PORT_MASK1_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK1: MASKP16 Position   */
+#define GPIO_PORT_MASK1_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos)                   /*!< GPIO_PORT MASK1: MASKP16 Mask       */
+#define GPIO_PORT_MASK1_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK1: MASKP17 Position   */
+#define GPIO_PORT_MASK1_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos)                   /*!< GPIO_PORT MASK1: MASKP17 Mask       */
+#define GPIO_PORT_MASK1_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK1: MASKP18 Position   */
+#define GPIO_PORT_MASK1_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos)                   /*!< GPIO_PORT MASK1: MASKP18 Mask       */
+#define GPIO_PORT_MASK1_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK1: MASKP19 Position   */
+#define GPIO_PORT_MASK1_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos)                   /*!< GPIO_PORT MASK1: MASKP19 Mask       */
+#define GPIO_PORT_MASK1_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK1: MASKP20 Position   */
+#define GPIO_PORT_MASK1_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos)                   /*!< GPIO_PORT MASK1: MASKP20 Mask       */
+#define GPIO_PORT_MASK1_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK1: MASKP21 Position   */
+#define GPIO_PORT_MASK1_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos)                   /*!< GPIO_PORT MASK1: MASKP21 Mask       */
+#define GPIO_PORT_MASK1_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK1: MASKP22 Position   */
+#define GPIO_PORT_MASK1_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos)                   /*!< GPIO_PORT MASK1: MASKP22 Mask       */
+#define GPIO_PORT_MASK1_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK1: MASKP23 Position   */
+#define GPIO_PORT_MASK1_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos)                   /*!< GPIO_PORT MASK1: MASKP23 Mask       */
+#define GPIO_PORT_MASK1_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK1: MASKP24 Position   */
+#define GPIO_PORT_MASK1_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos)                   /*!< GPIO_PORT MASK1: MASKP24 Mask       */
+#define GPIO_PORT_MASK1_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK1: MASKP25 Position   */
+#define GPIO_PORT_MASK1_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos)                   /*!< GPIO_PORT MASK1: MASKP25 Mask       */
+#define GPIO_PORT_MASK1_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK1: MASKP26 Position   */
+#define GPIO_PORT_MASK1_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos)                   /*!< GPIO_PORT MASK1: MASKP26 Mask       */
+#define GPIO_PORT_MASK1_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK1: MASKP27 Position   */
+#define GPIO_PORT_MASK1_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos)                   /*!< GPIO_PORT MASK1: MASKP27 Mask       */
+#define GPIO_PORT_MASK1_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK1: MASKP28 Position   */
+#define GPIO_PORT_MASK1_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos)                   /*!< GPIO_PORT MASK1: MASKP28 Mask       */
+#define GPIO_PORT_MASK1_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK1: MASKP29 Position   */
+#define GPIO_PORT_MASK1_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos)                   /*!< GPIO_PORT MASK1: MASKP29 Mask       */
+#define GPIO_PORT_MASK1_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK1: MASKP30 Position   */
+#define GPIO_PORT_MASK1_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos)                   /*!< GPIO_PORT MASK1: MASKP30 Mask       */
+#define GPIO_PORT_MASK1_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK1: MASKP31 Position   */
+#define GPIO_PORT_MASK1_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos)                   /*!< GPIO_PORT MASK1: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK2  ----------------------------------------
+#define GPIO_PORT_MASK2_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK2: MASKP0 Position    */
+#define GPIO_PORT_MASK2_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos)                    /*!< GPIO_PORT MASK2: MASKP0 Mask        */
+#define GPIO_PORT_MASK2_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK2: MASKP1 Position    */
+#define GPIO_PORT_MASK2_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos)                    /*!< GPIO_PORT MASK2: MASKP1 Mask        */
+#define GPIO_PORT_MASK2_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK2: MASKP2 Position    */
+#define GPIO_PORT_MASK2_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos)                    /*!< GPIO_PORT MASK2: MASKP2 Mask        */
+#define GPIO_PORT_MASK2_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK2: MASKP3 Position    */
+#define GPIO_PORT_MASK2_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos)                    /*!< GPIO_PORT MASK2: MASKP3 Mask        */
+#define GPIO_PORT_MASK2_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK2: MASKP4 Position    */
+#define GPIO_PORT_MASK2_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos)                    /*!< GPIO_PORT MASK2: MASKP4 Mask        */
+#define GPIO_PORT_MASK2_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK2: MASKP5 Position    */
+#define GPIO_PORT_MASK2_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos)                    /*!< GPIO_PORT MASK2: MASKP5 Mask        */
+#define GPIO_PORT_MASK2_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK2: MASKP6 Position    */
+#define GPIO_PORT_MASK2_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos)                    /*!< GPIO_PORT MASK2: MASKP6 Mask        */
+#define GPIO_PORT_MASK2_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK2: MASKP7 Position    */
+#define GPIO_PORT_MASK2_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos)                    /*!< GPIO_PORT MASK2: MASKP7 Mask        */
+#define GPIO_PORT_MASK2_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK2: MASKP8 Position    */
+#define GPIO_PORT_MASK2_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos)                    /*!< GPIO_PORT MASK2: MASKP8 Mask        */
+#define GPIO_PORT_MASK2_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK2: MASKP9 Position    */
+#define GPIO_PORT_MASK2_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos)                    /*!< GPIO_PORT MASK2: MASKP9 Mask        */
+#define GPIO_PORT_MASK2_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK2: MASKP10 Position   */
+#define GPIO_PORT_MASK2_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos)                   /*!< GPIO_PORT MASK2: MASKP10 Mask       */
+#define GPIO_PORT_MASK2_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK2: MASKP11 Position   */
+#define GPIO_PORT_MASK2_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos)                   /*!< GPIO_PORT MASK2: MASKP11 Mask       */
+#define GPIO_PORT_MASK2_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK2: MASKP12 Position   */
+#define GPIO_PORT_MASK2_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos)                   /*!< GPIO_PORT MASK2: MASKP12 Mask       */
+#define GPIO_PORT_MASK2_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK2: MASKP13 Position   */
+#define GPIO_PORT_MASK2_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos)                   /*!< GPIO_PORT MASK2: MASKP13 Mask       */
+#define GPIO_PORT_MASK2_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK2: MASKP14 Position   */
+#define GPIO_PORT_MASK2_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos)                   /*!< GPIO_PORT MASK2: MASKP14 Mask       */
+#define GPIO_PORT_MASK2_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK2: MASKP15 Position   */
+#define GPIO_PORT_MASK2_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos)                   /*!< GPIO_PORT MASK2: MASKP15 Mask       */
+#define GPIO_PORT_MASK2_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK2: MASKP16 Position   */
+#define GPIO_PORT_MASK2_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos)                   /*!< GPIO_PORT MASK2: MASKP16 Mask       */
+#define GPIO_PORT_MASK2_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK2: MASKP17 Position   */
+#define GPIO_PORT_MASK2_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos)                   /*!< GPIO_PORT MASK2: MASKP17 Mask       */
+#define GPIO_PORT_MASK2_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK2: MASKP18 Position   */
+#define GPIO_PORT_MASK2_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos)                   /*!< GPIO_PORT MASK2: MASKP18 Mask       */
+#define GPIO_PORT_MASK2_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK2: MASKP19 Position   */
+#define GPIO_PORT_MASK2_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos)                   /*!< GPIO_PORT MASK2: MASKP19 Mask       */
+#define GPIO_PORT_MASK2_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK2: MASKP20 Position   */
+#define GPIO_PORT_MASK2_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos)                   /*!< GPIO_PORT MASK2: MASKP20 Mask       */
+#define GPIO_PORT_MASK2_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK2: MASKP21 Position   */
+#define GPIO_PORT_MASK2_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos)                   /*!< GPIO_PORT MASK2: MASKP21 Mask       */
+#define GPIO_PORT_MASK2_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK2: MASKP22 Position   */
+#define GPIO_PORT_MASK2_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos)                   /*!< GPIO_PORT MASK2: MASKP22 Mask       */
+#define GPIO_PORT_MASK2_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK2: MASKP23 Position   */
+#define GPIO_PORT_MASK2_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos)                   /*!< GPIO_PORT MASK2: MASKP23 Mask       */
+#define GPIO_PORT_MASK2_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK2: MASKP24 Position   */
+#define GPIO_PORT_MASK2_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos)                   /*!< GPIO_PORT MASK2: MASKP24 Mask       */
+#define GPIO_PORT_MASK2_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK2: MASKP25 Position   */
+#define GPIO_PORT_MASK2_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos)                   /*!< GPIO_PORT MASK2: MASKP25 Mask       */
+#define GPIO_PORT_MASK2_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK2: MASKP26 Position   */
+#define GPIO_PORT_MASK2_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos)                   /*!< GPIO_PORT MASK2: MASKP26 Mask       */
+#define GPIO_PORT_MASK2_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK2: MASKP27 Position   */
+#define GPIO_PORT_MASK2_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos)                   /*!< GPIO_PORT MASK2: MASKP27 Mask       */
+#define GPIO_PORT_MASK2_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK2: MASKP28 Position   */
+#define GPIO_PORT_MASK2_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos)                   /*!< GPIO_PORT MASK2: MASKP28 Mask       */
+#define GPIO_PORT_MASK2_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK2: MASKP29 Position   */
+#define GPIO_PORT_MASK2_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos)                   /*!< GPIO_PORT MASK2: MASKP29 Mask       */
+#define GPIO_PORT_MASK2_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK2: MASKP30 Position   */
+#define GPIO_PORT_MASK2_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos)                   /*!< GPIO_PORT MASK2: MASKP30 Mask       */
+#define GPIO_PORT_MASK2_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK2: MASKP31 Position   */
+#define GPIO_PORT_MASK2_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos)                   /*!< GPIO_PORT MASK2: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK3  ----------------------------------------
+#define GPIO_PORT_MASK3_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK3: MASKP0 Position    */
+#define GPIO_PORT_MASK3_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos)                    /*!< GPIO_PORT MASK3: MASKP0 Mask        */
+#define GPIO_PORT_MASK3_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK3: MASKP1 Position    */
+#define GPIO_PORT_MASK3_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos)                    /*!< GPIO_PORT MASK3: MASKP1 Mask        */
+#define GPIO_PORT_MASK3_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK3: MASKP2 Position    */
+#define GPIO_PORT_MASK3_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos)                    /*!< GPIO_PORT MASK3: MASKP2 Mask        */
+#define GPIO_PORT_MASK3_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK3: MASKP3 Position    */
+#define GPIO_PORT_MASK3_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos)                    /*!< GPIO_PORT MASK3: MASKP3 Mask        */
+#define GPIO_PORT_MASK3_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK3: MASKP4 Position    */
+#define GPIO_PORT_MASK3_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos)                    /*!< GPIO_PORT MASK3: MASKP4 Mask        */
+#define GPIO_PORT_MASK3_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK3: MASKP5 Position    */
+#define GPIO_PORT_MASK3_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos)                    /*!< GPIO_PORT MASK3: MASKP5 Mask        */
+#define GPIO_PORT_MASK3_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK3: MASKP6 Position    */
+#define GPIO_PORT_MASK3_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos)                    /*!< GPIO_PORT MASK3: MASKP6 Mask        */
+#define GPIO_PORT_MASK3_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK3: MASKP7 Position    */
+#define GPIO_PORT_MASK3_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos)                    /*!< GPIO_PORT MASK3: MASKP7 Mask        */
+#define GPIO_PORT_MASK3_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK3: MASKP8 Position    */
+#define GPIO_PORT_MASK3_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos)                    /*!< GPIO_PORT MASK3: MASKP8 Mask        */
+#define GPIO_PORT_MASK3_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK3: MASKP9 Position    */
+#define GPIO_PORT_MASK3_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos)                    /*!< GPIO_PORT MASK3: MASKP9 Mask        */
+#define GPIO_PORT_MASK3_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK3: MASKP10 Position   */
+#define GPIO_PORT_MASK3_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos)                   /*!< GPIO_PORT MASK3: MASKP10 Mask       */
+#define GPIO_PORT_MASK3_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK3: MASKP11 Position   */
+#define GPIO_PORT_MASK3_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos)                   /*!< GPIO_PORT MASK3: MASKP11 Mask       */
+#define GPIO_PORT_MASK3_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK3: MASKP12 Position   */
+#define GPIO_PORT_MASK3_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos)                   /*!< GPIO_PORT MASK3: MASKP12 Mask       */
+#define GPIO_PORT_MASK3_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK3: MASKP13 Position   */
+#define GPIO_PORT_MASK3_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos)                   /*!< GPIO_PORT MASK3: MASKP13 Mask       */
+#define GPIO_PORT_MASK3_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK3: MASKP14 Position   */
+#define GPIO_PORT_MASK3_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos)                   /*!< GPIO_PORT MASK3: MASKP14 Mask       */
+#define GPIO_PORT_MASK3_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK3: MASKP15 Position   */
+#define GPIO_PORT_MASK3_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos)                   /*!< GPIO_PORT MASK3: MASKP15 Mask       */
+#define GPIO_PORT_MASK3_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK3: MASKP16 Position   */
+#define GPIO_PORT_MASK3_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos)                   /*!< GPIO_PORT MASK3: MASKP16 Mask       */
+#define GPIO_PORT_MASK3_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK3: MASKP17 Position   */
+#define GPIO_PORT_MASK3_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos)                   /*!< GPIO_PORT MASK3: MASKP17 Mask       */
+#define GPIO_PORT_MASK3_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK3: MASKP18 Position   */
+#define GPIO_PORT_MASK3_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos)                   /*!< GPIO_PORT MASK3: MASKP18 Mask       */
+#define GPIO_PORT_MASK3_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK3: MASKP19 Position   */
+#define GPIO_PORT_MASK3_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos)                   /*!< GPIO_PORT MASK3: MASKP19 Mask       */
+#define GPIO_PORT_MASK3_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK3: MASKP20 Position   */
+#define GPIO_PORT_MASK3_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos)                   /*!< GPIO_PORT MASK3: MASKP20 Mask       */
+#define GPIO_PORT_MASK3_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK3: MASKP21 Position   */
+#define GPIO_PORT_MASK3_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos)                   /*!< GPIO_PORT MASK3: MASKP21 Mask       */
+#define GPIO_PORT_MASK3_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK3: MASKP22 Position   */
+#define GPIO_PORT_MASK3_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos)                   /*!< GPIO_PORT MASK3: MASKP22 Mask       */
+#define GPIO_PORT_MASK3_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK3: MASKP23 Position   */
+#define GPIO_PORT_MASK3_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos)                   /*!< GPIO_PORT MASK3: MASKP23 Mask       */
+#define GPIO_PORT_MASK3_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK3: MASKP24 Position   */
+#define GPIO_PORT_MASK3_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos)                   /*!< GPIO_PORT MASK3: MASKP24 Mask       */
+#define GPIO_PORT_MASK3_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK3: MASKP25 Position   */
+#define GPIO_PORT_MASK3_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos)                   /*!< GPIO_PORT MASK3: MASKP25 Mask       */
+#define GPIO_PORT_MASK3_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK3: MASKP26 Position   */
+#define GPIO_PORT_MASK3_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos)                   /*!< GPIO_PORT MASK3: MASKP26 Mask       */
+#define GPIO_PORT_MASK3_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK3: MASKP27 Position   */
+#define GPIO_PORT_MASK3_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos)                   /*!< GPIO_PORT MASK3: MASKP27 Mask       */
+#define GPIO_PORT_MASK3_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK3: MASKP28 Position   */
+#define GPIO_PORT_MASK3_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos)                   /*!< GPIO_PORT MASK3: MASKP28 Mask       */
+#define GPIO_PORT_MASK3_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK3: MASKP29 Position   */
+#define GPIO_PORT_MASK3_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos)                   /*!< GPIO_PORT MASK3: MASKP29 Mask       */
+#define GPIO_PORT_MASK3_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK3: MASKP30 Position   */
+#define GPIO_PORT_MASK3_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos)                   /*!< GPIO_PORT MASK3: MASKP30 Mask       */
+#define GPIO_PORT_MASK3_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK3: MASKP31 Position   */
+#define GPIO_PORT_MASK3_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos)                   /*!< GPIO_PORT MASK3: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK4  ----------------------------------------
+#define GPIO_PORT_MASK4_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK4: MASKP0 Position    */
+#define GPIO_PORT_MASK4_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos)                    /*!< GPIO_PORT MASK4: MASKP0 Mask        */
+#define GPIO_PORT_MASK4_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK4: MASKP1 Position    */
+#define GPIO_PORT_MASK4_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos)                    /*!< GPIO_PORT MASK4: MASKP1 Mask        */
+#define GPIO_PORT_MASK4_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK4: MASKP2 Position    */
+#define GPIO_PORT_MASK4_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos)                    /*!< GPIO_PORT MASK4: MASKP2 Mask        */
+#define GPIO_PORT_MASK4_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK4: MASKP3 Position    */
+#define GPIO_PORT_MASK4_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos)                    /*!< GPIO_PORT MASK4: MASKP3 Mask        */
+#define GPIO_PORT_MASK4_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK4: MASKP4 Position    */
+#define GPIO_PORT_MASK4_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos)                    /*!< GPIO_PORT MASK4: MASKP4 Mask        */
+#define GPIO_PORT_MASK4_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK4: MASKP5 Position    */
+#define GPIO_PORT_MASK4_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos)                    /*!< GPIO_PORT MASK4: MASKP5 Mask        */
+#define GPIO_PORT_MASK4_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK4: MASKP6 Position    */
+#define GPIO_PORT_MASK4_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos)                    /*!< GPIO_PORT MASK4: MASKP6 Mask        */
+#define GPIO_PORT_MASK4_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK4: MASKP7 Position    */
+#define GPIO_PORT_MASK4_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos)                    /*!< GPIO_PORT MASK4: MASKP7 Mask        */
+#define GPIO_PORT_MASK4_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK4: MASKP8 Position    */
+#define GPIO_PORT_MASK4_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos)                    /*!< GPIO_PORT MASK4: MASKP8 Mask        */
+#define GPIO_PORT_MASK4_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK4: MASKP9 Position    */
+#define GPIO_PORT_MASK4_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos)                    /*!< GPIO_PORT MASK4: MASKP9 Mask        */
+#define GPIO_PORT_MASK4_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK4: MASKP10 Position   */
+#define GPIO_PORT_MASK4_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos)                   /*!< GPIO_PORT MASK4: MASKP10 Mask       */
+#define GPIO_PORT_MASK4_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK4: MASKP11 Position   */
+#define GPIO_PORT_MASK4_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos)                   /*!< GPIO_PORT MASK4: MASKP11 Mask       */
+#define GPIO_PORT_MASK4_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK4: MASKP12 Position   */
+#define GPIO_PORT_MASK4_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos)                   /*!< GPIO_PORT MASK4: MASKP12 Mask       */
+#define GPIO_PORT_MASK4_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK4: MASKP13 Position   */
+#define GPIO_PORT_MASK4_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos)                   /*!< GPIO_PORT MASK4: MASKP13 Mask       */
+#define GPIO_PORT_MASK4_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK4: MASKP14 Position   */
+#define GPIO_PORT_MASK4_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos)                   /*!< GPIO_PORT MASK4: MASKP14 Mask       */
+#define GPIO_PORT_MASK4_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK4: MASKP15 Position   */
+#define GPIO_PORT_MASK4_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos)                   /*!< GPIO_PORT MASK4: MASKP15 Mask       */
+#define GPIO_PORT_MASK4_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK4: MASKP16 Position   */
+#define GPIO_PORT_MASK4_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos)                   /*!< GPIO_PORT MASK4: MASKP16 Mask       */
+#define GPIO_PORT_MASK4_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK4: MASKP17 Position   */
+#define GPIO_PORT_MASK4_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos)                   /*!< GPIO_PORT MASK4: MASKP17 Mask       */
+#define GPIO_PORT_MASK4_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK4: MASKP18 Position   */
+#define GPIO_PORT_MASK4_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos)                   /*!< GPIO_PORT MASK4: MASKP18 Mask       */
+#define GPIO_PORT_MASK4_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK4: MASKP19 Position   */
+#define GPIO_PORT_MASK4_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos)                   /*!< GPIO_PORT MASK4: MASKP19 Mask       */
+#define GPIO_PORT_MASK4_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK4: MASKP20 Position   */
+#define GPIO_PORT_MASK4_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos)                   /*!< GPIO_PORT MASK4: MASKP20 Mask       */
+#define GPIO_PORT_MASK4_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK4: MASKP21 Position   */
+#define GPIO_PORT_MASK4_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos)                   /*!< GPIO_PORT MASK4: MASKP21 Mask       */
+#define GPIO_PORT_MASK4_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK4: MASKP22 Position   */
+#define GPIO_PORT_MASK4_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos)                   /*!< GPIO_PORT MASK4: MASKP22 Mask       */
+#define GPIO_PORT_MASK4_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK4: MASKP23 Position   */
+#define GPIO_PORT_MASK4_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos)                   /*!< GPIO_PORT MASK4: MASKP23 Mask       */
+#define GPIO_PORT_MASK4_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK4: MASKP24 Position   */
+#define GPIO_PORT_MASK4_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos)                   /*!< GPIO_PORT MASK4: MASKP24 Mask       */
+#define GPIO_PORT_MASK4_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK4: MASKP25 Position   */
+#define GPIO_PORT_MASK4_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos)                   /*!< GPIO_PORT MASK4: MASKP25 Mask       */
+#define GPIO_PORT_MASK4_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK4: MASKP26 Position   */
+#define GPIO_PORT_MASK4_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos)                   /*!< GPIO_PORT MASK4: MASKP26 Mask       */
+#define GPIO_PORT_MASK4_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK4: MASKP27 Position   */
+#define GPIO_PORT_MASK4_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos)                   /*!< GPIO_PORT MASK4: MASKP27 Mask       */
+#define GPIO_PORT_MASK4_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK4: MASKP28 Position   */
+#define GPIO_PORT_MASK4_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos)                   /*!< GPIO_PORT MASK4: MASKP28 Mask       */
+#define GPIO_PORT_MASK4_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK4: MASKP29 Position   */
+#define GPIO_PORT_MASK4_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos)                   /*!< GPIO_PORT MASK4: MASKP29 Mask       */
+#define GPIO_PORT_MASK4_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK4: MASKP30 Position   */
+#define GPIO_PORT_MASK4_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos)                   /*!< GPIO_PORT MASK4: MASKP30 Mask       */
+#define GPIO_PORT_MASK4_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK4: MASKP31 Position   */
+#define GPIO_PORT_MASK4_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos)                   /*!< GPIO_PORT MASK4: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK5  ----------------------------------------
+#define GPIO_PORT_MASK5_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK5: MASKP0 Position    */
+#define GPIO_PORT_MASK5_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos)                    /*!< GPIO_PORT MASK5: MASKP0 Mask        */
+#define GPIO_PORT_MASK5_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK5: MASKP1 Position    */
+#define GPIO_PORT_MASK5_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos)                    /*!< GPIO_PORT MASK5: MASKP1 Mask        */
+#define GPIO_PORT_MASK5_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK5: MASKP2 Position    */
+#define GPIO_PORT_MASK5_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos)                    /*!< GPIO_PORT MASK5: MASKP2 Mask        */
+#define GPIO_PORT_MASK5_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK5: MASKP3 Position    */
+#define GPIO_PORT_MASK5_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos)                    /*!< GPIO_PORT MASK5: MASKP3 Mask        */
+#define GPIO_PORT_MASK5_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK5: MASKP4 Position    */
+#define GPIO_PORT_MASK5_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos)                    /*!< GPIO_PORT MASK5: MASKP4 Mask        */
+#define GPIO_PORT_MASK5_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK5: MASKP5 Position    */
+#define GPIO_PORT_MASK5_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos)                    /*!< GPIO_PORT MASK5: MASKP5 Mask        */
+#define GPIO_PORT_MASK5_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK5: MASKP6 Position    */
+#define GPIO_PORT_MASK5_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos)                    /*!< GPIO_PORT MASK5: MASKP6 Mask        */
+#define GPIO_PORT_MASK5_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK5: MASKP7 Position    */
+#define GPIO_PORT_MASK5_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos)                    /*!< GPIO_PORT MASK5: MASKP7 Mask        */
+#define GPIO_PORT_MASK5_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK5: MASKP8 Position    */
+#define GPIO_PORT_MASK5_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos)                    /*!< GPIO_PORT MASK5: MASKP8 Mask        */
+#define GPIO_PORT_MASK5_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK5: MASKP9 Position    */
+#define GPIO_PORT_MASK5_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos)                    /*!< GPIO_PORT MASK5: MASKP9 Mask        */
+#define GPIO_PORT_MASK5_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK5: MASKP10 Position   */
+#define GPIO_PORT_MASK5_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos)                   /*!< GPIO_PORT MASK5: MASKP10 Mask       */
+#define GPIO_PORT_MASK5_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK5: MASKP11 Position   */
+#define GPIO_PORT_MASK5_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos)                   /*!< GPIO_PORT MASK5: MASKP11 Mask       */
+#define GPIO_PORT_MASK5_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK5: MASKP12 Position   */
+#define GPIO_PORT_MASK5_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos)                   /*!< GPIO_PORT MASK5: MASKP12 Mask       */
+#define GPIO_PORT_MASK5_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK5: MASKP13 Position   */
+#define GPIO_PORT_MASK5_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos)                   /*!< GPIO_PORT MASK5: MASKP13 Mask       */
+#define GPIO_PORT_MASK5_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK5: MASKP14 Position   */
+#define GPIO_PORT_MASK5_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos)                   /*!< GPIO_PORT MASK5: MASKP14 Mask       */
+#define GPIO_PORT_MASK5_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK5: MASKP15 Position   */
+#define GPIO_PORT_MASK5_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos)                   /*!< GPIO_PORT MASK5: MASKP15 Mask       */
+#define GPIO_PORT_MASK5_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK5: MASKP16 Position   */
+#define GPIO_PORT_MASK5_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos)                   /*!< GPIO_PORT MASK5: MASKP16 Mask       */
+#define GPIO_PORT_MASK5_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK5: MASKP17 Position   */
+#define GPIO_PORT_MASK5_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos)                   /*!< GPIO_PORT MASK5: MASKP17 Mask       */
+#define GPIO_PORT_MASK5_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK5: MASKP18 Position   */
+#define GPIO_PORT_MASK5_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos)                   /*!< GPIO_PORT MASK5: MASKP18 Mask       */
+#define GPIO_PORT_MASK5_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK5: MASKP19 Position   */
+#define GPIO_PORT_MASK5_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos)                   /*!< GPIO_PORT MASK5: MASKP19 Mask       */
+#define GPIO_PORT_MASK5_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK5: MASKP20 Position   */
+#define GPIO_PORT_MASK5_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos)                   /*!< GPIO_PORT MASK5: MASKP20 Mask       */
+#define GPIO_PORT_MASK5_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK5: MASKP21 Position   */
+#define GPIO_PORT_MASK5_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos)                   /*!< GPIO_PORT MASK5: MASKP21 Mask       */
+#define GPIO_PORT_MASK5_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK5: MASKP22 Position   */
+#define GPIO_PORT_MASK5_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos)                   /*!< GPIO_PORT MASK5: MASKP22 Mask       */
+#define GPIO_PORT_MASK5_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK5: MASKP23 Position   */
+#define GPIO_PORT_MASK5_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos)                   /*!< GPIO_PORT MASK5: MASKP23 Mask       */
+#define GPIO_PORT_MASK5_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK5: MASKP24 Position   */
+#define GPIO_PORT_MASK5_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos)                   /*!< GPIO_PORT MASK5: MASKP24 Mask       */
+#define GPIO_PORT_MASK5_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK5: MASKP25 Position   */
+#define GPIO_PORT_MASK5_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos)                   /*!< GPIO_PORT MASK5: MASKP25 Mask       */
+#define GPIO_PORT_MASK5_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK5: MASKP26 Position   */
+#define GPIO_PORT_MASK5_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos)                   /*!< GPIO_PORT MASK5: MASKP26 Mask       */
+#define GPIO_PORT_MASK5_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK5: MASKP27 Position   */
+#define GPIO_PORT_MASK5_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos)                   /*!< GPIO_PORT MASK5: MASKP27 Mask       */
+#define GPIO_PORT_MASK5_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK5: MASKP28 Position   */
+#define GPIO_PORT_MASK5_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos)                   /*!< GPIO_PORT MASK5: MASKP28 Mask       */
+#define GPIO_PORT_MASK5_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK5: MASKP29 Position   */
+#define GPIO_PORT_MASK5_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos)                   /*!< GPIO_PORT MASK5: MASKP29 Mask       */
+#define GPIO_PORT_MASK5_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK5: MASKP30 Position   */
+#define GPIO_PORT_MASK5_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos)                   /*!< GPIO_PORT MASK5: MASKP30 Mask       */
+#define GPIO_PORT_MASK5_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK5: MASKP31 Position   */
+#define GPIO_PORT_MASK5_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos)                   /*!< GPIO_PORT MASK5: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK6  ----------------------------------------
+#define GPIO_PORT_MASK6_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK6: MASKP0 Position    */
+#define GPIO_PORT_MASK6_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos)                    /*!< GPIO_PORT MASK6: MASKP0 Mask        */
+#define GPIO_PORT_MASK6_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK6: MASKP1 Position    */
+#define GPIO_PORT_MASK6_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos)                    /*!< GPIO_PORT MASK6: MASKP1 Mask        */
+#define GPIO_PORT_MASK6_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK6: MASKP2 Position    */
+#define GPIO_PORT_MASK6_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos)                    /*!< GPIO_PORT MASK6: MASKP2 Mask        */
+#define GPIO_PORT_MASK6_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK6: MASKP3 Position    */
+#define GPIO_PORT_MASK6_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos)                    /*!< GPIO_PORT MASK6: MASKP3 Mask        */
+#define GPIO_PORT_MASK6_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK6: MASKP4 Position    */
+#define GPIO_PORT_MASK6_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos)                    /*!< GPIO_PORT MASK6: MASKP4 Mask        */
+#define GPIO_PORT_MASK6_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK6: MASKP5 Position    */
+#define GPIO_PORT_MASK6_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos)                    /*!< GPIO_PORT MASK6: MASKP5 Mask        */
+#define GPIO_PORT_MASK6_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK6: MASKP6 Position    */
+#define GPIO_PORT_MASK6_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos)                    /*!< GPIO_PORT MASK6: MASKP6 Mask        */
+#define GPIO_PORT_MASK6_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK6: MASKP7 Position    */
+#define GPIO_PORT_MASK6_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos)                    /*!< GPIO_PORT MASK6: MASKP7 Mask        */
+#define GPIO_PORT_MASK6_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK6: MASKP8 Position    */
+#define GPIO_PORT_MASK6_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos)                    /*!< GPIO_PORT MASK6: MASKP8 Mask        */
+#define GPIO_PORT_MASK6_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK6: MASKP9 Position    */
+#define GPIO_PORT_MASK6_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos)                    /*!< GPIO_PORT MASK6: MASKP9 Mask        */
+#define GPIO_PORT_MASK6_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK6: MASKP10 Position   */
+#define GPIO_PORT_MASK6_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos)                   /*!< GPIO_PORT MASK6: MASKP10 Mask       */
+#define GPIO_PORT_MASK6_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK6: MASKP11 Position   */
+#define GPIO_PORT_MASK6_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos)                   /*!< GPIO_PORT MASK6: MASKP11 Mask       */
+#define GPIO_PORT_MASK6_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK6: MASKP12 Position   */
+#define GPIO_PORT_MASK6_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos)                   /*!< GPIO_PORT MASK6: MASKP12 Mask       */
+#define GPIO_PORT_MASK6_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK6: MASKP13 Position   */
+#define GPIO_PORT_MASK6_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos)                   /*!< GPIO_PORT MASK6: MASKP13 Mask       */
+#define GPIO_PORT_MASK6_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK6: MASKP14 Position   */
+#define GPIO_PORT_MASK6_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos)                   /*!< GPIO_PORT MASK6: MASKP14 Mask       */
+#define GPIO_PORT_MASK6_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK6: MASKP15 Position   */
+#define GPIO_PORT_MASK6_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos)                   /*!< GPIO_PORT MASK6: MASKP15 Mask       */
+#define GPIO_PORT_MASK6_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK6: MASKP16 Position   */
+#define GPIO_PORT_MASK6_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos)                   /*!< GPIO_PORT MASK6: MASKP16 Mask       */
+#define GPIO_PORT_MASK6_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK6: MASKP17 Position   */
+#define GPIO_PORT_MASK6_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos)                   /*!< GPIO_PORT MASK6: MASKP17 Mask       */
+#define GPIO_PORT_MASK6_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK6: MASKP18 Position   */
+#define GPIO_PORT_MASK6_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos)                   /*!< GPIO_PORT MASK6: MASKP18 Mask       */
+#define GPIO_PORT_MASK6_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK6: MASKP19 Position   */
+#define GPIO_PORT_MASK6_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos)                   /*!< GPIO_PORT MASK6: MASKP19 Mask       */
+#define GPIO_PORT_MASK6_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK6: MASKP20 Position   */
+#define GPIO_PORT_MASK6_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos)                   /*!< GPIO_PORT MASK6: MASKP20 Mask       */
+#define GPIO_PORT_MASK6_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK6: MASKP21 Position   */
+#define GPIO_PORT_MASK6_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos)                   /*!< GPIO_PORT MASK6: MASKP21 Mask       */
+#define GPIO_PORT_MASK6_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK6: MASKP22 Position   */
+#define GPIO_PORT_MASK6_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos)                   /*!< GPIO_PORT MASK6: MASKP22 Mask       */
+#define GPIO_PORT_MASK6_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK6: MASKP23 Position   */
+#define GPIO_PORT_MASK6_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos)                   /*!< GPIO_PORT MASK6: MASKP23 Mask       */
+#define GPIO_PORT_MASK6_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK6: MASKP24 Position   */
+#define GPIO_PORT_MASK6_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos)                   /*!< GPIO_PORT MASK6: MASKP24 Mask       */
+#define GPIO_PORT_MASK6_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK6: MASKP25 Position   */
+#define GPIO_PORT_MASK6_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos)                   /*!< GPIO_PORT MASK6: MASKP25 Mask       */
+#define GPIO_PORT_MASK6_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK6: MASKP26 Position   */
+#define GPIO_PORT_MASK6_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos)                   /*!< GPIO_PORT MASK6: MASKP26 Mask       */
+#define GPIO_PORT_MASK6_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK6: MASKP27 Position   */
+#define GPIO_PORT_MASK6_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos)                   /*!< GPIO_PORT MASK6: MASKP27 Mask       */
+#define GPIO_PORT_MASK6_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK6: MASKP28 Position   */
+#define GPIO_PORT_MASK6_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos)                   /*!< GPIO_PORT MASK6: MASKP28 Mask       */
+#define GPIO_PORT_MASK6_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK6: MASKP29 Position   */
+#define GPIO_PORT_MASK6_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos)                   /*!< GPIO_PORT MASK6: MASKP29 Mask       */
+#define GPIO_PORT_MASK6_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK6: MASKP30 Position   */
+#define GPIO_PORT_MASK6_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos)                   /*!< GPIO_PORT MASK6: MASKP30 Mask       */
+#define GPIO_PORT_MASK6_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK6: MASKP31 Position   */
+#define GPIO_PORT_MASK6_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos)                   /*!< GPIO_PORT MASK6: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK7  ----------------------------------------
+#define GPIO_PORT_MASK7_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK7: MASKP0 Position    */
+#define GPIO_PORT_MASK7_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos)                    /*!< GPIO_PORT MASK7: MASKP0 Mask        */
+#define GPIO_PORT_MASK7_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK7: MASKP1 Position    */
+#define GPIO_PORT_MASK7_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos)                    /*!< GPIO_PORT MASK7: MASKP1 Mask        */
+#define GPIO_PORT_MASK7_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK7: MASKP2 Position    */
+#define GPIO_PORT_MASK7_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos)                    /*!< GPIO_PORT MASK7: MASKP2 Mask        */
+#define GPIO_PORT_MASK7_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK7: MASKP3 Position    */
+#define GPIO_PORT_MASK7_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos)                    /*!< GPIO_PORT MASK7: MASKP3 Mask        */
+#define GPIO_PORT_MASK7_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK7: MASKP4 Position    */
+#define GPIO_PORT_MASK7_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos)                    /*!< GPIO_PORT MASK7: MASKP4 Mask        */
+#define GPIO_PORT_MASK7_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK7: MASKP5 Position    */
+#define GPIO_PORT_MASK7_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos)                    /*!< GPIO_PORT MASK7: MASKP5 Mask        */
+#define GPIO_PORT_MASK7_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK7: MASKP6 Position    */
+#define GPIO_PORT_MASK7_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos)                    /*!< GPIO_PORT MASK7: MASKP6 Mask        */
+#define GPIO_PORT_MASK7_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK7: MASKP7 Position    */
+#define GPIO_PORT_MASK7_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos)                    /*!< GPIO_PORT MASK7: MASKP7 Mask        */
+#define GPIO_PORT_MASK7_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK7: MASKP8 Position    */
+#define GPIO_PORT_MASK7_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos)                    /*!< GPIO_PORT MASK7: MASKP8 Mask        */
+#define GPIO_PORT_MASK7_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK7: MASKP9 Position    */
+#define GPIO_PORT_MASK7_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos)                    /*!< GPIO_PORT MASK7: MASKP9 Mask        */
+#define GPIO_PORT_MASK7_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK7: MASKP10 Position   */
+#define GPIO_PORT_MASK7_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos)                   /*!< GPIO_PORT MASK7: MASKP10 Mask       */
+#define GPIO_PORT_MASK7_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK7: MASKP11 Position   */
+#define GPIO_PORT_MASK7_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos)                   /*!< GPIO_PORT MASK7: MASKP11 Mask       */
+#define GPIO_PORT_MASK7_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK7: MASKP12 Position   */
+#define GPIO_PORT_MASK7_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos)                   /*!< GPIO_PORT MASK7: MASKP12 Mask       */
+#define GPIO_PORT_MASK7_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK7: MASKP13 Position   */
+#define GPIO_PORT_MASK7_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos)                   /*!< GPIO_PORT MASK7: MASKP13 Mask       */
+#define GPIO_PORT_MASK7_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK7: MASKP14 Position   */
+#define GPIO_PORT_MASK7_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos)                   /*!< GPIO_PORT MASK7: MASKP14 Mask       */
+#define GPIO_PORT_MASK7_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK7: MASKP15 Position   */
+#define GPIO_PORT_MASK7_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos)                   /*!< GPIO_PORT MASK7: MASKP15 Mask       */
+#define GPIO_PORT_MASK7_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK7: MASKP16 Position   */
+#define GPIO_PORT_MASK7_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos)                   /*!< GPIO_PORT MASK7: MASKP16 Mask       */
+#define GPIO_PORT_MASK7_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK7: MASKP17 Position   */
+#define GPIO_PORT_MASK7_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos)                   /*!< GPIO_PORT MASK7: MASKP17 Mask       */
+#define GPIO_PORT_MASK7_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK7: MASKP18 Position   */
+#define GPIO_PORT_MASK7_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos)                   /*!< GPIO_PORT MASK7: MASKP18 Mask       */
+#define GPIO_PORT_MASK7_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK7: MASKP19 Position   */
+#define GPIO_PORT_MASK7_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos)                   /*!< GPIO_PORT MASK7: MASKP19 Mask       */
+#define GPIO_PORT_MASK7_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK7: MASKP20 Position   */
+#define GPIO_PORT_MASK7_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos)                   /*!< GPIO_PORT MASK7: MASKP20 Mask       */
+#define GPIO_PORT_MASK7_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK7: MASKP21 Position   */
+#define GPIO_PORT_MASK7_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos)                   /*!< GPIO_PORT MASK7: MASKP21 Mask       */
+#define GPIO_PORT_MASK7_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK7: MASKP22 Position   */
+#define GPIO_PORT_MASK7_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos)                   /*!< GPIO_PORT MASK7: MASKP22 Mask       */
+#define GPIO_PORT_MASK7_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK7: MASKP23 Position   */
+#define GPIO_PORT_MASK7_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos)                   /*!< GPIO_PORT MASK7: MASKP23 Mask       */
+#define GPIO_PORT_MASK7_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK7: MASKP24 Position   */
+#define GPIO_PORT_MASK7_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos)                   /*!< GPIO_PORT MASK7: MASKP24 Mask       */
+#define GPIO_PORT_MASK7_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK7: MASKP25 Position   */
+#define GPIO_PORT_MASK7_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos)                   /*!< GPIO_PORT MASK7: MASKP25 Mask       */
+#define GPIO_PORT_MASK7_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK7: MASKP26 Position   */
+#define GPIO_PORT_MASK7_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos)                   /*!< GPIO_PORT MASK7: MASKP26 Mask       */
+#define GPIO_PORT_MASK7_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK7: MASKP27 Position   */
+#define GPIO_PORT_MASK7_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos)                   /*!< GPIO_PORT MASK7: MASKP27 Mask       */
+#define GPIO_PORT_MASK7_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK7: MASKP28 Position   */
+#define GPIO_PORT_MASK7_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos)                   /*!< GPIO_PORT MASK7: MASKP28 Mask       */
+#define GPIO_PORT_MASK7_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK7: MASKP29 Position   */
+#define GPIO_PORT_MASK7_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos)                   /*!< GPIO_PORT MASK7: MASKP29 Mask       */
+#define GPIO_PORT_MASK7_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK7: MASKP30 Position   */
+#define GPIO_PORT_MASK7_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos)                   /*!< GPIO_PORT MASK7: MASKP30 Mask       */
+#define GPIO_PORT_MASK7_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK7: MASKP31 Position   */
+#define GPIO_PORT_MASK7_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos)                   /*!< GPIO_PORT MASK7: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_PIN0  -----------------------------------------
+#define GPIO_PORT_PIN0_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN0: PORT0 Position      */
+#define GPIO_PORT_PIN0_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT0_Pos)                      /*!< GPIO_PORT PIN0: PORT0 Mask          */
+#define GPIO_PORT_PIN0_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN0: PORT1 Position      */
+#define GPIO_PORT_PIN0_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT1_Pos)                      /*!< GPIO_PORT PIN0: PORT1 Mask          */
+#define GPIO_PORT_PIN0_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN0: PORT2 Position      */
+#define GPIO_PORT_PIN0_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT2_Pos)                      /*!< GPIO_PORT PIN0: PORT2 Mask          */
+#define GPIO_PORT_PIN0_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN0: PORT3 Position      */
+#define GPIO_PORT_PIN0_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT3_Pos)                      /*!< GPIO_PORT PIN0: PORT3 Mask          */
+#define GPIO_PORT_PIN0_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN0: PORT4 Position      */
+#define GPIO_PORT_PIN0_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT4_Pos)                      /*!< GPIO_PORT PIN0: PORT4 Mask          */
+#define GPIO_PORT_PIN0_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN0: PORT5 Position      */
+#define GPIO_PORT_PIN0_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT5_Pos)                      /*!< GPIO_PORT PIN0: PORT5 Mask          */
+#define GPIO_PORT_PIN0_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN0: PORT6 Position      */
+#define GPIO_PORT_PIN0_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT6_Pos)                      /*!< GPIO_PORT PIN0: PORT6 Mask          */
+#define GPIO_PORT_PIN0_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN0: PORT7 Position      */
+#define GPIO_PORT_PIN0_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT7_Pos)                      /*!< GPIO_PORT PIN0: PORT7 Mask          */
+#define GPIO_PORT_PIN0_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN0: PORT8 Position      */
+#define GPIO_PORT_PIN0_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT8_Pos)                      /*!< GPIO_PORT PIN0: PORT8 Mask          */
+#define GPIO_PORT_PIN0_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN0: PORT9 Position      */
+#define GPIO_PORT_PIN0_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT9_Pos)                      /*!< GPIO_PORT PIN0: PORT9 Mask          */
+#define GPIO_PORT_PIN0_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN0: PORT10 Position     */
+#define GPIO_PORT_PIN0_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT10_Pos)                     /*!< GPIO_PORT PIN0: PORT10 Mask         */
+#define GPIO_PORT_PIN0_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN0: PORT11 Position     */
+#define GPIO_PORT_PIN0_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT11_Pos)                     /*!< GPIO_PORT PIN0: PORT11 Mask         */
+#define GPIO_PORT_PIN0_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN0: PORT12 Position     */
+#define GPIO_PORT_PIN0_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT12_Pos)                     /*!< GPIO_PORT PIN0: PORT12 Mask         */
+#define GPIO_PORT_PIN0_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN0: PORT13 Position     */
+#define GPIO_PORT_PIN0_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT13_Pos)                     /*!< GPIO_PORT PIN0: PORT13 Mask         */
+#define GPIO_PORT_PIN0_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN0: PORT14 Position     */
+#define GPIO_PORT_PIN0_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT14_Pos)                     /*!< GPIO_PORT PIN0: PORT14 Mask         */
+#define GPIO_PORT_PIN0_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN0: PORT15 Position     */
+#define GPIO_PORT_PIN0_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT15_Pos)                     /*!< GPIO_PORT PIN0: PORT15 Mask         */
+#define GPIO_PORT_PIN0_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN0: PORT16 Position     */
+#define GPIO_PORT_PIN0_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT16_Pos)                     /*!< GPIO_PORT PIN0: PORT16 Mask         */
+#define GPIO_PORT_PIN0_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN0: PORT17 Position     */
+#define GPIO_PORT_PIN0_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT17_Pos)                     /*!< GPIO_PORT PIN0: PORT17 Mask         */
+#define GPIO_PORT_PIN0_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN0: PORT18 Position     */
+#define GPIO_PORT_PIN0_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT18_Pos)                     /*!< GPIO_PORT PIN0: PORT18 Mask         */
+#define GPIO_PORT_PIN0_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN0: PORT19 Position     */
+#define GPIO_PORT_PIN0_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT19_Pos)                     /*!< GPIO_PORT PIN0: PORT19 Mask         */
+#define GPIO_PORT_PIN0_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN0: PORT20 Position     */
+#define GPIO_PORT_PIN0_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT20_Pos)                     /*!< GPIO_PORT PIN0: PORT20 Mask         */
+#define GPIO_PORT_PIN0_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN0: PORT21 Position     */
+#define GPIO_PORT_PIN0_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT21_Pos)                     /*!< GPIO_PORT PIN0: PORT21 Mask         */
+#define GPIO_PORT_PIN0_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN0: PORT22 Position     */
+#define GPIO_PORT_PIN0_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT22_Pos)                     /*!< GPIO_PORT PIN0: PORT22 Mask         */
+#define GPIO_PORT_PIN0_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN0: PORT23 Position     */
+#define GPIO_PORT_PIN0_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT23_Pos)                     /*!< GPIO_PORT PIN0: PORT23 Mask         */
+#define GPIO_PORT_PIN0_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN0: PORT24 Position     */
+#define GPIO_PORT_PIN0_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT24_Pos)                     /*!< GPIO_PORT PIN0: PORT24 Mask         */
+#define GPIO_PORT_PIN0_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN0: PORT25 Position     */
+#define GPIO_PORT_PIN0_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT25_Pos)                     /*!< GPIO_PORT PIN0: PORT25 Mask         */
+#define GPIO_PORT_PIN0_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN0: PORT26 Position     */
+#define GPIO_PORT_PIN0_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT26_Pos)                     /*!< GPIO_PORT PIN0: PORT26 Mask         */
+#define GPIO_PORT_PIN0_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN0: PORT27 Position     */
+#define GPIO_PORT_PIN0_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT27_Pos)                     /*!< GPIO_PORT PIN0: PORT27 Mask         */
+#define GPIO_PORT_PIN0_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN0: PORT28 Position     */
+#define GPIO_PORT_PIN0_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT28_Pos)                     /*!< GPIO_PORT PIN0: PORT28 Mask         */
+#define GPIO_PORT_PIN0_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN0: PORT29 Position     */
+#define GPIO_PORT_PIN0_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT29_Pos)                     /*!< GPIO_PORT PIN0: PORT29 Mask         */
+#define GPIO_PORT_PIN0_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN0: PORT30 Position     */
+#define GPIO_PORT_PIN0_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT30_Pos)                     /*!< GPIO_PORT PIN0: PORT30 Mask         */
+#define GPIO_PORT_PIN0_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN0: PORT31 Position     */
+#define GPIO_PORT_PIN0_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT31_Pos)                     /*!< GPIO_PORT PIN0: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN1  -----------------------------------------
+#define GPIO_PORT_PIN1_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN1: PORT0 Position      */
+#define GPIO_PORT_PIN1_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT0_Pos)                      /*!< GPIO_PORT PIN1: PORT0 Mask          */
+#define GPIO_PORT_PIN1_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN1: PORT1 Position      */
+#define GPIO_PORT_PIN1_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT1_Pos)                      /*!< GPIO_PORT PIN1: PORT1 Mask          */
+#define GPIO_PORT_PIN1_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN1: PORT2 Position      */
+#define GPIO_PORT_PIN1_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT2_Pos)                      /*!< GPIO_PORT PIN1: PORT2 Mask          */
+#define GPIO_PORT_PIN1_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN1: PORT3 Position      */
+#define GPIO_PORT_PIN1_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT3_Pos)                      /*!< GPIO_PORT PIN1: PORT3 Mask          */
+#define GPIO_PORT_PIN1_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN1: PORT4 Position      */
+#define GPIO_PORT_PIN1_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT4_Pos)                      /*!< GPIO_PORT PIN1: PORT4 Mask          */
+#define GPIO_PORT_PIN1_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN1: PORT5 Position      */
+#define GPIO_PORT_PIN1_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT5_Pos)                      /*!< GPIO_PORT PIN1: PORT5 Mask          */
+#define GPIO_PORT_PIN1_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN1: PORT6 Position      */
+#define GPIO_PORT_PIN1_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT6_Pos)                      /*!< GPIO_PORT PIN1: PORT6 Mask          */
+#define GPIO_PORT_PIN1_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN1: PORT7 Position      */
+#define GPIO_PORT_PIN1_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT7_Pos)                      /*!< GPIO_PORT PIN1: PORT7 Mask          */
+#define GPIO_PORT_PIN1_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN1: PORT8 Position      */
+#define GPIO_PORT_PIN1_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT8_Pos)                      /*!< GPIO_PORT PIN1: PORT8 Mask          */
+#define GPIO_PORT_PIN1_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN1: PORT9 Position      */
+#define GPIO_PORT_PIN1_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT9_Pos)                      /*!< GPIO_PORT PIN1: PORT9 Mask          */
+#define GPIO_PORT_PIN1_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN1: PORT10 Position     */
+#define GPIO_PORT_PIN1_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT10_Pos)                     /*!< GPIO_PORT PIN1: PORT10 Mask         */
+#define GPIO_PORT_PIN1_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN1: PORT11 Position     */
+#define GPIO_PORT_PIN1_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT11_Pos)                     /*!< GPIO_PORT PIN1: PORT11 Mask         */
+#define GPIO_PORT_PIN1_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN1: PORT12 Position     */
+#define GPIO_PORT_PIN1_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT12_Pos)                     /*!< GPIO_PORT PIN1: PORT12 Mask         */
+#define GPIO_PORT_PIN1_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN1: PORT13 Position     */
+#define GPIO_PORT_PIN1_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT13_Pos)                     /*!< GPIO_PORT PIN1: PORT13 Mask         */
+#define GPIO_PORT_PIN1_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN1: PORT14 Position     */
+#define GPIO_PORT_PIN1_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT14_Pos)                     /*!< GPIO_PORT PIN1: PORT14 Mask         */
+#define GPIO_PORT_PIN1_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN1: PORT15 Position     */
+#define GPIO_PORT_PIN1_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT15_Pos)                     /*!< GPIO_PORT PIN1: PORT15 Mask         */
+#define GPIO_PORT_PIN1_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN1: PORT16 Position     */
+#define GPIO_PORT_PIN1_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT16_Pos)                     /*!< GPIO_PORT PIN1: PORT16 Mask         */
+#define GPIO_PORT_PIN1_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN1: PORT17 Position     */
+#define GPIO_PORT_PIN1_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT17_Pos)                     /*!< GPIO_PORT PIN1: PORT17 Mask         */
+#define GPIO_PORT_PIN1_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN1: PORT18 Position     */
+#define GPIO_PORT_PIN1_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT18_Pos)                     /*!< GPIO_PORT PIN1: PORT18 Mask         */
+#define GPIO_PORT_PIN1_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN1: PORT19 Position     */
+#define GPIO_PORT_PIN1_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT19_Pos)                     /*!< GPIO_PORT PIN1: PORT19 Mask         */
+#define GPIO_PORT_PIN1_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN1: PORT20 Position     */
+#define GPIO_PORT_PIN1_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT20_Pos)                     /*!< GPIO_PORT PIN1: PORT20 Mask         */
+#define GPIO_PORT_PIN1_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN1: PORT21 Position     */
+#define GPIO_PORT_PIN1_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT21_Pos)                     /*!< GPIO_PORT PIN1: PORT21 Mask         */
+#define GPIO_PORT_PIN1_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN1: PORT22 Position     */
+#define GPIO_PORT_PIN1_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT22_Pos)                     /*!< GPIO_PORT PIN1: PORT22 Mask         */
+#define GPIO_PORT_PIN1_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN1: PORT23 Position     */
+#define GPIO_PORT_PIN1_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT23_Pos)                     /*!< GPIO_PORT PIN1: PORT23 Mask         */
+#define GPIO_PORT_PIN1_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN1: PORT24 Position     */
+#define GPIO_PORT_PIN1_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT24_Pos)                     /*!< GPIO_PORT PIN1: PORT24 Mask         */
+#define GPIO_PORT_PIN1_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN1: PORT25 Position     */
+#define GPIO_PORT_PIN1_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT25_Pos)                     /*!< GPIO_PORT PIN1: PORT25 Mask         */
+#define GPIO_PORT_PIN1_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN1: PORT26 Position     */
+#define GPIO_PORT_PIN1_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT26_Pos)                     /*!< GPIO_PORT PIN1: PORT26 Mask         */
+#define GPIO_PORT_PIN1_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN1: PORT27 Position     */
+#define GPIO_PORT_PIN1_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT27_Pos)                     /*!< GPIO_PORT PIN1: PORT27 Mask         */
+#define GPIO_PORT_PIN1_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN1: PORT28 Position     */
+#define GPIO_PORT_PIN1_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT28_Pos)                     /*!< GPIO_PORT PIN1: PORT28 Mask         */
+#define GPIO_PORT_PIN1_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN1: PORT29 Position     */
+#define GPIO_PORT_PIN1_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT29_Pos)                     /*!< GPIO_PORT PIN1: PORT29 Mask         */
+#define GPIO_PORT_PIN1_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN1: PORT30 Position     */
+#define GPIO_PORT_PIN1_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT30_Pos)                     /*!< GPIO_PORT PIN1: PORT30 Mask         */
+#define GPIO_PORT_PIN1_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN1: PORT31 Position     */
+#define GPIO_PORT_PIN1_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT31_Pos)                     /*!< GPIO_PORT PIN1: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN2  -----------------------------------------
+#define GPIO_PORT_PIN2_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN2: PORT0 Position      */
+#define GPIO_PORT_PIN2_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT0_Pos)                      /*!< GPIO_PORT PIN2: PORT0 Mask          */
+#define GPIO_PORT_PIN2_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN2: PORT1 Position      */
+#define GPIO_PORT_PIN2_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT1_Pos)                      /*!< GPIO_PORT PIN2: PORT1 Mask          */
+#define GPIO_PORT_PIN2_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN2: PORT2 Position      */
+#define GPIO_PORT_PIN2_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT2_Pos)                      /*!< GPIO_PORT PIN2: PORT2 Mask          */
+#define GPIO_PORT_PIN2_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN2: PORT3 Position      */
+#define GPIO_PORT_PIN2_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT3_Pos)                      /*!< GPIO_PORT PIN2: PORT3 Mask          */
+#define GPIO_PORT_PIN2_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN2: PORT4 Position      */
+#define GPIO_PORT_PIN2_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT4_Pos)                      /*!< GPIO_PORT PIN2: PORT4 Mask          */
+#define GPIO_PORT_PIN2_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN2: PORT5 Position      */
+#define GPIO_PORT_PIN2_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT5_Pos)                      /*!< GPIO_PORT PIN2: PORT5 Mask          */
+#define GPIO_PORT_PIN2_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN2: PORT6 Position      */
+#define GPIO_PORT_PIN2_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT6_Pos)                      /*!< GPIO_PORT PIN2: PORT6 Mask          */
+#define GPIO_PORT_PIN2_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN2: PORT7 Position      */
+#define GPIO_PORT_PIN2_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT7_Pos)                      /*!< GPIO_PORT PIN2: PORT7 Mask          */
+#define GPIO_PORT_PIN2_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN2: PORT8 Position      */
+#define GPIO_PORT_PIN2_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT8_Pos)                      /*!< GPIO_PORT PIN2: PORT8 Mask          */
+#define GPIO_PORT_PIN2_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN2: PORT9 Position      */
+#define GPIO_PORT_PIN2_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT9_Pos)                      /*!< GPIO_PORT PIN2: PORT9 Mask          */
+#define GPIO_PORT_PIN2_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN2: PORT10 Position     */
+#define GPIO_PORT_PIN2_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT10_Pos)                     /*!< GPIO_PORT PIN2: PORT10 Mask         */
+#define GPIO_PORT_PIN2_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN2: PORT11 Position     */
+#define GPIO_PORT_PIN2_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT11_Pos)                     /*!< GPIO_PORT PIN2: PORT11 Mask         */
+#define GPIO_PORT_PIN2_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN2: PORT12 Position     */
+#define GPIO_PORT_PIN2_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT12_Pos)                     /*!< GPIO_PORT PIN2: PORT12 Mask         */
+#define GPIO_PORT_PIN2_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN2: PORT13 Position     */
+#define GPIO_PORT_PIN2_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT13_Pos)                     /*!< GPIO_PORT PIN2: PORT13 Mask         */
+#define GPIO_PORT_PIN2_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN2: PORT14 Position     */
+#define GPIO_PORT_PIN2_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT14_Pos)                     /*!< GPIO_PORT PIN2: PORT14 Mask         */
+#define GPIO_PORT_PIN2_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN2: PORT15 Position     */
+#define GPIO_PORT_PIN2_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT15_Pos)                     /*!< GPIO_PORT PIN2: PORT15 Mask         */
+#define GPIO_PORT_PIN2_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN2: PORT16 Position     */
+#define GPIO_PORT_PIN2_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT16_Pos)                     /*!< GPIO_PORT PIN2: PORT16 Mask         */
+#define GPIO_PORT_PIN2_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN2: PORT17 Position     */
+#define GPIO_PORT_PIN2_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT17_Pos)                     /*!< GPIO_PORT PIN2: PORT17 Mask         */
+#define GPIO_PORT_PIN2_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN2: PORT18 Position     */
+#define GPIO_PORT_PIN2_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT18_Pos)                     /*!< GPIO_PORT PIN2: PORT18 Mask         */
+#define GPIO_PORT_PIN2_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN2: PORT19 Position     */
+#define GPIO_PORT_PIN2_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT19_Pos)                     /*!< GPIO_PORT PIN2: PORT19 Mask         */
+#define GPIO_PORT_PIN2_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN2: PORT20 Position     */
+#define GPIO_PORT_PIN2_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT20_Pos)                     /*!< GPIO_PORT PIN2: PORT20 Mask         */
+#define GPIO_PORT_PIN2_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN2: PORT21 Position     */
+#define GPIO_PORT_PIN2_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT21_Pos)                     /*!< GPIO_PORT PIN2: PORT21 Mask         */
+#define GPIO_PORT_PIN2_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN2: PORT22 Position     */
+#define GPIO_PORT_PIN2_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT22_Pos)                     /*!< GPIO_PORT PIN2: PORT22 Mask         */
+#define GPIO_PORT_PIN2_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN2: PORT23 Position     */
+#define GPIO_PORT_PIN2_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT23_Pos)                     /*!< GPIO_PORT PIN2: PORT23 Mask         */
+#define GPIO_PORT_PIN2_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN2: PORT24 Position     */
+#define GPIO_PORT_PIN2_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT24_Pos)                     /*!< GPIO_PORT PIN2: PORT24 Mask         */
+#define GPIO_PORT_PIN2_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN2: PORT25 Position     */
+#define GPIO_PORT_PIN2_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT25_Pos)                     /*!< GPIO_PORT PIN2: PORT25 Mask         */
+#define GPIO_PORT_PIN2_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN2: PORT26 Position     */
+#define GPIO_PORT_PIN2_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT26_Pos)                     /*!< GPIO_PORT PIN2: PORT26 Mask         */
+#define GPIO_PORT_PIN2_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN2: PORT27 Position     */
+#define GPIO_PORT_PIN2_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT27_Pos)                     /*!< GPIO_PORT PIN2: PORT27 Mask         */
+#define GPIO_PORT_PIN2_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN2: PORT28 Position     */
+#define GPIO_PORT_PIN2_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT28_Pos)                     /*!< GPIO_PORT PIN2: PORT28 Mask         */
+#define GPIO_PORT_PIN2_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN2: PORT29 Position     */
+#define GPIO_PORT_PIN2_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT29_Pos)                     /*!< GPIO_PORT PIN2: PORT29 Mask         */
+#define GPIO_PORT_PIN2_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN2: PORT30 Position     */
+#define GPIO_PORT_PIN2_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT30_Pos)                     /*!< GPIO_PORT PIN2: PORT30 Mask         */
+#define GPIO_PORT_PIN2_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN2: PORT31 Position     */
+#define GPIO_PORT_PIN2_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT31_Pos)                     /*!< GPIO_PORT PIN2: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN3  -----------------------------------------
+#define GPIO_PORT_PIN3_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN3: PORT0 Position      */
+#define GPIO_PORT_PIN3_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT0_Pos)                      /*!< GPIO_PORT PIN3: PORT0 Mask          */
+#define GPIO_PORT_PIN3_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN3: PORT1 Position      */
+#define GPIO_PORT_PIN3_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT1_Pos)                      /*!< GPIO_PORT PIN3: PORT1 Mask          */
+#define GPIO_PORT_PIN3_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN3: PORT2 Position      */
+#define GPIO_PORT_PIN3_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT2_Pos)                      /*!< GPIO_PORT PIN3: PORT2 Mask          */
+#define GPIO_PORT_PIN3_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN3: PORT3 Position      */
+#define GPIO_PORT_PIN3_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT3_Pos)                      /*!< GPIO_PORT PIN3: PORT3 Mask          */
+#define GPIO_PORT_PIN3_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN3: PORT4 Position      */
+#define GPIO_PORT_PIN3_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT4_Pos)                      /*!< GPIO_PORT PIN3: PORT4 Mask          */
+#define GPIO_PORT_PIN3_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN3: PORT5 Position      */
+#define GPIO_PORT_PIN3_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT5_Pos)                      /*!< GPIO_PORT PIN3: PORT5 Mask          */
+#define GPIO_PORT_PIN3_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN3: PORT6 Position      */
+#define GPIO_PORT_PIN3_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT6_Pos)                      /*!< GPIO_PORT PIN3: PORT6 Mask          */
+#define GPIO_PORT_PIN3_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN3: PORT7 Position      */
+#define GPIO_PORT_PIN3_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT7_Pos)                      /*!< GPIO_PORT PIN3: PORT7 Mask          */
+#define GPIO_PORT_PIN3_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN3: PORT8 Position      */
+#define GPIO_PORT_PIN3_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT8_Pos)                      /*!< GPIO_PORT PIN3: PORT8 Mask          */
+#define GPIO_PORT_PIN3_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN3: PORT9 Position      */
+#define GPIO_PORT_PIN3_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT9_Pos)                      /*!< GPIO_PORT PIN3: PORT9 Mask          */
+#define GPIO_PORT_PIN3_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN3: PORT10 Position     */
+#define GPIO_PORT_PIN3_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT10_Pos)                     /*!< GPIO_PORT PIN3: PORT10 Mask         */
+#define GPIO_PORT_PIN3_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN3: PORT11 Position     */
+#define GPIO_PORT_PIN3_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT11_Pos)                     /*!< GPIO_PORT PIN3: PORT11 Mask         */
+#define GPIO_PORT_PIN3_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN3: PORT12 Position     */
+#define GPIO_PORT_PIN3_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT12_Pos)                     /*!< GPIO_PORT PIN3: PORT12 Mask         */
+#define GPIO_PORT_PIN3_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN3: PORT13 Position     */
+#define GPIO_PORT_PIN3_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT13_Pos)                     /*!< GPIO_PORT PIN3: PORT13 Mask         */
+#define GPIO_PORT_PIN3_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN3: PORT14 Position     */
+#define GPIO_PORT_PIN3_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT14_Pos)                     /*!< GPIO_PORT PIN3: PORT14 Mask         */
+#define GPIO_PORT_PIN3_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN3: PORT15 Position     */
+#define GPIO_PORT_PIN3_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT15_Pos)                     /*!< GPIO_PORT PIN3: PORT15 Mask         */
+#define GPIO_PORT_PIN3_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN3: PORT16 Position     */
+#define GPIO_PORT_PIN3_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT16_Pos)                     /*!< GPIO_PORT PIN3: PORT16 Mask         */
+#define GPIO_PORT_PIN3_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN3: PORT17 Position     */
+#define GPIO_PORT_PIN3_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT17_Pos)                     /*!< GPIO_PORT PIN3: PORT17 Mask         */
+#define GPIO_PORT_PIN3_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN3: PORT18 Position     */
+#define GPIO_PORT_PIN3_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT18_Pos)                     /*!< GPIO_PORT PIN3: PORT18 Mask         */
+#define GPIO_PORT_PIN3_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN3: PORT19 Position     */
+#define GPIO_PORT_PIN3_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT19_Pos)                     /*!< GPIO_PORT PIN3: PORT19 Mask         */
+#define GPIO_PORT_PIN3_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN3: PORT20 Position     */
+#define GPIO_PORT_PIN3_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT20_Pos)                     /*!< GPIO_PORT PIN3: PORT20 Mask         */
+#define GPIO_PORT_PIN3_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN3: PORT21 Position     */
+#define GPIO_PORT_PIN3_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT21_Pos)                     /*!< GPIO_PORT PIN3: PORT21 Mask         */
+#define GPIO_PORT_PIN3_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN3: PORT22 Position     */
+#define GPIO_PORT_PIN3_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT22_Pos)                     /*!< GPIO_PORT PIN3: PORT22 Mask         */
+#define GPIO_PORT_PIN3_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN3: PORT23 Position     */
+#define GPIO_PORT_PIN3_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT23_Pos)                     /*!< GPIO_PORT PIN3: PORT23 Mask         */
+#define GPIO_PORT_PIN3_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN3: PORT24 Position     */
+#define GPIO_PORT_PIN3_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT24_Pos)                     /*!< GPIO_PORT PIN3: PORT24 Mask         */
+#define GPIO_PORT_PIN3_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN3: PORT25 Position     */
+#define GPIO_PORT_PIN3_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT25_Pos)                     /*!< GPIO_PORT PIN3: PORT25 Mask         */
+#define GPIO_PORT_PIN3_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN3: PORT26 Position     */
+#define GPIO_PORT_PIN3_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT26_Pos)                     /*!< GPIO_PORT PIN3: PORT26 Mask         */
+#define GPIO_PORT_PIN3_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN3: PORT27 Position     */
+#define GPIO_PORT_PIN3_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT27_Pos)                     /*!< GPIO_PORT PIN3: PORT27 Mask         */
+#define GPIO_PORT_PIN3_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN3: PORT28 Position     */
+#define GPIO_PORT_PIN3_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT28_Pos)                     /*!< GPIO_PORT PIN3: PORT28 Mask         */
+#define GPIO_PORT_PIN3_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN3: PORT29 Position     */
+#define GPIO_PORT_PIN3_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT29_Pos)                     /*!< GPIO_PORT PIN3: PORT29 Mask         */
+#define GPIO_PORT_PIN3_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN3: PORT30 Position     */
+#define GPIO_PORT_PIN3_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT30_Pos)                     /*!< GPIO_PORT PIN3: PORT30 Mask         */
+#define GPIO_PORT_PIN3_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN3: PORT31 Position     */
+#define GPIO_PORT_PIN3_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT31_Pos)                     /*!< GPIO_PORT PIN3: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN4  -----------------------------------------
+#define GPIO_PORT_PIN4_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN4: PORT0 Position      */
+#define GPIO_PORT_PIN4_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT0_Pos)                      /*!< GPIO_PORT PIN4: PORT0 Mask          */
+#define GPIO_PORT_PIN4_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN4: PORT1 Position      */
+#define GPIO_PORT_PIN4_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT1_Pos)                      /*!< GPIO_PORT PIN4: PORT1 Mask          */
+#define GPIO_PORT_PIN4_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN4: PORT2 Position      */
+#define GPIO_PORT_PIN4_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT2_Pos)                      /*!< GPIO_PORT PIN4: PORT2 Mask          */
+#define GPIO_PORT_PIN4_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN4: PORT3 Position      */
+#define GPIO_PORT_PIN4_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT3_Pos)                      /*!< GPIO_PORT PIN4: PORT3 Mask          */
+#define GPIO_PORT_PIN4_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN4: PORT4 Position      */
+#define GPIO_PORT_PIN4_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT4_Pos)                      /*!< GPIO_PORT PIN4: PORT4 Mask          */
+#define GPIO_PORT_PIN4_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN4: PORT5 Position      */
+#define GPIO_PORT_PIN4_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT5_Pos)                      /*!< GPIO_PORT PIN4: PORT5 Mask          */
+#define GPIO_PORT_PIN4_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN4: PORT6 Position      */
+#define GPIO_PORT_PIN4_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT6_Pos)                      /*!< GPIO_PORT PIN4: PORT6 Mask          */
+#define GPIO_PORT_PIN4_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN4: PORT7 Position      */
+#define GPIO_PORT_PIN4_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT7_Pos)                      /*!< GPIO_PORT PIN4: PORT7 Mask          */
+#define GPIO_PORT_PIN4_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN4: PORT8 Position      */
+#define GPIO_PORT_PIN4_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT8_Pos)                      /*!< GPIO_PORT PIN4: PORT8 Mask          */
+#define GPIO_PORT_PIN4_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN4: PORT9 Position      */
+#define GPIO_PORT_PIN4_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT9_Pos)                      /*!< GPIO_PORT PIN4: PORT9 Mask          */
+#define GPIO_PORT_PIN4_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN4: PORT10 Position     */
+#define GPIO_PORT_PIN4_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT10_Pos)                     /*!< GPIO_PORT PIN4: PORT10 Mask         */
+#define GPIO_PORT_PIN4_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN4: PORT11 Position     */
+#define GPIO_PORT_PIN4_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT11_Pos)                     /*!< GPIO_PORT PIN4: PORT11 Mask         */
+#define GPIO_PORT_PIN4_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN4: PORT12 Position     */
+#define GPIO_PORT_PIN4_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT12_Pos)                     /*!< GPIO_PORT PIN4: PORT12 Mask         */
+#define GPIO_PORT_PIN4_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN4: PORT13 Position     */
+#define GPIO_PORT_PIN4_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT13_Pos)                     /*!< GPIO_PORT PIN4: PORT13 Mask         */
+#define GPIO_PORT_PIN4_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN4: PORT14 Position     */
+#define GPIO_PORT_PIN4_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT14_Pos)                     /*!< GPIO_PORT PIN4: PORT14 Mask         */
+#define GPIO_PORT_PIN4_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN4: PORT15 Position     */
+#define GPIO_PORT_PIN4_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT15_Pos)                     /*!< GPIO_PORT PIN4: PORT15 Mask         */
+#define GPIO_PORT_PIN4_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN4: PORT16 Position     */
+#define GPIO_PORT_PIN4_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT16_Pos)                     /*!< GPIO_PORT PIN4: PORT16 Mask         */
+#define GPIO_PORT_PIN4_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN4: PORT17 Position     */
+#define GPIO_PORT_PIN4_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT17_Pos)                     /*!< GPIO_PORT PIN4: PORT17 Mask         */
+#define GPIO_PORT_PIN4_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN4: PORT18 Position     */
+#define GPIO_PORT_PIN4_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT18_Pos)                     /*!< GPIO_PORT PIN4: PORT18 Mask         */
+#define GPIO_PORT_PIN4_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN4: PORT19 Position     */
+#define GPIO_PORT_PIN4_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT19_Pos)                     /*!< GPIO_PORT PIN4: PORT19 Mask         */
+#define GPIO_PORT_PIN4_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN4: PORT20 Position     */
+#define GPIO_PORT_PIN4_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT20_Pos)                     /*!< GPIO_PORT PIN4: PORT20 Mask         */
+#define GPIO_PORT_PIN4_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN4: PORT21 Position     */
+#define GPIO_PORT_PIN4_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT21_Pos)                     /*!< GPIO_PORT PIN4: PORT21 Mask         */
+#define GPIO_PORT_PIN4_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN4: PORT22 Position     */
+#define GPIO_PORT_PIN4_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT22_Pos)                     /*!< GPIO_PORT PIN4: PORT22 Mask         */
+#define GPIO_PORT_PIN4_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN4: PORT23 Position     */
+#define GPIO_PORT_PIN4_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT23_Pos)                     /*!< GPIO_PORT PIN4: PORT23 Mask         */
+#define GPIO_PORT_PIN4_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN4: PORT24 Position     */
+#define GPIO_PORT_PIN4_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT24_Pos)                     /*!< GPIO_PORT PIN4: PORT24 Mask         */
+#define GPIO_PORT_PIN4_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN4: PORT25 Position     */
+#define GPIO_PORT_PIN4_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT25_Pos)                     /*!< GPIO_PORT PIN4: PORT25 Mask         */
+#define GPIO_PORT_PIN4_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN4: PORT26 Position     */
+#define GPIO_PORT_PIN4_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT26_Pos)                     /*!< GPIO_PORT PIN4: PORT26 Mask         */
+#define GPIO_PORT_PIN4_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN4: PORT27 Position     */
+#define GPIO_PORT_PIN4_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT27_Pos)                     /*!< GPIO_PORT PIN4: PORT27 Mask         */
+#define GPIO_PORT_PIN4_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN4: PORT28 Position     */
+#define GPIO_PORT_PIN4_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT28_Pos)                     /*!< GPIO_PORT PIN4: PORT28 Mask         */
+#define GPIO_PORT_PIN4_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN4: PORT29 Position     */
+#define GPIO_PORT_PIN4_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT29_Pos)                     /*!< GPIO_PORT PIN4: PORT29 Mask         */
+#define GPIO_PORT_PIN4_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN4: PORT30 Position     */
+#define GPIO_PORT_PIN4_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT30_Pos)                     /*!< GPIO_PORT PIN4: PORT30 Mask         */
+#define GPIO_PORT_PIN4_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN4: PORT31 Position     */
+#define GPIO_PORT_PIN4_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT31_Pos)                     /*!< GPIO_PORT PIN4: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN5  -----------------------------------------
+#define GPIO_PORT_PIN5_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN5: PORT0 Position      */
+#define GPIO_PORT_PIN5_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT0_Pos)                      /*!< GPIO_PORT PIN5: PORT0 Mask          */
+#define GPIO_PORT_PIN5_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN5: PORT1 Position      */
+#define GPIO_PORT_PIN5_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT1_Pos)                      /*!< GPIO_PORT PIN5: PORT1 Mask          */
+#define GPIO_PORT_PIN5_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN5: PORT2 Position      */
+#define GPIO_PORT_PIN5_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT2_Pos)                      /*!< GPIO_PORT PIN5: PORT2 Mask          */
+#define GPIO_PORT_PIN5_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN5: PORT3 Position      */
+#define GPIO_PORT_PIN5_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT3_Pos)                      /*!< GPIO_PORT PIN5: PORT3 Mask          */
+#define GPIO_PORT_PIN5_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN5: PORT4 Position      */
+#define GPIO_PORT_PIN5_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT4_Pos)                      /*!< GPIO_PORT PIN5: PORT4 Mask          */
+#define GPIO_PORT_PIN5_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN5: PORT5 Position      */
+#define GPIO_PORT_PIN5_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT5_Pos)                      /*!< GPIO_PORT PIN5: PORT5 Mask          */
+#define GPIO_PORT_PIN5_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN5: PORT6 Position      */
+#define GPIO_PORT_PIN5_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT6_Pos)                      /*!< GPIO_PORT PIN5: PORT6 Mask          */
+#define GPIO_PORT_PIN5_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN5: PORT7 Position      */
+#define GPIO_PORT_PIN5_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT7_Pos)                      /*!< GPIO_PORT PIN5: PORT7 Mask          */
+#define GPIO_PORT_PIN5_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN5: PORT8 Position      */
+#define GPIO_PORT_PIN5_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT8_Pos)                      /*!< GPIO_PORT PIN5: PORT8 Mask          */
+#define GPIO_PORT_PIN5_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN5: PORT9 Position      */
+#define GPIO_PORT_PIN5_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT9_Pos)                      /*!< GPIO_PORT PIN5: PORT9 Mask          */
+#define GPIO_PORT_PIN5_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN5: PORT10 Position     */
+#define GPIO_PORT_PIN5_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT10_Pos)                     /*!< GPIO_PORT PIN5: PORT10 Mask         */
+#define GPIO_PORT_PIN5_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN5: PORT11 Position     */
+#define GPIO_PORT_PIN5_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT11_Pos)                     /*!< GPIO_PORT PIN5: PORT11 Mask         */
+#define GPIO_PORT_PIN5_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN5: PORT12 Position     */
+#define GPIO_PORT_PIN5_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT12_Pos)                     /*!< GPIO_PORT PIN5: PORT12 Mask         */
+#define GPIO_PORT_PIN5_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN5: PORT13 Position     */
+#define GPIO_PORT_PIN5_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT13_Pos)                     /*!< GPIO_PORT PIN5: PORT13 Mask         */
+#define GPIO_PORT_PIN5_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN5: PORT14 Position     */
+#define GPIO_PORT_PIN5_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT14_Pos)                     /*!< GPIO_PORT PIN5: PORT14 Mask         */
+#define GPIO_PORT_PIN5_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN5: PORT15 Position     */
+#define GPIO_PORT_PIN5_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT15_Pos)                     /*!< GPIO_PORT PIN5: PORT15 Mask         */
+#define GPIO_PORT_PIN5_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN5: PORT16 Position     */
+#define GPIO_PORT_PIN5_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT16_Pos)                     /*!< GPIO_PORT PIN5: PORT16 Mask         */
+#define GPIO_PORT_PIN5_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN5: PORT17 Position     */
+#define GPIO_PORT_PIN5_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT17_Pos)                     /*!< GPIO_PORT PIN5: PORT17 Mask         */
+#define GPIO_PORT_PIN5_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN5: PORT18 Position     */
+#define GPIO_PORT_PIN5_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT18_Pos)                     /*!< GPIO_PORT PIN5: PORT18 Mask         */
+#define GPIO_PORT_PIN5_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN5: PORT19 Position     */
+#define GPIO_PORT_PIN5_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT19_Pos)                     /*!< GPIO_PORT PIN5: PORT19 Mask         */
+#define GPIO_PORT_PIN5_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN5: PORT20 Position     */
+#define GPIO_PORT_PIN5_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT20_Pos)                     /*!< GPIO_PORT PIN5: PORT20 Mask         */
+#define GPIO_PORT_PIN5_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN5: PORT21 Position     */
+#define GPIO_PORT_PIN5_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT21_Pos)                     /*!< GPIO_PORT PIN5: PORT21 Mask         */
+#define GPIO_PORT_PIN5_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN5: PORT22 Position     */
+#define GPIO_PORT_PIN5_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT22_Pos)                     /*!< GPIO_PORT PIN5: PORT22 Mask         */
+#define GPIO_PORT_PIN5_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN5: PORT23 Position     */
+#define GPIO_PORT_PIN5_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT23_Pos)                     /*!< GPIO_PORT PIN5: PORT23 Mask         */
+#define GPIO_PORT_PIN5_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN5: PORT24 Position     */
+#define GPIO_PORT_PIN5_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT24_Pos)                     /*!< GPIO_PORT PIN5: PORT24 Mask         */
+#define GPIO_PORT_PIN5_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN5: PORT25 Position     */
+#define GPIO_PORT_PIN5_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT25_Pos)                     /*!< GPIO_PORT PIN5: PORT25 Mask         */
+#define GPIO_PORT_PIN5_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN5: PORT26 Position     */
+#define GPIO_PORT_PIN5_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT26_Pos)                     /*!< GPIO_PORT PIN5: PORT26 Mask         */
+#define GPIO_PORT_PIN5_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN5: PORT27 Position     */
+#define GPIO_PORT_PIN5_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT27_Pos)                     /*!< GPIO_PORT PIN5: PORT27 Mask         */
+#define GPIO_PORT_PIN5_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN5: PORT28 Position     */
+#define GPIO_PORT_PIN5_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT28_Pos)                     /*!< GPIO_PORT PIN5: PORT28 Mask         */
+#define GPIO_PORT_PIN5_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN5: PORT29 Position     */
+#define GPIO_PORT_PIN5_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT29_Pos)                     /*!< GPIO_PORT PIN5: PORT29 Mask         */
+#define GPIO_PORT_PIN5_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN5: PORT30 Position     */
+#define GPIO_PORT_PIN5_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT30_Pos)                     /*!< GPIO_PORT PIN5: PORT30 Mask         */
+#define GPIO_PORT_PIN5_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN5: PORT31 Position     */
+#define GPIO_PORT_PIN5_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT31_Pos)                     /*!< GPIO_PORT PIN5: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN6  -----------------------------------------
+#define GPIO_PORT_PIN6_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN6: PORT0 Position      */
+#define GPIO_PORT_PIN6_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT0_Pos)                      /*!< GPIO_PORT PIN6: PORT0 Mask          */
+#define GPIO_PORT_PIN6_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN6: PORT1 Position      */
+#define GPIO_PORT_PIN6_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT1_Pos)                      /*!< GPIO_PORT PIN6: PORT1 Mask          */
+#define GPIO_PORT_PIN6_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN6: PORT2 Position      */
+#define GPIO_PORT_PIN6_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT2_Pos)                      /*!< GPIO_PORT PIN6: PORT2 Mask          */
+#define GPIO_PORT_PIN6_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN6: PORT3 Position      */
+#define GPIO_PORT_PIN6_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT3_Pos)                      /*!< GPIO_PORT PIN6: PORT3 Mask          */
+#define GPIO_PORT_PIN6_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN6: PORT4 Position      */
+#define GPIO_PORT_PIN6_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT4_Pos)                      /*!< GPIO_PORT PIN6: PORT4 Mask          */
+#define GPIO_PORT_PIN6_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN6: PORT5 Position      */
+#define GPIO_PORT_PIN6_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT5_Pos)                      /*!< GPIO_PORT PIN6: PORT5 Mask          */
+#define GPIO_PORT_PIN6_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN6: PORT6 Position      */
+#define GPIO_PORT_PIN6_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT6_Pos)                      /*!< GPIO_PORT PIN6: PORT6 Mask          */
+#define GPIO_PORT_PIN6_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN6: PORT7 Position      */
+#define GPIO_PORT_PIN6_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT7_Pos)                      /*!< GPIO_PORT PIN6: PORT7 Mask          */
+#define GPIO_PORT_PIN6_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN6: PORT8 Position      */
+#define GPIO_PORT_PIN6_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT8_Pos)                      /*!< GPIO_PORT PIN6: PORT8 Mask          */
+#define GPIO_PORT_PIN6_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN6: PORT9 Position      */
+#define GPIO_PORT_PIN6_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT9_Pos)                      /*!< GPIO_PORT PIN6: PORT9 Mask          */
+#define GPIO_PORT_PIN6_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN6: PORT10 Position     */
+#define GPIO_PORT_PIN6_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT10_Pos)                     /*!< GPIO_PORT PIN6: PORT10 Mask         */
+#define GPIO_PORT_PIN6_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN6: PORT11 Position     */
+#define GPIO_PORT_PIN6_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT11_Pos)                     /*!< GPIO_PORT PIN6: PORT11 Mask         */
+#define GPIO_PORT_PIN6_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN6: PORT12 Position     */
+#define GPIO_PORT_PIN6_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT12_Pos)                     /*!< GPIO_PORT PIN6: PORT12 Mask         */
+#define GPIO_PORT_PIN6_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN6: PORT13 Position     */
+#define GPIO_PORT_PIN6_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT13_Pos)                     /*!< GPIO_PORT PIN6: PORT13 Mask         */
+#define GPIO_PORT_PIN6_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN6: PORT14 Position     */
+#define GPIO_PORT_PIN6_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT14_Pos)                     /*!< GPIO_PORT PIN6: PORT14 Mask         */
+#define GPIO_PORT_PIN6_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN6: PORT15 Position     */
+#define GPIO_PORT_PIN6_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT15_Pos)                     /*!< GPIO_PORT PIN6: PORT15 Mask         */
+#define GPIO_PORT_PIN6_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN6: PORT16 Position     */
+#define GPIO_PORT_PIN6_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT16_Pos)                     /*!< GPIO_PORT PIN6: PORT16 Mask         */
+#define GPIO_PORT_PIN6_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN6: PORT17 Position     */
+#define GPIO_PORT_PIN6_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT17_Pos)                     /*!< GPIO_PORT PIN6: PORT17 Mask         */
+#define GPIO_PORT_PIN6_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN6: PORT18 Position     */
+#define GPIO_PORT_PIN6_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT18_Pos)                     /*!< GPIO_PORT PIN6: PORT18 Mask         */
+#define GPIO_PORT_PIN6_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN6: PORT19 Position     */
+#define GPIO_PORT_PIN6_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT19_Pos)                     /*!< GPIO_PORT PIN6: PORT19 Mask         */
+#define GPIO_PORT_PIN6_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN6: PORT20 Position     */
+#define GPIO_PORT_PIN6_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT20_Pos)                     /*!< GPIO_PORT PIN6: PORT20 Mask         */
+#define GPIO_PORT_PIN6_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN6: PORT21 Position     */
+#define GPIO_PORT_PIN6_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT21_Pos)                     /*!< GPIO_PORT PIN6: PORT21 Mask         */
+#define GPIO_PORT_PIN6_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN6: PORT22 Position     */
+#define GPIO_PORT_PIN6_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT22_Pos)                     /*!< GPIO_PORT PIN6: PORT22 Mask         */
+#define GPIO_PORT_PIN6_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN6: PORT23 Position     */
+#define GPIO_PORT_PIN6_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT23_Pos)                     /*!< GPIO_PORT PIN6: PORT23 Mask         */
+#define GPIO_PORT_PIN6_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN6: PORT24 Position     */
+#define GPIO_PORT_PIN6_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT24_Pos)                     /*!< GPIO_PORT PIN6: PORT24 Mask         */
+#define GPIO_PORT_PIN6_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN6: PORT25 Position     */
+#define GPIO_PORT_PIN6_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT25_Pos)                     /*!< GPIO_PORT PIN6: PORT25 Mask         */
+#define GPIO_PORT_PIN6_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN6: PORT26 Position     */
+#define GPIO_PORT_PIN6_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT26_Pos)                     /*!< GPIO_PORT PIN6: PORT26 Mask         */
+#define GPIO_PORT_PIN6_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN6: PORT27 Position     */
+#define GPIO_PORT_PIN6_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT27_Pos)                     /*!< GPIO_PORT PIN6: PORT27 Mask         */
+#define GPIO_PORT_PIN6_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN6: PORT28 Position     */
+#define GPIO_PORT_PIN6_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT28_Pos)                     /*!< GPIO_PORT PIN6: PORT28 Mask         */
+#define GPIO_PORT_PIN6_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN6: PORT29 Position     */
+#define GPIO_PORT_PIN6_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT29_Pos)                     /*!< GPIO_PORT PIN6: PORT29 Mask         */
+#define GPIO_PORT_PIN6_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN6: PORT30 Position     */
+#define GPIO_PORT_PIN6_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT30_Pos)                     /*!< GPIO_PORT PIN6: PORT30 Mask         */
+#define GPIO_PORT_PIN6_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN6: PORT31 Position     */
+#define GPIO_PORT_PIN6_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT31_Pos)                     /*!< GPIO_PORT PIN6: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN7  -----------------------------------------
+#define GPIO_PORT_PIN7_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN7: PORT0 Position      */
+#define GPIO_PORT_PIN7_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT0_Pos)                      /*!< GPIO_PORT PIN7: PORT0 Mask          */
+#define GPIO_PORT_PIN7_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN7: PORT1 Position      */
+#define GPIO_PORT_PIN7_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT1_Pos)                      /*!< GPIO_PORT PIN7: PORT1 Mask          */
+#define GPIO_PORT_PIN7_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN7: PORT2 Position      */
+#define GPIO_PORT_PIN7_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT2_Pos)                      /*!< GPIO_PORT PIN7: PORT2 Mask          */
+#define GPIO_PORT_PIN7_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN7: PORT3 Position      */
+#define GPIO_PORT_PIN7_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT3_Pos)                      /*!< GPIO_PORT PIN7: PORT3 Mask          */
+#define GPIO_PORT_PIN7_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN7: PORT4 Position      */
+#define GPIO_PORT_PIN7_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT4_Pos)                      /*!< GPIO_PORT PIN7: PORT4 Mask          */
+#define GPIO_PORT_PIN7_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN7: PORT5 Position      */
+#define GPIO_PORT_PIN7_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT5_Pos)                      /*!< GPIO_PORT PIN7: PORT5 Mask          */
+#define GPIO_PORT_PIN7_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN7: PORT6 Position      */
+#define GPIO_PORT_PIN7_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT6_Pos)                      /*!< GPIO_PORT PIN7: PORT6 Mask          */
+#define GPIO_PORT_PIN7_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN7: PORT7 Position      */
+#define GPIO_PORT_PIN7_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT7_Pos)                      /*!< GPIO_PORT PIN7: PORT7 Mask          */
+#define GPIO_PORT_PIN7_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN7: PORT8 Position      */
+#define GPIO_PORT_PIN7_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT8_Pos)                      /*!< GPIO_PORT PIN7: PORT8 Mask          */
+#define GPIO_PORT_PIN7_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN7: PORT9 Position      */
+#define GPIO_PORT_PIN7_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT9_Pos)                      /*!< GPIO_PORT PIN7: PORT9 Mask          */
+#define GPIO_PORT_PIN7_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN7: PORT10 Position     */
+#define GPIO_PORT_PIN7_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT10_Pos)                     /*!< GPIO_PORT PIN7: PORT10 Mask         */
+#define GPIO_PORT_PIN7_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN7: PORT11 Position     */
+#define GPIO_PORT_PIN7_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT11_Pos)                     /*!< GPIO_PORT PIN7: PORT11 Mask         */
+#define GPIO_PORT_PIN7_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN7: PORT12 Position     */
+#define GPIO_PORT_PIN7_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT12_Pos)                     /*!< GPIO_PORT PIN7: PORT12 Mask         */
+#define GPIO_PORT_PIN7_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN7: PORT13 Position     */
+#define GPIO_PORT_PIN7_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT13_Pos)                     /*!< GPIO_PORT PIN7: PORT13 Mask         */
+#define GPIO_PORT_PIN7_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN7: PORT14 Position     */
+#define GPIO_PORT_PIN7_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT14_Pos)                     /*!< GPIO_PORT PIN7: PORT14 Mask         */
+#define GPIO_PORT_PIN7_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN7: PORT15 Position     */
+#define GPIO_PORT_PIN7_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT15_Pos)                     /*!< GPIO_PORT PIN7: PORT15 Mask         */
+#define GPIO_PORT_PIN7_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN7: PORT16 Position     */
+#define GPIO_PORT_PIN7_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT16_Pos)                     /*!< GPIO_PORT PIN7: PORT16 Mask         */
+#define GPIO_PORT_PIN7_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN7: PORT17 Position     */
+#define GPIO_PORT_PIN7_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT17_Pos)                     /*!< GPIO_PORT PIN7: PORT17 Mask         */
+#define GPIO_PORT_PIN7_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN7: PORT18 Position     */
+#define GPIO_PORT_PIN7_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT18_Pos)                     /*!< GPIO_PORT PIN7: PORT18 Mask         */
+#define GPIO_PORT_PIN7_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN7: PORT19 Position     */
+#define GPIO_PORT_PIN7_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT19_Pos)                     /*!< GPIO_PORT PIN7: PORT19 Mask         */
+#define GPIO_PORT_PIN7_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN7: PORT20 Position     */
+#define GPIO_PORT_PIN7_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT20_Pos)                     /*!< GPIO_PORT PIN7: PORT20 Mask         */
+#define GPIO_PORT_PIN7_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN7: PORT21 Position     */
+#define GPIO_PORT_PIN7_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT21_Pos)                     /*!< GPIO_PORT PIN7: PORT21 Mask         */
+#define GPIO_PORT_PIN7_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN7: PORT22 Position     */
+#define GPIO_PORT_PIN7_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT22_Pos)                     /*!< GPIO_PORT PIN7: PORT22 Mask         */
+#define GPIO_PORT_PIN7_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN7: PORT23 Position     */
+#define GPIO_PORT_PIN7_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT23_Pos)                     /*!< GPIO_PORT PIN7: PORT23 Mask         */
+#define GPIO_PORT_PIN7_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN7: PORT24 Position     */
+#define GPIO_PORT_PIN7_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT24_Pos)                     /*!< GPIO_PORT PIN7: PORT24 Mask         */
+#define GPIO_PORT_PIN7_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN7: PORT25 Position     */
+#define GPIO_PORT_PIN7_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT25_Pos)                     /*!< GPIO_PORT PIN7: PORT25 Mask         */
+#define GPIO_PORT_PIN7_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN7: PORT26 Position     */
+#define GPIO_PORT_PIN7_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT26_Pos)                     /*!< GPIO_PORT PIN7: PORT26 Mask         */
+#define GPIO_PORT_PIN7_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN7: PORT27 Position     */
+#define GPIO_PORT_PIN7_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT27_Pos)                     /*!< GPIO_PORT PIN7: PORT27 Mask         */
+#define GPIO_PORT_PIN7_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN7: PORT28 Position     */
+#define GPIO_PORT_PIN7_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT28_Pos)                     /*!< GPIO_PORT PIN7: PORT28 Mask         */
+#define GPIO_PORT_PIN7_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN7: PORT29 Position     */
+#define GPIO_PORT_PIN7_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT29_Pos)                     /*!< GPIO_PORT PIN7: PORT29 Mask         */
+#define GPIO_PORT_PIN7_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN7: PORT30 Position     */
+#define GPIO_PORT_PIN7_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT30_Pos)                     /*!< GPIO_PORT PIN7: PORT30 Mask         */
+#define GPIO_PORT_PIN7_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN7: PORT31 Position     */
+#define GPIO_PORT_PIN7_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT31_Pos)                     /*!< GPIO_PORT PIN7: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_MPIN0  ----------------------------------------
+#define GPIO_PORT_MPIN0_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN0: MPORTP0 Position   */
+#define GPIO_PORT_MPIN0_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN0: MPORTP1 Position   */
+#define GPIO_PORT_MPIN0_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN0: MPORTP2 Position   */
+#define GPIO_PORT_MPIN0_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN0: MPORTP3 Position   */
+#define GPIO_PORT_MPIN0_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN0: MPORTP4 Position   */
+#define GPIO_PORT_MPIN0_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN0: MPORTP5 Position   */
+#define GPIO_PORT_MPIN0_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN0: MPORTP6 Position   */
+#define GPIO_PORT_MPIN0_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN0: MPORTP7 Position   */
+#define GPIO_PORT_MPIN0_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN0: MPORTP8 Position   */
+#define GPIO_PORT_MPIN0_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN0: MPORTP9 Position   */
+#define GPIO_PORT_MPIN0_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN0: MPORTP10 Position  */
+#define GPIO_PORT_MPIN0_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN0: MPORTP11 Position  */
+#define GPIO_PORT_MPIN0_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN0: MPORTP12 Position  */
+#define GPIO_PORT_MPIN0_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN0: MPORTP13 Position  */
+#define GPIO_PORT_MPIN0_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN0: MPORTP14 Position  */
+#define GPIO_PORT_MPIN0_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN0: MPORTP15 Position  */
+#define GPIO_PORT_MPIN0_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN0: MPORTP16 Position  */
+#define GPIO_PORT_MPIN0_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN0: MPORTP17 Position  */
+#define GPIO_PORT_MPIN0_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN0: MPORTP18 Position  */
+#define GPIO_PORT_MPIN0_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN0: MPORTP19 Position  */
+#define GPIO_PORT_MPIN0_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN0: MPORTP20 Position  */
+#define GPIO_PORT_MPIN0_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN0: MPORTP21 Position  */
+#define GPIO_PORT_MPIN0_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN0: MPORTP22 Position  */
+#define GPIO_PORT_MPIN0_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN0: MPORTP23 Position  */
+#define GPIO_PORT_MPIN0_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN0: MPORTP24 Position  */
+#define GPIO_PORT_MPIN0_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN0: MPORTP25 Position  */
+#define GPIO_PORT_MPIN0_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN0: MPORTP26 Position  */
+#define GPIO_PORT_MPIN0_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN0: MPORTP27 Position  */
+#define GPIO_PORT_MPIN0_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN0: MPORTP28 Position  */
+#define GPIO_PORT_MPIN0_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN0: MPORTP29 Position  */
+#define GPIO_PORT_MPIN0_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN0: MPORTP30 Position  */
+#define GPIO_PORT_MPIN0_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN0: MPORTP31 Position  */
+#define GPIO_PORT_MPIN0_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN1  ----------------------------------------
+#define GPIO_PORT_MPIN1_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN1: MPORTP0 Position   */
+#define GPIO_PORT_MPIN1_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN1: MPORTP1 Position   */
+#define GPIO_PORT_MPIN1_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN1: MPORTP2 Position   */
+#define GPIO_PORT_MPIN1_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN1: MPORTP3 Position   */
+#define GPIO_PORT_MPIN1_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN1: MPORTP4 Position   */
+#define GPIO_PORT_MPIN1_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN1: MPORTP5 Position   */
+#define GPIO_PORT_MPIN1_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN1: MPORTP6 Position   */
+#define GPIO_PORT_MPIN1_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN1: MPORTP7 Position   */
+#define GPIO_PORT_MPIN1_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN1: MPORTP8 Position   */
+#define GPIO_PORT_MPIN1_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN1: MPORTP9 Position   */
+#define GPIO_PORT_MPIN1_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN1: MPORTP10 Position  */
+#define GPIO_PORT_MPIN1_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN1: MPORTP11 Position  */
+#define GPIO_PORT_MPIN1_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN1: MPORTP12 Position  */
+#define GPIO_PORT_MPIN1_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN1: MPORTP13 Position  */
+#define GPIO_PORT_MPIN1_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN1: MPORTP14 Position  */
+#define GPIO_PORT_MPIN1_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN1: MPORTP15 Position  */
+#define GPIO_PORT_MPIN1_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN1: MPORTP16 Position  */
+#define GPIO_PORT_MPIN1_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN1: MPORTP17 Position  */
+#define GPIO_PORT_MPIN1_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN1: MPORTP18 Position  */
+#define GPIO_PORT_MPIN1_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN1: MPORTP19 Position  */
+#define GPIO_PORT_MPIN1_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN1: MPORTP20 Position  */
+#define GPIO_PORT_MPIN1_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN1: MPORTP21 Position  */
+#define GPIO_PORT_MPIN1_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN1: MPORTP22 Position  */
+#define GPIO_PORT_MPIN1_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN1: MPORTP23 Position  */
+#define GPIO_PORT_MPIN1_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN1: MPORTP24 Position  */
+#define GPIO_PORT_MPIN1_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN1: MPORTP25 Position  */
+#define GPIO_PORT_MPIN1_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN1: MPORTP26 Position  */
+#define GPIO_PORT_MPIN1_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN1: MPORTP27 Position  */
+#define GPIO_PORT_MPIN1_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN1: MPORTP28 Position  */
+#define GPIO_PORT_MPIN1_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN1: MPORTP29 Position  */
+#define GPIO_PORT_MPIN1_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN1: MPORTP30 Position  */
+#define GPIO_PORT_MPIN1_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN1: MPORTP31 Position  */
+#define GPIO_PORT_MPIN1_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN2  ----------------------------------------
+#define GPIO_PORT_MPIN2_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN2: MPORTP0 Position   */
+#define GPIO_PORT_MPIN2_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN2: MPORTP1 Position   */
+#define GPIO_PORT_MPIN2_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN2: MPORTP2 Position   */
+#define GPIO_PORT_MPIN2_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN2: MPORTP3 Position   */
+#define GPIO_PORT_MPIN2_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN2: MPORTP4 Position   */
+#define GPIO_PORT_MPIN2_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN2: MPORTP5 Position   */
+#define GPIO_PORT_MPIN2_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN2: MPORTP6 Position   */
+#define GPIO_PORT_MPIN2_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN2: MPORTP7 Position   */
+#define GPIO_PORT_MPIN2_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN2: MPORTP8 Position   */
+#define GPIO_PORT_MPIN2_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN2: MPORTP9 Position   */
+#define GPIO_PORT_MPIN2_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN2: MPORTP10 Position  */
+#define GPIO_PORT_MPIN2_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN2: MPORTP11 Position  */
+#define GPIO_PORT_MPIN2_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN2: MPORTP12 Position  */
+#define GPIO_PORT_MPIN2_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN2: MPORTP13 Position  */
+#define GPIO_PORT_MPIN2_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN2: MPORTP14 Position  */
+#define GPIO_PORT_MPIN2_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN2: MPORTP15 Position  */
+#define GPIO_PORT_MPIN2_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN2: MPORTP16 Position  */
+#define GPIO_PORT_MPIN2_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN2: MPORTP17 Position  */
+#define GPIO_PORT_MPIN2_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN2: MPORTP18 Position  */
+#define GPIO_PORT_MPIN2_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN2: MPORTP19 Position  */
+#define GPIO_PORT_MPIN2_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN2: MPORTP20 Position  */
+#define GPIO_PORT_MPIN2_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN2: MPORTP21 Position  */
+#define GPIO_PORT_MPIN2_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN2: MPORTP22 Position  */
+#define GPIO_PORT_MPIN2_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN2: MPORTP23 Position  */
+#define GPIO_PORT_MPIN2_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN2: MPORTP24 Position  */
+#define GPIO_PORT_MPIN2_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN2: MPORTP25 Position  */
+#define GPIO_PORT_MPIN2_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN2: MPORTP26 Position  */
+#define GPIO_PORT_MPIN2_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN2: MPORTP27 Position  */
+#define GPIO_PORT_MPIN2_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN2: MPORTP28 Position  */
+#define GPIO_PORT_MPIN2_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN2: MPORTP29 Position  */
+#define GPIO_PORT_MPIN2_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN2: MPORTP30 Position  */
+#define GPIO_PORT_MPIN2_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN2: MPORTP31 Position  */
+#define GPIO_PORT_MPIN2_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN3  ----------------------------------------
+#define GPIO_PORT_MPIN3_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN3: MPORTP0 Position   */
+#define GPIO_PORT_MPIN3_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN3: MPORTP1 Position   */
+#define GPIO_PORT_MPIN3_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN3: MPORTP2 Position   */
+#define GPIO_PORT_MPIN3_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN3: MPORTP3 Position   */
+#define GPIO_PORT_MPIN3_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN3: MPORTP4 Position   */
+#define GPIO_PORT_MPIN3_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN3: MPORTP5 Position   */
+#define GPIO_PORT_MPIN3_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN3: MPORTP6 Position   */
+#define GPIO_PORT_MPIN3_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN3: MPORTP7 Position   */
+#define GPIO_PORT_MPIN3_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN3: MPORTP8 Position   */
+#define GPIO_PORT_MPIN3_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN3: MPORTP9 Position   */
+#define GPIO_PORT_MPIN3_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN3: MPORTP10 Position  */
+#define GPIO_PORT_MPIN3_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN3: MPORTP11 Position  */
+#define GPIO_PORT_MPIN3_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN3: MPORTP12 Position  */
+#define GPIO_PORT_MPIN3_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN3: MPORTP13 Position  */
+#define GPIO_PORT_MPIN3_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN3: MPORTP14 Position  */
+#define GPIO_PORT_MPIN3_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN3: MPORTP15 Position  */
+#define GPIO_PORT_MPIN3_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN3: MPORTP16 Position  */
+#define GPIO_PORT_MPIN3_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN3: MPORTP17 Position  */
+#define GPIO_PORT_MPIN3_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN3: MPORTP18 Position  */
+#define GPIO_PORT_MPIN3_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN3: MPORTP19 Position  */
+#define GPIO_PORT_MPIN3_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN3: MPORTP20 Position  */
+#define GPIO_PORT_MPIN3_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN3: MPORTP21 Position  */
+#define GPIO_PORT_MPIN3_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN3: MPORTP22 Position  */
+#define GPIO_PORT_MPIN3_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN3: MPORTP23 Position  */
+#define GPIO_PORT_MPIN3_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN3: MPORTP24 Position  */
+#define GPIO_PORT_MPIN3_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN3: MPORTP25 Position  */
+#define GPIO_PORT_MPIN3_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN3: MPORTP26 Position  */
+#define GPIO_PORT_MPIN3_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN3: MPORTP27 Position  */
+#define GPIO_PORT_MPIN3_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN3: MPORTP28 Position  */
+#define GPIO_PORT_MPIN3_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN3: MPORTP29 Position  */
+#define GPIO_PORT_MPIN3_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN3: MPORTP30 Position  */
+#define GPIO_PORT_MPIN3_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN3: MPORTP31 Position  */
+#define GPIO_PORT_MPIN3_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN4  ----------------------------------------
+#define GPIO_PORT_MPIN4_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN4: MPORTP0 Position   */
+#define GPIO_PORT_MPIN4_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN4: MPORTP1 Position   */
+#define GPIO_PORT_MPIN4_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN4: MPORTP2 Position   */
+#define GPIO_PORT_MPIN4_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN4: MPORTP3 Position   */
+#define GPIO_PORT_MPIN4_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN4: MPORTP4 Position   */
+#define GPIO_PORT_MPIN4_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN4: MPORTP5 Position   */
+#define GPIO_PORT_MPIN4_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN4: MPORTP6 Position   */
+#define GPIO_PORT_MPIN4_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN4: MPORTP7 Position   */
+#define GPIO_PORT_MPIN4_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN4: MPORTP8 Position   */
+#define GPIO_PORT_MPIN4_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN4: MPORTP9 Position   */
+#define GPIO_PORT_MPIN4_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN4: MPORTP10 Position  */
+#define GPIO_PORT_MPIN4_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN4: MPORTP11 Position  */
+#define GPIO_PORT_MPIN4_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN4: MPORTP12 Position  */
+#define GPIO_PORT_MPIN4_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN4: MPORTP13 Position  */
+#define GPIO_PORT_MPIN4_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN4: MPORTP14 Position  */
+#define GPIO_PORT_MPIN4_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN4: MPORTP15 Position  */
+#define GPIO_PORT_MPIN4_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN4: MPORTP16 Position  */
+#define GPIO_PORT_MPIN4_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN4: MPORTP17 Position  */
+#define GPIO_PORT_MPIN4_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN4: MPORTP18 Position  */
+#define GPIO_PORT_MPIN4_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN4: MPORTP19 Position  */
+#define GPIO_PORT_MPIN4_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN4: MPORTP20 Position  */
+#define GPIO_PORT_MPIN4_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN4: MPORTP21 Position  */
+#define GPIO_PORT_MPIN4_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN4: MPORTP22 Position  */
+#define GPIO_PORT_MPIN4_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN4: MPORTP23 Position  */
+#define GPIO_PORT_MPIN4_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN4: MPORTP24 Position  */
+#define GPIO_PORT_MPIN4_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN4: MPORTP25 Position  */
+#define GPIO_PORT_MPIN4_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN4: MPORTP26 Position  */
+#define GPIO_PORT_MPIN4_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN4: MPORTP27 Position  */
+#define GPIO_PORT_MPIN4_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN4: MPORTP28 Position  */
+#define GPIO_PORT_MPIN4_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN4: MPORTP29 Position  */
+#define GPIO_PORT_MPIN4_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN4: MPORTP30 Position  */
+#define GPIO_PORT_MPIN4_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN4: MPORTP31 Position  */
+#define GPIO_PORT_MPIN4_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN5  ----------------------------------------
+#define GPIO_PORT_MPIN5_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN5: MPORTP0 Position   */
+#define GPIO_PORT_MPIN5_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN5: MPORTP1 Position   */
+#define GPIO_PORT_MPIN5_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN5: MPORTP2 Position   */
+#define GPIO_PORT_MPIN5_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN5: MPORTP3 Position   */
+#define GPIO_PORT_MPIN5_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN5: MPORTP4 Position   */
+#define GPIO_PORT_MPIN5_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN5: MPORTP5 Position   */
+#define GPIO_PORT_MPIN5_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN5: MPORTP6 Position   */
+#define GPIO_PORT_MPIN5_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN5: MPORTP7 Position   */
+#define GPIO_PORT_MPIN5_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN5: MPORTP8 Position   */
+#define GPIO_PORT_MPIN5_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN5: MPORTP9 Position   */
+#define GPIO_PORT_MPIN5_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN5: MPORTP10 Position  */
+#define GPIO_PORT_MPIN5_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN5: MPORTP11 Position  */
+#define GPIO_PORT_MPIN5_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN5: MPORTP12 Position  */
+#define GPIO_PORT_MPIN5_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN5: MPORTP13 Position  */
+#define GPIO_PORT_MPIN5_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN5: MPORTP14 Position  */
+#define GPIO_PORT_MPIN5_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN5: MPORTP15 Position  */
+#define GPIO_PORT_MPIN5_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN5: MPORTP16 Position  */
+#define GPIO_PORT_MPIN5_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN5: MPORTP17 Position  */
+#define GPIO_PORT_MPIN5_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN5: MPORTP18 Position  */
+#define GPIO_PORT_MPIN5_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN5: MPORTP19 Position  */
+#define GPIO_PORT_MPIN5_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN5: MPORTP20 Position  */
+#define GPIO_PORT_MPIN5_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN5: MPORTP21 Position  */
+#define GPIO_PORT_MPIN5_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN5: MPORTP22 Position  */
+#define GPIO_PORT_MPIN5_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN5: MPORTP23 Position  */
+#define GPIO_PORT_MPIN5_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN5: MPORTP24 Position  */
+#define GPIO_PORT_MPIN5_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN5: MPORTP25 Position  */
+#define GPIO_PORT_MPIN5_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN5: MPORTP26 Position  */
+#define GPIO_PORT_MPIN5_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN5: MPORTP27 Position  */
+#define GPIO_PORT_MPIN5_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN5: MPORTP28 Position  */
+#define GPIO_PORT_MPIN5_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN5: MPORTP29 Position  */
+#define GPIO_PORT_MPIN5_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN5: MPORTP30 Position  */
+#define GPIO_PORT_MPIN5_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN5: MPORTP31 Position  */
+#define GPIO_PORT_MPIN5_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN6  ----------------------------------------
+#define GPIO_PORT_MPIN6_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN6: MPORTP0 Position   */
+#define GPIO_PORT_MPIN6_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN6: MPORTP1 Position   */
+#define GPIO_PORT_MPIN6_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN6: MPORTP2 Position   */
+#define GPIO_PORT_MPIN6_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN6: MPORTP3 Position   */
+#define GPIO_PORT_MPIN6_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN6: MPORTP4 Position   */
+#define GPIO_PORT_MPIN6_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN6: MPORTP5 Position   */
+#define GPIO_PORT_MPIN6_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN6: MPORTP6 Position   */
+#define GPIO_PORT_MPIN6_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN6: MPORTP7 Position   */
+#define GPIO_PORT_MPIN6_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN6: MPORTP8 Position   */
+#define GPIO_PORT_MPIN6_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN6: MPORTP9 Position   */
+#define GPIO_PORT_MPIN6_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN6: MPORTP10 Position  */
+#define GPIO_PORT_MPIN6_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN6: MPORTP11 Position  */
+#define GPIO_PORT_MPIN6_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN6: MPORTP12 Position  */
+#define GPIO_PORT_MPIN6_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN6: MPORTP13 Position  */
+#define GPIO_PORT_MPIN6_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN6: MPORTP14 Position  */
+#define GPIO_PORT_MPIN6_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN6: MPORTP15 Position  */
+#define GPIO_PORT_MPIN6_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN6: MPORTP16 Position  */
+#define GPIO_PORT_MPIN6_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN6: MPORTP17 Position  */
+#define GPIO_PORT_MPIN6_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN6: MPORTP18 Position  */
+#define GPIO_PORT_MPIN6_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN6: MPORTP19 Position  */
+#define GPIO_PORT_MPIN6_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN6: MPORTP20 Position  */
+#define GPIO_PORT_MPIN6_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN6: MPORTP21 Position  */
+#define GPIO_PORT_MPIN6_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN6: MPORTP22 Position  */
+#define GPIO_PORT_MPIN6_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN6: MPORTP23 Position  */
+#define GPIO_PORT_MPIN6_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN6: MPORTP24 Position  */
+#define GPIO_PORT_MPIN6_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN6: MPORTP25 Position  */
+#define GPIO_PORT_MPIN6_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN6: MPORTP26 Position  */
+#define GPIO_PORT_MPIN6_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN6: MPORTP27 Position  */
+#define GPIO_PORT_MPIN6_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN6: MPORTP28 Position  */
+#define GPIO_PORT_MPIN6_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN6: MPORTP29 Position  */
+#define GPIO_PORT_MPIN6_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN6: MPORTP30 Position  */
+#define GPIO_PORT_MPIN6_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN6: MPORTP31 Position  */
+#define GPIO_PORT_MPIN6_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN7  ----------------------------------------
+#define GPIO_PORT_MPIN7_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN7: MPORTP0 Position   */
+#define GPIO_PORT_MPIN7_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN7: MPORTP1 Position   */
+#define GPIO_PORT_MPIN7_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN7: MPORTP2 Position   */
+#define GPIO_PORT_MPIN7_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN7: MPORTP3 Position   */
+#define GPIO_PORT_MPIN7_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN7: MPORTP4 Position   */
+#define GPIO_PORT_MPIN7_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN7: MPORTP5 Position   */
+#define GPIO_PORT_MPIN7_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN7: MPORTP6 Position   */
+#define GPIO_PORT_MPIN7_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN7: MPORTP7 Position   */
+#define GPIO_PORT_MPIN7_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN7: MPORTP8 Position   */
+#define GPIO_PORT_MPIN7_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN7: MPORTP9 Position   */
+#define GPIO_PORT_MPIN7_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN7: MPORTP10 Position  */
+#define GPIO_PORT_MPIN7_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN7: MPORTP11 Position  */
+#define GPIO_PORT_MPIN7_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN7: MPORTP12 Position  */
+#define GPIO_PORT_MPIN7_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN7: MPORTP13 Position  */
+#define GPIO_PORT_MPIN7_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN7: MPORTP14 Position  */
+#define GPIO_PORT_MPIN7_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN7: MPORTP15 Position  */
+#define GPIO_PORT_MPIN7_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN7: MPORTP16 Position  */
+#define GPIO_PORT_MPIN7_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN7: MPORTP17 Position  */
+#define GPIO_PORT_MPIN7_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN7: MPORTP18 Position  */
+#define GPIO_PORT_MPIN7_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN7: MPORTP19 Position  */
+#define GPIO_PORT_MPIN7_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN7: MPORTP20 Position  */
+#define GPIO_PORT_MPIN7_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN7: MPORTP21 Position  */
+#define GPIO_PORT_MPIN7_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN7: MPORTP22 Position  */
+#define GPIO_PORT_MPIN7_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN7: MPORTP23 Position  */
+#define GPIO_PORT_MPIN7_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN7: MPORTP24 Position  */
+#define GPIO_PORT_MPIN7_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN7: MPORTP25 Position  */
+#define GPIO_PORT_MPIN7_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN7: MPORTP26 Position  */
+#define GPIO_PORT_MPIN7_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN7: MPORTP27 Position  */
+#define GPIO_PORT_MPIN7_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN7: MPORTP28 Position  */
+#define GPIO_PORT_MPIN7_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN7: MPORTP29 Position  */
+#define GPIO_PORT_MPIN7_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN7: MPORTP30 Position  */
+#define GPIO_PORT_MPIN7_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN7: MPORTP31 Position  */
+#define GPIO_PORT_MPIN7_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_SET0  -----------------------------------------
+#define GPIO_PORT_SET0_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET0: SETP0 Position      */
+#define GPIO_PORT_SET0_SETP0_Msk                              (0x01UL << GPIO_PORT_SET0_SETP0_Pos)                      /*!< GPIO_PORT SET0: SETP0 Mask          */
+#define GPIO_PORT_SET0_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET0: SETP1 Position      */
+#define GPIO_PORT_SET0_SETP1_Msk                              (0x01UL << GPIO_PORT_SET0_SETP1_Pos)                      /*!< GPIO_PORT SET0: SETP1 Mask          */
+#define GPIO_PORT_SET0_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET0: SETP2 Position      */
+#define GPIO_PORT_SET0_SETP2_Msk                              (0x01UL << GPIO_PORT_SET0_SETP2_Pos)                      /*!< GPIO_PORT SET0: SETP2 Mask          */
+#define GPIO_PORT_SET0_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET0: SETP3 Position      */
+#define GPIO_PORT_SET0_SETP3_Msk                              (0x01UL << GPIO_PORT_SET0_SETP3_Pos)                      /*!< GPIO_PORT SET0: SETP3 Mask          */
+#define GPIO_PORT_SET0_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET0: SETP4 Position      */
+#define GPIO_PORT_SET0_SETP4_Msk                              (0x01UL << GPIO_PORT_SET0_SETP4_Pos)                      /*!< GPIO_PORT SET0: SETP4 Mask          */
+#define GPIO_PORT_SET0_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET0: SETP5 Position      */
+#define GPIO_PORT_SET0_SETP5_Msk                              (0x01UL << GPIO_PORT_SET0_SETP5_Pos)                      /*!< GPIO_PORT SET0: SETP5 Mask          */
+#define GPIO_PORT_SET0_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET0: SETP6 Position      */
+#define GPIO_PORT_SET0_SETP6_Msk                              (0x01UL << GPIO_PORT_SET0_SETP6_Pos)                      /*!< GPIO_PORT SET0: SETP6 Mask          */
+#define GPIO_PORT_SET0_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET0: SETP7 Position      */
+#define GPIO_PORT_SET0_SETP7_Msk                              (0x01UL << GPIO_PORT_SET0_SETP7_Pos)                      /*!< GPIO_PORT SET0: SETP7 Mask          */
+#define GPIO_PORT_SET0_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET0: SETP8 Position      */
+#define GPIO_PORT_SET0_SETP8_Msk                              (0x01UL << GPIO_PORT_SET0_SETP8_Pos)                      /*!< GPIO_PORT SET0: SETP8 Mask          */
+#define GPIO_PORT_SET0_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET0: SETP9 Position      */
+#define GPIO_PORT_SET0_SETP9_Msk                              (0x01UL << GPIO_PORT_SET0_SETP9_Pos)                      /*!< GPIO_PORT SET0: SETP9 Mask          */
+#define GPIO_PORT_SET0_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET0: SETP10 Position     */
+#define GPIO_PORT_SET0_SETP10_Msk                             (0x01UL << GPIO_PORT_SET0_SETP10_Pos)                     /*!< GPIO_PORT SET0: SETP10 Mask         */
+#define GPIO_PORT_SET0_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET0: SETP11 Position     */
+#define GPIO_PORT_SET0_SETP11_Msk                             (0x01UL << GPIO_PORT_SET0_SETP11_Pos)                     /*!< GPIO_PORT SET0: SETP11 Mask         */
+#define GPIO_PORT_SET0_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET0: SETP12 Position     */
+#define GPIO_PORT_SET0_SETP12_Msk                             (0x01UL << GPIO_PORT_SET0_SETP12_Pos)                     /*!< GPIO_PORT SET0: SETP12 Mask         */
+#define GPIO_PORT_SET0_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET0: SETP13 Position     */
+#define GPIO_PORT_SET0_SETP13_Msk                             (0x01UL << GPIO_PORT_SET0_SETP13_Pos)                     /*!< GPIO_PORT SET0: SETP13 Mask         */
+#define GPIO_PORT_SET0_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET0: SETP14 Position     */
+#define GPIO_PORT_SET0_SETP14_Msk                             (0x01UL << GPIO_PORT_SET0_SETP14_Pos)                     /*!< GPIO_PORT SET0: SETP14 Mask         */
+#define GPIO_PORT_SET0_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET0: SETP15 Position     */
+#define GPIO_PORT_SET0_SETP15_Msk                             (0x01UL << GPIO_PORT_SET0_SETP15_Pos)                     /*!< GPIO_PORT SET0: SETP15 Mask         */
+#define GPIO_PORT_SET0_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET0: SETP16 Position     */
+#define GPIO_PORT_SET0_SETP16_Msk                             (0x01UL << GPIO_PORT_SET0_SETP16_Pos)                     /*!< GPIO_PORT SET0: SETP16 Mask         */
+#define GPIO_PORT_SET0_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET0: SETP17 Position     */
+#define GPIO_PORT_SET0_SETP17_Msk                             (0x01UL << GPIO_PORT_SET0_SETP17_Pos)                     /*!< GPIO_PORT SET0: SETP17 Mask         */
+#define GPIO_PORT_SET0_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET0: SETP18 Position     */
+#define GPIO_PORT_SET0_SETP18_Msk                             (0x01UL << GPIO_PORT_SET0_SETP18_Pos)                     /*!< GPIO_PORT SET0: SETP18 Mask         */
+#define GPIO_PORT_SET0_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET0: SETP19 Position     */
+#define GPIO_PORT_SET0_SETP19_Msk                             (0x01UL << GPIO_PORT_SET0_SETP19_Pos)                     /*!< GPIO_PORT SET0: SETP19 Mask         */
+#define GPIO_PORT_SET0_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET0: SETP20 Position     */
+#define GPIO_PORT_SET0_SETP20_Msk                             (0x01UL << GPIO_PORT_SET0_SETP20_Pos)                     /*!< GPIO_PORT SET0: SETP20 Mask         */
+#define GPIO_PORT_SET0_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET0: SETP21 Position     */
+#define GPIO_PORT_SET0_SETP21_Msk                             (0x01UL << GPIO_PORT_SET0_SETP21_Pos)                     /*!< GPIO_PORT SET0: SETP21 Mask         */
+#define GPIO_PORT_SET0_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET0: SETP22 Position     */
+#define GPIO_PORT_SET0_SETP22_Msk                             (0x01UL << GPIO_PORT_SET0_SETP22_Pos)                     /*!< GPIO_PORT SET0: SETP22 Mask         */
+#define GPIO_PORT_SET0_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET0: SETP23 Position     */
+#define GPIO_PORT_SET0_SETP23_Msk                             (0x01UL << GPIO_PORT_SET0_SETP23_Pos)                     /*!< GPIO_PORT SET0: SETP23 Mask         */
+#define GPIO_PORT_SET0_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET0: SETP24 Position     */
+#define GPIO_PORT_SET0_SETP24_Msk                             (0x01UL << GPIO_PORT_SET0_SETP24_Pos)                     /*!< GPIO_PORT SET0: SETP24 Mask         */
+#define GPIO_PORT_SET0_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET0: SETP25 Position     */
+#define GPIO_PORT_SET0_SETP25_Msk                             (0x01UL << GPIO_PORT_SET0_SETP25_Pos)                     /*!< GPIO_PORT SET0: SETP25 Mask         */
+#define GPIO_PORT_SET0_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET0: SETP26 Position     */
+#define GPIO_PORT_SET0_SETP26_Msk                             (0x01UL << GPIO_PORT_SET0_SETP26_Pos)                     /*!< GPIO_PORT SET0: SETP26 Mask         */
+#define GPIO_PORT_SET0_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET0: SETP27 Position     */
+#define GPIO_PORT_SET0_SETP27_Msk                             (0x01UL << GPIO_PORT_SET0_SETP27_Pos)                     /*!< GPIO_PORT SET0: SETP27 Mask         */
+#define GPIO_PORT_SET0_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET0: SETP28 Position     */
+#define GPIO_PORT_SET0_SETP28_Msk                             (0x01UL << GPIO_PORT_SET0_SETP28_Pos)                     /*!< GPIO_PORT SET0: SETP28 Mask         */
+#define GPIO_PORT_SET0_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET0: SETP29 Position     */
+#define GPIO_PORT_SET0_SETP29_Msk                             (0x01UL << GPIO_PORT_SET0_SETP29_Pos)                     /*!< GPIO_PORT SET0: SETP29 Mask         */
+#define GPIO_PORT_SET0_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET0: SETP30 Position     */
+#define GPIO_PORT_SET0_SETP30_Msk                             (0x01UL << GPIO_PORT_SET0_SETP30_Pos)                     /*!< GPIO_PORT SET0: SETP30 Mask         */
+#define GPIO_PORT_SET0_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET0: SETP31 Position     */
+#define GPIO_PORT_SET0_SETP31_Msk                             (0x01UL << GPIO_PORT_SET0_SETP31_Pos)                     /*!< GPIO_PORT SET0: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET1  -----------------------------------------
+#define GPIO_PORT_SET1_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET1: SETP0 Position      */
+#define GPIO_PORT_SET1_SETP0_Msk                              (0x01UL << GPIO_PORT_SET1_SETP0_Pos)                      /*!< GPIO_PORT SET1: SETP0 Mask          */
+#define GPIO_PORT_SET1_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET1: SETP1 Position      */
+#define GPIO_PORT_SET1_SETP1_Msk                              (0x01UL << GPIO_PORT_SET1_SETP1_Pos)                      /*!< GPIO_PORT SET1: SETP1 Mask          */
+#define GPIO_PORT_SET1_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET1: SETP2 Position      */
+#define GPIO_PORT_SET1_SETP2_Msk                              (0x01UL << GPIO_PORT_SET1_SETP2_Pos)                      /*!< GPIO_PORT SET1: SETP2 Mask          */
+#define GPIO_PORT_SET1_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET1: SETP3 Position      */
+#define GPIO_PORT_SET1_SETP3_Msk                              (0x01UL << GPIO_PORT_SET1_SETP3_Pos)                      /*!< GPIO_PORT SET1: SETP3 Mask          */
+#define GPIO_PORT_SET1_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET1: SETP4 Position      */
+#define GPIO_PORT_SET1_SETP4_Msk                              (0x01UL << GPIO_PORT_SET1_SETP4_Pos)                      /*!< GPIO_PORT SET1: SETP4 Mask          */
+#define GPIO_PORT_SET1_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET1: SETP5 Position      */
+#define GPIO_PORT_SET1_SETP5_Msk                              (0x01UL << GPIO_PORT_SET1_SETP5_Pos)                      /*!< GPIO_PORT SET1: SETP5 Mask          */
+#define GPIO_PORT_SET1_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET1: SETP6 Position      */
+#define GPIO_PORT_SET1_SETP6_Msk                              (0x01UL << GPIO_PORT_SET1_SETP6_Pos)                      /*!< GPIO_PORT SET1: SETP6 Mask          */
+#define GPIO_PORT_SET1_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET1: SETP7 Position      */
+#define GPIO_PORT_SET1_SETP7_Msk                              (0x01UL << GPIO_PORT_SET1_SETP7_Pos)                      /*!< GPIO_PORT SET1: SETP7 Mask          */
+#define GPIO_PORT_SET1_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET1: SETP8 Position      */
+#define GPIO_PORT_SET1_SETP8_Msk                              (0x01UL << GPIO_PORT_SET1_SETP8_Pos)                      /*!< GPIO_PORT SET1: SETP8 Mask          */
+#define GPIO_PORT_SET1_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET1: SETP9 Position      */
+#define GPIO_PORT_SET1_SETP9_Msk                              (0x01UL << GPIO_PORT_SET1_SETP9_Pos)                      /*!< GPIO_PORT SET1: SETP9 Mask          */
+#define GPIO_PORT_SET1_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET1: SETP10 Position     */
+#define GPIO_PORT_SET1_SETP10_Msk                             (0x01UL << GPIO_PORT_SET1_SETP10_Pos)                     /*!< GPIO_PORT SET1: SETP10 Mask         */
+#define GPIO_PORT_SET1_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET1: SETP11 Position     */
+#define GPIO_PORT_SET1_SETP11_Msk                             (0x01UL << GPIO_PORT_SET1_SETP11_Pos)                     /*!< GPIO_PORT SET1: SETP11 Mask         */
+#define GPIO_PORT_SET1_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET1: SETP12 Position     */
+#define GPIO_PORT_SET1_SETP12_Msk                             (0x01UL << GPIO_PORT_SET1_SETP12_Pos)                     /*!< GPIO_PORT SET1: SETP12 Mask         */
+#define GPIO_PORT_SET1_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET1: SETP13 Position     */
+#define GPIO_PORT_SET1_SETP13_Msk                             (0x01UL << GPIO_PORT_SET1_SETP13_Pos)                     /*!< GPIO_PORT SET1: SETP13 Mask         */
+#define GPIO_PORT_SET1_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET1: SETP14 Position     */
+#define GPIO_PORT_SET1_SETP14_Msk                             (0x01UL << GPIO_PORT_SET1_SETP14_Pos)                     /*!< GPIO_PORT SET1: SETP14 Mask         */
+#define GPIO_PORT_SET1_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET1: SETP15 Position     */
+#define GPIO_PORT_SET1_SETP15_Msk                             (0x01UL << GPIO_PORT_SET1_SETP15_Pos)                     /*!< GPIO_PORT SET1: SETP15 Mask         */
+#define GPIO_PORT_SET1_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET1: SETP16 Position     */
+#define GPIO_PORT_SET1_SETP16_Msk                             (0x01UL << GPIO_PORT_SET1_SETP16_Pos)                     /*!< GPIO_PORT SET1: SETP16 Mask         */
+#define GPIO_PORT_SET1_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET1: SETP17 Position     */
+#define GPIO_PORT_SET1_SETP17_Msk                             (0x01UL << GPIO_PORT_SET1_SETP17_Pos)                     /*!< GPIO_PORT SET1: SETP17 Mask         */
+#define GPIO_PORT_SET1_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET1: SETP18 Position     */
+#define GPIO_PORT_SET1_SETP18_Msk                             (0x01UL << GPIO_PORT_SET1_SETP18_Pos)                     /*!< GPIO_PORT SET1: SETP18 Mask         */
+#define GPIO_PORT_SET1_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET1: SETP19 Position     */
+#define GPIO_PORT_SET1_SETP19_Msk                             (0x01UL << GPIO_PORT_SET1_SETP19_Pos)                     /*!< GPIO_PORT SET1: SETP19 Mask         */
+#define GPIO_PORT_SET1_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET1: SETP20 Position     */
+#define GPIO_PORT_SET1_SETP20_Msk                             (0x01UL << GPIO_PORT_SET1_SETP20_Pos)                     /*!< GPIO_PORT SET1: SETP20 Mask         */
+#define GPIO_PORT_SET1_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET1: SETP21 Position     */
+#define GPIO_PORT_SET1_SETP21_Msk                             (0x01UL << GPIO_PORT_SET1_SETP21_Pos)                     /*!< GPIO_PORT SET1: SETP21 Mask         */
+#define GPIO_PORT_SET1_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET1: SETP22 Position     */
+#define GPIO_PORT_SET1_SETP22_Msk                             (0x01UL << GPIO_PORT_SET1_SETP22_Pos)                     /*!< GPIO_PORT SET1: SETP22 Mask         */
+#define GPIO_PORT_SET1_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET1: SETP23 Position     */
+#define GPIO_PORT_SET1_SETP23_Msk                             (0x01UL << GPIO_PORT_SET1_SETP23_Pos)                     /*!< GPIO_PORT SET1: SETP23 Mask         */
+#define GPIO_PORT_SET1_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET1: SETP24 Position     */
+#define GPIO_PORT_SET1_SETP24_Msk                             (0x01UL << GPIO_PORT_SET1_SETP24_Pos)                     /*!< GPIO_PORT SET1: SETP24 Mask         */
+#define GPIO_PORT_SET1_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET1: SETP25 Position     */
+#define GPIO_PORT_SET1_SETP25_Msk                             (0x01UL << GPIO_PORT_SET1_SETP25_Pos)                     /*!< GPIO_PORT SET1: SETP25 Mask         */
+#define GPIO_PORT_SET1_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET1: SETP26 Position     */
+#define GPIO_PORT_SET1_SETP26_Msk                             (0x01UL << GPIO_PORT_SET1_SETP26_Pos)                     /*!< GPIO_PORT SET1: SETP26 Mask         */
+#define GPIO_PORT_SET1_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET1: SETP27 Position     */
+#define GPIO_PORT_SET1_SETP27_Msk                             (0x01UL << GPIO_PORT_SET1_SETP27_Pos)                     /*!< GPIO_PORT SET1: SETP27 Mask         */
+#define GPIO_PORT_SET1_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET1: SETP28 Position     */
+#define GPIO_PORT_SET1_SETP28_Msk                             (0x01UL << GPIO_PORT_SET1_SETP28_Pos)                     /*!< GPIO_PORT SET1: SETP28 Mask         */
+#define GPIO_PORT_SET1_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET1: SETP29 Position     */
+#define GPIO_PORT_SET1_SETP29_Msk                             (0x01UL << GPIO_PORT_SET1_SETP29_Pos)                     /*!< GPIO_PORT SET1: SETP29 Mask         */
+#define GPIO_PORT_SET1_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET1: SETP30 Position     */
+#define GPIO_PORT_SET1_SETP30_Msk                             (0x01UL << GPIO_PORT_SET1_SETP30_Pos)                     /*!< GPIO_PORT SET1: SETP30 Mask         */
+#define GPIO_PORT_SET1_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET1: SETP31 Position     */
+#define GPIO_PORT_SET1_SETP31_Msk                             (0x01UL << GPIO_PORT_SET1_SETP31_Pos)                     /*!< GPIO_PORT SET1: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET2  -----------------------------------------
+#define GPIO_PORT_SET2_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET2: SETP0 Position      */
+#define GPIO_PORT_SET2_SETP0_Msk                              (0x01UL << GPIO_PORT_SET2_SETP0_Pos)                      /*!< GPIO_PORT SET2: SETP0 Mask          */
+#define GPIO_PORT_SET2_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET2: SETP1 Position      */
+#define GPIO_PORT_SET2_SETP1_Msk                              (0x01UL << GPIO_PORT_SET2_SETP1_Pos)                      /*!< GPIO_PORT SET2: SETP1 Mask          */
+#define GPIO_PORT_SET2_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET2: SETP2 Position      */
+#define GPIO_PORT_SET2_SETP2_Msk                              (0x01UL << GPIO_PORT_SET2_SETP2_Pos)                      /*!< GPIO_PORT SET2: SETP2 Mask          */
+#define GPIO_PORT_SET2_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET2: SETP3 Position      */
+#define GPIO_PORT_SET2_SETP3_Msk                              (0x01UL << GPIO_PORT_SET2_SETP3_Pos)                      /*!< GPIO_PORT SET2: SETP3 Mask          */
+#define GPIO_PORT_SET2_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET2: SETP4 Position      */
+#define GPIO_PORT_SET2_SETP4_Msk                              (0x01UL << GPIO_PORT_SET2_SETP4_Pos)                      /*!< GPIO_PORT SET2: SETP4 Mask          */
+#define GPIO_PORT_SET2_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET2: SETP5 Position      */
+#define GPIO_PORT_SET2_SETP5_Msk                              (0x01UL << GPIO_PORT_SET2_SETP5_Pos)                      /*!< GPIO_PORT SET2: SETP5 Mask          */
+#define GPIO_PORT_SET2_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET2: SETP6 Position      */
+#define GPIO_PORT_SET2_SETP6_Msk                              (0x01UL << GPIO_PORT_SET2_SETP6_Pos)                      /*!< GPIO_PORT SET2: SETP6 Mask          */
+#define GPIO_PORT_SET2_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET2: SETP7 Position      */
+#define GPIO_PORT_SET2_SETP7_Msk                              (0x01UL << GPIO_PORT_SET2_SETP7_Pos)                      /*!< GPIO_PORT SET2: SETP7 Mask          */
+#define GPIO_PORT_SET2_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET2: SETP8 Position      */
+#define GPIO_PORT_SET2_SETP8_Msk                              (0x01UL << GPIO_PORT_SET2_SETP8_Pos)                      /*!< GPIO_PORT SET2: SETP8 Mask          */
+#define GPIO_PORT_SET2_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET2: SETP9 Position      */
+#define GPIO_PORT_SET2_SETP9_Msk                              (0x01UL << GPIO_PORT_SET2_SETP9_Pos)                      /*!< GPIO_PORT SET2: SETP9 Mask          */
+#define GPIO_PORT_SET2_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET2: SETP10 Position     */
+#define GPIO_PORT_SET2_SETP10_Msk                             (0x01UL << GPIO_PORT_SET2_SETP10_Pos)                     /*!< GPIO_PORT SET2: SETP10 Mask         */
+#define GPIO_PORT_SET2_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET2: SETP11 Position     */
+#define GPIO_PORT_SET2_SETP11_Msk                             (0x01UL << GPIO_PORT_SET2_SETP11_Pos)                     /*!< GPIO_PORT SET2: SETP11 Mask         */
+#define GPIO_PORT_SET2_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET2: SETP12 Position     */
+#define GPIO_PORT_SET2_SETP12_Msk                             (0x01UL << GPIO_PORT_SET2_SETP12_Pos)                     /*!< GPIO_PORT SET2: SETP12 Mask         */
+#define GPIO_PORT_SET2_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET2: SETP13 Position     */
+#define GPIO_PORT_SET2_SETP13_Msk                             (0x01UL << GPIO_PORT_SET2_SETP13_Pos)                     /*!< GPIO_PORT SET2: SETP13 Mask         */
+#define GPIO_PORT_SET2_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET2: SETP14 Position     */
+#define GPIO_PORT_SET2_SETP14_Msk                             (0x01UL << GPIO_PORT_SET2_SETP14_Pos)                     /*!< GPIO_PORT SET2: SETP14 Mask         */
+#define GPIO_PORT_SET2_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET2: SETP15 Position     */
+#define GPIO_PORT_SET2_SETP15_Msk                             (0x01UL << GPIO_PORT_SET2_SETP15_Pos)                     /*!< GPIO_PORT SET2: SETP15 Mask         */
+#define GPIO_PORT_SET2_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET2: SETP16 Position     */
+#define GPIO_PORT_SET2_SETP16_Msk                             (0x01UL << GPIO_PORT_SET2_SETP16_Pos)                     /*!< GPIO_PORT SET2: SETP16 Mask         */
+#define GPIO_PORT_SET2_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET2: SETP17 Position     */
+#define GPIO_PORT_SET2_SETP17_Msk                             (0x01UL << GPIO_PORT_SET2_SETP17_Pos)                     /*!< GPIO_PORT SET2: SETP17 Mask         */
+#define GPIO_PORT_SET2_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET2: SETP18 Position     */
+#define GPIO_PORT_SET2_SETP18_Msk                             (0x01UL << GPIO_PORT_SET2_SETP18_Pos)                     /*!< GPIO_PORT SET2: SETP18 Mask         */
+#define GPIO_PORT_SET2_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET2: SETP19 Position     */
+#define GPIO_PORT_SET2_SETP19_Msk                             (0x01UL << GPIO_PORT_SET2_SETP19_Pos)                     /*!< GPIO_PORT SET2: SETP19 Mask         */
+#define GPIO_PORT_SET2_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET2: SETP20 Position     */
+#define GPIO_PORT_SET2_SETP20_Msk                             (0x01UL << GPIO_PORT_SET2_SETP20_Pos)                     /*!< GPIO_PORT SET2: SETP20 Mask         */
+#define GPIO_PORT_SET2_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET2: SETP21 Position     */
+#define GPIO_PORT_SET2_SETP21_Msk                             (0x01UL << GPIO_PORT_SET2_SETP21_Pos)                     /*!< GPIO_PORT SET2: SETP21 Mask         */
+#define GPIO_PORT_SET2_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET2: SETP22 Position     */
+#define GPIO_PORT_SET2_SETP22_Msk                             (0x01UL << GPIO_PORT_SET2_SETP22_Pos)                     /*!< GPIO_PORT SET2: SETP22 Mask         */
+#define GPIO_PORT_SET2_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET2: SETP23 Position     */
+#define GPIO_PORT_SET2_SETP23_Msk                             (0x01UL << GPIO_PORT_SET2_SETP23_Pos)                     /*!< GPIO_PORT SET2: SETP23 Mask         */
+#define GPIO_PORT_SET2_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET2: SETP24 Position     */
+#define GPIO_PORT_SET2_SETP24_Msk                             (0x01UL << GPIO_PORT_SET2_SETP24_Pos)                     /*!< GPIO_PORT SET2: SETP24 Mask         */
+#define GPIO_PORT_SET2_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET2: SETP25 Position     */
+#define GPIO_PORT_SET2_SETP25_Msk                             (0x01UL << GPIO_PORT_SET2_SETP25_Pos)                     /*!< GPIO_PORT SET2: SETP25 Mask         */
+#define GPIO_PORT_SET2_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET2: SETP26 Position     */
+#define GPIO_PORT_SET2_SETP26_Msk                             (0x01UL << GPIO_PORT_SET2_SETP26_Pos)                     /*!< GPIO_PORT SET2: SETP26 Mask         */
+#define GPIO_PORT_SET2_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET2: SETP27 Position     */
+#define GPIO_PORT_SET2_SETP27_Msk                             (0x01UL << GPIO_PORT_SET2_SETP27_Pos)                     /*!< GPIO_PORT SET2: SETP27 Mask         */
+#define GPIO_PORT_SET2_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET2: SETP28 Position     */
+#define GPIO_PORT_SET2_SETP28_Msk                             (0x01UL << GPIO_PORT_SET2_SETP28_Pos)                     /*!< GPIO_PORT SET2: SETP28 Mask         */
+#define GPIO_PORT_SET2_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET2: SETP29 Position     */
+#define GPIO_PORT_SET2_SETP29_Msk                             (0x01UL << GPIO_PORT_SET2_SETP29_Pos)                     /*!< GPIO_PORT SET2: SETP29 Mask         */
+#define GPIO_PORT_SET2_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET2: SETP30 Position     */
+#define GPIO_PORT_SET2_SETP30_Msk                             (0x01UL << GPIO_PORT_SET2_SETP30_Pos)                     /*!< GPIO_PORT SET2: SETP30 Mask         */
+#define GPIO_PORT_SET2_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET2: SETP31 Position     */
+#define GPIO_PORT_SET2_SETP31_Msk                             (0x01UL << GPIO_PORT_SET2_SETP31_Pos)                     /*!< GPIO_PORT SET2: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET3  -----------------------------------------
+#define GPIO_PORT_SET3_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET3: SETP0 Position      */
+#define GPIO_PORT_SET3_SETP0_Msk                              (0x01UL << GPIO_PORT_SET3_SETP0_Pos)                      /*!< GPIO_PORT SET3: SETP0 Mask          */
+#define GPIO_PORT_SET3_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET3: SETP1 Position      */
+#define GPIO_PORT_SET3_SETP1_Msk                              (0x01UL << GPIO_PORT_SET3_SETP1_Pos)                      /*!< GPIO_PORT SET3: SETP1 Mask          */
+#define GPIO_PORT_SET3_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET3: SETP2 Position      */
+#define GPIO_PORT_SET3_SETP2_Msk                              (0x01UL << GPIO_PORT_SET3_SETP2_Pos)                      /*!< GPIO_PORT SET3: SETP2 Mask          */
+#define GPIO_PORT_SET3_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET3: SETP3 Position      */
+#define GPIO_PORT_SET3_SETP3_Msk                              (0x01UL << GPIO_PORT_SET3_SETP3_Pos)                      /*!< GPIO_PORT SET3: SETP3 Mask          */
+#define GPIO_PORT_SET3_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET3: SETP4 Position      */
+#define GPIO_PORT_SET3_SETP4_Msk                              (0x01UL << GPIO_PORT_SET3_SETP4_Pos)                      /*!< GPIO_PORT SET3: SETP4 Mask          */
+#define GPIO_PORT_SET3_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET3: SETP5 Position      */
+#define GPIO_PORT_SET3_SETP5_Msk                              (0x01UL << GPIO_PORT_SET3_SETP5_Pos)                      /*!< GPIO_PORT SET3: SETP5 Mask          */
+#define GPIO_PORT_SET3_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET3: SETP6 Position      */
+#define GPIO_PORT_SET3_SETP6_Msk                              (0x01UL << GPIO_PORT_SET3_SETP6_Pos)                      /*!< GPIO_PORT SET3: SETP6 Mask          */
+#define GPIO_PORT_SET3_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET3: SETP7 Position      */
+#define GPIO_PORT_SET3_SETP7_Msk                              (0x01UL << GPIO_PORT_SET3_SETP7_Pos)                      /*!< GPIO_PORT SET3: SETP7 Mask          */
+#define GPIO_PORT_SET3_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET3: SETP8 Position      */
+#define GPIO_PORT_SET3_SETP8_Msk                              (0x01UL << GPIO_PORT_SET3_SETP8_Pos)                      /*!< GPIO_PORT SET3: SETP8 Mask          */
+#define GPIO_PORT_SET3_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET3: SETP9 Position      */
+#define GPIO_PORT_SET3_SETP9_Msk                              (0x01UL << GPIO_PORT_SET3_SETP9_Pos)                      /*!< GPIO_PORT SET3: SETP9 Mask          */
+#define GPIO_PORT_SET3_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET3: SETP10 Position     */
+#define GPIO_PORT_SET3_SETP10_Msk                             (0x01UL << GPIO_PORT_SET3_SETP10_Pos)                     /*!< GPIO_PORT SET3: SETP10 Mask         */
+#define GPIO_PORT_SET3_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET3: SETP11 Position     */
+#define GPIO_PORT_SET3_SETP11_Msk                             (0x01UL << GPIO_PORT_SET3_SETP11_Pos)                     /*!< GPIO_PORT SET3: SETP11 Mask         */
+#define GPIO_PORT_SET3_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET3: SETP12 Position     */
+#define GPIO_PORT_SET3_SETP12_Msk                             (0x01UL << GPIO_PORT_SET3_SETP12_Pos)                     /*!< GPIO_PORT SET3: SETP12 Mask         */
+#define GPIO_PORT_SET3_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET3: SETP13 Position     */
+#define GPIO_PORT_SET3_SETP13_Msk                             (0x01UL << GPIO_PORT_SET3_SETP13_Pos)                     /*!< GPIO_PORT SET3: SETP13 Mask         */
+#define GPIO_PORT_SET3_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET3: SETP14 Position     */
+#define GPIO_PORT_SET3_SETP14_Msk                             (0x01UL << GPIO_PORT_SET3_SETP14_Pos)                     /*!< GPIO_PORT SET3: SETP14 Mask         */
+#define GPIO_PORT_SET3_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET3: SETP15 Position     */
+#define GPIO_PORT_SET3_SETP15_Msk                             (0x01UL << GPIO_PORT_SET3_SETP15_Pos)                     /*!< GPIO_PORT SET3: SETP15 Mask         */
+#define GPIO_PORT_SET3_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET3: SETP16 Position     */
+#define GPIO_PORT_SET3_SETP16_Msk                             (0x01UL << GPIO_PORT_SET3_SETP16_Pos)                     /*!< GPIO_PORT SET3: SETP16 Mask         */
+#define GPIO_PORT_SET3_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET3: SETP17 Position     */
+#define GPIO_PORT_SET3_SETP17_Msk                             (0x01UL << GPIO_PORT_SET3_SETP17_Pos)                     /*!< GPIO_PORT SET3: SETP17 Mask         */
+#define GPIO_PORT_SET3_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET3: SETP18 Position     */
+#define GPIO_PORT_SET3_SETP18_Msk                             (0x01UL << GPIO_PORT_SET3_SETP18_Pos)                     /*!< GPIO_PORT SET3: SETP18 Mask         */
+#define GPIO_PORT_SET3_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET3: SETP19 Position     */
+#define GPIO_PORT_SET3_SETP19_Msk                             (0x01UL << GPIO_PORT_SET3_SETP19_Pos)                     /*!< GPIO_PORT SET3: SETP19 Mask         */
+#define GPIO_PORT_SET3_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET3: SETP20 Position     */
+#define GPIO_PORT_SET3_SETP20_Msk                             (0x01UL << GPIO_PORT_SET3_SETP20_Pos)                     /*!< GPIO_PORT SET3: SETP20 Mask         */
+#define GPIO_PORT_SET3_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET3: SETP21 Position     */
+#define GPIO_PORT_SET3_SETP21_Msk                             (0x01UL << GPIO_PORT_SET3_SETP21_Pos)                     /*!< GPIO_PORT SET3: SETP21 Mask         */
+#define GPIO_PORT_SET3_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET3: SETP22 Position     */
+#define GPIO_PORT_SET3_SETP22_Msk                             (0x01UL << GPIO_PORT_SET3_SETP22_Pos)                     /*!< GPIO_PORT SET3: SETP22 Mask         */
+#define GPIO_PORT_SET3_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET3: SETP23 Position     */
+#define GPIO_PORT_SET3_SETP23_Msk                             (0x01UL << GPIO_PORT_SET3_SETP23_Pos)                     /*!< GPIO_PORT SET3: SETP23 Mask         */
+#define GPIO_PORT_SET3_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET3: SETP24 Position     */
+#define GPIO_PORT_SET3_SETP24_Msk                             (0x01UL << GPIO_PORT_SET3_SETP24_Pos)                     /*!< GPIO_PORT SET3: SETP24 Mask         */
+#define GPIO_PORT_SET3_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET3: SETP25 Position     */
+#define GPIO_PORT_SET3_SETP25_Msk                             (0x01UL << GPIO_PORT_SET3_SETP25_Pos)                     /*!< GPIO_PORT SET3: SETP25 Mask         */
+#define GPIO_PORT_SET3_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET3: SETP26 Position     */
+#define GPIO_PORT_SET3_SETP26_Msk                             (0x01UL << GPIO_PORT_SET3_SETP26_Pos)                     /*!< GPIO_PORT SET3: SETP26 Mask         */
+#define GPIO_PORT_SET3_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET3: SETP27 Position     */
+#define GPIO_PORT_SET3_SETP27_Msk                             (0x01UL << GPIO_PORT_SET3_SETP27_Pos)                     /*!< GPIO_PORT SET3: SETP27 Mask         */
+#define GPIO_PORT_SET3_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET3: SETP28 Position     */
+#define GPIO_PORT_SET3_SETP28_Msk                             (0x01UL << GPIO_PORT_SET3_SETP28_Pos)                     /*!< GPIO_PORT SET3: SETP28 Mask         */
+#define GPIO_PORT_SET3_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET3: SETP29 Position     */
+#define GPIO_PORT_SET3_SETP29_Msk                             (0x01UL << GPIO_PORT_SET3_SETP29_Pos)                     /*!< GPIO_PORT SET3: SETP29 Mask         */
+#define GPIO_PORT_SET3_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET3: SETP30 Position     */
+#define GPIO_PORT_SET3_SETP30_Msk                             (0x01UL << GPIO_PORT_SET3_SETP30_Pos)                     /*!< GPIO_PORT SET3: SETP30 Mask         */
+#define GPIO_PORT_SET3_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET3: SETP31 Position     */
+#define GPIO_PORT_SET3_SETP31_Msk                             (0x01UL << GPIO_PORT_SET3_SETP31_Pos)                     /*!< GPIO_PORT SET3: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET4  -----------------------------------------
+#define GPIO_PORT_SET4_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET4: SETP0 Position      */
+#define GPIO_PORT_SET4_SETP0_Msk                              (0x01UL << GPIO_PORT_SET4_SETP0_Pos)                      /*!< GPIO_PORT SET4: SETP0 Mask          */
+#define GPIO_PORT_SET4_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET4: SETP1 Position      */
+#define GPIO_PORT_SET4_SETP1_Msk                              (0x01UL << GPIO_PORT_SET4_SETP1_Pos)                      /*!< GPIO_PORT SET4: SETP1 Mask          */
+#define GPIO_PORT_SET4_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET4: SETP2 Position      */
+#define GPIO_PORT_SET4_SETP2_Msk                              (0x01UL << GPIO_PORT_SET4_SETP2_Pos)                      /*!< GPIO_PORT SET4: SETP2 Mask          */
+#define GPIO_PORT_SET4_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET4: SETP3 Position      */
+#define GPIO_PORT_SET4_SETP3_Msk                              (0x01UL << GPIO_PORT_SET4_SETP3_Pos)                      /*!< GPIO_PORT SET4: SETP3 Mask          */
+#define GPIO_PORT_SET4_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET4: SETP4 Position      */
+#define GPIO_PORT_SET4_SETP4_Msk                              (0x01UL << GPIO_PORT_SET4_SETP4_Pos)                      /*!< GPIO_PORT SET4: SETP4 Mask          */
+#define GPIO_PORT_SET4_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET4: SETP5 Position      */
+#define GPIO_PORT_SET4_SETP5_Msk                              (0x01UL << GPIO_PORT_SET4_SETP5_Pos)                      /*!< GPIO_PORT SET4: SETP5 Mask          */
+#define GPIO_PORT_SET4_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET4: SETP6 Position      */
+#define GPIO_PORT_SET4_SETP6_Msk                              (0x01UL << GPIO_PORT_SET4_SETP6_Pos)                      /*!< GPIO_PORT SET4: SETP6 Mask          */
+#define GPIO_PORT_SET4_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET4: SETP7 Position      */
+#define GPIO_PORT_SET4_SETP7_Msk                              (0x01UL << GPIO_PORT_SET4_SETP7_Pos)                      /*!< GPIO_PORT SET4: SETP7 Mask          */
+#define GPIO_PORT_SET4_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET4: SETP8 Position      */
+#define GPIO_PORT_SET4_SETP8_Msk                              (0x01UL << GPIO_PORT_SET4_SETP8_Pos)                      /*!< GPIO_PORT SET4: SETP8 Mask          */
+#define GPIO_PORT_SET4_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET4: SETP9 Position      */
+#define GPIO_PORT_SET4_SETP9_Msk                              (0x01UL << GPIO_PORT_SET4_SETP9_Pos)                      /*!< GPIO_PORT SET4: SETP9 Mask          */
+#define GPIO_PORT_SET4_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET4: SETP10 Position     */
+#define GPIO_PORT_SET4_SETP10_Msk                             (0x01UL << GPIO_PORT_SET4_SETP10_Pos)                     /*!< GPIO_PORT SET4: SETP10 Mask         */
+#define GPIO_PORT_SET4_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET4: SETP11 Position     */
+#define GPIO_PORT_SET4_SETP11_Msk                             (0x01UL << GPIO_PORT_SET4_SETP11_Pos)                     /*!< GPIO_PORT SET4: SETP11 Mask         */
+#define GPIO_PORT_SET4_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET4: SETP12 Position     */
+#define GPIO_PORT_SET4_SETP12_Msk                             (0x01UL << GPIO_PORT_SET4_SETP12_Pos)                     /*!< GPIO_PORT SET4: SETP12 Mask         */
+#define GPIO_PORT_SET4_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET4: SETP13 Position     */
+#define GPIO_PORT_SET4_SETP13_Msk                             (0x01UL << GPIO_PORT_SET4_SETP13_Pos)                     /*!< GPIO_PORT SET4: SETP13 Mask         */
+#define GPIO_PORT_SET4_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET4: SETP14 Position     */
+#define GPIO_PORT_SET4_SETP14_Msk                             (0x01UL << GPIO_PORT_SET4_SETP14_Pos)                     /*!< GPIO_PORT SET4: SETP14 Mask         */
+#define GPIO_PORT_SET4_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET4: SETP15 Position     */
+#define GPIO_PORT_SET4_SETP15_Msk                             (0x01UL << GPIO_PORT_SET4_SETP15_Pos)                     /*!< GPIO_PORT SET4: SETP15 Mask         */
+#define GPIO_PORT_SET4_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET4: SETP16 Position     */
+#define GPIO_PORT_SET4_SETP16_Msk                             (0x01UL << GPIO_PORT_SET4_SETP16_Pos)                     /*!< GPIO_PORT SET4: SETP16 Mask         */
+#define GPIO_PORT_SET4_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET4: SETP17 Position     */
+#define GPIO_PORT_SET4_SETP17_Msk                             (0x01UL << GPIO_PORT_SET4_SETP17_Pos)                     /*!< GPIO_PORT SET4: SETP17 Mask         */
+#define GPIO_PORT_SET4_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET4: SETP18 Position     */
+#define GPIO_PORT_SET4_SETP18_Msk                             (0x01UL << GPIO_PORT_SET4_SETP18_Pos)                     /*!< GPIO_PORT SET4: SETP18 Mask         */
+#define GPIO_PORT_SET4_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET4: SETP19 Position     */
+#define GPIO_PORT_SET4_SETP19_Msk                             (0x01UL << GPIO_PORT_SET4_SETP19_Pos)                     /*!< GPIO_PORT SET4: SETP19 Mask         */
+#define GPIO_PORT_SET4_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET4: SETP20 Position     */
+#define GPIO_PORT_SET4_SETP20_Msk                             (0x01UL << GPIO_PORT_SET4_SETP20_Pos)                     /*!< GPIO_PORT SET4: SETP20 Mask         */
+#define GPIO_PORT_SET4_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET4: SETP21 Position     */
+#define GPIO_PORT_SET4_SETP21_Msk                             (0x01UL << GPIO_PORT_SET4_SETP21_Pos)                     /*!< GPIO_PORT SET4: SETP21 Mask         */
+#define GPIO_PORT_SET4_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET4: SETP22 Position     */
+#define GPIO_PORT_SET4_SETP22_Msk                             (0x01UL << GPIO_PORT_SET4_SETP22_Pos)                     /*!< GPIO_PORT SET4: SETP22 Mask         */
+#define GPIO_PORT_SET4_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET4: SETP23 Position     */
+#define GPIO_PORT_SET4_SETP23_Msk                             (0x01UL << GPIO_PORT_SET4_SETP23_Pos)                     /*!< GPIO_PORT SET4: SETP23 Mask         */
+#define GPIO_PORT_SET4_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET4: SETP24 Position     */
+#define GPIO_PORT_SET4_SETP24_Msk                             (0x01UL << GPIO_PORT_SET4_SETP24_Pos)                     /*!< GPIO_PORT SET4: SETP24 Mask         */
+#define GPIO_PORT_SET4_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET4: SETP25 Position     */
+#define GPIO_PORT_SET4_SETP25_Msk                             (0x01UL << GPIO_PORT_SET4_SETP25_Pos)                     /*!< GPIO_PORT SET4: SETP25 Mask         */
+#define GPIO_PORT_SET4_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET4: SETP26 Position     */
+#define GPIO_PORT_SET4_SETP26_Msk                             (0x01UL << GPIO_PORT_SET4_SETP26_Pos)                     /*!< GPIO_PORT SET4: SETP26 Mask         */
+#define GPIO_PORT_SET4_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET4: SETP27 Position     */
+#define GPIO_PORT_SET4_SETP27_Msk                             (0x01UL << GPIO_PORT_SET4_SETP27_Pos)                     /*!< GPIO_PORT SET4: SETP27 Mask         */
+#define GPIO_PORT_SET4_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET4: SETP28 Position     */
+#define GPIO_PORT_SET4_SETP28_Msk                             (0x01UL << GPIO_PORT_SET4_SETP28_Pos)                     /*!< GPIO_PORT SET4: SETP28 Mask         */
+#define GPIO_PORT_SET4_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET4: SETP29 Position     */
+#define GPIO_PORT_SET4_SETP29_Msk                             (0x01UL << GPIO_PORT_SET4_SETP29_Pos)                     /*!< GPIO_PORT SET4: SETP29 Mask         */
+#define GPIO_PORT_SET4_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET4: SETP30 Position     */
+#define GPIO_PORT_SET4_SETP30_Msk                             (0x01UL << GPIO_PORT_SET4_SETP30_Pos)                     /*!< GPIO_PORT SET4: SETP30 Mask         */
+#define GPIO_PORT_SET4_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET4: SETP31 Position     */
+#define GPIO_PORT_SET4_SETP31_Msk                             (0x01UL << GPIO_PORT_SET4_SETP31_Pos)                     /*!< GPIO_PORT SET4: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET5  -----------------------------------------
+#define GPIO_PORT_SET5_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET5: SETP0 Position      */
+#define GPIO_PORT_SET5_SETP0_Msk                              (0x01UL << GPIO_PORT_SET5_SETP0_Pos)                      /*!< GPIO_PORT SET5: SETP0 Mask          */
+#define GPIO_PORT_SET5_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET5: SETP1 Position      */
+#define GPIO_PORT_SET5_SETP1_Msk                              (0x01UL << GPIO_PORT_SET5_SETP1_Pos)                      /*!< GPIO_PORT SET5: SETP1 Mask          */
+#define GPIO_PORT_SET5_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET5: SETP2 Position      */
+#define GPIO_PORT_SET5_SETP2_Msk                              (0x01UL << GPIO_PORT_SET5_SETP2_Pos)                      /*!< GPIO_PORT SET5: SETP2 Mask          */
+#define GPIO_PORT_SET5_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET5: SETP3 Position      */
+#define GPIO_PORT_SET5_SETP3_Msk                              (0x01UL << GPIO_PORT_SET5_SETP3_Pos)                      /*!< GPIO_PORT SET5: SETP3 Mask          */
+#define GPIO_PORT_SET5_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET5: SETP4 Position      */
+#define GPIO_PORT_SET5_SETP4_Msk                              (0x01UL << GPIO_PORT_SET5_SETP4_Pos)                      /*!< GPIO_PORT SET5: SETP4 Mask          */
+#define GPIO_PORT_SET5_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET5: SETP5 Position      */
+#define GPIO_PORT_SET5_SETP5_Msk                              (0x01UL << GPIO_PORT_SET5_SETP5_Pos)                      /*!< GPIO_PORT SET5: SETP5 Mask          */
+#define GPIO_PORT_SET5_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET5: SETP6 Position      */
+#define GPIO_PORT_SET5_SETP6_Msk                              (0x01UL << GPIO_PORT_SET5_SETP6_Pos)                      /*!< GPIO_PORT SET5: SETP6 Mask          */
+#define GPIO_PORT_SET5_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET5: SETP7 Position      */
+#define GPIO_PORT_SET5_SETP7_Msk                              (0x01UL << GPIO_PORT_SET5_SETP7_Pos)                      /*!< GPIO_PORT SET5: SETP7 Mask          */
+#define GPIO_PORT_SET5_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET5: SETP8 Position      */
+#define GPIO_PORT_SET5_SETP8_Msk                              (0x01UL << GPIO_PORT_SET5_SETP8_Pos)                      /*!< GPIO_PORT SET5: SETP8 Mask          */
+#define GPIO_PORT_SET5_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET5: SETP9 Position      */
+#define GPIO_PORT_SET5_SETP9_Msk                              (0x01UL << GPIO_PORT_SET5_SETP9_Pos)                      /*!< GPIO_PORT SET5: SETP9 Mask          */
+#define GPIO_PORT_SET5_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET5: SETP10 Position     */
+#define GPIO_PORT_SET5_SETP10_Msk                             (0x01UL << GPIO_PORT_SET5_SETP10_Pos)                     /*!< GPIO_PORT SET5: SETP10 Mask         */
+#define GPIO_PORT_SET5_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET5: SETP11 Position     */
+#define GPIO_PORT_SET5_SETP11_Msk                             (0x01UL << GPIO_PORT_SET5_SETP11_Pos)                     /*!< GPIO_PORT SET5: SETP11 Mask         */
+#define GPIO_PORT_SET5_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET5: SETP12 Position     */
+#define GPIO_PORT_SET5_SETP12_Msk                             (0x01UL << GPIO_PORT_SET5_SETP12_Pos)                     /*!< GPIO_PORT SET5: SETP12 Mask         */
+#define GPIO_PORT_SET5_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET5: SETP13 Position     */
+#define GPIO_PORT_SET5_SETP13_Msk                             (0x01UL << GPIO_PORT_SET5_SETP13_Pos)                     /*!< GPIO_PORT SET5: SETP13 Mask         */
+#define GPIO_PORT_SET5_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET5: SETP14 Position     */
+#define GPIO_PORT_SET5_SETP14_Msk                             (0x01UL << GPIO_PORT_SET5_SETP14_Pos)                     /*!< GPIO_PORT SET5: SETP14 Mask         */
+#define GPIO_PORT_SET5_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET5: SETP15 Position     */
+#define GPIO_PORT_SET5_SETP15_Msk                             (0x01UL << GPIO_PORT_SET5_SETP15_Pos)                     /*!< GPIO_PORT SET5: SETP15 Mask         */
+#define GPIO_PORT_SET5_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET5: SETP16 Position     */
+#define GPIO_PORT_SET5_SETP16_Msk                             (0x01UL << GPIO_PORT_SET5_SETP16_Pos)                     /*!< GPIO_PORT SET5: SETP16 Mask         */
+#define GPIO_PORT_SET5_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET5: SETP17 Position     */
+#define GPIO_PORT_SET5_SETP17_Msk                             (0x01UL << GPIO_PORT_SET5_SETP17_Pos)                     /*!< GPIO_PORT SET5: SETP17 Mask         */
+#define GPIO_PORT_SET5_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET5: SETP18 Position     */
+#define GPIO_PORT_SET5_SETP18_Msk                             (0x01UL << GPIO_PORT_SET5_SETP18_Pos)                     /*!< GPIO_PORT SET5: SETP18 Mask         */
+#define GPIO_PORT_SET5_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET5: SETP19 Position     */
+#define GPIO_PORT_SET5_SETP19_Msk                             (0x01UL << GPIO_PORT_SET5_SETP19_Pos)                     /*!< GPIO_PORT SET5: SETP19 Mask         */
+#define GPIO_PORT_SET5_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET5: SETP20 Position     */
+#define GPIO_PORT_SET5_SETP20_Msk                             (0x01UL << GPIO_PORT_SET5_SETP20_Pos)                     /*!< GPIO_PORT SET5: SETP20 Mask         */
+#define GPIO_PORT_SET5_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET5: SETP21 Position     */
+#define GPIO_PORT_SET5_SETP21_Msk                             (0x01UL << GPIO_PORT_SET5_SETP21_Pos)                     /*!< GPIO_PORT SET5: SETP21 Mask         */
+#define GPIO_PORT_SET5_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET5: SETP22 Position     */
+#define GPIO_PORT_SET5_SETP22_Msk                             (0x01UL << GPIO_PORT_SET5_SETP22_Pos)                     /*!< GPIO_PORT SET5: SETP22 Mask         */
+#define GPIO_PORT_SET5_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET5: SETP23 Position     */
+#define GPIO_PORT_SET5_SETP23_Msk                             (0x01UL << GPIO_PORT_SET5_SETP23_Pos)                     /*!< GPIO_PORT SET5: SETP23 Mask         */
+#define GPIO_PORT_SET5_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET5: SETP24 Position     */
+#define GPIO_PORT_SET5_SETP24_Msk                             (0x01UL << GPIO_PORT_SET5_SETP24_Pos)                     /*!< GPIO_PORT SET5: SETP24 Mask         */
+#define GPIO_PORT_SET5_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET5: SETP25 Position     */
+#define GPIO_PORT_SET5_SETP25_Msk                             (0x01UL << GPIO_PORT_SET5_SETP25_Pos)                     /*!< GPIO_PORT SET5: SETP25 Mask         */
+#define GPIO_PORT_SET5_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET5: SETP26 Position     */
+#define GPIO_PORT_SET5_SETP26_Msk                             (0x01UL << GPIO_PORT_SET5_SETP26_Pos)                     /*!< GPIO_PORT SET5: SETP26 Mask         */
+#define GPIO_PORT_SET5_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET5: SETP27 Position     */
+#define GPIO_PORT_SET5_SETP27_Msk                             (0x01UL << GPIO_PORT_SET5_SETP27_Pos)                     /*!< GPIO_PORT SET5: SETP27 Mask         */
+#define GPIO_PORT_SET5_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET5: SETP28 Position     */
+#define GPIO_PORT_SET5_SETP28_Msk                             (0x01UL << GPIO_PORT_SET5_SETP28_Pos)                     /*!< GPIO_PORT SET5: SETP28 Mask         */
+#define GPIO_PORT_SET5_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET5: SETP29 Position     */
+#define GPIO_PORT_SET5_SETP29_Msk                             (0x01UL << GPIO_PORT_SET5_SETP29_Pos)                     /*!< GPIO_PORT SET5: SETP29 Mask         */
+#define GPIO_PORT_SET5_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET5: SETP30 Position     */
+#define GPIO_PORT_SET5_SETP30_Msk                             (0x01UL << GPIO_PORT_SET5_SETP30_Pos)                     /*!< GPIO_PORT SET5: SETP30 Mask         */
+#define GPIO_PORT_SET5_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET5: SETP31 Position     */
+#define GPIO_PORT_SET5_SETP31_Msk                             (0x01UL << GPIO_PORT_SET5_SETP31_Pos)                     /*!< GPIO_PORT SET5: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET6  -----------------------------------------
+#define GPIO_PORT_SET6_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET6: SETP0 Position      */
+#define GPIO_PORT_SET6_SETP0_Msk                              (0x01UL << GPIO_PORT_SET6_SETP0_Pos)                      /*!< GPIO_PORT SET6: SETP0 Mask          */
+#define GPIO_PORT_SET6_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET6: SETP1 Position      */
+#define GPIO_PORT_SET6_SETP1_Msk                              (0x01UL << GPIO_PORT_SET6_SETP1_Pos)                      /*!< GPIO_PORT SET6: SETP1 Mask          */
+#define GPIO_PORT_SET6_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET6: SETP2 Position      */
+#define GPIO_PORT_SET6_SETP2_Msk                              (0x01UL << GPIO_PORT_SET6_SETP2_Pos)                      /*!< GPIO_PORT SET6: SETP2 Mask          */
+#define GPIO_PORT_SET6_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET6: SETP3 Position      */
+#define GPIO_PORT_SET6_SETP3_Msk                              (0x01UL << GPIO_PORT_SET6_SETP3_Pos)                      /*!< GPIO_PORT SET6: SETP3 Mask          */
+#define GPIO_PORT_SET6_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET6: SETP4 Position      */
+#define GPIO_PORT_SET6_SETP4_Msk                              (0x01UL << GPIO_PORT_SET6_SETP4_Pos)                      /*!< GPIO_PORT SET6: SETP4 Mask          */
+#define GPIO_PORT_SET6_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET6: SETP5 Position      */
+#define GPIO_PORT_SET6_SETP5_Msk                              (0x01UL << GPIO_PORT_SET6_SETP5_Pos)                      /*!< GPIO_PORT SET6: SETP5 Mask          */
+#define GPIO_PORT_SET6_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET6: SETP6 Position      */
+#define GPIO_PORT_SET6_SETP6_Msk                              (0x01UL << GPIO_PORT_SET6_SETP6_Pos)                      /*!< GPIO_PORT SET6: SETP6 Mask          */
+#define GPIO_PORT_SET6_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET6: SETP7 Position      */
+#define GPIO_PORT_SET6_SETP7_Msk                              (0x01UL << GPIO_PORT_SET6_SETP7_Pos)                      /*!< GPIO_PORT SET6: SETP7 Mask          */
+#define GPIO_PORT_SET6_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET6: SETP8 Position      */
+#define GPIO_PORT_SET6_SETP8_Msk                              (0x01UL << GPIO_PORT_SET6_SETP8_Pos)                      /*!< GPIO_PORT SET6: SETP8 Mask          */
+#define GPIO_PORT_SET6_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET6: SETP9 Position      */
+#define GPIO_PORT_SET6_SETP9_Msk                              (0x01UL << GPIO_PORT_SET6_SETP9_Pos)                      /*!< GPIO_PORT SET6: SETP9 Mask          */
+#define GPIO_PORT_SET6_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET6: SETP10 Position     */
+#define GPIO_PORT_SET6_SETP10_Msk                             (0x01UL << GPIO_PORT_SET6_SETP10_Pos)                     /*!< GPIO_PORT SET6: SETP10 Mask         */
+#define GPIO_PORT_SET6_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET6: SETP11 Position     */
+#define GPIO_PORT_SET6_SETP11_Msk                             (0x01UL << GPIO_PORT_SET6_SETP11_Pos)                     /*!< GPIO_PORT SET6: SETP11 Mask         */
+#define GPIO_PORT_SET6_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET6: SETP12 Position     */
+#define GPIO_PORT_SET6_SETP12_Msk                             (0x01UL << GPIO_PORT_SET6_SETP12_Pos)                     /*!< GPIO_PORT SET6: SETP12 Mask         */
+#define GPIO_PORT_SET6_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET6: SETP13 Position     */
+#define GPIO_PORT_SET6_SETP13_Msk                             (0x01UL << GPIO_PORT_SET6_SETP13_Pos)                     /*!< GPIO_PORT SET6: SETP13 Mask         */
+#define GPIO_PORT_SET6_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET6: SETP14 Position     */
+#define GPIO_PORT_SET6_SETP14_Msk                             (0x01UL << GPIO_PORT_SET6_SETP14_Pos)                     /*!< GPIO_PORT SET6: SETP14 Mask         */
+#define GPIO_PORT_SET6_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET6: SETP15 Position     */
+#define GPIO_PORT_SET6_SETP15_Msk                             (0x01UL << GPIO_PORT_SET6_SETP15_Pos)                     /*!< GPIO_PORT SET6: SETP15 Mask         */
+#define GPIO_PORT_SET6_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET6: SETP16 Position     */
+#define GPIO_PORT_SET6_SETP16_Msk                             (0x01UL << GPIO_PORT_SET6_SETP16_Pos)                     /*!< GPIO_PORT SET6: SETP16 Mask         */
+#define GPIO_PORT_SET6_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET6: SETP17 Position     */
+#define GPIO_PORT_SET6_SETP17_Msk                             (0x01UL << GPIO_PORT_SET6_SETP17_Pos)                     /*!< GPIO_PORT SET6: SETP17 Mask         */
+#define GPIO_PORT_SET6_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET6: SETP18 Position     */
+#define GPIO_PORT_SET6_SETP18_Msk                             (0x01UL << GPIO_PORT_SET6_SETP18_Pos)                     /*!< GPIO_PORT SET6: SETP18 Mask         */
+#define GPIO_PORT_SET6_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET6: SETP19 Position     */
+#define GPIO_PORT_SET6_SETP19_Msk                             (0x01UL << GPIO_PORT_SET6_SETP19_Pos)                     /*!< GPIO_PORT SET6: SETP19 Mask         */
+#define GPIO_PORT_SET6_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET6: SETP20 Position     */
+#define GPIO_PORT_SET6_SETP20_Msk                             (0x01UL << GPIO_PORT_SET6_SETP20_Pos)                     /*!< GPIO_PORT SET6: SETP20 Mask         */
+#define GPIO_PORT_SET6_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET6: SETP21 Position     */
+#define GPIO_PORT_SET6_SETP21_Msk                             (0x01UL << GPIO_PORT_SET6_SETP21_Pos)                     /*!< GPIO_PORT SET6: SETP21 Mask         */
+#define GPIO_PORT_SET6_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET6: SETP22 Position     */
+#define GPIO_PORT_SET6_SETP22_Msk                             (0x01UL << GPIO_PORT_SET6_SETP22_Pos)                     /*!< GPIO_PORT SET6: SETP22 Mask         */
+#define GPIO_PORT_SET6_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET6: SETP23 Position     */
+#define GPIO_PORT_SET6_SETP23_Msk                             (0x01UL << GPIO_PORT_SET6_SETP23_Pos)                     /*!< GPIO_PORT SET6: SETP23 Mask         */
+#define GPIO_PORT_SET6_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET6: SETP24 Position     */
+#define GPIO_PORT_SET6_SETP24_Msk                             (0x01UL << GPIO_PORT_SET6_SETP24_Pos)                     /*!< GPIO_PORT SET6: SETP24 Mask         */
+#define GPIO_PORT_SET6_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET6: SETP25 Position     */
+#define GPIO_PORT_SET6_SETP25_Msk                             (0x01UL << GPIO_PORT_SET6_SETP25_Pos)                     /*!< GPIO_PORT SET6: SETP25 Mask         */
+#define GPIO_PORT_SET6_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET6: SETP26 Position     */
+#define GPIO_PORT_SET6_SETP26_Msk                             (0x01UL << GPIO_PORT_SET6_SETP26_Pos)                     /*!< GPIO_PORT SET6: SETP26 Mask         */
+#define GPIO_PORT_SET6_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET6: SETP27 Position     */
+#define GPIO_PORT_SET6_SETP27_Msk                             (0x01UL << GPIO_PORT_SET6_SETP27_Pos)                     /*!< GPIO_PORT SET6: SETP27 Mask         */
+#define GPIO_PORT_SET6_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET6: SETP28 Position     */
+#define GPIO_PORT_SET6_SETP28_Msk                             (0x01UL << GPIO_PORT_SET6_SETP28_Pos)                     /*!< GPIO_PORT SET6: SETP28 Mask         */
+#define GPIO_PORT_SET6_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET6: SETP29 Position     */
+#define GPIO_PORT_SET6_SETP29_Msk                             (0x01UL << GPIO_PORT_SET6_SETP29_Pos)                     /*!< GPIO_PORT SET6: SETP29 Mask         */
+#define GPIO_PORT_SET6_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET6: SETP30 Position     */
+#define GPIO_PORT_SET6_SETP30_Msk                             (0x01UL << GPIO_PORT_SET6_SETP30_Pos)                     /*!< GPIO_PORT SET6: SETP30 Mask         */
+#define GPIO_PORT_SET6_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET6: SETP31 Position     */
+#define GPIO_PORT_SET6_SETP31_Msk                             (0x01UL << GPIO_PORT_SET6_SETP31_Pos)                     /*!< GPIO_PORT SET6: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET7  -----------------------------------------
+#define GPIO_PORT_SET7_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET7: SETP0 Position      */
+#define GPIO_PORT_SET7_SETP0_Msk                              (0x01UL << GPIO_PORT_SET7_SETP0_Pos)                      /*!< GPIO_PORT SET7: SETP0 Mask          */
+#define GPIO_PORT_SET7_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET7: SETP1 Position      */
+#define GPIO_PORT_SET7_SETP1_Msk                              (0x01UL << GPIO_PORT_SET7_SETP1_Pos)                      /*!< GPIO_PORT SET7: SETP1 Mask          */
+#define GPIO_PORT_SET7_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET7: SETP2 Position      */
+#define GPIO_PORT_SET7_SETP2_Msk                              (0x01UL << GPIO_PORT_SET7_SETP2_Pos)                      /*!< GPIO_PORT SET7: SETP2 Mask          */
+#define GPIO_PORT_SET7_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET7: SETP3 Position      */
+#define GPIO_PORT_SET7_SETP3_Msk                              (0x01UL << GPIO_PORT_SET7_SETP3_Pos)                      /*!< GPIO_PORT SET7: SETP3 Mask          */
+#define GPIO_PORT_SET7_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET7: SETP4 Position      */
+#define GPIO_PORT_SET7_SETP4_Msk                              (0x01UL << GPIO_PORT_SET7_SETP4_Pos)                      /*!< GPIO_PORT SET7: SETP4 Mask          */
+#define GPIO_PORT_SET7_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET7: SETP5 Position      */
+#define GPIO_PORT_SET7_SETP5_Msk                              (0x01UL << GPIO_PORT_SET7_SETP5_Pos)                      /*!< GPIO_PORT SET7: SETP5 Mask          */
+#define GPIO_PORT_SET7_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET7: SETP6 Position      */
+#define GPIO_PORT_SET7_SETP6_Msk                              (0x01UL << GPIO_PORT_SET7_SETP6_Pos)                      /*!< GPIO_PORT SET7: SETP6 Mask          */
+#define GPIO_PORT_SET7_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET7: SETP7 Position      */
+#define GPIO_PORT_SET7_SETP7_Msk                              (0x01UL << GPIO_PORT_SET7_SETP7_Pos)                      /*!< GPIO_PORT SET7: SETP7 Mask          */
+#define GPIO_PORT_SET7_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET7: SETP8 Position      */
+#define GPIO_PORT_SET7_SETP8_Msk                              (0x01UL << GPIO_PORT_SET7_SETP8_Pos)                      /*!< GPIO_PORT SET7: SETP8 Mask          */
+#define GPIO_PORT_SET7_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET7: SETP9 Position      */
+#define GPIO_PORT_SET7_SETP9_Msk                              (0x01UL << GPIO_PORT_SET7_SETP9_Pos)                      /*!< GPIO_PORT SET7: SETP9 Mask          */
+#define GPIO_PORT_SET7_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET7: SETP10 Position     */
+#define GPIO_PORT_SET7_SETP10_Msk                             (0x01UL << GPIO_PORT_SET7_SETP10_Pos)                     /*!< GPIO_PORT SET7: SETP10 Mask         */
+#define GPIO_PORT_SET7_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET7: SETP11 Position     */
+#define GPIO_PORT_SET7_SETP11_Msk                             (0x01UL << GPIO_PORT_SET7_SETP11_Pos)                     /*!< GPIO_PORT SET7: SETP11 Mask         */
+#define GPIO_PORT_SET7_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET7: SETP12 Position     */
+#define GPIO_PORT_SET7_SETP12_Msk                             (0x01UL << GPIO_PORT_SET7_SETP12_Pos)                     /*!< GPIO_PORT SET7: SETP12 Mask         */
+#define GPIO_PORT_SET7_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET7: SETP13 Position     */
+#define GPIO_PORT_SET7_SETP13_Msk                             (0x01UL << GPIO_PORT_SET7_SETP13_Pos)                     /*!< GPIO_PORT SET7: SETP13 Mask         */
+#define GPIO_PORT_SET7_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET7: SETP14 Position     */
+#define GPIO_PORT_SET7_SETP14_Msk                             (0x01UL << GPIO_PORT_SET7_SETP14_Pos)                     /*!< GPIO_PORT SET7: SETP14 Mask         */
+#define GPIO_PORT_SET7_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET7: SETP15 Position     */
+#define GPIO_PORT_SET7_SETP15_Msk                             (0x01UL << GPIO_PORT_SET7_SETP15_Pos)                     /*!< GPIO_PORT SET7: SETP15 Mask         */
+#define GPIO_PORT_SET7_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET7: SETP16 Position     */
+#define GPIO_PORT_SET7_SETP16_Msk                             (0x01UL << GPIO_PORT_SET7_SETP16_Pos)                     /*!< GPIO_PORT SET7: SETP16 Mask         */
+#define GPIO_PORT_SET7_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET7: SETP17 Position     */
+#define GPIO_PORT_SET7_SETP17_Msk                             (0x01UL << GPIO_PORT_SET7_SETP17_Pos)                     /*!< GPIO_PORT SET7: SETP17 Mask         */
+#define GPIO_PORT_SET7_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET7: SETP18 Position     */
+#define GPIO_PORT_SET7_SETP18_Msk                             (0x01UL << GPIO_PORT_SET7_SETP18_Pos)                     /*!< GPIO_PORT SET7: SETP18 Mask         */
+#define GPIO_PORT_SET7_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET7: SETP19 Position     */
+#define GPIO_PORT_SET7_SETP19_Msk                             (0x01UL << GPIO_PORT_SET7_SETP19_Pos)                     /*!< GPIO_PORT SET7: SETP19 Mask         */
+#define GPIO_PORT_SET7_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET7: SETP20 Position     */
+#define GPIO_PORT_SET7_SETP20_Msk                             (0x01UL << GPIO_PORT_SET7_SETP20_Pos)                     /*!< GPIO_PORT SET7: SETP20 Mask         */
+#define GPIO_PORT_SET7_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET7: SETP21 Position     */
+#define GPIO_PORT_SET7_SETP21_Msk                             (0x01UL << GPIO_PORT_SET7_SETP21_Pos)                     /*!< GPIO_PORT SET7: SETP21 Mask         */
+#define GPIO_PORT_SET7_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET7: SETP22 Position     */
+#define GPIO_PORT_SET7_SETP22_Msk                             (0x01UL << GPIO_PORT_SET7_SETP22_Pos)                     /*!< GPIO_PORT SET7: SETP22 Mask         */
+#define GPIO_PORT_SET7_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET7: SETP23 Position     */
+#define GPIO_PORT_SET7_SETP23_Msk                             (0x01UL << GPIO_PORT_SET7_SETP23_Pos)                     /*!< GPIO_PORT SET7: SETP23 Mask         */
+#define GPIO_PORT_SET7_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET7: SETP24 Position     */
+#define GPIO_PORT_SET7_SETP24_Msk                             (0x01UL << GPIO_PORT_SET7_SETP24_Pos)                     /*!< GPIO_PORT SET7: SETP24 Mask         */
+#define GPIO_PORT_SET7_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET7: SETP25 Position     */
+#define GPIO_PORT_SET7_SETP25_Msk                             (0x01UL << GPIO_PORT_SET7_SETP25_Pos)                     /*!< GPIO_PORT SET7: SETP25 Mask         */
+#define GPIO_PORT_SET7_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET7: SETP26 Position     */
+#define GPIO_PORT_SET7_SETP26_Msk                             (0x01UL << GPIO_PORT_SET7_SETP26_Pos)                     /*!< GPIO_PORT SET7: SETP26 Mask         */
+#define GPIO_PORT_SET7_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET7: SETP27 Position     */
+#define GPIO_PORT_SET7_SETP27_Msk                             (0x01UL << GPIO_PORT_SET7_SETP27_Pos)                     /*!< GPIO_PORT SET7: SETP27 Mask         */
+#define GPIO_PORT_SET7_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET7: SETP28 Position     */
+#define GPIO_PORT_SET7_SETP28_Msk                             (0x01UL << GPIO_PORT_SET7_SETP28_Pos)                     /*!< GPIO_PORT SET7: SETP28 Mask         */
+#define GPIO_PORT_SET7_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET7: SETP29 Position     */
+#define GPIO_PORT_SET7_SETP29_Msk                             (0x01UL << GPIO_PORT_SET7_SETP29_Pos)                     /*!< GPIO_PORT SET7: SETP29 Mask         */
+#define GPIO_PORT_SET7_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET7: SETP30 Position     */
+#define GPIO_PORT_SET7_SETP30_Msk                             (0x01UL << GPIO_PORT_SET7_SETP30_Pos)                     /*!< GPIO_PORT SET7: SETP30 Mask         */
+#define GPIO_PORT_SET7_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET7: SETP31 Position     */
+#define GPIO_PORT_SET7_SETP31_Msk                             (0x01UL << GPIO_PORT_SET7_SETP31_Pos)                     /*!< GPIO_PORT SET7: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_CLR0  -----------------------------------------
+#define GPIO_PORT_CLR0_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR0: CLRP00 Position     */
+#define GPIO_PORT_CLR0_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos)                     /*!< GPIO_PORT CLR0: CLRP00 Mask         */
+#define GPIO_PORT_CLR0_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR0: CLRP01 Position     */
+#define GPIO_PORT_CLR0_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos)                     /*!< GPIO_PORT CLR0: CLRP01 Mask         */
+#define GPIO_PORT_CLR0_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR0: CLRP02 Position     */
+#define GPIO_PORT_CLR0_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos)                     /*!< GPIO_PORT CLR0: CLRP02 Mask         */
+#define GPIO_PORT_CLR0_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR0: CLRP03 Position     */
+#define GPIO_PORT_CLR0_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos)                     /*!< GPIO_PORT CLR0: CLRP03 Mask         */
+#define GPIO_PORT_CLR0_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR0: CLRP04 Position     */
+#define GPIO_PORT_CLR0_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos)                     /*!< GPIO_PORT CLR0: CLRP04 Mask         */
+#define GPIO_PORT_CLR0_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR0: CLRP05 Position     */
+#define GPIO_PORT_CLR0_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos)                     /*!< GPIO_PORT CLR0: CLRP05 Mask         */
+#define GPIO_PORT_CLR0_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR0: CLRP06 Position     */
+#define GPIO_PORT_CLR0_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos)                     /*!< GPIO_PORT CLR0: CLRP06 Mask         */
+#define GPIO_PORT_CLR0_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR0: CLRP07 Position     */
+#define GPIO_PORT_CLR0_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos)                     /*!< GPIO_PORT CLR0: CLRP07 Mask         */
+#define GPIO_PORT_CLR0_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR0: CLRP08 Position     */
+#define GPIO_PORT_CLR0_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos)                     /*!< GPIO_PORT CLR0: CLRP08 Mask         */
+#define GPIO_PORT_CLR0_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR0: CLRP09 Position     */
+#define GPIO_PORT_CLR0_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos)                     /*!< GPIO_PORT CLR0: CLRP09 Mask         */
+#define GPIO_PORT_CLR0_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR0: CLRP010 Position    */
+#define GPIO_PORT_CLR0_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos)                    /*!< GPIO_PORT CLR0: CLRP010 Mask        */
+#define GPIO_PORT_CLR0_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR0: CLRP011 Position    */
+#define GPIO_PORT_CLR0_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos)                    /*!< GPIO_PORT CLR0: CLRP011 Mask        */
+#define GPIO_PORT_CLR0_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR0: CLRP012 Position    */
+#define GPIO_PORT_CLR0_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos)                    /*!< GPIO_PORT CLR0: CLRP012 Mask        */
+#define GPIO_PORT_CLR0_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR0: CLRP013 Position    */
+#define GPIO_PORT_CLR0_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos)                    /*!< GPIO_PORT CLR0: CLRP013 Mask        */
+#define GPIO_PORT_CLR0_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR0: CLRP014 Position    */
+#define GPIO_PORT_CLR0_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos)                    /*!< GPIO_PORT CLR0: CLRP014 Mask        */
+#define GPIO_PORT_CLR0_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR0: CLRP015 Position    */
+#define GPIO_PORT_CLR0_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos)                    /*!< GPIO_PORT CLR0: CLRP015 Mask        */
+#define GPIO_PORT_CLR0_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR0: CLRP016 Position    */
+#define GPIO_PORT_CLR0_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos)                    /*!< GPIO_PORT CLR0: CLRP016 Mask        */
+#define GPIO_PORT_CLR0_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR0: CLRP017 Position    */
+#define GPIO_PORT_CLR0_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos)                    /*!< GPIO_PORT CLR0: CLRP017 Mask        */
+#define GPIO_PORT_CLR0_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR0: CLRP018 Position    */
+#define GPIO_PORT_CLR0_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos)                    /*!< GPIO_PORT CLR0: CLRP018 Mask        */
+#define GPIO_PORT_CLR0_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR0: CLRP019 Position    */
+#define GPIO_PORT_CLR0_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos)                    /*!< GPIO_PORT CLR0: CLRP019 Mask        */
+#define GPIO_PORT_CLR0_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR0: CLRP020 Position    */
+#define GPIO_PORT_CLR0_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos)                    /*!< GPIO_PORT CLR0: CLRP020 Mask        */
+#define GPIO_PORT_CLR0_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR0: CLRP021 Position    */
+#define GPIO_PORT_CLR0_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos)                    /*!< GPIO_PORT CLR0: CLRP021 Mask        */
+#define GPIO_PORT_CLR0_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR0: CLRP022 Position    */
+#define GPIO_PORT_CLR0_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos)                    /*!< GPIO_PORT CLR0: CLRP022 Mask        */
+#define GPIO_PORT_CLR0_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR0: CLRP023 Position    */
+#define GPIO_PORT_CLR0_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos)                    /*!< GPIO_PORT CLR0: CLRP023 Mask        */
+#define GPIO_PORT_CLR0_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR0: CLRP024 Position    */
+#define GPIO_PORT_CLR0_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos)                    /*!< GPIO_PORT CLR0: CLRP024 Mask        */
+#define GPIO_PORT_CLR0_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR0: CLRP025 Position    */
+#define GPIO_PORT_CLR0_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos)                    /*!< GPIO_PORT CLR0: CLRP025 Mask        */
+#define GPIO_PORT_CLR0_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR0: CLRP026 Position    */
+#define GPIO_PORT_CLR0_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos)                    /*!< GPIO_PORT CLR0: CLRP026 Mask        */
+#define GPIO_PORT_CLR0_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR0: CLRP027 Position    */
+#define GPIO_PORT_CLR0_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos)                    /*!< GPIO_PORT CLR0: CLRP027 Mask        */
+#define GPIO_PORT_CLR0_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR0: CLRP028 Position    */
+#define GPIO_PORT_CLR0_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos)                    /*!< GPIO_PORT CLR0: CLRP028 Mask        */
+#define GPIO_PORT_CLR0_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR0: CLRP029 Position    */
+#define GPIO_PORT_CLR0_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos)                    /*!< GPIO_PORT CLR0: CLRP029 Mask        */
+#define GPIO_PORT_CLR0_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR0: CLRP030 Position    */
+#define GPIO_PORT_CLR0_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos)                    /*!< GPIO_PORT CLR0: CLRP030 Mask        */
+#define GPIO_PORT_CLR0_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR0: CLRP031 Position    */
+#define GPIO_PORT_CLR0_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos)                    /*!< GPIO_PORT CLR0: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR1  -----------------------------------------
+#define GPIO_PORT_CLR1_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR1: CLRP00 Position     */
+#define GPIO_PORT_CLR1_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos)                     /*!< GPIO_PORT CLR1: CLRP00 Mask         */
+#define GPIO_PORT_CLR1_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR1: CLRP01 Position     */
+#define GPIO_PORT_CLR1_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos)                     /*!< GPIO_PORT CLR1: CLRP01 Mask         */
+#define GPIO_PORT_CLR1_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR1: CLRP02 Position     */
+#define GPIO_PORT_CLR1_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos)                     /*!< GPIO_PORT CLR1: CLRP02 Mask         */
+#define GPIO_PORT_CLR1_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR1: CLRP03 Position     */
+#define GPIO_PORT_CLR1_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos)                     /*!< GPIO_PORT CLR1: CLRP03 Mask         */
+#define GPIO_PORT_CLR1_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR1: CLRP04 Position     */
+#define GPIO_PORT_CLR1_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos)                     /*!< GPIO_PORT CLR1: CLRP04 Mask         */
+#define GPIO_PORT_CLR1_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR1: CLRP05 Position     */
+#define GPIO_PORT_CLR1_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos)                     /*!< GPIO_PORT CLR1: CLRP05 Mask         */
+#define GPIO_PORT_CLR1_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR1: CLRP06 Position     */
+#define GPIO_PORT_CLR1_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos)                     /*!< GPIO_PORT CLR1: CLRP06 Mask         */
+#define GPIO_PORT_CLR1_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR1: CLRP07 Position     */
+#define GPIO_PORT_CLR1_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos)                     /*!< GPIO_PORT CLR1: CLRP07 Mask         */
+#define GPIO_PORT_CLR1_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR1: CLRP08 Position     */
+#define GPIO_PORT_CLR1_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos)                     /*!< GPIO_PORT CLR1: CLRP08 Mask         */
+#define GPIO_PORT_CLR1_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR1: CLRP09 Position     */
+#define GPIO_PORT_CLR1_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos)                     /*!< GPIO_PORT CLR1: CLRP09 Mask         */
+#define GPIO_PORT_CLR1_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR1: CLRP010 Position    */
+#define GPIO_PORT_CLR1_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos)                    /*!< GPIO_PORT CLR1: CLRP010 Mask        */
+#define GPIO_PORT_CLR1_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR1: CLRP011 Position    */
+#define GPIO_PORT_CLR1_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos)                    /*!< GPIO_PORT CLR1: CLRP011 Mask        */
+#define GPIO_PORT_CLR1_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR1: CLRP012 Position    */
+#define GPIO_PORT_CLR1_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos)                    /*!< GPIO_PORT CLR1: CLRP012 Mask        */
+#define GPIO_PORT_CLR1_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR1: CLRP013 Position    */
+#define GPIO_PORT_CLR1_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos)                    /*!< GPIO_PORT CLR1: CLRP013 Mask        */
+#define GPIO_PORT_CLR1_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR1: CLRP014 Position    */
+#define GPIO_PORT_CLR1_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos)                    /*!< GPIO_PORT CLR1: CLRP014 Mask        */
+#define GPIO_PORT_CLR1_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR1: CLRP015 Position    */
+#define GPIO_PORT_CLR1_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos)                    /*!< GPIO_PORT CLR1: CLRP015 Mask        */
+#define GPIO_PORT_CLR1_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR1: CLRP016 Position    */
+#define GPIO_PORT_CLR1_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos)                    /*!< GPIO_PORT CLR1: CLRP016 Mask        */
+#define GPIO_PORT_CLR1_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR1: CLRP017 Position    */
+#define GPIO_PORT_CLR1_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos)                    /*!< GPIO_PORT CLR1: CLRP017 Mask        */
+#define GPIO_PORT_CLR1_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR1: CLRP018 Position    */
+#define GPIO_PORT_CLR1_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos)                    /*!< GPIO_PORT CLR1: CLRP018 Mask        */
+#define GPIO_PORT_CLR1_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR1: CLRP019 Position    */
+#define GPIO_PORT_CLR1_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos)                    /*!< GPIO_PORT CLR1: CLRP019 Mask        */
+#define GPIO_PORT_CLR1_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR1: CLRP020 Position    */
+#define GPIO_PORT_CLR1_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos)                    /*!< GPIO_PORT CLR1: CLRP020 Mask        */
+#define GPIO_PORT_CLR1_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR1: CLRP021 Position    */
+#define GPIO_PORT_CLR1_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos)                    /*!< GPIO_PORT CLR1: CLRP021 Mask        */
+#define GPIO_PORT_CLR1_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR1: CLRP022 Position    */
+#define GPIO_PORT_CLR1_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos)                    /*!< GPIO_PORT CLR1: CLRP022 Mask        */
+#define GPIO_PORT_CLR1_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR1: CLRP023 Position    */
+#define GPIO_PORT_CLR1_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos)                    /*!< GPIO_PORT CLR1: CLRP023 Mask        */
+#define GPIO_PORT_CLR1_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR1: CLRP024 Position    */
+#define GPIO_PORT_CLR1_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos)                    /*!< GPIO_PORT CLR1: CLRP024 Mask        */
+#define GPIO_PORT_CLR1_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR1: CLRP025 Position    */
+#define GPIO_PORT_CLR1_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos)                    /*!< GPIO_PORT CLR1: CLRP025 Mask        */
+#define GPIO_PORT_CLR1_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR1: CLRP026 Position    */
+#define GPIO_PORT_CLR1_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos)                    /*!< GPIO_PORT CLR1: CLRP026 Mask        */
+#define GPIO_PORT_CLR1_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR1: CLRP027 Position    */
+#define GPIO_PORT_CLR1_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos)                    /*!< GPIO_PORT CLR1: CLRP027 Mask        */
+#define GPIO_PORT_CLR1_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR1: CLRP028 Position    */
+#define GPIO_PORT_CLR1_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos)                    /*!< GPIO_PORT CLR1: CLRP028 Mask        */
+#define GPIO_PORT_CLR1_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR1: CLRP029 Position    */
+#define GPIO_PORT_CLR1_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos)                    /*!< GPIO_PORT CLR1: CLRP029 Mask        */
+#define GPIO_PORT_CLR1_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR1: CLRP030 Position    */
+#define GPIO_PORT_CLR1_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos)                    /*!< GPIO_PORT CLR1: CLRP030 Mask        */
+#define GPIO_PORT_CLR1_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR1: CLRP031 Position    */
+#define GPIO_PORT_CLR1_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos)                    /*!< GPIO_PORT CLR1: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR2  -----------------------------------------
+#define GPIO_PORT_CLR2_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR2: CLRP00 Position     */
+#define GPIO_PORT_CLR2_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos)                     /*!< GPIO_PORT CLR2: CLRP00 Mask         */
+#define GPIO_PORT_CLR2_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR2: CLRP01 Position     */
+#define GPIO_PORT_CLR2_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos)                     /*!< GPIO_PORT CLR2: CLRP01 Mask         */
+#define GPIO_PORT_CLR2_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR2: CLRP02 Position     */
+#define GPIO_PORT_CLR2_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos)                     /*!< GPIO_PORT CLR2: CLRP02 Mask         */
+#define GPIO_PORT_CLR2_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR2: CLRP03 Position     */
+#define GPIO_PORT_CLR2_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos)                     /*!< GPIO_PORT CLR2: CLRP03 Mask         */
+#define GPIO_PORT_CLR2_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR2: CLRP04 Position     */
+#define GPIO_PORT_CLR2_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos)                     /*!< GPIO_PORT CLR2: CLRP04 Mask         */
+#define GPIO_PORT_CLR2_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR2: CLRP05 Position     */
+#define GPIO_PORT_CLR2_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos)                     /*!< GPIO_PORT CLR2: CLRP05 Mask         */
+#define GPIO_PORT_CLR2_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR2: CLRP06 Position     */
+#define GPIO_PORT_CLR2_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos)                     /*!< GPIO_PORT CLR2: CLRP06 Mask         */
+#define GPIO_PORT_CLR2_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR2: CLRP07 Position     */
+#define GPIO_PORT_CLR2_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos)                     /*!< GPIO_PORT CLR2: CLRP07 Mask         */
+#define GPIO_PORT_CLR2_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR2: CLRP08 Position     */
+#define GPIO_PORT_CLR2_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos)                     /*!< GPIO_PORT CLR2: CLRP08 Mask         */
+#define GPIO_PORT_CLR2_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR2: CLRP09 Position     */
+#define GPIO_PORT_CLR2_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos)                     /*!< GPIO_PORT CLR2: CLRP09 Mask         */
+#define GPIO_PORT_CLR2_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR2: CLRP010 Position    */
+#define GPIO_PORT_CLR2_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos)                    /*!< GPIO_PORT CLR2: CLRP010 Mask        */
+#define GPIO_PORT_CLR2_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR2: CLRP011 Position    */
+#define GPIO_PORT_CLR2_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos)                    /*!< GPIO_PORT CLR2: CLRP011 Mask        */
+#define GPIO_PORT_CLR2_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR2: CLRP012 Position    */
+#define GPIO_PORT_CLR2_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos)                    /*!< GPIO_PORT CLR2: CLRP012 Mask        */
+#define GPIO_PORT_CLR2_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR2: CLRP013 Position    */
+#define GPIO_PORT_CLR2_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos)                    /*!< GPIO_PORT CLR2: CLRP013 Mask        */
+#define GPIO_PORT_CLR2_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR2: CLRP014 Position    */
+#define GPIO_PORT_CLR2_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos)                    /*!< GPIO_PORT CLR2: CLRP014 Mask        */
+#define GPIO_PORT_CLR2_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR2: CLRP015 Position    */
+#define GPIO_PORT_CLR2_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos)                    /*!< GPIO_PORT CLR2: CLRP015 Mask        */
+#define GPIO_PORT_CLR2_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR2: CLRP016 Position    */
+#define GPIO_PORT_CLR2_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos)                    /*!< GPIO_PORT CLR2: CLRP016 Mask        */
+#define GPIO_PORT_CLR2_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR2: CLRP017 Position    */
+#define GPIO_PORT_CLR2_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos)                    /*!< GPIO_PORT CLR2: CLRP017 Mask        */
+#define GPIO_PORT_CLR2_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR2: CLRP018 Position    */
+#define GPIO_PORT_CLR2_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos)                    /*!< GPIO_PORT CLR2: CLRP018 Mask        */
+#define GPIO_PORT_CLR2_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR2: CLRP019 Position    */
+#define GPIO_PORT_CLR2_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos)                    /*!< GPIO_PORT CLR2: CLRP019 Mask        */
+#define GPIO_PORT_CLR2_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR2: CLRP020 Position    */
+#define GPIO_PORT_CLR2_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos)                    /*!< GPIO_PORT CLR2: CLRP020 Mask        */
+#define GPIO_PORT_CLR2_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR2: CLRP021 Position    */
+#define GPIO_PORT_CLR2_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos)                    /*!< GPIO_PORT CLR2: CLRP021 Mask        */
+#define GPIO_PORT_CLR2_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR2: CLRP022 Position    */
+#define GPIO_PORT_CLR2_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos)                    /*!< GPIO_PORT CLR2: CLRP022 Mask        */
+#define GPIO_PORT_CLR2_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR2: CLRP023 Position    */
+#define GPIO_PORT_CLR2_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos)                    /*!< GPIO_PORT CLR2: CLRP023 Mask        */
+#define GPIO_PORT_CLR2_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR2: CLRP024 Position    */
+#define GPIO_PORT_CLR2_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos)                    /*!< GPIO_PORT CLR2: CLRP024 Mask        */
+#define GPIO_PORT_CLR2_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR2: CLRP025 Position    */
+#define GPIO_PORT_CLR2_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos)                    /*!< GPIO_PORT CLR2: CLRP025 Mask        */
+#define GPIO_PORT_CLR2_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR2: CLRP026 Position    */
+#define GPIO_PORT_CLR2_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos)                    /*!< GPIO_PORT CLR2: CLRP026 Mask        */
+#define GPIO_PORT_CLR2_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR2: CLRP027 Position    */
+#define GPIO_PORT_CLR2_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos)                    /*!< GPIO_PORT CLR2: CLRP027 Mask        */
+#define GPIO_PORT_CLR2_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR2: CLRP028 Position    */
+#define GPIO_PORT_CLR2_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos)                    /*!< GPIO_PORT CLR2: CLRP028 Mask        */
+#define GPIO_PORT_CLR2_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR2: CLRP029 Position    */
+#define GPIO_PORT_CLR2_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos)                    /*!< GPIO_PORT CLR2: CLRP029 Mask        */
+#define GPIO_PORT_CLR2_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR2: CLRP030 Position    */
+#define GPIO_PORT_CLR2_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos)                    /*!< GPIO_PORT CLR2: CLRP030 Mask        */
+#define GPIO_PORT_CLR2_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR2: CLRP031 Position    */
+#define GPIO_PORT_CLR2_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos)                    /*!< GPIO_PORT CLR2: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR3  -----------------------------------------
+#define GPIO_PORT_CLR3_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR3: CLRP00 Position     */
+#define GPIO_PORT_CLR3_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos)                     /*!< GPIO_PORT CLR3: CLRP00 Mask         */
+#define GPIO_PORT_CLR3_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR3: CLRP01 Position     */
+#define GPIO_PORT_CLR3_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos)                     /*!< GPIO_PORT CLR3: CLRP01 Mask         */
+#define GPIO_PORT_CLR3_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR3: CLRP02 Position     */
+#define GPIO_PORT_CLR3_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos)                     /*!< GPIO_PORT CLR3: CLRP02 Mask         */
+#define GPIO_PORT_CLR3_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR3: CLRP03 Position     */
+#define GPIO_PORT_CLR3_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos)                     /*!< GPIO_PORT CLR3: CLRP03 Mask         */
+#define GPIO_PORT_CLR3_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR3: CLRP04 Position     */
+#define GPIO_PORT_CLR3_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos)                     /*!< GPIO_PORT CLR3: CLRP04 Mask         */
+#define GPIO_PORT_CLR3_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR3: CLRP05 Position     */
+#define GPIO_PORT_CLR3_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos)                     /*!< GPIO_PORT CLR3: CLRP05 Mask         */
+#define GPIO_PORT_CLR3_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR3: CLRP06 Position     */
+#define GPIO_PORT_CLR3_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos)                     /*!< GPIO_PORT CLR3: CLRP06 Mask         */
+#define GPIO_PORT_CLR3_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR3: CLRP07 Position     */
+#define GPIO_PORT_CLR3_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos)                     /*!< GPIO_PORT CLR3: CLRP07 Mask         */
+#define GPIO_PORT_CLR3_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR3: CLRP08 Position     */
+#define GPIO_PORT_CLR3_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos)                     /*!< GPIO_PORT CLR3: CLRP08 Mask         */
+#define GPIO_PORT_CLR3_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR3: CLRP09 Position     */
+#define GPIO_PORT_CLR3_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos)                     /*!< GPIO_PORT CLR3: CLRP09 Mask         */
+#define GPIO_PORT_CLR3_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR3: CLRP010 Position    */
+#define GPIO_PORT_CLR3_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos)                    /*!< GPIO_PORT CLR3: CLRP010 Mask        */
+#define GPIO_PORT_CLR3_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR3: CLRP011 Position    */
+#define GPIO_PORT_CLR3_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos)                    /*!< GPIO_PORT CLR3: CLRP011 Mask        */
+#define GPIO_PORT_CLR3_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR3: CLRP012 Position    */
+#define GPIO_PORT_CLR3_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos)                    /*!< GPIO_PORT CLR3: CLRP012 Mask        */
+#define GPIO_PORT_CLR3_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR3: CLRP013 Position    */
+#define GPIO_PORT_CLR3_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos)                    /*!< GPIO_PORT CLR3: CLRP013 Mask        */
+#define GPIO_PORT_CLR3_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR3: CLRP014 Position    */
+#define GPIO_PORT_CLR3_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos)                    /*!< GPIO_PORT CLR3: CLRP014 Mask        */
+#define GPIO_PORT_CLR3_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR3: CLRP015 Position    */
+#define GPIO_PORT_CLR3_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos)                    /*!< GPIO_PORT CLR3: CLRP015 Mask        */
+#define GPIO_PORT_CLR3_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR3: CLRP016 Position    */
+#define GPIO_PORT_CLR3_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos)                    /*!< GPIO_PORT CLR3: CLRP016 Mask        */
+#define GPIO_PORT_CLR3_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR3: CLRP017 Position    */
+#define GPIO_PORT_CLR3_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos)                    /*!< GPIO_PORT CLR3: CLRP017 Mask        */
+#define GPIO_PORT_CLR3_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR3: CLRP018 Position    */
+#define GPIO_PORT_CLR3_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos)                    /*!< GPIO_PORT CLR3: CLRP018 Mask        */
+#define GPIO_PORT_CLR3_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR3: CLRP019 Position    */
+#define GPIO_PORT_CLR3_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos)                    /*!< GPIO_PORT CLR3: CLRP019 Mask        */
+#define GPIO_PORT_CLR3_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR3: CLRP020 Position    */
+#define GPIO_PORT_CLR3_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos)                    /*!< GPIO_PORT CLR3: CLRP020 Mask        */
+#define GPIO_PORT_CLR3_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR3: CLRP021 Position    */
+#define GPIO_PORT_CLR3_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos)                    /*!< GPIO_PORT CLR3: CLRP021 Mask        */
+#define GPIO_PORT_CLR3_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR3: CLRP022 Position    */
+#define GPIO_PORT_CLR3_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos)                    /*!< GPIO_PORT CLR3: CLRP022 Mask        */
+#define GPIO_PORT_CLR3_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR3: CLRP023 Position    */
+#define GPIO_PORT_CLR3_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos)                    /*!< GPIO_PORT CLR3: CLRP023 Mask        */
+#define GPIO_PORT_CLR3_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR3: CLRP024 Position    */
+#define GPIO_PORT_CLR3_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos)                    /*!< GPIO_PORT CLR3: CLRP024 Mask        */
+#define GPIO_PORT_CLR3_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR3: CLRP025 Position    */
+#define GPIO_PORT_CLR3_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos)                    /*!< GPIO_PORT CLR3: CLRP025 Mask        */
+#define GPIO_PORT_CLR3_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR3: CLRP026 Position    */
+#define GPIO_PORT_CLR3_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos)                    /*!< GPIO_PORT CLR3: CLRP026 Mask        */
+#define GPIO_PORT_CLR3_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR3: CLRP027 Position    */
+#define GPIO_PORT_CLR3_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos)                    /*!< GPIO_PORT CLR3: CLRP027 Mask        */
+#define GPIO_PORT_CLR3_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR3: CLRP028 Position    */
+#define GPIO_PORT_CLR3_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos)                    /*!< GPIO_PORT CLR3: CLRP028 Mask        */
+#define GPIO_PORT_CLR3_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR3: CLRP029 Position    */
+#define GPIO_PORT_CLR3_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos)                    /*!< GPIO_PORT CLR3: CLRP029 Mask        */
+#define GPIO_PORT_CLR3_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR3: CLRP030 Position    */
+#define GPIO_PORT_CLR3_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos)                    /*!< GPIO_PORT CLR3: CLRP030 Mask        */
+#define GPIO_PORT_CLR3_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR3: CLRP031 Position    */
+#define GPIO_PORT_CLR3_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos)                    /*!< GPIO_PORT CLR3: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR4  -----------------------------------------
+#define GPIO_PORT_CLR4_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR4: CLRP00 Position     */
+#define GPIO_PORT_CLR4_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos)                     /*!< GPIO_PORT CLR4: CLRP00 Mask         */
+#define GPIO_PORT_CLR4_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR4: CLRP01 Position     */
+#define GPIO_PORT_CLR4_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos)                     /*!< GPIO_PORT CLR4: CLRP01 Mask         */
+#define GPIO_PORT_CLR4_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR4: CLRP02 Position     */
+#define GPIO_PORT_CLR4_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos)                     /*!< GPIO_PORT CLR4: CLRP02 Mask         */
+#define GPIO_PORT_CLR4_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR4: CLRP03 Position     */
+#define GPIO_PORT_CLR4_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos)                     /*!< GPIO_PORT CLR4: CLRP03 Mask         */
+#define GPIO_PORT_CLR4_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR4: CLRP04 Position     */
+#define GPIO_PORT_CLR4_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos)                     /*!< GPIO_PORT CLR4: CLRP04 Mask         */
+#define GPIO_PORT_CLR4_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR4: CLRP05 Position     */
+#define GPIO_PORT_CLR4_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos)                     /*!< GPIO_PORT CLR4: CLRP05 Mask         */
+#define GPIO_PORT_CLR4_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR4: CLRP06 Position     */
+#define GPIO_PORT_CLR4_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos)                     /*!< GPIO_PORT CLR4: CLRP06 Mask         */
+#define GPIO_PORT_CLR4_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR4: CLRP07 Position     */
+#define GPIO_PORT_CLR4_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos)                     /*!< GPIO_PORT CLR4: CLRP07 Mask         */
+#define GPIO_PORT_CLR4_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR4: CLRP08 Position     */
+#define GPIO_PORT_CLR4_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos)                     /*!< GPIO_PORT CLR4: CLRP08 Mask         */
+#define GPIO_PORT_CLR4_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR4: CLRP09 Position     */
+#define GPIO_PORT_CLR4_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos)                     /*!< GPIO_PORT CLR4: CLRP09 Mask         */
+#define GPIO_PORT_CLR4_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR4: CLRP010 Position    */
+#define GPIO_PORT_CLR4_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos)                    /*!< GPIO_PORT CLR4: CLRP010 Mask        */
+#define GPIO_PORT_CLR4_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR4: CLRP011 Position    */
+#define GPIO_PORT_CLR4_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos)                    /*!< GPIO_PORT CLR4: CLRP011 Mask        */
+#define GPIO_PORT_CLR4_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR4: CLRP012 Position    */
+#define GPIO_PORT_CLR4_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos)                    /*!< GPIO_PORT CLR4: CLRP012 Mask        */
+#define GPIO_PORT_CLR4_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR4: CLRP013 Position    */
+#define GPIO_PORT_CLR4_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos)                    /*!< GPIO_PORT CLR4: CLRP013 Mask        */
+#define GPIO_PORT_CLR4_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR4: CLRP014 Position    */
+#define GPIO_PORT_CLR4_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos)                    /*!< GPIO_PORT CLR4: CLRP014 Mask        */
+#define GPIO_PORT_CLR4_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR4: CLRP015 Position    */
+#define GPIO_PORT_CLR4_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos)                    /*!< GPIO_PORT CLR4: CLRP015 Mask        */
+#define GPIO_PORT_CLR4_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR4: CLRP016 Position    */
+#define GPIO_PORT_CLR4_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos)                    /*!< GPIO_PORT CLR4: CLRP016 Mask        */
+#define GPIO_PORT_CLR4_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR4: CLRP017 Position    */
+#define GPIO_PORT_CLR4_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos)                    /*!< GPIO_PORT CLR4: CLRP017 Mask        */
+#define GPIO_PORT_CLR4_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR4: CLRP018 Position    */
+#define GPIO_PORT_CLR4_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos)                    /*!< GPIO_PORT CLR4: CLRP018 Mask        */
+#define GPIO_PORT_CLR4_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR4: CLRP019 Position    */
+#define GPIO_PORT_CLR4_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos)                    /*!< GPIO_PORT CLR4: CLRP019 Mask        */
+#define GPIO_PORT_CLR4_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR4: CLRP020 Position    */
+#define GPIO_PORT_CLR4_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos)                    /*!< GPIO_PORT CLR4: CLRP020 Mask        */
+#define GPIO_PORT_CLR4_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR4: CLRP021 Position    */
+#define GPIO_PORT_CLR4_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos)                    /*!< GPIO_PORT CLR4: CLRP021 Mask        */
+#define GPIO_PORT_CLR4_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR4: CLRP022 Position    */
+#define GPIO_PORT_CLR4_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos)                    /*!< GPIO_PORT CLR4: CLRP022 Mask        */
+#define GPIO_PORT_CLR4_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR4: CLRP023 Position    */
+#define GPIO_PORT_CLR4_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos)                    /*!< GPIO_PORT CLR4: CLRP023 Mask        */
+#define GPIO_PORT_CLR4_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR4: CLRP024 Position    */
+#define GPIO_PORT_CLR4_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos)                    /*!< GPIO_PORT CLR4: CLRP024 Mask        */
+#define GPIO_PORT_CLR4_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR4: CLRP025 Position    */
+#define GPIO_PORT_CLR4_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos)                    /*!< GPIO_PORT CLR4: CLRP025 Mask        */
+#define GPIO_PORT_CLR4_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR4: CLRP026 Position    */
+#define GPIO_PORT_CLR4_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos)                    /*!< GPIO_PORT CLR4: CLRP026 Mask        */
+#define GPIO_PORT_CLR4_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR4: CLRP027 Position    */
+#define GPIO_PORT_CLR4_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos)                    /*!< GPIO_PORT CLR4: CLRP027 Mask        */
+#define GPIO_PORT_CLR4_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR4: CLRP028 Position    */
+#define GPIO_PORT_CLR4_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos)                    /*!< GPIO_PORT CLR4: CLRP028 Mask        */
+#define GPIO_PORT_CLR4_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR4: CLRP029 Position    */
+#define GPIO_PORT_CLR4_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos)                    /*!< GPIO_PORT CLR4: CLRP029 Mask        */
+#define GPIO_PORT_CLR4_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR4: CLRP030 Position    */
+#define GPIO_PORT_CLR4_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos)                    /*!< GPIO_PORT CLR4: CLRP030 Mask        */
+#define GPIO_PORT_CLR4_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR4: CLRP031 Position    */
+#define GPIO_PORT_CLR4_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos)                    /*!< GPIO_PORT CLR4: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR5  -----------------------------------------
+#define GPIO_PORT_CLR5_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR5: CLRP00 Position     */
+#define GPIO_PORT_CLR5_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos)                     /*!< GPIO_PORT CLR5: CLRP00 Mask         */
+#define GPIO_PORT_CLR5_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR5: CLRP01 Position     */
+#define GPIO_PORT_CLR5_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos)                     /*!< GPIO_PORT CLR5: CLRP01 Mask         */
+#define GPIO_PORT_CLR5_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR5: CLRP02 Position     */
+#define GPIO_PORT_CLR5_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos)                     /*!< GPIO_PORT CLR5: CLRP02 Mask         */
+#define GPIO_PORT_CLR5_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR5: CLRP03 Position     */
+#define GPIO_PORT_CLR5_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos)                     /*!< GPIO_PORT CLR5: CLRP03 Mask         */
+#define GPIO_PORT_CLR5_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR5: CLRP04 Position     */
+#define GPIO_PORT_CLR5_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos)                     /*!< GPIO_PORT CLR5: CLRP04 Mask         */
+#define GPIO_PORT_CLR5_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR5: CLRP05 Position     */
+#define GPIO_PORT_CLR5_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos)                     /*!< GPIO_PORT CLR5: CLRP05 Mask         */
+#define GPIO_PORT_CLR5_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR5: CLRP06 Position     */
+#define GPIO_PORT_CLR5_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos)                     /*!< GPIO_PORT CLR5: CLRP06 Mask         */
+#define GPIO_PORT_CLR5_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR5: CLRP07 Position     */
+#define GPIO_PORT_CLR5_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos)                     /*!< GPIO_PORT CLR5: CLRP07 Mask         */
+#define GPIO_PORT_CLR5_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR5: CLRP08 Position     */
+#define GPIO_PORT_CLR5_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos)                     /*!< GPIO_PORT CLR5: CLRP08 Mask         */
+#define GPIO_PORT_CLR5_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR5: CLRP09 Position     */
+#define GPIO_PORT_CLR5_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos)                     /*!< GPIO_PORT CLR5: CLRP09 Mask         */
+#define GPIO_PORT_CLR5_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR5: CLRP010 Position    */
+#define GPIO_PORT_CLR5_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos)                    /*!< GPIO_PORT CLR5: CLRP010 Mask        */
+#define GPIO_PORT_CLR5_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR5: CLRP011 Position    */
+#define GPIO_PORT_CLR5_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos)                    /*!< GPIO_PORT CLR5: CLRP011 Mask        */
+#define GPIO_PORT_CLR5_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR5: CLRP012 Position    */
+#define GPIO_PORT_CLR5_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos)                    /*!< GPIO_PORT CLR5: CLRP012 Mask        */
+#define GPIO_PORT_CLR5_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR5: CLRP013 Position    */
+#define GPIO_PORT_CLR5_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos)                    /*!< GPIO_PORT CLR5: CLRP013 Mask        */
+#define GPIO_PORT_CLR5_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR5: CLRP014 Position    */
+#define GPIO_PORT_CLR5_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos)                    /*!< GPIO_PORT CLR5: CLRP014 Mask        */
+#define GPIO_PORT_CLR5_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR5: CLRP015 Position    */
+#define GPIO_PORT_CLR5_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos)                    /*!< GPIO_PORT CLR5: CLRP015 Mask        */
+#define GPIO_PORT_CLR5_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR5: CLRP016 Position    */
+#define GPIO_PORT_CLR5_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos)                    /*!< GPIO_PORT CLR5: CLRP016 Mask        */
+#define GPIO_PORT_CLR5_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR5: CLRP017 Position    */
+#define GPIO_PORT_CLR5_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos)                    /*!< GPIO_PORT CLR5: CLRP017 Mask        */
+#define GPIO_PORT_CLR5_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR5: CLRP018 Position    */
+#define GPIO_PORT_CLR5_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos)                    /*!< GPIO_PORT CLR5: CLRP018 Mask        */
+#define GPIO_PORT_CLR5_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR5: CLRP019 Position    */
+#define GPIO_PORT_CLR5_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos)                    /*!< GPIO_PORT CLR5: CLRP019 Mask        */
+#define GPIO_PORT_CLR5_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR5: CLRP020 Position    */
+#define GPIO_PORT_CLR5_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos)                    /*!< GPIO_PORT CLR5: CLRP020 Mask        */
+#define GPIO_PORT_CLR5_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR5: CLRP021 Position    */
+#define GPIO_PORT_CLR5_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos)                    /*!< GPIO_PORT CLR5: CLRP021 Mask        */
+#define GPIO_PORT_CLR5_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR5: CLRP022 Position    */
+#define GPIO_PORT_CLR5_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos)                    /*!< GPIO_PORT CLR5: CLRP022 Mask        */
+#define GPIO_PORT_CLR5_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR5: CLRP023 Position    */
+#define GPIO_PORT_CLR5_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos)                    /*!< GPIO_PORT CLR5: CLRP023 Mask        */
+#define GPIO_PORT_CLR5_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR5: CLRP024 Position    */
+#define GPIO_PORT_CLR5_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos)                    /*!< GPIO_PORT CLR5: CLRP024 Mask        */
+#define GPIO_PORT_CLR5_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR5: CLRP025 Position    */
+#define GPIO_PORT_CLR5_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos)                    /*!< GPIO_PORT CLR5: CLRP025 Mask        */
+#define GPIO_PORT_CLR5_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR5: CLRP026 Position    */
+#define GPIO_PORT_CLR5_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos)                    /*!< GPIO_PORT CLR5: CLRP026 Mask        */
+#define GPIO_PORT_CLR5_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR5: CLRP027 Position    */
+#define GPIO_PORT_CLR5_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos)                    /*!< GPIO_PORT CLR5: CLRP027 Mask        */
+#define GPIO_PORT_CLR5_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR5: CLRP028 Position    */
+#define GPIO_PORT_CLR5_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos)                    /*!< GPIO_PORT CLR5: CLRP028 Mask        */
+#define GPIO_PORT_CLR5_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR5: CLRP029 Position    */
+#define GPIO_PORT_CLR5_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos)                    /*!< GPIO_PORT CLR5: CLRP029 Mask        */
+#define GPIO_PORT_CLR5_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR5: CLRP030 Position    */
+#define GPIO_PORT_CLR5_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos)                    /*!< GPIO_PORT CLR5: CLRP030 Mask        */
+#define GPIO_PORT_CLR5_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR5: CLRP031 Position    */
+#define GPIO_PORT_CLR5_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos)                    /*!< GPIO_PORT CLR5: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR6  -----------------------------------------
+#define GPIO_PORT_CLR6_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR6: CLRP00 Position     */
+#define GPIO_PORT_CLR6_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos)                     /*!< GPIO_PORT CLR6: CLRP00 Mask         */
+#define GPIO_PORT_CLR6_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR6: CLRP01 Position     */
+#define GPIO_PORT_CLR6_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos)                     /*!< GPIO_PORT CLR6: CLRP01 Mask         */
+#define GPIO_PORT_CLR6_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR6: CLRP02 Position     */
+#define GPIO_PORT_CLR6_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos)                     /*!< GPIO_PORT CLR6: CLRP02 Mask         */
+#define GPIO_PORT_CLR6_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR6: CLRP03 Position     */
+#define GPIO_PORT_CLR6_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos)                     /*!< GPIO_PORT CLR6: CLRP03 Mask         */
+#define GPIO_PORT_CLR6_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR6: CLRP04 Position     */
+#define GPIO_PORT_CLR6_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos)                     /*!< GPIO_PORT CLR6: CLRP04 Mask         */
+#define GPIO_PORT_CLR6_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR6: CLRP05 Position     */
+#define GPIO_PORT_CLR6_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos)                     /*!< GPIO_PORT CLR6: CLRP05 Mask         */
+#define GPIO_PORT_CLR6_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR6: CLRP06 Position     */
+#define GPIO_PORT_CLR6_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos)                     /*!< GPIO_PORT CLR6: CLRP06 Mask         */
+#define GPIO_PORT_CLR6_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR6: CLRP07 Position     */
+#define GPIO_PORT_CLR6_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos)                     /*!< GPIO_PORT CLR6: CLRP07 Mask         */
+#define GPIO_PORT_CLR6_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR6: CLRP08 Position     */
+#define GPIO_PORT_CLR6_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos)                     /*!< GPIO_PORT CLR6: CLRP08 Mask         */
+#define GPIO_PORT_CLR6_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR6: CLRP09 Position     */
+#define GPIO_PORT_CLR6_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos)                     /*!< GPIO_PORT CLR6: CLRP09 Mask         */
+#define GPIO_PORT_CLR6_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR6: CLRP010 Position    */
+#define GPIO_PORT_CLR6_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos)                    /*!< GPIO_PORT CLR6: CLRP010 Mask        */
+#define GPIO_PORT_CLR6_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR6: CLRP011 Position    */
+#define GPIO_PORT_CLR6_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos)                    /*!< GPIO_PORT CLR6: CLRP011 Mask        */
+#define GPIO_PORT_CLR6_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR6: CLRP012 Position    */
+#define GPIO_PORT_CLR6_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos)                    /*!< GPIO_PORT CLR6: CLRP012 Mask        */
+#define GPIO_PORT_CLR6_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR6: CLRP013 Position    */
+#define GPIO_PORT_CLR6_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos)                    /*!< GPIO_PORT CLR6: CLRP013 Mask        */
+#define GPIO_PORT_CLR6_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR6: CLRP014 Position    */
+#define GPIO_PORT_CLR6_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos)                    /*!< GPIO_PORT CLR6: CLRP014 Mask        */
+#define GPIO_PORT_CLR6_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR6: CLRP015 Position    */
+#define GPIO_PORT_CLR6_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos)                    /*!< GPIO_PORT CLR6: CLRP015 Mask        */
+#define GPIO_PORT_CLR6_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR6: CLRP016 Position    */
+#define GPIO_PORT_CLR6_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos)                    /*!< GPIO_PORT CLR6: CLRP016 Mask        */
+#define GPIO_PORT_CLR6_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR6: CLRP017 Position    */
+#define GPIO_PORT_CLR6_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos)                    /*!< GPIO_PORT CLR6: CLRP017 Mask        */
+#define GPIO_PORT_CLR6_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR6: CLRP018 Position    */
+#define GPIO_PORT_CLR6_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos)                    /*!< GPIO_PORT CLR6: CLRP018 Mask        */
+#define GPIO_PORT_CLR6_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR6: CLRP019 Position    */
+#define GPIO_PORT_CLR6_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos)                    /*!< GPIO_PORT CLR6: CLRP019 Mask        */
+#define GPIO_PORT_CLR6_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR6: CLRP020 Position    */
+#define GPIO_PORT_CLR6_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos)                    /*!< GPIO_PORT CLR6: CLRP020 Mask        */
+#define GPIO_PORT_CLR6_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR6: CLRP021 Position    */
+#define GPIO_PORT_CLR6_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos)                    /*!< GPIO_PORT CLR6: CLRP021 Mask        */
+#define GPIO_PORT_CLR6_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR6: CLRP022 Position    */
+#define GPIO_PORT_CLR6_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos)                    /*!< GPIO_PORT CLR6: CLRP022 Mask        */
+#define GPIO_PORT_CLR6_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR6: CLRP023 Position    */
+#define GPIO_PORT_CLR6_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos)                    /*!< GPIO_PORT CLR6: CLRP023 Mask        */
+#define GPIO_PORT_CLR6_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR6: CLRP024 Position    */
+#define GPIO_PORT_CLR6_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos)                    /*!< GPIO_PORT CLR6: CLRP024 Mask        */
+#define GPIO_PORT_CLR6_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR6: CLRP025 Position    */
+#define GPIO_PORT_CLR6_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos)                    /*!< GPIO_PORT CLR6: CLRP025 Mask        */
+#define GPIO_PORT_CLR6_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR6: CLRP026 Position    */
+#define GPIO_PORT_CLR6_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos)                    /*!< GPIO_PORT CLR6: CLRP026 Mask        */
+#define GPIO_PORT_CLR6_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR6: CLRP027 Position    */
+#define GPIO_PORT_CLR6_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos)                    /*!< GPIO_PORT CLR6: CLRP027 Mask        */
+#define GPIO_PORT_CLR6_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR6: CLRP028 Position    */
+#define GPIO_PORT_CLR6_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos)                    /*!< GPIO_PORT CLR6: CLRP028 Mask        */
+#define GPIO_PORT_CLR6_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR6: CLRP029 Position    */
+#define GPIO_PORT_CLR6_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos)                    /*!< GPIO_PORT CLR6: CLRP029 Mask        */
+#define GPIO_PORT_CLR6_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR6: CLRP030 Position    */
+#define GPIO_PORT_CLR6_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos)                    /*!< GPIO_PORT CLR6: CLRP030 Mask        */
+#define GPIO_PORT_CLR6_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR6: CLRP031 Position    */
+#define GPIO_PORT_CLR6_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos)                    /*!< GPIO_PORT CLR6: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR7  -----------------------------------------
+#define GPIO_PORT_CLR7_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR7: CLRP00 Position     */
+#define GPIO_PORT_CLR7_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos)                     /*!< GPIO_PORT CLR7: CLRP00 Mask         */
+#define GPIO_PORT_CLR7_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR7: CLRP01 Position     */
+#define GPIO_PORT_CLR7_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos)                     /*!< GPIO_PORT CLR7: CLRP01 Mask         */
+#define GPIO_PORT_CLR7_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR7: CLRP02 Position     */
+#define GPIO_PORT_CLR7_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos)                     /*!< GPIO_PORT CLR7: CLRP02 Mask         */
+#define GPIO_PORT_CLR7_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR7: CLRP03 Position     */
+#define GPIO_PORT_CLR7_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos)                     /*!< GPIO_PORT CLR7: CLRP03 Mask         */
+#define GPIO_PORT_CLR7_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR7: CLRP04 Position     */
+#define GPIO_PORT_CLR7_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos)                     /*!< GPIO_PORT CLR7: CLRP04 Mask         */
+#define GPIO_PORT_CLR7_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR7: CLRP05 Position     */
+#define GPIO_PORT_CLR7_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos)                     /*!< GPIO_PORT CLR7: CLRP05 Mask         */
+#define GPIO_PORT_CLR7_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR7: CLRP06 Position     */
+#define GPIO_PORT_CLR7_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos)                     /*!< GPIO_PORT CLR7: CLRP06 Mask         */
+#define GPIO_PORT_CLR7_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR7: CLRP07 Position     */
+#define GPIO_PORT_CLR7_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos)                     /*!< GPIO_PORT CLR7: CLRP07 Mask         */
+#define GPIO_PORT_CLR7_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR7: CLRP08 Position     */
+#define GPIO_PORT_CLR7_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos)                     /*!< GPIO_PORT CLR7: CLRP08 Mask         */
+#define GPIO_PORT_CLR7_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR7: CLRP09 Position     */
+#define GPIO_PORT_CLR7_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos)                     /*!< GPIO_PORT CLR7: CLRP09 Mask         */
+#define GPIO_PORT_CLR7_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR7: CLRP010 Position    */
+#define GPIO_PORT_CLR7_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos)                    /*!< GPIO_PORT CLR7: CLRP010 Mask        */
+#define GPIO_PORT_CLR7_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR7: CLRP011 Position    */
+#define GPIO_PORT_CLR7_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos)                    /*!< GPIO_PORT CLR7: CLRP011 Mask        */
+#define GPIO_PORT_CLR7_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR7: CLRP012 Position    */
+#define GPIO_PORT_CLR7_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos)                    /*!< GPIO_PORT CLR7: CLRP012 Mask        */
+#define GPIO_PORT_CLR7_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR7: CLRP013 Position    */
+#define GPIO_PORT_CLR7_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos)                    /*!< GPIO_PORT CLR7: CLRP013 Mask        */
+#define GPIO_PORT_CLR7_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR7: CLRP014 Position    */
+#define GPIO_PORT_CLR7_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos)                    /*!< GPIO_PORT CLR7: CLRP014 Mask        */
+#define GPIO_PORT_CLR7_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR7: CLRP015 Position    */
+#define GPIO_PORT_CLR7_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos)                    /*!< GPIO_PORT CLR7: CLRP015 Mask        */
+#define GPIO_PORT_CLR7_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR7: CLRP016 Position    */
+#define GPIO_PORT_CLR7_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos)                    /*!< GPIO_PORT CLR7: CLRP016 Mask        */
+#define GPIO_PORT_CLR7_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR7: CLRP017 Position    */
+#define GPIO_PORT_CLR7_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos)                    /*!< GPIO_PORT CLR7: CLRP017 Mask        */
+#define GPIO_PORT_CLR7_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR7: CLRP018 Position    */
+#define GPIO_PORT_CLR7_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos)                    /*!< GPIO_PORT CLR7: CLRP018 Mask        */
+#define GPIO_PORT_CLR7_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR7: CLRP019 Position    */
+#define GPIO_PORT_CLR7_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos)                    /*!< GPIO_PORT CLR7: CLRP019 Mask        */
+#define GPIO_PORT_CLR7_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR7: CLRP020 Position    */
+#define GPIO_PORT_CLR7_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos)                    /*!< GPIO_PORT CLR7: CLRP020 Mask        */
+#define GPIO_PORT_CLR7_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR7: CLRP021 Position    */
+#define GPIO_PORT_CLR7_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos)                    /*!< GPIO_PORT CLR7: CLRP021 Mask        */
+#define GPIO_PORT_CLR7_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR7: CLRP022 Position    */
+#define GPIO_PORT_CLR7_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos)                    /*!< GPIO_PORT CLR7: CLRP022 Mask        */
+#define GPIO_PORT_CLR7_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR7: CLRP023 Position    */
+#define GPIO_PORT_CLR7_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos)                    /*!< GPIO_PORT CLR7: CLRP023 Mask        */
+#define GPIO_PORT_CLR7_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR7: CLRP024 Position    */
+#define GPIO_PORT_CLR7_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos)                    /*!< GPIO_PORT CLR7: CLRP024 Mask        */
+#define GPIO_PORT_CLR7_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR7: CLRP025 Position    */
+#define GPIO_PORT_CLR7_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos)                    /*!< GPIO_PORT CLR7: CLRP025 Mask        */
+#define GPIO_PORT_CLR7_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR7: CLRP026 Position    */
+#define GPIO_PORT_CLR7_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos)                    /*!< GPIO_PORT CLR7: CLRP026 Mask        */
+#define GPIO_PORT_CLR7_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR7: CLRP027 Position    */
+#define GPIO_PORT_CLR7_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos)                    /*!< GPIO_PORT CLR7: CLRP027 Mask        */
+#define GPIO_PORT_CLR7_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR7: CLRP028 Position    */
+#define GPIO_PORT_CLR7_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos)                    /*!< GPIO_PORT CLR7: CLRP028 Mask        */
+#define GPIO_PORT_CLR7_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR7: CLRP029 Position    */
+#define GPIO_PORT_CLR7_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos)                    /*!< GPIO_PORT CLR7: CLRP029 Mask        */
+#define GPIO_PORT_CLR7_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR7: CLRP030 Position    */
+#define GPIO_PORT_CLR7_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos)                    /*!< GPIO_PORT CLR7: CLRP030 Mask        */
+#define GPIO_PORT_CLR7_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR7: CLRP031 Position    */
+#define GPIO_PORT_CLR7_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos)                    /*!< GPIO_PORT CLR7: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_NOT0  -----------------------------------------
+#define GPIO_PORT_NOT0_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT0: NOTP0 Position      */
+#define GPIO_PORT_NOT0_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos)                      /*!< GPIO_PORT NOT0: NOTP0 Mask          */
+#define GPIO_PORT_NOT0_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT0: NOTP1 Position      */
+#define GPIO_PORT_NOT0_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos)                      /*!< GPIO_PORT NOT0: NOTP1 Mask          */
+#define GPIO_PORT_NOT0_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT0: NOTP2 Position      */
+#define GPIO_PORT_NOT0_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos)                      /*!< GPIO_PORT NOT0: NOTP2 Mask          */
+#define GPIO_PORT_NOT0_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT0: NOTP3 Position      */
+#define GPIO_PORT_NOT0_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos)                      /*!< GPIO_PORT NOT0: NOTP3 Mask          */
+#define GPIO_PORT_NOT0_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT0: NOTP4 Position      */
+#define GPIO_PORT_NOT0_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos)                      /*!< GPIO_PORT NOT0: NOTP4 Mask          */
+#define GPIO_PORT_NOT0_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT0: NOTP5 Position      */
+#define GPIO_PORT_NOT0_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos)                      /*!< GPIO_PORT NOT0: NOTP5 Mask          */
+#define GPIO_PORT_NOT0_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT0: NOTP6 Position      */
+#define GPIO_PORT_NOT0_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos)                      /*!< GPIO_PORT NOT0: NOTP6 Mask          */
+#define GPIO_PORT_NOT0_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT0: NOTP7 Position      */
+#define GPIO_PORT_NOT0_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos)                      /*!< GPIO_PORT NOT0: NOTP7 Mask          */
+#define GPIO_PORT_NOT0_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT0: NOTP8 Position      */
+#define GPIO_PORT_NOT0_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos)                      /*!< GPIO_PORT NOT0: NOTP8 Mask          */
+#define GPIO_PORT_NOT0_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT0: NOTP9 Position      */
+#define GPIO_PORT_NOT0_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos)                      /*!< GPIO_PORT NOT0: NOTP9 Mask          */
+#define GPIO_PORT_NOT0_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT0: NOTP10 Position     */
+#define GPIO_PORT_NOT0_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos)                     /*!< GPIO_PORT NOT0: NOTP10 Mask         */
+#define GPIO_PORT_NOT0_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT0: NOTP11 Position     */
+#define GPIO_PORT_NOT0_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos)                     /*!< GPIO_PORT NOT0: NOTP11 Mask         */
+#define GPIO_PORT_NOT0_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT0: NOTP12 Position     */
+#define GPIO_PORT_NOT0_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos)                     /*!< GPIO_PORT NOT0: NOTP12 Mask         */
+#define GPIO_PORT_NOT0_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT0: NOTP13 Position     */
+#define GPIO_PORT_NOT0_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos)                     /*!< GPIO_PORT NOT0: NOTP13 Mask         */
+#define GPIO_PORT_NOT0_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT0: NOTP14 Position     */
+#define GPIO_PORT_NOT0_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos)                     /*!< GPIO_PORT NOT0: NOTP14 Mask         */
+#define GPIO_PORT_NOT0_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT0: NOTP15 Position     */
+#define GPIO_PORT_NOT0_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos)                     /*!< GPIO_PORT NOT0: NOTP15 Mask         */
+#define GPIO_PORT_NOT0_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT0: NOTP16 Position     */
+#define GPIO_PORT_NOT0_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos)                     /*!< GPIO_PORT NOT0: NOTP16 Mask         */
+#define GPIO_PORT_NOT0_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT0: NOTP17 Position     */
+#define GPIO_PORT_NOT0_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos)                     /*!< GPIO_PORT NOT0: NOTP17 Mask         */
+#define GPIO_PORT_NOT0_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT0: NOTP18 Position     */
+#define GPIO_PORT_NOT0_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos)                     /*!< GPIO_PORT NOT0: NOTP18 Mask         */
+#define GPIO_PORT_NOT0_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT0: NOTP19 Position     */
+#define GPIO_PORT_NOT0_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos)                     /*!< GPIO_PORT NOT0: NOTP19 Mask         */
+#define GPIO_PORT_NOT0_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT0: NOTP20 Position     */
+#define GPIO_PORT_NOT0_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos)                     /*!< GPIO_PORT NOT0: NOTP20 Mask         */
+#define GPIO_PORT_NOT0_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT0: NOTP21 Position     */
+#define GPIO_PORT_NOT0_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos)                     /*!< GPIO_PORT NOT0: NOTP21 Mask         */
+#define GPIO_PORT_NOT0_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT0: NOTP22 Position     */
+#define GPIO_PORT_NOT0_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos)                     /*!< GPIO_PORT NOT0: NOTP22 Mask         */
+#define GPIO_PORT_NOT0_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT0: NOTP23 Position     */
+#define GPIO_PORT_NOT0_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos)                     /*!< GPIO_PORT NOT0: NOTP23 Mask         */
+#define GPIO_PORT_NOT0_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT0: NOTP24 Position     */
+#define GPIO_PORT_NOT0_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos)                     /*!< GPIO_PORT NOT0: NOTP24 Mask         */
+#define GPIO_PORT_NOT0_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT0: NOTP25 Position     */
+#define GPIO_PORT_NOT0_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos)                     /*!< GPIO_PORT NOT0: NOTP25 Mask         */
+#define GPIO_PORT_NOT0_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT0: NOTP26 Position     */
+#define GPIO_PORT_NOT0_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos)                     /*!< GPIO_PORT NOT0: NOTP26 Mask         */
+#define GPIO_PORT_NOT0_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT0: NOTP27 Position     */
+#define GPIO_PORT_NOT0_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos)                     /*!< GPIO_PORT NOT0: NOTP27 Mask         */
+#define GPIO_PORT_NOT0_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT0: NOTP28 Position     */
+#define GPIO_PORT_NOT0_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos)                     /*!< GPIO_PORT NOT0: NOTP28 Mask         */
+#define GPIO_PORT_NOT0_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT0: NOTP29 Position     */
+#define GPIO_PORT_NOT0_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos)                     /*!< GPIO_PORT NOT0: NOTP29 Mask         */
+#define GPIO_PORT_NOT0_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT0: NOTP30 Position     */
+#define GPIO_PORT_NOT0_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos)                     /*!< GPIO_PORT NOT0: NOTP30 Mask         */
+#define GPIO_PORT_NOT0_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT0: NOTP31 Position     */
+#define GPIO_PORT_NOT0_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos)                     /*!< GPIO_PORT NOT0: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT1  -----------------------------------------
+#define GPIO_PORT_NOT1_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT1: NOTP0 Position      */
+#define GPIO_PORT_NOT1_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos)                      /*!< GPIO_PORT NOT1: NOTP0 Mask          */
+#define GPIO_PORT_NOT1_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT1: NOTP1 Position      */
+#define GPIO_PORT_NOT1_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos)                      /*!< GPIO_PORT NOT1: NOTP1 Mask          */
+#define GPIO_PORT_NOT1_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT1: NOTP2 Position      */
+#define GPIO_PORT_NOT1_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos)                      /*!< GPIO_PORT NOT1: NOTP2 Mask          */
+#define GPIO_PORT_NOT1_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT1: NOTP3 Position      */
+#define GPIO_PORT_NOT1_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos)                      /*!< GPIO_PORT NOT1: NOTP3 Mask          */
+#define GPIO_PORT_NOT1_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT1: NOTP4 Position      */
+#define GPIO_PORT_NOT1_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos)                      /*!< GPIO_PORT NOT1: NOTP4 Mask          */
+#define GPIO_PORT_NOT1_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT1: NOTP5 Position      */
+#define GPIO_PORT_NOT1_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos)                      /*!< GPIO_PORT NOT1: NOTP5 Mask          */
+#define GPIO_PORT_NOT1_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT1: NOTP6 Position      */
+#define GPIO_PORT_NOT1_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos)                      /*!< GPIO_PORT NOT1: NOTP6 Mask          */
+#define GPIO_PORT_NOT1_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT1: NOTP7 Position      */
+#define GPIO_PORT_NOT1_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos)                      /*!< GPIO_PORT NOT1: NOTP7 Mask          */
+#define GPIO_PORT_NOT1_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT1: NOTP8 Position      */
+#define GPIO_PORT_NOT1_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos)                      /*!< GPIO_PORT NOT1: NOTP8 Mask          */
+#define GPIO_PORT_NOT1_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT1: NOTP9 Position      */
+#define GPIO_PORT_NOT1_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos)                      /*!< GPIO_PORT NOT1: NOTP9 Mask          */
+#define GPIO_PORT_NOT1_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT1: NOTP10 Position     */
+#define GPIO_PORT_NOT1_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos)                     /*!< GPIO_PORT NOT1: NOTP10 Mask         */
+#define GPIO_PORT_NOT1_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT1: NOTP11 Position     */
+#define GPIO_PORT_NOT1_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos)                     /*!< GPIO_PORT NOT1: NOTP11 Mask         */
+#define GPIO_PORT_NOT1_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT1: NOTP12 Position     */
+#define GPIO_PORT_NOT1_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos)                     /*!< GPIO_PORT NOT1: NOTP12 Mask         */
+#define GPIO_PORT_NOT1_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT1: NOTP13 Position     */
+#define GPIO_PORT_NOT1_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos)                     /*!< GPIO_PORT NOT1: NOTP13 Mask         */
+#define GPIO_PORT_NOT1_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT1: NOTP14 Position     */
+#define GPIO_PORT_NOT1_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos)                     /*!< GPIO_PORT NOT1: NOTP14 Mask         */
+#define GPIO_PORT_NOT1_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT1: NOTP15 Position     */
+#define GPIO_PORT_NOT1_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos)                     /*!< GPIO_PORT NOT1: NOTP15 Mask         */
+#define GPIO_PORT_NOT1_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT1: NOTP16 Position     */
+#define GPIO_PORT_NOT1_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos)                     /*!< GPIO_PORT NOT1: NOTP16 Mask         */
+#define GPIO_PORT_NOT1_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT1: NOTP17 Position     */
+#define GPIO_PORT_NOT1_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos)                     /*!< GPIO_PORT NOT1: NOTP17 Mask         */
+#define GPIO_PORT_NOT1_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT1: NOTP18 Position     */
+#define GPIO_PORT_NOT1_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos)                     /*!< GPIO_PORT NOT1: NOTP18 Mask         */
+#define GPIO_PORT_NOT1_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT1: NOTP19 Position     */
+#define GPIO_PORT_NOT1_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos)                     /*!< GPIO_PORT NOT1: NOTP19 Mask         */
+#define GPIO_PORT_NOT1_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT1: NOTP20 Position     */
+#define GPIO_PORT_NOT1_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos)                     /*!< GPIO_PORT NOT1: NOTP20 Mask         */
+#define GPIO_PORT_NOT1_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT1: NOTP21 Position     */
+#define GPIO_PORT_NOT1_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos)                     /*!< GPIO_PORT NOT1: NOTP21 Mask         */
+#define GPIO_PORT_NOT1_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT1: NOTP22 Position     */
+#define GPIO_PORT_NOT1_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos)                     /*!< GPIO_PORT NOT1: NOTP22 Mask         */
+#define GPIO_PORT_NOT1_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT1: NOTP23 Position     */
+#define GPIO_PORT_NOT1_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos)                     /*!< GPIO_PORT NOT1: NOTP23 Mask         */
+#define GPIO_PORT_NOT1_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT1: NOTP24 Position     */
+#define GPIO_PORT_NOT1_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos)                     /*!< GPIO_PORT NOT1: NOTP24 Mask         */
+#define GPIO_PORT_NOT1_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT1: NOTP25 Position     */
+#define GPIO_PORT_NOT1_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos)                     /*!< GPIO_PORT NOT1: NOTP25 Mask         */
+#define GPIO_PORT_NOT1_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT1: NOTP26 Position     */
+#define GPIO_PORT_NOT1_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos)                     /*!< GPIO_PORT NOT1: NOTP26 Mask         */
+#define GPIO_PORT_NOT1_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT1: NOTP27 Position     */
+#define GPIO_PORT_NOT1_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos)                     /*!< GPIO_PORT NOT1: NOTP27 Mask         */
+#define GPIO_PORT_NOT1_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT1: NOTP28 Position     */
+#define GPIO_PORT_NOT1_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos)                     /*!< GPIO_PORT NOT1: NOTP28 Mask         */
+#define GPIO_PORT_NOT1_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT1: NOTP29 Position     */
+#define GPIO_PORT_NOT1_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos)                     /*!< GPIO_PORT NOT1: NOTP29 Mask         */
+#define GPIO_PORT_NOT1_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT1: NOTP30 Position     */
+#define GPIO_PORT_NOT1_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos)                     /*!< GPIO_PORT NOT1: NOTP30 Mask         */
+#define GPIO_PORT_NOT1_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT1: NOTP31 Position     */
+#define GPIO_PORT_NOT1_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos)                     /*!< GPIO_PORT NOT1: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT2  -----------------------------------------
+#define GPIO_PORT_NOT2_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT2: NOTP0 Position      */
+#define GPIO_PORT_NOT2_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos)                      /*!< GPIO_PORT NOT2: NOTP0 Mask          */
+#define GPIO_PORT_NOT2_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT2: NOTP1 Position      */
+#define GPIO_PORT_NOT2_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos)                      /*!< GPIO_PORT NOT2: NOTP1 Mask          */
+#define GPIO_PORT_NOT2_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT2: NOTP2 Position      */
+#define GPIO_PORT_NOT2_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos)                      /*!< GPIO_PORT NOT2: NOTP2 Mask          */
+#define GPIO_PORT_NOT2_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT2: NOTP3 Position      */
+#define GPIO_PORT_NOT2_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos)                      /*!< GPIO_PORT NOT2: NOTP3 Mask          */
+#define GPIO_PORT_NOT2_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT2: NOTP4 Position      */
+#define GPIO_PORT_NOT2_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos)                      /*!< GPIO_PORT NOT2: NOTP4 Mask          */
+#define GPIO_PORT_NOT2_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT2: NOTP5 Position      */
+#define GPIO_PORT_NOT2_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos)                      /*!< GPIO_PORT NOT2: NOTP5 Mask          */
+#define GPIO_PORT_NOT2_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT2: NOTP6 Position      */
+#define GPIO_PORT_NOT2_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos)                      /*!< GPIO_PORT NOT2: NOTP6 Mask          */
+#define GPIO_PORT_NOT2_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT2: NOTP7 Position      */
+#define GPIO_PORT_NOT2_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos)                      /*!< GPIO_PORT NOT2: NOTP7 Mask          */
+#define GPIO_PORT_NOT2_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT2: NOTP8 Position      */
+#define GPIO_PORT_NOT2_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos)                      /*!< GPIO_PORT NOT2: NOTP8 Mask          */
+#define GPIO_PORT_NOT2_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT2: NOTP9 Position      */
+#define GPIO_PORT_NOT2_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos)                      /*!< GPIO_PORT NOT2: NOTP9 Mask          */
+#define GPIO_PORT_NOT2_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT2: NOTP10 Position     */
+#define GPIO_PORT_NOT2_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos)                     /*!< GPIO_PORT NOT2: NOTP10 Mask         */
+#define GPIO_PORT_NOT2_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT2: NOTP11 Position     */
+#define GPIO_PORT_NOT2_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos)                     /*!< GPIO_PORT NOT2: NOTP11 Mask         */
+#define GPIO_PORT_NOT2_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT2: NOTP12 Position     */
+#define GPIO_PORT_NOT2_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos)                     /*!< GPIO_PORT NOT2: NOTP12 Mask         */
+#define GPIO_PORT_NOT2_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT2: NOTP13 Position     */
+#define GPIO_PORT_NOT2_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos)                     /*!< GPIO_PORT NOT2: NOTP13 Mask         */
+#define GPIO_PORT_NOT2_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT2: NOTP14 Position     */
+#define GPIO_PORT_NOT2_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos)                     /*!< GPIO_PORT NOT2: NOTP14 Mask         */
+#define GPIO_PORT_NOT2_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT2: NOTP15 Position     */
+#define GPIO_PORT_NOT2_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos)                     /*!< GPIO_PORT NOT2: NOTP15 Mask         */
+#define GPIO_PORT_NOT2_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT2: NOTP16 Position     */
+#define GPIO_PORT_NOT2_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos)                     /*!< GPIO_PORT NOT2: NOTP16 Mask         */
+#define GPIO_PORT_NOT2_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT2: NOTP17 Position     */
+#define GPIO_PORT_NOT2_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos)                     /*!< GPIO_PORT NOT2: NOTP17 Mask         */
+#define GPIO_PORT_NOT2_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT2: NOTP18 Position     */
+#define GPIO_PORT_NOT2_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos)                     /*!< GPIO_PORT NOT2: NOTP18 Mask         */
+#define GPIO_PORT_NOT2_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT2: NOTP19 Position     */
+#define GPIO_PORT_NOT2_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos)                     /*!< GPIO_PORT NOT2: NOTP19 Mask         */
+#define GPIO_PORT_NOT2_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT2: NOTP20 Position     */
+#define GPIO_PORT_NOT2_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos)                     /*!< GPIO_PORT NOT2: NOTP20 Mask         */
+#define GPIO_PORT_NOT2_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT2: NOTP21 Position     */
+#define GPIO_PORT_NOT2_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos)                     /*!< GPIO_PORT NOT2: NOTP21 Mask         */
+#define GPIO_PORT_NOT2_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT2: NOTP22 Position     */
+#define GPIO_PORT_NOT2_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos)                     /*!< GPIO_PORT NOT2: NOTP22 Mask         */
+#define GPIO_PORT_NOT2_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT2: NOTP23 Position     */
+#define GPIO_PORT_NOT2_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos)                     /*!< GPIO_PORT NOT2: NOTP23 Mask         */
+#define GPIO_PORT_NOT2_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT2: NOTP24 Position     */
+#define GPIO_PORT_NOT2_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos)                     /*!< GPIO_PORT NOT2: NOTP24 Mask         */
+#define GPIO_PORT_NOT2_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT2: NOTP25 Position     */
+#define GPIO_PORT_NOT2_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos)                     /*!< GPIO_PORT NOT2: NOTP25 Mask         */
+#define GPIO_PORT_NOT2_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT2: NOTP26 Position     */
+#define GPIO_PORT_NOT2_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos)                     /*!< GPIO_PORT NOT2: NOTP26 Mask         */
+#define GPIO_PORT_NOT2_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT2: NOTP27 Position     */
+#define GPIO_PORT_NOT2_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos)                     /*!< GPIO_PORT NOT2: NOTP27 Mask         */
+#define GPIO_PORT_NOT2_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT2: NOTP28 Position     */
+#define GPIO_PORT_NOT2_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos)                     /*!< GPIO_PORT NOT2: NOTP28 Mask         */
+#define GPIO_PORT_NOT2_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT2: NOTP29 Position     */
+#define GPIO_PORT_NOT2_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos)                     /*!< GPIO_PORT NOT2: NOTP29 Mask         */
+#define GPIO_PORT_NOT2_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT2: NOTP30 Position     */
+#define GPIO_PORT_NOT2_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos)                     /*!< GPIO_PORT NOT2: NOTP30 Mask         */
+#define GPIO_PORT_NOT2_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT2: NOTP31 Position     */
+#define GPIO_PORT_NOT2_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos)                     /*!< GPIO_PORT NOT2: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT3  -----------------------------------------
+#define GPIO_PORT_NOT3_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT3: NOTP0 Position      */
+#define GPIO_PORT_NOT3_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos)                      /*!< GPIO_PORT NOT3: NOTP0 Mask          */
+#define GPIO_PORT_NOT3_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT3: NOTP1 Position      */
+#define GPIO_PORT_NOT3_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos)                      /*!< GPIO_PORT NOT3: NOTP1 Mask          */
+#define GPIO_PORT_NOT3_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT3: NOTP2 Position      */
+#define GPIO_PORT_NOT3_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos)                      /*!< GPIO_PORT NOT3: NOTP2 Mask          */
+#define GPIO_PORT_NOT3_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT3: NOTP3 Position      */
+#define GPIO_PORT_NOT3_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos)                      /*!< GPIO_PORT NOT3: NOTP3 Mask          */
+#define GPIO_PORT_NOT3_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT3: NOTP4 Position      */
+#define GPIO_PORT_NOT3_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos)                      /*!< GPIO_PORT NOT3: NOTP4 Mask          */
+#define GPIO_PORT_NOT3_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT3: NOTP5 Position      */
+#define GPIO_PORT_NOT3_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos)                      /*!< GPIO_PORT NOT3: NOTP5 Mask          */
+#define GPIO_PORT_NOT3_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT3: NOTP6 Position      */
+#define GPIO_PORT_NOT3_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos)                      /*!< GPIO_PORT NOT3: NOTP6 Mask          */
+#define GPIO_PORT_NOT3_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT3: NOTP7 Position      */
+#define GPIO_PORT_NOT3_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos)                      /*!< GPIO_PORT NOT3: NOTP7 Mask          */
+#define GPIO_PORT_NOT3_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT3: NOTP8 Position      */
+#define GPIO_PORT_NOT3_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos)                      /*!< GPIO_PORT NOT3: NOTP8 Mask          */
+#define GPIO_PORT_NOT3_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT3: NOTP9 Position      */
+#define GPIO_PORT_NOT3_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos)                      /*!< GPIO_PORT NOT3: NOTP9 Mask          */
+#define GPIO_PORT_NOT3_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT3: NOTP10 Position     */
+#define GPIO_PORT_NOT3_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos)                     /*!< GPIO_PORT NOT3: NOTP10 Mask         */
+#define GPIO_PORT_NOT3_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT3: NOTP11 Position     */
+#define GPIO_PORT_NOT3_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos)                     /*!< GPIO_PORT NOT3: NOTP11 Mask         */
+#define GPIO_PORT_NOT3_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT3: NOTP12 Position     */
+#define GPIO_PORT_NOT3_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos)                     /*!< GPIO_PORT NOT3: NOTP12 Mask         */
+#define GPIO_PORT_NOT3_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT3: NOTP13 Position     */
+#define GPIO_PORT_NOT3_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos)                     /*!< GPIO_PORT NOT3: NOTP13 Mask         */
+#define GPIO_PORT_NOT3_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT3: NOTP14 Position     */
+#define GPIO_PORT_NOT3_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos)                     /*!< GPIO_PORT NOT3: NOTP14 Mask         */
+#define GPIO_PORT_NOT3_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT3: NOTP15 Position     */
+#define GPIO_PORT_NOT3_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos)                     /*!< GPIO_PORT NOT3: NOTP15 Mask         */
+#define GPIO_PORT_NOT3_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT3: NOTP16 Position     */
+#define GPIO_PORT_NOT3_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos)                     /*!< GPIO_PORT NOT3: NOTP16 Mask         */
+#define GPIO_PORT_NOT3_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT3: NOTP17 Position     */
+#define GPIO_PORT_NOT3_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos)                     /*!< GPIO_PORT NOT3: NOTP17 Mask         */
+#define GPIO_PORT_NOT3_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT3: NOTP18 Position     */
+#define GPIO_PORT_NOT3_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos)                     /*!< GPIO_PORT NOT3: NOTP18 Mask         */
+#define GPIO_PORT_NOT3_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT3: NOTP19 Position     */
+#define GPIO_PORT_NOT3_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos)                     /*!< GPIO_PORT NOT3: NOTP19 Mask         */
+#define GPIO_PORT_NOT3_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT3: NOTP20 Position     */
+#define GPIO_PORT_NOT3_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos)                     /*!< GPIO_PORT NOT3: NOTP20 Mask         */
+#define GPIO_PORT_NOT3_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT3: NOTP21 Position     */
+#define GPIO_PORT_NOT3_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos)                     /*!< GPIO_PORT NOT3: NOTP21 Mask         */
+#define GPIO_PORT_NOT3_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT3: NOTP22 Position     */
+#define GPIO_PORT_NOT3_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos)                     /*!< GPIO_PORT NOT3: NOTP22 Mask         */
+#define GPIO_PORT_NOT3_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT3: NOTP23 Position     */
+#define GPIO_PORT_NOT3_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos)                     /*!< GPIO_PORT NOT3: NOTP23 Mask         */
+#define GPIO_PORT_NOT3_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT3: NOTP24 Position     */
+#define GPIO_PORT_NOT3_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos)                     /*!< GPIO_PORT NOT3: NOTP24 Mask         */
+#define GPIO_PORT_NOT3_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT3: NOTP25 Position     */
+#define GPIO_PORT_NOT3_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos)                     /*!< GPIO_PORT NOT3: NOTP25 Mask         */
+#define GPIO_PORT_NOT3_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT3: NOTP26 Position     */
+#define GPIO_PORT_NOT3_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos)                     /*!< GPIO_PORT NOT3: NOTP26 Mask         */
+#define GPIO_PORT_NOT3_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT3: NOTP27 Position     */
+#define GPIO_PORT_NOT3_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos)                     /*!< GPIO_PORT NOT3: NOTP27 Mask         */
+#define GPIO_PORT_NOT3_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT3: NOTP28 Position     */
+#define GPIO_PORT_NOT3_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos)                     /*!< GPIO_PORT NOT3: NOTP28 Mask         */
+#define GPIO_PORT_NOT3_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT3: NOTP29 Position     */
+#define GPIO_PORT_NOT3_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos)                     /*!< GPIO_PORT NOT3: NOTP29 Mask         */
+#define GPIO_PORT_NOT3_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT3: NOTP30 Position     */
+#define GPIO_PORT_NOT3_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos)                     /*!< GPIO_PORT NOT3: NOTP30 Mask         */
+#define GPIO_PORT_NOT3_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT3: NOTP31 Position     */
+#define GPIO_PORT_NOT3_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos)                     /*!< GPIO_PORT NOT3: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT4  -----------------------------------------
+#define GPIO_PORT_NOT4_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT4: NOTP0 Position      */
+#define GPIO_PORT_NOT4_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos)                      /*!< GPIO_PORT NOT4: NOTP0 Mask          */
+#define GPIO_PORT_NOT4_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT4: NOTP1 Position      */
+#define GPIO_PORT_NOT4_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos)                      /*!< GPIO_PORT NOT4: NOTP1 Mask          */
+#define GPIO_PORT_NOT4_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT4: NOTP2 Position      */
+#define GPIO_PORT_NOT4_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos)                      /*!< GPIO_PORT NOT4: NOTP2 Mask          */
+#define GPIO_PORT_NOT4_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT4: NOTP3 Position      */
+#define GPIO_PORT_NOT4_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos)                      /*!< GPIO_PORT NOT4: NOTP3 Mask          */
+#define GPIO_PORT_NOT4_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT4: NOTP4 Position      */
+#define GPIO_PORT_NOT4_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos)                      /*!< GPIO_PORT NOT4: NOTP4 Mask          */
+#define GPIO_PORT_NOT4_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT4: NOTP5 Position      */
+#define GPIO_PORT_NOT4_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos)                      /*!< GPIO_PORT NOT4: NOTP5 Mask          */
+#define GPIO_PORT_NOT4_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT4: NOTP6 Position      */
+#define GPIO_PORT_NOT4_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos)                      /*!< GPIO_PORT NOT4: NOTP6 Mask          */
+#define GPIO_PORT_NOT4_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT4: NOTP7 Position      */
+#define GPIO_PORT_NOT4_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos)                      /*!< GPIO_PORT NOT4: NOTP7 Mask          */
+#define GPIO_PORT_NOT4_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT4: NOTP8 Position      */
+#define GPIO_PORT_NOT4_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos)                      /*!< GPIO_PORT NOT4: NOTP8 Mask          */
+#define GPIO_PORT_NOT4_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT4: NOTP9 Position      */
+#define GPIO_PORT_NOT4_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos)                      /*!< GPIO_PORT NOT4: NOTP9 Mask          */
+#define GPIO_PORT_NOT4_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT4: NOTP10 Position     */
+#define GPIO_PORT_NOT4_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos)                     /*!< GPIO_PORT NOT4: NOTP10 Mask         */
+#define GPIO_PORT_NOT4_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT4: NOTP11 Position     */
+#define GPIO_PORT_NOT4_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos)                     /*!< GPIO_PORT NOT4: NOTP11 Mask         */
+#define GPIO_PORT_NOT4_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT4: NOTP12 Position     */
+#define GPIO_PORT_NOT4_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos)                     /*!< GPIO_PORT NOT4: NOTP12 Mask         */
+#define GPIO_PORT_NOT4_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT4: NOTP13 Position     */
+#define GPIO_PORT_NOT4_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos)                     /*!< GPIO_PORT NOT4: NOTP13 Mask         */
+#define GPIO_PORT_NOT4_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT4: NOTP14 Position     */
+#define GPIO_PORT_NOT4_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos)                     /*!< GPIO_PORT NOT4: NOTP14 Mask         */
+#define GPIO_PORT_NOT4_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT4: NOTP15 Position     */
+#define GPIO_PORT_NOT4_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos)                     /*!< GPIO_PORT NOT4: NOTP15 Mask         */
+#define GPIO_PORT_NOT4_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT4: NOTP16 Position     */
+#define GPIO_PORT_NOT4_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos)                     /*!< GPIO_PORT NOT4: NOTP16 Mask         */
+#define GPIO_PORT_NOT4_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT4: NOTP17 Position     */
+#define GPIO_PORT_NOT4_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos)                     /*!< GPIO_PORT NOT4: NOTP17 Mask         */
+#define GPIO_PORT_NOT4_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT4: NOTP18 Position     */
+#define GPIO_PORT_NOT4_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos)                     /*!< GPIO_PORT NOT4: NOTP18 Mask         */
+#define GPIO_PORT_NOT4_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT4: NOTP19 Position     */
+#define GPIO_PORT_NOT4_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos)                     /*!< GPIO_PORT NOT4: NOTP19 Mask         */
+#define GPIO_PORT_NOT4_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT4: NOTP20 Position     */
+#define GPIO_PORT_NOT4_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos)                     /*!< GPIO_PORT NOT4: NOTP20 Mask         */
+#define GPIO_PORT_NOT4_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT4: NOTP21 Position     */
+#define GPIO_PORT_NOT4_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos)                     /*!< GPIO_PORT NOT4: NOTP21 Mask         */
+#define GPIO_PORT_NOT4_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT4: NOTP22 Position     */
+#define GPIO_PORT_NOT4_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos)                     /*!< GPIO_PORT NOT4: NOTP22 Mask         */
+#define GPIO_PORT_NOT4_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT4: NOTP23 Position     */
+#define GPIO_PORT_NOT4_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos)                     /*!< GPIO_PORT NOT4: NOTP23 Mask         */
+#define GPIO_PORT_NOT4_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT4: NOTP24 Position     */
+#define GPIO_PORT_NOT4_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos)                     /*!< GPIO_PORT NOT4: NOTP24 Mask         */
+#define GPIO_PORT_NOT4_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT4: NOTP25 Position     */
+#define GPIO_PORT_NOT4_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos)                     /*!< GPIO_PORT NOT4: NOTP25 Mask         */
+#define GPIO_PORT_NOT4_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT4: NOTP26 Position     */
+#define GPIO_PORT_NOT4_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos)                     /*!< GPIO_PORT NOT4: NOTP26 Mask         */
+#define GPIO_PORT_NOT4_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT4: NOTP27 Position     */
+#define GPIO_PORT_NOT4_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos)                     /*!< GPIO_PORT NOT4: NOTP27 Mask         */
+#define GPIO_PORT_NOT4_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT4: NOTP28 Position     */
+#define GPIO_PORT_NOT4_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos)                     /*!< GPIO_PORT NOT4: NOTP28 Mask         */
+#define GPIO_PORT_NOT4_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT4: NOTP29 Position     */
+#define GPIO_PORT_NOT4_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos)                     /*!< GPIO_PORT NOT4: NOTP29 Mask         */
+#define GPIO_PORT_NOT4_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT4: NOTP30 Position     */
+#define GPIO_PORT_NOT4_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos)                     /*!< GPIO_PORT NOT4: NOTP30 Mask         */
+#define GPIO_PORT_NOT4_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT4: NOTP31 Position     */
+#define GPIO_PORT_NOT4_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos)                     /*!< GPIO_PORT NOT4: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT5  -----------------------------------------
+#define GPIO_PORT_NOT5_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT5: NOTP0 Position      */
+#define GPIO_PORT_NOT5_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos)                      /*!< GPIO_PORT NOT5: NOTP0 Mask          */
+#define GPIO_PORT_NOT5_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT5: NOTP1 Position      */
+#define GPIO_PORT_NOT5_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos)                      /*!< GPIO_PORT NOT5: NOTP1 Mask          */
+#define GPIO_PORT_NOT5_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT5: NOTP2 Position      */
+#define GPIO_PORT_NOT5_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos)                      /*!< GPIO_PORT NOT5: NOTP2 Mask          */
+#define GPIO_PORT_NOT5_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT5: NOTP3 Position      */
+#define GPIO_PORT_NOT5_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos)                      /*!< GPIO_PORT NOT5: NOTP3 Mask          */
+#define GPIO_PORT_NOT5_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT5: NOTP4 Position      */
+#define GPIO_PORT_NOT5_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos)                      /*!< GPIO_PORT NOT5: NOTP4 Mask          */
+#define GPIO_PORT_NOT5_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT5: NOTP5 Position      */
+#define GPIO_PORT_NOT5_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos)                      /*!< GPIO_PORT NOT5: NOTP5 Mask          */
+#define GPIO_PORT_NOT5_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT5: NOTP6 Position      */
+#define GPIO_PORT_NOT5_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos)                      /*!< GPIO_PORT NOT5: NOTP6 Mask          */
+#define GPIO_PORT_NOT5_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT5: NOTP7 Position      */
+#define GPIO_PORT_NOT5_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos)                      /*!< GPIO_PORT NOT5: NOTP7 Mask          */
+#define GPIO_PORT_NOT5_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT5: NOTP8 Position      */
+#define GPIO_PORT_NOT5_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos)                      /*!< GPIO_PORT NOT5: NOTP8 Mask          */
+#define GPIO_PORT_NOT5_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT5: NOTP9 Position      */
+#define GPIO_PORT_NOT5_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos)                      /*!< GPIO_PORT NOT5: NOTP9 Mask          */
+#define GPIO_PORT_NOT5_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT5: NOTP10 Position     */
+#define GPIO_PORT_NOT5_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos)                     /*!< GPIO_PORT NOT5: NOTP10 Mask         */
+#define GPIO_PORT_NOT5_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT5: NOTP11 Position     */
+#define GPIO_PORT_NOT5_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos)                     /*!< GPIO_PORT NOT5: NOTP11 Mask         */
+#define GPIO_PORT_NOT5_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT5: NOTP12 Position     */
+#define GPIO_PORT_NOT5_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos)                     /*!< GPIO_PORT NOT5: NOTP12 Mask         */
+#define GPIO_PORT_NOT5_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT5: NOTP13 Position     */
+#define GPIO_PORT_NOT5_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos)                     /*!< GPIO_PORT NOT5: NOTP13 Mask         */
+#define GPIO_PORT_NOT5_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT5: NOTP14 Position     */
+#define GPIO_PORT_NOT5_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos)                     /*!< GPIO_PORT NOT5: NOTP14 Mask         */
+#define GPIO_PORT_NOT5_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT5: NOTP15 Position     */
+#define GPIO_PORT_NOT5_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos)                     /*!< GPIO_PORT NOT5: NOTP15 Mask         */
+#define GPIO_PORT_NOT5_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT5: NOTP16 Position     */
+#define GPIO_PORT_NOT5_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos)                     /*!< GPIO_PORT NOT5: NOTP16 Mask         */
+#define GPIO_PORT_NOT5_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT5: NOTP17 Position     */
+#define GPIO_PORT_NOT5_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos)                     /*!< GPIO_PORT NOT5: NOTP17 Mask         */
+#define GPIO_PORT_NOT5_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT5: NOTP18 Position     */
+#define GPIO_PORT_NOT5_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos)                     /*!< GPIO_PORT NOT5: NOTP18 Mask         */
+#define GPIO_PORT_NOT5_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT5: NOTP19 Position     */
+#define GPIO_PORT_NOT5_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos)                     /*!< GPIO_PORT NOT5: NOTP19 Mask         */
+#define GPIO_PORT_NOT5_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT5: NOTP20 Position     */
+#define GPIO_PORT_NOT5_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos)                     /*!< GPIO_PORT NOT5: NOTP20 Mask         */
+#define GPIO_PORT_NOT5_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT5: NOTP21 Position     */
+#define GPIO_PORT_NOT5_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos)                     /*!< GPIO_PORT NOT5: NOTP21 Mask         */
+#define GPIO_PORT_NOT5_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT5: NOTP22 Position     */
+#define GPIO_PORT_NOT5_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos)                     /*!< GPIO_PORT NOT5: NOTP22 Mask         */
+#define GPIO_PORT_NOT5_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT5: NOTP23 Position     */
+#define GPIO_PORT_NOT5_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos)                     /*!< GPIO_PORT NOT5: NOTP23 Mask         */
+#define GPIO_PORT_NOT5_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT5: NOTP24 Position     */
+#define GPIO_PORT_NOT5_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos)                     /*!< GPIO_PORT NOT5: NOTP24 Mask         */
+#define GPIO_PORT_NOT5_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT5: NOTP25 Position     */
+#define GPIO_PORT_NOT5_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos)                     /*!< GPIO_PORT NOT5: NOTP25 Mask         */
+#define GPIO_PORT_NOT5_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT5: NOTP26 Position     */
+#define GPIO_PORT_NOT5_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos)                     /*!< GPIO_PORT NOT5: NOTP26 Mask         */
+#define GPIO_PORT_NOT5_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT5: NOTP27 Position     */
+#define GPIO_PORT_NOT5_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos)                     /*!< GPIO_PORT NOT5: NOTP27 Mask         */
+#define GPIO_PORT_NOT5_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT5: NOTP28 Position     */
+#define GPIO_PORT_NOT5_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos)                     /*!< GPIO_PORT NOT5: NOTP28 Mask         */
+#define GPIO_PORT_NOT5_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT5: NOTP29 Position     */
+#define GPIO_PORT_NOT5_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos)                     /*!< GPIO_PORT NOT5: NOTP29 Mask         */
+#define GPIO_PORT_NOT5_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT5: NOTP30 Position     */
+#define GPIO_PORT_NOT5_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos)                     /*!< GPIO_PORT NOT5: NOTP30 Mask         */
+#define GPIO_PORT_NOT5_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT5: NOTP31 Position     */
+#define GPIO_PORT_NOT5_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos)                     /*!< GPIO_PORT NOT5: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT6  -----------------------------------------
+#define GPIO_PORT_NOT6_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT6: NOTP0 Position      */
+#define GPIO_PORT_NOT6_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos)                      /*!< GPIO_PORT NOT6: NOTP0 Mask          */
+#define GPIO_PORT_NOT6_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT6: NOTP1 Position      */
+#define GPIO_PORT_NOT6_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos)                      /*!< GPIO_PORT NOT6: NOTP1 Mask          */
+#define GPIO_PORT_NOT6_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT6: NOTP2 Position      */
+#define GPIO_PORT_NOT6_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos)                      /*!< GPIO_PORT NOT6: NOTP2 Mask          */
+#define GPIO_PORT_NOT6_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT6: NOTP3 Position      */
+#define GPIO_PORT_NOT6_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos)                      /*!< GPIO_PORT NOT6: NOTP3 Mask          */
+#define GPIO_PORT_NOT6_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT6: NOTP4 Position      */
+#define GPIO_PORT_NOT6_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos)                      /*!< GPIO_PORT NOT6: NOTP4 Mask          */
+#define GPIO_PORT_NOT6_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT6: NOTP5 Position      */
+#define GPIO_PORT_NOT6_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos)                      /*!< GPIO_PORT NOT6: NOTP5 Mask          */
+#define GPIO_PORT_NOT6_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT6: NOTP6 Position      */
+#define GPIO_PORT_NOT6_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos)                      /*!< GPIO_PORT NOT6: NOTP6 Mask          */
+#define GPIO_PORT_NOT6_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT6: NOTP7 Position      */
+#define GPIO_PORT_NOT6_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos)                      /*!< GPIO_PORT NOT6: NOTP7 Mask          */
+#define GPIO_PORT_NOT6_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT6: NOTP8 Position      */
+#define GPIO_PORT_NOT6_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos)                      /*!< GPIO_PORT NOT6: NOTP8 Mask          */
+#define GPIO_PORT_NOT6_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT6: NOTP9 Position      */
+#define GPIO_PORT_NOT6_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos)                      /*!< GPIO_PORT NOT6: NOTP9 Mask          */
+#define GPIO_PORT_NOT6_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT6: NOTP10 Position     */
+#define GPIO_PORT_NOT6_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos)                     /*!< GPIO_PORT NOT6: NOTP10 Mask         */
+#define GPIO_PORT_NOT6_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT6: NOTP11 Position     */
+#define GPIO_PORT_NOT6_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos)                     /*!< GPIO_PORT NOT6: NOTP11 Mask         */
+#define GPIO_PORT_NOT6_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT6: NOTP12 Position     */
+#define GPIO_PORT_NOT6_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos)                     /*!< GPIO_PORT NOT6: NOTP12 Mask         */
+#define GPIO_PORT_NOT6_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT6: NOTP13 Position     */
+#define GPIO_PORT_NOT6_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos)                     /*!< GPIO_PORT NOT6: NOTP13 Mask         */
+#define GPIO_PORT_NOT6_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT6: NOTP14 Position     */
+#define GPIO_PORT_NOT6_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos)                     /*!< GPIO_PORT NOT6: NOTP14 Mask         */
+#define GPIO_PORT_NOT6_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT6: NOTP15 Position     */
+#define GPIO_PORT_NOT6_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos)                     /*!< GPIO_PORT NOT6: NOTP15 Mask         */
+#define GPIO_PORT_NOT6_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT6: NOTP16 Position     */
+#define GPIO_PORT_NOT6_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos)                     /*!< GPIO_PORT NOT6: NOTP16 Mask         */
+#define GPIO_PORT_NOT6_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT6: NOTP17 Position     */
+#define GPIO_PORT_NOT6_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos)                     /*!< GPIO_PORT NOT6: NOTP17 Mask         */
+#define GPIO_PORT_NOT6_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT6: NOTP18 Position     */
+#define GPIO_PORT_NOT6_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos)                     /*!< GPIO_PORT NOT6: NOTP18 Mask         */
+#define GPIO_PORT_NOT6_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT6: NOTP19 Position     */
+#define GPIO_PORT_NOT6_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos)                     /*!< GPIO_PORT NOT6: NOTP19 Mask         */
+#define GPIO_PORT_NOT6_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT6: NOTP20 Position     */
+#define GPIO_PORT_NOT6_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos)                     /*!< GPIO_PORT NOT6: NOTP20 Mask         */
+#define GPIO_PORT_NOT6_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT6: NOTP21 Position     */
+#define GPIO_PORT_NOT6_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos)                     /*!< GPIO_PORT NOT6: NOTP21 Mask         */
+#define GPIO_PORT_NOT6_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT6: NOTP22 Position     */
+#define GPIO_PORT_NOT6_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos)                     /*!< GPIO_PORT NOT6: NOTP22 Mask         */
+#define GPIO_PORT_NOT6_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT6: NOTP23 Position     */
+#define GPIO_PORT_NOT6_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos)                     /*!< GPIO_PORT NOT6: NOTP23 Mask         */
+#define GPIO_PORT_NOT6_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT6: NOTP24 Position     */
+#define GPIO_PORT_NOT6_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos)                     /*!< GPIO_PORT NOT6: NOTP24 Mask         */
+#define GPIO_PORT_NOT6_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT6: NOTP25 Position     */
+#define GPIO_PORT_NOT6_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos)                     /*!< GPIO_PORT NOT6: NOTP25 Mask         */
+#define GPIO_PORT_NOT6_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT6: NOTP26 Position     */
+#define GPIO_PORT_NOT6_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos)                     /*!< GPIO_PORT NOT6: NOTP26 Mask         */
+#define GPIO_PORT_NOT6_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT6: NOTP27 Position     */
+#define GPIO_PORT_NOT6_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos)                     /*!< GPIO_PORT NOT6: NOTP27 Mask         */
+#define GPIO_PORT_NOT6_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT6: NOTP28 Position     */
+#define GPIO_PORT_NOT6_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos)                     /*!< GPIO_PORT NOT6: NOTP28 Mask         */
+#define GPIO_PORT_NOT6_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT6: NOTP29 Position     */
+#define GPIO_PORT_NOT6_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos)                     /*!< GPIO_PORT NOT6: NOTP29 Mask         */
+#define GPIO_PORT_NOT6_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT6: NOTP30 Position     */
+#define GPIO_PORT_NOT6_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos)                     /*!< GPIO_PORT NOT6: NOTP30 Mask         */
+#define GPIO_PORT_NOT6_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT6: NOTP31 Position     */
+#define GPIO_PORT_NOT6_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos)                     /*!< GPIO_PORT NOT6: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT7  -----------------------------------------
+#define GPIO_PORT_NOT7_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT7: NOTP0 Position      */
+#define GPIO_PORT_NOT7_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos)                      /*!< GPIO_PORT NOT7: NOTP0 Mask          */
+#define GPIO_PORT_NOT7_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT7: NOTP1 Position      */
+#define GPIO_PORT_NOT7_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos)                      /*!< GPIO_PORT NOT7: NOTP1 Mask          */
+#define GPIO_PORT_NOT7_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT7: NOTP2 Position      */
+#define GPIO_PORT_NOT7_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos)                      /*!< GPIO_PORT NOT7: NOTP2 Mask          */
+#define GPIO_PORT_NOT7_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT7: NOTP3 Position      */
+#define GPIO_PORT_NOT7_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos)                      /*!< GPIO_PORT NOT7: NOTP3 Mask          */
+#define GPIO_PORT_NOT7_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT7: NOTP4 Position      */
+#define GPIO_PORT_NOT7_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos)                      /*!< GPIO_PORT NOT7: NOTP4 Mask          */
+#define GPIO_PORT_NOT7_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT7: NOTP5 Position      */
+#define GPIO_PORT_NOT7_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos)                      /*!< GPIO_PORT NOT7: NOTP5 Mask          */
+#define GPIO_PORT_NOT7_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT7: NOTP6 Position      */
+#define GPIO_PORT_NOT7_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos)                      /*!< GPIO_PORT NOT7: NOTP6 Mask          */
+#define GPIO_PORT_NOT7_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT7: NOTP7 Position      */
+#define GPIO_PORT_NOT7_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos)                      /*!< GPIO_PORT NOT7: NOTP7 Mask          */
+#define GPIO_PORT_NOT7_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT7: NOTP8 Position      */
+#define GPIO_PORT_NOT7_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos)                      /*!< GPIO_PORT NOT7: NOTP8 Mask          */
+#define GPIO_PORT_NOT7_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT7: NOTP9 Position      */
+#define GPIO_PORT_NOT7_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos)                      /*!< GPIO_PORT NOT7: NOTP9 Mask          */
+#define GPIO_PORT_NOT7_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT7: NOTP10 Position     */
+#define GPIO_PORT_NOT7_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos)                     /*!< GPIO_PORT NOT7: NOTP10 Mask         */
+#define GPIO_PORT_NOT7_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT7: NOTP11 Position     */
+#define GPIO_PORT_NOT7_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos)                     /*!< GPIO_PORT NOT7: NOTP11 Mask         */
+#define GPIO_PORT_NOT7_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT7: NOTP12 Position     */
+#define GPIO_PORT_NOT7_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos)                     /*!< GPIO_PORT NOT7: NOTP12 Mask         */
+#define GPIO_PORT_NOT7_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT7: NOTP13 Position     */
+#define GPIO_PORT_NOT7_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos)                     /*!< GPIO_PORT NOT7: NOTP13 Mask         */
+#define GPIO_PORT_NOT7_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT7: NOTP14 Position     */
+#define GPIO_PORT_NOT7_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos)                     /*!< GPIO_PORT NOT7: NOTP14 Mask         */
+#define GPIO_PORT_NOT7_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT7: NOTP15 Position     */
+#define GPIO_PORT_NOT7_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos)                     /*!< GPIO_PORT NOT7: NOTP15 Mask         */
+#define GPIO_PORT_NOT7_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT7: NOTP16 Position     */
+#define GPIO_PORT_NOT7_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos)                     /*!< GPIO_PORT NOT7: NOTP16 Mask         */
+#define GPIO_PORT_NOT7_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT7: NOTP17 Position     */
+#define GPIO_PORT_NOT7_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos)                     /*!< GPIO_PORT NOT7: NOTP17 Mask         */
+#define GPIO_PORT_NOT7_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT7: NOTP18 Position     */
+#define GPIO_PORT_NOT7_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos)                     /*!< GPIO_PORT NOT7: NOTP18 Mask         */
+#define GPIO_PORT_NOT7_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT7: NOTP19 Position     */
+#define GPIO_PORT_NOT7_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos)                     /*!< GPIO_PORT NOT7: NOTP19 Mask         */
+#define GPIO_PORT_NOT7_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT7: NOTP20 Position     */
+#define GPIO_PORT_NOT7_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos)                     /*!< GPIO_PORT NOT7: NOTP20 Mask         */
+#define GPIO_PORT_NOT7_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT7: NOTP21 Position     */
+#define GPIO_PORT_NOT7_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos)                     /*!< GPIO_PORT NOT7: NOTP21 Mask         */
+#define GPIO_PORT_NOT7_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT7: NOTP22 Position     */
+#define GPIO_PORT_NOT7_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos)                     /*!< GPIO_PORT NOT7: NOTP22 Mask         */
+#define GPIO_PORT_NOT7_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT7: NOTP23 Position     */
+#define GPIO_PORT_NOT7_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos)                     /*!< GPIO_PORT NOT7: NOTP23 Mask         */
+#define GPIO_PORT_NOT7_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT7: NOTP24 Position     */
+#define GPIO_PORT_NOT7_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos)                     /*!< GPIO_PORT NOT7: NOTP24 Mask         */
+#define GPIO_PORT_NOT7_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT7: NOTP25 Position     */
+#define GPIO_PORT_NOT7_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos)                     /*!< GPIO_PORT NOT7: NOTP25 Mask         */
+#define GPIO_PORT_NOT7_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT7: NOTP26 Position     */
+#define GPIO_PORT_NOT7_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos)                     /*!< GPIO_PORT NOT7: NOTP26 Mask         */
+#define GPIO_PORT_NOT7_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT7: NOTP27 Position     */
+#define GPIO_PORT_NOT7_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos)                     /*!< GPIO_PORT NOT7: NOTP27 Mask         */
+#define GPIO_PORT_NOT7_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT7: NOTP28 Position     */
+#define GPIO_PORT_NOT7_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos)                     /*!< GPIO_PORT NOT7: NOTP28 Mask         */
+#define GPIO_PORT_NOT7_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT7: NOTP29 Position     */
+#define GPIO_PORT_NOT7_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos)                     /*!< GPIO_PORT NOT7: NOTP29 Mask         */
+#define GPIO_PORT_NOT7_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT7: NOTP30 Position     */
+#define GPIO_PORT_NOT7_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos)                     /*!< GPIO_PORT NOT7: NOTP30 Mask         */
+#define GPIO_PORT_NOT7_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT7: NOTP31 Position     */
+#define GPIO_PORT_NOT7_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos)                     /*!< GPIO_PORT NOT7: NOTP31 Mask         */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  SPI Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  SPI_CR  ---------------------------------------------
+#define SPI_CR_BITENABLE_Pos                                  2                                                         /*!< SPI CR: BITENABLE Position          */
+#define SPI_CR_BITENABLE_Msk                                  (0x01UL << SPI_CR_BITENABLE_Pos)                          /*!< SPI CR: BITENABLE Mask              */
+#define SPI_CR_CPHA_Pos                                       3                                                         /*!< SPI CR: CPHA Position               */
+#define SPI_CR_CPHA_Msk                                       (0x01UL << SPI_CR_CPHA_Pos)                               /*!< SPI CR: CPHA Mask                   */
+#define SPI_CR_CPOL_Pos                                       4                                                         /*!< SPI CR: CPOL Position               */
+#define SPI_CR_CPOL_Msk                                       (0x01UL << SPI_CR_CPOL_Pos)                               /*!< SPI CR: CPOL Mask                   */
+#define SPI_CR_MSTR_Pos                                       5                                                         /*!< SPI CR: MSTR Position               */
+#define SPI_CR_MSTR_Msk                                       (0x01UL << SPI_CR_MSTR_Pos)                               /*!< SPI CR: MSTR Mask                   */
+#define SPI_CR_LSBF_Pos                                       6                                                         /*!< SPI CR: LSBF Position               */
+#define SPI_CR_LSBF_Msk                                       (0x01UL << SPI_CR_LSBF_Pos)                               /*!< SPI CR: LSBF Mask                   */
+#define SPI_CR_SPIE_Pos                                       7                                                         /*!< SPI CR: SPIE Position               */
+#define SPI_CR_SPIE_Msk                                       (0x01UL << SPI_CR_SPIE_Pos)                               /*!< SPI CR: SPIE Mask                   */
+#define SPI_CR_BITS_Pos                                       8                                                         /*!< SPI CR: BITS Position               */
+#define SPI_CR_BITS_Msk                                       (0x0fUL << SPI_CR_BITS_Pos)                               /*!< SPI CR: BITS Mask                   */
+
+// -----------------------------------------  SPI_SR  ---------------------------------------------
+#define SPI_SR_ABRT_Pos                                       3                                                         /*!< SPI SR: ABRT Position               */
+#define SPI_SR_ABRT_Msk                                       (0x01UL << SPI_SR_ABRT_Pos)                               /*!< SPI SR: ABRT Mask                   */
+#define SPI_SR_MODF_Pos                                       4                                                         /*!< SPI SR: MODF Position               */
+#define SPI_SR_MODF_Msk                                       (0x01UL << SPI_SR_MODF_Pos)                               /*!< SPI SR: MODF Mask                   */
+#define SPI_SR_ROVR_Pos                                       5                                                         /*!< SPI SR: ROVR Position               */
+#define SPI_SR_ROVR_Msk                                       (0x01UL << SPI_SR_ROVR_Pos)                               /*!< SPI SR: ROVR Mask                   */
+#define SPI_SR_WCOL_Pos                                       6                                                         /*!< SPI SR: WCOL Position               */
+#define SPI_SR_WCOL_Msk                                       (0x01UL << SPI_SR_WCOL_Pos)                               /*!< SPI SR: WCOL Mask                   */
+#define SPI_SR_SPIF_Pos                                       7                                                         /*!< SPI SR: SPIF Position               */
+#define SPI_SR_SPIF_Msk                                       (0x01UL << SPI_SR_SPIF_Pos)                               /*!< SPI SR: SPIF Mask                   */
+
+// -----------------------------------------  SPI_DR  ---------------------------------------------
+#define SPI_DR_DATALOW_Pos                                    0                                                         /*!< SPI DR: DATALOW Position            */
+#define SPI_DR_DATALOW_Msk                                    (0x000000ffUL << SPI_DR_DATALOW_Pos)                      /*!< SPI DR: DATALOW Mask                */
+#define SPI_DR_DATAHIGH_Pos                                   8                                                         /*!< SPI DR: DATAHIGH Position           */
+#define SPI_DR_DATAHIGH_Msk                                   (0x000000ffUL << SPI_DR_DATAHIGH_Pos)                     /*!< SPI DR: DATAHIGH Mask               */
+
+// -----------------------------------------  SPI_CCR  --------------------------------------------
+#define SPI_CCR_COUNTER_Pos                                   0                                                         /*!< SPI CCR: COUNTER Position           */
+#define SPI_CCR_COUNTER_Msk                                   (0x000000ffUL << SPI_CCR_COUNTER_Pos)                     /*!< SPI CCR: COUNTER Mask               */
+
+// -----------------------------------------  SPI_TCR  --------------------------------------------
+#define SPI_TCR_TEST_Pos                                      1                                                         /*!< SPI TCR: TEST Position              */
+#define SPI_TCR_TEST_Msk                                      (0x7fUL << SPI_TCR_TEST_Pos)                              /*!< SPI TCR: TEST Mask                  */
+
+// -----------------------------------------  SPI_TSR  --------------------------------------------
+#define SPI_TSR_ABRT_Pos                                      3                                                         /*!< SPI TSR: ABRT Position              */
+#define SPI_TSR_ABRT_Msk                                      (0x01UL << SPI_TSR_ABRT_Pos)                              /*!< SPI TSR: ABRT Mask                  */
+#define SPI_TSR_MODF_Pos                                      4                                                         /*!< SPI TSR: MODF Position              */
+#define SPI_TSR_MODF_Msk                                      (0x01UL << SPI_TSR_MODF_Pos)                              /*!< SPI TSR: MODF Mask                  */
+#define SPI_TSR_ROVR_Pos                                      5                                                         /*!< SPI TSR: ROVR Position              */
+#define SPI_TSR_ROVR_Msk                                      (0x01UL << SPI_TSR_ROVR_Pos)                              /*!< SPI TSR: ROVR Mask                  */
+#define SPI_TSR_WCOL_Pos                                      6                                                         /*!< SPI TSR: WCOL Position              */
+#define SPI_TSR_WCOL_Msk                                      (0x01UL << SPI_TSR_WCOL_Pos)                              /*!< SPI TSR: WCOL Mask                  */
+#define SPI_TSR_SPIF_Pos                                      7                                                         /*!< SPI TSR: SPIF Position              */
+#define SPI_TSR_SPIF_Msk                                      (0x01UL << SPI_TSR_SPIF_Pos)                              /*!< SPI TSR: SPIF Mask                  */
+
+// -----------------------------------------  SPI_INT  --------------------------------------------
+#define SPI_INT_SPIF_Pos                                      0                                                         /*!< SPI INT: SPIF Position              */
+#define SPI_INT_SPIF_Msk                                      (0x01UL << SPI_INT_SPIF_Pos)                              /*!< SPI INT: SPIF Mask                  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SGPIO Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG0  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG1  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG2  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG3  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG4  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG5  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG6  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG7  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG8  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG9  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG10  --------------------------------------
+#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG11  --------------------------------------
+#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG12  --------------------------------------
+#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG13  --------------------------------------
+#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG14  --------------------------------------
+#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG15  --------------------------------------
+#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Mask  */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG0  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG1  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG2  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG3  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG4  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG5  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG6  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG7  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG8  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG9  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG10  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG11  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG12  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG13  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG14  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG15  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG0  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG1  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG2  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG3  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG4  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG5  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG6  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG7  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG8  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG9  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG10  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG11  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG12  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG13  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG14  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG15  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Mask */
+
+// ---------------------------------------  SGPIO_REG0  -------------------------------------------
+#define SGPIO_REG0_REG_Pos                                    0                                                         /*!< SGPIO REG0: REG Position            */
+#define SGPIO_REG0_REG_Msk                                    (0xffffffffUL << SGPIO_REG0_REG_Pos)                      /*!< SGPIO REG0: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG1  -------------------------------------------
+#define SGPIO_REG1_REG_Pos                                    0                                                         /*!< SGPIO REG1: REG Position            */
+#define SGPIO_REG1_REG_Msk                                    (0xffffffffUL << SGPIO_REG1_REG_Pos)                      /*!< SGPIO REG1: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG2  -------------------------------------------
+#define SGPIO_REG2_REG_Pos                                    0                                                         /*!< SGPIO REG2: REG Position            */
+#define SGPIO_REG2_REG_Msk                                    (0xffffffffUL << SGPIO_REG2_REG_Pos)                      /*!< SGPIO REG2: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG3  -------------------------------------------
+#define SGPIO_REG3_REG_Pos                                    0                                                         /*!< SGPIO REG3: REG Position            */
+#define SGPIO_REG3_REG_Msk                                    (0xffffffffUL << SGPIO_REG3_REG_Pos)                      /*!< SGPIO REG3: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG4  -------------------------------------------
+#define SGPIO_REG4_REG_Pos                                    0                                                         /*!< SGPIO REG4: REG Position            */
+#define SGPIO_REG4_REG_Msk                                    (0xffffffffUL << SGPIO_REG4_REG_Pos)                      /*!< SGPIO REG4: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG5  -------------------------------------------
+#define SGPIO_REG5_REG_Pos                                    0                                                         /*!< SGPIO REG5: REG Position            */
+#define SGPIO_REG5_REG_Msk                                    (0xffffffffUL << SGPIO_REG5_REG_Pos)                      /*!< SGPIO REG5: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG6  -------------------------------------------
+#define SGPIO_REG6_REG_Pos                                    0                                                         /*!< SGPIO REG6: REG Position            */
+#define SGPIO_REG6_REG_Msk                                    (0xffffffffUL << SGPIO_REG6_REG_Pos)                      /*!< SGPIO REG6: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG7  -------------------------------------------
+#define SGPIO_REG7_REG_Pos                                    0                                                         /*!< SGPIO REG7: REG Position            */
+#define SGPIO_REG7_REG_Msk                                    (0xffffffffUL << SGPIO_REG7_REG_Pos)                      /*!< SGPIO REG7: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG8  -------------------------------------------
+#define SGPIO_REG8_REG_Pos                                    0                                                         /*!< SGPIO REG8: REG Position            */
+#define SGPIO_REG8_REG_Msk                                    (0xffffffffUL << SGPIO_REG8_REG_Pos)                      /*!< SGPIO REG8: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG9  -------------------------------------------
+#define SGPIO_REG9_REG_Pos                                    0                                                         /*!< SGPIO REG9: REG Position            */
+#define SGPIO_REG9_REG_Msk                                    (0xffffffffUL << SGPIO_REG9_REG_Pos)                      /*!< SGPIO REG9: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG10  ------------------------------------------
+#define SGPIO_REG10_REG_Pos                                   0                                                         /*!< SGPIO REG10: REG Position           */
+#define SGPIO_REG10_REG_Msk                                   (0xffffffffUL << SGPIO_REG10_REG_Pos)                     /*!< SGPIO REG10: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG11  ------------------------------------------
+#define SGPIO_REG11_REG_Pos                                   0                                                         /*!< SGPIO REG11: REG Position           */
+#define SGPIO_REG11_REG_Msk                                   (0xffffffffUL << SGPIO_REG11_REG_Pos)                     /*!< SGPIO REG11: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG12  ------------------------------------------
+#define SGPIO_REG12_REG_Pos                                   0                                                         /*!< SGPIO REG12: REG Position           */
+#define SGPIO_REG12_REG_Msk                                   (0xffffffffUL << SGPIO_REG12_REG_Pos)                     /*!< SGPIO REG12: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG13  ------------------------------------------
+#define SGPIO_REG13_REG_Pos                                   0                                                         /*!< SGPIO REG13: REG Position           */
+#define SGPIO_REG13_REG_Msk                                   (0xffffffffUL << SGPIO_REG13_REG_Pos)                     /*!< SGPIO REG13: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG14  ------------------------------------------
+#define SGPIO_REG14_REG_Pos                                   0                                                         /*!< SGPIO REG14: REG Position           */
+#define SGPIO_REG14_REG_Msk                                   (0xffffffffUL << SGPIO_REG14_REG_Pos)                     /*!< SGPIO REG14: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG15  ------------------------------------------
+#define SGPIO_REG15_REG_Pos                                   0                                                         /*!< SGPIO REG15: REG Position           */
+#define SGPIO_REG15_REG_Msk                                   (0xffffffffUL << SGPIO_REG15_REG_Pos)                     /*!< SGPIO REG15: REG Mask               */
+
+// --------------------------------------  SGPIO_REG_SS0  -----------------------------------------
+#define SGPIO_REG_SS0_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS0: REG_SS Position      */
+#define SGPIO_REG_SS0_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos)                /*!< SGPIO REG_SS0: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS1  -----------------------------------------
+#define SGPIO_REG_SS1_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS1: REG_SS Position      */
+#define SGPIO_REG_SS1_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos)                /*!< SGPIO REG_SS1: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS2  -----------------------------------------
+#define SGPIO_REG_SS2_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS2: REG_SS Position      */
+#define SGPIO_REG_SS2_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos)                /*!< SGPIO REG_SS2: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS3  -----------------------------------------
+#define SGPIO_REG_SS3_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS3: REG_SS Position      */
+#define SGPIO_REG_SS3_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos)                /*!< SGPIO REG_SS3: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS4  -----------------------------------------
+#define SGPIO_REG_SS4_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS4: REG_SS Position      */
+#define SGPIO_REG_SS4_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos)                /*!< SGPIO REG_SS4: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS5  -----------------------------------------
+#define SGPIO_REG_SS5_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS5: REG_SS Position      */
+#define SGPIO_REG_SS5_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos)                /*!< SGPIO REG_SS5: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS6  -----------------------------------------
+#define SGPIO_REG_SS6_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS6: REG_SS Position      */
+#define SGPIO_REG_SS6_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos)                /*!< SGPIO REG_SS6: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS7  -----------------------------------------
+#define SGPIO_REG_SS7_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS7: REG_SS Position      */
+#define SGPIO_REG_SS7_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos)                /*!< SGPIO REG_SS7: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS8  -----------------------------------------
+#define SGPIO_REG_SS8_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS8: REG_SS Position      */
+#define SGPIO_REG_SS8_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos)                /*!< SGPIO REG_SS8: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS9  -----------------------------------------
+#define SGPIO_REG_SS9_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS9: REG_SS Position      */
+#define SGPIO_REG_SS9_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos)                /*!< SGPIO REG_SS9: REG_SS Mask          */
+
+// -------------------------------------  SGPIO_REG_SS10  -----------------------------------------
+#define SGPIO_REG_SS10_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS10: REG_SS Position     */
+#define SGPIO_REG_SS10_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos)               /*!< SGPIO REG_SS10: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS11  -----------------------------------------
+#define SGPIO_REG_SS11_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS11: REG_SS Position     */
+#define SGPIO_REG_SS11_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos)               /*!< SGPIO REG_SS11: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS12  -----------------------------------------
+#define SGPIO_REG_SS12_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS12: REG_SS Position     */
+#define SGPIO_REG_SS12_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos)               /*!< SGPIO REG_SS12: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS13  -----------------------------------------
+#define SGPIO_REG_SS13_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS13: REG_SS Position     */
+#define SGPIO_REG_SS13_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos)               /*!< SGPIO REG_SS13: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS14  -----------------------------------------
+#define SGPIO_REG_SS14_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS14: REG_SS Position     */
+#define SGPIO_REG_SS14_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos)               /*!< SGPIO REG_SS14: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS15  -----------------------------------------
+#define SGPIO_REG_SS15_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS15: REG_SS Position     */
+#define SGPIO_REG_SS15_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos)               /*!< SGPIO REG_SS15: REG_SS Mask         */
+
+// --------------------------------------  SGPIO_PRESET0  -----------------------------------------
+#define SGPIO_PRESET0_PRESET_Pos                              0                                                         /*!< SGPIO PRESET0: PRESET Position      */
+#define SGPIO_PRESET0_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos)                /*!< SGPIO PRESET0: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET1  -----------------------------------------
+#define SGPIO_PRESET1_PRESET_Pos                              0                                                         /*!< SGPIO PRESET1: PRESET Position      */
+#define SGPIO_PRESET1_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos)                /*!< SGPIO PRESET1: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET2  -----------------------------------------
+#define SGPIO_PRESET2_PRESET_Pos                              0                                                         /*!< SGPIO PRESET2: PRESET Position      */
+#define SGPIO_PRESET2_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos)                /*!< SGPIO PRESET2: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET3  -----------------------------------------
+#define SGPIO_PRESET3_PRESET_Pos                              0                                                         /*!< SGPIO PRESET3: PRESET Position      */
+#define SGPIO_PRESET3_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos)                /*!< SGPIO PRESET3: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET4  -----------------------------------------
+#define SGPIO_PRESET4_PRESET_Pos                              0                                                         /*!< SGPIO PRESET4: PRESET Position      */
+#define SGPIO_PRESET4_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos)                /*!< SGPIO PRESET4: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET5  -----------------------------------------
+#define SGPIO_PRESET5_PRESET_Pos                              0                                                         /*!< SGPIO PRESET5: PRESET Position      */
+#define SGPIO_PRESET5_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos)                /*!< SGPIO PRESET5: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET6  -----------------------------------------
+#define SGPIO_PRESET6_PRESET_Pos                              0                                                         /*!< SGPIO PRESET6: PRESET Position      */
+#define SGPIO_PRESET6_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos)                /*!< SGPIO PRESET6: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET7  -----------------------------------------
+#define SGPIO_PRESET7_PRESET_Pos                              0                                                         /*!< SGPIO PRESET7: PRESET Position      */
+#define SGPIO_PRESET7_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos)                /*!< SGPIO PRESET7: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET8  -----------------------------------------
+#define SGPIO_PRESET8_PRESET_Pos                              0                                                         /*!< SGPIO PRESET8: PRESET Position      */
+#define SGPIO_PRESET8_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos)                /*!< SGPIO PRESET8: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET9  -----------------------------------------
+#define SGPIO_PRESET9_PRESET_Pos                              0                                                         /*!< SGPIO PRESET9: PRESET Position      */
+#define SGPIO_PRESET9_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos)                /*!< SGPIO PRESET9: PRESET Mask          */
+
+// -------------------------------------  SGPIO_PRESET10  -----------------------------------------
+#define SGPIO_PRESET10_PRESET_Pos                             0                                                         /*!< SGPIO PRESET10: PRESET Position     */
+#define SGPIO_PRESET10_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos)               /*!< SGPIO PRESET10: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET11  -----------------------------------------
+#define SGPIO_PRESET11_PRESET_Pos                             0                                                         /*!< SGPIO PRESET11: PRESET Position     */
+#define SGPIO_PRESET11_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos)               /*!< SGPIO PRESET11: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET12  -----------------------------------------
+#define SGPIO_PRESET12_PRESET_Pos                             0                                                         /*!< SGPIO PRESET12: PRESET Position     */
+#define SGPIO_PRESET12_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos)               /*!< SGPIO PRESET12: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET13  -----------------------------------------
+#define SGPIO_PRESET13_PRESET_Pos                             0                                                         /*!< SGPIO PRESET13: PRESET Position     */
+#define SGPIO_PRESET13_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos)               /*!< SGPIO PRESET13: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET14  -----------------------------------------
+#define SGPIO_PRESET14_PRESET_Pos                             0                                                         /*!< SGPIO PRESET14: PRESET Position     */
+#define SGPIO_PRESET14_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos)               /*!< SGPIO PRESET14: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET15  -----------------------------------------
+#define SGPIO_PRESET15_PRESET_Pos                             0                                                         /*!< SGPIO PRESET15: PRESET Position     */
+#define SGPIO_PRESET15_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos)               /*!< SGPIO PRESET15: PRESET Mask         */
+
+// --------------------------------------  SGPIO_COUNT0  ------------------------------------------
+#define SGPIO_COUNT0_COUNT_Pos                                0                                                         /*!< SGPIO COUNT0: COUNT Position        */
+#define SGPIO_COUNT0_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos)                  /*!< SGPIO COUNT0: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT1  ------------------------------------------
+#define SGPIO_COUNT1_COUNT_Pos                                0                                                         /*!< SGPIO COUNT1: COUNT Position        */
+#define SGPIO_COUNT1_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos)                  /*!< SGPIO COUNT1: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT2  ------------------------------------------
+#define SGPIO_COUNT2_COUNT_Pos                                0                                                         /*!< SGPIO COUNT2: COUNT Position        */
+#define SGPIO_COUNT2_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos)                  /*!< SGPIO COUNT2: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT3  ------------------------------------------
+#define SGPIO_COUNT3_COUNT_Pos                                0                                                         /*!< SGPIO COUNT3: COUNT Position        */
+#define SGPIO_COUNT3_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos)                  /*!< SGPIO COUNT3: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT4  ------------------------------------------
+#define SGPIO_COUNT4_COUNT_Pos                                0                                                         /*!< SGPIO COUNT4: COUNT Position        */
+#define SGPIO_COUNT4_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos)                  /*!< SGPIO COUNT4: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT5  ------------------------------------------
+#define SGPIO_COUNT5_COUNT_Pos                                0                                                         /*!< SGPIO COUNT5: COUNT Position        */
+#define SGPIO_COUNT5_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos)                  /*!< SGPIO COUNT5: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT6  ------------------------------------------
+#define SGPIO_COUNT6_COUNT_Pos                                0                                                         /*!< SGPIO COUNT6: COUNT Position        */
+#define SGPIO_COUNT6_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos)                  /*!< SGPIO COUNT6: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT7  ------------------------------------------
+#define SGPIO_COUNT7_COUNT_Pos                                0                                                         /*!< SGPIO COUNT7: COUNT Position        */
+#define SGPIO_COUNT7_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos)                  /*!< SGPIO COUNT7: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT8  ------------------------------------------
+#define SGPIO_COUNT8_COUNT_Pos                                0                                                         /*!< SGPIO COUNT8: COUNT Position        */
+#define SGPIO_COUNT8_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos)                  /*!< SGPIO COUNT8: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT9  ------------------------------------------
+#define SGPIO_COUNT9_COUNT_Pos                                0                                                         /*!< SGPIO COUNT9: COUNT Position        */
+#define SGPIO_COUNT9_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos)                  /*!< SGPIO COUNT9: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT10  -----------------------------------------
+#define SGPIO_COUNT10_COUNT_Pos                               0                                                         /*!< SGPIO COUNT10: COUNT Position       */
+#define SGPIO_COUNT10_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos)                 /*!< SGPIO COUNT10: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT11  -----------------------------------------
+#define SGPIO_COUNT11_COUNT_Pos                               0                                                         /*!< SGPIO COUNT11: COUNT Position       */
+#define SGPIO_COUNT11_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos)                 /*!< SGPIO COUNT11: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT12  -----------------------------------------
+#define SGPIO_COUNT12_COUNT_Pos                               0                                                         /*!< SGPIO COUNT12: COUNT Position       */
+#define SGPIO_COUNT12_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos)                 /*!< SGPIO COUNT12: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT13  -----------------------------------------
+#define SGPIO_COUNT13_COUNT_Pos                               0                                                         /*!< SGPIO COUNT13: COUNT Position       */
+#define SGPIO_COUNT13_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos)                 /*!< SGPIO COUNT13: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT14  -----------------------------------------
+#define SGPIO_COUNT14_COUNT_Pos                               0                                                         /*!< SGPIO COUNT14: COUNT Position       */
+#define SGPIO_COUNT14_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos)                 /*!< SGPIO COUNT14: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT15  -----------------------------------------
+#define SGPIO_COUNT15_COUNT_Pos                               0                                                         /*!< SGPIO COUNT15: COUNT Position       */
+#define SGPIO_COUNT15_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos)                 /*!< SGPIO COUNT15: COUNT Mask           */
+
+// ---------------------------------------  SGPIO_POS0  -------------------------------------------
+#define SGPIO_POS0_POS_Pos                                    0                                                         /*!< SGPIO POS0: POS Position            */
+#define SGPIO_POS0_POS_Msk                                    (0x000000ffUL << SGPIO_POS0_POS_Pos)                      /*!< SGPIO POS0: POS Mask                */
+#define SGPIO_POS0_POS_RESET_Pos                              8                                                         /*!< SGPIO POS0: POS_RESET Position      */
+#define SGPIO_POS0_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos)                /*!< SGPIO POS0: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS1  -------------------------------------------
+#define SGPIO_POS1_POS_Pos                                    0                                                         /*!< SGPIO POS1: POS Position            */
+#define SGPIO_POS1_POS_Msk                                    (0x000000ffUL << SGPIO_POS1_POS_Pos)                      /*!< SGPIO POS1: POS Mask                */
+#define SGPIO_POS1_POS_RESET_Pos                              8                                                         /*!< SGPIO POS1: POS_RESET Position      */
+#define SGPIO_POS1_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos)                /*!< SGPIO POS1: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS2  -------------------------------------------
+#define SGPIO_POS2_POS_Pos                                    0                                                         /*!< SGPIO POS2: POS Position            */
+#define SGPIO_POS2_POS_Msk                                    (0x000000ffUL << SGPIO_POS2_POS_Pos)                      /*!< SGPIO POS2: POS Mask                */
+#define SGPIO_POS2_POS_RESET_Pos                              8                                                         /*!< SGPIO POS2: POS_RESET Position      */
+#define SGPIO_POS2_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos)                /*!< SGPIO POS2: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS3  -------------------------------------------
+#define SGPIO_POS3_POS_Pos                                    0                                                         /*!< SGPIO POS3: POS Position            */
+#define SGPIO_POS3_POS_Msk                                    (0x000000ffUL << SGPIO_POS3_POS_Pos)                      /*!< SGPIO POS3: POS Mask                */
+#define SGPIO_POS3_POS_RESET_Pos                              8                                                         /*!< SGPIO POS3: POS_RESET Position      */
+#define SGPIO_POS3_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos)                /*!< SGPIO POS3: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS4  -------------------------------------------
+#define SGPIO_POS4_POS_Pos                                    0                                                         /*!< SGPIO POS4: POS Position            */
+#define SGPIO_POS4_POS_Msk                                    (0x000000ffUL << SGPIO_POS4_POS_Pos)                      /*!< SGPIO POS4: POS Mask                */
+#define SGPIO_POS4_POS_RESET_Pos                              8                                                         /*!< SGPIO POS4: POS_RESET Position      */
+#define SGPIO_POS4_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos)                /*!< SGPIO POS4: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS5  -------------------------------------------
+#define SGPIO_POS5_POS_Pos                                    0                                                         /*!< SGPIO POS5: POS Position            */
+#define SGPIO_POS5_POS_Msk                                    (0x000000ffUL << SGPIO_POS5_POS_Pos)                      /*!< SGPIO POS5: POS Mask                */
+#define SGPIO_POS5_POS_RESET_Pos                              8                                                         /*!< SGPIO POS5: POS_RESET Position      */
+#define SGPIO_POS5_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos)                /*!< SGPIO POS5: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS6  -------------------------------------------
+#define SGPIO_POS6_POS_Pos                                    0                                                         /*!< SGPIO POS6: POS Position            */
+#define SGPIO_POS6_POS_Msk                                    (0x000000ffUL << SGPIO_POS6_POS_Pos)                      /*!< SGPIO POS6: POS Mask                */
+#define SGPIO_POS6_POS_RESET_Pos                              8                                                         /*!< SGPIO POS6: POS_RESET Position      */
+#define SGPIO_POS6_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos)                /*!< SGPIO POS6: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS7  -------------------------------------------
+#define SGPIO_POS7_POS_Pos                                    0                                                         /*!< SGPIO POS7: POS Position            */
+#define SGPIO_POS7_POS_Msk                                    (0x000000ffUL << SGPIO_POS7_POS_Pos)                      /*!< SGPIO POS7: POS Mask                */
+#define SGPIO_POS7_POS_RESET_Pos                              8                                                         /*!< SGPIO POS7: POS_RESET Position      */
+#define SGPIO_POS7_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos)                /*!< SGPIO POS7: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS8  -------------------------------------------
+#define SGPIO_POS8_POS_Pos                                    0                                                         /*!< SGPIO POS8: POS Position            */
+#define SGPIO_POS8_POS_Msk                                    (0x000000ffUL << SGPIO_POS8_POS_Pos)                      /*!< SGPIO POS8: POS Mask                */
+#define SGPIO_POS8_POS_RESET_Pos                              8                                                         /*!< SGPIO POS8: POS_RESET Position      */
+#define SGPIO_POS8_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos)                /*!< SGPIO POS8: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS9  -------------------------------------------
+#define SGPIO_POS9_POS_Pos                                    0                                                         /*!< SGPIO POS9: POS Position            */
+#define SGPIO_POS9_POS_Msk                                    (0x000000ffUL << SGPIO_POS9_POS_Pos)                      /*!< SGPIO POS9: POS Mask                */
+#define SGPIO_POS9_POS_RESET_Pos                              8                                                         /*!< SGPIO POS9: POS_RESET Position      */
+#define SGPIO_POS9_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos)                /*!< SGPIO POS9: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS10  ------------------------------------------
+#define SGPIO_POS10_POS_Pos                                   0                                                         /*!< SGPIO POS10: POS Position           */
+#define SGPIO_POS10_POS_Msk                                   (0x000000ffUL << SGPIO_POS10_POS_Pos)                     /*!< SGPIO POS10: POS Mask               */
+#define SGPIO_POS10_POS_RESET_Pos                             8                                                         /*!< SGPIO POS10: POS_RESET Position     */
+#define SGPIO_POS10_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos)               /*!< SGPIO POS10: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS11  ------------------------------------------
+#define SGPIO_POS11_POS_Pos                                   0                                                         /*!< SGPIO POS11: POS Position           */
+#define SGPIO_POS11_POS_Msk                                   (0x000000ffUL << SGPIO_POS11_POS_Pos)                     /*!< SGPIO POS11: POS Mask               */
+#define SGPIO_POS11_POS_RESET_Pos                             8                                                         /*!< SGPIO POS11: POS_RESET Position     */
+#define SGPIO_POS11_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos)               /*!< SGPIO POS11: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS12  ------------------------------------------
+#define SGPIO_POS12_POS_Pos                                   0                                                         /*!< SGPIO POS12: POS Position           */
+#define SGPIO_POS12_POS_Msk                                   (0x000000ffUL << SGPIO_POS12_POS_Pos)                     /*!< SGPIO POS12: POS Mask               */
+#define SGPIO_POS12_POS_RESET_Pos                             8                                                         /*!< SGPIO POS12: POS_RESET Position     */
+#define SGPIO_POS12_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos)               /*!< SGPIO POS12: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS13  ------------------------------------------
+#define SGPIO_POS13_POS_Pos                                   0                                                         /*!< SGPIO POS13: POS Position           */
+#define SGPIO_POS13_POS_Msk                                   (0x000000ffUL << SGPIO_POS13_POS_Pos)                     /*!< SGPIO POS13: POS Mask               */
+#define SGPIO_POS13_POS_RESET_Pos                             8                                                         /*!< SGPIO POS13: POS_RESET Position     */
+#define SGPIO_POS13_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos)               /*!< SGPIO POS13: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS14  ------------------------------------------
+#define SGPIO_POS14_POS_Pos                                   0                                                         /*!< SGPIO POS14: POS Position           */
+#define SGPIO_POS14_POS_Msk                                   (0x000000ffUL << SGPIO_POS14_POS_Pos)                     /*!< SGPIO POS14: POS Mask               */
+#define SGPIO_POS14_POS_RESET_Pos                             8                                                         /*!< SGPIO POS14: POS_RESET Position     */
+#define SGPIO_POS14_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos)               /*!< SGPIO POS14: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS15  ------------------------------------------
+#define SGPIO_POS15_POS_Pos                                   0                                                         /*!< SGPIO POS15: POS Position           */
+#define SGPIO_POS15_POS_Msk                                   (0x000000ffUL << SGPIO_POS15_POS_Pos)                     /*!< SGPIO POS15: POS Mask               */
+#define SGPIO_POS15_POS_RESET_Pos                             8                                                         /*!< SGPIO POS15: POS_RESET Position     */
+#define SGPIO_POS15_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos)               /*!< SGPIO POS15: POS_RESET Mask         */
+
+// --------------------------------------  SGPIO_MASK_A  ------------------------------------------
+#define SGPIO_MASK_A_MASK_A0_Pos                              0                                                         /*!< SGPIO MASK_A: MASK_A0 Position      */
+#define SGPIO_MASK_A_MASK_A0_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A0_Pos)                      /*!< SGPIO MASK_A: MASK_A0 Mask          */
+#define SGPIO_MASK_A_MASK_A1_Pos                              1                                                         /*!< SGPIO MASK_A: MASK_A1 Position      */
+#define SGPIO_MASK_A_MASK_A1_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A1_Pos)                      /*!< SGPIO MASK_A: MASK_A1 Mask          */
+#define SGPIO_MASK_A_MASK_A2_Pos                              2                                                         /*!< SGPIO MASK_A: MASK_A2 Position      */
+#define SGPIO_MASK_A_MASK_A2_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A2_Pos)                      /*!< SGPIO MASK_A: MASK_A2 Mask          */
+#define SGPIO_MASK_A_MASK_A3_Pos                              3                                                         /*!< SGPIO MASK_A: MASK_A3 Position      */
+#define SGPIO_MASK_A_MASK_A3_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A3_Pos)                      /*!< SGPIO MASK_A: MASK_A3 Mask          */
+#define SGPIO_MASK_A_MASK_A4_Pos                              4                                                         /*!< SGPIO MASK_A: MASK_A4 Position      */
+#define SGPIO_MASK_A_MASK_A4_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A4_Pos)                      /*!< SGPIO MASK_A: MASK_A4 Mask          */
+#define SGPIO_MASK_A_MASK_A5_Pos                              5                                                         /*!< SGPIO MASK_A: MASK_A5 Position      */
+#define SGPIO_MASK_A_MASK_A5_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A5_Pos)                      /*!< SGPIO MASK_A: MASK_A5 Mask          */
+#define SGPIO_MASK_A_MASK_A6_Pos                              6                                                         /*!< SGPIO MASK_A: MASK_A6 Position      */
+#define SGPIO_MASK_A_MASK_A6_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A6_Pos)                      /*!< SGPIO MASK_A: MASK_A6 Mask          */
+#define SGPIO_MASK_A_MASK_A7_Pos                              7                                                         /*!< SGPIO MASK_A: MASK_A7 Position      */
+#define SGPIO_MASK_A_MASK_A7_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A7_Pos)                      /*!< SGPIO MASK_A: MASK_A7 Mask          */
+#define SGPIO_MASK_A_MASK_A8_Pos                              8                                                         /*!< SGPIO MASK_A: MASK_A8 Position      */
+#define SGPIO_MASK_A_MASK_A8_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A8_Pos)                      /*!< SGPIO MASK_A: MASK_A8 Mask          */
+#define SGPIO_MASK_A_MASK_A9_Pos                              9                                                         /*!< SGPIO MASK_A: MASK_A9 Position      */
+#define SGPIO_MASK_A_MASK_A9_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A9_Pos)                      /*!< SGPIO MASK_A: MASK_A9 Mask          */
+#define SGPIO_MASK_A_MASK_A10_Pos                             10                                                        /*!< SGPIO MASK_A: MASK_A10 Position     */
+#define SGPIO_MASK_A_MASK_A10_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A10_Pos)                     /*!< SGPIO MASK_A: MASK_A10 Mask         */
+#define SGPIO_MASK_A_MASK_A11_Pos                             11                                                        /*!< SGPIO MASK_A: MASK_A11 Position     */
+#define SGPIO_MASK_A_MASK_A11_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A11_Pos)                     /*!< SGPIO MASK_A: MASK_A11 Mask         */
+#define SGPIO_MASK_A_MASK_A12_Pos                             12                                                        /*!< SGPIO MASK_A: MASK_A12 Position     */
+#define SGPIO_MASK_A_MASK_A12_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A12_Pos)                     /*!< SGPIO MASK_A: MASK_A12 Mask         */
+#define SGPIO_MASK_A_MASK_A13_Pos                             13                                                        /*!< SGPIO MASK_A: MASK_A13 Position     */
+#define SGPIO_MASK_A_MASK_A13_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A13_Pos)                     /*!< SGPIO MASK_A: MASK_A13 Mask         */
+#define SGPIO_MASK_A_MASK_A14_Pos                             14                                                        /*!< SGPIO MASK_A: MASK_A14 Position     */
+#define SGPIO_MASK_A_MASK_A14_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A14_Pos)                     /*!< SGPIO MASK_A: MASK_A14 Mask         */
+#define SGPIO_MASK_A_MASK_A15_Pos                             15                                                        /*!< SGPIO MASK_A: MASK_A15 Position     */
+#define SGPIO_MASK_A_MASK_A15_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A15_Pos)                     /*!< SGPIO MASK_A: MASK_A15 Mask         */
+#define SGPIO_MASK_A_MASK_A16_Pos                             16                                                        /*!< SGPIO MASK_A: MASK_A16 Position     */
+#define SGPIO_MASK_A_MASK_A16_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A16_Pos)                     /*!< SGPIO MASK_A: MASK_A16 Mask         */
+#define SGPIO_MASK_A_MASK_A17_Pos                             17                                                        /*!< SGPIO MASK_A: MASK_A17 Position     */
+#define SGPIO_MASK_A_MASK_A17_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A17_Pos)                     /*!< SGPIO MASK_A: MASK_A17 Mask         */
+#define SGPIO_MASK_A_MASK_A18_Pos                             18                                                        /*!< SGPIO MASK_A: MASK_A18 Position     */
+#define SGPIO_MASK_A_MASK_A18_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A18_Pos)                     /*!< SGPIO MASK_A: MASK_A18 Mask         */
+#define SGPIO_MASK_A_MASK_A19_Pos                             19                                                        /*!< SGPIO MASK_A: MASK_A19 Position     */
+#define SGPIO_MASK_A_MASK_A19_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A19_Pos)                     /*!< SGPIO MASK_A: MASK_A19 Mask         */
+#define SGPIO_MASK_A_MASK_A20_Pos                             20                                                        /*!< SGPIO MASK_A: MASK_A20 Position     */
+#define SGPIO_MASK_A_MASK_A20_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A20_Pos)                     /*!< SGPIO MASK_A: MASK_A20 Mask         */
+#define SGPIO_MASK_A_MASK_A21_Pos                             21                                                        /*!< SGPIO MASK_A: MASK_A21 Position     */
+#define SGPIO_MASK_A_MASK_A21_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A21_Pos)                     /*!< SGPIO MASK_A: MASK_A21 Mask         */
+#define SGPIO_MASK_A_MASK_A22_Pos                             22                                                        /*!< SGPIO MASK_A: MASK_A22 Position     */
+#define SGPIO_MASK_A_MASK_A22_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A22_Pos)                     /*!< SGPIO MASK_A: MASK_A22 Mask         */
+#define SGPIO_MASK_A_MASK_A23_Pos                             23                                                        /*!< SGPIO MASK_A: MASK_A23 Position     */
+#define SGPIO_MASK_A_MASK_A23_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A23_Pos)                     /*!< SGPIO MASK_A: MASK_A23 Mask         */
+#define SGPIO_MASK_A_MASK_A24_Pos                             24                                                        /*!< SGPIO MASK_A: MASK_A24 Position     */
+#define SGPIO_MASK_A_MASK_A24_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A24_Pos)                     /*!< SGPIO MASK_A: MASK_A24 Mask         */
+#define SGPIO_MASK_A_MASK_A25_Pos                             25                                                        /*!< SGPIO MASK_A: MASK_A25 Position     */
+#define SGPIO_MASK_A_MASK_A25_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A25_Pos)                     /*!< SGPIO MASK_A: MASK_A25 Mask         */
+#define SGPIO_MASK_A_MASK_A26_Pos                             26                                                        /*!< SGPIO MASK_A: MASK_A26 Position     */
+#define SGPIO_MASK_A_MASK_A26_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A26_Pos)                     /*!< SGPIO MASK_A: MASK_A26 Mask         */
+#define SGPIO_MASK_A_MASK_A27_Pos                             27                                                        /*!< SGPIO MASK_A: MASK_A27 Position     */
+#define SGPIO_MASK_A_MASK_A27_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A27_Pos)                     /*!< SGPIO MASK_A: MASK_A27 Mask         */
+#define SGPIO_MASK_A_MASK_A28_Pos                             28                                                        /*!< SGPIO MASK_A: MASK_A28 Position     */
+#define SGPIO_MASK_A_MASK_A28_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A28_Pos)                     /*!< SGPIO MASK_A: MASK_A28 Mask         */
+#define SGPIO_MASK_A_MASK_A29_Pos                             29                                                        /*!< SGPIO MASK_A: MASK_A29 Position     */
+#define SGPIO_MASK_A_MASK_A29_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A29_Pos)                     /*!< SGPIO MASK_A: MASK_A29 Mask         */
+#define SGPIO_MASK_A_MASK_A30_Pos                             30                                                        /*!< SGPIO MASK_A: MASK_A30 Position     */
+#define SGPIO_MASK_A_MASK_A30_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A30_Pos)                     /*!< SGPIO MASK_A: MASK_A30 Mask         */
+#define SGPIO_MASK_A_MASK_A31_Pos                             31                                                        /*!< SGPIO MASK_A: MASK_A31 Position     */
+#define SGPIO_MASK_A_MASK_A31_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A31_Pos)                     /*!< SGPIO MASK_A: MASK_A31 Mask         */
+
+// --------------------------------------  SGPIO_MASK_H  ------------------------------------------
+#define SGPIO_MASK_H_MASK_H0_Pos                              0                                                         /*!< SGPIO MASK_H: MASK_H0 Position      */
+#define SGPIO_MASK_H_MASK_H0_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H0_Pos)                      /*!< SGPIO MASK_H: MASK_H0 Mask          */
+#define SGPIO_MASK_H_MASK_H1_Pos                              1                                                         /*!< SGPIO MASK_H: MASK_H1 Position      */
+#define SGPIO_MASK_H_MASK_H1_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H1_Pos)                      /*!< SGPIO MASK_H: MASK_H1 Mask          */
+#define SGPIO_MASK_H_MASK_H2_Pos                              2                                                         /*!< SGPIO MASK_H: MASK_H2 Position      */
+#define SGPIO_MASK_H_MASK_H2_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H2_Pos)                      /*!< SGPIO MASK_H: MASK_H2 Mask          */
+#define SGPIO_MASK_H_MASK_H3_Pos                              3                                                         /*!< SGPIO MASK_H: MASK_H3 Position      */
+#define SGPIO_MASK_H_MASK_H3_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H3_Pos)                      /*!< SGPIO MASK_H: MASK_H3 Mask          */
+#define SGPIO_MASK_H_MASK_H4_Pos                              4                                                         /*!< SGPIO MASK_H: MASK_H4 Position      */
+#define SGPIO_MASK_H_MASK_H4_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H4_Pos)                      /*!< SGPIO MASK_H: MASK_H4 Mask          */
+#define SGPIO_MASK_H_MASK_H5_Pos                              5                                                         /*!< SGPIO MASK_H: MASK_H5 Position      */
+#define SGPIO_MASK_H_MASK_H5_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H5_Pos)                      /*!< SGPIO MASK_H: MASK_H5 Mask          */
+#define SGPIO_MASK_H_MASK_H6_Pos                              6                                                         /*!< SGPIO MASK_H: MASK_H6 Position      */
+#define SGPIO_MASK_H_MASK_H6_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H6_Pos)                      /*!< SGPIO MASK_H: MASK_H6 Mask          */
+#define SGPIO_MASK_H_MASK_H7_Pos                              7                                                         /*!< SGPIO MASK_H: MASK_H7 Position      */
+#define SGPIO_MASK_H_MASK_H7_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H7_Pos)                      /*!< SGPIO MASK_H: MASK_H7 Mask          */
+#define SGPIO_MASK_H_MASK_H8_Pos                              8                                                         /*!< SGPIO MASK_H: MASK_H8 Position      */
+#define SGPIO_MASK_H_MASK_H8_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H8_Pos)                      /*!< SGPIO MASK_H: MASK_H8 Mask          */
+#define SGPIO_MASK_H_MASK_H9_Pos                              9                                                         /*!< SGPIO MASK_H: MASK_H9 Position      */
+#define SGPIO_MASK_H_MASK_H9_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H9_Pos)                      /*!< SGPIO MASK_H: MASK_H9 Mask          */
+#define SGPIO_MASK_H_MASK_H10_Pos                             10                                                        /*!< SGPIO MASK_H: MASK_H10 Position     */
+#define SGPIO_MASK_H_MASK_H10_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H10_Pos)                     /*!< SGPIO MASK_H: MASK_H10 Mask         */
+#define SGPIO_MASK_H_MASK_H11_Pos                             11                                                        /*!< SGPIO MASK_H: MASK_H11 Position     */
+#define SGPIO_MASK_H_MASK_H11_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H11_Pos)                     /*!< SGPIO MASK_H: MASK_H11 Mask         */
+#define SGPIO_MASK_H_MASK_H12_Pos                             12                                                        /*!< SGPIO MASK_H: MASK_H12 Position     */
+#define SGPIO_MASK_H_MASK_H12_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H12_Pos)                     /*!< SGPIO MASK_H: MASK_H12 Mask         */
+#define SGPIO_MASK_H_MASK_H13_Pos                             13                                                        /*!< SGPIO MASK_H: MASK_H13 Position     */
+#define SGPIO_MASK_H_MASK_H13_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H13_Pos)                     /*!< SGPIO MASK_H: MASK_H13 Mask         */
+#define SGPIO_MASK_H_MASK_H14_Pos                             14                                                        /*!< SGPIO MASK_H: MASK_H14 Position     */
+#define SGPIO_MASK_H_MASK_H14_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H14_Pos)                     /*!< SGPIO MASK_H: MASK_H14 Mask         */
+#define SGPIO_MASK_H_MASK_H15_Pos                             15                                                        /*!< SGPIO MASK_H: MASK_H15 Position     */
+#define SGPIO_MASK_H_MASK_H15_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H15_Pos)                     /*!< SGPIO MASK_H: MASK_H15 Mask         */
+#define SGPIO_MASK_H_MASK_H16_Pos                             16                                                        /*!< SGPIO MASK_H: MASK_H16 Position     */
+#define SGPIO_MASK_H_MASK_H16_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H16_Pos)                     /*!< SGPIO MASK_H: MASK_H16 Mask         */
+#define SGPIO_MASK_H_MASK_H17_Pos                             17                                                        /*!< SGPIO MASK_H: MASK_H17 Position     */
+#define SGPIO_MASK_H_MASK_H17_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H17_Pos)                     /*!< SGPIO MASK_H: MASK_H17 Mask         */
+#define SGPIO_MASK_H_MASK_H18_Pos                             18                                                        /*!< SGPIO MASK_H: MASK_H18 Position     */
+#define SGPIO_MASK_H_MASK_H18_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H18_Pos)                     /*!< SGPIO MASK_H: MASK_H18 Mask         */
+#define SGPIO_MASK_H_MASK_H19_Pos                             19                                                        /*!< SGPIO MASK_H: MASK_H19 Position     */
+#define SGPIO_MASK_H_MASK_H19_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H19_Pos)                     /*!< SGPIO MASK_H: MASK_H19 Mask         */
+#define SGPIO_MASK_H_MASK_H20_Pos                             20                                                        /*!< SGPIO MASK_H: MASK_H20 Position     */
+#define SGPIO_MASK_H_MASK_H20_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H20_Pos)                     /*!< SGPIO MASK_H: MASK_H20 Mask         */
+#define SGPIO_MASK_H_MASK_H21_Pos                             21                                                        /*!< SGPIO MASK_H: MASK_H21 Position     */
+#define SGPIO_MASK_H_MASK_H21_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H21_Pos)                     /*!< SGPIO MASK_H: MASK_H21 Mask         */
+#define SGPIO_MASK_H_MASK_H22_Pos                             22                                                        /*!< SGPIO MASK_H: MASK_H22 Position     */
+#define SGPIO_MASK_H_MASK_H22_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H22_Pos)                     /*!< SGPIO MASK_H: MASK_H22 Mask         */
+#define SGPIO_MASK_H_MASK_H23_Pos                             23                                                        /*!< SGPIO MASK_H: MASK_H23 Position     */
+#define SGPIO_MASK_H_MASK_H23_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H23_Pos)                     /*!< SGPIO MASK_H: MASK_H23 Mask         */
+#define SGPIO_MASK_H_MASK_H24_Pos                             24                                                        /*!< SGPIO MASK_H: MASK_H24 Position     */
+#define SGPIO_MASK_H_MASK_H24_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H24_Pos)                     /*!< SGPIO MASK_H: MASK_H24 Mask         */
+#define SGPIO_MASK_H_MASK_H25_Pos                             25                                                        /*!< SGPIO MASK_H: MASK_H25 Position     */
+#define SGPIO_MASK_H_MASK_H25_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H25_Pos)                     /*!< SGPIO MASK_H: MASK_H25 Mask         */
+#define SGPIO_MASK_H_MASK_H26_Pos                             26                                                        /*!< SGPIO MASK_H: MASK_H26 Position     */
+#define SGPIO_MASK_H_MASK_H26_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H26_Pos)                     /*!< SGPIO MASK_H: MASK_H26 Mask         */
+#define SGPIO_MASK_H_MASK_H27_Pos                             27                                                        /*!< SGPIO MASK_H: MASK_H27 Position     */
+#define SGPIO_MASK_H_MASK_H27_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H27_Pos)                     /*!< SGPIO MASK_H: MASK_H27 Mask         */
+#define SGPIO_MASK_H_MASK_H28_Pos                             28                                                        /*!< SGPIO MASK_H: MASK_H28 Position     */
+#define SGPIO_MASK_H_MASK_H28_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H28_Pos)                     /*!< SGPIO MASK_H: MASK_H28 Mask         */
+#define SGPIO_MASK_H_MASK_H29_Pos                             29                                                        /*!< SGPIO MASK_H: MASK_H29 Position     */
+#define SGPIO_MASK_H_MASK_H29_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H29_Pos)                     /*!< SGPIO MASK_H: MASK_H29 Mask         */
+#define SGPIO_MASK_H_MASK_H30_Pos                             30                                                        /*!< SGPIO MASK_H: MASK_H30 Position     */
+#define SGPIO_MASK_H_MASK_H30_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H30_Pos)                     /*!< SGPIO MASK_H: MASK_H30 Mask         */
+#define SGPIO_MASK_H_MASK_H31_Pos                             31                                                        /*!< SGPIO MASK_H: MASK_H31 Position     */
+#define SGPIO_MASK_H_MASK_H31_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H31_Pos)                     /*!< SGPIO MASK_H: MASK_H31 Mask         */
+
+// --------------------------------------  SGPIO_MASK_I  ------------------------------------------
+#define SGPIO_MASK_I_MASK_I0_Pos                              0                                                         /*!< SGPIO MASK_I: MASK_I0 Position      */
+#define SGPIO_MASK_I_MASK_I0_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I0_Pos)                      /*!< SGPIO MASK_I: MASK_I0 Mask          */
+#define SGPIO_MASK_I_MASK_I1_Pos                              1                                                         /*!< SGPIO MASK_I: MASK_I1 Position      */
+#define SGPIO_MASK_I_MASK_I1_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I1_Pos)                      /*!< SGPIO MASK_I: MASK_I1 Mask          */
+#define SGPIO_MASK_I_MASK_I2_Pos                              2                                                         /*!< SGPIO MASK_I: MASK_I2 Position      */
+#define SGPIO_MASK_I_MASK_I2_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I2_Pos)                      /*!< SGPIO MASK_I: MASK_I2 Mask          */
+#define SGPIO_MASK_I_MASK_I3_Pos                              3                                                         /*!< SGPIO MASK_I: MASK_I3 Position      */
+#define SGPIO_MASK_I_MASK_I3_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I3_Pos)                      /*!< SGPIO MASK_I: MASK_I3 Mask          */
+#define SGPIO_MASK_I_MASK_I4_Pos                              4                                                         /*!< SGPIO MASK_I: MASK_I4 Position      */
+#define SGPIO_MASK_I_MASK_I4_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I4_Pos)                      /*!< SGPIO MASK_I: MASK_I4 Mask          */
+#define SGPIO_MASK_I_MASK_I5_Pos                              5                                                         /*!< SGPIO MASK_I: MASK_I5 Position      */
+#define SGPIO_MASK_I_MASK_I5_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I5_Pos)                      /*!< SGPIO MASK_I: MASK_I5 Mask          */
+#define SGPIO_MASK_I_MASK_I6_Pos                              6                                                         /*!< SGPIO MASK_I: MASK_I6 Position      */
+#define SGPIO_MASK_I_MASK_I6_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I6_Pos)                      /*!< SGPIO MASK_I: MASK_I6 Mask          */
+#define SGPIO_MASK_I_MASK_I7_Pos                              7                                                         /*!< SGPIO MASK_I: MASK_I7 Position      */
+#define SGPIO_MASK_I_MASK_I7_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I7_Pos)                      /*!< SGPIO MASK_I: MASK_I7 Mask          */
+#define SGPIO_MASK_I_MASK_I8_Pos                              8                                                         /*!< SGPIO MASK_I: MASK_I8 Position      */
+#define SGPIO_MASK_I_MASK_I8_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I8_Pos)                      /*!< SGPIO MASK_I: MASK_I8 Mask          */
+#define SGPIO_MASK_I_MASK_I9_Pos                              9                                                         /*!< SGPIO MASK_I: MASK_I9 Position      */
+#define SGPIO_MASK_I_MASK_I9_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I9_Pos)                      /*!< SGPIO MASK_I: MASK_I9 Mask          */
+#define SGPIO_MASK_I_MASK_I10_Pos                             10                                                        /*!< SGPIO MASK_I: MASK_I10 Position     */
+#define SGPIO_MASK_I_MASK_I10_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I10_Pos)                     /*!< SGPIO MASK_I: MASK_I10 Mask         */
+#define SGPIO_MASK_I_MASK_I11_Pos                             11                                                        /*!< SGPIO MASK_I: MASK_I11 Position     */
+#define SGPIO_MASK_I_MASK_I11_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I11_Pos)                     /*!< SGPIO MASK_I: MASK_I11 Mask         */
+#define SGPIO_MASK_I_MASK_I12_Pos                             12                                                        /*!< SGPIO MASK_I: MASK_I12 Position     */
+#define SGPIO_MASK_I_MASK_I12_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I12_Pos)                     /*!< SGPIO MASK_I: MASK_I12 Mask         */
+#define SGPIO_MASK_I_MASK_I13_Pos                             13                                                        /*!< SGPIO MASK_I: MASK_I13 Position     */
+#define SGPIO_MASK_I_MASK_I13_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I13_Pos)                     /*!< SGPIO MASK_I: MASK_I13 Mask         */
+#define SGPIO_MASK_I_MASK_I14_Pos                             14                                                        /*!< SGPIO MASK_I: MASK_I14 Position     */
+#define SGPIO_MASK_I_MASK_I14_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I14_Pos)                     /*!< SGPIO MASK_I: MASK_I14 Mask         */
+#define SGPIO_MASK_I_MASK_I15_Pos                             15                                                        /*!< SGPIO MASK_I: MASK_I15 Position     */
+#define SGPIO_MASK_I_MASK_I15_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I15_Pos)                     /*!< SGPIO MASK_I: MASK_I15 Mask         */
+#define SGPIO_MASK_I_MASK_I16_Pos                             16                                                        /*!< SGPIO MASK_I: MASK_I16 Position     */
+#define SGPIO_MASK_I_MASK_I16_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I16_Pos)                     /*!< SGPIO MASK_I: MASK_I16 Mask         */
+#define SGPIO_MASK_I_MASK_I17_Pos                             17                                                        /*!< SGPIO MASK_I: MASK_I17 Position     */
+#define SGPIO_MASK_I_MASK_I17_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I17_Pos)                     /*!< SGPIO MASK_I: MASK_I17 Mask         */
+#define SGPIO_MASK_I_MASK_I18_Pos                             18                                                        /*!< SGPIO MASK_I: MASK_I18 Position     */
+#define SGPIO_MASK_I_MASK_I18_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I18_Pos)                     /*!< SGPIO MASK_I: MASK_I18 Mask         */
+#define SGPIO_MASK_I_MASK_I19_Pos                             19                                                        /*!< SGPIO MASK_I: MASK_I19 Position     */
+#define SGPIO_MASK_I_MASK_I19_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I19_Pos)                     /*!< SGPIO MASK_I: MASK_I19 Mask         */
+#define SGPIO_MASK_I_MASK_I20_Pos                             20                                                        /*!< SGPIO MASK_I: MASK_I20 Position     */
+#define SGPIO_MASK_I_MASK_I20_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I20_Pos)                     /*!< SGPIO MASK_I: MASK_I20 Mask         */
+#define SGPIO_MASK_I_MASK_I21_Pos                             21                                                        /*!< SGPIO MASK_I: MASK_I21 Position     */
+#define SGPIO_MASK_I_MASK_I21_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I21_Pos)                     /*!< SGPIO MASK_I: MASK_I21 Mask         */
+#define SGPIO_MASK_I_MASK_I22_Pos                             22                                                        /*!< SGPIO MASK_I: MASK_I22 Position     */
+#define SGPIO_MASK_I_MASK_I22_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I22_Pos)                     /*!< SGPIO MASK_I: MASK_I22 Mask         */
+#define SGPIO_MASK_I_MASK_I23_Pos                             23                                                        /*!< SGPIO MASK_I: MASK_I23 Position     */
+#define SGPIO_MASK_I_MASK_I23_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I23_Pos)                     /*!< SGPIO MASK_I: MASK_I23 Mask         */
+#define SGPIO_MASK_I_MASK_I24_Pos                             24                                                        /*!< SGPIO MASK_I: MASK_I24 Position     */
+#define SGPIO_MASK_I_MASK_I24_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I24_Pos)                     /*!< SGPIO MASK_I: MASK_I24 Mask         */
+#define SGPIO_MASK_I_MASK_I25_Pos                             25                                                        /*!< SGPIO MASK_I: MASK_I25 Position     */
+#define SGPIO_MASK_I_MASK_I25_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I25_Pos)                     /*!< SGPIO MASK_I: MASK_I25 Mask         */
+#define SGPIO_MASK_I_MASK_I26_Pos                             26                                                        /*!< SGPIO MASK_I: MASK_I26 Position     */
+#define SGPIO_MASK_I_MASK_I26_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I26_Pos)                     /*!< SGPIO MASK_I: MASK_I26 Mask         */
+#define SGPIO_MASK_I_MASK_I27_Pos                             27                                                        /*!< SGPIO MASK_I: MASK_I27 Position     */
+#define SGPIO_MASK_I_MASK_I27_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I27_Pos)                     /*!< SGPIO MASK_I: MASK_I27 Mask         */
+#define SGPIO_MASK_I_MASK_I28_Pos                             28                                                        /*!< SGPIO MASK_I: MASK_I28 Position     */
+#define SGPIO_MASK_I_MASK_I28_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I28_Pos)                     /*!< SGPIO MASK_I: MASK_I28 Mask         */
+#define SGPIO_MASK_I_MASK_I29_Pos                             29                                                        /*!< SGPIO MASK_I: MASK_I29 Position     */
+#define SGPIO_MASK_I_MASK_I29_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I29_Pos)                     /*!< SGPIO MASK_I: MASK_I29 Mask         */
+#define SGPIO_MASK_I_MASK_I30_Pos                             30                                                        /*!< SGPIO MASK_I: MASK_I30 Position     */
+#define SGPIO_MASK_I_MASK_I30_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I30_Pos)                     /*!< SGPIO MASK_I: MASK_I30 Mask         */
+#define SGPIO_MASK_I_MASK_I31_Pos                             31                                                        /*!< SGPIO MASK_I: MASK_I31 Position     */
+#define SGPIO_MASK_I_MASK_I31_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I31_Pos)                     /*!< SGPIO MASK_I: MASK_I31 Mask         */
+
+// --------------------------------------  SGPIO_MASK_P  ------------------------------------------
+#define SGPIO_MASK_P_MASK_P0_Pos                              0                                                         /*!< SGPIO MASK_P: MASK_P0 Position      */
+#define SGPIO_MASK_P_MASK_P0_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P0_Pos)                      /*!< SGPIO MASK_P: MASK_P0 Mask          */
+#define SGPIO_MASK_P_MASK_P1_Pos                              1                                                         /*!< SGPIO MASK_P: MASK_P1 Position      */
+#define SGPIO_MASK_P_MASK_P1_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P1_Pos)                      /*!< SGPIO MASK_P: MASK_P1 Mask          */
+#define SGPIO_MASK_P_MASK_P2_Pos                              2                                                         /*!< SGPIO MASK_P: MASK_P2 Position      */
+#define SGPIO_MASK_P_MASK_P2_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P2_Pos)                      /*!< SGPIO MASK_P: MASK_P2 Mask          */
+#define SGPIO_MASK_P_MASK_P3_Pos                              3                                                         /*!< SGPIO MASK_P: MASK_P3 Position      */
+#define SGPIO_MASK_P_MASK_P3_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P3_Pos)                      /*!< SGPIO MASK_P: MASK_P3 Mask          */
+#define SGPIO_MASK_P_MASK_P4_Pos                              4                                                         /*!< SGPIO MASK_P: MASK_P4 Position      */
+#define SGPIO_MASK_P_MASK_P4_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P4_Pos)                      /*!< SGPIO MASK_P: MASK_P4 Mask          */
+#define SGPIO_MASK_P_MASK_P5_Pos                              5                                                         /*!< SGPIO MASK_P: MASK_P5 Position      */
+#define SGPIO_MASK_P_MASK_P5_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P5_Pos)                      /*!< SGPIO MASK_P: MASK_P5 Mask          */
+#define SGPIO_MASK_P_MASK_P6_Pos                              6                                                         /*!< SGPIO MASK_P: MASK_P6 Position      */
+#define SGPIO_MASK_P_MASK_P6_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P6_Pos)                      /*!< SGPIO MASK_P: MASK_P6 Mask          */
+#define SGPIO_MASK_P_MASK_P7_Pos                              7                                                         /*!< SGPIO MASK_P: MASK_P7 Position      */
+#define SGPIO_MASK_P_MASK_P7_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P7_Pos)                      /*!< SGPIO MASK_P: MASK_P7 Mask          */
+#define SGPIO_MASK_P_MASK_P8_Pos                              8                                                         /*!< SGPIO MASK_P: MASK_P8 Position      */
+#define SGPIO_MASK_P_MASK_P8_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P8_Pos)                      /*!< SGPIO MASK_P: MASK_P8 Mask          */
+#define SGPIO_MASK_P_MASK_P9_Pos                              9                                                         /*!< SGPIO MASK_P: MASK_P9 Position      */
+#define SGPIO_MASK_P_MASK_P9_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P9_Pos)                      /*!< SGPIO MASK_P: MASK_P9 Mask          */
+#define SGPIO_MASK_P_MASK_P10_Pos                             10                                                        /*!< SGPIO MASK_P: MASK_P10 Position     */
+#define SGPIO_MASK_P_MASK_P10_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P10_Pos)                     /*!< SGPIO MASK_P: MASK_P10 Mask         */
+#define SGPIO_MASK_P_MASK_P11_Pos                             11                                                        /*!< SGPIO MASK_P: MASK_P11 Position     */
+#define SGPIO_MASK_P_MASK_P11_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P11_Pos)                     /*!< SGPIO MASK_P: MASK_P11 Mask         */
+#define SGPIO_MASK_P_MASK_P12_Pos                             12                                                        /*!< SGPIO MASK_P: MASK_P12 Position     */
+#define SGPIO_MASK_P_MASK_P12_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P12_Pos)                     /*!< SGPIO MASK_P: MASK_P12 Mask         */
+#define SGPIO_MASK_P_MASK_P13_Pos                             13                                                        /*!< SGPIO MASK_P: MASK_P13 Position     */
+#define SGPIO_MASK_P_MASK_P13_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P13_Pos)                     /*!< SGPIO MASK_P: MASK_P13 Mask         */
+#define SGPIO_MASK_P_MASK_P14_Pos                             14                                                        /*!< SGPIO MASK_P: MASK_P14 Position     */
+#define SGPIO_MASK_P_MASK_P14_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P14_Pos)                     /*!< SGPIO MASK_P: MASK_P14 Mask         */
+#define SGPIO_MASK_P_MASK_P15_Pos                             15                                                        /*!< SGPIO MASK_P: MASK_P15 Position     */
+#define SGPIO_MASK_P_MASK_P15_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P15_Pos)                     /*!< SGPIO MASK_P: MASK_P15 Mask         */
+#define SGPIO_MASK_P_MASK_P16_Pos                             16                                                        /*!< SGPIO MASK_P: MASK_P16 Position     */
+#define SGPIO_MASK_P_MASK_P16_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P16_Pos)                     /*!< SGPIO MASK_P: MASK_P16 Mask         */
+#define SGPIO_MASK_P_MASK_P17_Pos                             17                                                        /*!< SGPIO MASK_P: MASK_P17 Position     */
+#define SGPIO_MASK_P_MASK_P17_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P17_Pos)                     /*!< SGPIO MASK_P: MASK_P17 Mask         */
+#define SGPIO_MASK_P_MASK_P18_Pos                             18                                                        /*!< SGPIO MASK_P: MASK_P18 Position     */
+#define SGPIO_MASK_P_MASK_P18_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P18_Pos)                     /*!< SGPIO MASK_P: MASK_P18 Mask         */
+#define SGPIO_MASK_P_MASK_P19_Pos                             19                                                        /*!< SGPIO MASK_P: MASK_P19 Position     */
+#define SGPIO_MASK_P_MASK_P19_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P19_Pos)                     /*!< SGPIO MASK_P: MASK_P19 Mask         */
+#define SGPIO_MASK_P_MASK_P20_Pos                             20                                                        /*!< SGPIO MASK_P: MASK_P20 Position     */
+#define SGPIO_MASK_P_MASK_P20_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P20_Pos)                     /*!< SGPIO MASK_P: MASK_P20 Mask         */
+#define SGPIO_MASK_P_MASK_P21_Pos                             21                                                        /*!< SGPIO MASK_P: MASK_P21 Position     */
+#define SGPIO_MASK_P_MASK_P21_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P21_Pos)                     /*!< SGPIO MASK_P: MASK_P21 Mask         */
+#define SGPIO_MASK_P_MASK_P22_Pos                             22                                                        /*!< SGPIO MASK_P: MASK_P22 Position     */
+#define SGPIO_MASK_P_MASK_P22_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P22_Pos)                     /*!< SGPIO MASK_P: MASK_P22 Mask         */
+#define SGPIO_MASK_P_MASK_P23_Pos                             23                                                        /*!< SGPIO MASK_P: MASK_P23 Position     */
+#define SGPIO_MASK_P_MASK_P23_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P23_Pos)                     /*!< SGPIO MASK_P: MASK_P23 Mask         */
+#define SGPIO_MASK_P_MASK_P24_Pos                             24                                                        /*!< SGPIO MASK_P: MASK_P24 Position     */
+#define SGPIO_MASK_P_MASK_P24_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P24_Pos)                     /*!< SGPIO MASK_P: MASK_P24 Mask         */
+#define SGPIO_MASK_P_MASK_P25_Pos                             25                                                        /*!< SGPIO MASK_P: MASK_P25 Position     */
+#define SGPIO_MASK_P_MASK_P25_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P25_Pos)                     /*!< SGPIO MASK_P: MASK_P25 Mask         */
+#define SGPIO_MASK_P_MASK_P26_Pos                             26                                                        /*!< SGPIO MASK_P: MASK_P26 Position     */
+#define SGPIO_MASK_P_MASK_P26_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P26_Pos)                     /*!< SGPIO MASK_P: MASK_P26 Mask         */
+#define SGPIO_MASK_P_MASK_P27_Pos                             27                                                        /*!< SGPIO MASK_P: MASK_P27 Position     */
+#define SGPIO_MASK_P_MASK_P27_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P27_Pos)                     /*!< SGPIO MASK_P: MASK_P27 Mask         */
+#define SGPIO_MASK_P_MASK_P28_Pos                             28                                                        /*!< SGPIO MASK_P: MASK_P28 Position     */
+#define SGPIO_MASK_P_MASK_P28_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P28_Pos)                     /*!< SGPIO MASK_P: MASK_P28 Mask         */
+#define SGPIO_MASK_P_MASK_P29_Pos                             29                                                        /*!< SGPIO MASK_P: MASK_P29 Position     */
+#define SGPIO_MASK_P_MASK_P29_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P29_Pos)                     /*!< SGPIO MASK_P: MASK_P29 Mask         */
+#define SGPIO_MASK_P_MASK_P30_Pos                             30                                                        /*!< SGPIO MASK_P: MASK_P30 Position     */
+#define SGPIO_MASK_P_MASK_P30_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P30_Pos)                     /*!< SGPIO MASK_P: MASK_P30 Mask         */
+#define SGPIO_MASK_P_MASK_P31_Pos                             31                                                        /*!< SGPIO MASK_P: MASK_P31 Position     */
+#define SGPIO_MASK_P_MASK_P31_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P31_Pos)                     /*!< SGPIO MASK_P: MASK_P31 Mask         */
+
+// ------------------------------------  SGPIO_GPIO_INREG  ----------------------------------------
+#define SGPIO_GPIO_INREG_GPIO_IN0_Pos                         0                                                         /*!< SGPIO GPIO_INREG: GPIO_IN0 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN0_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN0 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN1_Pos                         1                                                         /*!< SGPIO GPIO_INREG: GPIO_IN1 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN1_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN1 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN2_Pos                         2                                                         /*!< SGPIO GPIO_INREG: GPIO_IN2 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN2_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN2 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN3_Pos                         3                                                         /*!< SGPIO GPIO_INREG: GPIO_IN3 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN3_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN3 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN4_Pos                         4                                                         /*!< SGPIO GPIO_INREG: GPIO_IN4 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN4_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN4 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN5_Pos                         5                                                         /*!< SGPIO GPIO_INREG: GPIO_IN5 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN5_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN5 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN6_Pos                         6                                                         /*!< SGPIO GPIO_INREG: GPIO_IN6 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN6_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN6 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN7_Pos                         7                                                         /*!< SGPIO GPIO_INREG: GPIO_IN7 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN7_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN7 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN8_Pos                         8                                                         /*!< SGPIO GPIO_INREG: GPIO_IN8 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN8_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN8 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN9_Pos                         9                                                         /*!< SGPIO GPIO_INREG: GPIO_IN9 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN9_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN9 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN10_Pos                        10                                                        /*!< SGPIO GPIO_INREG: GPIO_IN10 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN10_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN10 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN11_Pos                        11                                                        /*!< SGPIO GPIO_INREG: GPIO_IN11 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN11_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN11 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN12_Pos                        12                                                        /*!< SGPIO GPIO_INREG: GPIO_IN12 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN12_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN12 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN13_Pos                        13                                                        /*!< SGPIO GPIO_INREG: GPIO_IN13 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN13_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN13 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN14_Pos                        14                                                        /*!< SGPIO GPIO_INREG: GPIO_IN14 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN14_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN14 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN15_Pos                        15                                                        /*!< SGPIO GPIO_INREG: GPIO_IN15 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN15_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN15 Mask    */
+
+// ------------------------------------  SGPIO_GPIO_OUTREG  ---------------------------------------
+#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos                       0                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos                       1                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos                       2                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos                       3                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos                       4                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos                       5                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos                       6                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos                       7                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos                       8                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos                       9                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos                      10                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos                      11                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos                      12                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos                      13                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos                      14                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos                      15                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Mask  */
+
+// ------------------------------------  SGPIO_GPIO_OENREG  ---------------------------------------
+#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos                        0                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE0 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE0 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos                        1                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE1 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE1 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos                        2                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE2 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE2 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos                        3                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE3 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE3 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos                        4                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE4 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE4 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos                        5                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE5 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE5 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos                        6                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE6 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE6 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos                        7                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE7 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE7 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos                        8                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE8 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE8 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos                        9                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE9 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE9 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos                       10                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE10 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE10 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos                       11                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE11 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE11 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos                       12                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE12 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE12 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos                       13                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE13 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE13 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos                       14                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE14 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE14 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos                       15                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE15 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE15 Mask   */
+
+// -----------------------------------  SGPIO_CTRL_ENABLED  ---------------------------------------
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos                  0                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos                  1                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos                  2                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos                  3                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos                  4                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos                  5                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos                  6                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos                  7                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos                  8                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos                  9                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos                 10                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos                 11                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos                 12                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos                 13                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos                 14                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos                 15                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Mask */
+
+// -----------------------------------  SGPIO_CTRL_DISABLED  --------------------------------------
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos               0                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos               1                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos               2                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos               3                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos               4                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos               5                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos               6                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos               7                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos               8                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos               9                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos              10                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos              11                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos              12                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos              13                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos              14                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos              15                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_0  -----------------------------------------
+#define SGPIO_CLR_EN_0_CLR_SCI0_Pos                           0                                                         /*!< SGPIO CLR_EN_0: CLR_SCI0 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI0_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI0 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI1_Pos                           1                                                         /*!< SGPIO CLR_EN_0: CLR_SCI1 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI1_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI1 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI2_Pos                           2                                                         /*!< SGPIO CLR_EN_0: CLR_SCI2 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI2_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI2 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI3_Pos                           3                                                         /*!< SGPIO CLR_EN_0: CLR_SCI3 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI3_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI3 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI4_Pos                           4                                                         /*!< SGPIO CLR_EN_0: CLR_SCI4 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI4_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI4 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI5_Pos                           5                                                         /*!< SGPIO CLR_EN_0: CLR_SCI5 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI5_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI5 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI6_Pos                           6                                                         /*!< SGPIO CLR_EN_0: CLR_SCI6 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI6_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI6 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI7_Pos                           7                                                         /*!< SGPIO CLR_EN_0: CLR_SCI7 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI7_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI7 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI8_Pos                           8                                                         /*!< SGPIO CLR_EN_0: CLR_SCI8 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI8_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI8 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI9_Pos                           9                                                         /*!< SGPIO CLR_EN_0: CLR_SCI9 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI9_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI9 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI10_Pos                          10                                                        /*!< SGPIO CLR_EN_0: CLR_SCI10 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI10_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI10 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI11_Pos                          11                                                        /*!< SGPIO CLR_EN_0: CLR_SCI11 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI11_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI11 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI12_Pos                          12                                                        /*!< SGPIO CLR_EN_0: CLR_SCI12 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI12_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI12 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI13_Pos                          13                                                        /*!< SGPIO CLR_EN_0: CLR_SCI13 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI13_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI13 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI14_Pos                          14                                                        /*!< SGPIO CLR_EN_0: CLR_SCI14 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI14_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI14 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI15_Pos                          15                                                        /*!< SGPIO CLR_EN_0: CLR_SCI15 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI15_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI15 Mask      */
+
+// -------------------------------------  SGPIO_SET_EN_0  -----------------------------------------
+#define SGPIO_SET_EN_0_SET_SCI0_Pos                           0                                                         /*!< SGPIO SET_EN_0: SET_SCI0 Position   */
+#define SGPIO_SET_EN_0_SET_SCI0_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI0 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI1_Pos                           1                                                         /*!< SGPIO SET_EN_0: SET_SCI1 Position   */
+#define SGPIO_SET_EN_0_SET_SCI1_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI1 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI2_Pos                           2                                                         /*!< SGPIO SET_EN_0: SET_SCI2 Position   */
+#define SGPIO_SET_EN_0_SET_SCI2_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI2 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI3_Pos                           3                                                         /*!< SGPIO SET_EN_0: SET_SCI3 Position   */
+#define SGPIO_SET_EN_0_SET_SCI3_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI3 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI4_Pos                           4                                                         /*!< SGPIO SET_EN_0: SET_SCI4 Position   */
+#define SGPIO_SET_EN_0_SET_SCI4_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI4 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI5_Pos                           5                                                         /*!< SGPIO SET_EN_0: SET_SCI5 Position   */
+#define SGPIO_SET_EN_0_SET_SCI5_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI5 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI6_Pos                           6                                                         /*!< SGPIO SET_EN_0: SET_SCI6 Position   */
+#define SGPIO_SET_EN_0_SET_SCI6_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI6 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI7_Pos                           7                                                         /*!< SGPIO SET_EN_0: SET_SCI7 Position   */
+#define SGPIO_SET_EN_0_SET_SCI7_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI7 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI8_Pos                           8                                                         /*!< SGPIO SET_EN_0: SET_SCI8 Position   */
+#define SGPIO_SET_EN_0_SET_SCI8_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI8 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI9_Pos                           9                                                         /*!< SGPIO SET_EN_0: SET_SCI9 Position   */
+#define SGPIO_SET_EN_0_SET_SCI9_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI9 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI10_Pos                          10                                                        /*!< SGPIO SET_EN_0: SET_SCI10 Position  */
+#define SGPIO_SET_EN_0_SET_SCI10_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI10 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI11_Pos                          11                                                        /*!< SGPIO SET_EN_0: SET_SCI11 Position  */
+#define SGPIO_SET_EN_0_SET_SCI11_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI11 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI12_Pos                          12                                                        /*!< SGPIO SET_EN_0: SET_SCI12 Position  */
+#define SGPIO_SET_EN_0_SET_SCI12_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI12 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI13_Pos                          13                                                        /*!< SGPIO SET_EN_0: SET_SCI13 Position  */
+#define SGPIO_SET_EN_0_SET_SCI13_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI13 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI14_Pos                          14                                                        /*!< SGPIO SET_EN_0: SET_SCI14 Position  */
+#define SGPIO_SET_EN_0_SET_SCI14_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI14 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI15_Pos                          15                                                        /*!< SGPIO SET_EN_0: SET_SCI15 Position  */
+#define SGPIO_SET_EN_0_SET_SCI15_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI15 Mask      */
+
+// -------------------------------------  SGPIO_ENABLE_0  -----------------------------------------
+#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos                        0                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI0 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI0 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos                        1                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI1 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI1 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos                        2                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI2 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI2 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos                        3                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI3 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI3 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos                        4                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI4 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI4 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos                        5                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI5 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI5 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos                        6                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI6 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI6 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos                        7                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI7 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI7 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos                        8                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI8 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI8 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos                        9                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI9 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI9 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos                       10                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI10 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI10 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos                       11                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI11 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI11 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos                       12                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI12 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI12 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos                       13                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI13 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI13 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos                       14                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI14 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI14 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos                       15                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI15 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI15 Mask   */
+
+// -------------------------------------  SGPIO_STATUS_0  -----------------------------------------
+#define SGPIO_STATUS_0_STATUS_SCI0_Pos                        0                                                         /*!< SGPIO STATUS_0: STATUS_SCI0 Position */
+#define SGPIO_STATUS_0_STATUS_SCI0_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI0 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI1_Pos                        1                                                         /*!< SGPIO STATUS_0: STATUS_SCI1 Position */
+#define SGPIO_STATUS_0_STATUS_SCI1_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI1 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI2_Pos                        2                                                         /*!< SGPIO STATUS_0: STATUS_SCI2 Position */
+#define SGPIO_STATUS_0_STATUS_SCI2_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI2 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI3_Pos                        3                                                         /*!< SGPIO STATUS_0: STATUS_SCI3 Position */
+#define SGPIO_STATUS_0_STATUS_SCI3_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI3 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI4_Pos                        4                                                         /*!< SGPIO STATUS_0: STATUS_SCI4 Position */
+#define SGPIO_STATUS_0_STATUS_SCI4_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI4 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI5_Pos                        5                                                         /*!< SGPIO STATUS_0: STATUS_SCI5 Position */
+#define SGPIO_STATUS_0_STATUS_SCI5_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI5 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI6_Pos                        6                                                         /*!< SGPIO STATUS_0: STATUS_SCI6 Position */
+#define SGPIO_STATUS_0_STATUS_SCI6_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI6 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI7_Pos                        7                                                         /*!< SGPIO STATUS_0: STATUS_SCI7 Position */
+#define SGPIO_STATUS_0_STATUS_SCI7_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI7 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI8_Pos                        8                                                         /*!< SGPIO STATUS_0: STATUS_SCI8 Position */
+#define SGPIO_STATUS_0_STATUS_SCI8_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI8 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI9_Pos                        9                                                         /*!< SGPIO STATUS_0: STATUS_SCI9 Position */
+#define SGPIO_STATUS_0_STATUS_SCI9_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI9 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI10_Pos                       10                                                        /*!< SGPIO STATUS_0: STATUS_SCI10 Position */
+#define SGPIO_STATUS_0_STATUS_SCI10_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI10 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI11_Pos                       11                                                        /*!< SGPIO STATUS_0: STATUS_SCI11 Position */
+#define SGPIO_STATUS_0_STATUS_SCI11_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI11 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI12_Pos                       12                                                        /*!< SGPIO STATUS_0: STATUS_SCI12 Position */
+#define SGPIO_STATUS_0_STATUS_SCI12_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI12 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI13_Pos                       13                                                        /*!< SGPIO STATUS_0: STATUS_SCI13 Position */
+#define SGPIO_STATUS_0_STATUS_SCI13_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI13 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI14_Pos                       14                                                        /*!< SGPIO STATUS_0: STATUS_SCI14 Position */
+#define SGPIO_STATUS_0_STATUS_SCI14_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI14 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI15_Pos                       15                                                        /*!< SGPIO STATUS_0: STATUS_SCI15 Position */
+#define SGPIO_STATUS_0_STATUS_SCI15_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI15 Mask   */
+
+// -----------------------------------  SGPIO_CTR_STATUS_0  ---------------------------------------
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_0  ---------------------------------------
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_1  -----------------------------------------
+#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos                        0                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos                        1                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos                        2                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos                        3                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos                        4                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos                        5                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos                        6                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos                        7                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos                        8                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos                        9                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos                       10                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos                       11                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos                       12                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos                       13                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos                       14                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos                       15                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Mask   */
+
+// -------------------------------------  SGPIO_SET_EN_1  -----------------------------------------
+#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos                        0                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI0 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI0 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos                        1                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI1 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI1 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos                        2                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI2 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI2 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos                        3                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI3 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI3 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos                        4                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI4 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI4 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos                        5                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI5 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI5 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos                        6                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI6 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI6 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos                        7                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI7 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI7 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos                        8                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI8 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI8 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos                        9                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI9 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI9 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos                       10                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI10 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI10 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos                       11                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI11 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI11 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos                       12                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI12 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI12 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos                       13                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI13 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI13 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos                       14                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI14 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI14 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos                       15                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI15 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI15 Mask   */
+
+// -------------------------------------  SGPIO_ENABLE_1  -----------------------------------------
+#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos                        0                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI0 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI0 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos                        1                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI1 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI1 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos                        2                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI2 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI2 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos                        3                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI3 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI3 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos                        4                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI4 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI4 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos                        5                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI5 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI5 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos                        6                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI6 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI6 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos                        7                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI7 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI7 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos                        8                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI8 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI8 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos                        9                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI9 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI9 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos                       10                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI10 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI10 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos                       11                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI11 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI11 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos                       12                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI12 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI12 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos                       13                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI13 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI13 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos                       14                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI14 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI14 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos                       15                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI15 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI15 Mask   */
+
+// -------------------------------------  SGPIO_STATUS_1  -----------------------------------------
+#define SGPIO_STATUS_1_STATUS_CCI0_Pos                        0                                                         /*!< SGPIO STATUS_1: STATUS_CCI0 Position */
+#define SGPIO_STATUS_1_STATUS_CCI0_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI0 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI1_Pos                        1                                                         /*!< SGPIO STATUS_1: STATUS_CCI1 Position */
+#define SGPIO_STATUS_1_STATUS_CCI1_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI1 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI2_Pos                        2                                                         /*!< SGPIO STATUS_1: STATUS_CCI2 Position */
+#define SGPIO_STATUS_1_STATUS_CCI2_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI2 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI3_Pos                        3                                                         /*!< SGPIO STATUS_1: STATUS_CCI3 Position */
+#define SGPIO_STATUS_1_STATUS_CCI3_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI3 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI4_Pos                        4                                                         /*!< SGPIO STATUS_1: STATUS_CCI4 Position */
+#define SGPIO_STATUS_1_STATUS_CCI4_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI4 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI5_Pos                        5                                                         /*!< SGPIO STATUS_1: STATUS_CCI5 Position */
+#define SGPIO_STATUS_1_STATUS_CCI5_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI5 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI6_Pos                        6                                                         /*!< SGPIO STATUS_1: STATUS_CCI6 Position */
+#define SGPIO_STATUS_1_STATUS_CCI6_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI6 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI7_Pos                        7                                                         /*!< SGPIO STATUS_1: STATUS_CCI7 Position */
+#define SGPIO_STATUS_1_STATUS_CCI7_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI7 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI8_Pos                        8                                                         /*!< SGPIO STATUS_1: STATUS_CCI8 Position */
+#define SGPIO_STATUS_1_STATUS_CCI8_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI8 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI9_Pos                        9                                                         /*!< SGPIO STATUS_1: STATUS_CCI9 Position */
+#define SGPIO_STATUS_1_STATUS_CCI9_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI9 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI10_Pos                       10                                                        /*!< SGPIO STATUS_1: STATUS_CCI10 Position */
+#define SGPIO_STATUS_1_STATUS_CCI10_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI10 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI11_Pos                       11                                                        /*!< SGPIO STATUS_1: STATUS_CCI11 Position */
+#define SGPIO_STATUS_1_STATUS_CCI11_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI11 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI12_Pos                       12                                                        /*!< SGPIO STATUS_1: STATUS_CCI12 Position */
+#define SGPIO_STATUS_1_STATUS_CCI12_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI12 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI13_Pos                       13                                                        /*!< SGPIO STATUS_1: STATUS_CCI13 Position */
+#define SGPIO_STATUS_1_STATUS_CCI13_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI13 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI14_Pos                       14                                                        /*!< SGPIO STATUS_1: STATUS_CCI14 Position */
+#define SGPIO_STATUS_1_STATUS_CCI14_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI14 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI15_Pos                       15                                                        /*!< SGPIO STATUS_1: STATUS_CCI15 Position */
+#define SGPIO_STATUS_1_STATUS_CCI15_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI15 Mask   */
+
+// -----------------------------------  SGPIO_CTR_STATUS_1  ---------------------------------------
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_1  ---------------------------------------
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_2  -----------------------------------------
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos                       0                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos                       1                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos                       2                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos                       3                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos                       4                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos                       5                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos                       6                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos                       7                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos                       8                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos                       9                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos                      10                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos                      11                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos                      12                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos                      13                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos                      14                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos                      15                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Mask  */
+
+// -------------------------------------  SGPIO_SET_EN_2  -----------------------------------------
+#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos                        0                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI0 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI0 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos                        1                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI1 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI1 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos                        2                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI2 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI2 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos                        3                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI3 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI3 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos                        4                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI4 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI4 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos                        5                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI5 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI5 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos                        6                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI6 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI6 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos                        7                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI7 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI7 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos                        8                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI8 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI8 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos                        9                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI9 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI9 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos                       10                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI10 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI10 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos                       11                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI11 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI11 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos                       12                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI12 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI12 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos                       13                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI13 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI13 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos                       14                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI14 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI14 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos                       15                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI15 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI15 Mask   */
+
+// -------------------------------------  SGPIO_ENABLE_2  -----------------------------------------
+#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos                        0                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI0 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI0 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos                        1                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI1 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI1 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos                        2                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI2 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI2 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos                        3                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI3 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI3 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos                        4                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI4 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI4 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos                        5                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI5 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI5 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos                        6                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI6 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI6 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos                        7                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI7 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI7 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos                        8                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI8 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI8 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos                        9                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI9 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI9 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos                       10                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI10 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI10 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos                       11                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI11 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI11 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos                       12                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI12 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI12 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos                       13                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI13 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI13 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos                       14                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI14 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI14 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos                       15                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI15 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI15 Mask   */
+
+// -------------------------------------  SGPIO_STATUS_2  -----------------------------------------
+#define SGPIO_STATUS_2_STATUS_PMI0_Pos                        0                                                         /*!< SGPIO STATUS_2: STATUS_PMI0 Position */
+#define SGPIO_STATUS_2_STATUS_PMI0_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI0 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI1_Pos                        1                                                         /*!< SGPIO STATUS_2: STATUS_PMI1 Position */
+#define SGPIO_STATUS_2_STATUS_PMI1_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI1 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI2_Pos                        2                                                         /*!< SGPIO STATUS_2: STATUS_PMI2 Position */
+#define SGPIO_STATUS_2_STATUS_PMI2_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI2 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI3_Pos                        3                                                         /*!< SGPIO STATUS_2: STATUS_PMI3 Position */
+#define SGPIO_STATUS_2_STATUS_PMI3_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI3 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI4_Pos                        4                                                         /*!< SGPIO STATUS_2: STATUS_PMI4 Position */
+#define SGPIO_STATUS_2_STATUS_PMI4_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI4 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI5_Pos                        5                                                         /*!< SGPIO STATUS_2: STATUS_PMI5 Position */
+#define SGPIO_STATUS_2_STATUS_PMI5_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI5 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI6_Pos                        6                                                         /*!< SGPIO STATUS_2: STATUS_PMI6 Position */
+#define SGPIO_STATUS_2_STATUS_PMI6_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI6 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI7_Pos                        7                                                         /*!< SGPIO STATUS_2: STATUS_PMI7 Position */
+#define SGPIO_STATUS_2_STATUS_PMI7_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI7 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI8_Pos                        8                                                         /*!< SGPIO STATUS_2: STATUS_PMI8 Position */
+#define SGPIO_STATUS_2_STATUS_PMI8_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI8 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI9_Pos                        9                                                         /*!< SGPIO STATUS_2: STATUS_PMI9 Position */
+#define SGPIO_STATUS_2_STATUS_PMI9_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI9 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI10_Pos                       10                                                        /*!< SGPIO STATUS_2: STATUS_PMI10 Position */
+#define SGPIO_STATUS_2_STATUS_PMI10_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI10 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI11_Pos                       11                                                        /*!< SGPIO STATUS_2: STATUS_PMI11 Position */
+#define SGPIO_STATUS_2_STATUS_PMI11_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI11 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI12_Pos                       12                                                        /*!< SGPIO STATUS_2: STATUS_PMI12 Position */
+#define SGPIO_STATUS_2_STATUS_PMI12_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI12 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI13_Pos                       13                                                        /*!< SGPIO STATUS_2: STATUS_PMI13 Position */
+#define SGPIO_STATUS_2_STATUS_PMI13_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI13 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI14_Pos                       14                                                        /*!< SGPIO STATUS_2: STATUS_PMI14 Position */
+#define SGPIO_STATUS_2_STATUS_PMI14_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI14 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI15_Pos                       15                                                        /*!< SGPIO STATUS_2: STATUS_PMI15 Position */
+#define SGPIO_STATUS_2_STATUS_PMI15_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI15 Mask   */
+
+// -----------------------------------  SGPIO_CTR_STATUS_2  ---------------------------------------
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_2  ---------------------------------------
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_3  -----------------------------------------
+#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos                       0                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos                       1                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos                       2                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos                       3                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos                       4                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos                       5                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos                       6                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos                       7                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos                       8                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos                       9                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos                      10                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos                      11                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos                      12                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos                      13                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos                      14                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos                      15                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Mask  */
+
+// -------------------------------------  SGPIO_SET_EN_3  -----------------------------------------
+#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos                       0                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI0 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI0 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos                       1                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI1 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI1 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos                       2                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI2 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI2 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos                       3                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI3 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI3 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos                       4                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI4 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI4 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos                       5                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI5 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI5 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos                       6                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI6 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI6 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos                       7                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI7 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI7 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos                       8                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI8 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI8 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos                       9                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI9 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI9 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos                      10                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI10 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI10 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos                      11                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI11 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI11 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos                      12                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI12 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI12 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos                      13                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI13 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI13 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos                      14                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI14 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI14 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos                      15                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI15 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI15 Mask  */
+
+// -------------------------------------  SGPIO_ENABLE_3  -----------------------------------------
+#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos                      0                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos                      1                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos                      2                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos                      3                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos                      4                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos                      5                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos                      6                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos                      7                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos                      8                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos                      9                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos                     10                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos                     11                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos                     12                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos                     13                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos                     14                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos                     15                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Mask */
+
+// -------------------------------------  SGPIO_STATUS_3  -----------------------------------------
+#define SGPIO_STATUS_3_STATUS_INPI0_Pos                       0                                                         /*!< SGPIO STATUS_3: STATUS_INPI0 Position */
+#define SGPIO_STATUS_3_STATUS_INPI0_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI0 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI1_Pos                       1                                                         /*!< SGPIO STATUS_3: STATUS_INPI1 Position */
+#define SGPIO_STATUS_3_STATUS_INPI1_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI1 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI2_Pos                       2                                                         /*!< SGPIO STATUS_3: STATUS_INPI2 Position */
+#define SGPIO_STATUS_3_STATUS_INPI2_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI2 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI3_Pos                       3                                                         /*!< SGPIO STATUS_3: STATUS_INPI3 Position */
+#define SGPIO_STATUS_3_STATUS_INPI3_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI3 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI4_Pos                       4                                                         /*!< SGPIO STATUS_3: STATUS_INPI4 Position */
+#define SGPIO_STATUS_3_STATUS_INPI4_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI4 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI5_Pos                       5                                                         /*!< SGPIO STATUS_3: STATUS_INPI5 Position */
+#define SGPIO_STATUS_3_STATUS_INPI5_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI5 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI6_Pos                       6                                                         /*!< SGPIO STATUS_3: STATUS_INPI6 Position */
+#define SGPIO_STATUS_3_STATUS_INPI6_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI6 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI7_Pos                       7                                                         /*!< SGPIO STATUS_3: STATUS_INPI7 Position */
+#define SGPIO_STATUS_3_STATUS_INPI7_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI7 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI8_Pos                       8                                                         /*!< SGPIO STATUS_3: STATUS_INPI8 Position */
+#define SGPIO_STATUS_3_STATUS_INPI8_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI8 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI9_Pos                       9                                                         /*!< SGPIO STATUS_3: STATUS_INPI9 Position */
+#define SGPIO_STATUS_3_STATUS_INPI9_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI9 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI10_Pos                      10                                                        /*!< SGPIO STATUS_3: STATUS_INPI10 Position */
+#define SGPIO_STATUS_3_STATUS_INPI10_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI10 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI11_Pos                      11                                                        /*!< SGPIO STATUS_3: STATUS_INPI11 Position */
+#define SGPIO_STATUS_3_STATUS_INPI11_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI11 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI12_Pos                      12                                                        /*!< SGPIO STATUS_3: STATUS_INPI12 Position */
+#define SGPIO_STATUS_3_STATUS_INPI12_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI12 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI13_Pos                      13                                                        /*!< SGPIO STATUS_3: STATUS_INPI13 Position */
+#define SGPIO_STATUS_3_STATUS_INPI13_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI13 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI14_Pos                      14                                                        /*!< SGPIO STATUS_3: STATUS_INPI14 Position */
+#define SGPIO_STATUS_3_STATUS_INPI14_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI14 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI15_Pos                      15                                                        /*!< SGPIO STATUS_3: STATUS_INPI15 Position */
+#define SGPIO_STATUS_3_STATUS_INPI15_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI15 Mask  */
+
+// -----------------------------------  SGPIO_CTR_STATUS_3  ---------------------------------------
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_3  ---------------------------------------
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Mask */
+
+#endif
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 Peripheral memory map                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_SCT_BASE              0x40000000
+#define LPC_GPDMA_BASE            0x40002000
+#define LPC_SDMMC_BASE            0x40004000
+#define LPC_EMC_BASE              0x40005000
+#define LPC_USB0_BASE             0x40006000
+#define LPC_USB1_BASE             0x40007000
+#define LPC_LCD_BASE              0x40008000
+#define LPC_ETHERNET_BASE         0x40010000
+#define LPC_ATIMER_BASE           0x40040000
+#define LPC_REGFILE_BASE          0x40041000
+#define LPC_PMC_BASE              0x40042000
+#define LPC_CREG_BASE             0x40043000
+#define LPC_EVENTROUTER_BASE      0x40044000
+#define LPC_RTC_BASE              0x40046000
+#define LPC_CGU_BASE              0x40050000
+#define LPC_CCU1_BASE             0x40051000
+#define LPC_CCU2_BASE             0x40052000
+#define LPC_RGU_BASE              0x40053000
+#define LPC_WWDT_BASE             0x40080000
+#define LPC_USART0_BASE           0x40081000
+#define LPC_USART2_BASE           0x400C1000
+#define LPC_USART3_BASE           0x400C2000
+#define LPC_UART1_BASE            0x40082000
+#define LPC_SSP0_BASE             0x40083000
+#define LPC_SSP1_BASE             0x400C5000
+#define LPC_TIMER0_BASE           0x40084000
+#define LPC_TIMER1_BASE           0x40085000
+#define LPC_TIMER2_BASE           0x400C3000
+#define LPC_TIMER3_BASE           0x400C4000
+#define LPC_SCU_BASE              0x40086000
+#define LPC_GPIO_PIN_INT_BASE     0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
+#define LPC_MCPWM_BASE            0x400A0000
+#define LPC_I2C0_BASE             0x400A1000
+#define LPC_I2C1_BASE             0x400E0000
+#define LPC_I2S0_BASE             0x400A2000
+#define LPC_I2S1_BASE             0x400A3000
+#define LPC_C_CAN1_BASE           0x400A4000
+#define LPC_RITIMER_BASE          0x400C0000
+#define LPC_QEI_BASE              0x400C6000
+#define LPC_GIMA_BASE             0x400C7000
+#define LPC_DAC_BASE              0x400E1000
+#define LPC_C_CAN0_BASE           0x400E2000
+#define LPC_ADC0_BASE             0x400E3000
+#define LPC_ADC1_BASE             0x400E4000
+#define LPC_GPIO_PORT_BASE        0x400F4000
+#define LPC_SPI_BASE              0x40100000
+#define LPC_SGPIO_BASE            0x40101000
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                Peripheral declaration                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_SCT                   ((LPC_SCT_Type            *) LPC_SCT_BASE)
+#define LPC_GPDMA                 ((LPC_GPDMA_Type          *) LPC_GPDMA_BASE)
+#define LPC_SDMMC                 ((LPC_SDMMC_Type          *) LPC_SDMMC_BASE)
+#define LPC_EMC                   ((LPC_EMC_Type            *) LPC_EMC_BASE)
+#define LPC_USB0                  ((LPC_USB0_Type           *) LPC_USB0_BASE)
+#define LPC_USB1                  ((LPC_USB1_Type           *) LPC_USB1_BASE)
+#define LPC_LCD                   ((LPC_LCD_Type            *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((LPC_ETHERNET_Type       *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER                ((LPC_ATIMER_Type         *) LPC_ATIMER_BASE)
+#define LPC_REGFILE               ((LPC_REGFILE_Type        *) LPC_REGFILE_BASE)
+#define LPC_PMC                   ((LPC_PMC_Type            *) LPC_PMC_BASE)
+#define LPC_CREG                  ((LPC_CREG_Type           *) LPC_CREG_BASE)
+#define LPC_EVENTROUTER           ((LPC_EVENTROUTER_Type    *) LPC_EVENTROUTER_BASE)
+#define LPC_RTC                   ((LPC_RTC_Type            *) LPC_RTC_BASE)
+#define LPC_CGU                   ((LPC_CGU_Type            *) LPC_CGU_BASE)
+#define LPC_CCU1                  ((LPC_CCU1_Type           *) LPC_CCU1_BASE)
+#define LPC_CCU2                  ((LPC_CCU2_Type           *) LPC_CCU2_BASE)
+#define LPC_RGU                   ((LPC_RGU_Type            *) LPC_RGU_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
+#define LPC_USART0                ((LPC_USARTn_Type         *) LPC_USART0_BASE)
+#define LPC_USART2                ((LPC_USARTn_Type         *) LPC_USART2_BASE)
+#define LPC_USART3                ((LPC_USARTn_Type         *) LPC_USART3_BASE)
+#define LPC_UART1                 ((LPC_UART1_Type          *) LPC_UART1_BASE)
+#define LPC_SSP0                  ((LPC_SSPn_Type           *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSPn_Type           *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((LPC_TIMERn_Type         *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((LPC_TIMERn_Type         *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((LPC_TIMERn_Type         *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((LPC_TIMERn_Type         *) LPC_TIMER3_BASE)
+#define LPC_SCU                   ((LPC_SCU_Type            *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM                 ((LPC_MCPWM_Type          *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((LPC_I2Cn_Type           *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((LPC_I2Cn_Type           *) LPC_I2C1_BASE)
+#define LPC_I2S0                  ((LPC_I2Sn_Type           *) LPC_I2S0_BASE)
+#define LPC_I2S1                  ((LPC_I2Sn_Type           *) LPC_I2S1_BASE)
+#define LPC_C_CAN1                ((LPC_C_CANn_Type         *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
+#define LPC_QEI                   ((LPC_QEI_Type            *) LPC_QEI_BASE)
+#define LPC_GIMA                  ((LPC_GIMA_Type           *) LPC_GIMA_BASE)
+#define LPC_DAC                   ((LPC_DAC_Type            *) LPC_DAC_BASE)
+#define LPC_C_CAN0                ((LPC_C_CANn_Type         *) LPC_C_CAN0_BASE)
+#define LPC_ADC0                  ((LPC_ADCn_Type           *) LPC_ADC0_BASE)
+#define LPC_ADC1                  ((LPC_ADCn_Type           *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT             ((LPC_GPIO_PORT_Type      *) LPC_GPIO_PORT_BASE)
+#define LPC_SPI                   ((LPC_SPI_Type            *) LPC_SPI_BASE)
+#define LPC_SGPIO                 ((LPC_SGPIO_Type          *) LPC_SGPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC43xx */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif 
+
+
+#endif  // __LPC43xx_H__
+
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
new file mode 100644
index 0000000000..21204cc535
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
@@ -0,0 +1,33 @@
+/*********************************************************************** 
+ * $Id: fpu_enable.h 
+ * 
+ * Project: LPC43xx 
+ * 
+ * Description: fpu initialization routine header
+ * 
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ * 
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only  
+ * which provides customers with programming information regarding the  
+ * products. This software is supplied "AS IS" without any warranties.  
+ * NXP Semiconductors assumes no responsibility or liability for the 
+ * use of the software, conveys no license or title under any patent, 
+ * copyright, or mask work right to the product. NXP Semiconductors 
+ * reserves the right to make changes in the software without 
+ * notification. NXP Semiconductors also make no representation or 
+ * warranty that such application will be suitable for the specified 
+ * use without further testing or modification. 
+ **********************************************************************/
+
+#ifndef __FPU_ENABLE_H 
+#define __FPU_ENABLE_H 
+
+#if defined(__ARMCC_VERSION)
+void fpuEnable(void) __attribute__ ((section("BOOTSTRAP_CODE")));
+#else
+extern void fpuEnable(void);
+#endif
+
+#endif /* __FPU_ENABLE_H */
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
new file mode 100644
index 0000000000..5b121f1299
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
@@ -0,0 +1,29 @@
+/*********************************************************************** 
+ * $Id: fpu_init.h 
+ * 
+ * Project: LPC43xx 
+ * 
+ * Description: fpu initialization routine header
+ * 
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ * 
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only  
+ * which provides customers with programming information regarding the  
+ * products. This software is supplied "AS IS" without any warranties.  
+ * NXP Semiconductors assumes no responsibility or liability for the 
+ * use of the software, conveys no license or title under any patent, 
+ * copyright, or mask work right to the product. NXP Semiconductors 
+ * reserves the right to make changes in the software without 
+ * notification. NXP Semiconductors also make no representation or 
+ * warranty that such application will be suitable for the specified 
+ * use without further testing or modification. 
+ **********************************************************************/
+
+#ifndef __FPU_INIT_H 
+#define __FPU_INIT_H 
+
+void fpuInit(void);
+
+#endif /* __FPU_INIT_H */
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
new file mode 100644
index 0000000000..6046f8da34
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
@@ -0,0 +1,50 @@
+/**********************************************************************
+* $Id$		system_lpc43xx.h			2011-06-02
+*//**
+* @file		system_lpc43xx.h
+* @brief	Cortex-M3 Device System Header File for NXP lpc43xx Series.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __SYSTEM_lpc43xx_H
+#define __SYSTEM_lpc43xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_lpc43xx_H */
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
new file mode 100644
index 0000000000..8514f36120
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
@@ -0,0 +1,339 @@
+;/***********************************************************************
+; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
+; *
+; * Project: LPC43xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx 
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp              ; 0 Top of Stack
+                DCD     Reset_Handler             ; 1 Reset Handler
+                DCD     NMI_Handler               ; 2 NMI Handler
+                DCD     HardFault_Handler         ; 3 Hard Fault Handler
+                DCD     MemManage_Handler         ; 4 MPU Fault Handler
+                DCD     BusFault_Handler          ; 5 Bus Fault Handler
+                DCD     UsageFault_Handler        ; 6 Usage Fault Handler
+                DCD     Sign_Value                ; 7 Reserved
+                DCD     0                         ; 8 Reserved
+                DCD     0                         ; 9 Reserved
+                DCD     0                         ; 10 Reserved
+                DCD     SVC_Handler               ; 11 SVCall Handler
+                DCD     DebugMon_Handler          ; 12 Debug Monitor Handler
+                DCD     0                         ; 13 Reserved
+                DCD     PendSV_Handler            ; 14 PendSV Handler
+                DCD     SysTick_Handler           ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     DAC_IRQHandler            ; 16 D/A Converter
+                DCD     M0CORE_IRQHandler         ; 17 M0 Core
+                DCD     DMA_IRQHandler            ; 18 General Purpose DMA
+                DCD     EZH_IRQHandler            ; 19 EZH/EDM
+                DCD     FLASH_EEPROM_IRQHandler   ; 20 Reserved for Typhoon
+                DCD     ETH_IRQHandler            ; 21 Ethernet
+                DCD     SDIO_IRQHandler           ; 22 SD/MMC
+                DCD     LCD_IRQHandler            ; 23 LCD
+                DCD     USB0_IRQHandler           ; 24 USB0
+                DCD     USB1_IRQHandler           ; 25 USB1
+                DCD     SCT_IRQHandler            ; 26 State Configurable Timer
+                DCD     RIT_IRQHandler            ; 27 Repetitive Interrupt Timer
+                DCD     TIMER0_IRQHandler         ; 28 Timer0
+                DCD     TIMER1_IRQHandler         ; 29 Timer1
+                DCD     TIMER2_IRQHandler         ; 30 Timer2
+                DCD     TIMER3_IRQHandler         ; 31 Timer3
+                DCD     MCPWM_IRQHandler          ; 32 Motor Control PWM
+                DCD     ADC0_IRQHandler           ; 33 A/D Converter 0
+                DCD     I2C0_IRQHandler           ; 34 I2C0
+                DCD     I2C1_IRQHandler           ; 35 I2C1
+                DCD     SPI_IRQHandler            ; 36 SPI
+                DCD     ADC1_IRQHandler           ; 37 A/D Converter 1
+                DCD     SSP0_IRQHandler           ; 38 SSP0
+                DCD     SSP1_IRQHandler           ; 39 SSP1
+                DCD     UART0_IRQHandler          ; 40 UART0
+                DCD     UART1_IRQHandler          ; 41 UART1
+                DCD     UART2_IRQHandler          ; 42 UART2
+                DCD     UART3_IRQHandler          ; 43 UART3
+                DCD     I2S0_IRQHandler           ; 44 I2S0
+                DCD     I2S1_IRQHandler           ; 45 I2S1
+                DCD     SPIFI_IRQHandler          ; 46 SPI Flash Interface
+                DCD     SGPIO_IRQHandler          ; 47 SGPIO
+                DCD     GPIO0_IRQHandler          ; 48 GPIO0
+                DCD     GPIO1_IRQHandler          ; 49 GPIO1
+                DCD     GPIO2_IRQHandler          ; 50 GPIO2
+                DCD     GPIO3_IRQHandler          ; 51 GPIO3
+                DCD     GPIO4_IRQHandler          ; 52 GPIO4
+                DCD     GPIO5_IRQHandler          ; 53 GPIO5
+                DCD     GPIO6_IRQHandler          ; 54 GPIO6
+                DCD     GPIO7_IRQHandler          ; 55 GPIO7
+                DCD     GINT0_IRQHandler          ; 56 GINT0
+                DCD     GINT1_IRQHandler          ; 57 GINT1
+                DCD     EVRT_IRQHandler           ; 58 Event Router
+                DCD     CAN1_IRQHandler           ; 59 C_CAN1
+                DCD     0                         ; 60 Reserved
+                DCD     VADC_IRQHandler           ; 61 VADC
+                DCD     ATIMER_IRQHandler         ; 62 ATIMER
+                DCD     RTC_IRQHandler            ; 63 RTC
+                DCD     0                         ; 64 Reserved
+                DCD     WDT_IRQHandler            ; 65 WDT
+                DCD     M0s_IRQHandler            ; 66 M0s
+                DCD     CAN0_IRQHandler           ; 67 C_CAN0
+                DCD     QEI_IRQHandler            ; 68 QEI
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DAC_IRQHandler          [WEAK]
+                EXPORT  M0CORE_IRQHandler       [WEAK]
+                EXPORT  DMA_IRQHandler          [WEAK]
+                EXPORT  EZH_IRQHandler          [WEAK]
+                EXPORT  FLASH_EEPROM_IRQHandler [WEAK]
+                EXPORT  ETH_IRQHandler          [WEAK]
+                EXPORT  SDIO_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler          [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  USB1_IRQHandler         [WEAK]
+                EXPORT  SCT_IRQHandler          [WEAK]
+                EXPORT  RIT_IRQHandler          [WEAK]
+                EXPORT  TIMER0_IRQHandler       [WEAK]
+                EXPORT  TIMER1_IRQHandler       [WEAK]
+                EXPORT  TIMER2_IRQHandler       [WEAK]
+                EXPORT  TIMER3_IRQHandler       [WEAK]
+                EXPORT  MCPWM_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  SPI_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler         [WEAK]
+                EXPORT  SSP0_IRQHandler         [WEAK]
+                EXPORT  SSP1_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler        [WEAK]
+                EXPORT  UART1_IRQHandler        [WEAK]
+                EXPORT  UART2_IRQHandler        [WEAK]
+                EXPORT  UART3_IRQHandler        [WEAK]
+                EXPORT  I2S0_IRQHandler         [WEAK]
+                EXPORT  I2S1_IRQHandler         [WEAK]
+                EXPORT  SPIFI_IRQHandler        [WEAK]
+                EXPORT  SGPIO_IRQHandler        [WEAK]
+                EXPORT  GPIO0_IRQHandler        [WEAK]
+                EXPORT  GPIO1_IRQHandler        [WEAK]
+                EXPORT  GPIO2_IRQHandler        [WEAK]
+                EXPORT  GPIO3_IRQHandler        [WEAK]
+                EXPORT  GPIO4_IRQHandler        [WEAK]
+                EXPORT  GPIO5_IRQHandler        [WEAK]
+                EXPORT  GPIO6_IRQHandler        [WEAK]
+                EXPORT  GPIO7_IRQHandler        [WEAK]
+                EXPORT  GINT0_IRQHandler        [WEAK]
+                EXPORT  GINT1_IRQHandler        [WEAK]
+                EXPORT  EVRT_IRQHandler         [WEAK]
+                EXPORT  CAN1_IRQHandler         [WEAK]
+                EXPORT  VADC_IRQHandler         [WEAK]
+                EXPORT  ATIMER_IRQHandler       [WEAK]
+                EXPORT  RTC_IRQHandler          [WEAK]
+                EXPORT  WDT_IRQHandler          [WEAK]
+                EXPORT  M0s_IRQHandler          [WEAK]
+                EXPORT  CAN0_IRQHandler         [WEAK]
+                EXPORT  QEI_IRQHandler          [WEAK]
+
+DAC_IRQHandler
+M0CORE_IRQHandler
+DMA_IRQHandler
+EZH_IRQHandler
+FLASH_EEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+M0s_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                AREA    |.text|,CODE, READONLY
+getPC           PROC
+                EXPORT  getPC
+
+                MOV     R0,LR
+                BX      LR
+
+                ENDP
+
+                END
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
new file mode 100644
index 0000000000..c5a5dbefd9
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
@@ -0,0 +1,255 @@
+;/***********************************************************************
+; * $Id: startup_LPC43xx_M0.s 6473 2011-02-16 17:40:54Z nxp27266 $
+; *
+; * Project: LPC43xx CMSIS Package
+; *
+; * Description: Cortex-M0 Core Device Startup File for the NXP LPC43xx
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp                      ; 0 Top of Stack
+                DCD     Reset_Handler                  ; 1 Reset Handler
+                DCD     NMI_Handler                    ; 2 NMI Handler
+                DCD     HardFault_Handler              ; 3 Hard Fault Handler
+                DCD     0                                 ; 4 Reserved
+                DCD     0                                 ; 5 Reserved
+                DCD     0                                 ; 6 Reserved
+                DCD     0                                 ; 7 Reserved
+                DCD     0                                 ; 8 Reserved
+                DCD     0                                 ; 9 Reserved
+                DCD     0                                 ; 10 Reserved
+                DCD     SVC_Handler                    ; 11 SVCall Handler
+                DCD     DebugMon_Handler               ; 12 Debug Monitor Handler
+                DCD     0                                 ; 13 Reserved
+                DCD     PendSV_Handler                 ; 14 PendSV Handler
+                DCD     SysTick_Handler                ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     RTC_IRQHandler                 ; 16 RTC
+                DCD     M4CORE_IRQHandler              ; 17 M4 Core
+                DCD     DMA_IRQHandler                 ; 18 General Purpose DMA
+                DCD     0                                 ; 19 Reserved
+                DCD     FLASHEEPROMAT_IRQHandler       ; 20 ORed flash bank A, flash bank B, EEPROM, Atimer
+                DCD     ETH_IRQHandler                 ; 21 Ethernet
+                DCD     SDIO_IRQHandler                ; 22 SD/MMC
+                DCD     LCD_IRQHandler                 ; 23 LCD
+                DCD     USB0_IRQHandler                ; 24 USB0
+                DCD     USB1_IRQHandler                ; 25 USB1
+                DCD     SCT_IRQHandler                 ; 26 State Configurable Timer
+                DCD     RIT_OR_WWDT_IRQHandler         ; 27 Repetitive Interrupt Timer or WWDT
+                DCD     TIMER0_IRQHandler              ; 28 Timer0
+                DCD     GINT1_IRQHandler               ; 29 GPIO global interrupt 1
+                DCD     PIN_INT4_IRQHandler               ; 30 GPIO pin interrupt 4
+                DCD     TIMER3_IRQHandler              ; 31 Timer3
+                DCD     MCPWM_IRQHandler               ; 32 Motor control PWM
+                DCD     ADC0_IRQHandler                ; 33 ADC0
+                DCD     I2C0_OR_I2C1_IRQHandler        ; 34 I2C or I2C1
+                DCD     SGPIO_IRQHandler               ; 35 Serial GPIO
+                DCD     SPI_OR_DAC_IRQHandler          ; 36 SPI or DAC
+                DCD     ADC1_IRQHandler                ; 37 ADC1
+                DCD     SSP0_OR_SSP1_IRQHandler        ; 38 SSP0 or SSP1
+                DCD     EVENTROUTER_IRQHandler         ; 39 Event router
+                DCD     USART0_IRQHandler              ; 40 USART0
+                DCD     UART1_IRQHandler               ; 41 UART1/Modem
+                DCD     USART2_OR_C_CAN1_IRQHandler    ; 42 USART2 or C CAN1
+                DCD     USART3_IRQHandler              ; 43 USART3
+                DCD     I2S0_OR_I2S1_OR_QEI_IRQHandler ; 44 I2S0 or I2S1 or QEI
+                DCD     C_CAN0_IRQHandler              ; 45 C CAN0
+                DCD     0                                 ; 46 Reserved
+                DCD     0                                 ; 47 Reserved
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler\
+                PROC
+                EXPORT  Reset_Handler                    [WEAK]
+                IMPORT  __main
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler  PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+SVC_Handler  PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   RTC_IRQHandler                  [WEAK]
+                EXPORT   M4CORE_IRQHandler               [WEAK]
+                EXPORT   DMA_IRQHandler                  [WEAK]
+                EXPORT   FLASHEEPROMAT_IRQHandler        [WEAK]
+                EXPORT   ETH_IRQHandler                  [WEAK]
+                EXPORT   SDIO_IRQHandler                 [WEAK]
+                EXPORT   LCD_IRQHandler                  [WEAK]
+                EXPORT   USB0_IRQHandler                 [WEAK]
+                EXPORT   USB1_IRQHandler                 [WEAK]
+                EXPORT   SCT_IRQHandler                  [WEAK]
+                EXPORT   RIT_OR_WWDT_IRQHandler          [WEAK]
+                EXPORT   TIMER0_IRQHandler               [WEAK]
+                EXPORT   GINT1_IRQHandler                [WEAK]
+                EXPORT   PIN_INT4_IRQHandler                [WEAK]
+                EXPORT   TIMER3_IRQHandler               [WEAK]
+                EXPORT   MCPWM_IRQHandler                [WEAK]
+                EXPORT   ADC0_IRQHandler                 [WEAK]
+                EXPORT   I2C0_OR_I2C1_IRQHandler         [WEAK]
+                EXPORT   SGPIO_IRQHandler                [WEAK]
+                EXPORT   SPI_OR_DAC_IRQHandler           [WEAK]
+                EXPORT   ADC1_IRQHandler                 [WEAK]
+                EXPORT   SSP0_OR_SSP1_IRQHandler         [WEAK]
+                EXPORT   EVENTROUTER_IRQHandler          [WEAK]
+                EXPORT   USART0_IRQHandler               [WEAK]
+                EXPORT   UART1_IRQHandler                [WEAK]
+                EXPORT   USART2_OR_C_CAN1_IRQHandler     [WEAK]
+                EXPORT   USART3_IRQHandler               [WEAK]
+                EXPORT   I2S0_OR_I2S1_OR_QEI_IRQHandler  [WEAK]
+                EXPORT   C_CAN0_IRQHandler               [WEAK]
+
+
+RTC_IRQHandler
+M4CORE_IRQHandler
+DMA_IRQHandler
+FLASHEEPROMAT_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_OR_WWDT_IRQHandler
+TIMER0_IRQHandler
+GINT1_IRQHandler
+PIN_INT4_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_OR_I2C1_IRQHandler
+SGPIO_IRQHandler
+SPI_OR_DAC_IRQHandler
+ADC1_IRQHandler
+SSP0_OR_SSP1_IRQHandler
+EVENTROUTER_IRQHandler
+USART0_IRQHandler
+UART1_IRQHandler
+USART2_OR_C_CAN1_IRQHandler
+USART3_IRQHandler
+I2S0_OR_I2S1_OR_QEI_IRQHandler
+C_CAN0_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                AREA    |.text|,CODE, READONLY
+getPC           PROC
+                EXPORT  getPC
+
+                MOV     R0,LR
+                BX      LR
+
+                ENDP
+
+                END
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
new file mode 100644
index 0000000000..5dd22339f8
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
@@ -0,0 +1,502 @@
+//*****************************************************************************
+// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 140113
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013-2014
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
+#if defined (__USE_LPCOPEN)
+void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
+#endif
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
+#if defined (__USE_LPCOPEN)
+void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+#endif
+void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM4
+    &_vStackTop,                    // The initial stack pointer
+    ResetISR,                       // The reset handler
+    NMI_Handler,                    // The NMI handler
+    HardFault_Handler,              // The hard fault handler
+    MemManage_Handler,              // The MPU fault handler
+    BusFault_Handler,               // The bus fault handler
+    UsageFault_Handler,             // The usage fault handler
+    0,                              // Reserved
+    0,                              // Reserved
+    0,                              // Reserved
+    0,                              // Reserved
+    SVC_Handler,                    // SVCall handler
+    DebugMon_Handler,               // Debug monitor handler
+    0,                              // Reserved
+    PendSV_Handler,                 // The PendSV handler
+    SysTick_Handler,                // The SysTick handler
+
+    // Chip Level - LPC43 (M4)
+    DAC_IRQHandler,           // 16
+#if defined (__USE_LPCOPEN)
+    M0APP_IRQHandler,        // 17 CortexM4/M0 (LPC43XX ONLY)
+#else
+    M0CORE_IRQHandler,        // 17
+#endif
+    DMA_IRQHandler,           // 18
+    0,           // 19
+    FLASH_EEPROM_IRQHandler,   // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
+    ETH_IRQHandler,           // 21
+    SDIO_IRQHandler,          // 22
+    LCD_IRQHandler,           // 23
+    USB0_IRQHandler,          // 24
+    USB1_IRQHandler,          // 25
+    SCT_IRQHandler,           // 26
+    RIT_IRQHandler,           // 27
+    TIMER0_IRQHandler,        // 28
+    TIMER1_IRQHandler,        // 29
+    TIMER2_IRQHandler,        // 30
+    TIMER3_IRQHandler,        // 31
+    MCPWM_IRQHandler,         // 32
+    ADC0_IRQHandler,          // 33
+    I2C0_IRQHandler,          // 34
+    I2C1_IRQHandler,          // 35
+    SPI_IRQHandler,           // 36
+    ADC1_IRQHandler,          // 37
+    SSP0_IRQHandler,          // 38
+    SSP1_IRQHandler,          // 39
+    UART0_IRQHandler,         // 40
+    UART1_IRQHandler,         // 41
+    UART2_IRQHandler,         // 42
+    UART3_IRQHandler,         // 43
+    I2S0_IRQHandler,          // 44
+    I2S1_IRQHandler,          // 45
+    SPIFI_IRQHandler,         // 46
+    SGPIO_IRQHandler,         // 47
+    GPIO0_IRQHandler,         // 48
+    GPIO1_IRQHandler,         // 49
+    GPIO2_IRQHandler,         // 50
+    GPIO3_IRQHandler,         // 51
+    GPIO4_IRQHandler,         // 52
+    GPIO5_IRQHandler,         // 53
+    GPIO6_IRQHandler,         // 54
+    GPIO7_IRQHandler,         // 55
+    GINT0_IRQHandler,         // 56
+    GINT1_IRQHandler,         // 57
+    EVRT_IRQHandler,          // 58
+    CAN1_IRQHandler,          // 59
+    0,                        // 60
+#if defined (__USE_LPCOPEN)
+    ADCHS_IRQHandler,         // 61 ADCHS combined interrupt
+#else
+    VADC_IRQHandler,          // 61
+#endif
+    ATIMER_IRQHandler,        // 62
+    RTC_IRQHandler,           // 63
+    0,                        // 64
+    WDT_IRQHandler,           // 65
+    M0SUB_IRQHandler,         // 66
+    CAN0_IRQHandler,          // 67
+    QEI_IRQHandler,           // 68
+};
+
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+        __attribute__((section(".after_vectors"
+)))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//
+//*****************************************************************************
+void ResetISR(void) {
+
+// *************************************************************
+// The following conditional block of code manually resets as
+// much of the peripheral set of the LPC43 as possible. This is
+// done because the LPC43 does not provide a means of triggering
+// a full system reset under debugger control, which can cause
+// problems in certain circumstances when debugging.
+//
+// You can prevent this code block being included if you require
+// (for example when creating a final executable which you will
+// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
+//
+#ifndef DONT_RESET_ON_RESTART
+
+    // Disable interrupts
+    __asm volatile ("cpsid i");
+    // equivalent to CMSIS '__disable_irq()' function
+
+    unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
+    // LPC_RGU->RESET_CTRL0 @ 0x40053100
+    // LPC_RGU->RESET_CTRL1 @ 0x40053104
+    // Note that we do not use the CMSIS register access mechanism,
+    // as there is no guarantee that the project has been configured
+    // to use CMSIS.
+
+    // Write to LPC_RGU->RESET_CTRL0
+    *(RESET_CONTROL + 0) = 0x10DF1000;
+    // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
+    // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
+
+    // Write to LPC_RGU->RESET_CTRL1
+    *(RESET_CONTROL + 1) = 0x01DFF7FF;
+    // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
+    // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
+    // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
+    // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
+
+    // Clear all pending interrupts in the NVIC
+    volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
+    unsigned int irqpendloop;
+    for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
+        *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
+    }
+
+    // Reenable interrupts
+    __asm volatile ("cpsie i");
+    // equivalent to CMSIS '__enable_irq()' function
+
+#endif  // ifndef DONT_RESET_ON_RESTART
+// *************************************************************
+
+#if defined (__USE_LPCOPEN)
+    SystemInit();
+#endif
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_LPCOPEN)
+// LPCOpen init code deals with FP and VTOR initialisation
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    /*
+     * Code to enable the Cortex-M4 FPU only included
+     * if appropriate build options have been selected.
+     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+     */
+    // CPACR is located at address 0xE000ED88
+    asm("LDR.W R0, =0xE000ED88");
+    // Read CPACR
+    asm("LDR R1, [R0]");
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    asm(" ORR R1, R1, #(0xF << 20)");
+    // Write back the modified value to the CPACR
+    asm("STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+    // ******************************
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+
+    // Note that we do not use the CMSIS register access mechanism,
+    // as there is no guarantee that the project has been configured
+    // to use CMSIS.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
+        // CMSIS : SCB->VTOR = <address of vector table>
+        *pSCB_VTOR = (unsigned int) g_pfnVectors;
+    }
+#endif
+
+#if defined (__USE_CMSIS)
+    SystemInit();
+#endif
+
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void) {
+    while (1) {
+    }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void) {
+    while (1) {
+    }
+}
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
new file mode 100644
index 0000000000..5f6233ad0e
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
@@ -0,0 +1,463 @@
+//*****************************************************************************
+// LPC43xx (Cortex M0 SUB) Startup code for use with LPCXpresso IDE
+//
+// Version : 131115
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+  extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+void SystemInit(void);
+#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+     void ResetISR(void);
+#if defined (__USE_LPCOPEN)
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+#else
+WEAK void M0S_NMI_Handler(void);
+WEAK void M0S_HardFault_Handler (void);
+WEAK void M0S_SVC_Handler(void);
+WEAK void M0S_PendSV_Handler(void);
+WEAK void M0S_SysTick_Handler(void);
+WEAK void M0S_IntDefaultHandler(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+#if defined (__USE_LPCOPEN)
+void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_INPUT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_MATCH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_SHIFT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_POS_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S0_I2S1_QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI_ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void M0S_DAC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_M4CORE_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_DMA_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_INPUT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_MATCH_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_SHIFT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_POS_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USB0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USB1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SCT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_RITIMER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_GINT1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_TIMER1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_TIMER2_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_PIN_INT5_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_ADC0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_MCPWM_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_I2C0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_I2C1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SPI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_ADC1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SSP0_OR_SSP1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_EVENTROUTER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USART0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_UART1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USART2_OR_C_CAN1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USART3_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_C_CAN0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SPIFI_OR_VADC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_M0APP_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+#endif
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+
+#if defined (__USE_LPCOPEN)
+    // Core Level - CM0
+    &_vStackTop,                        // The initial stack pointer
+    ResetISR,                           // 1 The reset handler
+    NMI_Handler,                    // The NMI handler
+    HardFault_Handler,              // The hard fault handler
+    0,                                  // 4 Reserved
+    0,                                  // 5 Reserved
+    0,                                  // 6 Reserved
+    0,                                  // 7 Reserved
+    0,                                  // 8 Reserved
+    0,                                  // 9 Reserved
+    0,                                  // 10 Reserved
+    SVC_Handler,                    // SVCall handler
+    0,                              // Reserved
+    0,                              // Reserved
+    PendSV_Handler,                 // The PendSV handler
+    SysTick_Handler,                // The SysTick handler
+
+    // Chip Level - 43xx M0SUB core
+    DAC_IRQHandler,                 // 16
+    M4_IRQHandler,             // 17 Interrupt from M4 Core
+    DMA_IRQHandler,                 // 18 General Purpose DMA
+    0,                              // 19 Reserved
+    SGPIO_INPUT_IRQHandler,         // 20
+    SGPIO_MATCH_IRQHandler,         // 21
+    SGPIO_SHIFT_IRQHandler,         // 22
+    SGPIO_POS_IRQHandler,           // 23
+    USB0_IRQHandler,                // 24 USB0
+    USB1_IRQHandler,                // 25 USB1
+    SCT_IRQHandler ,                // 26 State Configurable Timer
+    RIT_IRQHandler,                 // 27 Repetitive Interrupt Timer
+    GINT1_IRQHandler,               // 28 GINT1
+    TIMER1_IRQHandler,              // 29 Timer1
+    TIMER2_IRQHandler,              // 30 Timer2
+    GPIO5_IRQHandler,               // 31
+    MCPWM_IRQHandler,               // 32 Motor Control PWM
+    ADC0_IRQHandler,                // 33 ADC0
+    I2C0_IRQHandler,                // 34
+    I2C1_IRQHandler,                // 35
+    SPI_IRQHandler,                 // 36
+    ADC1_IRQHandler,                // 37
+    SSP0_SSP1_IRQHandler,           // 38
+    EVRT_IRQHandler,                // 39 Event Router
+    UART0_IRQHandler,               // 41 USART0
+    UART1_IRQHandler,               // 41 UART1
+    UART2_CAN1_IRQHandler,          // 42 USART2 or C CAN1
+    UART3_IRQHandler,               // 43 USART3
+    I2S0_I2S1_QEI_IRQHandler,       // 35 I2C0 or I2C1 or I2S1 or QEI
+    CAN0_IRQHandler,                // 45 C CAN0
+    SPIFI_ADCHS_IRQHandler,         // 46
+    M0APP_IRQHandler,               // 47 Interrupt from M0APP
+  };
+#else
+    // Core Level - CM0
+    &_vStackTop,                        // The initial stack pointer
+    ResetISR,                           // 1 The reset handler
+    M0S_NMI_Handler,                    // 2 The NMI handler
+    M0S_HardFault_Handler,              // 3 The hard fault handler
+    0,                                  // 4 Reserved
+    0,                                  // 5 Reserved
+    0,                                  // 6 Reserved
+    0,                                  // 7 Reserved
+    0,                                  // 8 Reserved
+    0,                                  // 9 Reserved
+    0,                                  // 10 Reserved
+    M0S_SVC_Handler,                    // 11 SVCall handler
+    M0S_DebugMon_Handler,               // 12 Debug monitor handler
+    0,                                  // 13 Reserved
+    M0S_PendSV_Handler,                 // 14 The PendSV handler
+    M0S_SysTick_Handler,                // 15 The SysTick handler
+
+    // Chip Level - LPC43 (CM0 SUB)
+    M0S_DAC_IRQHandler,                 // 16
+    M0S_M4CORE_IRQHandler,              // 17 Interrupt from M4 Core
+    M0S_DMA_IRQHandler,                 // 18 General Purpose DMA
+    0,                                  // 19 Reserved
+    M0S_SGPIO_INPUT_IRQHandler,         // 20
+    M0S_SGPIO_MATCH_IRQHandler,         // 21
+    M0S_SGPIO_SHIFT_IRQHandler,         // 22
+    M0S_SGPIO_POS_IRQHandler,           // 23
+    M0S_USB0_IRQHandler,                // 24 USB0
+    M0S_USB1_IRQHandler,                // 25 USB1
+    M0S_SCT_IRQHandler ,                // 26 State Configurable Timer
+    M0S_RITIMER_IRQHandler,             // 27 Repetitive Interrupt Timer
+    M0S_GINT1_IRQHandler,               // 28 GINT1
+    M0S_TIMER1_IRQHandler,              // 29 Timer1
+    M0S_TIMER2_IRQHandler,              // 30 Timer2
+    M0S_PIN_INT5_IRQHandler,            // 31
+    M0S_MCPWM_IRQHandler,               // 32 Motor Control PWM
+    M0S_ADC0_IRQHandler,                // 33 ADC0
+    M0S_I2C0_IRQHandler,                // 34
+    M0S_I2C1_IRQHandler,                // 35
+    M0S_SPI_IRQHandler,                 // 36
+    M0S_ADC1_IRQHandler,                // 37
+    M0S_SSP0_OR_SSP1_IRQHandler,        // 38
+    M0S_EVENTROUTER_IRQHandler,         // 39 Event Router
+    M0S_USART0_IRQHandler,              // 41 USART0
+    M0S_UART1_IRQHandler,               // 41 UART1
+    M0S_USART2_OR_C_CAN1_IRQHandler,    // 42 USART2 or C CAN1
+    M0S_USART3_IRQHandler,              // 43 USART3
+    M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler,
+                                        // 35 I2C0 or I2C1 or I2S1 or QEI
+    M0S_C_CAN0_IRQHandler,              // 45 C CAN0
+    M0S_SPIFI_OR_VADC_IRQHandler,       // 46
+    M0S_M0APP_IRQHandler,               // 47 Interrupt from M0APP
+  };
+#endif
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+  unsigned int *pulDest = (unsigned int*) start;
+  unsigned int *pulSrc = (unsigned int*) romstart;
+  unsigned int loop;
+  for (loop = 0; loop < len; loop = loop + 4)
+    *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+  unsigned int *pulDest = (unsigned int*) start;
+  unsigned int loop;
+  for (loop = 0; loop < len; loop = loop + 4)
+    *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//
+//*****************************************************************************
+void
+ResetISR(void) {
+
+  // ******************************
+  // Modify CREG->M0SUBMEMMAP so that M0 looks in correct place
+  // for its vector table when an exception is triggered.
+  // Note that we do not use the CMSIS register access mechanism,
+  // as there is no guarantee that the project has been configured
+  // to use CMSIS.
+  unsigned int *pCREG_M0SUBMEMMAP = (unsigned int *) 0x40043308;
+  // CMSIS : CREG->M0SUBMEMMAP = <address of vector table>
+  *pCREG_M0SUBMEMMAP = (unsigned int)g_pfnVectors;
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+  unsigned int LoadAddr, ExeAddr, SectionLen;
+  unsigned int *SectionTableAddr;
+
+  // Load base address of Global Section Table
+  SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+  while (SectionTableAddr < &__data_section_table_end) {
+    LoadAddr = *SectionTableAddr++;
+    ExeAddr = *SectionTableAddr++;
+    SectionLen = *SectionTableAddr++;
+    data_init(LoadAddr, ExeAddr, SectionLen);
+  }
+  // At this point, SectionTableAddr = &__bss_section_table;
+  // Zero fill the bss segment
+  while (SectionTableAddr < &__bss_section_table_end) {
+    ExeAddr = *SectionTableAddr++;
+    SectionLen = *SectionTableAddr++;
+    bss_init(ExeAddr, SectionLen);
+  }
+
+// **********************************************************
+// No need to call SystemInit() here, as master CM4 cpu will
+// have done the main system set up before enabling CM0.
+// **********************************************************
+
+#if defined (__cplusplus)
+  //
+  // Call C++ library initialisation
+  //
+  __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+  // Call the Redlib library, which in turn calls main()
+  __main() ;
+#else
+  main();
+#endif
+
+  //
+  // main() shouldn't return, but if it does, we'll just enter an infinite loop
+  //
+  while (1) {
+    ;
+  }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void NMI_Handler(void)
+#else
+void M0S_NMI_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void HardFault_Handler(void)
+#else
+void M0S_HardFault_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void SVC_Handler(void)
+#else
+void M0S_SVC_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void PendSV_Handler(void)
+#else
+void M0S_PendSV_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void SysTick_Handler(void)
+#else
+void M0S_SysTick_Handler(void)
+#endif
+{   while(1) { }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void IntDefaultHandler(void)
+#else
+void M0S_IntDefaultHandler(void)
+#endif
+{   while(1) { }
+}
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
new file mode 100644
index 0000000000..211a67d700
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
@@ -0,0 +1,431 @@
+;/*****************************************************************************
+; * @file:    startup_LPC18xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; *           for the NXP LPC18xx Device Series
+; * @version: V1.00
+; * @date:    24. May. 2011
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+Sign_Value		EQU		0x5A5A5A5A
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     Sign_Value
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD		DAC_IRQHandler	 			; 16 D/A Converter
+	DCD		0					; 17 Event Router
+        DCD		DMA_IRQHandler				; 18 General Purpose DMA
+        DCD		0				        ; 19 Reserved
+        DCD		0				        ; 20 Reserved
+        DCD		ETH_IRQHandler				; 21 Ethernet
+        DCD		SDIO_IRQHandler				; 22 SD/MMC
+        DCD		LCD_IRQHandler				; 23 LCD
+        DCD		USB0_IRQHandler				; 24 USB0
+        DCD		USB1_IRQHandler				; 25 USB1
+        DCD		SCT_IRQHandler				; 26 State Configurable Timer
+        DCD		RIT_IRQHandler				; 27 Repetitive Interrupt Timer
+        DCD		TIMER0_IRQHandler			; 28 Timer0
+        DCD		TIMER1_IRQHandler			; 29 Timer1
+        DCD		TIMER2_IRQHandler			; 30 Timer2
+        DCD		TIMER3_IRQHandler			; 31 Timer3
+        DCD		MCPWM_IRQHandler			; 32 Motor Control PWM
+        DCD		ADC0_IRQHandler				; 33 A/D Converter 0
+        DCD		I2C0_IRQHandler				; 34 I2C0
+        DCD		I2C1_IRQHandler				; 35 I2C1
+        DCD		0					; 36 Reserved
+        DCD		ADC1_IRQHandler				; 37 A/D Converter 1
+        DCD		SSP0_IRQHandler				; 38 SSP0
+        DCD		SSP1_IRQHandler				; 39 SSP1
+        DCD		UART0_IRQHandler			; 40 UART0
+        DCD		UART1_IRQHandler			; 41 UART1
+        DCD		UART2_IRQHandler			; 42 UART2
+        DCD		UART3_IRQHandler			; 43 UART3
+	DCD		I2S0_IRQHandler				; 44 I2S0
+	DCD		I2S1_IRQHandler				; 45 I2S1
+	DCD		SPIFI_IRQHandler			; 46 SPI Flash Interface
+	DCD		SGPIO_IRQHandler			; 47 SGPIO
+	DCD		GPIO0_IRQHandler			; 48 GPIO0
+	DCD		GPIO1_IRQHandler			; 49 GPIO1
+	DCD		GPIO2_IRQHandler			; 50 GPIO2
+	DCD		GPIO3_IRQHandler			; 51 GPIO3
+	DCD		GPIO4_IRQHandler			; 52 GPIO4
+	DCD		GPIO5_IRQHandler			; 53 GPIO5
+	DCD		GPIO6_IRQHandler			; 54 GPIO6
+	DCD		GPIO7_IRQHandler			; 55 GPIO7
+	DCD		GINT0_IRQHandler			; 56 GINT0
+	DCD		GINT1_IRQHandler			; 57 GINT1
+	DCD		EVRT_IRQHandler				; 58 Event Router
+	DCD		CAN1_IRQHandler				; 59 C_CAN1
+	DCD		0							; 60 Reserved
+	DCD		0       				; 61 VADC
+	DCD		ATIMER_IRQHandler			; 62 ATIMER
+	DCD		RTC_IRQHandler				; 63 RTC
+	DCD		0							; 64 Reserved
+	DCD		WDT_IRQHandler				; 65 WDT
+	DCD		0       				; 66 M0s
+	DCD		CAN0_IRQHandler				; 67 C_CAN0
+	DCD 	QEI_IRQHandler				; 68 QEI
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+
+        PUBWEAK EVRT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EVRT_IRQHandler
+        B EVRT_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ETH_IRQHandler
+        B ETH_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+        B SDIO_IRQHandler
+
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+
+        PUBWEAK USB0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB0_IRQHandler
+        B USB0_IRQHandler
+
+        PUBWEAK USB1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB1_IRQHandler
+        B USB1_IRQHandler
+
+        PUBWEAK SCT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SCT_IRQHandler
+        B SCT_IRQHandler
+
+        PUBWEAK RIT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RIT_IRQHandler
+        B RIT_IRQHandler
+
+        PUBWEAK TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER0_IRQHandler
+        B TIMER0_IRQHandler
+
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+
+        PUBWEAK TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER2_IRQHandler
+        B TIMER2_IRQHandler
+
+        PUBWEAK TIMER3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER3_IRQHandler
+        B TIMER3_IRQHandler
+
+        PUBWEAK MCPWM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+MCPWM_IRQHandler
+        B MCPWM_IRQHandler
+
+        PUBWEAK ADC0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC0_IRQHandler
+        B ADC0_IRQHandler
+
+        PUBWEAK I2C0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C0_IRQHandler
+        B I2C0_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK SSP0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP0_IRQHandler
+        B SSP0_IRQHandler
+
+        PUBWEAK SSP1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP1_IRQHandler
+        B SSP1_IRQHandler
+
+        PUBWEAK UART0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+        B UART0_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK I2S0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2S0_IRQHandler
+        B I2S0_IRQHandler
+
+        PUBWEAK I2S1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2S1_IRQHandler
+        B I2S1_IRQHandler
+        
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK SPIFI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPIFI_IRQHandler
+        B SPIFI_IRQHandler
+
+        PUBWEAK SGPIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SGPIO_IRQHandler
+        B SGPIO_IRQHandler
+
+        PUBWEAK GPIO0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO0_IRQHandler
+        B GPIO0_IRQHandler
+
+        PUBWEAK GPIO1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO1_IRQHandler
+        B GPIO1_IRQHandler
+        
+        PUBWEAK GPIO2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO2_IRQHandler
+        B GPIO2_IRQHandler
+        
+        PUBWEAK GPIO3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO3_IRQHandler
+        B GPIO3_IRQHandler
+        
+        PUBWEAK GPIO4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO4_IRQHandler
+        B GPIO4_IRQHandler
+        
+        PUBWEAK GPIO5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO5_IRQHandler
+        B GPIO5_IRQHandler
+        
+        PUBWEAK GPIO6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO6_IRQHandler
+        B GPIO6_IRQHandler
+        
+        PUBWEAK GPIO7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO7_IRQHandler
+        B GPIO7_IRQHandler
+        
+        PUBWEAK GINT0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GINT0_IRQHandler
+        B GINT0_IRQHandler
+        
+        PUBWEAK GINT1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GINT1_IRQHandler
+        B GINT1_IRQHandler
+        
+        PUBWEAK CAN1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_IRQHandler
+        B CAN1_IRQHandler
+        
+        PUBWEAK ATIMER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ATIMER_IRQHandler
+        B ATIMER_IRQHandler
+        
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+        
+        PUBWEAK CAN0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN0_IRQHandler
+        B CAN0_IRQHandler
+        
+        PUBWEAK QEI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+QEI_IRQHandler
+        B QEI_IRQHandler
+        
+        PUBWEAK getPC
+        SECTION .text:CODE:REORDER(2)
+getPC
+      MOV   R0,LR
+      BX    LR        
+        END
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
new file mode 100644
index 0000000000..1954b91b7b
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
@@ -0,0 +1,242 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start 
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+				
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+		DCD		DAC_IRQHandler
+		DCD		M4_IRQHandler
+		DCD		DMA_IRQHandler
+		DCD		0
+		DCD		SGPIO_INPUT_IRQHandler
+		DCD		SGPIO_MATCH_IRQHandler
+		DCD		SGPIO_SHIFT_IRQHandler
+		DCD		SGPIO_POS_IRQHandler
+		DCD		USB0_IRQHandler
+		DCD		USB1_IRQHandler
+		DCD		SCT_IRQHandler
+		DCD		RIT_IRQHandler
+		DCD		GINT1_IRQHandler
+		DCD		TIMER1_IRQHandler
+		DCD		TIMER2_IRQHandler
+		DCD		GPIO5_IRQHandler
+		DCD		MCPWM_IRQHandler
+		DCD		ADC0_IRQHandler
+		DCD		I2C0_IRQHandler
+		DCD		I2C1_IRQHandler
+		DCD		SPI_IRQHandler
+		DCD		ADC1_IRQHandler
+		DCD		SSP0_SSP1_IRQHandler
+		DCD		EVRT_IRQHandler
+		DCD		UART0_IRQHandler
+		DCD		UART1_IRQHandler
+		DCD		UART2_CAN1_IRQHandler
+		DCD		UART3_IRQHandler
+		DCD		I2S0_I2S1_QEI_IRQHandler
+		DCD		CAN0_IRQHandler
+		DCD		SPIFI_ADCHS_IRQHandler
+		DCD		M0APP_IRQHandler
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+		THUMB
+
+		PUBWEAK Reset_Handler
+		SECTION .text:CODE:REORDER(2)
+Reset_Handler
+		LDR     R0, =SystemInit
+		BLX     R0
+		LDR     R0, =__iar_program_start
+		BX      R0
+  
+		PUBWEAK NMI_Handler
+		PUBWEAK HardFault_Handler
+		PUBWEAK MemManage_Handler
+		PUBWEAK BusFault_Handler
+		PUBWEAK UsageFault_Handler
+		PUBWEAK SVC_Handler
+		PUBWEAK DebugMon_Handler
+		PUBWEAK PendSV_Handler
+		PUBWEAK SysTick_Handler
+
+		PUBWEAK DAC_IRQHandler
+		PUBWEAK M4_IRQHandler
+		PUBWEAK DMA_IRQHandler
+		PUBWEAK UnHandled_Vector
+		PUBWEAK SGPIO_INPUT_IRQHandler
+		PUBWEAK SGPIO_MATCH_IRQHandler
+		PUBWEAK SGPIO_SHIFT_IRQHandler
+		PUBWEAK SGPIO_POS_IRQHandler
+		PUBWEAK USB0_IRQHandler
+		PUBWEAK USB1_IRQHandler
+		PUBWEAK SCT_IRQHandler
+		PUBWEAK RIT_IRQHandler
+		PUBWEAK GINT1_IRQHandler
+		PUBWEAK TIMER1_IRQHandler
+		PUBWEAK TIMER2_IRQHandler
+		PUBWEAK GPIO5_IRQHandler
+		PUBWEAK MCPWM_IRQHandler
+		PUBWEAK ADC0_IRQHandler
+		PUBWEAK I2C0_IRQHandler
+		PUBWEAK I2C1_IRQHandler
+		PUBWEAK SPI_IRQHandler
+		PUBWEAK ADC1_IRQHandler
+		PUBWEAK SSP0_SSP1_IRQHandler
+		PUBWEAK EVRT_IRQHandler
+		PUBWEAK UART0_IRQHandler
+		PUBWEAK UART1_IRQHandler
+		PUBWEAK UART2_CAN1_IRQHandler
+		PUBWEAK UART3_IRQHandler
+		PUBWEAK I2S0_I2S1_QEI_IRQHandler
+		PUBWEAK CAN0_IRQHandler
+		PUBWEAK SPIFI_ADCHS_IRQHandler
+		PUBWEAK M0APP_IRQHandler
+
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B .
+SVC_Handler
+        B .
+DebugMon_Handler
+        B .
+PendSV_Handler
+        B .
+SysTick_Handler
+        B .
+HardFault_Handler
+        B .
+MemManage_Handler
+        B .
+BusFault_Handler
+        B .
+UsageFault_Handler
+DAC_IRQHandler
+M4_IRQHandler
+DMA_IRQHandler
+UnHandled_Vector
+SGPIO_INPUT_IRQHandler
+SGPIO_MATCH_IRQHandler
+SGPIO_SHIFT_IRQHandler
+SGPIO_POS_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+GINT1_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+GPIO5_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_SSP1_IRQHandler
+EVRT_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_CAN1_IRQHandler
+UART3_IRQHandler
+I2S0_I2S1_QEI_IRQHandler
+CAN0_IRQHandler
+SPIFI_ADCHS_IRQHandler
+M0APP_IRQHandler
+Default_IRQHandler
+        B .
+
+/* CRP Section - not needed for flashless devices */
+
+;;;        SECTION .crp:CODE:ROOT(2)
+;;;        DATA
+/* Code Read Protection
+NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+                   - Copy RAM to flash command can not write to Sector 0.
+                   - Erase command can erase Sector 0 only when all sectors
+                     are selected for erase.
+                   - Compare command is disabled.
+                   - Read Memory command is disabled.
+CRP2    0x87654321 - Read Memory is disabled.
+                   - Write to RAM is disabled.
+                   - "Go" command is disabled.
+                   - Copy RAM to flash is disabled.
+                   - Compare is disabled.
+CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+                     by pulling PIO0_1 LOW is disabled if a valid user code is
+                     present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+;;;	    DCD	0xFFFFFFFF
+;;;
+
+        END
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
new file mode 100644
index 0000000000..3bd76f5de6
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
@@ -0,0 +1,892 @@
+/*----------------------------------------------------------------------------
+ * Name:    system_LPC43xx.c
+ * Purpose: LCP43xx clock initialisation
+ * Version: V2.51
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2005-2012 Keil Software. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "LPC43xx.h"
+
+/*----------------------------------------------------------------------------
+  This file configures the clocks as follows:
+ -----------------------------------------------------------------------------
+ Clock Unit  |  Output clock  |  Source clock  |          Note
+ -----------------------------------------------------------------------------
+   PLL0USB   |    480 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    PLL1     |    180 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    CPU      |    180 MHz     |      PLL1      | CPU Clock ==  BASE_M4_CLK
+ -----------------------------------------------------------------------------
+   IDIV A    |     60 MHz     |      PLL1      | To the USB1 peripheral
+ -----------------------------------------------------------------------------
+   IDIV B    |     25 MHz     |   ENET_TX_CLK  | ENET_TX_CLK @ 50MHz
+ -----------------------------------------------------------------------------
+   IDIV C    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV D    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV E    |    5.3 MHz     |      PLL1      | To the LCD controller
+ -----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock source selection definitions (do not change)
+ *----------------------------------------------------------------------------*/
+#define CLK_SRC_32KHZ       0x00
+#define CLK_SRC_IRC         0x01
+#define CLK_SRC_ENET_RX     0x02
+#define CLK_SRC_ENET_TX     0x03
+#define CLK_SRC_GP_CLKIN    0x04
+#define CLK_SRC_XTAL        0x06
+#define CLK_SRC_PLL0U       0x07
+#define CLK_SRC_PLL0A       0x08
+#define CLK_SRC_PLL1        0x09
+#define CLK_SRC_IDIVA       0x0C
+#define CLK_SRC_IDIVB       0x0D
+#define CLK_SRC_IDIVC       0x0E
+#define CLK_SRC_IDIVD       0x0F
+#define CLK_SRC_IDIVE       0x10
+
+
+/*----------------------------------------------------------------------------
+  Define external input frequency values
+ *----------------------------------------------------------------------------*/
+#define CLK_32KHZ            32768UL    /* 32 kHz oscillator frequency        */
+#define CLK_IRC           12000000UL    /* Internal oscillator frequency      */
+#define CLK_ENET_RX       50000000UL    /* Ethernet Rx frequency              */
+#define CLK_ENET_TX       50000000UL    /* Ethernet Tx frequency              */
+#define CLK_GP_CLKIN      12000000UL    /* General purpose clock input freq.  */
+#define CLK_XTAL          12000000UL    /* Crystal oscilator frequency        */
+
+
+/*----------------------------------------------------------------------------
+  Define clock sources
+ *----------------------------------------------------------------------------*/
+#define PLL1_CLK_SEL      CLK_SRC_XTAL    /* PLL1 input clock: XTAL           */
+#define PLL0USB_CLK_SEL   CLK_SRC_XTAL    /* PLL0USB input clock: XTAL        */
+#define IDIVA_CLK_SEL     CLK_SRC_PLL1    /* IDIVA input clock: PLL1          */
+#define IDIVB_CLK_SEL     CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX       */
+#define IDIVC_CLK_SEL     CLK_SRC_IRC     /* IDIVC input clock: IRC           */
+#define IDIVD_CLK_SEL     CLK_SRC_IRC     /* IDIVD input clock: IRC           */
+#define IDIVE_CLK_SEL     CLK_SRC_PLL1    /* IDIVD input clock: PLL1          */
+
+
+/*----------------------------------------------------------------------------
+  Configure integer divider values
+ *----------------------------------------------------------------------------*/
+#define IDIVA_IDIV        2             /* Divide input clock by 3            */
+#define IDIVB_IDIV        1             /* Divide input clock by 2            */
+#define IDIVC_IDIV        0             /* Divide input clock by 1            */
+#define IDIVD_IDIV        0             /* Divide input clock by 1            */
+#define IDIVE_IDIV       33             /* Divide input clock by 34           */
+
+
+/*----------------------------------------------------------------------------
+  Define CPU clock input
+ *----------------------------------------------------------------------------*/
+#define CPU_CLK_SEL       CLK_SRC_PLL1  /* Default CPU clock source is PLL1   */
+
+
+/*----------------------------------------------------------------------------
+  Configure external memory controller options
+ *----------------------------------------------------------------------------*/
+#define USE_EXT_STAT_MEM_CS0 1          /* Use ext. static  memory with CS0   */
+#define USE_EXT_DYN_MEM_CS0  1          /* Use ext. dynamic memory with CS0   */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL1                                                                 
+ *----------------------------------------------------------------------------
+ * Integer mode:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 1 (Feedback divider runs from PLL output)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Non-integer:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 0 (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M / (2 * P)
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Direct mode:
+ *    - PLL1_DIRECT = 1         (Post divider disabled)
+ *    - PLL1_FBSEL  = dont care (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT
+ *
+ *----------------------------------------------------------------------------
+ * PLL1 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
+ * |   FCCO    |  156MHz   |  320MHz   |                                      |
+ * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkin |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
+ * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
+ * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |
+ * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
+ * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   |
+ * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
+ * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
+ * | 204MHz | 204MHz |  1  |  17 |  x  |   1    |   0   |    0   |
+ *----------------------------------------------------------------------------
+ * Relations beetwen PLL dividers and definitions:
+ * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
+ *----------------------------------------------------------------------------*/
+
+/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x              */
+#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
+#define PLL1_MSEL  14           /* Range [0 - 255]: Feedback-divider ratio M  */
+#define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
+
+#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
+#define PLL1_DIRECT 1           /* 0: Use PSEL, 1: Don't use PSEL             */
+#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
+                                /* 1: FCLKOUT is used as PLL feedback         */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL0USB
+ *----------------------------------------------------------------------------
+ *
+ *   Normal operating mode without post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * (M / P)
+ *                        FCCO = FOUT * 2 * P
+ *
+ *   Normal operating mode without post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 1 
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M / N
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * M / (P * N)
+ *                        FCCO = FOUT * 2 * P
+ *----------------------------------------------------------------------------
+ * PLL0 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |   14kHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |   14kHz   |  150MHz   |                                      |
+ * |   FCCO    |  275MHz   |  550MHz   |                                      |
+ * |  FCLKOUT  |  4.3MHz   |  550MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkin |  Fcco  |  N  |  M  |  P  | DIRECTI | DIRECTO | BYPASS |
+ * | 120MHz | 480MHz |  x  |  20 |  2  |    1    |    0    |    0   |
+ * | 480MHz | 480MHz |  1  |  20 |  1  |    1    |    1    |    0   |
+ *----------------------------------------------------------------------------*/
+
+/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1           */
+#define PLL0USB_N       1       /* Range [1 -  256]: Pre-divider              */
+#define PLL0USB_M      20       /* Range [1 - 2^15]: Feedback-divider         */
+#define PLL0USB_P       1       /* Range [1 -   32]: Post-divider             */
+
+#define PLL0USB_DIRECTI 1       /* 0: Use N_DIV, 1: Don't use N_DIV           */
+#define PLL0USB_DIRECTO 1       /* 0: Use P_DIV, 1: Don't use P_DIV           */
+#define PLL0USB_BYPASS  0       /* 0: Use PLL, 1: PLL is bypassed             */
+
+
+/*----------------------------------------------------------------------------
+  End of configuration
+ *----------------------------------------------------------------------------*/
+
+/* PLL0 Setting Check */
+#if (PLL0USB_BYPASS == 0)
+ #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL0USB_CLKIN CLK_XTAL
+ #else
+  #define PLL0USB_CLKIN CLK_IRC
+ #endif
+
+ #if   ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #else                                                    /* Mode 1d          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #endif
+
+ #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
+  #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
+ #endif
+ #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
+  #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
+ #endif
+#endif
+
+/* PLL1 Setting Check */
+#if (PLL1_BYPASS == 0)
+ #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL1_CLKIN CLK_XTAL
+ #else
+  #define PLL1_CLKIN CLK_IRC
+ #endif
+
+ #if   (PLL1_DIRECT == 1)               /* Direct Mode                        */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #elif (PLL1_FBSEL  == 1)               /* Integer Mode                       */
+  #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #else                                  /* Noninteger Mode                    */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
+ #endif
+ #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
+  #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
+ #endif
+ #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
+  #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
+ #endif
+#endif
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CLK_IRC;    /* System Clock Frequency (Core Clock) */
+
+
+/******************************************************************************
+ * SetClock
+ ******************************************************************************/
+void SetClock (void) {
+  uint32_t x, i;
+  uint32_t selp, seli;
+
+  /* Set flash wait states to maximum                                         */
+  LPC_EMC->STATICWAITRD0  = 0x1F;
+
+  /* Switch BASE_M4_CLOCK to IRC                                              */
+  LPC_CGU->BASE_M4_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CLK_SRC_IRC << 24) ;  /* Set clock source           */
+
+  /* Configure input to crystal oscilator                                     */
+  LPC_CGU->XTAL_OSC_CTRL = (0 << 0) |   /* Enable oscillator-pad              */
+                           (0 << 1) |   /* Operation with crystal connected   */
+                           (0 << 2) ;   /* Low-frequency mode                 */
+
+#if (USE_SPIFI)
+/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
+  LPC_CGU->IDIVA_CTRL     = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IRC    << 24) ;  /* Clock source         */
+
+  LPC_CGU->BASE_SPIFI_CLK = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IDIVA  << 24) ;  /* Clock source         */
+#endif
+
+/*----------------------------------------------------------------------------
+  PLL1 Setup
+ *----------------------------------------------------------------------------*/
+  /* Power down PLL                                                           */
+  LPC_CGU->PLL1_CTRL |= 1;
+
+#if ((PLL1_FOUT >= 180000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
+  /* To run at full speed, CPU must first run at an intermediate speed        */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (0            << 1) | /* CCO out sent to post-dividers */
+                       (0            << 6) | /* PLL output used as feedback   */
+                       (1            << 7) | /* Direct on/off                 */
+                       (0            << 8) | /* PSEL                          */
+                       (0            << 11)| /* Autoblock Disabled            */
+                       (2            << 12)| /* NSEL                          */
+                       (39           << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* CPU base clock @ 160 MHz before final clock set                          */
+  LPC_CGU->BASE_M4_CLK     = (0x01 << 11) |  /* Autoblock En                  */
+                             (0x09 << 24) ;  /* Clock source: PLL1            */
+
+  for (i = 1000; i; i--);                    /* Wait about 4000 cycles        */
+#endif
+  /* Configure PLL1                                                           */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (PLL1_DIRECT  << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (1            << 11)| /* Autoblock En                  */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* Set CPU base clock source                                                */
+  LPC_CGU->BASE_M4_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CPU_CLK_SEL << 24) ;  /* Set clock source           */
+
+
+/*----------------------------------------------------------------------------
+  PLL0USB Setup
+ *----------------------------------------------------------------------------*/
+  
+  /* Power down PLL0USB                                                       */
+  LPC_CGU->PLL0USB_CTRL  |= 1;
+
+  /* M divider                                                                */
+  x = 0x00004000;
+  switch (PLL0USB_M) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00018003;
+      break;
+    case 2:  x = 0x00010003;
+      break;
+    default:
+      for (i = PLL0USB_M; i <= 0x8000; i++) {
+        x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+      }
+  }
+  
+  if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
+  else        selp = 31;
+  
+  if      (PLL0USB_M > 16384) seli = 1;
+  else if (PLL0USB_M >  8192) seli = 2;
+  else if (PLL0USB_M >  2048) seli = 4;
+  else if (PLL0USB_M >=  501) seli = 8;
+  else if (PLL0USB_M >=   60) seli = 4 * (1024 / (PLL0USB_M + 9));
+  else                        seli = (PLL0USB_M & 0x3C) + 4;
+  LPC_CGU->PLL0USB_MDIV   =  (selp   << 17) |
+                             (seli   << 22) |
+                             (x      <<  0);
+
+  /* N divider                                                                */
+  x = 0x80;
+  switch (PLL0USB_N) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000302;
+      break;
+    case 2:  x = 0x00000202;
+      break;
+    default: 
+      for (i = PLL0USB_N; i <= 0x0100; i++) {
+        x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV = (x << 12);
+  
+  /* P divider                                                                */
+  x = 0x10;
+  switch (PLL0USB_P) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000062;
+      break;
+    case 2:  x = 0x00000042;
+      break;
+    default:
+      for (i = PLL0USB_P; i <= 0x200; i++) {
+        x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
+      }
+  } 
+  LPC_CGU->PLL0USB_NP_DIV |= x;
+  
+  LPC_CGU->PLL0USB_CTRL  = (PLL0USB_CLK_SEL   << 24) | /* Clock source sel    */                             
+                           (1                 << 11) | /* Autoblock En        */
+                           (1                 << 4 ) | /* PLL0USB clock en    */
+                           (PLL0USB_DIRECTO   << 3 ) | /* Direct output       */
+                           (PLL0USB_DIRECTI   << 2 ) | /* Direct input        */
+                           (PLL0USB_BYPASS    << 1 ) | /* PLL bypass          */
+                           (0                 << 0 ) ; /* PLL0USB Enabled     */
+  while (!(LPC_CGU->PLL0USB_STAT & 1));
+
+
+/*----------------------------------------------------------------------------
+  Integer divider Setup
+ *----------------------------------------------------------------------------*/
+  
+  /* Configure integer dividers                                               */
+  LPC_CGU->IDIVA_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVA_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVA_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVB_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVB_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVB_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVC_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVC_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVC_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVD_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVD_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVD_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVE_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVE_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVE_CLK_SEL  << 24) ;  /* Clock source             */
+}
+
+
+/*----------------------------------------------------------------------------
+  Approximate delay function (must be used after SystemCoreClockUpdate() call)
+ *----------------------------------------------------------------------------*/
+#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
+
+static void WaitUs (uint32_t us) {
+  uint32_t cyc = us * CPU_NANOSEC(1000)/4;
+  while(cyc--);
+}
+
+
+/*----------------------------------------------------------------------------
+  External Memory Controller Definitions
+ *----------------------------------------------------------------------------*/
+#define SDRAM_ADDR_BASE 0x28000000      /* SDRAM base address                 */
+/* Write Mode register macro                                                  */
+#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
+
+/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
+#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
+#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
+
+#define EMC_CLK_DLY_TIM_2  (0x7777)     /* 3.5 ns delay for the EMC clock out */
+#define EMC_CLK_DLY_TIM_0  (0x0000)     /* No delay for the EMC clock out     */
+
+typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
+
+const uint16_t emcdivby2_opc[] =  {
+  0x6803,        /*      LDR  R3,[R0,#0]      ; Load CREG6          */
+  0xF443,0x3380, /*      ORR  R3,R3,#0x10000  ; Set Divided by 2    */
+  0x6003,        /*      STR  R3,[R0,#0]      ; Store CREG6         */
+  0x600A,        /*      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg    */
+  0x684B,        /* loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT    */
+  0x07DB,        /*      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0 */
+  0xD0FC,        /*      BEQ  loop            ; Jump if 0           */
+  0x4770,        /*      BX   LR              ; Exit                */
+  0,
+};
+
+#define        emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
+#define        emcdivby2_ram 0x10000000
+
+/*----------------------------------------------------------------------------
+  Initialize external memory controller
+ *----------------------------------------------------------------------------*/
+
+void SystemInit_ExtMemCtl (void) {
+  uint32_t emcdivby2_buf[emcdivby2_szw];
+  uint32_t div, n;
+
+  /* Select and enable EMC branch clock */
+  LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
+  while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
+
+  /* Set EMC clock output delay */  
+  if (SystemCoreClock < 80000000UL) {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
+  }
+  else {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
+  }
+
+  /* Configure EMC port pins */
+  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
+  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
+  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
+  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
+  LPC_SCU->SFSP1_4  = EMC_PIN_SET | 3;  /* P1_4:  BLS0                        */
+  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
+  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
+  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
+  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
+  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
+  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
+  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
+  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
+  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
+  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */
+
+  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
+  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
+  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
+  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
+  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
+  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
+  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
+  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
+  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
+  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
+  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */
+
+  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
+  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
+  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
+  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
+  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
+  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
+  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
+  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
+
+  LPC_SCU->SFSP6_1  = EMC_PIN_SET | 1;  /* P6_1:  DYCS1                       */
+  LPC_SCU->SFSP6_2  = EMC_PIN_SET | 1;  /* P6_3:  CKEOUT1                     */
+  LPC_SCU->SFSP6_3  = EMC_PIN_SET | 3;  /* P6_3:  CS1                         */
+  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
+  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
+  LPC_SCU->SFSP6_6  = EMC_PIN_SET | 1;  /* P6_6:  BLS1                        */
+  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
+  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
+  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
+  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
+  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
+  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */
+
+  LPC_SCU->SFSPA_4  = EMC_PIN_SET | 3;  /* PA_4:  A23                         */
+
+  LPC_SCU->SFSPD_0  = EMC_PIN_SET | 2;  /* PD_0:  DQMOUT2                     */
+  LPC_SCU->SFSPD_1  = EMC_PIN_SET | 2;  /* PD_1:  CKEOUT2                     */
+  LPC_SCU->SFSPD_2  = EMC_PIN_SET | 2;  /* PD_2:  D16                         */
+  LPC_SCU->SFSPD_3  = EMC_PIN_SET | 2;  /* PD_3:  D17                         */
+  LPC_SCU->SFSPD_4  = EMC_PIN_SET | 2;  /* PD_4:  D18                         */
+  LPC_SCU->SFSPD_5  = EMC_PIN_SET | 2;  /* PD_5:  D19                         */
+  LPC_SCU->SFSPD_6  = EMC_PIN_SET | 2;  /* PD_6:  D20                         */
+  LPC_SCU->SFSPD_7  = EMC_PIN_SET | 2;  /* PD_7:  D21                         */ 
+  LPC_SCU->SFSPD_8  = EMC_PIN_SET | 2;  /* PD_8:  D22                         */
+  LPC_SCU->SFSPD_9  = EMC_PIN_SET | 2;  /* PD_9:  D23                         */
+  LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2;  /* PD_10: BLS3                        */
+  LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2;  /* PD_11: CS3                         */
+  LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2;  /* PD_12: CS2                         */
+  LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2;  /* PD_13: BLS2                        */
+  LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2;  /* PD_14: DYCS2                       */
+  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
+  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */
+
+  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
+  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
+  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
+  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
+  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */
+  LPC_SCU->SFSPE_5  = EMC_PIN_SET | 3;  /* PE_5:  D24                         */
+  LPC_SCU->SFSPE_6  = EMC_PIN_SET | 3;  /* PE_6:  D25                         */
+  LPC_SCU->SFSPE_7  = EMC_PIN_SET | 3;  /* PE_7:  D26                         */
+  LPC_SCU->SFSPE_8  = EMC_PIN_SET | 3;  /* PE_8:  D27                         */
+  LPC_SCU->SFSPE_9  = EMC_PIN_SET | 3;  /* PE_9:  D28                         */
+  LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3;  /* PE_10: D29                         */
+  LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3;  /* PE_11: D30                         */
+  LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3;  /* PE_12: D31                         */
+  LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3;  /* PE_13: DQMOUT3                     */
+  LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3;  /* PE_14: DYCS3                       */
+  LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3;  /* PE_15: CKEOUT3                     */
+
+  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
+  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */
+
+  div = 0;
+  if (SystemCoreClock > 120000000UL) {
+    /* Use EMC clock divider and EMC clock output delay */
+    div = 1;
+    /* Following code must be executed in RAM to ensure stable operation      */
+    /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
+    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
+    /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));                           */
+
+    /* This code configures EMC clock divider and is executed in RAM          */
+    for (n = 0; n < emcdivby2_szw; n++) {
+      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
+      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
+    }
+    __ISB();
+    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
+    for (n = 0; n < emcdivby2_szw; n++) {
+      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
+    }
+  }
+
+  /* Configure EMC clock-out pins                                             */
+  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
+  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
+  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
+  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
+  
+  /* Static memory configuration (chip select 0)                              */
+#if (USE_EXT_STAT_MEM_CS0)
+  LPC_EMC->STATICCONFIG0  = (1 <<  7) | /* Byte lane state: use WE signal     */
+                            (2 <<  0) ; /* Memory width 32-bit                */
+  LPC_EMC->STATICWAITOEN0 = (0 <<  0) ; /* Wait output enable: No delay       */
+
+  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
+  LPC_EMC->STATICWAITRD0  = EMC_NANOSEC(90, SystemCoreClock, div);
+  LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer                      */
+#endif
+  
+  /* Dynamic memory configuration (chip select 0)                             */
+#if (USE_EXT_DYN_MEM_CS0)
+
+  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
+  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
+                               (0 << 12) |  /* AM[12]   = 0                   */
+                               (2 <<  9) |  /* AM[11:9] = 2                   */
+                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
+
+  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
+  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
+
+  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
+  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
+  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);
+
+  WaitUs (100);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
+  WaitUs (1);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (1);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
+
+  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
+  WR_MODE(((3 << 4) | 2) << 12);
+
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
+  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
+#endif
+}
+
+
+/*----------------------------------------------------------------------------
+  Measure frequency using frequency monitor
+ *----------------------------------------------------------------------------*/
+uint32_t MeasureFreq (uint32_t clk_sel) {
+  uint32_t fcnt, rcnt, fout;
+
+  /* Set register values */
+  LPC_CGU->FREQ_MON &= ~(1 << 23);                /* Stop frequency counters  */
+  LPC_CGU->FREQ_MON  = (clk_sel << 24) | 511;     /* RCNT == 511              */
+  LPC_CGU->FREQ_MON |= (1 << 23);                 /* Start RCNT and FCNT      */
+  while (LPC_CGU->FREQ_MON & (1 << 23)) {
+    fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+    rcnt = (LPC_CGU->FREQ_MON     ) & 0x01FF;
+    if (fcnt == 0 && rcnt == 0) {
+      return (0);                                 /* No input clock present   */
+    }
+  }
+  fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
+
+  return (fout);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get PLL1 (divider and multiplier) parameters
+ *----------------------------------------------------------------------------*/
+__inline uint32_t GetPLL1Param (void) {
+  uint32_t ctrl;
+  uint32_t p;
+  uint32_t div, mul;
+
+  ctrl = LPC_CGU->PLL1_CTRL;
+  div = ((ctrl >> 12) & 0x03) + 1;
+  mul = ((ctrl >> 16) & 0xFF) + 1;
+  p = 1 << ((ctrl >>  8) & 0x03);
+
+  if (ctrl & (1 << 1)) {
+    /* Bypass = 1, PLL1 input clock sent to post-dividers */
+    if (ctrl & (1 << 7)) {
+      div *= (2*p);
+    }
+  }
+  else {
+    /* Direct and integer mode */
+    if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
+      /* Non-integer mode */
+      div *= (2*p);
+    }
+  }
+  return ((div << 8) | (mul)); 
+}
+
+
+/*----------------------------------------------------------------------------
+  Get input clock source for specified clock generation block
+ *----------------------------------------------------------------------------*/
+int32_t GetClkSel (uint32_t clk_src) {
+  uint32_t reg;
+  int32_t clk_sel = -1;
+
+  switch (clk_src) {
+    case CLK_SRC_IRC:
+    case CLK_SRC_ENET_RX:
+    case CLK_SRC_ENET_TX:
+    case CLK_SRC_GP_CLKIN:
+      return (clk_src);
+
+    case CLK_SRC_32KHZ:
+      return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
+    case CLK_SRC_XTAL:
+     return  (LPC_CGU->XTAL_OSC_CTRL & 1)       ? (-1) : (CLK_SRC_XTAL);
+    
+    case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL;    break;
+    case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL;  break;
+    case CLK_SRC_PLL1:  reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
+
+    case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL;      break;
+    case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL;      break;
+    case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL;      break;
+    case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL;      break;
+    case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL;      break;
+    
+    default:
+      return (clk_sel);
+  }
+  if (!(reg & 1)) {
+    clk_sel = (reg >> 24) & 0x1F;
+  }
+  return (clk_sel);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get clock frequency for specified clock source
+ *----------------------------------------------------------------------------*/
+uint32_t GetClockFreq (uint32_t clk_src) {
+  uint32_t tmp;
+  uint32_t mul        =  1;
+  uint32_t div        =  1;
+  uint32_t main_freq  =  0;
+  int32_t  clk_sel    = clk_src;
+
+  do {
+    switch (clk_sel) {      
+      case CLK_SRC_32KHZ:    main_freq = CLK_32KHZ;     break; 
+      case CLK_SRC_IRC:      main_freq = CLK_IRC;       break;
+      case CLK_SRC_ENET_RX:  main_freq = CLK_ENET_RX;   break; 
+      case CLK_SRC_ENET_TX:  main_freq = CLK_ENET_TX;   break; 
+      case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN;  break; 
+      case CLK_SRC_XTAL:     main_freq = CLK_XTAL;      break;
+  
+      case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0x3) + 1; break;
+  
+      case CLK_SRC_PLL0U: /* Not implemented */  break;
+      case CLK_SRC_PLL0A: /* Not implemented */  break;
+      
+      case CLK_SRC_PLL1:
+        tmp = GetPLL1Param ();
+        mul *= (tmp     ) & 0xFF;       /* PLL input clock multiplier         */
+        div *= (tmp >> 8) & 0xFF;       /* PLL input clock divider            */
+        break;
+      
+      default:
+        return (0);                     /* Clock not running or not supported */
+    }
+    if (main_freq == 0) {
+      clk_sel = GetClkSel (clk_sel);
+    }
+  }
+  while (main_freq == 0);
+
+  return ((main_freq * mul) / div);
+}
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) {
+  /* Check BASE_M4_CLK connection */
+  uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
+
+  /* Update core clock frequency */
+  SystemCoreClock = GetClockFreq (base_src);
+}
+
+
+extern uint32_t getPC (void);
+
+/*----------------------------------------------------------------------------
+  Initialize the system
+ *----------------------------------------------------------------------------*/
+void SystemInit (void) {
+
+  #if (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  /* Disable SysTick timer                                                    */
+  SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+#ifdef CORE_M4
+  /* Set vector table pointer */
+  SCB->VTOR = getPC() & 0xFFF00000;
+#endif
+  /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
+  SetClock();
+
+  /* Update SystemCoreClock variable */
+  SystemCoreClockUpdate();
+
+  /* Configure External Memory Controller */
+  SystemInit_ExtMemCtl ();
+}
diff --git a/bsp/lpc43xx/Libraries/Device/SConscript b/bsp/lpc43xx/Libraries/Device/SConscript
new file mode 100644
index 0000000000..d0aac1b070
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/SConscript
@@ -0,0 +1,30 @@
+# RT-Thread building script for component
+
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Split('''
+NXP/LPC43xx/Source/Templates/system_LPC43xx.c
+''')
+CPPPATH = [cwd + '/NXP/LPC43xx/Include', cwd + '/../CMSIS/Include']
+CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
+
+# add for startup script 
+if rtconfig.USE_CORE =='CORE_M4':
+	if rtconfig.CROSS_TOOL == 'gcc':
+		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s']
+	elif rtconfig.CROSS_TOOL == 'keil':
+		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s']
+	elif rtconfig.CROSS_TOOL == 'iar':
+		src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s']
+else:
+	if rtconfig.CROSS_TOOL == 'gcc':
+		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s']
+	elif rtconfig.CROSS_TOOL == 'keil':
+		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s']
+	elif rtconfig.CROSS_TOOL == 'iar':
+		src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s']
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/lpc43xx/Libraries/SConscript b/bsp/lpc43xx/Libraries/SConscript
new file mode 100644
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/lpc43xx/M0/SConscript b/bsp/lpc43xx/M0/SConscript
new file mode 100644
index 0000000000..e2c31c0755
--- /dev/null
+++ b/bsp/lpc43xx/M0/SConscript
@@ -0,0 +1,13 @@
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(os.path.join(cwd, '..'))
+
+for d in list:
+    if (d != 'M4' and d != 'M0'):
+        path = os.path.join(cwd, '..', d)
+        if os.path.isfile(os.path.join(path, 'SConscript')):
+            objs = objs + SConscript(os.path.join(path, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/lpc43xx/M0/SConstruct b/bsp/lpc43xx/M0/SConstruct
new file mode 100644
index 0000000000..f6f21f4ec4
--- /dev/null
+++ b/bsp/lpc43xx/M0/SConstruct
@@ -0,0 +1,29 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# do building 
+DoBuilding(TARGET, objs)
diff --git a/bsp/lpc43xx/M0/rtconfig.h b/bsp/lpc43xx/M0/rtconfig.h
new file mode 100644
index 0000000000..84fc28028c
--- /dev/null
+++ b/bsp/lpc43xx/M0/rtconfig.h
@@ -0,0 +1,230 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX 8
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE   4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX  32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
+#define RT_TICK_PER_SECOND  1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE  512
+// <bool name="RT_USING_MODULE" description="Using Application Module" default="true" />
+//#define RT_USING_MODULE
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
+#define RT_DEBUG_INIT   0
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+#define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO    4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE  512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND    100
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+#define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    256
+// <bool name="RT_USING_MTD_NAND" description="Using MTD NAND Framework" default="true" />
+//#define RT_USING_MTD_NAND
+// <bool name="RT_MTD_NAND_DEBUG" description="Enable MTD NAND Framework Debug" default="true" />
+//#define RT_MTD_NAND_DEBUG
+// <bool name="RT_USING_NFTL" description="Using NFTL layer" default="true" />
+//#define RT_USING_NFTL
+// <bool name="RT_USING_SPI" description="Using SPI Device Driver Framework" default="true" />
+//#define RT_USING_SPI
+// <bool name="RT_USING_I2C" description="Using I2C Device Driver Framework" default="true" />
+//#define RT_USING_I2C
+// <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" />
+//#define RT_USING_RTC
+// <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" />
+#define RT_MMCSD_THREAD_PREORITY    15
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE  128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+//#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE 4096
+// <bool name="FINSH_USING_MSH" description="Using module shell in finsh" default="true" />
+//#define FINSH_USING_MSH
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
+// #define RT_USING_NEWLIB
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+//#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+//#define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+//#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
+#define DFS_FILESYSTEM_TYPES_MAX  4
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX 4
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX           16
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" />
+#define RT_DFS_ELM_DRIVES    4
+// <bool name="RT_DFS_ELM_REENTRANT" description="Support reentrant" default="true" />
+#define RT_DFS_ELM_REENTRANT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN with static LFN working buffer">1</item>
+// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
+// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN  3
+// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
+#define RT_DFS_ELM_CODE_PAGE    936
+// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
+#define RT_DFS_ELM_CODE_PAGE_FILE
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN  256
+// <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" />
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  4096
+// <bool name="RT_DFS_ELM_USE_ERASE" description="Enable erase feature for flash" default="true" />
+#define RT_DFS_ELM_USE_ERASE
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_ROMFS" description="Using ROMFS" default="false" />
+//#define RT_USING_DFS_ROMFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS" default="false" />
+//#define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="The exported NFS host path" default="192.168.1.10:/" />
+#define RT_NFS_HOST_EXPORT  "192.168.1.20:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+//#define RT_USING_LWIP
+// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
+#define RT_USING_LWIP141
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
+#define RT_LWIP_PBUF_NUM    4
+// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
+#define RT_LWIP_TCP_PCB_NUM 3
+// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
+#define RT_LWIP_TCP_SND_BUF 4086
+// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
+#define RT_LWIP_TCP_WND 2048
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+// #define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
+#define RT_LWIP_TCP_SEG_NUM 8
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+
+
+// </RDTConfigurator>
+
+
+#endif
diff --git a/bsp/lpc43xx/M0/rtconfig.py b/bsp/lpc43xx/M0/rtconfig.py
new file mode 100644
index 0000000000..f548669122
--- /dev/null
+++ b/bsp/lpc43xx/M0/rtconfig.py
@@ -0,0 +1,139 @@
+import os
+
+# core to be use
+USE_CORE = 'CORE_M0'
+#USE_CORE = 'CORE_M4'
+
+# toolchains options
+ARCH='arm'
+
+if USE_CORE == 'CORE_M4':
+    CPU = 'cortex-m4'
+else:
+    CPU = 'cortex-m0'
+
+CROSS_TOOL='keil'
+
+
+# get setting from environment.
+if os.getenv('RTT_CC'):
+        CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM = 'gcc'
+    EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM = 'armcc'
+    EXEC_PATH = r'D:/Keil'
+elif CROSS_TOOL == 'iar':
+    PLATFORM = 'iar'
+    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    if USE_CORE == 'CORE_M4':
+        DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
+    CFLAGS = DEVICE 
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    if USE_CORE == 'CORE_M4':
+        CFLAGS += ' --cpu=Cortex-M4' 
+        CFLAGS += ' --fpu=None'
+    else:
+        CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e' 
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+    CFLAGS += ' --use_c++_inline'
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    if USE_CORE == 'CORE_M4':
+        AFLAGS += ' --cpu Cortex-M4' 
+        AFLAGS += ' --fpu None' 
+    else:
+        AFLAGS += ' --cpu Cortex-M0' 
+
+    LFLAGS = ' --config lpc43xx_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny' 
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''
diff --git a/bsp/lpc43xx/M0/template.uvopt b/bsp/lpc43xx/M0/template.uvopt
new file mode 100644
index 0000000000..59c68db91e
--- /dev/null
+++ b/bsp/lpc43xx/M0/template.uvopt
@@ -0,0 +1,349 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>LPC43xx SPIFI</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC43xx\UM10503.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC43xx\LPC435X_3X_2X_1X.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O975 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC8000 -FN3 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FF2LPC18xx43xx_S25FL032 -FS214000000 -FL2400000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC43xx RAM</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC43xx\UM10503.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC43xx\LPC435X_3X_2X_1X.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\Dbg_RAM.ini</tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O783 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC8000 -FN3 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FF2LPC18xx43xx_S25FL032 -FS214000000 -FL2400000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
diff --git a/bsp/lpc43xx/M0/template.uvproj b/bsp/lpc43xx/M0/template.uvproj
new file mode 100644
index 0000000000..95f6c36a2b
--- /dev/null
+++ b/bsp/lpc43xx/M0/template.uvproj
@@ -0,0 +1,777 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>LPC43xx SPIFI</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4357</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll>
+          <DeviceId>6414</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>1</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>1</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>0</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x14000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x14000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+    <Target>
+      <TargetName>LPC43xx RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4357</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll>
+          <DeviceId>6414</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Dbg_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>1</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>1</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x10000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/lpc43xx/M4/SConscript b/bsp/lpc43xx/M4/SConscript
new file mode 100644
index 0000000000..e2c31c0755
--- /dev/null
+++ b/bsp/lpc43xx/M4/SConscript
@@ -0,0 +1,13 @@
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(os.path.join(cwd, '..'))
+
+for d in list:
+    if (d != 'M4' and d != 'M0'):
+        path = os.path.join(cwd, '..', d)
+        if os.path.isfile(os.path.join(path, 'SConscript')):
+            objs = objs + SConscript(os.path.join(path, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/lpc43xx/M4/SConstruct b/bsp/lpc43xx/M4/SConstruct
new file mode 100644
index 0000000000..f6f21f4ec4
--- /dev/null
+++ b/bsp/lpc43xx/M4/SConstruct
@@ -0,0 +1,29 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# do building 
+DoBuilding(TARGET, objs)
diff --git a/bsp/lpc43xx/M4/rtconfig.h b/bsp/lpc43xx/M4/rtconfig.h
new file mode 100644
index 0000000000..84fc28028c
--- /dev/null
+++ b/bsp/lpc43xx/M4/rtconfig.h
@@ -0,0 +1,230 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX 8
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE   4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX  32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
+#define RT_TICK_PER_SECOND  1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE  512
+// <bool name="RT_USING_MODULE" description="Using Application Module" default="true" />
+//#define RT_USING_MODULE
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
+#define RT_DEBUG_INIT   0
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+#define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO    4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE  512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND    100
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+#define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    256
+// <bool name="RT_USING_MTD_NAND" description="Using MTD NAND Framework" default="true" />
+//#define RT_USING_MTD_NAND
+// <bool name="RT_MTD_NAND_DEBUG" description="Enable MTD NAND Framework Debug" default="true" />
+//#define RT_MTD_NAND_DEBUG
+// <bool name="RT_USING_NFTL" description="Using NFTL layer" default="true" />
+//#define RT_USING_NFTL
+// <bool name="RT_USING_SPI" description="Using SPI Device Driver Framework" default="true" />
+//#define RT_USING_SPI
+// <bool name="RT_USING_I2C" description="Using I2C Device Driver Framework" default="true" />
+//#define RT_USING_I2C
+// <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" />
+//#define RT_USING_RTC
+// <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" />
+#define RT_MMCSD_THREAD_PREORITY    15
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE  128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+//#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE 4096
+// <bool name="FINSH_USING_MSH" description="Using module shell in finsh" default="true" />
+//#define FINSH_USING_MSH
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
+// #define RT_USING_NEWLIB
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+//#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+//#define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+//#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
+#define DFS_FILESYSTEM_TYPES_MAX  4
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX 4
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX           16
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" />
+#define RT_DFS_ELM_DRIVES    4
+// <bool name="RT_DFS_ELM_REENTRANT" description="Support reentrant" default="true" />
+#define RT_DFS_ELM_REENTRANT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN with static LFN working buffer">1</item>
+// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
+// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN  3
+// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
+#define RT_DFS_ELM_CODE_PAGE    936
+// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
+#define RT_DFS_ELM_CODE_PAGE_FILE
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN  256
+// <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" />
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  4096
+// <bool name="RT_DFS_ELM_USE_ERASE" description="Enable erase feature for flash" default="true" />
+#define RT_DFS_ELM_USE_ERASE
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_ROMFS" description="Using ROMFS" default="false" />
+//#define RT_USING_DFS_ROMFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS" default="false" />
+//#define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="The exported NFS host path" default="192.168.1.10:/" />
+#define RT_NFS_HOST_EXPORT  "192.168.1.20:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+//#define RT_USING_LWIP
+// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
+#define RT_USING_LWIP141
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
+#define RT_LWIP_PBUF_NUM    4
+// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
+#define RT_LWIP_TCP_PCB_NUM 3
+// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
+#define RT_LWIP_TCP_SND_BUF 4086
+// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
+#define RT_LWIP_TCP_WND 2048
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+// #define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
+#define RT_LWIP_TCP_SEG_NUM 8
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+
+
+// </RDTConfigurator>
+
+
+#endif
diff --git a/bsp/lpc43xx/M4/rtconfig.py b/bsp/lpc43xx/M4/rtconfig.py
new file mode 100644
index 0000000000..d8c21c1dc8
--- /dev/null
+++ b/bsp/lpc43xx/M4/rtconfig.py
@@ -0,0 +1,139 @@
+import os
+
+# core to be use
+#USE_CORE = 'CORE_M0'
+USE_CORE = 'CORE_M4'
+
+# toolchains options
+ARCH='arm'
+
+if USE_CORE == 'CORE_M4':
+    CPU = 'cortex-m4'
+else:
+    CPU = 'cortex-m0'
+
+CROSS_TOOL='keil'
+
+
+# get setting from environment.
+if os.getenv('RTT_CC'):
+        CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM = 'gcc'
+    EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM = 'armcc'
+    EXEC_PATH = r'D:/Keil'
+elif CROSS_TOOL == 'iar':
+    PLATFORM = 'iar'
+    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    if USE_CORE == 'CORE_M4':
+        DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
+    CFLAGS = DEVICE 
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    if USE_CORE == 'CORE_M4':
+        CFLAGS += ' --cpu=Cortex-M4' 
+        CFLAGS += ' --fpu=None'
+    else:
+        CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e' 
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+    CFLAGS += ' --use_c++_inline'
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    if USE_CORE == 'CORE_M4':
+        AFLAGS += ' --cpu Cortex-M4' 
+        AFLAGS += ' --fpu None' 
+    else:
+        AFLAGS += ' --cpu Cortex-M0' 
+
+    LFLAGS = ' --config lpc43xx_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny' 
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''
diff --git a/bsp/lpc43xx/M4/template.uvopt b/bsp/lpc43xx/M4/template.uvopt
new file mode 100644
index 0000000000..5ea3e413e1
--- /dev/null
+++ b/bsp/lpc43xx/M4/template.uvopt
@@ -0,0 +1,349 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>LPC43xx SPIFI</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC43xx\UM10503.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC43xx\LPC435X_3X_2X_1X.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O783 -O783 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC8000 -FN3 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FF2LPC18xx43xx_S25FL032 -FS214000000 -FL2400000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC43xx RAM</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC43xx\UM10503.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC43xx\LPC435X_3X_2X_1X.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\Dbg_RAM.ini</tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O783 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC8000 -FN3 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FF2LPC18xx43xx_S25FL032 -FS214000000 -FL2400000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
diff --git a/bsp/lpc43xx/M4/template.uvproj b/bsp/lpc43xx/M4/template.uvproj
new file mode 100644
index 0000000000..f93cbd2c11
--- /dev/null
+++ b/bsp/lpc43xx/M4/template.uvproj
@@ -0,0 +1,777 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>LPC43xx SPIFI</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4357</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll>
+          <DeviceId>6414</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>1</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>0</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x14000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x14000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+    <Target>
+      <TargetName>LPC43xx RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4357</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll>
+          <DeviceId>6414</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Dbg_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>1</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x10000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/lpc43xx/applications/SConscript b/bsp/lpc43xx/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/lpc43xx/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/lpc43xx/applications/application.c b/bsp/lpc43xx/applications/application.c
new file mode 100644
index 0000000000..e40ad02e48
--- /dev/null
+++ b/bsp/lpc43xx/applications/application.c
@@ -0,0 +1,84 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-13     xiaonong     port for lpc43xx
+ */
+
+#include <rtthread.h>
+#include <board.h>
+#include <rtdevice.h>
+#include "drv_led.h"
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+/* thread phase init */
+void rt_init_thread_entry(void *parameter)
+{
+#ifdef RT_USING_FINSH
+    /* initialize finsh */
+    finsh_system_init();
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+/*the led thread*/
+ALIGN(RT_ALIGN_SIZE)
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+static void led_thread_entry(void *parameter)
+{
+    rt_uint8_t led_value = 0;
+    rt_device_t led_dev;
+    rt_led_hw_init();
+    led_dev = rt_device_find("led");
+    if (led_dev == RT_NULL)
+    {
+        rt_kprintf("can not find the led device!\n");
+        return;
+    }
+    while (1)
+    {
+        /* led0 on */
+        led_value = 1;
+        led_dev->write(led_dev, 0, &led_value, 1);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
+
+        /* led0 off */
+        led_value = 0;
+        led_dev->write(led_dev, 0, &led_value, 1);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+    }
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+    rt_err_t result;
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry, RT_NULL,
+                           2048, RT_THREAD_PRIORITY_MAX / 3, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+    /* init led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t *)&led_stack[0],
+                            sizeof(led_stack),
+                            20,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+    return 0;
+}
diff --git a/bsp/lpc43xx/applications/startup.c b/bsp/lpc43xx/applications/startup.c
new file mode 100644
index 0000000000..f6cf534b03
--- /dev/null
+++ b/bsp/lpc43xx/applications/startup.c
@@ -0,0 +1,74 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2014-07-13     xiaonong      for LPC43xx
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+extern int rt_application_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+#if LPC_EXT_SDRAM
+    rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
+    sram_init();
+#else
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize system timer*/
+    rt_system_timer_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize timer thread */
+    rt_system_timer_thread_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
diff --git a/bsp/lpc43xx/drivers/SConscript b/bsp/lpc43xx/drivers/SConscript
new file mode 100644
index 0000000000..e5f4cd4945
--- /dev/null
+++ b/bsp/lpc43xx/drivers/SConscript
@@ -0,0 +1,14 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_LWIP') == False:
+	SrcRemove(src, 'drv_emac.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/lpc43xx/drivers/board.c b/bsp/lpc43xx/drivers/board.c
new file mode 100644
index 0000000000..421298c19e
--- /dev/null
+++ b/bsp/lpc43xx/drivers/board.c
@@ -0,0 +1,77 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2014-06-20     xiaonong     ported to LPC43xx
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+extern void SystemCoreClockUpdate(void);
+/**
+ * This function will initial LPC43xx board.
+ */
+void rt_hw_board_init()
+{
+#ifdef CORE_M4
+    /* NVIC Configuration */
+#define NVIC_VTOR_MASK              0x3FFFFF80
+#ifdef  VECT_TAB_RAM
+    /* Set the Vector Table base location at 0x10000000 */
+    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+#else  /* VECT_TAB_FLASH  */
+    /* Set the Vector Table base location at 0x00000000 */
+    SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
+#endif
+#endif
+    /* update the core clock */
+    SystemCoreClockUpdate();
+
+    /* init systick */
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1);
+
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+
+    /* init uart device */
+    rt_hw_uart_init();
+
+    /* setup the console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#if LPC_EXT_SDRAM == 1
+    lpc_sdram_hw_init();
+    mpu_init();
+#endif
+}
+
+
+
diff --git a/bsp/lpc43xx/drivers/board.h b/bsp/lpc43xx/drivers/board.h
new file mode 100644
index 0000000000..393dc30c91
--- /dev/null
+++ b/bsp/lpc43xx/drivers/board.h
@@ -0,0 +1,60 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2010-02-04     Magicoe      add board.h to LPC176x bsp
+ * 2013-12-18     Bernard      porting to LPC4088 bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "LPC43xx.h"
+#include <rtthread.h>
+
+/* disable SDRAM in default */
+#ifndef LPC_EXT_SDRAM
+#define LPC_EXT_SDRAM       0
+#endif
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
+#define LPC_EXT_SDRAM_BEGIN    0xA0000000
+// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
+#define LPC_EXT_SDRAM_END      0xA2000000
+
+// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
+#define RT_USING_UART0
+// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
+//#define RT_USING_UART1
+// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
+//#define RT_USING_UART2
+
+// </RDTConfigurator>
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+#define HEAP_END    (void*)(0x10000000 + 0x8000)
+
+void rt_hw_board_init(void);
+int  rt_hw_board_heap_init(void);
+
+
+#endif
diff --git a/bsp/lpc43xx/drivers/drv_emac.c b/bsp/lpc43xx/drivers/drv_emac.c
new file mode 100644
index 0000000000..80aecff132
--- /dev/null
+++ b/bsp/lpc43xx/drivers/drv_emac.c
@@ -0,0 +1,536 @@
+/*
+ * File      : drv_emac.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-19     Bernard      porting from LPC17xx drivers.
+ */
+
+#include <rtthread.h>
+#include "lwipopts.h"
+#include <netif/ethernetif.h>
+
+#include "lpc_iap.h"
+#include "drv_emac.h"
+
+#define EMAC_PHY_AUTO       0
+#define EMAC_PHY_10MBIT     1
+#define EMAC_PHY_100MBIT    2
+
+#define MAX_ADDR_LEN 6
+static rt_uint32_t ETH_RAM_BASE[4 * 1024] SECTION("ETH_RAM");
+
+/* EMAC variables located in 16K Ethernet SRAM */
+#define RX_DESC_BASE         (uint32_t)&ETH_RAM_BASE[0]
+#define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
+#define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
+#define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
+#define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)
+#define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)
+
+/* RX and TX descriptor and status definitions. */
+#define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
+#define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
+#define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
+#define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
+#define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
+#define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
+#define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
+#define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)
+#define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)
+
+struct lpc_emac
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+
+    rt_uint8_t phy_mode;
+
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
+};
+static struct lpc_emac lpc_emac_device;
+static struct rt_semaphore sem_lock;
+static struct rt_event tx_event;
+
+/* Local Function Prototypes */
+static void write_PHY(rt_uint32_t PhyReg, rt_uint32_t Value);
+static rt_uint16_t read_PHY(rt_uint8_t PhyReg) ;
+
+void ENET_IRQHandler(void)
+{
+    rt_uint32_t status;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    status = LPC_EMAC->IntStatus;
+
+    if (status & INT_RX_DONE)
+    {
+        /* Disable EMAC RxDone interrupts. */
+        LPC_EMAC->IntEnable = INT_TX_DONE;
+
+        /* a frame has been received */
+        eth_device_ready(&(lpc_emac_device.parent));
+    }
+    else if (status & INT_TX_DONE)
+    {
+        /* set event */
+        rt_event_send(&tx_event, 0x01);
+    }
+
+    if (status & INT_RX_OVERRUN)
+    {
+        rt_kprintf("rx overrun\n");
+    }
+
+    if (status & INT_TX_UNDERRUN)
+    {
+        rt_kprintf("tx underrun\n");
+    }
+
+    /* Clear the interrupt. */
+    LPC_EMAC->IntClear = status;
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/* phy write */
+static void write_PHY(rt_uint32_t PhyReg, rt_uint32_t Value)
+{
+    unsigned int tout;
+
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Value;
+
+    /* Wait utill operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_WR_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
+}
+
+/* phy read */
+static rt_uint16_t read_PHY(rt_uint8_t PhyReg)
+{
+    rt_uint32_t tout;
+
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
+
+    /* Wait until operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_RD_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
+    LPC_EMAC->MCMD = 0;
+    return (LPC_EMAC->MRDD);
+}
+
+/* init rx descriptor */
+rt_inline void rx_descr_init(void)
+{
+    rt_uint32_t i;
+
+    for (i = 0; i < NUM_RX_FRAG; i++)
+    {
+        RX_DESC_PACKET(i)  = RX_BUF(i);
+        RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE - 1);
+        RX_STAT_INFO(i)    = 0;
+        RX_STAT_HASHCRC(i) = 0;
+    }
+
+    /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
+    LPC_EMAC->RxStatus        = RX_STAT_BASE;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
+
+    /* Rx Descriptors Point to 0 */
+    LPC_EMAC->RxConsumeIndex  = 0;
+}
+
+/* init tx descriptor */
+rt_inline void tx_descr_init(void)
+{
+    rt_uint32_t i;
+
+    for (i = 0; i < NUM_TX_FRAG; i++)
+    {
+        TX_DESC_PACKET(i) = TX_BUF(i);
+        TX_DESC_CTRL(i)   = (1ul << 31) | (1ul << 30) | (1ul << 29) | (1ul << 28) | (1ul << 26) | (ETH_FRAG_SIZE - 1);
+        TX_STAT_INFO(i)   = 0;
+    }
+
+    /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
+    LPC_EMAC->TxStatus        = TX_STAT_BASE;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
+
+    /* Tx Descriptors Point to 0 */
+    LPC_EMAC->TxProduceIndex  = 0;
+}
+
+/*
+TX_EN     P1_4
+TXD0      P1_0
+TXD1      P1_1
+
+RXD0      P1_9
+RXD1      P1_10
+RX_ER     P1_14
+CRS_DV    P1_8
+
+MDC       P1_16
+MDIO      P1_17
+
+REF_CLK   P1_15
+*/
+static rt_err_t lpc_emac_init(rt_device_t dev)
+{
+    /* Initialize the EMAC ethernet controller. */
+    rt_uint32_t regv, tout;
+
+    /* Power Up the EMAC controller. */
+    LPC_SC->PCONP |= (1UL << 30);
+
+    /* Enable P1 Ethernet Pins. */
+
+    /**< P1_0  ENET_TXD0 */
+    LPC_IOCON->P1_0 &= ~(0x07);
+    LPC_IOCON->P1_0 |= 0x01;
+    /**< P1_1  ENET_TXD1 */
+    LPC_IOCON->P1_1 &= ~(0x07);
+    LPC_IOCON->P1_1 |= 0x01;
+    /**< P1_4  ENET_TX_EN */
+    LPC_IOCON->P1_4 &= ~(0x07);
+    LPC_IOCON->P1_4 |= 0x01;
+    /**< P1_8  ENET_CRS_DV */
+    LPC_IOCON->P1_8 &= ~(0x07);
+    LPC_IOCON->P1_8 |= 0x01;
+    /**< P1_9  ENET_RXD0 */
+    LPC_IOCON->P1_9 &= ~(0x07);
+    LPC_IOCON->P1_9 |= 0x01;
+    /**< P1_10 ENET_RXD1 */
+    LPC_IOCON->P1_10 &= ~(0x07);
+    LPC_IOCON->P1_10 |= 0x01;
+    /**< P1_14 ENET_RX_ER */
+    LPC_IOCON->P1_14 &= ~(0x07);
+    LPC_IOCON->P1_14 |= 0x01;
+    /**< P1_15 ENET_REF_CLK */
+    LPC_IOCON->P1_15 &= ~(0x07);
+    LPC_IOCON->P1_15 |= 0x01;
+    /**< P1_16 ENET_MDC */
+    LPC_IOCON->P1_16 &= ~(0x07);
+    LPC_IOCON->P1_16 |= 0x01;
+    /**< P1_17 ENET_MDIO */
+    LPC_IOCON->P1_17 &= ~(0x07);
+    LPC_IOCON->P1_17 |= 0x01;
+
+    /* Reset all EMAC internal modules. */
+    LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+                     MAC1_SIM_RES | MAC1_SOFT_RES;
+    LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+
+    /* A short delay after reset. */
+    for (tout = 100; tout; tout--);
+
+    /* Initialize MAC control registers. */
+    LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+    LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+    LPC_EMAC->MAXF = ETH_MAX_FLEN;
+    LPC_EMAC->CLRT = CLRT_DEF;
+    LPC_EMAC->IPGR = IPGR_DEF;
+
+    /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20;
+
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
+
+    /* Reset Reduced MII Logic. */
+    LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->SUPP = SUPP_SPEED;
+
+    /* Put the PHY in reset mode */
+    write_PHY(PHY_REG_BMCR, 0x8000);
+    for (tout = 1000; tout; tout--);
+
+    /* Configure the PHY device */
+    /* Configure the PHY device */
+    switch (lpc_emac_device.phy_mode)
+    {
+    case EMAC_PHY_AUTO:
+        /* Use autonegotiation about the link speed. */
+        write_PHY(PHY_REG_BMCR, PHY_AUTO_NEG);
+        break;
+    case EMAC_PHY_10MBIT:
+        /* Connect at 10MBit */
+        write_PHY(PHY_REG_BMCR, PHY_FULLD_10M);
+        break;
+    case EMAC_PHY_100MBIT:
+        /* Connect at 100MBit */
+        write_PHY(PHY_REG_BMCR, PHY_FULLD_100M);
+        break;
+    }
+    if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
+
+    regv = 0x0004;
+    /* Configure Full/Half Duplex mode. */
+    if (regv & 0x0004)
+    {
+        /* Full duplex is enabled. */
+        LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
+        LPC_EMAC->Command |= CR_FULL_DUP;
+        LPC_EMAC->IPGT     = IPGT_FULL_DUP;
+    }
+    else
+    {
+        /* Half duplex mode. */
+        LPC_EMAC->IPGT = IPGT_HALF_DUP;
+    }
+
+    /* Configure 100MBit/10MBit mode. */
+    if (regv & 0x0002)
+    {
+        /* 10MBit mode. */
+        LPC_EMAC->SUPP = 0;
+    }
+    else
+    {
+        /* 100MBit mode. */
+        LPC_EMAC->SUPP = SUPP_SPEED;
+    }
+
+    /* Set the Ethernet MAC Address registers */
+    LPC_EMAC->SA0 = (lpc_emac_device.dev_addr[1] << 8) | lpc_emac_device.dev_addr[0];
+    LPC_EMAC->SA1 = (lpc_emac_device.dev_addr[3] << 8) | lpc_emac_device.dev_addr[2];
+    LPC_EMAC->SA2 = (lpc_emac_device.dev_addr[5] << 8) | lpc_emac_device.dev_addr[4];
+
+    /* Initialize Tx and Rx DMA Descriptors */
+    rx_descr_init();
+    tx_descr_init();
+
+    /* Receive Broadcast and Perfect Match Packets */
+    LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
+
+    /* Reset all interrupts */
+    LPC_EMAC->IntClear  = 0xFFFF;
+
+    /* Enable EMAC interrupts. */
+    LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+
+    /* Enable receive and transmit mode of MAC Ethernet core */
+    LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
+    LPC_EMAC->MAC1     |= MAC1_REC_EN;
+
+    /* Enable the ENET Interrupt */
+    NVIC_EnableIRQ(ENET_IRQn);
+
+    return RT_EOK;
+}
+
+static rt_err_t lpc_emac_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t lpc_emac_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t lpc_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t lpc_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t lpc_emac_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, lpc_emac_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/* EtherNet Device Interface */
+/* transmit packet. */
+rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p)
+{
+    rt_uint32_t Index, IndexNext;
+    rt_uint8_t *ptr;
+
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if (IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
+
+    /* check whether block is full */
+    while (IndexNext == LPC_EMAC->TxConsumeIndex)
+    {
+        rt_err_t result;
+        rt_uint32_t recved;
+
+        /* there is no block yet, wait a flag */
+        result = rt_event_recv(&tx_event, 0x01,
+                               RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+
+    /* get produce index */
+    Index = LPC_EMAC->TxProduceIndex;
+
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if (IndexNext > LPC_EMAC->TxDescriptorNumber)
+        IndexNext = 0;
+
+    /* copy data to tx buffer */
+    ptr = (rt_uint8_t *)TX_BUF(Index);
+    pbuf_copy_partial(p, ptr, p->tot_len, 0);
+
+    TX_DESC_CTRL(Index) &= ~0x7ff;
+    TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
+
+    /* change index to the next */
+    LPC_EMAC->TxProduceIndex = IndexNext;
+
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
+
+    return RT_EOK;
+}
+
+/* reception packet. */
+struct pbuf *lpc_emac_rx(rt_device_t dev)
+{
+    struct pbuf *p;
+    rt_uint32_t size;
+    rt_uint32_t Index;
+
+    /* init p pointer */
+    p = RT_NULL;
+
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+
+    Index = LPC_EMAC->RxConsumeIndex;
+    if (Index != LPC_EMAC->RxProduceIndex)
+    {
+        size = (RX_STAT_INFO(Index) & 0x7ff) + 1;
+        if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
+
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            pbuf_take(p, (rt_uint8_t *)RX_BUF(Index), size);
+        }
+
+        /* move Index to the next */
+        if (++Index > LPC_EMAC->RxDescriptorNumber)
+            Index = 0;
+
+        /* set consume index */
+        LPC_EMAC->RxConsumeIndex = Index;
+    }
+    else
+    {
+        /* Enable RxDone interrupt */
+        LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    }
+
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
+
+    return p;
+}
+
+int lpc_emac_hw_init(void)
+{
+    uint32_t result[4];
+
+    rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+
+    /* set autonegotiation mode */
+    lpc_emac_device.phy_mode = EMAC_PHY_AUTO;
+
+    // OUI 00-60-37 NXP Semiconductors
+    lpc_emac_device.dev_addr[0] = 0x00;
+    lpc_emac_device.dev_addr[1] = 0x60;
+    lpc_emac_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    ReadDeviceSerialNum(result);
+    lpc_emac_device.dev_addr[3] = result[0] ^ result[1];
+    lpc_emac_device.dev_addr[4] = result[1] ^ result[2];
+    lpc_emac_device.dev_addr[5] = result[2] ^ result[3];
+
+    lpc_emac_device.parent.parent.init      = lpc_emac_init;
+    lpc_emac_device.parent.parent.open      = lpc_emac_open;
+    lpc_emac_device.parent.parent.close     = lpc_emac_close;
+    lpc_emac_device.parent.parent.read      = lpc_emac_read;
+    lpc_emac_device.parent.parent.write     = lpc_emac_write;
+    lpc_emac_device.parent.parent.control   = lpc_emac_control;
+    lpc_emac_device.parent.parent.user_data = RT_NULL;
+
+    lpc_emac_device.parent.eth_rx           = lpc_emac_rx;
+    lpc_emac_device.parent.eth_tx           = lpc_emac_tx;
+
+    eth_device_init(&(lpc_emac_device.parent), "e0");
+    return 0;
+}
+INIT_DEVICE_EXPORT(lpc_emac_hw_init);
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void emac_dump()
+{
+    rt_kprintf("Command  : %08x\n", LPC_EMAC->Command);
+    rt_kprintf("Status   : %08x\n", LPC_EMAC->Status);
+    rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
+    rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
+    rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
+    rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
+}
+FINSH_FUNCTION_EXPORT(emac_dump, dump emac register);
+#endif
+
diff --git a/bsp/lpc43xx/drivers/drv_emac.h b/bsp/lpc43xx/drivers/drv_emac.h
new file mode 100644
index 0000000000..abadc18520
--- /dev/null
+++ b/bsp/lpc43xx/drivers/drv_emac.h
@@ -0,0 +1,291 @@
+/*
+ * File      : drv_emac.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-19     Bernard      porting from LPC17xx drivers.
+ */
+
+#ifndef __DRV_EMAC_H__
+#define __DRV_EMAC_H__
+
+#include "board.h"
+
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
+#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
+
+#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
+
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF            0x00000012  /* Recommended value                 */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF            0x0000370F  /* Default value                     */
+
+/* PHY Support Register */
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
+#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
+#define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
+
+#define MCFG_CLK_DIV4       0x00000000  /* MDC = hclk / 4                    */
+#define MCFG_CLK_DIV6       0x00000008  /* MDC = hclk / 6                    */
+#define MCFG_CLK_DIV8       0x0000000C  /* MDC = hclk / 8                    */
+#define MCFG_CLK_DIV10      0x00000010  /* MDC = hclk / 10                   */
+#define MCFG_CLK_DIV14      0x00000014  /* MDC = hclk / 14                   */
+#define MCFG_CLK_DIV20      0x00000018  /* MDC = hclk / 20                   */
+#define MCFG_CLK_DIV28      0x0000001C  /* MDC = hclk / 28                   */
+
+
+/* MII Management Command Register */
+#define MCMD_READ           0x00000001  /* MII Read                          */
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
+
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
+
+/* Command Register */
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
+
+/* Status Register */
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
+
+/* Power Down Register */
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
+
+/* RX Status Information Word */
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS         0x10        /* Status Register                   */
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
+
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
+
+#define DP83848C_DEF_ADR    0x0F00      /* Default PHY device address        */
+#define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
+
+int lpc_emac_hw_init(void);
+
+#endif
diff --git a/bsp/lpc43xx/drivers/drv_led.c b/bsp/lpc43xx/drivers/drv_led.c
new file mode 100644
index 0000000000..21b4514fdc
--- /dev/null
+++ b/bsp/lpc43xx/drivers/drv_led.c
@@ -0,0 +1,161 @@
+#include <rtthread.h>
+#include "board.h"
+#include "drv_led.h"
+
+
+/**
+*
+* LED1 <==> GPIO4[12]
+* LED2 <==> GPIO4[13]
+*
+**/
+
+#define LED_NUM    8
+
+#define LED1_PIN   12
+#define LED1_PORT  4
+
+#define LED2_PIN   13
+#define LED2_PORT  4
+
+struct led_ctrl
+{
+    uint8_t num;
+    uint8_t port;
+};
+
+struct lpc_led
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    struct led_ctrl ctrl[LED_NUM];
+};
+
+static struct lpc_led led;
+
+static rt_err_t rt_led_init(rt_device_t dev)
+{
+    /* Enable clock and init GPIO outputs */
+    LPC_CCU1->CLK_M4_GPIO_CFG  = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+    while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
+
+    /* set GPIO4[12] GPIO4[13] as GPIO. */
+    LPC_SCU->SFSP9_0  =  0;                              /* GPIO4[12]          */
+    LPC_SCU->SFSP9_1  =  0;                              /* GPIO4[13]          */
+    /* set GPIO4[12]  GPIO4[13]  output. */
+    LPC_GPIO_PORT->DIR[LED1_PORT] |= 0x01 << LED1_PIN;
+    LPC_GPIO_PORT->DIR[LED2_PORT] |= 0x01 << LED2_PIN;
+    /* turn off all the led */
+    LPC_GPIO_PORT->CLR[LED1_PORT] |= 0x01 << LED1_PIN;
+    LPC_GPIO_PORT->CLR[LED2_PORT] |= 0x01 << LED2_PIN;
+
+    led.ctrl[0].num = LED1_PIN;
+    led.ctrl[0].port = LED1_PORT;
+    led.ctrl[1].num = LED2_PIN;
+    led.ctrl[1].port = LED2_PORT;
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
+                             rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nr = size;
+    rt_uint8_t *value = buffer;
+
+    RT_ASSERT(dev == &led.parent);
+    RT_ASSERT((pos + size) <= LED_NUM);
+
+    for (index = 0; index < nr; index++)
+    {
+        if ((LPC_GPIO_PORT->PIN[led.ctrl[pos + index].port] & (1 << led.ctrl[pos + index].num)) != 0)
+        {
+            *value = 0;
+        }
+        else
+        {
+            *value = 1;
+        }
+        value++;
+    }
+    return index;
+}
+
+static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
+                              const void *buffer, rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nw = size;
+    const rt_uint8_t *value = buffer;
+
+    RT_ASSERT(dev == &led.parent);
+    RT_ASSERT((pos + size) <= LED_NUM);
+
+    for (index = 0; index < nw; index++)
+    {
+        if (*value++)
+        {
+            LPC_GPIO_PORT->CLR[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
+        }
+        else
+        {
+            LPC_GPIO_PORT->SET[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
+        }
+    }
+    return index;
+}
+
+static rt_err_t rt_led_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev == &led.parent);
+
+    if (cmd == LED_DEVICE_CTRL)
+    {
+        rt_uint32_t *led_num = args;
+        *led_num = LED_NUM;
+    }
+    return RT_EOK;
+}
+
+int rt_led_hw_init(void)
+{
+    led.parent.type         = RT_Device_Class_Char;
+    led.parent.rx_indicate  = RT_NULL;
+    led.parent.tx_complete  = RT_NULL;
+    led.parent.init         = rt_led_init;
+    led.parent.open         = rt_led_open;
+    led.parent.close        = rt_led_close;
+    led.parent.read         = rt_led_read;
+    led.parent.write        = rt_led_write;
+    led.parent.control      = rt_led_control;
+    led.parent.user_data    = RT_NULL;
+
+    /* register a character device */
+    rt_device_register(&led.parent, "led", RT_DEVICE_FLAG_RDWR);
+    /* init led device */
+    rt_led_init(&led.parent);
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_led_hw_init);
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led_test(rt_uint32_t led_num, rt_uint32_t value)
+{
+    rt_uint8_t led_value = value;
+    rt_led_write(&led.parent, led_num, &led_value, 1);
+}
+FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 100).)
+#endif
diff --git a/bsp/lpc43xx/drivers/drv_led.h b/bsp/lpc43xx/drivers/drv_led.h
new file mode 100644
index 0000000000..183f8256c2
--- /dev/null
+++ b/bsp/lpc43xx/drivers/drv_led.h
@@ -0,0 +1,12 @@
+#ifndef __DRV_LED_H
+#define __DRV_LED_H
+
+/* Clock Control Unit register bits */
+#define CCU_CLK_CFG_RUN   (1 << 0)
+#define CCU_CLK_CFG_AUTO  (1 << 1)
+#define CCU_CLK_STAT_RUN  (1 << 0)
+
+#define LED_DEVICE_CTRL     0x81        /*LED control command*/
+
+int rt_led_hw_init(void);
+#endif
diff --git a/bsp/lpc43xx/drivers/drv_uart.c b/bsp/lpc43xx/drivers/drv_uart.c
new file mode 100644
index 0000000000..867ee32bd5
--- /dev/null
+++ b/bsp/lpc43xx/drivers/drv_uart.c
@@ -0,0 +1,315 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-18     Bernard      The first version for LPC40xx
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_uart.h"
+
+struct lpc_uart
+{
+    LPC_USARTn_Type  *USART;
+    IRQn_Type USART_IRQn;
+};
+
+static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+//    struct lpc_uart *uart;
+
+
+    RT_ASSERT(serial != RT_NULL);
+    //  uart = (struct lpc_uart *)serial->parent.user_data;
+
+
+
+    // Initialize FIFO for UART0 peripheral
+//    UART_FIFOConfig(uart->USART, &UARTFIFOConfigStruct);
+
+//    UART_TxCmd(uart->USART, ENABLE);
+
+    return RT_EOK;
+}
+
+static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct lpc_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct lpc_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        uart->USART->IER &= ~UART_IER_RBRINT_EN;
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        uart->USART->IER |= UART_IER_RBRINT_EN;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int lpc_putc(struct rt_serial_device *serial, char c)
+{
+    struct lpc_uart *uart;
+
+    uart = (struct lpc_uart *)serial->parent.user_data;
+    while (!(uart->USART->LSR & 0x20));
+    uart->USART->THR = c;
+    return 1;
+}
+
+static int lpc_getc(struct rt_serial_device *serial)
+{
+    struct lpc_uart *uart;
+
+    uart = (struct lpc_uart *)serial->parent.user_data;
+
+    if (uart->USART->LSR & 0x01)
+    {
+        return (uart->USART->RBR);
+    }
+    return -1;
+}
+
+static const struct rt_uart_ops lpc_uart_ops =
+{
+    lpc_configure,
+    lpc_control,
+    lpc_putc,
+    lpc_getc,
+};
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct serial_ringbuffer uart0_int_rx;
+struct lpc_uart uart0 =
+{
+    LPC_USART0,
+    USART0_IRQn,
+};
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+    struct lpc_uart *uart;
+    volatile uint32_t intsrc, temp;
+
+    uart = &uart0;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Determine the interrupt source */
+    intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
+
+    switch (intsrc)
+    {
+
+    case UART_IIR_INTID_RLS:                                            /* Receive Line Status interrupt*/
+        /* read the line status */
+        intsrc = uart->USART->LSR;
+        /* Receive an error data */
+        if (intsrc & UART_LSR_PE)
+        {
+            temp = LPC_USART0->RBR;
+        }
+        break;
+
+    case UART_IIR_INTID_RDA:                                            /*  Receive data               */
+    case UART_IIR_INTID_CTI:                                            /*  Receive data timeout       */
+        /* read the data to buffer  */
+        while (uart->USART->LSR & UART_LSR_RDR)
+        {
+            rt_hw_serial_isr(&serial0);
+        }
+        break;
+
+    default:
+        break;
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#if defined(RT_USING_UART2)
+/* UART2 device driver structure */
+struct serial_ringbuffer uart2_int_rx;
+struct lpc_uart uart2 =
+{
+    LPC_USART2,
+    USART2_IRQn,
+};
+struct rt_serial_device serial2;
+
+void UART2_IRQHandler(void)
+{
+    struct lpc_uart *uart;
+    uint32_t intsrc, temp;
+
+    uart = &uart2;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Determine the interrupt source */
+    intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
+
+    switch (intsrc)
+    {
+
+    case UART_IIR_INTID_RLS:                                            /* Receive Line Status interrupt*/
+        /* read the line status */
+        intsrc = uart->USART->LSR;
+        /* Receive an error data */
+        if (intsrc & UART_LSR_PE)
+        {
+            temp = LPC_USART0->RBR;
+        }
+        break;
+
+    case UART_IIR_INTID_RDA:                                            /*  Receive data               */
+    case UART_IIR_INTID_CTI:                                            /*  Receive data timeout       */
+        /* read the data to buffer  */
+        while (uart->USART->LSR & UART_LSR_RDR)
+        {
+            rt_hw_serial_isr(&serial0);
+        }
+        break;
+
+    default:
+        break;
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+void rt_hw_uart_init(void)
+{
+    struct lpc_uart *uart;
+    struct serial_configure config;
+
+#ifdef RT_USING_UART0
+    uart = &uart0;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    serial0.ops    = &lpc_uart_ops;
+    serial0.int_rx = &uart0_int_rx;
+    serial0.config = config;
+
+    /* Enable GPIO register interface clock                                     */
+    LPC_CCU1->CLK_M4_GPIO_CFG     |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_GPIO_STAT  & 0x01));
+
+    /* Enable USART1 peripheral clock                                           */
+    LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
+    while (!(LPC_CCU2->CLK_APB0_USART0_STAT & 0x01));
+
+    /* Enable USART1 register interface clock                                   */
+    LPC_CCU1->CLK_M4_USART0_CFG   |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_USART0_STAT & 0x01));
+
+    /* Init GPIO pins                                                           */
+    LPC_SCU->SFSP2_0 = (1 << 6) |         /* Input buffer enabled               */
+                       (1 << 4) |        /* Pull-up disabled                   */
+                       (1 << 0) ;        /* Pin P2_0 used as U0_TXD            */
+
+    LPC_SCU->SFSP2_1 = (1 << 6) |         /* Input buffer enabled               */
+                       (1 << 4) |        /* Pull-up disabled                   */
+                       (1 << 0) ;        /* Pin P2_1 used as U0_RXD            */
+
+    /* Init USART0                                                              */
+    LPC_USART0->LCR    = 0x83;            /* 8 bits, no Parity, 1 Stop bit      */
+    LPC_USART0->DLL    = 0x06;            /* 115200 Baudrate @ 12 MHz IRC       */
+    LPC_USART0->DLM    = 0x00;
+    LPC_USART0->FDR    = 0xC1;
+    LPC_USART0->LCR    = 0x03;            /* DLAB = 0                           */
+    /* enable the receive interrupt */
+    LPC_USART0->IER |= UART_IER_RBRINT_EN;
+    /* preemption = 1, sub-priority = 1 */
+    NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
+
+    /* Enable Interrupt for UART channel */
+    NVIC_EnableIRQ(uart->USART_IRQn);
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          uart);
+#endif
+#ifdef RT_USING_UART2
+    uart = &uart2;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    serial2.ops    = &lpc_uart_ops;
+    serial2.int_rx = &uart2_int_rx;
+    serial2.config = config;
+
+    /* Enable GPIO register interface clock                                     */
+    LPC_CCU1->CLK_M4_GPIO_CFG     |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_GPIO_STAT  & 0x01));
+
+    /* Enable USART1 peripheral clock                                           */
+    LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
+    while (!(LPC_CCU2->CLK_APB2_USART2_STAT & 0x01));
+
+    /* Enable USART2 register interface clock                                   */
+    LPC_CCU1->CLK_M4_USART0_CFG   |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_USART2_STAT & 0x01));
+
+    /* Init GPIO pins                                                           */
+    LPC_SCU->SFSP1_15 = (1 << 6) |         /* Input buffer enabled               */
+                        (1 << 4) |        /* Pull-up disabled                   */
+                        (1 << 0) ;        /* Pin P1_15 used as U2_TXD            */
+
+    LPC_SCU->SFSP1_16 = (1 << 6) |         /* Input buffer enabled               */
+                        (1 << 4) |        /* Pull-up disabled                   */
+                        (1 << 0) ;        /* Pin P1_16 used as U2_RXD            */
+
+    /* Init USART2                                                              */
+    LPC_USART2->LCR    = 0x83;            /* 8 bits, no Parity, 1 Stop bit      */
+    LPC_USART2->DLL    = 0x06;            /* 115200 Baudrate @ 12 MHz IRC       */
+    LPC_USART2->DLM    = 0x00;
+    LPC_USART2->FDR    = 0xC1;
+    LPC_USART2->LCR    = 0x03;            /* DLAB = 0                           */
+    /* enable the receive interrupt */
+    LPC_USART2->IER |= UART_IER_RBRINT_EN;
+    /* preemption = 1, sub-priority = 1 */
+    NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
+
+    /* Enable Interrupt for UART channel */
+    NVIC_EnableIRQ(uart->USART_IRQn);
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          uart);
+#endif
+}
diff --git a/bsp/lpc43xx/drivers/drv_uart.h b/bsp/lpc43xx/drivers/drv_uart.h
new file mode 100644
index 0000000000..69596c6b98
--- /dev/null
+++ b/bsp/lpc43xx/drivers/drv_uart.h
@@ -0,0 +1,228 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR    (3)         /*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+#define UART_RBR_MASKBIT    ((uint8_t)0xFF)         /*!< UART Received Buffer mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+#define UART_THR_MASKBIT    ((uint8_t)0xFF)         /*!< UART Transmit Holding mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+#define UART_LOAD_DLL(div)  ((div) & 0xFF)  /**< Macro for loading least significant halfs of divisors */
+#define UART_DLL_MASKBIT    ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+#define UART_DLM_MASKBIT    ((uint8_t)0xFF)         /*!< Divisor latch MSB bit mask */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)   /**< Macro for loading most significant halfs of divisors */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+#define UART_IER_RBRINT_EN      ((uint32_t)(1<<0))  /*!< RBR Interrupt enable*/
+#define UART_IER_THREINT_EN     ((uint32_t)(1<<1))  /*!< THR Interrupt enable*/
+#define UART_IER_RLSINT_EN      ((uint32_t)(1<<2))  /*!< RX line status interrupt enable*/
+#define UART1_IER_MSINT_EN      ((uint32_t)(1<<3))  /*!< Modem status interrupt enable */
+#define UART1_IER_CTSINT_EN     ((uint32_t)(1<<7))  /*!< CTS1 signal transition interrupt enable */
+#define UART_IER_ABEOINT_EN     ((uint32_t)(1<<8))  /*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT_EN     ((uint32_t)(1<<9))  /*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK        ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
+#define UART1_IER_BITMASK       ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+#define UART_IIR_INTSTAT_PEND   ((uint32_t)(1<<0))  /*!<Interrupt Status - Active low */
+#define UART_IIR_INTID_RLS      ((uint32_t)(3<<1))  /*!<Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RDA      ((uint32_t)(2<<1))  /*!<Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_CTI      ((uint32_t)(6<<1))  /*!<Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_THRE     ((uint32_t)(1<<1))  /*!<Interrupt identification: THRE interrupt*/
+#define UART1_IIR_INTID_MODEM   ((uint32_t)(0<<1))  /*!<Interrupt identification: Modem interrupt*/
+#define UART_IIR_INTID_MASK     ((uint32_t)(7<<1))  /*!<Interrupt identification: Interrupt ID mask */
+#define UART_IIR_FIFO_EN        ((uint32_t)(3<<6))  /*!<These bits are equivalent to UnFCR[0] */
+#define UART_IIR_ABEO_INT       ((uint32_t)(1<<8))  /*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT       ((uint32_t)(1<<9))  /*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK        ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+#define UART_FCR_FIFO_EN        ((uint8_t)(1<<0))   /*!< UART FIFO enable */
+#define UART_FCR_RX_RS          ((uint8_t)(1<<1))   /*!< UART FIFO RX reset */
+#define UART_FCR_TX_RS          ((uint8_t)(1<<2))   /*!< UART FIFO TX reset */
+#define UART_FCR_DMAMODE_SEL    ((uint8_t)(1<<3))   /*!< UART DMA mode selection */
+#define UART_FCR_TRG_LEV0       ((uint8_t)(0))      /*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1       ((uint8_t)(1<<6))   /*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2       ((uint8_t)(2<<6))   /*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3       ((uint8_t)(3<<6))   /*!< UART FIFO trigger level 3: 14 character */
+#define UART_FCR_BITMASK        ((uint8_t)(0xCF))   /*!< UART FIFO control bit mask */
+#define UART_TX_FIFO_SIZE       (16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+#define UART_LCR_WLEN5          ((uint8_t)(0))          /*!< UART 5 bit data mode */
+#define UART_LCR_WLEN6          ((uint8_t)(1<<0))       /*!< UART 6 bit data mode */
+#define UART_LCR_WLEN7          ((uint8_t)(2<<0))       /*!< UART 7 bit data mode */
+#define UART_LCR_WLEN8          ((uint8_t)(3<<0))       /*!< UART 8 bit data mode */
+#define UART_LCR_STOPBIT_SEL    ((uint8_t)(1<<2))       /*!< UART Two Stop Bits Select */
+#define UART_LCR_PARITY_EN      ((uint8_t)(1<<3))       /*!< UART Parity Enable */
+#define UART_LCR_PARITY_ODD     ((uint8_t)(0))          /*!< UART Odd Parity Select */
+#define UART_LCR_PARITY_EVEN    ((uint8_t)(1<<4))       /*!< UART Even Parity Select */
+#define UART_LCR_PARITY_F_1     ((uint8_t)(2<<4))       /*!< UART force 1 stick parity */
+#define UART_LCR_PARITY_F_0     ((uint8_t)(3<<4))       /*!< UART force 0 stick parity */
+#define UART_LCR_BREAK_EN       ((uint8_t)(1<<6))       /*!< UART Transmission Break enable */
+#define UART_LCR_DLAB_EN        ((uint8_t)(1<<7))       /*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK        ((uint8_t)(0xFF))       /*!< UART line control bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+#define UART1_MCR_DTR_CTRL      ((uint8_t)(1<<0))       /*!< Source for modem output pin DTR */
+#define UART1_MCR_RTS_CTRL      ((uint8_t)(1<<1))       /*!< Source for modem output pin RTS */
+#define UART1_MCR_LOOPB_EN      ((uint8_t)(1<<4))       /*!< Loop back mode select */
+#define UART1_MCR_AUTO_RTS_EN   ((uint8_t)(1<<6))       /*!< Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN   ((uint8_t)(1<<7))       /*!< Enable Auto CTS flow-control */
+#define UART1_MCR_BITMASK       ((uint8_t)(0x0F3))      /*!< UART1 bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+#define UART_LSR_RDR        ((uint8_t)(1<<0))   /*!<Line status register: Receive data ready*/
+#define UART_LSR_OE         ((uint8_t)(1<<1))   /*!<Line status register: Overrun error*/
+#define UART_LSR_PE         ((uint8_t)(1<<2))   /*!<Line status register: Parity error*/
+#define UART_LSR_FE         ((uint8_t)(1<<3))   /*!<Line status register: Framing error*/
+#define UART_LSR_BI         ((uint8_t)(1<<4))   /*!<Line status register: Break interrupt*/
+#define UART_LSR_THRE       ((uint8_t)(1<<5))   /*!<Line status register: Transmit holding register empty*/
+#define UART_LSR_TEMT       ((uint8_t)(1<<6))   /*!<Line status register: Transmitter empty*/
+#define UART_LSR_RXFE       ((uint8_t)(1<<7))   /*!<Error in RX FIFO*/
+#define UART_LSR_BITMASK    ((uint8_t)(0xFF))   /*!<UART Line status bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+#define UART1_MSR_DELTA_CTS     ((uint8_t)(1<<0))   /*!< Set upon state change of input CTS */
+#define UART1_MSR_DELTA_DSR     ((uint8_t)(1<<1))   /*!< Set upon state change of input DSR */
+#define UART1_MSR_LO2HI_RI      ((uint8_t)(1<<2))   /*!< Set upon low to high transition of input RI */
+#define UART1_MSR_DELTA_DCD     ((uint8_t)(1<<3))   /*!< Set upon state change of input DCD */
+#define UART1_MSR_CTS           ((uint8_t)(1<<4))   /*!< Clear To Send State */
+#define UART1_MSR_DSR           ((uint8_t)(1<<5))   /*!< Data Set Ready State */
+#define UART1_MSR_RI            ((uint8_t)(1<<6))   /*!< Ring Indicator State */
+#define UART1_MSR_DCD           ((uint8_t)(1<<7))   /*!< Data Carrier Detect State */
+#define UART1_MSR_BITMASK       ((uint8_t)(0xFF))   /*!< MSR register bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+#define UART_SCR_BIMASK     ((uint8_t)(0xFF))   /*!< UART Scratch Pad bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+#define UART_ACR_START              ((uint32_t)(1<<0))  /**< UART Auto-baud start */
+#define UART_ACR_MODE               ((uint32_t)(1<<1))  /**< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART       ((uint32_t)(1<<2))  /**< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR        ((uint32_t)(1<<8))  /**< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR        ((uint32_t)(1<<9))  /**< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK            ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+#define UART_ICR_IRDAEN         ((uint32_t)(1<<0))          /**< IrDA mode enable */
+#define UART_ICR_IRDAINV        ((uint32_t)(1<<1))          /**< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN    ((uint32_t)(1<<2))          /**< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n)    ((uint32_t)((n&0x07)<<3))   /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK        ((uint32_t)(0x3F))          /*!< UART IRDA bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART half duplex register
+ **********************************************************************/
+#define UART_HDEN_HDEN          ((uint32_t)(1<<0))          /**< enable half-duplex mode*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART smart card interface control register
+ **********************************************************************/
+#define UART_SCICTRL_SCIEN      ((uint32_t)(1<<0))          /**< enable asynchronous half-duplex smart card interface*/
+#define UART_SCICTRL_NACKDIS    ((uint32_t)(1<<1))          /**< NACK response is inhibited*/
+#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2))          /**< ISO7816-3 protocol T1 is selected*/
+#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5))   /**< number of retransmission*/
+#define UART_SCICTRL_GUARDTIME(n)   ((uint32_t)((n&0xFF)<<8))   /**< Extra guard time*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART synchronous control register
+ **********************************************************************/
+#define UART_SYNCCTRL_SYNC      ((uint32_t)(1<<0))          /**< enable synchronous mode*/
+#define UART_SYNCCTRL_CSRC_MASTER   ((uint32_t)(1<<1))      /**< synchronous master mode*/
+#define UART_SYNCCTRL_FES       ((uint32_t)(1<<2))          /**< sample on falling edge*/
+#define UART_SYNCCTRL_TSBYPASS  ((uint32_t)(1<<3))          /**< to be defined*/
+#define UART_SYNCCTRL_CSCEN     ((uint32_t)(1<<4))          /**< continuous running clock enable (master mode only)*/
+#define UART_SYNCCTRL_STARTSTOPDISABLE  ((uint32_t)(1<<5))  /**< do not send start/stop bit*/
+#define UART_SYNCCTRL_CCCLR     ((uint32_t)(1<<6))          /**< stop continuous clock*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+#define UART_FDR_DIVADDVAL(n)   ((uint32_t)(n&0x0F))        /**< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n)      ((uint32_t)((n<<4)&0xF0))   /**< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK        ((uint32_t)(0xFF))          /**< UART Fractional Divider register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+#define UART1_TER_TXEN          ((uint8_t)(1<<7))       /*!< Transmit enable bit */
+#define UART1_TER_BITMASK       ((uint8_t)(0x80))       /**< UART Transmit Enable Register bit mask */
+#define UART0_2_3_TER_TXEN      ((uint8_t)(1<<0))       /*!< Transmit enable bit */
+#define UART0_2_3_TER_BITMASK   ((uint8_t)(0x01))       /**< UART Transmit Enable Register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+#define UART_RS485CTRL_NMM_EN       ((uint32_t)(1<<0))  /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
+is disabled */
+#define UART_RS485CTRL_RX_DIS       ((uint32_t)(1<<1))  /*!< The receiver is disabled */
+#define UART_RS485CTRL_AADEN        ((uint32_t)(1<<2))  /*!< Auto Address Detect (AAD) is enabled */
+#define UART_RS485CTRL_SEL_DTR      ((uint32_t)(1<<3))  /*!< If direction control is enabled
+(bit DCTRL = 1), pin DTR is used for direction control */
+#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))  /*!< Enable Auto Direction Control */
+#define UART_RS485CTRL_OINV_1       ((uint32_t)(1<<5))  /*!< This bit reverses the polarity of the direction
+control signal on the RTS (or DTR) pin. The direction control pin
+    will be driven to logic "1" when the transmitter has data to be sent */
+#define UART_RS485CTRL_BITMASK      ((uint32_t)(0x3F))  /**< RS485 control bit-mask value */
+
+    /*********************************************************************//**
+     * Macro defines for Macro defines for UART1 RS-485 Address Match register
+     **********************************************************************/
+#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF))    /**< Bit mask value */
+
+    /*********************************************************************//**
+     * Macro defines for Macro defines for UART1 RS-485 Delay value register
+     **********************************************************************/
+    /* Macro defines for UART1 RS-485 Delay value register */
+#define UART_RS485DLY_BITMASK       ((uint8_t)(0xFF))   /** Bit mask value */
+
+    /*********************************************************************//**
+     * Macro defines for Macro defines for UART FIFO Level register
+     **********************************************************************/
+#define UART_FIFOLVL_RXFIFOLVL(n)   ((uint32_t)(n&0x0F))        /**< Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n)   ((uint32_t)((n>>8)&0x0F))   /**< Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_BITMASK        ((uint32_t)(0x0F0F))        /**< UART FIFO Level Register bit mask */
+
+
+
+    void rt_hw_uart_init(void);
+
+#endif

From 5995b7a2a15240386b0c63babd917f14d8936378 Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@gmail.com>
Date: Sun, 13 Jul 2014 15:17:26 +0800
Subject: [PATCH 40/86] update the xplorer4330 bsp.

---
 .../CMSIS/Include/arm_common_tables.h         |    93 +
 .../Libraries/CMSIS/Include/arm_math.h        |  7306 ++++
 .../Libraries/CMSIS/Include/core_cm0.h        |   682 +
 .../Libraries/CMSIS/Include/core_cm0plus.h    |   793 +
 .../Libraries/CMSIS/Include/core_cm3.h        |  1627 +
 .../Libraries/CMSIS/Include/core_cm4.h        |  1772 +
 .../Libraries/CMSIS/Include/core_cm4_simd.h   |   673 +
 .../Libraries/CMSIS/Include/core_cmFunc.h     |   636 +
 .../Libraries/CMSIS/Include/core_cmInstr.h    |   688 +
 .../Libraries/CMSIS/Include/core_sc000.h      |   813 +
 .../Libraries/CMSIS/Include/core_sc300.h      |  1598 +
 .../Device/NXP/LPC43xx/Include/LPC43xx.h      | 34895 ++++++++++++++++
 .../Device/NXP/LPC43xx/Include/fpu_enable.h   |    33 +
 .../Device/NXP/LPC43xx/Include/fpu_init.h     |    29 +
 .../NXP/LPC43xx/Include/system_LPC43xx.h      |    50 +
 .../Source/Templates/ARM/startup_LPC43xx.s    |   339 +
 .../Source/Templates/ARM/startup_LPC43xx_M0.s |   255 +
 .../Source/Templates/GCC/cr_startup_lpc43xx.c |   502 +
 .../Templates/GCC/cr_startup_lpc43xx_m0sub.c  |   463 +
 .../Source/Templates/IAR/startup_LPC43xx.s    |   431 +
 .../Templates/IAR/startup_lpc43xx_m0sub.s     |   242 +
 .../LPC43xx/Source/Templates/system_LPC43xx.c |   892 +
 bsp/xplorer4330/Libraries/Device/SConscript   |    30 +
 bsp/xplorer4330/M0/SConscript                 |    13 +
 bsp/xplorer4330/M0/SConstruct                 |    29 +
 bsp/xplorer4330/M0/rtconfig.h                 |   230 +
 bsp/xplorer4330/M0/rtconfig.py                |   139 +
 bsp/xplorer4330/M0/template.uvproj            |   777 +
 bsp/xplorer4330/applications/SConscript       |     6 +-
 bsp/xplorer4330/applications/application.c    |    94 +-
 bsp/xplorer4330/applications/startup.c        |    56 +-
 bsp/xplorer4330/drivers/SConscript            |     8 +-
 bsp/xplorer4330/drivers/board.c               |    77 +
 bsp/xplorer4330/drivers/board.h               |    60 +
 bsp/xplorer4330/drivers/drv_led.c             |   162 +
 bsp/xplorer4330/drivers/drv_led.h             |    12 +
 bsp/xplorer4330/drivers/drv_uart.c            |   315 +
 bsp/xplorer4330/drivers/drv_uart.h            |   228 +
 bsp/xplorer4330/drivers/platform.c            |    64 -
 bsp/xplorer4330/drivers/platform.h            |    19 -
 bsp/xplorer4330/drivers/usart.c               |   394 -
 bsp/xplorer4330/drivers/usart.h               |    39 -
 bsp/xplorer4330/libraries/SConscript          |     5 +-
 .../libraries/lpc_board/SConscript            |    44 -
 .../lpc_board/board_common/board_api.h        |   176 -
 .../lpc_board/board_common/lpc_phy.h          |    90 -
 .../lpc_board/board_common/lpc_phy_dp83848.c  |   281 -
 .../lpc_board/board_common/lpc_phy_smsc87x0.c |   270 -
 .../lpc_board/board_common/retarget.c         |   253 -
 .../boards_18xx_43xx/boards_18xx43xx.dox      |    62 -
 .../hitex_eva_18504350/board.h                |    37 -
 .../board_hitex_eva_18504350.c                |   898 -
 .../board_hitex_eva_18504350.h                |   244 -
 .../hitex_eva_1850/sys_config.h               |    58 -
 .../hitex_eva_4350/sys_config.h               |    58 -
 .../sysinit_hitex_eva_18504350.c              |   455 -
 .../keil_mcb_18574357/board.h                 |    37 -
 .../board_keil_mcb_18574357.c                 |   841 -
 .../board_keil_mcb_18574357.h                 |   304 -
 .../keil_mcb_1857/sys_config.h                |    58 -
 .../keil_mcb_4357/sys_config.h                |    58 -
 .../sysinit_keil_mcb_18574357.c               |   433 -
 .../ngx_xplorer_18304330/board.h              |    37 -
 .../board_ngx_xplorer_18304330.c              |   385 -
 .../board_ngx_xplorer_18304330.h              |   232 -
 .../ngx_xplorer_1830/sys_config.h             |    58 -
 .../ngx_xplorer_4330/sys_config.h             |    58 -
 .../sysinit_ngx_xplorer_18304330.c            |   239 -
 bsp/xplorer4330/libraries/lpc_chip/SConscript |    15 -
 .../lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c   |   136 -
 .../lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h   |   240 -
 .../chip_18xx_43xx/atimer_18xx_43xx.c         |    55 -
 .../chip_18xx_43xx/atimer_18xx_43xx.h         |   117 -
 .../chip_18xx_43xx/cguccu_18xx_43xx.h         |   104 -
 .../libraries/lpc_chip/chip_18xx_43xx/chip.h  |    44 -
 .../lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox |    51 -
 .../lpc_chip/chip_18xx_43xx/chip_clocks.h     |   252 -
 .../lpc_chip/chip_18xx_43xx/chip_lpc18xx.h    |   240 -
 .../lpc_chip/chip_18xx_43xx/chip_lpc43xx.h    |   248 -
 .../lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c |   576 -
 .../lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h |   238 -
 .../libraries/lpc_chip/chip_18xx_43xx/cmsis.h |   355 -
 .../lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h  |   181 -
 .../lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c   |    89 -
 .../lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h   |   156 -
 .../lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c  |    82 -
 .../lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h  |   230 -
 .../lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c  |   111 -
 .../lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h  |   173 -
 .../lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c |   424 -
 .../lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h |   167 -
 .../lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c  |    53 -
 .../lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h  |   308 -
 .../lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c   |   313 -
 .../lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h   |   229 -
 .../lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c   |   138 -
 .../lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h   |   221 -
 .../lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c   |   118 -
 .../lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h   |   216 -
 .../lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c   |    92 -
 .../lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h   |   151 -
 .../chip_18xx_43xx/ritimer_18xx_43xx.c        |    67 -
 .../chip_18xx_43xx/ritimer_18xx_43xx.h        |   146 -
 .../lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c   |    57 -
 .../lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h   |   281 -
 .../lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c   |    80 -
 .../lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h   |   171 -
 .../lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c |   597 -
 .../lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h |   480 -
 .../lpc_chip/chip_18xx_43xx/spifi_rom_api.h   |   356 -
 .../lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c   |   434 -
 .../lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h   |   311 -
 .../lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h |   371 -
 .../lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c  |   353 -
 .../lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h  |   288 -
 .../lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c  |    70 -
 .../lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h  |   191 -
 .../lpc_chip/chip_common/mem_tests.c          |   294 -
 .../lpc_chip/chip_common/mem_tests.h          |   116 -
 .../lpc_chip/chip_common/ring_buffer.c        |   168 -
 .../lpc_chip/chip_common/ring_buffer.h        |   143 -
 bsp/xplorer4330/libraries/lpc_ip/SConscript   |     9 -
 bsp/xplorer4330/libraries/lpc_ip/adc_001.c    |   170 -
 bsp/xplorer4330/libraries/lpc_ip/adc_001.h    |   182 -
 bsp/xplorer4330/libraries/lpc_ip/atimer_001.c |    55 -
 bsp/xplorer4330/libraries/lpc_ip/atimer_001.h |   160 -
 bsp/xplorer4330/libraries/lpc_ip/ccan_001.h   |   114 -
 bsp/xplorer4330/libraries/lpc_ip/dac_001.h    |    64 -
 bsp/xplorer4330/libraries/lpc_ip/emc_001.c    |   274 -
 bsp/xplorer4330/libraries/lpc_ip/emc_001.h    |   357 -
 bsp/xplorer4330/libraries/lpc_ip/enet_001.c   |   204 -
 bsp/xplorer4330/libraries/lpc_ip/enet_001.h   |   608 -
 bsp/xplorer4330/libraries/lpc_ip/fpu_init.c   |    94 -
 bsp/xplorer4330/libraries/lpc_ip/fpu_init.h   |    56 -
 bsp/xplorer4330/libraries/lpc_ip/gima_001.h   |    70 -
 bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c  |   216 -
 bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h  |   258 -
 bsp/xplorer4330/libraries/lpc_ip/gpio_001.h   |   151 -
 .../libraries/lpc_ip/gpiogrpint_001.c         |    70 -
 .../libraries/lpc_ip/gpiogrpint_001.h         |   120 -
 .../libraries/lpc_ip/gpioint_001.c            |   111 -
 .../libraries/lpc_ip/gpioint_001.h            |   110 -
 .../libraries/lpc_ip/gpiopinint_001.c         |    71 -
 .../libraries/lpc_ip/gpiopinint_001.h         |   115 -
 bsp/xplorer4330/libraries/lpc_ip/i2c_001.c    |   786 -
 bsp/xplorer4330/libraries/lpc_ip/i2c_001.h    |   412 -
 bsp/xplorer4330/libraries/lpc_ip/i2s_001.c    |   327 -
 bsp/xplorer4330/libraries/lpc_ip/i2s_001.h    |   485 -
 bsp/xplorer4330/libraries/lpc_ip/lcd_001.c    |   214 -
 bsp/xplorer4330/libraries/lpc_ip/lcd_001.h    |   310 -
 bsp/xplorer4330/libraries/lpc_ip/lpc_types.h  |   216 -
 bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h  |    84 -
 bsp/xplorer4330/libraries/lpc_ip/pmc_001.h    |    65 -
 bsp/xplorer4330/libraries/lpc_ip/qei_001.h    |    90 -
 .../libraries/lpc_ip/regfile_001.h            |    94 -
 .../libraries/lpc_ip/ritimer_001.c            |   100 -
 .../libraries/lpc_ip/ritimer_001.h            |   151 -
 bsp/xplorer4330/libraries/lpc_ip/rtc_001.c    |   217 -
 bsp/xplorer4330/libraries/lpc_ip/rtc_001.h    |   405 -
 bsp/xplorer4330/libraries/lpc_ip/sct_001.h    |   171 -
 bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c  |   300 -
 bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h  |   408 -
 bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h  |   107 -
 bsp/xplorer4330/libraries/lpc_ip/spi_001.h    |    67 -
 bsp/xplorer4330/libraries/lpc_ip/spifi_001.h  |   226 -
 bsp/xplorer4330/libraries/lpc_ip/ssp_001.c    |   163 -
 bsp/xplorer4330/libraries/lpc_ip/ssp_001.h    |   351 -
 bsp/xplorer4330/libraries/lpc_ip/timer_001.c  |    83 -
 bsp/xplorer4330/libraries/lpc_ip/timer_001.h  |   426 -
 bsp/xplorer4330/libraries/lpc_ip/usart_001.c  |   516 -
 bsp/xplorer4330/libraries/lpc_ip/usart_001.h  |   675 -
 bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h  |   128 -
 bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h   |    75 -
 .../libraries/startup_code/SConscript         |    22 -
 .../startup_code/gcc_startup_lpc18xx43xx.s    |   300 -
 .../startup_code/keil_startup_lpc18xx43xx.s   |   327 -
 bsp/xplorer4330/m4/Internal SRAM.ini          |    10 -
 bsp/xplorer4330/m4/SConscript                 |     2 +-
 bsp/xplorer4330/m4/SConstruct                 |    19 +-
 bsp/xplorer4330/m4/SPIFI 32MB Debug.ini       |    10 -
 .../m4/lpc4330_xplorer_spifi32mb.ld           |   139 -
 .../m4/lpc4330_xplorer_spifi32mb.sct          |    15 -
 bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct   |    15 -
 bsp/xplorer4330/m4/project.uvopt              |  1402 +-
 bsp/xplorer4330/m4/project.uvproj             |   966 +-
 bsp/xplorer4330/m4/rtconfig.h                 |   138 +-
 bsp/xplorer4330/m4/rtconfig.py                |    83 +-
 bsp/xplorer4330/m4/template.uvproj            |   416 +-
 188 files changed, 58683 insertions(+), 30804 deletions(-)
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/arm_common_tables.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/arm_math.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0plus.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cm3.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4_simd.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cmFunc.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_cmInstr.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_sc000.h
 create mode 100644 bsp/xplorer4330/Libraries/CMSIS/Include/core_sc300.h
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
 create mode 100644 bsp/xplorer4330/Libraries/Device/SConscript
 create mode 100644 bsp/xplorer4330/M0/SConscript
 create mode 100644 bsp/xplorer4330/M0/SConstruct
 create mode 100644 bsp/xplorer4330/M0/rtconfig.h
 create mode 100644 bsp/xplorer4330/M0/rtconfig.py
 create mode 100644 bsp/xplorer4330/M0/template.uvproj
 create mode 100644 bsp/xplorer4330/drivers/board.c
 create mode 100644 bsp/xplorer4330/drivers/board.h
 create mode 100644 bsp/xplorer4330/drivers/drv_led.c
 create mode 100644 bsp/xplorer4330/drivers/drv_led.h
 create mode 100644 bsp/xplorer4330/drivers/drv_uart.c
 create mode 100644 bsp/xplorer4330/drivers/drv_uart.h
 delete mode 100644 bsp/xplorer4330/drivers/platform.c
 delete mode 100644 bsp/xplorer4330/drivers/platform.h
 delete mode 100644 bsp/xplorer4330/drivers/usart.c
 delete mode 100644 bsp/xplorer4330/drivers/usart.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/SConscript
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/board_common/retarget.c
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h
 delete mode 100644 bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c
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diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/xplorer4330/Libraries/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..7a59b5923e
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/arm_math.h b/bsp/xplorer4330/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..65304c127d
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("push")         \
+     _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT \
+     _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..ab31de0ee8
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..5cea74e9af
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm3.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..122c9aa4a8
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..d65016c714
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000..83db95b5f1
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000..0a18fafc30
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000..d213f0eed7
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_sc000.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..1a2a0f2e30
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_sc000.h
@@ -0,0 +1,813 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_sc300.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..cc34d6fc0e
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1598 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
new file mode 100644
index 0000000000..88872efab2
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
@@ -0,0 +1,34895 @@
+
+/****************************************************************************************************//**
+ * @file     LPC43xx.h
+ *
+ * @status   RELEASE
+ *
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
+ *           default LPC43xx Device Series
+ *
+ * @version  V5
+ * @date     9. December 2011
+ *
+ * @note     Generated with SVDConv V2.6 Build 6c  on Friday, 09.12.2011 13:56:08
+ *
+ *           from CMSIS SVD File 'LPC43xxv5.xml' Version 5,
+ *           created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+  * @{
+  */
+
+/** @addtogroup LPC43xx
+  * @{
+  */
+
+#ifndef __LPC43XX_H__
+#define __LPC43XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+
+
+/********************************************
+** Start of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma push
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// -------------------------  Cortex-M4 Processor Exceptions Numbers  -----------------------------
+  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
+  MemoryManagement_IRQn             = -12,  /*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+  BusFault_IRQn                     = -11,  /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn                   = -10,  /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  SVCall_IRQn                       =  -5,  /*!<  11  System Service Call via SVC instruction */
+  DebugMonitor_IRQn                 =  -4,  /*!<  12  Debug Monitor                    */
+  PendSV_IRQn                       =  -2,  /*!<  14  Pendable request for system service */
+  SysTick_IRQn                      =  -1,  /*!<  15  System Tick Timer                */
+// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
+  DAC_IRQn                          =   0,  /*!<   0  DAC                              */
+  M0CORE_IRQn                  		=   1,  /*!<   1  M0a                              */
+  DMA_IRQn                          =   2,  /*!<   2  DMA                              */
+  RESERVED1_IRQn                    =   3,  /*!<   3  EZH/EDM                          */
+  RESERVED2_IRQn                    =   4,
+  ETHERNET_IRQn                     =   5,  /*!<   5  ETHERNET                         */
+  SDIO_IRQn                         =   6,  /*!<   6  SDIO                             */
+  LCD_IRQn                          =   7,  /*!<   7  LCD                              */
+  USB0_IRQn                         =   8,  /*!<   8  USB0                             */
+  USB1_IRQn                         =   9,  /*!<   9  USB1                             */
+  SCT_IRQn                          =  10,  /*!<  10  SCT                              */
+  RITIMER_IRQn                      =  11,  /*!<  11  RITIMER                          */
+  TIMER0_IRQn                       =  12,  /*!<  12  TIMER0                           */
+  TIMER1_IRQn                       =  13,  /*!<  13  TIMER1                           */
+  TIMER2_IRQn                       =  14,  /*!<  14  TIMER2                           */
+  TIMER3_IRQn                       =  15,  /*!<  15  TIMER3                           */
+  MCPWM_IRQn                        =  16,  /*!<  16  MCPWM                            */
+  ADC0_IRQn                         =  17,  /*!<  17  ADC0                             */
+  I2C0_IRQn                         =  18,  /*!<  18  I2C0                             */
+  I2C1_IRQn                         =  19,  /*!<  19  I2C1                             */
+  SPI_INT_IRQn                      =  20,  /*!<  20  SPI_INT                          */
+  ADC1_IRQn                         =  21,  /*!<  21  ADC1                             */
+  SSP0_IRQn                         =  22,  /*!<  22  SSP0                             */
+  SSP1_IRQn                         =  23,  /*!<  23  SSP1                             */
+  USART0_IRQn                       =  24,  /*!<  24  USART0                           */
+  UART1_IRQn                        =  25,  /*!<  25  UART1                            */
+  USART2_IRQn                       =  26,  /*!<  26  USART2                           */
+  USART3_IRQn                       =  27,  /*!<  27  USART3                           */
+  I2S0_IRQn                         =  28,  /*!<  28  I2S0                             */
+  I2S1_IRQn                         =  29,  /*!<  29  I2S1                             */
+  RESERVED4_IRQn                    =  30,
+  SGPIO_IINT_IRQn                   =  31,  /*!<  31  SGPIO_IINT                       */
+  PIN_INT0_IRQn                     =  32,  /*!<  32  PIN_INT0                         */
+  PIN_INT1_IRQn                     =  33,  /*!<  33  PIN_INT1                         */
+  PIN_INT2_IRQn                     =  34,  /*!<  34  PIN_INT2                         */
+  PIN_INT3_IRQn                     =  35,  /*!<  35  PIN_INT3                         */
+  PIN_INT4_IRQn                     =  36,  /*!<  36  PIN_INT4                         */
+  PIN_INT5_IRQn                     =  37,  /*!<  37  PIN_INT5                         */
+  PIN_INT6_IRQn                     =  38,  /*!<  38  PIN_INT6                         */
+  PIN_INT7_IRQn                     =  39,  /*!<  39  PIN_INT7                         */
+  GINT0_IRQn                        =  40,  /*!<  40  GINT0                            */
+  GINT1_IRQn                        =  41,  /*!<  41  GINT1                            */
+  EVENTROUTER_IRQn                  =  42,  /*!<  42  EVENTROUTER                      */
+  C_CAN1_IRQn                       =  43,  /*!<  43  C_CAN1                           */
+  RESERVED6_IRQn                    =  44,
+  RESERVED7_IRQn                    =  45,  /*!<  45  VADC                             */
+  ATIMER_IRQn                       =  46,  /*!<  46  ATIMER                           */
+  RTC_IRQn                          =  47,  /*!<  47  RTC                              */
+  RESERVED8_IRQn                    =  48,
+  WWDT_IRQn                         =  49,  /*!<  49  WWDT                             */
+  RESERVED9_IRQn                    =  50,
+  C_CAN0_IRQn                       =  51,  /*!<  51  C_CAN0                           */
+  QEI_IRQn                          =  52,  /*!<  52  QEI                              */
+
+// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
+  M0_Reset_IRQn                     = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
+  M0_NonMaskableInt_IRQn            = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+  M0_HardFault_IRQn                 = -13,  /*!<   3  Hard Fault, all classes of Fault */
+  M0_SVCall_IRQn                    =  -5,  /*!<  11  System Service Call via SVC instruction */
+  M0_DebugMonitor_IRQn              =  -4,  /*!<  12  Debug Monitor                    */
+  M0_PendSV_IRQn                    =  -2,  /*!<  14  Pendable request for system service */
+  M0_SysTick_IRQn                   =  -1,  /*!<  15  System Tick Timer                */
+// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
+  M0_RTC_IRQn                       =   0,  /*!<   0  RTC                              */
+  M0_M4CORE_IRQn					=   1,  /*!<   1  M4                               */
+  M0_DMA_IRQn                       =   2,  /*!<   2  DMA                              */
+  M0_RESERVED0_IRQn					=   3,
+  M0_RESERVED1_IRQn					=   4,
+  M0_ETHERNET_IRQn                  =   5,  /*!<   5  ETHERNET                         */
+  M0_SDIO_IRQn                      =   6,  /*!<   6  SDIO                             */
+  M0_LCD_IRQn                       =   7,  /*!<   7  LCD                              */
+  M0_USB0_IRQn                      =   8,  /*!<   8  USB0                             */
+  M0_USB1_IRQn                      =   9,  /*!<   9  USB1                             */
+  M0_SCT_IRQn                       =  10,  /*!<  10  SCT                              */
+  M0_RITIMER_OR_WWDT_IRQn           =  11,  /*!<  11  RITIMER_OR_WWDT                  */
+  M0_TIMER0_IRQn                    =  12,  /*!<  12  TIMER0                           */
+  M0_GINT1_IRQn                     =  13,  /*!<  13  GINT1                            */
+  M0_TIMER3_IRQn                    =  15,  /*!<  15  TIMER3                           */
+  M0_RESERVED2_IRQn					=  14,
+  M0_RESERVED3_IRQn					=  15,
+  M0_MCPWM_IRQn                     =  16,  /*!<  16  MCPWM                            */
+  M0_ADC0_IRQn                      =  17,  /*!<  17  ADC0                             */
+  M0_I2C0_OR_I2C1_IRQn              =  18,  /*!<  18  I2C0_OR_I2C1                     */
+  M0_SGPIO_IRQn                     =  19,  /*!<  19  SGPIO                            */
+  M0_SPI_OR_DAC_IRQn                =  20,  /*!<  20  SPI_OR_DAC                       */
+  M0_ADC1_IRQn                      =  21,  /*!<  21  ADC1                             */
+  M0_SSP0_OR_SSP1_IRQn              =  22,  /*!<  22  SSP0_OR_SSP1                     */
+  M0_EVENTROUTER_IRQn               =  23,  /*!<  23  EVENTROUTER                      */
+  M0_USART0_IRQn                    =  24,  /*!<  24  USART0                           */
+  M0_UART1_IRQn                     =  25,  /*!<  25  UART1                            */
+  M0_USART2_OR_C_CAN1_IRQn          =  26,  /*!<  26  USART2_OR_C_CAN1                 */
+  M0_USART3_IRQn                    =  27,  /*!<  27  USART3                           */
+  M0_I2S0_OR_I2S1_OR_QEI_IRQn       =  28,  /*!<  28  I2S0_OR_I2S1_OR_QEI              */
+  M0_C_CAN0_IRQn                    =  29   /*!<  29  C_CAN0                           */
+} IRQn_Type;
+
+ /* Event Router Input (ERI) Number Definitions */
+typedef enum {
+  WAKEUP0_ERIn                      = 0,
+  WAKEUP1_ERIn                      = 1,
+  WAKEUP2_ERIn                      = 2,
+  WAKEUP3_ERIn                      = 3,
+  ATIMER_ERIn                       = 4,
+  RTC_ERIn                          = 5,
+  BOD1_ERIn                         = 6,  /* Bod trip 1 */
+  WWDT_ERIn                         = 7,
+  ETH_ERIn                          = 8,
+  USB0_ERIn                         = 9,
+  USB1_ERIn                         = 10,
+  SDIO_ERIn                         = 11,
+  CAN_ERIn                          = 12, /* CAN0/1 or'ed */
+  TIM2_ERIn                         = 13,
+  TIM6_ERIn                         = 14,
+  QEI_ERIn                          = 15,
+  TIM14_ERIn                        = 16,
+  RESERVED0_ERIn                    = 17, /* M0s */
+  RESERVED1_ERIn                    = 18, /* M3/M4 */
+  RESET_ERIn                        = 19
+}ERIn_Type;
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */
+
+#ifdef CORE_M4
+#define __CM4_REV              0x0000       /*!< Cortex-M4 Core Revision               */
+#define __MPU_PRESENT             1         /*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1         /*!< FPU present or not                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm4.h>                       /*!< Cortex-M4 processor and core peripherals */
+#else
+#ifdef CORE_M0
+#define __MPU_PRESENT             0         /*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0         /*!< FPU present or not                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm0.h>                       /*!< Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0 or CORE_M4
+#endif
+#endif
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+#include "system_LPC43xx.h"                 /*!< LPC43xx System                        */
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          SCT                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
+  */
+
+#define CONFIG_SCT_nEV   (16)            /* Number of events */
+#define CONFIG_SCT_nRG   (16)            /* Number of match/compare registers */
+#define CONFIG_SCT_nOU   (16)            /* Number of outputs */
+
+typedef struct
+{
+    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
+    union {
+        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
+        struct {
+            __IO uint16_t CTRL_L;       /* 0x004 low control register */
+            __IO uint16_t CTRL_H;       /* 0x006 high control register */
+        };
+    };
+    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
+    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
+    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
+    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
+    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
+    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
+    __IO uint16_t START_L;              /* 0x014 start register for counter L */
+    __IO uint16_t START_H;              /* 0x016 start register for counter H */
+         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
+    union {
+        __IO uint32_t COUNT_U;          /* 0x040 counter register */
+        struct {
+            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
+            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
+        };
+    };
+    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
+    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
+    __I  uint32_t INPUT;                /* 0x048 input register */
+    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
+    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
+    __IO uint32_t OUTPUT;               /* 0x050 output register */
+    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
+    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
+    __IO uint32_t DMA0REQUEST;          /* 0x05C DMA0 Request Register */
+    __IO uint32_t DMA1REQUEST;          /* 0x060 DMA1 Request Register */
+         uint32_t RESERVED2[35];        /* 0x064-0x0EC reserved */
+    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
+    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
+    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
+    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */
+
+    union {
+        __IO union {                    /* 0x100-... Match / Capture value */
+            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
+                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
+            };
+        } MATCH[CONFIG_SCT_nRG];
+        __I union {
+            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
+                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
+            };
+        } CAP[CONFIG_SCT_nRG];
+    };
+
+         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
+
+    union {
+        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
+        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
+    };
+         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
+    union {
+        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
+        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
+    };
+         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
+
+    union {
+        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
+            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
+                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
+            };
+        } MATCHREL[CONFIG_SCT_nRG];
+        __IO union {
+            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
+                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
+            };
+        } CAPCTRL[CONFIG_SCT_nRG];
+    };
+
+         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
+
+    union {
+        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
+        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
+    };
+         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
+    union {
+        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
+        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
+    };
+         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
+
+    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+        uint32_t STATE;                 /* Event State Register */
+        uint32_t CTRL;                  /* Event Control Register */
+    } EVENT[CONFIG_SCT_nEV];
+
+         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
+
+    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
+        uint32_t SET;                   /* Output n Set Register */
+        uint32_t CLR;                   /* Output n Clear Register */
+    } OUT[CONFIG_SCT_nOU];
+
+         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
+
+    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
+
+} LPC_SCT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         GPDMA                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (GPDMA)
+  */
+
+typedef struct {                            /*!< (@ 0x40002000) GPDMA Structure        */
+  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40002000) DMA Interrupt Status Register */
+  __I  uint32_t  INTTCSTAT;                 /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */
+  __O  uint32_t  INTTCCLEAR;                /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */
+  __I  uint32_t  INTERRSTAT;                /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */
+  __O  uint32_t  INTERRCLR;                 /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */
+  __I  uint32_t  RAWINTTCSTAT;              /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */
+  __I  uint32_t  RAWINTERRSTAT;             /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */
+  __I  uint32_t  ENBLDCHNS;                 /*!< (@ 0x4000201C) DMA Enabled Channel Register */
+  __IO uint32_t  SOFTBREQ;                  /*!< (@ 0x40002020) DMA Software Burst Request Register */
+  __IO uint32_t  SOFTSREQ;                  /*!< (@ 0x40002024) DMA Software Single Request Register */
+  __IO uint32_t  SOFTLBREQ;                 /*!< (@ 0x40002028) DMA Software Last Burst Request Register */
+  __IO uint32_t  SOFTLSREQ;                 /*!< (@ 0x4000202C) DMA Software Last Single Request Register */
+  __IO uint32_t  CONFIG;                    /*!< (@ 0x40002030) DMA Configuration Register */
+  __IO uint32_t  SYNC;                      /*!< (@ 0x40002034) DMA Synchronization Register */
+  __I  uint32_t  RESERVED0[50];
+  __IO uint32_t  C0SRCADDR;                 /*!< (@ 0x40002100) DMA Channel Source Address Register */
+  __IO uint32_t  C0DESTADDR;                /*!< (@ 0x40002104) DMA Channel Destination Address Register */
+  __IO uint32_t  C0LLI;                     /*!< (@ 0x40002108) DMA Channel Linked List Item Register */
+  __IO uint32_t  C0CONTROL;                 /*!< (@ 0x4000210C) DMA Channel Control Register */
+  __IO uint32_t  C0CONFIG;                  /*!< (@ 0x40002110) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED1[3];
+  __IO uint32_t  C1SRCADDR;                 /*!< (@ 0x40002120) DMA Channel Source Address Register */
+  __IO uint32_t  C1DESTADDR;                /*!< (@ 0x40002124) DMA Channel Destination Address Register */
+  __IO uint32_t  C1LLI;                     /*!< (@ 0x40002128) DMA Channel Linked List Item Register */
+  __IO uint32_t  C1CONTROL;                 /*!< (@ 0x4000212C) DMA Channel Control Register */
+  __IO uint32_t  C1CONFIG;                  /*!< (@ 0x40002130) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED2[3];
+  __IO uint32_t  C2SRCADDR;                 /*!< (@ 0x40002140) DMA Channel Source Address Register */
+  __IO uint32_t  C2DESTADDR;                /*!< (@ 0x40002144) DMA Channel Destination Address Register */
+  __IO uint32_t  C2LLI;                     /*!< (@ 0x40002148) DMA Channel Linked List Item Register */
+  __IO uint32_t  C2CONTROL;                 /*!< (@ 0x4000214C) DMA Channel Control Register */
+  __IO uint32_t  C2CONFIG;                  /*!< (@ 0x40002150) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  C3SRCADDR;                 /*!< (@ 0x40002160) DMA Channel Source Address Register */
+  __IO uint32_t  C3DESTADDR;                /*!< (@ 0x40002164) DMA Channel Destination Address Register */
+  __IO uint32_t  C3LLI;                     /*!< (@ 0x40002168) DMA Channel Linked List Item Register */
+  __IO uint32_t  C3CONTROL;                 /*!< (@ 0x4000216C) DMA Channel Control Register */
+  __IO uint32_t  C3CONFIG;                  /*!< (@ 0x40002170) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  C4SRCADDR;                 /*!< (@ 0x40002180) DMA Channel Source Address Register */
+  __IO uint32_t  C4DESTADDR;                /*!< (@ 0x40002184) DMA Channel Destination Address Register */
+  __IO uint32_t  C4LLI;                     /*!< (@ 0x40002188) DMA Channel Linked List Item Register */
+  __IO uint32_t  C4CONTROL;                 /*!< (@ 0x4000218C) DMA Channel Control Register */
+  __IO uint32_t  C4CONFIG;                  /*!< (@ 0x40002190) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  C5SRCADDR;                 /*!< (@ 0x400021A0) DMA Channel Source Address Register */
+  __IO uint32_t  C5DESTADDR;                /*!< (@ 0x400021A4) DMA Channel Destination Address Register */
+  __IO uint32_t  C5LLI;                     /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */
+  __IO uint32_t  C5CONTROL;                 /*!< (@ 0x400021AC) DMA Channel Control Register */
+  __IO uint32_t  C5CONFIG;                  /*!< (@ 0x400021B0) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  C6SRCADDR;                 /*!< (@ 0x400021C0) DMA Channel Source Address Register */
+  __IO uint32_t  C6DESTADDR;                /*!< (@ 0x400021C4) DMA Channel Destination Address Register */
+  __IO uint32_t  C6LLI;                     /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */
+  __IO uint32_t  C6CONTROL;                 /*!< (@ 0x400021CC) DMA Channel Control Register */
+  __IO uint32_t  C6CONFIG;                  /*!< (@ 0x400021D0) DMA Channel Configuration Register */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  C7SRCADDR;                 /*!< (@ 0x400021E0) DMA Channel Source Address Register */
+  __IO uint32_t  C7DESTADDR;                /*!< (@ 0x400021E4) DMA Channel Destination Address Register */
+  __IO uint32_t  C7LLI;                     /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */
+  __IO uint32_t  C7CONTROL;                 /*!< (@ 0x400021EC) DMA Channel Control Register */
+  __IO uint32_t  C7CONFIG;                  /*!< (@ 0x400021F0) DMA Channel Configuration Register */
+} LPC_GPDMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SDMMC                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a  (SDMMC)
+  */
+
+typedef struct {                            /*!< (@ 0x40004000) SDMMC Structure        */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40004000) Control Register       */
+  __IO uint32_t  PWREN;                     /*!< (@ 0x40004004) Power Enable Register  */
+  __IO uint32_t  CLKDIV;                    /*!< (@ 0x40004008) Clock Divider Register */
+  __IO uint32_t  CLKSRC;                    /*!< (@ 0x4000400C) SD Clock Source Register */
+  __IO uint32_t  CLKENA;                    /*!< (@ 0x40004010) Clock Enable Register  */
+  __IO uint32_t  TMOUT;                     /*!< (@ 0x40004014) Timeout Register       */
+  __IO uint32_t  CTYPE;                     /*!< (@ 0x40004018) Card Type Register     */
+  __IO uint32_t  BLKSIZ;                    /*!< (@ 0x4000401C) Block Size Register    */
+  __IO uint32_t  BYTCNT;                    /*!< (@ 0x40004020) Byte Count Register    */
+  __IO uint32_t  INTMASK;                   /*!< (@ 0x40004024) Interrupt Mask Register */
+  __IO uint32_t  CMDARG;                    /*!< (@ 0x40004028) Command Argument Register */
+  __IO uint32_t  CMD;                       /*!< (@ 0x4000402C) Command Register       */
+  __I  uint32_t  RESP0;                     /*!< (@ 0x40004030) Response Register 0    */
+  __I  uint32_t  RESP1;                     /*!< (@ 0x40004034) Response Register 1    */
+  __I  uint32_t  RESP2;                     /*!< (@ 0x40004038) Response Register 2    */
+  __I  uint32_t  RESP3;                     /*!< (@ 0x4000403C) Response Register 3    */
+  __I  uint32_t  MINTSTS;                   /*!< (@ 0x40004040) Masked Interrupt Status Register */
+  __IO uint32_t  RINTSTS;                   /*!< (@ 0x40004044) Raw Interrupt Status Register */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40004048) Status Register        */
+  __IO uint32_t  FIFOTH;                    /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */
+  __I  uint32_t  CDETECT;                   /*!< (@ 0x40004050) Card Detect Register   */
+  __I  uint32_t  WRTPRT;                    /*!< (@ 0x40004054) Write Protect Register */
+  __IO uint32_t  GPIO;                      /*!< (@ 0x40004058) General Purpose Input/Output Register */
+  __I  uint32_t  TCBCNT;                    /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */
+  __I  uint32_t  TBBCNT;                    /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */
+  __IO uint32_t  DEBNCE;                    /*!< (@ 0x40004064) Debounce Count Register */
+  __IO uint32_t  USRID;                     /*!< (@ 0x40004068) User ID Register       */
+  __I  uint32_t  VERID;                     /*!< (@ 0x4000406C) Version ID Register    */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UHS_REG;                   /*!< (@ 0x40004074) UHS-1 Register         */
+  __IO uint32_t  RST_N;                     /*!< (@ 0x40004078) Hardware Reset         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  BMOD;                      /*!< (@ 0x40004080) Bus Mode Register      */
+  __O  uint32_t  PLDMND;                    /*!< (@ 0x40004084) Poll Demand Register   */
+  __IO uint32_t  DBADDR;                    /*!< (@ 0x40004088) Descriptor List Base Address Register */
+  __IO uint32_t  IDSTS;                     /*!< (@ 0x4000408C) Internal DMAC Status Register */
+  __IO uint32_t  IDINTEN;                   /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */
+  __I  uint32_t  DSCADDR;                   /*!< (@ 0x40004094) Current Host Descriptor Address Register */
+  __I  uint32_t  BUFADDR;                   /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */
+} LPC_SDMMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          EMC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7  (EMC)
+  */
+
+typedef struct {                            /*!< (@ 0x40005000) EMC Structure          */
+  __IO uint32_t  CONTROL;                   /*!< (@ 0x40005000) Controls operation of the memory controller. */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40005004) Provides EMC status information. */
+  __IO uint32_t  CONFIG;                    /*!< (@ 0x40005008) Configures operation of the memory controller. */
+  __I  uint32_t  RESERVED0[5];
+  __IO uint32_t  DYNAMICCONTROL;            /*!< (@ 0x40005020) Controls dynamic memory operation. */
+  __IO uint32_t  DYNAMICREFRESH;            /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */
+  __IO uint32_t  DYNAMICREADCONFIG;         /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  DYNAMICRP;                 /*!< (@ 0x40005030) Selects the precharge command period. */
+  __IO uint32_t  DYNAMICRAS;                /*!< (@ 0x40005034) Selects the active to precharge command period. */
+  __IO uint32_t  DYNAMICSREX;               /*!< (@ 0x40005038) Selects the self-refresh exit time. */
+  __IO uint32_t  DYNAMICAPR;                /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */
+  __IO uint32_t  DYNAMICDAL;                /*!< (@ 0x40005040) Selects the data-in to active command time. */
+  __IO uint32_t  DYNAMICWR;                 /*!< (@ 0x40005044) Selects the write recovery time. */
+  __IO uint32_t  DYNAMICRC;                 /*!< (@ 0x40005048) Selects the active to active command period. */
+  __IO uint32_t  DYNAMICRFC;                /*!< (@ 0x4000504C) Selects the auto-refresh period. */
+  __IO uint32_t  DYNAMICXSR;                /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */
+  __IO uint32_t  DYNAMICRRD;                /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */
+  __IO uint32_t  DYNAMICMRD;                /*!< (@ 0x40005058) Selects the load mode register to active command time. */
+  __I  uint32_t  RESERVED2[9];
+  __IO uint32_t  STATICEXTENDEDWAIT;        /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */
+  __I  uint32_t  RESERVED3[31];
+  __IO uint32_t  DYNAMICCONFIG0;            /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS0;            /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED4[6];
+  __IO uint32_t  DYNAMICCONFIG1;            /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS1;            /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED5[6];
+  __IO uint32_t  DYNAMICCONFIG2;            /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS2;            /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED6[6];
+  __IO uint32_t  DYNAMICCONFIG3;            /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */
+  __IO uint32_t  DYNAMICRASCAS3;            /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+  __I  uint32_t  RESERVED7[38];
+  __IO uint32_t  STATICCONFIG0;             /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN0;            /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN0;            /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD0;             /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG0;            /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR0;             /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN0;           /*!< (@ 0x40005218) Selects bus turnaround cycles */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  STATICCONFIG1;             /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN1;            /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN1;            /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD1;             /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG1;            /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR1;             /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN1;           /*!< (@ 0x40005238) Selects bus turnaround cycles */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  STATICCONFIG2;             /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN2;            /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN2;            /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD2;             /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG2;            /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR2;             /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN2;           /*!< (@ 0x40005258) Selects bus turnaround cycles */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  STATICCONFIG3;             /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */
+  __IO uint32_t  STATICWAITWEN3;            /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */
+  __IO uint32_t  STATICWAITOEN3;            /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+  __IO uint32_t  STATICWAITRD3;             /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */
+  __IO uint32_t  STATICWAITPAG3;            /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+  __IO uint32_t  STATICWAITWR3;             /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */
+  __IO uint32_t  STATICWAITTURN3;           /*!< (@ 0x40005278) Selects bus turnaround cycles */
+} LPC_EMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         USB0                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB0)
+  */
+
+typedef struct {                            /*!< (@ 0x40006000) USB0 Structure         */
+  __I  uint32_t  RESERVED0[64];
+  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40006100) Capability register length */
+  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40006104) Host controller structural parameters */
+  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40006108) Host controller capability parameters */
+  __I  uint32_t  RESERVED1[5];
+  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40006120) Device interface version number */
+  __I  uint32_t  RESERVED2[7];
+  
+  union {
+    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40006140) USB command (host mode) */
+    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40006140) USB command (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40006144) USB status (host mode) */
+    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40006144) USB status (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40006148) USB interrupt enable (host mode) */
+    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40006148) USB interrupt enable (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000614C) USB frame index (host mode) */
+    __IO uint32_t  FRINDEX_D;               /*!< (@ 0x4000614C) USB frame index (device mode) */
+  } ;
+  __I  uint32_t  RESERVED3;
+  
+  union {
+    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40006154) Frame list base address (host mode) */
+    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40006154) USB device address (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40006158) Address of endpoint list in memory */
+    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40006158) Address of endpoint list in memory */
+  } ;
+  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */
+  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40006160) Programmable burst size */
+  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40006174) Length of virtual frame */
+  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40006178) Endpoint NAK (device mode) */
+  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */
+  __I  uint32_t  RESERVED5;
+  
+  union {
+    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40006184) Port 1 status/control (host mode) */
+    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40006184) Port 1 status/control (device mode) */
+  } ;
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  OTGSC;                     /*!< (@ 0x400061A4) OTG status and control */
+  
+  union {
+    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400061A8) USB mode (host mode)   */
+    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400061A8) USB device mode (device mode) */
+  } ;
+  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400061AC) Endpoint setup status  */
+  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400061B0) Endpoint initialization */
+  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400061B4) Endpoint de-initialization */
+  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400061B8) Endpoint status        */
+  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400061BC) Endpoint complete      */
+  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400061C0) Endpoint control 0     */
+  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400061C4) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400061C8) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400061CC) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL4;                /*!< (@ 0x400061D0) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL5;                /*!< (@ 0x400061D4) Endpoint control       */
+} LPC_USB0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         USB1                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB1)
+  */
+
+typedef struct {                            /*!< (@ 0x40007000) USB1 Structure         */
+  __I  uint32_t  RESERVED0[64];
+  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40007100) Capability register length */
+  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40007104) Host controller structural parameters */
+  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40007108) Host controller capability parameters */
+  __I  uint32_t  RESERVED1[5];
+  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40007120) Device interface version number */
+  __I  uint32_t  RESERVED2[7];
+  
+  union {
+    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40007140) USB command (host mode) */
+    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40007140) USB command (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40007144) USB status (host mode) */
+    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40007144) USB status (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40007148) USB interrupt enable (host mode) */
+    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40007148) USB interrupt enable (device mode) */
+  } ;
+  
+  union {
+    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000714C) USB frame index (host mode) */
+    __I  uint32_t  FRINDEX_D;               /*!< (@ 0x4000714C) USB frame index (device mode) */
+  } ;
+  __I  uint32_t  RESERVED3;
+  
+  union {
+    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40007154) Frame list base address */
+    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40007154) USB device address     */
+  } ;
+  
+  union {
+    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */
+    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */
+  } ;
+  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */
+  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40007160) Programmable burst size */
+  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  ULPIVIEWPORT;              /*!< (@ 0x40007170) ULPI viewport          */
+  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40007174) Length of virtual frame */
+  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40007178) Endpoint NAK (device mode) */
+  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */
+  __I  uint32_t  RESERVED5;
+  
+  union {
+    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40007184) Port 1 status/control (host mode) */
+    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40007184) Port 1 status/control (device mode) */
+  } ;
+  __I  uint32_t  RESERVED6[8];
+  
+  union {
+    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400071A8) USB mode (host mode)   */
+    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400071A8) USB mode (device mode) */
+  } ;
+  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400071AC) Endpoint setup status  */
+  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400071B0) Endpoint initialization */
+  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400071B4) Endpoint de-initialization */
+  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400071B8) Endpoint status        */
+  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400071BC) Endpoint complete      */
+  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400071C0) Endpoint control 0     */
+  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400071C4) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400071C8) Endpoint control       */
+  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400071CC) Endpoint control       */
+} LPC_USB1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          LCD                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7  (LCD)
+  */
+
+typedef struct {                            /*!< (@ 0x40008000) LCD Structure          */
+  __IO uint32_t  TIMH;                      /*!< (@ 0x40008000) Horizontal Timing Control register */
+  __IO uint32_t  TIMV;                      /*!< (@ 0x40008004) Vertical Timing Control register */
+  __IO uint32_t  POL;                       /*!< (@ 0x40008008) Clock and Signal Polarity Control register */
+  __IO uint32_t  LE;                        /*!< (@ 0x4000800C) Line End Control register */
+  __IO uint32_t  UPBASE;                    /*!< (@ 0x40008010) Upper Panel Frame Base Address register */
+  __IO uint32_t  LPBASE;                    /*!< (@ 0x40008014) Lower Panel Frame Base Address register */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40008018) LCD Control register   */
+  __IO uint32_t  INTMSK;                    /*!< (@ 0x4000801C) Interrupt Mask register */
+  __I  uint32_t  INTRAW;                    /*!< (@ 0x40008020) Raw Interrupt Status register */
+  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40008024) Masked Interrupt Status register */
+  __O  uint32_t  INTCLR;                    /*!< (@ 0x40008028) Interrupt Clear register */
+  __I  uint32_t  UPCURR;                    /*!< (@ 0x4000802C) Upper Panel Current Address Value register */
+  __I  uint32_t  LPCURR;                    /*!< (@ 0x40008030) Lower Panel Current Address Value register */
+  __I  uint32_t  RESERVED0[115];
+  __IO uint32_t PAL[256];					/*!< (@ 0x40008200) 256x16-bit Color Palette registers */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t CRSR_IMG[256];              /*!< (@ 0x40008800) Cursor Image registers */
+  __IO uint32_t  CRSR_CTRL;                 /*!< (@ 0x40008C00) Cursor Control register */
+  __IO uint32_t  CRSR_CFG;                  /*!< (@ 0x40008C04) Cursor Configuration register */
+  __IO uint32_t  CRSR_PAL0;                 /*!< (@ 0x40008C08) Cursor Palette register 0 */
+  __IO uint32_t  CRSR_PAL1;                 /*!< (@ 0x40008C0C) Cursor Palette register 1 */
+  __IO uint32_t  CRSR_XY;                   /*!< (@ 0x40008C10) Cursor XY Position register */
+  __IO uint32_t  CRSR_CLIP;                 /*!< (@ 0x40008C14) Cursor Clip Position register */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  CRSR_INTMSK;               /*!< (@ 0x40008C20) Cursor Interrupt Mask register */
+  __O  uint32_t  CRSR_INTCLR;               /*!< (@ 0x40008C24) Cursor Interrupt Clear register */
+  __I  uint32_t  CRSR_INTRAW;               /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */
+  __I  uint32_t  CRSR_INTSTAT;              /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */
+} LPC_LCD_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       ETHERNET                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available  (ETHERNET)
+  */
+
+typedef struct {                            /*!< (@ 0x40010000) ETHERNET Structure     */
+  __IO uint32_t  MAC_CONFIG;                /*!< (@ 0x40010000) MAC configuration register */
+  __IO uint32_t  MAC_FRAME_FILTER;          /*!< (@ 0x40010004) MAC frame filter       */
+  __IO uint32_t  MAC_HASHTABLE_HIGH;        /*!< (@ 0x40010008) Hash table high register */
+  __IO uint32_t  MAC_HASHTABLE_LOW;         /*!< (@ 0x4001000C) Hash table low register */
+  __IO uint32_t  MAC_MII_ADDR;              /*!< (@ 0x40010010) MII address register   */
+  __IO uint32_t  MAC_MII_DATA;              /*!< (@ 0x40010014) MII data register      */
+  __IO uint32_t  MAC_FLOW_CTRL;             /*!< (@ 0x40010018) Flow control register  */
+  __IO uint32_t  MAC_VLAN_TAG;              /*!< (@ 0x4001001C) VLAN tag register      */
+  __I  uint32_t  RESERVED0;
+  __I  uint32_t  MAC_DEBUG;                 /*!< (@ 0x40010024) Debug register         */
+  __IO uint32_t  MAC_RWAKE_FRFLT;           /*!< (@ 0x40010028) Remote wake-up frame filter */
+  __IO uint32_t  MAC_PMT_CTRL_STAT;         /*!< (@ 0x4001002C) PMT control and status */
+  __I  uint32_t  RESERVED1[2];
+  __I  uint32_t  MAC_INTR;                  /*!< (@ 0x40010038) Interrupt status register */
+  __IO uint32_t  MAC_INTR_MASK;             /*!< (@ 0x4001003C) Interrupt mask register */
+  __IO uint32_t  MAC_ADDR0_HIGH;            /*!< (@ 0x40010040) MAC address 0 high register */
+  __IO uint32_t  MAC_ADDR0_LOW;             /*!< (@ 0x40010044) MAC address 0 low register */
+  __I  uint32_t  RESERVED2[430];
+  __IO uint32_t  MAC_TIMESTP_CTRL;          /*!< (@ 0x40010700) Time stamp control register */
+  __IO uint32_t  SUBSECOND_INCR;            /*!< (@ 0x40010704) Sub-second increment register */
+  __I  uint32_t  SECONDS;                   /*!< (@ 0x40010708) System time seconds register */
+  __I  uint32_t  NANOSECONDS;               /*!< (@ 0x4001070C) System time nanoseconds register */
+  __IO uint32_t  SECONDSUPDATE;             /*!< (@ 0x40010710) System time seconds update register */
+  __IO uint32_t  NANOSECONDSUPDATE;         /*!< (@ 0x40010714) System time nanoseconds update register */
+  __IO uint32_t  ADDEND;                    /*!< (@ 0x40010718) Time stamp addend register */
+  __IO uint32_t  TARGETSECONDS;             /*!< (@ 0x4001071C) Target time seconds register */
+  __IO uint32_t  TARGETNANOSECONDS;         /*!< (@ 0x40010720) Target time nanoseconds register */
+  __IO uint32_t  HIGHWORD;                  /*!< (@ 0x40010724) System time higher word seconds register */
+  __I  uint32_t  TIMESTAMPSTAT;             /*!< (@ 0x40010728) Time stamp status register */
+  __IO uint32_t  PPSCTRL;                   /*!< (@ 0x4001072C) PPS control register   */
+  __I  uint32_t  AUXNANOSECONDS;            /*!< (@ 0x40010730) Auxiliary time stamp nanoseconds register */
+  __I  uint32_t  AUXSECONDS;                /*!< (@ 0x40010734) Auxiliary time stamp seconds register */
+  __I  uint32_t  RESERVED3[562];
+  __IO uint32_t  DMA_BUS_MODE;              /*!< (@ 0x40011000) Bus Mode Register      */
+  __IO uint32_t  DMA_TRANS_POLL_DEMAND;     /*!< (@ 0x40011004) Transmit poll demand register */
+  __IO uint32_t  DMA_REC_POLL_DEMAND;       /*!< (@ 0x40011008) Receive poll demand register */
+  __IO uint32_t  DMA_REC_DES_ADDR;          /*!< (@ 0x4001100C) Receive descriptor list address register */
+  __IO uint32_t  DMA_TRANS_DES_ADDR;        /*!< (@ 0x40011010) Transmit descriptor list address register */
+  __IO uint32_t  DMA_STAT;                  /*!< (@ 0x40011014) Status register        */
+  __IO uint32_t  DMA_OP_MODE;               /*!< (@ 0x40011018) Operation mode register */
+  __IO uint32_t  DMA_INT_EN;                /*!< (@ 0x4001101C) Interrupt enable register */
+  __I  uint32_t  DMA_MFRM_BUFOF;            /*!< (@ 0x40011020) Missed frame and buffer overflow register */
+  __IO uint32_t  DMA_REC_INT_WDT;           /*!< (@ 0x40011024) Receive interrupt watchdog timer register */
+  __I  uint32_t  RESERVED4[8];
+  __I  uint32_t  DMA_CURHOST_TRANS_DES;     /*!< (@ 0x40011048) Current host transmit descriptor register */
+  __I  uint32_t  DMA_CURHOST_REC_DES;       /*!< (@ 0x4001104C) Current host receive descriptor register */
+  __I  uint32_t  DMA_CURHOST_TRANS_BUF;     /*!< (@ 0x40011050) Current host transmit buffer address register */
+  __I  uint32_t  DMA_CURHOST_REC_BUF;       /*!< (@ 0x40011054) Current host receive buffer address register */
+} LPC_ETHERNET_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        ATIMER                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6  (ATIMER)
+  */
+
+typedef struct {                            /*!< (@ 0x40040000) ATIMER Structure       */
+  __IO uint32_t  DOWNCOUNTER;               /*!< (@ 0x40040000) Downcounter register   */
+  __IO uint32_t  PRESET;                    /*!< (@ 0x40040004) Preset value register  */
+  __I  uint32_t  RESERVED0[1012];
+  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40040FD8) Interrupt clear enable register */
+  __O  uint32_t  SET_EN;                    /*!< (@ 0x40040FDC) Interrupt set enable register */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40040FE0) Status register        */
+  __I  uint32_t  ENABLE;                    /*!< (@ 0x40040FE4) Enable register        */
+  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40040FE8) Clear register         */
+  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40040FEC) Set register           */
+} LPC_ATIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        REGFILE                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7  (REGFILE)
+  */
+
+typedef struct {                            /*!< (@ 0x40041000) REGFILE Structure      */
+  __IO uint32_t REGFILE[64];                /*!< (@ 0x40041000) General purpose storage register */
+} LPC_REGFILE_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          PMC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (PMC)
+  */
+
+typedef struct {                            /*!< (@ 0x40042000) PMC Structure          */
+  __IO uint32_t  PD0_SLEEP0_HW_ENA;         /*!< (@ 0x40042000) Hardware sleep event enable register */
+  __I  uint32_t  RESERVED0[6];
+  __IO uint32_t  PD0_SLEEP0_MODE;           /*!< (@ 0x4004201C) Sleep power mode register */
+} LPC_PMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         CREG                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3  (CREG)
+  */
+
+typedef struct {                            /*!< (@ 0x40043000) CREG Structure         */
+  __I  uint32_t  IRCTRM;                    /*!< (@ 0x40043000) IRC trim register      */
+  __IO uint32_t  CREG0;                     /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */
+  __I  uint32_t  RESERVED1[62];
+  __IO uint32_t  M4MEMMAP;                  /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */
+  __I  uint32_t  RESERVED2[5];
+  __IO uint32_t  CREG5;                     /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */
+  __IO uint32_t  DMAMUX;                    /*!< (@ 0x4004311C) DMA muxing control     */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  ETBCFG;                    /*!< (@ 0x40043128) ETB RAM configuration  */
+  __IO uint32_t  CREG6;                     /*!< (@ 0x4004312C) Chip configuration register 6. */
+  __IO uint32_t  M4TXEVENT;                 /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */
+  __I  uint32_t  RESERVED4[51];
+  __I  uint32_t  CHIPID;                    /*!< (@ 0x40043200) Part ID                */
+  __I  uint32_t  RESERVED5[127];
+  __IO uint32_t  M0TXEVENT;                 /*!< (@ 0x40043400) Cortex-M0 TXEV event clear */
+  __IO uint32_t  M0APPMEMMAP;               /*!< (@ 0x40043404) ARM Cortex-M0 memory mapping */
+} LPC_CREG_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                      EVENTROUTER                                     -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3  (EVENTROUTER)
+  */
+
+typedef struct {                            /*!< (@ 0x40044000) EVENTROUTER Structure  */
+  __IO uint32_t  HILO;                      /*!< (@ 0x40044000) Level configuration register */
+  __IO uint32_t  EDGE;                      /*!< (@ 0x40044004) Edge configuration     */
+  __I  uint32_t  RESERVED0[1012];
+  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40044FD8) Clear event enable register */
+  __O  uint32_t  SET_EN;                    /*!< (@ 0x40044FDC) Set event enable register */
+  __I  uint32_t  STATUS;                    /*!< (@ 0x40044FE0) Event Status register  */
+  __I  uint32_t  ENABLE;                    /*!< (@ 0x40044FE4) Event Enable register  */
+  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40044FE8) Clear event status register */
+  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40044FEC) Set event status register */
+} LPC_EVENTROUTER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          RTC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (RTC)
+  */
+
+typedef struct {                            /*!< (@ 0x40046000) RTC Structure          */
+  __O  uint32_t  ILR;                       /*!< (@ 0x40046000) Interrupt Location Register */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  CCR;                       /*!< (@ 0x40046008) Clock Control Register */
+  __IO uint32_t  CIIR;                      /*!< (@ 0x4004600C) Counter Increment Interrupt Register */
+  __IO uint32_t  AMR;                       /*!< (@ 0x40046010) Alarm Mask Register    */
+  __I  uint32_t  CTIME0;                    /*!< (@ 0x40046014) Consolidated Time Register 0 */
+  __I  uint32_t  CTIME1;                    /*!< (@ 0x40046018) Consolidated Time Register 1 */
+  __I  uint32_t  CTIME2;                    /*!< (@ 0x4004601C) Consolidated Time Register 2 */
+  __IO uint32_t  SEC;                       /*!< (@ 0x40046020) Seconds Register       */
+  __IO uint32_t  MIN;                       /*!< (@ 0x40046024) Minutes Register       */
+  __IO uint32_t  HRS;                       /*!< (@ 0x40046028) Hours Register         */
+  __IO uint32_t  DOM;                       /*!< (@ 0x4004602C) Day of Month Register  */
+  __IO uint32_t  DOW;                       /*!< (@ 0x40046030) Day of Week Register   */
+  __IO uint32_t  DOY;                       /*!< (@ 0x40046034) Day of Year Register   */
+  __IO uint32_t  MONTH;                     /*!< (@ 0x40046038) Months Register        */
+  __IO uint32_t  YEAR;                      /*!< (@ 0x4004603C) Years Register         */
+  __IO uint32_t  CALIBRATION;               /*!< (@ 0x40046040) Calibration Value Register */
+  __I  uint32_t  RESERVED1[7];
+  __IO uint32_t  ASEC;                      /*!< (@ 0x40046060) Alarm value for Seconds */
+  __IO uint32_t  AMIN;                      /*!< (@ 0x40046064) Alarm value for Minutes */
+  __IO uint32_t  AHRS;                      /*!< (@ 0x40046068) Alarm value for Hours  */
+  __IO uint32_t  ADOM;                      /*!< (@ 0x4004606C) Alarm value for Day of Month */
+  __IO uint32_t  ADOW;                      /*!< (@ 0x40046070) Alarm value for Day of Week */
+  __IO uint32_t  ADOY;                      /*!< (@ 0x40046074) Alarm value for Day of Year */
+  __IO uint32_t  AMON;                      /*!< (@ 0x40046078) Alarm value for Months */
+  __IO uint32_t  AYRS;                      /*!< (@ 0x4004607C) Alarm value for Year   */
+} LPC_RTC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          CGU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1  (CGU)
+  */
+
+typedef struct {                            /*!< (@ 0x40050000) CGU Structure          */
+  __I  uint32_t  RESERVED0[5];
+  __IO uint32_t  FREQ_MON;                  /*!< (@ 0x40050014) Frequency monitor register */
+  __IO uint32_t  XTAL_OSC_CTRL;             /*!< (@ 0x40050018) Crystal oscillator control register */
+  __I  uint32_t  PLL0USB_STAT;              /*!< (@ 0x4005001C) PLL0 (USB) status register */
+  __IO uint32_t  PLL0USB_CTRL;              /*!< (@ 0x40050020) PLL0 (USB) control register */
+  __IO uint32_t  PLL0USB_MDIV;              /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+  __IO uint32_t  PLL0USB_NP_DIV;            /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+  __I  uint32_t  PLL0AUDIO_STAT;            /*!< (@ 0x4005002C) PLL0 (audio) status register */
+  __IO uint32_t  PLL0AUDIO_CTRL;            /*!< (@ 0x40050030) PLL0 (audio) control register */
+  __IO uint32_t  PLL0AUDIO_MDIV;            /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+  __IO uint32_t  PLL0AUDIO_NP_DIV;          /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+  __IO uint32_t  PLL0AUDIO_FRAC;            /*!< (@ 0x4005003C) PLL0 (audio)           */
+  __I  uint32_t  PLL1_STAT;                 /*!< (@ 0x40050040) PLL1 status register   */
+  __IO uint32_t  PLL1_CTRL;                 /*!< (@ 0x40050044) PLL1 control register  */
+  __IO uint32_t  IDIVA_CTRL;                /*!< (@ 0x40050048) Integer divider A control register */
+  __IO uint32_t  IDIVB_CTRL;                /*!< (@ 0x4005004C) Integer divider B control register */
+  __IO uint32_t  IDIVC_CTRL;                /*!< (@ 0x40050050) Integer divider C control register */
+  __IO uint32_t  IDIVD_CTRL;                /*!< (@ 0x40050054) Integer divider D control register */
+  __IO uint32_t  IDIVE_CTRL;                /*!< (@ 0x40050058) Integer divider E control register */
+  __IO uint32_t  BASE_SAFE_CLK;             /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */
+  __IO uint32_t  BASE_USB0_CLK;             /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */
+  __IO uint32_t  BASE_PERIPH_CLK;           /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */
+  __IO uint32_t  BASE_USB1_CLK;             /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */
+  __IO uint32_t  BASE_M4_CLK;               /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */
+  __IO uint32_t  BASE_SPIFI_CLK;            /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */
+  __IO uint32_t  BASE_SPI_CLK;              /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */
+  __IO uint32_t  BASE_PHY_RX_CLK;           /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */
+  __IO uint32_t  BASE_PHY_TX_CLK;           /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */
+  __IO uint32_t  BASE_APB1_CLK;             /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */
+  __IO uint32_t  BASE_APB3_CLK;             /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */
+  __IO uint32_t  BASE_LCD_CLK;              /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  BASE_SDIO_CLK;             /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */
+  __IO uint32_t  BASE_SSP0_CLK;             /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */
+  __IO uint32_t  BASE_SSP1_CLK;             /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */
+  __IO uint32_t  BASE_UART0_CLK;            /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */
+  __IO uint32_t  BASE_UART1_CLK;            /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */
+  __IO uint32_t  BASE_UART2_CLK;            /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */
+  __IO uint32_t  BASE_UART3_CLK;            /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */
+  __IO uint32_t  BASE_OUT_CLK;              /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */
+  __I  uint32_t  RESERVED3[4];
+  __IO uint32_t  BASE_APLL_CLK;             /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */
+  __IO uint32_t  BASE_CGU_OUT0_CLK;         /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */
+  __IO uint32_t  BASE_CGU_OUT1_CLK;         /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */
+} LPC_CGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         CCU1                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1)
+  */
+
+typedef struct {                            /*!< (@ 0x40051000) CCU1 Structure         */
+  __IO uint32_t  PM;                        /*!< (@ 0x40051000) CCU1 power mode register */
+  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40051004) CCU1 base clocks status register */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  CLK_APB3_BUS_CFG;          /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */
+  __I  uint32_t  CLK_APB3_BUS_STAT;         /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */
+  __IO uint32_t  CLK_APB3_I2C1_CFG;         /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */
+  __I  uint32_t  CLK_APB3_I2C1_STAT;        /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */
+  __IO uint32_t  CLK_APB3_DAC_CFG;          /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */
+  __I  uint32_t  CLK_APB3_DAC_STAT;         /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */
+  __IO uint32_t  CLK_APB3_ADC0_CFG;         /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */
+  __I  uint32_t  CLK_APB3_ADC0_STAT;        /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */
+  __IO uint32_t  CLK_APB3_ADC1_CFG;         /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */
+  __I  uint32_t  CLK_APB3_ADC1_STAT;        /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */
+  __IO uint32_t  CLK_APB3_CAN0_CFG;         /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */
+  __I  uint32_t  CLK_APB3_CAN0_STAT;        /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  CLK_APB1_BUS_CFG;          /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */
+  __I  uint32_t  CLK_APB1_BUS_STAT;         /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */
+  __IO uint32_t  CLK_APB1_MOTOCONPWM_CFG;   /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */
+  __I  uint32_t  CLK_APB1_MOTOCONPWM_STAT;  /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */
+  __IO uint32_t  CLK_ABP1_I2C0_CFG;         /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */
+  __I  uint32_t  CLK_APB1_I2C0_STAT;        /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */
+  __IO uint32_t  CLK_APB1_I2S_CFG;          /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */
+  __I  uint32_t  CLK_APB1_I2S_STAT;         /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */
+  __IO uint32_t  CLK_APB1_CAN1_CFG;         /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */
+  __I  uint32_t  CLK_APB1_CAN1_STAT;        /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */
+  __I  uint32_t  RESERVED2[54];
+  __IO uint32_t  CLK_SPIFI_CFG;             /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */
+  __I  uint32_t  CLK_SPIFI_STAT;            /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */
+  __I  uint32_t  RESERVED3[62];
+  __IO uint32_t  CLK_M4_BUS_CFG;            /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */
+  __I  uint32_t  CLK_M4_BUS_STAT;           /*!< (@ 0x40051404) CLK_M4_BUSclock status register */
+  __IO uint32_t  CLK_M4_SPIFI_CFG;          /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */
+  __I  uint32_t  CLK_M4_SPIFI_STAT;         /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */
+  __IO uint32_t  CLK_M4_GPIO_CFG;           /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */
+  __I  uint32_t  CLK_M4_GPIO_STAT;          /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */
+  __IO uint32_t  CLK_M4_LCD_CFG;            /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */
+  __I  uint32_t  CLK_M4_LCD_STAT;           /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */
+  __IO uint32_t  CLK_M4_ETHERNET_CFG;       /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */
+  __I  uint32_t  CLK_M4_ETHERNET_STAT;      /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */
+  __IO uint32_t  CLK_M4_USB0_CFG;           /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */
+  __I  uint32_t  CLK_M4_USB0_STAT;          /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */
+  __IO uint32_t  CLK_M4_EMC_CFG;            /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */
+  __I  uint32_t  CLK_M4_EMC_STAT;           /*!< (@ 0x40051434) CLK_M4_EMC clock status register */
+  __IO uint32_t  CLK_M4_SDIO_CFG;           /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */
+  __I  uint32_t  CLK_M4_SDIO_STAT;          /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */
+  __IO uint32_t  CLK_M4_DMA_CFG;            /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */
+  __I  uint32_t  CLK_M4_DMA_STAT;           /*!< (@ 0x40051444) CLK_M4_DMA clock status register */
+  __IO uint32_t  CLK_M4_M4CORE_CFG;         /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */
+  __I  uint32_t  CLK_M4_M3CORE_STAT;        /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */
+  __I  uint32_t  RESERVED4[6];
+  __IO uint32_t  CLK_M4_SCT_CFG;            /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */
+  __I  uint32_t  CLK_M4_SCT_STAT;           /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */
+  __IO uint32_t  CLK_M4_USB1_CFG;           /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */
+  __I  uint32_t  CLK_M4_USB1_STAT;          /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */
+  __IO uint32_t  CLK_M4_EMCDIV_CFG;         /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */
+  __I  uint32_t  CLK_M4_EMCDIV_STAT;        /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  CLK_M4_M0APP_CFG;          /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */
+  __I  uint32_t  CLK_M4_M0APP_STAT;         /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */
+  __I  uint32_t  RESERVED6[26];
+  __IO uint32_t  CLK_M4_WWDT_CFG;           /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */
+  __I  uint32_t  CLK_M4_WWDT_STAT;          /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */
+  __IO uint32_t  CLK_M4_USART0_CFG;         /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */
+  __I  uint32_t  CLK_M4_USART0_STAT;        /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */
+  __IO uint32_t  CLK_M4_UART1_CFG;          /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */
+  __I  uint32_t  CLK_M4_UART1_STAT;         /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */
+  __IO uint32_t  CLK_M4_SSP0_CFG;           /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */
+  __I  uint32_t  CLK_M4_SSP0_STAT;          /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */
+  __IO uint32_t  CLK_M4_TIMER0_CFG;         /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER0_STAT;        /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */
+  __IO uint32_t  CLK_M4_TIMER1_CFG;         /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER1_STAT;        /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */
+  __IO uint32_t  CLK_M4_SCU_CFG;            /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */
+  __I  uint32_t  CLK_M4_SCU_STAT;           /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */
+  __IO uint32_t  CLK_M4_CREG_CFG;           /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */
+  __I  uint32_t  CLK_M4_CREG_STAT;          /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */
+  __I  uint32_t  RESERVED7[48];
+  __IO uint32_t  CLK_M4_RITIMER_CFG;        /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */
+  __I  uint32_t  CLK_M4_RITIMER_STAT;       /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */
+  __IO uint32_t  CLK_M4_USART2_CFG;         /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */
+  __I  uint32_t  CLK_M4_USART2_STAT;        /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */
+  __IO uint32_t  CLK_M4_USART3_CFG;         /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */
+  __I  uint32_t  CLK_M4_USART3_STAT;        /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */
+  __IO uint32_t  CLK_M4_TIMER2_CFG;         /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER2_STAT;        /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */
+  __IO uint32_t  CLK_M4_TIMER3_CFG;         /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */
+  __I  uint32_t  CLK_M4_TIMER3_STAT;        /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */
+  __IO uint32_t  CLK_M4_SSP1_CFG;           /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */
+  __I  uint32_t  CLK_M4_SSP1_STAT;          /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */
+  __IO uint32_t  CLK_M4_QEI_CFG;            /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */
+  __I  uint32_t  CLK_M4_QEI_STAT;           /*!< (@ 0x40051634) CLK_M4_QEI clock status register */
+  __I  uint32_t  RESERVED8[50];
+  __IO uint32_t  CLK_PERIPH_BUS_CFG;        /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */
+  __I  uint32_t  CLK_PERIPH_BUS_STAT;       /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  CLK_PERIPH_CORE_CFG;       /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */
+  __I  uint32_t  CLK_PERIPH_CORE_STAT;      /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */
+  __IO uint32_t  CLK_PERIPH_SGPIO_CFG;      /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */
+  __I  uint32_t  CLK_PERIPH_SGPIO_STAT;     /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */
+  __I  uint32_t  RESERVED10[56];
+  __IO uint32_t  CLK_USB0_CFG;              /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */
+  __I  uint32_t  CLK_USB0_STAT;             /*!< (@ 0x40051804) CLK_USB0 clock status register */
+  __I  uint32_t  RESERVED11[62];
+  __IO uint32_t  CLK_USB1_CFG;              /*!< (@ 0x40051900) CLK_USB1 clock configuration register */
+  __I  uint32_t  CLK_USB1_STAT;             /*!< (@ 0x40051904) CLK_USB1 clock status register */
+  __I  uint32_t  RESERVED12[62];
+  __IO uint32_t  CLK_SPI_CFG;               /*!< (@ 0x40051A00) CLK_SPI clock configuration register */
+  __I  uint32_t  CLK_SPI_STAT;              /*!< (@ 0x40051A04) CLK_SPI clock status register */
+  __I  uint32_t  RESERVED13[62];
+  __IO uint32_t  CLK_VADC_CFG;              /*!< (@ 0x40051B00) CLK_VADC clock configuration register */
+  __I  uint32_t  CLK_VADC_STAT;             /*!< (@ 0x40051B04) CLK_VADC clock status register */
+} LPC_CCU1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         CCU2                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7  (CCU2)
+  */
+
+typedef struct {                            /*!< (@ 0x40052000) CCU2 Structure         */
+  __IO uint32_t  PM;                        /*!< (@ 0x40052000) Power mode register    */
+  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40052004) CCU base clocks status register */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  CLK_APLL_CFG;              /*!< (@ 0x40052100) CLK_APLL clock configuration register */
+  __I  uint32_t  CLK_APLL_STAT;             /*!< (@ 0x40052104) CLK_APLL clock status register */
+  __I  uint32_t  RESERVED1[62];
+  __IO uint32_t  CLK_APB2_USART3_CFG;       /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */
+  __I  uint32_t  CLK_APB2_USART3_STAT;      /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */
+  __I  uint32_t  RESERVED2[62];
+  __IO uint32_t  CLK_APB2_USART2_CFG;       /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */
+  __I  uint32_t  CLK_APB2_USART2_STAT;      /*!< (@ 0x40052304) CLK_APB2_USART clock status register */
+  __I  uint32_t  RESERVED3[62];
+  __IO uint32_t  CLK_APB0_UART1_CFG;        /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */
+  __I  uint32_t  CLK_APB0_UART1_STAT;       /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */
+  __I  uint32_t  RESERVED4[62];
+  __IO uint32_t  CLK_APB0_USART0_CFG;       /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */
+  __I  uint32_t  CLK_APB0_USART0_STAT;      /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  CLK_APB2_SSP1_CFG;         /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */
+  __I  uint32_t  CLK_APB2_SSP1_STAT;        /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */
+  __I  uint32_t  RESERVED6[62];
+  __IO uint32_t  CLK_APB0_SSP0_CFG;         /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */
+  __I  uint32_t  CLK_APB0_SSP0_STAT;        /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */
+  __I  uint32_t  RESERVED7[62];
+  __IO uint32_t  CLK_SDIO_CFG;              /*!< (@ 0x40052800) CLK_SDIO clock configuration register */
+  __I  uint32_t  CLK_SDIO_STAT;             /*!< (@ 0x40052804) CLK_SDIO clock status register */
+} LPC_CCU2_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          RGU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13  (RGU)
+  */
+
+typedef struct {                            /*!< (@ 0x40053000) RGU Structure          */
+  __I  uint32_t  RESERVED0[64];
+  __O  uint32_t  RESET_CTRL0;               /*!< (@ 0x40053100) Reset control register 0 */
+  __O  uint32_t  RESET_CTRL1;               /*!< (@ 0x40053104) Reset control register 1 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  RESET_STATUS0;             /*!< (@ 0x40053110) Reset status register 0 */
+  __IO uint32_t  RESET_STATUS1;             /*!< (@ 0x40053114) Reset status register 1 */
+  __IO uint32_t  RESET_STATUS2;             /*!< (@ 0x40053118) Reset status register 2 */
+  __IO uint32_t  RESET_STATUS3;             /*!< (@ 0x4005311C) Reset status register 3 */
+  __I  uint32_t  RESERVED2[12];
+  __I  uint32_t  RESET_ACTIVE_STATUS0;      /*!< (@ 0x40053150) Reset active status register 0 */
+  __I  uint32_t  RESET_ACTIVE_STATUS1;      /*!< (@ 0x40053154) Reset active status register 1 */
+  __I  uint32_t  RESERVED3[170];
+  __IO uint32_t  RESET_EXT_STAT0;           /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */
+  __IO uint32_t  RESET_EXT_STAT1;           /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */
+  __IO uint32_t  RESET_EXT_STAT2;           /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  RESET_EXT_STAT4;           /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */
+  __IO uint32_t  RESET_EXT_STAT5;           /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  RESET_EXT_STAT8;           /*!< (@ 0x40053420) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT9;           /*!< (@ 0x40053424) Reset external status register */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  RESET_EXT_STAT13;          /*!< (@ 0x40053434) Reset external status register */
+  __I  uint32_t  RESERVED7[2];
+  __IO uint32_t  RESET_EXT_STAT16;          /*!< (@ 0x40053440) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT17;          /*!< (@ 0x40053444) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT18;          /*!< (@ 0x40053448) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT19;          /*!< (@ 0x4005344C) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT20;          /*!< (@ 0x40053450) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT21;          /*!< (@ 0x40053454) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT22;          /*!< (@ 0x40053458) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT23;          /*!< (@ 0x4005345C) Reset external status register */
+  __I  uint32_t  RESERVED8[4];
+  __IO uint32_t  RESET_EXT_STAT28;          /*!< (@ 0x40053470) Reset external status register */
+  __I  uint32_t  RESERVED9[3];
+  __IO uint32_t  RESET_EXT_STAT32;          /*!< (@ 0x40053480) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT33;          /*!< (@ 0x40053484) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT34;          /*!< (@ 0x40053488) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT35;          /*!< (@ 0x4005348C) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT36;          /*!< (@ 0x40053490) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT37;          /*!< (@ 0x40053494) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT38;          /*!< (@ 0x40053498) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT39;          /*!< (@ 0x4005349C) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT40;          /*!< (@ 0x400534A0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT41;          /*!< (@ 0x400534A4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT42;          /*!< (@ 0x400534A8) Reset external status register */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  RESET_EXT_STAT44;          /*!< (@ 0x400534B0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT45;          /*!< (@ 0x400534B4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT46;          /*!< (@ 0x400534B8) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT47;          /*!< (@ 0x400534BC) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT48;          /*!< (@ 0x400534C0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT49;          /*!< (@ 0x400534C4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT50;          /*!< (@ 0x400534C8) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT51;          /*!< (@ 0x400534CC) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT52;          /*!< (@ 0x400534D0) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT53;          /*!< (@ 0x400534D4) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT54;          /*!< (@ 0x400534D8) Reset external status register */
+  __IO uint32_t  RESET_EXT_STAT55;          /*!< (@ 0x400534DC) Reset external status register */
+} LPC_RGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         WWDT                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (WWDT)
+  */
+
+typedef struct {                            /*!< (@ 0x40080000) WWDT Structure         */
+  __IO uint32_t  MOD;                       /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+  __IO uint32_t  TC;                        /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */
+  __O  uint32_t  FEED;                      /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+  __I  uint32_t  TV;                        /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  WARNINT;                   /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+  __IO uint32_t  WINDOW;                    /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        USARTn                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (USARTn)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) USARTn Structure       */
+  
+  union {
+    __IO uint32_t  DLL;                     /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+    __O  uint32_t  THR;                     /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+    __I  uint32_t  RBR;                     /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+  } ;
+  
+  union {
+    __IO uint32_t IER;                      /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+    __IO uint32_t DLM;                      /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+  } ;
+  
+  union {
+    __O  uint32_t FCR;                      /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */
+    __I  uint32_t IIR;                      /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+  } ;
+  __IO uint32_t LCR;                        /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */
+  __I  uint32_t RESERVED0[1];
+  __I  uint32_t LSR;                        /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+  __I  uint32_t RESERVED1[1];
+  __IO uint32_t SCR;                        /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */
+  __IO uint32_t ACR;                        /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+  __IO uint32_t ICR;                        /*!< (@ 0x400xx024) IrDA control register (UART3 only) */
+  __IO uint32_t FDR;                        /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+  __IO uint32_t OSR;                        /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t HDEN;                       /*!< (@ 0x400xx03C) Half-duplex enable Register */
+  __I  uint32_t RESERVED3[1];
+  __IO uint32_t SCICTRL;                    /*!< (@ 0x400xx048) Smart card interface control register */
+  __IO uint32_t RS485CTRL;                  /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+  __IO uint32_t RS485DLY;                   /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */
+  __IO uint32_t SYNCCTRL;                   /*!< (@ 0x400xx058) Synchronous mode control register. */
+  __IO uint32_t TER;                        /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+} LPC_USARTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         UART1                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (UART1)
+  */
+
+typedef struct {                            /*!< (@ 0x40082000) UART1 Structure        */
+  
+  union {
+    __IO uint32_t  DLL;                     /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+    __O  uint32_t  THR;                     /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+    __I  uint32_t  RBR;                     /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+  } ;
+  
+  union {
+    __IO uint32_t  IER;                     /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */
+    __IO uint32_t  DLM;                     /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */
+  } ;
+  
+  union {
+    __O  uint32_t  FCR;                     /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */
+    __I  uint32_t  IIR;                     /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+  } ;
+  __IO uint32_t  LCR;                       /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */
+  __IO uint32_t  MCR;                       /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */
+  __I  uint32_t  LSR;                       /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+  __I  uint32_t  MSR;                       /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */
+  __IO uint32_t  SCR;                       /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */
+  __IO uint32_t  ACR;                       /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  FDR;                       /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  TER;                       /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+  __I  uint32_t  RESERVED2[6];
+  __IO uint32_t  RS485CTRL;                 /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+  __IO uint32_t  RS485ADRMATCH;             /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+  __IO uint32_t  RS485DLY;                  /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */
+  __I  uint32_t  FIFOLVL;                   /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs.  */
+} LPC_UART1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SSPn                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (SSP0)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) SSPn Structure         */
+  __IO uint32_t CR0;                        /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+  __IO uint32_t CR1;                        /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */
+  __IO uint32_t DR;                         /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+  __I  uint32_t SR;                         /*!< (@ 0x400xx00C) Status Register        */
+  __IO uint32_t CPSR;                       /*!< (@ 0x400xx010) Clock Prescale Register */
+  __IO uint32_t IMSC;                       /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */
+  __I  uint32_t RIS;                        /*!< (@ 0x400xx018) Raw Interrupt Status Register */
+  __I  uint32_t MIS;                        /*!< (@ 0x400xx01C) Masked Interrupt Status Register */
+  __O  uint32_t ICR;                        /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */
+  __IO uint32_t DMACR;                      /*!< (@ 0x400xx024) SSPn DMA control register */
+} LPC_SSPn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        TIMERn                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (TIMERn)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) TIMERn Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  __IO uint32_t MR[4];                      /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  __IO uint32_t CCR;                        /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  __IO uint32_t CR[4];                      /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+  __IO uint32_t EMR;                        /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+  __I  uint32_t  RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMERn_Type;
+
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          SCU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10  (SCU)
+  */
+
+typedef struct {                            /*!< (@ 0x40086000) SCU Structure          */
+  __IO uint32_t  SFSP0_0;                   /*!< (@ 0x40086000) Pin configuration register for pins P0 */
+  __IO uint32_t  SFSP0_1;                   /*!< (@ 0x40086004) Pin configuration register for pins P0 */
+  __I  uint32_t  RESERVED0[30];
+  __IO uint32_t  SFSP1_0;                   /*!< (@ 0x40086080) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_1;                   /*!< (@ 0x40086084) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_2;                   /*!< (@ 0x40086088) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_3;                   /*!< (@ 0x4008608C) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_4;                   /*!< (@ 0x40086090) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_5;                   /*!< (@ 0x40086094) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_6;                   /*!< (@ 0x40086098) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_7;                   /*!< (@ 0x4008609C) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_8;                   /*!< (@ 0x400860A0) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_9;                   /*!< (@ 0x400860A4) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_10;                  /*!< (@ 0x400860A8) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_11;                  /*!< (@ 0x400860AC) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_12;                  /*!< (@ 0x400860B0) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_13;                  /*!< (@ 0x400860B4) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_14;                  /*!< (@ 0x400860B8) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_15;                  /*!< (@ 0x400860BC) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_16;                  /*!< (@ 0x400860C0) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_17;                  /*!< (@ 0x400860C4) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_18;                  /*!< (@ 0x400860C8) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_19;                  /*!< (@ 0x400860CC) Pin configuration register for pins P1 */
+  __IO uint32_t  SFSP1_20;                  /*!< (@ 0x400860D0) Pin configuration register for pins P1 */
+  __I  uint32_t  RESERVED1[11];
+  __IO uint32_t  SFSP2_0;                   /*!< (@ 0x40086100) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_1;                   /*!< (@ 0x40086104) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_2;                   /*!< (@ 0x40086108) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_3;                   /*!< (@ 0x4008610C) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_4;                   /*!< (@ 0x40086110) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_5;                   /*!< (@ 0x40086114) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_6;                   /*!< (@ 0x40086118) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_7;                   /*!< (@ 0x4008611C) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_8;                   /*!< (@ 0x40086120) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_9;                   /*!< (@ 0x40086124) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_10;                  /*!< (@ 0x40086128) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_11;                  /*!< (@ 0x4008612C) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_12;                  /*!< (@ 0x40086130) Pin configuration register for pins P2 */
+  __IO uint32_t  SFSP2_13;                  /*!< (@ 0x40086134) Pin configuration register for pins P2 */
+  __I  uint32_t  RESERVED2[18];
+  __IO uint32_t  SFSP3_0;                   /*!< (@ 0x40086180) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_1;                   /*!< (@ 0x40086184) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_2;                   /*!< (@ 0x40086188) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_3;                   /*!< (@ 0x4008618C) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_4;                   /*!< (@ 0x40086190) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_5;                   /*!< (@ 0x40086194) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_6;                   /*!< (@ 0x40086198) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_7;                   /*!< (@ 0x4008619C) Pin configuration register for pins P3 */
+  __IO uint32_t  SFSP3_8;                   /*!< (@ 0x400861A0) Pin configuration register for pins P3 */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  SFSP4_0;                   /*!< (@ 0x40086200) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_1;                   /*!< (@ 0x40086204) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_2;                   /*!< (@ 0x40086208) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_3;                   /*!< (@ 0x4008620C) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_4;                   /*!< (@ 0x40086210) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_5;                   /*!< (@ 0x40086214) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_6;                   /*!< (@ 0x40086218) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_7;                   /*!< (@ 0x4008621C) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_8;                   /*!< (@ 0x40086220) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_9;                   /*!< (@ 0x40086224) Pin configuration register for pins P4 */
+  __IO uint32_t  SFSP4_10;                  /*!< (@ 0x40086228) Pin configuration register for pins P4 */
+  __I  uint32_t  RESERVED4[21];
+  __IO uint32_t  SFSP5_0;                   /*!< (@ 0x40086280) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_1;                   /*!< (@ 0x40086284) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_2;                   /*!< (@ 0x40086288) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_3;                   /*!< (@ 0x4008628C) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_4;                   /*!< (@ 0x40086290) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_5;                   /*!< (@ 0x40086294) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_6;                   /*!< (@ 0x40086298) Pin configuration register for pins P5 */
+  __IO uint32_t  SFSP5_7;                   /*!< (@ 0x4008629C) Pin configuration register for pins P5 */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  SFSP6_0;                   /*!< (@ 0x40086300) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_1;                   /*!< (@ 0x40086304) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_2;                   /*!< (@ 0x40086308) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_3;                   /*!< (@ 0x4008630C) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_4;                   /*!< (@ 0x40086310) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_5;                   /*!< (@ 0x40086314) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_6;                   /*!< (@ 0x40086318) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_7;                   /*!< (@ 0x4008631C) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_8;                   /*!< (@ 0x40086320) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_9;                   /*!< (@ 0x40086324) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_10;                  /*!< (@ 0x40086328) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_11;                  /*!< (@ 0x4008632C) Pin configuration register for pins P6 */
+  __IO uint32_t  SFSP6_12;                  /*!< (@ 0x40086330) Pin configuration register for pins P6 */
+  __I  uint32_t  RESERVED6[19];
+  __IO uint32_t  SFSP7_0;                   /*!< (@ 0x40086380) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_1;                   /*!< (@ 0x40086384) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_2;                   /*!< (@ 0x40086388) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_3;                   /*!< (@ 0x4008638C) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_4;                   /*!< (@ 0x40086390) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_5;                   /*!< (@ 0x40086394) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_6;                   /*!< (@ 0x40086398) Pin configuration register for pins P7 */
+  __IO uint32_t  SFSP7_7;                   /*!< (@ 0x4008639C) Pin configuration register for pins P7 */
+  __I  uint32_t  RESERVED7[24];
+  __IO uint32_t  SFSP8_0;                   /*!< (@ 0x40086400) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_1;                   /*!< (@ 0x40086404) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_2;                   /*!< (@ 0x40086408) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_3;                   /*!< (@ 0x4008640C) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_4;                   /*!< (@ 0x40086410) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_5;                   /*!< (@ 0x40086414) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_6;                   /*!< (@ 0x40086418) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_7;                   /*!< (@ 0x4008641C) Pin configuration register for pins P8 */
+  __IO uint32_t  SFSP8_8;                   /*!< (@ 0x40086420) Pin configuration register for pins P8 */
+  __I  uint32_t  RESERVED8[23];
+  __IO uint32_t  SFSP9_0;                   /*!< (@ 0x40086480) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_1;                   /*!< (@ 0x40086484) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_2;                   /*!< (@ 0x40086488) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_3;                   /*!< (@ 0x4008648C) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_4;                   /*!< (@ 0x40086490) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_5;                   /*!< (@ 0x40086494) Pin configuration register for pins P9 */
+  __IO uint32_t  SFSP9_6;                   /*!< (@ 0x40086498) Pin configuration register for pins P9 */
+  __I  uint32_t  RESERVED9[25];
+  __IO uint32_t  SFSPA_0;                   /*!< (@ 0x40086500) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_1;                   /*!< (@ 0x40086504) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_2;                   /*!< (@ 0x40086508) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_3;                   /*!< (@ 0x4008650C) Pin configuration register for pins PA */
+  __IO uint32_t  SFSPA_4;                   /*!< (@ 0x40086510) Pin configuration register for pins PA */
+  __I  uint32_t  RESERVED10[27];
+  __IO uint32_t  SFSPB_0;                   /*!< (@ 0x40086580) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_1;                   /*!< (@ 0x40086584) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_2;                   /*!< (@ 0x40086588) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_3;                   /*!< (@ 0x4008658C) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_4;                   /*!< (@ 0x40086590) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_5;                   /*!< (@ 0x40086594) Pin configuration register for pins PB */
+  __IO uint32_t  SFSPB_6;                   /*!< (@ 0x40086598) Pin configuration register for pins PB */
+  __I  uint32_t  RESERVED11[25];
+  __IO uint32_t  SFSPC_0;                   /*!< (@ 0x40086600) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_1;                   /*!< (@ 0x40086604) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_2;                   /*!< (@ 0x40086608) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_3;                   /*!< (@ 0x4008660C) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_4;                   /*!< (@ 0x40086610) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_5;                   /*!< (@ 0x40086614) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_6;                   /*!< (@ 0x40086618) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_7;                   /*!< (@ 0x4008661C) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_8;                   /*!< (@ 0x40086620) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_9;                   /*!< (@ 0x40086624) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_10;                  /*!< (@ 0x40086628) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_11;                  /*!< (@ 0x4008662C) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_12;                  /*!< (@ 0x40086630) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_13;                  /*!< (@ 0x40086634) Pin configuration register for pins PC */
+  __IO uint32_t  SFSPC_14;                  /*!< (@ 0x40086638) Pin configuration register for pins PC */
+  __I  uint32_t  RESERVED12[17];
+  __IO uint32_t  SFSPD_0;                   /*!< (@ 0x40086680) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_1;                   /*!< (@ 0x40086684) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_2;                   /*!< (@ 0x40086688) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_3;                   /*!< (@ 0x4008668C) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_4;                   /*!< (@ 0x40086690) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_5;                   /*!< (@ 0x40086694) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_6;                   /*!< (@ 0x40086698) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_7;                   /*!< (@ 0x4008669C) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_8;                   /*!< (@ 0x400866A0) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_9;                   /*!< (@ 0x400866A4) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_10;                  /*!< (@ 0x400866A8) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_11;                  /*!< (@ 0x400866AC) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_12;                  /*!< (@ 0x400866B0) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_13;                  /*!< (@ 0x400866B4) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_14;                  /*!< (@ 0x400866B8) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_15;                  /*!< (@ 0x400866BC) Pin configuration register for pins PD */
+  __IO uint32_t  SFSPD_16;                  /*!< (@ 0x400866C0) Pin configuration register for pins PD */
+  __I  uint32_t  RESERVED13[15];
+  __IO uint32_t  SFSPE_0;                   /*!< (@ 0x40086700) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_1;                   /*!< (@ 0x40086704) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_2;                   /*!< (@ 0x40086708) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_3;                   /*!< (@ 0x4008670C) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_4;                   /*!< (@ 0x40086710) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_5;                   /*!< (@ 0x40086714) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_6;                   /*!< (@ 0x40086718) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_7;                   /*!< (@ 0x4008671C) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_8;                   /*!< (@ 0x40086720) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_9;                   /*!< (@ 0x40086724) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_10;                  /*!< (@ 0x40086728) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_11;                  /*!< (@ 0x4008672C) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_12;                  /*!< (@ 0x40086730) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_13;                  /*!< (@ 0x40086734) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_14;                  /*!< (@ 0x40086738) Pin configuration register for pins PE */
+  __IO uint32_t  SFSPE_15;                  /*!< (@ 0x4008673C) Pin configuration register for pins PE */
+  __I  uint32_t  RESERVED14[16];
+  __IO uint32_t  SFSPF_0;                   /*!< (@ 0x40086780) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_1;                   /*!< (@ 0x40086784) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_2;                   /*!< (@ 0x40086788) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_3;                   /*!< (@ 0x4008678C) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_4;                   /*!< (@ 0x40086790) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_5;                   /*!< (@ 0x40086794) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_6;                   /*!< (@ 0x40086798) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_7;                   /*!< (@ 0x4008679C) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_8;                   /*!< (@ 0x400867A0) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_9;                   /*!< (@ 0x400867A4) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_10;                  /*!< (@ 0x400867A8) Pin configuration register for pins PF */
+  __IO uint32_t  SFSPF_11;                  /*!< (@ 0x400867AC) Pin configuration register for pins PF */
+  __I  uint32_t  RESERVED15[276];
+  __IO uint32_t  SFSCLK_0;                  /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */
+  __IO uint32_t  SFSCLK_1;                  /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */
+  __IO uint32_t  SFSCLK_2;                  /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */
+  __IO uint32_t  SFSCLK_3;                  /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */
+  __I  uint32_t  RESERVED16[28];
+  __IO uint32_t  SFSUSB;                    /*!< (@ 0x40086C80) Pin configuration register for */
+  __IO uint32_t  SFSI2C0;                   /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */
+  __IO uint32_t  ENAIO0;                    /*!< (@ 0x40086C88) ADC0 function select register */
+  __IO uint32_t  ENAIO1;                    /*!< (@ 0x40086C8C) ADC1 function select register */
+  __IO uint32_t  ENAIO2;                    /*!< (@ 0x40086C90) Analog function select register */
+  __I  uint32_t  RESERVED17[27];
+  __IO uint32_t  EMCDELAYCLK;               /*!< (@ 0x40086D00) EMC clock delay register */
+  __I  uint32_t  RESERVED18[63];
+  __IO uint32_t  PINTSEL0;                  /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */
+  __IO uint32_t  PINTSEL1;                  /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                     GPIO_PIN_INT                                     -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief GPIO pin interrupt (GPIO_PIN_INT)
+  */
+
+typedef struct {                            /*!< (@ 0x40087000) GPIO_PIN_INT Structure */
+  __IO uint32_t  ISEL;                      /*!< (@ 0x40087000) Pin Interrupt Mode register */
+  __IO uint32_t  IENR;                      /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */
+  __O  uint32_t  SIENR;                     /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */
+  __O  uint32_t  CIENR;                     /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */
+  __IO uint32_t  IENF;                      /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */
+  __O  uint32_t  SIENF;                     /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+  __O  uint32_t  CIENF;                     /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+  __IO uint32_t  RISE;                      /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */
+  __IO uint32_t  FALL;                      /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */
+  __IO uint32_t  IST;                       /*!< (@ 0x40087024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                    GPIO_GROUP_INTn                                   -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
+  */
+
+typedef struct {                            /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40088000) GPIO grouped interrupt control register */
+  __I  uint32_t  RESERVED0[7];
+  __IO uint32_t  PORT_POL0;                 /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL1;                 /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL2;                 /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL3;                 /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL4;                 /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL5;                 /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL6;                 /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_POL7;                 /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */
+  __IO uint32_t  PORT_ENA0;                 /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA1;                 /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA2;                 /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA3;                 /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA4;                 /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA5;                 /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA6;                 /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */
+  __IO uint32_t  PORT_ENA7;                 /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */
+} LPC_GPIO_GROUP_INTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         MCPWM                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7  (MCPWM)
+  */
+
+typedef struct {                            /*!< (@ 0x400A0000) MCPWM Structure        */
+  __I  uint32_t  CON;                       /*!< (@ 0x400A0000) PWM Control read address */
+  __O  uint32_t  CON_SET;                   /*!< (@ 0x400A0004) PWM Control set address */
+  __O  uint32_t  CON_CLR;                   /*!< (@ 0x400A0008) PWM Control clear address */
+  __I  uint32_t  CAPCON;                    /*!< (@ 0x400A000C) Capture Control read address */
+  __O  uint32_t  CAPCON_SET;                /*!< (@ 0x400A0010) Capture Control set address */
+  __O  uint32_t  CAPCON_CLR;                /*!< (@ 0x400A0014) Event Control clear address */
+  __IO uint32_t TC[3];                      /*!< (@ 0x400A0018) Timer Counter register */
+  __IO uint32_t LIM[3];                     /*!< (@ 0x400A0024) Limit register         */
+  __IO uint32_t MAT[3];                     /*!< (@ 0x400A0030) Match register         */
+  __IO uint32_t  DT;                        /*!< (@ 0x400A003C) Dead time register     */
+  __IO uint32_t  CCP;                       /*!< (@ 0x400A0040) Communication Pattern register */
+  __I  uint32_t CAP[3];                     /*!< (@ 0x400A0044) Capture register       */
+  __I  uint32_t  INTEN;                     /*!< (@ 0x400A0050) Interrupt Enable read address */
+  __O  uint32_t  INTEN_SET;                 /*!< (@ 0x400A0054) Interrupt Enable set address */
+  __O  uint32_t  INTEN_CLR;                 /*!< (@ 0x400A0058) Interrupt Enable clear address */
+  __I  uint32_t  CNTCON;                    /*!< (@ 0x400A005C) Count Control read address */
+  __O  uint32_t  CNTCON_SET;                /*!< (@ 0x400A0060) Count Control set address */
+  __O  uint32_t  CNTCON_CLR;                /*!< (@ 0x400A0064) Count Control clear address */
+  __I  uint32_t  INTF;                      /*!< (@ 0x400A0068) Interrupt flags read address */
+  __O  uint32_t  INTF_SET;                  /*!< (@ 0x400A006C) Interrupt flags set address */
+  __O  uint32_t  INTF_CLR;                  /*!< (@ 0x400A0070) Interrupt flags clear address */
+  __O  uint32_t  CAP_CLR;                   /*!< (@ 0x400A0074) Capture clear address  */
+} LPC_MCPWM_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         I2C0                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Cn)
+  */
+
+typedef struct {                            /*!< (@ 0x400xx000) I2C0 Structure         */
+  __IO uint32_t CONSET;                     /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+  __I  uint32_t STAT;                       /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+  __IO uint32_t DAT;                        /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+  __IO uint32_t ADR0;                       /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t SCLH;                       /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+  __IO uint32_t SCLL;                       /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+  __O  uint32_t CONCLR;                     /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+  __IO uint32_t MMCTRL;                     /*!< (@ 0x400xx01C) Monitor mode control register. */
+  __IO uint32_t ADR1;                       /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t ADR2;                       /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t ADR3;                       /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+  __IO uint32_t MASK[4];                    /*!< (@ 0x400xx030) I2C Slave address mask register */
+} LPC_I2Cn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         I2Sn                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Sn)
+    0x400A2000 / 0x400A3000
+  */
+
+typedef struct {                            /*!< (@ 0x400Ax000) I2S Structure         */
+  __IO uint32_t DAO;                        /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */
+  __IO uint32_t DAI;                        /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */
+  __O  uint32_t TXFIFO;                     /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */
+  __I  uint32_t RXFIFO;                     /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */
+  __I  uint32_t STATE;                      /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */
+  __IO uint32_t DMA1;                       /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */
+  __IO uint32_t DMA2;                       /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */
+  __IO uint32_t IRQ;                        /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */
+  __IO uint32_t TXRATE;                     /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+  __IO uint32_t RXRATE;                     /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+  __IO uint32_t TXBITRATE;                  /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */
+  __IO uint32_t RXBITRATE;                  /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */
+  __IO uint32_t TXMODE;                     /*!< (@ 0x400Ax030) I2S Transmit mode control. */
+  __IO uint32_t RXMODE;                     /*!< (@ 0x400Ax034) I2S Receive mode control. */
+} LPC_I2Sn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        C_CANn                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7  (C_CANn)
+    0x400A4000 / 0x400E2000
+  */
+
+typedef struct {                            /*!< (@ 0x400E2000) C_CAN Structure       */
+  __IO uint32_t CNTL;                       /*!< (@ 0x400E2000) CAN control            */
+  __IO uint32_t STAT;                       /*!< (@ 0x400E2004) Status register        */
+  __I  uint32_t EC;                         /*!< (@ 0x400E2008) Error counter          */
+  __IO uint32_t BT;                         /*!< (@ 0x400E200C) Bit timing register    */
+  __I  uint32_t INT;                        /*!< (@ 0x400E2010) Interrupt register     */
+  __IO uint32_t TEST;                       /*!< (@ 0x400E2014) Test register          */
+  __IO uint32_t BRPE;                       /*!< (@ 0x400E2018) Baud rate prescaler extension register */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t IF1_CMDREQ;                 /*!< (@ 0x400E2020) Message interface command request  */
+  
+  union {
+    __IO uint32_t IF1_CMDMSK_R;             /*!< (@ 0x400E2024) Message interface command mask (read direction) */
+    __IO uint32_t IF1_CMDMSK_W;             /*!< (@ 0x400E2024) Message interface command mask (write direction) */
+  } ;
+  __IO uint32_t IF1_MSK1;                   /*!< (@ 0x400E2028) Message interface mask 1 */
+  __IO uint32_t IF1_MSK2;                   /*!< (@ 0x400E202C) Message interface 1 mask 2 */
+  __IO uint32_t IF1_ARB1;                   /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */
+  __IO uint32_t IF1_ARB2;                   /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */
+  __IO uint32_t IF1_MCTRL;                  /*!< (@ 0x400E2038) Message interface 1 message control */
+  __IO uint32_t IF1_DA1;                    /*!< (@ 0x400E203C) Message interface data A1 */
+  __IO uint32_t IF1_DA2;                    /*!< (@ 0x400E2040) Message interface 1 data A2 */
+  __IO uint32_t IF1_DB1;                    /*!< (@ 0x400E2044) Message interface 1 data B1 */
+  __IO uint32_t IF1_DB2;                    /*!< (@ 0x400E2048) Message interface 1 data B2 */
+  __I  uint32_t  RESERVED1[13];
+  __IO uint32_t IF2_CMDREQ;                 /*!< (@ 0x400E2080) Message interface command request  */
+  
+  union {
+    __IO uint32_t IF2_CMDMSK_R;             /*!< (@ 0x400E2084) Message interface command mask (read direction) */
+    __IO uint32_t IF2_CMDMSK_W;             /*!< (@ 0x400E2084) Message interface command mask (write direction) */
+  } ;
+  __IO uint32_t IF2_MSK1;                   /*!< (@ 0x400E2088) Message interface mask 1 */
+  __IO uint32_t IF2_MSK2;                   /*!< (@ 0x400E208C) Message interface 1 mask 2 */
+  __IO uint32_t IF2_ARB1;                   /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */
+  __IO uint32_t IF2_ARB2;                   /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */
+  __IO uint32_t IF2_MCTRL;                  /*!< (@ 0x400E2098) Message interface 1 message control */
+  __IO uint32_t IF2_DA1;                    /*!< (@ 0x400E209C) Message interface data A1 */
+  __IO uint32_t IF2_DA2;                    /*!< (@ 0x400E20A0) Message interface 1 data A2 */
+  __IO uint32_t IF2_DB1;                    /*!< (@ 0x400E20A4) Message interface 1 data B1 */
+  __IO uint32_t IF2_DB2;                    /*!< (@ 0x400E20A8) Message interface 1 data B2 */
+  __I  uint32_t  RESERVED2[21];
+  __I  uint32_t TXREQ1;                     /*!< (@ 0x400E2100) Transmission request 1 */
+  __I  uint32_t TXREQ2;                     /*!< (@ 0x400E2104) Transmission request 2 */
+  __I  uint32_t  RESERVED3[6];
+  __I  uint32_t ND1;                        /*!< (@ 0x400E2120) New data 1             */
+  __I  uint32_t ND2;                        /*!< (@ 0x400E2124) New data 2             */
+  __I  uint32_t  RESERVED4[6];
+  __I  uint32_t IR1;                        /*!< (@ 0x400E2140) Interrupt pending 1    */
+  __I  uint32_t IR2;                        /*!< (@ 0x400E2144) Interrupt pending 2    */
+  __I  uint32_t  RESERVED5[6];
+  __I  uint32_t MSGV1;                      /*!< (@ 0x400E2160) Message valid 1        */
+  __I  uint32_t MSGV2;                      /*!< (@ 0x400E2164) Message valid 2        */
+  __I  uint32_t  RESERVED6[6];
+  __IO uint32_t CLKDIV;                     /*!< (@ 0x400E2180) CAN clock divider register */
+} LPC_C_CANn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        RITIMER                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (RITIMER)
+  */
+
+typedef struct {                            /*!< (@ 0x400C0000) RITIMER Structure      */
+  __IO uint32_t  COMPVAL;                   /*!< (@ 0x400C0000) Compare register       */
+  __IO uint32_t  MASK;                      /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x400C0008) Control register.      */
+  __IO uint32_t  COUNTER;                   /*!< (@ 0x400C000C) 32-bit counter         */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          QEI                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7  (QEI)
+  */
+
+typedef struct {                            /*!< (@ 0x400C6000) QEI Structure          */
+  __O  uint32_t  CON;                       /*!< (@ 0x400C6000) Control register       */
+  __I  uint32_t  STAT;                      /*!< (@ 0x400C6004) Encoder status register */
+  __IO uint32_t  CONF;                      /*!< (@ 0x400C6008) Configuration register */
+  __I  uint32_t  POS;                       /*!< (@ 0x400C600C) Position register      */
+  __IO uint32_t  MAXPOS;                    /*!< (@ 0x400C6010) Maximum position register */
+  __IO uint32_t  CMPOS0;                    /*!< (@ 0x400C6014) position compare register 0 */
+  __IO uint32_t  CMPOS1;                    /*!< (@ 0x400C6018) position compare register 1 */
+  __IO uint32_t  CMPOS2;                    /*!< (@ 0x400C601C) position compare register 2 */
+  __I  uint32_t  INXCNT;                    /*!< (@ 0x400C6020) Index count register   */
+  __IO uint32_t  INXCMP0;                   /*!< (@ 0x400C6024) Index compare register 0 */
+  __IO uint32_t  LOAD;                      /*!< (@ 0x400C6028) Velocity timer reload register */
+  __I  uint32_t  TIME;                      /*!< (@ 0x400C602C) Velocity timer register */
+  __I  uint32_t  VEL;                       /*!< (@ 0x400C6030) Velocity counter register */
+  __I  uint32_t  CAP;                       /*!< (@ 0x400C6034) Velocity capture register */
+  __IO uint32_t  VELCOMP;                   /*!< (@ 0x400C6038) Velocity compare register */
+  __IO uint32_t  FILTERPHA;                 /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */
+  __IO uint32_t  FILTERPHB;                 /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */
+  __IO uint32_t  FILTERINX;                 /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */
+  __IO uint32_t  WINDOW;                    /*!< (@ 0x400C6048) Index acceptance window register */
+  __IO uint32_t  INXCMP1;                   /*!< (@ 0x400C604C) Index compare register 1 */
+  __IO uint32_t  INXCMP2;                   /*!< (@ 0x400C6050) Index compare register 2 */
+  __I  uint32_t  RESERVED0[993];
+  __O  uint32_t  IEC;                       /*!< (@ 0x400C6FD8) Interrupt enable clear register */
+  __O  uint32_t  IES;                       /*!< (@ 0x400C6FDC) Interrupt enable set register */
+  __I  uint32_t  INTSTAT;                   /*!< (@ 0x400C6FE0) Interrupt status register */
+  __I  uint32_t  IE;                        /*!< (@ 0x400C6FE4) Interrupt enable register */
+  __O  uint32_t  CLR;                       /*!< (@ 0x400C6FE8) Interrupt status clear register */
+  __O  uint32_t  SET;                       /*!< (@ 0x400C6FEC) Interrupt status set register */
+} LPC_QEI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         GIMA                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3  (GIMA)
+  */
+
+typedef struct {                            /*!< (@ 0x400C7000) GIMA Structure         */
+  __IO uint32_t  CAP0_0_IN;                 /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+  __IO uint32_t  CAP0_1_IN;                 /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+  __IO uint32_t  CAP0_2_IN;                 /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+  __IO uint32_t  CAP0_3_IN;                 /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+  __IO uint32_t  CAP1_0_IN;                 /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+  __IO uint32_t  CAP1_1_IN;                 /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+  __IO uint32_t  CAP1_2_IN;                 /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+  __IO uint32_t  CAP1_3_IN;                 /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+  __IO uint32_t  CAP2_0_IN;                 /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+  __IO uint32_t  CAP2_1_IN;                 /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+  __IO uint32_t  CAP2_2_IN;                 /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+  __IO uint32_t  CAP2_3_IN;                 /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+  __IO uint32_t  CAP3_0_IN;                 /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+  __IO uint32_t  CAP3_1_IN;                 /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+  __IO uint32_t  CAP3_2_IN;                 /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+  __IO uint32_t  CAP3_3_IN;                 /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+  __IO uint32_t  CTIN_0_IN;                 /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+  __IO uint32_t  CTIN_1_IN;                 /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+  __IO uint32_t  CTIN_2_IN;                 /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+  __IO uint32_t  CTIN_3_IN;                 /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+  __IO uint32_t  CTIN_4_IN;                 /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+  __IO uint32_t  CTIN_5_IN;                 /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+  __IO uint32_t  CTIN_6_IN;                 /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+  __IO uint32_t  CTIN_7_IN;                 /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+  __IO uint32_t  VADC_TRIGGER_IN;           /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */
+  __IO uint32_t  EVENTROUTER_13_IN;         /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */
+  __IO uint32_t  EVENTROUTER_14_IN;         /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */
+  __IO uint32_t  EVENTROUTER_16_IN;         /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */
+  __IO uint32_t  ADCSTART0_IN;              /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */
+  __IO uint32_t  ADCSTART1_IN;              /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */
+} LPC_GIMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          DAC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7  (DAC)
+  */
+
+typedef struct {                            /*!< (@ 0x400E1000) DAC Structure          */
+  __IO uint32_t  CR;                        /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x400E1004) DAC control register.  */
+  __IO uint32_t  CNTVAL;                    /*!< (@ 0x400E1008) DAC counter value register. */
+} LPC_DAC_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         ADCn                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7  (ADCn)
+    0x400E3000 / 0x400E4000
+  */
+
+typedef struct {                            /*!< (@ 0x400Ex000) ADCn Structure         */
+  __IO uint32_t CR;                         /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+  __I  uint32_t GDR;                        /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t INTEN;                      /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+  __I  uint32_t DR[8];                      /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+  __I  uint32_t STAT;                       /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADCn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       GPIO_PORT                                      -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief GPIO port  (GPIO_PORT)
+  */
+
+typedef struct {                            /*!< (@ 0x400F4000) GPIO_PORT Structure    */
+  __IO uint8_t B[256];                      /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
+  __I  uint32_t  RESERVED0[960];
+  __IO uint32_t W[256];                     /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */
+  __I  uint32_t  RESERVED1[768];
+  __IO uint32_t DIR[8];                     /*!< (@ 0x400F6000) Direction registers port n */
+  __I  uint32_t  RESERVED2[24];
+  __IO uint32_t MASK[8];                    /*!< (@ 0x400F6080) Mask register port n   */
+  __I  uint32_t  RESERVED3[24];
+  __IO uint32_t PIN[8];                     /*!< (@ 0x400F6100) Portpin register port n */
+  __I  uint32_t  RESERVED4[24];
+  __IO uint32_t MPIN[8];                    /*!< (@ 0x400F6180) Masked port register port n */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t SET[8];                     /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */
+  __I  uint32_t  RESERVED6[24];
+  __O  uint32_t CLR[8];                     /*!< (@ 0x400F6280) Clear port n           */
+  __I  uint32_t  RESERVED7[24];
+  __O  uint32_t NOT[8];                     /*!< (@ 0x400F6300) Toggle port n          */
+} LPC_GPIO_PORT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          SPI                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3  (SPI)
+  */
+
+typedef struct {                            /*!< (@ 0x40100000) SPI Structure          */
+  __IO uint32_t  CR;                        /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */
+  __I  uint32_t  SR;                        /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */
+  __IO uint32_t  DR;                        /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
+  __IO uint32_t  CCR;                       /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+  __IO uint32_t  TCR;                       /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */
+  __IO uint32_t  TSR;                       /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  INT;                       /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+} LPC_SPI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SGPIO                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3  (SGPIO)
+  */
+
+typedef struct {                            /*!< (@ 0x40101000) SGPIO Structure        */
+  __IO uint32_t  OUT_MUX_CFG[16];              /*!< (@ 0x40101000) Pin multiplexer configurationregisters. */
+  __IO uint32_t  SGPIO_MUX_CFG[16];            /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */
+  __IO uint32_t  SLICE_MUX_CFG[16];            /*!< (@ 0x40101080) Slice multiplexer configuration registers. */
+  __IO uint32_t  REG[16];                      /*!< (@ 0x401010C0) Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
+  __IO uint32_t  REG_SS[16];                   /*!< (@ 0x40101100) Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
+  __IO uint32_t  PRESET[16];                   /*!< (@ 0x40101140) Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
+  __IO uint32_t  COUNT[16];                    /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */
+  __IO uint32_t  POS[16];                      /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 */
+  __IO uint32_t  MASK_A;                    /*!< (@ 0x40101200) Mask for pattern match function of slice A */
+  __IO uint32_t  MASK_H;                    /*!< (@ 0x40101204) Mask for pattern match function of slice H */
+  __IO uint32_t  MASK_I;                    /*!< (@ 0x40101208) Mask for pattern match function of slice I */
+  __IO uint32_t  MASK_P;                    /*!< (@ 0x4010120C) Mask for pattern match function of slice P */
+  __I  uint32_t  GPIO_INREG;                /*!< (@ 0x40101210) GPIO input status register */
+  __IO uint32_t  GPIO_OUTREG;               /*!< (@ 0x40101214) GPIO output control register */
+  __IO uint32_t  GPIO_OENREG;               /*!< (@ 0x40101218) GPIO OE control register */
+  __IO uint32_t  CTRL_ENABLED;              /*!< (@ 0x4010121C) Enables the slice COUNT counter */
+  __IO uint32_t  CTRL_DISABLED;             /*!< (@ 0x40101220) Disables the slice COUNT counter */
+  __I  uint32_t  RESERVED0[823];
+  __O  uint32_t  CLR_EN_0;                  /*!< (@ 0x40101F00) Shift clock interrupt clear mask */
+  __O  uint32_t  SET_EN_0;                  /*!< (@ 0x40101F04) Shift clock interrupt set mask */
+  __I  uint32_t  ENABLE_0;                  /*!< (@ 0x40101F08) Shift clock interrupt enable */
+  __I  uint32_t  STATUS_0;                  /*!< (@ 0x40101F0C) Shift clock interrupt status */
+  __O  uint32_t  CTR_STATUS_0;              /*!< (@ 0x40101F10) Shift clock interrupt clear status */
+  __O  uint32_t  SET_STATUS_0;              /*!< (@ 0x40101F14) Shift clock interrupt set status */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  CLR_EN_1;                  /*!< (@ 0x40101F20) Capture clock interrupt clear mask */
+  __O  uint32_t  SET_EN_1;                  /*!< (@ 0x40101F24) Capture clock interrupt set mask */
+  __I  uint32_t  ENABLE_1;                  /*!< (@ 0x40101F28) Capture clock interrupt enable */
+  __I  uint32_t  STATUS_1;                  /*!< (@ 0x40101F2C) Capture clock interrupt status */
+  __O  uint32_t  CTR_STATUS_1;              /*!< (@ 0x40101F30) Capture clock interrupt clear status */
+  __O  uint32_t  SET_STATUS_1;              /*!< (@ 0x40101F34) Capture clock interrupt set status */
+  __I  uint32_t  RESERVED2[2];
+  __O  uint32_t  CLR_EN_2;                  /*!< (@ 0x40101F40) Pattern match interrupt clear mask */
+  __O  uint32_t  SET_EN_2;                  /*!< (@ 0x40101F44) Pattern match interrupt set mask */
+  __I  uint32_t  ENABLE_2;                  /*!< (@ 0x40101F48) Pattern match interrupt enable */
+  __I  uint32_t  STATUS_2;                  /*!< (@ 0x40101F4C) Pattern match interrupt status */
+  __O  uint32_t  CTR_STATUS_2;              /*!< (@ 0x40101F50) Pattern match interrupt clear status */
+  __O  uint32_t  SET_STATUS_2;              /*!< (@ 0x40101F54) Pattern match interrupt set status */
+  __I  uint32_t  RESERVED3[2];
+  __O  uint32_t  CLR_EN_3;                  /*!< (@ 0x40101F60) Input interrupt clear mask */
+  __O  uint32_t  SET_EN_3;                  /*!< (@ 0x40101F64) Input bit match interrupt set mask */
+  __I  uint32_t  ENABLE_3;                  /*!< (@ 0x40101F68) Input bit match interrupt enable */
+  __I  uint32_t  STATUS_3;                  /*!< (@ 0x40101F6C) Input bit match interrupt status */
+  __O  uint32_t  CTR_STATUS_3;              /*!< (@ 0x40101F70) Input bit match interrupt clear status */
+  __O  uint32_t  SET_STATUS_3;              /*!< (@ 0x40101F74) Shift clock interrupt set status */
+} LPC_SGPIO_Type;
+
+
+
+/********************************************
+** End of section using anonymous unions   **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma pop
+#else
+  #error Not supported compiler type
+#endif
+
+
+#ifdef CMSIS_BITPOSITIONS
+// ------------------------------------------------------------------------------------------------
+// -----                                  SCT Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  SCT_CONFIG  -------------------------------------------
+#define SCT_CONFIG_UNIFY_Pos                                  0                                                         /*!< SCT CONFIG: UNIFY Position          */
+#define SCT_CONFIG_UNIFY_Msk                                  (0x01UL << SCT_CONFIG_UNIFY_Pos)                          /*!< SCT CONFIG: UNIFY Mask              */
+#define SCT_CONFIG_CLKMODE_Pos                                1                                                         /*!< SCT CONFIG: CLKMODE Position        */
+#define SCT_CONFIG_CLKMODE_Msk                                (0x03UL << SCT_CONFIG_CLKMODE_Pos)                        /*!< SCT CONFIG: CLKMODE Mask            */
+#define SCT_CONFIG_CLKSEL_Pos                                 3                                                         /*!< SCT CONFIG: CLKSEL Position         */
+#define SCT_CONFIG_CLKSEL_Msk                                 (0x0fUL << SCT_CONFIG_CLKSEL_Pos)                         /*!< SCT CONFIG: CLKSEL Mask             */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Pos                    7                                                         /*!< SCT CONFIG: NORELAODL_NORELOADU Position */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Msk                    (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos)            /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */
+#define SCT_CONFIG_NORELOADH_Pos                              8                                                         /*!< SCT CONFIG: NORELOADH Position      */
+#define SCT_CONFIG_NORELOADH_Msk                              (0x01UL << SCT_CONFIG_NORELOADH_Pos)                      /*!< SCT CONFIG: NORELOADH Mask          */
+#define SCT_CONFIG_INSYNCn_Pos                                9                                                         /*!< SCT CONFIG: INSYNCn Position        */
+#define SCT_CONFIG_INSYNCn_Msk                                (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos)                  /*!< SCT CONFIG: INSYNCn Mask            */
+
+// ----------------------------------------  SCT_CTRL  --------------------------------------------
+#define SCT_CTRL_DOWN_L_Pos                                   0                                                         /*!< SCT CTRL: DOWN_L Position           */
+#define SCT_CTRL_DOWN_L_Msk                                   (0x01UL << SCT_CTRL_DOWN_L_Pos)                           /*!< SCT CTRL: DOWN_L Mask               */
+#define SCT_CTRL_STOP_L_Pos                                   1                                                         /*!< SCT CTRL: STOP_L Position           */
+#define SCT_CTRL_STOP_L_Msk                                   (0x01UL << SCT_CTRL_STOP_L_Pos)                           /*!< SCT CTRL: STOP_L Mask               */
+#define SCT_CTRL_HALT_L_Pos                                   2                                                         /*!< SCT CTRL: HALT_L Position           */
+#define SCT_CTRL_HALT_L_Msk                                   (0x01UL << SCT_CTRL_HALT_L_Pos)                           /*!< SCT CTRL: HALT_L Mask               */
+#define SCT_CTRL_CLRCTR_L_Pos                                 3                                                         /*!< SCT CTRL: CLRCTR_L Position         */
+#define SCT_CTRL_CLRCTR_L_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_L_Pos)                         /*!< SCT CTRL: CLRCTR_L Mask             */
+#define SCT_CTRL_BIDIR_L_Pos                                  4                                                         /*!< SCT CTRL: BIDIR_L Position          */
+#define SCT_CTRL_BIDIR_L_Msk                                  (0x01UL << SCT_CTRL_BIDIR_L_Pos)                          /*!< SCT CTRL: BIDIR_L Mask              */
+#define SCT_CTRL_PRE_L_Pos                                    5                                                         /*!< SCT CTRL: PRE_L Position            */
+#define SCT_CTRL_PRE_L_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_L_Pos)                      /*!< SCT CTRL: PRE_L Mask                */
+#define SCT_CTRL_DOWN_H_Pos                                   16                                                        /*!< SCT CTRL: DOWN_H Position           */
+#define SCT_CTRL_DOWN_H_Msk                                   (0x01UL << SCT_CTRL_DOWN_H_Pos)                           /*!< SCT CTRL: DOWN_H Mask               */
+#define SCT_CTRL_STOP_H_Pos                                   17                                                        /*!< SCT CTRL: STOP_H Position           */
+#define SCT_CTRL_STOP_H_Msk                                   (0x01UL << SCT_CTRL_STOP_H_Pos)                           /*!< SCT CTRL: STOP_H Mask               */
+#define SCT_CTRL_HALT_H_Pos                                   18                                                        /*!< SCT CTRL: HALT_H Position           */
+#define SCT_CTRL_HALT_H_Msk                                   (0x01UL << SCT_CTRL_HALT_H_Pos)                           /*!< SCT CTRL: HALT_H Mask               */
+#define SCT_CTRL_CLRCTR_H_Pos                                 19                                                        /*!< SCT CTRL: CLRCTR_H Position         */
+#define SCT_CTRL_CLRCTR_H_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_H_Pos)                         /*!< SCT CTRL: CLRCTR_H Mask             */
+#define SCT_CTRL_BIDIR_H_Pos                                  20                                                        /*!< SCT CTRL: BIDIR_H Position          */
+#define SCT_CTRL_BIDIR_H_Msk                                  (0x01UL << SCT_CTRL_BIDIR_H_Pos)                          /*!< SCT CTRL: BIDIR_H Mask              */
+#define SCT_CTRL_PRE_H_Pos                                    21                                                        /*!< SCT CTRL: PRE_H Position            */
+#define SCT_CTRL_PRE_H_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_H_Pos)                      /*!< SCT CTRL: PRE_H Mask                */
+
+// ----------------------------------------  SCT_LIMIT  -------------------------------------------
+#define SCT_LIMIT_LIMMSK_L_Pos                                0                                                         /*!< SCT LIMIT: LIMMSK_L Position        */
+#define SCT_LIMIT_LIMMSK_L_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos)                  /*!< SCT LIMIT: LIMMSK_L Mask            */
+#define SCT_LIMIT_LIMMSK_H_Pos                                16                                                        /*!< SCT LIMIT: LIMMSK_H Position        */
+#define SCT_LIMIT_LIMMSK_H_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos)                  /*!< SCT LIMIT: LIMMSK_H Mask            */
+
+// ----------------------------------------  SCT_HALT  --------------------------------------------
+#define SCT_HALT_HALTMSK_L_Pos                                0                                                         /*!< SCT HALT: HALTMSK_L Position        */
+#define SCT_HALT_HALTMSK_L_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos)                  /*!< SCT HALT: HALTMSK_L Mask            */
+#define SCT_HALT_HALTMSK_H_Pos                                16                                                        /*!< SCT HALT: HALTMSK_H Position        */
+#define SCT_HALT_HALTMSK_H_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos)                  /*!< SCT HALT: HALTMSK_H Mask            */
+
+// ----------------------------------------  SCT_STOP  --------------------------------------------
+#define SCT_STOP_STOPMSK_L_Pos                                0                                                         /*!< SCT STOP: STOPMSK_L Position        */
+#define SCT_STOP_STOPMSK_L_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos)                  /*!< SCT STOP: STOPMSK_L Mask            */
+#define SCT_STOP_STOPMSK_H_Pos                                16                                                        /*!< SCT STOP: STOPMSK_H Position        */
+#define SCT_STOP_STOPMSK_H_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos)                  /*!< SCT STOP: STOPMSK_H Mask            */
+
+// ----------------------------------------  SCT_START  -------------------------------------------
+#define SCT_START_STARTMSK_L_Pos                              0                                                         /*!< SCT START: STARTMSK_L Position      */
+#define SCT_START_STARTMSK_L_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_L_Pos)                /*!< SCT START: STARTMSK_L Mask          */
+#define SCT_START_STARTMSK_H_Pos                              16                                                        /*!< SCT START: STARTMSK_H Position      */
+#define SCT_START_STARTMSK_H_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_H_Pos)                /*!< SCT START: STARTMSK_H Mask          */
+
+// ----------------------------------------  SCT_COUNT  -------------------------------------------
+#define SCT_COUNT_CTR_L_Pos                                   0                                                         /*!< SCT COUNT: CTR_L Position           */
+#define SCT_COUNT_CTR_L_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_L_Pos)                     /*!< SCT COUNT: CTR_L Mask               */
+#define SCT_COUNT_CTR_H_Pos                                   16                                                        /*!< SCT COUNT: CTR_H Position           */
+#define SCT_COUNT_CTR_H_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_H_Pos)                     /*!< SCT COUNT: CTR_H Mask               */
+
+// ----------------------------------------  SCT_STATE  -------------------------------------------
+#define SCT_STATE_STATE_L_Pos                                 0                                                         /*!< SCT STATE: STATE_L Position         */
+#define SCT_STATE_STATE_L_Msk                                 (0x1fUL << SCT_STATE_STATE_L_Pos)                         /*!< SCT STATE: STATE_L Mask             */
+#define SCT_STATE_STATE_H_Pos                                 16                                                        /*!< SCT STATE: STATE_H Position         */
+#define SCT_STATE_STATE_H_Msk                                 (0x1fUL << SCT_STATE_STATE_H_Pos)                         /*!< SCT STATE: STATE_H Mask             */
+
+// ----------------------------------------  SCT_INPUT  -------------------------------------------
+#define SCT_INPUT_AIN0_Pos                                    0                                                         /*!< SCT INPUT: AIN0 Position            */
+#define SCT_INPUT_AIN0_Msk                                    (0x01UL << SCT_INPUT_AIN0_Pos)                            /*!< SCT INPUT: AIN0 Mask                */
+#define SCT_INPUT_AIN1_Pos                                    1                                                         /*!< SCT INPUT: AIN1 Position            */
+#define SCT_INPUT_AIN1_Msk                                    (0x01UL << SCT_INPUT_AIN1_Pos)                            /*!< SCT INPUT: AIN1 Mask                */
+#define SCT_INPUT_AIN2_Pos                                    2                                                         /*!< SCT INPUT: AIN2 Position            */
+#define SCT_INPUT_AIN2_Msk                                    (0x01UL << SCT_INPUT_AIN2_Pos)                            /*!< SCT INPUT: AIN2 Mask                */
+#define SCT_INPUT_AIN3_Pos                                    3                                                         /*!< SCT INPUT: AIN3 Position            */
+#define SCT_INPUT_AIN3_Msk                                    (0x01UL << SCT_INPUT_AIN3_Pos)                            /*!< SCT INPUT: AIN3 Mask                */
+#define SCT_INPUT_AIN4_Pos                                    4                                                         /*!< SCT INPUT: AIN4 Position            */
+#define SCT_INPUT_AIN4_Msk                                    (0x01UL << SCT_INPUT_AIN4_Pos)                            /*!< SCT INPUT: AIN4 Mask                */
+#define SCT_INPUT_AIN5_Pos                                    5                                                         /*!< SCT INPUT: AIN5 Position            */
+#define SCT_INPUT_AIN5_Msk                                    (0x01UL << SCT_INPUT_AIN5_Pos)                            /*!< SCT INPUT: AIN5 Mask                */
+#define SCT_INPUT_AIN6_Pos                                    6                                                         /*!< SCT INPUT: AIN6 Position            */
+#define SCT_INPUT_AIN6_Msk                                    (0x01UL << SCT_INPUT_AIN6_Pos)                            /*!< SCT INPUT: AIN6 Mask                */
+#define SCT_INPUT_AIN7_Pos                                    7                                                         /*!< SCT INPUT: AIN7 Position            */
+#define SCT_INPUT_AIN7_Msk                                    (0x01UL << SCT_INPUT_AIN7_Pos)                            /*!< SCT INPUT: AIN7 Mask                */
+#define SCT_INPUT_SIN0_Pos                                    16                                                        /*!< SCT INPUT: SIN0 Position            */
+#define SCT_INPUT_SIN0_Msk                                    (0x01UL << SCT_INPUT_SIN0_Pos)                            /*!< SCT INPUT: SIN0 Mask                */
+#define SCT_INPUT_SIN1_Pos                                    17                                                        /*!< SCT INPUT: SIN1 Position            */
+#define SCT_INPUT_SIN1_Msk                                    (0x01UL << SCT_INPUT_SIN1_Pos)                            /*!< SCT INPUT: SIN1 Mask                */
+#define SCT_INPUT_SIN2_Pos                                    18                                                        /*!< SCT INPUT: SIN2 Position            */
+#define SCT_INPUT_SIN2_Msk                                    (0x01UL << SCT_INPUT_SIN2_Pos)                            /*!< SCT INPUT: SIN2 Mask                */
+#define SCT_INPUT_SIN3_Pos                                    19                                                        /*!< SCT INPUT: SIN3 Position            */
+#define SCT_INPUT_SIN3_Msk                                    (0x01UL << SCT_INPUT_SIN3_Pos)                            /*!< SCT INPUT: SIN3 Mask                */
+#define SCT_INPUT_SIN4_Pos                                    20                                                        /*!< SCT INPUT: SIN4 Position            */
+#define SCT_INPUT_SIN4_Msk                                    (0x01UL << SCT_INPUT_SIN4_Pos)                            /*!< SCT INPUT: SIN4 Mask                */
+#define SCT_INPUT_SIN5_Pos                                    21                                                        /*!< SCT INPUT: SIN5 Position            */
+#define SCT_INPUT_SIN5_Msk                                    (0x01UL << SCT_INPUT_SIN5_Pos)                            /*!< SCT INPUT: SIN5 Mask                */
+#define SCT_INPUT_SIN6_Pos                                    22                                                        /*!< SCT INPUT: SIN6 Position            */
+#define SCT_INPUT_SIN6_Msk                                    (0x01UL << SCT_INPUT_SIN6_Pos)                            /*!< SCT INPUT: SIN6 Mask                */
+#define SCT_INPUT_SIN7_Pos                                    23                                                        /*!< SCT INPUT: SIN7 Position            */
+#define SCT_INPUT_SIN7_Msk                                    (0x01UL << SCT_INPUT_SIN7_Pos)                            /*!< SCT INPUT: SIN7 Mask                */
+
+// ---------------------------------------  SCT_REGMODE  ------------------------------------------
+#define SCT_REGMODE_REGMOD_L0_Pos                             0                                                         /*!< SCT REGMODE: REGMOD_L0 Position     */
+#define SCT_REGMODE_REGMOD_L0_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L0_Pos)                     /*!< SCT REGMODE: REGMOD_L0 Mask         */
+#define SCT_REGMODE_REGMOD_L1_Pos                             1                                                         /*!< SCT REGMODE: REGMOD_L1 Position     */
+#define SCT_REGMODE_REGMOD_L1_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L1_Pos)                     /*!< SCT REGMODE: REGMOD_L1 Mask         */
+#define SCT_REGMODE_REGMOD_L2_Pos                             2                                                         /*!< SCT REGMODE: REGMOD_L2 Position     */
+#define SCT_REGMODE_REGMOD_L2_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L2_Pos)                     /*!< SCT REGMODE: REGMOD_L2 Mask         */
+#define SCT_REGMODE_REGMOD_L3_Pos                             3                                                         /*!< SCT REGMODE: REGMOD_L3 Position     */
+#define SCT_REGMODE_REGMOD_L3_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L3_Pos)                     /*!< SCT REGMODE: REGMOD_L3 Mask         */
+#define SCT_REGMODE_REGMOD_L4_Pos                             4                                                         /*!< SCT REGMODE: REGMOD_L4 Position     */
+#define SCT_REGMODE_REGMOD_L4_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L4_Pos)                     /*!< SCT REGMODE: REGMOD_L4 Mask         */
+#define SCT_REGMODE_REGMOD_L5_Pos                             5                                                         /*!< SCT REGMODE: REGMOD_L5 Position     */
+#define SCT_REGMODE_REGMOD_L5_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L5_Pos)                     /*!< SCT REGMODE: REGMOD_L5 Mask         */
+#define SCT_REGMODE_REGMOD_L6_Pos                             6                                                         /*!< SCT REGMODE: REGMOD_L6 Position     */
+#define SCT_REGMODE_REGMOD_L6_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L6_Pos)                     /*!< SCT REGMODE: REGMOD_L6 Mask         */
+#define SCT_REGMODE_REGMOD_L7_Pos                             7                                                         /*!< SCT REGMODE: REGMOD_L7 Position     */
+#define SCT_REGMODE_REGMOD_L7_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L7_Pos)                     /*!< SCT REGMODE: REGMOD_L7 Mask         */
+#define SCT_REGMODE_REGMOD_L8_Pos                             8                                                         /*!< SCT REGMODE: REGMOD_L8 Position     */
+#define SCT_REGMODE_REGMOD_L8_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L8_Pos)                     /*!< SCT REGMODE: REGMOD_L8 Mask         */
+#define SCT_REGMODE_REGMOD_L9_Pos                             9                                                         /*!< SCT REGMODE: REGMOD_L9 Position     */
+#define SCT_REGMODE_REGMOD_L9_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L9_Pos)                     /*!< SCT REGMODE: REGMOD_L9 Mask         */
+#define SCT_REGMODE_REGMOD_L10_Pos                            10                                                        /*!< SCT REGMODE: REGMOD_L10 Position    */
+#define SCT_REGMODE_REGMOD_L10_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L10_Pos)                    /*!< SCT REGMODE: REGMOD_L10 Mask        */
+#define SCT_REGMODE_REGMOD_L11_Pos                            11                                                        /*!< SCT REGMODE: REGMOD_L11 Position    */
+#define SCT_REGMODE_REGMOD_L11_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L11_Pos)                    /*!< SCT REGMODE: REGMOD_L11 Mask        */
+#define SCT_REGMODE_REGMOD_L12_Pos                            12                                                        /*!< SCT REGMODE: REGMOD_L12 Position    */
+#define SCT_REGMODE_REGMOD_L12_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L12_Pos)                    /*!< SCT REGMODE: REGMOD_L12 Mask        */
+#define SCT_REGMODE_REGMOD_L13_Pos                            13                                                        /*!< SCT REGMODE: REGMOD_L13 Position    */
+#define SCT_REGMODE_REGMOD_L13_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L13_Pos)                    /*!< SCT REGMODE: REGMOD_L13 Mask        */
+#define SCT_REGMODE_REGMOD_L14_Pos                            14                                                        /*!< SCT REGMODE: REGMOD_L14 Position    */
+#define SCT_REGMODE_REGMOD_L14_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L14_Pos)                    /*!< SCT REGMODE: REGMOD_L14 Mask        */
+#define SCT_REGMODE_REGMOD_L15_Pos                            15                                                        /*!< SCT REGMODE: REGMOD_L15 Position    */
+#define SCT_REGMODE_REGMOD_L15_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L15_Pos)                    /*!< SCT REGMODE: REGMOD_L15 Mask        */
+#define SCT_REGMODE_REGMOD_H16_Pos                            16                                                        /*!< SCT REGMODE: REGMOD_H16 Position    */
+#define SCT_REGMODE_REGMOD_H16_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H16_Pos)                    /*!< SCT REGMODE: REGMOD_H16 Mask        */
+#define SCT_REGMODE_REGMOD_H17_Pos                            17                                                        /*!< SCT REGMODE: REGMOD_H17 Position    */
+#define SCT_REGMODE_REGMOD_H17_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H17_Pos)                    /*!< SCT REGMODE: REGMOD_H17 Mask        */
+#define SCT_REGMODE_REGMOD_H18_Pos                            18                                                        /*!< SCT REGMODE: REGMOD_H18 Position    */
+#define SCT_REGMODE_REGMOD_H18_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H18_Pos)                    /*!< SCT REGMODE: REGMOD_H18 Mask        */
+#define SCT_REGMODE_REGMOD_H19_Pos                            19                                                        /*!< SCT REGMODE: REGMOD_H19 Position    */
+#define SCT_REGMODE_REGMOD_H19_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H19_Pos)                    /*!< SCT REGMODE: REGMOD_H19 Mask        */
+#define SCT_REGMODE_REGMOD_H20_Pos                            20                                                        /*!< SCT REGMODE: REGMOD_H20 Position    */
+#define SCT_REGMODE_REGMOD_H20_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H20_Pos)                    /*!< SCT REGMODE: REGMOD_H20 Mask        */
+#define SCT_REGMODE_REGMOD_H21_Pos                            21                                                        /*!< SCT REGMODE: REGMOD_H21 Position    */
+#define SCT_REGMODE_REGMOD_H21_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H21_Pos)                    /*!< SCT REGMODE: REGMOD_H21 Mask        */
+#define SCT_REGMODE_REGMOD_H22_Pos                            22                                                        /*!< SCT REGMODE: REGMOD_H22 Position    */
+#define SCT_REGMODE_REGMOD_H22_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H22_Pos)                    /*!< SCT REGMODE: REGMOD_H22 Mask        */
+#define SCT_REGMODE_REGMOD_H23_Pos                            23                                                        /*!< SCT REGMODE: REGMOD_H23 Position    */
+#define SCT_REGMODE_REGMOD_H23_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H23_Pos)                    /*!< SCT REGMODE: REGMOD_H23 Mask        */
+#define SCT_REGMODE_REGMOD_H24_Pos                            24                                                        /*!< SCT REGMODE: REGMOD_H24 Position    */
+#define SCT_REGMODE_REGMOD_H24_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H24_Pos)                    /*!< SCT REGMODE: REGMOD_H24 Mask        */
+#define SCT_REGMODE_REGMOD_H25_Pos                            25                                                        /*!< SCT REGMODE: REGMOD_H25 Position    */
+#define SCT_REGMODE_REGMOD_H25_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H25_Pos)                    /*!< SCT REGMODE: REGMOD_H25 Mask        */
+#define SCT_REGMODE_REGMOD_H26_Pos                            26                                                        /*!< SCT REGMODE: REGMOD_H26 Position    */
+#define SCT_REGMODE_REGMOD_H26_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H26_Pos)                    /*!< SCT REGMODE: REGMOD_H26 Mask        */
+#define SCT_REGMODE_REGMOD_H27_Pos                            27                                                        /*!< SCT REGMODE: REGMOD_H27 Position    */
+#define SCT_REGMODE_REGMOD_H27_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H27_Pos)                    /*!< SCT REGMODE: REGMOD_H27 Mask        */
+#define SCT_REGMODE_REGMOD_H28_Pos                            28                                                        /*!< SCT REGMODE: REGMOD_H28 Position    */
+#define SCT_REGMODE_REGMOD_H28_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H28_Pos)                    /*!< SCT REGMODE: REGMOD_H28 Mask        */
+#define SCT_REGMODE_REGMOD_H29_Pos                            29                                                        /*!< SCT REGMODE: REGMOD_H29 Position    */
+#define SCT_REGMODE_REGMOD_H29_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H29_Pos)                    /*!< SCT REGMODE: REGMOD_H29 Mask        */
+#define SCT_REGMODE_REGMOD_H30_Pos                            30                                                        /*!< SCT REGMODE: REGMOD_H30 Position    */
+#define SCT_REGMODE_REGMOD_H30_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H30_Pos)                    /*!< SCT REGMODE: REGMOD_H30 Mask        */
+#define SCT_REGMODE_REGMOD_H31_Pos                            31                                                        /*!< SCT REGMODE: REGMOD_H31 Position    */
+#define SCT_REGMODE_REGMOD_H31_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H31_Pos)                    /*!< SCT REGMODE: REGMOD_H31 Mask        */
+
+// ---------------------------------------  SCT_OUTPUT  -------------------------------------------
+#define SCT_OUTPUT_OUT0_Pos                                   0                                                         /*!< SCT OUTPUT: OUT0 Position           */
+#define SCT_OUTPUT_OUT0_Msk                                   (0x01UL << SCT_OUTPUT_OUT0_Pos)                           /*!< SCT OUTPUT: OUT0 Mask               */
+#define SCT_OUTPUT_OUT1_Pos                                   1                                                         /*!< SCT OUTPUT: OUT1 Position           */
+#define SCT_OUTPUT_OUT1_Msk                                   (0x01UL << SCT_OUTPUT_OUT1_Pos)                           /*!< SCT OUTPUT: OUT1 Mask               */
+#define SCT_OUTPUT_OUT2_Pos                                   2                                                         /*!< SCT OUTPUT: OUT2 Position           */
+#define SCT_OUTPUT_OUT2_Msk                                   (0x01UL << SCT_OUTPUT_OUT2_Pos)                           /*!< SCT OUTPUT: OUT2 Mask               */
+#define SCT_OUTPUT_OUT3_Pos                                   3                                                         /*!< SCT OUTPUT: OUT3 Position           */
+#define SCT_OUTPUT_OUT3_Msk                                   (0x01UL << SCT_OUTPUT_OUT3_Pos)                           /*!< SCT OUTPUT: OUT3 Mask               */
+#define SCT_OUTPUT_OUT4_Pos                                   4                                                         /*!< SCT OUTPUT: OUT4 Position           */
+#define SCT_OUTPUT_OUT4_Msk                                   (0x01UL << SCT_OUTPUT_OUT4_Pos)                           /*!< SCT OUTPUT: OUT4 Mask               */
+#define SCT_OUTPUT_OUT5_Pos                                   5                                                         /*!< SCT OUTPUT: OUT5 Position           */
+#define SCT_OUTPUT_OUT5_Msk                                   (0x01UL << SCT_OUTPUT_OUT5_Pos)                           /*!< SCT OUTPUT: OUT5 Mask               */
+#define SCT_OUTPUT_OUT6_Pos                                   6                                                         /*!< SCT OUTPUT: OUT6 Position           */
+#define SCT_OUTPUT_OUT6_Msk                                   (0x01UL << SCT_OUTPUT_OUT6_Pos)                           /*!< SCT OUTPUT: OUT6 Mask               */
+#define SCT_OUTPUT_OUT7_Pos                                   7                                                         /*!< SCT OUTPUT: OUT7 Position           */
+#define SCT_OUTPUT_OUT7_Msk                                   (0x01UL << SCT_OUTPUT_OUT7_Pos)                           /*!< SCT OUTPUT: OUT7 Mask               */
+#define SCT_OUTPUT_OUT8_Pos                                   8                                                         /*!< SCT OUTPUT: OUT8 Position           */
+#define SCT_OUTPUT_OUT8_Msk                                   (0x01UL << SCT_OUTPUT_OUT8_Pos)                           /*!< SCT OUTPUT: OUT8 Mask               */
+#define SCT_OUTPUT_OUT9_Pos                                   9                                                         /*!< SCT OUTPUT: OUT9 Position           */
+#define SCT_OUTPUT_OUT9_Msk                                   (0x01UL << SCT_OUTPUT_OUT9_Pos)                           /*!< SCT OUTPUT: OUT9 Mask               */
+#define SCT_OUTPUT_OUT10_Pos                                  10                                                        /*!< SCT OUTPUT: OUT10 Position          */
+#define SCT_OUTPUT_OUT10_Msk                                  (0x01UL << SCT_OUTPUT_OUT10_Pos)                          /*!< SCT OUTPUT: OUT10 Mask              */
+#define SCT_OUTPUT_OUT11_Pos                                  11                                                        /*!< SCT OUTPUT: OUT11 Position          */
+#define SCT_OUTPUT_OUT11_Msk                                  (0x01UL << SCT_OUTPUT_OUT11_Pos)                          /*!< SCT OUTPUT: OUT11 Mask              */
+#define SCT_OUTPUT_OUT12_Pos                                  12                                                        /*!< SCT OUTPUT: OUT12 Position          */
+#define SCT_OUTPUT_OUT12_Msk                                  (0x01UL << SCT_OUTPUT_OUT12_Pos)                          /*!< SCT OUTPUT: OUT12 Mask              */
+#define SCT_OUTPUT_OUT13_Pos                                  13                                                        /*!< SCT OUTPUT: OUT13 Position          */
+#define SCT_OUTPUT_OUT13_Msk                                  (0x01UL << SCT_OUTPUT_OUT13_Pos)                          /*!< SCT OUTPUT: OUT13 Mask              */
+#define SCT_OUTPUT_OUT14_Pos                                  14                                                        /*!< SCT OUTPUT: OUT14 Position          */
+#define SCT_OUTPUT_OUT14_Msk                                  (0x01UL << SCT_OUTPUT_OUT14_Pos)                          /*!< SCT OUTPUT: OUT14 Mask              */
+#define SCT_OUTPUT_OUT15_Pos                                  15                                                        /*!< SCT OUTPUT: OUT15 Position          */
+#define SCT_OUTPUT_OUT15_Msk                                  (0x01UL << SCT_OUTPUT_OUT15_Pos)                          /*!< SCT OUTPUT: OUT15 Mask              */
+
+// ------------------------------------  SCT_OUTPUTDIRCTRL  ---------------------------------------
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos                         0                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos                         2                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos                         4                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos                         6                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos                         8                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos                         10                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos                         12                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos                         14                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos                         16                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos                         18                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask     */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos                        20                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos                        22                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos                        24                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos                        26                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos                        28                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask    */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos                        30                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask    */
+
+// -----------------------------------------  SCT_RES  --------------------------------------------
+#define SCT_RES_O0RES_Pos                                     0                                                         /*!< SCT RES: O0RES Position             */
+#define SCT_RES_O0RES_Msk                                     (0x03UL << SCT_RES_O0RES_Pos)                             /*!< SCT RES: O0RES Mask                 */
+#define SCT_RES_O1RES_Pos                                     2                                                         /*!< SCT RES: O1RES Position             */
+#define SCT_RES_O1RES_Msk                                     (0x03UL << SCT_RES_O1RES_Pos)                             /*!< SCT RES: O1RES Mask                 */
+#define SCT_RES_O2RES_Pos                                     4                                                         /*!< SCT RES: O2RES Position             */
+#define SCT_RES_O2RES_Msk                                     (0x03UL << SCT_RES_O2RES_Pos)                             /*!< SCT RES: O2RES Mask                 */
+#define SCT_RES_O3RES_Pos                                     6                                                         /*!< SCT RES: O3RES Position             */
+#define SCT_RES_O3RES_Msk                                     (0x03UL << SCT_RES_O3RES_Pos)                             /*!< SCT RES: O3RES Mask                 */
+#define SCT_RES_O4RES_Pos                                     8                                                         /*!< SCT RES: O4RES Position             */
+#define SCT_RES_O4RES_Msk                                     (0x03UL << SCT_RES_O4RES_Pos)                             /*!< SCT RES: O4RES Mask                 */
+#define SCT_RES_O5RES_Pos                                     10                                                        /*!< SCT RES: O5RES Position             */
+#define SCT_RES_O5RES_Msk                                     (0x03UL << SCT_RES_O5RES_Pos)                             /*!< SCT RES: O5RES Mask                 */
+#define SCT_RES_O6RES_Pos                                     12                                                        /*!< SCT RES: O6RES Position             */
+#define SCT_RES_O6RES_Msk                                     (0x03UL << SCT_RES_O6RES_Pos)                             /*!< SCT RES: O6RES Mask                 */
+#define SCT_RES_O7RES_Pos                                     14                                                        /*!< SCT RES: O7RES Position             */
+#define SCT_RES_O7RES_Msk                                     (0x03UL << SCT_RES_O7RES_Pos)                             /*!< SCT RES: O7RES Mask                 */
+#define SCT_RES_O8RES_Pos                                     16                                                        /*!< SCT RES: O8RES Position             */
+#define SCT_RES_O8RES_Msk                                     (0x03UL << SCT_RES_O8RES_Pos)                             /*!< SCT RES: O8RES Mask                 */
+#define SCT_RES_O9RES_Pos                                     18                                                        /*!< SCT RES: O9RES Position             */
+#define SCT_RES_O9RES_Msk                                     (0x03UL << SCT_RES_O9RES_Pos)                             /*!< SCT RES: O9RES Mask                 */
+#define SCT_RES_O10RES_Pos                                    20                                                        /*!< SCT RES: O10RES Position            */
+#define SCT_RES_O10RES_Msk                                    (0x03UL << SCT_RES_O10RES_Pos)                            /*!< SCT RES: O10RES Mask                */
+#define SCT_RES_O11RES_Pos                                    22                                                        /*!< SCT RES: O11RES Position            */
+#define SCT_RES_O11RES_Msk                                    (0x03UL << SCT_RES_O11RES_Pos)                            /*!< SCT RES: O11RES Mask                */
+#define SCT_RES_O12RES_Pos                                    24                                                        /*!< SCT RES: O12RES Position            */
+#define SCT_RES_O12RES_Msk                                    (0x03UL << SCT_RES_O12RES_Pos)                            /*!< SCT RES: O12RES Mask                */
+#define SCT_RES_O13RES_Pos                                    26                                                        /*!< SCT RES: O13RES Position            */
+#define SCT_RES_O13RES_Msk                                    (0x03UL << SCT_RES_O13RES_Pos)                            /*!< SCT RES: O13RES Mask                */
+#define SCT_RES_O14RES_Pos                                    28                                                        /*!< SCT RES: O14RES Position            */
+#define SCT_RES_O14RES_Msk                                    (0x03UL << SCT_RES_O14RES_Pos)                            /*!< SCT RES: O14RES Mask                */
+#define SCT_RES_O15RES_Pos                                    30                                                        /*!< SCT RES: O15RES Position            */
+#define SCT_RES_O15RES_Msk                                    (0x03UL << SCT_RES_O15RES_Pos)                            /*!< SCT RES: O15RES Mask                */
+
+// ---------------------------------------  SCT_DMAREQ0  ------------------------------------------
+#define SCT_DMAREQ0_DEV_0_0_Pos                               0                                                         /*!< SCT DMAREQ0: DEV_0_0 Position       */
+#define SCT_DMAREQ0_DEV_0_0_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos)                       /*!< SCT DMAREQ0: DEV_0_0 Mask           */
+#define SCT_DMAREQ0_DEV_0_1_Pos                               1                                                         /*!< SCT DMAREQ0: DEV_0_1 Position       */
+#define SCT_DMAREQ0_DEV_0_1_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos)                       /*!< SCT DMAREQ0: DEV_0_1 Mask           */
+#define SCT_DMAREQ0_DEV_0_2_Pos                               2                                                         /*!< SCT DMAREQ0: DEV_0_2 Position       */
+#define SCT_DMAREQ0_DEV_0_2_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos)                       /*!< SCT DMAREQ0: DEV_0_2 Mask           */
+#define SCT_DMAREQ0_DEV_0_3_Pos                               3                                                         /*!< SCT DMAREQ0: DEV_0_3 Position       */
+#define SCT_DMAREQ0_DEV_0_3_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos)                       /*!< SCT DMAREQ0: DEV_0_3 Mask           */
+#define SCT_DMAREQ0_DEV_0_4_Pos                               4                                                         /*!< SCT DMAREQ0: DEV_0_4 Position       */
+#define SCT_DMAREQ0_DEV_0_4_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos)                       /*!< SCT DMAREQ0: DEV_0_4 Mask           */
+#define SCT_DMAREQ0_DEV_0_5_Pos                               5                                                         /*!< SCT DMAREQ0: DEV_0_5 Position       */
+#define SCT_DMAREQ0_DEV_0_5_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos)                       /*!< SCT DMAREQ0: DEV_0_5 Mask           */
+#define SCT_DMAREQ0_DEV_0_6_Pos                               6                                                         /*!< SCT DMAREQ0: DEV_0_6 Position       */
+#define SCT_DMAREQ0_DEV_0_6_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos)                       /*!< SCT DMAREQ0: DEV_0_6 Mask           */
+#define SCT_DMAREQ0_DEV_0_7_Pos                               7                                                         /*!< SCT DMAREQ0: DEV_0_7 Position       */
+#define SCT_DMAREQ0_DEV_0_7_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos)                       /*!< SCT DMAREQ0: DEV_0_7 Mask           */
+#define SCT_DMAREQ0_DEV_0_8_Pos                               8                                                         /*!< SCT DMAREQ0: DEV_0_8 Position       */
+#define SCT_DMAREQ0_DEV_0_8_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos)                       /*!< SCT DMAREQ0: DEV_0_8 Mask           */
+#define SCT_DMAREQ0_DEV_0_9_Pos                               9                                                         /*!< SCT DMAREQ0: DEV_0_9 Position       */
+#define SCT_DMAREQ0_DEV_0_9_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos)                       /*!< SCT DMAREQ0: DEV_0_9 Mask           */
+#define SCT_DMAREQ0_DEV_0_10_Pos                              10                                                        /*!< SCT DMAREQ0: DEV_0_10 Position      */
+#define SCT_DMAREQ0_DEV_0_10_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos)                      /*!< SCT DMAREQ0: DEV_0_10 Mask          */
+#define SCT_DMAREQ0_DEV_0_11_Pos                              11                                                        /*!< SCT DMAREQ0: DEV_0_11 Position      */
+#define SCT_DMAREQ0_DEV_0_11_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos)                      /*!< SCT DMAREQ0: DEV_0_11 Mask          */
+#define SCT_DMAREQ0_DEV_0_12_Pos                              12                                                        /*!< SCT DMAREQ0: DEV_0_12 Position      */
+#define SCT_DMAREQ0_DEV_0_12_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos)                      /*!< SCT DMAREQ0: DEV_0_12 Mask          */
+#define SCT_DMAREQ0_DEV_0_13_Pos                              13                                                        /*!< SCT DMAREQ0: DEV_0_13 Position      */
+#define SCT_DMAREQ0_DEV_0_13_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos)                      /*!< SCT DMAREQ0: DEV_0_13 Mask          */
+#define SCT_DMAREQ0_DEV_0_14_Pos                              14                                                        /*!< SCT DMAREQ0: DEV_0_14 Position      */
+#define SCT_DMAREQ0_DEV_0_14_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos)                      /*!< SCT DMAREQ0: DEV_0_14 Mask          */
+#define SCT_DMAREQ0_DEV_0_15_Pos                              15                                                        /*!< SCT DMAREQ0: DEV_0_15 Position      */
+#define SCT_DMAREQ0_DEV_0_15_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos)                      /*!< SCT DMAREQ0: DEV_0_15 Mask          */
+#define SCT_DMAREQ0_DRL0_Pos                                  30                                                        /*!< SCT DMAREQ0: DRL0 Position          */
+#define SCT_DMAREQ0_DRL0_Msk                                  (0x01UL << SCT_DMAREQ0_DRL0_Pos)                          /*!< SCT DMAREQ0: DRL0 Mask              */
+#define SCT_DMAREQ0_DRQ0_Pos                                  31                                                        /*!< SCT DMAREQ0: DRQ0 Position          */
+#define SCT_DMAREQ0_DRQ0_Msk                                  (0x01UL << SCT_DMAREQ0_DRQ0_Pos)                          /*!< SCT DMAREQ0: DRQ0 Mask              */
+
+// ---------------------------------------  SCT_DMAREQ1  ------------------------------------------
+#define SCT_DMAREQ1_DEV_1_0_Pos                               0                                                         /*!< SCT DMAREQ1: DEV_1_0 Position       */
+#define SCT_DMAREQ1_DEV_1_0_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos)                       /*!< SCT DMAREQ1: DEV_1_0 Mask           */
+#define SCT_DMAREQ1_DEV_1_1_Pos                               1                                                         /*!< SCT DMAREQ1: DEV_1_1 Position       */
+#define SCT_DMAREQ1_DEV_1_1_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos)                       /*!< SCT DMAREQ1: DEV_1_1 Mask           */
+#define SCT_DMAREQ1_DEV_1_2_Pos                               2                                                         /*!< SCT DMAREQ1: DEV_1_2 Position       */
+#define SCT_DMAREQ1_DEV_1_2_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos)                       /*!< SCT DMAREQ1: DEV_1_2 Mask           */
+#define SCT_DMAREQ1_DEV_1_3_Pos                               3                                                         /*!< SCT DMAREQ1: DEV_1_3 Position       */
+#define SCT_DMAREQ1_DEV_1_3_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos)                       /*!< SCT DMAREQ1: DEV_1_3 Mask           */
+#define SCT_DMAREQ1_DEV_1_4_Pos                               4                                                         /*!< SCT DMAREQ1: DEV_1_4 Position       */
+#define SCT_DMAREQ1_DEV_1_4_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos)                       /*!< SCT DMAREQ1: DEV_1_4 Mask           */
+#define SCT_DMAREQ1_DEV_1_5_Pos                               5                                                         /*!< SCT DMAREQ1: DEV_1_5 Position       */
+#define SCT_DMAREQ1_DEV_1_5_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos)                       /*!< SCT DMAREQ1: DEV_1_5 Mask           */
+#define SCT_DMAREQ1_DEV_1_6_Pos                               6                                                         /*!< SCT DMAREQ1: DEV_1_6 Position       */
+#define SCT_DMAREQ1_DEV_1_6_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos)                       /*!< SCT DMAREQ1: DEV_1_6 Mask           */
+#define SCT_DMAREQ1_DEV_1_7_Pos                               7                                                         /*!< SCT DMAREQ1: DEV_1_7 Position       */
+#define SCT_DMAREQ1_DEV_1_7_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos)                       /*!< SCT DMAREQ1: DEV_1_7 Mask           */
+#define SCT_DMAREQ1_DEV_1_8_Pos                               8                                                         /*!< SCT DMAREQ1: DEV_1_8 Position       */
+#define SCT_DMAREQ1_DEV_1_8_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos)                       /*!< SCT DMAREQ1: DEV_1_8 Mask           */
+#define SCT_DMAREQ1_DEV_1_9_Pos                               9                                                         /*!< SCT DMAREQ1: DEV_1_9 Position       */
+#define SCT_DMAREQ1_DEV_1_9_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos)                       /*!< SCT DMAREQ1: DEV_1_9 Mask           */
+#define SCT_DMAREQ1_DEV_1_10_Pos                              10                                                        /*!< SCT DMAREQ1: DEV_1_10 Position      */
+#define SCT_DMAREQ1_DEV_1_10_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos)                      /*!< SCT DMAREQ1: DEV_1_10 Mask          */
+#define SCT_DMAREQ1_DEV_1_11_Pos                              11                                                        /*!< SCT DMAREQ1: DEV_1_11 Position      */
+#define SCT_DMAREQ1_DEV_1_11_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos)                      /*!< SCT DMAREQ1: DEV_1_11 Mask          */
+#define SCT_DMAREQ1_DEV_1_12_Pos                              12                                                        /*!< SCT DMAREQ1: DEV_1_12 Position      */
+#define SCT_DMAREQ1_DEV_1_12_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos)                      /*!< SCT DMAREQ1: DEV_1_12 Mask          */
+#define SCT_DMAREQ1_DEV_1_13_Pos                              13                                                        /*!< SCT DMAREQ1: DEV_1_13 Position      */
+#define SCT_DMAREQ1_DEV_1_13_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos)                      /*!< SCT DMAREQ1: DEV_1_13 Mask          */
+#define SCT_DMAREQ1_DEV_1_14_Pos                              14                                                        /*!< SCT DMAREQ1: DEV_1_14 Position      */
+#define SCT_DMAREQ1_DEV_1_14_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos)                      /*!< SCT DMAREQ1: DEV_1_14 Mask          */
+#define SCT_DMAREQ1_DEV_1_15_Pos                              15                                                        /*!< SCT DMAREQ1: DEV_1_15 Position      */
+#define SCT_DMAREQ1_DEV_1_15_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos)                      /*!< SCT DMAREQ1: DEV_1_15 Mask          */
+#define SCT_DMAREQ1_DRL1_Pos                                  30                                                        /*!< SCT DMAREQ1: DRL1 Position          */
+#define SCT_DMAREQ1_DRL1_Msk                                  (0x01UL << SCT_DMAREQ1_DRL1_Pos)                          /*!< SCT DMAREQ1: DRL1 Mask              */
+#define SCT_DMAREQ1_DRQ1_Pos                                  31                                                        /*!< SCT DMAREQ1: DRQ1 Position          */
+#define SCT_DMAREQ1_DRQ1_Msk                                  (0x01UL << SCT_DMAREQ1_DRQ1_Pos)                          /*!< SCT DMAREQ1: DRQ1 Mask              */
+
+// ----------------------------------------  SCT_EVEN  --------------------------------------------
+#define SCT_EVEN_IEN0_Pos                                     0                                                         /*!< SCT EVEN: IEN0 Position             */
+#define SCT_EVEN_IEN0_Msk                                     (0x01UL << SCT_EVEN_IEN0_Pos)                             /*!< SCT EVEN: IEN0 Mask                 */
+#define SCT_EVEN_IEN1_Pos                                     1                                                         /*!< SCT EVEN: IEN1 Position             */
+#define SCT_EVEN_IEN1_Msk                                     (0x01UL << SCT_EVEN_IEN1_Pos)                             /*!< SCT EVEN: IEN1 Mask                 */
+#define SCT_EVEN_IEN2_Pos                                     2                                                         /*!< SCT EVEN: IEN2 Position             */
+#define SCT_EVEN_IEN2_Msk                                     (0x01UL << SCT_EVEN_IEN2_Pos)                             /*!< SCT EVEN: IEN2 Mask                 */
+#define SCT_EVEN_IEN3_Pos                                     3                                                         /*!< SCT EVEN: IEN3 Position             */
+#define SCT_EVEN_IEN3_Msk                                     (0x01UL << SCT_EVEN_IEN3_Pos)                             /*!< SCT EVEN: IEN3 Mask                 */
+#define SCT_EVEN_IEN4_Pos                                     4                                                         /*!< SCT EVEN: IEN4 Position             */
+#define SCT_EVEN_IEN4_Msk                                     (0x01UL << SCT_EVEN_IEN4_Pos)                             /*!< SCT EVEN: IEN4 Mask                 */
+#define SCT_EVEN_IEN5_Pos                                     5                                                         /*!< SCT EVEN: IEN5 Position             */
+#define SCT_EVEN_IEN5_Msk                                     (0x01UL << SCT_EVEN_IEN5_Pos)                             /*!< SCT EVEN: IEN5 Mask                 */
+#define SCT_EVEN_IEN6_Pos                                     6                                                         /*!< SCT EVEN: IEN6 Position             */
+#define SCT_EVEN_IEN6_Msk                                     (0x01UL << SCT_EVEN_IEN6_Pos)                             /*!< SCT EVEN: IEN6 Mask                 */
+#define SCT_EVEN_IEN7_Pos                                     7                                                         /*!< SCT EVEN: IEN7 Position             */
+#define SCT_EVEN_IEN7_Msk                                     (0x01UL << SCT_EVEN_IEN7_Pos)                             /*!< SCT EVEN: IEN7 Mask                 */
+#define SCT_EVEN_IEN8_Pos                                     8                                                         /*!< SCT EVEN: IEN8 Position             */
+#define SCT_EVEN_IEN8_Msk                                     (0x01UL << SCT_EVEN_IEN8_Pos)                             /*!< SCT EVEN: IEN8 Mask                 */
+#define SCT_EVEN_IEN9_Pos                                     9                                                         /*!< SCT EVEN: IEN9 Position             */
+#define SCT_EVEN_IEN9_Msk                                     (0x01UL << SCT_EVEN_IEN9_Pos)                             /*!< SCT EVEN: IEN9 Mask                 */
+#define SCT_EVEN_IEN10_Pos                                    10                                                        /*!< SCT EVEN: IEN10 Position            */
+#define SCT_EVEN_IEN10_Msk                                    (0x01UL << SCT_EVEN_IEN10_Pos)                            /*!< SCT EVEN: IEN10 Mask                */
+#define SCT_EVEN_IEN11_Pos                                    11                                                        /*!< SCT EVEN: IEN11 Position            */
+#define SCT_EVEN_IEN11_Msk                                    (0x01UL << SCT_EVEN_IEN11_Pos)                            /*!< SCT EVEN: IEN11 Mask                */
+#define SCT_EVEN_IEN12_Pos                                    12                                                        /*!< SCT EVEN: IEN12 Position            */
+#define SCT_EVEN_IEN12_Msk                                    (0x01UL << SCT_EVEN_IEN12_Pos)                            /*!< SCT EVEN: IEN12 Mask                */
+#define SCT_EVEN_IEN13_Pos                                    13                                                        /*!< SCT EVEN: IEN13 Position            */
+#define SCT_EVEN_IEN13_Msk                                    (0x01UL << SCT_EVEN_IEN13_Pos)                            /*!< SCT EVEN: IEN13 Mask                */
+#define SCT_EVEN_IEN14_Pos                                    14                                                        /*!< SCT EVEN: IEN14 Position            */
+#define SCT_EVEN_IEN14_Msk                                    (0x01UL << SCT_EVEN_IEN14_Pos)                            /*!< SCT EVEN: IEN14 Mask                */
+#define SCT_EVEN_IEN15_Pos                                    15                                                        /*!< SCT EVEN: IEN15 Position            */
+#define SCT_EVEN_IEN15_Msk                                    (0x01UL << SCT_EVEN_IEN15_Pos)                            /*!< SCT EVEN: IEN15 Mask                */
+
+// ---------------------------------------  SCT_EVFLAG  -------------------------------------------
+#define SCT_EVFLAG_FLAG0_Pos                                  0                                                         /*!< SCT EVFLAG: FLAG0 Position          */
+#define SCT_EVFLAG_FLAG0_Msk                                  (0x01UL << SCT_EVFLAG_FLAG0_Pos)                          /*!< SCT EVFLAG: FLAG0 Mask              */
+#define SCT_EVFLAG_FLAG1_Pos                                  1                                                         /*!< SCT EVFLAG: FLAG1 Position          */
+#define SCT_EVFLAG_FLAG1_Msk                                  (0x01UL << SCT_EVFLAG_FLAG1_Pos)                          /*!< SCT EVFLAG: FLAG1 Mask              */
+#define SCT_EVFLAG_FLAG2_Pos                                  2                                                         /*!< SCT EVFLAG: FLAG2 Position          */
+#define SCT_EVFLAG_FLAG2_Msk                                  (0x01UL << SCT_EVFLAG_FLAG2_Pos)                          /*!< SCT EVFLAG: FLAG2 Mask              */
+#define SCT_EVFLAG_FLAG3_Pos                                  3                                                         /*!< SCT EVFLAG: FLAG3 Position          */
+#define SCT_EVFLAG_FLAG3_Msk                                  (0x01UL << SCT_EVFLAG_FLAG3_Pos)                          /*!< SCT EVFLAG: FLAG3 Mask              */
+#define SCT_EVFLAG_FLAG4_Pos                                  4                                                         /*!< SCT EVFLAG: FLAG4 Position          */
+#define SCT_EVFLAG_FLAG4_Msk                                  (0x01UL << SCT_EVFLAG_FLAG4_Pos)                          /*!< SCT EVFLAG: FLAG4 Mask              */
+#define SCT_EVFLAG_FLAG5_Pos                                  5                                                         /*!< SCT EVFLAG: FLAG5 Position          */
+#define SCT_EVFLAG_FLAG5_Msk                                  (0x01UL << SCT_EVFLAG_FLAG5_Pos)                          /*!< SCT EVFLAG: FLAG5 Mask              */
+#define SCT_EVFLAG_FLAG6_Pos                                  6                                                         /*!< SCT EVFLAG: FLAG6 Position          */
+#define SCT_EVFLAG_FLAG6_Msk                                  (0x01UL << SCT_EVFLAG_FLAG6_Pos)                          /*!< SCT EVFLAG: FLAG6 Mask              */
+#define SCT_EVFLAG_FLAG7_Pos                                  7                                                         /*!< SCT EVFLAG: FLAG7 Position          */
+#define SCT_EVFLAG_FLAG7_Msk                                  (0x01UL << SCT_EVFLAG_FLAG7_Pos)                          /*!< SCT EVFLAG: FLAG7 Mask              */
+#define SCT_EVFLAG_FLAG8_Pos                                  8                                                         /*!< SCT EVFLAG: FLAG8 Position          */
+#define SCT_EVFLAG_FLAG8_Msk                                  (0x01UL << SCT_EVFLAG_FLAG8_Pos)                          /*!< SCT EVFLAG: FLAG8 Mask              */
+#define SCT_EVFLAG_FLAG9_Pos                                  9                                                         /*!< SCT EVFLAG: FLAG9 Position          */
+#define SCT_EVFLAG_FLAG9_Msk                                  (0x01UL << SCT_EVFLAG_FLAG9_Pos)                          /*!< SCT EVFLAG: FLAG9 Mask              */
+#define SCT_EVFLAG_FLAG10_Pos                                 10                                                        /*!< SCT EVFLAG: FLAG10 Position         */
+#define SCT_EVFLAG_FLAG10_Msk                                 (0x01UL << SCT_EVFLAG_FLAG10_Pos)                         /*!< SCT EVFLAG: FLAG10 Mask             */
+#define SCT_EVFLAG_FLAG11_Pos                                 11                                                        /*!< SCT EVFLAG: FLAG11 Position         */
+#define SCT_EVFLAG_FLAG11_Msk                                 (0x01UL << SCT_EVFLAG_FLAG11_Pos)                         /*!< SCT EVFLAG: FLAG11 Mask             */
+#define SCT_EVFLAG_FLAG12_Pos                                 12                                                        /*!< SCT EVFLAG: FLAG12 Position         */
+#define SCT_EVFLAG_FLAG12_Msk                                 (0x01UL << SCT_EVFLAG_FLAG12_Pos)                         /*!< SCT EVFLAG: FLAG12 Mask             */
+#define SCT_EVFLAG_FLAG13_Pos                                 13                                                        /*!< SCT EVFLAG: FLAG13 Position         */
+#define SCT_EVFLAG_FLAG13_Msk                                 (0x01UL << SCT_EVFLAG_FLAG13_Pos)                         /*!< SCT EVFLAG: FLAG13 Mask             */
+#define SCT_EVFLAG_FLAG14_Pos                                 14                                                        /*!< SCT EVFLAG: FLAG14 Position         */
+#define SCT_EVFLAG_FLAG14_Msk                                 (0x01UL << SCT_EVFLAG_FLAG14_Pos)                         /*!< SCT EVFLAG: FLAG14 Mask             */
+#define SCT_EVFLAG_FLAG15_Pos                                 15                                                        /*!< SCT EVFLAG: FLAG15 Position         */
+#define SCT_EVFLAG_FLAG15_Msk                                 (0x01UL << SCT_EVFLAG_FLAG15_Pos)                         /*!< SCT EVFLAG: FLAG15 Mask             */
+
+// ----------------------------------------  SCT_CONEN  -------------------------------------------
+#define SCT_CONEN_NCEN0_Pos                                   0                                                         /*!< SCT CONEN: NCEN0 Position           */
+#define SCT_CONEN_NCEN0_Msk                                   (0x01UL << SCT_CONEN_NCEN0_Pos)                           /*!< SCT CONEN: NCEN0 Mask               */
+#define SCT_CONEN_NCEN1_Pos                                   1                                                         /*!< SCT CONEN: NCEN1 Position           */
+#define SCT_CONEN_NCEN1_Msk                                   (0x01UL << SCT_CONEN_NCEN1_Pos)                           /*!< SCT CONEN: NCEN1 Mask               */
+#define SCT_CONEN_NCEN2_Pos                                   2                                                         /*!< SCT CONEN: NCEN2 Position           */
+#define SCT_CONEN_NCEN2_Msk                                   (0x01UL << SCT_CONEN_NCEN2_Pos)                           /*!< SCT CONEN: NCEN2 Mask               */
+#define SCT_CONEN_NCEN3_Pos                                   3                                                         /*!< SCT CONEN: NCEN3 Position           */
+#define SCT_CONEN_NCEN3_Msk                                   (0x01UL << SCT_CONEN_NCEN3_Pos)                           /*!< SCT CONEN: NCEN3 Mask               */
+#define SCT_CONEN_NCEN4_Pos                                   4                                                         /*!< SCT CONEN: NCEN4 Position           */
+#define SCT_CONEN_NCEN4_Msk                                   (0x01UL << SCT_CONEN_NCEN4_Pos)                           /*!< SCT CONEN: NCEN4 Mask               */
+#define SCT_CONEN_NCEN5_Pos                                   5                                                         /*!< SCT CONEN: NCEN5 Position           */
+#define SCT_CONEN_NCEN5_Msk                                   (0x01UL << SCT_CONEN_NCEN5_Pos)                           /*!< SCT CONEN: NCEN5 Mask               */
+#define SCT_CONEN_NCEN6_Pos                                   6                                                         /*!< SCT CONEN: NCEN6 Position           */
+#define SCT_CONEN_NCEN6_Msk                                   (0x01UL << SCT_CONEN_NCEN6_Pos)                           /*!< SCT CONEN: NCEN6 Mask               */
+#define SCT_CONEN_NCEN7_Pos                                   7                                                         /*!< SCT CONEN: NCEN7 Position           */
+#define SCT_CONEN_NCEN7_Msk                                   (0x01UL << SCT_CONEN_NCEN7_Pos)                           /*!< SCT CONEN: NCEN7 Mask               */
+#define SCT_CONEN_NCEN8_Pos                                   8                                                         /*!< SCT CONEN: NCEN8 Position           */
+#define SCT_CONEN_NCEN8_Msk                                   (0x01UL << SCT_CONEN_NCEN8_Pos)                           /*!< SCT CONEN: NCEN8 Mask               */
+#define SCT_CONEN_NCEN9_Pos                                   9                                                         /*!< SCT CONEN: NCEN9 Position           */
+#define SCT_CONEN_NCEN9_Msk                                   (0x01UL << SCT_CONEN_NCEN9_Pos)                           /*!< SCT CONEN: NCEN9 Mask               */
+#define SCT_CONEN_NCEN10_Pos                                  10                                                        /*!< SCT CONEN: NCEN10 Position          */
+#define SCT_CONEN_NCEN10_Msk                                  (0x01UL << SCT_CONEN_NCEN10_Pos)                          /*!< SCT CONEN: NCEN10 Mask              */
+#define SCT_CONEN_NCEN11_Pos                                  11                                                        /*!< SCT CONEN: NCEN11 Position          */
+#define SCT_CONEN_NCEN11_Msk                                  (0x01UL << SCT_CONEN_NCEN11_Pos)                          /*!< SCT CONEN: NCEN11 Mask              */
+#define SCT_CONEN_NCEN12_Pos                                  12                                                        /*!< SCT CONEN: NCEN12 Position          */
+#define SCT_CONEN_NCEN12_Msk                                  (0x01UL << SCT_CONEN_NCEN12_Pos)                          /*!< SCT CONEN: NCEN12 Mask              */
+#define SCT_CONEN_NCEN13_Pos                                  13                                                        /*!< SCT CONEN: NCEN13 Position          */
+#define SCT_CONEN_NCEN13_Msk                                  (0x01UL << SCT_CONEN_NCEN13_Pos)                          /*!< SCT CONEN: NCEN13 Mask              */
+#define SCT_CONEN_NCEN14_Pos                                  14                                                        /*!< SCT CONEN: NCEN14 Position          */
+#define SCT_CONEN_NCEN14_Msk                                  (0x01UL << SCT_CONEN_NCEN14_Pos)                          /*!< SCT CONEN: NCEN14 Mask              */
+#define SCT_CONEN_NCEN15_Pos                                  15                                                        /*!< SCT CONEN: NCEN15 Position          */
+#define SCT_CONEN_NCEN15_Msk                                  (0x01UL << SCT_CONEN_NCEN15_Pos)                          /*!< SCT CONEN: NCEN15 Mask              */
+
+// ---------------------------------------  SCT_CONFLAG  ------------------------------------------
+#define SCT_CONFLAG_NCFLAG0_Pos                               0                                                         /*!< SCT CONFLAG: NCFLAG0 Position       */
+#define SCT_CONFLAG_NCFLAG0_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG0_Pos)                       /*!< SCT CONFLAG: NCFLAG0 Mask           */
+#define SCT_CONFLAG_NCFLAG1_Pos                               1                                                         /*!< SCT CONFLAG: NCFLAG1 Position       */
+#define SCT_CONFLAG_NCFLAG1_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG1_Pos)                       /*!< SCT CONFLAG: NCFLAG1 Mask           */
+#define SCT_CONFLAG_NCFLAG2_Pos                               2                                                         /*!< SCT CONFLAG: NCFLAG2 Position       */
+#define SCT_CONFLAG_NCFLAG2_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG2_Pos)                       /*!< SCT CONFLAG: NCFLAG2 Mask           */
+#define SCT_CONFLAG_NCFLAG3_Pos                               3                                                         /*!< SCT CONFLAG: NCFLAG3 Position       */
+#define SCT_CONFLAG_NCFLAG3_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG3_Pos)                       /*!< SCT CONFLAG: NCFLAG3 Mask           */
+#define SCT_CONFLAG_NCFLAG4_Pos                               4                                                         /*!< SCT CONFLAG: NCFLAG4 Position       */
+#define SCT_CONFLAG_NCFLAG4_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG4_Pos)                       /*!< SCT CONFLAG: NCFLAG4 Mask           */
+#define SCT_CONFLAG_NCFLAG5_Pos                               5                                                         /*!< SCT CONFLAG: NCFLAG5 Position       */
+#define SCT_CONFLAG_NCFLAG5_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG5_Pos)                       /*!< SCT CONFLAG: NCFLAG5 Mask           */
+#define SCT_CONFLAG_NCFLAG6_Pos                               6                                                         /*!< SCT CONFLAG: NCFLAG6 Position       */
+#define SCT_CONFLAG_NCFLAG6_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG6_Pos)                       /*!< SCT CONFLAG: NCFLAG6 Mask           */
+#define SCT_CONFLAG_NCFLAG7_Pos                               7                                                         /*!< SCT CONFLAG: NCFLAG7 Position       */
+#define SCT_CONFLAG_NCFLAG7_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG7_Pos)                       /*!< SCT CONFLAG: NCFLAG7 Mask           */
+#define SCT_CONFLAG_NCFLAG8_Pos                               8                                                         /*!< SCT CONFLAG: NCFLAG8 Position       */
+#define SCT_CONFLAG_NCFLAG8_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG8_Pos)                       /*!< SCT CONFLAG: NCFLAG8 Mask           */
+#define SCT_CONFLAG_NCFLAG9_Pos                               9                                                         /*!< SCT CONFLAG: NCFLAG9 Position       */
+#define SCT_CONFLAG_NCFLAG9_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG9_Pos)                       /*!< SCT CONFLAG: NCFLAG9 Mask           */
+#define SCT_CONFLAG_NCFLAG10_Pos                              10                                                        /*!< SCT CONFLAG: NCFLAG10 Position      */
+#define SCT_CONFLAG_NCFLAG10_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG10_Pos)                      /*!< SCT CONFLAG: NCFLAG10 Mask          */
+#define SCT_CONFLAG_NCFLAG11_Pos                              11                                                        /*!< SCT CONFLAG: NCFLAG11 Position      */
+#define SCT_CONFLAG_NCFLAG11_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG11_Pos)                      /*!< SCT CONFLAG: NCFLAG11 Mask          */
+#define SCT_CONFLAG_NCFLAG12_Pos                              12                                                        /*!< SCT CONFLAG: NCFLAG12 Position      */
+#define SCT_CONFLAG_NCFLAG12_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG12_Pos)                      /*!< SCT CONFLAG: NCFLAG12 Mask          */
+#define SCT_CONFLAG_NCFLAG13_Pos                              13                                                        /*!< SCT CONFLAG: NCFLAG13 Position      */
+#define SCT_CONFLAG_NCFLAG13_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG13_Pos)                      /*!< SCT CONFLAG: NCFLAG13 Mask          */
+#define SCT_CONFLAG_NCFLAG14_Pos                              14                                                        /*!< SCT CONFLAG: NCFLAG14 Position      */
+#define SCT_CONFLAG_NCFLAG14_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG14_Pos)                      /*!< SCT CONFLAG: NCFLAG14 Mask          */
+#define SCT_CONFLAG_NCFLAG15_Pos                              15                                                        /*!< SCT CONFLAG: NCFLAG15 Position      */
+#define SCT_CONFLAG_NCFLAG15_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG15_Pos)                      /*!< SCT CONFLAG: NCFLAG15 Mask          */
+#define SCT_CONFLAG_BUSERRL_Pos                               30                                                        /*!< SCT CONFLAG: BUSERRL Position       */
+#define SCT_CONFLAG_BUSERRL_Msk                               (0x01UL << SCT_CONFLAG_BUSERRL_Pos)                       /*!< SCT CONFLAG: BUSERRL Mask           */
+#define SCT_CONFLAG_BUSERRH_Pos                               31                                                        /*!< SCT CONFLAG: BUSERRH Position       */
+#define SCT_CONFLAG_BUSERRH_Msk                               (0x01UL << SCT_CONFLAG_BUSERRH_Pos)                       /*!< SCT CONFLAG: BUSERRH Mask           */
+
+// ---------------------------------------  SCT_MATCH0  -------------------------------------------
+#define SCT_MATCH0_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH0: MATCHn_L Position       */
+#define SCT_MATCH0_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos)                 /*!< SCT MATCH0: MATCHn_L Mask           */
+#define SCT_MATCH0_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH0: MATCHn_H Position       */
+#define SCT_MATCH0_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos)                 /*!< SCT MATCH0: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP0  --------------------------------------------
+#define SCT_CAP0_CAPn_L_Pos                                   0                                                         /*!< SCT CAP0: CAPn_L Position           */
+#define SCT_CAP0_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos)                     /*!< SCT CAP0: CAPn_L Mask               */
+#define SCT_CAP0_CAPn_H_Pos                                   16                                                        /*!< SCT CAP0: CAPn_H Position           */
+#define SCT_CAP0_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos)                     /*!< SCT CAP0: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH1  -------------------------------------------
+#define SCT_MATCH1_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH1: MATCHn_L Position       */
+#define SCT_MATCH1_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos)                 /*!< SCT MATCH1: MATCHn_L Mask           */
+#define SCT_MATCH1_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH1: MATCHn_H Position       */
+#define SCT_MATCH1_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos)                 /*!< SCT MATCH1: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP1  --------------------------------------------
+#define SCT_CAP1_CAPn_L_Pos                                   0                                                         /*!< SCT CAP1: CAPn_L Position           */
+#define SCT_CAP1_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos)                     /*!< SCT CAP1: CAPn_L Mask               */
+#define SCT_CAP1_CAPn_H_Pos                                   16                                                        /*!< SCT CAP1: CAPn_H Position           */
+#define SCT_CAP1_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos)                     /*!< SCT CAP1: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH2  -------------------------------------------
+#define SCT_MATCH2_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH2: MATCHn_L Position       */
+#define SCT_MATCH2_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos)                 /*!< SCT MATCH2: MATCHn_L Mask           */
+#define SCT_MATCH2_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH2: MATCHn_H Position       */
+#define SCT_MATCH2_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos)                 /*!< SCT MATCH2: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP2  --------------------------------------------
+#define SCT_CAP2_CAPn_L_Pos                                   0                                                         /*!< SCT CAP2: CAPn_L Position           */
+#define SCT_CAP2_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos)                     /*!< SCT CAP2: CAPn_L Mask               */
+#define SCT_CAP2_CAPn_H_Pos                                   16                                                        /*!< SCT CAP2: CAPn_H Position           */
+#define SCT_CAP2_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos)                     /*!< SCT CAP2: CAPn_H Mask               */
+
+// ----------------------------------------  SCT_CAP3  --------------------------------------------
+#define SCT_CAP3_CAPn_L_Pos                                   0                                                         /*!< SCT CAP3: CAPn_L Position           */
+#define SCT_CAP3_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos)                     /*!< SCT CAP3: CAPn_L Mask               */
+#define SCT_CAP3_CAPn_H_Pos                                   16                                                        /*!< SCT CAP3: CAPn_H Position           */
+#define SCT_CAP3_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos)                     /*!< SCT CAP3: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH3  -------------------------------------------
+#define SCT_MATCH3_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH3: MATCHn_L Position       */
+#define SCT_MATCH3_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos)                 /*!< SCT MATCH3: MATCHn_L Mask           */
+#define SCT_MATCH3_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH3: MATCHn_H Position       */
+#define SCT_MATCH3_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos)                 /*!< SCT MATCH3: MATCHn_H Mask           */
+
+// ---------------------------------------  SCT_MATCH4  -------------------------------------------
+#define SCT_MATCH4_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH4: MATCHn_L Position       */
+#define SCT_MATCH4_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos)                 /*!< SCT MATCH4: MATCHn_L Mask           */
+#define SCT_MATCH4_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH4: MATCHn_H Position       */
+#define SCT_MATCH4_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos)                 /*!< SCT MATCH4: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP4  --------------------------------------------
+#define SCT_CAP4_CAPn_L_Pos                                   0                                                         /*!< SCT CAP4: CAPn_L Position           */
+#define SCT_CAP4_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos)                     /*!< SCT CAP4: CAPn_L Mask               */
+#define SCT_CAP4_CAPn_H_Pos                                   16                                                        /*!< SCT CAP4: CAPn_H Position           */
+#define SCT_CAP4_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos)                     /*!< SCT CAP4: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH5  -------------------------------------------
+#define SCT_MATCH5_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH5: MATCHn_L Position       */
+#define SCT_MATCH5_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos)                 /*!< SCT MATCH5: MATCHn_L Mask           */
+#define SCT_MATCH5_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH5: MATCHn_H Position       */
+#define SCT_MATCH5_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos)                 /*!< SCT MATCH5: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP5  --------------------------------------------
+#define SCT_CAP5_CAPn_L_Pos                                   0                                                         /*!< SCT CAP5: CAPn_L Position           */
+#define SCT_CAP5_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos)                     /*!< SCT CAP5: CAPn_L Mask               */
+#define SCT_CAP5_CAPn_H_Pos                                   16                                                        /*!< SCT CAP5: CAPn_H Position           */
+#define SCT_CAP5_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos)                     /*!< SCT CAP5: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH6  -------------------------------------------
+#define SCT_MATCH6_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH6: MATCHn_L Position       */
+#define SCT_MATCH6_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos)                 /*!< SCT MATCH6: MATCHn_L Mask           */
+#define SCT_MATCH6_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH6: MATCHn_H Position       */
+#define SCT_MATCH6_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos)                 /*!< SCT MATCH6: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP6  --------------------------------------------
+#define SCT_CAP6_CAPn_L_Pos                                   0                                                         /*!< SCT CAP6: CAPn_L Position           */
+#define SCT_CAP6_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos)                     /*!< SCT CAP6: CAPn_L Mask               */
+#define SCT_CAP6_CAPn_H_Pos                                   16                                                        /*!< SCT CAP6: CAPn_H Position           */
+#define SCT_CAP6_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos)                     /*!< SCT CAP6: CAPn_H Mask               */
+
+// ----------------------------------------  SCT_CAP7  --------------------------------------------
+#define SCT_CAP7_CAPn_L_Pos                                   0                                                         /*!< SCT CAP7: CAPn_L Position           */
+#define SCT_CAP7_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos)                     /*!< SCT CAP7: CAPn_L Mask               */
+#define SCT_CAP7_CAPn_H_Pos                                   16                                                        /*!< SCT CAP7: CAPn_H Position           */
+#define SCT_CAP7_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos)                     /*!< SCT CAP7: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH7  -------------------------------------------
+#define SCT_MATCH7_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH7: MATCHn_L Position       */
+#define SCT_MATCH7_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos)                 /*!< SCT MATCH7: MATCHn_L Mask           */
+#define SCT_MATCH7_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH7: MATCHn_H Position       */
+#define SCT_MATCH7_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos)                 /*!< SCT MATCH7: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP8  --------------------------------------------
+#define SCT_CAP8_CAPn_L_Pos                                   0                                                         /*!< SCT CAP8: CAPn_L Position           */
+#define SCT_CAP8_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos)                     /*!< SCT CAP8: CAPn_L Mask               */
+#define SCT_CAP8_CAPn_H_Pos                                   16                                                        /*!< SCT CAP8: CAPn_H Position           */
+#define SCT_CAP8_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos)                     /*!< SCT CAP8: CAPn_H Mask               */
+
+// ---------------------------------------  SCT_MATCH8  -------------------------------------------
+#define SCT_MATCH8_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH8: MATCHn_L Position       */
+#define SCT_MATCH8_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos)                 /*!< SCT MATCH8: MATCHn_L Mask           */
+#define SCT_MATCH8_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH8: MATCHn_H Position       */
+#define SCT_MATCH8_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos)                 /*!< SCT MATCH8: MATCHn_H Mask           */
+
+// ---------------------------------------  SCT_MATCH9  -------------------------------------------
+#define SCT_MATCH9_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH9: MATCHn_L Position       */
+#define SCT_MATCH9_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos)                 /*!< SCT MATCH9: MATCHn_L Mask           */
+#define SCT_MATCH9_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH9: MATCHn_H Position       */
+#define SCT_MATCH9_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos)                 /*!< SCT MATCH9: MATCHn_H Mask           */
+
+// ----------------------------------------  SCT_CAP9  --------------------------------------------
+#define SCT_CAP9_CAPn_L_Pos                                   0                                                         /*!< SCT CAP9: CAPn_L Position           */
+#define SCT_CAP9_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos)                     /*!< SCT CAP9: CAPn_L Mask               */
+#define SCT_CAP9_CAPn_H_Pos                                   16                                                        /*!< SCT CAP9: CAPn_H Position           */
+#define SCT_CAP9_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos)                     /*!< SCT CAP9: CAPn_H Mask               */
+
+// ----------------------------------------  SCT_CAP10  -------------------------------------------
+#define SCT_CAP10_CAPn_L_Pos                                  0                                                         /*!< SCT CAP10: CAPn_L Position          */
+#define SCT_CAP10_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos)                    /*!< SCT CAP10: CAPn_L Mask              */
+#define SCT_CAP10_CAPn_H_Pos                                  16                                                        /*!< SCT CAP10: CAPn_H Position          */
+#define SCT_CAP10_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos)                    /*!< SCT CAP10: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH10  ------------------------------------------
+#define SCT_MATCH10_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH10: MATCHn_L Position      */
+#define SCT_MATCH10_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos)                /*!< SCT MATCH10: MATCHn_L Mask          */
+#define SCT_MATCH10_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH10: MATCHn_H Position      */
+#define SCT_MATCH10_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos)                /*!< SCT MATCH10: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP11  -------------------------------------------
+#define SCT_CAP11_CAPn_L_Pos                                  0                                                         /*!< SCT CAP11: CAPn_L Position          */
+#define SCT_CAP11_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos)                    /*!< SCT CAP11: CAPn_L Mask              */
+#define SCT_CAP11_CAPn_H_Pos                                  16                                                        /*!< SCT CAP11: CAPn_H Position          */
+#define SCT_CAP11_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos)                    /*!< SCT CAP11: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH11  ------------------------------------------
+#define SCT_MATCH11_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH11: MATCHn_L Position      */
+#define SCT_MATCH11_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos)                /*!< SCT MATCH11: MATCHn_L Mask          */
+#define SCT_MATCH11_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH11: MATCHn_H Position      */
+#define SCT_MATCH11_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos)                /*!< SCT MATCH11: MATCHn_H Mask          */
+
+// ---------------------------------------  SCT_MATCH12  ------------------------------------------
+#define SCT_MATCH12_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH12: MATCHn_L Position      */
+#define SCT_MATCH12_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos)                /*!< SCT MATCH12: MATCHn_L Mask          */
+#define SCT_MATCH12_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH12: MATCHn_H Position      */
+#define SCT_MATCH12_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos)                /*!< SCT MATCH12: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP12  -------------------------------------------
+#define SCT_CAP12_CAPn_L_Pos                                  0                                                         /*!< SCT CAP12: CAPn_L Position          */
+#define SCT_CAP12_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos)                    /*!< SCT CAP12: CAPn_L Mask              */
+#define SCT_CAP12_CAPn_H_Pos                                  16                                                        /*!< SCT CAP12: CAPn_H Position          */
+#define SCT_CAP12_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos)                    /*!< SCT CAP12: CAPn_H Mask              */
+
+// ----------------------------------------  SCT_CAP13  -------------------------------------------
+#define SCT_CAP13_CAPn_L_Pos                                  0                                                         /*!< SCT CAP13: CAPn_L Position          */
+#define SCT_CAP13_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos)                    /*!< SCT CAP13: CAPn_L Mask              */
+#define SCT_CAP13_CAPn_H_Pos                                  16                                                        /*!< SCT CAP13: CAPn_H Position          */
+#define SCT_CAP13_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos)                    /*!< SCT CAP13: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH13  ------------------------------------------
+#define SCT_MATCH13_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH13: MATCHn_L Position      */
+#define SCT_MATCH13_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos)                /*!< SCT MATCH13: MATCHn_L Mask          */
+#define SCT_MATCH13_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH13: MATCHn_H Position      */
+#define SCT_MATCH13_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos)                /*!< SCT MATCH13: MATCHn_H Mask          */
+
+// ---------------------------------------  SCT_MATCH14  ------------------------------------------
+#define SCT_MATCH14_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH14: MATCHn_L Position      */
+#define SCT_MATCH14_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos)                /*!< SCT MATCH14: MATCHn_L Mask          */
+#define SCT_MATCH14_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH14: MATCHn_H Position      */
+#define SCT_MATCH14_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos)                /*!< SCT MATCH14: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP14  -------------------------------------------
+#define SCT_CAP14_CAPn_L_Pos                                  0                                                         /*!< SCT CAP14: CAPn_L Position          */
+#define SCT_CAP14_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos)                    /*!< SCT CAP14: CAPn_L Mask              */
+#define SCT_CAP14_CAPn_H_Pos                                  16                                                        /*!< SCT CAP14: CAPn_H Position          */
+#define SCT_CAP14_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos)                    /*!< SCT CAP14: CAPn_H Mask              */
+
+// ---------------------------------------  SCT_MATCH15  ------------------------------------------
+#define SCT_MATCH15_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH15: MATCHn_L Position      */
+#define SCT_MATCH15_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos)                /*!< SCT MATCH15: MATCHn_L Mask          */
+#define SCT_MATCH15_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH15: MATCHn_H Position      */
+#define SCT_MATCH15_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos)                /*!< SCT MATCH15: MATCHn_H Mask          */
+
+// ----------------------------------------  SCT_CAP15  -------------------------------------------
+#define SCT_CAP15_CAPn_L_Pos                                  0                                                         /*!< SCT CAP15: CAPn_L Position          */
+#define SCT_CAP15_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos)                    /*!< SCT CAP15: CAPn_L Mask              */
+#define SCT_CAP15_CAPn_H_Pos                                  16                                                        /*!< SCT CAP15: CAPn_H Position          */
+#define SCT_CAP15_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos)                    /*!< SCT CAP15: CAPn_H Mask              */
+
+// --------------------------------------  SCT_MATCHREL0  -----------------------------------------
+#define SCT_MATCHREL0_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL0: RELOADn_L Position   */
+#define SCT_MATCHREL0_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos)             /*!< SCT MATCHREL0: RELOADn_L Mask       */
+#define SCT_MATCHREL0_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL0: RELOADn_H Position   */
+#define SCT_MATCHREL0_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos)             /*!< SCT MATCHREL0: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL0  ------------------------------------------
+#define SCT_CAPCTRL0_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL0: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL0: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL0: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL0: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL0: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL0: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL0: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL0: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL0: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL0: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL0_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL0_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL0: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL0: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL0: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL0: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL0: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL0: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL0_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL0_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL0: CAPCONn_H Position    */
+#define SCT_CAPCTRL0_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos)              /*!< SCT CAPCTRL0: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL1  -----------------------------------------
+#define SCT_MATCHREL1_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL1: RELOADn_L Position   */
+#define SCT_MATCHREL1_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos)             /*!< SCT MATCHREL1: RELOADn_L Mask       */
+#define SCT_MATCHREL1_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL1: RELOADn_H Position   */
+#define SCT_MATCHREL1_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos)             /*!< SCT MATCHREL1: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL1  ------------------------------------------
+#define SCT_CAPCTRL1_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL1: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL1: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL1: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL1: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL1: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL1: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL1: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL1: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL1: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL1: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL1_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL1_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL1: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL1: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL1: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL1: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL1: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL1: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL1_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL1_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL1: CAPCONn_H Position    */
+#define SCT_CAPCTRL1_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos)              /*!< SCT CAPCTRL1: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL2  -----------------------------------------
+#define SCT_MATCHREL2_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL2: RELOADn_L Position   */
+#define SCT_MATCHREL2_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos)             /*!< SCT MATCHREL2: RELOADn_L Mask       */
+#define SCT_MATCHREL2_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL2: RELOADn_H Position   */
+#define SCT_MATCHREL2_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos)             /*!< SCT MATCHREL2: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL2  ------------------------------------------
+#define SCT_CAPCTRL2_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL2: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL2: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL2: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL2: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL2: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL2: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL2: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL2: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL2: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL2: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL2_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL2_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL2: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL2: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL2: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL2: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL2: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL2: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL2_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL2_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL2: CAPCONn_H Position    */
+#define SCT_CAPCTRL2_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos)              /*!< SCT CAPCTRL2: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL3  -----------------------------------------
+#define SCT_MATCHREL3_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL3: RELOADn_L Position   */
+#define SCT_MATCHREL3_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos)             /*!< SCT MATCHREL3: RELOADn_L Mask       */
+#define SCT_MATCHREL3_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL3: RELOADn_H Position   */
+#define SCT_MATCHREL3_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos)             /*!< SCT MATCHREL3: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL3  ------------------------------------------
+#define SCT_CAPCTRL3_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL3: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL3: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL3: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL3: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL3: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL3: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL3: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL3: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL3: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL3: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL3_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL3_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL3: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL3: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL3: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL3: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL3: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL3: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL3_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL3_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL3: CAPCONn_H Position    */
+#define SCT_CAPCTRL3_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos)              /*!< SCT CAPCTRL3: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_CAPCTRL4  ------------------------------------------
+#define SCT_CAPCTRL4_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL4: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL4: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL4: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL4: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL4: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL4: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL4: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL4: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL4: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL4: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL4_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL4_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL4: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL4: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL4: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL4: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL4: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL4: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL4_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL4_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL4: CAPCONn_H Position    */
+#define SCT_CAPCTRL4_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos)              /*!< SCT CAPCTRL4: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL4  -----------------------------------------
+#define SCT_MATCHREL4_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL4: RELOADn_L Position   */
+#define SCT_MATCHREL4_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos)             /*!< SCT MATCHREL4: RELOADn_L Mask       */
+#define SCT_MATCHREL4_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL4: RELOADn_H Position   */
+#define SCT_MATCHREL4_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos)             /*!< SCT MATCHREL4: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL5  ------------------------------------------
+#define SCT_CAPCTRL5_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL5: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL5: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL5: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL5: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL5: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL5: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL5: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL5: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL5: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL5: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL5_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL5_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL5: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL5: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL5: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL5: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL5: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL5: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL5_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL5_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL5: CAPCONn_H Position    */
+#define SCT_CAPCTRL5_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos)              /*!< SCT CAPCTRL5: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL5  -----------------------------------------
+#define SCT_MATCHREL5_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL5: RELOADn_L Position   */
+#define SCT_MATCHREL5_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos)             /*!< SCT MATCHREL5: RELOADn_L Mask       */
+#define SCT_MATCHREL5_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL5: RELOADn_H Position   */
+#define SCT_MATCHREL5_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos)             /*!< SCT MATCHREL5: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_MATCHREL6  -----------------------------------------
+#define SCT_MATCHREL6_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL6: RELOADn_L Position   */
+#define SCT_MATCHREL6_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos)             /*!< SCT MATCHREL6: RELOADn_L Mask       */
+#define SCT_MATCHREL6_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL6: RELOADn_H Position   */
+#define SCT_MATCHREL6_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos)             /*!< SCT MATCHREL6: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL6  ------------------------------------------
+#define SCT_CAPCTRL6_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL6: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL6: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL6: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL6: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL6: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL6: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL6: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL6: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL6: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL6: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL6_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL6_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL6: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL6: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL6: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL6: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL6: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL6: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL6_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL6_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL6: CAPCONn_H Position    */
+#define SCT_CAPCTRL6_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos)              /*!< SCT CAPCTRL6: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_CAPCTRL7  ------------------------------------------
+#define SCT_CAPCTRL7_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL7: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL7: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL7: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL7: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL7: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL7: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL7: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL7: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL7: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL7: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL7_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL7_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL7: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL7: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL7: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL7: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL7: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL7: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL7_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL7_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL7: CAPCONn_H Position    */
+#define SCT_CAPCTRL7_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos)              /*!< SCT CAPCTRL7: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL7  -----------------------------------------
+#define SCT_MATCHREL7_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL7: RELOADn_L Position   */
+#define SCT_MATCHREL7_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos)             /*!< SCT MATCHREL7: RELOADn_L Mask       */
+#define SCT_MATCHREL7_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL7: RELOADn_H Position   */
+#define SCT_MATCHREL7_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos)             /*!< SCT MATCHREL7: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL8  ------------------------------------------
+#define SCT_CAPCTRL8_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL8: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL8: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL8: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL8: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL8: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL8: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL8: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL8: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL8: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL8: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL8_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL8_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL8: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL8: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL8: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL8: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL8: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL8: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL8_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL8_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL8: CAPCONn_H Position    */
+#define SCT_CAPCTRL8_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos)              /*!< SCT CAPCTRL8: CAPCONn_H Mask        */
+
+// --------------------------------------  SCT_MATCHREL8  -----------------------------------------
+#define SCT_MATCHREL8_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL8: RELOADn_L Position   */
+#define SCT_MATCHREL8_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos)             /*!< SCT MATCHREL8: RELOADn_L Mask       */
+#define SCT_MATCHREL8_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL8: RELOADn_H Position   */
+#define SCT_MATCHREL8_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos)             /*!< SCT MATCHREL8: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_MATCHREL9  -----------------------------------------
+#define SCT_MATCHREL9_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL9: RELOADn_L Position   */
+#define SCT_MATCHREL9_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos)             /*!< SCT MATCHREL9: RELOADn_L Mask       */
+#define SCT_MATCHREL9_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL9: RELOADn_H Position   */
+#define SCT_MATCHREL9_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos)             /*!< SCT MATCHREL9: RELOADn_H Mask       */
+
+// --------------------------------------  SCT_CAPCTRL9  ------------------------------------------
+#define SCT_CAPCTRL9_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL9: CAPCONn_L0 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L0 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL9: CAPCONn_L1 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L1 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL9: CAPCONn_L2 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L2 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL9: CAPCONn_L3 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L3 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL9: CAPCONn_L4 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L4 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL9: CAPCONn_L5 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L5 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL9: CAPCONn_L6 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L6 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL9: CAPCONn_L7 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L7 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL9: CAPCONn_L8 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L8 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL9: CAPCONn_L9 Position   */
+#define SCT_CAPCTRL9_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L9 Mask       */
+#define SCT_CAPCTRL9_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL9: CAPCONn_L10 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L10 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL9: CAPCONn_L11 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L11 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL9: CAPCONn_L12 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L12 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL9: CAPCONn_L13 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L13 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL9: CAPCONn_L14 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L14 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL9: CAPCONn_L15 Position  */
+#define SCT_CAPCTRL9_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L15 Mask      */
+#define SCT_CAPCTRL9_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL9: CAPCONn_H Position    */
+#define SCT_CAPCTRL9_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos)              /*!< SCT CAPCTRL9: CAPCONn_H Mask        */
+
+// -------------------------------------  SCT_MATCHREL10  -----------------------------------------
+#define SCT_MATCHREL10_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL10: RELOADn_L Position  */
+#define SCT_MATCHREL10_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos)            /*!< SCT MATCHREL10: RELOADn_L Mask      */
+#define SCT_MATCHREL10_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL10: RELOADn_H Position  */
+#define SCT_MATCHREL10_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos)            /*!< SCT MATCHREL10: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL10  -----------------------------------------
+#define SCT_CAPCTRL10_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL10: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL10: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL10: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL10: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL10: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL10: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL10: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL10: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL10: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL10: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL10_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL10_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL10: CAPCONn_L10 Position */
+#define SCT_CAPCTRL10_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL10: CAPCONn_L11 Position */
+#define SCT_CAPCTRL10_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL10: CAPCONn_L12 Position */
+#define SCT_CAPCTRL10_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL10: CAPCONn_L13 Position */
+#define SCT_CAPCTRL10_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL10: CAPCONn_L14 Position */
+#define SCT_CAPCTRL10_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL10: CAPCONn_L15 Position */
+#define SCT_CAPCTRL10_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL10_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL10: CAPCONn_H Position   */
+#define SCT_CAPCTRL10_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos)             /*!< SCT CAPCTRL10: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL11  -----------------------------------------
+#define SCT_MATCHREL11_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL11: RELOADn_L Position  */
+#define SCT_MATCHREL11_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos)            /*!< SCT MATCHREL11: RELOADn_L Mask      */
+#define SCT_MATCHREL11_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL11: RELOADn_H Position  */
+#define SCT_MATCHREL11_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos)            /*!< SCT MATCHREL11: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL11  -----------------------------------------
+#define SCT_CAPCTRL11_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL11: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL11: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL11: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL11: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL11: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL11: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL11: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL11: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL11: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL11: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL11_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL11_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL11: CAPCONn_L10 Position */
+#define SCT_CAPCTRL11_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL11: CAPCONn_L11 Position */
+#define SCT_CAPCTRL11_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL11: CAPCONn_L12 Position */
+#define SCT_CAPCTRL11_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL11: CAPCONn_L13 Position */
+#define SCT_CAPCTRL11_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL11: CAPCONn_L14 Position */
+#define SCT_CAPCTRL11_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL11: CAPCONn_L15 Position */
+#define SCT_CAPCTRL11_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL11_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL11: CAPCONn_H Position   */
+#define SCT_CAPCTRL11_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos)             /*!< SCT CAPCTRL11: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL12  -----------------------------------------
+#define SCT_MATCHREL12_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL12: RELOADn_L Position  */
+#define SCT_MATCHREL12_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos)            /*!< SCT MATCHREL12: RELOADn_L Mask      */
+#define SCT_MATCHREL12_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL12: RELOADn_H Position  */
+#define SCT_MATCHREL12_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos)            /*!< SCT MATCHREL12: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL12  -----------------------------------------
+#define SCT_CAPCTRL12_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL12: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL12: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL12: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL12: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL12: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL12: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL12: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL12: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL12: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL12: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL12_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL12_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL12: CAPCONn_L10 Position */
+#define SCT_CAPCTRL12_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL12: CAPCONn_L11 Position */
+#define SCT_CAPCTRL12_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL12: CAPCONn_L12 Position */
+#define SCT_CAPCTRL12_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL12: CAPCONn_L13 Position */
+#define SCT_CAPCTRL12_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL12: CAPCONn_L14 Position */
+#define SCT_CAPCTRL12_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL12: CAPCONn_L15 Position */
+#define SCT_CAPCTRL12_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL12_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL12: CAPCONn_H Position   */
+#define SCT_CAPCTRL12_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos)             /*!< SCT CAPCTRL12: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL13  -----------------------------------------
+#define SCT_MATCHREL13_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL13: RELOADn_L Position  */
+#define SCT_MATCHREL13_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos)            /*!< SCT MATCHREL13: RELOADn_L Mask      */
+#define SCT_MATCHREL13_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL13: RELOADn_H Position  */
+#define SCT_MATCHREL13_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos)            /*!< SCT MATCHREL13: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL13  -----------------------------------------
+#define SCT_CAPCTRL13_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL13: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL13: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL13: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL13: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL13: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL13: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL13: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL13: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL13: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL13: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL13_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL13_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL13: CAPCONn_L10 Position */
+#define SCT_CAPCTRL13_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL13: CAPCONn_L11 Position */
+#define SCT_CAPCTRL13_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL13: CAPCONn_L12 Position */
+#define SCT_CAPCTRL13_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL13: CAPCONn_L13 Position */
+#define SCT_CAPCTRL13_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL13: CAPCONn_L14 Position */
+#define SCT_CAPCTRL13_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL13: CAPCONn_L15 Position */
+#define SCT_CAPCTRL13_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL13_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL13: CAPCONn_H Position   */
+#define SCT_CAPCTRL13_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos)             /*!< SCT CAPCTRL13: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL14  -----------------------------------------
+#define SCT_MATCHREL14_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL14: RELOADn_L Position  */
+#define SCT_MATCHREL14_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos)            /*!< SCT MATCHREL14: RELOADn_L Mask      */
+#define SCT_MATCHREL14_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL14: RELOADn_H Position  */
+#define SCT_MATCHREL14_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos)            /*!< SCT MATCHREL14: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL14  -----------------------------------------
+#define SCT_CAPCTRL14_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL14: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL14: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL14: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL14: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL14: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL14: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL14: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL14: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL14: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL14: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL14_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL14_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL14: CAPCONn_L10 Position */
+#define SCT_CAPCTRL14_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL14: CAPCONn_L11 Position */
+#define SCT_CAPCTRL14_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL14: CAPCONn_L12 Position */
+#define SCT_CAPCTRL14_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL14: CAPCONn_L13 Position */
+#define SCT_CAPCTRL14_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL14: CAPCONn_L14 Position */
+#define SCT_CAPCTRL14_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL14: CAPCONn_L15 Position */
+#define SCT_CAPCTRL14_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL14_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL14: CAPCONn_H Position   */
+#define SCT_CAPCTRL14_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos)             /*!< SCT CAPCTRL14: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_MATCHREL15  -----------------------------------------
+#define SCT_MATCHREL15_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL15: RELOADn_L Position  */
+#define SCT_MATCHREL15_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos)            /*!< SCT MATCHREL15: RELOADn_L Mask      */
+#define SCT_MATCHREL15_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL15: RELOADn_H Position  */
+#define SCT_MATCHREL15_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos)            /*!< SCT MATCHREL15: RELOADn_H Mask      */
+
+// --------------------------------------  SCT_CAPCTRL15  -----------------------------------------
+#define SCT_CAPCTRL15_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL15: CAPCONn_L0 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L0 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL15: CAPCONn_L1 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L1 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL15: CAPCONn_L2 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L2 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL15: CAPCONn_L3 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L3 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL15: CAPCONn_L4 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L4 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL15: CAPCONn_L5 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L5 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL15: CAPCONn_L6 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L6 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL15: CAPCONn_L7 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L7 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL15: CAPCONn_L8 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L8 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL15: CAPCONn_L9 Position  */
+#define SCT_CAPCTRL15_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L9 Mask      */
+#define SCT_CAPCTRL15_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL15: CAPCONn_L10 Position */
+#define SCT_CAPCTRL15_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L10 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL15: CAPCONn_L11 Position */
+#define SCT_CAPCTRL15_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L11 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL15: CAPCONn_L12 Position */
+#define SCT_CAPCTRL15_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L12 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL15: CAPCONn_L13 Position */
+#define SCT_CAPCTRL15_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L13 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL15: CAPCONn_L14 Position */
+#define SCT_CAPCTRL15_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L14 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL15: CAPCONn_L15 Position */
+#define SCT_CAPCTRL15_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L15 Mask     */
+#define SCT_CAPCTRL15_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL15: CAPCONn_H Position   */
+#define SCT_CAPCTRL15_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos)             /*!< SCT CAPCTRL15: CAPCONn_H Mask       */
+
+// -------------------------------------  SCT_EVSTATEMSK0  ----------------------------------------
+#define SCT_EVSTATEMSK0_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL0  ------------------------------------------
+#define SCT_EVCTRL0_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL0: MATCHSEL Position      */
+#define SCT_EVCTRL0_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos)                      /*!< SCT EVCTRL0: MATCHSEL Mask          */
+#define SCT_EVCTRL0_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL0: HEVENT Position        */
+#define SCT_EVCTRL0_HEVENT_Msk                                (0x01UL << SCT_EVCTRL0_HEVENT_Pos)                        /*!< SCT EVCTRL0: HEVENT Mask            */
+#define SCT_EVCTRL0_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL0: OUTSEL Position        */
+#define SCT_EVCTRL0_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL0_OUTSEL_Pos)                        /*!< SCT EVCTRL0: OUTSEL Mask            */
+#define SCT_EVCTRL0_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL0: IOSEL Position         */
+#define SCT_EVCTRL0_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL0_IOSEL_Pos)                         /*!< SCT EVCTRL0: IOSEL Mask             */
+#define SCT_EVCTRL0_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL0: IOCOND Position        */
+#define SCT_EVCTRL0_IOCOND_Msk                                (0x03UL << SCT_EVCTRL0_IOCOND_Pos)                        /*!< SCT EVCTRL0: IOCOND Mask            */
+#define SCT_EVCTRL0_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL0: COMBMODE Position      */
+#define SCT_EVCTRL0_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL0_COMBMODE_Pos)                      /*!< SCT EVCTRL0: COMBMODE Mask          */
+#define SCT_EVCTRL0_STATELD_Pos                               14                                                        /*!< SCT EVCTRL0: STATELD Position       */
+#define SCT_EVCTRL0_STATELD_Msk                               (0x01UL << SCT_EVCTRL0_STATELD_Pos)                       /*!< SCT EVCTRL0: STATELD Mask           */
+#define SCT_EVCTRL0_STATEV_Pos                                15                                                        /*!< SCT EVCTRL0: STATEV Position        */
+#define SCT_EVCTRL0_STATEV_Msk                                (0x1fUL << SCT_EVCTRL0_STATEV_Pos)                        /*!< SCT EVCTRL0: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK1  ----------------------------------------
+#define SCT_EVSTATEMSK1_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL1  ------------------------------------------
+#define SCT_EVCTRL1_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL1: MATCHSEL Position      */
+#define SCT_EVCTRL1_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos)                      /*!< SCT EVCTRL1: MATCHSEL Mask          */
+#define SCT_EVCTRL1_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL1: HEVENT Position        */
+#define SCT_EVCTRL1_HEVENT_Msk                                (0x01UL << SCT_EVCTRL1_HEVENT_Pos)                        /*!< SCT EVCTRL1: HEVENT Mask            */
+#define SCT_EVCTRL1_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL1: OUTSEL Position        */
+#define SCT_EVCTRL1_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL1_OUTSEL_Pos)                        /*!< SCT EVCTRL1: OUTSEL Mask            */
+#define SCT_EVCTRL1_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL1: IOSEL Position         */
+#define SCT_EVCTRL1_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL1_IOSEL_Pos)                         /*!< SCT EVCTRL1: IOSEL Mask             */
+#define SCT_EVCTRL1_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL1: IOCOND Position        */
+#define SCT_EVCTRL1_IOCOND_Msk                                (0x03UL << SCT_EVCTRL1_IOCOND_Pos)                        /*!< SCT EVCTRL1: IOCOND Mask            */
+#define SCT_EVCTRL1_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL1: COMBMODE Position      */
+#define SCT_EVCTRL1_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL1_COMBMODE_Pos)                      /*!< SCT EVCTRL1: COMBMODE Mask          */
+#define SCT_EVCTRL1_STATELD_Pos                               14                                                        /*!< SCT EVCTRL1: STATELD Position       */
+#define SCT_EVCTRL1_STATELD_Msk                               (0x01UL << SCT_EVCTRL1_STATELD_Pos)                       /*!< SCT EVCTRL1: STATELD Mask           */
+#define SCT_EVCTRL1_STATEV_Pos                                15                                                        /*!< SCT EVCTRL1: STATEV Position        */
+#define SCT_EVCTRL1_STATEV_Msk                                (0x1fUL << SCT_EVCTRL1_STATEV_Pos)                        /*!< SCT EVCTRL1: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK2  ----------------------------------------
+#define SCT_EVSTATEMSK2_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL2  ------------------------------------------
+#define SCT_EVCTRL2_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL2: MATCHSEL Position      */
+#define SCT_EVCTRL2_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos)                      /*!< SCT EVCTRL2: MATCHSEL Mask          */
+#define SCT_EVCTRL2_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL2: HEVENT Position        */
+#define SCT_EVCTRL2_HEVENT_Msk                                (0x01UL << SCT_EVCTRL2_HEVENT_Pos)                        /*!< SCT EVCTRL2: HEVENT Mask            */
+#define SCT_EVCTRL2_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL2: OUTSEL Position        */
+#define SCT_EVCTRL2_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL2_OUTSEL_Pos)                        /*!< SCT EVCTRL2: OUTSEL Mask            */
+#define SCT_EVCTRL2_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL2: IOSEL Position         */
+#define SCT_EVCTRL2_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL2_IOSEL_Pos)                         /*!< SCT EVCTRL2: IOSEL Mask             */
+#define SCT_EVCTRL2_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL2: IOCOND Position        */
+#define SCT_EVCTRL2_IOCOND_Msk                                (0x03UL << SCT_EVCTRL2_IOCOND_Pos)                        /*!< SCT EVCTRL2: IOCOND Mask            */
+#define SCT_EVCTRL2_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL2: COMBMODE Position      */
+#define SCT_EVCTRL2_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL2_COMBMODE_Pos)                      /*!< SCT EVCTRL2: COMBMODE Mask          */
+#define SCT_EVCTRL2_STATELD_Pos                               14                                                        /*!< SCT EVCTRL2: STATELD Position       */
+#define SCT_EVCTRL2_STATELD_Msk                               (0x01UL << SCT_EVCTRL2_STATELD_Pos)                       /*!< SCT EVCTRL2: STATELD Mask           */
+#define SCT_EVCTRL2_STATEV_Pos                                15                                                        /*!< SCT EVCTRL2: STATEV Position        */
+#define SCT_EVCTRL2_STATEV_Msk                                (0x1fUL << SCT_EVCTRL2_STATEV_Pos)                        /*!< SCT EVCTRL2: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK3  ----------------------------------------
+#define SCT_EVSTATEMSK3_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL3  ------------------------------------------
+#define SCT_EVCTRL3_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL3: MATCHSEL Position      */
+#define SCT_EVCTRL3_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos)                      /*!< SCT EVCTRL3: MATCHSEL Mask          */
+#define SCT_EVCTRL3_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL3: HEVENT Position        */
+#define SCT_EVCTRL3_HEVENT_Msk                                (0x01UL << SCT_EVCTRL3_HEVENT_Pos)                        /*!< SCT EVCTRL3: HEVENT Mask            */
+#define SCT_EVCTRL3_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL3: OUTSEL Position        */
+#define SCT_EVCTRL3_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL3_OUTSEL_Pos)                        /*!< SCT EVCTRL3: OUTSEL Mask            */
+#define SCT_EVCTRL3_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL3: IOSEL Position         */
+#define SCT_EVCTRL3_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL3_IOSEL_Pos)                         /*!< SCT EVCTRL3: IOSEL Mask             */
+#define SCT_EVCTRL3_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL3: IOCOND Position        */
+#define SCT_EVCTRL3_IOCOND_Msk                                (0x03UL << SCT_EVCTRL3_IOCOND_Pos)                        /*!< SCT EVCTRL3: IOCOND Mask            */
+#define SCT_EVCTRL3_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL3: COMBMODE Position      */
+#define SCT_EVCTRL3_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL3_COMBMODE_Pos)                      /*!< SCT EVCTRL3: COMBMODE Mask          */
+#define SCT_EVCTRL3_STATELD_Pos                               14                                                        /*!< SCT EVCTRL3: STATELD Position       */
+#define SCT_EVCTRL3_STATELD_Msk                               (0x01UL << SCT_EVCTRL3_STATELD_Pos)                       /*!< SCT EVCTRL3: STATELD Mask           */
+#define SCT_EVCTRL3_STATEV_Pos                                15                                                        /*!< SCT EVCTRL3: STATEV Position        */
+#define SCT_EVCTRL3_STATEV_Msk                                (0x1fUL << SCT_EVCTRL3_STATEV_Pos)                        /*!< SCT EVCTRL3: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK4  ----------------------------------------
+#define SCT_EVSTATEMSK4_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL4  ------------------------------------------
+#define SCT_EVCTRL4_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL4: MATCHSEL Position      */
+#define SCT_EVCTRL4_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos)                      /*!< SCT EVCTRL4: MATCHSEL Mask          */
+#define SCT_EVCTRL4_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL4: HEVENT Position        */
+#define SCT_EVCTRL4_HEVENT_Msk                                (0x01UL << SCT_EVCTRL4_HEVENT_Pos)                        /*!< SCT EVCTRL4: HEVENT Mask            */
+#define SCT_EVCTRL4_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL4: OUTSEL Position        */
+#define SCT_EVCTRL4_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL4_OUTSEL_Pos)                        /*!< SCT EVCTRL4: OUTSEL Mask            */
+#define SCT_EVCTRL4_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL4: IOSEL Position         */
+#define SCT_EVCTRL4_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL4_IOSEL_Pos)                         /*!< SCT EVCTRL4: IOSEL Mask             */
+#define SCT_EVCTRL4_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL4: IOCOND Position        */
+#define SCT_EVCTRL4_IOCOND_Msk                                (0x03UL << SCT_EVCTRL4_IOCOND_Pos)                        /*!< SCT EVCTRL4: IOCOND Mask            */
+#define SCT_EVCTRL4_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL4: COMBMODE Position      */
+#define SCT_EVCTRL4_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL4_COMBMODE_Pos)                      /*!< SCT EVCTRL4: COMBMODE Mask          */
+#define SCT_EVCTRL4_STATELD_Pos                               14                                                        /*!< SCT EVCTRL4: STATELD Position       */
+#define SCT_EVCTRL4_STATELD_Msk                               (0x01UL << SCT_EVCTRL4_STATELD_Pos)                       /*!< SCT EVCTRL4: STATELD Mask           */
+#define SCT_EVCTRL4_STATEV_Pos                                15                                                        /*!< SCT EVCTRL4: STATEV Position        */
+#define SCT_EVCTRL4_STATEV_Msk                                (0x1fUL << SCT_EVCTRL4_STATEV_Pos)                        /*!< SCT EVCTRL4: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK5  ----------------------------------------
+#define SCT_EVSTATEMSK5_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL5  ------------------------------------------
+#define SCT_EVCTRL5_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL5: MATCHSEL Position      */
+#define SCT_EVCTRL5_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos)                      /*!< SCT EVCTRL5: MATCHSEL Mask          */
+#define SCT_EVCTRL5_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL5: HEVENT Position        */
+#define SCT_EVCTRL5_HEVENT_Msk                                (0x01UL << SCT_EVCTRL5_HEVENT_Pos)                        /*!< SCT EVCTRL5: HEVENT Mask            */
+#define SCT_EVCTRL5_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL5: OUTSEL Position        */
+#define SCT_EVCTRL5_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL5_OUTSEL_Pos)                        /*!< SCT EVCTRL5: OUTSEL Mask            */
+#define SCT_EVCTRL5_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL5: IOSEL Position         */
+#define SCT_EVCTRL5_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL5_IOSEL_Pos)                         /*!< SCT EVCTRL5: IOSEL Mask             */
+#define SCT_EVCTRL5_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL5: IOCOND Position        */
+#define SCT_EVCTRL5_IOCOND_Msk                                (0x03UL << SCT_EVCTRL5_IOCOND_Pos)                        /*!< SCT EVCTRL5: IOCOND Mask            */
+#define SCT_EVCTRL5_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL5: COMBMODE Position      */
+#define SCT_EVCTRL5_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL5_COMBMODE_Pos)                      /*!< SCT EVCTRL5: COMBMODE Mask          */
+#define SCT_EVCTRL5_STATELD_Pos                               14                                                        /*!< SCT EVCTRL5: STATELD Position       */
+#define SCT_EVCTRL5_STATELD_Msk                               (0x01UL << SCT_EVCTRL5_STATELD_Pos)                       /*!< SCT EVCTRL5: STATELD Mask           */
+#define SCT_EVCTRL5_STATEV_Pos                                15                                                        /*!< SCT EVCTRL5: STATEV Position        */
+#define SCT_EVCTRL5_STATEV_Msk                                (0x1fUL << SCT_EVCTRL5_STATEV_Pos)                        /*!< SCT EVCTRL5: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK6  ----------------------------------------
+#define SCT_EVSTATEMSK6_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL6  ------------------------------------------
+#define SCT_EVCTRL6_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL6: MATCHSEL Position      */
+#define SCT_EVCTRL6_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos)                      /*!< SCT EVCTRL6: MATCHSEL Mask          */
+#define SCT_EVCTRL6_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL6: HEVENT Position        */
+#define SCT_EVCTRL6_HEVENT_Msk                                (0x01UL << SCT_EVCTRL6_HEVENT_Pos)                        /*!< SCT EVCTRL6: HEVENT Mask            */
+#define SCT_EVCTRL6_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL6: OUTSEL Position        */
+#define SCT_EVCTRL6_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL6_OUTSEL_Pos)                        /*!< SCT EVCTRL6: OUTSEL Mask            */
+#define SCT_EVCTRL6_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL6: IOSEL Position         */
+#define SCT_EVCTRL6_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL6_IOSEL_Pos)                         /*!< SCT EVCTRL6: IOSEL Mask             */
+#define SCT_EVCTRL6_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL6: IOCOND Position        */
+#define SCT_EVCTRL6_IOCOND_Msk                                (0x03UL << SCT_EVCTRL6_IOCOND_Pos)                        /*!< SCT EVCTRL6: IOCOND Mask            */
+#define SCT_EVCTRL6_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL6: COMBMODE Position      */
+#define SCT_EVCTRL6_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL6_COMBMODE_Pos)                      /*!< SCT EVCTRL6: COMBMODE Mask          */
+#define SCT_EVCTRL6_STATELD_Pos                               14                                                        /*!< SCT EVCTRL6: STATELD Position       */
+#define SCT_EVCTRL6_STATELD_Msk                               (0x01UL << SCT_EVCTRL6_STATELD_Pos)                       /*!< SCT EVCTRL6: STATELD Mask           */
+#define SCT_EVCTRL6_STATEV_Pos                                15                                                        /*!< SCT EVCTRL6: STATEV Position        */
+#define SCT_EVCTRL6_STATEV_Msk                                (0x1fUL << SCT_EVCTRL6_STATEV_Pos)                        /*!< SCT EVCTRL6: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK7  ----------------------------------------
+#define SCT_EVSTATEMSK7_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL7  ------------------------------------------
+#define SCT_EVCTRL7_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL7: MATCHSEL Position      */
+#define SCT_EVCTRL7_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos)                      /*!< SCT EVCTRL7: MATCHSEL Mask          */
+#define SCT_EVCTRL7_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL7: HEVENT Position        */
+#define SCT_EVCTRL7_HEVENT_Msk                                (0x01UL << SCT_EVCTRL7_HEVENT_Pos)                        /*!< SCT EVCTRL7: HEVENT Mask            */
+#define SCT_EVCTRL7_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL7: OUTSEL Position        */
+#define SCT_EVCTRL7_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL7_OUTSEL_Pos)                        /*!< SCT EVCTRL7: OUTSEL Mask            */
+#define SCT_EVCTRL7_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL7: IOSEL Position         */
+#define SCT_EVCTRL7_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL7_IOSEL_Pos)                         /*!< SCT EVCTRL7: IOSEL Mask             */
+#define SCT_EVCTRL7_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL7: IOCOND Position        */
+#define SCT_EVCTRL7_IOCOND_Msk                                (0x03UL << SCT_EVCTRL7_IOCOND_Pos)                        /*!< SCT EVCTRL7: IOCOND Mask            */
+#define SCT_EVCTRL7_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL7: COMBMODE Position      */
+#define SCT_EVCTRL7_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL7_COMBMODE_Pos)                      /*!< SCT EVCTRL7: COMBMODE Mask          */
+#define SCT_EVCTRL7_STATELD_Pos                               14                                                        /*!< SCT EVCTRL7: STATELD Position       */
+#define SCT_EVCTRL7_STATELD_Msk                               (0x01UL << SCT_EVCTRL7_STATELD_Pos)                       /*!< SCT EVCTRL7: STATELD Mask           */
+#define SCT_EVCTRL7_STATEV_Pos                                15                                                        /*!< SCT EVCTRL7: STATEV Position        */
+#define SCT_EVCTRL7_STATEV_Msk                                (0x1fUL << SCT_EVCTRL7_STATEV_Pos)                        /*!< SCT EVCTRL7: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK8  ----------------------------------------
+#define SCT_EVSTATEMSK8_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL8  ------------------------------------------
+#define SCT_EVCTRL8_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL8: MATCHSEL Position      */
+#define SCT_EVCTRL8_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos)                      /*!< SCT EVCTRL8: MATCHSEL Mask          */
+#define SCT_EVCTRL8_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL8: HEVENT Position        */
+#define SCT_EVCTRL8_HEVENT_Msk                                (0x01UL << SCT_EVCTRL8_HEVENT_Pos)                        /*!< SCT EVCTRL8: HEVENT Mask            */
+#define SCT_EVCTRL8_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL8: OUTSEL Position        */
+#define SCT_EVCTRL8_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL8_OUTSEL_Pos)                        /*!< SCT EVCTRL8: OUTSEL Mask            */
+#define SCT_EVCTRL8_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL8: IOSEL Position         */
+#define SCT_EVCTRL8_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL8_IOSEL_Pos)                         /*!< SCT EVCTRL8: IOSEL Mask             */
+#define SCT_EVCTRL8_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL8: IOCOND Position        */
+#define SCT_EVCTRL8_IOCOND_Msk                                (0x03UL << SCT_EVCTRL8_IOCOND_Pos)                        /*!< SCT EVCTRL8: IOCOND Mask            */
+#define SCT_EVCTRL8_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL8: COMBMODE Position      */
+#define SCT_EVCTRL8_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL8_COMBMODE_Pos)                      /*!< SCT EVCTRL8: COMBMODE Mask          */
+#define SCT_EVCTRL8_STATELD_Pos                               14                                                        /*!< SCT EVCTRL8: STATELD Position       */
+#define SCT_EVCTRL8_STATELD_Msk                               (0x01UL << SCT_EVCTRL8_STATELD_Pos)                       /*!< SCT EVCTRL8: STATELD Mask           */
+#define SCT_EVCTRL8_STATEV_Pos                                15                                                        /*!< SCT EVCTRL8: STATEV Position        */
+#define SCT_EVCTRL8_STATEV_Msk                                (0x1fUL << SCT_EVCTRL8_STATEV_Pos)                        /*!< SCT EVCTRL8: STATEV Mask            */
+
+// -------------------------------------  SCT_EVSTATEMSK9  ----------------------------------------
+#define SCT_EVSTATEMSK9_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask    */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask   */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask   */
+
+// ---------------------------------------  SCT_EVCTRL9  ------------------------------------------
+#define SCT_EVCTRL9_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL9: MATCHSEL Position      */
+#define SCT_EVCTRL9_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos)                      /*!< SCT EVCTRL9: MATCHSEL Mask          */
+#define SCT_EVCTRL9_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL9: HEVENT Position        */
+#define SCT_EVCTRL9_HEVENT_Msk                                (0x01UL << SCT_EVCTRL9_HEVENT_Pos)                        /*!< SCT EVCTRL9: HEVENT Mask            */
+#define SCT_EVCTRL9_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL9: OUTSEL Position        */
+#define SCT_EVCTRL9_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL9_OUTSEL_Pos)                        /*!< SCT EVCTRL9: OUTSEL Mask            */
+#define SCT_EVCTRL9_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL9: IOSEL Position         */
+#define SCT_EVCTRL9_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL9_IOSEL_Pos)                         /*!< SCT EVCTRL9: IOSEL Mask             */
+#define SCT_EVCTRL9_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL9: IOCOND Position        */
+#define SCT_EVCTRL9_IOCOND_Msk                                (0x03UL << SCT_EVCTRL9_IOCOND_Pos)                        /*!< SCT EVCTRL9: IOCOND Mask            */
+#define SCT_EVCTRL9_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL9: COMBMODE Position      */
+#define SCT_EVCTRL9_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL9_COMBMODE_Pos)                      /*!< SCT EVCTRL9: COMBMODE Mask          */
+#define SCT_EVCTRL9_STATELD_Pos                               14                                                        /*!< SCT EVCTRL9: STATELD Position       */
+#define SCT_EVCTRL9_STATELD_Msk                               (0x01UL << SCT_EVCTRL9_STATELD_Pos)                       /*!< SCT EVCTRL9: STATELD Mask           */
+#define SCT_EVCTRL9_STATEV_Pos                                15                                                        /*!< SCT EVCTRL9: STATEV Position        */
+#define SCT_EVCTRL9_STATEV_Msk                                (0x1fUL << SCT_EVCTRL9_STATEV_Pos)                        /*!< SCT EVCTRL9: STATEV Mask            */
+
+// ------------------------------------  SCT_EVSTATEMSK10  ----------------------------------------
+#define SCT_EVSTATEMSK10_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL10  ------------------------------------------
+#define SCT_EVCTRL10_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL10: MATCHSEL Position     */
+#define SCT_EVCTRL10_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos)                     /*!< SCT EVCTRL10: MATCHSEL Mask         */
+#define SCT_EVCTRL10_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL10: HEVENT Position       */
+#define SCT_EVCTRL10_HEVENT_Msk                               (0x01UL << SCT_EVCTRL10_HEVENT_Pos)                       /*!< SCT EVCTRL10: HEVENT Mask           */
+#define SCT_EVCTRL10_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL10: OUTSEL Position       */
+#define SCT_EVCTRL10_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL10_OUTSEL_Pos)                       /*!< SCT EVCTRL10: OUTSEL Mask           */
+#define SCT_EVCTRL10_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL10: IOSEL Position        */
+#define SCT_EVCTRL10_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL10_IOSEL_Pos)                        /*!< SCT EVCTRL10: IOSEL Mask            */
+#define SCT_EVCTRL10_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL10: IOCOND Position       */
+#define SCT_EVCTRL10_IOCOND_Msk                               (0x03UL << SCT_EVCTRL10_IOCOND_Pos)                       /*!< SCT EVCTRL10: IOCOND Mask           */
+#define SCT_EVCTRL10_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL10: COMBMODE Position     */
+#define SCT_EVCTRL10_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL10_COMBMODE_Pos)                     /*!< SCT EVCTRL10: COMBMODE Mask         */
+#define SCT_EVCTRL10_STATELD_Pos                              14                                                        /*!< SCT EVCTRL10: STATELD Position      */
+#define SCT_EVCTRL10_STATELD_Msk                              (0x01UL << SCT_EVCTRL10_STATELD_Pos)                      /*!< SCT EVCTRL10: STATELD Mask          */
+#define SCT_EVCTRL10_STATEV_Pos                               15                                                        /*!< SCT EVCTRL10: STATEV Position       */
+#define SCT_EVCTRL10_STATEV_Msk                               (0x1fUL << SCT_EVCTRL10_STATEV_Pos)                       /*!< SCT EVCTRL10: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK11  ----------------------------------------
+#define SCT_EVSTATEMSK11_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL11  ------------------------------------------
+#define SCT_EVCTRL11_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL11: MATCHSEL Position     */
+#define SCT_EVCTRL11_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos)                     /*!< SCT EVCTRL11: MATCHSEL Mask         */
+#define SCT_EVCTRL11_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL11: HEVENT Position       */
+#define SCT_EVCTRL11_HEVENT_Msk                               (0x01UL << SCT_EVCTRL11_HEVENT_Pos)                       /*!< SCT EVCTRL11: HEVENT Mask           */
+#define SCT_EVCTRL11_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL11: OUTSEL Position       */
+#define SCT_EVCTRL11_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL11_OUTSEL_Pos)                       /*!< SCT EVCTRL11: OUTSEL Mask           */
+#define SCT_EVCTRL11_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL11: IOSEL Position        */
+#define SCT_EVCTRL11_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL11_IOSEL_Pos)                        /*!< SCT EVCTRL11: IOSEL Mask            */
+#define SCT_EVCTRL11_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL11: IOCOND Position       */
+#define SCT_EVCTRL11_IOCOND_Msk                               (0x03UL << SCT_EVCTRL11_IOCOND_Pos)                       /*!< SCT EVCTRL11: IOCOND Mask           */
+#define SCT_EVCTRL11_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL11: COMBMODE Position     */
+#define SCT_EVCTRL11_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL11_COMBMODE_Pos)                     /*!< SCT EVCTRL11: COMBMODE Mask         */
+#define SCT_EVCTRL11_STATELD_Pos                              14                                                        /*!< SCT EVCTRL11: STATELD Position      */
+#define SCT_EVCTRL11_STATELD_Msk                              (0x01UL << SCT_EVCTRL11_STATELD_Pos)                      /*!< SCT EVCTRL11: STATELD Mask          */
+#define SCT_EVCTRL11_STATEV_Pos                               15                                                        /*!< SCT EVCTRL11: STATEV Position       */
+#define SCT_EVCTRL11_STATEV_Msk                               (0x1fUL << SCT_EVCTRL11_STATEV_Pos)                       /*!< SCT EVCTRL11: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK12  ----------------------------------------
+#define SCT_EVSTATEMSK12_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL12  ------------------------------------------
+#define SCT_EVCTRL12_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL12: MATCHSEL Position     */
+#define SCT_EVCTRL12_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos)                     /*!< SCT EVCTRL12: MATCHSEL Mask         */
+#define SCT_EVCTRL12_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL12: HEVENT Position       */
+#define SCT_EVCTRL12_HEVENT_Msk                               (0x01UL << SCT_EVCTRL12_HEVENT_Pos)                       /*!< SCT EVCTRL12: HEVENT Mask           */
+#define SCT_EVCTRL12_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL12: OUTSEL Position       */
+#define SCT_EVCTRL12_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL12_OUTSEL_Pos)                       /*!< SCT EVCTRL12: OUTSEL Mask           */
+#define SCT_EVCTRL12_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL12: IOSEL Position        */
+#define SCT_EVCTRL12_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL12_IOSEL_Pos)                        /*!< SCT EVCTRL12: IOSEL Mask            */
+#define SCT_EVCTRL12_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL12: IOCOND Position       */
+#define SCT_EVCTRL12_IOCOND_Msk                               (0x03UL << SCT_EVCTRL12_IOCOND_Pos)                       /*!< SCT EVCTRL12: IOCOND Mask           */
+#define SCT_EVCTRL12_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL12: COMBMODE Position     */
+#define SCT_EVCTRL12_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL12_COMBMODE_Pos)                     /*!< SCT EVCTRL12: COMBMODE Mask         */
+#define SCT_EVCTRL12_STATELD_Pos                              14                                                        /*!< SCT EVCTRL12: STATELD Position      */
+#define SCT_EVCTRL12_STATELD_Msk                              (0x01UL << SCT_EVCTRL12_STATELD_Pos)                      /*!< SCT EVCTRL12: STATELD Mask          */
+#define SCT_EVCTRL12_STATEV_Pos                               15                                                        /*!< SCT EVCTRL12: STATEV Position       */
+#define SCT_EVCTRL12_STATEV_Msk                               (0x1fUL << SCT_EVCTRL12_STATEV_Pos)                       /*!< SCT EVCTRL12: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK13  ----------------------------------------
+#define SCT_EVSTATEMSK13_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL13  ------------------------------------------
+#define SCT_EVCTRL13_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL13: MATCHSEL Position     */
+#define SCT_EVCTRL13_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos)                     /*!< SCT EVCTRL13: MATCHSEL Mask         */
+#define SCT_EVCTRL13_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL13: HEVENT Position       */
+#define SCT_EVCTRL13_HEVENT_Msk                               (0x01UL << SCT_EVCTRL13_HEVENT_Pos)                       /*!< SCT EVCTRL13: HEVENT Mask           */
+#define SCT_EVCTRL13_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL13: OUTSEL Position       */
+#define SCT_EVCTRL13_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL13_OUTSEL_Pos)                       /*!< SCT EVCTRL13: OUTSEL Mask           */
+#define SCT_EVCTRL13_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL13: IOSEL Position        */
+#define SCT_EVCTRL13_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL13_IOSEL_Pos)                        /*!< SCT EVCTRL13: IOSEL Mask            */
+#define SCT_EVCTRL13_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL13: IOCOND Position       */
+#define SCT_EVCTRL13_IOCOND_Msk                               (0x03UL << SCT_EVCTRL13_IOCOND_Pos)                       /*!< SCT EVCTRL13: IOCOND Mask           */
+#define SCT_EVCTRL13_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL13: COMBMODE Position     */
+#define SCT_EVCTRL13_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL13_COMBMODE_Pos)                     /*!< SCT EVCTRL13: COMBMODE Mask         */
+#define SCT_EVCTRL13_STATELD_Pos                              14                                                        /*!< SCT EVCTRL13: STATELD Position      */
+#define SCT_EVCTRL13_STATELD_Msk                              (0x01UL << SCT_EVCTRL13_STATELD_Pos)                      /*!< SCT EVCTRL13: STATELD Mask          */
+#define SCT_EVCTRL13_STATEV_Pos                               15                                                        /*!< SCT EVCTRL13: STATEV Position       */
+#define SCT_EVCTRL13_STATEV_Msk                               (0x1fUL << SCT_EVCTRL13_STATEV_Pos)                       /*!< SCT EVCTRL13: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK14  ----------------------------------------
+#define SCT_EVSTATEMSK14_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL14  ------------------------------------------
+#define SCT_EVCTRL14_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL14: MATCHSEL Position     */
+#define SCT_EVCTRL14_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos)                     /*!< SCT EVCTRL14: MATCHSEL Mask         */
+#define SCT_EVCTRL14_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL14: HEVENT Position       */
+#define SCT_EVCTRL14_HEVENT_Msk                               (0x01UL << SCT_EVCTRL14_HEVENT_Pos)                       /*!< SCT EVCTRL14: HEVENT Mask           */
+#define SCT_EVCTRL14_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL14: OUTSEL Position       */
+#define SCT_EVCTRL14_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL14_OUTSEL_Pos)                       /*!< SCT EVCTRL14: OUTSEL Mask           */
+#define SCT_EVCTRL14_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL14: IOSEL Position        */
+#define SCT_EVCTRL14_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL14_IOSEL_Pos)                        /*!< SCT EVCTRL14: IOSEL Mask            */
+#define SCT_EVCTRL14_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL14: IOCOND Position       */
+#define SCT_EVCTRL14_IOCOND_Msk                               (0x03UL << SCT_EVCTRL14_IOCOND_Pos)                       /*!< SCT EVCTRL14: IOCOND Mask           */
+#define SCT_EVCTRL14_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL14: COMBMODE Position     */
+#define SCT_EVCTRL14_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL14_COMBMODE_Pos)                     /*!< SCT EVCTRL14: COMBMODE Mask         */
+#define SCT_EVCTRL14_STATELD_Pos                              14                                                        /*!< SCT EVCTRL14: STATELD Position      */
+#define SCT_EVCTRL14_STATELD_Msk                              (0x01UL << SCT_EVCTRL14_STATELD_Pos)                      /*!< SCT EVCTRL14: STATELD Mask          */
+#define SCT_EVCTRL14_STATEV_Pos                               15                                                        /*!< SCT EVCTRL14: STATEV Position       */
+#define SCT_EVCTRL14_STATEV_Msk                               (0x1fUL << SCT_EVCTRL14_STATEV_Pos)                       /*!< SCT EVCTRL14: STATEV Mask           */
+
+// ------------------------------------  SCT_EVSTATEMSK15  ----------------------------------------
+#define SCT_EVSTATEMSK15_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask   */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask  */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask  */
+
+// --------------------------------------  SCT_EVCTRL15  ------------------------------------------
+#define SCT_EVCTRL15_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL15: MATCHSEL Position     */
+#define SCT_EVCTRL15_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos)                     /*!< SCT EVCTRL15: MATCHSEL Mask         */
+#define SCT_EVCTRL15_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL15: HEVENT Position       */
+#define SCT_EVCTRL15_HEVENT_Msk                               (0x01UL << SCT_EVCTRL15_HEVENT_Pos)                       /*!< SCT EVCTRL15: HEVENT Mask           */
+#define SCT_EVCTRL15_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL15: OUTSEL Position       */
+#define SCT_EVCTRL15_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL15_OUTSEL_Pos)                       /*!< SCT EVCTRL15: OUTSEL Mask           */
+#define SCT_EVCTRL15_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL15: IOSEL Position        */
+#define SCT_EVCTRL15_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL15_IOSEL_Pos)                        /*!< SCT EVCTRL15: IOSEL Mask            */
+#define SCT_EVCTRL15_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL15: IOCOND Position       */
+#define SCT_EVCTRL15_IOCOND_Msk                               (0x03UL << SCT_EVCTRL15_IOCOND_Pos)                       /*!< SCT EVCTRL15: IOCOND Mask           */
+#define SCT_EVCTRL15_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL15: COMBMODE Position     */
+#define SCT_EVCTRL15_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL15_COMBMODE_Pos)                     /*!< SCT EVCTRL15: COMBMODE Mask         */
+#define SCT_EVCTRL15_STATELD_Pos                              14                                                        /*!< SCT EVCTRL15: STATELD Position      */
+#define SCT_EVCTRL15_STATELD_Msk                              (0x01UL << SCT_EVCTRL15_STATELD_Pos)                      /*!< SCT EVCTRL15: STATELD Mask          */
+#define SCT_EVCTRL15_STATEV_Pos                               15                                                        /*!< SCT EVCTRL15: STATEV Position       */
+#define SCT_EVCTRL15_STATEV_Msk                               (0x1fUL << SCT_EVCTRL15_STATEV_Pos)                       /*!< SCT EVCTRL15: STATEV Mask           */
+
+// -------------------------------------  SCT_OUTPUTSET0  -----------------------------------------
+#define SCT_OUTPUTSET0_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET0: SETn0 Position      */
+#define SCT_OUTPUTSET0_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn0_Pos)                      /*!< SCT OUTPUTSET0: SETn0 Mask          */
+#define SCT_OUTPUTSET0_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET0: SETn1 Position      */
+#define SCT_OUTPUTSET0_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn1_Pos)                      /*!< SCT OUTPUTSET0: SETn1 Mask          */
+#define SCT_OUTPUTSET0_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET0: SETn2 Position      */
+#define SCT_OUTPUTSET0_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn2_Pos)                      /*!< SCT OUTPUTSET0: SETn2 Mask          */
+#define SCT_OUTPUTSET0_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET0: SETn3 Position      */
+#define SCT_OUTPUTSET0_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn3_Pos)                      /*!< SCT OUTPUTSET0: SETn3 Mask          */
+#define SCT_OUTPUTSET0_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET0: SETn4 Position      */
+#define SCT_OUTPUTSET0_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn4_Pos)                      /*!< SCT OUTPUTSET0: SETn4 Mask          */
+#define SCT_OUTPUTSET0_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET0: SETn5 Position      */
+#define SCT_OUTPUTSET0_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn5_Pos)                      /*!< SCT OUTPUTSET0: SETn5 Mask          */
+#define SCT_OUTPUTSET0_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET0: SETn6 Position      */
+#define SCT_OUTPUTSET0_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn6_Pos)                      /*!< SCT OUTPUTSET0: SETn6 Mask          */
+#define SCT_OUTPUTSET0_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET0: SETn7 Position      */
+#define SCT_OUTPUTSET0_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn7_Pos)                      /*!< SCT OUTPUTSET0: SETn7 Mask          */
+#define SCT_OUTPUTSET0_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET0: SETn8 Position      */
+#define SCT_OUTPUTSET0_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn8_Pos)                      /*!< SCT OUTPUTSET0: SETn8 Mask          */
+#define SCT_OUTPUTSET0_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET0: SETn9 Position      */
+#define SCT_OUTPUTSET0_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn9_Pos)                      /*!< SCT OUTPUTSET0: SETn9 Mask          */
+#define SCT_OUTPUTSET0_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET0: SETn10 Position     */
+#define SCT_OUTPUTSET0_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn10_Pos)                     /*!< SCT OUTPUTSET0: SETn10 Mask         */
+#define SCT_OUTPUTSET0_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET0: SETn11 Position     */
+#define SCT_OUTPUTSET0_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn11_Pos)                     /*!< SCT OUTPUTSET0: SETn11 Mask         */
+#define SCT_OUTPUTSET0_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET0: SETn12 Position     */
+#define SCT_OUTPUTSET0_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn12_Pos)                     /*!< SCT OUTPUTSET0: SETn12 Mask         */
+#define SCT_OUTPUTSET0_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET0: SETn13 Position     */
+#define SCT_OUTPUTSET0_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn13_Pos)                     /*!< SCT OUTPUTSET0: SETn13 Mask         */
+#define SCT_OUTPUTSET0_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET0: SETn14 Position     */
+#define SCT_OUTPUTSET0_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn14_Pos)                     /*!< SCT OUTPUTSET0: SETn14 Mask         */
+#define SCT_OUTPUTSET0_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET0: SETn15 Position     */
+#define SCT_OUTPUTSET0_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn15_Pos)                     /*!< SCT OUTPUTSET0: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR0  -----------------------------------------
+#define SCT_OUTPUTCLR0_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR0: CLRn0 Position      */
+#define SCT_OUTPUTCLR0_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos)                      /*!< SCT OUTPUTCLR0: CLRn0 Mask          */
+#define SCT_OUTPUTCLR0_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR0: CLRn1 Position      */
+#define SCT_OUTPUTCLR0_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos)                      /*!< SCT OUTPUTCLR0: CLRn1 Mask          */
+#define SCT_OUTPUTCLR0_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR0: CLRn2 Position      */
+#define SCT_OUTPUTCLR0_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos)                      /*!< SCT OUTPUTCLR0: CLRn2 Mask          */
+#define SCT_OUTPUTCLR0_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR0: CLRn3 Position      */
+#define SCT_OUTPUTCLR0_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos)                      /*!< SCT OUTPUTCLR0: CLRn3 Mask          */
+#define SCT_OUTPUTCLR0_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR0: CLRn4 Position      */
+#define SCT_OUTPUTCLR0_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos)                      /*!< SCT OUTPUTCLR0: CLRn4 Mask          */
+#define SCT_OUTPUTCLR0_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR0: CLRn5 Position      */
+#define SCT_OUTPUTCLR0_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos)                      /*!< SCT OUTPUTCLR0: CLRn5 Mask          */
+#define SCT_OUTPUTCLR0_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR0: CLRn6 Position      */
+#define SCT_OUTPUTCLR0_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos)                      /*!< SCT OUTPUTCLR0: CLRn6 Mask          */
+#define SCT_OUTPUTCLR0_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR0: CLRn7 Position      */
+#define SCT_OUTPUTCLR0_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos)                      /*!< SCT OUTPUTCLR0: CLRn7 Mask          */
+#define SCT_OUTPUTCLR0_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR0: CLRn8 Position      */
+#define SCT_OUTPUTCLR0_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos)                      /*!< SCT OUTPUTCLR0: CLRn8 Mask          */
+#define SCT_OUTPUTCLR0_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR0: CLRn9 Position      */
+#define SCT_OUTPUTCLR0_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos)                      /*!< SCT OUTPUTCLR0: CLRn9 Mask          */
+#define SCT_OUTPUTCLR0_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR0: CLRn10 Position     */
+#define SCT_OUTPUTCLR0_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos)                     /*!< SCT OUTPUTCLR0: CLRn10 Mask         */
+#define SCT_OUTPUTCLR0_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR0: CLRn11 Position     */
+#define SCT_OUTPUTCLR0_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos)                     /*!< SCT OUTPUTCLR0: CLRn11 Mask         */
+#define SCT_OUTPUTCLR0_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR0: CLRn12 Position     */
+#define SCT_OUTPUTCLR0_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos)                     /*!< SCT OUTPUTCLR0: CLRn12 Mask         */
+#define SCT_OUTPUTCLR0_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR0: CLRn13 Position     */
+#define SCT_OUTPUTCLR0_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos)                     /*!< SCT OUTPUTCLR0: CLRn13 Mask         */
+#define SCT_OUTPUTCLR0_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR0: CLRn14 Position     */
+#define SCT_OUTPUTCLR0_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos)                     /*!< SCT OUTPUTCLR0: CLRn14 Mask         */
+#define SCT_OUTPUTCLR0_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR0: CLRn15 Position     */
+#define SCT_OUTPUTCLR0_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos)                     /*!< SCT OUTPUTCLR0: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET1  -----------------------------------------
+#define SCT_OUTPUTSET1_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET1: SETn0 Position      */
+#define SCT_OUTPUTSET1_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn0_Pos)                      /*!< SCT OUTPUTSET1: SETn0 Mask          */
+#define SCT_OUTPUTSET1_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET1: SETn1 Position      */
+#define SCT_OUTPUTSET1_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn1_Pos)                      /*!< SCT OUTPUTSET1: SETn1 Mask          */
+#define SCT_OUTPUTSET1_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET1: SETn2 Position      */
+#define SCT_OUTPUTSET1_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn2_Pos)                      /*!< SCT OUTPUTSET1: SETn2 Mask          */
+#define SCT_OUTPUTSET1_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET1: SETn3 Position      */
+#define SCT_OUTPUTSET1_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn3_Pos)                      /*!< SCT OUTPUTSET1: SETn3 Mask          */
+#define SCT_OUTPUTSET1_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET1: SETn4 Position      */
+#define SCT_OUTPUTSET1_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn4_Pos)                      /*!< SCT OUTPUTSET1: SETn4 Mask          */
+#define SCT_OUTPUTSET1_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET1: SETn5 Position      */
+#define SCT_OUTPUTSET1_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn5_Pos)                      /*!< SCT OUTPUTSET1: SETn5 Mask          */
+#define SCT_OUTPUTSET1_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET1: SETn6 Position      */
+#define SCT_OUTPUTSET1_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn6_Pos)                      /*!< SCT OUTPUTSET1: SETn6 Mask          */
+#define SCT_OUTPUTSET1_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET1: SETn7 Position      */
+#define SCT_OUTPUTSET1_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn7_Pos)                      /*!< SCT OUTPUTSET1: SETn7 Mask          */
+#define SCT_OUTPUTSET1_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET1: SETn8 Position      */
+#define SCT_OUTPUTSET1_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn8_Pos)                      /*!< SCT OUTPUTSET1: SETn8 Mask          */
+#define SCT_OUTPUTSET1_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET1: SETn9 Position      */
+#define SCT_OUTPUTSET1_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn9_Pos)                      /*!< SCT OUTPUTSET1: SETn9 Mask          */
+#define SCT_OUTPUTSET1_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET1: SETn10 Position     */
+#define SCT_OUTPUTSET1_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn10_Pos)                     /*!< SCT OUTPUTSET1: SETn10 Mask         */
+#define SCT_OUTPUTSET1_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET1: SETn11 Position     */
+#define SCT_OUTPUTSET1_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn11_Pos)                     /*!< SCT OUTPUTSET1: SETn11 Mask         */
+#define SCT_OUTPUTSET1_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET1: SETn12 Position     */
+#define SCT_OUTPUTSET1_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn12_Pos)                     /*!< SCT OUTPUTSET1: SETn12 Mask         */
+#define SCT_OUTPUTSET1_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET1: SETn13 Position     */
+#define SCT_OUTPUTSET1_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn13_Pos)                     /*!< SCT OUTPUTSET1: SETn13 Mask         */
+#define SCT_OUTPUTSET1_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET1: SETn14 Position     */
+#define SCT_OUTPUTSET1_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn14_Pos)                     /*!< SCT OUTPUTSET1: SETn14 Mask         */
+#define SCT_OUTPUTSET1_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET1: SETn15 Position     */
+#define SCT_OUTPUTSET1_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn15_Pos)                     /*!< SCT OUTPUTSET1: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR1  -----------------------------------------
+#define SCT_OUTPUTCLR1_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR1: CLRn0 Position      */
+#define SCT_OUTPUTCLR1_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos)                      /*!< SCT OUTPUTCLR1: CLRn0 Mask          */
+#define SCT_OUTPUTCLR1_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR1: CLRn1 Position      */
+#define SCT_OUTPUTCLR1_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos)                      /*!< SCT OUTPUTCLR1: CLRn1 Mask          */
+#define SCT_OUTPUTCLR1_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR1: CLRn2 Position      */
+#define SCT_OUTPUTCLR1_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos)                      /*!< SCT OUTPUTCLR1: CLRn2 Mask          */
+#define SCT_OUTPUTCLR1_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR1: CLRn3 Position      */
+#define SCT_OUTPUTCLR1_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos)                      /*!< SCT OUTPUTCLR1: CLRn3 Mask          */
+#define SCT_OUTPUTCLR1_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR1: CLRn4 Position      */
+#define SCT_OUTPUTCLR1_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos)                      /*!< SCT OUTPUTCLR1: CLRn4 Mask          */
+#define SCT_OUTPUTCLR1_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR1: CLRn5 Position      */
+#define SCT_OUTPUTCLR1_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos)                      /*!< SCT OUTPUTCLR1: CLRn5 Mask          */
+#define SCT_OUTPUTCLR1_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR1: CLRn6 Position      */
+#define SCT_OUTPUTCLR1_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos)                      /*!< SCT OUTPUTCLR1: CLRn6 Mask          */
+#define SCT_OUTPUTCLR1_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR1: CLRn7 Position      */
+#define SCT_OUTPUTCLR1_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos)                      /*!< SCT OUTPUTCLR1: CLRn7 Mask          */
+#define SCT_OUTPUTCLR1_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR1: CLRn8 Position      */
+#define SCT_OUTPUTCLR1_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos)                      /*!< SCT OUTPUTCLR1: CLRn8 Mask          */
+#define SCT_OUTPUTCLR1_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR1: CLRn9 Position      */
+#define SCT_OUTPUTCLR1_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos)                      /*!< SCT OUTPUTCLR1: CLRn9 Mask          */
+#define SCT_OUTPUTCLR1_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR1: CLRn10 Position     */
+#define SCT_OUTPUTCLR1_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos)                     /*!< SCT OUTPUTCLR1: CLRn10 Mask         */
+#define SCT_OUTPUTCLR1_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR1: CLRn11 Position     */
+#define SCT_OUTPUTCLR1_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos)                     /*!< SCT OUTPUTCLR1: CLRn11 Mask         */
+#define SCT_OUTPUTCLR1_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR1: CLRn12 Position     */
+#define SCT_OUTPUTCLR1_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos)                     /*!< SCT OUTPUTCLR1: CLRn12 Mask         */
+#define SCT_OUTPUTCLR1_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR1: CLRn13 Position     */
+#define SCT_OUTPUTCLR1_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos)                     /*!< SCT OUTPUTCLR1: CLRn13 Mask         */
+#define SCT_OUTPUTCLR1_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR1: CLRn14 Position     */
+#define SCT_OUTPUTCLR1_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos)                     /*!< SCT OUTPUTCLR1: CLRn14 Mask         */
+#define SCT_OUTPUTCLR1_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR1: CLRn15 Position     */
+#define SCT_OUTPUTCLR1_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos)                     /*!< SCT OUTPUTCLR1: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET2  -----------------------------------------
+#define SCT_OUTPUTSET2_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET2: SETn0 Position      */
+#define SCT_OUTPUTSET2_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn0_Pos)                      /*!< SCT OUTPUTSET2: SETn0 Mask          */
+#define SCT_OUTPUTSET2_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET2: SETn1 Position      */
+#define SCT_OUTPUTSET2_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn1_Pos)                      /*!< SCT OUTPUTSET2: SETn1 Mask          */
+#define SCT_OUTPUTSET2_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET2: SETn2 Position      */
+#define SCT_OUTPUTSET2_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn2_Pos)                      /*!< SCT OUTPUTSET2: SETn2 Mask          */
+#define SCT_OUTPUTSET2_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET2: SETn3 Position      */
+#define SCT_OUTPUTSET2_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn3_Pos)                      /*!< SCT OUTPUTSET2: SETn3 Mask          */
+#define SCT_OUTPUTSET2_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET2: SETn4 Position      */
+#define SCT_OUTPUTSET2_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn4_Pos)                      /*!< SCT OUTPUTSET2: SETn4 Mask          */
+#define SCT_OUTPUTSET2_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET2: SETn5 Position      */
+#define SCT_OUTPUTSET2_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn5_Pos)                      /*!< SCT OUTPUTSET2: SETn5 Mask          */
+#define SCT_OUTPUTSET2_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET2: SETn6 Position      */
+#define SCT_OUTPUTSET2_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn6_Pos)                      /*!< SCT OUTPUTSET2: SETn6 Mask          */
+#define SCT_OUTPUTSET2_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET2: SETn7 Position      */
+#define SCT_OUTPUTSET2_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn7_Pos)                      /*!< SCT OUTPUTSET2: SETn7 Mask          */
+#define SCT_OUTPUTSET2_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET2: SETn8 Position      */
+#define SCT_OUTPUTSET2_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn8_Pos)                      /*!< SCT OUTPUTSET2: SETn8 Mask          */
+#define SCT_OUTPUTSET2_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET2: SETn9 Position      */
+#define SCT_OUTPUTSET2_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn9_Pos)                      /*!< SCT OUTPUTSET2: SETn9 Mask          */
+#define SCT_OUTPUTSET2_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET2: SETn10 Position     */
+#define SCT_OUTPUTSET2_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn10_Pos)                     /*!< SCT OUTPUTSET2: SETn10 Mask         */
+#define SCT_OUTPUTSET2_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET2: SETn11 Position     */
+#define SCT_OUTPUTSET2_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn11_Pos)                     /*!< SCT OUTPUTSET2: SETn11 Mask         */
+#define SCT_OUTPUTSET2_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET2: SETn12 Position     */
+#define SCT_OUTPUTSET2_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn12_Pos)                     /*!< SCT OUTPUTSET2: SETn12 Mask         */
+#define SCT_OUTPUTSET2_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET2: SETn13 Position     */
+#define SCT_OUTPUTSET2_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn13_Pos)                     /*!< SCT OUTPUTSET2: SETn13 Mask         */
+#define SCT_OUTPUTSET2_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET2: SETn14 Position     */
+#define SCT_OUTPUTSET2_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn14_Pos)                     /*!< SCT OUTPUTSET2: SETn14 Mask         */
+#define SCT_OUTPUTSET2_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET2: SETn15 Position     */
+#define SCT_OUTPUTSET2_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn15_Pos)                     /*!< SCT OUTPUTSET2: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR2  -----------------------------------------
+#define SCT_OUTPUTCLR2_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR2: CLRn0 Position      */
+#define SCT_OUTPUTCLR2_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos)                      /*!< SCT OUTPUTCLR2: CLRn0 Mask          */
+#define SCT_OUTPUTCLR2_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR2: CLRn1 Position      */
+#define SCT_OUTPUTCLR2_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos)                      /*!< SCT OUTPUTCLR2: CLRn1 Mask          */
+#define SCT_OUTPUTCLR2_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR2: CLRn2 Position      */
+#define SCT_OUTPUTCLR2_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos)                      /*!< SCT OUTPUTCLR2: CLRn2 Mask          */
+#define SCT_OUTPUTCLR2_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR2: CLRn3 Position      */
+#define SCT_OUTPUTCLR2_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos)                      /*!< SCT OUTPUTCLR2: CLRn3 Mask          */
+#define SCT_OUTPUTCLR2_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR2: CLRn4 Position      */
+#define SCT_OUTPUTCLR2_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos)                      /*!< SCT OUTPUTCLR2: CLRn4 Mask          */
+#define SCT_OUTPUTCLR2_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR2: CLRn5 Position      */
+#define SCT_OUTPUTCLR2_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos)                      /*!< SCT OUTPUTCLR2: CLRn5 Mask          */
+#define SCT_OUTPUTCLR2_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR2: CLRn6 Position      */
+#define SCT_OUTPUTCLR2_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos)                      /*!< SCT OUTPUTCLR2: CLRn6 Mask          */
+#define SCT_OUTPUTCLR2_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR2: CLRn7 Position      */
+#define SCT_OUTPUTCLR2_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos)                      /*!< SCT OUTPUTCLR2: CLRn7 Mask          */
+#define SCT_OUTPUTCLR2_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR2: CLRn8 Position      */
+#define SCT_OUTPUTCLR2_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos)                      /*!< SCT OUTPUTCLR2: CLRn8 Mask          */
+#define SCT_OUTPUTCLR2_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR2: CLRn9 Position      */
+#define SCT_OUTPUTCLR2_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos)                      /*!< SCT OUTPUTCLR2: CLRn9 Mask          */
+#define SCT_OUTPUTCLR2_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR2: CLRn10 Position     */
+#define SCT_OUTPUTCLR2_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos)                     /*!< SCT OUTPUTCLR2: CLRn10 Mask         */
+#define SCT_OUTPUTCLR2_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR2: CLRn11 Position     */
+#define SCT_OUTPUTCLR2_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos)                     /*!< SCT OUTPUTCLR2: CLRn11 Mask         */
+#define SCT_OUTPUTCLR2_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR2: CLRn12 Position     */
+#define SCT_OUTPUTCLR2_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos)                     /*!< SCT OUTPUTCLR2: CLRn12 Mask         */
+#define SCT_OUTPUTCLR2_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR2: CLRn13 Position     */
+#define SCT_OUTPUTCLR2_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos)                     /*!< SCT OUTPUTCLR2: CLRn13 Mask         */
+#define SCT_OUTPUTCLR2_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR2: CLRn14 Position     */
+#define SCT_OUTPUTCLR2_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos)                     /*!< SCT OUTPUTCLR2: CLRn14 Mask         */
+#define SCT_OUTPUTCLR2_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR2: CLRn15 Position     */
+#define SCT_OUTPUTCLR2_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos)                     /*!< SCT OUTPUTCLR2: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET3  -----------------------------------------
+#define SCT_OUTPUTSET3_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET3: SETn0 Position      */
+#define SCT_OUTPUTSET3_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn0_Pos)                      /*!< SCT OUTPUTSET3: SETn0 Mask          */
+#define SCT_OUTPUTSET3_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET3: SETn1 Position      */
+#define SCT_OUTPUTSET3_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn1_Pos)                      /*!< SCT OUTPUTSET3: SETn1 Mask          */
+#define SCT_OUTPUTSET3_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET3: SETn2 Position      */
+#define SCT_OUTPUTSET3_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn2_Pos)                      /*!< SCT OUTPUTSET3: SETn2 Mask          */
+#define SCT_OUTPUTSET3_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET3: SETn3 Position      */
+#define SCT_OUTPUTSET3_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn3_Pos)                      /*!< SCT OUTPUTSET3: SETn3 Mask          */
+#define SCT_OUTPUTSET3_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET3: SETn4 Position      */
+#define SCT_OUTPUTSET3_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn4_Pos)                      /*!< SCT OUTPUTSET3: SETn4 Mask          */
+#define SCT_OUTPUTSET3_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET3: SETn5 Position      */
+#define SCT_OUTPUTSET3_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn5_Pos)                      /*!< SCT OUTPUTSET3: SETn5 Mask          */
+#define SCT_OUTPUTSET3_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET3: SETn6 Position      */
+#define SCT_OUTPUTSET3_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn6_Pos)                      /*!< SCT OUTPUTSET3: SETn6 Mask          */
+#define SCT_OUTPUTSET3_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET3: SETn7 Position      */
+#define SCT_OUTPUTSET3_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn7_Pos)                      /*!< SCT OUTPUTSET3: SETn7 Mask          */
+#define SCT_OUTPUTSET3_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET3: SETn8 Position      */
+#define SCT_OUTPUTSET3_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn8_Pos)                      /*!< SCT OUTPUTSET3: SETn8 Mask          */
+#define SCT_OUTPUTSET3_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET3: SETn9 Position      */
+#define SCT_OUTPUTSET3_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn9_Pos)                      /*!< SCT OUTPUTSET3: SETn9 Mask          */
+#define SCT_OUTPUTSET3_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET3: SETn10 Position     */
+#define SCT_OUTPUTSET3_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn10_Pos)                     /*!< SCT OUTPUTSET3: SETn10 Mask         */
+#define SCT_OUTPUTSET3_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET3: SETn11 Position     */
+#define SCT_OUTPUTSET3_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn11_Pos)                     /*!< SCT OUTPUTSET3: SETn11 Mask         */
+#define SCT_OUTPUTSET3_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET3: SETn12 Position     */
+#define SCT_OUTPUTSET3_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn12_Pos)                     /*!< SCT OUTPUTSET3: SETn12 Mask         */
+#define SCT_OUTPUTSET3_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET3: SETn13 Position     */
+#define SCT_OUTPUTSET3_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn13_Pos)                     /*!< SCT OUTPUTSET3: SETn13 Mask         */
+#define SCT_OUTPUTSET3_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET3: SETn14 Position     */
+#define SCT_OUTPUTSET3_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn14_Pos)                     /*!< SCT OUTPUTSET3: SETn14 Mask         */
+#define SCT_OUTPUTSET3_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET3: SETn15 Position     */
+#define SCT_OUTPUTSET3_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn15_Pos)                     /*!< SCT OUTPUTSET3: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR3  -----------------------------------------
+#define SCT_OUTPUTCLR3_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR3: CLRn0 Position      */
+#define SCT_OUTPUTCLR3_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos)                      /*!< SCT OUTPUTCLR3: CLRn0 Mask          */
+#define SCT_OUTPUTCLR3_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR3: CLRn1 Position      */
+#define SCT_OUTPUTCLR3_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos)                      /*!< SCT OUTPUTCLR3: CLRn1 Mask          */
+#define SCT_OUTPUTCLR3_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR3: CLRn2 Position      */
+#define SCT_OUTPUTCLR3_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos)                      /*!< SCT OUTPUTCLR3: CLRn2 Mask          */
+#define SCT_OUTPUTCLR3_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR3: CLRn3 Position      */
+#define SCT_OUTPUTCLR3_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos)                      /*!< SCT OUTPUTCLR3: CLRn3 Mask          */
+#define SCT_OUTPUTCLR3_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR3: CLRn4 Position      */
+#define SCT_OUTPUTCLR3_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos)                      /*!< SCT OUTPUTCLR3: CLRn4 Mask          */
+#define SCT_OUTPUTCLR3_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR3: CLRn5 Position      */
+#define SCT_OUTPUTCLR3_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos)                      /*!< SCT OUTPUTCLR3: CLRn5 Mask          */
+#define SCT_OUTPUTCLR3_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR3: CLRn6 Position      */
+#define SCT_OUTPUTCLR3_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos)                      /*!< SCT OUTPUTCLR3: CLRn6 Mask          */
+#define SCT_OUTPUTCLR3_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR3: CLRn7 Position      */
+#define SCT_OUTPUTCLR3_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos)                      /*!< SCT OUTPUTCLR3: CLRn7 Mask          */
+#define SCT_OUTPUTCLR3_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR3: CLRn8 Position      */
+#define SCT_OUTPUTCLR3_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos)                      /*!< SCT OUTPUTCLR3: CLRn8 Mask          */
+#define SCT_OUTPUTCLR3_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR3: CLRn9 Position      */
+#define SCT_OUTPUTCLR3_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos)                      /*!< SCT OUTPUTCLR3: CLRn9 Mask          */
+#define SCT_OUTPUTCLR3_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR3: CLRn10 Position     */
+#define SCT_OUTPUTCLR3_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos)                     /*!< SCT OUTPUTCLR3: CLRn10 Mask         */
+#define SCT_OUTPUTCLR3_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR3: CLRn11 Position     */
+#define SCT_OUTPUTCLR3_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos)                     /*!< SCT OUTPUTCLR3: CLRn11 Mask         */
+#define SCT_OUTPUTCLR3_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR3: CLRn12 Position     */
+#define SCT_OUTPUTCLR3_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos)                     /*!< SCT OUTPUTCLR3: CLRn12 Mask         */
+#define SCT_OUTPUTCLR3_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR3: CLRn13 Position     */
+#define SCT_OUTPUTCLR3_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos)                     /*!< SCT OUTPUTCLR3: CLRn13 Mask         */
+#define SCT_OUTPUTCLR3_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR3: CLRn14 Position     */
+#define SCT_OUTPUTCLR3_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos)                     /*!< SCT OUTPUTCLR3: CLRn14 Mask         */
+#define SCT_OUTPUTCLR3_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR3: CLRn15 Position     */
+#define SCT_OUTPUTCLR3_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos)                     /*!< SCT OUTPUTCLR3: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET4  -----------------------------------------
+#define SCT_OUTPUTSET4_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET4: SETn0 Position      */
+#define SCT_OUTPUTSET4_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn0_Pos)                      /*!< SCT OUTPUTSET4: SETn0 Mask          */
+#define SCT_OUTPUTSET4_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET4: SETn1 Position      */
+#define SCT_OUTPUTSET4_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn1_Pos)                      /*!< SCT OUTPUTSET4: SETn1 Mask          */
+#define SCT_OUTPUTSET4_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET4: SETn2 Position      */
+#define SCT_OUTPUTSET4_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn2_Pos)                      /*!< SCT OUTPUTSET4: SETn2 Mask          */
+#define SCT_OUTPUTSET4_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET4: SETn3 Position      */
+#define SCT_OUTPUTSET4_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn3_Pos)                      /*!< SCT OUTPUTSET4: SETn3 Mask          */
+#define SCT_OUTPUTSET4_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET4: SETn4 Position      */
+#define SCT_OUTPUTSET4_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn4_Pos)                      /*!< SCT OUTPUTSET4: SETn4 Mask          */
+#define SCT_OUTPUTSET4_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET4: SETn5 Position      */
+#define SCT_OUTPUTSET4_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn5_Pos)                      /*!< SCT OUTPUTSET4: SETn5 Mask          */
+#define SCT_OUTPUTSET4_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET4: SETn6 Position      */
+#define SCT_OUTPUTSET4_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn6_Pos)                      /*!< SCT OUTPUTSET4: SETn6 Mask          */
+#define SCT_OUTPUTSET4_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET4: SETn7 Position      */
+#define SCT_OUTPUTSET4_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn7_Pos)                      /*!< SCT OUTPUTSET4: SETn7 Mask          */
+#define SCT_OUTPUTSET4_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET4: SETn8 Position      */
+#define SCT_OUTPUTSET4_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn8_Pos)                      /*!< SCT OUTPUTSET4: SETn8 Mask          */
+#define SCT_OUTPUTSET4_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET4: SETn9 Position      */
+#define SCT_OUTPUTSET4_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn9_Pos)                      /*!< SCT OUTPUTSET4: SETn9 Mask          */
+#define SCT_OUTPUTSET4_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET4: SETn10 Position     */
+#define SCT_OUTPUTSET4_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn10_Pos)                     /*!< SCT OUTPUTSET4: SETn10 Mask         */
+#define SCT_OUTPUTSET4_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET4: SETn11 Position     */
+#define SCT_OUTPUTSET4_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn11_Pos)                     /*!< SCT OUTPUTSET4: SETn11 Mask         */
+#define SCT_OUTPUTSET4_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET4: SETn12 Position     */
+#define SCT_OUTPUTSET4_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn12_Pos)                     /*!< SCT OUTPUTSET4: SETn12 Mask         */
+#define SCT_OUTPUTSET4_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET4: SETn13 Position     */
+#define SCT_OUTPUTSET4_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn13_Pos)                     /*!< SCT OUTPUTSET4: SETn13 Mask         */
+#define SCT_OUTPUTSET4_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET4: SETn14 Position     */
+#define SCT_OUTPUTSET4_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn14_Pos)                     /*!< SCT OUTPUTSET4: SETn14 Mask         */
+#define SCT_OUTPUTSET4_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET4: SETn15 Position     */
+#define SCT_OUTPUTSET4_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn15_Pos)                     /*!< SCT OUTPUTSET4: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR4  -----------------------------------------
+#define SCT_OUTPUTCLR4_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR4: CLRn0 Position      */
+#define SCT_OUTPUTCLR4_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos)                      /*!< SCT OUTPUTCLR4: CLRn0 Mask          */
+#define SCT_OUTPUTCLR4_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR4: CLRn1 Position      */
+#define SCT_OUTPUTCLR4_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos)                      /*!< SCT OUTPUTCLR4: CLRn1 Mask          */
+#define SCT_OUTPUTCLR4_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR4: CLRn2 Position      */
+#define SCT_OUTPUTCLR4_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos)                      /*!< SCT OUTPUTCLR4: CLRn2 Mask          */
+#define SCT_OUTPUTCLR4_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR4: CLRn3 Position      */
+#define SCT_OUTPUTCLR4_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos)                      /*!< SCT OUTPUTCLR4: CLRn3 Mask          */
+#define SCT_OUTPUTCLR4_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR4: CLRn4 Position      */
+#define SCT_OUTPUTCLR4_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos)                      /*!< SCT OUTPUTCLR4: CLRn4 Mask          */
+#define SCT_OUTPUTCLR4_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR4: CLRn5 Position      */
+#define SCT_OUTPUTCLR4_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos)                      /*!< SCT OUTPUTCLR4: CLRn5 Mask          */
+#define SCT_OUTPUTCLR4_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR4: CLRn6 Position      */
+#define SCT_OUTPUTCLR4_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos)                      /*!< SCT OUTPUTCLR4: CLRn6 Mask          */
+#define SCT_OUTPUTCLR4_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR4: CLRn7 Position      */
+#define SCT_OUTPUTCLR4_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos)                      /*!< SCT OUTPUTCLR4: CLRn7 Mask          */
+#define SCT_OUTPUTCLR4_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR4: CLRn8 Position      */
+#define SCT_OUTPUTCLR4_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos)                      /*!< SCT OUTPUTCLR4: CLRn8 Mask          */
+#define SCT_OUTPUTCLR4_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR4: CLRn9 Position      */
+#define SCT_OUTPUTCLR4_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos)                      /*!< SCT OUTPUTCLR4: CLRn9 Mask          */
+#define SCT_OUTPUTCLR4_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR4: CLRn10 Position     */
+#define SCT_OUTPUTCLR4_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos)                     /*!< SCT OUTPUTCLR4: CLRn10 Mask         */
+#define SCT_OUTPUTCLR4_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR4: CLRn11 Position     */
+#define SCT_OUTPUTCLR4_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos)                     /*!< SCT OUTPUTCLR4: CLRn11 Mask         */
+#define SCT_OUTPUTCLR4_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR4: CLRn12 Position     */
+#define SCT_OUTPUTCLR4_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos)                     /*!< SCT OUTPUTCLR4: CLRn12 Mask         */
+#define SCT_OUTPUTCLR4_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR4: CLRn13 Position     */
+#define SCT_OUTPUTCLR4_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos)                     /*!< SCT OUTPUTCLR4: CLRn13 Mask         */
+#define SCT_OUTPUTCLR4_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR4: CLRn14 Position     */
+#define SCT_OUTPUTCLR4_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos)                     /*!< SCT OUTPUTCLR4: CLRn14 Mask         */
+#define SCT_OUTPUTCLR4_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR4: CLRn15 Position     */
+#define SCT_OUTPUTCLR4_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos)                     /*!< SCT OUTPUTCLR4: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET5  -----------------------------------------
+#define SCT_OUTPUTSET5_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET5: SETn0 Position      */
+#define SCT_OUTPUTSET5_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn0_Pos)                      /*!< SCT OUTPUTSET5: SETn0 Mask          */
+#define SCT_OUTPUTSET5_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET5: SETn1 Position      */
+#define SCT_OUTPUTSET5_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn1_Pos)                      /*!< SCT OUTPUTSET5: SETn1 Mask          */
+#define SCT_OUTPUTSET5_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET5: SETn2 Position      */
+#define SCT_OUTPUTSET5_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn2_Pos)                      /*!< SCT OUTPUTSET5: SETn2 Mask          */
+#define SCT_OUTPUTSET5_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET5: SETn3 Position      */
+#define SCT_OUTPUTSET5_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn3_Pos)                      /*!< SCT OUTPUTSET5: SETn3 Mask          */
+#define SCT_OUTPUTSET5_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET5: SETn4 Position      */
+#define SCT_OUTPUTSET5_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn4_Pos)                      /*!< SCT OUTPUTSET5: SETn4 Mask          */
+#define SCT_OUTPUTSET5_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET5: SETn5 Position      */
+#define SCT_OUTPUTSET5_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn5_Pos)                      /*!< SCT OUTPUTSET5: SETn5 Mask          */
+#define SCT_OUTPUTSET5_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET5: SETn6 Position      */
+#define SCT_OUTPUTSET5_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn6_Pos)                      /*!< SCT OUTPUTSET5: SETn6 Mask          */
+#define SCT_OUTPUTSET5_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET5: SETn7 Position      */
+#define SCT_OUTPUTSET5_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn7_Pos)                      /*!< SCT OUTPUTSET5: SETn7 Mask          */
+#define SCT_OUTPUTSET5_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET5: SETn8 Position      */
+#define SCT_OUTPUTSET5_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn8_Pos)                      /*!< SCT OUTPUTSET5: SETn8 Mask          */
+#define SCT_OUTPUTSET5_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET5: SETn9 Position      */
+#define SCT_OUTPUTSET5_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn9_Pos)                      /*!< SCT OUTPUTSET5: SETn9 Mask          */
+#define SCT_OUTPUTSET5_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET5: SETn10 Position     */
+#define SCT_OUTPUTSET5_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn10_Pos)                     /*!< SCT OUTPUTSET5: SETn10 Mask         */
+#define SCT_OUTPUTSET5_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET5: SETn11 Position     */
+#define SCT_OUTPUTSET5_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn11_Pos)                     /*!< SCT OUTPUTSET5: SETn11 Mask         */
+#define SCT_OUTPUTSET5_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET5: SETn12 Position     */
+#define SCT_OUTPUTSET5_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn12_Pos)                     /*!< SCT OUTPUTSET5: SETn12 Mask         */
+#define SCT_OUTPUTSET5_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET5: SETn13 Position     */
+#define SCT_OUTPUTSET5_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn13_Pos)                     /*!< SCT OUTPUTSET5: SETn13 Mask         */
+#define SCT_OUTPUTSET5_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET5: SETn14 Position     */
+#define SCT_OUTPUTSET5_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn14_Pos)                     /*!< SCT OUTPUTSET5: SETn14 Mask         */
+#define SCT_OUTPUTSET5_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET5: SETn15 Position     */
+#define SCT_OUTPUTSET5_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn15_Pos)                     /*!< SCT OUTPUTSET5: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR5  -----------------------------------------
+#define SCT_OUTPUTCLR5_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR5: CLRn0 Position      */
+#define SCT_OUTPUTCLR5_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos)                      /*!< SCT OUTPUTCLR5: CLRn0 Mask          */
+#define SCT_OUTPUTCLR5_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR5: CLRn1 Position      */
+#define SCT_OUTPUTCLR5_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos)                      /*!< SCT OUTPUTCLR5: CLRn1 Mask          */
+#define SCT_OUTPUTCLR5_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR5: CLRn2 Position      */
+#define SCT_OUTPUTCLR5_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos)                      /*!< SCT OUTPUTCLR5: CLRn2 Mask          */
+#define SCT_OUTPUTCLR5_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR5: CLRn3 Position      */
+#define SCT_OUTPUTCLR5_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos)                      /*!< SCT OUTPUTCLR5: CLRn3 Mask          */
+#define SCT_OUTPUTCLR5_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR5: CLRn4 Position      */
+#define SCT_OUTPUTCLR5_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos)                      /*!< SCT OUTPUTCLR5: CLRn4 Mask          */
+#define SCT_OUTPUTCLR5_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR5: CLRn5 Position      */
+#define SCT_OUTPUTCLR5_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos)                      /*!< SCT OUTPUTCLR5: CLRn5 Mask          */
+#define SCT_OUTPUTCLR5_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR5: CLRn6 Position      */
+#define SCT_OUTPUTCLR5_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos)                      /*!< SCT OUTPUTCLR5: CLRn6 Mask          */
+#define SCT_OUTPUTCLR5_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR5: CLRn7 Position      */
+#define SCT_OUTPUTCLR5_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos)                      /*!< SCT OUTPUTCLR5: CLRn7 Mask          */
+#define SCT_OUTPUTCLR5_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR5: CLRn8 Position      */
+#define SCT_OUTPUTCLR5_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos)                      /*!< SCT OUTPUTCLR5: CLRn8 Mask          */
+#define SCT_OUTPUTCLR5_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR5: CLRn9 Position      */
+#define SCT_OUTPUTCLR5_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos)                      /*!< SCT OUTPUTCLR5: CLRn9 Mask          */
+#define SCT_OUTPUTCLR5_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR5: CLRn10 Position     */
+#define SCT_OUTPUTCLR5_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos)                     /*!< SCT OUTPUTCLR5: CLRn10 Mask         */
+#define SCT_OUTPUTCLR5_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR5: CLRn11 Position     */
+#define SCT_OUTPUTCLR5_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos)                     /*!< SCT OUTPUTCLR5: CLRn11 Mask         */
+#define SCT_OUTPUTCLR5_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR5: CLRn12 Position     */
+#define SCT_OUTPUTCLR5_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos)                     /*!< SCT OUTPUTCLR5: CLRn12 Mask         */
+#define SCT_OUTPUTCLR5_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR5: CLRn13 Position     */
+#define SCT_OUTPUTCLR5_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos)                     /*!< SCT OUTPUTCLR5: CLRn13 Mask         */
+#define SCT_OUTPUTCLR5_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR5: CLRn14 Position     */
+#define SCT_OUTPUTCLR5_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos)                     /*!< SCT OUTPUTCLR5: CLRn14 Mask         */
+#define SCT_OUTPUTCLR5_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR5: CLRn15 Position     */
+#define SCT_OUTPUTCLR5_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos)                     /*!< SCT OUTPUTCLR5: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET6  -----------------------------------------
+#define SCT_OUTPUTSET6_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET6: SETn0 Position      */
+#define SCT_OUTPUTSET6_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn0_Pos)                      /*!< SCT OUTPUTSET6: SETn0 Mask          */
+#define SCT_OUTPUTSET6_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET6: SETn1 Position      */
+#define SCT_OUTPUTSET6_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn1_Pos)                      /*!< SCT OUTPUTSET6: SETn1 Mask          */
+#define SCT_OUTPUTSET6_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET6: SETn2 Position      */
+#define SCT_OUTPUTSET6_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn2_Pos)                      /*!< SCT OUTPUTSET6: SETn2 Mask          */
+#define SCT_OUTPUTSET6_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET6: SETn3 Position      */
+#define SCT_OUTPUTSET6_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn3_Pos)                      /*!< SCT OUTPUTSET6: SETn3 Mask          */
+#define SCT_OUTPUTSET6_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET6: SETn4 Position      */
+#define SCT_OUTPUTSET6_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn4_Pos)                      /*!< SCT OUTPUTSET6: SETn4 Mask          */
+#define SCT_OUTPUTSET6_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET6: SETn5 Position      */
+#define SCT_OUTPUTSET6_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn5_Pos)                      /*!< SCT OUTPUTSET6: SETn5 Mask          */
+#define SCT_OUTPUTSET6_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET6: SETn6 Position      */
+#define SCT_OUTPUTSET6_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn6_Pos)                      /*!< SCT OUTPUTSET6: SETn6 Mask          */
+#define SCT_OUTPUTSET6_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET6: SETn7 Position      */
+#define SCT_OUTPUTSET6_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn7_Pos)                      /*!< SCT OUTPUTSET6: SETn7 Mask          */
+#define SCT_OUTPUTSET6_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET6: SETn8 Position      */
+#define SCT_OUTPUTSET6_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn8_Pos)                      /*!< SCT OUTPUTSET6: SETn8 Mask          */
+#define SCT_OUTPUTSET6_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET6: SETn9 Position      */
+#define SCT_OUTPUTSET6_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn9_Pos)                      /*!< SCT OUTPUTSET6: SETn9 Mask          */
+#define SCT_OUTPUTSET6_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET6: SETn10 Position     */
+#define SCT_OUTPUTSET6_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn10_Pos)                     /*!< SCT OUTPUTSET6: SETn10 Mask         */
+#define SCT_OUTPUTSET6_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET6: SETn11 Position     */
+#define SCT_OUTPUTSET6_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn11_Pos)                     /*!< SCT OUTPUTSET6: SETn11 Mask         */
+#define SCT_OUTPUTSET6_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET6: SETn12 Position     */
+#define SCT_OUTPUTSET6_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn12_Pos)                     /*!< SCT OUTPUTSET6: SETn12 Mask         */
+#define SCT_OUTPUTSET6_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET6: SETn13 Position     */
+#define SCT_OUTPUTSET6_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn13_Pos)                     /*!< SCT OUTPUTSET6: SETn13 Mask         */
+#define SCT_OUTPUTSET6_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET6: SETn14 Position     */
+#define SCT_OUTPUTSET6_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn14_Pos)                     /*!< SCT OUTPUTSET6: SETn14 Mask         */
+#define SCT_OUTPUTSET6_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET6: SETn15 Position     */
+#define SCT_OUTPUTSET6_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn15_Pos)                     /*!< SCT OUTPUTSET6: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR6  -----------------------------------------
+#define SCT_OUTPUTCLR6_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR6: CLRn0 Position      */
+#define SCT_OUTPUTCLR6_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos)                      /*!< SCT OUTPUTCLR6: CLRn0 Mask          */
+#define SCT_OUTPUTCLR6_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR6: CLRn1 Position      */
+#define SCT_OUTPUTCLR6_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos)                      /*!< SCT OUTPUTCLR6: CLRn1 Mask          */
+#define SCT_OUTPUTCLR6_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR6: CLRn2 Position      */
+#define SCT_OUTPUTCLR6_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos)                      /*!< SCT OUTPUTCLR6: CLRn2 Mask          */
+#define SCT_OUTPUTCLR6_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR6: CLRn3 Position      */
+#define SCT_OUTPUTCLR6_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos)                      /*!< SCT OUTPUTCLR6: CLRn3 Mask          */
+#define SCT_OUTPUTCLR6_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR6: CLRn4 Position      */
+#define SCT_OUTPUTCLR6_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos)                      /*!< SCT OUTPUTCLR6: CLRn4 Mask          */
+#define SCT_OUTPUTCLR6_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR6: CLRn5 Position      */
+#define SCT_OUTPUTCLR6_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos)                      /*!< SCT OUTPUTCLR6: CLRn5 Mask          */
+#define SCT_OUTPUTCLR6_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR6: CLRn6 Position      */
+#define SCT_OUTPUTCLR6_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos)                      /*!< SCT OUTPUTCLR6: CLRn6 Mask          */
+#define SCT_OUTPUTCLR6_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR6: CLRn7 Position      */
+#define SCT_OUTPUTCLR6_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos)                      /*!< SCT OUTPUTCLR6: CLRn7 Mask          */
+#define SCT_OUTPUTCLR6_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR6: CLRn8 Position      */
+#define SCT_OUTPUTCLR6_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos)                      /*!< SCT OUTPUTCLR6: CLRn8 Mask          */
+#define SCT_OUTPUTCLR6_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR6: CLRn9 Position      */
+#define SCT_OUTPUTCLR6_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos)                      /*!< SCT OUTPUTCLR6: CLRn9 Mask          */
+#define SCT_OUTPUTCLR6_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR6: CLRn10 Position     */
+#define SCT_OUTPUTCLR6_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos)                     /*!< SCT OUTPUTCLR6: CLRn10 Mask         */
+#define SCT_OUTPUTCLR6_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR6: CLRn11 Position     */
+#define SCT_OUTPUTCLR6_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos)                     /*!< SCT OUTPUTCLR6: CLRn11 Mask         */
+#define SCT_OUTPUTCLR6_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR6: CLRn12 Position     */
+#define SCT_OUTPUTCLR6_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos)                     /*!< SCT OUTPUTCLR6: CLRn12 Mask         */
+#define SCT_OUTPUTCLR6_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR6: CLRn13 Position     */
+#define SCT_OUTPUTCLR6_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos)                     /*!< SCT OUTPUTCLR6: CLRn13 Mask         */
+#define SCT_OUTPUTCLR6_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR6: CLRn14 Position     */
+#define SCT_OUTPUTCLR6_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos)                     /*!< SCT OUTPUTCLR6: CLRn14 Mask         */
+#define SCT_OUTPUTCLR6_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR6: CLRn15 Position     */
+#define SCT_OUTPUTCLR6_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos)                     /*!< SCT OUTPUTCLR6: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET7  -----------------------------------------
+#define SCT_OUTPUTSET7_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET7: SETn0 Position      */
+#define SCT_OUTPUTSET7_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn0_Pos)                      /*!< SCT OUTPUTSET7: SETn0 Mask          */
+#define SCT_OUTPUTSET7_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET7: SETn1 Position      */
+#define SCT_OUTPUTSET7_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn1_Pos)                      /*!< SCT OUTPUTSET7: SETn1 Mask          */
+#define SCT_OUTPUTSET7_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET7: SETn2 Position      */
+#define SCT_OUTPUTSET7_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn2_Pos)                      /*!< SCT OUTPUTSET7: SETn2 Mask          */
+#define SCT_OUTPUTSET7_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET7: SETn3 Position      */
+#define SCT_OUTPUTSET7_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn3_Pos)                      /*!< SCT OUTPUTSET7: SETn3 Mask          */
+#define SCT_OUTPUTSET7_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET7: SETn4 Position      */
+#define SCT_OUTPUTSET7_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn4_Pos)                      /*!< SCT OUTPUTSET7: SETn4 Mask          */
+#define SCT_OUTPUTSET7_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET7: SETn5 Position      */
+#define SCT_OUTPUTSET7_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn5_Pos)                      /*!< SCT OUTPUTSET7: SETn5 Mask          */
+#define SCT_OUTPUTSET7_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET7: SETn6 Position      */
+#define SCT_OUTPUTSET7_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn6_Pos)                      /*!< SCT OUTPUTSET7: SETn6 Mask          */
+#define SCT_OUTPUTSET7_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET7: SETn7 Position      */
+#define SCT_OUTPUTSET7_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn7_Pos)                      /*!< SCT OUTPUTSET7: SETn7 Mask          */
+#define SCT_OUTPUTSET7_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET7: SETn8 Position      */
+#define SCT_OUTPUTSET7_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn8_Pos)                      /*!< SCT OUTPUTSET7: SETn8 Mask          */
+#define SCT_OUTPUTSET7_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET7: SETn9 Position      */
+#define SCT_OUTPUTSET7_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn9_Pos)                      /*!< SCT OUTPUTSET7: SETn9 Mask          */
+#define SCT_OUTPUTSET7_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET7: SETn10 Position     */
+#define SCT_OUTPUTSET7_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn10_Pos)                     /*!< SCT OUTPUTSET7: SETn10 Mask         */
+#define SCT_OUTPUTSET7_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET7: SETn11 Position     */
+#define SCT_OUTPUTSET7_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn11_Pos)                     /*!< SCT OUTPUTSET7: SETn11 Mask         */
+#define SCT_OUTPUTSET7_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET7: SETn12 Position     */
+#define SCT_OUTPUTSET7_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn12_Pos)                     /*!< SCT OUTPUTSET7: SETn12 Mask         */
+#define SCT_OUTPUTSET7_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET7: SETn13 Position     */
+#define SCT_OUTPUTSET7_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn13_Pos)                     /*!< SCT OUTPUTSET7: SETn13 Mask         */
+#define SCT_OUTPUTSET7_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET7: SETn14 Position     */
+#define SCT_OUTPUTSET7_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn14_Pos)                     /*!< SCT OUTPUTSET7: SETn14 Mask         */
+#define SCT_OUTPUTSET7_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET7: SETn15 Position     */
+#define SCT_OUTPUTSET7_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn15_Pos)                     /*!< SCT OUTPUTSET7: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR7  -----------------------------------------
+#define SCT_OUTPUTCLR7_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR7: CLRn0 Position      */
+#define SCT_OUTPUTCLR7_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos)                      /*!< SCT OUTPUTCLR7: CLRn0 Mask          */
+#define SCT_OUTPUTCLR7_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR7: CLRn1 Position      */
+#define SCT_OUTPUTCLR7_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos)                      /*!< SCT OUTPUTCLR7: CLRn1 Mask          */
+#define SCT_OUTPUTCLR7_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR7: CLRn2 Position      */
+#define SCT_OUTPUTCLR7_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos)                      /*!< SCT OUTPUTCLR7: CLRn2 Mask          */
+#define SCT_OUTPUTCLR7_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR7: CLRn3 Position      */
+#define SCT_OUTPUTCLR7_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos)                      /*!< SCT OUTPUTCLR7: CLRn3 Mask          */
+#define SCT_OUTPUTCLR7_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR7: CLRn4 Position      */
+#define SCT_OUTPUTCLR7_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos)                      /*!< SCT OUTPUTCLR7: CLRn4 Mask          */
+#define SCT_OUTPUTCLR7_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR7: CLRn5 Position      */
+#define SCT_OUTPUTCLR7_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos)                      /*!< SCT OUTPUTCLR7: CLRn5 Mask          */
+#define SCT_OUTPUTCLR7_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR7: CLRn6 Position      */
+#define SCT_OUTPUTCLR7_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos)                      /*!< SCT OUTPUTCLR7: CLRn6 Mask          */
+#define SCT_OUTPUTCLR7_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR7: CLRn7 Position      */
+#define SCT_OUTPUTCLR7_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos)                      /*!< SCT OUTPUTCLR7: CLRn7 Mask          */
+#define SCT_OUTPUTCLR7_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR7: CLRn8 Position      */
+#define SCT_OUTPUTCLR7_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos)                      /*!< SCT OUTPUTCLR7: CLRn8 Mask          */
+#define SCT_OUTPUTCLR7_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR7: CLRn9 Position      */
+#define SCT_OUTPUTCLR7_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos)                      /*!< SCT OUTPUTCLR7: CLRn9 Mask          */
+#define SCT_OUTPUTCLR7_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR7: CLRn10 Position     */
+#define SCT_OUTPUTCLR7_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos)                     /*!< SCT OUTPUTCLR7: CLRn10 Mask         */
+#define SCT_OUTPUTCLR7_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR7: CLRn11 Position     */
+#define SCT_OUTPUTCLR7_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos)                     /*!< SCT OUTPUTCLR7: CLRn11 Mask         */
+#define SCT_OUTPUTCLR7_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR7: CLRn12 Position     */
+#define SCT_OUTPUTCLR7_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos)                     /*!< SCT OUTPUTCLR7: CLRn12 Mask         */
+#define SCT_OUTPUTCLR7_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR7: CLRn13 Position     */
+#define SCT_OUTPUTCLR7_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos)                     /*!< SCT OUTPUTCLR7: CLRn13 Mask         */
+#define SCT_OUTPUTCLR7_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR7: CLRn14 Position     */
+#define SCT_OUTPUTCLR7_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos)                     /*!< SCT OUTPUTCLR7: CLRn14 Mask         */
+#define SCT_OUTPUTCLR7_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR7: CLRn15 Position     */
+#define SCT_OUTPUTCLR7_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos)                     /*!< SCT OUTPUTCLR7: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET8  -----------------------------------------
+#define SCT_OUTPUTSET8_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET8: SETn0 Position      */
+#define SCT_OUTPUTSET8_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn0_Pos)                      /*!< SCT OUTPUTSET8: SETn0 Mask          */
+#define SCT_OUTPUTSET8_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET8: SETn1 Position      */
+#define SCT_OUTPUTSET8_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn1_Pos)                      /*!< SCT OUTPUTSET8: SETn1 Mask          */
+#define SCT_OUTPUTSET8_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET8: SETn2 Position      */
+#define SCT_OUTPUTSET8_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn2_Pos)                      /*!< SCT OUTPUTSET8: SETn2 Mask          */
+#define SCT_OUTPUTSET8_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET8: SETn3 Position      */
+#define SCT_OUTPUTSET8_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn3_Pos)                      /*!< SCT OUTPUTSET8: SETn3 Mask          */
+#define SCT_OUTPUTSET8_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET8: SETn4 Position      */
+#define SCT_OUTPUTSET8_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn4_Pos)                      /*!< SCT OUTPUTSET8: SETn4 Mask          */
+#define SCT_OUTPUTSET8_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET8: SETn5 Position      */
+#define SCT_OUTPUTSET8_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn5_Pos)                      /*!< SCT OUTPUTSET8: SETn5 Mask          */
+#define SCT_OUTPUTSET8_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET8: SETn6 Position      */
+#define SCT_OUTPUTSET8_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn6_Pos)                      /*!< SCT OUTPUTSET8: SETn6 Mask          */
+#define SCT_OUTPUTSET8_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET8: SETn7 Position      */
+#define SCT_OUTPUTSET8_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn7_Pos)                      /*!< SCT OUTPUTSET8: SETn7 Mask          */
+#define SCT_OUTPUTSET8_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET8: SETn8 Position      */
+#define SCT_OUTPUTSET8_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn8_Pos)                      /*!< SCT OUTPUTSET8: SETn8 Mask          */
+#define SCT_OUTPUTSET8_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET8: SETn9 Position      */
+#define SCT_OUTPUTSET8_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn9_Pos)                      /*!< SCT OUTPUTSET8: SETn9 Mask          */
+#define SCT_OUTPUTSET8_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET8: SETn10 Position     */
+#define SCT_OUTPUTSET8_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn10_Pos)                     /*!< SCT OUTPUTSET8: SETn10 Mask         */
+#define SCT_OUTPUTSET8_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET8: SETn11 Position     */
+#define SCT_OUTPUTSET8_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn11_Pos)                     /*!< SCT OUTPUTSET8: SETn11 Mask         */
+#define SCT_OUTPUTSET8_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET8: SETn12 Position     */
+#define SCT_OUTPUTSET8_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn12_Pos)                     /*!< SCT OUTPUTSET8: SETn12 Mask         */
+#define SCT_OUTPUTSET8_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET8: SETn13 Position     */
+#define SCT_OUTPUTSET8_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn13_Pos)                     /*!< SCT OUTPUTSET8: SETn13 Mask         */
+#define SCT_OUTPUTSET8_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET8: SETn14 Position     */
+#define SCT_OUTPUTSET8_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn14_Pos)                     /*!< SCT OUTPUTSET8: SETn14 Mask         */
+#define SCT_OUTPUTSET8_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET8: SETn15 Position     */
+#define SCT_OUTPUTSET8_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn15_Pos)                     /*!< SCT OUTPUTSET8: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR8  -----------------------------------------
+#define SCT_OUTPUTCLR8_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR8: CLRn0 Position      */
+#define SCT_OUTPUTCLR8_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos)                      /*!< SCT OUTPUTCLR8: CLRn0 Mask          */
+#define SCT_OUTPUTCLR8_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR8: CLRn1 Position      */
+#define SCT_OUTPUTCLR8_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos)                      /*!< SCT OUTPUTCLR8: CLRn1 Mask          */
+#define SCT_OUTPUTCLR8_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR8: CLRn2 Position      */
+#define SCT_OUTPUTCLR8_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos)                      /*!< SCT OUTPUTCLR8: CLRn2 Mask          */
+#define SCT_OUTPUTCLR8_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR8: CLRn3 Position      */
+#define SCT_OUTPUTCLR8_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos)                      /*!< SCT OUTPUTCLR8: CLRn3 Mask          */
+#define SCT_OUTPUTCLR8_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR8: CLRn4 Position      */
+#define SCT_OUTPUTCLR8_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos)                      /*!< SCT OUTPUTCLR8: CLRn4 Mask          */
+#define SCT_OUTPUTCLR8_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR8: CLRn5 Position      */
+#define SCT_OUTPUTCLR8_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos)                      /*!< SCT OUTPUTCLR8: CLRn5 Mask          */
+#define SCT_OUTPUTCLR8_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR8: CLRn6 Position      */
+#define SCT_OUTPUTCLR8_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos)                      /*!< SCT OUTPUTCLR8: CLRn6 Mask          */
+#define SCT_OUTPUTCLR8_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR8: CLRn7 Position      */
+#define SCT_OUTPUTCLR8_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos)                      /*!< SCT OUTPUTCLR8: CLRn7 Mask          */
+#define SCT_OUTPUTCLR8_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR8: CLRn8 Position      */
+#define SCT_OUTPUTCLR8_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos)                      /*!< SCT OUTPUTCLR8: CLRn8 Mask          */
+#define SCT_OUTPUTCLR8_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR8: CLRn9 Position      */
+#define SCT_OUTPUTCLR8_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos)                      /*!< SCT OUTPUTCLR8: CLRn9 Mask          */
+#define SCT_OUTPUTCLR8_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR8: CLRn10 Position     */
+#define SCT_OUTPUTCLR8_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos)                     /*!< SCT OUTPUTCLR8: CLRn10 Mask         */
+#define SCT_OUTPUTCLR8_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR8: CLRn11 Position     */
+#define SCT_OUTPUTCLR8_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos)                     /*!< SCT OUTPUTCLR8: CLRn11 Mask         */
+#define SCT_OUTPUTCLR8_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR8: CLRn12 Position     */
+#define SCT_OUTPUTCLR8_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos)                     /*!< SCT OUTPUTCLR8: CLRn12 Mask         */
+#define SCT_OUTPUTCLR8_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR8: CLRn13 Position     */
+#define SCT_OUTPUTCLR8_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos)                     /*!< SCT OUTPUTCLR8: CLRn13 Mask         */
+#define SCT_OUTPUTCLR8_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR8: CLRn14 Position     */
+#define SCT_OUTPUTCLR8_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos)                     /*!< SCT OUTPUTCLR8: CLRn14 Mask         */
+#define SCT_OUTPUTCLR8_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR8: CLRn15 Position     */
+#define SCT_OUTPUTCLR8_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos)                     /*!< SCT OUTPUTCLR8: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET9  -----------------------------------------
+#define SCT_OUTPUTSET9_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET9: SETn0 Position      */
+#define SCT_OUTPUTSET9_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn0_Pos)                      /*!< SCT OUTPUTSET9: SETn0 Mask          */
+#define SCT_OUTPUTSET9_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET9: SETn1 Position      */
+#define SCT_OUTPUTSET9_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn1_Pos)                      /*!< SCT OUTPUTSET9: SETn1 Mask          */
+#define SCT_OUTPUTSET9_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET9: SETn2 Position      */
+#define SCT_OUTPUTSET9_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn2_Pos)                      /*!< SCT OUTPUTSET9: SETn2 Mask          */
+#define SCT_OUTPUTSET9_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET9: SETn3 Position      */
+#define SCT_OUTPUTSET9_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn3_Pos)                      /*!< SCT OUTPUTSET9: SETn3 Mask          */
+#define SCT_OUTPUTSET9_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET9: SETn4 Position      */
+#define SCT_OUTPUTSET9_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn4_Pos)                      /*!< SCT OUTPUTSET9: SETn4 Mask          */
+#define SCT_OUTPUTSET9_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET9: SETn5 Position      */
+#define SCT_OUTPUTSET9_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn5_Pos)                      /*!< SCT OUTPUTSET9: SETn5 Mask          */
+#define SCT_OUTPUTSET9_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET9: SETn6 Position      */
+#define SCT_OUTPUTSET9_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn6_Pos)                      /*!< SCT OUTPUTSET9: SETn6 Mask          */
+#define SCT_OUTPUTSET9_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET9: SETn7 Position      */
+#define SCT_OUTPUTSET9_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn7_Pos)                      /*!< SCT OUTPUTSET9: SETn7 Mask          */
+#define SCT_OUTPUTSET9_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET9: SETn8 Position      */
+#define SCT_OUTPUTSET9_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn8_Pos)                      /*!< SCT OUTPUTSET9: SETn8 Mask          */
+#define SCT_OUTPUTSET9_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET9: SETn9 Position      */
+#define SCT_OUTPUTSET9_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn9_Pos)                      /*!< SCT OUTPUTSET9: SETn9 Mask          */
+#define SCT_OUTPUTSET9_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET9: SETn10 Position     */
+#define SCT_OUTPUTSET9_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn10_Pos)                     /*!< SCT OUTPUTSET9: SETn10 Mask         */
+#define SCT_OUTPUTSET9_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET9: SETn11 Position     */
+#define SCT_OUTPUTSET9_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn11_Pos)                     /*!< SCT OUTPUTSET9: SETn11 Mask         */
+#define SCT_OUTPUTSET9_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET9: SETn12 Position     */
+#define SCT_OUTPUTSET9_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn12_Pos)                     /*!< SCT OUTPUTSET9: SETn12 Mask         */
+#define SCT_OUTPUTSET9_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET9: SETn13 Position     */
+#define SCT_OUTPUTSET9_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn13_Pos)                     /*!< SCT OUTPUTSET9: SETn13 Mask         */
+#define SCT_OUTPUTSET9_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET9: SETn14 Position     */
+#define SCT_OUTPUTSET9_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn14_Pos)                     /*!< SCT OUTPUTSET9: SETn14 Mask         */
+#define SCT_OUTPUTSET9_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET9: SETn15 Position     */
+#define SCT_OUTPUTSET9_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn15_Pos)                     /*!< SCT OUTPUTSET9: SETn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTCLR9  -----------------------------------------
+#define SCT_OUTPUTCLR9_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR9: CLRn0 Position      */
+#define SCT_OUTPUTCLR9_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos)                      /*!< SCT OUTPUTCLR9: CLRn0 Mask          */
+#define SCT_OUTPUTCLR9_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR9: CLRn1 Position      */
+#define SCT_OUTPUTCLR9_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos)                      /*!< SCT OUTPUTCLR9: CLRn1 Mask          */
+#define SCT_OUTPUTCLR9_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR9: CLRn2 Position      */
+#define SCT_OUTPUTCLR9_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos)                      /*!< SCT OUTPUTCLR9: CLRn2 Mask          */
+#define SCT_OUTPUTCLR9_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR9: CLRn3 Position      */
+#define SCT_OUTPUTCLR9_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos)                      /*!< SCT OUTPUTCLR9: CLRn3 Mask          */
+#define SCT_OUTPUTCLR9_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR9: CLRn4 Position      */
+#define SCT_OUTPUTCLR9_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos)                      /*!< SCT OUTPUTCLR9: CLRn4 Mask          */
+#define SCT_OUTPUTCLR9_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR9: CLRn5 Position      */
+#define SCT_OUTPUTCLR9_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos)                      /*!< SCT OUTPUTCLR9: CLRn5 Mask          */
+#define SCT_OUTPUTCLR9_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR9: CLRn6 Position      */
+#define SCT_OUTPUTCLR9_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos)                      /*!< SCT OUTPUTCLR9: CLRn6 Mask          */
+#define SCT_OUTPUTCLR9_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR9: CLRn7 Position      */
+#define SCT_OUTPUTCLR9_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos)                      /*!< SCT OUTPUTCLR9: CLRn7 Mask          */
+#define SCT_OUTPUTCLR9_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR9: CLRn8 Position      */
+#define SCT_OUTPUTCLR9_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos)                      /*!< SCT OUTPUTCLR9: CLRn8 Mask          */
+#define SCT_OUTPUTCLR9_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR9: CLRn9 Position      */
+#define SCT_OUTPUTCLR9_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos)                      /*!< SCT OUTPUTCLR9: CLRn9 Mask          */
+#define SCT_OUTPUTCLR9_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR9: CLRn10 Position     */
+#define SCT_OUTPUTCLR9_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos)                     /*!< SCT OUTPUTCLR9: CLRn10 Mask         */
+#define SCT_OUTPUTCLR9_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR9: CLRn11 Position     */
+#define SCT_OUTPUTCLR9_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos)                     /*!< SCT OUTPUTCLR9: CLRn11 Mask         */
+#define SCT_OUTPUTCLR9_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR9: CLRn12 Position     */
+#define SCT_OUTPUTCLR9_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos)                     /*!< SCT OUTPUTCLR9: CLRn12 Mask         */
+#define SCT_OUTPUTCLR9_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR9: CLRn13 Position     */
+#define SCT_OUTPUTCLR9_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos)                     /*!< SCT OUTPUTCLR9: CLRn13 Mask         */
+#define SCT_OUTPUTCLR9_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR9: CLRn14 Position     */
+#define SCT_OUTPUTCLR9_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos)                     /*!< SCT OUTPUTCLR9: CLRn14 Mask         */
+#define SCT_OUTPUTCLR9_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR9: CLRn15 Position     */
+#define SCT_OUTPUTCLR9_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos)                     /*!< SCT OUTPUTCLR9: CLRn15 Mask         */
+
+// -------------------------------------  SCT_OUTPUTSET10  ----------------------------------------
+#define SCT_OUTPUTSET10_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET10: SETn0 Position     */
+#define SCT_OUTPUTSET10_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn0_Pos)                     /*!< SCT OUTPUTSET10: SETn0 Mask         */
+#define SCT_OUTPUTSET10_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET10: SETn1 Position     */
+#define SCT_OUTPUTSET10_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn1_Pos)                     /*!< SCT OUTPUTSET10: SETn1 Mask         */
+#define SCT_OUTPUTSET10_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET10: SETn2 Position     */
+#define SCT_OUTPUTSET10_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn2_Pos)                     /*!< SCT OUTPUTSET10: SETn2 Mask         */
+#define SCT_OUTPUTSET10_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET10: SETn3 Position     */
+#define SCT_OUTPUTSET10_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn3_Pos)                     /*!< SCT OUTPUTSET10: SETn3 Mask         */
+#define SCT_OUTPUTSET10_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET10: SETn4 Position     */
+#define SCT_OUTPUTSET10_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn4_Pos)                     /*!< SCT OUTPUTSET10: SETn4 Mask         */
+#define SCT_OUTPUTSET10_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET10: SETn5 Position     */
+#define SCT_OUTPUTSET10_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn5_Pos)                     /*!< SCT OUTPUTSET10: SETn5 Mask         */
+#define SCT_OUTPUTSET10_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET10: SETn6 Position     */
+#define SCT_OUTPUTSET10_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn6_Pos)                     /*!< SCT OUTPUTSET10: SETn6 Mask         */
+#define SCT_OUTPUTSET10_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET10: SETn7 Position     */
+#define SCT_OUTPUTSET10_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn7_Pos)                     /*!< SCT OUTPUTSET10: SETn7 Mask         */
+#define SCT_OUTPUTSET10_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET10: SETn8 Position     */
+#define SCT_OUTPUTSET10_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn8_Pos)                     /*!< SCT OUTPUTSET10: SETn8 Mask         */
+#define SCT_OUTPUTSET10_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET10: SETn9 Position     */
+#define SCT_OUTPUTSET10_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn9_Pos)                     /*!< SCT OUTPUTSET10: SETn9 Mask         */
+#define SCT_OUTPUTSET10_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET10: SETn10 Position    */
+#define SCT_OUTPUTSET10_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn10_Pos)                    /*!< SCT OUTPUTSET10: SETn10 Mask        */
+#define SCT_OUTPUTSET10_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET10: SETn11 Position    */
+#define SCT_OUTPUTSET10_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn11_Pos)                    /*!< SCT OUTPUTSET10: SETn11 Mask        */
+#define SCT_OUTPUTSET10_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET10: SETn12 Position    */
+#define SCT_OUTPUTSET10_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn12_Pos)                    /*!< SCT OUTPUTSET10: SETn12 Mask        */
+#define SCT_OUTPUTSET10_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET10: SETn13 Position    */
+#define SCT_OUTPUTSET10_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn13_Pos)                    /*!< SCT OUTPUTSET10: SETn13 Mask        */
+#define SCT_OUTPUTSET10_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET10: SETn14 Position    */
+#define SCT_OUTPUTSET10_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn14_Pos)                    /*!< SCT OUTPUTSET10: SETn14 Mask        */
+#define SCT_OUTPUTSET10_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET10: SETn15 Position    */
+#define SCT_OUTPUTSET10_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn15_Pos)                    /*!< SCT OUTPUTSET10: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR10  ----------------------------------------
+#define SCT_OUTPUTCLR10_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR10: CLRn0 Position     */
+#define SCT_OUTPUTCLR10_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos)                     /*!< SCT OUTPUTCLR10: CLRn0 Mask         */
+#define SCT_OUTPUTCLR10_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR10: CLRn1 Position     */
+#define SCT_OUTPUTCLR10_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos)                     /*!< SCT OUTPUTCLR10: CLRn1 Mask         */
+#define SCT_OUTPUTCLR10_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR10: CLRn2 Position     */
+#define SCT_OUTPUTCLR10_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos)                     /*!< SCT OUTPUTCLR10: CLRn2 Mask         */
+#define SCT_OUTPUTCLR10_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR10: CLRn3 Position     */
+#define SCT_OUTPUTCLR10_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos)                     /*!< SCT OUTPUTCLR10: CLRn3 Mask         */
+#define SCT_OUTPUTCLR10_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR10: CLRn4 Position     */
+#define SCT_OUTPUTCLR10_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos)                     /*!< SCT OUTPUTCLR10: CLRn4 Mask         */
+#define SCT_OUTPUTCLR10_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR10: CLRn5 Position     */
+#define SCT_OUTPUTCLR10_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos)                     /*!< SCT OUTPUTCLR10: CLRn5 Mask         */
+#define SCT_OUTPUTCLR10_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR10: CLRn6 Position     */
+#define SCT_OUTPUTCLR10_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos)                     /*!< SCT OUTPUTCLR10: CLRn6 Mask         */
+#define SCT_OUTPUTCLR10_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR10: CLRn7 Position     */
+#define SCT_OUTPUTCLR10_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos)                     /*!< SCT OUTPUTCLR10: CLRn7 Mask         */
+#define SCT_OUTPUTCLR10_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR10: CLRn8 Position     */
+#define SCT_OUTPUTCLR10_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos)                     /*!< SCT OUTPUTCLR10: CLRn8 Mask         */
+#define SCT_OUTPUTCLR10_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR10: CLRn9 Position     */
+#define SCT_OUTPUTCLR10_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos)                     /*!< SCT OUTPUTCLR10: CLRn9 Mask         */
+#define SCT_OUTPUTCLR10_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR10: CLRn10 Position    */
+#define SCT_OUTPUTCLR10_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos)                    /*!< SCT OUTPUTCLR10: CLRn10 Mask        */
+#define SCT_OUTPUTCLR10_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR10: CLRn11 Position    */
+#define SCT_OUTPUTCLR10_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos)                    /*!< SCT OUTPUTCLR10: CLRn11 Mask        */
+#define SCT_OUTPUTCLR10_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR10: CLRn12 Position    */
+#define SCT_OUTPUTCLR10_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos)                    /*!< SCT OUTPUTCLR10: CLRn12 Mask        */
+#define SCT_OUTPUTCLR10_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR10: CLRn13 Position    */
+#define SCT_OUTPUTCLR10_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos)                    /*!< SCT OUTPUTCLR10: CLRn13 Mask        */
+#define SCT_OUTPUTCLR10_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR10: CLRn14 Position    */
+#define SCT_OUTPUTCLR10_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos)                    /*!< SCT OUTPUTCLR10: CLRn14 Mask        */
+#define SCT_OUTPUTCLR10_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR10: CLRn15 Position    */
+#define SCT_OUTPUTCLR10_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos)                    /*!< SCT OUTPUTCLR10: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET11  ----------------------------------------
+#define SCT_OUTPUTSET11_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET11: SETn0 Position     */
+#define SCT_OUTPUTSET11_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn0_Pos)                     /*!< SCT OUTPUTSET11: SETn0 Mask         */
+#define SCT_OUTPUTSET11_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET11: SETn1 Position     */
+#define SCT_OUTPUTSET11_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn1_Pos)                     /*!< SCT OUTPUTSET11: SETn1 Mask         */
+#define SCT_OUTPUTSET11_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET11: SETn2 Position     */
+#define SCT_OUTPUTSET11_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn2_Pos)                     /*!< SCT OUTPUTSET11: SETn2 Mask         */
+#define SCT_OUTPUTSET11_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET11: SETn3 Position     */
+#define SCT_OUTPUTSET11_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn3_Pos)                     /*!< SCT OUTPUTSET11: SETn3 Mask         */
+#define SCT_OUTPUTSET11_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET11: SETn4 Position     */
+#define SCT_OUTPUTSET11_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn4_Pos)                     /*!< SCT OUTPUTSET11: SETn4 Mask         */
+#define SCT_OUTPUTSET11_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET11: SETn5 Position     */
+#define SCT_OUTPUTSET11_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn5_Pos)                     /*!< SCT OUTPUTSET11: SETn5 Mask         */
+#define SCT_OUTPUTSET11_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET11: SETn6 Position     */
+#define SCT_OUTPUTSET11_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn6_Pos)                     /*!< SCT OUTPUTSET11: SETn6 Mask         */
+#define SCT_OUTPUTSET11_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET11: SETn7 Position     */
+#define SCT_OUTPUTSET11_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn7_Pos)                     /*!< SCT OUTPUTSET11: SETn7 Mask         */
+#define SCT_OUTPUTSET11_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET11: SETn8 Position     */
+#define SCT_OUTPUTSET11_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn8_Pos)                     /*!< SCT OUTPUTSET11: SETn8 Mask         */
+#define SCT_OUTPUTSET11_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET11: SETn9 Position     */
+#define SCT_OUTPUTSET11_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn9_Pos)                     /*!< SCT OUTPUTSET11: SETn9 Mask         */
+#define SCT_OUTPUTSET11_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET11: SETn10 Position    */
+#define SCT_OUTPUTSET11_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn10_Pos)                    /*!< SCT OUTPUTSET11: SETn10 Mask        */
+#define SCT_OUTPUTSET11_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET11: SETn11 Position    */
+#define SCT_OUTPUTSET11_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn11_Pos)                    /*!< SCT OUTPUTSET11: SETn11 Mask        */
+#define SCT_OUTPUTSET11_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET11: SETn12 Position    */
+#define SCT_OUTPUTSET11_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn12_Pos)                    /*!< SCT OUTPUTSET11: SETn12 Mask        */
+#define SCT_OUTPUTSET11_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET11: SETn13 Position    */
+#define SCT_OUTPUTSET11_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn13_Pos)                    /*!< SCT OUTPUTSET11: SETn13 Mask        */
+#define SCT_OUTPUTSET11_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET11: SETn14 Position    */
+#define SCT_OUTPUTSET11_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn14_Pos)                    /*!< SCT OUTPUTSET11: SETn14 Mask        */
+#define SCT_OUTPUTSET11_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET11: SETn15 Position    */
+#define SCT_OUTPUTSET11_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn15_Pos)                    /*!< SCT OUTPUTSET11: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR11  ----------------------------------------
+#define SCT_OUTPUTCLR11_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR11: CLRn0 Position     */
+#define SCT_OUTPUTCLR11_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos)                     /*!< SCT OUTPUTCLR11: CLRn0 Mask         */
+#define SCT_OUTPUTCLR11_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR11: CLRn1 Position     */
+#define SCT_OUTPUTCLR11_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos)                     /*!< SCT OUTPUTCLR11: CLRn1 Mask         */
+#define SCT_OUTPUTCLR11_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR11: CLRn2 Position     */
+#define SCT_OUTPUTCLR11_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos)                     /*!< SCT OUTPUTCLR11: CLRn2 Mask         */
+#define SCT_OUTPUTCLR11_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR11: CLRn3 Position     */
+#define SCT_OUTPUTCLR11_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos)                     /*!< SCT OUTPUTCLR11: CLRn3 Mask         */
+#define SCT_OUTPUTCLR11_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR11: CLRn4 Position     */
+#define SCT_OUTPUTCLR11_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos)                     /*!< SCT OUTPUTCLR11: CLRn4 Mask         */
+#define SCT_OUTPUTCLR11_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR11: CLRn5 Position     */
+#define SCT_OUTPUTCLR11_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos)                     /*!< SCT OUTPUTCLR11: CLRn5 Mask         */
+#define SCT_OUTPUTCLR11_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR11: CLRn6 Position     */
+#define SCT_OUTPUTCLR11_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos)                     /*!< SCT OUTPUTCLR11: CLRn6 Mask         */
+#define SCT_OUTPUTCLR11_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR11: CLRn7 Position     */
+#define SCT_OUTPUTCLR11_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos)                     /*!< SCT OUTPUTCLR11: CLRn7 Mask         */
+#define SCT_OUTPUTCLR11_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR11: CLRn8 Position     */
+#define SCT_OUTPUTCLR11_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos)                     /*!< SCT OUTPUTCLR11: CLRn8 Mask         */
+#define SCT_OUTPUTCLR11_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR11: CLRn9 Position     */
+#define SCT_OUTPUTCLR11_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos)                     /*!< SCT OUTPUTCLR11: CLRn9 Mask         */
+#define SCT_OUTPUTCLR11_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR11: CLRn10 Position    */
+#define SCT_OUTPUTCLR11_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos)                    /*!< SCT OUTPUTCLR11: CLRn10 Mask        */
+#define SCT_OUTPUTCLR11_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR11: CLRn11 Position    */
+#define SCT_OUTPUTCLR11_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos)                    /*!< SCT OUTPUTCLR11: CLRn11 Mask        */
+#define SCT_OUTPUTCLR11_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR11: CLRn12 Position    */
+#define SCT_OUTPUTCLR11_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos)                    /*!< SCT OUTPUTCLR11: CLRn12 Mask        */
+#define SCT_OUTPUTCLR11_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR11: CLRn13 Position    */
+#define SCT_OUTPUTCLR11_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos)                    /*!< SCT OUTPUTCLR11: CLRn13 Mask        */
+#define SCT_OUTPUTCLR11_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR11: CLRn14 Position    */
+#define SCT_OUTPUTCLR11_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos)                    /*!< SCT OUTPUTCLR11: CLRn14 Mask        */
+#define SCT_OUTPUTCLR11_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR11: CLRn15 Position    */
+#define SCT_OUTPUTCLR11_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos)                    /*!< SCT OUTPUTCLR11: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET12  ----------------------------------------
+#define SCT_OUTPUTSET12_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET12: SETn0 Position     */
+#define SCT_OUTPUTSET12_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn0_Pos)                     /*!< SCT OUTPUTSET12: SETn0 Mask         */
+#define SCT_OUTPUTSET12_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET12: SETn1 Position     */
+#define SCT_OUTPUTSET12_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn1_Pos)                     /*!< SCT OUTPUTSET12: SETn1 Mask         */
+#define SCT_OUTPUTSET12_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET12: SETn2 Position     */
+#define SCT_OUTPUTSET12_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn2_Pos)                     /*!< SCT OUTPUTSET12: SETn2 Mask         */
+#define SCT_OUTPUTSET12_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET12: SETn3 Position     */
+#define SCT_OUTPUTSET12_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn3_Pos)                     /*!< SCT OUTPUTSET12: SETn3 Mask         */
+#define SCT_OUTPUTSET12_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET12: SETn4 Position     */
+#define SCT_OUTPUTSET12_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn4_Pos)                     /*!< SCT OUTPUTSET12: SETn4 Mask         */
+#define SCT_OUTPUTSET12_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET12: SETn5 Position     */
+#define SCT_OUTPUTSET12_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn5_Pos)                     /*!< SCT OUTPUTSET12: SETn5 Mask         */
+#define SCT_OUTPUTSET12_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET12: SETn6 Position     */
+#define SCT_OUTPUTSET12_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn6_Pos)                     /*!< SCT OUTPUTSET12: SETn6 Mask         */
+#define SCT_OUTPUTSET12_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET12: SETn7 Position     */
+#define SCT_OUTPUTSET12_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn7_Pos)                     /*!< SCT OUTPUTSET12: SETn7 Mask         */
+#define SCT_OUTPUTSET12_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET12: SETn8 Position     */
+#define SCT_OUTPUTSET12_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn8_Pos)                     /*!< SCT OUTPUTSET12: SETn8 Mask         */
+#define SCT_OUTPUTSET12_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET12: SETn9 Position     */
+#define SCT_OUTPUTSET12_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn9_Pos)                     /*!< SCT OUTPUTSET12: SETn9 Mask         */
+#define SCT_OUTPUTSET12_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET12: SETn10 Position    */
+#define SCT_OUTPUTSET12_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn10_Pos)                    /*!< SCT OUTPUTSET12: SETn10 Mask        */
+#define SCT_OUTPUTSET12_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET12: SETn11 Position    */
+#define SCT_OUTPUTSET12_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn11_Pos)                    /*!< SCT OUTPUTSET12: SETn11 Mask        */
+#define SCT_OUTPUTSET12_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET12: SETn12 Position    */
+#define SCT_OUTPUTSET12_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn12_Pos)                    /*!< SCT OUTPUTSET12: SETn12 Mask        */
+#define SCT_OUTPUTSET12_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET12: SETn13 Position    */
+#define SCT_OUTPUTSET12_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn13_Pos)                    /*!< SCT OUTPUTSET12: SETn13 Mask        */
+#define SCT_OUTPUTSET12_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET12: SETn14 Position    */
+#define SCT_OUTPUTSET12_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn14_Pos)                    /*!< SCT OUTPUTSET12: SETn14 Mask        */
+#define SCT_OUTPUTSET12_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET12: SETn15 Position    */
+#define SCT_OUTPUTSET12_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn15_Pos)                    /*!< SCT OUTPUTSET12: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR12  ----------------------------------------
+#define SCT_OUTPUTCLR12_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR12: CLRn0 Position     */
+#define SCT_OUTPUTCLR12_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos)                     /*!< SCT OUTPUTCLR12: CLRn0 Mask         */
+#define SCT_OUTPUTCLR12_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR12: CLRn1 Position     */
+#define SCT_OUTPUTCLR12_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos)                     /*!< SCT OUTPUTCLR12: CLRn1 Mask         */
+#define SCT_OUTPUTCLR12_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR12: CLRn2 Position     */
+#define SCT_OUTPUTCLR12_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos)                     /*!< SCT OUTPUTCLR12: CLRn2 Mask         */
+#define SCT_OUTPUTCLR12_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR12: CLRn3 Position     */
+#define SCT_OUTPUTCLR12_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos)                     /*!< SCT OUTPUTCLR12: CLRn3 Mask         */
+#define SCT_OUTPUTCLR12_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR12: CLRn4 Position     */
+#define SCT_OUTPUTCLR12_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos)                     /*!< SCT OUTPUTCLR12: CLRn4 Mask         */
+#define SCT_OUTPUTCLR12_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR12: CLRn5 Position     */
+#define SCT_OUTPUTCLR12_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos)                     /*!< SCT OUTPUTCLR12: CLRn5 Mask         */
+#define SCT_OUTPUTCLR12_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR12: CLRn6 Position     */
+#define SCT_OUTPUTCLR12_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos)                     /*!< SCT OUTPUTCLR12: CLRn6 Mask         */
+#define SCT_OUTPUTCLR12_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR12: CLRn7 Position     */
+#define SCT_OUTPUTCLR12_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos)                     /*!< SCT OUTPUTCLR12: CLRn7 Mask         */
+#define SCT_OUTPUTCLR12_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR12: CLRn8 Position     */
+#define SCT_OUTPUTCLR12_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos)                     /*!< SCT OUTPUTCLR12: CLRn8 Mask         */
+#define SCT_OUTPUTCLR12_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR12: CLRn9 Position     */
+#define SCT_OUTPUTCLR12_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos)                     /*!< SCT OUTPUTCLR12: CLRn9 Mask         */
+#define SCT_OUTPUTCLR12_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR12: CLRn10 Position    */
+#define SCT_OUTPUTCLR12_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos)                    /*!< SCT OUTPUTCLR12: CLRn10 Mask        */
+#define SCT_OUTPUTCLR12_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR12: CLRn11 Position    */
+#define SCT_OUTPUTCLR12_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos)                    /*!< SCT OUTPUTCLR12: CLRn11 Mask        */
+#define SCT_OUTPUTCLR12_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR12: CLRn12 Position    */
+#define SCT_OUTPUTCLR12_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos)                    /*!< SCT OUTPUTCLR12: CLRn12 Mask        */
+#define SCT_OUTPUTCLR12_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR12: CLRn13 Position    */
+#define SCT_OUTPUTCLR12_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos)                    /*!< SCT OUTPUTCLR12: CLRn13 Mask        */
+#define SCT_OUTPUTCLR12_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR12: CLRn14 Position    */
+#define SCT_OUTPUTCLR12_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos)                    /*!< SCT OUTPUTCLR12: CLRn14 Mask        */
+#define SCT_OUTPUTCLR12_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR12: CLRn15 Position    */
+#define SCT_OUTPUTCLR12_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos)                    /*!< SCT OUTPUTCLR12: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET13  ----------------------------------------
+#define SCT_OUTPUTSET13_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET13: SETn0 Position     */
+#define SCT_OUTPUTSET13_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn0_Pos)                     /*!< SCT OUTPUTSET13: SETn0 Mask         */
+#define SCT_OUTPUTSET13_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET13: SETn1 Position     */
+#define SCT_OUTPUTSET13_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn1_Pos)                     /*!< SCT OUTPUTSET13: SETn1 Mask         */
+#define SCT_OUTPUTSET13_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET13: SETn2 Position     */
+#define SCT_OUTPUTSET13_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn2_Pos)                     /*!< SCT OUTPUTSET13: SETn2 Mask         */
+#define SCT_OUTPUTSET13_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET13: SETn3 Position     */
+#define SCT_OUTPUTSET13_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn3_Pos)                     /*!< SCT OUTPUTSET13: SETn3 Mask         */
+#define SCT_OUTPUTSET13_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET13: SETn4 Position     */
+#define SCT_OUTPUTSET13_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn4_Pos)                     /*!< SCT OUTPUTSET13: SETn4 Mask         */
+#define SCT_OUTPUTSET13_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET13: SETn5 Position     */
+#define SCT_OUTPUTSET13_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn5_Pos)                     /*!< SCT OUTPUTSET13: SETn5 Mask         */
+#define SCT_OUTPUTSET13_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET13: SETn6 Position     */
+#define SCT_OUTPUTSET13_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn6_Pos)                     /*!< SCT OUTPUTSET13: SETn6 Mask         */
+#define SCT_OUTPUTSET13_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET13: SETn7 Position     */
+#define SCT_OUTPUTSET13_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn7_Pos)                     /*!< SCT OUTPUTSET13: SETn7 Mask         */
+#define SCT_OUTPUTSET13_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET13: SETn8 Position     */
+#define SCT_OUTPUTSET13_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn8_Pos)                     /*!< SCT OUTPUTSET13: SETn8 Mask         */
+#define SCT_OUTPUTSET13_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET13: SETn9 Position     */
+#define SCT_OUTPUTSET13_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn9_Pos)                     /*!< SCT OUTPUTSET13: SETn9 Mask         */
+#define SCT_OUTPUTSET13_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET13: SETn10 Position    */
+#define SCT_OUTPUTSET13_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn10_Pos)                    /*!< SCT OUTPUTSET13: SETn10 Mask        */
+#define SCT_OUTPUTSET13_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET13: SETn11 Position    */
+#define SCT_OUTPUTSET13_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn11_Pos)                    /*!< SCT OUTPUTSET13: SETn11 Mask        */
+#define SCT_OUTPUTSET13_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET13: SETn12 Position    */
+#define SCT_OUTPUTSET13_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn12_Pos)                    /*!< SCT OUTPUTSET13: SETn12 Mask        */
+#define SCT_OUTPUTSET13_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET13: SETn13 Position    */
+#define SCT_OUTPUTSET13_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn13_Pos)                    /*!< SCT OUTPUTSET13: SETn13 Mask        */
+#define SCT_OUTPUTSET13_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET13: SETn14 Position    */
+#define SCT_OUTPUTSET13_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn14_Pos)                    /*!< SCT OUTPUTSET13: SETn14 Mask        */
+#define SCT_OUTPUTSET13_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET13: SETn15 Position    */
+#define SCT_OUTPUTSET13_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn15_Pos)                    /*!< SCT OUTPUTSET13: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR13  ----------------------------------------
+#define SCT_OUTPUTCLR13_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR13: CLRn0 Position     */
+#define SCT_OUTPUTCLR13_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos)                     /*!< SCT OUTPUTCLR13: CLRn0 Mask         */
+#define SCT_OUTPUTCLR13_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR13: CLRn1 Position     */
+#define SCT_OUTPUTCLR13_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos)                     /*!< SCT OUTPUTCLR13: CLRn1 Mask         */
+#define SCT_OUTPUTCLR13_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR13: CLRn2 Position     */
+#define SCT_OUTPUTCLR13_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos)                     /*!< SCT OUTPUTCLR13: CLRn2 Mask         */
+#define SCT_OUTPUTCLR13_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR13: CLRn3 Position     */
+#define SCT_OUTPUTCLR13_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos)                     /*!< SCT OUTPUTCLR13: CLRn3 Mask         */
+#define SCT_OUTPUTCLR13_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR13: CLRn4 Position     */
+#define SCT_OUTPUTCLR13_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos)                     /*!< SCT OUTPUTCLR13: CLRn4 Mask         */
+#define SCT_OUTPUTCLR13_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR13: CLRn5 Position     */
+#define SCT_OUTPUTCLR13_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos)                     /*!< SCT OUTPUTCLR13: CLRn5 Mask         */
+#define SCT_OUTPUTCLR13_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR13: CLRn6 Position     */
+#define SCT_OUTPUTCLR13_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos)                     /*!< SCT OUTPUTCLR13: CLRn6 Mask         */
+#define SCT_OUTPUTCLR13_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR13: CLRn7 Position     */
+#define SCT_OUTPUTCLR13_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos)                     /*!< SCT OUTPUTCLR13: CLRn7 Mask         */
+#define SCT_OUTPUTCLR13_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR13: CLRn8 Position     */
+#define SCT_OUTPUTCLR13_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos)                     /*!< SCT OUTPUTCLR13: CLRn8 Mask         */
+#define SCT_OUTPUTCLR13_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR13: CLRn9 Position     */
+#define SCT_OUTPUTCLR13_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos)                     /*!< SCT OUTPUTCLR13: CLRn9 Mask         */
+#define SCT_OUTPUTCLR13_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR13: CLRn10 Position    */
+#define SCT_OUTPUTCLR13_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos)                    /*!< SCT OUTPUTCLR13: CLRn10 Mask        */
+#define SCT_OUTPUTCLR13_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR13: CLRn11 Position    */
+#define SCT_OUTPUTCLR13_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos)                    /*!< SCT OUTPUTCLR13: CLRn11 Mask        */
+#define SCT_OUTPUTCLR13_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR13: CLRn12 Position    */
+#define SCT_OUTPUTCLR13_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos)                    /*!< SCT OUTPUTCLR13: CLRn12 Mask        */
+#define SCT_OUTPUTCLR13_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR13: CLRn13 Position    */
+#define SCT_OUTPUTCLR13_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos)                    /*!< SCT OUTPUTCLR13: CLRn13 Mask        */
+#define SCT_OUTPUTCLR13_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR13: CLRn14 Position    */
+#define SCT_OUTPUTCLR13_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos)                    /*!< SCT OUTPUTCLR13: CLRn14 Mask        */
+#define SCT_OUTPUTCLR13_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR13: CLRn15 Position    */
+#define SCT_OUTPUTCLR13_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos)                    /*!< SCT OUTPUTCLR13: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET14  ----------------------------------------
+#define SCT_OUTPUTSET14_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET14: SETn0 Position     */
+#define SCT_OUTPUTSET14_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn0_Pos)                     /*!< SCT OUTPUTSET14: SETn0 Mask         */
+#define SCT_OUTPUTSET14_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET14: SETn1 Position     */
+#define SCT_OUTPUTSET14_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn1_Pos)                     /*!< SCT OUTPUTSET14: SETn1 Mask         */
+#define SCT_OUTPUTSET14_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET14: SETn2 Position     */
+#define SCT_OUTPUTSET14_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn2_Pos)                     /*!< SCT OUTPUTSET14: SETn2 Mask         */
+#define SCT_OUTPUTSET14_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET14: SETn3 Position     */
+#define SCT_OUTPUTSET14_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn3_Pos)                     /*!< SCT OUTPUTSET14: SETn3 Mask         */
+#define SCT_OUTPUTSET14_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET14: SETn4 Position     */
+#define SCT_OUTPUTSET14_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn4_Pos)                     /*!< SCT OUTPUTSET14: SETn4 Mask         */
+#define SCT_OUTPUTSET14_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET14: SETn5 Position     */
+#define SCT_OUTPUTSET14_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn5_Pos)                     /*!< SCT OUTPUTSET14: SETn5 Mask         */
+#define SCT_OUTPUTSET14_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET14: SETn6 Position     */
+#define SCT_OUTPUTSET14_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn6_Pos)                     /*!< SCT OUTPUTSET14: SETn6 Mask         */
+#define SCT_OUTPUTSET14_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET14: SETn7 Position     */
+#define SCT_OUTPUTSET14_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn7_Pos)                     /*!< SCT OUTPUTSET14: SETn7 Mask         */
+#define SCT_OUTPUTSET14_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET14: SETn8 Position     */
+#define SCT_OUTPUTSET14_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn8_Pos)                     /*!< SCT OUTPUTSET14: SETn8 Mask         */
+#define SCT_OUTPUTSET14_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET14: SETn9 Position     */
+#define SCT_OUTPUTSET14_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn9_Pos)                     /*!< SCT OUTPUTSET14: SETn9 Mask         */
+#define SCT_OUTPUTSET14_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET14: SETn10 Position    */
+#define SCT_OUTPUTSET14_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn10_Pos)                    /*!< SCT OUTPUTSET14: SETn10 Mask        */
+#define SCT_OUTPUTSET14_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET14: SETn11 Position    */
+#define SCT_OUTPUTSET14_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn11_Pos)                    /*!< SCT OUTPUTSET14: SETn11 Mask        */
+#define SCT_OUTPUTSET14_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET14: SETn12 Position    */
+#define SCT_OUTPUTSET14_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn12_Pos)                    /*!< SCT OUTPUTSET14: SETn12 Mask        */
+#define SCT_OUTPUTSET14_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET14: SETn13 Position    */
+#define SCT_OUTPUTSET14_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn13_Pos)                    /*!< SCT OUTPUTSET14: SETn13 Mask        */
+#define SCT_OUTPUTSET14_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET14: SETn14 Position    */
+#define SCT_OUTPUTSET14_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn14_Pos)                    /*!< SCT OUTPUTSET14: SETn14 Mask        */
+#define SCT_OUTPUTSET14_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET14: SETn15 Position    */
+#define SCT_OUTPUTSET14_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn15_Pos)                    /*!< SCT OUTPUTSET14: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR14  ----------------------------------------
+#define SCT_OUTPUTCLR14_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR14: CLRn0 Position     */
+#define SCT_OUTPUTCLR14_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos)                     /*!< SCT OUTPUTCLR14: CLRn0 Mask         */
+#define SCT_OUTPUTCLR14_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR14: CLRn1 Position     */
+#define SCT_OUTPUTCLR14_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos)                     /*!< SCT OUTPUTCLR14: CLRn1 Mask         */
+#define SCT_OUTPUTCLR14_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR14: CLRn2 Position     */
+#define SCT_OUTPUTCLR14_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos)                     /*!< SCT OUTPUTCLR14: CLRn2 Mask         */
+#define SCT_OUTPUTCLR14_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR14: CLRn3 Position     */
+#define SCT_OUTPUTCLR14_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos)                     /*!< SCT OUTPUTCLR14: CLRn3 Mask         */
+#define SCT_OUTPUTCLR14_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR14: CLRn4 Position     */
+#define SCT_OUTPUTCLR14_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos)                     /*!< SCT OUTPUTCLR14: CLRn4 Mask         */
+#define SCT_OUTPUTCLR14_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR14: CLRn5 Position     */
+#define SCT_OUTPUTCLR14_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos)                     /*!< SCT OUTPUTCLR14: CLRn5 Mask         */
+#define SCT_OUTPUTCLR14_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR14: CLRn6 Position     */
+#define SCT_OUTPUTCLR14_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos)                     /*!< SCT OUTPUTCLR14: CLRn6 Mask         */
+#define SCT_OUTPUTCLR14_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR14: CLRn7 Position     */
+#define SCT_OUTPUTCLR14_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos)                     /*!< SCT OUTPUTCLR14: CLRn7 Mask         */
+#define SCT_OUTPUTCLR14_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR14: CLRn8 Position     */
+#define SCT_OUTPUTCLR14_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos)                     /*!< SCT OUTPUTCLR14: CLRn8 Mask         */
+#define SCT_OUTPUTCLR14_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR14: CLRn9 Position     */
+#define SCT_OUTPUTCLR14_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos)                     /*!< SCT OUTPUTCLR14: CLRn9 Mask         */
+#define SCT_OUTPUTCLR14_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR14: CLRn10 Position    */
+#define SCT_OUTPUTCLR14_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos)                    /*!< SCT OUTPUTCLR14: CLRn10 Mask        */
+#define SCT_OUTPUTCLR14_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR14: CLRn11 Position    */
+#define SCT_OUTPUTCLR14_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos)                    /*!< SCT OUTPUTCLR14: CLRn11 Mask        */
+#define SCT_OUTPUTCLR14_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR14: CLRn12 Position    */
+#define SCT_OUTPUTCLR14_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos)                    /*!< SCT OUTPUTCLR14: CLRn12 Mask        */
+#define SCT_OUTPUTCLR14_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR14: CLRn13 Position    */
+#define SCT_OUTPUTCLR14_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos)                    /*!< SCT OUTPUTCLR14: CLRn13 Mask        */
+#define SCT_OUTPUTCLR14_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR14: CLRn14 Position    */
+#define SCT_OUTPUTCLR14_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos)                    /*!< SCT OUTPUTCLR14: CLRn14 Mask        */
+#define SCT_OUTPUTCLR14_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR14: CLRn15 Position    */
+#define SCT_OUTPUTCLR14_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos)                    /*!< SCT OUTPUTCLR14: CLRn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTSET15  ----------------------------------------
+#define SCT_OUTPUTSET15_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET15: SETn0 Position     */
+#define SCT_OUTPUTSET15_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn0_Pos)                     /*!< SCT OUTPUTSET15: SETn0 Mask         */
+#define SCT_OUTPUTSET15_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET15: SETn1 Position     */
+#define SCT_OUTPUTSET15_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn1_Pos)                     /*!< SCT OUTPUTSET15: SETn1 Mask         */
+#define SCT_OUTPUTSET15_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET15: SETn2 Position     */
+#define SCT_OUTPUTSET15_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn2_Pos)                     /*!< SCT OUTPUTSET15: SETn2 Mask         */
+#define SCT_OUTPUTSET15_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET15: SETn3 Position     */
+#define SCT_OUTPUTSET15_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn3_Pos)                     /*!< SCT OUTPUTSET15: SETn3 Mask         */
+#define SCT_OUTPUTSET15_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET15: SETn4 Position     */
+#define SCT_OUTPUTSET15_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn4_Pos)                     /*!< SCT OUTPUTSET15: SETn4 Mask         */
+#define SCT_OUTPUTSET15_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET15: SETn5 Position     */
+#define SCT_OUTPUTSET15_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn5_Pos)                     /*!< SCT OUTPUTSET15: SETn5 Mask         */
+#define SCT_OUTPUTSET15_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET15: SETn6 Position     */
+#define SCT_OUTPUTSET15_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn6_Pos)                     /*!< SCT OUTPUTSET15: SETn6 Mask         */
+#define SCT_OUTPUTSET15_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET15: SETn7 Position     */
+#define SCT_OUTPUTSET15_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn7_Pos)                     /*!< SCT OUTPUTSET15: SETn7 Mask         */
+#define SCT_OUTPUTSET15_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET15: SETn8 Position     */
+#define SCT_OUTPUTSET15_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn8_Pos)                     /*!< SCT OUTPUTSET15: SETn8 Mask         */
+#define SCT_OUTPUTSET15_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET15: SETn9 Position     */
+#define SCT_OUTPUTSET15_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn9_Pos)                     /*!< SCT OUTPUTSET15: SETn9 Mask         */
+#define SCT_OUTPUTSET15_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET15: SETn10 Position    */
+#define SCT_OUTPUTSET15_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn10_Pos)                    /*!< SCT OUTPUTSET15: SETn10 Mask        */
+#define SCT_OUTPUTSET15_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET15: SETn11 Position    */
+#define SCT_OUTPUTSET15_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn11_Pos)                    /*!< SCT OUTPUTSET15: SETn11 Mask        */
+#define SCT_OUTPUTSET15_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET15: SETn12 Position    */
+#define SCT_OUTPUTSET15_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn12_Pos)                    /*!< SCT OUTPUTSET15: SETn12 Mask        */
+#define SCT_OUTPUTSET15_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET15: SETn13 Position    */
+#define SCT_OUTPUTSET15_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn13_Pos)                    /*!< SCT OUTPUTSET15: SETn13 Mask        */
+#define SCT_OUTPUTSET15_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET15: SETn14 Position    */
+#define SCT_OUTPUTSET15_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn14_Pos)                    /*!< SCT OUTPUTSET15: SETn14 Mask        */
+#define SCT_OUTPUTSET15_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET15: SETn15 Position    */
+#define SCT_OUTPUTSET15_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn15_Pos)                    /*!< SCT OUTPUTSET15: SETn15 Mask        */
+
+// -------------------------------------  SCT_OUTPUTCLR15  ----------------------------------------
+#define SCT_OUTPUTCLR15_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR15: CLRn0 Position     */
+#define SCT_OUTPUTCLR15_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos)                     /*!< SCT OUTPUTCLR15: CLRn0 Mask         */
+#define SCT_OUTPUTCLR15_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR15: CLRn1 Position     */
+#define SCT_OUTPUTCLR15_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos)                     /*!< SCT OUTPUTCLR15: CLRn1 Mask         */
+#define SCT_OUTPUTCLR15_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR15: CLRn2 Position     */
+#define SCT_OUTPUTCLR15_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos)                     /*!< SCT OUTPUTCLR15: CLRn2 Mask         */
+#define SCT_OUTPUTCLR15_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR15: CLRn3 Position     */
+#define SCT_OUTPUTCLR15_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos)                     /*!< SCT OUTPUTCLR15: CLRn3 Mask         */
+#define SCT_OUTPUTCLR15_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR15: CLRn4 Position     */
+#define SCT_OUTPUTCLR15_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos)                     /*!< SCT OUTPUTCLR15: CLRn4 Mask         */
+#define SCT_OUTPUTCLR15_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR15: CLRn5 Position     */
+#define SCT_OUTPUTCLR15_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos)                     /*!< SCT OUTPUTCLR15: CLRn5 Mask         */
+#define SCT_OUTPUTCLR15_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR15: CLRn6 Position     */
+#define SCT_OUTPUTCLR15_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos)                     /*!< SCT OUTPUTCLR15: CLRn6 Mask         */
+#define SCT_OUTPUTCLR15_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR15: CLRn7 Position     */
+#define SCT_OUTPUTCLR15_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos)                     /*!< SCT OUTPUTCLR15: CLRn7 Mask         */
+#define SCT_OUTPUTCLR15_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR15: CLRn8 Position     */
+#define SCT_OUTPUTCLR15_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos)                     /*!< SCT OUTPUTCLR15: CLRn8 Mask         */
+#define SCT_OUTPUTCLR15_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR15: CLRn9 Position     */
+#define SCT_OUTPUTCLR15_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos)                     /*!< SCT OUTPUTCLR15: CLRn9 Mask         */
+#define SCT_OUTPUTCLR15_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR15: CLRn10 Position    */
+#define SCT_OUTPUTCLR15_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos)                    /*!< SCT OUTPUTCLR15: CLRn10 Mask        */
+#define SCT_OUTPUTCLR15_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR15: CLRn11 Position    */
+#define SCT_OUTPUTCLR15_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos)                    /*!< SCT OUTPUTCLR15: CLRn11 Mask        */
+#define SCT_OUTPUTCLR15_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR15: CLRn12 Position    */
+#define SCT_OUTPUTCLR15_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos)                    /*!< SCT OUTPUTCLR15: CLRn12 Mask        */
+#define SCT_OUTPUTCLR15_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR15: CLRn13 Position    */
+#define SCT_OUTPUTCLR15_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos)                    /*!< SCT OUTPUTCLR15: CLRn13 Mask        */
+#define SCT_OUTPUTCLR15_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR15: CLRn14 Position    */
+#define SCT_OUTPUTCLR15_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos)                    /*!< SCT OUTPUTCLR15: CLRn14 Mask        */
+#define SCT_OUTPUTCLR15_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR15: CLRn15 Position    */
+#define SCT_OUTPUTCLR15_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos)                    /*!< SCT OUTPUTCLR15: CLRn15 Mask        */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 GPDMA Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------  GPDMA_INTSTAT  -----------------------------------------
+#define GPDMA_INTSTAT_INTSTAT0_Pos                            0                                                         /*!< GPDMA INTSTAT: INTSTAT0 Position    */
+#define GPDMA_INTSTAT_INTSTAT0_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos)                    /*!< GPDMA INTSTAT: INTSTAT0 Mask        */
+#define GPDMA_INTSTAT_INTSTAT1_Pos                            1                                                         /*!< GPDMA INTSTAT: INTSTAT1 Position    */
+#define GPDMA_INTSTAT_INTSTAT1_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos)                    /*!< GPDMA INTSTAT: INTSTAT1 Mask        */
+#define GPDMA_INTSTAT_INTSTAT2_Pos                            2                                                         /*!< GPDMA INTSTAT: INTSTAT2 Position    */
+#define GPDMA_INTSTAT_INTSTAT2_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos)                    /*!< GPDMA INTSTAT: INTSTAT2 Mask        */
+#define GPDMA_INTSTAT_INTSTAT3_Pos                            3                                                         /*!< GPDMA INTSTAT: INTSTAT3 Position    */
+#define GPDMA_INTSTAT_INTSTAT3_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos)                    /*!< GPDMA INTSTAT: INTSTAT3 Mask        */
+#define GPDMA_INTSTAT_INTSTAT4_Pos                            4                                                         /*!< GPDMA INTSTAT: INTSTAT4 Position    */
+#define GPDMA_INTSTAT_INTSTAT4_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos)                    /*!< GPDMA INTSTAT: INTSTAT4 Mask        */
+#define GPDMA_INTSTAT_INTSTAT5_Pos                            5                                                         /*!< GPDMA INTSTAT: INTSTAT5 Position    */
+#define GPDMA_INTSTAT_INTSTAT5_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos)                    /*!< GPDMA INTSTAT: INTSTAT5 Mask        */
+#define GPDMA_INTSTAT_INTSTAT6_Pos                            6                                                         /*!< GPDMA INTSTAT: INTSTAT6 Position    */
+#define GPDMA_INTSTAT_INTSTAT6_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos)                    /*!< GPDMA INTSTAT: INTSTAT6 Mask        */
+#define GPDMA_INTSTAT_INTSTAT7_Pos                            7                                                         /*!< GPDMA INTSTAT: INTSTAT7 Position    */
+#define GPDMA_INTSTAT_INTSTAT7_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos)                    /*!< GPDMA INTSTAT: INTSTAT7 Mask        */
+
+// -------------------------------------  GPDMA_INTTCSTAT  ----------------------------------------
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos                        0                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos                        1                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos                        2                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos                        3                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos                        4                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos                        5                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos                        6                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask    */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos                        7                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask    */
+
+// ------------------------------------  GPDMA_INTTCCLEAR  ----------------------------------------
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos                      0                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos                      1                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos                      2                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos                      3                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos                      4                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos                      5                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos                      6                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask  */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos                      7                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask  */
+
+// ------------------------------------  GPDMA_INTERRSTAT  ----------------------------------------
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos                      0                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos                      1                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos                      2                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos                      3                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos                      4                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos                      5                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos                      6                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask  */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos                      7                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask  */
+
+// -------------------------------------  GPDMA_INTERRCLR  ----------------------------------------
+#define GPDMA_INTERRCLR_INTERRCLR0_Pos                        0                                                         /*!< GPDMA INTERRCLR: INTERRCLR0 Position */
+#define GPDMA_INTERRCLR_INTERRCLR0_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR0 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR1_Pos                        1                                                         /*!< GPDMA INTERRCLR: INTERRCLR1 Position */
+#define GPDMA_INTERRCLR_INTERRCLR1_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR1 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR2_Pos                        2                                                         /*!< GPDMA INTERRCLR: INTERRCLR2 Position */
+#define GPDMA_INTERRCLR_INTERRCLR2_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR2 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR3_Pos                        3                                                         /*!< GPDMA INTERRCLR: INTERRCLR3 Position */
+#define GPDMA_INTERRCLR_INTERRCLR3_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR3 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR4_Pos                        4                                                         /*!< GPDMA INTERRCLR: INTERRCLR4 Position */
+#define GPDMA_INTERRCLR_INTERRCLR4_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR4 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR5_Pos                        5                                                         /*!< GPDMA INTERRCLR: INTERRCLR5 Position */
+#define GPDMA_INTERRCLR_INTERRCLR5_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR5 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR6_Pos                        6                                                         /*!< GPDMA INTERRCLR: INTERRCLR6 Position */
+#define GPDMA_INTERRCLR_INTERRCLR6_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR6 Mask    */
+#define GPDMA_INTERRCLR_INTERRCLR7_Pos                        7                                                         /*!< GPDMA INTERRCLR: INTERRCLR7 Position */
+#define GPDMA_INTERRCLR_INTERRCLR7_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR7 Mask    */
+
+// -----------------------------------  GPDMA_RAWINTTCSTAT  ---------------------------------------
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos                  0                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos                  1                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos                  2                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos                  3                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos                  4                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos                  5                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos                  6                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos                  7                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */
+
+// -----------------------------------  GPDMA_RAWINTERRSTAT  --------------------------------------
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos                0                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos                1                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos                2                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos                3                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos                4                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos                5                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos                6                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos                7                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */
+
+// -------------------------------------  GPDMA_ENBLDCHNS  ----------------------------------------
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos                  0                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos                  1                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos                  2                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos                  3                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos                  4                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos                  5                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos                  6                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos                  7                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */
+
+// -------------------------------------  GPDMA_SOFTBREQ  -----------------------------------------
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos                          0                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos                          1                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos                          2                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos                          3                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos                          4                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos                          5                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos                          6                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos                          7                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos                          8                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos                          9                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position  */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask      */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos                         10                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos                         11                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos                         12                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos                         13                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos                         14                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask     */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos                         15                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask     */
+
+// -------------------------------------  GPDMA_SOFTSREQ  -----------------------------------------
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos                          0                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos                          1                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos                          2                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos                          3                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos                          4                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos                          5                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos                          6                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos                          7                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos                          8                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos                          9                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position  */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask      */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos                         10                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos                         11                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos                         12                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos                         13                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos                         14                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask     */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos                         15                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask     */
+
+// -------------------------------------  GPDMA_SOFTLBREQ  ----------------------------------------
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos                        0                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos                        1                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos                        2                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos                        3                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos                        4                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos                        5                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos                        6                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos                        7                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos                        8                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos                        9                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask    */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos                       10                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos                       11                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos                       12                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos                       13                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos                       14                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask   */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos                       15                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask   */
+
+// -------------------------------------  GPDMA_SOFTLSREQ  ----------------------------------------
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos                        0                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos                        1                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos                        2                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos                        3                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos                        4                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos                        5                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos                        6                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos                        7                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos                        8                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos                        9                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask    */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos                       10                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos                       11                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos                       12                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos                       13                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos                       14                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask   */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos                       15                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask   */
+
+// --------------------------------------  GPDMA_CONFIG  ------------------------------------------
+#define GPDMA_CONFIG_E_Pos                                    0                                                         /*!< GPDMA CONFIG: E Position            */
+#define GPDMA_CONFIG_E_Msk                                    (0x01UL << GPDMA_CONFIG_E_Pos)                            /*!< GPDMA CONFIG: E Mask                */
+#define GPDMA_CONFIG_M0_Pos                                   1                                                         /*!< GPDMA CONFIG: M0 Position           */
+#define GPDMA_CONFIG_M0_Msk                                   (0x01UL << GPDMA_CONFIG_M0_Pos)                           /*!< GPDMA CONFIG: M0 Mask               */
+#define GPDMA_CONFIG_M1_Pos                                   2                                                         /*!< GPDMA CONFIG: M1 Position           */
+#define GPDMA_CONFIG_M1_Msk                                   (0x01UL << GPDMA_CONFIG_M1_Pos)                           /*!< GPDMA CONFIG: M1 Mask               */
+
+// ---------------------------------------  GPDMA_SYNC  -------------------------------------------
+#define GPDMA_SYNC_DMACSYNC0_Pos                              0                                                         /*!< GPDMA SYNC: DMACSYNC0 Position      */
+#define GPDMA_SYNC_DMACSYNC0_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos)                      /*!< GPDMA SYNC: DMACSYNC0 Mask          */
+#define GPDMA_SYNC_DMACSYNC1_Pos                              1                                                         /*!< GPDMA SYNC: DMACSYNC1 Position      */
+#define GPDMA_SYNC_DMACSYNC1_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos)                      /*!< GPDMA SYNC: DMACSYNC1 Mask          */
+#define GPDMA_SYNC_DMACSYNC2_Pos                              2                                                         /*!< GPDMA SYNC: DMACSYNC2 Position      */
+#define GPDMA_SYNC_DMACSYNC2_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos)                      /*!< GPDMA SYNC: DMACSYNC2 Mask          */
+#define GPDMA_SYNC_DMACSYNC3_Pos                              3                                                         /*!< GPDMA SYNC: DMACSYNC3 Position      */
+#define GPDMA_SYNC_DMACSYNC3_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos)                      /*!< GPDMA SYNC: DMACSYNC3 Mask          */
+#define GPDMA_SYNC_DMACSYNC4_Pos                              4                                                         /*!< GPDMA SYNC: DMACSYNC4 Position      */
+#define GPDMA_SYNC_DMACSYNC4_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos)                      /*!< GPDMA SYNC: DMACSYNC4 Mask          */
+#define GPDMA_SYNC_DMACSYNC5_Pos                              5                                                         /*!< GPDMA SYNC: DMACSYNC5 Position      */
+#define GPDMA_SYNC_DMACSYNC5_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos)                      /*!< GPDMA SYNC: DMACSYNC5 Mask          */
+#define GPDMA_SYNC_DMACSYNC6_Pos                              6                                                         /*!< GPDMA SYNC: DMACSYNC6 Position      */
+#define GPDMA_SYNC_DMACSYNC6_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos)                      /*!< GPDMA SYNC: DMACSYNC6 Mask          */
+#define GPDMA_SYNC_DMACSYNC7_Pos                              7                                                         /*!< GPDMA SYNC: DMACSYNC7 Position      */
+#define GPDMA_SYNC_DMACSYNC7_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos)                      /*!< GPDMA SYNC: DMACSYNC7 Mask          */
+#define GPDMA_SYNC_DMACSYNC8_Pos                              8                                                         /*!< GPDMA SYNC: DMACSYNC8 Position      */
+#define GPDMA_SYNC_DMACSYNC8_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos)                      /*!< GPDMA SYNC: DMACSYNC8 Mask          */
+#define GPDMA_SYNC_DMACSYNC9_Pos                              9                                                         /*!< GPDMA SYNC: DMACSYNC9 Position      */
+#define GPDMA_SYNC_DMACSYNC9_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos)                      /*!< GPDMA SYNC: DMACSYNC9 Mask          */
+#define GPDMA_SYNC_DMACSYNC10_Pos                             10                                                        /*!< GPDMA SYNC: DMACSYNC10 Position     */
+#define GPDMA_SYNC_DMACSYNC10_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos)                     /*!< GPDMA SYNC: DMACSYNC10 Mask         */
+#define GPDMA_SYNC_DMACSYNC11_Pos                             11                                                        /*!< GPDMA SYNC: DMACSYNC11 Position     */
+#define GPDMA_SYNC_DMACSYNC11_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos)                     /*!< GPDMA SYNC: DMACSYNC11 Mask         */
+#define GPDMA_SYNC_DMACSYNC12_Pos                             12                                                        /*!< GPDMA SYNC: DMACSYNC12 Position     */
+#define GPDMA_SYNC_DMACSYNC12_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos)                     /*!< GPDMA SYNC: DMACSYNC12 Mask         */
+#define GPDMA_SYNC_DMACSYNC13_Pos                             13                                                        /*!< GPDMA SYNC: DMACSYNC13 Position     */
+#define GPDMA_SYNC_DMACSYNC13_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos)                     /*!< GPDMA SYNC: DMACSYNC13 Mask         */
+#define GPDMA_SYNC_DMACSYNC14_Pos                             14                                                        /*!< GPDMA SYNC: DMACSYNC14 Position     */
+#define GPDMA_SYNC_DMACSYNC14_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos)                     /*!< GPDMA SYNC: DMACSYNC14 Mask         */
+#define GPDMA_SYNC_DMACSYNC15_Pos                             15                                                        /*!< GPDMA SYNC: DMACSYNC15 Position     */
+#define GPDMA_SYNC_DMACSYNC15_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos)                     /*!< GPDMA SYNC: DMACSYNC15 Mask         */
+
+// -------------------------------------  GPDMA_C0SRCADDR  ----------------------------------------
+#define GPDMA_C0SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C0SRCADDR: SRCADDR Position   */
+#define GPDMA_C0SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos)             /*!< GPDMA C0SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C0DESTADDR  ----------------------------------------
+#define GPDMA_C0DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C0DESTADDR: DESTADDR Position */
+#define GPDMA_C0DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos)           /*!< GPDMA C0DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C0LLI  ------------------------------------------
+#define GPDMA_C0LLI_LM_Pos                                    0                                                         /*!< GPDMA C0LLI: LM Position            */
+#define GPDMA_C0LLI_LM_Msk                                    (0x01UL << GPDMA_C0LLI_LM_Pos)                            /*!< GPDMA C0LLI: LM Mask                */
+#define GPDMA_C0LLI_R_Pos                                     1                                                         /*!< GPDMA C0LLI: R Position             */
+#define GPDMA_C0LLI_R_Msk                                     (0x01UL << GPDMA_C0LLI_R_Pos)                             /*!< GPDMA C0LLI: R Mask                 */
+#define GPDMA_C0LLI_LLI_Pos                                   2                                                         /*!< GPDMA C0LLI: LLI Position           */
+#define GPDMA_C0LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos)                     /*!< GPDMA C0LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C0CONTROL  ----------------------------------------
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C0CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C0CONTROL: SBSIZE Position    */
+#define GPDMA_C0CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos)                    /*!< GPDMA C0CONTROL: SBSIZE Mask        */
+#define GPDMA_C0CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C0CONTROL: DBSIZE Position    */
+#define GPDMA_C0CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos)                    /*!< GPDMA C0CONTROL: DBSIZE Mask        */
+#define GPDMA_C0CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C0CONTROL: SWIDTH Position    */
+#define GPDMA_C0CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos)                    /*!< GPDMA C0CONTROL: SWIDTH Mask        */
+#define GPDMA_C0CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C0CONTROL: DWIDTH Position    */
+#define GPDMA_C0CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos)                    /*!< GPDMA C0CONTROL: DWIDTH Mask        */
+#define GPDMA_C0CONTROL_S_Pos                                 24                                                        /*!< GPDMA C0CONTROL: S Position         */
+#define GPDMA_C0CONTROL_S_Msk                                 (0x01UL << GPDMA_C0CONTROL_S_Pos)                         /*!< GPDMA C0CONTROL: S Mask             */
+#define GPDMA_C0CONTROL_D_Pos                                 25                                                        /*!< GPDMA C0CONTROL: D Position         */
+#define GPDMA_C0CONTROL_D_Msk                                 (0x01UL << GPDMA_C0CONTROL_D_Pos)                         /*!< GPDMA C0CONTROL: D Mask             */
+#define GPDMA_C0CONTROL_SI_Pos                                26                                                        /*!< GPDMA C0CONTROL: SI Position        */
+#define GPDMA_C0CONTROL_SI_Msk                                (0x01UL << GPDMA_C0CONTROL_SI_Pos)                        /*!< GPDMA C0CONTROL: SI Mask            */
+#define GPDMA_C0CONTROL_DI_Pos                                27                                                        /*!< GPDMA C0CONTROL: DI Position        */
+#define GPDMA_C0CONTROL_DI_Msk                                (0x01UL << GPDMA_C0CONTROL_DI_Pos)                        /*!< GPDMA C0CONTROL: DI Mask            */
+#define GPDMA_C0CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C0CONTROL: PROT1 Position     */
+#define GPDMA_C0CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT1_Pos)                     /*!< GPDMA C0CONTROL: PROT1 Mask         */
+#define GPDMA_C0CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C0CONTROL: PROT2 Position     */
+#define GPDMA_C0CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT2_Pos)                     /*!< GPDMA C0CONTROL: PROT2 Mask         */
+#define GPDMA_C0CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C0CONTROL: PROT3 Position     */
+#define GPDMA_C0CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT3_Pos)                     /*!< GPDMA C0CONTROL: PROT3 Mask         */
+#define GPDMA_C0CONTROL_I_Pos                                 31                                                        /*!< GPDMA C0CONTROL: I Position         */
+#define GPDMA_C0CONTROL_I_Msk                                 (0x01UL << GPDMA_C0CONTROL_I_Pos)                         /*!< GPDMA C0CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C0CONFIG  -----------------------------------------
+#define GPDMA_C0CONFIG_E_Pos                                  0                                                         /*!< GPDMA C0CONFIG: E Position          */
+#define GPDMA_C0CONFIG_E_Msk                                  (0x01UL << GPDMA_C0CONFIG_E_Pos)                          /*!< GPDMA C0CONFIG: E Mask              */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C0CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C0CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C0CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C0CONFIG: IE Position         */
+#define GPDMA_C0CONFIG_IE_Msk                                 (0x01UL << GPDMA_C0CONFIG_IE_Pos)                         /*!< GPDMA C0CONFIG: IE Mask             */
+#define GPDMA_C0CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C0CONFIG: ITC Position        */
+#define GPDMA_C0CONFIG_ITC_Msk                                (0x01UL << GPDMA_C0CONFIG_ITC_Pos)                        /*!< GPDMA C0CONFIG: ITC Mask            */
+#define GPDMA_C0CONFIG_L_Pos                                  16                                                        /*!< GPDMA C0CONFIG: L Position          */
+#define GPDMA_C0CONFIG_L_Msk                                  (0x01UL << GPDMA_C0CONFIG_L_Pos)                          /*!< GPDMA C0CONFIG: L Mask              */
+#define GPDMA_C0CONFIG_A_Pos                                  17                                                        /*!< GPDMA C0CONFIG: A Position          */
+#define GPDMA_C0CONFIG_A_Msk                                  (0x01UL << GPDMA_C0CONFIG_A_Pos)                          /*!< GPDMA C0CONFIG: A Mask              */
+#define GPDMA_C0CONFIG_H_Pos                                  18                                                        /*!< GPDMA C0CONFIG: H Position          */
+#define GPDMA_C0CONFIG_H_Msk                                  (0x01UL << GPDMA_C0CONFIG_H_Pos)                          /*!< GPDMA C0CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C1SRCADDR  ----------------------------------------
+#define GPDMA_C1SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C1SRCADDR: SRCADDR Position   */
+#define GPDMA_C1SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos)             /*!< GPDMA C1SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C1DESTADDR  ----------------------------------------
+#define GPDMA_C1DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C1DESTADDR: DESTADDR Position */
+#define GPDMA_C1DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos)           /*!< GPDMA C1DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C1LLI  ------------------------------------------
+#define GPDMA_C1LLI_LM_Pos                                    0                                                         /*!< GPDMA C1LLI: LM Position            */
+#define GPDMA_C1LLI_LM_Msk                                    (0x01UL << GPDMA_C1LLI_LM_Pos)                            /*!< GPDMA C1LLI: LM Mask                */
+#define GPDMA_C1LLI_R_Pos                                     1                                                         /*!< GPDMA C1LLI: R Position             */
+#define GPDMA_C1LLI_R_Msk                                     (0x01UL << GPDMA_C1LLI_R_Pos)                             /*!< GPDMA C1LLI: R Mask                 */
+#define GPDMA_C1LLI_LLI_Pos                                   2                                                         /*!< GPDMA C1LLI: LLI Position           */
+#define GPDMA_C1LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos)                     /*!< GPDMA C1LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C1CONTROL  ----------------------------------------
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C1CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C1CONTROL: SBSIZE Position    */
+#define GPDMA_C1CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos)                    /*!< GPDMA C1CONTROL: SBSIZE Mask        */
+#define GPDMA_C1CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C1CONTROL: DBSIZE Position    */
+#define GPDMA_C1CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos)                    /*!< GPDMA C1CONTROL: DBSIZE Mask        */
+#define GPDMA_C1CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C1CONTROL: SWIDTH Position    */
+#define GPDMA_C1CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos)                    /*!< GPDMA C1CONTROL: SWIDTH Mask        */
+#define GPDMA_C1CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C1CONTROL: DWIDTH Position    */
+#define GPDMA_C1CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos)                    /*!< GPDMA C1CONTROL: DWIDTH Mask        */
+#define GPDMA_C1CONTROL_S_Pos                                 24                                                        /*!< GPDMA C1CONTROL: S Position         */
+#define GPDMA_C1CONTROL_S_Msk                                 (0x01UL << GPDMA_C1CONTROL_S_Pos)                         /*!< GPDMA C1CONTROL: S Mask             */
+#define GPDMA_C1CONTROL_D_Pos                                 25                                                        /*!< GPDMA C1CONTROL: D Position         */
+#define GPDMA_C1CONTROL_D_Msk                                 (0x01UL << GPDMA_C1CONTROL_D_Pos)                         /*!< GPDMA C1CONTROL: D Mask             */
+#define GPDMA_C1CONTROL_SI_Pos                                26                                                        /*!< GPDMA C1CONTROL: SI Position        */
+#define GPDMA_C1CONTROL_SI_Msk                                (0x01UL << GPDMA_C1CONTROL_SI_Pos)                        /*!< GPDMA C1CONTROL: SI Mask            */
+#define GPDMA_C1CONTROL_DI_Pos                                27                                                        /*!< GPDMA C1CONTROL: DI Position        */
+#define GPDMA_C1CONTROL_DI_Msk                                (0x01UL << GPDMA_C1CONTROL_DI_Pos)                        /*!< GPDMA C1CONTROL: DI Mask            */
+#define GPDMA_C1CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C1CONTROL: PROT1 Position     */
+#define GPDMA_C1CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT1_Pos)                     /*!< GPDMA C1CONTROL: PROT1 Mask         */
+#define GPDMA_C1CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C1CONTROL: PROT2 Position     */
+#define GPDMA_C1CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT2_Pos)                     /*!< GPDMA C1CONTROL: PROT2 Mask         */
+#define GPDMA_C1CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C1CONTROL: PROT3 Position     */
+#define GPDMA_C1CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT3_Pos)                     /*!< GPDMA C1CONTROL: PROT3 Mask         */
+#define GPDMA_C1CONTROL_I_Pos                                 31                                                        /*!< GPDMA C1CONTROL: I Position         */
+#define GPDMA_C1CONTROL_I_Msk                                 (0x01UL << GPDMA_C1CONTROL_I_Pos)                         /*!< GPDMA C1CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C1CONFIG  -----------------------------------------
+#define GPDMA_C1CONFIG_E_Pos                                  0                                                         /*!< GPDMA C1CONFIG: E Position          */
+#define GPDMA_C1CONFIG_E_Msk                                  (0x01UL << GPDMA_C1CONFIG_E_Pos)                          /*!< GPDMA C1CONFIG: E Mask              */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C1CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C1CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C1CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C1CONFIG: IE Position         */
+#define GPDMA_C1CONFIG_IE_Msk                                 (0x01UL << GPDMA_C1CONFIG_IE_Pos)                         /*!< GPDMA C1CONFIG: IE Mask             */
+#define GPDMA_C1CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C1CONFIG: ITC Position        */
+#define GPDMA_C1CONFIG_ITC_Msk                                (0x01UL << GPDMA_C1CONFIG_ITC_Pos)                        /*!< GPDMA C1CONFIG: ITC Mask            */
+#define GPDMA_C1CONFIG_L_Pos                                  16                                                        /*!< GPDMA C1CONFIG: L Position          */
+#define GPDMA_C1CONFIG_L_Msk                                  (0x01UL << GPDMA_C1CONFIG_L_Pos)                          /*!< GPDMA C1CONFIG: L Mask              */
+#define GPDMA_C1CONFIG_A_Pos                                  17                                                        /*!< GPDMA C1CONFIG: A Position          */
+#define GPDMA_C1CONFIG_A_Msk                                  (0x01UL << GPDMA_C1CONFIG_A_Pos)                          /*!< GPDMA C1CONFIG: A Mask              */
+#define GPDMA_C1CONFIG_H_Pos                                  18                                                        /*!< GPDMA C1CONFIG: H Position          */
+#define GPDMA_C1CONFIG_H_Msk                                  (0x01UL << GPDMA_C1CONFIG_H_Pos)                          /*!< GPDMA C1CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C2SRCADDR  ----------------------------------------
+#define GPDMA_C2SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C2SRCADDR: SRCADDR Position   */
+#define GPDMA_C2SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos)             /*!< GPDMA C2SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C2DESTADDR  ----------------------------------------
+#define GPDMA_C2DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C2DESTADDR: DESTADDR Position */
+#define GPDMA_C2DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos)           /*!< GPDMA C2DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C2LLI  ------------------------------------------
+#define GPDMA_C2LLI_LM_Pos                                    0                                                         /*!< GPDMA C2LLI: LM Position            */
+#define GPDMA_C2LLI_LM_Msk                                    (0x01UL << GPDMA_C2LLI_LM_Pos)                            /*!< GPDMA C2LLI: LM Mask                */
+#define GPDMA_C2LLI_R_Pos                                     1                                                         /*!< GPDMA C2LLI: R Position             */
+#define GPDMA_C2LLI_R_Msk                                     (0x01UL << GPDMA_C2LLI_R_Pos)                             /*!< GPDMA C2LLI: R Mask                 */
+#define GPDMA_C2LLI_LLI_Pos                                   2                                                         /*!< GPDMA C2LLI: LLI Position           */
+#define GPDMA_C2LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos)                     /*!< GPDMA C2LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C2CONTROL  ----------------------------------------
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C2CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C2CONTROL: SBSIZE Position    */
+#define GPDMA_C2CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos)                    /*!< GPDMA C2CONTROL: SBSIZE Mask        */
+#define GPDMA_C2CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C2CONTROL: DBSIZE Position    */
+#define GPDMA_C2CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos)                    /*!< GPDMA C2CONTROL: DBSIZE Mask        */
+#define GPDMA_C2CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C2CONTROL: SWIDTH Position    */
+#define GPDMA_C2CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos)                    /*!< GPDMA C2CONTROL: SWIDTH Mask        */
+#define GPDMA_C2CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C2CONTROL: DWIDTH Position    */
+#define GPDMA_C2CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos)                    /*!< GPDMA C2CONTROL: DWIDTH Mask        */
+#define GPDMA_C2CONTROL_S_Pos                                 24                                                        /*!< GPDMA C2CONTROL: S Position         */
+#define GPDMA_C2CONTROL_S_Msk                                 (0x01UL << GPDMA_C2CONTROL_S_Pos)                         /*!< GPDMA C2CONTROL: S Mask             */
+#define GPDMA_C2CONTROL_D_Pos                                 25                                                        /*!< GPDMA C2CONTROL: D Position         */
+#define GPDMA_C2CONTROL_D_Msk                                 (0x01UL << GPDMA_C2CONTROL_D_Pos)                         /*!< GPDMA C2CONTROL: D Mask             */
+#define GPDMA_C2CONTROL_SI_Pos                                26                                                        /*!< GPDMA C2CONTROL: SI Position        */
+#define GPDMA_C2CONTROL_SI_Msk                                (0x01UL << GPDMA_C2CONTROL_SI_Pos)                        /*!< GPDMA C2CONTROL: SI Mask            */
+#define GPDMA_C2CONTROL_DI_Pos                                27                                                        /*!< GPDMA C2CONTROL: DI Position        */
+#define GPDMA_C2CONTROL_DI_Msk                                (0x01UL << GPDMA_C2CONTROL_DI_Pos)                        /*!< GPDMA C2CONTROL: DI Mask            */
+#define GPDMA_C2CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C2CONTROL: PROT1 Position     */
+#define GPDMA_C2CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT1_Pos)                     /*!< GPDMA C2CONTROL: PROT1 Mask         */
+#define GPDMA_C2CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C2CONTROL: PROT2 Position     */
+#define GPDMA_C2CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT2_Pos)                     /*!< GPDMA C2CONTROL: PROT2 Mask         */
+#define GPDMA_C2CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C2CONTROL: PROT3 Position     */
+#define GPDMA_C2CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT3_Pos)                     /*!< GPDMA C2CONTROL: PROT3 Mask         */
+#define GPDMA_C2CONTROL_I_Pos                                 31                                                        /*!< GPDMA C2CONTROL: I Position         */
+#define GPDMA_C2CONTROL_I_Msk                                 (0x01UL << GPDMA_C2CONTROL_I_Pos)                         /*!< GPDMA C2CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C2CONFIG  -----------------------------------------
+#define GPDMA_C2CONFIG_E_Pos                                  0                                                         /*!< GPDMA C2CONFIG: E Position          */
+#define GPDMA_C2CONFIG_E_Msk                                  (0x01UL << GPDMA_C2CONFIG_E_Pos)                          /*!< GPDMA C2CONFIG: E Mask              */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C2CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C2CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C2CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C2CONFIG: IE Position         */
+#define GPDMA_C2CONFIG_IE_Msk                                 (0x01UL << GPDMA_C2CONFIG_IE_Pos)                         /*!< GPDMA C2CONFIG: IE Mask             */
+#define GPDMA_C2CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C2CONFIG: ITC Position        */
+#define GPDMA_C2CONFIG_ITC_Msk                                (0x01UL << GPDMA_C2CONFIG_ITC_Pos)                        /*!< GPDMA C2CONFIG: ITC Mask            */
+#define GPDMA_C2CONFIG_L_Pos                                  16                                                        /*!< GPDMA C2CONFIG: L Position          */
+#define GPDMA_C2CONFIG_L_Msk                                  (0x01UL << GPDMA_C2CONFIG_L_Pos)                          /*!< GPDMA C2CONFIG: L Mask              */
+#define GPDMA_C2CONFIG_A_Pos                                  17                                                        /*!< GPDMA C2CONFIG: A Position          */
+#define GPDMA_C2CONFIG_A_Msk                                  (0x01UL << GPDMA_C2CONFIG_A_Pos)                          /*!< GPDMA C2CONFIG: A Mask              */
+#define GPDMA_C2CONFIG_H_Pos                                  18                                                        /*!< GPDMA C2CONFIG: H Position          */
+#define GPDMA_C2CONFIG_H_Msk                                  (0x01UL << GPDMA_C2CONFIG_H_Pos)                          /*!< GPDMA C2CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C3SRCADDR  ----------------------------------------
+#define GPDMA_C3SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C3SRCADDR: SRCADDR Position   */
+#define GPDMA_C3SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos)             /*!< GPDMA C3SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C3DESTADDR  ----------------------------------------
+#define GPDMA_C3DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C3DESTADDR: DESTADDR Position */
+#define GPDMA_C3DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos)           /*!< GPDMA C3DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C3LLI  ------------------------------------------
+#define GPDMA_C3LLI_LM_Pos                                    0                                                         /*!< GPDMA C3LLI: LM Position            */
+#define GPDMA_C3LLI_LM_Msk                                    (0x01UL << GPDMA_C3LLI_LM_Pos)                            /*!< GPDMA C3LLI: LM Mask                */
+#define GPDMA_C3LLI_R_Pos                                     1                                                         /*!< GPDMA C3LLI: R Position             */
+#define GPDMA_C3LLI_R_Msk                                     (0x01UL << GPDMA_C3LLI_R_Pos)                             /*!< GPDMA C3LLI: R Mask                 */
+#define GPDMA_C3LLI_LLI_Pos                                   2                                                         /*!< GPDMA C3LLI: LLI Position           */
+#define GPDMA_C3LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos)                     /*!< GPDMA C3LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C3CONTROL  ----------------------------------------
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C3CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C3CONTROL: SBSIZE Position    */
+#define GPDMA_C3CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos)                    /*!< GPDMA C3CONTROL: SBSIZE Mask        */
+#define GPDMA_C3CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C3CONTROL: DBSIZE Position    */
+#define GPDMA_C3CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos)                    /*!< GPDMA C3CONTROL: DBSIZE Mask        */
+#define GPDMA_C3CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C3CONTROL: SWIDTH Position    */
+#define GPDMA_C3CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos)                    /*!< GPDMA C3CONTROL: SWIDTH Mask        */
+#define GPDMA_C3CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C3CONTROL: DWIDTH Position    */
+#define GPDMA_C3CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos)                    /*!< GPDMA C3CONTROL: DWIDTH Mask        */
+#define GPDMA_C3CONTROL_S_Pos                                 24                                                        /*!< GPDMA C3CONTROL: S Position         */
+#define GPDMA_C3CONTROL_S_Msk                                 (0x01UL << GPDMA_C3CONTROL_S_Pos)                         /*!< GPDMA C3CONTROL: S Mask             */
+#define GPDMA_C3CONTROL_D_Pos                                 25                                                        /*!< GPDMA C3CONTROL: D Position         */
+#define GPDMA_C3CONTROL_D_Msk                                 (0x01UL << GPDMA_C3CONTROL_D_Pos)                         /*!< GPDMA C3CONTROL: D Mask             */
+#define GPDMA_C3CONTROL_SI_Pos                                26                                                        /*!< GPDMA C3CONTROL: SI Position        */
+#define GPDMA_C3CONTROL_SI_Msk                                (0x01UL << GPDMA_C3CONTROL_SI_Pos)                        /*!< GPDMA C3CONTROL: SI Mask            */
+#define GPDMA_C3CONTROL_DI_Pos                                27                                                        /*!< GPDMA C3CONTROL: DI Position        */
+#define GPDMA_C3CONTROL_DI_Msk                                (0x01UL << GPDMA_C3CONTROL_DI_Pos)                        /*!< GPDMA C3CONTROL: DI Mask            */
+#define GPDMA_C3CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C3CONTROL: PROT1 Position     */
+#define GPDMA_C3CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT1_Pos)                     /*!< GPDMA C3CONTROL: PROT1 Mask         */
+#define GPDMA_C3CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C3CONTROL: PROT2 Position     */
+#define GPDMA_C3CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT2_Pos)                     /*!< GPDMA C3CONTROL: PROT2 Mask         */
+#define GPDMA_C3CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C3CONTROL: PROT3 Position     */
+#define GPDMA_C3CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT3_Pos)                     /*!< GPDMA C3CONTROL: PROT3 Mask         */
+#define GPDMA_C3CONTROL_I_Pos                                 31                                                        /*!< GPDMA C3CONTROL: I Position         */
+#define GPDMA_C3CONTROL_I_Msk                                 (0x01UL << GPDMA_C3CONTROL_I_Pos)                         /*!< GPDMA C3CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C3CONFIG  -----------------------------------------
+#define GPDMA_C3CONFIG_E_Pos                                  0                                                         /*!< GPDMA C3CONFIG: E Position          */
+#define GPDMA_C3CONFIG_E_Msk                                  (0x01UL << GPDMA_C3CONFIG_E_Pos)                          /*!< GPDMA C3CONFIG: E Mask              */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C3CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C3CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C3CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C3CONFIG: IE Position         */
+#define GPDMA_C3CONFIG_IE_Msk                                 (0x01UL << GPDMA_C3CONFIG_IE_Pos)                         /*!< GPDMA C3CONFIG: IE Mask             */
+#define GPDMA_C3CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C3CONFIG: ITC Position        */
+#define GPDMA_C3CONFIG_ITC_Msk                                (0x01UL << GPDMA_C3CONFIG_ITC_Pos)                        /*!< GPDMA C3CONFIG: ITC Mask            */
+#define GPDMA_C3CONFIG_L_Pos                                  16                                                        /*!< GPDMA C3CONFIG: L Position          */
+#define GPDMA_C3CONFIG_L_Msk                                  (0x01UL << GPDMA_C3CONFIG_L_Pos)                          /*!< GPDMA C3CONFIG: L Mask              */
+#define GPDMA_C3CONFIG_A_Pos                                  17                                                        /*!< GPDMA C3CONFIG: A Position          */
+#define GPDMA_C3CONFIG_A_Msk                                  (0x01UL << GPDMA_C3CONFIG_A_Pos)                          /*!< GPDMA C3CONFIG: A Mask              */
+#define GPDMA_C3CONFIG_H_Pos                                  18                                                        /*!< GPDMA C3CONFIG: H Position          */
+#define GPDMA_C3CONFIG_H_Msk                                  (0x01UL << GPDMA_C3CONFIG_H_Pos)                          /*!< GPDMA C3CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C4SRCADDR  ----------------------------------------
+#define GPDMA_C4SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C4SRCADDR: SRCADDR Position   */
+#define GPDMA_C4SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos)             /*!< GPDMA C4SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C4DESTADDR  ----------------------------------------
+#define GPDMA_C4DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C4DESTADDR: DESTADDR Position */
+#define GPDMA_C4DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos)           /*!< GPDMA C4DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C4LLI  ------------------------------------------
+#define GPDMA_C4LLI_LM_Pos                                    0                                                         /*!< GPDMA C4LLI: LM Position            */
+#define GPDMA_C4LLI_LM_Msk                                    (0x01UL << GPDMA_C4LLI_LM_Pos)                            /*!< GPDMA C4LLI: LM Mask                */
+#define GPDMA_C4LLI_R_Pos                                     1                                                         /*!< GPDMA C4LLI: R Position             */
+#define GPDMA_C4LLI_R_Msk                                     (0x01UL << GPDMA_C4LLI_R_Pos)                             /*!< GPDMA C4LLI: R Mask                 */
+#define GPDMA_C4LLI_LLI_Pos                                   2                                                         /*!< GPDMA C4LLI: LLI Position           */
+#define GPDMA_C4LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos)                     /*!< GPDMA C4LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C4CONTROL  ----------------------------------------
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C4CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C4CONTROL: SBSIZE Position    */
+#define GPDMA_C4CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos)                    /*!< GPDMA C4CONTROL: SBSIZE Mask        */
+#define GPDMA_C4CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C4CONTROL: DBSIZE Position    */
+#define GPDMA_C4CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos)                    /*!< GPDMA C4CONTROL: DBSIZE Mask        */
+#define GPDMA_C4CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C4CONTROL: SWIDTH Position    */
+#define GPDMA_C4CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos)                    /*!< GPDMA C4CONTROL: SWIDTH Mask        */
+#define GPDMA_C4CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C4CONTROL: DWIDTH Position    */
+#define GPDMA_C4CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos)                    /*!< GPDMA C4CONTROL: DWIDTH Mask        */
+#define GPDMA_C4CONTROL_S_Pos                                 24                                                        /*!< GPDMA C4CONTROL: S Position         */
+#define GPDMA_C4CONTROL_S_Msk                                 (0x01UL << GPDMA_C4CONTROL_S_Pos)                         /*!< GPDMA C4CONTROL: S Mask             */
+#define GPDMA_C4CONTROL_D_Pos                                 25                                                        /*!< GPDMA C4CONTROL: D Position         */
+#define GPDMA_C4CONTROL_D_Msk                                 (0x01UL << GPDMA_C4CONTROL_D_Pos)                         /*!< GPDMA C4CONTROL: D Mask             */
+#define GPDMA_C4CONTROL_SI_Pos                                26                                                        /*!< GPDMA C4CONTROL: SI Position        */
+#define GPDMA_C4CONTROL_SI_Msk                                (0x01UL << GPDMA_C4CONTROL_SI_Pos)                        /*!< GPDMA C4CONTROL: SI Mask            */
+#define GPDMA_C4CONTROL_DI_Pos                                27                                                        /*!< GPDMA C4CONTROL: DI Position        */
+#define GPDMA_C4CONTROL_DI_Msk                                (0x01UL << GPDMA_C4CONTROL_DI_Pos)                        /*!< GPDMA C4CONTROL: DI Mask            */
+#define GPDMA_C4CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C4CONTROL: PROT1 Position     */
+#define GPDMA_C4CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT1_Pos)                     /*!< GPDMA C4CONTROL: PROT1 Mask         */
+#define GPDMA_C4CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C4CONTROL: PROT2 Position     */
+#define GPDMA_C4CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT2_Pos)                     /*!< GPDMA C4CONTROL: PROT2 Mask         */
+#define GPDMA_C4CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C4CONTROL: PROT3 Position     */
+#define GPDMA_C4CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT3_Pos)                     /*!< GPDMA C4CONTROL: PROT3 Mask         */
+#define GPDMA_C4CONTROL_I_Pos                                 31                                                        /*!< GPDMA C4CONTROL: I Position         */
+#define GPDMA_C4CONTROL_I_Msk                                 (0x01UL << GPDMA_C4CONTROL_I_Pos)                         /*!< GPDMA C4CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C4CONFIG  -----------------------------------------
+#define GPDMA_C4CONFIG_E_Pos                                  0                                                         /*!< GPDMA C4CONFIG: E Position          */
+#define GPDMA_C4CONFIG_E_Msk                                  (0x01UL << GPDMA_C4CONFIG_E_Pos)                          /*!< GPDMA C4CONFIG: E Mask              */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C4CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C4CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C4CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C4CONFIG: IE Position         */
+#define GPDMA_C4CONFIG_IE_Msk                                 (0x01UL << GPDMA_C4CONFIG_IE_Pos)                         /*!< GPDMA C4CONFIG: IE Mask             */
+#define GPDMA_C4CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C4CONFIG: ITC Position        */
+#define GPDMA_C4CONFIG_ITC_Msk                                (0x01UL << GPDMA_C4CONFIG_ITC_Pos)                        /*!< GPDMA C4CONFIG: ITC Mask            */
+#define GPDMA_C4CONFIG_L_Pos                                  16                                                        /*!< GPDMA C4CONFIG: L Position          */
+#define GPDMA_C4CONFIG_L_Msk                                  (0x01UL << GPDMA_C4CONFIG_L_Pos)                          /*!< GPDMA C4CONFIG: L Mask              */
+#define GPDMA_C4CONFIG_A_Pos                                  17                                                        /*!< GPDMA C4CONFIG: A Position          */
+#define GPDMA_C4CONFIG_A_Msk                                  (0x01UL << GPDMA_C4CONFIG_A_Pos)                          /*!< GPDMA C4CONFIG: A Mask              */
+#define GPDMA_C4CONFIG_H_Pos                                  18                                                        /*!< GPDMA C4CONFIG: H Position          */
+#define GPDMA_C4CONFIG_H_Msk                                  (0x01UL << GPDMA_C4CONFIG_H_Pos)                          /*!< GPDMA C4CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C5SRCADDR  ----------------------------------------
+#define GPDMA_C5SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C5SRCADDR: SRCADDR Position   */
+#define GPDMA_C5SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos)             /*!< GPDMA C5SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C5DESTADDR  ----------------------------------------
+#define GPDMA_C5DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C5DESTADDR: DESTADDR Position */
+#define GPDMA_C5DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos)           /*!< GPDMA C5DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C5LLI  ------------------------------------------
+#define GPDMA_C5LLI_LM_Pos                                    0                                                         /*!< GPDMA C5LLI: LM Position            */
+#define GPDMA_C5LLI_LM_Msk                                    (0x01UL << GPDMA_C5LLI_LM_Pos)                            /*!< GPDMA C5LLI: LM Mask                */
+#define GPDMA_C5LLI_R_Pos                                     1                                                         /*!< GPDMA C5LLI: R Position             */
+#define GPDMA_C5LLI_R_Msk                                     (0x01UL << GPDMA_C5LLI_R_Pos)                             /*!< GPDMA C5LLI: R Mask                 */
+#define GPDMA_C5LLI_LLI_Pos                                   2                                                         /*!< GPDMA C5LLI: LLI Position           */
+#define GPDMA_C5LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos)                     /*!< GPDMA C5LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C5CONTROL  ----------------------------------------
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C5CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C5CONTROL: SBSIZE Position    */
+#define GPDMA_C5CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos)                    /*!< GPDMA C5CONTROL: SBSIZE Mask        */
+#define GPDMA_C5CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C5CONTROL: DBSIZE Position    */
+#define GPDMA_C5CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos)                    /*!< GPDMA C5CONTROL: DBSIZE Mask        */
+#define GPDMA_C5CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C5CONTROL: SWIDTH Position    */
+#define GPDMA_C5CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos)                    /*!< GPDMA C5CONTROL: SWIDTH Mask        */
+#define GPDMA_C5CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C5CONTROL: DWIDTH Position    */
+#define GPDMA_C5CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos)                    /*!< GPDMA C5CONTROL: DWIDTH Mask        */
+#define GPDMA_C5CONTROL_S_Pos                                 24                                                        /*!< GPDMA C5CONTROL: S Position         */
+#define GPDMA_C5CONTROL_S_Msk                                 (0x01UL << GPDMA_C5CONTROL_S_Pos)                         /*!< GPDMA C5CONTROL: S Mask             */
+#define GPDMA_C5CONTROL_D_Pos                                 25                                                        /*!< GPDMA C5CONTROL: D Position         */
+#define GPDMA_C5CONTROL_D_Msk                                 (0x01UL << GPDMA_C5CONTROL_D_Pos)                         /*!< GPDMA C5CONTROL: D Mask             */
+#define GPDMA_C5CONTROL_SI_Pos                                26                                                        /*!< GPDMA C5CONTROL: SI Position        */
+#define GPDMA_C5CONTROL_SI_Msk                                (0x01UL << GPDMA_C5CONTROL_SI_Pos)                        /*!< GPDMA C5CONTROL: SI Mask            */
+#define GPDMA_C5CONTROL_DI_Pos                                27                                                        /*!< GPDMA C5CONTROL: DI Position        */
+#define GPDMA_C5CONTROL_DI_Msk                                (0x01UL << GPDMA_C5CONTROL_DI_Pos)                        /*!< GPDMA C5CONTROL: DI Mask            */
+#define GPDMA_C5CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C5CONTROL: PROT1 Position     */
+#define GPDMA_C5CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT1_Pos)                     /*!< GPDMA C5CONTROL: PROT1 Mask         */
+#define GPDMA_C5CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C5CONTROL: PROT2 Position     */
+#define GPDMA_C5CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT2_Pos)                     /*!< GPDMA C5CONTROL: PROT2 Mask         */
+#define GPDMA_C5CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C5CONTROL: PROT3 Position     */
+#define GPDMA_C5CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT3_Pos)                     /*!< GPDMA C5CONTROL: PROT3 Mask         */
+#define GPDMA_C5CONTROL_I_Pos                                 31                                                        /*!< GPDMA C5CONTROL: I Position         */
+#define GPDMA_C5CONTROL_I_Msk                                 (0x01UL << GPDMA_C5CONTROL_I_Pos)                         /*!< GPDMA C5CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C5CONFIG  -----------------------------------------
+#define GPDMA_C5CONFIG_E_Pos                                  0                                                         /*!< GPDMA C5CONFIG: E Position          */
+#define GPDMA_C5CONFIG_E_Msk                                  (0x01UL << GPDMA_C5CONFIG_E_Pos)                          /*!< GPDMA C5CONFIG: E Mask              */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C5CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C5CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C5CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C5CONFIG: IE Position         */
+#define GPDMA_C5CONFIG_IE_Msk                                 (0x01UL << GPDMA_C5CONFIG_IE_Pos)                         /*!< GPDMA C5CONFIG: IE Mask             */
+#define GPDMA_C5CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C5CONFIG: ITC Position        */
+#define GPDMA_C5CONFIG_ITC_Msk                                (0x01UL << GPDMA_C5CONFIG_ITC_Pos)                        /*!< GPDMA C5CONFIG: ITC Mask            */
+#define GPDMA_C5CONFIG_L_Pos                                  16                                                        /*!< GPDMA C5CONFIG: L Position          */
+#define GPDMA_C5CONFIG_L_Msk                                  (0x01UL << GPDMA_C5CONFIG_L_Pos)                          /*!< GPDMA C5CONFIG: L Mask              */
+#define GPDMA_C5CONFIG_A_Pos                                  17                                                        /*!< GPDMA C5CONFIG: A Position          */
+#define GPDMA_C5CONFIG_A_Msk                                  (0x01UL << GPDMA_C5CONFIG_A_Pos)                          /*!< GPDMA C5CONFIG: A Mask              */
+#define GPDMA_C5CONFIG_H_Pos                                  18                                                        /*!< GPDMA C5CONFIG: H Position          */
+#define GPDMA_C5CONFIG_H_Msk                                  (0x01UL << GPDMA_C5CONFIG_H_Pos)                          /*!< GPDMA C5CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C6SRCADDR  ----------------------------------------
+#define GPDMA_C6SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C6SRCADDR: SRCADDR Position   */
+#define GPDMA_C6SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos)             /*!< GPDMA C6SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C6DESTADDR  ----------------------------------------
+#define GPDMA_C6DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C6DESTADDR: DESTADDR Position */
+#define GPDMA_C6DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos)           /*!< GPDMA C6DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C6LLI  ------------------------------------------
+#define GPDMA_C6LLI_LM_Pos                                    0                                                         /*!< GPDMA C6LLI: LM Position            */
+#define GPDMA_C6LLI_LM_Msk                                    (0x01UL << GPDMA_C6LLI_LM_Pos)                            /*!< GPDMA C6LLI: LM Mask                */
+#define GPDMA_C6LLI_R_Pos                                     1                                                         /*!< GPDMA C6LLI: R Position             */
+#define GPDMA_C6LLI_R_Msk                                     (0x01UL << GPDMA_C6LLI_R_Pos)                             /*!< GPDMA C6LLI: R Mask                 */
+#define GPDMA_C6LLI_LLI_Pos                                   2                                                         /*!< GPDMA C6LLI: LLI Position           */
+#define GPDMA_C6LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos)                     /*!< GPDMA C6LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C6CONTROL  ----------------------------------------
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C6CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C6CONTROL: SBSIZE Position    */
+#define GPDMA_C6CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos)                    /*!< GPDMA C6CONTROL: SBSIZE Mask        */
+#define GPDMA_C6CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C6CONTROL: DBSIZE Position    */
+#define GPDMA_C6CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos)                    /*!< GPDMA C6CONTROL: DBSIZE Mask        */
+#define GPDMA_C6CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C6CONTROL: SWIDTH Position    */
+#define GPDMA_C6CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos)                    /*!< GPDMA C6CONTROL: SWIDTH Mask        */
+#define GPDMA_C6CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C6CONTROL: DWIDTH Position    */
+#define GPDMA_C6CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos)                    /*!< GPDMA C6CONTROL: DWIDTH Mask        */
+#define GPDMA_C6CONTROL_S_Pos                                 24                                                        /*!< GPDMA C6CONTROL: S Position         */
+#define GPDMA_C6CONTROL_S_Msk                                 (0x01UL << GPDMA_C6CONTROL_S_Pos)                         /*!< GPDMA C6CONTROL: S Mask             */
+#define GPDMA_C6CONTROL_D_Pos                                 25                                                        /*!< GPDMA C6CONTROL: D Position         */
+#define GPDMA_C6CONTROL_D_Msk                                 (0x01UL << GPDMA_C6CONTROL_D_Pos)                         /*!< GPDMA C6CONTROL: D Mask             */
+#define GPDMA_C6CONTROL_SI_Pos                                26                                                        /*!< GPDMA C6CONTROL: SI Position        */
+#define GPDMA_C6CONTROL_SI_Msk                                (0x01UL << GPDMA_C6CONTROL_SI_Pos)                        /*!< GPDMA C6CONTROL: SI Mask            */
+#define GPDMA_C6CONTROL_DI_Pos                                27                                                        /*!< GPDMA C6CONTROL: DI Position        */
+#define GPDMA_C6CONTROL_DI_Msk                                (0x01UL << GPDMA_C6CONTROL_DI_Pos)                        /*!< GPDMA C6CONTROL: DI Mask            */
+#define GPDMA_C6CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C6CONTROL: PROT1 Position     */
+#define GPDMA_C6CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT1_Pos)                     /*!< GPDMA C6CONTROL: PROT1 Mask         */
+#define GPDMA_C6CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C6CONTROL: PROT2 Position     */
+#define GPDMA_C6CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT2_Pos)                     /*!< GPDMA C6CONTROL: PROT2 Mask         */
+#define GPDMA_C6CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C6CONTROL: PROT3 Position     */
+#define GPDMA_C6CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT3_Pos)                     /*!< GPDMA C6CONTROL: PROT3 Mask         */
+#define GPDMA_C6CONTROL_I_Pos                                 31                                                        /*!< GPDMA C6CONTROL: I Position         */
+#define GPDMA_C6CONTROL_I_Msk                                 (0x01UL << GPDMA_C6CONTROL_I_Pos)                         /*!< GPDMA C6CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C6CONFIG  -----------------------------------------
+#define GPDMA_C6CONFIG_E_Pos                                  0                                                         /*!< GPDMA C6CONFIG: E Position          */
+#define GPDMA_C6CONFIG_E_Msk                                  (0x01UL << GPDMA_C6CONFIG_E_Pos)                          /*!< GPDMA C6CONFIG: E Mask              */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C6CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C6CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C6CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C6CONFIG: IE Position         */
+#define GPDMA_C6CONFIG_IE_Msk                                 (0x01UL << GPDMA_C6CONFIG_IE_Pos)                         /*!< GPDMA C6CONFIG: IE Mask             */
+#define GPDMA_C6CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C6CONFIG: ITC Position        */
+#define GPDMA_C6CONFIG_ITC_Msk                                (0x01UL << GPDMA_C6CONFIG_ITC_Pos)                        /*!< GPDMA C6CONFIG: ITC Mask            */
+#define GPDMA_C6CONFIG_L_Pos                                  16                                                        /*!< GPDMA C6CONFIG: L Position          */
+#define GPDMA_C6CONFIG_L_Msk                                  (0x01UL << GPDMA_C6CONFIG_L_Pos)                          /*!< GPDMA C6CONFIG: L Mask              */
+#define GPDMA_C6CONFIG_A_Pos                                  17                                                        /*!< GPDMA C6CONFIG: A Position          */
+#define GPDMA_C6CONFIG_A_Msk                                  (0x01UL << GPDMA_C6CONFIG_A_Pos)                          /*!< GPDMA C6CONFIG: A Mask              */
+#define GPDMA_C6CONFIG_H_Pos                                  18                                                        /*!< GPDMA C6CONFIG: H Position          */
+#define GPDMA_C6CONFIG_H_Msk                                  (0x01UL << GPDMA_C6CONFIG_H_Pos)                          /*!< GPDMA C6CONFIG: H Mask              */
+
+// -------------------------------------  GPDMA_C7SRCADDR  ----------------------------------------
+#define GPDMA_C7SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C7SRCADDR: SRCADDR Position   */
+#define GPDMA_C7SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos)             /*!< GPDMA C7SRCADDR: SRCADDR Mask       */
+
+// ------------------------------------  GPDMA_C7DESTADDR  ----------------------------------------
+#define GPDMA_C7DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C7DESTADDR: DESTADDR Position */
+#define GPDMA_C7DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos)           /*!< GPDMA C7DESTADDR: DESTADDR Mask     */
+
+// ---------------------------------------  GPDMA_C7LLI  ------------------------------------------
+#define GPDMA_C7LLI_LM_Pos                                    0                                                         /*!< GPDMA C7LLI: LM Position            */
+#define GPDMA_C7LLI_LM_Msk                                    (0x01UL << GPDMA_C7LLI_LM_Pos)                            /*!< GPDMA C7LLI: LM Mask                */
+#define GPDMA_C7LLI_R_Pos                                     1                                                         /*!< GPDMA C7LLI: R Position             */
+#define GPDMA_C7LLI_R_Msk                                     (0x01UL << GPDMA_C7LLI_R_Pos)                             /*!< GPDMA C7LLI: R Mask                 */
+#define GPDMA_C7LLI_LLI_Pos                                   2                                                         /*!< GPDMA C7LLI: LLI Position           */
+#define GPDMA_C7LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos)                     /*!< GPDMA C7LLI: LLI Mask               */
+
+// -------------------------------------  GPDMA_C7CONTROL  ----------------------------------------
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask  */
+#define GPDMA_C7CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C7CONTROL: SBSIZE Position    */
+#define GPDMA_C7CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos)                    /*!< GPDMA C7CONTROL: SBSIZE Mask        */
+#define GPDMA_C7CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C7CONTROL: DBSIZE Position    */
+#define GPDMA_C7CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos)                    /*!< GPDMA C7CONTROL: DBSIZE Mask        */
+#define GPDMA_C7CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C7CONTROL: SWIDTH Position    */
+#define GPDMA_C7CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos)                    /*!< GPDMA C7CONTROL: SWIDTH Mask        */
+#define GPDMA_C7CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C7CONTROL: DWIDTH Position    */
+#define GPDMA_C7CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos)                    /*!< GPDMA C7CONTROL: DWIDTH Mask        */
+#define GPDMA_C7CONTROL_S_Pos                                 24                                                        /*!< GPDMA C7CONTROL: S Position         */
+#define GPDMA_C7CONTROL_S_Msk                                 (0x01UL << GPDMA_C7CONTROL_S_Pos)                         /*!< GPDMA C7CONTROL: S Mask             */
+#define GPDMA_C7CONTROL_D_Pos                                 25                                                        /*!< GPDMA C7CONTROL: D Position         */
+#define GPDMA_C7CONTROL_D_Msk                                 (0x01UL << GPDMA_C7CONTROL_D_Pos)                         /*!< GPDMA C7CONTROL: D Mask             */
+#define GPDMA_C7CONTROL_SI_Pos                                26                                                        /*!< GPDMA C7CONTROL: SI Position        */
+#define GPDMA_C7CONTROL_SI_Msk                                (0x01UL << GPDMA_C7CONTROL_SI_Pos)                        /*!< GPDMA C7CONTROL: SI Mask            */
+#define GPDMA_C7CONTROL_DI_Pos                                27                                                        /*!< GPDMA C7CONTROL: DI Position        */
+#define GPDMA_C7CONTROL_DI_Msk                                (0x01UL << GPDMA_C7CONTROL_DI_Pos)                        /*!< GPDMA C7CONTROL: DI Mask            */
+#define GPDMA_C7CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C7CONTROL: PROT1 Position     */
+#define GPDMA_C7CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT1_Pos)                     /*!< GPDMA C7CONTROL: PROT1 Mask         */
+#define GPDMA_C7CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C7CONTROL: PROT2 Position     */
+#define GPDMA_C7CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT2_Pos)                     /*!< GPDMA C7CONTROL: PROT2 Mask         */
+#define GPDMA_C7CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C7CONTROL: PROT3 Position     */
+#define GPDMA_C7CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT3_Pos)                     /*!< GPDMA C7CONTROL: PROT3 Mask         */
+#define GPDMA_C7CONTROL_I_Pos                                 31                                                        /*!< GPDMA C7CONTROL: I Position         */
+#define GPDMA_C7CONTROL_I_Msk                                 (0x01UL << GPDMA_C7CONTROL_I_Pos)                         /*!< GPDMA C7CONTROL: I Mask             */
+
+// -------------------------------------  GPDMA_C7CONFIG  -----------------------------------------
+#define GPDMA_C7CONFIG_E_Pos                                  0                                                         /*!< GPDMA C7CONFIG: E Position          */
+#define GPDMA_C7CONFIG_E_Msk                                  (0x01UL << GPDMA_C7CONFIG_E_Pos)                          /*!< GPDMA C7CONFIG: E Mask              */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask  */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C7CONFIG: FLOWCNTRL Position  */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C7CONFIG: FLOWCNTRL Mask      */
+#define GPDMA_C7CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C7CONFIG: IE Position         */
+#define GPDMA_C7CONFIG_IE_Msk                                 (0x01UL << GPDMA_C7CONFIG_IE_Pos)                         /*!< GPDMA C7CONFIG: IE Mask             */
+#define GPDMA_C7CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C7CONFIG: ITC Position        */
+#define GPDMA_C7CONFIG_ITC_Msk                                (0x01UL << GPDMA_C7CONFIG_ITC_Pos)                        /*!< GPDMA C7CONFIG: ITC Mask            */
+#define GPDMA_C7CONFIG_L_Pos                                  16                                                        /*!< GPDMA C7CONFIG: L Position          */
+#define GPDMA_C7CONFIG_L_Msk                                  (0x01UL << GPDMA_C7CONFIG_L_Pos)                          /*!< GPDMA C7CONFIG: L Mask              */
+#define GPDMA_C7CONFIG_A_Pos                                  17                                                        /*!< GPDMA C7CONFIG: A Position          */
+#define GPDMA_C7CONFIG_A_Msk                                  (0x01UL << GPDMA_C7CONFIG_A_Pos)                          /*!< GPDMA C7CONFIG: A Mask              */
+#define GPDMA_C7CONFIG_H_Pos                                  18                                                        /*!< GPDMA C7CONFIG: H Position          */
+#define GPDMA_C7CONFIG_H_Msk                                  (0x01UL << GPDMA_C7CONFIG_H_Pos)                          /*!< GPDMA C7CONFIG: H Mask              */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SDMMC Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  SDMMC_CTRL  -------------------------------------------
+#define SDMMC_CTRL_CONTROLLER_RESET_Pos                       0                                                         /*!< SDMMC CTRL: CONTROLLER_RESET Position */
+#define SDMMC_CTRL_CONTROLLER_RESET_Msk                       (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos)               /*!< SDMMC CTRL: CONTROLLER_RESET Mask   */
+#define SDMMC_CTRL_FIFO_RESET_Pos                             1                                                         /*!< SDMMC CTRL: FIFO_RESET Position     */
+#define SDMMC_CTRL_FIFO_RESET_Msk                             (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos)                     /*!< SDMMC CTRL: FIFO_RESET Mask         */
+#define SDMMC_CTRL_DMA_RESET_Pos                              2                                                         /*!< SDMMC CTRL: DMA_RESET Position      */
+#define SDMMC_CTRL_DMA_RESET_Msk                              (0x01UL << SDMMC_CTRL_DMA_RESET_Pos)                      /*!< SDMMC CTRL: DMA_RESET Mask          */
+#define SDMMC_CTRL_INT_ENABLE_Pos                             4                                                         /*!< SDMMC CTRL: INT_ENABLE Position     */
+#define SDMMC_CTRL_INT_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos)                     /*!< SDMMC CTRL: INT_ENABLE Mask         */
+#define SDMMC_CTRL_DMA_ENABLE_Pos                             5                                                         /*!< SDMMC CTRL: DMA_ENABLE Position     */
+#define SDMMC_CTRL_DMA_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos)                     /*!< SDMMC CTRL: DMA_ENABLE Mask         */
+#define SDMMC_CTRL_READ_WAIT_Pos                              6                                                         /*!< SDMMC CTRL: READ_WAIT Position      */
+#define SDMMC_CTRL_READ_WAIT_Msk                              (0x01UL << SDMMC_CTRL_READ_WAIT_Pos)                      /*!< SDMMC CTRL: READ_WAIT Mask          */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos                      7                                                         /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk                      (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos)              /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask  */
+#define SDMMC_CTRL_ABORT_READ_DATA_Pos                        8                                                         /*!< SDMMC CTRL: ABORT_READ_DATA Position */
+#define SDMMC_CTRL_ABORT_READ_DATA_Msk                        (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos)                /*!< SDMMC CTRL: ABORT_READ_DATA Mask    */
+#define SDMMC_CTRL_SEND_CCSD_Pos                              9                                                         /*!< SDMMC CTRL: SEND_CCSD Position      */
+#define SDMMC_CTRL_SEND_CCSD_Msk                              (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos)                      /*!< SDMMC CTRL: SEND_CCSD Mask          */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos                    10                                                        /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk                    (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos)            /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos          11                                                        /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk          (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)  /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos                         16                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask     */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos                         20                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask     */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos                       24                                                        /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk                       (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos)               /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask   */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos                      25                                                        /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk                      (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos)              /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask  */
+
+// ---------------------------------------  SDMMC_PWREN  ------------------------------------------
+#define SDMMC_PWREN_POWER_ENABLE_Pos                          0                                                         /*!< SDMMC PWREN: POWER_ENABLE Position  */
+#define SDMMC_PWREN_POWER_ENABLE_Msk                          (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos)            /*!< SDMMC PWREN: POWER_ENABLE Mask      */
+
+// --------------------------------------  SDMMC_CLKDIV  ------------------------------------------
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos                         0                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask     */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos                         8                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask     */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos                         16                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask     */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos                         24                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask     */
+
+// --------------------------------------  SDMMC_CLKSRC  ------------------------------------------
+#define SDMMC_CLKSRC_CLK_SOURCE_Pos                           0                                                         /*!< SDMMC CLKSRC: CLK_SOURCE Position   */
+#define SDMMC_CLKSRC_CLK_SOURCE_Msk                           (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos)             /*!< SDMMC CLKSRC: CLK_SOURCE Mask       */
+
+// --------------------------------------  SDMMC_CLKENA  ------------------------------------------
+#define SDMMC_CLKENA_CCLK_ENABLE_Pos                          0                                                         /*!< SDMMC CLKENA: CCLK_ENABLE Position  */
+#define SDMMC_CLKENA_CCLK_ENABLE_Msk                          (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos)            /*!< SDMMC CLKENA: CCLK_ENABLE Mask      */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos                       16                                                        /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk                       (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos)         /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask   */
+
+// ---------------------------------------  SDMMC_TMOUT  ------------------------------------------
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos                      0                                                         /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk                      (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos)        /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask  */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Pos                          8                                                         /*!< SDMMC TMOUT: DATA_TIMEOUT Position  */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Msk                          (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos)            /*!< SDMMC TMOUT: DATA_TIMEOUT Mask      */
+
+// ---------------------------------------  SDMMC_CTYPE  ------------------------------------------
+#define SDMMC_CTYPE_CARD_WIDTH0_Pos                           0                                                         /*!< SDMMC CTYPE: CARD_WIDTH0 Position   */
+#define SDMMC_CTYPE_CARD_WIDTH0_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH0 Mask       */
+#define SDMMC_CTYPE_CARD_WIDTH1_Pos                           16                                                        /*!< SDMMC CTYPE: CARD_WIDTH1 Position   */
+#define SDMMC_CTYPE_CARD_WIDTH1_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH1 Mask       */
+
+// --------------------------------------  SDMMC_BLKSIZ  ------------------------------------------
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos                           0                                                         /*!< SDMMC BLKSIZ: BLOCK_SIZE Position   */
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk                           (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos)             /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask       */
+
+// --------------------------------------  SDMMC_BYTCNT  ------------------------------------------
+#define SDMMC_BYTCNT_BYTE_COUNT_Pos                           0                                                         /*!< SDMMC BYTCNT: BYTE_COUNT Position   */
+#define SDMMC_BYTCNT_BYTE_COUNT_Msk                           (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos)             /*!< SDMMC BYTCNT: BYTE_COUNT Mask       */
+
+// --------------------------------------  SDMMC_INTMASK  -----------------------------------------
+#define SDMMC_INTMASK_CDET_Pos                                0                                                         /*!< SDMMC INTMASK: CDET Position        */
+#define SDMMC_INTMASK_CDET_Msk                                (0x01UL << SDMMC_INTMASK_CDET_Pos)                        /*!< SDMMC INTMASK: CDET Mask            */
+#define SDMMC_INTMASK_RE_Pos                                  1                                                         /*!< SDMMC INTMASK: RE Position          */
+#define SDMMC_INTMASK_RE_Msk                                  (0x01UL << SDMMC_INTMASK_RE_Pos)                          /*!< SDMMC INTMASK: RE Mask              */
+#define SDMMC_INTMASK_CDONE_Pos                               2                                                         /*!< SDMMC INTMASK: CDONE Position       */
+#define SDMMC_INTMASK_CDONE_Msk                               (0x01UL << SDMMC_INTMASK_CDONE_Pos)                       /*!< SDMMC INTMASK: CDONE Mask           */
+#define SDMMC_INTMASK_DTO_Pos                                 3                                                         /*!< SDMMC INTMASK: DTO Position         */
+#define SDMMC_INTMASK_DTO_Msk                                 (0x01UL << SDMMC_INTMASK_DTO_Pos)                         /*!< SDMMC INTMASK: DTO Mask             */
+#define SDMMC_INTMASK_TXDR_Pos                                4                                                         /*!< SDMMC INTMASK: TXDR Position        */
+#define SDMMC_INTMASK_TXDR_Msk                                (0x01UL << SDMMC_INTMASK_TXDR_Pos)                        /*!< SDMMC INTMASK: TXDR Mask            */
+#define SDMMC_INTMASK_RXDR_Pos                                5                                                         /*!< SDMMC INTMASK: RXDR Position        */
+#define SDMMC_INTMASK_RXDR_Msk                                (0x01UL << SDMMC_INTMASK_RXDR_Pos)                        /*!< SDMMC INTMASK: RXDR Mask            */
+#define SDMMC_INTMASK_RCRC_Pos                                6                                                         /*!< SDMMC INTMASK: RCRC Position        */
+#define SDMMC_INTMASK_RCRC_Msk                                (0x01UL << SDMMC_INTMASK_RCRC_Pos)                        /*!< SDMMC INTMASK: RCRC Mask            */
+#define SDMMC_INTMASK_DCRC_Pos                                7                                                         /*!< SDMMC INTMASK: DCRC Position        */
+#define SDMMC_INTMASK_DCRC_Msk                                (0x01UL << SDMMC_INTMASK_DCRC_Pos)                        /*!< SDMMC INTMASK: DCRC Mask            */
+#define SDMMC_INTMASK_RTO_Pos                                 8                                                         /*!< SDMMC INTMASK: RTO Position         */
+#define SDMMC_INTMASK_RTO_Msk                                 (0x01UL << SDMMC_INTMASK_RTO_Pos)                         /*!< SDMMC INTMASK: RTO Mask             */
+#define SDMMC_INTMASK_DRTO_Pos                                9                                                         /*!< SDMMC INTMASK: DRTO Position        */
+#define SDMMC_INTMASK_DRTO_Msk                                (0x01UL << SDMMC_INTMASK_DRTO_Pos)                        /*!< SDMMC INTMASK: DRTO Mask            */
+#define SDMMC_INTMASK_HTO_Pos                                 10                                                        /*!< SDMMC INTMASK: HTO Position         */
+#define SDMMC_INTMASK_HTO_Msk                                 (0x01UL << SDMMC_INTMASK_HTO_Pos)                         /*!< SDMMC INTMASK: HTO Mask             */
+#define SDMMC_INTMASK_FRUN_Pos                                11                                                        /*!< SDMMC INTMASK: FRUN Position        */
+#define SDMMC_INTMASK_FRUN_Msk                                (0x01UL << SDMMC_INTMASK_FRUN_Pos)                        /*!< SDMMC INTMASK: FRUN Mask            */
+#define SDMMC_INTMASK_HLE_Pos                                 12                                                        /*!< SDMMC INTMASK: HLE Position         */
+#define SDMMC_INTMASK_HLE_Msk                                 (0x01UL << SDMMC_INTMASK_HLE_Pos)                         /*!< SDMMC INTMASK: HLE Mask             */
+#define SDMMC_INTMASK_SBE_Pos                                 13                                                        /*!< SDMMC INTMASK: SBE Position         */
+#define SDMMC_INTMASK_SBE_Msk                                 (0x01UL << SDMMC_INTMASK_SBE_Pos)                         /*!< SDMMC INTMASK: SBE Mask             */
+#define SDMMC_INTMASK_ACD_Pos                                 14                                                        /*!< SDMMC INTMASK: ACD Position         */
+#define SDMMC_INTMASK_ACD_Msk                                 (0x01UL << SDMMC_INTMASK_ACD_Pos)                         /*!< SDMMC INTMASK: ACD Mask             */
+#define SDMMC_INTMASK_EBE_Pos                                 15                                                        /*!< SDMMC INTMASK: EBE Position         */
+#define SDMMC_INTMASK_EBE_Msk                                 (0x01UL << SDMMC_INTMASK_EBE_Pos)                         /*!< SDMMC INTMASK: EBE Mask             */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Pos                       16                                                        /*!< SDMMC INTMASK: SDIO_INT_MASK Position */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Msk                       (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos)         /*!< SDMMC INTMASK: SDIO_INT_MASK Mask   */
+
+// --------------------------------------  SDMMC_CMDARG  ------------------------------------------
+#define SDMMC_CMDARG_CMD_ARG_Pos                              0                                                         /*!< SDMMC CMDARG: CMD_ARG Position      */
+#define SDMMC_CMDARG_CMD_ARG_Msk                              (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos)                /*!< SDMMC CMDARG: CMD_ARG Mask          */
+
+// ----------------------------------------  SDMMC_CMD  -------------------------------------------
+#define SDMMC_CMD_CMD_INDEX_Pos                               0                                                         /*!< SDMMC CMD: CMD_INDEX Position       */
+#define SDMMC_CMD_CMD_INDEX_Msk                               (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos)                       /*!< SDMMC CMD: CMD_INDEX Mask           */
+#define SDMMC_CMD_RESPONSE_EXPECT_Pos                         6                                                         /*!< SDMMC CMD: RESPONSE_EXPECT Position */
+#define SDMMC_CMD_RESPONSE_EXPECT_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos)                 /*!< SDMMC CMD: RESPONSE_EXPECT Mask     */
+#define SDMMC_CMD_RESPONSE_LENGTH_Pos                         7                                                         /*!< SDMMC CMD: RESPONSE_LENGTH Position */
+#define SDMMC_CMD_RESPONSE_LENGTH_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos)                 /*!< SDMMC CMD: RESPONSE_LENGTH Mask     */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos                      8                                                         /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk                      (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos)              /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask  */
+#define SDMMC_CMD_DATA_EXPECTED_Pos                           9                                                         /*!< SDMMC CMD: DATA_EXPECTED Position   */
+#define SDMMC_CMD_DATA_EXPECTED_Msk                           (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos)                   /*!< SDMMC CMD: DATA_EXPECTED Mask       */
+#define SDMMC_CMD_READ_WRITE_Pos                              10                                                        /*!< SDMMC CMD: READ_WRITE Position      */
+#define SDMMC_CMD_READ_WRITE_Msk                              (0x01UL << SDMMC_CMD_READ_WRITE_Pos)                      /*!< SDMMC CMD: READ_WRITE Mask          */
+#define SDMMC_CMD_TRANSFER_MODE_Pos                           11                                                        /*!< SDMMC CMD: TRANSFER_MODE Position   */
+#define SDMMC_CMD_TRANSFER_MODE_Msk                           (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos)                   /*!< SDMMC CMD: TRANSFER_MODE Mask       */
+#define SDMMC_CMD_SEND_AUTO_STOP_Pos                          12                                                        /*!< SDMMC CMD: SEND_AUTO_STOP Position  */
+#define SDMMC_CMD_SEND_AUTO_STOP_Msk                          (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos)                  /*!< SDMMC CMD: SEND_AUTO_STOP Mask      */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos                   13                                                        /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk                   (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos)           /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */
+#define SDMMC_CMD_STOP_ABORT_CMd_Pos                          14                                                        /*!< SDMMC CMD: STOP_ABORT_CMd Position  */
+#define SDMMC_CMD_STOP_ABORT_CMd_Msk                          (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos)                  /*!< SDMMC CMD: STOP_ABORT_CMd Mask      */
+#define SDMMC_CMD_SEND_INITIALIZATION_Pos                     15                                                        /*!< SDMMC CMD: SEND_INITIALIZATION Position */
+#define SDMMC_CMD_SEND_INITIALIZATION_Msk                     (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos)             /*!< SDMMC CMD: SEND_INITIALIZATION Mask */
+#define SDMMC_CMD_CARD_NUMBER_Pos                             16                                                        /*!< SDMMC CMD: CARD_NUMBER Position     */
+#define SDMMC_CMD_CARD_NUMBER_Msk                             (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos)                     /*!< SDMMC CMD: CARD_NUMBER Mask         */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos             21                                                        /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk             (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)     /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Pos                       22                                                        /*!< SDMMC CMD: READ_CEATA_DEVICE Position */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Msk                       (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos)               /*!< SDMMC CMD: READ_CEATA_DEVICE Mask   */
+#define SDMMC_CMD_CCS_EXPECTED_Pos                            23                                                        /*!< SDMMC CMD: CCS_EXPECTED Position    */
+#define SDMMC_CMD_CCS_EXPECTED_Msk                            (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos)                    /*!< SDMMC CMD: CCS_EXPECTED Mask        */
+#define SDMMC_CMD_ENABLE_BOOT_Pos                             24                                                        /*!< SDMMC CMD: ENABLE_BOOT Position     */
+#define SDMMC_CMD_ENABLE_BOOT_Msk                             (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos)                     /*!< SDMMC CMD: ENABLE_BOOT Mask         */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos                         25                                                        /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk                         (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos)                 /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask     */
+#define SDMMC_CMD_DISABLE_BOOT_Pos                            26                                                        /*!< SDMMC CMD: DISABLE_BOOT Position    */
+#define SDMMC_CMD_DISABLE_BOOT_Msk                            (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos)                    /*!< SDMMC CMD: DISABLE_BOOT Mask        */
+#define SDMMC_CMD_BOOT_MODE_Pos                               27                                                        /*!< SDMMC CMD: BOOT_MODE Position       */
+#define SDMMC_CMD_BOOT_MODE_Msk                               (0x01UL << SDMMC_CMD_BOOT_MODE_Pos)                       /*!< SDMMC CMD: BOOT_MODE Mask           */
+#define SDMMC_CMD_VOLT_SWITCH_Pos                             28                                                        /*!< SDMMC CMD: VOLT_SWITCH Position     */
+#define SDMMC_CMD_VOLT_SWITCH_Msk                             (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos)                     /*!< SDMMC CMD: VOLT_SWITCH Mask         */
+#define SDMMC_CMD_START_CMD_Pos                               31                                                        /*!< SDMMC CMD: START_CMD Position       */
+#define SDMMC_CMD_START_CMD_Msk                               (0x01UL << SDMMC_CMD_START_CMD_Pos)                       /*!< SDMMC CMD: START_CMD Mask           */
+
+// ---------------------------------------  SDMMC_RESP0  ------------------------------------------
+#define SDMMC_RESP0_RESPONSE0_Pos                             0                                                         /*!< SDMMC RESP0: RESPONSE0 Position     */
+#define SDMMC_RESP0_RESPONSE0_Msk                             (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos)               /*!< SDMMC RESP0: RESPONSE0 Mask         */
+
+// ---------------------------------------  SDMMC_RESP1  ------------------------------------------
+#define SDMMC_RESP1_RESPONSE1_Pos                             0                                                         /*!< SDMMC RESP1: RESPONSE1 Position     */
+#define SDMMC_RESP1_RESPONSE1_Msk                             (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos)               /*!< SDMMC RESP1: RESPONSE1 Mask         */
+
+// ---------------------------------------  SDMMC_RESP2  ------------------------------------------
+#define SDMMC_RESP2_RESPONSE2_Pos                             0                                                         /*!< SDMMC RESP2: RESPONSE2 Position     */
+#define SDMMC_RESP2_RESPONSE2_Msk                             (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos)               /*!< SDMMC RESP2: RESPONSE2 Mask         */
+
+// ---------------------------------------  SDMMC_RESP3  ------------------------------------------
+#define SDMMC_RESP3_RESPONSE3_Pos                             0                                                         /*!< SDMMC RESP3: RESPONSE3 Position     */
+#define SDMMC_RESP3_RESPONSE3_Msk                             (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos)               /*!< SDMMC RESP3: RESPONSE3 Mask         */
+
+// --------------------------------------  SDMMC_MINTSTS  -----------------------------------------
+#define SDMMC_MINTSTS_CDET_Pos                                0                                                         /*!< SDMMC MINTSTS: CDET Position        */
+#define SDMMC_MINTSTS_CDET_Msk                                (0x01UL << SDMMC_MINTSTS_CDET_Pos)                        /*!< SDMMC MINTSTS: CDET Mask            */
+#define SDMMC_MINTSTS_RE_Pos                                  1                                                         /*!< SDMMC MINTSTS: RE Position          */
+#define SDMMC_MINTSTS_RE_Msk                                  (0x01UL << SDMMC_MINTSTS_RE_Pos)                          /*!< SDMMC MINTSTS: RE Mask              */
+#define SDMMC_MINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC MINTSTS: CDONE Position       */
+#define SDMMC_MINTSTS_CDONE_Msk                               (0x01UL << SDMMC_MINTSTS_CDONE_Pos)                       /*!< SDMMC MINTSTS: CDONE Mask           */
+#define SDMMC_MINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC MINTSTS: DTO Position         */
+#define SDMMC_MINTSTS_DTO_Msk                                 (0x01UL << SDMMC_MINTSTS_DTO_Pos)                         /*!< SDMMC MINTSTS: DTO Mask             */
+#define SDMMC_MINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC MINTSTS: TXDR Position        */
+#define SDMMC_MINTSTS_TXDR_Msk                                (0x01UL << SDMMC_MINTSTS_TXDR_Pos)                        /*!< SDMMC MINTSTS: TXDR Mask            */
+#define SDMMC_MINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC MINTSTS: RXDR Position        */
+#define SDMMC_MINTSTS_RXDR_Msk                                (0x01UL << SDMMC_MINTSTS_RXDR_Pos)                        /*!< SDMMC MINTSTS: RXDR Mask            */
+#define SDMMC_MINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC MINTSTS: RCRC Position        */
+#define SDMMC_MINTSTS_RCRC_Msk                                (0x01UL << SDMMC_MINTSTS_RCRC_Pos)                        /*!< SDMMC MINTSTS: RCRC Mask            */
+#define SDMMC_MINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC MINTSTS: DCRC Position        */
+#define SDMMC_MINTSTS_DCRC_Msk                                (0x01UL << SDMMC_MINTSTS_DCRC_Pos)                        /*!< SDMMC MINTSTS: DCRC Mask            */
+#define SDMMC_MINTSTS_RTO_Pos                                 8                                                         /*!< SDMMC MINTSTS: RTO Position         */
+#define SDMMC_MINTSTS_RTO_Msk                                 (0x01UL << SDMMC_MINTSTS_RTO_Pos)                         /*!< SDMMC MINTSTS: RTO Mask             */
+#define SDMMC_MINTSTS_DRTO_Pos                                9                                                         /*!< SDMMC MINTSTS: DRTO Position        */
+#define SDMMC_MINTSTS_DRTO_Msk                                (0x01UL << SDMMC_MINTSTS_DRTO_Pos)                        /*!< SDMMC MINTSTS: DRTO Mask            */
+#define SDMMC_MINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC MINTSTS: HTO Position         */
+#define SDMMC_MINTSTS_HTO_Msk                                 (0x01UL << SDMMC_MINTSTS_HTO_Pos)                         /*!< SDMMC MINTSTS: HTO Mask             */
+#define SDMMC_MINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC MINTSTS: FRUN Position        */
+#define SDMMC_MINTSTS_FRUN_Msk                                (0x01UL << SDMMC_MINTSTS_FRUN_Pos)                        /*!< SDMMC MINTSTS: FRUN Mask            */
+#define SDMMC_MINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC MINTSTS: HLE Position         */
+#define SDMMC_MINTSTS_HLE_Msk                                 (0x01UL << SDMMC_MINTSTS_HLE_Pos)                         /*!< SDMMC MINTSTS: HLE Mask             */
+#define SDMMC_MINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC MINTSTS: SBE Position         */
+#define SDMMC_MINTSTS_SBE_Msk                                 (0x01UL << SDMMC_MINTSTS_SBE_Pos)                         /*!< SDMMC MINTSTS: SBE Mask             */
+#define SDMMC_MINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC MINTSTS: ACD Position         */
+#define SDMMC_MINTSTS_ACD_Msk                                 (0x01UL << SDMMC_MINTSTS_ACD_Pos)                         /*!< SDMMC MINTSTS: ACD Mask             */
+#define SDMMC_MINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC MINTSTS: EBE Position         */
+#define SDMMC_MINTSTS_EBE_Msk                                 (0x01UL << SDMMC_MINTSTS_EBE_Pos)                         /*!< SDMMC MINTSTS: EBE Mask             */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask  */
+
+// --------------------------------------  SDMMC_RINTSTS  -----------------------------------------
+#define SDMMC_RINTSTS_CDET_Pos                                0                                                         /*!< SDMMC RINTSTS: CDET Position        */
+#define SDMMC_RINTSTS_CDET_Msk                                (0x01UL << SDMMC_RINTSTS_CDET_Pos)                        /*!< SDMMC RINTSTS: CDET Mask            */
+#define SDMMC_RINTSTS_RE_Pos                                  1                                                         /*!< SDMMC RINTSTS: RE Position          */
+#define SDMMC_RINTSTS_RE_Msk                                  (0x01UL << SDMMC_RINTSTS_RE_Pos)                          /*!< SDMMC RINTSTS: RE Mask              */
+#define SDMMC_RINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC RINTSTS: CDONE Position       */
+#define SDMMC_RINTSTS_CDONE_Msk                               (0x01UL << SDMMC_RINTSTS_CDONE_Pos)                       /*!< SDMMC RINTSTS: CDONE Mask           */
+#define SDMMC_RINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC RINTSTS: DTO Position         */
+#define SDMMC_RINTSTS_DTO_Msk                                 (0x01UL << SDMMC_RINTSTS_DTO_Pos)                         /*!< SDMMC RINTSTS: DTO Mask             */
+#define SDMMC_RINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC RINTSTS: TXDR Position        */
+#define SDMMC_RINTSTS_TXDR_Msk                                (0x01UL << SDMMC_RINTSTS_TXDR_Pos)                        /*!< SDMMC RINTSTS: TXDR Mask            */
+#define SDMMC_RINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC RINTSTS: RXDR Position        */
+#define SDMMC_RINTSTS_RXDR_Msk                                (0x01UL << SDMMC_RINTSTS_RXDR_Pos)                        /*!< SDMMC RINTSTS: RXDR Mask            */
+#define SDMMC_RINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC RINTSTS: RCRC Position        */
+#define SDMMC_RINTSTS_RCRC_Msk                                (0x01UL << SDMMC_RINTSTS_RCRC_Pos)                        /*!< SDMMC RINTSTS: RCRC Mask            */
+#define SDMMC_RINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC RINTSTS: DCRC Position        */
+#define SDMMC_RINTSTS_DCRC_Msk                                (0x01UL << SDMMC_RINTSTS_DCRC_Pos)                        /*!< SDMMC RINTSTS: DCRC Mask            */
+#define SDMMC_RINTSTS_RTO_BAR_Pos                             8                                                         /*!< SDMMC RINTSTS: RTO_BAR Position     */
+#define SDMMC_RINTSTS_RTO_BAR_Msk                             (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos)                     /*!< SDMMC RINTSTS: RTO_BAR Mask         */
+#define SDMMC_RINTSTS_DRTO_BDS_Pos                            9                                                         /*!< SDMMC RINTSTS: DRTO_BDS Position    */
+#define SDMMC_RINTSTS_DRTO_BDS_Msk                            (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos)                    /*!< SDMMC RINTSTS: DRTO_BDS Mask        */
+#define SDMMC_RINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC RINTSTS: HTO Position         */
+#define SDMMC_RINTSTS_HTO_Msk                                 (0x01UL << SDMMC_RINTSTS_HTO_Pos)                         /*!< SDMMC RINTSTS: HTO Mask             */
+#define SDMMC_RINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC RINTSTS: FRUN Position        */
+#define SDMMC_RINTSTS_FRUN_Msk                                (0x01UL << SDMMC_RINTSTS_FRUN_Pos)                        /*!< SDMMC RINTSTS: FRUN Mask            */
+#define SDMMC_RINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC RINTSTS: HLE Position         */
+#define SDMMC_RINTSTS_HLE_Msk                                 (0x01UL << SDMMC_RINTSTS_HLE_Pos)                         /*!< SDMMC RINTSTS: HLE Mask             */
+#define SDMMC_RINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC RINTSTS: SBE Position         */
+#define SDMMC_RINTSTS_SBE_Msk                                 (0x01UL << SDMMC_RINTSTS_SBE_Pos)                         /*!< SDMMC RINTSTS: SBE Mask             */
+#define SDMMC_RINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC RINTSTS: ACD Position         */
+#define SDMMC_RINTSTS_ACD_Msk                                 (0x01UL << SDMMC_RINTSTS_ACD_Pos)                         /*!< SDMMC RINTSTS: ACD Mask             */
+#define SDMMC_RINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC RINTSTS: EBE Position         */
+#define SDMMC_RINTSTS_EBE_Msk                                 (0x01UL << SDMMC_RINTSTS_EBE_Pos)                         /*!< SDMMC RINTSTS: EBE Mask             */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask  */
+
+// --------------------------------------  SDMMC_STATUS  ------------------------------------------
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos                    0                                                         /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos                    1                                                         /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_EMPTY_Pos                           2                                                         /*!< SDMMC STATUS: FIFO_EMPTY Position   */
+#define SDMMC_STATUS_FIFO_EMPTY_Msk                           (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos)                   /*!< SDMMC STATUS: FIFO_EMPTY Mask       */
+#define SDMMC_STATUS_FIFO_FULL_Pos                            3                                                         /*!< SDMMC STATUS: FIFO_FULL Position    */
+#define SDMMC_STATUS_FIFO_FULL_Msk                            (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos)                    /*!< SDMMC STATUS: FIFO_FULL Mask        */
+#define SDMMC_STATUS_CMDFSMSTATES_Pos                         4                                                         /*!< SDMMC STATUS: CMDFSMSTATES Position */
+#define SDMMC_STATUS_CMDFSMSTATES_Msk                         (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos)                 /*!< SDMMC STATUS: CMDFSMSTATES Mask     */
+#define SDMMC_STATUS_DATA_3_STATUS_Pos                        8                                                         /*!< SDMMC STATUS: DATA_3_STATUS Position */
+#define SDMMC_STATUS_DATA_3_STATUS_Msk                        (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos)                /*!< SDMMC STATUS: DATA_3_STATUS Mask    */
+#define SDMMC_STATUS_DATA_BUSY_Pos                            9                                                         /*!< SDMMC STATUS: DATA_BUSY Position    */
+#define SDMMC_STATUS_DATA_BUSY_Msk                            (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos)                    /*!< SDMMC STATUS: DATA_BUSY Mask        */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos                   10                                                        /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk                   (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos)           /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */
+#define SDMMC_STATUS_RESPONSE_INDEX_Pos                       11                                                        /*!< SDMMC STATUS: RESPONSE_INDEX Position */
+#define SDMMC_STATUS_RESPONSE_INDEX_Msk                       (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos)               /*!< SDMMC STATUS: RESPONSE_INDEX Mask   */
+#define SDMMC_STATUS_FIFO_COUNT_Pos                           17                                                        /*!< SDMMC STATUS: FIFO_COUNT Position   */
+#define SDMMC_STATUS_FIFO_COUNT_Msk                           (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos)             /*!< SDMMC STATUS: FIFO_COUNT Mask       */
+#define SDMMC_STATUS_DMA_ACK_Pos                              30                                                        /*!< SDMMC STATUS: DMA_ACK Position      */
+#define SDMMC_STATUS_DMA_ACK_Msk                              (0x01UL << SDMMC_STATUS_DMA_ACK_Pos)                      /*!< SDMMC STATUS: DMA_ACK Mask          */
+#define SDMMC_STATUS_DMA_REQ_Pos                              31                                                        /*!< SDMMC STATUS: DMA_REQ Position      */
+#define SDMMC_STATUS_DMA_REQ_Msk                              (0x01UL << SDMMC_STATUS_DMA_REQ_Pos)                      /*!< SDMMC STATUS: DMA_REQ Mask          */
+
+// --------------------------------------  SDMMC_FIFOTH  ------------------------------------------
+#define SDMMC_FIFOTH_TX_WMARK_Pos                             0                                                         /*!< SDMMC FIFOTH: TX_WMARK Position     */
+#define SDMMC_FIFOTH_TX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos)               /*!< SDMMC FIFOTH: TX_WMARK Mask         */
+#define SDMMC_FIFOTH_RX_WMARK_Pos                             16                                                        /*!< SDMMC FIFOTH: RX_WMARK Position     */
+#define SDMMC_FIFOTH_RX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos)               /*!< SDMMC FIFOTH: RX_WMARK Mask         */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos      28                                                        /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk      (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */
+
+// --------------------------------------  SDMMC_CDETECT  -----------------------------------------
+#define SDMMC_CDETECT_CARD_DETECT_N_Pos                       0                                                         /*!< SDMMC CDETECT: CARD_DETECT_N Position */
+#define SDMMC_CDETECT_CARD_DETECT_N_Msk                       (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos)         /*!< SDMMC CDETECT: CARD_DETECT_N Mask   */
+
+// --------------------------------------  SDMMC_WRTPRT  ------------------------------------------
+#define SDMMC_WRTPRT_WRITE_PROTECT_Pos                        0                                                         /*!< SDMMC WRTPRT: WRITE_PROTECT Position */
+#define SDMMC_WRTPRT_WRITE_PROTECT_Msk                        (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos)          /*!< SDMMC WRTPRT: WRITE_PROTECT Mask    */
+
+// ---------------------------------------  SDMMC_GPIO  -------------------------------------------
+#define SDMMC_GPIO_GPI_Pos                                    0                                                         /*!< SDMMC GPIO: GPI Position            */
+#define SDMMC_GPIO_GPI_Msk                                    (0x000000ffUL << SDMMC_GPIO_GPI_Pos)                      /*!< SDMMC GPIO: GPI Mask                */
+#define SDMMC_GPIO_GPO_Pos                                    8                                                         /*!< SDMMC GPIO: GPO Position            */
+#define SDMMC_GPIO_GPO_Msk                                    (0x0000ffffUL << SDMMC_GPIO_GPO_Pos)                      /*!< SDMMC GPIO: GPO Mask                */
+
+// --------------------------------------  SDMMC_TCBCNT  ------------------------------------------
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)  /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */
+
+// --------------------------------------  SDMMC_TBBCNT  ------------------------------------------
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)  /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */
+
+// --------------------------------------  SDMMC_DEBNCE  ------------------------------------------
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos                       0                                                         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk                       (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos)         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask   */
+
+// ---------------------------------------  SDMMC_USRID  ------------------------------------------
+#define SDMMC_USRID_USRID_Pos                                 0                                                         /*!< SDMMC USRID: USRID Position         */
+#define SDMMC_USRID_USRID_Msk                                 (0xffffffffUL << SDMMC_USRID_USRID_Pos)                   /*!< SDMMC USRID: USRID Mask             */
+
+// ---------------------------------------  SDMMC_VERID  ------------------------------------------
+#define SDMMC_VERID_VERID_Pos                                 0                                                         /*!< SDMMC VERID: VERID Position         */
+#define SDMMC_VERID_VERID_Msk                                 (0xffffffffUL << SDMMC_VERID_VERID_Pos)                   /*!< SDMMC VERID: VERID Mask             */
+
+// --------------------------------------  SDMMC_UHS_REG  -----------------------------------------
+#define SDMMC_UHS_REG_VOLT_REG_Pos                            0                                                         /*!< SDMMC UHS_REG: VOLT_REG Position    */
+#define SDMMC_UHS_REG_VOLT_REG_Msk                            (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos)              /*!< SDMMC UHS_REG: VOLT_REG Mask        */
+#define SDMMC_UHS_REG_DDR_REG_Pos                             16                                                        /*!< SDMMC UHS_REG: DDR_REG Position     */
+#define SDMMC_UHS_REG_DDR_REG_Msk                             (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos)               /*!< SDMMC UHS_REG: DDR_REG Mask         */
+
+// ---------------------------------------  SDMMC_RST_N  ------------------------------------------
+#define SDMMC_RST_N_CARD_RESET_Pos                            0                                                         /*!< SDMMC RST_N: CARD_RESET Position    */
+#define SDMMC_RST_N_CARD_RESET_Msk                            (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos)              /*!< SDMMC RST_N: CARD_RESET Mask        */
+
+// ---------------------------------------  SDMMC_BMOD  -------------------------------------------
+#define SDMMC_BMOD_SWR_Pos                                    0                                                         /*!< SDMMC BMOD: SWR Position            */
+#define SDMMC_BMOD_SWR_Msk                                    (0x01UL << SDMMC_BMOD_SWR_Pos)                            /*!< SDMMC BMOD: SWR Mask                */
+#define SDMMC_BMOD_FB_Pos                                     1                                                         /*!< SDMMC BMOD: FB Position             */
+#define SDMMC_BMOD_FB_Msk                                     (0x01UL << SDMMC_BMOD_FB_Pos)                             /*!< SDMMC BMOD: FB Mask                 */
+#define SDMMC_BMOD_DSL_Pos                                    2                                                         /*!< SDMMC BMOD: DSL Position            */
+#define SDMMC_BMOD_DSL_Msk                                    (0x1fUL << SDMMC_BMOD_DSL_Pos)                            /*!< SDMMC BMOD: DSL Mask                */
+#define SDMMC_BMOD_DE_Pos                                     7                                                         /*!< SDMMC BMOD: DE Position             */
+#define SDMMC_BMOD_DE_Msk                                     (0x01UL << SDMMC_BMOD_DE_Pos)                             /*!< SDMMC BMOD: DE Mask                 */
+#define SDMMC_BMOD_PBL_Pos                                    8                                                         /*!< SDMMC BMOD: PBL Position            */
+#define SDMMC_BMOD_PBL_Msk                                    (0x07UL << SDMMC_BMOD_PBL_Pos)                            /*!< SDMMC BMOD: PBL Mask                */
+
+// --------------------------------------  SDMMC_PLDMND  ------------------------------------------
+#define SDMMC_PLDMND_PD_Pos                                   0                                                         /*!< SDMMC PLDMND: PD Position           */
+#define SDMMC_PLDMND_PD_Msk                                   (0xffffffffUL << SDMMC_PLDMND_PD_Pos)                     /*!< SDMMC PLDMND: PD Mask               */
+
+// --------------------------------------  SDMMC_DBADDR  ------------------------------------------
+#define SDMMC_DBADDR_SDL_Pos                                  0                                                         /*!< SDMMC DBADDR: SDL Position          */
+#define SDMMC_DBADDR_SDL_Msk                                  (0xffffffffUL << SDMMC_DBADDR_SDL_Pos)                    /*!< SDMMC DBADDR: SDL Mask              */
+
+// ---------------------------------------  SDMMC_IDSTS  ------------------------------------------
+#define SDMMC_IDSTS_TI_Pos                                    0                                                         /*!< SDMMC IDSTS: TI Position            */
+#define SDMMC_IDSTS_TI_Msk                                    (0x01UL << SDMMC_IDSTS_TI_Pos)                            /*!< SDMMC IDSTS: TI Mask                */
+#define SDMMC_IDSTS_RI_Pos                                    1                                                         /*!< SDMMC IDSTS: RI Position            */
+#define SDMMC_IDSTS_RI_Msk                                    (0x01UL << SDMMC_IDSTS_RI_Pos)                            /*!< SDMMC IDSTS: RI Mask                */
+#define SDMMC_IDSTS_FBE_Pos                                   2                                                         /*!< SDMMC IDSTS: FBE Position           */
+#define SDMMC_IDSTS_FBE_Msk                                   (0x01UL << SDMMC_IDSTS_FBE_Pos)                           /*!< SDMMC IDSTS: FBE Mask               */
+#define SDMMC_IDSTS_DU_Pos                                    4                                                         /*!< SDMMC IDSTS: DU Position            */
+#define SDMMC_IDSTS_DU_Msk                                    (0x01UL << SDMMC_IDSTS_DU_Pos)                            /*!< SDMMC IDSTS: DU Mask                */
+#define SDMMC_IDSTS_CES_Pos                                   5                                                         /*!< SDMMC IDSTS: CES Position           */
+#define SDMMC_IDSTS_CES_Msk                                   (0x01UL << SDMMC_IDSTS_CES_Pos)                           /*!< SDMMC IDSTS: CES Mask               */
+#define SDMMC_IDSTS_NIS_Pos                                   8                                                         /*!< SDMMC IDSTS: NIS Position           */
+#define SDMMC_IDSTS_NIS_Msk                                   (0x01UL << SDMMC_IDSTS_NIS_Pos)                           /*!< SDMMC IDSTS: NIS Mask               */
+#define SDMMC_IDSTS_AIS_Pos                                   9                                                         /*!< SDMMC IDSTS: AIS Position           */
+#define SDMMC_IDSTS_AIS_Msk                                   (0x01UL << SDMMC_IDSTS_AIS_Pos)                           /*!< SDMMC IDSTS: AIS Mask               */
+#define SDMMC_IDSTS_EB_Pos                                    10                                                        /*!< SDMMC IDSTS: EB Position            */
+#define SDMMC_IDSTS_EB_Msk                                    (0x07UL << SDMMC_IDSTS_EB_Pos)                            /*!< SDMMC IDSTS: EB Mask                */
+#define SDMMC_IDSTS_FSM_Pos                                   13                                                        /*!< SDMMC IDSTS: FSM Position           */
+#define SDMMC_IDSTS_FSM_Msk                                   (0x0fUL << SDMMC_IDSTS_FSM_Pos)                           /*!< SDMMC IDSTS: FSM Mask               */
+
+// --------------------------------------  SDMMC_IDINTEN  -----------------------------------------
+#define SDMMC_IDINTEN_TI_Pos                                  0                                                         /*!< SDMMC IDINTEN: TI Position          */
+#define SDMMC_IDINTEN_TI_Msk                                  (0x01UL << SDMMC_IDINTEN_TI_Pos)                          /*!< SDMMC IDINTEN: TI Mask              */
+#define SDMMC_IDINTEN_RI_Pos                                  1                                                         /*!< SDMMC IDINTEN: RI Position          */
+#define SDMMC_IDINTEN_RI_Msk                                  (0x01UL << SDMMC_IDINTEN_RI_Pos)                          /*!< SDMMC IDINTEN: RI Mask              */
+#define SDMMC_IDINTEN_FBE_Pos                                 2                                                         /*!< SDMMC IDINTEN: FBE Position         */
+#define SDMMC_IDINTEN_FBE_Msk                                 (0x01UL << SDMMC_IDINTEN_FBE_Pos)                         /*!< SDMMC IDINTEN: FBE Mask             */
+#define SDMMC_IDINTEN_DU_Pos                                  4                                                         /*!< SDMMC IDINTEN: DU Position          */
+#define SDMMC_IDINTEN_DU_Msk                                  (0x01UL << SDMMC_IDINTEN_DU_Pos)                          /*!< SDMMC IDINTEN: DU Mask              */
+#define SDMMC_IDINTEN_CES_Pos                                 5                                                         /*!< SDMMC IDINTEN: CES Position         */
+#define SDMMC_IDINTEN_CES_Msk                                 (0x01UL << SDMMC_IDINTEN_CES_Pos)                         /*!< SDMMC IDINTEN: CES Mask             */
+#define SDMMC_IDINTEN_NIS_Pos                                 8                                                         /*!< SDMMC IDINTEN: NIS Position         */
+#define SDMMC_IDINTEN_NIS_Msk                                 (0x01UL << SDMMC_IDINTEN_NIS_Pos)                         /*!< SDMMC IDINTEN: NIS Mask             */
+#define SDMMC_IDINTEN_AIS_Pos                                 9                                                         /*!< SDMMC IDINTEN: AIS Position         */
+#define SDMMC_IDINTEN_AIS_Msk                                 (0x01UL << SDMMC_IDINTEN_AIS_Pos)                         /*!< SDMMC IDINTEN: AIS Mask             */
+
+// --------------------------------------  SDMMC_DSCADDR  -----------------------------------------
+#define SDMMC_DSCADDR_HDA_Pos                                 0                                                         /*!< SDMMC DSCADDR: HDA Position         */
+#define SDMMC_DSCADDR_HDA_Msk                                 (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos)                   /*!< SDMMC DSCADDR: HDA Mask             */
+
+// --------------------------------------  SDMMC_BUFADDR  -----------------------------------------
+#define SDMMC_BUFADDR_HBA_Pos                                 0                                                         /*!< SDMMC BUFADDR: HBA Position         */
+#define SDMMC_BUFADDR_HBA_Msk                                 (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos)                   /*!< SDMMC BUFADDR: HBA Mask             */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  EMC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  EMC_CONTROL  ------------------------------------------
+#define EMC_CONTROL_E_Pos                                     0                                                         /*!< EMC CONTROL: E Position             */
+#define EMC_CONTROL_E_Msk                                     (0x01UL << EMC_CONTROL_E_Pos)                             /*!< EMC CONTROL: E Mask                 */
+#define EMC_CONTROL_M_Pos                                     1                                                         /*!< EMC CONTROL: M Position             */
+#define EMC_CONTROL_M_Msk                                     (0x01UL << EMC_CONTROL_M_Pos)                             /*!< EMC CONTROL: M Mask                 */
+#define EMC_CONTROL_L_Pos                                     2                                                         /*!< EMC CONTROL: L Position             */
+#define EMC_CONTROL_L_Msk                                     (0x01UL << EMC_CONTROL_L_Pos)                             /*!< EMC CONTROL: L Mask                 */
+
+// ---------------------------------------  EMC_STATUS  -------------------------------------------
+#define EMC_STATUS_B_Pos                                      0                                                         /*!< EMC STATUS: B Position              */
+#define EMC_STATUS_B_Msk                                      (0x01UL << EMC_STATUS_B_Pos)                              /*!< EMC STATUS: B Mask                  */
+#define EMC_STATUS_S_Pos                                      1                                                         /*!< EMC STATUS: S Position              */
+#define EMC_STATUS_S_Msk                                      (0x01UL << EMC_STATUS_S_Pos)                              /*!< EMC STATUS: S Mask                  */
+#define EMC_STATUS_SA_Pos                                     2                                                         /*!< EMC STATUS: SA Position             */
+#define EMC_STATUS_SA_Msk                                     (0x01UL << EMC_STATUS_SA_Pos)                             /*!< EMC STATUS: SA Mask                 */
+
+// ---------------------------------------  EMC_CONFIG  -------------------------------------------
+#define EMC_CONFIG_EM_Pos                                     0                                                         /*!< EMC CONFIG: EM Position             */
+#define EMC_CONFIG_EM_Msk                                     (0x01UL << EMC_CONFIG_EM_Pos)                             /*!< EMC CONFIG: EM Mask                 */
+#define EMC_CONFIG_CR_Pos                                     8                                                         /*!< EMC CONFIG: CR Position             */
+#define EMC_CONFIG_CR_Msk                                     (0x01UL << EMC_CONFIG_CR_Pos)                             /*!< EMC CONFIG: CR Mask                 */
+
+// -----------------------------------  EMC_DYNAMICCONTROL  ---------------------------------------
+#define EMC_DYNAMICCONTROL_CE_Pos                             0                                                         /*!< EMC DYNAMICCONTROL: CE Position     */
+#define EMC_DYNAMICCONTROL_CE_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CE_Pos)                     /*!< EMC DYNAMICCONTROL: CE Mask         */
+#define EMC_DYNAMICCONTROL_CS_Pos                             1                                                         /*!< EMC DYNAMICCONTROL: CS Position     */
+#define EMC_DYNAMICCONTROL_CS_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CS_Pos)                     /*!< EMC DYNAMICCONTROL: CS Mask         */
+#define EMC_DYNAMICCONTROL_SR_Pos                             2                                                         /*!< EMC DYNAMICCONTROL: SR Position     */
+#define EMC_DYNAMICCONTROL_SR_Msk                             (0x01UL << EMC_DYNAMICCONTROL_SR_Pos)                     /*!< EMC DYNAMICCONTROL: SR Mask         */
+#define EMC_DYNAMICCONTROL_MMC_Pos                            5                                                         /*!< EMC DYNAMICCONTROL: MMC Position    */
+#define EMC_DYNAMICCONTROL_MMC_Msk                            (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos)                    /*!< EMC DYNAMICCONTROL: MMC Mask        */
+#define EMC_DYNAMICCONTROL_I_Pos                              7                                                         /*!< EMC DYNAMICCONTROL: I Position      */
+#define EMC_DYNAMICCONTROL_I_Msk                              (0x03UL << EMC_DYNAMICCONTROL_I_Pos)                      /*!< EMC DYNAMICCONTROL: I Mask          */
+#define EMC_DYNAMICCONTROL_DP_Pos                             13                                                        /*!< EMC DYNAMICCONTROL: DP Position     */
+#define EMC_DYNAMICCONTROL_DP_Msk                             (0x01UL << EMC_DYNAMICCONTROL_DP_Pos)                     /*!< EMC DYNAMICCONTROL: DP Mask         */
+
+// -----------------------------------  EMC_DYNAMICREFRESH  ---------------------------------------
+#define EMC_DYNAMICREFRESH_REFRESH_Pos                        0                                                         /*!< EMC DYNAMICREFRESH: REFRESH Position */
+#define EMC_DYNAMICREFRESH_REFRESH_Msk                        (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos)          /*!< EMC DYNAMICREFRESH: REFRESH Mask    */
+
+// ----------------------------------  EMC_DYNAMICREADCONFIG  -------------------------------------
+#define EMC_DYNAMICREADCONFIG_RD_Pos                          0                                                         /*!< EMC DYNAMICREADCONFIG: RD Position  */
+#define EMC_DYNAMICREADCONFIG_RD_Msk                          (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos)                  /*!< EMC DYNAMICREADCONFIG: RD Mask      */
+
+// --------------------------------------  EMC_DYNAMICRP  -----------------------------------------
+#define EMC_DYNAMICRP_tRP_Pos                                 0                                                         /*!< EMC DYNAMICRP: tRP Position         */
+#define EMC_DYNAMICRP_tRP_Msk                                 (0x0fUL << EMC_DYNAMICRP_tRP_Pos)                         /*!< EMC DYNAMICRP: tRP Mask             */
+
+// -------------------------------------  EMC_DYNAMICRAS  -----------------------------------------
+#define EMC_DYNAMICRAS_tRAS_Pos                               0                                                         /*!< EMC DYNAMICRAS: tRAS Position       */
+#define EMC_DYNAMICRAS_tRAS_Msk                               (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos)                       /*!< EMC DYNAMICRAS: tRAS Mask           */
+
+// -------------------------------------  EMC_DYNAMICSREX  ----------------------------------------
+#define EMC_DYNAMICSREX_tSREX_Pos                             0                                                         /*!< EMC DYNAMICSREX: tSREX Position     */
+#define EMC_DYNAMICSREX_tSREX_Msk                             (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos)                     /*!< EMC DYNAMICSREX: tSREX Mask         */
+
+// -------------------------------------  EMC_DYNAMICAPR  -----------------------------------------
+#define EMC_DYNAMICAPR_tAPR_Pos                               0                                                         /*!< EMC DYNAMICAPR: tAPR Position       */
+#define EMC_DYNAMICAPR_tAPR_Msk                               (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos)                       /*!< EMC DYNAMICAPR: tAPR Mask           */
+
+// -------------------------------------  EMC_DYNAMICDAL  -----------------------------------------
+#define EMC_DYNAMICDAL_tDAL_Pos                               0                                                         /*!< EMC DYNAMICDAL: tDAL Position       */
+#define EMC_DYNAMICDAL_tDAL_Msk                               (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos)                       /*!< EMC DYNAMICDAL: tDAL Mask           */
+
+// --------------------------------------  EMC_DYNAMICWR  -----------------------------------------
+#define EMC_DYNAMICWR_tWR_Pos                                 0                                                         /*!< EMC DYNAMICWR: tWR Position         */
+#define EMC_DYNAMICWR_tWR_Msk                                 (0x0fUL << EMC_DYNAMICWR_tWR_Pos)                         /*!< EMC DYNAMICWR: tWR Mask             */
+
+// --------------------------------------  EMC_DYNAMICRC  -----------------------------------------
+#define EMC_DYNAMICRC_tRC_Pos                                 0                                                         /*!< EMC DYNAMICRC: tRC Position         */
+#define EMC_DYNAMICRC_tRC_Msk                                 (0x1fUL << EMC_DYNAMICRC_tRC_Pos)                         /*!< EMC DYNAMICRC: tRC Mask             */
+
+// -------------------------------------  EMC_DYNAMICRFC  -----------------------------------------
+#define EMC_DYNAMICRFC_tRFC_Pos                               0                                                         /*!< EMC DYNAMICRFC: tRFC Position       */
+#define EMC_DYNAMICRFC_tRFC_Msk                               (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos)                       /*!< EMC DYNAMICRFC: tRFC Mask           */
+
+// -------------------------------------  EMC_DYNAMICXSR  -----------------------------------------
+#define EMC_DYNAMICXSR_tXSR_Pos                               0                                                         /*!< EMC DYNAMICXSR: tXSR Position       */
+#define EMC_DYNAMICXSR_tXSR_Msk                               (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos)                       /*!< EMC DYNAMICXSR: tXSR Mask           */
+
+// -------------------------------------  EMC_DYNAMICRRD  -----------------------------------------
+#define EMC_DYNAMICRRD_tRRD_Pos                               0                                                         /*!< EMC DYNAMICRRD: tRRD Position       */
+#define EMC_DYNAMICRRD_tRRD_Msk                               (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos)                       /*!< EMC DYNAMICRRD: tRRD Mask           */
+
+// -------------------------------------  EMC_DYNAMICMRD  -----------------------------------------
+#define EMC_DYNAMICMRD_tMRD_Pos                               0                                                         /*!< EMC DYNAMICMRD: tMRD Position       */
+#define EMC_DYNAMICMRD_tMRD_Msk                               (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos)                       /*!< EMC DYNAMICMRD: tMRD Mask           */
+
+// ---------------------------------  EMC_STATICEXTENDEDWAIT  -------------------------------------
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos               0                                                         /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk               (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */
+
+// -----------------------------------  EMC_DYNAMICCONFIG0  ---------------------------------------
+#define EMC_DYNAMICCONFIG0_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG0: MD Position     */
+#define EMC_DYNAMICCONFIG0_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos)                     /*!< EMC DYNAMICCONFIG0: MD Mask         */
+#define EMC_DYNAMICCONFIG0_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG0: AM0 Position    */
+#define EMC_DYNAMICCONFIG0_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos)                    /*!< EMC DYNAMICCONFIG0: AM0 Mask        */
+#define EMC_DYNAMICCONFIG0_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG0: AM1 Position    */
+#define EMC_DYNAMICCONFIG0_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos)                    /*!< EMC DYNAMICCONFIG0: AM1 Mask        */
+#define EMC_DYNAMICCONFIG0_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG0: B Position      */
+#define EMC_DYNAMICCONFIG0_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_B_Pos)                      /*!< EMC DYNAMICCONFIG0: B Mask          */
+#define EMC_DYNAMICCONFIG0_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG0: P Position      */
+#define EMC_DYNAMICCONFIG0_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_P_Pos)                      /*!< EMC DYNAMICCONFIG0: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS0  ---------------------------------------
+#define EMC_DYNAMICRASCAS0_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS0: RAS Position    */
+#define EMC_DYNAMICRASCAS0_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos)                    /*!< EMC DYNAMICRASCAS0: RAS Mask        */
+#define EMC_DYNAMICRASCAS0_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS0: CAS Position    */
+#define EMC_DYNAMICRASCAS0_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos)                    /*!< EMC DYNAMICRASCAS0: CAS Mask        */
+
+// -----------------------------------  EMC_DYNAMICCONFIG1  ---------------------------------------
+#define EMC_DYNAMICCONFIG1_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG1: MD Position     */
+#define EMC_DYNAMICCONFIG1_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos)                     /*!< EMC DYNAMICCONFIG1: MD Mask         */
+#define EMC_DYNAMICCONFIG1_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG1: AM0 Position    */
+#define EMC_DYNAMICCONFIG1_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos)                    /*!< EMC DYNAMICCONFIG1: AM0 Mask        */
+#define EMC_DYNAMICCONFIG1_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG1: AM1 Position    */
+#define EMC_DYNAMICCONFIG1_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos)                    /*!< EMC DYNAMICCONFIG1: AM1 Mask        */
+#define EMC_DYNAMICCONFIG1_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG1: B Position      */
+#define EMC_DYNAMICCONFIG1_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_B_Pos)                      /*!< EMC DYNAMICCONFIG1: B Mask          */
+#define EMC_DYNAMICCONFIG1_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG1: P Position      */
+#define EMC_DYNAMICCONFIG1_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_P_Pos)                      /*!< EMC DYNAMICCONFIG1: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS1  ---------------------------------------
+#define EMC_DYNAMICRASCAS1_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS1: RAS Position    */
+#define EMC_DYNAMICRASCAS1_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos)                    /*!< EMC DYNAMICRASCAS1: RAS Mask        */
+#define EMC_DYNAMICRASCAS1_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS1: CAS Position    */
+#define EMC_DYNAMICRASCAS1_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos)                    /*!< EMC DYNAMICRASCAS1: CAS Mask        */
+
+// -----------------------------------  EMC_DYNAMICCONFIG2  ---------------------------------------
+#define EMC_DYNAMICCONFIG2_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG2: MD Position     */
+#define EMC_DYNAMICCONFIG2_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos)                     /*!< EMC DYNAMICCONFIG2: MD Mask         */
+#define EMC_DYNAMICCONFIG2_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG2: AM0 Position    */
+#define EMC_DYNAMICCONFIG2_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos)                    /*!< EMC DYNAMICCONFIG2: AM0 Mask        */
+#define EMC_DYNAMICCONFIG2_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG2: AM1 Position    */
+#define EMC_DYNAMICCONFIG2_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos)                    /*!< EMC DYNAMICCONFIG2: AM1 Mask        */
+#define EMC_DYNAMICCONFIG2_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG2: B Position      */
+#define EMC_DYNAMICCONFIG2_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_B_Pos)                      /*!< EMC DYNAMICCONFIG2: B Mask          */
+#define EMC_DYNAMICCONFIG2_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG2: P Position      */
+#define EMC_DYNAMICCONFIG2_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_P_Pos)                      /*!< EMC DYNAMICCONFIG2: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS2  ---------------------------------------
+#define EMC_DYNAMICRASCAS2_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS2: RAS Position    */
+#define EMC_DYNAMICRASCAS2_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos)                    /*!< EMC DYNAMICRASCAS2: RAS Mask        */
+#define EMC_DYNAMICRASCAS2_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS2: CAS Position    */
+#define EMC_DYNAMICRASCAS2_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos)                    /*!< EMC DYNAMICRASCAS2: CAS Mask        */
+
+// -----------------------------------  EMC_DYNAMICCONFIG3  ---------------------------------------
+#define EMC_DYNAMICCONFIG3_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG3: MD Position     */
+#define EMC_DYNAMICCONFIG3_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos)                     /*!< EMC DYNAMICCONFIG3: MD Mask         */
+#define EMC_DYNAMICCONFIG3_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG3: AM0 Position    */
+#define EMC_DYNAMICCONFIG3_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos)                    /*!< EMC DYNAMICCONFIG3: AM0 Mask        */
+#define EMC_DYNAMICCONFIG3_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG3: AM1 Position    */
+#define EMC_DYNAMICCONFIG3_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos)                    /*!< EMC DYNAMICCONFIG3: AM1 Mask        */
+#define EMC_DYNAMICCONFIG3_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG3: B Position      */
+#define EMC_DYNAMICCONFIG3_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_B_Pos)                      /*!< EMC DYNAMICCONFIG3: B Mask          */
+#define EMC_DYNAMICCONFIG3_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG3: P Position      */
+#define EMC_DYNAMICCONFIG3_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_P_Pos)                      /*!< EMC DYNAMICCONFIG3: P Mask          */
+
+// -----------------------------------  EMC_DYNAMICRASCAS3  ---------------------------------------
+#define EMC_DYNAMICRASCAS3_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS3: RAS Position    */
+#define EMC_DYNAMICRASCAS3_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos)                    /*!< EMC DYNAMICRASCAS3: RAS Mask        */
+#define EMC_DYNAMICRASCAS3_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS3: CAS Position    */
+#define EMC_DYNAMICRASCAS3_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos)                    /*!< EMC DYNAMICRASCAS3: CAS Mask        */
+
+// ------------------------------------  EMC_STATICCONFIG0  ---------------------------------------
+#define EMC_STATICCONFIG0_MW_Pos                              0                                                         /*!< EMC STATICCONFIG0: MW Position      */
+#define EMC_STATICCONFIG0_MW_Msk                              (0x03UL << EMC_STATICCONFIG0_MW_Pos)                      /*!< EMC STATICCONFIG0: MW Mask          */
+#define EMC_STATICCONFIG0_PM_Pos                              3                                                         /*!< EMC STATICCONFIG0: PM Position      */
+#define EMC_STATICCONFIG0_PM_Msk                              (0x01UL << EMC_STATICCONFIG0_PM_Pos)                      /*!< EMC STATICCONFIG0: PM Mask          */
+#define EMC_STATICCONFIG0_PC_Pos                              6                                                         /*!< EMC STATICCONFIG0: PC Position      */
+#define EMC_STATICCONFIG0_PC_Msk                              (0x01UL << EMC_STATICCONFIG0_PC_Pos)                      /*!< EMC STATICCONFIG0: PC Mask          */
+#define EMC_STATICCONFIG0_PB_Pos                              7                                                         /*!< EMC STATICCONFIG0: PB Position      */
+#define EMC_STATICCONFIG0_PB_Msk                              (0x01UL << EMC_STATICCONFIG0_PB_Pos)                      /*!< EMC STATICCONFIG0: PB Mask          */
+#define EMC_STATICCONFIG0_EW_Pos                              8                                                         /*!< EMC STATICCONFIG0: EW Position      */
+#define EMC_STATICCONFIG0_EW_Msk                              (0x01UL << EMC_STATICCONFIG0_EW_Pos)                      /*!< EMC STATICCONFIG0: EW Mask          */
+#define EMC_STATICCONFIG0_B_Pos                               19                                                        /*!< EMC STATICCONFIG0: B Position       */
+#define EMC_STATICCONFIG0_B_Msk                               (0x01UL << EMC_STATICCONFIG0_B_Pos)                       /*!< EMC STATICCONFIG0: B Mask           */
+#define EMC_STATICCONFIG0_P_Pos                               20                                                        /*!< EMC STATICCONFIG0: P Position       */
+#define EMC_STATICCONFIG0_P_Msk                               (0x01UL << EMC_STATICCONFIG0_P_Pos)                       /*!< EMC STATICCONFIG0: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN0  ---------------------------------------
+#define EMC_STATICWAITWEN0_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN0: WAITWEN Position */
+#define EMC_STATICWAITWEN0_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos)                /*!< EMC STATICWAITWEN0: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN0  ---------------------------------------
+#define EMC_STATICWAITOEN0_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN0: WAITOEN Position */
+#define EMC_STATICWAITOEN0_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos)                /*!< EMC STATICWAITOEN0: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD0  ---------------------------------------
+#define EMC_STATICWAITRD0_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD0: WAITRD Position  */
+#define EMC_STATICWAITRD0_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos)                  /*!< EMC STATICWAITRD0: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG0  ---------------------------------------
+#define EMC_STATICWAITPAG0_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG0: WAITPAGE Position */
+#define EMC_STATICWAITPAG0_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG0: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR0  ---------------------------------------
+#define EMC_STATICWAITWR0_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR0: WAITWR Position  */
+#define EMC_STATICWAITWR0_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos)                  /*!< EMC STATICWAITWR0: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN0  --------------------------------------
+#define EMC_STATICWAITTURN0_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN0: WAITTURN Position */
+#define EMC_STATICWAITTURN0_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos)              /*!< EMC STATICWAITTURN0: WAITTURN Mask  */
+
+// ------------------------------------  EMC_STATICCONFIG1  ---------------------------------------
+#define EMC_STATICCONFIG1_MW_Pos                              0                                                         /*!< EMC STATICCONFIG1: MW Position      */
+#define EMC_STATICCONFIG1_MW_Msk                              (0x03UL << EMC_STATICCONFIG1_MW_Pos)                      /*!< EMC STATICCONFIG1: MW Mask          */
+#define EMC_STATICCONFIG1_PM_Pos                              3                                                         /*!< EMC STATICCONFIG1: PM Position      */
+#define EMC_STATICCONFIG1_PM_Msk                              (0x01UL << EMC_STATICCONFIG1_PM_Pos)                      /*!< EMC STATICCONFIG1: PM Mask          */
+#define EMC_STATICCONFIG1_PC_Pos                              6                                                         /*!< EMC STATICCONFIG1: PC Position      */
+#define EMC_STATICCONFIG1_PC_Msk                              (0x01UL << EMC_STATICCONFIG1_PC_Pos)                      /*!< EMC STATICCONFIG1: PC Mask          */
+#define EMC_STATICCONFIG1_PB_Pos                              7                                                         /*!< EMC STATICCONFIG1: PB Position      */
+#define EMC_STATICCONFIG1_PB_Msk                              (0x01UL << EMC_STATICCONFIG1_PB_Pos)                      /*!< EMC STATICCONFIG1: PB Mask          */
+#define EMC_STATICCONFIG1_EW_Pos                              8                                                         /*!< EMC STATICCONFIG1: EW Position      */
+#define EMC_STATICCONFIG1_EW_Msk                              (0x01UL << EMC_STATICCONFIG1_EW_Pos)                      /*!< EMC STATICCONFIG1: EW Mask          */
+#define EMC_STATICCONFIG1_B_Pos                               19                                                        /*!< EMC STATICCONFIG1: B Position       */
+#define EMC_STATICCONFIG1_B_Msk                               (0x01UL << EMC_STATICCONFIG1_B_Pos)                       /*!< EMC STATICCONFIG1: B Mask           */
+#define EMC_STATICCONFIG1_P_Pos                               20                                                        /*!< EMC STATICCONFIG1: P Position       */
+#define EMC_STATICCONFIG1_P_Msk                               (0x01UL << EMC_STATICCONFIG1_P_Pos)                       /*!< EMC STATICCONFIG1: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN1  ---------------------------------------
+#define EMC_STATICWAITWEN1_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN1: WAITWEN Position */
+#define EMC_STATICWAITWEN1_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos)                /*!< EMC STATICWAITWEN1: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN1  ---------------------------------------
+#define EMC_STATICWAITOEN1_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN1: WAITOEN Position */
+#define EMC_STATICWAITOEN1_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos)                /*!< EMC STATICWAITOEN1: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD1  ---------------------------------------
+#define EMC_STATICWAITRD1_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD1: WAITRD Position  */
+#define EMC_STATICWAITRD1_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos)                  /*!< EMC STATICWAITRD1: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG1  ---------------------------------------
+#define EMC_STATICWAITPAG1_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG1: WAITPAGE Position */
+#define EMC_STATICWAITPAG1_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG1: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR1  ---------------------------------------
+#define EMC_STATICWAITWR1_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR1: WAITWR Position  */
+#define EMC_STATICWAITWR1_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos)                  /*!< EMC STATICWAITWR1: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN1  --------------------------------------
+#define EMC_STATICWAITTURN1_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN1: WAITTURN Position */
+#define EMC_STATICWAITTURN1_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos)              /*!< EMC STATICWAITTURN1: WAITTURN Mask  */
+
+// ------------------------------------  EMC_STATICCONFIG2  ---------------------------------------
+#define EMC_STATICCONFIG2_MW_Pos                              0                                                         /*!< EMC STATICCONFIG2: MW Position      */
+#define EMC_STATICCONFIG2_MW_Msk                              (0x03UL << EMC_STATICCONFIG2_MW_Pos)                      /*!< EMC STATICCONFIG2: MW Mask          */
+#define EMC_STATICCONFIG2_PM_Pos                              3                                                         /*!< EMC STATICCONFIG2: PM Position      */
+#define EMC_STATICCONFIG2_PM_Msk                              (0x01UL << EMC_STATICCONFIG2_PM_Pos)                      /*!< EMC STATICCONFIG2: PM Mask          */
+#define EMC_STATICCONFIG2_PC_Pos                              6                                                         /*!< EMC STATICCONFIG2: PC Position      */
+#define EMC_STATICCONFIG2_PC_Msk                              (0x01UL << EMC_STATICCONFIG2_PC_Pos)                      /*!< EMC STATICCONFIG2: PC Mask          */
+#define EMC_STATICCONFIG2_PB_Pos                              7                                                         /*!< EMC STATICCONFIG2: PB Position      */
+#define EMC_STATICCONFIG2_PB_Msk                              (0x01UL << EMC_STATICCONFIG2_PB_Pos)                      /*!< EMC STATICCONFIG2: PB Mask          */
+#define EMC_STATICCONFIG2_EW_Pos                              8                                                         /*!< EMC STATICCONFIG2: EW Position      */
+#define EMC_STATICCONFIG2_EW_Msk                              (0x01UL << EMC_STATICCONFIG2_EW_Pos)                      /*!< EMC STATICCONFIG2: EW Mask          */
+#define EMC_STATICCONFIG2_B_Pos                               19                                                        /*!< EMC STATICCONFIG2: B Position       */
+#define EMC_STATICCONFIG2_B_Msk                               (0x01UL << EMC_STATICCONFIG2_B_Pos)                       /*!< EMC STATICCONFIG2: B Mask           */
+#define EMC_STATICCONFIG2_P_Pos                               20                                                        /*!< EMC STATICCONFIG2: P Position       */
+#define EMC_STATICCONFIG2_P_Msk                               (0x01UL << EMC_STATICCONFIG2_P_Pos)                       /*!< EMC STATICCONFIG2: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN2  ---------------------------------------
+#define EMC_STATICWAITWEN2_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN2: WAITWEN Position */
+#define EMC_STATICWAITWEN2_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos)                /*!< EMC STATICWAITWEN2: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN2  ---------------------------------------
+#define EMC_STATICWAITOEN2_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN2: WAITOEN Position */
+#define EMC_STATICWAITOEN2_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos)                /*!< EMC STATICWAITOEN2: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD2  ---------------------------------------
+#define EMC_STATICWAITRD2_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD2: WAITRD Position  */
+#define EMC_STATICWAITRD2_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos)                  /*!< EMC STATICWAITRD2: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG2  ---------------------------------------
+#define EMC_STATICWAITPAG2_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG2: WAITPAGE Position */
+#define EMC_STATICWAITPAG2_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG2: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR2  ---------------------------------------
+#define EMC_STATICWAITWR2_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR2: WAITWR Position  */
+#define EMC_STATICWAITWR2_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos)                  /*!< EMC STATICWAITWR2: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN2  --------------------------------------
+#define EMC_STATICWAITTURN2_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN2: WAITTURN Position */
+#define EMC_STATICWAITTURN2_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos)              /*!< EMC STATICWAITTURN2: WAITTURN Mask  */
+
+// ------------------------------------  EMC_STATICCONFIG3  ---------------------------------------
+#define EMC_STATICCONFIG3_MW_Pos                              0                                                         /*!< EMC STATICCONFIG3: MW Position      */
+#define EMC_STATICCONFIG3_MW_Msk                              (0x03UL << EMC_STATICCONFIG3_MW_Pos)                      /*!< EMC STATICCONFIG3: MW Mask          */
+#define EMC_STATICCONFIG3_PM_Pos                              3                                                         /*!< EMC STATICCONFIG3: PM Position      */
+#define EMC_STATICCONFIG3_PM_Msk                              (0x01UL << EMC_STATICCONFIG3_PM_Pos)                      /*!< EMC STATICCONFIG3: PM Mask          */
+#define EMC_STATICCONFIG3_PC_Pos                              6                                                         /*!< EMC STATICCONFIG3: PC Position      */
+#define EMC_STATICCONFIG3_PC_Msk                              (0x01UL << EMC_STATICCONFIG3_PC_Pos)                      /*!< EMC STATICCONFIG3: PC Mask          */
+#define EMC_STATICCONFIG3_PB_Pos                              7                                                         /*!< EMC STATICCONFIG3: PB Position      */
+#define EMC_STATICCONFIG3_PB_Msk                              (0x01UL << EMC_STATICCONFIG3_PB_Pos)                      /*!< EMC STATICCONFIG3: PB Mask          */
+#define EMC_STATICCONFIG3_EW_Pos                              8                                                         /*!< EMC STATICCONFIG3: EW Position      */
+#define EMC_STATICCONFIG3_EW_Msk                              (0x01UL << EMC_STATICCONFIG3_EW_Pos)                      /*!< EMC STATICCONFIG3: EW Mask          */
+#define EMC_STATICCONFIG3_B_Pos                               19                                                        /*!< EMC STATICCONFIG3: B Position       */
+#define EMC_STATICCONFIG3_B_Msk                               (0x01UL << EMC_STATICCONFIG3_B_Pos)                       /*!< EMC STATICCONFIG3: B Mask           */
+#define EMC_STATICCONFIG3_P_Pos                               20                                                        /*!< EMC STATICCONFIG3: P Position       */
+#define EMC_STATICCONFIG3_P_Msk                               (0x01UL << EMC_STATICCONFIG3_P_Pos)                       /*!< EMC STATICCONFIG3: P Mask           */
+
+// -----------------------------------  EMC_STATICWAITWEN3  ---------------------------------------
+#define EMC_STATICWAITWEN3_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN3: WAITWEN Position */
+#define EMC_STATICWAITWEN3_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos)                /*!< EMC STATICWAITWEN3: WAITWEN Mask    */
+
+// -----------------------------------  EMC_STATICWAITOEN3  ---------------------------------------
+#define EMC_STATICWAITOEN3_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN3: WAITOEN Position */
+#define EMC_STATICWAITOEN3_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos)                /*!< EMC STATICWAITOEN3: WAITOEN Mask    */
+
+// ------------------------------------  EMC_STATICWAITRD3  ---------------------------------------
+#define EMC_STATICWAITRD3_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD3: WAITRD Position  */
+#define EMC_STATICWAITRD3_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos)                  /*!< EMC STATICWAITRD3: WAITRD Mask      */
+
+// -----------------------------------  EMC_STATICWAITPAG3  ---------------------------------------
+#define EMC_STATICWAITPAG3_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG3: WAITPAGE Position */
+#define EMC_STATICWAITPAG3_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG3: WAITPAGE Mask   */
+
+// ------------------------------------  EMC_STATICWAITWR3  ---------------------------------------
+#define EMC_STATICWAITWR3_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR3: WAITWR Position  */
+#define EMC_STATICWAITWR3_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos)                  /*!< EMC STATICWAITWR3: WAITWR Mask      */
+
+// -----------------------------------  EMC_STATICWAITTURN3  --------------------------------------
+#define EMC_STATICWAITTURN3_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN3: WAITTURN Position */
+#define EMC_STATICWAITTURN3_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos)              /*!< EMC STATICWAITTURN3: WAITTURN Mask  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 USB0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  USB0_CAPLENGTH  -----------------------------------------
+#define USB0_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB0 CAPLENGTH: CAPLENGTH Position  */
+#define USB0_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB0 CAPLENGTH: CAPLENGTH Mask      */
+#define USB0_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB0 CAPLENGTH: HCIVERSION Position */
+#define USB0_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos)           /*!< USB0 CAPLENGTH: HCIVERSION Mask     */
+
+// -------------------------------------  USB0_HCSPARAMS  -----------------------------------------
+#define USB0_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB0 HCSPARAMS: N_PORTS Position    */
+#define USB0_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos)                    /*!< USB0 HCSPARAMS: N_PORTS Mask        */
+#define USB0_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB0 HCSPARAMS: PPC Position        */
+#define USB0_HCSPARAMS_PPC_Msk                                (0x01UL << USB0_HCSPARAMS_PPC_Pos)                        /*!< USB0 HCSPARAMS: PPC Mask            */
+#define USB0_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB0 HCSPARAMS: N_PCC Position      */
+#define USB0_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos)                      /*!< USB0 HCSPARAMS: N_PCC Mask          */
+#define USB0_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB0 HCSPARAMS: N_CC Position       */
+#define USB0_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB0_HCSPARAMS_N_CC_Pos)                       /*!< USB0 HCSPARAMS: N_CC Mask           */
+#define USB0_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB0 HCSPARAMS: PI Position         */
+#define USB0_HCSPARAMS_PI_Msk                                 (0x01UL << USB0_HCSPARAMS_PI_Pos)                         /*!< USB0 HCSPARAMS: PI Mask             */
+#define USB0_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB0 HCSPARAMS: N_PTT Position      */
+#define USB0_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos)                      /*!< USB0 HCSPARAMS: N_PTT Mask          */
+#define USB0_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB0 HCSPARAMS: N_TT Position       */
+#define USB0_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB0_HCSPARAMS_N_TT_Pos)                       /*!< USB0 HCSPARAMS: N_TT Mask           */
+
+// -------------------------------------  USB0_HCCPARAMS  -----------------------------------------
+#define USB0_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB0 HCCPARAMS: ADC Position        */
+#define USB0_HCCPARAMS_ADC_Msk                                (0x01UL << USB0_HCCPARAMS_ADC_Pos)                        /*!< USB0 HCCPARAMS: ADC Mask            */
+#define USB0_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB0 HCCPARAMS: PFL Position        */
+#define USB0_HCCPARAMS_PFL_Msk                                (0x01UL << USB0_HCCPARAMS_PFL_Pos)                        /*!< USB0 HCCPARAMS: PFL Mask            */
+#define USB0_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB0 HCCPARAMS: ASP Position        */
+#define USB0_HCCPARAMS_ASP_Msk                                (0x01UL << USB0_HCCPARAMS_ASP_Pos)                        /*!< USB0 HCCPARAMS: ASP Mask            */
+#define USB0_HCCPARAMS_IST_Pos                                4                                                         /*!< USB0 HCCPARAMS: IST Position        */
+#define USB0_HCCPARAMS_IST_Msk                                (0x0fUL << USB0_HCCPARAMS_IST_Pos)                        /*!< USB0 HCCPARAMS: IST Mask            */
+#define USB0_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB0 HCCPARAMS: EECP Position       */
+#define USB0_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos)                 /*!< USB0 HCCPARAMS: EECP Mask           */
+
+// -------------------------------------  USB0_DCIVERSION  ----------------------------------------
+#define USB0_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB0 DCIVERSION: DCIVERSION Position */
+#define USB0_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos)          /*!< USB0 DCIVERSION: DCIVERSION Mask    */
+
+// --------------------------------------  USB0_USBCMD_D  -----------------------------------------
+#define USB0_USBCMD_D_RS_Pos                                  0                                                         /*!< USB0 USBCMD_D: RS Position          */
+#define USB0_USBCMD_D_RS_Msk                                  (0x01UL << USB0_USBCMD_D_RS_Pos)                          /*!< USB0 USBCMD_D: RS Mask              */
+#define USB0_USBCMD_D_RST_Pos                                 1                                                         /*!< USB0 USBCMD_D: RST Position         */
+#define USB0_USBCMD_D_RST_Msk                                 (0x01UL << USB0_USBCMD_D_RST_Pos)                         /*!< USB0 USBCMD_D: RST Mask             */
+#define USB0_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB0 USBCMD_D: SUTW Position        */
+#define USB0_USBCMD_D_SUTW_Msk                                (0x01UL << USB0_USBCMD_D_SUTW_Pos)                        /*!< USB0 USBCMD_D: SUTW Mask            */
+#define USB0_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB0 USBCMD_D: ATDTW Position       */
+#define USB0_USBCMD_D_ATDTW_Msk                               (0x01UL << USB0_USBCMD_D_ATDTW_Pos)                       /*!< USB0 USBCMD_D: ATDTW Mask           */
+#define USB0_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_D: ITC Position         */
+#define USB0_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_D_ITC_Pos)                   /*!< USB0 USBCMD_D: ITC Mask             */
+
+// --------------------------------------  USB0_USBCMD_H  -----------------------------------------
+#define USB0_USBCMD_H_RS_Pos                                  0                                                         /*!< USB0 USBCMD_H: RS Position          */
+#define USB0_USBCMD_H_RS_Msk                                  (0x01UL << USB0_USBCMD_H_RS_Pos)                          /*!< USB0 USBCMD_H: RS Mask              */
+#define USB0_USBCMD_H_RST_Pos                                 1                                                         /*!< USB0 USBCMD_H: RST Position         */
+#define USB0_USBCMD_H_RST_Msk                                 (0x01UL << USB0_USBCMD_H_RST_Pos)                         /*!< USB0 USBCMD_H: RST Mask             */
+#define USB0_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB0 USBCMD_H: FS0 Position         */
+#define USB0_USBCMD_H_FS0_Msk                                 (0x01UL << USB0_USBCMD_H_FS0_Pos)                         /*!< USB0 USBCMD_H: FS0 Mask             */
+#define USB0_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB0 USBCMD_H: FS1 Position         */
+#define USB0_USBCMD_H_FS1_Msk                                 (0x01UL << USB0_USBCMD_H_FS1_Pos)                         /*!< USB0 USBCMD_H: FS1 Mask             */
+#define USB0_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB0 USBCMD_H: PSE Position         */
+#define USB0_USBCMD_H_PSE_Msk                                 (0x01UL << USB0_USBCMD_H_PSE_Pos)                         /*!< USB0 USBCMD_H: PSE Mask             */
+#define USB0_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB0 USBCMD_H: ASE Position         */
+#define USB0_USBCMD_H_ASE_Msk                                 (0x01UL << USB0_USBCMD_H_ASE_Pos)                         /*!< USB0 USBCMD_H: ASE Mask             */
+#define USB0_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB0 USBCMD_H: IAA Position         */
+#define USB0_USBCMD_H_IAA_Msk                                 (0x01UL << USB0_USBCMD_H_IAA_Pos)                         /*!< USB0 USBCMD_H: IAA Mask             */
+#define USB0_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB0 USBCMD_H: ASP1_0 Position      */
+#define USB0_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB0_USBCMD_H_ASP1_0_Pos)                      /*!< USB0 USBCMD_H: ASP1_0 Mask          */
+#define USB0_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB0 USBCMD_H: ASPE Position        */
+#define USB0_USBCMD_H_ASPE_Msk                                (0x01UL << USB0_USBCMD_H_ASPE_Pos)                        /*!< USB0 USBCMD_H: ASPE Mask            */
+#define USB0_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB0 USBCMD_H: FS2 Position         */
+#define USB0_USBCMD_H_FS2_Msk                                 (0x01UL << USB0_USBCMD_H_FS2_Pos)                         /*!< USB0 USBCMD_H: FS2 Mask             */
+#define USB0_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_H: ITC Position         */
+#define USB0_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_H_ITC_Pos)                   /*!< USB0 USBCMD_H: ITC Mask             */
+
+// --------------------------------------  USB0_USBSTS_D  -----------------------------------------
+#define USB0_USBSTS_D_UI_Pos                                  0                                                         /*!< USB0 USBSTS_D: UI Position          */
+#define USB0_USBSTS_D_UI_Msk                                  (0x01UL << USB0_USBSTS_D_UI_Pos)                          /*!< USB0 USBSTS_D: UI Mask              */
+#define USB0_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_D: UEI Position         */
+#define USB0_USBSTS_D_UEI_Msk                                 (0x01UL << USB0_USBSTS_D_UEI_Pos)                         /*!< USB0 USBSTS_D: UEI Mask             */
+#define USB0_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_D: PCI Position         */
+#define USB0_USBSTS_D_PCI_Msk                                 (0x01UL << USB0_USBSTS_D_PCI_Pos)                         /*!< USB0 USBSTS_D: PCI Mask             */
+#define USB0_USBSTS_D_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_D: AAI Position         */
+#define USB0_USBSTS_D_AAI_Msk                                 (0x01UL << USB0_USBSTS_D_AAI_Pos)                         /*!< USB0 USBSTS_D: AAI Mask             */
+#define USB0_USBSTS_D_URI_Pos                                 6                                                         /*!< USB0 USBSTS_D: URI Position         */
+#define USB0_USBSTS_D_URI_Msk                                 (0x01UL << USB0_USBSTS_D_URI_Pos)                         /*!< USB0 USBSTS_D: URI Mask             */
+#define USB0_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_D: SRI Position         */
+#define USB0_USBSTS_D_SRI_Msk                                 (0x01UL << USB0_USBSTS_D_SRI_Pos)                         /*!< USB0 USBSTS_D: SRI Mask             */
+#define USB0_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB0 USBSTS_D: SLI Position         */
+#define USB0_USBSTS_D_SLI_Msk                                 (0x01UL << USB0_USBSTS_D_SLI_Pos)                         /*!< USB0 USBSTS_D: SLI Mask             */
+#define USB0_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB0 USBSTS_D: NAKI Position        */
+#define USB0_USBSTS_D_NAKI_Msk                                (0x01UL << USB0_USBSTS_D_NAKI_Pos)                        /*!< USB0 USBSTS_D: NAKI Mask            */
+
+// --------------------------------------  USB0_USBSTS_H  -----------------------------------------
+#define USB0_USBSTS_H_UI_Pos                                  0                                                         /*!< USB0 USBSTS_H: UI Position          */
+#define USB0_USBSTS_H_UI_Msk                                  (0x01UL << USB0_USBSTS_H_UI_Pos)                          /*!< USB0 USBSTS_H: UI Mask              */
+#define USB0_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_H: UEI Position         */
+#define USB0_USBSTS_H_UEI_Msk                                 (0x01UL << USB0_USBSTS_H_UEI_Pos)                         /*!< USB0 USBSTS_H: UEI Mask             */
+#define USB0_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_H: PCI Position         */
+#define USB0_USBSTS_H_PCI_Msk                                 (0x01UL << USB0_USBSTS_H_PCI_Pos)                         /*!< USB0 USBSTS_H: PCI Mask             */
+#define USB0_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB0 USBSTS_H: FRI Position         */
+#define USB0_USBSTS_H_FRI_Msk                                 (0x01UL << USB0_USBSTS_H_FRI_Pos)                         /*!< USB0 USBSTS_H: FRI Mask             */
+#define USB0_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_H: AAI Position         */
+#define USB0_USBSTS_H_AAI_Msk                                 (0x01UL << USB0_USBSTS_H_AAI_Pos)                         /*!< USB0 USBSTS_H: AAI Mask             */
+#define USB0_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_H: SRI Position         */
+#define USB0_USBSTS_H_SRI_Msk                                 (0x01UL << USB0_USBSTS_H_SRI_Pos)                         /*!< USB0 USBSTS_H: SRI Mask             */
+#define USB0_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB0 USBSTS_H: HCH Position         */
+#define USB0_USBSTS_H_HCH_Msk                                 (0x01UL << USB0_USBSTS_H_HCH_Pos)                         /*!< USB0 USBSTS_H: HCH Mask             */
+#define USB0_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB0 USBSTS_H: RCL Position         */
+#define USB0_USBSTS_H_RCL_Msk                                 (0x01UL << USB0_USBSTS_H_RCL_Pos)                         /*!< USB0 USBSTS_H: RCL Mask             */
+#define USB0_USBSTS_H_PS_Pos                                  14                                                        /*!< USB0 USBSTS_H: PS Position          */
+#define USB0_USBSTS_H_PS_Msk                                  (0x01UL << USB0_USBSTS_H_PS_Pos)                          /*!< USB0 USBSTS_H: PS Mask              */
+#define USB0_USBSTS_H_AS_Pos                                  15                                                        /*!< USB0 USBSTS_H: AS Position          */
+#define USB0_USBSTS_H_AS_Msk                                  (0x01UL << USB0_USBSTS_H_AS_Pos)                          /*!< USB0 USBSTS_H: AS Mask              */
+#define USB0_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB0 USBSTS_H: UAI Position         */
+#define USB0_USBSTS_H_UAI_Msk                                 (0x01UL << USB0_USBSTS_H_UAI_Pos)                         /*!< USB0 USBSTS_H: UAI Mask             */
+#define USB0_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB0 USBSTS_H: UPI Position         */
+#define USB0_USBSTS_H_UPI_Msk                                 (0x01UL << USB0_USBSTS_H_UPI_Pos)                         /*!< USB0 USBSTS_H: UPI Mask             */
+
+// -------------------------------------  USB0_USBINTR_D  -----------------------------------------
+#define USB0_USBINTR_D_UE_Pos                                 0                                                         /*!< USB0 USBINTR_D: UE Position         */
+#define USB0_USBINTR_D_UE_Msk                                 (0x01UL << USB0_USBINTR_D_UE_Pos)                         /*!< USB0 USBINTR_D: UE Mask             */
+#define USB0_USBINTR_D_UEE_Pos                                1                                                         /*!< USB0 USBINTR_D: UEE Position        */
+#define USB0_USBINTR_D_UEE_Msk                                (0x01UL << USB0_USBINTR_D_UEE_Pos)                        /*!< USB0 USBINTR_D: UEE Mask            */
+#define USB0_USBINTR_D_PCE_Pos                                2                                                         /*!< USB0 USBINTR_D: PCE Position        */
+#define USB0_USBINTR_D_PCE_Msk                                (0x01UL << USB0_USBINTR_D_PCE_Pos)                        /*!< USB0 USBINTR_D: PCE Mask            */
+#define USB0_USBINTR_D_URE_Pos                                6                                                         /*!< USB0 USBINTR_D: URE Position        */
+#define USB0_USBINTR_D_URE_Msk                                (0x01UL << USB0_USBINTR_D_URE_Pos)                        /*!< USB0 USBINTR_D: URE Mask            */
+#define USB0_USBINTR_D_SRE_Pos                                7                                                         /*!< USB0 USBINTR_D: SRE Position        */
+#define USB0_USBINTR_D_SRE_Msk                                (0x01UL << USB0_USBINTR_D_SRE_Pos)                        /*!< USB0 USBINTR_D: SRE Mask            */
+#define USB0_USBINTR_D_SLE_Pos                                8                                                         /*!< USB0 USBINTR_D: SLE Position        */
+#define USB0_USBINTR_D_SLE_Msk                                (0x01UL << USB0_USBINTR_D_SLE_Pos)                        /*!< USB0 USBINTR_D: SLE Mask            */
+#define USB0_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB0 USBINTR_D: NAKE Position       */
+#define USB0_USBINTR_D_NAKE_Msk                               (0x01UL << USB0_USBINTR_D_NAKE_Pos)                       /*!< USB0 USBINTR_D: NAKE Mask           */
+
+// -------------------------------------  USB0_USBINTR_H  -----------------------------------------
+#define USB0_USBINTR_H_UE_Pos                                 0                                                         /*!< USB0 USBINTR_H: UE Position         */
+#define USB0_USBINTR_H_UE_Msk                                 (0x01UL << USB0_USBINTR_H_UE_Pos)                         /*!< USB0 USBINTR_H: UE Mask             */
+#define USB0_USBINTR_H_UEE_Pos                                1                                                         /*!< USB0 USBINTR_H: UEE Position        */
+#define USB0_USBINTR_H_UEE_Msk                                (0x01UL << USB0_USBINTR_H_UEE_Pos)                        /*!< USB0 USBINTR_H: UEE Mask            */
+#define USB0_USBINTR_H_PCE_Pos                                2                                                         /*!< USB0 USBINTR_H: PCE Position        */
+#define USB0_USBINTR_H_PCE_Msk                                (0x01UL << USB0_USBINTR_H_PCE_Pos)                        /*!< USB0 USBINTR_H: PCE Mask            */
+#define USB0_USBINTR_H_FRE_Pos                                3                                                         /*!< USB0 USBINTR_H: FRE Position        */
+#define USB0_USBINTR_H_FRE_Msk                                (0x01UL << USB0_USBINTR_H_FRE_Pos)                        /*!< USB0 USBINTR_H: FRE Mask            */
+#define USB0_USBINTR_H_AAE_Pos                                5                                                         /*!< USB0 USBINTR_H: AAE Position        */
+#define USB0_USBINTR_H_AAE_Msk                                (0x01UL << USB0_USBINTR_H_AAE_Pos)                        /*!< USB0 USBINTR_H: AAE Mask            */
+#define USB0_USBINTR_H_SRE_Pos                                7                                                         /*!< USB0 USBINTR_H: SRE Position        */
+#define USB0_USBINTR_H_SRE_Msk                                (0x01UL << USB0_USBINTR_H_SRE_Pos)                        /*!< USB0 USBINTR_H: SRE Mask            */
+#define USB0_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB0 USBINTR_H: UAIE Position       */
+#define USB0_USBINTR_H_UAIE_Msk                               (0x01UL << USB0_USBINTR_H_UAIE_Pos)                       /*!< USB0 USBINTR_H: UAIE Mask           */
+#define USB0_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB0 USBINTR_H: UPIA Position       */
+#define USB0_USBINTR_H_UPIA_Msk                               (0x01UL << USB0_USBINTR_H_UPIA_Pos)                       /*!< USB0 USBINTR_H: UPIA Mask           */
+
+// -------------------------------------  USB0_FRINDEX_D  -----------------------------------------
+#define USB0_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */
+#define USB0_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask     */
+#define USB0_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */
+#define USB0_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask    */
+
+// -------------------------------------  USB0_FRINDEX_H  -----------------------------------------
+#define USB0_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */
+#define USB0_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask     */
+#define USB0_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */
+#define USB0_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask    */
+
+// -------------------------------------  USB0_DEVICEADDR  ----------------------------------------
+#define USB0_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB0 DEVICEADDR: USBADRA Position   */
+#define USB0_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB0_DEVICEADDR_USBADRA_Pos)                   /*!< USB0 DEVICEADDR: USBADRA Mask       */
+#define USB0_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB0 DEVICEADDR: USBADR Position    */
+#define USB0_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB0_DEVICEADDR_USBADR_Pos)                    /*!< USB0 DEVICEADDR: USBADR Mask        */
+
+// ----------------------------------  USB0_PERIODICLISTBASE  -------------------------------------
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ----------------------------------  USB0_ENDPOINTLISTADDR  -------------------------------------
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// -----------------------------------  USB0_ASYNCLISTADDR  ---------------------------------------
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// ---------------------------------------  USB0_TTCTRL  ------------------------------------------
+#define USB0_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB0 TTCTRL: TTHA Position          */
+#define USB0_TTCTRL_TTHA_Msk                                  (0x7fUL << USB0_TTCTRL_TTHA_Pos)                          /*!< USB0 TTCTRL: TTHA Mask              */
+
+// -------------------------------------  USB0_BURSTSIZE  -----------------------------------------
+#define USB0_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB0 BURSTSIZE: RXPBURST Position   */
+#define USB0_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos)             /*!< USB0 BURSTSIZE: RXPBURST Mask       */
+#define USB0_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB0 BURSTSIZE: TXPBURST Position   */
+#define USB0_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos)             /*!< USB0 BURSTSIZE: TXPBURST Mask       */
+
+// ------------------------------------  USB0_TXFILLTUNING  ---------------------------------------
+#define USB0_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB0 TXFILLTUNING: TXSCHOH Position */
+#define USB0_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB0 TXFILLTUNING: TXSCHOH Mask     */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// -------------------------------------  USB0_BINTERVAL  -----------------------------------------
+#define USB0_BINTERVAL_BINT_Pos                               0                                                         /*!< USB0 BINTERVAL: BINT Position       */
+#define USB0_BINTERVAL_BINT_Msk                               (0x0fUL << USB0_BINTERVAL_BINT_Pos)                       /*!< USB0 BINTERVAL: BINT Mask           */
+
+// --------------------------------------  USB0_ENDPTNAK  -----------------------------------------
+#define USB0_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB0 ENDPTNAK: EPRN0 Position       */
+#define USB0_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN0_Pos)                       /*!< USB0 ENDPTNAK: EPRN0 Mask           */
+#define USB0_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB0 ENDPTNAK: EPRN1 Position       */
+#define USB0_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN1_Pos)                       /*!< USB0 ENDPTNAK: EPRN1 Mask           */
+#define USB0_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB0 ENDPTNAK: EPRN2 Position       */
+#define USB0_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN2_Pos)                       /*!< USB0 ENDPTNAK: EPRN2 Mask           */
+#define USB0_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB0 ENDPTNAK: EPRN3 Position       */
+#define USB0_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN3_Pos)                       /*!< USB0 ENDPTNAK: EPRN3 Mask           */
+#define USB0_ENDPTNAK_EPRN4_Pos                               4                                                         /*!< USB0 ENDPTNAK: EPRN4 Position       */
+#define USB0_ENDPTNAK_EPRN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN4_Pos)                       /*!< USB0 ENDPTNAK: EPRN4 Mask           */
+#define USB0_ENDPTNAK_EPRN5_Pos                               5                                                         /*!< USB0 ENDPTNAK: EPRN5 Position       */
+#define USB0_ENDPTNAK_EPRN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN5_Pos)                       /*!< USB0 ENDPTNAK: EPRN5 Mask           */
+#define USB0_ENDPTNAK_EPTN0_Pos                               16                                                        /*!< USB0 ENDPTNAK: EPTN0 Position       */
+#define USB0_ENDPTNAK_EPTN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN0_Pos)                       /*!< USB0 ENDPTNAK: EPTN0 Mask           */
+#define USB0_ENDPTNAK_EPTN1_Pos                               17                                                        /*!< USB0 ENDPTNAK: EPTN1 Position       */
+#define USB0_ENDPTNAK_EPTN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN1_Pos)                       /*!< USB0 ENDPTNAK: EPTN1 Mask           */
+#define USB0_ENDPTNAK_EPTN2_Pos                               18                                                        /*!< USB0 ENDPTNAK: EPTN2 Position       */
+#define USB0_ENDPTNAK_EPTN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN2_Pos)                       /*!< USB0 ENDPTNAK: EPTN2 Mask           */
+#define USB0_ENDPTNAK_EPTN3_Pos                               19                                                        /*!< USB0 ENDPTNAK: EPTN3 Position       */
+#define USB0_ENDPTNAK_EPTN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN3_Pos)                       /*!< USB0 ENDPTNAK: EPTN3 Mask           */
+#define USB0_ENDPTNAK_EPTN4_Pos                               20                                                        /*!< USB0 ENDPTNAK: EPTN4 Position       */
+#define USB0_ENDPTNAK_EPTN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN4_Pos)                       /*!< USB0 ENDPTNAK: EPTN4 Mask           */
+#define USB0_ENDPTNAK_EPTN5_Pos                               21                                                        /*!< USB0 ENDPTNAK: EPTN5 Position       */
+#define USB0_ENDPTNAK_EPTN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN5_Pos)                       /*!< USB0 ENDPTNAK: EPTN5 Mask           */
+
+// -------------------------------------  USB0_ENDPTNAKEN  ----------------------------------------
+#define USB0_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB0 ENDPTNAKEN: EPRNE0 Position    */
+#define USB0_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE0 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB0 ENDPTNAKEN: EPRNE1 Position    */
+#define USB0_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE1 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB0 ENDPTNAKEN: EPRNE2 Position    */
+#define USB0_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE2 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB0 ENDPTNAKEN: EPRNE3 Position    */
+#define USB0_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE3 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE4_Pos                            4                                                         /*!< USB0 ENDPTNAKEN: EPRNE4 Position    */
+#define USB0_ENDPTNAKEN_EPRNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE4 Mask        */
+#define USB0_ENDPTNAKEN_EPRNE5_Pos                            5                                                         /*!< USB0 ENDPTNAKEN: EPRNE5 Position    */
+#define USB0_ENDPTNAKEN_EPRNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE5 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE0_Pos                            16                                                        /*!< USB0 ENDPTNAKEN: EPTNE0 Position    */
+#define USB0_ENDPTNAKEN_EPTNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE0 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE1_Pos                            17                                                        /*!< USB0 ENDPTNAKEN: EPTNE1 Position    */
+#define USB0_ENDPTNAKEN_EPTNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE1 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE2_Pos                            18                                                        /*!< USB0 ENDPTNAKEN: EPTNE2 Position    */
+#define USB0_ENDPTNAKEN_EPTNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE2 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE3_Pos                            19                                                        /*!< USB0 ENDPTNAKEN: EPTNE3 Position    */
+#define USB0_ENDPTNAKEN_EPTNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE3 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE4_Pos                            20                                                        /*!< USB0 ENDPTNAKEN: EPTNE4 Position    */
+#define USB0_ENDPTNAKEN_EPTNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE4 Mask        */
+#define USB0_ENDPTNAKEN_EPTNE5_Pos                            21                                                        /*!< USB0 ENDPTNAKEN: EPTNE5 Position    */
+#define USB0_ENDPTNAKEN_EPTNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE5 Mask        */
+
+// -------------------------------------  USB0_PORTSC1_D  -----------------------------------------
+#define USB0_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_D: CCS Position        */
+#define USB0_PORTSC1_D_CCS_Msk                                (0x01UL << USB0_PORTSC1_D_CCS_Pos)                        /*!< USB0 PORTSC1_D: CCS Mask            */
+#define USB0_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_D: PE Position         */
+#define USB0_PORTSC1_D_PE_Msk                                 (0x01UL << USB0_PORTSC1_D_PE_Pos)                         /*!< USB0 PORTSC1_D: PE Mask             */
+#define USB0_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_D: PEC Position        */
+#define USB0_PORTSC1_D_PEC_Msk                                (0x01UL << USB0_PORTSC1_D_PEC_Pos)                        /*!< USB0 PORTSC1_D: PEC Mask            */
+#define USB0_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_D: FPR Position        */
+#define USB0_PORTSC1_D_FPR_Msk                                (0x01UL << USB0_PORTSC1_D_FPR_Pos)                        /*!< USB0 PORTSC1_D: FPR Mask            */
+#define USB0_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_D: SUSP Position       */
+#define USB0_PORTSC1_D_SUSP_Msk                               (0x01UL << USB0_PORTSC1_D_SUSP_Pos)                       /*!< USB0 PORTSC1_D: SUSP Mask           */
+#define USB0_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_D: PR Position         */
+#define USB0_PORTSC1_D_PR_Msk                                 (0x01UL << USB0_PORTSC1_D_PR_Pos)                         /*!< USB0 PORTSC1_D: PR Mask             */
+#define USB0_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_D: HSP Position        */
+#define USB0_PORTSC1_D_HSP_Msk                                (0x01UL << USB0_PORTSC1_D_HSP_Pos)                        /*!< USB0 PORTSC1_D: HSP Mask            */
+#define USB0_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_D: PIC1_0 Position     */
+#define USB0_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos)                     /*!< USB0 PORTSC1_D: PIC1_0 Mask         */
+#define USB0_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_D: PTC3_0 Position     */
+#define USB0_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos)                     /*!< USB0 PORTSC1_D: PTC3_0 Mask         */
+#define USB0_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_D: PHCD Position       */
+#define USB0_PORTSC1_D_PHCD_Msk                               (0x01UL << USB0_PORTSC1_D_PHCD_Pos)                       /*!< USB0 PORTSC1_D: PHCD Mask           */
+#define USB0_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_D: PFSC Position       */
+#define USB0_PORTSC1_D_PFSC_Msk                               (0x01UL << USB0_PORTSC1_D_PFSC_Pos)                       /*!< USB0 PORTSC1_D: PFSC Mask           */
+#define USB0_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_D: PSPD Position       */
+#define USB0_PORTSC1_D_PSPD_Msk                               (0x03UL << USB0_PORTSC1_D_PSPD_Pos)                       /*!< USB0 PORTSC1_D: PSPD Mask           */
+
+// -------------------------------------  USB0_PORTSC1_H  -----------------------------------------
+#define USB0_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_H: CCS Position        */
+#define USB0_PORTSC1_H_CCS_Msk                                (0x01UL << USB0_PORTSC1_H_CCS_Pos)                        /*!< USB0 PORTSC1_H: CCS Mask            */
+#define USB0_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB0 PORTSC1_H: CSC Position        */
+#define USB0_PORTSC1_H_CSC_Msk                                (0x01UL << USB0_PORTSC1_H_CSC_Pos)                        /*!< USB0 PORTSC1_H: CSC Mask            */
+#define USB0_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_H: PE Position         */
+#define USB0_PORTSC1_H_PE_Msk                                 (0x01UL << USB0_PORTSC1_H_PE_Pos)                         /*!< USB0 PORTSC1_H: PE Mask             */
+#define USB0_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_H: PEC Position        */
+#define USB0_PORTSC1_H_PEC_Msk                                (0x01UL << USB0_PORTSC1_H_PEC_Pos)                        /*!< USB0 PORTSC1_H: PEC Mask            */
+#define USB0_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB0 PORTSC1_H: OCA Position        */
+#define USB0_PORTSC1_H_OCA_Msk                                (0x01UL << USB0_PORTSC1_H_OCA_Pos)                        /*!< USB0 PORTSC1_H: OCA Mask            */
+#define USB0_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB0 PORTSC1_H: OCC Position        */
+#define USB0_PORTSC1_H_OCC_Msk                                (0x01UL << USB0_PORTSC1_H_OCC_Pos)                        /*!< USB0 PORTSC1_H: OCC Mask            */
+#define USB0_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_H: FPR Position        */
+#define USB0_PORTSC1_H_FPR_Msk                                (0x01UL << USB0_PORTSC1_H_FPR_Pos)                        /*!< USB0 PORTSC1_H: FPR Mask            */
+#define USB0_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_H: SUSP Position       */
+#define USB0_PORTSC1_H_SUSP_Msk                               (0x01UL << USB0_PORTSC1_H_SUSP_Pos)                       /*!< USB0 PORTSC1_H: SUSP Mask           */
+#define USB0_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_H: PR Position         */
+#define USB0_PORTSC1_H_PR_Msk                                 (0x01UL << USB0_PORTSC1_H_PR_Pos)                         /*!< USB0 PORTSC1_H: PR Mask             */
+#define USB0_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_H: HSP Position        */
+#define USB0_PORTSC1_H_HSP_Msk                                (0x01UL << USB0_PORTSC1_H_HSP_Pos)                        /*!< USB0 PORTSC1_H: HSP Mask            */
+#define USB0_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB0 PORTSC1_H: LS Position         */
+#define USB0_PORTSC1_H_LS_Msk                                 (0x03UL << USB0_PORTSC1_H_LS_Pos)                         /*!< USB0 PORTSC1_H: LS Mask             */
+#define USB0_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB0 PORTSC1_H: PP Position         */
+#define USB0_PORTSC1_H_PP_Msk                                 (0x01UL << USB0_PORTSC1_H_PP_Pos)                         /*!< USB0 PORTSC1_H: PP Mask             */
+#define USB0_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_H: PIC1_0 Position     */
+#define USB0_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos)                     /*!< USB0 PORTSC1_H: PIC1_0 Mask         */
+#define USB0_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_H: PTC3_0 Position     */
+#define USB0_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos)                     /*!< USB0 PORTSC1_H: PTC3_0 Mask         */
+#define USB0_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB0 PORTSC1_H: WKCN Position       */
+#define USB0_PORTSC1_H_WKCN_Msk                               (0x01UL << USB0_PORTSC1_H_WKCN_Pos)                       /*!< USB0 PORTSC1_H: WKCN Mask           */
+#define USB0_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB0 PORTSC1_H: WKDC Position       */
+#define USB0_PORTSC1_H_WKDC_Msk                               (0x01UL << USB0_PORTSC1_H_WKDC_Pos)                       /*!< USB0 PORTSC1_H: WKDC Mask           */
+#define USB0_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB0 PORTSC1_H: WKOC Position       */
+#define USB0_PORTSC1_H_WKOC_Msk                               (0x01UL << USB0_PORTSC1_H_WKOC_Pos)                       /*!< USB0 PORTSC1_H: WKOC Mask           */
+#define USB0_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_H: PHCD Position       */
+#define USB0_PORTSC1_H_PHCD_Msk                               (0x01UL << USB0_PORTSC1_H_PHCD_Pos)                       /*!< USB0 PORTSC1_H: PHCD Mask           */
+#define USB0_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_H: PFSC Position       */
+#define USB0_PORTSC1_H_PFSC_Msk                               (0x01UL << USB0_PORTSC1_H_PFSC_Pos)                       /*!< USB0 PORTSC1_H: PFSC Mask           */
+#define USB0_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_H: PSPD Position       */
+#define USB0_PORTSC1_H_PSPD_Msk                               (0x03UL << USB0_PORTSC1_H_PSPD_Pos)                       /*!< USB0 PORTSC1_H: PSPD Mask           */
+
+// ---------------------------------------  USB0_OTGSC  -------------------------------------------
+#define USB0_OTGSC_VD_Pos                                     0                                                         /*!< USB0 OTGSC: VD Position             */
+#define USB0_OTGSC_VD_Msk                                     (0x01UL << USB0_OTGSC_VD_Pos)                             /*!< USB0 OTGSC: VD Mask                 */
+#define USB0_OTGSC_VC_Pos                                     1                                                         /*!< USB0 OTGSC: VC Position             */
+#define USB0_OTGSC_VC_Msk                                     (0x01UL << USB0_OTGSC_VC_Pos)                             /*!< USB0 OTGSC: VC Mask                 */
+#define USB0_OTGSC_HAAR_Pos                                   2                                                         /*!< USB0 OTGSC: HAAR Position           */
+#define USB0_OTGSC_HAAR_Msk                                   (0x01UL << USB0_OTGSC_HAAR_Pos)                           /*!< USB0 OTGSC: HAAR Mask               */
+#define USB0_OTGSC_OT_Pos                                     3                                                         /*!< USB0 OTGSC: OT Position             */
+#define USB0_OTGSC_OT_Msk                                     (0x01UL << USB0_OTGSC_OT_Pos)                             /*!< USB0 OTGSC: OT Mask                 */
+#define USB0_OTGSC_DP_Pos                                     4                                                         /*!< USB0 OTGSC: DP Position             */
+#define USB0_OTGSC_DP_Msk                                     (0x01UL << USB0_OTGSC_DP_Pos)                             /*!< USB0 OTGSC: DP Mask                 */
+#define USB0_OTGSC_IDPU_Pos                                   5                                                         /*!< USB0 OTGSC: IDPU Position           */
+#define USB0_OTGSC_IDPU_Msk                                   (0x01UL << USB0_OTGSC_IDPU_Pos)                           /*!< USB0 OTGSC: IDPU Mask               */
+#define USB0_OTGSC_HADP_Pos                                   6                                                         /*!< USB0 OTGSC: HADP Position           */
+#define USB0_OTGSC_HADP_Msk                                   (0x01UL << USB0_OTGSC_HADP_Pos)                           /*!< USB0 OTGSC: HADP Mask               */
+#define USB0_OTGSC_HABA_Pos                                   7                                                         /*!< USB0 OTGSC: HABA Position           */
+#define USB0_OTGSC_HABA_Msk                                   (0x01UL << USB0_OTGSC_HABA_Pos)                           /*!< USB0 OTGSC: HABA Mask               */
+#define USB0_OTGSC_ID_Pos                                     8                                                         /*!< USB0 OTGSC: ID Position             */
+#define USB0_OTGSC_ID_Msk                                     (0x01UL << USB0_OTGSC_ID_Pos)                             /*!< USB0 OTGSC: ID Mask                 */
+#define USB0_OTGSC_AVV_Pos                                    9                                                         /*!< USB0 OTGSC: AVV Position            */
+#define USB0_OTGSC_AVV_Msk                                    (0x01UL << USB0_OTGSC_AVV_Pos)                            /*!< USB0 OTGSC: AVV Mask                */
+#define USB0_OTGSC_ASV_Pos                                    10                                                        /*!< USB0 OTGSC: ASV Position            */
+#define USB0_OTGSC_ASV_Msk                                    (0x01UL << USB0_OTGSC_ASV_Pos)                            /*!< USB0 OTGSC: ASV Mask                */
+#define USB0_OTGSC_BSV_Pos                                    11                                                        /*!< USB0 OTGSC: BSV Position            */
+#define USB0_OTGSC_BSV_Msk                                    (0x01UL << USB0_OTGSC_BSV_Pos)                            /*!< USB0 OTGSC: BSV Mask                */
+#define USB0_OTGSC_BSE_Pos                                    12                                                        /*!< USB0 OTGSC: BSE Position            */
+#define USB0_OTGSC_BSE_Msk                                    (0x01UL << USB0_OTGSC_BSE_Pos)                            /*!< USB0 OTGSC: BSE Mask                */
+#define USB0_OTGSC_MS1T_Pos                                   13                                                        /*!< USB0 OTGSC: MS1T Position           */
+#define USB0_OTGSC_MS1T_Msk                                   (0x01UL << USB0_OTGSC_MS1T_Pos)                           /*!< USB0 OTGSC: MS1T Mask               */
+#define USB0_OTGSC_DPS_Pos                                    14                                                        /*!< USB0 OTGSC: DPS Position            */
+#define USB0_OTGSC_DPS_Msk                                    (0x01UL << USB0_OTGSC_DPS_Pos)                            /*!< USB0 OTGSC: DPS Mask                */
+#define USB0_OTGSC_IDIS_Pos                                   16                                                        /*!< USB0 OTGSC: IDIS Position           */
+#define USB0_OTGSC_IDIS_Msk                                   (0x01UL << USB0_OTGSC_IDIS_Pos)                           /*!< USB0 OTGSC: IDIS Mask               */
+#define USB0_OTGSC_AVVIS_Pos                                  17                                                        /*!< USB0 OTGSC: AVVIS Position          */
+#define USB0_OTGSC_AVVIS_Msk                                  (0x01UL << USB0_OTGSC_AVVIS_Pos)                          /*!< USB0 OTGSC: AVVIS Mask              */
+#define USB0_OTGSC_ASVIS_Pos                                  18                                                        /*!< USB0 OTGSC: ASVIS Position          */
+#define USB0_OTGSC_ASVIS_Msk                                  (0x01UL << USB0_OTGSC_ASVIS_Pos)                          /*!< USB0 OTGSC: ASVIS Mask              */
+#define USB0_OTGSC_BSVIS_Pos                                  19                                                        /*!< USB0 OTGSC: BSVIS Position          */
+#define USB0_OTGSC_BSVIS_Msk                                  (0x01UL << USB0_OTGSC_BSVIS_Pos)                          /*!< USB0 OTGSC: BSVIS Mask              */
+#define USB0_OTGSC_BSEIS_Pos                                  20                                                        /*!< USB0 OTGSC: BSEIS Position          */
+#define USB0_OTGSC_BSEIS_Msk                                  (0x01UL << USB0_OTGSC_BSEIS_Pos)                          /*!< USB0 OTGSC: BSEIS Mask              */
+#define USB0_OTGSC_ms1S_Pos                                   21                                                        /*!< USB0 OTGSC: ms1S Position           */
+#define USB0_OTGSC_ms1S_Msk                                   (0x01UL << USB0_OTGSC_ms1S_Pos)                           /*!< USB0 OTGSC: ms1S Mask               */
+#define USB0_OTGSC_DPIS_Pos                                   22                                                        /*!< USB0 OTGSC: DPIS Position           */
+#define USB0_OTGSC_DPIS_Msk                                   (0x01UL << USB0_OTGSC_DPIS_Pos)                           /*!< USB0 OTGSC: DPIS Mask               */
+#define USB0_OTGSC_IDIE_Pos                                   24                                                        /*!< USB0 OTGSC: IDIE Position           */
+#define USB0_OTGSC_IDIE_Msk                                   (0x01UL << USB0_OTGSC_IDIE_Pos)                           /*!< USB0 OTGSC: IDIE Mask               */
+#define USB0_OTGSC_AVVIE_Pos                                  25                                                        /*!< USB0 OTGSC: AVVIE Position          */
+#define USB0_OTGSC_AVVIE_Msk                                  (0x01UL << USB0_OTGSC_AVVIE_Pos)                          /*!< USB0 OTGSC: AVVIE Mask              */
+#define USB0_OTGSC_ASVIE_Pos                                  26                                                        /*!< USB0 OTGSC: ASVIE Position          */
+#define USB0_OTGSC_ASVIE_Msk                                  (0x01UL << USB0_OTGSC_ASVIE_Pos)                          /*!< USB0 OTGSC: ASVIE Mask              */
+#define USB0_OTGSC_BSVIE_Pos                                  27                                                        /*!< USB0 OTGSC: BSVIE Position          */
+#define USB0_OTGSC_BSVIE_Msk                                  (0x01UL << USB0_OTGSC_BSVIE_Pos)                          /*!< USB0 OTGSC: BSVIE Mask              */
+#define USB0_OTGSC_BSEIE_Pos                                  28                                                        /*!< USB0 OTGSC: BSEIE Position          */
+#define USB0_OTGSC_BSEIE_Msk                                  (0x01UL << USB0_OTGSC_BSEIE_Pos)                          /*!< USB0 OTGSC: BSEIE Mask              */
+#define USB0_OTGSC_MS1E_Pos                                   29                                                        /*!< USB0 OTGSC: MS1E Position           */
+#define USB0_OTGSC_MS1E_Msk                                   (0x01UL << USB0_OTGSC_MS1E_Pos)                           /*!< USB0 OTGSC: MS1E Mask               */
+#define USB0_OTGSC_DPIE_Pos                                   30                                                        /*!< USB0 OTGSC: DPIE Position           */
+#define USB0_OTGSC_DPIE_Msk                                   (0x01UL << USB0_OTGSC_DPIE_Pos)                           /*!< USB0 OTGSC: DPIE Mask               */
+
+// -------------------------------------  USB0_USBMODE_D  -----------------------------------------
+#define USB0_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB0 USBMODE_D: CM1_0 Position      */
+#define USB0_USBMODE_D_CM1_0_Msk                              (0x03UL << USB0_USBMODE_D_CM1_0_Pos)                      /*!< USB0 USBMODE_D: CM1_0 Mask          */
+#define USB0_USBMODE_D_ES_Pos                                 2                                                         /*!< USB0 USBMODE_D: ES Position         */
+#define USB0_USBMODE_D_ES_Msk                                 (0x01UL << USB0_USBMODE_D_ES_Pos)                         /*!< USB0 USBMODE_D: ES Mask             */
+#define USB0_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB0 USBMODE_D: SLOM Position       */
+#define USB0_USBMODE_D_SLOM_Msk                               (0x01UL << USB0_USBMODE_D_SLOM_Pos)                       /*!< USB0 USBMODE_D: SLOM Mask           */
+#define USB0_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_D: SDIS Position       */
+#define USB0_USBMODE_D_SDIS_Msk                               (0x01UL << USB0_USBMODE_D_SDIS_Pos)                       /*!< USB0 USBMODE_D: SDIS Mask           */
+
+// -------------------------------------  USB0_USBMODE_H  -----------------------------------------
+#define USB0_USBMODE_H_CM_Pos                                 0                                                         /*!< USB0 USBMODE_H: CM Position         */
+#define USB0_USBMODE_H_CM_Msk                                 (0x03UL << USB0_USBMODE_H_CM_Pos)                         /*!< USB0 USBMODE_H: CM Mask             */
+#define USB0_USBMODE_H_ES_Pos                                 2                                                         /*!< USB0 USBMODE_H: ES Position         */
+#define USB0_USBMODE_H_ES_Msk                                 (0x01UL << USB0_USBMODE_H_ES_Pos)                         /*!< USB0 USBMODE_H: ES Mask             */
+#define USB0_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_H: SDIS Position       */
+#define USB0_USBMODE_H_SDIS_Msk                               (0x01UL << USB0_USBMODE_H_SDIS_Pos)                       /*!< USB0 USBMODE_H: SDIS Mask           */
+#define USB0_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB0 USBMODE_H: VBPS Position       */
+#define USB0_USBMODE_H_VBPS_Msk                               (0x01UL << USB0_USBMODE_H_VBPS_Pos)                       /*!< USB0 USBMODE_H: VBPS Mask           */
+
+// -----------------------------------  USB0_ENDPTSETUPSTAT  --------------------------------------
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos               4                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos               5                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */
+
+// -------------------------------------  USB0_ENDPTPRIME  ----------------------------------------
+#define USB0_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB0 ENDPTPRIME: PERB0 Position     */
+#define USB0_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB0_Pos)                     /*!< USB0 ENDPTPRIME: PERB0 Mask         */
+#define USB0_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB0 ENDPTPRIME: PERB1 Position     */
+#define USB0_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB1_Pos)                     /*!< USB0 ENDPTPRIME: PERB1 Mask         */
+#define USB0_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB0 ENDPTPRIME: PERB2 Position     */
+#define USB0_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB2_Pos)                     /*!< USB0 ENDPTPRIME: PERB2 Mask         */
+#define USB0_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB0 ENDPTPRIME: PERB3 Position     */
+#define USB0_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB3_Pos)                     /*!< USB0 ENDPTPRIME: PERB3 Mask         */
+#define USB0_ENDPTPRIME_PERB4_Pos                             4                                                         /*!< USB0 ENDPTPRIME: PERB4 Position     */
+#define USB0_ENDPTPRIME_PERB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB4_Pos)                     /*!< USB0 ENDPTPRIME: PERB4 Mask         */
+#define USB0_ENDPTPRIME_PERB5_Pos                             5                                                         /*!< USB0 ENDPTPRIME: PERB5 Position     */
+#define USB0_ENDPTPRIME_PERB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB5_Pos)                     /*!< USB0 ENDPTPRIME: PERB5 Mask         */
+#define USB0_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB0 ENDPTPRIME: PETB0 Position     */
+#define USB0_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB0_Pos)                     /*!< USB0 ENDPTPRIME: PETB0 Mask         */
+#define USB0_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB0 ENDPTPRIME: PETB1 Position     */
+#define USB0_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB1_Pos)                     /*!< USB0 ENDPTPRIME: PETB1 Mask         */
+#define USB0_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB0 ENDPTPRIME: PETB2 Position     */
+#define USB0_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB2_Pos)                     /*!< USB0 ENDPTPRIME: PETB2 Mask         */
+#define USB0_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB0 ENDPTPRIME: PETB3 Position     */
+#define USB0_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB3_Pos)                     /*!< USB0 ENDPTPRIME: PETB3 Mask         */
+#define USB0_ENDPTPRIME_PETB4_Pos                             20                                                        /*!< USB0 ENDPTPRIME: PETB4 Position     */
+#define USB0_ENDPTPRIME_PETB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB4_Pos)                     /*!< USB0 ENDPTPRIME: PETB4 Mask         */
+#define USB0_ENDPTPRIME_PETB5_Pos                             21                                                        /*!< USB0 ENDPTPRIME: PETB5 Position     */
+#define USB0_ENDPTPRIME_PETB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB5_Pos)                     /*!< USB0 ENDPTPRIME: PETB5 Mask         */
+
+// -------------------------------------  USB0_ENDPTFLUSH  ----------------------------------------
+#define USB0_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB0 ENDPTFLUSH: FERB0 Position     */
+#define USB0_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos)                     /*!< USB0 ENDPTFLUSH: FERB0 Mask         */
+#define USB0_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB0 ENDPTFLUSH: FERB1 Position     */
+#define USB0_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos)                     /*!< USB0 ENDPTFLUSH: FERB1 Mask         */
+#define USB0_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB0 ENDPTFLUSH: FERB2 Position     */
+#define USB0_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos)                     /*!< USB0 ENDPTFLUSH: FERB2 Mask         */
+#define USB0_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB0 ENDPTFLUSH: FERB3 Position     */
+#define USB0_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos)                     /*!< USB0 ENDPTFLUSH: FERB3 Mask         */
+#define USB0_ENDPTFLUSH_FERB4_Pos                             4                                                         /*!< USB0 ENDPTFLUSH: FERB4 Position     */
+#define USB0_ENDPTFLUSH_FERB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos)                     /*!< USB0 ENDPTFLUSH: FERB4 Mask         */
+#define USB0_ENDPTFLUSH_FERB5_Pos                             5                                                         /*!< USB0 ENDPTFLUSH: FERB5 Position     */
+#define USB0_ENDPTFLUSH_FERB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos)                     /*!< USB0 ENDPTFLUSH: FERB5 Mask         */
+#define USB0_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB0 ENDPTFLUSH: FETB0 Position     */
+#define USB0_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos)                     /*!< USB0 ENDPTFLUSH: FETB0 Mask         */
+#define USB0_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB0 ENDPTFLUSH: FETB1 Position     */
+#define USB0_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos)                     /*!< USB0 ENDPTFLUSH: FETB1 Mask         */
+#define USB0_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB0 ENDPTFLUSH: FETB2 Position     */
+#define USB0_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos)                     /*!< USB0 ENDPTFLUSH: FETB2 Mask         */
+#define USB0_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB0 ENDPTFLUSH: FETB3 Position     */
+#define USB0_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos)                     /*!< USB0 ENDPTFLUSH: FETB3 Mask         */
+#define USB0_ENDPTFLUSH_FETB4_Pos                             20                                                        /*!< USB0 ENDPTFLUSH: FETB4 Position     */
+#define USB0_ENDPTFLUSH_FETB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos)                     /*!< USB0 ENDPTFLUSH: FETB4 Mask         */
+#define USB0_ENDPTFLUSH_FETB5_Pos                             21                                                        /*!< USB0 ENDPTFLUSH: FETB5 Position     */
+#define USB0_ENDPTFLUSH_FETB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos)                     /*!< USB0 ENDPTFLUSH: FETB5 Mask         */
+
+// -------------------------------------  USB0_ENDPTSTAT  -----------------------------------------
+#define USB0_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB0 ENDPTSTAT: ERBR0 Position      */
+#define USB0_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos)                      /*!< USB0 ENDPTSTAT: ERBR0 Mask          */
+#define USB0_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB0 ENDPTSTAT: ERBR1 Position      */
+#define USB0_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos)                      /*!< USB0 ENDPTSTAT: ERBR1 Mask          */
+#define USB0_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB0 ENDPTSTAT: ERBR2 Position      */
+#define USB0_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos)                      /*!< USB0 ENDPTSTAT: ERBR2 Mask          */
+#define USB0_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB0 ENDPTSTAT: ERBR3 Position      */
+#define USB0_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos)                      /*!< USB0 ENDPTSTAT: ERBR3 Mask          */
+#define USB0_ENDPTSTAT_ERBR4_Pos                              4                                                         /*!< USB0 ENDPTSTAT: ERBR4 Position      */
+#define USB0_ENDPTSTAT_ERBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos)                      /*!< USB0 ENDPTSTAT: ERBR4 Mask          */
+#define USB0_ENDPTSTAT_ERBR5_Pos                              5                                                         /*!< USB0 ENDPTSTAT: ERBR5 Position      */
+#define USB0_ENDPTSTAT_ERBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos)                      /*!< USB0 ENDPTSTAT: ERBR5 Mask          */
+#define USB0_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB0 ENDPTSTAT: ETBR0 Position      */
+#define USB0_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos)                      /*!< USB0 ENDPTSTAT: ETBR0 Mask          */
+#define USB0_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB0 ENDPTSTAT: ETBR1 Position      */
+#define USB0_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos)                      /*!< USB0 ENDPTSTAT: ETBR1 Mask          */
+#define USB0_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB0 ENDPTSTAT: ETBR2 Position      */
+#define USB0_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos)                      /*!< USB0 ENDPTSTAT: ETBR2 Mask          */
+#define USB0_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB0 ENDPTSTAT: ETBR3 Position      */
+#define USB0_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos)                      /*!< USB0 ENDPTSTAT: ETBR3 Mask          */
+#define USB0_ENDPTSTAT_ETBR4_Pos                              20                                                        /*!< USB0 ENDPTSTAT: ETBR4 Position      */
+#define USB0_ENDPTSTAT_ETBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos)                      /*!< USB0 ENDPTSTAT: ETBR4 Mask          */
+#define USB0_ENDPTSTAT_ETBR5_Pos                              21                                                        /*!< USB0 ENDPTSTAT: ETBR5 Position      */
+#define USB0_ENDPTSTAT_ETBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos)                      /*!< USB0 ENDPTSTAT: ETBR5 Mask          */
+
+// -----------------------------------  USB0_ENDPTCOMPLETE  ---------------------------------------
+#define USB0_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB0 ENDPTCOMPLETE: ERCE0 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB0 ENDPTCOMPLETE: ERCE1 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB0 ENDPTCOMPLETE: ERCE2 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB0 ENDPTCOMPLETE: ERCE3 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE4_Pos                          4                                                         /*!< USB0 ENDPTCOMPLETE: ERCE4 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask      */
+#define USB0_ENDPTCOMPLETE_ERCE5_Pos                          5                                                         /*!< USB0 ENDPTCOMPLETE: ERCE5 Position  */
+#define USB0_ENDPTCOMPLETE_ERCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB0 ENDPTCOMPLETE: ETCE0 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB0 ENDPTCOMPLETE: ETCE1 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB0 ENDPTCOMPLETE: ETCE2 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB0 ENDPTCOMPLETE: ETCE3 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE4_Pos                          20                                                        /*!< USB0 ENDPTCOMPLETE: ETCE4 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask      */
+#define USB0_ENDPTCOMPLETE_ETCE5_Pos                          21                                                        /*!< USB0 ENDPTCOMPLETE: ETCE5 Position  */
+#define USB0_ENDPTCOMPLETE_ETCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask      */
+
+// -------------------------------------  USB0_ENDPTCTRL0  ----------------------------------------
+#define USB0_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL0: RXS Position       */
+#define USB0_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXS_Pos)                       /*!< USB0 ENDPTCTRL0: RXS Mask           */
+#define USB0_ENDPTCTRL0_RXT1_0_Pos                            2                                                         /*!< USB0 ENDPTCTRL0: RXT1_0 Position    */
+#define USB0_ENDPTCTRL0_RXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: RXT1_0 Mask        */
+#define USB0_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL0: RXE Position       */
+#define USB0_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXE_Pos)                       /*!< USB0 ENDPTCTRL0: RXE Mask           */
+#define USB0_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL0: TXS Position       */
+#define USB0_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXS_Pos)                       /*!< USB0 ENDPTCTRL0: TXS Mask           */
+#define USB0_ENDPTCTRL0_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL0: TXT1_0 Position    */
+#define USB0_ENDPTCTRL0_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL0: TXE Position       */
+#define USB0_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXE_Pos)                       /*!< USB0 ENDPTCTRL0: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL1  ----------------------------------------
+#define USB0_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL1: RXS Position       */
+#define USB0_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXS_Pos)                       /*!< USB0 ENDPTCTRL1: RXS Mask           */
+#define USB0_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL1: RXT Position       */
+#define USB0_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL1_RXT_Pos)                       /*!< USB0 ENDPTCTRL1: RXT Mask           */
+#define USB0_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL1: RXI Position       */
+#define USB0_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXI_Pos)                       /*!< USB0 ENDPTCTRL1: RXI Mask           */
+#define USB0_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL1: RXR Position       */
+#define USB0_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXR_Pos)                       /*!< USB0 ENDPTCTRL1: RXR Mask           */
+#define USB0_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL1: RXE Position       */
+#define USB0_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXE_Pos)                       /*!< USB0 ENDPTCTRL1: RXE Mask           */
+#define USB0_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL1: TXS Position       */
+#define USB0_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXS_Pos)                       /*!< USB0 ENDPTCTRL1: TXS Mask           */
+#define USB0_ENDPTCTRL1_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL1: TXT1_0 Position    */
+#define USB0_ENDPTCTRL1_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL1: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL1: TXI Position       */
+#define USB0_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXI_Pos)                       /*!< USB0 ENDPTCTRL1: TXI Mask           */
+#define USB0_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL1: TXR Position       */
+#define USB0_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXR_Pos)                       /*!< USB0 ENDPTCTRL1: TXR Mask           */
+#define USB0_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL1: TXE Position       */
+#define USB0_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXE_Pos)                       /*!< USB0 ENDPTCTRL1: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL2  ----------------------------------------
+#define USB0_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL2: RXS Position       */
+#define USB0_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXS_Pos)                       /*!< USB0 ENDPTCTRL2: RXS Mask           */
+#define USB0_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL2: RXT Position       */
+#define USB0_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL2_RXT_Pos)                       /*!< USB0 ENDPTCTRL2: RXT Mask           */
+#define USB0_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL2: RXI Position       */
+#define USB0_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXI_Pos)                       /*!< USB0 ENDPTCTRL2: RXI Mask           */
+#define USB0_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL2: RXR Position       */
+#define USB0_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXR_Pos)                       /*!< USB0 ENDPTCTRL2: RXR Mask           */
+#define USB0_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL2: RXE Position       */
+#define USB0_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXE_Pos)                       /*!< USB0 ENDPTCTRL2: RXE Mask           */
+#define USB0_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL2: TXS Position       */
+#define USB0_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXS_Pos)                       /*!< USB0 ENDPTCTRL2: TXS Mask           */
+#define USB0_ENDPTCTRL2_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL2: TXT1_0 Position    */
+#define USB0_ENDPTCTRL2_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL2: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL2: TXI Position       */
+#define USB0_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXI_Pos)                       /*!< USB0 ENDPTCTRL2: TXI Mask           */
+#define USB0_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL2: TXR Position       */
+#define USB0_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXR_Pos)                       /*!< USB0 ENDPTCTRL2: TXR Mask           */
+#define USB0_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL2: TXE Position       */
+#define USB0_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXE_Pos)                       /*!< USB0 ENDPTCTRL2: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL3  ----------------------------------------
+#define USB0_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL3: RXS Position       */
+#define USB0_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXS_Pos)                       /*!< USB0 ENDPTCTRL3: RXS Mask           */
+#define USB0_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL3: RXT Position       */
+#define USB0_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL3_RXT_Pos)                       /*!< USB0 ENDPTCTRL3: RXT Mask           */
+#define USB0_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL3: RXI Position       */
+#define USB0_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXI_Pos)                       /*!< USB0 ENDPTCTRL3: RXI Mask           */
+#define USB0_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL3: RXR Position       */
+#define USB0_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXR_Pos)                       /*!< USB0 ENDPTCTRL3: RXR Mask           */
+#define USB0_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL3: RXE Position       */
+#define USB0_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXE_Pos)                       /*!< USB0 ENDPTCTRL3: RXE Mask           */
+#define USB0_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL3: TXS Position       */
+#define USB0_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXS_Pos)                       /*!< USB0 ENDPTCTRL3: TXS Mask           */
+#define USB0_ENDPTCTRL3_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL3: TXT1_0 Position    */
+#define USB0_ENDPTCTRL3_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL3: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL3: TXI Position       */
+#define USB0_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXI_Pos)                       /*!< USB0 ENDPTCTRL3: TXI Mask           */
+#define USB0_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL3: TXR Position       */
+#define USB0_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXR_Pos)                       /*!< USB0 ENDPTCTRL3: TXR Mask           */
+#define USB0_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL3: TXE Position       */
+#define USB0_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXE_Pos)                       /*!< USB0 ENDPTCTRL3: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL4  ----------------------------------------
+#define USB0_ENDPTCTRL4_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL4: RXS Position       */
+#define USB0_ENDPTCTRL4_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXS_Pos)                       /*!< USB0 ENDPTCTRL4: RXS Mask           */
+#define USB0_ENDPTCTRL4_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL4: RXT Position       */
+#define USB0_ENDPTCTRL4_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL4_RXT_Pos)                       /*!< USB0 ENDPTCTRL4: RXT Mask           */
+#define USB0_ENDPTCTRL4_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL4: RXI Position       */
+#define USB0_ENDPTCTRL4_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXI_Pos)                       /*!< USB0 ENDPTCTRL4: RXI Mask           */
+#define USB0_ENDPTCTRL4_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL4: RXR Position       */
+#define USB0_ENDPTCTRL4_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXR_Pos)                       /*!< USB0 ENDPTCTRL4: RXR Mask           */
+#define USB0_ENDPTCTRL4_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL4: RXE Position       */
+#define USB0_ENDPTCTRL4_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXE_Pos)                       /*!< USB0 ENDPTCTRL4: RXE Mask           */
+#define USB0_ENDPTCTRL4_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL4: TXS Position       */
+#define USB0_ENDPTCTRL4_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXS_Pos)                       /*!< USB0 ENDPTCTRL4: TXS Mask           */
+#define USB0_ENDPTCTRL4_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL4: TXT1_0 Position    */
+#define USB0_ENDPTCTRL4_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL4: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL4_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL4: TXI Position       */
+#define USB0_ENDPTCTRL4_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXI_Pos)                       /*!< USB0 ENDPTCTRL4: TXI Mask           */
+#define USB0_ENDPTCTRL4_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL4: TXR Position       */
+#define USB0_ENDPTCTRL4_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXR_Pos)                       /*!< USB0 ENDPTCTRL4: TXR Mask           */
+#define USB0_ENDPTCTRL4_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL4: TXE Position       */
+#define USB0_ENDPTCTRL4_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXE_Pos)                       /*!< USB0 ENDPTCTRL4: TXE Mask           */
+
+// -------------------------------------  USB0_ENDPTCTRL5  ----------------------------------------
+#define USB0_ENDPTCTRL5_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL5: RXS Position       */
+#define USB0_ENDPTCTRL5_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXS_Pos)                       /*!< USB0 ENDPTCTRL5: RXS Mask           */
+#define USB0_ENDPTCTRL5_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL5: RXT Position       */
+#define USB0_ENDPTCTRL5_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL5_RXT_Pos)                       /*!< USB0 ENDPTCTRL5: RXT Mask           */
+#define USB0_ENDPTCTRL5_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL5: RXI Position       */
+#define USB0_ENDPTCTRL5_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXI_Pos)                       /*!< USB0 ENDPTCTRL5: RXI Mask           */
+#define USB0_ENDPTCTRL5_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL5: RXR Position       */
+#define USB0_ENDPTCTRL5_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXR_Pos)                       /*!< USB0 ENDPTCTRL5: RXR Mask           */
+#define USB0_ENDPTCTRL5_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL5: RXE Position       */
+#define USB0_ENDPTCTRL5_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXE_Pos)                       /*!< USB0 ENDPTCTRL5: RXE Mask           */
+#define USB0_ENDPTCTRL5_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL5: TXS Position       */
+#define USB0_ENDPTCTRL5_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXS_Pos)                       /*!< USB0 ENDPTCTRL5: TXS Mask           */
+#define USB0_ENDPTCTRL5_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL5: TXT1_0 Position    */
+#define USB0_ENDPTCTRL5_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL5: TXT1_0 Mask        */
+#define USB0_ENDPTCTRL5_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL5: TXI Position       */
+#define USB0_ENDPTCTRL5_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXI_Pos)                       /*!< USB0 ENDPTCTRL5: TXI Mask           */
+#define USB0_ENDPTCTRL5_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL5: TXR Position       */
+#define USB0_ENDPTCTRL5_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXR_Pos)                       /*!< USB0 ENDPTCTRL5: TXR Mask           */
+#define USB0_ENDPTCTRL5_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL5: TXE Position       */
+#define USB0_ENDPTCTRL5_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXE_Pos)                       /*!< USB0 ENDPTCTRL5: TXE Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 USB1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  USB1_CAPLENGTH  -----------------------------------------
+#define USB1_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB1 CAPLENGTH: CAPLENGTH Position  */
+#define USB1_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB1 CAPLENGTH: CAPLENGTH Mask      */
+#define USB1_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB1 CAPLENGTH: HCIVERSION Position */
+#define USB1_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos)           /*!< USB1 CAPLENGTH: HCIVERSION Mask     */
+
+// -------------------------------------  USB1_HCSPARAMS  -----------------------------------------
+#define USB1_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB1 HCSPARAMS: N_PORTS Position    */
+#define USB1_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos)                    /*!< USB1 HCSPARAMS: N_PORTS Mask        */
+#define USB1_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB1 HCSPARAMS: PPC Position        */
+#define USB1_HCSPARAMS_PPC_Msk                                (0x01UL << USB1_HCSPARAMS_PPC_Pos)                        /*!< USB1 HCSPARAMS: PPC Mask            */
+#define USB1_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB1 HCSPARAMS: N_PCC Position      */
+#define USB1_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos)                      /*!< USB1 HCSPARAMS: N_PCC Mask          */
+#define USB1_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB1 HCSPARAMS: N_CC Position       */
+#define USB1_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB1_HCSPARAMS_N_CC_Pos)                       /*!< USB1 HCSPARAMS: N_CC Mask           */
+#define USB1_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB1 HCSPARAMS: PI Position         */
+#define USB1_HCSPARAMS_PI_Msk                                 (0x01UL << USB1_HCSPARAMS_PI_Pos)                         /*!< USB1 HCSPARAMS: PI Mask             */
+#define USB1_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB1 HCSPARAMS: N_PTT Position      */
+#define USB1_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos)                      /*!< USB1 HCSPARAMS: N_PTT Mask          */
+#define USB1_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB1 HCSPARAMS: N_TT Position       */
+#define USB1_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB1_HCSPARAMS_N_TT_Pos)                       /*!< USB1 HCSPARAMS: N_TT Mask           */
+
+// -------------------------------------  USB1_HCCPARAMS  -----------------------------------------
+#define USB1_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB1 HCCPARAMS: ADC Position        */
+#define USB1_HCCPARAMS_ADC_Msk                                (0x01UL << USB1_HCCPARAMS_ADC_Pos)                        /*!< USB1 HCCPARAMS: ADC Mask            */
+#define USB1_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB1 HCCPARAMS: PFL Position        */
+#define USB1_HCCPARAMS_PFL_Msk                                (0x01UL << USB1_HCCPARAMS_PFL_Pos)                        /*!< USB1 HCCPARAMS: PFL Mask            */
+#define USB1_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB1 HCCPARAMS: ASP Position        */
+#define USB1_HCCPARAMS_ASP_Msk                                (0x01UL << USB1_HCCPARAMS_ASP_Pos)                        /*!< USB1 HCCPARAMS: ASP Mask            */
+#define USB1_HCCPARAMS_IST_Pos                                4                                                         /*!< USB1 HCCPARAMS: IST Position        */
+#define USB1_HCCPARAMS_IST_Msk                                (0x0fUL << USB1_HCCPARAMS_IST_Pos)                        /*!< USB1 HCCPARAMS: IST Mask            */
+#define USB1_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB1 HCCPARAMS: EECP Position       */
+#define USB1_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos)                 /*!< USB1 HCCPARAMS: EECP Mask           */
+
+// -------------------------------------  USB1_DCIVERSION  ----------------------------------------
+#define USB1_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB1 DCIVERSION: DCIVERSION Position */
+#define USB1_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos)          /*!< USB1 DCIVERSION: DCIVERSION Mask    */
+
+// --------------------------------------  USB1_USBCMD_D  -----------------------------------------
+#define USB1_USBCMD_D_RS_Pos                                  0                                                         /*!< USB1 USBCMD_D: RS Position          */
+#define USB1_USBCMD_D_RS_Msk                                  (0x01UL << USB1_USBCMD_D_RS_Pos)                          /*!< USB1 USBCMD_D: RS Mask              */
+#define USB1_USBCMD_D_RST_Pos                                 1                                                         /*!< USB1 USBCMD_D: RST Position         */
+#define USB1_USBCMD_D_RST_Msk                                 (0x01UL << USB1_USBCMD_D_RST_Pos)                         /*!< USB1 USBCMD_D: RST Mask             */
+#define USB1_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB1 USBCMD_D: SUTW Position        */
+#define USB1_USBCMD_D_SUTW_Msk                                (0x01UL << USB1_USBCMD_D_SUTW_Pos)                        /*!< USB1 USBCMD_D: SUTW Mask            */
+#define USB1_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB1 USBCMD_D: ATDTW Position       */
+#define USB1_USBCMD_D_ATDTW_Msk                               (0x01UL << USB1_USBCMD_D_ATDTW_Pos)                       /*!< USB1 USBCMD_D: ATDTW Mask           */
+#define USB1_USBCMD_D_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_D: FS2 Position         */
+#define USB1_USBCMD_D_FS2_Msk                                 (0x01UL << USB1_USBCMD_D_FS2_Pos)                         /*!< USB1 USBCMD_D: FS2 Mask             */
+#define USB1_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_D: ITC Position         */
+#define USB1_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_D_ITC_Pos)                   /*!< USB1 USBCMD_D: ITC Mask             */
+
+// --------------------------------------  USB1_USBCMD_H  -----------------------------------------
+#define USB1_USBCMD_H_RS_Pos                                  0                                                         /*!< USB1 USBCMD_H: RS Position          */
+#define USB1_USBCMD_H_RS_Msk                                  (0x01UL << USB1_USBCMD_H_RS_Pos)                          /*!< USB1 USBCMD_H: RS Mask              */
+#define USB1_USBCMD_H_RST_Pos                                 1                                                         /*!< USB1 USBCMD_H: RST Position         */
+#define USB1_USBCMD_H_RST_Msk                                 (0x01UL << USB1_USBCMD_H_RST_Pos)                         /*!< USB1 USBCMD_H: RST Mask             */
+#define USB1_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB1 USBCMD_H: FS0 Position         */
+#define USB1_USBCMD_H_FS0_Msk                                 (0x01UL << USB1_USBCMD_H_FS0_Pos)                         /*!< USB1 USBCMD_H: FS0 Mask             */
+#define USB1_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB1 USBCMD_H: FS1 Position         */
+#define USB1_USBCMD_H_FS1_Msk                                 (0x01UL << USB1_USBCMD_H_FS1_Pos)                         /*!< USB1 USBCMD_H: FS1 Mask             */
+#define USB1_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB1 USBCMD_H: PSE Position         */
+#define USB1_USBCMD_H_PSE_Msk                                 (0x01UL << USB1_USBCMD_H_PSE_Pos)                         /*!< USB1 USBCMD_H: PSE Mask             */
+#define USB1_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB1 USBCMD_H: ASE Position         */
+#define USB1_USBCMD_H_ASE_Msk                                 (0x01UL << USB1_USBCMD_H_ASE_Pos)                         /*!< USB1 USBCMD_H: ASE Mask             */
+#define USB1_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB1 USBCMD_H: IAA Position         */
+#define USB1_USBCMD_H_IAA_Msk                                 (0x01UL << USB1_USBCMD_H_IAA_Pos)                         /*!< USB1 USBCMD_H: IAA Mask             */
+#define USB1_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB1 USBCMD_H: ASP1_0 Position      */
+#define USB1_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB1_USBCMD_H_ASP1_0_Pos)                      /*!< USB1 USBCMD_H: ASP1_0 Mask          */
+#define USB1_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB1 USBCMD_H: ASPE Position        */
+#define USB1_USBCMD_H_ASPE_Msk                                (0x01UL << USB1_USBCMD_H_ASPE_Pos)                        /*!< USB1 USBCMD_H: ASPE Mask            */
+#define USB1_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_H: FS2 Position         */
+#define USB1_USBCMD_H_FS2_Msk                                 (0x01UL << USB1_USBCMD_H_FS2_Pos)                         /*!< USB1 USBCMD_H: FS2 Mask             */
+#define USB1_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_H: ITC Position         */
+#define USB1_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_H_ITC_Pos)                   /*!< USB1 USBCMD_H: ITC Mask             */
+
+// --------------------------------------  USB1_USBSTS_D  -----------------------------------------
+#define USB1_USBSTS_D_UI_Pos                                  0                                                         /*!< USB1 USBSTS_D: UI Position          */
+#define USB1_USBSTS_D_UI_Msk                                  (0x01UL << USB1_USBSTS_D_UI_Pos)                          /*!< USB1 USBSTS_D: UI Mask              */
+#define USB1_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_D: UEI Position         */
+#define USB1_USBSTS_D_UEI_Msk                                 (0x01UL << USB1_USBSTS_D_UEI_Pos)                         /*!< USB1 USBSTS_D: UEI Mask             */
+#define USB1_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_D: PCI Position         */
+#define USB1_USBSTS_D_PCI_Msk                                 (0x01UL << USB1_USBSTS_D_PCI_Pos)                         /*!< USB1 USBSTS_D: PCI Mask             */
+#define USB1_USBSTS_D_URI_Pos                                 6                                                         /*!< USB1 USBSTS_D: URI Position         */
+#define USB1_USBSTS_D_URI_Msk                                 (0x01UL << USB1_USBSTS_D_URI_Pos)                         /*!< USB1 USBSTS_D: URI Mask             */
+#define USB1_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_D: SRI Position         */
+#define USB1_USBSTS_D_SRI_Msk                                 (0x01UL << USB1_USBSTS_D_SRI_Pos)                         /*!< USB1 USBSTS_D: SRI Mask             */
+#define USB1_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_D: SLI Position         */
+#define USB1_USBSTS_D_SLI_Msk                                 (0x01UL << USB1_USBSTS_D_SLI_Pos)                         /*!< USB1 USBSTS_D: SLI Mask             */
+#define USB1_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB1 USBSTS_D: NAKI Position        */
+#define USB1_USBSTS_D_NAKI_Msk                                (0x01UL << USB1_USBSTS_D_NAKI_Pos)                        /*!< USB1 USBSTS_D: NAKI Mask            */
+
+// --------------------------------------  USB1_USBSTS_H  -----------------------------------------
+#define USB1_USBSTS_H_UI_Pos                                  0                                                         /*!< USB1 USBSTS_H: UI Position          */
+#define USB1_USBSTS_H_UI_Msk                                  (0x01UL << USB1_USBSTS_H_UI_Pos)                          /*!< USB1 USBSTS_H: UI Mask              */
+#define USB1_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_H: UEI Position         */
+#define USB1_USBSTS_H_UEI_Msk                                 (0x01UL << USB1_USBSTS_H_UEI_Pos)                         /*!< USB1 USBSTS_H: UEI Mask             */
+#define USB1_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_H: PCI Position         */
+#define USB1_USBSTS_H_PCI_Msk                                 (0x01UL << USB1_USBSTS_H_PCI_Pos)                         /*!< USB1 USBSTS_H: PCI Mask             */
+#define USB1_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB1 USBSTS_H: FRI Position         */
+#define USB1_USBSTS_H_FRI_Msk                                 (0x01UL << USB1_USBSTS_H_FRI_Pos)                         /*!< USB1 USBSTS_H: FRI Mask             */
+#define USB1_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB1 USBSTS_H: AAI Position         */
+#define USB1_USBSTS_H_AAI_Msk                                 (0x01UL << USB1_USBSTS_H_AAI_Pos)                         /*!< USB1 USBSTS_H: AAI Mask             */
+#define USB1_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_H: SRI Position         */
+#define USB1_USBSTS_H_SRI_Msk                                 (0x01UL << USB1_USBSTS_H_SRI_Pos)                         /*!< USB1 USBSTS_H: SRI Mask             */
+#define USB1_USBSTS_H_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_H: SLI Position         */
+#define USB1_USBSTS_H_SLI_Msk                                 (0x01UL << USB1_USBSTS_H_SLI_Pos)                         /*!< USB1 USBSTS_H: SLI Mask             */
+#define USB1_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB1 USBSTS_H: HCH Position         */
+#define USB1_USBSTS_H_HCH_Msk                                 (0x01UL << USB1_USBSTS_H_HCH_Pos)                         /*!< USB1 USBSTS_H: HCH Mask             */
+#define USB1_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB1 USBSTS_H: RCL Position         */
+#define USB1_USBSTS_H_RCL_Msk                                 (0x01UL << USB1_USBSTS_H_RCL_Pos)                         /*!< USB1 USBSTS_H: RCL Mask             */
+#define USB1_USBSTS_H_PS_Pos                                  14                                                        /*!< USB1 USBSTS_H: PS Position          */
+#define USB1_USBSTS_H_PS_Msk                                  (0x01UL << USB1_USBSTS_H_PS_Pos)                          /*!< USB1 USBSTS_H: PS Mask              */
+#define USB1_USBSTS_H_AS_Pos                                  15                                                        /*!< USB1 USBSTS_H: AS Position          */
+#define USB1_USBSTS_H_AS_Msk                                  (0x01UL << USB1_USBSTS_H_AS_Pos)                          /*!< USB1 USBSTS_H: AS Mask              */
+#define USB1_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB1 USBSTS_H: UAI Position         */
+#define USB1_USBSTS_H_UAI_Msk                                 (0x01UL << USB1_USBSTS_H_UAI_Pos)                         /*!< USB1 USBSTS_H: UAI Mask             */
+#define USB1_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB1 USBSTS_H: UPI Position         */
+#define USB1_USBSTS_H_UPI_Msk                                 (0x01UL << USB1_USBSTS_H_UPI_Pos)                         /*!< USB1 USBSTS_H: UPI Mask             */
+
+// -------------------------------------  USB1_USBINTR_D  -----------------------------------------
+#define USB1_USBINTR_D_UE_Pos                                 0                                                         /*!< USB1 USBINTR_D: UE Position         */
+#define USB1_USBINTR_D_UE_Msk                                 (0x01UL << USB1_USBINTR_D_UE_Pos)                         /*!< USB1 USBINTR_D: UE Mask             */
+#define USB1_USBINTR_D_UEE_Pos                                1                                                         /*!< USB1 USBINTR_D: UEE Position        */
+#define USB1_USBINTR_D_UEE_Msk                                (0x01UL << USB1_USBINTR_D_UEE_Pos)                        /*!< USB1 USBINTR_D: UEE Mask            */
+#define USB1_USBINTR_D_PCE_Pos                                2                                                         /*!< USB1 USBINTR_D: PCE Position        */
+#define USB1_USBINTR_D_PCE_Msk                                (0x01UL << USB1_USBINTR_D_PCE_Pos)                        /*!< USB1 USBINTR_D: PCE Mask            */
+#define USB1_USBINTR_D_URE_Pos                                6                                                         /*!< USB1 USBINTR_D: URE Position        */
+#define USB1_USBINTR_D_URE_Msk                                (0x01UL << USB1_USBINTR_D_URE_Pos)                        /*!< USB1 USBINTR_D: URE Mask            */
+#define USB1_USBINTR_D_SRE_Pos                                7                                                         /*!< USB1 USBINTR_D: SRE Position        */
+#define USB1_USBINTR_D_SRE_Msk                                (0x01UL << USB1_USBINTR_D_SRE_Pos)                        /*!< USB1 USBINTR_D: SRE Mask            */
+#define USB1_USBINTR_D_SLE_Pos                                8                                                         /*!< USB1 USBINTR_D: SLE Position        */
+#define USB1_USBINTR_D_SLE_Msk                                (0x01UL << USB1_USBINTR_D_SLE_Pos)                        /*!< USB1 USBINTR_D: SLE Mask            */
+#define USB1_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB1 USBINTR_D: NAKE Position       */
+#define USB1_USBINTR_D_NAKE_Msk                               (0x01UL << USB1_USBINTR_D_NAKE_Pos)                       /*!< USB1 USBINTR_D: NAKE Mask           */
+#define USB1_USBINTR_D_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_D: UAIE Position       */
+#define USB1_USBINTR_D_UAIE_Msk                               (0x01UL << USB1_USBINTR_D_UAIE_Pos)                       /*!< USB1 USBINTR_D: UAIE Mask           */
+#define USB1_USBINTR_D_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_D: UPIA Position       */
+#define USB1_USBINTR_D_UPIA_Msk                               (0x01UL << USB1_USBINTR_D_UPIA_Pos)                       /*!< USB1 USBINTR_D: UPIA Mask           */
+
+// -------------------------------------  USB1_USBINTR_H  -----------------------------------------
+#define USB1_USBINTR_H_UE_Pos                                 0                                                         /*!< USB1 USBINTR_H: UE Position         */
+#define USB1_USBINTR_H_UE_Msk                                 (0x01UL << USB1_USBINTR_H_UE_Pos)                         /*!< USB1 USBINTR_H: UE Mask             */
+#define USB1_USBINTR_H_UEE_Pos                                1                                                         /*!< USB1 USBINTR_H: UEE Position        */
+#define USB1_USBINTR_H_UEE_Msk                                (0x01UL << USB1_USBINTR_H_UEE_Pos)                        /*!< USB1 USBINTR_H: UEE Mask            */
+#define USB1_USBINTR_H_PCE_Pos                                2                                                         /*!< USB1 USBINTR_H: PCE Position        */
+#define USB1_USBINTR_H_PCE_Msk                                (0x01UL << USB1_USBINTR_H_PCE_Pos)                        /*!< USB1 USBINTR_H: PCE Mask            */
+#define USB1_USBINTR_H_FRE_Pos                                3                                                         /*!< USB1 USBINTR_H: FRE Position        */
+#define USB1_USBINTR_H_FRE_Msk                                (0x01UL << USB1_USBINTR_H_FRE_Pos)                        /*!< USB1 USBINTR_H: FRE Mask            */
+#define USB1_USBINTR_H_AAE_Pos                                5                                                         /*!< USB1 USBINTR_H: AAE Position        */
+#define USB1_USBINTR_H_AAE_Msk                                (0x01UL << USB1_USBINTR_H_AAE_Pos)                        /*!< USB1 USBINTR_H: AAE Mask            */
+#define USB1_USBINTR_H_SRE_Pos                                7                                                         /*!< USB1 USBINTR_H: SRE Position        */
+#define USB1_USBINTR_H_SRE_Msk                                (0x01UL << USB1_USBINTR_H_SRE_Pos)                        /*!< USB1 USBINTR_H: SRE Mask            */
+#define USB1_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_H: UAIE Position       */
+#define USB1_USBINTR_H_UAIE_Msk                               (0x01UL << USB1_USBINTR_H_UAIE_Pos)                       /*!< USB1 USBINTR_H: UAIE Mask           */
+#define USB1_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_H: UPIA Position       */
+#define USB1_USBINTR_H_UPIA_Msk                               (0x01UL << USB1_USBINTR_H_UPIA_Pos)                       /*!< USB1 USBINTR_H: UPIA Mask           */
+
+// -------------------------------------  USB1_FRINDEX_D  -----------------------------------------
+#define USB1_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */
+#define USB1_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask     */
+#define USB1_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */
+#define USB1_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask    */
+
+// -------------------------------------  USB1_FRINDEX_H  -----------------------------------------
+#define USB1_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */
+#define USB1_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask     */
+#define USB1_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */
+#define USB1_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask    */
+
+// -------------------------------------  USB1_DEVICEADDR  ----------------------------------------
+#define USB1_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB1 DEVICEADDR: USBADRA Position   */
+#define USB1_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB1_DEVICEADDR_USBADRA_Pos)                   /*!< USB1 DEVICEADDR: USBADRA Mask       */
+#define USB1_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB1 DEVICEADDR: USBADR Position    */
+#define USB1_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB1_DEVICEADDR_USBADR_Pos)                    /*!< USB1 DEVICEADDR: USBADR Mask        */
+
+// ----------------------------------  USB1_PERIODICLISTBASE  -------------------------------------
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ----------------------------------  USB1_ENDPOINTLISTADDR  -------------------------------------
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// -----------------------------------  USB1_ASYNCLISTADDR  ---------------------------------------
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// ---------------------------------------  USB1_TTCTRL  ------------------------------------------
+#define USB1_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB1 TTCTRL: TTHA Position          */
+#define USB1_TTCTRL_TTHA_Msk                                  (0x7fUL << USB1_TTCTRL_TTHA_Pos)                          /*!< USB1 TTCTRL: TTHA Mask              */
+
+// -------------------------------------  USB1_BURSTSIZE  -----------------------------------------
+#define USB1_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB1 BURSTSIZE: RXPBURST Position   */
+#define USB1_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos)             /*!< USB1 BURSTSIZE: RXPBURST Mask       */
+#define USB1_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB1 BURSTSIZE: TXPBURST Position   */
+#define USB1_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos)             /*!< USB1 BURSTSIZE: TXPBURST Mask       */
+
+// ------------------------------------  USB1_TXFILLTUNING  ---------------------------------------
+#define USB1_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB1 TXFILLTUNING: TXSCHOH Position */
+#define USB1_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB1 TXFILLTUNING: TXSCHOH Mask     */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// ------------------------------------  USB1_ULPIVIEWPORT  ---------------------------------------
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos                       0                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask   */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos                       8                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask   */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Pos                        16                                                        /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Msk                        (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos)          /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask    */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Pos                        24                                                        /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Msk                        (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos)                /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask    */
+#define USB1_ULPIVIEWPORT_ULPISS_Pos                          27                                                        /*!< USB1 ULPIVIEWPORT: ULPISS Position  */
+#define USB1_ULPIVIEWPORT_ULPISS_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPISS Mask      */
+#define USB1_ULPIVIEWPORT_ULPIRW_Pos                          29                                                        /*!< USB1 ULPIVIEWPORT: ULPIRW Position  */
+#define USB1_ULPIVIEWPORT_ULPIRW_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIRW Mask      */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Pos                         30                                                        /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Msk                         (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos)                 /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask     */
+#define USB1_ULPIVIEWPORT_ULPIWU_Pos                          31                                                        /*!< USB1 ULPIVIEWPORT: ULPIWU Position  */
+#define USB1_ULPIVIEWPORT_ULPIWU_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIWU Mask      */
+
+// -------------------------------------  USB1_BINTERVAL  -----------------------------------------
+#define USB1_BINTERVAL_BINT_Pos                               0                                                         /*!< USB1 BINTERVAL: BINT Position       */
+#define USB1_BINTERVAL_BINT_Msk                               (0x0fUL << USB1_BINTERVAL_BINT_Pos)                       /*!< USB1 BINTERVAL: BINT Mask           */
+
+// --------------------------------------  USB1_ENDPTNAK  -----------------------------------------
+#define USB1_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB1 ENDPTNAK: EPRN0 Position       */
+#define USB1_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN0_Pos)                       /*!< USB1 ENDPTNAK: EPRN0 Mask           */
+#define USB1_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB1 ENDPTNAK: EPRN1 Position       */
+#define USB1_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN1_Pos)                       /*!< USB1 ENDPTNAK: EPRN1 Mask           */
+#define USB1_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB1 ENDPTNAK: EPRN2 Position       */
+#define USB1_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN2_Pos)                       /*!< USB1 ENDPTNAK: EPRN2 Mask           */
+#define USB1_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB1 ENDPTNAK: EPRN3 Position       */
+#define USB1_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN3_Pos)                       /*!< USB1 ENDPTNAK: EPRN3 Mask           */
+#define USB1_ENDPTNAK_EPTN16_Pos                              16                                                        /*!< USB1 ENDPTNAK: EPTN16 Position      */
+#define USB1_ENDPTNAK_EPTN16_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN16_Pos)                      /*!< USB1 ENDPTNAK: EPTN16 Mask          */
+#define USB1_ENDPTNAK_EPTN17_Pos                              17                                                        /*!< USB1 ENDPTNAK: EPTN17 Position      */
+#define USB1_ENDPTNAK_EPTN17_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN17_Pos)                      /*!< USB1 ENDPTNAK: EPTN17 Mask          */
+#define USB1_ENDPTNAK_EPTN18_Pos                              18                                                        /*!< USB1 ENDPTNAK: EPTN18 Position      */
+#define USB1_ENDPTNAK_EPTN18_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN18_Pos)                      /*!< USB1 ENDPTNAK: EPTN18 Mask          */
+#define USB1_ENDPTNAK_EPTN19_Pos                              19                                                        /*!< USB1 ENDPTNAK: EPTN19 Position      */
+#define USB1_ENDPTNAK_EPTN19_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN19_Pos)                      /*!< USB1 ENDPTNAK: EPTN19 Mask          */
+
+// -------------------------------------  USB1_ENDPTNAKEN  ----------------------------------------
+#define USB1_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB1 ENDPTNAKEN: EPRNE0 Position    */
+#define USB1_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE0 Mask        */
+#define USB1_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB1 ENDPTNAKEN: EPRNE1 Position    */
+#define USB1_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE1 Mask        */
+#define USB1_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB1 ENDPTNAKEN: EPRNE2 Position    */
+#define USB1_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE2 Mask        */
+#define USB1_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB1 ENDPTNAKEN: EPRNE3 Position    */
+#define USB1_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE3 Mask        */
+#define USB1_ENDPTNAKEN_EPTNE16_Pos                           16                                                        /*!< USB1 ENDPTNAKEN: EPTNE16 Position   */
+#define USB1_ENDPTNAKEN_EPTNE16_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE16 Mask       */
+#define USB1_ENDPTNAKEN_EPTNE17_Pos                           17                                                        /*!< USB1 ENDPTNAKEN: EPTNE17 Position   */
+#define USB1_ENDPTNAKEN_EPTNE17_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE17 Mask       */
+#define USB1_ENDPTNAKEN_EPTNE18_Pos                           18                                                        /*!< USB1 ENDPTNAKEN: EPTNE18 Position   */
+#define USB1_ENDPTNAKEN_EPTNE18_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE18 Mask       */
+#define USB1_ENDPTNAKEN_EPTNE19_Pos                           19                                                        /*!< USB1 ENDPTNAKEN: EPTNE19 Position   */
+#define USB1_ENDPTNAKEN_EPTNE19_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE19 Mask       */
+
+// -------------------------------------  USB1_PORTSC1_D  -----------------------------------------
+#define USB1_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_D: CCS Position        */
+#define USB1_PORTSC1_D_CCS_Msk                                (0x01UL << USB1_PORTSC1_D_CCS_Pos)                        /*!< USB1 PORTSC1_D: CCS Mask            */
+#define USB1_PORTSC1_D_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_D: CSC Position        */
+#define USB1_PORTSC1_D_CSC_Msk                                (0x01UL << USB1_PORTSC1_D_CSC_Pos)                        /*!< USB1 PORTSC1_D: CSC Mask            */
+#define USB1_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_D: PE Position         */
+#define USB1_PORTSC1_D_PE_Msk                                 (0x01UL << USB1_PORTSC1_D_PE_Pos)                         /*!< USB1 PORTSC1_D: PE Mask             */
+#define USB1_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_D: PEC Position        */
+#define USB1_PORTSC1_D_PEC_Msk                                (0x01UL << USB1_PORTSC1_D_PEC_Pos)                        /*!< USB1 PORTSC1_D: PEC Mask            */
+#define USB1_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_D: FPR Position        */
+#define USB1_PORTSC1_D_FPR_Msk                                (0x01UL << USB1_PORTSC1_D_FPR_Pos)                        /*!< USB1 PORTSC1_D: FPR Mask            */
+#define USB1_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_D: SUSP Position       */
+#define USB1_PORTSC1_D_SUSP_Msk                               (0x01UL << USB1_PORTSC1_D_SUSP_Pos)                       /*!< USB1 PORTSC1_D: SUSP Mask           */
+#define USB1_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_D: PR Position         */
+#define USB1_PORTSC1_D_PR_Msk                                 (0x01UL << USB1_PORTSC1_D_PR_Pos)                         /*!< USB1 PORTSC1_D: PR Mask             */
+#define USB1_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_D: HSP Position        */
+#define USB1_PORTSC1_D_HSP_Msk                                (0x01UL << USB1_PORTSC1_D_HSP_Pos)                        /*!< USB1 PORTSC1_D: HSP Mask            */
+#define USB1_PORTSC1_D_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_D: LS Position         */
+#define USB1_PORTSC1_D_LS_Msk                                 (0x03UL << USB1_PORTSC1_D_LS_Pos)                         /*!< USB1 PORTSC1_D: LS Mask             */
+#define USB1_PORTSC1_D_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_D: PP Position         */
+#define USB1_PORTSC1_D_PP_Msk                                 (0x01UL << USB1_PORTSC1_D_PP_Pos)                         /*!< USB1 PORTSC1_D: PP Mask             */
+#define USB1_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_D: PIC1_0 Position     */
+#define USB1_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos)                     /*!< USB1 PORTSC1_D: PIC1_0 Mask         */
+#define USB1_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_D: PTC3_0 Position     */
+#define USB1_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos)                     /*!< USB1 PORTSC1_D: PTC3_0 Mask         */
+#define USB1_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_D: PHCD Position       */
+#define USB1_PORTSC1_D_PHCD_Msk                               (0x01UL << USB1_PORTSC1_D_PHCD_Pos)                       /*!< USB1 PORTSC1_D: PHCD Mask           */
+#define USB1_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_D: PFSC Position       */
+#define USB1_PORTSC1_D_PFSC_Msk                               (0x01UL << USB1_PORTSC1_D_PFSC_Pos)                       /*!< USB1 PORTSC1_D: PFSC Mask           */
+#define USB1_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_D: PSPD Position       */
+#define USB1_PORTSC1_D_PSPD_Msk                               (0x03UL << USB1_PORTSC1_D_PSPD_Pos)                       /*!< USB1 PORTSC1_D: PSPD Mask           */
+#define USB1_PORTSC1_D_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_D: PTS Position        */
+#define USB1_PORTSC1_D_PTS_Msk                                (0x03UL << USB1_PORTSC1_D_PTS_Pos)                        /*!< USB1 PORTSC1_D: PTS Mask            */
+
+// -------------------------------------  USB1_PORTSC1_H  -----------------------------------------
+#define USB1_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_H: CCS Position        */
+#define USB1_PORTSC1_H_CCS_Msk                                (0x01UL << USB1_PORTSC1_H_CCS_Pos)                        /*!< USB1 PORTSC1_H: CCS Mask            */
+#define USB1_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_H: CSC Position        */
+#define USB1_PORTSC1_H_CSC_Msk                                (0x01UL << USB1_PORTSC1_H_CSC_Pos)                        /*!< USB1 PORTSC1_H: CSC Mask            */
+#define USB1_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_H: PE Position         */
+#define USB1_PORTSC1_H_PE_Msk                                 (0x01UL << USB1_PORTSC1_H_PE_Pos)                         /*!< USB1 PORTSC1_H: PE Mask             */
+#define USB1_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_H: PEC Position        */
+#define USB1_PORTSC1_H_PEC_Msk                                (0x01UL << USB1_PORTSC1_H_PEC_Pos)                        /*!< USB1 PORTSC1_H: PEC Mask            */
+#define USB1_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB1 PORTSC1_H: OCA Position        */
+#define USB1_PORTSC1_H_OCA_Msk                                (0x01UL << USB1_PORTSC1_H_OCA_Pos)                        /*!< USB1 PORTSC1_H: OCA Mask            */
+#define USB1_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB1 PORTSC1_H: OCC Position        */
+#define USB1_PORTSC1_H_OCC_Msk                                (0x01UL << USB1_PORTSC1_H_OCC_Pos)                        /*!< USB1 PORTSC1_H: OCC Mask            */
+#define USB1_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_H: FPR Position        */
+#define USB1_PORTSC1_H_FPR_Msk                                (0x01UL << USB1_PORTSC1_H_FPR_Pos)                        /*!< USB1 PORTSC1_H: FPR Mask            */
+#define USB1_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_H: SUSP Position       */
+#define USB1_PORTSC1_H_SUSP_Msk                               (0x01UL << USB1_PORTSC1_H_SUSP_Pos)                       /*!< USB1 PORTSC1_H: SUSP Mask           */
+#define USB1_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_H: PR Position         */
+#define USB1_PORTSC1_H_PR_Msk                                 (0x01UL << USB1_PORTSC1_H_PR_Pos)                         /*!< USB1 PORTSC1_H: PR Mask             */
+#define USB1_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_H: HSP Position        */
+#define USB1_PORTSC1_H_HSP_Msk                                (0x01UL << USB1_PORTSC1_H_HSP_Pos)                        /*!< USB1 PORTSC1_H: HSP Mask            */
+#define USB1_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_H: LS Position         */
+#define USB1_PORTSC1_H_LS_Msk                                 (0x03UL << USB1_PORTSC1_H_LS_Pos)                         /*!< USB1 PORTSC1_H: LS Mask             */
+#define USB1_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_H: PP Position         */
+#define USB1_PORTSC1_H_PP_Msk                                 (0x01UL << USB1_PORTSC1_H_PP_Pos)                         /*!< USB1 PORTSC1_H: PP Mask             */
+#define USB1_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_H: PIC1_0 Position     */
+#define USB1_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos)                     /*!< USB1 PORTSC1_H: PIC1_0 Mask         */
+#define USB1_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_H: PTC3_0 Position     */
+#define USB1_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos)                     /*!< USB1 PORTSC1_H: PTC3_0 Mask         */
+#define USB1_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB1 PORTSC1_H: WKCN Position       */
+#define USB1_PORTSC1_H_WKCN_Msk                               (0x01UL << USB1_PORTSC1_H_WKCN_Pos)                       /*!< USB1 PORTSC1_H: WKCN Mask           */
+#define USB1_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB1 PORTSC1_H: WKDC Position       */
+#define USB1_PORTSC1_H_WKDC_Msk                               (0x01UL << USB1_PORTSC1_H_WKDC_Pos)                       /*!< USB1 PORTSC1_H: WKDC Mask           */
+#define USB1_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB1 PORTSC1_H: WKOC Position       */
+#define USB1_PORTSC1_H_WKOC_Msk                               (0x01UL << USB1_PORTSC1_H_WKOC_Pos)                       /*!< USB1 PORTSC1_H: WKOC Mask           */
+#define USB1_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_H: PHCD Position       */
+#define USB1_PORTSC1_H_PHCD_Msk                               (0x01UL << USB1_PORTSC1_H_PHCD_Pos)                       /*!< USB1 PORTSC1_H: PHCD Mask           */
+#define USB1_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_H: PFSC Position       */
+#define USB1_PORTSC1_H_PFSC_Msk                               (0x01UL << USB1_PORTSC1_H_PFSC_Pos)                       /*!< USB1 PORTSC1_H: PFSC Mask           */
+#define USB1_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_H: PSPD Position       */
+#define USB1_PORTSC1_H_PSPD_Msk                               (0x03UL << USB1_PORTSC1_H_PSPD_Pos)                       /*!< USB1 PORTSC1_H: PSPD Mask           */
+#define USB1_PORTSC1_H_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_H: PTS Position        */
+#define USB1_PORTSC1_H_PTS_Msk                                (0x03UL << USB1_PORTSC1_H_PTS_Pos)                        /*!< USB1 PORTSC1_H: PTS Mask            */
+
+// -------------------------------------  USB1_USBMODE_D  -----------------------------------------
+#define USB1_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_D: CM1_0 Position      */
+#define USB1_USBMODE_D_CM1_0_Msk                              (0x03UL << USB1_USBMODE_D_CM1_0_Pos)                      /*!< USB1 USBMODE_D: CM1_0 Mask          */
+#define USB1_USBMODE_D_ES_Pos                                 2                                                         /*!< USB1 USBMODE_D: ES Position         */
+#define USB1_USBMODE_D_ES_Msk                                 (0x01UL << USB1_USBMODE_D_ES_Pos)                         /*!< USB1 USBMODE_D: ES Mask             */
+#define USB1_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB1 USBMODE_D: SLOM Position       */
+#define USB1_USBMODE_D_SLOM_Msk                               (0x01UL << USB1_USBMODE_D_SLOM_Pos)                       /*!< USB1 USBMODE_D: SLOM Mask           */
+#define USB1_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_D: SDIS Position       */
+#define USB1_USBMODE_D_SDIS_Msk                               (0x01UL << USB1_USBMODE_D_SDIS_Pos)                       /*!< USB1 USBMODE_D: SDIS Mask           */
+
+// -------------------------------------  USB1_USBMODE_H  -----------------------------------------
+#define USB1_USBMODE_H_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_H: CM1_0 Position      */
+#define USB1_USBMODE_H_CM1_0_Msk                              (0x03UL << USB1_USBMODE_H_CM1_0_Pos)                      /*!< USB1 USBMODE_H: CM1_0 Mask          */
+#define USB1_USBMODE_H_ES_Pos                                 2                                                         /*!< USB1 USBMODE_H: ES Position         */
+#define USB1_USBMODE_H_ES_Msk                                 (0x01UL << USB1_USBMODE_H_ES_Pos)                         /*!< USB1 USBMODE_H: ES Mask             */
+#define USB1_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_H: SDIS Position       */
+#define USB1_USBMODE_H_SDIS_Msk                               (0x01UL << USB1_USBMODE_H_SDIS_Pos)                       /*!< USB1 USBMODE_H: SDIS Mask           */
+#define USB1_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB1 USBMODE_H: VBPS Position       */
+#define USB1_USBMODE_H_VBPS_Msk                               (0x01UL << USB1_USBMODE_H_VBPS_Pos)                       /*!< USB1 USBMODE_H: VBPS Mask           */
+
+// -----------------------------------  USB1_ENDPTSETUPSTAT  --------------------------------------
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+
+// -------------------------------------  USB1_ENDPTPRIME  ----------------------------------------
+#define USB1_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB1 ENDPTPRIME: PERB0 Position     */
+#define USB1_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB0_Pos)                     /*!< USB1 ENDPTPRIME: PERB0 Mask         */
+#define USB1_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB1 ENDPTPRIME: PERB1 Position     */
+#define USB1_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB1_Pos)                     /*!< USB1 ENDPTPRIME: PERB1 Mask         */
+#define USB1_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB1 ENDPTPRIME: PERB2 Position     */
+#define USB1_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB2_Pos)                     /*!< USB1 ENDPTPRIME: PERB2 Mask         */
+#define USB1_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB1 ENDPTPRIME: PERB3 Position     */
+#define USB1_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB3_Pos)                     /*!< USB1 ENDPTPRIME: PERB3 Mask         */
+#define USB1_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB1 ENDPTPRIME: PETB0 Position     */
+#define USB1_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB0_Pos)                     /*!< USB1 ENDPTPRIME: PETB0 Mask         */
+#define USB1_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB1 ENDPTPRIME: PETB1 Position     */
+#define USB1_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB1_Pos)                     /*!< USB1 ENDPTPRIME: PETB1 Mask         */
+#define USB1_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB1 ENDPTPRIME: PETB2 Position     */
+#define USB1_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB2_Pos)                     /*!< USB1 ENDPTPRIME: PETB2 Mask         */
+#define USB1_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB1 ENDPTPRIME: PETB3 Position     */
+#define USB1_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB3_Pos)                     /*!< USB1 ENDPTPRIME: PETB3 Mask         */
+
+// -------------------------------------  USB1_ENDPTFLUSH  ----------------------------------------
+#define USB1_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB1 ENDPTFLUSH: FERB0 Position     */
+#define USB1_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos)                     /*!< USB1 ENDPTFLUSH: FERB0 Mask         */
+#define USB1_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB1 ENDPTFLUSH: FERB1 Position     */
+#define USB1_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos)                     /*!< USB1 ENDPTFLUSH: FERB1 Mask         */
+#define USB1_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB1 ENDPTFLUSH: FERB2 Position     */
+#define USB1_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos)                     /*!< USB1 ENDPTFLUSH: FERB2 Mask         */
+#define USB1_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB1 ENDPTFLUSH: FERB3 Position     */
+#define USB1_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos)                     /*!< USB1 ENDPTFLUSH: FERB3 Mask         */
+#define USB1_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB1 ENDPTFLUSH: FETB0 Position     */
+#define USB1_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos)                     /*!< USB1 ENDPTFLUSH: FETB0 Mask         */
+#define USB1_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB1 ENDPTFLUSH: FETB1 Position     */
+#define USB1_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos)                     /*!< USB1 ENDPTFLUSH: FETB1 Mask         */
+#define USB1_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB1 ENDPTFLUSH: FETB2 Position     */
+#define USB1_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos)                     /*!< USB1 ENDPTFLUSH: FETB2 Mask         */
+#define USB1_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB1 ENDPTFLUSH: FETB3 Position     */
+#define USB1_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos)                     /*!< USB1 ENDPTFLUSH: FETB3 Mask         */
+
+// -------------------------------------  USB1_ENDPTSTAT  -----------------------------------------
+#define USB1_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB1 ENDPTSTAT: ERBR0 Position      */
+#define USB1_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos)                      /*!< USB1 ENDPTSTAT: ERBR0 Mask          */
+#define USB1_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB1 ENDPTSTAT: ERBR1 Position      */
+#define USB1_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos)                      /*!< USB1 ENDPTSTAT: ERBR1 Mask          */
+#define USB1_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB1 ENDPTSTAT: ERBR2 Position      */
+#define USB1_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos)                      /*!< USB1 ENDPTSTAT: ERBR2 Mask          */
+#define USB1_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB1 ENDPTSTAT: ERBR3 Position      */
+#define USB1_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos)                      /*!< USB1 ENDPTSTAT: ERBR3 Mask          */
+#define USB1_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB1 ENDPTSTAT: ETBR0 Position      */
+#define USB1_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos)                      /*!< USB1 ENDPTSTAT: ETBR0 Mask          */
+#define USB1_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB1 ENDPTSTAT: ETBR1 Position      */
+#define USB1_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos)                      /*!< USB1 ENDPTSTAT: ETBR1 Mask          */
+#define USB1_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB1 ENDPTSTAT: ETBR2 Position      */
+#define USB1_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos)                      /*!< USB1 ENDPTSTAT: ETBR2 Mask          */
+#define USB1_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB1 ENDPTSTAT: ETBR3 Position      */
+#define USB1_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos)                      /*!< USB1 ENDPTSTAT: ETBR3 Mask          */
+
+// -----------------------------------  USB1_ENDPTCOMPLETE  ---------------------------------------
+#define USB1_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB1 ENDPTCOMPLETE: ERCE0 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask      */
+#define USB1_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB1 ENDPTCOMPLETE: ERCE1 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask      */
+#define USB1_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB1 ENDPTCOMPLETE: ERCE2 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask      */
+#define USB1_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB1 ENDPTCOMPLETE: ERCE3 Position  */
+#define USB1_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB1 ENDPTCOMPLETE: ETCE0 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB1 ENDPTCOMPLETE: ETCE1 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB1 ENDPTCOMPLETE: ETCE2 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask      */
+#define USB1_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB1 ENDPTCOMPLETE: ETCE3 Position  */
+#define USB1_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask      */
+
+// -------------------------------------  USB1_ENDPTCTRL0  ----------------------------------------
+#define USB1_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL0: RXS Position       */
+#define USB1_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXS_Pos)                       /*!< USB1 ENDPTCTRL0: RXS Mask           */
+#define USB1_ENDPTCTRL0_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL0: RXT Position       */
+#define USB1_ENDPTCTRL0_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_RXT_Pos)                       /*!< USB1 ENDPTCTRL0: RXT Mask           */
+#define USB1_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL0: RXE Position       */
+#define USB1_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXE_Pos)                       /*!< USB1 ENDPTCTRL0: RXE Mask           */
+#define USB1_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL0: TXS Position       */
+#define USB1_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXS_Pos)                       /*!< USB1 ENDPTCTRL0: TXS Mask           */
+#define USB1_ENDPTCTRL0_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL0: TXT Position       */
+#define USB1_ENDPTCTRL0_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_TXT_Pos)                       /*!< USB1 ENDPTCTRL0: TXT Mask           */
+#define USB1_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL0: TXE Position       */
+#define USB1_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXE_Pos)                       /*!< USB1 ENDPTCTRL0: TXE Mask           */
+
+// -------------------------------------  USB1_ENDPTCTRL1  ----------------------------------------
+#define USB1_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL1: RXS Position       */
+#define USB1_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXS_Pos)                       /*!< USB1 ENDPTCTRL1: RXS Mask           */
+#define USB1_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL1: RXT Position       */
+#define USB1_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_RXT_Pos)                       /*!< USB1 ENDPTCTRL1: RXT Mask           */
+#define USB1_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL1: RXI Position       */
+#define USB1_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXI_Pos)                       /*!< USB1 ENDPTCTRL1: RXI Mask           */
+#define USB1_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL1: RXR Position       */
+#define USB1_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXR_Pos)                       /*!< USB1 ENDPTCTRL1: RXR Mask           */
+#define USB1_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL1: RXE Position       */
+#define USB1_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXE_Pos)                       /*!< USB1 ENDPTCTRL1: RXE Mask           */
+#define USB1_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL1: TXS Position       */
+#define USB1_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXS_Pos)                       /*!< USB1 ENDPTCTRL1: TXS Mask           */
+#define USB1_ENDPTCTRL1_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL1: TXT Position       */
+#define USB1_ENDPTCTRL1_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_TXT_Pos)                       /*!< USB1 ENDPTCTRL1: TXT Mask           */
+#define USB1_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL1: TXI Position       */
+#define USB1_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXI_Pos)                       /*!< USB1 ENDPTCTRL1: TXI Mask           */
+#define USB1_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL1: TXR Position       */
+#define USB1_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXR_Pos)                       /*!< USB1 ENDPTCTRL1: TXR Mask           */
+#define USB1_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL1: TXE Position       */
+#define USB1_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXE_Pos)                       /*!< USB1 ENDPTCTRL1: TXE Mask           */
+
+// -------------------------------------  USB1_ENDPTCTRL2  ----------------------------------------
+#define USB1_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL2: RXS Position       */
+#define USB1_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXS_Pos)                       /*!< USB1 ENDPTCTRL2: RXS Mask           */
+#define USB1_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL2: RXT Position       */
+#define USB1_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_RXT_Pos)                       /*!< USB1 ENDPTCTRL2: RXT Mask           */
+#define USB1_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL2: RXI Position       */
+#define USB1_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXI_Pos)                       /*!< USB1 ENDPTCTRL2: RXI Mask           */
+#define USB1_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL2: RXR Position       */
+#define USB1_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXR_Pos)                       /*!< USB1 ENDPTCTRL2: RXR Mask           */
+#define USB1_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL2: RXE Position       */
+#define USB1_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXE_Pos)                       /*!< USB1 ENDPTCTRL2: RXE Mask           */
+#define USB1_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL2: TXS Position       */
+#define USB1_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXS_Pos)                       /*!< USB1 ENDPTCTRL2: TXS Mask           */
+#define USB1_ENDPTCTRL2_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL2: TXT Position       */
+#define USB1_ENDPTCTRL2_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_TXT_Pos)                       /*!< USB1 ENDPTCTRL2: TXT Mask           */
+#define USB1_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL2: TXI Position       */
+#define USB1_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXI_Pos)                       /*!< USB1 ENDPTCTRL2: TXI Mask           */
+#define USB1_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL2: TXR Position       */
+#define USB1_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXR_Pos)                       /*!< USB1 ENDPTCTRL2: TXR Mask           */
+#define USB1_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL2: TXE Position       */
+#define USB1_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXE_Pos)                       /*!< USB1 ENDPTCTRL2: TXE Mask           */
+
+// -------------------------------------  USB1_ENDPTCTRL3  ----------------------------------------
+#define USB1_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL3: RXS Position       */
+#define USB1_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXS_Pos)                       /*!< USB1 ENDPTCTRL3: RXS Mask           */
+#define USB1_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL3: RXT Position       */
+#define USB1_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_RXT_Pos)                       /*!< USB1 ENDPTCTRL3: RXT Mask           */
+#define USB1_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL3: RXI Position       */
+#define USB1_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXI_Pos)                       /*!< USB1 ENDPTCTRL3: RXI Mask           */
+#define USB1_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL3: RXR Position       */
+#define USB1_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXR_Pos)                       /*!< USB1 ENDPTCTRL3: RXR Mask           */
+#define USB1_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL3: RXE Position       */
+#define USB1_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXE_Pos)                       /*!< USB1 ENDPTCTRL3: RXE Mask           */
+#define USB1_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL3: TXS Position       */
+#define USB1_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXS_Pos)                       /*!< USB1 ENDPTCTRL3: TXS Mask           */
+#define USB1_ENDPTCTRL3_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL3: TXT Position       */
+#define USB1_ENDPTCTRL3_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_TXT_Pos)                       /*!< USB1 ENDPTCTRL3: TXT Mask           */
+#define USB1_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL3: TXI Position       */
+#define USB1_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXI_Pos)                       /*!< USB1 ENDPTCTRL3: TXI Mask           */
+#define USB1_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL3: TXR Position       */
+#define USB1_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXR_Pos)                       /*!< USB1 ENDPTCTRL3: TXR Mask           */
+#define USB1_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL3: TXE Position       */
+#define USB1_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXE_Pos)                       /*!< USB1 ENDPTCTRL3: TXE Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  LCD Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  LCD_TIMH  --------------------------------------------
+#define LCD_TIMH_PPL_Pos                                      2                                                         /*!< LCD TIMH: PPL Position              */
+#define LCD_TIMH_PPL_Msk                                      (0x3fUL << LCD_TIMH_PPL_Pos)                              /*!< LCD TIMH: PPL Mask                  */
+#define LCD_TIMH_HSW_Pos                                      8                                                         /*!< LCD TIMH: HSW Position              */
+#define LCD_TIMH_HSW_Msk                                      (0x000000ffUL << LCD_TIMH_HSW_Pos)                        /*!< LCD TIMH: HSW Mask                  */
+#define LCD_TIMH_HFP_Pos                                      16                                                        /*!< LCD TIMH: HFP Position              */
+#define LCD_TIMH_HFP_Msk                                      (0x000000ffUL << LCD_TIMH_HFP_Pos)                        /*!< LCD TIMH: HFP Mask                  */
+#define LCD_TIMH_HBP_Pos                                      24                                                        /*!< LCD TIMH: HBP Position              */
+#define LCD_TIMH_HBP_Msk                                      (0x000000ffUL << LCD_TIMH_HBP_Pos)                        /*!< LCD TIMH: HBP Mask                  */
+
+// ----------------------------------------  LCD_TIMV  --------------------------------------------
+#define LCD_TIMV_LPP_Pos                                      0                                                         /*!< LCD TIMV: LPP Position              */
+#define LCD_TIMV_LPP_Msk                                      (0x000003ffUL << LCD_TIMV_LPP_Pos)                        /*!< LCD TIMV: LPP Mask                  */
+#define LCD_TIMV_VSW_Pos                                      10                                                        /*!< LCD TIMV: VSW Position              */
+#define LCD_TIMV_VSW_Msk                                      (0x3fUL << LCD_TIMV_VSW_Pos)                              /*!< LCD TIMV: VSW Mask                  */
+#define LCD_TIMV_VFP_Pos                                      16                                                        /*!< LCD TIMV: VFP Position              */
+#define LCD_TIMV_VFP_Msk                                      (0x000000ffUL << LCD_TIMV_VFP_Pos)                        /*!< LCD TIMV: VFP Mask                  */
+#define LCD_TIMV_VBP_Pos                                      24                                                        /*!< LCD TIMV: VBP Position              */
+#define LCD_TIMV_VBP_Msk                                      (0x000000ffUL << LCD_TIMV_VBP_Pos)                        /*!< LCD TIMV: VBP Mask                  */
+
+// -----------------------------------------  LCD_POL  --------------------------------------------
+#define LCD_POL_PCD_LO_Pos                                    0                                                         /*!< LCD POL: PCD_LO Position            */
+#define LCD_POL_PCD_LO_Msk                                    (0x1fUL << LCD_POL_PCD_LO_Pos)                            /*!< LCD POL: PCD_LO Mask                */
+#define LCD_POL_CLKSEL_Pos                                    5                                                         /*!< LCD POL: CLKSEL Position            */
+#define LCD_POL_CLKSEL_Msk                                    (0x01UL << LCD_POL_CLKSEL_Pos)                            /*!< LCD POL: CLKSEL Mask                */
+#define LCD_POL_ACB_Pos                                       6                                                         /*!< LCD POL: ACB Position               */
+#define LCD_POL_ACB_Msk                                       (0x1fUL << LCD_POL_ACB_Pos)                               /*!< LCD POL: ACB Mask                   */
+#define LCD_POL_IVS_Pos                                       11                                                        /*!< LCD POL: IVS Position               */
+#define LCD_POL_IVS_Msk                                       (0x01UL << LCD_POL_IVS_Pos)                               /*!< LCD POL: IVS Mask                   */
+#define LCD_POL_IHS_Pos                                       12                                                        /*!< LCD POL: IHS Position               */
+#define LCD_POL_IHS_Msk                                       (0x01UL << LCD_POL_IHS_Pos)                               /*!< LCD POL: IHS Mask                   */
+#define LCD_POL_IPC_Pos                                       13                                                        /*!< LCD POL: IPC Position               */
+#define LCD_POL_IPC_Msk                                       (0x01UL << LCD_POL_IPC_Pos)                               /*!< LCD POL: IPC Mask                   */
+#define LCD_POL_IOE_Pos                                       14                                                        /*!< LCD POL: IOE Position               */
+#define LCD_POL_IOE_Msk                                       (0x01UL << LCD_POL_IOE_Pos)                               /*!< LCD POL: IOE Mask                   */
+#define LCD_POL_CPL_Pos                                       16                                                        /*!< LCD POL: CPL Position               */
+#define LCD_POL_CPL_Msk                                       (0x000003ffUL << LCD_POL_CPL_Pos)                         /*!< LCD POL: CPL Mask                   */
+#define LCD_POL_BCD_Pos                                       26                                                        /*!< LCD POL: BCD Position               */
+#define LCD_POL_BCD_Msk                                       (0x01UL << LCD_POL_BCD_Pos)                               /*!< LCD POL: BCD Mask                   */
+#define LCD_POL_PCD_HI_Pos                                    27                                                        /*!< LCD POL: PCD_HI Position            */
+#define LCD_POL_PCD_HI_Msk                                    (0x1fUL << LCD_POL_PCD_HI_Pos)                            /*!< LCD POL: PCD_HI Mask                */
+
+// -----------------------------------------  LCD_LE  ---------------------------------------------
+#define LCD_LE_LED_Pos                                        0                                                         /*!< LCD LE: LED Position                */
+#define LCD_LE_LED_Msk                                        (0x7fUL << LCD_LE_LED_Pos)                                /*!< LCD LE: LED Mask                    */
+#define LCD_LE_LEE_Pos                                        16                                                        /*!< LCD LE: LEE Position                */
+#define LCD_LE_LEE_Msk                                        (0x01UL << LCD_LE_LEE_Pos)                                /*!< LCD LE: LEE Mask                    */
+
+// ---------------------------------------  LCD_UPBASE  -------------------------------------------
+#define LCD_UPBASE_LCDUPBASE_Pos                              3                                                         /*!< LCD UPBASE: LCDUPBASE Position      */
+#define LCD_UPBASE_LCDUPBASE_Msk                              (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos)                /*!< LCD UPBASE: LCDUPBASE Mask          */
+
+// ---------------------------------------  LCD_LPBASE  -------------------------------------------
+#define LCD_LPBASE_LCDLPBASE_Pos                              3                                                         /*!< LCD LPBASE: LCDLPBASE Position      */
+#define LCD_LPBASE_LCDLPBASE_Msk                              (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos)                /*!< LCD LPBASE: LCDLPBASE Mask          */
+
+// ----------------------------------------  LCD_CTRL  --------------------------------------------
+#define LCD_CTRL_LCDEN_Pos                                    0                                                         /*!< LCD CTRL: LCDEN Position            */
+#define LCD_CTRL_LCDEN_Msk                                    (0x01UL << LCD_CTRL_LCDEN_Pos)                            /*!< LCD CTRL: LCDEN Mask                */
+#define LCD_CTRL_LCDBPP_Pos                                   1                                                         /*!< LCD CTRL: LCDBPP Position           */
+#define LCD_CTRL_LCDBPP_Msk                                   (0x07UL << LCD_CTRL_LCDBPP_Pos)                           /*!< LCD CTRL: LCDBPP Mask               */
+#define LCD_CTRL_LCDBW_Pos                                    4                                                         /*!< LCD CTRL: LCDBW Position            */
+#define LCD_CTRL_LCDBW_Msk                                    (0x01UL << LCD_CTRL_LCDBW_Pos)                            /*!< LCD CTRL: LCDBW Mask                */
+#define LCD_CTRL_LCDTFT_Pos                                   5                                                         /*!< LCD CTRL: LCDTFT Position           */
+#define LCD_CTRL_LCDTFT_Msk                                   (0x01UL << LCD_CTRL_LCDTFT_Pos)                           /*!< LCD CTRL: LCDTFT Mask               */
+#define LCD_CTRL_LCDMONO8_Pos                                 6                                                         /*!< LCD CTRL: LCDMONO8 Position         */
+#define LCD_CTRL_LCDMONO8_Msk                                 (0x01UL << LCD_CTRL_LCDMONO8_Pos)                         /*!< LCD CTRL: LCDMONO8 Mask             */
+#define LCD_CTRL_LCDDUAL_Pos                                  7                                                         /*!< LCD CTRL: LCDDUAL Position          */
+#define LCD_CTRL_LCDDUAL_Msk                                  (0x01UL << LCD_CTRL_LCDDUAL_Pos)                          /*!< LCD CTRL: LCDDUAL Mask              */
+#define LCD_CTRL_BGR_Pos                                      8                                                         /*!< LCD CTRL: BGR Position              */
+#define LCD_CTRL_BGR_Msk                                      (0x01UL << LCD_CTRL_BGR_Pos)                              /*!< LCD CTRL: BGR Mask                  */
+#define LCD_CTRL_BEBO_Pos                                     9                                                         /*!< LCD CTRL: BEBO Position             */
+#define LCD_CTRL_BEBO_Msk                                     (0x01UL << LCD_CTRL_BEBO_Pos)                             /*!< LCD CTRL: BEBO Mask                 */
+#define LCD_CTRL_BEPO_Pos                                     10                                                        /*!< LCD CTRL: BEPO Position             */
+#define LCD_CTRL_BEPO_Msk                                     (0x01UL << LCD_CTRL_BEPO_Pos)                             /*!< LCD CTRL: BEPO Mask                 */
+#define LCD_CTRL_LCDPWR_Pos                                   11                                                        /*!< LCD CTRL: LCDPWR Position           */
+#define LCD_CTRL_LCDPWR_Msk                                   (0x01UL << LCD_CTRL_LCDPWR_Pos)                           /*!< LCD CTRL: LCDPWR Mask               */
+#define LCD_CTRL_LCDVCOMP_Pos                                 12                                                        /*!< LCD CTRL: LCDVCOMP Position         */
+#define LCD_CTRL_LCDVCOMP_Msk                                 (0x03UL << LCD_CTRL_LCDVCOMP_Pos)                         /*!< LCD CTRL: LCDVCOMP Mask             */
+#define LCD_CTRL_WATERMARK_Pos                                16                                                        /*!< LCD CTRL: WATERMARK Position        */
+#define LCD_CTRL_WATERMARK_Msk                                (0x01UL << LCD_CTRL_WATERMARK_Pos)                        /*!< LCD CTRL: WATERMARK Mask            */
+
+// ---------------------------------------  LCD_INTMSK  -------------------------------------------
+#define LCD_INTMSK_FUFIM_Pos                                  1                                                         /*!< LCD INTMSK: FUFIM Position          */
+#define LCD_INTMSK_FUFIM_Msk                                  (0x01UL << LCD_INTMSK_FUFIM_Pos)                          /*!< LCD INTMSK: FUFIM Mask              */
+#define LCD_INTMSK_LNBUIM_Pos                                 2                                                         /*!< LCD INTMSK: LNBUIM Position         */
+#define LCD_INTMSK_LNBUIM_Msk                                 (0x01UL << LCD_INTMSK_LNBUIM_Pos)                         /*!< LCD INTMSK: LNBUIM Mask             */
+#define LCD_INTMSK_VCOMPIM_Pos                                3                                                         /*!< LCD INTMSK: VCOMPIM Position        */
+#define LCD_INTMSK_VCOMPIM_Msk                                (0x01UL << LCD_INTMSK_VCOMPIM_Pos)                        /*!< LCD INTMSK: VCOMPIM Mask            */
+#define LCD_INTMSK_BERIM_Pos                                  4                                                         /*!< LCD INTMSK: BERIM Position          */
+#define LCD_INTMSK_BERIM_Msk                                  (0x01UL << LCD_INTMSK_BERIM_Pos)                          /*!< LCD INTMSK: BERIM Mask              */
+
+// ---------------------------------------  LCD_INTRAW  -------------------------------------------
+#define LCD_INTRAW_FUFRIS_Pos                                 1                                                         /*!< LCD INTRAW: FUFRIS Position         */
+#define LCD_INTRAW_FUFRIS_Msk                                 (0x01UL << LCD_INTRAW_FUFRIS_Pos)                         /*!< LCD INTRAW: FUFRIS Mask             */
+#define LCD_INTRAW_LNBURIS_Pos                                2                                                         /*!< LCD INTRAW: LNBURIS Position        */
+#define LCD_INTRAW_LNBURIS_Msk                                (0x01UL << LCD_INTRAW_LNBURIS_Pos)                        /*!< LCD INTRAW: LNBURIS Mask            */
+#define LCD_INTRAW_VCOMPRIS_Pos                               3                                                         /*!< LCD INTRAW: VCOMPRIS Position       */
+#define LCD_INTRAW_VCOMPRIS_Msk                               (0x01UL << LCD_INTRAW_VCOMPRIS_Pos)                       /*!< LCD INTRAW: VCOMPRIS Mask           */
+#define LCD_INTRAW_BERRAW_Pos                                 4                                                         /*!< LCD INTRAW: BERRAW Position         */
+#define LCD_INTRAW_BERRAW_Msk                                 (0x01UL << LCD_INTRAW_BERRAW_Pos)                         /*!< LCD INTRAW: BERRAW Mask             */
+
+// ---------------------------------------  LCD_INTSTAT  ------------------------------------------
+#define LCD_INTSTAT_FUFMIS_Pos                                1                                                         /*!< LCD INTSTAT: FUFMIS Position        */
+#define LCD_INTSTAT_FUFMIS_Msk                                (0x01UL << LCD_INTSTAT_FUFMIS_Pos)                        /*!< LCD INTSTAT: FUFMIS Mask            */
+#define LCD_INTSTAT_LNBUMIS_Pos                               2                                                         /*!< LCD INTSTAT: LNBUMIS Position       */
+#define LCD_INTSTAT_LNBUMIS_Msk                               (0x01UL << LCD_INTSTAT_LNBUMIS_Pos)                       /*!< LCD INTSTAT: LNBUMIS Mask           */
+#define LCD_INTSTAT_VCOMPMIS_Pos                              3                                                         /*!< LCD INTSTAT: VCOMPMIS Position      */
+#define LCD_INTSTAT_VCOMPMIS_Msk                              (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos)                      /*!< LCD INTSTAT: VCOMPMIS Mask          */
+#define LCD_INTSTAT_BERMIS_Pos                                4                                                         /*!< LCD INTSTAT: BERMIS Position        */
+#define LCD_INTSTAT_BERMIS_Msk                                (0x01UL << LCD_INTSTAT_BERMIS_Pos)                        /*!< LCD INTSTAT: BERMIS Mask            */
+
+// ---------------------------------------  LCD_INTCLR  -------------------------------------------
+#define LCD_INTCLR_FUFIC_Pos                                  1                                                         /*!< LCD INTCLR: FUFIC Position          */
+#define LCD_INTCLR_FUFIC_Msk                                  (0x01UL << LCD_INTCLR_FUFIC_Pos)                          /*!< LCD INTCLR: FUFIC Mask              */
+#define LCD_INTCLR_LNBUIC_Pos                                 2                                                         /*!< LCD INTCLR: LNBUIC Position         */
+#define LCD_INTCLR_LNBUIC_Msk                                 (0x01UL << LCD_INTCLR_LNBUIC_Pos)                         /*!< LCD INTCLR: LNBUIC Mask             */
+#define LCD_INTCLR_VCOMPIC_Pos                                3                                                         /*!< LCD INTCLR: VCOMPIC Position        */
+#define LCD_INTCLR_VCOMPIC_Msk                                (0x01UL << LCD_INTCLR_VCOMPIC_Pos)                        /*!< LCD INTCLR: VCOMPIC Mask            */
+#define LCD_INTCLR_BERIC_Pos                                  4                                                         /*!< LCD INTCLR: BERIC Position          */
+#define LCD_INTCLR_BERIC_Msk                                  (0x01UL << LCD_INTCLR_BERIC_Pos)                          /*!< LCD INTCLR: BERIC Mask              */
+
+// ---------------------------------------  LCD_UPCURR  -------------------------------------------
+#define LCD_UPCURR_LCDUPCURR_Pos                              0                                                         /*!< LCD UPCURR: LCDUPCURR Position      */
+#define LCD_UPCURR_LCDUPCURR_Msk                              (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos)                /*!< LCD UPCURR: LCDUPCURR Mask          */
+
+// ---------------------------------------  LCD_LPCURR  -------------------------------------------
+#define LCD_LPCURR_LCDLPCURR_Pos                              0                                                         /*!< LCD LPCURR: LCDLPCURR Position      */
+#define LCD_LPCURR_LCDLPCURR_Msk                              (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos)                /*!< LCD LPCURR: LCDLPCURR Mask          */
+
+// ----------------------------------------  LCD_PAL0  --------------------------------------------
+#define LCD_PAL0_R04_0_Pos                                    0                                                         /*!< LCD PAL0: R04_0 Position            */
+#define LCD_PAL0_R04_0_Msk                                    (0x1fUL << LCD_PAL0_R04_0_Pos)                            /*!< LCD PAL0: R04_0 Mask                */
+#define LCD_PAL0_G04_0_Pos                                    5                                                         /*!< LCD PAL0: G04_0 Position            */
+#define LCD_PAL0_G04_0_Msk                                    (0x1fUL << LCD_PAL0_G04_0_Pos)                            /*!< LCD PAL0: G04_0 Mask                */
+#define LCD_PAL0_B04_0_Pos                                    10                                                        /*!< LCD PAL0: B04_0 Position            */
+#define LCD_PAL0_B04_0_Msk                                    (0x1fUL << LCD_PAL0_B04_0_Pos)                            /*!< LCD PAL0: B04_0 Mask                */
+#define LCD_PAL0_I0_Pos                                       15                                                        /*!< LCD PAL0: I0 Position               */
+#define LCD_PAL0_I0_Msk                                       (0x01UL << LCD_PAL0_I0_Pos)                               /*!< LCD PAL0: I0 Mask                   */
+#define LCD_PAL0_R14_0_Pos                                    16                                                        /*!< LCD PAL0: R14_0 Position            */
+#define LCD_PAL0_R14_0_Msk                                    (0x1fUL << LCD_PAL0_R14_0_Pos)                            /*!< LCD PAL0: R14_0 Mask                */
+#define LCD_PAL0_G14_0_Pos                                    21                                                        /*!< LCD PAL0: G14_0 Position            */
+#define LCD_PAL0_G14_0_Msk                                    (0x1fUL << LCD_PAL0_G14_0_Pos)                            /*!< LCD PAL0: G14_0 Mask                */
+#define LCD_PAL0_B14_0_Pos                                    26                                                        /*!< LCD PAL0: B14_0 Position            */
+#define LCD_PAL0_B14_0_Msk                                    (0x1fUL << LCD_PAL0_B14_0_Pos)                            /*!< LCD PAL0: B14_0 Mask                */
+#define LCD_PAL0_I1_Pos                                       31                                                        /*!< LCD PAL0: I1 Position               */
+#define LCD_PAL0_I1_Msk                                       (0x01UL << LCD_PAL0_I1_Pos)                               /*!< LCD PAL0: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL1  --------------------------------------------
+#define LCD_PAL1_R04_0_Pos                                    0                                                         /*!< LCD PAL1: R04_0 Position            */
+#define LCD_PAL1_R04_0_Msk                                    (0x1fUL << LCD_PAL1_R04_0_Pos)                            /*!< LCD PAL1: R04_0 Mask                */
+#define LCD_PAL1_G04_0_Pos                                    5                                                         /*!< LCD PAL1: G04_0 Position            */
+#define LCD_PAL1_G04_0_Msk                                    (0x1fUL << LCD_PAL1_G04_0_Pos)                            /*!< LCD PAL1: G04_0 Mask                */
+#define LCD_PAL1_B04_0_Pos                                    10                                                        /*!< LCD PAL1: B04_0 Position            */
+#define LCD_PAL1_B04_0_Msk                                    (0x1fUL << LCD_PAL1_B04_0_Pos)                            /*!< LCD PAL1: B04_0 Mask                */
+#define LCD_PAL1_I0_Pos                                       15                                                        /*!< LCD PAL1: I0 Position               */
+#define LCD_PAL1_I0_Msk                                       (0x01UL << LCD_PAL1_I0_Pos)                               /*!< LCD PAL1: I0 Mask                   */
+#define LCD_PAL1_R14_0_Pos                                    16                                                        /*!< LCD PAL1: R14_0 Position            */
+#define LCD_PAL1_R14_0_Msk                                    (0x1fUL << LCD_PAL1_R14_0_Pos)                            /*!< LCD PAL1: R14_0 Mask                */
+#define LCD_PAL1_G14_0_Pos                                    21                                                        /*!< LCD PAL1: G14_0 Position            */
+#define LCD_PAL1_G14_0_Msk                                    (0x1fUL << LCD_PAL1_G14_0_Pos)                            /*!< LCD PAL1: G14_0 Mask                */
+#define LCD_PAL1_B14_0_Pos                                    26                                                        /*!< LCD PAL1: B14_0 Position            */
+#define LCD_PAL1_B14_0_Msk                                    (0x1fUL << LCD_PAL1_B14_0_Pos)                            /*!< LCD PAL1: B14_0 Mask                */
+#define LCD_PAL1_I1_Pos                                       31                                                        /*!< LCD PAL1: I1 Position               */
+#define LCD_PAL1_I1_Msk                                       (0x01UL << LCD_PAL1_I1_Pos)                               /*!< LCD PAL1: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL2  --------------------------------------------
+#define LCD_PAL2_R04_0_Pos                                    0                                                         /*!< LCD PAL2: R04_0 Position            */
+#define LCD_PAL2_R04_0_Msk                                    (0x1fUL << LCD_PAL2_R04_0_Pos)                            /*!< LCD PAL2: R04_0 Mask                */
+#define LCD_PAL2_G04_0_Pos                                    5                                                         /*!< LCD PAL2: G04_0 Position            */
+#define LCD_PAL2_G04_0_Msk                                    (0x1fUL << LCD_PAL2_G04_0_Pos)                            /*!< LCD PAL2: G04_0 Mask                */
+#define LCD_PAL2_B04_0_Pos                                    10                                                        /*!< LCD PAL2: B04_0 Position            */
+#define LCD_PAL2_B04_0_Msk                                    (0x1fUL << LCD_PAL2_B04_0_Pos)                            /*!< LCD PAL2: B04_0 Mask                */
+#define LCD_PAL2_I0_Pos                                       15                                                        /*!< LCD PAL2: I0 Position               */
+#define LCD_PAL2_I0_Msk                                       (0x01UL << LCD_PAL2_I0_Pos)                               /*!< LCD PAL2: I0 Mask                   */
+#define LCD_PAL2_R14_0_Pos                                    16                                                        /*!< LCD PAL2: R14_0 Position            */
+#define LCD_PAL2_R14_0_Msk                                    (0x1fUL << LCD_PAL2_R14_0_Pos)                            /*!< LCD PAL2: R14_0 Mask                */
+#define LCD_PAL2_G14_0_Pos                                    21                                                        /*!< LCD PAL2: G14_0 Position            */
+#define LCD_PAL2_G14_0_Msk                                    (0x1fUL << LCD_PAL2_G14_0_Pos)                            /*!< LCD PAL2: G14_0 Mask                */
+#define LCD_PAL2_B14_0_Pos                                    26                                                        /*!< LCD PAL2: B14_0 Position            */
+#define LCD_PAL2_B14_0_Msk                                    (0x1fUL << LCD_PAL2_B14_0_Pos)                            /*!< LCD PAL2: B14_0 Mask                */
+#define LCD_PAL2_I1_Pos                                       31                                                        /*!< LCD PAL2: I1 Position               */
+#define LCD_PAL2_I1_Msk                                       (0x01UL << LCD_PAL2_I1_Pos)                               /*!< LCD PAL2: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL3  --------------------------------------------
+#define LCD_PAL3_R04_0_Pos                                    0                                                         /*!< LCD PAL3: R04_0 Position            */
+#define LCD_PAL3_R04_0_Msk                                    (0x1fUL << LCD_PAL3_R04_0_Pos)                            /*!< LCD PAL3: R04_0 Mask                */
+#define LCD_PAL3_G04_0_Pos                                    5                                                         /*!< LCD PAL3: G04_0 Position            */
+#define LCD_PAL3_G04_0_Msk                                    (0x1fUL << LCD_PAL3_G04_0_Pos)                            /*!< LCD PAL3: G04_0 Mask                */
+#define LCD_PAL3_B04_0_Pos                                    10                                                        /*!< LCD PAL3: B04_0 Position            */
+#define LCD_PAL3_B04_0_Msk                                    (0x1fUL << LCD_PAL3_B04_0_Pos)                            /*!< LCD PAL3: B04_0 Mask                */
+#define LCD_PAL3_I0_Pos                                       15                                                        /*!< LCD PAL3: I0 Position               */
+#define LCD_PAL3_I0_Msk                                       (0x01UL << LCD_PAL3_I0_Pos)                               /*!< LCD PAL3: I0 Mask                   */
+#define LCD_PAL3_R14_0_Pos                                    16                                                        /*!< LCD PAL3: R14_0 Position            */
+#define LCD_PAL3_R14_0_Msk                                    (0x1fUL << LCD_PAL3_R14_0_Pos)                            /*!< LCD PAL3: R14_0 Mask                */
+#define LCD_PAL3_G14_0_Pos                                    21                                                        /*!< LCD PAL3: G14_0 Position            */
+#define LCD_PAL3_G14_0_Msk                                    (0x1fUL << LCD_PAL3_G14_0_Pos)                            /*!< LCD PAL3: G14_0 Mask                */
+#define LCD_PAL3_B14_0_Pos                                    26                                                        /*!< LCD PAL3: B14_0 Position            */
+#define LCD_PAL3_B14_0_Msk                                    (0x1fUL << LCD_PAL3_B14_0_Pos)                            /*!< LCD PAL3: B14_0 Mask                */
+#define LCD_PAL3_I1_Pos                                       31                                                        /*!< LCD PAL3: I1 Position               */
+#define LCD_PAL3_I1_Msk                                       (0x01UL << LCD_PAL3_I1_Pos)                               /*!< LCD PAL3: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL4  --------------------------------------------
+#define LCD_PAL4_R04_0_Pos                                    0                                                         /*!< LCD PAL4: R04_0 Position            */
+#define LCD_PAL4_R04_0_Msk                                    (0x1fUL << LCD_PAL4_R04_0_Pos)                            /*!< LCD PAL4: R04_0 Mask                */
+#define LCD_PAL4_G04_0_Pos                                    5                                                         /*!< LCD PAL4: G04_0 Position            */
+#define LCD_PAL4_G04_0_Msk                                    (0x1fUL << LCD_PAL4_G04_0_Pos)                            /*!< LCD PAL4: G04_0 Mask                */
+#define LCD_PAL4_B04_0_Pos                                    10                                                        /*!< LCD PAL4: B04_0 Position            */
+#define LCD_PAL4_B04_0_Msk                                    (0x1fUL << LCD_PAL4_B04_0_Pos)                            /*!< LCD PAL4: B04_0 Mask                */
+#define LCD_PAL4_I0_Pos                                       15                                                        /*!< LCD PAL4: I0 Position               */
+#define LCD_PAL4_I0_Msk                                       (0x01UL << LCD_PAL4_I0_Pos)                               /*!< LCD PAL4: I0 Mask                   */
+#define LCD_PAL4_R14_0_Pos                                    16                                                        /*!< LCD PAL4: R14_0 Position            */
+#define LCD_PAL4_R14_0_Msk                                    (0x1fUL << LCD_PAL4_R14_0_Pos)                            /*!< LCD PAL4: R14_0 Mask                */
+#define LCD_PAL4_G14_0_Pos                                    21                                                        /*!< LCD PAL4: G14_0 Position            */
+#define LCD_PAL4_G14_0_Msk                                    (0x1fUL << LCD_PAL4_G14_0_Pos)                            /*!< LCD PAL4: G14_0 Mask                */
+#define LCD_PAL4_B14_0_Pos                                    26                                                        /*!< LCD PAL4: B14_0 Position            */
+#define LCD_PAL4_B14_0_Msk                                    (0x1fUL << LCD_PAL4_B14_0_Pos)                            /*!< LCD PAL4: B14_0 Mask                */
+#define LCD_PAL4_I1_Pos                                       31                                                        /*!< LCD PAL4: I1 Position               */
+#define LCD_PAL4_I1_Msk                                       (0x01UL << LCD_PAL4_I1_Pos)                               /*!< LCD PAL4: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL5  --------------------------------------------
+#define LCD_PAL5_R04_0_Pos                                    0                                                         /*!< LCD PAL5: R04_0 Position            */
+#define LCD_PAL5_R04_0_Msk                                    (0x1fUL << LCD_PAL5_R04_0_Pos)                            /*!< LCD PAL5: R04_0 Mask                */
+#define LCD_PAL5_G04_0_Pos                                    5                                                         /*!< LCD PAL5: G04_0 Position            */
+#define LCD_PAL5_G04_0_Msk                                    (0x1fUL << LCD_PAL5_G04_0_Pos)                            /*!< LCD PAL5: G04_0 Mask                */
+#define LCD_PAL5_B04_0_Pos                                    10                                                        /*!< LCD PAL5: B04_0 Position            */
+#define LCD_PAL5_B04_0_Msk                                    (0x1fUL << LCD_PAL5_B04_0_Pos)                            /*!< LCD PAL5: B04_0 Mask                */
+#define LCD_PAL5_I0_Pos                                       15                                                        /*!< LCD PAL5: I0 Position               */
+#define LCD_PAL5_I0_Msk                                       (0x01UL << LCD_PAL5_I0_Pos)                               /*!< LCD PAL5: I0 Mask                   */
+#define LCD_PAL5_R14_0_Pos                                    16                                                        /*!< LCD PAL5: R14_0 Position            */
+#define LCD_PAL5_R14_0_Msk                                    (0x1fUL << LCD_PAL5_R14_0_Pos)                            /*!< LCD PAL5: R14_0 Mask                */
+#define LCD_PAL5_G14_0_Pos                                    21                                                        /*!< LCD PAL5: G14_0 Position            */
+#define LCD_PAL5_G14_0_Msk                                    (0x1fUL << LCD_PAL5_G14_0_Pos)                            /*!< LCD PAL5: G14_0 Mask                */
+#define LCD_PAL5_B14_0_Pos                                    26                                                        /*!< LCD PAL5: B14_0 Position            */
+#define LCD_PAL5_B14_0_Msk                                    (0x1fUL << LCD_PAL5_B14_0_Pos)                            /*!< LCD PAL5: B14_0 Mask                */
+#define LCD_PAL5_I1_Pos                                       31                                                        /*!< LCD PAL5: I1 Position               */
+#define LCD_PAL5_I1_Msk                                       (0x01UL << LCD_PAL5_I1_Pos)                               /*!< LCD PAL5: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL6  --------------------------------------------
+#define LCD_PAL6_R04_0_Pos                                    0                                                         /*!< LCD PAL6: R04_0 Position            */
+#define LCD_PAL6_R04_0_Msk                                    (0x1fUL << LCD_PAL6_R04_0_Pos)                            /*!< LCD PAL6: R04_0 Mask                */
+#define LCD_PAL6_G04_0_Pos                                    5                                                         /*!< LCD PAL6: G04_0 Position            */
+#define LCD_PAL6_G04_0_Msk                                    (0x1fUL << LCD_PAL6_G04_0_Pos)                            /*!< LCD PAL6: G04_0 Mask                */
+#define LCD_PAL6_B04_0_Pos                                    10                                                        /*!< LCD PAL6: B04_0 Position            */
+#define LCD_PAL6_B04_0_Msk                                    (0x1fUL << LCD_PAL6_B04_0_Pos)                            /*!< LCD PAL6: B04_0 Mask                */
+#define LCD_PAL6_I0_Pos                                       15                                                        /*!< LCD PAL6: I0 Position               */
+#define LCD_PAL6_I0_Msk                                       (0x01UL << LCD_PAL6_I0_Pos)                               /*!< LCD PAL6: I0 Mask                   */
+#define LCD_PAL6_R14_0_Pos                                    16                                                        /*!< LCD PAL6: R14_0 Position            */
+#define LCD_PAL6_R14_0_Msk                                    (0x1fUL << LCD_PAL6_R14_0_Pos)                            /*!< LCD PAL6: R14_0 Mask                */
+#define LCD_PAL6_G14_0_Pos                                    21                                                        /*!< LCD PAL6: G14_0 Position            */
+#define LCD_PAL6_G14_0_Msk                                    (0x1fUL << LCD_PAL6_G14_0_Pos)                            /*!< LCD PAL6: G14_0 Mask                */
+#define LCD_PAL6_B14_0_Pos                                    26                                                        /*!< LCD PAL6: B14_0 Position            */
+#define LCD_PAL6_B14_0_Msk                                    (0x1fUL << LCD_PAL6_B14_0_Pos)                            /*!< LCD PAL6: B14_0 Mask                */
+#define LCD_PAL6_I1_Pos                                       31                                                        /*!< LCD PAL6: I1 Position               */
+#define LCD_PAL6_I1_Msk                                       (0x01UL << LCD_PAL6_I1_Pos)                               /*!< LCD PAL6: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL7  --------------------------------------------
+#define LCD_PAL7_R04_0_Pos                                    0                                                         /*!< LCD PAL7: R04_0 Position            */
+#define LCD_PAL7_R04_0_Msk                                    (0x1fUL << LCD_PAL7_R04_0_Pos)                            /*!< LCD PAL7: R04_0 Mask                */
+#define LCD_PAL7_G04_0_Pos                                    5                                                         /*!< LCD PAL7: G04_0 Position            */
+#define LCD_PAL7_G04_0_Msk                                    (0x1fUL << LCD_PAL7_G04_0_Pos)                            /*!< LCD PAL7: G04_0 Mask                */
+#define LCD_PAL7_B04_0_Pos                                    10                                                        /*!< LCD PAL7: B04_0 Position            */
+#define LCD_PAL7_B04_0_Msk                                    (0x1fUL << LCD_PAL7_B04_0_Pos)                            /*!< LCD PAL7: B04_0 Mask                */
+#define LCD_PAL7_I0_Pos                                       15                                                        /*!< LCD PAL7: I0 Position               */
+#define LCD_PAL7_I0_Msk                                       (0x01UL << LCD_PAL7_I0_Pos)                               /*!< LCD PAL7: I0 Mask                   */
+#define LCD_PAL7_R14_0_Pos                                    16                                                        /*!< LCD PAL7: R14_0 Position            */
+#define LCD_PAL7_R14_0_Msk                                    (0x1fUL << LCD_PAL7_R14_0_Pos)                            /*!< LCD PAL7: R14_0 Mask                */
+#define LCD_PAL7_G14_0_Pos                                    21                                                        /*!< LCD PAL7: G14_0 Position            */
+#define LCD_PAL7_G14_0_Msk                                    (0x1fUL << LCD_PAL7_G14_0_Pos)                            /*!< LCD PAL7: G14_0 Mask                */
+#define LCD_PAL7_B14_0_Pos                                    26                                                        /*!< LCD PAL7: B14_0 Position            */
+#define LCD_PAL7_B14_0_Msk                                    (0x1fUL << LCD_PAL7_B14_0_Pos)                            /*!< LCD PAL7: B14_0 Mask                */
+#define LCD_PAL7_I1_Pos                                       31                                                        /*!< LCD PAL7: I1 Position               */
+#define LCD_PAL7_I1_Msk                                       (0x01UL << LCD_PAL7_I1_Pos)                               /*!< LCD PAL7: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL8  --------------------------------------------
+#define LCD_PAL8_R04_0_Pos                                    0                                                         /*!< LCD PAL8: R04_0 Position            */
+#define LCD_PAL8_R04_0_Msk                                    (0x1fUL << LCD_PAL8_R04_0_Pos)                            /*!< LCD PAL8: R04_0 Mask                */
+#define LCD_PAL8_G04_0_Pos                                    5                                                         /*!< LCD PAL8: G04_0 Position            */
+#define LCD_PAL8_G04_0_Msk                                    (0x1fUL << LCD_PAL8_G04_0_Pos)                            /*!< LCD PAL8: G04_0 Mask                */
+#define LCD_PAL8_B04_0_Pos                                    10                                                        /*!< LCD PAL8: B04_0 Position            */
+#define LCD_PAL8_B04_0_Msk                                    (0x1fUL << LCD_PAL8_B04_0_Pos)                            /*!< LCD PAL8: B04_0 Mask                */
+#define LCD_PAL8_I0_Pos                                       15                                                        /*!< LCD PAL8: I0 Position               */
+#define LCD_PAL8_I0_Msk                                       (0x01UL << LCD_PAL8_I0_Pos)                               /*!< LCD PAL8: I0 Mask                   */
+#define LCD_PAL8_R14_0_Pos                                    16                                                        /*!< LCD PAL8: R14_0 Position            */
+#define LCD_PAL8_R14_0_Msk                                    (0x1fUL << LCD_PAL8_R14_0_Pos)                            /*!< LCD PAL8: R14_0 Mask                */
+#define LCD_PAL8_G14_0_Pos                                    21                                                        /*!< LCD PAL8: G14_0 Position            */
+#define LCD_PAL8_G14_0_Msk                                    (0x1fUL << LCD_PAL8_G14_0_Pos)                            /*!< LCD PAL8: G14_0 Mask                */
+#define LCD_PAL8_B14_0_Pos                                    26                                                        /*!< LCD PAL8: B14_0 Position            */
+#define LCD_PAL8_B14_0_Msk                                    (0x1fUL << LCD_PAL8_B14_0_Pos)                            /*!< LCD PAL8: B14_0 Mask                */
+#define LCD_PAL8_I1_Pos                                       31                                                        /*!< LCD PAL8: I1 Position               */
+#define LCD_PAL8_I1_Msk                                       (0x01UL << LCD_PAL8_I1_Pos)                               /*!< LCD PAL8: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL9  --------------------------------------------
+#define LCD_PAL9_R04_0_Pos                                    0                                                         /*!< LCD PAL9: R04_0 Position            */
+#define LCD_PAL9_R04_0_Msk                                    (0x1fUL << LCD_PAL9_R04_0_Pos)                            /*!< LCD PAL9: R04_0 Mask                */
+#define LCD_PAL9_G04_0_Pos                                    5                                                         /*!< LCD PAL9: G04_0 Position            */
+#define LCD_PAL9_G04_0_Msk                                    (0x1fUL << LCD_PAL9_G04_0_Pos)                            /*!< LCD PAL9: G04_0 Mask                */
+#define LCD_PAL9_B04_0_Pos                                    10                                                        /*!< LCD PAL9: B04_0 Position            */
+#define LCD_PAL9_B04_0_Msk                                    (0x1fUL << LCD_PAL9_B04_0_Pos)                            /*!< LCD PAL9: B04_0 Mask                */
+#define LCD_PAL9_I0_Pos                                       15                                                        /*!< LCD PAL9: I0 Position               */
+#define LCD_PAL9_I0_Msk                                       (0x01UL << LCD_PAL9_I0_Pos)                               /*!< LCD PAL9: I0 Mask                   */
+#define LCD_PAL9_R14_0_Pos                                    16                                                        /*!< LCD PAL9: R14_0 Position            */
+#define LCD_PAL9_R14_0_Msk                                    (0x1fUL << LCD_PAL9_R14_0_Pos)                            /*!< LCD PAL9: R14_0 Mask                */
+#define LCD_PAL9_G14_0_Pos                                    21                                                        /*!< LCD PAL9: G14_0 Position            */
+#define LCD_PAL9_G14_0_Msk                                    (0x1fUL << LCD_PAL9_G14_0_Pos)                            /*!< LCD PAL9: G14_0 Mask                */
+#define LCD_PAL9_B14_0_Pos                                    26                                                        /*!< LCD PAL9: B14_0 Position            */
+#define LCD_PAL9_B14_0_Msk                                    (0x1fUL << LCD_PAL9_B14_0_Pos)                            /*!< LCD PAL9: B14_0 Mask                */
+#define LCD_PAL9_I1_Pos                                       31                                                        /*!< LCD PAL9: I1 Position               */
+#define LCD_PAL9_I1_Msk                                       (0x01UL << LCD_PAL9_I1_Pos)                               /*!< LCD PAL9: I1 Mask                   */
+
+// ----------------------------------------  LCD_PAL10  -------------------------------------------
+#define LCD_PAL10_R04_0_Pos                                   0                                                         /*!< LCD PAL10: R04_0 Position           */
+#define LCD_PAL10_R04_0_Msk                                   (0x1fUL << LCD_PAL10_R04_0_Pos)                           /*!< LCD PAL10: R04_0 Mask               */
+#define LCD_PAL10_G04_0_Pos                                   5                                                         /*!< LCD PAL10: G04_0 Position           */
+#define LCD_PAL10_G04_0_Msk                                   (0x1fUL << LCD_PAL10_G04_0_Pos)                           /*!< LCD PAL10: G04_0 Mask               */
+#define LCD_PAL10_B04_0_Pos                                   10                                                        /*!< LCD PAL10: B04_0 Position           */
+#define LCD_PAL10_B04_0_Msk                                   (0x1fUL << LCD_PAL10_B04_0_Pos)                           /*!< LCD PAL10: B04_0 Mask               */
+#define LCD_PAL10_I0_Pos                                      15                                                        /*!< LCD PAL10: I0 Position              */
+#define LCD_PAL10_I0_Msk                                      (0x01UL << LCD_PAL10_I0_Pos)                              /*!< LCD PAL10: I0 Mask                  */
+#define LCD_PAL10_R14_0_Pos                                   16                                                        /*!< LCD PAL10: R14_0 Position           */
+#define LCD_PAL10_R14_0_Msk                                   (0x1fUL << LCD_PAL10_R14_0_Pos)                           /*!< LCD PAL10: R14_0 Mask               */
+#define LCD_PAL10_G14_0_Pos                                   21                                                        /*!< LCD PAL10: G14_0 Position           */
+#define LCD_PAL10_G14_0_Msk                                   (0x1fUL << LCD_PAL10_G14_0_Pos)                           /*!< LCD PAL10: G14_0 Mask               */
+#define LCD_PAL10_B14_0_Pos                                   26                                                        /*!< LCD PAL10: B14_0 Position           */
+#define LCD_PAL10_B14_0_Msk                                   (0x1fUL << LCD_PAL10_B14_0_Pos)                           /*!< LCD PAL10: B14_0 Mask               */
+#define LCD_PAL10_I1_Pos                                      31                                                        /*!< LCD PAL10: I1 Position              */
+#define LCD_PAL10_I1_Msk                                      (0x01UL << LCD_PAL10_I1_Pos)                              /*!< LCD PAL10: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL11  -------------------------------------------
+#define LCD_PAL11_R04_0_Pos                                   0                                                         /*!< LCD PAL11: R04_0 Position           */
+#define LCD_PAL11_R04_0_Msk                                   (0x1fUL << LCD_PAL11_R04_0_Pos)                           /*!< LCD PAL11: R04_0 Mask               */
+#define LCD_PAL11_G04_0_Pos                                   5                                                         /*!< LCD PAL11: G04_0 Position           */
+#define LCD_PAL11_G04_0_Msk                                   (0x1fUL << LCD_PAL11_G04_0_Pos)                           /*!< LCD PAL11: G04_0 Mask               */
+#define LCD_PAL11_B04_0_Pos                                   10                                                        /*!< LCD PAL11: B04_0 Position           */
+#define LCD_PAL11_B04_0_Msk                                   (0x1fUL << LCD_PAL11_B04_0_Pos)                           /*!< LCD PAL11: B04_0 Mask               */
+#define LCD_PAL11_I0_Pos                                      15                                                        /*!< LCD PAL11: I0 Position              */
+#define LCD_PAL11_I0_Msk                                      (0x01UL << LCD_PAL11_I0_Pos)                              /*!< LCD PAL11: I0 Mask                  */
+#define LCD_PAL11_R14_0_Pos                                   16                                                        /*!< LCD PAL11: R14_0 Position           */
+#define LCD_PAL11_R14_0_Msk                                   (0x1fUL << LCD_PAL11_R14_0_Pos)                           /*!< LCD PAL11: R14_0 Mask               */
+#define LCD_PAL11_G14_0_Pos                                   21                                                        /*!< LCD PAL11: G14_0 Position           */
+#define LCD_PAL11_G14_0_Msk                                   (0x1fUL << LCD_PAL11_G14_0_Pos)                           /*!< LCD PAL11: G14_0 Mask               */
+#define LCD_PAL11_B14_0_Pos                                   26                                                        /*!< LCD PAL11: B14_0 Position           */
+#define LCD_PAL11_B14_0_Msk                                   (0x1fUL << LCD_PAL11_B14_0_Pos)                           /*!< LCD PAL11: B14_0 Mask               */
+#define LCD_PAL11_I1_Pos                                      31                                                        /*!< LCD PAL11: I1 Position              */
+#define LCD_PAL11_I1_Msk                                      (0x01UL << LCD_PAL11_I1_Pos)                              /*!< LCD PAL11: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL12  -------------------------------------------
+#define LCD_PAL12_R04_0_Pos                                   0                                                         /*!< LCD PAL12: R04_0 Position           */
+#define LCD_PAL12_R04_0_Msk                                   (0x1fUL << LCD_PAL12_R04_0_Pos)                           /*!< LCD PAL12: R04_0 Mask               */
+#define LCD_PAL12_G04_0_Pos                                   5                                                         /*!< LCD PAL12: G04_0 Position           */
+#define LCD_PAL12_G04_0_Msk                                   (0x1fUL << LCD_PAL12_G04_0_Pos)                           /*!< LCD PAL12: G04_0 Mask               */
+#define LCD_PAL12_B04_0_Pos                                   10                                                        /*!< LCD PAL12: B04_0 Position           */
+#define LCD_PAL12_B04_0_Msk                                   (0x1fUL << LCD_PAL12_B04_0_Pos)                           /*!< LCD PAL12: B04_0 Mask               */
+#define LCD_PAL12_I0_Pos                                      15                                                        /*!< LCD PAL12: I0 Position              */
+#define LCD_PAL12_I0_Msk                                      (0x01UL << LCD_PAL12_I0_Pos)                              /*!< LCD PAL12: I0 Mask                  */
+#define LCD_PAL12_R14_0_Pos                                   16                                                        /*!< LCD PAL12: R14_0 Position           */
+#define LCD_PAL12_R14_0_Msk                                   (0x1fUL << LCD_PAL12_R14_0_Pos)                           /*!< LCD PAL12: R14_0 Mask               */
+#define LCD_PAL12_G14_0_Pos                                   21                                                        /*!< LCD PAL12: G14_0 Position           */
+#define LCD_PAL12_G14_0_Msk                                   (0x1fUL << LCD_PAL12_G14_0_Pos)                           /*!< LCD PAL12: G14_0 Mask               */
+#define LCD_PAL12_B14_0_Pos                                   26                                                        /*!< LCD PAL12: B14_0 Position           */
+#define LCD_PAL12_B14_0_Msk                                   (0x1fUL << LCD_PAL12_B14_0_Pos)                           /*!< LCD PAL12: B14_0 Mask               */
+#define LCD_PAL12_I1_Pos                                      31                                                        /*!< LCD PAL12: I1 Position              */
+#define LCD_PAL12_I1_Msk                                      (0x01UL << LCD_PAL12_I1_Pos)                              /*!< LCD PAL12: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL13  -------------------------------------------
+#define LCD_PAL13_R04_0_Pos                                   0                                                         /*!< LCD PAL13: R04_0 Position           */
+#define LCD_PAL13_R04_0_Msk                                   (0x1fUL << LCD_PAL13_R04_0_Pos)                           /*!< LCD PAL13: R04_0 Mask               */
+#define LCD_PAL13_G04_0_Pos                                   5                                                         /*!< LCD PAL13: G04_0 Position           */
+#define LCD_PAL13_G04_0_Msk                                   (0x1fUL << LCD_PAL13_G04_0_Pos)                           /*!< LCD PAL13: G04_0 Mask               */
+#define LCD_PAL13_B04_0_Pos                                   10                                                        /*!< LCD PAL13: B04_0 Position           */
+#define LCD_PAL13_B04_0_Msk                                   (0x1fUL << LCD_PAL13_B04_0_Pos)                           /*!< LCD PAL13: B04_0 Mask               */
+#define LCD_PAL13_I0_Pos                                      15                                                        /*!< LCD PAL13: I0 Position              */
+#define LCD_PAL13_I0_Msk                                      (0x01UL << LCD_PAL13_I0_Pos)                              /*!< LCD PAL13: I0 Mask                  */
+#define LCD_PAL13_R14_0_Pos                                   16                                                        /*!< LCD PAL13: R14_0 Position           */
+#define LCD_PAL13_R14_0_Msk                                   (0x1fUL << LCD_PAL13_R14_0_Pos)                           /*!< LCD PAL13: R14_0 Mask               */
+#define LCD_PAL13_G14_0_Pos                                   21                                                        /*!< LCD PAL13: G14_0 Position           */
+#define LCD_PAL13_G14_0_Msk                                   (0x1fUL << LCD_PAL13_G14_0_Pos)                           /*!< LCD PAL13: G14_0 Mask               */
+#define LCD_PAL13_B14_0_Pos                                   26                                                        /*!< LCD PAL13: B14_0 Position           */
+#define LCD_PAL13_B14_0_Msk                                   (0x1fUL << LCD_PAL13_B14_0_Pos)                           /*!< LCD PAL13: B14_0 Mask               */
+#define LCD_PAL13_I1_Pos                                      31                                                        /*!< LCD PAL13: I1 Position              */
+#define LCD_PAL13_I1_Msk                                      (0x01UL << LCD_PAL13_I1_Pos)                              /*!< LCD PAL13: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL14  -------------------------------------------
+#define LCD_PAL14_R04_0_Pos                                   0                                                         /*!< LCD PAL14: R04_0 Position           */
+#define LCD_PAL14_R04_0_Msk                                   (0x1fUL << LCD_PAL14_R04_0_Pos)                           /*!< LCD PAL14: R04_0 Mask               */
+#define LCD_PAL14_G04_0_Pos                                   5                                                         /*!< LCD PAL14: G04_0 Position           */
+#define LCD_PAL14_G04_0_Msk                                   (0x1fUL << LCD_PAL14_G04_0_Pos)                           /*!< LCD PAL14: G04_0 Mask               */
+#define LCD_PAL14_B04_0_Pos                                   10                                                        /*!< LCD PAL14: B04_0 Position           */
+#define LCD_PAL14_B04_0_Msk                                   (0x1fUL << LCD_PAL14_B04_0_Pos)                           /*!< LCD PAL14: B04_0 Mask               */
+#define LCD_PAL14_I0_Pos                                      15                                                        /*!< LCD PAL14: I0 Position              */
+#define LCD_PAL14_I0_Msk                                      (0x01UL << LCD_PAL14_I0_Pos)                              /*!< LCD PAL14: I0 Mask                  */
+#define LCD_PAL14_R14_0_Pos                                   16                                                        /*!< LCD PAL14: R14_0 Position           */
+#define LCD_PAL14_R14_0_Msk                                   (0x1fUL << LCD_PAL14_R14_0_Pos)                           /*!< LCD PAL14: R14_0 Mask               */
+#define LCD_PAL14_G14_0_Pos                                   21                                                        /*!< LCD PAL14: G14_0 Position           */
+#define LCD_PAL14_G14_0_Msk                                   (0x1fUL << LCD_PAL14_G14_0_Pos)                           /*!< LCD PAL14: G14_0 Mask               */
+#define LCD_PAL14_B14_0_Pos                                   26                                                        /*!< LCD PAL14: B14_0 Position           */
+#define LCD_PAL14_B14_0_Msk                                   (0x1fUL << LCD_PAL14_B14_0_Pos)                           /*!< LCD PAL14: B14_0 Mask               */
+#define LCD_PAL14_I1_Pos                                      31                                                        /*!< LCD PAL14: I1 Position              */
+#define LCD_PAL14_I1_Msk                                      (0x01UL << LCD_PAL14_I1_Pos)                              /*!< LCD PAL14: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL15  -------------------------------------------
+#define LCD_PAL15_R04_0_Pos                                   0                                                         /*!< LCD PAL15: R04_0 Position           */
+#define LCD_PAL15_R04_0_Msk                                   (0x1fUL << LCD_PAL15_R04_0_Pos)                           /*!< LCD PAL15: R04_0 Mask               */
+#define LCD_PAL15_G04_0_Pos                                   5                                                         /*!< LCD PAL15: G04_0 Position           */
+#define LCD_PAL15_G04_0_Msk                                   (0x1fUL << LCD_PAL15_G04_0_Pos)                           /*!< LCD PAL15: G04_0 Mask               */
+#define LCD_PAL15_B04_0_Pos                                   10                                                        /*!< LCD PAL15: B04_0 Position           */
+#define LCD_PAL15_B04_0_Msk                                   (0x1fUL << LCD_PAL15_B04_0_Pos)                           /*!< LCD PAL15: B04_0 Mask               */
+#define LCD_PAL15_I0_Pos                                      15                                                        /*!< LCD PAL15: I0 Position              */
+#define LCD_PAL15_I0_Msk                                      (0x01UL << LCD_PAL15_I0_Pos)                              /*!< LCD PAL15: I0 Mask                  */
+#define LCD_PAL15_R14_0_Pos                                   16                                                        /*!< LCD PAL15: R14_0 Position           */
+#define LCD_PAL15_R14_0_Msk                                   (0x1fUL << LCD_PAL15_R14_0_Pos)                           /*!< LCD PAL15: R14_0 Mask               */
+#define LCD_PAL15_G14_0_Pos                                   21                                                        /*!< LCD PAL15: G14_0 Position           */
+#define LCD_PAL15_G14_0_Msk                                   (0x1fUL << LCD_PAL15_G14_0_Pos)                           /*!< LCD PAL15: G14_0 Mask               */
+#define LCD_PAL15_B14_0_Pos                                   26                                                        /*!< LCD PAL15: B14_0 Position           */
+#define LCD_PAL15_B14_0_Msk                                   (0x1fUL << LCD_PAL15_B14_0_Pos)                           /*!< LCD PAL15: B14_0 Mask               */
+#define LCD_PAL15_I1_Pos                                      31                                                        /*!< LCD PAL15: I1 Position              */
+#define LCD_PAL15_I1_Msk                                      (0x01UL << LCD_PAL15_I1_Pos)                              /*!< LCD PAL15: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL16  -------------------------------------------
+#define LCD_PAL16_R04_0_Pos                                   0                                                         /*!< LCD PAL16: R04_0 Position           */
+#define LCD_PAL16_R04_0_Msk                                   (0x1fUL << LCD_PAL16_R04_0_Pos)                           /*!< LCD PAL16: R04_0 Mask               */
+#define LCD_PAL16_G04_0_Pos                                   5                                                         /*!< LCD PAL16: G04_0 Position           */
+#define LCD_PAL16_G04_0_Msk                                   (0x1fUL << LCD_PAL16_G04_0_Pos)                           /*!< LCD PAL16: G04_0 Mask               */
+#define LCD_PAL16_B04_0_Pos                                   10                                                        /*!< LCD PAL16: B04_0 Position           */
+#define LCD_PAL16_B04_0_Msk                                   (0x1fUL << LCD_PAL16_B04_0_Pos)                           /*!< LCD PAL16: B04_0 Mask               */
+#define LCD_PAL16_I0_Pos                                      15                                                        /*!< LCD PAL16: I0 Position              */
+#define LCD_PAL16_I0_Msk                                      (0x01UL << LCD_PAL16_I0_Pos)                              /*!< LCD PAL16: I0 Mask                  */
+#define LCD_PAL16_R14_0_Pos                                   16                                                        /*!< LCD PAL16: R14_0 Position           */
+#define LCD_PAL16_R14_0_Msk                                   (0x1fUL << LCD_PAL16_R14_0_Pos)                           /*!< LCD PAL16: R14_0 Mask               */
+#define LCD_PAL16_G14_0_Pos                                   21                                                        /*!< LCD PAL16: G14_0 Position           */
+#define LCD_PAL16_G14_0_Msk                                   (0x1fUL << LCD_PAL16_G14_0_Pos)                           /*!< LCD PAL16: G14_0 Mask               */
+#define LCD_PAL16_B14_0_Pos                                   26                                                        /*!< LCD PAL16: B14_0 Position           */
+#define LCD_PAL16_B14_0_Msk                                   (0x1fUL << LCD_PAL16_B14_0_Pos)                           /*!< LCD PAL16: B14_0 Mask               */
+#define LCD_PAL16_I1_Pos                                      31                                                        /*!< LCD PAL16: I1 Position              */
+#define LCD_PAL16_I1_Msk                                      (0x01UL << LCD_PAL16_I1_Pos)                              /*!< LCD PAL16: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL17  -------------------------------------------
+#define LCD_PAL17_R04_0_Pos                                   0                                                         /*!< LCD PAL17: R04_0 Position           */
+#define LCD_PAL17_R04_0_Msk                                   (0x1fUL << LCD_PAL17_R04_0_Pos)                           /*!< LCD PAL17: R04_0 Mask               */
+#define LCD_PAL17_G04_0_Pos                                   5                                                         /*!< LCD PAL17: G04_0 Position           */
+#define LCD_PAL17_G04_0_Msk                                   (0x1fUL << LCD_PAL17_G04_0_Pos)                           /*!< LCD PAL17: G04_0 Mask               */
+#define LCD_PAL17_B04_0_Pos                                   10                                                        /*!< LCD PAL17: B04_0 Position           */
+#define LCD_PAL17_B04_0_Msk                                   (0x1fUL << LCD_PAL17_B04_0_Pos)                           /*!< LCD PAL17: B04_0 Mask               */
+#define LCD_PAL17_I0_Pos                                      15                                                        /*!< LCD PAL17: I0 Position              */
+#define LCD_PAL17_I0_Msk                                      (0x01UL << LCD_PAL17_I0_Pos)                              /*!< LCD PAL17: I0 Mask                  */
+#define LCD_PAL17_R14_0_Pos                                   16                                                        /*!< LCD PAL17: R14_0 Position           */
+#define LCD_PAL17_R14_0_Msk                                   (0x1fUL << LCD_PAL17_R14_0_Pos)                           /*!< LCD PAL17: R14_0 Mask               */
+#define LCD_PAL17_G14_0_Pos                                   21                                                        /*!< LCD PAL17: G14_0 Position           */
+#define LCD_PAL17_G14_0_Msk                                   (0x1fUL << LCD_PAL17_G14_0_Pos)                           /*!< LCD PAL17: G14_0 Mask               */
+#define LCD_PAL17_B14_0_Pos                                   26                                                        /*!< LCD PAL17: B14_0 Position           */
+#define LCD_PAL17_B14_0_Msk                                   (0x1fUL << LCD_PAL17_B14_0_Pos)                           /*!< LCD PAL17: B14_0 Mask               */
+#define LCD_PAL17_I1_Pos                                      31                                                        /*!< LCD PAL17: I1 Position              */
+#define LCD_PAL17_I1_Msk                                      (0x01UL << LCD_PAL17_I1_Pos)                              /*!< LCD PAL17: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL18  -------------------------------------------
+#define LCD_PAL18_R04_0_Pos                                   0                                                         /*!< LCD PAL18: R04_0 Position           */
+#define LCD_PAL18_R04_0_Msk                                   (0x1fUL << LCD_PAL18_R04_0_Pos)                           /*!< LCD PAL18: R04_0 Mask               */
+#define LCD_PAL18_G04_0_Pos                                   5                                                         /*!< LCD PAL18: G04_0 Position           */
+#define LCD_PAL18_G04_0_Msk                                   (0x1fUL << LCD_PAL18_G04_0_Pos)                           /*!< LCD PAL18: G04_0 Mask               */
+#define LCD_PAL18_B04_0_Pos                                   10                                                        /*!< LCD PAL18: B04_0 Position           */
+#define LCD_PAL18_B04_0_Msk                                   (0x1fUL << LCD_PAL18_B04_0_Pos)                           /*!< LCD PAL18: B04_0 Mask               */
+#define LCD_PAL18_I0_Pos                                      15                                                        /*!< LCD PAL18: I0 Position              */
+#define LCD_PAL18_I0_Msk                                      (0x01UL << LCD_PAL18_I0_Pos)                              /*!< LCD PAL18: I0 Mask                  */
+#define LCD_PAL18_R14_0_Pos                                   16                                                        /*!< LCD PAL18: R14_0 Position           */
+#define LCD_PAL18_R14_0_Msk                                   (0x1fUL << LCD_PAL18_R14_0_Pos)                           /*!< LCD PAL18: R14_0 Mask               */
+#define LCD_PAL18_G14_0_Pos                                   21                                                        /*!< LCD PAL18: G14_0 Position           */
+#define LCD_PAL18_G14_0_Msk                                   (0x1fUL << LCD_PAL18_G14_0_Pos)                           /*!< LCD PAL18: G14_0 Mask               */
+#define LCD_PAL18_B14_0_Pos                                   26                                                        /*!< LCD PAL18: B14_0 Position           */
+#define LCD_PAL18_B14_0_Msk                                   (0x1fUL << LCD_PAL18_B14_0_Pos)                           /*!< LCD PAL18: B14_0 Mask               */
+#define LCD_PAL18_I1_Pos                                      31                                                        /*!< LCD PAL18: I1 Position              */
+#define LCD_PAL18_I1_Msk                                      (0x01UL << LCD_PAL18_I1_Pos)                              /*!< LCD PAL18: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL19  -------------------------------------------
+#define LCD_PAL19_R04_0_Pos                                   0                                                         /*!< LCD PAL19: R04_0 Position           */
+#define LCD_PAL19_R04_0_Msk                                   (0x1fUL << LCD_PAL19_R04_0_Pos)                           /*!< LCD PAL19: R04_0 Mask               */
+#define LCD_PAL19_G04_0_Pos                                   5                                                         /*!< LCD PAL19: G04_0 Position           */
+#define LCD_PAL19_G04_0_Msk                                   (0x1fUL << LCD_PAL19_G04_0_Pos)                           /*!< LCD PAL19: G04_0 Mask               */
+#define LCD_PAL19_B04_0_Pos                                   10                                                        /*!< LCD PAL19: B04_0 Position           */
+#define LCD_PAL19_B04_0_Msk                                   (0x1fUL << LCD_PAL19_B04_0_Pos)                           /*!< LCD PAL19: B04_0 Mask               */
+#define LCD_PAL19_I0_Pos                                      15                                                        /*!< LCD PAL19: I0 Position              */
+#define LCD_PAL19_I0_Msk                                      (0x01UL << LCD_PAL19_I0_Pos)                              /*!< LCD PAL19: I0 Mask                  */
+#define LCD_PAL19_R14_0_Pos                                   16                                                        /*!< LCD PAL19: R14_0 Position           */
+#define LCD_PAL19_R14_0_Msk                                   (0x1fUL << LCD_PAL19_R14_0_Pos)                           /*!< LCD PAL19: R14_0 Mask               */
+#define LCD_PAL19_G14_0_Pos                                   21                                                        /*!< LCD PAL19: G14_0 Position           */
+#define LCD_PAL19_G14_0_Msk                                   (0x1fUL << LCD_PAL19_G14_0_Pos)                           /*!< LCD PAL19: G14_0 Mask               */
+#define LCD_PAL19_B14_0_Pos                                   26                                                        /*!< LCD PAL19: B14_0 Position           */
+#define LCD_PAL19_B14_0_Msk                                   (0x1fUL << LCD_PAL19_B14_0_Pos)                           /*!< LCD PAL19: B14_0 Mask               */
+#define LCD_PAL19_I1_Pos                                      31                                                        /*!< LCD PAL19: I1 Position              */
+#define LCD_PAL19_I1_Msk                                      (0x01UL << LCD_PAL19_I1_Pos)                              /*!< LCD PAL19: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL20  -------------------------------------------
+#define LCD_PAL20_R04_0_Pos                                   0                                                         /*!< LCD PAL20: R04_0 Position           */
+#define LCD_PAL20_R04_0_Msk                                   (0x1fUL << LCD_PAL20_R04_0_Pos)                           /*!< LCD PAL20: R04_0 Mask               */
+#define LCD_PAL20_G04_0_Pos                                   5                                                         /*!< LCD PAL20: G04_0 Position           */
+#define LCD_PAL20_G04_0_Msk                                   (0x1fUL << LCD_PAL20_G04_0_Pos)                           /*!< LCD PAL20: G04_0 Mask               */
+#define LCD_PAL20_B04_0_Pos                                   10                                                        /*!< LCD PAL20: B04_0 Position           */
+#define LCD_PAL20_B04_0_Msk                                   (0x1fUL << LCD_PAL20_B04_0_Pos)                           /*!< LCD PAL20: B04_0 Mask               */
+#define LCD_PAL20_I0_Pos                                      15                                                        /*!< LCD PAL20: I0 Position              */
+#define LCD_PAL20_I0_Msk                                      (0x01UL << LCD_PAL20_I0_Pos)                              /*!< LCD PAL20: I0 Mask                  */
+#define LCD_PAL20_R14_0_Pos                                   16                                                        /*!< LCD PAL20: R14_0 Position           */
+#define LCD_PAL20_R14_0_Msk                                   (0x1fUL << LCD_PAL20_R14_0_Pos)                           /*!< LCD PAL20: R14_0 Mask               */
+#define LCD_PAL20_G14_0_Pos                                   21                                                        /*!< LCD PAL20: G14_0 Position           */
+#define LCD_PAL20_G14_0_Msk                                   (0x1fUL << LCD_PAL20_G14_0_Pos)                           /*!< LCD PAL20: G14_0 Mask               */
+#define LCD_PAL20_B14_0_Pos                                   26                                                        /*!< LCD PAL20: B14_0 Position           */
+#define LCD_PAL20_B14_0_Msk                                   (0x1fUL << LCD_PAL20_B14_0_Pos)                           /*!< LCD PAL20: B14_0 Mask               */
+#define LCD_PAL20_I1_Pos                                      31                                                        /*!< LCD PAL20: I1 Position              */
+#define LCD_PAL20_I1_Msk                                      (0x01UL << LCD_PAL20_I1_Pos)                              /*!< LCD PAL20: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL21  -------------------------------------------
+#define LCD_PAL21_R04_0_Pos                                   0                                                         /*!< LCD PAL21: R04_0 Position           */
+#define LCD_PAL21_R04_0_Msk                                   (0x1fUL << LCD_PAL21_R04_0_Pos)                           /*!< LCD PAL21: R04_0 Mask               */
+#define LCD_PAL21_G04_0_Pos                                   5                                                         /*!< LCD PAL21: G04_0 Position           */
+#define LCD_PAL21_G04_0_Msk                                   (0x1fUL << LCD_PAL21_G04_0_Pos)                           /*!< LCD PAL21: G04_0 Mask               */
+#define LCD_PAL21_B04_0_Pos                                   10                                                        /*!< LCD PAL21: B04_0 Position           */
+#define LCD_PAL21_B04_0_Msk                                   (0x1fUL << LCD_PAL21_B04_0_Pos)                           /*!< LCD PAL21: B04_0 Mask               */
+#define LCD_PAL21_I0_Pos                                      15                                                        /*!< LCD PAL21: I0 Position              */
+#define LCD_PAL21_I0_Msk                                      (0x01UL << LCD_PAL21_I0_Pos)                              /*!< LCD PAL21: I0 Mask                  */
+#define LCD_PAL21_R14_0_Pos                                   16                                                        /*!< LCD PAL21: R14_0 Position           */
+#define LCD_PAL21_R14_0_Msk                                   (0x1fUL << LCD_PAL21_R14_0_Pos)                           /*!< LCD PAL21: R14_0 Mask               */
+#define LCD_PAL21_G14_0_Pos                                   21                                                        /*!< LCD PAL21: G14_0 Position           */
+#define LCD_PAL21_G14_0_Msk                                   (0x1fUL << LCD_PAL21_G14_0_Pos)                           /*!< LCD PAL21: G14_0 Mask               */
+#define LCD_PAL21_B14_0_Pos                                   26                                                        /*!< LCD PAL21: B14_0 Position           */
+#define LCD_PAL21_B14_0_Msk                                   (0x1fUL << LCD_PAL21_B14_0_Pos)                           /*!< LCD PAL21: B14_0 Mask               */
+#define LCD_PAL21_I1_Pos                                      31                                                        /*!< LCD PAL21: I1 Position              */
+#define LCD_PAL21_I1_Msk                                      (0x01UL << LCD_PAL21_I1_Pos)                              /*!< LCD PAL21: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL22  -------------------------------------------
+#define LCD_PAL22_R04_0_Pos                                   0                                                         /*!< LCD PAL22: R04_0 Position           */
+#define LCD_PAL22_R04_0_Msk                                   (0x1fUL << LCD_PAL22_R04_0_Pos)                           /*!< LCD PAL22: R04_0 Mask               */
+#define LCD_PAL22_G04_0_Pos                                   5                                                         /*!< LCD PAL22: G04_0 Position           */
+#define LCD_PAL22_G04_0_Msk                                   (0x1fUL << LCD_PAL22_G04_0_Pos)                           /*!< LCD PAL22: G04_0 Mask               */
+#define LCD_PAL22_B04_0_Pos                                   10                                                        /*!< LCD PAL22: B04_0 Position           */
+#define LCD_PAL22_B04_0_Msk                                   (0x1fUL << LCD_PAL22_B04_0_Pos)                           /*!< LCD PAL22: B04_0 Mask               */
+#define LCD_PAL22_I0_Pos                                      15                                                        /*!< LCD PAL22: I0 Position              */
+#define LCD_PAL22_I0_Msk                                      (0x01UL << LCD_PAL22_I0_Pos)                              /*!< LCD PAL22: I0 Mask                  */
+#define LCD_PAL22_R14_0_Pos                                   16                                                        /*!< LCD PAL22: R14_0 Position           */
+#define LCD_PAL22_R14_0_Msk                                   (0x1fUL << LCD_PAL22_R14_0_Pos)                           /*!< LCD PAL22: R14_0 Mask               */
+#define LCD_PAL22_G14_0_Pos                                   21                                                        /*!< LCD PAL22: G14_0 Position           */
+#define LCD_PAL22_G14_0_Msk                                   (0x1fUL << LCD_PAL22_G14_0_Pos)                           /*!< LCD PAL22: G14_0 Mask               */
+#define LCD_PAL22_B14_0_Pos                                   26                                                        /*!< LCD PAL22: B14_0 Position           */
+#define LCD_PAL22_B14_0_Msk                                   (0x1fUL << LCD_PAL22_B14_0_Pos)                           /*!< LCD PAL22: B14_0 Mask               */
+#define LCD_PAL22_I1_Pos                                      31                                                        /*!< LCD PAL22: I1 Position              */
+#define LCD_PAL22_I1_Msk                                      (0x01UL << LCD_PAL22_I1_Pos)                              /*!< LCD PAL22: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL23  -------------------------------------------
+#define LCD_PAL23_R04_0_Pos                                   0                                                         /*!< LCD PAL23: R04_0 Position           */
+#define LCD_PAL23_R04_0_Msk                                   (0x1fUL << LCD_PAL23_R04_0_Pos)                           /*!< LCD PAL23: R04_0 Mask               */
+#define LCD_PAL23_G04_0_Pos                                   5                                                         /*!< LCD PAL23: G04_0 Position           */
+#define LCD_PAL23_G04_0_Msk                                   (0x1fUL << LCD_PAL23_G04_0_Pos)                           /*!< LCD PAL23: G04_0 Mask               */
+#define LCD_PAL23_B04_0_Pos                                   10                                                        /*!< LCD PAL23: B04_0 Position           */
+#define LCD_PAL23_B04_0_Msk                                   (0x1fUL << LCD_PAL23_B04_0_Pos)                           /*!< LCD PAL23: B04_0 Mask               */
+#define LCD_PAL23_I0_Pos                                      15                                                        /*!< LCD PAL23: I0 Position              */
+#define LCD_PAL23_I0_Msk                                      (0x01UL << LCD_PAL23_I0_Pos)                              /*!< LCD PAL23: I0 Mask                  */
+#define LCD_PAL23_R14_0_Pos                                   16                                                        /*!< LCD PAL23: R14_0 Position           */
+#define LCD_PAL23_R14_0_Msk                                   (0x1fUL << LCD_PAL23_R14_0_Pos)                           /*!< LCD PAL23: R14_0 Mask               */
+#define LCD_PAL23_G14_0_Pos                                   21                                                        /*!< LCD PAL23: G14_0 Position           */
+#define LCD_PAL23_G14_0_Msk                                   (0x1fUL << LCD_PAL23_G14_0_Pos)                           /*!< LCD PAL23: G14_0 Mask               */
+#define LCD_PAL23_B14_0_Pos                                   26                                                        /*!< LCD PAL23: B14_0 Position           */
+#define LCD_PAL23_B14_0_Msk                                   (0x1fUL << LCD_PAL23_B14_0_Pos)                           /*!< LCD PAL23: B14_0 Mask               */
+#define LCD_PAL23_I1_Pos                                      31                                                        /*!< LCD PAL23: I1 Position              */
+#define LCD_PAL23_I1_Msk                                      (0x01UL << LCD_PAL23_I1_Pos)                              /*!< LCD PAL23: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL24  -------------------------------------------
+#define LCD_PAL24_R04_0_Pos                                   0                                                         /*!< LCD PAL24: R04_0 Position           */
+#define LCD_PAL24_R04_0_Msk                                   (0x1fUL << LCD_PAL24_R04_0_Pos)                           /*!< LCD PAL24: R04_0 Mask               */
+#define LCD_PAL24_G04_0_Pos                                   5                                                         /*!< LCD PAL24: G04_0 Position           */
+#define LCD_PAL24_G04_0_Msk                                   (0x1fUL << LCD_PAL24_G04_0_Pos)                           /*!< LCD PAL24: G04_0 Mask               */
+#define LCD_PAL24_B04_0_Pos                                   10                                                        /*!< LCD PAL24: B04_0 Position           */
+#define LCD_PAL24_B04_0_Msk                                   (0x1fUL << LCD_PAL24_B04_0_Pos)                           /*!< LCD PAL24: B04_0 Mask               */
+#define LCD_PAL24_I0_Pos                                      15                                                        /*!< LCD PAL24: I0 Position              */
+#define LCD_PAL24_I0_Msk                                      (0x01UL << LCD_PAL24_I0_Pos)                              /*!< LCD PAL24: I0 Mask                  */
+#define LCD_PAL24_R14_0_Pos                                   16                                                        /*!< LCD PAL24: R14_0 Position           */
+#define LCD_PAL24_R14_0_Msk                                   (0x1fUL << LCD_PAL24_R14_0_Pos)                           /*!< LCD PAL24: R14_0 Mask               */
+#define LCD_PAL24_G14_0_Pos                                   21                                                        /*!< LCD PAL24: G14_0 Position           */
+#define LCD_PAL24_G14_0_Msk                                   (0x1fUL << LCD_PAL24_G14_0_Pos)                           /*!< LCD PAL24: G14_0 Mask               */
+#define LCD_PAL24_B14_0_Pos                                   26                                                        /*!< LCD PAL24: B14_0 Position           */
+#define LCD_PAL24_B14_0_Msk                                   (0x1fUL << LCD_PAL24_B14_0_Pos)                           /*!< LCD PAL24: B14_0 Mask               */
+#define LCD_PAL24_I1_Pos                                      31                                                        /*!< LCD PAL24: I1 Position              */
+#define LCD_PAL24_I1_Msk                                      (0x01UL << LCD_PAL24_I1_Pos)                              /*!< LCD PAL24: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL25  -------------------------------------------
+#define LCD_PAL25_R04_0_Pos                                   0                                                         /*!< LCD PAL25: R04_0 Position           */
+#define LCD_PAL25_R04_0_Msk                                   (0x1fUL << LCD_PAL25_R04_0_Pos)                           /*!< LCD PAL25: R04_0 Mask               */
+#define LCD_PAL25_G04_0_Pos                                   5                                                         /*!< LCD PAL25: G04_0 Position           */
+#define LCD_PAL25_G04_0_Msk                                   (0x1fUL << LCD_PAL25_G04_0_Pos)                           /*!< LCD PAL25: G04_0 Mask               */
+#define LCD_PAL25_B04_0_Pos                                   10                                                        /*!< LCD PAL25: B04_0 Position           */
+#define LCD_PAL25_B04_0_Msk                                   (0x1fUL << LCD_PAL25_B04_0_Pos)                           /*!< LCD PAL25: B04_0 Mask               */
+#define LCD_PAL25_I0_Pos                                      15                                                        /*!< LCD PAL25: I0 Position              */
+#define LCD_PAL25_I0_Msk                                      (0x01UL << LCD_PAL25_I0_Pos)                              /*!< LCD PAL25: I0 Mask                  */
+#define LCD_PAL25_R14_0_Pos                                   16                                                        /*!< LCD PAL25: R14_0 Position           */
+#define LCD_PAL25_R14_0_Msk                                   (0x1fUL << LCD_PAL25_R14_0_Pos)                           /*!< LCD PAL25: R14_0 Mask               */
+#define LCD_PAL25_G14_0_Pos                                   21                                                        /*!< LCD PAL25: G14_0 Position           */
+#define LCD_PAL25_G14_0_Msk                                   (0x1fUL << LCD_PAL25_G14_0_Pos)                           /*!< LCD PAL25: G14_0 Mask               */
+#define LCD_PAL25_B14_0_Pos                                   26                                                        /*!< LCD PAL25: B14_0 Position           */
+#define LCD_PAL25_B14_0_Msk                                   (0x1fUL << LCD_PAL25_B14_0_Pos)                           /*!< LCD PAL25: B14_0 Mask               */
+#define LCD_PAL25_I1_Pos                                      31                                                        /*!< LCD PAL25: I1 Position              */
+#define LCD_PAL25_I1_Msk                                      (0x01UL << LCD_PAL25_I1_Pos)                              /*!< LCD PAL25: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL26  -------------------------------------------
+#define LCD_PAL26_R04_0_Pos                                   0                                                         /*!< LCD PAL26: R04_0 Position           */
+#define LCD_PAL26_R04_0_Msk                                   (0x1fUL << LCD_PAL26_R04_0_Pos)                           /*!< LCD PAL26: R04_0 Mask               */
+#define LCD_PAL26_G04_0_Pos                                   5                                                         /*!< LCD PAL26: G04_0 Position           */
+#define LCD_PAL26_G04_0_Msk                                   (0x1fUL << LCD_PAL26_G04_0_Pos)                           /*!< LCD PAL26: G04_0 Mask               */
+#define LCD_PAL26_B04_0_Pos                                   10                                                        /*!< LCD PAL26: B04_0 Position           */
+#define LCD_PAL26_B04_0_Msk                                   (0x1fUL << LCD_PAL26_B04_0_Pos)                           /*!< LCD PAL26: B04_0 Mask               */
+#define LCD_PAL26_I0_Pos                                      15                                                        /*!< LCD PAL26: I0 Position              */
+#define LCD_PAL26_I0_Msk                                      (0x01UL << LCD_PAL26_I0_Pos)                              /*!< LCD PAL26: I0 Mask                  */
+#define LCD_PAL26_R14_0_Pos                                   16                                                        /*!< LCD PAL26: R14_0 Position           */
+#define LCD_PAL26_R14_0_Msk                                   (0x1fUL << LCD_PAL26_R14_0_Pos)                           /*!< LCD PAL26: R14_0 Mask               */
+#define LCD_PAL26_G14_0_Pos                                   21                                                        /*!< LCD PAL26: G14_0 Position           */
+#define LCD_PAL26_G14_0_Msk                                   (0x1fUL << LCD_PAL26_G14_0_Pos)                           /*!< LCD PAL26: G14_0 Mask               */
+#define LCD_PAL26_B14_0_Pos                                   26                                                        /*!< LCD PAL26: B14_0 Position           */
+#define LCD_PAL26_B14_0_Msk                                   (0x1fUL << LCD_PAL26_B14_0_Pos)                           /*!< LCD PAL26: B14_0 Mask               */
+#define LCD_PAL26_I1_Pos                                      31                                                        /*!< LCD PAL26: I1 Position              */
+#define LCD_PAL26_I1_Msk                                      (0x01UL << LCD_PAL26_I1_Pos)                              /*!< LCD PAL26: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL27  -------------------------------------------
+#define LCD_PAL27_R04_0_Pos                                   0                                                         /*!< LCD PAL27: R04_0 Position           */
+#define LCD_PAL27_R04_0_Msk                                   (0x1fUL << LCD_PAL27_R04_0_Pos)                           /*!< LCD PAL27: R04_0 Mask               */
+#define LCD_PAL27_G04_0_Pos                                   5                                                         /*!< LCD PAL27: G04_0 Position           */
+#define LCD_PAL27_G04_0_Msk                                   (0x1fUL << LCD_PAL27_G04_0_Pos)                           /*!< LCD PAL27: G04_0 Mask               */
+#define LCD_PAL27_B04_0_Pos                                   10                                                        /*!< LCD PAL27: B04_0 Position           */
+#define LCD_PAL27_B04_0_Msk                                   (0x1fUL << LCD_PAL27_B04_0_Pos)                           /*!< LCD PAL27: B04_0 Mask               */
+#define LCD_PAL27_I0_Pos                                      15                                                        /*!< LCD PAL27: I0 Position              */
+#define LCD_PAL27_I0_Msk                                      (0x01UL << LCD_PAL27_I0_Pos)                              /*!< LCD PAL27: I0 Mask                  */
+#define LCD_PAL27_R14_0_Pos                                   16                                                        /*!< LCD PAL27: R14_0 Position           */
+#define LCD_PAL27_R14_0_Msk                                   (0x1fUL << LCD_PAL27_R14_0_Pos)                           /*!< LCD PAL27: R14_0 Mask               */
+#define LCD_PAL27_G14_0_Pos                                   21                                                        /*!< LCD PAL27: G14_0 Position           */
+#define LCD_PAL27_G14_0_Msk                                   (0x1fUL << LCD_PAL27_G14_0_Pos)                           /*!< LCD PAL27: G14_0 Mask               */
+#define LCD_PAL27_B14_0_Pos                                   26                                                        /*!< LCD PAL27: B14_0 Position           */
+#define LCD_PAL27_B14_0_Msk                                   (0x1fUL << LCD_PAL27_B14_0_Pos)                           /*!< LCD PAL27: B14_0 Mask               */
+#define LCD_PAL27_I1_Pos                                      31                                                        /*!< LCD PAL27: I1 Position              */
+#define LCD_PAL27_I1_Msk                                      (0x01UL << LCD_PAL27_I1_Pos)                              /*!< LCD PAL27: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL28  -------------------------------------------
+#define LCD_PAL28_R04_0_Pos                                   0                                                         /*!< LCD PAL28: R04_0 Position           */
+#define LCD_PAL28_R04_0_Msk                                   (0x1fUL << LCD_PAL28_R04_0_Pos)                           /*!< LCD PAL28: R04_0 Mask               */
+#define LCD_PAL28_G04_0_Pos                                   5                                                         /*!< LCD PAL28: G04_0 Position           */
+#define LCD_PAL28_G04_0_Msk                                   (0x1fUL << LCD_PAL28_G04_0_Pos)                           /*!< LCD PAL28: G04_0 Mask               */
+#define LCD_PAL28_B04_0_Pos                                   10                                                        /*!< LCD PAL28: B04_0 Position           */
+#define LCD_PAL28_B04_0_Msk                                   (0x1fUL << LCD_PAL28_B04_0_Pos)                           /*!< LCD PAL28: B04_0 Mask               */
+#define LCD_PAL28_I0_Pos                                      15                                                        /*!< LCD PAL28: I0 Position              */
+#define LCD_PAL28_I0_Msk                                      (0x01UL << LCD_PAL28_I0_Pos)                              /*!< LCD PAL28: I0 Mask                  */
+#define LCD_PAL28_R14_0_Pos                                   16                                                        /*!< LCD PAL28: R14_0 Position           */
+#define LCD_PAL28_R14_0_Msk                                   (0x1fUL << LCD_PAL28_R14_0_Pos)                           /*!< LCD PAL28: R14_0 Mask               */
+#define LCD_PAL28_G14_0_Pos                                   21                                                        /*!< LCD PAL28: G14_0 Position           */
+#define LCD_PAL28_G14_0_Msk                                   (0x1fUL << LCD_PAL28_G14_0_Pos)                           /*!< LCD PAL28: G14_0 Mask               */
+#define LCD_PAL28_B14_0_Pos                                   26                                                        /*!< LCD PAL28: B14_0 Position           */
+#define LCD_PAL28_B14_0_Msk                                   (0x1fUL << LCD_PAL28_B14_0_Pos)                           /*!< LCD PAL28: B14_0 Mask               */
+#define LCD_PAL28_I1_Pos                                      31                                                        /*!< LCD PAL28: I1 Position              */
+#define LCD_PAL28_I1_Msk                                      (0x01UL << LCD_PAL28_I1_Pos)                              /*!< LCD PAL28: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL29  -------------------------------------------
+#define LCD_PAL29_R04_0_Pos                                   0                                                         /*!< LCD PAL29: R04_0 Position           */
+#define LCD_PAL29_R04_0_Msk                                   (0x1fUL << LCD_PAL29_R04_0_Pos)                           /*!< LCD PAL29: R04_0 Mask               */
+#define LCD_PAL29_G04_0_Pos                                   5                                                         /*!< LCD PAL29: G04_0 Position           */
+#define LCD_PAL29_G04_0_Msk                                   (0x1fUL << LCD_PAL29_G04_0_Pos)                           /*!< LCD PAL29: G04_0 Mask               */
+#define LCD_PAL29_B04_0_Pos                                   10                                                        /*!< LCD PAL29: B04_0 Position           */
+#define LCD_PAL29_B04_0_Msk                                   (0x1fUL << LCD_PAL29_B04_0_Pos)                           /*!< LCD PAL29: B04_0 Mask               */
+#define LCD_PAL29_I0_Pos                                      15                                                        /*!< LCD PAL29: I0 Position              */
+#define LCD_PAL29_I0_Msk                                      (0x01UL << LCD_PAL29_I0_Pos)                              /*!< LCD PAL29: I0 Mask                  */
+#define LCD_PAL29_R14_0_Pos                                   16                                                        /*!< LCD PAL29: R14_0 Position           */
+#define LCD_PAL29_R14_0_Msk                                   (0x1fUL << LCD_PAL29_R14_0_Pos)                           /*!< LCD PAL29: R14_0 Mask               */
+#define LCD_PAL29_G14_0_Pos                                   21                                                        /*!< LCD PAL29: G14_0 Position           */
+#define LCD_PAL29_G14_0_Msk                                   (0x1fUL << LCD_PAL29_G14_0_Pos)                           /*!< LCD PAL29: G14_0 Mask               */
+#define LCD_PAL29_B14_0_Pos                                   26                                                        /*!< LCD PAL29: B14_0 Position           */
+#define LCD_PAL29_B14_0_Msk                                   (0x1fUL << LCD_PAL29_B14_0_Pos)                           /*!< LCD PAL29: B14_0 Mask               */
+#define LCD_PAL29_I1_Pos                                      31                                                        /*!< LCD PAL29: I1 Position              */
+#define LCD_PAL29_I1_Msk                                      (0x01UL << LCD_PAL29_I1_Pos)                              /*!< LCD PAL29: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL30  -------------------------------------------
+#define LCD_PAL30_R04_0_Pos                                   0                                                         /*!< LCD PAL30: R04_0 Position           */
+#define LCD_PAL30_R04_0_Msk                                   (0x1fUL << LCD_PAL30_R04_0_Pos)                           /*!< LCD PAL30: R04_0 Mask               */
+#define LCD_PAL30_G04_0_Pos                                   5                                                         /*!< LCD PAL30: G04_0 Position           */
+#define LCD_PAL30_G04_0_Msk                                   (0x1fUL << LCD_PAL30_G04_0_Pos)                           /*!< LCD PAL30: G04_0 Mask               */
+#define LCD_PAL30_B04_0_Pos                                   10                                                        /*!< LCD PAL30: B04_0 Position           */
+#define LCD_PAL30_B04_0_Msk                                   (0x1fUL << LCD_PAL30_B04_0_Pos)                           /*!< LCD PAL30: B04_0 Mask               */
+#define LCD_PAL30_I0_Pos                                      15                                                        /*!< LCD PAL30: I0 Position              */
+#define LCD_PAL30_I0_Msk                                      (0x01UL << LCD_PAL30_I0_Pos)                              /*!< LCD PAL30: I0 Mask                  */
+#define LCD_PAL30_R14_0_Pos                                   16                                                        /*!< LCD PAL30: R14_0 Position           */
+#define LCD_PAL30_R14_0_Msk                                   (0x1fUL << LCD_PAL30_R14_0_Pos)                           /*!< LCD PAL30: R14_0 Mask               */
+#define LCD_PAL30_G14_0_Pos                                   21                                                        /*!< LCD PAL30: G14_0 Position           */
+#define LCD_PAL30_G14_0_Msk                                   (0x1fUL << LCD_PAL30_G14_0_Pos)                           /*!< LCD PAL30: G14_0 Mask               */
+#define LCD_PAL30_B14_0_Pos                                   26                                                        /*!< LCD PAL30: B14_0 Position           */
+#define LCD_PAL30_B14_0_Msk                                   (0x1fUL << LCD_PAL30_B14_0_Pos)                           /*!< LCD PAL30: B14_0 Mask               */
+#define LCD_PAL30_I1_Pos                                      31                                                        /*!< LCD PAL30: I1 Position              */
+#define LCD_PAL30_I1_Msk                                      (0x01UL << LCD_PAL30_I1_Pos)                              /*!< LCD PAL30: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL31  -------------------------------------------
+#define LCD_PAL31_R04_0_Pos                                   0                                                         /*!< LCD PAL31: R04_0 Position           */
+#define LCD_PAL31_R04_0_Msk                                   (0x1fUL << LCD_PAL31_R04_0_Pos)                           /*!< LCD PAL31: R04_0 Mask               */
+#define LCD_PAL31_G04_0_Pos                                   5                                                         /*!< LCD PAL31: G04_0 Position           */
+#define LCD_PAL31_G04_0_Msk                                   (0x1fUL << LCD_PAL31_G04_0_Pos)                           /*!< LCD PAL31: G04_0 Mask               */
+#define LCD_PAL31_B04_0_Pos                                   10                                                        /*!< LCD PAL31: B04_0 Position           */
+#define LCD_PAL31_B04_0_Msk                                   (0x1fUL << LCD_PAL31_B04_0_Pos)                           /*!< LCD PAL31: B04_0 Mask               */
+#define LCD_PAL31_I0_Pos                                      15                                                        /*!< LCD PAL31: I0 Position              */
+#define LCD_PAL31_I0_Msk                                      (0x01UL << LCD_PAL31_I0_Pos)                              /*!< LCD PAL31: I0 Mask                  */
+#define LCD_PAL31_R14_0_Pos                                   16                                                        /*!< LCD PAL31: R14_0 Position           */
+#define LCD_PAL31_R14_0_Msk                                   (0x1fUL << LCD_PAL31_R14_0_Pos)                           /*!< LCD PAL31: R14_0 Mask               */
+#define LCD_PAL31_G14_0_Pos                                   21                                                        /*!< LCD PAL31: G14_0 Position           */
+#define LCD_PAL31_G14_0_Msk                                   (0x1fUL << LCD_PAL31_G14_0_Pos)                           /*!< LCD PAL31: G14_0 Mask               */
+#define LCD_PAL31_B14_0_Pos                                   26                                                        /*!< LCD PAL31: B14_0 Position           */
+#define LCD_PAL31_B14_0_Msk                                   (0x1fUL << LCD_PAL31_B14_0_Pos)                           /*!< LCD PAL31: B14_0 Mask               */
+#define LCD_PAL31_I1_Pos                                      31                                                        /*!< LCD PAL31: I1 Position              */
+#define LCD_PAL31_I1_Msk                                      (0x01UL << LCD_PAL31_I1_Pos)                              /*!< LCD PAL31: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL32  -------------------------------------------
+#define LCD_PAL32_R04_0_Pos                                   0                                                         /*!< LCD PAL32: R04_0 Position           */
+#define LCD_PAL32_R04_0_Msk                                   (0x1fUL << LCD_PAL32_R04_0_Pos)                           /*!< LCD PAL32: R04_0 Mask               */
+#define LCD_PAL32_G04_0_Pos                                   5                                                         /*!< LCD PAL32: G04_0 Position           */
+#define LCD_PAL32_G04_0_Msk                                   (0x1fUL << LCD_PAL32_G04_0_Pos)                           /*!< LCD PAL32: G04_0 Mask               */
+#define LCD_PAL32_B04_0_Pos                                   10                                                        /*!< LCD PAL32: B04_0 Position           */
+#define LCD_PAL32_B04_0_Msk                                   (0x1fUL << LCD_PAL32_B04_0_Pos)                           /*!< LCD PAL32: B04_0 Mask               */
+#define LCD_PAL32_I0_Pos                                      15                                                        /*!< LCD PAL32: I0 Position              */
+#define LCD_PAL32_I0_Msk                                      (0x01UL << LCD_PAL32_I0_Pos)                              /*!< LCD PAL32: I0 Mask                  */
+#define LCD_PAL32_R14_0_Pos                                   16                                                        /*!< LCD PAL32: R14_0 Position           */
+#define LCD_PAL32_R14_0_Msk                                   (0x1fUL << LCD_PAL32_R14_0_Pos)                           /*!< LCD PAL32: R14_0 Mask               */
+#define LCD_PAL32_G14_0_Pos                                   21                                                        /*!< LCD PAL32: G14_0 Position           */
+#define LCD_PAL32_G14_0_Msk                                   (0x1fUL << LCD_PAL32_G14_0_Pos)                           /*!< LCD PAL32: G14_0 Mask               */
+#define LCD_PAL32_B14_0_Pos                                   26                                                        /*!< LCD PAL32: B14_0 Position           */
+#define LCD_PAL32_B14_0_Msk                                   (0x1fUL << LCD_PAL32_B14_0_Pos)                           /*!< LCD PAL32: B14_0 Mask               */
+#define LCD_PAL32_I1_Pos                                      31                                                        /*!< LCD PAL32: I1 Position              */
+#define LCD_PAL32_I1_Msk                                      (0x01UL << LCD_PAL32_I1_Pos)                              /*!< LCD PAL32: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL33  -------------------------------------------
+#define LCD_PAL33_R04_0_Pos                                   0                                                         /*!< LCD PAL33: R04_0 Position           */
+#define LCD_PAL33_R04_0_Msk                                   (0x1fUL << LCD_PAL33_R04_0_Pos)                           /*!< LCD PAL33: R04_0 Mask               */
+#define LCD_PAL33_G04_0_Pos                                   5                                                         /*!< LCD PAL33: G04_0 Position           */
+#define LCD_PAL33_G04_0_Msk                                   (0x1fUL << LCD_PAL33_G04_0_Pos)                           /*!< LCD PAL33: G04_0 Mask               */
+#define LCD_PAL33_B04_0_Pos                                   10                                                        /*!< LCD PAL33: B04_0 Position           */
+#define LCD_PAL33_B04_0_Msk                                   (0x1fUL << LCD_PAL33_B04_0_Pos)                           /*!< LCD PAL33: B04_0 Mask               */
+#define LCD_PAL33_I0_Pos                                      15                                                        /*!< LCD PAL33: I0 Position              */
+#define LCD_PAL33_I0_Msk                                      (0x01UL << LCD_PAL33_I0_Pos)                              /*!< LCD PAL33: I0 Mask                  */
+#define LCD_PAL33_R14_0_Pos                                   16                                                        /*!< LCD PAL33: R14_0 Position           */
+#define LCD_PAL33_R14_0_Msk                                   (0x1fUL << LCD_PAL33_R14_0_Pos)                           /*!< LCD PAL33: R14_0 Mask               */
+#define LCD_PAL33_G14_0_Pos                                   21                                                        /*!< LCD PAL33: G14_0 Position           */
+#define LCD_PAL33_G14_0_Msk                                   (0x1fUL << LCD_PAL33_G14_0_Pos)                           /*!< LCD PAL33: G14_0 Mask               */
+#define LCD_PAL33_B14_0_Pos                                   26                                                        /*!< LCD PAL33: B14_0 Position           */
+#define LCD_PAL33_B14_0_Msk                                   (0x1fUL << LCD_PAL33_B14_0_Pos)                           /*!< LCD PAL33: B14_0 Mask               */
+#define LCD_PAL33_I1_Pos                                      31                                                        /*!< LCD PAL33: I1 Position              */
+#define LCD_PAL33_I1_Msk                                      (0x01UL << LCD_PAL33_I1_Pos)                              /*!< LCD PAL33: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL34  -------------------------------------------
+#define LCD_PAL34_R04_0_Pos                                   0                                                         /*!< LCD PAL34: R04_0 Position           */
+#define LCD_PAL34_R04_0_Msk                                   (0x1fUL << LCD_PAL34_R04_0_Pos)                           /*!< LCD PAL34: R04_0 Mask               */
+#define LCD_PAL34_G04_0_Pos                                   5                                                         /*!< LCD PAL34: G04_0 Position           */
+#define LCD_PAL34_G04_0_Msk                                   (0x1fUL << LCD_PAL34_G04_0_Pos)                           /*!< LCD PAL34: G04_0 Mask               */
+#define LCD_PAL34_B04_0_Pos                                   10                                                        /*!< LCD PAL34: B04_0 Position           */
+#define LCD_PAL34_B04_0_Msk                                   (0x1fUL << LCD_PAL34_B04_0_Pos)                           /*!< LCD PAL34: B04_0 Mask               */
+#define LCD_PAL34_I0_Pos                                      15                                                        /*!< LCD PAL34: I0 Position              */
+#define LCD_PAL34_I0_Msk                                      (0x01UL << LCD_PAL34_I0_Pos)                              /*!< LCD PAL34: I0 Mask                  */
+#define LCD_PAL34_R14_0_Pos                                   16                                                        /*!< LCD PAL34: R14_0 Position           */
+#define LCD_PAL34_R14_0_Msk                                   (0x1fUL << LCD_PAL34_R14_0_Pos)                           /*!< LCD PAL34: R14_0 Mask               */
+#define LCD_PAL34_G14_0_Pos                                   21                                                        /*!< LCD PAL34: G14_0 Position           */
+#define LCD_PAL34_G14_0_Msk                                   (0x1fUL << LCD_PAL34_G14_0_Pos)                           /*!< LCD PAL34: G14_0 Mask               */
+#define LCD_PAL34_B14_0_Pos                                   26                                                        /*!< LCD PAL34: B14_0 Position           */
+#define LCD_PAL34_B14_0_Msk                                   (0x1fUL << LCD_PAL34_B14_0_Pos)                           /*!< LCD PAL34: B14_0 Mask               */
+#define LCD_PAL34_I1_Pos                                      31                                                        /*!< LCD PAL34: I1 Position              */
+#define LCD_PAL34_I1_Msk                                      (0x01UL << LCD_PAL34_I1_Pos)                              /*!< LCD PAL34: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL35  -------------------------------------------
+#define LCD_PAL35_R04_0_Pos                                   0                                                         /*!< LCD PAL35: R04_0 Position           */
+#define LCD_PAL35_R04_0_Msk                                   (0x1fUL << LCD_PAL35_R04_0_Pos)                           /*!< LCD PAL35: R04_0 Mask               */
+#define LCD_PAL35_G04_0_Pos                                   5                                                         /*!< LCD PAL35: G04_0 Position           */
+#define LCD_PAL35_G04_0_Msk                                   (0x1fUL << LCD_PAL35_G04_0_Pos)                           /*!< LCD PAL35: G04_0 Mask               */
+#define LCD_PAL35_B04_0_Pos                                   10                                                        /*!< LCD PAL35: B04_0 Position           */
+#define LCD_PAL35_B04_0_Msk                                   (0x1fUL << LCD_PAL35_B04_0_Pos)                           /*!< LCD PAL35: B04_0 Mask               */
+#define LCD_PAL35_I0_Pos                                      15                                                        /*!< LCD PAL35: I0 Position              */
+#define LCD_PAL35_I0_Msk                                      (0x01UL << LCD_PAL35_I0_Pos)                              /*!< LCD PAL35: I0 Mask                  */
+#define LCD_PAL35_R14_0_Pos                                   16                                                        /*!< LCD PAL35: R14_0 Position           */
+#define LCD_PAL35_R14_0_Msk                                   (0x1fUL << LCD_PAL35_R14_0_Pos)                           /*!< LCD PAL35: R14_0 Mask               */
+#define LCD_PAL35_G14_0_Pos                                   21                                                        /*!< LCD PAL35: G14_0 Position           */
+#define LCD_PAL35_G14_0_Msk                                   (0x1fUL << LCD_PAL35_G14_0_Pos)                           /*!< LCD PAL35: G14_0 Mask               */
+#define LCD_PAL35_B14_0_Pos                                   26                                                        /*!< LCD PAL35: B14_0 Position           */
+#define LCD_PAL35_B14_0_Msk                                   (0x1fUL << LCD_PAL35_B14_0_Pos)                           /*!< LCD PAL35: B14_0 Mask               */
+#define LCD_PAL35_I1_Pos                                      31                                                        /*!< LCD PAL35: I1 Position              */
+#define LCD_PAL35_I1_Msk                                      (0x01UL << LCD_PAL35_I1_Pos)                              /*!< LCD PAL35: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL36  -------------------------------------------
+#define LCD_PAL36_R04_0_Pos                                   0                                                         /*!< LCD PAL36: R04_0 Position           */
+#define LCD_PAL36_R04_0_Msk                                   (0x1fUL << LCD_PAL36_R04_0_Pos)                           /*!< LCD PAL36: R04_0 Mask               */
+#define LCD_PAL36_G04_0_Pos                                   5                                                         /*!< LCD PAL36: G04_0 Position           */
+#define LCD_PAL36_G04_0_Msk                                   (0x1fUL << LCD_PAL36_G04_0_Pos)                           /*!< LCD PAL36: G04_0 Mask               */
+#define LCD_PAL36_B04_0_Pos                                   10                                                        /*!< LCD PAL36: B04_0 Position           */
+#define LCD_PAL36_B04_0_Msk                                   (0x1fUL << LCD_PAL36_B04_0_Pos)                           /*!< LCD PAL36: B04_0 Mask               */
+#define LCD_PAL36_I0_Pos                                      15                                                        /*!< LCD PAL36: I0 Position              */
+#define LCD_PAL36_I0_Msk                                      (0x01UL << LCD_PAL36_I0_Pos)                              /*!< LCD PAL36: I0 Mask                  */
+#define LCD_PAL36_R14_0_Pos                                   16                                                        /*!< LCD PAL36: R14_0 Position           */
+#define LCD_PAL36_R14_0_Msk                                   (0x1fUL << LCD_PAL36_R14_0_Pos)                           /*!< LCD PAL36: R14_0 Mask               */
+#define LCD_PAL36_G14_0_Pos                                   21                                                        /*!< LCD PAL36: G14_0 Position           */
+#define LCD_PAL36_G14_0_Msk                                   (0x1fUL << LCD_PAL36_G14_0_Pos)                           /*!< LCD PAL36: G14_0 Mask               */
+#define LCD_PAL36_B14_0_Pos                                   26                                                        /*!< LCD PAL36: B14_0 Position           */
+#define LCD_PAL36_B14_0_Msk                                   (0x1fUL << LCD_PAL36_B14_0_Pos)                           /*!< LCD PAL36: B14_0 Mask               */
+#define LCD_PAL36_I1_Pos                                      31                                                        /*!< LCD PAL36: I1 Position              */
+#define LCD_PAL36_I1_Msk                                      (0x01UL << LCD_PAL36_I1_Pos)                              /*!< LCD PAL36: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL37  -------------------------------------------
+#define LCD_PAL37_R04_0_Pos                                   0                                                         /*!< LCD PAL37: R04_0 Position           */
+#define LCD_PAL37_R04_0_Msk                                   (0x1fUL << LCD_PAL37_R04_0_Pos)                           /*!< LCD PAL37: R04_0 Mask               */
+#define LCD_PAL37_G04_0_Pos                                   5                                                         /*!< LCD PAL37: G04_0 Position           */
+#define LCD_PAL37_G04_0_Msk                                   (0x1fUL << LCD_PAL37_G04_0_Pos)                           /*!< LCD PAL37: G04_0 Mask               */
+#define LCD_PAL37_B04_0_Pos                                   10                                                        /*!< LCD PAL37: B04_0 Position           */
+#define LCD_PAL37_B04_0_Msk                                   (0x1fUL << LCD_PAL37_B04_0_Pos)                           /*!< LCD PAL37: B04_0 Mask               */
+#define LCD_PAL37_I0_Pos                                      15                                                        /*!< LCD PAL37: I0 Position              */
+#define LCD_PAL37_I0_Msk                                      (0x01UL << LCD_PAL37_I0_Pos)                              /*!< LCD PAL37: I0 Mask                  */
+#define LCD_PAL37_R14_0_Pos                                   16                                                        /*!< LCD PAL37: R14_0 Position           */
+#define LCD_PAL37_R14_0_Msk                                   (0x1fUL << LCD_PAL37_R14_0_Pos)                           /*!< LCD PAL37: R14_0 Mask               */
+#define LCD_PAL37_G14_0_Pos                                   21                                                        /*!< LCD PAL37: G14_0 Position           */
+#define LCD_PAL37_G14_0_Msk                                   (0x1fUL << LCD_PAL37_G14_0_Pos)                           /*!< LCD PAL37: G14_0 Mask               */
+#define LCD_PAL37_B14_0_Pos                                   26                                                        /*!< LCD PAL37: B14_0 Position           */
+#define LCD_PAL37_B14_0_Msk                                   (0x1fUL << LCD_PAL37_B14_0_Pos)                           /*!< LCD PAL37: B14_0 Mask               */
+#define LCD_PAL37_I1_Pos                                      31                                                        /*!< LCD PAL37: I1 Position              */
+#define LCD_PAL37_I1_Msk                                      (0x01UL << LCD_PAL37_I1_Pos)                              /*!< LCD PAL37: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL38  -------------------------------------------
+#define LCD_PAL38_R04_0_Pos                                   0                                                         /*!< LCD PAL38: R04_0 Position           */
+#define LCD_PAL38_R04_0_Msk                                   (0x1fUL << LCD_PAL38_R04_0_Pos)                           /*!< LCD PAL38: R04_0 Mask               */
+#define LCD_PAL38_G04_0_Pos                                   5                                                         /*!< LCD PAL38: G04_0 Position           */
+#define LCD_PAL38_G04_0_Msk                                   (0x1fUL << LCD_PAL38_G04_0_Pos)                           /*!< LCD PAL38: G04_0 Mask               */
+#define LCD_PAL38_B04_0_Pos                                   10                                                        /*!< LCD PAL38: B04_0 Position           */
+#define LCD_PAL38_B04_0_Msk                                   (0x1fUL << LCD_PAL38_B04_0_Pos)                           /*!< LCD PAL38: B04_0 Mask               */
+#define LCD_PAL38_I0_Pos                                      15                                                        /*!< LCD PAL38: I0 Position              */
+#define LCD_PAL38_I0_Msk                                      (0x01UL << LCD_PAL38_I0_Pos)                              /*!< LCD PAL38: I0 Mask                  */
+#define LCD_PAL38_R14_0_Pos                                   16                                                        /*!< LCD PAL38: R14_0 Position           */
+#define LCD_PAL38_R14_0_Msk                                   (0x1fUL << LCD_PAL38_R14_0_Pos)                           /*!< LCD PAL38: R14_0 Mask               */
+#define LCD_PAL38_G14_0_Pos                                   21                                                        /*!< LCD PAL38: G14_0 Position           */
+#define LCD_PAL38_G14_0_Msk                                   (0x1fUL << LCD_PAL38_G14_0_Pos)                           /*!< LCD PAL38: G14_0 Mask               */
+#define LCD_PAL38_B14_0_Pos                                   26                                                        /*!< LCD PAL38: B14_0 Position           */
+#define LCD_PAL38_B14_0_Msk                                   (0x1fUL << LCD_PAL38_B14_0_Pos)                           /*!< LCD PAL38: B14_0 Mask               */
+#define LCD_PAL38_I1_Pos                                      31                                                        /*!< LCD PAL38: I1 Position              */
+#define LCD_PAL38_I1_Msk                                      (0x01UL << LCD_PAL38_I1_Pos)                              /*!< LCD PAL38: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL39  -------------------------------------------
+#define LCD_PAL39_R04_0_Pos                                   0                                                         /*!< LCD PAL39: R04_0 Position           */
+#define LCD_PAL39_R04_0_Msk                                   (0x1fUL << LCD_PAL39_R04_0_Pos)                           /*!< LCD PAL39: R04_0 Mask               */
+#define LCD_PAL39_G04_0_Pos                                   5                                                         /*!< LCD PAL39: G04_0 Position           */
+#define LCD_PAL39_G04_0_Msk                                   (0x1fUL << LCD_PAL39_G04_0_Pos)                           /*!< LCD PAL39: G04_0 Mask               */
+#define LCD_PAL39_B04_0_Pos                                   10                                                        /*!< LCD PAL39: B04_0 Position           */
+#define LCD_PAL39_B04_0_Msk                                   (0x1fUL << LCD_PAL39_B04_0_Pos)                           /*!< LCD PAL39: B04_0 Mask               */
+#define LCD_PAL39_I0_Pos                                      15                                                        /*!< LCD PAL39: I0 Position              */
+#define LCD_PAL39_I0_Msk                                      (0x01UL << LCD_PAL39_I0_Pos)                              /*!< LCD PAL39: I0 Mask                  */
+#define LCD_PAL39_R14_0_Pos                                   16                                                        /*!< LCD PAL39: R14_0 Position           */
+#define LCD_PAL39_R14_0_Msk                                   (0x1fUL << LCD_PAL39_R14_0_Pos)                           /*!< LCD PAL39: R14_0 Mask               */
+#define LCD_PAL39_G14_0_Pos                                   21                                                        /*!< LCD PAL39: G14_0 Position           */
+#define LCD_PAL39_G14_0_Msk                                   (0x1fUL << LCD_PAL39_G14_0_Pos)                           /*!< LCD PAL39: G14_0 Mask               */
+#define LCD_PAL39_B14_0_Pos                                   26                                                        /*!< LCD PAL39: B14_0 Position           */
+#define LCD_PAL39_B14_0_Msk                                   (0x1fUL << LCD_PAL39_B14_0_Pos)                           /*!< LCD PAL39: B14_0 Mask               */
+#define LCD_PAL39_I1_Pos                                      31                                                        /*!< LCD PAL39: I1 Position              */
+#define LCD_PAL39_I1_Msk                                      (0x01UL << LCD_PAL39_I1_Pos)                              /*!< LCD PAL39: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL40  -------------------------------------------
+#define LCD_PAL40_R04_0_Pos                                   0                                                         /*!< LCD PAL40: R04_0 Position           */
+#define LCD_PAL40_R04_0_Msk                                   (0x1fUL << LCD_PAL40_R04_0_Pos)                           /*!< LCD PAL40: R04_0 Mask               */
+#define LCD_PAL40_G04_0_Pos                                   5                                                         /*!< LCD PAL40: G04_0 Position           */
+#define LCD_PAL40_G04_0_Msk                                   (0x1fUL << LCD_PAL40_G04_0_Pos)                           /*!< LCD PAL40: G04_0 Mask               */
+#define LCD_PAL40_B04_0_Pos                                   10                                                        /*!< LCD PAL40: B04_0 Position           */
+#define LCD_PAL40_B04_0_Msk                                   (0x1fUL << LCD_PAL40_B04_0_Pos)                           /*!< LCD PAL40: B04_0 Mask               */
+#define LCD_PAL40_I0_Pos                                      15                                                        /*!< LCD PAL40: I0 Position              */
+#define LCD_PAL40_I0_Msk                                      (0x01UL << LCD_PAL40_I0_Pos)                              /*!< LCD PAL40: I0 Mask                  */
+#define LCD_PAL40_R14_0_Pos                                   16                                                        /*!< LCD PAL40: R14_0 Position           */
+#define LCD_PAL40_R14_0_Msk                                   (0x1fUL << LCD_PAL40_R14_0_Pos)                           /*!< LCD PAL40: R14_0 Mask               */
+#define LCD_PAL40_G14_0_Pos                                   21                                                        /*!< LCD PAL40: G14_0 Position           */
+#define LCD_PAL40_G14_0_Msk                                   (0x1fUL << LCD_PAL40_G14_0_Pos)                           /*!< LCD PAL40: G14_0 Mask               */
+#define LCD_PAL40_B14_0_Pos                                   26                                                        /*!< LCD PAL40: B14_0 Position           */
+#define LCD_PAL40_B14_0_Msk                                   (0x1fUL << LCD_PAL40_B14_0_Pos)                           /*!< LCD PAL40: B14_0 Mask               */
+#define LCD_PAL40_I1_Pos                                      31                                                        /*!< LCD PAL40: I1 Position              */
+#define LCD_PAL40_I1_Msk                                      (0x01UL << LCD_PAL40_I1_Pos)                              /*!< LCD PAL40: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL41  -------------------------------------------
+#define LCD_PAL41_R04_0_Pos                                   0                                                         /*!< LCD PAL41: R04_0 Position           */
+#define LCD_PAL41_R04_0_Msk                                   (0x1fUL << LCD_PAL41_R04_0_Pos)                           /*!< LCD PAL41: R04_0 Mask               */
+#define LCD_PAL41_G04_0_Pos                                   5                                                         /*!< LCD PAL41: G04_0 Position           */
+#define LCD_PAL41_G04_0_Msk                                   (0x1fUL << LCD_PAL41_G04_0_Pos)                           /*!< LCD PAL41: G04_0 Mask               */
+#define LCD_PAL41_B04_0_Pos                                   10                                                        /*!< LCD PAL41: B04_0 Position           */
+#define LCD_PAL41_B04_0_Msk                                   (0x1fUL << LCD_PAL41_B04_0_Pos)                           /*!< LCD PAL41: B04_0 Mask               */
+#define LCD_PAL41_I0_Pos                                      15                                                        /*!< LCD PAL41: I0 Position              */
+#define LCD_PAL41_I0_Msk                                      (0x01UL << LCD_PAL41_I0_Pos)                              /*!< LCD PAL41: I0 Mask                  */
+#define LCD_PAL41_R14_0_Pos                                   16                                                        /*!< LCD PAL41: R14_0 Position           */
+#define LCD_PAL41_R14_0_Msk                                   (0x1fUL << LCD_PAL41_R14_0_Pos)                           /*!< LCD PAL41: R14_0 Mask               */
+#define LCD_PAL41_G14_0_Pos                                   21                                                        /*!< LCD PAL41: G14_0 Position           */
+#define LCD_PAL41_G14_0_Msk                                   (0x1fUL << LCD_PAL41_G14_0_Pos)                           /*!< LCD PAL41: G14_0 Mask               */
+#define LCD_PAL41_B14_0_Pos                                   26                                                        /*!< LCD PAL41: B14_0 Position           */
+#define LCD_PAL41_B14_0_Msk                                   (0x1fUL << LCD_PAL41_B14_0_Pos)                           /*!< LCD PAL41: B14_0 Mask               */
+#define LCD_PAL41_I1_Pos                                      31                                                        /*!< LCD PAL41: I1 Position              */
+#define LCD_PAL41_I1_Msk                                      (0x01UL << LCD_PAL41_I1_Pos)                              /*!< LCD PAL41: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL42  -------------------------------------------
+#define LCD_PAL42_R04_0_Pos                                   0                                                         /*!< LCD PAL42: R04_0 Position           */
+#define LCD_PAL42_R04_0_Msk                                   (0x1fUL << LCD_PAL42_R04_0_Pos)                           /*!< LCD PAL42: R04_0 Mask               */
+#define LCD_PAL42_G04_0_Pos                                   5                                                         /*!< LCD PAL42: G04_0 Position           */
+#define LCD_PAL42_G04_0_Msk                                   (0x1fUL << LCD_PAL42_G04_0_Pos)                           /*!< LCD PAL42: G04_0 Mask               */
+#define LCD_PAL42_B04_0_Pos                                   10                                                        /*!< LCD PAL42: B04_0 Position           */
+#define LCD_PAL42_B04_0_Msk                                   (0x1fUL << LCD_PAL42_B04_0_Pos)                           /*!< LCD PAL42: B04_0 Mask               */
+#define LCD_PAL42_I0_Pos                                      15                                                        /*!< LCD PAL42: I0 Position              */
+#define LCD_PAL42_I0_Msk                                      (0x01UL << LCD_PAL42_I0_Pos)                              /*!< LCD PAL42: I0 Mask                  */
+#define LCD_PAL42_R14_0_Pos                                   16                                                        /*!< LCD PAL42: R14_0 Position           */
+#define LCD_PAL42_R14_0_Msk                                   (0x1fUL << LCD_PAL42_R14_0_Pos)                           /*!< LCD PAL42: R14_0 Mask               */
+#define LCD_PAL42_G14_0_Pos                                   21                                                        /*!< LCD PAL42: G14_0 Position           */
+#define LCD_PAL42_G14_0_Msk                                   (0x1fUL << LCD_PAL42_G14_0_Pos)                           /*!< LCD PAL42: G14_0 Mask               */
+#define LCD_PAL42_B14_0_Pos                                   26                                                        /*!< LCD PAL42: B14_0 Position           */
+#define LCD_PAL42_B14_0_Msk                                   (0x1fUL << LCD_PAL42_B14_0_Pos)                           /*!< LCD PAL42: B14_0 Mask               */
+#define LCD_PAL42_I1_Pos                                      31                                                        /*!< LCD PAL42: I1 Position              */
+#define LCD_PAL42_I1_Msk                                      (0x01UL << LCD_PAL42_I1_Pos)                              /*!< LCD PAL42: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL43  -------------------------------------------
+#define LCD_PAL43_R04_0_Pos                                   0                                                         /*!< LCD PAL43: R04_0 Position           */
+#define LCD_PAL43_R04_0_Msk                                   (0x1fUL << LCD_PAL43_R04_0_Pos)                           /*!< LCD PAL43: R04_0 Mask               */
+#define LCD_PAL43_G04_0_Pos                                   5                                                         /*!< LCD PAL43: G04_0 Position           */
+#define LCD_PAL43_G04_0_Msk                                   (0x1fUL << LCD_PAL43_G04_0_Pos)                           /*!< LCD PAL43: G04_0 Mask               */
+#define LCD_PAL43_B04_0_Pos                                   10                                                        /*!< LCD PAL43: B04_0 Position           */
+#define LCD_PAL43_B04_0_Msk                                   (0x1fUL << LCD_PAL43_B04_0_Pos)                           /*!< LCD PAL43: B04_0 Mask               */
+#define LCD_PAL43_I0_Pos                                      15                                                        /*!< LCD PAL43: I0 Position              */
+#define LCD_PAL43_I0_Msk                                      (0x01UL << LCD_PAL43_I0_Pos)                              /*!< LCD PAL43: I0 Mask                  */
+#define LCD_PAL43_R14_0_Pos                                   16                                                        /*!< LCD PAL43: R14_0 Position           */
+#define LCD_PAL43_R14_0_Msk                                   (0x1fUL << LCD_PAL43_R14_0_Pos)                           /*!< LCD PAL43: R14_0 Mask               */
+#define LCD_PAL43_G14_0_Pos                                   21                                                        /*!< LCD PAL43: G14_0 Position           */
+#define LCD_PAL43_G14_0_Msk                                   (0x1fUL << LCD_PAL43_G14_0_Pos)                           /*!< LCD PAL43: G14_0 Mask               */
+#define LCD_PAL43_B14_0_Pos                                   26                                                        /*!< LCD PAL43: B14_0 Position           */
+#define LCD_PAL43_B14_0_Msk                                   (0x1fUL << LCD_PAL43_B14_0_Pos)                           /*!< LCD PAL43: B14_0 Mask               */
+#define LCD_PAL43_I1_Pos                                      31                                                        /*!< LCD PAL43: I1 Position              */
+#define LCD_PAL43_I1_Msk                                      (0x01UL << LCD_PAL43_I1_Pos)                              /*!< LCD PAL43: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL44  -------------------------------------------
+#define LCD_PAL44_R04_0_Pos                                   0                                                         /*!< LCD PAL44: R04_0 Position           */
+#define LCD_PAL44_R04_0_Msk                                   (0x1fUL << LCD_PAL44_R04_0_Pos)                           /*!< LCD PAL44: R04_0 Mask               */
+#define LCD_PAL44_G04_0_Pos                                   5                                                         /*!< LCD PAL44: G04_0 Position           */
+#define LCD_PAL44_G04_0_Msk                                   (0x1fUL << LCD_PAL44_G04_0_Pos)                           /*!< LCD PAL44: G04_0 Mask               */
+#define LCD_PAL44_B04_0_Pos                                   10                                                        /*!< LCD PAL44: B04_0 Position           */
+#define LCD_PAL44_B04_0_Msk                                   (0x1fUL << LCD_PAL44_B04_0_Pos)                           /*!< LCD PAL44: B04_0 Mask               */
+#define LCD_PAL44_I0_Pos                                      15                                                        /*!< LCD PAL44: I0 Position              */
+#define LCD_PAL44_I0_Msk                                      (0x01UL << LCD_PAL44_I0_Pos)                              /*!< LCD PAL44: I0 Mask                  */
+#define LCD_PAL44_R14_0_Pos                                   16                                                        /*!< LCD PAL44: R14_0 Position           */
+#define LCD_PAL44_R14_0_Msk                                   (0x1fUL << LCD_PAL44_R14_0_Pos)                           /*!< LCD PAL44: R14_0 Mask               */
+#define LCD_PAL44_G14_0_Pos                                   21                                                        /*!< LCD PAL44: G14_0 Position           */
+#define LCD_PAL44_G14_0_Msk                                   (0x1fUL << LCD_PAL44_G14_0_Pos)                           /*!< LCD PAL44: G14_0 Mask               */
+#define LCD_PAL44_B14_0_Pos                                   26                                                        /*!< LCD PAL44: B14_0 Position           */
+#define LCD_PAL44_B14_0_Msk                                   (0x1fUL << LCD_PAL44_B14_0_Pos)                           /*!< LCD PAL44: B14_0 Mask               */
+#define LCD_PAL44_I1_Pos                                      31                                                        /*!< LCD PAL44: I1 Position              */
+#define LCD_PAL44_I1_Msk                                      (0x01UL << LCD_PAL44_I1_Pos)                              /*!< LCD PAL44: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL45  -------------------------------------------
+#define LCD_PAL45_R04_0_Pos                                   0                                                         /*!< LCD PAL45: R04_0 Position           */
+#define LCD_PAL45_R04_0_Msk                                   (0x1fUL << LCD_PAL45_R04_0_Pos)                           /*!< LCD PAL45: R04_0 Mask               */
+#define LCD_PAL45_G04_0_Pos                                   5                                                         /*!< LCD PAL45: G04_0 Position           */
+#define LCD_PAL45_G04_0_Msk                                   (0x1fUL << LCD_PAL45_G04_0_Pos)                           /*!< LCD PAL45: G04_0 Mask               */
+#define LCD_PAL45_B04_0_Pos                                   10                                                        /*!< LCD PAL45: B04_0 Position           */
+#define LCD_PAL45_B04_0_Msk                                   (0x1fUL << LCD_PAL45_B04_0_Pos)                           /*!< LCD PAL45: B04_0 Mask               */
+#define LCD_PAL45_I0_Pos                                      15                                                        /*!< LCD PAL45: I0 Position              */
+#define LCD_PAL45_I0_Msk                                      (0x01UL << LCD_PAL45_I0_Pos)                              /*!< LCD PAL45: I0 Mask                  */
+#define LCD_PAL45_R14_0_Pos                                   16                                                        /*!< LCD PAL45: R14_0 Position           */
+#define LCD_PAL45_R14_0_Msk                                   (0x1fUL << LCD_PAL45_R14_0_Pos)                           /*!< LCD PAL45: R14_0 Mask               */
+#define LCD_PAL45_G14_0_Pos                                   21                                                        /*!< LCD PAL45: G14_0 Position           */
+#define LCD_PAL45_G14_0_Msk                                   (0x1fUL << LCD_PAL45_G14_0_Pos)                           /*!< LCD PAL45: G14_0 Mask               */
+#define LCD_PAL45_B14_0_Pos                                   26                                                        /*!< LCD PAL45: B14_0 Position           */
+#define LCD_PAL45_B14_0_Msk                                   (0x1fUL << LCD_PAL45_B14_0_Pos)                           /*!< LCD PAL45: B14_0 Mask               */
+#define LCD_PAL45_I1_Pos                                      31                                                        /*!< LCD PAL45: I1 Position              */
+#define LCD_PAL45_I1_Msk                                      (0x01UL << LCD_PAL45_I1_Pos)                              /*!< LCD PAL45: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL46  -------------------------------------------
+#define LCD_PAL46_R04_0_Pos                                   0                                                         /*!< LCD PAL46: R04_0 Position           */
+#define LCD_PAL46_R04_0_Msk                                   (0x1fUL << LCD_PAL46_R04_0_Pos)                           /*!< LCD PAL46: R04_0 Mask               */
+#define LCD_PAL46_G04_0_Pos                                   5                                                         /*!< LCD PAL46: G04_0 Position           */
+#define LCD_PAL46_G04_0_Msk                                   (0x1fUL << LCD_PAL46_G04_0_Pos)                           /*!< LCD PAL46: G04_0 Mask               */
+#define LCD_PAL46_B04_0_Pos                                   10                                                        /*!< LCD PAL46: B04_0 Position           */
+#define LCD_PAL46_B04_0_Msk                                   (0x1fUL << LCD_PAL46_B04_0_Pos)                           /*!< LCD PAL46: B04_0 Mask               */
+#define LCD_PAL46_I0_Pos                                      15                                                        /*!< LCD PAL46: I0 Position              */
+#define LCD_PAL46_I0_Msk                                      (0x01UL << LCD_PAL46_I0_Pos)                              /*!< LCD PAL46: I0 Mask                  */
+#define LCD_PAL46_R14_0_Pos                                   16                                                        /*!< LCD PAL46: R14_0 Position           */
+#define LCD_PAL46_R14_0_Msk                                   (0x1fUL << LCD_PAL46_R14_0_Pos)                           /*!< LCD PAL46: R14_0 Mask               */
+#define LCD_PAL46_G14_0_Pos                                   21                                                        /*!< LCD PAL46: G14_0 Position           */
+#define LCD_PAL46_G14_0_Msk                                   (0x1fUL << LCD_PAL46_G14_0_Pos)                           /*!< LCD PAL46: G14_0 Mask               */
+#define LCD_PAL46_B14_0_Pos                                   26                                                        /*!< LCD PAL46: B14_0 Position           */
+#define LCD_PAL46_B14_0_Msk                                   (0x1fUL << LCD_PAL46_B14_0_Pos)                           /*!< LCD PAL46: B14_0 Mask               */
+#define LCD_PAL46_I1_Pos                                      31                                                        /*!< LCD PAL46: I1 Position              */
+#define LCD_PAL46_I1_Msk                                      (0x01UL << LCD_PAL46_I1_Pos)                              /*!< LCD PAL46: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL47  -------------------------------------------
+#define LCD_PAL47_R04_0_Pos                                   0                                                         /*!< LCD PAL47: R04_0 Position           */
+#define LCD_PAL47_R04_0_Msk                                   (0x1fUL << LCD_PAL47_R04_0_Pos)                           /*!< LCD PAL47: R04_0 Mask               */
+#define LCD_PAL47_G04_0_Pos                                   5                                                         /*!< LCD PAL47: G04_0 Position           */
+#define LCD_PAL47_G04_0_Msk                                   (0x1fUL << LCD_PAL47_G04_0_Pos)                           /*!< LCD PAL47: G04_0 Mask               */
+#define LCD_PAL47_B04_0_Pos                                   10                                                        /*!< LCD PAL47: B04_0 Position           */
+#define LCD_PAL47_B04_0_Msk                                   (0x1fUL << LCD_PAL47_B04_0_Pos)                           /*!< LCD PAL47: B04_0 Mask               */
+#define LCD_PAL47_I0_Pos                                      15                                                        /*!< LCD PAL47: I0 Position              */
+#define LCD_PAL47_I0_Msk                                      (0x01UL << LCD_PAL47_I0_Pos)                              /*!< LCD PAL47: I0 Mask                  */
+#define LCD_PAL47_R14_0_Pos                                   16                                                        /*!< LCD PAL47: R14_0 Position           */
+#define LCD_PAL47_R14_0_Msk                                   (0x1fUL << LCD_PAL47_R14_0_Pos)                           /*!< LCD PAL47: R14_0 Mask               */
+#define LCD_PAL47_G14_0_Pos                                   21                                                        /*!< LCD PAL47: G14_0 Position           */
+#define LCD_PAL47_G14_0_Msk                                   (0x1fUL << LCD_PAL47_G14_0_Pos)                           /*!< LCD PAL47: G14_0 Mask               */
+#define LCD_PAL47_B14_0_Pos                                   26                                                        /*!< LCD PAL47: B14_0 Position           */
+#define LCD_PAL47_B14_0_Msk                                   (0x1fUL << LCD_PAL47_B14_0_Pos)                           /*!< LCD PAL47: B14_0 Mask               */
+#define LCD_PAL47_I1_Pos                                      31                                                        /*!< LCD PAL47: I1 Position              */
+#define LCD_PAL47_I1_Msk                                      (0x01UL << LCD_PAL47_I1_Pos)                              /*!< LCD PAL47: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL48  -------------------------------------------
+#define LCD_PAL48_R04_0_Pos                                   0                                                         /*!< LCD PAL48: R04_0 Position           */
+#define LCD_PAL48_R04_0_Msk                                   (0x1fUL << LCD_PAL48_R04_0_Pos)                           /*!< LCD PAL48: R04_0 Mask               */
+#define LCD_PAL48_G04_0_Pos                                   5                                                         /*!< LCD PAL48: G04_0 Position           */
+#define LCD_PAL48_G04_0_Msk                                   (0x1fUL << LCD_PAL48_G04_0_Pos)                           /*!< LCD PAL48: G04_0 Mask               */
+#define LCD_PAL48_B04_0_Pos                                   10                                                        /*!< LCD PAL48: B04_0 Position           */
+#define LCD_PAL48_B04_0_Msk                                   (0x1fUL << LCD_PAL48_B04_0_Pos)                           /*!< LCD PAL48: B04_0 Mask               */
+#define LCD_PAL48_I0_Pos                                      15                                                        /*!< LCD PAL48: I0 Position              */
+#define LCD_PAL48_I0_Msk                                      (0x01UL << LCD_PAL48_I0_Pos)                              /*!< LCD PAL48: I0 Mask                  */
+#define LCD_PAL48_R14_0_Pos                                   16                                                        /*!< LCD PAL48: R14_0 Position           */
+#define LCD_PAL48_R14_0_Msk                                   (0x1fUL << LCD_PAL48_R14_0_Pos)                           /*!< LCD PAL48: R14_0 Mask               */
+#define LCD_PAL48_G14_0_Pos                                   21                                                        /*!< LCD PAL48: G14_0 Position           */
+#define LCD_PAL48_G14_0_Msk                                   (0x1fUL << LCD_PAL48_G14_0_Pos)                           /*!< LCD PAL48: G14_0 Mask               */
+#define LCD_PAL48_B14_0_Pos                                   26                                                        /*!< LCD PAL48: B14_0 Position           */
+#define LCD_PAL48_B14_0_Msk                                   (0x1fUL << LCD_PAL48_B14_0_Pos)                           /*!< LCD PAL48: B14_0 Mask               */
+#define LCD_PAL48_I1_Pos                                      31                                                        /*!< LCD PAL48: I1 Position              */
+#define LCD_PAL48_I1_Msk                                      (0x01UL << LCD_PAL48_I1_Pos)                              /*!< LCD PAL48: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL49  -------------------------------------------
+#define LCD_PAL49_R04_0_Pos                                   0                                                         /*!< LCD PAL49: R04_0 Position           */
+#define LCD_PAL49_R04_0_Msk                                   (0x1fUL << LCD_PAL49_R04_0_Pos)                           /*!< LCD PAL49: R04_0 Mask               */
+#define LCD_PAL49_G04_0_Pos                                   5                                                         /*!< LCD PAL49: G04_0 Position           */
+#define LCD_PAL49_G04_0_Msk                                   (0x1fUL << LCD_PAL49_G04_0_Pos)                           /*!< LCD PAL49: G04_0 Mask               */
+#define LCD_PAL49_B04_0_Pos                                   10                                                        /*!< LCD PAL49: B04_0 Position           */
+#define LCD_PAL49_B04_0_Msk                                   (0x1fUL << LCD_PAL49_B04_0_Pos)                           /*!< LCD PAL49: B04_0 Mask               */
+#define LCD_PAL49_I0_Pos                                      15                                                        /*!< LCD PAL49: I0 Position              */
+#define LCD_PAL49_I0_Msk                                      (0x01UL << LCD_PAL49_I0_Pos)                              /*!< LCD PAL49: I0 Mask                  */
+#define LCD_PAL49_R14_0_Pos                                   16                                                        /*!< LCD PAL49: R14_0 Position           */
+#define LCD_PAL49_R14_0_Msk                                   (0x1fUL << LCD_PAL49_R14_0_Pos)                           /*!< LCD PAL49: R14_0 Mask               */
+#define LCD_PAL49_G14_0_Pos                                   21                                                        /*!< LCD PAL49: G14_0 Position           */
+#define LCD_PAL49_G14_0_Msk                                   (0x1fUL << LCD_PAL49_G14_0_Pos)                           /*!< LCD PAL49: G14_0 Mask               */
+#define LCD_PAL49_B14_0_Pos                                   26                                                        /*!< LCD PAL49: B14_0 Position           */
+#define LCD_PAL49_B14_0_Msk                                   (0x1fUL << LCD_PAL49_B14_0_Pos)                           /*!< LCD PAL49: B14_0 Mask               */
+#define LCD_PAL49_I1_Pos                                      31                                                        /*!< LCD PAL49: I1 Position              */
+#define LCD_PAL49_I1_Msk                                      (0x01UL << LCD_PAL49_I1_Pos)                              /*!< LCD PAL49: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL50  -------------------------------------------
+#define LCD_PAL50_R04_0_Pos                                   0                                                         /*!< LCD PAL50: R04_0 Position           */
+#define LCD_PAL50_R04_0_Msk                                   (0x1fUL << LCD_PAL50_R04_0_Pos)                           /*!< LCD PAL50: R04_0 Mask               */
+#define LCD_PAL50_G04_0_Pos                                   5                                                         /*!< LCD PAL50: G04_0 Position           */
+#define LCD_PAL50_G04_0_Msk                                   (0x1fUL << LCD_PAL50_G04_0_Pos)                           /*!< LCD PAL50: G04_0 Mask               */
+#define LCD_PAL50_B04_0_Pos                                   10                                                        /*!< LCD PAL50: B04_0 Position           */
+#define LCD_PAL50_B04_0_Msk                                   (0x1fUL << LCD_PAL50_B04_0_Pos)                           /*!< LCD PAL50: B04_0 Mask               */
+#define LCD_PAL50_I0_Pos                                      15                                                        /*!< LCD PAL50: I0 Position              */
+#define LCD_PAL50_I0_Msk                                      (0x01UL << LCD_PAL50_I0_Pos)                              /*!< LCD PAL50: I0 Mask                  */
+#define LCD_PAL50_R14_0_Pos                                   16                                                        /*!< LCD PAL50: R14_0 Position           */
+#define LCD_PAL50_R14_0_Msk                                   (0x1fUL << LCD_PAL50_R14_0_Pos)                           /*!< LCD PAL50: R14_0 Mask               */
+#define LCD_PAL50_G14_0_Pos                                   21                                                        /*!< LCD PAL50: G14_0 Position           */
+#define LCD_PAL50_G14_0_Msk                                   (0x1fUL << LCD_PAL50_G14_0_Pos)                           /*!< LCD PAL50: G14_0 Mask               */
+#define LCD_PAL50_B14_0_Pos                                   26                                                        /*!< LCD PAL50: B14_0 Position           */
+#define LCD_PAL50_B14_0_Msk                                   (0x1fUL << LCD_PAL50_B14_0_Pos)                           /*!< LCD PAL50: B14_0 Mask               */
+#define LCD_PAL50_I1_Pos                                      31                                                        /*!< LCD PAL50: I1 Position              */
+#define LCD_PAL50_I1_Msk                                      (0x01UL << LCD_PAL50_I1_Pos)                              /*!< LCD PAL50: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL51  -------------------------------------------
+#define LCD_PAL51_R04_0_Pos                                   0                                                         /*!< LCD PAL51: R04_0 Position           */
+#define LCD_PAL51_R04_0_Msk                                   (0x1fUL << LCD_PAL51_R04_0_Pos)                           /*!< LCD PAL51: R04_0 Mask               */
+#define LCD_PAL51_G04_0_Pos                                   5                                                         /*!< LCD PAL51: G04_0 Position           */
+#define LCD_PAL51_G04_0_Msk                                   (0x1fUL << LCD_PAL51_G04_0_Pos)                           /*!< LCD PAL51: G04_0 Mask               */
+#define LCD_PAL51_B04_0_Pos                                   10                                                        /*!< LCD PAL51: B04_0 Position           */
+#define LCD_PAL51_B04_0_Msk                                   (0x1fUL << LCD_PAL51_B04_0_Pos)                           /*!< LCD PAL51: B04_0 Mask               */
+#define LCD_PAL51_I0_Pos                                      15                                                        /*!< LCD PAL51: I0 Position              */
+#define LCD_PAL51_I0_Msk                                      (0x01UL << LCD_PAL51_I0_Pos)                              /*!< LCD PAL51: I0 Mask                  */
+#define LCD_PAL51_R14_0_Pos                                   16                                                        /*!< LCD PAL51: R14_0 Position           */
+#define LCD_PAL51_R14_0_Msk                                   (0x1fUL << LCD_PAL51_R14_0_Pos)                           /*!< LCD PAL51: R14_0 Mask               */
+#define LCD_PAL51_G14_0_Pos                                   21                                                        /*!< LCD PAL51: G14_0 Position           */
+#define LCD_PAL51_G14_0_Msk                                   (0x1fUL << LCD_PAL51_G14_0_Pos)                           /*!< LCD PAL51: G14_0 Mask               */
+#define LCD_PAL51_B14_0_Pos                                   26                                                        /*!< LCD PAL51: B14_0 Position           */
+#define LCD_PAL51_B14_0_Msk                                   (0x1fUL << LCD_PAL51_B14_0_Pos)                           /*!< LCD PAL51: B14_0 Mask               */
+#define LCD_PAL51_I1_Pos                                      31                                                        /*!< LCD PAL51: I1 Position              */
+#define LCD_PAL51_I1_Msk                                      (0x01UL << LCD_PAL51_I1_Pos)                              /*!< LCD PAL51: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL52  -------------------------------------------
+#define LCD_PAL52_R04_0_Pos                                   0                                                         /*!< LCD PAL52: R04_0 Position           */
+#define LCD_PAL52_R04_0_Msk                                   (0x1fUL << LCD_PAL52_R04_0_Pos)                           /*!< LCD PAL52: R04_0 Mask               */
+#define LCD_PAL52_G04_0_Pos                                   5                                                         /*!< LCD PAL52: G04_0 Position           */
+#define LCD_PAL52_G04_0_Msk                                   (0x1fUL << LCD_PAL52_G04_0_Pos)                           /*!< LCD PAL52: G04_0 Mask               */
+#define LCD_PAL52_B04_0_Pos                                   10                                                        /*!< LCD PAL52: B04_0 Position           */
+#define LCD_PAL52_B04_0_Msk                                   (0x1fUL << LCD_PAL52_B04_0_Pos)                           /*!< LCD PAL52: B04_0 Mask               */
+#define LCD_PAL52_I0_Pos                                      15                                                        /*!< LCD PAL52: I0 Position              */
+#define LCD_PAL52_I0_Msk                                      (0x01UL << LCD_PAL52_I0_Pos)                              /*!< LCD PAL52: I0 Mask                  */
+#define LCD_PAL52_R14_0_Pos                                   16                                                        /*!< LCD PAL52: R14_0 Position           */
+#define LCD_PAL52_R14_0_Msk                                   (0x1fUL << LCD_PAL52_R14_0_Pos)                           /*!< LCD PAL52: R14_0 Mask               */
+#define LCD_PAL52_G14_0_Pos                                   21                                                        /*!< LCD PAL52: G14_0 Position           */
+#define LCD_PAL52_G14_0_Msk                                   (0x1fUL << LCD_PAL52_G14_0_Pos)                           /*!< LCD PAL52: G14_0 Mask               */
+#define LCD_PAL52_B14_0_Pos                                   26                                                        /*!< LCD PAL52: B14_0 Position           */
+#define LCD_PAL52_B14_0_Msk                                   (0x1fUL << LCD_PAL52_B14_0_Pos)                           /*!< LCD PAL52: B14_0 Mask               */
+#define LCD_PAL52_I1_Pos                                      31                                                        /*!< LCD PAL52: I1 Position              */
+#define LCD_PAL52_I1_Msk                                      (0x01UL << LCD_PAL52_I1_Pos)                              /*!< LCD PAL52: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL53  -------------------------------------------
+#define LCD_PAL53_R04_0_Pos                                   0                                                         /*!< LCD PAL53: R04_0 Position           */
+#define LCD_PAL53_R04_0_Msk                                   (0x1fUL << LCD_PAL53_R04_0_Pos)                           /*!< LCD PAL53: R04_0 Mask               */
+#define LCD_PAL53_G04_0_Pos                                   5                                                         /*!< LCD PAL53: G04_0 Position           */
+#define LCD_PAL53_G04_0_Msk                                   (0x1fUL << LCD_PAL53_G04_0_Pos)                           /*!< LCD PAL53: G04_0 Mask               */
+#define LCD_PAL53_B04_0_Pos                                   10                                                        /*!< LCD PAL53: B04_0 Position           */
+#define LCD_PAL53_B04_0_Msk                                   (0x1fUL << LCD_PAL53_B04_0_Pos)                           /*!< LCD PAL53: B04_0 Mask               */
+#define LCD_PAL53_I0_Pos                                      15                                                        /*!< LCD PAL53: I0 Position              */
+#define LCD_PAL53_I0_Msk                                      (0x01UL << LCD_PAL53_I0_Pos)                              /*!< LCD PAL53: I0 Mask                  */
+#define LCD_PAL53_R14_0_Pos                                   16                                                        /*!< LCD PAL53: R14_0 Position           */
+#define LCD_PAL53_R14_0_Msk                                   (0x1fUL << LCD_PAL53_R14_0_Pos)                           /*!< LCD PAL53: R14_0 Mask               */
+#define LCD_PAL53_G14_0_Pos                                   21                                                        /*!< LCD PAL53: G14_0 Position           */
+#define LCD_PAL53_G14_0_Msk                                   (0x1fUL << LCD_PAL53_G14_0_Pos)                           /*!< LCD PAL53: G14_0 Mask               */
+#define LCD_PAL53_B14_0_Pos                                   26                                                        /*!< LCD PAL53: B14_0 Position           */
+#define LCD_PAL53_B14_0_Msk                                   (0x1fUL << LCD_PAL53_B14_0_Pos)                           /*!< LCD PAL53: B14_0 Mask               */
+#define LCD_PAL53_I1_Pos                                      31                                                        /*!< LCD PAL53: I1 Position              */
+#define LCD_PAL53_I1_Msk                                      (0x01UL << LCD_PAL53_I1_Pos)                              /*!< LCD PAL53: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL54  -------------------------------------------
+#define LCD_PAL54_R04_0_Pos                                   0                                                         /*!< LCD PAL54: R04_0 Position           */
+#define LCD_PAL54_R04_0_Msk                                   (0x1fUL << LCD_PAL54_R04_0_Pos)                           /*!< LCD PAL54: R04_0 Mask               */
+#define LCD_PAL54_G04_0_Pos                                   5                                                         /*!< LCD PAL54: G04_0 Position           */
+#define LCD_PAL54_G04_0_Msk                                   (0x1fUL << LCD_PAL54_G04_0_Pos)                           /*!< LCD PAL54: G04_0 Mask               */
+#define LCD_PAL54_B04_0_Pos                                   10                                                        /*!< LCD PAL54: B04_0 Position           */
+#define LCD_PAL54_B04_0_Msk                                   (0x1fUL << LCD_PAL54_B04_0_Pos)                           /*!< LCD PAL54: B04_0 Mask               */
+#define LCD_PAL54_I0_Pos                                      15                                                        /*!< LCD PAL54: I0 Position              */
+#define LCD_PAL54_I0_Msk                                      (0x01UL << LCD_PAL54_I0_Pos)                              /*!< LCD PAL54: I0 Mask                  */
+#define LCD_PAL54_R14_0_Pos                                   16                                                        /*!< LCD PAL54: R14_0 Position           */
+#define LCD_PAL54_R14_0_Msk                                   (0x1fUL << LCD_PAL54_R14_0_Pos)                           /*!< LCD PAL54: R14_0 Mask               */
+#define LCD_PAL54_G14_0_Pos                                   21                                                        /*!< LCD PAL54: G14_0 Position           */
+#define LCD_PAL54_G14_0_Msk                                   (0x1fUL << LCD_PAL54_G14_0_Pos)                           /*!< LCD PAL54: G14_0 Mask               */
+#define LCD_PAL54_B14_0_Pos                                   26                                                        /*!< LCD PAL54: B14_0 Position           */
+#define LCD_PAL54_B14_0_Msk                                   (0x1fUL << LCD_PAL54_B14_0_Pos)                           /*!< LCD PAL54: B14_0 Mask               */
+#define LCD_PAL54_I1_Pos                                      31                                                        /*!< LCD PAL54: I1 Position              */
+#define LCD_PAL54_I1_Msk                                      (0x01UL << LCD_PAL54_I1_Pos)                              /*!< LCD PAL54: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL55  -------------------------------------------
+#define LCD_PAL55_R04_0_Pos                                   0                                                         /*!< LCD PAL55: R04_0 Position           */
+#define LCD_PAL55_R04_0_Msk                                   (0x1fUL << LCD_PAL55_R04_0_Pos)                           /*!< LCD PAL55: R04_0 Mask               */
+#define LCD_PAL55_G04_0_Pos                                   5                                                         /*!< LCD PAL55: G04_0 Position           */
+#define LCD_PAL55_G04_0_Msk                                   (0x1fUL << LCD_PAL55_G04_0_Pos)                           /*!< LCD PAL55: G04_0 Mask               */
+#define LCD_PAL55_B04_0_Pos                                   10                                                        /*!< LCD PAL55: B04_0 Position           */
+#define LCD_PAL55_B04_0_Msk                                   (0x1fUL << LCD_PAL55_B04_0_Pos)                           /*!< LCD PAL55: B04_0 Mask               */
+#define LCD_PAL55_I0_Pos                                      15                                                        /*!< LCD PAL55: I0 Position              */
+#define LCD_PAL55_I0_Msk                                      (0x01UL << LCD_PAL55_I0_Pos)                              /*!< LCD PAL55: I0 Mask                  */
+#define LCD_PAL55_R14_0_Pos                                   16                                                        /*!< LCD PAL55: R14_0 Position           */
+#define LCD_PAL55_R14_0_Msk                                   (0x1fUL << LCD_PAL55_R14_0_Pos)                           /*!< LCD PAL55: R14_0 Mask               */
+#define LCD_PAL55_G14_0_Pos                                   21                                                        /*!< LCD PAL55: G14_0 Position           */
+#define LCD_PAL55_G14_0_Msk                                   (0x1fUL << LCD_PAL55_G14_0_Pos)                           /*!< LCD PAL55: G14_0 Mask               */
+#define LCD_PAL55_B14_0_Pos                                   26                                                        /*!< LCD PAL55: B14_0 Position           */
+#define LCD_PAL55_B14_0_Msk                                   (0x1fUL << LCD_PAL55_B14_0_Pos)                           /*!< LCD PAL55: B14_0 Mask               */
+#define LCD_PAL55_I1_Pos                                      31                                                        /*!< LCD PAL55: I1 Position              */
+#define LCD_PAL55_I1_Msk                                      (0x01UL << LCD_PAL55_I1_Pos)                              /*!< LCD PAL55: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL56  -------------------------------------------
+#define LCD_PAL56_R04_0_Pos                                   0                                                         /*!< LCD PAL56: R04_0 Position           */
+#define LCD_PAL56_R04_0_Msk                                   (0x1fUL << LCD_PAL56_R04_0_Pos)                           /*!< LCD PAL56: R04_0 Mask               */
+#define LCD_PAL56_G04_0_Pos                                   5                                                         /*!< LCD PAL56: G04_0 Position           */
+#define LCD_PAL56_G04_0_Msk                                   (0x1fUL << LCD_PAL56_G04_0_Pos)                           /*!< LCD PAL56: G04_0 Mask               */
+#define LCD_PAL56_B04_0_Pos                                   10                                                        /*!< LCD PAL56: B04_0 Position           */
+#define LCD_PAL56_B04_0_Msk                                   (0x1fUL << LCD_PAL56_B04_0_Pos)                           /*!< LCD PAL56: B04_0 Mask               */
+#define LCD_PAL56_I0_Pos                                      15                                                        /*!< LCD PAL56: I0 Position              */
+#define LCD_PAL56_I0_Msk                                      (0x01UL << LCD_PAL56_I0_Pos)                              /*!< LCD PAL56: I0 Mask                  */
+#define LCD_PAL56_R14_0_Pos                                   16                                                        /*!< LCD PAL56: R14_0 Position           */
+#define LCD_PAL56_R14_0_Msk                                   (0x1fUL << LCD_PAL56_R14_0_Pos)                           /*!< LCD PAL56: R14_0 Mask               */
+#define LCD_PAL56_G14_0_Pos                                   21                                                        /*!< LCD PAL56: G14_0 Position           */
+#define LCD_PAL56_G14_0_Msk                                   (0x1fUL << LCD_PAL56_G14_0_Pos)                           /*!< LCD PAL56: G14_0 Mask               */
+#define LCD_PAL56_B14_0_Pos                                   26                                                        /*!< LCD PAL56: B14_0 Position           */
+#define LCD_PAL56_B14_0_Msk                                   (0x1fUL << LCD_PAL56_B14_0_Pos)                           /*!< LCD PAL56: B14_0 Mask               */
+#define LCD_PAL56_I1_Pos                                      31                                                        /*!< LCD PAL56: I1 Position              */
+#define LCD_PAL56_I1_Msk                                      (0x01UL << LCD_PAL56_I1_Pos)                              /*!< LCD PAL56: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL57  -------------------------------------------
+#define LCD_PAL57_R04_0_Pos                                   0                                                         /*!< LCD PAL57: R04_0 Position           */
+#define LCD_PAL57_R04_0_Msk                                   (0x1fUL << LCD_PAL57_R04_0_Pos)                           /*!< LCD PAL57: R04_0 Mask               */
+#define LCD_PAL57_G04_0_Pos                                   5                                                         /*!< LCD PAL57: G04_0 Position           */
+#define LCD_PAL57_G04_0_Msk                                   (0x1fUL << LCD_PAL57_G04_0_Pos)                           /*!< LCD PAL57: G04_0 Mask               */
+#define LCD_PAL57_B04_0_Pos                                   10                                                        /*!< LCD PAL57: B04_0 Position           */
+#define LCD_PAL57_B04_0_Msk                                   (0x1fUL << LCD_PAL57_B04_0_Pos)                           /*!< LCD PAL57: B04_0 Mask               */
+#define LCD_PAL57_I0_Pos                                      15                                                        /*!< LCD PAL57: I0 Position              */
+#define LCD_PAL57_I0_Msk                                      (0x01UL << LCD_PAL57_I0_Pos)                              /*!< LCD PAL57: I0 Mask                  */
+#define LCD_PAL57_R14_0_Pos                                   16                                                        /*!< LCD PAL57: R14_0 Position           */
+#define LCD_PAL57_R14_0_Msk                                   (0x1fUL << LCD_PAL57_R14_0_Pos)                           /*!< LCD PAL57: R14_0 Mask               */
+#define LCD_PAL57_G14_0_Pos                                   21                                                        /*!< LCD PAL57: G14_0 Position           */
+#define LCD_PAL57_G14_0_Msk                                   (0x1fUL << LCD_PAL57_G14_0_Pos)                           /*!< LCD PAL57: G14_0 Mask               */
+#define LCD_PAL57_B14_0_Pos                                   26                                                        /*!< LCD PAL57: B14_0 Position           */
+#define LCD_PAL57_B14_0_Msk                                   (0x1fUL << LCD_PAL57_B14_0_Pos)                           /*!< LCD PAL57: B14_0 Mask               */
+#define LCD_PAL57_I1_Pos                                      31                                                        /*!< LCD PAL57: I1 Position              */
+#define LCD_PAL57_I1_Msk                                      (0x01UL << LCD_PAL57_I1_Pos)                              /*!< LCD PAL57: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL58  -------------------------------------------
+#define LCD_PAL58_R04_0_Pos                                   0                                                         /*!< LCD PAL58: R04_0 Position           */
+#define LCD_PAL58_R04_0_Msk                                   (0x1fUL << LCD_PAL58_R04_0_Pos)                           /*!< LCD PAL58: R04_0 Mask               */
+#define LCD_PAL58_G04_0_Pos                                   5                                                         /*!< LCD PAL58: G04_0 Position           */
+#define LCD_PAL58_G04_0_Msk                                   (0x1fUL << LCD_PAL58_G04_0_Pos)                           /*!< LCD PAL58: G04_0 Mask               */
+#define LCD_PAL58_B04_0_Pos                                   10                                                        /*!< LCD PAL58: B04_0 Position           */
+#define LCD_PAL58_B04_0_Msk                                   (0x1fUL << LCD_PAL58_B04_0_Pos)                           /*!< LCD PAL58: B04_0 Mask               */
+#define LCD_PAL58_I0_Pos                                      15                                                        /*!< LCD PAL58: I0 Position              */
+#define LCD_PAL58_I0_Msk                                      (0x01UL << LCD_PAL58_I0_Pos)                              /*!< LCD PAL58: I0 Mask                  */
+#define LCD_PAL58_R14_0_Pos                                   16                                                        /*!< LCD PAL58: R14_0 Position           */
+#define LCD_PAL58_R14_0_Msk                                   (0x1fUL << LCD_PAL58_R14_0_Pos)                           /*!< LCD PAL58: R14_0 Mask               */
+#define LCD_PAL58_G14_0_Pos                                   21                                                        /*!< LCD PAL58: G14_0 Position           */
+#define LCD_PAL58_G14_0_Msk                                   (0x1fUL << LCD_PAL58_G14_0_Pos)                           /*!< LCD PAL58: G14_0 Mask               */
+#define LCD_PAL58_B14_0_Pos                                   26                                                        /*!< LCD PAL58: B14_0 Position           */
+#define LCD_PAL58_B14_0_Msk                                   (0x1fUL << LCD_PAL58_B14_0_Pos)                           /*!< LCD PAL58: B14_0 Mask               */
+#define LCD_PAL58_I1_Pos                                      31                                                        /*!< LCD PAL58: I1 Position              */
+#define LCD_PAL58_I1_Msk                                      (0x01UL << LCD_PAL58_I1_Pos)                              /*!< LCD PAL58: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL59  -------------------------------------------
+#define LCD_PAL59_R04_0_Pos                                   0                                                         /*!< LCD PAL59: R04_0 Position           */
+#define LCD_PAL59_R04_0_Msk                                   (0x1fUL << LCD_PAL59_R04_0_Pos)                           /*!< LCD PAL59: R04_0 Mask               */
+#define LCD_PAL59_G04_0_Pos                                   5                                                         /*!< LCD PAL59: G04_0 Position           */
+#define LCD_PAL59_G04_0_Msk                                   (0x1fUL << LCD_PAL59_G04_0_Pos)                           /*!< LCD PAL59: G04_0 Mask               */
+#define LCD_PAL59_B04_0_Pos                                   10                                                        /*!< LCD PAL59: B04_0 Position           */
+#define LCD_PAL59_B04_0_Msk                                   (0x1fUL << LCD_PAL59_B04_0_Pos)                           /*!< LCD PAL59: B04_0 Mask               */
+#define LCD_PAL59_I0_Pos                                      15                                                        /*!< LCD PAL59: I0 Position              */
+#define LCD_PAL59_I0_Msk                                      (0x01UL << LCD_PAL59_I0_Pos)                              /*!< LCD PAL59: I0 Mask                  */
+#define LCD_PAL59_R14_0_Pos                                   16                                                        /*!< LCD PAL59: R14_0 Position           */
+#define LCD_PAL59_R14_0_Msk                                   (0x1fUL << LCD_PAL59_R14_0_Pos)                           /*!< LCD PAL59: R14_0 Mask               */
+#define LCD_PAL59_G14_0_Pos                                   21                                                        /*!< LCD PAL59: G14_0 Position           */
+#define LCD_PAL59_G14_0_Msk                                   (0x1fUL << LCD_PAL59_G14_0_Pos)                           /*!< LCD PAL59: G14_0 Mask               */
+#define LCD_PAL59_B14_0_Pos                                   26                                                        /*!< LCD PAL59: B14_0 Position           */
+#define LCD_PAL59_B14_0_Msk                                   (0x1fUL << LCD_PAL59_B14_0_Pos)                           /*!< LCD PAL59: B14_0 Mask               */
+#define LCD_PAL59_I1_Pos                                      31                                                        /*!< LCD PAL59: I1 Position              */
+#define LCD_PAL59_I1_Msk                                      (0x01UL << LCD_PAL59_I1_Pos)                              /*!< LCD PAL59: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL60  -------------------------------------------
+#define LCD_PAL60_R04_0_Pos                                   0                                                         /*!< LCD PAL60: R04_0 Position           */
+#define LCD_PAL60_R04_0_Msk                                   (0x1fUL << LCD_PAL60_R04_0_Pos)                           /*!< LCD PAL60: R04_0 Mask               */
+#define LCD_PAL60_G04_0_Pos                                   5                                                         /*!< LCD PAL60: G04_0 Position           */
+#define LCD_PAL60_G04_0_Msk                                   (0x1fUL << LCD_PAL60_G04_0_Pos)                           /*!< LCD PAL60: G04_0 Mask               */
+#define LCD_PAL60_B04_0_Pos                                   10                                                        /*!< LCD PAL60: B04_0 Position           */
+#define LCD_PAL60_B04_0_Msk                                   (0x1fUL << LCD_PAL60_B04_0_Pos)                           /*!< LCD PAL60: B04_0 Mask               */
+#define LCD_PAL60_I0_Pos                                      15                                                        /*!< LCD PAL60: I0 Position              */
+#define LCD_PAL60_I0_Msk                                      (0x01UL << LCD_PAL60_I0_Pos)                              /*!< LCD PAL60: I0 Mask                  */
+#define LCD_PAL60_R14_0_Pos                                   16                                                        /*!< LCD PAL60: R14_0 Position           */
+#define LCD_PAL60_R14_0_Msk                                   (0x1fUL << LCD_PAL60_R14_0_Pos)                           /*!< LCD PAL60: R14_0 Mask               */
+#define LCD_PAL60_G14_0_Pos                                   21                                                        /*!< LCD PAL60: G14_0 Position           */
+#define LCD_PAL60_G14_0_Msk                                   (0x1fUL << LCD_PAL60_G14_0_Pos)                           /*!< LCD PAL60: G14_0 Mask               */
+#define LCD_PAL60_B14_0_Pos                                   26                                                        /*!< LCD PAL60: B14_0 Position           */
+#define LCD_PAL60_B14_0_Msk                                   (0x1fUL << LCD_PAL60_B14_0_Pos)                           /*!< LCD PAL60: B14_0 Mask               */
+#define LCD_PAL60_I1_Pos                                      31                                                        /*!< LCD PAL60: I1 Position              */
+#define LCD_PAL60_I1_Msk                                      (0x01UL << LCD_PAL60_I1_Pos)                              /*!< LCD PAL60: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL61  -------------------------------------------
+#define LCD_PAL61_R04_0_Pos                                   0                                                         /*!< LCD PAL61: R04_0 Position           */
+#define LCD_PAL61_R04_0_Msk                                   (0x1fUL << LCD_PAL61_R04_0_Pos)                           /*!< LCD PAL61: R04_0 Mask               */
+#define LCD_PAL61_G04_0_Pos                                   5                                                         /*!< LCD PAL61: G04_0 Position           */
+#define LCD_PAL61_G04_0_Msk                                   (0x1fUL << LCD_PAL61_G04_0_Pos)                           /*!< LCD PAL61: G04_0 Mask               */
+#define LCD_PAL61_B04_0_Pos                                   10                                                        /*!< LCD PAL61: B04_0 Position           */
+#define LCD_PAL61_B04_0_Msk                                   (0x1fUL << LCD_PAL61_B04_0_Pos)                           /*!< LCD PAL61: B04_0 Mask               */
+#define LCD_PAL61_I0_Pos                                      15                                                        /*!< LCD PAL61: I0 Position              */
+#define LCD_PAL61_I0_Msk                                      (0x01UL << LCD_PAL61_I0_Pos)                              /*!< LCD PAL61: I0 Mask                  */
+#define LCD_PAL61_R14_0_Pos                                   16                                                        /*!< LCD PAL61: R14_0 Position           */
+#define LCD_PAL61_R14_0_Msk                                   (0x1fUL << LCD_PAL61_R14_0_Pos)                           /*!< LCD PAL61: R14_0 Mask               */
+#define LCD_PAL61_G14_0_Pos                                   21                                                        /*!< LCD PAL61: G14_0 Position           */
+#define LCD_PAL61_G14_0_Msk                                   (0x1fUL << LCD_PAL61_G14_0_Pos)                           /*!< LCD PAL61: G14_0 Mask               */
+#define LCD_PAL61_B14_0_Pos                                   26                                                        /*!< LCD PAL61: B14_0 Position           */
+#define LCD_PAL61_B14_0_Msk                                   (0x1fUL << LCD_PAL61_B14_0_Pos)                           /*!< LCD PAL61: B14_0 Mask               */
+#define LCD_PAL61_I1_Pos                                      31                                                        /*!< LCD PAL61: I1 Position              */
+#define LCD_PAL61_I1_Msk                                      (0x01UL << LCD_PAL61_I1_Pos)                              /*!< LCD PAL61: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL62  -------------------------------------------
+#define LCD_PAL62_R04_0_Pos                                   0                                                         /*!< LCD PAL62: R04_0 Position           */
+#define LCD_PAL62_R04_0_Msk                                   (0x1fUL << LCD_PAL62_R04_0_Pos)                           /*!< LCD PAL62: R04_0 Mask               */
+#define LCD_PAL62_G04_0_Pos                                   5                                                         /*!< LCD PAL62: G04_0 Position           */
+#define LCD_PAL62_G04_0_Msk                                   (0x1fUL << LCD_PAL62_G04_0_Pos)                           /*!< LCD PAL62: G04_0 Mask               */
+#define LCD_PAL62_B04_0_Pos                                   10                                                        /*!< LCD PAL62: B04_0 Position           */
+#define LCD_PAL62_B04_0_Msk                                   (0x1fUL << LCD_PAL62_B04_0_Pos)                           /*!< LCD PAL62: B04_0 Mask               */
+#define LCD_PAL62_I0_Pos                                      15                                                        /*!< LCD PAL62: I0 Position              */
+#define LCD_PAL62_I0_Msk                                      (0x01UL << LCD_PAL62_I0_Pos)                              /*!< LCD PAL62: I0 Mask                  */
+#define LCD_PAL62_R14_0_Pos                                   16                                                        /*!< LCD PAL62: R14_0 Position           */
+#define LCD_PAL62_R14_0_Msk                                   (0x1fUL << LCD_PAL62_R14_0_Pos)                           /*!< LCD PAL62: R14_0 Mask               */
+#define LCD_PAL62_G14_0_Pos                                   21                                                        /*!< LCD PAL62: G14_0 Position           */
+#define LCD_PAL62_G14_0_Msk                                   (0x1fUL << LCD_PAL62_G14_0_Pos)                           /*!< LCD PAL62: G14_0 Mask               */
+#define LCD_PAL62_B14_0_Pos                                   26                                                        /*!< LCD PAL62: B14_0 Position           */
+#define LCD_PAL62_B14_0_Msk                                   (0x1fUL << LCD_PAL62_B14_0_Pos)                           /*!< LCD PAL62: B14_0 Mask               */
+#define LCD_PAL62_I1_Pos                                      31                                                        /*!< LCD PAL62: I1 Position              */
+#define LCD_PAL62_I1_Msk                                      (0x01UL << LCD_PAL62_I1_Pos)                              /*!< LCD PAL62: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL63  -------------------------------------------
+#define LCD_PAL63_R04_0_Pos                                   0                                                         /*!< LCD PAL63: R04_0 Position           */
+#define LCD_PAL63_R04_0_Msk                                   (0x1fUL << LCD_PAL63_R04_0_Pos)                           /*!< LCD PAL63: R04_0 Mask               */
+#define LCD_PAL63_G04_0_Pos                                   5                                                         /*!< LCD PAL63: G04_0 Position           */
+#define LCD_PAL63_G04_0_Msk                                   (0x1fUL << LCD_PAL63_G04_0_Pos)                           /*!< LCD PAL63: G04_0 Mask               */
+#define LCD_PAL63_B04_0_Pos                                   10                                                        /*!< LCD PAL63: B04_0 Position           */
+#define LCD_PAL63_B04_0_Msk                                   (0x1fUL << LCD_PAL63_B04_0_Pos)                           /*!< LCD PAL63: B04_0 Mask               */
+#define LCD_PAL63_I0_Pos                                      15                                                        /*!< LCD PAL63: I0 Position              */
+#define LCD_PAL63_I0_Msk                                      (0x01UL << LCD_PAL63_I0_Pos)                              /*!< LCD PAL63: I0 Mask                  */
+#define LCD_PAL63_R14_0_Pos                                   16                                                        /*!< LCD PAL63: R14_0 Position           */
+#define LCD_PAL63_R14_0_Msk                                   (0x1fUL << LCD_PAL63_R14_0_Pos)                           /*!< LCD PAL63: R14_0 Mask               */
+#define LCD_PAL63_G14_0_Pos                                   21                                                        /*!< LCD PAL63: G14_0 Position           */
+#define LCD_PAL63_G14_0_Msk                                   (0x1fUL << LCD_PAL63_G14_0_Pos)                           /*!< LCD PAL63: G14_0 Mask               */
+#define LCD_PAL63_B14_0_Pos                                   26                                                        /*!< LCD PAL63: B14_0 Position           */
+#define LCD_PAL63_B14_0_Msk                                   (0x1fUL << LCD_PAL63_B14_0_Pos)                           /*!< LCD PAL63: B14_0 Mask               */
+#define LCD_PAL63_I1_Pos                                      31                                                        /*!< LCD PAL63: I1 Position              */
+#define LCD_PAL63_I1_Msk                                      (0x01UL << LCD_PAL63_I1_Pos)                              /*!< LCD PAL63: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL64  -------------------------------------------
+#define LCD_PAL64_R04_0_Pos                                   0                                                         /*!< LCD PAL64: R04_0 Position           */
+#define LCD_PAL64_R04_0_Msk                                   (0x1fUL << LCD_PAL64_R04_0_Pos)                           /*!< LCD PAL64: R04_0 Mask               */
+#define LCD_PAL64_G04_0_Pos                                   5                                                         /*!< LCD PAL64: G04_0 Position           */
+#define LCD_PAL64_G04_0_Msk                                   (0x1fUL << LCD_PAL64_G04_0_Pos)                           /*!< LCD PAL64: G04_0 Mask               */
+#define LCD_PAL64_B04_0_Pos                                   10                                                        /*!< LCD PAL64: B04_0 Position           */
+#define LCD_PAL64_B04_0_Msk                                   (0x1fUL << LCD_PAL64_B04_0_Pos)                           /*!< LCD PAL64: B04_0 Mask               */
+#define LCD_PAL64_I0_Pos                                      15                                                        /*!< LCD PAL64: I0 Position              */
+#define LCD_PAL64_I0_Msk                                      (0x01UL << LCD_PAL64_I0_Pos)                              /*!< LCD PAL64: I0 Mask                  */
+#define LCD_PAL64_R14_0_Pos                                   16                                                        /*!< LCD PAL64: R14_0 Position           */
+#define LCD_PAL64_R14_0_Msk                                   (0x1fUL << LCD_PAL64_R14_0_Pos)                           /*!< LCD PAL64: R14_0 Mask               */
+#define LCD_PAL64_G14_0_Pos                                   21                                                        /*!< LCD PAL64: G14_0 Position           */
+#define LCD_PAL64_G14_0_Msk                                   (0x1fUL << LCD_PAL64_G14_0_Pos)                           /*!< LCD PAL64: G14_0 Mask               */
+#define LCD_PAL64_B14_0_Pos                                   26                                                        /*!< LCD PAL64: B14_0 Position           */
+#define LCD_PAL64_B14_0_Msk                                   (0x1fUL << LCD_PAL64_B14_0_Pos)                           /*!< LCD PAL64: B14_0 Mask               */
+#define LCD_PAL64_I1_Pos                                      31                                                        /*!< LCD PAL64: I1 Position              */
+#define LCD_PAL64_I1_Msk                                      (0x01UL << LCD_PAL64_I1_Pos)                              /*!< LCD PAL64: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL65  -------------------------------------------
+#define LCD_PAL65_R04_0_Pos                                   0                                                         /*!< LCD PAL65: R04_0 Position           */
+#define LCD_PAL65_R04_0_Msk                                   (0x1fUL << LCD_PAL65_R04_0_Pos)                           /*!< LCD PAL65: R04_0 Mask               */
+#define LCD_PAL65_G04_0_Pos                                   5                                                         /*!< LCD PAL65: G04_0 Position           */
+#define LCD_PAL65_G04_0_Msk                                   (0x1fUL << LCD_PAL65_G04_0_Pos)                           /*!< LCD PAL65: G04_0 Mask               */
+#define LCD_PAL65_B04_0_Pos                                   10                                                        /*!< LCD PAL65: B04_0 Position           */
+#define LCD_PAL65_B04_0_Msk                                   (0x1fUL << LCD_PAL65_B04_0_Pos)                           /*!< LCD PAL65: B04_0 Mask               */
+#define LCD_PAL65_I0_Pos                                      15                                                        /*!< LCD PAL65: I0 Position              */
+#define LCD_PAL65_I0_Msk                                      (0x01UL << LCD_PAL65_I0_Pos)                              /*!< LCD PAL65: I0 Mask                  */
+#define LCD_PAL65_R14_0_Pos                                   16                                                        /*!< LCD PAL65: R14_0 Position           */
+#define LCD_PAL65_R14_0_Msk                                   (0x1fUL << LCD_PAL65_R14_0_Pos)                           /*!< LCD PAL65: R14_0 Mask               */
+#define LCD_PAL65_G14_0_Pos                                   21                                                        /*!< LCD PAL65: G14_0 Position           */
+#define LCD_PAL65_G14_0_Msk                                   (0x1fUL << LCD_PAL65_G14_0_Pos)                           /*!< LCD PAL65: G14_0 Mask               */
+#define LCD_PAL65_B14_0_Pos                                   26                                                        /*!< LCD PAL65: B14_0 Position           */
+#define LCD_PAL65_B14_0_Msk                                   (0x1fUL << LCD_PAL65_B14_0_Pos)                           /*!< LCD PAL65: B14_0 Mask               */
+#define LCD_PAL65_I1_Pos                                      31                                                        /*!< LCD PAL65: I1 Position              */
+#define LCD_PAL65_I1_Msk                                      (0x01UL << LCD_PAL65_I1_Pos)                              /*!< LCD PAL65: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL66  -------------------------------------------
+#define LCD_PAL66_R04_0_Pos                                   0                                                         /*!< LCD PAL66: R04_0 Position           */
+#define LCD_PAL66_R04_0_Msk                                   (0x1fUL << LCD_PAL66_R04_0_Pos)                           /*!< LCD PAL66: R04_0 Mask               */
+#define LCD_PAL66_G04_0_Pos                                   5                                                         /*!< LCD PAL66: G04_0 Position           */
+#define LCD_PAL66_G04_0_Msk                                   (0x1fUL << LCD_PAL66_G04_0_Pos)                           /*!< LCD PAL66: G04_0 Mask               */
+#define LCD_PAL66_B04_0_Pos                                   10                                                        /*!< LCD PAL66: B04_0 Position           */
+#define LCD_PAL66_B04_0_Msk                                   (0x1fUL << LCD_PAL66_B04_0_Pos)                           /*!< LCD PAL66: B04_0 Mask               */
+#define LCD_PAL66_I0_Pos                                      15                                                        /*!< LCD PAL66: I0 Position              */
+#define LCD_PAL66_I0_Msk                                      (0x01UL << LCD_PAL66_I0_Pos)                              /*!< LCD PAL66: I0 Mask                  */
+#define LCD_PAL66_R14_0_Pos                                   16                                                        /*!< LCD PAL66: R14_0 Position           */
+#define LCD_PAL66_R14_0_Msk                                   (0x1fUL << LCD_PAL66_R14_0_Pos)                           /*!< LCD PAL66: R14_0 Mask               */
+#define LCD_PAL66_G14_0_Pos                                   21                                                        /*!< LCD PAL66: G14_0 Position           */
+#define LCD_PAL66_G14_0_Msk                                   (0x1fUL << LCD_PAL66_G14_0_Pos)                           /*!< LCD PAL66: G14_0 Mask               */
+#define LCD_PAL66_B14_0_Pos                                   26                                                        /*!< LCD PAL66: B14_0 Position           */
+#define LCD_PAL66_B14_0_Msk                                   (0x1fUL << LCD_PAL66_B14_0_Pos)                           /*!< LCD PAL66: B14_0 Mask               */
+#define LCD_PAL66_I1_Pos                                      31                                                        /*!< LCD PAL66: I1 Position              */
+#define LCD_PAL66_I1_Msk                                      (0x01UL << LCD_PAL66_I1_Pos)                              /*!< LCD PAL66: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL67  -------------------------------------------
+#define LCD_PAL67_R04_0_Pos                                   0                                                         /*!< LCD PAL67: R04_0 Position           */
+#define LCD_PAL67_R04_0_Msk                                   (0x1fUL << LCD_PAL67_R04_0_Pos)                           /*!< LCD PAL67: R04_0 Mask               */
+#define LCD_PAL67_G04_0_Pos                                   5                                                         /*!< LCD PAL67: G04_0 Position           */
+#define LCD_PAL67_G04_0_Msk                                   (0x1fUL << LCD_PAL67_G04_0_Pos)                           /*!< LCD PAL67: G04_0 Mask               */
+#define LCD_PAL67_B04_0_Pos                                   10                                                        /*!< LCD PAL67: B04_0 Position           */
+#define LCD_PAL67_B04_0_Msk                                   (0x1fUL << LCD_PAL67_B04_0_Pos)                           /*!< LCD PAL67: B04_0 Mask               */
+#define LCD_PAL67_I0_Pos                                      15                                                        /*!< LCD PAL67: I0 Position              */
+#define LCD_PAL67_I0_Msk                                      (0x01UL << LCD_PAL67_I0_Pos)                              /*!< LCD PAL67: I0 Mask                  */
+#define LCD_PAL67_R14_0_Pos                                   16                                                        /*!< LCD PAL67: R14_0 Position           */
+#define LCD_PAL67_R14_0_Msk                                   (0x1fUL << LCD_PAL67_R14_0_Pos)                           /*!< LCD PAL67: R14_0 Mask               */
+#define LCD_PAL67_G14_0_Pos                                   21                                                        /*!< LCD PAL67: G14_0 Position           */
+#define LCD_PAL67_G14_0_Msk                                   (0x1fUL << LCD_PAL67_G14_0_Pos)                           /*!< LCD PAL67: G14_0 Mask               */
+#define LCD_PAL67_B14_0_Pos                                   26                                                        /*!< LCD PAL67: B14_0 Position           */
+#define LCD_PAL67_B14_0_Msk                                   (0x1fUL << LCD_PAL67_B14_0_Pos)                           /*!< LCD PAL67: B14_0 Mask               */
+#define LCD_PAL67_I1_Pos                                      31                                                        /*!< LCD PAL67: I1 Position              */
+#define LCD_PAL67_I1_Msk                                      (0x01UL << LCD_PAL67_I1_Pos)                              /*!< LCD PAL67: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL68  -------------------------------------------
+#define LCD_PAL68_R04_0_Pos                                   0                                                         /*!< LCD PAL68: R04_0 Position           */
+#define LCD_PAL68_R04_0_Msk                                   (0x1fUL << LCD_PAL68_R04_0_Pos)                           /*!< LCD PAL68: R04_0 Mask               */
+#define LCD_PAL68_G04_0_Pos                                   5                                                         /*!< LCD PAL68: G04_0 Position           */
+#define LCD_PAL68_G04_0_Msk                                   (0x1fUL << LCD_PAL68_G04_0_Pos)                           /*!< LCD PAL68: G04_0 Mask               */
+#define LCD_PAL68_B04_0_Pos                                   10                                                        /*!< LCD PAL68: B04_0 Position           */
+#define LCD_PAL68_B04_0_Msk                                   (0x1fUL << LCD_PAL68_B04_0_Pos)                           /*!< LCD PAL68: B04_0 Mask               */
+#define LCD_PAL68_I0_Pos                                      15                                                        /*!< LCD PAL68: I0 Position              */
+#define LCD_PAL68_I0_Msk                                      (0x01UL << LCD_PAL68_I0_Pos)                              /*!< LCD PAL68: I0 Mask                  */
+#define LCD_PAL68_R14_0_Pos                                   16                                                        /*!< LCD PAL68: R14_0 Position           */
+#define LCD_PAL68_R14_0_Msk                                   (0x1fUL << LCD_PAL68_R14_0_Pos)                           /*!< LCD PAL68: R14_0 Mask               */
+#define LCD_PAL68_G14_0_Pos                                   21                                                        /*!< LCD PAL68: G14_0 Position           */
+#define LCD_PAL68_G14_0_Msk                                   (0x1fUL << LCD_PAL68_G14_0_Pos)                           /*!< LCD PAL68: G14_0 Mask               */
+#define LCD_PAL68_B14_0_Pos                                   26                                                        /*!< LCD PAL68: B14_0 Position           */
+#define LCD_PAL68_B14_0_Msk                                   (0x1fUL << LCD_PAL68_B14_0_Pos)                           /*!< LCD PAL68: B14_0 Mask               */
+#define LCD_PAL68_I1_Pos                                      31                                                        /*!< LCD PAL68: I1 Position              */
+#define LCD_PAL68_I1_Msk                                      (0x01UL << LCD_PAL68_I1_Pos)                              /*!< LCD PAL68: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL69  -------------------------------------------
+#define LCD_PAL69_R04_0_Pos                                   0                                                         /*!< LCD PAL69: R04_0 Position           */
+#define LCD_PAL69_R04_0_Msk                                   (0x1fUL << LCD_PAL69_R04_0_Pos)                           /*!< LCD PAL69: R04_0 Mask               */
+#define LCD_PAL69_G04_0_Pos                                   5                                                         /*!< LCD PAL69: G04_0 Position           */
+#define LCD_PAL69_G04_0_Msk                                   (0x1fUL << LCD_PAL69_G04_0_Pos)                           /*!< LCD PAL69: G04_0 Mask               */
+#define LCD_PAL69_B04_0_Pos                                   10                                                        /*!< LCD PAL69: B04_0 Position           */
+#define LCD_PAL69_B04_0_Msk                                   (0x1fUL << LCD_PAL69_B04_0_Pos)                           /*!< LCD PAL69: B04_0 Mask               */
+#define LCD_PAL69_I0_Pos                                      15                                                        /*!< LCD PAL69: I0 Position              */
+#define LCD_PAL69_I0_Msk                                      (0x01UL << LCD_PAL69_I0_Pos)                              /*!< LCD PAL69: I0 Mask                  */
+#define LCD_PAL69_R14_0_Pos                                   16                                                        /*!< LCD PAL69: R14_0 Position           */
+#define LCD_PAL69_R14_0_Msk                                   (0x1fUL << LCD_PAL69_R14_0_Pos)                           /*!< LCD PAL69: R14_0 Mask               */
+#define LCD_PAL69_G14_0_Pos                                   21                                                        /*!< LCD PAL69: G14_0 Position           */
+#define LCD_PAL69_G14_0_Msk                                   (0x1fUL << LCD_PAL69_G14_0_Pos)                           /*!< LCD PAL69: G14_0 Mask               */
+#define LCD_PAL69_B14_0_Pos                                   26                                                        /*!< LCD PAL69: B14_0 Position           */
+#define LCD_PAL69_B14_0_Msk                                   (0x1fUL << LCD_PAL69_B14_0_Pos)                           /*!< LCD PAL69: B14_0 Mask               */
+#define LCD_PAL69_I1_Pos                                      31                                                        /*!< LCD PAL69: I1 Position              */
+#define LCD_PAL69_I1_Msk                                      (0x01UL << LCD_PAL69_I1_Pos)                              /*!< LCD PAL69: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL70  -------------------------------------------
+#define LCD_PAL70_R04_0_Pos                                   0                                                         /*!< LCD PAL70: R04_0 Position           */
+#define LCD_PAL70_R04_0_Msk                                   (0x1fUL << LCD_PAL70_R04_0_Pos)                           /*!< LCD PAL70: R04_0 Mask               */
+#define LCD_PAL70_G04_0_Pos                                   5                                                         /*!< LCD PAL70: G04_0 Position           */
+#define LCD_PAL70_G04_0_Msk                                   (0x1fUL << LCD_PAL70_G04_0_Pos)                           /*!< LCD PAL70: G04_0 Mask               */
+#define LCD_PAL70_B04_0_Pos                                   10                                                        /*!< LCD PAL70: B04_0 Position           */
+#define LCD_PAL70_B04_0_Msk                                   (0x1fUL << LCD_PAL70_B04_0_Pos)                           /*!< LCD PAL70: B04_0 Mask               */
+#define LCD_PAL70_I0_Pos                                      15                                                        /*!< LCD PAL70: I0 Position              */
+#define LCD_PAL70_I0_Msk                                      (0x01UL << LCD_PAL70_I0_Pos)                              /*!< LCD PAL70: I0 Mask                  */
+#define LCD_PAL70_R14_0_Pos                                   16                                                        /*!< LCD PAL70: R14_0 Position           */
+#define LCD_PAL70_R14_0_Msk                                   (0x1fUL << LCD_PAL70_R14_0_Pos)                           /*!< LCD PAL70: R14_0 Mask               */
+#define LCD_PAL70_G14_0_Pos                                   21                                                        /*!< LCD PAL70: G14_0 Position           */
+#define LCD_PAL70_G14_0_Msk                                   (0x1fUL << LCD_PAL70_G14_0_Pos)                           /*!< LCD PAL70: G14_0 Mask               */
+#define LCD_PAL70_B14_0_Pos                                   26                                                        /*!< LCD PAL70: B14_0 Position           */
+#define LCD_PAL70_B14_0_Msk                                   (0x1fUL << LCD_PAL70_B14_0_Pos)                           /*!< LCD PAL70: B14_0 Mask               */
+#define LCD_PAL70_I1_Pos                                      31                                                        /*!< LCD PAL70: I1 Position              */
+#define LCD_PAL70_I1_Msk                                      (0x01UL << LCD_PAL70_I1_Pos)                              /*!< LCD PAL70: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL71  -------------------------------------------
+#define LCD_PAL71_R04_0_Pos                                   0                                                         /*!< LCD PAL71: R04_0 Position           */
+#define LCD_PAL71_R04_0_Msk                                   (0x1fUL << LCD_PAL71_R04_0_Pos)                           /*!< LCD PAL71: R04_0 Mask               */
+#define LCD_PAL71_G04_0_Pos                                   5                                                         /*!< LCD PAL71: G04_0 Position           */
+#define LCD_PAL71_G04_0_Msk                                   (0x1fUL << LCD_PAL71_G04_0_Pos)                           /*!< LCD PAL71: G04_0 Mask               */
+#define LCD_PAL71_B04_0_Pos                                   10                                                        /*!< LCD PAL71: B04_0 Position           */
+#define LCD_PAL71_B04_0_Msk                                   (0x1fUL << LCD_PAL71_B04_0_Pos)                           /*!< LCD PAL71: B04_0 Mask               */
+#define LCD_PAL71_I0_Pos                                      15                                                        /*!< LCD PAL71: I0 Position              */
+#define LCD_PAL71_I0_Msk                                      (0x01UL << LCD_PAL71_I0_Pos)                              /*!< LCD PAL71: I0 Mask                  */
+#define LCD_PAL71_R14_0_Pos                                   16                                                        /*!< LCD PAL71: R14_0 Position           */
+#define LCD_PAL71_R14_0_Msk                                   (0x1fUL << LCD_PAL71_R14_0_Pos)                           /*!< LCD PAL71: R14_0 Mask               */
+#define LCD_PAL71_G14_0_Pos                                   21                                                        /*!< LCD PAL71: G14_0 Position           */
+#define LCD_PAL71_G14_0_Msk                                   (0x1fUL << LCD_PAL71_G14_0_Pos)                           /*!< LCD PAL71: G14_0 Mask               */
+#define LCD_PAL71_B14_0_Pos                                   26                                                        /*!< LCD PAL71: B14_0 Position           */
+#define LCD_PAL71_B14_0_Msk                                   (0x1fUL << LCD_PAL71_B14_0_Pos)                           /*!< LCD PAL71: B14_0 Mask               */
+#define LCD_PAL71_I1_Pos                                      31                                                        /*!< LCD PAL71: I1 Position              */
+#define LCD_PAL71_I1_Msk                                      (0x01UL << LCD_PAL71_I1_Pos)                              /*!< LCD PAL71: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL72  -------------------------------------------
+#define LCD_PAL72_R04_0_Pos                                   0                                                         /*!< LCD PAL72: R04_0 Position           */
+#define LCD_PAL72_R04_0_Msk                                   (0x1fUL << LCD_PAL72_R04_0_Pos)                           /*!< LCD PAL72: R04_0 Mask               */
+#define LCD_PAL72_G04_0_Pos                                   5                                                         /*!< LCD PAL72: G04_0 Position           */
+#define LCD_PAL72_G04_0_Msk                                   (0x1fUL << LCD_PAL72_G04_0_Pos)                           /*!< LCD PAL72: G04_0 Mask               */
+#define LCD_PAL72_B04_0_Pos                                   10                                                        /*!< LCD PAL72: B04_0 Position           */
+#define LCD_PAL72_B04_0_Msk                                   (0x1fUL << LCD_PAL72_B04_0_Pos)                           /*!< LCD PAL72: B04_0 Mask               */
+#define LCD_PAL72_I0_Pos                                      15                                                        /*!< LCD PAL72: I0 Position              */
+#define LCD_PAL72_I0_Msk                                      (0x01UL << LCD_PAL72_I0_Pos)                              /*!< LCD PAL72: I0 Mask                  */
+#define LCD_PAL72_R14_0_Pos                                   16                                                        /*!< LCD PAL72: R14_0 Position           */
+#define LCD_PAL72_R14_0_Msk                                   (0x1fUL << LCD_PAL72_R14_0_Pos)                           /*!< LCD PAL72: R14_0 Mask               */
+#define LCD_PAL72_G14_0_Pos                                   21                                                        /*!< LCD PAL72: G14_0 Position           */
+#define LCD_PAL72_G14_0_Msk                                   (0x1fUL << LCD_PAL72_G14_0_Pos)                           /*!< LCD PAL72: G14_0 Mask               */
+#define LCD_PAL72_B14_0_Pos                                   26                                                        /*!< LCD PAL72: B14_0 Position           */
+#define LCD_PAL72_B14_0_Msk                                   (0x1fUL << LCD_PAL72_B14_0_Pos)                           /*!< LCD PAL72: B14_0 Mask               */
+#define LCD_PAL72_I1_Pos                                      31                                                        /*!< LCD PAL72: I1 Position              */
+#define LCD_PAL72_I1_Msk                                      (0x01UL << LCD_PAL72_I1_Pos)                              /*!< LCD PAL72: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL73  -------------------------------------------
+#define LCD_PAL73_R04_0_Pos                                   0                                                         /*!< LCD PAL73: R04_0 Position           */
+#define LCD_PAL73_R04_0_Msk                                   (0x1fUL << LCD_PAL73_R04_0_Pos)                           /*!< LCD PAL73: R04_0 Mask               */
+#define LCD_PAL73_G04_0_Pos                                   5                                                         /*!< LCD PAL73: G04_0 Position           */
+#define LCD_PAL73_G04_0_Msk                                   (0x1fUL << LCD_PAL73_G04_0_Pos)                           /*!< LCD PAL73: G04_0 Mask               */
+#define LCD_PAL73_B04_0_Pos                                   10                                                        /*!< LCD PAL73: B04_0 Position           */
+#define LCD_PAL73_B04_0_Msk                                   (0x1fUL << LCD_PAL73_B04_0_Pos)                           /*!< LCD PAL73: B04_0 Mask               */
+#define LCD_PAL73_I0_Pos                                      15                                                        /*!< LCD PAL73: I0 Position              */
+#define LCD_PAL73_I0_Msk                                      (0x01UL << LCD_PAL73_I0_Pos)                              /*!< LCD PAL73: I0 Mask                  */
+#define LCD_PAL73_R14_0_Pos                                   16                                                        /*!< LCD PAL73: R14_0 Position           */
+#define LCD_PAL73_R14_0_Msk                                   (0x1fUL << LCD_PAL73_R14_0_Pos)                           /*!< LCD PAL73: R14_0 Mask               */
+#define LCD_PAL73_G14_0_Pos                                   21                                                        /*!< LCD PAL73: G14_0 Position           */
+#define LCD_PAL73_G14_0_Msk                                   (0x1fUL << LCD_PAL73_G14_0_Pos)                           /*!< LCD PAL73: G14_0 Mask               */
+#define LCD_PAL73_B14_0_Pos                                   26                                                        /*!< LCD PAL73: B14_0 Position           */
+#define LCD_PAL73_B14_0_Msk                                   (0x1fUL << LCD_PAL73_B14_0_Pos)                           /*!< LCD PAL73: B14_0 Mask               */
+#define LCD_PAL73_I1_Pos                                      31                                                        /*!< LCD PAL73: I1 Position              */
+#define LCD_PAL73_I1_Msk                                      (0x01UL << LCD_PAL73_I1_Pos)                              /*!< LCD PAL73: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL74  -------------------------------------------
+#define LCD_PAL74_R04_0_Pos                                   0                                                         /*!< LCD PAL74: R04_0 Position           */
+#define LCD_PAL74_R04_0_Msk                                   (0x1fUL << LCD_PAL74_R04_0_Pos)                           /*!< LCD PAL74: R04_0 Mask               */
+#define LCD_PAL74_G04_0_Pos                                   5                                                         /*!< LCD PAL74: G04_0 Position           */
+#define LCD_PAL74_G04_0_Msk                                   (0x1fUL << LCD_PAL74_G04_0_Pos)                           /*!< LCD PAL74: G04_0 Mask               */
+#define LCD_PAL74_B04_0_Pos                                   10                                                        /*!< LCD PAL74: B04_0 Position           */
+#define LCD_PAL74_B04_0_Msk                                   (0x1fUL << LCD_PAL74_B04_0_Pos)                           /*!< LCD PAL74: B04_0 Mask               */
+#define LCD_PAL74_I0_Pos                                      15                                                        /*!< LCD PAL74: I0 Position              */
+#define LCD_PAL74_I0_Msk                                      (0x01UL << LCD_PAL74_I0_Pos)                              /*!< LCD PAL74: I0 Mask                  */
+#define LCD_PAL74_R14_0_Pos                                   16                                                        /*!< LCD PAL74: R14_0 Position           */
+#define LCD_PAL74_R14_0_Msk                                   (0x1fUL << LCD_PAL74_R14_0_Pos)                           /*!< LCD PAL74: R14_0 Mask               */
+#define LCD_PAL74_G14_0_Pos                                   21                                                        /*!< LCD PAL74: G14_0 Position           */
+#define LCD_PAL74_G14_0_Msk                                   (0x1fUL << LCD_PAL74_G14_0_Pos)                           /*!< LCD PAL74: G14_0 Mask               */
+#define LCD_PAL74_B14_0_Pos                                   26                                                        /*!< LCD PAL74: B14_0 Position           */
+#define LCD_PAL74_B14_0_Msk                                   (0x1fUL << LCD_PAL74_B14_0_Pos)                           /*!< LCD PAL74: B14_0 Mask               */
+#define LCD_PAL74_I1_Pos                                      31                                                        /*!< LCD PAL74: I1 Position              */
+#define LCD_PAL74_I1_Msk                                      (0x01UL << LCD_PAL74_I1_Pos)                              /*!< LCD PAL74: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL75  -------------------------------------------
+#define LCD_PAL75_R04_0_Pos                                   0                                                         /*!< LCD PAL75: R04_0 Position           */
+#define LCD_PAL75_R04_0_Msk                                   (0x1fUL << LCD_PAL75_R04_0_Pos)                           /*!< LCD PAL75: R04_0 Mask               */
+#define LCD_PAL75_G04_0_Pos                                   5                                                         /*!< LCD PAL75: G04_0 Position           */
+#define LCD_PAL75_G04_0_Msk                                   (0x1fUL << LCD_PAL75_G04_0_Pos)                           /*!< LCD PAL75: G04_0 Mask               */
+#define LCD_PAL75_B04_0_Pos                                   10                                                        /*!< LCD PAL75: B04_0 Position           */
+#define LCD_PAL75_B04_0_Msk                                   (0x1fUL << LCD_PAL75_B04_0_Pos)                           /*!< LCD PAL75: B04_0 Mask               */
+#define LCD_PAL75_I0_Pos                                      15                                                        /*!< LCD PAL75: I0 Position              */
+#define LCD_PAL75_I0_Msk                                      (0x01UL << LCD_PAL75_I0_Pos)                              /*!< LCD PAL75: I0 Mask                  */
+#define LCD_PAL75_R14_0_Pos                                   16                                                        /*!< LCD PAL75: R14_0 Position           */
+#define LCD_PAL75_R14_0_Msk                                   (0x1fUL << LCD_PAL75_R14_0_Pos)                           /*!< LCD PAL75: R14_0 Mask               */
+#define LCD_PAL75_G14_0_Pos                                   21                                                        /*!< LCD PAL75: G14_0 Position           */
+#define LCD_PAL75_G14_0_Msk                                   (0x1fUL << LCD_PAL75_G14_0_Pos)                           /*!< LCD PAL75: G14_0 Mask               */
+#define LCD_PAL75_B14_0_Pos                                   26                                                        /*!< LCD PAL75: B14_0 Position           */
+#define LCD_PAL75_B14_0_Msk                                   (0x1fUL << LCD_PAL75_B14_0_Pos)                           /*!< LCD PAL75: B14_0 Mask               */
+#define LCD_PAL75_I1_Pos                                      31                                                        /*!< LCD PAL75: I1 Position              */
+#define LCD_PAL75_I1_Msk                                      (0x01UL << LCD_PAL75_I1_Pos)                              /*!< LCD PAL75: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL76  -------------------------------------------
+#define LCD_PAL76_R04_0_Pos                                   0                                                         /*!< LCD PAL76: R04_0 Position           */
+#define LCD_PAL76_R04_0_Msk                                   (0x1fUL << LCD_PAL76_R04_0_Pos)                           /*!< LCD PAL76: R04_0 Mask               */
+#define LCD_PAL76_G04_0_Pos                                   5                                                         /*!< LCD PAL76: G04_0 Position           */
+#define LCD_PAL76_G04_0_Msk                                   (0x1fUL << LCD_PAL76_G04_0_Pos)                           /*!< LCD PAL76: G04_0 Mask               */
+#define LCD_PAL76_B04_0_Pos                                   10                                                        /*!< LCD PAL76: B04_0 Position           */
+#define LCD_PAL76_B04_0_Msk                                   (0x1fUL << LCD_PAL76_B04_0_Pos)                           /*!< LCD PAL76: B04_0 Mask               */
+#define LCD_PAL76_I0_Pos                                      15                                                        /*!< LCD PAL76: I0 Position              */
+#define LCD_PAL76_I0_Msk                                      (0x01UL << LCD_PAL76_I0_Pos)                              /*!< LCD PAL76: I0 Mask                  */
+#define LCD_PAL76_R14_0_Pos                                   16                                                        /*!< LCD PAL76: R14_0 Position           */
+#define LCD_PAL76_R14_0_Msk                                   (0x1fUL << LCD_PAL76_R14_0_Pos)                           /*!< LCD PAL76: R14_0 Mask               */
+#define LCD_PAL76_G14_0_Pos                                   21                                                        /*!< LCD PAL76: G14_0 Position           */
+#define LCD_PAL76_G14_0_Msk                                   (0x1fUL << LCD_PAL76_G14_0_Pos)                           /*!< LCD PAL76: G14_0 Mask               */
+#define LCD_PAL76_B14_0_Pos                                   26                                                        /*!< LCD PAL76: B14_0 Position           */
+#define LCD_PAL76_B14_0_Msk                                   (0x1fUL << LCD_PAL76_B14_0_Pos)                           /*!< LCD PAL76: B14_0 Mask               */
+#define LCD_PAL76_I1_Pos                                      31                                                        /*!< LCD PAL76: I1 Position              */
+#define LCD_PAL76_I1_Msk                                      (0x01UL << LCD_PAL76_I1_Pos)                              /*!< LCD PAL76: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL77  -------------------------------------------
+#define LCD_PAL77_R04_0_Pos                                   0                                                         /*!< LCD PAL77: R04_0 Position           */
+#define LCD_PAL77_R04_0_Msk                                   (0x1fUL << LCD_PAL77_R04_0_Pos)                           /*!< LCD PAL77: R04_0 Mask               */
+#define LCD_PAL77_G04_0_Pos                                   5                                                         /*!< LCD PAL77: G04_0 Position           */
+#define LCD_PAL77_G04_0_Msk                                   (0x1fUL << LCD_PAL77_G04_0_Pos)                           /*!< LCD PAL77: G04_0 Mask               */
+#define LCD_PAL77_B04_0_Pos                                   10                                                        /*!< LCD PAL77: B04_0 Position           */
+#define LCD_PAL77_B04_0_Msk                                   (0x1fUL << LCD_PAL77_B04_0_Pos)                           /*!< LCD PAL77: B04_0 Mask               */
+#define LCD_PAL77_I0_Pos                                      15                                                        /*!< LCD PAL77: I0 Position              */
+#define LCD_PAL77_I0_Msk                                      (0x01UL << LCD_PAL77_I0_Pos)                              /*!< LCD PAL77: I0 Mask                  */
+#define LCD_PAL77_R14_0_Pos                                   16                                                        /*!< LCD PAL77: R14_0 Position           */
+#define LCD_PAL77_R14_0_Msk                                   (0x1fUL << LCD_PAL77_R14_0_Pos)                           /*!< LCD PAL77: R14_0 Mask               */
+#define LCD_PAL77_G14_0_Pos                                   21                                                        /*!< LCD PAL77: G14_0 Position           */
+#define LCD_PAL77_G14_0_Msk                                   (0x1fUL << LCD_PAL77_G14_0_Pos)                           /*!< LCD PAL77: G14_0 Mask               */
+#define LCD_PAL77_B14_0_Pos                                   26                                                        /*!< LCD PAL77: B14_0 Position           */
+#define LCD_PAL77_B14_0_Msk                                   (0x1fUL << LCD_PAL77_B14_0_Pos)                           /*!< LCD PAL77: B14_0 Mask               */
+#define LCD_PAL77_I1_Pos                                      31                                                        /*!< LCD PAL77: I1 Position              */
+#define LCD_PAL77_I1_Msk                                      (0x01UL << LCD_PAL77_I1_Pos)                              /*!< LCD PAL77: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL78  -------------------------------------------
+#define LCD_PAL78_R04_0_Pos                                   0                                                         /*!< LCD PAL78: R04_0 Position           */
+#define LCD_PAL78_R04_0_Msk                                   (0x1fUL << LCD_PAL78_R04_0_Pos)                           /*!< LCD PAL78: R04_0 Mask               */
+#define LCD_PAL78_G04_0_Pos                                   5                                                         /*!< LCD PAL78: G04_0 Position           */
+#define LCD_PAL78_G04_0_Msk                                   (0x1fUL << LCD_PAL78_G04_0_Pos)                           /*!< LCD PAL78: G04_0 Mask               */
+#define LCD_PAL78_B04_0_Pos                                   10                                                        /*!< LCD PAL78: B04_0 Position           */
+#define LCD_PAL78_B04_0_Msk                                   (0x1fUL << LCD_PAL78_B04_0_Pos)                           /*!< LCD PAL78: B04_0 Mask               */
+#define LCD_PAL78_I0_Pos                                      15                                                        /*!< LCD PAL78: I0 Position              */
+#define LCD_PAL78_I0_Msk                                      (0x01UL << LCD_PAL78_I0_Pos)                              /*!< LCD PAL78: I0 Mask                  */
+#define LCD_PAL78_R14_0_Pos                                   16                                                        /*!< LCD PAL78: R14_0 Position           */
+#define LCD_PAL78_R14_0_Msk                                   (0x1fUL << LCD_PAL78_R14_0_Pos)                           /*!< LCD PAL78: R14_0 Mask               */
+#define LCD_PAL78_G14_0_Pos                                   21                                                        /*!< LCD PAL78: G14_0 Position           */
+#define LCD_PAL78_G14_0_Msk                                   (0x1fUL << LCD_PAL78_G14_0_Pos)                           /*!< LCD PAL78: G14_0 Mask               */
+#define LCD_PAL78_B14_0_Pos                                   26                                                        /*!< LCD PAL78: B14_0 Position           */
+#define LCD_PAL78_B14_0_Msk                                   (0x1fUL << LCD_PAL78_B14_0_Pos)                           /*!< LCD PAL78: B14_0 Mask               */
+#define LCD_PAL78_I1_Pos                                      31                                                        /*!< LCD PAL78: I1 Position              */
+#define LCD_PAL78_I1_Msk                                      (0x01UL << LCD_PAL78_I1_Pos)                              /*!< LCD PAL78: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL79  -------------------------------------------
+#define LCD_PAL79_R04_0_Pos                                   0                                                         /*!< LCD PAL79: R04_0 Position           */
+#define LCD_PAL79_R04_0_Msk                                   (0x1fUL << LCD_PAL79_R04_0_Pos)                           /*!< LCD PAL79: R04_0 Mask               */
+#define LCD_PAL79_G04_0_Pos                                   5                                                         /*!< LCD PAL79: G04_0 Position           */
+#define LCD_PAL79_G04_0_Msk                                   (0x1fUL << LCD_PAL79_G04_0_Pos)                           /*!< LCD PAL79: G04_0 Mask               */
+#define LCD_PAL79_B04_0_Pos                                   10                                                        /*!< LCD PAL79: B04_0 Position           */
+#define LCD_PAL79_B04_0_Msk                                   (0x1fUL << LCD_PAL79_B04_0_Pos)                           /*!< LCD PAL79: B04_0 Mask               */
+#define LCD_PAL79_I0_Pos                                      15                                                        /*!< LCD PAL79: I0 Position              */
+#define LCD_PAL79_I0_Msk                                      (0x01UL << LCD_PAL79_I0_Pos)                              /*!< LCD PAL79: I0 Mask                  */
+#define LCD_PAL79_R14_0_Pos                                   16                                                        /*!< LCD PAL79: R14_0 Position           */
+#define LCD_PAL79_R14_0_Msk                                   (0x1fUL << LCD_PAL79_R14_0_Pos)                           /*!< LCD PAL79: R14_0 Mask               */
+#define LCD_PAL79_G14_0_Pos                                   21                                                        /*!< LCD PAL79: G14_0 Position           */
+#define LCD_PAL79_G14_0_Msk                                   (0x1fUL << LCD_PAL79_G14_0_Pos)                           /*!< LCD PAL79: G14_0 Mask               */
+#define LCD_PAL79_B14_0_Pos                                   26                                                        /*!< LCD PAL79: B14_0 Position           */
+#define LCD_PAL79_B14_0_Msk                                   (0x1fUL << LCD_PAL79_B14_0_Pos)                           /*!< LCD PAL79: B14_0 Mask               */
+#define LCD_PAL79_I1_Pos                                      31                                                        /*!< LCD PAL79: I1 Position              */
+#define LCD_PAL79_I1_Msk                                      (0x01UL << LCD_PAL79_I1_Pos)                              /*!< LCD PAL79: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL80  -------------------------------------------
+#define LCD_PAL80_R04_0_Pos                                   0                                                         /*!< LCD PAL80: R04_0 Position           */
+#define LCD_PAL80_R04_0_Msk                                   (0x1fUL << LCD_PAL80_R04_0_Pos)                           /*!< LCD PAL80: R04_0 Mask               */
+#define LCD_PAL80_G04_0_Pos                                   5                                                         /*!< LCD PAL80: G04_0 Position           */
+#define LCD_PAL80_G04_0_Msk                                   (0x1fUL << LCD_PAL80_G04_0_Pos)                           /*!< LCD PAL80: G04_0 Mask               */
+#define LCD_PAL80_B04_0_Pos                                   10                                                        /*!< LCD PAL80: B04_0 Position           */
+#define LCD_PAL80_B04_0_Msk                                   (0x1fUL << LCD_PAL80_B04_0_Pos)                           /*!< LCD PAL80: B04_0 Mask               */
+#define LCD_PAL80_I0_Pos                                      15                                                        /*!< LCD PAL80: I0 Position              */
+#define LCD_PAL80_I0_Msk                                      (0x01UL << LCD_PAL80_I0_Pos)                              /*!< LCD PAL80: I0 Mask                  */
+#define LCD_PAL80_R14_0_Pos                                   16                                                        /*!< LCD PAL80: R14_0 Position           */
+#define LCD_PAL80_R14_0_Msk                                   (0x1fUL << LCD_PAL80_R14_0_Pos)                           /*!< LCD PAL80: R14_0 Mask               */
+#define LCD_PAL80_G14_0_Pos                                   21                                                        /*!< LCD PAL80: G14_0 Position           */
+#define LCD_PAL80_G14_0_Msk                                   (0x1fUL << LCD_PAL80_G14_0_Pos)                           /*!< LCD PAL80: G14_0 Mask               */
+#define LCD_PAL80_B14_0_Pos                                   26                                                        /*!< LCD PAL80: B14_0 Position           */
+#define LCD_PAL80_B14_0_Msk                                   (0x1fUL << LCD_PAL80_B14_0_Pos)                           /*!< LCD PAL80: B14_0 Mask               */
+#define LCD_PAL80_I1_Pos                                      31                                                        /*!< LCD PAL80: I1 Position              */
+#define LCD_PAL80_I1_Msk                                      (0x01UL << LCD_PAL80_I1_Pos)                              /*!< LCD PAL80: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL81  -------------------------------------------
+#define LCD_PAL81_R04_0_Pos                                   0                                                         /*!< LCD PAL81: R04_0 Position           */
+#define LCD_PAL81_R04_0_Msk                                   (0x1fUL << LCD_PAL81_R04_0_Pos)                           /*!< LCD PAL81: R04_0 Mask               */
+#define LCD_PAL81_G04_0_Pos                                   5                                                         /*!< LCD PAL81: G04_0 Position           */
+#define LCD_PAL81_G04_0_Msk                                   (0x1fUL << LCD_PAL81_G04_0_Pos)                           /*!< LCD PAL81: G04_0 Mask               */
+#define LCD_PAL81_B04_0_Pos                                   10                                                        /*!< LCD PAL81: B04_0 Position           */
+#define LCD_PAL81_B04_0_Msk                                   (0x1fUL << LCD_PAL81_B04_0_Pos)                           /*!< LCD PAL81: B04_0 Mask               */
+#define LCD_PAL81_I0_Pos                                      15                                                        /*!< LCD PAL81: I0 Position              */
+#define LCD_PAL81_I0_Msk                                      (0x01UL << LCD_PAL81_I0_Pos)                              /*!< LCD PAL81: I0 Mask                  */
+#define LCD_PAL81_R14_0_Pos                                   16                                                        /*!< LCD PAL81: R14_0 Position           */
+#define LCD_PAL81_R14_0_Msk                                   (0x1fUL << LCD_PAL81_R14_0_Pos)                           /*!< LCD PAL81: R14_0 Mask               */
+#define LCD_PAL81_G14_0_Pos                                   21                                                        /*!< LCD PAL81: G14_0 Position           */
+#define LCD_PAL81_G14_0_Msk                                   (0x1fUL << LCD_PAL81_G14_0_Pos)                           /*!< LCD PAL81: G14_0 Mask               */
+#define LCD_PAL81_B14_0_Pos                                   26                                                        /*!< LCD PAL81: B14_0 Position           */
+#define LCD_PAL81_B14_0_Msk                                   (0x1fUL << LCD_PAL81_B14_0_Pos)                           /*!< LCD PAL81: B14_0 Mask               */
+#define LCD_PAL81_I1_Pos                                      31                                                        /*!< LCD PAL81: I1 Position              */
+#define LCD_PAL81_I1_Msk                                      (0x01UL << LCD_PAL81_I1_Pos)                              /*!< LCD PAL81: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL82  -------------------------------------------
+#define LCD_PAL82_R04_0_Pos                                   0                                                         /*!< LCD PAL82: R04_0 Position           */
+#define LCD_PAL82_R04_0_Msk                                   (0x1fUL << LCD_PAL82_R04_0_Pos)                           /*!< LCD PAL82: R04_0 Mask               */
+#define LCD_PAL82_G04_0_Pos                                   5                                                         /*!< LCD PAL82: G04_0 Position           */
+#define LCD_PAL82_G04_0_Msk                                   (0x1fUL << LCD_PAL82_G04_0_Pos)                           /*!< LCD PAL82: G04_0 Mask               */
+#define LCD_PAL82_B04_0_Pos                                   10                                                        /*!< LCD PAL82: B04_0 Position           */
+#define LCD_PAL82_B04_0_Msk                                   (0x1fUL << LCD_PAL82_B04_0_Pos)                           /*!< LCD PAL82: B04_0 Mask               */
+#define LCD_PAL82_I0_Pos                                      15                                                        /*!< LCD PAL82: I0 Position              */
+#define LCD_PAL82_I0_Msk                                      (0x01UL << LCD_PAL82_I0_Pos)                              /*!< LCD PAL82: I0 Mask                  */
+#define LCD_PAL82_R14_0_Pos                                   16                                                        /*!< LCD PAL82: R14_0 Position           */
+#define LCD_PAL82_R14_0_Msk                                   (0x1fUL << LCD_PAL82_R14_0_Pos)                           /*!< LCD PAL82: R14_0 Mask               */
+#define LCD_PAL82_G14_0_Pos                                   21                                                        /*!< LCD PAL82: G14_0 Position           */
+#define LCD_PAL82_G14_0_Msk                                   (0x1fUL << LCD_PAL82_G14_0_Pos)                           /*!< LCD PAL82: G14_0 Mask               */
+#define LCD_PAL82_B14_0_Pos                                   26                                                        /*!< LCD PAL82: B14_0 Position           */
+#define LCD_PAL82_B14_0_Msk                                   (0x1fUL << LCD_PAL82_B14_0_Pos)                           /*!< LCD PAL82: B14_0 Mask               */
+#define LCD_PAL82_I1_Pos                                      31                                                        /*!< LCD PAL82: I1 Position              */
+#define LCD_PAL82_I1_Msk                                      (0x01UL << LCD_PAL82_I1_Pos)                              /*!< LCD PAL82: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL83  -------------------------------------------
+#define LCD_PAL83_R04_0_Pos                                   0                                                         /*!< LCD PAL83: R04_0 Position           */
+#define LCD_PAL83_R04_0_Msk                                   (0x1fUL << LCD_PAL83_R04_0_Pos)                           /*!< LCD PAL83: R04_0 Mask               */
+#define LCD_PAL83_G04_0_Pos                                   5                                                         /*!< LCD PAL83: G04_0 Position           */
+#define LCD_PAL83_G04_0_Msk                                   (0x1fUL << LCD_PAL83_G04_0_Pos)                           /*!< LCD PAL83: G04_0 Mask               */
+#define LCD_PAL83_B04_0_Pos                                   10                                                        /*!< LCD PAL83: B04_0 Position           */
+#define LCD_PAL83_B04_0_Msk                                   (0x1fUL << LCD_PAL83_B04_0_Pos)                           /*!< LCD PAL83: B04_0 Mask               */
+#define LCD_PAL83_I0_Pos                                      15                                                        /*!< LCD PAL83: I0 Position              */
+#define LCD_PAL83_I0_Msk                                      (0x01UL << LCD_PAL83_I0_Pos)                              /*!< LCD PAL83: I0 Mask                  */
+#define LCD_PAL83_R14_0_Pos                                   16                                                        /*!< LCD PAL83: R14_0 Position           */
+#define LCD_PAL83_R14_0_Msk                                   (0x1fUL << LCD_PAL83_R14_0_Pos)                           /*!< LCD PAL83: R14_0 Mask               */
+#define LCD_PAL83_G14_0_Pos                                   21                                                        /*!< LCD PAL83: G14_0 Position           */
+#define LCD_PAL83_G14_0_Msk                                   (0x1fUL << LCD_PAL83_G14_0_Pos)                           /*!< LCD PAL83: G14_0 Mask               */
+#define LCD_PAL83_B14_0_Pos                                   26                                                        /*!< LCD PAL83: B14_0 Position           */
+#define LCD_PAL83_B14_0_Msk                                   (0x1fUL << LCD_PAL83_B14_0_Pos)                           /*!< LCD PAL83: B14_0 Mask               */
+#define LCD_PAL83_I1_Pos                                      31                                                        /*!< LCD PAL83: I1 Position              */
+#define LCD_PAL83_I1_Msk                                      (0x01UL << LCD_PAL83_I1_Pos)                              /*!< LCD PAL83: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL84  -------------------------------------------
+#define LCD_PAL84_R04_0_Pos                                   0                                                         /*!< LCD PAL84: R04_0 Position           */
+#define LCD_PAL84_R04_0_Msk                                   (0x1fUL << LCD_PAL84_R04_0_Pos)                           /*!< LCD PAL84: R04_0 Mask               */
+#define LCD_PAL84_G04_0_Pos                                   5                                                         /*!< LCD PAL84: G04_0 Position           */
+#define LCD_PAL84_G04_0_Msk                                   (0x1fUL << LCD_PAL84_G04_0_Pos)                           /*!< LCD PAL84: G04_0 Mask               */
+#define LCD_PAL84_B04_0_Pos                                   10                                                        /*!< LCD PAL84: B04_0 Position           */
+#define LCD_PAL84_B04_0_Msk                                   (0x1fUL << LCD_PAL84_B04_0_Pos)                           /*!< LCD PAL84: B04_0 Mask               */
+#define LCD_PAL84_I0_Pos                                      15                                                        /*!< LCD PAL84: I0 Position              */
+#define LCD_PAL84_I0_Msk                                      (0x01UL << LCD_PAL84_I0_Pos)                              /*!< LCD PAL84: I0 Mask                  */
+#define LCD_PAL84_R14_0_Pos                                   16                                                        /*!< LCD PAL84: R14_0 Position           */
+#define LCD_PAL84_R14_0_Msk                                   (0x1fUL << LCD_PAL84_R14_0_Pos)                           /*!< LCD PAL84: R14_0 Mask               */
+#define LCD_PAL84_G14_0_Pos                                   21                                                        /*!< LCD PAL84: G14_0 Position           */
+#define LCD_PAL84_G14_0_Msk                                   (0x1fUL << LCD_PAL84_G14_0_Pos)                           /*!< LCD PAL84: G14_0 Mask               */
+#define LCD_PAL84_B14_0_Pos                                   26                                                        /*!< LCD PAL84: B14_0 Position           */
+#define LCD_PAL84_B14_0_Msk                                   (0x1fUL << LCD_PAL84_B14_0_Pos)                           /*!< LCD PAL84: B14_0 Mask               */
+#define LCD_PAL84_I1_Pos                                      31                                                        /*!< LCD PAL84: I1 Position              */
+#define LCD_PAL84_I1_Msk                                      (0x01UL << LCD_PAL84_I1_Pos)                              /*!< LCD PAL84: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL85  -------------------------------------------
+#define LCD_PAL85_R04_0_Pos                                   0                                                         /*!< LCD PAL85: R04_0 Position           */
+#define LCD_PAL85_R04_0_Msk                                   (0x1fUL << LCD_PAL85_R04_0_Pos)                           /*!< LCD PAL85: R04_0 Mask               */
+#define LCD_PAL85_G04_0_Pos                                   5                                                         /*!< LCD PAL85: G04_0 Position           */
+#define LCD_PAL85_G04_0_Msk                                   (0x1fUL << LCD_PAL85_G04_0_Pos)                           /*!< LCD PAL85: G04_0 Mask               */
+#define LCD_PAL85_B04_0_Pos                                   10                                                        /*!< LCD PAL85: B04_0 Position           */
+#define LCD_PAL85_B04_0_Msk                                   (0x1fUL << LCD_PAL85_B04_0_Pos)                           /*!< LCD PAL85: B04_0 Mask               */
+#define LCD_PAL85_I0_Pos                                      15                                                        /*!< LCD PAL85: I0 Position              */
+#define LCD_PAL85_I0_Msk                                      (0x01UL << LCD_PAL85_I0_Pos)                              /*!< LCD PAL85: I0 Mask                  */
+#define LCD_PAL85_R14_0_Pos                                   16                                                        /*!< LCD PAL85: R14_0 Position           */
+#define LCD_PAL85_R14_0_Msk                                   (0x1fUL << LCD_PAL85_R14_0_Pos)                           /*!< LCD PAL85: R14_0 Mask               */
+#define LCD_PAL85_G14_0_Pos                                   21                                                        /*!< LCD PAL85: G14_0 Position           */
+#define LCD_PAL85_G14_0_Msk                                   (0x1fUL << LCD_PAL85_G14_0_Pos)                           /*!< LCD PAL85: G14_0 Mask               */
+#define LCD_PAL85_B14_0_Pos                                   26                                                        /*!< LCD PAL85: B14_0 Position           */
+#define LCD_PAL85_B14_0_Msk                                   (0x1fUL << LCD_PAL85_B14_0_Pos)                           /*!< LCD PAL85: B14_0 Mask               */
+#define LCD_PAL85_I1_Pos                                      31                                                        /*!< LCD PAL85: I1 Position              */
+#define LCD_PAL85_I1_Msk                                      (0x01UL << LCD_PAL85_I1_Pos)                              /*!< LCD PAL85: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL86  -------------------------------------------
+#define LCD_PAL86_R04_0_Pos                                   0                                                         /*!< LCD PAL86: R04_0 Position           */
+#define LCD_PAL86_R04_0_Msk                                   (0x1fUL << LCD_PAL86_R04_0_Pos)                           /*!< LCD PAL86: R04_0 Mask               */
+#define LCD_PAL86_G04_0_Pos                                   5                                                         /*!< LCD PAL86: G04_0 Position           */
+#define LCD_PAL86_G04_0_Msk                                   (0x1fUL << LCD_PAL86_G04_0_Pos)                           /*!< LCD PAL86: G04_0 Mask               */
+#define LCD_PAL86_B04_0_Pos                                   10                                                        /*!< LCD PAL86: B04_0 Position           */
+#define LCD_PAL86_B04_0_Msk                                   (0x1fUL << LCD_PAL86_B04_0_Pos)                           /*!< LCD PAL86: B04_0 Mask               */
+#define LCD_PAL86_I0_Pos                                      15                                                        /*!< LCD PAL86: I0 Position              */
+#define LCD_PAL86_I0_Msk                                      (0x01UL << LCD_PAL86_I0_Pos)                              /*!< LCD PAL86: I0 Mask                  */
+#define LCD_PAL86_R14_0_Pos                                   16                                                        /*!< LCD PAL86: R14_0 Position           */
+#define LCD_PAL86_R14_0_Msk                                   (0x1fUL << LCD_PAL86_R14_0_Pos)                           /*!< LCD PAL86: R14_0 Mask               */
+#define LCD_PAL86_G14_0_Pos                                   21                                                        /*!< LCD PAL86: G14_0 Position           */
+#define LCD_PAL86_G14_0_Msk                                   (0x1fUL << LCD_PAL86_G14_0_Pos)                           /*!< LCD PAL86: G14_0 Mask               */
+#define LCD_PAL86_B14_0_Pos                                   26                                                        /*!< LCD PAL86: B14_0 Position           */
+#define LCD_PAL86_B14_0_Msk                                   (0x1fUL << LCD_PAL86_B14_0_Pos)                           /*!< LCD PAL86: B14_0 Mask               */
+#define LCD_PAL86_I1_Pos                                      31                                                        /*!< LCD PAL86: I1 Position              */
+#define LCD_PAL86_I1_Msk                                      (0x01UL << LCD_PAL86_I1_Pos)                              /*!< LCD PAL86: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL87  -------------------------------------------
+#define LCD_PAL87_R04_0_Pos                                   0                                                         /*!< LCD PAL87: R04_0 Position           */
+#define LCD_PAL87_R04_0_Msk                                   (0x1fUL << LCD_PAL87_R04_0_Pos)                           /*!< LCD PAL87: R04_0 Mask               */
+#define LCD_PAL87_G04_0_Pos                                   5                                                         /*!< LCD PAL87: G04_0 Position           */
+#define LCD_PAL87_G04_0_Msk                                   (0x1fUL << LCD_PAL87_G04_0_Pos)                           /*!< LCD PAL87: G04_0 Mask               */
+#define LCD_PAL87_B04_0_Pos                                   10                                                        /*!< LCD PAL87: B04_0 Position           */
+#define LCD_PAL87_B04_0_Msk                                   (0x1fUL << LCD_PAL87_B04_0_Pos)                           /*!< LCD PAL87: B04_0 Mask               */
+#define LCD_PAL87_I0_Pos                                      15                                                        /*!< LCD PAL87: I0 Position              */
+#define LCD_PAL87_I0_Msk                                      (0x01UL << LCD_PAL87_I0_Pos)                              /*!< LCD PAL87: I0 Mask                  */
+#define LCD_PAL87_R14_0_Pos                                   16                                                        /*!< LCD PAL87: R14_0 Position           */
+#define LCD_PAL87_R14_0_Msk                                   (0x1fUL << LCD_PAL87_R14_0_Pos)                           /*!< LCD PAL87: R14_0 Mask               */
+#define LCD_PAL87_G14_0_Pos                                   21                                                        /*!< LCD PAL87: G14_0 Position           */
+#define LCD_PAL87_G14_0_Msk                                   (0x1fUL << LCD_PAL87_G14_0_Pos)                           /*!< LCD PAL87: G14_0 Mask               */
+#define LCD_PAL87_B14_0_Pos                                   26                                                        /*!< LCD PAL87: B14_0 Position           */
+#define LCD_PAL87_B14_0_Msk                                   (0x1fUL << LCD_PAL87_B14_0_Pos)                           /*!< LCD PAL87: B14_0 Mask               */
+#define LCD_PAL87_I1_Pos                                      31                                                        /*!< LCD PAL87: I1 Position              */
+#define LCD_PAL87_I1_Msk                                      (0x01UL << LCD_PAL87_I1_Pos)                              /*!< LCD PAL87: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL88  -------------------------------------------
+#define LCD_PAL88_R04_0_Pos                                   0                                                         /*!< LCD PAL88: R04_0 Position           */
+#define LCD_PAL88_R04_0_Msk                                   (0x1fUL << LCD_PAL88_R04_0_Pos)                           /*!< LCD PAL88: R04_0 Mask               */
+#define LCD_PAL88_G04_0_Pos                                   5                                                         /*!< LCD PAL88: G04_0 Position           */
+#define LCD_PAL88_G04_0_Msk                                   (0x1fUL << LCD_PAL88_G04_0_Pos)                           /*!< LCD PAL88: G04_0 Mask               */
+#define LCD_PAL88_B04_0_Pos                                   10                                                        /*!< LCD PAL88: B04_0 Position           */
+#define LCD_PAL88_B04_0_Msk                                   (0x1fUL << LCD_PAL88_B04_0_Pos)                           /*!< LCD PAL88: B04_0 Mask               */
+#define LCD_PAL88_I0_Pos                                      15                                                        /*!< LCD PAL88: I0 Position              */
+#define LCD_PAL88_I0_Msk                                      (0x01UL << LCD_PAL88_I0_Pos)                              /*!< LCD PAL88: I0 Mask                  */
+#define LCD_PAL88_R14_0_Pos                                   16                                                        /*!< LCD PAL88: R14_0 Position           */
+#define LCD_PAL88_R14_0_Msk                                   (0x1fUL << LCD_PAL88_R14_0_Pos)                           /*!< LCD PAL88: R14_0 Mask               */
+#define LCD_PAL88_G14_0_Pos                                   21                                                        /*!< LCD PAL88: G14_0 Position           */
+#define LCD_PAL88_G14_0_Msk                                   (0x1fUL << LCD_PAL88_G14_0_Pos)                           /*!< LCD PAL88: G14_0 Mask               */
+#define LCD_PAL88_B14_0_Pos                                   26                                                        /*!< LCD PAL88: B14_0 Position           */
+#define LCD_PAL88_B14_0_Msk                                   (0x1fUL << LCD_PAL88_B14_0_Pos)                           /*!< LCD PAL88: B14_0 Mask               */
+#define LCD_PAL88_I1_Pos                                      31                                                        /*!< LCD PAL88: I1 Position              */
+#define LCD_PAL88_I1_Msk                                      (0x01UL << LCD_PAL88_I1_Pos)                              /*!< LCD PAL88: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL89  -------------------------------------------
+#define LCD_PAL89_R04_0_Pos                                   0                                                         /*!< LCD PAL89: R04_0 Position           */
+#define LCD_PAL89_R04_0_Msk                                   (0x1fUL << LCD_PAL89_R04_0_Pos)                           /*!< LCD PAL89: R04_0 Mask               */
+#define LCD_PAL89_G04_0_Pos                                   5                                                         /*!< LCD PAL89: G04_0 Position           */
+#define LCD_PAL89_G04_0_Msk                                   (0x1fUL << LCD_PAL89_G04_0_Pos)                           /*!< LCD PAL89: G04_0 Mask               */
+#define LCD_PAL89_B04_0_Pos                                   10                                                        /*!< LCD PAL89: B04_0 Position           */
+#define LCD_PAL89_B04_0_Msk                                   (0x1fUL << LCD_PAL89_B04_0_Pos)                           /*!< LCD PAL89: B04_0 Mask               */
+#define LCD_PAL89_I0_Pos                                      15                                                        /*!< LCD PAL89: I0 Position              */
+#define LCD_PAL89_I0_Msk                                      (0x01UL << LCD_PAL89_I0_Pos)                              /*!< LCD PAL89: I0 Mask                  */
+#define LCD_PAL89_R14_0_Pos                                   16                                                        /*!< LCD PAL89: R14_0 Position           */
+#define LCD_PAL89_R14_0_Msk                                   (0x1fUL << LCD_PAL89_R14_0_Pos)                           /*!< LCD PAL89: R14_0 Mask               */
+#define LCD_PAL89_G14_0_Pos                                   21                                                        /*!< LCD PAL89: G14_0 Position           */
+#define LCD_PAL89_G14_0_Msk                                   (0x1fUL << LCD_PAL89_G14_0_Pos)                           /*!< LCD PAL89: G14_0 Mask               */
+#define LCD_PAL89_B14_0_Pos                                   26                                                        /*!< LCD PAL89: B14_0 Position           */
+#define LCD_PAL89_B14_0_Msk                                   (0x1fUL << LCD_PAL89_B14_0_Pos)                           /*!< LCD PAL89: B14_0 Mask               */
+#define LCD_PAL89_I1_Pos                                      31                                                        /*!< LCD PAL89: I1 Position              */
+#define LCD_PAL89_I1_Msk                                      (0x01UL << LCD_PAL89_I1_Pos)                              /*!< LCD PAL89: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL90  -------------------------------------------
+#define LCD_PAL90_R04_0_Pos                                   0                                                         /*!< LCD PAL90: R04_0 Position           */
+#define LCD_PAL90_R04_0_Msk                                   (0x1fUL << LCD_PAL90_R04_0_Pos)                           /*!< LCD PAL90: R04_0 Mask               */
+#define LCD_PAL90_G04_0_Pos                                   5                                                         /*!< LCD PAL90: G04_0 Position           */
+#define LCD_PAL90_G04_0_Msk                                   (0x1fUL << LCD_PAL90_G04_0_Pos)                           /*!< LCD PAL90: G04_0 Mask               */
+#define LCD_PAL90_B04_0_Pos                                   10                                                        /*!< LCD PAL90: B04_0 Position           */
+#define LCD_PAL90_B04_0_Msk                                   (0x1fUL << LCD_PAL90_B04_0_Pos)                           /*!< LCD PAL90: B04_0 Mask               */
+#define LCD_PAL90_I0_Pos                                      15                                                        /*!< LCD PAL90: I0 Position              */
+#define LCD_PAL90_I0_Msk                                      (0x01UL << LCD_PAL90_I0_Pos)                              /*!< LCD PAL90: I0 Mask                  */
+#define LCD_PAL90_R14_0_Pos                                   16                                                        /*!< LCD PAL90: R14_0 Position           */
+#define LCD_PAL90_R14_0_Msk                                   (0x1fUL << LCD_PAL90_R14_0_Pos)                           /*!< LCD PAL90: R14_0 Mask               */
+#define LCD_PAL90_G14_0_Pos                                   21                                                        /*!< LCD PAL90: G14_0 Position           */
+#define LCD_PAL90_G14_0_Msk                                   (0x1fUL << LCD_PAL90_G14_0_Pos)                           /*!< LCD PAL90: G14_0 Mask               */
+#define LCD_PAL90_B14_0_Pos                                   26                                                        /*!< LCD PAL90: B14_0 Position           */
+#define LCD_PAL90_B14_0_Msk                                   (0x1fUL << LCD_PAL90_B14_0_Pos)                           /*!< LCD PAL90: B14_0 Mask               */
+#define LCD_PAL90_I1_Pos                                      31                                                        /*!< LCD PAL90: I1 Position              */
+#define LCD_PAL90_I1_Msk                                      (0x01UL << LCD_PAL90_I1_Pos)                              /*!< LCD PAL90: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL91  -------------------------------------------
+#define LCD_PAL91_R04_0_Pos                                   0                                                         /*!< LCD PAL91: R04_0 Position           */
+#define LCD_PAL91_R04_0_Msk                                   (0x1fUL << LCD_PAL91_R04_0_Pos)                           /*!< LCD PAL91: R04_0 Mask               */
+#define LCD_PAL91_G04_0_Pos                                   5                                                         /*!< LCD PAL91: G04_0 Position           */
+#define LCD_PAL91_G04_0_Msk                                   (0x1fUL << LCD_PAL91_G04_0_Pos)                           /*!< LCD PAL91: G04_0 Mask               */
+#define LCD_PAL91_B04_0_Pos                                   10                                                        /*!< LCD PAL91: B04_0 Position           */
+#define LCD_PAL91_B04_0_Msk                                   (0x1fUL << LCD_PAL91_B04_0_Pos)                           /*!< LCD PAL91: B04_0 Mask               */
+#define LCD_PAL91_I0_Pos                                      15                                                        /*!< LCD PAL91: I0 Position              */
+#define LCD_PAL91_I0_Msk                                      (0x01UL << LCD_PAL91_I0_Pos)                              /*!< LCD PAL91: I0 Mask                  */
+#define LCD_PAL91_R14_0_Pos                                   16                                                        /*!< LCD PAL91: R14_0 Position           */
+#define LCD_PAL91_R14_0_Msk                                   (0x1fUL << LCD_PAL91_R14_0_Pos)                           /*!< LCD PAL91: R14_0 Mask               */
+#define LCD_PAL91_G14_0_Pos                                   21                                                        /*!< LCD PAL91: G14_0 Position           */
+#define LCD_PAL91_G14_0_Msk                                   (0x1fUL << LCD_PAL91_G14_0_Pos)                           /*!< LCD PAL91: G14_0 Mask               */
+#define LCD_PAL91_B14_0_Pos                                   26                                                        /*!< LCD PAL91: B14_0 Position           */
+#define LCD_PAL91_B14_0_Msk                                   (0x1fUL << LCD_PAL91_B14_0_Pos)                           /*!< LCD PAL91: B14_0 Mask               */
+#define LCD_PAL91_I1_Pos                                      31                                                        /*!< LCD PAL91: I1 Position              */
+#define LCD_PAL91_I1_Msk                                      (0x01UL << LCD_PAL91_I1_Pos)                              /*!< LCD PAL91: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL92  -------------------------------------------
+#define LCD_PAL92_R04_0_Pos                                   0                                                         /*!< LCD PAL92: R04_0 Position           */
+#define LCD_PAL92_R04_0_Msk                                   (0x1fUL << LCD_PAL92_R04_0_Pos)                           /*!< LCD PAL92: R04_0 Mask               */
+#define LCD_PAL92_G04_0_Pos                                   5                                                         /*!< LCD PAL92: G04_0 Position           */
+#define LCD_PAL92_G04_0_Msk                                   (0x1fUL << LCD_PAL92_G04_0_Pos)                           /*!< LCD PAL92: G04_0 Mask               */
+#define LCD_PAL92_B04_0_Pos                                   10                                                        /*!< LCD PAL92: B04_0 Position           */
+#define LCD_PAL92_B04_0_Msk                                   (0x1fUL << LCD_PAL92_B04_0_Pos)                           /*!< LCD PAL92: B04_0 Mask               */
+#define LCD_PAL92_I0_Pos                                      15                                                        /*!< LCD PAL92: I0 Position              */
+#define LCD_PAL92_I0_Msk                                      (0x01UL << LCD_PAL92_I0_Pos)                              /*!< LCD PAL92: I0 Mask                  */
+#define LCD_PAL92_R14_0_Pos                                   16                                                        /*!< LCD PAL92: R14_0 Position           */
+#define LCD_PAL92_R14_0_Msk                                   (0x1fUL << LCD_PAL92_R14_0_Pos)                           /*!< LCD PAL92: R14_0 Mask               */
+#define LCD_PAL92_G14_0_Pos                                   21                                                        /*!< LCD PAL92: G14_0 Position           */
+#define LCD_PAL92_G14_0_Msk                                   (0x1fUL << LCD_PAL92_G14_0_Pos)                           /*!< LCD PAL92: G14_0 Mask               */
+#define LCD_PAL92_B14_0_Pos                                   26                                                        /*!< LCD PAL92: B14_0 Position           */
+#define LCD_PAL92_B14_0_Msk                                   (0x1fUL << LCD_PAL92_B14_0_Pos)                           /*!< LCD PAL92: B14_0 Mask               */
+#define LCD_PAL92_I1_Pos                                      31                                                        /*!< LCD PAL92: I1 Position              */
+#define LCD_PAL92_I1_Msk                                      (0x01UL << LCD_PAL92_I1_Pos)                              /*!< LCD PAL92: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL93  -------------------------------------------
+#define LCD_PAL93_R04_0_Pos                                   0                                                         /*!< LCD PAL93: R04_0 Position           */
+#define LCD_PAL93_R04_0_Msk                                   (0x1fUL << LCD_PAL93_R04_0_Pos)                           /*!< LCD PAL93: R04_0 Mask               */
+#define LCD_PAL93_G04_0_Pos                                   5                                                         /*!< LCD PAL93: G04_0 Position           */
+#define LCD_PAL93_G04_0_Msk                                   (0x1fUL << LCD_PAL93_G04_0_Pos)                           /*!< LCD PAL93: G04_0 Mask               */
+#define LCD_PAL93_B04_0_Pos                                   10                                                        /*!< LCD PAL93: B04_0 Position           */
+#define LCD_PAL93_B04_0_Msk                                   (0x1fUL << LCD_PAL93_B04_0_Pos)                           /*!< LCD PAL93: B04_0 Mask               */
+#define LCD_PAL93_I0_Pos                                      15                                                        /*!< LCD PAL93: I0 Position              */
+#define LCD_PAL93_I0_Msk                                      (0x01UL << LCD_PAL93_I0_Pos)                              /*!< LCD PAL93: I0 Mask                  */
+#define LCD_PAL93_R14_0_Pos                                   16                                                        /*!< LCD PAL93: R14_0 Position           */
+#define LCD_PAL93_R14_0_Msk                                   (0x1fUL << LCD_PAL93_R14_0_Pos)                           /*!< LCD PAL93: R14_0 Mask               */
+#define LCD_PAL93_G14_0_Pos                                   21                                                        /*!< LCD PAL93: G14_0 Position           */
+#define LCD_PAL93_G14_0_Msk                                   (0x1fUL << LCD_PAL93_G14_0_Pos)                           /*!< LCD PAL93: G14_0 Mask               */
+#define LCD_PAL93_B14_0_Pos                                   26                                                        /*!< LCD PAL93: B14_0 Position           */
+#define LCD_PAL93_B14_0_Msk                                   (0x1fUL << LCD_PAL93_B14_0_Pos)                           /*!< LCD PAL93: B14_0 Mask               */
+#define LCD_PAL93_I1_Pos                                      31                                                        /*!< LCD PAL93: I1 Position              */
+#define LCD_PAL93_I1_Msk                                      (0x01UL << LCD_PAL93_I1_Pos)                              /*!< LCD PAL93: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL94  -------------------------------------------
+#define LCD_PAL94_R04_0_Pos                                   0                                                         /*!< LCD PAL94: R04_0 Position           */
+#define LCD_PAL94_R04_0_Msk                                   (0x1fUL << LCD_PAL94_R04_0_Pos)                           /*!< LCD PAL94: R04_0 Mask               */
+#define LCD_PAL94_G04_0_Pos                                   5                                                         /*!< LCD PAL94: G04_0 Position           */
+#define LCD_PAL94_G04_0_Msk                                   (0x1fUL << LCD_PAL94_G04_0_Pos)                           /*!< LCD PAL94: G04_0 Mask               */
+#define LCD_PAL94_B04_0_Pos                                   10                                                        /*!< LCD PAL94: B04_0 Position           */
+#define LCD_PAL94_B04_0_Msk                                   (0x1fUL << LCD_PAL94_B04_0_Pos)                           /*!< LCD PAL94: B04_0 Mask               */
+#define LCD_PAL94_I0_Pos                                      15                                                        /*!< LCD PAL94: I0 Position              */
+#define LCD_PAL94_I0_Msk                                      (0x01UL << LCD_PAL94_I0_Pos)                              /*!< LCD PAL94: I0 Mask                  */
+#define LCD_PAL94_R14_0_Pos                                   16                                                        /*!< LCD PAL94: R14_0 Position           */
+#define LCD_PAL94_R14_0_Msk                                   (0x1fUL << LCD_PAL94_R14_0_Pos)                           /*!< LCD PAL94: R14_0 Mask               */
+#define LCD_PAL94_G14_0_Pos                                   21                                                        /*!< LCD PAL94: G14_0 Position           */
+#define LCD_PAL94_G14_0_Msk                                   (0x1fUL << LCD_PAL94_G14_0_Pos)                           /*!< LCD PAL94: G14_0 Mask               */
+#define LCD_PAL94_B14_0_Pos                                   26                                                        /*!< LCD PAL94: B14_0 Position           */
+#define LCD_PAL94_B14_0_Msk                                   (0x1fUL << LCD_PAL94_B14_0_Pos)                           /*!< LCD PAL94: B14_0 Mask               */
+#define LCD_PAL94_I1_Pos                                      31                                                        /*!< LCD PAL94: I1 Position              */
+#define LCD_PAL94_I1_Msk                                      (0x01UL << LCD_PAL94_I1_Pos)                              /*!< LCD PAL94: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL95  -------------------------------------------
+#define LCD_PAL95_R04_0_Pos                                   0                                                         /*!< LCD PAL95: R04_0 Position           */
+#define LCD_PAL95_R04_0_Msk                                   (0x1fUL << LCD_PAL95_R04_0_Pos)                           /*!< LCD PAL95: R04_0 Mask               */
+#define LCD_PAL95_G04_0_Pos                                   5                                                         /*!< LCD PAL95: G04_0 Position           */
+#define LCD_PAL95_G04_0_Msk                                   (0x1fUL << LCD_PAL95_G04_0_Pos)                           /*!< LCD PAL95: G04_0 Mask               */
+#define LCD_PAL95_B04_0_Pos                                   10                                                        /*!< LCD PAL95: B04_0 Position           */
+#define LCD_PAL95_B04_0_Msk                                   (0x1fUL << LCD_PAL95_B04_0_Pos)                           /*!< LCD PAL95: B04_0 Mask               */
+#define LCD_PAL95_I0_Pos                                      15                                                        /*!< LCD PAL95: I0 Position              */
+#define LCD_PAL95_I0_Msk                                      (0x01UL << LCD_PAL95_I0_Pos)                              /*!< LCD PAL95: I0 Mask                  */
+#define LCD_PAL95_R14_0_Pos                                   16                                                        /*!< LCD PAL95: R14_0 Position           */
+#define LCD_PAL95_R14_0_Msk                                   (0x1fUL << LCD_PAL95_R14_0_Pos)                           /*!< LCD PAL95: R14_0 Mask               */
+#define LCD_PAL95_G14_0_Pos                                   21                                                        /*!< LCD PAL95: G14_0 Position           */
+#define LCD_PAL95_G14_0_Msk                                   (0x1fUL << LCD_PAL95_G14_0_Pos)                           /*!< LCD PAL95: G14_0 Mask               */
+#define LCD_PAL95_B14_0_Pos                                   26                                                        /*!< LCD PAL95: B14_0 Position           */
+#define LCD_PAL95_B14_0_Msk                                   (0x1fUL << LCD_PAL95_B14_0_Pos)                           /*!< LCD PAL95: B14_0 Mask               */
+#define LCD_PAL95_I1_Pos                                      31                                                        /*!< LCD PAL95: I1 Position              */
+#define LCD_PAL95_I1_Msk                                      (0x01UL << LCD_PAL95_I1_Pos)                              /*!< LCD PAL95: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL96  -------------------------------------------
+#define LCD_PAL96_R04_0_Pos                                   0                                                         /*!< LCD PAL96: R04_0 Position           */
+#define LCD_PAL96_R04_0_Msk                                   (0x1fUL << LCD_PAL96_R04_0_Pos)                           /*!< LCD PAL96: R04_0 Mask               */
+#define LCD_PAL96_G04_0_Pos                                   5                                                         /*!< LCD PAL96: G04_0 Position           */
+#define LCD_PAL96_G04_0_Msk                                   (0x1fUL << LCD_PAL96_G04_0_Pos)                           /*!< LCD PAL96: G04_0 Mask               */
+#define LCD_PAL96_B04_0_Pos                                   10                                                        /*!< LCD PAL96: B04_0 Position           */
+#define LCD_PAL96_B04_0_Msk                                   (0x1fUL << LCD_PAL96_B04_0_Pos)                           /*!< LCD PAL96: B04_0 Mask               */
+#define LCD_PAL96_I0_Pos                                      15                                                        /*!< LCD PAL96: I0 Position              */
+#define LCD_PAL96_I0_Msk                                      (0x01UL << LCD_PAL96_I0_Pos)                              /*!< LCD PAL96: I0 Mask                  */
+#define LCD_PAL96_R14_0_Pos                                   16                                                        /*!< LCD PAL96: R14_0 Position           */
+#define LCD_PAL96_R14_0_Msk                                   (0x1fUL << LCD_PAL96_R14_0_Pos)                           /*!< LCD PAL96: R14_0 Mask               */
+#define LCD_PAL96_G14_0_Pos                                   21                                                        /*!< LCD PAL96: G14_0 Position           */
+#define LCD_PAL96_G14_0_Msk                                   (0x1fUL << LCD_PAL96_G14_0_Pos)                           /*!< LCD PAL96: G14_0 Mask               */
+#define LCD_PAL96_B14_0_Pos                                   26                                                        /*!< LCD PAL96: B14_0 Position           */
+#define LCD_PAL96_B14_0_Msk                                   (0x1fUL << LCD_PAL96_B14_0_Pos)                           /*!< LCD PAL96: B14_0 Mask               */
+#define LCD_PAL96_I1_Pos                                      31                                                        /*!< LCD PAL96: I1 Position              */
+#define LCD_PAL96_I1_Msk                                      (0x01UL << LCD_PAL96_I1_Pos)                              /*!< LCD PAL96: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL97  -------------------------------------------
+#define LCD_PAL97_R04_0_Pos                                   0                                                         /*!< LCD PAL97: R04_0 Position           */
+#define LCD_PAL97_R04_0_Msk                                   (0x1fUL << LCD_PAL97_R04_0_Pos)                           /*!< LCD PAL97: R04_0 Mask               */
+#define LCD_PAL97_G04_0_Pos                                   5                                                         /*!< LCD PAL97: G04_0 Position           */
+#define LCD_PAL97_G04_0_Msk                                   (0x1fUL << LCD_PAL97_G04_0_Pos)                           /*!< LCD PAL97: G04_0 Mask               */
+#define LCD_PAL97_B04_0_Pos                                   10                                                        /*!< LCD PAL97: B04_0 Position           */
+#define LCD_PAL97_B04_0_Msk                                   (0x1fUL << LCD_PAL97_B04_0_Pos)                           /*!< LCD PAL97: B04_0 Mask               */
+#define LCD_PAL97_I0_Pos                                      15                                                        /*!< LCD PAL97: I0 Position              */
+#define LCD_PAL97_I0_Msk                                      (0x01UL << LCD_PAL97_I0_Pos)                              /*!< LCD PAL97: I0 Mask                  */
+#define LCD_PAL97_R14_0_Pos                                   16                                                        /*!< LCD PAL97: R14_0 Position           */
+#define LCD_PAL97_R14_0_Msk                                   (0x1fUL << LCD_PAL97_R14_0_Pos)                           /*!< LCD PAL97: R14_0 Mask               */
+#define LCD_PAL97_G14_0_Pos                                   21                                                        /*!< LCD PAL97: G14_0 Position           */
+#define LCD_PAL97_G14_0_Msk                                   (0x1fUL << LCD_PAL97_G14_0_Pos)                           /*!< LCD PAL97: G14_0 Mask               */
+#define LCD_PAL97_B14_0_Pos                                   26                                                        /*!< LCD PAL97: B14_0 Position           */
+#define LCD_PAL97_B14_0_Msk                                   (0x1fUL << LCD_PAL97_B14_0_Pos)                           /*!< LCD PAL97: B14_0 Mask               */
+#define LCD_PAL97_I1_Pos                                      31                                                        /*!< LCD PAL97: I1 Position              */
+#define LCD_PAL97_I1_Msk                                      (0x01UL << LCD_PAL97_I1_Pos)                              /*!< LCD PAL97: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL98  -------------------------------------------
+#define LCD_PAL98_R04_0_Pos                                   0                                                         /*!< LCD PAL98: R04_0 Position           */
+#define LCD_PAL98_R04_0_Msk                                   (0x1fUL << LCD_PAL98_R04_0_Pos)                           /*!< LCD PAL98: R04_0 Mask               */
+#define LCD_PAL98_G04_0_Pos                                   5                                                         /*!< LCD PAL98: G04_0 Position           */
+#define LCD_PAL98_G04_0_Msk                                   (0x1fUL << LCD_PAL98_G04_0_Pos)                           /*!< LCD PAL98: G04_0 Mask               */
+#define LCD_PAL98_B04_0_Pos                                   10                                                        /*!< LCD PAL98: B04_0 Position           */
+#define LCD_PAL98_B04_0_Msk                                   (0x1fUL << LCD_PAL98_B04_0_Pos)                           /*!< LCD PAL98: B04_0 Mask               */
+#define LCD_PAL98_I0_Pos                                      15                                                        /*!< LCD PAL98: I0 Position              */
+#define LCD_PAL98_I0_Msk                                      (0x01UL << LCD_PAL98_I0_Pos)                              /*!< LCD PAL98: I0 Mask                  */
+#define LCD_PAL98_R14_0_Pos                                   16                                                        /*!< LCD PAL98: R14_0 Position           */
+#define LCD_PAL98_R14_0_Msk                                   (0x1fUL << LCD_PAL98_R14_0_Pos)                           /*!< LCD PAL98: R14_0 Mask               */
+#define LCD_PAL98_G14_0_Pos                                   21                                                        /*!< LCD PAL98: G14_0 Position           */
+#define LCD_PAL98_G14_0_Msk                                   (0x1fUL << LCD_PAL98_G14_0_Pos)                           /*!< LCD PAL98: G14_0 Mask               */
+#define LCD_PAL98_B14_0_Pos                                   26                                                        /*!< LCD PAL98: B14_0 Position           */
+#define LCD_PAL98_B14_0_Msk                                   (0x1fUL << LCD_PAL98_B14_0_Pos)                           /*!< LCD PAL98: B14_0 Mask               */
+#define LCD_PAL98_I1_Pos                                      31                                                        /*!< LCD PAL98: I1 Position              */
+#define LCD_PAL98_I1_Msk                                      (0x01UL << LCD_PAL98_I1_Pos)                              /*!< LCD PAL98: I1 Mask                  */
+
+// ----------------------------------------  LCD_PAL99  -------------------------------------------
+#define LCD_PAL99_R04_0_Pos                                   0                                                         /*!< LCD PAL99: R04_0 Position           */
+#define LCD_PAL99_R04_0_Msk                                   (0x1fUL << LCD_PAL99_R04_0_Pos)                           /*!< LCD PAL99: R04_0 Mask               */
+#define LCD_PAL99_G04_0_Pos                                   5                                                         /*!< LCD PAL99: G04_0 Position           */
+#define LCD_PAL99_G04_0_Msk                                   (0x1fUL << LCD_PAL99_G04_0_Pos)                           /*!< LCD PAL99: G04_0 Mask               */
+#define LCD_PAL99_B04_0_Pos                                   10                                                        /*!< LCD PAL99: B04_0 Position           */
+#define LCD_PAL99_B04_0_Msk                                   (0x1fUL << LCD_PAL99_B04_0_Pos)                           /*!< LCD PAL99: B04_0 Mask               */
+#define LCD_PAL99_I0_Pos                                      15                                                        /*!< LCD PAL99: I0 Position              */
+#define LCD_PAL99_I0_Msk                                      (0x01UL << LCD_PAL99_I0_Pos)                              /*!< LCD PAL99: I0 Mask                  */
+#define LCD_PAL99_R14_0_Pos                                   16                                                        /*!< LCD PAL99: R14_0 Position           */
+#define LCD_PAL99_R14_0_Msk                                   (0x1fUL << LCD_PAL99_R14_0_Pos)                           /*!< LCD PAL99: R14_0 Mask               */
+#define LCD_PAL99_G14_0_Pos                                   21                                                        /*!< LCD PAL99: G14_0 Position           */
+#define LCD_PAL99_G14_0_Msk                                   (0x1fUL << LCD_PAL99_G14_0_Pos)                           /*!< LCD PAL99: G14_0 Mask               */
+#define LCD_PAL99_B14_0_Pos                                   26                                                        /*!< LCD PAL99: B14_0 Position           */
+#define LCD_PAL99_B14_0_Msk                                   (0x1fUL << LCD_PAL99_B14_0_Pos)                           /*!< LCD PAL99: B14_0 Mask               */
+#define LCD_PAL99_I1_Pos                                      31                                                        /*!< LCD PAL99: I1 Position              */
+#define LCD_PAL99_I1_Msk                                      (0x01UL << LCD_PAL99_I1_Pos)                              /*!< LCD PAL99: I1 Mask                  */
+
+// ---------------------------------------  LCD_PAL100  -------------------------------------------
+#define LCD_PAL100_R04_0_Pos                                  0                                                         /*!< LCD PAL100: R04_0 Position          */
+#define LCD_PAL100_R04_0_Msk                                  (0x1fUL << LCD_PAL100_R04_0_Pos)                          /*!< LCD PAL100: R04_0 Mask              */
+#define LCD_PAL100_G04_0_Pos                                  5                                                         /*!< LCD PAL100: G04_0 Position          */
+#define LCD_PAL100_G04_0_Msk                                  (0x1fUL << LCD_PAL100_G04_0_Pos)                          /*!< LCD PAL100: G04_0 Mask              */
+#define LCD_PAL100_B04_0_Pos                                  10                                                        /*!< LCD PAL100: B04_0 Position          */
+#define LCD_PAL100_B04_0_Msk                                  (0x1fUL << LCD_PAL100_B04_0_Pos)                          /*!< LCD PAL100: B04_0 Mask              */
+#define LCD_PAL100_I0_Pos                                     15                                                        /*!< LCD PAL100: I0 Position             */
+#define LCD_PAL100_I0_Msk                                     (0x01UL << LCD_PAL100_I0_Pos)                             /*!< LCD PAL100: I0 Mask                 */
+#define LCD_PAL100_R14_0_Pos                                  16                                                        /*!< LCD PAL100: R14_0 Position          */
+#define LCD_PAL100_R14_0_Msk                                  (0x1fUL << LCD_PAL100_R14_0_Pos)                          /*!< LCD PAL100: R14_0 Mask              */
+#define LCD_PAL100_G14_0_Pos                                  21                                                        /*!< LCD PAL100: G14_0 Position          */
+#define LCD_PAL100_G14_0_Msk                                  (0x1fUL << LCD_PAL100_G14_0_Pos)                          /*!< LCD PAL100: G14_0 Mask              */
+#define LCD_PAL100_B14_0_Pos                                  26                                                        /*!< LCD PAL100: B14_0 Position          */
+#define LCD_PAL100_B14_0_Msk                                  (0x1fUL << LCD_PAL100_B14_0_Pos)                          /*!< LCD PAL100: B14_0 Mask              */
+#define LCD_PAL100_I1_Pos                                     31                                                        /*!< LCD PAL100: I1 Position             */
+#define LCD_PAL100_I1_Msk                                     (0x01UL << LCD_PAL100_I1_Pos)                             /*!< LCD PAL100: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL101  -------------------------------------------
+#define LCD_PAL101_R04_0_Pos                                  0                                                         /*!< LCD PAL101: R04_0 Position          */
+#define LCD_PAL101_R04_0_Msk                                  (0x1fUL << LCD_PAL101_R04_0_Pos)                          /*!< LCD PAL101: R04_0 Mask              */
+#define LCD_PAL101_G04_0_Pos                                  5                                                         /*!< LCD PAL101: G04_0 Position          */
+#define LCD_PAL101_G04_0_Msk                                  (0x1fUL << LCD_PAL101_G04_0_Pos)                          /*!< LCD PAL101: G04_0 Mask              */
+#define LCD_PAL101_B04_0_Pos                                  10                                                        /*!< LCD PAL101: B04_0 Position          */
+#define LCD_PAL101_B04_0_Msk                                  (0x1fUL << LCD_PAL101_B04_0_Pos)                          /*!< LCD PAL101: B04_0 Mask              */
+#define LCD_PAL101_I0_Pos                                     15                                                        /*!< LCD PAL101: I0 Position             */
+#define LCD_PAL101_I0_Msk                                     (0x01UL << LCD_PAL101_I0_Pos)                             /*!< LCD PAL101: I0 Mask                 */
+#define LCD_PAL101_R14_0_Pos                                  16                                                        /*!< LCD PAL101: R14_0 Position          */
+#define LCD_PAL101_R14_0_Msk                                  (0x1fUL << LCD_PAL101_R14_0_Pos)                          /*!< LCD PAL101: R14_0 Mask              */
+#define LCD_PAL101_G14_0_Pos                                  21                                                        /*!< LCD PAL101: G14_0 Position          */
+#define LCD_PAL101_G14_0_Msk                                  (0x1fUL << LCD_PAL101_G14_0_Pos)                          /*!< LCD PAL101: G14_0 Mask              */
+#define LCD_PAL101_B14_0_Pos                                  26                                                        /*!< LCD PAL101: B14_0 Position          */
+#define LCD_PAL101_B14_0_Msk                                  (0x1fUL << LCD_PAL101_B14_0_Pos)                          /*!< LCD PAL101: B14_0 Mask              */
+#define LCD_PAL101_I1_Pos                                     31                                                        /*!< LCD PAL101: I1 Position             */
+#define LCD_PAL101_I1_Msk                                     (0x01UL << LCD_PAL101_I1_Pos)                             /*!< LCD PAL101: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL102  -------------------------------------------
+#define LCD_PAL102_R04_0_Pos                                  0                                                         /*!< LCD PAL102: R04_0 Position          */
+#define LCD_PAL102_R04_0_Msk                                  (0x1fUL << LCD_PAL102_R04_0_Pos)                          /*!< LCD PAL102: R04_0 Mask              */
+#define LCD_PAL102_G04_0_Pos                                  5                                                         /*!< LCD PAL102: G04_0 Position          */
+#define LCD_PAL102_G04_0_Msk                                  (0x1fUL << LCD_PAL102_G04_0_Pos)                          /*!< LCD PAL102: G04_0 Mask              */
+#define LCD_PAL102_B04_0_Pos                                  10                                                        /*!< LCD PAL102: B04_0 Position          */
+#define LCD_PAL102_B04_0_Msk                                  (0x1fUL << LCD_PAL102_B04_0_Pos)                          /*!< LCD PAL102: B04_0 Mask              */
+#define LCD_PAL102_I0_Pos                                     15                                                        /*!< LCD PAL102: I0 Position             */
+#define LCD_PAL102_I0_Msk                                     (0x01UL << LCD_PAL102_I0_Pos)                             /*!< LCD PAL102: I0 Mask                 */
+#define LCD_PAL102_R14_0_Pos                                  16                                                        /*!< LCD PAL102: R14_0 Position          */
+#define LCD_PAL102_R14_0_Msk                                  (0x1fUL << LCD_PAL102_R14_0_Pos)                          /*!< LCD PAL102: R14_0 Mask              */
+#define LCD_PAL102_G14_0_Pos                                  21                                                        /*!< LCD PAL102: G14_0 Position          */
+#define LCD_PAL102_G14_0_Msk                                  (0x1fUL << LCD_PAL102_G14_0_Pos)                          /*!< LCD PAL102: G14_0 Mask              */
+#define LCD_PAL102_B14_0_Pos                                  26                                                        /*!< LCD PAL102: B14_0 Position          */
+#define LCD_PAL102_B14_0_Msk                                  (0x1fUL << LCD_PAL102_B14_0_Pos)                          /*!< LCD PAL102: B14_0 Mask              */
+#define LCD_PAL102_I1_Pos                                     31                                                        /*!< LCD PAL102: I1 Position             */
+#define LCD_PAL102_I1_Msk                                     (0x01UL << LCD_PAL102_I1_Pos)                             /*!< LCD PAL102: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL103  -------------------------------------------
+#define LCD_PAL103_R04_0_Pos                                  0                                                         /*!< LCD PAL103: R04_0 Position          */
+#define LCD_PAL103_R04_0_Msk                                  (0x1fUL << LCD_PAL103_R04_0_Pos)                          /*!< LCD PAL103: R04_0 Mask              */
+#define LCD_PAL103_G04_0_Pos                                  5                                                         /*!< LCD PAL103: G04_0 Position          */
+#define LCD_PAL103_G04_0_Msk                                  (0x1fUL << LCD_PAL103_G04_0_Pos)                          /*!< LCD PAL103: G04_0 Mask              */
+#define LCD_PAL103_B04_0_Pos                                  10                                                        /*!< LCD PAL103: B04_0 Position          */
+#define LCD_PAL103_B04_0_Msk                                  (0x1fUL << LCD_PAL103_B04_0_Pos)                          /*!< LCD PAL103: B04_0 Mask              */
+#define LCD_PAL103_I0_Pos                                     15                                                        /*!< LCD PAL103: I0 Position             */
+#define LCD_PAL103_I0_Msk                                     (0x01UL << LCD_PAL103_I0_Pos)                             /*!< LCD PAL103: I0 Mask                 */
+#define LCD_PAL103_R14_0_Pos                                  16                                                        /*!< LCD PAL103: R14_0 Position          */
+#define LCD_PAL103_R14_0_Msk                                  (0x1fUL << LCD_PAL103_R14_0_Pos)                          /*!< LCD PAL103: R14_0 Mask              */
+#define LCD_PAL103_G14_0_Pos                                  21                                                        /*!< LCD PAL103: G14_0 Position          */
+#define LCD_PAL103_G14_0_Msk                                  (0x1fUL << LCD_PAL103_G14_0_Pos)                          /*!< LCD PAL103: G14_0 Mask              */
+#define LCD_PAL103_B14_0_Pos                                  26                                                        /*!< LCD PAL103: B14_0 Position          */
+#define LCD_PAL103_B14_0_Msk                                  (0x1fUL << LCD_PAL103_B14_0_Pos)                          /*!< LCD PAL103: B14_0 Mask              */
+#define LCD_PAL103_I1_Pos                                     31                                                        /*!< LCD PAL103: I1 Position             */
+#define LCD_PAL103_I1_Msk                                     (0x01UL << LCD_PAL103_I1_Pos)                             /*!< LCD PAL103: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL104  -------------------------------------------
+#define LCD_PAL104_R04_0_Pos                                  0                                                         /*!< LCD PAL104: R04_0 Position          */
+#define LCD_PAL104_R04_0_Msk                                  (0x1fUL << LCD_PAL104_R04_0_Pos)                          /*!< LCD PAL104: R04_0 Mask              */
+#define LCD_PAL104_G04_0_Pos                                  5                                                         /*!< LCD PAL104: G04_0 Position          */
+#define LCD_PAL104_G04_0_Msk                                  (0x1fUL << LCD_PAL104_G04_0_Pos)                          /*!< LCD PAL104: G04_0 Mask              */
+#define LCD_PAL104_B04_0_Pos                                  10                                                        /*!< LCD PAL104: B04_0 Position          */
+#define LCD_PAL104_B04_0_Msk                                  (0x1fUL << LCD_PAL104_B04_0_Pos)                          /*!< LCD PAL104: B04_0 Mask              */
+#define LCD_PAL104_I0_Pos                                     15                                                        /*!< LCD PAL104: I0 Position             */
+#define LCD_PAL104_I0_Msk                                     (0x01UL << LCD_PAL104_I0_Pos)                             /*!< LCD PAL104: I0 Mask                 */
+#define LCD_PAL104_R14_0_Pos                                  16                                                        /*!< LCD PAL104: R14_0 Position          */
+#define LCD_PAL104_R14_0_Msk                                  (0x1fUL << LCD_PAL104_R14_0_Pos)                          /*!< LCD PAL104: R14_0 Mask              */
+#define LCD_PAL104_G14_0_Pos                                  21                                                        /*!< LCD PAL104: G14_0 Position          */
+#define LCD_PAL104_G14_0_Msk                                  (0x1fUL << LCD_PAL104_G14_0_Pos)                          /*!< LCD PAL104: G14_0 Mask              */
+#define LCD_PAL104_B14_0_Pos                                  26                                                        /*!< LCD PAL104: B14_0 Position          */
+#define LCD_PAL104_B14_0_Msk                                  (0x1fUL << LCD_PAL104_B14_0_Pos)                          /*!< LCD PAL104: B14_0 Mask              */
+#define LCD_PAL104_I1_Pos                                     31                                                        /*!< LCD PAL104: I1 Position             */
+#define LCD_PAL104_I1_Msk                                     (0x01UL << LCD_PAL104_I1_Pos)                             /*!< LCD PAL104: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL105  -------------------------------------------
+#define LCD_PAL105_R04_0_Pos                                  0                                                         /*!< LCD PAL105: R04_0 Position          */
+#define LCD_PAL105_R04_0_Msk                                  (0x1fUL << LCD_PAL105_R04_0_Pos)                          /*!< LCD PAL105: R04_0 Mask              */
+#define LCD_PAL105_G04_0_Pos                                  5                                                         /*!< LCD PAL105: G04_0 Position          */
+#define LCD_PAL105_G04_0_Msk                                  (0x1fUL << LCD_PAL105_G04_0_Pos)                          /*!< LCD PAL105: G04_0 Mask              */
+#define LCD_PAL105_B04_0_Pos                                  10                                                        /*!< LCD PAL105: B04_0 Position          */
+#define LCD_PAL105_B04_0_Msk                                  (0x1fUL << LCD_PAL105_B04_0_Pos)                          /*!< LCD PAL105: B04_0 Mask              */
+#define LCD_PAL105_I0_Pos                                     15                                                        /*!< LCD PAL105: I0 Position             */
+#define LCD_PAL105_I0_Msk                                     (0x01UL << LCD_PAL105_I0_Pos)                             /*!< LCD PAL105: I0 Mask                 */
+#define LCD_PAL105_R14_0_Pos                                  16                                                        /*!< LCD PAL105: R14_0 Position          */
+#define LCD_PAL105_R14_0_Msk                                  (0x1fUL << LCD_PAL105_R14_0_Pos)                          /*!< LCD PAL105: R14_0 Mask              */
+#define LCD_PAL105_G14_0_Pos                                  21                                                        /*!< LCD PAL105: G14_0 Position          */
+#define LCD_PAL105_G14_0_Msk                                  (0x1fUL << LCD_PAL105_G14_0_Pos)                          /*!< LCD PAL105: G14_0 Mask              */
+#define LCD_PAL105_B14_0_Pos                                  26                                                        /*!< LCD PAL105: B14_0 Position          */
+#define LCD_PAL105_B14_0_Msk                                  (0x1fUL << LCD_PAL105_B14_0_Pos)                          /*!< LCD PAL105: B14_0 Mask              */
+#define LCD_PAL105_I1_Pos                                     31                                                        /*!< LCD PAL105: I1 Position             */
+#define LCD_PAL105_I1_Msk                                     (0x01UL << LCD_PAL105_I1_Pos)                             /*!< LCD PAL105: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL106  -------------------------------------------
+#define LCD_PAL106_R04_0_Pos                                  0                                                         /*!< LCD PAL106: R04_0 Position          */
+#define LCD_PAL106_R04_0_Msk                                  (0x1fUL << LCD_PAL106_R04_0_Pos)                          /*!< LCD PAL106: R04_0 Mask              */
+#define LCD_PAL106_G04_0_Pos                                  5                                                         /*!< LCD PAL106: G04_0 Position          */
+#define LCD_PAL106_G04_0_Msk                                  (0x1fUL << LCD_PAL106_G04_0_Pos)                          /*!< LCD PAL106: G04_0 Mask              */
+#define LCD_PAL106_B04_0_Pos                                  10                                                        /*!< LCD PAL106: B04_0 Position          */
+#define LCD_PAL106_B04_0_Msk                                  (0x1fUL << LCD_PAL106_B04_0_Pos)                          /*!< LCD PAL106: B04_0 Mask              */
+#define LCD_PAL106_I0_Pos                                     15                                                        /*!< LCD PAL106: I0 Position             */
+#define LCD_PAL106_I0_Msk                                     (0x01UL << LCD_PAL106_I0_Pos)                             /*!< LCD PAL106: I0 Mask                 */
+#define LCD_PAL106_R14_0_Pos                                  16                                                        /*!< LCD PAL106: R14_0 Position          */
+#define LCD_PAL106_R14_0_Msk                                  (0x1fUL << LCD_PAL106_R14_0_Pos)                          /*!< LCD PAL106: R14_0 Mask              */
+#define LCD_PAL106_G14_0_Pos                                  21                                                        /*!< LCD PAL106: G14_0 Position          */
+#define LCD_PAL106_G14_0_Msk                                  (0x1fUL << LCD_PAL106_G14_0_Pos)                          /*!< LCD PAL106: G14_0 Mask              */
+#define LCD_PAL106_B14_0_Pos                                  26                                                        /*!< LCD PAL106: B14_0 Position          */
+#define LCD_PAL106_B14_0_Msk                                  (0x1fUL << LCD_PAL106_B14_0_Pos)                          /*!< LCD PAL106: B14_0 Mask              */
+#define LCD_PAL106_I1_Pos                                     31                                                        /*!< LCD PAL106: I1 Position             */
+#define LCD_PAL106_I1_Msk                                     (0x01UL << LCD_PAL106_I1_Pos)                             /*!< LCD PAL106: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL107  -------------------------------------------
+#define LCD_PAL107_R04_0_Pos                                  0                                                         /*!< LCD PAL107: R04_0 Position          */
+#define LCD_PAL107_R04_0_Msk                                  (0x1fUL << LCD_PAL107_R04_0_Pos)                          /*!< LCD PAL107: R04_0 Mask              */
+#define LCD_PAL107_G04_0_Pos                                  5                                                         /*!< LCD PAL107: G04_0 Position          */
+#define LCD_PAL107_G04_0_Msk                                  (0x1fUL << LCD_PAL107_G04_0_Pos)                          /*!< LCD PAL107: G04_0 Mask              */
+#define LCD_PAL107_B04_0_Pos                                  10                                                        /*!< LCD PAL107: B04_0 Position          */
+#define LCD_PAL107_B04_0_Msk                                  (0x1fUL << LCD_PAL107_B04_0_Pos)                          /*!< LCD PAL107: B04_0 Mask              */
+#define LCD_PAL107_I0_Pos                                     15                                                        /*!< LCD PAL107: I0 Position             */
+#define LCD_PAL107_I0_Msk                                     (0x01UL << LCD_PAL107_I0_Pos)                             /*!< LCD PAL107: I0 Mask                 */
+#define LCD_PAL107_R14_0_Pos                                  16                                                        /*!< LCD PAL107: R14_0 Position          */
+#define LCD_PAL107_R14_0_Msk                                  (0x1fUL << LCD_PAL107_R14_0_Pos)                          /*!< LCD PAL107: R14_0 Mask              */
+#define LCD_PAL107_G14_0_Pos                                  21                                                        /*!< LCD PAL107: G14_0 Position          */
+#define LCD_PAL107_G14_0_Msk                                  (0x1fUL << LCD_PAL107_G14_0_Pos)                          /*!< LCD PAL107: G14_0 Mask              */
+#define LCD_PAL107_B14_0_Pos                                  26                                                        /*!< LCD PAL107: B14_0 Position          */
+#define LCD_PAL107_B14_0_Msk                                  (0x1fUL << LCD_PAL107_B14_0_Pos)                          /*!< LCD PAL107: B14_0 Mask              */
+#define LCD_PAL107_I1_Pos                                     31                                                        /*!< LCD PAL107: I1 Position             */
+#define LCD_PAL107_I1_Msk                                     (0x01UL << LCD_PAL107_I1_Pos)                             /*!< LCD PAL107: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL108  -------------------------------------------
+#define LCD_PAL108_R04_0_Pos                                  0                                                         /*!< LCD PAL108: R04_0 Position          */
+#define LCD_PAL108_R04_0_Msk                                  (0x1fUL << LCD_PAL108_R04_0_Pos)                          /*!< LCD PAL108: R04_0 Mask              */
+#define LCD_PAL108_G04_0_Pos                                  5                                                         /*!< LCD PAL108: G04_0 Position          */
+#define LCD_PAL108_G04_0_Msk                                  (0x1fUL << LCD_PAL108_G04_0_Pos)                          /*!< LCD PAL108: G04_0 Mask              */
+#define LCD_PAL108_B04_0_Pos                                  10                                                        /*!< LCD PAL108: B04_0 Position          */
+#define LCD_PAL108_B04_0_Msk                                  (0x1fUL << LCD_PAL108_B04_0_Pos)                          /*!< LCD PAL108: B04_0 Mask              */
+#define LCD_PAL108_I0_Pos                                     15                                                        /*!< LCD PAL108: I0 Position             */
+#define LCD_PAL108_I0_Msk                                     (0x01UL << LCD_PAL108_I0_Pos)                             /*!< LCD PAL108: I0 Mask                 */
+#define LCD_PAL108_R14_0_Pos                                  16                                                        /*!< LCD PAL108: R14_0 Position          */
+#define LCD_PAL108_R14_0_Msk                                  (0x1fUL << LCD_PAL108_R14_0_Pos)                          /*!< LCD PAL108: R14_0 Mask              */
+#define LCD_PAL108_G14_0_Pos                                  21                                                        /*!< LCD PAL108: G14_0 Position          */
+#define LCD_PAL108_G14_0_Msk                                  (0x1fUL << LCD_PAL108_G14_0_Pos)                          /*!< LCD PAL108: G14_0 Mask              */
+#define LCD_PAL108_B14_0_Pos                                  26                                                        /*!< LCD PAL108: B14_0 Position          */
+#define LCD_PAL108_B14_0_Msk                                  (0x1fUL << LCD_PAL108_B14_0_Pos)                          /*!< LCD PAL108: B14_0 Mask              */
+#define LCD_PAL108_I1_Pos                                     31                                                        /*!< LCD PAL108: I1 Position             */
+#define LCD_PAL108_I1_Msk                                     (0x01UL << LCD_PAL108_I1_Pos)                             /*!< LCD PAL108: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL109  -------------------------------------------
+#define LCD_PAL109_R04_0_Pos                                  0                                                         /*!< LCD PAL109: R04_0 Position          */
+#define LCD_PAL109_R04_0_Msk                                  (0x1fUL << LCD_PAL109_R04_0_Pos)                          /*!< LCD PAL109: R04_0 Mask              */
+#define LCD_PAL109_G04_0_Pos                                  5                                                         /*!< LCD PAL109: G04_0 Position          */
+#define LCD_PAL109_G04_0_Msk                                  (0x1fUL << LCD_PAL109_G04_0_Pos)                          /*!< LCD PAL109: G04_0 Mask              */
+#define LCD_PAL109_B04_0_Pos                                  10                                                        /*!< LCD PAL109: B04_0 Position          */
+#define LCD_PAL109_B04_0_Msk                                  (0x1fUL << LCD_PAL109_B04_0_Pos)                          /*!< LCD PAL109: B04_0 Mask              */
+#define LCD_PAL109_I0_Pos                                     15                                                        /*!< LCD PAL109: I0 Position             */
+#define LCD_PAL109_I0_Msk                                     (0x01UL << LCD_PAL109_I0_Pos)                             /*!< LCD PAL109: I0 Mask                 */
+#define LCD_PAL109_R14_0_Pos                                  16                                                        /*!< LCD PAL109: R14_0 Position          */
+#define LCD_PAL109_R14_0_Msk                                  (0x1fUL << LCD_PAL109_R14_0_Pos)                          /*!< LCD PAL109: R14_0 Mask              */
+#define LCD_PAL109_G14_0_Pos                                  21                                                        /*!< LCD PAL109: G14_0 Position          */
+#define LCD_PAL109_G14_0_Msk                                  (0x1fUL << LCD_PAL109_G14_0_Pos)                          /*!< LCD PAL109: G14_0 Mask              */
+#define LCD_PAL109_B14_0_Pos                                  26                                                        /*!< LCD PAL109: B14_0 Position          */
+#define LCD_PAL109_B14_0_Msk                                  (0x1fUL << LCD_PAL109_B14_0_Pos)                          /*!< LCD PAL109: B14_0 Mask              */
+#define LCD_PAL109_I1_Pos                                     31                                                        /*!< LCD PAL109: I1 Position             */
+#define LCD_PAL109_I1_Msk                                     (0x01UL << LCD_PAL109_I1_Pos)                             /*!< LCD PAL109: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL110  -------------------------------------------
+#define LCD_PAL110_R04_0_Pos                                  0                                                         /*!< LCD PAL110: R04_0 Position          */
+#define LCD_PAL110_R04_0_Msk                                  (0x1fUL << LCD_PAL110_R04_0_Pos)                          /*!< LCD PAL110: R04_0 Mask              */
+#define LCD_PAL110_G04_0_Pos                                  5                                                         /*!< LCD PAL110: G04_0 Position          */
+#define LCD_PAL110_G04_0_Msk                                  (0x1fUL << LCD_PAL110_G04_0_Pos)                          /*!< LCD PAL110: G04_0 Mask              */
+#define LCD_PAL110_B04_0_Pos                                  10                                                        /*!< LCD PAL110: B04_0 Position          */
+#define LCD_PAL110_B04_0_Msk                                  (0x1fUL << LCD_PAL110_B04_0_Pos)                          /*!< LCD PAL110: B04_0 Mask              */
+#define LCD_PAL110_I0_Pos                                     15                                                        /*!< LCD PAL110: I0 Position             */
+#define LCD_PAL110_I0_Msk                                     (0x01UL << LCD_PAL110_I0_Pos)                             /*!< LCD PAL110: I0 Mask                 */
+#define LCD_PAL110_R14_0_Pos                                  16                                                        /*!< LCD PAL110: R14_0 Position          */
+#define LCD_PAL110_R14_0_Msk                                  (0x1fUL << LCD_PAL110_R14_0_Pos)                          /*!< LCD PAL110: R14_0 Mask              */
+#define LCD_PAL110_G14_0_Pos                                  21                                                        /*!< LCD PAL110: G14_0 Position          */
+#define LCD_PAL110_G14_0_Msk                                  (0x1fUL << LCD_PAL110_G14_0_Pos)                          /*!< LCD PAL110: G14_0 Mask              */
+#define LCD_PAL110_B14_0_Pos                                  26                                                        /*!< LCD PAL110: B14_0 Position          */
+#define LCD_PAL110_B14_0_Msk                                  (0x1fUL << LCD_PAL110_B14_0_Pos)                          /*!< LCD PAL110: B14_0 Mask              */
+#define LCD_PAL110_I1_Pos                                     31                                                        /*!< LCD PAL110: I1 Position             */
+#define LCD_PAL110_I1_Msk                                     (0x01UL << LCD_PAL110_I1_Pos)                             /*!< LCD PAL110: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL111  -------------------------------------------
+#define LCD_PAL111_R04_0_Pos                                  0                                                         /*!< LCD PAL111: R04_0 Position          */
+#define LCD_PAL111_R04_0_Msk                                  (0x1fUL << LCD_PAL111_R04_0_Pos)                          /*!< LCD PAL111: R04_0 Mask              */
+#define LCD_PAL111_G04_0_Pos                                  5                                                         /*!< LCD PAL111: G04_0 Position          */
+#define LCD_PAL111_G04_0_Msk                                  (0x1fUL << LCD_PAL111_G04_0_Pos)                          /*!< LCD PAL111: G04_0 Mask              */
+#define LCD_PAL111_B04_0_Pos                                  10                                                        /*!< LCD PAL111: B04_0 Position          */
+#define LCD_PAL111_B04_0_Msk                                  (0x1fUL << LCD_PAL111_B04_0_Pos)                          /*!< LCD PAL111: B04_0 Mask              */
+#define LCD_PAL111_I0_Pos                                     15                                                        /*!< LCD PAL111: I0 Position             */
+#define LCD_PAL111_I0_Msk                                     (0x01UL << LCD_PAL111_I0_Pos)                             /*!< LCD PAL111: I0 Mask                 */
+#define LCD_PAL111_R14_0_Pos                                  16                                                        /*!< LCD PAL111: R14_0 Position          */
+#define LCD_PAL111_R14_0_Msk                                  (0x1fUL << LCD_PAL111_R14_0_Pos)                          /*!< LCD PAL111: R14_0 Mask              */
+#define LCD_PAL111_G14_0_Pos                                  21                                                        /*!< LCD PAL111: G14_0 Position          */
+#define LCD_PAL111_G14_0_Msk                                  (0x1fUL << LCD_PAL111_G14_0_Pos)                          /*!< LCD PAL111: G14_0 Mask              */
+#define LCD_PAL111_B14_0_Pos                                  26                                                        /*!< LCD PAL111: B14_0 Position          */
+#define LCD_PAL111_B14_0_Msk                                  (0x1fUL << LCD_PAL111_B14_0_Pos)                          /*!< LCD PAL111: B14_0 Mask              */
+#define LCD_PAL111_I1_Pos                                     31                                                        /*!< LCD PAL111: I1 Position             */
+#define LCD_PAL111_I1_Msk                                     (0x01UL << LCD_PAL111_I1_Pos)                             /*!< LCD PAL111: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL112  -------------------------------------------
+#define LCD_PAL112_R04_0_Pos                                  0                                                         /*!< LCD PAL112: R04_0 Position          */
+#define LCD_PAL112_R04_0_Msk                                  (0x1fUL << LCD_PAL112_R04_0_Pos)                          /*!< LCD PAL112: R04_0 Mask              */
+#define LCD_PAL112_G04_0_Pos                                  5                                                         /*!< LCD PAL112: G04_0 Position          */
+#define LCD_PAL112_G04_0_Msk                                  (0x1fUL << LCD_PAL112_G04_0_Pos)                          /*!< LCD PAL112: G04_0 Mask              */
+#define LCD_PAL112_B04_0_Pos                                  10                                                        /*!< LCD PAL112: B04_0 Position          */
+#define LCD_PAL112_B04_0_Msk                                  (0x1fUL << LCD_PAL112_B04_0_Pos)                          /*!< LCD PAL112: B04_0 Mask              */
+#define LCD_PAL112_I0_Pos                                     15                                                        /*!< LCD PAL112: I0 Position             */
+#define LCD_PAL112_I0_Msk                                     (0x01UL << LCD_PAL112_I0_Pos)                             /*!< LCD PAL112: I0 Mask                 */
+#define LCD_PAL112_R14_0_Pos                                  16                                                        /*!< LCD PAL112: R14_0 Position          */
+#define LCD_PAL112_R14_0_Msk                                  (0x1fUL << LCD_PAL112_R14_0_Pos)                          /*!< LCD PAL112: R14_0 Mask              */
+#define LCD_PAL112_G14_0_Pos                                  21                                                        /*!< LCD PAL112: G14_0 Position          */
+#define LCD_PAL112_G14_0_Msk                                  (0x1fUL << LCD_PAL112_G14_0_Pos)                          /*!< LCD PAL112: G14_0 Mask              */
+#define LCD_PAL112_B14_0_Pos                                  26                                                        /*!< LCD PAL112: B14_0 Position          */
+#define LCD_PAL112_B14_0_Msk                                  (0x1fUL << LCD_PAL112_B14_0_Pos)                          /*!< LCD PAL112: B14_0 Mask              */
+#define LCD_PAL112_I1_Pos                                     31                                                        /*!< LCD PAL112: I1 Position             */
+#define LCD_PAL112_I1_Msk                                     (0x01UL << LCD_PAL112_I1_Pos)                             /*!< LCD PAL112: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL113  -------------------------------------------
+#define LCD_PAL113_R04_0_Pos                                  0                                                         /*!< LCD PAL113: R04_0 Position          */
+#define LCD_PAL113_R04_0_Msk                                  (0x1fUL << LCD_PAL113_R04_0_Pos)                          /*!< LCD PAL113: R04_0 Mask              */
+#define LCD_PAL113_G04_0_Pos                                  5                                                         /*!< LCD PAL113: G04_0 Position          */
+#define LCD_PAL113_G04_0_Msk                                  (0x1fUL << LCD_PAL113_G04_0_Pos)                          /*!< LCD PAL113: G04_0 Mask              */
+#define LCD_PAL113_B04_0_Pos                                  10                                                        /*!< LCD PAL113: B04_0 Position          */
+#define LCD_PAL113_B04_0_Msk                                  (0x1fUL << LCD_PAL113_B04_0_Pos)                          /*!< LCD PAL113: B04_0 Mask              */
+#define LCD_PAL113_I0_Pos                                     15                                                        /*!< LCD PAL113: I0 Position             */
+#define LCD_PAL113_I0_Msk                                     (0x01UL << LCD_PAL113_I0_Pos)                             /*!< LCD PAL113: I0 Mask                 */
+#define LCD_PAL113_R14_0_Pos                                  16                                                        /*!< LCD PAL113: R14_0 Position          */
+#define LCD_PAL113_R14_0_Msk                                  (0x1fUL << LCD_PAL113_R14_0_Pos)                          /*!< LCD PAL113: R14_0 Mask              */
+#define LCD_PAL113_G14_0_Pos                                  21                                                        /*!< LCD PAL113: G14_0 Position          */
+#define LCD_PAL113_G14_0_Msk                                  (0x1fUL << LCD_PAL113_G14_0_Pos)                          /*!< LCD PAL113: G14_0 Mask              */
+#define LCD_PAL113_B14_0_Pos                                  26                                                        /*!< LCD PAL113: B14_0 Position          */
+#define LCD_PAL113_B14_0_Msk                                  (0x1fUL << LCD_PAL113_B14_0_Pos)                          /*!< LCD PAL113: B14_0 Mask              */
+#define LCD_PAL113_I1_Pos                                     31                                                        /*!< LCD PAL113: I1 Position             */
+#define LCD_PAL113_I1_Msk                                     (0x01UL << LCD_PAL113_I1_Pos)                             /*!< LCD PAL113: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL114  -------------------------------------------
+#define LCD_PAL114_R04_0_Pos                                  0                                                         /*!< LCD PAL114: R04_0 Position          */
+#define LCD_PAL114_R04_0_Msk                                  (0x1fUL << LCD_PAL114_R04_0_Pos)                          /*!< LCD PAL114: R04_0 Mask              */
+#define LCD_PAL114_G04_0_Pos                                  5                                                         /*!< LCD PAL114: G04_0 Position          */
+#define LCD_PAL114_G04_0_Msk                                  (0x1fUL << LCD_PAL114_G04_0_Pos)                          /*!< LCD PAL114: G04_0 Mask              */
+#define LCD_PAL114_B04_0_Pos                                  10                                                        /*!< LCD PAL114: B04_0 Position          */
+#define LCD_PAL114_B04_0_Msk                                  (0x1fUL << LCD_PAL114_B04_0_Pos)                          /*!< LCD PAL114: B04_0 Mask              */
+#define LCD_PAL114_I0_Pos                                     15                                                        /*!< LCD PAL114: I0 Position             */
+#define LCD_PAL114_I0_Msk                                     (0x01UL << LCD_PAL114_I0_Pos)                             /*!< LCD PAL114: I0 Mask                 */
+#define LCD_PAL114_R14_0_Pos                                  16                                                        /*!< LCD PAL114: R14_0 Position          */
+#define LCD_PAL114_R14_0_Msk                                  (0x1fUL << LCD_PAL114_R14_0_Pos)                          /*!< LCD PAL114: R14_0 Mask              */
+#define LCD_PAL114_G14_0_Pos                                  21                                                        /*!< LCD PAL114: G14_0 Position          */
+#define LCD_PAL114_G14_0_Msk                                  (0x1fUL << LCD_PAL114_G14_0_Pos)                          /*!< LCD PAL114: G14_0 Mask              */
+#define LCD_PAL114_B14_0_Pos                                  26                                                        /*!< LCD PAL114: B14_0 Position          */
+#define LCD_PAL114_B14_0_Msk                                  (0x1fUL << LCD_PAL114_B14_0_Pos)                          /*!< LCD PAL114: B14_0 Mask              */
+#define LCD_PAL114_I1_Pos                                     31                                                        /*!< LCD PAL114: I1 Position             */
+#define LCD_PAL114_I1_Msk                                     (0x01UL << LCD_PAL114_I1_Pos)                             /*!< LCD PAL114: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL115  -------------------------------------------
+#define LCD_PAL115_R04_0_Pos                                  0                                                         /*!< LCD PAL115: R04_0 Position          */
+#define LCD_PAL115_R04_0_Msk                                  (0x1fUL << LCD_PAL115_R04_0_Pos)                          /*!< LCD PAL115: R04_0 Mask              */
+#define LCD_PAL115_G04_0_Pos                                  5                                                         /*!< LCD PAL115: G04_0 Position          */
+#define LCD_PAL115_G04_0_Msk                                  (0x1fUL << LCD_PAL115_G04_0_Pos)                          /*!< LCD PAL115: G04_0 Mask              */
+#define LCD_PAL115_B04_0_Pos                                  10                                                        /*!< LCD PAL115: B04_0 Position          */
+#define LCD_PAL115_B04_0_Msk                                  (0x1fUL << LCD_PAL115_B04_0_Pos)                          /*!< LCD PAL115: B04_0 Mask              */
+#define LCD_PAL115_I0_Pos                                     15                                                        /*!< LCD PAL115: I0 Position             */
+#define LCD_PAL115_I0_Msk                                     (0x01UL << LCD_PAL115_I0_Pos)                             /*!< LCD PAL115: I0 Mask                 */
+#define LCD_PAL115_R14_0_Pos                                  16                                                        /*!< LCD PAL115: R14_0 Position          */
+#define LCD_PAL115_R14_0_Msk                                  (0x1fUL << LCD_PAL115_R14_0_Pos)                          /*!< LCD PAL115: R14_0 Mask              */
+#define LCD_PAL115_G14_0_Pos                                  21                                                        /*!< LCD PAL115: G14_0 Position          */
+#define LCD_PAL115_G14_0_Msk                                  (0x1fUL << LCD_PAL115_G14_0_Pos)                          /*!< LCD PAL115: G14_0 Mask              */
+#define LCD_PAL115_B14_0_Pos                                  26                                                        /*!< LCD PAL115: B14_0 Position          */
+#define LCD_PAL115_B14_0_Msk                                  (0x1fUL << LCD_PAL115_B14_0_Pos)                          /*!< LCD PAL115: B14_0 Mask              */
+#define LCD_PAL115_I1_Pos                                     31                                                        /*!< LCD PAL115: I1 Position             */
+#define LCD_PAL115_I1_Msk                                     (0x01UL << LCD_PAL115_I1_Pos)                             /*!< LCD PAL115: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL116  -------------------------------------------
+#define LCD_PAL116_R04_0_Pos                                  0                                                         /*!< LCD PAL116: R04_0 Position          */
+#define LCD_PAL116_R04_0_Msk                                  (0x1fUL << LCD_PAL116_R04_0_Pos)                          /*!< LCD PAL116: R04_0 Mask              */
+#define LCD_PAL116_G04_0_Pos                                  5                                                         /*!< LCD PAL116: G04_0 Position          */
+#define LCD_PAL116_G04_0_Msk                                  (0x1fUL << LCD_PAL116_G04_0_Pos)                          /*!< LCD PAL116: G04_0 Mask              */
+#define LCD_PAL116_B04_0_Pos                                  10                                                        /*!< LCD PAL116: B04_0 Position          */
+#define LCD_PAL116_B04_0_Msk                                  (0x1fUL << LCD_PAL116_B04_0_Pos)                          /*!< LCD PAL116: B04_0 Mask              */
+#define LCD_PAL116_I0_Pos                                     15                                                        /*!< LCD PAL116: I0 Position             */
+#define LCD_PAL116_I0_Msk                                     (0x01UL << LCD_PAL116_I0_Pos)                             /*!< LCD PAL116: I0 Mask                 */
+#define LCD_PAL116_R14_0_Pos                                  16                                                        /*!< LCD PAL116: R14_0 Position          */
+#define LCD_PAL116_R14_0_Msk                                  (0x1fUL << LCD_PAL116_R14_0_Pos)                          /*!< LCD PAL116: R14_0 Mask              */
+#define LCD_PAL116_G14_0_Pos                                  21                                                        /*!< LCD PAL116: G14_0 Position          */
+#define LCD_PAL116_G14_0_Msk                                  (0x1fUL << LCD_PAL116_G14_0_Pos)                          /*!< LCD PAL116: G14_0 Mask              */
+#define LCD_PAL116_B14_0_Pos                                  26                                                        /*!< LCD PAL116: B14_0 Position          */
+#define LCD_PAL116_B14_0_Msk                                  (0x1fUL << LCD_PAL116_B14_0_Pos)                          /*!< LCD PAL116: B14_0 Mask              */
+#define LCD_PAL116_I1_Pos                                     31                                                        /*!< LCD PAL116: I1 Position             */
+#define LCD_PAL116_I1_Msk                                     (0x01UL << LCD_PAL116_I1_Pos)                             /*!< LCD PAL116: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL117  -------------------------------------------
+#define LCD_PAL117_R04_0_Pos                                  0                                                         /*!< LCD PAL117: R04_0 Position          */
+#define LCD_PAL117_R04_0_Msk                                  (0x1fUL << LCD_PAL117_R04_0_Pos)                          /*!< LCD PAL117: R04_0 Mask              */
+#define LCD_PAL117_G04_0_Pos                                  5                                                         /*!< LCD PAL117: G04_0 Position          */
+#define LCD_PAL117_G04_0_Msk                                  (0x1fUL << LCD_PAL117_G04_0_Pos)                          /*!< LCD PAL117: G04_0 Mask              */
+#define LCD_PAL117_B04_0_Pos                                  10                                                        /*!< LCD PAL117: B04_0 Position          */
+#define LCD_PAL117_B04_0_Msk                                  (0x1fUL << LCD_PAL117_B04_0_Pos)                          /*!< LCD PAL117: B04_0 Mask              */
+#define LCD_PAL117_I0_Pos                                     15                                                        /*!< LCD PAL117: I0 Position             */
+#define LCD_PAL117_I0_Msk                                     (0x01UL << LCD_PAL117_I0_Pos)                             /*!< LCD PAL117: I0 Mask                 */
+#define LCD_PAL117_R14_0_Pos                                  16                                                        /*!< LCD PAL117: R14_0 Position          */
+#define LCD_PAL117_R14_0_Msk                                  (0x1fUL << LCD_PAL117_R14_0_Pos)                          /*!< LCD PAL117: R14_0 Mask              */
+#define LCD_PAL117_G14_0_Pos                                  21                                                        /*!< LCD PAL117: G14_0 Position          */
+#define LCD_PAL117_G14_0_Msk                                  (0x1fUL << LCD_PAL117_G14_0_Pos)                          /*!< LCD PAL117: G14_0 Mask              */
+#define LCD_PAL117_B14_0_Pos                                  26                                                        /*!< LCD PAL117: B14_0 Position          */
+#define LCD_PAL117_B14_0_Msk                                  (0x1fUL << LCD_PAL117_B14_0_Pos)                          /*!< LCD PAL117: B14_0 Mask              */
+#define LCD_PAL117_I1_Pos                                     31                                                        /*!< LCD PAL117: I1 Position             */
+#define LCD_PAL117_I1_Msk                                     (0x01UL << LCD_PAL117_I1_Pos)                             /*!< LCD PAL117: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL118  -------------------------------------------
+#define LCD_PAL118_R04_0_Pos                                  0                                                         /*!< LCD PAL118: R04_0 Position          */
+#define LCD_PAL118_R04_0_Msk                                  (0x1fUL << LCD_PAL118_R04_0_Pos)                          /*!< LCD PAL118: R04_0 Mask              */
+#define LCD_PAL118_G04_0_Pos                                  5                                                         /*!< LCD PAL118: G04_0 Position          */
+#define LCD_PAL118_G04_0_Msk                                  (0x1fUL << LCD_PAL118_G04_0_Pos)                          /*!< LCD PAL118: G04_0 Mask              */
+#define LCD_PAL118_B04_0_Pos                                  10                                                        /*!< LCD PAL118: B04_0 Position          */
+#define LCD_PAL118_B04_0_Msk                                  (0x1fUL << LCD_PAL118_B04_0_Pos)                          /*!< LCD PAL118: B04_0 Mask              */
+#define LCD_PAL118_I0_Pos                                     15                                                        /*!< LCD PAL118: I0 Position             */
+#define LCD_PAL118_I0_Msk                                     (0x01UL << LCD_PAL118_I0_Pos)                             /*!< LCD PAL118: I0 Mask                 */
+#define LCD_PAL118_R14_0_Pos                                  16                                                        /*!< LCD PAL118: R14_0 Position          */
+#define LCD_PAL118_R14_0_Msk                                  (0x1fUL << LCD_PAL118_R14_0_Pos)                          /*!< LCD PAL118: R14_0 Mask              */
+#define LCD_PAL118_G14_0_Pos                                  21                                                        /*!< LCD PAL118: G14_0 Position          */
+#define LCD_PAL118_G14_0_Msk                                  (0x1fUL << LCD_PAL118_G14_0_Pos)                          /*!< LCD PAL118: G14_0 Mask              */
+#define LCD_PAL118_B14_0_Pos                                  26                                                        /*!< LCD PAL118: B14_0 Position          */
+#define LCD_PAL118_B14_0_Msk                                  (0x1fUL << LCD_PAL118_B14_0_Pos)                          /*!< LCD PAL118: B14_0 Mask              */
+#define LCD_PAL118_I1_Pos                                     31                                                        /*!< LCD PAL118: I1 Position             */
+#define LCD_PAL118_I1_Msk                                     (0x01UL << LCD_PAL118_I1_Pos)                             /*!< LCD PAL118: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL119  -------------------------------------------
+#define LCD_PAL119_R04_0_Pos                                  0                                                         /*!< LCD PAL119: R04_0 Position          */
+#define LCD_PAL119_R04_0_Msk                                  (0x1fUL << LCD_PAL119_R04_0_Pos)                          /*!< LCD PAL119: R04_0 Mask              */
+#define LCD_PAL119_G04_0_Pos                                  5                                                         /*!< LCD PAL119: G04_0 Position          */
+#define LCD_PAL119_G04_0_Msk                                  (0x1fUL << LCD_PAL119_G04_0_Pos)                          /*!< LCD PAL119: G04_0 Mask              */
+#define LCD_PAL119_B04_0_Pos                                  10                                                        /*!< LCD PAL119: B04_0 Position          */
+#define LCD_PAL119_B04_0_Msk                                  (0x1fUL << LCD_PAL119_B04_0_Pos)                          /*!< LCD PAL119: B04_0 Mask              */
+#define LCD_PAL119_I0_Pos                                     15                                                        /*!< LCD PAL119: I0 Position             */
+#define LCD_PAL119_I0_Msk                                     (0x01UL << LCD_PAL119_I0_Pos)                             /*!< LCD PAL119: I0 Mask                 */
+#define LCD_PAL119_R14_0_Pos                                  16                                                        /*!< LCD PAL119: R14_0 Position          */
+#define LCD_PAL119_R14_0_Msk                                  (0x1fUL << LCD_PAL119_R14_0_Pos)                          /*!< LCD PAL119: R14_0 Mask              */
+#define LCD_PAL119_G14_0_Pos                                  21                                                        /*!< LCD PAL119: G14_0 Position          */
+#define LCD_PAL119_G14_0_Msk                                  (0x1fUL << LCD_PAL119_G14_0_Pos)                          /*!< LCD PAL119: G14_0 Mask              */
+#define LCD_PAL119_B14_0_Pos                                  26                                                        /*!< LCD PAL119: B14_0 Position          */
+#define LCD_PAL119_B14_0_Msk                                  (0x1fUL << LCD_PAL119_B14_0_Pos)                          /*!< LCD PAL119: B14_0 Mask              */
+#define LCD_PAL119_I1_Pos                                     31                                                        /*!< LCD PAL119: I1 Position             */
+#define LCD_PAL119_I1_Msk                                     (0x01UL << LCD_PAL119_I1_Pos)                             /*!< LCD PAL119: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL120  -------------------------------------------
+#define LCD_PAL120_R04_0_Pos                                  0                                                         /*!< LCD PAL120: R04_0 Position          */
+#define LCD_PAL120_R04_0_Msk                                  (0x1fUL << LCD_PAL120_R04_0_Pos)                          /*!< LCD PAL120: R04_0 Mask              */
+#define LCD_PAL120_G04_0_Pos                                  5                                                         /*!< LCD PAL120: G04_0 Position          */
+#define LCD_PAL120_G04_0_Msk                                  (0x1fUL << LCD_PAL120_G04_0_Pos)                          /*!< LCD PAL120: G04_0 Mask              */
+#define LCD_PAL120_B04_0_Pos                                  10                                                        /*!< LCD PAL120: B04_0 Position          */
+#define LCD_PAL120_B04_0_Msk                                  (0x1fUL << LCD_PAL120_B04_0_Pos)                          /*!< LCD PAL120: B04_0 Mask              */
+#define LCD_PAL120_I0_Pos                                     15                                                        /*!< LCD PAL120: I0 Position             */
+#define LCD_PAL120_I0_Msk                                     (0x01UL << LCD_PAL120_I0_Pos)                             /*!< LCD PAL120: I0 Mask                 */
+#define LCD_PAL120_R14_0_Pos                                  16                                                        /*!< LCD PAL120: R14_0 Position          */
+#define LCD_PAL120_R14_0_Msk                                  (0x1fUL << LCD_PAL120_R14_0_Pos)                          /*!< LCD PAL120: R14_0 Mask              */
+#define LCD_PAL120_G14_0_Pos                                  21                                                        /*!< LCD PAL120: G14_0 Position          */
+#define LCD_PAL120_G14_0_Msk                                  (0x1fUL << LCD_PAL120_G14_0_Pos)                          /*!< LCD PAL120: G14_0 Mask              */
+#define LCD_PAL120_B14_0_Pos                                  26                                                        /*!< LCD PAL120: B14_0 Position          */
+#define LCD_PAL120_B14_0_Msk                                  (0x1fUL << LCD_PAL120_B14_0_Pos)                          /*!< LCD PAL120: B14_0 Mask              */
+#define LCD_PAL120_I1_Pos                                     31                                                        /*!< LCD PAL120: I1 Position             */
+#define LCD_PAL120_I1_Msk                                     (0x01UL << LCD_PAL120_I1_Pos)                             /*!< LCD PAL120: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL121  -------------------------------------------
+#define LCD_PAL121_R04_0_Pos                                  0                                                         /*!< LCD PAL121: R04_0 Position          */
+#define LCD_PAL121_R04_0_Msk                                  (0x1fUL << LCD_PAL121_R04_0_Pos)                          /*!< LCD PAL121: R04_0 Mask              */
+#define LCD_PAL121_G04_0_Pos                                  5                                                         /*!< LCD PAL121: G04_0 Position          */
+#define LCD_PAL121_G04_0_Msk                                  (0x1fUL << LCD_PAL121_G04_0_Pos)                          /*!< LCD PAL121: G04_0 Mask              */
+#define LCD_PAL121_B04_0_Pos                                  10                                                        /*!< LCD PAL121: B04_0 Position          */
+#define LCD_PAL121_B04_0_Msk                                  (0x1fUL << LCD_PAL121_B04_0_Pos)                          /*!< LCD PAL121: B04_0 Mask              */
+#define LCD_PAL121_I0_Pos                                     15                                                        /*!< LCD PAL121: I0 Position             */
+#define LCD_PAL121_I0_Msk                                     (0x01UL << LCD_PAL121_I0_Pos)                             /*!< LCD PAL121: I0 Mask                 */
+#define LCD_PAL121_R14_0_Pos                                  16                                                        /*!< LCD PAL121: R14_0 Position          */
+#define LCD_PAL121_R14_0_Msk                                  (0x1fUL << LCD_PAL121_R14_0_Pos)                          /*!< LCD PAL121: R14_0 Mask              */
+#define LCD_PAL121_G14_0_Pos                                  21                                                        /*!< LCD PAL121: G14_0 Position          */
+#define LCD_PAL121_G14_0_Msk                                  (0x1fUL << LCD_PAL121_G14_0_Pos)                          /*!< LCD PAL121: G14_0 Mask              */
+#define LCD_PAL121_B14_0_Pos                                  26                                                        /*!< LCD PAL121: B14_0 Position          */
+#define LCD_PAL121_B14_0_Msk                                  (0x1fUL << LCD_PAL121_B14_0_Pos)                          /*!< LCD PAL121: B14_0 Mask              */
+#define LCD_PAL121_I1_Pos                                     31                                                        /*!< LCD PAL121: I1 Position             */
+#define LCD_PAL121_I1_Msk                                     (0x01UL << LCD_PAL121_I1_Pos)                             /*!< LCD PAL121: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL122  -------------------------------------------
+#define LCD_PAL122_R04_0_Pos                                  0                                                         /*!< LCD PAL122: R04_0 Position          */
+#define LCD_PAL122_R04_0_Msk                                  (0x1fUL << LCD_PAL122_R04_0_Pos)                          /*!< LCD PAL122: R04_0 Mask              */
+#define LCD_PAL122_G04_0_Pos                                  5                                                         /*!< LCD PAL122: G04_0 Position          */
+#define LCD_PAL122_G04_0_Msk                                  (0x1fUL << LCD_PAL122_G04_0_Pos)                          /*!< LCD PAL122: G04_0 Mask              */
+#define LCD_PAL122_B04_0_Pos                                  10                                                        /*!< LCD PAL122: B04_0 Position          */
+#define LCD_PAL122_B04_0_Msk                                  (0x1fUL << LCD_PAL122_B04_0_Pos)                          /*!< LCD PAL122: B04_0 Mask              */
+#define LCD_PAL122_I0_Pos                                     15                                                        /*!< LCD PAL122: I0 Position             */
+#define LCD_PAL122_I0_Msk                                     (0x01UL << LCD_PAL122_I0_Pos)                             /*!< LCD PAL122: I0 Mask                 */
+#define LCD_PAL122_R14_0_Pos                                  16                                                        /*!< LCD PAL122: R14_0 Position          */
+#define LCD_PAL122_R14_0_Msk                                  (0x1fUL << LCD_PAL122_R14_0_Pos)                          /*!< LCD PAL122: R14_0 Mask              */
+#define LCD_PAL122_G14_0_Pos                                  21                                                        /*!< LCD PAL122: G14_0 Position          */
+#define LCD_PAL122_G14_0_Msk                                  (0x1fUL << LCD_PAL122_G14_0_Pos)                          /*!< LCD PAL122: G14_0 Mask              */
+#define LCD_PAL122_B14_0_Pos                                  26                                                        /*!< LCD PAL122: B14_0 Position          */
+#define LCD_PAL122_B14_0_Msk                                  (0x1fUL << LCD_PAL122_B14_0_Pos)                          /*!< LCD PAL122: B14_0 Mask              */
+#define LCD_PAL122_I1_Pos                                     31                                                        /*!< LCD PAL122: I1 Position             */
+#define LCD_PAL122_I1_Msk                                     (0x01UL << LCD_PAL122_I1_Pos)                             /*!< LCD PAL122: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL123  -------------------------------------------
+#define LCD_PAL123_R04_0_Pos                                  0                                                         /*!< LCD PAL123: R04_0 Position          */
+#define LCD_PAL123_R04_0_Msk                                  (0x1fUL << LCD_PAL123_R04_0_Pos)                          /*!< LCD PAL123: R04_0 Mask              */
+#define LCD_PAL123_G04_0_Pos                                  5                                                         /*!< LCD PAL123: G04_0 Position          */
+#define LCD_PAL123_G04_0_Msk                                  (0x1fUL << LCD_PAL123_G04_0_Pos)                          /*!< LCD PAL123: G04_0 Mask              */
+#define LCD_PAL123_B04_0_Pos                                  10                                                        /*!< LCD PAL123: B04_0 Position          */
+#define LCD_PAL123_B04_0_Msk                                  (0x1fUL << LCD_PAL123_B04_0_Pos)                          /*!< LCD PAL123: B04_0 Mask              */
+#define LCD_PAL123_I0_Pos                                     15                                                        /*!< LCD PAL123: I0 Position             */
+#define LCD_PAL123_I0_Msk                                     (0x01UL << LCD_PAL123_I0_Pos)                             /*!< LCD PAL123: I0 Mask                 */
+#define LCD_PAL123_R14_0_Pos                                  16                                                        /*!< LCD PAL123: R14_0 Position          */
+#define LCD_PAL123_R14_0_Msk                                  (0x1fUL << LCD_PAL123_R14_0_Pos)                          /*!< LCD PAL123: R14_0 Mask              */
+#define LCD_PAL123_G14_0_Pos                                  21                                                        /*!< LCD PAL123: G14_0 Position          */
+#define LCD_PAL123_G14_0_Msk                                  (0x1fUL << LCD_PAL123_G14_0_Pos)                          /*!< LCD PAL123: G14_0 Mask              */
+#define LCD_PAL123_B14_0_Pos                                  26                                                        /*!< LCD PAL123: B14_0 Position          */
+#define LCD_PAL123_B14_0_Msk                                  (0x1fUL << LCD_PAL123_B14_0_Pos)                          /*!< LCD PAL123: B14_0 Mask              */
+#define LCD_PAL123_I1_Pos                                     31                                                        /*!< LCD PAL123: I1 Position             */
+#define LCD_PAL123_I1_Msk                                     (0x01UL << LCD_PAL123_I1_Pos)                             /*!< LCD PAL123: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL124  -------------------------------------------
+#define LCD_PAL124_R04_0_Pos                                  0                                                         /*!< LCD PAL124: R04_0 Position          */
+#define LCD_PAL124_R04_0_Msk                                  (0x1fUL << LCD_PAL124_R04_0_Pos)                          /*!< LCD PAL124: R04_0 Mask              */
+#define LCD_PAL124_G04_0_Pos                                  5                                                         /*!< LCD PAL124: G04_0 Position          */
+#define LCD_PAL124_G04_0_Msk                                  (0x1fUL << LCD_PAL124_G04_0_Pos)                          /*!< LCD PAL124: G04_0 Mask              */
+#define LCD_PAL124_B04_0_Pos                                  10                                                        /*!< LCD PAL124: B04_0 Position          */
+#define LCD_PAL124_B04_0_Msk                                  (0x1fUL << LCD_PAL124_B04_0_Pos)                          /*!< LCD PAL124: B04_0 Mask              */
+#define LCD_PAL124_I0_Pos                                     15                                                        /*!< LCD PAL124: I0 Position             */
+#define LCD_PAL124_I0_Msk                                     (0x01UL << LCD_PAL124_I0_Pos)                             /*!< LCD PAL124: I0 Mask                 */
+#define LCD_PAL124_R14_0_Pos                                  16                                                        /*!< LCD PAL124: R14_0 Position          */
+#define LCD_PAL124_R14_0_Msk                                  (0x1fUL << LCD_PAL124_R14_0_Pos)                          /*!< LCD PAL124: R14_0 Mask              */
+#define LCD_PAL124_G14_0_Pos                                  21                                                        /*!< LCD PAL124: G14_0 Position          */
+#define LCD_PAL124_G14_0_Msk                                  (0x1fUL << LCD_PAL124_G14_0_Pos)                          /*!< LCD PAL124: G14_0 Mask              */
+#define LCD_PAL124_B14_0_Pos                                  26                                                        /*!< LCD PAL124: B14_0 Position          */
+#define LCD_PAL124_B14_0_Msk                                  (0x1fUL << LCD_PAL124_B14_0_Pos)                          /*!< LCD PAL124: B14_0 Mask              */
+#define LCD_PAL124_I1_Pos                                     31                                                        /*!< LCD PAL124: I1 Position             */
+#define LCD_PAL124_I1_Msk                                     (0x01UL << LCD_PAL124_I1_Pos)                             /*!< LCD PAL124: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL125  -------------------------------------------
+#define LCD_PAL125_R04_0_Pos                                  0                                                         /*!< LCD PAL125: R04_0 Position          */
+#define LCD_PAL125_R04_0_Msk                                  (0x1fUL << LCD_PAL125_R04_0_Pos)                          /*!< LCD PAL125: R04_0 Mask              */
+#define LCD_PAL125_G04_0_Pos                                  5                                                         /*!< LCD PAL125: G04_0 Position          */
+#define LCD_PAL125_G04_0_Msk                                  (0x1fUL << LCD_PAL125_G04_0_Pos)                          /*!< LCD PAL125: G04_0 Mask              */
+#define LCD_PAL125_B04_0_Pos                                  10                                                        /*!< LCD PAL125: B04_0 Position          */
+#define LCD_PAL125_B04_0_Msk                                  (0x1fUL << LCD_PAL125_B04_0_Pos)                          /*!< LCD PAL125: B04_0 Mask              */
+#define LCD_PAL125_I0_Pos                                     15                                                        /*!< LCD PAL125: I0 Position             */
+#define LCD_PAL125_I0_Msk                                     (0x01UL << LCD_PAL125_I0_Pos)                             /*!< LCD PAL125: I0 Mask                 */
+#define LCD_PAL125_R14_0_Pos                                  16                                                        /*!< LCD PAL125: R14_0 Position          */
+#define LCD_PAL125_R14_0_Msk                                  (0x1fUL << LCD_PAL125_R14_0_Pos)                          /*!< LCD PAL125: R14_0 Mask              */
+#define LCD_PAL125_G14_0_Pos                                  21                                                        /*!< LCD PAL125: G14_0 Position          */
+#define LCD_PAL125_G14_0_Msk                                  (0x1fUL << LCD_PAL125_G14_0_Pos)                          /*!< LCD PAL125: G14_0 Mask              */
+#define LCD_PAL125_B14_0_Pos                                  26                                                        /*!< LCD PAL125: B14_0 Position          */
+#define LCD_PAL125_B14_0_Msk                                  (0x1fUL << LCD_PAL125_B14_0_Pos)                          /*!< LCD PAL125: B14_0 Mask              */
+#define LCD_PAL125_I1_Pos                                     31                                                        /*!< LCD PAL125: I1 Position             */
+#define LCD_PAL125_I1_Msk                                     (0x01UL << LCD_PAL125_I1_Pos)                             /*!< LCD PAL125: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL126  -------------------------------------------
+#define LCD_PAL126_R04_0_Pos                                  0                                                         /*!< LCD PAL126: R04_0 Position          */
+#define LCD_PAL126_R04_0_Msk                                  (0x1fUL << LCD_PAL126_R04_0_Pos)                          /*!< LCD PAL126: R04_0 Mask              */
+#define LCD_PAL126_G04_0_Pos                                  5                                                         /*!< LCD PAL126: G04_0 Position          */
+#define LCD_PAL126_G04_0_Msk                                  (0x1fUL << LCD_PAL126_G04_0_Pos)                          /*!< LCD PAL126: G04_0 Mask              */
+#define LCD_PAL126_B04_0_Pos                                  10                                                        /*!< LCD PAL126: B04_0 Position          */
+#define LCD_PAL126_B04_0_Msk                                  (0x1fUL << LCD_PAL126_B04_0_Pos)                          /*!< LCD PAL126: B04_0 Mask              */
+#define LCD_PAL126_I0_Pos                                     15                                                        /*!< LCD PAL126: I0 Position             */
+#define LCD_PAL126_I0_Msk                                     (0x01UL << LCD_PAL126_I0_Pos)                             /*!< LCD PAL126: I0 Mask                 */
+#define LCD_PAL126_R14_0_Pos                                  16                                                        /*!< LCD PAL126: R14_0 Position          */
+#define LCD_PAL126_R14_0_Msk                                  (0x1fUL << LCD_PAL126_R14_0_Pos)                          /*!< LCD PAL126: R14_0 Mask              */
+#define LCD_PAL126_G14_0_Pos                                  21                                                        /*!< LCD PAL126: G14_0 Position          */
+#define LCD_PAL126_G14_0_Msk                                  (0x1fUL << LCD_PAL126_G14_0_Pos)                          /*!< LCD PAL126: G14_0 Mask              */
+#define LCD_PAL126_B14_0_Pos                                  26                                                        /*!< LCD PAL126: B14_0 Position          */
+#define LCD_PAL126_B14_0_Msk                                  (0x1fUL << LCD_PAL126_B14_0_Pos)                          /*!< LCD PAL126: B14_0 Mask              */
+#define LCD_PAL126_I1_Pos                                     31                                                        /*!< LCD PAL126: I1 Position             */
+#define LCD_PAL126_I1_Msk                                     (0x01UL << LCD_PAL126_I1_Pos)                             /*!< LCD PAL126: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL127  -------------------------------------------
+#define LCD_PAL127_R04_0_Pos                                  0                                                         /*!< LCD PAL127: R04_0 Position          */
+#define LCD_PAL127_R04_0_Msk                                  (0x1fUL << LCD_PAL127_R04_0_Pos)                          /*!< LCD PAL127: R04_0 Mask              */
+#define LCD_PAL127_G04_0_Pos                                  5                                                         /*!< LCD PAL127: G04_0 Position          */
+#define LCD_PAL127_G04_0_Msk                                  (0x1fUL << LCD_PAL127_G04_0_Pos)                          /*!< LCD PAL127: G04_0 Mask              */
+#define LCD_PAL127_B04_0_Pos                                  10                                                        /*!< LCD PAL127: B04_0 Position          */
+#define LCD_PAL127_B04_0_Msk                                  (0x1fUL << LCD_PAL127_B04_0_Pos)                          /*!< LCD PAL127: B04_0 Mask              */
+#define LCD_PAL127_I0_Pos                                     15                                                        /*!< LCD PAL127: I0 Position             */
+#define LCD_PAL127_I0_Msk                                     (0x01UL << LCD_PAL127_I0_Pos)                             /*!< LCD PAL127: I0 Mask                 */
+#define LCD_PAL127_R14_0_Pos                                  16                                                        /*!< LCD PAL127: R14_0 Position          */
+#define LCD_PAL127_R14_0_Msk                                  (0x1fUL << LCD_PAL127_R14_0_Pos)                          /*!< LCD PAL127: R14_0 Mask              */
+#define LCD_PAL127_G14_0_Pos                                  21                                                        /*!< LCD PAL127: G14_0 Position          */
+#define LCD_PAL127_G14_0_Msk                                  (0x1fUL << LCD_PAL127_G14_0_Pos)                          /*!< LCD PAL127: G14_0 Mask              */
+#define LCD_PAL127_B14_0_Pos                                  26                                                        /*!< LCD PAL127: B14_0 Position          */
+#define LCD_PAL127_B14_0_Msk                                  (0x1fUL << LCD_PAL127_B14_0_Pos)                          /*!< LCD PAL127: B14_0 Mask              */
+#define LCD_PAL127_I1_Pos                                     31                                                        /*!< LCD PAL127: I1 Position             */
+#define LCD_PAL127_I1_Msk                                     (0x01UL << LCD_PAL127_I1_Pos)                             /*!< LCD PAL127: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL128  -------------------------------------------
+#define LCD_PAL128_R04_0_Pos                                  0                                                         /*!< LCD PAL128: R04_0 Position          */
+#define LCD_PAL128_R04_0_Msk                                  (0x1fUL << LCD_PAL128_R04_0_Pos)                          /*!< LCD PAL128: R04_0 Mask              */
+#define LCD_PAL128_G04_0_Pos                                  5                                                         /*!< LCD PAL128: G04_0 Position          */
+#define LCD_PAL128_G04_0_Msk                                  (0x1fUL << LCD_PAL128_G04_0_Pos)                          /*!< LCD PAL128: G04_0 Mask              */
+#define LCD_PAL128_B04_0_Pos                                  10                                                        /*!< LCD PAL128: B04_0 Position          */
+#define LCD_PAL128_B04_0_Msk                                  (0x1fUL << LCD_PAL128_B04_0_Pos)                          /*!< LCD PAL128: B04_0 Mask              */
+#define LCD_PAL128_I0_Pos                                     15                                                        /*!< LCD PAL128: I0 Position             */
+#define LCD_PAL128_I0_Msk                                     (0x01UL << LCD_PAL128_I0_Pos)                             /*!< LCD PAL128: I0 Mask                 */
+#define LCD_PAL128_R14_0_Pos                                  16                                                        /*!< LCD PAL128: R14_0 Position          */
+#define LCD_PAL128_R14_0_Msk                                  (0x1fUL << LCD_PAL128_R14_0_Pos)                          /*!< LCD PAL128: R14_0 Mask              */
+#define LCD_PAL128_G14_0_Pos                                  21                                                        /*!< LCD PAL128: G14_0 Position          */
+#define LCD_PAL128_G14_0_Msk                                  (0x1fUL << LCD_PAL128_G14_0_Pos)                          /*!< LCD PAL128: G14_0 Mask              */
+#define LCD_PAL128_B14_0_Pos                                  26                                                        /*!< LCD PAL128: B14_0 Position          */
+#define LCD_PAL128_B14_0_Msk                                  (0x1fUL << LCD_PAL128_B14_0_Pos)                          /*!< LCD PAL128: B14_0 Mask              */
+#define LCD_PAL128_I1_Pos                                     31                                                        /*!< LCD PAL128: I1 Position             */
+#define LCD_PAL128_I1_Msk                                     (0x01UL << LCD_PAL128_I1_Pos)                             /*!< LCD PAL128: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL129  -------------------------------------------
+#define LCD_PAL129_R04_0_Pos                                  0                                                         /*!< LCD PAL129: R04_0 Position          */
+#define LCD_PAL129_R04_0_Msk                                  (0x1fUL << LCD_PAL129_R04_0_Pos)                          /*!< LCD PAL129: R04_0 Mask              */
+#define LCD_PAL129_G04_0_Pos                                  5                                                         /*!< LCD PAL129: G04_0 Position          */
+#define LCD_PAL129_G04_0_Msk                                  (0x1fUL << LCD_PAL129_G04_0_Pos)                          /*!< LCD PAL129: G04_0 Mask              */
+#define LCD_PAL129_B04_0_Pos                                  10                                                        /*!< LCD PAL129: B04_0 Position          */
+#define LCD_PAL129_B04_0_Msk                                  (0x1fUL << LCD_PAL129_B04_0_Pos)                          /*!< LCD PAL129: B04_0 Mask              */
+#define LCD_PAL129_I0_Pos                                     15                                                        /*!< LCD PAL129: I0 Position             */
+#define LCD_PAL129_I0_Msk                                     (0x01UL << LCD_PAL129_I0_Pos)                             /*!< LCD PAL129: I0 Mask                 */
+#define LCD_PAL129_R14_0_Pos                                  16                                                        /*!< LCD PAL129: R14_0 Position          */
+#define LCD_PAL129_R14_0_Msk                                  (0x1fUL << LCD_PAL129_R14_0_Pos)                          /*!< LCD PAL129: R14_0 Mask              */
+#define LCD_PAL129_G14_0_Pos                                  21                                                        /*!< LCD PAL129: G14_0 Position          */
+#define LCD_PAL129_G14_0_Msk                                  (0x1fUL << LCD_PAL129_G14_0_Pos)                          /*!< LCD PAL129: G14_0 Mask              */
+#define LCD_PAL129_B14_0_Pos                                  26                                                        /*!< LCD PAL129: B14_0 Position          */
+#define LCD_PAL129_B14_0_Msk                                  (0x1fUL << LCD_PAL129_B14_0_Pos)                          /*!< LCD PAL129: B14_0 Mask              */
+#define LCD_PAL129_I1_Pos                                     31                                                        /*!< LCD PAL129: I1 Position             */
+#define LCD_PAL129_I1_Msk                                     (0x01UL << LCD_PAL129_I1_Pos)                             /*!< LCD PAL129: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL130  -------------------------------------------
+#define LCD_PAL130_R04_0_Pos                                  0                                                         /*!< LCD PAL130: R04_0 Position          */
+#define LCD_PAL130_R04_0_Msk                                  (0x1fUL << LCD_PAL130_R04_0_Pos)                          /*!< LCD PAL130: R04_0 Mask              */
+#define LCD_PAL130_G04_0_Pos                                  5                                                         /*!< LCD PAL130: G04_0 Position          */
+#define LCD_PAL130_G04_0_Msk                                  (0x1fUL << LCD_PAL130_G04_0_Pos)                          /*!< LCD PAL130: G04_0 Mask              */
+#define LCD_PAL130_B04_0_Pos                                  10                                                        /*!< LCD PAL130: B04_0 Position          */
+#define LCD_PAL130_B04_0_Msk                                  (0x1fUL << LCD_PAL130_B04_0_Pos)                          /*!< LCD PAL130: B04_0 Mask              */
+#define LCD_PAL130_I0_Pos                                     15                                                        /*!< LCD PAL130: I0 Position             */
+#define LCD_PAL130_I0_Msk                                     (0x01UL << LCD_PAL130_I0_Pos)                             /*!< LCD PAL130: I0 Mask                 */
+#define LCD_PAL130_R14_0_Pos                                  16                                                        /*!< LCD PAL130: R14_0 Position          */
+#define LCD_PAL130_R14_0_Msk                                  (0x1fUL << LCD_PAL130_R14_0_Pos)                          /*!< LCD PAL130: R14_0 Mask              */
+#define LCD_PAL130_G14_0_Pos                                  21                                                        /*!< LCD PAL130: G14_0 Position          */
+#define LCD_PAL130_G14_0_Msk                                  (0x1fUL << LCD_PAL130_G14_0_Pos)                          /*!< LCD PAL130: G14_0 Mask              */
+#define LCD_PAL130_B14_0_Pos                                  26                                                        /*!< LCD PAL130: B14_0 Position          */
+#define LCD_PAL130_B14_0_Msk                                  (0x1fUL << LCD_PAL130_B14_0_Pos)                          /*!< LCD PAL130: B14_0 Mask              */
+#define LCD_PAL130_I1_Pos                                     31                                                        /*!< LCD PAL130: I1 Position             */
+#define LCD_PAL130_I1_Msk                                     (0x01UL << LCD_PAL130_I1_Pos)                             /*!< LCD PAL130: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL131  -------------------------------------------
+#define LCD_PAL131_R04_0_Pos                                  0                                                         /*!< LCD PAL131: R04_0 Position          */
+#define LCD_PAL131_R04_0_Msk                                  (0x1fUL << LCD_PAL131_R04_0_Pos)                          /*!< LCD PAL131: R04_0 Mask              */
+#define LCD_PAL131_G04_0_Pos                                  5                                                         /*!< LCD PAL131: G04_0 Position          */
+#define LCD_PAL131_G04_0_Msk                                  (0x1fUL << LCD_PAL131_G04_0_Pos)                          /*!< LCD PAL131: G04_0 Mask              */
+#define LCD_PAL131_B04_0_Pos                                  10                                                        /*!< LCD PAL131: B04_0 Position          */
+#define LCD_PAL131_B04_0_Msk                                  (0x1fUL << LCD_PAL131_B04_0_Pos)                          /*!< LCD PAL131: B04_0 Mask              */
+#define LCD_PAL131_I0_Pos                                     15                                                        /*!< LCD PAL131: I0 Position             */
+#define LCD_PAL131_I0_Msk                                     (0x01UL << LCD_PAL131_I0_Pos)                             /*!< LCD PAL131: I0 Mask                 */
+#define LCD_PAL131_R14_0_Pos                                  16                                                        /*!< LCD PAL131: R14_0 Position          */
+#define LCD_PAL131_R14_0_Msk                                  (0x1fUL << LCD_PAL131_R14_0_Pos)                          /*!< LCD PAL131: R14_0 Mask              */
+#define LCD_PAL131_G14_0_Pos                                  21                                                        /*!< LCD PAL131: G14_0 Position          */
+#define LCD_PAL131_G14_0_Msk                                  (0x1fUL << LCD_PAL131_G14_0_Pos)                          /*!< LCD PAL131: G14_0 Mask              */
+#define LCD_PAL131_B14_0_Pos                                  26                                                        /*!< LCD PAL131: B14_0 Position          */
+#define LCD_PAL131_B14_0_Msk                                  (0x1fUL << LCD_PAL131_B14_0_Pos)                          /*!< LCD PAL131: B14_0 Mask              */
+#define LCD_PAL131_I1_Pos                                     31                                                        /*!< LCD PAL131: I1 Position             */
+#define LCD_PAL131_I1_Msk                                     (0x01UL << LCD_PAL131_I1_Pos)                             /*!< LCD PAL131: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL132  -------------------------------------------
+#define LCD_PAL132_R04_0_Pos                                  0                                                         /*!< LCD PAL132: R04_0 Position          */
+#define LCD_PAL132_R04_0_Msk                                  (0x1fUL << LCD_PAL132_R04_0_Pos)                          /*!< LCD PAL132: R04_0 Mask              */
+#define LCD_PAL132_G04_0_Pos                                  5                                                         /*!< LCD PAL132: G04_0 Position          */
+#define LCD_PAL132_G04_0_Msk                                  (0x1fUL << LCD_PAL132_G04_0_Pos)                          /*!< LCD PAL132: G04_0 Mask              */
+#define LCD_PAL132_B04_0_Pos                                  10                                                        /*!< LCD PAL132: B04_0 Position          */
+#define LCD_PAL132_B04_0_Msk                                  (0x1fUL << LCD_PAL132_B04_0_Pos)                          /*!< LCD PAL132: B04_0 Mask              */
+#define LCD_PAL132_I0_Pos                                     15                                                        /*!< LCD PAL132: I0 Position             */
+#define LCD_PAL132_I0_Msk                                     (0x01UL << LCD_PAL132_I0_Pos)                             /*!< LCD PAL132: I0 Mask                 */
+#define LCD_PAL132_R14_0_Pos                                  16                                                        /*!< LCD PAL132: R14_0 Position          */
+#define LCD_PAL132_R14_0_Msk                                  (0x1fUL << LCD_PAL132_R14_0_Pos)                          /*!< LCD PAL132: R14_0 Mask              */
+#define LCD_PAL132_G14_0_Pos                                  21                                                        /*!< LCD PAL132: G14_0 Position          */
+#define LCD_PAL132_G14_0_Msk                                  (0x1fUL << LCD_PAL132_G14_0_Pos)                          /*!< LCD PAL132: G14_0 Mask              */
+#define LCD_PAL132_B14_0_Pos                                  26                                                        /*!< LCD PAL132: B14_0 Position          */
+#define LCD_PAL132_B14_0_Msk                                  (0x1fUL << LCD_PAL132_B14_0_Pos)                          /*!< LCD PAL132: B14_0 Mask              */
+#define LCD_PAL132_I1_Pos                                     31                                                        /*!< LCD PAL132: I1 Position             */
+#define LCD_PAL132_I1_Msk                                     (0x01UL << LCD_PAL132_I1_Pos)                             /*!< LCD PAL132: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL133  -------------------------------------------
+#define LCD_PAL133_R04_0_Pos                                  0                                                         /*!< LCD PAL133: R04_0 Position          */
+#define LCD_PAL133_R04_0_Msk                                  (0x1fUL << LCD_PAL133_R04_0_Pos)                          /*!< LCD PAL133: R04_0 Mask              */
+#define LCD_PAL133_G04_0_Pos                                  5                                                         /*!< LCD PAL133: G04_0 Position          */
+#define LCD_PAL133_G04_0_Msk                                  (0x1fUL << LCD_PAL133_G04_0_Pos)                          /*!< LCD PAL133: G04_0 Mask              */
+#define LCD_PAL133_B04_0_Pos                                  10                                                        /*!< LCD PAL133: B04_0 Position          */
+#define LCD_PAL133_B04_0_Msk                                  (0x1fUL << LCD_PAL133_B04_0_Pos)                          /*!< LCD PAL133: B04_0 Mask              */
+#define LCD_PAL133_I0_Pos                                     15                                                        /*!< LCD PAL133: I0 Position             */
+#define LCD_PAL133_I0_Msk                                     (0x01UL << LCD_PAL133_I0_Pos)                             /*!< LCD PAL133: I0 Mask                 */
+#define LCD_PAL133_R14_0_Pos                                  16                                                        /*!< LCD PAL133: R14_0 Position          */
+#define LCD_PAL133_R14_0_Msk                                  (0x1fUL << LCD_PAL133_R14_0_Pos)                          /*!< LCD PAL133: R14_0 Mask              */
+#define LCD_PAL133_G14_0_Pos                                  21                                                        /*!< LCD PAL133: G14_0 Position          */
+#define LCD_PAL133_G14_0_Msk                                  (0x1fUL << LCD_PAL133_G14_0_Pos)                          /*!< LCD PAL133: G14_0 Mask              */
+#define LCD_PAL133_B14_0_Pos                                  26                                                        /*!< LCD PAL133: B14_0 Position          */
+#define LCD_PAL133_B14_0_Msk                                  (0x1fUL << LCD_PAL133_B14_0_Pos)                          /*!< LCD PAL133: B14_0 Mask              */
+#define LCD_PAL133_I1_Pos                                     31                                                        /*!< LCD PAL133: I1 Position             */
+#define LCD_PAL133_I1_Msk                                     (0x01UL << LCD_PAL133_I1_Pos)                             /*!< LCD PAL133: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL134  -------------------------------------------
+#define LCD_PAL134_R04_0_Pos                                  0                                                         /*!< LCD PAL134: R04_0 Position          */
+#define LCD_PAL134_R04_0_Msk                                  (0x1fUL << LCD_PAL134_R04_0_Pos)                          /*!< LCD PAL134: R04_0 Mask              */
+#define LCD_PAL134_G04_0_Pos                                  5                                                         /*!< LCD PAL134: G04_0 Position          */
+#define LCD_PAL134_G04_0_Msk                                  (0x1fUL << LCD_PAL134_G04_0_Pos)                          /*!< LCD PAL134: G04_0 Mask              */
+#define LCD_PAL134_B04_0_Pos                                  10                                                        /*!< LCD PAL134: B04_0 Position          */
+#define LCD_PAL134_B04_0_Msk                                  (0x1fUL << LCD_PAL134_B04_0_Pos)                          /*!< LCD PAL134: B04_0 Mask              */
+#define LCD_PAL134_I0_Pos                                     15                                                        /*!< LCD PAL134: I0 Position             */
+#define LCD_PAL134_I0_Msk                                     (0x01UL << LCD_PAL134_I0_Pos)                             /*!< LCD PAL134: I0 Mask                 */
+#define LCD_PAL134_R14_0_Pos                                  16                                                        /*!< LCD PAL134: R14_0 Position          */
+#define LCD_PAL134_R14_0_Msk                                  (0x1fUL << LCD_PAL134_R14_0_Pos)                          /*!< LCD PAL134: R14_0 Mask              */
+#define LCD_PAL134_G14_0_Pos                                  21                                                        /*!< LCD PAL134: G14_0 Position          */
+#define LCD_PAL134_G14_0_Msk                                  (0x1fUL << LCD_PAL134_G14_0_Pos)                          /*!< LCD PAL134: G14_0 Mask              */
+#define LCD_PAL134_B14_0_Pos                                  26                                                        /*!< LCD PAL134: B14_0 Position          */
+#define LCD_PAL134_B14_0_Msk                                  (0x1fUL << LCD_PAL134_B14_0_Pos)                          /*!< LCD PAL134: B14_0 Mask              */
+#define LCD_PAL134_I1_Pos                                     31                                                        /*!< LCD PAL134: I1 Position             */
+#define LCD_PAL134_I1_Msk                                     (0x01UL << LCD_PAL134_I1_Pos)                             /*!< LCD PAL134: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL135  -------------------------------------------
+#define LCD_PAL135_R04_0_Pos                                  0                                                         /*!< LCD PAL135: R04_0 Position          */
+#define LCD_PAL135_R04_0_Msk                                  (0x1fUL << LCD_PAL135_R04_0_Pos)                          /*!< LCD PAL135: R04_0 Mask              */
+#define LCD_PAL135_G04_0_Pos                                  5                                                         /*!< LCD PAL135: G04_0 Position          */
+#define LCD_PAL135_G04_0_Msk                                  (0x1fUL << LCD_PAL135_G04_0_Pos)                          /*!< LCD PAL135: G04_0 Mask              */
+#define LCD_PAL135_B04_0_Pos                                  10                                                        /*!< LCD PAL135: B04_0 Position          */
+#define LCD_PAL135_B04_0_Msk                                  (0x1fUL << LCD_PAL135_B04_0_Pos)                          /*!< LCD PAL135: B04_0 Mask              */
+#define LCD_PAL135_I0_Pos                                     15                                                        /*!< LCD PAL135: I0 Position             */
+#define LCD_PAL135_I0_Msk                                     (0x01UL << LCD_PAL135_I0_Pos)                             /*!< LCD PAL135: I0 Mask                 */
+#define LCD_PAL135_R14_0_Pos                                  16                                                        /*!< LCD PAL135: R14_0 Position          */
+#define LCD_PAL135_R14_0_Msk                                  (0x1fUL << LCD_PAL135_R14_0_Pos)                          /*!< LCD PAL135: R14_0 Mask              */
+#define LCD_PAL135_G14_0_Pos                                  21                                                        /*!< LCD PAL135: G14_0 Position          */
+#define LCD_PAL135_G14_0_Msk                                  (0x1fUL << LCD_PAL135_G14_0_Pos)                          /*!< LCD PAL135: G14_0 Mask              */
+#define LCD_PAL135_B14_0_Pos                                  26                                                        /*!< LCD PAL135: B14_0 Position          */
+#define LCD_PAL135_B14_0_Msk                                  (0x1fUL << LCD_PAL135_B14_0_Pos)                          /*!< LCD PAL135: B14_0 Mask              */
+#define LCD_PAL135_I1_Pos                                     31                                                        /*!< LCD PAL135: I1 Position             */
+#define LCD_PAL135_I1_Msk                                     (0x01UL << LCD_PAL135_I1_Pos)                             /*!< LCD PAL135: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL136  -------------------------------------------
+#define LCD_PAL136_R04_0_Pos                                  0                                                         /*!< LCD PAL136: R04_0 Position          */
+#define LCD_PAL136_R04_0_Msk                                  (0x1fUL << LCD_PAL136_R04_0_Pos)                          /*!< LCD PAL136: R04_0 Mask              */
+#define LCD_PAL136_G04_0_Pos                                  5                                                         /*!< LCD PAL136: G04_0 Position          */
+#define LCD_PAL136_G04_0_Msk                                  (0x1fUL << LCD_PAL136_G04_0_Pos)                          /*!< LCD PAL136: G04_0 Mask              */
+#define LCD_PAL136_B04_0_Pos                                  10                                                        /*!< LCD PAL136: B04_0 Position          */
+#define LCD_PAL136_B04_0_Msk                                  (0x1fUL << LCD_PAL136_B04_0_Pos)                          /*!< LCD PAL136: B04_0 Mask              */
+#define LCD_PAL136_I0_Pos                                     15                                                        /*!< LCD PAL136: I0 Position             */
+#define LCD_PAL136_I0_Msk                                     (0x01UL << LCD_PAL136_I0_Pos)                             /*!< LCD PAL136: I0 Mask                 */
+#define LCD_PAL136_R14_0_Pos                                  16                                                        /*!< LCD PAL136: R14_0 Position          */
+#define LCD_PAL136_R14_0_Msk                                  (0x1fUL << LCD_PAL136_R14_0_Pos)                          /*!< LCD PAL136: R14_0 Mask              */
+#define LCD_PAL136_G14_0_Pos                                  21                                                        /*!< LCD PAL136: G14_0 Position          */
+#define LCD_PAL136_G14_0_Msk                                  (0x1fUL << LCD_PAL136_G14_0_Pos)                          /*!< LCD PAL136: G14_0 Mask              */
+#define LCD_PAL136_B14_0_Pos                                  26                                                        /*!< LCD PAL136: B14_0 Position          */
+#define LCD_PAL136_B14_0_Msk                                  (0x1fUL << LCD_PAL136_B14_0_Pos)                          /*!< LCD PAL136: B14_0 Mask              */
+#define LCD_PAL136_I1_Pos                                     31                                                        /*!< LCD PAL136: I1 Position             */
+#define LCD_PAL136_I1_Msk                                     (0x01UL << LCD_PAL136_I1_Pos)                             /*!< LCD PAL136: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL137  -------------------------------------------
+#define LCD_PAL137_R04_0_Pos                                  0                                                         /*!< LCD PAL137: R04_0 Position          */
+#define LCD_PAL137_R04_0_Msk                                  (0x1fUL << LCD_PAL137_R04_0_Pos)                          /*!< LCD PAL137: R04_0 Mask              */
+#define LCD_PAL137_G04_0_Pos                                  5                                                         /*!< LCD PAL137: G04_0 Position          */
+#define LCD_PAL137_G04_0_Msk                                  (0x1fUL << LCD_PAL137_G04_0_Pos)                          /*!< LCD PAL137: G04_0 Mask              */
+#define LCD_PAL137_B04_0_Pos                                  10                                                        /*!< LCD PAL137: B04_0 Position          */
+#define LCD_PAL137_B04_0_Msk                                  (0x1fUL << LCD_PAL137_B04_0_Pos)                          /*!< LCD PAL137: B04_0 Mask              */
+#define LCD_PAL137_I0_Pos                                     15                                                        /*!< LCD PAL137: I0 Position             */
+#define LCD_PAL137_I0_Msk                                     (0x01UL << LCD_PAL137_I0_Pos)                             /*!< LCD PAL137: I0 Mask                 */
+#define LCD_PAL137_R14_0_Pos                                  16                                                        /*!< LCD PAL137: R14_0 Position          */
+#define LCD_PAL137_R14_0_Msk                                  (0x1fUL << LCD_PAL137_R14_0_Pos)                          /*!< LCD PAL137: R14_0 Mask              */
+#define LCD_PAL137_G14_0_Pos                                  21                                                        /*!< LCD PAL137: G14_0 Position          */
+#define LCD_PAL137_G14_0_Msk                                  (0x1fUL << LCD_PAL137_G14_0_Pos)                          /*!< LCD PAL137: G14_0 Mask              */
+#define LCD_PAL137_B14_0_Pos                                  26                                                        /*!< LCD PAL137: B14_0 Position          */
+#define LCD_PAL137_B14_0_Msk                                  (0x1fUL << LCD_PAL137_B14_0_Pos)                          /*!< LCD PAL137: B14_0 Mask              */
+#define LCD_PAL137_I1_Pos                                     31                                                        /*!< LCD PAL137: I1 Position             */
+#define LCD_PAL137_I1_Msk                                     (0x01UL << LCD_PAL137_I1_Pos)                             /*!< LCD PAL137: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL138  -------------------------------------------
+#define LCD_PAL138_R04_0_Pos                                  0                                                         /*!< LCD PAL138: R04_0 Position          */
+#define LCD_PAL138_R04_0_Msk                                  (0x1fUL << LCD_PAL138_R04_0_Pos)                          /*!< LCD PAL138: R04_0 Mask              */
+#define LCD_PAL138_G04_0_Pos                                  5                                                         /*!< LCD PAL138: G04_0 Position          */
+#define LCD_PAL138_G04_0_Msk                                  (0x1fUL << LCD_PAL138_G04_0_Pos)                          /*!< LCD PAL138: G04_0 Mask              */
+#define LCD_PAL138_B04_0_Pos                                  10                                                        /*!< LCD PAL138: B04_0 Position          */
+#define LCD_PAL138_B04_0_Msk                                  (0x1fUL << LCD_PAL138_B04_0_Pos)                          /*!< LCD PAL138: B04_0 Mask              */
+#define LCD_PAL138_I0_Pos                                     15                                                        /*!< LCD PAL138: I0 Position             */
+#define LCD_PAL138_I0_Msk                                     (0x01UL << LCD_PAL138_I0_Pos)                             /*!< LCD PAL138: I0 Mask                 */
+#define LCD_PAL138_R14_0_Pos                                  16                                                        /*!< LCD PAL138: R14_0 Position          */
+#define LCD_PAL138_R14_0_Msk                                  (0x1fUL << LCD_PAL138_R14_0_Pos)                          /*!< LCD PAL138: R14_0 Mask              */
+#define LCD_PAL138_G14_0_Pos                                  21                                                        /*!< LCD PAL138: G14_0 Position          */
+#define LCD_PAL138_G14_0_Msk                                  (0x1fUL << LCD_PAL138_G14_0_Pos)                          /*!< LCD PAL138: G14_0 Mask              */
+#define LCD_PAL138_B14_0_Pos                                  26                                                        /*!< LCD PAL138: B14_0 Position          */
+#define LCD_PAL138_B14_0_Msk                                  (0x1fUL << LCD_PAL138_B14_0_Pos)                          /*!< LCD PAL138: B14_0 Mask              */
+#define LCD_PAL138_I1_Pos                                     31                                                        /*!< LCD PAL138: I1 Position             */
+#define LCD_PAL138_I1_Msk                                     (0x01UL << LCD_PAL138_I1_Pos)                             /*!< LCD PAL138: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL139  -------------------------------------------
+#define LCD_PAL139_R04_0_Pos                                  0                                                         /*!< LCD PAL139: R04_0 Position          */
+#define LCD_PAL139_R04_0_Msk                                  (0x1fUL << LCD_PAL139_R04_0_Pos)                          /*!< LCD PAL139: R04_0 Mask              */
+#define LCD_PAL139_G04_0_Pos                                  5                                                         /*!< LCD PAL139: G04_0 Position          */
+#define LCD_PAL139_G04_0_Msk                                  (0x1fUL << LCD_PAL139_G04_0_Pos)                          /*!< LCD PAL139: G04_0 Mask              */
+#define LCD_PAL139_B04_0_Pos                                  10                                                        /*!< LCD PAL139: B04_0 Position          */
+#define LCD_PAL139_B04_0_Msk                                  (0x1fUL << LCD_PAL139_B04_0_Pos)                          /*!< LCD PAL139: B04_0 Mask              */
+#define LCD_PAL139_I0_Pos                                     15                                                        /*!< LCD PAL139: I0 Position             */
+#define LCD_PAL139_I0_Msk                                     (0x01UL << LCD_PAL139_I0_Pos)                             /*!< LCD PAL139: I0 Mask                 */
+#define LCD_PAL139_R14_0_Pos                                  16                                                        /*!< LCD PAL139: R14_0 Position          */
+#define LCD_PAL139_R14_0_Msk                                  (0x1fUL << LCD_PAL139_R14_0_Pos)                          /*!< LCD PAL139: R14_0 Mask              */
+#define LCD_PAL139_G14_0_Pos                                  21                                                        /*!< LCD PAL139: G14_0 Position          */
+#define LCD_PAL139_G14_0_Msk                                  (0x1fUL << LCD_PAL139_G14_0_Pos)                          /*!< LCD PAL139: G14_0 Mask              */
+#define LCD_PAL139_B14_0_Pos                                  26                                                        /*!< LCD PAL139: B14_0 Position          */
+#define LCD_PAL139_B14_0_Msk                                  (0x1fUL << LCD_PAL139_B14_0_Pos)                          /*!< LCD PAL139: B14_0 Mask              */
+#define LCD_PAL139_I1_Pos                                     31                                                        /*!< LCD PAL139: I1 Position             */
+#define LCD_PAL139_I1_Msk                                     (0x01UL << LCD_PAL139_I1_Pos)                             /*!< LCD PAL139: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL140  -------------------------------------------
+#define LCD_PAL140_R04_0_Pos                                  0                                                         /*!< LCD PAL140: R04_0 Position          */
+#define LCD_PAL140_R04_0_Msk                                  (0x1fUL << LCD_PAL140_R04_0_Pos)                          /*!< LCD PAL140: R04_0 Mask              */
+#define LCD_PAL140_G04_0_Pos                                  5                                                         /*!< LCD PAL140: G04_0 Position          */
+#define LCD_PAL140_G04_0_Msk                                  (0x1fUL << LCD_PAL140_G04_0_Pos)                          /*!< LCD PAL140: G04_0 Mask              */
+#define LCD_PAL140_B04_0_Pos                                  10                                                        /*!< LCD PAL140: B04_0 Position          */
+#define LCD_PAL140_B04_0_Msk                                  (0x1fUL << LCD_PAL140_B04_0_Pos)                          /*!< LCD PAL140: B04_0 Mask              */
+#define LCD_PAL140_I0_Pos                                     15                                                        /*!< LCD PAL140: I0 Position             */
+#define LCD_PAL140_I0_Msk                                     (0x01UL << LCD_PAL140_I0_Pos)                             /*!< LCD PAL140: I0 Mask                 */
+#define LCD_PAL140_R14_0_Pos                                  16                                                        /*!< LCD PAL140: R14_0 Position          */
+#define LCD_PAL140_R14_0_Msk                                  (0x1fUL << LCD_PAL140_R14_0_Pos)                          /*!< LCD PAL140: R14_0 Mask              */
+#define LCD_PAL140_G14_0_Pos                                  21                                                        /*!< LCD PAL140: G14_0 Position          */
+#define LCD_PAL140_G14_0_Msk                                  (0x1fUL << LCD_PAL140_G14_0_Pos)                          /*!< LCD PAL140: G14_0 Mask              */
+#define LCD_PAL140_B14_0_Pos                                  26                                                        /*!< LCD PAL140: B14_0 Position          */
+#define LCD_PAL140_B14_0_Msk                                  (0x1fUL << LCD_PAL140_B14_0_Pos)                          /*!< LCD PAL140: B14_0 Mask              */
+#define LCD_PAL140_I1_Pos                                     31                                                        /*!< LCD PAL140: I1 Position             */
+#define LCD_PAL140_I1_Msk                                     (0x01UL << LCD_PAL140_I1_Pos)                             /*!< LCD PAL140: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL141  -------------------------------------------
+#define LCD_PAL141_R04_0_Pos                                  0                                                         /*!< LCD PAL141: R04_0 Position          */
+#define LCD_PAL141_R04_0_Msk                                  (0x1fUL << LCD_PAL141_R04_0_Pos)                          /*!< LCD PAL141: R04_0 Mask              */
+#define LCD_PAL141_G04_0_Pos                                  5                                                         /*!< LCD PAL141: G04_0 Position          */
+#define LCD_PAL141_G04_0_Msk                                  (0x1fUL << LCD_PAL141_G04_0_Pos)                          /*!< LCD PAL141: G04_0 Mask              */
+#define LCD_PAL141_B04_0_Pos                                  10                                                        /*!< LCD PAL141: B04_0 Position          */
+#define LCD_PAL141_B04_0_Msk                                  (0x1fUL << LCD_PAL141_B04_0_Pos)                          /*!< LCD PAL141: B04_0 Mask              */
+#define LCD_PAL141_I0_Pos                                     15                                                        /*!< LCD PAL141: I0 Position             */
+#define LCD_PAL141_I0_Msk                                     (0x01UL << LCD_PAL141_I0_Pos)                             /*!< LCD PAL141: I0 Mask                 */
+#define LCD_PAL141_R14_0_Pos                                  16                                                        /*!< LCD PAL141: R14_0 Position          */
+#define LCD_PAL141_R14_0_Msk                                  (0x1fUL << LCD_PAL141_R14_0_Pos)                          /*!< LCD PAL141: R14_0 Mask              */
+#define LCD_PAL141_G14_0_Pos                                  21                                                        /*!< LCD PAL141: G14_0 Position          */
+#define LCD_PAL141_G14_0_Msk                                  (0x1fUL << LCD_PAL141_G14_0_Pos)                          /*!< LCD PAL141: G14_0 Mask              */
+#define LCD_PAL141_B14_0_Pos                                  26                                                        /*!< LCD PAL141: B14_0 Position          */
+#define LCD_PAL141_B14_0_Msk                                  (0x1fUL << LCD_PAL141_B14_0_Pos)                          /*!< LCD PAL141: B14_0 Mask              */
+#define LCD_PAL141_I1_Pos                                     31                                                        /*!< LCD PAL141: I1 Position             */
+#define LCD_PAL141_I1_Msk                                     (0x01UL << LCD_PAL141_I1_Pos)                             /*!< LCD PAL141: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL142  -------------------------------------------
+#define LCD_PAL142_R04_0_Pos                                  0                                                         /*!< LCD PAL142: R04_0 Position          */
+#define LCD_PAL142_R04_0_Msk                                  (0x1fUL << LCD_PAL142_R04_0_Pos)                          /*!< LCD PAL142: R04_0 Mask              */
+#define LCD_PAL142_G04_0_Pos                                  5                                                         /*!< LCD PAL142: G04_0 Position          */
+#define LCD_PAL142_G04_0_Msk                                  (0x1fUL << LCD_PAL142_G04_0_Pos)                          /*!< LCD PAL142: G04_0 Mask              */
+#define LCD_PAL142_B04_0_Pos                                  10                                                        /*!< LCD PAL142: B04_0 Position          */
+#define LCD_PAL142_B04_0_Msk                                  (0x1fUL << LCD_PAL142_B04_0_Pos)                          /*!< LCD PAL142: B04_0 Mask              */
+#define LCD_PAL142_I0_Pos                                     15                                                        /*!< LCD PAL142: I0 Position             */
+#define LCD_PAL142_I0_Msk                                     (0x01UL << LCD_PAL142_I0_Pos)                             /*!< LCD PAL142: I0 Mask                 */
+#define LCD_PAL142_R14_0_Pos                                  16                                                        /*!< LCD PAL142: R14_0 Position          */
+#define LCD_PAL142_R14_0_Msk                                  (0x1fUL << LCD_PAL142_R14_0_Pos)                          /*!< LCD PAL142: R14_0 Mask              */
+#define LCD_PAL142_G14_0_Pos                                  21                                                        /*!< LCD PAL142: G14_0 Position          */
+#define LCD_PAL142_G14_0_Msk                                  (0x1fUL << LCD_PAL142_G14_0_Pos)                          /*!< LCD PAL142: G14_0 Mask              */
+#define LCD_PAL142_B14_0_Pos                                  26                                                        /*!< LCD PAL142: B14_0 Position          */
+#define LCD_PAL142_B14_0_Msk                                  (0x1fUL << LCD_PAL142_B14_0_Pos)                          /*!< LCD PAL142: B14_0 Mask              */
+#define LCD_PAL142_I1_Pos                                     31                                                        /*!< LCD PAL142: I1 Position             */
+#define LCD_PAL142_I1_Msk                                     (0x01UL << LCD_PAL142_I1_Pos)                             /*!< LCD PAL142: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL143  -------------------------------------------
+#define LCD_PAL143_R04_0_Pos                                  0                                                         /*!< LCD PAL143: R04_0 Position          */
+#define LCD_PAL143_R04_0_Msk                                  (0x1fUL << LCD_PAL143_R04_0_Pos)                          /*!< LCD PAL143: R04_0 Mask              */
+#define LCD_PAL143_G04_0_Pos                                  5                                                         /*!< LCD PAL143: G04_0 Position          */
+#define LCD_PAL143_G04_0_Msk                                  (0x1fUL << LCD_PAL143_G04_0_Pos)                          /*!< LCD PAL143: G04_0 Mask              */
+#define LCD_PAL143_B04_0_Pos                                  10                                                        /*!< LCD PAL143: B04_0 Position          */
+#define LCD_PAL143_B04_0_Msk                                  (0x1fUL << LCD_PAL143_B04_0_Pos)                          /*!< LCD PAL143: B04_0 Mask              */
+#define LCD_PAL143_I0_Pos                                     15                                                        /*!< LCD PAL143: I0 Position             */
+#define LCD_PAL143_I0_Msk                                     (0x01UL << LCD_PAL143_I0_Pos)                             /*!< LCD PAL143: I0 Mask                 */
+#define LCD_PAL143_R14_0_Pos                                  16                                                        /*!< LCD PAL143: R14_0 Position          */
+#define LCD_PAL143_R14_0_Msk                                  (0x1fUL << LCD_PAL143_R14_0_Pos)                          /*!< LCD PAL143: R14_0 Mask              */
+#define LCD_PAL143_G14_0_Pos                                  21                                                        /*!< LCD PAL143: G14_0 Position          */
+#define LCD_PAL143_G14_0_Msk                                  (0x1fUL << LCD_PAL143_G14_0_Pos)                          /*!< LCD PAL143: G14_0 Mask              */
+#define LCD_PAL143_B14_0_Pos                                  26                                                        /*!< LCD PAL143: B14_0 Position          */
+#define LCD_PAL143_B14_0_Msk                                  (0x1fUL << LCD_PAL143_B14_0_Pos)                          /*!< LCD PAL143: B14_0 Mask              */
+#define LCD_PAL143_I1_Pos                                     31                                                        /*!< LCD PAL143: I1 Position             */
+#define LCD_PAL143_I1_Msk                                     (0x01UL << LCD_PAL143_I1_Pos)                             /*!< LCD PAL143: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL144  -------------------------------------------
+#define LCD_PAL144_R04_0_Pos                                  0                                                         /*!< LCD PAL144: R04_0 Position          */
+#define LCD_PAL144_R04_0_Msk                                  (0x1fUL << LCD_PAL144_R04_0_Pos)                          /*!< LCD PAL144: R04_0 Mask              */
+#define LCD_PAL144_G04_0_Pos                                  5                                                         /*!< LCD PAL144: G04_0 Position          */
+#define LCD_PAL144_G04_0_Msk                                  (0x1fUL << LCD_PAL144_G04_0_Pos)                          /*!< LCD PAL144: G04_0 Mask              */
+#define LCD_PAL144_B04_0_Pos                                  10                                                        /*!< LCD PAL144: B04_0 Position          */
+#define LCD_PAL144_B04_0_Msk                                  (0x1fUL << LCD_PAL144_B04_0_Pos)                          /*!< LCD PAL144: B04_0 Mask              */
+#define LCD_PAL144_I0_Pos                                     15                                                        /*!< LCD PAL144: I0 Position             */
+#define LCD_PAL144_I0_Msk                                     (0x01UL << LCD_PAL144_I0_Pos)                             /*!< LCD PAL144: I0 Mask                 */
+#define LCD_PAL144_R14_0_Pos                                  16                                                        /*!< LCD PAL144: R14_0 Position          */
+#define LCD_PAL144_R14_0_Msk                                  (0x1fUL << LCD_PAL144_R14_0_Pos)                          /*!< LCD PAL144: R14_0 Mask              */
+#define LCD_PAL144_G14_0_Pos                                  21                                                        /*!< LCD PAL144: G14_0 Position          */
+#define LCD_PAL144_G14_0_Msk                                  (0x1fUL << LCD_PAL144_G14_0_Pos)                          /*!< LCD PAL144: G14_0 Mask              */
+#define LCD_PAL144_B14_0_Pos                                  26                                                        /*!< LCD PAL144: B14_0 Position          */
+#define LCD_PAL144_B14_0_Msk                                  (0x1fUL << LCD_PAL144_B14_0_Pos)                          /*!< LCD PAL144: B14_0 Mask              */
+#define LCD_PAL144_I1_Pos                                     31                                                        /*!< LCD PAL144: I1 Position             */
+#define LCD_PAL144_I1_Msk                                     (0x01UL << LCD_PAL144_I1_Pos)                             /*!< LCD PAL144: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL145  -------------------------------------------
+#define LCD_PAL145_R04_0_Pos                                  0                                                         /*!< LCD PAL145: R04_0 Position          */
+#define LCD_PAL145_R04_0_Msk                                  (0x1fUL << LCD_PAL145_R04_0_Pos)                          /*!< LCD PAL145: R04_0 Mask              */
+#define LCD_PAL145_G04_0_Pos                                  5                                                         /*!< LCD PAL145: G04_0 Position          */
+#define LCD_PAL145_G04_0_Msk                                  (0x1fUL << LCD_PAL145_G04_0_Pos)                          /*!< LCD PAL145: G04_0 Mask              */
+#define LCD_PAL145_B04_0_Pos                                  10                                                        /*!< LCD PAL145: B04_0 Position          */
+#define LCD_PAL145_B04_0_Msk                                  (0x1fUL << LCD_PAL145_B04_0_Pos)                          /*!< LCD PAL145: B04_0 Mask              */
+#define LCD_PAL145_I0_Pos                                     15                                                        /*!< LCD PAL145: I0 Position             */
+#define LCD_PAL145_I0_Msk                                     (0x01UL << LCD_PAL145_I0_Pos)                             /*!< LCD PAL145: I0 Mask                 */
+#define LCD_PAL145_R14_0_Pos                                  16                                                        /*!< LCD PAL145: R14_0 Position          */
+#define LCD_PAL145_R14_0_Msk                                  (0x1fUL << LCD_PAL145_R14_0_Pos)                          /*!< LCD PAL145: R14_0 Mask              */
+#define LCD_PAL145_G14_0_Pos                                  21                                                        /*!< LCD PAL145: G14_0 Position          */
+#define LCD_PAL145_G14_0_Msk                                  (0x1fUL << LCD_PAL145_G14_0_Pos)                          /*!< LCD PAL145: G14_0 Mask              */
+#define LCD_PAL145_B14_0_Pos                                  26                                                        /*!< LCD PAL145: B14_0 Position          */
+#define LCD_PAL145_B14_0_Msk                                  (0x1fUL << LCD_PAL145_B14_0_Pos)                          /*!< LCD PAL145: B14_0 Mask              */
+#define LCD_PAL145_I1_Pos                                     31                                                        /*!< LCD PAL145: I1 Position             */
+#define LCD_PAL145_I1_Msk                                     (0x01UL << LCD_PAL145_I1_Pos)                             /*!< LCD PAL145: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL146  -------------------------------------------
+#define LCD_PAL146_R04_0_Pos                                  0                                                         /*!< LCD PAL146: R04_0 Position          */
+#define LCD_PAL146_R04_0_Msk                                  (0x1fUL << LCD_PAL146_R04_0_Pos)                          /*!< LCD PAL146: R04_0 Mask              */
+#define LCD_PAL146_G04_0_Pos                                  5                                                         /*!< LCD PAL146: G04_0 Position          */
+#define LCD_PAL146_G04_0_Msk                                  (0x1fUL << LCD_PAL146_G04_0_Pos)                          /*!< LCD PAL146: G04_0 Mask              */
+#define LCD_PAL146_B04_0_Pos                                  10                                                        /*!< LCD PAL146: B04_0 Position          */
+#define LCD_PAL146_B04_0_Msk                                  (0x1fUL << LCD_PAL146_B04_0_Pos)                          /*!< LCD PAL146: B04_0 Mask              */
+#define LCD_PAL146_I0_Pos                                     15                                                        /*!< LCD PAL146: I0 Position             */
+#define LCD_PAL146_I0_Msk                                     (0x01UL << LCD_PAL146_I0_Pos)                             /*!< LCD PAL146: I0 Mask                 */
+#define LCD_PAL146_R14_0_Pos                                  16                                                        /*!< LCD PAL146: R14_0 Position          */
+#define LCD_PAL146_R14_0_Msk                                  (0x1fUL << LCD_PAL146_R14_0_Pos)                          /*!< LCD PAL146: R14_0 Mask              */
+#define LCD_PAL146_G14_0_Pos                                  21                                                        /*!< LCD PAL146: G14_0 Position          */
+#define LCD_PAL146_G14_0_Msk                                  (0x1fUL << LCD_PAL146_G14_0_Pos)                          /*!< LCD PAL146: G14_0 Mask              */
+#define LCD_PAL146_B14_0_Pos                                  26                                                        /*!< LCD PAL146: B14_0 Position          */
+#define LCD_PAL146_B14_0_Msk                                  (0x1fUL << LCD_PAL146_B14_0_Pos)                          /*!< LCD PAL146: B14_0 Mask              */
+#define LCD_PAL146_I1_Pos                                     31                                                        /*!< LCD PAL146: I1 Position             */
+#define LCD_PAL146_I1_Msk                                     (0x01UL << LCD_PAL146_I1_Pos)                             /*!< LCD PAL146: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL147  -------------------------------------------
+#define LCD_PAL147_R04_0_Pos                                  0                                                         /*!< LCD PAL147: R04_0 Position          */
+#define LCD_PAL147_R04_0_Msk                                  (0x1fUL << LCD_PAL147_R04_0_Pos)                          /*!< LCD PAL147: R04_0 Mask              */
+#define LCD_PAL147_G04_0_Pos                                  5                                                         /*!< LCD PAL147: G04_0 Position          */
+#define LCD_PAL147_G04_0_Msk                                  (0x1fUL << LCD_PAL147_G04_0_Pos)                          /*!< LCD PAL147: G04_0 Mask              */
+#define LCD_PAL147_B04_0_Pos                                  10                                                        /*!< LCD PAL147: B04_0 Position          */
+#define LCD_PAL147_B04_0_Msk                                  (0x1fUL << LCD_PAL147_B04_0_Pos)                          /*!< LCD PAL147: B04_0 Mask              */
+#define LCD_PAL147_I0_Pos                                     15                                                        /*!< LCD PAL147: I0 Position             */
+#define LCD_PAL147_I0_Msk                                     (0x01UL << LCD_PAL147_I0_Pos)                             /*!< LCD PAL147: I0 Mask                 */
+#define LCD_PAL147_R14_0_Pos                                  16                                                        /*!< LCD PAL147: R14_0 Position          */
+#define LCD_PAL147_R14_0_Msk                                  (0x1fUL << LCD_PAL147_R14_0_Pos)                          /*!< LCD PAL147: R14_0 Mask              */
+#define LCD_PAL147_G14_0_Pos                                  21                                                        /*!< LCD PAL147: G14_0 Position          */
+#define LCD_PAL147_G14_0_Msk                                  (0x1fUL << LCD_PAL147_G14_0_Pos)                          /*!< LCD PAL147: G14_0 Mask              */
+#define LCD_PAL147_B14_0_Pos                                  26                                                        /*!< LCD PAL147: B14_0 Position          */
+#define LCD_PAL147_B14_0_Msk                                  (0x1fUL << LCD_PAL147_B14_0_Pos)                          /*!< LCD PAL147: B14_0 Mask              */
+#define LCD_PAL147_I1_Pos                                     31                                                        /*!< LCD PAL147: I1 Position             */
+#define LCD_PAL147_I1_Msk                                     (0x01UL << LCD_PAL147_I1_Pos)                             /*!< LCD PAL147: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL148  -------------------------------------------
+#define LCD_PAL148_R04_0_Pos                                  0                                                         /*!< LCD PAL148: R04_0 Position          */
+#define LCD_PAL148_R04_0_Msk                                  (0x1fUL << LCD_PAL148_R04_0_Pos)                          /*!< LCD PAL148: R04_0 Mask              */
+#define LCD_PAL148_G04_0_Pos                                  5                                                         /*!< LCD PAL148: G04_0 Position          */
+#define LCD_PAL148_G04_0_Msk                                  (0x1fUL << LCD_PAL148_G04_0_Pos)                          /*!< LCD PAL148: G04_0 Mask              */
+#define LCD_PAL148_B04_0_Pos                                  10                                                        /*!< LCD PAL148: B04_0 Position          */
+#define LCD_PAL148_B04_0_Msk                                  (0x1fUL << LCD_PAL148_B04_0_Pos)                          /*!< LCD PAL148: B04_0 Mask              */
+#define LCD_PAL148_I0_Pos                                     15                                                        /*!< LCD PAL148: I0 Position             */
+#define LCD_PAL148_I0_Msk                                     (0x01UL << LCD_PAL148_I0_Pos)                             /*!< LCD PAL148: I0 Mask                 */
+#define LCD_PAL148_R14_0_Pos                                  16                                                        /*!< LCD PAL148: R14_0 Position          */
+#define LCD_PAL148_R14_0_Msk                                  (0x1fUL << LCD_PAL148_R14_0_Pos)                          /*!< LCD PAL148: R14_0 Mask              */
+#define LCD_PAL148_G14_0_Pos                                  21                                                        /*!< LCD PAL148: G14_0 Position          */
+#define LCD_PAL148_G14_0_Msk                                  (0x1fUL << LCD_PAL148_G14_0_Pos)                          /*!< LCD PAL148: G14_0 Mask              */
+#define LCD_PAL148_B14_0_Pos                                  26                                                        /*!< LCD PAL148: B14_0 Position          */
+#define LCD_PAL148_B14_0_Msk                                  (0x1fUL << LCD_PAL148_B14_0_Pos)                          /*!< LCD PAL148: B14_0 Mask              */
+#define LCD_PAL148_I1_Pos                                     31                                                        /*!< LCD PAL148: I1 Position             */
+#define LCD_PAL148_I1_Msk                                     (0x01UL << LCD_PAL148_I1_Pos)                             /*!< LCD PAL148: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL149  -------------------------------------------
+#define LCD_PAL149_R04_0_Pos                                  0                                                         /*!< LCD PAL149: R04_0 Position          */
+#define LCD_PAL149_R04_0_Msk                                  (0x1fUL << LCD_PAL149_R04_0_Pos)                          /*!< LCD PAL149: R04_0 Mask              */
+#define LCD_PAL149_G04_0_Pos                                  5                                                         /*!< LCD PAL149: G04_0 Position          */
+#define LCD_PAL149_G04_0_Msk                                  (0x1fUL << LCD_PAL149_G04_0_Pos)                          /*!< LCD PAL149: G04_0 Mask              */
+#define LCD_PAL149_B04_0_Pos                                  10                                                        /*!< LCD PAL149: B04_0 Position          */
+#define LCD_PAL149_B04_0_Msk                                  (0x1fUL << LCD_PAL149_B04_0_Pos)                          /*!< LCD PAL149: B04_0 Mask              */
+#define LCD_PAL149_I0_Pos                                     15                                                        /*!< LCD PAL149: I0 Position             */
+#define LCD_PAL149_I0_Msk                                     (0x01UL << LCD_PAL149_I0_Pos)                             /*!< LCD PAL149: I0 Mask                 */
+#define LCD_PAL149_R14_0_Pos                                  16                                                        /*!< LCD PAL149: R14_0 Position          */
+#define LCD_PAL149_R14_0_Msk                                  (0x1fUL << LCD_PAL149_R14_0_Pos)                          /*!< LCD PAL149: R14_0 Mask              */
+#define LCD_PAL149_G14_0_Pos                                  21                                                        /*!< LCD PAL149: G14_0 Position          */
+#define LCD_PAL149_G14_0_Msk                                  (0x1fUL << LCD_PAL149_G14_0_Pos)                          /*!< LCD PAL149: G14_0 Mask              */
+#define LCD_PAL149_B14_0_Pos                                  26                                                        /*!< LCD PAL149: B14_0 Position          */
+#define LCD_PAL149_B14_0_Msk                                  (0x1fUL << LCD_PAL149_B14_0_Pos)                          /*!< LCD PAL149: B14_0 Mask              */
+#define LCD_PAL149_I1_Pos                                     31                                                        /*!< LCD PAL149: I1 Position             */
+#define LCD_PAL149_I1_Msk                                     (0x01UL << LCD_PAL149_I1_Pos)                             /*!< LCD PAL149: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL150  -------------------------------------------
+#define LCD_PAL150_R04_0_Pos                                  0                                                         /*!< LCD PAL150: R04_0 Position          */
+#define LCD_PAL150_R04_0_Msk                                  (0x1fUL << LCD_PAL150_R04_0_Pos)                          /*!< LCD PAL150: R04_0 Mask              */
+#define LCD_PAL150_G04_0_Pos                                  5                                                         /*!< LCD PAL150: G04_0 Position          */
+#define LCD_PAL150_G04_0_Msk                                  (0x1fUL << LCD_PAL150_G04_0_Pos)                          /*!< LCD PAL150: G04_0 Mask              */
+#define LCD_PAL150_B04_0_Pos                                  10                                                        /*!< LCD PAL150: B04_0 Position          */
+#define LCD_PAL150_B04_0_Msk                                  (0x1fUL << LCD_PAL150_B04_0_Pos)                          /*!< LCD PAL150: B04_0 Mask              */
+#define LCD_PAL150_I0_Pos                                     15                                                        /*!< LCD PAL150: I0 Position             */
+#define LCD_PAL150_I0_Msk                                     (0x01UL << LCD_PAL150_I0_Pos)                             /*!< LCD PAL150: I0 Mask                 */
+#define LCD_PAL150_R14_0_Pos                                  16                                                        /*!< LCD PAL150: R14_0 Position          */
+#define LCD_PAL150_R14_0_Msk                                  (0x1fUL << LCD_PAL150_R14_0_Pos)                          /*!< LCD PAL150: R14_0 Mask              */
+#define LCD_PAL150_G14_0_Pos                                  21                                                        /*!< LCD PAL150: G14_0 Position          */
+#define LCD_PAL150_G14_0_Msk                                  (0x1fUL << LCD_PAL150_G14_0_Pos)                          /*!< LCD PAL150: G14_0 Mask              */
+#define LCD_PAL150_B14_0_Pos                                  26                                                        /*!< LCD PAL150: B14_0 Position          */
+#define LCD_PAL150_B14_0_Msk                                  (0x1fUL << LCD_PAL150_B14_0_Pos)                          /*!< LCD PAL150: B14_0 Mask              */
+#define LCD_PAL150_I1_Pos                                     31                                                        /*!< LCD PAL150: I1 Position             */
+#define LCD_PAL150_I1_Msk                                     (0x01UL << LCD_PAL150_I1_Pos)                             /*!< LCD PAL150: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL151  -------------------------------------------
+#define LCD_PAL151_R04_0_Pos                                  0                                                         /*!< LCD PAL151: R04_0 Position          */
+#define LCD_PAL151_R04_0_Msk                                  (0x1fUL << LCD_PAL151_R04_0_Pos)                          /*!< LCD PAL151: R04_0 Mask              */
+#define LCD_PAL151_G04_0_Pos                                  5                                                         /*!< LCD PAL151: G04_0 Position          */
+#define LCD_PAL151_G04_0_Msk                                  (0x1fUL << LCD_PAL151_G04_0_Pos)                          /*!< LCD PAL151: G04_0 Mask              */
+#define LCD_PAL151_B04_0_Pos                                  10                                                        /*!< LCD PAL151: B04_0 Position          */
+#define LCD_PAL151_B04_0_Msk                                  (0x1fUL << LCD_PAL151_B04_0_Pos)                          /*!< LCD PAL151: B04_0 Mask              */
+#define LCD_PAL151_I0_Pos                                     15                                                        /*!< LCD PAL151: I0 Position             */
+#define LCD_PAL151_I0_Msk                                     (0x01UL << LCD_PAL151_I0_Pos)                             /*!< LCD PAL151: I0 Mask                 */
+#define LCD_PAL151_R14_0_Pos                                  16                                                        /*!< LCD PAL151: R14_0 Position          */
+#define LCD_PAL151_R14_0_Msk                                  (0x1fUL << LCD_PAL151_R14_0_Pos)                          /*!< LCD PAL151: R14_0 Mask              */
+#define LCD_PAL151_G14_0_Pos                                  21                                                        /*!< LCD PAL151: G14_0 Position          */
+#define LCD_PAL151_G14_0_Msk                                  (0x1fUL << LCD_PAL151_G14_0_Pos)                          /*!< LCD PAL151: G14_0 Mask              */
+#define LCD_PAL151_B14_0_Pos                                  26                                                        /*!< LCD PAL151: B14_0 Position          */
+#define LCD_PAL151_B14_0_Msk                                  (0x1fUL << LCD_PAL151_B14_0_Pos)                          /*!< LCD PAL151: B14_0 Mask              */
+#define LCD_PAL151_I1_Pos                                     31                                                        /*!< LCD PAL151: I1 Position             */
+#define LCD_PAL151_I1_Msk                                     (0x01UL << LCD_PAL151_I1_Pos)                             /*!< LCD PAL151: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL152  -------------------------------------------
+#define LCD_PAL152_R04_0_Pos                                  0                                                         /*!< LCD PAL152: R04_0 Position          */
+#define LCD_PAL152_R04_0_Msk                                  (0x1fUL << LCD_PAL152_R04_0_Pos)                          /*!< LCD PAL152: R04_0 Mask              */
+#define LCD_PAL152_G04_0_Pos                                  5                                                         /*!< LCD PAL152: G04_0 Position          */
+#define LCD_PAL152_G04_0_Msk                                  (0x1fUL << LCD_PAL152_G04_0_Pos)                          /*!< LCD PAL152: G04_0 Mask              */
+#define LCD_PAL152_B04_0_Pos                                  10                                                        /*!< LCD PAL152: B04_0 Position          */
+#define LCD_PAL152_B04_0_Msk                                  (0x1fUL << LCD_PAL152_B04_0_Pos)                          /*!< LCD PAL152: B04_0 Mask              */
+#define LCD_PAL152_I0_Pos                                     15                                                        /*!< LCD PAL152: I0 Position             */
+#define LCD_PAL152_I0_Msk                                     (0x01UL << LCD_PAL152_I0_Pos)                             /*!< LCD PAL152: I0 Mask                 */
+#define LCD_PAL152_R14_0_Pos                                  16                                                        /*!< LCD PAL152: R14_0 Position          */
+#define LCD_PAL152_R14_0_Msk                                  (0x1fUL << LCD_PAL152_R14_0_Pos)                          /*!< LCD PAL152: R14_0 Mask              */
+#define LCD_PAL152_G14_0_Pos                                  21                                                        /*!< LCD PAL152: G14_0 Position          */
+#define LCD_PAL152_G14_0_Msk                                  (0x1fUL << LCD_PAL152_G14_0_Pos)                          /*!< LCD PAL152: G14_0 Mask              */
+#define LCD_PAL152_B14_0_Pos                                  26                                                        /*!< LCD PAL152: B14_0 Position          */
+#define LCD_PAL152_B14_0_Msk                                  (0x1fUL << LCD_PAL152_B14_0_Pos)                          /*!< LCD PAL152: B14_0 Mask              */
+#define LCD_PAL152_I1_Pos                                     31                                                        /*!< LCD PAL152: I1 Position             */
+#define LCD_PAL152_I1_Msk                                     (0x01UL << LCD_PAL152_I1_Pos)                             /*!< LCD PAL152: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL153  -------------------------------------------
+#define LCD_PAL153_R04_0_Pos                                  0                                                         /*!< LCD PAL153: R04_0 Position          */
+#define LCD_PAL153_R04_0_Msk                                  (0x1fUL << LCD_PAL153_R04_0_Pos)                          /*!< LCD PAL153: R04_0 Mask              */
+#define LCD_PAL153_G04_0_Pos                                  5                                                         /*!< LCD PAL153: G04_0 Position          */
+#define LCD_PAL153_G04_0_Msk                                  (0x1fUL << LCD_PAL153_G04_0_Pos)                          /*!< LCD PAL153: G04_0 Mask              */
+#define LCD_PAL153_B04_0_Pos                                  10                                                        /*!< LCD PAL153: B04_0 Position          */
+#define LCD_PAL153_B04_0_Msk                                  (0x1fUL << LCD_PAL153_B04_0_Pos)                          /*!< LCD PAL153: B04_0 Mask              */
+#define LCD_PAL153_I0_Pos                                     15                                                        /*!< LCD PAL153: I0 Position             */
+#define LCD_PAL153_I0_Msk                                     (0x01UL << LCD_PAL153_I0_Pos)                             /*!< LCD PAL153: I0 Mask                 */
+#define LCD_PAL153_R14_0_Pos                                  16                                                        /*!< LCD PAL153: R14_0 Position          */
+#define LCD_PAL153_R14_0_Msk                                  (0x1fUL << LCD_PAL153_R14_0_Pos)                          /*!< LCD PAL153: R14_0 Mask              */
+#define LCD_PAL153_G14_0_Pos                                  21                                                        /*!< LCD PAL153: G14_0 Position          */
+#define LCD_PAL153_G14_0_Msk                                  (0x1fUL << LCD_PAL153_G14_0_Pos)                          /*!< LCD PAL153: G14_0 Mask              */
+#define LCD_PAL153_B14_0_Pos                                  26                                                        /*!< LCD PAL153: B14_0 Position          */
+#define LCD_PAL153_B14_0_Msk                                  (0x1fUL << LCD_PAL153_B14_0_Pos)                          /*!< LCD PAL153: B14_0 Mask              */
+#define LCD_PAL153_I1_Pos                                     31                                                        /*!< LCD PAL153: I1 Position             */
+#define LCD_PAL153_I1_Msk                                     (0x01UL << LCD_PAL153_I1_Pos)                             /*!< LCD PAL153: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL154  -------------------------------------------
+#define LCD_PAL154_R04_0_Pos                                  0                                                         /*!< LCD PAL154: R04_0 Position          */
+#define LCD_PAL154_R04_0_Msk                                  (0x1fUL << LCD_PAL154_R04_0_Pos)                          /*!< LCD PAL154: R04_0 Mask              */
+#define LCD_PAL154_G04_0_Pos                                  5                                                         /*!< LCD PAL154: G04_0 Position          */
+#define LCD_PAL154_G04_0_Msk                                  (0x1fUL << LCD_PAL154_G04_0_Pos)                          /*!< LCD PAL154: G04_0 Mask              */
+#define LCD_PAL154_B04_0_Pos                                  10                                                        /*!< LCD PAL154: B04_0 Position          */
+#define LCD_PAL154_B04_0_Msk                                  (0x1fUL << LCD_PAL154_B04_0_Pos)                          /*!< LCD PAL154: B04_0 Mask              */
+#define LCD_PAL154_I0_Pos                                     15                                                        /*!< LCD PAL154: I0 Position             */
+#define LCD_PAL154_I0_Msk                                     (0x01UL << LCD_PAL154_I0_Pos)                             /*!< LCD PAL154: I0 Mask                 */
+#define LCD_PAL154_R14_0_Pos                                  16                                                        /*!< LCD PAL154: R14_0 Position          */
+#define LCD_PAL154_R14_0_Msk                                  (0x1fUL << LCD_PAL154_R14_0_Pos)                          /*!< LCD PAL154: R14_0 Mask              */
+#define LCD_PAL154_G14_0_Pos                                  21                                                        /*!< LCD PAL154: G14_0 Position          */
+#define LCD_PAL154_G14_0_Msk                                  (0x1fUL << LCD_PAL154_G14_0_Pos)                          /*!< LCD PAL154: G14_0 Mask              */
+#define LCD_PAL154_B14_0_Pos                                  26                                                        /*!< LCD PAL154: B14_0 Position          */
+#define LCD_PAL154_B14_0_Msk                                  (0x1fUL << LCD_PAL154_B14_0_Pos)                          /*!< LCD PAL154: B14_0 Mask              */
+#define LCD_PAL154_I1_Pos                                     31                                                        /*!< LCD PAL154: I1 Position             */
+#define LCD_PAL154_I1_Msk                                     (0x01UL << LCD_PAL154_I1_Pos)                             /*!< LCD PAL154: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL155  -------------------------------------------
+#define LCD_PAL155_R04_0_Pos                                  0                                                         /*!< LCD PAL155: R04_0 Position          */
+#define LCD_PAL155_R04_0_Msk                                  (0x1fUL << LCD_PAL155_R04_0_Pos)                          /*!< LCD PAL155: R04_0 Mask              */
+#define LCD_PAL155_G04_0_Pos                                  5                                                         /*!< LCD PAL155: G04_0 Position          */
+#define LCD_PAL155_G04_0_Msk                                  (0x1fUL << LCD_PAL155_G04_0_Pos)                          /*!< LCD PAL155: G04_0 Mask              */
+#define LCD_PAL155_B04_0_Pos                                  10                                                        /*!< LCD PAL155: B04_0 Position          */
+#define LCD_PAL155_B04_0_Msk                                  (0x1fUL << LCD_PAL155_B04_0_Pos)                          /*!< LCD PAL155: B04_0 Mask              */
+#define LCD_PAL155_I0_Pos                                     15                                                        /*!< LCD PAL155: I0 Position             */
+#define LCD_PAL155_I0_Msk                                     (0x01UL << LCD_PAL155_I0_Pos)                             /*!< LCD PAL155: I0 Mask                 */
+#define LCD_PAL155_R14_0_Pos                                  16                                                        /*!< LCD PAL155: R14_0 Position          */
+#define LCD_PAL155_R14_0_Msk                                  (0x1fUL << LCD_PAL155_R14_0_Pos)                          /*!< LCD PAL155: R14_0 Mask              */
+#define LCD_PAL155_G14_0_Pos                                  21                                                        /*!< LCD PAL155: G14_0 Position          */
+#define LCD_PAL155_G14_0_Msk                                  (0x1fUL << LCD_PAL155_G14_0_Pos)                          /*!< LCD PAL155: G14_0 Mask              */
+#define LCD_PAL155_B14_0_Pos                                  26                                                        /*!< LCD PAL155: B14_0 Position          */
+#define LCD_PAL155_B14_0_Msk                                  (0x1fUL << LCD_PAL155_B14_0_Pos)                          /*!< LCD PAL155: B14_0 Mask              */
+#define LCD_PAL155_I1_Pos                                     31                                                        /*!< LCD PAL155: I1 Position             */
+#define LCD_PAL155_I1_Msk                                     (0x01UL << LCD_PAL155_I1_Pos)                             /*!< LCD PAL155: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL156  -------------------------------------------
+#define LCD_PAL156_R04_0_Pos                                  0                                                         /*!< LCD PAL156: R04_0 Position          */
+#define LCD_PAL156_R04_0_Msk                                  (0x1fUL << LCD_PAL156_R04_0_Pos)                          /*!< LCD PAL156: R04_0 Mask              */
+#define LCD_PAL156_G04_0_Pos                                  5                                                         /*!< LCD PAL156: G04_0 Position          */
+#define LCD_PAL156_G04_0_Msk                                  (0x1fUL << LCD_PAL156_G04_0_Pos)                          /*!< LCD PAL156: G04_0 Mask              */
+#define LCD_PAL156_B04_0_Pos                                  10                                                        /*!< LCD PAL156: B04_0 Position          */
+#define LCD_PAL156_B04_0_Msk                                  (0x1fUL << LCD_PAL156_B04_0_Pos)                          /*!< LCD PAL156: B04_0 Mask              */
+#define LCD_PAL156_I0_Pos                                     15                                                        /*!< LCD PAL156: I0 Position             */
+#define LCD_PAL156_I0_Msk                                     (0x01UL << LCD_PAL156_I0_Pos)                             /*!< LCD PAL156: I0 Mask                 */
+#define LCD_PAL156_R14_0_Pos                                  16                                                        /*!< LCD PAL156: R14_0 Position          */
+#define LCD_PAL156_R14_0_Msk                                  (0x1fUL << LCD_PAL156_R14_0_Pos)                          /*!< LCD PAL156: R14_0 Mask              */
+#define LCD_PAL156_G14_0_Pos                                  21                                                        /*!< LCD PAL156: G14_0 Position          */
+#define LCD_PAL156_G14_0_Msk                                  (0x1fUL << LCD_PAL156_G14_0_Pos)                          /*!< LCD PAL156: G14_0 Mask              */
+#define LCD_PAL156_B14_0_Pos                                  26                                                        /*!< LCD PAL156: B14_0 Position          */
+#define LCD_PAL156_B14_0_Msk                                  (0x1fUL << LCD_PAL156_B14_0_Pos)                          /*!< LCD PAL156: B14_0 Mask              */
+#define LCD_PAL156_I1_Pos                                     31                                                        /*!< LCD PAL156: I1 Position             */
+#define LCD_PAL156_I1_Msk                                     (0x01UL << LCD_PAL156_I1_Pos)                             /*!< LCD PAL156: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL157  -------------------------------------------
+#define LCD_PAL157_R04_0_Pos                                  0                                                         /*!< LCD PAL157: R04_0 Position          */
+#define LCD_PAL157_R04_0_Msk                                  (0x1fUL << LCD_PAL157_R04_0_Pos)                          /*!< LCD PAL157: R04_0 Mask              */
+#define LCD_PAL157_G04_0_Pos                                  5                                                         /*!< LCD PAL157: G04_0 Position          */
+#define LCD_PAL157_G04_0_Msk                                  (0x1fUL << LCD_PAL157_G04_0_Pos)                          /*!< LCD PAL157: G04_0 Mask              */
+#define LCD_PAL157_B04_0_Pos                                  10                                                        /*!< LCD PAL157: B04_0 Position          */
+#define LCD_PAL157_B04_0_Msk                                  (0x1fUL << LCD_PAL157_B04_0_Pos)                          /*!< LCD PAL157: B04_0 Mask              */
+#define LCD_PAL157_I0_Pos                                     15                                                        /*!< LCD PAL157: I0 Position             */
+#define LCD_PAL157_I0_Msk                                     (0x01UL << LCD_PAL157_I0_Pos)                             /*!< LCD PAL157: I0 Mask                 */
+#define LCD_PAL157_R14_0_Pos                                  16                                                        /*!< LCD PAL157: R14_0 Position          */
+#define LCD_PAL157_R14_0_Msk                                  (0x1fUL << LCD_PAL157_R14_0_Pos)                          /*!< LCD PAL157: R14_0 Mask              */
+#define LCD_PAL157_G14_0_Pos                                  21                                                        /*!< LCD PAL157: G14_0 Position          */
+#define LCD_PAL157_G14_0_Msk                                  (0x1fUL << LCD_PAL157_G14_0_Pos)                          /*!< LCD PAL157: G14_0 Mask              */
+#define LCD_PAL157_B14_0_Pos                                  26                                                        /*!< LCD PAL157: B14_0 Position          */
+#define LCD_PAL157_B14_0_Msk                                  (0x1fUL << LCD_PAL157_B14_0_Pos)                          /*!< LCD PAL157: B14_0 Mask              */
+#define LCD_PAL157_I1_Pos                                     31                                                        /*!< LCD PAL157: I1 Position             */
+#define LCD_PAL157_I1_Msk                                     (0x01UL << LCD_PAL157_I1_Pos)                             /*!< LCD PAL157: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL158  -------------------------------------------
+#define LCD_PAL158_R04_0_Pos                                  0                                                         /*!< LCD PAL158: R04_0 Position          */
+#define LCD_PAL158_R04_0_Msk                                  (0x1fUL << LCD_PAL158_R04_0_Pos)                          /*!< LCD PAL158: R04_0 Mask              */
+#define LCD_PAL158_G04_0_Pos                                  5                                                         /*!< LCD PAL158: G04_0 Position          */
+#define LCD_PAL158_G04_0_Msk                                  (0x1fUL << LCD_PAL158_G04_0_Pos)                          /*!< LCD PAL158: G04_0 Mask              */
+#define LCD_PAL158_B04_0_Pos                                  10                                                        /*!< LCD PAL158: B04_0 Position          */
+#define LCD_PAL158_B04_0_Msk                                  (0x1fUL << LCD_PAL158_B04_0_Pos)                          /*!< LCD PAL158: B04_0 Mask              */
+#define LCD_PAL158_I0_Pos                                     15                                                        /*!< LCD PAL158: I0 Position             */
+#define LCD_PAL158_I0_Msk                                     (0x01UL << LCD_PAL158_I0_Pos)                             /*!< LCD PAL158: I0 Mask                 */
+#define LCD_PAL158_R14_0_Pos                                  16                                                        /*!< LCD PAL158: R14_0 Position          */
+#define LCD_PAL158_R14_0_Msk                                  (0x1fUL << LCD_PAL158_R14_0_Pos)                          /*!< LCD PAL158: R14_0 Mask              */
+#define LCD_PAL158_G14_0_Pos                                  21                                                        /*!< LCD PAL158: G14_0 Position          */
+#define LCD_PAL158_G14_0_Msk                                  (0x1fUL << LCD_PAL158_G14_0_Pos)                          /*!< LCD PAL158: G14_0 Mask              */
+#define LCD_PAL158_B14_0_Pos                                  26                                                        /*!< LCD PAL158: B14_0 Position          */
+#define LCD_PAL158_B14_0_Msk                                  (0x1fUL << LCD_PAL158_B14_0_Pos)                          /*!< LCD PAL158: B14_0 Mask              */
+#define LCD_PAL158_I1_Pos                                     31                                                        /*!< LCD PAL158: I1 Position             */
+#define LCD_PAL158_I1_Msk                                     (0x01UL << LCD_PAL158_I1_Pos)                             /*!< LCD PAL158: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL159  -------------------------------------------
+#define LCD_PAL159_R04_0_Pos                                  0                                                         /*!< LCD PAL159: R04_0 Position          */
+#define LCD_PAL159_R04_0_Msk                                  (0x1fUL << LCD_PAL159_R04_0_Pos)                          /*!< LCD PAL159: R04_0 Mask              */
+#define LCD_PAL159_G04_0_Pos                                  5                                                         /*!< LCD PAL159: G04_0 Position          */
+#define LCD_PAL159_G04_0_Msk                                  (0x1fUL << LCD_PAL159_G04_0_Pos)                          /*!< LCD PAL159: G04_0 Mask              */
+#define LCD_PAL159_B04_0_Pos                                  10                                                        /*!< LCD PAL159: B04_0 Position          */
+#define LCD_PAL159_B04_0_Msk                                  (0x1fUL << LCD_PAL159_B04_0_Pos)                          /*!< LCD PAL159: B04_0 Mask              */
+#define LCD_PAL159_I0_Pos                                     15                                                        /*!< LCD PAL159: I0 Position             */
+#define LCD_PAL159_I0_Msk                                     (0x01UL << LCD_PAL159_I0_Pos)                             /*!< LCD PAL159: I0 Mask                 */
+#define LCD_PAL159_R14_0_Pos                                  16                                                        /*!< LCD PAL159: R14_0 Position          */
+#define LCD_PAL159_R14_0_Msk                                  (0x1fUL << LCD_PAL159_R14_0_Pos)                          /*!< LCD PAL159: R14_0 Mask              */
+#define LCD_PAL159_G14_0_Pos                                  21                                                        /*!< LCD PAL159: G14_0 Position          */
+#define LCD_PAL159_G14_0_Msk                                  (0x1fUL << LCD_PAL159_G14_0_Pos)                          /*!< LCD PAL159: G14_0 Mask              */
+#define LCD_PAL159_B14_0_Pos                                  26                                                        /*!< LCD PAL159: B14_0 Position          */
+#define LCD_PAL159_B14_0_Msk                                  (0x1fUL << LCD_PAL159_B14_0_Pos)                          /*!< LCD PAL159: B14_0 Mask              */
+#define LCD_PAL159_I1_Pos                                     31                                                        /*!< LCD PAL159: I1 Position             */
+#define LCD_PAL159_I1_Msk                                     (0x01UL << LCD_PAL159_I1_Pos)                             /*!< LCD PAL159: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL160  -------------------------------------------
+#define LCD_PAL160_R04_0_Pos                                  0                                                         /*!< LCD PAL160: R04_0 Position          */
+#define LCD_PAL160_R04_0_Msk                                  (0x1fUL << LCD_PAL160_R04_0_Pos)                          /*!< LCD PAL160: R04_0 Mask              */
+#define LCD_PAL160_G04_0_Pos                                  5                                                         /*!< LCD PAL160: G04_0 Position          */
+#define LCD_PAL160_G04_0_Msk                                  (0x1fUL << LCD_PAL160_G04_0_Pos)                          /*!< LCD PAL160: G04_0 Mask              */
+#define LCD_PAL160_B04_0_Pos                                  10                                                        /*!< LCD PAL160: B04_0 Position          */
+#define LCD_PAL160_B04_0_Msk                                  (0x1fUL << LCD_PAL160_B04_0_Pos)                          /*!< LCD PAL160: B04_0 Mask              */
+#define LCD_PAL160_I0_Pos                                     15                                                        /*!< LCD PAL160: I0 Position             */
+#define LCD_PAL160_I0_Msk                                     (0x01UL << LCD_PAL160_I0_Pos)                             /*!< LCD PAL160: I0 Mask                 */
+#define LCD_PAL160_R14_0_Pos                                  16                                                        /*!< LCD PAL160: R14_0 Position          */
+#define LCD_PAL160_R14_0_Msk                                  (0x1fUL << LCD_PAL160_R14_0_Pos)                          /*!< LCD PAL160: R14_0 Mask              */
+#define LCD_PAL160_G14_0_Pos                                  21                                                        /*!< LCD PAL160: G14_0 Position          */
+#define LCD_PAL160_G14_0_Msk                                  (0x1fUL << LCD_PAL160_G14_0_Pos)                          /*!< LCD PAL160: G14_0 Mask              */
+#define LCD_PAL160_B14_0_Pos                                  26                                                        /*!< LCD PAL160: B14_0 Position          */
+#define LCD_PAL160_B14_0_Msk                                  (0x1fUL << LCD_PAL160_B14_0_Pos)                          /*!< LCD PAL160: B14_0 Mask              */
+#define LCD_PAL160_I1_Pos                                     31                                                        /*!< LCD PAL160: I1 Position             */
+#define LCD_PAL160_I1_Msk                                     (0x01UL << LCD_PAL160_I1_Pos)                             /*!< LCD PAL160: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL161  -------------------------------------------
+#define LCD_PAL161_R04_0_Pos                                  0                                                         /*!< LCD PAL161: R04_0 Position          */
+#define LCD_PAL161_R04_0_Msk                                  (0x1fUL << LCD_PAL161_R04_0_Pos)                          /*!< LCD PAL161: R04_0 Mask              */
+#define LCD_PAL161_G04_0_Pos                                  5                                                         /*!< LCD PAL161: G04_0 Position          */
+#define LCD_PAL161_G04_0_Msk                                  (0x1fUL << LCD_PAL161_G04_0_Pos)                          /*!< LCD PAL161: G04_0 Mask              */
+#define LCD_PAL161_B04_0_Pos                                  10                                                        /*!< LCD PAL161: B04_0 Position          */
+#define LCD_PAL161_B04_0_Msk                                  (0x1fUL << LCD_PAL161_B04_0_Pos)                          /*!< LCD PAL161: B04_0 Mask              */
+#define LCD_PAL161_I0_Pos                                     15                                                        /*!< LCD PAL161: I0 Position             */
+#define LCD_PAL161_I0_Msk                                     (0x01UL << LCD_PAL161_I0_Pos)                             /*!< LCD PAL161: I0 Mask                 */
+#define LCD_PAL161_R14_0_Pos                                  16                                                        /*!< LCD PAL161: R14_0 Position          */
+#define LCD_PAL161_R14_0_Msk                                  (0x1fUL << LCD_PAL161_R14_0_Pos)                          /*!< LCD PAL161: R14_0 Mask              */
+#define LCD_PAL161_G14_0_Pos                                  21                                                        /*!< LCD PAL161: G14_0 Position          */
+#define LCD_PAL161_G14_0_Msk                                  (0x1fUL << LCD_PAL161_G14_0_Pos)                          /*!< LCD PAL161: G14_0 Mask              */
+#define LCD_PAL161_B14_0_Pos                                  26                                                        /*!< LCD PAL161: B14_0 Position          */
+#define LCD_PAL161_B14_0_Msk                                  (0x1fUL << LCD_PAL161_B14_0_Pos)                          /*!< LCD PAL161: B14_0 Mask              */
+#define LCD_PAL161_I1_Pos                                     31                                                        /*!< LCD PAL161: I1 Position             */
+#define LCD_PAL161_I1_Msk                                     (0x01UL << LCD_PAL161_I1_Pos)                             /*!< LCD PAL161: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL162  -------------------------------------------
+#define LCD_PAL162_R04_0_Pos                                  0                                                         /*!< LCD PAL162: R04_0 Position          */
+#define LCD_PAL162_R04_0_Msk                                  (0x1fUL << LCD_PAL162_R04_0_Pos)                          /*!< LCD PAL162: R04_0 Mask              */
+#define LCD_PAL162_G04_0_Pos                                  5                                                         /*!< LCD PAL162: G04_0 Position          */
+#define LCD_PAL162_G04_0_Msk                                  (0x1fUL << LCD_PAL162_G04_0_Pos)                          /*!< LCD PAL162: G04_0 Mask              */
+#define LCD_PAL162_B04_0_Pos                                  10                                                        /*!< LCD PAL162: B04_0 Position          */
+#define LCD_PAL162_B04_0_Msk                                  (0x1fUL << LCD_PAL162_B04_0_Pos)                          /*!< LCD PAL162: B04_0 Mask              */
+#define LCD_PAL162_I0_Pos                                     15                                                        /*!< LCD PAL162: I0 Position             */
+#define LCD_PAL162_I0_Msk                                     (0x01UL << LCD_PAL162_I0_Pos)                             /*!< LCD PAL162: I0 Mask                 */
+#define LCD_PAL162_R14_0_Pos                                  16                                                        /*!< LCD PAL162: R14_0 Position          */
+#define LCD_PAL162_R14_0_Msk                                  (0x1fUL << LCD_PAL162_R14_0_Pos)                          /*!< LCD PAL162: R14_0 Mask              */
+#define LCD_PAL162_G14_0_Pos                                  21                                                        /*!< LCD PAL162: G14_0 Position          */
+#define LCD_PAL162_G14_0_Msk                                  (0x1fUL << LCD_PAL162_G14_0_Pos)                          /*!< LCD PAL162: G14_0 Mask              */
+#define LCD_PAL162_B14_0_Pos                                  26                                                        /*!< LCD PAL162: B14_0 Position          */
+#define LCD_PAL162_B14_0_Msk                                  (0x1fUL << LCD_PAL162_B14_0_Pos)                          /*!< LCD PAL162: B14_0 Mask              */
+#define LCD_PAL162_I1_Pos                                     31                                                        /*!< LCD PAL162: I1 Position             */
+#define LCD_PAL162_I1_Msk                                     (0x01UL << LCD_PAL162_I1_Pos)                             /*!< LCD PAL162: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL163  -------------------------------------------
+#define LCD_PAL163_R04_0_Pos                                  0                                                         /*!< LCD PAL163: R04_0 Position          */
+#define LCD_PAL163_R04_0_Msk                                  (0x1fUL << LCD_PAL163_R04_0_Pos)                          /*!< LCD PAL163: R04_0 Mask              */
+#define LCD_PAL163_G04_0_Pos                                  5                                                         /*!< LCD PAL163: G04_0 Position          */
+#define LCD_PAL163_G04_0_Msk                                  (0x1fUL << LCD_PAL163_G04_0_Pos)                          /*!< LCD PAL163: G04_0 Mask              */
+#define LCD_PAL163_B04_0_Pos                                  10                                                        /*!< LCD PAL163: B04_0 Position          */
+#define LCD_PAL163_B04_0_Msk                                  (0x1fUL << LCD_PAL163_B04_0_Pos)                          /*!< LCD PAL163: B04_0 Mask              */
+#define LCD_PAL163_I0_Pos                                     15                                                        /*!< LCD PAL163: I0 Position             */
+#define LCD_PAL163_I0_Msk                                     (0x01UL << LCD_PAL163_I0_Pos)                             /*!< LCD PAL163: I0 Mask                 */
+#define LCD_PAL163_R14_0_Pos                                  16                                                        /*!< LCD PAL163: R14_0 Position          */
+#define LCD_PAL163_R14_0_Msk                                  (0x1fUL << LCD_PAL163_R14_0_Pos)                          /*!< LCD PAL163: R14_0 Mask              */
+#define LCD_PAL163_G14_0_Pos                                  21                                                        /*!< LCD PAL163: G14_0 Position          */
+#define LCD_PAL163_G14_0_Msk                                  (0x1fUL << LCD_PAL163_G14_0_Pos)                          /*!< LCD PAL163: G14_0 Mask              */
+#define LCD_PAL163_B14_0_Pos                                  26                                                        /*!< LCD PAL163: B14_0 Position          */
+#define LCD_PAL163_B14_0_Msk                                  (0x1fUL << LCD_PAL163_B14_0_Pos)                          /*!< LCD PAL163: B14_0 Mask              */
+#define LCD_PAL163_I1_Pos                                     31                                                        /*!< LCD PAL163: I1 Position             */
+#define LCD_PAL163_I1_Msk                                     (0x01UL << LCD_PAL163_I1_Pos)                             /*!< LCD PAL163: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL164  -------------------------------------------
+#define LCD_PAL164_R04_0_Pos                                  0                                                         /*!< LCD PAL164: R04_0 Position          */
+#define LCD_PAL164_R04_0_Msk                                  (0x1fUL << LCD_PAL164_R04_0_Pos)                          /*!< LCD PAL164: R04_0 Mask              */
+#define LCD_PAL164_G04_0_Pos                                  5                                                         /*!< LCD PAL164: G04_0 Position          */
+#define LCD_PAL164_G04_0_Msk                                  (0x1fUL << LCD_PAL164_G04_0_Pos)                          /*!< LCD PAL164: G04_0 Mask              */
+#define LCD_PAL164_B04_0_Pos                                  10                                                        /*!< LCD PAL164: B04_0 Position          */
+#define LCD_PAL164_B04_0_Msk                                  (0x1fUL << LCD_PAL164_B04_0_Pos)                          /*!< LCD PAL164: B04_0 Mask              */
+#define LCD_PAL164_I0_Pos                                     15                                                        /*!< LCD PAL164: I0 Position             */
+#define LCD_PAL164_I0_Msk                                     (0x01UL << LCD_PAL164_I0_Pos)                             /*!< LCD PAL164: I0 Mask                 */
+#define LCD_PAL164_R14_0_Pos                                  16                                                        /*!< LCD PAL164: R14_0 Position          */
+#define LCD_PAL164_R14_0_Msk                                  (0x1fUL << LCD_PAL164_R14_0_Pos)                          /*!< LCD PAL164: R14_0 Mask              */
+#define LCD_PAL164_G14_0_Pos                                  21                                                        /*!< LCD PAL164: G14_0 Position          */
+#define LCD_PAL164_G14_0_Msk                                  (0x1fUL << LCD_PAL164_G14_0_Pos)                          /*!< LCD PAL164: G14_0 Mask              */
+#define LCD_PAL164_B14_0_Pos                                  26                                                        /*!< LCD PAL164: B14_0 Position          */
+#define LCD_PAL164_B14_0_Msk                                  (0x1fUL << LCD_PAL164_B14_0_Pos)                          /*!< LCD PAL164: B14_0 Mask              */
+#define LCD_PAL164_I1_Pos                                     31                                                        /*!< LCD PAL164: I1 Position             */
+#define LCD_PAL164_I1_Msk                                     (0x01UL << LCD_PAL164_I1_Pos)                             /*!< LCD PAL164: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL165  -------------------------------------------
+#define LCD_PAL165_R04_0_Pos                                  0                                                         /*!< LCD PAL165: R04_0 Position          */
+#define LCD_PAL165_R04_0_Msk                                  (0x1fUL << LCD_PAL165_R04_0_Pos)                          /*!< LCD PAL165: R04_0 Mask              */
+#define LCD_PAL165_G04_0_Pos                                  5                                                         /*!< LCD PAL165: G04_0 Position          */
+#define LCD_PAL165_G04_0_Msk                                  (0x1fUL << LCD_PAL165_G04_0_Pos)                          /*!< LCD PAL165: G04_0 Mask              */
+#define LCD_PAL165_B04_0_Pos                                  10                                                        /*!< LCD PAL165: B04_0 Position          */
+#define LCD_PAL165_B04_0_Msk                                  (0x1fUL << LCD_PAL165_B04_0_Pos)                          /*!< LCD PAL165: B04_0 Mask              */
+#define LCD_PAL165_I0_Pos                                     15                                                        /*!< LCD PAL165: I0 Position             */
+#define LCD_PAL165_I0_Msk                                     (0x01UL << LCD_PAL165_I0_Pos)                             /*!< LCD PAL165: I0 Mask                 */
+#define LCD_PAL165_R14_0_Pos                                  16                                                        /*!< LCD PAL165: R14_0 Position          */
+#define LCD_PAL165_R14_0_Msk                                  (0x1fUL << LCD_PAL165_R14_0_Pos)                          /*!< LCD PAL165: R14_0 Mask              */
+#define LCD_PAL165_G14_0_Pos                                  21                                                        /*!< LCD PAL165: G14_0 Position          */
+#define LCD_PAL165_G14_0_Msk                                  (0x1fUL << LCD_PAL165_G14_0_Pos)                          /*!< LCD PAL165: G14_0 Mask              */
+#define LCD_PAL165_B14_0_Pos                                  26                                                        /*!< LCD PAL165: B14_0 Position          */
+#define LCD_PAL165_B14_0_Msk                                  (0x1fUL << LCD_PAL165_B14_0_Pos)                          /*!< LCD PAL165: B14_0 Mask              */
+#define LCD_PAL165_I1_Pos                                     31                                                        /*!< LCD PAL165: I1 Position             */
+#define LCD_PAL165_I1_Msk                                     (0x01UL << LCD_PAL165_I1_Pos)                             /*!< LCD PAL165: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL166  -------------------------------------------
+#define LCD_PAL166_R04_0_Pos                                  0                                                         /*!< LCD PAL166: R04_0 Position          */
+#define LCD_PAL166_R04_0_Msk                                  (0x1fUL << LCD_PAL166_R04_0_Pos)                          /*!< LCD PAL166: R04_0 Mask              */
+#define LCD_PAL166_G04_0_Pos                                  5                                                         /*!< LCD PAL166: G04_0 Position          */
+#define LCD_PAL166_G04_0_Msk                                  (0x1fUL << LCD_PAL166_G04_0_Pos)                          /*!< LCD PAL166: G04_0 Mask              */
+#define LCD_PAL166_B04_0_Pos                                  10                                                        /*!< LCD PAL166: B04_0 Position          */
+#define LCD_PAL166_B04_0_Msk                                  (0x1fUL << LCD_PAL166_B04_0_Pos)                          /*!< LCD PAL166: B04_0 Mask              */
+#define LCD_PAL166_I0_Pos                                     15                                                        /*!< LCD PAL166: I0 Position             */
+#define LCD_PAL166_I0_Msk                                     (0x01UL << LCD_PAL166_I0_Pos)                             /*!< LCD PAL166: I0 Mask                 */
+#define LCD_PAL166_R14_0_Pos                                  16                                                        /*!< LCD PAL166: R14_0 Position          */
+#define LCD_PAL166_R14_0_Msk                                  (0x1fUL << LCD_PAL166_R14_0_Pos)                          /*!< LCD PAL166: R14_0 Mask              */
+#define LCD_PAL166_G14_0_Pos                                  21                                                        /*!< LCD PAL166: G14_0 Position          */
+#define LCD_PAL166_G14_0_Msk                                  (0x1fUL << LCD_PAL166_G14_0_Pos)                          /*!< LCD PAL166: G14_0 Mask              */
+#define LCD_PAL166_B14_0_Pos                                  26                                                        /*!< LCD PAL166: B14_0 Position          */
+#define LCD_PAL166_B14_0_Msk                                  (0x1fUL << LCD_PAL166_B14_0_Pos)                          /*!< LCD PAL166: B14_0 Mask              */
+#define LCD_PAL166_I1_Pos                                     31                                                        /*!< LCD PAL166: I1 Position             */
+#define LCD_PAL166_I1_Msk                                     (0x01UL << LCD_PAL166_I1_Pos)                             /*!< LCD PAL166: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL167  -------------------------------------------
+#define LCD_PAL167_R04_0_Pos                                  0                                                         /*!< LCD PAL167: R04_0 Position          */
+#define LCD_PAL167_R04_0_Msk                                  (0x1fUL << LCD_PAL167_R04_0_Pos)                          /*!< LCD PAL167: R04_0 Mask              */
+#define LCD_PAL167_G04_0_Pos                                  5                                                         /*!< LCD PAL167: G04_0 Position          */
+#define LCD_PAL167_G04_0_Msk                                  (0x1fUL << LCD_PAL167_G04_0_Pos)                          /*!< LCD PAL167: G04_0 Mask              */
+#define LCD_PAL167_B04_0_Pos                                  10                                                        /*!< LCD PAL167: B04_0 Position          */
+#define LCD_PAL167_B04_0_Msk                                  (0x1fUL << LCD_PAL167_B04_0_Pos)                          /*!< LCD PAL167: B04_0 Mask              */
+#define LCD_PAL167_I0_Pos                                     15                                                        /*!< LCD PAL167: I0 Position             */
+#define LCD_PAL167_I0_Msk                                     (0x01UL << LCD_PAL167_I0_Pos)                             /*!< LCD PAL167: I0 Mask                 */
+#define LCD_PAL167_R14_0_Pos                                  16                                                        /*!< LCD PAL167: R14_0 Position          */
+#define LCD_PAL167_R14_0_Msk                                  (0x1fUL << LCD_PAL167_R14_0_Pos)                          /*!< LCD PAL167: R14_0 Mask              */
+#define LCD_PAL167_G14_0_Pos                                  21                                                        /*!< LCD PAL167: G14_0 Position          */
+#define LCD_PAL167_G14_0_Msk                                  (0x1fUL << LCD_PAL167_G14_0_Pos)                          /*!< LCD PAL167: G14_0 Mask              */
+#define LCD_PAL167_B14_0_Pos                                  26                                                        /*!< LCD PAL167: B14_0 Position          */
+#define LCD_PAL167_B14_0_Msk                                  (0x1fUL << LCD_PAL167_B14_0_Pos)                          /*!< LCD PAL167: B14_0 Mask              */
+#define LCD_PAL167_I1_Pos                                     31                                                        /*!< LCD PAL167: I1 Position             */
+#define LCD_PAL167_I1_Msk                                     (0x01UL << LCD_PAL167_I1_Pos)                             /*!< LCD PAL167: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL168  -------------------------------------------
+#define LCD_PAL168_R04_0_Pos                                  0                                                         /*!< LCD PAL168: R04_0 Position          */
+#define LCD_PAL168_R04_0_Msk                                  (0x1fUL << LCD_PAL168_R04_0_Pos)                          /*!< LCD PAL168: R04_0 Mask              */
+#define LCD_PAL168_G04_0_Pos                                  5                                                         /*!< LCD PAL168: G04_0 Position          */
+#define LCD_PAL168_G04_0_Msk                                  (0x1fUL << LCD_PAL168_G04_0_Pos)                          /*!< LCD PAL168: G04_0 Mask              */
+#define LCD_PAL168_B04_0_Pos                                  10                                                        /*!< LCD PAL168: B04_0 Position          */
+#define LCD_PAL168_B04_0_Msk                                  (0x1fUL << LCD_PAL168_B04_0_Pos)                          /*!< LCD PAL168: B04_0 Mask              */
+#define LCD_PAL168_I0_Pos                                     15                                                        /*!< LCD PAL168: I0 Position             */
+#define LCD_PAL168_I0_Msk                                     (0x01UL << LCD_PAL168_I0_Pos)                             /*!< LCD PAL168: I0 Mask                 */
+#define LCD_PAL168_R14_0_Pos                                  16                                                        /*!< LCD PAL168: R14_0 Position          */
+#define LCD_PAL168_R14_0_Msk                                  (0x1fUL << LCD_PAL168_R14_0_Pos)                          /*!< LCD PAL168: R14_0 Mask              */
+#define LCD_PAL168_G14_0_Pos                                  21                                                        /*!< LCD PAL168: G14_0 Position          */
+#define LCD_PAL168_G14_0_Msk                                  (0x1fUL << LCD_PAL168_G14_0_Pos)                          /*!< LCD PAL168: G14_0 Mask              */
+#define LCD_PAL168_B14_0_Pos                                  26                                                        /*!< LCD PAL168: B14_0 Position          */
+#define LCD_PAL168_B14_0_Msk                                  (0x1fUL << LCD_PAL168_B14_0_Pos)                          /*!< LCD PAL168: B14_0 Mask              */
+#define LCD_PAL168_I1_Pos                                     31                                                        /*!< LCD PAL168: I1 Position             */
+#define LCD_PAL168_I1_Msk                                     (0x01UL << LCD_PAL168_I1_Pos)                             /*!< LCD PAL168: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL169  -------------------------------------------
+#define LCD_PAL169_R04_0_Pos                                  0                                                         /*!< LCD PAL169: R04_0 Position          */
+#define LCD_PAL169_R04_0_Msk                                  (0x1fUL << LCD_PAL169_R04_0_Pos)                          /*!< LCD PAL169: R04_0 Mask              */
+#define LCD_PAL169_G04_0_Pos                                  5                                                         /*!< LCD PAL169: G04_0 Position          */
+#define LCD_PAL169_G04_0_Msk                                  (0x1fUL << LCD_PAL169_G04_0_Pos)                          /*!< LCD PAL169: G04_0 Mask              */
+#define LCD_PAL169_B04_0_Pos                                  10                                                        /*!< LCD PAL169: B04_0 Position          */
+#define LCD_PAL169_B04_0_Msk                                  (0x1fUL << LCD_PAL169_B04_0_Pos)                          /*!< LCD PAL169: B04_0 Mask              */
+#define LCD_PAL169_I0_Pos                                     15                                                        /*!< LCD PAL169: I0 Position             */
+#define LCD_PAL169_I0_Msk                                     (0x01UL << LCD_PAL169_I0_Pos)                             /*!< LCD PAL169: I0 Mask                 */
+#define LCD_PAL169_R14_0_Pos                                  16                                                        /*!< LCD PAL169: R14_0 Position          */
+#define LCD_PAL169_R14_0_Msk                                  (0x1fUL << LCD_PAL169_R14_0_Pos)                          /*!< LCD PAL169: R14_0 Mask              */
+#define LCD_PAL169_G14_0_Pos                                  21                                                        /*!< LCD PAL169: G14_0 Position          */
+#define LCD_PAL169_G14_0_Msk                                  (0x1fUL << LCD_PAL169_G14_0_Pos)                          /*!< LCD PAL169: G14_0 Mask              */
+#define LCD_PAL169_B14_0_Pos                                  26                                                        /*!< LCD PAL169: B14_0 Position          */
+#define LCD_PAL169_B14_0_Msk                                  (0x1fUL << LCD_PAL169_B14_0_Pos)                          /*!< LCD PAL169: B14_0 Mask              */
+#define LCD_PAL169_I1_Pos                                     31                                                        /*!< LCD PAL169: I1 Position             */
+#define LCD_PAL169_I1_Msk                                     (0x01UL << LCD_PAL169_I1_Pos)                             /*!< LCD PAL169: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL170  -------------------------------------------
+#define LCD_PAL170_R04_0_Pos                                  0                                                         /*!< LCD PAL170: R04_0 Position          */
+#define LCD_PAL170_R04_0_Msk                                  (0x1fUL << LCD_PAL170_R04_0_Pos)                          /*!< LCD PAL170: R04_0 Mask              */
+#define LCD_PAL170_G04_0_Pos                                  5                                                         /*!< LCD PAL170: G04_0 Position          */
+#define LCD_PAL170_G04_0_Msk                                  (0x1fUL << LCD_PAL170_G04_0_Pos)                          /*!< LCD PAL170: G04_0 Mask              */
+#define LCD_PAL170_B04_0_Pos                                  10                                                        /*!< LCD PAL170: B04_0 Position          */
+#define LCD_PAL170_B04_0_Msk                                  (0x1fUL << LCD_PAL170_B04_0_Pos)                          /*!< LCD PAL170: B04_0 Mask              */
+#define LCD_PAL170_I0_Pos                                     15                                                        /*!< LCD PAL170: I0 Position             */
+#define LCD_PAL170_I0_Msk                                     (0x01UL << LCD_PAL170_I0_Pos)                             /*!< LCD PAL170: I0 Mask                 */
+#define LCD_PAL170_R14_0_Pos                                  16                                                        /*!< LCD PAL170: R14_0 Position          */
+#define LCD_PAL170_R14_0_Msk                                  (0x1fUL << LCD_PAL170_R14_0_Pos)                          /*!< LCD PAL170: R14_0 Mask              */
+#define LCD_PAL170_G14_0_Pos                                  21                                                        /*!< LCD PAL170: G14_0 Position          */
+#define LCD_PAL170_G14_0_Msk                                  (0x1fUL << LCD_PAL170_G14_0_Pos)                          /*!< LCD PAL170: G14_0 Mask              */
+#define LCD_PAL170_B14_0_Pos                                  26                                                        /*!< LCD PAL170: B14_0 Position          */
+#define LCD_PAL170_B14_0_Msk                                  (0x1fUL << LCD_PAL170_B14_0_Pos)                          /*!< LCD PAL170: B14_0 Mask              */
+#define LCD_PAL170_I1_Pos                                     31                                                        /*!< LCD PAL170: I1 Position             */
+#define LCD_PAL170_I1_Msk                                     (0x01UL << LCD_PAL170_I1_Pos)                             /*!< LCD PAL170: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL171  -------------------------------------------
+#define LCD_PAL171_R04_0_Pos                                  0                                                         /*!< LCD PAL171: R04_0 Position          */
+#define LCD_PAL171_R04_0_Msk                                  (0x1fUL << LCD_PAL171_R04_0_Pos)                          /*!< LCD PAL171: R04_0 Mask              */
+#define LCD_PAL171_G04_0_Pos                                  5                                                         /*!< LCD PAL171: G04_0 Position          */
+#define LCD_PAL171_G04_0_Msk                                  (0x1fUL << LCD_PAL171_G04_0_Pos)                          /*!< LCD PAL171: G04_0 Mask              */
+#define LCD_PAL171_B04_0_Pos                                  10                                                        /*!< LCD PAL171: B04_0 Position          */
+#define LCD_PAL171_B04_0_Msk                                  (0x1fUL << LCD_PAL171_B04_0_Pos)                          /*!< LCD PAL171: B04_0 Mask              */
+#define LCD_PAL171_I0_Pos                                     15                                                        /*!< LCD PAL171: I0 Position             */
+#define LCD_PAL171_I0_Msk                                     (0x01UL << LCD_PAL171_I0_Pos)                             /*!< LCD PAL171: I0 Mask                 */
+#define LCD_PAL171_R14_0_Pos                                  16                                                        /*!< LCD PAL171: R14_0 Position          */
+#define LCD_PAL171_R14_0_Msk                                  (0x1fUL << LCD_PAL171_R14_0_Pos)                          /*!< LCD PAL171: R14_0 Mask              */
+#define LCD_PAL171_G14_0_Pos                                  21                                                        /*!< LCD PAL171: G14_0 Position          */
+#define LCD_PAL171_G14_0_Msk                                  (0x1fUL << LCD_PAL171_G14_0_Pos)                          /*!< LCD PAL171: G14_0 Mask              */
+#define LCD_PAL171_B14_0_Pos                                  26                                                        /*!< LCD PAL171: B14_0 Position          */
+#define LCD_PAL171_B14_0_Msk                                  (0x1fUL << LCD_PAL171_B14_0_Pos)                          /*!< LCD PAL171: B14_0 Mask              */
+#define LCD_PAL171_I1_Pos                                     31                                                        /*!< LCD PAL171: I1 Position             */
+#define LCD_PAL171_I1_Msk                                     (0x01UL << LCD_PAL171_I1_Pos)                             /*!< LCD PAL171: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL172  -------------------------------------------
+#define LCD_PAL172_R04_0_Pos                                  0                                                         /*!< LCD PAL172: R04_0 Position          */
+#define LCD_PAL172_R04_0_Msk                                  (0x1fUL << LCD_PAL172_R04_0_Pos)                          /*!< LCD PAL172: R04_0 Mask              */
+#define LCD_PAL172_G04_0_Pos                                  5                                                         /*!< LCD PAL172: G04_0 Position          */
+#define LCD_PAL172_G04_0_Msk                                  (0x1fUL << LCD_PAL172_G04_0_Pos)                          /*!< LCD PAL172: G04_0 Mask              */
+#define LCD_PAL172_B04_0_Pos                                  10                                                        /*!< LCD PAL172: B04_0 Position          */
+#define LCD_PAL172_B04_0_Msk                                  (0x1fUL << LCD_PAL172_B04_0_Pos)                          /*!< LCD PAL172: B04_0 Mask              */
+#define LCD_PAL172_I0_Pos                                     15                                                        /*!< LCD PAL172: I0 Position             */
+#define LCD_PAL172_I0_Msk                                     (0x01UL << LCD_PAL172_I0_Pos)                             /*!< LCD PAL172: I0 Mask                 */
+#define LCD_PAL172_R14_0_Pos                                  16                                                        /*!< LCD PAL172: R14_0 Position          */
+#define LCD_PAL172_R14_0_Msk                                  (0x1fUL << LCD_PAL172_R14_0_Pos)                          /*!< LCD PAL172: R14_0 Mask              */
+#define LCD_PAL172_G14_0_Pos                                  21                                                        /*!< LCD PAL172: G14_0 Position          */
+#define LCD_PAL172_G14_0_Msk                                  (0x1fUL << LCD_PAL172_G14_0_Pos)                          /*!< LCD PAL172: G14_0 Mask              */
+#define LCD_PAL172_B14_0_Pos                                  26                                                        /*!< LCD PAL172: B14_0 Position          */
+#define LCD_PAL172_B14_0_Msk                                  (0x1fUL << LCD_PAL172_B14_0_Pos)                          /*!< LCD PAL172: B14_0 Mask              */
+#define LCD_PAL172_I1_Pos                                     31                                                        /*!< LCD PAL172: I1 Position             */
+#define LCD_PAL172_I1_Msk                                     (0x01UL << LCD_PAL172_I1_Pos)                             /*!< LCD PAL172: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL173  -------------------------------------------
+#define LCD_PAL173_R04_0_Pos                                  0                                                         /*!< LCD PAL173: R04_0 Position          */
+#define LCD_PAL173_R04_0_Msk                                  (0x1fUL << LCD_PAL173_R04_0_Pos)                          /*!< LCD PAL173: R04_0 Mask              */
+#define LCD_PAL173_G04_0_Pos                                  5                                                         /*!< LCD PAL173: G04_0 Position          */
+#define LCD_PAL173_G04_0_Msk                                  (0x1fUL << LCD_PAL173_G04_0_Pos)                          /*!< LCD PAL173: G04_0 Mask              */
+#define LCD_PAL173_B04_0_Pos                                  10                                                        /*!< LCD PAL173: B04_0 Position          */
+#define LCD_PAL173_B04_0_Msk                                  (0x1fUL << LCD_PAL173_B04_0_Pos)                          /*!< LCD PAL173: B04_0 Mask              */
+#define LCD_PAL173_I0_Pos                                     15                                                        /*!< LCD PAL173: I0 Position             */
+#define LCD_PAL173_I0_Msk                                     (0x01UL << LCD_PAL173_I0_Pos)                             /*!< LCD PAL173: I0 Mask                 */
+#define LCD_PAL173_R14_0_Pos                                  16                                                        /*!< LCD PAL173: R14_0 Position          */
+#define LCD_PAL173_R14_0_Msk                                  (0x1fUL << LCD_PAL173_R14_0_Pos)                          /*!< LCD PAL173: R14_0 Mask              */
+#define LCD_PAL173_G14_0_Pos                                  21                                                        /*!< LCD PAL173: G14_0 Position          */
+#define LCD_PAL173_G14_0_Msk                                  (0x1fUL << LCD_PAL173_G14_0_Pos)                          /*!< LCD PAL173: G14_0 Mask              */
+#define LCD_PAL173_B14_0_Pos                                  26                                                        /*!< LCD PAL173: B14_0 Position          */
+#define LCD_PAL173_B14_0_Msk                                  (0x1fUL << LCD_PAL173_B14_0_Pos)                          /*!< LCD PAL173: B14_0 Mask              */
+#define LCD_PAL173_I1_Pos                                     31                                                        /*!< LCD PAL173: I1 Position             */
+#define LCD_PAL173_I1_Msk                                     (0x01UL << LCD_PAL173_I1_Pos)                             /*!< LCD PAL173: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL174  -------------------------------------------
+#define LCD_PAL174_R04_0_Pos                                  0                                                         /*!< LCD PAL174: R04_0 Position          */
+#define LCD_PAL174_R04_0_Msk                                  (0x1fUL << LCD_PAL174_R04_0_Pos)                          /*!< LCD PAL174: R04_0 Mask              */
+#define LCD_PAL174_G04_0_Pos                                  5                                                         /*!< LCD PAL174: G04_0 Position          */
+#define LCD_PAL174_G04_0_Msk                                  (0x1fUL << LCD_PAL174_G04_0_Pos)                          /*!< LCD PAL174: G04_0 Mask              */
+#define LCD_PAL174_B04_0_Pos                                  10                                                        /*!< LCD PAL174: B04_0 Position          */
+#define LCD_PAL174_B04_0_Msk                                  (0x1fUL << LCD_PAL174_B04_0_Pos)                          /*!< LCD PAL174: B04_0 Mask              */
+#define LCD_PAL174_I0_Pos                                     15                                                        /*!< LCD PAL174: I0 Position             */
+#define LCD_PAL174_I0_Msk                                     (0x01UL << LCD_PAL174_I0_Pos)                             /*!< LCD PAL174: I0 Mask                 */
+#define LCD_PAL174_R14_0_Pos                                  16                                                        /*!< LCD PAL174: R14_0 Position          */
+#define LCD_PAL174_R14_0_Msk                                  (0x1fUL << LCD_PAL174_R14_0_Pos)                          /*!< LCD PAL174: R14_0 Mask              */
+#define LCD_PAL174_G14_0_Pos                                  21                                                        /*!< LCD PAL174: G14_0 Position          */
+#define LCD_PAL174_G14_0_Msk                                  (0x1fUL << LCD_PAL174_G14_0_Pos)                          /*!< LCD PAL174: G14_0 Mask              */
+#define LCD_PAL174_B14_0_Pos                                  26                                                        /*!< LCD PAL174: B14_0 Position          */
+#define LCD_PAL174_B14_0_Msk                                  (0x1fUL << LCD_PAL174_B14_0_Pos)                          /*!< LCD PAL174: B14_0 Mask              */
+#define LCD_PAL174_I1_Pos                                     31                                                        /*!< LCD PAL174: I1 Position             */
+#define LCD_PAL174_I1_Msk                                     (0x01UL << LCD_PAL174_I1_Pos)                             /*!< LCD PAL174: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL175  -------------------------------------------
+#define LCD_PAL175_R04_0_Pos                                  0                                                         /*!< LCD PAL175: R04_0 Position          */
+#define LCD_PAL175_R04_0_Msk                                  (0x1fUL << LCD_PAL175_R04_0_Pos)                          /*!< LCD PAL175: R04_0 Mask              */
+#define LCD_PAL175_G04_0_Pos                                  5                                                         /*!< LCD PAL175: G04_0 Position          */
+#define LCD_PAL175_G04_0_Msk                                  (0x1fUL << LCD_PAL175_G04_0_Pos)                          /*!< LCD PAL175: G04_0 Mask              */
+#define LCD_PAL175_B04_0_Pos                                  10                                                        /*!< LCD PAL175: B04_0 Position          */
+#define LCD_PAL175_B04_0_Msk                                  (0x1fUL << LCD_PAL175_B04_0_Pos)                          /*!< LCD PAL175: B04_0 Mask              */
+#define LCD_PAL175_I0_Pos                                     15                                                        /*!< LCD PAL175: I0 Position             */
+#define LCD_PAL175_I0_Msk                                     (0x01UL << LCD_PAL175_I0_Pos)                             /*!< LCD PAL175: I0 Mask                 */
+#define LCD_PAL175_R14_0_Pos                                  16                                                        /*!< LCD PAL175: R14_0 Position          */
+#define LCD_PAL175_R14_0_Msk                                  (0x1fUL << LCD_PAL175_R14_0_Pos)                          /*!< LCD PAL175: R14_0 Mask              */
+#define LCD_PAL175_G14_0_Pos                                  21                                                        /*!< LCD PAL175: G14_0 Position          */
+#define LCD_PAL175_G14_0_Msk                                  (0x1fUL << LCD_PAL175_G14_0_Pos)                          /*!< LCD PAL175: G14_0 Mask              */
+#define LCD_PAL175_B14_0_Pos                                  26                                                        /*!< LCD PAL175: B14_0 Position          */
+#define LCD_PAL175_B14_0_Msk                                  (0x1fUL << LCD_PAL175_B14_0_Pos)                          /*!< LCD PAL175: B14_0 Mask              */
+#define LCD_PAL175_I1_Pos                                     31                                                        /*!< LCD PAL175: I1 Position             */
+#define LCD_PAL175_I1_Msk                                     (0x01UL << LCD_PAL175_I1_Pos)                             /*!< LCD PAL175: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL176  -------------------------------------------
+#define LCD_PAL176_R04_0_Pos                                  0                                                         /*!< LCD PAL176: R04_0 Position          */
+#define LCD_PAL176_R04_0_Msk                                  (0x1fUL << LCD_PAL176_R04_0_Pos)                          /*!< LCD PAL176: R04_0 Mask              */
+#define LCD_PAL176_G04_0_Pos                                  5                                                         /*!< LCD PAL176: G04_0 Position          */
+#define LCD_PAL176_G04_0_Msk                                  (0x1fUL << LCD_PAL176_G04_0_Pos)                          /*!< LCD PAL176: G04_0 Mask              */
+#define LCD_PAL176_B04_0_Pos                                  10                                                        /*!< LCD PAL176: B04_0 Position          */
+#define LCD_PAL176_B04_0_Msk                                  (0x1fUL << LCD_PAL176_B04_0_Pos)                          /*!< LCD PAL176: B04_0 Mask              */
+#define LCD_PAL176_I0_Pos                                     15                                                        /*!< LCD PAL176: I0 Position             */
+#define LCD_PAL176_I0_Msk                                     (0x01UL << LCD_PAL176_I0_Pos)                             /*!< LCD PAL176: I0 Mask                 */
+#define LCD_PAL176_R14_0_Pos                                  16                                                        /*!< LCD PAL176: R14_0 Position          */
+#define LCD_PAL176_R14_0_Msk                                  (0x1fUL << LCD_PAL176_R14_0_Pos)                          /*!< LCD PAL176: R14_0 Mask              */
+#define LCD_PAL176_G14_0_Pos                                  21                                                        /*!< LCD PAL176: G14_0 Position          */
+#define LCD_PAL176_G14_0_Msk                                  (0x1fUL << LCD_PAL176_G14_0_Pos)                          /*!< LCD PAL176: G14_0 Mask              */
+#define LCD_PAL176_B14_0_Pos                                  26                                                        /*!< LCD PAL176: B14_0 Position          */
+#define LCD_PAL176_B14_0_Msk                                  (0x1fUL << LCD_PAL176_B14_0_Pos)                          /*!< LCD PAL176: B14_0 Mask              */
+#define LCD_PAL176_I1_Pos                                     31                                                        /*!< LCD PAL176: I1 Position             */
+#define LCD_PAL176_I1_Msk                                     (0x01UL << LCD_PAL176_I1_Pos)                             /*!< LCD PAL176: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL177  -------------------------------------------
+#define LCD_PAL177_R04_0_Pos                                  0                                                         /*!< LCD PAL177: R04_0 Position          */
+#define LCD_PAL177_R04_0_Msk                                  (0x1fUL << LCD_PAL177_R04_0_Pos)                          /*!< LCD PAL177: R04_0 Mask              */
+#define LCD_PAL177_G04_0_Pos                                  5                                                         /*!< LCD PAL177: G04_0 Position          */
+#define LCD_PAL177_G04_0_Msk                                  (0x1fUL << LCD_PAL177_G04_0_Pos)                          /*!< LCD PAL177: G04_0 Mask              */
+#define LCD_PAL177_B04_0_Pos                                  10                                                        /*!< LCD PAL177: B04_0 Position          */
+#define LCD_PAL177_B04_0_Msk                                  (0x1fUL << LCD_PAL177_B04_0_Pos)                          /*!< LCD PAL177: B04_0 Mask              */
+#define LCD_PAL177_I0_Pos                                     15                                                        /*!< LCD PAL177: I0 Position             */
+#define LCD_PAL177_I0_Msk                                     (0x01UL << LCD_PAL177_I0_Pos)                             /*!< LCD PAL177: I0 Mask                 */
+#define LCD_PAL177_R14_0_Pos                                  16                                                        /*!< LCD PAL177: R14_0 Position          */
+#define LCD_PAL177_R14_0_Msk                                  (0x1fUL << LCD_PAL177_R14_0_Pos)                          /*!< LCD PAL177: R14_0 Mask              */
+#define LCD_PAL177_G14_0_Pos                                  21                                                        /*!< LCD PAL177: G14_0 Position          */
+#define LCD_PAL177_G14_0_Msk                                  (0x1fUL << LCD_PAL177_G14_0_Pos)                          /*!< LCD PAL177: G14_0 Mask              */
+#define LCD_PAL177_B14_0_Pos                                  26                                                        /*!< LCD PAL177: B14_0 Position          */
+#define LCD_PAL177_B14_0_Msk                                  (0x1fUL << LCD_PAL177_B14_0_Pos)                          /*!< LCD PAL177: B14_0 Mask              */
+#define LCD_PAL177_I1_Pos                                     31                                                        /*!< LCD PAL177: I1 Position             */
+#define LCD_PAL177_I1_Msk                                     (0x01UL << LCD_PAL177_I1_Pos)                             /*!< LCD PAL177: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL178  -------------------------------------------
+#define LCD_PAL178_R04_0_Pos                                  0                                                         /*!< LCD PAL178: R04_0 Position          */
+#define LCD_PAL178_R04_0_Msk                                  (0x1fUL << LCD_PAL178_R04_0_Pos)                          /*!< LCD PAL178: R04_0 Mask              */
+#define LCD_PAL178_G04_0_Pos                                  5                                                         /*!< LCD PAL178: G04_0 Position          */
+#define LCD_PAL178_G04_0_Msk                                  (0x1fUL << LCD_PAL178_G04_0_Pos)                          /*!< LCD PAL178: G04_0 Mask              */
+#define LCD_PAL178_B04_0_Pos                                  10                                                        /*!< LCD PAL178: B04_0 Position          */
+#define LCD_PAL178_B04_0_Msk                                  (0x1fUL << LCD_PAL178_B04_0_Pos)                          /*!< LCD PAL178: B04_0 Mask              */
+#define LCD_PAL178_I0_Pos                                     15                                                        /*!< LCD PAL178: I0 Position             */
+#define LCD_PAL178_I0_Msk                                     (0x01UL << LCD_PAL178_I0_Pos)                             /*!< LCD PAL178: I0 Mask                 */
+#define LCD_PAL178_R14_0_Pos                                  16                                                        /*!< LCD PAL178: R14_0 Position          */
+#define LCD_PAL178_R14_0_Msk                                  (0x1fUL << LCD_PAL178_R14_0_Pos)                          /*!< LCD PAL178: R14_0 Mask              */
+#define LCD_PAL178_G14_0_Pos                                  21                                                        /*!< LCD PAL178: G14_0 Position          */
+#define LCD_PAL178_G14_0_Msk                                  (0x1fUL << LCD_PAL178_G14_0_Pos)                          /*!< LCD PAL178: G14_0 Mask              */
+#define LCD_PAL178_B14_0_Pos                                  26                                                        /*!< LCD PAL178: B14_0 Position          */
+#define LCD_PAL178_B14_0_Msk                                  (0x1fUL << LCD_PAL178_B14_0_Pos)                          /*!< LCD PAL178: B14_0 Mask              */
+#define LCD_PAL178_I1_Pos                                     31                                                        /*!< LCD PAL178: I1 Position             */
+#define LCD_PAL178_I1_Msk                                     (0x01UL << LCD_PAL178_I1_Pos)                             /*!< LCD PAL178: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL179  -------------------------------------------
+#define LCD_PAL179_R04_0_Pos                                  0                                                         /*!< LCD PAL179: R04_0 Position          */
+#define LCD_PAL179_R04_0_Msk                                  (0x1fUL << LCD_PAL179_R04_0_Pos)                          /*!< LCD PAL179: R04_0 Mask              */
+#define LCD_PAL179_G04_0_Pos                                  5                                                         /*!< LCD PAL179: G04_0 Position          */
+#define LCD_PAL179_G04_0_Msk                                  (0x1fUL << LCD_PAL179_G04_0_Pos)                          /*!< LCD PAL179: G04_0 Mask              */
+#define LCD_PAL179_B04_0_Pos                                  10                                                        /*!< LCD PAL179: B04_0 Position          */
+#define LCD_PAL179_B04_0_Msk                                  (0x1fUL << LCD_PAL179_B04_0_Pos)                          /*!< LCD PAL179: B04_0 Mask              */
+#define LCD_PAL179_I0_Pos                                     15                                                        /*!< LCD PAL179: I0 Position             */
+#define LCD_PAL179_I0_Msk                                     (0x01UL << LCD_PAL179_I0_Pos)                             /*!< LCD PAL179: I0 Mask                 */
+#define LCD_PAL179_R14_0_Pos                                  16                                                        /*!< LCD PAL179: R14_0 Position          */
+#define LCD_PAL179_R14_0_Msk                                  (0x1fUL << LCD_PAL179_R14_0_Pos)                          /*!< LCD PAL179: R14_0 Mask              */
+#define LCD_PAL179_G14_0_Pos                                  21                                                        /*!< LCD PAL179: G14_0 Position          */
+#define LCD_PAL179_G14_0_Msk                                  (0x1fUL << LCD_PAL179_G14_0_Pos)                          /*!< LCD PAL179: G14_0 Mask              */
+#define LCD_PAL179_B14_0_Pos                                  26                                                        /*!< LCD PAL179: B14_0 Position          */
+#define LCD_PAL179_B14_0_Msk                                  (0x1fUL << LCD_PAL179_B14_0_Pos)                          /*!< LCD PAL179: B14_0 Mask              */
+#define LCD_PAL179_I1_Pos                                     31                                                        /*!< LCD PAL179: I1 Position             */
+#define LCD_PAL179_I1_Msk                                     (0x01UL << LCD_PAL179_I1_Pos)                             /*!< LCD PAL179: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL180  -------------------------------------------
+#define LCD_PAL180_R04_0_Pos                                  0                                                         /*!< LCD PAL180: R04_0 Position          */
+#define LCD_PAL180_R04_0_Msk                                  (0x1fUL << LCD_PAL180_R04_0_Pos)                          /*!< LCD PAL180: R04_0 Mask              */
+#define LCD_PAL180_G04_0_Pos                                  5                                                         /*!< LCD PAL180: G04_0 Position          */
+#define LCD_PAL180_G04_0_Msk                                  (0x1fUL << LCD_PAL180_G04_0_Pos)                          /*!< LCD PAL180: G04_0 Mask              */
+#define LCD_PAL180_B04_0_Pos                                  10                                                        /*!< LCD PAL180: B04_0 Position          */
+#define LCD_PAL180_B04_0_Msk                                  (0x1fUL << LCD_PAL180_B04_0_Pos)                          /*!< LCD PAL180: B04_0 Mask              */
+#define LCD_PAL180_I0_Pos                                     15                                                        /*!< LCD PAL180: I0 Position             */
+#define LCD_PAL180_I0_Msk                                     (0x01UL << LCD_PAL180_I0_Pos)                             /*!< LCD PAL180: I0 Mask                 */
+#define LCD_PAL180_R14_0_Pos                                  16                                                        /*!< LCD PAL180: R14_0 Position          */
+#define LCD_PAL180_R14_0_Msk                                  (0x1fUL << LCD_PAL180_R14_0_Pos)                          /*!< LCD PAL180: R14_0 Mask              */
+#define LCD_PAL180_G14_0_Pos                                  21                                                        /*!< LCD PAL180: G14_0 Position          */
+#define LCD_PAL180_G14_0_Msk                                  (0x1fUL << LCD_PAL180_G14_0_Pos)                          /*!< LCD PAL180: G14_0 Mask              */
+#define LCD_PAL180_B14_0_Pos                                  26                                                        /*!< LCD PAL180: B14_0 Position          */
+#define LCD_PAL180_B14_0_Msk                                  (0x1fUL << LCD_PAL180_B14_0_Pos)                          /*!< LCD PAL180: B14_0 Mask              */
+#define LCD_PAL180_I1_Pos                                     31                                                        /*!< LCD PAL180: I1 Position             */
+#define LCD_PAL180_I1_Msk                                     (0x01UL << LCD_PAL180_I1_Pos)                             /*!< LCD PAL180: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL181  -------------------------------------------
+#define LCD_PAL181_R04_0_Pos                                  0                                                         /*!< LCD PAL181: R04_0 Position          */
+#define LCD_PAL181_R04_0_Msk                                  (0x1fUL << LCD_PAL181_R04_0_Pos)                          /*!< LCD PAL181: R04_0 Mask              */
+#define LCD_PAL181_G04_0_Pos                                  5                                                         /*!< LCD PAL181: G04_0 Position          */
+#define LCD_PAL181_G04_0_Msk                                  (0x1fUL << LCD_PAL181_G04_0_Pos)                          /*!< LCD PAL181: G04_0 Mask              */
+#define LCD_PAL181_B04_0_Pos                                  10                                                        /*!< LCD PAL181: B04_0 Position          */
+#define LCD_PAL181_B04_0_Msk                                  (0x1fUL << LCD_PAL181_B04_0_Pos)                          /*!< LCD PAL181: B04_0 Mask              */
+#define LCD_PAL181_I0_Pos                                     15                                                        /*!< LCD PAL181: I0 Position             */
+#define LCD_PAL181_I0_Msk                                     (0x01UL << LCD_PAL181_I0_Pos)                             /*!< LCD PAL181: I0 Mask                 */
+#define LCD_PAL181_R14_0_Pos                                  16                                                        /*!< LCD PAL181: R14_0 Position          */
+#define LCD_PAL181_R14_0_Msk                                  (0x1fUL << LCD_PAL181_R14_0_Pos)                          /*!< LCD PAL181: R14_0 Mask              */
+#define LCD_PAL181_G14_0_Pos                                  21                                                        /*!< LCD PAL181: G14_0 Position          */
+#define LCD_PAL181_G14_0_Msk                                  (0x1fUL << LCD_PAL181_G14_0_Pos)                          /*!< LCD PAL181: G14_0 Mask              */
+#define LCD_PAL181_B14_0_Pos                                  26                                                        /*!< LCD PAL181: B14_0 Position          */
+#define LCD_PAL181_B14_0_Msk                                  (0x1fUL << LCD_PAL181_B14_0_Pos)                          /*!< LCD PAL181: B14_0 Mask              */
+#define LCD_PAL181_I1_Pos                                     31                                                        /*!< LCD PAL181: I1 Position             */
+#define LCD_PAL181_I1_Msk                                     (0x01UL << LCD_PAL181_I1_Pos)                             /*!< LCD PAL181: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL182  -------------------------------------------
+#define LCD_PAL182_R04_0_Pos                                  0                                                         /*!< LCD PAL182: R04_0 Position          */
+#define LCD_PAL182_R04_0_Msk                                  (0x1fUL << LCD_PAL182_R04_0_Pos)                          /*!< LCD PAL182: R04_0 Mask              */
+#define LCD_PAL182_G04_0_Pos                                  5                                                         /*!< LCD PAL182: G04_0 Position          */
+#define LCD_PAL182_G04_0_Msk                                  (0x1fUL << LCD_PAL182_G04_0_Pos)                          /*!< LCD PAL182: G04_0 Mask              */
+#define LCD_PAL182_B04_0_Pos                                  10                                                        /*!< LCD PAL182: B04_0 Position          */
+#define LCD_PAL182_B04_0_Msk                                  (0x1fUL << LCD_PAL182_B04_0_Pos)                          /*!< LCD PAL182: B04_0 Mask              */
+#define LCD_PAL182_I0_Pos                                     15                                                        /*!< LCD PAL182: I0 Position             */
+#define LCD_PAL182_I0_Msk                                     (0x01UL << LCD_PAL182_I0_Pos)                             /*!< LCD PAL182: I0 Mask                 */
+#define LCD_PAL182_R14_0_Pos                                  16                                                        /*!< LCD PAL182: R14_0 Position          */
+#define LCD_PAL182_R14_0_Msk                                  (0x1fUL << LCD_PAL182_R14_0_Pos)                          /*!< LCD PAL182: R14_0 Mask              */
+#define LCD_PAL182_G14_0_Pos                                  21                                                        /*!< LCD PAL182: G14_0 Position          */
+#define LCD_PAL182_G14_0_Msk                                  (0x1fUL << LCD_PAL182_G14_0_Pos)                          /*!< LCD PAL182: G14_0 Mask              */
+#define LCD_PAL182_B14_0_Pos                                  26                                                        /*!< LCD PAL182: B14_0 Position          */
+#define LCD_PAL182_B14_0_Msk                                  (0x1fUL << LCD_PAL182_B14_0_Pos)                          /*!< LCD PAL182: B14_0 Mask              */
+#define LCD_PAL182_I1_Pos                                     31                                                        /*!< LCD PAL182: I1 Position             */
+#define LCD_PAL182_I1_Msk                                     (0x01UL << LCD_PAL182_I1_Pos)                             /*!< LCD PAL182: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL183  -------------------------------------------
+#define LCD_PAL183_R04_0_Pos                                  0                                                         /*!< LCD PAL183: R04_0 Position          */
+#define LCD_PAL183_R04_0_Msk                                  (0x1fUL << LCD_PAL183_R04_0_Pos)                          /*!< LCD PAL183: R04_0 Mask              */
+#define LCD_PAL183_G04_0_Pos                                  5                                                         /*!< LCD PAL183: G04_0 Position          */
+#define LCD_PAL183_G04_0_Msk                                  (0x1fUL << LCD_PAL183_G04_0_Pos)                          /*!< LCD PAL183: G04_0 Mask              */
+#define LCD_PAL183_B04_0_Pos                                  10                                                        /*!< LCD PAL183: B04_0 Position          */
+#define LCD_PAL183_B04_0_Msk                                  (0x1fUL << LCD_PAL183_B04_0_Pos)                          /*!< LCD PAL183: B04_0 Mask              */
+#define LCD_PAL183_I0_Pos                                     15                                                        /*!< LCD PAL183: I0 Position             */
+#define LCD_PAL183_I0_Msk                                     (0x01UL << LCD_PAL183_I0_Pos)                             /*!< LCD PAL183: I0 Mask                 */
+#define LCD_PAL183_R14_0_Pos                                  16                                                        /*!< LCD PAL183: R14_0 Position          */
+#define LCD_PAL183_R14_0_Msk                                  (0x1fUL << LCD_PAL183_R14_0_Pos)                          /*!< LCD PAL183: R14_0 Mask              */
+#define LCD_PAL183_G14_0_Pos                                  21                                                        /*!< LCD PAL183: G14_0 Position          */
+#define LCD_PAL183_G14_0_Msk                                  (0x1fUL << LCD_PAL183_G14_0_Pos)                          /*!< LCD PAL183: G14_0 Mask              */
+#define LCD_PAL183_B14_0_Pos                                  26                                                        /*!< LCD PAL183: B14_0 Position          */
+#define LCD_PAL183_B14_0_Msk                                  (0x1fUL << LCD_PAL183_B14_0_Pos)                          /*!< LCD PAL183: B14_0 Mask              */
+#define LCD_PAL183_I1_Pos                                     31                                                        /*!< LCD PAL183: I1 Position             */
+#define LCD_PAL183_I1_Msk                                     (0x01UL << LCD_PAL183_I1_Pos)                             /*!< LCD PAL183: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL184  -------------------------------------------
+#define LCD_PAL184_R04_0_Pos                                  0                                                         /*!< LCD PAL184: R04_0 Position          */
+#define LCD_PAL184_R04_0_Msk                                  (0x1fUL << LCD_PAL184_R04_0_Pos)                          /*!< LCD PAL184: R04_0 Mask              */
+#define LCD_PAL184_G04_0_Pos                                  5                                                         /*!< LCD PAL184: G04_0 Position          */
+#define LCD_PAL184_G04_0_Msk                                  (0x1fUL << LCD_PAL184_G04_0_Pos)                          /*!< LCD PAL184: G04_0 Mask              */
+#define LCD_PAL184_B04_0_Pos                                  10                                                        /*!< LCD PAL184: B04_0 Position          */
+#define LCD_PAL184_B04_0_Msk                                  (0x1fUL << LCD_PAL184_B04_0_Pos)                          /*!< LCD PAL184: B04_0 Mask              */
+#define LCD_PAL184_I0_Pos                                     15                                                        /*!< LCD PAL184: I0 Position             */
+#define LCD_PAL184_I0_Msk                                     (0x01UL << LCD_PAL184_I0_Pos)                             /*!< LCD PAL184: I0 Mask                 */
+#define LCD_PAL184_R14_0_Pos                                  16                                                        /*!< LCD PAL184: R14_0 Position          */
+#define LCD_PAL184_R14_0_Msk                                  (0x1fUL << LCD_PAL184_R14_0_Pos)                          /*!< LCD PAL184: R14_0 Mask              */
+#define LCD_PAL184_G14_0_Pos                                  21                                                        /*!< LCD PAL184: G14_0 Position          */
+#define LCD_PAL184_G14_0_Msk                                  (0x1fUL << LCD_PAL184_G14_0_Pos)                          /*!< LCD PAL184: G14_0 Mask              */
+#define LCD_PAL184_B14_0_Pos                                  26                                                        /*!< LCD PAL184: B14_0 Position          */
+#define LCD_PAL184_B14_0_Msk                                  (0x1fUL << LCD_PAL184_B14_0_Pos)                          /*!< LCD PAL184: B14_0 Mask              */
+#define LCD_PAL184_I1_Pos                                     31                                                        /*!< LCD PAL184: I1 Position             */
+#define LCD_PAL184_I1_Msk                                     (0x01UL << LCD_PAL184_I1_Pos)                             /*!< LCD PAL184: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL185  -------------------------------------------
+#define LCD_PAL185_R04_0_Pos                                  0                                                         /*!< LCD PAL185: R04_0 Position          */
+#define LCD_PAL185_R04_0_Msk                                  (0x1fUL << LCD_PAL185_R04_0_Pos)                          /*!< LCD PAL185: R04_0 Mask              */
+#define LCD_PAL185_G04_0_Pos                                  5                                                         /*!< LCD PAL185: G04_0 Position          */
+#define LCD_PAL185_G04_0_Msk                                  (0x1fUL << LCD_PAL185_G04_0_Pos)                          /*!< LCD PAL185: G04_0 Mask              */
+#define LCD_PAL185_B04_0_Pos                                  10                                                        /*!< LCD PAL185: B04_0 Position          */
+#define LCD_PAL185_B04_0_Msk                                  (0x1fUL << LCD_PAL185_B04_0_Pos)                          /*!< LCD PAL185: B04_0 Mask              */
+#define LCD_PAL185_I0_Pos                                     15                                                        /*!< LCD PAL185: I0 Position             */
+#define LCD_PAL185_I0_Msk                                     (0x01UL << LCD_PAL185_I0_Pos)                             /*!< LCD PAL185: I0 Mask                 */
+#define LCD_PAL185_R14_0_Pos                                  16                                                        /*!< LCD PAL185: R14_0 Position          */
+#define LCD_PAL185_R14_0_Msk                                  (0x1fUL << LCD_PAL185_R14_0_Pos)                          /*!< LCD PAL185: R14_0 Mask              */
+#define LCD_PAL185_G14_0_Pos                                  21                                                        /*!< LCD PAL185: G14_0 Position          */
+#define LCD_PAL185_G14_0_Msk                                  (0x1fUL << LCD_PAL185_G14_0_Pos)                          /*!< LCD PAL185: G14_0 Mask              */
+#define LCD_PAL185_B14_0_Pos                                  26                                                        /*!< LCD PAL185: B14_0 Position          */
+#define LCD_PAL185_B14_0_Msk                                  (0x1fUL << LCD_PAL185_B14_0_Pos)                          /*!< LCD PAL185: B14_0 Mask              */
+#define LCD_PAL185_I1_Pos                                     31                                                        /*!< LCD PAL185: I1 Position             */
+#define LCD_PAL185_I1_Msk                                     (0x01UL << LCD_PAL185_I1_Pos)                             /*!< LCD PAL185: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL186  -------------------------------------------
+#define LCD_PAL186_R04_0_Pos                                  0                                                         /*!< LCD PAL186: R04_0 Position          */
+#define LCD_PAL186_R04_0_Msk                                  (0x1fUL << LCD_PAL186_R04_0_Pos)                          /*!< LCD PAL186: R04_0 Mask              */
+#define LCD_PAL186_G04_0_Pos                                  5                                                         /*!< LCD PAL186: G04_0 Position          */
+#define LCD_PAL186_G04_0_Msk                                  (0x1fUL << LCD_PAL186_G04_0_Pos)                          /*!< LCD PAL186: G04_0 Mask              */
+#define LCD_PAL186_B04_0_Pos                                  10                                                        /*!< LCD PAL186: B04_0 Position          */
+#define LCD_PAL186_B04_0_Msk                                  (0x1fUL << LCD_PAL186_B04_0_Pos)                          /*!< LCD PAL186: B04_0 Mask              */
+#define LCD_PAL186_I0_Pos                                     15                                                        /*!< LCD PAL186: I0 Position             */
+#define LCD_PAL186_I0_Msk                                     (0x01UL << LCD_PAL186_I0_Pos)                             /*!< LCD PAL186: I0 Mask                 */
+#define LCD_PAL186_R14_0_Pos                                  16                                                        /*!< LCD PAL186: R14_0 Position          */
+#define LCD_PAL186_R14_0_Msk                                  (0x1fUL << LCD_PAL186_R14_0_Pos)                          /*!< LCD PAL186: R14_0 Mask              */
+#define LCD_PAL186_G14_0_Pos                                  21                                                        /*!< LCD PAL186: G14_0 Position          */
+#define LCD_PAL186_G14_0_Msk                                  (0x1fUL << LCD_PAL186_G14_0_Pos)                          /*!< LCD PAL186: G14_0 Mask              */
+#define LCD_PAL186_B14_0_Pos                                  26                                                        /*!< LCD PAL186: B14_0 Position          */
+#define LCD_PAL186_B14_0_Msk                                  (0x1fUL << LCD_PAL186_B14_0_Pos)                          /*!< LCD PAL186: B14_0 Mask              */
+#define LCD_PAL186_I1_Pos                                     31                                                        /*!< LCD PAL186: I1 Position             */
+#define LCD_PAL186_I1_Msk                                     (0x01UL << LCD_PAL186_I1_Pos)                             /*!< LCD PAL186: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL187  -------------------------------------------
+#define LCD_PAL187_R04_0_Pos                                  0                                                         /*!< LCD PAL187: R04_0 Position          */
+#define LCD_PAL187_R04_0_Msk                                  (0x1fUL << LCD_PAL187_R04_0_Pos)                          /*!< LCD PAL187: R04_0 Mask              */
+#define LCD_PAL187_G04_0_Pos                                  5                                                         /*!< LCD PAL187: G04_0 Position          */
+#define LCD_PAL187_G04_0_Msk                                  (0x1fUL << LCD_PAL187_G04_0_Pos)                          /*!< LCD PAL187: G04_0 Mask              */
+#define LCD_PAL187_B04_0_Pos                                  10                                                        /*!< LCD PAL187: B04_0 Position          */
+#define LCD_PAL187_B04_0_Msk                                  (0x1fUL << LCD_PAL187_B04_0_Pos)                          /*!< LCD PAL187: B04_0 Mask              */
+#define LCD_PAL187_I0_Pos                                     15                                                        /*!< LCD PAL187: I0 Position             */
+#define LCD_PAL187_I0_Msk                                     (0x01UL << LCD_PAL187_I0_Pos)                             /*!< LCD PAL187: I0 Mask                 */
+#define LCD_PAL187_R14_0_Pos                                  16                                                        /*!< LCD PAL187: R14_0 Position          */
+#define LCD_PAL187_R14_0_Msk                                  (0x1fUL << LCD_PAL187_R14_0_Pos)                          /*!< LCD PAL187: R14_0 Mask              */
+#define LCD_PAL187_G14_0_Pos                                  21                                                        /*!< LCD PAL187: G14_0 Position          */
+#define LCD_PAL187_G14_0_Msk                                  (0x1fUL << LCD_PAL187_G14_0_Pos)                          /*!< LCD PAL187: G14_0 Mask              */
+#define LCD_PAL187_B14_0_Pos                                  26                                                        /*!< LCD PAL187: B14_0 Position          */
+#define LCD_PAL187_B14_0_Msk                                  (0x1fUL << LCD_PAL187_B14_0_Pos)                          /*!< LCD PAL187: B14_0 Mask              */
+#define LCD_PAL187_I1_Pos                                     31                                                        /*!< LCD PAL187: I1 Position             */
+#define LCD_PAL187_I1_Msk                                     (0x01UL << LCD_PAL187_I1_Pos)                             /*!< LCD PAL187: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL188  -------------------------------------------
+#define LCD_PAL188_R04_0_Pos                                  0                                                         /*!< LCD PAL188: R04_0 Position          */
+#define LCD_PAL188_R04_0_Msk                                  (0x1fUL << LCD_PAL188_R04_0_Pos)                          /*!< LCD PAL188: R04_0 Mask              */
+#define LCD_PAL188_G04_0_Pos                                  5                                                         /*!< LCD PAL188: G04_0 Position          */
+#define LCD_PAL188_G04_0_Msk                                  (0x1fUL << LCD_PAL188_G04_0_Pos)                          /*!< LCD PAL188: G04_0 Mask              */
+#define LCD_PAL188_B04_0_Pos                                  10                                                        /*!< LCD PAL188: B04_0 Position          */
+#define LCD_PAL188_B04_0_Msk                                  (0x1fUL << LCD_PAL188_B04_0_Pos)                          /*!< LCD PAL188: B04_0 Mask              */
+#define LCD_PAL188_I0_Pos                                     15                                                        /*!< LCD PAL188: I0 Position             */
+#define LCD_PAL188_I0_Msk                                     (0x01UL << LCD_PAL188_I0_Pos)                             /*!< LCD PAL188: I0 Mask                 */
+#define LCD_PAL188_R14_0_Pos                                  16                                                        /*!< LCD PAL188: R14_0 Position          */
+#define LCD_PAL188_R14_0_Msk                                  (0x1fUL << LCD_PAL188_R14_0_Pos)                          /*!< LCD PAL188: R14_0 Mask              */
+#define LCD_PAL188_G14_0_Pos                                  21                                                        /*!< LCD PAL188: G14_0 Position          */
+#define LCD_PAL188_G14_0_Msk                                  (0x1fUL << LCD_PAL188_G14_0_Pos)                          /*!< LCD PAL188: G14_0 Mask              */
+#define LCD_PAL188_B14_0_Pos                                  26                                                        /*!< LCD PAL188: B14_0 Position          */
+#define LCD_PAL188_B14_0_Msk                                  (0x1fUL << LCD_PAL188_B14_0_Pos)                          /*!< LCD PAL188: B14_0 Mask              */
+#define LCD_PAL188_I1_Pos                                     31                                                        /*!< LCD PAL188: I1 Position             */
+#define LCD_PAL188_I1_Msk                                     (0x01UL << LCD_PAL188_I1_Pos)                             /*!< LCD PAL188: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL189  -------------------------------------------
+#define LCD_PAL189_R04_0_Pos                                  0                                                         /*!< LCD PAL189: R04_0 Position          */
+#define LCD_PAL189_R04_0_Msk                                  (0x1fUL << LCD_PAL189_R04_0_Pos)                          /*!< LCD PAL189: R04_0 Mask              */
+#define LCD_PAL189_G04_0_Pos                                  5                                                         /*!< LCD PAL189: G04_0 Position          */
+#define LCD_PAL189_G04_0_Msk                                  (0x1fUL << LCD_PAL189_G04_0_Pos)                          /*!< LCD PAL189: G04_0 Mask              */
+#define LCD_PAL189_B04_0_Pos                                  10                                                        /*!< LCD PAL189: B04_0 Position          */
+#define LCD_PAL189_B04_0_Msk                                  (0x1fUL << LCD_PAL189_B04_0_Pos)                          /*!< LCD PAL189: B04_0 Mask              */
+#define LCD_PAL189_I0_Pos                                     15                                                        /*!< LCD PAL189: I0 Position             */
+#define LCD_PAL189_I0_Msk                                     (0x01UL << LCD_PAL189_I0_Pos)                             /*!< LCD PAL189: I0 Mask                 */
+#define LCD_PAL189_R14_0_Pos                                  16                                                        /*!< LCD PAL189: R14_0 Position          */
+#define LCD_PAL189_R14_0_Msk                                  (0x1fUL << LCD_PAL189_R14_0_Pos)                          /*!< LCD PAL189: R14_0 Mask              */
+#define LCD_PAL189_G14_0_Pos                                  21                                                        /*!< LCD PAL189: G14_0 Position          */
+#define LCD_PAL189_G14_0_Msk                                  (0x1fUL << LCD_PAL189_G14_0_Pos)                          /*!< LCD PAL189: G14_0 Mask              */
+#define LCD_PAL189_B14_0_Pos                                  26                                                        /*!< LCD PAL189: B14_0 Position          */
+#define LCD_PAL189_B14_0_Msk                                  (0x1fUL << LCD_PAL189_B14_0_Pos)                          /*!< LCD PAL189: B14_0 Mask              */
+#define LCD_PAL189_I1_Pos                                     31                                                        /*!< LCD PAL189: I1 Position             */
+#define LCD_PAL189_I1_Msk                                     (0x01UL << LCD_PAL189_I1_Pos)                             /*!< LCD PAL189: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL190  -------------------------------------------
+#define LCD_PAL190_R04_0_Pos                                  0                                                         /*!< LCD PAL190: R04_0 Position          */
+#define LCD_PAL190_R04_0_Msk                                  (0x1fUL << LCD_PAL190_R04_0_Pos)                          /*!< LCD PAL190: R04_0 Mask              */
+#define LCD_PAL190_G04_0_Pos                                  5                                                         /*!< LCD PAL190: G04_0 Position          */
+#define LCD_PAL190_G04_0_Msk                                  (0x1fUL << LCD_PAL190_G04_0_Pos)                          /*!< LCD PAL190: G04_0 Mask              */
+#define LCD_PAL190_B04_0_Pos                                  10                                                        /*!< LCD PAL190: B04_0 Position          */
+#define LCD_PAL190_B04_0_Msk                                  (0x1fUL << LCD_PAL190_B04_0_Pos)                          /*!< LCD PAL190: B04_0 Mask              */
+#define LCD_PAL190_I0_Pos                                     15                                                        /*!< LCD PAL190: I0 Position             */
+#define LCD_PAL190_I0_Msk                                     (0x01UL << LCD_PAL190_I0_Pos)                             /*!< LCD PAL190: I0 Mask                 */
+#define LCD_PAL190_R14_0_Pos                                  16                                                        /*!< LCD PAL190: R14_0 Position          */
+#define LCD_PAL190_R14_0_Msk                                  (0x1fUL << LCD_PAL190_R14_0_Pos)                          /*!< LCD PAL190: R14_0 Mask              */
+#define LCD_PAL190_G14_0_Pos                                  21                                                        /*!< LCD PAL190: G14_0 Position          */
+#define LCD_PAL190_G14_0_Msk                                  (0x1fUL << LCD_PAL190_G14_0_Pos)                          /*!< LCD PAL190: G14_0 Mask              */
+#define LCD_PAL190_B14_0_Pos                                  26                                                        /*!< LCD PAL190: B14_0 Position          */
+#define LCD_PAL190_B14_0_Msk                                  (0x1fUL << LCD_PAL190_B14_0_Pos)                          /*!< LCD PAL190: B14_0 Mask              */
+#define LCD_PAL190_I1_Pos                                     31                                                        /*!< LCD PAL190: I1 Position             */
+#define LCD_PAL190_I1_Msk                                     (0x01UL << LCD_PAL190_I1_Pos)                             /*!< LCD PAL190: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL191  -------------------------------------------
+#define LCD_PAL191_R04_0_Pos                                  0                                                         /*!< LCD PAL191: R04_0 Position          */
+#define LCD_PAL191_R04_0_Msk                                  (0x1fUL << LCD_PAL191_R04_0_Pos)                          /*!< LCD PAL191: R04_0 Mask              */
+#define LCD_PAL191_G04_0_Pos                                  5                                                         /*!< LCD PAL191: G04_0 Position          */
+#define LCD_PAL191_G04_0_Msk                                  (0x1fUL << LCD_PAL191_G04_0_Pos)                          /*!< LCD PAL191: G04_0 Mask              */
+#define LCD_PAL191_B04_0_Pos                                  10                                                        /*!< LCD PAL191: B04_0 Position          */
+#define LCD_PAL191_B04_0_Msk                                  (0x1fUL << LCD_PAL191_B04_0_Pos)                          /*!< LCD PAL191: B04_0 Mask              */
+#define LCD_PAL191_I0_Pos                                     15                                                        /*!< LCD PAL191: I0 Position             */
+#define LCD_PAL191_I0_Msk                                     (0x01UL << LCD_PAL191_I0_Pos)                             /*!< LCD PAL191: I0 Mask                 */
+#define LCD_PAL191_R14_0_Pos                                  16                                                        /*!< LCD PAL191: R14_0 Position          */
+#define LCD_PAL191_R14_0_Msk                                  (0x1fUL << LCD_PAL191_R14_0_Pos)                          /*!< LCD PAL191: R14_0 Mask              */
+#define LCD_PAL191_G14_0_Pos                                  21                                                        /*!< LCD PAL191: G14_0 Position          */
+#define LCD_PAL191_G14_0_Msk                                  (0x1fUL << LCD_PAL191_G14_0_Pos)                          /*!< LCD PAL191: G14_0 Mask              */
+#define LCD_PAL191_B14_0_Pos                                  26                                                        /*!< LCD PAL191: B14_0 Position          */
+#define LCD_PAL191_B14_0_Msk                                  (0x1fUL << LCD_PAL191_B14_0_Pos)                          /*!< LCD PAL191: B14_0 Mask              */
+#define LCD_PAL191_I1_Pos                                     31                                                        /*!< LCD PAL191: I1 Position             */
+#define LCD_PAL191_I1_Msk                                     (0x01UL << LCD_PAL191_I1_Pos)                             /*!< LCD PAL191: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL192  -------------------------------------------
+#define LCD_PAL192_R04_0_Pos                                  0                                                         /*!< LCD PAL192: R04_0 Position          */
+#define LCD_PAL192_R04_0_Msk                                  (0x1fUL << LCD_PAL192_R04_0_Pos)                          /*!< LCD PAL192: R04_0 Mask              */
+#define LCD_PAL192_G04_0_Pos                                  5                                                         /*!< LCD PAL192: G04_0 Position          */
+#define LCD_PAL192_G04_0_Msk                                  (0x1fUL << LCD_PAL192_G04_0_Pos)                          /*!< LCD PAL192: G04_0 Mask              */
+#define LCD_PAL192_B04_0_Pos                                  10                                                        /*!< LCD PAL192: B04_0 Position          */
+#define LCD_PAL192_B04_0_Msk                                  (0x1fUL << LCD_PAL192_B04_0_Pos)                          /*!< LCD PAL192: B04_0 Mask              */
+#define LCD_PAL192_I0_Pos                                     15                                                        /*!< LCD PAL192: I0 Position             */
+#define LCD_PAL192_I0_Msk                                     (0x01UL << LCD_PAL192_I0_Pos)                             /*!< LCD PAL192: I0 Mask                 */
+#define LCD_PAL192_R14_0_Pos                                  16                                                        /*!< LCD PAL192: R14_0 Position          */
+#define LCD_PAL192_R14_0_Msk                                  (0x1fUL << LCD_PAL192_R14_0_Pos)                          /*!< LCD PAL192: R14_0 Mask              */
+#define LCD_PAL192_G14_0_Pos                                  21                                                        /*!< LCD PAL192: G14_0 Position          */
+#define LCD_PAL192_G14_0_Msk                                  (0x1fUL << LCD_PAL192_G14_0_Pos)                          /*!< LCD PAL192: G14_0 Mask              */
+#define LCD_PAL192_B14_0_Pos                                  26                                                        /*!< LCD PAL192: B14_0 Position          */
+#define LCD_PAL192_B14_0_Msk                                  (0x1fUL << LCD_PAL192_B14_0_Pos)                          /*!< LCD PAL192: B14_0 Mask              */
+#define LCD_PAL192_I1_Pos                                     31                                                        /*!< LCD PAL192: I1 Position             */
+#define LCD_PAL192_I1_Msk                                     (0x01UL << LCD_PAL192_I1_Pos)                             /*!< LCD PAL192: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL193  -------------------------------------------
+#define LCD_PAL193_R04_0_Pos                                  0                                                         /*!< LCD PAL193: R04_0 Position          */
+#define LCD_PAL193_R04_0_Msk                                  (0x1fUL << LCD_PAL193_R04_0_Pos)                          /*!< LCD PAL193: R04_0 Mask              */
+#define LCD_PAL193_G04_0_Pos                                  5                                                         /*!< LCD PAL193: G04_0 Position          */
+#define LCD_PAL193_G04_0_Msk                                  (0x1fUL << LCD_PAL193_G04_0_Pos)                          /*!< LCD PAL193: G04_0 Mask              */
+#define LCD_PAL193_B04_0_Pos                                  10                                                        /*!< LCD PAL193: B04_0 Position          */
+#define LCD_PAL193_B04_0_Msk                                  (0x1fUL << LCD_PAL193_B04_0_Pos)                          /*!< LCD PAL193: B04_0 Mask              */
+#define LCD_PAL193_I0_Pos                                     15                                                        /*!< LCD PAL193: I0 Position             */
+#define LCD_PAL193_I0_Msk                                     (0x01UL << LCD_PAL193_I0_Pos)                             /*!< LCD PAL193: I0 Mask                 */
+#define LCD_PAL193_R14_0_Pos                                  16                                                        /*!< LCD PAL193: R14_0 Position          */
+#define LCD_PAL193_R14_0_Msk                                  (0x1fUL << LCD_PAL193_R14_0_Pos)                          /*!< LCD PAL193: R14_0 Mask              */
+#define LCD_PAL193_G14_0_Pos                                  21                                                        /*!< LCD PAL193: G14_0 Position          */
+#define LCD_PAL193_G14_0_Msk                                  (0x1fUL << LCD_PAL193_G14_0_Pos)                          /*!< LCD PAL193: G14_0 Mask              */
+#define LCD_PAL193_B14_0_Pos                                  26                                                        /*!< LCD PAL193: B14_0 Position          */
+#define LCD_PAL193_B14_0_Msk                                  (0x1fUL << LCD_PAL193_B14_0_Pos)                          /*!< LCD PAL193: B14_0 Mask              */
+#define LCD_PAL193_I1_Pos                                     31                                                        /*!< LCD PAL193: I1 Position             */
+#define LCD_PAL193_I1_Msk                                     (0x01UL << LCD_PAL193_I1_Pos)                             /*!< LCD PAL193: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL194  -------------------------------------------
+#define LCD_PAL194_R04_0_Pos                                  0                                                         /*!< LCD PAL194: R04_0 Position          */
+#define LCD_PAL194_R04_0_Msk                                  (0x1fUL << LCD_PAL194_R04_0_Pos)                          /*!< LCD PAL194: R04_0 Mask              */
+#define LCD_PAL194_G04_0_Pos                                  5                                                         /*!< LCD PAL194: G04_0 Position          */
+#define LCD_PAL194_G04_0_Msk                                  (0x1fUL << LCD_PAL194_G04_0_Pos)                          /*!< LCD PAL194: G04_0 Mask              */
+#define LCD_PAL194_B04_0_Pos                                  10                                                        /*!< LCD PAL194: B04_0 Position          */
+#define LCD_PAL194_B04_0_Msk                                  (0x1fUL << LCD_PAL194_B04_0_Pos)                          /*!< LCD PAL194: B04_0 Mask              */
+#define LCD_PAL194_I0_Pos                                     15                                                        /*!< LCD PAL194: I0 Position             */
+#define LCD_PAL194_I0_Msk                                     (0x01UL << LCD_PAL194_I0_Pos)                             /*!< LCD PAL194: I0 Mask                 */
+#define LCD_PAL194_R14_0_Pos                                  16                                                        /*!< LCD PAL194: R14_0 Position          */
+#define LCD_PAL194_R14_0_Msk                                  (0x1fUL << LCD_PAL194_R14_0_Pos)                          /*!< LCD PAL194: R14_0 Mask              */
+#define LCD_PAL194_G14_0_Pos                                  21                                                        /*!< LCD PAL194: G14_0 Position          */
+#define LCD_PAL194_G14_0_Msk                                  (0x1fUL << LCD_PAL194_G14_0_Pos)                          /*!< LCD PAL194: G14_0 Mask              */
+#define LCD_PAL194_B14_0_Pos                                  26                                                        /*!< LCD PAL194: B14_0 Position          */
+#define LCD_PAL194_B14_0_Msk                                  (0x1fUL << LCD_PAL194_B14_0_Pos)                          /*!< LCD PAL194: B14_0 Mask              */
+#define LCD_PAL194_I1_Pos                                     31                                                        /*!< LCD PAL194: I1 Position             */
+#define LCD_PAL194_I1_Msk                                     (0x01UL << LCD_PAL194_I1_Pos)                             /*!< LCD PAL194: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL195  -------------------------------------------
+#define LCD_PAL195_R04_0_Pos                                  0                                                         /*!< LCD PAL195: R04_0 Position          */
+#define LCD_PAL195_R04_0_Msk                                  (0x1fUL << LCD_PAL195_R04_0_Pos)                          /*!< LCD PAL195: R04_0 Mask              */
+#define LCD_PAL195_G04_0_Pos                                  5                                                         /*!< LCD PAL195: G04_0 Position          */
+#define LCD_PAL195_G04_0_Msk                                  (0x1fUL << LCD_PAL195_G04_0_Pos)                          /*!< LCD PAL195: G04_0 Mask              */
+#define LCD_PAL195_B04_0_Pos                                  10                                                        /*!< LCD PAL195: B04_0 Position          */
+#define LCD_PAL195_B04_0_Msk                                  (0x1fUL << LCD_PAL195_B04_0_Pos)                          /*!< LCD PAL195: B04_0 Mask              */
+#define LCD_PAL195_I0_Pos                                     15                                                        /*!< LCD PAL195: I0 Position             */
+#define LCD_PAL195_I0_Msk                                     (0x01UL << LCD_PAL195_I0_Pos)                             /*!< LCD PAL195: I0 Mask                 */
+#define LCD_PAL195_R14_0_Pos                                  16                                                        /*!< LCD PAL195: R14_0 Position          */
+#define LCD_PAL195_R14_0_Msk                                  (0x1fUL << LCD_PAL195_R14_0_Pos)                          /*!< LCD PAL195: R14_0 Mask              */
+#define LCD_PAL195_G14_0_Pos                                  21                                                        /*!< LCD PAL195: G14_0 Position          */
+#define LCD_PAL195_G14_0_Msk                                  (0x1fUL << LCD_PAL195_G14_0_Pos)                          /*!< LCD PAL195: G14_0 Mask              */
+#define LCD_PAL195_B14_0_Pos                                  26                                                        /*!< LCD PAL195: B14_0 Position          */
+#define LCD_PAL195_B14_0_Msk                                  (0x1fUL << LCD_PAL195_B14_0_Pos)                          /*!< LCD PAL195: B14_0 Mask              */
+#define LCD_PAL195_I1_Pos                                     31                                                        /*!< LCD PAL195: I1 Position             */
+#define LCD_PAL195_I1_Msk                                     (0x01UL << LCD_PAL195_I1_Pos)                             /*!< LCD PAL195: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL196  -------------------------------------------
+#define LCD_PAL196_R04_0_Pos                                  0                                                         /*!< LCD PAL196: R04_0 Position          */
+#define LCD_PAL196_R04_0_Msk                                  (0x1fUL << LCD_PAL196_R04_0_Pos)                          /*!< LCD PAL196: R04_0 Mask              */
+#define LCD_PAL196_G04_0_Pos                                  5                                                         /*!< LCD PAL196: G04_0 Position          */
+#define LCD_PAL196_G04_0_Msk                                  (0x1fUL << LCD_PAL196_G04_0_Pos)                          /*!< LCD PAL196: G04_0 Mask              */
+#define LCD_PAL196_B04_0_Pos                                  10                                                        /*!< LCD PAL196: B04_0 Position          */
+#define LCD_PAL196_B04_0_Msk                                  (0x1fUL << LCD_PAL196_B04_0_Pos)                          /*!< LCD PAL196: B04_0 Mask              */
+#define LCD_PAL196_I0_Pos                                     15                                                        /*!< LCD PAL196: I0 Position             */
+#define LCD_PAL196_I0_Msk                                     (0x01UL << LCD_PAL196_I0_Pos)                             /*!< LCD PAL196: I0 Mask                 */
+#define LCD_PAL196_R14_0_Pos                                  16                                                        /*!< LCD PAL196: R14_0 Position          */
+#define LCD_PAL196_R14_0_Msk                                  (0x1fUL << LCD_PAL196_R14_0_Pos)                          /*!< LCD PAL196: R14_0 Mask              */
+#define LCD_PAL196_G14_0_Pos                                  21                                                        /*!< LCD PAL196: G14_0 Position          */
+#define LCD_PAL196_G14_0_Msk                                  (0x1fUL << LCD_PAL196_G14_0_Pos)                          /*!< LCD PAL196: G14_0 Mask              */
+#define LCD_PAL196_B14_0_Pos                                  26                                                        /*!< LCD PAL196: B14_0 Position          */
+#define LCD_PAL196_B14_0_Msk                                  (0x1fUL << LCD_PAL196_B14_0_Pos)                          /*!< LCD PAL196: B14_0 Mask              */
+#define LCD_PAL196_I1_Pos                                     31                                                        /*!< LCD PAL196: I1 Position             */
+#define LCD_PAL196_I1_Msk                                     (0x01UL << LCD_PAL196_I1_Pos)                             /*!< LCD PAL196: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL197  -------------------------------------------
+#define LCD_PAL197_R04_0_Pos                                  0                                                         /*!< LCD PAL197: R04_0 Position          */
+#define LCD_PAL197_R04_0_Msk                                  (0x1fUL << LCD_PAL197_R04_0_Pos)                          /*!< LCD PAL197: R04_0 Mask              */
+#define LCD_PAL197_G04_0_Pos                                  5                                                         /*!< LCD PAL197: G04_0 Position          */
+#define LCD_PAL197_G04_0_Msk                                  (0x1fUL << LCD_PAL197_G04_0_Pos)                          /*!< LCD PAL197: G04_0 Mask              */
+#define LCD_PAL197_B04_0_Pos                                  10                                                        /*!< LCD PAL197: B04_0 Position          */
+#define LCD_PAL197_B04_0_Msk                                  (0x1fUL << LCD_PAL197_B04_0_Pos)                          /*!< LCD PAL197: B04_0 Mask              */
+#define LCD_PAL197_I0_Pos                                     15                                                        /*!< LCD PAL197: I0 Position             */
+#define LCD_PAL197_I0_Msk                                     (0x01UL << LCD_PAL197_I0_Pos)                             /*!< LCD PAL197: I0 Mask                 */
+#define LCD_PAL197_R14_0_Pos                                  16                                                        /*!< LCD PAL197: R14_0 Position          */
+#define LCD_PAL197_R14_0_Msk                                  (0x1fUL << LCD_PAL197_R14_0_Pos)                          /*!< LCD PAL197: R14_0 Mask              */
+#define LCD_PAL197_G14_0_Pos                                  21                                                        /*!< LCD PAL197: G14_0 Position          */
+#define LCD_PAL197_G14_0_Msk                                  (0x1fUL << LCD_PAL197_G14_0_Pos)                          /*!< LCD PAL197: G14_0 Mask              */
+#define LCD_PAL197_B14_0_Pos                                  26                                                        /*!< LCD PAL197: B14_0 Position          */
+#define LCD_PAL197_B14_0_Msk                                  (0x1fUL << LCD_PAL197_B14_0_Pos)                          /*!< LCD PAL197: B14_0 Mask              */
+#define LCD_PAL197_I1_Pos                                     31                                                        /*!< LCD PAL197: I1 Position             */
+#define LCD_PAL197_I1_Msk                                     (0x01UL << LCD_PAL197_I1_Pos)                             /*!< LCD PAL197: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL198  -------------------------------------------
+#define LCD_PAL198_R04_0_Pos                                  0                                                         /*!< LCD PAL198: R04_0 Position          */
+#define LCD_PAL198_R04_0_Msk                                  (0x1fUL << LCD_PAL198_R04_0_Pos)                          /*!< LCD PAL198: R04_0 Mask              */
+#define LCD_PAL198_G04_0_Pos                                  5                                                         /*!< LCD PAL198: G04_0 Position          */
+#define LCD_PAL198_G04_0_Msk                                  (0x1fUL << LCD_PAL198_G04_0_Pos)                          /*!< LCD PAL198: G04_0 Mask              */
+#define LCD_PAL198_B04_0_Pos                                  10                                                        /*!< LCD PAL198: B04_0 Position          */
+#define LCD_PAL198_B04_0_Msk                                  (0x1fUL << LCD_PAL198_B04_0_Pos)                          /*!< LCD PAL198: B04_0 Mask              */
+#define LCD_PAL198_I0_Pos                                     15                                                        /*!< LCD PAL198: I0 Position             */
+#define LCD_PAL198_I0_Msk                                     (0x01UL << LCD_PAL198_I0_Pos)                             /*!< LCD PAL198: I0 Mask                 */
+#define LCD_PAL198_R14_0_Pos                                  16                                                        /*!< LCD PAL198: R14_0 Position          */
+#define LCD_PAL198_R14_0_Msk                                  (0x1fUL << LCD_PAL198_R14_0_Pos)                          /*!< LCD PAL198: R14_0 Mask              */
+#define LCD_PAL198_G14_0_Pos                                  21                                                        /*!< LCD PAL198: G14_0 Position          */
+#define LCD_PAL198_G14_0_Msk                                  (0x1fUL << LCD_PAL198_G14_0_Pos)                          /*!< LCD PAL198: G14_0 Mask              */
+#define LCD_PAL198_B14_0_Pos                                  26                                                        /*!< LCD PAL198: B14_0 Position          */
+#define LCD_PAL198_B14_0_Msk                                  (0x1fUL << LCD_PAL198_B14_0_Pos)                          /*!< LCD PAL198: B14_0 Mask              */
+#define LCD_PAL198_I1_Pos                                     31                                                        /*!< LCD PAL198: I1 Position             */
+#define LCD_PAL198_I1_Msk                                     (0x01UL << LCD_PAL198_I1_Pos)                             /*!< LCD PAL198: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL199  -------------------------------------------
+#define LCD_PAL199_R04_0_Pos                                  0                                                         /*!< LCD PAL199: R04_0 Position          */
+#define LCD_PAL199_R04_0_Msk                                  (0x1fUL << LCD_PAL199_R04_0_Pos)                          /*!< LCD PAL199: R04_0 Mask              */
+#define LCD_PAL199_G04_0_Pos                                  5                                                         /*!< LCD PAL199: G04_0 Position          */
+#define LCD_PAL199_G04_0_Msk                                  (0x1fUL << LCD_PAL199_G04_0_Pos)                          /*!< LCD PAL199: G04_0 Mask              */
+#define LCD_PAL199_B04_0_Pos                                  10                                                        /*!< LCD PAL199: B04_0 Position          */
+#define LCD_PAL199_B04_0_Msk                                  (0x1fUL << LCD_PAL199_B04_0_Pos)                          /*!< LCD PAL199: B04_0 Mask              */
+#define LCD_PAL199_I0_Pos                                     15                                                        /*!< LCD PAL199: I0 Position             */
+#define LCD_PAL199_I0_Msk                                     (0x01UL << LCD_PAL199_I0_Pos)                             /*!< LCD PAL199: I0 Mask                 */
+#define LCD_PAL199_R14_0_Pos                                  16                                                        /*!< LCD PAL199: R14_0 Position          */
+#define LCD_PAL199_R14_0_Msk                                  (0x1fUL << LCD_PAL199_R14_0_Pos)                          /*!< LCD PAL199: R14_0 Mask              */
+#define LCD_PAL199_G14_0_Pos                                  21                                                        /*!< LCD PAL199: G14_0 Position          */
+#define LCD_PAL199_G14_0_Msk                                  (0x1fUL << LCD_PAL199_G14_0_Pos)                          /*!< LCD PAL199: G14_0 Mask              */
+#define LCD_PAL199_B14_0_Pos                                  26                                                        /*!< LCD PAL199: B14_0 Position          */
+#define LCD_PAL199_B14_0_Msk                                  (0x1fUL << LCD_PAL199_B14_0_Pos)                          /*!< LCD PAL199: B14_0 Mask              */
+#define LCD_PAL199_I1_Pos                                     31                                                        /*!< LCD PAL199: I1 Position             */
+#define LCD_PAL199_I1_Msk                                     (0x01UL << LCD_PAL199_I1_Pos)                             /*!< LCD PAL199: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL200  -------------------------------------------
+#define LCD_PAL200_R04_0_Pos                                  0                                                         /*!< LCD PAL200: R04_0 Position          */
+#define LCD_PAL200_R04_0_Msk                                  (0x1fUL << LCD_PAL200_R04_0_Pos)                          /*!< LCD PAL200: R04_0 Mask              */
+#define LCD_PAL200_G04_0_Pos                                  5                                                         /*!< LCD PAL200: G04_0 Position          */
+#define LCD_PAL200_G04_0_Msk                                  (0x1fUL << LCD_PAL200_G04_0_Pos)                          /*!< LCD PAL200: G04_0 Mask              */
+#define LCD_PAL200_B04_0_Pos                                  10                                                        /*!< LCD PAL200: B04_0 Position          */
+#define LCD_PAL200_B04_0_Msk                                  (0x1fUL << LCD_PAL200_B04_0_Pos)                          /*!< LCD PAL200: B04_0 Mask              */
+#define LCD_PAL200_I0_Pos                                     15                                                        /*!< LCD PAL200: I0 Position             */
+#define LCD_PAL200_I0_Msk                                     (0x01UL << LCD_PAL200_I0_Pos)                             /*!< LCD PAL200: I0 Mask                 */
+#define LCD_PAL200_R14_0_Pos                                  16                                                        /*!< LCD PAL200: R14_0 Position          */
+#define LCD_PAL200_R14_0_Msk                                  (0x1fUL << LCD_PAL200_R14_0_Pos)                          /*!< LCD PAL200: R14_0 Mask              */
+#define LCD_PAL200_G14_0_Pos                                  21                                                        /*!< LCD PAL200: G14_0 Position          */
+#define LCD_PAL200_G14_0_Msk                                  (0x1fUL << LCD_PAL200_G14_0_Pos)                          /*!< LCD PAL200: G14_0 Mask              */
+#define LCD_PAL200_B14_0_Pos                                  26                                                        /*!< LCD PAL200: B14_0 Position          */
+#define LCD_PAL200_B14_0_Msk                                  (0x1fUL << LCD_PAL200_B14_0_Pos)                          /*!< LCD PAL200: B14_0 Mask              */
+#define LCD_PAL200_I1_Pos                                     31                                                        /*!< LCD PAL200: I1 Position             */
+#define LCD_PAL200_I1_Msk                                     (0x01UL << LCD_PAL200_I1_Pos)                             /*!< LCD PAL200: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL201  -------------------------------------------
+#define LCD_PAL201_R04_0_Pos                                  0                                                         /*!< LCD PAL201: R04_0 Position          */
+#define LCD_PAL201_R04_0_Msk                                  (0x1fUL << LCD_PAL201_R04_0_Pos)                          /*!< LCD PAL201: R04_0 Mask              */
+#define LCD_PAL201_G04_0_Pos                                  5                                                         /*!< LCD PAL201: G04_0 Position          */
+#define LCD_PAL201_G04_0_Msk                                  (0x1fUL << LCD_PAL201_G04_0_Pos)                          /*!< LCD PAL201: G04_0 Mask              */
+#define LCD_PAL201_B04_0_Pos                                  10                                                        /*!< LCD PAL201: B04_0 Position          */
+#define LCD_PAL201_B04_0_Msk                                  (0x1fUL << LCD_PAL201_B04_0_Pos)                          /*!< LCD PAL201: B04_0 Mask              */
+#define LCD_PAL201_I0_Pos                                     15                                                        /*!< LCD PAL201: I0 Position             */
+#define LCD_PAL201_I0_Msk                                     (0x01UL << LCD_PAL201_I0_Pos)                             /*!< LCD PAL201: I0 Mask                 */
+#define LCD_PAL201_R14_0_Pos                                  16                                                        /*!< LCD PAL201: R14_0 Position          */
+#define LCD_PAL201_R14_0_Msk                                  (0x1fUL << LCD_PAL201_R14_0_Pos)                          /*!< LCD PAL201: R14_0 Mask              */
+#define LCD_PAL201_G14_0_Pos                                  21                                                        /*!< LCD PAL201: G14_0 Position          */
+#define LCD_PAL201_G14_0_Msk                                  (0x1fUL << LCD_PAL201_G14_0_Pos)                          /*!< LCD PAL201: G14_0 Mask              */
+#define LCD_PAL201_B14_0_Pos                                  26                                                        /*!< LCD PAL201: B14_0 Position          */
+#define LCD_PAL201_B14_0_Msk                                  (0x1fUL << LCD_PAL201_B14_0_Pos)                          /*!< LCD PAL201: B14_0 Mask              */
+#define LCD_PAL201_I1_Pos                                     31                                                        /*!< LCD PAL201: I1 Position             */
+#define LCD_PAL201_I1_Msk                                     (0x01UL << LCD_PAL201_I1_Pos)                             /*!< LCD PAL201: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL202  -------------------------------------------
+#define LCD_PAL202_R04_0_Pos                                  0                                                         /*!< LCD PAL202: R04_0 Position          */
+#define LCD_PAL202_R04_0_Msk                                  (0x1fUL << LCD_PAL202_R04_0_Pos)                          /*!< LCD PAL202: R04_0 Mask              */
+#define LCD_PAL202_G04_0_Pos                                  5                                                         /*!< LCD PAL202: G04_0 Position          */
+#define LCD_PAL202_G04_0_Msk                                  (0x1fUL << LCD_PAL202_G04_0_Pos)                          /*!< LCD PAL202: G04_0 Mask              */
+#define LCD_PAL202_B04_0_Pos                                  10                                                        /*!< LCD PAL202: B04_0 Position          */
+#define LCD_PAL202_B04_0_Msk                                  (0x1fUL << LCD_PAL202_B04_0_Pos)                          /*!< LCD PAL202: B04_0 Mask              */
+#define LCD_PAL202_I0_Pos                                     15                                                        /*!< LCD PAL202: I0 Position             */
+#define LCD_PAL202_I0_Msk                                     (0x01UL << LCD_PAL202_I0_Pos)                             /*!< LCD PAL202: I0 Mask                 */
+#define LCD_PAL202_R14_0_Pos                                  16                                                        /*!< LCD PAL202: R14_0 Position          */
+#define LCD_PAL202_R14_0_Msk                                  (0x1fUL << LCD_PAL202_R14_0_Pos)                          /*!< LCD PAL202: R14_0 Mask              */
+#define LCD_PAL202_G14_0_Pos                                  21                                                        /*!< LCD PAL202: G14_0 Position          */
+#define LCD_PAL202_G14_0_Msk                                  (0x1fUL << LCD_PAL202_G14_0_Pos)                          /*!< LCD PAL202: G14_0 Mask              */
+#define LCD_PAL202_B14_0_Pos                                  26                                                        /*!< LCD PAL202: B14_0 Position          */
+#define LCD_PAL202_B14_0_Msk                                  (0x1fUL << LCD_PAL202_B14_0_Pos)                          /*!< LCD PAL202: B14_0 Mask              */
+#define LCD_PAL202_I1_Pos                                     31                                                        /*!< LCD PAL202: I1 Position             */
+#define LCD_PAL202_I1_Msk                                     (0x01UL << LCD_PAL202_I1_Pos)                             /*!< LCD PAL202: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL203  -------------------------------------------
+#define LCD_PAL203_R04_0_Pos                                  0                                                         /*!< LCD PAL203: R04_0 Position          */
+#define LCD_PAL203_R04_0_Msk                                  (0x1fUL << LCD_PAL203_R04_0_Pos)                          /*!< LCD PAL203: R04_0 Mask              */
+#define LCD_PAL203_G04_0_Pos                                  5                                                         /*!< LCD PAL203: G04_0 Position          */
+#define LCD_PAL203_G04_0_Msk                                  (0x1fUL << LCD_PAL203_G04_0_Pos)                          /*!< LCD PAL203: G04_0 Mask              */
+#define LCD_PAL203_B04_0_Pos                                  10                                                        /*!< LCD PAL203: B04_0 Position          */
+#define LCD_PAL203_B04_0_Msk                                  (0x1fUL << LCD_PAL203_B04_0_Pos)                          /*!< LCD PAL203: B04_0 Mask              */
+#define LCD_PAL203_I0_Pos                                     15                                                        /*!< LCD PAL203: I0 Position             */
+#define LCD_PAL203_I0_Msk                                     (0x01UL << LCD_PAL203_I0_Pos)                             /*!< LCD PAL203: I0 Mask                 */
+#define LCD_PAL203_R14_0_Pos                                  16                                                        /*!< LCD PAL203: R14_0 Position          */
+#define LCD_PAL203_R14_0_Msk                                  (0x1fUL << LCD_PAL203_R14_0_Pos)                          /*!< LCD PAL203: R14_0 Mask              */
+#define LCD_PAL203_G14_0_Pos                                  21                                                        /*!< LCD PAL203: G14_0 Position          */
+#define LCD_PAL203_G14_0_Msk                                  (0x1fUL << LCD_PAL203_G14_0_Pos)                          /*!< LCD PAL203: G14_0 Mask              */
+#define LCD_PAL203_B14_0_Pos                                  26                                                        /*!< LCD PAL203: B14_0 Position          */
+#define LCD_PAL203_B14_0_Msk                                  (0x1fUL << LCD_PAL203_B14_0_Pos)                          /*!< LCD PAL203: B14_0 Mask              */
+#define LCD_PAL203_I1_Pos                                     31                                                        /*!< LCD PAL203: I1 Position             */
+#define LCD_PAL203_I1_Msk                                     (0x01UL << LCD_PAL203_I1_Pos)                             /*!< LCD PAL203: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL204  -------------------------------------------
+#define LCD_PAL204_R04_0_Pos                                  0                                                         /*!< LCD PAL204: R04_0 Position          */
+#define LCD_PAL204_R04_0_Msk                                  (0x1fUL << LCD_PAL204_R04_0_Pos)                          /*!< LCD PAL204: R04_0 Mask              */
+#define LCD_PAL204_G04_0_Pos                                  5                                                         /*!< LCD PAL204: G04_0 Position          */
+#define LCD_PAL204_G04_0_Msk                                  (0x1fUL << LCD_PAL204_G04_0_Pos)                          /*!< LCD PAL204: G04_0 Mask              */
+#define LCD_PAL204_B04_0_Pos                                  10                                                        /*!< LCD PAL204: B04_0 Position          */
+#define LCD_PAL204_B04_0_Msk                                  (0x1fUL << LCD_PAL204_B04_0_Pos)                          /*!< LCD PAL204: B04_0 Mask              */
+#define LCD_PAL204_I0_Pos                                     15                                                        /*!< LCD PAL204: I0 Position             */
+#define LCD_PAL204_I0_Msk                                     (0x01UL << LCD_PAL204_I0_Pos)                             /*!< LCD PAL204: I0 Mask                 */
+#define LCD_PAL204_R14_0_Pos                                  16                                                        /*!< LCD PAL204: R14_0 Position          */
+#define LCD_PAL204_R14_0_Msk                                  (0x1fUL << LCD_PAL204_R14_0_Pos)                          /*!< LCD PAL204: R14_0 Mask              */
+#define LCD_PAL204_G14_0_Pos                                  21                                                        /*!< LCD PAL204: G14_0 Position          */
+#define LCD_PAL204_G14_0_Msk                                  (0x1fUL << LCD_PAL204_G14_0_Pos)                          /*!< LCD PAL204: G14_0 Mask              */
+#define LCD_PAL204_B14_0_Pos                                  26                                                        /*!< LCD PAL204: B14_0 Position          */
+#define LCD_PAL204_B14_0_Msk                                  (0x1fUL << LCD_PAL204_B14_0_Pos)                          /*!< LCD PAL204: B14_0 Mask              */
+#define LCD_PAL204_I1_Pos                                     31                                                        /*!< LCD PAL204: I1 Position             */
+#define LCD_PAL204_I1_Msk                                     (0x01UL << LCD_PAL204_I1_Pos)                             /*!< LCD PAL204: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL205  -------------------------------------------
+#define LCD_PAL205_R04_0_Pos                                  0                                                         /*!< LCD PAL205: R04_0 Position          */
+#define LCD_PAL205_R04_0_Msk                                  (0x1fUL << LCD_PAL205_R04_0_Pos)                          /*!< LCD PAL205: R04_0 Mask              */
+#define LCD_PAL205_G04_0_Pos                                  5                                                         /*!< LCD PAL205: G04_0 Position          */
+#define LCD_PAL205_G04_0_Msk                                  (0x1fUL << LCD_PAL205_G04_0_Pos)                          /*!< LCD PAL205: G04_0 Mask              */
+#define LCD_PAL205_B04_0_Pos                                  10                                                        /*!< LCD PAL205: B04_0 Position          */
+#define LCD_PAL205_B04_0_Msk                                  (0x1fUL << LCD_PAL205_B04_0_Pos)                          /*!< LCD PAL205: B04_0 Mask              */
+#define LCD_PAL205_I0_Pos                                     15                                                        /*!< LCD PAL205: I0 Position             */
+#define LCD_PAL205_I0_Msk                                     (0x01UL << LCD_PAL205_I0_Pos)                             /*!< LCD PAL205: I0 Mask                 */
+#define LCD_PAL205_R14_0_Pos                                  16                                                        /*!< LCD PAL205: R14_0 Position          */
+#define LCD_PAL205_R14_0_Msk                                  (0x1fUL << LCD_PAL205_R14_0_Pos)                          /*!< LCD PAL205: R14_0 Mask              */
+#define LCD_PAL205_G14_0_Pos                                  21                                                        /*!< LCD PAL205: G14_0 Position          */
+#define LCD_PAL205_G14_0_Msk                                  (0x1fUL << LCD_PAL205_G14_0_Pos)                          /*!< LCD PAL205: G14_0 Mask              */
+#define LCD_PAL205_B14_0_Pos                                  26                                                        /*!< LCD PAL205: B14_0 Position          */
+#define LCD_PAL205_B14_0_Msk                                  (0x1fUL << LCD_PAL205_B14_0_Pos)                          /*!< LCD PAL205: B14_0 Mask              */
+#define LCD_PAL205_I1_Pos                                     31                                                        /*!< LCD PAL205: I1 Position             */
+#define LCD_PAL205_I1_Msk                                     (0x01UL << LCD_PAL205_I1_Pos)                             /*!< LCD PAL205: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL206  -------------------------------------------
+#define LCD_PAL206_R04_0_Pos                                  0                                                         /*!< LCD PAL206: R04_0 Position          */
+#define LCD_PAL206_R04_0_Msk                                  (0x1fUL << LCD_PAL206_R04_0_Pos)                          /*!< LCD PAL206: R04_0 Mask              */
+#define LCD_PAL206_G04_0_Pos                                  5                                                         /*!< LCD PAL206: G04_0 Position          */
+#define LCD_PAL206_G04_0_Msk                                  (0x1fUL << LCD_PAL206_G04_0_Pos)                          /*!< LCD PAL206: G04_0 Mask              */
+#define LCD_PAL206_B04_0_Pos                                  10                                                        /*!< LCD PAL206: B04_0 Position          */
+#define LCD_PAL206_B04_0_Msk                                  (0x1fUL << LCD_PAL206_B04_0_Pos)                          /*!< LCD PAL206: B04_0 Mask              */
+#define LCD_PAL206_I0_Pos                                     15                                                        /*!< LCD PAL206: I0 Position             */
+#define LCD_PAL206_I0_Msk                                     (0x01UL << LCD_PAL206_I0_Pos)                             /*!< LCD PAL206: I0 Mask                 */
+#define LCD_PAL206_R14_0_Pos                                  16                                                        /*!< LCD PAL206: R14_0 Position          */
+#define LCD_PAL206_R14_0_Msk                                  (0x1fUL << LCD_PAL206_R14_0_Pos)                          /*!< LCD PAL206: R14_0 Mask              */
+#define LCD_PAL206_G14_0_Pos                                  21                                                        /*!< LCD PAL206: G14_0 Position          */
+#define LCD_PAL206_G14_0_Msk                                  (0x1fUL << LCD_PAL206_G14_0_Pos)                          /*!< LCD PAL206: G14_0 Mask              */
+#define LCD_PAL206_B14_0_Pos                                  26                                                        /*!< LCD PAL206: B14_0 Position          */
+#define LCD_PAL206_B14_0_Msk                                  (0x1fUL << LCD_PAL206_B14_0_Pos)                          /*!< LCD PAL206: B14_0 Mask              */
+#define LCD_PAL206_I1_Pos                                     31                                                        /*!< LCD PAL206: I1 Position             */
+#define LCD_PAL206_I1_Msk                                     (0x01UL << LCD_PAL206_I1_Pos)                             /*!< LCD PAL206: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL207  -------------------------------------------
+#define LCD_PAL207_R04_0_Pos                                  0                                                         /*!< LCD PAL207: R04_0 Position          */
+#define LCD_PAL207_R04_0_Msk                                  (0x1fUL << LCD_PAL207_R04_0_Pos)                          /*!< LCD PAL207: R04_0 Mask              */
+#define LCD_PAL207_G04_0_Pos                                  5                                                         /*!< LCD PAL207: G04_0 Position          */
+#define LCD_PAL207_G04_0_Msk                                  (0x1fUL << LCD_PAL207_G04_0_Pos)                          /*!< LCD PAL207: G04_0 Mask              */
+#define LCD_PAL207_B04_0_Pos                                  10                                                        /*!< LCD PAL207: B04_0 Position          */
+#define LCD_PAL207_B04_0_Msk                                  (0x1fUL << LCD_PAL207_B04_0_Pos)                          /*!< LCD PAL207: B04_0 Mask              */
+#define LCD_PAL207_I0_Pos                                     15                                                        /*!< LCD PAL207: I0 Position             */
+#define LCD_PAL207_I0_Msk                                     (0x01UL << LCD_PAL207_I0_Pos)                             /*!< LCD PAL207: I0 Mask                 */
+#define LCD_PAL207_R14_0_Pos                                  16                                                        /*!< LCD PAL207: R14_0 Position          */
+#define LCD_PAL207_R14_0_Msk                                  (0x1fUL << LCD_PAL207_R14_0_Pos)                          /*!< LCD PAL207: R14_0 Mask              */
+#define LCD_PAL207_G14_0_Pos                                  21                                                        /*!< LCD PAL207: G14_0 Position          */
+#define LCD_PAL207_G14_0_Msk                                  (0x1fUL << LCD_PAL207_G14_0_Pos)                          /*!< LCD PAL207: G14_0 Mask              */
+#define LCD_PAL207_B14_0_Pos                                  26                                                        /*!< LCD PAL207: B14_0 Position          */
+#define LCD_PAL207_B14_0_Msk                                  (0x1fUL << LCD_PAL207_B14_0_Pos)                          /*!< LCD PAL207: B14_0 Mask              */
+#define LCD_PAL207_I1_Pos                                     31                                                        /*!< LCD PAL207: I1 Position             */
+#define LCD_PAL207_I1_Msk                                     (0x01UL << LCD_PAL207_I1_Pos)                             /*!< LCD PAL207: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL208  -------------------------------------------
+#define LCD_PAL208_R04_0_Pos                                  0                                                         /*!< LCD PAL208: R04_0 Position          */
+#define LCD_PAL208_R04_0_Msk                                  (0x1fUL << LCD_PAL208_R04_0_Pos)                          /*!< LCD PAL208: R04_0 Mask              */
+#define LCD_PAL208_G04_0_Pos                                  5                                                         /*!< LCD PAL208: G04_0 Position          */
+#define LCD_PAL208_G04_0_Msk                                  (0x1fUL << LCD_PAL208_G04_0_Pos)                          /*!< LCD PAL208: G04_0 Mask              */
+#define LCD_PAL208_B04_0_Pos                                  10                                                        /*!< LCD PAL208: B04_0 Position          */
+#define LCD_PAL208_B04_0_Msk                                  (0x1fUL << LCD_PAL208_B04_0_Pos)                          /*!< LCD PAL208: B04_0 Mask              */
+#define LCD_PAL208_I0_Pos                                     15                                                        /*!< LCD PAL208: I0 Position             */
+#define LCD_PAL208_I0_Msk                                     (0x01UL << LCD_PAL208_I0_Pos)                             /*!< LCD PAL208: I0 Mask                 */
+#define LCD_PAL208_R14_0_Pos                                  16                                                        /*!< LCD PAL208: R14_0 Position          */
+#define LCD_PAL208_R14_0_Msk                                  (0x1fUL << LCD_PAL208_R14_0_Pos)                          /*!< LCD PAL208: R14_0 Mask              */
+#define LCD_PAL208_G14_0_Pos                                  21                                                        /*!< LCD PAL208: G14_0 Position          */
+#define LCD_PAL208_G14_0_Msk                                  (0x1fUL << LCD_PAL208_G14_0_Pos)                          /*!< LCD PAL208: G14_0 Mask              */
+#define LCD_PAL208_B14_0_Pos                                  26                                                        /*!< LCD PAL208: B14_0 Position          */
+#define LCD_PAL208_B14_0_Msk                                  (0x1fUL << LCD_PAL208_B14_0_Pos)                          /*!< LCD PAL208: B14_0 Mask              */
+#define LCD_PAL208_I1_Pos                                     31                                                        /*!< LCD PAL208: I1 Position             */
+#define LCD_PAL208_I1_Msk                                     (0x01UL << LCD_PAL208_I1_Pos)                             /*!< LCD PAL208: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL209  -------------------------------------------
+#define LCD_PAL209_R04_0_Pos                                  0                                                         /*!< LCD PAL209: R04_0 Position          */
+#define LCD_PAL209_R04_0_Msk                                  (0x1fUL << LCD_PAL209_R04_0_Pos)                          /*!< LCD PAL209: R04_0 Mask              */
+#define LCD_PAL209_G04_0_Pos                                  5                                                         /*!< LCD PAL209: G04_0 Position          */
+#define LCD_PAL209_G04_0_Msk                                  (0x1fUL << LCD_PAL209_G04_0_Pos)                          /*!< LCD PAL209: G04_0 Mask              */
+#define LCD_PAL209_B04_0_Pos                                  10                                                        /*!< LCD PAL209: B04_0 Position          */
+#define LCD_PAL209_B04_0_Msk                                  (0x1fUL << LCD_PAL209_B04_0_Pos)                          /*!< LCD PAL209: B04_0 Mask              */
+#define LCD_PAL209_I0_Pos                                     15                                                        /*!< LCD PAL209: I0 Position             */
+#define LCD_PAL209_I0_Msk                                     (0x01UL << LCD_PAL209_I0_Pos)                             /*!< LCD PAL209: I0 Mask                 */
+#define LCD_PAL209_R14_0_Pos                                  16                                                        /*!< LCD PAL209: R14_0 Position          */
+#define LCD_PAL209_R14_0_Msk                                  (0x1fUL << LCD_PAL209_R14_0_Pos)                          /*!< LCD PAL209: R14_0 Mask              */
+#define LCD_PAL209_G14_0_Pos                                  21                                                        /*!< LCD PAL209: G14_0 Position          */
+#define LCD_PAL209_G14_0_Msk                                  (0x1fUL << LCD_PAL209_G14_0_Pos)                          /*!< LCD PAL209: G14_0 Mask              */
+#define LCD_PAL209_B14_0_Pos                                  26                                                        /*!< LCD PAL209: B14_0 Position          */
+#define LCD_PAL209_B14_0_Msk                                  (0x1fUL << LCD_PAL209_B14_0_Pos)                          /*!< LCD PAL209: B14_0 Mask              */
+#define LCD_PAL209_I1_Pos                                     31                                                        /*!< LCD PAL209: I1 Position             */
+#define LCD_PAL209_I1_Msk                                     (0x01UL << LCD_PAL209_I1_Pos)                             /*!< LCD PAL209: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL210  -------------------------------------------
+#define LCD_PAL210_R04_0_Pos                                  0                                                         /*!< LCD PAL210: R04_0 Position          */
+#define LCD_PAL210_R04_0_Msk                                  (0x1fUL << LCD_PAL210_R04_0_Pos)                          /*!< LCD PAL210: R04_0 Mask              */
+#define LCD_PAL210_G04_0_Pos                                  5                                                         /*!< LCD PAL210: G04_0 Position          */
+#define LCD_PAL210_G04_0_Msk                                  (0x1fUL << LCD_PAL210_G04_0_Pos)                          /*!< LCD PAL210: G04_0 Mask              */
+#define LCD_PAL210_B04_0_Pos                                  10                                                        /*!< LCD PAL210: B04_0 Position          */
+#define LCD_PAL210_B04_0_Msk                                  (0x1fUL << LCD_PAL210_B04_0_Pos)                          /*!< LCD PAL210: B04_0 Mask              */
+#define LCD_PAL210_I0_Pos                                     15                                                        /*!< LCD PAL210: I0 Position             */
+#define LCD_PAL210_I0_Msk                                     (0x01UL << LCD_PAL210_I0_Pos)                             /*!< LCD PAL210: I0 Mask                 */
+#define LCD_PAL210_R14_0_Pos                                  16                                                        /*!< LCD PAL210: R14_0 Position          */
+#define LCD_PAL210_R14_0_Msk                                  (0x1fUL << LCD_PAL210_R14_0_Pos)                          /*!< LCD PAL210: R14_0 Mask              */
+#define LCD_PAL210_G14_0_Pos                                  21                                                        /*!< LCD PAL210: G14_0 Position          */
+#define LCD_PAL210_G14_0_Msk                                  (0x1fUL << LCD_PAL210_G14_0_Pos)                          /*!< LCD PAL210: G14_0 Mask              */
+#define LCD_PAL210_B14_0_Pos                                  26                                                        /*!< LCD PAL210: B14_0 Position          */
+#define LCD_PAL210_B14_0_Msk                                  (0x1fUL << LCD_PAL210_B14_0_Pos)                          /*!< LCD PAL210: B14_0 Mask              */
+#define LCD_PAL210_I1_Pos                                     31                                                        /*!< LCD PAL210: I1 Position             */
+#define LCD_PAL210_I1_Msk                                     (0x01UL << LCD_PAL210_I1_Pos)                             /*!< LCD PAL210: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL211  -------------------------------------------
+#define LCD_PAL211_R04_0_Pos                                  0                                                         /*!< LCD PAL211: R04_0 Position          */
+#define LCD_PAL211_R04_0_Msk                                  (0x1fUL << LCD_PAL211_R04_0_Pos)                          /*!< LCD PAL211: R04_0 Mask              */
+#define LCD_PAL211_G04_0_Pos                                  5                                                         /*!< LCD PAL211: G04_0 Position          */
+#define LCD_PAL211_G04_0_Msk                                  (0x1fUL << LCD_PAL211_G04_0_Pos)                          /*!< LCD PAL211: G04_0 Mask              */
+#define LCD_PAL211_B04_0_Pos                                  10                                                        /*!< LCD PAL211: B04_0 Position          */
+#define LCD_PAL211_B04_0_Msk                                  (0x1fUL << LCD_PAL211_B04_0_Pos)                          /*!< LCD PAL211: B04_0 Mask              */
+#define LCD_PAL211_I0_Pos                                     15                                                        /*!< LCD PAL211: I0 Position             */
+#define LCD_PAL211_I0_Msk                                     (0x01UL << LCD_PAL211_I0_Pos)                             /*!< LCD PAL211: I0 Mask                 */
+#define LCD_PAL211_R14_0_Pos                                  16                                                        /*!< LCD PAL211: R14_0 Position          */
+#define LCD_PAL211_R14_0_Msk                                  (0x1fUL << LCD_PAL211_R14_0_Pos)                          /*!< LCD PAL211: R14_0 Mask              */
+#define LCD_PAL211_G14_0_Pos                                  21                                                        /*!< LCD PAL211: G14_0 Position          */
+#define LCD_PAL211_G14_0_Msk                                  (0x1fUL << LCD_PAL211_G14_0_Pos)                          /*!< LCD PAL211: G14_0 Mask              */
+#define LCD_PAL211_B14_0_Pos                                  26                                                        /*!< LCD PAL211: B14_0 Position          */
+#define LCD_PAL211_B14_0_Msk                                  (0x1fUL << LCD_PAL211_B14_0_Pos)                          /*!< LCD PAL211: B14_0 Mask              */
+#define LCD_PAL211_I1_Pos                                     31                                                        /*!< LCD PAL211: I1 Position             */
+#define LCD_PAL211_I1_Msk                                     (0x01UL << LCD_PAL211_I1_Pos)                             /*!< LCD PAL211: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL212  -------------------------------------------
+#define LCD_PAL212_R04_0_Pos                                  0                                                         /*!< LCD PAL212: R04_0 Position          */
+#define LCD_PAL212_R04_0_Msk                                  (0x1fUL << LCD_PAL212_R04_0_Pos)                          /*!< LCD PAL212: R04_0 Mask              */
+#define LCD_PAL212_G04_0_Pos                                  5                                                         /*!< LCD PAL212: G04_0 Position          */
+#define LCD_PAL212_G04_0_Msk                                  (0x1fUL << LCD_PAL212_G04_0_Pos)                          /*!< LCD PAL212: G04_0 Mask              */
+#define LCD_PAL212_B04_0_Pos                                  10                                                        /*!< LCD PAL212: B04_0 Position          */
+#define LCD_PAL212_B04_0_Msk                                  (0x1fUL << LCD_PAL212_B04_0_Pos)                          /*!< LCD PAL212: B04_0 Mask              */
+#define LCD_PAL212_I0_Pos                                     15                                                        /*!< LCD PAL212: I0 Position             */
+#define LCD_PAL212_I0_Msk                                     (0x01UL << LCD_PAL212_I0_Pos)                             /*!< LCD PAL212: I0 Mask                 */
+#define LCD_PAL212_R14_0_Pos                                  16                                                        /*!< LCD PAL212: R14_0 Position          */
+#define LCD_PAL212_R14_0_Msk                                  (0x1fUL << LCD_PAL212_R14_0_Pos)                          /*!< LCD PAL212: R14_0 Mask              */
+#define LCD_PAL212_G14_0_Pos                                  21                                                        /*!< LCD PAL212: G14_0 Position          */
+#define LCD_PAL212_G14_0_Msk                                  (0x1fUL << LCD_PAL212_G14_0_Pos)                          /*!< LCD PAL212: G14_0 Mask              */
+#define LCD_PAL212_B14_0_Pos                                  26                                                        /*!< LCD PAL212: B14_0 Position          */
+#define LCD_PAL212_B14_0_Msk                                  (0x1fUL << LCD_PAL212_B14_0_Pos)                          /*!< LCD PAL212: B14_0 Mask              */
+#define LCD_PAL212_I1_Pos                                     31                                                        /*!< LCD PAL212: I1 Position             */
+#define LCD_PAL212_I1_Msk                                     (0x01UL << LCD_PAL212_I1_Pos)                             /*!< LCD PAL212: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL213  -------------------------------------------
+#define LCD_PAL213_R04_0_Pos                                  0                                                         /*!< LCD PAL213: R04_0 Position          */
+#define LCD_PAL213_R04_0_Msk                                  (0x1fUL << LCD_PAL213_R04_0_Pos)                          /*!< LCD PAL213: R04_0 Mask              */
+#define LCD_PAL213_G04_0_Pos                                  5                                                         /*!< LCD PAL213: G04_0 Position          */
+#define LCD_PAL213_G04_0_Msk                                  (0x1fUL << LCD_PAL213_G04_0_Pos)                          /*!< LCD PAL213: G04_0 Mask              */
+#define LCD_PAL213_B04_0_Pos                                  10                                                        /*!< LCD PAL213: B04_0 Position          */
+#define LCD_PAL213_B04_0_Msk                                  (0x1fUL << LCD_PAL213_B04_0_Pos)                          /*!< LCD PAL213: B04_0 Mask              */
+#define LCD_PAL213_I0_Pos                                     15                                                        /*!< LCD PAL213: I0 Position             */
+#define LCD_PAL213_I0_Msk                                     (0x01UL << LCD_PAL213_I0_Pos)                             /*!< LCD PAL213: I0 Mask                 */
+#define LCD_PAL213_R14_0_Pos                                  16                                                        /*!< LCD PAL213: R14_0 Position          */
+#define LCD_PAL213_R14_0_Msk                                  (0x1fUL << LCD_PAL213_R14_0_Pos)                          /*!< LCD PAL213: R14_0 Mask              */
+#define LCD_PAL213_G14_0_Pos                                  21                                                        /*!< LCD PAL213: G14_0 Position          */
+#define LCD_PAL213_G14_0_Msk                                  (0x1fUL << LCD_PAL213_G14_0_Pos)                          /*!< LCD PAL213: G14_0 Mask              */
+#define LCD_PAL213_B14_0_Pos                                  26                                                        /*!< LCD PAL213: B14_0 Position          */
+#define LCD_PAL213_B14_0_Msk                                  (0x1fUL << LCD_PAL213_B14_0_Pos)                          /*!< LCD PAL213: B14_0 Mask              */
+#define LCD_PAL213_I1_Pos                                     31                                                        /*!< LCD PAL213: I1 Position             */
+#define LCD_PAL213_I1_Msk                                     (0x01UL << LCD_PAL213_I1_Pos)                             /*!< LCD PAL213: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL214  -------------------------------------------
+#define LCD_PAL214_R04_0_Pos                                  0                                                         /*!< LCD PAL214: R04_0 Position          */
+#define LCD_PAL214_R04_0_Msk                                  (0x1fUL << LCD_PAL214_R04_0_Pos)                          /*!< LCD PAL214: R04_0 Mask              */
+#define LCD_PAL214_G04_0_Pos                                  5                                                         /*!< LCD PAL214: G04_0 Position          */
+#define LCD_PAL214_G04_0_Msk                                  (0x1fUL << LCD_PAL214_G04_0_Pos)                          /*!< LCD PAL214: G04_0 Mask              */
+#define LCD_PAL214_B04_0_Pos                                  10                                                        /*!< LCD PAL214: B04_0 Position          */
+#define LCD_PAL214_B04_0_Msk                                  (0x1fUL << LCD_PAL214_B04_0_Pos)                          /*!< LCD PAL214: B04_0 Mask              */
+#define LCD_PAL214_I0_Pos                                     15                                                        /*!< LCD PAL214: I0 Position             */
+#define LCD_PAL214_I0_Msk                                     (0x01UL << LCD_PAL214_I0_Pos)                             /*!< LCD PAL214: I0 Mask                 */
+#define LCD_PAL214_R14_0_Pos                                  16                                                        /*!< LCD PAL214: R14_0 Position          */
+#define LCD_PAL214_R14_0_Msk                                  (0x1fUL << LCD_PAL214_R14_0_Pos)                          /*!< LCD PAL214: R14_0 Mask              */
+#define LCD_PAL214_G14_0_Pos                                  21                                                        /*!< LCD PAL214: G14_0 Position          */
+#define LCD_PAL214_G14_0_Msk                                  (0x1fUL << LCD_PAL214_G14_0_Pos)                          /*!< LCD PAL214: G14_0 Mask              */
+#define LCD_PAL214_B14_0_Pos                                  26                                                        /*!< LCD PAL214: B14_0 Position          */
+#define LCD_PAL214_B14_0_Msk                                  (0x1fUL << LCD_PAL214_B14_0_Pos)                          /*!< LCD PAL214: B14_0 Mask              */
+#define LCD_PAL214_I1_Pos                                     31                                                        /*!< LCD PAL214: I1 Position             */
+#define LCD_PAL214_I1_Msk                                     (0x01UL << LCD_PAL214_I1_Pos)                             /*!< LCD PAL214: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL215  -------------------------------------------
+#define LCD_PAL215_R04_0_Pos                                  0                                                         /*!< LCD PAL215: R04_0 Position          */
+#define LCD_PAL215_R04_0_Msk                                  (0x1fUL << LCD_PAL215_R04_0_Pos)                          /*!< LCD PAL215: R04_0 Mask              */
+#define LCD_PAL215_G04_0_Pos                                  5                                                         /*!< LCD PAL215: G04_0 Position          */
+#define LCD_PAL215_G04_0_Msk                                  (0x1fUL << LCD_PAL215_G04_0_Pos)                          /*!< LCD PAL215: G04_0 Mask              */
+#define LCD_PAL215_B04_0_Pos                                  10                                                        /*!< LCD PAL215: B04_0 Position          */
+#define LCD_PAL215_B04_0_Msk                                  (0x1fUL << LCD_PAL215_B04_0_Pos)                          /*!< LCD PAL215: B04_0 Mask              */
+#define LCD_PAL215_I0_Pos                                     15                                                        /*!< LCD PAL215: I0 Position             */
+#define LCD_PAL215_I0_Msk                                     (0x01UL << LCD_PAL215_I0_Pos)                             /*!< LCD PAL215: I0 Mask                 */
+#define LCD_PAL215_R14_0_Pos                                  16                                                        /*!< LCD PAL215: R14_0 Position          */
+#define LCD_PAL215_R14_0_Msk                                  (0x1fUL << LCD_PAL215_R14_0_Pos)                          /*!< LCD PAL215: R14_0 Mask              */
+#define LCD_PAL215_G14_0_Pos                                  21                                                        /*!< LCD PAL215: G14_0 Position          */
+#define LCD_PAL215_G14_0_Msk                                  (0x1fUL << LCD_PAL215_G14_0_Pos)                          /*!< LCD PAL215: G14_0 Mask              */
+#define LCD_PAL215_B14_0_Pos                                  26                                                        /*!< LCD PAL215: B14_0 Position          */
+#define LCD_PAL215_B14_0_Msk                                  (0x1fUL << LCD_PAL215_B14_0_Pos)                          /*!< LCD PAL215: B14_0 Mask              */
+#define LCD_PAL215_I1_Pos                                     31                                                        /*!< LCD PAL215: I1 Position             */
+#define LCD_PAL215_I1_Msk                                     (0x01UL << LCD_PAL215_I1_Pos)                             /*!< LCD PAL215: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL216  -------------------------------------------
+#define LCD_PAL216_R04_0_Pos                                  0                                                         /*!< LCD PAL216: R04_0 Position          */
+#define LCD_PAL216_R04_0_Msk                                  (0x1fUL << LCD_PAL216_R04_0_Pos)                          /*!< LCD PAL216: R04_0 Mask              */
+#define LCD_PAL216_G04_0_Pos                                  5                                                         /*!< LCD PAL216: G04_0 Position          */
+#define LCD_PAL216_G04_0_Msk                                  (0x1fUL << LCD_PAL216_G04_0_Pos)                          /*!< LCD PAL216: G04_0 Mask              */
+#define LCD_PAL216_B04_0_Pos                                  10                                                        /*!< LCD PAL216: B04_0 Position          */
+#define LCD_PAL216_B04_0_Msk                                  (0x1fUL << LCD_PAL216_B04_0_Pos)                          /*!< LCD PAL216: B04_0 Mask              */
+#define LCD_PAL216_I0_Pos                                     15                                                        /*!< LCD PAL216: I0 Position             */
+#define LCD_PAL216_I0_Msk                                     (0x01UL << LCD_PAL216_I0_Pos)                             /*!< LCD PAL216: I0 Mask                 */
+#define LCD_PAL216_R14_0_Pos                                  16                                                        /*!< LCD PAL216: R14_0 Position          */
+#define LCD_PAL216_R14_0_Msk                                  (0x1fUL << LCD_PAL216_R14_0_Pos)                          /*!< LCD PAL216: R14_0 Mask              */
+#define LCD_PAL216_G14_0_Pos                                  21                                                        /*!< LCD PAL216: G14_0 Position          */
+#define LCD_PAL216_G14_0_Msk                                  (0x1fUL << LCD_PAL216_G14_0_Pos)                          /*!< LCD PAL216: G14_0 Mask              */
+#define LCD_PAL216_B14_0_Pos                                  26                                                        /*!< LCD PAL216: B14_0 Position          */
+#define LCD_PAL216_B14_0_Msk                                  (0x1fUL << LCD_PAL216_B14_0_Pos)                          /*!< LCD PAL216: B14_0 Mask              */
+#define LCD_PAL216_I1_Pos                                     31                                                        /*!< LCD PAL216: I1 Position             */
+#define LCD_PAL216_I1_Msk                                     (0x01UL << LCD_PAL216_I1_Pos)                             /*!< LCD PAL216: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL217  -------------------------------------------
+#define LCD_PAL217_R04_0_Pos                                  0                                                         /*!< LCD PAL217: R04_0 Position          */
+#define LCD_PAL217_R04_0_Msk                                  (0x1fUL << LCD_PAL217_R04_0_Pos)                          /*!< LCD PAL217: R04_0 Mask              */
+#define LCD_PAL217_G04_0_Pos                                  5                                                         /*!< LCD PAL217: G04_0 Position          */
+#define LCD_PAL217_G04_0_Msk                                  (0x1fUL << LCD_PAL217_G04_0_Pos)                          /*!< LCD PAL217: G04_0 Mask              */
+#define LCD_PAL217_B04_0_Pos                                  10                                                        /*!< LCD PAL217: B04_0 Position          */
+#define LCD_PAL217_B04_0_Msk                                  (0x1fUL << LCD_PAL217_B04_0_Pos)                          /*!< LCD PAL217: B04_0 Mask              */
+#define LCD_PAL217_I0_Pos                                     15                                                        /*!< LCD PAL217: I0 Position             */
+#define LCD_PAL217_I0_Msk                                     (0x01UL << LCD_PAL217_I0_Pos)                             /*!< LCD PAL217: I0 Mask                 */
+#define LCD_PAL217_R14_0_Pos                                  16                                                        /*!< LCD PAL217: R14_0 Position          */
+#define LCD_PAL217_R14_0_Msk                                  (0x1fUL << LCD_PAL217_R14_0_Pos)                          /*!< LCD PAL217: R14_0 Mask              */
+#define LCD_PAL217_G14_0_Pos                                  21                                                        /*!< LCD PAL217: G14_0 Position          */
+#define LCD_PAL217_G14_0_Msk                                  (0x1fUL << LCD_PAL217_G14_0_Pos)                          /*!< LCD PAL217: G14_0 Mask              */
+#define LCD_PAL217_B14_0_Pos                                  26                                                        /*!< LCD PAL217: B14_0 Position          */
+#define LCD_PAL217_B14_0_Msk                                  (0x1fUL << LCD_PAL217_B14_0_Pos)                          /*!< LCD PAL217: B14_0 Mask              */
+#define LCD_PAL217_I1_Pos                                     31                                                        /*!< LCD PAL217: I1 Position             */
+#define LCD_PAL217_I1_Msk                                     (0x01UL << LCD_PAL217_I1_Pos)                             /*!< LCD PAL217: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL218  -------------------------------------------
+#define LCD_PAL218_R04_0_Pos                                  0                                                         /*!< LCD PAL218: R04_0 Position          */
+#define LCD_PAL218_R04_0_Msk                                  (0x1fUL << LCD_PAL218_R04_0_Pos)                          /*!< LCD PAL218: R04_0 Mask              */
+#define LCD_PAL218_G04_0_Pos                                  5                                                         /*!< LCD PAL218: G04_0 Position          */
+#define LCD_PAL218_G04_0_Msk                                  (0x1fUL << LCD_PAL218_G04_0_Pos)                          /*!< LCD PAL218: G04_0 Mask              */
+#define LCD_PAL218_B04_0_Pos                                  10                                                        /*!< LCD PAL218: B04_0 Position          */
+#define LCD_PAL218_B04_0_Msk                                  (0x1fUL << LCD_PAL218_B04_0_Pos)                          /*!< LCD PAL218: B04_0 Mask              */
+#define LCD_PAL218_I0_Pos                                     15                                                        /*!< LCD PAL218: I0 Position             */
+#define LCD_PAL218_I0_Msk                                     (0x01UL << LCD_PAL218_I0_Pos)                             /*!< LCD PAL218: I0 Mask                 */
+#define LCD_PAL218_R14_0_Pos                                  16                                                        /*!< LCD PAL218: R14_0 Position          */
+#define LCD_PAL218_R14_0_Msk                                  (0x1fUL << LCD_PAL218_R14_0_Pos)                          /*!< LCD PAL218: R14_0 Mask              */
+#define LCD_PAL218_G14_0_Pos                                  21                                                        /*!< LCD PAL218: G14_0 Position          */
+#define LCD_PAL218_G14_0_Msk                                  (0x1fUL << LCD_PAL218_G14_0_Pos)                          /*!< LCD PAL218: G14_0 Mask              */
+#define LCD_PAL218_B14_0_Pos                                  26                                                        /*!< LCD PAL218: B14_0 Position          */
+#define LCD_PAL218_B14_0_Msk                                  (0x1fUL << LCD_PAL218_B14_0_Pos)                          /*!< LCD PAL218: B14_0 Mask              */
+#define LCD_PAL218_I1_Pos                                     31                                                        /*!< LCD PAL218: I1 Position             */
+#define LCD_PAL218_I1_Msk                                     (0x01UL << LCD_PAL218_I1_Pos)                             /*!< LCD PAL218: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL219  -------------------------------------------
+#define LCD_PAL219_R04_0_Pos                                  0                                                         /*!< LCD PAL219: R04_0 Position          */
+#define LCD_PAL219_R04_0_Msk                                  (0x1fUL << LCD_PAL219_R04_0_Pos)                          /*!< LCD PAL219: R04_0 Mask              */
+#define LCD_PAL219_G04_0_Pos                                  5                                                         /*!< LCD PAL219: G04_0 Position          */
+#define LCD_PAL219_G04_0_Msk                                  (0x1fUL << LCD_PAL219_G04_0_Pos)                          /*!< LCD PAL219: G04_0 Mask              */
+#define LCD_PAL219_B04_0_Pos                                  10                                                        /*!< LCD PAL219: B04_0 Position          */
+#define LCD_PAL219_B04_0_Msk                                  (0x1fUL << LCD_PAL219_B04_0_Pos)                          /*!< LCD PAL219: B04_0 Mask              */
+#define LCD_PAL219_I0_Pos                                     15                                                        /*!< LCD PAL219: I0 Position             */
+#define LCD_PAL219_I0_Msk                                     (0x01UL << LCD_PAL219_I0_Pos)                             /*!< LCD PAL219: I0 Mask                 */
+#define LCD_PAL219_R14_0_Pos                                  16                                                        /*!< LCD PAL219: R14_0 Position          */
+#define LCD_PAL219_R14_0_Msk                                  (0x1fUL << LCD_PAL219_R14_0_Pos)                          /*!< LCD PAL219: R14_0 Mask              */
+#define LCD_PAL219_G14_0_Pos                                  21                                                        /*!< LCD PAL219: G14_0 Position          */
+#define LCD_PAL219_G14_0_Msk                                  (0x1fUL << LCD_PAL219_G14_0_Pos)                          /*!< LCD PAL219: G14_0 Mask              */
+#define LCD_PAL219_B14_0_Pos                                  26                                                        /*!< LCD PAL219: B14_0 Position          */
+#define LCD_PAL219_B14_0_Msk                                  (0x1fUL << LCD_PAL219_B14_0_Pos)                          /*!< LCD PAL219: B14_0 Mask              */
+#define LCD_PAL219_I1_Pos                                     31                                                        /*!< LCD PAL219: I1 Position             */
+#define LCD_PAL219_I1_Msk                                     (0x01UL << LCD_PAL219_I1_Pos)                             /*!< LCD PAL219: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL220  -------------------------------------------
+#define LCD_PAL220_R04_0_Pos                                  0                                                         /*!< LCD PAL220: R04_0 Position          */
+#define LCD_PAL220_R04_0_Msk                                  (0x1fUL << LCD_PAL220_R04_0_Pos)                          /*!< LCD PAL220: R04_0 Mask              */
+#define LCD_PAL220_G04_0_Pos                                  5                                                         /*!< LCD PAL220: G04_0 Position          */
+#define LCD_PAL220_G04_0_Msk                                  (0x1fUL << LCD_PAL220_G04_0_Pos)                          /*!< LCD PAL220: G04_0 Mask              */
+#define LCD_PAL220_B04_0_Pos                                  10                                                        /*!< LCD PAL220: B04_0 Position          */
+#define LCD_PAL220_B04_0_Msk                                  (0x1fUL << LCD_PAL220_B04_0_Pos)                          /*!< LCD PAL220: B04_0 Mask              */
+#define LCD_PAL220_I0_Pos                                     15                                                        /*!< LCD PAL220: I0 Position             */
+#define LCD_PAL220_I0_Msk                                     (0x01UL << LCD_PAL220_I0_Pos)                             /*!< LCD PAL220: I0 Mask                 */
+#define LCD_PAL220_R14_0_Pos                                  16                                                        /*!< LCD PAL220: R14_0 Position          */
+#define LCD_PAL220_R14_0_Msk                                  (0x1fUL << LCD_PAL220_R14_0_Pos)                          /*!< LCD PAL220: R14_0 Mask              */
+#define LCD_PAL220_G14_0_Pos                                  21                                                        /*!< LCD PAL220: G14_0 Position          */
+#define LCD_PAL220_G14_0_Msk                                  (0x1fUL << LCD_PAL220_G14_0_Pos)                          /*!< LCD PAL220: G14_0 Mask              */
+#define LCD_PAL220_B14_0_Pos                                  26                                                        /*!< LCD PAL220: B14_0 Position          */
+#define LCD_PAL220_B14_0_Msk                                  (0x1fUL << LCD_PAL220_B14_0_Pos)                          /*!< LCD PAL220: B14_0 Mask              */
+#define LCD_PAL220_I1_Pos                                     31                                                        /*!< LCD PAL220: I1 Position             */
+#define LCD_PAL220_I1_Msk                                     (0x01UL << LCD_PAL220_I1_Pos)                             /*!< LCD PAL220: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL221  -------------------------------------------
+#define LCD_PAL221_R04_0_Pos                                  0                                                         /*!< LCD PAL221: R04_0 Position          */
+#define LCD_PAL221_R04_0_Msk                                  (0x1fUL << LCD_PAL221_R04_0_Pos)                          /*!< LCD PAL221: R04_0 Mask              */
+#define LCD_PAL221_G04_0_Pos                                  5                                                         /*!< LCD PAL221: G04_0 Position          */
+#define LCD_PAL221_G04_0_Msk                                  (0x1fUL << LCD_PAL221_G04_0_Pos)                          /*!< LCD PAL221: G04_0 Mask              */
+#define LCD_PAL221_B04_0_Pos                                  10                                                        /*!< LCD PAL221: B04_0 Position          */
+#define LCD_PAL221_B04_0_Msk                                  (0x1fUL << LCD_PAL221_B04_0_Pos)                          /*!< LCD PAL221: B04_0 Mask              */
+#define LCD_PAL221_I0_Pos                                     15                                                        /*!< LCD PAL221: I0 Position             */
+#define LCD_PAL221_I0_Msk                                     (0x01UL << LCD_PAL221_I0_Pos)                             /*!< LCD PAL221: I0 Mask                 */
+#define LCD_PAL221_R14_0_Pos                                  16                                                        /*!< LCD PAL221: R14_0 Position          */
+#define LCD_PAL221_R14_0_Msk                                  (0x1fUL << LCD_PAL221_R14_0_Pos)                          /*!< LCD PAL221: R14_0 Mask              */
+#define LCD_PAL221_G14_0_Pos                                  21                                                        /*!< LCD PAL221: G14_0 Position          */
+#define LCD_PAL221_G14_0_Msk                                  (0x1fUL << LCD_PAL221_G14_0_Pos)                          /*!< LCD PAL221: G14_0 Mask              */
+#define LCD_PAL221_B14_0_Pos                                  26                                                        /*!< LCD PAL221: B14_0 Position          */
+#define LCD_PAL221_B14_0_Msk                                  (0x1fUL << LCD_PAL221_B14_0_Pos)                          /*!< LCD PAL221: B14_0 Mask              */
+#define LCD_PAL221_I1_Pos                                     31                                                        /*!< LCD PAL221: I1 Position             */
+#define LCD_PAL221_I1_Msk                                     (0x01UL << LCD_PAL221_I1_Pos)                             /*!< LCD PAL221: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL222  -------------------------------------------
+#define LCD_PAL222_R04_0_Pos                                  0                                                         /*!< LCD PAL222: R04_0 Position          */
+#define LCD_PAL222_R04_0_Msk                                  (0x1fUL << LCD_PAL222_R04_0_Pos)                          /*!< LCD PAL222: R04_0 Mask              */
+#define LCD_PAL222_G04_0_Pos                                  5                                                         /*!< LCD PAL222: G04_0 Position          */
+#define LCD_PAL222_G04_0_Msk                                  (0x1fUL << LCD_PAL222_G04_0_Pos)                          /*!< LCD PAL222: G04_0 Mask              */
+#define LCD_PAL222_B04_0_Pos                                  10                                                        /*!< LCD PAL222: B04_0 Position          */
+#define LCD_PAL222_B04_0_Msk                                  (0x1fUL << LCD_PAL222_B04_0_Pos)                          /*!< LCD PAL222: B04_0 Mask              */
+#define LCD_PAL222_I0_Pos                                     15                                                        /*!< LCD PAL222: I0 Position             */
+#define LCD_PAL222_I0_Msk                                     (0x01UL << LCD_PAL222_I0_Pos)                             /*!< LCD PAL222: I0 Mask                 */
+#define LCD_PAL222_R14_0_Pos                                  16                                                        /*!< LCD PAL222: R14_0 Position          */
+#define LCD_PAL222_R14_0_Msk                                  (0x1fUL << LCD_PAL222_R14_0_Pos)                          /*!< LCD PAL222: R14_0 Mask              */
+#define LCD_PAL222_G14_0_Pos                                  21                                                        /*!< LCD PAL222: G14_0 Position          */
+#define LCD_PAL222_G14_0_Msk                                  (0x1fUL << LCD_PAL222_G14_0_Pos)                          /*!< LCD PAL222: G14_0 Mask              */
+#define LCD_PAL222_B14_0_Pos                                  26                                                        /*!< LCD PAL222: B14_0 Position          */
+#define LCD_PAL222_B14_0_Msk                                  (0x1fUL << LCD_PAL222_B14_0_Pos)                          /*!< LCD PAL222: B14_0 Mask              */
+#define LCD_PAL222_I1_Pos                                     31                                                        /*!< LCD PAL222: I1 Position             */
+#define LCD_PAL222_I1_Msk                                     (0x01UL << LCD_PAL222_I1_Pos)                             /*!< LCD PAL222: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL223  -------------------------------------------
+#define LCD_PAL223_R04_0_Pos                                  0                                                         /*!< LCD PAL223: R04_0 Position          */
+#define LCD_PAL223_R04_0_Msk                                  (0x1fUL << LCD_PAL223_R04_0_Pos)                          /*!< LCD PAL223: R04_0 Mask              */
+#define LCD_PAL223_G04_0_Pos                                  5                                                         /*!< LCD PAL223: G04_0 Position          */
+#define LCD_PAL223_G04_0_Msk                                  (0x1fUL << LCD_PAL223_G04_0_Pos)                          /*!< LCD PAL223: G04_0 Mask              */
+#define LCD_PAL223_B04_0_Pos                                  10                                                        /*!< LCD PAL223: B04_0 Position          */
+#define LCD_PAL223_B04_0_Msk                                  (0x1fUL << LCD_PAL223_B04_0_Pos)                          /*!< LCD PAL223: B04_0 Mask              */
+#define LCD_PAL223_I0_Pos                                     15                                                        /*!< LCD PAL223: I0 Position             */
+#define LCD_PAL223_I0_Msk                                     (0x01UL << LCD_PAL223_I0_Pos)                             /*!< LCD PAL223: I0 Mask                 */
+#define LCD_PAL223_R14_0_Pos                                  16                                                        /*!< LCD PAL223: R14_0 Position          */
+#define LCD_PAL223_R14_0_Msk                                  (0x1fUL << LCD_PAL223_R14_0_Pos)                          /*!< LCD PAL223: R14_0 Mask              */
+#define LCD_PAL223_G14_0_Pos                                  21                                                        /*!< LCD PAL223: G14_0 Position          */
+#define LCD_PAL223_G14_0_Msk                                  (0x1fUL << LCD_PAL223_G14_0_Pos)                          /*!< LCD PAL223: G14_0 Mask              */
+#define LCD_PAL223_B14_0_Pos                                  26                                                        /*!< LCD PAL223: B14_0 Position          */
+#define LCD_PAL223_B14_0_Msk                                  (0x1fUL << LCD_PAL223_B14_0_Pos)                          /*!< LCD PAL223: B14_0 Mask              */
+#define LCD_PAL223_I1_Pos                                     31                                                        /*!< LCD PAL223: I1 Position             */
+#define LCD_PAL223_I1_Msk                                     (0x01UL << LCD_PAL223_I1_Pos)                             /*!< LCD PAL223: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL224  -------------------------------------------
+#define LCD_PAL224_R04_0_Pos                                  0                                                         /*!< LCD PAL224: R04_0 Position          */
+#define LCD_PAL224_R04_0_Msk                                  (0x1fUL << LCD_PAL224_R04_0_Pos)                          /*!< LCD PAL224: R04_0 Mask              */
+#define LCD_PAL224_G04_0_Pos                                  5                                                         /*!< LCD PAL224: G04_0 Position          */
+#define LCD_PAL224_G04_0_Msk                                  (0x1fUL << LCD_PAL224_G04_0_Pos)                          /*!< LCD PAL224: G04_0 Mask              */
+#define LCD_PAL224_B04_0_Pos                                  10                                                        /*!< LCD PAL224: B04_0 Position          */
+#define LCD_PAL224_B04_0_Msk                                  (0x1fUL << LCD_PAL224_B04_0_Pos)                          /*!< LCD PAL224: B04_0 Mask              */
+#define LCD_PAL224_I0_Pos                                     15                                                        /*!< LCD PAL224: I0 Position             */
+#define LCD_PAL224_I0_Msk                                     (0x01UL << LCD_PAL224_I0_Pos)                             /*!< LCD PAL224: I0 Mask                 */
+#define LCD_PAL224_R14_0_Pos                                  16                                                        /*!< LCD PAL224: R14_0 Position          */
+#define LCD_PAL224_R14_0_Msk                                  (0x1fUL << LCD_PAL224_R14_0_Pos)                          /*!< LCD PAL224: R14_0 Mask              */
+#define LCD_PAL224_G14_0_Pos                                  21                                                        /*!< LCD PAL224: G14_0 Position          */
+#define LCD_PAL224_G14_0_Msk                                  (0x1fUL << LCD_PAL224_G14_0_Pos)                          /*!< LCD PAL224: G14_0 Mask              */
+#define LCD_PAL224_B14_0_Pos                                  26                                                        /*!< LCD PAL224: B14_0 Position          */
+#define LCD_PAL224_B14_0_Msk                                  (0x1fUL << LCD_PAL224_B14_0_Pos)                          /*!< LCD PAL224: B14_0 Mask              */
+#define LCD_PAL224_I1_Pos                                     31                                                        /*!< LCD PAL224: I1 Position             */
+#define LCD_PAL224_I1_Msk                                     (0x01UL << LCD_PAL224_I1_Pos)                             /*!< LCD PAL224: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL225  -------------------------------------------
+#define LCD_PAL225_R04_0_Pos                                  0                                                         /*!< LCD PAL225: R04_0 Position          */
+#define LCD_PAL225_R04_0_Msk                                  (0x1fUL << LCD_PAL225_R04_0_Pos)                          /*!< LCD PAL225: R04_0 Mask              */
+#define LCD_PAL225_G04_0_Pos                                  5                                                         /*!< LCD PAL225: G04_0 Position          */
+#define LCD_PAL225_G04_0_Msk                                  (0x1fUL << LCD_PAL225_G04_0_Pos)                          /*!< LCD PAL225: G04_0 Mask              */
+#define LCD_PAL225_B04_0_Pos                                  10                                                        /*!< LCD PAL225: B04_0 Position          */
+#define LCD_PAL225_B04_0_Msk                                  (0x1fUL << LCD_PAL225_B04_0_Pos)                          /*!< LCD PAL225: B04_0 Mask              */
+#define LCD_PAL225_I0_Pos                                     15                                                        /*!< LCD PAL225: I0 Position             */
+#define LCD_PAL225_I0_Msk                                     (0x01UL << LCD_PAL225_I0_Pos)                             /*!< LCD PAL225: I0 Mask                 */
+#define LCD_PAL225_R14_0_Pos                                  16                                                        /*!< LCD PAL225: R14_0 Position          */
+#define LCD_PAL225_R14_0_Msk                                  (0x1fUL << LCD_PAL225_R14_0_Pos)                          /*!< LCD PAL225: R14_0 Mask              */
+#define LCD_PAL225_G14_0_Pos                                  21                                                        /*!< LCD PAL225: G14_0 Position          */
+#define LCD_PAL225_G14_0_Msk                                  (0x1fUL << LCD_PAL225_G14_0_Pos)                          /*!< LCD PAL225: G14_0 Mask              */
+#define LCD_PAL225_B14_0_Pos                                  26                                                        /*!< LCD PAL225: B14_0 Position          */
+#define LCD_PAL225_B14_0_Msk                                  (0x1fUL << LCD_PAL225_B14_0_Pos)                          /*!< LCD PAL225: B14_0 Mask              */
+#define LCD_PAL225_I1_Pos                                     31                                                        /*!< LCD PAL225: I1 Position             */
+#define LCD_PAL225_I1_Msk                                     (0x01UL << LCD_PAL225_I1_Pos)                             /*!< LCD PAL225: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL226  -------------------------------------------
+#define LCD_PAL226_R04_0_Pos                                  0                                                         /*!< LCD PAL226: R04_0 Position          */
+#define LCD_PAL226_R04_0_Msk                                  (0x1fUL << LCD_PAL226_R04_0_Pos)                          /*!< LCD PAL226: R04_0 Mask              */
+#define LCD_PAL226_G04_0_Pos                                  5                                                         /*!< LCD PAL226: G04_0 Position          */
+#define LCD_PAL226_G04_0_Msk                                  (0x1fUL << LCD_PAL226_G04_0_Pos)                          /*!< LCD PAL226: G04_0 Mask              */
+#define LCD_PAL226_B04_0_Pos                                  10                                                        /*!< LCD PAL226: B04_0 Position          */
+#define LCD_PAL226_B04_0_Msk                                  (0x1fUL << LCD_PAL226_B04_0_Pos)                          /*!< LCD PAL226: B04_0 Mask              */
+#define LCD_PAL226_I0_Pos                                     15                                                        /*!< LCD PAL226: I0 Position             */
+#define LCD_PAL226_I0_Msk                                     (0x01UL << LCD_PAL226_I0_Pos)                             /*!< LCD PAL226: I0 Mask                 */
+#define LCD_PAL226_R14_0_Pos                                  16                                                        /*!< LCD PAL226: R14_0 Position          */
+#define LCD_PAL226_R14_0_Msk                                  (0x1fUL << LCD_PAL226_R14_0_Pos)                          /*!< LCD PAL226: R14_0 Mask              */
+#define LCD_PAL226_G14_0_Pos                                  21                                                        /*!< LCD PAL226: G14_0 Position          */
+#define LCD_PAL226_G14_0_Msk                                  (0x1fUL << LCD_PAL226_G14_0_Pos)                          /*!< LCD PAL226: G14_0 Mask              */
+#define LCD_PAL226_B14_0_Pos                                  26                                                        /*!< LCD PAL226: B14_0 Position          */
+#define LCD_PAL226_B14_0_Msk                                  (0x1fUL << LCD_PAL226_B14_0_Pos)                          /*!< LCD PAL226: B14_0 Mask              */
+#define LCD_PAL226_I1_Pos                                     31                                                        /*!< LCD PAL226: I1 Position             */
+#define LCD_PAL226_I1_Msk                                     (0x01UL << LCD_PAL226_I1_Pos)                             /*!< LCD PAL226: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL227  -------------------------------------------
+#define LCD_PAL227_R04_0_Pos                                  0                                                         /*!< LCD PAL227: R04_0 Position          */
+#define LCD_PAL227_R04_0_Msk                                  (0x1fUL << LCD_PAL227_R04_0_Pos)                          /*!< LCD PAL227: R04_0 Mask              */
+#define LCD_PAL227_G04_0_Pos                                  5                                                         /*!< LCD PAL227: G04_0 Position          */
+#define LCD_PAL227_G04_0_Msk                                  (0x1fUL << LCD_PAL227_G04_0_Pos)                          /*!< LCD PAL227: G04_0 Mask              */
+#define LCD_PAL227_B04_0_Pos                                  10                                                        /*!< LCD PAL227: B04_0 Position          */
+#define LCD_PAL227_B04_0_Msk                                  (0x1fUL << LCD_PAL227_B04_0_Pos)                          /*!< LCD PAL227: B04_0 Mask              */
+#define LCD_PAL227_I0_Pos                                     15                                                        /*!< LCD PAL227: I0 Position             */
+#define LCD_PAL227_I0_Msk                                     (0x01UL << LCD_PAL227_I0_Pos)                             /*!< LCD PAL227: I0 Mask                 */
+#define LCD_PAL227_R14_0_Pos                                  16                                                        /*!< LCD PAL227: R14_0 Position          */
+#define LCD_PAL227_R14_0_Msk                                  (0x1fUL << LCD_PAL227_R14_0_Pos)                          /*!< LCD PAL227: R14_0 Mask              */
+#define LCD_PAL227_G14_0_Pos                                  21                                                        /*!< LCD PAL227: G14_0 Position          */
+#define LCD_PAL227_G14_0_Msk                                  (0x1fUL << LCD_PAL227_G14_0_Pos)                          /*!< LCD PAL227: G14_0 Mask              */
+#define LCD_PAL227_B14_0_Pos                                  26                                                        /*!< LCD PAL227: B14_0 Position          */
+#define LCD_PAL227_B14_0_Msk                                  (0x1fUL << LCD_PAL227_B14_0_Pos)                          /*!< LCD PAL227: B14_0 Mask              */
+#define LCD_PAL227_I1_Pos                                     31                                                        /*!< LCD PAL227: I1 Position             */
+#define LCD_PAL227_I1_Msk                                     (0x01UL << LCD_PAL227_I1_Pos)                             /*!< LCD PAL227: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL228  -------------------------------------------
+#define LCD_PAL228_R04_0_Pos                                  0                                                         /*!< LCD PAL228: R04_0 Position          */
+#define LCD_PAL228_R04_0_Msk                                  (0x1fUL << LCD_PAL228_R04_0_Pos)                          /*!< LCD PAL228: R04_0 Mask              */
+#define LCD_PAL228_G04_0_Pos                                  5                                                         /*!< LCD PAL228: G04_0 Position          */
+#define LCD_PAL228_G04_0_Msk                                  (0x1fUL << LCD_PAL228_G04_0_Pos)                          /*!< LCD PAL228: G04_0 Mask              */
+#define LCD_PAL228_B04_0_Pos                                  10                                                        /*!< LCD PAL228: B04_0 Position          */
+#define LCD_PAL228_B04_0_Msk                                  (0x1fUL << LCD_PAL228_B04_0_Pos)                          /*!< LCD PAL228: B04_0 Mask              */
+#define LCD_PAL228_I0_Pos                                     15                                                        /*!< LCD PAL228: I0 Position             */
+#define LCD_PAL228_I0_Msk                                     (0x01UL << LCD_PAL228_I0_Pos)                             /*!< LCD PAL228: I0 Mask                 */
+#define LCD_PAL228_R14_0_Pos                                  16                                                        /*!< LCD PAL228: R14_0 Position          */
+#define LCD_PAL228_R14_0_Msk                                  (0x1fUL << LCD_PAL228_R14_0_Pos)                          /*!< LCD PAL228: R14_0 Mask              */
+#define LCD_PAL228_G14_0_Pos                                  21                                                        /*!< LCD PAL228: G14_0 Position          */
+#define LCD_PAL228_G14_0_Msk                                  (0x1fUL << LCD_PAL228_G14_0_Pos)                          /*!< LCD PAL228: G14_0 Mask              */
+#define LCD_PAL228_B14_0_Pos                                  26                                                        /*!< LCD PAL228: B14_0 Position          */
+#define LCD_PAL228_B14_0_Msk                                  (0x1fUL << LCD_PAL228_B14_0_Pos)                          /*!< LCD PAL228: B14_0 Mask              */
+#define LCD_PAL228_I1_Pos                                     31                                                        /*!< LCD PAL228: I1 Position             */
+#define LCD_PAL228_I1_Msk                                     (0x01UL << LCD_PAL228_I1_Pos)                             /*!< LCD PAL228: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL229  -------------------------------------------
+#define LCD_PAL229_R04_0_Pos                                  0                                                         /*!< LCD PAL229: R04_0 Position          */
+#define LCD_PAL229_R04_0_Msk                                  (0x1fUL << LCD_PAL229_R04_0_Pos)                          /*!< LCD PAL229: R04_0 Mask              */
+#define LCD_PAL229_G04_0_Pos                                  5                                                         /*!< LCD PAL229: G04_0 Position          */
+#define LCD_PAL229_G04_0_Msk                                  (0x1fUL << LCD_PAL229_G04_0_Pos)                          /*!< LCD PAL229: G04_0 Mask              */
+#define LCD_PAL229_B04_0_Pos                                  10                                                        /*!< LCD PAL229: B04_0 Position          */
+#define LCD_PAL229_B04_0_Msk                                  (0x1fUL << LCD_PAL229_B04_0_Pos)                          /*!< LCD PAL229: B04_0 Mask              */
+#define LCD_PAL229_I0_Pos                                     15                                                        /*!< LCD PAL229: I0 Position             */
+#define LCD_PAL229_I0_Msk                                     (0x01UL << LCD_PAL229_I0_Pos)                             /*!< LCD PAL229: I0 Mask                 */
+#define LCD_PAL229_R14_0_Pos                                  16                                                        /*!< LCD PAL229: R14_0 Position          */
+#define LCD_PAL229_R14_0_Msk                                  (0x1fUL << LCD_PAL229_R14_0_Pos)                          /*!< LCD PAL229: R14_0 Mask              */
+#define LCD_PAL229_G14_0_Pos                                  21                                                        /*!< LCD PAL229: G14_0 Position          */
+#define LCD_PAL229_G14_0_Msk                                  (0x1fUL << LCD_PAL229_G14_0_Pos)                          /*!< LCD PAL229: G14_0 Mask              */
+#define LCD_PAL229_B14_0_Pos                                  26                                                        /*!< LCD PAL229: B14_0 Position          */
+#define LCD_PAL229_B14_0_Msk                                  (0x1fUL << LCD_PAL229_B14_0_Pos)                          /*!< LCD PAL229: B14_0 Mask              */
+#define LCD_PAL229_I1_Pos                                     31                                                        /*!< LCD PAL229: I1 Position             */
+#define LCD_PAL229_I1_Msk                                     (0x01UL << LCD_PAL229_I1_Pos)                             /*!< LCD PAL229: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL230  -------------------------------------------
+#define LCD_PAL230_R04_0_Pos                                  0                                                         /*!< LCD PAL230: R04_0 Position          */
+#define LCD_PAL230_R04_0_Msk                                  (0x1fUL << LCD_PAL230_R04_0_Pos)                          /*!< LCD PAL230: R04_0 Mask              */
+#define LCD_PAL230_G04_0_Pos                                  5                                                         /*!< LCD PAL230: G04_0 Position          */
+#define LCD_PAL230_G04_0_Msk                                  (0x1fUL << LCD_PAL230_G04_0_Pos)                          /*!< LCD PAL230: G04_0 Mask              */
+#define LCD_PAL230_B04_0_Pos                                  10                                                        /*!< LCD PAL230: B04_0 Position          */
+#define LCD_PAL230_B04_0_Msk                                  (0x1fUL << LCD_PAL230_B04_0_Pos)                          /*!< LCD PAL230: B04_0 Mask              */
+#define LCD_PAL230_I0_Pos                                     15                                                        /*!< LCD PAL230: I0 Position             */
+#define LCD_PAL230_I0_Msk                                     (0x01UL << LCD_PAL230_I0_Pos)                             /*!< LCD PAL230: I0 Mask                 */
+#define LCD_PAL230_R14_0_Pos                                  16                                                        /*!< LCD PAL230: R14_0 Position          */
+#define LCD_PAL230_R14_0_Msk                                  (0x1fUL << LCD_PAL230_R14_0_Pos)                          /*!< LCD PAL230: R14_0 Mask              */
+#define LCD_PAL230_G14_0_Pos                                  21                                                        /*!< LCD PAL230: G14_0 Position          */
+#define LCD_PAL230_G14_0_Msk                                  (0x1fUL << LCD_PAL230_G14_0_Pos)                          /*!< LCD PAL230: G14_0 Mask              */
+#define LCD_PAL230_B14_0_Pos                                  26                                                        /*!< LCD PAL230: B14_0 Position          */
+#define LCD_PAL230_B14_0_Msk                                  (0x1fUL << LCD_PAL230_B14_0_Pos)                          /*!< LCD PAL230: B14_0 Mask              */
+#define LCD_PAL230_I1_Pos                                     31                                                        /*!< LCD PAL230: I1 Position             */
+#define LCD_PAL230_I1_Msk                                     (0x01UL << LCD_PAL230_I1_Pos)                             /*!< LCD PAL230: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL231  -------------------------------------------
+#define LCD_PAL231_R04_0_Pos                                  0                                                         /*!< LCD PAL231: R04_0 Position          */
+#define LCD_PAL231_R04_0_Msk                                  (0x1fUL << LCD_PAL231_R04_0_Pos)                          /*!< LCD PAL231: R04_0 Mask              */
+#define LCD_PAL231_G04_0_Pos                                  5                                                         /*!< LCD PAL231: G04_0 Position          */
+#define LCD_PAL231_G04_0_Msk                                  (0x1fUL << LCD_PAL231_G04_0_Pos)                          /*!< LCD PAL231: G04_0 Mask              */
+#define LCD_PAL231_B04_0_Pos                                  10                                                        /*!< LCD PAL231: B04_0 Position          */
+#define LCD_PAL231_B04_0_Msk                                  (0x1fUL << LCD_PAL231_B04_0_Pos)                          /*!< LCD PAL231: B04_0 Mask              */
+#define LCD_PAL231_I0_Pos                                     15                                                        /*!< LCD PAL231: I0 Position             */
+#define LCD_PAL231_I0_Msk                                     (0x01UL << LCD_PAL231_I0_Pos)                             /*!< LCD PAL231: I0 Mask                 */
+#define LCD_PAL231_R14_0_Pos                                  16                                                        /*!< LCD PAL231: R14_0 Position          */
+#define LCD_PAL231_R14_0_Msk                                  (0x1fUL << LCD_PAL231_R14_0_Pos)                          /*!< LCD PAL231: R14_0 Mask              */
+#define LCD_PAL231_G14_0_Pos                                  21                                                        /*!< LCD PAL231: G14_0 Position          */
+#define LCD_PAL231_G14_0_Msk                                  (0x1fUL << LCD_PAL231_G14_0_Pos)                          /*!< LCD PAL231: G14_0 Mask              */
+#define LCD_PAL231_B14_0_Pos                                  26                                                        /*!< LCD PAL231: B14_0 Position          */
+#define LCD_PAL231_B14_0_Msk                                  (0x1fUL << LCD_PAL231_B14_0_Pos)                          /*!< LCD PAL231: B14_0 Mask              */
+#define LCD_PAL231_I1_Pos                                     31                                                        /*!< LCD PAL231: I1 Position             */
+#define LCD_PAL231_I1_Msk                                     (0x01UL << LCD_PAL231_I1_Pos)                             /*!< LCD PAL231: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL232  -------------------------------------------
+#define LCD_PAL232_R04_0_Pos                                  0                                                         /*!< LCD PAL232: R04_0 Position          */
+#define LCD_PAL232_R04_0_Msk                                  (0x1fUL << LCD_PAL232_R04_0_Pos)                          /*!< LCD PAL232: R04_0 Mask              */
+#define LCD_PAL232_G04_0_Pos                                  5                                                         /*!< LCD PAL232: G04_0 Position          */
+#define LCD_PAL232_G04_0_Msk                                  (0x1fUL << LCD_PAL232_G04_0_Pos)                          /*!< LCD PAL232: G04_0 Mask              */
+#define LCD_PAL232_B04_0_Pos                                  10                                                        /*!< LCD PAL232: B04_0 Position          */
+#define LCD_PAL232_B04_0_Msk                                  (0x1fUL << LCD_PAL232_B04_0_Pos)                          /*!< LCD PAL232: B04_0 Mask              */
+#define LCD_PAL232_I0_Pos                                     15                                                        /*!< LCD PAL232: I0 Position             */
+#define LCD_PAL232_I0_Msk                                     (0x01UL << LCD_PAL232_I0_Pos)                             /*!< LCD PAL232: I0 Mask                 */
+#define LCD_PAL232_R14_0_Pos                                  16                                                        /*!< LCD PAL232: R14_0 Position          */
+#define LCD_PAL232_R14_0_Msk                                  (0x1fUL << LCD_PAL232_R14_0_Pos)                          /*!< LCD PAL232: R14_0 Mask              */
+#define LCD_PAL232_G14_0_Pos                                  21                                                        /*!< LCD PAL232: G14_0 Position          */
+#define LCD_PAL232_G14_0_Msk                                  (0x1fUL << LCD_PAL232_G14_0_Pos)                          /*!< LCD PAL232: G14_0 Mask              */
+#define LCD_PAL232_B14_0_Pos                                  26                                                        /*!< LCD PAL232: B14_0 Position          */
+#define LCD_PAL232_B14_0_Msk                                  (0x1fUL << LCD_PAL232_B14_0_Pos)                          /*!< LCD PAL232: B14_0 Mask              */
+#define LCD_PAL232_I1_Pos                                     31                                                        /*!< LCD PAL232: I1 Position             */
+#define LCD_PAL232_I1_Msk                                     (0x01UL << LCD_PAL232_I1_Pos)                             /*!< LCD PAL232: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL233  -------------------------------------------
+#define LCD_PAL233_R04_0_Pos                                  0                                                         /*!< LCD PAL233: R04_0 Position          */
+#define LCD_PAL233_R04_0_Msk                                  (0x1fUL << LCD_PAL233_R04_0_Pos)                          /*!< LCD PAL233: R04_0 Mask              */
+#define LCD_PAL233_G04_0_Pos                                  5                                                         /*!< LCD PAL233: G04_0 Position          */
+#define LCD_PAL233_G04_0_Msk                                  (0x1fUL << LCD_PAL233_G04_0_Pos)                          /*!< LCD PAL233: G04_0 Mask              */
+#define LCD_PAL233_B04_0_Pos                                  10                                                        /*!< LCD PAL233: B04_0 Position          */
+#define LCD_PAL233_B04_0_Msk                                  (0x1fUL << LCD_PAL233_B04_0_Pos)                          /*!< LCD PAL233: B04_0 Mask              */
+#define LCD_PAL233_I0_Pos                                     15                                                        /*!< LCD PAL233: I0 Position             */
+#define LCD_PAL233_I0_Msk                                     (0x01UL << LCD_PAL233_I0_Pos)                             /*!< LCD PAL233: I0 Mask                 */
+#define LCD_PAL233_R14_0_Pos                                  16                                                        /*!< LCD PAL233: R14_0 Position          */
+#define LCD_PAL233_R14_0_Msk                                  (0x1fUL << LCD_PAL233_R14_0_Pos)                          /*!< LCD PAL233: R14_0 Mask              */
+#define LCD_PAL233_G14_0_Pos                                  21                                                        /*!< LCD PAL233: G14_0 Position          */
+#define LCD_PAL233_G14_0_Msk                                  (0x1fUL << LCD_PAL233_G14_0_Pos)                          /*!< LCD PAL233: G14_0 Mask              */
+#define LCD_PAL233_B14_0_Pos                                  26                                                        /*!< LCD PAL233: B14_0 Position          */
+#define LCD_PAL233_B14_0_Msk                                  (0x1fUL << LCD_PAL233_B14_0_Pos)                          /*!< LCD PAL233: B14_0 Mask              */
+#define LCD_PAL233_I1_Pos                                     31                                                        /*!< LCD PAL233: I1 Position             */
+#define LCD_PAL233_I1_Msk                                     (0x01UL << LCD_PAL233_I1_Pos)                             /*!< LCD PAL233: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL234  -------------------------------------------
+#define LCD_PAL234_R04_0_Pos                                  0                                                         /*!< LCD PAL234: R04_0 Position          */
+#define LCD_PAL234_R04_0_Msk                                  (0x1fUL << LCD_PAL234_R04_0_Pos)                          /*!< LCD PAL234: R04_0 Mask              */
+#define LCD_PAL234_G04_0_Pos                                  5                                                         /*!< LCD PAL234: G04_0 Position          */
+#define LCD_PAL234_G04_0_Msk                                  (0x1fUL << LCD_PAL234_G04_0_Pos)                          /*!< LCD PAL234: G04_0 Mask              */
+#define LCD_PAL234_B04_0_Pos                                  10                                                        /*!< LCD PAL234: B04_0 Position          */
+#define LCD_PAL234_B04_0_Msk                                  (0x1fUL << LCD_PAL234_B04_0_Pos)                          /*!< LCD PAL234: B04_0 Mask              */
+#define LCD_PAL234_I0_Pos                                     15                                                        /*!< LCD PAL234: I0 Position             */
+#define LCD_PAL234_I0_Msk                                     (0x01UL << LCD_PAL234_I0_Pos)                             /*!< LCD PAL234: I0 Mask                 */
+#define LCD_PAL234_R14_0_Pos                                  16                                                        /*!< LCD PAL234: R14_0 Position          */
+#define LCD_PAL234_R14_0_Msk                                  (0x1fUL << LCD_PAL234_R14_0_Pos)                          /*!< LCD PAL234: R14_0 Mask              */
+#define LCD_PAL234_G14_0_Pos                                  21                                                        /*!< LCD PAL234: G14_0 Position          */
+#define LCD_PAL234_G14_0_Msk                                  (0x1fUL << LCD_PAL234_G14_0_Pos)                          /*!< LCD PAL234: G14_0 Mask              */
+#define LCD_PAL234_B14_0_Pos                                  26                                                        /*!< LCD PAL234: B14_0 Position          */
+#define LCD_PAL234_B14_0_Msk                                  (0x1fUL << LCD_PAL234_B14_0_Pos)                          /*!< LCD PAL234: B14_0 Mask              */
+#define LCD_PAL234_I1_Pos                                     31                                                        /*!< LCD PAL234: I1 Position             */
+#define LCD_PAL234_I1_Msk                                     (0x01UL << LCD_PAL234_I1_Pos)                             /*!< LCD PAL234: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL235  -------------------------------------------
+#define LCD_PAL235_R04_0_Pos                                  0                                                         /*!< LCD PAL235: R04_0 Position          */
+#define LCD_PAL235_R04_0_Msk                                  (0x1fUL << LCD_PAL235_R04_0_Pos)                          /*!< LCD PAL235: R04_0 Mask              */
+#define LCD_PAL235_G04_0_Pos                                  5                                                         /*!< LCD PAL235: G04_0 Position          */
+#define LCD_PAL235_G04_0_Msk                                  (0x1fUL << LCD_PAL235_G04_0_Pos)                          /*!< LCD PAL235: G04_0 Mask              */
+#define LCD_PAL235_B04_0_Pos                                  10                                                        /*!< LCD PAL235: B04_0 Position          */
+#define LCD_PAL235_B04_0_Msk                                  (0x1fUL << LCD_PAL235_B04_0_Pos)                          /*!< LCD PAL235: B04_0 Mask              */
+#define LCD_PAL235_I0_Pos                                     15                                                        /*!< LCD PAL235: I0 Position             */
+#define LCD_PAL235_I0_Msk                                     (0x01UL << LCD_PAL235_I0_Pos)                             /*!< LCD PAL235: I0 Mask                 */
+#define LCD_PAL235_R14_0_Pos                                  16                                                        /*!< LCD PAL235: R14_0 Position          */
+#define LCD_PAL235_R14_0_Msk                                  (0x1fUL << LCD_PAL235_R14_0_Pos)                          /*!< LCD PAL235: R14_0 Mask              */
+#define LCD_PAL235_G14_0_Pos                                  21                                                        /*!< LCD PAL235: G14_0 Position          */
+#define LCD_PAL235_G14_0_Msk                                  (0x1fUL << LCD_PAL235_G14_0_Pos)                          /*!< LCD PAL235: G14_0 Mask              */
+#define LCD_PAL235_B14_0_Pos                                  26                                                        /*!< LCD PAL235: B14_0 Position          */
+#define LCD_PAL235_B14_0_Msk                                  (0x1fUL << LCD_PAL235_B14_0_Pos)                          /*!< LCD PAL235: B14_0 Mask              */
+#define LCD_PAL235_I1_Pos                                     31                                                        /*!< LCD PAL235: I1 Position             */
+#define LCD_PAL235_I1_Msk                                     (0x01UL << LCD_PAL235_I1_Pos)                             /*!< LCD PAL235: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL236  -------------------------------------------
+#define LCD_PAL236_R04_0_Pos                                  0                                                         /*!< LCD PAL236: R04_0 Position          */
+#define LCD_PAL236_R04_0_Msk                                  (0x1fUL << LCD_PAL236_R04_0_Pos)                          /*!< LCD PAL236: R04_0 Mask              */
+#define LCD_PAL236_G04_0_Pos                                  5                                                         /*!< LCD PAL236: G04_0 Position          */
+#define LCD_PAL236_G04_0_Msk                                  (0x1fUL << LCD_PAL236_G04_0_Pos)                          /*!< LCD PAL236: G04_0 Mask              */
+#define LCD_PAL236_B04_0_Pos                                  10                                                        /*!< LCD PAL236: B04_0 Position          */
+#define LCD_PAL236_B04_0_Msk                                  (0x1fUL << LCD_PAL236_B04_0_Pos)                          /*!< LCD PAL236: B04_0 Mask              */
+#define LCD_PAL236_I0_Pos                                     15                                                        /*!< LCD PAL236: I0 Position             */
+#define LCD_PAL236_I0_Msk                                     (0x01UL << LCD_PAL236_I0_Pos)                             /*!< LCD PAL236: I0 Mask                 */
+#define LCD_PAL236_R14_0_Pos                                  16                                                        /*!< LCD PAL236: R14_0 Position          */
+#define LCD_PAL236_R14_0_Msk                                  (0x1fUL << LCD_PAL236_R14_0_Pos)                          /*!< LCD PAL236: R14_0 Mask              */
+#define LCD_PAL236_G14_0_Pos                                  21                                                        /*!< LCD PAL236: G14_0 Position          */
+#define LCD_PAL236_G14_0_Msk                                  (0x1fUL << LCD_PAL236_G14_0_Pos)                          /*!< LCD PAL236: G14_0 Mask              */
+#define LCD_PAL236_B14_0_Pos                                  26                                                        /*!< LCD PAL236: B14_0 Position          */
+#define LCD_PAL236_B14_0_Msk                                  (0x1fUL << LCD_PAL236_B14_0_Pos)                          /*!< LCD PAL236: B14_0 Mask              */
+#define LCD_PAL236_I1_Pos                                     31                                                        /*!< LCD PAL236: I1 Position             */
+#define LCD_PAL236_I1_Msk                                     (0x01UL << LCD_PAL236_I1_Pos)                             /*!< LCD PAL236: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL237  -------------------------------------------
+#define LCD_PAL237_R04_0_Pos                                  0                                                         /*!< LCD PAL237: R04_0 Position          */
+#define LCD_PAL237_R04_0_Msk                                  (0x1fUL << LCD_PAL237_R04_0_Pos)                          /*!< LCD PAL237: R04_0 Mask              */
+#define LCD_PAL237_G04_0_Pos                                  5                                                         /*!< LCD PAL237: G04_0 Position          */
+#define LCD_PAL237_G04_0_Msk                                  (0x1fUL << LCD_PAL237_G04_0_Pos)                          /*!< LCD PAL237: G04_0 Mask              */
+#define LCD_PAL237_B04_0_Pos                                  10                                                        /*!< LCD PAL237: B04_0 Position          */
+#define LCD_PAL237_B04_0_Msk                                  (0x1fUL << LCD_PAL237_B04_0_Pos)                          /*!< LCD PAL237: B04_0 Mask              */
+#define LCD_PAL237_I0_Pos                                     15                                                        /*!< LCD PAL237: I0 Position             */
+#define LCD_PAL237_I0_Msk                                     (0x01UL << LCD_PAL237_I0_Pos)                             /*!< LCD PAL237: I0 Mask                 */
+#define LCD_PAL237_R14_0_Pos                                  16                                                        /*!< LCD PAL237: R14_0 Position          */
+#define LCD_PAL237_R14_0_Msk                                  (0x1fUL << LCD_PAL237_R14_0_Pos)                          /*!< LCD PAL237: R14_0 Mask              */
+#define LCD_PAL237_G14_0_Pos                                  21                                                        /*!< LCD PAL237: G14_0 Position          */
+#define LCD_PAL237_G14_0_Msk                                  (0x1fUL << LCD_PAL237_G14_0_Pos)                          /*!< LCD PAL237: G14_0 Mask              */
+#define LCD_PAL237_B14_0_Pos                                  26                                                        /*!< LCD PAL237: B14_0 Position          */
+#define LCD_PAL237_B14_0_Msk                                  (0x1fUL << LCD_PAL237_B14_0_Pos)                          /*!< LCD PAL237: B14_0 Mask              */
+#define LCD_PAL237_I1_Pos                                     31                                                        /*!< LCD PAL237: I1 Position             */
+#define LCD_PAL237_I1_Msk                                     (0x01UL << LCD_PAL237_I1_Pos)                             /*!< LCD PAL237: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL238  -------------------------------------------
+#define LCD_PAL238_R04_0_Pos                                  0                                                         /*!< LCD PAL238: R04_0 Position          */
+#define LCD_PAL238_R04_0_Msk                                  (0x1fUL << LCD_PAL238_R04_0_Pos)                          /*!< LCD PAL238: R04_0 Mask              */
+#define LCD_PAL238_G04_0_Pos                                  5                                                         /*!< LCD PAL238: G04_0 Position          */
+#define LCD_PAL238_G04_0_Msk                                  (0x1fUL << LCD_PAL238_G04_0_Pos)                          /*!< LCD PAL238: G04_0 Mask              */
+#define LCD_PAL238_B04_0_Pos                                  10                                                        /*!< LCD PAL238: B04_0 Position          */
+#define LCD_PAL238_B04_0_Msk                                  (0x1fUL << LCD_PAL238_B04_0_Pos)                          /*!< LCD PAL238: B04_0 Mask              */
+#define LCD_PAL238_I0_Pos                                     15                                                        /*!< LCD PAL238: I0 Position             */
+#define LCD_PAL238_I0_Msk                                     (0x01UL << LCD_PAL238_I0_Pos)                             /*!< LCD PAL238: I0 Mask                 */
+#define LCD_PAL238_R14_0_Pos                                  16                                                        /*!< LCD PAL238: R14_0 Position          */
+#define LCD_PAL238_R14_0_Msk                                  (0x1fUL << LCD_PAL238_R14_0_Pos)                          /*!< LCD PAL238: R14_0 Mask              */
+#define LCD_PAL238_G14_0_Pos                                  21                                                        /*!< LCD PAL238: G14_0 Position          */
+#define LCD_PAL238_G14_0_Msk                                  (0x1fUL << LCD_PAL238_G14_0_Pos)                          /*!< LCD PAL238: G14_0 Mask              */
+#define LCD_PAL238_B14_0_Pos                                  26                                                        /*!< LCD PAL238: B14_0 Position          */
+#define LCD_PAL238_B14_0_Msk                                  (0x1fUL << LCD_PAL238_B14_0_Pos)                          /*!< LCD PAL238: B14_0 Mask              */
+#define LCD_PAL238_I1_Pos                                     31                                                        /*!< LCD PAL238: I1 Position             */
+#define LCD_PAL238_I1_Msk                                     (0x01UL << LCD_PAL238_I1_Pos)                             /*!< LCD PAL238: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL239  -------------------------------------------
+#define LCD_PAL239_R04_0_Pos                                  0                                                         /*!< LCD PAL239: R04_0 Position          */
+#define LCD_PAL239_R04_0_Msk                                  (0x1fUL << LCD_PAL239_R04_0_Pos)                          /*!< LCD PAL239: R04_0 Mask              */
+#define LCD_PAL239_G04_0_Pos                                  5                                                         /*!< LCD PAL239: G04_0 Position          */
+#define LCD_PAL239_G04_0_Msk                                  (0x1fUL << LCD_PAL239_G04_0_Pos)                          /*!< LCD PAL239: G04_0 Mask              */
+#define LCD_PAL239_B04_0_Pos                                  10                                                        /*!< LCD PAL239: B04_0 Position          */
+#define LCD_PAL239_B04_0_Msk                                  (0x1fUL << LCD_PAL239_B04_0_Pos)                          /*!< LCD PAL239: B04_0 Mask              */
+#define LCD_PAL239_I0_Pos                                     15                                                        /*!< LCD PAL239: I0 Position             */
+#define LCD_PAL239_I0_Msk                                     (0x01UL << LCD_PAL239_I0_Pos)                             /*!< LCD PAL239: I0 Mask                 */
+#define LCD_PAL239_R14_0_Pos                                  16                                                        /*!< LCD PAL239: R14_0 Position          */
+#define LCD_PAL239_R14_0_Msk                                  (0x1fUL << LCD_PAL239_R14_0_Pos)                          /*!< LCD PAL239: R14_0 Mask              */
+#define LCD_PAL239_G14_0_Pos                                  21                                                        /*!< LCD PAL239: G14_0 Position          */
+#define LCD_PAL239_G14_0_Msk                                  (0x1fUL << LCD_PAL239_G14_0_Pos)                          /*!< LCD PAL239: G14_0 Mask              */
+#define LCD_PAL239_B14_0_Pos                                  26                                                        /*!< LCD PAL239: B14_0 Position          */
+#define LCD_PAL239_B14_0_Msk                                  (0x1fUL << LCD_PAL239_B14_0_Pos)                          /*!< LCD PAL239: B14_0 Mask              */
+#define LCD_PAL239_I1_Pos                                     31                                                        /*!< LCD PAL239: I1 Position             */
+#define LCD_PAL239_I1_Msk                                     (0x01UL << LCD_PAL239_I1_Pos)                             /*!< LCD PAL239: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL240  -------------------------------------------
+#define LCD_PAL240_R04_0_Pos                                  0                                                         /*!< LCD PAL240: R04_0 Position          */
+#define LCD_PAL240_R04_0_Msk                                  (0x1fUL << LCD_PAL240_R04_0_Pos)                          /*!< LCD PAL240: R04_0 Mask              */
+#define LCD_PAL240_G04_0_Pos                                  5                                                         /*!< LCD PAL240: G04_0 Position          */
+#define LCD_PAL240_G04_0_Msk                                  (0x1fUL << LCD_PAL240_G04_0_Pos)                          /*!< LCD PAL240: G04_0 Mask              */
+#define LCD_PAL240_B04_0_Pos                                  10                                                        /*!< LCD PAL240: B04_0 Position          */
+#define LCD_PAL240_B04_0_Msk                                  (0x1fUL << LCD_PAL240_B04_0_Pos)                          /*!< LCD PAL240: B04_0 Mask              */
+#define LCD_PAL240_I0_Pos                                     15                                                        /*!< LCD PAL240: I0 Position             */
+#define LCD_PAL240_I0_Msk                                     (0x01UL << LCD_PAL240_I0_Pos)                             /*!< LCD PAL240: I0 Mask                 */
+#define LCD_PAL240_R14_0_Pos                                  16                                                        /*!< LCD PAL240: R14_0 Position          */
+#define LCD_PAL240_R14_0_Msk                                  (0x1fUL << LCD_PAL240_R14_0_Pos)                          /*!< LCD PAL240: R14_0 Mask              */
+#define LCD_PAL240_G14_0_Pos                                  21                                                        /*!< LCD PAL240: G14_0 Position          */
+#define LCD_PAL240_G14_0_Msk                                  (0x1fUL << LCD_PAL240_G14_0_Pos)                          /*!< LCD PAL240: G14_0 Mask              */
+#define LCD_PAL240_B14_0_Pos                                  26                                                        /*!< LCD PAL240: B14_0 Position          */
+#define LCD_PAL240_B14_0_Msk                                  (0x1fUL << LCD_PAL240_B14_0_Pos)                          /*!< LCD PAL240: B14_0 Mask              */
+#define LCD_PAL240_I1_Pos                                     31                                                        /*!< LCD PAL240: I1 Position             */
+#define LCD_PAL240_I1_Msk                                     (0x01UL << LCD_PAL240_I1_Pos)                             /*!< LCD PAL240: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL241  -------------------------------------------
+#define LCD_PAL241_R04_0_Pos                                  0                                                         /*!< LCD PAL241: R04_0 Position          */
+#define LCD_PAL241_R04_0_Msk                                  (0x1fUL << LCD_PAL241_R04_0_Pos)                          /*!< LCD PAL241: R04_0 Mask              */
+#define LCD_PAL241_G04_0_Pos                                  5                                                         /*!< LCD PAL241: G04_0 Position          */
+#define LCD_PAL241_G04_0_Msk                                  (0x1fUL << LCD_PAL241_G04_0_Pos)                          /*!< LCD PAL241: G04_0 Mask              */
+#define LCD_PAL241_B04_0_Pos                                  10                                                        /*!< LCD PAL241: B04_0 Position          */
+#define LCD_PAL241_B04_0_Msk                                  (0x1fUL << LCD_PAL241_B04_0_Pos)                          /*!< LCD PAL241: B04_0 Mask              */
+#define LCD_PAL241_I0_Pos                                     15                                                        /*!< LCD PAL241: I0 Position             */
+#define LCD_PAL241_I0_Msk                                     (0x01UL << LCD_PAL241_I0_Pos)                             /*!< LCD PAL241: I0 Mask                 */
+#define LCD_PAL241_R14_0_Pos                                  16                                                        /*!< LCD PAL241: R14_0 Position          */
+#define LCD_PAL241_R14_0_Msk                                  (0x1fUL << LCD_PAL241_R14_0_Pos)                          /*!< LCD PAL241: R14_0 Mask              */
+#define LCD_PAL241_G14_0_Pos                                  21                                                        /*!< LCD PAL241: G14_0 Position          */
+#define LCD_PAL241_G14_0_Msk                                  (0x1fUL << LCD_PAL241_G14_0_Pos)                          /*!< LCD PAL241: G14_0 Mask              */
+#define LCD_PAL241_B14_0_Pos                                  26                                                        /*!< LCD PAL241: B14_0 Position          */
+#define LCD_PAL241_B14_0_Msk                                  (0x1fUL << LCD_PAL241_B14_0_Pos)                          /*!< LCD PAL241: B14_0 Mask              */
+#define LCD_PAL241_I1_Pos                                     31                                                        /*!< LCD PAL241: I1 Position             */
+#define LCD_PAL241_I1_Msk                                     (0x01UL << LCD_PAL241_I1_Pos)                             /*!< LCD PAL241: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL242  -------------------------------------------
+#define LCD_PAL242_R04_0_Pos                                  0                                                         /*!< LCD PAL242: R04_0 Position          */
+#define LCD_PAL242_R04_0_Msk                                  (0x1fUL << LCD_PAL242_R04_0_Pos)                          /*!< LCD PAL242: R04_0 Mask              */
+#define LCD_PAL242_G04_0_Pos                                  5                                                         /*!< LCD PAL242: G04_0 Position          */
+#define LCD_PAL242_G04_0_Msk                                  (0x1fUL << LCD_PAL242_G04_0_Pos)                          /*!< LCD PAL242: G04_0 Mask              */
+#define LCD_PAL242_B04_0_Pos                                  10                                                        /*!< LCD PAL242: B04_0 Position          */
+#define LCD_PAL242_B04_0_Msk                                  (0x1fUL << LCD_PAL242_B04_0_Pos)                          /*!< LCD PAL242: B04_0 Mask              */
+#define LCD_PAL242_I0_Pos                                     15                                                        /*!< LCD PAL242: I0 Position             */
+#define LCD_PAL242_I0_Msk                                     (0x01UL << LCD_PAL242_I0_Pos)                             /*!< LCD PAL242: I0 Mask                 */
+#define LCD_PAL242_R14_0_Pos                                  16                                                        /*!< LCD PAL242: R14_0 Position          */
+#define LCD_PAL242_R14_0_Msk                                  (0x1fUL << LCD_PAL242_R14_0_Pos)                          /*!< LCD PAL242: R14_0 Mask              */
+#define LCD_PAL242_G14_0_Pos                                  21                                                        /*!< LCD PAL242: G14_0 Position          */
+#define LCD_PAL242_G14_0_Msk                                  (0x1fUL << LCD_PAL242_G14_0_Pos)                          /*!< LCD PAL242: G14_0 Mask              */
+#define LCD_PAL242_B14_0_Pos                                  26                                                        /*!< LCD PAL242: B14_0 Position          */
+#define LCD_PAL242_B14_0_Msk                                  (0x1fUL << LCD_PAL242_B14_0_Pos)                          /*!< LCD PAL242: B14_0 Mask              */
+#define LCD_PAL242_I1_Pos                                     31                                                        /*!< LCD PAL242: I1 Position             */
+#define LCD_PAL242_I1_Msk                                     (0x01UL << LCD_PAL242_I1_Pos)                             /*!< LCD PAL242: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL243  -------------------------------------------
+#define LCD_PAL243_R04_0_Pos                                  0                                                         /*!< LCD PAL243: R04_0 Position          */
+#define LCD_PAL243_R04_0_Msk                                  (0x1fUL << LCD_PAL243_R04_0_Pos)                          /*!< LCD PAL243: R04_0 Mask              */
+#define LCD_PAL243_G04_0_Pos                                  5                                                         /*!< LCD PAL243: G04_0 Position          */
+#define LCD_PAL243_G04_0_Msk                                  (0x1fUL << LCD_PAL243_G04_0_Pos)                          /*!< LCD PAL243: G04_0 Mask              */
+#define LCD_PAL243_B04_0_Pos                                  10                                                        /*!< LCD PAL243: B04_0 Position          */
+#define LCD_PAL243_B04_0_Msk                                  (0x1fUL << LCD_PAL243_B04_0_Pos)                          /*!< LCD PAL243: B04_0 Mask              */
+#define LCD_PAL243_I0_Pos                                     15                                                        /*!< LCD PAL243: I0 Position             */
+#define LCD_PAL243_I0_Msk                                     (0x01UL << LCD_PAL243_I0_Pos)                             /*!< LCD PAL243: I0 Mask                 */
+#define LCD_PAL243_R14_0_Pos                                  16                                                        /*!< LCD PAL243: R14_0 Position          */
+#define LCD_PAL243_R14_0_Msk                                  (0x1fUL << LCD_PAL243_R14_0_Pos)                          /*!< LCD PAL243: R14_0 Mask              */
+#define LCD_PAL243_G14_0_Pos                                  21                                                        /*!< LCD PAL243: G14_0 Position          */
+#define LCD_PAL243_G14_0_Msk                                  (0x1fUL << LCD_PAL243_G14_0_Pos)                          /*!< LCD PAL243: G14_0 Mask              */
+#define LCD_PAL243_B14_0_Pos                                  26                                                        /*!< LCD PAL243: B14_0 Position          */
+#define LCD_PAL243_B14_0_Msk                                  (0x1fUL << LCD_PAL243_B14_0_Pos)                          /*!< LCD PAL243: B14_0 Mask              */
+#define LCD_PAL243_I1_Pos                                     31                                                        /*!< LCD PAL243: I1 Position             */
+#define LCD_PAL243_I1_Msk                                     (0x01UL << LCD_PAL243_I1_Pos)                             /*!< LCD PAL243: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL244  -------------------------------------------
+#define LCD_PAL244_R04_0_Pos                                  0                                                         /*!< LCD PAL244: R04_0 Position          */
+#define LCD_PAL244_R04_0_Msk                                  (0x1fUL << LCD_PAL244_R04_0_Pos)                          /*!< LCD PAL244: R04_0 Mask              */
+#define LCD_PAL244_G04_0_Pos                                  5                                                         /*!< LCD PAL244: G04_0 Position          */
+#define LCD_PAL244_G04_0_Msk                                  (0x1fUL << LCD_PAL244_G04_0_Pos)                          /*!< LCD PAL244: G04_0 Mask              */
+#define LCD_PAL244_B04_0_Pos                                  10                                                        /*!< LCD PAL244: B04_0 Position          */
+#define LCD_PAL244_B04_0_Msk                                  (0x1fUL << LCD_PAL244_B04_0_Pos)                          /*!< LCD PAL244: B04_0 Mask              */
+#define LCD_PAL244_I0_Pos                                     15                                                        /*!< LCD PAL244: I0 Position             */
+#define LCD_PAL244_I0_Msk                                     (0x01UL << LCD_PAL244_I0_Pos)                             /*!< LCD PAL244: I0 Mask                 */
+#define LCD_PAL244_R14_0_Pos                                  16                                                        /*!< LCD PAL244: R14_0 Position          */
+#define LCD_PAL244_R14_0_Msk                                  (0x1fUL << LCD_PAL244_R14_0_Pos)                          /*!< LCD PAL244: R14_0 Mask              */
+#define LCD_PAL244_G14_0_Pos                                  21                                                        /*!< LCD PAL244: G14_0 Position          */
+#define LCD_PAL244_G14_0_Msk                                  (0x1fUL << LCD_PAL244_G14_0_Pos)                          /*!< LCD PAL244: G14_0 Mask              */
+#define LCD_PAL244_B14_0_Pos                                  26                                                        /*!< LCD PAL244: B14_0 Position          */
+#define LCD_PAL244_B14_0_Msk                                  (0x1fUL << LCD_PAL244_B14_0_Pos)                          /*!< LCD PAL244: B14_0 Mask              */
+#define LCD_PAL244_I1_Pos                                     31                                                        /*!< LCD PAL244: I1 Position             */
+#define LCD_PAL244_I1_Msk                                     (0x01UL << LCD_PAL244_I1_Pos)                             /*!< LCD PAL244: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL245  -------------------------------------------
+#define LCD_PAL245_R04_0_Pos                                  0                                                         /*!< LCD PAL245: R04_0 Position          */
+#define LCD_PAL245_R04_0_Msk                                  (0x1fUL << LCD_PAL245_R04_0_Pos)                          /*!< LCD PAL245: R04_0 Mask              */
+#define LCD_PAL245_G04_0_Pos                                  5                                                         /*!< LCD PAL245: G04_0 Position          */
+#define LCD_PAL245_G04_0_Msk                                  (0x1fUL << LCD_PAL245_G04_0_Pos)                          /*!< LCD PAL245: G04_0 Mask              */
+#define LCD_PAL245_B04_0_Pos                                  10                                                        /*!< LCD PAL245: B04_0 Position          */
+#define LCD_PAL245_B04_0_Msk                                  (0x1fUL << LCD_PAL245_B04_0_Pos)                          /*!< LCD PAL245: B04_0 Mask              */
+#define LCD_PAL245_I0_Pos                                     15                                                        /*!< LCD PAL245: I0 Position             */
+#define LCD_PAL245_I0_Msk                                     (0x01UL << LCD_PAL245_I0_Pos)                             /*!< LCD PAL245: I0 Mask                 */
+#define LCD_PAL245_R14_0_Pos                                  16                                                        /*!< LCD PAL245: R14_0 Position          */
+#define LCD_PAL245_R14_0_Msk                                  (0x1fUL << LCD_PAL245_R14_0_Pos)                          /*!< LCD PAL245: R14_0 Mask              */
+#define LCD_PAL245_G14_0_Pos                                  21                                                        /*!< LCD PAL245: G14_0 Position          */
+#define LCD_PAL245_G14_0_Msk                                  (0x1fUL << LCD_PAL245_G14_0_Pos)                          /*!< LCD PAL245: G14_0 Mask              */
+#define LCD_PAL245_B14_0_Pos                                  26                                                        /*!< LCD PAL245: B14_0 Position          */
+#define LCD_PAL245_B14_0_Msk                                  (0x1fUL << LCD_PAL245_B14_0_Pos)                          /*!< LCD PAL245: B14_0 Mask              */
+#define LCD_PAL245_I1_Pos                                     31                                                        /*!< LCD PAL245: I1 Position             */
+#define LCD_PAL245_I1_Msk                                     (0x01UL << LCD_PAL245_I1_Pos)                             /*!< LCD PAL245: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL246  -------------------------------------------
+#define LCD_PAL246_R04_0_Pos                                  0                                                         /*!< LCD PAL246: R04_0 Position          */
+#define LCD_PAL246_R04_0_Msk                                  (0x1fUL << LCD_PAL246_R04_0_Pos)                          /*!< LCD PAL246: R04_0 Mask              */
+#define LCD_PAL246_G04_0_Pos                                  5                                                         /*!< LCD PAL246: G04_0 Position          */
+#define LCD_PAL246_G04_0_Msk                                  (0x1fUL << LCD_PAL246_G04_0_Pos)                          /*!< LCD PAL246: G04_0 Mask              */
+#define LCD_PAL246_B04_0_Pos                                  10                                                        /*!< LCD PAL246: B04_0 Position          */
+#define LCD_PAL246_B04_0_Msk                                  (0x1fUL << LCD_PAL246_B04_0_Pos)                          /*!< LCD PAL246: B04_0 Mask              */
+#define LCD_PAL246_I0_Pos                                     15                                                        /*!< LCD PAL246: I0 Position             */
+#define LCD_PAL246_I0_Msk                                     (0x01UL << LCD_PAL246_I0_Pos)                             /*!< LCD PAL246: I0 Mask                 */
+#define LCD_PAL246_R14_0_Pos                                  16                                                        /*!< LCD PAL246: R14_0 Position          */
+#define LCD_PAL246_R14_0_Msk                                  (0x1fUL << LCD_PAL246_R14_0_Pos)                          /*!< LCD PAL246: R14_0 Mask              */
+#define LCD_PAL246_G14_0_Pos                                  21                                                        /*!< LCD PAL246: G14_0 Position          */
+#define LCD_PAL246_G14_0_Msk                                  (0x1fUL << LCD_PAL246_G14_0_Pos)                          /*!< LCD PAL246: G14_0 Mask              */
+#define LCD_PAL246_B14_0_Pos                                  26                                                        /*!< LCD PAL246: B14_0 Position          */
+#define LCD_PAL246_B14_0_Msk                                  (0x1fUL << LCD_PAL246_B14_0_Pos)                          /*!< LCD PAL246: B14_0 Mask              */
+#define LCD_PAL246_I1_Pos                                     31                                                        /*!< LCD PAL246: I1 Position             */
+#define LCD_PAL246_I1_Msk                                     (0x01UL << LCD_PAL246_I1_Pos)                             /*!< LCD PAL246: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL247  -------------------------------------------
+#define LCD_PAL247_R04_0_Pos                                  0                                                         /*!< LCD PAL247: R04_0 Position          */
+#define LCD_PAL247_R04_0_Msk                                  (0x1fUL << LCD_PAL247_R04_0_Pos)                          /*!< LCD PAL247: R04_0 Mask              */
+#define LCD_PAL247_G04_0_Pos                                  5                                                         /*!< LCD PAL247: G04_0 Position          */
+#define LCD_PAL247_G04_0_Msk                                  (0x1fUL << LCD_PAL247_G04_0_Pos)                          /*!< LCD PAL247: G04_0 Mask              */
+#define LCD_PAL247_B04_0_Pos                                  10                                                        /*!< LCD PAL247: B04_0 Position          */
+#define LCD_PAL247_B04_0_Msk                                  (0x1fUL << LCD_PAL247_B04_0_Pos)                          /*!< LCD PAL247: B04_0 Mask              */
+#define LCD_PAL247_I0_Pos                                     15                                                        /*!< LCD PAL247: I0 Position             */
+#define LCD_PAL247_I0_Msk                                     (0x01UL << LCD_PAL247_I0_Pos)                             /*!< LCD PAL247: I0 Mask                 */
+#define LCD_PAL247_R14_0_Pos                                  16                                                        /*!< LCD PAL247: R14_0 Position          */
+#define LCD_PAL247_R14_0_Msk                                  (0x1fUL << LCD_PAL247_R14_0_Pos)                          /*!< LCD PAL247: R14_0 Mask              */
+#define LCD_PAL247_G14_0_Pos                                  21                                                        /*!< LCD PAL247: G14_0 Position          */
+#define LCD_PAL247_G14_0_Msk                                  (0x1fUL << LCD_PAL247_G14_0_Pos)                          /*!< LCD PAL247: G14_0 Mask              */
+#define LCD_PAL247_B14_0_Pos                                  26                                                        /*!< LCD PAL247: B14_0 Position          */
+#define LCD_PAL247_B14_0_Msk                                  (0x1fUL << LCD_PAL247_B14_0_Pos)                          /*!< LCD PAL247: B14_0 Mask              */
+#define LCD_PAL247_I1_Pos                                     31                                                        /*!< LCD PAL247: I1 Position             */
+#define LCD_PAL247_I1_Msk                                     (0x01UL << LCD_PAL247_I1_Pos)                             /*!< LCD PAL247: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL248  -------------------------------------------
+#define LCD_PAL248_R04_0_Pos                                  0                                                         /*!< LCD PAL248: R04_0 Position          */
+#define LCD_PAL248_R04_0_Msk                                  (0x1fUL << LCD_PAL248_R04_0_Pos)                          /*!< LCD PAL248: R04_0 Mask              */
+#define LCD_PAL248_G04_0_Pos                                  5                                                         /*!< LCD PAL248: G04_0 Position          */
+#define LCD_PAL248_G04_0_Msk                                  (0x1fUL << LCD_PAL248_G04_0_Pos)                          /*!< LCD PAL248: G04_0 Mask              */
+#define LCD_PAL248_B04_0_Pos                                  10                                                        /*!< LCD PAL248: B04_0 Position          */
+#define LCD_PAL248_B04_0_Msk                                  (0x1fUL << LCD_PAL248_B04_0_Pos)                          /*!< LCD PAL248: B04_0 Mask              */
+#define LCD_PAL248_I0_Pos                                     15                                                        /*!< LCD PAL248: I0 Position             */
+#define LCD_PAL248_I0_Msk                                     (0x01UL << LCD_PAL248_I0_Pos)                             /*!< LCD PAL248: I0 Mask                 */
+#define LCD_PAL248_R14_0_Pos                                  16                                                        /*!< LCD PAL248: R14_0 Position          */
+#define LCD_PAL248_R14_0_Msk                                  (0x1fUL << LCD_PAL248_R14_0_Pos)                          /*!< LCD PAL248: R14_0 Mask              */
+#define LCD_PAL248_G14_0_Pos                                  21                                                        /*!< LCD PAL248: G14_0 Position          */
+#define LCD_PAL248_G14_0_Msk                                  (0x1fUL << LCD_PAL248_G14_0_Pos)                          /*!< LCD PAL248: G14_0 Mask              */
+#define LCD_PAL248_B14_0_Pos                                  26                                                        /*!< LCD PAL248: B14_0 Position          */
+#define LCD_PAL248_B14_0_Msk                                  (0x1fUL << LCD_PAL248_B14_0_Pos)                          /*!< LCD PAL248: B14_0 Mask              */
+#define LCD_PAL248_I1_Pos                                     31                                                        /*!< LCD PAL248: I1 Position             */
+#define LCD_PAL248_I1_Msk                                     (0x01UL << LCD_PAL248_I1_Pos)                             /*!< LCD PAL248: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL249  -------------------------------------------
+#define LCD_PAL249_R04_0_Pos                                  0                                                         /*!< LCD PAL249: R04_0 Position          */
+#define LCD_PAL249_R04_0_Msk                                  (0x1fUL << LCD_PAL249_R04_0_Pos)                          /*!< LCD PAL249: R04_0 Mask              */
+#define LCD_PAL249_G04_0_Pos                                  5                                                         /*!< LCD PAL249: G04_0 Position          */
+#define LCD_PAL249_G04_0_Msk                                  (0x1fUL << LCD_PAL249_G04_0_Pos)                          /*!< LCD PAL249: G04_0 Mask              */
+#define LCD_PAL249_B04_0_Pos                                  10                                                        /*!< LCD PAL249: B04_0 Position          */
+#define LCD_PAL249_B04_0_Msk                                  (0x1fUL << LCD_PAL249_B04_0_Pos)                          /*!< LCD PAL249: B04_0 Mask              */
+#define LCD_PAL249_I0_Pos                                     15                                                        /*!< LCD PAL249: I0 Position             */
+#define LCD_PAL249_I0_Msk                                     (0x01UL << LCD_PAL249_I0_Pos)                             /*!< LCD PAL249: I0 Mask                 */
+#define LCD_PAL249_R14_0_Pos                                  16                                                        /*!< LCD PAL249: R14_0 Position          */
+#define LCD_PAL249_R14_0_Msk                                  (0x1fUL << LCD_PAL249_R14_0_Pos)                          /*!< LCD PAL249: R14_0 Mask              */
+#define LCD_PAL249_G14_0_Pos                                  21                                                        /*!< LCD PAL249: G14_0 Position          */
+#define LCD_PAL249_G14_0_Msk                                  (0x1fUL << LCD_PAL249_G14_0_Pos)                          /*!< LCD PAL249: G14_0 Mask              */
+#define LCD_PAL249_B14_0_Pos                                  26                                                        /*!< LCD PAL249: B14_0 Position          */
+#define LCD_PAL249_B14_0_Msk                                  (0x1fUL << LCD_PAL249_B14_0_Pos)                          /*!< LCD PAL249: B14_0 Mask              */
+#define LCD_PAL249_I1_Pos                                     31                                                        /*!< LCD PAL249: I1 Position             */
+#define LCD_PAL249_I1_Msk                                     (0x01UL << LCD_PAL249_I1_Pos)                             /*!< LCD PAL249: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL250  -------------------------------------------
+#define LCD_PAL250_R04_0_Pos                                  0                                                         /*!< LCD PAL250: R04_0 Position          */
+#define LCD_PAL250_R04_0_Msk                                  (0x1fUL << LCD_PAL250_R04_0_Pos)                          /*!< LCD PAL250: R04_0 Mask              */
+#define LCD_PAL250_G04_0_Pos                                  5                                                         /*!< LCD PAL250: G04_0 Position          */
+#define LCD_PAL250_G04_0_Msk                                  (0x1fUL << LCD_PAL250_G04_0_Pos)                          /*!< LCD PAL250: G04_0 Mask              */
+#define LCD_PAL250_B04_0_Pos                                  10                                                        /*!< LCD PAL250: B04_0 Position          */
+#define LCD_PAL250_B04_0_Msk                                  (0x1fUL << LCD_PAL250_B04_0_Pos)                          /*!< LCD PAL250: B04_0 Mask              */
+#define LCD_PAL250_I0_Pos                                     15                                                        /*!< LCD PAL250: I0 Position             */
+#define LCD_PAL250_I0_Msk                                     (0x01UL << LCD_PAL250_I0_Pos)                             /*!< LCD PAL250: I0 Mask                 */
+#define LCD_PAL250_R14_0_Pos                                  16                                                        /*!< LCD PAL250: R14_0 Position          */
+#define LCD_PAL250_R14_0_Msk                                  (0x1fUL << LCD_PAL250_R14_0_Pos)                          /*!< LCD PAL250: R14_0 Mask              */
+#define LCD_PAL250_G14_0_Pos                                  21                                                        /*!< LCD PAL250: G14_0 Position          */
+#define LCD_PAL250_G14_0_Msk                                  (0x1fUL << LCD_PAL250_G14_0_Pos)                          /*!< LCD PAL250: G14_0 Mask              */
+#define LCD_PAL250_B14_0_Pos                                  26                                                        /*!< LCD PAL250: B14_0 Position          */
+#define LCD_PAL250_B14_0_Msk                                  (0x1fUL << LCD_PAL250_B14_0_Pos)                          /*!< LCD PAL250: B14_0 Mask              */
+#define LCD_PAL250_I1_Pos                                     31                                                        /*!< LCD PAL250: I1 Position             */
+#define LCD_PAL250_I1_Msk                                     (0x01UL << LCD_PAL250_I1_Pos)                             /*!< LCD PAL250: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL251  -------------------------------------------
+#define LCD_PAL251_R04_0_Pos                                  0                                                         /*!< LCD PAL251: R04_0 Position          */
+#define LCD_PAL251_R04_0_Msk                                  (0x1fUL << LCD_PAL251_R04_0_Pos)                          /*!< LCD PAL251: R04_0 Mask              */
+#define LCD_PAL251_G04_0_Pos                                  5                                                         /*!< LCD PAL251: G04_0 Position          */
+#define LCD_PAL251_G04_0_Msk                                  (0x1fUL << LCD_PAL251_G04_0_Pos)                          /*!< LCD PAL251: G04_0 Mask              */
+#define LCD_PAL251_B04_0_Pos                                  10                                                        /*!< LCD PAL251: B04_0 Position          */
+#define LCD_PAL251_B04_0_Msk                                  (0x1fUL << LCD_PAL251_B04_0_Pos)                          /*!< LCD PAL251: B04_0 Mask              */
+#define LCD_PAL251_I0_Pos                                     15                                                        /*!< LCD PAL251: I0 Position             */
+#define LCD_PAL251_I0_Msk                                     (0x01UL << LCD_PAL251_I0_Pos)                             /*!< LCD PAL251: I0 Mask                 */
+#define LCD_PAL251_R14_0_Pos                                  16                                                        /*!< LCD PAL251: R14_0 Position          */
+#define LCD_PAL251_R14_0_Msk                                  (0x1fUL << LCD_PAL251_R14_0_Pos)                          /*!< LCD PAL251: R14_0 Mask              */
+#define LCD_PAL251_G14_0_Pos                                  21                                                        /*!< LCD PAL251: G14_0 Position          */
+#define LCD_PAL251_G14_0_Msk                                  (0x1fUL << LCD_PAL251_G14_0_Pos)                          /*!< LCD PAL251: G14_0 Mask              */
+#define LCD_PAL251_B14_0_Pos                                  26                                                        /*!< LCD PAL251: B14_0 Position          */
+#define LCD_PAL251_B14_0_Msk                                  (0x1fUL << LCD_PAL251_B14_0_Pos)                          /*!< LCD PAL251: B14_0 Mask              */
+#define LCD_PAL251_I1_Pos                                     31                                                        /*!< LCD PAL251: I1 Position             */
+#define LCD_PAL251_I1_Msk                                     (0x01UL << LCD_PAL251_I1_Pos)                             /*!< LCD PAL251: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL252  -------------------------------------------
+#define LCD_PAL252_R04_0_Pos                                  0                                                         /*!< LCD PAL252: R04_0 Position          */
+#define LCD_PAL252_R04_0_Msk                                  (0x1fUL << LCD_PAL252_R04_0_Pos)                          /*!< LCD PAL252: R04_0 Mask              */
+#define LCD_PAL252_G04_0_Pos                                  5                                                         /*!< LCD PAL252: G04_0 Position          */
+#define LCD_PAL252_G04_0_Msk                                  (0x1fUL << LCD_PAL252_G04_0_Pos)                          /*!< LCD PAL252: G04_0 Mask              */
+#define LCD_PAL252_B04_0_Pos                                  10                                                        /*!< LCD PAL252: B04_0 Position          */
+#define LCD_PAL252_B04_0_Msk                                  (0x1fUL << LCD_PAL252_B04_0_Pos)                          /*!< LCD PAL252: B04_0 Mask              */
+#define LCD_PAL252_I0_Pos                                     15                                                        /*!< LCD PAL252: I0 Position             */
+#define LCD_PAL252_I0_Msk                                     (0x01UL << LCD_PAL252_I0_Pos)                             /*!< LCD PAL252: I0 Mask                 */
+#define LCD_PAL252_R14_0_Pos                                  16                                                        /*!< LCD PAL252: R14_0 Position          */
+#define LCD_PAL252_R14_0_Msk                                  (0x1fUL << LCD_PAL252_R14_0_Pos)                          /*!< LCD PAL252: R14_0 Mask              */
+#define LCD_PAL252_G14_0_Pos                                  21                                                        /*!< LCD PAL252: G14_0 Position          */
+#define LCD_PAL252_G14_0_Msk                                  (0x1fUL << LCD_PAL252_G14_0_Pos)                          /*!< LCD PAL252: G14_0 Mask              */
+#define LCD_PAL252_B14_0_Pos                                  26                                                        /*!< LCD PAL252: B14_0 Position          */
+#define LCD_PAL252_B14_0_Msk                                  (0x1fUL << LCD_PAL252_B14_0_Pos)                          /*!< LCD PAL252: B14_0 Mask              */
+#define LCD_PAL252_I1_Pos                                     31                                                        /*!< LCD PAL252: I1 Position             */
+#define LCD_PAL252_I1_Msk                                     (0x01UL << LCD_PAL252_I1_Pos)                             /*!< LCD PAL252: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL253  -------------------------------------------
+#define LCD_PAL253_R04_0_Pos                                  0                                                         /*!< LCD PAL253: R04_0 Position          */
+#define LCD_PAL253_R04_0_Msk                                  (0x1fUL << LCD_PAL253_R04_0_Pos)                          /*!< LCD PAL253: R04_0 Mask              */
+#define LCD_PAL253_G04_0_Pos                                  5                                                         /*!< LCD PAL253: G04_0 Position          */
+#define LCD_PAL253_G04_0_Msk                                  (0x1fUL << LCD_PAL253_G04_0_Pos)                          /*!< LCD PAL253: G04_0 Mask              */
+#define LCD_PAL253_B04_0_Pos                                  10                                                        /*!< LCD PAL253: B04_0 Position          */
+#define LCD_PAL253_B04_0_Msk                                  (0x1fUL << LCD_PAL253_B04_0_Pos)                          /*!< LCD PAL253: B04_0 Mask              */
+#define LCD_PAL253_I0_Pos                                     15                                                        /*!< LCD PAL253: I0 Position             */
+#define LCD_PAL253_I0_Msk                                     (0x01UL << LCD_PAL253_I0_Pos)                             /*!< LCD PAL253: I0 Mask                 */
+#define LCD_PAL253_R14_0_Pos                                  16                                                        /*!< LCD PAL253: R14_0 Position          */
+#define LCD_PAL253_R14_0_Msk                                  (0x1fUL << LCD_PAL253_R14_0_Pos)                          /*!< LCD PAL253: R14_0 Mask              */
+#define LCD_PAL253_G14_0_Pos                                  21                                                        /*!< LCD PAL253: G14_0 Position          */
+#define LCD_PAL253_G14_0_Msk                                  (0x1fUL << LCD_PAL253_G14_0_Pos)                          /*!< LCD PAL253: G14_0 Mask              */
+#define LCD_PAL253_B14_0_Pos                                  26                                                        /*!< LCD PAL253: B14_0 Position          */
+#define LCD_PAL253_B14_0_Msk                                  (0x1fUL << LCD_PAL253_B14_0_Pos)                          /*!< LCD PAL253: B14_0 Mask              */
+#define LCD_PAL253_I1_Pos                                     31                                                        /*!< LCD PAL253: I1 Position             */
+#define LCD_PAL253_I1_Msk                                     (0x01UL << LCD_PAL253_I1_Pos)                             /*!< LCD PAL253: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL254  -------------------------------------------
+#define LCD_PAL254_R04_0_Pos                                  0                                                         /*!< LCD PAL254: R04_0 Position          */
+#define LCD_PAL254_R04_0_Msk                                  (0x1fUL << LCD_PAL254_R04_0_Pos)                          /*!< LCD PAL254: R04_0 Mask              */
+#define LCD_PAL254_G04_0_Pos                                  5                                                         /*!< LCD PAL254: G04_0 Position          */
+#define LCD_PAL254_G04_0_Msk                                  (0x1fUL << LCD_PAL254_G04_0_Pos)                          /*!< LCD PAL254: G04_0 Mask              */
+#define LCD_PAL254_B04_0_Pos                                  10                                                        /*!< LCD PAL254: B04_0 Position          */
+#define LCD_PAL254_B04_0_Msk                                  (0x1fUL << LCD_PAL254_B04_0_Pos)                          /*!< LCD PAL254: B04_0 Mask              */
+#define LCD_PAL254_I0_Pos                                     15                                                        /*!< LCD PAL254: I0 Position             */
+#define LCD_PAL254_I0_Msk                                     (0x01UL << LCD_PAL254_I0_Pos)                             /*!< LCD PAL254: I0 Mask                 */
+#define LCD_PAL254_R14_0_Pos                                  16                                                        /*!< LCD PAL254: R14_0 Position          */
+#define LCD_PAL254_R14_0_Msk                                  (0x1fUL << LCD_PAL254_R14_0_Pos)                          /*!< LCD PAL254: R14_0 Mask              */
+#define LCD_PAL254_G14_0_Pos                                  21                                                        /*!< LCD PAL254: G14_0 Position          */
+#define LCD_PAL254_G14_0_Msk                                  (0x1fUL << LCD_PAL254_G14_0_Pos)                          /*!< LCD PAL254: G14_0 Mask              */
+#define LCD_PAL254_B14_0_Pos                                  26                                                        /*!< LCD PAL254: B14_0 Position          */
+#define LCD_PAL254_B14_0_Msk                                  (0x1fUL << LCD_PAL254_B14_0_Pos)                          /*!< LCD PAL254: B14_0 Mask              */
+#define LCD_PAL254_I1_Pos                                     31                                                        /*!< LCD PAL254: I1 Position             */
+#define LCD_PAL254_I1_Msk                                     (0x01UL << LCD_PAL254_I1_Pos)                             /*!< LCD PAL254: I1 Mask                 */
+
+// ---------------------------------------  LCD_PAL255  -------------------------------------------
+#define LCD_PAL255_R04_0_Pos                                  0                                                         /*!< LCD PAL255: R04_0 Position          */
+#define LCD_PAL255_R04_0_Msk                                  (0x1fUL << LCD_PAL255_R04_0_Pos)                          /*!< LCD PAL255: R04_0 Mask              */
+#define LCD_PAL255_G04_0_Pos                                  5                                                         /*!< LCD PAL255: G04_0 Position          */
+#define LCD_PAL255_G04_0_Msk                                  (0x1fUL << LCD_PAL255_G04_0_Pos)                          /*!< LCD PAL255: G04_0 Mask              */
+#define LCD_PAL255_B04_0_Pos                                  10                                                        /*!< LCD PAL255: B04_0 Position          */
+#define LCD_PAL255_B04_0_Msk                                  (0x1fUL << LCD_PAL255_B04_0_Pos)                          /*!< LCD PAL255: B04_0 Mask              */
+#define LCD_PAL255_I0_Pos                                     15                                                        /*!< LCD PAL255: I0 Position             */
+#define LCD_PAL255_I0_Msk                                     (0x01UL << LCD_PAL255_I0_Pos)                             /*!< LCD PAL255: I0 Mask                 */
+#define LCD_PAL255_R14_0_Pos                                  16                                                        /*!< LCD PAL255: R14_0 Position          */
+#define LCD_PAL255_R14_0_Msk                                  (0x1fUL << LCD_PAL255_R14_0_Pos)                          /*!< LCD PAL255: R14_0 Mask              */
+#define LCD_PAL255_G14_0_Pos                                  21                                                        /*!< LCD PAL255: G14_0 Position          */
+#define LCD_PAL255_G14_0_Msk                                  (0x1fUL << LCD_PAL255_G14_0_Pos)                          /*!< LCD PAL255: G14_0 Mask              */
+#define LCD_PAL255_B14_0_Pos                                  26                                                        /*!< LCD PAL255: B14_0 Position          */
+#define LCD_PAL255_B14_0_Msk                                  (0x1fUL << LCD_PAL255_B14_0_Pos)                          /*!< LCD PAL255: B14_0 Mask              */
+#define LCD_PAL255_I1_Pos                                     31                                                        /*!< LCD PAL255: I1 Position             */
+#define LCD_PAL255_I1_Msk                                     (0x01UL << LCD_PAL255_I1_Pos)                             /*!< LCD PAL255: I1 Mask                 */
+
+// --------------------------------------  LCD_CRSR_IMG0  -----------------------------------------
+#define LCD_CRSR_IMG0_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG0: CRSR_IMG Position    */
+#define LCD_CRSR_IMG0_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG0: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG1  -----------------------------------------
+#define LCD_CRSR_IMG1_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG1: CRSR_IMG Position    */
+#define LCD_CRSR_IMG1_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG1: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG2  -----------------------------------------
+#define LCD_CRSR_IMG2_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG2: CRSR_IMG Position    */
+#define LCD_CRSR_IMG2_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG2: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG3  -----------------------------------------
+#define LCD_CRSR_IMG3_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG3: CRSR_IMG Position    */
+#define LCD_CRSR_IMG3_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG3: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG4  -----------------------------------------
+#define LCD_CRSR_IMG4_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG4: CRSR_IMG Position    */
+#define LCD_CRSR_IMG4_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG4: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG5  -----------------------------------------
+#define LCD_CRSR_IMG5_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG5: CRSR_IMG Position    */
+#define LCD_CRSR_IMG5_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG5: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG6  -----------------------------------------
+#define LCD_CRSR_IMG6_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG6: CRSR_IMG Position    */
+#define LCD_CRSR_IMG6_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG6: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG7  -----------------------------------------
+#define LCD_CRSR_IMG7_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG7: CRSR_IMG Position    */
+#define LCD_CRSR_IMG7_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG7: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG8  -----------------------------------------
+#define LCD_CRSR_IMG8_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG8: CRSR_IMG Position    */
+#define LCD_CRSR_IMG8_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG8: CRSR_IMG Mask        */
+
+// --------------------------------------  LCD_CRSR_IMG9  -----------------------------------------
+#define LCD_CRSR_IMG9_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG9: CRSR_IMG Position    */
+#define LCD_CRSR_IMG9_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG9: CRSR_IMG Mask        */
+
+// -------------------------------------  LCD_CRSR_IMG10  -----------------------------------------
+#define LCD_CRSR_IMG10_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG10: CRSR_IMG Position   */
+#define LCD_CRSR_IMG10_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG10: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG11  -----------------------------------------
+#define LCD_CRSR_IMG11_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG11: CRSR_IMG Position   */
+#define LCD_CRSR_IMG11_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG11: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG12  -----------------------------------------
+#define LCD_CRSR_IMG12_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG12: CRSR_IMG Position   */
+#define LCD_CRSR_IMG12_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG12: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG13  -----------------------------------------
+#define LCD_CRSR_IMG13_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG13: CRSR_IMG Position   */
+#define LCD_CRSR_IMG13_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG13: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG14  -----------------------------------------
+#define LCD_CRSR_IMG14_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG14: CRSR_IMG Position   */
+#define LCD_CRSR_IMG14_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG14: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG15  -----------------------------------------
+#define LCD_CRSR_IMG15_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG15: CRSR_IMG Position   */
+#define LCD_CRSR_IMG15_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG15: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG16  -----------------------------------------
+#define LCD_CRSR_IMG16_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG16: CRSR_IMG Position   */
+#define LCD_CRSR_IMG16_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG16: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG17  -----------------------------------------
+#define LCD_CRSR_IMG17_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG17: CRSR_IMG Position   */
+#define LCD_CRSR_IMG17_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG17: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG18  -----------------------------------------
+#define LCD_CRSR_IMG18_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG18: CRSR_IMG Position   */
+#define LCD_CRSR_IMG18_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG18: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG19  -----------------------------------------
+#define LCD_CRSR_IMG19_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG19: CRSR_IMG Position   */
+#define LCD_CRSR_IMG19_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG19: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG20  -----------------------------------------
+#define LCD_CRSR_IMG20_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG20: CRSR_IMG Position   */
+#define LCD_CRSR_IMG20_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG20: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG21  -----------------------------------------
+#define LCD_CRSR_IMG21_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG21: CRSR_IMG Position   */
+#define LCD_CRSR_IMG21_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG21: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG22  -----------------------------------------
+#define LCD_CRSR_IMG22_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG22: CRSR_IMG Position   */
+#define LCD_CRSR_IMG22_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG22: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG23  -----------------------------------------
+#define LCD_CRSR_IMG23_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG23: CRSR_IMG Position   */
+#define LCD_CRSR_IMG23_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG23: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG24  -----------------------------------------
+#define LCD_CRSR_IMG24_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG24: CRSR_IMG Position   */
+#define LCD_CRSR_IMG24_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG24: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG25  -----------------------------------------
+#define LCD_CRSR_IMG25_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG25: CRSR_IMG Position   */
+#define LCD_CRSR_IMG25_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG25: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG26  -----------------------------------------
+#define LCD_CRSR_IMG26_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG26: CRSR_IMG Position   */
+#define LCD_CRSR_IMG26_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG26: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG27  -----------------------------------------
+#define LCD_CRSR_IMG27_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG27: CRSR_IMG Position   */
+#define LCD_CRSR_IMG27_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG27: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG28  -----------------------------------------
+#define LCD_CRSR_IMG28_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG28: CRSR_IMG Position   */
+#define LCD_CRSR_IMG28_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG28: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG29  -----------------------------------------
+#define LCD_CRSR_IMG29_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG29: CRSR_IMG Position   */
+#define LCD_CRSR_IMG29_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG29: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG30  -----------------------------------------
+#define LCD_CRSR_IMG30_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG30: CRSR_IMG Position   */
+#define LCD_CRSR_IMG30_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG30: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG31  -----------------------------------------
+#define LCD_CRSR_IMG31_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG31: CRSR_IMG Position   */
+#define LCD_CRSR_IMG31_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG31: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG32  -----------------------------------------
+#define LCD_CRSR_IMG32_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG32: CRSR_IMG Position   */
+#define LCD_CRSR_IMG32_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG32: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG33  -----------------------------------------
+#define LCD_CRSR_IMG33_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG33: CRSR_IMG Position   */
+#define LCD_CRSR_IMG33_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG33: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG34  -----------------------------------------
+#define LCD_CRSR_IMG34_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG34: CRSR_IMG Position   */
+#define LCD_CRSR_IMG34_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG34: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG35  -----------------------------------------
+#define LCD_CRSR_IMG35_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG35: CRSR_IMG Position   */
+#define LCD_CRSR_IMG35_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG35: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG36  -----------------------------------------
+#define LCD_CRSR_IMG36_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG36: CRSR_IMG Position   */
+#define LCD_CRSR_IMG36_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG36: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG37  -----------------------------------------
+#define LCD_CRSR_IMG37_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG37: CRSR_IMG Position   */
+#define LCD_CRSR_IMG37_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG37: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG38  -----------------------------------------
+#define LCD_CRSR_IMG38_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG38: CRSR_IMG Position   */
+#define LCD_CRSR_IMG38_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG38: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG39  -----------------------------------------
+#define LCD_CRSR_IMG39_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG39: CRSR_IMG Position   */
+#define LCD_CRSR_IMG39_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG39: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG40  -----------------------------------------
+#define LCD_CRSR_IMG40_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG40: CRSR_IMG Position   */
+#define LCD_CRSR_IMG40_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG40: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG41  -----------------------------------------
+#define LCD_CRSR_IMG41_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG41: CRSR_IMG Position   */
+#define LCD_CRSR_IMG41_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG41: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG42  -----------------------------------------
+#define LCD_CRSR_IMG42_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG42: CRSR_IMG Position   */
+#define LCD_CRSR_IMG42_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG42: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG43  -----------------------------------------
+#define LCD_CRSR_IMG43_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG43: CRSR_IMG Position   */
+#define LCD_CRSR_IMG43_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG43: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG44  -----------------------------------------
+#define LCD_CRSR_IMG44_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG44: CRSR_IMG Position   */
+#define LCD_CRSR_IMG44_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG44: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG45  -----------------------------------------
+#define LCD_CRSR_IMG45_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG45: CRSR_IMG Position   */
+#define LCD_CRSR_IMG45_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG45: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG46  -----------------------------------------
+#define LCD_CRSR_IMG46_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG46: CRSR_IMG Position   */
+#define LCD_CRSR_IMG46_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG46: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG47  -----------------------------------------
+#define LCD_CRSR_IMG47_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG47: CRSR_IMG Position   */
+#define LCD_CRSR_IMG47_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG47: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG48  -----------------------------------------
+#define LCD_CRSR_IMG48_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG48: CRSR_IMG Position   */
+#define LCD_CRSR_IMG48_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG48: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG49  -----------------------------------------
+#define LCD_CRSR_IMG49_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG49: CRSR_IMG Position   */
+#define LCD_CRSR_IMG49_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG49: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG50  -----------------------------------------
+#define LCD_CRSR_IMG50_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG50: CRSR_IMG Position   */
+#define LCD_CRSR_IMG50_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG50: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG51  -----------------------------------------
+#define LCD_CRSR_IMG51_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG51: CRSR_IMG Position   */
+#define LCD_CRSR_IMG51_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG51: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG52  -----------------------------------------
+#define LCD_CRSR_IMG52_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG52: CRSR_IMG Position   */
+#define LCD_CRSR_IMG52_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG52: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG53  -----------------------------------------
+#define LCD_CRSR_IMG53_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG53: CRSR_IMG Position   */
+#define LCD_CRSR_IMG53_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG53: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG54  -----------------------------------------
+#define LCD_CRSR_IMG54_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG54: CRSR_IMG Position   */
+#define LCD_CRSR_IMG54_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG54: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG55  -----------------------------------------
+#define LCD_CRSR_IMG55_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG55: CRSR_IMG Position   */
+#define LCD_CRSR_IMG55_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG55: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG56  -----------------------------------------
+#define LCD_CRSR_IMG56_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG56: CRSR_IMG Position   */
+#define LCD_CRSR_IMG56_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG56: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG57  -----------------------------------------
+#define LCD_CRSR_IMG57_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG57: CRSR_IMG Position   */
+#define LCD_CRSR_IMG57_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG57: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG58  -----------------------------------------
+#define LCD_CRSR_IMG58_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG58: CRSR_IMG Position   */
+#define LCD_CRSR_IMG58_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG58: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG59  -----------------------------------------
+#define LCD_CRSR_IMG59_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG59: CRSR_IMG Position   */
+#define LCD_CRSR_IMG59_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG59: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG60  -----------------------------------------
+#define LCD_CRSR_IMG60_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG60: CRSR_IMG Position   */
+#define LCD_CRSR_IMG60_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG60: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG61  -----------------------------------------
+#define LCD_CRSR_IMG61_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG61: CRSR_IMG Position   */
+#define LCD_CRSR_IMG61_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG61: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG62  -----------------------------------------
+#define LCD_CRSR_IMG62_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG62: CRSR_IMG Position   */
+#define LCD_CRSR_IMG62_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG62: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG63  -----------------------------------------
+#define LCD_CRSR_IMG63_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG63: CRSR_IMG Position   */
+#define LCD_CRSR_IMG63_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG63: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG64  -----------------------------------------
+#define LCD_CRSR_IMG64_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG64: CRSR_IMG Position   */
+#define LCD_CRSR_IMG64_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG64: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG65  -----------------------------------------
+#define LCD_CRSR_IMG65_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG65: CRSR_IMG Position   */
+#define LCD_CRSR_IMG65_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG65: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG66  -----------------------------------------
+#define LCD_CRSR_IMG66_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG66: CRSR_IMG Position   */
+#define LCD_CRSR_IMG66_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG66: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG67  -----------------------------------------
+#define LCD_CRSR_IMG67_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG67: CRSR_IMG Position   */
+#define LCD_CRSR_IMG67_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG67: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG68  -----------------------------------------
+#define LCD_CRSR_IMG68_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG68: CRSR_IMG Position   */
+#define LCD_CRSR_IMG68_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG68: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG69  -----------------------------------------
+#define LCD_CRSR_IMG69_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG69: CRSR_IMG Position   */
+#define LCD_CRSR_IMG69_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG69: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG70  -----------------------------------------
+#define LCD_CRSR_IMG70_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG70: CRSR_IMG Position   */
+#define LCD_CRSR_IMG70_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG70: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG71  -----------------------------------------
+#define LCD_CRSR_IMG71_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG71: CRSR_IMG Position   */
+#define LCD_CRSR_IMG71_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG71: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG72  -----------------------------------------
+#define LCD_CRSR_IMG72_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG72: CRSR_IMG Position   */
+#define LCD_CRSR_IMG72_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG72: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG73  -----------------------------------------
+#define LCD_CRSR_IMG73_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG73: CRSR_IMG Position   */
+#define LCD_CRSR_IMG73_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG73: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG74  -----------------------------------------
+#define LCD_CRSR_IMG74_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG74: CRSR_IMG Position   */
+#define LCD_CRSR_IMG74_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG74: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG75  -----------------------------------------
+#define LCD_CRSR_IMG75_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG75: CRSR_IMG Position   */
+#define LCD_CRSR_IMG75_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG75: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG76  -----------------------------------------
+#define LCD_CRSR_IMG76_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG76: CRSR_IMG Position   */
+#define LCD_CRSR_IMG76_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG76: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG77  -----------------------------------------
+#define LCD_CRSR_IMG77_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG77: CRSR_IMG Position   */
+#define LCD_CRSR_IMG77_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG77: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG78  -----------------------------------------
+#define LCD_CRSR_IMG78_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG78: CRSR_IMG Position   */
+#define LCD_CRSR_IMG78_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG78: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG79  -----------------------------------------
+#define LCD_CRSR_IMG79_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG79: CRSR_IMG Position   */
+#define LCD_CRSR_IMG79_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG79: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG80  -----------------------------------------
+#define LCD_CRSR_IMG80_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG80: CRSR_IMG Position   */
+#define LCD_CRSR_IMG80_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG80: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG81  -----------------------------------------
+#define LCD_CRSR_IMG81_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG81: CRSR_IMG Position   */
+#define LCD_CRSR_IMG81_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG81: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG82  -----------------------------------------
+#define LCD_CRSR_IMG82_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG82: CRSR_IMG Position   */
+#define LCD_CRSR_IMG82_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG82: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG83  -----------------------------------------
+#define LCD_CRSR_IMG83_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG83: CRSR_IMG Position   */
+#define LCD_CRSR_IMG83_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG83: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG84  -----------------------------------------
+#define LCD_CRSR_IMG84_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG84: CRSR_IMG Position   */
+#define LCD_CRSR_IMG84_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG84: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG85  -----------------------------------------
+#define LCD_CRSR_IMG85_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG85: CRSR_IMG Position   */
+#define LCD_CRSR_IMG85_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG85: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG86  -----------------------------------------
+#define LCD_CRSR_IMG86_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG86: CRSR_IMG Position   */
+#define LCD_CRSR_IMG86_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG86: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG87  -----------------------------------------
+#define LCD_CRSR_IMG87_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG87: CRSR_IMG Position   */
+#define LCD_CRSR_IMG87_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG87: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG88  -----------------------------------------
+#define LCD_CRSR_IMG88_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG88: CRSR_IMG Position   */
+#define LCD_CRSR_IMG88_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG88: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG89  -----------------------------------------
+#define LCD_CRSR_IMG89_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG89: CRSR_IMG Position   */
+#define LCD_CRSR_IMG89_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG89: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG90  -----------------------------------------
+#define LCD_CRSR_IMG90_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG90: CRSR_IMG Position   */
+#define LCD_CRSR_IMG90_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG90: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG91  -----------------------------------------
+#define LCD_CRSR_IMG91_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG91: CRSR_IMG Position   */
+#define LCD_CRSR_IMG91_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG91: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG92  -----------------------------------------
+#define LCD_CRSR_IMG92_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG92: CRSR_IMG Position   */
+#define LCD_CRSR_IMG92_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG92: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG93  -----------------------------------------
+#define LCD_CRSR_IMG93_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG93: CRSR_IMG Position   */
+#define LCD_CRSR_IMG93_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG93: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG94  -----------------------------------------
+#define LCD_CRSR_IMG94_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG94: CRSR_IMG Position   */
+#define LCD_CRSR_IMG94_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG94: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG95  -----------------------------------------
+#define LCD_CRSR_IMG95_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG95: CRSR_IMG Position   */
+#define LCD_CRSR_IMG95_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG95: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG96  -----------------------------------------
+#define LCD_CRSR_IMG96_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG96: CRSR_IMG Position   */
+#define LCD_CRSR_IMG96_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG96: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG97  -----------------------------------------
+#define LCD_CRSR_IMG97_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG97: CRSR_IMG Position   */
+#define LCD_CRSR_IMG97_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG97: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG98  -----------------------------------------
+#define LCD_CRSR_IMG98_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG98: CRSR_IMG Position   */
+#define LCD_CRSR_IMG98_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG98: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG99  -----------------------------------------
+#define LCD_CRSR_IMG99_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG99: CRSR_IMG Position   */
+#define LCD_CRSR_IMG99_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG99: CRSR_IMG Mask       */
+
+// -------------------------------------  LCD_CRSR_IMG100  ----------------------------------------
+#define LCD_CRSR_IMG100_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG100: CRSR_IMG Position  */
+#define LCD_CRSR_IMG100_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG100: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG101  ----------------------------------------
+#define LCD_CRSR_IMG101_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG101: CRSR_IMG Position  */
+#define LCD_CRSR_IMG101_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG101: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG102  ----------------------------------------
+#define LCD_CRSR_IMG102_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG102: CRSR_IMG Position  */
+#define LCD_CRSR_IMG102_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG102: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG103  ----------------------------------------
+#define LCD_CRSR_IMG103_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG103: CRSR_IMG Position  */
+#define LCD_CRSR_IMG103_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG103: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG104  ----------------------------------------
+#define LCD_CRSR_IMG104_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG104: CRSR_IMG Position  */
+#define LCD_CRSR_IMG104_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG104: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG105  ----------------------------------------
+#define LCD_CRSR_IMG105_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG105: CRSR_IMG Position  */
+#define LCD_CRSR_IMG105_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG105: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG106  ----------------------------------------
+#define LCD_CRSR_IMG106_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG106: CRSR_IMG Position  */
+#define LCD_CRSR_IMG106_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG106: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG107  ----------------------------------------
+#define LCD_CRSR_IMG107_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG107: CRSR_IMG Position  */
+#define LCD_CRSR_IMG107_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG107: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG108  ----------------------------------------
+#define LCD_CRSR_IMG108_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG108: CRSR_IMG Position  */
+#define LCD_CRSR_IMG108_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG108: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG109  ----------------------------------------
+#define LCD_CRSR_IMG109_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG109: CRSR_IMG Position  */
+#define LCD_CRSR_IMG109_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG109: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG110  ----------------------------------------
+#define LCD_CRSR_IMG110_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG110: CRSR_IMG Position  */
+#define LCD_CRSR_IMG110_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG110: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG111  ----------------------------------------
+#define LCD_CRSR_IMG111_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG111: CRSR_IMG Position  */
+#define LCD_CRSR_IMG111_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG111: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG112  ----------------------------------------
+#define LCD_CRSR_IMG112_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG112: CRSR_IMG Position  */
+#define LCD_CRSR_IMG112_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG112: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG113  ----------------------------------------
+#define LCD_CRSR_IMG113_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG113: CRSR_IMG Position  */
+#define LCD_CRSR_IMG113_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG113: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG114  ----------------------------------------
+#define LCD_CRSR_IMG114_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG114: CRSR_IMG Position  */
+#define LCD_CRSR_IMG114_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG114: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG115  ----------------------------------------
+#define LCD_CRSR_IMG115_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG115: CRSR_IMG Position  */
+#define LCD_CRSR_IMG115_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG115: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG116  ----------------------------------------
+#define LCD_CRSR_IMG116_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG116: CRSR_IMG Position  */
+#define LCD_CRSR_IMG116_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG116: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG117  ----------------------------------------
+#define LCD_CRSR_IMG117_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG117: CRSR_IMG Position  */
+#define LCD_CRSR_IMG117_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG117: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG118  ----------------------------------------
+#define LCD_CRSR_IMG118_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG118: CRSR_IMG Position  */
+#define LCD_CRSR_IMG118_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG118: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG119  ----------------------------------------
+#define LCD_CRSR_IMG119_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG119: CRSR_IMG Position  */
+#define LCD_CRSR_IMG119_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG119: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG120  ----------------------------------------
+#define LCD_CRSR_IMG120_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG120: CRSR_IMG Position  */
+#define LCD_CRSR_IMG120_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG120: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG121  ----------------------------------------
+#define LCD_CRSR_IMG121_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG121: CRSR_IMG Position  */
+#define LCD_CRSR_IMG121_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG121: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG122  ----------------------------------------
+#define LCD_CRSR_IMG122_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG122: CRSR_IMG Position  */
+#define LCD_CRSR_IMG122_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG122: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG123  ----------------------------------------
+#define LCD_CRSR_IMG123_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG123: CRSR_IMG Position  */
+#define LCD_CRSR_IMG123_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG123: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG124  ----------------------------------------
+#define LCD_CRSR_IMG124_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG124: CRSR_IMG Position  */
+#define LCD_CRSR_IMG124_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG124: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG125  ----------------------------------------
+#define LCD_CRSR_IMG125_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG125: CRSR_IMG Position  */
+#define LCD_CRSR_IMG125_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG125: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG126  ----------------------------------------
+#define LCD_CRSR_IMG126_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG126: CRSR_IMG Position  */
+#define LCD_CRSR_IMG126_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG126: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG127  ----------------------------------------
+#define LCD_CRSR_IMG127_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG127: CRSR_IMG Position  */
+#define LCD_CRSR_IMG127_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG127: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG128  ----------------------------------------
+#define LCD_CRSR_IMG128_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG128: CRSR_IMG Position  */
+#define LCD_CRSR_IMG128_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG128: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG129  ----------------------------------------
+#define LCD_CRSR_IMG129_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG129: CRSR_IMG Position  */
+#define LCD_CRSR_IMG129_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG129: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG130  ----------------------------------------
+#define LCD_CRSR_IMG130_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG130: CRSR_IMG Position  */
+#define LCD_CRSR_IMG130_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG130: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG131  ----------------------------------------
+#define LCD_CRSR_IMG131_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG131: CRSR_IMG Position  */
+#define LCD_CRSR_IMG131_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG131: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG132  ----------------------------------------
+#define LCD_CRSR_IMG132_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG132: CRSR_IMG Position  */
+#define LCD_CRSR_IMG132_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG132: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG133  ----------------------------------------
+#define LCD_CRSR_IMG133_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG133: CRSR_IMG Position  */
+#define LCD_CRSR_IMG133_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG133: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG134  ----------------------------------------
+#define LCD_CRSR_IMG134_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG134: CRSR_IMG Position  */
+#define LCD_CRSR_IMG134_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG134: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG135  ----------------------------------------
+#define LCD_CRSR_IMG135_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG135: CRSR_IMG Position  */
+#define LCD_CRSR_IMG135_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG135: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG136  ----------------------------------------
+#define LCD_CRSR_IMG136_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG136: CRSR_IMG Position  */
+#define LCD_CRSR_IMG136_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG136: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG137  ----------------------------------------
+#define LCD_CRSR_IMG137_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG137: CRSR_IMG Position  */
+#define LCD_CRSR_IMG137_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG137: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG138  ----------------------------------------
+#define LCD_CRSR_IMG138_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG138: CRSR_IMG Position  */
+#define LCD_CRSR_IMG138_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG138: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG139  ----------------------------------------
+#define LCD_CRSR_IMG139_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG139: CRSR_IMG Position  */
+#define LCD_CRSR_IMG139_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG139: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG140  ----------------------------------------
+#define LCD_CRSR_IMG140_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG140: CRSR_IMG Position  */
+#define LCD_CRSR_IMG140_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG140: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG141  ----------------------------------------
+#define LCD_CRSR_IMG141_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG141: CRSR_IMG Position  */
+#define LCD_CRSR_IMG141_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG141: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG142  ----------------------------------------
+#define LCD_CRSR_IMG142_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG142: CRSR_IMG Position  */
+#define LCD_CRSR_IMG142_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG142: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG143  ----------------------------------------
+#define LCD_CRSR_IMG143_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG143: CRSR_IMG Position  */
+#define LCD_CRSR_IMG143_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG143: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG144  ----------------------------------------
+#define LCD_CRSR_IMG144_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG144: CRSR_IMG Position  */
+#define LCD_CRSR_IMG144_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG144: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG145  ----------------------------------------
+#define LCD_CRSR_IMG145_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG145: CRSR_IMG Position  */
+#define LCD_CRSR_IMG145_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG145: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG146  ----------------------------------------
+#define LCD_CRSR_IMG146_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG146: CRSR_IMG Position  */
+#define LCD_CRSR_IMG146_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG146: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG147  ----------------------------------------
+#define LCD_CRSR_IMG147_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG147: CRSR_IMG Position  */
+#define LCD_CRSR_IMG147_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG147: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG148  ----------------------------------------
+#define LCD_CRSR_IMG148_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG148: CRSR_IMG Position  */
+#define LCD_CRSR_IMG148_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG148: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG149  ----------------------------------------
+#define LCD_CRSR_IMG149_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG149: CRSR_IMG Position  */
+#define LCD_CRSR_IMG149_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG149: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG150  ----------------------------------------
+#define LCD_CRSR_IMG150_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG150: CRSR_IMG Position  */
+#define LCD_CRSR_IMG150_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG150: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG151  ----------------------------------------
+#define LCD_CRSR_IMG151_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG151: CRSR_IMG Position  */
+#define LCD_CRSR_IMG151_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG151: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG152  ----------------------------------------
+#define LCD_CRSR_IMG152_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG152: CRSR_IMG Position  */
+#define LCD_CRSR_IMG152_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG152: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG153  ----------------------------------------
+#define LCD_CRSR_IMG153_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG153: CRSR_IMG Position  */
+#define LCD_CRSR_IMG153_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG153: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG154  ----------------------------------------
+#define LCD_CRSR_IMG154_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG154: CRSR_IMG Position  */
+#define LCD_CRSR_IMG154_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG154: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG155  ----------------------------------------
+#define LCD_CRSR_IMG155_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG155: CRSR_IMG Position  */
+#define LCD_CRSR_IMG155_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG155: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG156  ----------------------------------------
+#define LCD_CRSR_IMG156_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG156: CRSR_IMG Position  */
+#define LCD_CRSR_IMG156_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG156: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG157  ----------------------------------------
+#define LCD_CRSR_IMG157_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG157: CRSR_IMG Position  */
+#define LCD_CRSR_IMG157_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG157: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG158  ----------------------------------------
+#define LCD_CRSR_IMG158_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG158: CRSR_IMG Position  */
+#define LCD_CRSR_IMG158_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG158: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG159  ----------------------------------------
+#define LCD_CRSR_IMG159_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG159: CRSR_IMG Position  */
+#define LCD_CRSR_IMG159_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG159: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG160  ----------------------------------------
+#define LCD_CRSR_IMG160_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG160: CRSR_IMG Position  */
+#define LCD_CRSR_IMG160_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG160: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG161  ----------------------------------------
+#define LCD_CRSR_IMG161_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG161: CRSR_IMG Position  */
+#define LCD_CRSR_IMG161_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG161: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG162  ----------------------------------------
+#define LCD_CRSR_IMG162_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG162: CRSR_IMG Position  */
+#define LCD_CRSR_IMG162_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG162: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG163  ----------------------------------------
+#define LCD_CRSR_IMG163_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG163: CRSR_IMG Position  */
+#define LCD_CRSR_IMG163_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG163: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG164  ----------------------------------------
+#define LCD_CRSR_IMG164_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG164: CRSR_IMG Position  */
+#define LCD_CRSR_IMG164_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG164: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG165  ----------------------------------------
+#define LCD_CRSR_IMG165_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG165: CRSR_IMG Position  */
+#define LCD_CRSR_IMG165_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG165: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG166  ----------------------------------------
+#define LCD_CRSR_IMG166_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG166: CRSR_IMG Position  */
+#define LCD_CRSR_IMG166_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG166: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG167  ----------------------------------------
+#define LCD_CRSR_IMG167_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG167: CRSR_IMG Position  */
+#define LCD_CRSR_IMG167_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG167: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG168  ----------------------------------------
+#define LCD_CRSR_IMG168_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG168: CRSR_IMG Position  */
+#define LCD_CRSR_IMG168_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG168: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG169  ----------------------------------------
+#define LCD_CRSR_IMG169_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG169: CRSR_IMG Position  */
+#define LCD_CRSR_IMG169_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG169: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG170  ----------------------------------------
+#define LCD_CRSR_IMG170_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG170: CRSR_IMG Position  */
+#define LCD_CRSR_IMG170_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG170: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG171  ----------------------------------------
+#define LCD_CRSR_IMG171_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG171: CRSR_IMG Position  */
+#define LCD_CRSR_IMG171_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG171: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG172  ----------------------------------------
+#define LCD_CRSR_IMG172_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG172: CRSR_IMG Position  */
+#define LCD_CRSR_IMG172_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG172: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG173  ----------------------------------------
+#define LCD_CRSR_IMG173_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG173: CRSR_IMG Position  */
+#define LCD_CRSR_IMG173_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG173: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG174  ----------------------------------------
+#define LCD_CRSR_IMG174_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG174: CRSR_IMG Position  */
+#define LCD_CRSR_IMG174_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG174: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG175  ----------------------------------------
+#define LCD_CRSR_IMG175_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG175: CRSR_IMG Position  */
+#define LCD_CRSR_IMG175_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG175: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG176  ----------------------------------------
+#define LCD_CRSR_IMG176_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG176: CRSR_IMG Position  */
+#define LCD_CRSR_IMG176_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG176: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG177  ----------------------------------------
+#define LCD_CRSR_IMG177_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG177: CRSR_IMG Position  */
+#define LCD_CRSR_IMG177_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG177: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG178  ----------------------------------------
+#define LCD_CRSR_IMG178_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG178: CRSR_IMG Position  */
+#define LCD_CRSR_IMG178_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG178: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG179  ----------------------------------------
+#define LCD_CRSR_IMG179_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG179: CRSR_IMG Position  */
+#define LCD_CRSR_IMG179_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG179: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG180  ----------------------------------------
+#define LCD_CRSR_IMG180_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG180: CRSR_IMG Position  */
+#define LCD_CRSR_IMG180_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG180: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG181  ----------------------------------------
+#define LCD_CRSR_IMG181_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG181: CRSR_IMG Position  */
+#define LCD_CRSR_IMG181_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG181: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG182  ----------------------------------------
+#define LCD_CRSR_IMG182_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG182: CRSR_IMG Position  */
+#define LCD_CRSR_IMG182_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG182: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG183  ----------------------------------------
+#define LCD_CRSR_IMG183_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG183: CRSR_IMG Position  */
+#define LCD_CRSR_IMG183_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG183: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG184  ----------------------------------------
+#define LCD_CRSR_IMG184_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG184: CRSR_IMG Position  */
+#define LCD_CRSR_IMG184_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG184: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG185  ----------------------------------------
+#define LCD_CRSR_IMG185_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG185: CRSR_IMG Position  */
+#define LCD_CRSR_IMG185_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG185: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG186  ----------------------------------------
+#define LCD_CRSR_IMG186_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG186: CRSR_IMG Position  */
+#define LCD_CRSR_IMG186_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG186: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG187  ----------------------------------------
+#define LCD_CRSR_IMG187_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG187: CRSR_IMG Position  */
+#define LCD_CRSR_IMG187_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG187: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG188  ----------------------------------------
+#define LCD_CRSR_IMG188_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG188: CRSR_IMG Position  */
+#define LCD_CRSR_IMG188_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG188: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG189  ----------------------------------------
+#define LCD_CRSR_IMG189_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG189: CRSR_IMG Position  */
+#define LCD_CRSR_IMG189_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG189: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG190  ----------------------------------------
+#define LCD_CRSR_IMG190_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG190: CRSR_IMG Position  */
+#define LCD_CRSR_IMG190_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG190: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG191  ----------------------------------------
+#define LCD_CRSR_IMG191_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG191: CRSR_IMG Position  */
+#define LCD_CRSR_IMG191_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG191: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG192  ----------------------------------------
+#define LCD_CRSR_IMG192_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG192: CRSR_IMG Position  */
+#define LCD_CRSR_IMG192_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG192: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG193  ----------------------------------------
+#define LCD_CRSR_IMG193_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG193: CRSR_IMG Position  */
+#define LCD_CRSR_IMG193_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG193: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG194  ----------------------------------------
+#define LCD_CRSR_IMG194_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG194: CRSR_IMG Position  */
+#define LCD_CRSR_IMG194_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG194: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG195  ----------------------------------------
+#define LCD_CRSR_IMG195_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG195: CRSR_IMG Position  */
+#define LCD_CRSR_IMG195_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG195: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG196  ----------------------------------------
+#define LCD_CRSR_IMG196_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG196: CRSR_IMG Position  */
+#define LCD_CRSR_IMG196_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG196: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG197  ----------------------------------------
+#define LCD_CRSR_IMG197_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG197: CRSR_IMG Position  */
+#define LCD_CRSR_IMG197_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG197: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG198  ----------------------------------------
+#define LCD_CRSR_IMG198_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG198: CRSR_IMG Position  */
+#define LCD_CRSR_IMG198_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG198: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG199  ----------------------------------------
+#define LCD_CRSR_IMG199_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG199: CRSR_IMG Position  */
+#define LCD_CRSR_IMG199_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG199: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG200  ----------------------------------------
+#define LCD_CRSR_IMG200_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG200: CRSR_IMG Position  */
+#define LCD_CRSR_IMG200_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG200: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG201  ----------------------------------------
+#define LCD_CRSR_IMG201_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG201: CRSR_IMG Position  */
+#define LCD_CRSR_IMG201_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG201: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG202  ----------------------------------------
+#define LCD_CRSR_IMG202_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG202: CRSR_IMG Position  */
+#define LCD_CRSR_IMG202_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG202: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG203  ----------------------------------------
+#define LCD_CRSR_IMG203_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG203: CRSR_IMG Position  */
+#define LCD_CRSR_IMG203_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG203: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG204  ----------------------------------------
+#define LCD_CRSR_IMG204_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG204: CRSR_IMG Position  */
+#define LCD_CRSR_IMG204_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG204: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG205  ----------------------------------------
+#define LCD_CRSR_IMG205_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG205: CRSR_IMG Position  */
+#define LCD_CRSR_IMG205_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG205: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG206  ----------------------------------------
+#define LCD_CRSR_IMG206_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG206: CRSR_IMG Position  */
+#define LCD_CRSR_IMG206_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG206: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG207  ----------------------------------------
+#define LCD_CRSR_IMG207_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG207: CRSR_IMG Position  */
+#define LCD_CRSR_IMG207_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG207: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG208  ----------------------------------------
+#define LCD_CRSR_IMG208_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG208: CRSR_IMG Position  */
+#define LCD_CRSR_IMG208_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG208: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG209  ----------------------------------------
+#define LCD_CRSR_IMG209_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG209: CRSR_IMG Position  */
+#define LCD_CRSR_IMG209_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG209: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG210  ----------------------------------------
+#define LCD_CRSR_IMG210_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG210: CRSR_IMG Position  */
+#define LCD_CRSR_IMG210_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG210: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG211  ----------------------------------------
+#define LCD_CRSR_IMG211_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG211: CRSR_IMG Position  */
+#define LCD_CRSR_IMG211_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG211: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG212  ----------------------------------------
+#define LCD_CRSR_IMG212_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG212: CRSR_IMG Position  */
+#define LCD_CRSR_IMG212_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG212: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG213  ----------------------------------------
+#define LCD_CRSR_IMG213_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG213: CRSR_IMG Position  */
+#define LCD_CRSR_IMG213_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG213: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG214  ----------------------------------------
+#define LCD_CRSR_IMG214_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG214: CRSR_IMG Position  */
+#define LCD_CRSR_IMG214_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG214: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG215  ----------------------------------------
+#define LCD_CRSR_IMG215_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG215: CRSR_IMG Position  */
+#define LCD_CRSR_IMG215_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG215: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG216  ----------------------------------------
+#define LCD_CRSR_IMG216_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG216: CRSR_IMG Position  */
+#define LCD_CRSR_IMG216_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG216: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG217  ----------------------------------------
+#define LCD_CRSR_IMG217_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG217: CRSR_IMG Position  */
+#define LCD_CRSR_IMG217_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG217: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG218  ----------------------------------------
+#define LCD_CRSR_IMG218_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG218: CRSR_IMG Position  */
+#define LCD_CRSR_IMG218_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG218: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG219  ----------------------------------------
+#define LCD_CRSR_IMG219_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG219: CRSR_IMG Position  */
+#define LCD_CRSR_IMG219_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG219: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG220  ----------------------------------------
+#define LCD_CRSR_IMG220_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG220: CRSR_IMG Position  */
+#define LCD_CRSR_IMG220_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG220: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG221  ----------------------------------------
+#define LCD_CRSR_IMG221_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG221: CRSR_IMG Position  */
+#define LCD_CRSR_IMG221_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG221: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG222  ----------------------------------------
+#define LCD_CRSR_IMG222_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG222: CRSR_IMG Position  */
+#define LCD_CRSR_IMG222_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG222: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG223  ----------------------------------------
+#define LCD_CRSR_IMG223_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG223: CRSR_IMG Position  */
+#define LCD_CRSR_IMG223_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG223: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG224  ----------------------------------------
+#define LCD_CRSR_IMG224_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG224: CRSR_IMG Position  */
+#define LCD_CRSR_IMG224_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG224: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG225  ----------------------------------------
+#define LCD_CRSR_IMG225_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG225: CRSR_IMG Position  */
+#define LCD_CRSR_IMG225_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG225: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG226  ----------------------------------------
+#define LCD_CRSR_IMG226_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG226: CRSR_IMG Position  */
+#define LCD_CRSR_IMG226_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG226: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG227  ----------------------------------------
+#define LCD_CRSR_IMG227_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG227: CRSR_IMG Position  */
+#define LCD_CRSR_IMG227_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG227: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG228  ----------------------------------------
+#define LCD_CRSR_IMG228_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG228: CRSR_IMG Position  */
+#define LCD_CRSR_IMG228_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG228: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG229  ----------------------------------------
+#define LCD_CRSR_IMG229_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG229: CRSR_IMG Position  */
+#define LCD_CRSR_IMG229_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG229: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG230  ----------------------------------------
+#define LCD_CRSR_IMG230_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG230: CRSR_IMG Position  */
+#define LCD_CRSR_IMG230_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG230: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG231  ----------------------------------------
+#define LCD_CRSR_IMG231_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG231: CRSR_IMG Position  */
+#define LCD_CRSR_IMG231_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG231: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG232  ----------------------------------------
+#define LCD_CRSR_IMG232_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG232: CRSR_IMG Position  */
+#define LCD_CRSR_IMG232_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG232: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG233  ----------------------------------------
+#define LCD_CRSR_IMG233_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG233: CRSR_IMG Position  */
+#define LCD_CRSR_IMG233_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG233: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG234  ----------------------------------------
+#define LCD_CRSR_IMG234_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG234: CRSR_IMG Position  */
+#define LCD_CRSR_IMG234_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG234: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG235  ----------------------------------------
+#define LCD_CRSR_IMG235_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG235: CRSR_IMG Position  */
+#define LCD_CRSR_IMG235_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG235: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG236  ----------------------------------------
+#define LCD_CRSR_IMG236_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG236: CRSR_IMG Position  */
+#define LCD_CRSR_IMG236_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG236: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG237  ----------------------------------------
+#define LCD_CRSR_IMG237_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG237: CRSR_IMG Position  */
+#define LCD_CRSR_IMG237_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG237: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG238  ----------------------------------------
+#define LCD_CRSR_IMG238_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG238: CRSR_IMG Position  */
+#define LCD_CRSR_IMG238_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG238: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG239  ----------------------------------------
+#define LCD_CRSR_IMG239_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG239: CRSR_IMG Position  */
+#define LCD_CRSR_IMG239_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG239: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG240  ----------------------------------------
+#define LCD_CRSR_IMG240_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG240: CRSR_IMG Position  */
+#define LCD_CRSR_IMG240_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG240: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG241  ----------------------------------------
+#define LCD_CRSR_IMG241_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG241: CRSR_IMG Position  */
+#define LCD_CRSR_IMG241_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG241: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG242  ----------------------------------------
+#define LCD_CRSR_IMG242_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG242: CRSR_IMG Position  */
+#define LCD_CRSR_IMG242_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG242: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG243  ----------------------------------------
+#define LCD_CRSR_IMG243_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG243: CRSR_IMG Position  */
+#define LCD_CRSR_IMG243_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG243: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG244  ----------------------------------------
+#define LCD_CRSR_IMG244_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG244: CRSR_IMG Position  */
+#define LCD_CRSR_IMG244_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG244: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG245  ----------------------------------------
+#define LCD_CRSR_IMG245_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG245: CRSR_IMG Position  */
+#define LCD_CRSR_IMG245_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG245: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG246  ----------------------------------------
+#define LCD_CRSR_IMG246_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG246: CRSR_IMG Position  */
+#define LCD_CRSR_IMG246_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG246: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG247  ----------------------------------------
+#define LCD_CRSR_IMG247_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG247: CRSR_IMG Position  */
+#define LCD_CRSR_IMG247_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG247: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG248  ----------------------------------------
+#define LCD_CRSR_IMG248_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG248: CRSR_IMG Position  */
+#define LCD_CRSR_IMG248_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG248: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG249  ----------------------------------------
+#define LCD_CRSR_IMG249_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG249: CRSR_IMG Position  */
+#define LCD_CRSR_IMG249_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG249: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG250  ----------------------------------------
+#define LCD_CRSR_IMG250_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG250: CRSR_IMG Position  */
+#define LCD_CRSR_IMG250_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG250: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG251  ----------------------------------------
+#define LCD_CRSR_IMG251_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG251: CRSR_IMG Position  */
+#define LCD_CRSR_IMG251_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG251: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG252  ----------------------------------------
+#define LCD_CRSR_IMG252_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG252: CRSR_IMG Position  */
+#define LCD_CRSR_IMG252_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG252: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG253  ----------------------------------------
+#define LCD_CRSR_IMG253_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG253: CRSR_IMG Position  */
+#define LCD_CRSR_IMG253_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG253: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG254  ----------------------------------------
+#define LCD_CRSR_IMG254_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG254: CRSR_IMG Position  */
+#define LCD_CRSR_IMG254_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG254: CRSR_IMG Mask      */
+
+// -------------------------------------  LCD_CRSR_IMG255  ----------------------------------------
+#define LCD_CRSR_IMG255_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG255: CRSR_IMG Position  */
+#define LCD_CRSR_IMG255_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG255: CRSR_IMG Mask      */
+
+// --------------------------------------  LCD_CRSR_CTRL  -----------------------------------------
+#define LCD_CRSR_CTRL_CrsrOn_Pos                              0                                                         /*!< LCD CRSR_CTRL: CrsrOn Position      */
+#define LCD_CRSR_CTRL_CrsrOn_Msk                              (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos)                      /*!< LCD CRSR_CTRL: CrsrOn Mask          */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos                          4                                                         /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position  */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk                          (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos)                  /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask      */
+
+// --------------------------------------  LCD_CRSR_CFG  ------------------------------------------
+#define LCD_CRSR_CFG_CrsrSize_Pos                             0                                                         /*!< LCD CRSR_CFG: CrsrSize Position     */
+#define LCD_CRSR_CFG_CrsrSize_Msk                             (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos)                     /*!< LCD CRSR_CFG: CrsrSize Mask         */
+#define LCD_CRSR_CFG_FRAMESYNC_Pos                            1                                                         /*!< LCD CRSR_CFG: FRAMESYNC Position    */
+#define LCD_CRSR_CFG_FRAMESYNC_Msk                            (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos)                    /*!< LCD CRSR_CFG: FRAMESYNC Mask        */
+
+// --------------------------------------  LCD_CRSR_PAL0  -----------------------------------------
+#define LCD_CRSR_PAL0_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL0: RED Position         */
+#define LCD_CRSR_PAL0_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos)                   /*!< LCD CRSR_PAL0: RED Mask             */
+#define LCD_CRSR_PAL0_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL0: GREEN Position       */
+#define LCD_CRSR_PAL0_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos)                 /*!< LCD CRSR_PAL0: GREEN Mask           */
+#define LCD_CRSR_PAL0_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL0: BLUE Position        */
+#define LCD_CRSR_PAL0_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos)                  /*!< LCD CRSR_PAL0: BLUE Mask            */
+
+// --------------------------------------  LCD_CRSR_PAL1  -----------------------------------------
+#define LCD_CRSR_PAL1_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL1: RED Position         */
+#define LCD_CRSR_PAL1_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos)                   /*!< LCD CRSR_PAL1: RED Mask             */
+#define LCD_CRSR_PAL1_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL1: GREEN Position       */
+#define LCD_CRSR_PAL1_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos)                 /*!< LCD CRSR_PAL1: GREEN Mask           */
+#define LCD_CRSR_PAL1_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL1: BLUE Position        */
+#define LCD_CRSR_PAL1_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos)                  /*!< LCD CRSR_PAL1: BLUE Mask            */
+
+// ---------------------------------------  LCD_CRSR_XY  ------------------------------------------
+#define LCD_CRSR_XY_CRSRX_Pos                                 0                                                         /*!< LCD CRSR_XY: CRSRX Position         */
+#define LCD_CRSR_XY_CRSRX_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos)                   /*!< LCD CRSR_XY: CRSRX Mask             */
+#define LCD_CRSR_XY_CRSRY_Pos                                 16                                                        /*!< LCD CRSR_XY: CRSRY Position         */
+#define LCD_CRSR_XY_CRSRY_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos)                   /*!< LCD CRSR_XY: CRSRY Mask             */
+
+// --------------------------------------  LCD_CRSR_CLIP  -----------------------------------------
+#define LCD_CRSR_CLIP_CRSRCLIPX_Pos                           0                                                         /*!< LCD CRSR_CLIP: CRSRCLIPX Position   */
+#define LCD_CRSR_CLIP_CRSRCLIPX_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPX Mask       */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Pos                           8                                                         /*!< LCD CRSR_CLIP: CRSRCLIPY Position   */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPY Mask       */
+
+// -------------------------------------  LCD_CRSR_INTMSK  ----------------------------------------
+#define LCD_CRSR_INTMSK_CRSRIM_Pos                            0                                                         /*!< LCD CRSR_INTMSK: CRSRIM Position    */
+#define LCD_CRSR_INTMSK_CRSRIM_Msk                            (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos)                    /*!< LCD CRSR_INTMSK: CRSRIM Mask        */
+
+// -------------------------------------  LCD_CRSR_INTCLR  ----------------------------------------
+#define LCD_CRSR_INTCLR_CRSRIC_Pos                            0                                                         /*!< LCD CRSR_INTCLR: CRSRIC Position    */
+#define LCD_CRSR_INTCLR_CRSRIC_Msk                            (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos)                    /*!< LCD CRSR_INTCLR: CRSRIC Mask        */
+
+// -------------------------------------  LCD_CRSR_INTRAW  ----------------------------------------
+#define LCD_CRSR_INTRAW_CRSRRIS_Pos                           0                                                         /*!< LCD CRSR_INTRAW: CRSRRIS Position   */
+#define LCD_CRSR_INTRAW_CRSRRIS_Msk                           (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos)                   /*!< LCD CRSR_INTRAW: CRSRRIS Mask       */
+
+// ------------------------------------  LCD_CRSR_INTSTAT  ----------------------------------------
+#define LCD_CRSR_INTSTAT_CRSRMIS_Pos                          0                                                         /*!< LCD CRSR_INTSTAT: CRSRMIS Position  */
+#define LCD_CRSR_INTSTAT_CRSRMIS_Msk                          (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos)                  /*!< LCD CRSR_INTSTAT: CRSRMIS Mask      */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                               ETHERNET Position & Mask                               -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------  ETHERNET_MAC_CONFIG  --------------------------------------
+#define ETHERNET_MAC_CONFIG_RE_Pos                            2                                                         /*!< ETHERNET MAC_CONFIG: RE Position    */
+#define ETHERNET_MAC_CONFIG_RE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos)                    /*!< ETHERNET MAC_CONFIG: RE Mask        */
+#define ETHERNET_MAC_CONFIG_TE_Pos                            3                                                         /*!< ETHERNET MAC_CONFIG: TE Position    */
+#define ETHERNET_MAC_CONFIG_TE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos)                    /*!< ETHERNET MAC_CONFIG: TE Mask        */
+#define ETHERNET_MAC_CONFIG_DF_Pos                            4                                                         /*!< ETHERNET MAC_CONFIG: DF Position    */
+#define ETHERNET_MAC_CONFIG_DF_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos)                    /*!< ETHERNET MAC_CONFIG: DF Mask        */
+#define ETHERNET_MAC_CONFIG_BL_Pos                            5                                                         /*!< ETHERNET MAC_CONFIG: BL Position    */
+#define ETHERNET_MAC_CONFIG_BL_Msk                            (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos)                    /*!< ETHERNET MAC_CONFIG: BL Mask        */
+#define ETHERNET_MAC_CONFIG_ACS_Pos                           7                                                         /*!< ETHERNET MAC_CONFIG: ACS Position   */
+#define ETHERNET_MAC_CONFIG_ACS_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos)                   /*!< ETHERNET MAC_CONFIG: ACS Mask       */
+#define ETHERNET_MAC_CONFIG_DR_Pos                            9                                                         /*!< ETHERNET MAC_CONFIG: DR Position    */
+#define ETHERNET_MAC_CONFIG_DR_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos)                    /*!< ETHERNET MAC_CONFIG: DR Mask        */
+#define ETHERNET_MAC_CONFIG_IPC_Pos                           10                                                        /*!< ETHERNET MAC_CONFIG: IPC Position   */
+#define ETHERNET_MAC_CONFIG_IPC_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos)                   /*!< ETHERNET MAC_CONFIG: IPC Mask       */
+#define ETHERNET_MAC_CONFIG_DM_Pos                            11                                                        /*!< ETHERNET MAC_CONFIG: DM Position    */
+#define ETHERNET_MAC_CONFIG_DM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos)                    /*!< ETHERNET MAC_CONFIG: DM Mask        */
+#define ETHERNET_MAC_CONFIG_LM_Pos                            12                                                        /*!< ETHERNET MAC_CONFIG: LM Position    */
+#define ETHERNET_MAC_CONFIG_LM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos)                    /*!< ETHERNET MAC_CONFIG: LM Mask        */
+#define ETHERNET_MAC_CONFIG_DO_Pos                            13                                                        /*!< ETHERNET MAC_CONFIG: DO Position    */
+#define ETHERNET_MAC_CONFIG_DO_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos)                    /*!< ETHERNET MAC_CONFIG: DO Mask        */
+#define ETHERNET_MAC_CONFIG_FES_Pos                           14                                                        /*!< ETHERNET MAC_CONFIG: FES Position   */
+#define ETHERNET_MAC_CONFIG_FES_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos)                   /*!< ETHERNET MAC_CONFIG: FES Mask       */
+#define ETHERNET_MAC_CONFIG_PS_Pos                            15                                                        /*!< ETHERNET MAC_CONFIG: PS Position    */
+#define ETHERNET_MAC_CONFIG_PS_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos)                    /*!< ETHERNET MAC_CONFIG: PS Mask        */
+#define ETHERNET_MAC_CONFIG_DCRS_Pos                          16                                                        /*!< ETHERNET MAC_CONFIG: DCRS Position  */
+#define ETHERNET_MAC_CONFIG_DCRS_Msk                          (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos)                  /*!< ETHERNET MAC_CONFIG: DCRS Mask      */
+#define ETHERNET_MAC_CONFIG_IFG_Pos                           17                                                        /*!< ETHERNET MAC_CONFIG: IFG Position   */
+#define ETHERNET_MAC_CONFIG_IFG_Msk                           (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos)                   /*!< ETHERNET MAC_CONFIG: IFG Mask       */
+#define ETHERNET_MAC_CONFIG_JE_Pos                            20                                                        /*!< ETHERNET MAC_CONFIG: JE Position    */
+#define ETHERNET_MAC_CONFIG_JE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos)                    /*!< ETHERNET MAC_CONFIG: JE Mask        */
+#define ETHERNET_MAC_CONFIG_JD_Pos                            22                                                        /*!< ETHERNET MAC_CONFIG: JD Position    */
+#define ETHERNET_MAC_CONFIG_JD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos)                    /*!< ETHERNET MAC_CONFIG: JD Mask        */
+#define ETHERNET_MAC_CONFIG_WD_Pos                            23                                                        /*!< ETHERNET MAC_CONFIG: WD Position    */
+#define ETHERNET_MAC_CONFIG_WD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos)                    /*!< ETHERNET MAC_CONFIG: WD Mask        */
+
+// --------------------------------  ETHERNET_MAC_FRAME_FILTER  -----------------------------------
+#define ETHERNET_MAC_FRAME_FILTER_PR_Pos                      0                                                         /*!< ETHERNET MAC_FRAME_FILTER: PR Position */
+#define ETHERNET_MAC_FRAME_FILTER_PR_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PR Mask  */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos                    3                                                         /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Pos                      4                                                         /*!< ETHERNET MAC_FRAME_FILTER: PM Position */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PM Mask  */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos                     5                                                         /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos                     6                                                         /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk                     (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos                    8                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos                     9                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Pos                      31                                                        /*!< ETHERNET MAC_FRAME_FILTER: RA Position */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: RA Mask  */
+
+// -------------------------------  ETHERNET_MAC_HASHTABLE_HIGH  ----------------------------------
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos                   0                                                         /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk                   (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos)     /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */
+
+// -------------------------------  ETHERNET_MAC_HASHTABLE_LOW  -----------------------------------
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos                    0                                                         /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk                    (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos)      /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */
+
+// ----------------------------------  ETHERNET_MAC_MII_ADDR  -------------------------------------
+#define ETHERNET_MAC_MII_ADDR_GB_Pos                          0                                                         /*!< ETHERNET MAC_MII_ADDR: GB Position  */
+#define ETHERNET_MAC_MII_ADDR_GB_Msk                          (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GB Mask      */
+#define ETHERNET_MAC_MII_ADDR_W_Pos                           1                                                         /*!< ETHERNET MAC_MII_ADDR: W Position   */
+#define ETHERNET_MAC_MII_ADDR_W_Msk                           (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos)                   /*!< ETHERNET MAC_MII_ADDR: W Mask       */
+#define ETHERNET_MAC_MII_ADDR_CR_Pos                          2                                                         /*!< ETHERNET MAC_MII_ADDR: CR Position  */
+#define ETHERNET_MAC_MII_ADDR_CR_Msk                          (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: CR Mask      */
+#define ETHERNET_MAC_MII_ADDR_GR_Pos                          6                                                         /*!< ETHERNET MAC_MII_ADDR: GR Position  */
+#define ETHERNET_MAC_MII_ADDR_GR_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GR Mask      */
+#define ETHERNET_MAC_MII_ADDR_PA_Pos                          11                                                        /*!< ETHERNET MAC_MII_ADDR: PA Position  */
+#define ETHERNET_MAC_MII_ADDR_PA_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos)                  /*!< ETHERNET MAC_MII_ADDR: PA Mask      */
+
+// ----------------------------------  ETHERNET_MAC_MII_DATA  -------------------------------------
+#define ETHERNET_MAC_MII_DATA_GD_Pos                          0                                                         /*!< ETHERNET MAC_MII_DATA: GD Position  */
+#define ETHERNET_MAC_MII_DATA_GD_Msk                          (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos)            /*!< ETHERNET MAC_MII_DATA: GD Mask      */
+
+// ---------------------------------  ETHERNET_MAC_FLOW_CTRL  -------------------------------------
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos                        0                                                         /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos                        1                                                         /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos                        2                                                         /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Pos                         3                                                         /*!< ETHERNET MAC_FLOW_CTRL: UP Position */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Msk                         (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos)                 /*!< ETHERNET MAC_FLOW_CTRL: UP Mask     */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos                        4                                                         /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk                        (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask    */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos                       7                                                         /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk                       (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos)               /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask   */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Pos                         16                                                        /*!< ETHERNET MAC_FLOW_CTRL: PT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Msk                         (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos)           /*!< ETHERNET MAC_FLOW_CTRL: PT Mask     */
+
+// ----------------------------------  ETHERNET_MAC_VLAN_TAG  -------------------------------------
+#define ETHERNET_MAC_VLAN_TAG_VL_Pos                          0                                                         /*!< ETHERNET MAC_VLAN_TAG: VL Position  */
+#define ETHERNET_MAC_VLAN_TAG_VL_Msk                          (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos)            /*!< ETHERNET MAC_VLAN_TAG: VL Mask      */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Pos                         16                                                        /*!< ETHERNET MAC_VLAN_TAG: ETV Position */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Msk                         (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos)                 /*!< ETHERNET MAC_VLAN_TAG: ETV Mask     */
+
+// -----------------------------------  ETHERNET_MAC_DEBUG  ---------------------------------------
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos                     0                                                         /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos                      1                                                         /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos)              /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask  */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos                    4                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos                     5                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos                      8                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask  */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos                     16                                                        /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Pos                         17                                                        /*!< ETHERNET MAC_DEBUG: TXSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Msk                         (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos)                 /*!< ETHERNET MAC_DEBUG: TXSTAT Mask     */
+#define ETHERNET_MAC_DEBUG_PAUSE_Pos                          19                                                        /*!< ETHERNET MAC_DEBUG: PAUSE Position  */
+#define ETHERNET_MAC_DEBUG_PAUSE_Msk                          (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos)                  /*!< ETHERNET MAC_DEBUG: PAUSE Mask      */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos                     20                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos                    22                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos                      24                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk                      (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask  */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos                     25                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */
+
+// --------------------------------  ETHERNET_MAC_RWAKE_FRFLT  ------------------------------------
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos                     0                                                         /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk                     (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos)       /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */
+
+// -------------------------------  ETHERNET_MAC_PMT_CTRL_STAT  -----------------------------------
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos                     0                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos                    1                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos                    2                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos                    5                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos                    6                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos                     9                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos                 31                                                        /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk                 (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos)         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */
+
+// ---------------------------------  ETHERNET_MAC_INTR_MASK  -------------------------------------
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos                     3                                                         /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk                     (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos)             /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */
+
+// ---------------------------------  ETHERNET_MAC_ADDR0_HIGH  ------------------------------------
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos                    0                                                         /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk                    (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos)      /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos                        31                                                        /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk                        (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos)                /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask    */
+
+// ---------------------------------  ETHERNET_MAC_ADDR0_LOW  -------------------------------------
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos                      0                                                         /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk                      (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos)        /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask  */
+
+// --------------------------------  ETHERNET_MAC_TIMESTP_CTRL  -----------------------------------
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos                   0                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk                   (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos)           /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos                1                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos                  2                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos                  3                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos                  4                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos                5                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos                 8                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos               9                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos               10                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos                 11                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos               12                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos               13                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos               14                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos               15                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos               16                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk               (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos             18                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk             (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)     /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */
+
+// ---------------------------------  ETHERNET_SUBSECOND_INCR  ------------------------------------
+#define ETHERNET_SUBSECOND_INCR_SSINC_Pos                     0                                                         /*!< ETHERNET SUBSECOND_INCR: SSINC Position */
+#define ETHERNET_SUBSECOND_INCR_SSINC_Msk                     (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos)       /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */
+
+// ------------------------------------  ETHERNET_SECONDS  ----------------------------------------
+#define ETHERNET_SECONDS_TSS_Pos                              0                                                         /*!< ETHERNET SECONDS: TSS Position      */
+#define ETHERNET_SECONDS_TSS_Msk                              (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos)                /*!< ETHERNET SECONDS: TSS Mask          */
+
+// ----------------------------------  ETHERNET_NANOSECONDS  --------------------------------------
+#define ETHERNET_NANOSECONDS_TSSS_Pos                         0                                                         /*!< ETHERNET NANOSECONDS: TSSS Position */
+#define ETHERNET_NANOSECONDS_TSSS_Msk                         (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos)           /*!< ETHERNET NANOSECONDS: TSSS Mask     */
+#define ETHERNET_NANOSECONDS_PSNT_Pos                         31                                                        /*!< ETHERNET NANOSECONDS: PSNT Position */
+#define ETHERNET_NANOSECONDS_PSNT_Msk                         (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos)                 /*!< ETHERNET NANOSECONDS: PSNT Mask     */
+
+// ---------------------------------  ETHERNET_SECONDSUPDATE  -------------------------------------
+#define ETHERNET_SECONDSUPDATE_TSS_Pos                        0                                                         /*!< ETHERNET SECONDSUPDATE: TSS Position */
+#define ETHERNET_SECONDSUPDATE_TSS_Msk                        (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos)          /*!< ETHERNET SECONDSUPDATE: TSS Mask    */
+
+// -------------------------------  ETHERNET_NANOSECONDSUPDATE  -----------------------------------
+#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos                   0                                                         /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */
+#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk                   (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos)     /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */
+#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos                 31                                                        /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */
+#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk                 (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos)         /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */
+
+// -------------------------------------  ETHERNET_ADDEND  ----------------------------------------
+#define ETHERNET_ADDEND_TSAR_Pos                              0                                                         /*!< ETHERNET ADDEND: TSAR Position      */
+#define ETHERNET_ADDEND_TSAR_Msk                              (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos)                /*!< ETHERNET ADDEND: TSAR Mask          */
+
+// ---------------------------------  ETHERNET_TARGETSECONDS  -------------------------------------
+#define ETHERNET_TARGETSECONDS_TSTR_Pos                       0                                                         /*!< ETHERNET TARGETSECONDS: TSTR Position */
+#define ETHERNET_TARGETSECONDS_TSTR_Msk                       (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos)         /*!< ETHERNET TARGETSECONDS: TSTR Mask   */
+
+// -------------------------------  ETHERNET_TARGETNANOSECONDS  -----------------------------------
+#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos                   0                                                         /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */
+#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk                   (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos)     /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */
+
+// ------------------------------------  ETHERNET_HIGHWORD  ---------------------------------------
+#define ETHERNET_HIGHWORD_TSHWR_Pos                           0                                                         /*!< ETHERNET HIGHWORD: TSHWR Position   */
+#define ETHERNET_HIGHWORD_TSHWR_Msk                           (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos)             /*!< ETHERNET HIGHWORD: TSHWR Mask       */
+
+// ---------------------------------  ETHERNET_TIMESTAMPSTAT  -------------------------------------
+#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos                     0                                                         /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */
+#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos)             /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */
+#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos                    1                                                         /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */
+#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk                    (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos)            /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */
+#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos                      2                                                         /*!< ETHERNET TIMESTAMPSTAT: AUXSS Position */
+#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk                      (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: AUXSS Mask  */
+#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos                     24                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Position */
+#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos)             /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Mask */
+#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos                      25                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSNS Position */
+#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk                      (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: ATSNS Mask  */
+
+// ------------------------------------  ETHERNET_PPSCTRL  ----------------------------------------
+#define ETHERNET_PPSCTRL_PPSCTRL_Pos                          0                                                         /*!< ETHERNET PPSCTRL: PPSCTRL Position  */
+#define ETHERNET_PPSCTRL_PPSCTRL_Msk                          (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos)                  /*!< ETHERNET PPSCTRL: PPSCTRL Mask      */
+
+// ---------------------------------  ETHERNET_AUXNANOSECONDS  ------------------------------------
+#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos                     0                                                         /*!< ETHERNET AUXNANOSECONDS: AUXNS Position */
+#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk                     (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos)       /*!< ETHERNET AUXNANOSECONDS: AUXNS Mask */
+
+// -----------------------------------  ETHERNET_AUXSECONDS  --------------------------------------
+#define ETHERNET_AUXSECONDS_AUXS_Pos                          0                                                         /*!< ETHERNET AUXSECONDS: AUXS Position  */
+#define ETHERNET_AUXSECONDS_AUXS_Msk                          (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos)            /*!< ETHERNET AUXSECONDS: AUXS Mask      */
+
+// ----------------------------------  ETHERNET_DMA_BUS_MODE  -------------------------------------
+#define ETHERNET_DMA_BUS_MODE_SWR_Pos                         0                                                         /*!< ETHERNET DMA_BUS_MODE: SWR Position */
+#define ETHERNET_DMA_BUS_MODE_SWR_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos)                 /*!< ETHERNET DMA_BUS_MODE: SWR Mask     */
+#define ETHERNET_DMA_BUS_MODE_DA_Pos                          1                                                         /*!< ETHERNET DMA_BUS_MODE: DA Position  */
+#define ETHERNET_DMA_BUS_MODE_DA_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos)                  /*!< ETHERNET DMA_BUS_MODE: DA Mask      */
+#define ETHERNET_DMA_BUS_MODE_DSL_Pos                         2                                                         /*!< ETHERNET DMA_BUS_MODE: DSL Position */
+#define ETHERNET_DMA_BUS_MODE_DSL_Msk                         (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: DSL Mask     */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Pos                        7                                                         /*!< ETHERNET DMA_BUS_MODE: ATDS Position */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos)                /*!< ETHERNET DMA_BUS_MODE: ATDS Mask    */
+#define ETHERNET_DMA_BUS_MODE_PBL_Pos                         8                                                         /*!< ETHERNET DMA_BUS_MODE: PBL Position */
+#define ETHERNET_DMA_BUS_MODE_PBL_Msk                         (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: PBL Mask     */
+#define ETHERNET_DMA_BUS_MODE_PR_Pos                          14                                                        /*!< ETHERNET DMA_BUS_MODE: PR Position  */
+#define ETHERNET_DMA_BUS_MODE_PR_Msk                          (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos)                  /*!< ETHERNET DMA_BUS_MODE: PR Mask      */
+#define ETHERNET_DMA_BUS_MODE_FB_Pos                          16                                                        /*!< ETHERNET DMA_BUS_MODE: FB Position  */
+#define ETHERNET_DMA_BUS_MODE_FB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: FB Mask      */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Pos                        17                                                        /*!< ETHERNET DMA_BUS_MODE: RPBL Position */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Msk                        (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos)                /*!< ETHERNET DMA_BUS_MODE: RPBL Mask    */
+#define ETHERNET_DMA_BUS_MODE_USP_Pos                         23                                                        /*!< ETHERNET DMA_BUS_MODE: USP Position */
+#define ETHERNET_DMA_BUS_MODE_USP_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos)                 /*!< ETHERNET DMA_BUS_MODE: USP Mask     */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos                       24                                                        /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk                       (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos)               /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask   */
+#define ETHERNET_DMA_BUS_MODE_AAL_Pos                         25                                                        /*!< ETHERNET DMA_BUS_MODE: AAL Position */
+#define ETHERNET_DMA_BUS_MODE_AAL_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: AAL Mask     */
+#define ETHERNET_DMA_BUS_MODE_MB_Pos                          26                                                        /*!< ETHERNET DMA_BUS_MODE: MB Position  */
+#define ETHERNET_DMA_BUS_MODE_MB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: MB Mask      */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Pos                        27                                                        /*!< ETHERNET DMA_BUS_MODE: TXPR Position */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos)                /*!< ETHERNET DMA_BUS_MODE: TXPR Mask    */
+
+// -----------------------------  ETHERNET_DMA_TRANS_POLL_DEMAND  ---------------------------------
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos                0                                                         /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk                (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)  /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */
+
+// ------------------------------  ETHERNET_DMA_REC_POLL_DEMAND  ----------------------------------
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos                  0                                                         /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk                  (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos)    /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */
+
+// --------------------------------  ETHERNET_DMA_REC_DES_ADDR  -----------------------------------
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos                     0                                                         /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk                     (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos)       /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */
+
+// -------------------------------  ETHERNET_DMA_TRANS_DES_ADDR  ----------------------------------
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos                   0                                                         /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk                   (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos)     /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */
+
+// ------------------------------------  ETHERNET_DMA_STAT  ---------------------------------------
+#define ETHERNET_DMA_STAT_TI_Pos                              0                                                         /*!< ETHERNET DMA_STAT: TI Position      */
+#define ETHERNET_DMA_STAT_TI_Msk                              (0x01UL << ETHERNET_DMA_STAT_TI_Pos)                      /*!< ETHERNET DMA_STAT: TI Mask          */
+#define ETHERNET_DMA_STAT_TPS_Pos                             1                                                         /*!< ETHERNET DMA_STAT: TPS Position     */
+#define ETHERNET_DMA_STAT_TPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_TPS_Pos)                     /*!< ETHERNET DMA_STAT: TPS Mask         */
+#define ETHERNET_DMA_STAT_TU_Pos                              2                                                         /*!< ETHERNET DMA_STAT: TU Position      */
+#define ETHERNET_DMA_STAT_TU_Msk                              (0x01UL << ETHERNET_DMA_STAT_TU_Pos)                      /*!< ETHERNET DMA_STAT: TU Mask          */
+#define ETHERNET_DMA_STAT_TJT_Pos                             3                                                         /*!< ETHERNET DMA_STAT: TJT Position     */
+#define ETHERNET_DMA_STAT_TJT_Msk                             (0x01UL << ETHERNET_DMA_STAT_TJT_Pos)                     /*!< ETHERNET DMA_STAT: TJT Mask         */
+#define ETHERNET_DMA_STAT_OVF_Pos                             4                                                         /*!< ETHERNET DMA_STAT: OVF Position     */
+#define ETHERNET_DMA_STAT_OVF_Msk                             (0x01UL << ETHERNET_DMA_STAT_OVF_Pos)                     /*!< ETHERNET DMA_STAT: OVF Mask         */
+#define ETHERNET_DMA_STAT_UNF_Pos                             5                                                         /*!< ETHERNET DMA_STAT: UNF Position     */
+#define ETHERNET_DMA_STAT_UNF_Msk                             (0x01UL << ETHERNET_DMA_STAT_UNF_Pos)                     /*!< ETHERNET DMA_STAT: UNF Mask         */
+#define ETHERNET_DMA_STAT_RI_Pos                              6                                                         /*!< ETHERNET DMA_STAT: RI Position      */
+#define ETHERNET_DMA_STAT_RI_Msk                              (0x01UL << ETHERNET_DMA_STAT_RI_Pos)                      /*!< ETHERNET DMA_STAT: RI Mask          */
+#define ETHERNET_DMA_STAT_RU_Pos                              7                                                         /*!< ETHERNET DMA_STAT: RU Position      */
+#define ETHERNET_DMA_STAT_RU_Msk                              (0x01UL << ETHERNET_DMA_STAT_RU_Pos)                      /*!< ETHERNET DMA_STAT: RU Mask          */
+#define ETHERNET_DMA_STAT_RPS_Pos                             8                                                         /*!< ETHERNET DMA_STAT: RPS Position     */
+#define ETHERNET_DMA_STAT_RPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_RPS_Pos)                     /*!< ETHERNET DMA_STAT: RPS Mask         */
+#define ETHERNET_DMA_STAT_RWT_Pos                             9                                                         /*!< ETHERNET DMA_STAT: RWT Position     */
+#define ETHERNET_DMA_STAT_RWT_Msk                             (0x01UL << ETHERNET_DMA_STAT_RWT_Pos)                     /*!< ETHERNET DMA_STAT: RWT Mask         */
+#define ETHERNET_DMA_STAT_ETI_Pos                             10                                                        /*!< ETHERNET DMA_STAT: ETI Position     */
+#define ETHERNET_DMA_STAT_ETI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ETI_Pos)                     /*!< ETHERNET DMA_STAT: ETI Mask         */
+#define ETHERNET_DMA_STAT_FBI_Pos                             13                                                        /*!< ETHERNET DMA_STAT: FBI Position     */
+#define ETHERNET_DMA_STAT_FBI_Msk                             (0x01UL << ETHERNET_DMA_STAT_FBI_Pos)                     /*!< ETHERNET DMA_STAT: FBI Mask         */
+#define ETHERNET_DMA_STAT_ERI_Pos                             14                                                        /*!< ETHERNET DMA_STAT: ERI Position     */
+#define ETHERNET_DMA_STAT_ERI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ERI_Pos)                     /*!< ETHERNET DMA_STAT: ERI Mask         */
+#define ETHERNET_DMA_STAT_AIE_Pos                             15                                                        /*!< ETHERNET DMA_STAT: AIE Position     */
+#define ETHERNET_DMA_STAT_AIE_Msk                             (0x01UL << ETHERNET_DMA_STAT_AIE_Pos)                     /*!< ETHERNET DMA_STAT: AIE Mask         */
+#define ETHERNET_DMA_STAT_NIS_Pos                             16                                                        /*!< ETHERNET DMA_STAT: NIS Position     */
+#define ETHERNET_DMA_STAT_NIS_Msk                             (0x01UL << ETHERNET_DMA_STAT_NIS_Pos)                     /*!< ETHERNET DMA_STAT: NIS Mask         */
+
+// ----------------------------------  ETHERNET_DMA_OP_MODE  --------------------------------------
+#define ETHERNET_DMA_OP_MODE_SR_Pos                           1                                                         /*!< ETHERNET DMA_OP_MODE: SR Position   */
+#define ETHERNET_DMA_OP_MODE_SR_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos)                   /*!< ETHERNET DMA_OP_MODE: SR Mask       */
+#define ETHERNET_DMA_OP_MODE_OSF_Pos                          2                                                         /*!< ETHERNET DMA_OP_MODE: OSF Position  */
+#define ETHERNET_DMA_OP_MODE_OSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: OSF Mask      */
+#define ETHERNET_DMA_OP_MODE_RTC_Pos                          3                                                         /*!< ETHERNET DMA_OP_MODE: RTC Position  */
+#define ETHERNET_DMA_OP_MODE_RTC_Msk                          (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: RTC Mask      */
+#define ETHERNET_DMA_OP_MODE_FUF_Pos                          6                                                         /*!< ETHERNET DMA_OP_MODE: FUF Position  */
+#define ETHERNET_DMA_OP_MODE_FUF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FUF Mask      */
+#define ETHERNET_DMA_OP_MODE_FEF_Pos                          7                                                         /*!< ETHERNET DMA_OP_MODE: FEF Position  */
+#define ETHERNET_DMA_OP_MODE_FEF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FEF Mask      */
+#define ETHERNET_DMA_OP_MODE_ST_Pos                           13                                                        /*!< ETHERNET DMA_OP_MODE: ST Position   */
+#define ETHERNET_DMA_OP_MODE_ST_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos)                   /*!< ETHERNET DMA_OP_MODE: ST Mask       */
+#define ETHERNET_DMA_OP_MODE_TTC_Pos                          14                                                        /*!< ETHERNET DMA_OP_MODE: TTC Position  */
+#define ETHERNET_DMA_OP_MODE_TTC_Msk                          (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: TTC Mask      */
+#define ETHERNET_DMA_OP_MODE_FTF_Pos                          20                                                        /*!< ETHERNET DMA_OP_MODE: FTF Position  */
+#define ETHERNET_DMA_OP_MODE_FTF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FTF Mask      */
+#define ETHERNET_DMA_OP_MODE_TSF_Pos                          21                                                        /*!< ETHERNET DMA_OP_MODE: TSF Position  */
+#define ETHERNET_DMA_OP_MODE_TSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: TSF Mask      */
+#define ETHERNET_DMA_OP_MODE_DFF_Pos                          24                                                        /*!< ETHERNET DMA_OP_MODE: DFF Position  */
+#define ETHERNET_DMA_OP_MODE_DFF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos)                  /*!< ETHERNET DMA_OP_MODE: DFF Mask      */
+#define ETHERNET_DMA_OP_MODE_RSF_Pos                          25                                                        /*!< ETHERNET DMA_OP_MODE: RSF Position  */
+#define ETHERNET_DMA_OP_MODE_RSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: RSF Mask      */
+#define ETHERNET_DMA_OP_MODE_DT_Pos                           26                                                        /*!< ETHERNET DMA_OP_MODE: DT Position   */
+#define ETHERNET_DMA_OP_MODE_DT_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos)                   /*!< ETHERNET DMA_OP_MODE: DT Mask       */
+
+// -----------------------------------  ETHERNET_DMA_INT_EN  --------------------------------------
+#define ETHERNET_DMA_INT_EN_TIE_Pos                           0                                                         /*!< ETHERNET DMA_INT_EN: TIE Position   */
+#define ETHERNET_DMA_INT_EN_TIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos)                   /*!< ETHERNET DMA_INT_EN: TIE Mask       */
+#define ETHERNET_DMA_INT_EN_TSE_Pos                           1                                                         /*!< ETHERNET DMA_INT_EN: TSE Position   */
+#define ETHERNET_DMA_INT_EN_TSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos)                   /*!< ETHERNET DMA_INT_EN: TSE Mask       */
+#define ETHERNET_DMA_INT_EN_TUE_Pos                           2                                                         /*!< ETHERNET DMA_INT_EN: TUE Position   */
+#define ETHERNET_DMA_INT_EN_TUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos)                   /*!< ETHERNET DMA_INT_EN: TUE Mask       */
+#define ETHERNET_DMA_INT_EN_TJE_Pos                           3                                                         /*!< ETHERNET DMA_INT_EN: TJE Position   */
+#define ETHERNET_DMA_INT_EN_TJE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos)                   /*!< ETHERNET DMA_INT_EN: TJE Mask       */
+#define ETHERNET_DMA_INT_EN_OVE_Pos                           4                                                         /*!< ETHERNET DMA_INT_EN: OVE Position   */
+#define ETHERNET_DMA_INT_EN_OVE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos)                   /*!< ETHERNET DMA_INT_EN: OVE Mask       */
+#define ETHERNET_DMA_INT_EN_UNE_Pos                           5                                                         /*!< ETHERNET DMA_INT_EN: UNE Position   */
+#define ETHERNET_DMA_INT_EN_UNE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos)                   /*!< ETHERNET DMA_INT_EN: UNE Mask       */
+#define ETHERNET_DMA_INT_EN_RIE_Pos                           6                                                         /*!< ETHERNET DMA_INT_EN: RIE Position   */
+#define ETHERNET_DMA_INT_EN_RIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos)                   /*!< ETHERNET DMA_INT_EN: RIE Mask       */
+#define ETHERNET_DMA_INT_EN_RUE_Pos                           7                                                         /*!< ETHERNET DMA_INT_EN: RUE Position   */
+#define ETHERNET_DMA_INT_EN_RUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos)                   /*!< ETHERNET DMA_INT_EN: RUE Mask       */
+#define ETHERNET_DMA_INT_EN_RSE_Pos                           8                                                         /*!< ETHERNET DMA_INT_EN: RSE Position   */
+#define ETHERNET_DMA_INT_EN_RSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos)                   /*!< ETHERNET DMA_INT_EN: RSE Mask       */
+#define ETHERNET_DMA_INT_EN_RWE_Pos                           9                                                         /*!< ETHERNET DMA_INT_EN: RWE Position   */
+#define ETHERNET_DMA_INT_EN_RWE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos)                   /*!< ETHERNET DMA_INT_EN: RWE Mask       */
+#define ETHERNET_DMA_INT_EN_ETE_Pos                           10                                                        /*!< ETHERNET DMA_INT_EN: ETE Position   */
+#define ETHERNET_DMA_INT_EN_ETE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos)                   /*!< ETHERNET DMA_INT_EN: ETE Mask       */
+#define ETHERNET_DMA_INT_EN_FBE_Pos                           13                                                        /*!< ETHERNET DMA_INT_EN: FBE Position   */
+#define ETHERNET_DMA_INT_EN_FBE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos)                   /*!< ETHERNET DMA_INT_EN: FBE Mask       */
+#define ETHERNET_DMA_INT_EN_ERE_Pos                           14                                                        /*!< ETHERNET DMA_INT_EN: ERE Position   */
+#define ETHERNET_DMA_INT_EN_ERE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos)                   /*!< ETHERNET DMA_INT_EN: ERE Mask       */
+#define ETHERNET_DMA_INT_EN_AIE_Pos                           15                                                        /*!< ETHERNET DMA_INT_EN: AIE Position   */
+#define ETHERNET_DMA_INT_EN_AIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos)                   /*!< ETHERNET DMA_INT_EN: AIE Mask       */
+#define ETHERNET_DMA_INT_EN_NIE_Pos                           16                                                        /*!< ETHERNET DMA_INT_EN: NIE Position   */
+#define ETHERNET_DMA_INT_EN_NIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos)                   /*!< ETHERNET DMA_INT_EN: NIE Mask       */
+
+// ---------------------------------  ETHERNET_DMA_MFRM_BUFOF  ------------------------------------
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos                       0                                                         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk                       (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask   */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos                        16                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask    */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos                       17                                                        /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk                       (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask   */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos                        28                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask    */
+
+// --------------------------------  ETHERNET_DMA_REC_INT_WDT  ------------------------------------
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos                     0                                                         /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk                     (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos)       /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */
+
+// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_DES  ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */
+
+// ------------------------------  ETHERNET_DMA_CURHOST_REC_DES  ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos)    /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */
+
+// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_BUF  ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */
+
+// ------------------------------  ETHERNET_DMA_CURHOST_REC_BUF  ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos)    /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                ATIMER Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------  ATIMER_DOWNCOUNTER  ---------------------------------------
+#define ATIMER_DOWNCOUNTER_CVAL_Pos                           0                                                         /*!< ATIMER DOWNCOUNTER: CVAL Position   */
+#define ATIMER_DOWNCOUNTER_CVAL_Msk                           (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos)             /*!< ATIMER DOWNCOUNTER: CVAL Mask       */
+
+// --------------------------------------  ATIMER_PRESET  -----------------------------------------
+#define ATIMER_PRESET_PRESETVAL_Pos                           0                                                         /*!< ATIMER PRESET: PRESETVAL Position   */
+#define ATIMER_PRESET_PRESETVAL_Msk                           (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos)             /*!< ATIMER PRESET: PRESETVAL Mask       */
+
+// --------------------------------------  ATIMER_CLR_EN  -----------------------------------------
+#define ATIMER_CLR_EN_CLR_EN_Pos                              0                                                         /*!< ATIMER CLR_EN: CLR_EN Position      */
+#define ATIMER_CLR_EN_CLR_EN_Msk                              (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos)                      /*!< ATIMER CLR_EN: CLR_EN Mask          */
+
+// --------------------------------------  ATIMER_SET_EN  -----------------------------------------
+#define ATIMER_SET_EN_SET_EN_Pos                              0                                                         /*!< ATIMER SET_EN: SET_EN Position      */
+#define ATIMER_SET_EN_SET_EN_Msk                              (0x01UL << ATIMER_SET_EN_SET_EN_Pos)                      /*!< ATIMER SET_EN: SET_EN Mask          */
+
+// --------------------------------------  ATIMER_STATUS  -----------------------------------------
+#define ATIMER_STATUS_STAT_Pos                                0                                                         /*!< ATIMER STATUS: STAT Position        */
+#define ATIMER_STATUS_STAT_Msk                                (0x01UL << ATIMER_STATUS_STAT_Pos)                        /*!< ATIMER STATUS: STAT Mask            */
+
+// --------------------------------------  ATIMER_ENABLE  -----------------------------------------
+#define ATIMER_ENABLE_EN_Pos                                  0                                                         /*!< ATIMER ENABLE: EN Position          */
+#define ATIMER_ENABLE_EN_Msk                                  (0x01UL << ATIMER_ENABLE_EN_Pos)                          /*!< ATIMER ENABLE: EN Mask              */
+
+// -------------------------------------  ATIMER_CLR_STAT  ----------------------------------------
+#define ATIMER_CLR_STAT_CSTAT_Pos                             0                                                         /*!< ATIMER CLR_STAT: CSTAT Position     */
+#define ATIMER_CLR_STAT_CSTAT_Msk                             (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos)                     /*!< ATIMER CLR_STAT: CSTAT Mask         */
+
+// -------------------------------------  ATIMER_SET_STAT  ----------------------------------------
+#define ATIMER_SET_STAT_SSTAT_Pos                             0                                                         /*!< ATIMER SET_STAT: SSTAT Position     */
+#define ATIMER_SET_STAT_SSTAT_Msk                             (0x01UL << ATIMER_SET_STAT_SSTAT_Pos)                     /*!< ATIMER SET_STAT: SSTAT Mask         */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                REGFILE Position & Mask                               -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------  REGFILE_REGFILE0  ----------------------------------------
+#define REGFILE_REGFILE0_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE0: REGVAL Position   */
+#define REGFILE_REGFILE0_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos)             /*!< REGFILE REGFILE0: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE1  ----------------------------------------
+#define REGFILE_REGFILE1_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE1: REGVAL Position   */
+#define REGFILE_REGFILE1_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos)             /*!< REGFILE REGFILE1: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE2  ----------------------------------------
+#define REGFILE_REGFILE2_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE2: REGVAL Position   */
+#define REGFILE_REGFILE2_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos)             /*!< REGFILE REGFILE2: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE3  ----------------------------------------
+#define REGFILE_REGFILE3_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE3: REGVAL Position   */
+#define REGFILE_REGFILE3_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos)             /*!< REGFILE REGFILE3: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE4  ----------------------------------------
+#define REGFILE_REGFILE4_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE4: REGVAL Position   */
+#define REGFILE_REGFILE4_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos)             /*!< REGFILE REGFILE4: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE5  ----------------------------------------
+#define REGFILE_REGFILE5_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE5: REGVAL Position   */
+#define REGFILE_REGFILE5_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos)             /*!< REGFILE REGFILE5: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE6  ----------------------------------------
+#define REGFILE_REGFILE6_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE6: REGVAL Position   */
+#define REGFILE_REGFILE6_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos)             /*!< REGFILE REGFILE6: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE7  ----------------------------------------
+#define REGFILE_REGFILE7_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE7: REGVAL Position   */
+#define REGFILE_REGFILE7_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos)             /*!< REGFILE REGFILE7: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE8  ----------------------------------------
+#define REGFILE_REGFILE8_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE8: REGVAL Position   */
+#define REGFILE_REGFILE8_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos)             /*!< REGFILE REGFILE8: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE9  ----------------------------------------
+#define REGFILE_REGFILE9_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE9: REGVAL Position   */
+#define REGFILE_REGFILE9_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos)             /*!< REGFILE REGFILE9: REGVAL Mask       */
+
+// ------------------------------------  REGFILE_REGFILE10  ---------------------------------------
+#define REGFILE_REGFILE10_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE10: REGVAL Position  */
+#define REGFILE_REGFILE10_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos)            /*!< REGFILE REGFILE10: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE11  ---------------------------------------
+#define REGFILE_REGFILE11_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE11: REGVAL Position  */
+#define REGFILE_REGFILE11_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos)            /*!< REGFILE REGFILE11: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE12  ---------------------------------------
+#define REGFILE_REGFILE12_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE12: REGVAL Position  */
+#define REGFILE_REGFILE12_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos)            /*!< REGFILE REGFILE12: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE13  ---------------------------------------
+#define REGFILE_REGFILE13_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE13: REGVAL Position  */
+#define REGFILE_REGFILE13_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos)            /*!< REGFILE REGFILE13: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE14  ---------------------------------------
+#define REGFILE_REGFILE14_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE14: REGVAL Position  */
+#define REGFILE_REGFILE14_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos)            /*!< REGFILE REGFILE14: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE15  ---------------------------------------
+#define REGFILE_REGFILE15_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE15: REGVAL Position  */
+#define REGFILE_REGFILE15_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos)            /*!< REGFILE REGFILE15: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE16  ---------------------------------------
+#define REGFILE_REGFILE16_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE16: REGVAL Position  */
+#define REGFILE_REGFILE16_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos)            /*!< REGFILE REGFILE16: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE17  ---------------------------------------
+#define REGFILE_REGFILE17_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE17: REGVAL Position  */
+#define REGFILE_REGFILE17_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos)            /*!< REGFILE REGFILE17: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE18  ---------------------------------------
+#define REGFILE_REGFILE18_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE18: REGVAL Position  */
+#define REGFILE_REGFILE18_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos)            /*!< REGFILE REGFILE18: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE19  ---------------------------------------
+#define REGFILE_REGFILE19_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE19: REGVAL Position  */
+#define REGFILE_REGFILE19_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos)            /*!< REGFILE REGFILE19: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE20  ---------------------------------------
+#define REGFILE_REGFILE20_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE20: REGVAL Position  */
+#define REGFILE_REGFILE20_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos)            /*!< REGFILE REGFILE20: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE21  ---------------------------------------
+#define REGFILE_REGFILE21_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE21: REGVAL Position  */
+#define REGFILE_REGFILE21_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos)            /*!< REGFILE REGFILE21: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE22  ---------------------------------------
+#define REGFILE_REGFILE22_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE22: REGVAL Position  */
+#define REGFILE_REGFILE22_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos)            /*!< REGFILE REGFILE22: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE23  ---------------------------------------
+#define REGFILE_REGFILE23_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE23: REGVAL Position  */
+#define REGFILE_REGFILE23_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos)            /*!< REGFILE REGFILE23: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE24  ---------------------------------------
+#define REGFILE_REGFILE24_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE24: REGVAL Position  */
+#define REGFILE_REGFILE24_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos)            /*!< REGFILE REGFILE24: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE25  ---------------------------------------
+#define REGFILE_REGFILE25_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE25: REGVAL Position  */
+#define REGFILE_REGFILE25_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos)            /*!< REGFILE REGFILE25: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE26  ---------------------------------------
+#define REGFILE_REGFILE26_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE26: REGVAL Position  */
+#define REGFILE_REGFILE26_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos)            /*!< REGFILE REGFILE26: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE27  ---------------------------------------
+#define REGFILE_REGFILE27_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE27: REGVAL Position  */
+#define REGFILE_REGFILE27_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos)            /*!< REGFILE REGFILE27: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE28  ---------------------------------------
+#define REGFILE_REGFILE28_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE28: REGVAL Position  */
+#define REGFILE_REGFILE28_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos)            /*!< REGFILE REGFILE28: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE29  ---------------------------------------
+#define REGFILE_REGFILE29_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE29: REGVAL Position  */
+#define REGFILE_REGFILE29_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos)            /*!< REGFILE REGFILE29: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE30  ---------------------------------------
+#define REGFILE_REGFILE30_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE30: REGVAL Position  */
+#define REGFILE_REGFILE30_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos)            /*!< REGFILE REGFILE30: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE31  ---------------------------------------
+#define REGFILE_REGFILE31_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE31: REGVAL Position  */
+#define REGFILE_REGFILE31_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos)            /*!< REGFILE REGFILE31: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE32  ---------------------------------------
+#define REGFILE_REGFILE32_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE32: REGVAL Position  */
+#define REGFILE_REGFILE32_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos)            /*!< REGFILE REGFILE32: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE33  ---------------------------------------
+#define REGFILE_REGFILE33_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE33: REGVAL Position  */
+#define REGFILE_REGFILE33_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos)            /*!< REGFILE REGFILE33: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE34  ---------------------------------------
+#define REGFILE_REGFILE34_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE34: REGVAL Position  */
+#define REGFILE_REGFILE34_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos)            /*!< REGFILE REGFILE34: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE35  ---------------------------------------
+#define REGFILE_REGFILE35_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE35: REGVAL Position  */
+#define REGFILE_REGFILE35_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos)            /*!< REGFILE REGFILE35: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE36  ---------------------------------------
+#define REGFILE_REGFILE36_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE36: REGVAL Position  */
+#define REGFILE_REGFILE36_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos)            /*!< REGFILE REGFILE36: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE37  ---------------------------------------
+#define REGFILE_REGFILE37_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE37: REGVAL Position  */
+#define REGFILE_REGFILE37_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos)            /*!< REGFILE REGFILE37: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE38  ---------------------------------------
+#define REGFILE_REGFILE38_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE38: REGVAL Position  */
+#define REGFILE_REGFILE38_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos)            /*!< REGFILE REGFILE38: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE39  ---------------------------------------
+#define REGFILE_REGFILE39_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE39: REGVAL Position  */
+#define REGFILE_REGFILE39_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos)            /*!< REGFILE REGFILE39: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE40  ---------------------------------------
+#define REGFILE_REGFILE40_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE40: REGVAL Position  */
+#define REGFILE_REGFILE40_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos)            /*!< REGFILE REGFILE40: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE41  ---------------------------------------
+#define REGFILE_REGFILE41_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE41: REGVAL Position  */
+#define REGFILE_REGFILE41_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos)            /*!< REGFILE REGFILE41: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE42  ---------------------------------------
+#define REGFILE_REGFILE42_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE42: REGVAL Position  */
+#define REGFILE_REGFILE42_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos)            /*!< REGFILE REGFILE42: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE43  ---------------------------------------
+#define REGFILE_REGFILE43_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE43: REGVAL Position  */
+#define REGFILE_REGFILE43_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos)            /*!< REGFILE REGFILE43: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE44  ---------------------------------------
+#define REGFILE_REGFILE44_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE44: REGVAL Position  */
+#define REGFILE_REGFILE44_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos)            /*!< REGFILE REGFILE44: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE45  ---------------------------------------
+#define REGFILE_REGFILE45_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE45: REGVAL Position  */
+#define REGFILE_REGFILE45_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos)            /*!< REGFILE REGFILE45: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE46  ---------------------------------------
+#define REGFILE_REGFILE46_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE46: REGVAL Position  */
+#define REGFILE_REGFILE46_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos)            /*!< REGFILE REGFILE46: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE47  ---------------------------------------
+#define REGFILE_REGFILE47_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE47: REGVAL Position  */
+#define REGFILE_REGFILE47_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos)            /*!< REGFILE REGFILE47: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE48  ---------------------------------------
+#define REGFILE_REGFILE48_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE48: REGVAL Position  */
+#define REGFILE_REGFILE48_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos)            /*!< REGFILE REGFILE48: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE49  ---------------------------------------
+#define REGFILE_REGFILE49_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE49: REGVAL Position  */
+#define REGFILE_REGFILE49_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos)            /*!< REGFILE REGFILE49: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE50  ---------------------------------------
+#define REGFILE_REGFILE50_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE50: REGVAL Position  */
+#define REGFILE_REGFILE50_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos)            /*!< REGFILE REGFILE50: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE51  ---------------------------------------
+#define REGFILE_REGFILE51_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE51: REGVAL Position  */
+#define REGFILE_REGFILE51_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos)            /*!< REGFILE REGFILE51: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE52  ---------------------------------------
+#define REGFILE_REGFILE52_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE52: REGVAL Position  */
+#define REGFILE_REGFILE52_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos)            /*!< REGFILE REGFILE52: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE53  ---------------------------------------
+#define REGFILE_REGFILE53_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE53: REGVAL Position  */
+#define REGFILE_REGFILE53_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos)            /*!< REGFILE REGFILE53: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE54  ---------------------------------------
+#define REGFILE_REGFILE54_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE54: REGVAL Position  */
+#define REGFILE_REGFILE54_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos)            /*!< REGFILE REGFILE54: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE55  ---------------------------------------
+#define REGFILE_REGFILE55_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE55: REGVAL Position  */
+#define REGFILE_REGFILE55_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos)            /*!< REGFILE REGFILE55: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE56  ---------------------------------------
+#define REGFILE_REGFILE56_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE56: REGVAL Position  */
+#define REGFILE_REGFILE56_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos)            /*!< REGFILE REGFILE56: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE57  ---------------------------------------
+#define REGFILE_REGFILE57_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE57: REGVAL Position  */
+#define REGFILE_REGFILE57_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos)            /*!< REGFILE REGFILE57: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE58  ---------------------------------------
+#define REGFILE_REGFILE58_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE58: REGVAL Position  */
+#define REGFILE_REGFILE58_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos)            /*!< REGFILE REGFILE58: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE59  ---------------------------------------
+#define REGFILE_REGFILE59_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE59: REGVAL Position  */
+#define REGFILE_REGFILE59_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos)            /*!< REGFILE REGFILE59: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE60  ---------------------------------------
+#define REGFILE_REGFILE60_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE60: REGVAL Position  */
+#define REGFILE_REGFILE60_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos)            /*!< REGFILE REGFILE60: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE61  ---------------------------------------
+#define REGFILE_REGFILE61_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE61: REGVAL Position  */
+#define REGFILE_REGFILE61_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos)            /*!< REGFILE REGFILE61: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE62  ---------------------------------------
+#define REGFILE_REGFILE62_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE62: REGVAL Position  */
+#define REGFILE_REGFILE62_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos)            /*!< REGFILE REGFILE62: REGVAL Mask      */
+
+// ------------------------------------  REGFILE_REGFILE63  ---------------------------------------
+#define REGFILE_REGFILE63_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE63: REGVAL Position  */
+#define REGFILE_REGFILE63_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos)            /*!< REGFILE REGFILE63: REGVAL Mask      */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  PMC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------  PMC_PD0_SLEEP0_HW_ENA  -------------------------------------
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos                  0                                                         /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk                  (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos)          /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */
+
+// -----------------------------------  PMC_PD0_SLEEP0_MODE  --------------------------------------
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos                     0                                                         /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk                     (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos)       /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 CREG Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  CREG_IRCTRM  ------------------------------------------
+#define CREG_IRCTRM_TRM_Pos                                   0                                                         /*!< CREG IRCTRM: TRM Position           */
+#define CREG_IRCTRM_TRM_Msk                                   (0x00000fffUL << CREG_IRCTRM_TRM_Pos)                     /*!< CREG IRCTRM: TRM Mask               */
+
+// ---------------------------------------  CREG_CREG0  -------------------------------------------
+#define CREG_CREG0_EN1KHZ_Pos                                 0                                                         /*!< CREG CREG0: EN1KHZ Position         */
+#define CREG_CREG0_EN1KHZ_Msk                                 (0x01UL << CREG_CREG0_EN1KHZ_Pos)                         /*!< CREG CREG0: EN1KHZ Mask             */
+#define CREG_CREG0_EN32KHZ_Pos                                1                                                         /*!< CREG CREG0: EN32KHZ Position        */
+#define CREG_CREG0_EN32KHZ_Msk                                (0x01UL << CREG_CREG0_EN32KHZ_Pos)                        /*!< CREG CREG0: EN32KHZ Mask            */
+#define CREG_CREG0_RESET32KHZ_Pos                             2                                                         /*!< CREG CREG0: RESET32KHZ Position     */
+#define CREG_CREG0_RESET32KHZ_Msk                             (0x01UL << CREG_CREG0_RESET32KHZ_Pos)                     /*!< CREG CREG0: RESET32KHZ Mask         */
+#define CREG_CREG0_32KHZPD_Pos                                3                                                         /*!< CREG CREG0: 32KHZPD Position        */
+#define CREG_CREG0_32KHZPD_Msk                                (0x01UL << CREG_CREG0_32KHZPD_Pos)                        /*!< CREG CREG0: 32KHZPD Mask            */
+#define CREG_CREG0_USB0PHY_Pos                                5                                                         /*!< CREG CREG0: USB0PHY Position        */
+#define CREG_CREG0_USB0PHY_Msk                                (0x01UL << CREG_CREG0_USB0PHY_Pos)                        /*!< CREG CREG0: USB0PHY Mask            */
+#define CREG_CREG0_ALARMCTRL_Pos                              6                                                         /*!< CREG CREG0: ALARMCTRL Position      */
+#define CREG_CREG0_ALARMCTRL_Msk                              (0x03UL << CREG_CREG0_ALARMCTRL_Pos)                      /*!< CREG CREG0: ALARMCTRL Mask          */
+#define CREG_CREG0_BODLVL1_Pos                                8                                                         /*!< CREG CREG0: BODLVL1 Position        */
+#define CREG_CREG0_BODLVL1_Msk                                (0x03UL << CREG_CREG0_BODLVL1_Pos)                        /*!< CREG CREG0: BODLVL1 Mask            */
+#define CREG_CREG0_BODLVL2_Pos                                10                                                        /*!< CREG CREG0: BODLVL2 Position        */
+#define CREG_CREG0_BODLVL2_Msk                                (0x03UL << CREG_CREG0_BODLVL2_Pos)                        /*!< CREG CREG0: BODLVL2 Mask            */
+#define CREG_CREG0_WAKEUP0CTRL_Pos                            14                                                        /*!< CREG CREG0: WAKEUP0CTRL Position    */
+#define CREG_CREG0_WAKEUP0CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos)                    /*!< CREG CREG0: WAKEUP0CTRL Mask        */
+#define CREG_CREG0_WAKEUP1CTRL_Pos                            16                                                        /*!< CREG CREG0: WAKEUP1CTRL Position    */
+#define CREG_CREG0_WAKEUP1CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos)                    /*!< CREG CREG0: WAKEUP1CTRL Mask        */
+
+// --------------------------------------  CREG_M4MEMMAP  -----------------------------------------
+#define CREG_M4MEMMAP_M4MAP_Pos                               12                                                        /*!< CREG M4MEMMAP: M4MAP Position       */
+#define CREG_M4MEMMAP_M4MAP_Msk                               (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos)                 /*!< CREG M4MEMMAP: M4MAP Mask           */
+
+// ---------------------------------------  CREG_CREG5  -------------------------------------------
+#define CREG_CREG5_M4TAPSEL_Pos                               6                                                         /*!< CREG CREG5: M4TAPSEL Position       */
+#define CREG_CREG5_M4TAPSEL_Msk                               (0x01UL << CREG_CREG5_M4TAPSEL_Pos)                       /*!< CREG CREG5: M4TAPSEL Mask           */
+
+// ---------------------------------------  CREG_DMAMUX  ------------------------------------------
+#define CREG_DMAMUX_DMAMUXCH0_Pos                             0                                                         /*!< CREG DMAMUX: DMAMUXCH0 Position     */
+#define CREG_DMAMUX_DMAMUXCH0_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos)                     /*!< CREG DMAMUX: DMAMUXCH0 Mask         */
+#define CREG_DMAMUX_DMAMUXCH1_Pos                             2                                                         /*!< CREG DMAMUX: DMAMUXCH1 Position     */
+#define CREG_DMAMUX_DMAMUXCH1_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos)                     /*!< CREG DMAMUX: DMAMUXCH1 Mask         */
+#define CREG_DMAMUX_DMAMUXCH2_Pos                             4                                                         /*!< CREG DMAMUX: DMAMUXCH2 Position     */
+#define CREG_DMAMUX_DMAMUXCH2_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos)                     /*!< CREG DMAMUX: DMAMUXCH2 Mask         */
+#define CREG_DMAMUX_DMAMUXCH3_Pos                             6                                                         /*!< CREG DMAMUX: DMAMUXCH3 Position     */
+#define CREG_DMAMUX_DMAMUXCH3_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos)                     /*!< CREG DMAMUX: DMAMUXCH3 Mask         */
+#define CREG_DMAMUX_DMAMUXCH4_Pos                             8                                                         /*!< CREG DMAMUX: DMAMUXCH4 Position     */
+#define CREG_DMAMUX_DMAMUXCH4_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos)                     /*!< CREG DMAMUX: DMAMUXCH4 Mask         */
+#define CREG_DMAMUX_DMAMUXCH5_Pos                             10                                                        /*!< CREG DMAMUX: DMAMUXCH5 Position     */
+#define CREG_DMAMUX_DMAMUXCH5_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos)                     /*!< CREG DMAMUX: DMAMUXCH5 Mask         */
+#define CREG_DMAMUX_DMAMUXCH6_Pos                             12                                                        /*!< CREG DMAMUX: DMAMUXCH6 Position     */
+#define CREG_DMAMUX_DMAMUXCH6_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos)                     /*!< CREG DMAMUX: DMAMUXCH6 Mask         */
+#define CREG_DMAMUX_DMAMUXCH7_Pos                             14                                                        /*!< CREG DMAMUX: DMAMUXCH7 Position     */
+#define CREG_DMAMUX_DMAMUXCH7_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos)                     /*!< CREG DMAMUX: DMAMUXCH7 Mask         */
+#define CREG_DMAMUX_DMAMUXCH8_Pos                             16                                                        /*!< CREG DMAMUX: DMAMUXCH8 Position     */
+#define CREG_DMAMUX_DMAMUXCH8_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos)                     /*!< CREG DMAMUX: DMAMUXCH8 Mask         */
+#define CREG_DMAMUX_DMAMUXCH9_Pos                             18                                                        /*!< CREG DMAMUX: DMAMUXCH9 Position     */
+#define CREG_DMAMUX_DMAMUXCH9_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos)                     /*!< CREG DMAMUX: DMAMUXCH9 Mask         */
+#define CREG_DMAMUX_DMAMUXCH10_Pos                            20                                                        /*!< CREG DMAMUX: DMAMUXCH10 Position    */
+#define CREG_DMAMUX_DMAMUXCH10_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos)                    /*!< CREG DMAMUX: DMAMUXCH10 Mask        */
+#define CREG_DMAMUX_DMAMUXCH11_Pos                            22                                                        /*!< CREG DMAMUX: DMAMUXCH11 Position    */
+#define CREG_DMAMUX_DMAMUXCH11_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos)                    /*!< CREG DMAMUX: DMAMUXCH11 Mask        */
+#define CREG_DMAMUX_DMAMUXCH12_Pos                            24                                                        /*!< CREG DMAMUX: DMAMUXCH12 Position    */
+#define CREG_DMAMUX_DMAMUXCH12_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos)                    /*!< CREG DMAMUX: DMAMUXCH12 Mask        */
+#define CREG_DMAMUX_DMAMUXCH13_Pos                            26                                                        /*!< CREG DMAMUX: DMAMUXCH13 Position    */
+#define CREG_DMAMUX_DMAMUXCH13_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos)                    /*!< CREG DMAMUX: DMAMUXCH13 Mask        */
+#define CREG_DMAMUX_DMAMUXCH14_Pos                            28                                                        /*!< CREG DMAMUX: DMAMUXCH14 Position    */
+#define CREG_DMAMUX_DMAMUXCH14_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos)                    /*!< CREG DMAMUX: DMAMUXCH14 Mask        */
+#define CREG_DMAMUX_DMAMUXCH15_Pos                            30                                                        /*!< CREG DMAMUX: DMAMUXCH15 Position    */
+#define CREG_DMAMUX_DMAMUXCH15_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos)                    /*!< CREG DMAMUX: DMAMUXCH15 Mask        */
+
+// ---------------------------------------  CREG_ETBCFG  ------------------------------------------
+#define CREG_ETBCFG_ETB_Pos                                   0                                                         /*!< CREG ETBCFG: ETB Position           */
+#define CREG_ETBCFG_ETB_Msk                                   (0x01UL << CREG_ETBCFG_ETB_Pos)                           /*!< CREG ETBCFG: ETB Mask               */
+
+// ---------------------------------------  CREG_CREG6  -------------------------------------------
+#define CREG_CREG6_ETHMODE_Pos                                0                                                         /*!< CREG CREG6: ETHMODE Position        */
+#define CREG_CREG6_ETHMODE_Msk                                (0x07UL << CREG_CREG6_ETHMODE_Pos)                        /*!< CREG CREG6: ETHMODE Mask            */
+#define CREG_CREG6_TIMCTRL_Pos                                4                                                         /*!< CREG CREG6: TIMCTRL Position        */
+#define CREG_CREG6_TIMCTRL_Msk                                (0x01UL << CREG_CREG6_TIMCTRL_Pos)                        /*!< CREG CREG6: TIMCTRL Mask            */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos                     12                                                        /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos                     13                                                        /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos                     14                                                        /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos                     15                                                        /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_EMC_CLK_SEL_Pos                            16                                                        /*!< CREG CREG6: EMC_CLK_SEL Position    */
+#define CREG_CREG6_EMC_CLK_SEL_Msk                            (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos)                    /*!< CREG CREG6: EMC_CLK_SEL Mask        */
+
+// -------------------------------------  CREG_M4TXEVENT  -----------------------------------------
+#define CREG_M4TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M4TXEVENT: TXEVCLR Position    */
+#define CREG_M4TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos)                    /*!< CREG M4TXEVENT: TXEVCLR Mask        */
+
+// ---------------------------------------  CREG_CHIPID  ------------------------------------------
+#define CREG_CHIPID_ID_Pos                                    0                                                         /*!< CREG CHIPID: ID Position            */
+#define CREG_CHIPID_ID_Msk                                    (0xffffffffUL << CREG_CHIPID_ID_Pos)                      /*!< CREG CHIPID: ID Mask                */
+
+// -------------------------------------  CREG_M0TXEVENT  -----------------------------------------
+#define CREG_M0TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M0TXEVENT: TXEVCLR Position    */
+#define CREG_M0TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos)                    /*!< CREG M0TXEVENT: TXEVCLR Mask        */
+
+// ------------------------------------  CREG_M0APPMEMMAP  ----------------------------------------
+#define CREG_M0APPMEMMAP_M0APPMAP_Pos                         12                                                        /*!< CREG M0APPMEMMAP: M0APPMAP Position */
+#define CREG_M0APPMEMMAP_M0APPMAP_Msk                         (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos)           /*!< CREG M0APPMEMMAP: M0APPMAP Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                              EVENTROUTER Position & Mask                             -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------  EVENTROUTER_HILO  ----------------------------------------
+#define EVENTROUTER_HILO_WAKEUP0_L_Pos                        0                                                         /*!< EVENTROUTER HILO: WAKEUP0_L Position */
+#define EVENTROUTER_HILO_WAKEUP0_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP0_L Mask    */
+#define EVENTROUTER_HILO_WAKEUP1_L_Pos                        1                                                         /*!< EVENTROUTER HILO: WAKEUP1_L Position */
+#define EVENTROUTER_HILO_WAKEUP1_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP1_L Mask    */
+#define EVENTROUTER_HILO_WAKEUP2_L_Pos                        2                                                         /*!< EVENTROUTER HILO: WAKEUP2_L Position */
+#define EVENTROUTER_HILO_WAKEUP2_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP2_L Mask    */
+#define EVENTROUTER_HILO_WAKEUP3_L_Pos                        3                                                         /*!< EVENTROUTER HILO: WAKEUP3_L Position */
+#define EVENTROUTER_HILO_WAKEUP3_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP3_L Mask    */
+#define EVENTROUTER_HILO_ATIMER_L_Pos                         4                                                         /*!< EVENTROUTER HILO: ATIMER_L Position */
+#define EVENTROUTER_HILO_ATIMER_L_Msk                         (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos)                 /*!< EVENTROUTER HILO: ATIMER_L Mask     */
+#define EVENTROUTER_HILO_RTC_L_Pos                            5                                                         /*!< EVENTROUTER HILO: RTC_L Position    */
+#define EVENTROUTER_HILO_RTC_L_Msk                            (0x01UL << EVENTROUTER_HILO_RTC_L_Pos)                    /*!< EVENTROUTER HILO: RTC_L Mask        */
+#define EVENTROUTER_HILO_BOD_L_Pos                            6                                                         /*!< EVENTROUTER HILO: BOD_L Position    */
+#define EVENTROUTER_HILO_BOD_L_Msk                            (0x01UL << EVENTROUTER_HILO_BOD_L_Pos)                    /*!< EVENTROUTER HILO: BOD_L Mask        */
+#define EVENTROUTER_HILO_WWDT_L_Pos                           7                                                         /*!< EVENTROUTER HILO: WWDT_L Position   */
+#define EVENTROUTER_HILO_WWDT_L_Msk                           (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos)                   /*!< EVENTROUTER HILO: WWDT_L Mask       */
+#define EVENTROUTER_HILO_ETH_L_Pos                            8                                                         /*!< EVENTROUTER HILO: ETH_L Position    */
+#define EVENTROUTER_HILO_ETH_L_Msk                            (0x01UL << EVENTROUTER_HILO_ETH_L_Pos)                    /*!< EVENTROUTER HILO: ETH_L Mask        */
+#define EVENTROUTER_HILO_USB0_L_Pos                           9                                                         /*!< EVENTROUTER HILO: USB0_L Position   */
+#define EVENTROUTER_HILO_USB0_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB0_L_Pos)                   /*!< EVENTROUTER HILO: USB0_L Mask       */
+#define EVENTROUTER_HILO_USB1_L_Pos                           10                                                        /*!< EVENTROUTER HILO: USB1_L Position   */
+#define EVENTROUTER_HILO_USB1_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB1_L_Pos)                   /*!< EVENTROUTER HILO: USB1_L Mask       */
+#define EVENTROUTER_HILO_SDMMC_L_Pos                          11                                                        /*!< EVENTROUTER HILO: SDMMC_L Position  */
+#define EVENTROUTER_HILO_SDMMC_L_Msk                          (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos)                  /*!< EVENTROUTER HILO: SDMMC_L Mask      */
+#define EVENTROUTER_HILO_CAN_L_Pos                            12                                                        /*!< EVENTROUTER HILO: CAN_L Position    */
+#define EVENTROUTER_HILO_CAN_L_Msk                            (0x01UL << EVENTROUTER_HILO_CAN_L_Pos)                    /*!< EVENTROUTER HILO: CAN_L Mask        */
+#define EVENTROUTER_HILO_TIM2_L_Pos                           13                                                        /*!< EVENTROUTER HILO: TIM2_L Position   */
+#define EVENTROUTER_HILO_TIM2_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos)                   /*!< EVENTROUTER HILO: TIM2_L Mask       */
+#define EVENTROUTER_HILO_TIM6_L_Pos                           14                                                        /*!< EVENTROUTER HILO: TIM6_L Position   */
+#define EVENTROUTER_HILO_TIM6_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos)                   /*!< EVENTROUTER HILO: TIM6_L Mask       */
+#define EVENTROUTER_HILO_QEI_L_Pos                            15                                                        /*!< EVENTROUTER HILO: QEI_L Position    */
+#define EVENTROUTER_HILO_QEI_L_Msk                            (0x01UL << EVENTROUTER_HILO_QEI_L_Pos)                    /*!< EVENTROUTER HILO: QEI_L Mask        */
+#define EVENTROUTER_HILO_TIM14_L_Pos                          16                                                        /*!< EVENTROUTER HILO: TIM14_L Position  */
+#define EVENTROUTER_HILO_TIM14_L_Msk                          (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos)                  /*!< EVENTROUTER HILO: TIM14_L Mask      */
+#define EVENTROUTER_HILO_RESET_L_Pos                          19                                                        /*!< EVENTROUTER HILO: RESET_L Position  */
+#define EVENTROUTER_HILO_RESET_L_Msk                          (0x01UL << EVENTROUTER_HILO_RESET_L_Pos)                  /*!< EVENTROUTER HILO: RESET_L Mask      */
+
+// ------------------------------------  EVENTROUTER_EDGE  ----------------------------------------
+#define EVENTROUTER_EDGE_WAKEUP0_E_Pos                        0                                                         /*!< EVENTROUTER EDGE: WAKEUP0_E Position */
+#define EVENTROUTER_EDGE_WAKEUP0_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP0_E Mask    */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Pos                        1                                                         /*!< EVENTROUTER EDGE: WAKEUP1_E Position */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP1_E Mask    */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Pos                        2                                                         /*!< EVENTROUTER EDGE: WAKEUP2_E Position */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP2_E Mask    */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Pos                        3                                                         /*!< EVENTROUTER EDGE: WAKEUP3_E Position */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP3_E Mask    */
+#define EVENTROUTER_EDGE_ATIMER_E_Pos                         4                                                         /*!< EVENTROUTER EDGE: ATIMER_E Position */
+#define EVENTROUTER_EDGE_ATIMER_E_Msk                         (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos)                 /*!< EVENTROUTER EDGE: ATIMER_E Mask     */
+#define EVENTROUTER_EDGE_RTC_E_Pos                            5                                                         /*!< EVENTROUTER EDGE: RTC_E Position    */
+#define EVENTROUTER_EDGE_RTC_E_Msk                            (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos)                    /*!< EVENTROUTER EDGE: RTC_E Mask        */
+#define EVENTROUTER_EDGE_BOD_E_Pos                            6                                                         /*!< EVENTROUTER EDGE: BOD_E Position    */
+#define EVENTROUTER_EDGE_BOD_E_Msk                            (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos)                    /*!< EVENTROUTER EDGE: BOD_E Mask        */
+#define EVENTROUTER_EDGE_WWDT_E_Pos                           7                                                         /*!< EVENTROUTER EDGE: WWDT_E Position   */
+#define EVENTROUTER_EDGE_WWDT_E_Msk                           (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos)                   /*!< EVENTROUTER EDGE: WWDT_E Mask       */
+#define EVENTROUTER_EDGE_ETH_E_Pos                            8                                                         /*!< EVENTROUTER EDGE: ETH_E Position    */
+#define EVENTROUTER_EDGE_ETH_E_Msk                            (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos)                    /*!< EVENTROUTER EDGE: ETH_E Mask        */
+#define EVENTROUTER_EDGE_USB0_E_Pos                           9                                                         /*!< EVENTROUTER EDGE: USB0_E Position   */
+#define EVENTROUTER_EDGE_USB0_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos)                   /*!< EVENTROUTER EDGE: USB0_E Mask       */
+#define EVENTROUTER_EDGE_USB1_E_Pos                           10                                                        /*!< EVENTROUTER EDGE: USB1_E Position   */
+#define EVENTROUTER_EDGE_USB1_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos)                   /*!< EVENTROUTER EDGE: USB1_E Mask       */
+#define EVENTROUTER_EDGE_SDMMC_E_Pos                          11                                                        /*!< EVENTROUTER EDGE: SDMMC_E Position  */
+#define EVENTROUTER_EDGE_SDMMC_E_Msk                          (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos)                  /*!< EVENTROUTER EDGE: SDMMC_E Mask      */
+#define EVENTROUTER_EDGE_CAN_E_Pos                            12                                                        /*!< EVENTROUTER EDGE: CAN_E Position    */
+#define EVENTROUTER_EDGE_CAN_E_Msk                            (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos)                    /*!< EVENTROUTER EDGE: CAN_E Mask        */
+#define EVENTROUTER_EDGE_TIM2_E_Pos                           13                                                        /*!< EVENTROUTER EDGE: TIM2_E Position   */
+#define EVENTROUTER_EDGE_TIM2_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos)                   /*!< EVENTROUTER EDGE: TIM2_E Mask       */
+#define EVENTROUTER_EDGE_TIM6_E_Pos                           14                                                        /*!< EVENTROUTER EDGE: TIM6_E Position   */
+#define EVENTROUTER_EDGE_TIM6_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos)                   /*!< EVENTROUTER EDGE: TIM6_E Mask       */
+#define EVENTROUTER_EDGE_QEI_E_Pos                            15                                                        /*!< EVENTROUTER EDGE: QEI_E Position    */
+#define EVENTROUTER_EDGE_QEI_E_Msk                            (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos)                    /*!< EVENTROUTER EDGE: QEI_E Mask        */
+#define EVENTROUTER_EDGE_TIM14_E_Pos                          16                                                        /*!< EVENTROUTER EDGE: TIM14_E Position  */
+#define EVENTROUTER_EDGE_TIM14_E_Msk                          (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos)                  /*!< EVENTROUTER EDGE: TIM14_E Mask      */
+#define EVENTROUTER_EDGE_RESET_E_Pos                          19                                                        /*!< EVENTROUTER EDGE: RESET_E Position  */
+#define EVENTROUTER_EDGE_RESET_E_Msk                          (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos)                  /*!< EVENTROUTER EDGE: RESET_E Mask      */
+
+// -----------------------------------  EVENTROUTER_CLR_EN  ---------------------------------------
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos                  0                                                         /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos                  1                                                         /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos                  2                                                         /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos                  3                                                         /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos                   4                                                         /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk                   (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos)           /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos                      5                                                         /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos                      6                                                         /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos                     7                                                         /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos                      8                                                         /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos                     9                                                         /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos                     10                                                        /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos                    11                                                        /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos                      12                                                        /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos                     13                                                        /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos                     14                                                        /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos                      15                                                        /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask  */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos                    16                                                        /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos                    19                                                        /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */
+
+// -----------------------------------  EVENTROUTER_SET_EN  ---------------------------------------
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos                  0                                                         /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos                  1                                                         /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos                  2                                                         /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos                  3                                                         /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos                   4                                                         /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk                   (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos)           /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Pos                      5                                                         /*!< EVENTROUTER SET_EN: RTC_SETEN Position */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos)              /*!< EVENTROUTER SET_EN: RTC_SETEN Mask  */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Pos                      6                                                         /*!< EVENTROUTER SET_EN: BOD_SETEN Position */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos)              /*!< EVENTROUTER SET_EN: BOD_SETEN Mask  */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos                     7                                                         /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos)             /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Pos                      8                                                         /*!< EVENTROUTER SET_EN: ETH_SETEN Position */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos)              /*!< EVENTROUTER SET_EN: ETH_SETEN Mask  */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Pos                     9                                                         /*!< EVENTROUTER SET_EN: USB0_SETEN Position */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Pos                     10                                                        /*!< EVENTROUTER SET_EN: USB1_SETEN Position */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos                    11                                                        /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos)            /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Pos                      12                                                        /*!< EVENTROUTER SET_EN: CAN_SETEN Position */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos)              /*!< EVENTROUTER SET_EN: CAN_SETEN Mask  */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos                     13                                                        /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos                     14                                                        /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Pos                      15                                                        /*!< EVENTROUTER SET_EN: QEI_SETEN Position */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos)              /*!< EVENTROUTER SET_EN: QEI_SETEN Mask  */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos                    16                                                        /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos)            /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Pos                    19                                                        /*!< EVENTROUTER SET_EN: RESET_SETEN Position */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos)            /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */
+
+// -----------------------------------  EVENTROUTER_STATUS  ---------------------------------------
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos                     0                                                         /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos                     1                                                         /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos                     2                                                         /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos                     3                                                         /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */
+#define EVENTROUTER_STATUS_ATIMER_ST_Pos                      4                                                         /*!< EVENTROUTER STATUS: ATIMER_ST Position */
+#define EVENTROUTER_STATUS_ATIMER_ST_Msk                      (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos)              /*!< EVENTROUTER STATUS: ATIMER_ST Mask  */
+#define EVENTROUTER_STATUS_RTC_ST_Pos                         5                                                         /*!< EVENTROUTER STATUS: RTC_ST Position */
+#define EVENTROUTER_STATUS_RTC_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos)                 /*!< EVENTROUTER STATUS: RTC_ST Mask     */
+#define EVENTROUTER_STATUS_BOD_ST_Pos                         6                                                         /*!< EVENTROUTER STATUS: BOD_ST Position */
+#define EVENTROUTER_STATUS_BOD_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos)                 /*!< EVENTROUTER STATUS: BOD_ST Mask     */
+#define EVENTROUTER_STATUS_WWDT_ST_Pos                        7                                                         /*!< EVENTROUTER STATUS: WWDT_ST Position */
+#define EVENTROUTER_STATUS_WWDT_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos)                /*!< EVENTROUTER STATUS: WWDT_ST Mask    */
+#define EVENTROUTER_STATUS_ETH_ST_Pos                         8                                                         /*!< EVENTROUTER STATUS: ETH_ST Position */
+#define EVENTROUTER_STATUS_ETH_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos)                 /*!< EVENTROUTER STATUS: ETH_ST Mask     */
+#define EVENTROUTER_STATUS_USB0_ST_Pos                        9                                                         /*!< EVENTROUTER STATUS: USB0_ST Position */
+#define EVENTROUTER_STATUS_USB0_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos)                /*!< EVENTROUTER STATUS: USB0_ST Mask    */
+#define EVENTROUTER_STATUS_USB1_ST_Pos                        10                                                        /*!< EVENTROUTER STATUS: USB1_ST Position */
+#define EVENTROUTER_STATUS_USB1_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos)                /*!< EVENTROUTER STATUS: USB1_ST Mask    */
+#define EVENTROUTER_STATUS_SDMMC_ST_Pos                       11                                                        /*!< EVENTROUTER STATUS: SDMMC_ST Position */
+#define EVENTROUTER_STATUS_SDMMC_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos)               /*!< EVENTROUTER STATUS: SDMMC_ST Mask   */
+#define EVENTROUTER_STATUS_CAN_ST_Pos                         12                                                        /*!< EVENTROUTER STATUS: CAN_ST Position */
+#define EVENTROUTER_STATUS_CAN_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos)                 /*!< EVENTROUTER STATUS: CAN_ST Mask     */
+#define EVENTROUTER_STATUS_TIM2_ST_Pos                        13                                                        /*!< EVENTROUTER STATUS: TIM2_ST Position */
+#define EVENTROUTER_STATUS_TIM2_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos)                /*!< EVENTROUTER STATUS: TIM2_ST Mask    */
+#define EVENTROUTER_STATUS_TIM6_ST_Pos                        14                                                        /*!< EVENTROUTER STATUS: TIM6_ST Position */
+#define EVENTROUTER_STATUS_TIM6_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos)                /*!< EVENTROUTER STATUS: TIM6_ST Mask    */
+#define EVENTROUTER_STATUS_QEI_ST_Pos                         15                                                        /*!< EVENTROUTER STATUS: QEI_ST Position */
+#define EVENTROUTER_STATUS_QEI_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos)                 /*!< EVENTROUTER STATUS: QEI_ST Mask     */
+#define EVENTROUTER_STATUS_TIM14_ST_Pos                       16                                                        /*!< EVENTROUTER STATUS: TIM14_ST Position */
+#define EVENTROUTER_STATUS_TIM14_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos)               /*!< EVENTROUTER STATUS: TIM14_ST Mask   */
+#define EVENTROUTER_STATUS_RESET_ST_Pos                       19                                                        /*!< EVENTROUTER STATUS: RESET_ST Position */
+#define EVENTROUTER_STATUS_RESET_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos)               /*!< EVENTROUTER STATUS: RESET_ST Mask   */
+
+// -----------------------------------  EVENTROUTER_ENABLE  ---------------------------------------
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos                     0                                                         /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos                     1                                                         /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos                     2                                                         /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos                     3                                                         /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Pos                      4                                                         /*!< EVENTROUTER ENABLE: ATIMER_EN Position */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Msk                      (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos)              /*!< EVENTROUTER ENABLE: ATIMER_EN Mask  */
+#define EVENTROUTER_ENABLE_RTC_EN_Pos                         5                                                         /*!< EVENTROUTER ENABLE: RTC_EN Position */
+#define EVENTROUTER_ENABLE_RTC_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos)                 /*!< EVENTROUTER ENABLE: RTC_EN Mask     */
+#define EVENTROUTER_ENABLE_BOD_EN_Pos                         6                                                         /*!< EVENTROUTER ENABLE: BOD_EN Position */
+#define EVENTROUTER_ENABLE_BOD_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos)                 /*!< EVENTROUTER ENABLE: BOD_EN Mask     */
+#define EVENTROUTER_ENABLE_WWDT_EN_Pos                        7                                                         /*!< EVENTROUTER ENABLE: WWDT_EN Position */
+#define EVENTROUTER_ENABLE_WWDT_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos)                /*!< EVENTROUTER ENABLE: WWDT_EN Mask    */
+#define EVENTROUTER_ENABLE_ETH_EN_Pos                         8                                                         /*!< EVENTROUTER ENABLE: ETH_EN Position */
+#define EVENTROUTER_ENABLE_ETH_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos)                 /*!< EVENTROUTER ENABLE: ETH_EN Mask     */
+#define EVENTROUTER_ENABLE_USB0_EN_Pos                        9                                                         /*!< EVENTROUTER ENABLE: USB0_EN Position */
+#define EVENTROUTER_ENABLE_USB0_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos)                /*!< EVENTROUTER ENABLE: USB0_EN Mask    */
+#define EVENTROUTER_ENABLE_USB1_EN_Pos                        10                                                        /*!< EVENTROUTER ENABLE: USB1_EN Position */
+#define EVENTROUTER_ENABLE_USB1_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos)                /*!< EVENTROUTER ENABLE: USB1_EN Mask    */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Pos                       11                                                        /*!< EVENTROUTER ENABLE: SDMMC_EN Position */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos)               /*!< EVENTROUTER ENABLE: SDMMC_EN Mask   */
+#define EVENTROUTER_ENABLE_CAN_EN_Pos                         12                                                        /*!< EVENTROUTER ENABLE: CAN_EN Position */
+#define EVENTROUTER_ENABLE_CAN_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos)                 /*!< EVENTROUTER ENABLE: CAN_EN Mask     */
+#define EVENTROUTER_ENABLE_TIM2_EN_Pos                        13                                                        /*!< EVENTROUTER ENABLE: TIM2_EN Position */
+#define EVENTROUTER_ENABLE_TIM2_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM2_EN Mask    */
+#define EVENTROUTER_ENABLE_TIM6_EN_Pos                        14                                                        /*!< EVENTROUTER ENABLE: TIM6_EN Position */
+#define EVENTROUTER_ENABLE_TIM6_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM6_EN Mask    */
+#define EVENTROUTER_ENABLE_QEI_EN_Pos                         15                                                        /*!< EVENTROUTER ENABLE: QEI_EN Position */
+#define EVENTROUTER_ENABLE_QEI_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos)                 /*!< EVENTROUTER ENABLE: QEI_EN Mask     */
+#define EVENTROUTER_ENABLE_TIM14_EN_Pos                       16                                                        /*!< EVENTROUTER ENABLE: TIM14_EN Position */
+#define EVENTROUTER_ENABLE_TIM14_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos)               /*!< EVENTROUTER ENABLE: TIM14_EN Mask   */
+#define EVENTROUTER_ENABLE_RESET_EN_Pos                       19                                                        /*!< EVENTROUTER ENABLE: RESET_EN Position */
+#define EVENTROUTER_ENABLE_RESET_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos)               /*!< EVENTROUTER ENABLE: RESET_EN Mask   */
+
+// ----------------------------------  EVENTROUTER_CLR_STAT  --------------------------------------
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos                0                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos                1                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos                2                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos                3                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos                 4                                                         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk                 (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos)         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos                    5                                                         /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos                    6                                                         /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos                   7                                                         /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos                    8                                                         /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos                   9                                                         /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos                   10                                                        /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos                  11                                                        /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos                    12                                                        /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos                   13                                                        /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos                   14                                                        /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos                    15                                                        /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos                  16                                                        /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos                  19                                                        /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */
+
+// ----------------------------------  EVENTROUTER_SET_STAT  --------------------------------------
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos                0                                                         /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos                1                                                         /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos                2                                                         /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos                3                                                         /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos                 4                                                         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk                 (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos)         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Pos                    5                                                         /*!< EVENTROUTER SET_STAT: RTC_SETST Position */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos)            /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Pos                    6                                                         /*!< EVENTROUTER SET_STAT: BOD_SETST Position */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos)            /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos                   7                                                         /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos)           /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Pos                    8                                                         /*!< EVENTROUTER SET_STAT: ETH_SETST Position */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos)            /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Pos                   9                                                         /*!< EVENTROUTER SET_STAT: USB0_SETST Position */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Pos                   10                                                        /*!< EVENTROUTER SET_STAT: USB1_SETST Position */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos                  11                                                        /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos)          /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Pos                    12                                                        /*!< EVENTROUTER SET_STAT: CAN_SETST Position */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos)            /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos                   13                                                        /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos                   14                                                        /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Pos                    15                                                        /*!< EVENTROUTER SET_STAT: QEI_SETST Position */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos)            /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos                  16                                                        /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos)          /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Pos                  19                                                        /*!< EVENTROUTER SET_STAT: RESET_SETST Position */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos)          /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  RTC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  RTC_ILR  --------------------------------------------
+#define RTC_ILR_RTCCIF_Pos                                    0                                                         /*!< RTC ILR: RTCCIF Position            */
+#define RTC_ILR_RTCCIF_Msk                                    (0x01UL << RTC_ILR_RTCCIF_Pos)                            /*!< RTC ILR: RTCCIF Mask                */
+#define RTC_ILR_RTCALF_Pos                                    1                                                         /*!< RTC ILR: RTCALF Position            */
+#define RTC_ILR_RTCALF_Msk                                    (0x01UL << RTC_ILR_RTCALF_Pos)                            /*!< RTC ILR: RTCALF Mask                */
+
+// -----------------------------------------  RTC_CCR  --------------------------------------------
+#define RTC_CCR_CLKEN_Pos                                     0                                                         /*!< RTC CCR: CLKEN Position             */
+#define RTC_CCR_CLKEN_Msk                                     (0x01UL << RTC_CCR_CLKEN_Pos)                             /*!< RTC CCR: CLKEN Mask                 */
+#define RTC_CCR_CTCRST_Pos                                    1                                                         /*!< RTC CCR: CTCRST Position            */
+#define RTC_CCR_CTCRST_Msk                                    (0x01UL << RTC_CCR_CTCRST_Pos)                            /*!< RTC CCR: CTCRST Mask                */
+#define RTC_CCR_CCALEN_Pos                                    4                                                         /*!< RTC CCR: CCALEN Position            */
+#define RTC_CCR_CCALEN_Msk                                    (0x01UL << RTC_CCR_CCALEN_Pos)                            /*!< RTC CCR: CCALEN Mask                */
+
+// ----------------------------------------  RTC_CIIR  --------------------------------------------
+#define RTC_CIIR_IMSEC_Pos                                    0                                                         /*!< RTC CIIR: IMSEC Position            */
+#define RTC_CIIR_IMSEC_Msk                                    (0x01UL << RTC_CIIR_IMSEC_Pos)                            /*!< RTC CIIR: IMSEC Mask                */
+#define RTC_CIIR_IMMIN_Pos                                    1                                                         /*!< RTC CIIR: IMMIN Position            */
+#define RTC_CIIR_IMMIN_Msk                                    (0x01UL << RTC_CIIR_IMMIN_Pos)                            /*!< RTC CIIR: IMMIN Mask                */
+#define RTC_CIIR_IMHOUR_Pos                                   2                                                         /*!< RTC CIIR: IMHOUR Position           */
+#define RTC_CIIR_IMHOUR_Msk                                   (0x01UL << RTC_CIIR_IMHOUR_Pos)                           /*!< RTC CIIR: IMHOUR Mask               */
+#define RTC_CIIR_IMDOM_Pos                                    3                                                         /*!< RTC CIIR: IMDOM Position            */
+#define RTC_CIIR_IMDOM_Msk                                    (0x01UL << RTC_CIIR_IMDOM_Pos)                            /*!< RTC CIIR: IMDOM Mask                */
+#define RTC_CIIR_IMDOW_Pos                                    4                                                         /*!< RTC CIIR: IMDOW Position            */
+#define RTC_CIIR_IMDOW_Msk                                    (0x01UL << RTC_CIIR_IMDOW_Pos)                            /*!< RTC CIIR: IMDOW Mask                */
+#define RTC_CIIR_IMDOY_Pos                                    5                                                         /*!< RTC CIIR: IMDOY Position            */
+#define RTC_CIIR_IMDOY_Msk                                    (0x01UL << RTC_CIIR_IMDOY_Pos)                            /*!< RTC CIIR: IMDOY Mask                */
+#define RTC_CIIR_IMMON_Pos                                    6                                                         /*!< RTC CIIR: IMMON Position            */
+#define RTC_CIIR_IMMON_Msk                                    (0x01UL << RTC_CIIR_IMMON_Pos)                            /*!< RTC CIIR: IMMON Mask                */
+#define RTC_CIIR_IMYEAR_Pos                                   7                                                         /*!< RTC CIIR: IMYEAR Position           */
+#define RTC_CIIR_IMYEAR_Msk                                   (0x01UL << RTC_CIIR_IMYEAR_Pos)                           /*!< RTC CIIR: IMYEAR Mask               */
+
+// -----------------------------------------  RTC_AMR  --------------------------------------------
+#define RTC_AMR_AMRSEC_Pos                                    0                                                         /*!< RTC AMR: AMRSEC Position            */
+#define RTC_AMR_AMRSEC_Msk                                    (0x01UL << RTC_AMR_AMRSEC_Pos)                            /*!< RTC AMR: AMRSEC Mask                */
+#define RTC_AMR_AMRMIN_Pos                                    1                                                         /*!< RTC AMR: AMRMIN Position            */
+#define RTC_AMR_AMRMIN_Msk                                    (0x01UL << RTC_AMR_AMRMIN_Pos)                            /*!< RTC AMR: AMRMIN Mask                */
+#define RTC_AMR_AMRHOUR_Pos                                   2                                                         /*!< RTC AMR: AMRHOUR Position           */
+#define RTC_AMR_AMRHOUR_Msk                                   (0x01UL << RTC_AMR_AMRHOUR_Pos)                           /*!< RTC AMR: AMRHOUR Mask               */
+#define RTC_AMR_AMRDOM_Pos                                    3                                                         /*!< RTC AMR: AMRDOM Position            */
+#define RTC_AMR_AMRDOM_Msk                                    (0x01UL << RTC_AMR_AMRDOM_Pos)                            /*!< RTC AMR: AMRDOM Mask                */
+#define RTC_AMR_AMRDOW_Pos                                    4                                                         /*!< RTC AMR: AMRDOW Position            */
+#define RTC_AMR_AMRDOW_Msk                                    (0x01UL << RTC_AMR_AMRDOW_Pos)                            /*!< RTC AMR: AMRDOW Mask                */
+#define RTC_AMR_AMRDOY_Pos                                    5                                                         /*!< RTC AMR: AMRDOY Position            */
+#define RTC_AMR_AMRDOY_Msk                                    (0x01UL << RTC_AMR_AMRDOY_Pos)                            /*!< RTC AMR: AMRDOY Mask                */
+#define RTC_AMR_AMRMON_Pos                                    6                                                         /*!< RTC AMR: AMRMON Position            */
+#define RTC_AMR_AMRMON_Msk                                    (0x01UL << RTC_AMR_AMRMON_Pos)                            /*!< RTC AMR: AMRMON Mask                */
+#define RTC_AMR_AMRYEAR_Pos                                   7                                                         /*!< RTC AMR: AMRYEAR Position           */
+#define RTC_AMR_AMRYEAR_Msk                                   (0x01UL << RTC_AMR_AMRYEAR_Pos)                           /*!< RTC AMR: AMRYEAR Mask               */
+
+// ---------------------------------------  RTC_CTIME0  -------------------------------------------
+#define RTC_CTIME0_SECONDS_Pos                                0                                                         /*!< RTC CTIME0: SECONDS Position        */
+#define RTC_CTIME0_SECONDS_Msk                                (0x3fUL << RTC_CTIME0_SECONDS_Pos)                        /*!< RTC CTIME0: SECONDS Mask            */
+#define RTC_CTIME0_MINUTES_Pos                                8                                                         /*!< RTC CTIME0: MINUTES Position        */
+#define RTC_CTIME0_MINUTES_Msk                                (0x3fUL << RTC_CTIME0_MINUTES_Pos)                        /*!< RTC CTIME0: MINUTES Mask            */
+#define RTC_CTIME0_HOURS_Pos                                  16                                                        /*!< RTC CTIME0: HOURS Position          */
+#define RTC_CTIME0_HOURS_Msk                                  (0x1fUL << RTC_CTIME0_HOURS_Pos)                          /*!< RTC CTIME0: HOURS Mask              */
+#define RTC_CTIME0_DOW_Pos                                    24                                                        /*!< RTC CTIME0: DOW Position            */
+#define RTC_CTIME0_DOW_Msk                                    (0x07UL << RTC_CTIME0_DOW_Pos)                            /*!< RTC CTIME0: DOW Mask                */
+
+// ---------------------------------------  RTC_CTIME1  -------------------------------------------
+#define RTC_CTIME1_DOM_Pos                                    0                                                         /*!< RTC CTIME1: DOM Position            */
+#define RTC_CTIME1_DOM_Msk                                    (0x1fUL << RTC_CTIME1_DOM_Pos)                            /*!< RTC CTIME1: DOM Mask                */
+#define RTC_CTIME1_MONTH_Pos                                  8                                                         /*!< RTC CTIME1: MONTH Position          */
+#define RTC_CTIME1_MONTH_Msk                                  (0x0fUL << RTC_CTIME1_MONTH_Pos)                          /*!< RTC CTIME1: MONTH Mask              */
+#define RTC_CTIME1_YEAR_Pos                                   16                                                        /*!< RTC CTIME1: YEAR Position           */
+#define RTC_CTIME1_YEAR_Msk                                   (0x00000fffUL << RTC_CTIME1_YEAR_Pos)                     /*!< RTC CTIME1: YEAR Mask               */
+
+// ---------------------------------------  RTC_CTIME2  -------------------------------------------
+#define RTC_CTIME2_DOY_Pos                                    0                                                         /*!< RTC CTIME2: DOY Position            */
+#define RTC_CTIME2_DOY_Msk                                    (0x00000fffUL << RTC_CTIME2_DOY_Pos)                      /*!< RTC CTIME2: DOY Mask                */
+
+// -----------------------------------------  RTC_SEC  --------------------------------------------
+#define RTC_SEC_SECONDS_Pos                                   0                                                         /*!< RTC SEC: SECONDS Position           */
+#define RTC_SEC_SECONDS_Msk                                   (0x3fUL << RTC_SEC_SECONDS_Pos)                           /*!< RTC SEC: SECONDS Mask               */
+
+// -----------------------------------------  RTC_MIN  --------------------------------------------
+#define RTC_MIN_MINUTES_Pos                                   0                                                         /*!< RTC MIN: MINUTES Position           */
+#define RTC_MIN_MINUTES_Msk                                   (0x3fUL << RTC_MIN_MINUTES_Pos)                           /*!< RTC MIN: MINUTES Mask               */
+
+// -----------------------------------------  RTC_HRS  --------------------------------------------
+#define RTC_HRS_HOURS_Pos                                     0                                                         /*!< RTC HRS: HOURS Position             */
+#define RTC_HRS_HOURS_Msk                                     (0x1fUL << RTC_HRS_HOURS_Pos)                             /*!< RTC HRS: HOURS Mask                 */
+
+// -----------------------------------------  RTC_DOM  --------------------------------------------
+#define RTC_DOM_DOM_Pos                                       0                                                         /*!< RTC DOM: DOM Position               */
+#define RTC_DOM_DOM_Msk                                       (0x1fUL << RTC_DOM_DOM_Pos)                               /*!< RTC DOM: DOM Mask                   */
+
+// -----------------------------------------  RTC_DOW  --------------------------------------------
+#define RTC_DOW_DOW_Pos                                       0                                                         /*!< RTC DOW: DOW Position               */
+#define RTC_DOW_DOW_Msk                                       (0x07UL << RTC_DOW_DOW_Pos)                               /*!< RTC DOW: DOW Mask                   */
+
+// -----------------------------------------  RTC_DOY  --------------------------------------------
+#define RTC_DOY_DOY_Pos                                       0                                                         /*!< RTC DOY: DOY Position               */
+#define RTC_DOY_DOY_Msk                                       (0x000001ffUL << RTC_DOY_DOY_Pos)                         /*!< RTC DOY: DOY Mask                   */
+
+// ----------------------------------------  RTC_MONTH  -------------------------------------------
+#define RTC_MONTH_MONTH_Pos                                   0                                                         /*!< RTC MONTH: MONTH Position           */
+#define RTC_MONTH_MONTH_Msk                                   (0x0fUL << RTC_MONTH_MONTH_Pos)                           /*!< RTC MONTH: MONTH Mask               */
+
+// ----------------------------------------  RTC_YEAR  --------------------------------------------
+#define RTC_YEAR_YEAR_Pos                                     0                                                         /*!< RTC YEAR: YEAR Position             */
+#define RTC_YEAR_YEAR_Msk                                     (0x00000fffUL << RTC_YEAR_YEAR_Pos)                       /*!< RTC YEAR: YEAR Mask                 */
+
+// -------------------------------------  RTC_CALIBRATION  ----------------------------------------
+#define RTC_CALIBRATION_CALVAL_Pos                            0                                                         /*!< RTC CALIBRATION: CALVAL Position    */
+#define RTC_CALIBRATION_CALVAL_Msk                            (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos)              /*!< RTC CALIBRATION: CALVAL Mask        */
+#define RTC_CALIBRATION_CALDIR_Pos                            17                                                        /*!< RTC CALIBRATION: CALDIR Position    */
+#define RTC_CALIBRATION_CALDIR_Msk                            (0x01UL << RTC_CALIBRATION_CALDIR_Pos)                    /*!< RTC CALIBRATION: CALDIR Mask        */
+
+// ----------------------------------------  RTC_ASEC  --------------------------------------------
+#define RTC_ASEC_SECONDS_Pos                                  0                                                         /*!< RTC ASEC: SECONDS Position          */
+#define RTC_ASEC_SECONDS_Msk                                  (0x3fUL << RTC_ASEC_SECONDS_Pos)                          /*!< RTC ASEC: SECONDS Mask              */
+
+// ----------------------------------------  RTC_AMIN  --------------------------------------------
+#define RTC_AMIN_MINUTES_Pos                                  0                                                         /*!< RTC AMIN: MINUTES Position          */
+#define RTC_AMIN_MINUTES_Msk                                  (0x3fUL << RTC_AMIN_MINUTES_Pos)                          /*!< RTC AMIN: MINUTES Mask              */
+
+// ----------------------------------------  RTC_AHRS  --------------------------------------------
+#define RTC_AHRS_HOURS_Pos                                    0                                                         /*!< RTC AHRS: HOURS Position            */
+#define RTC_AHRS_HOURS_Msk                                    (0x1fUL << RTC_AHRS_HOURS_Pos)                            /*!< RTC AHRS: HOURS Mask                */
+
+// ----------------------------------------  RTC_ADOM  --------------------------------------------
+#define RTC_ADOM_DOM_Pos                                      0                                                         /*!< RTC ADOM: DOM Position              */
+#define RTC_ADOM_DOM_Msk                                      (0x1fUL << RTC_ADOM_DOM_Pos)                              /*!< RTC ADOM: DOM Mask                  */
+
+// ----------------------------------------  RTC_ADOW  --------------------------------------------
+#define RTC_ADOW_DOW_Pos                                      0                                                         /*!< RTC ADOW: DOW Position              */
+#define RTC_ADOW_DOW_Msk                                      (0x07UL << RTC_ADOW_DOW_Pos)                              /*!< RTC ADOW: DOW Mask                  */
+
+// ----------------------------------------  RTC_ADOY  --------------------------------------------
+#define RTC_ADOY_DOY_Pos                                      0                                                         /*!< RTC ADOY: DOY Position              */
+#define RTC_ADOY_DOY_Msk                                      (0x000001ffUL << RTC_ADOY_DOY_Pos)                        /*!< RTC ADOY: DOY Mask                  */
+
+// ----------------------------------------  RTC_AMON  --------------------------------------------
+#define RTC_AMON_MONTH_Pos                                    0                                                         /*!< RTC AMON: MONTH Position            */
+#define RTC_AMON_MONTH_Msk                                    (0x0fUL << RTC_AMON_MONTH_Pos)                            /*!< RTC AMON: MONTH Mask                */
+
+// ----------------------------------------  RTC_AYRS  --------------------------------------------
+#define RTC_AYRS_YEAR_Pos                                     0                                                         /*!< RTC AYRS: YEAR Position             */
+#define RTC_AYRS_YEAR_Msk                                     (0x00000fffUL << RTC_AYRS_YEAR_Pos)                       /*!< RTC AYRS: YEAR Mask                 */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  CGU Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------  CGU_FREQ_MON  ------------------------------------------
+#define CGU_FREQ_MON_RCNT_Pos                                 0                                                         /*!< CGU FREQ_MON: RCNT Position         */
+#define CGU_FREQ_MON_RCNT_Msk                                 (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos)                   /*!< CGU FREQ_MON: RCNT Mask             */
+#define CGU_FREQ_MON_FCNT_Pos                                 9                                                         /*!< CGU FREQ_MON: FCNT Position         */
+#define CGU_FREQ_MON_FCNT_Msk                                 (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos)                   /*!< CGU FREQ_MON: FCNT Mask             */
+#define CGU_FREQ_MON_MEAS_Pos                                 23                                                        /*!< CGU FREQ_MON: MEAS Position         */
+#define CGU_FREQ_MON_MEAS_Msk                                 (0x01UL << CGU_FREQ_MON_MEAS_Pos)                         /*!< CGU FREQ_MON: MEAS Mask             */
+#define CGU_FREQ_MON_CLK_SEL_Pos                              24                                                        /*!< CGU FREQ_MON: CLK_SEL Position      */
+#define CGU_FREQ_MON_CLK_SEL_Msk                              (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos)                      /*!< CGU FREQ_MON: CLK_SEL Mask          */
+
+// ------------------------------------  CGU_XTAL_OSC_CTRL  ---------------------------------------
+#define CGU_XTAL_OSC_CTRL_ENABLE_Pos                          0                                                         /*!< CGU XTAL_OSC_CTRL: ENABLE Position  */
+#define CGU_XTAL_OSC_CTRL_ENABLE_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos)                  /*!< CGU XTAL_OSC_CTRL: ENABLE Mask      */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Pos                          1                                                         /*!< CGU XTAL_OSC_CTRL: BYPASS Position  */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos)                  /*!< CGU XTAL_OSC_CTRL: BYPASS Mask      */
+#define CGU_XTAL_OSC_CTRL_HF_Pos                              2                                                         /*!< CGU XTAL_OSC_CTRL: HF Position      */
+#define CGU_XTAL_OSC_CTRL_HF_Msk                              (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos)                      /*!< CGU XTAL_OSC_CTRL: HF Mask          */
+
+// ------------------------------------  CGU_PLL0USB_STAT  ----------------------------------------
+#define CGU_PLL0USB_STAT_LOCK_Pos                             0                                                         /*!< CGU PLL0USB_STAT: LOCK Position     */
+#define CGU_PLL0USB_STAT_LOCK_Msk                             (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos)                     /*!< CGU PLL0USB_STAT: LOCK Mask         */
+#define CGU_PLL0USB_STAT_FR_Pos                               1                                                         /*!< CGU PLL0USB_STAT: FR Position       */
+#define CGU_PLL0USB_STAT_FR_Msk                               (0x01UL << CGU_PLL0USB_STAT_FR_Pos)                       /*!< CGU PLL0USB_STAT: FR Mask           */
+
+// ------------------------------------  CGU_PLL0USB_CTRL  ----------------------------------------
+#define CGU_PLL0USB_CTRL_PD_Pos                               0                                                         /*!< CGU PLL0USB_CTRL: PD Position       */
+#define CGU_PLL0USB_CTRL_PD_Msk                               (0x01UL << CGU_PLL0USB_CTRL_PD_Pos)                       /*!< CGU PLL0USB_CTRL: PD Mask           */
+#define CGU_PLL0USB_CTRL_BYPASS_Pos                           1                                                         /*!< CGU PLL0USB_CTRL: BYPASS Position   */
+#define CGU_PLL0USB_CTRL_BYPASS_Msk                           (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos)                   /*!< CGU PLL0USB_CTRL: BYPASS Mask       */
+#define CGU_PLL0USB_CTRL_DIRECTI_Pos                          2                                                         /*!< CGU PLL0USB_CTRL: DIRECTI Position  */
+#define CGU_PLL0USB_CTRL_DIRECTI_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTI Mask      */
+#define CGU_PLL0USB_CTRL_DIRECTO_Pos                          3                                                         /*!< CGU PLL0USB_CTRL: DIRECTO Position  */
+#define CGU_PLL0USB_CTRL_DIRECTO_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTO Mask      */
+#define CGU_PLL0USB_CTRL_CLKEN_Pos                            4                                                         /*!< CGU PLL0USB_CTRL: CLKEN Position    */
+#define CGU_PLL0USB_CTRL_CLKEN_Msk                            (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos)                    /*!< CGU PLL0USB_CTRL: CLKEN Mask        */
+#define CGU_PLL0USB_CTRL_FRM_Pos                              6                                                         /*!< CGU PLL0USB_CTRL: FRM Position      */
+#define CGU_PLL0USB_CTRL_FRM_Msk                              (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos)                      /*!< CGU PLL0USB_CTRL: FRM Mask          */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos                        11                                                        /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk                        (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos)                /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask    */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Pos                          24                                                        /*!< CGU PLL0USB_CTRL: CLK_SEL Position  */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Msk                          (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos)                  /*!< CGU PLL0USB_CTRL: CLK_SEL Mask      */
+
+// ------------------------------------  CGU_PLL0USB_MDIV  ----------------------------------------
+#define CGU_PLL0USB_MDIV_MDEC_Pos                             0                                                         /*!< CGU PLL0USB_MDIV: MDEC Position     */
+#define CGU_PLL0USB_MDIV_MDEC_Msk                             (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos)               /*!< CGU PLL0USB_MDIV: MDEC Mask         */
+#define CGU_PLL0USB_MDIV_SELP_Pos                             17                                                        /*!< CGU PLL0USB_MDIV: SELP Position     */
+#define CGU_PLL0USB_MDIV_SELP_Msk                             (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos)                     /*!< CGU PLL0USB_MDIV: SELP Mask         */
+#define CGU_PLL0USB_MDIV_SELI_Pos                             22                                                        /*!< CGU PLL0USB_MDIV: SELI Position     */
+#define CGU_PLL0USB_MDIV_SELI_Msk                             (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos)                     /*!< CGU PLL0USB_MDIV: SELI Mask         */
+#define CGU_PLL0USB_MDIV_SELR_Pos                             28                                                        /*!< CGU PLL0USB_MDIV: SELR Position     */
+#define CGU_PLL0USB_MDIV_SELR_Msk                             (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos)                     /*!< CGU PLL0USB_MDIV: SELR Mask         */
+
+// -----------------------------------  CGU_PLL0USB_NP_DIV  ---------------------------------------
+#define CGU_PLL0USB_NP_DIV_PDEC_Pos                           0                                                         /*!< CGU PLL0USB_NP_DIV: PDEC Position   */
+#define CGU_PLL0USB_NP_DIV_PDEC_Msk                           (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos)                   /*!< CGU PLL0USB_NP_DIV: PDEC Mask       */
+#define CGU_PLL0USB_NP_DIV_NDEC_Pos                           12                                                        /*!< CGU PLL0USB_NP_DIV: NDEC Position   */
+#define CGU_PLL0USB_NP_DIV_NDEC_Msk                           (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos)             /*!< CGU PLL0USB_NP_DIV: NDEC Mask       */
+
+// -----------------------------------  CGU_PLL0AUDIO_STAT  ---------------------------------------
+#define CGU_PLL0AUDIO_STAT_LOCK_Pos                           0                                                         /*!< CGU PLL0AUDIO_STAT: LOCK Position   */
+#define CGU_PLL0AUDIO_STAT_LOCK_Msk                           (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos)                   /*!< CGU PLL0AUDIO_STAT: LOCK Mask       */
+#define CGU_PLL0AUDIO_STAT_FR_Pos                             1                                                         /*!< CGU PLL0AUDIO_STAT: FR Position     */
+#define CGU_PLL0AUDIO_STAT_FR_Msk                             (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos)                     /*!< CGU PLL0AUDIO_STAT: FR Mask         */
+
+// -----------------------------------  CGU_PLL0AUDIO_CTRL  ---------------------------------------
+#define CGU_PLL0AUDIO_CTRL_PD_Pos                             0                                                         /*!< CGU PLL0AUDIO_CTRL: PD Position     */
+#define CGU_PLL0AUDIO_CTRL_PD_Msk                             (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos)                     /*!< CGU PLL0AUDIO_CTRL: PD Mask         */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos                         1                                                         /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos)                 /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask     */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos                        2                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask    */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos                        3                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask    */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos                          4                                                         /*!< CGU PLL0AUDIO_CTRL: CLKEN Position  */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk                          (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos)                  /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask      */
+#define CGU_PLL0AUDIO_CTRL_FRM_Pos                            6                                                         /*!< CGU PLL0AUDIO_CTRL: FRM Position    */
+#define CGU_PLL0AUDIO_CTRL_FRM_Msk                            (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos)                    /*!< CGU PLL0AUDIO_CTRL: FRM Mask        */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos                      11                                                        /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk                      (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos)              /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask  */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos                    12                                                        /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk                    (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos)            /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos                        13                                                        /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos)                /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask    */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos                         14                                                        /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos)                 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask     */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos                        24                                                        /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk                        (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos)                /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_PLL0AUDIO_MDIV  ---------------------------------------
+#define CGU_PLL0AUDIO_MDIV_MDEC_Pos                           0                                                         /*!< CGU PLL0AUDIO_MDIV: MDEC Position   */
+#define CGU_PLL0AUDIO_MDIV_MDEC_Msk                           (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos)             /*!< CGU PLL0AUDIO_MDIV: MDEC Mask       */
+
+// ----------------------------------  CGU_PLL0AUDIO_NP_DIV  --------------------------------------
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos                         0                                                         /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk                         (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos)                 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask     */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos                         12                                                        /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk                         (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos)           /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask     */
+
+// -----------------------------------  CGU_PLL0AUDIO_FRAC  ---------------------------------------
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos                  0                                                         /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk                  (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos)    /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */
+
+// --------------------------------------  CGU_PLL1_STAT  -----------------------------------------
+#define CGU_PLL1_STAT_LOCK_Pos                                0                                                         /*!< CGU PLL1_STAT: LOCK Position        */
+#define CGU_PLL1_STAT_LOCK_Msk                                (0x01UL << CGU_PLL1_STAT_LOCK_Pos)                        /*!< CGU PLL1_STAT: LOCK Mask            */
+
+// --------------------------------------  CGU_PLL1_CTRL  -----------------------------------------
+#define CGU_PLL1_CTRL_PD_Pos                                  0                                                         /*!< CGU PLL1_CTRL: PD Position          */
+#define CGU_PLL1_CTRL_PD_Msk                                  (0x01UL << CGU_PLL1_CTRL_PD_Pos)                          /*!< CGU PLL1_CTRL: PD Mask              */
+#define CGU_PLL1_CTRL_BYPASS_Pos                              1                                                         /*!< CGU PLL1_CTRL: BYPASS Position      */
+#define CGU_PLL1_CTRL_BYPASS_Msk                              (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos)                      /*!< CGU PLL1_CTRL: BYPASS Mask          */
+#define CGU_PLL1_CTRL_FBSEL_Pos                               6                                                         /*!< CGU PLL1_CTRL: FBSEL Position       */
+#define CGU_PLL1_CTRL_FBSEL_Msk                               (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos)                       /*!< CGU PLL1_CTRL: FBSEL Mask           */
+#define CGU_PLL1_CTRL_DIRECT_Pos                              7                                                         /*!< CGU PLL1_CTRL: DIRECT Position      */
+#define CGU_PLL1_CTRL_DIRECT_Msk                              (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos)                      /*!< CGU PLL1_CTRL: DIRECT Mask          */
+#define CGU_PLL1_CTRL_PSEL_Pos                                8                                                         /*!< CGU PLL1_CTRL: PSEL Position        */
+#define CGU_PLL1_CTRL_PSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_PSEL_Pos)                        /*!< CGU PLL1_CTRL: PSEL Mask            */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Pos                           11                                                        /*!< CGU PLL1_CTRL: AUTOBLOCK Position   */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Msk                           (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos)                   /*!< CGU PLL1_CTRL: AUTOBLOCK Mask       */
+#define CGU_PLL1_CTRL_NSEL_Pos                                12                                                        /*!< CGU PLL1_CTRL: NSEL Position        */
+#define CGU_PLL1_CTRL_NSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_NSEL_Pos)                        /*!< CGU PLL1_CTRL: NSEL Mask            */
+#define CGU_PLL1_CTRL_MSEL_Pos                                16                                                        /*!< CGU PLL1_CTRL: MSEL Position        */
+#define CGU_PLL1_CTRL_MSEL_Msk                                (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos)                  /*!< CGU PLL1_CTRL: MSEL Mask            */
+#define CGU_PLL1_CTRL_CLK_SEL_Pos                             24                                                        /*!< CGU PLL1_CTRL: CLK_SEL Position     */
+#define CGU_PLL1_CTRL_CLK_SEL_Msk                             (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos)                     /*!< CGU PLL1_CTRL: CLK_SEL Mask         */
+
+// -------------------------------------  CGU_IDIVA_CTRL  -----------------------------------------
+#define CGU_IDIVA_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVA_CTRL: PD Position         */
+#define CGU_IDIVA_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVA_CTRL_PD_Pos)                         /*!< CGU IDIVA_CTRL: PD Mask             */
+#define CGU_IDIVA_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVA_CTRL: IDIV Position       */
+#define CGU_IDIVA_CTRL_IDIV_Msk                               (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos)                       /*!< CGU IDIVA_CTRL: IDIV Mask           */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVA_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVA_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVA_CTRL: CLK_SEL Position    */
+#define CGU_IDIVA_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVA_CTRL: CLK_SEL Mask        */
+
+// -------------------------------------  CGU_IDIVB_CTRL  -----------------------------------------
+#define CGU_IDIVB_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVB_CTRL: PD Position         */
+#define CGU_IDIVB_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVB_CTRL_PD_Pos)                         /*!< CGU IDIVB_CTRL: PD Mask             */
+#define CGU_IDIVB_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVB_CTRL: IDIV Position       */
+#define CGU_IDIVB_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos)                       /*!< CGU IDIVB_CTRL: IDIV Mask           */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVB_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVB_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVB_CTRL: CLK_SEL Position    */
+#define CGU_IDIVB_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVB_CTRL: CLK_SEL Mask        */
+
+// -------------------------------------  CGU_IDIVE_CTRL  -----------------------------------------
+#define CGU_IDIVE_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVE_CTRL: PD Position         */
+#define CGU_IDIVE_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVE_CTRL_PD_Pos)                         /*!< CGU IDIVE_CTRL: PD Mask             */
+#define CGU_IDIVE_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVE_CTRL: IDIV Position       */
+#define CGU_IDIVE_CTRL_IDIV_Msk                               (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos)                 /*!< CGU IDIVE_CTRL: IDIV Mask           */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVE_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVE_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVE_CTRL: CLK_SEL Position    */
+#define CGU_IDIVE_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVE_CTRL: CLK_SEL Mask        */
+
+// ------------------------------------  CGU_BASE_SAFE_CLK  ---------------------------------------
+#define CGU_BASE_SAFE_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SAFE_CLK: PD Position      */
+#define CGU_BASE_SAFE_CLK_PD_Msk                              (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos)                      /*!< CGU BASE_SAFE_CLK: PD Mask          */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_USB0_CLK  ---------------------------------------
+#define CGU_BASE_USB0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB0_CLK: PD Position      */
+#define CGU_BASE_USB0_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB0_CLK_PD_Pos)                      /*!< CGU BASE_USB0_CLK: PD Mask          */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB0_CLK: CLK_SEL Position */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB0_CLK: CLK_SEL Mask     */
+
+// -----------------------------------  CGU_BASE_PERIPH_CLK  --------------------------------------
+#define CGU_BASE_PERIPH_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PERIPH_CLK: PD Position    */
+#define CGU_BASE_PERIPH_CLK_PD_Msk                            (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos)                    /*!< CGU BASE_PERIPH_CLK: PD Mask        */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask   */
+
+// ------------------------------------  CGU_BASE_USB1_CLK  ---------------------------------------
+#define CGU_BASE_USB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB1_CLK: PD Position      */
+#define CGU_BASE_USB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB1_CLK_PD_Pos)                      /*!< CGU BASE_USB1_CLK: PD Mask          */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB1_CLK: CLK_SEL Position */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB1_CLK: CLK_SEL Mask     */
+
+// -------------------------------------  CGU_BASE_M4_CLK  ----------------------------------------
+#define CGU_BASE_M4_CLK_PD_Pos                                0                                                         /*!< CGU BASE_M4_CLK: PD Position        */
+#define CGU_BASE_M4_CLK_PD_Msk                                (0x01UL << CGU_BASE_M4_CLK_PD_Pos)                        /*!< CGU BASE_M4_CLK: PD Mask            */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos                         11                                                        /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk                         (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos)                 /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask     */
+#define CGU_BASE_M4_CLK_CLK_SEL_Pos                           24                                                        /*!< CGU BASE_M4_CLK: CLK_SEL Position   */
+#define CGU_BASE_M4_CLK_CLK_SEL_Msk                           (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos)                   /*!< CGU BASE_M4_CLK: CLK_SEL Mask       */
+
+// -----------------------------------  CGU_BASE_SPIFI_CLK  ---------------------------------------
+#define CGU_BASE_SPIFI_CLK_PD_Pos                             0                                                         /*!< CGU BASE_SPIFI_CLK: PD Position     */
+#define CGU_BASE_SPIFI_CLK_PD_Msk                             (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos)                     /*!< CGU BASE_SPIFI_CLK: PD Mask         */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos)                /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask    */
+
+// ------------------------------------  CGU_BASE_SPI_CLK  ----------------------------------------
+#define CGU_BASE_SPI_CLK_PD_Pos                               0                                                         /*!< CGU BASE_SPI_CLK: PD Position       */
+#define CGU_BASE_SPI_CLK_PD_Msk                               (0x01UL << CGU_BASE_SPI_CLK_PD_Pos)                       /*!< CGU BASE_SPI_CLK: PD Mask           */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask    */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_SPI_CLK: CLK_SEL Position  */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_SPI_CLK: CLK_SEL Mask      */
+
+// -----------------------------------  CGU_BASE_PHY_RX_CLK  --------------------------------------
+#define CGU_BASE_PHY_RX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_RX_CLK: PD Position    */
+#define CGU_BASE_PHY_RX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_RX_CLK: PD Mask        */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask   */
+
+// -----------------------------------  CGU_BASE_PHY_TX_CLK  --------------------------------------
+#define CGU_BASE_PHY_TX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_TX_CLK: PD Position    */
+#define CGU_BASE_PHY_TX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_TX_CLK: PD Mask        */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask   */
+
+// ------------------------------------  CGU_BASE_APB1_CLK  ---------------------------------------
+#define CGU_BASE_APB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB1_CLK: PD Position      */
+#define CGU_BASE_APB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB1_CLK_PD_Pos)                      /*!< CGU BASE_APB1_CLK: PD Mask          */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB1_CLK: CLK_SEL Position */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB1_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_APB3_CLK  ---------------------------------------
+#define CGU_BASE_APB3_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB3_CLK: PD Position      */
+#define CGU_BASE_APB3_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB3_CLK_PD_Pos)                      /*!< CGU BASE_APB3_CLK: PD Mask          */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB3_CLK: CLK_SEL Position */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB3_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_LCD_CLK  ----------------------------------------
+#define CGU_BASE_LCD_CLK_PD_Pos                               0                                                         /*!< CGU BASE_LCD_CLK: PD Position       */
+#define CGU_BASE_LCD_CLK_PD_Msk                               (0x01UL << CGU_BASE_LCD_CLK_PD_Pos)                       /*!< CGU BASE_LCD_CLK: PD Mask           */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask    */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_LCD_CLK: CLK_SEL Position  */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_LCD_CLK: CLK_SEL Mask      */
+
+// ------------------------------------  CGU_BASE_SDIO_CLK  ---------------------------------------
+#define CGU_BASE_SDIO_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SDIO_CLK: PD Position      */
+#define CGU_BASE_SDIO_CLK_PD_Msk                              (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos)                      /*!< CGU BASE_SDIO_CLK: PD Mask          */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_SSP0_CLK  ---------------------------------------
+#define CGU_BASE_SSP0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP0_CLK: PD Position      */
+#define CGU_BASE_SSP0_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos)                      /*!< CGU BASE_SSP0_CLK: PD Mask          */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask     */
+
+// ------------------------------------  CGU_BASE_SSP1_CLK  ---------------------------------------
+#define CGU_BASE_SSP1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP1_CLK: PD Position      */
+#define CGU_BASE_SSP1_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos)                      /*!< CGU BASE_SSP1_CLK: PD Mask          */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask     */
+
+// -----------------------------------  CGU_BASE_UART0_CLK  ---------------------------------------
+#define CGU_BASE_UART0_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART0_CLK: PD Position     */
+#define CGU_BASE_UART0_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART0_CLK_PD_Pos)                     /*!< CGU BASE_UART0_CLK: PD Mask         */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART0_CLK: CLK_SEL Position */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART0_CLK: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_BASE_UART1_CLK  ---------------------------------------
+#define CGU_BASE_UART1_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART1_CLK: PD Position     */
+#define CGU_BASE_UART1_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART1_CLK_PD_Pos)                     /*!< CGU BASE_UART1_CLK: PD Mask         */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART1_CLK: CLK_SEL Position */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART1_CLK: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_BASE_UART2_CLK  ---------------------------------------
+#define CGU_BASE_UART2_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART2_CLK: PD Position     */
+#define CGU_BASE_UART2_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART2_CLK_PD_Pos)                     /*!< CGU BASE_UART2_CLK: PD Mask         */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART2_CLK: CLK_SEL Position */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART2_CLK: CLK_SEL Mask    */
+
+// -----------------------------------  CGU_BASE_UART3_CLK  ---------------------------------------
+#define CGU_BASE_UART3_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART3_CLK: PD Position     */
+#define CGU_BASE_UART3_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART3_CLK_PD_Pos)                     /*!< CGU BASE_UART3_CLK: PD Mask         */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask  */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART3_CLK: CLK_SEL Position */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART3_CLK: CLK_SEL Mask    */
+
+// ------------------------------------  CGU_BASE_OUT_CLK  ----------------------------------------
+#define CGU_BASE_OUT_CLK_PD_Pos                               0                                                         /*!< CGU BASE_OUT_CLK: PD Position       */
+#define CGU_BASE_OUT_CLK_PD_Msk                               (0x01UL << CGU_BASE_OUT_CLK_PD_Pos)                       /*!< CGU BASE_OUT_CLK: PD Mask           */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask    */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_OUT_CLK: CLK_SEL Position  */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_OUT_CLK: CLK_SEL Mask      */
+
+// ------------------------------------  CGU_BASE_APLL_CLK  ---------------------------------------
+#define CGU_BASE_APLL_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APLL_CLK: PD Position      */
+#define CGU_BASE_APLL_CLK_PD_Msk                              (0x01UL << CGU_BASE_APLL_CLK_PD_Pos)                      /*!< CGU BASE_APLL_CLK: PD Mask          */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask   */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APLL_CLK: CLK_SEL Position */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APLL_CLK: CLK_SEL Mask     */
+
+// ----------------------------------  CGU_BASE_CGU_OUT0_CLK  -------------------------------------
+#define CGU_BASE_CGU_OUT0_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT0_CLK: PD Position  */
+#define CGU_BASE_CGU_OUT0_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT0_CLK: PD Mask      */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */
+
+// ----------------------------------  CGU_BASE_CGU_OUT1_CLK  -------------------------------------
+#define CGU_BASE_CGU_OUT1_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT1_CLK: PD Position  */
+#define CGU_BASE_CGU_OUT1_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT1_CLK: PD Mask      */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */
+
+// -------------------------------------  CGU_IDIVC_CTRL  -----------------------------------------
+#define CGU_IDIVC_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVC_CTRL: PD Position         */
+#define CGU_IDIVC_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVC_CTRL_PD_Pos)                         /*!< CGU IDIVC_CTRL: PD Mask             */
+#define CGU_IDIVC_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVC_CTRL: IDIV Position       */
+#define CGU_IDIVC_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos)                       /*!< CGU IDIVC_CTRL: IDIV Mask           */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVC_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVC_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVC_CTRL: CLK_SEL Position    */
+#define CGU_IDIVC_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVC_CTRL: CLK_SEL Mask        */
+
+// -------------------------------------  CGU_IDIVD_CTRL  -----------------------------------------
+#define CGU_IDIVD_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVD_CTRL: PD Position         */
+#define CGU_IDIVD_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVD_CTRL_PD_Pos)                         /*!< CGU IDIVD_CTRL: PD Mask             */
+#define CGU_IDIVD_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVD_CTRL: IDIV Position       */
+#define CGU_IDIVD_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos)                       /*!< CGU IDIVD_CTRL: IDIV Mask           */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVD_CTRL: AUTOBLOCK Position  */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask      */
+#define CGU_IDIVD_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVD_CTRL: CLK_SEL Position    */
+#define CGU_IDIVD_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVD_CTRL: CLK_SEL Mask        */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 CCU1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  CCU1_PM  --------------------------------------------
+#define CCU1_PM_PD_Pos                                        0                                                         /*!< CCU1 PM: PD Position                */
+#define CCU1_PM_PD_Msk                                        (0x01UL << CCU1_PM_PD_Pos)                                /*!< CCU1 PM: PD Mask                    */
+
+// -------------------------------------  CCU1_BASE_STAT  -----------------------------------------
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos                  0                                                         /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos                  1                                                         /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos                 2                                                         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk                 (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos)         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos                    3                                                         /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk                    (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos)            /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos                  7                                                         /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos                  8                                                         /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */
+
+// ----------------------------------  CCU1_CLK_APB3_BUS_CFG  -------------------------------------
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask     */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask    */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB3_BUS_STAT  -------------------------------------
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask    */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask   */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_I2C1_CFG  -------------------------------------
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_I2C1_STAT  ------------------------------------
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_APB3_DAC_CFG  -------------------------------------
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask     */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask    */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB3_DAC_STAT  -------------------------------------
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask    */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask   */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC0_CFG  -------------------------------------
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC0_STAT  ------------------------------------
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC1_CFG  -------------------------------------
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_ADC1_STAT  ------------------------------------
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_CAN0_CFG  -------------------------------------
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask    */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask   */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB3_CAN0_STAT  ------------------------------------
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask   */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask  */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_APB1_BUS_CFG  -------------------------------------
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask     */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask    */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB1_BUS_STAT  -------------------------------------
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask    */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask   */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */
+
+// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_CFG  ----------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos                  0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk                  (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos)          /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos                 1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos               2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk               (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos)       /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */
+
+// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_STAT  ---------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos                 0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos                1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk                (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos)        /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos              2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk              (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos)      /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_ABP1_I2C0_CFG  -------------------------------------
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos)                /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask    */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos)               /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask   */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB1_I2C0_STAT  ------------------------------------
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask   */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask  */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_APB1_I2S_CFG  -------------------------------------
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask     */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask    */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_APB1_I2S_STAT  -------------------------------------
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask    */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask   */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB1_CAN1_CFG  -------------------------------------
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask    */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask   */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_APB1_CAN1_STAT  ------------------------------------
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask   */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask  */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */
+
+// -----------------------------------  CCU1_CLK_SPIFI_CFG  ---------------------------------------
+#define CCU1_CLK_SPIFI_CFG_RUN_Pos                            0                                                         /*!< CCU1 CLK_SPIFI_CFG: RUN Position    */
+#define CCU1_CLK_SPIFI_CFG_RUN_Msk                            (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos)                    /*!< CCU1 CLK_SPIFI_CFG: RUN Mask        */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Pos                           1                                                         /*!< CCU1 CLK_SPIFI_CFG: AUTO Position   */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Msk                           (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos)                   /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask       */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk                         (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos)                 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask     */
+
+// -----------------------------------  CCU1_CLK_SPIFI_STAT  --------------------------------------
+#define CCU1_CLK_SPIFI_STAT_RUN_Pos                           0                                                         /*!< CCU1 CLK_SPIFI_STAT: RUN Position   */
+#define CCU1_CLK_SPIFI_STAT_RUN_Msk                           (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos)                   /*!< CCU1 CLK_SPIFI_STAT: RUN Mask       */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Pos                          1                                                         /*!< CCU1 CLK_SPIFI_STAT: AUTO Position  */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Msk                          (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos)                  /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask      */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk                        (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos)                /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask    */
+
+// -----------------------------------  CCU1_CLK_M4_BUS_CFG  --------------------------------------
+#define CCU1_CLK_M4_BUS_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_BUS_CFG: RUN Position   */
+#define CCU1_CLK_M4_BUS_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask       */
+#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position  */
+#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_BUS_STAT  --------------------------------------
+#define CCU1_CLK_M4_BUS_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_BUS_STAT: RUN Position  */
+#define CCU1_CLK_M4_BUS_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask      */
+#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */
+#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SPIFI_CFG  -------------------------------------
+#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */
+#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask     */
+#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */
+#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask    */
+#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_SPIFI_STAT  -------------------------------------
+#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */
+#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask    */
+#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */
+#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask   */
+#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_GPIO_CFG  --------------------------------------
+#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position  */
+#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask      */
+#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */
+#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_GPIO_STAT  -------------------------------------
+#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */
+#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask     */
+#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */
+#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_LCD_CFG  --------------------------------------
+#define CCU1_CLK_M4_LCD_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_LCD_CFG: RUN Position   */
+#define CCU1_CLK_M4_LCD_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask       */
+#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position  */
+#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_LCD_STAT  --------------------------------------
+#define CCU1_CLK_M4_LCD_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_LCD_STAT: RUN Position  */
+#define CCU1_CLK_M4_LCD_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask      */
+#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */
+#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask   */
+
+// --------------------------------  CCU1_CLK_M4_ETHERNET_CFG  ------------------------------------
+#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos)              /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask  */
+#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos)             /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */
+#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_M4_ETHERNET_STAT  -----------------------------------
+#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos)             /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */
+#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos)            /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */
+#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_USB0_CFG  --------------------------------------
+#define CCU1_CLK_M4_USB0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB0_CFG: RUN Position  */
+#define CCU1_CLK_M4_USB0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask      */
+#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */
+#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_USB0_STAT  -------------------------------------
+#define CCU1_CLK_M4_USB0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */
+#define CCU1_CLK_M4_USB0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask     */
+#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */
+#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_EMC_CFG  --------------------------------------
+#define CCU1_CLK_M4_EMC_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_EMC_CFG: RUN Position   */
+#define CCU1_CLK_M4_EMC_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask       */
+#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position  */
+#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_EMC_STAT  --------------------------------------
+#define CCU1_CLK_M4_EMC_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_EMC_STAT: RUN Position  */
+#define CCU1_CLK_M4_EMC_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask      */
+#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */
+#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SDIO_CFG  --------------------------------------
+#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position  */
+#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask      */
+#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */
+#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SDIO_STAT  -------------------------------------
+#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */
+#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask     */
+#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */
+#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_DMA_CFG  --------------------------------------
+#define CCU1_CLK_M4_DMA_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_DMA_CFG: RUN Position   */
+#define CCU1_CLK_M4_DMA_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask       */
+#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position  */
+#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_DMA_STAT  --------------------------------------
+#define CCU1_CLK_M4_DMA_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_DMA_STAT: RUN Position  */
+#define CCU1_CLK_M4_DMA_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask      */
+#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */
+#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask   */
+
+// ---------------------------------  CCU1_CLK_M4_M4CORE_CFG  -------------------------------------
+#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */
+#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask    */
+#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */
+#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_M3CORE_STAT  ------------------------------------
+#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Position */
+#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Mask   */
+#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Position */
+#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Mask */
+
+// -----------------------------------  CCU1_CLK_M4_SCT_CFG  --------------------------------------
+#define CCU1_CLK_M4_SCT_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCT_CFG: RUN Position   */
+#define CCU1_CLK_M4_SCT_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask       */
+#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position  */
+#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_SCT_STAT  --------------------------------------
+#define CCU1_CLK_M4_SCT_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCT_STAT: RUN Position  */
+#define CCU1_CLK_M4_SCT_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask      */
+#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */
+#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_USB1_CFG  --------------------------------------
+#define CCU1_CLK_M4_USB1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB1_CFG: RUN Position  */
+#define CCU1_CLK_M4_USB1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask      */
+#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */
+#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_USB1_STAT  -------------------------------------
+#define CCU1_CLK_M4_USB1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */
+#define CCU1_CLK_M4_USB1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask     */
+#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */
+#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_EMCDIV_CFG  -------------------------------------
+#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask    */
+#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_EMCDIV_STAT  ------------------------------------
+#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask   */
+#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_M0APP_CFG  -------------------------------------
+#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */
+#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask     */
+#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */
+#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask    */
+#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_M0APP_STAT  -------------------------------------
+#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */
+#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask    */
+#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */
+#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask   */
+#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_WWDT_CFG  --------------------------------------
+#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position  */
+#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask      */
+#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */
+#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_WWDT_STAT  -------------------------------------
+#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */
+#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask     */
+#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */
+#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_USART0_CFG  -------------------------------------
+#define CCU1_CLK_M4_USART0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */
+#define CCU1_CLK_M4_USART0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask    */
+#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART0_STAT  ------------------------------------
+#define CCU1_CLK_M4_USART0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */
+#define CCU1_CLK_M4_USART0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask   */
+#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_UART1_CFG  -------------------------------------
+#define CCU1_CLK_M4_UART1_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */
+#define CCU1_CLK_M4_UART1_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask     */
+#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */
+#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask    */
+#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_UART1_STAT  -------------------------------------
+#define CCU1_CLK_M4_UART1_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */
+#define CCU1_CLK_M4_UART1_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask    */
+#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */
+#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask   */
+#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_SSP0_CFG  --------------------------------------
+#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position  */
+#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask      */
+#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */
+#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SSP0_STAT  -------------------------------------
+#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */
+#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask     */
+#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */
+#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER0_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER0_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER1_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER1_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */
+
+// -----------------------------------  CCU1_CLK_M4_SCU_CFG  --------------------------------------
+#define CCU1_CLK_M4_SCU_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCU_CFG: RUN Position   */
+#define CCU1_CLK_M4_SCU_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask       */
+#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position  */
+#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_SCU_STAT  --------------------------------------
+#define CCU1_CLK_M4_SCU_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCU_STAT: RUN Position  */
+#define CCU1_CLK_M4_SCU_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask      */
+#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */
+#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_CREG_CFG  --------------------------------------
+#define CCU1_CLK_M4_CREG_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_CREG_CFG: RUN Position  */
+#define CCU1_CLK_M4_CREG_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask      */
+#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */
+#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_CREG_STAT  -------------------------------------
+#define CCU1_CLK_M4_CREG_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */
+#define CCU1_CLK_M4_CREG_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask     */
+#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */
+#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask  */
+
+// ---------------------------------  CCU1_CLK_M4_RITIMER_CFG  ------------------------------------
+#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */
+#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos)               /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask   */
+#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */
+#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos)              /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask  */
+#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_M4_RITIMER_STAT  ------------------------------------
+#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */
+#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos)              /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask  */
+#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */
+#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos)             /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */
+#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART2_CFG  -------------------------------------
+#define CCU1_CLK_M4_USART2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */
+#define CCU1_CLK_M4_USART2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask    */
+#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART2_STAT  ------------------------------------
+#define CCU1_CLK_M4_USART2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */
+#define CCU1_CLK_M4_USART2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask   */
+#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART3_CFG  -------------------------------------
+#define CCU1_CLK_M4_USART3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */
+#define CCU1_CLK_M4_USART3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask    */
+#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_USART3_STAT  ------------------------------------
+#define CCU1_CLK_M4_USART3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */
+#define CCU1_CLK_M4_USART3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask   */
+#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER2_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER2_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER3_CFG  -------------------------------------
+#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask    */
+#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask   */
+#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU1_CLK_M4_TIMER3_STAT  ------------------------------------
+#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask   */
+#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask  */
+#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */
+
+// ----------------------------------  CCU1_CLK_M4_SSP1_CFG  --------------------------------------
+#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position  */
+#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask      */
+#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */
+#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask     */
+#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask   */
+
+// ----------------------------------  CCU1_CLK_M4_SSP1_STAT  -------------------------------------
+#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */
+#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask     */
+#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */
+#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask    */
+#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask  */
+
+// -----------------------------------  CCU1_CLK_M4_QEI_CFG  --------------------------------------
+#define CCU1_CLK_M4_QEI_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_QEI_CFG: RUN Position   */
+#define CCU1_CLK_M4_QEI_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask       */
+#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position  */
+#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask      */
+#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask    */
+
+// ----------------------------------  CCU1_CLK_M4_QEI_STAT  --------------------------------------
+#define CCU1_CLK_M4_QEI_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_QEI_STAT: RUN Position  */
+#define CCU1_CLK_M4_QEI_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask      */
+#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */
+#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask     */
+#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask   */
+
+// ---------------------------------  CCU1_CLK_PERIPH_BUS_CFG  ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos)               /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask   */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos)              /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask  */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_BUS_STAT  ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos)              /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask  */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_CORE_CFG  ------------------------------------
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos)              /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask  */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_CORE_STAT  -----------------------------------
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos)             /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU1_CLK_PERIPH_SGPIO_CFG  -----------------------------------
+#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos)             /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */
+
+// -------------------------------  CCU1_CLK_PERIPH_SGPIO_STAT  -----------------------------------
+#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos                    0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos                   1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk                   (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos)           /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos                 2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk                 (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos)         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */
+
+// ------------------------------------  CCU1_CLK_USB0_CFG  ---------------------------------------
+#define CCU1_CLK_USB0_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB0_CFG: RUN Position     */
+#define CCU1_CLK_USB0_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB0_CFG: RUN Mask         */
+#define CCU1_CLK_USB0_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB0_CFG: AUTO Position    */
+#define CCU1_CLK_USB0_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB0_CFG: AUTO Mask        */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB0_CFG: WAKEUP Position  */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU1_CLK_USB0_STAT  ---------------------------------------
+#define CCU1_CLK_USB0_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB0_STAT: RUN Position    */
+#define CCU1_CLK_USB0_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB0_STAT: RUN Mask        */
+#define CCU1_CLK_USB0_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB0_STAT: AUTO Position   */
+#define CCU1_CLK_USB0_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB0_STAT: AUTO Mask       */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask     */
+
+// ------------------------------------  CCU1_CLK_USB1_CFG  ---------------------------------------
+#define CCU1_CLK_USB1_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB1_CFG: RUN Position     */
+#define CCU1_CLK_USB1_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB1_CFG: RUN Mask         */
+#define CCU1_CLK_USB1_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB1_CFG: AUTO Position    */
+#define CCU1_CLK_USB1_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB1_CFG: AUTO Mask        */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB1_CFG: WAKEUP Position  */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU1_CLK_USB1_STAT  ---------------------------------------
+#define CCU1_CLK_USB1_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB1_STAT: RUN Position    */
+#define CCU1_CLK_USB1_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB1_STAT: RUN Mask        */
+#define CCU1_CLK_USB1_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB1_STAT: AUTO Position   */
+#define CCU1_CLK_USB1_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB1_STAT: AUTO Mask       */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask     */
+
+// ------------------------------------  CCU1_CLK_SPI_CFG  ----------------------------------------
+#define CCU1_CLK_SPI_CFG_RUN_Pos                              0                                                         /*!< CCU1 CLK_SPI_CFG: RUN Position      */
+#define CCU1_CLK_SPI_CFG_RUN_Msk                              (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos)                      /*!< CCU1 CLK_SPI_CFG: RUN Mask          */
+#define CCU1_CLK_SPI_CFG_AUTO_Pos                             1                                                         /*!< CCU1 CLK_SPI_CFG: AUTO Position     */
+#define CCU1_CLK_SPI_CFG_AUTO_Msk                             (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos)                     /*!< CCU1 CLK_SPI_CFG: AUTO Mask         */
+#define CCU1_CLK_SPI_CFG_WAKEUP_Pos                           2                                                         /*!< CCU1 CLK_SPI_CFG: WAKEUP Position   */
+#define CCU1_CLK_SPI_CFG_WAKEUP_Msk                           (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos)                   /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask       */
+
+// ------------------------------------  CCU1_CLK_SPI_STAT  ---------------------------------------
+#define CCU1_CLK_SPI_STAT_RUN_Pos                             0                                                         /*!< CCU1 CLK_SPI_STAT: RUN Position     */
+#define CCU1_CLK_SPI_STAT_RUN_Msk                             (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos)                     /*!< CCU1 CLK_SPI_STAT: RUN Mask         */
+#define CCU1_CLK_SPI_STAT_AUTO_Pos                            1                                                         /*!< CCU1 CLK_SPI_STAT: AUTO Position    */
+#define CCU1_CLK_SPI_STAT_AUTO_Msk                            (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos)                    /*!< CCU1 CLK_SPI_STAT: AUTO Mask        */
+#define CCU1_CLK_SPI_STAT_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_SPI_STAT: WAKEUP Position  */
+#define CCU1_CLK_SPI_STAT_WAKEUP_Msk                          (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos)                  /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask      */
+
+// ------------------------------------  CCU1_CLK_VADC_CFG  ---------------------------------------
+#define CCU1_CLK_VADC_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_VADC_CFG: RUN Position     */
+#define CCU1_CLK_VADC_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos)                     /*!< CCU1 CLK_VADC_CFG: RUN Mask         */
+#define CCU1_CLK_VADC_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_VADC_CFG: AUTO Position    */
+#define CCU1_CLK_VADC_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos)                    /*!< CCU1 CLK_VADC_CFG: AUTO Mask        */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_VADC_CFG: WAKEUP Position  */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU1_CLK_VADC_STAT  ---------------------------------------
+#define CCU1_CLK_VADC_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_VADC_STAT: RUN Position    */
+#define CCU1_CLK_VADC_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos)                    /*!< CCU1 CLK_VADC_STAT: RUN Mask        */
+#define CCU1_CLK_VADC_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_VADC_STAT: AUTO Position   */
+#define CCU1_CLK_VADC_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos)                   /*!< CCU1 CLK_VADC_STAT: AUTO Mask       */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 CCU2 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  CCU2_PM  --------------------------------------------
+#define CCU2_PM_PD_Pos                                        0                                                         /*!< CCU2 PM: PD Position                */
+#define CCU2_PM_PD_Msk                                        (0x01UL << CCU2_PM_PD_Pos)                                /*!< CCU2 PM: PD Mask                    */
+
+// -------------------------------------  CCU2_BASE_STAT  -----------------------------------------
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos                     1                                                         /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos                     2                                                         /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos                     3                                                         /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos                     4                                                         /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos                      5                                                         /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask  */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos                      6                                                         /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask  */
+
+// ------------------------------------  CCU2_CLK_APLL_CFG  ---------------------------------------
+#define CCU2_CLK_APLL_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_APLL_CFG: RUN Position     */
+#define CCU2_CLK_APLL_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos)                     /*!< CCU2 CLK_APLL_CFG: RUN Mask         */
+#define CCU2_CLK_APLL_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_APLL_CFG: AUTO Position    */
+#define CCU2_CLK_APLL_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos)                    /*!< CCU2 CLK_APLL_CFG: AUTO Mask        */
+#define CCU2_CLK_APLL_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_APLL_CFG: WAKEUP Position  */
+#define CCU2_CLK_APLL_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_APLL_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU2_CLK_APLL_STAT  ---------------------------------------
+#define CCU2_CLK_APLL_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_APLL_STAT: RUN Position    */
+#define CCU2_CLK_APLL_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos)                    /*!< CCU2 CLK_APLL_STAT: RUN Mask        */
+#define CCU2_CLK_APLL_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_APLL_STAT: AUTO Position   */
+#define CCU2_CLK_APLL_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos)                   /*!< CCU2 CLK_APLL_STAT: AUTO Mask       */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask     */
+
+// --------------------------------  CCU2_CLK_APB2_USART3_CFG  ------------------------------------
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask  */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB2_USART3_STAT  -----------------------------------
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB2_USART2_CFG  ------------------------------------
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask  */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB2_USART2_STAT  -----------------------------------
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */
+
+// -------------------------------  CCU2_CLK_APB0_UART1_BUS_CFG  ----------------------------------
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos                   0                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos)           /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos                  1                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk                  (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos)          /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos                2                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk                (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos)        /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB0_UART1_STAT  ------------------------------------
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos)              /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask  */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos)             /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB0_USART0_CFG  ------------------------------------
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos)              /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask  */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */
+
+// --------------------------------  CCU2_CLK_APB0_USART0_STAT  -----------------------------------
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos)             /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB2_SSP1_CFG  -------------------------------------
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos)                /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask    */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask   */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB2_SSP1_STAT  ------------------------------------
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos)               /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask   */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask  */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB0_SSP0_CFG  -------------------------------------
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos)                /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask    */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask   */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */
+
+// ---------------------------------  CCU2_CLK_APB0_SSP0_STAT  ------------------------------------
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos)               /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask   */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask  */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */
+
+// ------------------------------------  CCU2_CLK_SDIO_CFG  ---------------------------------------
+#define CCU2_CLK_SDIO_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_SDIO_CFG: RUN Position     */
+#define CCU2_CLK_SDIO_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos)                     /*!< CCU2 CLK_SDIO_CFG: RUN Mask         */
+#define CCU2_CLK_SDIO_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_SDIO_CFG: AUTO Position    */
+#define CCU2_CLK_SDIO_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos)                    /*!< CCU2 CLK_SDIO_CFG: AUTO Mask        */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position  */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask      */
+
+// -----------------------------------  CCU2_CLK_SDIO_STAT  ---------------------------------------
+#define CCU2_CLK_SDIO_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_SDIO_STAT: RUN Position    */
+#define CCU2_CLK_SDIO_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos)                    /*!< CCU2 CLK_SDIO_STAT: RUN Mask        */
+#define CCU2_CLK_SDIO_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_SDIO_STAT: AUTO Position   */
+#define CCU2_CLK_SDIO_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos)                   /*!< CCU2 CLK_SDIO_STAT: AUTO Mask       */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  RGU Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  RGU_RESET_CTRL0  ----------------------------------------
+#define RGU_RESET_CTRL0_CORE_RST_Pos                          0                                                         /*!< RGU RESET_CTRL0: CORE_RST Position  */
+#define RGU_RESET_CTRL0_CORE_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos)                  /*!< RGU RESET_CTRL0: CORE_RST Mask      */
+#define RGU_RESET_CTRL0_PERIPH_RST_Pos                        1                                                         /*!< RGU RESET_CTRL0: PERIPH_RST Position */
+#define RGU_RESET_CTRL0_PERIPH_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos)                /*!< RGU RESET_CTRL0: PERIPH_RST Mask    */
+#define RGU_RESET_CTRL0_MASTER_RST_Pos                        2                                                         /*!< RGU RESET_CTRL0: MASTER_RST Position */
+#define RGU_RESET_CTRL0_MASTER_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos)                /*!< RGU RESET_CTRL0: MASTER_RST Mask    */
+#define RGU_RESET_CTRL0_WWDT_RST_Pos                          4                                                         /*!< RGU RESET_CTRL0: WWDT_RST Position  */
+#define RGU_RESET_CTRL0_WWDT_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos)                  /*!< RGU RESET_CTRL0: WWDT_RST Mask      */
+#define RGU_RESET_CTRL0_CREG_RST_Pos                          5                                                         /*!< RGU RESET_CTRL0: CREG_RST Position  */
+#define RGU_RESET_CTRL0_CREG_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos)                  /*!< RGU RESET_CTRL0: CREG_RST Mask      */
+#define RGU_RESET_CTRL0_BUS_RST_Pos                           8                                                         /*!< RGU RESET_CTRL0: BUS_RST Position   */
+#define RGU_RESET_CTRL0_BUS_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos)                   /*!< RGU RESET_CTRL0: BUS_RST Mask       */
+#define RGU_RESET_CTRL0_SCU_RST_Pos                           9                                                         /*!< RGU RESET_CTRL0: SCU_RST Position   */
+#define RGU_RESET_CTRL0_SCU_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos)                   /*!< RGU RESET_CTRL0: SCU_RST Mask       */
+#define RGU_RESET_CTRL0_PINMUX_RST_Pos                        10                                                        /*!< RGU RESET_CTRL0: PINMUX_RST Position */
+#define RGU_RESET_CTRL0_PINMUX_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos)                /*!< RGU RESET_CTRL0: PINMUX_RST Mask    */
+#define RGU_RESET_CTRL0_M4_RST_Pos                            13                                                        /*!< RGU RESET_CTRL0: M4_RST Position    */
+#define RGU_RESET_CTRL0_M4_RST_Msk                            (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos)                    /*!< RGU RESET_CTRL0: M4_RST Mask        */
+#define RGU_RESET_CTRL0_LCD_RST_Pos                           16                                                        /*!< RGU RESET_CTRL0: LCD_RST Position   */
+#define RGU_RESET_CTRL0_LCD_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos)                   /*!< RGU RESET_CTRL0: LCD_RST Mask       */
+#define RGU_RESET_CTRL0_USB0_RST_Pos                          17                                                        /*!< RGU RESET_CTRL0: USB0_RST Position  */
+#define RGU_RESET_CTRL0_USB0_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos)                  /*!< RGU RESET_CTRL0: USB0_RST Mask      */
+#define RGU_RESET_CTRL0_USB1_RST_Pos                          18                                                        /*!< RGU RESET_CTRL0: USB1_RST Position  */
+#define RGU_RESET_CTRL0_USB1_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos)                  /*!< RGU RESET_CTRL0: USB1_RST Mask      */
+#define RGU_RESET_CTRL0_DMA_RST_Pos                           19                                                        /*!< RGU RESET_CTRL0: DMA_RST Position   */
+#define RGU_RESET_CTRL0_DMA_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos)                   /*!< RGU RESET_CTRL0: DMA_RST Mask       */
+#define RGU_RESET_CTRL0_SDIO_RST_Pos                          20                                                        /*!< RGU RESET_CTRL0: SDIO_RST Position  */
+#define RGU_RESET_CTRL0_SDIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos)                  /*!< RGU RESET_CTRL0: SDIO_RST Mask      */
+#define RGU_RESET_CTRL0_EMC_RST_Pos                           21                                                        /*!< RGU RESET_CTRL0: EMC_RST Position   */
+#define RGU_RESET_CTRL0_EMC_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos)                   /*!< RGU RESET_CTRL0: EMC_RST Mask       */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Pos                      22                                                        /*!< RGU RESET_CTRL0: ETHERNET_RST Position */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Msk                      (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos)              /*!< RGU RESET_CTRL0: ETHERNET_RST Mask  */
+#define RGU_RESET_CTRL0_GPIO_RST_Pos                          28                                                        /*!< RGU RESET_CTRL0: GPIO_RST Position  */
+#define RGU_RESET_CTRL0_GPIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos)                  /*!< RGU RESET_CTRL0: GPIO_RST Mask      */
+
+// -------------------------------------  RGU_RESET_CTRL1  ----------------------------------------
+#define RGU_RESET_CTRL1_TIMER0_RST_Pos                        0                                                         /*!< RGU RESET_CTRL1: TIMER0_RST Position */
+#define RGU_RESET_CTRL1_TIMER0_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER0_RST Mask    */
+#define RGU_RESET_CTRL1_TIMER1_RST_Pos                        1                                                         /*!< RGU RESET_CTRL1: TIMER1_RST Position */
+#define RGU_RESET_CTRL1_TIMER1_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER1_RST Mask    */
+#define RGU_RESET_CTRL1_TIMER2_RST_Pos                        2                                                         /*!< RGU RESET_CTRL1: TIMER2_RST Position */
+#define RGU_RESET_CTRL1_TIMER2_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER2_RST Mask    */
+#define RGU_RESET_CTRL1_TIMER3_RST_Pos                        3                                                         /*!< RGU RESET_CTRL1: TIMER3_RST Position */
+#define RGU_RESET_CTRL1_TIMER3_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER3_RST Mask    */
+#define RGU_RESET_CTRL1_RITIMER_RST_Pos                       4                                                         /*!< RGU RESET_CTRL1: RITIMER_RST Position */
+#define RGU_RESET_CTRL1_RITIMER_RST_Msk                       (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos)               /*!< RGU RESET_CTRL1: RITIMER_RST Mask   */
+#define RGU_RESET_CTRL1_SCT_RST_Pos                           5                                                         /*!< RGU RESET_CTRL1: SCT_RST Position   */
+#define RGU_RESET_CTRL1_SCT_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos)                   /*!< RGU RESET_CTRL1: SCT_RST Mask       */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos                    6                                                         /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk                    (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos)            /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_CTRL1_QEI_RST_Pos                           7                                                         /*!< RGU RESET_CTRL1: QEI_RST Position   */
+#define RGU_RESET_CTRL1_QEI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos)                   /*!< RGU RESET_CTRL1: QEI_RST Mask       */
+#define RGU_RESET_CTRL1_ADC0_RST_Pos                          8                                                         /*!< RGU RESET_CTRL1: ADC0_RST Position  */
+#define RGU_RESET_CTRL1_ADC0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC0_RST Mask      */
+#define RGU_RESET_CTRL1_ADC1_RST_Pos                          9                                                         /*!< RGU RESET_CTRL1: ADC1_RST Position  */
+#define RGU_RESET_CTRL1_ADC1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC1_RST Mask      */
+#define RGU_RESET_CTRL1_DAC_RST_Pos                           10                                                        /*!< RGU RESET_CTRL1: DAC_RST Position   */
+#define RGU_RESET_CTRL1_DAC_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos)                   /*!< RGU RESET_CTRL1: DAC_RST Mask       */
+#define RGU_RESET_CTRL1_UART0_RST_Pos                         12                                                        /*!< RGU RESET_CTRL1: UART0_RST Position */
+#define RGU_RESET_CTRL1_UART0_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos)                 /*!< RGU RESET_CTRL1: UART0_RST Mask     */
+#define RGU_RESET_CTRL1_UART1_RST_Pos                         13                                                        /*!< RGU RESET_CTRL1: UART1_RST Position */
+#define RGU_RESET_CTRL1_UART1_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos)                 /*!< RGU RESET_CTRL1: UART1_RST Mask     */
+#define RGU_RESET_CTRL1_UART2_RST_Pos                         14                                                        /*!< RGU RESET_CTRL1: UART2_RST Position */
+#define RGU_RESET_CTRL1_UART2_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos)                 /*!< RGU RESET_CTRL1: UART2_RST Mask     */
+#define RGU_RESET_CTRL1_UART3_RST_Pos                         15                                                        /*!< RGU RESET_CTRL1: UART3_RST Position */
+#define RGU_RESET_CTRL1_UART3_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos)                 /*!< RGU RESET_CTRL1: UART3_RST Mask     */
+#define RGU_RESET_CTRL1_I2C0_RST_Pos                          16                                                        /*!< RGU RESET_CTRL1: I2C0_RST Position  */
+#define RGU_RESET_CTRL1_I2C0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C0_RST Mask      */
+#define RGU_RESET_CTRL1_I2C1_RST_Pos                          17                                                        /*!< RGU RESET_CTRL1: I2C1_RST Position  */
+#define RGU_RESET_CTRL1_I2C1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C1_RST Mask      */
+#define RGU_RESET_CTRL1_SSP0_RST_Pos                          18                                                        /*!< RGU RESET_CTRL1: SSP0_RST Position  */
+#define RGU_RESET_CTRL1_SSP0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP0_RST Mask      */
+#define RGU_RESET_CTRL1_SSP1_RST_Pos                          19                                                        /*!< RGU RESET_CTRL1: SSP1_RST Position  */
+#define RGU_RESET_CTRL1_SSP1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP1_RST Mask      */
+#define RGU_RESET_CTRL1_I2S_RST_Pos                           20                                                        /*!< RGU RESET_CTRL1: I2S_RST Position   */
+#define RGU_RESET_CTRL1_I2S_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos)                   /*!< RGU RESET_CTRL1: I2S_RST Mask       */
+#define RGU_RESET_CTRL1_SPIFI_RST_Pos                         21                                                        /*!< RGU RESET_CTRL1: SPIFI_RST Position */
+#define RGU_RESET_CTRL1_SPIFI_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos)                 /*!< RGU RESET_CTRL1: SPIFI_RST Mask     */
+#define RGU_RESET_CTRL1_CAN1_RST_Pos                          22                                                        /*!< RGU RESET_CTRL1: CAN1_RST Position  */
+#define RGU_RESET_CTRL1_CAN1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN1_RST Mask      */
+#define RGU_RESET_CTRL1_CAN0_RST_Pos                          23                                                        /*!< RGU RESET_CTRL1: CAN0_RST Position  */
+#define RGU_RESET_CTRL1_CAN0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN0_RST Mask      */
+#define RGU_RESET_CTRL1_M0APP_RST_Pos                         24                                                        /*!< RGU RESET_CTRL1: M0APP_RST Position */
+#define RGU_RESET_CTRL1_M0APP_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos)                 /*!< RGU RESET_CTRL1: M0APP_RST Mask     */
+#define RGU_RESET_CTRL1_SGPIO_RST_Pos                         25                                                        /*!< RGU RESET_CTRL1: SGPIO_RST Position */
+#define RGU_RESET_CTRL1_SGPIO_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos)                 /*!< RGU RESET_CTRL1: SGPIO_RST Mask     */
+#define RGU_RESET_CTRL1_SPI_RST_Pos                           26                                                        /*!< RGU RESET_CTRL1: SPI_RST Position   */
+#define RGU_RESET_CTRL1_SPI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos)                   /*!< RGU RESET_CTRL1: SPI_RST Mask       */
+
+// ------------------------------------  RGU_RESET_STATUS0  ---------------------------------------
+#define RGU_RESET_STATUS0_CORE_RST_Pos                        0                                                         /*!< RGU RESET_STATUS0: CORE_RST Position */
+#define RGU_RESET_STATUS0_CORE_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos)                /*!< RGU RESET_STATUS0: CORE_RST Mask    */
+#define RGU_RESET_STATUS0_PERIPH_RST_Pos                      2                                                         /*!< RGU RESET_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_STATUS0_PERIPH_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos)              /*!< RGU RESET_STATUS0: PERIPH_RST Mask  */
+#define RGU_RESET_STATUS0_MASTER_RST_Pos                      4                                                         /*!< RGU RESET_STATUS0: MASTER_RST Position */
+#define RGU_RESET_STATUS0_MASTER_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos)              /*!< RGU RESET_STATUS0: MASTER_RST Mask  */
+#define RGU_RESET_STATUS0_WWDT_RST_Pos                        8                                                         /*!< RGU RESET_STATUS0: WWDT_RST Position */
+#define RGU_RESET_STATUS0_WWDT_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos)                /*!< RGU RESET_STATUS0: WWDT_RST Mask    */
+#define RGU_RESET_STATUS0_CREG_RST_Pos                        10                                                        /*!< RGU RESET_STATUS0: CREG_RST Position */
+#define RGU_RESET_STATUS0_CREG_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos)                /*!< RGU RESET_STATUS0: CREG_RST Mask    */
+#define RGU_RESET_STATUS0_BUS_RST_Pos                         16                                                        /*!< RGU RESET_STATUS0: BUS_RST Position */
+#define RGU_RESET_STATUS0_BUS_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos)                 /*!< RGU RESET_STATUS0: BUS_RST Mask     */
+#define RGU_RESET_STATUS0_SCU_RST_Pos                         18                                                        /*!< RGU RESET_STATUS0: SCU_RST Position */
+#define RGU_RESET_STATUS0_SCU_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos)                 /*!< RGU RESET_STATUS0: SCU_RST Mask     */
+#define RGU_RESET_STATUS0_M4_RST_Pos                          26                                                        /*!< RGU RESET_STATUS0: M4_RST Position  */
+#define RGU_RESET_STATUS0_M4_RST_Msk                          (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos)                  /*!< RGU RESET_STATUS0: M4_RST Mask      */
+
+// ------------------------------------  RGU_RESET_STATUS1  ---------------------------------------
+#define RGU_RESET_STATUS1_LCD_RST_Pos                         0                                                         /*!< RGU RESET_STATUS1: LCD_RST Position */
+#define RGU_RESET_STATUS1_LCD_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos)                 /*!< RGU RESET_STATUS1: LCD_RST Mask     */
+#define RGU_RESET_STATUS1_USB0_RST_Pos                        2                                                         /*!< RGU RESET_STATUS1: USB0_RST Position */
+#define RGU_RESET_STATUS1_USB0_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos)                /*!< RGU RESET_STATUS1: USB0_RST Mask    */
+#define RGU_RESET_STATUS1_USB1_RST_Pos                        4                                                         /*!< RGU RESET_STATUS1: USB1_RST Position */
+#define RGU_RESET_STATUS1_USB1_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos)                /*!< RGU RESET_STATUS1: USB1_RST Mask    */
+#define RGU_RESET_STATUS1_DMA_RST_Pos                         6                                                         /*!< RGU RESET_STATUS1: DMA_RST Position */
+#define RGU_RESET_STATUS1_DMA_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos)                 /*!< RGU RESET_STATUS1: DMA_RST Mask     */
+#define RGU_RESET_STATUS1_SDIO_RST_Pos                        8                                                         /*!< RGU RESET_STATUS1: SDIO_RST Position */
+#define RGU_RESET_STATUS1_SDIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos)                /*!< RGU RESET_STATUS1: SDIO_RST Mask    */
+#define RGU_RESET_STATUS1_EMC_RST_Pos                         10                                                        /*!< RGU RESET_STATUS1: EMC_RST Position */
+#define RGU_RESET_STATUS1_EMC_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos)                 /*!< RGU RESET_STATUS1: EMC_RST Mask     */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Pos                    12                                                        /*!< RGU RESET_STATUS1: ETHERNET_RST Position */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Msk                    (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos)            /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */
+#define RGU_RESET_STATUS1_GPIO_RST_Pos                        24                                                        /*!< RGU RESET_STATUS1: GPIO_RST Position */
+#define RGU_RESET_STATUS1_GPIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos)                /*!< RGU RESET_STATUS1: GPIO_RST Mask    */
+
+// ------------------------------------  RGU_RESET_STATUS2  ---------------------------------------
+#define RGU_RESET_STATUS2_TIMER0_RST_Pos                      0                                                         /*!< RGU RESET_STATUS2: TIMER0_RST Position */
+#define RGU_RESET_STATUS2_TIMER0_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER0_RST Mask  */
+#define RGU_RESET_STATUS2_TIMER1_RST_Pos                      2                                                         /*!< RGU RESET_STATUS2: TIMER1_RST Position */
+#define RGU_RESET_STATUS2_TIMER1_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER1_RST Mask  */
+#define RGU_RESET_STATUS2_TIMER2_RST_Pos                      4                                                         /*!< RGU RESET_STATUS2: TIMER2_RST Position */
+#define RGU_RESET_STATUS2_TIMER2_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER2_RST Mask  */
+#define RGU_RESET_STATUS2_TIMER3_RST_Pos                      6                                                         /*!< RGU RESET_STATUS2: TIMER3_RST Position */
+#define RGU_RESET_STATUS2_TIMER3_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER3_RST Mask  */
+#define RGU_RESET_STATUS2_RITIMER_RST_Pos                     8                                                         /*!< RGU RESET_STATUS2: RITIMER_RST Position */
+#define RGU_RESET_STATUS2_RITIMER_RST_Msk                     (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos)             /*!< RGU RESET_STATUS2: RITIMER_RST Mask */
+#define RGU_RESET_STATUS2_SCT_RST_Pos                         10                                                        /*!< RGU RESET_STATUS2: SCT_RST Position */
+#define RGU_RESET_STATUS2_SCT_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos)                 /*!< RGU RESET_STATUS2: SCT_RST Mask     */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos                  12                                                        /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk                  (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos)          /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */
+#define RGU_RESET_STATUS2_QEI_RST_Pos                         14                                                        /*!< RGU RESET_STATUS2: QEI_RST Position */
+#define RGU_RESET_STATUS2_QEI_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos)                 /*!< RGU RESET_STATUS2: QEI_RST Mask     */
+#define RGU_RESET_STATUS2_ADC0_RST_Pos                        16                                                        /*!< RGU RESET_STATUS2: ADC0_RST Position */
+#define RGU_RESET_STATUS2_ADC0_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos)                /*!< RGU RESET_STATUS2: ADC0_RST Mask    */
+#define RGU_RESET_STATUS2_ADC1_RST_Pos                        18                                                        /*!< RGU RESET_STATUS2: ADC1_RST Position */
+#define RGU_RESET_STATUS2_ADC1_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos)                /*!< RGU RESET_STATUS2: ADC1_RST Mask    */
+#define RGU_RESET_STATUS2_DAC_RST_Pos                         20                                                        /*!< RGU RESET_STATUS2: DAC_RST Position */
+#define RGU_RESET_STATUS2_DAC_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos)                 /*!< RGU RESET_STATUS2: DAC_RST Mask     */
+#define RGU_RESET_STATUS2_UART0_RST_Pos                       24                                                        /*!< RGU RESET_STATUS2: UART0_RST Position */
+#define RGU_RESET_STATUS2_UART0_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos)               /*!< RGU RESET_STATUS2: UART0_RST Mask   */
+#define RGU_RESET_STATUS2_UART1_RST_Pos                       26                                                        /*!< RGU RESET_STATUS2: UART1_RST Position */
+#define RGU_RESET_STATUS2_UART1_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos)               /*!< RGU RESET_STATUS2: UART1_RST Mask   */
+#define RGU_RESET_STATUS2_UART2_RST_Pos                       28                                                        /*!< RGU RESET_STATUS2: UART2_RST Position */
+#define RGU_RESET_STATUS2_UART2_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos)               /*!< RGU RESET_STATUS2: UART2_RST Mask   */
+#define RGU_RESET_STATUS2_UART3_RST_Pos                       30                                                        /*!< RGU RESET_STATUS2: UART3_RST Position */
+#define RGU_RESET_STATUS2_UART3_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos)               /*!< RGU RESET_STATUS2: UART3_RST Mask   */
+
+// ------------------------------------  RGU_RESET_STATUS3  ---------------------------------------
+#define RGU_RESET_STATUS3_I2C0_RST_Pos                        0                                                         /*!< RGU RESET_STATUS3: I2C0_RST Position */
+#define RGU_RESET_STATUS3_I2C0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos)                /*!< RGU RESET_STATUS3: I2C0_RST Mask    */
+#define RGU_RESET_STATUS3_I2C1_RST_Pos                        2                                                         /*!< RGU RESET_STATUS3: I2C1_RST Position */
+#define RGU_RESET_STATUS3_I2C1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos)                /*!< RGU RESET_STATUS3: I2C1_RST Mask    */
+#define RGU_RESET_STATUS3_SSP0_RST_Pos                        4                                                         /*!< RGU RESET_STATUS3: SSP0_RST Position */
+#define RGU_RESET_STATUS3_SSP0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos)                /*!< RGU RESET_STATUS3: SSP0_RST Mask    */
+#define RGU_RESET_STATUS3_SSP1_RST_Pos                        6                                                         /*!< RGU RESET_STATUS3: SSP1_RST Position */
+#define RGU_RESET_STATUS3_SSP1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos)                /*!< RGU RESET_STATUS3: SSP1_RST Mask    */
+#define RGU_RESET_STATUS3_I2S_RST_Pos                         8                                                         /*!< RGU RESET_STATUS3: I2S_RST Position */
+#define RGU_RESET_STATUS3_I2S_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos)                 /*!< RGU RESET_STATUS3: I2S_RST Mask     */
+#define RGU_RESET_STATUS3_SPIFI_RST_Pos                       10                                                        /*!< RGU RESET_STATUS3: SPIFI_RST Position */
+#define RGU_RESET_STATUS3_SPIFI_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos)               /*!< RGU RESET_STATUS3: SPIFI_RST Mask   */
+#define RGU_RESET_STATUS3_CAN1_RST_Pos                        12                                                        /*!< RGU RESET_STATUS3: CAN1_RST Position */
+#define RGU_RESET_STATUS3_CAN1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos)                /*!< RGU RESET_STATUS3: CAN1_RST Mask    */
+#define RGU_RESET_STATUS3_CAN0_RST_Pos                        14                                                        /*!< RGU RESET_STATUS3: CAN0_RST Position */
+#define RGU_RESET_STATUS3_CAN0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos)                /*!< RGU RESET_STATUS3: CAN0_RST Mask    */
+#define RGU_RESET_STATUS3_M0APP_RST_Pos                       16                                                        /*!< RGU RESET_STATUS3: M0APP_RST Position */
+#define RGU_RESET_STATUS3_M0APP_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos)               /*!< RGU RESET_STATUS3: M0APP_RST Mask   */
+#define RGU_RESET_STATUS3_SGPIO_RST_Pos                       18                                                        /*!< RGU RESET_STATUS3: SGPIO_RST Position */
+#define RGU_RESET_STATUS3_SGPIO_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos)               /*!< RGU RESET_STATUS3: SGPIO_RST Mask   */
+#define RGU_RESET_STATUS3_SPI_RST_Pos                         20                                                        /*!< RGU RESET_STATUS3: SPI_RST Position */
+#define RGU_RESET_STATUS3_SPI_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos)                 /*!< RGU RESET_STATUS3: SPI_RST Mask     */
+
+// --------------------------------  RGU_RESET_ACTIVE_STATUS0  ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos                 0                                                         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos                 4                                                         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos                 5                                                         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos                  8                                                         /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos                  9                                                         /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos               10                                                        /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos                   13                                                        /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk                   (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos)           /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos                  16                                                        /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos                  19                                                        /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos                 20                                                        /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos                  21                                                        /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos             22                                                        /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk             (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)     /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos                 28                                                        /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */
+
+// --------------------------------  RGU_RESET_ACTIVE_STATUS1  ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos               0                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos               3                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos              4                                                         /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk              (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos)      /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos                  5                                                         /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos           6                                                         /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk           (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)   /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos                  7                                                         /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos                 8                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos                 9                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos                  10                                                        /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos                12                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos                13                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos                14                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos                15                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos                 16                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos                 19                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos                  20                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos                21                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos                 22                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos                 23                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos                24                                                        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos                25                                                        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos                  26                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT0  --------------------------------------
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos                     0                                                         /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos                     4                                                         /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos                    5                                                         /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos)            /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT1  --------------------------------------
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT2  --------------------------------------
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT4  --------------------------------------
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT5  --------------------------------------
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT8  --------------------------------------
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */
+
+// -----------------------------------  RGU_RESET_EXT_STAT9  --------------------------------------
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT13  --------------------------------------
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT16  --------------------------------------
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT17  --------------------------------------
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT18  --------------------------------------
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT19  --------------------------------------
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT20  --------------------------------------
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT21  --------------------------------------
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT22  --------------------------------------
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT23  --------------------------------------
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT28  --------------------------------------
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT32  --------------------------------------
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT33  --------------------------------------
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT34  --------------------------------------
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT35  --------------------------------------
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT36  --------------------------------------
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT37  --------------------------------------
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT38  --------------------------------------
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT39  --------------------------------------
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT40  --------------------------------------
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT41  --------------------------------------
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT42  --------------------------------------
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT44  --------------------------------------
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT45  --------------------------------------
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT46  --------------------------------------
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT47  --------------------------------------
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT48  --------------------------------------
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT49  --------------------------------------
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT50  --------------------------------------
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT51  --------------------------------------
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT52  --------------------------------------
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT53  --------------------------------------
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT54  --------------------------------------
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */
+
+// ----------------------------------  RGU_RESET_EXT_STAT55  --------------------------------------
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 WWDT Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  WWDT_MOD  --------------------------------------------
+#define WWDT_MOD_WDEN_Pos                                     0                                                         /*!< WWDT MOD: WDEN Position             */
+#define WWDT_MOD_WDEN_Msk                                     (0x01UL << WWDT_MOD_WDEN_Pos)                             /*!< WWDT MOD: WDEN Mask                 */
+#define WWDT_MOD_WDRESET_Pos                                  1                                                         /*!< WWDT MOD: WDRESET Position          */
+#define WWDT_MOD_WDRESET_Msk                                  (0x01UL << WWDT_MOD_WDRESET_Pos)                          /*!< WWDT MOD: WDRESET Mask              */
+#define WWDT_MOD_WDTOF_Pos                                    2                                                         /*!< WWDT MOD: WDTOF Position            */
+#define WWDT_MOD_WDTOF_Msk                                    (0x01UL << WWDT_MOD_WDTOF_Pos)                            /*!< WWDT MOD: WDTOF Mask                */
+#define WWDT_MOD_WDINT_Pos                                    3                                                         /*!< WWDT MOD: WDINT Position            */
+#define WWDT_MOD_WDINT_Msk                                    (0x01UL << WWDT_MOD_WDINT_Pos)                            /*!< WWDT MOD: WDINT Mask                */
+#define WWDT_MOD_WDPROTECT_Pos                                4                                                         /*!< WWDT MOD: WDPROTECT Position        */
+#define WWDT_MOD_WDPROTECT_Msk                                (0x01UL << WWDT_MOD_WDPROTECT_Pos)                        /*!< WWDT MOD: WDPROTECT Mask            */
+
+// -----------------------------------------  WWDT_TC  --------------------------------------------
+#define WWDT_TC_WDTC_Pos                                      0                                                         /*!< WWDT TC: WDTC Position              */
+#define WWDT_TC_WDTC_Msk                                      (0x00ffffffUL << WWDT_TC_WDTC_Pos)                        /*!< WWDT TC: WDTC Mask                  */
+
+// ----------------------------------------  WWDT_FEED  -------------------------------------------
+#define WWDT_FEED_Feed_Pos                                    0                                                         /*!< WWDT FEED: Feed Position            */
+#define WWDT_FEED_Feed_Msk                                    (0x000000ffUL << WWDT_FEED_Feed_Pos)                      /*!< WWDT FEED: Feed Mask                */
+
+// -----------------------------------------  WWDT_TV  --------------------------------------------
+#define WWDT_TV_Count_Pos                                     0                                                         /*!< WWDT TV: Count Position             */
+#define WWDT_TV_Count_Msk                                     (0x00ffffffUL << WWDT_TV_Count_Pos)                       /*!< WWDT TV: Count Mask                 */
+
+// --------------------------------------  WWDT_WARNINT  ------------------------------------------
+#define WWDT_WARNINT_WDWARNINT_Pos                            0                                                         /*!< WWDT WARNINT: WDWARNINT Position    */
+#define WWDT_WARNINT_WDWARNINT_Msk                            (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos)              /*!< WWDT WARNINT: WDWARNINT Mask        */
+
+// ---------------------------------------  WWDT_WINDOW  ------------------------------------------
+#define WWDT_WINDOW_WDWINDOW_Pos                              0                                                         /*!< WWDT WINDOW: WDWINDOW Position      */
+#define WWDT_WINDOW_WDWINDOW_Msk                              (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos)                /*!< WWDT WINDOW: WDWINDOW Mask          */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                USART0 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  USART0_RBR  -------------------------------------------
+#define USART0_RBR_RBR_Pos                                    0                                                         /*!< USART0 RBR: RBR Position            */
+#define USART0_RBR_RBR_Msk                                    (0x000000ffUL << USART0_RBR_RBR_Pos)                      /*!< USART0 RBR: RBR Mask                */
+
+// ---------------------------------------  USART0_THR  -------------------------------------------
+#define USART0_THR_THR_Pos                                    0                                                         /*!< USART0 THR: THR Position            */
+#define USART0_THR_THR_Msk                                    (0x000000ffUL << USART0_THR_THR_Pos)                      /*!< USART0 THR: THR Mask                */
+
+// ---------------------------------------  USART0_DLL  -------------------------------------------
+#define USART0_DLL_DLLSB_Pos                                  0                                                         /*!< USART0 DLL: DLLSB Position          */
+#define USART0_DLL_DLLSB_Msk                                  (0x000000ffUL << USART0_DLL_DLLSB_Pos)                    /*!< USART0 DLL: DLLSB Mask              */
+
+// ---------------------------------------  USART0_DLM  -------------------------------------------
+#define USART0_DLM_DLMSB_Pos                                  0                                                         /*!< USART0 DLM: DLMSB Position          */
+#define USART0_DLM_DLMSB_Msk                                  (0x000000ffUL << USART0_DLM_DLMSB_Pos)                    /*!< USART0 DLM: DLMSB Mask              */
+
+// ---------------------------------------  USART0_IER  -------------------------------------------
+#define USART0_IER_RBRIE_Pos                                  0                                                         /*!< USART0 IER: RBRIE Position          */
+#define USART0_IER_RBRIE_Msk                                  (0x01UL << USART0_IER_RBRIE_Pos)                          /*!< USART0 IER: RBRIE Mask              */
+#define USART0_IER_THREIE_Pos                                 1                                                         /*!< USART0 IER: THREIE Position         */
+#define USART0_IER_THREIE_Msk                                 (0x01UL << USART0_IER_THREIE_Pos)                         /*!< USART0 IER: THREIE Mask             */
+#define USART0_IER_RXIE_Pos                                   2                                                         /*!< USART0 IER: RXIE Position           */
+#define USART0_IER_RXIE_Msk                                   (0x01UL << USART0_IER_RXIE_Pos)                           /*!< USART0 IER: RXIE Mask               */
+#define USART0_IER_ABEOINTEN_Pos                              8                                                         /*!< USART0 IER: ABEOINTEN Position      */
+#define USART0_IER_ABEOINTEN_Msk                              (0x01UL << USART0_IER_ABEOINTEN_Pos)                      /*!< USART0 IER: ABEOINTEN Mask          */
+#define USART0_IER_ABTOINTEN_Pos                              9                                                         /*!< USART0 IER: ABTOINTEN Position      */
+#define USART0_IER_ABTOINTEN_Msk                              (0x01UL << USART0_IER_ABTOINTEN_Pos)                      /*!< USART0 IER: ABTOINTEN Mask          */
+
+// ---------------------------------------  USART0_IIR  -------------------------------------------
+#define USART0_IIR_INTSTATUS_Pos                              0                                                         /*!< USART0 IIR: INTSTATUS Position      */
+#define USART0_IIR_INTSTATUS_Msk                              (0x01UL << USART0_IIR_INTSTATUS_Pos)                      /*!< USART0 IIR: INTSTATUS Mask          */
+#define USART0_IIR_INTID_Pos                                  1                                                         /*!< USART0 IIR: INTID Position          */
+#define USART0_IIR_INTID_Msk                                  (0x07UL << USART0_IIR_INTID_Pos)                          /*!< USART0 IIR: INTID Mask              */
+#define USART0_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART0 IIR: FIFOENABLE Position     */
+#define USART0_IIR_FIFOENABLE_Msk                             (0x03UL << USART0_IIR_FIFOENABLE_Pos)                     /*!< USART0 IIR: FIFOENABLE Mask         */
+#define USART0_IIR_ABEOINT_Pos                                8                                                         /*!< USART0 IIR: ABEOINT Position        */
+#define USART0_IIR_ABEOINT_Msk                                (0x01UL << USART0_IIR_ABEOINT_Pos)                        /*!< USART0 IIR: ABEOINT Mask            */
+#define USART0_IIR_ABTOINT_Pos                                9                                                         /*!< USART0 IIR: ABTOINT Position        */
+#define USART0_IIR_ABTOINT_Msk                                (0x01UL << USART0_IIR_ABTOINT_Pos)                        /*!< USART0 IIR: ABTOINT Mask            */
+
+// ---------------------------------------  USART0_FCR  -------------------------------------------
+#define USART0_FCR_FIFOEN_Pos                                 0                                                         /*!< USART0 FCR: FIFOEN Position         */
+#define USART0_FCR_FIFOEN_Msk                                 (0x01UL << USART0_FCR_FIFOEN_Pos)                         /*!< USART0 FCR: FIFOEN Mask             */
+#define USART0_FCR_RXFIFORES_Pos                              1                                                         /*!< USART0 FCR: RXFIFORES Position      */
+#define USART0_FCR_RXFIFORES_Msk                              (0x01UL << USART0_FCR_RXFIFORES_Pos)                      /*!< USART0 FCR: RXFIFORES Mask          */
+#define USART0_FCR_TXFIFORES_Pos                              2                                                         /*!< USART0 FCR: TXFIFORES Position      */
+#define USART0_FCR_TXFIFORES_Msk                              (0x01UL << USART0_FCR_TXFIFORES_Pos)                      /*!< USART0 FCR: TXFIFORES Mask          */
+#define USART0_FCR_DMAMODE_Pos                                3                                                         /*!< USART0 FCR: DMAMODE Position        */
+#define USART0_FCR_DMAMODE_Msk                                (0x01UL << USART0_FCR_DMAMODE_Pos)                        /*!< USART0 FCR: DMAMODE Mask            */
+#define USART0_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART0 FCR: RXTRIGLVL Position      */
+#define USART0_FCR_RXTRIGLVL_Msk                              (0x03UL << USART0_FCR_RXTRIGLVL_Pos)                      /*!< USART0 FCR: RXTRIGLVL Mask          */
+
+// ---------------------------------------  USART0_LCR  -------------------------------------------
+#define USART0_LCR_WLS_Pos                                    0                                                         /*!< USART0 LCR: WLS Position            */
+#define USART0_LCR_WLS_Msk                                    (0x03UL << USART0_LCR_WLS_Pos)                            /*!< USART0 LCR: WLS Mask                */
+#define USART0_LCR_SBS_Pos                                    2                                                         /*!< USART0 LCR: SBS Position            */
+#define USART0_LCR_SBS_Msk                                    (0x01UL << USART0_LCR_SBS_Pos)                            /*!< USART0 LCR: SBS Mask                */
+#define USART0_LCR_PE_Pos                                     3                                                         /*!< USART0 LCR: PE Position             */
+#define USART0_LCR_PE_Msk                                     (0x01UL << USART0_LCR_PE_Pos)                             /*!< USART0 LCR: PE Mask                 */
+#define USART0_LCR_PS_Pos                                     4                                                         /*!< USART0 LCR: PS Position             */
+#define USART0_LCR_PS_Msk                                     (0x03UL << USART0_LCR_PS_Pos)                             /*!< USART0 LCR: PS Mask                 */
+#define USART0_LCR_BC_Pos                                     6                                                         /*!< USART0 LCR: BC Position             */
+#define USART0_LCR_BC_Msk                                     (0x01UL << USART0_LCR_BC_Pos)                             /*!< USART0 LCR: BC Mask                 */
+#define USART0_LCR_DLAB_Pos                                   7                                                         /*!< USART0 LCR: DLAB Position           */
+#define USART0_LCR_DLAB_Msk                                   (0x01UL << USART0_LCR_DLAB_Pos)                           /*!< USART0 LCR: DLAB Mask               */
+
+// ---------------------------------------  USART0_LSR  -------------------------------------------
+#define USART0_LSR_RDR_Pos                                    0                                                         /*!< USART0 LSR: RDR Position            */
+#define USART0_LSR_RDR_Msk                                    (0x01UL << USART0_LSR_RDR_Pos)                            /*!< USART0 LSR: RDR Mask                */
+#define USART0_LSR_OE_Pos                                     1                                                         /*!< USART0 LSR: OE Position             */
+#define USART0_LSR_OE_Msk                                     (0x01UL << USART0_LSR_OE_Pos)                             /*!< USART0 LSR: OE Mask                 */
+#define USART0_LSR_PE_Pos                                     2                                                         /*!< USART0 LSR: PE Position             */
+#define USART0_LSR_PE_Msk                                     (0x01UL << USART0_LSR_PE_Pos)                             /*!< USART0 LSR: PE Mask                 */
+#define USART0_LSR_FE_Pos                                     3                                                         /*!< USART0 LSR: FE Position             */
+#define USART0_LSR_FE_Msk                                     (0x01UL << USART0_LSR_FE_Pos)                             /*!< USART0 LSR: FE Mask                 */
+#define USART0_LSR_BI_Pos                                     4                                                         /*!< USART0 LSR: BI Position             */
+#define USART0_LSR_BI_Msk                                     (0x01UL << USART0_LSR_BI_Pos)                             /*!< USART0 LSR: BI Mask                 */
+#define USART0_LSR_THRE_Pos                                   5                                                         /*!< USART0 LSR: THRE Position           */
+#define USART0_LSR_THRE_Msk                                   (0x01UL << USART0_LSR_THRE_Pos)                           /*!< USART0 LSR: THRE Mask               */
+#define USART0_LSR_TEMT_Pos                                   6                                                         /*!< USART0 LSR: TEMT Position           */
+#define USART0_LSR_TEMT_Msk                                   (0x01UL << USART0_LSR_TEMT_Pos)                           /*!< USART0 LSR: TEMT Mask               */
+#define USART0_LSR_RXFE_Pos                                   7                                                         /*!< USART0 LSR: RXFE Position           */
+#define USART0_LSR_RXFE_Msk                                   (0x01UL << USART0_LSR_RXFE_Pos)                           /*!< USART0 LSR: RXFE Mask               */
+#define USART0_LSR_TXERR_Pos                                  8                                                         /*!< USART0 LSR: TXERR Position          */
+#define USART0_LSR_TXERR_Msk                                  (0x01UL << USART0_LSR_TXERR_Pos)                          /*!< USART0 LSR: TXERR Mask              */
+
+// ---------------------------------------  USART0_SCR  -------------------------------------------
+#define USART0_SCR_PAD_Pos                                    0                                                         /*!< USART0 SCR: PAD Position            */
+#define USART0_SCR_PAD_Msk                                    (0x000000ffUL << USART0_SCR_PAD_Pos)                      /*!< USART0 SCR: PAD Mask                */
+
+// ---------------------------------------  USART0_ACR  -------------------------------------------
+#define USART0_ACR_START_Pos                                  0                                                         /*!< USART0 ACR: START Position          */
+#define USART0_ACR_START_Msk                                  (0x01UL << USART0_ACR_START_Pos)                          /*!< USART0 ACR: START Mask              */
+#define USART0_ACR_MODE_Pos                                   1                                                         /*!< USART0 ACR: MODE Position           */
+#define USART0_ACR_MODE_Msk                                   (0x01UL << USART0_ACR_MODE_Pos)                           /*!< USART0 ACR: MODE Mask               */
+#define USART0_ACR_AUTORESTART_Pos                            2                                                         /*!< USART0 ACR: AUTORESTART Position    */
+#define USART0_ACR_AUTORESTART_Msk                            (0x01UL << USART0_ACR_AUTORESTART_Pos)                    /*!< USART0 ACR: AUTORESTART Mask        */
+#define USART0_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART0 ACR: ABEOINTCLR Position     */
+#define USART0_ACR_ABEOINTCLR_Msk                             (0x01UL << USART0_ACR_ABEOINTCLR_Pos)                     /*!< USART0 ACR: ABEOINTCLR Mask         */
+#define USART0_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART0 ACR: ABTOINTCLR Position     */
+#define USART0_ACR_ABTOINTCLR_Msk                             (0x01UL << USART0_ACR_ABTOINTCLR_Pos)                     /*!< USART0 ACR: ABTOINTCLR Mask         */
+
+// ---------------------------------------  USART0_ICR  -------------------------------------------
+#define USART0_ICR_IRDAEN_Pos                                 0                                                         /*!< USART0 ICR: IRDAEN Position         */
+#define USART0_ICR_IRDAEN_Msk                                 (0x01UL << USART0_ICR_IRDAEN_Pos)                         /*!< USART0 ICR: IRDAEN Mask             */
+#define USART0_ICR_IRDAINV_Pos                                1                                                         /*!< USART0 ICR: IRDAINV Position        */
+#define USART0_ICR_IRDAINV_Msk                                (0x01UL << USART0_ICR_IRDAINV_Pos)                        /*!< USART0 ICR: IRDAINV Mask            */
+#define USART0_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART0 ICR: FIXPULSEEN Position     */
+#define USART0_ICR_FIXPULSEEN_Msk                             (0x01UL << USART0_ICR_FIXPULSEEN_Pos)                     /*!< USART0 ICR: FIXPULSEEN Mask         */
+#define USART0_ICR_PULSEDIV_Pos                               3                                                         /*!< USART0 ICR: PULSEDIV Position       */
+#define USART0_ICR_PULSEDIV_Msk                               (0x07UL << USART0_ICR_PULSEDIV_Pos)                       /*!< USART0 ICR: PULSEDIV Mask           */
+
+// ---------------------------------------  USART0_FDR  -------------------------------------------
+#define USART0_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART0 FDR: DIVADDVAL Position      */
+#define USART0_FDR_DIVADDVAL_Msk                              (0x0fUL << USART0_FDR_DIVADDVAL_Pos)                      /*!< USART0 FDR: DIVADDVAL Mask          */
+#define USART0_FDR_MULVAL_Pos                                 4                                                         /*!< USART0 FDR: MULVAL Position         */
+#define USART0_FDR_MULVAL_Msk                                 (0x0fUL << USART0_FDR_MULVAL_Pos)                         /*!< USART0 FDR: MULVAL Mask             */
+
+// ---------------------------------------  USART0_OSR  -------------------------------------------
+#define USART0_OSR_OSFRAC_Pos                                 1                                                         /*!< USART0 OSR: OSFRAC Position         */
+#define USART0_OSR_OSFRAC_Msk                                 (0x07UL << USART0_OSR_OSFRAC_Pos)                         /*!< USART0 OSR: OSFRAC Mask             */
+#define USART0_OSR_OSINT_Pos                                  4                                                         /*!< USART0 OSR: OSINT Position          */
+#define USART0_OSR_OSINT_Msk                                  (0x0fUL << USART0_OSR_OSINT_Pos)                          /*!< USART0 OSR: OSINT Mask              */
+#define USART0_OSR_FDINT_Pos                                  8                                                         /*!< USART0 OSR: FDINT Position          */
+#define USART0_OSR_FDINT_Msk                                  (0x7fUL << USART0_OSR_FDINT_Pos)                          /*!< USART0 OSR: FDINT Mask              */
+
+// ---------------------------------------  USART0_HDEN  ------------------------------------------
+#define USART0_HDEN_HDEN_Pos                                  0                                                         /*!< USART0 HDEN: HDEN Position          */
+#define USART0_HDEN_HDEN_Msk                                  (0x01UL << USART0_HDEN_HDEN_Pos)                          /*!< USART0 HDEN: HDEN Mask              */
+
+// -------------------------------------  USART0_SCICTRL  -----------------------------------------
+#define USART0_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART0 SCICTRL: SCIEN Position      */
+#define USART0_SCICTRL_SCIEN_Msk                              (0x01UL << USART0_SCICTRL_SCIEN_Pos)                      /*!< USART0 SCICTRL: SCIEN Mask          */
+#define USART0_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART0 SCICTRL: NACKDIS Position    */
+#define USART0_SCICTRL_NACKDIS_Msk                            (0x01UL << USART0_SCICTRL_NACKDIS_Pos)                    /*!< USART0 SCICTRL: NACKDIS Mask        */
+#define USART0_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART0 SCICTRL: PROTSEL Position    */
+#define USART0_SCICTRL_PROTSEL_Msk                            (0x01UL << USART0_SCICTRL_PROTSEL_Pos)                    /*!< USART0 SCICTRL: PROTSEL Mask        */
+#define USART0_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART0 SCICTRL: TXRETRY Position    */
+#define USART0_SCICTRL_TXRETRY_Msk                            (0x07UL << USART0_SCICTRL_TXRETRY_Pos)                    /*!< USART0 SCICTRL: TXRETRY Mask        */
+#define USART0_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART0 SCICTRL: GUARDTIME Position  */
+#define USART0_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos)            /*!< USART0 SCICTRL: GUARDTIME Mask      */
+
+// ------------------------------------  USART0_RS485CTRL  ----------------------------------------
+#define USART0_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART0 RS485CTRL: NMMEN Position    */
+#define USART0_RS485CTRL_NMMEN_Msk                            (0x01UL << USART0_RS485CTRL_NMMEN_Pos)                    /*!< USART0 RS485CTRL: NMMEN Mask        */
+#define USART0_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART0 RS485CTRL: RXDIS Position    */
+#define USART0_RS485CTRL_RXDIS_Msk                            (0x01UL << USART0_RS485CTRL_RXDIS_Pos)                    /*!< USART0 RS485CTRL: RXDIS Mask        */
+#define USART0_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART0 RS485CTRL: AADEN Position    */
+#define USART0_RS485CTRL_AADEN_Msk                            (0x01UL << USART0_RS485CTRL_AADEN_Pos)                    /*!< USART0 RS485CTRL: AADEN Mask        */
+#define USART0_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART0 RS485CTRL: DCTRL Position    */
+#define USART0_RS485CTRL_DCTRL_Msk                            (0x01UL << USART0_RS485CTRL_DCTRL_Pos)                    /*!< USART0 RS485CTRL: DCTRL Mask        */
+#define USART0_RS485CTRL_OINV_Pos                             5                                                         /*!< USART0 RS485CTRL: OINV Position     */
+#define USART0_RS485CTRL_OINV_Msk                             (0x01UL << USART0_RS485CTRL_OINV_Pos)                     /*!< USART0 RS485CTRL: OINV Mask         */
+
+// ----------------------------------  USART0_RS485ADRMATCH  --------------------------------------
+#define USART0_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART0 RS485ADRMATCH: ADRMATCH Position */
+#define USART0_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */
+
+// -------------------------------------  USART0_RS485DLY  ----------------------------------------
+#define USART0_RS485DLY_DLY_Pos                               0                                                         /*!< USART0 RS485DLY: DLY Position       */
+#define USART0_RS485DLY_DLY_Msk                               (0x000000ffUL << USART0_RS485DLY_DLY_Pos)                 /*!< USART0 RS485DLY: DLY Mask           */
+
+// -------------------------------------  USART0_SYNCCTRL  ----------------------------------------
+#define USART0_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART0 SYNCCTRL: SYNC Position      */
+#define USART0_SYNCCTRL_SYNC_Msk                              (0x01UL << USART0_SYNCCTRL_SYNC_Pos)                      /*!< USART0 SYNCCTRL: SYNC Mask          */
+#define USART0_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART0 SYNCCTRL: CSRC Position      */
+#define USART0_SYNCCTRL_CSRC_Msk                              (0x01UL << USART0_SYNCCTRL_CSRC_Pos)                      /*!< USART0 SYNCCTRL: CSRC Mask          */
+#define USART0_SYNCCTRL_FES_Pos                               2                                                         /*!< USART0 SYNCCTRL: FES Position       */
+#define USART0_SYNCCTRL_FES_Msk                               (0x01UL << USART0_SYNCCTRL_FES_Pos)                       /*!< USART0 SYNCCTRL: FES Mask           */
+#define USART0_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART0 SYNCCTRL: TSBYPASS Position  */
+#define USART0_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART0 SYNCCTRL: TSBYPASS Mask      */
+#define USART0_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART0 SYNCCTRL: CSCEN Position     */
+#define USART0_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART0_SYNCCTRL_CSCEN_Pos)                     /*!< USART0 SYNCCTRL: CSCEN Mask         */
+#define USART0_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART0 SYNCCTRL: SSSDIS Position    */
+#define USART0_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos)                    /*!< USART0 SYNCCTRL: SSSDIS Mask        */
+#define USART0_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART0 SYNCCTRL: CCCLR Position     */
+#define USART0_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART0_SYNCCTRL_CCCLR_Pos)                     /*!< USART0 SYNCCTRL: CCCLR Mask         */
+
+// ---------------------------------------  USART0_TER  -------------------------------------------
+#define USART0_TER_TXEN_Pos                                   0                                                         /*!< USART0 TER: TXEN Position           */
+#define USART0_TER_TXEN_Msk                                   (0x01UL << USART0_TER_TXEN_Pos)                           /*!< USART0 TER: TXEN Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                USART2 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  USART2_DLL  -------------------------------------------
+#define USART2_DLL_DLLSB_Pos                                  0                                                         /*!< USART2 DLL: DLLSB Position          */
+#define USART2_DLL_DLLSB_Msk                                  (0x000000ffUL << USART2_DLL_DLLSB_Pos)                    /*!< USART2 DLL: DLLSB Mask              */
+
+// ---------------------------------------  USART2_THR  -------------------------------------------
+#define USART2_THR_THR_Pos                                    0                                                         /*!< USART2 THR: THR Position            */
+#define USART2_THR_THR_Msk                                    (0x000000ffUL << USART2_THR_THR_Pos)                      /*!< USART2 THR: THR Mask                */
+
+// ---------------------------------------  USART2_RBR  -------------------------------------------
+#define USART2_RBR_RBR_Pos                                    0                                                         /*!< USART2 RBR: RBR Position            */
+#define USART2_RBR_RBR_Msk                                    (0x000000ffUL << USART2_RBR_RBR_Pos)                      /*!< USART2 RBR: RBR Mask                */
+
+// ---------------------------------------  USART2_IER  -------------------------------------------
+#define USART2_IER_RBRIE_Pos                                  0                                                         /*!< USART2 IER: RBRIE Position          */
+#define USART2_IER_RBRIE_Msk                                  (0x01UL << USART2_IER_RBRIE_Pos)                          /*!< USART2 IER: RBRIE Mask              */
+#define USART2_IER_THREIE_Pos                                 1                                                         /*!< USART2 IER: THREIE Position         */
+#define USART2_IER_THREIE_Msk                                 (0x01UL << USART2_IER_THREIE_Pos)                         /*!< USART2 IER: THREIE Mask             */
+#define USART2_IER_RXIE_Pos                                   2                                                         /*!< USART2 IER: RXIE Position           */
+#define USART2_IER_RXIE_Msk                                   (0x01UL << USART2_IER_RXIE_Pos)                           /*!< USART2 IER: RXIE Mask               */
+#define USART2_IER_ABEOINTEN_Pos                              8                                                         /*!< USART2 IER: ABEOINTEN Position      */
+#define USART2_IER_ABEOINTEN_Msk                              (0x01UL << USART2_IER_ABEOINTEN_Pos)                      /*!< USART2 IER: ABEOINTEN Mask          */
+#define USART2_IER_ABTOINTEN_Pos                              9                                                         /*!< USART2 IER: ABTOINTEN Position      */
+#define USART2_IER_ABTOINTEN_Msk                              (0x01UL << USART2_IER_ABTOINTEN_Pos)                      /*!< USART2 IER: ABTOINTEN Mask          */
+
+// ---------------------------------------  USART2_DLM  -------------------------------------------
+#define USART2_DLM_DLMSB_Pos                                  0                                                         /*!< USART2 DLM: DLMSB Position          */
+#define USART2_DLM_DLMSB_Msk                                  (0x000000ffUL << USART2_DLM_DLMSB_Pos)                    /*!< USART2 DLM: DLMSB Mask              */
+
+// ---------------------------------------  USART2_FCR  -------------------------------------------
+#define USART2_FCR_FIFOEN_Pos                                 0                                                         /*!< USART2 FCR: FIFOEN Position         */
+#define USART2_FCR_FIFOEN_Msk                                 (0x01UL << USART2_FCR_FIFOEN_Pos)                         /*!< USART2 FCR: FIFOEN Mask             */
+#define USART2_FCR_RXFIFORES_Pos                              1                                                         /*!< USART2 FCR: RXFIFORES Position      */
+#define USART2_FCR_RXFIFORES_Msk                              (0x01UL << USART2_FCR_RXFIFORES_Pos)                      /*!< USART2 FCR: RXFIFORES Mask          */
+#define USART2_FCR_TXFIFORES_Pos                              2                                                         /*!< USART2 FCR: TXFIFORES Position      */
+#define USART2_FCR_TXFIFORES_Msk                              (0x01UL << USART2_FCR_TXFIFORES_Pos)                      /*!< USART2 FCR: TXFIFORES Mask          */
+#define USART2_FCR_DMAMODE_Pos                                3                                                         /*!< USART2 FCR: DMAMODE Position        */
+#define USART2_FCR_DMAMODE_Msk                                (0x01UL << USART2_FCR_DMAMODE_Pos)                        /*!< USART2 FCR: DMAMODE Mask            */
+#define USART2_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART2 FCR: RXTRIGLVL Position      */
+#define USART2_FCR_RXTRIGLVL_Msk                              (0x03UL << USART2_FCR_RXTRIGLVL_Pos)                      /*!< USART2 FCR: RXTRIGLVL Mask          */
+
+// ---------------------------------------  USART2_IIR  -------------------------------------------
+#define USART2_IIR_INTSTATUS_Pos                              0                                                         /*!< USART2 IIR: INTSTATUS Position      */
+#define USART2_IIR_INTSTATUS_Msk                              (0x01UL << USART2_IIR_INTSTATUS_Pos)                      /*!< USART2 IIR: INTSTATUS Mask          */
+#define USART2_IIR_INTID_Pos                                  1                                                         /*!< USART2 IIR: INTID Position          */
+#define USART2_IIR_INTID_Msk                                  (0x07UL << USART2_IIR_INTID_Pos)                          /*!< USART2 IIR: INTID Mask              */
+#define USART2_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART2 IIR: FIFOENABLE Position     */
+#define USART2_IIR_FIFOENABLE_Msk                             (0x03UL << USART2_IIR_FIFOENABLE_Pos)                     /*!< USART2 IIR: FIFOENABLE Mask         */
+#define USART2_IIR_ABEOINT_Pos                                8                                                         /*!< USART2 IIR: ABEOINT Position        */
+#define USART2_IIR_ABEOINT_Msk                                (0x01UL << USART2_IIR_ABEOINT_Pos)                        /*!< USART2 IIR: ABEOINT Mask            */
+#define USART2_IIR_ABTOINT_Pos                                9                                                         /*!< USART2 IIR: ABTOINT Position        */
+#define USART2_IIR_ABTOINT_Msk                                (0x01UL << USART2_IIR_ABTOINT_Pos)                        /*!< USART2 IIR: ABTOINT Mask            */
+
+// ---------------------------------------  USART2_LCR  -------------------------------------------
+#define USART2_LCR_WLS_Pos                                    0                                                         /*!< USART2 LCR: WLS Position            */
+#define USART2_LCR_WLS_Msk                                    (0x03UL << USART2_LCR_WLS_Pos)                            /*!< USART2 LCR: WLS Mask                */
+#define USART2_LCR_SBS_Pos                                    2                                                         /*!< USART2 LCR: SBS Position            */
+#define USART2_LCR_SBS_Msk                                    (0x01UL << USART2_LCR_SBS_Pos)                            /*!< USART2 LCR: SBS Mask                */
+#define USART2_LCR_PE_Pos                                     3                                                         /*!< USART2 LCR: PE Position             */
+#define USART2_LCR_PE_Msk                                     (0x01UL << USART2_LCR_PE_Pos)                             /*!< USART2 LCR: PE Mask                 */
+#define USART2_LCR_PS_Pos                                     4                                                         /*!< USART2 LCR: PS Position             */
+#define USART2_LCR_PS_Msk                                     (0x03UL << USART2_LCR_PS_Pos)                             /*!< USART2 LCR: PS Mask                 */
+#define USART2_LCR_BC_Pos                                     6                                                         /*!< USART2 LCR: BC Position             */
+#define USART2_LCR_BC_Msk                                     (0x01UL << USART2_LCR_BC_Pos)                             /*!< USART2 LCR: BC Mask                 */
+#define USART2_LCR_DLAB_Pos                                   7                                                         /*!< USART2 LCR: DLAB Position           */
+#define USART2_LCR_DLAB_Msk                                   (0x01UL << USART2_LCR_DLAB_Pos)                           /*!< USART2 LCR: DLAB Mask               */
+
+// ---------------------------------------  USART2_LSR  -------------------------------------------
+#define USART2_LSR_RDR_Pos                                    0                                                         /*!< USART2 LSR: RDR Position            */
+#define USART2_LSR_RDR_Msk                                    (0x01UL << USART2_LSR_RDR_Pos)                            /*!< USART2 LSR: RDR Mask                */
+#define USART2_LSR_OE_Pos                                     1                                                         /*!< USART2 LSR: OE Position             */
+#define USART2_LSR_OE_Msk                                     (0x01UL << USART2_LSR_OE_Pos)                             /*!< USART2 LSR: OE Mask                 */
+#define USART2_LSR_PE_Pos                                     2                                                         /*!< USART2 LSR: PE Position             */
+#define USART2_LSR_PE_Msk                                     (0x01UL << USART2_LSR_PE_Pos)                             /*!< USART2 LSR: PE Mask                 */
+#define USART2_LSR_FE_Pos                                     3                                                         /*!< USART2 LSR: FE Position             */
+#define USART2_LSR_FE_Msk                                     (0x01UL << USART2_LSR_FE_Pos)                             /*!< USART2 LSR: FE Mask                 */
+#define USART2_LSR_BI_Pos                                     4                                                         /*!< USART2 LSR: BI Position             */
+#define USART2_LSR_BI_Msk                                     (0x01UL << USART2_LSR_BI_Pos)                             /*!< USART2 LSR: BI Mask                 */
+#define USART2_LSR_THRE_Pos                                   5                                                         /*!< USART2 LSR: THRE Position           */
+#define USART2_LSR_THRE_Msk                                   (0x01UL << USART2_LSR_THRE_Pos)                           /*!< USART2 LSR: THRE Mask               */
+#define USART2_LSR_TEMT_Pos                                   6                                                         /*!< USART2 LSR: TEMT Position           */
+#define USART2_LSR_TEMT_Msk                                   (0x01UL << USART2_LSR_TEMT_Pos)                           /*!< USART2 LSR: TEMT Mask               */
+#define USART2_LSR_RXFE_Pos                                   7                                                         /*!< USART2 LSR: RXFE Position           */
+#define USART2_LSR_RXFE_Msk                                   (0x01UL << USART2_LSR_RXFE_Pos)                           /*!< USART2 LSR: RXFE Mask               */
+#define USART2_LSR_TXERR_Pos                                  8                                                         /*!< USART2 LSR: TXERR Position          */
+#define USART2_LSR_TXERR_Msk                                  (0x01UL << USART2_LSR_TXERR_Pos)                          /*!< USART2 LSR: TXERR Mask              */
+
+// ---------------------------------------  USART2_SCR  -------------------------------------------
+#define USART2_SCR_PAD_Pos                                    0                                                         /*!< USART2 SCR: PAD Position            */
+#define USART2_SCR_PAD_Msk                                    (0x000000ffUL << USART2_SCR_PAD_Pos)                      /*!< USART2 SCR: PAD Mask                */
+
+// ---------------------------------------  USART2_ACR  -------------------------------------------
+#define USART2_ACR_START_Pos                                  0                                                         /*!< USART2 ACR: START Position          */
+#define USART2_ACR_START_Msk                                  (0x01UL << USART2_ACR_START_Pos)                          /*!< USART2 ACR: START Mask              */
+#define USART2_ACR_MODE_Pos                                   1                                                         /*!< USART2 ACR: MODE Position           */
+#define USART2_ACR_MODE_Msk                                   (0x01UL << USART2_ACR_MODE_Pos)                           /*!< USART2 ACR: MODE Mask               */
+#define USART2_ACR_AUTORESTART_Pos                            2                                                         /*!< USART2 ACR: AUTORESTART Position    */
+#define USART2_ACR_AUTORESTART_Msk                            (0x01UL << USART2_ACR_AUTORESTART_Pos)                    /*!< USART2 ACR: AUTORESTART Mask        */
+#define USART2_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART2 ACR: ABEOINTCLR Position     */
+#define USART2_ACR_ABEOINTCLR_Msk                             (0x01UL << USART2_ACR_ABEOINTCLR_Pos)                     /*!< USART2 ACR: ABEOINTCLR Mask         */
+#define USART2_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART2 ACR: ABTOINTCLR Position     */
+#define USART2_ACR_ABTOINTCLR_Msk                             (0x01UL << USART2_ACR_ABTOINTCLR_Pos)                     /*!< USART2 ACR: ABTOINTCLR Mask         */
+
+// ---------------------------------------  USART2_ICR  -------------------------------------------
+#define USART2_ICR_IRDAEN_Pos                                 0                                                         /*!< USART2 ICR: IRDAEN Position         */
+#define USART2_ICR_IRDAEN_Msk                                 (0x01UL << USART2_ICR_IRDAEN_Pos)                         /*!< USART2 ICR: IRDAEN Mask             */
+#define USART2_ICR_IRDAINV_Pos                                1                                                         /*!< USART2 ICR: IRDAINV Position        */
+#define USART2_ICR_IRDAINV_Msk                                (0x01UL << USART2_ICR_IRDAINV_Pos)                        /*!< USART2 ICR: IRDAINV Mask            */
+#define USART2_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART2 ICR: FIXPULSEEN Position     */
+#define USART2_ICR_FIXPULSEEN_Msk                             (0x01UL << USART2_ICR_FIXPULSEEN_Pos)                     /*!< USART2 ICR: FIXPULSEEN Mask         */
+#define USART2_ICR_PULSEDIV_Pos                               3                                                         /*!< USART2 ICR: PULSEDIV Position       */
+#define USART2_ICR_PULSEDIV_Msk                               (0x07UL << USART2_ICR_PULSEDIV_Pos)                       /*!< USART2 ICR: PULSEDIV Mask           */
+
+// ---------------------------------------  USART2_FDR  -------------------------------------------
+#define USART2_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART2 FDR: DIVADDVAL Position      */
+#define USART2_FDR_DIVADDVAL_Msk                              (0x0fUL << USART2_FDR_DIVADDVAL_Pos)                      /*!< USART2 FDR: DIVADDVAL Mask          */
+#define USART2_FDR_MULVAL_Pos                                 4                                                         /*!< USART2 FDR: MULVAL Position         */
+#define USART2_FDR_MULVAL_Msk                                 (0x0fUL << USART2_FDR_MULVAL_Pos)                         /*!< USART2 FDR: MULVAL Mask             */
+
+// ---------------------------------------  USART2_OSR  -------------------------------------------
+#define USART2_OSR_OSFRAC_Pos                                 1                                                         /*!< USART2 OSR: OSFRAC Position         */
+#define USART2_OSR_OSFRAC_Msk                                 (0x07UL << USART2_OSR_OSFRAC_Pos)                         /*!< USART2 OSR: OSFRAC Mask             */
+#define USART2_OSR_OSINT_Pos                                  4                                                         /*!< USART2 OSR: OSINT Position          */
+#define USART2_OSR_OSINT_Msk                                  (0x0fUL << USART2_OSR_OSINT_Pos)                          /*!< USART2 OSR: OSINT Mask              */
+#define USART2_OSR_FDINT_Pos                                  8                                                         /*!< USART2 OSR: FDINT Position          */
+#define USART2_OSR_FDINT_Msk                                  (0x7fUL << USART2_OSR_FDINT_Pos)                          /*!< USART2 OSR: FDINT Mask              */
+
+// ---------------------------------------  USART2_HDEN  ------------------------------------------
+#define USART2_HDEN_HDEN_Pos                                  0                                                         /*!< USART2 HDEN: HDEN Position          */
+#define USART2_HDEN_HDEN_Msk                                  (0x01UL << USART2_HDEN_HDEN_Pos)                          /*!< USART2 HDEN: HDEN Mask              */
+
+// -------------------------------------  USART2_SCICTRL  -----------------------------------------
+#define USART2_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART2 SCICTRL: SCIEN Position      */
+#define USART2_SCICTRL_SCIEN_Msk                              (0x01UL << USART2_SCICTRL_SCIEN_Pos)                      /*!< USART2 SCICTRL: SCIEN Mask          */
+#define USART2_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART2 SCICTRL: NACKDIS Position    */
+#define USART2_SCICTRL_NACKDIS_Msk                            (0x01UL << USART2_SCICTRL_NACKDIS_Pos)                    /*!< USART2 SCICTRL: NACKDIS Mask        */
+#define USART2_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART2 SCICTRL: PROTSEL Position    */
+#define USART2_SCICTRL_PROTSEL_Msk                            (0x01UL << USART2_SCICTRL_PROTSEL_Pos)                    /*!< USART2 SCICTRL: PROTSEL Mask        */
+#define USART2_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART2 SCICTRL: TXRETRY Position    */
+#define USART2_SCICTRL_TXRETRY_Msk                            (0x07UL << USART2_SCICTRL_TXRETRY_Pos)                    /*!< USART2 SCICTRL: TXRETRY Mask        */
+#define USART2_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART2 SCICTRL: GUARDTIME Position  */
+#define USART2_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos)            /*!< USART2 SCICTRL: GUARDTIME Mask      */
+
+// ------------------------------------  USART2_RS485CTRL  ----------------------------------------
+#define USART2_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART2 RS485CTRL: NMMEN Position    */
+#define USART2_RS485CTRL_NMMEN_Msk                            (0x01UL << USART2_RS485CTRL_NMMEN_Pos)                    /*!< USART2 RS485CTRL: NMMEN Mask        */
+#define USART2_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART2 RS485CTRL: RXDIS Position    */
+#define USART2_RS485CTRL_RXDIS_Msk                            (0x01UL << USART2_RS485CTRL_RXDIS_Pos)                    /*!< USART2 RS485CTRL: RXDIS Mask        */
+#define USART2_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART2 RS485CTRL: AADEN Position    */
+#define USART2_RS485CTRL_AADEN_Msk                            (0x01UL << USART2_RS485CTRL_AADEN_Pos)                    /*!< USART2 RS485CTRL: AADEN Mask        */
+#define USART2_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART2 RS485CTRL: DCTRL Position    */
+#define USART2_RS485CTRL_DCTRL_Msk                            (0x01UL << USART2_RS485CTRL_DCTRL_Pos)                    /*!< USART2 RS485CTRL: DCTRL Mask        */
+#define USART2_RS485CTRL_OINV_Pos                             5                                                         /*!< USART2 RS485CTRL: OINV Position     */
+#define USART2_RS485CTRL_OINV_Msk                             (0x01UL << USART2_RS485CTRL_OINV_Pos)                     /*!< USART2 RS485CTRL: OINV Mask         */
+
+// ----------------------------------  USART2_RS485ADRMATCH  --------------------------------------
+#define USART2_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART2 RS485ADRMATCH: ADRMATCH Position */
+#define USART2_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */
+
+// -------------------------------------  USART2_RS485DLY  ----------------------------------------
+#define USART2_RS485DLY_DLY_Pos                               0                                                         /*!< USART2 RS485DLY: DLY Position       */
+#define USART2_RS485DLY_DLY_Msk                               (0x000000ffUL << USART2_RS485DLY_DLY_Pos)                 /*!< USART2 RS485DLY: DLY Mask           */
+
+// -------------------------------------  USART2_SYNCCTRL  ----------------------------------------
+#define USART2_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART2 SYNCCTRL: SYNC Position      */
+#define USART2_SYNCCTRL_SYNC_Msk                              (0x01UL << USART2_SYNCCTRL_SYNC_Pos)                      /*!< USART2 SYNCCTRL: SYNC Mask          */
+#define USART2_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART2 SYNCCTRL: CSRC Position      */
+#define USART2_SYNCCTRL_CSRC_Msk                              (0x01UL << USART2_SYNCCTRL_CSRC_Pos)                      /*!< USART2 SYNCCTRL: CSRC Mask          */
+#define USART2_SYNCCTRL_FES_Pos                               2                                                         /*!< USART2 SYNCCTRL: FES Position       */
+#define USART2_SYNCCTRL_FES_Msk                               (0x01UL << USART2_SYNCCTRL_FES_Pos)                       /*!< USART2 SYNCCTRL: FES Mask           */
+#define USART2_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART2 SYNCCTRL: TSBYPASS Position  */
+#define USART2_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART2 SYNCCTRL: TSBYPASS Mask      */
+#define USART2_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART2 SYNCCTRL: CSCEN Position     */
+#define USART2_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART2_SYNCCTRL_CSCEN_Pos)                     /*!< USART2 SYNCCTRL: CSCEN Mask         */
+#define USART2_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART2 SYNCCTRL: SSSDIS Position    */
+#define USART2_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos)                    /*!< USART2 SYNCCTRL: SSSDIS Mask        */
+#define USART2_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART2 SYNCCTRL: CCCLR Position     */
+#define USART2_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART2_SYNCCTRL_CCCLR_Pos)                     /*!< USART2 SYNCCTRL: CCCLR Mask         */
+
+// ---------------------------------------  USART2_TER  -------------------------------------------
+#define USART2_TER_TXEN_Pos                                   0                                                         /*!< USART2 TER: TXEN Position           */
+#define USART2_TER_TXEN_Msk                                   (0x01UL << USART2_TER_TXEN_Pos)                           /*!< USART2 TER: TXEN Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                USART3 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  USART3_DLL  -------------------------------------------
+#define USART3_DLL_DLLSB_Pos                                  0                                                         /*!< USART3 DLL: DLLSB Position          */
+#define USART3_DLL_DLLSB_Msk                                  (0x000000ffUL << USART3_DLL_DLLSB_Pos)                    /*!< USART3 DLL: DLLSB Mask              */
+
+// ---------------------------------------  USART3_THR  -------------------------------------------
+#define USART3_THR_THR_Pos                                    0                                                         /*!< USART3 THR: THR Position            */
+#define USART3_THR_THR_Msk                                    (0x000000ffUL << USART3_THR_THR_Pos)                      /*!< USART3 THR: THR Mask                */
+
+// ---------------------------------------  USART3_RBR  -------------------------------------------
+#define USART3_RBR_RBR_Pos                                    0                                                         /*!< USART3 RBR: RBR Position            */
+#define USART3_RBR_RBR_Msk                                    (0x000000ffUL << USART3_RBR_RBR_Pos)                      /*!< USART3 RBR: RBR Mask                */
+
+// ---------------------------------------  USART3_IER  -------------------------------------------
+#define USART3_IER_RBRIE_Pos                                  0                                                         /*!< USART3 IER: RBRIE Position          */
+#define USART3_IER_RBRIE_Msk                                  (0x01UL << USART3_IER_RBRIE_Pos)                          /*!< USART3 IER: RBRIE Mask              */
+#define USART3_IER_THREIE_Pos                                 1                                                         /*!< USART3 IER: THREIE Position         */
+#define USART3_IER_THREIE_Msk                                 (0x01UL << USART3_IER_THREIE_Pos)                         /*!< USART3 IER: THREIE Mask             */
+#define USART3_IER_RXIE_Pos                                   2                                                         /*!< USART3 IER: RXIE Position           */
+#define USART3_IER_RXIE_Msk                                   (0x01UL << USART3_IER_RXIE_Pos)                           /*!< USART3 IER: RXIE Mask               */
+#define USART3_IER_ABEOINTEN_Pos                              8                                                         /*!< USART3 IER: ABEOINTEN Position      */
+#define USART3_IER_ABEOINTEN_Msk                              (0x01UL << USART3_IER_ABEOINTEN_Pos)                      /*!< USART3 IER: ABEOINTEN Mask          */
+#define USART3_IER_ABTOINTEN_Pos                              9                                                         /*!< USART3 IER: ABTOINTEN Position      */
+#define USART3_IER_ABTOINTEN_Msk                              (0x01UL << USART3_IER_ABTOINTEN_Pos)                      /*!< USART3 IER: ABTOINTEN Mask          */
+
+// ---------------------------------------  USART3_DLM  -------------------------------------------
+#define USART3_DLM_DLMSB_Pos                                  0                                                         /*!< USART3 DLM: DLMSB Position          */
+#define USART3_DLM_DLMSB_Msk                                  (0x000000ffUL << USART3_DLM_DLMSB_Pos)                    /*!< USART3 DLM: DLMSB Mask              */
+
+// ---------------------------------------  USART3_FCR  -------------------------------------------
+#define USART3_FCR_FIFOEN_Pos                                 0                                                         /*!< USART3 FCR: FIFOEN Position         */
+#define USART3_FCR_FIFOEN_Msk                                 (0x01UL << USART3_FCR_FIFOEN_Pos)                         /*!< USART3 FCR: FIFOEN Mask             */
+#define USART3_FCR_RXFIFORES_Pos                              1                                                         /*!< USART3 FCR: RXFIFORES Position      */
+#define USART3_FCR_RXFIFORES_Msk                              (0x01UL << USART3_FCR_RXFIFORES_Pos)                      /*!< USART3 FCR: RXFIFORES Mask          */
+#define USART3_FCR_TXFIFORES_Pos                              2                                                         /*!< USART3 FCR: TXFIFORES Position      */
+#define USART3_FCR_TXFIFORES_Msk                              (0x01UL << USART3_FCR_TXFIFORES_Pos)                      /*!< USART3 FCR: TXFIFORES Mask          */
+#define USART3_FCR_DMAMODE_Pos                                3                                                         /*!< USART3 FCR: DMAMODE Position        */
+#define USART3_FCR_DMAMODE_Msk                                (0x01UL << USART3_FCR_DMAMODE_Pos)                        /*!< USART3 FCR: DMAMODE Mask            */
+#define USART3_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART3 FCR: RXTRIGLVL Position      */
+#define USART3_FCR_RXTRIGLVL_Msk                              (0x03UL << USART3_FCR_RXTRIGLVL_Pos)                      /*!< USART3 FCR: RXTRIGLVL Mask          */
+
+// ---------------------------------------  USART3_IIR  -------------------------------------------
+#define USART3_IIR_INTSTATUS_Pos                              0                                                         /*!< USART3 IIR: INTSTATUS Position      */
+#define USART3_IIR_INTSTATUS_Msk                              (0x01UL << USART3_IIR_INTSTATUS_Pos)                      /*!< USART3 IIR: INTSTATUS Mask          */
+#define USART3_IIR_INTID_Pos                                  1                                                         /*!< USART3 IIR: INTID Position          */
+#define USART3_IIR_INTID_Msk                                  (0x07UL << USART3_IIR_INTID_Pos)                          /*!< USART3 IIR: INTID Mask              */
+#define USART3_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART3 IIR: FIFOENABLE Position     */
+#define USART3_IIR_FIFOENABLE_Msk                             (0x03UL << USART3_IIR_FIFOENABLE_Pos)                     /*!< USART3 IIR: FIFOENABLE Mask         */
+#define USART3_IIR_ABEOINT_Pos                                8                                                         /*!< USART3 IIR: ABEOINT Position        */
+#define USART3_IIR_ABEOINT_Msk                                (0x01UL << USART3_IIR_ABEOINT_Pos)                        /*!< USART3 IIR: ABEOINT Mask            */
+#define USART3_IIR_ABTOINT_Pos                                9                                                         /*!< USART3 IIR: ABTOINT Position        */
+#define USART3_IIR_ABTOINT_Msk                                (0x01UL << USART3_IIR_ABTOINT_Pos)                        /*!< USART3 IIR: ABTOINT Mask            */
+
+// ---------------------------------------  USART3_LCR  -------------------------------------------
+#define USART3_LCR_WLS_Pos                                    0                                                         /*!< USART3 LCR: WLS Position            */
+#define USART3_LCR_WLS_Msk                                    (0x03UL << USART3_LCR_WLS_Pos)                            /*!< USART3 LCR: WLS Mask                */
+#define USART3_LCR_SBS_Pos                                    2                                                         /*!< USART3 LCR: SBS Position            */
+#define USART3_LCR_SBS_Msk                                    (0x01UL << USART3_LCR_SBS_Pos)                            /*!< USART3 LCR: SBS Mask                */
+#define USART3_LCR_PE_Pos                                     3                                                         /*!< USART3 LCR: PE Position             */
+#define USART3_LCR_PE_Msk                                     (0x01UL << USART3_LCR_PE_Pos)                             /*!< USART3 LCR: PE Mask                 */
+#define USART3_LCR_PS_Pos                                     4                                                         /*!< USART3 LCR: PS Position             */
+#define USART3_LCR_PS_Msk                                     (0x03UL << USART3_LCR_PS_Pos)                             /*!< USART3 LCR: PS Mask                 */
+#define USART3_LCR_BC_Pos                                     6                                                         /*!< USART3 LCR: BC Position             */
+#define USART3_LCR_BC_Msk                                     (0x01UL << USART3_LCR_BC_Pos)                             /*!< USART3 LCR: BC Mask                 */
+#define USART3_LCR_DLAB_Pos                                   7                                                         /*!< USART3 LCR: DLAB Position           */
+#define USART3_LCR_DLAB_Msk                                   (0x01UL << USART3_LCR_DLAB_Pos)                           /*!< USART3 LCR: DLAB Mask               */
+
+// ---------------------------------------  USART3_LSR  -------------------------------------------
+#define USART3_LSR_RDR_Pos                                    0                                                         /*!< USART3 LSR: RDR Position            */
+#define USART3_LSR_RDR_Msk                                    (0x01UL << USART3_LSR_RDR_Pos)                            /*!< USART3 LSR: RDR Mask                */
+#define USART3_LSR_OE_Pos                                     1                                                         /*!< USART3 LSR: OE Position             */
+#define USART3_LSR_OE_Msk                                     (0x01UL << USART3_LSR_OE_Pos)                             /*!< USART3 LSR: OE Mask                 */
+#define USART3_LSR_PE_Pos                                     2                                                         /*!< USART3 LSR: PE Position             */
+#define USART3_LSR_PE_Msk                                     (0x01UL << USART3_LSR_PE_Pos)                             /*!< USART3 LSR: PE Mask                 */
+#define USART3_LSR_FE_Pos                                     3                                                         /*!< USART3 LSR: FE Position             */
+#define USART3_LSR_FE_Msk                                     (0x01UL << USART3_LSR_FE_Pos)                             /*!< USART3 LSR: FE Mask                 */
+#define USART3_LSR_BI_Pos                                     4                                                         /*!< USART3 LSR: BI Position             */
+#define USART3_LSR_BI_Msk                                     (0x01UL << USART3_LSR_BI_Pos)                             /*!< USART3 LSR: BI Mask                 */
+#define USART3_LSR_THRE_Pos                                   5                                                         /*!< USART3 LSR: THRE Position           */
+#define USART3_LSR_THRE_Msk                                   (0x01UL << USART3_LSR_THRE_Pos)                           /*!< USART3 LSR: THRE Mask               */
+#define USART3_LSR_TEMT_Pos                                   6                                                         /*!< USART3 LSR: TEMT Position           */
+#define USART3_LSR_TEMT_Msk                                   (0x01UL << USART3_LSR_TEMT_Pos)                           /*!< USART3 LSR: TEMT Mask               */
+#define USART3_LSR_RXFE_Pos                                   7                                                         /*!< USART3 LSR: RXFE Position           */
+#define USART3_LSR_RXFE_Msk                                   (0x01UL << USART3_LSR_RXFE_Pos)                           /*!< USART3 LSR: RXFE Mask               */
+#define USART3_LSR_TXERR_Pos                                  8                                                         /*!< USART3 LSR: TXERR Position          */
+#define USART3_LSR_TXERR_Msk                                  (0x01UL << USART3_LSR_TXERR_Pos)                          /*!< USART3 LSR: TXERR Mask              */
+
+// ---------------------------------------  USART3_SCR  -------------------------------------------
+#define USART3_SCR_PAD_Pos                                    0                                                         /*!< USART3 SCR: PAD Position            */
+#define USART3_SCR_PAD_Msk                                    (0x000000ffUL << USART3_SCR_PAD_Pos)                      /*!< USART3 SCR: PAD Mask                */
+
+// ---------------------------------------  USART3_ACR  -------------------------------------------
+#define USART3_ACR_START_Pos                                  0                                                         /*!< USART3 ACR: START Position          */
+#define USART3_ACR_START_Msk                                  (0x01UL << USART3_ACR_START_Pos)                          /*!< USART3 ACR: START Mask              */
+#define USART3_ACR_MODE_Pos                                   1                                                         /*!< USART3 ACR: MODE Position           */
+#define USART3_ACR_MODE_Msk                                   (0x01UL << USART3_ACR_MODE_Pos)                           /*!< USART3 ACR: MODE Mask               */
+#define USART3_ACR_AUTORESTART_Pos                            2                                                         /*!< USART3 ACR: AUTORESTART Position    */
+#define USART3_ACR_AUTORESTART_Msk                            (0x01UL << USART3_ACR_AUTORESTART_Pos)                    /*!< USART3 ACR: AUTORESTART Mask        */
+#define USART3_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART3 ACR: ABEOINTCLR Position     */
+#define USART3_ACR_ABEOINTCLR_Msk                             (0x01UL << USART3_ACR_ABEOINTCLR_Pos)                     /*!< USART3 ACR: ABEOINTCLR Mask         */
+#define USART3_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART3 ACR: ABTOINTCLR Position     */
+#define USART3_ACR_ABTOINTCLR_Msk                             (0x01UL << USART3_ACR_ABTOINTCLR_Pos)                     /*!< USART3 ACR: ABTOINTCLR Mask         */
+
+// ---------------------------------------  USART3_ICR  -------------------------------------------
+#define USART3_ICR_IRDAEN_Pos                                 0                                                         /*!< USART3 ICR: IRDAEN Position         */
+#define USART3_ICR_IRDAEN_Msk                                 (0x01UL << USART3_ICR_IRDAEN_Pos)                         /*!< USART3 ICR: IRDAEN Mask             */
+#define USART3_ICR_IRDAINV_Pos                                1                                                         /*!< USART3 ICR: IRDAINV Position        */
+#define USART3_ICR_IRDAINV_Msk                                (0x01UL << USART3_ICR_IRDAINV_Pos)                        /*!< USART3 ICR: IRDAINV Mask            */
+#define USART3_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART3 ICR: FIXPULSEEN Position     */
+#define USART3_ICR_FIXPULSEEN_Msk                             (0x01UL << USART3_ICR_FIXPULSEEN_Pos)                     /*!< USART3 ICR: FIXPULSEEN Mask         */
+#define USART3_ICR_PULSEDIV_Pos                               3                                                         /*!< USART3 ICR: PULSEDIV Position       */
+#define USART3_ICR_PULSEDIV_Msk                               (0x07UL << USART3_ICR_PULSEDIV_Pos)                       /*!< USART3 ICR: PULSEDIV Mask           */
+
+// ---------------------------------------  USART3_FDR  -------------------------------------------
+#define USART3_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART3 FDR: DIVADDVAL Position      */
+#define USART3_FDR_DIVADDVAL_Msk                              (0x0fUL << USART3_FDR_DIVADDVAL_Pos)                      /*!< USART3 FDR: DIVADDVAL Mask          */
+#define USART3_FDR_MULVAL_Pos                                 4                                                         /*!< USART3 FDR: MULVAL Position         */
+#define USART3_FDR_MULVAL_Msk                                 (0x0fUL << USART3_FDR_MULVAL_Pos)                         /*!< USART3 FDR: MULVAL Mask             */
+
+// ---------------------------------------  USART3_OSR  -------------------------------------------
+#define USART3_OSR_OSFRAC_Pos                                 1                                                         /*!< USART3 OSR: OSFRAC Position         */
+#define USART3_OSR_OSFRAC_Msk                                 (0x07UL << USART3_OSR_OSFRAC_Pos)                         /*!< USART3 OSR: OSFRAC Mask             */
+#define USART3_OSR_OSINT_Pos                                  4                                                         /*!< USART3 OSR: OSINT Position          */
+#define USART3_OSR_OSINT_Msk                                  (0x0fUL << USART3_OSR_OSINT_Pos)                          /*!< USART3 OSR: OSINT Mask              */
+#define USART3_OSR_FDINT_Pos                                  8                                                         /*!< USART3 OSR: FDINT Position          */
+#define USART3_OSR_FDINT_Msk                                  (0x7fUL << USART3_OSR_FDINT_Pos)                          /*!< USART3 OSR: FDINT Mask              */
+
+// ---------------------------------------  USART3_HDEN  ------------------------------------------
+#define USART3_HDEN_HDEN_Pos                                  0                                                         /*!< USART3 HDEN: HDEN Position          */
+#define USART3_HDEN_HDEN_Msk                                  (0x01UL << USART3_HDEN_HDEN_Pos)                          /*!< USART3 HDEN: HDEN Mask              */
+
+// -------------------------------------  USART3_SCICTRL  -----------------------------------------
+#define USART3_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART3 SCICTRL: SCIEN Position      */
+#define USART3_SCICTRL_SCIEN_Msk                              (0x01UL << USART3_SCICTRL_SCIEN_Pos)                      /*!< USART3 SCICTRL: SCIEN Mask          */
+#define USART3_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART3 SCICTRL: NACKDIS Position    */
+#define USART3_SCICTRL_NACKDIS_Msk                            (0x01UL << USART3_SCICTRL_NACKDIS_Pos)                    /*!< USART3 SCICTRL: NACKDIS Mask        */
+#define USART3_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART3 SCICTRL: PROTSEL Position    */
+#define USART3_SCICTRL_PROTSEL_Msk                            (0x01UL << USART3_SCICTRL_PROTSEL_Pos)                    /*!< USART3 SCICTRL: PROTSEL Mask        */
+#define USART3_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART3 SCICTRL: TXRETRY Position    */
+#define USART3_SCICTRL_TXRETRY_Msk                            (0x07UL << USART3_SCICTRL_TXRETRY_Pos)                    /*!< USART3 SCICTRL: TXRETRY Mask        */
+#define USART3_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART3 SCICTRL: GUARDTIME Position  */
+#define USART3_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos)            /*!< USART3 SCICTRL: GUARDTIME Mask      */
+
+// ------------------------------------  USART3_RS485CTRL  ----------------------------------------
+#define USART3_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART3 RS485CTRL: NMMEN Position    */
+#define USART3_RS485CTRL_NMMEN_Msk                            (0x01UL << USART3_RS485CTRL_NMMEN_Pos)                    /*!< USART3 RS485CTRL: NMMEN Mask        */
+#define USART3_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART3 RS485CTRL: RXDIS Position    */
+#define USART3_RS485CTRL_RXDIS_Msk                            (0x01UL << USART3_RS485CTRL_RXDIS_Pos)                    /*!< USART3 RS485CTRL: RXDIS Mask        */
+#define USART3_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART3 RS485CTRL: AADEN Position    */
+#define USART3_RS485CTRL_AADEN_Msk                            (0x01UL << USART3_RS485CTRL_AADEN_Pos)                    /*!< USART3 RS485CTRL: AADEN Mask        */
+#define USART3_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART3 RS485CTRL: DCTRL Position    */
+#define USART3_RS485CTRL_DCTRL_Msk                            (0x01UL << USART3_RS485CTRL_DCTRL_Pos)                    /*!< USART3 RS485CTRL: DCTRL Mask        */
+#define USART3_RS485CTRL_OINV_Pos                             5                                                         /*!< USART3 RS485CTRL: OINV Position     */
+#define USART3_RS485CTRL_OINV_Msk                             (0x01UL << USART3_RS485CTRL_OINV_Pos)                     /*!< USART3 RS485CTRL: OINV Mask         */
+
+// ----------------------------------  USART3_RS485ADRMATCH  --------------------------------------
+#define USART3_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART3 RS485ADRMATCH: ADRMATCH Position */
+#define USART3_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */
+
+// -------------------------------------  USART3_RS485DLY  ----------------------------------------
+#define USART3_RS485DLY_DLY_Pos                               0                                                         /*!< USART3 RS485DLY: DLY Position       */
+#define USART3_RS485DLY_DLY_Msk                               (0x000000ffUL << USART3_RS485DLY_DLY_Pos)                 /*!< USART3 RS485DLY: DLY Mask           */
+
+// -------------------------------------  USART3_SYNCCTRL  ----------------------------------------
+#define USART3_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART3 SYNCCTRL: SYNC Position      */
+#define USART3_SYNCCTRL_SYNC_Msk                              (0x01UL << USART3_SYNCCTRL_SYNC_Pos)                      /*!< USART3 SYNCCTRL: SYNC Mask          */
+#define USART3_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART3 SYNCCTRL: CSRC Position      */
+#define USART3_SYNCCTRL_CSRC_Msk                              (0x01UL << USART3_SYNCCTRL_CSRC_Pos)                      /*!< USART3 SYNCCTRL: CSRC Mask          */
+#define USART3_SYNCCTRL_FES_Pos                               2                                                         /*!< USART3 SYNCCTRL: FES Position       */
+#define USART3_SYNCCTRL_FES_Msk                               (0x01UL << USART3_SYNCCTRL_FES_Pos)                       /*!< USART3 SYNCCTRL: FES Mask           */
+#define USART3_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART3 SYNCCTRL: TSBYPASS Position  */
+#define USART3_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART3 SYNCCTRL: TSBYPASS Mask      */
+#define USART3_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART3 SYNCCTRL: CSCEN Position     */
+#define USART3_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART3_SYNCCTRL_CSCEN_Pos)                     /*!< USART3 SYNCCTRL: CSCEN Mask         */
+#define USART3_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART3 SYNCCTRL: SSSDIS Position    */
+#define USART3_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos)                    /*!< USART3 SYNCCTRL: SSSDIS Mask        */
+#define USART3_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART3 SYNCCTRL: CCCLR Position     */
+#define USART3_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART3_SYNCCTRL_CCCLR_Pos)                     /*!< USART3 SYNCCTRL: CCCLR Mask         */
+
+// ---------------------------------------  USART3_TER  -------------------------------------------
+#define USART3_TER_TXEN_Pos                                   0                                                         /*!< USART3 TER: TXEN Position           */
+#define USART3_TER_TXEN_Msk                                   (0x01UL << USART3_TER_TXEN_Pos)                           /*!< USART3 TER: TXEN Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 UART1 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  UART1_RBR  -------------------------------------------
+#define UART1_RBR_RBR_Pos                                     0                                                         /*!< UART1 RBR: RBR Position             */
+#define UART1_RBR_RBR_Msk                                     (0x000000ffUL << UART1_RBR_RBR_Pos)                       /*!< UART1 RBR: RBR Mask                 */
+
+// ----------------------------------------  UART1_THR  -------------------------------------------
+#define UART1_THR_THR_Pos                                     0                                                         /*!< UART1 THR: THR Position             */
+#define UART1_THR_THR_Msk                                     (0x000000ffUL << UART1_THR_THR_Pos)                       /*!< UART1 THR: THR Mask                 */
+
+// ----------------------------------------  UART1_DLL  -------------------------------------------
+#define UART1_DLL_DLLSB_Pos                                   0                                                         /*!< UART1 DLL: DLLSB Position           */
+#define UART1_DLL_DLLSB_Msk                                   (0x000000ffUL << UART1_DLL_DLLSB_Pos)                     /*!< UART1 DLL: DLLSB Mask               */
+
+// ----------------------------------------  UART1_DLM  -------------------------------------------
+#define UART1_DLM_DLMSB_Pos                                   0                                                         /*!< UART1 DLM: DLMSB Position           */
+#define UART1_DLM_DLMSB_Msk                                   (0x000000ffUL << UART1_DLM_DLMSB_Pos)                     /*!< UART1 DLM: DLMSB Mask               */
+
+// ----------------------------------------  UART1_IER  -------------------------------------------
+#define UART1_IER_RBRIE_Pos                                   0                                                         /*!< UART1 IER: RBRIE Position           */
+#define UART1_IER_RBRIE_Msk                                   (0x01UL << UART1_IER_RBRIE_Pos)                           /*!< UART1 IER: RBRIE Mask               */
+#define UART1_IER_THREIE_Pos                                  1                                                         /*!< UART1 IER: THREIE Position          */
+#define UART1_IER_THREIE_Msk                                  (0x01UL << UART1_IER_THREIE_Pos)                          /*!< UART1 IER: THREIE Mask              */
+#define UART1_IER_RXIE_Pos                                    2                                                         /*!< UART1 IER: RXIE Position            */
+#define UART1_IER_RXIE_Msk                                    (0x01UL << UART1_IER_RXIE_Pos)                            /*!< UART1 IER: RXIE Mask                */
+#define UART1_IER_MSIE_Pos                                    3                                                         /*!< UART1 IER: MSIE Position            */
+#define UART1_IER_MSIE_Msk                                    (0x01UL << UART1_IER_MSIE_Pos)                            /*!< UART1 IER: MSIE Mask                */
+#define UART1_IER_CTSIE_Pos                                   7                                                         /*!< UART1 IER: CTSIE Position           */
+#define UART1_IER_CTSIE_Msk                                   (0x01UL << UART1_IER_CTSIE_Pos)                           /*!< UART1 IER: CTSIE Mask               */
+#define UART1_IER_ABEOIE_Pos                                  8                                                         /*!< UART1 IER: ABEOIE Position          */
+#define UART1_IER_ABEOIE_Msk                                  (0x01UL << UART1_IER_ABEOIE_Pos)                          /*!< UART1 IER: ABEOIE Mask              */
+#define UART1_IER_ABTOIE_Pos                                  9                                                         /*!< UART1 IER: ABTOIE Position          */
+#define UART1_IER_ABTOIE_Msk                                  (0x01UL << UART1_IER_ABTOIE_Pos)                          /*!< UART1 IER: ABTOIE Mask              */
+
+// ----------------------------------------  UART1_IIR  -------------------------------------------
+#define UART1_IIR_INTSTATUS_Pos                               0                                                         /*!< UART1 IIR: INTSTATUS Position       */
+#define UART1_IIR_INTSTATUS_Msk                               (0x01UL << UART1_IIR_INTSTATUS_Pos)                       /*!< UART1 IIR: INTSTATUS Mask           */
+#define UART1_IIR_INTID_Pos                                   1                                                         /*!< UART1 IIR: INTID Position           */
+#define UART1_IIR_INTID_Msk                                   (0x07UL << UART1_IIR_INTID_Pos)                           /*!< UART1 IIR: INTID Mask               */
+#define UART1_IIR_FIFOENABLE_Pos                              6                                                         /*!< UART1 IIR: FIFOENABLE Position      */
+#define UART1_IIR_FIFOENABLE_Msk                              (0x03UL << UART1_IIR_FIFOENABLE_Pos)                      /*!< UART1 IIR: FIFOENABLE Mask          */
+#define UART1_IIR_ABEOINT_Pos                                 8                                                         /*!< UART1 IIR: ABEOINT Position         */
+#define UART1_IIR_ABEOINT_Msk                                 (0x01UL << UART1_IIR_ABEOINT_Pos)                         /*!< UART1 IIR: ABEOINT Mask             */
+#define UART1_IIR_ABTOINT_Pos                                 9                                                         /*!< UART1 IIR: ABTOINT Position         */
+#define UART1_IIR_ABTOINT_Msk                                 (0x01UL << UART1_IIR_ABTOINT_Pos)                         /*!< UART1 IIR: ABTOINT Mask             */
+
+// ----------------------------------------  UART1_FCR  -------------------------------------------
+#define UART1_FCR_FIFOEN_Pos                                  0                                                         /*!< UART1 FCR: FIFOEN Position          */
+#define UART1_FCR_FIFOEN_Msk                                  (0x01UL << UART1_FCR_FIFOEN_Pos)                          /*!< UART1 FCR: FIFOEN Mask              */
+#define UART1_FCR_RXFIFORES_Pos                               1                                                         /*!< UART1 FCR: RXFIFORES Position       */
+#define UART1_FCR_RXFIFORES_Msk                               (0x01UL << UART1_FCR_RXFIFORES_Pos)                       /*!< UART1 FCR: RXFIFORES Mask           */
+#define UART1_FCR_TXFIFORES_Pos                               2                                                         /*!< UART1 FCR: TXFIFORES Position       */
+#define UART1_FCR_TXFIFORES_Msk                               (0x01UL << UART1_FCR_TXFIFORES_Pos)                       /*!< UART1 FCR: TXFIFORES Mask           */
+#define UART1_FCR_DMAMODE_Pos                                 3                                                         /*!< UART1 FCR: DMAMODE Position         */
+#define UART1_FCR_DMAMODE_Msk                                 (0x01UL << UART1_FCR_DMAMODE_Pos)                         /*!< UART1 FCR: DMAMODE Mask             */
+#define UART1_FCR_RXTRIGLVL_Pos                               6                                                         /*!< UART1 FCR: RXTRIGLVL Position       */
+#define UART1_FCR_RXTRIGLVL_Msk                               (0x03UL << UART1_FCR_RXTRIGLVL_Pos)                       /*!< UART1 FCR: RXTRIGLVL Mask           */
+
+// ----------------------------------------  UART1_LCR  -------------------------------------------
+#define UART1_LCR_WLS_Pos                                     0                                                         /*!< UART1 LCR: WLS Position             */
+#define UART1_LCR_WLS_Msk                                     (0x03UL << UART1_LCR_WLS_Pos)                             /*!< UART1 LCR: WLS Mask                 */
+#define UART1_LCR_SBS_Pos                                     2                                                         /*!< UART1 LCR: SBS Position             */
+#define UART1_LCR_SBS_Msk                                     (0x01UL << UART1_LCR_SBS_Pos)                             /*!< UART1 LCR: SBS Mask                 */
+#define UART1_LCR_PE_Pos                                      3                                                         /*!< UART1 LCR: PE Position              */
+#define UART1_LCR_PE_Msk                                      (0x01UL << UART1_LCR_PE_Pos)                              /*!< UART1 LCR: PE Mask                  */
+#define UART1_LCR_PS_Pos                                      4                                                         /*!< UART1 LCR: PS Position              */
+#define UART1_LCR_PS_Msk                                      (0x03UL << UART1_LCR_PS_Pos)                              /*!< UART1 LCR: PS Mask                  */
+#define UART1_LCR_BC_Pos                                      6                                                         /*!< UART1 LCR: BC Position              */
+#define UART1_LCR_BC_Msk                                      (0x01UL << UART1_LCR_BC_Pos)                              /*!< UART1 LCR: BC Mask                  */
+#define UART1_LCR_DLAB_Pos                                    7                                                         /*!< UART1 LCR: DLAB Position            */
+#define UART1_LCR_DLAB_Msk                                    (0x01UL << UART1_LCR_DLAB_Pos)                            /*!< UART1 LCR: DLAB Mask                */
+
+// ----------------------------------------  UART1_MCR  -------------------------------------------
+#define UART1_MCR_DTRCTRL_Pos                                 0                                                         /*!< UART1 MCR: DTRCTRL Position         */
+#define UART1_MCR_DTRCTRL_Msk                                 (0x01UL << UART1_MCR_DTRCTRL_Pos)                         /*!< UART1 MCR: DTRCTRL Mask             */
+#define UART1_MCR_RTSCTRL_Pos                                 1                                                         /*!< UART1 MCR: RTSCTRL Position         */
+#define UART1_MCR_RTSCTRL_Msk                                 (0x01UL << UART1_MCR_RTSCTRL_Pos)                         /*!< UART1 MCR: RTSCTRL Mask             */
+#define UART1_MCR_LMS_Pos                                     4                                                         /*!< UART1 MCR: LMS Position             */
+#define UART1_MCR_LMS_Msk                                     (0x01UL << UART1_MCR_LMS_Pos)                             /*!< UART1 MCR: LMS Mask                 */
+#define UART1_MCR_RTSEN_Pos                                   6                                                         /*!< UART1 MCR: RTSEN Position           */
+#define UART1_MCR_RTSEN_Msk                                   (0x01UL << UART1_MCR_RTSEN_Pos)                           /*!< UART1 MCR: RTSEN Mask               */
+#define UART1_MCR_CTSEN_Pos                                   7                                                         /*!< UART1 MCR: CTSEN Position           */
+#define UART1_MCR_CTSEN_Msk                                   (0x01UL << UART1_MCR_CTSEN_Pos)                           /*!< UART1 MCR: CTSEN Mask               */
+
+// ----------------------------------------  UART1_LSR  -------------------------------------------
+#define UART1_LSR_RDR_Pos                                     0                                                         /*!< UART1 LSR: RDR Position             */
+#define UART1_LSR_RDR_Msk                                     (0x01UL << UART1_LSR_RDR_Pos)                             /*!< UART1 LSR: RDR Mask                 */
+#define UART1_LSR_OE_Pos                                      1                                                         /*!< UART1 LSR: OE Position              */
+#define UART1_LSR_OE_Msk                                      (0x01UL << UART1_LSR_OE_Pos)                              /*!< UART1 LSR: OE Mask                  */
+#define UART1_LSR_PE_Pos                                      2                                                         /*!< UART1 LSR: PE Position              */
+#define UART1_LSR_PE_Msk                                      (0x01UL << UART1_LSR_PE_Pos)                              /*!< UART1 LSR: PE Mask                  */
+#define UART1_LSR_FE_Pos                                      3                                                         /*!< UART1 LSR: FE Position              */
+#define UART1_LSR_FE_Msk                                      (0x01UL << UART1_LSR_FE_Pos)                              /*!< UART1 LSR: FE Mask                  */
+#define UART1_LSR_BI_Pos                                      4                                                         /*!< UART1 LSR: BI Position              */
+#define UART1_LSR_BI_Msk                                      (0x01UL << UART1_LSR_BI_Pos)                              /*!< UART1 LSR: BI Mask                  */
+#define UART1_LSR_THRE_Pos                                    5                                                         /*!< UART1 LSR: THRE Position            */
+#define UART1_LSR_THRE_Msk                                    (0x01UL << UART1_LSR_THRE_Pos)                            /*!< UART1 LSR: THRE Mask                */
+#define UART1_LSR_TEMT_Pos                                    6                                                         /*!< UART1 LSR: TEMT Position            */
+#define UART1_LSR_TEMT_Msk                                    (0x01UL << UART1_LSR_TEMT_Pos)                            /*!< UART1 LSR: TEMT Mask                */
+#define UART1_LSR_RXFE_Pos                                    7                                                         /*!< UART1 LSR: RXFE Position            */
+#define UART1_LSR_RXFE_Msk                                    (0x01UL << UART1_LSR_RXFE_Pos)                            /*!< UART1 LSR: RXFE Mask                */
+
+// ----------------------------------------  UART1_MSR  -------------------------------------------
+#define UART1_MSR_DCTS_Pos                                    0                                                         /*!< UART1 MSR: DCTS Position            */
+#define UART1_MSR_DCTS_Msk                                    (0x01UL << UART1_MSR_DCTS_Pos)                            /*!< UART1 MSR: DCTS Mask                */
+#define UART1_MSR_DDSR_Pos                                    1                                                         /*!< UART1 MSR: DDSR Position            */
+#define UART1_MSR_DDSR_Msk                                    (0x01UL << UART1_MSR_DDSR_Pos)                            /*!< UART1 MSR: DDSR Mask                */
+#define UART1_MSR_TERI_Pos                                    2                                                         /*!< UART1 MSR: TERI Position            */
+#define UART1_MSR_TERI_Msk                                    (0x01UL << UART1_MSR_TERI_Pos)                            /*!< UART1 MSR: TERI Mask                */
+#define UART1_MSR_DDCD_Pos                                    3                                                         /*!< UART1 MSR: DDCD Position            */
+#define UART1_MSR_DDCD_Msk                                    (0x01UL << UART1_MSR_DDCD_Pos)                            /*!< UART1 MSR: DDCD Mask                */
+#define UART1_MSR_CTS_Pos                                     4                                                         /*!< UART1 MSR: CTS Position             */
+#define UART1_MSR_CTS_Msk                                     (0x01UL << UART1_MSR_CTS_Pos)                             /*!< UART1 MSR: CTS Mask                 */
+#define UART1_MSR_DSR_Pos                                     5                                                         /*!< UART1 MSR: DSR Position             */
+#define UART1_MSR_DSR_Msk                                     (0x01UL << UART1_MSR_DSR_Pos)                             /*!< UART1 MSR: DSR Mask                 */
+#define UART1_MSR_RI_Pos                                      6                                                         /*!< UART1 MSR: RI Position              */
+#define UART1_MSR_RI_Msk                                      (0x01UL << UART1_MSR_RI_Pos)                              /*!< UART1 MSR: RI Mask                  */
+#define UART1_MSR_DCD_Pos                                     7                                                         /*!< UART1 MSR: DCD Position             */
+#define UART1_MSR_DCD_Msk                                     (0x01UL << UART1_MSR_DCD_Pos)                             /*!< UART1 MSR: DCD Mask                 */
+
+// ----------------------------------------  UART1_SCR  -------------------------------------------
+#define UART1_SCR_Pad_Pos                                     0                                                         /*!< UART1 SCR: Pad Position             */
+#define UART1_SCR_Pad_Msk                                     (0x000000ffUL << UART1_SCR_Pad_Pos)                       /*!< UART1 SCR: Pad Mask                 */
+
+// ----------------------------------------  UART1_ACR  -------------------------------------------
+#define UART1_ACR_START_Pos                                   0                                                         /*!< UART1 ACR: START Position           */
+#define UART1_ACR_START_Msk                                   (0x01UL << UART1_ACR_START_Pos)                           /*!< UART1 ACR: START Mask               */
+#define UART1_ACR_MODE_Pos                                    1                                                         /*!< UART1 ACR: MODE Position            */
+#define UART1_ACR_MODE_Msk                                    (0x01UL << UART1_ACR_MODE_Pos)                            /*!< UART1 ACR: MODE Mask                */
+#define UART1_ACR_AUTORESTART_Pos                             2                                                         /*!< UART1 ACR: AUTORESTART Position     */
+#define UART1_ACR_AUTORESTART_Msk                             (0x01UL << UART1_ACR_AUTORESTART_Pos)                     /*!< UART1 ACR: AUTORESTART Mask         */
+#define UART1_ACR_ABEOINTCLR_Pos                              8                                                         /*!< UART1 ACR: ABEOINTCLR Position      */
+#define UART1_ACR_ABEOINTCLR_Msk                              (0x01UL << UART1_ACR_ABEOINTCLR_Pos)                      /*!< UART1 ACR: ABEOINTCLR Mask          */
+#define UART1_ACR_ABTOINTCLR_Pos                              9                                                         /*!< UART1 ACR: ABTOINTCLR Position      */
+#define UART1_ACR_ABTOINTCLR_Msk                              (0x01UL << UART1_ACR_ABTOINTCLR_Pos)                      /*!< UART1 ACR: ABTOINTCLR Mask          */
+
+// ----------------------------------------  UART1_FDR  -------------------------------------------
+#define UART1_FDR_DIVADDVAL_Pos                               0                                                         /*!< UART1 FDR: DIVADDVAL Position       */
+#define UART1_FDR_DIVADDVAL_Msk                               (0x0fUL << UART1_FDR_DIVADDVAL_Pos)                       /*!< UART1 FDR: DIVADDVAL Mask           */
+#define UART1_FDR_MULVAL_Pos                                  4                                                         /*!< UART1 FDR: MULVAL Position          */
+#define UART1_FDR_MULVAL_Msk                                  (0x0fUL << UART1_FDR_MULVAL_Pos)                          /*!< UART1 FDR: MULVAL Mask              */
+
+// ----------------------------------------  UART1_TER  -------------------------------------------
+#define UART1_TER_TXEN_Pos                                    7                                                         /*!< UART1 TER: TXEN Position            */
+#define UART1_TER_TXEN_Msk                                    (0x01UL << UART1_TER_TXEN_Pos)                            /*!< UART1 TER: TXEN Mask                */
+
+// -------------------------------------  UART1_RS485CTRL  ----------------------------------------
+#define UART1_RS485CTRL_NMMEN_Pos                             0                                                         /*!< UART1 RS485CTRL: NMMEN Position     */
+#define UART1_RS485CTRL_NMMEN_Msk                             (0x01UL << UART1_RS485CTRL_NMMEN_Pos)                     /*!< UART1 RS485CTRL: NMMEN Mask         */
+#define UART1_RS485CTRL_RXDIS_Pos                             1                                                         /*!< UART1 RS485CTRL: RXDIS Position     */
+#define UART1_RS485CTRL_RXDIS_Msk                             (0x01UL << UART1_RS485CTRL_RXDIS_Pos)                     /*!< UART1 RS485CTRL: RXDIS Mask         */
+#define UART1_RS485CTRL_AADEN_Pos                             2                                                         /*!< UART1 RS485CTRL: AADEN Position     */
+#define UART1_RS485CTRL_AADEN_Msk                             (0x01UL << UART1_RS485CTRL_AADEN_Pos)                     /*!< UART1 RS485CTRL: AADEN Mask         */
+#define UART1_RS485CTRL_SEL_Pos                               3                                                         /*!< UART1 RS485CTRL: SEL Position       */
+#define UART1_RS485CTRL_SEL_Msk                               (0x01UL << UART1_RS485CTRL_SEL_Pos)                       /*!< UART1 RS485CTRL: SEL Mask           */
+#define UART1_RS485CTRL_DCTRL_Pos                             4                                                         /*!< UART1 RS485CTRL: DCTRL Position     */
+#define UART1_RS485CTRL_DCTRL_Msk                             (0x01UL << UART1_RS485CTRL_DCTRL_Pos)                     /*!< UART1 RS485CTRL: DCTRL Mask         */
+#define UART1_RS485CTRL_OINV_Pos                              5                                                         /*!< UART1 RS485CTRL: OINV Position      */
+#define UART1_RS485CTRL_OINV_Msk                              (0x01UL << UART1_RS485CTRL_OINV_Pos)                      /*!< UART1 RS485CTRL: OINV Mask          */
+
+// -----------------------------------  UART1_RS485ADRMATCH  --------------------------------------
+#define UART1_RS485ADRMATCH_ADRMATCH_Pos                      0                                                         /*!< UART1 RS485ADRMATCH: ADRMATCH Position */
+#define UART1_RS485ADRMATCH_ADRMATCH_Msk                      (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos)        /*!< UART1 RS485ADRMATCH: ADRMATCH Mask  */
+
+// -------------------------------------  UART1_RS485DLY  -----------------------------------------
+#define UART1_RS485DLY_DLY_Pos                                0                                                         /*!< UART1 RS485DLY: DLY Position        */
+#define UART1_RS485DLY_DLY_Msk                                (0x000000ffUL << UART1_RS485DLY_DLY_Pos)                  /*!< UART1 RS485DLY: DLY Mask            */
+
+// --------------------------------------  UART1_FIFOLVL  -----------------------------------------
+#define UART1_FIFOLVL_RXFIFILVL_Pos                           0                                                         /*!< UART1 FIFOLVL: RXFIFILVL Position   */
+#define UART1_FIFOLVL_RXFIFILVL_Msk                           (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos)                   /*!< UART1 FIFOLVL: RXFIFILVL Mask       */
+#define UART1_FIFOLVL_TXFIFOLVL_Pos                           8                                                         /*!< UART1 FIFOLVL: TXFIFOLVL Position   */
+#define UART1_FIFOLVL_TXFIFOLVL_Msk                           (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos)                   /*!< UART1 FIFOLVL: TXFIFOLVL Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SSP0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  SSP0_CR0  --------------------------------------------
+#define SSP0_CR0_DSS_Pos                                      0                                                         /*!< SSP0 CR0: DSS Position              */
+#define SSP0_CR0_DSS_Msk                                      (0x0fUL << SSP0_CR0_DSS_Pos)                              /*!< SSP0 CR0: DSS Mask                  */
+#define SSP0_CR0_FRF_Pos                                      4                                                         /*!< SSP0 CR0: FRF Position              */
+#define SSP0_CR0_FRF_Msk                                      (0x03UL << SSP0_CR0_FRF_Pos)                              /*!< SSP0 CR0: FRF Mask                  */
+#define SSP0_CR0_CPOL_Pos                                     6                                                         /*!< SSP0 CR0: CPOL Position             */
+#define SSP0_CR0_CPOL_Msk                                     (0x01UL << SSP0_CR0_CPOL_Pos)                             /*!< SSP0 CR0: CPOL Mask                 */
+#define SSP0_CR0_CPHA_Pos                                     7                                                         /*!< SSP0 CR0: CPHA Position             */
+#define SSP0_CR0_CPHA_Msk                                     (0x01UL << SSP0_CR0_CPHA_Pos)                             /*!< SSP0 CR0: CPHA Mask                 */
+#define SSP0_CR0_SCR_Pos                                      8                                                         /*!< SSP0 CR0: SCR Position              */
+#define SSP0_CR0_SCR_Msk                                      (0x000000ffUL << SSP0_CR0_SCR_Pos)                        /*!< SSP0 CR0: SCR Mask                  */
+
+// ----------------------------------------  SSP0_CR1  --------------------------------------------
+#define SSP0_CR1_LBM_Pos                                      0                                                         /*!< SSP0 CR1: LBM Position              */
+#define SSP0_CR1_LBM_Msk                                      (0x01UL << SSP0_CR1_LBM_Pos)                              /*!< SSP0 CR1: LBM Mask                  */
+#define SSP0_CR1_SSE_Pos                                      1                                                         /*!< SSP0 CR1: SSE Position              */
+#define SSP0_CR1_SSE_Msk                                      (0x01UL << SSP0_CR1_SSE_Pos)                              /*!< SSP0 CR1: SSE Mask                  */
+#define SSP0_CR1_MS_Pos                                       2                                                         /*!< SSP0 CR1: MS Position               */
+#define SSP0_CR1_MS_Msk                                       (0x01UL << SSP0_CR1_MS_Pos)                               /*!< SSP0 CR1: MS Mask                   */
+#define SSP0_CR1_SOD_Pos                                      3                                                         /*!< SSP0 CR1: SOD Position              */
+#define SSP0_CR1_SOD_Msk                                      (0x01UL << SSP0_CR1_SOD_Pos)                              /*!< SSP0 CR1: SOD Mask                  */
+
+// -----------------------------------------  SSP0_DR  --------------------------------------------
+#define SSP0_DR_DATA_Pos                                      0                                                         /*!< SSP0 DR: DATA Position              */
+#define SSP0_DR_DATA_Msk                                      (0x0000ffffUL << SSP0_DR_DATA_Pos)                        /*!< SSP0 DR: DATA Mask                  */
+
+// -----------------------------------------  SSP0_SR  --------------------------------------------
+#define SSP0_SR_TFE_Pos                                       0                                                         /*!< SSP0 SR: TFE Position               */
+#define SSP0_SR_TFE_Msk                                       (0x01UL << SSP0_SR_TFE_Pos)                               /*!< SSP0 SR: TFE Mask                   */
+#define SSP0_SR_TNF_Pos                                       1                                                         /*!< SSP0 SR: TNF Position               */
+#define SSP0_SR_TNF_Msk                                       (0x01UL << SSP0_SR_TNF_Pos)                               /*!< SSP0 SR: TNF Mask                   */
+#define SSP0_SR_RNE_Pos                                       2                                                         /*!< SSP0 SR: RNE Position               */
+#define SSP0_SR_RNE_Msk                                       (0x01UL << SSP0_SR_RNE_Pos)                               /*!< SSP0 SR: RNE Mask                   */
+#define SSP0_SR_RFF_Pos                                       3                                                         /*!< SSP0 SR: RFF Position               */
+#define SSP0_SR_RFF_Msk                                       (0x01UL << SSP0_SR_RFF_Pos)                               /*!< SSP0 SR: RFF Mask                   */
+#define SSP0_SR_BSY_Pos                                       4                                                         /*!< SSP0 SR: BSY Position               */
+#define SSP0_SR_BSY_Msk                                       (0x01UL << SSP0_SR_BSY_Pos)                               /*!< SSP0 SR: BSY Mask                   */
+
+// ----------------------------------------  SSP0_CPSR  -------------------------------------------
+#define SSP0_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP0 CPSR: CPSDVSR Position         */
+#define SSP0_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos)                   /*!< SSP0 CPSR: CPSDVSR Mask             */
+
+// ----------------------------------------  SSP0_IMSC  -------------------------------------------
+#define SSP0_IMSC_RORIM_Pos                                   0                                                         /*!< SSP0 IMSC: RORIM Position           */
+#define SSP0_IMSC_RORIM_Msk                                   (0x01UL << SSP0_IMSC_RORIM_Pos)                           /*!< SSP0 IMSC: RORIM Mask               */
+#define SSP0_IMSC_RTIM_Pos                                    1                                                         /*!< SSP0 IMSC: RTIM Position            */
+#define SSP0_IMSC_RTIM_Msk                                    (0x01UL << SSP0_IMSC_RTIM_Pos)                            /*!< SSP0 IMSC: RTIM Mask                */
+#define SSP0_IMSC_RXIM_Pos                                    2                                                         /*!< SSP0 IMSC: RXIM Position            */
+#define SSP0_IMSC_RXIM_Msk                                    (0x01UL << SSP0_IMSC_RXIM_Pos)                            /*!< SSP0 IMSC: RXIM Mask                */
+#define SSP0_IMSC_TXIM_Pos                                    3                                                         /*!< SSP0 IMSC: TXIM Position            */
+#define SSP0_IMSC_TXIM_Msk                                    (0x01UL << SSP0_IMSC_TXIM_Pos)                            /*!< SSP0 IMSC: TXIM Mask                */
+
+// ----------------------------------------  SSP0_RIS  --------------------------------------------
+#define SSP0_RIS_RORRIS_Pos                                   0                                                         /*!< SSP0 RIS: RORRIS Position           */
+#define SSP0_RIS_RORRIS_Msk                                   (0x01UL << SSP0_RIS_RORRIS_Pos)                           /*!< SSP0 RIS: RORRIS Mask               */
+#define SSP0_RIS_RTRIS_Pos                                    1                                                         /*!< SSP0 RIS: RTRIS Position            */
+#define SSP0_RIS_RTRIS_Msk                                    (0x01UL << SSP0_RIS_RTRIS_Pos)                            /*!< SSP0 RIS: RTRIS Mask                */
+#define SSP0_RIS_RXRIS_Pos                                    2                                                         /*!< SSP0 RIS: RXRIS Position            */
+#define SSP0_RIS_RXRIS_Msk                                    (0x01UL << SSP0_RIS_RXRIS_Pos)                            /*!< SSP0 RIS: RXRIS Mask                */
+#define SSP0_RIS_TXRIS_Pos                                    3                                                         /*!< SSP0 RIS: TXRIS Position            */
+#define SSP0_RIS_TXRIS_Msk                                    (0x01UL << SSP0_RIS_TXRIS_Pos)                            /*!< SSP0 RIS: TXRIS Mask                */
+
+// ----------------------------------------  SSP0_MIS  --------------------------------------------
+#define SSP0_MIS_RORMIS_Pos                                   0                                                         /*!< SSP0 MIS: RORMIS Position           */
+#define SSP0_MIS_RORMIS_Msk                                   (0x01UL << SSP0_MIS_RORMIS_Pos)                           /*!< SSP0 MIS: RORMIS Mask               */
+#define SSP0_MIS_RTMIS_Pos                                    1                                                         /*!< SSP0 MIS: RTMIS Position            */
+#define SSP0_MIS_RTMIS_Msk                                    (0x01UL << SSP0_MIS_RTMIS_Pos)                            /*!< SSP0 MIS: RTMIS Mask                */
+#define SSP0_MIS_RXMIS_Pos                                    2                                                         /*!< SSP0 MIS: RXMIS Position            */
+#define SSP0_MIS_RXMIS_Msk                                    (0x01UL << SSP0_MIS_RXMIS_Pos)                            /*!< SSP0 MIS: RXMIS Mask                */
+#define SSP0_MIS_TXMIS_Pos                                    3                                                         /*!< SSP0 MIS: TXMIS Position            */
+#define SSP0_MIS_TXMIS_Msk                                    (0x01UL << SSP0_MIS_TXMIS_Pos)                            /*!< SSP0 MIS: TXMIS Mask                */
+
+// ----------------------------------------  SSP0_ICR  --------------------------------------------
+#define SSP0_ICR_RORIC_Pos                                    0                                                         /*!< SSP0 ICR: RORIC Position            */
+#define SSP0_ICR_RORIC_Msk                                    (0x01UL << SSP0_ICR_RORIC_Pos)                            /*!< SSP0 ICR: RORIC Mask                */
+#define SSP0_ICR_RTIC_Pos                                     1                                                         /*!< SSP0 ICR: RTIC Position             */
+#define SSP0_ICR_RTIC_Msk                                     (0x01UL << SSP0_ICR_RTIC_Pos)                             /*!< SSP0 ICR: RTIC Mask                 */
+
+// ---------------------------------------  SSP0_DMACR  -------------------------------------------
+#define SSP0_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP0 DMACR: RXDMAE Position         */
+#define SSP0_DMACR_RXDMAE_Msk                                 (0x01UL << SSP0_DMACR_RXDMAE_Pos)                         /*!< SSP0 DMACR: RXDMAE Mask             */
+#define SSP0_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP0 DMACR: TXDMAE Position         */
+#define SSP0_DMACR_TXDMAE_Msk                                 (0x01UL << SSP0_DMACR_TXDMAE_Pos)                         /*!< SSP0 DMACR: TXDMAE Mask             */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SSP1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  SSP1_CR0  --------------------------------------------
+#define SSP1_CR0_DSS_Pos                                      0                                                         /*!< SSP1 CR0: DSS Position              */
+#define SSP1_CR0_DSS_Msk                                      (0x0fUL << SSP1_CR0_DSS_Pos)                              /*!< SSP1 CR0: DSS Mask                  */
+#define SSP1_CR0_FRF_Pos                                      4                                                         /*!< SSP1 CR0: FRF Position              */
+#define SSP1_CR0_FRF_Msk                                      (0x03UL << SSP1_CR0_FRF_Pos)                              /*!< SSP1 CR0: FRF Mask                  */
+#define SSP1_CR0_CPOL_Pos                                     6                                                         /*!< SSP1 CR0: CPOL Position             */
+#define SSP1_CR0_CPOL_Msk                                     (0x01UL << SSP1_CR0_CPOL_Pos)                             /*!< SSP1 CR0: CPOL Mask                 */
+#define SSP1_CR0_CPHA_Pos                                     7                                                         /*!< SSP1 CR0: CPHA Position             */
+#define SSP1_CR0_CPHA_Msk                                     (0x01UL << SSP1_CR0_CPHA_Pos)                             /*!< SSP1 CR0: CPHA Mask                 */
+#define SSP1_CR0_SCR_Pos                                      8                                                         /*!< SSP1 CR0: SCR Position              */
+#define SSP1_CR0_SCR_Msk                                      (0x000000ffUL << SSP1_CR0_SCR_Pos)                        /*!< SSP1 CR0: SCR Mask                  */
+
+// ----------------------------------------  SSP1_CR1  --------------------------------------------
+#define SSP1_CR1_LBM_Pos                                      0                                                         /*!< SSP1 CR1: LBM Position              */
+#define SSP1_CR1_LBM_Msk                                      (0x01UL << SSP1_CR1_LBM_Pos)                              /*!< SSP1 CR1: LBM Mask                  */
+#define SSP1_CR1_SSE_Pos                                      1                                                         /*!< SSP1 CR1: SSE Position              */
+#define SSP1_CR1_SSE_Msk                                      (0x01UL << SSP1_CR1_SSE_Pos)                              /*!< SSP1 CR1: SSE Mask                  */
+#define SSP1_CR1_MS_Pos                                       2                                                         /*!< SSP1 CR1: MS Position               */
+#define SSP1_CR1_MS_Msk                                       (0x01UL << SSP1_CR1_MS_Pos)                               /*!< SSP1 CR1: MS Mask                   */
+#define SSP1_CR1_SOD_Pos                                      3                                                         /*!< SSP1 CR1: SOD Position              */
+#define SSP1_CR1_SOD_Msk                                      (0x01UL << SSP1_CR1_SOD_Pos)                              /*!< SSP1 CR1: SOD Mask                  */
+
+// -----------------------------------------  SSP1_DR  --------------------------------------------
+#define SSP1_DR_DATA_Pos                                      0                                                         /*!< SSP1 DR: DATA Position              */
+#define SSP1_DR_DATA_Msk                                      (0x0000ffffUL << SSP1_DR_DATA_Pos)                        /*!< SSP1 DR: DATA Mask                  */
+
+// -----------------------------------------  SSP1_SR  --------------------------------------------
+#define SSP1_SR_TFE_Pos                                       0                                                         /*!< SSP1 SR: TFE Position               */
+#define SSP1_SR_TFE_Msk                                       (0x01UL << SSP1_SR_TFE_Pos)                               /*!< SSP1 SR: TFE Mask                   */
+#define SSP1_SR_TNF_Pos                                       1                                                         /*!< SSP1 SR: TNF Position               */
+#define SSP1_SR_TNF_Msk                                       (0x01UL << SSP1_SR_TNF_Pos)                               /*!< SSP1 SR: TNF Mask                   */
+#define SSP1_SR_RNE_Pos                                       2                                                         /*!< SSP1 SR: RNE Position               */
+#define SSP1_SR_RNE_Msk                                       (0x01UL << SSP1_SR_RNE_Pos)                               /*!< SSP1 SR: RNE Mask                   */
+#define SSP1_SR_RFF_Pos                                       3                                                         /*!< SSP1 SR: RFF Position               */
+#define SSP1_SR_RFF_Msk                                       (0x01UL << SSP1_SR_RFF_Pos)                               /*!< SSP1 SR: RFF Mask                   */
+#define SSP1_SR_BSY_Pos                                       4                                                         /*!< SSP1 SR: BSY Position               */
+#define SSP1_SR_BSY_Msk                                       (0x01UL << SSP1_SR_BSY_Pos)                               /*!< SSP1 SR: BSY Mask                   */
+
+// ----------------------------------------  SSP1_CPSR  -------------------------------------------
+#define SSP1_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP1 CPSR: CPSDVSR Position         */
+#define SSP1_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos)                   /*!< SSP1 CPSR: CPSDVSR Mask             */
+
+// ----------------------------------------  SSP1_IMSC  -------------------------------------------
+#define SSP1_IMSC_RORIM_Pos                                   0                                                         /*!< SSP1 IMSC: RORIM Position           */
+#define SSP1_IMSC_RORIM_Msk                                   (0x01UL << SSP1_IMSC_RORIM_Pos)                           /*!< SSP1 IMSC: RORIM Mask               */
+#define SSP1_IMSC_RTIM_Pos                                    1                                                         /*!< SSP1 IMSC: RTIM Position            */
+#define SSP1_IMSC_RTIM_Msk                                    (0x01UL << SSP1_IMSC_RTIM_Pos)                            /*!< SSP1 IMSC: RTIM Mask                */
+#define SSP1_IMSC_RXIM_Pos                                    2                                                         /*!< SSP1 IMSC: RXIM Position            */
+#define SSP1_IMSC_RXIM_Msk                                    (0x01UL << SSP1_IMSC_RXIM_Pos)                            /*!< SSP1 IMSC: RXIM Mask                */
+#define SSP1_IMSC_TXIM_Pos                                    3                                                         /*!< SSP1 IMSC: TXIM Position            */
+#define SSP1_IMSC_TXIM_Msk                                    (0x01UL << SSP1_IMSC_TXIM_Pos)                            /*!< SSP1 IMSC: TXIM Mask                */
+
+// ----------------------------------------  SSP1_RIS  --------------------------------------------
+#define SSP1_RIS_RORRIS_Pos                                   0                                                         /*!< SSP1 RIS: RORRIS Position           */
+#define SSP1_RIS_RORRIS_Msk                                   (0x01UL << SSP1_RIS_RORRIS_Pos)                           /*!< SSP1 RIS: RORRIS Mask               */
+#define SSP1_RIS_RTRIS_Pos                                    1                                                         /*!< SSP1 RIS: RTRIS Position            */
+#define SSP1_RIS_RTRIS_Msk                                    (0x01UL << SSP1_RIS_RTRIS_Pos)                            /*!< SSP1 RIS: RTRIS Mask                */
+#define SSP1_RIS_RXRIS_Pos                                    2                                                         /*!< SSP1 RIS: RXRIS Position            */
+#define SSP1_RIS_RXRIS_Msk                                    (0x01UL << SSP1_RIS_RXRIS_Pos)                            /*!< SSP1 RIS: RXRIS Mask                */
+#define SSP1_RIS_TXRIS_Pos                                    3                                                         /*!< SSP1 RIS: TXRIS Position            */
+#define SSP1_RIS_TXRIS_Msk                                    (0x01UL << SSP1_RIS_TXRIS_Pos)                            /*!< SSP1 RIS: TXRIS Mask                */
+
+// ----------------------------------------  SSP1_MIS  --------------------------------------------
+#define SSP1_MIS_RORMIS_Pos                                   0                                                         /*!< SSP1 MIS: RORMIS Position           */
+#define SSP1_MIS_RORMIS_Msk                                   (0x01UL << SSP1_MIS_RORMIS_Pos)                           /*!< SSP1 MIS: RORMIS Mask               */
+#define SSP1_MIS_RTMIS_Pos                                    1                                                         /*!< SSP1 MIS: RTMIS Position            */
+#define SSP1_MIS_RTMIS_Msk                                    (0x01UL << SSP1_MIS_RTMIS_Pos)                            /*!< SSP1 MIS: RTMIS Mask                */
+#define SSP1_MIS_RXMIS_Pos                                    2                                                         /*!< SSP1 MIS: RXMIS Position            */
+#define SSP1_MIS_RXMIS_Msk                                    (0x01UL << SSP1_MIS_RXMIS_Pos)                            /*!< SSP1 MIS: RXMIS Mask                */
+#define SSP1_MIS_TXMIS_Pos                                    3                                                         /*!< SSP1 MIS: TXMIS Position            */
+#define SSP1_MIS_TXMIS_Msk                                    (0x01UL << SSP1_MIS_TXMIS_Pos)                            /*!< SSP1 MIS: TXMIS Mask                */
+
+// ----------------------------------------  SSP1_ICR  --------------------------------------------
+#define SSP1_ICR_RORIC_Pos                                    0                                                         /*!< SSP1 ICR: RORIC Position            */
+#define SSP1_ICR_RORIC_Msk                                    (0x01UL << SSP1_ICR_RORIC_Pos)                            /*!< SSP1 ICR: RORIC Mask                */
+#define SSP1_ICR_RTIC_Pos                                     1                                                         /*!< SSP1 ICR: RTIC Position             */
+#define SSP1_ICR_RTIC_Msk                                     (0x01UL << SSP1_ICR_RTIC_Pos)                             /*!< SSP1 ICR: RTIC Mask                 */
+
+// ---------------------------------------  SSP1_DMACR  -------------------------------------------
+#define SSP1_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP1 DMACR: RXDMAE Position         */
+#define SSP1_DMACR_RXDMAE_Msk                                 (0x01UL << SSP1_DMACR_RXDMAE_Pos)                         /*!< SSP1 DMACR: RXDMAE Mask             */
+#define SSP1_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP1 DMACR: TXDMAE Position         */
+#define SSP1_DMACR_TXDMAE_Msk                                 (0x01UL << SSP1_DMACR_TXDMAE_Pos)                         /*!< SSP1 DMACR: TXDMAE Mask             */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER0 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER0_IR  -------------------------------------------
+#define TIMER0_IR_MR0INT_Pos                                  0                                                         /*!< TIMER0 IR: MR0INT Position          */
+#define TIMER0_IR_MR0INT_Msk                                  (0x01UL << TIMER0_IR_MR0INT_Pos)                          /*!< TIMER0 IR: MR0INT Mask              */
+#define TIMER0_IR_MR1INT_Pos                                  1                                                         /*!< TIMER0 IR: MR1INT Position          */
+#define TIMER0_IR_MR1INT_Msk                                  (0x01UL << TIMER0_IR_MR1INT_Pos)                          /*!< TIMER0 IR: MR1INT Mask              */
+#define TIMER0_IR_MR2INT_Pos                                  2                                                         /*!< TIMER0 IR: MR2INT Position          */
+#define TIMER0_IR_MR2INT_Msk                                  (0x01UL << TIMER0_IR_MR2INT_Pos)                          /*!< TIMER0 IR: MR2INT Mask              */
+#define TIMER0_IR_MR3INT_Pos                                  3                                                         /*!< TIMER0 IR: MR3INT Position          */
+#define TIMER0_IR_MR3INT_Msk                                  (0x01UL << TIMER0_IR_MR3INT_Pos)                          /*!< TIMER0 IR: MR3INT Mask              */
+#define TIMER0_IR_CR0INT_Pos                                  4                                                         /*!< TIMER0 IR: CR0INT Position          */
+#define TIMER0_IR_CR0INT_Msk                                  (0x01UL << TIMER0_IR_CR0INT_Pos)                          /*!< TIMER0 IR: CR0INT Mask              */
+#define TIMER0_IR_CR1INT_Pos                                  5                                                         /*!< TIMER0 IR: CR1INT Position          */
+#define TIMER0_IR_CR1INT_Msk                                  (0x01UL << TIMER0_IR_CR1INT_Pos)                          /*!< TIMER0 IR: CR1INT Mask              */
+#define TIMER0_IR_CR2INT_Pos                                  6                                                         /*!< TIMER0 IR: CR2INT Position          */
+#define TIMER0_IR_CR2INT_Msk                                  (0x01UL << TIMER0_IR_CR2INT_Pos)                          /*!< TIMER0 IR: CR2INT Mask              */
+#define TIMER0_IR_CR3INT_Pos                                  7                                                         /*!< TIMER0 IR: CR3INT Position          */
+#define TIMER0_IR_CR3INT_Msk                                  (0x01UL << TIMER0_IR_CR3INT_Pos)                          /*!< TIMER0 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER0_TCR  -------------------------------------------
+#define TIMER0_TCR_CEN_Pos                                    0                                                         /*!< TIMER0 TCR: CEN Position            */
+#define TIMER0_TCR_CEN_Msk                                    (0x01UL << TIMER0_TCR_CEN_Pos)                            /*!< TIMER0 TCR: CEN Mask                */
+#define TIMER0_TCR_CRST_Pos                                   1                                                         /*!< TIMER0 TCR: CRST Position           */
+#define TIMER0_TCR_CRST_Msk                                   (0x01UL << TIMER0_TCR_CRST_Pos)                           /*!< TIMER0 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER0_TC  -------------------------------------------
+#define TIMER0_TC_TC_Pos                                      0                                                         /*!< TIMER0 TC: TC Position              */
+#define TIMER0_TC_TC_Msk                                      (0xffffffffUL << TIMER0_TC_TC_Pos)                        /*!< TIMER0 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER0_PR  -------------------------------------------
+#define TIMER0_PR_PM_Pos                                      0                                                         /*!< TIMER0 PR: PM Position              */
+#define TIMER0_PR_PM_Msk                                      (0xffffffffUL << TIMER0_PR_PM_Pos)                        /*!< TIMER0 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER0_PC  -------------------------------------------
+#define TIMER0_PC_PC_Pos                                      0                                                         /*!< TIMER0 PC: PC Position              */
+#define TIMER0_PC_PC_Msk                                      (0xffffffffUL << TIMER0_PC_PC_Pos)                        /*!< TIMER0 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER0_MCR  -------------------------------------------
+#define TIMER0_MCR_MR0I_Pos                                   0                                                         /*!< TIMER0 MCR: MR0I Position           */
+#define TIMER0_MCR_MR0I_Msk                                   (0x01UL << TIMER0_MCR_MR0I_Pos)                           /*!< TIMER0 MCR: MR0I Mask               */
+#define TIMER0_MCR_MR0R_Pos                                   1                                                         /*!< TIMER0 MCR: MR0R Position           */
+#define TIMER0_MCR_MR0R_Msk                                   (0x01UL << TIMER0_MCR_MR0R_Pos)                           /*!< TIMER0 MCR: MR0R Mask               */
+#define TIMER0_MCR_MR0S_Pos                                   2                                                         /*!< TIMER0 MCR: MR0S Position           */
+#define TIMER0_MCR_MR0S_Msk                                   (0x01UL << TIMER0_MCR_MR0S_Pos)                           /*!< TIMER0 MCR: MR0S Mask               */
+#define TIMER0_MCR_MR1I_Pos                                   3                                                         /*!< TIMER0 MCR: MR1I Position           */
+#define TIMER0_MCR_MR1I_Msk                                   (0x01UL << TIMER0_MCR_MR1I_Pos)                           /*!< TIMER0 MCR: MR1I Mask               */
+#define TIMER0_MCR_MR1R_Pos                                   4                                                         /*!< TIMER0 MCR: MR1R Position           */
+#define TIMER0_MCR_MR1R_Msk                                   (0x01UL << TIMER0_MCR_MR1R_Pos)                           /*!< TIMER0 MCR: MR1R Mask               */
+#define TIMER0_MCR_MR1S_Pos                                   5                                                         /*!< TIMER0 MCR: MR1S Position           */
+#define TIMER0_MCR_MR1S_Msk                                   (0x01UL << TIMER0_MCR_MR1S_Pos)                           /*!< TIMER0 MCR: MR1S Mask               */
+#define TIMER0_MCR_MR2I_Pos                                   6                                                         /*!< TIMER0 MCR: MR2I Position           */
+#define TIMER0_MCR_MR2I_Msk                                   (0x01UL << TIMER0_MCR_MR2I_Pos)                           /*!< TIMER0 MCR: MR2I Mask               */
+#define TIMER0_MCR_MR2R_Pos                                   7                                                         /*!< TIMER0 MCR: MR2R Position           */
+#define TIMER0_MCR_MR2R_Msk                                   (0x01UL << TIMER0_MCR_MR2R_Pos)                           /*!< TIMER0 MCR: MR2R Mask               */
+#define TIMER0_MCR_MR2S_Pos                                   8                                                         /*!< TIMER0 MCR: MR2S Position           */
+#define TIMER0_MCR_MR2S_Msk                                   (0x01UL << TIMER0_MCR_MR2S_Pos)                           /*!< TIMER0 MCR: MR2S Mask               */
+#define TIMER0_MCR_MR3I_Pos                                   9                                                         /*!< TIMER0 MCR: MR3I Position           */
+#define TIMER0_MCR_MR3I_Msk                                   (0x01UL << TIMER0_MCR_MR3I_Pos)                           /*!< TIMER0 MCR: MR3I Mask               */
+#define TIMER0_MCR_MR3R_Pos                                   10                                                        /*!< TIMER0 MCR: MR3R Position           */
+#define TIMER0_MCR_MR3R_Msk                                   (0x01UL << TIMER0_MCR_MR3R_Pos)                           /*!< TIMER0 MCR: MR3R Mask               */
+#define TIMER0_MCR_MR3S_Pos                                   11                                                        /*!< TIMER0 MCR: MR3S Position           */
+#define TIMER0_MCR_MR3S_Msk                                   (0x01UL << TIMER0_MCR_MR3S_Pos)                           /*!< TIMER0 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER0_MR0  -------------------------------------------
+#define TIMER0_MR0_MATCH_Pos                                  0                                                         /*!< TIMER0 MR0: MATCH Position          */
+#define TIMER0_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR0_MATCH_Pos)                    /*!< TIMER0 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_MR1  -------------------------------------------
+#define TIMER0_MR1_MATCH_Pos                                  0                                                         /*!< TIMER0 MR1: MATCH Position          */
+#define TIMER0_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR1_MATCH_Pos)                    /*!< TIMER0 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_MR2  -------------------------------------------
+#define TIMER0_MR2_MATCH_Pos                                  0                                                         /*!< TIMER0 MR2: MATCH Position          */
+#define TIMER0_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR2_MATCH_Pos)                    /*!< TIMER0 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_MR3  -------------------------------------------
+#define TIMER0_MR3_MATCH_Pos                                  0                                                         /*!< TIMER0 MR3: MATCH Position          */
+#define TIMER0_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR3_MATCH_Pos)                    /*!< TIMER0 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER0_CCR  -------------------------------------------
+#define TIMER0_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER0 CCR: CAP0RE Position         */
+#define TIMER0_CCR_CAP0RE_Msk                                 (0x01UL << TIMER0_CCR_CAP0RE_Pos)                         /*!< TIMER0 CCR: CAP0RE Mask             */
+#define TIMER0_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER0 CCR: CAP0FE Position         */
+#define TIMER0_CCR_CAP0FE_Msk                                 (0x01UL << TIMER0_CCR_CAP0FE_Pos)                         /*!< TIMER0 CCR: CAP0FE Mask             */
+#define TIMER0_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER0 CCR: CAP0I Position          */
+#define TIMER0_CCR_CAP0I_Msk                                  (0x01UL << TIMER0_CCR_CAP0I_Pos)                          /*!< TIMER0 CCR: CAP0I Mask              */
+#define TIMER0_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER0 CCR: CAP1RE Position         */
+#define TIMER0_CCR_CAP1RE_Msk                                 (0x01UL << TIMER0_CCR_CAP1RE_Pos)                         /*!< TIMER0 CCR: CAP1RE Mask             */
+#define TIMER0_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER0 CCR: CAP1FE Position         */
+#define TIMER0_CCR_CAP1FE_Msk                                 (0x01UL << TIMER0_CCR_CAP1FE_Pos)                         /*!< TIMER0 CCR: CAP1FE Mask             */
+#define TIMER0_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER0 CCR: CAP1I Position          */
+#define TIMER0_CCR_CAP1I_Msk                                  (0x01UL << TIMER0_CCR_CAP1I_Pos)                          /*!< TIMER0 CCR: CAP1I Mask              */
+#define TIMER0_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER0 CCR: CAP2RE Position         */
+#define TIMER0_CCR_CAP2RE_Msk                                 (0x01UL << TIMER0_CCR_CAP2RE_Pos)                         /*!< TIMER0 CCR: CAP2RE Mask             */
+#define TIMER0_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER0 CCR: CAP2FE Position         */
+#define TIMER0_CCR_CAP2FE_Msk                                 (0x01UL << TIMER0_CCR_CAP2FE_Pos)                         /*!< TIMER0 CCR: CAP2FE Mask             */
+#define TIMER0_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER0 CCR: CAP2I Position          */
+#define TIMER0_CCR_CAP2I_Msk                                  (0x01UL << TIMER0_CCR_CAP2I_Pos)                          /*!< TIMER0 CCR: CAP2I Mask              */
+#define TIMER0_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER0 CCR: CAP3RE Position         */
+#define TIMER0_CCR_CAP3RE_Msk                                 (0x01UL << TIMER0_CCR_CAP3RE_Pos)                         /*!< TIMER0 CCR: CAP3RE Mask             */
+#define TIMER0_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER0 CCR: CAP3FE Position         */
+#define TIMER0_CCR_CAP3FE_Msk                                 (0x01UL << TIMER0_CCR_CAP3FE_Pos)                         /*!< TIMER0 CCR: CAP3FE Mask             */
+#define TIMER0_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER0 CCR: CAP3I Position          */
+#define TIMER0_CCR_CAP3I_Msk                                  (0x01UL << TIMER0_CCR_CAP3I_Pos)                          /*!< TIMER0 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER0_CR0  -------------------------------------------
+#define TIMER0_CR0_CAP_Pos                                    0                                                         /*!< TIMER0 CR0: CAP Position            */
+#define TIMER0_CR0_CAP_Msk                                    (0xffffffffUL << TIMER0_CR0_CAP_Pos)                      /*!< TIMER0 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER0_CR1  -------------------------------------------
+#define TIMER0_CR1_CAP_Pos                                    0                                                         /*!< TIMER0 CR1: CAP Position            */
+#define TIMER0_CR1_CAP_Msk                                    (0xffffffffUL << TIMER0_CR1_CAP_Pos)                      /*!< TIMER0 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER0_CR2  -------------------------------------------
+#define TIMER0_CR2_CAP_Pos                                    0                                                         /*!< TIMER0 CR2: CAP Position            */
+#define TIMER0_CR2_CAP_Msk                                    (0xffffffffUL << TIMER0_CR2_CAP_Pos)                      /*!< TIMER0 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER0_CR3  -------------------------------------------
+#define TIMER0_CR3_CAP_Pos                                    0                                                         /*!< TIMER0 CR3: CAP Position            */
+#define TIMER0_CR3_CAP_Msk                                    (0xffffffffUL << TIMER0_CR3_CAP_Pos)                      /*!< TIMER0 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER0_EMR  -------------------------------------------
+#define TIMER0_EMR_EM0_Pos                                    0                                                         /*!< TIMER0 EMR: EM0 Position            */
+#define TIMER0_EMR_EM0_Msk                                    (0x01UL << TIMER0_EMR_EM0_Pos)                            /*!< TIMER0 EMR: EM0 Mask                */
+#define TIMER0_EMR_EM1_Pos                                    1                                                         /*!< TIMER0 EMR: EM1 Position            */
+#define TIMER0_EMR_EM1_Msk                                    (0x01UL << TIMER0_EMR_EM1_Pos)                            /*!< TIMER0 EMR: EM1 Mask                */
+#define TIMER0_EMR_EM2_Pos                                    2                                                         /*!< TIMER0 EMR: EM2 Position            */
+#define TIMER0_EMR_EM2_Msk                                    (0x01UL << TIMER0_EMR_EM2_Pos)                            /*!< TIMER0 EMR: EM2 Mask                */
+#define TIMER0_EMR_EM3_Pos                                    3                                                         /*!< TIMER0 EMR: EM3 Position            */
+#define TIMER0_EMR_EM3_Msk                                    (0x01UL << TIMER0_EMR_EM3_Pos)                            /*!< TIMER0 EMR: EM3 Mask                */
+#define TIMER0_EMR_EMC0_Pos                                   4                                                         /*!< TIMER0 EMR: EMC0 Position           */
+#define TIMER0_EMR_EMC0_Msk                                   (0x03UL << TIMER0_EMR_EMC0_Pos)                           /*!< TIMER0 EMR: EMC0 Mask               */
+#define TIMER0_EMR_EMC1_Pos                                   6                                                         /*!< TIMER0 EMR: EMC1 Position           */
+#define TIMER0_EMR_EMC1_Msk                                   (0x03UL << TIMER0_EMR_EMC1_Pos)                           /*!< TIMER0 EMR: EMC1 Mask               */
+#define TIMER0_EMR_EMC2_Pos                                   8                                                         /*!< TIMER0 EMR: EMC2 Position           */
+#define TIMER0_EMR_EMC2_Msk                                   (0x03UL << TIMER0_EMR_EMC2_Pos)                           /*!< TIMER0 EMR: EMC2 Mask               */
+#define TIMER0_EMR_EMC3_Pos                                   10                                                        /*!< TIMER0 EMR: EMC3 Position           */
+#define TIMER0_EMR_EMC3_Msk                                   (0x03UL << TIMER0_EMR_EMC3_Pos)                           /*!< TIMER0 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER0_CTCR  ------------------------------------------
+#define TIMER0_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER0 CTCR: CTMODE Position        */
+#define TIMER0_CTCR_CTMODE_Msk                                (0x03UL << TIMER0_CTCR_CTMODE_Pos)                        /*!< TIMER0 CTCR: CTMODE Mask            */
+#define TIMER0_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER0 CTCR: CINSEL Position        */
+#define TIMER0_CTCR_CINSEL_Msk                                (0x03UL << TIMER0_CTCR_CINSEL_Pos)                        /*!< TIMER0 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER1 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER1_IR  -------------------------------------------
+#define TIMER1_IR_MR0INT_Pos                                  0                                                         /*!< TIMER1 IR: MR0INT Position          */
+#define TIMER1_IR_MR0INT_Msk                                  (0x01UL << TIMER1_IR_MR0INT_Pos)                          /*!< TIMER1 IR: MR0INT Mask              */
+#define TIMER1_IR_MR1INT_Pos                                  1                                                         /*!< TIMER1 IR: MR1INT Position          */
+#define TIMER1_IR_MR1INT_Msk                                  (0x01UL << TIMER1_IR_MR1INT_Pos)                          /*!< TIMER1 IR: MR1INT Mask              */
+#define TIMER1_IR_MR2INT_Pos                                  2                                                         /*!< TIMER1 IR: MR2INT Position          */
+#define TIMER1_IR_MR2INT_Msk                                  (0x01UL << TIMER1_IR_MR2INT_Pos)                          /*!< TIMER1 IR: MR2INT Mask              */
+#define TIMER1_IR_MR3INT_Pos                                  3                                                         /*!< TIMER1 IR: MR3INT Position          */
+#define TIMER1_IR_MR3INT_Msk                                  (0x01UL << TIMER1_IR_MR3INT_Pos)                          /*!< TIMER1 IR: MR3INT Mask              */
+#define TIMER1_IR_CR0INT_Pos                                  4                                                         /*!< TIMER1 IR: CR0INT Position          */
+#define TIMER1_IR_CR0INT_Msk                                  (0x01UL << TIMER1_IR_CR0INT_Pos)                          /*!< TIMER1 IR: CR0INT Mask              */
+#define TIMER1_IR_CR1INT_Pos                                  5                                                         /*!< TIMER1 IR: CR1INT Position          */
+#define TIMER1_IR_CR1INT_Msk                                  (0x01UL << TIMER1_IR_CR1INT_Pos)                          /*!< TIMER1 IR: CR1INT Mask              */
+#define TIMER1_IR_CR2INT_Pos                                  6                                                         /*!< TIMER1 IR: CR2INT Position          */
+#define TIMER1_IR_CR2INT_Msk                                  (0x01UL << TIMER1_IR_CR2INT_Pos)                          /*!< TIMER1 IR: CR2INT Mask              */
+#define TIMER1_IR_CR3INT_Pos                                  7                                                         /*!< TIMER1 IR: CR3INT Position          */
+#define TIMER1_IR_CR3INT_Msk                                  (0x01UL << TIMER1_IR_CR3INT_Pos)                          /*!< TIMER1 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER1_TCR  -------------------------------------------
+#define TIMER1_TCR_CEN_Pos                                    0                                                         /*!< TIMER1 TCR: CEN Position            */
+#define TIMER1_TCR_CEN_Msk                                    (0x01UL << TIMER1_TCR_CEN_Pos)                            /*!< TIMER1 TCR: CEN Mask                */
+#define TIMER1_TCR_CRST_Pos                                   1                                                         /*!< TIMER1 TCR: CRST Position           */
+#define TIMER1_TCR_CRST_Msk                                   (0x01UL << TIMER1_TCR_CRST_Pos)                           /*!< TIMER1 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER1_TC  -------------------------------------------
+#define TIMER1_TC_TC_Pos                                      0                                                         /*!< TIMER1 TC: TC Position              */
+#define TIMER1_TC_TC_Msk                                      (0xffffffffUL << TIMER1_TC_TC_Pos)                        /*!< TIMER1 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER1_PR  -------------------------------------------
+#define TIMER1_PR_PM_Pos                                      0                                                         /*!< TIMER1 PR: PM Position              */
+#define TIMER1_PR_PM_Msk                                      (0xffffffffUL << TIMER1_PR_PM_Pos)                        /*!< TIMER1 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER1_PC  -------------------------------------------
+#define TIMER1_PC_PC_Pos                                      0                                                         /*!< TIMER1 PC: PC Position              */
+#define TIMER1_PC_PC_Msk                                      (0xffffffffUL << TIMER1_PC_PC_Pos)                        /*!< TIMER1 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER1_MCR  -------------------------------------------
+#define TIMER1_MCR_MR0I_Pos                                   0                                                         /*!< TIMER1 MCR: MR0I Position           */
+#define TIMER1_MCR_MR0I_Msk                                   (0x01UL << TIMER1_MCR_MR0I_Pos)                           /*!< TIMER1 MCR: MR0I Mask               */
+#define TIMER1_MCR_MR0R_Pos                                   1                                                         /*!< TIMER1 MCR: MR0R Position           */
+#define TIMER1_MCR_MR0R_Msk                                   (0x01UL << TIMER1_MCR_MR0R_Pos)                           /*!< TIMER1 MCR: MR0R Mask               */
+#define TIMER1_MCR_MR0S_Pos                                   2                                                         /*!< TIMER1 MCR: MR0S Position           */
+#define TIMER1_MCR_MR0S_Msk                                   (0x01UL << TIMER1_MCR_MR0S_Pos)                           /*!< TIMER1 MCR: MR0S Mask               */
+#define TIMER1_MCR_MR1I_Pos                                   3                                                         /*!< TIMER1 MCR: MR1I Position           */
+#define TIMER1_MCR_MR1I_Msk                                   (0x01UL << TIMER1_MCR_MR1I_Pos)                           /*!< TIMER1 MCR: MR1I Mask               */
+#define TIMER1_MCR_MR1R_Pos                                   4                                                         /*!< TIMER1 MCR: MR1R Position           */
+#define TIMER1_MCR_MR1R_Msk                                   (0x01UL << TIMER1_MCR_MR1R_Pos)                           /*!< TIMER1 MCR: MR1R Mask               */
+#define TIMER1_MCR_MR1S_Pos                                   5                                                         /*!< TIMER1 MCR: MR1S Position           */
+#define TIMER1_MCR_MR1S_Msk                                   (0x01UL << TIMER1_MCR_MR1S_Pos)                           /*!< TIMER1 MCR: MR1S Mask               */
+#define TIMER1_MCR_MR2I_Pos                                   6                                                         /*!< TIMER1 MCR: MR2I Position           */
+#define TIMER1_MCR_MR2I_Msk                                   (0x01UL << TIMER1_MCR_MR2I_Pos)                           /*!< TIMER1 MCR: MR2I Mask               */
+#define TIMER1_MCR_MR2R_Pos                                   7                                                         /*!< TIMER1 MCR: MR2R Position           */
+#define TIMER1_MCR_MR2R_Msk                                   (0x01UL << TIMER1_MCR_MR2R_Pos)                           /*!< TIMER1 MCR: MR2R Mask               */
+#define TIMER1_MCR_MR2S_Pos                                   8                                                         /*!< TIMER1 MCR: MR2S Position           */
+#define TIMER1_MCR_MR2S_Msk                                   (0x01UL << TIMER1_MCR_MR2S_Pos)                           /*!< TIMER1 MCR: MR2S Mask               */
+#define TIMER1_MCR_MR3I_Pos                                   9                                                         /*!< TIMER1 MCR: MR3I Position           */
+#define TIMER1_MCR_MR3I_Msk                                   (0x01UL << TIMER1_MCR_MR3I_Pos)                           /*!< TIMER1 MCR: MR3I Mask               */
+#define TIMER1_MCR_MR3R_Pos                                   10                                                        /*!< TIMER1 MCR: MR3R Position           */
+#define TIMER1_MCR_MR3R_Msk                                   (0x01UL << TIMER1_MCR_MR3R_Pos)                           /*!< TIMER1 MCR: MR3R Mask               */
+#define TIMER1_MCR_MR3S_Pos                                   11                                                        /*!< TIMER1 MCR: MR3S Position           */
+#define TIMER1_MCR_MR3S_Msk                                   (0x01UL << TIMER1_MCR_MR3S_Pos)                           /*!< TIMER1 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER1_MR0  -------------------------------------------
+#define TIMER1_MR0_MATCH_Pos                                  0                                                         /*!< TIMER1 MR0: MATCH Position          */
+#define TIMER1_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR0_MATCH_Pos)                    /*!< TIMER1 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_MR1  -------------------------------------------
+#define TIMER1_MR1_MATCH_Pos                                  0                                                         /*!< TIMER1 MR1: MATCH Position          */
+#define TIMER1_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR1_MATCH_Pos)                    /*!< TIMER1 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_MR2  -------------------------------------------
+#define TIMER1_MR2_MATCH_Pos                                  0                                                         /*!< TIMER1 MR2: MATCH Position          */
+#define TIMER1_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR2_MATCH_Pos)                    /*!< TIMER1 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_MR3  -------------------------------------------
+#define TIMER1_MR3_MATCH_Pos                                  0                                                         /*!< TIMER1 MR3: MATCH Position          */
+#define TIMER1_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR3_MATCH_Pos)                    /*!< TIMER1 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER1_CCR  -------------------------------------------
+#define TIMER1_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER1 CCR: CAP0RE Position         */
+#define TIMER1_CCR_CAP0RE_Msk                                 (0x01UL << TIMER1_CCR_CAP0RE_Pos)                         /*!< TIMER1 CCR: CAP0RE Mask             */
+#define TIMER1_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER1 CCR: CAP0FE Position         */
+#define TIMER1_CCR_CAP0FE_Msk                                 (0x01UL << TIMER1_CCR_CAP0FE_Pos)                         /*!< TIMER1 CCR: CAP0FE Mask             */
+#define TIMER1_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER1 CCR: CAP0I Position          */
+#define TIMER1_CCR_CAP0I_Msk                                  (0x01UL << TIMER1_CCR_CAP0I_Pos)                          /*!< TIMER1 CCR: CAP0I Mask              */
+#define TIMER1_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER1 CCR: CAP1RE Position         */
+#define TIMER1_CCR_CAP1RE_Msk                                 (0x01UL << TIMER1_CCR_CAP1RE_Pos)                         /*!< TIMER1 CCR: CAP1RE Mask             */
+#define TIMER1_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER1 CCR: CAP1FE Position         */
+#define TIMER1_CCR_CAP1FE_Msk                                 (0x01UL << TIMER1_CCR_CAP1FE_Pos)                         /*!< TIMER1 CCR: CAP1FE Mask             */
+#define TIMER1_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER1 CCR: CAP1I Position          */
+#define TIMER1_CCR_CAP1I_Msk                                  (0x01UL << TIMER1_CCR_CAP1I_Pos)                          /*!< TIMER1 CCR: CAP1I Mask              */
+#define TIMER1_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER1 CCR: CAP2RE Position         */
+#define TIMER1_CCR_CAP2RE_Msk                                 (0x01UL << TIMER1_CCR_CAP2RE_Pos)                         /*!< TIMER1 CCR: CAP2RE Mask             */
+#define TIMER1_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER1 CCR: CAP2FE Position         */
+#define TIMER1_CCR_CAP2FE_Msk                                 (0x01UL << TIMER1_CCR_CAP2FE_Pos)                         /*!< TIMER1 CCR: CAP2FE Mask             */
+#define TIMER1_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER1 CCR: CAP2I Position          */
+#define TIMER1_CCR_CAP2I_Msk                                  (0x01UL << TIMER1_CCR_CAP2I_Pos)                          /*!< TIMER1 CCR: CAP2I Mask              */
+#define TIMER1_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER1 CCR: CAP3RE Position         */
+#define TIMER1_CCR_CAP3RE_Msk                                 (0x01UL << TIMER1_CCR_CAP3RE_Pos)                         /*!< TIMER1 CCR: CAP3RE Mask             */
+#define TIMER1_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER1 CCR: CAP3FE Position         */
+#define TIMER1_CCR_CAP3FE_Msk                                 (0x01UL << TIMER1_CCR_CAP3FE_Pos)                         /*!< TIMER1 CCR: CAP3FE Mask             */
+#define TIMER1_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER1 CCR: CAP3I Position          */
+#define TIMER1_CCR_CAP3I_Msk                                  (0x01UL << TIMER1_CCR_CAP3I_Pos)                          /*!< TIMER1 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER1_CR0  -------------------------------------------
+#define TIMER1_CR0_CAP_Pos                                    0                                                         /*!< TIMER1 CR0: CAP Position            */
+#define TIMER1_CR0_CAP_Msk                                    (0xffffffffUL << TIMER1_CR0_CAP_Pos)                      /*!< TIMER1 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER1_CR1  -------------------------------------------
+#define TIMER1_CR1_CAP_Pos                                    0                                                         /*!< TIMER1 CR1: CAP Position            */
+#define TIMER1_CR1_CAP_Msk                                    (0xffffffffUL << TIMER1_CR1_CAP_Pos)                      /*!< TIMER1 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER1_CR2  -------------------------------------------
+#define TIMER1_CR2_CAP_Pos                                    0                                                         /*!< TIMER1 CR2: CAP Position            */
+#define TIMER1_CR2_CAP_Msk                                    (0xffffffffUL << TIMER1_CR2_CAP_Pos)                      /*!< TIMER1 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER1_CR3  -------------------------------------------
+#define TIMER1_CR3_CAP_Pos                                    0                                                         /*!< TIMER1 CR3: CAP Position            */
+#define TIMER1_CR3_CAP_Msk                                    (0xffffffffUL << TIMER1_CR3_CAP_Pos)                      /*!< TIMER1 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER1_EMR  -------------------------------------------
+#define TIMER1_EMR_EM0_Pos                                    0                                                         /*!< TIMER1 EMR: EM0 Position            */
+#define TIMER1_EMR_EM0_Msk                                    (0x01UL << TIMER1_EMR_EM0_Pos)                            /*!< TIMER1 EMR: EM0 Mask                */
+#define TIMER1_EMR_EM1_Pos                                    1                                                         /*!< TIMER1 EMR: EM1 Position            */
+#define TIMER1_EMR_EM1_Msk                                    (0x01UL << TIMER1_EMR_EM1_Pos)                            /*!< TIMER1 EMR: EM1 Mask                */
+#define TIMER1_EMR_EM2_Pos                                    2                                                         /*!< TIMER1 EMR: EM2 Position            */
+#define TIMER1_EMR_EM2_Msk                                    (0x01UL << TIMER1_EMR_EM2_Pos)                            /*!< TIMER1 EMR: EM2 Mask                */
+#define TIMER1_EMR_EM3_Pos                                    3                                                         /*!< TIMER1 EMR: EM3 Position            */
+#define TIMER1_EMR_EM3_Msk                                    (0x01UL << TIMER1_EMR_EM3_Pos)                            /*!< TIMER1 EMR: EM3 Mask                */
+#define TIMER1_EMR_EMC0_Pos                                   4                                                         /*!< TIMER1 EMR: EMC0 Position           */
+#define TIMER1_EMR_EMC0_Msk                                   (0x03UL << TIMER1_EMR_EMC0_Pos)                           /*!< TIMER1 EMR: EMC0 Mask               */
+#define TIMER1_EMR_EMC1_Pos                                   6                                                         /*!< TIMER1 EMR: EMC1 Position           */
+#define TIMER1_EMR_EMC1_Msk                                   (0x03UL << TIMER1_EMR_EMC1_Pos)                           /*!< TIMER1 EMR: EMC1 Mask               */
+#define TIMER1_EMR_EMC2_Pos                                   8                                                         /*!< TIMER1 EMR: EMC2 Position           */
+#define TIMER1_EMR_EMC2_Msk                                   (0x03UL << TIMER1_EMR_EMC2_Pos)                           /*!< TIMER1 EMR: EMC2 Mask               */
+#define TIMER1_EMR_EMC3_Pos                                   10                                                        /*!< TIMER1 EMR: EMC3 Position           */
+#define TIMER1_EMR_EMC3_Msk                                   (0x03UL << TIMER1_EMR_EMC3_Pos)                           /*!< TIMER1 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER1_CTCR  ------------------------------------------
+#define TIMER1_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER1 CTCR: CTMODE Position        */
+#define TIMER1_CTCR_CTMODE_Msk                                (0x03UL << TIMER1_CTCR_CTMODE_Pos)                        /*!< TIMER1 CTCR: CTMODE Mask            */
+#define TIMER1_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER1 CTCR: CINSEL Position        */
+#define TIMER1_CTCR_CINSEL_Msk                                (0x03UL << TIMER1_CTCR_CINSEL_Pos)                        /*!< TIMER1 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER2 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER2_IR  -------------------------------------------
+#define TIMER2_IR_MR0INT_Pos                                  0                                                         /*!< TIMER2 IR: MR0INT Position          */
+#define TIMER2_IR_MR0INT_Msk                                  (0x01UL << TIMER2_IR_MR0INT_Pos)                          /*!< TIMER2 IR: MR0INT Mask              */
+#define TIMER2_IR_MR1INT_Pos                                  1                                                         /*!< TIMER2 IR: MR1INT Position          */
+#define TIMER2_IR_MR1INT_Msk                                  (0x01UL << TIMER2_IR_MR1INT_Pos)                          /*!< TIMER2 IR: MR1INT Mask              */
+#define TIMER2_IR_MR2INT_Pos                                  2                                                         /*!< TIMER2 IR: MR2INT Position          */
+#define TIMER2_IR_MR2INT_Msk                                  (0x01UL << TIMER2_IR_MR2INT_Pos)                          /*!< TIMER2 IR: MR2INT Mask              */
+#define TIMER2_IR_MR3INT_Pos                                  3                                                         /*!< TIMER2 IR: MR3INT Position          */
+#define TIMER2_IR_MR3INT_Msk                                  (0x01UL << TIMER2_IR_MR3INT_Pos)                          /*!< TIMER2 IR: MR3INT Mask              */
+#define TIMER2_IR_CR0INT_Pos                                  4                                                         /*!< TIMER2 IR: CR0INT Position          */
+#define TIMER2_IR_CR0INT_Msk                                  (0x01UL << TIMER2_IR_CR0INT_Pos)                          /*!< TIMER2 IR: CR0INT Mask              */
+#define TIMER2_IR_CR1INT_Pos                                  5                                                         /*!< TIMER2 IR: CR1INT Position          */
+#define TIMER2_IR_CR1INT_Msk                                  (0x01UL << TIMER2_IR_CR1INT_Pos)                          /*!< TIMER2 IR: CR1INT Mask              */
+#define TIMER2_IR_CR2INT_Pos                                  6                                                         /*!< TIMER2 IR: CR2INT Position          */
+#define TIMER2_IR_CR2INT_Msk                                  (0x01UL << TIMER2_IR_CR2INT_Pos)                          /*!< TIMER2 IR: CR2INT Mask              */
+#define TIMER2_IR_CR3INT_Pos                                  7                                                         /*!< TIMER2 IR: CR3INT Position          */
+#define TIMER2_IR_CR3INT_Msk                                  (0x01UL << TIMER2_IR_CR3INT_Pos)                          /*!< TIMER2 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER2_TCR  -------------------------------------------
+#define TIMER2_TCR_CEN_Pos                                    0                                                         /*!< TIMER2 TCR: CEN Position            */
+#define TIMER2_TCR_CEN_Msk                                    (0x01UL << TIMER2_TCR_CEN_Pos)                            /*!< TIMER2 TCR: CEN Mask                */
+#define TIMER2_TCR_CRST_Pos                                   1                                                         /*!< TIMER2 TCR: CRST Position           */
+#define TIMER2_TCR_CRST_Msk                                   (0x01UL << TIMER2_TCR_CRST_Pos)                           /*!< TIMER2 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER2_TC  -------------------------------------------
+#define TIMER2_TC_TC_Pos                                      0                                                         /*!< TIMER2 TC: TC Position              */
+#define TIMER2_TC_TC_Msk                                      (0xffffffffUL << TIMER2_TC_TC_Pos)                        /*!< TIMER2 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER2_PR  -------------------------------------------
+#define TIMER2_PR_PM_Pos                                      0                                                         /*!< TIMER2 PR: PM Position              */
+#define TIMER2_PR_PM_Msk                                      (0xffffffffUL << TIMER2_PR_PM_Pos)                        /*!< TIMER2 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER2_PC  -------------------------------------------
+#define TIMER2_PC_PC_Pos                                      0                                                         /*!< TIMER2 PC: PC Position              */
+#define TIMER2_PC_PC_Msk                                      (0xffffffffUL << TIMER2_PC_PC_Pos)                        /*!< TIMER2 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER2_MCR  -------------------------------------------
+#define TIMER2_MCR_MR0I_Pos                                   0                                                         /*!< TIMER2 MCR: MR0I Position           */
+#define TIMER2_MCR_MR0I_Msk                                   (0x01UL << TIMER2_MCR_MR0I_Pos)                           /*!< TIMER2 MCR: MR0I Mask               */
+#define TIMER2_MCR_MR0R_Pos                                   1                                                         /*!< TIMER2 MCR: MR0R Position           */
+#define TIMER2_MCR_MR0R_Msk                                   (0x01UL << TIMER2_MCR_MR0R_Pos)                           /*!< TIMER2 MCR: MR0R Mask               */
+#define TIMER2_MCR_MR0S_Pos                                   2                                                         /*!< TIMER2 MCR: MR0S Position           */
+#define TIMER2_MCR_MR0S_Msk                                   (0x01UL << TIMER2_MCR_MR0S_Pos)                           /*!< TIMER2 MCR: MR0S Mask               */
+#define TIMER2_MCR_MR1I_Pos                                   3                                                         /*!< TIMER2 MCR: MR1I Position           */
+#define TIMER2_MCR_MR1I_Msk                                   (0x01UL << TIMER2_MCR_MR1I_Pos)                           /*!< TIMER2 MCR: MR1I Mask               */
+#define TIMER2_MCR_MR1R_Pos                                   4                                                         /*!< TIMER2 MCR: MR1R Position           */
+#define TIMER2_MCR_MR1R_Msk                                   (0x01UL << TIMER2_MCR_MR1R_Pos)                           /*!< TIMER2 MCR: MR1R Mask               */
+#define TIMER2_MCR_MR1S_Pos                                   5                                                         /*!< TIMER2 MCR: MR1S Position           */
+#define TIMER2_MCR_MR1S_Msk                                   (0x01UL << TIMER2_MCR_MR1S_Pos)                           /*!< TIMER2 MCR: MR1S Mask               */
+#define TIMER2_MCR_MR2I_Pos                                   6                                                         /*!< TIMER2 MCR: MR2I Position           */
+#define TIMER2_MCR_MR2I_Msk                                   (0x01UL << TIMER2_MCR_MR2I_Pos)                           /*!< TIMER2 MCR: MR2I Mask               */
+#define TIMER2_MCR_MR2R_Pos                                   7                                                         /*!< TIMER2 MCR: MR2R Position           */
+#define TIMER2_MCR_MR2R_Msk                                   (0x01UL << TIMER2_MCR_MR2R_Pos)                           /*!< TIMER2 MCR: MR2R Mask               */
+#define TIMER2_MCR_MR2S_Pos                                   8                                                         /*!< TIMER2 MCR: MR2S Position           */
+#define TIMER2_MCR_MR2S_Msk                                   (0x01UL << TIMER2_MCR_MR2S_Pos)                           /*!< TIMER2 MCR: MR2S Mask               */
+#define TIMER2_MCR_MR3I_Pos                                   9                                                         /*!< TIMER2 MCR: MR3I Position           */
+#define TIMER2_MCR_MR3I_Msk                                   (0x01UL << TIMER2_MCR_MR3I_Pos)                           /*!< TIMER2 MCR: MR3I Mask               */
+#define TIMER2_MCR_MR3R_Pos                                   10                                                        /*!< TIMER2 MCR: MR3R Position           */
+#define TIMER2_MCR_MR3R_Msk                                   (0x01UL << TIMER2_MCR_MR3R_Pos)                           /*!< TIMER2 MCR: MR3R Mask               */
+#define TIMER2_MCR_MR3S_Pos                                   11                                                        /*!< TIMER2 MCR: MR3S Position           */
+#define TIMER2_MCR_MR3S_Msk                                   (0x01UL << TIMER2_MCR_MR3S_Pos)                           /*!< TIMER2 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER2_MR0  -------------------------------------------
+#define TIMER2_MR0_MATCH_Pos                                  0                                                         /*!< TIMER2 MR0: MATCH Position          */
+#define TIMER2_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR0_MATCH_Pos)                    /*!< TIMER2 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_MR1  -------------------------------------------
+#define TIMER2_MR1_MATCH_Pos                                  0                                                         /*!< TIMER2 MR1: MATCH Position          */
+#define TIMER2_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR1_MATCH_Pos)                    /*!< TIMER2 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_MR2  -------------------------------------------
+#define TIMER2_MR2_MATCH_Pos                                  0                                                         /*!< TIMER2 MR2: MATCH Position          */
+#define TIMER2_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR2_MATCH_Pos)                    /*!< TIMER2 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_MR3  -------------------------------------------
+#define TIMER2_MR3_MATCH_Pos                                  0                                                         /*!< TIMER2 MR3: MATCH Position          */
+#define TIMER2_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR3_MATCH_Pos)                    /*!< TIMER2 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER2_CCR  -------------------------------------------
+#define TIMER2_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER2 CCR: CAP0RE Position         */
+#define TIMER2_CCR_CAP0RE_Msk                                 (0x01UL << TIMER2_CCR_CAP0RE_Pos)                         /*!< TIMER2 CCR: CAP0RE Mask             */
+#define TIMER2_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER2 CCR: CAP0FE Position         */
+#define TIMER2_CCR_CAP0FE_Msk                                 (0x01UL << TIMER2_CCR_CAP0FE_Pos)                         /*!< TIMER2 CCR: CAP0FE Mask             */
+#define TIMER2_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER2 CCR: CAP0I Position          */
+#define TIMER2_CCR_CAP0I_Msk                                  (0x01UL << TIMER2_CCR_CAP0I_Pos)                          /*!< TIMER2 CCR: CAP0I Mask              */
+#define TIMER2_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER2 CCR: CAP1RE Position         */
+#define TIMER2_CCR_CAP1RE_Msk                                 (0x01UL << TIMER2_CCR_CAP1RE_Pos)                         /*!< TIMER2 CCR: CAP1RE Mask             */
+#define TIMER2_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER2 CCR: CAP1FE Position         */
+#define TIMER2_CCR_CAP1FE_Msk                                 (0x01UL << TIMER2_CCR_CAP1FE_Pos)                         /*!< TIMER2 CCR: CAP1FE Mask             */
+#define TIMER2_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER2 CCR: CAP1I Position          */
+#define TIMER2_CCR_CAP1I_Msk                                  (0x01UL << TIMER2_CCR_CAP1I_Pos)                          /*!< TIMER2 CCR: CAP1I Mask              */
+#define TIMER2_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER2 CCR: CAP2RE Position         */
+#define TIMER2_CCR_CAP2RE_Msk                                 (0x01UL << TIMER2_CCR_CAP2RE_Pos)                         /*!< TIMER2 CCR: CAP2RE Mask             */
+#define TIMER2_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER2 CCR: CAP2FE Position         */
+#define TIMER2_CCR_CAP2FE_Msk                                 (0x01UL << TIMER2_CCR_CAP2FE_Pos)                         /*!< TIMER2 CCR: CAP2FE Mask             */
+#define TIMER2_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER2 CCR: CAP2I Position          */
+#define TIMER2_CCR_CAP2I_Msk                                  (0x01UL << TIMER2_CCR_CAP2I_Pos)                          /*!< TIMER2 CCR: CAP2I Mask              */
+#define TIMER2_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER2 CCR: CAP3RE Position         */
+#define TIMER2_CCR_CAP3RE_Msk                                 (0x01UL << TIMER2_CCR_CAP3RE_Pos)                         /*!< TIMER2 CCR: CAP3RE Mask             */
+#define TIMER2_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER2 CCR: CAP3FE Position         */
+#define TIMER2_CCR_CAP3FE_Msk                                 (0x01UL << TIMER2_CCR_CAP3FE_Pos)                         /*!< TIMER2 CCR: CAP3FE Mask             */
+#define TIMER2_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER2 CCR: CAP3I Position          */
+#define TIMER2_CCR_CAP3I_Msk                                  (0x01UL << TIMER2_CCR_CAP3I_Pos)                          /*!< TIMER2 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER2_CR0  -------------------------------------------
+#define TIMER2_CR0_CAP_Pos                                    0                                                         /*!< TIMER2 CR0: CAP Position            */
+#define TIMER2_CR0_CAP_Msk                                    (0xffffffffUL << TIMER2_CR0_CAP_Pos)                      /*!< TIMER2 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER2_CR1  -------------------------------------------
+#define TIMER2_CR1_CAP_Pos                                    0                                                         /*!< TIMER2 CR1: CAP Position            */
+#define TIMER2_CR1_CAP_Msk                                    (0xffffffffUL << TIMER2_CR1_CAP_Pos)                      /*!< TIMER2 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER2_CR2  -------------------------------------------
+#define TIMER2_CR2_CAP_Pos                                    0                                                         /*!< TIMER2 CR2: CAP Position            */
+#define TIMER2_CR2_CAP_Msk                                    (0xffffffffUL << TIMER2_CR2_CAP_Pos)                      /*!< TIMER2 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER2_CR3  -------------------------------------------
+#define TIMER2_CR3_CAP_Pos                                    0                                                         /*!< TIMER2 CR3: CAP Position            */
+#define TIMER2_CR3_CAP_Msk                                    (0xffffffffUL << TIMER2_CR3_CAP_Pos)                      /*!< TIMER2 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER2_EMR  -------------------------------------------
+#define TIMER2_EMR_EM0_Pos                                    0                                                         /*!< TIMER2 EMR: EM0 Position            */
+#define TIMER2_EMR_EM0_Msk                                    (0x01UL << TIMER2_EMR_EM0_Pos)                            /*!< TIMER2 EMR: EM0 Mask                */
+#define TIMER2_EMR_EM1_Pos                                    1                                                         /*!< TIMER2 EMR: EM1 Position            */
+#define TIMER2_EMR_EM1_Msk                                    (0x01UL << TIMER2_EMR_EM1_Pos)                            /*!< TIMER2 EMR: EM1 Mask                */
+#define TIMER2_EMR_EM2_Pos                                    2                                                         /*!< TIMER2 EMR: EM2 Position            */
+#define TIMER2_EMR_EM2_Msk                                    (0x01UL << TIMER2_EMR_EM2_Pos)                            /*!< TIMER2 EMR: EM2 Mask                */
+#define TIMER2_EMR_EM3_Pos                                    3                                                         /*!< TIMER2 EMR: EM3 Position            */
+#define TIMER2_EMR_EM3_Msk                                    (0x01UL << TIMER2_EMR_EM3_Pos)                            /*!< TIMER2 EMR: EM3 Mask                */
+#define TIMER2_EMR_EMC0_Pos                                   4                                                         /*!< TIMER2 EMR: EMC0 Position           */
+#define TIMER2_EMR_EMC0_Msk                                   (0x03UL << TIMER2_EMR_EMC0_Pos)                           /*!< TIMER2 EMR: EMC0 Mask               */
+#define TIMER2_EMR_EMC1_Pos                                   6                                                         /*!< TIMER2 EMR: EMC1 Position           */
+#define TIMER2_EMR_EMC1_Msk                                   (0x03UL << TIMER2_EMR_EMC1_Pos)                           /*!< TIMER2 EMR: EMC1 Mask               */
+#define TIMER2_EMR_EMC2_Pos                                   8                                                         /*!< TIMER2 EMR: EMC2 Position           */
+#define TIMER2_EMR_EMC2_Msk                                   (0x03UL << TIMER2_EMR_EMC2_Pos)                           /*!< TIMER2 EMR: EMC2 Mask               */
+#define TIMER2_EMR_EMC3_Pos                                   10                                                        /*!< TIMER2 EMR: EMC3 Position           */
+#define TIMER2_EMR_EMC3_Msk                                   (0x03UL << TIMER2_EMR_EMC3_Pos)                           /*!< TIMER2 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER2_CTCR  ------------------------------------------
+#define TIMER2_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER2 CTCR: CTMODE Position        */
+#define TIMER2_CTCR_CTMODE_Msk                                (0x03UL << TIMER2_CTCR_CTMODE_Pos)                        /*!< TIMER2 CTCR: CTMODE Mask            */
+#define TIMER2_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER2 CTCR: CINSEL Position        */
+#define TIMER2_CTCR_CINSEL_Msk                                (0x03UL << TIMER2_CTCR_CINSEL_Pos)                        /*!< TIMER2 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                TIMER3 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  TIMER3_IR  -------------------------------------------
+#define TIMER3_IR_MR0INT_Pos                                  0                                                         /*!< TIMER3 IR: MR0INT Position          */
+#define TIMER3_IR_MR0INT_Msk                                  (0x01UL << TIMER3_IR_MR0INT_Pos)                          /*!< TIMER3 IR: MR0INT Mask              */
+#define TIMER3_IR_MR1INT_Pos                                  1                                                         /*!< TIMER3 IR: MR1INT Position          */
+#define TIMER3_IR_MR1INT_Msk                                  (0x01UL << TIMER3_IR_MR1INT_Pos)                          /*!< TIMER3 IR: MR1INT Mask              */
+#define TIMER3_IR_MR2INT_Pos                                  2                                                         /*!< TIMER3 IR: MR2INT Position          */
+#define TIMER3_IR_MR2INT_Msk                                  (0x01UL << TIMER3_IR_MR2INT_Pos)                          /*!< TIMER3 IR: MR2INT Mask              */
+#define TIMER3_IR_MR3INT_Pos                                  3                                                         /*!< TIMER3 IR: MR3INT Position          */
+#define TIMER3_IR_MR3INT_Msk                                  (0x01UL << TIMER3_IR_MR3INT_Pos)                          /*!< TIMER3 IR: MR3INT Mask              */
+#define TIMER3_IR_CR0INT_Pos                                  4                                                         /*!< TIMER3 IR: CR0INT Position          */
+#define TIMER3_IR_CR0INT_Msk                                  (0x01UL << TIMER3_IR_CR0INT_Pos)                          /*!< TIMER3 IR: CR0INT Mask              */
+#define TIMER3_IR_CR1INT_Pos                                  5                                                         /*!< TIMER3 IR: CR1INT Position          */
+#define TIMER3_IR_CR1INT_Msk                                  (0x01UL << TIMER3_IR_CR1INT_Pos)                          /*!< TIMER3 IR: CR1INT Mask              */
+#define TIMER3_IR_CR2INT_Pos                                  6                                                         /*!< TIMER3 IR: CR2INT Position          */
+#define TIMER3_IR_CR2INT_Msk                                  (0x01UL << TIMER3_IR_CR2INT_Pos)                          /*!< TIMER3 IR: CR2INT Mask              */
+#define TIMER3_IR_CR3INT_Pos                                  7                                                         /*!< TIMER3 IR: CR3INT Position          */
+#define TIMER3_IR_CR3INT_Msk                                  (0x01UL << TIMER3_IR_CR3INT_Pos)                          /*!< TIMER3 IR: CR3INT Mask              */
+
+// ---------------------------------------  TIMER3_TCR  -------------------------------------------
+#define TIMER3_TCR_CEN_Pos                                    0                                                         /*!< TIMER3 TCR: CEN Position            */
+#define TIMER3_TCR_CEN_Msk                                    (0x01UL << TIMER3_TCR_CEN_Pos)                            /*!< TIMER3 TCR: CEN Mask                */
+#define TIMER3_TCR_CRST_Pos                                   1                                                         /*!< TIMER3 TCR: CRST Position           */
+#define TIMER3_TCR_CRST_Msk                                   (0x01UL << TIMER3_TCR_CRST_Pos)                           /*!< TIMER3 TCR: CRST Mask               */
+
+// ----------------------------------------  TIMER3_TC  -------------------------------------------
+#define TIMER3_TC_TC_Pos                                      0                                                         /*!< TIMER3 TC: TC Position              */
+#define TIMER3_TC_TC_Msk                                      (0xffffffffUL << TIMER3_TC_TC_Pos)                        /*!< TIMER3 TC: TC Mask                  */
+
+// ----------------------------------------  TIMER3_PR  -------------------------------------------
+#define TIMER3_PR_PM_Pos                                      0                                                         /*!< TIMER3 PR: PM Position              */
+#define TIMER3_PR_PM_Msk                                      (0xffffffffUL << TIMER3_PR_PM_Pos)                        /*!< TIMER3 PR: PM Mask                  */
+
+// ----------------------------------------  TIMER3_PC  -------------------------------------------
+#define TIMER3_PC_PC_Pos                                      0                                                         /*!< TIMER3 PC: PC Position              */
+#define TIMER3_PC_PC_Msk                                      (0xffffffffUL << TIMER3_PC_PC_Pos)                        /*!< TIMER3 PC: PC Mask                  */
+
+// ---------------------------------------  TIMER3_MCR  -------------------------------------------
+#define TIMER3_MCR_MR0I_Pos                                   0                                                         /*!< TIMER3 MCR: MR0I Position           */
+#define TIMER3_MCR_MR0I_Msk                                   (0x01UL << TIMER3_MCR_MR0I_Pos)                           /*!< TIMER3 MCR: MR0I Mask               */
+#define TIMER3_MCR_MR0R_Pos                                   1                                                         /*!< TIMER3 MCR: MR0R Position           */
+#define TIMER3_MCR_MR0R_Msk                                   (0x01UL << TIMER3_MCR_MR0R_Pos)                           /*!< TIMER3 MCR: MR0R Mask               */
+#define TIMER3_MCR_MR0S_Pos                                   2                                                         /*!< TIMER3 MCR: MR0S Position           */
+#define TIMER3_MCR_MR0S_Msk                                   (0x01UL << TIMER3_MCR_MR0S_Pos)                           /*!< TIMER3 MCR: MR0S Mask               */
+#define TIMER3_MCR_MR1I_Pos                                   3                                                         /*!< TIMER3 MCR: MR1I Position           */
+#define TIMER3_MCR_MR1I_Msk                                   (0x01UL << TIMER3_MCR_MR1I_Pos)                           /*!< TIMER3 MCR: MR1I Mask               */
+#define TIMER3_MCR_MR1R_Pos                                   4                                                         /*!< TIMER3 MCR: MR1R Position           */
+#define TIMER3_MCR_MR1R_Msk                                   (0x01UL << TIMER3_MCR_MR1R_Pos)                           /*!< TIMER3 MCR: MR1R Mask               */
+#define TIMER3_MCR_MR1S_Pos                                   5                                                         /*!< TIMER3 MCR: MR1S Position           */
+#define TIMER3_MCR_MR1S_Msk                                   (0x01UL << TIMER3_MCR_MR1S_Pos)                           /*!< TIMER3 MCR: MR1S Mask               */
+#define TIMER3_MCR_MR2I_Pos                                   6                                                         /*!< TIMER3 MCR: MR2I Position           */
+#define TIMER3_MCR_MR2I_Msk                                   (0x01UL << TIMER3_MCR_MR2I_Pos)                           /*!< TIMER3 MCR: MR2I Mask               */
+#define TIMER3_MCR_MR2R_Pos                                   7                                                         /*!< TIMER3 MCR: MR2R Position           */
+#define TIMER3_MCR_MR2R_Msk                                   (0x01UL << TIMER3_MCR_MR2R_Pos)                           /*!< TIMER3 MCR: MR2R Mask               */
+#define TIMER3_MCR_MR2S_Pos                                   8                                                         /*!< TIMER3 MCR: MR2S Position           */
+#define TIMER3_MCR_MR2S_Msk                                   (0x01UL << TIMER3_MCR_MR2S_Pos)                           /*!< TIMER3 MCR: MR2S Mask               */
+#define TIMER3_MCR_MR3I_Pos                                   9                                                         /*!< TIMER3 MCR: MR3I Position           */
+#define TIMER3_MCR_MR3I_Msk                                   (0x01UL << TIMER3_MCR_MR3I_Pos)                           /*!< TIMER3 MCR: MR3I Mask               */
+#define TIMER3_MCR_MR3R_Pos                                   10                                                        /*!< TIMER3 MCR: MR3R Position           */
+#define TIMER3_MCR_MR3R_Msk                                   (0x01UL << TIMER3_MCR_MR3R_Pos)                           /*!< TIMER3 MCR: MR3R Mask               */
+#define TIMER3_MCR_MR3S_Pos                                   11                                                        /*!< TIMER3 MCR: MR3S Position           */
+#define TIMER3_MCR_MR3S_Msk                                   (0x01UL << TIMER3_MCR_MR3S_Pos)                           /*!< TIMER3 MCR: MR3S Mask               */
+
+// ---------------------------------------  TIMER3_MR0  -------------------------------------------
+#define TIMER3_MR0_MATCH_Pos                                  0                                                         /*!< TIMER3 MR0: MATCH Position          */
+#define TIMER3_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR0_MATCH_Pos)                    /*!< TIMER3 MR0: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_MR1  -------------------------------------------
+#define TIMER3_MR1_MATCH_Pos                                  0                                                         /*!< TIMER3 MR1: MATCH Position          */
+#define TIMER3_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR1_MATCH_Pos)                    /*!< TIMER3 MR1: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_MR2  -------------------------------------------
+#define TIMER3_MR2_MATCH_Pos                                  0                                                         /*!< TIMER3 MR2: MATCH Position          */
+#define TIMER3_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR2_MATCH_Pos)                    /*!< TIMER3 MR2: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_MR3  -------------------------------------------
+#define TIMER3_MR3_MATCH_Pos                                  0                                                         /*!< TIMER3 MR3: MATCH Position          */
+#define TIMER3_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR3_MATCH_Pos)                    /*!< TIMER3 MR3: MATCH Mask              */
+
+// ---------------------------------------  TIMER3_CCR  -------------------------------------------
+#define TIMER3_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER3 CCR: CAP0RE Position         */
+#define TIMER3_CCR_CAP0RE_Msk                                 (0x01UL << TIMER3_CCR_CAP0RE_Pos)                         /*!< TIMER3 CCR: CAP0RE Mask             */
+#define TIMER3_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER3 CCR: CAP0FE Position         */
+#define TIMER3_CCR_CAP0FE_Msk                                 (0x01UL << TIMER3_CCR_CAP0FE_Pos)                         /*!< TIMER3 CCR: CAP0FE Mask             */
+#define TIMER3_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER3 CCR: CAP0I Position          */
+#define TIMER3_CCR_CAP0I_Msk                                  (0x01UL << TIMER3_CCR_CAP0I_Pos)                          /*!< TIMER3 CCR: CAP0I Mask              */
+#define TIMER3_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER3 CCR: CAP1RE Position         */
+#define TIMER3_CCR_CAP1RE_Msk                                 (0x01UL << TIMER3_CCR_CAP1RE_Pos)                         /*!< TIMER3 CCR: CAP1RE Mask             */
+#define TIMER3_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER3 CCR: CAP1FE Position         */
+#define TIMER3_CCR_CAP1FE_Msk                                 (0x01UL << TIMER3_CCR_CAP1FE_Pos)                         /*!< TIMER3 CCR: CAP1FE Mask             */
+#define TIMER3_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER3 CCR: CAP1I Position          */
+#define TIMER3_CCR_CAP1I_Msk                                  (0x01UL << TIMER3_CCR_CAP1I_Pos)                          /*!< TIMER3 CCR: CAP1I Mask              */
+#define TIMER3_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER3 CCR: CAP2RE Position         */
+#define TIMER3_CCR_CAP2RE_Msk                                 (0x01UL << TIMER3_CCR_CAP2RE_Pos)                         /*!< TIMER3 CCR: CAP2RE Mask             */
+#define TIMER3_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER3 CCR: CAP2FE Position         */
+#define TIMER3_CCR_CAP2FE_Msk                                 (0x01UL << TIMER3_CCR_CAP2FE_Pos)                         /*!< TIMER3 CCR: CAP2FE Mask             */
+#define TIMER3_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER3 CCR: CAP2I Position          */
+#define TIMER3_CCR_CAP2I_Msk                                  (0x01UL << TIMER3_CCR_CAP2I_Pos)                          /*!< TIMER3 CCR: CAP2I Mask              */
+#define TIMER3_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER3 CCR: CAP3RE Position         */
+#define TIMER3_CCR_CAP3RE_Msk                                 (0x01UL << TIMER3_CCR_CAP3RE_Pos)                         /*!< TIMER3 CCR: CAP3RE Mask             */
+#define TIMER3_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER3 CCR: CAP3FE Position         */
+#define TIMER3_CCR_CAP3FE_Msk                                 (0x01UL << TIMER3_CCR_CAP3FE_Pos)                         /*!< TIMER3 CCR: CAP3FE Mask             */
+#define TIMER3_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER3 CCR: CAP3I Position          */
+#define TIMER3_CCR_CAP3I_Msk                                  (0x01UL << TIMER3_CCR_CAP3I_Pos)                          /*!< TIMER3 CCR: CAP3I Mask              */
+
+// ---------------------------------------  TIMER3_CR0  -------------------------------------------
+#define TIMER3_CR0_CAP_Pos                                    0                                                         /*!< TIMER3 CR0: CAP Position            */
+#define TIMER3_CR0_CAP_Msk                                    (0xffffffffUL << TIMER3_CR0_CAP_Pos)                      /*!< TIMER3 CR0: CAP Mask                */
+
+// ---------------------------------------  TIMER3_CR1  -------------------------------------------
+#define TIMER3_CR1_CAP_Pos                                    0                                                         /*!< TIMER3 CR1: CAP Position            */
+#define TIMER3_CR1_CAP_Msk                                    (0xffffffffUL << TIMER3_CR1_CAP_Pos)                      /*!< TIMER3 CR1: CAP Mask                */
+
+// ---------------------------------------  TIMER3_CR2  -------------------------------------------
+#define TIMER3_CR2_CAP_Pos                                    0                                                         /*!< TIMER3 CR2: CAP Position            */
+#define TIMER3_CR2_CAP_Msk                                    (0xffffffffUL << TIMER3_CR2_CAP_Pos)                      /*!< TIMER3 CR2: CAP Mask                */
+
+// ---------------------------------------  TIMER3_CR3  -------------------------------------------
+#define TIMER3_CR3_CAP_Pos                                    0                                                         /*!< TIMER3 CR3: CAP Position            */
+#define TIMER3_CR3_CAP_Msk                                    (0xffffffffUL << TIMER3_CR3_CAP_Pos)                      /*!< TIMER3 CR3: CAP Mask                */
+
+// ---------------------------------------  TIMER3_EMR  -------------------------------------------
+#define TIMER3_EMR_EM0_Pos                                    0                                                         /*!< TIMER3 EMR: EM0 Position            */
+#define TIMER3_EMR_EM0_Msk                                    (0x01UL << TIMER3_EMR_EM0_Pos)                            /*!< TIMER3 EMR: EM0 Mask                */
+#define TIMER3_EMR_EM1_Pos                                    1                                                         /*!< TIMER3 EMR: EM1 Position            */
+#define TIMER3_EMR_EM1_Msk                                    (0x01UL << TIMER3_EMR_EM1_Pos)                            /*!< TIMER3 EMR: EM1 Mask                */
+#define TIMER3_EMR_EM2_Pos                                    2                                                         /*!< TIMER3 EMR: EM2 Position            */
+#define TIMER3_EMR_EM2_Msk                                    (0x01UL << TIMER3_EMR_EM2_Pos)                            /*!< TIMER3 EMR: EM2 Mask                */
+#define TIMER3_EMR_EM3_Pos                                    3                                                         /*!< TIMER3 EMR: EM3 Position            */
+#define TIMER3_EMR_EM3_Msk                                    (0x01UL << TIMER3_EMR_EM3_Pos)                            /*!< TIMER3 EMR: EM3 Mask                */
+#define TIMER3_EMR_EMC0_Pos                                   4                                                         /*!< TIMER3 EMR: EMC0 Position           */
+#define TIMER3_EMR_EMC0_Msk                                   (0x03UL << TIMER3_EMR_EMC0_Pos)                           /*!< TIMER3 EMR: EMC0 Mask               */
+#define TIMER3_EMR_EMC1_Pos                                   6                                                         /*!< TIMER3 EMR: EMC1 Position           */
+#define TIMER3_EMR_EMC1_Msk                                   (0x03UL << TIMER3_EMR_EMC1_Pos)                           /*!< TIMER3 EMR: EMC1 Mask               */
+#define TIMER3_EMR_EMC2_Pos                                   8                                                         /*!< TIMER3 EMR: EMC2 Position           */
+#define TIMER3_EMR_EMC2_Msk                                   (0x03UL << TIMER3_EMR_EMC2_Pos)                           /*!< TIMER3 EMR: EMC2 Mask               */
+#define TIMER3_EMR_EMC3_Pos                                   10                                                        /*!< TIMER3 EMR: EMC3 Position           */
+#define TIMER3_EMR_EMC3_Msk                                   (0x03UL << TIMER3_EMR_EMC3_Pos)                           /*!< TIMER3 EMR: EMC3 Mask               */
+
+// ---------------------------------------  TIMER3_CTCR  ------------------------------------------
+#define TIMER3_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER3 CTCR: CTMODE Position        */
+#define TIMER3_CTCR_CTMODE_Msk                                (0x03UL << TIMER3_CTCR_CTMODE_Pos)                        /*!< TIMER3 CTCR: CTMODE Mask            */
+#define TIMER3_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER3 CTCR: CINSEL Position        */
+#define TIMER3_CTCR_CINSEL_Msk                                (0x03UL << TIMER3_CTCR_CINSEL_Pos)                        /*!< TIMER3 CTCR: CINSEL Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  SCU Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  SCU_SFSP0_0  ------------------------------------------
+#define SCU_SFSP0_0_MODE_Pos                                  0                                                         /*!< SCU SFSP0_0: MODE Position          */
+#define SCU_SFSP0_0_MODE_Msk                                  (0x07UL << SCU_SFSP0_0_MODE_Pos)                          /*!< SCU SFSP0_0: MODE Mask              */
+#define SCU_SFSP0_0_EPD_Pos                                   3                                                         /*!< SCU SFSP0_0: EPD Position           */
+#define SCU_SFSP0_0_EPD_Msk                                   (0x01UL << SCU_SFSP0_0_EPD_Pos)                           /*!< SCU SFSP0_0: EPD Mask               */
+#define SCU_SFSP0_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_0: EPUN Position          */
+#define SCU_SFSP0_0_EPUN_Msk                                  (0x01UL << SCU_SFSP0_0_EPUN_Pos)                          /*!< SCU SFSP0_0: EPUN Mask              */
+#define SCU_SFSP0_0_EHS_Pos                                   5                                                         /*!< SCU SFSP0_0: EHS Position           */
+#define SCU_SFSP0_0_EHS_Msk                                   (0x01UL << SCU_SFSP0_0_EHS_Pos)                           /*!< SCU SFSP0_0: EHS Mask               */
+#define SCU_SFSP0_0_EZI_Pos                                   6                                                         /*!< SCU SFSP0_0: EZI Position           */
+#define SCU_SFSP0_0_EZI_Msk                                   (0x01UL << SCU_SFSP0_0_EZI_Pos)                           /*!< SCU SFSP0_0: EZI Mask               */
+
+// ---------------------------------------  SCU_SFSP0_1  ------------------------------------------
+#define SCU_SFSP0_1_MODE_Pos                                  0                                                         /*!< SCU SFSP0_1: MODE Position          */
+#define SCU_SFSP0_1_MODE_Msk                                  (0x07UL << SCU_SFSP0_1_MODE_Pos)                          /*!< SCU SFSP0_1: MODE Mask              */
+#define SCU_SFSP0_1_EPD_Pos                                   3                                                         /*!< SCU SFSP0_1: EPD Position           */
+#define SCU_SFSP0_1_EPD_Msk                                   (0x01UL << SCU_SFSP0_1_EPD_Pos)                           /*!< SCU SFSP0_1: EPD Mask               */
+#define SCU_SFSP0_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_1: EPUN Position          */
+#define SCU_SFSP0_1_EPUN_Msk                                  (0x01UL << SCU_SFSP0_1_EPUN_Pos)                          /*!< SCU SFSP0_1: EPUN Mask              */
+#define SCU_SFSP0_1_EHS_Pos                                   5                                                         /*!< SCU SFSP0_1: EHS Position           */
+#define SCU_SFSP0_1_EHS_Msk                                   (0x01UL << SCU_SFSP0_1_EHS_Pos)                           /*!< SCU SFSP0_1: EHS Mask               */
+#define SCU_SFSP0_1_EZI_Pos                                   6                                                         /*!< SCU SFSP0_1: EZI Position           */
+#define SCU_SFSP0_1_EZI_Msk                                   (0x01UL << SCU_SFSP0_1_EZI_Pos)                           /*!< SCU SFSP0_1: EZI Mask               */
+
+// ---------------------------------------  SCU_SFSP1_0  ------------------------------------------
+#define SCU_SFSP1_0_MODE_Pos                                  0                                                         /*!< SCU SFSP1_0: MODE Position          */
+#define SCU_SFSP1_0_MODE_Msk                                  (0x07UL << SCU_SFSP1_0_MODE_Pos)                          /*!< SCU SFSP1_0: MODE Mask              */
+#define SCU_SFSP1_0_EPD_Pos                                   3                                                         /*!< SCU SFSP1_0: EPD Position           */
+#define SCU_SFSP1_0_EPD_Msk                                   (0x01UL << SCU_SFSP1_0_EPD_Pos)                           /*!< SCU SFSP1_0: EPD Mask               */
+#define SCU_SFSP1_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_0: EPUN Position          */
+#define SCU_SFSP1_0_EPUN_Msk                                  (0x01UL << SCU_SFSP1_0_EPUN_Pos)                          /*!< SCU SFSP1_0: EPUN Mask              */
+#define SCU_SFSP1_0_EHS_Pos                                   5                                                         /*!< SCU SFSP1_0: EHS Position           */
+#define SCU_SFSP1_0_EHS_Msk                                   (0x01UL << SCU_SFSP1_0_EHS_Pos)                           /*!< SCU SFSP1_0: EHS Mask               */
+#define SCU_SFSP1_0_EZI_Pos                                   6                                                         /*!< SCU SFSP1_0: EZI Position           */
+#define SCU_SFSP1_0_EZI_Msk                                   (0x01UL << SCU_SFSP1_0_EZI_Pos)                           /*!< SCU SFSP1_0: EZI Mask               */
+#define SCU_SFSP1_0_EHD_Pos                                   8                                                         /*!< SCU SFSP1_0: EHD Position           */
+#define SCU_SFSP1_0_EHD_Msk                                   (0x03UL << SCU_SFSP1_0_EHD_Pos)                           /*!< SCU SFSP1_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_1  ------------------------------------------
+#define SCU_SFSP1_1_MODE_Pos                                  0                                                         /*!< SCU SFSP1_1: MODE Position          */
+#define SCU_SFSP1_1_MODE_Msk                                  (0x07UL << SCU_SFSP1_1_MODE_Pos)                          /*!< SCU SFSP1_1: MODE Mask              */
+#define SCU_SFSP1_1_EPD_Pos                                   3                                                         /*!< SCU SFSP1_1: EPD Position           */
+#define SCU_SFSP1_1_EPD_Msk                                   (0x01UL << SCU_SFSP1_1_EPD_Pos)                           /*!< SCU SFSP1_1: EPD Mask               */
+#define SCU_SFSP1_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_1: EPUN Position          */
+#define SCU_SFSP1_1_EPUN_Msk                                  (0x01UL << SCU_SFSP1_1_EPUN_Pos)                          /*!< SCU SFSP1_1: EPUN Mask              */
+#define SCU_SFSP1_1_EHS_Pos                                   5                                                         /*!< SCU SFSP1_1: EHS Position           */
+#define SCU_SFSP1_1_EHS_Msk                                   (0x01UL << SCU_SFSP1_1_EHS_Pos)                           /*!< SCU SFSP1_1: EHS Mask               */
+#define SCU_SFSP1_1_EZI_Pos                                   6                                                         /*!< SCU SFSP1_1: EZI Position           */
+#define SCU_SFSP1_1_EZI_Msk                                   (0x01UL << SCU_SFSP1_1_EZI_Pos)                           /*!< SCU SFSP1_1: EZI Mask               */
+#define SCU_SFSP1_1_EHD_Pos                                   8                                                         /*!< SCU SFSP1_1: EHD Position           */
+#define SCU_SFSP1_1_EHD_Msk                                   (0x03UL << SCU_SFSP1_1_EHD_Pos)                           /*!< SCU SFSP1_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_2  ------------------------------------------
+#define SCU_SFSP1_2_MODE_Pos                                  0                                                         /*!< SCU SFSP1_2: MODE Position          */
+#define SCU_SFSP1_2_MODE_Msk                                  (0x07UL << SCU_SFSP1_2_MODE_Pos)                          /*!< SCU SFSP1_2: MODE Mask              */
+#define SCU_SFSP1_2_EPD_Pos                                   3                                                         /*!< SCU SFSP1_2: EPD Position           */
+#define SCU_SFSP1_2_EPD_Msk                                   (0x01UL << SCU_SFSP1_2_EPD_Pos)                           /*!< SCU SFSP1_2: EPD Mask               */
+#define SCU_SFSP1_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_2: EPUN Position          */
+#define SCU_SFSP1_2_EPUN_Msk                                  (0x01UL << SCU_SFSP1_2_EPUN_Pos)                          /*!< SCU SFSP1_2: EPUN Mask              */
+#define SCU_SFSP1_2_EHS_Pos                                   5                                                         /*!< SCU SFSP1_2: EHS Position           */
+#define SCU_SFSP1_2_EHS_Msk                                   (0x01UL << SCU_SFSP1_2_EHS_Pos)                           /*!< SCU SFSP1_2: EHS Mask               */
+#define SCU_SFSP1_2_EZI_Pos                                   6                                                         /*!< SCU SFSP1_2: EZI Position           */
+#define SCU_SFSP1_2_EZI_Msk                                   (0x01UL << SCU_SFSP1_2_EZI_Pos)                           /*!< SCU SFSP1_2: EZI Mask               */
+#define SCU_SFSP1_2_EHD_Pos                                   8                                                         /*!< SCU SFSP1_2: EHD Position           */
+#define SCU_SFSP1_2_EHD_Msk                                   (0x03UL << SCU_SFSP1_2_EHD_Pos)                           /*!< SCU SFSP1_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_3  ------------------------------------------
+#define SCU_SFSP1_3_MODE_Pos                                  0                                                         /*!< SCU SFSP1_3: MODE Position          */
+#define SCU_SFSP1_3_MODE_Msk                                  (0x07UL << SCU_SFSP1_3_MODE_Pos)                          /*!< SCU SFSP1_3: MODE Mask              */
+#define SCU_SFSP1_3_EPD_Pos                                   3                                                         /*!< SCU SFSP1_3: EPD Position           */
+#define SCU_SFSP1_3_EPD_Msk                                   (0x01UL << SCU_SFSP1_3_EPD_Pos)                           /*!< SCU SFSP1_3: EPD Mask               */
+#define SCU_SFSP1_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_3: EPUN Position          */
+#define SCU_SFSP1_3_EPUN_Msk                                  (0x01UL << SCU_SFSP1_3_EPUN_Pos)                          /*!< SCU SFSP1_3: EPUN Mask              */
+#define SCU_SFSP1_3_EHS_Pos                                   5                                                         /*!< SCU SFSP1_3: EHS Position           */
+#define SCU_SFSP1_3_EHS_Msk                                   (0x01UL << SCU_SFSP1_3_EHS_Pos)                           /*!< SCU SFSP1_3: EHS Mask               */
+#define SCU_SFSP1_3_EZI_Pos                                   6                                                         /*!< SCU SFSP1_3: EZI Position           */
+#define SCU_SFSP1_3_EZI_Msk                                   (0x01UL << SCU_SFSP1_3_EZI_Pos)                           /*!< SCU SFSP1_3: EZI Mask               */
+#define SCU_SFSP1_3_EHD_Pos                                   8                                                         /*!< SCU SFSP1_3: EHD Position           */
+#define SCU_SFSP1_3_EHD_Msk                                   (0x03UL << SCU_SFSP1_3_EHD_Pos)                           /*!< SCU SFSP1_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_4  ------------------------------------------
+#define SCU_SFSP1_4_MODE_Pos                                  0                                                         /*!< SCU SFSP1_4: MODE Position          */
+#define SCU_SFSP1_4_MODE_Msk                                  (0x07UL << SCU_SFSP1_4_MODE_Pos)                          /*!< SCU SFSP1_4: MODE Mask              */
+#define SCU_SFSP1_4_EPD_Pos                                   3                                                         /*!< SCU SFSP1_4: EPD Position           */
+#define SCU_SFSP1_4_EPD_Msk                                   (0x01UL << SCU_SFSP1_4_EPD_Pos)                           /*!< SCU SFSP1_4: EPD Mask               */
+#define SCU_SFSP1_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_4: EPUN Position          */
+#define SCU_SFSP1_4_EPUN_Msk                                  (0x01UL << SCU_SFSP1_4_EPUN_Pos)                          /*!< SCU SFSP1_4: EPUN Mask              */
+#define SCU_SFSP1_4_EHS_Pos                                   5                                                         /*!< SCU SFSP1_4: EHS Position           */
+#define SCU_SFSP1_4_EHS_Msk                                   (0x01UL << SCU_SFSP1_4_EHS_Pos)                           /*!< SCU SFSP1_4: EHS Mask               */
+#define SCU_SFSP1_4_EZI_Pos                                   6                                                         /*!< SCU SFSP1_4: EZI Position           */
+#define SCU_SFSP1_4_EZI_Msk                                   (0x01UL << SCU_SFSP1_4_EZI_Pos)                           /*!< SCU SFSP1_4: EZI Mask               */
+#define SCU_SFSP1_4_EHD_Pos                                   8                                                         /*!< SCU SFSP1_4: EHD Position           */
+#define SCU_SFSP1_4_EHD_Msk                                   (0x03UL << SCU_SFSP1_4_EHD_Pos)                           /*!< SCU SFSP1_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_5  ------------------------------------------
+#define SCU_SFSP1_5_MODE_Pos                                  0                                                         /*!< SCU SFSP1_5: MODE Position          */
+#define SCU_SFSP1_5_MODE_Msk                                  (0x07UL << SCU_SFSP1_5_MODE_Pos)                          /*!< SCU SFSP1_5: MODE Mask              */
+#define SCU_SFSP1_5_EPD_Pos                                   3                                                         /*!< SCU SFSP1_5: EPD Position           */
+#define SCU_SFSP1_5_EPD_Msk                                   (0x01UL << SCU_SFSP1_5_EPD_Pos)                           /*!< SCU SFSP1_5: EPD Mask               */
+#define SCU_SFSP1_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_5: EPUN Position          */
+#define SCU_SFSP1_5_EPUN_Msk                                  (0x01UL << SCU_SFSP1_5_EPUN_Pos)                          /*!< SCU SFSP1_5: EPUN Mask              */
+#define SCU_SFSP1_5_EHS_Pos                                   5                                                         /*!< SCU SFSP1_5: EHS Position           */
+#define SCU_SFSP1_5_EHS_Msk                                   (0x01UL << SCU_SFSP1_5_EHS_Pos)                           /*!< SCU SFSP1_5: EHS Mask               */
+#define SCU_SFSP1_5_EZI_Pos                                   6                                                         /*!< SCU SFSP1_5: EZI Position           */
+#define SCU_SFSP1_5_EZI_Msk                                   (0x01UL << SCU_SFSP1_5_EZI_Pos)                           /*!< SCU SFSP1_5: EZI Mask               */
+#define SCU_SFSP1_5_EHD_Pos                                   8                                                         /*!< SCU SFSP1_5: EHD Position           */
+#define SCU_SFSP1_5_EHD_Msk                                   (0x03UL << SCU_SFSP1_5_EHD_Pos)                           /*!< SCU SFSP1_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_6  ------------------------------------------
+#define SCU_SFSP1_6_MODE_Pos                                  0                                                         /*!< SCU SFSP1_6: MODE Position          */
+#define SCU_SFSP1_6_MODE_Msk                                  (0x07UL << SCU_SFSP1_6_MODE_Pos)                          /*!< SCU SFSP1_6: MODE Mask              */
+#define SCU_SFSP1_6_EPD_Pos                                   3                                                         /*!< SCU SFSP1_6: EPD Position           */
+#define SCU_SFSP1_6_EPD_Msk                                   (0x01UL << SCU_SFSP1_6_EPD_Pos)                           /*!< SCU SFSP1_6: EPD Mask               */
+#define SCU_SFSP1_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_6: EPUN Position          */
+#define SCU_SFSP1_6_EPUN_Msk                                  (0x01UL << SCU_SFSP1_6_EPUN_Pos)                          /*!< SCU SFSP1_6: EPUN Mask              */
+#define SCU_SFSP1_6_EHS_Pos                                   5                                                         /*!< SCU SFSP1_6: EHS Position           */
+#define SCU_SFSP1_6_EHS_Msk                                   (0x01UL << SCU_SFSP1_6_EHS_Pos)                           /*!< SCU SFSP1_6: EHS Mask               */
+#define SCU_SFSP1_6_EZI_Pos                                   6                                                         /*!< SCU SFSP1_6: EZI Position           */
+#define SCU_SFSP1_6_EZI_Msk                                   (0x01UL << SCU_SFSP1_6_EZI_Pos)                           /*!< SCU SFSP1_6: EZI Mask               */
+#define SCU_SFSP1_6_EHD_Pos                                   8                                                         /*!< SCU SFSP1_6: EHD Position           */
+#define SCU_SFSP1_6_EHD_Msk                                   (0x03UL << SCU_SFSP1_6_EHD_Pos)                           /*!< SCU SFSP1_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_7  ------------------------------------------
+#define SCU_SFSP1_7_MODE_Pos                                  0                                                         /*!< SCU SFSP1_7: MODE Position          */
+#define SCU_SFSP1_7_MODE_Msk                                  (0x07UL << SCU_SFSP1_7_MODE_Pos)                          /*!< SCU SFSP1_7: MODE Mask              */
+#define SCU_SFSP1_7_EPD_Pos                                   3                                                         /*!< SCU SFSP1_7: EPD Position           */
+#define SCU_SFSP1_7_EPD_Msk                                   (0x01UL << SCU_SFSP1_7_EPD_Pos)                           /*!< SCU SFSP1_7: EPD Mask               */
+#define SCU_SFSP1_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_7: EPUN Position          */
+#define SCU_SFSP1_7_EPUN_Msk                                  (0x01UL << SCU_SFSP1_7_EPUN_Pos)                          /*!< SCU SFSP1_7: EPUN Mask              */
+#define SCU_SFSP1_7_EHS_Pos                                   5                                                         /*!< SCU SFSP1_7: EHS Position           */
+#define SCU_SFSP1_7_EHS_Msk                                   (0x01UL << SCU_SFSP1_7_EHS_Pos)                           /*!< SCU SFSP1_7: EHS Mask               */
+#define SCU_SFSP1_7_EZI_Pos                                   6                                                         /*!< SCU SFSP1_7: EZI Position           */
+#define SCU_SFSP1_7_EZI_Msk                                   (0x01UL << SCU_SFSP1_7_EZI_Pos)                           /*!< SCU SFSP1_7: EZI Mask               */
+#define SCU_SFSP1_7_EHD_Pos                                   8                                                         /*!< SCU SFSP1_7: EHD Position           */
+#define SCU_SFSP1_7_EHD_Msk                                   (0x03UL << SCU_SFSP1_7_EHD_Pos)                           /*!< SCU SFSP1_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_8  ------------------------------------------
+#define SCU_SFSP1_8_MODE_Pos                                  0                                                         /*!< SCU SFSP1_8: MODE Position          */
+#define SCU_SFSP1_8_MODE_Msk                                  (0x07UL << SCU_SFSP1_8_MODE_Pos)                          /*!< SCU SFSP1_8: MODE Mask              */
+#define SCU_SFSP1_8_EPD_Pos                                   3                                                         /*!< SCU SFSP1_8: EPD Position           */
+#define SCU_SFSP1_8_EPD_Msk                                   (0x01UL << SCU_SFSP1_8_EPD_Pos)                           /*!< SCU SFSP1_8: EPD Mask               */
+#define SCU_SFSP1_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_8: EPUN Position          */
+#define SCU_SFSP1_8_EPUN_Msk                                  (0x01UL << SCU_SFSP1_8_EPUN_Pos)                          /*!< SCU SFSP1_8: EPUN Mask              */
+#define SCU_SFSP1_8_EHS_Pos                                   5                                                         /*!< SCU SFSP1_8: EHS Position           */
+#define SCU_SFSP1_8_EHS_Msk                                   (0x01UL << SCU_SFSP1_8_EHS_Pos)                           /*!< SCU SFSP1_8: EHS Mask               */
+#define SCU_SFSP1_8_EZI_Pos                                   6                                                         /*!< SCU SFSP1_8: EZI Position           */
+#define SCU_SFSP1_8_EZI_Msk                                   (0x01UL << SCU_SFSP1_8_EZI_Pos)                           /*!< SCU SFSP1_8: EZI Mask               */
+#define SCU_SFSP1_8_EHD_Pos                                   8                                                         /*!< SCU SFSP1_8: EHD Position           */
+#define SCU_SFSP1_8_EHD_Msk                                   (0x03UL << SCU_SFSP1_8_EHD_Pos)                           /*!< SCU SFSP1_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP1_9  ------------------------------------------
+#define SCU_SFSP1_9_MODE_Pos                                  0                                                         /*!< SCU SFSP1_9: MODE Position          */
+#define SCU_SFSP1_9_MODE_Msk                                  (0x07UL << SCU_SFSP1_9_MODE_Pos)                          /*!< SCU SFSP1_9: MODE Mask              */
+#define SCU_SFSP1_9_EPD_Pos                                   3                                                         /*!< SCU SFSP1_9: EPD Position           */
+#define SCU_SFSP1_9_EPD_Msk                                   (0x01UL << SCU_SFSP1_9_EPD_Pos)                           /*!< SCU SFSP1_9: EPD Mask               */
+#define SCU_SFSP1_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_9: EPUN Position          */
+#define SCU_SFSP1_9_EPUN_Msk                                  (0x01UL << SCU_SFSP1_9_EPUN_Pos)                          /*!< SCU SFSP1_9: EPUN Mask              */
+#define SCU_SFSP1_9_EHS_Pos                                   5                                                         /*!< SCU SFSP1_9: EHS Position           */
+#define SCU_SFSP1_9_EHS_Msk                                   (0x01UL << SCU_SFSP1_9_EHS_Pos)                           /*!< SCU SFSP1_9: EHS Mask               */
+#define SCU_SFSP1_9_EZI_Pos                                   6                                                         /*!< SCU SFSP1_9: EZI Position           */
+#define SCU_SFSP1_9_EZI_Msk                                   (0x01UL << SCU_SFSP1_9_EZI_Pos)                           /*!< SCU SFSP1_9: EZI Mask               */
+#define SCU_SFSP1_9_EHD_Pos                                   8                                                         /*!< SCU SFSP1_9: EHD Position           */
+#define SCU_SFSP1_9_EHD_Msk                                   (0x03UL << SCU_SFSP1_9_EHD_Pos)                           /*!< SCU SFSP1_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP1_10  ------------------------------------------
+#define SCU_SFSP1_10_MODE_Pos                                 0                                                         /*!< SCU SFSP1_10: MODE Position         */
+#define SCU_SFSP1_10_MODE_Msk                                 (0x07UL << SCU_SFSP1_10_MODE_Pos)                         /*!< SCU SFSP1_10: MODE Mask             */
+#define SCU_SFSP1_10_EPD_Pos                                  3                                                         /*!< SCU SFSP1_10: EPD Position          */
+#define SCU_SFSP1_10_EPD_Msk                                  (0x01UL << SCU_SFSP1_10_EPD_Pos)                          /*!< SCU SFSP1_10: EPD Mask              */
+#define SCU_SFSP1_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_10: EPUN Position         */
+#define SCU_SFSP1_10_EPUN_Msk                                 (0x01UL << SCU_SFSP1_10_EPUN_Pos)                         /*!< SCU SFSP1_10: EPUN Mask             */
+#define SCU_SFSP1_10_EHS_Pos                                  5                                                         /*!< SCU SFSP1_10: EHS Position          */
+#define SCU_SFSP1_10_EHS_Msk                                  (0x01UL << SCU_SFSP1_10_EHS_Pos)                          /*!< SCU SFSP1_10: EHS Mask              */
+#define SCU_SFSP1_10_EZI_Pos                                  6                                                         /*!< SCU SFSP1_10: EZI Position          */
+#define SCU_SFSP1_10_EZI_Msk                                  (0x01UL << SCU_SFSP1_10_EZI_Pos)                          /*!< SCU SFSP1_10: EZI Mask              */
+#define SCU_SFSP1_10_EHD_Pos                                  8                                                         /*!< SCU SFSP1_10: EHD Position          */
+#define SCU_SFSP1_10_EHD_Msk                                  (0x03UL << SCU_SFSP1_10_EHD_Pos)                          /*!< SCU SFSP1_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_11  ------------------------------------------
+#define SCU_SFSP1_11_MODE_Pos                                 0                                                         /*!< SCU SFSP1_11: MODE Position         */
+#define SCU_SFSP1_11_MODE_Msk                                 (0x07UL << SCU_SFSP1_11_MODE_Pos)                         /*!< SCU SFSP1_11: MODE Mask             */
+#define SCU_SFSP1_11_EPD_Pos                                  3                                                         /*!< SCU SFSP1_11: EPD Position          */
+#define SCU_SFSP1_11_EPD_Msk                                  (0x01UL << SCU_SFSP1_11_EPD_Pos)                          /*!< SCU SFSP1_11: EPD Mask              */
+#define SCU_SFSP1_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_11: EPUN Position         */
+#define SCU_SFSP1_11_EPUN_Msk                                 (0x01UL << SCU_SFSP1_11_EPUN_Pos)                         /*!< SCU SFSP1_11: EPUN Mask             */
+#define SCU_SFSP1_11_EHS_Pos                                  5                                                         /*!< SCU SFSP1_11: EHS Position          */
+#define SCU_SFSP1_11_EHS_Msk                                  (0x01UL << SCU_SFSP1_11_EHS_Pos)                          /*!< SCU SFSP1_11: EHS Mask              */
+#define SCU_SFSP1_11_EZI_Pos                                  6                                                         /*!< SCU SFSP1_11: EZI Position          */
+#define SCU_SFSP1_11_EZI_Msk                                  (0x01UL << SCU_SFSP1_11_EZI_Pos)                          /*!< SCU SFSP1_11: EZI Mask              */
+#define SCU_SFSP1_11_EHD_Pos                                  8                                                         /*!< SCU SFSP1_11: EHD Position          */
+#define SCU_SFSP1_11_EHD_Msk                                  (0x03UL << SCU_SFSP1_11_EHD_Pos)                          /*!< SCU SFSP1_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_12  ------------------------------------------
+#define SCU_SFSP1_12_MODE_Pos                                 0                                                         /*!< SCU SFSP1_12: MODE Position         */
+#define SCU_SFSP1_12_MODE_Msk                                 (0x07UL << SCU_SFSP1_12_MODE_Pos)                         /*!< SCU SFSP1_12: MODE Mask             */
+#define SCU_SFSP1_12_EPD_Pos                                  3                                                         /*!< SCU SFSP1_12: EPD Position          */
+#define SCU_SFSP1_12_EPD_Msk                                  (0x01UL << SCU_SFSP1_12_EPD_Pos)                          /*!< SCU SFSP1_12: EPD Mask              */
+#define SCU_SFSP1_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_12: EPUN Position         */
+#define SCU_SFSP1_12_EPUN_Msk                                 (0x01UL << SCU_SFSP1_12_EPUN_Pos)                         /*!< SCU SFSP1_12: EPUN Mask             */
+#define SCU_SFSP1_12_EHS_Pos                                  5                                                         /*!< SCU SFSP1_12: EHS Position          */
+#define SCU_SFSP1_12_EHS_Msk                                  (0x01UL << SCU_SFSP1_12_EHS_Pos)                          /*!< SCU SFSP1_12: EHS Mask              */
+#define SCU_SFSP1_12_EZI_Pos                                  6                                                         /*!< SCU SFSP1_12: EZI Position          */
+#define SCU_SFSP1_12_EZI_Msk                                  (0x01UL << SCU_SFSP1_12_EZI_Pos)                          /*!< SCU SFSP1_12: EZI Mask              */
+#define SCU_SFSP1_12_EHD_Pos                                  8                                                         /*!< SCU SFSP1_12: EHD Position          */
+#define SCU_SFSP1_12_EHD_Msk                                  (0x03UL << SCU_SFSP1_12_EHD_Pos)                          /*!< SCU SFSP1_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_13  ------------------------------------------
+#define SCU_SFSP1_13_MODE_Pos                                 0                                                         /*!< SCU SFSP1_13: MODE Position         */
+#define SCU_SFSP1_13_MODE_Msk                                 (0x07UL << SCU_SFSP1_13_MODE_Pos)                         /*!< SCU SFSP1_13: MODE Mask             */
+#define SCU_SFSP1_13_EPD_Pos                                  3                                                         /*!< SCU SFSP1_13: EPD Position          */
+#define SCU_SFSP1_13_EPD_Msk                                  (0x01UL << SCU_SFSP1_13_EPD_Pos)                          /*!< SCU SFSP1_13: EPD Mask              */
+#define SCU_SFSP1_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_13: EPUN Position         */
+#define SCU_SFSP1_13_EPUN_Msk                                 (0x01UL << SCU_SFSP1_13_EPUN_Pos)                         /*!< SCU SFSP1_13: EPUN Mask             */
+#define SCU_SFSP1_13_EHS_Pos                                  5                                                         /*!< SCU SFSP1_13: EHS Position          */
+#define SCU_SFSP1_13_EHS_Msk                                  (0x01UL << SCU_SFSP1_13_EHS_Pos)                          /*!< SCU SFSP1_13: EHS Mask              */
+#define SCU_SFSP1_13_EZI_Pos                                  6                                                         /*!< SCU SFSP1_13: EZI Position          */
+#define SCU_SFSP1_13_EZI_Msk                                  (0x01UL << SCU_SFSP1_13_EZI_Pos)                          /*!< SCU SFSP1_13: EZI Mask              */
+#define SCU_SFSP1_13_EHD_Pos                                  8                                                         /*!< SCU SFSP1_13: EHD Position          */
+#define SCU_SFSP1_13_EHD_Msk                                  (0x03UL << SCU_SFSP1_13_EHD_Pos)                          /*!< SCU SFSP1_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_14  ------------------------------------------
+#define SCU_SFSP1_14_MODE_Pos                                 0                                                         /*!< SCU SFSP1_14: MODE Position         */
+#define SCU_SFSP1_14_MODE_Msk                                 (0x07UL << SCU_SFSP1_14_MODE_Pos)                         /*!< SCU SFSP1_14: MODE Mask             */
+#define SCU_SFSP1_14_EPD_Pos                                  3                                                         /*!< SCU SFSP1_14: EPD Position          */
+#define SCU_SFSP1_14_EPD_Msk                                  (0x01UL << SCU_SFSP1_14_EPD_Pos)                          /*!< SCU SFSP1_14: EPD Mask              */
+#define SCU_SFSP1_14_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_14: EPUN Position         */
+#define SCU_SFSP1_14_EPUN_Msk                                 (0x01UL << SCU_SFSP1_14_EPUN_Pos)                         /*!< SCU SFSP1_14: EPUN Mask             */
+#define SCU_SFSP1_14_EHS_Pos                                  5                                                         /*!< SCU SFSP1_14: EHS Position          */
+#define SCU_SFSP1_14_EHS_Msk                                  (0x01UL << SCU_SFSP1_14_EHS_Pos)                          /*!< SCU SFSP1_14: EHS Mask              */
+#define SCU_SFSP1_14_EZI_Pos                                  6                                                         /*!< SCU SFSP1_14: EZI Position          */
+#define SCU_SFSP1_14_EZI_Msk                                  (0x01UL << SCU_SFSP1_14_EZI_Pos)                          /*!< SCU SFSP1_14: EZI Mask              */
+#define SCU_SFSP1_14_EHD_Pos                                  8                                                         /*!< SCU SFSP1_14: EHD Position          */
+#define SCU_SFSP1_14_EHD_Msk                                  (0x03UL << SCU_SFSP1_14_EHD_Pos)                          /*!< SCU SFSP1_14: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_15  ------------------------------------------
+#define SCU_SFSP1_15_MODE_Pos                                 0                                                         /*!< SCU SFSP1_15: MODE Position         */
+#define SCU_SFSP1_15_MODE_Msk                                 (0x07UL << SCU_SFSP1_15_MODE_Pos)                         /*!< SCU SFSP1_15: MODE Mask             */
+#define SCU_SFSP1_15_EPD_Pos                                  3                                                         /*!< SCU SFSP1_15: EPD Position          */
+#define SCU_SFSP1_15_EPD_Msk                                  (0x01UL << SCU_SFSP1_15_EPD_Pos)                          /*!< SCU SFSP1_15: EPD Mask              */
+#define SCU_SFSP1_15_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_15: EPUN Position         */
+#define SCU_SFSP1_15_EPUN_Msk                                 (0x01UL << SCU_SFSP1_15_EPUN_Pos)                         /*!< SCU SFSP1_15: EPUN Mask             */
+#define SCU_SFSP1_15_EHS_Pos                                  5                                                         /*!< SCU SFSP1_15: EHS Position          */
+#define SCU_SFSP1_15_EHS_Msk                                  (0x01UL << SCU_SFSP1_15_EHS_Pos)                          /*!< SCU SFSP1_15: EHS Mask              */
+#define SCU_SFSP1_15_EZI_Pos                                  6                                                         /*!< SCU SFSP1_15: EZI Position          */
+#define SCU_SFSP1_15_EZI_Msk                                  (0x01UL << SCU_SFSP1_15_EZI_Pos)                          /*!< SCU SFSP1_15: EZI Mask              */
+#define SCU_SFSP1_15_EHD_Pos                                  8                                                         /*!< SCU SFSP1_15: EHD Position          */
+#define SCU_SFSP1_15_EHD_Msk                                  (0x03UL << SCU_SFSP1_15_EHD_Pos)                          /*!< SCU SFSP1_15: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_16  ------------------------------------------
+#define SCU_SFSP1_16_MODE_Pos                                 0                                                         /*!< SCU SFSP1_16: MODE Position         */
+#define SCU_SFSP1_16_MODE_Msk                                 (0x07UL << SCU_SFSP1_16_MODE_Pos)                         /*!< SCU SFSP1_16: MODE Mask             */
+#define SCU_SFSP1_16_EPD_Pos                                  3                                                         /*!< SCU SFSP1_16: EPD Position          */
+#define SCU_SFSP1_16_EPD_Msk                                  (0x01UL << SCU_SFSP1_16_EPD_Pos)                          /*!< SCU SFSP1_16: EPD Mask              */
+#define SCU_SFSP1_16_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_16: EPUN Position         */
+#define SCU_SFSP1_16_EPUN_Msk                                 (0x01UL << SCU_SFSP1_16_EPUN_Pos)                         /*!< SCU SFSP1_16: EPUN Mask             */
+#define SCU_SFSP1_16_EHS_Pos                                  5                                                         /*!< SCU SFSP1_16: EHS Position          */
+#define SCU_SFSP1_16_EHS_Msk                                  (0x01UL << SCU_SFSP1_16_EHS_Pos)                          /*!< SCU SFSP1_16: EHS Mask              */
+#define SCU_SFSP1_16_EZI_Pos                                  6                                                         /*!< SCU SFSP1_16: EZI Position          */
+#define SCU_SFSP1_16_EZI_Msk                                  (0x01UL << SCU_SFSP1_16_EZI_Pos)                          /*!< SCU SFSP1_16: EZI Mask              */
+#define SCU_SFSP1_16_EHD_Pos                                  8                                                         /*!< SCU SFSP1_16: EHD Position          */
+#define SCU_SFSP1_16_EHD_Msk                                  (0x03UL << SCU_SFSP1_16_EHD_Pos)                          /*!< SCU SFSP1_16: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_17  ------------------------------------------
+#define SCU_SFSP1_17_MODE_Pos                                 0                                                         /*!< SCU SFSP1_17: MODE Position         */
+#define SCU_SFSP1_17_MODE_Msk                                 (0x07UL << SCU_SFSP1_17_MODE_Pos)                         /*!< SCU SFSP1_17: MODE Mask             */
+#define SCU_SFSP1_17_EPD_Pos                                  3                                                         /*!< SCU SFSP1_17: EPD Position          */
+#define SCU_SFSP1_17_EPD_Msk                                  (0x01UL << SCU_SFSP1_17_EPD_Pos)                          /*!< SCU SFSP1_17: EPD Mask              */
+#define SCU_SFSP1_17_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_17: EPUN Position         */
+#define SCU_SFSP1_17_EPUN_Msk                                 (0x01UL << SCU_SFSP1_17_EPUN_Pos)                         /*!< SCU SFSP1_17: EPUN Mask             */
+#define SCU_SFSP1_17_EHS_Pos                                  5                                                         /*!< SCU SFSP1_17: EHS Position          */
+#define SCU_SFSP1_17_EHS_Msk                                  (0x01UL << SCU_SFSP1_17_EHS_Pos)                          /*!< SCU SFSP1_17: EHS Mask              */
+#define SCU_SFSP1_17_EZI_Pos                                  6                                                         /*!< SCU SFSP1_17: EZI Position          */
+#define SCU_SFSP1_17_EZI_Msk                                  (0x01UL << SCU_SFSP1_17_EZI_Pos)                          /*!< SCU SFSP1_17: EZI Mask              */
+#define SCU_SFSP1_17_EHD_Pos                                  8                                                         /*!< SCU SFSP1_17: EHD Position          */
+#define SCU_SFSP1_17_EHD_Msk                                  (0x03UL << SCU_SFSP1_17_EHD_Pos)                          /*!< SCU SFSP1_17: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_18  ------------------------------------------
+#define SCU_SFSP1_18_MODE_Pos                                 0                                                         /*!< SCU SFSP1_18: MODE Position         */
+#define SCU_SFSP1_18_MODE_Msk                                 (0x07UL << SCU_SFSP1_18_MODE_Pos)                         /*!< SCU SFSP1_18: MODE Mask             */
+#define SCU_SFSP1_18_EPD_Pos                                  3                                                         /*!< SCU SFSP1_18: EPD Position          */
+#define SCU_SFSP1_18_EPD_Msk                                  (0x01UL << SCU_SFSP1_18_EPD_Pos)                          /*!< SCU SFSP1_18: EPD Mask              */
+#define SCU_SFSP1_18_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_18: EPUN Position         */
+#define SCU_SFSP1_18_EPUN_Msk                                 (0x01UL << SCU_SFSP1_18_EPUN_Pos)                         /*!< SCU SFSP1_18: EPUN Mask             */
+#define SCU_SFSP1_18_EHS_Pos                                  5                                                         /*!< SCU SFSP1_18: EHS Position          */
+#define SCU_SFSP1_18_EHS_Msk                                  (0x01UL << SCU_SFSP1_18_EHS_Pos)                          /*!< SCU SFSP1_18: EHS Mask              */
+#define SCU_SFSP1_18_EZI_Pos                                  6                                                         /*!< SCU SFSP1_18: EZI Position          */
+#define SCU_SFSP1_18_EZI_Msk                                  (0x01UL << SCU_SFSP1_18_EZI_Pos)                          /*!< SCU SFSP1_18: EZI Mask              */
+#define SCU_SFSP1_18_EHD_Pos                                  8                                                         /*!< SCU SFSP1_18: EHD Position          */
+#define SCU_SFSP1_18_EHD_Msk                                  (0x03UL << SCU_SFSP1_18_EHD_Pos)                          /*!< SCU SFSP1_18: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_19  ------------------------------------------
+#define SCU_SFSP1_19_MODE_Pos                                 0                                                         /*!< SCU SFSP1_19: MODE Position         */
+#define SCU_SFSP1_19_MODE_Msk                                 (0x07UL << SCU_SFSP1_19_MODE_Pos)                         /*!< SCU SFSP1_19: MODE Mask             */
+#define SCU_SFSP1_19_EPD_Pos                                  3                                                         /*!< SCU SFSP1_19: EPD Position          */
+#define SCU_SFSP1_19_EPD_Msk                                  (0x01UL << SCU_SFSP1_19_EPD_Pos)                          /*!< SCU SFSP1_19: EPD Mask              */
+#define SCU_SFSP1_19_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_19: EPUN Position         */
+#define SCU_SFSP1_19_EPUN_Msk                                 (0x01UL << SCU_SFSP1_19_EPUN_Pos)                         /*!< SCU SFSP1_19: EPUN Mask             */
+#define SCU_SFSP1_19_EHS_Pos                                  5                                                         /*!< SCU SFSP1_19: EHS Position          */
+#define SCU_SFSP1_19_EHS_Msk                                  (0x01UL << SCU_SFSP1_19_EHS_Pos)                          /*!< SCU SFSP1_19: EHS Mask              */
+#define SCU_SFSP1_19_EZI_Pos                                  6                                                         /*!< SCU SFSP1_19: EZI Position          */
+#define SCU_SFSP1_19_EZI_Msk                                  (0x01UL << SCU_SFSP1_19_EZI_Pos)                          /*!< SCU SFSP1_19: EZI Mask              */
+#define SCU_SFSP1_19_EHD_Pos                                  8                                                         /*!< SCU SFSP1_19: EHD Position          */
+#define SCU_SFSP1_19_EHD_Msk                                  (0x03UL << SCU_SFSP1_19_EHD_Pos)                          /*!< SCU SFSP1_19: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP1_20  ------------------------------------------
+#define SCU_SFSP1_20_MODE_Pos                                 0                                                         /*!< SCU SFSP1_20: MODE Position         */
+#define SCU_SFSP1_20_MODE_Msk                                 (0x07UL << SCU_SFSP1_20_MODE_Pos)                         /*!< SCU SFSP1_20: MODE Mask             */
+#define SCU_SFSP1_20_EPD_Pos                                  3                                                         /*!< SCU SFSP1_20: EPD Position          */
+#define SCU_SFSP1_20_EPD_Msk                                  (0x01UL << SCU_SFSP1_20_EPD_Pos)                          /*!< SCU SFSP1_20: EPD Mask              */
+#define SCU_SFSP1_20_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_20: EPUN Position         */
+#define SCU_SFSP1_20_EPUN_Msk                                 (0x01UL << SCU_SFSP1_20_EPUN_Pos)                         /*!< SCU SFSP1_20: EPUN Mask             */
+#define SCU_SFSP1_20_EHS_Pos                                  5                                                         /*!< SCU SFSP1_20: EHS Position          */
+#define SCU_SFSP1_20_EHS_Msk                                  (0x01UL << SCU_SFSP1_20_EHS_Pos)                          /*!< SCU SFSP1_20: EHS Mask              */
+#define SCU_SFSP1_20_EZI_Pos                                  6                                                         /*!< SCU SFSP1_20: EZI Position          */
+#define SCU_SFSP1_20_EZI_Msk                                  (0x01UL << SCU_SFSP1_20_EZI_Pos)                          /*!< SCU SFSP1_20: EZI Mask              */
+#define SCU_SFSP1_20_EHD_Pos                                  8                                                         /*!< SCU SFSP1_20: EHD Position          */
+#define SCU_SFSP1_20_EHD_Msk                                  (0x03UL << SCU_SFSP1_20_EHD_Pos)                          /*!< SCU SFSP1_20: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP2_0  ------------------------------------------
+#define SCU_SFSP2_0_MODE_Pos                                  0                                                         /*!< SCU SFSP2_0: MODE Position          */
+#define SCU_SFSP2_0_MODE_Msk                                  (0x07UL << SCU_SFSP2_0_MODE_Pos)                          /*!< SCU SFSP2_0: MODE Mask              */
+#define SCU_SFSP2_0_EPD_Pos                                   3                                                         /*!< SCU SFSP2_0: EPD Position           */
+#define SCU_SFSP2_0_EPD_Msk                                   (0x01UL << SCU_SFSP2_0_EPD_Pos)                           /*!< SCU SFSP2_0: EPD Mask               */
+#define SCU_SFSP2_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_0: EPUN Position          */
+#define SCU_SFSP2_0_EPUN_Msk                                  (0x01UL << SCU_SFSP2_0_EPUN_Pos)                          /*!< SCU SFSP2_0: EPUN Mask              */
+#define SCU_SFSP2_0_EHS_Pos                                   5                                                         /*!< SCU SFSP2_0: EHS Position           */
+#define SCU_SFSP2_0_EHS_Msk                                   (0x01UL << SCU_SFSP2_0_EHS_Pos)                           /*!< SCU SFSP2_0: EHS Mask               */
+#define SCU_SFSP2_0_EZI_Pos                                   6                                                         /*!< SCU SFSP2_0: EZI Position           */
+#define SCU_SFSP2_0_EZI_Msk                                   (0x01UL << SCU_SFSP2_0_EZI_Pos)                           /*!< SCU SFSP2_0: EZI Mask               */
+#define SCU_SFSP2_0_EHD_Pos                                   8                                                         /*!< SCU SFSP2_0: EHD Position           */
+#define SCU_SFSP2_0_EHD_Msk                                   (0x03UL << SCU_SFSP2_0_EHD_Pos)                           /*!< SCU SFSP2_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_1  ------------------------------------------
+#define SCU_SFSP2_1_MODE_Pos                                  0                                                         /*!< SCU SFSP2_1: MODE Position          */
+#define SCU_SFSP2_1_MODE_Msk                                  (0x07UL << SCU_SFSP2_1_MODE_Pos)                          /*!< SCU SFSP2_1: MODE Mask              */
+#define SCU_SFSP2_1_EPD_Pos                                   3                                                         /*!< SCU SFSP2_1: EPD Position           */
+#define SCU_SFSP2_1_EPD_Msk                                   (0x01UL << SCU_SFSP2_1_EPD_Pos)                           /*!< SCU SFSP2_1: EPD Mask               */
+#define SCU_SFSP2_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_1: EPUN Position          */
+#define SCU_SFSP2_1_EPUN_Msk                                  (0x01UL << SCU_SFSP2_1_EPUN_Pos)                          /*!< SCU SFSP2_1: EPUN Mask              */
+#define SCU_SFSP2_1_EHS_Pos                                   5                                                         /*!< SCU SFSP2_1: EHS Position           */
+#define SCU_SFSP2_1_EHS_Msk                                   (0x01UL << SCU_SFSP2_1_EHS_Pos)                           /*!< SCU SFSP2_1: EHS Mask               */
+#define SCU_SFSP2_1_EZI_Pos                                   6                                                         /*!< SCU SFSP2_1: EZI Position           */
+#define SCU_SFSP2_1_EZI_Msk                                   (0x01UL << SCU_SFSP2_1_EZI_Pos)                           /*!< SCU SFSP2_1: EZI Mask               */
+#define SCU_SFSP2_1_EHD_Pos                                   8                                                         /*!< SCU SFSP2_1: EHD Position           */
+#define SCU_SFSP2_1_EHD_Msk                                   (0x03UL << SCU_SFSP2_1_EHD_Pos)                           /*!< SCU SFSP2_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_2  ------------------------------------------
+#define SCU_SFSP2_2_MODE_Pos                                  0                                                         /*!< SCU SFSP2_2: MODE Position          */
+#define SCU_SFSP2_2_MODE_Msk                                  (0x07UL << SCU_SFSP2_2_MODE_Pos)                          /*!< SCU SFSP2_2: MODE Mask              */
+#define SCU_SFSP2_2_EPD_Pos                                   3                                                         /*!< SCU SFSP2_2: EPD Position           */
+#define SCU_SFSP2_2_EPD_Msk                                   (0x01UL << SCU_SFSP2_2_EPD_Pos)                           /*!< SCU SFSP2_2: EPD Mask               */
+#define SCU_SFSP2_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_2: EPUN Position          */
+#define SCU_SFSP2_2_EPUN_Msk                                  (0x01UL << SCU_SFSP2_2_EPUN_Pos)                          /*!< SCU SFSP2_2: EPUN Mask              */
+#define SCU_SFSP2_2_EHS_Pos                                   5                                                         /*!< SCU SFSP2_2: EHS Position           */
+#define SCU_SFSP2_2_EHS_Msk                                   (0x01UL << SCU_SFSP2_2_EHS_Pos)                           /*!< SCU SFSP2_2: EHS Mask               */
+#define SCU_SFSP2_2_EZI_Pos                                   6                                                         /*!< SCU SFSP2_2: EZI Position           */
+#define SCU_SFSP2_2_EZI_Msk                                   (0x01UL << SCU_SFSP2_2_EZI_Pos)                           /*!< SCU SFSP2_2: EZI Mask               */
+#define SCU_SFSP2_2_EHD_Pos                                   8                                                         /*!< SCU SFSP2_2: EHD Position           */
+#define SCU_SFSP2_2_EHD_Msk                                   (0x03UL << SCU_SFSP2_2_EHD_Pos)                           /*!< SCU SFSP2_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_3  ------------------------------------------
+#define SCU_SFSP2_3_MODE_Pos                                  0                                                         /*!< SCU SFSP2_3: MODE Position          */
+#define SCU_SFSP2_3_MODE_Msk                                  (0x07UL << SCU_SFSP2_3_MODE_Pos)                          /*!< SCU SFSP2_3: MODE Mask              */
+#define SCU_SFSP2_3_EPD_Pos                                   3                                                         /*!< SCU SFSP2_3: EPD Position           */
+#define SCU_SFSP2_3_EPD_Msk                                   (0x01UL << SCU_SFSP2_3_EPD_Pos)                           /*!< SCU SFSP2_3: EPD Mask               */
+#define SCU_SFSP2_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_3: EPUN Position          */
+#define SCU_SFSP2_3_EPUN_Msk                                  (0x01UL << SCU_SFSP2_3_EPUN_Pos)                          /*!< SCU SFSP2_3: EPUN Mask              */
+#define SCU_SFSP2_3_EHS_Pos                                   5                                                         /*!< SCU SFSP2_3: EHS Position           */
+#define SCU_SFSP2_3_EHS_Msk                                   (0x01UL << SCU_SFSP2_3_EHS_Pos)                           /*!< SCU SFSP2_3: EHS Mask               */
+#define SCU_SFSP2_3_EZI_Pos                                   6                                                         /*!< SCU SFSP2_3: EZI Position           */
+#define SCU_SFSP2_3_EZI_Msk                                   (0x01UL << SCU_SFSP2_3_EZI_Pos)                           /*!< SCU SFSP2_3: EZI Mask               */
+#define SCU_SFSP2_3_EHD_Pos                                   8                                                         /*!< SCU SFSP2_3: EHD Position           */
+#define SCU_SFSP2_3_EHD_Msk                                   (0x03UL << SCU_SFSP2_3_EHD_Pos)                           /*!< SCU SFSP2_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_4  ------------------------------------------
+#define SCU_SFSP2_4_MODE_Pos                                  0                                                         /*!< SCU SFSP2_4: MODE Position          */
+#define SCU_SFSP2_4_MODE_Msk                                  (0x07UL << SCU_SFSP2_4_MODE_Pos)                          /*!< SCU SFSP2_4: MODE Mask              */
+#define SCU_SFSP2_4_EPD_Pos                                   3                                                         /*!< SCU SFSP2_4: EPD Position           */
+#define SCU_SFSP2_4_EPD_Msk                                   (0x01UL << SCU_SFSP2_4_EPD_Pos)                           /*!< SCU SFSP2_4: EPD Mask               */
+#define SCU_SFSP2_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_4: EPUN Position          */
+#define SCU_SFSP2_4_EPUN_Msk                                  (0x01UL << SCU_SFSP2_4_EPUN_Pos)                          /*!< SCU SFSP2_4: EPUN Mask              */
+#define SCU_SFSP2_4_EHS_Pos                                   5                                                         /*!< SCU SFSP2_4: EHS Position           */
+#define SCU_SFSP2_4_EHS_Msk                                   (0x01UL << SCU_SFSP2_4_EHS_Pos)                           /*!< SCU SFSP2_4: EHS Mask               */
+#define SCU_SFSP2_4_EZI_Pos                                   6                                                         /*!< SCU SFSP2_4: EZI Position           */
+#define SCU_SFSP2_4_EZI_Msk                                   (0x01UL << SCU_SFSP2_4_EZI_Pos)                           /*!< SCU SFSP2_4: EZI Mask               */
+#define SCU_SFSP2_4_EHD_Pos                                   8                                                         /*!< SCU SFSP2_4: EHD Position           */
+#define SCU_SFSP2_4_EHD_Msk                                   (0x03UL << SCU_SFSP2_4_EHD_Pos)                           /*!< SCU SFSP2_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_5  ------------------------------------------
+#define SCU_SFSP2_5_MODE_Pos                                  0                                                         /*!< SCU SFSP2_5: MODE Position          */
+#define SCU_SFSP2_5_MODE_Msk                                  (0x07UL << SCU_SFSP2_5_MODE_Pos)                          /*!< SCU SFSP2_5: MODE Mask              */
+#define SCU_SFSP2_5_EPD_Pos                                   3                                                         /*!< SCU SFSP2_5: EPD Position           */
+#define SCU_SFSP2_5_EPD_Msk                                   (0x01UL << SCU_SFSP2_5_EPD_Pos)                           /*!< SCU SFSP2_5: EPD Mask               */
+#define SCU_SFSP2_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_5: EPUN Position          */
+#define SCU_SFSP2_5_EPUN_Msk                                  (0x01UL << SCU_SFSP2_5_EPUN_Pos)                          /*!< SCU SFSP2_5: EPUN Mask              */
+#define SCU_SFSP2_5_EHS_Pos                                   5                                                         /*!< SCU SFSP2_5: EHS Position           */
+#define SCU_SFSP2_5_EHS_Msk                                   (0x01UL << SCU_SFSP2_5_EHS_Pos)                           /*!< SCU SFSP2_5: EHS Mask               */
+#define SCU_SFSP2_5_EZI_Pos                                   6                                                         /*!< SCU SFSP2_5: EZI Position           */
+#define SCU_SFSP2_5_EZI_Msk                                   (0x01UL << SCU_SFSP2_5_EZI_Pos)                           /*!< SCU SFSP2_5: EZI Mask               */
+#define SCU_SFSP2_5_EHD_Pos                                   8                                                         /*!< SCU SFSP2_5: EHD Position           */
+#define SCU_SFSP2_5_EHD_Msk                                   (0x03UL << SCU_SFSP2_5_EHD_Pos)                           /*!< SCU SFSP2_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_6  ------------------------------------------
+#define SCU_SFSP2_6_MODE_Pos                                  0                                                         /*!< SCU SFSP2_6: MODE Position          */
+#define SCU_SFSP2_6_MODE_Msk                                  (0x07UL << SCU_SFSP2_6_MODE_Pos)                          /*!< SCU SFSP2_6: MODE Mask              */
+#define SCU_SFSP2_6_EPD_Pos                                   3                                                         /*!< SCU SFSP2_6: EPD Position           */
+#define SCU_SFSP2_6_EPD_Msk                                   (0x01UL << SCU_SFSP2_6_EPD_Pos)                           /*!< SCU SFSP2_6: EPD Mask               */
+#define SCU_SFSP2_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_6: EPUN Position          */
+#define SCU_SFSP2_6_EPUN_Msk                                  (0x01UL << SCU_SFSP2_6_EPUN_Pos)                          /*!< SCU SFSP2_6: EPUN Mask              */
+#define SCU_SFSP2_6_EHS_Pos                                   5                                                         /*!< SCU SFSP2_6: EHS Position           */
+#define SCU_SFSP2_6_EHS_Msk                                   (0x01UL << SCU_SFSP2_6_EHS_Pos)                           /*!< SCU SFSP2_6: EHS Mask               */
+#define SCU_SFSP2_6_EZI_Pos                                   6                                                         /*!< SCU SFSP2_6: EZI Position           */
+#define SCU_SFSP2_6_EZI_Msk                                   (0x01UL << SCU_SFSP2_6_EZI_Pos)                           /*!< SCU SFSP2_6: EZI Mask               */
+#define SCU_SFSP2_6_EHD_Pos                                   8                                                         /*!< SCU SFSP2_6: EHD Position           */
+#define SCU_SFSP2_6_EHD_Msk                                   (0x03UL << SCU_SFSP2_6_EHD_Pos)                           /*!< SCU SFSP2_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_7  ------------------------------------------
+#define SCU_SFSP2_7_MODE_Pos                                  0                                                         /*!< SCU SFSP2_7: MODE Position          */
+#define SCU_SFSP2_7_MODE_Msk                                  (0x07UL << SCU_SFSP2_7_MODE_Pos)                          /*!< SCU SFSP2_7: MODE Mask              */
+#define SCU_SFSP2_7_EPD_Pos                                   3                                                         /*!< SCU SFSP2_7: EPD Position           */
+#define SCU_SFSP2_7_EPD_Msk                                   (0x01UL << SCU_SFSP2_7_EPD_Pos)                           /*!< SCU SFSP2_7: EPD Mask               */
+#define SCU_SFSP2_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_7: EPUN Position          */
+#define SCU_SFSP2_7_EPUN_Msk                                  (0x01UL << SCU_SFSP2_7_EPUN_Pos)                          /*!< SCU SFSP2_7: EPUN Mask              */
+#define SCU_SFSP2_7_EHS_Pos                                   5                                                         /*!< SCU SFSP2_7: EHS Position           */
+#define SCU_SFSP2_7_EHS_Msk                                   (0x01UL << SCU_SFSP2_7_EHS_Pos)                           /*!< SCU SFSP2_7: EHS Mask               */
+#define SCU_SFSP2_7_EZI_Pos                                   6                                                         /*!< SCU SFSP2_7: EZI Position           */
+#define SCU_SFSP2_7_EZI_Msk                                   (0x01UL << SCU_SFSP2_7_EZI_Pos)                           /*!< SCU SFSP2_7: EZI Mask               */
+#define SCU_SFSP2_7_EHD_Pos                                   8                                                         /*!< SCU SFSP2_7: EHD Position           */
+#define SCU_SFSP2_7_EHD_Msk                                   (0x03UL << SCU_SFSP2_7_EHD_Pos)                           /*!< SCU SFSP2_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_8  ------------------------------------------
+#define SCU_SFSP2_8_MODE_Pos                                  0                                                         /*!< SCU SFSP2_8: MODE Position          */
+#define SCU_SFSP2_8_MODE_Msk                                  (0x07UL << SCU_SFSP2_8_MODE_Pos)                          /*!< SCU SFSP2_8: MODE Mask              */
+#define SCU_SFSP2_8_EPD_Pos                                   3                                                         /*!< SCU SFSP2_8: EPD Position           */
+#define SCU_SFSP2_8_EPD_Msk                                   (0x01UL << SCU_SFSP2_8_EPD_Pos)                           /*!< SCU SFSP2_8: EPD Mask               */
+#define SCU_SFSP2_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_8: EPUN Position          */
+#define SCU_SFSP2_8_EPUN_Msk                                  (0x01UL << SCU_SFSP2_8_EPUN_Pos)                          /*!< SCU SFSP2_8: EPUN Mask              */
+#define SCU_SFSP2_8_EHS_Pos                                   5                                                         /*!< SCU SFSP2_8: EHS Position           */
+#define SCU_SFSP2_8_EHS_Msk                                   (0x01UL << SCU_SFSP2_8_EHS_Pos)                           /*!< SCU SFSP2_8: EHS Mask               */
+#define SCU_SFSP2_8_EZI_Pos                                   6                                                         /*!< SCU SFSP2_8: EZI Position           */
+#define SCU_SFSP2_8_EZI_Msk                                   (0x01UL << SCU_SFSP2_8_EZI_Pos)                           /*!< SCU SFSP2_8: EZI Mask               */
+#define SCU_SFSP2_8_EHD_Pos                                   8                                                         /*!< SCU SFSP2_8: EHD Position           */
+#define SCU_SFSP2_8_EHD_Msk                                   (0x03UL << SCU_SFSP2_8_EHD_Pos)                           /*!< SCU SFSP2_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP2_9  ------------------------------------------
+#define SCU_SFSP2_9_MODE_Pos                                  0                                                         /*!< SCU SFSP2_9: MODE Position          */
+#define SCU_SFSP2_9_MODE_Msk                                  (0x07UL << SCU_SFSP2_9_MODE_Pos)                          /*!< SCU SFSP2_9: MODE Mask              */
+#define SCU_SFSP2_9_EPD_Pos                                   3                                                         /*!< SCU SFSP2_9: EPD Position           */
+#define SCU_SFSP2_9_EPD_Msk                                   (0x01UL << SCU_SFSP2_9_EPD_Pos)                           /*!< SCU SFSP2_9: EPD Mask               */
+#define SCU_SFSP2_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_9: EPUN Position          */
+#define SCU_SFSP2_9_EPUN_Msk                                  (0x01UL << SCU_SFSP2_9_EPUN_Pos)                          /*!< SCU SFSP2_9: EPUN Mask              */
+#define SCU_SFSP2_9_EHS_Pos                                   5                                                         /*!< SCU SFSP2_9: EHS Position           */
+#define SCU_SFSP2_9_EHS_Msk                                   (0x01UL << SCU_SFSP2_9_EHS_Pos)                           /*!< SCU SFSP2_9: EHS Mask               */
+#define SCU_SFSP2_9_EZI_Pos                                   6                                                         /*!< SCU SFSP2_9: EZI Position           */
+#define SCU_SFSP2_9_EZI_Msk                                   (0x01UL << SCU_SFSP2_9_EZI_Pos)                           /*!< SCU SFSP2_9: EZI Mask               */
+#define SCU_SFSP2_9_EHD_Pos                                   8                                                         /*!< SCU SFSP2_9: EHD Position           */
+#define SCU_SFSP2_9_EHD_Msk                                   (0x03UL << SCU_SFSP2_9_EHD_Pos)                           /*!< SCU SFSP2_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP2_10  ------------------------------------------
+#define SCU_SFSP2_10_MODE_Pos                                 0                                                         /*!< SCU SFSP2_10: MODE Position         */
+#define SCU_SFSP2_10_MODE_Msk                                 (0x07UL << SCU_SFSP2_10_MODE_Pos)                         /*!< SCU SFSP2_10: MODE Mask             */
+#define SCU_SFSP2_10_EPD_Pos                                  3                                                         /*!< SCU SFSP2_10: EPD Position          */
+#define SCU_SFSP2_10_EPD_Msk                                  (0x01UL << SCU_SFSP2_10_EPD_Pos)                          /*!< SCU SFSP2_10: EPD Mask              */
+#define SCU_SFSP2_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_10: EPUN Position         */
+#define SCU_SFSP2_10_EPUN_Msk                                 (0x01UL << SCU_SFSP2_10_EPUN_Pos)                         /*!< SCU SFSP2_10: EPUN Mask             */
+#define SCU_SFSP2_10_EHS_Pos                                  5                                                         /*!< SCU SFSP2_10: EHS Position          */
+#define SCU_SFSP2_10_EHS_Msk                                  (0x01UL << SCU_SFSP2_10_EHS_Pos)                          /*!< SCU SFSP2_10: EHS Mask              */
+#define SCU_SFSP2_10_EZI_Pos                                  6                                                         /*!< SCU SFSP2_10: EZI Position          */
+#define SCU_SFSP2_10_EZI_Msk                                  (0x01UL << SCU_SFSP2_10_EZI_Pos)                          /*!< SCU SFSP2_10: EZI Mask              */
+#define SCU_SFSP2_10_EHD_Pos                                  8                                                         /*!< SCU SFSP2_10: EHD Position          */
+#define SCU_SFSP2_10_EHD_Msk                                  (0x03UL << SCU_SFSP2_10_EHD_Pos)                          /*!< SCU SFSP2_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP2_11  ------------------------------------------
+#define SCU_SFSP2_11_MODE_Pos                                 0                                                         /*!< SCU SFSP2_11: MODE Position         */
+#define SCU_SFSP2_11_MODE_Msk                                 (0x07UL << SCU_SFSP2_11_MODE_Pos)                         /*!< SCU SFSP2_11: MODE Mask             */
+#define SCU_SFSP2_11_EPD_Pos                                  3                                                         /*!< SCU SFSP2_11: EPD Position          */
+#define SCU_SFSP2_11_EPD_Msk                                  (0x01UL << SCU_SFSP2_11_EPD_Pos)                          /*!< SCU SFSP2_11: EPD Mask              */
+#define SCU_SFSP2_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_11: EPUN Position         */
+#define SCU_SFSP2_11_EPUN_Msk                                 (0x01UL << SCU_SFSP2_11_EPUN_Pos)                         /*!< SCU SFSP2_11: EPUN Mask             */
+#define SCU_SFSP2_11_EHS_Pos                                  5                                                         /*!< SCU SFSP2_11: EHS Position          */
+#define SCU_SFSP2_11_EHS_Msk                                  (0x01UL << SCU_SFSP2_11_EHS_Pos)                          /*!< SCU SFSP2_11: EHS Mask              */
+#define SCU_SFSP2_11_EZI_Pos                                  6                                                         /*!< SCU SFSP2_11: EZI Position          */
+#define SCU_SFSP2_11_EZI_Msk                                  (0x01UL << SCU_SFSP2_11_EZI_Pos)                          /*!< SCU SFSP2_11: EZI Mask              */
+#define SCU_SFSP2_11_EHD_Pos                                  8                                                         /*!< SCU SFSP2_11: EHD Position          */
+#define SCU_SFSP2_11_EHD_Msk                                  (0x03UL << SCU_SFSP2_11_EHD_Pos)                          /*!< SCU SFSP2_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP2_12  ------------------------------------------
+#define SCU_SFSP2_12_MODE_Pos                                 0                                                         /*!< SCU SFSP2_12: MODE Position         */
+#define SCU_SFSP2_12_MODE_Msk                                 (0x07UL << SCU_SFSP2_12_MODE_Pos)                         /*!< SCU SFSP2_12: MODE Mask             */
+#define SCU_SFSP2_12_EPD_Pos                                  3                                                         /*!< SCU SFSP2_12: EPD Position          */
+#define SCU_SFSP2_12_EPD_Msk                                  (0x01UL << SCU_SFSP2_12_EPD_Pos)                          /*!< SCU SFSP2_12: EPD Mask              */
+#define SCU_SFSP2_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_12: EPUN Position         */
+#define SCU_SFSP2_12_EPUN_Msk                                 (0x01UL << SCU_SFSP2_12_EPUN_Pos)                         /*!< SCU SFSP2_12: EPUN Mask             */
+#define SCU_SFSP2_12_EHS_Pos                                  5                                                         /*!< SCU SFSP2_12: EHS Position          */
+#define SCU_SFSP2_12_EHS_Msk                                  (0x01UL << SCU_SFSP2_12_EHS_Pos)                          /*!< SCU SFSP2_12: EHS Mask              */
+#define SCU_SFSP2_12_EZI_Pos                                  6                                                         /*!< SCU SFSP2_12: EZI Position          */
+#define SCU_SFSP2_12_EZI_Msk                                  (0x01UL << SCU_SFSP2_12_EZI_Pos)                          /*!< SCU SFSP2_12: EZI Mask              */
+#define SCU_SFSP2_12_EHD_Pos                                  8                                                         /*!< SCU SFSP2_12: EHD Position          */
+#define SCU_SFSP2_12_EHD_Msk                                  (0x03UL << SCU_SFSP2_12_EHD_Pos)                          /*!< SCU SFSP2_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP2_13  ------------------------------------------
+#define SCU_SFSP2_13_MODE_Pos                                 0                                                         /*!< SCU SFSP2_13: MODE Position         */
+#define SCU_SFSP2_13_MODE_Msk                                 (0x07UL << SCU_SFSP2_13_MODE_Pos)                         /*!< SCU SFSP2_13: MODE Mask             */
+#define SCU_SFSP2_13_EPD_Pos                                  3                                                         /*!< SCU SFSP2_13: EPD Position          */
+#define SCU_SFSP2_13_EPD_Msk                                  (0x01UL << SCU_SFSP2_13_EPD_Pos)                          /*!< SCU SFSP2_13: EPD Mask              */
+#define SCU_SFSP2_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_13: EPUN Position         */
+#define SCU_SFSP2_13_EPUN_Msk                                 (0x01UL << SCU_SFSP2_13_EPUN_Pos)                         /*!< SCU SFSP2_13: EPUN Mask             */
+#define SCU_SFSP2_13_EHS_Pos                                  5                                                         /*!< SCU SFSP2_13: EHS Position          */
+#define SCU_SFSP2_13_EHS_Msk                                  (0x01UL << SCU_SFSP2_13_EHS_Pos)                          /*!< SCU SFSP2_13: EHS Mask              */
+#define SCU_SFSP2_13_EZI_Pos                                  6                                                         /*!< SCU SFSP2_13: EZI Position          */
+#define SCU_SFSP2_13_EZI_Msk                                  (0x01UL << SCU_SFSP2_13_EZI_Pos)                          /*!< SCU SFSP2_13: EZI Mask              */
+#define SCU_SFSP2_13_EHD_Pos                                  8                                                         /*!< SCU SFSP2_13: EHD Position          */
+#define SCU_SFSP2_13_EHD_Msk                                  (0x03UL << SCU_SFSP2_13_EHD_Pos)                          /*!< SCU SFSP2_13: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP3_0  ------------------------------------------
+#define SCU_SFSP3_0_MODE_Pos                                  0                                                         /*!< SCU SFSP3_0: MODE Position          */
+#define SCU_SFSP3_0_MODE_Msk                                  (0x07UL << SCU_SFSP3_0_MODE_Pos)                          /*!< SCU SFSP3_0: MODE Mask              */
+#define SCU_SFSP3_0_EPD_Pos                                   3                                                         /*!< SCU SFSP3_0: EPD Position           */
+#define SCU_SFSP3_0_EPD_Msk                                   (0x01UL << SCU_SFSP3_0_EPD_Pos)                           /*!< SCU SFSP3_0: EPD Mask               */
+#define SCU_SFSP3_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_0: EPUN Position          */
+#define SCU_SFSP3_0_EPUN_Msk                                  (0x01UL << SCU_SFSP3_0_EPUN_Pos)                          /*!< SCU SFSP3_0: EPUN Mask              */
+#define SCU_SFSP3_0_EHS_Pos                                   5                                                         /*!< SCU SFSP3_0: EHS Position           */
+#define SCU_SFSP3_0_EHS_Msk                                   (0x01UL << SCU_SFSP3_0_EHS_Pos)                           /*!< SCU SFSP3_0: EHS Mask               */
+#define SCU_SFSP3_0_EZI_Pos                                   6                                                         /*!< SCU SFSP3_0: EZI Position           */
+#define SCU_SFSP3_0_EZI_Msk                                   (0x01UL << SCU_SFSP3_0_EZI_Pos)                           /*!< SCU SFSP3_0: EZI Mask               */
+#define SCU_SFSP3_0_EHD_Pos                                   8                                                         /*!< SCU SFSP3_0: EHD Position           */
+#define SCU_SFSP3_0_EHD_Msk                                   (0x03UL << SCU_SFSP3_0_EHD_Pos)                           /*!< SCU SFSP3_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_1  ------------------------------------------
+#define SCU_SFSP3_1_MODE_Pos                                  0                                                         /*!< SCU SFSP3_1: MODE Position          */
+#define SCU_SFSP3_1_MODE_Msk                                  (0x07UL << SCU_SFSP3_1_MODE_Pos)                          /*!< SCU SFSP3_1: MODE Mask              */
+#define SCU_SFSP3_1_EPD_Pos                                   3                                                         /*!< SCU SFSP3_1: EPD Position           */
+#define SCU_SFSP3_1_EPD_Msk                                   (0x01UL << SCU_SFSP3_1_EPD_Pos)                           /*!< SCU SFSP3_1: EPD Mask               */
+#define SCU_SFSP3_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_1: EPUN Position          */
+#define SCU_SFSP3_1_EPUN_Msk                                  (0x01UL << SCU_SFSP3_1_EPUN_Pos)                          /*!< SCU SFSP3_1: EPUN Mask              */
+#define SCU_SFSP3_1_EHS_Pos                                   5                                                         /*!< SCU SFSP3_1: EHS Position           */
+#define SCU_SFSP3_1_EHS_Msk                                   (0x01UL << SCU_SFSP3_1_EHS_Pos)                           /*!< SCU SFSP3_1: EHS Mask               */
+#define SCU_SFSP3_1_EZI_Pos                                   6                                                         /*!< SCU SFSP3_1: EZI Position           */
+#define SCU_SFSP3_1_EZI_Msk                                   (0x01UL << SCU_SFSP3_1_EZI_Pos)                           /*!< SCU SFSP3_1: EZI Mask               */
+#define SCU_SFSP3_1_EHD_Pos                                   8                                                         /*!< SCU SFSP3_1: EHD Position           */
+#define SCU_SFSP3_1_EHD_Msk                                   (0x03UL << SCU_SFSP3_1_EHD_Pos)                           /*!< SCU SFSP3_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_2  ------------------------------------------
+#define SCU_SFSP3_2_MODE_Pos                                  0                                                         /*!< SCU SFSP3_2: MODE Position          */
+#define SCU_SFSP3_2_MODE_Msk                                  (0x07UL << SCU_SFSP3_2_MODE_Pos)                          /*!< SCU SFSP3_2: MODE Mask              */
+#define SCU_SFSP3_2_EPD_Pos                                   3                                                         /*!< SCU SFSP3_2: EPD Position           */
+#define SCU_SFSP3_2_EPD_Msk                                   (0x01UL << SCU_SFSP3_2_EPD_Pos)                           /*!< SCU SFSP3_2: EPD Mask               */
+#define SCU_SFSP3_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_2: EPUN Position          */
+#define SCU_SFSP3_2_EPUN_Msk                                  (0x01UL << SCU_SFSP3_2_EPUN_Pos)                          /*!< SCU SFSP3_2: EPUN Mask              */
+#define SCU_SFSP3_2_EHS_Pos                                   5                                                         /*!< SCU SFSP3_2: EHS Position           */
+#define SCU_SFSP3_2_EHS_Msk                                   (0x01UL << SCU_SFSP3_2_EHS_Pos)                           /*!< SCU SFSP3_2: EHS Mask               */
+#define SCU_SFSP3_2_EZI_Pos                                   6                                                         /*!< SCU SFSP3_2: EZI Position           */
+#define SCU_SFSP3_2_EZI_Msk                                   (0x01UL << SCU_SFSP3_2_EZI_Pos)                           /*!< SCU SFSP3_2: EZI Mask               */
+#define SCU_SFSP3_2_EHD_Pos                                   8                                                         /*!< SCU SFSP3_2: EHD Position           */
+#define SCU_SFSP3_2_EHD_Msk                                   (0x03UL << SCU_SFSP3_2_EHD_Pos)                           /*!< SCU SFSP3_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_3  ------------------------------------------
+#define SCU_SFSP3_3_MODE_Pos                                  0                                                         /*!< SCU SFSP3_3: MODE Position          */
+#define SCU_SFSP3_3_MODE_Msk                                  (0x07UL << SCU_SFSP3_3_MODE_Pos)                          /*!< SCU SFSP3_3: MODE Mask              */
+#define SCU_SFSP3_3_EPD_Pos                                   3                                                         /*!< SCU SFSP3_3: EPD Position           */
+#define SCU_SFSP3_3_EPD_Msk                                   (0x01UL << SCU_SFSP3_3_EPD_Pos)                           /*!< SCU SFSP3_3: EPD Mask               */
+#define SCU_SFSP3_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_3: EPUN Position          */
+#define SCU_SFSP3_3_EPUN_Msk                                  (0x01UL << SCU_SFSP3_3_EPUN_Pos)                          /*!< SCU SFSP3_3: EPUN Mask              */
+#define SCU_SFSP3_3_EHS_Pos                                   5                                                         /*!< SCU SFSP3_3: EHS Position           */
+#define SCU_SFSP3_3_EHS_Msk                                   (0x01UL << SCU_SFSP3_3_EHS_Pos)                           /*!< SCU SFSP3_3: EHS Mask               */
+#define SCU_SFSP3_3_EZI_Pos                                   6                                                         /*!< SCU SFSP3_3: EZI Position           */
+#define SCU_SFSP3_3_EZI_Msk                                   (0x01UL << SCU_SFSP3_3_EZI_Pos)                           /*!< SCU SFSP3_3: EZI Mask               */
+#define SCU_SFSP3_3_EHD_Pos                                   8                                                         /*!< SCU SFSP3_3: EHD Position           */
+#define SCU_SFSP3_3_EHD_Msk                                   (0x03UL << SCU_SFSP3_3_EHD_Pos)                           /*!< SCU SFSP3_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_4  ------------------------------------------
+#define SCU_SFSP3_4_MODE_Pos                                  0                                                         /*!< SCU SFSP3_4: MODE Position          */
+#define SCU_SFSP3_4_MODE_Msk                                  (0x07UL << SCU_SFSP3_4_MODE_Pos)                          /*!< SCU SFSP3_4: MODE Mask              */
+#define SCU_SFSP3_4_EPD_Pos                                   3                                                         /*!< SCU SFSP3_4: EPD Position           */
+#define SCU_SFSP3_4_EPD_Msk                                   (0x01UL << SCU_SFSP3_4_EPD_Pos)                           /*!< SCU SFSP3_4: EPD Mask               */
+#define SCU_SFSP3_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_4: EPUN Position          */
+#define SCU_SFSP3_4_EPUN_Msk                                  (0x01UL << SCU_SFSP3_4_EPUN_Pos)                          /*!< SCU SFSP3_4: EPUN Mask              */
+#define SCU_SFSP3_4_EHS_Pos                                   5                                                         /*!< SCU SFSP3_4: EHS Position           */
+#define SCU_SFSP3_4_EHS_Msk                                   (0x01UL << SCU_SFSP3_4_EHS_Pos)                           /*!< SCU SFSP3_4: EHS Mask               */
+#define SCU_SFSP3_4_EZI_Pos                                   6                                                         /*!< SCU SFSP3_4: EZI Position           */
+#define SCU_SFSP3_4_EZI_Msk                                   (0x01UL << SCU_SFSP3_4_EZI_Pos)                           /*!< SCU SFSP3_4: EZI Mask               */
+#define SCU_SFSP3_4_EHD_Pos                                   8                                                         /*!< SCU SFSP3_4: EHD Position           */
+#define SCU_SFSP3_4_EHD_Msk                                   (0x03UL << SCU_SFSP3_4_EHD_Pos)                           /*!< SCU SFSP3_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_5  ------------------------------------------
+#define SCU_SFSP3_5_MODE_Pos                                  0                                                         /*!< SCU SFSP3_5: MODE Position          */
+#define SCU_SFSP3_5_MODE_Msk                                  (0x07UL << SCU_SFSP3_5_MODE_Pos)                          /*!< SCU SFSP3_5: MODE Mask              */
+#define SCU_SFSP3_5_EPD_Pos                                   3                                                         /*!< SCU SFSP3_5: EPD Position           */
+#define SCU_SFSP3_5_EPD_Msk                                   (0x01UL << SCU_SFSP3_5_EPD_Pos)                           /*!< SCU SFSP3_5: EPD Mask               */
+#define SCU_SFSP3_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_5: EPUN Position          */
+#define SCU_SFSP3_5_EPUN_Msk                                  (0x01UL << SCU_SFSP3_5_EPUN_Pos)                          /*!< SCU SFSP3_5: EPUN Mask              */
+#define SCU_SFSP3_5_EHS_Pos                                   5                                                         /*!< SCU SFSP3_5: EHS Position           */
+#define SCU_SFSP3_5_EHS_Msk                                   (0x01UL << SCU_SFSP3_5_EHS_Pos)                           /*!< SCU SFSP3_5: EHS Mask               */
+#define SCU_SFSP3_5_EZI_Pos                                   6                                                         /*!< SCU SFSP3_5: EZI Position           */
+#define SCU_SFSP3_5_EZI_Msk                                   (0x01UL << SCU_SFSP3_5_EZI_Pos)                           /*!< SCU SFSP3_5: EZI Mask               */
+#define SCU_SFSP3_5_EHD_Pos                                   8                                                         /*!< SCU SFSP3_5: EHD Position           */
+#define SCU_SFSP3_5_EHD_Msk                                   (0x03UL << SCU_SFSP3_5_EHD_Pos)                           /*!< SCU SFSP3_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_6  ------------------------------------------
+#define SCU_SFSP3_6_MODE_Pos                                  0                                                         /*!< SCU SFSP3_6: MODE Position          */
+#define SCU_SFSP3_6_MODE_Msk                                  (0x07UL << SCU_SFSP3_6_MODE_Pos)                          /*!< SCU SFSP3_6: MODE Mask              */
+#define SCU_SFSP3_6_EPD_Pos                                   3                                                         /*!< SCU SFSP3_6: EPD Position           */
+#define SCU_SFSP3_6_EPD_Msk                                   (0x01UL << SCU_SFSP3_6_EPD_Pos)                           /*!< SCU SFSP3_6: EPD Mask               */
+#define SCU_SFSP3_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_6: EPUN Position          */
+#define SCU_SFSP3_6_EPUN_Msk                                  (0x01UL << SCU_SFSP3_6_EPUN_Pos)                          /*!< SCU SFSP3_6: EPUN Mask              */
+#define SCU_SFSP3_6_EHS_Pos                                   5                                                         /*!< SCU SFSP3_6: EHS Position           */
+#define SCU_SFSP3_6_EHS_Msk                                   (0x01UL << SCU_SFSP3_6_EHS_Pos)                           /*!< SCU SFSP3_6: EHS Mask               */
+#define SCU_SFSP3_6_EZI_Pos                                   6                                                         /*!< SCU SFSP3_6: EZI Position           */
+#define SCU_SFSP3_6_EZI_Msk                                   (0x01UL << SCU_SFSP3_6_EZI_Pos)                           /*!< SCU SFSP3_6: EZI Mask               */
+#define SCU_SFSP3_6_EHD_Pos                                   8                                                         /*!< SCU SFSP3_6: EHD Position           */
+#define SCU_SFSP3_6_EHD_Msk                                   (0x03UL << SCU_SFSP3_6_EHD_Pos)                           /*!< SCU SFSP3_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_7  ------------------------------------------
+#define SCU_SFSP3_7_MODE_Pos                                  0                                                         /*!< SCU SFSP3_7: MODE Position          */
+#define SCU_SFSP3_7_MODE_Msk                                  (0x07UL << SCU_SFSP3_7_MODE_Pos)                          /*!< SCU SFSP3_7: MODE Mask              */
+#define SCU_SFSP3_7_EPD_Pos                                   3                                                         /*!< SCU SFSP3_7: EPD Position           */
+#define SCU_SFSP3_7_EPD_Msk                                   (0x01UL << SCU_SFSP3_7_EPD_Pos)                           /*!< SCU SFSP3_7: EPD Mask               */
+#define SCU_SFSP3_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_7: EPUN Position          */
+#define SCU_SFSP3_7_EPUN_Msk                                  (0x01UL << SCU_SFSP3_7_EPUN_Pos)                          /*!< SCU SFSP3_7: EPUN Mask              */
+#define SCU_SFSP3_7_EHS_Pos                                   5                                                         /*!< SCU SFSP3_7: EHS Position           */
+#define SCU_SFSP3_7_EHS_Msk                                   (0x01UL << SCU_SFSP3_7_EHS_Pos)                           /*!< SCU SFSP3_7: EHS Mask               */
+#define SCU_SFSP3_7_EZI_Pos                                   6                                                         /*!< SCU SFSP3_7: EZI Position           */
+#define SCU_SFSP3_7_EZI_Msk                                   (0x01UL << SCU_SFSP3_7_EZI_Pos)                           /*!< SCU SFSP3_7: EZI Mask               */
+#define SCU_SFSP3_7_EHD_Pos                                   8                                                         /*!< SCU SFSP3_7: EHD Position           */
+#define SCU_SFSP3_7_EHD_Msk                                   (0x03UL << SCU_SFSP3_7_EHD_Pos)                           /*!< SCU SFSP3_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP3_8  ------------------------------------------
+#define SCU_SFSP3_8_MODE_Pos                                  0                                                         /*!< SCU SFSP3_8: MODE Position          */
+#define SCU_SFSP3_8_MODE_Msk                                  (0x07UL << SCU_SFSP3_8_MODE_Pos)                          /*!< SCU SFSP3_8: MODE Mask              */
+#define SCU_SFSP3_8_EPD_Pos                                   3                                                         /*!< SCU SFSP3_8: EPD Position           */
+#define SCU_SFSP3_8_EPD_Msk                                   (0x01UL << SCU_SFSP3_8_EPD_Pos)                           /*!< SCU SFSP3_8: EPD Mask               */
+#define SCU_SFSP3_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_8: EPUN Position          */
+#define SCU_SFSP3_8_EPUN_Msk                                  (0x01UL << SCU_SFSP3_8_EPUN_Pos)                          /*!< SCU SFSP3_8: EPUN Mask              */
+#define SCU_SFSP3_8_EHS_Pos                                   5                                                         /*!< SCU SFSP3_8: EHS Position           */
+#define SCU_SFSP3_8_EHS_Msk                                   (0x01UL << SCU_SFSP3_8_EHS_Pos)                           /*!< SCU SFSP3_8: EHS Mask               */
+#define SCU_SFSP3_8_EZI_Pos                                   6                                                         /*!< SCU SFSP3_8: EZI Position           */
+#define SCU_SFSP3_8_EZI_Msk                                   (0x01UL << SCU_SFSP3_8_EZI_Pos)                           /*!< SCU SFSP3_8: EZI Mask               */
+#define SCU_SFSP3_8_EHD_Pos                                   8                                                         /*!< SCU SFSP3_8: EHD Position           */
+#define SCU_SFSP3_8_EHD_Msk                                   (0x03UL << SCU_SFSP3_8_EHD_Pos)                           /*!< SCU SFSP3_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_0  ------------------------------------------
+#define SCU_SFSP4_0_MODE_Pos                                  0                                                         /*!< SCU SFSP4_0: MODE Position          */
+#define SCU_SFSP4_0_MODE_Msk                                  (0x07UL << SCU_SFSP4_0_MODE_Pos)                          /*!< SCU SFSP4_0: MODE Mask              */
+#define SCU_SFSP4_0_EPD_Pos                                   3                                                         /*!< SCU SFSP4_0: EPD Position           */
+#define SCU_SFSP4_0_EPD_Msk                                   (0x01UL << SCU_SFSP4_0_EPD_Pos)                           /*!< SCU SFSP4_0: EPD Mask               */
+#define SCU_SFSP4_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_0: EPUN Position          */
+#define SCU_SFSP4_0_EPUN_Msk                                  (0x01UL << SCU_SFSP4_0_EPUN_Pos)                          /*!< SCU SFSP4_0: EPUN Mask              */
+#define SCU_SFSP4_0_EHS_Pos                                   5                                                         /*!< SCU SFSP4_0: EHS Position           */
+#define SCU_SFSP4_0_EHS_Msk                                   (0x01UL << SCU_SFSP4_0_EHS_Pos)                           /*!< SCU SFSP4_0: EHS Mask               */
+#define SCU_SFSP4_0_EZI_Pos                                   6                                                         /*!< SCU SFSP4_0: EZI Position           */
+#define SCU_SFSP4_0_EZI_Msk                                   (0x01UL << SCU_SFSP4_0_EZI_Pos)                           /*!< SCU SFSP4_0: EZI Mask               */
+#define SCU_SFSP4_0_EHD_Pos                                   8                                                         /*!< SCU SFSP4_0: EHD Position           */
+#define SCU_SFSP4_0_EHD_Msk                                   (0x03UL << SCU_SFSP4_0_EHD_Pos)                           /*!< SCU SFSP4_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_1  ------------------------------------------
+#define SCU_SFSP4_1_MODE_Pos                                  0                                                         /*!< SCU SFSP4_1: MODE Position          */
+#define SCU_SFSP4_1_MODE_Msk                                  (0x07UL << SCU_SFSP4_1_MODE_Pos)                          /*!< SCU SFSP4_1: MODE Mask              */
+#define SCU_SFSP4_1_EPD_Pos                                   3                                                         /*!< SCU SFSP4_1: EPD Position           */
+#define SCU_SFSP4_1_EPD_Msk                                   (0x01UL << SCU_SFSP4_1_EPD_Pos)                           /*!< SCU SFSP4_1: EPD Mask               */
+#define SCU_SFSP4_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_1: EPUN Position          */
+#define SCU_SFSP4_1_EPUN_Msk                                  (0x01UL << SCU_SFSP4_1_EPUN_Pos)                          /*!< SCU SFSP4_1: EPUN Mask              */
+#define SCU_SFSP4_1_EHS_Pos                                   5                                                         /*!< SCU SFSP4_1: EHS Position           */
+#define SCU_SFSP4_1_EHS_Msk                                   (0x01UL << SCU_SFSP4_1_EHS_Pos)                           /*!< SCU SFSP4_1: EHS Mask               */
+#define SCU_SFSP4_1_EZI_Pos                                   6                                                         /*!< SCU SFSP4_1: EZI Position           */
+#define SCU_SFSP4_1_EZI_Msk                                   (0x01UL << SCU_SFSP4_1_EZI_Pos)                           /*!< SCU SFSP4_1: EZI Mask               */
+#define SCU_SFSP4_1_EHD_Pos                                   8                                                         /*!< SCU SFSP4_1: EHD Position           */
+#define SCU_SFSP4_1_EHD_Msk                                   (0x03UL << SCU_SFSP4_1_EHD_Pos)                           /*!< SCU SFSP4_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_2  ------------------------------------------
+#define SCU_SFSP4_2_MODE_Pos                                  0                                                         /*!< SCU SFSP4_2: MODE Position          */
+#define SCU_SFSP4_2_MODE_Msk                                  (0x07UL << SCU_SFSP4_2_MODE_Pos)                          /*!< SCU SFSP4_2: MODE Mask              */
+#define SCU_SFSP4_2_EPD_Pos                                   3                                                         /*!< SCU SFSP4_2: EPD Position           */
+#define SCU_SFSP4_2_EPD_Msk                                   (0x01UL << SCU_SFSP4_2_EPD_Pos)                           /*!< SCU SFSP4_2: EPD Mask               */
+#define SCU_SFSP4_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_2: EPUN Position          */
+#define SCU_SFSP4_2_EPUN_Msk                                  (0x01UL << SCU_SFSP4_2_EPUN_Pos)                          /*!< SCU SFSP4_2: EPUN Mask              */
+#define SCU_SFSP4_2_EHS_Pos                                   5                                                         /*!< SCU SFSP4_2: EHS Position           */
+#define SCU_SFSP4_2_EHS_Msk                                   (0x01UL << SCU_SFSP4_2_EHS_Pos)                           /*!< SCU SFSP4_2: EHS Mask               */
+#define SCU_SFSP4_2_EZI_Pos                                   6                                                         /*!< SCU SFSP4_2: EZI Position           */
+#define SCU_SFSP4_2_EZI_Msk                                   (0x01UL << SCU_SFSP4_2_EZI_Pos)                           /*!< SCU SFSP4_2: EZI Mask               */
+#define SCU_SFSP4_2_EHD_Pos                                   8                                                         /*!< SCU SFSP4_2: EHD Position           */
+#define SCU_SFSP4_2_EHD_Msk                                   (0x03UL << SCU_SFSP4_2_EHD_Pos)                           /*!< SCU SFSP4_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_3  ------------------------------------------
+#define SCU_SFSP4_3_MODE_Pos                                  0                                                         /*!< SCU SFSP4_3: MODE Position          */
+#define SCU_SFSP4_3_MODE_Msk                                  (0x07UL << SCU_SFSP4_3_MODE_Pos)                          /*!< SCU SFSP4_3: MODE Mask              */
+#define SCU_SFSP4_3_EPD_Pos                                   3                                                         /*!< SCU SFSP4_3: EPD Position           */
+#define SCU_SFSP4_3_EPD_Msk                                   (0x01UL << SCU_SFSP4_3_EPD_Pos)                           /*!< SCU SFSP4_3: EPD Mask               */
+#define SCU_SFSP4_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_3: EPUN Position          */
+#define SCU_SFSP4_3_EPUN_Msk                                  (0x01UL << SCU_SFSP4_3_EPUN_Pos)                          /*!< SCU SFSP4_3: EPUN Mask              */
+#define SCU_SFSP4_3_EHS_Pos                                   5                                                         /*!< SCU SFSP4_3: EHS Position           */
+#define SCU_SFSP4_3_EHS_Msk                                   (0x01UL << SCU_SFSP4_3_EHS_Pos)                           /*!< SCU SFSP4_3: EHS Mask               */
+#define SCU_SFSP4_3_EZI_Pos                                   6                                                         /*!< SCU SFSP4_3: EZI Position           */
+#define SCU_SFSP4_3_EZI_Msk                                   (0x01UL << SCU_SFSP4_3_EZI_Pos)                           /*!< SCU SFSP4_3: EZI Mask               */
+#define SCU_SFSP4_3_EHD_Pos                                   8                                                         /*!< SCU SFSP4_3: EHD Position           */
+#define SCU_SFSP4_3_EHD_Msk                                   (0x03UL << SCU_SFSP4_3_EHD_Pos)                           /*!< SCU SFSP4_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_4  ------------------------------------------
+#define SCU_SFSP4_4_MODE_Pos                                  0                                                         /*!< SCU SFSP4_4: MODE Position          */
+#define SCU_SFSP4_4_MODE_Msk                                  (0x07UL << SCU_SFSP4_4_MODE_Pos)                          /*!< SCU SFSP4_4: MODE Mask              */
+#define SCU_SFSP4_4_EPD_Pos                                   3                                                         /*!< SCU SFSP4_4: EPD Position           */
+#define SCU_SFSP4_4_EPD_Msk                                   (0x01UL << SCU_SFSP4_4_EPD_Pos)                           /*!< SCU SFSP4_4: EPD Mask               */
+#define SCU_SFSP4_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_4: EPUN Position          */
+#define SCU_SFSP4_4_EPUN_Msk                                  (0x01UL << SCU_SFSP4_4_EPUN_Pos)                          /*!< SCU SFSP4_4: EPUN Mask              */
+#define SCU_SFSP4_4_EHS_Pos                                   5                                                         /*!< SCU SFSP4_4: EHS Position           */
+#define SCU_SFSP4_4_EHS_Msk                                   (0x01UL << SCU_SFSP4_4_EHS_Pos)                           /*!< SCU SFSP4_4: EHS Mask               */
+#define SCU_SFSP4_4_EZI_Pos                                   6                                                         /*!< SCU SFSP4_4: EZI Position           */
+#define SCU_SFSP4_4_EZI_Msk                                   (0x01UL << SCU_SFSP4_4_EZI_Pos)                           /*!< SCU SFSP4_4: EZI Mask               */
+#define SCU_SFSP4_4_EHD_Pos                                   8                                                         /*!< SCU SFSP4_4: EHD Position           */
+#define SCU_SFSP4_4_EHD_Msk                                   (0x03UL << SCU_SFSP4_4_EHD_Pos)                           /*!< SCU SFSP4_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_5  ------------------------------------------
+#define SCU_SFSP4_5_MODE_Pos                                  0                                                         /*!< SCU SFSP4_5: MODE Position          */
+#define SCU_SFSP4_5_MODE_Msk                                  (0x07UL << SCU_SFSP4_5_MODE_Pos)                          /*!< SCU SFSP4_5: MODE Mask              */
+#define SCU_SFSP4_5_EPD_Pos                                   3                                                         /*!< SCU SFSP4_5: EPD Position           */
+#define SCU_SFSP4_5_EPD_Msk                                   (0x01UL << SCU_SFSP4_5_EPD_Pos)                           /*!< SCU SFSP4_5: EPD Mask               */
+#define SCU_SFSP4_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_5: EPUN Position          */
+#define SCU_SFSP4_5_EPUN_Msk                                  (0x01UL << SCU_SFSP4_5_EPUN_Pos)                          /*!< SCU SFSP4_5: EPUN Mask              */
+#define SCU_SFSP4_5_EHS_Pos                                   5                                                         /*!< SCU SFSP4_5: EHS Position           */
+#define SCU_SFSP4_5_EHS_Msk                                   (0x01UL << SCU_SFSP4_5_EHS_Pos)                           /*!< SCU SFSP4_5: EHS Mask               */
+#define SCU_SFSP4_5_EZI_Pos                                   6                                                         /*!< SCU SFSP4_5: EZI Position           */
+#define SCU_SFSP4_5_EZI_Msk                                   (0x01UL << SCU_SFSP4_5_EZI_Pos)                           /*!< SCU SFSP4_5: EZI Mask               */
+#define SCU_SFSP4_5_EHD_Pos                                   8                                                         /*!< SCU SFSP4_5: EHD Position           */
+#define SCU_SFSP4_5_EHD_Msk                                   (0x03UL << SCU_SFSP4_5_EHD_Pos)                           /*!< SCU SFSP4_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_6  ------------------------------------------
+#define SCU_SFSP4_6_MODE_Pos                                  0                                                         /*!< SCU SFSP4_6: MODE Position          */
+#define SCU_SFSP4_6_MODE_Msk                                  (0x07UL << SCU_SFSP4_6_MODE_Pos)                          /*!< SCU SFSP4_6: MODE Mask              */
+#define SCU_SFSP4_6_EPD_Pos                                   3                                                         /*!< SCU SFSP4_6: EPD Position           */
+#define SCU_SFSP4_6_EPD_Msk                                   (0x01UL << SCU_SFSP4_6_EPD_Pos)                           /*!< SCU SFSP4_6: EPD Mask               */
+#define SCU_SFSP4_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_6: EPUN Position          */
+#define SCU_SFSP4_6_EPUN_Msk                                  (0x01UL << SCU_SFSP4_6_EPUN_Pos)                          /*!< SCU SFSP4_6: EPUN Mask              */
+#define SCU_SFSP4_6_EHS_Pos                                   5                                                         /*!< SCU SFSP4_6: EHS Position           */
+#define SCU_SFSP4_6_EHS_Msk                                   (0x01UL << SCU_SFSP4_6_EHS_Pos)                           /*!< SCU SFSP4_6: EHS Mask               */
+#define SCU_SFSP4_6_EZI_Pos                                   6                                                         /*!< SCU SFSP4_6: EZI Position           */
+#define SCU_SFSP4_6_EZI_Msk                                   (0x01UL << SCU_SFSP4_6_EZI_Pos)                           /*!< SCU SFSP4_6: EZI Mask               */
+#define SCU_SFSP4_6_EHD_Pos                                   8                                                         /*!< SCU SFSP4_6: EHD Position           */
+#define SCU_SFSP4_6_EHD_Msk                                   (0x03UL << SCU_SFSP4_6_EHD_Pos)                           /*!< SCU SFSP4_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_7  ------------------------------------------
+#define SCU_SFSP4_7_MODE_Pos                                  0                                                         /*!< SCU SFSP4_7: MODE Position          */
+#define SCU_SFSP4_7_MODE_Msk                                  (0x07UL << SCU_SFSP4_7_MODE_Pos)                          /*!< SCU SFSP4_7: MODE Mask              */
+#define SCU_SFSP4_7_EPD_Pos                                   3                                                         /*!< SCU SFSP4_7: EPD Position           */
+#define SCU_SFSP4_7_EPD_Msk                                   (0x01UL << SCU_SFSP4_7_EPD_Pos)                           /*!< SCU SFSP4_7: EPD Mask               */
+#define SCU_SFSP4_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_7: EPUN Position          */
+#define SCU_SFSP4_7_EPUN_Msk                                  (0x01UL << SCU_SFSP4_7_EPUN_Pos)                          /*!< SCU SFSP4_7: EPUN Mask              */
+#define SCU_SFSP4_7_EHS_Pos                                   5                                                         /*!< SCU SFSP4_7: EHS Position           */
+#define SCU_SFSP4_7_EHS_Msk                                   (0x01UL << SCU_SFSP4_7_EHS_Pos)                           /*!< SCU SFSP4_7: EHS Mask               */
+#define SCU_SFSP4_7_EZI_Pos                                   6                                                         /*!< SCU SFSP4_7: EZI Position           */
+#define SCU_SFSP4_7_EZI_Msk                                   (0x01UL << SCU_SFSP4_7_EZI_Pos)                           /*!< SCU SFSP4_7: EZI Mask               */
+#define SCU_SFSP4_7_EHD_Pos                                   8                                                         /*!< SCU SFSP4_7: EHD Position           */
+#define SCU_SFSP4_7_EHD_Msk                                   (0x03UL << SCU_SFSP4_7_EHD_Pos)                           /*!< SCU SFSP4_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_8  ------------------------------------------
+#define SCU_SFSP4_8_MODE_Pos                                  0                                                         /*!< SCU SFSP4_8: MODE Position          */
+#define SCU_SFSP4_8_MODE_Msk                                  (0x07UL << SCU_SFSP4_8_MODE_Pos)                          /*!< SCU SFSP4_8: MODE Mask              */
+#define SCU_SFSP4_8_EPD_Pos                                   3                                                         /*!< SCU SFSP4_8: EPD Position           */
+#define SCU_SFSP4_8_EPD_Msk                                   (0x01UL << SCU_SFSP4_8_EPD_Pos)                           /*!< SCU SFSP4_8: EPD Mask               */
+#define SCU_SFSP4_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_8: EPUN Position          */
+#define SCU_SFSP4_8_EPUN_Msk                                  (0x01UL << SCU_SFSP4_8_EPUN_Pos)                          /*!< SCU SFSP4_8: EPUN Mask              */
+#define SCU_SFSP4_8_EHS_Pos                                   5                                                         /*!< SCU SFSP4_8: EHS Position           */
+#define SCU_SFSP4_8_EHS_Msk                                   (0x01UL << SCU_SFSP4_8_EHS_Pos)                           /*!< SCU SFSP4_8: EHS Mask               */
+#define SCU_SFSP4_8_EZI_Pos                                   6                                                         /*!< SCU SFSP4_8: EZI Position           */
+#define SCU_SFSP4_8_EZI_Msk                                   (0x01UL << SCU_SFSP4_8_EZI_Pos)                           /*!< SCU SFSP4_8: EZI Mask               */
+#define SCU_SFSP4_8_EHD_Pos                                   8                                                         /*!< SCU SFSP4_8: EHD Position           */
+#define SCU_SFSP4_8_EHD_Msk                                   (0x03UL << SCU_SFSP4_8_EHD_Pos)                           /*!< SCU SFSP4_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP4_9  ------------------------------------------
+#define SCU_SFSP4_9_MODE_Pos                                  0                                                         /*!< SCU SFSP4_9: MODE Position          */
+#define SCU_SFSP4_9_MODE_Msk                                  (0x07UL << SCU_SFSP4_9_MODE_Pos)                          /*!< SCU SFSP4_9: MODE Mask              */
+#define SCU_SFSP4_9_EPD_Pos                                   3                                                         /*!< SCU SFSP4_9: EPD Position           */
+#define SCU_SFSP4_9_EPD_Msk                                   (0x01UL << SCU_SFSP4_9_EPD_Pos)                           /*!< SCU SFSP4_9: EPD Mask               */
+#define SCU_SFSP4_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_9: EPUN Position          */
+#define SCU_SFSP4_9_EPUN_Msk                                  (0x01UL << SCU_SFSP4_9_EPUN_Pos)                          /*!< SCU SFSP4_9: EPUN Mask              */
+#define SCU_SFSP4_9_EHS_Pos                                   5                                                         /*!< SCU SFSP4_9: EHS Position           */
+#define SCU_SFSP4_9_EHS_Msk                                   (0x01UL << SCU_SFSP4_9_EHS_Pos)                           /*!< SCU SFSP4_9: EHS Mask               */
+#define SCU_SFSP4_9_EZI_Pos                                   6                                                         /*!< SCU SFSP4_9: EZI Position           */
+#define SCU_SFSP4_9_EZI_Msk                                   (0x01UL << SCU_SFSP4_9_EZI_Pos)                           /*!< SCU SFSP4_9: EZI Mask               */
+#define SCU_SFSP4_9_EHD_Pos                                   8                                                         /*!< SCU SFSP4_9: EHD Position           */
+#define SCU_SFSP4_9_EHD_Msk                                   (0x03UL << SCU_SFSP4_9_EHD_Pos)                           /*!< SCU SFSP4_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP4_10  ------------------------------------------
+#define SCU_SFSP4_10_MODE_Pos                                 0                                                         /*!< SCU SFSP4_10: MODE Position         */
+#define SCU_SFSP4_10_MODE_Msk                                 (0x07UL << SCU_SFSP4_10_MODE_Pos)                         /*!< SCU SFSP4_10: MODE Mask             */
+#define SCU_SFSP4_10_EPD_Pos                                  3                                                         /*!< SCU SFSP4_10: EPD Position          */
+#define SCU_SFSP4_10_EPD_Msk                                  (0x01UL << SCU_SFSP4_10_EPD_Pos)                          /*!< SCU SFSP4_10: EPD Mask              */
+#define SCU_SFSP4_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP4_10: EPUN Position         */
+#define SCU_SFSP4_10_EPUN_Msk                                 (0x01UL << SCU_SFSP4_10_EPUN_Pos)                         /*!< SCU SFSP4_10: EPUN Mask             */
+#define SCU_SFSP4_10_EHS_Pos                                  5                                                         /*!< SCU SFSP4_10: EHS Position          */
+#define SCU_SFSP4_10_EHS_Msk                                  (0x01UL << SCU_SFSP4_10_EHS_Pos)                          /*!< SCU SFSP4_10: EHS Mask              */
+#define SCU_SFSP4_10_EZI_Pos                                  6                                                         /*!< SCU SFSP4_10: EZI Position          */
+#define SCU_SFSP4_10_EZI_Msk                                  (0x01UL << SCU_SFSP4_10_EZI_Pos)                          /*!< SCU SFSP4_10: EZI Mask              */
+#define SCU_SFSP4_10_EHD_Pos                                  8                                                         /*!< SCU SFSP4_10: EHD Position          */
+#define SCU_SFSP4_10_EHD_Msk                                  (0x03UL << SCU_SFSP4_10_EHD_Pos)                          /*!< SCU SFSP4_10: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP5_0  ------------------------------------------
+#define SCU_SFSP5_0_MODE_Pos                                  0                                                         /*!< SCU SFSP5_0: MODE Position          */
+#define SCU_SFSP5_0_MODE_Msk                                  (0x07UL << SCU_SFSP5_0_MODE_Pos)                          /*!< SCU SFSP5_0: MODE Mask              */
+#define SCU_SFSP5_0_EPD_Pos                                   3                                                         /*!< SCU SFSP5_0: EPD Position           */
+#define SCU_SFSP5_0_EPD_Msk                                   (0x01UL << SCU_SFSP5_0_EPD_Pos)                           /*!< SCU SFSP5_0: EPD Mask               */
+#define SCU_SFSP5_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_0: EPUN Position          */
+#define SCU_SFSP5_0_EPUN_Msk                                  (0x01UL << SCU_SFSP5_0_EPUN_Pos)                          /*!< SCU SFSP5_0: EPUN Mask              */
+#define SCU_SFSP5_0_EHS_Pos                                   5                                                         /*!< SCU SFSP5_0: EHS Position           */
+#define SCU_SFSP5_0_EHS_Msk                                   (0x01UL << SCU_SFSP5_0_EHS_Pos)                           /*!< SCU SFSP5_0: EHS Mask               */
+#define SCU_SFSP5_0_EZI_Pos                                   6                                                         /*!< SCU SFSP5_0: EZI Position           */
+#define SCU_SFSP5_0_EZI_Msk                                   (0x01UL << SCU_SFSP5_0_EZI_Pos)                           /*!< SCU SFSP5_0: EZI Mask               */
+#define SCU_SFSP5_0_EHD_Pos                                   8                                                         /*!< SCU SFSP5_0: EHD Position           */
+#define SCU_SFSP5_0_EHD_Msk                                   (0x03UL << SCU_SFSP5_0_EHD_Pos)                           /*!< SCU SFSP5_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_1  ------------------------------------------
+#define SCU_SFSP5_1_MODE_Pos                                  0                                                         /*!< SCU SFSP5_1: MODE Position          */
+#define SCU_SFSP5_1_MODE_Msk                                  (0x07UL << SCU_SFSP5_1_MODE_Pos)                          /*!< SCU SFSP5_1: MODE Mask              */
+#define SCU_SFSP5_1_EPD_Pos                                   3                                                         /*!< SCU SFSP5_1: EPD Position           */
+#define SCU_SFSP5_1_EPD_Msk                                   (0x01UL << SCU_SFSP5_1_EPD_Pos)                           /*!< SCU SFSP5_1: EPD Mask               */
+#define SCU_SFSP5_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_1: EPUN Position          */
+#define SCU_SFSP5_1_EPUN_Msk                                  (0x01UL << SCU_SFSP5_1_EPUN_Pos)                          /*!< SCU SFSP5_1: EPUN Mask              */
+#define SCU_SFSP5_1_EHS_Pos                                   5                                                         /*!< SCU SFSP5_1: EHS Position           */
+#define SCU_SFSP5_1_EHS_Msk                                   (0x01UL << SCU_SFSP5_1_EHS_Pos)                           /*!< SCU SFSP5_1: EHS Mask               */
+#define SCU_SFSP5_1_EZI_Pos                                   6                                                         /*!< SCU SFSP5_1: EZI Position           */
+#define SCU_SFSP5_1_EZI_Msk                                   (0x01UL << SCU_SFSP5_1_EZI_Pos)                           /*!< SCU SFSP5_1: EZI Mask               */
+#define SCU_SFSP5_1_EHD_Pos                                   8                                                         /*!< SCU SFSP5_1: EHD Position           */
+#define SCU_SFSP5_1_EHD_Msk                                   (0x03UL << SCU_SFSP5_1_EHD_Pos)                           /*!< SCU SFSP5_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_2  ------------------------------------------
+#define SCU_SFSP5_2_MODE_Pos                                  0                                                         /*!< SCU SFSP5_2: MODE Position          */
+#define SCU_SFSP5_2_MODE_Msk                                  (0x07UL << SCU_SFSP5_2_MODE_Pos)                          /*!< SCU SFSP5_2: MODE Mask              */
+#define SCU_SFSP5_2_EPD_Pos                                   3                                                         /*!< SCU SFSP5_2: EPD Position           */
+#define SCU_SFSP5_2_EPD_Msk                                   (0x01UL << SCU_SFSP5_2_EPD_Pos)                           /*!< SCU SFSP5_2: EPD Mask               */
+#define SCU_SFSP5_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_2: EPUN Position          */
+#define SCU_SFSP5_2_EPUN_Msk                                  (0x01UL << SCU_SFSP5_2_EPUN_Pos)                          /*!< SCU SFSP5_2: EPUN Mask              */
+#define SCU_SFSP5_2_EHS_Pos                                   5                                                         /*!< SCU SFSP5_2: EHS Position           */
+#define SCU_SFSP5_2_EHS_Msk                                   (0x01UL << SCU_SFSP5_2_EHS_Pos)                           /*!< SCU SFSP5_2: EHS Mask               */
+#define SCU_SFSP5_2_EZI_Pos                                   6                                                         /*!< SCU SFSP5_2: EZI Position           */
+#define SCU_SFSP5_2_EZI_Msk                                   (0x01UL << SCU_SFSP5_2_EZI_Pos)                           /*!< SCU SFSP5_2: EZI Mask               */
+#define SCU_SFSP5_2_EHD_Pos                                   8                                                         /*!< SCU SFSP5_2: EHD Position           */
+#define SCU_SFSP5_2_EHD_Msk                                   (0x03UL << SCU_SFSP5_2_EHD_Pos)                           /*!< SCU SFSP5_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_3  ------------------------------------------
+#define SCU_SFSP5_3_MODE_Pos                                  0                                                         /*!< SCU SFSP5_3: MODE Position          */
+#define SCU_SFSP5_3_MODE_Msk                                  (0x07UL << SCU_SFSP5_3_MODE_Pos)                          /*!< SCU SFSP5_3: MODE Mask              */
+#define SCU_SFSP5_3_EPD_Pos                                   3                                                         /*!< SCU SFSP5_3: EPD Position           */
+#define SCU_SFSP5_3_EPD_Msk                                   (0x01UL << SCU_SFSP5_3_EPD_Pos)                           /*!< SCU SFSP5_3: EPD Mask               */
+#define SCU_SFSP5_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_3: EPUN Position          */
+#define SCU_SFSP5_3_EPUN_Msk                                  (0x01UL << SCU_SFSP5_3_EPUN_Pos)                          /*!< SCU SFSP5_3: EPUN Mask              */
+#define SCU_SFSP5_3_EHS_Pos                                   5                                                         /*!< SCU SFSP5_3: EHS Position           */
+#define SCU_SFSP5_3_EHS_Msk                                   (0x01UL << SCU_SFSP5_3_EHS_Pos)                           /*!< SCU SFSP5_3: EHS Mask               */
+#define SCU_SFSP5_3_EZI_Pos                                   6                                                         /*!< SCU SFSP5_3: EZI Position           */
+#define SCU_SFSP5_3_EZI_Msk                                   (0x01UL << SCU_SFSP5_3_EZI_Pos)                           /*!< SCU SFSP5_3: EZI Mask               */
+#define SCU_SFSP5_3_EHD_Pos                                   8                                                         /*!< SCU SFSP5_3: EHD Position           */
+#define SCU_SFSP5_3_EHD_Msk                                   (0x03UL << SCU_SFSP5_3_EHD_Pos)                           /*!< SCU SFSP5_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_4  ------------------------------------------
+#define SCU_SFSP5_4_MODE_Pos                                  0                                                         /*!< SCU SFSP5_4: MODE Position          */
+#define SCU_SFSP5_4_MODE_Msk                                  (0x07UL << SCU_SFSP5_4_MODE_Pos)                          /*!< SCU SFSP5_4: MODE Mask              */
+#define SCU_SFSP5_4_EPD_Pos                                   3                                                         /*!< SCU SFSP5_4: EPD Position           */
+#define SCU_SFSP5_4_EPD_Msk                                   (0x01UL << SCU_SFSP5_4_EPD_Pos)                           /*!< SCU SFSP5_4: EPD Mask               */
+#define SCU_SFSP5_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_4: EPUN Position          */
+#define SCU_SFSP5_4_EPUN_Msk                                  (0x01UL << SCU_SFSP5_4_EPUN_Pos)                          /*!< SCU SFSP5_4: EPUN Mask              */
+#define SCU_SFSP5_4_EHS_Pos                                   5                                                         /*!< SCU SFSP5_4: EHS Position           */
+#define SCU_SFSP5_4_EHS_Msk                                   (0x01UL << SCU_SFSP5_4_EHS_Pos)                           /*!< SCU SFSP5_4: EHS Mask               */
+#define SCU_SFSP5_4_EZI_Pos                                   6                                                         /*!< SCU SFSP5_4: EZI Position           */
+#define SCU_SFSP5_4_EZI_Msk                                   (0x01UL << SCU_SFSP5_4_EZI_Pos)                           /*!< SCU SFSP5_4: EZI Mask               */
+#define SCU_SFSP5_4_EHD_Pos                                   8                                                         /*!< SCU SFSP5_4: EHD Position           */
+#define SCU_SFSP5_4_EHD_Msk                                   (0x03UL << SCU_SFSP5_4_EHD_Pos)                           /*!< SCU SFSP5_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_5  ------------------------------------------
+#define SCU_SFSP5_5_MODE_Pos                                  0                                                         /*!< SCU SFSP5_5: MODE Position          */
+#define SCU_SFSP5_5_MODE_Msk                                  (0x07UL << SCU_SFSP5_5_MODE_Pos)                          /*!< SCU SFSP5_5: MODE Mask              */
+#define SCU_SFSP5_5_EPD_Pos                                   3                                                         /*!< SCU SFSP5_5: EPD Position           */
+#define SCU_SFSP5_5_EPD_Msk                                   (0x01UL << SCU_SFSP5_5_EPD_Pos)                           /*!< SCU SFSP5_5: EPD Mask               */
+#define SCU_SFSP5_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_5: EPUN Position          */
+#define SCU_SFSP5_5_EPUN_Msk                                  (0x01UL << SCU_SFSP5_5_EPUN_Pos)                          /*!< SCU SFSP5_5: EPUN Mask              */
+#define SCU_SFSP5_5_EHS_Pos                                   5                                                         /*!< SCU SFSP5_5: EHS Position           */
+#define SCU_SFSP5_5_EHS_Msk                                   (0x01UL << SCU_SFSP5_5_EHS_Pos)                           /*!< SCU SFSP5_5: EHS Mask               */
+#define SCU_SFSP5_5_EZI_Pos                                   6                                                         /*!< SCU SFSP5_5: EZI Position           */
+#define SCU_SFSP5_5_EZI_Msk                                   (0x01UL << SCU_SFSP5_5_EZI_Pos)                           /*!< SCU SFSP5_5: EZI Mask               */
+#define SCU_SFSP5_5_EHD_Pos                                   8                                                         /*!< SCU SFSP5_5: EHD Position           */
+#define SCU_SFSP5_5_EHD_Msk                                   (0x03UL << SCU_SFSP5_5_EHD_Pos)                           /*!< SCU SFSP5_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_6  ------------------------------------------
+#define SCU_SFSP5_6_MODE_Pos                                  0                                                         /*!< SCU SFSP5_6: MODE Position          */
+#define SCU_SFSP5_6_MODE_Msk                                  (0x07UL << SCU_SFSP5_6_MODE_Pos)                          /*!< SCU SFSP5_6: MODE Mask              */
+#define SCU_SFSP5_6_EPD_Pos                                   3                                                         /*!< SCU SFSP5_6: EPD Position           */
+#define SCU_SFSP5_6_EPD_Msk                                   (0x01UL << SCU_SFSP5_6_EPD_Pos)                           /*!< SCU SFSP5_6: EPD Mask               */
+#define SCU_SFSP5_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_6: EPUN Position          */
+#define SCU_SFSP5_6_EPUN_Msk                                  (0x01UL << SCU_SFSP5_6_EPUN_Pos)                          /*!< SCU SFSP5_6: EPUN Mask              */
+#define SCU_SFSP5_6_EHS_Pos                                   5                                                         /*!< SCU SFSP5_6: EHS Position           */
+#define SCU_SFSP5_6_EHS_Msk                                   (0x01UL << SCU_SFSP5_6_EHS_Pos)                           /*!< SCU SFSP5_6: EHS Mask               */
+#define SCU_SFSP5_6_EZI_Pos                                   6                                                         /*!< SCU SFSP5_6: EZI Position           */
+#define SCU_SFSP5_6_EZI_Msk                                   (0x01UL << SCU_SFSP5_6_EZI_Pos)                           /*!< SCU SFSP5_6: EZI Mask               */
+#define SCU_SFSP5_6_EHD_Pos                                   8                                                         /*!< SCU SFSP5_6: EHD Position           */
+#define SCU_SFSP5_6_EHD_Msk                                   (0x03UL << SCU_SFSP5_6_EHD_Pos)                           /*!< SCU SFSP5_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP5_7  ------------------------------------------
+#define SCU_SFSP5_7_MODE_Pos                                  0                                                         /*!< SCU SFSP5_7: MODE Position          */
+#define SCU_SFSP5_7_MODE_Msk                                  (0x07UL << SCU_SFSP5_7_MODE_Pos)                          /*!< SCU SFSP5_7: MODE Mask              */
+#define SCU_SFSP5_7_EPD_Pos                                   3                                                         /*!< SCU SFSP5_7: EPD Position           */
+#define SCU_SFSP5_7_EPD_Msk                                   (0x01UL << SCU_SFSP5_7_EPD_Pos)                           /*!< SCU SFSP5_7: EPD Mask               */
+#define SCU_SFSP5_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_7: EPUN Position          */
+#define SCU_SFSP5_7_EPUN_Msk                                  (0x01UL << SCU_SFSP5_7_EPUN_Pos)                          /*!< SCU SFSP5_7: EPUN Mask              */
+#define SCU_SFSP5_7_EHS_Pos                                   5                                                         /*!< SCU SFSP5_7: EHS Position           */
+#define SCU_SFSP5_7_EHS_Msk                                   (0x01UL << SCU_SFSP5_7_EHS_Pos)                           /*!< SCU SFSP5_7: EHS Mask               */
+#define SCU_SFSP5_7_EZI_Pos                                   6                                                         /*!< SCU SFSP5_7: EZI Position           */
+#define SCU_SFSP5_7_EZI_Msk                                   (0x01UL << SCU_SFSP5_7_EZI_Pos)                           /*!< SCU SFSP5_7: EZI Mask               */
+#define SCU_SFSP5_7_EHD_Pos                                   8                                                         /*!< SCU SFSP5_7: EHD Position           */
+#define SCU_SFSP5_7_EHD_Msk                                   (0x03UL << SCU_SFSP5_7_EHD_Pos)                           /*!< SCU SFSP5_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_0  ------------------------------------------
+#define SCU_SFSP6_0_MODE_Pos                                  0                                                         /*!< SCU SFSP6_0: MODE Position          */
+#define SCU_SFSP6_0_MODE_Msk                                  (0x07UL << SCU_SFSP6_0_MODE_Pos)                          /*!< SCU SFSP6_0: MODE Mask              */
+#define SCU_SFSP6_0_EPD_Pos                                   3                                                         /*!< SCU SFSP6_0: EPD Position           */
+#define SCU_SFSP6_0_EPD_Msk                                   (0x01UL << SCU_SFSP6_0_EPD_Pos)                           /*!< SCU SFSP6_0: EPD Mask               */
+#define SCU_SFSP6_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_0: EPUN Position          */
+#define SCU_SFSP6_0_EPUN_Msk                                  (0x01UL << SCU_SFSP6_0_EPUN_Pos)                          /*!< SCU SFSP6_0: EPUN Mask              */
+#define SCU_SFSP6_0_EHS_Pos                                   5                                                         /*!< SCU SFSP6_0: EHS Position           */
+#define SCU_SFSP6_0_EHS_Msk                                   (0x01UL << SCU_SFSP6_0_EHS_Pos)                           /*!< SCU SFSP6_0: EHS Mask               */
+#define SCU_SFSP6_0_EZI_Pos                                   6                                                         /*!< SCU SFSP6_0: EZI Position           */
+#define SCU_SFSP6_0_EZI_Msk                                   (0x01UL << SCU_SFSP6_0_EZI_Pos)                           /*!< SCU SFSP6_0: EZI Mask               */
+#define SCU_SFSP6_0_EHD_Pos                                   8                                                         /*!< SCU SFSP6_0: EHD Position           */
+#define SCU_SFSP6_0_EHD_Msk                                   (0x03UL << SCU_SFSP6_0_EHD_Pos)                           /*!< SCU SFSP6_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_1  ------------------------------------------
+#define SCU_SFSP6_1_MODE_Pos                                  0                                                         /*!< SCU SFSP6_1: MODE Position          */
+#define SCU_SFSP6_1_MODE_Msk                                  (0x07UL << SCU_SFSP6_1_MODE_Pos)                          /*!< SCU SFSP6_1: MODE Mask              */
+#define SCU_SFSP6_1_EPD_Pos                                   3                                                         /*!< SCU SFSP6_1: EPD Position           */
+#define SCU_SFSP6_1_EPD_Msk                                   (0x01UL << SCU_SFSP6_1_EPD_Pos)                           /*!< SCU SFSP6_1: EPD Mask               */
+#define SCU_SFSP6_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_1: EPUN Position          */
+#define SCU_SFSP6_1_EPUN_Msk                                  (0x01UL << SCU_SFSP6_1_EPUN_Pos)                          /*!< SCU SFSP6_1: EPUN Mask              */
+#define SCU_SFSP6_1_EHS_Pos                                   5                                                         /*!< SCU SFSP6_1: EHS Position           */
+#define SCU_SFSP6_1_EHS_Msk                                   (0x01UL << SCU_SFSP6_1_EHS_Pos)                           /*!< SCU SFSP6_1: EHS Mask               */
+#define SCU_SFSP6_1_EZI_Pos                                   6                                                         /*!< SCU SFSP6_1: EZI Position           */
+#define SCU_SFSP6_1_EZI_Msk                                   (0x01UL << SCU_SFSP6_1_EZI_Pos)                           /*!< SCU SFSP6_1: EZI Mask               */
+#define SCU_SFSP6_1_EHD_Pos                                   8                                                         /*!< SCU SFSP6_1: EHD Position           */
+#define SCU_SFSP6_1_EHD_Msk                                   (0x03UL << SCU_SFSP6_1_EHD_Pos)                           /*!< SCU SFSP6_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_2  ------------------------------------------
+#define SCU_SFSP6_2_MODE_Pos                                  0                                                         /*!< SCU SFSP6_2: MODE Position          */
+#define SCU_SFSP6_2_MODE_Msk                                  (0x07UL << SCU_SFSP6_2_MODE_Pos)                          /*!< SCU SFSP6_2: MODE Mask              */
+#define SCU_SFSP6_2_EPD_Pos                                   3                                                         /*!< SCU SFSP6_2: EPD Position           */
+#define SCU_SFSP6_2_EPD_Msk                                   (0x01UL << SCU_SFSP6_2_EPD_Pos)                           /*!< SCU SFSP6_2: EPD Mask               */
+#define SCU_SFSP6_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_2: EPUN Position          */
+#define SCU_SFSP6_2_EPUN_Msk                                  (0x01UL << SCU_SFSP6_2_EPUN_Pos)                          /*!< SCU SFSP6_2: EPUN Mask              */
+#define SCU_SFSP6_2_EHS_Pos                                   5                                                         /*!< SCU SFSP6_2: EHS Position           */
+#define SCU_SFSP6_2_EHS_Msk                                   (0x01UL << SCU_SFSP6_2_EHS_Pos)                           /*!< SCU SFSP6_2: EHS Mask               */
+#define SCU_SFSP6_2_EZI_Pos                                   6                                                         /*!< SCU SFSP6_2: EZI Position           */
+#define SCU_SFSP6_2_EZI_Msk                                   (0x01UL << SCU_SFSP6_2_EZI_Pos)                           /*!< SCU SFSP6_2: EZI Mask               */
+#define SCU_SFSP6_2_EHD_Pos                                   8                                                         /*!< SCU SFSP6_2: EHD Position           */
+#define SCU_SFSP6_2_EHD_Msk                                   (0x03UL << SCU_SFSP6_2_EHD_Pos)                           /*!< SCU SFSP6_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_3  ------------------------------------------
+#define SCU_SFSP6_3_MODE_Pos                                  0                                                         /*!< SCU SFSP6_3: MODE Position          */
+#define SCU_SFSP6_3_MODE_Msk                                  (0x07UL << SCU_SFSP6_3_MODE_Pos)                          /*!< SCU SFSP6_3: MODE Mask              */
+#define SCU_SFSP6_3_EPD_Pos                                   3                                                         /*!< SCU SFSP6_3: EPD Position           */
+#define SCU_SFSP6_3_EPD_Msk                                   (0x01UL << SCU_SFSP6_3_EPD_Pos)                           /*!< SCU SFSP6_3: EPD Mask               */
+#define SCU_SFSP6_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_3: EPUN Position          */
+#define SCU_SFSP6_3_EPUN_Msk                                  (0x01UL << SCU_SFSP6_3_EPUN_Pos)                          /*!< SCU SFSP6_3: EPUN Mask              */
+#define SCU_SFSP6_3_EHS_Pos                                   5                                                         /*!< SCU SFSP6_3: EHS Position           */
+#define SCU_SFSP6_3_EHS_Msk                                   (0x01UL << SCU_SFSP6_3_EHS_Pos)                           /*!< SCU SFSP6_3: EHS Mask               */
+#define SCU_SFSP6_3_EZI_Pos                                   6                                                         /*!< SCU SFSP6_3: EZI Position           */
+#define SCU_SFSP6_3_EZI_Msk                                   (0x01UL << SCU_SFSP6_3_EZI_Pos)                           /*!< SCU SFSP6_3: EZI Mask               */
+#define SCU_SFSP6_3_EHD_Pos                                   8                                                         /*!< SCU SFSP6_3: EHD Position           */
+#define SCU_SFSP6_3_EHD_Msk                                   (0x03UL << SCU_SFSP6_3_EHD_Pos)                           /*!< SCU SFSP6_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_4  ------------------------------------------
+#define SCU_SFSP6_4_MODE_Pos                                  0                                                         /*!< SCU SFSP6_4: MODE Position          */
+#define SCU_SFSP6_4_MODE_Msk                                  (0x07UL << SCU_SFSP6_4_MODE_Pos)                          /*!< SCU SFSP6_4: MODE Mask              */
+#define SCU_SFSP6_4_EPD_Pos                                   3                                                         /*!< SCU SFSP6_4: EPD Position           */
+#define SCU_SFSP6_4_EPD_Msk                                   (0x01UL << SCU_SFSP6_4_EPD_Pos)                           /*!< SCU SFSP6_4: EPD Mask               */
+#define SCU_SFSP6_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_4: EPUN Position          */
+#define SCU_SFSP6_4_EPUN_Msk                                  (0x01UL << SCU_SFSP6_4_EPUN_Pos)                          /*!< SCU SFSP6_4: EPUN Mask              */
+#define SCU_SFSP6_4_EHS_Pos                                   5                                                         /*!< SCU SFSP6_4: EHS Position           */
+#define SCU_SFSP6_4_EHS_Msk                                   (0x01UL << SCU_SFSP6_4_EHS_Pos)                           /*!< SCU SFSP6_4: EHS Mask               */
+#define SCU_SFSP6_4_EZI_Pos                                   6                                                         /*!< SCU SFSP6_4: EZI Position           */
+#define SCU_SFSP6_4_EZI_Msk                                   (0x01UL << SCU_SFSP6_4_EZI_Pos)                           /*!< SCU SFSP6_4: EZI Mask               */
+#define SCU_SFSP6_4_EHD_Pos                                   8                                                         /*!< SCU SFSP6_4: EHD Position           */
+#define SCU_SFSP6_4_EHD_Msk                                   (0x03UL << SCU_SFSP6_4_EHD_Pos)                           /*!< SCU SFSP6_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_5  ------------------------------------------
+#define SCU_SFSP6_5_MODE_Pos                                  0                                                         /*!< SCU SFSP6_5: MODE Position          */
+#define SCU_SFSP6_5_MODE_Msk                                  (0x07UL << SCU_SFSP6_5_MODE_Pos)                          /*!< SCU SFSP6_5: MODE Mask              */
+#define SCU_SFSP6_5_EPD_Pos                                   3                                                         /*!< SCU SFSP6_5: EPD Position           */
+#define SCU_SFSP6_5_EPD_Msk                                   (0x01UL << SCU_SFSP6_5_EPD_Pos)                           /*!< SCU SFSP6_5: EPD Mask               */
+#define SCU_SFSP6_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_5: EPUN Position          */
+#define SCU_SFSP6_5_EPUN_Msk                                  (0x01UL << SCU_SFSP6_5_EPUN_Pos)                          /*!< SCU SFSP6_5: EPUN Mask              */
+#define SCU_SFSP6_5_EHS_Pos                                   5                                                         /*!< SCU SFSP6_5: EHS Position           */
+#define SCU_SFSP6_5_EHS_Msk                                   (0x01UL << SCU_SFSP6_5_EHS_Pos)                           /*!< SCU SFSP6_5: EHS Mask               */
+#define SCU_SFSP6_5_EZI_Pos                                   6                                                         /*!< SCU SFSP6_5: EZI Position           */
+#define SCU_SFSP6_5_EZI_Msk                                   (0x01UL << SCU_SFSP6_5_EZI_Pos)                           /*!< SCU SFSP6_5: EZI Mask               */
+#define SCU_SFSP6_5_EHD_Pos                                   8                                                         /*!< SCU SFSP6_5: EHD Position           */
+#define SCU_SFSP6_5_EHD_Msk                                   (0x03UL << SCU_SFSP6_5_EHD_Pos)                           /*!< SCU SFSP6_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_6  ------------------------------------------
+#define SCU_SFSP6_6_MODE_Pos                                  0                                                         /*!< SCU SFSP6_6: MODE Position          */
+#define SCU_SFSP6_6_MODE_Msk                                  (0x07UL << SCU_SFSP6_6_MODE_Pos)                          /*!< SCU SFSP6_6: MODE Mask              */
+#define SCU_SFSP6_6_EPD_Pos                                   3                                                         /*!< SCU SFSP6_6: EPD Position           */
+#define SCU_SFSP6_6_EPD_Msk                                   (0x01UL << SCU_SFSP6_6_EPD_Pos)                           /*!< SCU SFSP6_6: EPD Mask               */
+#define SCU_SFSP6_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_6: EPUN Position          */
+#define SCU_SFSP6_6_EPUN_Msk                                  (0x01UL << SCU_SFSP6_6_EPUN_Pos)                          /*!< SCU SFSP6_6: EPUN Mask              */
+#define SCU_SFSP6_6_EHS_Pos                                   5                                                         /*!< SCU SFSP6_6: EHS Position           */
+#define SCU_SFSP6_6_EHS_Msk                                   (0x01UL << SCU_SFSP6_6_EHS_Pos)                           /*!< SCU SFSP6_6: EHS Mask               */
+#define SCU_SFSP6_6_EZI_Pos                                   6                                                         /*!< SCU SFSP6_6: EZI Position           */
+#define SCU_SFSP6_6_EZI_Msk                                   (0x01UL << SCU_SFSP6_6_EZI_Pos)                           /*!< SCU SFSP6_6: EZI Mask               */
+#define SCU_SFSP6_6_EHD_Pos                                   8                                                         /*!< SCU SFSP6_6: EHD Position           */
+#define SCU_SFSP6_6_EHD_Msk                                   (0x03UL << SCU_SFSP6_6_EHD_Pos)                           /*!< SCU SFSP6_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_7  ------------------------------------------
+#define SCU_SFSP6_7_MODE_Pos                                  0                                                         /*!< SCU SFSP6_7: MODE Position          */
+#define SCU_SFSP6_7_MODE_Msk                                  (0x07UL << SCU_SFSP6_7_MODE_Pos)                          /*!< SCU SFSP6_7: MODE Mask              */
+#define SCU_SFSP6_7_EPD_Pos                                   3                                                         /*!< SCU SFSP6_7: EPD Position           */
+#define SCU_SFSP6_7_EPD_Msk                                   (0x01UL << SCU_SFSP6_7_EPD_Pos)                           /*!< SCU SFSP6_7: EPD Mask               */
+#define SCU_SFSP6_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_7: EPUN Position          */
+#define SCU_SFSP6_7_EPUN_Msk                                  (0x01UL << SCU_SFSP6_7_EPUN_Pos)                          /*!< SCU SFSP6_7: EPUN Mask              */
+#define SCU_SFSP6_7_EHS_Pos                                   5                                                         /*!< SCU SFSP6_7: EHS Position           */
+#define SCU_SFSP6_7_EHS_Msk                                   (0x01UL << SCU_SFSP6_7_EHS_Pos)                           /*!< SCU SFSP6_7: EHS Mask               */
+#define SCU_SFSP6_7_EZI_Pos                                   6                                                         /*!< SCU SFSP6_7: EZI Position           */
+#define SCU_SFSP6_7_EZI_Msk                                   (0x01UL << SCU_SFSP6_7_EZI_Pos)                           /*!< SCU SFSP6_7: EZI Mask               */
+#define SCU_SFSP6_7_EHD_Pos                                   8                                                         /*!< SCU SFSP6_7: EHD Position           */
+#define SCU_SFSP6_7_EHD_Msk                                   (0x03UL << SCU_SFSP6_7_EHD_Pos)                           /*!< SCU SFSP6_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_8  ------------------------------------------
+#define SCU_SFSP6_8_MODE_Pos                                  0                                                         /*!< SCU SFSP6_8: MODE Position          */
+#define SCU_SFSP6_8_MODE_Msk                                  (0x07UL << SCU_SFSP6_8_MODE_Pos)                          /*!< SCU SFSP6_8: MODE Mask              */
+#define SCU_SFSP6_8_EPD_Pos                                   3                                                         /*!< SCU SFSP6_8: EPD Position           */
+#define SCU_SFSP6_8_EPD_Msk                                   (0x01UL << SCU_SFSP6_8_EPD_Pos)                           /*!< SCU SFSP6_8: EPD Mask               */
+#define SCU_SFSP6_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_8: EPUN Position          */
+#define SCU_SFSP6_8_EPUN_Msk                                  (0x01UL << SCU_SFSP6_8_EPUN_Pos)                          /*!< SCU SFSP6_8: EPUN Mask              */
+#define SCU_SFSP6_8_EHS_Pos                                   5                                                         /*!< SCU SFSP6_8: EHS Position           */
+#define SCU_SFSP6_8_EHS_Msk                                   (0x01UL << SCU_SFSP6_8_EHS_Pos)                           /*!< SCU SFSP6_8: EHS Mask               */
+#define SCU_SFSP6_8_EZI_Pos                                   6                                                         /*!< SCU SFSP6_8: EZI Position           */
+#define SCU_SFSP6_8_EZI_Msk                                   (0x01UL << SCU_SFSP6_8_EZI_Pos)                           /*!< SCU SFSP6_8: EZI Mask               */
+#define SCU_SFSP6_8_EHD_Pos                                   8                                                         /*!< SCU SFSP6_8: EHD Position           */
+#define SCU_SFSP6_8_EHD_Msk                                   (0x03UL << SCU_SFSP6_8_EHD_Pos)                           /*!< SCU SFSP6_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP6_9  ------------------------------------------
+#define SCU_SFSP6_9_MODE_Pos                                  0                                                         /*!< SCU SFSP6_9: MODE Position          */
+#define SCU_SFSP6_9_MODE_Msk                                  (0x07UL << SCU_SFSP6_9_MODE_Pos)                          /*!< SCU SFSP6_9: MODE Mask              */
+#define SCU_SFSP6_9_EPD_Pos                                   3                                                         /*!< SCU SFSP6_9: EPD Position           */
+#define SCU_SFSP6_9_EPD_Msk                                   (0x01UL << SCU_SFSP6_9_EPD_Pos)                           /*!< SCU SFSP6_9: EPD Mask               */
+#define SCU_SFSP6_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_9: EPUN Position          */
+#define SCU_SFSP6_9_EPUN_Msk                                  (0x01UL << SCU_SFSP6_9_EPUN_Pos)                          /*!< SCU SFSP6_9: EPUN Mask              */
+#define SCU_SFSP6_9_EHS_Pos                                   5                                                         /*!< SCU SFSP6_9: EHS Position           */
+#define SCU_SFSP6_9_EHS_Msk                                   (0x01UL << SCU_SFSP6_9_EHS_Pos)                           /*!< SCU SFSP6_9: EHS Mask               */
+#define SCU_SFSP6_9_EZI_Pos                                   6                                                         /*!< SCU SFSP6_9: EZI Position           */
+#define SCU_SFSP6_9_EZI_Msk                                   (0x01UL << SCU_SFSP6_9_EZI_Pos)                           /*!< SCU SFSP6_9: EZI Mask               */
+#define SCU_SFSP6_9_EHD_Pos                                   8                                                         /*!< SCU SFSP6_9: EHD Position           */
+#define SCU_SFSP6_9_EHD_Msk                                   (0x03UL << SCU_SFSP6_9_EHD_Pos)                           /*!< SCU SFSP6_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSP6_10  ------------------------------------------
+#define SCU_SFSP6_10_MODE_Pos                                 0                                                         /*!< SCU SFSP6_10: MODE Position         */
+#define SCU_SFSP6_10_MODE_Msk                                 (0x07UL << SCU_SFSP6_10_MODE_Pos)                         /*!< SCU SFSP6_10: MODE Mask             */
+#define SCU_SFSP6_10_EPD_Pos                                  3                                                         /*!< SCU SFSP6_10: EPD Position          */
+#define SCU_SFSP6_10_EPD_Msk                                  (0x01UL << SCU_SFSP6_10_EPD_Pos)                          /*!< SCU SFSP6_10: EPD Mask              */
+#define SCU_SFSP6_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_10: EPUN Position         */
+#define SCU_SFSP6_10_EPUN_Msk                                 (0x01UL << SCU_SFSP6_10_EPUN_Pos)                         /*!< SCU SFSP6_10: EPUN Mask             */
+#define SCU_SFSP6_10_EHS_Pos                                  5                                                         /*!< SCU SFSP6_10: EHS Position          */
+#define SCU_SFSP6_10_EHS_Msk                                  (0x01UL << SCU_SFSP6_10_EHS_Pos)                          /*!< SCU SFSP6_10: EHS Mask              */
+#define SCU_SFSP6_10_EZI_Pos                                  6                                                         /*!< SCU SFSP6_10: EZI Position          */
+#define SCU_SFSP6_10_EZI_Msk                                  (0x01UL << SCU_SFSP6_10_EZI_Pos)                          /*!< SCU SFSP6_10: EZI Mask              */
+#define SCU_SFSP6_10_EHD_Pos                                  8                                                         /*!< SCU SFSP6_10: EHD Position          */
+#define SCU_SFSP6_10_EHD_Msk                                  (0x03UL << SCU_SFSP6_10_EHD_Pos)                          /*!< SCU SFSP6_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP6_11  ------------------------------------------
+#define SCU_SFSP6_11_MODE_Pos                                 0                                                         /*!< SCU SFSP6_11: MODE Position         */
+#define SCU_SFSP6_11_MODE_Msk                                 (0x07UL << SCU_SFSP6_11_MODE_Pos)                         /*!< SCU SFSP6_11: MODE Mask             */
+#define SCU_SFSP6_11_EPD_Pos                                  3                                                         /*!< SCU SFSP6_11: EPD Position          */
+#define SCU_SFSP6_11_EPD_Msk                                  (0x01UL << SCU_SFSP6_11_EPD_Pos)                          /*!< SCU SFSP6_11: EPD Mask              */
+#define SCU_SFSP6_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_11: EPUN Position         */
+#define SCU_SFSP6_11_EPUN_Msk                                 (0x01UL << SCU_SFSP6_11_EPUN_Pos)                         /*!< SCU SFSP6_11: EPUN Mask             */
+#define SCU_SFSP6_11_EHS_Pos                                  5                                                         /*!< SCU SFSP6_11: EHS Position          */
+#define SCU_SFSP6_11_EHS_Msk                                  (0x01UL << SCU_SFSP6_11_EHS_Pos)                          /*!< SCU SFSP6_11: EHS Mask              */
+#define SCU_SFSP6_11_EZI_Pos                                  6                                                         /*!< SCU SFSP6_11: EZI Position          */
+#define SCU_SFSP6_11_EZI_Msk                                  (0x01UL << SCU_SFSP6_11_EZI_Pos)                          /*!< SCU SFSP6_11: EZI Mask              */
+#define SCU_SFSP6_11_EHD_Pos                                  8                                                         /*!< SCU SFSP6_11: EHD Position          */
+#define SCU_SFSP6_11_EHD_Msk                                  (0x03UL << SCU_SFSP6_11_EHD_Pos)                          /*!< SCU SFSP6_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSP6_12  ------------------------------------------
+#define SCU_SFSP6_12_MODE_Pos                                 0                                                         /*!< SCU SFSP6_12: MODE Position         */
+#define SCU_SFSP6_12_MODE_Msk                                 (0x07UL << SCU_SFSP6_12_MODE_Pos)                         /*!< SCU SFSP6_12: MODE Mask             */
+#define SCU_SFSP6_12_EPD_Pos                                  3                                                         /*!< SCU SFSP6_12: EPD Position          */
+#define SCU_SFSP6_12_EPD_Msk                                  (0x01UL << SCU_SFSP6_12_EPD_Pos)                          /*!< SCU SFSP6_12: EPD Mask              */
+#define SCU_SFSP6_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_12: EPUN Position         */
+#define SCU_SFSP6_12_EPUN_Msk                                 (0x01UL << SCU_SFSP6_12_EPUN_Pos)                         /*!< SCU SFSP6_12: EPUN Mask             */
+#define SCU_SFSP6_12_EHS_Pos                                  5                                                         /*!< SCU SFSP6_12: EHS Position          */
+#define SCU_SFSP6_12_EHS_Msk                                  (0x01UL << SCU_SFSP6_12_EHS_Pos)                          /*!< SCU SFSP6_12: EHS Mask              */
+#define SCU_SFSP6_12_EZI_Pos                                  6                                                         /*!< SCU SFSP6_12: EZI Position          */
+#define SCU_SFSP6_12_EZI_Msk                                  (0x01UL << SCU_SFSP6_12_EZI_Pos)                          /*!< SCU SFSP6_12: EZI Mask              */
+#define SCU_SFSP6_12_EHD_Pos                                  8                                                         /*!< SCU SFSP6_12: EHD Position          */
+#define SCU_SFSP6_12_EHD_Msk                                  (0x03UL << SCU_SFSP6_12_EHD_Pos)                          /*!< SCU SFSP6_12: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSP7_0  ------------------------------------------
+#define SCU_SFSP7_0_MODE_Pos                                  0                                                         /*!< SCU SFSP7_0: MODE Position          */
+#define SCU_SFSP7_0_MODE_Msk                                  (0x07UL << SCU_SFSP7_0_MODE_Pos)                          /*!< SCU SFSP7_0: MODE Mask              */
+#define SCU_SFSP7_0_EPD_Pos                                   3                                                         /*!< SCU SFSP7_0: EPD Position           */
+#define SCU_SFSP7_0_EPD_Msk                                   (0x01UL << SCU_SFSP7_0_EPD_Pos)                           /*!< SCU SFSP7_0: EPD Mask               */
+#define SCU_SFSP7_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_0: EPUN Position          */
+#define SCU_SFSP7_0_EPUN_Msk                                  (0x01UL << SCU_SFSP7_0_EPUN_Pos)                          /*!< SCU SFSP7_0: EPUN Mask              */
+#define SCU_SFSP7_0_EHS_Pos                                   5                                                         /*!< SCU SFSP7_0: EHS Position           */
+#define SCU_SFSP7_0_EHS_Msk                                   (0x01UL << SCU_SFSP7_0_EHS_Pos)                           /*!< SCU SFSP7_0: EHS Mask               */
+#define SCU_SFSP7_0_EZI_Pos                                   6                                                         /*!< SCU SFSP7_0: EZI Position           */
+#define SCU_SFSP7_0_EZI_Msk                                   (0x01UL << SCU_SFSP7_0_EZI_Pos)                           /*!< SCU SFSP7_0: EZI Mask               */
+#define SCU_SFSP7_0_EHD_Pos                                   8                                                         /*!< SCU SFSP7_0: EHD Position           */
+#define SCU_SFSP7_0_EHD_Msk                                   (0x03UL << SCU_SFSP7_0_EHD_Pos)                           /*!< SCU SFSP7_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_1  ------------------------------------------
+#define SCU_SFSP7_1_MODE_Pos                                  0                                                         /*!< SCU SFSP7_1: MODE Position          */
+#define SCU_SFSP7_1_MODE_Msk                                  (0x07UL << SCU_SFSP7_1_MODE_Pos)                          /*!< SCU SFSP7_1: MODE Mask              */
+#define SCU_SFSP7_1_EPD_Pos                                   3                                                         /*!< SCU SFSP7_1: EPD Position           */
+#define SCU_SFSP7_1_EPD_Msk                                   (0x01UL << SCU_SFSP7_1_EPD_Pos)                           /*!< SCU SFSP7_1: EPD Mask               */
+#define SCU_SFSP7_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_1: EPUN Position          */
+#define SCU_SFSP7_1_EPUN_Msk                                  (0x01UL << SCU_SFSP7_1_EPUN_Pos)                          /*!< SCU SFSP7_1: EPUN Mask              */
+#define SCU_SFSP7_1_EHS_Pos                                   5                                                         /*!< SCU SFSP7_1: EHS Position           */
+#define SCU_SFSP7_1_EHS_Msk                                   (0x01UL << SCU_SFSP7_1_EHS_Pos)                           /*!< SCU SFSP7_1: EHS Mask               */
+#define SCU_SFSP7_1_EZI_Pos                                   6                                                         /*!< SCU SFSP7_1: EZI Position           */
+#define SCU_SFSP7_1_EZI_Msk                                   (0x01UL << SCU_SFSP7_1_EZI_Pos)                           /*!< SCU SFSP7_1: EZI Mask               */
+#define SCU_SFSP7_1_EHD_Pos                                   8                                                         /*!< SCU SFSP7_1: EHD Position           */
+#define SCU_SFSP7_1_EHD_Msk                                   (0x03UL << SCU_SFSP7_1_EHD_Pos)                           /*!< SCU SFSP7_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_2  ------------------------------------------
+#define SCU_SFSP7_2_MODE_Pos                                  0                                                         /*!< SCU SFSP7_2: MODE Position          */
+#define SCU_SFSP7_2_MODE_Msk                                  (0x07UL << SCU_SFSP7_2_MODE_Pos)                          /*!< SCU SFSP7_2: MODE Mask              */
+#define SCU_SFSP7_2_EPD_Pos                                   3                                                         /*!< SCU SFSP7_2: EPD Position           */
+#define SCU_SFSP7_2_EPD_Msk                                   (0x01UL << SCU_SFSP7_2_EPD_Pos)                           /*!< SCU SFSP7_2: EPD Mask               */
+#define SCU_SFSP7_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_2: EPUN Position          */
+#define SCU_SFSP7_2_EPUN_Msk                                  (0x01UL << SCU_SFSP7_2_EPUN_Pos)                          /*!< SCU SFSP7_2: EPUN Mask              */
+#define SCU_SFSP7_2_EHS_Pos                                   5                                                         /*!< SCU SFSP7_2: EHS Position           */
+#define SCU_SFSP7_2_EHS_Msk                                   (0x01UL << SCU_SFSP7_2_EHS_Pos)                           /*!< SCU SFSP7_2: EHS Mask               */
+#define SCU_SFSP7_2_EZI_Pos                                   6                                                         /*!< SCU SFSP7_2: EZI Position           */
+#define SCU_SFSP7_2_EZI_Msk                                   (0x01UL << SCU_SFSP7_2_EZI_Pos)                           /*!< SCU SFSP7_2: EZI Mask               */
+#define SCU_SFSP7_2_EHD_Pos                                   8                                                         /*!< SCU SFSP7_2: EHD Position           */
+#define SCU_SFSP7_2_EHD_Msk                                   (0x03UL << SCU_SFSP7_2_EHD_Pos)                           /*!< SCU SFSP7_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_3  ------------------------------------------
+#define SCU_SFSP7_3_MODE_Pos                                  0                                                         /*!< SCU SFSP7_3: MODE Position          */
+#define SCU_SFSP7_3_MODE_Msk                                  (0x07UL << SCU_SFSP7_3_MODE_Pos)                          /*!< SCU SFSP7_3: MODE Mask              */
+#define SCU_SFSP7_3_EPD_Pos                                   3                                                         /*!< SCU SFSP7_3: EPD Position           */
+#define SCU_SFSP7_3_EPD_Msk                                   (0x01UL << SCU_SFSP7_3_EPD_Pos)                           /*!< SCU SFSP7_3: EPD Mask               */
+#define SCU_SFSP7_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_3: EPUN Position          */
+#define SCU_SFSP7_3_EPUN_Msk                                  (0x01UL << SCU_SFSP7_3_EPUN_Pos)                          /*!< SCU SFSP7_3: EPUN Mask              */
+#define SCU_SFSP7_3_EHS_Pos                                   5                                                         /*!< SCU SFSP7_3: EHS Position           */
+#define SCU_SFSP7_3_EHS_Msk                                   (0x01UL << SCU_SFSP7_3_EHS_Pos)                           /*!< SCU SFSP7_3: EHS Mask               */
+#define SCU_SFSP7_3_EZI_Pos                                   6                                                         /*!< SCU SFSP7_3: EZI Position           */
+#define SCU_SFSP7_3_EZI_Msk                                   (0x01UL << SCU_SFSP7_3_EZI_Pos)                           /*!< SCU SFSP7_3: EZI Mask               */
+#define SCU_SFSP7_3_EHD_Pos                                   8                                                         /*!< SCU SFSP7_3: EHD Position           */
+#define SCU_SFSP7_3_EHD_Msk                                   (0x03UL << SCU_SFSP7_3_EHD_Pos)                           /*!< SCU SFSP7_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_4  ------------------------------------------
+#define SCU_SFSP7_4_MODE_Pos                                  0                                                         /*!< SCU SFSP7_4: MODE Position          */
+#define SCU_SFSP7_4_MODE_Msk                                  (0x07UL << SCU_SFSP7_4_MODE_Pos)                          /*!< SCU SFSP7_4: MODE Mask              */
+#define SCU_SFSP7_4_EPD_Pos                                   3                                                         /*!< SCU SFSP7_4: EPD Position           */
+#define SCU_SFSP7_4_EPD_Msk                                   (0x01UL << SCU_SFSP7_4_EPD_Pos)                           /*!< SCU SFSP7_4: EPD Mask               */
+#define SCU_SFSP7_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_4: EPUN Position          */
+#define SCU_SFSP7_4_EPUN_Msk                                  (0x01UL << SCU_SFSP7_4_EPUN_Pos)                          /*!< SCU SFSP7_4: EPUN Mask              */
+#define SCU_SFSP7_4_EHS_Pos                                   5                                                         /*!< SCU SFSP7_4: EHS Position           */
+#define SCU_SFSP7_4_EHS_Msk                                   (0x01UL << SCU_SFSP7_4_EHS_Pos)                           /*!< SCU SFSP7_4: EHS Mask               */
+#define SCU_SFSP7_4_EZI_Pos                                   6                                                         /*!< SCU SFSP7_4: EZI Position           */
+#define SCU_SFSP7_4_EZI_Msk                                   (0x01UL << SCU_SFSP7_4_EZI_Pos)                           /*!< SCU SFSP7_4: EZI Mask               */
+#define SCU_SFSP7_4_EHD_Pos                                   8                                                         /*!< SCU SFSP7_4: EHD Position           */
+#define SCU_SFSP7_4_EHD_Msk                                   (0x03UL << SCU_SFSP7_4_EHD_Pos)                           /*!< SCU SFSP7_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_5  ------------------------------------------
+#define SCU_SFSP7_5_MODE_Pos                                  0                                                         /*!< SCU SFSP7_5: MODE Position          */
+#define SCU_SFSP7_5_MODE_Msk                                  (0x07UL << SCU_SFSP7_5_MODE_Pos)                          /*!< SCU SFSP7_5: MODE Mask              */
+#define SCU_SFSP7_5_EPD_Pos                                   3                                                         /*!< SCU SFSP7_5: EPD Position           */
+#define SCU_SFSP7_5_EPD_Msk                                   (0x01UL << SCU_SFSP7_5_EPD_Pos)                           /*!< SCU SFSP7_5: EPD Mask               */
+#define SCU_SFSP7_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_5: EPUN Position          */
+#define SCU_SFSP7_5_EPUN_Msk                                  (0x01UL << SCU_SFSP7_5_EPUN_Pos)                          /*!< SCU SFSP7_5: EPUN Mask              */
+#define SCU_SFSP7_5_EHS_Pos                                   5                                                         /*!< SCU SFSP7_5: EHS Position           */
+#define SCU_SFSP7_5_EHS_Msk                                   (0x01UL << SCU_SFSP7_5_EHS_Pos)                           /*!< SCU SFSP7_5: EHS Mask               */
+#define SCU_SFSP7_5_EZI_Pos                                   6                                                         /*!< SCU SFSP7_5: EZI Position           */
+#define SCU_SFSP7_5_EZI_Msk                                   (0x01UL << SCU_SFSP7_5_EZI_Pos)                           /*!< SCU SFSP7_5: EZI Mask               */
+#define SCU_SFSP7_5_EHD_Pos                                   8                                                         /*!< SCU SFSP7_5: EHD Position           */
+#define SCU_SFSP7_5_EHD_Msk                                   (0x03UL << SCU_SFSP7_5_EHD_Pos)                           /*!< SCU SFSP7_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_6  ------------------------------------------
+#define SCU_SFSP7_6_MODE_Pos                                  0                                                         /*!< SCU SFSP7_6: MODE Position          */
+#define SCU_SFSP7_6_MODE_Msk                                  (0x07UL << SCU_SFSP7_6_MODE_Pos)                          /*!< SCU SFSP7_6: MODE Mask              */
+#define SCU_SFSP7_6_EPD_Pos                                   3                                                         /*!< SCU SFSP7_6: EPD Position           */
+#define SCU_SFSP7_6_EPD_Msk                                   (0x01UL << SCU_SFSP7_6_EPD_Pos)                           /*!< SCU SFSP7_6: EPD Mask               */
+#define SCU_SFSP7_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_6: EPUN Position          */
+#define SCU_SFSP7_6_EPUN_Msk                                  (0x01UL << SCU_SFSP7_6_EPUN_Pos)                          /*!< SCU SFSP7_6: EPUN Mask              */
+#define SCU_SFSP7_6_EHS_Pos                                   5                                                         /*!< SCU SFSP7_6: EHS Position           */
+#define SCU_SFSP7_6_EHS_Msk                                   (0x01UL << SCU_SFSP7_6_EHS_Pos)                           /*!< SCU SFSP7_6: EHS Mask               */
+#define SCU_SFSP7_6_EZI_Pos                                   6                                                         /*!< SCU SFSP7_6: EZI Position           */
+#define SCU_SFSP7_6_EZI_Msk                                   (0x01UL << SCU_SFSP7_6_EZI_Pos)                           /*!< SCU SFSP7_6: EZI Mask               */
+#define SCU_SFSP7_6_EHD_Pos                                   8                                                         /*!< SCU SFSP7_6: EHD Position           */
+#define SCU_SFSP7_6_EHD_Msk                                   (0x03UL << SCU_SFSP7_6_EHD_Pos)                           /*!< SCU SFSP7_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP7_7  ------------------------------------------
+#define SCU_SFSP7_7_MODE_Pos                                  0                                                         /*!< SCU SFSP7_7: MODE Position          */
+#define SCU_SFSP7_7_MODE_Msk                                  (0x07UL << SCU_SFSP7_7_MODE_Pos)                          /*!< SCU SFSP7_7: MODE Mask              */
+#define SCU_SFSP7_7_EPD_Pos                                   3                                                         /*!< SCU SFSP7_7: EPD Position           */
+#define SCU_SFSP7_7_EPD_Msk                                   (0x01UL << SCU_SFSP7_7_EPD_Pos)                           /*!< SCU SFSP7_7: EPD Mask               */
+#define SCU_SFSP7_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_7: EPUN Position          */
+#define SCU_SFSP7_7_EPUN_Msk                                  (0x01UL << SCU_SFSP7_7_EPUN_Pos)                          /*!< SCU SFSP7_7: EPUN Mask              */
+#define SCU_SFSP7_7_EHS_Pos                                   5                                                         /*!< SCU SFSP7_7: EHS Position           */
+#define SCU_SFSP7_7_EHS_Msk                                   (0x01UL << SCU_SFSP7_7_EHS_Pos)                           /*!< SCU SFSP7_7: EHS Mask               */
+#define SCU_SFSP7_7_EZI_Pos                                   6                                                         /*!< SCU SFSP7_7: EZI Position           */
+#define SCU_SFSP7_7_EZI_Msk                                   (0x01UL << SCU_SFSP7_7_EZI_Pos)                           /*!< SCU SFSP7_7: EZI Mask               */
+#define SCU_SFSP7_7_EHD_Pos                                   8                                                         /*!< SCU SFSP7_7: EHD Position           */
+#define SCU_SFSP7_7_EHD_Msk                                   (0x03UL << SCU_SFSP7_7_EHD_Pos)                           /*!< SCU SFSP7_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_0  ------------------------------------------
+#define SCU_SFSP8_0_MODE_Pos                                  0                                                         /*!< SCU SFSP8_0: MODE Position          */
+#define SCU_SFSP8_0_MODE_Msk                                  (0x07UL << SCU_SFSP8_0_MODE_Pos)                          /*!< SCU SFSP8_0: MODE Mask              */
+#define SCU_SFSP8_0_EPD_Pos                                   3                                                         /*!< SCU SFSP8_0: EPD Position           */
+#define SCU_SFSP8_0_EPD_Msk                                   (0x01UL << SCU_SFSP8_0_EPD_Pos)                           /*!< SCU SFSP8_0: EPD Mask               */
+#define SCU_SFSP8_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_0: EPUN Position          */
+#define SCU_SFSP8_0_EPUN_Msk                                  (0x01UL << SCU_SFSP8_0_EPUN_Pos)                          /*!< SCU SFSP8_0: EPUN Mask              */
+#define SCU_SFSP8_0_EHS_Pos                                   5                                                         /*!< SCU SFSP8_0: EHS Position           */
+#define SCU_SFSP8_0_EHS_Msk                                   (0x01UL << SCU_SFSP8_0_EHS_Pos)                           /*!< SCU SFSP8_0: EHS Mask               */
+#define SCU_SFSP8_0_EZI_Pos                                   6                                                         /*!< SCU SFSP8_0: EZI Position           */
+#define SCU_SFSP8_0_EZI_Msk                                   (0x01UL << SCU_SFSP8_0_EZI_Pos)                           /*!< SCU SFSP8_0: EZI Mask               */
+#define SCU_SFSP8_0_EHD_Pos                                   8                                                         /*!< SCU SFSP8_0: EHD Position           */
+#define SCU_SFSP8_0_EHD_Msk                                   (0x03UL << SCU_SFSP8_0_EHD_Pos)                           /*!< SCU SFSP8_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_1  ------------------------------------------
+#define SCU_SFSP8_1_MODE_Pos                                  0                                                         /*!< SCU SFSP8_1: MODE Position          */
+#define SCU_SFSP8_1_MODE_Msk                                  (0x07UL << SCU_SFSP8_1_MODE_Pos)                          /*!< SCU SFSP8_1: MODE Mask              */
+#define SCU_SFSP8_1_EPD_Pos                                   3                                                         /*!< SCU SFSP8_1: EPD Position           */
+#define SCU_SFSP8_1_EPD_Msk                                   (0x01UL << SCU_SFSP8_1_EPD_Pos)                           /*!< SCU SFSP8_1: EPD Mask               */
+#define SCU_SFSP8_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_1: EPUN Position          */
+#define SCU_SFSP8_1_EPUN_Msk                                  (0x01UL << SCU_SFSP8_1_EPUN_Pos)                          /*!< SCU SFSP8_1: EPUN Mask              */
+#define SCU_SFSP8_1_EHS_Pos                                   5                                                         /*!< SCU SFSP8_1: EHS Position           */
+#define SCU_SFSP8_1_EHS_Msk                                   (0x01UL << SCU_SFSP8_1_EHS_Pos)                           /*!< SCU SFSP8_1: EHS Mask               */
+#define SCU_SFSP8_1_EZI_Pos                                   6                                                         /*!< SCU SFSP8_1: EZI Position           */
+#define SCU_SFSP8_1_EZI_Msk                                   (0x01UL << SCU_SFSP8_1_EZI_Pos)                           /*!< SCU SFSP8_1: EZI Mask               */
+#define SCU_SFSP8_1_EHD_Pos                                   8                                                         /*!< SCU SFSP8_1: EHD Position           */
+#define SCU_SFSP8_1_EHD_Msk                                   (0x03UL << SCU_SFSP8_1_EHD_Pos)                           /*!< SCU SFSP8_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_2  ------------------------------------------
+#define SCU_SFSP8_2_MODE_Pos                                  0                                                         /*!< SCU SFSP8_2: MODE Position          */
+#define SCU_SFSP8_2_MODE_Msk                                  (0x07UL << SCU_SFSP8_2_MODE_Pos)                          /*!< SCU SFSP8_2: MODE Mask              */
+#define SCU_SFSP8_2_EPD_Pos                                   3                                                         /*!< SCU SFSP8_2: EPD Position           */
+#define SCU_SFSP8_2_EPD_Msk                                   (0x01UL << SCU_SFSP8_2_EPD_Pos)                           /*!< SCU SFSP8_2: EPD Mask               */
+#define SCU_SFSP8_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_2: EPUN Position          */
+#define SCU_SFSP8_2_EPUN_Msk                                  (0x01UL << SCU_SFSP8_2_EPUN_Pos)                          /*!< SCU SFSP8_2: EPUN Mask              */
+#define SCU_SFSP8_2_EHS_Pos                                   5                                                         /*!< SCU SFSP8_2: EHS Position           */
+#define SCU_SFSP8_2_EHS_Msk                                   (0x01UL << SCU_SFSP8_2_EHS_Pos)                           /*!< SCU SFSP8_2: EHS Mask               */
+#define SCU_SFSP8_2_EZI_Pos                                   6                                                         /*!< SCU SFSP8_2: EZI Position           */
+#define SCU_SFSP8_2_EZI_Msk                                   (0x01UL << SCU_SFSP8_2_EZI_Pos)                           /*!< SCU SFSP8_2: EZI Mask               */
+#define SCU_SFSP8_2_EHD_Pos                                   8                                                         /*!< SCU SFSP8_2: EHD Position           */
+#define SCU_SFSP8_2_EHD_Msk                                   (0x03UL << SCU_SFSP8_2_EHD_Pos)                           /*!< SCU SFSP8_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_3  ------------------------------------------
+#define SCU_SFSP8_3_MODE_Pos                                  0                                                         /*!< SCU SFSP8_3: MODE Position          */
+#define SCU_SFSP8_3_MODE_Msk                                  (0x07UL << SCU_SFSP8_3_MODE_Pos)                          /*!< SCU SFSP8_3: MODE Mask              */
+#define SCU_SFSP8_3_EPD_Pos                                   3                                                         /*!< SCU SFSP8_3: EPD Position           */
+#define SCU_SFSP8_3_EPD_Msk                                   (0x01UL << SCU_SFSP8_3_EPD_Pos)                           /*!< SCU SFSP8_3: EPD Mask               */
+#define SCU_SFSP8_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_3: EPUN Position          */
+#define SCU_SFSP8_3_EPUN_Msk                                  (0x01UL << SCU_SFSP8_3_EPUN_Pos)                          /*!< SCU SFSP8_3: EPUN Mask              */
+#define SCU_SFSP8_3_EHS_Pos                                   5                                                         /*!< SCU SFSP8_3: EHS Position           */
+#define SCU_SFSP8_3_EHS_Msk                                   (0x01UL << SCU_SFSP8_3_EHS_Pos)                           /*!< SCU SFSP8_3: EHS Mask               */
+#define SCU_SFSP8_3_EZI_Pos                                   6                                                         /*!< SCU SFSP8_3: EZI Position           */
+#define SCU_SFSP8_3_EZI_Msk                                   (0x01UL << SCU_SFSP8_3_EZI_Pos)                           /*!< SCU SFSP8_3: EZI Mask               */
+#define SCU_SFSP8_3_EHD_Pos                                   8                                                         /*!< SCU SFSP8_3: EHD Position           */
+#define SCU_SFSP8_3_EHD_Msk                                   (0x03UL << SCU_SFSP8_3_EHD_Pos)                           /*!< SCU SFSP8_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_4  ------------------------------------------
+#define SCU_SFSP8_4_MODE_Pos                                  0                                                         /*!< SCU SFSP8_4: MODE Position          */
+#define SCU_SFSP8_4_MODE_Msk                                  (0x07UL << SCU_SFSP8_4_MODE_Pos)                          /*!< SCU SFSP8_4: MODE Mask              */
+#define SCU_SFSP8_4_EPD_Pos                                   3                                                         /*!< SCU SFSP8_4: EPD Position           */
+#define SCU_SFSP8_4_EPD_Msk                                   (0x01UL << SCU_SFSP8_4_EPD_Pos)                           /*!< SCU SFSP8_4: EPD Mask               */
+#define SCU_SFSP8_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_4: EPUN Position          */
+#define SCU_SFSP8_4_EPUN_Msk                                  (0x01UL << SCU_SFSP8_4_EPUN_Pos)                          /*!< SCU SFSP8_4: EPUN Mask              */
+#define SCU_SFSP8_4_EHS_Pos                                   5                                                         /*!< SCU SFSP8_4: EHS Position           */
+#define SCU_SFSP8_4_EHS_Msk                                   (0x01UL << SCU_SFSP8_4_EHS_Pos)                           /*!< SCU SFSP8_4: EHS Mask               */
+#define SCU_SFSP8_4_EZI_Pos                                   6                                                         /*!< SCU SFSP8_4: EZI Position           */
+#define SCU_SFSP8_4_EZI_Msk                                   (0x01UL << SCU_SFSP8_4_EZI_Pos)                           /*!< SCU SFSP8_4: EZI Mask               */
+#define SCU_SFSP8_4_EHD_Pos                                   8                                                         /*!< SCU SFSP8_4: EHD Position           */
+#define SCU_SFSP8_4_EHD_Msk                                   (0x03UL << SCU_SFSP8_4_EHD_Pos)                           /*!< SCU SFSP8_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_5  ------------------------------------------
+#define SCU_SFSP8_5_MODE_Pos                                  0                                                         /*!< SCU SFSP8_5: MODE Position          */
+#define SCU_SFSP8_5_MODE_Msk                                  (0x07UL << SCU_SFSP8_5_MODE_Pos)                          /*!< SCU SFSP8_5: MODE Mask              */
+#define SCU_SFSP8_5_EPD_Pos                                   3                                                         /*!< SCU SFSP8_5: EPD Position           */
+#define SCU_SFSP8_5_EPD_Msk                                   (0x01UL << SCU_SFSP8_5_EPD_Pos)                           /*!< SCU SFSP8_5: EPD Mask               */
+#define SCU_SFSP8_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_5: EPUN Position          */
+#define SCU_SFSP8_5_EPUN_Msk                                  (0x01UL << SCU_SFSP8_5_EPUN_Pos)                          /*!< SCU SFSP8_5: EPUN Mask              */
+#define SCU_SFSP8_5_EHS_Pos                                   5                                                         /*!< SCU SFSP8_5: EHS Position           */
+#define SCU_SFSP8_5_EHS_Msk                                   (0x01UL << SCU_SFSP8_5_EHS_Pos)                           /*!< SCU SFSP8_5: EHS Mask               */
+#define SCU_SFSP8_5_EZI_Pos                                   6                                                         /*!< SCU SFSP8_5: EZI Position           */
+#define SCU_SFSP8_5_EZI_Msk                                   (0x01UL << SCU_SFSP8_5_EZI_Pos)                           /*!< SCU SFSP8_5: EZI Mask               */
+#define SCU_SFSP8_5_EHD_Pos                                   8                                                         /*!< SCU SFSP8_5: EHD Position           */
+#define SCU_SFSP8_5_EHD_Msk                                   (0x03UL << SCU_SFSP8_5_EHD_Pos)                           /*!< SCU SFSP8_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_6  ------------------------------------------
+#define SCU_SFSP8_6_MODE_Pos                                  0                                                         /*!< SCU SFSP8_6: MODE Position          */
+#define SCU_SFSP8_6_MODE_Msk                                  (0x07UL << SCU_SFSP8_6_MODE_Pos)                          /*!< SCU SFSP8_6: MODE Mask              */
+#define SCU_SFSP8_6_EPD_Pos                                   3                                                         /*!< SCU SFSP8_6: EPD Position           */
+#define SCU_SFSP8_6_EPD_Msk                                   (0x01UL << SCU_SFSP8_6_EPD_Pos)                           /*!< SCU SFSP8_6: EPD Mask               */
+#define SCU_SFSP8_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_6: EPUN Position          */
+#define SCU_SFSP8_6_EPUN_Msk                                  (0x01UL << SCU_SFSP8_6_EPUN_Pos)                          /*!< SCU SFSP8_6: EPUN Mask              */
+#define SCU_SFSP8_6_EHS_Pos                                   5                                                         /*!< SCU SFSP8_6: EHS Position           */
+#define SCU_SFSP8_6_EHS_Msk                                   (0x01UL << SCU_SFSP8_6_EHS_Pos)                           /*!< SCU SFSP8_6: EHS Mask               */
+#define SCU_SFSP8_6_EZI_Pos                                   6                                                         /*!< SCU SFSP8_6: EZI Position           */
+#define SCU_SFSP8_6_EZI_Msk                                   (0x01UL << SCU_SFSP8_6_EZI_Pos)                           /*!< SCU SFSP8_6: EZI Mask               */
+#define SCU_SFSP8_6_EHD_Pos                                   8                                                         /*!< SCU SFSP8_6: EHD Position           */
+#define SCU_SFSP8_6_EHD_Msk                                   (0x03UL << SCU_SFSP8_6_EHD_Pos)                           /*!< SCU SFSP8_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_7  ------------------------------------------
+#define SCU_SFSP8_7_MODE_Pos                                  0                                                         /*!< SCU SFSP8_7: MODE Position          */
+#define SCU_SFSP8_7_MODE_Msk                                  (0x07UL << SCU_SFSP8_7_MODE_Pos)                          /*!< SCU SFSP8_7: MODE Mask              */
+#define SCU_SFSP8_7_EPD_Pos                                   3                                                         /*!< SCU SFSP8_7: EPD Position           */
+#define SCU_SFSP8_7_EPD_Msk                                   (0x01UL << SCU_SFSP8_7_EPD_Pos)                           /*!< SCU SFSP8_7: EPD Mask               */
+#define SCU_SFSP8_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_7: EPUN Position          */
+#define SCU_SFSP8_7_EPUN_Msk                                  (0x01UL << SCU_SFSP8_7_EPUN_Pos)                          /*!< SCU SFSP8_7: EPUN Mask              */
+#define SCU_SFSP8_7_EHS_Pos                                   5                                                         /*!< SCU SFSP8_7: EHS Position           */
+#define SCU_SFSP8_7_EHS_Msk                                   (0x01UL << SCU_SFSP8_7_EHS_Pos)                           /*!< SCU SFSP8_7: EHS Mask               */
+#define SCU_SFSP8_7_EZI_Pos                                   6                                                         /*!< SCU SFSP8_7: EZI Position           */
+#define SCU_SFSP8_7_EZI_Msk                                   (0x01UL << SCU_SFSP8_7_EZI_Pos)                           /*!< SCU SFSP8_7: EZI Mask               */
+#define SCU_SFSP8_7_EHD_Pos                                   8                                                         /*!< SCU SFSP8_7: EHD Position           */
+#define SCU_SFSP8_7_EHD_Msk                                   (0x03UL << SCU_SFSP8_7_EHD_Pos)                           /*!< SCU SFSP8_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP8_8  ------------------------------------------
+#define SCU_SFSP8_8_MODE_Pos                                  0                                                         /*!< SCU SFSP8_8: MODE Position          */
+#define SCU_SFSP8_8_MODE_Msk                                  (0x07UL << SCU_SFSP8_8_MODE_Pos)                          /*!< SCU SFSP8_8: MODE Mask              */
+#define SCU_SFSP8_8_EPD_Pos                                   3                                                         /*!< SCU SFSP8_8: EPD Position           */
+#define SCU_SFSP8_8_EPD_Msk                                   (0x01UL << SCU_SFSP8_8_EPD_Pos)                           /*!< SCU SFSP8_8: EPD Mask               */
+#define SCU_SFSP8_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_8: EPUN Position          */
+#define SCU_SFSP8_8_EPUN_Msk                                  (0x01UL << SCU_SFSP8_8_EPUN_Pos)                          /*!< SCU SFSP8_8: EPUN Mask              */
+#define SCU_SFSP8_8_EHS_Pos                                   5                                                         /*!< SCU SFSP8_8: EHS Position           */
+#define SCU_SFSP8_8_EHS_Msk                                   (0x01UL << SCU_SFSP8_8_EHS_Pos)                           /*!< SCU SFSP8_8: EHS Mask               */
+#define SCU_SFSP8_8_EZI_Pos                                   6                                                         /*!< SCU SFSP8_8: EZI Position           */
+#define SCU_SFSP8_8_EZI_Msk                                   (0x01UL << SCU_SFSP8_8_EZI_Pos)                           /*!< SCU SFSP8_8: EZI Mask               */
+#define SCU_SFSP8_8_EHD_Pos                                   8                                                         /*!< SCU SFSP8_8: EHD Position           */
+#define SCU_SFSP8_8_EHD_Msk                                   (0x03UL << SCU_SFSP8_8_EHD_Pos)                           /*!< SCU SFSP8_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_0  ------------------------------------------
+#define SCU_SFSP9_0_MODE_Pos                                  0                                                         /*!< SCU SFSP9_0: MODE Position          */
+#define SCU_SFSP9_0_MODE_Msk                                  (0x07UL << SCU_SFSP9_0_MODE_Pos)                          /*!< SCU SFSP9_0: MODE Mask              */
+#define SCU_SFSP9_0_EPD_Pos                                   3                                                         /*!< SCU SFSP9_0: EPD Position           */
+#define SCU_SFSP9_0_EPD_Msk                                   (0x01UL << SCU_SFSP9_0_EPD_Pos)                           /*!< SCU SFSP9_0: EPD Mask               */
+#define SCU_SFSP9_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_0: EPUN Position          */
+#define SCU_SFSP9_0_EPUN_Msk                                  (0x01UL << SCU_SFSP9_0_EPUN_Pos)                          /*!< SCU SFSP9_0: EPUN Mask              */
+#define SCU_SFSP9_0_EHS_Pos                                   5                                                         /*!< SCU SFSP9_0: EHS Position           */
+#define SCU_SFSP9_0_EHS_Msk                                   (0x01UL << SCU_SFSP9_0_EHS_Pos)                           /*!< SCU SFSP9_0: EHS Mask               */
+#define SCU_SFSP9_0_EZI_Pos                                   6                                                         /*!< SCU SFSP9_0: EZI Position           */
+#define SCU_SFSP9_0_EZI_Msk                                   (0x01UL << SCU_SFSP9_0_EZI_Pos)                           /*!< SCU SFSP9_0: EZI Mask               */
+#define SCU_SFSP9_0_EHD_Pos                                   8                                                         /*!< SCU SFSP9_0: EHD Position           */
+#define SCU_SFSP9_0_EHD_Msk                                   (0x03UL << SCU_SFSP9_0_EHD_Pos)                           /*!< SCU SFSP9_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_1  ------------------------------------------
+#define SCU_SFSP9_1_MODE_Pos                                  0                                                         /*!< SCU SFSP9_1: MODE Position          */
+#define SCU_SFSP9_1_MODE_Msk                                  (0x07UL << SCU_SFSP9_1_MODE_Pos)                          /*!< SCU SFSP9_1: MODE Mask              */
+#define SCU_SFSP9_1_EPD_Pos                                   3                                                         /*!< SCU SFSP9_1: EPD Position           */
+#define SCU_SFSP9_1_EPD_Msk                                   (0x01UL << SCU_SFSP9_1_EPD_Pos)                           /*!< SCU SFSP9_1: EPD Mask               */
+#define SCU_SFSP9_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_1: EPUN Position          */
+#define SCU_SFSP9_1_EPUN_Msk                                  (0x01UL << SCU_SFSP9_1_EPUN_Pos)                          /*!< SCU SFSP9_1: EPUN Mask              */
+#define SCU_SFSP9_1_EHS_Pos                                   5                                                         /*!< SCU SFSP9_1: EHS Position           */
+#define SCU_SFSP9_1_EHS_Msk                                   (0x01UL << SCU_SFSP9_1_EHS_Pos)                           /*!< SCU SFSP9_1: EHS Mask               */
+#define SCU_SFSP9_1_EZI_Pos                                   6                                                         /*!< SCU SFSP9_1: EZI Position           */
+#define SCU_SFSP9_1_EZI_Msk                                   (0x01UL << SCU_SFSP9_1_EZI_Pos)                           /*!< SCU SFSP9_1: EZI Mask               */
+#define SCU_SFSP9_1_EHD_Pos                                   8                                                         /*!< SCU SFSP9_1: EHD Position           */
+#define SCU_SFSP9_1_EHD_Msk                                   (0x03UL << SCU_SFSP9_1_EHD_Pos)                           /*!< SCU SFSP9_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_2  ------------------------------------------
+#define SCU_SFSP9_2_MODE_Pos                                  0                                                         /*!< SCU SFSP9_2: MODE Position          */
+#define SCU_SFSP9_2_MODE_Msk                                  (0x07UL << SCU_SFSP9_2_MODE_Pos)                          /*!< SCU SFSP9_2: MODE Mask              */
+#define SCU_SFSP9_2_EPD_Pos                                   3                                                         /*!< SCU SFSP9_2: EPD Position           */
+#define SCU_SFSP9_2_EPD_Msk                                   (0x01UL << SCU_SFSP9_2_EPD_Pos)                           /*!< SCU SFSP9_2: EPD Mask               */
+#define SCU_SFSP9_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_2: EPUN Position          */
+#define SCU_SFSP9_2_EPUN_Msk                                  (0x01UL << SCU_SFSP9_2_EPUN_Pos)                          /*!< SCU SFSP9_2: EPUN Mask              */
+#define SCU_SFSP9_2_EHS_Pos                                   5                                                         /*!< SCU SFSP9_2: EHS Position           */
+#define SCU_SFSP9_2_EHS_Msk                                   (0x01UL << SCU_SFSP9_2_EHS_Pos)                           /*!< SCU SFSP9_2: EHS Mask               */
+#define SCU_SFSP9_2_EZI_Pos                                   6                                                         /*!< SCU SFSP9_2: EZI Position           */
+#define SCU_SFSP9_2_EZI_Msk                                   (0x01UL << SCU_SFSP9_2_EZI_Pos)                           /*!< SCU SFSP9_2: EZI Mask               */
+#define SCU_SFSP9_2_EHD_Pos                                   8                                                         /*!< SCU SFSP9_2: EHD Position           */
+#define SCU_SFSP9_2_EHD_Msk                                   (0x03UL << SCU_SFSP9_2_EHD_Pos)                           /*!< SCU SFSP9_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_3  ------------------------------------------
+#define SCU_SFSP9_3_MODE_Pos                                  0                                                         /*!< SCU SFSP9_3: MODE Position          */
+#define SCU_SFSP9_3_MODE_Msk                                  (0x07UL << SCU_SFSP9_3_MODE_Pos)                          /*!< SCU SFSP9_3: MODE Mask              */
+#define SCU_SFSP9_3_EPD_Pos                                   3                                                         /*!< SCU SFSP9_3: EPD Position           */
+#define SCU_SFSP9_3_EPD_Msk                                   (0x01UL << SCU_SFSP9_3_EPD_Pos)                           /*!< SCU SFSP9_3: EPD Mask               */
+#define SCU_SFSP9_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_3: EPUN Position          */
+#define SCU_SFSP9_3_EPUN_Msk                                  (0x01UL << SCU_SFSP9_3_EPUN_Pos)                          /*!< SCU SFSP9_3: EPUN Mask              */
+#define SCU_SFSP9_3_EHS_Pos                                   5                                                         /*!< SCU SFSP9_3: EHS Position           */
+#define SCU_SFSP9_3_EHS_Msk                                   (0x01UL << SCU_SFSP9_3_EHS_Pos)                           /*!< SCU SFSP9_3: EHS Mask               */
+#define SCU_SFSP9_3_EZI_Pos                                   6                                                         /*!< SCU SFSP9_3: EZI Position           */
+#define SCU_SFSP9_3_EZI_Msk                                   (0x01UL << SCU_SFSP9_3_EZI_Pos)                           /*!< SCU SFSP9_3: EZI Mask               */
+#define SCU_SFSP9_3_EHD_Pos                                   8                                                         /*!< SCU SFSP9_3: EHD Position           */
+#define SCU_SFSP9_3_EHD_Msk                                   (0x03UL << SCU_SFSP9_3_EHD_Pos)                           /*!< SCU SFSP9_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_4  ------------------------------------------
+#define SCU_SFSP9_4_MODE_Pos                                  0                                                         /*!< SCU SFSP9_4: MODE Position          */
+#define SCU_SFSP9_4_MODE_Msk                                  (0x07UL << SCU_SFSP9_4_MODE_Pos)                          /*!< SCU SFSP9_4: MODE Mask              */
+#define SCU_SFSP9_4_EPD_Pos                                   3                                                         /*!< SCU SFSP9_4: EPD Position           */
+#define SCU_SFSP9_4_EPD_Msk                                   (0x01UL << SCU_SFSP9_4_EPD_Pos)                           /*!< SCU SFSP9_4: EPD Mask               */
+#define SCU_SFSP9_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_4: EPUN Position          */
+#define SCU_SFSP9_4_EPUN_Msk                                  (0x01UL << SCU_SFSP9_4_EPUN_Pos)                          /*!< SCU SFSP9_4: EPUN Mask              */
+#define SCU_SFSP9_4_EHS_Pos                                   5                                                         /*!< SCU SFSP9_4: EHS Position           */
+#define SCU_SFSP9_4_EHS_Msk                                   (0x01UL << SCU_SFSP9_4_EHS_Pos)                           /*!< SCU SFSP9_4: EHS Mask               */
+#define SCU_SFSP9_4_EZI_Pos                                   6                                                         /*!< SCU SFSP9_4: EZI Position           */
+#define SCU_SFSP9_4_EZI_Msk                                   (0x01UL << SCU_SFSP9_4_EZI_Pos)                           /*!< SCU SFSP9_4: EZI Mask               */
+#define SCU_SFSP9_4_EHD_Pos                                   8                                                         /*!< SCU SFSP9_4: EHD Position           */
+#define SCU_SFSP9_4_EHD_Msk                                   (0x03UL << SCU_SFSP9_4_EHD_Pos)                           /*!< SCU SFSP9_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_5  ------------------------------------------
+#define SCU_SFSP9_5_MODE_Pos                                  0                                                         /*!< SCU SFSP9_5: MODE Position          */
+#define SCU_SFSP9_5_MODE_Msk                                  (0x07UL << SCU_SFSP9_5_MODE_Pos)                          /*!< SCU SFSP9_5: MODE Mask              */
+#define SCU_SFSP9_5_EPD_Pos                                   3                                                         /*!< SCU SFSP9_5: EPD Position           */
+#define SCU_SFSP9_5_EPD_Msk                                   (0x01UL << SCU_SFSP9_5_EPD_Pos)                           /*!< SCU SFSP9_5: EPD Mask               */
+#define SCU_SFSP9_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_5: EPUN Position          */
+#define SCU_SFSP9_5_EPUN_Msk                                  (0x01UL << SCU_SFSP9_5_EPUN_Pos)                          /*!< SCU SFSP9_5: EPUN Mask              */
+#define SCU_SFSP9_5_EHS_Pos                                   5                                                         /*!< SCU SFSP9_5: EHS Position           */
+#define SCU_SFSP9_5_EHS_Msk                                   (0x01UL << SCU_SFSP9_5_EHS_Pos)                           /*!< SCU SFSP9_5: EHS Mask               */
+#define SCU_SFSP9_5_EZI_Pos                                   6                                                         /*!< SCU SFSP9_5: EZI Position           */
+#define SCU_SFSP9_5_EZI_Msk                                   (0x01UL << SCU_SFSP9_5_EZI_Pos)                           /*!< SCU SFSP9_5: EZI Mask               */
+#define SCU_SFSP9_5_EHD_Pos                                   8                                                         /*!< SCU SFSP9_5: EHD Position           */
+#define SCU_SFSP9_5_EHD_Msk                                   (0x03UL << SCU_SFSP9_5_EHD_Pos)                           /*!< SCU SFSP9_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSP9_6  ------------------------------------------
+#define SCU_SFSP9_6_MODE_Pos                                  0                                                         /*!< SCU SFSP9_6: MODE Position          */
+#define SCU_SFSP9_6_MODE_Msk                                  (0x07UL << SCU_SFSP9_6_MODE_Pos)                          /*!< SCU SFSP9_6: MODE Mask              */
+#define SCU_SFSP9_6_EPD_Pos                                   3                                                         /*!< SCU SFSP9_6: EPD Position           */
+#define SCU_SFSP9_6_EPD_Msk                                   (0x01UL << SCU_SFSP9_6_EPD_Pos)                           /*!< SCU SFSP9_6: EPD Mask               */
+#define SCU_SFSP9_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_6: EPUN Position          */
+#define SCU_SFSP9_6_EPUN_Msk                                  (0x01UL << SCU_SFSP9_6_EPUN_Pos)                          /*!< SCU SFSP9_6: EPUN Mask              */
+#define SCU_SFSP9_6_EHS_Pos                                   5                                                         /*!< SCU SFSP9_6: EHS Position           */
+#define SCU_SFSP9_6_EHS_Msk                                   (0x01UL << SCU_SFSP9_6_EHS_Pos)                           /*!< SCU SFSP9_6: EHS Mask               */
+#define SCU_SFSP9_6_EZI_Pos                                   6                                                         /*!< SCU SFSP9_6: EZI Position           */
+#define SCU_SFSP9_6_EZI_Msk                                   (0x01UL << SCU_SFSP9_6_EZI_Pos)                           /*!< SCU SFSP9_6: EZI Mask               */
+#define SCU_SFSP9_6_EHD_Pos                                   8                                                         /*!< SCU SFSP9_6: EHD Position           */
+#define SCU_SFSP9_6_EHD_Msk                                   (0x03UL << SCU_SFSP9_6_EHD_Pos)                           /*!< SCU SFSP9_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_0  ------------------------------------------
+#define SCU_SFSPA_0_MODE_Pos                                  0                                                         /*!< SCU SFSPA_0: MODE Position          */
+#define SCU_SFSPA_0_MODE_Msk                                  (0x07UL << SCU_SFSPA_0_MODE_Pos)                          /*!< SCU SFSPA_0: MODE Mask              */
+#define SCU_SFSPA_0_EPD_Pos                                   3                                                         /*!< SCU SFSPA_0: EPD Position           */
+#define SCU_SFSPA_0_EPD_Msk                                   (0x01UL << SCU_SFSPA_0_EPD_Pos)                           /*!< SCU SFSPA_0: EPD Mask               */
+#define SCU_SFSPA_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_0: EPUN Position          */
+#define SCU_SFSPA_0_EPUN_Msk                                  (0x01UL << SCU_SFSPA_0_EPUN_Pos)                          /*!< SCU SFSPA_0: EPUN Mask              */
+#define SCU_SFSPA_0_EHS_Pos                                   5                                                         /*!< SCU SFSPA_0: EHS Position           */
+#define SCU_SFSPA_0_EHS_Msk                                   (0x01UL << SCU_SFSPA_0_EHS_Pos)                           /*!< SCU SFSPA_0: EHS Mask               */
+#define SCU_SFSPA_0_EZI_Pos                                   6                                                         /*!< SCU SFSPA_0: EZI Position           */
+#define SCU_SFSPA_0_EZI_Msk                                   (0x01UL << SCU_SFSPA_0_EZI_Pos)                           /*!< SCU SFSPA_0: EZI Mask               */
+#define SCU_SFSPA_0_EHD_Pos                                   8                                                         /*!< SCU SFSPA_0: EHD Position           */
+#define SCU_SFSPA_0_EHD_Msk                                   (0x03UL << SCU_SFSPA_0_EHD_Pos)                           /*!< SCU SFSPA_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_1  ------------------------------------------
+#define SCU_SFSPA_1_MODE_Pos                                  0                                                         /*!< SCU SFSPA_1: MODE Position          */
+#define SCU_SFSPA_1_MODE_Msk                                  (0x07UL << SCU_SFSPA_1_MODE_Pos)                          /*!< SCU SFSPA_1: MODE Mask              */
+#define SCU_SFSPA_1_EPD_Pos                                   3                                                         /*!< SCU SFSPA_1: EPD Position           */
+#define SCU_SFSPA_1_EPD_Msk                                   (0x01UL << SCU_SFSPA_1_EPD_Pos)                           /*!< SCU SFSPA_1: EPD Mask               */
+#define SCU_SFSPA_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_1: EPUN Position          */
+#define SCU_SFSPA_1_EPUN_Msk                                  (0x01UL << SCU_SFSPA_1_EPUN_Pos)                          /*!< SCU SFSPA_1: EPUN Mask              */
+#define SCU_SFSPA_1_EHS_Pos                                   5                                                         /*!< SCU SFSPA_1: EHS Position           */
+#define SCU_SFSPA_1_EHS_Msk                                   (0x01UL << SCU_SFSPA_1_EHS_Pos)                           /*!< SCU SFSPA_1: EHS Mask               */
+#define SCU_SFSPA_1_EZI_Pos                                   6                                                         /*!< SCU SFSPA_1: EZI Position           */
+#define SCU_SFSPA_1_EZI_Msk                                   (0x01UL << SCU_SFSPA_1_EZI_Pos)                           /*!< SCU SFSPA_1: EZI Mask               */
+#define SCU_SFSPA_1_EHD_Pos                                   8                                                         /*!< SCU SFSPA_1: EHD Position           */
+#define SCU_SFSPA_1_EHD_Msk                                   (0x03UL << SCU_SFSPA_1_EHD_Pos)                           /*!< SCU SFSPA_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_2  ------------------------------------------
+#define SCU_SFSPA_2_MODE_Pos                                  0                                                         /*!< SCU SFSPA_2: MODE Position          */
+#define SCU_SFSPA_2_MODE_Msk                                  (0x07UL << SCU_SFSPA_2_MODE_Pos)                          /*!< SCU SFSPA_2: MODE Mask              */
+#define SCU_SFSPA_2_EPD_Pos                                   3                                                         /*!< SCU SFSPA_2: EPD Position           */
+#define SCU_SFSPA_2_EPD_Msk                                   (0x01UL << SCU_SFSPA_2_EPD_Pos)                           /*!< SCU SFSPA_2: EPD Mask               */
+#define SCU_SFSPA_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_2: EPUN Position          */
+#define SCU_SFSPA_2_EPUN_Msk                                  (0x01UL << SCU_SFSPA_2_EPUN_Pos)                          /*!< SCU SFSPA_2: EPUN Mask              */
+#define SCU_SFSPA_2_EHS_Pos                                   5                                                         /*!< SCU SFSPA_2: EHS Position           */
+#define SCU_SFSPA_2_EHS_Msk                                   (0x01UL << SCU_SFSPA_2_EHS_Pos)                           /*!< SCU SFSPA_2: EHS Mask               */
+#define SCU_SFSPA_2_EZI_Pos                                   6                                                         /*!< SCU SFSPA_2: EZI Position           */
+#define SCU_SFSPA_2_EZI_Msk                                   (0x01UL << SCU_SFSPA_2_EZI_Pos)                           /*!< SCU SFSPA_2: EZI Mask               */
+#define SCU_SFSPA_2_EHD_Pos                                   8                                                         /*!< SCU SFSPA_2: EHD Position           */
+#define SCU_SFSPA_2_EHD_Msk                                   (0x03UL << SCU_SFSPA_2_EHD_Pos)                           /*!< SCU SFSPA_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_3  ------------------------------------------
+#define SCU_SFSPA_3_MODE_Pos                                  0                                                         /*!< SCU SFSPA_3: MODE Position          */
+#define SCU_SFSPA_3_MODE_Msk                                  (0x07UL << SCU_SFSPA_3_MODE_Pos)                          /*!< SCU SFSPA_3: MODE Mask              */
+#define SCU_SFSPA_3_EPD_Pos                                   3                                                         /*!< SCU SFSPA_3: EPD Position           */
+#define SCU_SFSPA_3_EPD_Msk                                   (0x01UL << SCU_SFSPA_3_EPD_Pos)                           /*!< SCU SFSPA_3: EPD Mask               */
+#define SCU_SFSPA_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_3: EPUN Position          */
+#define SCU_SFSPA_3_EPUN_Msk                                  (0x01UL << SCU_SFSPA_3_EPUN_Pos)                          /*!< SCU SFSPA_3: EPUN Mask              */
+#define SCU_SFSPA_3_EHS_Pos                                   5                                                         /*!< SCU SFSPA_3: EHS Position           */
+#define SCU_SFSPA_3_EHS_Msk                                   (0x01UL << SCU_SFSPA_3_EHS_Pos)                           /*!< SCU SFSPA_3: EHS Mask               */
+#define SCU_SFSPA_3_EZI_Pos                                   6                                                         /*!< SCU SFSPA_3: EZI Position           */
+#define SCU_SFSPA_3_EZI_Msk                                   (0x01UL << SCU_SFSPA_3_EZI_Pos)                           /*!< SCU SFSPA_3: EZI Mask               */
+#define SCU_SFSPA_3_EHD_Pos                                   8                                                         /*!< SCU SFSPA_3: EHD Position           */
+#define SCU_SFSPA_3_EHD_Msk                                   (0x03UL << SCU_SFSPA_3_EHD_Pos)                           /*!< SCU SFSPA_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPA_4  ------------------------------------------
+#define SCU_SFSPA_4_MODE_Pos                                  0                                                         /*!< SCU SFSPA_4: MODE Position          */
+#define SCU_SFSPA_4_MODE_Msk                                  (0x07UL << SCU_SFSPA_4_MODE_Pos)                          /*!< SCU SFSPA_4: MODE Mask              */
+#define SCU_SFSPA_4_EPD_Pos                                   3                                                         /*!< SCU SFSPA_4: EPD Position           */
+#define SCU_SFSPA_4_EPD_Msk                                   (0x01UL << SCU_SFSPA_4_EPD_Pos)                           /*!< SCU SFSPA_4: EPD Mask               */
+#define SCU_SFSPA_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_4: EPUN Position          */
+#define SCU_SFSPA_4_EPUN_Msk                                  (0x01UL << SCU_SFSPA_4_EPUN_Pos)                          /*!< SCU SFSPA_4: EPUN Mask              */
+#define SCU_SFSPA_4_EHS_Pos                                   5                                                         /*!< SCU SFSPA_4: EHS Position           */
+#define SCU_SFSPA_4_EHS_Msk                                   (0x01UL << SCU_SFSPA_4_EHS_Pos)                           /*!< SCU SFSPA_4: EHS Mask               */
+#define SCU_SFSPA_4_EZI_Pos                                   6                                                         /*!< SCU SFSPA_4: EZI Position           */
+#define SCU_SFSPA_4_EZI_Msk                                   (0x01UL << SCU_SFSPA_4_EZI_Pos)                           /*!< SCU SFSPA_4: EZI Mask               */
+#define SCU_SFSPA_4_EHD_Pos                                   8                                                         /*!< SCU SFSPA_4: EHD Position           */
+#define SCU_SFSPA_4_EHD_Msk                                   (0x03UL << SCU_SFSPA_4_EHD_Pos)                           /*!< SCU SFSPA_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_0  ------------------------------------------
+#define SCU_SFSPB_0_MODE_Pos                                  0                                                         /*!< SCU SFSPB_0: MODE Position          */
+#define SCU_SFSPB_0_MODE_Msk                                  (0x07UL << SCU_SFSPB_0_MODE_Pos)                          /*!< SCU SFSPB_0: MODE Mask              */
+#define SCU_SFSPB_0_EPD_Pos                                   3                                                         /*!< SCU SFSPB_0: EPD Position           */
+#define SCU_SFSPB_0_EPD_Msk                                   (0x01UL << SCU_SFSPB_0_EPD_Pos)                           /*!< SCU SFSPB_0: EPD Mask               */
+#define SCU_SFSPB_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_0: EPUN Position          */
+#define SCU_SFSPB_0_EPUN_Msk                                  (0x01UL << SCU_SFSPB_0_EPUN_Pos)                          /*!< SCU SFSPB_0: EPUN Mask              */
+#define SCU_SFSPB_0_EHS_Pos                                   5                                                         /*!< SCU SFSPB_0: EHS Position           */
+#define SCU_SFSPB_0_EHS_Msk                                   (0x01UL << SCU_SFSPB_0_EHS_Pos)                           /*!< SCU SFSPB_0: EHS Mask               */
+#define SCU_SFSPB_0_EZI_Pos                                   6                                                         /*!< SCU SFSPB_0: EZI Position           */
+#define SCU_SFSPB_0_EZI_Msk                                   (0x01UL << SCU_SFSPB_0_EZI_Pos)                           /*!< SCU SFSPB_0: EZI Mask               */
+#define SCU_SFSPB_0_EHD_Pos                                   8                                                         /*!< SCU SFSPB_0: EHD Position           */
+#define SCU_SFSPB_0_EHD_Msk                                   (0x03UL << SCU_SFSPB_0_EHD_Pos)                           /*!< SCU SFSPB_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_1  ------------------------------------------
+#define SCU_SFSPB_1_MODE_Pos                                  0                                                         /*!< SCU SFSPB_1: MODE Position          */
+#define SCU_SFSPB_1_MODE_Msk                                  (0x07UL << SCU_SFSPB_1_MODE_Pos)                          /*!< SCU SFSPB_1: MODE Mask              */
+#define SCU_SFSPB_1_EPD_Pos                                   3                                                         /*!< SCU SFSPB_1: EPD Position           */
+#define SCU_SFSPB_1_EPD_Msk                                   (0x01UL << SCU_SFSPB_1_EPD_Pos)                           /*!< SCU SFSPB_1: EPD Mask               */
+#define SCU_SFSPB_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_1: EPUN Position          */
+#define SCU_SFSPB_1_EPUN_Msk                                  (0x01UL << SCU_SFSPB_1_EPUN_Pos)                          /*!< SCU SFSPB_1: EPUN Mask              */
+#define SCU_SFSPB_1_EHS_Pos                                   5                                                         /*!< SCU SFSPB_1: EHS Position           */
+#define SCU_SFSPB_1_EHS_Msk                                   (0x01UL << SCU_SFSPB_1_EHS_Pos)                           /*!< SCU SFSPB_1: EHS Mask               */
+#define SCU_SFSPB_1_EZI_Pos                                   6                                                         /*!< SCU SFSPB_1: EZI Position           */
+#define SCU_SFSPB_1_EZI_Msk                                   (0x01UL << SCU_SFSPB_1_EZI_Pos)                           /*!< SCU SFSPB_1: EZI Mask               */
+#define SCU_SFSPB_1_EHD_Pos                                   8                                                         /*!< SCU SFSPB_1: EHD Position           */
+#define SCU_SFSPB_1_EHD_Msk                                   (0x03UL << SCU_SFSPB_1_EHD_Pos)                           /*!< SCU SFSPB_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_2  ------------------------------------------
+#define SCU_SFSPB_2_MODE_Pos                                  0                                                         /*!< SCU SFSPB_2: MODE Position          */
+#define SCU_SFSPB_2_MODE_Msk                                  (0x07UL << SCU_SFSPB_2_MODE_Pos)                          /*!< SCU SFSPB_2: MODE Mask              */
+#define SCU_SFSPB_2_EPD_Pos                                   3                                                         /*!< SCU SFSPB_2: EPD Position           */
+#define SCU_SFSPB_2_EPD_Msk                                   (0x01UL << SCU_SFSPB_2_EPD_Pos)                           /*!< SCU SFSPB_2: EPD Mask               */
+#define SCU_SFSPB_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_2: EPUN Position          */
+#define SCU_SFSPB_2_EPUN_Msk                                  (0x01UL << SCU_SFSPB_2_EPUN_Pos)                          /*!< SCU SFSPB_2: EPUN Mask              */
+#define SCU_SFSPB_2_EHS_Pos                                   5                                                         /*!< SCU SFSPB_2: EHS Position           */
+#define SCU_SFSPB_2_EHS_Msk                                   (0x01UL << SCU_SFSPB_2_EHS_Pos)                           /*!< SCU SFSPB_2: EHS Mask               */
+#define SCU_SFSPB_2_EZI_Pos                                   6                                                         /*!< SCU SFSPB_2: EZI Position           */
+#define SCU_SFSPB_2_EZI_Msk                                   (0x01UL << SCU_SFSPB_2_EZI_Pos)                           /*!< SCU SFSPB_2: EZI Mask               */
+#define SCU_SFSPB_2_EHD_Pos                                   8                                                         /*!< SCU SFSPB_2: EHD Position           */
+#define SCU_SFSPB_2_EHD_Msk                                   (0x03UL << SCU_SFSPB_2_EHD_Pos)                           /*!< SCU SFSPB_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_3  ------------------------------------------
+#define SCU_SFSPB_3_MODE_Pos                                  0                                                         /*!< SCU SFSPB_3: MODE Position          */
+#define SCU_SFSPB_3_MODE_Msk                                  (0x07UL << SCU_SFSPB_3_MODE_Pos)                          /*!< SCU SFSPB_3: MODE Mask              */
+#define SCU_SFSPB_3_EPD_Pos                                   3                                                         /*!< SCU SFSPB_3: EPD Position           */
+#define SCU_SFSPB_3_EPD_Msk                                   (0x01UL << SCU_SFSPB_3_EPD_Pos)                           /*!< SCU SFSPB_3: EPD Mask               */
+#define SCU_SFSPB_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_3: EPUN Position          */
+#define SCU_SFSPB_3_EPUN_Msk                                  (0x01UL << SCU_SFSPB_3_EPUN_Pos)                          /*!< SCU SFSPB_3: EPUN Mask              */
+#define SCU_SFSPB_3_EHS_Pos                                   5                                                         /*!< SCU SFSPB_3: EHS Position           */
+#define SCU_SFSPB_3_EHS_Msk                                   (0x01UL << SCU_SFSPB_3_EHS_Pos)                           /*!< SCU SFSPB_3: EHS Mask               */
+#define SCU_SFSPB_3_EZI_Pos                                   6                                                         /*!< SCU SFSPB_3: EZI Position           */
+#define SCU_SFSPB_3_EZI_Msk                                   (0x01UL << SCU_SFSPB_3_EZI_Pos)                           /*!< SCU SFSPB_3: EZI Mask               */
+#define SCU_SFSPB_3_EHD_Pos                                   8                                                         /*!< SCU SFSPB_3: EHD Position           */
+#define SCU_SFSPB_3_EHD_Msk                                   (0x03UL << SCU_SFSPB_3_EHD_Pos)                           /*!< SCU SFSPB_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_4  ------------------------------------------
+#define SCU_SFSPB_4_MODE_Pos                                  0                                                         /*!< SCU SFSPB_4: MODE Position          */
+#define SCU_SFSPB_4_MODE_Msk                                  (0x07UL << SCU_SFSPB_4_MODE_Pos)                          /*!< SCU SFSPB_4: MODE Mask              */
+#define SCU_SFSPB_4_EPD_Pos                                   3                                                         /*!< SCU SFSPB_4: EPD Position           */
+#define SCU_SFSPB_4_EPD_Msk                                   (0x01UL << SCU_SFSPB_4_EPD_Pos)                           /*!< SCU SFSPB_4: EPD Mask               */
+#define SCU_SFSPB_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_4: EPUN Position          */
+#define SCU_SFSPB_4_EPUN_Msk                                  (0x01UL << SCU_SFSPB_4_EPUN_Pos)                          /*!< SCU SFSPB_4: EPUN Mask              */
+#define SCU_SFSPB_4_EHS_Pos                                   5                                                         /*!< SCU SFSPB_4: EHS Position           */
+#define SCU_SFSPB_4_EHS_Msk                                   (0x01UL << SCU_SFSPB_4_EHS_Pos)                           /*!< SCU SFSPB_4: EHS Mask               */
+#define SCU_SFSPB_4_EZI_Pos                                   6                                                         /*!< SCU SFSPB_4: EZI Position           */
+#define SCU_SFSPB_4_EZI_Msk                                   (0x01UL << SCU_SFSPB_4_EZI_Pos)                           /*!< SCU SFSPB_4: EZI Mask               */
+#define SCU_SFSPB_4_EHD_Pos                                   8                                                         /*!< SCU SFSPB_4: EHD Position           */
+#define SCU_SFSPB_4_EHD_Msk                                   (0x03UL << SCU_SFSPB_4_EHD_Pos)                           /*!< SCU SFSPB_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_5  ------------------------------------------
+#define SCU_SFSPB_5_MODE_Pos                                  0                                                         /*!< SCU SFSPB_5: MODE Position          */
+#define SCU_SFSPB_5_MODE_Msk                                  (0x07UL << SCU_SFSPB_5_MODE_Pos)                          /*!< SCU SFSPB_5: MODE Mask              */
+#define SCU_SFSPB_5_EPD_Pos                                   3                                                         /*!< SCU SFSPB_5: EPD Position           */
+#define SCU_SFSPB_5_EPD_Msk                                   (0x01UL << SCU_SFSPB_5_EPD_Pos)                           /*!< SCU SFSPB_5: EPD Mask               */
+#define SCU_SFSPB_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_5: EPUN Position          */
+#define SCU_SFSPB_5_EPUN_Msk                                  (0x01UL << SCU_SFSPB_5_EPUN_Pos)                          /*!< SCU SFSPB_5: EPUN Mask              */
+#define SCU_SFSPB_5_EHS_Pos                                   5                                                         /*!< SCU SFSPB_5: EHS Position           */
+#define SCU_SFSPB_5_EHS_Msk                                   (0x01UL << SCU_SFSPB_5_EHS_Pos)                           /*!< SCU SFSPB_5: EHS Mask               */
+#define SCU_SFSPB_5_EZI_Pos                                   6                                                         /*!< SCU SFSPB_5: EZI Position           */
+#define SCU_SFSPB_5_EZI_Msk                                   (0x01UL << SCU_SFSPB_5_EZI_Pos)                           /*!< SCU SFSPB_5: EZI Mask               */
+#define SCU_SFSPB_5_EHD_Pos                                   8                                                         /*!< SCU SFSPB_5: EHD Position           */
+#define SCU_SFSPB_5_EHD_Msk                                   (0x03UL << SCU_SFSPB_5_EHD_Pos)                           /*!< SCU SFSPB_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPB_6  ------------------------------------------
+#define SCU_SFSPB_6_MODE_Pos                                  0                                                         /*!< SCU SFSPB_6: MODE Position          */
+#define SCU_SFSPB_6_MODE_Msk                                  (0x07UL << SCU_SFSPB_6_MODE_Pos)                          /*!< SCU SFSPB_6: MODE Mask              */
+#define SCU_SFSPB_6_EPD_Pos                                   3                                                         /*!< SCU SFSPB_6: EPD Position           */
+#define SCU_SFSPB_6_EPD_Msk                                   (0x01UL << SCU_SFSPB_6_EPD_Pos)                           /*!< SCU SFSPB_6: EPD Mask               */
+#define SCU_SFSPB_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_6: EPUN Position          */
+#define SCU_SFSPB_6_EPUN_Msk                                  (0x01UL << SCU_SFSPB_6_EPUN_Pos)                          /*!< SCU SFSPB_6: EPUN Mask              */
+#define SCU_SFSPB_6_EHS_Pos                                   5                                                         /*!< SCU SFSPB_6: EHS Position           */
+#define SCU_SFSPB_6_EHS_Msk                                   (0x01UL << SCU_SFSPB_6_EHS_Pos)                           /*!< SCU SFSPB_6: EHS Mask               */
+#define SCU_SFSPB_6_EZI_Pos                                   6                                                         /*!< SCU SFSPB_6: EZI Position           */
+#define SCU_SFSPB_6_EZI_Msk                                   (0x01UL << SCU_SFSPB_6_EZI_Pos)                           /*!< SCU SFSPB_6: EZI Mask               */
+#define SCU_SFSPB_6_EHD_Pos                                   8                                                         /*!< SCU SFSPB_6: EHD Position           */
+#define SCU_SFSPB_6_EHD_Msk                                   (0x03UL << SCU_SFSPB_6_EHD_Pos)                           /*!< SCU SFSPB_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_0  ------------------------------------------
+#define SCU_SFSPC_0_MODE_Pos                                  0                                                         /*!< SCU SFSPC_0: MODE Position          */
+#define SCU_SFSPC_0_MODE_Msk                                  (0x07UL << SCU_SFSPC_0_MODE_Pos)                          /*!< SCU SFSPC_0: MODE Mask              */
+#define SCU_SFSPC_0_EPD_Pos                                   3                                                         /*!< SCU SFSPC_0: EPD Position           */
+#define SCU_SFSPC_0_EPD_Msk                                   (0x01UL << SCU_SFSPC_0_EPD_Pos)                           /*!< SCU SFSPC_0: EPD Mask               */
+#define SCU_SFSPC_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_0: EPUN Position          */
+#define SCU_SFSPC_0_EPUN_Msk                                  (0x01UL << SCU_SFSPC_0_EPUN_Pos)                          /*!< SCU SFSPC_0: EPUN Mask              */
+#define SCU_SFSPC_0_EHS_Pos                                   5                                                         /*!< SCU SFSPC_0: EHS Position           */
+#define SCU_SFSPC_0_EHS_Msk                                   (0x01UL << SCU_SFSPC_0_EHS_Pos)                           /*!< SCU SFSPC_0: EHS Mask               */
+#define SCU_SFSPC_0_EZI_Pos                                   6                                                         /*!< SCU SFSPC_0: EZI Position           */
+#define SCU_SFSPC_0_EZI_Msk                                   (0x01UL << SCU_SFSPC_0_EZI_Pos)                           /*!< SCU SFSPC_0: EZI Mask               */
+#define SCU_SFSPC_0_EHD_Pos                                   8                                                         /*!< SCU SFSPC_0: EHD Position           */
+#define SCU_SFSPC_0_EHD_Msk                                   (0x03UL << SCU_SFSPC_0_EHD_Pos)                           /*!< SCU SFSPC_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_1  ------------------------------------------
+#define SCU_SFSPC_1_MODE_Pos                                  0                                                         /*!< SCU SFSPC_1: MODE Position          */
+#define SCU_SFSPC_1_MODE_Msk                                  (0x07UL << SCU_SFSPC_1_MODE_Pos)                          /*!< SCU SFSPC_1: MODE Mask              */
+#define SCU_SFSPC_1_EPD_Pos                                   3                                                         /*!< SCU SFSPC_1: EPD Position           */
+#define SCU_SFSPC_1_EPD_Msk                                   (0x01UL << SCU_SFSPC_1_EPD_Pos)                           /*!< SCU SFSPC_1: EPD Mask               */
+#define SCU_SFSPC_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_1: EPUN Position          */
+#define SCU_SFSPC_1_EPUN_Msk                                  (0x01UL << SCU_SFSPC_1_EPUN_Pos)                          /*!< SCU SFSPC_1: EPUN Mask              */
+#define SCU_SFSPC_1_EHS_Pos                                   5                                                         /*!< SCU SFSPC_1: EHS Position           */
+#define SCU_SFSPC_1_EHS_Msk                                   (0x01UL << SCU_SFSPC_1_EHS_Pos)                           /*!< SCU SFSPC_1: EHS Mask               */
+#define SCU_SFSPC_1_EZI_Pos                                   6                                                         /*!< SCU SFSPC_1: EZI Position           */
+#define SCU_SFSPC_1_EZI_Msk                                   (0x01UL << SCU_SFSPC_1_EZI_Pos)                           /*!< SCU SFSPC_1: EZI Mask               */
+#define SCU_SFSPC_1_EHD_Pos                                   8                                                         /*!< SCU SFSPC_1: EHD Position           */
+#define SCU_SFSPC_1_EHD_Msk                                   (0x03UL << SCU_SFSPC_1_EHD_Pos)                           /*!< SCU SFSPC_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_2  ------------------------------------------
+#define SCU_SFSPC_2_MODE_Pos                                  0                                                         /*!< SCU SFSPC_2: MODE Position          */
+#define SCU_SFSPC_2_MODE_Msk                                  (0x07UL << SCU_SFSPC_2_MODE_Pos)                          /*!< SCU SFSPC_2: MODE Mask              */
+#define SCU_SFSPC_2_EPD_Pos                                   3                                                         /*!< SCU SFSPC_2: EPD Position           */
+#define SCU_SFSPC_2_EPD_Msk                                   (0x01UL << SCU_SFSPC_2_EPD_Pos)                           /*!< SCU SFSPC_2: EPD Mask               */
+#define SCU_SFSPC_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_2: EPUN Position          */
+#define SCU_SFSPC_2_EPUN_Msk                                  (0x01UL << SCU_SFSPC_2_EPUN_Pos)                          /*!< SCU SFSPC_2: EPUN Mask              */
+#define SCU_SFSPC_2_EHS_Pos                                   5                                                         /*!< SCU SFSPC_2: EHS Position           */
+#define SCU_SFSPC_2_EHS_Msk                                   (0x01UL << SCU_SFSPC_2_EHS_Pos)                           /*!< SCU SFSPC_2: EHS Mask               */
+#define SCU_SFSPC_2_EZI_Pos                                   6                                                         /*!< SCU SFSPC_2: EZI Position           */
+#define SCU_SFSPC_2_EZI_Msk                                   (0x01UL << SCU_SFSPC_2_EZI_Pos)                           /*!< SCU SFSPC_2: EZI Mask               */
+#define SCU_SFSPC_2_EHD_Pos                                   8                                                         /*!< SCU SFSPC_2: EHD Position           */
+#define SCU_SFSPC_2_EHD_Msk                                   (0x03UL << SCU_SFSPC_2_EHD_Pos)                           /*!< SCU SFSPC_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_3  ------------------------------------------
+#define SCU_SFSPC_3_MODE_Pos                                  0                                                         /*!< SCU SFSPC_3: MODE Position          */
+#define SCU_SFSPC_3_MODE_Msk                                  (0x07UL << SCU_SFSPC_3_MODE_Pos)                          /*!< SCU SFSPC_3: MODE Mask              */
+#define SCU_SFSPC_3_EPD_Pos                                   3                                                         /*!< SCU SFSPC_3: EPD Position           */
+#define SCU_SFSPC_3_EPD_Msk                                   (0x01UL << SCU_SFSPC_3_EPD_Pos)                           /*!< SCU SFSPC_3: EPD Mask               */
+#define SCU_SFSPC_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_3: EPUN Position          */
+#define SCU_SFSPC_3_EPUN_Msk                                  (0x01UL << SCU_SFSPC_3_EPUN_Pos)                          /*!< SCU SFSPC_3: EPUN Mask              */
+#define SCU_SFSPC_3_EHS_Pos                                   5                                                         /*!< SCU SFSPC_3: EHS Position           */
+#define SCU_SFSPC_3_EHS_Msk                                   (0x01UL << SCU_SFSPC_3_EHS_Pos)                           /*!< SCU SFSPC_3: EHS Mask               */
+#define SCU_SFSPC_3_EZI_Pos                                   6                                                         /*!< SCU SFSPC_3: EZI Position           */
+#define SCU_SFSPC_3_EZI_Msk                                   (0x01UL << SCU_SFSPC_3_EZI_Pos)                           /*!< SCU SFSPC_3: EZI Mask               */
+#define SCU_SFSPC_3_EHD_Pos                                   8                                                         /*!< SCU SFSPC_3: EHD Position           */
+#define SCU_SFSPC_3_EHD_Msk                                   (0x03UL << SCU_SFSPC_3_EHD_Pos)                           /*!< SCU SFSPC_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_4  ------------------------------------------
+#define SCU_SFSPC_4_MODE_Pos                                  0                                                         /*!< SCU SFSPC_4: MODE Position          */
+#define SCU_SFSPC_4_MODE_Msk                                  (0x07UL << SCU_SFSPC_4_MODE_Pos)                          /*!< SCU SFSPC_4: MODE Mask              */
+#define SCU_SFSPC_4_EPD_Pos                                   3                                                         /*!< SCU SFSPC_4: EPD Position           */
+#define SCU_SFSPC_4_EPD_Msk                                   (0x01UL << SCU_SFSPC_4_EPD_Pos)                           /*!< SCU SFSPC_4: EPD Mask               */
+#define SCU_SFSPC_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_4: EPUN Position          */
+#define SCU_SFSPC_4_EPUN_Msk                                  (0x01UL << SCU_SFSPC_4_EPUN_Pos)                          /*!< SCU SFSPC_4: EPUN Mask              */
+#define SCU_SFSPC_4_EHS_Pos                                   5                                                         /*!< SCU SFSPC_4: EHS Position           */
+#define SCU_SFSPC_4_EHS_Msk                                   (0x01UL << SCU_SFSPC_4_EHS_Pos)                           /*!< SCU SFSPC_4: EHS Mask               */
+#define SCU_SFSPC_4_EZI_Pos                                   6                                                         /*!< SCU SFSPC_4: EZI Position           */
+#define SCU_SFSPC_4_EZI_Msk                                   (0x01UL << SCU_SFSPC_4_EZI_Pos)                           /*!< SCU SFSPC_4: EZI Mask               */
+#define SCU_SFSPC_4_EHD_Pos                                   8                                                         /*!< SCU SFSPC_4: EHD Position           */
+#define SCU_SFSPC_4_EHD_Msk                                   (0x03UL << SCU_SFSPC_4_EHD_Pos)                           /*!< SCU SFSPC_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_5  ------------------------------------------
+#define SCU_SFSPC_5_MODE_Pos                                  0                                                         /*!< SCU SFSPC_5: MODE Position          */
+#define SCU_SFSPC_5_MODE_Msk                                  (0x07UL << SCU_SFSPC_5_MODE_Pos)                          /*!< SCU SFSPC_5: MODE Mask              */
+#define SCU_SFSPC_5_EPD_Pos                                   3                                                         /*!< SCU SFSPC_5: EPD Position           */
+#define SCU_SFSPC_5_EPD_Msk                                   (0x01UL << SCU_SFSPC_5_EPD_Pos)                           /*!< SCU SFSPC_5: EPD Mask               */
+#define SCU_SFSPC_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_5: EPUN Position          */
+#define SCU_SFSPC_5_EPUN_Msk                                  (0x01UL << SCU_SFSPC_5_EPUN_Pos)                          /*!< SCU SFSPC_5: EPUN Mask              */
+#define SCU_SFSPC_5_EHS_Pos                                   5                                                         /*!< SCU SFSPC_5: EHS Position           */
+#define SCU_SFSPC_5_EHS_Msk                                   (0x01UL << SCU_SFSPC_5_EHS_Pos)                           /*!< SCU SFSPC_5: EHS Mask               */
+#define SCU_SFSPC_5_EZI_Pos                                   6                                                         /*!< SCU SFSPC_5: EZI Position           */
+#define SCU_SFSPC_5_EZI_Msk                                   (0x01UL << SCU_SFSPC_5_EZI_Pos)                           /*!< SCU SFSPC_5: EZI Mask               */
+#define SCU_SFSPC_5_EHD_Pos                                   8                                                         /*!< SCU SFSPC_5: EHD Position           */
+#define SCU_SFSPC_5_EHD_Msk                                   (0x03UL << SCU_SFSPC_5_EHD_Pos)                           /*!< SCU SFSPC_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_6  ------------------------------------------
+#define SCU_SFSPC_6_MODE_Pos                                  0                                                         /*!< SCU SFSPC_6: MODE Position          */
+#define SCU_SFSPC_6_MODE_Msk                                  (0x07UL << SCU_SFSPC_6_MODE_Pos)                          /*!< SCU SFSPC_6: MODE Mask              */
+#define SCU_SFSPC_6_EPD_Pos                                   3                                                         /*!< SCU SFSPC_6: EPD Position           */
+#define SCU_SFSPC_6_EPD_Msk                                   (0x01UL << SCU_SFSPC_6_EPD_Pos)                           /*!< SCU SFSPC_6: EPD Mask               */
+#define SCU_SFSPC_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_6: EPUN Position          */
+#define SCU_SFSPC_6_EPUN_Msk                                  (0x01UL << SCU_SFSPC_6_EPUN_Pos)                          /*!< SCU SFSPC_6: EPUN Mask              */
+#define SCU_SFSPC_6_EHS_Pos                                   5                                                         /*!< SCU SFSPC_6: EHS Position           */
+#define SCU_SFSPC_6_EHS_Msk                                   (0x01UL << SCU_SFSPC_6_EHS_Pos)                           /*!< SCU SFSPC_6: EHS Mask               */
+#define SCU_SFSPC_6_EZI_Pos                                   6                                                         /*!< SCU SFSPC_6: EZI Position           */
+#define SCU_SFSPC_6_EZI_Msk                                   (0x01UL << SCU_SFSPC_6_EZI_Pos)                           /*!< SCU SFSPC_6: EZI Mask               */
+#define SCU_SFSPC_6_EHD_Pos                                   8                                                         /*!< SCU SFSPC_6: EHD Position           */
+#define SCU_SFSPC_6_EHD_Msk                                   (0x03UL << SCU_SFSPC_6_EHD_Pos)                           /*!< SCU SFSPC_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_7  ------------------------------------------
+#define SCU_SFSPC_7_MODE_Pos                                  0                                                         /*!< SCU SFSPC_7: MODE Position          */
+#define SCU_SFSPC_7_MODE_Msk                                  (0x07UL << SCU_SFSPC_7_MODE_Pos)                          /*!< SCU SFSPC_7: MODE Mask              */
+#define SCU_SFSPC_7_EPD_Pos                                   3                                                         /*!< SCU SFSPC_7: EPD Position           */
+#define SCU_SFSPC_7_EPD_Msk                                   (0x01UL << SCU_SFSPC_7_EPD_Pos)                           /*!< SCU SFSPC_7: EPD Mask               */
+#define SCU_SFSPC_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_7: EPUN Position          */
+#define SCU_SFSPC_7_EPUN_Msk                                  (0x01UL << SCU_SFSPC_7_EPUN_Pos)                          /*!< SCU SFSPC_7: EPUN Mask              */
+#define SCU_SFSPC_7_EHS_Pos                                   5                                                         /*!< SCU SFSPC_7: EHS Position           */
+#define SCU_SFSPC_7_EHS_Msk                                   (0x01UL << SCU_SFSPC_7_EHS_Pos)                           /*!< SCU SFSPC_7: EHS Mask               */
+#define SCU_SFSPC_7_EZI_Pos                                   6                                                         /*!< SCU SFSPC_7: EZI Position           */
+#define SCU_SFSPC_7_EZI_Msk                                   (0x01UL << SCU_SFSPC_7_EZI_Pos)                           /*!< SCU SFSPC_7: EZI Mask               */
+#define SCU_SFSPC_7_EHD_Pos                                   8                                                         /*!< SCU SFSPC_7: EHD Position           */
+#define SCU_SFSPC_7_EHD_Msk                                   (0x03UL << SCU_SFSPC_7_EHD_Pos)                           /*!< SCU SFSPC_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_8  ------------------------------------------
+#define SCU_SFSPC_8_MODE_Pos                                  0                                                         /*!< SCU SFSPC_8: MODE Position          */
+#define SCU_SFSPC_8_MODE_Msk                                  (0x07UL << SCU_SFSPC_8_MODE_Pos)                          /*!< SCU SFSPC_8: MODE Mask              */
+#define SCU_SFSPC_8_EPD_Pos                                   3                                                         /*!< SCU SFSPC_8: EPD Position           */
+#define SCU_SFSPC_8_EPD_Msk                                   (0x01UL << SCU_SFSPC_8_EPD_Pos)                           /*!< SCU SFSPC_8: EPD Mask               */
+#define SCU_SFSPC_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_8: EPUN Position          */
+#define SCU_SFSPC_8_EPUN_Msk                                  (0x01UL << SCU_SFSPC_8_EPUN_Pos)                          /*!< SCU SFSPC_8: EPUN Mask              */
+#define SCU_SFSPC_8_EHS_Pos                                   5                                                         /*!< SCU SFSPC_8: EHS Position           */
+#define SCU_SFSPC_8_EHS_Msk                                   (0x01UL << SCU_SFSPC_8_EHS_Pos)                           /*!< SCU SFSPC_8: EHS Mask               */
+#define SCU_SFSPC_8_EZI_Pos                                   6                                                         /*!< SCU SFSPC_8: EZI Position           */
+#define SCU_SFSPC_8_EZI_Msk                                   (0x01UL << SCU_SFSPC_8_EZI_Pos)                           /*!< SCU SFSPC_8: EZI Mask               */
+#define SCU_SFSPC_8_EHD_Pos                                   8                                                         /*!< SCU SFSPC_8: EHD Position           */
+#define SCU_SFSPC_8_EHD_Msk                                   (0x03UL << SCU_SFSPC_8_EHD_Pos)                           /*!< SCU SFSPC_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPC_9  ------------------------------------------
+#define SCU_SFSPC_9_MODE_Pos                                  0                                                         /*!< SCU SFSPC_9: MODE Position          */
+#define SCU_SFSPC_9_MODE_Msk                                  (0x07UL << SCU_SFSPC_9_MODE_Pos)                          /*!< SCU SFSPC_9: MODE Mask              */
+#define SCU_SFSPC_9_EPD_Pos                                   3                                                         /*!< SCU SFSPC_9: EPD Position           */
+#define SCU_SFSPC_9_EPD_Msk                                   (0x01UL << SCU_SFSPC_9_EPD_Pos)                           /*!< SCU SFSPC_9: EPD Mask               */
+#define SCU_SFSPC_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_9: EPUN Position          */
+#define SCU_SFSPC_9_EPUN_Msk                                  (0x01UL << SCU_SFSPC_9_EPUN_Pos)                          /*!< SCU SFSPC_9: EPUN Mask              */
+#define SCU_SFSPC_9_EHS_Pos                                   5                                                         /*!< SCU SFSPC_9: EHS Position           */
+#define SCU_SFSPC_9_EHS_Msk                                   (0x01UL << SCU_SFSPC_9_EHS_Pos)                           /*!< SCU SFSPC_9: EHS Mask               */
+#define SCU_SFSPC_9_EZI_Pos                                   6                                                         /*!< SCU SFSPC_9: EZI Position           */
+#define SCU_SFSPC_9_EZI_Msk                                   (0x01UL << SCU_SFSPC_9_EZI_Pos)                           /*!< SCU SFSPC_9: EZI Mask               */
+#define SCU_SFSPC_9_EHD_Pos                                   8                                                         /*!< SCU SFSPC_9: EHD Position           */
+#define SCU_SFSPC_9_EHD_Msk                                   (0x03UL << SCU_SFSPC_9_EHD_Pos)                           /*!< SCU SFSPC_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPC_10  ------------------------------------------
+#define SCU_SFSPC_10_MODE_Pos                                 0                                                         /*!< SCU SFSPC_10: MODE Position         */
+#define SCU_SFSPC_10_MODE_Msk                                 (0x07UL << SCU_SFSPC_10_MODE_Pos)                         /*!< SCU SFSPC_10: MODE Mask             */
+#define SCU_SFSPC_10_EPD_Pos                                  3                                                         /*!< SCU SFSPC_10: EPD Position          */
+#define SCU_SFSPC_10_EPD_Msk                                  (0x01UL << SCU_SFSPC_10_EPD_Pos)                          /*!< SCU SFSPC_10: EPD Mask              */
+#define SCU_SFSPC_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_10: EPUN Position         */
+#define SCU_SFSPC_10_EPUN_Msk                                 (0x01UL << SCU_SFSPC_10_EPUN_Pos)                         /*!< SCU SFSPC_10: EPUN Mask             */
+#define SCU_SFSPC_10_EHS_Pos                                  5                                                         /*!< SCU SFSPC_10: EHS Position          */
+#define SCU_SFSPC_10_EHS_Msk                                  (0x01UL << SCU_SFSPC_10_EHS_Pos)                          /*!< SCU SFSPC_10: EHS Mask              */
+#define SCU_SFSPC_10_EZI_Pos                                  6                                                         /*!< SCU SFSPC_10: EZI Position          */
+#define SCU_SFSPC_10_EZI_Msk                                  (0x01UL << SCU_SFSPC_10_EZI_Pos)                          /*!< SCU SFSPC_10: EZI Mask              */
+#define SCU_SFSPC_10_EHD_Pos                                  8                                                         /*!< SCU SFSPC_10: EHD Position          */
+#define SCU_SFSPC_10_EHD_Msk                                  (0x03UL << SCU_SFSPC_10_EHD_Pos)                          /*!< SCU SFSPC_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_11  ------------------------------------------
+#define SCU_SFSPC_11_MODE_Pos                                 0                                                         /*!< SCU SFSPC_11: MODE Position         */
+#define SCU_SFSPC_11_MODE_Msk                                 (0x07UL << SCU_SFSPC_11_MODE_Pos)                         /*!< SCU SFSPC_11: MODE Mask             */
+#define SCU_SFSPC_11_EPD_Pos                                  3                                                         /*!< SCU SFSPC_11: EPD Position          */
+#define SCU_SFSPC_11_EPD_Msk                                  (0x01UL << SCU_SFSPC_11_EPD_Pos)                          /*!< SCU SFSPC_11: EPD Mask              */
+#define SCU_SFSPC_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_11: EPUN Position         */
+#define SCU_SFSPC_11_EPUN_Msk                                 (0x01UL << SCU_SFSPC_11_EPUN_Pos)                         /*!< SCU SFSPC_11: EPUN Mask             */
+#define SCU_SFSPC_11_EHS_Pos                                  5                                                         /*!< SCU SFSPC_11: EHS Position          */
+#define SCU_SFSPC_11_EHS_Msk                                  (0x01UL << SCU_SFSPC_11_EHS_Pos)                          /*!< SCU SFSPC_11: EHS Mask              */
+#define SCU_SFSPC_11_EZI_Pos                                  6                                                         /*!< SCU SFSPC_11: EZI Position          */
+#define SCU_SFSPC_11_EZI_Msk                                  (0x01UL << SCU_SFSPC_11_EZI_Pos)                          /*!< SCU SFSPC_11: EZI Mask              */
+#define SCU_SFSPC_11_EHD_Pos                                  8                                                         /*!< SCU SFSPC_11: EHD Position          */
+#define SCU_SFSPC_11_EHD_Msk                                  (0x03UL << SCU_SFSPC_11_EHD_Pos)                          /*!< SCU SFSPC_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_12  ------------------------------------------
+#define SCU_SFSPC_12_MODE_Pos                                 0                                                         /*!< SCU SFSPC_12: MODE Position         */
+#define SCU_SFSPC_12_MODE_Msk                                 (0x07UL << SCU_SFSPC_12_MODE_Pos)                         /*!< SCU SFSPC_12: MODE Mask             */
+#define SCU_SFSPC_12_EPD_Pos                                  3                                                         /*!< SCU SFSPC_12: EPD Position          */
+#define SCU_SFSPC_12_EPD_Msk                                  (0x01UL << SCU_SFSPC_12_EPD_Pos)                          /*!< SCU SFSPC_12: EPD Mask              */
+#define SCU_SFSPC_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_12: EPUN Position         */
+#define SCU_SFSPC_12_EPUN_Msk                                 (0x01UL << SCU_SFSPC_12_EPUN_Pos)                         /*!< SCU SFSPC_12: EPUN Mask             */
+#define SCU_SFSPC_12_EHS_Pos                                  5                                                         /*!< SCU SFSPC_12: EHS Position          */
+#define SCU_SFSPC_12_EHS_Msk                                  (0x01UL << SCU_SFSPC_12_EHS_Pos)                          /*!< SCU SFSPC_12: EHS Mask              */
+#define SCU_SFSPC_12_EZI_Pos                                  6                                                         /*!< SCU SFSPC_12: EZI Position          */
+#define SCU_SFSPC_12_EZI_Msk                                  (0x01UL << SCU_SFSPC_12_EZI_Pos)                          /*!< SCU SFSPC_12: EZI Mask              */
+#define SCU_SFSPC_12_EHD_Pos                                  8                                                         /*!< SCU SFSPC_12: EHD Position          */
+#define SCU_SFSPC_12_EHD_Msk                                  (0x03UL << SCU_SFSPC_12_EHD_Pos)                          /*!< SCU SFSPC_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_13  ------------------------------------------
+#define SCU_SFSPC_13_MODE_Pos                                 0                                                         /*!< SCU SFSPC_13: MODE Position         */
+#define SCU_SFSPC_13_MODE_Msk                                 (0x07UL << SCU_SFSPC_13_MODE_Pos)                         /*!< SCU SFSPC_13: MODE Mask             */
+#define SCU_SFSPC_13_EPD_Pos                                  3                                                         /*!< SCU SFSPC_13: EPD Position          */
+#define SCU_SFSPC_13_EPD_Msk                                  (0x01UL << SCU_SFSPC_13_EPD_Pos)                          /*!< SCU SFSPC_13: EPD Mask              */
+#define SCU_SFSPC_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_13: EPUN Position         */
+#define SCU_SFSPC_13_EPUN_Msk                                 (0x01UL << SCU_SFSPC_13_EPUN_Pos)                         /*!< SCU SFSPC_13: EPUN Mask             */
+#define SCU_SFSPC_13_EHS_Pos                                  5                                                         /*!< SCU SFSPC_13: EHS Position          */
+#define SCU_SFSPC_13_EHS_Msk                                  (0x01UL << SCU_SFSPC_13_EHS_Pos)                          /*!< SCU SFSPC_13: EHS Mask              */
+#define SCU_SFSPC_13_EZI_Pos                                  6                                                         /*!< SCU SFSPC_13: EZI Position          */
+#define SCU_SFSPC_13_EZI_Msk                                  (0x01UL << SCU_SFSPC_13_EZI_Pos)                          /*!< SCU SFSPC_13: EZI Mask              */
+#define SCU_SFSPC_13_EHD_Pos                                  8                                                         /*!< SCU SFSPC_13: EHD Position          */
+#define SCU_SFSPC_13_EHD_Msk                                  (0x03UL << SCU_SFSPC_13_EHD_Pos)                          /*!< SCU SFSPC_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPC_14  ------------------------------------------
+#define SCU_SFSPC_14_MODE_Pos                                 0                                                         /*!< SCU SFSPC_14: MODE Position         */
+#define SCU_SFSPC_14_MODE_Msk                                 (0x07UL << SCU_SFSPC_14_MODE_Pos)                         /*!< SCU SFSPC_14: MODE Mask             */
+#define SCU_SFSPC_14_EPD_Pos                                  3                                                         /*!< SCU SFSPC_14: EPD Position          */
+#define SCU_SFSPC_14_EPD_Msk                                  (0x01UL << SCU_SFSPC_14_EPD_Pos)                          /*!< SCU SFSPC_14: EPD Mask              */
+#define SCU_SFSPC_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_14: EPUN Position         */
+#define SCU_SFSPC_14_EPUN_Msk                                 (0x01UL << SCU_SFSPC_14_EPUN_Pos)                         /*!< SCU SFSPC_14: EPUN Mask             */
+#define SCU_SFSPC_14_EHS_Pos                                  5                                                         /*!< SCU SFSPC_14: EHS Position          */
+#define SCU_SFSPC_14_EHS_Msk                                  (0x01UL << SCU_SFSPC_14_EHS_Pos)                          /*!< SCU SFSPC_14: EHS Mask              */
+#define SCU_SFSPC_14_EZI_Pos                                  6                                                         /*!< SCU SFSPC_14: EZI Position          */
+#define SCU_SFSPC_14_EZI_Msk                                  (0x01UL << SCU_SFSPC_14_EZI_Pos)                          /*!< SCU SFSPC_14: EZI Mask              */
+#define SCU_SFSPC_14_EHD_Pos                                  8                                                         /*!< SCU SFSPC_14: EHD Position          */
+#define SCU_SFSPC_14_EHD_Msk                                  (0x03UL << SCU_SFSPC_14_EHD_Pos)                          /*!< SCU SFSPC_14: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSPD_0  ------------------------------------------
+#define SCU_SFSPD_0_MODE_Pos                                  0                                                         /*!< SCU SFSPD_0: MODE Position          */
+#define SCU_SFSPD_0_MODE_Msk                                  (0x07UL << SCU_SFSPD_0_MODE_Pos)                          /*!< SCU SFSPD_0: MODE Mask              */
+#define SCU_SFSPD_0_EPD_Pos                                   3                                                         /*!< SCU SFSPD_0: EPD Position           */
+#define SCU_SFSPD_0_EPD_Msk                                   (0x01UL << SCU_SFSPD_0_EPD_Pos)                           /*!< SCU SFSPD_0: EPD Mask               */
+#define SCU_SFSPD_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_0: EPUN Position          */
+#define SCU_SFSPD_0_EPUN_Msk                                  (0x01UL << SCU_SFSPD_0_EPUN_Pos)                          /*!< SCU SFSPD_0: EPUN Mask              */
+#define SCU_SFSPD_0_EHS_Pos                                   5                                                         /*!< SCU SFSPD_0: EHS Position           */
+#define SCU_SFSPD_0_EHS_Msk                                   (0x01UL << SCU_SFSPD_0_EHS_Pos)                           /*!< SCU SFSPD_0: EHS Mask               */
+#define SCU_SFSPD_0_EZI_Pos                                   6                                                         /*!< SCU SFSPD_0: EZI Position           */
+#define SCU_SFSPD_0_EZI_Msk                                   (0x01UL << SCU_SFSPD_0_EZI_Pos)                           /*!< SCU SFSPD_0: EZI Mask               */
+#define SCU_SFSPD_0_EHD_Pos                                   8                                                         /*!< SCU SFSPD_0: EHD Position           */
+#define SCU_SFSPD_0_EHD_Msk                                   (0x03UL << SCU_SFSPD_0_EHD_Pos)                           /*!< SCU SFSPD_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_1  ------------------------------------------
+#define SCU_SFSPD_1_MODE_Pos                                  0                                                         /*!< SCU SFSPD_1: MODE Position          */
+#define SCU_SFSPD_1_MODE_Msk                                  (0x07UL << SCU_SFSPD_1_MODE_Pos)                          /*!< SCU SFSPD_1: MODE Mask              */
+#define SCU_SFSPD_1_EPD_Pos                                   3                                                         /*!< SCU SFSPD_1: EPD Position           */
+#define SCU_SFSPD_1_EPD_Msk                                   (0x01UL << SCU_SFSPD_1_EPD_Pos)                           /*!< SCU SFSPD_1: EPD Mask               */
+#define SCU_SFSPD_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_1: EPUN Position          */
+#define SCU_SFSPD_1_EPUN_Msk                                  (0x01UL << SCU_SFSPD_1_EPUN_Pos)                          /*!< SCU SFSPD_1: EPUN Mask              */
+#define SCU_SFSPD_1_EHS_Pos                                   5                                                         /*!< SCU SFSPD_1: EHS Position           */
+#define SCU_SFSPD_1_EHS_Msk                                   (0x01UL << SCU_SFSPD_1_EHS_Pos)                           /*!< SCU SFSPD_1: EHS Mask               */
+#define SCU_SFSPD_1_EZI_Pos                                   6                                                         /*!< SCU SFSPD_1: EZI Position           */
+#define SCU_SFSPD_1_EZI_Msk                                   (0x01UL << SCU_SFSPD_1_EZI_Pos)                           /*!< SCU SFSPD_1: EZI Mask               */
+#define SCU_SFSPD_1_EHD_Pos                                   8                                                         /*!< SCU SFSPD_1: EHD Position           */
+#define SCU_SFSPD_1_EHD_Msk                                   (0x03UL << SCU_SFSPD_1_EHD_Pos)                           /*!< SCU SFSPD_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_2  ------------------------------------------
+#define SCU_SFSPD_2_MODE_Pos                                  0                                                         /*!< SCU SFSPD_2: MODE Position          */
+#define SCU_SFSPD_2_MODE_Msk                                  (0x07UL << SCU_SFSPD_2_MODE_Pos)                          /*!< SCU SFSPD_2: MODE Mask              */
+#define SCU_SFSPD_2_EPD_Pos                                   3                                                         /*!< SCU SFSPD_2: EPD Position           */
+#define SCU_SFSPD_2_EPD_Msk                                   (0x01UL << SCU_SFSPD_2_EPD_Pos)                           /*!< SCU SFSPD_2: EPD Mask               */
+#define SCU_SFSPD_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_2: EPUN Position          */
+#define SCU_SFSPD_2_EPUN_Msk                                  (0x01UL << SCU_SFSPD_2_EPUN_Pos)                          /*!< SCU SFSPD_2: EPUN Mask              */
+#define SCU_SFSPD_2_EHS_Pos                                   5                                                         /*!< SCU SFSPD_2: EHS Position           */
+#define SCU_SFSPD_2_EHS_Msk                                   (0x01UL << SCU_SFSPD_2_EHS_Pos)                           /*!< SCU SFSPD_2: EHS Mask               */
+#define SCU_SFSPD_2_EZI_Pos                                   6                                                         /*!< SCU SFSPD_2: EZI Position           */
+#define SCU_SFSPD_2_EZI_Msk                                   (0x01UL << SCU_SFSPD_2_EZI_Pos)                           /*!< SCU SFSPD_2: EZI Mask               */
+#define SCU_SFSPD_2_EHD_Pos                                   8                                                         /*!< SCU SFSPD_2: EHD Position           */
+#define SCU_SFSPD_2_EHD_Msk                                   (0x03UL << SCU_SFSPD_2_EHD_Pos)                           /*!< SCU SFSPD_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_3  ------------------------------------------
+#define SCU_SFSPD_3_MODE_Pos                                  0                                                         /*!< SCU SFSPD_3: MODE Position          */
+#define SCU_SFSPD_3_MODE_Msk                                  (0x07UL << SCU_SFSPD_3_MODE_Pos)                          /*!< SCU SFSPD_3: MODE Mask              */
+#define SCU_SFSPD_3_EPD_Pos                                   3                                                         /*!< SCU SFSPD_3: EPD Position           */
+#define SCU_SFSPD_3_EPD_Msk                                   (0x01UL << SCU_SFSPD_3_EPD_Pos)                           /*!< SCU SFSPD_3: EPD Mask               */
+#define SCU_SFSPD_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_3: EPUN Position          */
+#define SCU_SFSPD_3_EPUN_Msk                                  (0x01UL << SCU_SFSPD_3_EPUN_Pos)                          /*!< SCU SFSPD_3: EPUN Mask              */
+#define SCU_SFSPD_3_EHS_Pos                                   5                                                         /*!< SCU SFSPD_3: EHS Position           */
+#define SCU_SFSPD_3_EHS_Msk                                   (0x01UL << SCU_SFSPD_3_EHS_Pos)                           /*!< SCU SFSPD_3: EHS Mask               */
+#define SCU_SFSPD_3_EZI_Pos                                   6                                                         /*!< SCU SFSPD_3: EZI Position           */
+#define SCU_SFSPD_3_EZI_Msk                                   (0x01UL << SCU_SFSPD_3_EZI_Pos)                           /*!< SCU SFSPD_3: EZI Mask               */
+#define SCU_SFSPD_3_EHD_Pos                                   8                                                         /*!< SCU SFSPD_3: EHD Position           */
+#define SCU_SFSPD_3_EHD_Msk                                   (0x03UL << SCU_SFSPD_3_EHD_Pos)                           /*!< SCU SFSPD_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_4  ------------------------------------------
+#define SCU_SFSPD_4_MODE_Pos                                  0                                                         /*!< SCU SFSPD_4: MODE Position          */
+#define SCU_SFSPD_4_MODE_Msk                                  (0x07UL << SCU_SFSPD_4_MODE_Pos)                          /*!< SCU SFSPD_4: MODE Mask              */
+#define SCU_SFSPD_4_EPD_Pos                                   3                                                         /*!< SCU SFSPD_4: EPD Position           */
+#define SCU_SFSPD_4_EPD_Msk                                   (0x01UL << SCU_SFSPD_4_EPD_Pos)                           /*!< SCU SFSPD_4: EPD Mask               */
+#define SCU_SFSPD_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_4: EPUN Position          */
+#define SCU_SFSPD_4_EPUN_Msk                                  (0x01UL << SCU_SFSPD_4_EPUN_Pos)                          /*!< SCU SFSPD_4: EPUN Mask              */
+#define SCU_SFSPD_4_EHS_Pos                                   5                                                         /*!< SCU SFSPD_4: EHS Position           */
+#define SCU_SFSPD_4_EHS_Msk                                   (0x01UL << SCU_SFSPD_4_EHS_Pos)                           /*!< SCU SFSPD_4: EHS Mask               */
+#define SCU_SFSPD_4_EZI_Pos                                   6                                                         /*!< SCU SFSPD_4: EZI Position           */
+#define SCU_SFSPD_4_EZI_Msk                                   (0x01UL << SCU_SFSPD_4_EZI_Pos)                           /*!< SCU SFSPD_4: EZI Mask               */
+#define SCU_SFSPD_4_EHD_Pos                                   8                                                         /*!< SCU SFSPD_4: EHD Position           */
+#define SCU_SFSPD_4_EHD_Msk                                   (0x03UL << SCU_SFSPD_4_EHD_Pos)                           /*!< SCU SFSPD_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_5  ------------------------------------------
+#define SCU_SFSPD_5_MODE_Pos                                  0                                                         /*!< SCU SFSPD_5: MODE Position          */
+#define SCU_SFSPD_5_MODE_Msk                                  (0x07UL << SCU_SFSPD_5_MODE_Pos)                          /*!< SCU SFSPD_5: MODE Mask              */
+#define SCU_SFSPD_5_EPD_Pos                                   3                                                         /*!< SCU SFSPD_5: EPD Position           */
+#define SCU_SFSPD_5_EPD_Msk                                   (0x01UL << SCU_SFSPD_5_EPD_Pos)                           /*!< SCU SFSPD_5: EPD Mask               */
+#define SCU_SFSPD_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_5: EPUN Position          */
+#define SCU_SFSPD_5_EPUN_Msk                                  (0x01UL << SCU_SFSPD_5_EPUN_Pos)                          /*!< SCU SFSPD_5: EPUN Mask              */
+#define SCU_SFSPD_5_EHS_Pos                                   5                                                         /*!< SCU SFSPD_5: EHS Position           */
+#define SCU_SFSPD_5_EHS_Msk                                   (0x01UL << SCU_SFSPD_5_EHS_Pos)                           /*!< SCU SFSPD_5: EHS Mask               */
+#define SCU_SFSPD_5_EZI_Pos                                   6                                                         /*!< SCU SFSPD_5: EZI Position           */
+#define SCU_SFSPD_5_EZI_Msk                                   (0x01UL << SCU_SFSPD_5_EZI_Pos)                           /*!< SCU SFSPD_5: EZI Mask               */
+#define SCU_SFSPD_5_EHD_Pos                                   8                                                         /*!< SCU SFSPD_5: EHD Position           */
+#define SCU_SFSPD_5_EHD_Msk                                   (0x03UL << SCU_SFSPD_5_EHD_Pos)                           /*!< SCU SFSPD_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_6  ------------------------------------------
+#define SCU_SFSPD_6_MODE_Pos                                  0                                                         /*!< SCU SFSPD_6: MODE Position          */
+#define SCU_SFSPD_6_MODE_Msk                                  (0x07UL << SCU_SFSPD_6_MODE_Pos)                          /*!< SCU SFSPD_6: MODE Mask              */
+#define SCU_SFSPD_6_EPD_Pos                                   3                                                         /*!< SCU SFSPD_6: EPD Position           */
+#define SCU_SFSPD_6_EPD_Msk                                   (0x01UL << SCU_SFSPD_6_EPD_Pos)                           /*!< SCU SFSPD_6: EPD Mask               */
+#define SCU_SFSPD_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_6: EPUN Position          */
+#define SCU_SFSPD_6_EPUN_Msk                                  (0x01UL << SCU_SFSPD_6_EPUN_Pos)                          /*!< SCU SFSPD_6: EPUN Mask              */
+#define SCU_SFSPD_6_EHS_Pos                                   5                                                         /*!< SCU SFSPD_6: EHS Position           */
+#define SCU_SFSPD_6_EHS_Msk                                   (0x01UL << SCU_SFSPD_6_EHS_Pos)                           /*!< SCU SFSPD_6: EHS Mask               */
+#define SCU_SFSPD_6_EZI_Pos                                   6                                                         /*!< SCU SFSPD_6: EZI Position           */
+#define SCU_SFSPD_6_EZI_Msk                                   (0x01UL << SCU_SFSPD_6_EZI_Pos)                           /*!< SCU SFSPD_6: EZI Mask               */
+#define SCU_SFSPD_6_EHD_Pos                                   8                                                         /*!< SCU SFSPD_6: EHD Position           */
+#define SCU_SFSPD_6_EHD_Msk                                   (0x03UL << SCU_SFSPD_6_EHD_Pos)                           /*!< SCU SFSPD_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_7  ------------------------------------------
+#define SCU_SFSPD_7_MODE_Pos                                  0                                                         /*!< SCU SFSPD_7: MODE Position          */
+#define SCU_SFSPD_7_MODE_Msk                                  (0x07UL << SCU_SFSPD_7_MODE_Pos)                          /*!< SCU SFSPD_7: MODE Mask              */
+#define SCU_SFSPD_7_EPD_Pos                                   3                                                         /*!< SCU SFSPD_7: EPD Position           */
+#define SCU_SFSPD_7_EPD_Msk                                   (0x01UL << SCU_SFSPD_7_EPD_Pos)                           /*!< SCU SFSPD_7: EPD Mask               */
+#define SCU_SFSPD_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_7: EPUN Position          */
+#define SCU_SFSPD_7_EPUN_Msk                                  (0x01UL << SCU_SFSPD_7_EPUN_Pos)                          /*!< SCU SFSPD_7: EPUN Mask              */
+#define SCU_SFSPD_7_EHS_Pos                                   5                                                         /*!< SCU SFSPD_7: EHS Position           */
+#define SCU_SFSPD_7_EHS_Msk                                   (0x01UL << SCU_SFSPD_7_EHS_Pos)                           /*!< SCU SFSPD_7: EHS Mask               */
+#define SCU_SFSPD_7_EZI_Pos                                   6                                                         /*!< SCU SFSPD_7: EZI Position           */
+#define SCU_SFSPD_7_EZI_Msk                                   (0x01UL << SCU_SFSPD_7_EZI_Pos)                           /*!< SCU SFSPD_7: EZI Mask               */
+#define SCU_SFSPD_7_EHD_Pos                                   8                                                         /*!< SCU SFSPD_7: EHD Position           */
+#define SCU_SFSPD_7_EHD_Msk                                   (0x03UL << SCU_SFSPD_7_EHD_Pos)                           /*!< SCU SFSPD_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_8  ------------------------------------------
+#define SCU_SFSPD_8_MODE_Pos                                  0                                                         /*!< SCU SFSPD_8: MODE Position          */
+#define SCU_SFSPD_8_MODE_Msk                                  (0x07UL << SCU_SFSPD_8_MODE_Pos)                          /*!< SCU SFSPD_8: MODE Mask              */
+#define SCU_SFSPD_8_EPD_Pos                                   3                                                         /*!< SCU SFSPD_8: EPD Position           */
+#define SCU_SFSPD_8_EPD_Msk                                   (0x01UL << SCU_SFSPD_8_EPD_Pos)                           /*!< SCU SFSPD_8: EPD Mask               */
+#define SCU_SFSPD_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_8: EPUN Position          */
+#define SCU_SFSPD_8_EPUN_Msk                                  (0x01UL << SCU_SFSPD_8_EPUN_Pos)                          /*!< SCU SFSPD_8: EPUN Mask              */
+#define SCU_SFSPD_8_EHS_Pos                                   5                                                         /*!< SCU SFSPD_8: EHS Position           */
+#define SCU_SFSPD_8_EHS_Msk                                   (0x01UL << SCU_SFSPD_8_EHS_Pos)                           /*!< SCU SFSPD_8: EHS Mask               */
+#define SCU_SFSPD_8_EZI_Pos                                   6                                                         /*!< SCU SFSPD_8: EZI Position           */
+#define SCU_SFSPD_8_EZI_Msk                                   (0x01UL << SCU_SFSPD_8_EZI_Pos)                           /*!< SCU SFSPD_8: EZI Mask               */
+#define SCU_SFSPD_8_EHD_Pos                                   8                                                         /*!< SCU SFSPD_8: EHD Position           */
+#define SCU_SFSPD_8_EHD_Msk                                   (0x03UL << SCU_SFSPD_8_EHD_Pos)                           /*!< SCU SFSPD_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPD_9  ------------------------------------------
+#define SCU_SFSPD_9_MODE_Pos                                  0                                                         /*!< SCU SFSPD_9: MODE Position          */
+#define SCU_SFSPD_9_MODE_Msk                                  (0x07UL << SCU_SFSPD_9_MODE_Pos)                          /*!< SCU SFSPD_9: MODE Mask              */
+#define SCU_SFSPD_9_EPD_Pos                                   3                                                         /*!< SCU SFSPD_9: EPD Position           */
+#define SCU_SFSPD_9_EPD_Msk                                   (0x01UL << SCU_SFSPD_9_EPD_Pos)                           /*!< SCU SFSPD_9: EPD Mask               */
+#define SCU_SFSPD_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_9: EPUN Position          */
+#define SCU_SFSPD_9_EPUN_Msk                                  (0x01UL << SCU_SFSPD_9_EPUN_Pos)                          /*!< SCU SFSPD_9: EPUN Mask              */
+#define SCU_SFSPD_9_EHS_Pos                                   5                                                         /*!< SCU SFSPD_9: EHS Position           */
+#define SCU_SFSPD_9_EHS_Msk                                   (0x01UL << SCU_SFSPD_9_EHS_Pos)                           /*!< SCU SFSPD_9: EHS Mask               */
+#define SCU_SFSPD_9_EZI_Pos                                   6                                                         /*!< SCU SFSPD_9: EZI Position           */
+#define SCU_SFSPD_9_EZI_Msk                                   (0x01UL << SCU_SFSPD_9_EZI_Pos)                           /*!< SCU SFSPD_9: EZI Mask               */
+#define SCU_SFSPD_9_EHD_Pos                                   8                                                         /*!< SCU SFSPD_9: EHD Position           */
+#define SCU_SFSPD_9_EHD_Msk                                   (0x03UL << SCU_SFSPD_9_EHD_Pos)                           /*!< SCU SFSPD_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPD_10  ------------------------------------------
+#define SCU_SFSPD_10_MODE_Pos                                 0                                                         /*!< SCU SFSPD_10: MODE Position         */
+#define SCU_SFSPD_10_MODE_Msk                                 (0x07UL << SCU_SFSPD_10_MODE_Pos)                         /*!< SCU SFSPD_10: MODE Mask             */
+#define SCU_SFSPD_10_EPD_Pos                                  3                                                         /*!< SCU SFSPD_10: EPD Position          */
+#define SCU_SFSPD_10_EPD_Msk                                  (0x01UL << SCU_SFSPD_10_EPD_Pos)                          /*!< SCU SFSPD_10: EPD Mask              */
+#define SCU_SFSPD_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_10: EPUN Position         */
+#define SCU_SFSPD_10_EPUN_Msk                                 (0x01UL << SCU_SFSPD_10_EPUN_Pos)                         /*!< SCU SFSPD_10: EPUN Mask             */
+#define SCU_SFSPD_10_EHS_Pos                                  5                                                         /*!< SCU SFSPD_10: EHS Position          */
+#define SCU_SFSPD_10_EHS_Msk                                  (0x01UL << SCU_SFSPD_10_EHS_Pos)                          /*!< SCU SFSPD_10: EHS Mask              */
+#define SCU_SFSPD_10_EZI_Pos                                  6                                                         /*!< SCU SFSPD_10: EZI Position          */
+#define SCU_SFSPD_10_EZI_Msk                                  (0x01UL << SCU_SFSPD_10_EZI_Pos)                          /*!< SCU SFSPD_10: EZI Mask              */
+#define SCU_SFSPD_10_EHD_Pos                                  8                                                         /*!< SCU SFSPD_10: EHD Position          */
+#define SCU_SFSPD_10_EHD_Msk                                  (0x03UL << SCU_SFSPD_10_EHD_Pos)                          /*!< SCU SFSPD_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_11  ------------------------------------------
+#define SCU_SFSPD_11_MODE_Pos                                 0                                                         /*!< SCU SFSPD_11: MODE Position         */
+#define SCU_SFSPD_11_MODE_Msk                                 (0x07UL << SCU_SFSPD_11_MODE_Pos)                         /*!< SCU SFSPD_11: MODE Mask             */
+#define SCU_SFSPD_11_EPD_Pos                                  3                                                         /*!< SCU SFSPD_11: EPD Position          */
+#define SCU_SFSPD_11_EPD_Msk                                  (0x01UL << SCU_SFSPD_11_EPD_Pos)                          /*!< SCU SFSPD_11: EPD Mask              */
+#define SCU_SFSPD_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_11: EPUN Position         */
+#define SCU_SFSPD_11_EPUN_Msk                                 (0x01UL << SCU_SFSPD_11_EPUN_Pos)                         /*!< SCU SFSPD_11: EPUN Mask             */
+#define SCU_SFSPD_11_EHS_Pos                                  5                                                         /*!< SCU SFSPD_11: EHS Position          */
+#define SCU_SFSPD_11_EHS_Msk                                  (0x01UL << SCU_SFSPD_11_EHS_Pos)                          /*!< SCU SFSPD_11: EHS Mask              */
+#define SCU_SFSPD_11_EZI_Pos                                  6                                                         /*!< SCU SFSPD_11: EZI Position          */
+#define SCU_SFSPD_11_EZI_Msk                                  (0x01UL << SCU_SFSPD_11_EZI_Pos)                          /*!< SCU SFSPD_11: EZI Mask              */
+#define SCU_SFSPD_11_EHD_Pos                                  8                                                         /*!< SCU SFSPD_11: EHD Position          */
+#define SCU_SFSPD_11_EHD_Msk                                  (0x03UL << SCU_SFSPD_11_EHD_Pos)                          /*!< SCU SFSPD_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_12  ------------------------------------------
+#define SCU_SFSPD_12_MODE_Pos                                 0                                                         /*!< SCU SFSPD_12: MODE Position         */
+#define SCU_SFSPD_12_MODE_Msk                                 (0x07UL << SCU_SFSPD_12_MODE_Pos)                         /*!< SCU SFSPD_12: MODE Mask             */
+#define SCU_SFSPD_12_EPD_Pos                                  3                                                         /*!< SCU SFSPD_12: EPD Position          */
+#define SCU_SFSPD_12_EPD_Msk                                  (0x01UL << SCU_SFSPD_12_EPD_Pos)                          /*!< SCU SFSPD_12: EPD Mask              */
+#define SCU_SFSPD_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_12: EPUN Position         */
+#define SCU_SFSPD_12_EPUN_Msk                                 (0x01UL << SCU_SFSPD_12_EPUN_Pos)                         /*!< SCU SFSPD_12: EPUN Mask             */
+#define SCU_SFSPD_12_EHS_Pos                                  5                                                         /*!< SCU SFSPD_12: EHS Position          */
+#define SCU_SFSPD_12_EHS_Msk                                  (0x01UL << SCU_SFSPD_12_EHS_Pos)                          /*!< SCU SFSPD_12: EHS Mask              */
+#define SCU_SFSPD_12_EZI_Pos                                  6                                                         /*!< SCU SFSPD_12: EZI Position          */
+#define SCU_SFSPD_12_EZI_Msk                                  (0x01UL << SCU_SFSPD_12_EZI_Pos)                          /*!< SCU SFSPD_12: EZI Mask              */
+#define SCU_SFSPD_12_EHD_Pos                                  8                                                         /*!< SCU SFSPD_12: EHD Position          */
+#define SCU_SFSPD_12_EHD_Msk                                  (0x03UL << SCU_SFSPD_12_EHD_Pos)                          /*!< SCU SFSPD_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_13  ------------------------------------------
+#define SCU_SFSPD_13_MODE_Pos                                 0                                                         /*!< SCU SFSPD_13: MODE Position         */
+#define SCU_SFSPD_13_MODE_Msk                                 (0x07UL << SCU_SFSPD_13_MODE_Pos)                         /*!< SCU SFSPD_13: MODE Mask             */
+#define SCU_SFSPD_13_EPD_Pos                                  3                                                         /*!< SCU SFSPD_13: EPD Position          */
+#define SCU_SFSPD_13_EPD_Msk                                  (0x01UL << SCU_SFSPD_13_EPD_Pos)                          /*!< SCU SFSPD_13: EPD Mask              */
+#define SCU_SFSPD_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_13: EPUN Position         */
+#define SCU_SFSPD_13_EPUN_Msk                                 (0x01UL << SCU_SFSPD_13_EPUN_Pos)                         /*!< SCU SFSPD_13: EPUN Mask             */
+#define SCU_SFSPD_13_EHS_Pos                                  5                                                         /*!< SCU SFSPD_13: EHS Position          */
+#define SCU_SFSPD_13_EHS_Msk                                  (0x01UL << SCU_SFSPD_13_EHS_Pos)                          /*!< SCU SFSPD_13: EHS Mask              */
+#define SCU_SFSPD_13_EZI_Pos                                  6                                                         /*!< SCU SFSPD_13: EZI Position          */
+#define SCU_SFSPD_13_EZI_Msk                                  (0x01UL << SCU_SFSPD_13_EZI_Pos)                          /*!< SCU SFSPD_13: EZI Mask              */
+#define SCU_SFSPD_13_EHD_Pos                                  8                                                         /*!< SCU SFSPD_13: EHD Position          */
+#define SCU_SFSPD_13_EHD_Msk                                  (0x03UL << SCU_SFSPD_13_EHD_Pos)                          /*!< SCU SFSPD_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_14  ------------------------------------------
+#define SCU_SFSPD_14_MODE_Pos                                 0                                                         /*!< SCU SFSPD_14: MODE Position         */
+#define SCU_SFSPD_14_MODE_Msk                                 (0x07UL << SCU_SFSPD_14_MODE_Pos)                         /*!< SCU SFSPD_14: MODE Mask             */
+#define SCU_SFSPD_14_EPD_Pos                                  3                                                         /*!< SCU SFSPD_14: EPD Position          */
+#define SCU_SFSPD_14_EPD_Msk                                  (0x01UL << SCU_SFSPD_14_EPD_Pos)                          /*!< SCU SFSPD_14: EPD Mask              */
+#define SCU_SFSPD_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_14: EPUN Position         */
+#define SCU_SFSPD_14_EPUN_Msk                                 (0x01UL << SCU_SFSPD_14_EPUN_Pos)                         /*!< SCU SFSPD_14: EPUN Mask             */
+#define SCU_SFSPD_14_EHS_Pos                                  5                                                         /*!< SCU SFSPD_14: EHS Position          */
+#define SCU_SFSPD_14_EHS_Msk                                  (0x01UL << SCU_SFSPD_14_EHS_Pos)                          /*!< SCU SFSPD_14: EHS Mask              */
+#define SCU_SFSPD_14_EZI_Pos                                  6                                                         /*!< SCU SFSPD_14: EZI Position          */
+#define SCU_SFSPD_14_EZI_Msk                                  (0x01UL << SCU_SFSPD_14_EZI_Pos)                          /*!< SCU SFSPD_14: EZI Mask              */
+#define SCU_SFSPD_14_EHD_Pos                                  8                                                         /*!< SCU SFSPD_14: EHD Position          */
+#define SCU_SFSPD_14_EHD_Msk                                  (0x03UL << SCU_SFSPD_14_EHD_Pos)                          /*!< SCU SFSPD_14: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_15  ------------------------------------------
+#define SCU_SFSPD_15_MODE_Pos                                 0                                                         /*!< SCU SFSPD_15: MODE Position         */
+#define SCU_SFSPD_15_MODE_Msk                                 (0x07UL << SCU_SFSPD_15_MODE_Pos)                         /*!< SCU SFSPD_15: MODE Mask             */
+#define SCU_SFSPD_15_EPD_Pos                                  3                                                         /*!< SCU SFSPD_15: EPD Position          */
+#define SCU_SFSPD_15_EPD_Msk                                  (0x01UL << SCU_SFSPD_15_EPD_Pos)                          /*!< SCU SFSPD_15: EPD Mask              */
+#define SCU_SFSPD_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_15: EPUN Position         */
+#define SCU_SFSPD_15_EPUN_Msk                                 (0x01UL << SCU_SFSPD_15_EPUN_Pos)                         /*!< SCU SFSPD_15: EPUN Mask             */
+#define SCU_SFSPD_15_EHS_Pos                                  5                                                         /*!< SCU SFSPD_15: EHS Position          */
+#define SCU_SFSPD_15_EHS_Msk                                  (0x01UL << SCU_SFSPD_15_EHS_Pos)                          /*!< SCU SFSPD_15: EHS Mask              */
+#define SCU_SFSPD_15_EZI_Pos                                  6                                                         /*!< SCU SFSPD_15: EZI Position          */
+#define SCU_SFSPD_15_EZI_Msk                                  (0x01UL << SCU_SFSPD_15_EZI_Pos)                          /*!< SCU SFSPD_15: EZI Mask              */
+#define SCU_SFSPD_15_EHD_Pos                                  8                                                         /*!< SCU SFSPD_15: EHD Position          */
+#define SCU_SFSPD_15_EHD_Msk                                  (0x03UL << SCU_SFSPD_15_EHD_Pos)                          /*!< SCU SFSPD_15: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPD_16  ------------------------------------------
+#define SCU_SFSPD_16_MODE_Pos                                 0                                                         /*!< SCU SFSPD_16: MODE Position         */
+#define SCU_SFSPD_16_MODE_Msk                                 (0x07UL << SCU_SFSPD_16_MODE_Pos)                         /*!< SCU SFSPD_16: MODE Mask             */
+#define SCU_SFSPD_16_EPD_Pos                                  3                                                         /*!< SCU SFSPD_16: EPD Position          */
+#define SCU_SFSPD_16_EPD_Msk                                  (0x01UL << SCU_SFSPD_16_EPD_Pos)                          /*!< SCU SFSPD_16: EPD Mask              */
+#define SCU_SFSPD_16_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_16: EPUN Position         */
+#define SCU_SFSPD_16_EPUN_Msk                                 (0x01UL << SCU_SFSPD_16_EPUN_Pos)                         /*!< SCU SFSPD_16: EPUN Mask             */
+#define SCU_SFSPD_16_EHS_Pos                                  5                                                         /*!< SCU SFSPD_16: EHS Position          */
+#define SCU_SFSPD_16_EHS_Msk                                  (0x01UL << SCU_SFSPD_16_EHS_Pos)                          /*!< SCU SFSPD_16: EHS Mask              */
+#define SCU_SFSPD_16_EZI_Pos                                  6                                                         /*!< SCU SFSPD_16: EZI Position          */
+#define SCU_SFSPD_16_EZI_Msk                                  (0x01UL << SCU_SFSPD_16_EZI_Pos)                          /*!< SCU SFSPD_16: EZI Mask              */
+#define SCU_SFSPD_16_EHD_Pos                                  8                                                         /*!< SCU SFSPD_16: EHD Position          */
+#define SCU_SFSPD_16_EHD_Msk                                  (0x03UL << SCU_SFSPD_16_EHD_Pos)                          /*!< SCU SFSPD_16: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSPE_0  ------------------------------------------
+#define SCU_SFSPE_0_MODE_Pos                                  0                                                         /*!< SCU SFSPE_0: MODE Position          */
+#define SCU_SFSPE_0_MODE_Msk                                  (0x07UL << SCU_SFSPE_0_MODE_Pos)                          /*!< SCU SFSPE_0: MODE Mask              */
+#define SCU_SFSPE_0_EPD_Pos                                   3                                                         /*!< SCU SFSPE_0: EPD Position           */
+#define SCU_SFSPE_0_EPD_Msk                                   (0x01UL << SCU_SFSPE_0_EPD_Pos)                           /*!< SCU SFSPE_0: EPD Mask               */
+#define SCU_SFSPE_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_0: EPUN Position          */
+#define SCU_SFSPE_0_EPUN_Msk                                  (0x01UL << SCU_SFSPE_0_EPUN_Pos)                          /*!< SCU SFSPE_0: EPUN Mask              */
+#define SCU_SFSPE_0_EHS_Pos                                   5                                                         /*!< SCU SFSPE_0: EHS Position           */
+#define SCU_SFSPE_0_EHS_Msk                                   (0x01UL << SCU_SFSPE_0_EHS_Pos)                           /*!< SCU SFSPE_0: EHS Mask               */
+#define SCU_SFSPE_0_EZI_Pos                                   6                                                         /*!< SCU SFSPE_0: EZI Position           */
+#define SCU_SFSPE_0_EZI_Msk                                   (0x01UL << SCU_SFSPE_0_EZI_Pos)                           /*!< SCU SFSPE_0: EZI Mask               */
+#define SCU_SFSPE_0_EHD_Pos                                   8                                                         /*!< SCU SFSPE_0: EHD Position           */
+#define SCU_SFSPE_0_EHD_Msk                                   (0x03UL << SCU_SFSPE_0_EHD_Pos)                           /*!< SCU SFSPE_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_1  ------------------------------------------
+#define SCU_SFSPE_1_MODE_Pos                                  0                                                         /*!< SCU SFSPE_1: MODE Position          */
+#define SCU_SFSPE_1_MODE_Msk                                  (0x07UL << SCU_SFSPE_1_MODE_Pos)                          /*!< SCU SFSPE_1: MODE Mask              */
+#define SCU_SFSPE_1_EPD_Pos                                   3                                                         /*!< SCU SFSPE_1: EPD Position           */
+#define SCU_SFSPE_1_EPD_Msk                                   (0x01UL << SCU_SFSPE_1_EPD_Pos)                           /*!< SCU SFSPE_1: EPD Mask               */
+#define SCU_SFSPE_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_1: EPUN Position          */
+#define SCU_SFSPE_1_EPUN_Msk                                  (0x01UL << SCU_SFSPE_1_EPUN_Pos)                          /*!< SCU SFSPE_1: EPUN Mask              */
+#define SCU_SFSPE_1_EHS_Pos                                   5                                                         /*!< SCU SFSPE_1: EHS Position           */
+#define SCU_SFSPE_1_EHS_Msk                                   (0x01UL << SCU_SFSPE_1_EHS_Pos)                           /*!< SCU SFSPE_1: EHS Mask               */
+#define SCU_SFSPE_1_EZI_Pos                                   6                                                         /*!< SCU SFSPE_1: EZI Position           */
+#define SCU_SFSPE_1_EZI_Msk                                   (0x01UL << SCU_SFSPE_1_EZI_Pos)                           /*!< SCU SFSPE_1: EZI Mask               */
+#define SCU_SFSPE_1_EHD_Pos                                   8                                                         /*!< SCU SFSPE_1: EHD Position           */
+#define SCU_SFSPE_1_EHD_Msk                                   (0x03UL << SCU_SFSPE_1_EHD_Pos)                           /*!< SCU SFSPE_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_2  ------------------------------------------
+#define SCU_SFSPE_2_MODE_Pos                                  0                                                         /*!< SCU SFSPE_2: MODE Position          */
+#define SCU_SFSPE_2_MODE_Msk                                  (0x07UL << SCU_SFSPE_2_MODE_Pos)                          /*!< SCU SFSPE_2: MODE Mask              */
+#define SCU_SFSPE_2_EPD_Pos                                   3                                                         /*!< SCU SFSPE_2: EPD Position           */
+#define SCU_SFSPE_2_EPD_Msk                                   (0x01UL << SCU_SFSPE_2_EPD_Pos)                           /*!< SCU SFSPE_2: EPD Mask               */
+#define SCU_SFSPE_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_2: EPUN Position          */
+#define SCU_SFSPE_2_EPUN_Msk                                  (0x01UL << SCU_SFSPE_2_EPUN_Pos)                          /*!< SCU SFSPE_2: EPUN Mask              */
+#define SCU_SFSPE_2_EHS_Pos                                   5                                                         /*!< SCU SFSPE_2: EHS Position           */
+#define SCU_SFSPE_2_EHS_Msk                                   (0x01UL << SCU_SFSPE_2_EHS_Pos)                           /*!< SCU SFSPE_2: EHS Mask               */
+#define SCU_SFSPE_2_EZI_Pos                                   6                                                         /*!< SCU SFSPE_2: EZI Position           */
+#define SCU_SFSPE_2_EZI_Msk                                   (0x01UL << SCU_SFSPE_2_EZI_Pos)                           /*!< SCU SFSPE_2: EZI Mask               */
+#define SCU_SFSPE_2_EHD_Pos                                   8                                                         /*!< SCU SFSPE_2: EHD Position           */
+#define SCU_SFSPE_2_EHD_Msk                                   (0x03UL << SCU_SFSPE_2_EHD_Pos)                           /*!< SCU SFSPE_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_3  ------------------------------------------
+#define SCU_SFSPE_3_MODE_Pos                                  0                                                         /*!< SCU SFSPE_3: MODE Position          */
+#define SCU_SFSPE_3_MODE_Msk                                  (0x07UL << SCU_SFSPE_3_MODE_Pos)                          /*!< SCU SFSPE_3: MODE Mask              */
+#define SCU_SFSPE_3_EPD_Pos                                   3                                                         /*!< SCU SFSPE_3: EPD Position           */
+#define SCU_SFSPE_3_EPD_Msk                                   (0x01UL << SCU_SFSPE_3_EPD_Pos)                           /*!< SCU SFSPE_3: EPD Mask               */
+#define SCU_SFSPE_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_3: EPUN Position          */
+#define SCU_SFSPE_3_EPUN_Msk                                  (0x01UL << SCU_SFSPE_3_EPUN_Pos)                          /*!< SCU SFSPE_3: EPUN Mask              */
+#define SCU_SFSPE_3_EHS_Pos                                   5                                                         /*!< SCU SFSPE_3: EHS Position           */
+#define SCU_SFSPE_3_EHS_Msk                                   (0x01UL << SCU_SFSPE_3_EHS_Pos)                           /*!< SCU SFSPE_3: EHS Mask               */
+#define SCU_SFSPE_3_EZI_Pos                                   6                                                         /*!< SCU SFSPE_3: EZI Position           */
+#define SCU_SFSPE_3_EZI_Msk                                   (0x01UL << SCU_SFSPE_3_EZI_Pos)                           /*!< SCU SFSPE_3: EZI Mask               */
+#define SCU_SFSPE_3_EHD_Pos                                   8                                                         /*!< SCU SFSPE_3: EHD Position           */
+#define SCU_SFSPE_3_EHD_Msk                                   (0x03UL << SCU_SFSPE_3_EHD_Pos)                           /*!< SCU SFSPE_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_4  ------------------------------------------
+#define SCU_SFSPE_4_MODE_Pos                                  0                                                         /*!< SCU SFSPE_4: MODE Position          */
+#define SCU_SFSPE_4_MODE_Msk                                  (0x07UL << SCU_SFSPE_4_MODE_Pos)                          /*!< SCU SFSPE_4: MODE Mask              */
+#define SCU_SFSPE_4_EPD_Pos                                   3                                                         /*!< SCU SFSPE_4: EPD Position           */
+#define SCU_SFSPE_4_EPD_Msk                                   (0x01UL << SCU_SFSPE_4_EPD_Pos)                           /*!< SCU SFSPE_4: EPD Mask               */
+#define SCU_SFSPE_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_4: EPUN Position          */
+#define SCU_SFSPE_4_EPUN_Msk                                  (0x01UL << SCU_SFSPE_4_EPUN_Pos)                          /*!< SCU SFSPE_4: EPUN Mask              */
+#define SCU_SFSPE_4_EHS_Pos                                   5                                                         /*!< SCU SFSPE_4: EHS Position           */
+#define SCU_SFSPE_4_EHS_Msk                                   (0x01UL << SCU_SFSPE_4_EHS_Pos)                           /*!< SCU SFSPE_4: EHS Mask               */
+#define SCU_SFSPE_4_EZI_Pos                                   6                                                         /*!< SCU SFSPE_4: EZI Position           */
+#define SCU_SFSPE_4_EZI_Msk                                   (0x01UL << SCU_SFSPE_4_EZI_Pos)                           /*!< SCU SFSPE_4: EZI Mask               */
+#define SCU_SFSPE_4_EHD_Pos                                   8                                                         /*!< SCU SFSPE_4: EHD Position           */
+#define SCU_SFSPE_4_EHD_Msk                                   (0x03UL << SCU_SFSPE_4_EHD_Pos)                           /*!< SCU SFSPE_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_5  ------------------------------------------
+#define SCU_SFSPE_5_MODE_Pos                                  0                                                         /*!< SCU SFSPE_5: MODE Position          */
+#define SCU_SFSPE_5_MODE_Msk                                  (0x07UL << SCU_SFSPE_5_MODE_Pos)                          /*!< SCU SFSPE_5: MODE Mask              */
+#define SCU_SFSPE_5_EPD_Pos                                   3                                                         /*!< SCU SFSPE_5: EPD Position           */
+#define SCU_SFSPE_5_EPD_Msk                                   (0x01UL << SCU_SFSPE_5_EPD_Pos)                           /*!< SCU SFSPE_5: EPD Mask               */
+#define SCU_SFSPE_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_5: EPUN Position          */
+#define SCU_SFSPE_5_EPUN_Msk                                  (0x01UL << SCU_SFSPE_5_EPUN_Pos)                          /*!< SCU SFSPE_5: EPUN Mask              */
+#define SCU_SFSPE_5_EHS_Pos                                   5                                                         /*!< SCU SFSPE_5: EHS Position           */
+#define SCU_SFSPE_5_EHS_Msk                                   (0x01UL << SCU_SFSPE_5_EHS_Pos)                           /*!< SCU SFSPE_5: EHS Mask               */
+#define SCU_SFSPE_5_EZI_Pos                                   6                                                         /*!< SCU SFSPE_5: EZI Position           */
+#define SCU_SFSPE_5_EZI_Msk                                   (0x01UL << SCU_SFSPE_5_EZI_Pos)                           /*!< SCU SFSPE_5: EZI Mask               */
+#define SCU_SFSPE_5_EHD_Pos                                   8                                                         /*!< SCU SFSPE_5: EHD Position           */
+#define SCU_SFSPE_5_EHD_Msk                                   (0x03UL << SCU_SFSPE_5_EHD_Pos)                           /*!< SCU SFSPE_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_6  ------------------------------------------
+#define SCU_SFSPE_6_MODE_Pos                                  0                                                         /*!< SCU SFSPE_6: MODE Position          */
+#define SCU_SFSPE_6_MODE_Msk                                  (0x07UL << SCU_SFSPE_6_MODE_Pos)                          /*!< SCU SFSPE_6: MODE Mask              */
+#define SCU_SFSPE_6_EPD_Pos                                   3                                                         /*!< SCU SFSPE_6: EPD Position           */
+#define SCU_SFSPE_6_EPD_Msk                                   (0x01UL << SCU_SFSPE_6_EPD_Pos)                           /*!< SCU SFSPE_6: EPD Mask               */
+#define SCU_SFSPE_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_6: EPUN Position          */
+#define SCU_SFSPE_6_EPUN_Msk                                  (0x01UL << SCU_SFSPE_6_EPUN_Pos)                          /*!< SCU SFSPE_6: EPUN Mask              */
+#define SCU_SFSPE_6_EHS_Pos                                   5                                                         /*!< SCU SFSPE_6: EHS Position           */
+#define SCU_SFSPE_6_EHS_Msk                                   (0x01UL << SCU_SFSPE_6_EHS_Pos)                           /*!< SCU SFSPE_6: EHS Mask               */
+#define SCU_SFSPE_6_EZI_Pos                                   6                                                         /*!< SCU SFSPE_6: EZI Position           */
+#define SCU_SFSPE_6_EZI_Msk                                   (0x01UL << SCU_SFSPE_6_EZI_Pos)                           /*!< SCU SFSPE_6: EZI Mask               */
+#define SCU_SFSPE_6_EHD_Pos                                   8                                                         /*!< SCU SFSPE_6: EHD Position           */
+#define SCU_SFSPE_6_EHD_Msk                                   (0x03UL << SCU_SFSPE_6_EHD_Pos)                           /*!< SCU SFSPE_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_7  ------------------------------------------
+#define SCU_SFSPE_7_MODE_Pos                                  0                                                         /*!< SCU SFSPE_7: MODE Position          */
+#define SCU_SFSPE_7_MODE_Msk                                  (0x07UL << SCU_SFSPE_7_MODE_Pos)                          /*!< SCU SFSPE_7: MODE Mask              */
+#define SCU_SFSPE_7_EPD_Pos                                   3                                                         /*!< SCU SFSPE_7: EPD Position           */
+#define SCU_SFSPE_7_EPD_Msk                                   (0x01UL << SCU_SFSPE_7_EPD_Pos)                           /*!< SCU SFSPE_7: EPD Mask               */
+#define SCU_SFSPE_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_7: EPUN Position          */
+#define SCU_SFSPE_7_EPUN_Msk                                  (0x01UL << SCU_SFSPE_7_EPUN_Pos)                          /*!< SCU SFSPE_7: EPUN Mask              */
+#define SCU_SFSPE_7_EHS_Pos                                   5                                                         /*!< SCU SFSPE_7: EHS Position           */
+#define SCU_SFSPE_7_EHS_Msk                                   (0x01UL << SCU_SFSPE_7_EHS_Pos)                           /*!< SCU SFSPE_7: EHS Mask               */
+#define SCU_SFSPE_7_EZI_Pos                                   6                                                         /*!< SCU SFSPE_7: EZI Position           */
+#define SCU_SFSPE_7_EZI_Msk                                   (0x01UL << SCU_SFSPE_7_EZI_Pos)                           /*!< SCU SFSPE_7: EZI Mask               */
+#define SCU_SFSPE_7_EHD_Pos                                   8                                                         /*!< SCU SFSPE_7: EHD Position           */
+#define SCU_SFSPE_7_EHD_Msk                                   (0x03UL << SCU_SFSPE_7_EHD_Pos)                           /*!< SCU SFSPE_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_8  ------------------------------------------
+#define SCU_SFSPE_8_MODE_Pos                                  0                                                         /*!< SCU SFSPE_8: MODE Position          */
+#define SCU_SFSPE_8_MODE_Msk                                  (0x07UL << SCU_SFSPE_8_MODE_Pos)                          /*!< SCU SFSPE_8: MODE Mask              */
+#define SCU_SFSPE_8_EPD_Pos                                   3                                                         /*!< SCU SFSPE_8: EPD Position           */
+#define SCU_SFSPE_8_EPD_Msk                                   (0x01UL << SCU_SFSPE_8_EPD_Pos)                           /*!< SCU SFSPE_8: EPD Mask               */
+#define SCU_SFSPE_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_8: EPUN Position          */
+#define SCU_SFSPE_8_EPUN_Msk                                  (0x01UL << SCU_SFSPE_8_EPUN_Pos)                          /*!< SCU SFSPE_8: EPUN Mask              */
+#define SCU_SFSPE_8_EHS_Pos                                   5                                                         /*!< SCU SFSPE_8: EHS Position           */
+#define SCU_SFSPE_8_EHS_Msk                                   (0x01UL << SCU_SFSPE_8_EHS_Pos)                           /*!< SCU SFSPE_8: EHS Mask               */
+#define SCU_SFSPE_8_EZI_Pos                                   6                                                         /*!< SCU SFSPE_8: EZI Position           */
+#define SCU_SFSPE_8_EZI_Msk                                   (0x01UL << SCU_SFSPE_8_EZI_Pos)                           /*!< SCU SFSPE_8: EZI Mask               */
+#define SCU_SFSPE_8_EHD_Pos                                   8                                                         /*!< SCU SFSPE_8: EHD Position           */
+#define SCU_SFSPE_8_EHD_Msk                                   (0x03UL << SCU_SFSPE_8_EHD_Pos)                           /*!< SCU SFSPE_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPE_9  ------------------------------------------
+#define SCU_SFSPE_9_MODE_Pos                                  0                                                         /*!< SCU SFSPE_9: MODE Position          */
+#define SCU_SFSPE_9_MODE_Msk                                  (0x07UL << SCU_SFSPE_9_MODE_Pos)                          /*!< SCU SFSPE_9: MODE Mask              */
+#define SCU_SFSPE_9_EPD_Pos                                   3                                                         /*!< SCU SFSPE_9: EPD Position           */
+#define SCU_SFSPE_9_EPD_Msk                                   (0x01UL << SCU_SFSPE_9_EPD_Pos)                           /*!< SCU SFSPE_9: EPD Mask               */
+#define SCU_SFSPE_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_9: EPUN Position          */
+#define SCU_SFSPE_9_EPUN_Msk                                  (0x01UL << SCU_SFSPE_9_EPUN_Pos)                          /*!< SCU SFSPE_9: EPUN Mask              */
+#define SCU_SFSPE_9_EHS_Pos                                   5                                                         /*!< SCU SFSPE_9: EHS Position           */
+#define SCU_SFSPE_9_EHS_Msk                                   (0x01UL << SCU_SFSPE_9_EHS_Pos)                           /*!< SCU SFSPE_9: EHS Mask               */
+#define SCU_SFSPE_9_EZI_Pos                                   6                                                         /*!< SCU SFSPE_9: EZI Position           */
+#define SCU_SFSPE_9_EZI_Msk                                   (0x01UL << SCU_SFSPE_9_EZI_Pos)                           /*!< SCU SFSPE_9: EZI Mask               */
+#define SCU_SFSPE_9_EHD_Pos                                   8                                                         /*!< SCU SFSPE_9: EHD Position           */
+#define SCU_SFSPE_9_EHD_Msk                                   (0x03UL << SCU_SFSPE_9_EHD_Pos)                           /*!< SCU SFSPE_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPE_10  ------------------------------------------
+#define SCU_SFSPE_10_MODE_Pos                                 0                                                         /*!< SCU SFSPE_10: MODE Position         */
+#define SCU_SFSPE_10_MODE_Msk                                 (0x07UL << SCU_SFSPE_10_MODE_Pos)                         /*!< SCU SFSPE_10: MODE Mask             */
+#define SCU_SFSPE_10_EPD_Pos                                  3                                                         /*!< SCU SFSPE_10: EPD Position          */
+#define SCU_SFSPE_10_EPD_Msk                                  (0x01UL << SCU_SFSPE_10_EPD_Pos)                          /*!< SCU SFSPE_10: EPD Mask              */
+#define SCU_SFSPE_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_10: EPUN Position         */
+#define SCU_SFSPE_10_EPUN_Msk                                 (0x01UL << SCU_SFSPE_10_EPUN_Pos)                         /*!< SCU SFSPE_10: EPUN Mask             */
+#define SCU_SFSPE_10_EHS_Pos                                  5                                                         /*!< SCU SFSPE_10: EHS Position          */
+#define SCU_SFSPE_10_EHS_Msk                                  (0x01UL << SCU_SFSPE_10_EHS_Pos)                          /*!< SCU SFSPE_10: EHS Mask              */
+#define SCU_SFSPE_10_EZI_Pos                                  6                                                         /*!< SCU SFSPE_10: EZI Position          */
+#define SCU_SFSPE_10_EZI_Msk                                  (0x01UL << SCU_SFSPE_10_EZI_Pos)                          /*!< SCU SFSPE_10: EZI Mask              */
+#define SCU_SFSPE_10_EHD_Pos                                  8                                                         /*!< SCU SFSPE_10: EHD Position          */
+#define SCU_SFSPE_10_EHD_Msk                                  (0x03UL << SCU_SFSPE_10_EHD_Pos)                          /*!< SCU SFSPE_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_11  ------------------------------------------
+#define SCU_SFSPE_11_MODE_Pos                                 0                                                         /*!< SCU SFSPE_11: MODE Position         */
+#define SCU_SFSPE_11_MODE_Msk                                 (0x07UL << SCU_SFSPE_11_MODE_Pos)                         /*!< SCU SFSPE_11: MODE Mask             */
+#define SCU_SFSPE_11_EPD_Pos                                  3                                                         /*!< SCU SFSPE_11: EPD Position          */
+#define SCU_SFSPE_11_EPD_Msk                                  (0x01UL << SCU_SFSPE_11_EPD_Pos)                          /*!< SCU SFSPE_11: EPD Mask              */
+#define SCU_SFSPE_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_11: EPUN Position         */
+#define SCU_SFSPE_11_EPUN_Msk                                 (0x01UL << SCU_SFSPE_11_EPUN_Pos)                         /*!< SCU SFSPE_11: EPUN Mask             */
+#define SCU_SFSPE_11_EHS_Pos                                  5                                                         /*!< SCU SFSPE_11: EHS Position          */
+#define SCU_SFSPE_11_EHS_Msk                                  (0x01UL << SCU_SFSPE_11_EHS_Pos)                          /*!< SCU SFSPE_11: EHS Mask              */
+#define SCU_SFSPE_11_EZI_Pos                                  6                                                         /*!< SCU SFSPE_11: EZI Position          */
+#define SCU_SFSPE_11_EZI_Msk                                  (0x01UL << SCU_SFSPE_11_EZI_Pos)                          /*!< SCU SFSPE_11: EZI Mask              */
+#define SCU_SFSPE_11_EHD_Pos                                  8                                                         /*!< SCU SFSPE_11: EHD Position          */
+#define SCU_SFSPE_11_EHD_Msk                                  (0x03UL << SCU_SFSPE_11_EHD_Pos)                          /*!< SCU SFSPE_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_12  ------------------------------------------
+#define SCU_SFSPE_12_MODE_Pos                                 0                                                         /*!< SCU SFSPE_12: MODE Position         */
+#define SCU_SFSPE_12_MODE_Msk                                 (0x07UL << SCU_SFSPE_12_MODE_Pos)                         /*!< SCU SFSPE_12: MODE Mask             */
+#define SCU_SFSPE_12_EPD_Pos                                  3                                                         /*!< SCU SFSPE_12: EPD Position          */
+#define SCU_SFSPE_12_EPD_Msk                                  (0x01UL << SCU_SFSPE_12_EPD_Pos)                          /*!< SCU SFSPE_12: EPD Mask              */
+#define SCU_SFSPE_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_12: EPUN Position         */
+#define SCU_SFSPE_12_EPUN_Msk                                 (0x01UL << SCU_SFSPE_12_EPUN_Pos)                         /*!< SCU SFSPE_12: EPUN Mask             */
+#define SCU_SFSPE_12_EHS_Pos                                  5                                                         /*!< SCU SFSPE_12: EHS Position          */
+#define SCU_SFSPE_12_EHS_Msk                                  (0x01UL << SCU_SFSPE_12_EHS_Pos)                          /*!< SCU SFSPE_12: EHS Mask              */
+#define SCU_SFSPE_12_EZI_Pos                                  6                                                         /*!< SCU SFSPE_12: EZI Position          */
+#define SCU_SFSPE_12_EZI_Msk                                  (0x01UL << SCU_SFSPE_12_EZI_Pos)                          /*!< SCU SFSPE_12: EZI Mask              */
+#define SCU_SFSPE_12_EHD_Pos                                  8                                                         /*!< SCU SFSPE_12: EHD Position          */
+#define SCU_SFSPE_12_EHD_Msk                                  (0x03UL << SCU_SFSPE_12_EHD_Pos)                          /*!< SCU SFSPE_12: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_13  ------------------------------------------
+#define SCU_SFSPE_13_MODE_Pos                                 0                                                         /*!< SCU SFSPE_13: MODE Position         */
+#define SCU_SFSPE_13_MODE_Msk                                 (0x07UL << SCU_SFSPE_13_MODE_Pos)                         /*!< SCU SFSPE_13: MODE Mask             */
+#define SCU_SFSPE_13_EPD_Pos                                  3                                                         /*!< SCU SFSPE_13: EPD Position          */
+#define SCU_SFSPE_13_EPD_Msk                                  (0x01UL << SCU_SFSPE_13_EPD_Pos)                          /*!< SCU SFSPE_13: EPD Mask              */
+#define SCU_SFSPE_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_13: EPUN Position         */
+#define SCU_SFSPE_13_EPUN_Msk                                 (0x01UL << SCU_SFSPE_13_EPUN_Pos)                         /*!< SCU SFSPE_13: EPUN Mask             */
+#define SCU_SFSPE_13_EHS_Pos                                  5                                                         /*!< SCU SFSPE_13: EHS Position          */
+#define SCU_SFSPE_13_EHS_Msk                                  (0x01UL << SCU_SFSPE_13_EHS_Pos)                          /*!< SCU SFSPE_13: EHS Mask              */
+#define SCU_SFSPE_13_EZI_Pos                                  6                                                         /*!< SCU SFSPE_13: EZI Position          */
+#define SCU_SFSPE_13_EZI_Msk                                  (0x01UL << SCU_SFSPE_13_EZI_Pos)                          /*!< SCU SFSPE_13: EZI Mask              */
+#define SCU_SFSPE_13_EHD_Pos                                  8                                                         /*!< SCU SFSPE_13: EHD Position          */
+#define SCU_SFSPE_13_EHD_Msk                                  (0x03UL << SCU_SFSPE_13_EHD_Pos)                          /*!< SCU SFSPE_13: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_14  ------------------------------------------
+#define SCU_SFSPE_14_MODE_Pos                                 0                                                         /*!< SCU SFSPE_14: MODE Position         */
+#define SCU_SFSPE_14_MODE_Msk                                 (0x07UL << SCU_SFSPE_14_MODE_Pos)                         /*!< SCU SFSPE_14: MODE Mask             */
+#define SCU_SFSPE_14_EPD_Pos                                  3                                                         /*!< SCU SFSPE_14: EPD Position          */
+#define SCU_SFSPE_14_EPD_Msk                                  (0x01UL << SCU_SFSPE_14_EPD_Pos)                          /*!< SCU SFSPE_14: EPD Mask              */
+#define SCU_SFSPE_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_14: EPUN Position         */
+#define SCU_SFSPE_14_EPUN_Msk                                 (0x01UL << SCU_SFSPE_14_EPUN_Pos)                         /*!< SCU SFSPE_14: EPUN Mask             */
+#define SCU_SFSPE_14_EHS_Pos                                  5                                                         /*!< SCU SFSPE_14: EHS Position          */
+#define SCU_SFSPE_14_EHS_Msk                                  (0x01UL << SCU_SFSPE_14_EHS_Pos)                          /*!< SCU SFSPE_14: EHS Mask              */
+#define SCU_SFSPE_14_EZI_Pos                                  6                                                         /*!< SCU SFSPE_14: EZI Position          */
+#define SCU_SFSPE_14_EZI_Msk                                  (0x01UL << SCU_SFSPE_14_EZI_Pos)                          /*!< SCU SFSPE_14: EZI Mask              */
+#define SCU_SFSPE_14_EHD_Pos                                  8                                                         /*!< SCU SFSPE_14: EHD Position          */
+#define SCU_SFSPE_14_EHD_Msk                                  (0x03UL << SCU_SFSPE_14_EHD_Pos)                          /*!< SCU SFSPE_14: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPE_15  ------------------------------------------
+#define SCU_SFSPE_15_MODE_Pos                                 0                                                         /*!< SCU SFSPE_15: MODE Position         */
+#define SCU_SFSPE_15_MODE_Msk                                 (0x07UL << SCU_SFSPE_15_MODE_Pos)                         /*!< SCU SFSPE_15: MODE Mask             */
+#define SCU_SFSPE_15_EPD_Pos                                  3                                                         /*!< SCU SFSPE_15: EPD Position          */
+#define SCU_SFSPE_15_EPD_Msk                                  (0x01UL << SCU_SFSPE_15_EPD_Pos)                          /*!< SCU SFSPE_15: EPD Mask              */
+#define SCU_SFSPE_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_15: EPUN Position         */
+#define SCU_SFSPE_15_EPUN_Msk                                 (0x01UL << SCU_SFSPE_15_EPUN_Pos)                         /*!< SCU SFSPE_15: EPUN Mask             */
+#define SCU_SFSPE_15_EHS_Pos                                  5                                                         /*!< SCU SFSPE_15: EHS Position          */
+#define SCU_SFSPE_15_EHS_Msk                                  (0x01UL << SCU_SFSPE_15_EHS_Pos)                          /*!< SCU SFSPE_15: EHS Mask              */
+#define SCU_SFSPE_15_EZI_Pos                                  6                                                         /*!< SCU SFSPE_15: EZI Position          */
+#define SCU_SFSPE_15_EZI_Msk                                  (0x01UL << SCU_SFSPE_15_EZI_Pos)                          /*!< SCU SFSPE_15: EZI Mask              */
+#define SCU_SFSPE_15_EHD_Pos                                  8                                                         /*!< SCU SFSPE_15: EHD Position          */
+#define SCU_SFSPE_15_EHD_Msk                                  (0x03UL << SCU_SFSPE_15_EHD_Pos)                          /*!< SCU SFSPE_15: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSPF_0  ------------------------------------------
+#define SCU_SFSPF_0_MODE_Pos                                  0                                                         /*!< SCU SFSPF_0: MODE Position          */
+#define SCU_SFSPF_0_MODE_Msk                                  (0x07UL << SCU_SFSPF_0_MODE_Pos)                          /*!< SCU SFSPF_0: MODE Mask              */
+#define SCU_SFSPF_0_EPD_Pos                                   3                                                         /*!< SCU SFSPF_0: EPD Position           */
+#define SCU_SFSPF_0_EPD_Msk                                   (0x01UL << SCU_SFSPF_0_EPD_Pos)                           /*!< SCU SFSPF_0: EPD Mask               */
+#define SCU_SFSPF_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_0: EPUN Position          */
+#define SCU_SFSPF_0_EPUN_Msk                                  (0x01UL << SCU_SFSPF_0_EPUN_Pos)                          /*!< SCU SFSPF_0: EPUN Mask              */
+#define SCU_SFSPF_0_EHS_Pos                                   5                                                         /*!< SCU SFSPF_0: EHS Position           */
+#define SCU_SFSPF_0_EHS_Msk                                   (0x01UL << SCU_SFSPF_0_EHS_Pos)                           /*!< SCU SFSPF_0: EHS Mask               */
+#define SCU_SFSPF_0_EZI_Pos                                   6                                                         /*!< SCU SFSPF_0: EZI Position           */
+#define SCU_SFSPF_0_EZI_Msk                                   (0x01UL << SCU_SFSPF_0_EZI_Pos)                           /*!< SCU SFSPF_0: EZI Mask               */
+#define SCU_SFSPF_0_EHD_Pos                                   8                                                         /*!< SCU SFSPF_0: EHD Position           */
+#define SCU_SFSPF_0_EHD_Msk                                   (0x03UL << SCU_SFSPF_0_EHD_Pos)                           /*!< SCU SFSPF_0: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_1  ------------------------------------------
+#define SCU_SFSPF_1_MODE_Pos                                  0                                                         /*!< SCU SFSPF_1: MODE Position          */
+#define SCU_SFSPF_1_MODE_Msk                                  (0x07UL << SCU_SFSPF_1_MODE_Pos)                          /*!< SCU SFSPF_1: MODE Mask              */
+#define SCU_SFSPF_1_EPD_Pos                                   3                                                         /*!< SCU SFSPF_1: EPD Position           */
+#define SCU_SFSPF_1_EPD_Msk                                   (0x01UL << SCU_SFSPF_1_EPD_Pos)                           /*!< SCU SFSPF_1: EPD Mask               */
+#define SCU_SFSPF_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_1: EPUN Position          */
+#define SCU_SFSPF_1_EPUN_Msk                                  (0x01UL << SCU_SFSPF_1_EPUN_Pos)                          /*!< SCU SFSPF_1: EPUN Mask              */
+#define SCU_SFSPF_1_EHS_Pos                                   5                                                         /*!< SCU SFSPF_1: EHS Position           */
+#define SCU_SFSPF_1_EHS_Msk                                   (0x01UL << SCU_SFSPF_1_EHS_Pos)                           /*!< SCU SFSPF_1: EHS Mask               */
+#define SCU_SFSPF_1_EZI_Pos                                   6                                                         /*!< SCU SFSPF_1: EZI Position           */
+#define SCU_SFSPF_1_EZI_Msk                                   (0x01UL << SCU_SFSPF_1_EZI_Pos)                           /*!< SCU SFSPF_1: EZI Mask               */
+#define SCU_SFSPF_1_EHD_Pos                                   8                                                         /*!< SCU SFSPF_1: EHD Position           */
+#define SCU_SFSPF_1_EHD_Msk                                   (0x03UL << SCU_SFSPF_1_EHD_Pos)                           /*!< SCU SFSPF_1: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_2  ------------------------------------------
+#define SCU_SFSPF_2_MODE_Pos                                  0                                                         /*!< SCU SFSPF_2: MODE Position          */
+#define SCU_SFSPF_2_MODE_Msk                                  (0x07UL << SCU_SFSPF_2_MODE_Pos)                          /*!< SCU SFSPF_2: MODE Mask              */
+#define SCU_SFSPF_2_EPD_Pos                                   3                                                         /*!< SCU SFSPF_2: EPD Position           */
+#define SCU_SFSPF_2_EPD_Msk                                   (0x01UL << SCU_SFSPF_2_EPD_Pos)                           /*!< SCU SFSPF_2: EPD Mask               */
+#define SCU_SFSPF_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_2: EPUN Position          */
+#define SCU_SFSPF_2_EPUN_Msk                                  (0x01UL << SCU_SFSPF_2_EPUN_Pos)                          /*!< SCU SFSPF_2: EPUN Mask              */
+#define SCU_SFSPF_2_EHS_Pos                                   5                                                         /*!< SCU SFSPF_2: EHS Position           */
+#define SCU_SFSPF_2_EHS_Msk                                   (0x01UL << SCU_SFSPF_2_EHS_Pos)                           /*!< SCU SFSPF_2: EHS Mask               */
+#define SCU_SFSPF_2_EZI_Pos                                   6                                                         /*!< SCU SFSPF_2: EZI Position           */
+#define SCU_SFSPF_2_EZI_Msk                                   (0x01UL << SCU_SFSPF_2_EZI_Pos)                           /*!< SCU SFSPF_2: EZI Mask               */
+#define SCU_SFSPF_2_EHD_Pos                                   8                                                         /*!< SCU SFSPF_2: EHD Position           */
+#define SCU_SFSPF_2_EHD_Msk                                   (0x03UL << SCU_SFSPF_2_EHD_Pos)                           /*!< SCU SFSPF_2: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_3  ------------------------------------------
+#define SCU_SFSPF_3_MODE_Pos                                  0                                                         /*!< SCU SFSPF_3: MODE Position          */
+#define SCU_SFSPF_3_MODE_Msk                                  (0x07UL << SCU_SFSPF_3_MODE_Pos)                          /*!< SCU SFSPF_3: MODE Mask              */
+#define SCU_SFSPF_3_EPD_Pos                                   3                                                         /*!< SCU SFSPF_3: EPD Position           */
+#define SCU_SFSPF_3_EPD_Msk                                   (0x01UL << SCU_SFSPF_3_EPD_Pos)                           /*!< SCU SFSPF_3: EPD Mask               */
+#define SCU_SFSPF_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_3: EPUN Position          */
+#define SCU_SFSPF_3_EPUN_Msk                                  (0x01UL << SCU_SFSPF_3_EPUN_Pos)                          /*!< SCU SFSPF_3: EPUN Mask              */
+#define SCU_SFSPF_3_EHS_Pos                                   5                                                         /*!< SCU SFSPF_3: EHS Position           */
+#define SCU_SFSPF_3_EHS_Msk                                   (0x01UL << SCU_SFSPF_3_EHS_Pos)                           /*!< SCU SFSPF_3: EHS Mask               */
+#define SCU_SFSPF_3_EZI_Pos                                   6                                                         /*!< SCU SFSPF_3: EZI Position           */
+#define SCU_SFSPF_3_EZI_Msk                                   (0x01UL << SCU_SFSPF_3_EZI_Pos)                           /*!< SCU SFSPF_3: EZI Mask               */
+#define SCU_SFSPF_3_EHD_Pos                                   8                                                         /*!< SCU SFSPF_3: EHD Position           */
+#define SCU_SFSPF_3_EHD_Msk                                   (0x03UL << SCU_SFSPF_3_EHD_Pos)                           /*!< SCU SFSPF_3: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_4  ------------------------------------------
+#define SCU_SFSPF_4_MODE_Pos                                  0                                                         /*!< SCU SFSPF_4: MODE Position          */
+#define SCU_SFSPF_4_MODE_Msk                                  (0x07UL << SCU_SFSPF_4_MODE_Pos)                          /*!< SCU SFSPF_4: MODE Mask              */
+#define SCU_SFSPF_4_EPD_Pos                                   3                                                         /*!< SCU SFSPF_4: EPD Position           */
+#define SCU_SFSPF_4_EPD_Msk                                   (0x01UL << SCU_SFSPF_4_EPD_Pos)                           /*!< SCU SFSPF_4: EPD Mask               */
+#define SCU_SFSPF_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_4: EPUN Position          */
+#define SCU_SFSPF_4_EPUN_Msk                                  (0x01UL << SCU_SFSPF_4_EPUN_Pos)                          /*!< SCU SFSPF_4: EPUN Mask              */
+#define SCU_SFSPF_4_EHS_Pos                                   5                                                         /*!< SCU SFSPF_4: EHS Position           */
+#define SCU_SFSPF_4_EHS_Msk                                   (0x01UL << SCU_SFSPF_4_EHS_Pos)                           /*!< SCU SFSPF_4: EHS Mask               */
+#define SCU_SFSPF_4_EZI_Pos                                   6                                                         /*!< SCU SFSPF_4: EZI Position           */
+#define SCU_SFSPF_4_EZI_Msk                                   (0x01UL << SCU_SFSPF_4_EZI_Pos)                           /*!< SCU SFSPF_4: EZI Mask               */
+#define SCU_SFSPF_4_EHD_Pos                                   8                                                         /*!< SCU SFSPF_4: EHD Position           */
+#define SCU_SFSPF_4_EHD_Msk                                   (0x03UL << SCU_SFSPF_4_EHD_Pos)                           /*!< SCU SFSPF_4: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_5  ------------------------------------------
+#define SCU_SFSPF_5_MODE_Pos                                  0                                                         /*!< SCU SFSPF_5: MODE Position          */
+#define SCU_SFSPF_5_MODE_Msk                                  (0x07UL << SCU_SFSPF_5_MODE_Pos)                          /*!< SCU SFSPF_5: MODE Mask              */
+#define SCU_SFSPF_5_EPD_Pos                                   3                                                         /*!< SCU SFSPF_5: EPD Position           */
+#define SCU_SFSPF_5_EPD_Msk                                   (0x01UL << SCU_SFSPF_5_EPD_Pos)                           /*!< SCU SFSPF_5: EPD Mask               */
+#define SCU_SFSPF_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_5: EPUN Position          */
+#define SCU_SFSPF_5_EPUN_Msk                                  (0x01UL << SCU_SFSPF_5_EPUN_Pos)                          /*!< SCU SFSPF_5: EPUN Mask              */
+#define SCU_SFSPF_5_EHS_Pos                                   5                                                         /*!< SCU SFSPF_5: EHS Position           */
+#define SCU_SFSPF_5_EHS_Msk                                   (0x01UL << SCU_SFSPF_5_EHS_Pos)                           /*!< SCU SFSPF_5: EHS Mask               */
+#define SCU_SFSPF_5_EZI_Pos                                   6                                                         /*!< SCU SFSPF_5: EZI Position           */
+#define SCU_SFSPF_5_EZI_Msk                                   (0x01UL << SCU_SFSPF_5_EZI_Pos)                           /*!< SCU SFSPF_5: EZI Mask               */
+#define SCU_SFSPF_5_EHD_Pos                                   8                                                         /*!< SCU SFSPF_5: EHD Position           */
+#define SCU_SFSPF_5_EHD_Msk                                   (0x03UL << SCU_SFSPF_5_EHD_Pos)                           /*!< SCU SFSPF_5: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_6  ------------------------------------------
+#define SCU_SFSPF_6_MODE_Pos                                  0                                                         /*!< SCU SFSPF_6: MODE Position          */
+#define SCU_SFSPF_6_MODE_Msk                                  (0x07UL << SCU_SFSPF_6_MODE_Pos)                          /*!< SCU SFSPF_6: MODE Mask              */
+#define SCU_SFSPF_6_EPD_Pos                                   3                                                         /*!< SCU SFSPF_6: EPD Position           */
+#define SCU_SFSPF_6_EPD_Msk                                   (0x01UL << SCU_SFSPF_6_EPD_Pos)                           /*!< SCU SFSPF_6: EPD Mask               */
+#define SCU_SFSPF_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_6: EPUN Position          */
+#define SCU_SFSPF_6_EPUN_Msk                                  (0x01UL << SCU_SFSPF_6_EPUN_Pos)                          /*!< SCU SFSPF_6: EPUN Mask              */
+#define SCU_SFSPF_6_EHS_Pos                                   5                                                         /*!< SCU SFSPF_6: EHS Position           */
+#define SCU_SFSPF_6_EHS_Msk                                   (0x01UL << SCU_SFSPF_6_EHS_Pos)                           /*!< SCU SFSPF_6: EHS Mask               */
+#define SCU_SFSPF_6_EZI_Pos                                   6                                                         /*!< SCU SFSPF_6: EZI Position           */
+#define SCU_SFSPF_6_EZI_Msk                                   (0x01UL << SCU_SFSPF_6_EZI_Pos)                           /*!< SCU SFSPF_6: EZI Mask               */
+#define SCU_SFSPF_6_EHD_Pos                                   8                                                         /*!< SCU SFSPF_6: EHD Position           */
+#define SCU_SFSPF_6_EHD_Msk                                   (0x03UL << SCU_SFSPF_6_EHD_Pos)                           /*!< SCU SFSPF_6: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_7  ------------------------------------------
+#define SCU_SFSPF_7_MODE_Pos                                  0                                                         /*!< SCU SFSPF_7: MODE Position          */
+#define SCU_SFSPF_7_MODE_Msk                                  (0x07UL << SCU_SFSPF_7_MODE_Pos)                          /*!< SCU SFSPF_7: MODE Mask              */
+#define SCU_SFSPF_7_EPD_Pos                                   3                                                         /*!< SCU SFSPF_7: EPD Position           */
+#define SCU_SFSPF_7_EPD_Msk                                   (0x01UL << SCU_SFSPF_7_EPD_Pos)                           /*!< SCU SFSPF_7: EPD Mask               */
+#define SCU_SFSPF_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_7: EPUN Position          */
+#define SCU_SFSPF_7_EPUN_Msk                                  (0x01UL << SCU_SFSPF_7_EPUN_Pos)                          /*!< SCU SFSPF_7: EPUN Mask              */
+#define SCU_SFSPF_7_EHS_Pos                                   5                                                         /*!< SCU SFSPF_7: EHS Position           */
+#define SCU_SFSPF_7_EHS_Msk                                   (0x01UL << SCU_SFSPF_7_EHS_Pos)                           /*!< SCU SFSPF_7: EHS Mask               */
+#define SCU_SFSPF_7_EZI_Pos                                   6                                                         /*!< SCU SFSPF_7: EZI Position           */
+#define SCU_SFSPF_7_EZI_Msk                                   (0x01UL << SCU_SFSPF_7_EZI_Pos)                           /*!< SCU SFSPF_7: EZI Mask               */
+#define SCU_SFSPF_7_EHD_Pos                                   8                                                         /*!< SCU SFSPF_7: EHD Position           */
+#define SCU_SFSPF_7_EHD_Msk                                   (0x03UL << SCU_SFSPF_7_EHD_Pos)                           /*!< SCU SFSPF_7: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_8  ------------------------------------------
+#define SCU_SFSPF_8_MODE_Pos                                  0                                                         /*!< SCU SFSPF_8: MODE Position          */
+#define SCU_SFSPF_8_MODE_Msk                                  (0x07UL << SCU_SFSPF_8_MODE_Pos)                          /*!< SCU SFSPF_8: MODE Mask              */
+#define SCU_SFSPF_8_EPD_Pos                                   3                                                         /*!< SCU SFSPF_8: EPD Position           */
+#define SCU_SFSPF_8_EPD_Msk                                   (0x01UL << SCU_SFSPF_8_EPD_Pos)                           /*!< SCU SFSPF_8: EPD Mask               */
+#define SCU_SFSPF_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_8: EPUN Position          */
+#define SCU_SFSPF_8_EPUN_Msk                                  (0x01UL << SCU_SFSPF_8_EPUN_Pos)                          /*!< SCU SFSPF_8: EPUN Mask              */
+#define SCU_SFSPF_8_EHS_Pos                                   5                                                         /*!< SCU SFSPF_8: EHS Position           */
+#define SCU_SFSPF_8_EHS_Msk                                   (0x01UL << SCU_SFSPF_8_EHS_Pos)                           /*!< SCU SFSPF_8: EHS Mask               */
+#define SCU_SFSPF_8_EZI_Pos                                   6                                                         /*!< SCU SFSPF_8: EZI Position           */
+#define SCU_SFSPF_8_EZI_Msk                                   (0x01UL << SCU_SFSPF_8_EZI_Pos)                           /*!< SCU SFSPF_8: EZI Mask               */
+#define SCU_SFSPF_8_EHD_Pos                                   8                                                         /*!< SCU SFSPF_8: EHD Position           */
+#define SCU_SFSPF_8_EHD_Msk                                   (0x03UL << SCU_SFSPF_8_EHD_Pos)                           /*!< SCU SFSPF_8: EHD Mask               */
+
+// ---------------------------------------  SCU_SFSPF_9  ------------------------------------------
+#define SCU_SFSPF_9_MODE_Pos                                  0                                                         /*!< SCU SFSPF_9: MODE Position          */
+#define SCU_SFSPF_9_MODE_Msk                                  (0x07UL << SCU_SFSPF_9_MODE_Pos)                          /*!< SCU SFSPF_9: MODE Mask              */
+#define SCU_SFSPF_9_EPD_Pos                                   3                                                         /*!< SCU SFSPF_9: EPD Position           */
+#define SCU_SFSPF_9_EPD_Msk                                   (0x01UL << SCU_SFSPF_9_EPD_Pos)                           /*!< SCU SFSPF_9: EPD Mask               */
+#define SCU_SFSPF_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_9: EPUN Position          */
+#define SCU_SFSPF_9_EPUN_Msk                                  (0x01UL << SCU_SFSPF_9_EPUN_Pos)                          /*!< SCU SFSPF_9: EPUN Mask              */
+#define SCU_SFSPF_9_EHS_Pos                                   5                                                         /*!< SCU SFSPF_9: EHS Position           */
+#define SCU_SFSPF_9_EHS_Msk                                   (0x01UL << SCU_SFSPF_9_EHS_Pos)                           /*!< SCU SFSPF_9: EHS Mask               */
+#define SCU_SFSPF_9_EZI_Pos                                   6                                                         /*!< SCU SFSPF_9: EZI Position           */
+#define SCU_SFSPF_9_EZI_Msk                                   (0x01UL << SCU_SFSPF_9_EZI_Pos)                           /*!< SCU SFSPF_9: EZI Mask               */
+#define SCU_SFSPF_9_EHD_Pos                                   8                                                         /*!< SCU SFSPF_9: EHD Position           */
+#define SCU_SFSPF_9_EHD_Msk                                   (0x03UL << SCU_SFSPF_9_EHD_Pos)                           /*!< SCU SFSPF_9: EHD Mask               */
+
+// --------------------------------------  SCU_SFSPF_10  ------------------------------------------
+#define SCU_SFSPF_10_MODE_Pos                                 0                                                         /*!< SCU SFSPF_10: MODE Position         */
+#define SCU_SFSPF_10_MODE_Msk                                 (0x07UL << SCU_SFSPF_10_MODE_Pos)                         /*!< SCU SFSPF_10: MODE Mask             */
+#define SCU_SFSPF_10_EPD_Pos                                  3                                                         /*!< SCU SFSPF_10: EPD Position          */
+#define SCU_SFSPF_10_EPD_Msk                                  (0x01UL << SCU_SFSPF_10_EPD_Pos)                          /*!< SCU SFSPF_10: EPD Mask              */
+#define SCU_SFSPF_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_10: EPUN Position         */
+#define SCU_SFSPF_10_EPUN_Msk                                 (0x01UL << SCU_SFSPF_10_EPUN_Pos)                         /*!< SCU SFSPF_10: EPUN Mask             */
+#define SCU_SFSPF_10_EHS_Pos                                  5                                                         /*!< SCU SFSPF_10: EHS Position          */
+#define SCU_SFSPF_10_EHS_Msk                                  (0x01UL << SCU_SFSPF_10_EHS_Pos)                          /*!< SCU SFSPF_10: EHS Mask              */
+#define SCU_SFSPF_10_EZI_Pos                                  6                                                         /*!< SCU SFSPF_10: EZI Position          */
+#define SCU_SFSPF_10_EZI_Msk                                  (0x01UL << SCU_SFSPF_10_EZI_Pos)                          /*!< SCU SFSPF_10: EZI Mask              */
+#define SCU_SFSPF_10_EHD_Pos                                  8                                                         /*!< SCU SFSPF_10: EHD Position          */
+#define SCU_SFSPF_10_EHD_Msk                                  (0x03UL << SCU_SFSPF_10_EHD_Pos)                          /*!< SCU SFSPF_10: EHD Mask              */
+
+// --------------------------------------  SCU_SFSPF_11  ------------------------------------------
+#define SCU_SFSPF_11_MODE_Pos                                 0                                                         /*!< SCU SFSPF_11: MODE Position         */
+#define SCU_SFSPF_11_MODE_Msk                                 (0x07UL << SCU_SFSPF_11_MODE_Pos)                         /*!< SCU SFSPF_11: MODE Mask             */
+#define SCU_SFSPF_11_EPD_Pos                                  3                                                         /*!< SCU SFSPF_11: EPD Position          */
+#define SCU_SFSPF_11_EPD_Msk                                  (0x01UL << SCU_SFSPF_11_EPD_Pos)                          /*!< SCU SFSPF_11: EPD Mask              */
+#define SCU_SFSPF_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_11: EPUN Position         */
+#define SCU_SFSPF_11_EPUN_Msk                                 (0x01UL << SCU_SFSPF_11_EPUN_Pos)                         /*!< SCU SFSPF_11: EPUN Mask             */
+#define SCU_SFSPF_11_EHS_Pos                                  5                                                         /*!< SCU SFSPF_11: EHS Position          */
+#define SCU_SFSPF_11_EHS_Msk                                  (0x01UL << SCU_SFSPF_11_EHS_Pos)                          /*!< SCU SFSPF_11: EHS Mask              */
+#define SCU_SFSPF_11_EZI_Pos                                  6                                                         /*!< SCU SFSPF_11: EZI Position          */
+#define SCU_SFSPF_11_EZI_Msk                                  (0x01UL << SCU_SFSPF_11_EZI_Pos)                          /*!< SCU SFSPF_11: EZI Mask              */
+#define SCU_SFSPF_11_EHD_Pos                                  8                                                         /*!< SCU SFSPF_11: EHD Position          */
+#define SCU_SFSPF_11_EHD_Msk                                  (0x03UL << SCU_SFSPF_11_EHD_Pos)                          /*!< SCU SFSPF_11: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_0  ------------------------------------------
+#define SCU_SFSCLK_0_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_0: MODE Position         */
+#define SCU_SFSCLK_0_MODE_Msk                                 (0x07UL << SCU_SFSCLK_0_MODE_Pos)                         /*!< SCU SFSCLK_0: MODE Mask             */
+#define SCU_SFSCLK_0_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_0: EPD Position          */
+#define SCU_SFSCLK_0_EPD_Msk                                  (0x01UL << SCU_SFSCLK_0_EPD_Pos)                          /*!< SCU SFSCLK_0: EPD Mask              */
+#define SCU_SFSCLK_0_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_0: EPUN Position         */
+#define SCU_SFSCLK_0_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_0_EPUN_Pos)                         /*!< SCU SFSCLK_0: EPUN Mask             */
+#define SCU_SFSCLK_0_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_0: EHS Position          */
+#define SCU_SFSCLK_0_EHS_Msk                                  (0x01UL << SCU_SFSCLK_0_EHS_Pos)                          /*!< SCU SFSCLK_0: EHS Mask              */
+#define SCU_SFSCLK_0_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_0: EZI Position          */
+#define SCU_SFSCLK_0_EZI_Msk                                  (0x01UL << SCU_SFSCLK_0_EZI_Pos)                          /*!< SCU SFSCLK_0: EZI Mask              */
+#define SCU_SFSCLK_0_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_0: EHD Position          */
+#define SCU_SFSCLK_0_EHD_Msk                                  (0x03UL << SCU_SFSCLK_0_EHD_Pos)                          /*!< SCU SFSCLK_0: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_1  ------------------------------------------
+#define SCU_SFSCLK_1_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_1: MODE Position         */
+#define SCU_SFSCLK_1_MODE_Msk                                 (0x07UL << SCU_SFSCLK_1_MODE_Pos)                         /*!< SCU SFSCLK_1: MODE Mask             */
+#define SCU_SFSCLK_1_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_1: EPD Position          */
+#define SCU_SFSCLK_1_EPD_Msk                                  (0x01UL << SCU_SFSCLK_1_EPD_Pos)                          /*!< SCU SFSCLK_1: EPD Mask              */
+#define SCU_SFSCLK_1_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_1: EPUN Position         */
+#define SCU_SFSCLK_1_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_1_EPUN_Pos)                         /*!< SCU SFSCLK_1: EPUN Mask             */
+#define SCU_SFSCLK_1_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_1: EHS Position          */
+#define SCU_SFSCLK_1_EHS_Msk                                  (0x01UL << SCU_SFSCLK_1_EHS_Pos)                          /*!< SCU SFSCLK_1: EHS Mask              */
+#define SCU_SFSCLK_1_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_1: EZI Position          */
+#define SCU_SFSCLK_1_EZI_Msk                                  (0x01UL << SCU_SFSCLK_1_EZI_Pos)                          /*!< SCU SFSCLK_1: EZI Mask              */
+#define SCU_SFSCLK_1_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_1: EHD Position          */
+#define SCU_SFSCLK_1_EHD_Msk                                  (0x03UL << SCU_SFSCLK_1_EHD_Pos)                          /*!< SCU SFSCLK_1: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_2  ------------------------------------------
+#define SCU_SFSCLK_2_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_2: MODE Position         */
+#define SCU_SFSCLK_2_MODE_Msk                                 (0x07UL << SCU_SFSCLK_2_MODE_Pos)                         /*!< SCU SFSCLK_2: MODE Mask             */
+#define SCU_SFSCLK_2_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_2: EPD Position          */
+#define SCU_SFSCLK_2_EPD_Msk                                  (0x01UL << SCU_SFSCLK_2_EPD_Pos)                          /*!< SCU SFSCLK_2: EPD Mask              */
+#define SCU_SFSCLK_2_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_2: EPUN Position         */
+#define SCU_SFSCLK_2_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_2_EPUN_Pos)                         /*!< SCU SFSCLK_2: EPUN Mask             */
+#define SCU_SFSCLK_2_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_2: EHS Position          */
+#define SCU_SFSCLK_2_EHS_Msk                                  (0x01UL << SCU_SFSCLK_2_EHS_Pos)                          /*!< SCU SFSCLK_2: EHS Mask              */
+#define SCU_SFSCLK_2_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_2: EZI Position          */
+#define SCU_SFSCLK_2_EZI_Msk                                  (0x01UL << SCU_SFSCLK_2_EZI_Pos)                          /*!< SCU SFSCLK_2: EZI Mask              */
+#define SCU_SFSCLK_2_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_2: EHD Position          */
+#define SCU_SFSCLK_2_EHD_Msk                                  (0x03UL << SCU_SFSCLK_2_EHD_Pos)                          /*!< SCU SFSCLK_2: EHD Mask              */
+
+// --------------------------------------  SCU_SFSCLK_3  ------------------------------------------
+#define SCU_SFSCLK_3_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_3: MODE Position         */
+#define SCU_SFSCLK_3_MODE_Msk                                 (0x07UL << SCU_SFSCLK_3_MODE_Pos)                         /*!< SCU SFSCLK_3: MODE Mask             */
+#define SCU_SFSCLK_3_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_3: EPD Position          */
+#define SCU_SFSCLK_3_EPD_Msk                                  (0x01UL << SCU_SFSCLK_3_EPD_Pos)                          /*!< SCU SFSCLK_3: EPD Mask              */
+#define SCU_SFSCLK_3_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_3: EPUN Position         */
+#define SCU_SFSCLK_3_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_3_EPUN_Pos)                         /*!< SCU SFSCLK_3: EPUN Mask             */
+#define SCU_SFSCLK_3_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_3: EHS Position          */
+#define SCU_SFSCLK_3_EHS_Msk                                  (0x01UL << SCU_SFSCLK_3_EHS_Pos)                          /*!< SCU SFSCLK_3: EHS Mask              */
+#define SCU_SFSCLK_3_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_3: EZI Position          */
+#define SCU_SFSCLK_3_EZI_Msk                                  (0x01UL << SCU_SFSCLK_3_EZI_Pos)                          /*!< SCU SFSCLK_3: EZI Mask              */
+#define SCU_SFSCLK_3_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_3: EHD Position          */
+#define SCU_SFSCLK_3_EHD_Msk                                  (0x03UL << SCU_SFSCLK_3_EHD_Pos)                          /*!< SCU SFSCLK_3: EHD Mask              */
+
+// ---------------------------------------  SCU_SFSUSB  -------------------------------------------
+#define SCU_SFSUSB_USB_AIM_Pos                                0                                                         /*!< SCU SFSUSB: USB_AIM Position        */
+#define SCU_SFSUSB_USB_AIM_Msk                                (0x01UL << SCU_SFSUSB_USB_AIM_Pos)                        /*!< SCU SFSUSB: USB_AIM Mask            */
+#define SCU_SFSUSB_USB_ESEA_Pos                               1                                                         /*!< SCU SFSUSB: USB_ESEA Position       */
+#define SCU_SFSUSB_USB_ESEA_Msk                               (0x01UL << SCU_SFSUSB_USB_ESEA_Pos)                       /*!< SCU SFSUSB: USB_ESEA Mask           */
+
+// ---------------------------------------  SCU_SFSI2C0  ------------------------------------------
+#define SCU_SFSI2C0_SDA_EHS_Pos                               0                                                         /*!< SCU SFSI2C0: SDA_EHS Position       */
+#define SCU_SFSI2C0_SDA_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos)                       /*!< SCU SFSI2C0: SDA_EHS Mask           */
+#define SCU_SFSI2C0_SCL_EHS_Pos                               1                                                         /*!< SCU SFSI2C0: SCL_EHS Position       */
+#define SCU_SFSI2C0_SCL_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos)                       /*!< SCU SFSI2C0: SCL_EHS Mask           */
+#define SCU_SFSI2C0_SCL_ECS_Pos                               2                                                         /*!< SCU SFSI2C0: SCL_ECS Position       */
+#define SCU_SFSI2C0_SCL_ECS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos)                       /*!< SCU SFSI2C0: SCL_ECS Mask           */
+
+// ---------------------------------------  SCU_ENAIO0  -------------------------------------------
+#define SCU_ENAIO0_ADC0_0_Pos                                 0                                                         /*!< SCU ENAIO0: ADC0_0 Position         */
+#define SCU_ENAIO0_ADC0_0_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_0_Pos)                         /*!< SCU ENAIO0: ADC0_0 Mask             */
+#define SCU_ENAIO0_ADC0_1_Pos                                 1                                                         /*!< SCU ENAIO0: ADC0_1 Position         */
+#define SCU_ENAIO0_ADC0_1_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_1_Pos)                         /*!< SCU ENAIO0: ADC0_1 Mask             */
+#define SCU_ENAIO0_ADC0_2_Pos                                 2                                                         /*!< SCU ENAIO0: ADC0_2 Position         */
+#define SCU_ENAIO0_ADC0_2_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_2_Pos)                         /*!< SCU ENAIO0: ADC0_2 Mask             */
+#define SCU_ENAIO0_ADC0_3_Pos                                 3                                                         /*!< SCU ENAIO0: ADC0_3 Position         */
+#define SCU_ENAIO0_ADC0_3_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_3_Pos)                         /*!< SCU ENAIO0: ADC0_3 Mask             */
+#define SCU_ENAIO0_ADC0_4_Pos                                 4                                                         /*!< SCU ENAIO0: ADC0_4 Position         */
+#define SCU_ENAIO0_ADC0_4_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_4_Pos)                         /*!< SCU ENAIO0: ADC0_4 Mask             */
+#define SCU_ENAIO0_ADC0_5_Pos                                 5                                                         /*!< SCU ENAIO0: ADC0_5 Position         */
+#define SCU_ENAIO0_ADC0_5_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_5_Pos)                         /*!< SCU ENAIO0: ADC0_5 Mask             */
+#define SCU_ENAIO0_ADC0_6_Pos                                 6                                                         /*!< SCU ENAIO0: ADC0_6 Position         */
+#define SCU_ENAIO0_ADC0_6_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_6_Pos)                         /*!< SCU ENAIO0: ADC0_6 Mask             */
+
+// ---------------------------------------  SCU_ENAIO1  -------------------------------------------
+#define SCU_ENAIO1_ADC1_0_Pos                                 0                                                         /*!< SCU ENAIO1: ADC1_0 Position         */
+#define SCU_ENAIO1_ADC1_0_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_0_Pos)                         /*!< SCU ENAIO1: ADC1_0 Mask             */
+#define SCU_ENAIO1_ADC1_1_Pos                                 1                                                         /*!< SCU ENAIO1: ADC1_1 Position         */
+#define SCU_ENAIO1_ADC1_1_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_1_Pos)                         /*!< SCU ENAIO1: ADC1_1 Mask             */
+#define SCU_ENAIO1_ADC1_2_Pos                                 2                                                         /*!< SCU ENAIO1: ADC1_2 Position         */
+#define SCU_ENAIO1_ADC1_2_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_2_Pos)                         /*!< SCU ENAIO1: ADC1_2 Mask             */
+#define SCU_ENAIO1_ADC1_3_Pos                                 3                                                         /*!< SCU ENAIO1: ADC1_3 Position         */
+#define SCU_ENAIO1_ADC1_3_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_3_Pos)                         /*!< SCU ENAIO1: ADC1_3 Mask             */
+#define SCU_ENAIO1_ADC1_4_Pos                                 4                                                         /*!< SCU ENAIO1: ADC1_4 Position         */
+#define SCU_ENAIO1_ADC1_4_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_4_Pos)                         /*!< SCU ENAIO1: ADC1_4 Mask             */
+#define SCU_ENAIO1_ADC1_5_Pos                                 5                                                         /*!< SCU ENAIO1: ADC1_5 Position         */
+#define SCU_ENAIO1_ADC1_5_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_5_Pos)                         /*!< SCU ENAIO1: ADC1_5 Mask             */
+#define SCU_ENAIO1_ADC1_6_Pos                                 6                                                         /*!< SCU ENAIO1: ADC1_6 Position         */
+#define SCU_ENAIO1_ADC1_6_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_6_Pos)                         /*!< SCU ENAIO1: ADC1_6 Mask             */
+#define SCU_ENAIO1_ADC1_7_Pos                                 7                                                         /*!< SCU ENAIO1: ADC1_7 Position         */
+#define SCU_ENAIO1_ADC1_7_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_7_Pos)                         /*!< SCU ENAIO1: ADC1_7 Mask             */
+
+// ---------------------------------------  SCU_ENAIO2  -------------------------------------------
+#define SCU_ENAIO2_DAC_Pos                                    0                                                         /*!< SCU ENAIO2: DAC Position            */
+#define SCU_ENAIO2_DAC_Msk                                    (0x01UL << SCU_ENAIO2_DAC_Pos)                            /*!< SCU ENAIO2: DAC Mask                */
+#define SCU_ENAIO2_BG_Pos                                     4                                                         /*!< SCU ENAIO2: BG Position             */
+#define SCU_ENAIO2_BG_Msk                                     (0x01UL << SCU_ENAIO2_BG_Pos)                             /*!< SCU ENAIO2: BG Mask                 */
+
+// -------------------------------------  SCU_EMCDELAYCLK  ----------------------------------------
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos                        0                                                         /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos                        4                                                         /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos                        8                                                         /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos                        12                                                        /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos                        16                                                        /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos                        20                                                        /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos                        24                                                        /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask    */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos                        28                                                        /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask    */
+
+// --------------------------------------  SCU_PINTSEL0  ------------------------------------------
+#define SCU_PINTSEL0_INTPIN0_Pos                              0                                                         /*!< SCU PINTSEL0: INTPIN0 Position      */
+#define SCU_PINTSEL0_INTPIN0_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos)                      /*!< SCU PINTSEL0: INTPIN0 Mask          */
+#define SCU_PINTSEL0_PORTSEL0_Pos                             5                                                         /*!< SCU PINTSEL0: PORTSEL0 Position     */
+#define SCU_PINTSEL0_PORTSEL0_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos)                     /*!< SCU PINTSEL0: PORTSEL0 Mask         */
+#define SCU_PINTSEL0_INTPIN1_Pos                              8                                                         /*!< SCU PINTSEL0: INTPIN1 Position      */
+#define SCU_PINTSEL0_INTPIN1_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos)                      /*!< SCU PINTSEL0: INTPIN1 Mask          */
+#define SCU_PINTSEL0_PORTSEL1_Pos                             13                                                        /*!< SCU PINTSEL0: PORTSEL1 Position     */
+#define SCU_PINTSEL0_PORTSEL1_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos)                     /*!< SCU PINTSEL0: PORTSEL1 Mask         */
+#define SCU_PINTSEL0_INTPIN2_Pos                              16                                                        /*!< SCU PINTSEL0: INTPIN2 Position      */
+#define SCU_PINTSEL0_INTPIN2_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos)                      /*!< SCU PINTSEL0: INTPIN2 Mask          */
+#define SCU_PINTSEL0_PORTSEL2_Pos                             21                                                        /*!< SCU PINTSEL0: PORTSEL2 Position     */
+#define SCU_PINTSEL0_PORTSEL2_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos)                     /*!< SCU PINTSEL0: PORTSEL2 Mask         */
+#define SCU_PINTSEL0_INTPIN3_Pos                              24                                                        /*!< SCU PINTSEL0: INTPIN3 Position      */
+#define SCU_PINTSEL0_INTPIN3_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos)                      /*!< SCU PINTSEL0: INTPIN3 Mask          */
+#define SCU_PINTSEL0_PORTSEL3_Pos                             29                                                        /*!< SCU PINTSEL0: PORTSEL3 Position     */
+#define SCU_PINTSEL0_PORTSEL3_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos)                     /*!< SCU PINTSEL0: PORTSEL3 Mask         */
+
+// --------------------------------------  SCU_PINTSEL1  ------------------------------------------
+#define SCU_PINTSEL1_INTPIN4_Pos                              0                                                         /*!< SCU PINTSEL1: INTPIN4 Position      */
+#define SCU_PINTSEL1_INTPIN4_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos)                      /*!< SCU PINTSEL1: INTPIN4 Mask          */
+#define SCU_PINTSEL1_PORTSEL4_Pos                             5                                                         /*!< SCU PINTSEL1: PORTSEL4 Position     */
+#define SCU_PINTSEL1_PORTSEL4_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos)                     /*!< SCU PINTSEL1: PORTSEL4 Mask         */
+#define SCU_PINTSEL1_INTPIN5_Pos                              8                                                         /*!< SCU PINTSEL1: INTPIN5 Position      */
+#define SCU_PINTSEL1_INTPIN5_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos)                      /*!< SCU PINTSEL1: INTPIN5 Mask          */
+#define SCU_PINTSEL1_PORTSEL5_Pos                             13                                                        /*!< SCU PINTSEL1: PORTSEL5 Position     */
+#define SCU_PINTSEL1_PORTSEL5_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos)                     /*!< SCU PINTSEL1: PORTSEL5 Mask         */
+#define SCU_PINTSEL1_INTPIN6_Pos                              16                                                        /*!< SCU PINTSEL1: INTPIN6 Position      */
+#define SCU_PINTSEL1_INTPIN6_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos)                      /*!< SCU PINTSEL1: INTPIN6 Mask          */
+#define SCU_PINTSEL1_PORTSEL6_Pos                             21                                                        /*!< SCU PINTSEL1: PORTSEL6 Position     */
+#define SCU_PINTSEL1_PORTSEL6_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos)                     /*!< SCU PINTSEL1: PORTSEL6 Mask         */
+#define SCU_PINTSEL1_INTPIN7_Pos                              24                                                        /*!< SCU PINTSEL1: INTPIN7 Position      */
+#define SCU_PINTSEL1_INTPIN7_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos)                      /*!< SCU PINTSEL1: INTPIN7 Mask          */
+#define SCU_PINTSEL1_PORTSEL7_Pos                             29                                                        /*!< SCU PINTSEL1: PORTSEL7 Position     */
+#define SCU_PINTSEL1_PORTSEL7_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos)                     /*!< SCU PINTSEL1: PORTSEL7 Mask         */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                             GPIO_PIN_INT Position & Mask                             -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------  GPIO_PIN_INT_ISEL  ---------------------------------------
+#define GPIO_PIN_INT_ISEL_PMODE0_Pos                          0                                                         /*!< GPIO_PIN_INT ISEL: PMODE0 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE0_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE0 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE1_Pos                          1                                                         /*!< GPIO_PIN_INT ISEL: PMODE1 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE1_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE1 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE2_Pos                          2                                                         /*!< GPIO_PIN_INT ISEL: PMODE2 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE2_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE2 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE3_Pos                          3                                                         /*!< GPIO_PIN_INT ISEL: PMODE3 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE3_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE3 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE4_Pos                          4                                                         /*!< GPIO_PIN_INT ISEL: PMODE4 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE4_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE4 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE5_Pos                          5                                                         /*!< GPIO_PIN_INT ISEL: PMODE5 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE5_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE5 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE6_Pos                          6                                                         /*!< GPIO_PIN_INT ISEL: PMODE6 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE6_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE6 Mask      */
+#define GPIO_PIN_INT_ISEL_PMODE7_Pos                          7                                                         /*!< GPIO_PIN_INT ISEL: PMODE7 Position  */
+#define GPIO_PIN_INT_ISEL_PMODE7_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE7 Mask      */
+
+// ------------------------------------  GPIO_PIN_INT_IENR  ---------------------------------------
+#define GPIO_PIN_INT_IENR_ENRL0_Pos                           0                                                         /*!< GPIO_PIN_INT IENR: ENRL0 Position   */
+#define GPIO_PIN_INT_IENR_ENRL0_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL0 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL1_Pos                           1                                                         /*!< GPIO_PIN_INT IENR: ENRL1 Position   */
+#define GPIO_PIN_INT_IENR_ENRL1_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL1 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL2_Pos                           2                                                         /*!< GPIO_PIN_INT IENR: ENRL2 Position   */
+#define GPIO_PIN_INT_IENR_ENRL2_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL2 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL3_Pos                           3                                                         /*!< GPIO_PIN_INT IENR: ENRL3 Position   */
+#define GPIO_PIN_INT_IENR_ENRL3_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL3 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL4_Pos                           4                                                         /*!< GPIO_PIN_INT IENR: ENRL4 Position   */
+#define GPIO_PIN_INT_IENR_ENRL4_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL4 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL5_Pos                           5                                                         /*!< GPIO_PIN_INT IENR: ENRL5 Position   */
+#define GPIO_PIN_INT_IENR_ENRL5_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL5 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL6_Pos                           6                                                         /*!< GPIO_PIN_INT IENR: ENRL6 Position   */
+#define GPIO_PIN_INT_IENR_ENRL6_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL6 Mask       */
+#define GPIO_PIN_INT_IENR_ENRL7_Pos                           7                                                         /*!< GPIO_PIN_INT IENR: ENRL7 Position   */
+#define GPIO_PIN_INT_IENR_ENRL7_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL7 Mask       */
+
+// -----------------------------------  GPIO_PIN_INT_SIENR  ---------------------------------------
+#define GPIO_PIN_INT_SIENR_SETENRL0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL0_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask   */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask   */
+
+// -----------------------------------  GPIO_PIN_INT_CIENR  ---------------------------------------
+#define GPIO_PIN_INT_CIENR_CENRL0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENR: CENRL0 Position */
+#define GPIO_PIN_INT_CIENR_CENRL0_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL0 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENR: CENRL1 Position */
+#define GPIO_PIN_INT_CIENR_CENRL1_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL1 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENR: CENRL2 Position */
+#define GPIO_PIN_INT_CIENR_CENRL2_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL2 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENR: CENRL3 Position */
+#define GPIO_PIN_INT_CIENR_CENRL3_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL3 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENR: CENRL4 Position */
+#define GPIO_PIN_INT_CIENR_CENRL4_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL4 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENR: CENRL5 Position */
+#define GPIO_PIN_INT_CIENR_CENRL5_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL5 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENR: CENRL6 Position */
+#define GPIO_PIN_INT_CIENR_CENRL6_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL6 Mask     */
+#define GPIO_PIN_INT_CIENR_CENRL7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENR: CENRL7 Position */
+#define GPIO_PIN_INT_CIENR_CENRL7_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL7 Mask     */
+
+// ------------------------------------  GPIO_PIN_INT_IENF  ---------------------------------------
+#define GPIO_PIN_INT_IENF_ENAF0_Pos                           0                                                         /*!< GPIO_PIN_INT IENF: ENAF0 Position   */
+#define GPIO_PIN_INT_IENF_ENAF0_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF0 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF1_Pos                           1                                                         /*!< GPIO_PIN_INT IENF: ENAF1 Position   */
+#define GPIO_PIN_INT_IENF_ENAF1_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF1 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF2_Pos                           2                                                         /*!< GPIO_PIN_INT IENF: ENAF2 Position   */
+#define GPIO_PIN_INT_IENF_ENAF2_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF2 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF3_Pos                           3                                                         /*!< GPIO_PIN_INT IENF: ENAF3 Position   */
+#define GPIO_PIN_INT_IENF_ENAF3_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF3 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF4_Pos                           4                                                         /*!< GPIO_PIN_INT IENF: ENAF4 Position   */
+#define GPIO_PIN_INT_IENF_ENAF4_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF4 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF5_Pos                           5                                                         /*!< GPIO_PIN_INT IENF: ENAF5 Position   */
+#define GPIO_PIN_INT_IENF_ENAF5_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF5 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF6_Pos                           6                                                         /*!< GPIO_PIN_INT IENF: ENAF6 Position   */
+#define GPIO_PIN_INT_IENF_ENAF6_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF6 Mask       */
+#define GPIO_PIN_INT_IENF_ENAF7_Pos                           7                                                         /*!< GPIO_PIN_INT IENF: ENAF7 Position   */
+#define GPIO_PIN_INT_IENF_ENAF7_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF7 Mask       */
+
+// -----------------------------------  GPIO_PIN_INT_SIENF  ---------------------------------------
+#define GPIO_PIN_INT_SIENF_SETENAF0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF0_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask   */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask   */
+
+// -----------------------------------  GPIO_PIN_INT_CIENF  ---------------------------------------
+#define GPIO_PIN_INT_CIENF_CENAF0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENF: CENAF0 Position */
+#define GPIO_PIN_INT_CIENF_CENAF0_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF0 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENF: CENAF1 Position */
+#define GPIO_PIN_INT_CIENF_CENAF1_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF1 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENF: CENAF2 Position */
+#define GPIO_PIN_INT_CIENF_CENAF2_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF2 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENF: CENAF3 Position */
+#define GPIO_PIN_INT_CIENF_CENAF3_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF3 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENF: CENAF4 Position */
+#define GPIO_PIN_INT_CIENF_CENAF4_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF4 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENF: CENAF5 Position */
+#define GPIO_PIN_INT_CIENF_CENAF5_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF5 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENF: CENAF6 Position */
+#define GPIO_PIN_INT_CIENF_CENAF6_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF6 Mask     */
+#define GPIO_PIN_INT_CIENF_CENAF7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENF: CENAF7 Position */
+#define GPIO_PIN_INT_CIENF_CENAF7_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF7 Mask     */
+
+// ------------------------------------  GPIO_PIN_INT_RISE  ---------------------------------------
+#define GPIO_PIN_INT_RISE_RDET0_Pos                           0                                                         /*!< GPIO_PIN_INT RISE: RDET0 Position   */
+#define GPIO_PIN_INT_RISE_RDET0_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos)                   /*!< GPIO_PIN_INT RISE: RDET0 Mask       */
+#define GPIO_PIN_INT_RISE_RDET1_Pos                           1                                                         /*!< GPIO_PIN_INT RISE: RDET1 Position   */
+#define GPIO_PIN_INT_RISE_RDET1_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos)                   /*!< GPIO_PIN_INT RISE: RDET1 Mask       */
+#define GPIO_PIN_INT_RISE_RDET2_Pos                           2                                                         /*!< GPIO_PIN_INT RISE: RDET2 Position   */
+#define GPIO_PIN_INT_RISE_RDET2_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos)                   /*!< GPIO_PIN_INT RISE: RDET2 Mask       */
+#define GPIO_PIN_INT_RISE_RDET3_Pos                           3                                                         /*!< GPIO_PIN_INT RISE: RDET3 Position   */
+#define GPIO_PIN_INT_RISE_RDET3_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos)                   /*!< GPIO_PIN_INT RISE: RDET3 Mask       */
+#define GPIO_PIN_INT_RISE_RDET4_Pos                           4                                                         /*!< GPIO_PIN_INT RISE: RDET4 Position   */
+#define GPIO_PIN_INT_RISE_RDET4_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos)                   /*!< GPIO_PIN_INT RISE: RDET4 Mask       */
+#define GPIO_PIN_INT_RISE_RDET5_Pos                           5                                                         /*!< GPIO_PIN_INT RISE: RDET5 Position   */
+#define GPIO_PIN_INT_RISE_RDET5_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos)                   /*!< GPIO_PIN_INT RISE: RDET5 Mask       */
+#define GPIO_PIN_INT_RISE_RDET6_Pos                           6                                                         /*!< GPIO_PIN_INT RISE: RDET6 Position   */
+#define GPIO_PIN_INT_RISE_RDET6_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos)                   /*!< GPIO_PIN_INT RISE: RDET6 Mask       */
+#define GPIO_PIN_INT_RISE_RDET7_Pos                           7                                                         /*!< GPIO_PIN_INT RISE: RDET7 Position   */
+#define GPIO_PIN_INT_RISE_RDET7_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos)                   /*!< GPIO_PIN_INT RISE: RDET7 Mask       */
+
+// ------------------------------------  GPIO_PIN_INT_FALL  ---------------------------------------
+#define GPIO_PIN_INT_FALL_FDET0_Pos                           0                                                         /*!< GPIO_PIN_INT FALL: FDET0 Position   */
+#define GPIO_PIN_INT_FALL_FDET0_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos)                   /*!< GPIO_PIN_INT FALL: FDET0 Mask       */
+#define GPIO_PIN_INT_FALL_FDET1_Pos                           1                                                         /*!< GPIO_PIN_INT FALL: FDET1 Position   */
+#define GPIO_PIN_INT_FALL_FDET1_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos)                   /*!< GPIO_PIN_INT FALL: FDET1 Mask       */
+#define GPIO_PIN_INT_FALL_FDET2_Pos                           2                                                         /*!< GPIO_PIN_INT FALL: FDET2 Position   */
+#define GPIO_PIN_INT_FALL_FDET2_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos)                   /*!< GPIO_PIN_INT FALL: FDET2 Mask       */
+#define GPIO_PIN_INT_FALL_FDET3_Pos                           3                                                         /*!< GPIO_PIN_INT FALL: FDET3 Position   */
+#define GPIO_PIN_INT_FALL_FDET3_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos)                   /*!< GPIO_PIN_INT FALL: FDET3 Mask       */
+#define GPIO_PIN_INT_FALL_FDET4_Pos                           4                                                         /*!< GPIO_PIN_INT FALL: FDET4 Position   */
+#define GPIO_PIN_INT_FALL_FDET4_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos)                   /*!< GPIO_PIN_INT FALL: FDET4 Mask       */
+#define GPIO_PIN_INT_FALL_FDET5_Pos                           5                                                         /*!< GPIO_PIN_INT FALL: FDET5 Position   */
+#define GPIO_PIN_INT_FALL_FDET5_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos)                   /*!< GPIO_PIN_INT FALL: FDET5 Mask       */
+#define GPIO_PIN_INT_FALL_FDET6_Pos                           6                                                         /*!< GPIO_PIN_INT FALL: FDET6 Position   */
+#define GPIO_PIN_INT_FALL_FDET6_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos)                   /*!< GPIO_PIN_INT FALL: FDET6 Mask       */
+#define GPIO_PIN_INT_FALL_FDET7_Pos                           7                                                         /*!< GPIO_PIN_INT FALL: FDET7 Position   */
+#define GPIO_PIN_INT_FALL_FDET7_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos)                   /*!< GPIO_PIN_INT FALL: FDET7 Mask       */
+
+// ------------------------------------  GPIO_PIN_INT_IST  ----------------------------------------
+#define GPIO_PIN_INT_IST_PSTAT0_Pos                           0                                                         /*!< GPIO_PIN_INT IST: PSTAT0 Position   */
+#define GPIO_PIN_INT_IST_PSTAT0_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT0 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT1_Pos                           1                                                         /*!< GPIO_PIN_INT IST: PSTAT1 Position   */
+#define GPIO_PIN_INT_IST_PSTAT1_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT1 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT2_Pos                           2                                                         /*!< GPIO_PIN_INT IST: PSTAT2 Position   */
+#define GPIO_PIN_INT_IST_PSTAT2_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT2 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT3_Pos                           3                                                         /*!< GPIO_PIN_INT IST: PSTAT3 Position   */
+#define GPIO_PIN_INT_IST_PSTAT3_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT3 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT4_Pos                           4                                                         /*!< GPIO_PIN_INT IST: PSTAT4 Position   */
+#define GPIO_PIN_INT_IST_PSTAT4_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT4 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT5_Pos                           5                                                         /*!< GPIO_PIN_INT IST: PSTAT5 Position   */
+#define GPIO_PIN_INT_IST_PSTAT5_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT5 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT6_Pos                           6                                                         /*!< GPIO_PIN_INT IST: PSTAT6 Position   */
+#define GPIO_PIN_INT_IST_PSTAT6_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT6 Mask       */
+#define GPIO_PIN_INT_IST_PSTAT7_Pos                           7                                                         /*!< GPIO_PIN_INT IST: PSTAT7 Position   */
+#define GPIO_PIN_INT_IST_PSTAT7_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT7 Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                            GPIO_GROUP_INTn Position & Mask                           -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------  GPIO_GROUP_INTn_CTRL  --------------------------------------
+#define GPIO_GROUP_INTn_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INTn CTRL: INT Position  */
+#define GPIO_GROUP_INTn_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INTn CTRL: INT Mask      */
+#define GPIO_GROUP_INTn_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INTn CTRL: COMB Position */
+#define GPIO_GROUP_INTn_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INTn CTRL: COMB Mask     */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INTn CTRL: TRIG Position */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INTn CTRL: TRIG Mask     */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL0  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL1  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL2  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL3  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL4  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL5  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL6  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_POL7  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA0  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA1  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA2  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA3  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA4  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA5  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA6  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INTn_PORT_ENA7  -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                            GPIO_GROUP_INT1 Position & Mask                           -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------  GPIO_GROUP_INT1_CTRL  --------------------------------------
+#define GPIO_GROUP_INT1_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INT1 CTRL: INT Position  */
+#define GPIO_GROUP_INT1_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INT1 CTRL: INT Mask      */
+#define GPIO_GROUP_INT1_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INT1 CTRL: COMB Position */
+#define GPIO_GROUP_INT1_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: COMB Mask     */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask     */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL0  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL1  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL2  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL3  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL4  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL5  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL6  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_POL7  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA0  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA1  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA2  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA3  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA4  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA5  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA6  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */
+
+// --------------------------------  GPIO_GROUP_INT1_PORT_ENA7  -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 MCPWM Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  MCPWM_CON  -------------------------------------------
+#define MCPWM_CON_RUN0_Pos                                    0                                                         /*!< MCPWM CON: RUN0 Position            */
+#define MCPWM_CON_RUN0_Msk                                    (0x01UL << MCPWM_CON_RUN0_Pos)                            /*!< MCPWM CON: RUN0 Mask                */
+#define MCPWM_CON_CENTER0_Pos                                 1                                                         /*!< MCPWM CON: CENTER0 Position         */
+#define MCPWM_CON_CENTER0_Msk                                 (0x01UL << MCPWM_CON_CENTER0_Pos)                         /*!< MCPWM CON: CENTER0 Mask             */
+#define MCPWM_CON_POLA0_Pos                                   2                                                         /*!< MCPWM CON: POLA0 Position           */
+#define MCPWM_CON_POLA0_Msk                                   (0x01UL << MCPWM_CON_POLA0_Pos)                           /*!< MCPWM CON: POLA0 Mask               */
+#define MCPWM_CON_DTE0_Pos                                    3                                                         /*!< MCPWM CON: DTE0 Position            */
+#define MCPWM_CON_DTE0_Msk                                    (0x01UL << MCPWM_CON_DTE0_Pos)                            /*!< MCPWM CON: DTE0 Mask                */
+#define MCPWM_CON_DISUP0_Pos                                  4                                                         /*!< MCPWM CON: DISUP0 Position          */
+#define MCPWM_CON_DISUP0_Msk                                  (0x01UL << MCPWM_CON_DISUP0_Pos)                          /*!< MCPWM CON: DISUP0 Mask              */
+#define MCPWM_CON_RUN1_Pos                                    8                                                         /*!< MCPWM CON: RUN1 Position            */
+#define MCPWM_CON_RUN1_Msk                                    (0x01UL << MCPWM_CON_RUN1_Pos)                            /*!< MCPWM CON: RUN1 Mask                */
+#define MCPWM_CON_CENTER1_Pos                                 9                                                         /*!< MCPWM CON: CENTER1 Position         */
+#define MCPWM_CON_CENTER1_Msk                                 (0x01UL << MCPWM_CON_CENTER1_Pos)                         /*!< MCPWM CON: CENTER1 Mask             */
+#define MCPWM_CON_POLA1_Pos                                   10                                                        /*!< MCPWM CON: POLA1 Position           */
+#define MCPWM_CON_POLA1_Msk                                   (0x01UL << MCPWM_CON_POLA1_Pos)                           /*!< MCPWM CON: POLA1 Mask               */
+#define MCPWM_CON_DTE1_Pos                                    11                                                        /*!< MCPWM CON: DTE1 Position            */
+#define MCPWM_CON_DTE1_Msk                                    (0x01UL << MCPWM_CON_DTE1_Pos)                            /*!< MCPWM CON: DTE1 Mask                */
+#define MCPWM_CON_DISUP1_Pos                                  12                                                        /*!< MCPWM CON: DISUP1 Position          */
+#define MCPWM_CON_DISUP1_Msk                                  (0x01UL << MCPWM_CON_DISUP1_Pos)                          /*!< MCPWM CON: DISUP1 Mask              */
+#define MCPWM_CON_RUN2_Pos                                    16                                                        /*!< MCPWM CON: RUN2 Position            */
+#define MCPWM_CON_RUN2_Msk                                    (0x01UL << MCPWM_CON_RUN2_Pos)                            /*!< MCPWM CON: RUN2 Mask                */
+#define MCPWM_CON_CENTER2_Pos                                 17                                                        /*!< MCPWM CON: CENTER2 Position         */
+#define MCPWM_CON_CENTER2_Msk                                 (0x01UL << MCPWM_CON_CENTER2_Pos)                         /*!< MCPWM CON: CENTER2 Mask             */
+#define MCPWM_CON_POLA2_Pos                                   18                                                        /*!< MCPWM CON: POLA2 Position           */
+#define MCPWM_CON_POLA2_Msk                                   (0x01UL << MCPWM_CON_POLA2_Pos)                           /*!< MCPWM CON: POLA2 Mask               */
+#define MCPWM_CON_DTE2_Pos                                    19                                                        /*!< MCPWM CON: DTE2 Position            */
+#define MCPWM_CON_DTE2_Msk                                    (0x01UL << MCPWM_CON_DTE2_Pos)                            /*!< MCPWM CON: DTE2 Mask                */
+#define MCPWM_CON_DISUP2_Pos                                  20                                                        /*!< MCPWM CON: DISUP2 Position          */
+#define MCPWM_CON_DISUP2_Msk                                  (0x01UL << MCPWM_CON_DISUP2_Pos)                          /*!< MCPWM CON: DISUP2 Mask              */
+#define MCPWM_CON_INVBDC_Pos                                  29                                                        /*!< MCPWM CON: INVBDC Position          */
+#define MCPWM_CON_INVBDC_Msk                                  (0x01UL << MCPWM_CON_INVBDC_Pos)                          /*!< MCPWM CON: INVBDC Mask              */
+#define MCPWM_CON_ACMODE_Pos                                  30                                                        /*!< MCPWM CON: ACMODE Position          */
+#define MCPWM_CON_ACMODE_Msk                                  (0x01UL << MCPWM_CON_ACMODE_Pos)                          /*!< MCPWM CON: ACMODE Mask              */
+#define MCPWM_CON_DCMODE_Pos                                  31                                                        /*!< MCPWM CON: DCMODE Position          */
+#define MCPWM_CON_DCMODE_Msk                                  (0x01UL << MCPWM_CON_DCMODE_Pos)                          /*!< MCPWM CON: DCMODE Mask              */
+
+// --------------------------------------  MCPWM_CON_SET  -----------------------------------------
+#define MCPWM_CON_SET_RUN0_SET_Pos                            0                                                         /*!< MCPWM CON_SET: RUN0_SET Position    */
+#define MCPWM_CON_SET_RUN0_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos)                    /*!< MCPWM CON_SET: RUN0_SET Mask        */
+#define MCPWM_CON_SET_CENTER0_SET_Pos                         1                                                         /*!< MCPWM CON_SET: CENTER0_SET Position */
+#define MCPWM_CON_SET_CENTER0_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos)                 /*!< MCPWM CON_SET: CENTER0_SET Mask     */
+#define MCPWM_CON_SET_POLA0_SET_Pos                           2                                                         /*!< MCPWM CON_SET: POLA0_SET Position   */
+#define MCPWM_CON_SET_POLA0_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos)                   /*!< MCPWM CON_SET: POLA0_SET Mask       */
+#define MCPWM_CON_SET_DTE0_SET_Pos                            3                                                         /*!< MCPWM CON_SET: DTE0_SET Position    */
+#define MCPWM_CON_SET_DTE0_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos)                    /*!< MCPWM CON_SET: DTE0_SET Mask        */
+#define MCPWM_CON_SET_DISUP0_SET_Pos                          4                                                         /*!< MCPWM CON_SET: DISUP0_SET Position  */
+#define MCPWM_CON_SET_DISUP0_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos)                  /*!< MCPWM CON_SET: DISUP0_SET Mask      */
+#define MCPWM_CON_SET_RUN1_SET_Pos                            8                                                         /*!< MCPWM CON_SET: RUN1_SET Position    */
+#define MCPWM_CON_SET_RUN1_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos)                    /*!< MCPWM CON_SET: RUN1_SET Mask        */
+#define MCPWM_CON_SET_CENTER1_SET_Pos                         9                                                         /*!< MCPWM CON_SET: CENTER1_SET Position */
+#define MCPWM_CON_SET_CENTER1_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos)                 /*!< MCPWM CON_SET: CENTER1_SET Mask     */
+#define MCPWM_CON_SET_POLA1_SET_Pos                           10                                                        /*!< MCPWM CON_SET: POLA1_SET Position   */
+#define MCPWM_CON_SET_POLA1_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos)                   /*!< MCPWM CON_SET: POLA1_SET Mask       */
+#define MCPWM_CON_SET_DTE1_SET_Pos                            11                                                        /*!< MCPWM CON_SET: DTE1_SET Position    */
+#define MCPWM_CON_SET_DTE1_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos)                    /*!< MCPWM CON_SET: DTE1_SET Mask        */
+#define MCPWM_CON_SET_DISUP1_SET_Pos                          12                                                        /*!< MCPWM CON_SET: DISUP1_SET Position  */
+#define MCPWM_CON_SET_DISUP1_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos)                  /*!< MCPWM CON_SET: DISUP1_SET Mask      */
+#define MCPWM_CON_SET_RUN2_SET_Pos                            16                                                        /*!< MCPWM CON_SET: RUN2_SET Position    */
+#define MCPWM_CON_SET_RUN2_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos)                    /*!< MCPWM CON_SET: RUN2_SET Mask        */
+#define MCPWM_CON_SET_CENTER2_SET_Pos                         17                                                        /*!< MCPWM CON_SET: CENTER2_SET Position */
+#define MCPWM_CON_SET_CENTER2_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos)                 /*!< MCPWM CON_SET: CENTER2_SET Mask     */
+#define MCPWM_CON_SET_POLA2_SET_Pos                           18                                                        /*!< MCPWM CON_SET: POLA2_SET Position   */
+#define MCPWM_CON_SET_POLA2_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos)                   /*!< MCPWM CON_SET: POLA2_SET Mask       */
+#define MCPWM_CON_SET_DTE2_SET_Pos                            19                                                        /*!< MCPWM CON_SET: DTE2_SET Position    */
+#define MCPWM_CON_SET_DTE2_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos)                    /*!< MCPWM CON_SET: DTE2_SET Mask        */
+#define MCPWM_CON_SET_DISUP2_SET_Pos                          20                                                        /*!< MCPWM CON_SET: DISUP2_SET Position  */
+#define MCPWM_CON_SET_DISUP2_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos)                  /*!< MCPWM CON_SET: DISUP2_SET Mask      */
+#define MCPWM_CON_SET_INVBDC_SET_Pos                          29                                                        /*!< MCPWM CON_SET: INVBDC_SET Position  */
+#define MCPWM_CON_SET_INVBDC_SET_Msk                          (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos)                  /*!< MCPWM CON_SET: INVBDC_SET Mask      */
+#define MCPWM_CON_SET_ACMODE_SET_Pos                          30                                                        /*!< MCPWM CON_SET: ACMODE_SET Position  */
+#define MCPWM_CON_SET_ACMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos)                  /*!< MCPWM CON_SET: ACMODE_SET Mask      */
+#define MCPWM_CON_SET_DCMODE_SET_Pos                          31                                                        /*!< MCPWM CON_SET: DCMODE_SET Position  */
+#define MCPWM_CON_SET_DCMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos)                  /*!< MCPWM CON_SET: DCMODE_SET Mask      */
+
+// --------------------------------------  MCPWM_CON_CLR  -----------------------------------------
+#define MCPWM_CON_CLR_RUN0_CLR_Pos                            0                                                         /*!< MCPWM CON_CLR: RUN0_CLR Position    */
+#define MCPWM_CON_CLR_RUN0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN0_CLR Mask        */
+#define MCPWM_CON_CLR_CENTER0_CLR_Pos                         1                                                         /*!< MCPWM CON_CLR: CENTER0_CLR Position */
+#define MCPWM_CON_CLR_CENTER0_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER0_CLR Mask     */
+#define MCPWM_CON_CLR_POLA0_CLR_Pos                           2                                                         /*!< MCPWM CON_CLR: POLA0_CLR Position   */
+#define MCPWM_CON_CLR_POLA0_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA0_CLR Mask       */
+#define MCPWM_CON_CLR_DTE0_CLR_Pos                            3                                                         /*!< MCPWM CON_CLR: DTE0_CLR Position    */
+#define MCPWM_CON_CLR_DTE0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE0_CLR Mask        */
+#define MCPWM_CON_CLR_DISUP0_CLR_Pos                          4                                                         /*!< MCPWM CON_CLR: DISUP0_CLR Position  */
+#define MCPWM_CON_CLR_DISUP0_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP0_CLR Mask      */
+#define MCPWM_CON_CLR_RUN1_CLR_Pos                            8                                                         /*!< MCPWM CON_CLR: RUN1_CLR Position    */
+#define MCPWM_CON_CLR_RUN1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN1_CLR Mask        */
+#define MCPWM_CON_CLR_CENTER1_CLR_Pos                         9                                                         /*!< MCPWM CON_CLR: CENTER1_CLR Position */
+#define MCPWM_CON_CLR_CENTER1_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER1_CLR Mask     */
+#define MCPWM_CON_CLR_POLA1_CLR_Pos                           10                                                        /*!< MCPWM CON_CLR: POLA1_CLR Position   */
+#define MCPWM_CON_CLR_POLA1_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA1_CLR Mask       */
+#define MCPWM_CON_CLR_DTE1_CLR_Pos                            11                                                        /*!< MCPWM CON_CLR: DTE1_CLR Position    */
+#define MCPWM_CON_CLR_DTE1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE1_CLR Mask        */
+#define MCPWM_CON_CLR_DISUP1_CLR_Pos                          12                                                        /*!< MCPWM CON_CLR: DISUP1_CLR Position  */
+#define MCPWM_CON_CLR_DISUP1_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP1_CLR Mask      */
+#define MCPWM_CON_CLR_RUN2_CLR_Pos                            16                                                        /*!< MCPWM CON_CLR: RUN2_CLR Position    */
+#define MCPWM_CON_CLR_RUN2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN2_CLR Mask        */
+#define MCPWM_CON_CLR_CENTER2_CLR_Pos                         17                                                        /*!< MCPWM CON_CLR: CENTER2_CLR Position */
+#define MCPWM_CON_CLR_CENTER2_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER2_CLR Mask     */
+#define MCPWM_CON_CLR_POLA2_CLR_Pos                           18                                                        /*!< MCPWM CON_CLR: POLA2_CLR Position   */
+#define MCPWM_CON_CLR_POLA2_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA2_CLR Mask       */
+#define MCPWM_CON_CLR_DTE2_CLR_Pos                            19                                                        /*!< MCPWM CON_CLR: DTE2_CLR Position    */
+#define MCPWM_CON_CLR_DTE2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE2_CLR Mask        */
+#define MCPWM_CON_CLR_DISUP2_CLR_Pos                          20                                                        /*!< MCPWM CON_CLR: DISUP2_CLR Position  */
+#define MCPWM_CON_CLR_DISUP2_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP2_CLR Mask      */
+#define MCPWM_CON_CLR_INVBDC_CLR_Pos                          29                                                        /*!< MCPWM CON_CLR: INVBDC_CLR Position  */
+#define MCPWM_CON_CLR_INVBDC_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos)                  /*!< MCPWM CON_CLR: INVBDC_CLR Mask      */
+#define MCPWM_CON_CLR_ACMOD_CLR_Pos                           30                                                        /*!< MCPWM CON_CLR: ACMOD_CLR Position   */
+#define MCPWM_CON_CLR_ACMOD_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos)                   /*!< MCPWM CON_CLR: ACMOD_CLR Mask       */
+#define MCPWM_CON_CLR_DCMODE_CLR_Pos                          31                                                        /*!< MCPWM CON_CLR: DCMODE_CLR Position  */
+#define MCPWM_CON_CLR_DCMODE_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos)                  /*!< MCPWM CON_CLR: DCMODE_CLR Mask      */
+
+// --------------------------------------  MCPWM_CAPCON  ------------------------------------------
+#define MCPWM_CAPCON_CAP0MCI0_RE_Pos                          0                                                         /*!< MCPWM CAPCON: CAP0MCI0_RE Position  */
+#define MCPWM_CAPCON_CAP0MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_RE Mask      */
+#define MCPWM_CAPCON_CAP0MCI0_FE_Pos                          1                                                         /*!< MCPWM CAPCON: CAP0MCI0_FE Position  */
+#define MCPWM_CAPCON_CAP0MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_FE Mask      */
+#define MCPWM_CAPCON_CAP0MCI1_RE_Pos                          2                                                         /*!< MCPWM CAPCON: CAP0MCI1_RE Position  */
+#define MCPWM_CAPCON_CAP0MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_RE Mask      */
+#define MCPWM_CAPCON_CAP0MCI1_FE_Pos                          3                                                         /*!< MCPWM CAPCON: CAP0MCI1_FE Position  */
+#define MCPWM_CAPCON_CAP0MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_FE Mask      */
+#define MCPWM_CAPCON_CAP0MCI2_RE_Pos                          4                                                         /*!< MCPWM CAPCON: CAP0MCI2_RE Position  */
+#define MCPWM_CAPCON_CAP0MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_RE Mask      */
+#define MCPWM_CAPCON_CAP0MCI2_FE_Pos                          5                                                         /*!< MCPWM CAPCON: CAP0MCI2_FE Position  */
+#define MCPWM_CAPCON_CAP0MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_FE Mask      */
+#define MCPWM_CAPCON_CAP1MCI0_RE_Pos                          6                                                         /*!< MCPWM CAPCON: CAP1MCI0_RE Position  */
+#define MCPWM_CAPCON_CAP1MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_RE Mask      */
+#define MCPWM_CAPCON_CAP1MCI0_FE_Pos                          7                                                         /*!< MCPWM CAPCON: CAP1MCI0_FE Position  */
+#define MCPWM_CAPCON_CAP1MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_FE Mask      */
+#define MCPWM_CAPCON_CAP1MCI1_RE_Pos                          8                                                         /*!< MCPWM CAPCON: CAP1MCI1_RE Position  */
+#define MCPWM_CAPCON_CAP1MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_RE Mask      */
+#define MCPWM_CAPCON_CAP1MCI1_FE_Pos                          9                                                         /*!< MCPWM CAPCON: CAP1MCI1_FE Position  */
+#define MCPWM_CAPCON_CAP1MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_FE Mask      */
+#define MCPWM_CAPCON_CAP1MCI2_RE_Pos                          10                                                        /*!< MCPWM CAPCON: CAP1MCI2_RE Position  */
+#define MCPWM_CAPCON_CAP1MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_RE Mask      */
+#define MCPWM_CAPCON_CAP1MCI2_FE_Pos                          11                                                        /*!< MCPWM CAPCON: CAP1MCI2_FE Position  */
+#define MCPWM_CAPCON_CAP1MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_FE Mask      */
+#define MCPWM_CAPCON_CAP2MCI0_RE_Pos                          12                                                        /*!< MCPWM CAPCON: CAP2MCI0_RE Position  */
+#define MCPWM_CAPCON_CAP2MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_RE Mask      */
+#define MCPWM_CAPCON_CAP2MCI0_FE_Pos                          13                                                        /*!< MCPWM CAPCON: CAP2MCI0_FE Position  */
+#define MCPWM_CAPCON_CAP2MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_FE Mask      */
+#define MCPWM_CAPCON_CAP2MCI1_RE_Pos                          14                                                        /*!< MCPWM CAPCON: CAP2MCI1_RE Position  */
+#define MCPWM_CAPCON_CAP2MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_RE Mask      */
+#define MCPWM_CAPCON_CAP2MCI1_FE_Pos                          15                                                        /*!< MCPWM CAPCON: CAP2MCI1_FE Position  */
+#define MCPWM_CAPCON_CAP2MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_FE Mask      */
+#define MCPWM_CAPCON_CAP2MCI2_RE_Pos                          16                                                        /*!< MCPWM CAPCON: CAP2MCI2_RE Position  */
+#define MCPWM_CAPCON_CAP2MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_RE Mask      */
+#define MCPWM_CAPCON_CAP2MCI2_FE_Pos                          17                                                        /*!< MCPWM CAPCON: CAP2MCI2_FE Position  */
+#define MCPWM_CAPCON_CAP2MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_FE Mask      */
+#define MCPWM_CAPCON_RT0_Pos                                  18                                                        /*!< MCPWM CAPCON: RT0 Position          */
+#define MCPWM_CAPCON_RT0_Msk                                  (0x01UL << MCPWM_CAPCON_RT0_Pos)                          /*!< MCPWM CAPCON: RT0 Mask              */
+#define MCPWM_CAPCON_RT1_Pos                                  19                                                        /*!< MCPWM CAPCON: RT1 Position          */
+#define MCPWM_CAPCON_RT1_Msk                                  (0x01UL << MCPWM_CAPCON_RT1_Pos)                          /*!< MCPWM CAPCON: RT1 Mask              */
+#define MCPWM_CAPCON_RT2_Pos                                  20                                                        /*!< MCPWM CAPCON: RT2 Position          */
+#define MCPWM_CAPCON_RT2_Msk                                  (0x01UL << MCPWM_CAPCON_RT2_Pos)                          /*!< MCPWM CAPCON: RT2 Mask              */
+#define MCPWM_CAPCON_HNFCAP0_Pos                              21                                                        /*!< MCPWM CAPCON: HNFCAP0 Position      */
+#define MCPWM_CAPCON_HNFCAP0_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos)                      /*!< MCPWM CAPCON: HNFCAP0 Mask          */
+#define MCPWM_CAPCON_HNFCAP1_Pos                              22                                                        /*!< MCPWM CAPCON: HNFCAP1 Position      */
+#define MCPWM_CAPCON_HNFCAP1_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos)                      /*!< MCPWM CAPCON: HNFCAP1 Mask          */
+#define MCPWM_CAPCON_HNFCAP2_Pos                              23                                                        /*!< MCPWM CAPCON: HNFCAP2 Position      */
+#define MCPWM_CAPCON_HNFCAP2_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos)                      /*!< MCPWM CAPCON: HNFCAP2 Mask          */
+
+// ------------------------------------  MCPWM_CAPCON_SET  ----------------------------------------
+#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos                  0                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos                  1                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos                  2                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos                  3                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos                  4                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos                  5                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos                  6                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos                  7                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos                  8                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos                  9                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos                  10                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos                  11                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos                  12                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos                  13                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos                  14                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos                  15                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos                  16                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos                  17                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_RT0_SET_Pos                          18                                                        /*!< MCPWM CAPCON_SET: RT0_SET Position  */
+#define MCPWM_CAPCON_SET_RT0_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT0_SET Mask      */
+#define MCPWM_CAPCON_SET_RT1_SET_Pos                          19                                                        /*!< MCPWM CAPCON_SET: RT1_SET Position  */
+#define MCPWM_CAPCON_SET_RT1_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT1_SET Mask      */
+#define MCPWM_CAPCON_SET_RT2_SET_Pos                          20                                                        /*!< MCPWM CAPCON_SET: RT2_SET Position  */
+#define MCPWM_CAPCON_SET_RT2_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT2_SET Mask      */
+#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos                      21                                                        /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask  */
+#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos                      22                                                        /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask  */
+#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos                      23                                                        /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask  */
+
+// ------------------------------------  MCPWM_CAPCON_CLR  ----------------------------------------
+#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos                  0                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos                  1                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos                  2                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos                  3                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos                  4                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos                  5                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos                  6                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos                  7                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos                  8                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos                  9                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos                  10                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos                  11                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos                  12                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos                  13                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos                  14                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos                  15                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos                  16                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos                  17                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_RT0_CLR_Pos                          18                                                        /*!< MCPWM CAPCON_CLR: RT0_CLR Position  */
+#define MCPWM_CAPCON_CLR_RT0_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT0_CLR Mask      */
+#define MCPWM_CAPCON_CLR_RT1_CLR_Pos                          19                                                        /*!< MCPWM CAPCON_CLR: RT1_CLR Position  */
+#define MCPWM_CAPCON_CLR_RT1_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT1_CLR Mask      */
+#define MCPWM_CAPCON_CLR_RT2_CLR_Pos                          20                                                        /*!< MCPWM CAPCON_CLR: RT2_CLR Position  */
+#define MCPWM_CAPCON_CLR_RT2_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT2_CLR Mask      */
+#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos                      21                                                        /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask  */
+#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos                      22                                                        /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask  */
+#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos                      23                                                        /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask  */
+
+// ----------------------------------------  MCPWM_TC0  -------------------------------------------
+#define MCPWM_TC0_MCTC_Pos                                    0                                                         /*!< MCPWM TC0: MCTC Position            */
+#define MCPWM_TC0_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC0_MCTC_Pos)                      /*!< MCPWM TC0: MCTC Mask                */
+
+// ----------------------------------------  MCPWM_TC1  -------------------------------------------
+#define MCPWM_TC1_MCTC_Pos                                    0                                                         /*!< MCPWM TC1: MCTC Position            */
+#define MCPWM_TC1_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC1_MCTC_Pos)                      /*!< MCPWM TC1: MCTC Mask                */
+
+// ----------------------------------------  MCPWM_TC2  -------------------------------------------
+#define MCPWM_TC2_MCTC_Pos                                    0                                                         /*!< MCPWM TC2: MCTC Position            */
+#define MCPWM_TC2_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC2_MCTC_Pos)                      /*!< MCPWM TC2: MCTC Mask                */
+
+// ---------------------------------------  MCPWM_LIM0  -------------------------------------------
+#define MCPWM_LIM0_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM0: MCLIM Position          */
+#define MCPWM_LIM0_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos)                    /*!< MCPWM LIM0: MCLIM Mask              */
+
+// ---------------------------------------  MCPWM_LIM1  -------------------------------------------
+#define MCPWM_LIM1_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM1: MCLIM Position          */
+#define MCPWM_LIM1_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos)                    /*!< MCPWM LIM1: MCLIM Mask              */
+
+// ---------------------------------------  MCPWM_LIM2  -------------------------------------------
+#define MCPWM_LIM2_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM2: MCLIM Position          */
+#define MCPWM_LIM2_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos)                    /*!< MCPWM LIM2: MCLIM Mask              */
+
+// ---------------------------------------  MCPWM_MAT0  -------------------------------------------
+#define MCPWM_MAT0_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT0: MCMAT Position          */
+#define MCPWM_MAT0_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos)                    /*!< MCPWM MAT0: MCMAT Mask              */
+
+// ---------------------------------------  MCPWM_MAT1  -------------------------------------------
+#define MCPWM_MAT1_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT1: MCMAT Position          */
+#define MCPWM_MAT1_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos)                    /*!< MCPWM MAT1: MCMAT Mask              */
+
+// ---------------------------------------  MCPWM_MAT2  -------------------------------------------
+#define MCPWM_MAT2_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT2: MCMAT Position          */
+#define MCPWM_MAT2_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos)                    /*!< MCPWM MAT2: MCMAT Mask              */
+
+// ----------------------------------------  MCPWM_DT  --------------------------------------------
+#define MCPWM_DT_DT0_Pos                                      0                                                         /*!< MCPWM DT: DT0 Position              */
+#define MCPWM_DT_DT0_Msk                                      (0x000003ffUL << MCPWM_DT_DT0_Pos)                        /*!< MCPWM DT: DT0 Mask                  */
+#define MCPWM_DT_DT1_Pos                                      10                                                        /*!< MCPWM DT: DT1 Position              */
+#define MCPWM_DT_DT1_Msk                                      (0x000003ffUL << MCPWM_DT_DT1_Pos)                        /*!< MCPWM DT: DT1 Mask                  */
+#define MCPWM_DT_DT2_Pos                                      20                                                        /*!< MCPWM DT: DT2 Position              */
+#define MCPWM_DT_DT2_Msk                                      (0x000003ffUL << MCPWM_DT_DT2_Pos)                        /*!< MCPWM DT: DT2 Mask                  */
+
+// ----------------------------------------  MCPWM_CCP  -------------------------------------------
+#define MCPWM_CCP_CCPA0_Pos                                   0                                                         /*!< MCPWM CCP: CCPA0 Position           */
+#define MCPWM_CCP_CCPA0_Msk                                   (0x01UL << MCPWM_CCP_CCPA0_Pos)                           /*!< MCPWM CCP: CCPA0 Mask               */
+#define MCPWM_CCP_CCPB0_Pos                                   1                                                         /*!< MCPWM CCP: CCPB0 Position           */
+#define MCPWM_CCP_CCPB0_Msk                                   (0x01UL << MCPWM_CCP_CCPB0_Pos)                           /*!< MCPWM CCP: CCPB0 Mask               */
+#define MCPWM_CCP_CCPA1_Pos                                   2                                                         /*!< MCPWM CCP: CCPA1 Position           */
+#define MCPWM_CCP_CCPA1_Msk                                   (0x01UL << MCPWM_CCP_CCPA1_Pos)                           /*!< MCPWM CCP: CCPA1 Mask               */
+#define MCPWM_CCP_CCPB1_Pos                                   3                                                         /*!< MCPWM CCP: CCPB1 Position           */
+#define MCPWM_CCP_CCPB1_Msk                                   (0x01UL << MCPWM_CCP_CCPB1_Pos)                           /*!< MCPWM CCP: CCPB1 Mask               */
+#define MCPWM_CCP_CCPA2_Pos                                   4                                                         /*!< MCPWM CCP: CCPA2 Position           */
+#define MCPWM_CCP_CCPA2_Msk                                   (0x01UL << MCPWM_CCP_CCPA2_Pos)                           /*!< MCPWM CCP: CCPA2 Mask               */
+#define MCPWM_CCP_CCPB2_Pos                                   5                                                         /*!< MCPWM CCP: CCPB2 Position           */
+#define MCPWM_CCP_CCPB2_Msk                                   (0x01UL << MCPWM_CCP_CCPB2_Pos)                           /*!< MCPWM CCP: CCPB2 Mask               */
+
+// ---------------------------------------  MCPWM_CAP0  -------------------------------------------
+#define MCPWM_CAP0_CAP_Pos                                    0                                                         /*!< MCPWM CAP0: CAP Position            */
+#define MCPWM_CAP0_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP0_CAP_Pos)                      /*!< MCPWM CAP0: CAP Mask                */
+
+// ---------------------------------------  MCPWM_CAP1  -------------------------------------------
+#define MCPWM_CAP1_CAP_Pos                                    0                                                         /*!< MCPWM CAP1: CAP Position            */
+#define MCPWM_CAP1_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP1_CAP_Pos)                      /*!< MCPWM CAP1: CAP Mask                */
+
+// ---------------------------------------  MCPWM_CAP2  -------------------------------------------
+#define MCPWM_CAP2_CAP_Pos                                    0                                                         /*!< MCPWM CAP2: CAP Position            */
+#define MCPWM_CAP2_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP2_CAP_Pos)                      /*!< MCPWM CAP2: CAP Mask                */
+
+// ---------------------------------------  MCPWM_INTEN  ------------------------------------------
+#define MCPWM_INTEN_ILIM0_Pos                                 0                                                         /*!< MCPWM INTEN: ILIM0 Position         */
+#define MCPWM_INTEN_ILIM0_Msk                                 (0x01UL << MCPWM_INTEN_ILIM0_Pos)                         /*!< MCPWM INTEN: ILIM0 Mask             */
+#define MCPWM_INTEN_IMAT0_Pos                                 1                                                         /*!< MCPWM INTEN: IMAT0 Position         */
+#define MCPWM_INTEN_IMAT0_Msk                                 (0x01UL << MCPWM_INTEN_IMAT0_Pos)                         /*!< MCPWM INTEN: IMAT0 Mask             */
+#define MCPWM_INTEN_ICAP0_Pos                                 2                                                         /*!< MCPWM INTEN: ICAP0 Position         */
+#define MCPWM_INTEN_ICAP0_Msk                                 (0x01UL << MCPWM_INTEN_ICAP0_Pos)                         /*!< MCPWM INTEN: ICAP0 Mask             */
+#define MCPWM_INTEN_ILIM1_Pos                                 4                                                         /*!< MCPWM INTEN: ILIM1 Position         */
+#define MCPWM_INTEN_ILIM1_Msk                                 (0x01UL << MCPWM_INTEN_ILIM1_Pos)                         /*!< MCPWM INTEN: ILIM1 Mask             */
+#define MCPWM_INTEN_IMAT1_Pos                                 5                                                         /*!< MCPWM INTEN: IMAT1 Position         */
+#define MCPWM_INTEN_IMAT1_Msk                                 (0x01UL << MCPWM_INTEN_IMAT1_Pos)                         /*!< MCPWM INTEN: IMAT1 Mask             */
+#define MCPWM_INTEN_ICAP1_Pos                                 6                                                         /*!< MCPWM INTEN: ICAP1 Position         */
+#define MCPWM_INTEN_ICAP1_Msk                                 (0x01UL << MCPWM_INTEN_ICAP1_Pos)                         /*!< MCPWM INTEN: ICAP1 Mask             */
+#define MCPWM_INTEN_ILIM2_Pos                                 8                                                         /*!< MCPWM INTEN: ILIM2 Position         */
+#define MCPWM_INTEN_ILIM2_Msk                                 (0x01UL << MCPWM_INTEN_ILIM2_Pos)                         /*!< MCPWM INTEN: ILIM2 Mask             */
+#define MCPWM_INTEN_IMAT2_Pos                                 9                                                         /*!< MCPWM INTEN: IMAT2 Position         */
+#define MCPWM_INTEN_IMAT2_Msk                                 (0x01UL << MCPWM_INTEN_IMAT2_Pos)                         /*!< MCPWM INTEN: IMAT2 Mask             */
+#define MCPWM_INTEN_ICAP2_Pos                                 10                                                        /*!< MCPWM INTEN: ICAP2 Position         */
+#define MCPWM_INTEN_ICAP2_Msk                                 (0x01UL << MCPWM_INTEN_ICAP2_Pos)                         /*!< MCPWM INTEN: ICAP2 Mask             */
+#define MCPWM_INTEN_ABORT_Pos                                 15                                                        /*!< MCPWM INTEN: ABORT Position         */
+#define MCPWM_INTEN_ABORT_Msk                                 (0x01UL << MCPWM_INTEN_ABORT_Pos)                         /*!< MCPWM INTEN: ABORT Mask             */
+
+// -------------------------------------  MCPWM_INTEN_SET  ----------------------------------------
+#define MCPWM_INTEN_SET_ILIM0_SET_Pos                         0                                                         /*!< MCPWM INTEN_SET: ILIM0_SET Position */
+#define MCPWM_INTEN_SET_ILIM0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM0_SET Mask     */
+#define MCPWM_INTEN_SET_IMAT0_SET_Pos                         1                                                         /*!< MCPWM INTEN_SET: IMAT0_SET Position */
+#define MCPWM_INTEN_SET_IMAT0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT0_SET Mask     */
+#define MCPWM_INTEN_SET_ICAP0_SET_Pos                         2                                                         /*!< MCPWM INTEN_SET: ICAP0_SET Position */
+#define MCPWM_INTEN_SET_ICAP0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP0_SET Mask     */
+#define MCPWM_INTEN_SET_ILIM1_SET_Pos                         4                                                         /*!< MCPWM INTEN_SET: ILIM1_SET Position */
+#define MCPWM_INTEN_SET_ILIM1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM1_SET Mask     */
+#define MCPWM_INTEN_SET_IMAT1_SET_Pos                         5                                                         /*!< MCPWM INTEN_SET: IMAT1_SET Position */
+#define MCPWM_INTEN_SET_IMAT1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT1_SET Mask     */
+#define MCPWM_INTEN_SET_ICAP1_SET_Pos                         6                                                         /*!< MCPWM INTEN_SET: ICAP1_SET Position */
+#define MCPWM_INTEN_SET_ICAP1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP1_SET Mask     */
+#define MCPWM_INTEN_SET_ILIM2_SET_Pos                         9                                                         /*!< MCPWM INTEN_SET: ILIM2_SET Position */
+#define MCPWM_INTEN_SET_ILIM2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM2_SET Mask     */
+#define MCPWM_INTEN_SET_IMAT2_SET_Pos                         10                                                        /*!< MCPWM INTEN_SET: IMAT2_SET Position */
+#define MCPWM_INTEN_SET_IMAT2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT2_SET Mask     */
+#define MCPWM_INTEN_SET_ICAP2_SET_Pos                         11                                                        /*!< MCPWM INTEN_SET: ICAP2_SET Position */
+#define MCPWM_INTEN_SET_ICAP2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP2_SET Mask     */
+#define MCPWM_INTEN_SET_ABORT_SET_Pos                         15                                                        /*!< MCPWM INTEN_SET: ABORT_SET Position */
+#define MCPWM_INTEN_SET_ABORT_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos)                 /*!< MCPWM INTEN_SET: ABORT_SET Mask     */
+
+// -------------------------------------  MCPWM_INTEN_CLR  ----------------------------------------
+#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos                         0                                                         /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask     */
+#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos                         1                                                         /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask     */
+#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos                         2                                                         /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask     */
+#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos                         4                                                         /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask     */
+#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos                         5                                                         /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask     */
+#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos                         6                                                         /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask     */
+#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos                         8                                                         /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask     */
+#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos                         9                                                         /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask     */
+#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos                         10                                                        /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask     */
+#define MCPWM_INTEN_CLR_ABORT_CLR_Pos                         15                                                        /*!< MCPWM INTEN_CLR: ABORT_CLR Position */
+#define MCPWM_INTEN_CLR_ABORT_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ABORT_CLR Mask     */
+
+// --------------------------------------  MCPWM_CNTCON  ------------------------------------------
+#define MCPWM_CNTCON_TC0MCI0_RE_Pos                           0                                                         /*!< MCPWM CNTCON: TC0MCI0_RE Position   */
+#define MCPWM_CNTCON_TC0MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_RE Mask       */
+#define MCPWM_CNTCON_TC0MCI0_FE_Pos                           1                                                         /*!< MCPWM CNTCON: TC0MCI0_FE Position   */
+#define MCPWM_CNTCON_TC0MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_FE Mask       */
+#define MCPWM_CNTCON_TC0MCI1_RE_Pos                           2                                                         /*!< MCPWM CNTCON: TC0MCI1_RE Position   */
+#define MCPWM_CNTCON_TC0MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_RE Mask       */
+#define MCPWM_CNTCON_TC0MCI1_FE_Pos                           3                                                         /*!< MCPWM CNTCON: TC0MCI1_FE Position   */
+#define MCPWM_CNTCON_TC0MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_FE Mask       */
+#define MCPWM_CNTCON_TC0MCI2_RE_Pos                           4                                                         /*!< MCPWM CNTCON: TC0MCI2_RE Position   */
+#define MCPWM_CNTCON_TC0MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_RE Mask       */
+#define MCPWM_CNTCON_TC0MCI2_FE_Pos                           5                                                         /*!< MCPWM CNTCON: TC0MCI2_FE Position   */
+#define MCPWM_CNTCON_TC0MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_FE Mask       */
+#define MCPWM_CNTCON_TC1MCI0_RE_Pos                           6                                                         /*!< MCPWM CNTCON: TC1MCI0_RE Position   */
+#define MCPWM_CNTCON_TC1MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_RE Mask       */
+#define MCPWM_CNTCON_TC1MCI0_FE_Pos                           7                                                         /*!< MCPWM CNTCON: TC1MCI0_FE Position   */
+#define MCPWM_CNTCON_TC1MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_FE Mask       */
+#define MCPWM_CNTCON_TC1MCI1_RE_Pos                           8                                                         /*!< MCPWM CNTCON: TC1MCI1_RE Position   */
+#define MCPWM_CNTCON_TC1MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_RE Mask       */
+#define MCPWM_CNTCON_TC1MCI1_FE_Pos                           9                                                         /*!< MCPWM CNTCON: TC1MCI1_FE Position   */
+#define MCPWM_CNTCON_TC1MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_FE Mask       */
+#define MCPWM_CNTCON_TC1MCI2_RE_Pos                           10                                                        /*!< MCPWM CNTCON: TC1MCI2_RE Position   */
+#define MCPWM_CNTCON_TC1MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_RE Mask       */
+#define MCPWM_CNTCON_TC1MCI2_FE_Pos                           11                                                        /*!< MCPWM CNTCON: TC1MCI2_FE Position   */
+#define MCPWM_CNTCON_TC1MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_FE Mask       */
+#define MCPWM_CNTCON_TC2MCI0_RE_Pos                           12                                                        /*!< MCPWM CNTCON: TC2MCI0_RE Position   */
+#define MCPWM_CNTCON_TC2MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_RE Mask       */
+#define MCPWM_CNTCON_TC2MCI0_FE_Pos                           13                                                        /*!< MCPWM CNTCON: TC2MCI0_FE Position   */
+#define MCPWM_CNTCON_TC2MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_FE Mask       */
+#define MCPWM_CNTCON_TC2MCI1_RE_Pos                           14                                                        /*!< MCPWM CNTCON: TC2MCI1_RE Position   */
+#define MCPWM_CNTCON_TC2MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_RE Mask       */
+#define MCPWM_CNTCON_TC2MCI1_FE_Pos                           15                                                        /*!< MCPWM CNTCON: TC2MCI1_FE Position   */
+#define MCPWM_CNTCON_TC2MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_FE Mask       */
+#define MCPWM_CNTCON_TC2MCI2_RE_Pos                           16                                                        /*!< MCPWM CNTCON: TC2MCI2_RE Position   */
+#define MCPWM_CNTCON_TC2MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_RE Mask       */
+#define MCPWM_CNTCON_TC2MCI2_FE_Pos                           17                                                        /*!< MCPWM CNTCON: TC2MCI2_FE Position   */
+#define MCPWM_CNTCON_TC2MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_FE Mask       */
+#define MCPWM_CNTCON_CNTR0_Pos                                29                                                        /*!< MCPWM CNTCON: CNTR0 Position        */
+#define MCPWM_CNTCON_CNTR0_Msk                                (0x01UL << MCPWM_CNTCON_CNTR0_Pos)                        /*!< MCPWM CNTCON: CNTR0 Mask            */
+#define MCPWM_CNTCON_CNTR1_Pos                                30                                                        /*!< MCPWM CNTCON: CNTR1 Position        */
+#define MCPWM_CNTCON_CNTR1_Msk                                (0x01UL << MCPWM_CNTCON_CNTR1_Pos)                        /*!< MCPWM CNTCON: CNTR1 Mask            */
+#define MCPWM_CNTCON_CNTR2_Pos                                31                                                        /*!< MCPWM CNTCON: CNTR2 Position        */
+#define MCPWM_CNTCON_CNTR2_Msk                                (0x01UL << MCPWM_CNTCON_CNTR2_Pos)                        /*!< MCPWM CNTCON: CNTR2 Mask            */
+
+// ------------------------------------  MCPWM_CNTCON_SET  ----------------------------------------
+#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos                   0                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos                   1                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos                   2                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos                   3                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos                   4                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos                   5                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos                   6                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos                   7                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos                   8                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos                   9                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos                   10                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos                   11                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos                   12                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos                   13                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos                   14                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos                   15                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos                   16                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos                   17                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_CNTR0_SET_Pos                        29                                                        /*!< MCPWM CNTCON_SET: CNTR0_SET Position */
+#define MCPWM_CNTCON_SET_CNTR0_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR0_SET Mask    */
+#define MCPWM_CNTCON_SET_CNTR1_SET_Pos                        30                                                        /*!< MCPWM CNTCON_SET: CNTR1_SET Position */
+#define MCPWM_CNTCON_SET_CNTR1_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR1_SET Mask    */
+#define MCPWM_CNTCON_SET_CNTR2_SET_Pos                        31                                                        /*!< MCPWM CNTCON_SET: CNTR2_SET Position */
+#define MCPWM_CNTCON_SET_CNTR2_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR2_SET Mask    */
+
+// ------------------------------------  MCPWM_CNTCON_CLR  ----------------------------------------
+#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos                   0                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos                   1                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos                   2                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos                   3                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos                       4                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */
+#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk                       (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos)               /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask   */
+#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos                   5                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos                   6                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos                   7                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos                   8                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos                   9                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos                   10                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos                   11                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos                   12                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos                   13                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos                   14                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos                   15                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos                   16                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos                   17                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos                        29                                                        /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask    */
+#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos                        30                                                        /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask    */
+#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos                        31                                                        /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask    */
+
+// ---------------------------------------  MCPWM_INTF  -------------------------------------------
+#define MCPWM_INTF_ILIM0_F_Pos                                0                                                         /*!< MCPWM INTF: ILIM0_F Position        */
+#define MCPWM_INTF_ILIM0_F_Msk                                (0x01UL << MCPWM_INTF_ILIM0_F_Pos)                        /*!< MCPWM INTF: ILIM0_F Mask            */
+#define MCPWM_INTF_IMAT0_F_Pos                                1                                                         /*!< MCPWM INTF: IMAT0_F Position        */
+#define MCPWM_INTF_IMAT0_F_Msk                                (0x01UL << MCPWM_INTF_IMAT0_F_Pos)                        /*!< MCPWM INTF: IMAT0_F Mask            */
+#define MCPWM_INTF_ICAP0_F_Pos                                2                                                         /*!< MCPWM INTF: ICAP0_F Position        */
+#define MCPWM_INTF_ICAP0_F_Msk                                (0x01UL << MCPWM_INTF_ICAP0_F_Pos)                        /*!< MCPWM INTF: ICAP0_F Mask            */
+#define MCPWM_INTF_ILIM1_F_Pos                                4                                                         /*!< MCPWM INTF: ILIM1_F Position        */
+#define MCPWM_INTF_ILIM1_F_Msk                                (0x01UL << MCPWM_INTF_ILIM1_F_Pos)                        /*!< MCPWM INTF: ILIM1_F Mask            */
+#define MCPWM_INTF_IMAT1_F_Pos                                5                                                         /*!< MCPWM INTF: IMAT1_F Position        */
+#define MCPWM_INTF_IMAT1_F_Msk                                (0x01UL << MCPWM_INTF_IMAT1_F_Pos)                        /*!< MCPWM INTF: IMAT1_F Mask            */
+#define MCPWM_INTF_ICAP1_F_Pos                                6                                                         /*!< MCPWM INTF: ICAP1_F Position        */
+#define MCPWM_INTF_ICAP1_F_Msk                                (0x01UL << MCPWM_INTF_ICAP1_F_Pos)                        /*!< MCPWM INTF: ICAP1_F Mask            */
+#define MCPWM_INTF_ILIM2_F_Pos                                8                                                         /*!< MCPWM INTF: ILIM2_F Position        */
+#define MCPWM_INTF_ILIM2_F_Msk                                (0x01UL << MCPWM_INTF_ILIM2_F_Pos)                        /*!< MCPWM INTF: ILIM2_F Mask            */
+#define MCPWM_INTF_IMAT2_F_Pos                                9                                                         /*!< MCPWM INTF: IMAT2_F Position        */
+#define MCPWM_INTF_IMAT2_F_Msk                                (0x01UL << MCPWM_INTF_IMAT2_F_Pos)                        /*!< MCPWM INTF: IMAT2_F Mask            */
+#define MCPWM_INTF_ICAP2_F_Pos                                10                                                        /*!< MCPWM INTF: ICAP2_F Position        */
+#define MCPWM_INTF_ICAP2_F_Msk                                (0x01UL << MCPWM_INTF_ICAP2_F_Pos)                        /*!< MCPWM INTF: ICAP2_F Mask            */
+#define MCPWM_INTF_ABORT_F_Pos                                15                                                        /*!< MCPWM INTF: ABORT_F Position        */
+#define MCPWM_INTF_ABORT_F_Msk                                (0x01UL << MCPWM_INTF_ABORT_F_Pos)                        /*!< MCPWM INTF: ABORT_F Mask            */
+
+// -------------------------------------  MCPWM_INTF_SET  -----------------------------------------
+#define MCPWM_INTF_SET_ILIM0_F_SET_Pos                        0                                                         /*!< MCPWM INTF_SET: ILIM0_F_SET Position */
+#define MCPWM_INTF_SET_ILIM0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM0_F_SET Mask    */
+#define MCPWM_INTF_SET_IMAT0_F_SET_Pos                        1                                                         /*!< MCPWM INTF_SET: IMAT0_F_SET Position */
+#define MCPWM_INTF_SET_IMAT0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT0_F_SET Mask    */
+#define MCPWM_INTF_SET_ICAP0_F_SET_Pos                        2                                                         /*!< MCPWM INTF_SET: ICAP0_F_SET Position */
+#define MCPWM_INTF_SET_ICAP0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP0_F_SET Mask    */
+#define MCPWM_INTF_SET_ILIM1_F_SET_Pos                        4                                                         /*!< MCPWM INTF_SET: ILIM1_F_SET Position */
+#define MCPWM_INTF_SET_ILIM1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM1_F_SET Mask    */
+#define MCPWM_INTF_SET_IMAT1_F_SET_Pos                        5                                                         /*!< MCPWM INTF_SET: IMAT1_F_SET Position */
+#define MCPWM_INTF_SET_IMAT1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT1_F_SET Mask    */
+#define MCPWM_INTF_SET_ICAP1_F_SET_Pos                        6                                                         /*!< MCPWM INTF_SET: ICAP1_F_SET Position */
+#define MCPWM_INTF_SET_ICAP1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP1_F_SET Mask    */
+#define MCPWM_INTF_SET_ILIM2_F_SET_Pos                        8                                                         /*!< MCPWM INTF_SET: ILIM2_F_SET Position */
+#define MCPWM_INTF_SET_ILIM2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM2_F_SET Mask    */
+#define MCPWM_INTF_SET_IMAT2_F_SET_Pos                        9                                                         /*!< MCPWM INTF_SET: IMAT2_F_SET Position */
+#define MCPWM_INTF_SET_IMAT2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT2_F_SET Mask    */
+#define MCPWM_INTF_SET_ICAP2_F_SET_Pos                        10                                                        /*!< MCPWM INTF_SET: ICAP2_F_SET Position */
+#define MCPWM_INTF_SET_ICAP2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP2_F_SET Mask    */
+#define MCPWM_INTF_SET_ABORT_F_SET_Pos                        15                                                        /*!< MCPWM INTF_SET: ABORT_F_SET Position */
+#define MCPWM_INTF_SET_ABORT_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos)                /*!< MCPWM INTF_SET: ABORT_F_SET Mask    */
+
+// -------------------------------------  MCPWM_INTF_CLR  -----------------------------------------
+#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos                        0                                                         /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask    */
+#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos                        1                                                         /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos                        2                                                         /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos                        4                                                         /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask    */
+#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos                        5                                                         /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos                        6                                                         /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos                        8                                                         /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask    */
+#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos                        9                                                         /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos                        10                                                        /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask    */
+#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos                        15                                                        /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */
+#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask    */
+
+// --------------------------------------  MCPWM_CAP_CLR  -----------------------------------------
+#define MCPWM_CAP_CLR_CAP_CLR0_Pos                            0                                                         /*!< MCPWM CAP_CLR: CAP_CLR0 Position    */
+#define MCPWM_CAP_CLR_CAP_CLR0_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR0 Mask        */
+#define MCPWM_CAP_CLR_CAP_CLR1_Pos                            1                                                         /*!< MCPWM CAP_CLR: CAP_CLR1 Position    */
+#define MCPWM_CAP_CLR_CAP_CLR1_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR1 Mask        */
+#define MCPWM_CAP_CLR_CAP_CLR2_Pos                            2                                                         /*!< MCPWM CAP_CLR: CAP_CLR2 Position    */
+#define MCPWM_CAP_CLR_CAP_CLR2_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR2 Mask        */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2C0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  I2C0_CONSET  ------------------------------------------
+#define I2C0_CONSET_AA_Pos                                    2                                                         /*!< I2C0 CONSET: AA Position            */
+#define I2C0_CONSET_AA_Msk                                    (0x01UL << I2C0_CONSET_AA_Pos)                            /*!< I2C0 CONSET: AA Mask                */
+#define I2C0_CONSET_SI_Pos                                    3                                                         /*!< I2C0 CONSET: SI Position            */
+#define I2C0_CONSET_SI_Msk                                    (0x01UL << I2C0_CONSET_SI_Pos)                            /*!< I2C0 CONSET: SI Mask                */
+#define I2C0_CONSET_STO_Pos                                   4                                                         /*!< I2C0 CONSET: STO Position           */
+#define I2C0_CONSET_STO_Msk                                   (0x01UL << I2C0_CONSET_STO_Pos)                           /*!< I2C0 CONSET: STO Mask               */
+#define I2C0_CONSET_STA_Pos                                   5                                                         /*!< I2C0 CONSET: STA Position           */
+#define I2C0_CONSET_STA_Msk                                   (0x01UL << I2C0_CONSET_STA_Pos)                           /*!< I2C0 CONSET: STA Mask               */
+#define I2C0_CONSET_I2EN_Pos                                  6                                                         /*!< I2C0 CONSET: I2EN Position          */
+#define I2C0_CONSET_I2EN_Msk                                  (0x01UL << I2C0_CONSET_I2EN_Pos)                          /*!< I2C0 CONSET: I2EN Mask              */
+
+// ----------------------------------------  I2C0_STAT  -------------------------------------------
+#define I2C0_STAT_Status_Pos                                  3                                                         /*!< I2C0 STAT: Status Position          */
+#define I2C0_STAT_Status_Msk                                  (0x1fUL << I2C0_STAT_Status_Pos)                          /*!< I2C0 STAT: Status Mask              */
+
+// ----------------------------------------  I2C0_DAT  --------------------------------------------
+#define I2C0_DAT_Data_Pos                                     0                                                         /*!< I2C0 DAT: Data Position             */
+#define I2C0_DAT_Data_Msk                                     (0x000000ffUL << I2C0_DAT_Data_Pos)                       /*!< I2C0 DAT: Data Mask                 */
+
+// ----------------------------------------  I2C0_ADR0  -------------------------------------------
+#define I2C0_ADR0_GC_Pos                                      0                                                         /*!< I2C0 ADR0: GC Position              */
+#define I2C0_ADR0_GC_Msk                                      (0x01UL << I2C0_ADR0_GC_Pos)                              /*!< I2C0 ADR0: GC Mask                  */
+#define I2C0_ADR0_Address_Pos                                 1                                                         /*!< I2C0 ADR0: Address Position         */
+#define I2C0_ADR0_Address_Msk                                 (0x7fUL << I2C0_ADR0_Address_Pos)                         /*!< I2C0 ADR0: Address Mask             */
+
+// ----------------------------------------  I2C0_SCLH  -------------------------------------------
+#define I2C0_SCLH_SCLH_Pos                                    0                                                         /*!< I2C0 SCLH: SCLH Position            */
+#define I2C0_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C0_SCLH_SCLH_Pos)                      /*!< I2C0 SCLH: SCLH Mask                */
+
+// ----------------------------------------  I2C0_SCLL  -------------------------------------------
+#define I2C0_SCLL_SCLL_Pos                                    0                                                         /*!< I2C0 SCLL: SCLL Position            */
+#define I2C0_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C0_SCLL_SCLL_Pos)                      /*!< I2C0 SCLL: SCLL Mask                */
+
+// ---------------------------------------  I2C0_CONCLR  ------------------------------------------
+#define I2C0_CONCLR_AAC_Pos                                   2                                                         /*!< I2C0 CONCLR: AAC Position           */
+#define I2C0_CONCLR_AAC_Msk                                   (0x01UL << I2C0_CONCLR_AAC_Pos)                           /*!< I2C0 CONCLR: AAC Mask               */
+#define I2C0_CONCLR_SIC_Pos                                   3                                                         /*!< I2C0 CONCLR: SIC Position           */
+#define I2C0_CONCLR_SIC_Msk                                   (0x01UL << I2C0_CONCLR_SIC_Pos)                           /*!< I2C0 CONCLR: SIC Mask               */
+#define I2C0_CONCLR_STAC_Pos                                  5                                                         /*!< I2C0 CONCLR: STAC Position          */
+#define I2C0_CONCLR_STAC_Msk                                  (0x01UL << I2C0_CONCLR_STAC_Pos)                          /*!< I2C0 CONCLR: STAC Mask              */
+#define I2C0_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C0 CONCLR: I2ENC Position         */
+#define I2C0_CONCLR_I2ENC_Msk                                 (0x01UL << I2C0_CONCLR_I2ENC_Pos)                         /*!< I2C0 CONCLR: I2ENC Mask             */
+
+// ---------------------------------------  I2C0_MMCTRL  ------------------------------------------
+#define I2C0_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C0 MMCTRL: MM_ENA Position        */
+#define I2C0_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C0_MMCTRL_MM_ENA_Pos)                        /*!< I2C0 MMCTRL: MM_ENA Mask            */
+#define I2C0_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C0 MMCTRL: ENA_SCL Position       */
+#define I2C0_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos)                       /*!< I2C0 MMCTRL: ENA_SCL Mask           */
+#define I2C0_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C0 MMCTRL: MATCH_ALL Position     */
+#define I2C0_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C0 MMCTRL: MATCH_ALL Mask         */
+
+// ----------------------------------------  I2C0_ADR1  -------------------------------------------
+#define I2C0_ADR1_GC_Pos                                      0                                                         /*!< I2C0 ADR1: GC Position              */
+#define I2C0_ADR1_GC_Msk                                      (0x01UL << I2C0_ADR1_GC_Pos)                              /*!< I2C0 ADR1: GC Mask                  */
+#define I2C0_ADR1_Address_Pos                                 1                                                         /*!< I2C0 ADR1: Address Position         */
+#define I2C0_ADR1_Address_Msk                                 (0x7fUL << I2C0_ADR1_Address_Pos)                         /*!< I2C0 ADR1: Address Mask             */
+
+// ----------------------------------------  I2C0_ADR2  -------------------------------------------
+#define I2C0_ADR2_GC_Pos                                      0                                                         /*!< I2C0 ADR2: GC Position              */
+#define I2C0_ADR2_GC_Msk                                      (0x01UL << I2C0_ADR2_GC_Pos)                              /*!< I2C0 ADR2: GC Mask                  */
+#define I2C0_ADR2_Address_Pos                                 1                                                         /*!< I2C0 ADR2: Address Position         */
+#define I2C0_ADR2_Address_Msk                                 (0x7fUL << I2C0_ADR2_Address_Pos)                         /*!< I2C0 ADR2: Address Mask             */
+
+// ----------------------------------------  I2C0_ADR3  -------------------------------------------
+#define I2C0_ADR3_GC_Pos                                      0                                                         /*!< I2C0 ADR3: GC Position              */
+#define I2C0_ADR3_GC_Msk                                      (0x01UL << I2C0_ADR3_GC_Pos)                              /*!< I2C0 ADR3: GC Mask                  */
+#define I2C0_ADR3_Address_Pos                                 1                                                         /*!< I2C0 ADR3: Address Position         */
+#define I2C0_ADR3_Address_Msk                                 (0x7fUL << I2C0_ADR3_Address_Pos)                         /*!< I2C0 ADR3: Address Mask             */
+
+// ------------------------------------  I2C0_DATA_BUFFER  ----------------------------------------
+#define I2C0_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C0 DATA_BUFFER: Data Position     */
+#define I2C0_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos)               /*!< I2C0 DATA_BUFFER: Data Mask         */
+
+// ---------------------------------------  I2C0_MASK0  -------------------------------------------
+#define I2C0_MASK0_MASK_Pos                                   1                                                         /*!< I2C0 MASK0: MASK Position           */
+#define I2C0_MASK0_MASK_Msk                                   (0x7fUL << I2C0_MASK0_MASK_Pos)                           /*!< I2C0 MASK0: MASK Mask               */
+
+// ---------------------------------------  I2C0_MASK1  -------------------------------------------
+#define I2C0_MASK1_MASK_Pos                                   1                                                         /*!< I2C0 MASK1: MASK Position           */
+#define I2C0_MASK1_MASK_Msk                                   (0x7fUL << I2C0_MASK1_MASK_Pos)                           /*!< I2C0 MASK1: MASK Mask               */
+
+// ---------------------------------------  I2C0_MASK2  -------------------------------------------
+#define I2C0_MASK2_MASK_Pos                                   1                                                         /*!< I2C0 MASK2: MASK Position           */
+#define I2C0_MASK2_MASK_Msk                                   (0x7fUL << I2C0_MASK2_MASK_Pos)                           /*!< I2C0 MASK2: MASK Mask               */
+
+// ---------------------------------------  I2C0_MASK3  -------------------------------------------
+#define I2C0_MASK3_MASK_Pos                                   1                                                         /*!< I2C0 MASK3: MASK Position           */
+#define I2C0_MASK3_MASK_Msk                                   (0x7fUL << I2C0_MASK3_MASK_Pos)                           /*!< I2C0 MASK3: MASK Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2C1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  I2C1_CONSET  ------------------------------------------
+#define I2C1_CONSET_AA_Pos                                    2                                                         /*!< I2C1 CONSET: AA Position            */
+#define I2C1_CONSET_AA_Msk                                    (0x01UL << I2C1_CONSET_AA_Pos)                            /*!< I2C1 CONSET: AA Mask                */
+#define I2C1_CONSET_SI_Pos                                    3                                                         /*!< I2C1 CONSET: SI Position            */
+#define I2C1_CONSET_SI_Msk                                    (0x01UL << I2C1_CONSET_SI_Pos)                            /*!< I2C1 CONSET: SI Mask                */
+#define I2C1_CONSET_STO_Pos                                   4                                                         /*!< I2C1 CONSET: STO Position           */
+#define I2C1_CONSET_STO_Msk                                   (0x01UL << I2C1_CONSET_STO_Pos)                           /*!< I2C1 CONSET: STO Mask               */
+#define I2C1_CONSET_STA_Pos                                   5                                                         /*!< I2C1 CONSET: STA Position           */
+#define I2C1_CONSET_STA_Msk                                   (0x01UL << I2C1_CONSET_STA_Pos)                           /*!< I2C1 CONSET: STA Mask               */
+#define I2C1_CONSET_I2EN_Pos                                  6                                                         /*!< I2C1 CONSET: I2EN Position          */
+#define I2C1_CONSET_I2EN_Msk                                  (0x01UL << I2C1_CONSET_I2EN_Pos)                          /*!< I2C1 CONSET: I2EN Mask              */
+
+// ----------------------------------------  I2C1_STAT  -------------------------------------------
+#define I2C1_STAT_Status_Pos                                  3                                                         /*!< I2C1 STAT: Status Position          */
+#define I2C1_STAT_Status_Msk                                  (0x1fUL << I2C1_STAT_Status_Pos)                          /*!< I2C1 STAT: Status Mask              */
+
+// ----------------------------------------  I2C1_DAT  --------------------------------------------
+#define I2C1_DAT_Data_Pos                                     0                                                         /*!< I2C1 DAT: Data Position             */
+#define I2C1_DAT_Data_Msk                                     (0x000000ffUL << I2C1_DAT_Data_Pos)                       /*!< I2C1 DAT: Data Mask                 */
+
+// ----------------------------------------  I2C1_ADR0  -------------------------------------------
+#define I2C1_ADR0_GC_Pos                                      0                                                         /*!< I2C1 ADR0: GC Position              */
+#define I2C1_ADR0_GC_Msk                                      (0x01UL << I2C1_ADR0_GC_Pos)                              /*!< I2C1 ADR0: GC Mask                  */
+#define I2C1_ADR0_Address_Pos                                 1                                                         /*!< I2C1 ADR0: Address Position         */
+#define I2C1_ADR0_Address_Msk                                 (0x7fUL << I2C1_ADR0_Address_Pos)                         /*!< I2C1 ADR0: Address Mask             */
+
+// ----------------------------------------  I2C1_SCLH  -------------------------------------------
+#define I2C1_SCLH_SCLH_Pos                                    0                                                         /*!< I2C1 SCLH: SCLH Position            */
+#define I2C1_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C1_SCLH_SCLH_Pos)                      /*!< I2C1 SCLH: SCLH Mask                */
+
+// ----------------------------------------  I2C1_SCLL  -------------------------------------------
+#define I2C1_SCLL_SCLL_Pos                                    0                                                         /*!< I2C1 SCLL: SCLL Position            */
+#define I2C1_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C1_SCLL_SCLL_Pos)                      /*!< I2C1 SCLL: SCLL Mask                */
+
+// ---------------------------------------  I2C1_CONCLR  ------------------------------------------
+#define I2C1_CONCLR_AAC_Pos                                   2                                                         /*!< I2C1 CONCLR: AAC Position           */
+#define I2C1_CONCLR_AAC_Msk                                   (0x01UL << I2C1_CONCLR_AAC_Pos)                           /*!< I2C1 CONCLR: AAC Mask               */
+#define I2C1_CONCLR_SIC_Pos                                   3                                                         /*!< I2C1 CONCLR: SIC Position           */
+#define I2C1_CONCLR_SIC_Msk                                   (0x01UL << I2C1_CONCLR_SIC_Pos)                           /*!< I2C1 CONCLR: SIC Mask               */
+#define I2C1_CONCLR_STAC_Pos                                  5                                                         /*!< I2C1 CONCLR: STAC Position          */
+#define I2C1_CONCLR_STAC_Msk                                  (0x01UL << I2C1_CONCLR_STAC_Pos)                          /*!< I2C1 CONCLR: STAC Mask              */
+#define I2C1_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C1 CONCLR: I2ENC Position         */
+#define I2C1_CONCLR_I2ENC_Msk                                 (0x01UL << I2C1_CONCLR_I2ENC_Pos)                         /*!< I2C1 CONCLR: I2ENC Mask             */
+
+// ---------------------------------------  I2C1_MMCTRL  ------------------------------------------
+#define I2C1_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C1 MMCTRL: MM_ENA Position        */
+#define I2C1_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C1_MMCTRL_MM_ENA_Pos)                        /*!< I2C1 MMCTRL: MM_ENA Mask            */
+#define I2C1_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C1 MMCTRL: ENA_SCL Position       */
+#define I2C1_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos)                       /*!< I2C1 MMCTRL: ENA_SCL Mask           */
+#define I2C1_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C1 MMCTRL: MATCH_ALL Position     */
+#define I2C1_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C1 MMCTRL: MATCH_ALL Mask         */
+
+// ----------------------------------------  I2C1_ADR1  -------------------------------------------
+#define I2C1_ADR1_GC_Pos                                      0                                                         /*!< I2C1 ADR1: GC Position              */
+#define I2C1_ADR1_GC_Msk                                      (0x01UL << I2C1_ADR1_GC_Pos)                              /*!< I2C1 ADR1: GC Mask                  */
+#define I2C1_ADR1_Address_Pos                                 1                                                         /*!< I2C1 ADR1: Address Position         */
+#define I2C1_ADR1_Address_Msk                                 (0x7fUL << I2C1_ADR1_Address_Pos)                         /*!< I2C1 ADR1: Address Mask             */
+
+// ----------------------------------------  I2C1_ADR2  -------------------------------------------
+#define I2C1_ADR2_GC_Pos                                      0                                                         /*!< I2C1 ADR2: GC Position              */
+#define I2C1_ADR2_GC_Msk                                      (0x01UL << I2C1_ADR2_GC_Pos)                              /*!< I2C1 ADR2: GC Mask                  */
+#define I2C1_ADR2_Address_Pos                                 1                                                         /*!< I2C1 ADR2: Address Position         */
+#define I2C1_ADR2_Address_Msk                                 (0x7fUL << I2C1_ADR2_Address_Pos)                         /*!< I2C1 ADR2: Address Mask             */
+
+// ----------------------------------------  I2C1_ADR3  -------------------------------------------
+#define I2C1_ADR3_GC_Pos                                      0                                                         /*!< I2C1 ADR3: GC Position              */
+#define I2C1_ADR3_GC_Msk                                      (0x01UL << I2C1_ADR3_GC_Pos)                              /*!< I2C1 ADR3: GC Mask                  */
+#define I2C1_ADR3_Address_Pos                                 1                                                         /*!< I2C1 ADR3: Address Position         */
+#define I2C1_ADR3_Address_Msk                                 (0x7fUL << I2C1_ADR3_Address_Pos)                         /*!< I2C1 ADR3: Address Mask             */
+
+// ------------------------------------  I2C1_DATA_BUFFER  ----------------------------------------
+#define I2C1_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C1 DATA_BUFFER: Data Position     */
+#define I2C1_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos)               /*!< I2C1 DATA_BUFFER: Data Mask         */
+
+// ---------------------------------------  I2C1_MASK0  -------------------------------------------
+#define I2C1_MASK0_MASK_Pos                                   1                                                         /*!< I2C1 MASK0: MASK Position           */
+#define I2C1_MASK0_MASK_Msk                                   (0x7fUL << I2C1_MASK0_MASK_Pos)                           /*!< I2C1 MASK0: MASK Mask               */
+
+// ---------------------------------------  I2C1_MASK1  -------------------------------------------
+#define I2C1_MASK1_MASK_Pos                                   1                                                         /*!< I2C1 MASK1: MASK Position           */
+#define I2C1_MASK1_MASK_Msk                                   (0x7fUL << I2C1_MASK1_MASK_Pos)                           /*!< I2C1 MASK1: MASK Mask               */
+
+// ---------------------------------------  I2C1_MASK2  -------------------------------------------
+#define I2C1_MASK2_MASK_Pos                                   1                                                         /*!< I2C1 MASK2: MASK Position           */
+#define I2C1_MASK2_MASK_Msk                                   (0x7fUL << I2C1_MASK2_MASK_Pos)                           /*!< I2C1 MASK2: MASK Mask               */
+
+// ---------------------------------------  I2C1_MASK3  -------------------------------------------
+#define I2C1_MASK3_MASK_Pos                                   1                                                         /*!< I2C1 MASK3: MASK Position           */
+#define I2C1_MASK3_MASK_Msk                                   (0x7fUL << I2C1_MASK3_MASK_Pos)                           /*!< I2C1 MASK3: MASK Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2S0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  I2S0_DAO  --------------------------------------------
+#define I2S0_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAO: WORDWIDTH Position        */
+#define I2S0_DAO_WORDWIDTH_Msk                                (0x03UL << I2S0_DAO_WORDWIDTH_Pos)                        /*!< I2S0 DAO: WORDWIDTH Mask            */
+#define I2S0_DAO_MONO_Pos                                     2                                                         /*!< I2S0 DAO: MONO Position             */
+#define I2S0_DAO_MONO_Msk                                     (0x01UL << I2S0_DAO_MONO_Pos)                             /*!< I2S0 DAO: MONO Mask                 */
+#define I2S0_DAO_STOP_Pos                                     3                                                         /*!< I2S0 DAO: STOP Position             */
+#define I2S0_DAO_STOP_Msk                                     (0x01UL << I2S0_DAO_STOP_Pos)                             /*!< I2S0 DAO: STOP Mask                 */
+#define I2S0_DAO_RESET_Pos                                    4                                                         /*!< I2S0 DAO: RESET Position            */
+#define I2S0_DAO_RESET_Msk                                    (0x01UL << I2S0_DAO_RESET_Pos)                            /*!< I2S0 DAO: RESET Mask                */
+#define I2S0_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAO: WS_SEL Position           */
+#define I2S0_DAO_WS_SEL_Msk                                   (0x01UL << I2S0_DAO_WS_SEL_Pos)                           /*!< I2S0 DAO: WS_SEL Mask               */
+#define I2S0_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAO: WS_HALFPERIOD Position    */
+#define I2S0_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos)              /*!< I2S0 DAO: WS_HALFPERIOD Mask        */
+#define I2S0_DAO_MUTE_Pos                                     15                                                        /*!< I2S0 DAO: MUTE Position             */
+#define I2S0_DAO_MUTE_Msk                                     (0x01UL << I2S0_DAO_MUTE_Pos)                             /*!< I2S0 DAO: MUTE Mask                 */
+
+// ----------------------------------------  I2S0_DAI  --------------------------------------------
+#define I2S0_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAI: WORDWIDTH Position        */
+#define I2S0_DAI_WORDWIDTH_Msk                                (0x03UL << I2S0_DAI_WORDWIDTH_Pos)                        /*!< I2S0 DAI: WORDWIDTH Mask            */
+#define I2S0_DAI_MONO_Pos                                     2                                                         /*!< I2S0 DAI: MONO Position             */
+#define I2S0_DAI_MONO_Msk                                     (0x01UL << I2S0_DAI_MONO_Pos)                             /*!< I2S0 DAI: MONO Mask                 */
+#define I2S0_DAI_STOP_Pos                                     3                                                         /*!< I2S0 DAI: STOP Position             */
+#define I2S0_DAI_STOP_Msk                                     (0x01UL << I2S0_DAI_STOP_Pos)                             /*!< I2S0 DAI: STOP Mask                 */
+#define I2S0_DAI_RESET_Pos                                    4                                                         /*!< I2S0 DAI: RESET Position            */
+#define I2S0_DAI_RESET_Msk                                    (0x01UL << I2S0_DAI_RESET_Pos)                            /*!< I2S0 DAI: RESET Mask                */
+#define I2S0_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAI: WS_SEL Position           */
+#define I2S0_DAI_WS_SEL_Msk                                   (0x01UL << I2S0_DAI_WS_SEL_Pos)                           /*!< I2S0 DAI: WS_SEL Mask               */
+#define I2S0_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAI: WS_HALFPERIOD Position    */
+#define I2S0_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos)              /*!< I2S0 DAI: WS_HALFPERIOD Mask        */
+
+// ---------------------------------------  I2S0_TXFIFO  ------------------------------------------
+#define I2S0_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S0 TXFIFO: I2STXFIFO Position     */
+#define I2S0_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos)               /*!< I2S0 TXFIFO: I2STXFIFO Mask         */
+
+// ---------------------------------------  I2S0_RXFIFO  ------------------------------------------
+#define I2S0_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S0 RXFIFO: I2SRXFIFO Position     */
+#define I2S0_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S0 RXFIFO: I2SRXFIFO Mask         */
+
+// ---------------------------------------  I2S0_STATE  -------------------------------------------
+#define I2S0_STATE_IRQ_Pos                                    0                                                         /*!< I2S0 STATE: IRQ Position            */
+#define I2S0_STATE_IRQ_Msk                                    (0x01UL << I2S0_STATE_IRQ_Pos)                            /*!< I2S0 STATE: IRQ Mask                */
+#define I2S0_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S0 STATE: DMAREQ1 Position        */
+#define I2S0_STATE_DMAREQ1_Msk                                (0x01UL << I2S0_STATE_DMAREQ1_Pos)                        /*!< I2S0 STATE: DMAREQ1 Mask            */
+#define I2S0_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S0 STATE: DMAREQ2 Position        */
+#define I2S0_STATE_DMAREQ2_Msk                                (0x01UL << I2S0_STATE_DMAREQ2_Pos)                        /*!< I2S0 STATE: DMAREQ2 Mask            */
+#define I2S0_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S0 STATE: RX_LEVEL Position       */
+#define I2S0_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_RX_LEVEL_Pos)                       /*!< I2S0 STATE: RX_LEVEL Mask           */
+#define I2S0_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S0 STATE: TX_LEVEL Position       */
+#define I2S0_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_TX_LEVEL_Pos)                       /*!< I2S0 STATE: TX_LEVEL Mask           */
+
+// ----------------------------------------  I2S0_DMA1  -------------------------------------------
+#define I2S0_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S0 DMA1: RX_DMA1_ENABLE Position  */
+#define I2S0_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask      */
+#define I2S0_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S0 DMA1: TX_DMA1_ENABLE Position  */
+#define I2S0_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask      */
+#define I2S0_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position   */
+#define I2S0_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask       */
+#define I2S0_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position   */
+#define I2S0_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask       */
+
+// ----------------------------------------  I2S0_DMA2  -------------------------------------------
+#define I2S0_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S0 DMA2: RX_DMA2_ENABLE Position  */
+#define I2S0_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask      */
+#define I2S0_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S0 DMA2: TX_DMA2_ENABLE Position  */
+#define I2S0_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask      */
+#define I2S0_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position   */
+#define I2S0_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask       */
+#define I2S0_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position   */
+#define I2S0_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask       */
+
+// ----------------------------------------  I2S0_IRQ  --------------------------------------------
+#define I2S0_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S0 IRQ: RX_IRQ_ENABLE Position    */
+#define I2S0_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask        */
+#define I2S0_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S0 IRQ: TX_IRQ_ENABLE Position    */
+#define I2S0_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask        */
+#define I2S0_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S0 IRQ: RX_DEPTH_IRQ Position     */
+#define I2S0_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask         */
+#define I2S0_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S0 IRQ: TX_DEPTH_IRQ Position     */
+#define I2S0_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask         */
+
+// ---------------------------------------  I2S0_TXRATE  ------------------------------------------
+#define I2S0_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 TXRATE: Y_DIVIDER Position     */
+#define I2S0_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos)               /*!< I2S0 TXRATE: Y_DIVIDER Mask         */
+#define I2S0_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 TXRATE: X_DIVIDER Position     */
+#define I2S0_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos)               /*!< I2S0 TXRATE: X_DIVIDER Mask         */
+
+// ---------------------------------------  I2S0_RXRATE  ------------------------------------------
+#define I2S0_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 RXRATE: Y_DIVIDER Position     */
+#define I2S0_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos)               /*!< I2S0 RXRATE: Y_DIVIDER Mask         */
+#define I2S0_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 RXRATE: X_DIVIDER Position     */
+#define I2S0_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos)               /*!< I2S0 RXRATE: X_DIVIDER Mask         */
+
+// -------------------------------------  I2S0_TXBITRATE  -----------------------------------------
+#define I2S0_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S0 TXBITRATE: TX_BITRATE Position */
+#define I2S0_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S0 TXBITRATE: TX_BITRATE Mask     */
+
+// -------------------------------------  I2S0_RXBITRATE  -----------------------------------------
+#define I2S0_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S0 RXBITRATE: RX_BITRATE Position */
+#define I2S0_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S0 RXBITRATE: RX_BITRATE Mask     */
+
+// ---------------------------------------  I2S0_TXMODE  ------------------------------------------
+#define I2S0_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S0 TXMODE: TXCLKSEL Position      */
+#define I2S0_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos)                      /*!< I2S0 TXMODE: TXCLKSEL Mask          */
+#define I2S0_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S0 TXMODE: TX4PIN Position        */
+#define I2S0_TXMODE_TX4PIN_Msk                                (0x01UL << I2S0_TXMODE_TX4PIN_Pos)                        /*!< I2S0 TXMODE: TX4PIN Mask            */
+#define I2S0_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S0 TXMODE: TXMCENA Position       */
+#define I2S0_TXMODE_TXMCENA_Msk                               (0x01UL << I2S0_TXMODE_TXMCENA_Pos)                       /*!< I2S0 TXMODE: TXMCENA Mask           */
+
+// ---------------------------------------  I2S0_RXMODE  ------------------------------------------
+#define I2S0_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S0 RXMODE: RXCLKSEL Position      */
+#define I2S0_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos)                      /*!< I2S0 RXMODE: RXCLKSEL Mask          */
+#define I2S0_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S0 RXMODE: RX4PIN Position        */
+#define I2S0_RXMODE_RX4PIN_Msk                                (0x01UL << I2S0_RXMODE_RX4PIN_Pos)                        /*!< I2S0 RXMODE: RX4PIN Mask            */
+#define I2S0_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S0 RXMODE: RXMCENA Position       */
+#define I2S0_RXMODE_RXMCENA_Msk                               (0x01UL << I2S0_RXMODE_RXMCENA_Pos)                       /*!< I2S0 RXMODE: RXMCENA Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 I2S1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------  I2S1_DAO  --------------------------------------------
+#define I2S1_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAO: WORDWIDTH Position        */
+#define I2S1_DAO_WORDWIDTH_Msk                                (0x03UL << I2S1_DAO_WORDWIDTH_Pos)                        /*!< I2S1 DAO: WORDWIDTH Mask            */
+#define I2S1_DAO_MONO_Pos                                     2                                                         /*!< I2S1 DAO: MONO Position             */
+#define I2S1_DAO_MONO_Msk                                     (0x01UL << I2S1_DAO_MONO_Pos)                             /*!< I2S1 DAO: MONO Mask                 */
+#define I2S1_DAO_STOP_Pos                                     3                                                         /*!< I2S1 DAO: STOP Position             */
+#define I2S1_DAO_STOP_Msk                                     (0x01UL << I2S1_DAO_STOP_Pos)                             /*!< I2S1 DAO: STOP Mask                 */
+#define I2S1_DAO_RESET_Pos                                    4                                                         /*!< I2S1 DAO: RESET Position            */
+#define I2S1_DAO_RESET_Msk                                    (0x01UL << I2S1_DAO_RESET_Pos)                            /*!< I2S1 DAO: RESET Mask                */
+#define I2S1_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAO: WS_SEL Position           */
+#define I2S1_DAO_WS_SEL_Msk                                   (0x01UL << I2S1_DAO_WS_SEL_Pos)                           /*!< I2S1 DAO: WS_SEL Mask               */
+#define I2S1_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAO: WS_HALFPERIOD Position    */
+#define I2S1_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos)              /*!< I2S1 DAO: WS_HALFPERIOD Mask        */
+#define I2S1_DAO_MUTE_Pos                                     15                                                        /*!< I2S1 DAO: MUTE Position             */
+#define I2S1_DAO_MUTE_Msk                                     (0x01UL << I2S1_DAO_MUTE_Pos)                             /*!< I2S1 DAO: MUTE Mask                 */
+
+// ----------------------------------------  I2S1_DAI  --------------------------------------------
+#define I2S1_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAI: WORDWIDTH Position        */
+#define I2S1_DAI_WORDWIDTH_Msk                                (0x03UL << I2S1_DAI_WORDWIDTH_Pos)                        /*!< I2S1 DAI: WORDWIDTH Mask            */
+#define I2S1_DAI_MONO_Pos                                     2                                                         /*!< I2S1 DAI: MONO Position             */
+#define I2S1_DAI_MONO_Msk                                     (0x01UL << I2S1_DAI_MONO_Pos)                             /*!< I2S1 DAI: MONO Mask                 */
+#define I2S1_DAI_STOP_Pos                                     3                                                         /*!< I2S1 DAI: STOP Position             */
+#define I2S1_DAI_STOP_Msk                                     (0x01UL << I2S1_DAI_STOP_Pos)                             /*!< I2S1 DAI: STOP Mask                 */
+#define I2S1_DAI_RESET_Pos                                    4                                                         /*!< I2S1 DAI: RESET Position            */
+#define I2S1_DAI_RESET_Msk                                    (0x01UL << I2S1_DAI_RESET_Pos)                            /*!< I2S1 DAI: RESET Mask                */
+#define I2S1_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAI: WS_SEL Position           */
+#define I2S1_DAI_WS_SEL_Msk                                   (0x01UL << I2S1_DAI_WS_SEL_Pos)                           /*!< I2S1 DAI: WS_SEL Mask               */
+#define I2S1_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAI: WS_HALFPERIOD Position    */
+#define I2S1_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos)              /*!< I2S1 DAI: WS_HALFPERIOD Mask        */
+
+// ---------------------------------------  I2S1_TXFIFO  ------------------------------------------
+#define I2S1_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S1 TXFIFO: I2STXFIFO Position     */
+#define I2S1_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos)               /*!< I2S1 TXFIFO: I2STXFIFO Mask         */
+
+// ---------------------------------------  I2S1_RXFIFO  ------------------------------------------
+#define I2S1_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S1 RXFIFO: I2SRXFIFO Position     */
+#define I2S1_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S1 RXFIFO: I2SRXFIFO Mask         */
+
+// ---------------------------------------  I2S1_STATE  -------------------------------------------
+#define I2S1_STATE_IRQ_Pos                                    0                                                         /*!< I2S1 STATE: IRQ Position            */
+#define I2S1_STATE_IRQ_Msk                                    (0x01UL << I2S1_STATE_IRQ_Pos)                            /*!< I2S1 STATE: IRQ Mask                */
+#define I2S1_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S1 STATE: DMAREQ1 Position        */
+#define I2S1_STATE_DMAREQ1_Msk                                (0x01UL << I2S1_STATE_DMAREQ1_Pos)                        /*!< I2S1 STATE: DMAREQ1 Mask            */
+#define I2S1_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S1 STATE: DMAREQ2 Position        */
+#define I2S1_STATE_DMAREQ2_Msk                                (0x01UL << I2S1_STATE_DMAREQ2_Pos)                        /*!< I2S1 STATE: DMAREQ2 Mask            */
+#define I2S1_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S1 STATE: RX_LEVEL Position       */
+#define I2S1_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_RX_LEVEL_Pos)                       /*!< I2S1 STATE: RX_LEVEL Mask           */
+#define I2S1_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S1 STATE: TX_LEVEL Position       */
+#define I2S1_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_TX_LEVEL_Pos)                       /*!< I2S1 STATE: TX_LEVEL Mask           */
+
+// ----------------------------------------  I2S1_DMA1  -------------------------------------------
+#define I2S1_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S1 DMA1: RX_DMA1_ENABLE Position  */
+#define I2S1_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask      */
+#define I2S1_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S1 DMA1: TX_DMA1_ENABLE Position  */
+#define I2S1_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask      */
+#define I2S1_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position   */
+#define I2S1_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask       */
+#define I2S1_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position   */
+#define I2S1_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask       */
+
+// ----------------------------------------  I2S1_DMA2  -------------------------------------------
+#define I2S1_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S1 DMA2: RX_DMA2_ENABLE Position  */
+#define I2S1_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask      */
+#define I2S1_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S1 DMA2: TX_DMA2_ENABLE Position  */
+#define I2S1_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask      */
+#define I2S1_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position   */
+#define I2S1_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask       */
+#define I2S1_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position   */
+#define I2S1_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask       */
+
+// ----------------------------------------  I2S1_IRQ  --------------------------------------------
+#define I2S1_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S1 IRQ: RX_IRQ_ENABLE Position    */
+#define I2S1_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask        */
+#define I2S1_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S1 IRQ: TX_IRQ_ENABLE Position    */
+#define I2S1_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask        */
+#define I2S1_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S1 IRQ: RX_DEPTH_IRQ Position     */
+#define I2S1_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask         */
+#define I2S1_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S1 IRQ: TX_DEPTH_IRQ Position     */
+#define I2S1_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask         */
+
+// ---------------------------------------  I2S1_TXRATE  ------------------------------------------
+#define I2S1_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 TXRATE: Y_DIVIDER Position     */
+#define I2S1_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos)               /*!< I2S1 TXRATE: Y_DIVIDER Mask         */
+#define I2S1_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 TXRATE: X_DIVIDER Position     */
+#define I2S1_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos)               /*!< I2S1 TXRATE: X_DIVIDER Mask         */
+
+// ---------------------------------------  I2S1_RXRATE  ------------------------------------------
+#define I2S1_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 RXRATE: Y_DIVIDER Position     */
+#define I2S1_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos)               /*!< I2S1 RXRATE: Y_DIVIDER Mask         */
+#define I2S1_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 RXRATE: X_DIVIDER Position     */
+#define I2S1_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos)               /*!< I2S1 RXRATE: X_DIVIDER Mask         */
+
+// -------------------------------------  I2S1_TXBITRATE  -----------------------------------------
+#define I2S1_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S1 TXBITRATE: TX_BITRATE Position */
+#define I2S1_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S1 TXBITRATE: TX_BITRATE Mask     */
+
+// -------------------------------------  I2S1_RXBITRATE  -----------------------------------------
+#define I2S1_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S1 RXBITRATE: RX_BITRATE Position */
+#define I2S1_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S1 RXBITRATE: RX_BITRATE Mask     */
+
+// ---------------------------------------  I2S1_TXMODE  ------------------------------------------
+#define I2S1_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S1 TXMODE: TXCLKSEL Position      */
+#define I2S1_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos)                      /*!< I2S1 TXMODE: TXCLKSEL Mask          */
+#define I2S1_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S1 TXMODE: TX4PIN Position        */
+#define I2S1_TXMODE_TX4PIN_Msk                                (0x01UL << I2S1_TXMODE_TX4PIN_Pos)                        /*!< I2S1 TXMODE: TX4PIN Mask            */
+#define I2S1_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S1 TXMODE: TXMCENA Position       */
+#define I2S1_TXMODE_TXMCENA_Msk                               (0x01UL << I2S1_TXMODE_TXMCENA_Pos)                       /*!< I2S1 TXMODE: TXMCENA Mask           */
+
+// ---------------------------------------  I2S1_RXMODE  ------------------------------------------
+#define I2S1_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S1 RXMODE: RXCLKSEL Position      */
+#define I2S1_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos)                      /*!< I2S1 RXMODE: RXCLKSEL Mask          */
+#define I2S1_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S1 RXMODE: RX4PIN Position        */
+#define I2S1_RXMODE_RX4PIN_Msk                                (0x01UL << I2S1_RXMODE_RX4PIN_Pos)                        /*!< I2S1 RXMODE: RX4PIN Mask            */
+#define I2S1_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S1 RXMODE: RXMCENA Position       */
+#define I2S1_RXMODE_RXMCENA_Msk                               (0x01UL << I2S1_RXMODE_RXMCENA_Pos)                       /*!< I2S1 RXMODE: RXMCENA Mask           */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                C_CAN1 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  C_CAN1_CNTL  ------------------------------------------
+#define C_CAN1_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN1 CNTL: INIT Position          */
+#define C_CAN1_CNTL_INIT_Msk                                  (0x01UL << C_CAN1_CNTL_INIT_Pos)                          /*!< C_CAN1 CNTL: INIT Mask              */
+#define C_CAN1_CNTL_IE_Pos                                    1                                                         /*!< C_CAN1 CNTL: IE Position            */
+#define C_CAN1_CNTL_IE_Msk                                    (0x01UL << C_CAN1_CNTL_IE_Pos)                            /*!< C_CAN1 CNTL: IE Mask                */
+#define C_CAN1_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN1 CNTL: SIE Position           */
+#define C_CAN1_CNTL_SIE_Msk                                   (0x01UL << C_CAN1_CNTL_SIE_Pos)                           /*!< C_CAN1 CNTL: SIE Mask               */
+#define C_CAN1_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN1 CNTL: EIE Position           */
+#define C_CAN1_CNTL_EIE_Msk                                   (0x01UL << C_CAN1_CNTL_EIE_Pos)                           /*!< C_CAN1 CNTL: EIE Mask               */
+#define C_CAN1_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN1 CNTL: DAR Position           */
+#define C_CAN1_CNTL_DAR_Msk                                   (0x01UL << C_CAN1_CNTL_DAR_Pos)                           /*!< C_CAN1 CNTL: DAR Mask               */
+#define C_CAN1_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN1 CNTL: CCE Position           */
+#define C_CAN1_CNTL_CCE_Msk                                   (0x01UL << C_CAN1_CNTL_CCE_Pos)                           /*!< C_CAN1 CNTL: CCE Mask               */
+#define C_CAN1_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN1 CNTL: TEST Position          */
+#define C_CAN1_CNTL_TEST_Msk                                  (0x01UL << C_CAN1_CNTL_TEST_Pos)                          /*!< C_CAN1 CNTL: TEST Mask              */
+
+// ---------------------------------------  C_CAN1_STAT  ------------------------------------------
+#define C_CAN1_STAT_LEC_Pos                                   0                                                         /*!< C_CAN1 STAT: LEC Position           */
+#define C_CAN1_STAT_LEC_Msk                                   (0x07UL << C_CAN1_STAT_LEC_Pos)                           /*!< C_CAN1 STAT: LEC Mask               */
+#define C_CAN1_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN1 STAT: TXOK Position          */
+#define C_CAN1_STAT_TXOK_Msk                                  (0x01UL << C_CAN1_STAT_TXOK_Pos)                          /*!< C_CAN1 STAT: TXOK Mask              */
+#define C_CAN1_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN1 STAT: RXOK Position          */
+#define C_CAN1_STAT_RXOK_Msk                                  (0x01UL << C_CAN1_STAT_RXOK_Pos)                          /*!< C_CAN1 STAT: RXOK Mask              */
+#define C_CAN1_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN1 STAT: EPASS Position         */
+#define C_CAN1_STAT_EPASS_Msk                                 (0x01UL << C_CAN1_STAT_EPASS_Pos)                         /*!< C_CAN1 STAT: EPASS Mask             */
+#define C_CAN1_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN1 STAT: EWARN Position         */
+#define C_CAN1_STAT_EWARN_Msk                                 (0x01UL << C_CAN1_STAT_EWARN_Pos)                         /*!< C_CAN1 STAT: EWARN Mask             */
+#define C_CAN1_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN1 STAT: BOFF Position          */
+#define C_CAN1_STAT_BOFF_Msk                                  (0x01UL << C_CAN1_STAT_BOFF_Pos)                          /*!< C_CAN1 STAT: BOFF Mask              */
+
+// ----------------------------------------  C_CAN1_EC  -------------------------------------------
+#define C_CAN1_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN1 EC: TEC_7_0 Position         */
+#define C_CAN1_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos)                   /*!< C_CAN1 EC: TEC_7_0 Mask             */
+#define C_CAN1_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN1 EC: REC_6_0 Position         */
+#define C_CAN1_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN1_EC_REC_6_0_Pos)                         /*!< C_CAN1 EC: REC_6_0 Mask             */
+#define C_CAN1_EC_RP_Pos                                      15                                                        /*!< C_CAN1 EC: RP Position              */
+#define C_CAN1_EC_RP_Msk                                      (0x01UL << C_CAN1_EC_RP_Pos)                              /*!< C_CAN1 EC: RP Mask                  */
+
+// ----------------------------------------  C_CAN1_BT  -------------------------------------------
+#define C_CAN1_BT_BRP_Pos                                     0                                                         /*!< C_CAN1 BT: BRP Position             */
+#define C_CAN1_BT_BRP_Msk                                     (0x3fUL << C_CAN1_BT_BRP_Pos)                             /*!< C_CAN1 BT: BRP Mask                 */
+#define C_CAN1_BT_SJW_Pos                                     6                                                         /*!< C_CAN1 BT: SJW Position             */
+#define C_CAN1_BT_SJW_Msk                                     (0x03UL << C_CAN1_BT_SJW_Pos)                             /*!< C_CAN1 BT: SJW Mask                 */
+#define C_CAN1_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN1 BT: TSEG1 Position           */
+#define C_CAN1_BT_TSEG1_Msk                                   (0x0fUL << C_CAN1_BT_TSEG1_Pos)                           /*!< C_CAN1 BT: TSEG1 Mask               */
+#define C_CAN1_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN1 BT: TSEG2 Position           */
+#define C_CAN1_BT_TSEG2_Msk                                   (0x07UL << C_CAN1_BT_TSEG2_Pos)                           /*!< C_CAN1 BT: TSEG2 Mask               */
+
+// ---------------------------------------  C_CAN1_INT  -------------------------------------------
+#define C_CAN1_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN1 INT: INTID15_0 Position      */
+#define C_CAN1_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos)                /*!< C_CAN1 INT: INTID15_0 Mask          */
+
+// ---------------------------------------  C_CAN1_TEST  ------------------------------------------
+#define C_CAN1_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN1 TEST: BASIC Position         */
+#define C_CAN1_TEST_BASIC_Msk                                 (0x01UL << C_CAN1_TEST_BASIC_Pos)                         /*!< C_CAN1 TEST: BASIC Mask             */
+#define C_CAN1_TEST_SILENT_Pos                                3                                                         /*!< C_CAN1 TEST: SILENT Position        */
+#define C_CAN1_TEST_SILENT_Msk                                (0x01UL << C_CAN1_TEST_SILENT_Pos)                        /*!< C_CAN1 TEST: SILENT Mask            */
+#define C_CAN1_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN1 TEST: LBACK Position         */
+#define C_CAN1_TEST_LBACK_Msk                                 (0x01UL << C_CAN1_TEST_LBACK_Pos)                         /*!< C_CAN1 TEST: LBACK Mask             */
+#define C_CAN1_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN1 TEST: TX1_0 Position         */
+#define C_CAN1_TEST_TX1_0_Msk                                 (0x03UL << C_CAN1_TEST_TX1_0_Pos)                         /*!< C_CAN1 TEST: TX1_0 Mask             */
+#define C_CAN1_TEST_RX_Pos                                    7                                                         /*!< C_CAN1 TEST: RX Position            */
+#define C_CAN1_TEST_RX_Msk                                    (0x01UL << C_CAN1_TEST_RX_Pos)                            /*!< C_CAN1 TEST: RX Mask                */
+
+// ---------------------------------------  C_CAN1_BRPE  ------------------------------------------
+#define C_CAN1_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN1 BRPE: BRPE Position          */
+#define C_CAN1_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN1_BRPE_BRPE_Pos)                          /*!< C_CAN1 BRPE: BRPE Mask              */
+
+// ------------------------------------  C_CAN1_IF1_CMDREQ  ---------------------------------------
+#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */
+#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask     */
+#define C_CAN1_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF1_CMDREQ: BUSY Position    */
+#define C_CAN1_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF1_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN1_IF1_CMDMSK_W  --------------------------------------
+#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */
+#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask    */
+#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */
+#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask    */
+#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */
+#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask    */
+#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */
+#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position  */
+#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask      */
+#define C_CAN1_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_W: ARB Position   */
+#define C_CAN1_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask       */
+#define C_CAN1_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_W: MASK Position  */
+#define C_CAN1_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask      */
+#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */
+#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask     */
+
+// -----------------------------------  C_CAN1_IF1_CMDMSK_R  --------------------------------------
+#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */
+#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask    */
+#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */
+#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask    */
+#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */
+#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */
+#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position  */
+#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask      */
+#define C_CAN1_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_R: ARB Position   */
+#define C_CAN1_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask       */
+#define C_CAN1_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_R: MASK Position  */
+#define C_CAN1_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask      */
+#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */
+#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask     */
+
+// -------------------------------------  C_CAN1_IF1_MSK1  ----------------------------------------
+#define C_CAN1_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF1_MSK1: MSK15_0 Position   */
+#define C_CAN1_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN1_IF1_MSK2  ----------------------------------------
+#define C_CAN1_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF1_MSK2: MSK28_16 Position  */
+#define C_CAN1_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask      */
+#define C_CAN1_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF1_MSK2: MDIR Position      */
+#define C_CAN1_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF1_MSK2: MDIR Mask          */
+#define C_CAN1_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF1_MSK2: MXTD Position      */
+#define C_CAN1_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF1_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN1_IF1_ARB1  ----------------------------------------
+#define C_CAN1_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF1_ARB1: ID15_0 Position    */
+#define C_CAN1_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF1_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN1_IF1_ARB2  ----------------------------------------
+#define C_CAN1_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF1_ARB2: ID28_16 Position   */
+#define C_CAN1_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF1_ARB2: ID28_16 Mask       */
+#define C_CAN1_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF1_ARB2: DIR Position       */
+#define C_CAN1_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos)                       /*!< C_CAN1 IF1_ARB2: DIR Mask           */
+#define C_CAN1_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF1_ARB2: XTD Position       */
+#define C_CAN1_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos)                       /*!< C_CAN1 IF1_ARB2: XTD Mask           */
+#define C_CAN1_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF1_ARB2: MSGVAL Position    */
+#define C_CAN1_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF1_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN1_IF1_MCTRL  ----------------------------------------
+#define C_CAN1_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position   */
+#define C_CAN1_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask       */
+#define C_CAN1_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF1_MCTRL: EOB Position      */
+#define C_CAN1_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF1_MCTRL: EOB Mask          */
+#define C_CAN1_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF1_MCTRL: TXRQST Position   */
+#define C_CAN1_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF1_MCTRL: TXRQST Mask       */
+#define C_CAN1_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF1_MCTRL: RMTEN Position    */
+#define C_CAN1_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF1_MCTRL: RMTEN Mask        */
+#define C_CAN1_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF1_MCTRL: RXIE Position     */
+#define C_CAN1_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: RXIE Mask         */
+#define C_CAN1_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF1_MCTRL: TXIE Position     */
+#define C_CAN1_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: TXIE Mask         */
+#define C_CAN1_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF1_MCTRL: UMASK Position    */
+#define C_CAN1_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF1_MCTRL: UMASK Mask        */
+#define C_CAN1_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF1_MCTRL: INTPND Position   */
+#define C_CAN1_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF1_MCTRL: INTPND Mask       */
+#define C_CAN1_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF1_MCTRL: MSGLST Position   */
+#define C_CAN1_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF1_MCTRL: MSGLST Mask       */
+#define C_CAN1_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF1_MCTRL: NEWDAT Position   */
+#define C_CAN1_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN1_IF1_DA1  -----------------------------------------
+#define C_CAN1_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF1_DA1: DATA0 Position      */
+#define C_CAN1_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos)                /*!< C_CAN1 IF1_DA1: DATA0 Mask          */
+#define C_CAN1_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF1_DA1: DATA1 Position      */
+#define C_CAN1_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos)                /*!< C_CAN1 IF1_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN1_IF1_DA2  -----------------------------------------
+#define C_CAN1_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF1_DA2: DATA2 Position      */
+#define C_CAN1_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos)                /*!< C_CAN1 IF1_DA2: DATA2 Mask          */
+#define C_CAN1_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF1_DA2: DATA3 Position      */
+#define C_CAN1_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos)                /*!< C_CAN1 IF1_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN1_IF1_DB1  -----------------------------------------
+#define C_CAN1_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF1_DB1: DATA4 Position      */
+#define C_CAN1_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos)                /*!< C_CAN1 IF1_DB1: DATA4 Mask          */
+#define C_CAN1_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF1_DB1: DATA5 Position      */
+#define C_CAN1_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos)                /*!< C_CAN1 IF1_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN1_IF1_DB2  -----------------------------------------
+#define C_CAN1_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF1_DB2: DATA6 Position      */
+#define C_CAN1_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos)                /*!< C_CAN1 IF1_DB2: DATA6 Mask          */
+#define C_CAN1_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF1_DB2: DATA7 Position      */
+#define C_CAN1_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos)                /*!< C_CAN1 IF1_DB2: DATA7 Mask          */
+
+// ------------------------------------  C_CAN1_IF2_CMDREQ  ---------------------------------------
+#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */
+#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask     */
+#define C_CAN1_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF2_CMDREQ: BUSY Position    */
+#define C_CAN1_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF2_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN1_IF2_CMDMSK_W  --------------------------------------
+#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */
+#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask    */
+#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */
+#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask    */
+#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */
+#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask    */
+#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */
+#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position  */
+#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask      */
+#define C_CAN1_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_W: ARB Position   */
+#define C_CAN1_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask       */
+#define C_CAN1_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_W: MASK Position  */
+#define C_CAN1_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask      */
+#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */
+#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask     */
+
+// -----------------------------------  C_CAN1_IF2_CMDMSK_R  --------------------------------------
+#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */
+#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask    */
+#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */
+#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask    */
+#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */
+#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */
+#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position  */
+#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask      */
+#define C_CAN1_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_R: ARB Position   */
+#define C_CAN1_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask       */
+#define C_CAN1_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_R: MASK Position  */
+#define C_CAN1_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask      */
+#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */
+#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask     */
+
+// -------------------------------------  C_CAN1_IF2_MSK1  ----------------------------------------
+#define C_CAN1_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF2_MSK1: MSK15_0 Position   */
+#define C_CAN1_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN1_IF2_MSK2  ----------------------------------------
+#define C_CAN1_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF2_MSK2: MSK28_16 Position  */
+#define C_CAN1_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask      */
+#define C_CAN1_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF2_MSK2: MDIR Position      */
+#define C_CAN1_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF2_MSK2: MDIR Mask          */
+#define C_CAN1_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF2_MSK2: MXTD Position      */
+#define C_CAN1_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF2_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN1_IF2_ARB1  ----------------------------------------
+#define C_CAN1_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF2_ARB1: ID15_0 Position    */
+#define C_CAN1_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF2_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN1_IF2_ARB2  ----------------------------------------
+#define C_CAN1_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF2_ARB2: ID28_16 Position   */
+#define C_CAN1_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF2_ARB2: ID28_16 Mask       */
+#define C_CAN1_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF2_ARB2: DIR Position       */
+#define C_CAN1_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos)                       /*!< C_CAN1 IF2_ARB2: DIR Mask           */
+#define C_CAN1_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF2_ARB2: XTD Position       */
+#define C_CAN1_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos)                       /*!< C_CAN1 IF2_ARB2: XTD Mask           */
+#define C_CAN1_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF2_ARB2: MSGVAL Position    */
+#define C_CAN1_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF2_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN1_IF2_MCTRL  ----------------------------------------
+#define C_CAN1_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position   */
+#define C_CAN1_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask       */
+#define C_CAN1_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF2_MCTRL: EOB Position      */
+#define C_CAN1_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF2_MCTRL: EOB Mask          */
+#define C_CAN1_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF2_MCTRL: TXRQST Position   */
+#define C_CAN1_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF2_MCTRL: TXRQST Mask       */
+#define C_CAN1_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF2_MCTRL: RMTEN Position    */
+#define C_CAN1_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF2_MCTRL: RMTEN Mask        */
+#define C_CAN1_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF2_MCTRL: RXIE Position     */
+#define C_CAN1_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: RXIE Mask         */
+#define C_CAN1_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF2_MCTRL: TXIE Position     */
+#define C_CAN1_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: TXIE Mask         */
+#define C_CAN1_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF2_MCTRL: UMASK Position    */
+#define C_CAN1_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF2_MCTRL: UMASK Mask        */
+#define C_CAN1_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF2_MCTRL: INTPND Position   */
+#define C_CAN1_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF2_MCTRL: INTPND Mask       */
+#define C_CAN1_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF2_MCTRL: MSGLST Position   */
+#define C_CAN1_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF2_MCTRL: MSGLST Mask       */
+#define C_CAN1_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF2_MCTRL: NEWDAT Position   */
+#define C_CAN1_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN1_IF2_DA1  -----------------------------------------
+#define C_CAN1_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF2_DA1: DATA0 Position      */
+#define C_CAN1_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos)                /*!< C_CAN1 IF2_DA1: DATA0 Mask          */
+#define C_CAN1_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF2_DA1: DATA1 Position      */
+#define C_CAN1_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos)                /*!< C_CAN1 IF2_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN1_IF2_DA2  -----------------------------------------
+#define C_CAN1_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF2_DA2: DATA2 Position      */
+#define C_CAN1_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos)                /*!< C_CAN1 IF2_DA2: DATA2 Mask          */
+#define C_CAN1_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF2_DA2: DATA3 Position      */
+#define C_CAN1_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos)                /*!< C_CAN1 IF2_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN1_IF2_DB1  -----------------------------------------
+#define C_CAN1_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF2_DB1: DATA4 Position      */
+#define C_CAN1_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos)                /*!< C_CAN1 IF2_DB1: DATA4 Mask          */
+#define C_CAN1_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF2_DB1: DATA5 Position      */
+#define C_CAN1_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos)                /*!< C_CAN1 IF2_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN1_IF2_DB2  -----------------------------------------
+#define C_CAN1_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF2_DB2: DATA6 Position      */
+#define C_CAN1_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos)                /*!< C_CAN1 IF2_DB2: DATA6 Mask          */
+#define C_CAN1_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF2_DB2: DATA7 Position      */
+#define C_CAN1_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos)                /*!< C_CAN1 IF2_DB2: DATA7 Mask          */
+
+// --------------------------------------  C_CAN1_TXREQ1  -----------------------------------------
+#define C_CAN1_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN1 TXREQ1: TXRQST16_1 Position  */
+#define C_CAN1_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask      */
+
+// --------------------------------------  C_CAN1_TXREQ2  -----------------------------------------
+#define C_CAN1_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */
+#define C_CAN1_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask     */
+
+// ---------------------------------------  C_CAN1_ND1  -------------------------------------------
+#define C_CAN1_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN1 ND1: NEWDAT16_1 Position     */
+#define C_CAN1_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos)               /*!< C_CAN1 ND1: NEWDAT16_1 Mask         */
+
+// ---------------------------------------  C_CAN1_ND2  -------------------------------------------
+#define C_CAN1_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN1 ND2: NEWDAT32_17 Position    */
+#define C_CAN1_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos)              /*!< C_CAN1 ND2: NEWDAT32_17 Mask        */
+
+// ---------------------------------------  C_CAN1_IR1  -------------------------------------------
+#define C_CAN1_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN1 IR1: INTPND16_1 Position     */
+#define C_CAN1_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos)               /*!< C_CAN1 IR1: INTPND16_1 Mask         */
+
+// ---------------------------------------  C_CAN1_IR2  -------------------------------------------
+#define C_CAN1_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN1 IR2: INTPND32_17 Position    */
+#define C_CAN1_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos)              /*!< C_CAN1 IR2: INTPND32_17 Mask        */
+
+// --------------------------------------  C_CAN1_MSGV1  ------------------------------------------
+#define C_CAN1_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN1 MSGV1: MSGVAL16_1 Position   */
+#define C_CAN1_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask       */
+
+// --------------------------------------  C_CAN1_MSGV2  ------------------------------------------
+#define C_CAN1_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN1 MSGV2: MSGVAL32_17 Position  */
+#define C_CAN1_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask      */
+
+// --------------------------------------  C_CAN1_CLKDIV  -----------------------------------------
+#define C_CAN1_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN1 CLKDIV: CLKDIVVAL Position   */
+#define C_CAN1_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                RITIMER Position & Mask                               -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  RITIMER_COMPVAL  ----------------------------------------
+#define RITIMER_COMPVAL_RICOMP_Pos                            0                                                         /*!< RITIMER COMPVAL: RICOMP Position    */
+#define RITIMER_COMPVAL_RICOMP_Msk                            (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos)              /*!< RITIMER COMPVAL: RICOMP Mask        */
+
+// --------------------------------------  RITIMER_MASK  ------------------------------------------
+#define RITIMER_MASK_RIMASK_Pos                               0                                                         /*!< RITIMER MASK: RIMASK Position       */
+#define RITIMER_MASK_RIMASK_Msk                               (0xffffffffUL << RITIMER_MASK_RIMASK_Pos)                 /*!< RITIMER MASK: RIMASK Mask           */
+
+// --------------------------------------  RITIMER_CTRL  ------------------------------------------
+#define RITIMER_CTRL_RITINT_Pos                               0                                                         /*!< RITIMER CTRL: RITINT Position       */
+#define RITIMER_CTRL_RITINT_Msk                               (0x01UL << RITIMER_CTRL_RITINT_Pos)                       /*!< RITIMER CTRL: RITINT Mask           */
+#define RITIMER_CTRL_RITENCLR_Pos                             1                                                         /*!< RITIMER CTRL: RITENCLR Position     */
+#define RITIMER_CTRL_RITENCLR_Msk                             (0x01UL << RITIMER_CTRL_RITENCLR_Pos)                     /*!< RITIMER CTRL: RITENCLR Mask         */
+#define RITIMER_CTRL_RITENBR_Pos                              2                                                         /*!< RITIMER CTRL: RITENBR Position      */
+#define RITIMER_CTRL_RITENBR_Msk                              (0x01UL << RITIMER_CTRL_RITENBR_Pos)                      /*!< RITIMER CTRL: RITENBR Mask          */
+#define RITIMER_CTRL_RITEN_Pos                                3                                                         /*!< RITIMER CTRL: RITEN Position        */
+#define RITIMER_CTRL_RITEN_Msk                                (0x01UL << RITIMER_CTRL_RITEN_Pos)                        /*!< RITIMER CTRL: RITEN Mask            */
+
+// -------------------------------------  RITIMER_COUNTER  ----------------------------------------
+#define RITIMER_COUNTER_RICOUNTER_Pos                         0                                                         /*!< RITIMER COUNTER: RICOUNTER Position */
+#define RITIMER_COUNTER_RICOUNTER_Msk                         (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos)           /*!< RITIMER COUNTER: RICOUNTER Mask     */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  QEI Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  QEI_CON  --------------------------------------------
+#define QEI_CON_RESP_Pos                                      0                                                         /*!< QEI CON: RESP Position              */
+#define QEI_CON_RESP_Msk                                      (0x01UL << QEI_CON_RESP_Pos)                              /*!< QEI CON: RESP Mask                  */
+#define QEI_CON_RESPI_Pos                                     1                                                         /*!< QEI CON: RESPI Position             */
+#define QEI_CON_RESPI_Msk                                     (0x01UL << QEI_CON_RESPI_Pos)                             /*!< QEI CON: RESPI Mask                 */
+#define QEI_CON_RESV_Pos                                      2                                                         /*!< QEI CON: RESV Position              */
+#define QEI_CON_RESV_Msk                                      (0x01UL << QEI_CON_RESV_Pos)                              /*!< QEI CON: RESV Mask                  */
+#define QEI_CON_RESI_Pos                                      3                                                         /*!< QEI CON: RESI Position              */
+#define QEI_CON_RESI_Msk                                      (0x01UL << QEI_CON_RESI_Pos)                              /*!< QEI CON: RESI Mask                  */
+
+// ----------------------------------------  QEI_STAT  --------------------------------------------
+#define QEI_STAT_DIR_Pos                                      0                                                         /*!< QEI STAT: DIR Position              */
+#define QEI_STAT_DIR_Msk                                      (0x01UL << QEI_STAT_DIR_Pos)                              /*!< QEI STAT: DIR Mask                  */
+
+// ----------------------------------------  QEI_CONF  --------------------------------------------
+#define QEI_CONF_DIRINV_Pos                                   0                                                         /*!< QEI CONF: DIRINV Position           */
+#define QEI_CONF_DIRINV_Msk                                   (0x01UL << QEI_CONF_DIRINV_Pos)                           /*!< QEI CONF: DIRINV Mask               */
+#define QEI_CONF_SIGMODE_Pos                                  1                                                         /*!< QEI CONF: SIGMODE Position          */
+#define QEI_CONF_SIGMODE_Msk                                  (0x01UL << QEI_CONF_SIGMODE_Pos)                          /*!< QEI CONF: SIGMODE Mask              */
+#define QEI_CONF_CAPMODE_Pos                                  2                                                         /*!< QEI CONF: CAPMODE Position          */
+#define QEI_CONF_CAPMODE_Msk                                  (0x01UL << QEI_CONF_CAPMODE_Pos)                          /*!< QEI CONF: CAPMODE Mask              */
+#define QEI_CONF_INVINX_Pos                                   3                                                         /*!< QEI CONF: INVINX Position           */
+#define QEI_CONF_INVINX_Msk                                   (0x01UL << QEI_CONF_INVINX_Pos)                           /*!< QEI CONF: INVINX Mask               */
+#define QEI_CONF_CRESPI_Pos                                   4                                                         /*!< QEI CONF: CRESPI Position           */
+#define QEI_CONF_CRESPI_Msk                                   (0x01UL << QEI_CONF_CRESPI_Pos)                           /*!< QEI CONF: CRESPI Mask               */
+#define QEI_CONF_INXGATE_Pos                                  16                                                        /*!< QEI CONF: INXGATE Position          */
+#define QEI_CONF_INXGATE_Msk                                  (0x0fUL << QEI_CONF_INXGATE_Pos)                          /*!< QEI CONF: INXGATE Mask              */
+
+// -----------------------------------------  QEI_POS  --------------------------------------------
+#define QEI_POS_POS_Pos                                       0                                                         /*!< QEI POS: POS Position               */
+#define QEI_POS_POS_Msk                                       (0xffffffffUL << QEI_POS_POS_Pos)                         /*!< QEI POS: POS Mask                   */
+
+// ---------------------------------------  QEI_MAXPOS  -------------------------------------------
+#define QEI_MAXPOS_MAXPOS_Pos                                 0                                                         /*!< QEI MAXPOS: MAXPOS Position         */
+#define QEI_MAXPOS_MAXPOS_Msk                                 (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos)                   /*!< QEI MAXPOS: MAXPOS Mask             */
+
+// ---------------------------------------  QEI_CMPOS0  -------------------------------------------
+#define QEI_CMPOS0_PCMP0_Pos                                  0                                                         /*!< QEI CMPOS0: PCMP0 Position          */
+#define QEI_CMPOS0_PCMP0_Msk                                  (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos)                    /*!< QEI CMPOS0: PCMP0 Mask              */
+
+// ---------------------------------------  QEI_CMPOS1  -------------------------------------------
+#define QEI_CMPOS1_PCMP1_Pos                                  0                                                         /*!< QEI CMPOS1: PCMP1 Position          */
+#define QEI_CMPOS1_PCMP1_Msk                                  (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos)                    /*!< QEI CMPOS1: PCMP1 Mask              */
+
+// ---------------------------------------  QEI_CMPOS2  -------------------------------------------
+#define QEI_CMPOS2_PCMP2_Pos                                  0                                                         /*!< QEI CMPOS2: PCMP2 Position          */
+#define QEI_CMPOS2_PCMP2_Msk                                  (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos)                    /*!< QEI CMPOS2: PCMP2 Mask              */
+
+// ---------------------------------------  QEI_INXCNT  -------------------------------------------
+#define QEI_INXCNT_ENCPOS_Pos                                 0                                                         /*!< QEI INXCNT: ENCPOS Position         */
+#define QEI_INXCNT_ENCPOS_Msk                                 (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos)                   /*!< QEI INXCNT: ENCPOS Mask             */
+
+// ---------------------------------------  QEI_INXCMP0  ------------------------------------------
+#define QEI_INXCMP0_ICMP0_Pos                                 0                                                         /*!< QEI INXCMP0: ICMP0 Position         */
+#define QEI_INXCMP0_ICMP0_Msk                                 (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos)                   /*!< QEI INXCMP0: ICMP0 Mask             */
+
+// ----------------------------------------  QEI_LOAD  --------------------------------------------
+#define QEI_LOAD_VELLOAD_Pos                                  0                                                         /*!< QEI LOAD: VELLOAD Position          */
+#define QEI_LOAD_VELLOAD_Msk                                  (0xffffffffUL << QEI_LOAD_VELLOAD_Pos)                    /*!< QEI LOAD: VELLOAD Mask              */
+
+// ----------------------------------------  QEI_TIME  --------------------------------------------
+#define QEI_TIME_VELVAL_Pos                                   0                                                         /*!< QEI TIME: VELVAL Position           */
+#define QEI_TIME_VELVAL_Msk                                   (0xffffffffUL << QEI_TIME_VELVAL_Pos)                     /*!< QEI TIME: VELVAL Mask               */
+
+// -----------------------------------------  QEI_VEL  --------------------------------------------
+#define QEI_VEL_VELPC_Pos                                     0                                                         /*!< QEI VEL: VELPC Position             */
+#define QEI_VEL_VELPC_Msk                                     (0xffffffffUL << QEI_VEL_VELPC_Pos)                       /*!< QEI VEL: VELPC Mask                 */
+
+// -----------------------------------------  QEI_CAP  --------------------------------------------
+#define QEI_CAP_VELCAP_Pos                                    0                                                         /*!< QEI CAP: VELCAP Position            */
+#define QEI_CAP_VELCAP_Msk                                    (0xffffffffUL << QEI_CAP_VELCAP_Pos)                      /*!< QEI CAP: VELCAP Mask                */
+
+// ---------------------------------------  QEI_VELCOMP  ------------------------------------------
+#define QEI_VELCOMP_VELCMP_Pos                                0                                                         /*!< QEI VELCOMP: VELCMP Position        */
+#define QEI_VELCOMP_VELCMP_Msk                                (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos)                  /*!< QEI VELCOMP: VELCMP Mask            */
+
+// --------------------------------------  QEI_FILTERPHA  -----------------------------------------
+#define QEI_FILTERPHA_FILTA_Pos                               0                                                         /*!< QEI FILTERPHA: FILTA Position       */
+#define QEI_FILTERPHA_FILTA_Msk                               (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos)                 /*!< QEI FILTERPHA: FILTA Mask           */
+
+// --------------------------------------  QEI_FILTERPHB  -----------------------------------------
+#define QEI_FILTERPHB_FILTB_Pos                               0                                                         /*!< QEI FILTERPHB: FILTB Position       */
+#define QEI_FILTERPHB_FILTB_Msk                               (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos)                 /*!< QEI FILTERPHB: FILTB Mask           */
+
+// --------------------------------------  QEI_FILTERINX  -----------------------------------------
+#define QEI_FILTERINX_FITLINX_Pos                             0                                                         /*!< QEI FILTERINX: FITLINX Position     */
+#define QEI_FILTERINX_FITLINX_Msk                             (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos)               /*!< QEI FILTERINX: FITLINX Mask         */
+
+// ---------------------------------------  QEI_WINDOW  -------------------------------------------
+#define QEI_WINDOW_WINDOW_Pos                                 0                                                         /*!< QEI WINDOW: WINDOW Position         */
+#define QEI_WINDOW_WINDOW_Msk                                 (0xffffffffUL << QEI_WINDOW_WINDOW_Pos)                   /*!< QEI WINDOW: WINDOW Mask             */
+
+// ---------------------------------------  QEI_INXCMP1  ------------------------------------------
+#define QEI_INXCMP1_ICMP1_Pos                                 0                                                         /*!< QEI INXCMP1: ICMP1 Position         */
+#define QEI_INXCMP1_ICMP1_Msk                                 (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos)                   /*!< QEI INXCMP1: ICMP1 Mask             */
+
+// ---------------------------------------  QEI_INXCMP2  ------------------------------------------
+#define QEI_INXCMP2_ICMP2_Pos                                 0                                                         /*!< QEI INXCMP2: ICMP2 Position         */
+#define QEI_INXCMP2_ICMP2_Msk                                 (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos)                   /*!< QEI INXCMP2: ICMP2 Mask             */
+
+// -----------------------------------------  QEI_IEC  --------------------------------------------
+#define QEI_IEC_INX_EN_Pos                                    0                                                         /*!< QEI IEC: INX_EN Position            */
+#define QEI_IEC_INX_EN_Msk                                    (0x01UL << QEI_IEC_INX_EN_Pos)                            /*!< QEI IEC: INX_EN Mask                */
+#define QEI_IEC_TIM_EN_Pos                                    1                                                         /*!< QEI IEC: TIM_EN Position            */
+#define QEI_IEC_TIM_EN_Msk                                    (0x01UL << QEI_IEC_TIM_EN_Pos)                            /*!< QEI IEC: TIM_EN Mask                */
+#define QEI_IEC_VELC_EN_Pos                                   2                                                         /*!< QEI IEC: VELC_EN Position           */
+#define QEI_IEC_VELC_EN_Msk                                   (0x01UL << QEI_IEC_VELC_EN_Pos)                           /*!< QEI IEC: VELC_EN Mask               */
+#define QEI_IEC_DIR_EN_Pos                                    3                                                         /*!< QEI IEC: DIR_EN Position            */
+#define QEI_IEC_DIR_EN_Msk                                    (0x01UL << QEI_IEC_DIR_EN_Pos)                            /*!< QEI IEC: DIR_EN Mask                */
+#define QEI_IEC_ERR_EN_Pos                                    4                                                         /*!< QEI IEC: ERR_EN Position            */
+#define QEI_IEC_ERR_EN_Msk                                    (0x01UL << QEI_IEC_ERR_EN_Pos)                            /*!< QEI IEC: ERR_EN Mask                */
+#define QEI_IEC_ENCLK_EN_Pos                                  5                                                         /*!< QEI IEC: ENCLK_EN Position          */
+#define QEI_IEC_ENCLK_EN_Msk                                  (0x01UL << QEI_IEC_ENCLK_EN_Pos)                          /*!< QEI IEC: ENCLK_EN Mask              */
+#define QEI_IEC_POS0_Int_Pos                                  6                                                         /*!< QEI IEC: POS0_Int Position          */
+#define QEI_IEC_POS0_Int_Msk                                  (0x01UL << QEI_IEC_POS0_Int_Pos)                          /*!< QEI IEC: POS0_Int Mask              */
+#define QEI_IEC_POS1_Int_Pos                                  7                                                         /*!< QEI IEC: POS1_Int Position          */
+#define QEI_IEC_POS1_Int_Msk                                  (0x01UL << QEI_IEC_POS1_Int_Pos)                          /*!< QEI IEC: POS1_Int Mask              */
+#define QEI_IEC_POS2_Int_Pos                                  8                                                         /*!< QEI IEC: POS2_Int Position          */
+#define QEI_IEC_POS2_Int_Msk                                  (0x01UL << QEI_IEC_POS2_Int_Pos)                          /*!< QEI IEC: POS2_Int Mask              */
+#define QEI_IEC_REV_Int_Pos                                   9                                                         /*!< QEI IEC: REV_Int Position           */
+#define QEI_IEC_REV_Int_Msk                                   (0x01UL << QEI_IEC_REV_Int_Pos)                           /*!< QEI IEC: REV_Int Mask               */
+#define QEI_IEC_POS0REV_Int_Pos                               10                                                        /*!< QEI IEC: POS0REV_Int Position       */
+#define QEI_IEC_POS0REV_Int_Msk                               (0x01UL << QEI_IEC_POS0REV_Int_Pos)                       /*!< QEI IEC: POS0REV_Int Mask           */
+#define QEI_IEC_POS1REV_Int_Pos                               11                                                        /*!< QEI IEC: POS1REV_Int Position       */
+#define QEI_IEC_POS1REV_Int_Msk                               (0x01UL << QEI_IEC_POS1REV_Int_Pos)                       /*!< QEI IEC: POS1REV_Int Mask           */
+#define QEI_IEC_POS2REV_Int_Pos                               12                                                        /*!< QEI IEC: POS2REV_Int Position       */
+#define QEI_IEC_POS2REV_Int_Msk                               (0x01UL << QEI_IEC_POS2REV_Int_Pos)                       /*!< QEI IEC: POS2REV_Int Mask           */
+#define QEI_IEC_REV1_Int_Pos                                  13                                                        /*!< QEI IEC: REV1_Int Position          */
+#define QEI_IEC_REV1_Int_Msk                                  (0x01UL << QEI_IEC_REV1_Int_Pos)                          /*!< QEI IEC: REV1_Int Mask              */
+#define QEI_IEC_REV2_Int_Pos                                  14                                                        /*!< QEI IEC: REV2_Int Position          */
+#define QEI_IEC_REV2_Int_Msk                                  (0x01UL << QEI_IEC_REV2_Int_Pos)                          /*!< QEI IEC: REV2_Int Mask              */
+#define QEI_IEC_MAXPOS_Int_Pos                                15                                                        /*!< QEI IEC: MAXPOS_Int Position        */
+#define QEI_IEC_MAXPOS_Int_Msk                                (0x01UL << QEI_IEC_MAXPOS_Int_Pos)                        /*!< QEI IEC: MAXPOS_Int Mask            */
+
+// -----------------------------------------  QEI_IES  --------------------------------------------
+#define QEI_IES_INX_EN_Pos                                    0                                                         /*!< QEI IES: INX_EN Position            */
+#define QEI_IES_INX_EN_Msk                                    (0x01UL << QEI_IES_INX_EN_Pos)                            /*!< QEI IES: INX_EN Mask                */
+#define QEI_IES_TIM_EN_Pos                                    1                                                         /*!< QEI IES: TIM_EN Position            */
+#define QEI_IES_TIM_EN_Msk                                    (0x01UL << QEI_IES_TIM_EN_Pos)                            /*!< QEI IES: TIM_EN Mask                */
+#define QEI_IES_VELC_EN_Pos                                   2                                                         /*!< QEI IES: VELC_EN Position           */
+#define QEI_IES_VELC_EN_Msk                                   (0x01UL << QEI_IES_VELC_EN_Pos)                           /*!< QEI IES: VELC_EN Mask               */
+#define QEI_IES_DIR_EN_Pos                                    3                                                         /*!< QEI IES: DIR_EN Position            */
+#define QEI_IES_DIR_EN_Msk                                    (0x01UL << QEI_IES_DIR_EN_Pos)                            /*!< QEI IES: DIR_EN Mask                */
+#define QEI_IES_ERR_EN_Pos                                    4                                                         /*!< QEI IES: ERR_EN Position            */
+#define QEI_IES_ERR_EN_Msk                                    (0x01UL << QEI_IES_ERR_EN_Pos)                            /*!< QEI IES: ERR_EN Mask                */
+#define QEI_IES_ENCLK_EN_Pos                                  5                                                         /*!< QEI IES: ENCLK_EN Position          */
+#define QEI_IES_ENCLK_EN_Msk                                  (0x01UL << QEI_IES_ENCLK_EN_Pos)                          /*!< QEI IES: ENCLK_EN Mask              */
+#define QEI_IES_POS0_Int_Pos                                  6                                                         /*!< QEI IES: POS0_Int Position          */
+#define QEI_IES_POS0_Int_Msk                                  (0x01UL << QEI_IES_POS0_Int_Pos)                          /*!< QEI IES: POS0_Int Mask              */
+#define QEI_IES_POS1_Int_Pos                                  7                                                         /*!< QEI IES: POS1_Int Position          */
+#define QEI_IES_POS1_Int_Msk                                  (0x01UL << QEI_IES_POS1_Int_Pos)                          /*!< QEI IES: POS1_Int Mask              */
+#define QEI_IES_POS2_Int_Pos                                  8                                                         /*!< QEI IES: POS2_Int Position          */
+#define QEI_IES_POS2_Int_Msk                                  (0x01UL << QEI_IES_POS2_Int_Pos)                          /*!< QEI IES: POS2_Int Mask              */
+#define QEI_IES_REV_Int_Pos                                   9                                                         /*!< QEI IES: REV_Int Position           */
+#define QEI_IES_REV_Int_Msk                                   (0x01UL << QEI_IES_REV_Int_Pos)                           /*!< QEI IES: REV_Int Mask               */
+#define QEI_IES_POS0REV_Int_Pos                               10                                                        /*!< QEI IES: POS0REV_Int Position       */
+#define QEI_IES_POS0REV_Int_Msk                               (0x01UL << QEI_IES_POS0REV_Int_Pos)                       /*!< QEI IES: POS0REV_Int Mask           */
+#define QEI_IES_POS1REV_Int_Pos                               11                                                        /*!< QEI IES: POS1REV_Int Position       */
+#define QEI_IES_POS1REV_Int_Msk                               (0x01UL << QEI_IES_POS1REV_Int_Pos)                       /*!< QEI IES: POS1REV_Int Mask           */
+#define QEI_IES_POS2REV_Int_Pos                               12                                                        /*!< QEI IES: POS2REV_Int Position       */
+#define QEI_IES_POS2REV_Int_Msk                               (0x01UL << QEI_IES_POS2REV_Int_Pos)                       /*!< QEI IES: POS2REV_Int Mask           */
+#define QEI_IES_REV1_Int_Pos                                  13                                                        /*!< QEI IES: REV1_Int Position          */
+#define QEI_IES_REV1_Int_Msk                                  (0x01UL << QEI_IES_REV1_Int_Pos)                          /*!< QEI IES: REV1_Int Mask              */
+#define QEI_IES_REV2_Int_Pos                                  14                                                        /*!< QEI IES: REV2_Int Position          */
+#define QEI_IES_REV2_Int_Msk                                  (0x01UL << QEI_IES_REV2_Int_Pos)                          /*!< QEI IES: REV2_Int Mask              */
+#define QEI_IES_MAXPOS_Int_Pos                                15                                                        /*!< QEI IES: MAXPOS_Int Position        */
+#define QEI_IES_MAXPOS_Int_Msk                                (0x01UL << QEI_IES_MAXPOS_Int_Pos)                        /*!< QEI IES: MAXPOS_Int Mask            */
+
+// ---------------------------------------  QEI_INTSTAT  ------------------------------------------
+#define QEI_INTSTAT_INX_Int_Pos                               0                                                         /*!< QEI INTSTAT: INX_Int Position       */
+#define QEI_INTSTAT_INX_Int_Msk                               (0x01UL << QEI_INTSTAT_INX_Int_Pos)                       /*!< QEI INTSTAT: INX_Int Mask           */
+#define QEI_INTSTAT_TIM_Int_Pos                               1                                                         /*!< QEI INTSTAT: TIM_Int Position       */
+#define QEI_INTSTAT_TIM_Int_Msk                               (0x01UL << QEI_INTSTAT_TIM_Int_Pos)                       /*!< QEI INTSTAT: TIM_Int Mask           */
+#define QEI_INTSTAT_VELC_Int_Pos                              2                                                         /*!< QEI INTSTAT: VELC_Int Position      */
+#define QEI_INTSTAT_VELC_Int_Msk                              (0x01UL << QEI_INTSTAT_VELC_Int_Pos)                      /*!< QEI INTSTAT: VELC_Int Mask          */
+#define QEI_INTSTAT_DIR_Int_Pos                               3                                                         /*!< QEI INTSTAT: DIR_Int Position       */
+#define QEI_INTSTAT_DIR_Int_Msk                               (0x01UL << QEI_INTSTAT_DIR_Int_Pos)                       /*!< QEI INTSTAT: DIR_Int Mask           */
+#define QEI_INTSTAT_ERR_Int_Pos                               4                                                         /*!< QEI INTSTAT: ERR_Int Position       */
+#define QEI_INTSTAT_ERR_Int_Msk                               (0x01UL << QEI_INTSTAT_ERR_Int_Pos)                       /*!< QEI INTSTAT: ERR_Int Mask           */
+#define QEI_INTSTAT_ENCLK_Int_Pos                             5                                                         /*!< QEI INTSTAT: ENCLK_Int Position     */
+#define QEI_INTSTAT_ENCLK_Int_Msk                             (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos)                     /*!< QEI INTSTAT: ENCLK_Int Mask         */
+#define QEI_INTSTAT_POS0_Int_Pos                              6                                                         /*!< QEI INTSTAT: POS0_Int Position      */
+#define QEI_INTSTAT_POS0_Int_Msk                              (0x01UL << QEI_INTSTAT_POS0_Int_Pos)                      /*!< QEI INTSTAT: POS0_Int Mask          */
+#define QEI_INTSTAT_POS1_Int_Pos                              7                                                         /*!< QEI INTSTAT: POS1_Int Position      */
+#define QEI_INTSTAT_POS1_Int_Msk                              (0x01UL << QEI_INTSTAT_POS1_Int_Pos)                      /*!< QEI INTSTAT: POS1_Int Mask          */
+#define QEI_INTSTAT_POS2_Int_Pos                              8                                                         /*!< QEI INTSTAT: POS2_Int Position      */
+#define QEI_INTSTAT_POS2_Int_Msk                              (0x01UL << QEI_INTSTAT_POS2_Int_Pos)                      /*!< QEI INTSTAT: POS2_Int Mask          */
+#define QEI_INTSTAT_REV_Int_Pos                               9                                                         /*!< QEI INTSTAT: REV_Int Position       */
+#define QEI_INTSTAT_REV_Int_Msk                               (0x01UL << QEI_INTSTAT_REV_Int_Pos)                       /*!< QEI INTSTAT: REV_Int Mask           */
+#define QEI_INTSTAT_POS0REV_Int_Pos                           10                                                        /*!< QEI INTSTAT: POS0REV_Int Position   */
+#define QEI_INTSTAT_POS0REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos)                   /*!< QEI INTSTAT: POS0REV_Int Mask       */
+#define QEI_INTSTAT_POS1REV_Int_Pos                           11                                                        /*!< QEI INTSTAT: POS1REV_Int Position   */
+#define QEI_INTSTAT_POS1REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos)                   /*!< QEI INTSTAT: POS1REV_Int Mask       */
+#define QEI_INTSTAT_POS2REV_Int_Pos                           12                                                        /*!< QEI INTSTAT: POS2REV_Int Position   */
+#define QEI_INTSTAT_POS2REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos)                   /*!< QEI INTSTAT: POS2REV_Int Mask       */
+#define QEI_INTSTAT_REV1_Int_Pos                              13                                                        /*!< QEI INTSTAT: REV1_Int Position      */
+#define QEI_INTSTAT_REV1_Int_Msk                              (0x01UL << QEI_INTSTAT_REV1_Int_Pos)                      /*!< QEI INTSTAT: REV1_Int Mask          */
+#define QEI_INTSTAT_REV2_Int_Pos                              14                                                        /*!< QEI INTSTAT: REV2_Int Position      */
+#define QEI_INTSTAT_REV2_Int_Msk                              (0x01UL << QEI_INTSTAT_REV2_Int_Pos)                      /*!< QEI INTSTAT: REV2_Int Mask          */
+#define QEI_INTSTAT_MAXPOS_Int_Pos                            15                                                        /*!< QEI INTSTAT: MAXPOS_Int Position    */
+#define QEI_INTSTAT_MAXPOS_Int_Msk                            (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos)                    /*!< QEI INTSTAT: MAXPOS_Int Mask        */
+
+// -----------------------------------------  QEI_IE  ---------------------------------------------
+#define QEI_IE_INX_Int_Pos                                    0                                                         /*!< QEI IE: INX_Int Position            */
+#define QEI_IE_INX_Int_Msk                                    (0x01UL << QEI_IE_INX_Int_Pos)                            /*!< QEI IE: INX_Int Mask                */
+#define QEI_IE_TIM_Int_Pos                                    1                                                         /*!< QEI IE: TIM_Int Position            */
+#define QEI_IE_TIM_Int_Msk                                    (0x01UL << QEI_IE_TIM_Int_Pos)                            /*!< QEI IE: TIM_Int Mask                */
+#define QEI_IE_VELC_Int_Pos                                   2                                                         /*!< QEI IE: VELC_Int Position           */
+#define QEI_IE_VELC_Int_Msk                                   (0x01UL << QEI_IE_VELC_Int_Pos)                           /*!< QEI IE: VELC_Int Mask               */
+#define QEI_IE_DIR_Int_Pos                                    3                                                         /*!< QEI IE: DIR_Int Position            */
+#define QEI_IE_DIR_Int_Msk                                    (0x01UL << QEI_IE_DIR_Int_Pos)                            /*!< QEI IE: DIR_Int Mask                */
+#define QEI_IE_ERR_Int_Pos                                    4                                                         /*!< QEI IE: ERR_Int Position            */
+#define QEI_IE_ERR_Int_Msk                                    (0x01UL << QEI_IE_ERR_Int_Pos)                            /*!< QEI IE: ERR_Int Mask                */
+#define QEI_IE_ENCLK_Int_Pos                                  5                                                         /*!< QEI IE: ENCLK_Int Position          */
+#define QEI_IE_ENCLK_Int_Msk                                  (0x01UL << QEI_IE_ENCLK_Int_Pos)                          /*!< QEI IE: ENCLK_Int Mask              */
+#define QEI_IE_POS0_Int_Pos                                   6                                                         /*!< QEI IE: POS0_Int Position           */
+#define QEI_IE_POS0_Int_Msk                                   (0x01UL << QEI_IE_POS0_Int_Pos)                           /*!< QEI IE: POS0_Int Mask               */
+#define QEI_IE_POS1_Int_Pos                                   7                                                         /*!< QEI IE: POS1_Int Position           */
+#define QEI_IE_POS1_Int_Msk                                   (0x01UL << QEI_IE_POS1_Int_Pos)                           /*!< QEI IE: POS1_Int Mask               */
+#define QEI_IE_POS2_Int_Pos                                   8                                                         /*!< QEI IE: POS2_Int Position           */
+#define QEI_IE_POS2_Int_Msk                                   (0x01UL << QEI_IE_POS2_Int_Pos)                           /*!< QEI IE: POS2_Int Mask               */
+#define QEI_IE_REV_Int_Pos                                    9                                                         /*!< QEI IE: REV_Int Position            */
+#define QEI_IE_REV_Int_Msk                                    (0x01UL << QEI_IE_REV_Int_Pos)                            /*!< QEI IE: REV_Int Mask                */
+#define QEI_IE_POS0REV_Int_Pos                                10                                                        /*!< QEI IE: POS0REV_Int Position        */
+#define QEI_IE_POS0REV_Int_Msk                                (0x01UL << QEI_IE_POS0REV_Int_Pos)                        /*!< QEI IE: POS0REV_Int Mask            */
+#define QEI_IE_POS1REV_Int_Pos                                11                                                        /*!< QEI IE: POS1REV_Int Position        */
+#define QEI_IE_POS1REV_Int_Msk                                (0x01UL << QEI_IE_POS1REV_Int_Pos)                        /*!< QEI IE: POS1REV_Int Mask            */
+#define QEI_IE_POS2REV_Int_Pos                                12                                                        /*!< QEI IE: POS2REV_Int Position        */
+#define QEI_IE_POS2REV_Int_Msk                                (0x01UL << QEI_IE_POS2REV_Int_Pos)                        /*!< QEI IE: POS2REV_Int Mask            */
+#define QEI_IE_REV1_Int_Pos                                   13                                                        /*!< QEI IE: REV1_Int Position           */
+#define QEI_IE_REV1_Int_Msk                                   (0x01UL << QEI_IE_REV1_Int_Pos)                           /*!< QEI IE: REV1_Int Mask               */
+#define QEI_IE_REV2_Int_Pos                                   14                                                        /*!< QEI IE: REV2_Int Position           */
+#define QEI_IE_REV2_Int_Msk                                   (0x01UL << QEI_IE_REV2_Int_Pos)                           /*!< QEI IE: REV2_Int Mask               */
+#define QEI_IE_MAXPOS_Int_Pos                                 15                                                        /*!< QEI IE: MAXPOS_Int Position         */
+#define QEI_IE_MAXPOS_Int_Msk                                 (0x01UL << QEI_IE_MAXPOS_Int_Pos)                         /*!< QEI IE: MAXPOS_Int Mask             */
+
+// -----------------------------------------  QEI_CLR  --------------------------------------------
+#define QEI_CLR_INX_Int_Pos                                   0                                                         /*!< QEI CLR: INX_Int Position           */
+#define QEI_CLR_INX_Int_Msk                                   (0x01UL << QEI_CLR_INX_Int_Pos)                           /*!< QEI CLR: INX_Int Mask               */
+#define QEI_CLR_TIM_Int_Pos                                   1                                                         /*!< QEI CLR: TIM_Int Position           */
+#define QEI_CLR_TIM_Int_Msk                                   (0x01UL << QEI_CLR_TIM_Int_Pos)                           /*!< QEI CLR: TIM_Int Mask               */
+#define QEI_CLR_VELC_Int_Pos                                  2                                                         /*!< QEI CLR: VELC_Int Position          */
+#define QEI_CLR_VELC_Int_Msk                                  (0x01UL << QEI_CLR_VELC_Int_Pos)                          /*!< QEI CLR: VELC_Int Mask              */
+#define QEI_CLR_DIR_Int_Pos                                   3                                                         /*!< QEI CLR: DIR_Int Position           */
+#define QEI_CLR_DIR_Int_Msk                                   (0x01UL << QEI_CLR_DIR_Int_Pos)                           /*!< QEI CLR: DIR_Int Mask               */
+#define QEI_CLR_ERR_Int_Pos                                   4                                                         /*!< QEI CLR: ERR_Int Position           */
+#define QEI_CLR_ERR_Int_Msk                                   (0x01UL << QEI_CLR_ERR_Int_Pos)                           /*!< QEI CLR: ERR_Int Mask               */
+#define QEI_CLR_ENCLK_Int_Pos                                 5                                                         /*!< QEI CLR: ENCLK_Int Position         */
+#define QEI_CLR_ENCLK_Int_Msk                                 (0x01UL << QEI_CLR_ENCLK_Int_Pos)                         /*!< QEI CLR: ENCLK_Int Mask             */
+#define QEI_CLR_POS0_Int_Pos                                  6                                                         /*!< QEI CLR: POS0_Int Position          */
+#define QEI_CLR_POS0_Int_Msk                                  (0x01UL << QEI_CLR_POS0_Int_Pos)                          /*!< QEI CLR: POS0_Int Mask              */
+#define QEI_CLR_POS1_Int_Pos                                  7                                                         /*!< QEI CLR: POS1_Int Position          */
+#define QEI_CLR_POS1_Int_Msk                                  (0x01UL << QEI_CLR_POS1_Int_Pos)                          /*!< QEI CLR: POS1_Int Mask              */
+#define QEI_CLR_POS2_Int_Pos                                  8                                                         /*!< QEI CLR: POS2_Int Position          */
+#define QEI_CLR_POS2_Int_Msk                                  (0x01UL << QEI_CLR_POS2_Int_Pos)                          /*!< QEI CLR: POS2_Int Mask              */
+#define QEI_CLR_REV_Int_Pos                                   9                                                         /*!< QEI CLR: REV_Int Position           */
+#define QEI_CLR_REV_Int_Msk                                   (0x01UL << QEI_CLR_REV_Int_Pos)                           /*!< QEI CLR: REV_Int Mask               */
+#define QEI_CLR_POS0REV_Int_Pos                               10                                                        /*!< QEI CLR: POS0REV_Int Position       */
+#define QEI_CLR_POS0REV_Int_Msk                               (0x01UL << QEI_CLR_POS0REV_Int_Pos)                       /*!< QEI CLR: POS0REV_Int Mask           */
+#define QEI_CLR_POS1REV_Int_Pos                               11                                                        /*!< QEI CLR: POS1REV_Int Position       */
+#define QEI_CLR_POS1REV_Int_Msk                               (0x01UL << QEI_CLR_POS1REV_Int_Pos)                       /*!< QEI CLR: POS1REV_Int Mask           */
+#define QEI_CLR_REV1_Int_Pos                                  13                                                        /*!< QEI CLR: REV1_Int Position          */
+#define QEI_CLR_REV1_Int_Msk                                  (0x01UL << QEI_CLR_REV1_Int_Pos)                          /*!< QEI CLR: REV1_Int Mask              */
+#define QEI_CLR_REV2_Int_Pos                                  14                                                        /*!< QEI CLR: REV2_Int Position          */
+#define QEI_CLR_REV2_Int_Msk                                  (0x01UL << QEI_CLR_REV2_Int_Pos)                          /*!< QEI CLR: REV2_Int Mask              */
+#define QEI_CLR_MAXPOS_Int_Pos                                15                                                        /*!< QEI CLR: MAXPOS_Int Position        */
+#define QEI_CLR_MAXPOS_Int_Msk                                (0x01UL << QEI_CLR_MAXPOS_Int_Pos)                        /*!< QEI CLR: MAXPOS_Int Mask            */
+
+// -----------------------------------------  QEI_SET  --------------------------------------------
+#define QEI_SET_INX_Int_Pos                                   0                                                         /*!< QEI SET: INX_Int Position           */
+#define QEI_SET_INX_Int_Msk                                   (0x01UL << QEI_SET_INX_Int_Pos)                           /*!< QEI SET: INX_Int Mask               */
+#define QEI_SET_TIM_Int_Pos                                   1                                                         /*!< QEI SET: TIM_Int Position           */
+#define QEI_SET_TIM_Int_Msk                                   (0x01UL << QEI_SET_TIM_Int_Pos)                           /*!< QEI SET: TIM_Int Mask               */
+#define QEI_SET_VELC_Int_Pos                                  2                                                         /*!< QEI SET: VELC_Int Position          */
+#define QEI_SET_VELC_Int_Msk                                  (0x01UL << QEI_SET_VELC_Int_Pos)                          /*!< QEI SET: VELC_Int Mask              */
+#define QEI_SET_DIR_Int_Pos                                   3                                                         /*!< QEI SET: DIR_Int Position           */
+#define QEI_SET_DIR_Int_Msk                                   (0x01UL << QEI_SET_DIR_Int_Pos)                           /*!< QEI SET: DIR_Int Mask               */
+#define QEI_SET_ERR_Int_Pos                                   4                                                         /*!< QEI SET: ERR_Int Position           */
+#define QEI_SET_ERR_Int_Msk                                   (0x01UL << QEI_SET_ERR_Int_Pos)                           /*!< QEI SET: ERR_Int Mask               */
+#define QEI_SET_ENCLK_Int_Pos                                 5                                                         /*!< QEI SET: ENCLK_Int Position         */
+#define QEI_SET_ENCLK_Int_Msk                                 (0x01UL << QEI_SET_ENCLK_Int_Pos)                         /*!< QEI SET: ENCLK_Int Mask             */
+#define QEI_SET_POS0_Int_Pos                                  6                                                         /*!< QEI SET: POS0_Int Position          */
+#define QEI_SET_POS0_Int_Msk                                  (0x01UL << QEI_SET_POS0_Int_Pos)                          /*!< QEI SET: POS0_Int Mask              */
+#define QEI_SET_POS1_Int_Pos                                  7                                                         /*!< QEI SET: POS1_Int Position          */
+#define QEI_SET_POS1_Int_Msk                                  (0x01UL << QEI_SET_POS1_Int_Pos)                          /*!< QEI SET: POS1_Int Mask              */
+#define QEI_SET_POS2_Int_Pos                                  8                                                         /*!< QEI SET: POS2_Int Position          */
+#define QEI_SET_POS2_Int_Msk                                  (0x01UL << QEI_SET_POS2_Int_Pos)                          /*!< QEI SET: POS2_Int Mask              */
+#define QEI_SET_REV_Int_Pos                                   9                                                         /*!< QEI SET: REV_Int Position           */
+#define QEI_SET_REV_Int_Msk                                   (0x01UL << QEI_SET_REV_Int_Pos)                           /*!< QEI SET: REV_Int Mask               */
+#define QEI_SET_POS0REV_Int_Pos                               10                                                        /*!< QEI SET: POS0REV_Int Position       */
+#define QEI_SET_POS0REV_Int_Msk                               (0x01UL << QEI_SET_POS0REV_Int_Pos)                       /*!< QEI SET: POS0REV_Int Mask           */
+#define QEI_SET_POS1REV_Int_Pos                               11                                                        /*!< QEI SET: POS1REV_Int Position       */
+#define QEI_SET_POS1REV_Int_Msk                               (0x01UL << QEI_SET_POS1REV_Int_Pos)                       /*!< QEI SET: POS1REV_Int Mask           */
+#define QEI_SET_POS2REV_Int_Pos                               12                                                        /*!< QEI SET: POS2REV_Int Position       */
+#define QEI_SET_POS2REV_Int_Msk                               (0x01UL << QEI_SET_POS2REV_Int_Pos)                       /*!< QEI SET: POS2REV_Int Mask           */
+#define QEI_SET_REV1_Int_Pos                                  13                                                        /*!< QEI SET: REV1_Int Position          */
+#define QEI_SET_REV1_Int_Msk                                  (0x01UL << QEI_SET_REV1_Int_Pos)                          /*!< QEI SET: REV1_Int Mask              */
+#define QEI_SET_REV2_Int_Pos                                  14                                                        /*!< QEI SET: REV2_Int Position          */
+#define QEI_SET_REV2_Int_Msk                                  (0x01UL << QEI_SET_REV2_Int_Pos)                          /*!< QEI SET: REV2_Int Mask              */
+#define QEI_SET_MAXPOS_Int_Pos                                15                                                        /*!< QEI SET: MAXPOS_Int Position        */
+#define QEI_SET_MAXPOS_Int_Msk                                (0x01UL << QEI_SET_MAXPOS_Int_Pos)                        /*!< QEI SET: MAXPOS_Int Mask            */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 GIMA Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------  GIMA_CAP0_0_IN  -----------------------------------------
+#define GIMA_CAP0_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_0_IN: INV Position        */
+#define GIMA_CAP0_0_IN_INV_Msk                                (0x01UL << GIMA_CAP0_0_IN_INV_Pos)                        /*!< GIMA CAP0_0_IN: INV Mask            */
+#define GIMA_CAP0_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_0_IN: EDGE Position       */
+#define GIMA_CAP0_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos)                       /*!< GIMA CAP0_0_IN: EDGE Mask           */
+#define GIMA_CAP0_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_0_IN: SYNCH Position      */
+#define GIMA_CAP0_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos)                      /*!< GIMA CAP0_0_IN: SYNCH Mask          */
+#define GIMA_CAP0_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_0_IN: PULSE Position      */
+#define GIMA_CAP0_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos)                      /*!< GIMA CAP0_0_IN: PULSE Mask          */
+#define GIMA_CAP0_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_0_IN: SELECT Position     */
+#define GIMA_CAP0_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos)                     /*!< GIMA CAP0_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP0_1_IN  -----------------------------------------
+#define GIMA_CAP0_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_1_IN: INV Position        */
+#define GIMA_CAP0_1_IN_INV_Msk                                (0x01UL << GIMA_CAP0_1_IN_INV_Pos)                        /*!< GIMA CAP0_1_IN: INV Mask            */
+#define GIMA_CAP0_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_1_IN: EDGE Position       */
+#define GIMA_CAP0_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos)                       /*!< GIMA CAP0_1_IN: EDGE Mask           */
+#define GIMA_CAP0_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_1_IN: SYNCH Position      */
+#define GIMA_CAP0_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos)                      /*!< GIMA CAP0_1_IN: SYNCH Mask          */
+#define GIMA_CAP0_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_1_IN: PULSE Position      */
+#define GIMA_CAP0_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos)                      /*!< GIMA CAP0_1_IN: PULSE Mask          */
+#define GIMA_CAP0_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_1_IN: SELECT Position     */
+#define GIMA_CAP0_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos)                     /*!< GIMA CAP0_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP0_2_IN  -----------------------------------------
+#define GIMA_CAP0_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_2_IN: INV Position        */
+#define GIMA_CAP0_2_IN_INV_Msk                                (0x01UL << GIMA_CAP0_2_IN_INV_Pos)                        /*!< GIMA CAP0_2_IN: INV Mask            */
+#define GIMA_CAP0_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_2_IN: EDGE Position       */
+#define GIMA_CAP0_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos)                       /*!< GIMA CAP0_2_IN: EDGE Mask           */
+#define GIMA_CAP0_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_2_IN: SYNCH Position      */
+#define GIMA_CAP0_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos)                      /*!< GIMA CAP0_2_IN: SYNCH Mask          */
+#define GIMA_CAP0_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_2_IN: PULSE Position      */
+#define GIMA_CAP0_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos)                      /*!< GIMA CAP0_2_IN: PULSE Mask          */
+#define GIMA_CAP0_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_2_IN: SELECT Position     */
+#define GIMA_CAP0_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos)                     /*!< GIMA CAP0_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP0_3_IN  -----------------------------------------
+#define GIMA_CAP0_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_3_IN: INV Position        */
+#define GIMA_CAP0_3_IN_INV_Msk                                (0x01UL << GIMA_CAP0_3_IN_INV_Pos)                        /*!< GIMA CAP0_3_IN: INV Mask            */
+#define GIMA_CAP0_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_3_IN: EDGE Position       */
+#define GIMA_CAP0_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos)                       /*!< GIMA CAP0_3_IN: EDGE Mask           */
+#define GIMA_CAP0_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_3_IN: SYNCH Position      */
+#define GIMA_CAP0_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos)                      /*!< GIMA CAP0_3_IN: SYNCH Mask          */
+#define GIMA_CAP0_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_3_IN: PULSE Position      */
+#define GIMA_CAP0_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos)                      /*!< GIMA CAP0_3_IN: PULSE Mask          */
+#define GIMA_CAP0_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_3_IN: SELECT Position     */
+#define GIMA_CAP0_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos)                     /*!< GIMA CAP0_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_0_IN  -----------------------------------------
+#define GIMA_CAP1_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_0_IN: INV Position        */
+#define GIMA_CAP1_0_IN_INV_Msk                                (0x01UL << GIMA_CAP1_0_IN_INV_Pos)                        /*!< GIMA CAP1_0_IN: INV Mask            */
+#define GIMA_CAP1_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_0_IN: EDGE Position       */
+#define GIMA_CAP1_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos)                       /*!< GIMA CAP1_0_IN: EDGE Mask           */
+#define GIMA_CAP1_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_0_IN: SYNCH Position      */
+#define GIMA_CAP1_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos)                      /*!< GIMA CAP1_0_IN: SYNCH Mask          */
+#define GIMA_CAP1_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_0_IN: PULSE Position      */
+#define GIMA_CAP1_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos)                      /*!< GIMA CAP1_0_IN: PULSE Mask          */
+#define GIMA_CAP1_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_0_IN: SELECT Position     */
+#define GIMA_CAP1_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos)                     /*!< GIMA CAP1_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_1_IN  -----------------------------------------
+#define GIMA_CAP1_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_1_IN: INV Position        */
+#define GIMA_CAP1_1_IN_INV_Msk                                (0x01UL << GIMA_CAP1_1_IN_INV_Pos)                        /*!< GIMA CAP1_1_IN: INV Mask            */
+#define GIMA_CAP1_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_1_IN: EDGE Position       */
+#define GIMA_CAP1_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos)                       /*!< GIMA CAP1_1_IN: EDGE Mask           */
+#define GIMA_CAP1_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_1_IN: SYNCH Position      */
+#define GIMA_CAP1_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos)                      /*!< GIMA CAP1_1_IN: SYNCH Mask          */
+#define GIMA_CAP1_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_1_IN: PULSE Position      */
+#define GIMA_CAP1_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos)                      /*!< GIMA CAP1_1_IN: PULSE Mask          */
+#define GIMA_CAP1_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_1_IN: SELECT Position     */
+#define GIMA_CAP1_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos)                     /*!< GIMA CAP1_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_2_IN  -----------------------------------------
+#define GIMA_CAP1_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_2_IN: INV Position        */
+#define GIMA_CAP1_2_IN_INV_Msk                                (0x01UL << GIMA_CAP1_2_IN_INV_Pos)                        /*!< GIMA CAP1_2_IN: INV Mask            */
+#define GIMA_CAP1_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_2_IN: EDGE Position       */
+#define GIMA_CAP1_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos)                       /*!< GIMA CAP1_2_IN: EDGE Mask           */
+#define GIMA_CAP1_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_2_IN: SYNCH Position      */
+#define GIMA_CAP1_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos)                      /*!< GIMA CAP1_2_IN: SYNCH Mask          */
+#define GIMA_CAP1_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_2_IN: PULSE Position      */
+#define GIMA_CAP1_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos)                      /*!< GIMA CAP1_2_IN: PULSE Mask          */
+#define GIMA_CAP1_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_2_IN: SELECT Position     */
+#define GIMA_CAP1_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos)                     /*!< GIMA CAP1_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP1_3_IN  -----------------------------------------
+#define GIMA_CAP1_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_3_IN: INV Position        */
+#define GIMA_CAP1_3_IN_INV_Msk                                (0x01UL << GIMA_CAP1_3_IN_INV_Pos)                        /*!< GIMA CAP1_3_IN: INV Mask            */
+#define GIMA_CAP1_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_3_IN: EDGE Position       */
+#define GIMA_CAP1_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos)                       /*!< GIMA CAP1_3_IN: EDGE Mask           */
+#define GIMA_CAP1_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_3_IN: SYNCH Position      */
+#define GIMA_CAP1_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos)                      /*!< GIMA CAP1_3_IN: SYNCH Mask          */
+#define GIMA_CAP1_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_3_IN: PULSE Position      */
+#define GIMA_CAP1_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos)                      /*!< GIMA CAP1_3_IN: PULSE Mask          */
+#define GIMA_CAP1_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_3_IN: SELECT Position     */
+#define GIMA_CAP1_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos)                     /*!< GIMA CAP1_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_0_IN  -----------------------------------------
+#define GIMA_CAP2_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_0_IN: INV Position        */
+#define GIMA_CAP2_0_IN_INV_Msk                                (0x01UL << GIMA_CAP2_0_IN_INV_Pos)                        /*!< GIMA CAP2_0_IN: INV Mask            */
+#define GIMA_CAP2_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_0_IN: EDGE Position       */
+#define GIMA_CAP2_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos)                       /*!< GIMA CAP2_0_IN: EDGE Mask           */
+#define GIMA_CAP2_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_0_IN: SYNCH Position      */
+#define GIMA_CAP2_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos)                      /*!< GIMA CAP2_0_IN: SYNCH Mask          */
+#define GIMA_CAP2_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_0_IN: PULSE Position      */
+#define GIMA_CAP2_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos)                      /*!< GIMA CAP2_0_IN: PULSE Mask          */
+#define GIMA_CAP2_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_0_IN: SELECT Position     */
+#define GIMA_CAP2_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos)                     /*!< GIMA CAP2_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_1_IN  -----------------------------------------
+#define GIMA_CAP2_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_1_IN: INV Position        */
+#define GIMA_CAP2_1_IN_INV_Msk                                (0x01UL << GIMA_CAP2_1_IN_INV_Pos)                        /*!< GIMA CAP2_1_IN: INV Mask            */
+#define GIMA_CAP2_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_1_IN: EDGE Position       */
+#define GIMA_CAP2_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos)                       /*!< GIMA CAP2_1_IN: EDGE Mask           */
+#define GIMA_CAP2_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_1_IN: SYNCH Position      */
+#define GIMA_CAP2_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos)                      /*!< GIMA CAP2_1_IN: SYNCH Mask          */
+#define GIMA_CAP2_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_1_IN: PULSE Position      */
+#define GIMA_CAP2_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos)                      /*!< GIMA CAP2_1_IN: PULSE Mask          */
+#define GIMA_CAP2_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_1_IN: SELECT Position     */
+#define GIMA_CAP2_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos)                     /*!< GIMA CAP2_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_2_IN  -----------------------------------------
+#define GIMA_CAP2_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_2_IN: INV Position        */
+#define GIMA_CAP2_2_IN_INV_Msk                                (0x01UL << GIMA_CAP2_2_IN_INV_Pos)                        /*!< GIMA CAP2_2_IN: INV Mask            */
+#define GIMA_CAP2_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_2_IN: EDGE Position       */
+#define GIMA_CAP2_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos)                       /*!< GIMA CAP2_2_IN: EDGE Mask           */
+#define GIMA_CAP2_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_2_IN: SYNCH Position      */
+#define GIMA_CAP2_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos)                      /*!< GIMA CAP2_2_IN: SYNCH Mask          */
+#define GIMA_CAP2_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_2_IN: PULSE Position      */
+#define GIMA_CAP2_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos)                      /*!< GIMA CAP2_2_IN: PULSE Mask          */
+#define GIMA_CAP2_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_2_IN: SELECT Position     */
+#define GIMA_CAP2_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos)                     /*!< GIMA CAP2_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP2_3_IN  -----------------------------------------
+#define GIMA_CAP2_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_3_IN: INV Position        */
+#define GIMA_CAP2_3_IN_INV_Msk                                (0x01UL << GIMA_CAP2_3_IN_INV_Pos)                        /*!< GIMA CAP2_3_IN: INV Mask            */
+#define GIMA_CAP2_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_3_IN: EDGE Position       */
+#define GIMA_CAP2_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos)                       /*!< GIMA CAP2_3_IN: EDGE Mask           */
+#define GIMA_CAP2_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_3_IN: SYNCH Position      */
+#define GIMA_CAP2_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos)                      /*!< GIMA CAP2_3_IN: SYNCH Mask          */
+#define GIMA_CAP2_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_3_IN: PULSE Position      */
+#define GIMA_CAP2_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos)                      /*!< GIMA CAP2_3_IN: PULSE Mask          */
+#define GIMA_CAP2_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_3_IN: SELECT Position     */
+#define GIMA_CAP2_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos)                     /*!< GIMA CAP2_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_0_IN  -----------------------------------------
+#define GIMA_CAP3_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_0_IN: INV Position        */
+#define GIMA_CAP3_0_IN_INV_Msk                                (0x01UL << GIMA_CAP3_0_IN_INV_Pos)                        /*!< GIMA CAP3_0_IN: INV Mask            */
+#define GIMA_CAP3_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_0_IN: EDGE Position       */
+#define GIMA_CAP3_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos)                       /*!< GIMA CAP3_0_IN: EDGE Mask           */
+#define GIMA_CAP3_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_0_IN: SYNCH Position      */
+#define GIMA_CAP3_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos)                      /*!< GIMA CAP3_0_IN: SYNCH Mask          */
+#define GIMA_CAP3_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_0_IN: PULSE Position      */
+#define GIMA_CAP3_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos)                      /*!< GIMA CAP3_0_IN: PULSE Mask          */
+#define GIMA_CAP3_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_0_IN: SELECT Position     */
+#define GIMA_CAP3_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos)                     /*!< GIMA CAP3_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_1_IN  -----------------------------------------
+#define GIMA_CAP3_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_1_IN: INV Position        */
+#define GIMA_CAP3_1_IN_INV_Msk                                (0x01UL << GIMA_CAP3_1_IN_INV_Pos)                        /*!< GIMA CAP3_1_IN: INV Mask            */
+#define GIMA_CAP3_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_1_IN: EDGE Position       */
+#define GIMA_CAP3_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos)                       /*!< GIMA CAP3_1_IN: EDGE Mask           */
+#define GIMA_CAP3_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_1_IN: SYNCH Position      */
+#define GIMA_CAP3_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos)                      /*!< GIMA CAP3_1_IN: SYNCH Mask          */
+#define GIMA_CAP3_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_1_IN: PULSE Position      */
+#define GIMA_CAP3_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos)                      /*!< GIMA CAP3_1_IN: PULSE Mask          */
+#define GIMA_CAP3_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_1_IN: SELECT Position     */
+#define GIMA_CAP3_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos)                     /*!< GIMA CAP3_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_2_IN  -----------------------------------------
+#define GIMA_CAP3_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_2_IN: INV Position        */
+#define GIMA_CAP3_2_IN_INV_Msk                                (0x01UL << GIMA_CAP3_2_IN_INV_Pos)                        /*!< GIMA CAP3_2_IN: INV Mask            */
+#define GIMA_CAP3_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_2_IN: EDGE Position       */
+#define GIMA_CAP3_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos)                       /*!< GIMA CAP3_2_IN: EDGE Mask           */
+#define GIMA_CAP3_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_2_IN: SYNCH Position      */
+#define GIMA_CAP3_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos)                      /*!< GIMA CAP3_2_IN: SYNCH Mask          */
+#define GIMA_CAP3_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_2_IN: PULSE Position      */
+#define GIMA_CAP3_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos)                      /*!< GIMA CAP3_2_IN: PULSE Mask          */
+#define GIMA_CAP3_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_2_IN: SELECT Position     */
+#define GIMA_CAP3_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos)                     /*!< GIMA CAP3_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CAP3_3_IN  -----------------------------------------
+#define GIMA_CAP3_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_3_IN: INV Position        */
+#define GIMA_CAP3_3_IN_INV_Msk                                (0x01UL << GIMA_CAP3_3_IN_INV_Pos)                        /*!< GIMA CAP3_3_IN: INV Mask            */
+#define GIMA_CAP3_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_3_IN: EDGE Position       */
+#define GIMA_CAP3_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos)                       /*!< GIMA CAP3_3_IN: EDGE Mask           */
+#define GIMA_CAP3_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_3_IN: SYNCH Position      */
+#define GIMA_CAP3_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos)                      /*!< GIMA CAP3_3_IN: SYNCH Mask          */
+#define GIMA_CAP3_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_3_IN: PULSE Position      */
+#define GIMA_CAP3_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos)                      /*!< GIMA CAP3_3_IN: PULSE Mask          */
+#define GIMA_CAP3_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_3_IN: SELECT Position     */
+#define GIMA_CAP3_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos)                     /*!< GIMA CAP3_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_0_IN  -----------------------------------------
+#define GIMA_CTIN_0_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_0_IN: INV Position        */
+#define GIMA_CTIN_0_IN_INV_Msk                                (0x01UL << GIMA_CTIN_0_IN_INV_Pos)                        /*!< GIMA CTIN_0_IN: INV Mask            */
+#define GIMA_CTIN_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_0_IN: EDGE Position       */
+#define GIMA_CTIN_0_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos)                       /*!< GIMA CTIN_0_IN: EDGE Mask           */
+#define GIMA_CTIN_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_0_IN: SYNCH Position      */
+#define GIMA_CTIN_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos)                      /*!< GIMA CTIN_0_IN: SYNCH Mask          */
+#define GIMA_CTIN_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_0_IN: PULSE Position      */
+#define GIMA_CTIN_0_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos)                      /*!< GIMA CTIN_0_IN: PULSE Mask          */
+#define GIMA_CTIN_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_0_IN: SELECT Position     */
+#define GIMA_CTIN_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos)                     /*!< GIMA CTIN_0_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_1_IN  -----------------------------------------
+#define GIMA_CTIN_1_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_1_IN: INV Position        */
+#define GIMA_CTIN_1_IN_INV_Msk                                (0x01UL << GIMA_CTIN_1_IN_INV_Pos)                        /*!< GIMA CTIN_1_IN: INV Mask            */
+#define GIMA_CTIN_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_1_IN: EDGE Position       */
+#define GIMA_CTIN_1_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos)                       /*!< GIMA CTIN_1_IN: EDGE Mask           */
+#define GIMA_CTIN_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_1_IN: SYNCH Position      */
+#define GIMA_CTIN_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos)                      /*!< GIMA CTIN_1_IN: SYNCH Mask          */
+#define GIMA_CTIN_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_1_IN: PULSE Position      */
+#define GIMA_CTIN_1_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos)                      /*!< GIMA CTIN_1_IN: PULSE Mask          */
+#define GIMA_CTIN_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_1_IN: SELECT Position     */
+#define GIMA_CTIN_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos)                     /*!< GIMA CTIN_1_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_2_IN  -----------------------------------------
+#define GIMA_CTIN_2_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_2_IN: INV Position        */
+#define GIMA_CTIN_2_IN_INV_Msk                                (0x01UL << GIMA_CTIN_2_IN_INV_Pos)                        /*!< GIMA CTIN_2_IN: INV Mask            */
+#define GIMA_CTIN_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_2_IN: EDGE Position       */
+#define GIMA_CTIN_2_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos)                       /*!< GIMA CTIN_2_IN: EDGE Mask           */
+#define GIMA_CTIN_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_2_IN: SYNCH Position      */
+#define GIMA_CTIN_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos)                      /*!< GIMA CTIN_2_IN: SYNCH Mask          */
+#define GIMA_CTIN_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_2_IN: PULSE Position      */
+#define GIMA_CTIN_2_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos)                      /*!< GIMA CTIN_2_IN: PULSE Mask          */
+#define GIMA_CTIN_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_2_IN: SELECT Position     */
+#define GIMA_CTIN_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos)                     /*!< GIMA CTIN_2_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_3_IN  -----------------------------------------
+#define GIMA_CTIN_3_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_3_IN: INV Position        */
+#define GIMA_CTIN_3_IN_INV_Msk                                (0x01UL << GIMA_CTIN_3_IN_INV_Pos)                        /*!< GIMA CTIN_3_IN: INV Mask            */
+#define GIMA_CTIN_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_3_IN: EDGE Position       */
+#define GIMA_CTIN_3_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos)                       /*!< GIMA CTIN_3_IN: EDGE Mask           */
+#define GIMA_CTIN_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_3_IN: SYNCH Position      */
+#define GIMA_CTIN_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos)                      /*!< GIMA CTIN_3_IN: SYNCH Mask          */
+#define GIMA_CTIN_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_3_IN: PULSE Position      */
+#define GIMA_CTIN_3_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos)                      /*!< GIMA CTIN_3_IN: PULSE Mask          */
+#define GIMA_CTIN_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_3_IN: SELECT Position     */
+#define GIMA_CTIN_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos)                     /*!< GIMA CTIN_3_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_4_IN  -----------------------------------------
+#define GIMA_CTIN_4_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_4_IN: INV Position        */
+#define GIMA_CTIN_4_IN_INV_Msk                                (0x01UL << GIMA_CTIN_4_IN_INV_Pos)                        /*!< GIMA CTIN_4_IN: INV Mask            */
+#define GIMA_CTIN_4_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_4_IN: EDGE Position       */
+#define GIMA_CTIN_4_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos)                       /*!< GIMA CTIN_4_IN: EDGE Mask           */
+#define GIMA_CTIN_4_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_4_IN: SYNCH Position      */
+#define GIMA_CTIN_4_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos)                      /*!< GIMA CTIN_4_IN: SYNCH Mask          */
+#define GIMA_CTIN_4_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_4_IN: PULSE Position      */
+#define GIMA_CTIN_4_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos)                      /*!< GIMA CTIN_4_IN: PULSE Mask          */
+#define GIMA_CTIN_4_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_4_IN: SELECT Position     */
+#define GIMA_CTIN_4_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos)                     /*!< GIMA CTIN_4_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_5_IN  -----------------------------------------
+#define GIMA_CTIN_5_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_5_IN: INV Position        */
+#define GIMA_CTIN_5_IN_INV_Msk                                (0x01UL << GIMA_CTIN_5_IN_INV_Pos)                        /*!< GIMA CTIN_5_IN: INV Mask            */
+#define GIMA_CTIN_5_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_5_IN: EDGE Position       */
+#define GIMA_CTIN_5_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos)                       /*!< GIMA CTIN_5_IN: EDGE Mask           */
+#define GIMA_CTIN_5_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_5_IN: SYNCH Position      */
+#define GIMA_CTIN_5_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos)                      /*!< GIMA CTIN_5_IN: SYNCH Mask          */
+#define GIMA_CTIN_5_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_5_IN: PULSE Position      */
+#define GIMA_CTIN_5_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos)                      /*!< GIMA CTIN_5_IN: PULSE Mask          */
+#define GIMA_CTIN_5_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_5_IN: SELECT Position     */
+#define GIMA_CTIN_5_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos)                     /*!< GIMA CTIN_5_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_6_IN  -----------------------------------------
+#define GIMA_CTIN_6_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_6_IN: INV Position        */
+#define GIMA_CTIN_6_IN_INV_Msk                                (0x01UL << GIMA_CTIN_6_IN_INV_Pos)                        /*!< GIMA CTIN_6_IN: INV Mask            */
+#define GIMA_CTIN_6_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_6_IN: EDGE Position       */
+#define GIMA_CTIN_6_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos)                       /*!< GIMA CTIN_6_IN: EDGE Mask           */
+#define GIMA_CTIN_6_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_6_IN: SYNCH Position      */
+#define GIMA_CTIN_6_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos)                      /*!< GIMA CTIN_6_IN: SYNCH Mask          */
+#define GIMA_CTIN_6_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_6_IN: PULSE Position      */
+#define GIMA_CTIN_6_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos)                      /*!< GIMA CTIN_6_IN: PULSE Mask          */
+#define GIMA_CTIN_6_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_6_IN: SELECT Position     */
+#define GIMA_CTIN_6_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos)                     /*!< GIMA CTIN_6_IN: SELECT Mask         */
+
+// -------------------------------------  GIMA_CTIN_7_IN  -----------------------------------------
+#define GIMA_CTIN_7_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_7_IN: INV Position        */
+#define GIMA_CTIN_7_IN_INV_Msk                                (0x01UL << GIMA_CTIN_7_IN_INV_Pos)                        /*!< GIMA CTIN_7_IN: INV Mask            */
+#define GIMA_CTIN_7_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_7_IN: EDGE Position       */
+#define GIMA_CTIN_7_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos)                       /*!< GIMA CTIN_7_IN: EDGE Mask           */
+#define GIMA_CTIN_7_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_7_IN: SYNCH Position      */
+#define GIMA_CTIN_7_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos)                      /*!< GIMA CTIN_7_IN: SYNCH Mask          */
+#define GIMA_CTIN_7_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_7_IN: PULSE Position      */
+#define GIMA_CTIN_7_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos)                      /*!< GIMA CTIN_7_IN: PULSE Mask          */
+#define GIMA_CTIN_7_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_7_IN: SELECT Position     */
+#define GIMA_CTIN_7_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos)                     /*!< GIMA CTIN_7_IN: SELECT Mask         */
+
+// ----------------------------------  GIMA_VADC_TRIGGER_IN  --------------------------------------
+#define GIMA_VADC_TRIGGER_IN_INV_Pos                          0                                                         /*!< GIMA VADC_TRIGGER_IN: INV Position  */
+#define GIMA_VADC_TRIGGER_IN_INV_Msk                          (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos)                  /*!< GIMA VADC_TRIGGER_IN: INV Mask      */
+#define GIMA_VADC_TRIGGER_IN_EDGE_Pos                         1                                                         /*!< GIMA VADC_TRIGGER_IN: EDGE Position */
+#define GIMA_VADC_TRIGGER_IN_EDGE_Msk                         (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos)                 /*!< GIMA VADC_TRIGGER_IN: EDGE Mask     */
+#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos                        2                                                         /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */
+#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos)                /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask    */
+#define GIMA_VADC_TRIGGER_IN_PULSE_Pos                        3                                                         /*!< GIMA VADC_TRIGGER_IN: PULSE Position */
+#define GIMA_VADC_TRIGGER_IN_PULSE_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos)                /*!< GIMA VADC_TRIGGER_IN: PULSE Mask    */
+#define GIMA_VADC_TRIGGER_IN_SELECT_Pos                       4                                                         /*!< GIMA VADC_TRIGGER_IN: SELECT Position */
+#define GIMA_VADC_TRIGGER_IN_SELECT_Msk                       (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos)               /*!< GIMA VADC_TRIGGER_IN: SELECT Mask   */
+
+// ---------------------------------  GIMA_EVENTROUTER_13_IN  -------------------------------------
+#define GIMA_EVENTROUTER_13_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_13_IN: INV Position */
+#define GIMA_EVENTROUTER_13_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos)                /*!< GIMA EVENTROUTER_13_IN: INV Mask    */
+#define GIMA_EVENTROUTER_13_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_13_IN: EDGE Position */
+#define GIMA_EVENTROUTER_13_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_13_IN: EDGE Mask   */
+#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask  */
+#define GIMA_EVENTROUTER_13_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_13_IN: PULSE Position */
+#define GIMA_EVENTROUTER_13_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_13_IN: PULSE Mask  */
+#define GIMA_EVENTROUTER_13_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_13_IN: SELECT Position */
+#define GIMA_EVENTROUTER_13_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */
+
+// ---------------------------------  GIMA_EVENTROUTER_14_IN  -------------------------------------
+#define GIMA_EVENTROUTER_14_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_14_IN: INV Position */
+#define GIMA_EVENTROUTER_14_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos)                /*!< GIMA EVENTROUTER_14_IN: INV Mask    */
+#define GIMA_EVENTROUTER_14_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_14_IN: EDGE Position */
+#define GIMA_EVENTROUTER_14_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_14_IN: EDGE Mask   */
+#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask  */
+#define GIMA_EVENTROUTER_14_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_14_IN: PULSE Position */
+#define GIMA_EVENTROUTER_14_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_14_IN: PULSE Mask  */
+#define GIMA_EVENTROUTER_14_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_14_IN: SELECT Position */
+#define GIMA_EVENTROUTER_14_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */
+
+// ---------------------------------  GIMA_EVENTROUTER_16_IN  -------------------------------------
+#define GIMA_EVENTROUTER_16_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_16_IN: INV Position */
+#define GIMA_EVENTROUTER_16_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos)                /*!< GIMA EVENTROUTER_16_IN: INV Mask    */
+#define GIMA_EVENTROUTER_16_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_16_IN: EDGE Position */
+#define GIMA_EVENTROUTER_16_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_16_IN: EDGE Mask   */
+#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask  */
+#define GIMA_EVENTROUTER_16_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_16_IN: PULSE Position */
+#define GIMA_EVENTROUTER_16_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_16_IN: PULSE Mask  */
+#define GIMA_EVENTROUTER_16_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_16_IN: SELECT Position */
+#define GIMA_EVENTROUTER_16_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */
+
+// ------------------------------------  GIMA_ADCSTART0_IN  ---------------------------------------
+#define GIMA_ADCSTART0_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART0_IN: INV Position     */
+#define GIMA_ADCSTART0_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART0_IN_INV_Pos)                     /*!< GIMA ADCSTART0_IN: INV Mask         */
+#define GIMA_ADCSTART0_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART0_IN: EDGE Position    */
+#define GIMA_ADCSTART0_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos)                    /*!< GIMA ADCSTART0_IN: EDGE Mask        */
+#define GIMA_ADCSTART0_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART0_IN: SYNCH Position   */
+#define GIMA_ADCSTART0_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART0_IN: SYNCH Mask       */
+#define GIMA_ADCSTART0_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART0_IN: PULSE Position   */
+#define GIMA_ADCSTART0_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos)                   /*!< GIMA ADCSTART0_IN: PULSE Mask       */
+#define GIMA_ADCSTART0_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART0_IN: SELECT Position  */
+#define GIMA_ADCSTART0_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos)                  /*!< GIMA ADCSTART0_IN: SELECT Mask      */
+
+// ------------------------------------  GIMA_ADCSTART1_IN  ---------------------------------------
+#define GIMA_ADCSTART1_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART1_IN: INV Position     */
+#define GIMA_ADCSTART1_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART1_IN_INV_Pos)                     /*!< GIMA ADCSTART1_IN: INV Mask         */
+#define GIMA_ADCSTART1_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART1_IN: EDGE Position    */
+#define GIMA_ADCSTART1_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos)                    /*!< GIMA ADCSTART1_IN: EDGE Mask        */
+#define GIMA_ADCSTART1_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART1_IN: SYNCH Position   */
+#define GIMA_ADCSTART1_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART1_IN: SYNCH Mask       */
+#define GIMA_ADCSTART1_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART1_IN: PULSE Position   */
+#define GIMA_ADCSTART1_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos)                   /*!< GIMA ADCSTART1_IN: PULSE Mask       */
+#define GIMA_ADCSTART1_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART1_IN: SELECT Position  */
+#define GIMA_ADCSTART1_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos)                  /*!< GIMA ADCSTART1_IN: SELECT Mask      */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  DAC Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  DAC_CR  ---------------------------------------------
+#define DAC_CR_VALUE_Pos                                      6                                                         /*!< DAC CR: VALUE Position              */
+#define DAC_CR_VALUE_Msk                                      (0x000003ffUL << DAC_CR_VALUE_Pos)                        /*!< DAC CR: VALUE Mask                  */
+#define DAC_CR_BIAS_Pos                                       16                                                        /*!< DAC CR: BIAS Position               */
+#define DAC_CR_BIAS_Msk                                       (0x01UL << DAC_CR_BIAS_Pos)                               /*!< DAC CR: BIAS Mask                   */
+
+// ----------------------------------------  DAC_CTRL  --------------------------------------------
+#define DAC_CTRL_INT_DMA_REQ_Pos                              0                                                         /*!< DAC CTRL: INT_DMA_REQ Position      */
+#define DAC_CTRL_INT_DMA_REQ_Msk                              (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos)                      /*!< DAC CTRL: INT_DMA_REQ Mask          */
+#define DAC_CTRL_DBLBUF_ENA_Pos                               1                                                         /*!< DAC CTRL: DBLBUF_ENA Position       */
+#define DAC_CTRL_DBLBUF_ENA_Msk                               (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos)                       /*!< DAC CTRL: DBLBUF_ENA Mask           */
+#define DAC_CTRL_CNT_ENA_Pos                                  2                                                         /*!< DAC CTRL: CNT_ENA Position          */
+#define DAC_CTRL_CNT_ENA_Msk                                  (0x01UL << DAC_CTRL_CNT_ENA_Pos)                          /*!< DAC CTRL: CNT_ENA Mask              */
+#define DAC_CTRL_DMA_ENA_Pos                                  3                                                         /*!< DAC CTRL: DMA_ENA Position          */
+#define DAC_CTRL_DMA_ENA_Msk                                  (0x01UL << DAC_CTRL_DMA_ENA_Pos)                          /*!< DAC CTRL: DMA_ENA Mask              */
+
+// ---------------------------------------  DAC_CNTVAL  -------------------------------------------
+#define DAC_CNTVAL_VALUE_Pos                                  0                                                         /*!< DAC CNTVAL: VALUE Position          */
+#define DAC_CNTVAL_VALUE_Msk                                  (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos)                    /*!< DAC CNTVAL: VALUE Mask              */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                C_CAN0 Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------  C_CAN0_CNTL  ------------------------------------------
+#define C_CAN0_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN0 CNTL: INIT Position          */
+#define C_CAN0_CNTL_INIT_Msk                                  (0x01UL << C_CAN0_CNTL_INIT_Pos)                          /*!< C_CAN0 CNTL: INIT Mask              */
+#define C_CAN0_CNTL_IE_Pos                                    1                                                         /*!< C_CAN0 CNTL: IE Position            */
+#define C_CAN0_CNTL_IE_Msk                                    (0x01UL << C_CAN0_CNTL_IE_Pos)                            /*!< C_CAN0 CNTL: IE Mask                */
+#define C_CAN0_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN0 CNTL: SIE Position           */
+#define C_CAN0_CNTL_SIE_Msk                                   (0x01UL << C_CAN0_CNTL_SIE_Pos)                           /*!< C_CAN0 CNTL: SIE Mask               */
+#define C_CAN0_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN0 CNTL: EIE Position           */
+#define C_CAN0_CNTL_EIE_Msk                                   (0x01UL << C_CAN0_CNTL_EIE_Pos)                           /*!< C_CAN0 CNTL: EIE Mask               */
+#define C_CAN0_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN0 CNTL: DAR Position           */
+#define C_CAN0_CNTL_DAR_Msk                                   (0x01UL << C_CAN0_CNTL_DAR_Pos)                           /*!< C_CAN0 CNTL: DAR Mask               */
+#define C_CAN0_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN0 CNTL: CCE Position           */
+#define C_CAN0_CNTL_CCE_Msk                                   (0x01UL << C_CAN0_CNTL_CCE_Pos)                           /*!< C_CAN0 CNTL: CCE Mask               */
+#define C_CAN0_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN0 CNTL: TEST Position          */
+#define C_CAN0_CNTL_TEST_Msk                                  (0x01UL << C_CAN0_CNTL_TEST_Pos)                          /*!< C_CAN0 CNTL: TEST Mask              */
+
+// ---------------------------------------  C_CAN0_STAT  ------------------------------------------
+#define C_CAN0_STAT_LEC_Pos                                   0                                                         /*!< C_CAN0 STAT: LEC Position           */
+#define C_CAN0_STAT_LEC_Msk                                   (0x07UL << C_CAN0_STAT_LEC_Pos)                           /*!< C_CAN0 STAT: LEC Mask               */
+#define C_CAN0_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN0 STAT: TXOK Position          */
+#define C_CAN0_STAT_TXOK_Msk                                  (0x01UL << C_CAN0_STAT_TXOK_Pos)                          /*!< C_CAN0 STAT: TXOK Mask              */
+#define C_CAN0_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN0 STAT: RXOK Position          */
+#define C_CAN0_STAT_RXOK_Msk                                  (0x01UL << C_CAN0_STAT_RXOK_Pos)                          /*!< C_CAN0 STAT: RXOK Mask              */
+#define C_CAN0_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN0 STAT: EPASS Position         */
+#define C_CAN0_STAT_EPASS_Msk                                 (0x01UL << C_CAN0_STAT_EPASS_Pos)                         /*!< C_CAN0 STAT: EPASS Mask             */
+#define C_CAN0_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN0 STAT: EWARN Position         */
+#define C_CAN0_STAT_EWARN_Msk                                 (0x01UL << C_CAN0_STAT_EWARN_Pos)                         /*!< C_CAN0 STAT: EWARN Mask             */
+#define C_CAN0_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN0 STAT: BOFF Position          */
+#define C_CAN0_STAT_BOFF_Msk                                  (0x01UL << C_CAN0_STAT_BOFF_Pos)                          /*!< C_CAN0 STAT: BOFF Mask              */
+
+// ----------------------------------------  C_CAN0_EC  -------------------------------------------
+#define C_CAN0_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN0 EC: TEC_7_0 Position         */
+#define C_CAN0_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos)                   /*!< C_CAN0 EC: TEC_7_0 Mask             */
+#define C_CAN0_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN0 EC: REC_6_0 Position         */
+#define C_CAN0_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN0_EC_REC_6_0_Pos)                         /*!< C_CAN0 EC: REC_6_0 Mask             */
+#define C_CAN0_EC_RP_Pos                                      15                                                        /*!< C_CAN0 EC: RP Position              */
+#define C_CAN0_EC_RP_Msk                                      (0x01UL << C_CAN0_EC_RP_Pos)                              /*!< C_CAN0 EC: RP Mask                  */
+
+// ----------------------------------------  C_CAN0_BT  -------------------------------------------
+#define C_CAN0_BT_BRP_Pos                                     0                                                         /*!< C_CAN0 BT: BRP Position             */
+#define C_CAN0_BT_BRP_Msk                                     (0x3fUL << C_CAN0_BT_BRP_Pos)                             /*!< C_CAN0 BT: BRP Mask                 */
+#define C_CAN0_BT_SJW_Pos                                     6                                                         /*!< C_CAN0 BT: SJW Position             */
+#define C_CAN0_BT_SJW_Msk                                     (0x03UL << C_CAN0_BT_SJW_Pos)                             /*!< C_CAN0 BT: SJW Mask                 */
+#define C_CAN0_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN0 BT: TSEG1 Position           */
+#define C_CAN0_BT_TSEG1_Msk                                   (0x0fUL << C_CAN0_BT_TSEG1_Pos)                           /*!< C_CAN0 BT: TSEG1 Mask               */
+#define C_CAN0_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN0 BT: TSEG2 Position           */
+#define C_CAN0_BT_TSEG2_Msk                                   (0x07UL << C_CAN0_BT_TSEG2_Pos)                           /*!< C_CAN0 BT: TSEG2 Mask               */
+
+// ---------------------------------------  C_CAN0_INT  -------------------------------------------
+#define C_CAN0_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN0 INT: INTID15_0 Position      */
+#define C_CAN0_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos)                /*!< C_CAN0 INT: INTID15_0 Mask          */
+
+// ---------------------------------------  C_CAN0_TEST  ------------------------------------------
+#define C_CAN0_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN0 TEST: BASIC Position         */
+#define C_CAN0_TEST_BASIC_Msk                                 (0x01UL << C_CAN0_TEST_BASIC_Pos)                         /*!< C_CAN0 TEST: BASIC Mask             */
+#define C_CAN0_TEST_SILENT_Pos                                3                                                         /*!< C_CAN0 TEST: SILENT Position        */
+#define C_CAN0_TEST_SILENT_Msk                                (0x01UL << C_CAN0_TEST_SILENT_Pos)                        /*!< C_CAN0 TEST: SILENT Mask            */
+#define C_CAN0_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN0 TEST: LBACK Position         */
+#define C_CAN0_TEST_LBACK_Msk                                 (0x01UL << C_CAN0_TEST_LBACK_Pos)                         /*!< C_CAN0 TEST: LBACK Mask             */
+#define C_CAN0_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN0 TEST: TX1_0 Position         */
+#define C_CAN0_TEST_TX1_0_Msk                                 (0x03UL << C_CAN0_TEST_TX1_0_Pos)                         /*!< C_CAN0 TEST: TX1_0 Mask             */
+#define C_CAN0_TEST_RX_Pos                                    7                                                         /*!< C_CAN0 TEST: RX Position            */
+#define C_CAN0_TEST_RX_Msk                                    (0x01UL << C_CAN0_TEST_RX_Pos)                            /*!< C_CAN0 TEST: RX Mask                */
+
+// ---------------------------------------  C_CAN0_BRPE  ------------------------------------------
+#define C_CAN0_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN0 BRPE: BRPE Position          */
+#define C_CAN0_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN0_BRPE_BRPE_Pos)                          /*!< C_CAN0 BRPE: BRPE Mask              */
+
+// ------------------------------------  C_CAN0_IF1_CMDREQ  ---------------------------------------
+#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */
+#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask     */
+#define C_CAN0_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF1_CMDREQ: BUSY Position    */
+#define C_CAN0_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF1_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN0_IF1_CMDMSK_R  --------------------------------------
+#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */
+#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask    */
+#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */
+#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask    */
+#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */
+#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */
+#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position  */
+#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask      */
+#define C_CAN0_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_R: ARB Position   */
+#define C_CAN0_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask       */
+#define C_CAN0_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_R: MASK Position  */
+#define C_CAN0_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask      */
+#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */
+#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask     */
+
+// -----------------------------------  C_CAN0_IF1_CMDMSK_W  --------------------------------------
+#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */
+#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask    */
+#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */
+#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask    */
+#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */
+#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask    */
+#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */
+#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position  */
+#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask      */
+#define C_CAN0_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_W: ARB Position   */
+#define C_CAN0_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask       */
+#define C_CAN0_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_W: MASK Position  */
+#define C_CAN0_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask      */
+#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */
+#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask     */
+
+// -------------------------------------  C_CAN0_IF1_MSK1  ----------------------------------------
+#define C_CAN0_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF1_MSK1: MSK15_0 Position   */
+#define C_CAN0_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN0_IF1_MSK2  ----------------------------------------
+#define C_CAN0_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF1_MSK2: MSK28_16 Position  */
+#define C_CAN0_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask      */
+#define C_CAN0_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF1_MSK2: MDIR Position      */
+#define C_CAN0_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF1_MSK2: MDIR Mask          */
+#define C_CAN0_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF1_MSK2: MXTD Position      */
+#define C_CAN0_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF1_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN0_IF1_ARB1  ----------------------------------------
+#define C_CAN0_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF1_ARB1: ID15_0 Position    */
+#define C_CAN0_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF1_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN0_IF1_ARB2  ----------------------------------------
+#define C_CAN0_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF1_ARB2: ID28_16 Position   */
+#define C_CAN0_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF1_ARB2: ID28_16 Mask       */
+#define C_CAN0_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF1_ARB2: DIR Position       */
+#define C_CAN0_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos)                       /*!< C_CAN0 IF1_ARB2: DIR Mask           */
+#define C_CAN0_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF1_ARB2: XTD Position       */
+#define C_CAN0_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos)                       /*!< C_CAN0 IF1_ARB2: XTD Mask           */
+#define C_CAN0_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF1_ARB2: MSGVAL Position    */
+#define C_CAN0_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF1_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN0_IF1_MCTRL  ----------------------------------------
+#define C_CAN0_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position   */
+#define C_CAN0_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask       */
+#define C_CAN0_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF1_MCTRL: EOB Position      */
+#define C_CAN0_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF1_MCTRL: EOB Mask          */
+#define C_CAN0_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF1_MCTRL: TXRQST Position   */
+#define C_CAN0_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF1_MCTRL: TXRQST Mask       */
+#define C_CAN0_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF1_MCTRL: RMTEN Position    */
+#define C_CAN0_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF1_MCTRL: RMTEN Mask        */
+#define C_CAN0_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF1_MCTRL: RXIE Position     */
+#define C_CAN0_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: RXIE Mask         */
+#define C_CAN0_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF1_MCTRL: TXIE Position     */
+#define C_CAN0_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: TXIE Mask         */
+#define C_CAN0_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF1_MCTRL: UMASK Position    */
+#define C_CAN0_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF1_MCTRL: UMASK Mask        */
+#define C_CAN0_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF1_MCTRL: INTPND Position   */
+#define C_CAN0_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF1_MCTRL: INTPND Mask       */
+#define C_CAN0_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF1_MCTRL: MSGLST Position   */
+#define C_CAN0_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF1_MCTRL: MSGLST Mask       */
+#define C_CAN0_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF1_MCTRL: NEWDAT Position   */
+#define C_CAN0_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN0_IF1_DA1  -----------------------------------------
+#define C_CAN0_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF1_DA1: DATA0 Position      */
+#define C_CAN0_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos)                /*!< C_CAN0 IF1_DA1: DATA0 Mask          */
+#define C_CAN0_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF1_DA1: DATA1 Position      */
+#define C_CAN0_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos)                /*!< C_CAN0 IF1_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN0_IF1_DA2  -----------------------------------------
+#define C_CAN0_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF1_DA2: DATA2 Position      */
+#define C_CAN0_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos)                /*!< C_CAN0 IF1_DA2: DATA2 Mask          */
+#define C_CAN0_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF1_DA2: DATA3 Position      */
+#define C_CAN0_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos)                /*!< C_CAN0 IF1_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN0_IF1_DB1  -----------------------------------------
+#define C_CAN0_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF1_DB1: DATA4 Position      */
+#define C_CAN0_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos)                /*!< C_CAN0 IF1_DB1: DATA4 Mask          */
+#define C_CAN0_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF1_DB1: DATA5 Position      */
+#define C_CAN0_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos)                /*!< C_CAN0 IF1_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN0_IF1_DB2  -----------------------------------------
+#define C_CAN0_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF1_DB2: DATA6 Position      */
+#define C_CAN0_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos)                /*!< C_CAN0 IF1_DB2: DATA6 Mask          */
+#define C_CAN0_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF1_DB2: DATA7 Position      */
+#define C_CAN0_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos)                /*!< C_CAN0 IF1_DB2: DATA7 Mask          */
+
+// ------------------------------------  C_CAN0_IF2_CMDREQ  ---------------------------------------
+#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */
+#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask     */
+#define C_CAN0_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF2_CMDREQ: BUSY Position    */
+#define C_CAN0_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF2_CMDREQ: BUSY Mask        */
+
+// -----------------------------------  C_CAN0_IF2_CMDMSK_R  --------------------------------------
+#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */
+#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask    */
+#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */
+#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask    */
+#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */
+#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask    */
+#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */
+#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position  */
+#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask      */
+#define C_CAN0_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_R: ARB Position   */
+#define C_CAN0_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask       */
+#define C_CAN0_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_R: MASK Position  */
+#define C_CAN0_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask      */
+#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */
+#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask     */
+
+// -----------------------------------  C_CAN0_IF2_CMDMSK_W  --------------------------------------
+#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */
+#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask    */
+#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */
+#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask    */
+#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */
+#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask    */
+#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */
+#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position  */
+#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask      */
+#define C_CAN0_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_W: ARB Position   */
+#define C_CAN0_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask       */
+#define C_CAN0_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_W: MASK Position  */
+#define C_CAN0_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask      */
+#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */
+#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask     */
+
+// -------------------------------------  C_CAN0_IF2_MSK1  ----------------------------------------
+#define C_CAN0_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF2_MSK1: MSK15_0 Position   */
+#define C_CAN0_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask       */
+
+// -------------------------------------  C_CAN0_IF2_MSK2  ----------------------------------------
+#define C_CAN0_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF2_MSK2: MSK28_16 Position  */
+#define C_CAN0_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask      */
+#define C_CAN0_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF2_MSK2: MDIR Position      */
+#define C_CAN0_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF2_MSK2: MDIR Mask          */
+#define C_CAN0_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF2_MSK2: MXTD Position      */
+#define C_CAN0_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF2_MSK2: MXTD Mask          */
+
+// -------------------------------------  C_CAN0_IF2_ARB1  ----------------------------------------
+#define C_CAN0_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF2_ARB1: ID15_0 Position    */
+#define C_CAN0_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF2_ARB1: ID15_0 Mask        */
+
+// -------------------------------------  C_CAN0_IF2_ARB2  ----------------------------------------
+#define C_CAN0_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF2_ARB2: ID28_16 Position   */
+#define C_CAN0_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF2_ARB2: ID28_16 Mask       */
+#define C_CAN0_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF2_ARB2: DIR Position       */
+#define C_CAN0_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos)                       /*!< C_CAN0 IF2_ARB2: DIR Mask           */
+#define C_CAN0_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF2_ARB2: XTD Position       */
+#define C_CAN0_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos)                       /*!< C_CAN0 IF2_ARB2: XTD Mask           */
+#define C_CAN0_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF2_ARB2: MSGVAL Position    */
+#define C_CAN0_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF2_ARB2: MSGVAL Mask        */
+
+// ------------------------------------  C_CAN0_IF2_MCTRL  ----------------------------------------
+#define C_CAN0_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position   */
+#define C_CAN0_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask       */
+#define C_CAN0_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF2_MCTRL: EOB Position      */
+#define C_CAN0_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF2_MCTRL: EOB Mask          */
+#define C_CAN0_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF2_MCTRL: TXRQST Position   */
+#define C_CAN0_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF2_MCTRL: TXRQST Mask       */
+#define C_CAN0_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF2_MCTRL: RMTEN Position    */
+#define C_CAN0_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF2_MCTRL: RMTEN Mask        */
+#define C_CAN0_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF2_MCTRL: RXIE Position     */
+#define C_CAN0_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: RXIE Mask         */
+#define C_CAN0_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF2_MCTRL: TXIE Position     */
+#define C_CAN0_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: TXIE Mask         */
+#define C_CAN0_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF2_MCTRL: UMASK Position    */
+#define C_CAN0_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF2_MCTRL: UMASK Mask        */
+#define C_CAN0_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF2_MCTRL: INTPND Position   */
+#define C_CAN0_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF2_MCTRL: INTPND Mask       */
+#define C_CAN0_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF2_MCTRL: MSGLST Position   */
+#define C_CAN0_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF2_MCTRL: MSGLST Mask       */
+#define C_CAN0_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF2_MCTRL: NEWDAT Position   */
+#define C_CAN0_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask       */
+
+// -------------------------------------  C_CAN0_IF2_DA1  -----------------------------------------
+#define C_CAN0_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF2_DA1: DATA0 Position      */
+#define C_CAN0_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos)                /*!< C_CAN0 IF2_DA1: DATA0 Mask          */
+#define C_CAN0_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF2_DA1: DATA1 Position      */
+#define C_CAN0_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos)                /*!< C_CAN0 IF2_DA1: DATA1 Mask          */
+
+// -------------------------------------  C_CAN0_IF2_DA2  -----------------------------------------
+#define C_CAN0_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF2_DA2: DATA2 Position      */
+#define C_CAN0_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos)                /*!< C_CAN0 IF2_DA2: DATA2 Mask          */
+#define C_CAN0_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF2_DA2: DATA3 Position      */
+#define C_CAN0_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos)                /*!< C_CAN0 IF2_DA2: DATA3 Mask          */
+
+// -------------------------------------  C_CAN0_IF2_DB1  -----------------------------------------
+#define C_CAN0_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF2_DB1: DATA4 Position      */
+#define C_CAN0_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos)                /*!< C_CAN0 IF2_DB1: DATA4 Mask          */
+#define C_CAN0_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF2_DB1: DATA5 Position      */
+#define C_CAN0_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos)                /*!< C_CAN0 IF2_DB1: DATA5 Mask          */
+
+// -------------------------------------  C_CAN0_IF2_DB2  -----------------------------------------
+#define C_CAN0_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF2_DB2: DATA6 Position      */
+#define C_CAN0_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos)                /*!< C_CAN0 IF2_DB2: DATA6 Mask          */
+#define C_CAN0_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF2_DB2: DATA7 Position      */
+#define C_CAN0_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos)                /*!< C_CAN0 IF2_DB2: DATA7 Mask          */
+
+// --------------------------------------  C_CAN0_TXREQ1  -----------------------------------------
+#define C_CAN0_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN0 TXREQ1: TXRQST16_1 Position  */
+#define C_CAN0_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask      */
+
+// --------------------------------------  C_CAN0_TXREQ2  -----------------------------------------
+#define C_CAN0_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */
+#define C_CAN0_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask     */
+
+// ---------------------------------------  C_CAN0_ND1  -------------------------------------------
+#define C_CAN0_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN0 ND1: NEWDAT16_1 Position     */
+#define C_CAN0_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos)               /*!< C_CAN0 ND1: NEWDAT16_1 Mask         */
+
+// ---------------------------------------  C_CAN0_ND2  -------------------------------------------
+#define C_CAN0_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN0 ND2: NEWDAT32_17 Position    */
+#define C_CAN0_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos)              /*!< C_CAN0 ND2: NEWDAT32_17 Mask        */
+
+// ---------------------------------------  C_CAN0_IR1  -------------------------------------------
+#define C_CAN0_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN0 IR1: INTPND16_1 Position     */
+#define C_CAN0_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos)               /*!< C_CAN0 IR1: INTPND16_1 Mask         */
+
+// ---------------------------------------  C_CAN0_IR2  -------------------------------------------
+#define C_CAN0_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN0 IR2: INTPND32_17 Position    */
+#define C_CAN0_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos)              /*!< C_CAN0 IR2: INTPND32_17 Mask        */
+
+// --------------------------------------  C_CAN0_MSGV1  ------------------------------------------
+#define C_CAN0_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN0 MSGV1: MSGVAL16_1 Position   */
+#define C_CAN0_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask       */
+
+// --------------------------------------  C_CAN0_MSGV2  ------------------------------------------
+#define C_CAN0_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN0 MSGV2: MSGVAL32_17 Position  */
+#define C_CAN0_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask      */
+
+// --------------------------------------  C_CAN0_CLKDIV  -----------------------------------------
+#define C_CAN0_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN0 CLKDIV: CLKDIVVAL Position   */
+#define C_CAN0_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask       */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 ADC0 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  ADC0_CR  --------------------------------------------
+#define ADC0_CR_SEL_Pos                                       0                                                         /*!< ADC0 CR: SEL Position               */
+#define ADC0_CR_SEL_Msk                                       (0x000000ffUL << ADC0_CR_SEL_Pos)                         /*!< ADC0 CR: SEL Mask                   */
+#define ADC0_CR_CLKDIV_Pos                                    8                                                         /*!< ADC0 CR: CLKDIV Position            */
+#define ADC0_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC0_CR_CLKDIV_Pos)                      /*!< ADC0 CR: CLKDIV Mask                */
+#define ADC0_CR_BURST_Pos                                     16                                                        /*!< ADC0 CR: BURST Position             */
+#define ADC0_CR_BURST_Msk                                     (0x01UL << ADC0_CR_BURST_Pos)                             /*!< ADC0 CR: BURST Mask                 */
+#define ADC0_CR_CLKS_Pos                                      17                                                        /*!< ADC0 CR: CLKS Position              */
+#define ADC0_CR_CLKS_Msk                                      (0x07UL << ADC0_CR_CLKS_Pos)                              /*!< ADC0 CR: CLKS Mask                  */
+#define ADC0_CR_PDN_Pos                                       21                                                        /*!< ADC0 CR: PDN Position               */
+#define ADC0_CR_PDN_Msk                                       (0x01UL << ADC0_CR_PDN_Pos)                               /*!< ADC0 CR: PDN Mask                   */
+#define ADC0_CR_START_Pos                                     24                                                        /*!< ADC0 CR: START Position             */
+#define ADC0_CR_START_Msk                                     (0x07UL << ADC0_CR_START_Pos)                             /*!< ADC0 CR: START Mask                 */
+#define ADC0_CR_EDGE_Pos                                      27                                                        /*!< ADC0 CR: EDGE Position              */
+#define ADC0_CR_EDGE_Msk                                      (0x01UL << ADC0_CR_EDGE_Pos)                              /*!< ADC0 CR: EDGE Mask                  */
+
+// ----------------------------------------  ADC0_GDR  --------------------------------------------
+#define ADC0_GDR_V_VREF_Pos                                   6                                                         /*!< ADC0 GDR: V_VREF Position           */
+#define ADC0_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC0_GDR_V_VREF_Pos)                     /*!< ADC0 GDR: V_VREF Mask               */
+#define ADC0_GDR_CHN_Pos                                      24                                                        /*!< ADC0 GDR: CHN Position              */
+#define ADC0_GDR_CHN_Msk                                      (0x07UL << ADC0_GDR_CHN_Pos)                              /*!< ADC0 GDR: CHN Mask                  */
+#define ADC0_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC0 GDR: OVERRUN Position          */
+#define ADC0_GDR_OVERRUN_Msk                                  (0x01UL << ADC0_GDR_OVERRUN_Pos)                          /*!< ADC0 GDR: OVERRUN Mask              */
+#define ADC0_GDR_DONE_Pos                                     31                                                        /*!< ADC0 GDR: DONE Position             */
+#define ADC0_GDR_DONE_Msk                                     (0x01UL << ADC0_GDR_DONE_Pos)                             /*!< ADC0 GDR: DONE Mask                 */
+
+// ---------------------------------------  ADC0_INTEN  -------------------------------------------
+#define ADC0_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC0 INTEN: ADINTEN Position        */
+#define ADC0_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos)                  /*!< ADC0 INTEN: ADINTEN Mask            */
+#define ADC0_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC0 INTEN: ADGINTEN Position       */
+#define ADC0_INTEN_ADGINTEN_Msk                               (0x01UL << ADC0_INTEN_ADGINTEN_Pos)                       /*!< ADC0 INTEN: ADGINTEN Mask           */
+
+// ----------------------------------------  ADC0_DR0  --------------------------------------------
+#define ADC0_DR0_V_VREF_Pos                                   6                                                         /*!< ADC0 DR0: V_VREF Position           */
+#define ADC0_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR0_V_VREF_Pos)                     /*!< ADC0 DR0: V_VREF Mask               */
+#define ADC0_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR0: OVERRUN Position          */
+#define ADC0_DR0_OVERRUN_Msk                                  (0x01UL << ADC0_DR0_OVERRUN_Pos)                          /*!< ADC0 DR0: OVERRUN Mask              */
+#define ADC0_DR0_DONE_Pos                                     31                                                        /*!< ADC0 DR0: DONE Position             */
+#define ADC0_DR0_DONE_Msk                                     (0x01UL << ADC0_DR0_DONE_Pos)                             /*!< ADC0 DR0: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR1  --------------------------------------------
+#define ADC0_DR1_V_VREF_Pos                                   6                                                         /*!< ADC0 DR1: V_VREF Position           */
+#define ADC0_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR1_V_VREF_Pos)                     /*!< ADC0 DR1: V_VREF Mask               */
+#define ADC0_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR1: OVERRUN Position          */
+#define ADC0_DR1_OVERRUN_Msk                                  (0x01UL << ADC0_DR1_OVERRUN_Pos)                          /*!< ADC0 DR1: OVERRUN Mask              */
+#define ADC0_DR1_DONE_Pos                                     31                                                        /*!< ADC0 DR1: DONE Position             */
+#define ADC0_DR1_DONE_Msk                                     (0x01UL << ADC0_DR1_DONE_Pos)                             /*!< ADC0 DR1: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR2  --------------------------------------------
+#define ADC0_DR2_V_VREF_Pos                                   6                                                         /*!< ADC0 DR2: V_VREF Position           */
+#define ADC0_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR2_V_VREF_Pos)                     /*!< ADC0 DR2: V_VREF Mask               */
+#define ADC0_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR2: OVERRUN Position          */
+#define ADC0_DR2_OVERRUN_Msk                                  (0x01UL << ADC0_DR2_OVERRUN_Pos)                          /*!< ADC0 DR2: OVERRUN Mask              */
+#define ADC0_DR2_DONE_Pos                                     31                                                        /*!< ADC0 DR2: DONE Position             */
+#define ADC0_DR2_DONE_Msk                                     (0x01UL << ADC0_DR2_DONE_Pos)                             /*!< ADC0 DR2: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR3  --------------------------------------------
+#define ADC0_DR3_V_VREF_Pos                                   6                                                         /*!< ADC0 DR3: V_VREF Position           */
+#define ADC0_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR3_V_VREF_Pos)                     /*!< ADC0 DR3: V_VREF Mask               */
+#define ADC0_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR3: OVERRUN Position          */
+#define ADC0_DR3_OVERRUN_Msk                                  (0x01UL << ADC0_DR3_OVERRUN_Pos)                          /*!< ADC0 DR3: OVERRUN Mask              */
+#define ADC0_DR3_DONE_Pos                                     31                                                        /*!< ADC0 DR3: DONE Position             */
+#define ADC0_DR3_DONE_Msk                                     (0x01UL << ADC0_DR3_DONE_Pos)                             /*!< ADC0 DR3: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR4  --------------------------------------------
+#define ADC0_DR4_V_VREF_Pos                                   6                                                         /*!< ADC0 DR4: V_VREF Position           */
+#define ADC0_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR4_V_VREF_Pos)                     /*!< ADC0 DR4: V_VREF Mask               */
+#define ADC0_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR4: OVERRUN Position          */
+#define ADC0_DR4_OVERRUN_Msk                                  (0x01UL << ADC0_DR4_OVERRUN_Pos)                          /*!< ADC0 DR4: OVERRUN Mask              */
+#define ADC0_DR4_DONE_Pos                                     31                                                        /*!< ADC0 DR4: DONE Position             */
+#define ADC0_DR4_DONE_Msk                                     (0x01UL << ADC0_DR4_DONE_Pos)                             /*!< ADC0 DR4: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR5  --------------------------------------------
+#define ADC0_DR5_V_VREF_Pos                                   6                                                         /*!< ADC0 DR5: V_VREF Position           */
+#define ADC0_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR5_V_VREF_Pos)                     /*!< ADC0 DR5: V_VREF Mask               */
+#define ADC0_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR5: OVERRUN Position          */
+#define ADC0_DR5_OVERRUN_Msk                                  (0x01UL << ADC0_DR5_OVERRUN_Pos)                          /*!< ADC0 DR5: OVERRUN Mask              */
+#define ADC0_DR5_DONE_Pos                                     31                                                        /*!< ADC0 DR5: DONE Position             */
+#define ADC0_DR5_DONE_Msk                                     (0x01UL << ADC0_DR5_DONE_Pos)                             /*!< ADC0 DR5: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR6  --------------------------------------------
+#define ADC0_DR6_V_VREF_Pos                                   6                                                         /*!< ADC0 DR6: V_VREF Position           */
+#define ADC0_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR6_V_VREF_Pos)                     /*!< ADC0 DR6: V_VREF Mask               */
+#define ADC0_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR6: OVERRUN Position          */
+#define ADC0_DR6_OVERRUN_Msk                                  (0x01UL << ADC0_DR6_OVERRUN_Pos)                          /*!< ADC0 DR6: OVERRUN Mask              */
+#define ADC0_DR6_DONE_Pos                                     31                                                        /*!< ADC0 DR6: DONE Position             */
+#define ADC0_DR6_DONE_Msk                                     (0x01UL << ADC0_DR6_DONE_Pos)                             /*!< ADC0 DR6: DONE Mask                 */
+
+// ----------------------------------------  ADC0_DR7  --------------------------------------------
+#define ADC0_DR7_V_VREF_Pos                                   6                                                         /*!< ADC0 DR7: V_VREF Position           */
+#define ADC0_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR7_V_VREF_Pos)                     /*!< ADC0 DR7: V_VREF Mask               */
+#define ADC0_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR7: OVERRUN Position          */
+#define ADC0_DR7_OVERRUN_Msk                                  (0x01UL << ADC0_DR7_OVERRUN_Pos)                          /*!< ADC0 DR7: OVERRUN Mask              */
+#define ADC0_DR7_DONE_Pos                                     31                                                        /*!< ADC0 DR7: DONE Position             */
+#define ADC0_DR7_DONE_Msk                                     (0x01UL << ADC0_DR7_DONE_Pos)                             /*!< ADC0 DR7: DONE Mask                 */
+
+// ----------------------------------------  ADC0_STAT  -------------------------------------------
+#define ADC0_STAT_DONE_Pos                                    0                                                         /*!< ADC0 STAT: DONE Position            */
+#define ADC0_STAT_DONE_Msk                                    (0x000000ffUL << ADC0_STAT_DONE_Pos)                      /*!< ADC0 STAT: DONE Mask                */
+#define ADC0_STAT_OVERUN_Pos                                  8                                                         /*!< ADC0 STAT: OVERUN Position          */
+#define ADC0_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC0_STAT_OVERUN_Pos)                    /*!< ADC0 STAT: OVERUN Mask              */
+#define ADC0_STAT_ADINT_Pos                                   16                                                        /*!< ADC0 STAT: ADINT Position           */
+#define ADC0_STAT_ADINT_Msk                                   (0x01UL << ADC0_STAT_ADINT_Pos)                           /*!< ADC0 STAT: ADINT Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 ADC1 Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  ADC1_CR  --------------------------------------------
+#define ADC1_CR_SEL_Pos                                       0                                                         /*!< ADC1 CR: SEL Position               */
+#define ADC1_CR_SEL_Msk                                       (0x000000ffUL << ADC1_CR_SEL_Pos)                         /*!< ADC1 CR: SEL Mask                   */
+#define ADC1_CR_CLKDIV_Pos                                    8                                                         /*!< ADC1 CR: CLKDIV Position            */
+#define ADC1_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC1_CR_CLKDIV_Pos)                      /*!< ADC1 CR: CLKDIV Mask                */
+#define ADC1_CR_BURST_Pos                                     16                                                        /*!< ADC1 CR: BURST Position             */
+#define ADC1_CR_BURST_Msk                                     (0x01UL << ADC1_CR_BURST_Pos)                             /*!< ADC1 CR: BURST Mask                 */
+#define ADC1_CR_CLKS_Pos                                      17                                                        /*!< ADC1 CR: CLKS Position              */
+#define ADC1_CR_CLKS_Msk                                      (0x07UL << ADC1_CR_CLKS_Pos)                              /*!< ADC1 CR: CLKS Mask                  */
+#define ADC1_CR_PDN_Pos                                       21                                                        /*!< ADC1 CR: PDN Position               */
+#define ADC1_CR_PDN_Msk                                       (0x01UL << ADC1_CR_PDN_Pos)                               /*!< ADC1 CR: PDN Mask                   */
+#define ADC1_CR_START_Pos                                     24                                                        /*!< ADC1 CR: START Position             */
+#define ADC1_CR_START_Msk                                     (0x07UL << ADC1_CR_START_Pos)                             /*!< ADC1 CR: START Mask                 */
+#define ADC1_CR_EDGE_Pos                                      27                                                        /*!< ADC1 CR: EDGE Position              */
+#define ADC1_CR_EDGE_Msk                                      (0x01UL << ADC1_CR_EDGE_Pos)                              /*!< ADC1 CR: EDGE Mask                  */
+
+// ----------------------------------------  ADC1_GDR  --------------------------------------------
+#define ADC1_GDR_V_VREF_Pos                                   6                                                         /*!< ADC1 GDR: V_VREF Position           */
+#define ADC1_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC1_GDR_V_VREF_Pos)                     /*!< ADC1 GDR: V_VREF Mask               */
+#define ADC1_GDR_CHN_Pos                                      24                                                        /*!< ADC1 GDR: CHN Position              */
+#define ADC1_GDR_CHN_Msk                                      (0x07UL << ADC1_GDR_CHN_Pos)                              /*!< ADC1 GDR: CHN Mask                  */
+#define ADC1_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC1 GDR: OVERRUN Position          */
+#define ADC1_GDR_OVERRUN_Msk                                  (0x01UL << ADC1_GDR_OVERRUN_Pos)                          /*!< ADC1 GDR: OVERRUN Mask              */
+#define ADC1_GDR_DONE_Pos                                     31                                                        /*!< ADC1 GDR: DONE Position             */
+#define ADC1_GDR_DONE_Msk                                     (0x01UL << ADC1_GDR_DONE_Pos)                             /*!< ADC1 GDR: DONE Mask                 */
+
+// ---------------------------------------  ADC1_INTEN  -------------------------------------------
+#define ADC1_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC1 INTEN: ADINTEN Position        */
+#define ADC1_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos)                  /*!< ADC1 INTEN: ADINTEN Mask            */
+#define ADC1_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC1 INTEN: ADGINTEN Position       */
+#define ADC1_INTEN_ADGINTEN_Msk                               (0x01UL << ADC1_INTEN_ADGINTEN_Pos)                       /*!< ADC1 INTEN: ADGINTEN Mask           */
+
+// ----------------------------------------  ADC1_DR0  --------------------------------------------
+#define ADC1_DR0_V_VREF_Pos                                   6                                                         /*!< ADC1 DR0: V_VREF Position           */
+#define ADC1_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR0_V_VREF_Pos)                     /*!< ADC1 DR0: V_VREF Mask               */
+#define ADC1_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR0: OVERRUN Position          */
+#define ADC1_DR0_OVERRUN_Msk                                  (0x01UL << ADC1_DR0_OVERRUN_Pos)                          /*!< ADC1 DR0: OVERRUN Mask              */
+#define ADC1_DR0_DONE_Pos                                     31                                                        /*!< ADC1 DR0: DONE Position             */
+#define ADC1_DR0_DONE_Msk                                     (0x01UL << ADC1_DR0_DONE_Pos)                             /*!< ADC1 DR0: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR1  --------------------------------------------
+#define ADC1_DR1_V_VREF_Pos                                   6                                                         /*!< ADC1 DR1: V_VREF Position           */
+#define ADC1_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR1_V_VREF_Pos)                     /*!< ADC1 DR1: V_VREF Mask               */
+#define ADC1_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR1: OVERRUN Position          */
+#define ADC1_DR1_OVERRUN_Msk                                  (0x01UL << ADC1_DR1_OVERRUN_Pos)                          /*!< ADC1 DR1: OVERRUN Mask              */
+#define ADC1_DR1_DONE_Pos                                     31                                                        /*!< ADC1 DR1: DONE Position             */
+#define ADC1_DR1_DONE_Msk                                     (0x01UL << ADC1_DR1_DONE_Pos)                             /*!< ADC1 DR1: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR2  --------------------------------------------
+#define ADC1_DR2_V_VREF_Pos                                   6                                                         /*!< ADC1 DR2: V_VREF Position           */
+#define ADC1_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR2_V_VREF_Pos)                     /*!< ADC1 DR2: V_VREF Mask               */
+#define ADC1_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR2: OVERRUN Position          */
+#define ADC1_DR2_OVERRUN_Msk                                  (0x01UL << ADC1_DR2_OVERRUN_Pos)                          /*!< ADC1 DR2: OVERRUN Mask              */
+#define ADC1_DR2_DONE_Pos                                     31                                                        /*!< ADC1 DR2: DONE Position             */
+#define ADC1_DR2_DONE_Msk                                     (0x01UL << ADC1_DR2_DONE_Pos)                             /*!< ADC1 DR2: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR3  --------------------------------------------
+#define ADC1_DR3_V_VREF_Pos                                   6                                                         /*!< ADC1 DR3: V_VREF Position           */
+#define ADC1_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR3_V_VREF_Pos)                     /*!< ADC1 DR3: V_VREF Mask               */
+#define ADC1_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR3: OVERRUN Position          */
+#define ADC1_DR3_OVERRUN_Msk                                  (0x01UL << ADC1_DR3_OVERRUN_Pos)                          /*!< ADC1 DR3: OVERRUN Mask              */
+#define ADC1_DR3_DONE_Pos                                     31                                                        /*!< ADC1 DR3: DONE Position             */
+#define ADC1_DR3_DONE_Msk                                     (0x01UL << ADC1_DR3_DONE_Pos)                             /*!< ADC1 DR3: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR4  --------------------------------------------
+#define ADC1_DR4_V_VREF_Pos                                   6                                                         /*!< ADC1 DR4: V_VREF Position           */
+#define ADC1_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR4_V_VREF_Pos)                     /*!< ADC1 DR4: V_VREF Mask               */
+#define ADC1_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR4: OVERRUN Position          */
+#define ADC1_DR4_OVERRUN_Msk                                  (0x01UL << ADC1_DR4_OVERRUN_Pos)                          /*!< ADC1 DR4: OVERRUN Mask              */
+#define ADC1_DR4_DONE_Pos                                     31                                                        /*!< ADC1 DR4: DONE Position             */
+#define ADC1_DR4_DONE_Msk                                     (0x01UL << ADC1_DR4_DONE_Pos)                             /*!< ADC1 DR4: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR5  --------------------------------------------
+#define ADC1_DR5_V_VREF_Pos                                   6                                                         /*!< ADC1 DR5: V_VREF Position           */
+#define ADC1_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR5_V_VREF_Pos)                     /*!< ADC1 DR5: V_VREF Mask               */
+#define ADC1_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR5: OVERRUN Position          */
+#define ADC1_DR5_OVERRUN_Msk                                  (0x01UL << ADC1_DR5_OVERRUN_Pos)                          /*!< ADC1 DR5: OVERRUN Mask              */
+#define ADC1_DR5_DONE_Pos                                     31                                                        /*!< ADC1 DR5: DONE Position             */
+#define ADC1_DR5_DONE_Msk                                     (0x01UL << ADC1_DR5_DONE_Pos)                             /*!< ADC1 DR5: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR6  --------------------------------------------
+#define ADC1_DR6_V_VREF_Pos                                   6                                                         /*!< ADC1 DR6: V_VREF Position           */
+#define ADC1_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR6_V_VREF_Pos)                     /*!< ADC1 DR6: V_VREF Mask               */
+#define ADC1_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR6: OVERRUN Position          */
+#define ADC1_DR6_OVERRUN_Msk                                  (0x01UL << ADC1_DR6_OVERRUN_Pos)                          /*!< ADC1 DR6: OVERRUN Mask              */
+#define ADC1_DR6_DONE_Pos                                     31                                                        /*!< ADC1 DR6: DONE Position             */
+#define ADC1_DR6_DONE_Msk                                     (0x01UL << ADC1_DR6_DONE_Pos)                             /*!< ADC1 DR6: DONE Mask                 */
+
+// ----------------------------------------  ADC1_DR7  --------------------------------------------
+#define ADC1_DR7_V_VREF_Pos                                   6                                                         /*!< ADC1 DR7: V_VREF Position           */
+#define ADC1_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR7_V_VREF_Pos)                     /*!< ADC1 DR7: V_VREF Mask               */
+#define ADC1_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR7: OVERRUN Position          */
+#define ADC1_DR7_OVERRUN_Msk                                  (0x01UL << ADC1_DR7_OVERRUN_Pos)                          /*!< ADC1 DR7: OVERRUN Mask              */
+#define ADC1_DR7_DONE_Pos                                     31                                                        /*!< ADC1 DR7: DONE Position             */
+#define ADC1_DR7_DONE_Msk                                     (0x01UL << ADC1_DR7_DONE_Pos)                             /*!< ADC1 DR7: DONE Mask                 */
+
+// ----------------------------------------  ADC1_STAT  -------------------------------------------
+#define ADC1_STAT_DONE_Pos                                    0                                                         /*!< ADC1 STAT: DONE Position            */
+#define ADC1_STAT_DONE_Msk                                    (0x000000ffUL << ADC1_STAT_DONE_Pos)                      /*!< ADC1 STAT: DONE Mask                */
+#define ADC1_STAT_OVERUN_Pos                                  8                                                         /*!< ADC1 STAT: OVERUN Position          */
+#define ADC1_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC1_STAT_OVERUN_Pos)                    /*!< ADC1 STAT: OVERUN Mask              */
+#define ADC1_STAT_ADINT_Pos                                   16                                                        /*!< ADC1 STAT: ADINT Position           */
+#define ADC1_STAT_ADINT_Msk                                   (0x01UL << ADC1_STAT_ADINT_Pos)                           /*!< ADC1 STAT: ADINT Mask               */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                               GPIO_PORT Position & Mask                              -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------  GPIO_PORT_B0  ------------------------------------------
+#define GPIO_PORT_B0_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B0: PBYTE Position        */
+#define GPIO_PORT_B0_PBYTE_Msk                                (0x01UL << GPIO_PORT_B0_PBYTE_Pos)                        /*!< GPIO_PORT B0: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B1  ------------------------------------------
+#define GPIO_PORT_B1_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B1: PBYTE Position        */
+#define GPIO_PORT_B1_PBYTE_Msk                                (0x01UL << GPIO_PORT_B1_PBYTE_Pos)                        /*!< GPIO_PORT B1: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B2  ------------------------------------------
+#define GPIO_PORT_B2_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B2: PBYTE Position        */
+#define GPIO_PORT_B2_PBYTE_Msk                                (0x01UL << GPIO_PORT_B2_PBYTE_Pos)                        /*!< GPIO_PORT B2: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B3  ------------------------------------------
+#define GPIO_PORT_B3_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B3: PBYTE Position        */
+#define GPIO_PORT_B3_PBYTE_Msk                                (0x01UL << GPIO_PORT_B3_PBYTE_Pos)                        /*!< GPIO_PORT B3: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B4  ------------------------------------------
+#define GPIO_PORT_B4_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B4: PBYTE Position        */
+#define GPIO_PORT_B4_PBYTE_Msk                                (0x01UL << GPIO_PORT_B4_PBYTE_Pos)                        /*!< GPIO_PORT B4: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B5  ------------------------------------------
+#define GPIO_PORT_B5_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B5: PBYTE Position        */
+#define GPIO_PORT_B5_PBYTE_Msk                                (0x01UL << GPIO_PORT_B5_PBYTE_Pos)                        /*!< GPIO_PORT B5: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B6  ------------------------------------------
+#define GPIO_PORT_B6_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B6: PBYTE Position        */
+#define GPIO_PORT_B6_PBYTE_Msk                                (0x01UL << GPIO_PORT_B6_PBYTE_Pos)                        /*!< GPIO_PORT B6: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B7  ------------------------------------------
+#define GPIO_PORT_B7_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B7: PBYTE Position        */
+#define GPIO_PORT_B7_PBYTE_Msk                                (0x01UL << GPIO_PORT_B7_PBYTE_Pos)                        /*!< GPIO_PORT B7: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B8  ------------------------------------------
+#define GPIO_PORT_B8_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B8: PBYTE Position        */
+#define GPIO_PORT_B8_PBYTE_Msk                                (0x01UL << GPIO_PORT_B8_PBYTE_Pos)                        /*!< GPIO_PORT B8: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B9  ------------------------------------------
+#define GPIO_PORT_B9_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B9: PBYTE Position        */
+#define GPIO_PORT_B9_PBYTE_Msk                                (0x01UL << GPIO_PORT_B9_PBYTE_Pos)                        /*!< GPIO_PORT B9: PBYTE Mask            */
+
+// --------------------------------------  GPIO_PORT_B10  -----------------------------------------
+#define GPIO_PORT_B10_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B10: PBYTE Position       */
+#define GPIO_PORT_B10_PBYTE_Msk                               (0x01UL << GPIO_PORT_B10_PBYTE_Pos)                       /*!< GPIO_PORT B10: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B11  -----------------------------------------
+#define GPIO_PORT_B11_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B11: PBYTE Position       */
+#define GPIO_PORT_B11_PBYTE_Msk                               (0x01UL << GPIO_PORT_B11_PBYTE_Pos)                       /*!< GPIO_PORT B11: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B12  -----------------------------------------
+#define GPIO_PORT_B12_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B12: PBYTE Position       */
+#define GPIO_PORT_B12_PBYTE_Msk                               (0x01UL << GPIO_PORT_B12_PBYTE_Pos)                       /*!< GPIO_PORT B12: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B13  -----------------------------------------
+#define GPIO_PORT_B13_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B13: PBYTE Position       */
+#define GPIO_PORT_B13_PBYTE_Msk                               (0x01UL << GPIO_PORT_B13_PBYTE_Pos)                       /*!< GPIO_PORT B13: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B14  -----------------------------------------
+#define GPIO_PORT_B14_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B14: PBYTE Position       */
+#define GPIO_PORT_B14_PBYTE_Msk                               (0x01UL << GPIO_PORT_B14_PBYTE_Pos)                       /*!< GPIO_PORT B14: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B15  -----------------------------------------
+#define GPIO_PORT_B15_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B15: PBYTE Position       */
+#define GPIO_PORT_B15_PBYTE_Msk                               (0x01UL << GPIO_PORT_B15_PBYTE_Pos)                       /*!< GPIO_PORT B15: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B16  -----------------------------------------
+#define GPIO_PORT_B16_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B16: PBYTE Position       */
+#define GPIO_PORT_B16_PBYTE_Msk                               (0x01UL << GPIO_PORT_B16_PBYTE_Pos)                       /*!< GPIO_PORT B16: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B17  -----------------------------------------
+#define GPIO_PORT_B17_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B17: PBYTE Position       */
+#define GPIO_PORT_B17_PBYTE_Msk                               (0x01UL << GPIO_PORT_B17_PBYTE_Pos)                       /*!< GPIO_PORT B17: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B18  -----------------------------------------
+#define GPIO_PORT_B18_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B18: PBYTE Position       */
+#define GPIO_PORT_B18_PBYTE_Msk                               (0x01UL << GPIO_PORT_B18_PBYTE_Pos)                       /*!< GPIO_PORT B18: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B19  -----------------------------------------
+#define GPIO_PORT_B19_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B19: PBYTE Position       */
+#define GPIO_PORT_B19_PBYTE_Msk                               (0x01UL << GPIO_PORT_B19_PBYTE_Pos)                       /*!< GPIO_PORT B19: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B20  -----------------------------------------
+#define GPIO_PORT_B20_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B20: PBYTE Position       */
+#define GPIO_PORT_B20_PBYTE_Msk                               (0x01UL << GPIO_PORT_B20_PBYTE_Pos)                       /*!< GPIO_PORT B20: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B21  -----------------------------------------
+#define GPIO_PORT_B21_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B21: PBYTE Position       */
+#define GPIO_PORT_B21_PBYTE_Msk                               (0x01UL << GPIO_PORT_B21_PBYTE_Pos)                       /*!< GPIO_PORT B21: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B22  -----------------------------------------
+#define GPIO_PORT_B22_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B22: PBYTE Position       */
+#define GPIO_PORT_B22_PBYTE_Msk                               (0x01UL << GPIO_PORT_B22_PBYTE_Pos)                       /*!< GPIO_PORT B22: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B23  -----------------------------------------
+#define GPIO_PORT_B23_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B23: PBYTE Position       */
+#define GPIO_PORT_B23_PBYTE_Msk                               (0x01UL << GPIO_PORT_B23_PBYTE_Pos)                       /*!< GPIO_PORT B23: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B24  -----------------------------------------
+#define GPIO_PORT_B24_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B24: PBYTE Position       */
+#define GPIO_PORT_B24_PBYTE_Msk                               (0x01UL << GPIO_PORT_B24_PBYTE_Pos)                       /*!< GPIO_PORT B24: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B25  -----------------------------------------
+#define GPIO_PORT_B25_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B25: PBYTE Position       */
+#define GPIO_PORT_B25_PBYTE_Msk                               (0x01UL << GPIO_PORT_B25_PBYTE_Pos)                       /*!< GPIO_PORT B25: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B26  -----------------------------------------
+#define GPIO_PORT_B26_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B26: PBYTE Position       */
+#define GPIO_PORT_B26_PBYTE_Msk                               (0x01UL << GPIO_PORT_B26_PBYTE_Pos)                       /*!< GPIO_PORT B26: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B27  -----------------------------------------
+#define GPIO_PORT_B27_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B27: PBYTE Position       */
+#define GPIO_PORT_B27_PBYTE_Msk                               (0x01UL << GPIO_PORT_B27_PBYTE_Pos)                       /*!< GPIO_PORT B27: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B28  -----------------------------------------
+#define GPIO_PORT_B28_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B28: PBYTE Position       */
+#define GPIO_PORT_B28_PBYTE_Msk                               (0x01UL << GPIO_PORT_B28_PBYTE_Pos)                       /*!< GPIO_PORT B28: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B29  -----------------------------------------
+#define GPIO_PORT_B29_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B29: PBYTE Position       */
+#define GPIO_PORT_B29_PBYTE_Msk                               (0x01UL << GPIO_PORT_B29_PBYTE_Pos)                       /*!< GPIO_PORT B29: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B30  -----------------------------------------
+#define GPIO_PORT_B30_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B30: PBYTE Position       */
+#define GPIO_PORT_B30_PBYTE_Msk                               (0x01UL << GPIO_PORT_B30_PBYTE_Pos)                       /*!< GPIO_PORT B30: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B31  -----------------------------------------
+#define GPIO_PORT_B31_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B31: PBYTE Position       */
+#define GPIO_PORT_B31_PBYTE_Msk                               (0x01UL << GPIO_PORT_B31_PBYTE_Pos)                       /*!< GPIO_PORT B31: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B32  -----------------------------------------
+#define GPIO_PORT_B32_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B32: PBYTE Position       */
+#define GPIO_PORT_B32_PBYTE_Msk                               (0x01UL << GPIO_PORT_B32_PBYTE_Pos)                       /*!< GPIO_PORT B32: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B33  -----------------------------------------
+#define GPIO_PORT_B33_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B33: PBYTE Position       */
+#define GPIO_PORT_B33_PBYTE_Msk                               (0x01UL << GPIO_PORT_B33_PBYTE_Pos)                       /*!< GPIO_PORT B33: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B34  -----------------------------------------
+#define GPIO_PORT_B34_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B34: PBYTE Position       */
+#define GPIO_PORT_B34_PBYTE_Msk                               (0x01UL << GPIO_PORT_B34_PBYTE_Pos)                       /*!< GPIO_PORT B34: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B35  -----------------------------------------
+#define GPIO_PORT_B35_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B35: PBYTE Position       */
+#define GPIO_PORT_B35_PBYTE_Msk                               (0x01UL << GPIO_PORT_B35_PBYTE_Pos)                       /*!< GPIO_PORT B35: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B36  -----------------------------------------
+#define GPIO_PORT_B36_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B36: PBYTE Position       */
+#define GPIO_PORT_B36_PBYTE_Msk                               (0x01UL << GPIO_PORT_B36_PBYTE_Pos)                       /*!< GPIO_PORT B36: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B37  -----------------------------------------
+#define GPIO_PORT_B37_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B37: PBYTE Position       */
+#define GPIO_PORT_B37_PBYTE_Msk                               (0x01UL << GPIO_PORT_B37_PBYTE_Pos)                       /*!< GPIO_PORT B37: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B38  -----------------------------------------
+#define GPIO_PORT_B38_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B38: PBYTE Position       */
+#define GPIO_PORT_B38_PBYTE_Msk                               (0x01UL << GPIO_PORT_B38_PBYTE_Pos)                       /*!< GPIO_PORT B38: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B39  -----------------------------------------
+#define GPIO_PORT_B39_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B39: PBYTE Position       */
+#define GPIO_PORT_B39_PBYTE_Msk                               (0x01UL << GPIO_PORT_B39_PBYTE_Pos)                       /*!< GPIO_PORT B39: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B40  -----------------------------------------
+#define GPIO_PORT_B40_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B40: PBYTE Position       */
+#define GPIO_PORT_B40_PBYTE_Msk                               (0x01UL << GPIO_PORT_B40_PBYTE_Pos)                       /*!< GPIO_PORT B40: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B41  -----------------------------------------
+#define GPIO_PORT_B41_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B41: PBYTE Position       */
+#define GPIO_PORT_B41_PBYTE_Msk                               (0x01UL << GPIO_PORT_B41_PBYTE_Pos)                       /*!< GPIO_PORT B41: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B42  -----------------------------------------
+#define GPIO_PORT_B42_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B42: PBYTE Position       */
+#define GPIO_PORT_B42_PBYTE_Msk                               (0x01UL << GPIO_PORT_B42_PBYTE_Pos)                       /*!< GPIO_PORT B42: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B43  -----------------------------------------
+#define GPIO_PORT_B43_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B43: PBYTE Position       */
+#define GPIO_PORT_B43_PBYTE_Msk                               (0x01UL << GPIO_PORT_B43_PBYTE_Pos)                       /*!< GPIO_PORT B43: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B44  -----------------------------------------
+#define GPIO_PORT_B44_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B44: PBYTE Position       */
+#define GPIO_PORT_B44_PBYTE_Msk                               (0x01UL << GPIO_PORT_B44_PBYTE_Pos)                       /*!< GPIO_PORT B44: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B45  -----------------------------------------
+#define GPIO_PORT_B45_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B45: PBYTE Position       */
+#define GPIO_PORT_B45_PBYTE_Msk                               (0x01UL << GPIO_PORT_B45_PBYTE_Pos)                       /*!< GPIO_PORT B45: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B46  -----------------------------------------
+#define GPIO_PORT_B46_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B46: PBYTE Position       */
+#define GPIO_PORT_B46_PBYTE_Msk                               (0x01UL << GPIO_PORT_B46_PBYTE_Pos)                       /*!< GPIO_PORT B46: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B47  -----------------------------------------
+#define GPIO_PORT_B47_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B47: PBYTE Position       */
+#define GPIO_PORT_B47_PBYTE_Msk                               (0x01UL << GPIO_PORT_B47_PBYTE_Pos)                       /*!< GPIO_PORT B47: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B48  -----------------------------------------
+#define GPIO_PORT_B48_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B48: PBYTE Position       */
+#define GPIO_PORT_B48_PBYTE_Msk                               (0x01UL << GPIO_PORT_B48_PBYTE_Pos)                       /*!< GPIO_PORT B48: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B49  -----------------------------------------
+#define GPIO_PORT_B49_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B49: PBYTE Position       */
+#define GPIO_PORT_B49_PBYTE_Msk                               (0x01UL << GPIO_PORT_B49_PBYTE_Pos)                       /*!< GPIO_PORT B49: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B50  -----------------------------------------
+#define GPIO_PORT_B50_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B50: PBYTE Position       */
+#define GPIO_PORT_B50_PBYTE_Msk                               (0x01UL << GPIO_PORT_B50_PBYTE_Pos)                       /*!< GPIO_PORT B50: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B51  -----------------------------------------
+#define GPIO_PORT_B51_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B51: PBYTE Position       */
+#define GPIO_PORT_B51_PBYTE_Msk                               (0x01UL << GPIO_PORT_B51_PBYTE_Pos)                       /*!< GPIO_PORT B51: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B52  -----------------------------------------
+#define GPIO_PORT_B52_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B52: PBYTE Position       */
+#define GPIO_PORT_B52_PBYTE_Msk                               (0x01UL << GPIO_PORT_B52_PBYTE_Pos)                       /*!< GPIO_PORT B52: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B53  -----------------------------------------
+#define GPIO_PORT_B53_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B53: PBYTE Position       */
+#define GPIO_PORT_B53_PBYTE_Msk                               (0x01UL << GPIO_PORT_B53_PBYTE_Pos)                       /*!< GPIO_PORT B53: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B54  -----------------------------------------
+#define GPIO_PORT_B54_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B54: PBYTE Position       */
+#define GPIO_PORT_B54_PBYTE_Msk                               (0x01UL << GPIO_PORT_B54_PBYTE_Pos)                       /*!< GPIO_PORT B54: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B55  -----------------------------------------
+#define GPIO_PORT_B55_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B55: PBYTE Position       */
+#define GPIO_PORT_B55_PBYTE_Msk                               (0x01UL << GPIO_PORT_B55_PBYTE_Pos)                       /*!< GPIO_PORT B55: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B56  -----------------------------------------
+#define GPIO_PORT_B56_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B56: PBYTE Position       */
+#define GPIO_PORT_B56_PBYTE_Msk                               (0x01UL << GPIO_PORT_B56_PBYTE_Pos)                       /*!< GPIO_PORT B56: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B57  -----------------------------------------
+#define GPIO_PORT_B57_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B57: PBYTE Position       */
+#define GPIO_PORT_B57_PBYTE_Msk                               (0x01UL << GPIO_PORT_B57_PBYTE_Pos)                       /*!< GPIO_PORT B57: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B58  -----------------------------------------
+#define GPIO_PORT_B58_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B58: PBYTE Position       */
+#define GPIO_PORT_B58_PBYTE_Msk                               (0x01UL << GPIO_PORT_B58_PBYTE_Pos)                       /*!< GPIO_PORT B58: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B59  -----------------------------------------
+#define GPIO_PORT_B59_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B59: PBYTE Position       */
+#define GPIO_PORT_B59_PBYTE_Msk                               (0x01UL << GPIO_PORT_B59_PBYTE_Pos)                       /*!< GPIO_PORT B59: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B60  -----------------------------------------
+#define GPIO_PORT_B60_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B60: PBYTE Position       */
+#define GPIO_PORT_B60_PBYTE_Msk                               (0x01UL << GPIO_PORT_B60_PBYTE_Pos)                       /*!< GPIO_PORT B60: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B61  -----------------------------------------
+#define GPIO_PORT_B61_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B61: PBYTE Position       */
+#define GPIO_PORT_B61_PBYTE_Msk                               (0x01UL << GPIO_PORT_B61_PBYTE_Pos)                       /*!< GPIO_PORT B61: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B62  -----------------------------------------
+#define GPIO_PORT_B62_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B62: PBYTE Position       */
+#define GPIO_PORT_B62_PBYTE_Msk                               (0x01UL << GPIO_PORT_B62_PBYTE_Pos)                       /*!< GPIO_PORT B62: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B63  -----------------------------------------
+#define GPIO_PORT_B63_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B63: PBYTE Position       */
+#define GPIO_PORT_B63_PBYTE_Msk                               (0x01UL << GPIO_PORT_B63_PBYTE_Pos)                       /*!< GPIO_PORT B63: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B64  -----------------------------------------
+#define GPIO_PORT_B64_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B64: PBYTE Position       */
+#define GPIO_PORT_B64_PBYTE_Msk                               (0x01UL << GPIO_PORT_B64_PBYTE_Pos)                       /*!< GPIO_PORT B64: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B65  -----------------------------------------
+#define GPIO_PORT_B65_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B65: PBYTE Position       */
+#define GPIO_PORT_B65_PBYTE_Msk                               (0x01UL << GPIO_PORT_B65_PBYTE_Pos)                       /*!< GPIO_PORT B65: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B66  -----------------------------------------
+#define GPIO_PORT_B66_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B66: PBYTE Position       */
+#define GPIO_PORT_B66_PBYTE_Msk                               (0x01UL << GPIO_PORT_B66_PBYTE_Pos)                       /*!< GPIO_PORT B66: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B67  -----------------------------------------
+#define GPIO_PORT_B67_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B67: PBYTE Position       */
+#define GPIO_PORT_B67_PBYTE_Msk                               (0x01UL << GPIO_PORT_B67_PBYTE_Pos)                       /*!< GPIO_PORT B67: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B68  -----------------------------------------
+#define GPIO_PORT_B68_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B68: PBYTE Position       */
+#define GPIO_PORT_B68_PBYTE_Msk                               (0x01UL << GPIO_PORT_B68_PBYTE_Pos)                       /*!< GPIO_PORT B68: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B69  -----------------------------------------
+#define GPIO_PORT_B69_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B69: PBYTE Position       */
+#define GPIO_PORT_B69_PBYTE_Msk                               (0x01UL << GPIO_PORT_B69_PBYTE_Pos)                       /*!< GPIO_PORT B69: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B70  -----------------------------------------
+#define GPIO_PORT_B70_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B70: PBYTE Position       */
+#define GPIO_PORT_B70_PBYTE_Msk                               (0x01UL << GPIO_PORT_B70_PBYTE_Pos)                       /*!< GPIO_PORT B70: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B71  -----------------------------------------
+#define GPIO_PORT_B71_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B71: PBYTE Position       */
+#define GPIO_PORT_B71_PBYTE_Msk                               (0x01UL << GPIO_PORT_B71_PBYTE_Pos)                       /*!< GPIO_PORT B71: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B72  -----------------------------------------
+#define GPIO_PORT_B72_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B72: PBYTE Position       */
+#define GPIO_PORT_B72_PBYTE_Msk                               (0x01UL << GPIO_PORT_B72_PBYTE_Pos)                       /*!< GPIO_PORT B72: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B73  -----------------------------------------
+#define GPIO_PORT_B73_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B73: PBYTE Position       */
+#define GPIO_PORT_B73_PBYTE_Msk                               (0x01UL << GPIO_PORT_B73_PBYTE_Pos)                       /*!< GPIO_PORT B73: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B74  -----------------------------------------
+#define GPIO_PORT_B74_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B74: PBYTE Position       */
+#define GPIO_PORT_B74_PBYTE_Msk                               (0x01UL << GPIO_PORT_B74_PBYTE_Pos)                       /*!< GPIO_PORT B74: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B75  -----------------------------------------
+#define GPIO_PORT_B75_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B75: PBYTE Position       */
+#define GPIO_PORT_B75_PBYTE_Msk                               (0x01UL << GPIO_PORT_B75_PBYTE_Pos)                       /*!< GPIO_PORT B75: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B76  -----------------------------------------
+#define GPIO_PORT_B76_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B76: PBYTE Position       */
+#define GPIO_PORT_B76_PBYTE_Msk                               (0x01UL << GPIO_PORT_B76_PBYTE_Pos)                       /*!< GPIO_PORT B76: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B77  -----------------------------------------
+#define GPIO_PORT_B77_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B77: PBYTE Position       */
+#define GPIO_PORT_B77_PBYTE_Msk                               (0x01UL << GPIO_PORT_B77_PBYTE_Pos)                       /*!< GPIO_PORT B77: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B78  -----------------------------------------
+#define GPIO_PORT_B78_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B78: PBYTE Position       */
+#define GPIO_PORT_B78_PBYTE_Msk                               (0x01UL << GPIO_PORT_B78_PBYTE_Pos)                       /*!< GPIO_PORT B78: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B79  -----------------------------------------
+#define GPIO_PORT_B79_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B79: PBYTE Position       */
+#define GPIO_PORT_B79_PBYTE_Msk                               (0x01UL << GPIO_PORT_B79_PBYTE_Pos)                       /*!< GPIO_PORT B79: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B80  -----------------------------------------
+#define GPIO_PORT_B80_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B80: PBYTE Position       */
+#define GPIO_PORT_B80_PBYTE_Msk                               (0x01UL << GPIO_PORT_B80_PBYTE_Pos)                       /*!< GPIO_PORT B80: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B81  -----------------------------------------
+#define GPIO_PORT_B81_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B81: PBYTE Position       */
+#define GPIO_PORT_B81_PBYTE_Msk                               (0x01UL << GPIO_PORT_B81_PBYTE_Pos)                       /*!< GPIO_PORT B81: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B82  -----------------------------------------
+#define GPIO_PORT_B82_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B82: PBYTE Position       */
+#define GPIO_PORT_B82_PBYTE_Msk                               (0x01UL << GPIO_PORT_B82_PBYTE_Pos)                       /*!< GPIO_PORT B82: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B83  -----------------------------------------
+#define GPIO_PORT_B83_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B83: PBYTE Position       */
+#define GPIO_PORT_B83_PBYTE_Msk                               (0x01UL << GPIO_PORT_B83_PBYTE_Pos)                       /*!< GPIO_PORT B83: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B84  -----------------------------------------
+#define GPIO_PORT_B84_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B84: PBYTE Position       */
+#define GPIO_PORT_B84_PBYTE_Msk                               (0x01UL << GPIO_PORT_B84_PBYTE_Pos)                       /*!< GPIO_PORT B84: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B85  -----------------------------------------
+#define GPIO_PORT_B85_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B85: PBYTE Position       */
+#define GPIO_PORT_B85_PBYTE_Msk                               (0x01UL << GPIO_PORT_B85_PBYTE_Pos)                       /*!< GPIO_PORT B85: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B86  -----------------------------------------
+#define GPIO_PORT_B86_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B86: PBYTE Position       */
+#define GPIO_PORT_B86_PBYTE_Msk                               (0x01UL << GPIO_PORT_B86_PBYTE_Pos)                       /*!< GPIO_PORT B86: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B87  -----------------------------------------
+#define GPIO_PORT_B87_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B87: PBYTE Position       */
+#define GPIO_PORT_B87_PBYTE_Msk                               (0x01UL << GPIO_PORT_B87_PBYTE_Pos)                       /*!< GPIO_PORT B87: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B88  -----------------------------------------
+#define GPIO_PORT_B88_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B88: PBYTE Position       */
+#define GPIO_PORT_B88_PBYTE_Msk                               (0x01UL << GPIO_PORT_B88_PBYTE_Pos)                       /*!< GPIO_PORT B88: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B89  -----------------------------------------
+#define GPIO_PORT_B89_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B89: PBYTE Position       */
+#define GPIO_PORT_B89_PBYTE_Msk                               (0x01UL << GPIO_PORT_B89_PBYTE_Pos)                       /*!< GPIO_PORT B89: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B90  -----------------------------------------
+#define GPIO_PORT_B90_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B90: PBYTE Position       */
+#define GPIO_PORT_B90_PBYTE_Msk                               (0x01UL << GPIO_PORT_B90_PBYTE_Pos)                       /*!< GPIO_PORT B90: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B91  -----------------------------------------
+#define GPIO_PORT_B91_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B91: PBYTE Position       */
+#define GPIO_PORT_B91_PBYTE_Msk                               (0x01UL << GPIO_PORT_B91_PBYTE_Pos)                       /*!< GPIO_PORT B91: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B92  -----------------------------------------
+#define GPIO_PORT_B92_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B92: PBYTE Position       */
+#define GPIO_PORT_B92_PBYTE_Msk                               (0x01UL << GPIO_PORT_B92_PBYTE_Pos)                       /*!< GPIO_PORT B92: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B93  -----------------------------------------
+#define GPIO_PORT_B93_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B93: PBYTE Position       */
+#define GPIO_PORT_B93_PBYTE_Msk                               (0x01UL << GPIO_PORT_B93_PBYTE_Pos)                       /*!< GPIO_PORT B93: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B94  -----------------------------------------
+#define GPIO_PORT_B94_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B94: PBYTE Position       */
+#define GPIO_PORT_B94_PBYTE_Msk                               (0x01UL << GPIO_PORT_B94_PBYTE_Pos)                       /*!< GPIO_PORT B94: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B95  -----------------------------------------
+#define GPIO_PORT_B95_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B95: PBYTE Position       */
+#define GPIO_PORT_B95_PBYTE_Msk                               (0x01UL << GPIO_PORT_B95_PBYTE_Pos)                       /*!< GPIO_PORT B95: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B96  -----------------------------------------
+#define GPIO_PORT_B96_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B96: PBYTE Position       */
+#define GPIO_PORT_B96_PBYTE_Msk                               (0x01UL << GPIO_PORT_B96_PBYTE_Pos)                       /*!< GPIO_PORT B96: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B97  -----------------------------------------
+#define GPIO_PORT_B97_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B97: PBYTE Position       */
+#define GPIO_PORT_B97_PBYTE_Msk                               (0x01UL << GPIO_PORT_B97_PBYTE_Pos)                       /*!< GPIO_PORT B97: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B98  -----------------------------------------
+#define GPIO_PORT_B98_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B98: PBYTE Position       */
+#define GPIO_PORT_B98_PBYTE_Msk                               (0x01UL << GPIO_PORT_B98_PBYTE_Pos)                       /*!< GPIO_PORT B98: PBYTE Mask           */
+
+// --------------------------------------  GPIO_PORT_B99  -----------------------------------------
+#define GPIO_PORT_B99_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B99: PBYTE Position       */
+#define GPIO_PORT_B99_PBYTE_Msk                               (0x01UL << GPIO_PORT_B99_PBYTE_Pos)                       /*!< GPIO_PORT B99: PBYTE Mask           */
+
+// -------------------------------------  GPIO_PORT_B100  -----------------------------------------
+#define GPIO_PORT_B100_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B100: PBYTE Position      */
+#define GPIO_PORT_B100_PBYTE_Msk                              (0x01UL << GPIO_PORT_B100_PBYTE_Pos)                      /*!< GPIO_PORT B100: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B101  -----------------------------------------
+#define GPIO_PORT_B101_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B101: PBYTE Position      */
+#define GPIO_PORT_B101_PBYTE_Msk                              (0x01UL << GPIO_PORT_B101_PBYTE_Pos)                      /*!< GPIO_PORT B101: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B102  -----------------------------------------
+#define GPIO_PORT_B102_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B102: PBYTE Position      */
+#define GPIO_PORT_B102_PBYTE_Msk                              (0x01UL << GPIO_PORT_B102_PBYTE_Pos)                      /*!< GPIO_PORT B102: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B103  -----------------------------------------
+#define GPIO_PORT_B103_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B103: PBYTE Position      */
+#define GPIO_PORT_B103_PBYTE_Msk                              (0x01UL << GPIO_PORT_B103_PBYTE_Pos)                      /*!< GPIO_PORT B103: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B104  -----------------------------------------
+#define GPIO_PORT_B104_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B104: PBYTE Position      */
+#define GPIO_PORT_B104_PBYTE_Msk                              (0x01UL << GPIO_PORT_B104_PBYTE_Pos)                      /*!< GPIO_PORT B104: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B105  -----------------------------------------
+#define GPIO_PORT_B105_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B105: PBYTE Position      */
+#define GPIO_PORT_B105_PBYTE_Msk                              (0x01UL << GPIO_PORT_B105_PBYTE_Pos)                      /*!< GPIO_PORT B105: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B106  -----------------------------------------
+#define GPIO_PORT_B106_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B106: PBYTE Position      */
+#define GPIO_PORT_B106_PBYTE_Msk                              (0x01UL << GPIO_PORT_B106_PBYTE_Pos)                      /*!< GPIO_PORT B106: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B107  -----------------------------------------
+#define GPIO_PORT_B107_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B107: PBYTE Position      */
+#define GPIO_PORT_B107_PBYTE_Msk                              (0x01UL << GPIO_PORT_B107_PBYTE_Pos)                      /*!< GPIO_PORT B107: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B108  -----------------------------------------
+#define GPIO_PORT_B108_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B108: PBYTE Position      */
+#define GPIO_PORT_B108_PBYTE_Msk                              (0x01UL << GPIO_PORT_B108_PBYTE_Pos)                      /*!< GPIO_PORT B108: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B109  -----------------------------------------
+#define GPIO_PORT_B109_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B109: PBYTE Position      */
+#define GPIO_PORT_B109_PBYTE_Msk                              (0x01UL << GPIO_PORT_B109_PBYTE_Pos)                      /*!< GPIO_PORT B109: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B110  -----------------------------------------
+#define GPIO_PORT_B110_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B110: PBYTE Position      */
+#define GPIO_PORT_B110_PBYTE_Msk                              (0x01UL << GPIO_PORT_B110_PBYTE_Pos)                      /*!< GPIO_PORT B110: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B111  -----------------------------------------
+#define GPIO_PORT_B111_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B111: PBYTE Position      */
+#define GPIO_PORT_B111_PBYTE_Msk                              (0x01UL << GPIO_PORT_B111_PBYTE_Pos)                      /*!< GPIO_PORT B111: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B112  -----------------------------------------
+#define GPIO_PORT_B112_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B112: PBYTE Position      */
+#define GPIO_PORT_B112_PBYTE_Msk                              (0x01UL << GPIO_PORT_B112_PBYTE_Pos)                      /*!< GPIO_PORT B112: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B113  -----------------------------------------
+#define GPIO_PORT_B113_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B113: PBYTE Position      */
+#define GPIO_PORT_B113_PBYTE_Msk                              (0x01UL << GPIO_PORT_B113_PBYTE_Pos)                      /*!< GPIO_PORT B113: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B114  -----------------------------------------
+#define GPIO_PORT_B114_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B114: PBYTE Position      */
+#define GPIO_PORT_B114_PBYTE_Msk                              (0x01UL << GPIO_PORT_B114_PBYTE_Pos)                      /*!< GPIO_PORT B114: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B115  -----------------------------------------
+#define GPIO_PORT_B115_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B115: PBYTE Position      */
+#define GPIO_PORT_B115_PBYTE_Msk                              (0x01UL << GPIO_PORT_B115_PBYTE_Pos)                      /*!< GPIO_PORT B115: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B116  -----------------------------------------
+#define GPIO_PORT_B116_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B116: PBYTE Position      */
+#define GPIO_PORT_B116_PBYTE_Msk                              (0x01UL << GPIO_PORT_B116_PBYTE_Pos)                      /*!< GPIO_PORT B116: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B117  -----------------------------------------
+#define GPIO_PORT_B117_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B117: PBYTE Position      */
+#define GPIO_PORT_B117_PBYTE_Msk                              (0x01UL << GPIO_PORT_B117_PBYTE_Pos)                      /*!< GPIO_PORT B117: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B118  -----------------------------------------
+#define GPIO_PORT_B118_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B118: PBYTE Position      */
+#define GPIO_PORT_B118_PBYTE_Msk                              (0x01UL << GPIO_PORT_B118_PBYTE_Pos)                      /*!< GPIO_PORT B118: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B119  -----------------------------------------
+#define GPIO_PORT_B119_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B119: PBYTE Position      */
+#define GPIO_PORT_B119_PBYTE_Msk                              (0x01UL << GPIO_PORT_B119_PBYTE_Pos)                      /*!< GPIO_PORT B119: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B120  -----------------------------------------
+#define GPIO_PORT_B120_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B120: PBYTE Position      */
+#define GPIO_PORT_B120_PBYTE_Msk                              (0x01UL << GPIO_PORT_B120_PBYTE_Pos)                      /*!< GPIO_PORT B120: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B121  -----------------------------------------
+#define GPIO_PORT_B121_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B121: PBYTE Position      */
+#define GPIO_PORT_B121_PBYTE_Msk                              (0x01UL << GPIO_PORT_B121_PBYTE_Pos)                      /*!< GPIO_PORT B121: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B122  -----------------------------------------
+#define GPIO_PORT_B122_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B122: PBYTE Position      */
+#define GPIO_PORT_B122_PBYTE_Msk                              (0x01UL << GPIO_PORT_B122_PBYTE_Pos)                      /*!< GPIO_PORT B122: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B123  -----------------------------------------
+#define GPIO_PORT_B123_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B123: PBYTE Position      */
+#define GPIO_PORT_B123_PBYTE_Msk                              (0x01UL << GPIO_PORT_B123_PBYTE_Pos)                      /*!< GPIO_PORT B123: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B124  -----------------------------------------
+#define GPIO_PORT_B124_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B124: PBYTE Position      */
+#define GPIO_PORT_B124_PBYTE_Msk                              (0x01UL << GPIO_PORT_B124_PBYTE_Pos)                      /*!< GPIO_PORT B124: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B125  -----------------------------------------
+#define GPIO_PORT_B125_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B125: PBYTE Position      */
+#define GPIO_PORT_B125_PBYTE_Msk                              (0x01UL << GPIO_PORT_B125_PBYTE_Pos)                      /*!< GPIO_PORT B125: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B126  -----------------------------------------
+#define GPIO_PORT_B126_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B126: PBYTE Position      */
+#define GPIO_PORT_B126_PBYTE_Msk                              (0x01UL << GPIO_PORT_B126_PBYTE_Pos)                      /*!< GPIO_PORT B126: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B127  -----------------------------------------
+#define GPIO_PORT_B127_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B127: PBYTE Position      */
+#define GPIO_PORT_B127_PBYTE_Msk                              (0x01UL << GPIO_PORT_B127_PBYTE_Pos)                      /*!< GPIO_PORT B127: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B128  -----------------------------------------
+#define GPIO_PORT_B128_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B128: PBYTE Position      */
+#define GPIO_PORT_B128_PBYTE_Msk                              (0x01UL << GPIO_PORT_B128_PBYTE_Pos)                      /*!< GPIO_PORT B128: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B129  -----------------------------------------
+#define GPIO_PORT_B129_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B129: PBYTE Position      */
+#define GPIO_PORT_B129_PBYTE_Msk                              (0x01UL << GPIO_PORT_B129_PBYTE_Pos)                      /*!< GPIO_PORT B129: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B130  -----------------------------------------
+#define GPIO_PORT_B130_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B130: PBYTE Position      */
+#define GPIO_PORT_B130_PBYTE_Msk                              (0x01UL << GPIO_PORT_B130_PBYTE_Pos)                      /*!< GPIO_PORT B130: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B131  -----------------------------------------
+#define GPIO_PORT_B131_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B131: PBYTE Position      */
+#define GPIO_PORT_B131_PBYTE_Msk                              (0x01UL << GPIO_PORT_B131_PBYTE_Pos)                      /*!< GPIO_PORT B131: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B132  -----------------------------------------
+#define GPIO_PORT_B132_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B132: PBYTE Position      */
+#define GPIO_PORT_B132_PBYTE_Msk                              (0x01UL << GPIO_PORT_B132_PBYTE_Pos)                      /*!< GPIO_PORT B132: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B133  -----------------------------------------
+#define GPIO_PORT_B133_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B133: PBYTE Position      */
+#define GPIO_PORT_B133_PBYTE_Msk                              (0x01UL << GPIO_PORT_B133_PBYTE_Pos)                      /*!< GPIO_PORT B133: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B134  -----------------------------------------
+#define GPIO_PORT_B134_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B134: PBYTE Position      */
+#define GPIO_PORT_B134_PBYTE_Msk                              (0x01UL << GPIO_PORT_B134_PBYTE_Pos)                      /*!< GPIO_PORT B134: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B135  -----------------------------------------
+#define GPIO_PORT_B135_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B135: PBYTE Position      */
+#define GPIO_PORT_B135_PBYTE_Msk                              (0x01UL << GPIO_PORT_B135_PBYTE_Pos)                      /*!< GPIO_PORT B135: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B136  -----------------------------------------
+#define GPIO_PORT_B136_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B136: PBYTE Position      */
+#define GPIO_PORT_B136_PBYTE_Msk                              (0x01UL << GPIO_PORT_B136_PBYTE_Pos)                      /*!< GPIO_PORT B136: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B137  -----------------------------------------
+#define GPIO_PORT_B137_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B137: PBYTE Position      */
+#define GPIO_PORT_B137_PBYTE_Msk                              (0x01UL << GPIO_PORT_B137_PBYTE_Pos)                      /*!< GPIO_PORT B137: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B138  -----------------------------------------
+#define GPIO_PORT_B138_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B138: PBYTE Position      */
+#define GPIO_PORT_B138_PBYTE_Msk                              (0x01UL << GPIO_PORT_B138_PBYTE_Pos)                      /*!< GPIO_PORT B138: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B139  -----------------------------------------
+#define GPIO_PORT_B139_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B139: PBYTE Position      */
+#define GPIO_PORT_B139_PBYTE_Msk                              (0x01UL << GPIO_PORT_B139_PBYTE_Pos)                      /*!< GPIO_PORT B139: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B140  -----------------------------------------
+#define GPIO_PORT_B140_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B140: PBYTE Position      */
+#define GPIO_PORT_B140_PBYTE_Msk                              (0x01UL << GPIO_PORT_B140_PBYTE_Pos)                      /*!< GPIO_PORT B140: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B141  -----------------------------------------
+#define GPIO_PORT_B141_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B141: PBYTE Position      */
+#define GPIO_PORT_B141_PBYTE_Msk                              (0x01UL << GPIO_PORT_B141_PBYTE_Pos)                      /*!< GPIO_PORT B141: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B142  -----------------------------------------
+#define GPIO_PORT_B142_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B142: PBYTE Position      */
+#define GPIO_PORT_B142_PBYTE_Msk                              (0x01UL << GPIO_PORT_B142_PBYTE_Pos)                      /*!< GPIO_PORT B142: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B143  -----------------------------------------
+#define GPIO_PORT_B143_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B143: PBYTE Position      */
+#define GPIO_PORT_B143_PBYTE_Msk                              (0x01UL << GPIO_PORT_B143_PBYTE_Pos)                      /*!< GPIO_PORT B143: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B144  -----------------------------------------
+#define GPIO_PORT_B144_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B144: PBYTE Position      */
+#define GPIO_PORT_B144_PBYTE_Msk                              (0x01UL << GPIO_PORT_B144_PBYTE_Pos)                      /*!< GPIO_PORT B144: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B145  -----------------------------------------
+#define GPIO_PORT_B145_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B145: PBYTE Position      */
+#define GPIO_PORT_B145_PBYTE_Msk                              (0x01UL << GPIO_PORT_B145_PBYTE_Pos)                      /*!< GPIO_PORT B145: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B146  -----------------------------------------
+#define GPIO_PORT_B146_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B146: PBYTE Position      */
+#define GPIO_PORT_B146_PBYTE_Msk                              (0x01UL << GPIO_PORT_B146_PBYTE_Pos)                      /*!< GPIO_PORT B146: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B147  -----------------------------------------
+#define GPIO_PORT_B147_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B147: PBYTE Position      */
+#define GPIO_PORT_B147_PBYTE_Msk                              (0x01UL << GPIO_PORT_B147_PBYTE_Pos)                      /*!< GPIO_PORT B147: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B148  -----------------------------------------
+#define GPIO_PORT_B148_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B148: PBYTE Position      */
+#define GPIO_PORT_B148_PBYTE_Msk                              (0x01UL << GPIO_PORT_B148_PBYTE_Pos)                      /*!< GPIO_PORT B148: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B149  -----------------------------------------
+#define GPIO_PORT_B149_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B149: PBYTE Position      */
+#define GPIO_PORT_B149_PBYTE_Msk                              (0x01UL << GPIO_PORT_B149_PBYTE_Pos)                      /*!< GPIO_PORT B149: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B150  -----------------------------------------
+#define GPIO_PORT_B150_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B150: PBYTE Position      */
+#define GPIO_PORT_B150_PBYTE_Msk                              (0x01UL << GPIO_PORT_B150_PBYTE_Pos)                      /*!< GPIO_PORT B150: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B151  -----------------------------------------
+#define GPIO_PORT_B151_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B151: PBYTE Position      */
+#define GPIO_PORT_B151_PBYTE_Msk                              (0x01UL << GPIO_PORT_B151_PBYTE_Pos)                      /*!< GPIO_PORT B151: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B152  -----------------------------------------
+#define GPIO_PORT_B152_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B152: PBYTE Position      */
+#define GPIO_PORT_B152_PBYTE_Msk                              (0x01UL << GPIO_PORT_B152_PBYTE_Pos)                      /*!< GPIO_PORT B152: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B153  -----------------------------------------
+#define GPIO_PORT_B153_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B153: PBYTE Position      */
+#define GPIO_PORT_B153_PBYTE_Msk                              (0x01UL << GPIO_PORT_B153_PBYTE_Pos)                      /*!< GPIO_PORT B153: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B154  -----------------------------------------
+#define GPIO_PORT_B154_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B154: PBYTE Position      */
+#define GPIO_PORT_B154_PBYTE_Msk                              (0x01UL << GPIO_PORT_B154_PBYTE_Pos)                      /*!< GPIO_PORT B154: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B155  -----------------------------------------
+#define GPIO_PORT_B155_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B155: PBYTE Position      */
+#define GPIO_PORT_B155_PBYTE_Msk                              (0x01UL << GPIO_PORT_B155_PBYTE_Pos)                      /*!< GPIO_PORT B155: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B156  -----------------------------------------
+#define GPIO_PORT_B156_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B156: PBYTE Position      */
+#define GPIO_PORT_B156_PBYTE_Msk                              (0x01UL << GPIO_PORT_B156_PBYTE_Pos)                      /*!< GPIO_PORT B156: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B157  -----------------------------------------
+#define GPIO_PORT_B157_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B157: PBYTE Position      */
+#define GPIO_PORT_B157_PBYTE_Msk                              (0x01UL << GPIO_PORT_B157_PBYTE_Pos)                      /*!< GPIO_PORT B157: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B158  -----------------------------------------
+#define GPIO_PORT_B158_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B158: PBYTE Position      */
+#define GPIO_PORT_B158_PBYTE_Msk                              (0x01UL << GPIO_PORT_B158_PBYTE_Pos)                      /*!< GPIO_PORT B158: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B159  -----------------------------------------
+#define GPIO_PORT_B159_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B159: PBYTE Position      */
+#define GPIO_PORT_B159_PBYTE_Msk                              (0x01UL << GPIO_PORT_B159_PBYTE_Pos)                      /*!< GPIO_PORT B159: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B160  -----------------------------------------
+#define GPIO_PORT_B160_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B160: PBYTE Position      */
+#define GPIO_PORT_B160_PBYTE_Msk                              (0x01UL << GPIO_PORT_B160_PBYTE_Pos)                      /*!< GPIO_PORT B160: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B161  -----------------------------------------
+#define GPIO_PORT_B161_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B161: PBYTE Position      */
+#define GPIO_PORT_B161_PBYTE_Msk                              (0x01UL << GPIO_PORT_B161_PBYTE_Pos)                      /*!< GPIO_PORT B161: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B162  -----------------------------------------
+#define GPIO_PORT_B162_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B162: PBYTE Position      */
+#define GPIO_PORT_B162_PBYTE_Msk                              (0x01UL << GPIO_PORT_B162_PBYTE_Pos)                      /*!< GPIO_PORT B162: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B163  -----------------------------------------
+#define GPIO_PORT_B163_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B163: PBYTE Position      */
+#define GPIO_PORT_B163_PBYTE_Msk                              (0x01UL << GPIO_PORT_B163_PBYTE_Pos)                      /*!< GPIO_PORT B163: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B164  -----------------------------------------
+#define GPIO_PORT_B164_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B164: PBYTE Position      */
+#define GPIO_PORT_B164_PBYTE_Msk                              (0x01UL << GPIO_PORT_B164_PBYTE_Pos)                      /*!< GPIO_PORT B164: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B165  -----------------------------------------
+#define GPIO_PORT_B165_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B165: PBYTE Position      */
+#define GPIO_PORT_B165_PBYTE_Msk                              (0x01UL << GPIO_PORT_B165_PBYTE_Pos)                      /*!< GPIO_PORT B165: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B166  -----------------------------------------
+#define GPIO_PORT_B166_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B166: PBYTE Position      */
+#define GPIO_PORT_B166_PBYTE_Msk                              (0x01UL << GPIO_PORT_B166_PBYTE_Pos)                      /*!< GPIO_PORT B166: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B167  -----------------------------------------
+#define GPIO_PORT_B167_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B167: PBYTE Position      */
+#define GPIO_PORT_B167_PBYTE_Msk                              (0x01UL << GPIO_PORT_B167_PBYTE_Pos)                      /*!< GPIO_PORT B167: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B168  -----------------------------------------
+#define GPIO_PORT_B168_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B168: PBYTE Position      */
+#define GPIO_PORT_B168_PBYTE_Msk                              (0x01UL << GPIO_PORT_B168_PBYTE_Pos)                      /*!< GPIO_PORT B168: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B169  -----------------------------------------
+#define GPIO_PORT_B169_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B169: PBYTE Position      */
+#define GPIO_PORT_B169_PBYTE_Msk                              (0x01UL << GPIO_PORT_B169_PBYTE_Pos)                      /*!< GPIO_PORT B169: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B170  -----------------------------------------
+#define GPIO_PORT_B170_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B170: PBYTE Position      */
+#define GPIO_PORT_B170_PBYTE_Msk                              (0x01UL << GPIO_PORT_B170_PBYTE_Pos)                      /*!< GPIO_PORT B170: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B171  -----------------------------------------
+#define GPIO_PORT_B171_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B171: PBYTE Position      */
+#define GPIO_PORT_B171_PBYTE_Msk                              (0x01UL << GPIO_PORT_B171_PBYTE_Pos)                      /*!< GPIO_PORT B171: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B172  -----------------------------------------
+#define GPIO_PORT_B172_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B172: PBYTE Position      */
+#define GPIO_PORT_B172_PBYTE_Msk                              (0x01UL << GPIO_PORT_B172_PBYTE_Pos)                      /*!< GPIO_PORT B172: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B173  -----------------------------------------
+#define GPIO_PORT_B173_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B173: PBYTE Position      */
+#define GPIO_PORT_B173_PBYTE_Msk                              (0x01UL << GPIO_PORT_B173_PBYTE_Pos)                      /*!< GPIO_PORT B173: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B174  -----------------------------------------
+#define GPIO_PORT_B174_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B174: PBYTE Position      */
+#define GPIO_PORT_B174_PBYTE_Msk                              (0x01UL << GPIO_PORT_B174_PBYTE_Pos)                      /*!< GPIO_PORT B174: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B175  -----------------------------------------
+#define GPIO_PORT_B175_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B175: PBYTE Position      */
+#define GPIO_PORT_B175_PBYTE_Msk                              (0x01UL << GPIO_PORT_B175_PBYTE_Pos)                      /*!< GPIO_PORT B175: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B176  -----------------------------------------
+#define GPIO_PORT_B176_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B176: PBYTE Position      */
+#define GPIO_PORT_B176_PBYTE_Msk                              (0x01UL << GPIO_PORT_B176_PBYTE_Pos)                      /*!< GPIO_PORT B176: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B177  -----------------------------------------
+#define GPIO_PORT_B177_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B177: PBYTE Position      */
+#define GPIO_PORT_B177_PBYTE_Msk                              (0x01UL << GPIO_PORT_B177_PBYTE_Pos)                      /*!< GPIO_PORT B177: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B178  -----------------------------------------
+#define GPIO_PORT_B178_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B178: PBYTE Position      */
+#define GPIO_PORT_B178_PBYTE_Msk                              (0x01UL << GPIO_PORT_B178_PBYTE_Pos)                      /*!< GPIO_PORT B178: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B179  -----------------------------------------
+#define GPIO_PORT_B179_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B179: PBYTE Position      */
+#define GPIO_PORT_B179_PBYTE_Msk                              (0x01UL << GPIO_PORT_B179_PBYTE_Pos)                      /*!< GPIO_PORT B179: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B180  -----------------------------------------
+#define GPIO_PORT_B180_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B180: PBYTE Position      */
+#define GPIO_PORT_B180_PBYTE_Msk                              (0x01UL << GPIO_PORT_B180_PBYTE_Pos)                      /*!< GPIO_PORT B180: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B181  -----------------------------------------
+#define GPIO_PORT_B181_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B181: PBYTE Position      */
+#define GPIO_PORT_B181_PBYTE_Msk                              (0x01UL << GPIO_PORT_B181_PBYTE_Pos)                      /*!< GPIO_PORT B181: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B182  -----------------------------------------
+#define GPIO_PORT_B182_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B182: PBYTE Position      */
+#define GPIO_PORT_B182_PBYTE_Msk                              (0x01UL << GPIO_PORT_B182_PBYTE_Pos)                      /*!< GPIO_PORT B182: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B183  -----------------------------------------
+#define GPIO_PORT_B183_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B183: PBYTE Position      */
+#define GPIO_PORT_B183_PBYTE_Msk                              (0x01UL << GPIO_PORT_B183_PBYTE_Pos)                      /*!< GPIO_PORT B183: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B184  -----------------------------------------
+#define GPIO_PORT_B184_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B184: PBYTE Position      */
+#define GPIO_PORT_B184_PBYTE_Msk                              (0x01UL << GPIO_PORT_B184_PBYTE_Pos)                      /*!< GPIO_PORT B184: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B185  -----------------------------------------
+#define GPIO_PORT_B185_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B185: PBYTE Position      */
+#define GPIO_PORT_B185_PBYTE_Msk                              (0x01UL << GPIO_PORT_B185_PBYTE_Pos)                      /*!< GPIO_PORT B185: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B186  -----------------------------------------
+#define GPIO_PORT_B186_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B186: PBYTE Position      */
+#define GPIO_PORT_B186_PBYTE_Msk                              (0x01UL << GPIO_PORT_B186_PBYTE_Pos)                      /*!< GPIO_PORT B186: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B187  -----------------------------------------
+#define GPIO_PORT_B187_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B187: PBYTE Position      */
+#define GPIO_PORT_B187_PBYTE_Msk                              (0x01UL << GPIO_PORT_B187_PBYTE_Pos)                      /*!< GPIO_PORT B187: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B188  -----------------------------------------
+#define GPIO_PORT_B188_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B188: PBYTE Position      */
+#define GPIO_PORT_B188_PBYTE_Msk                              (0x01UL << GPIO_PORT_B188_PBYTE_Pos)                      /*!< GPIO_PORT B188: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B189  -----------------------------------------
+#define GPIO_PORT_B189_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B189: PBYTE Position      */
+#define GPIO_PORT_B189_PBYTE_Msk                              (0x01UL << GPIO_PORT_B189_PBYTE_Pos)                      /*!< GPIO_PORT B189: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B190  -----------------------------------------
+#define GPIO_PORT_B190_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B190: PBYTE Position      */
+#define GPIO_PORT_B190_PBYTE_Msk                              (0x01UL << GPIO_PORT_B190_PBYTE_Pos)                      /*!< GPIO_PORT B190: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B191  -----------------------------------------
+#define GPIO_PORT_B191_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B191: PBYTE Position      */
+#define GPIO_PORT_B191_PBYTE_Msk                              (0x01UL << GPIO_PORT_B191_PBYTE_Pos)                      /*!< GPIO_PORT B191: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B192  -----------------------------------------
+#define GPIO_PORT_B192_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B192: PBYTE Position      */
+#define GPIO_PORT_B192_PBYTE_Msk                              (0x01UL << GPIO_PORT_B192_PBYTE_Pos)                      /*!< GPIO_PORT B192: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B193  -----------------------------------------
+#define GPIO_PORT_B193_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B193: PBYTE Position      */
+#define GPIO_PORT_B193_PBYTE_Msk                              (0x01UL << GPIO_PORT_B193_PBYTE_Pos)                      /*!< GPIO_PORT B193: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B194  -----------------------------------------
+#define GPIO_PORT_B194_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B194: PBYTE Position      */
+#define GPIO_PORT_B194_PBYTE_Msk                              (0x01UL << GPIO_PORT_B194_PBYTE_Pos)                      /*!< GPIO_PORT B194: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B195  -----------------------------------------
+#define GPIO_PORT_B195_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B195: PBYTE Position      */
+#define GPIO_PORT_B195_PBYTE_Msk                              (0x01UL << GPIO_PORT_B195_PBYTE_Pos)                      /*!< GPIO_PORT B195: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B196  -----------------------------------------
+#define GPIO_PORT_B196_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B196: PBYTE Position      */
+#define GPIO_PORT_B196_PBYTE_Msk                              (0x01UL << GPIO_PORT_B196_PBYTE_Pos)                      /*!< GPIO_PORT B196: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B197  -----------------------------------------
+#define GPIO_PORT_B197_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B197: PBYTE Position      */
+#define GPIO_PORT_B197_PBYTE_Msk                              (0x01UL << GPIO_PORT_B197_PBYTE_Pos)                      /*!< GPIO_PORT B197: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B198  -----------------------------------------
+#define GPIO_PORT_B198_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B198: PBYTE Position      */
+#define GPIO_PORT_B198_PBYTE_Msk                              (0x01UL << GPIO_PORT_B198_PBYTE_Pos)                      /*!< GPIO_PORT B198: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B199  -----------------------------------------
+#define GPIO_PORT_B199_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B199: PBYTE Position      */
+#define GPIO_PORT_B199_PBYTE_Msk                              (0x01UL << GPIO_PORT_B199_PBYTE_Pos)                      /*!< GPIO_PORT B199: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B200  -----------------------------------------
+#define GPIO_PORT_B200_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B200: PBYTE Position      */
+#define GPIO_PORT_B200_PBYTE_Msk                              (0x01UL << GPIO_PORT_B200_PBYTE_Pos)                      /*!< GPIO_PORT B200: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B201  -----------------------------------------
+#define GPIO_PORT_B201_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B201: PBYTE Position      */
+#define GPIO_PORT_B201_PBYTE_Msk                              (0x01UL << GPIO_PORT_B201_PBYTE_Pos)                      /*!< GPIO_PORT B201: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B202  -----------------------------------------
+#define GPIO_PORT_B202_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B202: PBYTE Position      */
+#define GPIO_PORT_B202_PBYTE_Msk                              (0x01UL << GPIO_PORT_B202_PBYTE_Pos)                      /*!< GPIO_PORT B202: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B203  -----------------------------------------
+#define GPIO_PORT_B203_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B203: PBYTE Position      */
+#define GPIO_PORT_B203_PBYTE_Msk                              (0x01UL << GPIO_PORT_B203_PBYTE_Pos)                      /*!< GPIO_PORT B203: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B204  -----------------------------------------
+#define GPIO_PORT_B204_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B204: PBYTE Position      */
+#define GPIO_PORT_B204_PBYTE_Msk                              (0x01UL << GPIO_PORT_B204_PBYTE_Pos)                      /*!< GPIO_PORT B204: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B205  -----------------------------------------
+#define GPIO_PORT_B205_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B205: PBYTE Position      */
+#define GPIO_PORT_B205_PBYTE_Msk                              (0x01UL << GPIO_PORT_B205_PBYTE_Pos)                      /*!< GPIO_PORT B205: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B206  -----------------------------------------
+#define GPIO_PORT_B206_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B206: PBYTE Position      */
+#define GPIO_PORT_B206_PBYTE_Msk                              (0x01UL << GPIO_PORT_B206_PBYTE_Pos)                      /*!< GPIO_PORT B206: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B207  -----------------------------------------
+#define GPIO_PORT_B207_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B207: PBYTE Position      */
+#define GPIO_PORT_B207_PBYTE_Msk                              (0x01UL << GPIO_PORT_B207_PBYTE_Pos)                      /*!< GPIO_PORT B207: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B208  -----------------------------------------
+#define GPIO_PORT_B208_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B208: PBYTE Position      */
+#define GPIO_PORT_B208_PBYTE_Msk                              (0x01UL << GPIO_PORT_B208_PBYTE_Pos)                      /*!< GPIO_PORT B208: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B209  -----------------------------------------
+#define GPIO_PORT_B209_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B209: PBYTE Position      */
+#define GPIO_PORT_B209_PBYTE_Msk                              (0x01UL << GPIO_PORT_B209_PBYTE_Pos)                      /*!< GPIO_PORT B209: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B210  -----------------------------------------
+#define GPIO_PORT_B210_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B210: PBYTE Position      */
+#define GPIO_PORT_B210_PBYTE_Msk                              (0x01UL << GPIO_PORT_B210_PBYTE_Pos)                      /*!< GPIO_PORT B210: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B211  -----------------------------------------
+#define GPIO_PORT_B211_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B211: PBYTE Position      */
+#define GPIO_PORT_B211_PBYTE_Msk                              (0x01UL << GPIO_PORT_B211_PBYTE_Pos)                      /*!< GPIO_PORT B211: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B212  -----------------------------------------
+#define GPIO_PORT_B212_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B212: PBYTE Position      */
+#define GPIO_PORT_B212_PBYTE_Msk                              (0x01UL << GPIO_PORT_B212_PBYTE_Pos)                      /*!< GPIO_PORT B212: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B213  -----------------------------------------
+#define GPIO_PORT_B213_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B213: PBYTE Position      */
+#define GPIO_PORT_B213_PBYTE_Msk                              (0x01UL << GPIO_PORT_B213_PBYTE_Pos)                      /*!< GPIO_PORT B213: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B214  -----------------------------------------
+#define GPIO_PORT_B214_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B214: PBYTE Position      */
+#define GPIO_PORT_B214_PBYTE_Msk                              (0x01UL << GPIO_PORT_B214_PBYTE_Pos)                      /*!< GPIO_PORT B214: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B215  -----------------------------------------
+#define GPIO_PORT_B215_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B215: PBYTE Position      */
+#define GPIO_PORT_B215_PBYTE_Msk                              (0x01UL << GPIO_PORT_B215_PBYTE_Pos)                      /*!< GPIO_PORT B215: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B216  -----------------------------------------
+#define GPIO_PORT_B216_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B216: PBYTE Position      */
+#define GPIO_PORT_B216_PBYTE_Msk                              (0x01UL << GPIO_PORT_B216_PBYTE_Pos)                      /*!< GPIO_PORT B216: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B217  -----------------------------------------
+#define GPIO_PORT_B217_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B217: PBYTE Position      */
+#define GPIO_PORT_B217_PBYTE_Msk                              (0x01UL << GPIO_PORT_B217_PBYTE_Pos)                      /*!< GPIO_PORT B217: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B218  -----------------------------------------
+#define GPIO_PORT_B218_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B218: PBYTE Position      */
+#define GPIO_PORT_B218_PBYTE_Msk                              (0x01UL << GPIO_PORT_B218_PBYTE_Pos)                      /*!< GPIO_PORT B218: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B219  -----------------------------------------
+#define GPIO_PORT_B219_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B219: PBYTE Position      */
+#define GPIO_PORT_B219_PBYTE_Msk                              (0x01UL << GPIO_PORT_B219_PBYTE_Pos)                      /*!< GPIO_PORT B219: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B220  -----------------------------------------
+#define GPIO_PORT_B220_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B220: PBYTE Position      */
+#define GPIO_PORT_B220_PBYTE_Msk                              (0x01UL << GPIO_PORT_B220_PBYTE_Pos)                      /*!< GPIO_PORT B220: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B221  -----------------------------------------
+#define GPIO_PORT_B221_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B221: PBYTE Position      */
+#define GPIO_PORT_B221_PBYTE_Msk                              (0x01UL << GPIO_PORT_B221_PBYTE_Pos)                      /*!< GPIO_PORT B221: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B222  -----------------------------------------
+#define GPIO_PORT_B222_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B222: PBYTE Position      */
+#define GPIO_PORT_B222_PBYTE_Msk                              (0x01UL << GPIO_PORT_B222_PBYTE_Pos)                      /*!< GPIO_PORT B222: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B223  -----------------------------------------
+#define GPIO_PORT_B223_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B223: PBYTE Position      */
+#define GPIO_PORT_B223_PBYTE_Msk                              (0x01UL << GPIO_PORT_B223_PBYTE_Pos)                      /*!< GPIO_PORT B223: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B224  -----------------------------------------
+#define GPIO_PORT_B224_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B224: PBYTE Position      */
+#define GPIO_PORT_B224_PBYTE_Msk                              (0x01UL << GPIO_PORT_B224_PBYTE_Pos)                      /*!< GPIO_PORT B224: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B225  -----------------------------------------
+#define GPIO_PORT_B225_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B225: PBYTE Position      */
+#define GPIO_PORT_B225_PBYTE_Msk                              (0x01UL << GPIO_PORT_B225_PBYTE_Pos)                      /*!< GPIO_PORT B225: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B226  -----------------------------------------
+#define GPIO_PORT_B226_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B226: PBYTE Position      */
+#define GPIO_PORT_B226_PBYTE_Msk                              (0x01UL << GPIO_PORT_B226_PBYTE_Pos)                      /*!< GPIO_PORT B226: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B227  -----------------------------------------
+#define GPIO_PORT_B227_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B227: PBYTE Position      */
+#define GPIO_PORT_B227_PBYTE_Msk                              (0x01UL << GPIO_PORT_B227_PBYTE_Pos)                      /*!< GPIO_PORT B227: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B228  -----------------------------------------
+#define GPIO_PORT_B228_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B228: PBYTE Position      */
+#define GPIO_PORT_B228_PBYTE_Msk                              (0x01UL << GPIO_PORT_B228_PBYTE_Pos)                      /*!< GPIO_PORT B228: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B229  -----------------------------------------
+#define GPIO_PORT_B229_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B229: PBYTE Position      */
+#define GPIO_PORT_B229_PBYTE_Msk                              (0x01UL << GPIO_PORT_B229_PBYTE_Pos)                      /*!< GPIO_PORT B229: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B230  -----------------------------------------
+#define GPIO_PORT_B230_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B230: PBYTE Position      */
+#define GPIO_PORT_B230_PBYTE_Msk                              (0x01UL << GPIO_PORT_B230_PBYTE_Pos)                      /*!< GPIO_PORT B230: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B231  -----------------------------------------
+#define GPIO_PORT_B231_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B231: PBYTE Position      */
+#define GPIO_PORT_B231_PBYTE_Msk                              (0x01UL << GPIO_PORT_B231_PBYTE_Pos)                      /*!< GPIO_PORT B231: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B232  -----------------------------------------
+#define GPIO_PORT_B232_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B232: PBYTE Position      */
+#define GPIO_PORT_B232_PBYTE_Msk                              (0x01UL << GPIO_PORT_B232_PBYTE_Pos)                      /*!< GPIO_PORT B232: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B233  -----------------------------------------
+#define GPIO_PORT_B233_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B233: PBYTE Position      */
+#define GPIO_PORT_B233_PBYTE_Msk                              (0x01UL << GPIO_PORT_B233_PBYTE_Pos)                      /*!< GPIO_PORT B233: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B234  -----------------------------------------
+#define GPIO_PORT_B234_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B234: PBYTE Position      */
+#define GPIO_PORT_B234_PBYTE_Msk                              (0x01UL << GPIO_PORT_B234_PBYTE_Pos)                      /*!< GPIO_PORT B234: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B235  -----------------------------------------
+#define GPIO_PORT_B235_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B235: PBYTE Position      */
+#define GPIO_PORT_B235_PBYTE_Msk                              (0x01UL << GPIO_PORT_B235_PBYTE_Pos)                      /*!< GPIO_PORT B235: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B236  -----------------------------------------
+#define GPIO_PORT_B236_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B236: PBYTE Position      */
+#define GPIO_PORT_B236_PBYTE_Msk                              (0x01UL << GPIO_PORT_B236_PBYTE_Pos)                      /*!< GPIO_PORT B236: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B237  -----------------------------------------
+#define GPIO_PORT_B237_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B237: PBYTE Position      */
+#define GPIO_PORT_B237_PBYTE_Msk                              (0x01UL << GPIO_PORT_B237_PBYTE_Pos)                      /*!< GPIO_PORT B237: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B238  -----------------------------------------
+#define GPIO_PORT_B238_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B238: PBYTE Position      */
+#define GPIO_PORT_B238_PBYTE_Msk                              (0x01UL << GPIO_PORT_B238_PBYTE_Pos)                      /*!< GPIO_PORT B238: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B239  -----------------------------------------
+#define GPIO_PORT_B239_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B239: PBYTE Position      */
+#define GPIO_PORT_B239_PBYTE_Msk                              (0x01UL << GPIO_PORT_B239_PBYTE_Pos)                      /*!< GPIO_PORT B239: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B240  -----------------------------------------
+#define GPIO_PORT_B240_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B240: PBYTE Position      */
+#define GPIO_PORT_B240_PBYTE_Msk                              (0x01UL << GPIO_PORT_B240_PBYTE_Pos)                      /*!< GPIO_PORT B240: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B241  -----------------------------------------
+#define GPIO_PORT_B241_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B241: PBYTE Position      */
+#define GPIO_PORT_B241_PBYTE_Msk                              (0x01UL << GPIO_PORT_B241_PBYTE_Pos)                      /*!< GPIO_PORT B241: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B242  -----------------------------------------
+#define GPIO_PORT_B242_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B242: PBYTE Position      */
+#define GPIO_PORT_B242_PBYTE_Msk                              (0x01UL << GPIO_PORT_B242_PBYTE_Pos)                      /*!< GPIO_PORT B242: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B243  -----------------------------------------
+#define GPIO_PORT_B243_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B243: PBYTE Position      */
+#define GPIO_PORT_B243_PBYTE_Msk                              (0x01UL << GPIO_PORT_B243_PBYTE_Pos)                      /*!< GPIO_PORT B243: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B244  -----------------------------------------
+#define GPIO_PORT_B244_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B244: PBYTE Position      */
+#define GPIO_PORT_B244_PBYTE_Msk                              (0x01UL << GPIO_PORT_B244_PBYTE_Pos)                      /*!< GPIO_PORT B244: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B245  -----------------------------------------
+#define GPIO_PORT_B245_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B245: PBYTE Position      */
+#define GPIO_PORT_B245_PBYTE_Msk                              (0x01UL << GPIO_PORT_B245_PBYTE_Pos)                      /*!< GPIO_PORT B245: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B246  -----------------------------------------
+#define GPIO_PORT_B246_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B246: PBYTE Position      */
+#define GPIO_PORT_B246_PBYTE_Msk                              (0x01UL << GPIO_PORT_B246_PBYTE_Pos)                      /*!< GPIO_PORT B246: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B247  -----------------------------------------
+#define GPIO_PORT_B247_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B247: PBYTE Position      */
+#define GPIO_PORT_B247_PBYTE_Msk                              (0x01UL << GPIO_PORT_B247_PBYTE_Pos)                      /*!< GPIO_PORT B247: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B248  -----------------------------------------
+#define GPIO_PORT_B248_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B248: PBYTE Position      */
+#define GPIO_PORT_B248_PBYTE_Msk                              (0x01UL << GPIO_PORT_B248_PBYTE_Pos)                      /*!< GPIO_PORT B248: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B249  -----------------------------------------
+#define GPIO_PORT_B249_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B249: PBYTE Position      */
+#define GPIO_PORT_B249_PBYTE_Msk                              (0x01UL << GPIO_PORT_B249_PBYTE_Pos)                      /*!< GPIO_PORT B249: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B250  -----------------------------------------
+#define GPIO_PORT_B250_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B250: PBYTE Position      */
+#define GPIO_PORT_B250_PBYTE_Msk                              (0x01UL << GPIO_PORT_B250_PBYTE_Pos)                      /*!< GPIO_PORT B250: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B251  -----------------------------------------
+#define GPIO_PORT_B251_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B251: PBYTE Position      */
+#define GPIO_PORT_B251_PBYTE_Msk                              (0x01UL << GPIO_PORT_B251_PBYTE_Pos)                      /*!< GPIO_PORT B251: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B252  -----------------------------------------
+#define GPIO_PORT_B252_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B252: PBYTE Position      */
+#define GPIO_PORT_B252_PBYTE_Msk                              (0x01UL << GPIO_PORT_B252_PBYTE_Pos)                      /*!< GPIO_PORT B252: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B253  -----------------------------------------
+#define GPIO_PORT_B253_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B253: PBYTE Position      */
+#define GPIO_PORT_B253_PBYTE_Msk                              (0x01UL << GPIO_PORT_B253_PBYTE_Pos)                      /*!< GPIO_PORT B253: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B254  -----------------------------------------
+#define GPIO_PORT_B254_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B254: PBYTE Position      */
+#define GPIO_PORT_B254_PBYTE_Msk                              (0x01UL << GPIO_PORT_B254_PBYTE_Pos)                      /*!< GPIO_PORT B254: PBYTE Mask          */
+
+// -------------------------------------  GPIO_PORT_B255  -----------------------------------------
+#define GPIO_PORT_B255_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B255: PBYTE Position      */
+#define GPIO_PORT_B255_PBYTE_Msk                              (0x01UL << GPIO_PORT_B255_PBYTE_Pos)                      /*!< GPIO_PORT B255: PBYTE Mask          */
+
+// --------------------------------------  GPIO_PORT_W0  ------------------------------------------
+#define GPIO_PORT_W0_PWORD_Pos                                0                                                         /*!< GPIO_PORT W0: PWORD Position        */
+#define GPIO_PORT_W0_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos)                  /*!< GPIO_PORT W0: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W1  ------------------------------------------
+#define GPIO_PORT_W1_PWORD_Pos                                0                                                         /*!< GPIO_PORT W1: PWORD Position        */
+#define GPIO_PORT_W1_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos)                  /*!< GPIO_PORT W1: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W2  ------------------------------------------
+#define GPIO_PORT_W2_PWORD_Pos                                0                                                         /*!< GPIO_PORT W2: PWORD Position        */
+#define GPIO_PORT_W2_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos)                  /*!< GPIO_PORT W2: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W3  ------------------------------------------
+#define GPIO_PORT_W3_PWORD_Pos                                0                                                         /*!< GPIO_PORT W3: PWORD Position        */
+#define GPIO_PORT_W3_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos)                  /*!< GPIO_PORT W3: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W4  ------------------------------------------
+#define GPIO_PORT_W4_PWORD_Pos                                0                                                         /*!< GPIO_PORT W4: PWORD Position        */
+#define GPIO_PORT_W4_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos)                  /*!< GPIO_PORT W4: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W5  ------------------------------------------
+#define GPIO_PORT_W5_PWORD_Pos                                0                                                         /*!< GPIO_PORT W5: PWORD Position        */
+#define GPIO_PORT_W5_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos)                  /*!< GPIO_PORT W5: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W6  ------------------------------------------
+#define GPIO_PORT_W6_PWORD_Pos                                0                                                         /*!< GPIO_PORT W6: PWORD Position        */
+#define GPIO_PORT_W6_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos)                  /*!< GPIO_PORT W6: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W7  ------------------------------------------
+#define GPIO_PORT_W7_PWORD_Pos                                0                                                         /*!< GPIO_PORT W7: PWORD Position        */
+#define GPIO_PORT_W7_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos)                  /*!< GPIO_PORT W7: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W8  ------------------------------------------
+#define GPIO_PORT_W8_PWORD_Pos                                0                                                         /*!< GPIO_PORT W8: PWORD Position        */
+#define GPIO_PORT_W8_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos)                  /*!< GPIO_PORT W8: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W9  ------------------------------------------
+#define GPIO_PORT_W9_PWORD_Pos                                0                                                         /*!< GPIO_PORT W9: PWORD Position        */
+#define GPIO_PORT_W9_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos)                  /*!< GPIO_PORT W9: PWORD Mask            */
+
+// --------------------------------------  GPIO_PORT_W10  -----------------------------------------
+#define GPIO_PORT_W10_PWORD_Pos                               0                                                         /*!< GPIO_PORT W10: PWORD Position       */
+#define GPIO_PORT_W10_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos)                 /*!< GPIO_PORT W10: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W11  -----------------------------------------
+#define GPIO_PORT_W11_PWORD_Pos                               0                                                         /*!< GPIO_PORT W11: PWORD Position       */
+#define GPIO_PORT_W11_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos)                 /*!< GPIO_PORT W11: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W12  -----------------------------------------
+#define GPIO_PORT_W12_PWORD_Pos                               0                                                         /*!< GPIO_PORT W12: PWORD Position       */
+#define GPIO_PORT_W12_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos)                 /*!< GPIO_PORT W12: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W13  -----------------------------------------
+#define GPIO_PORT_W13_PWORD_Pos                               0                                                         /*!< GPIO_PORT W13: PWORD Position       */
+#define GPIO_PORT_W13_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos)                 /*!< GPIO_PORT W13: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W14  -----------------------------------------
+#define GPIO_PORT_W14_PWORD_Pos                               0                                                         /*!< GPIO_PORT W14: PWORD Position       */
+#define GPIO_PORT_W14_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos)                 /*!< GPIO_PORT W14: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W15  -----------------------------------------
+#define GPIO_PORT_W15_PWORD_Pos                               0                                                         /*!< GPIO_PORT W15: PWORD Position       */
+#define GPIO_PORT_W15_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos)                 /*!< GPIO_PORT W15: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W16  -----------------------------------------
+#define GPIO_PORT_W16_PWORD_Pos                               0                                                         /*!< GPIO_PORT W16: PWORD Position       */
+#define GPIO_PORT_W16_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos)                 /*!< GPIO_PORT W16: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W17  -----------------------------------------
+#define GPIO_PORT_W17_PWORD_Pos                               0                                                         /*!< GPIO_PORT W17: PWORD Position       */
+#define GPIO_PORT_W17_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos)                 /*!< GPIO_PORT W17: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W18  -----------------------------------------
+#define GPIO_PORT_W18_PWORD_Pos                               0                                                         /*!< GPIO_PORT W18: PWORD Position       */
+#define GPIO_PORT_W18_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos)                 /*!< GPIO_PORT W18: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W19  -----------------------------------------
+#define GPIO_PORT_W19_PWORD_Pos                               0                                                         /*!< GPIO_PORT W19: PWORD Position       */
+#define GPIO_PORT_W19_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos)                 /*!< GPIO_PORT W19: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W20  -----------------------------------------
+#define GPIO_PORT_W20_PWORD_Pos                               0                                                         /*!< GPIO_PORT W20: PWORD Position       */
+#define GPIO_PORT_W20_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos)                 /*!< GPIO_PORT W20: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W21  -----------------------------------------
+#define GPIO_PORT_W21_PWORD_Pos                               0                                                         /*!< GPIO_PORT W21: PWORD Position       */
+#define GPIO_PORT_W21_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos)                 /*!< GPIO_PORT W21: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W22  -----------------------------------------
+#define GPIO_PORT_W22_PWORD_Pos                               0                                                         /*!< GPIO_PORT W22: PWORD Position       */
+#define GPIO_PORT_W22_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos)                 /*!< GPIO_PORT W22: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W23  -----------------------------------------
+#define GPIO_PORT_W23_PWORD_Pos                               0                                                         /*!< GPIO_PORT W23: PWORD Position       */
+#define GPIO_PORT_W23_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos)                 /*!< GPIO_PORT W23: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W24  -----------------------------------------
+#define GPIO_PORT_W24_PWORD_Pos                               0                                                         /*!< GPIO_PORT W24: PWORD Position       */
+#define GPIO_PORT_W24_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos)                 /*!< GPIO_PORT W24: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W25  -----------------------------------------
+#define GPIO_PORT_W25_PWORD_Pos                               0                                                         /*!< GPIO_PORT W25: PWORD Position       */
+#define GPIO_PORT_W25_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos)                 /*!< GPIO_PORT W25: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W26  -----------------------------------------
+#define GPIO_PORT_W26_PWORD_Pos                               0                                                         /*!< GPIO_PORT W26: PWORD Position       */
+#define GPIO_PORT_W26_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos)                 /*!< GPIO_PORT W26: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W27  -----------------------------------------
+#define GPIO_PORT_W27_PWORD_Pos                               0                                                         /*!< GPIO_PORT W27: PWORD Position       */
+#define GPIO_PORT_W27_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos)                 /*!< GPIO_PORT W27: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W28  -----------------------------------------
+#define GPIO_PORT_W28_PWORD_Pos                               0                                                         /*!< GPIO_PORT W28: PWORD Position       */
+#define GPIO_PORT_W28_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos)                 /*!< GPIO_PORT W28: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W29  -----------------------------------------
+#define GPIO_PORT_W29_PWORD_Pos                               0                                                         /*!< GPIO_PORT W29: PWORD Position       */
+#define GPIO_PORT_W29_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos)                 /*!< GPIO_PORT W29: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W30  -----------------------------------------
+#define GPIO_PORT_W30_PWORD_Pos                               0                                                         /*!< GPIO_PORT W30: PWORD Position       */
+#define GPIO_PORT_W30_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos)                 /*!< GPIO_PORT W30: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W31  -----------------------------------------
+#define GPIO_PORT_W31_PWORD_Pos                               0                                                         /*!< GPIO_PORT W31: PWORD Position       */
+#define GPIO_PORT_W31_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos)                 /*!< GPIO_PORT W31: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W32  -----------------------------------------
+#define GPIO_PORT_W32_PWORD_Pos                               0                                                         /*!< GPIO_PORT W32: PWORD Position       */
+#define GPIO_PORT_W32_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos)                 /*!< GPIO_PORT W32: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W33  -----------------------------------------
+#define GPIO_PORT_W33_PWORD_Pos                               0                                                         /*!< GPIO_PORT W33: PWORD Position       */
+#define GPIO_PORT_W33_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos)                 /*!< GPIO_PORT W33: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W34  -----------------------------------------
+#define GPIO_PORT_W34_PWORD_Pos                               0                                                         /*!< GPIO_PORT W34: PWORD Position       */
+#define GPIO_PORT_W34_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos)                 /*!< GPIO_PORT W34: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W35  -----------------------------------------
+#define GPIO_PORT_W35_PWORD_Pos                               0                                                         /*!< GPIO_PORT W35: PWORD Position       */
+#define GPIO_PORT_W35_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos)                 /*!< GPIO_PORT W35: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W36  -----------------------------------------
+#define GPIO_PORT_W36_PWORD_Pos                               0                                                         /*!< GPIO_PORT W36: PWORD Position       */
+#define GPIO_PORT_W36_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos)                 /*!< GPIO_PORT W36: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W37  -----------------------------------------
+#define GPIO_PORT_W37_PWORD_Pos                               0                                                         /*!< GPIO_PORT W37: PWORD Position       */
+#define GPIO_PORT_W37_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos)                 /*!< GPIO_PORT W37: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W38  -----------------------------------------
+#define GPIO_PORT_W38_PWORD_Pos                               0                                                         /*!< GPIO_PORT W38: PWORD Position       */
+#define GPIO_PORT_W38_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos)                 /*!< GPIO_PORT W38: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W39  -----------------------------------------
+#define GPIO_PORT_W39_PWORD_Pos                               0                                                         /*!< GPIO_PORT W39: PWORD Position       */
+#define GPIO_PORT_W39_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos)                 /*!< GPIO_PORT W39: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W40  -----------------------------------------
+#define GPIO_PORT_W40_PWORD_Pos                               0                                                         /*!< GPIO_PORT W40: PWORD Position       */
+#define GPIO_PORT_W40_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos)                 /*!< GPIO_PORT W40: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W41  -----------------------------------------
+#define GPIO_PORT_W41_PWORD_Pos                               0                                                         /*!< GPIO_PORT W41: PWORD Position       */
+#define GPIO_PORT_W41_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos)                 /*!< GPIO_PORT W41: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W42  -----------------------------------------
+#define GPIO_PORT_W42_PWORD_Pos                               0                                                         /*!< GPIO_PORT W42: PWORD Position       */
+#define GPIO_PORT_W42_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos)                 /*!< GPIO_PORT W42: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W43  -----------------------------------------
+#define GPIO_PORT_W43_PWORD_Pos                               0                                                         /*!< GPIO_PORT W43: PWORD Position       */
+#define GPIO_PORT_W43_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos)                 /*!< GPIO_PORT W43: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W44  -----------------------------------------
+#define GPIO_PORT_W44_PWORD_Pos                               0                                                         /*!< GPIO_PORT W44: PWORD Position       */
+#define GPIO_PORT_W44_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos)                 /*!< GPIO_PORT W44: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W45  -----------------------------------------
+#define GPIO_PORT_W45_PWORD_Pos                               0                                                         /*!< GPIO_PORT W45: PWORD Position       */
+#define GPIO_PORT_W45_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos)                 /*!< GPIO_PORT W45: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W46  -----------------------------------------
+#define GPIO_PORT_W46_PWORD_Pos                               0                                                         /*!< GPIO_PORT W46: PWORD Position       */
+#define GPIO_PORT_W46_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos)                 /*!< GPIO_PORT W46: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W47  -----------------------------------------
+#define GPIO_PORT_W47_PWORD_Pos                               0                                                         /*!< GPIO_PORT W47: PWORD Position       */
+#define GPIO_PORT_W47_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos)                 /*!< GPIO_PORT W47: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W48  -----------------------------------------
+#define GPIO_PORT_W48_PWORD_Pos                               0                                                         /*!< GPIO_PORT W48: PWORD Position       */
+#define GPIO_PORT_W48_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos)                 /*!< GPIO_PORT W48: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W49  -----------------------------------------
+#define GPIO_PORT_W49_PWORD_Pos                               0                                                         /*!< GPIO_PORT W49: PWORD Position       */
+#define GPIO_PORT_W49_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos)                 /*!< GPIO_PORT W49: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W50  -----------------------------------------
+#define GPIO_PORT_W50_PWORD_Pos                               0                                                         /*!< GPIO_PORT W50: PWORD Position       */
+#define GPIO_PORT_W50_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos)                 /*!< GPIO_PORT W50: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W51  -----------------------------------------
+#define GPIO_PORT_W51_PWORD_Pos                               0                                                         /*!< GPIO_PORT W51: PWORD Position       */
+#define GPIO_PORT_W51_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos)                 /*!< GPIO_PORT W51: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W52  -----------------------------------------
+#define GPIO_PORT_W52_PWORD_Pos                               0                                                         /*!< GPIO_PORT W52: PWORD Position       */
+#define GPIO_PORT_W52_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos)                 /*!< GPIO_PORT W52: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W53  -----------------------------------------
+#define GPIO_PORT_W53_PWORD_Pos                               0                                                         /*!< GPIO_PORT W53: PWORD Position       */
+#define GPIO_PORT_W53_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos)                 /*!< GPIO_PORT W53: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W54  -----------------------------------------
+#define GPIO_PORT_W54_PWORD_Pos                               0                                                         /*!< GPIO_PORT W54: PWORD Position       */
+#define GPIO_PORT_W54_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos)                 /*!< GPIO_PORT W54: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W55  -----------------------------------------
+#define GPIO_PORT_W55_PWORD_Pos                               0                                                         /*!< GPIO_PORT W55: PWORD Position       */
+#define GPIO_PORT_W55_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos)                 /*!< GPIO_PORT W55: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W56  -----------------------------------------
+#define GPIO_PORT_W56_PWORD_Pos                               0                                                         /*!< GPIO_PORT W56: PWORD Position       */
+#define GPIO_PORT_W56_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos)                 /*!< GPIO_PORT W56: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W57  -----------------------------------------
+#define GPIO_PORT_W57_PWORD_Pos                               0                                                         /*!< GPIO_PORT W57: PWORD Position       */
+#define GPIO_PORT_W57_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos)                 /*!< GPIO_PORT W57: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W58  -----------------------------------------
+#define GPIO_PORT_W58_PWORD_Pos                               0                                                         /*!< GPIO_PORT W58: PWORD Position       */
+#define GPIO_PORT_W58_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos)                 /*!< GPIO_PORT W58: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W59  -----------------------------------------
+#define GPIO_PORT_W59_PWORD_Pos                               0                                                         /*!< GPIO_PORT W59: PWORD Position       */
+#define GPIO_PORT_W59_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos)                 /*!< GPIO_PORT W59: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W60  -----------------------------------------
+#define GPIO_PORT_W60_PWORD_Pos                               0                                                         /*!< GPIO_PORT W60: PWORD Position       */
+#define GPIO_PORT_W60_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos)                 /*!< GPIO_PORT W60: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W61  -----------------------------------------
+#define GPIO_PORT_W61_PWORD_Pos                               0                                                         /*!< GPIO_PORT W61: PWORD Position       */
+#define GPIO_PORT_W61_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos)                 /*!< GPIO_PORT W61: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W62  -----------------------------------------
+#define GPIO_PORT_W62_PWORD_Pos                               0                                                         /*!< GPIO_PORT W62: PWORD Position       */
+#define GPIO_PORT_W62_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos)                 /*!< GPIO_PORT W62: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W63  -----------------------------------------
+#define GPIO_PORT_W63_PWORD_Pos                               0                                                         /*!< GPIO_PORT W63: PWORD Position       */
+#define GPIO_PORT_W63_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos)                 /*!< GPIO_PORT W63: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W64  -----------------------------------------
+#define GPIO_PORT_W64_PWORD_Pos                               0                                                         /*!< GPIO_PORT W64: PWORD Position       */
+#define GPIO_PORT_W64_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos)                 /*!< GPIO_PORT W64: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W65  -----------------------------------------
+#define GPIO_PORT_W65_PWORD_Pos                               0                                                         /*!< GPIO_PORT W65: PWORD Position       */
+#define GPIO_PORT_W65_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos)                 /*!< GPIO_PORT W65: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W66  -----------------------------------------
+#define GPIO_PORT_W66_PWORD_Pos                               0                                                         /*!< GPIO_PORT W66: PWORD Position       */
+#define GPIO_PORT_W66_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos)                 /*!< GPIO_PORT W66: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W67  -----------------------------------------
+#define GPIO_PORT_W67_PWORD_Pos                               0                                                         /*!< GPIO_PORT W67: PWORD Position       */
+#define GPIO_PORT_W67_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos)                 /*!< GPIO_PORT W67: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W68  -----------------------------------------
+#define GPIO_PORT_W68_PWORD_Pos                               0                                                         /*!< GPIO_PORT W68: PWORD Position       */
+#define GPIO_PORT_W68_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos)                 /*!< GPIO_PORT W68: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W69  -----------------------------------------
+#define GPIO_PORT_W69_PWORD_Pos                               0                                                         /*!< GPIO_PORT W69: PWORD Position       */
+#define GPIO_PORT_W69_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos)                 /*!< GPIO_PORT W69: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W70  -----------------------------------------
+#define GPIO_PORT_W70_PWORD_Pos                               0                                                         /*!< GPIO_PORT W70: PWORD Position       */
+#define GPIO_PORT_W70_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos)                 /*!< GPIO_PORT W70: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W71  -----------------------------------------
+#define GPIO_PORT_W71_PWORD_Pos                               0                                                         /*!< GPIO_PORT W71: PWORD Position       */
+#define GPIO_PORT_W71_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos)                 /*!< GPIO_PORT W71: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W72  -----------------------------------------
+#define GPIO_PORT_W72_PWORD_Pos                               0                                                         /*!< GPIO_PORT W72: PWORD Position       */
+#define GPIO_PORT_W72_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos)                 /*!< GPIO_PORT W72: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W73  -----------------------------------------
+#define GPIO_PORT_W73_PWORD_Pos                               0                                                         /*!< GPIO_PORT W73: PWORD Position       */
+#define GPIO_PORT_W73_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos)                 /*!< GPIO_PORT W73: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W74  -----------------------------------------
+#define GPIO_PORT_W74_PWORD_Pos                               0                                                         /*!< GPIO_PORT W74: PWORD Position       */
+#define GPIO_PORT_W74_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos)                 /*!< GPIO_PORT W74: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W75  -----------------------------------------
+#define GPIO_PORT_W75_PWORD_Pos                               0                                                         /*!< GPIO_PORT W75: PWORD Position       */
+#define GPIO_PORT_W75_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos)                 /*!< GPIO_PORT W75: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W76  -----------------------------------------
+#define GPIO_PORT_W76_PWORD_Pos                               0                                                         /*!< GPIO_PORT W76: PWORD Position       */
+#define GPIO_PORT_W76_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos)                 /*!< GPIO_PORT W76: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W77  -----------------------------------------
+#define GPIO_PORT_W77_PWORD_Pos                               0                                                         /*!< GPIO_PORT W77: PWORD Position       */
+#define GPIO_PORT_W77_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos)                 /*!< GPIO_PORT W77: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W78  -----------------------------------------
+#define GPIO_PORT_W78_PWORD_Pos                               0                                                         /*!< GPIO_PORT W78: PWORD Position       */
+#define GPIO_PORT_W78_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos)                 /*!< GPIO_PORT W78: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W79  -----------------------------------------
+#define GPIO_PORT_W79_PWORD_Pos                               0                                                         /*!< GPIO_PORT W79: PWORD Position       */
+#define GPIO_PORT_W79_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos)                 /*!< GPIO_PORT W79: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W80  -----------------------------------------
+#define GPIO_PORT_W80_PWORD_Pos                               0                                                         /*!< GPIO_PORT W80: PWORD Position       */
+#define GPIO_PORT_W80_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos)                 /*!< GPIO_PORT W80: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W81  -----------------------------------------
+#define GPIO_PORT_W81_PWORD_Pos                               0                                                         /*!< GPIO_PORT W81: PWORD Position       */
+#define GPIO_PORT_W81_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos)                 /*!< GPIO_PORT W81: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W82  -----------------------------------------
+#define GPIO_PORT_W82_PWORD_Pos                               0                                                         /*!< GPIO_PORT W82: PWORD Position       */
+#define GPIO_PORT_W82_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos)                 /*!< GPIO_PORT W82: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W83  -----------------------------------------
+#define GPIO_PORT_W83_PWORD_Pos                               0                                                         /*!< GPIO_PORT W83: PWORD Position       */
+#define GPIO_PORT_W83_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos)                 /*!< GPIO_PORT W83: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W84  -----------------------------------------
+#define GPIO_PORT_W84_PWORD_Pos                               0                                                         /*!< GPIO_PORT W84: PWORD Position       */
+#define GPIO_PORT_W84_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos)                 /*!< GPIO_PORT W84: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W85  -----------------------------------------
+#define GPIO_PORT_W85_PWORD_Pos                               0                                                         /*!< GPIO_PORT W85: PWORD Position       */
+#define GPIO_PORT_W85_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos)                 /*!< GPIO_PORT W85: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W86  -----------------------------------------
+#define GPIO_PORT_W86_PWORD_Pos                               0                                                         /*!< GPIO_PORT W86: PWORD Position       */
+#define GPIO_PORT_W86_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos)                 /*!< GPIO_PORT W86: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W87  -----------------------------------------
+#define GPIO_PORT_W87_PWORD_Pos                               0                                                         /*!< GPIO_PORT W87: PWORD Position       */
+#define GPIO_PORT_W87_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos)                 /*!< GPIO_PORT W87: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W88  -----------------------------------------
+#define GPIO_PORT_W88_PWORD_Pos                               0                                                         /*!< GPIO_PORT W88: PWORD Position       */
+#define GPIO_PORT_W88_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos)                 /*!< GPIO_PORT W88: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W89  -----------------------------------------
+#define GPIO_PORT_W89_PWORD_Pos                               0                                                         /*!< GPIO_PORT W89: PWORD Position       */
+#define GPIO_PORT_W89_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos)                 /*!< GPIO_PORT W89: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W90  -----------------------------------------
+#define GPIO_PORT_W90_PWORD_Pos                               0                                                         /*!< GPIO_PORT W90: PWORD Position       */
+#define GPIO_PORT_W90_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos)                 /*!< GPIO_PORT W90: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W91  -----------------------------------------
+#define GPIO_PORT_W91_PWORD_Pos                               0                                                         /*!< GPIO_PORT W91: PWORD Position       */
+#define GPIO_PORT_W91_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos)                 /*!< GPIO_PORT W91: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W92  -----------------------------------------
+#define GPIO_PORT_W92_PWORD_Pos                               0                                                         /*!< GPIO_PORT W92: PWORD Position       */
+#define GPIO_PORT_W92_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos)                 /*!< GPIO_PORT W92: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W93  -----------------------------------------
+#define GPIO_PORT_W93_PWORD_Pos                               0                                                         /*!< GPIO_PORT W93: PWORD Position       */
+#define GPIO_PORT_W93_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos)                 /*!< GPIO_PORT W93: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W94  -----------------------------------------
+#define GPIO_PORT_W94_PWORD_Pos                               0                                                         /*!< GPIO_PORT W94: PWORD Position       */
+#define GPIO_PORT_W94_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos)                 /*!< GPIO_PORT W94: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W95  -----------------------------------------
+#define GPIO_PORT_W95_PWORD_Pos                               0                                                         /*!< GPIO_PORT W95: PWORD Position       */
+#define GPIO_PORT_W95_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos)                 /*!< GPIO_PORT W95: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W96  -----------------------------------------
+#define GPIO_PORT_W96_PWORD_Pos                               0                                                         /*!< GPIO_PORT W96: PWORD Position       */
+#define GPIO_PORT_W96_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos)                 /*!< GPIO_PORT W96: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W97  -----------------------------------------
+#define GPIO_PORT_W97_PWORD_Pos                               0                                                         /*!< GPIO_PORT W97: PWORD Position       */
+#define GPIO_PORT_W97_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos)                 /*!< GPIO_PORT W97: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W98  -----------------------------------------
+#define GPIO_PORT_W98_PWORD_Pos                               0                                                         /*!< GPIO_PORT W98: PWORD Position       */
+#define GPIO_PORT_W98_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos)                 /*!< GPIO_PORT W98: PWORD Mask           */
+
+// --------------------------------------  GPIO_PORT_W99  -----------------------------------------
+#define GPIO_PORT_W99_PWORD_Pos                               0                                                         /*!< GPIO_PORT W99: PWORD Position       */
+#define GPIO_PORT_W99_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos)                 /*!< GPIO_PORT W99: PWORD Mask           */
+
+// -------------------------------------  GPIO_PORT_W100  -----------------------------------------
+#define GPIO_PORT_W100_PWORD_Pos                              0                                                         /*!< GPIO_PORT W100: PWORD Position      */
+#define GPIO_PORT_W100_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos)                /*!< GPIO_PORT W100: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W101  -----------------------------------------
+#define GPIO_PORT_W101_PWORD_Pos                              0                                                         /*!< GPIO_PORT W101: PWORD Position      */
+#define GPIO_PORT_W101_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos)                /*!< GPIO_PORT W101: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W102  -----------------------------------------
+#define GPIO_PORT_W102_PWORD_Pos                              0                                                         /*!< GPIO_PORT W102: PWORD Position      */
+#define GPIO_PORT_W102_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos)                /*!< GPIO_PORT W102: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W103  -----------------------------------------
+#define GPIO_PORT_W103_PWORD_Pos                              0                                                         /*!< GPIO_PORT W103: PWORD Position      */
+#define GPIO_PORT_W103_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos)                /*!< GPIO_PORT W103: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W104  -----------------------------------------
+#define GPIO_PORT_W104_PWORD_Pos                              0                                                         /*!< GPIO_PORT W104: PWORD Position      */
+#define GPIO_PORT_W104_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos)                /*!< GPIO_PORT W104: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W105  -----------------------------------------
+#define GPIO_PORT_W105_PWORD_Pos                              0                                                         /*!< GPIO_PORT W105: PWORD Position      */
+#define GPIO_PORT_W105_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos)                /*!< GPIO_PORT W105: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W106  -----------------------------------------
+#define GPIO_PORT_W106_PWORD_Pos                              0                                                         /*!< GPIO_PORT W106: PWORD Position      */
+#define GPIO_PORT_W106_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos)                /*!< GPIO_PORT W106: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W107  -----------------------------------------
+#define GPIO_PORT_W107_PWORD_Pos                              0                                                         /*!< GPIO_PORT W107: PWORD Position      */
+#define GPIO_PORT_W107_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos)                /*!< GPIO_PORT W107: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W108  -----------------------------------------
+#define GPIO_PORT_W108_PWORD_Pos                              0                                                         /*!< GPIO_PORT W108: PWORD Position      */
+#define GPIO_PORT_W108_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos)                /*!< GPIO_PORT W108: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W109  -----------------------------------------
+#define GPIO_PORT_W109_PWORD_Pos                              0                                                         /*!< GPIO_PORT W109: PWORD Position      */
+#define GPIO_PORT_W109_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos)                /*!< GPIO_PORT W109: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W110  -----------------------------------------
+#define GPIO_PORT_W110_PWORD_Pos                              0                                                         /*!< GPIO_PORT W110: PWORD Position      */
+#define GPIO_PORT_W110_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos)                /*!< GPIO_PORT W110: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W111  -----------------------------------------
+#define GPIO_PORT_W111_PWORD_Pos                              0                                                         /*!< GPIO_PORT W111: PWORD Position      */
+#define GPIO_PORT_W111_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos)                /*!< GPIO_PORT W111: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W112  -----------------------------------------
+#define GPIO_PORT_W112_PWORD_Pos                              0                                                         /*!< GPIO_PORT W112: PWORD Position      */
+#define GPIO_PORT_W112_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos)                /*!< GPIO_PORT W112: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W113  -----------------------------------------
+#define GPIO_PORT_W113_PWORD_Pos                              0                                                         /*!< GPIO_PORT W113: PWORD Position      */
+#define GPIO_PORT_W113_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos)                /*!< GPIO_PORT W113: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W114  -----------------------------------------
+#define GPIO_PORT_W114_PWORD_Pos                              0                                                         /*!< GPIO_PORT W114: PWORD Position      */
+#define GPIO_PORT_W114_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos)                /*!< GPIO_PORT W114: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W115  -----------------------------------------
+#define GPIO_PORT_W115_PWORD_Pos                              0                                                         /*!< GPIO_PORT W115: PWORD Position      */
+#define GPIO_PORT_W115_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos)                /*!< GPIO_PORT W115: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W116  -----------------------------------------
+#define GPIO_PORT_W116_PWORD_Pos                              0                                                         /*!< GPIO_PORT W116: PWORD Position      */
+#define GPIO_PORT_W116_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos)                /*!< GPIO_PORT W116: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W117  -----------------------------------------
+#define GPIO_PORT_W117_PWORD_Pos                              0                                                         /*!< GPIO_PORT W117: PWORD Position      */
+#define GPIO_PORT_W117_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos)                /*!< GPIO_PORT W117: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W118  -----------------------------------------
+#define GPIO_PORT_W118_PWORD_Pos                              0                                                         /*!< GPIO_PORT W118: PWORD Position      */
+#define GPIO_PORT_W118_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos)                /*!< GPIO_PORT W118: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W119  -----------------------------------------
+#define GPIO_PORT_W119_PWORD_Pos                              0                                                         /*!< GPIO_PORT W119: PWORD Position      */
+#define GPIO_PORT_W119_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos)                /*!< GPIO_PORT W119: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W120  -----------------------------------------
+#define GPIO_PORT_W120_PWORD_Pos                              0                                                         /*!< GPIO_PORT W120: PWORD Position      */
+#define GPIO_PORT_W120_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos)                /*!< GPIO_PORT W120: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W121  -----------------------------------------
+#define GPIO_PORT_W121_PWORD_Pos                              0                                                         /*!< GPIO_PORT W121: PWORD Position      */
+#define GPIO_PORT_W121_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos)                /*!< GPIO_PORT W121: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W122  -----------------------------------------
+#define GPIO_PORT_W122_PWORD_Pos                              0                                                         /*!< GPIO_PORT W122: PWORD Position      */
+#define GPIO_PORT_W122_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos)                /*!< GPIO_PORT W122: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W123  -----------------------------------------
+#define GPIO_PORT_W123_PWORD_Pos                              0                                                         /*!< GPIO_PORT W123: PWORD Position      */
+#define GPIO_PORT_W123_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos)                /*!< GPIO_PORT W123: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W124  -----------------------------------------
+#define GPIO_PORT_W124_PWORD_Pos                              0                                                         /*!< GPIO_PORT W124: PWORD Position      */
+#define GPIO_PORT_W124_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos)                /*!< GPIO_PORT W124: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W125  -----------------------------------------
+#define GPIO_PORT_W125_PWORD_Pos                              0                                                         /*!< GPIO_PORT W125: PWORD Position      */
+#define GPIO_PORT_W125_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos)                /*!< GPIO_PORT W125: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W126  -----------------------------------------
+#define GPIO_PORT_W126_PWORD_Pos                              0                                                         /*!< GPIO_PORT W126: PWORD Position      */
+#define GPIO_PORT_W126_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos)                /*!< GPIO_PORT W126: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W127  -----------------------------------------
+#define GPIO_PORT_W127_PWORD_Pos                              0                                                         /*!< GPIO_PORT W127: PWORD Position      */
+#define GPIO_PORT_W127_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos)                /*!< GPIO_PORT W127: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W128  -----------------------------------------
+#define GPIO_PORT_W128_PWORD_Pos                              0                                                         /*!< GPIO_PORT W128: PWORD Position      */
+#define GPIO_PORT_W128_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos)                /*!< GPIO_PORT W128: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W129  -----------------------------------------
+#define GPIO_PORT_W129_PWORD_Pos                              0                                                         /*!< GPIO_PORT W129: PWORD Position      */
+#define GPIO_PORT_W129_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos)                /*!< GPIO_PORT W129: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W130  -----------------------------------------
+#define GPIO_PORT_W130_PWORD_Pos                              0                                                         /*!< GPIO_PORT W130: PWORD Position      */
+#define GPIO_PORT_W130_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos)                /*!< GPIO_PORT W130: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W131  -----------------------------------------
+#define GPIO_PORT_W131_PWORD_Pos                              0                                                         /*!< GPIO_PORT W131: PWORD Position      */
+#define GPIO_PORT_W131_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos)                /*!< GPIO_PORT W131: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W132  -----------------------------------------
+#define GPIO_PORT_W132_PWORD_Pos                              0                                                         /*!< GPIO_PORT W132: PWORD Position      */
+#define GPIO_PORT_W132_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos)                /*!< GPIO_PORT W132: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W133  -----------------------------------------
+#define GPIO_PORT_W133_PWORD_Pos                              0                                                         /*!< GPIO_PORT W133: PWORD Position      */
+#define GPIO_PORT_W133_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos)                /*!< GPIO_PORT W133: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W134  -----------------------------------------
+#define GPIO_PORT_W134_PWORD_Pos                              0                                                         /*!< GPIO_PORT W134: PWORD Position      */
+#define GPIO_PORT_W134_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos)                /*!< GPIO_PORT W134: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W135  -----------------------------------------
+#define GPIO_PORT_W135_PWORD_Pos                              0                                                         /*!< GPIO_PORT W135: PWORD Position      */
+#define GPIO_PORT_W135_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos)                /*!< GPIO_PORT W135: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W136  -----------------------------------------
+#define GPIO_PORT_W136_PWORD_Pos                              0                                                         /*!< GPIO_PORT W136: PWORD Position      */
+#define GPIO_PORT_W136_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos)                /*!< GPIO_PORT W136: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W137  -----------------------------------------
+#define GPIO_PORT_W137_PWORD_Pos                              0                                                         /*!< GPIO_PORT W137: PWORD Position      */
+#define GPIO_PORT_W137_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos)                /*!< GPIO_PORT W137: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W138  -----------------------------------------
+#define GPIO_PORT_W138_PWORD_Pos                              0                                                         /*!< GPIO_PORT W138: PWORD Position      */
+#define GPIO_PORT_W138_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos)                /*!< GPIO_PORT W138: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W139  -----------------------------------------
+#define GPIO_PORT_W139_PWORD_Pos                              0                                                         /*!< GPIO_PORT W139: PWORD Position      */
+#define GPIO_PORT_W139_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos)                /*!< GPIO_PORT W139: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W140  -----------------------------------------
+#define GPIO_PORT_W140_PWORD_Pos                              0                                                         /*!< GPIO_PORT W140: PWORD Position      */
+#define GPIO_PORT_W140_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos)                /*!< GPIO_PORT W140: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W141  -----------------------------------------
+#define GPIO_PORT_W141_PWORD_Pos                              0                                                         /*!< GPIO_PORT W141: PWORD Position      */
+#define GPIO_PORT_W141_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos)                /*!< GPIO_PORT W141: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W142  -----------------------------------------
+#define GPIO_PORT_W142_PWORD_Pos                              0                                                         /*!< GPIO_PORT W142: PWORD Position      */
+#define GPIO_PORT_W142_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos)                /*!< GPIO_PORT W142: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W143  -----------------------------------------
+#define GPIO_PORT_W143_PWORD_Pos                              0                                                         /*!< GPIO_PORT W143: PWORD Position      */
+#define GPIO_PORT_W143_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos)                /*!< GPIO_PORT W143: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W144  -----------------------------------------
+#define GPIO_PORT_W144_PWORD_Pos                              0                                                         /*!< GPIO_PORT W144: PWORD Position      */
+#define GPIO_PORT_W144_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos)                /*!< GPIO_PORT W144: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W145  -----------------------------------------
+#define GPIO_PORT_W145_PWORD_Pos                              0                                                         /*!< GPIO_PORT W145: PWORD Position      */
+#define GPIO_PORT_W145_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos)                /*!< GPIO_PORT W145: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W146  -----------------------------------------
+#define GPIO_PORT_W146_PWORD_Pos                              0                                                         /*!< GPIO_PORT W146: PWORD Position      */
+#define GPIO_PORT_W146_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos)                /*!< GPIO_PORT W146: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W147  -----------------------------------------
+#define GPIO_PORT_W147_PWORD_Pos                              0                                                         /*!< GPIO_PORT W147: PWORD Position      */
+#define GPIO_PORT_W147_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos)                /*!< GPIO_PORT W147: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W148  -----------------------------------------
+#define GPIO_PORT_W148_PWORD_Pos                              0                                                         /*!< GPIO_PORT W148: PWORD Position      */
+#define GPIO_PORT_W148_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos)                /*!< GPIO_PORT W148: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W149  -----------------------------------------
+#define GPIO_PORT_W149_PWORD_Pos                              0                                                         /*!< GPIO_PORT W149: PWORD Position      */
+#define GPIO_PORT_W149_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos)                /*!< GPIO_PORT W149: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W150  -----------------------------------------
+#define GPIO_PORT_W150_PWORD_Pos                              0                                                         /*!< GPIO_PORT W150: PWORD Position      */
+#define GPIO_PORT_W150_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos)                /*!< GPIO_PORT W150: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W151  -----------------------------------------
+#define GPIO_PORT_W151_PWORD_Pos                              0                                                         /*!< GPIO_PORT W151: PWORD Position      */
+#define GPIO_PORT_W151_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos)                /*!< GPIO_PORT W151: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W152  -----------------------------------------
+#define GPIO_PORT_W152_PWORD_Pos                              0                                                         /*!< GPIO_PORT W152: PWORD Position      */
+#define GPIO_PORT_W152_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos)                /*!< GPIO_PORT W152: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W153  -----------------------------------------
+#define GPIO_PORT_W153_PWORD_Pos                              0                                                         /*!< GPIO_PORT W153: PWORD Position      */
+#define GPIO_PORT_W153_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos)                /*!< GPIO_PORT W153: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W154  -----------------------------------------
+#define GPIO_PORT_W154_PWORD_Pos                              0                                                         /*!< GPIO_PORT W154: PWORD Position      */
+#define GPIO_PORT_W154_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos)                /*!< GPIO_PORT W154: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W155  -----------------------------------------
+#define GPIO_PORT_W155_PWORD_Pos                              0                                                         /*!< GPIO_PORT W155: PWORD Position      */
+#define GPIO_PORT_W155_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos)                /*!< GPIO_PORT W155: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W156  -----------------------------------------
+#define GPIO_PORT_W156_PWORD_Pos                              0                                                         /*!< GPIO_PORT W156: PWORD Position      */
+#define GPIO_PORT_W156_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos)                /*!< GPIO_PORT W156: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W157  -----------------------------------------
+#define GPIO_PORT_W157_PWORD_Pos                              0                                                         /*!< GPIO_PORT W157: PWORD Position      */
+#define GPIO_PORT_W157_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos)                /*!< GPIO_PORT W157: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W158  -----------------------------------------
+#define GPIO_PORT_W158_PWORD_Pos                              0                                                         /*!< GPIO_PORT W158: PWORD Position      */
+#define GPIO_PORT_W158_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos)                /*!< GPIO_PORT W158: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W159  -----------------------------------------
+#define GPIO_PORT_W159_PWORD_Pos                              0                                                         /*!< GPIO_PORT W159: PWORD Position      */
+#define GPIO_PORT_W159_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos)                /*!< GPIO_PORT W159: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W160  -----------------------------------------
+#define GPIO_PORT_W160_PWORD_Pos                              0                                                         /*!< GPIO_PORT W160: PWORD Position      */
+#define GPIO_PORT_W160_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos)                /*!< GPIO_PORT W160: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W161  -----------------------------------------
+#define GPIO_PORT_W161_PWORD_Pos                              0                                                         /*!< GPIO_PORT W161: PWORD Position      */
+#define GPIO_PORT_W161_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos)                /*!< GPIO_PORT W161: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W162  -----------------------------------------
+#define GPIO_PORT_W162_PWORD_Pos                              0                                                         /*!< GPIO_PORT W162: PWORD Position      */
+#define GPIO_PORT_W162_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos)                /*!< GPIO_PORT W162: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W163  -----------------------------------------
+#define GPIO_PORT_W163_PWORD_Pos                              0                                                         /*!< GPIO_PORT W163: PWORD Position      */
+#define GPIO_PORT_W163_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos)                /*!< GPIO_PORT W163: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W164  -----------------------------------------
+#define GPIO_PORT_W164_PWORD_Pos                              0                                                         /*!< GPIO_PORT W164: PWORD Position      */
+#define GPIO_PORT_W164_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos)                /*!< GPIO_PORT W164: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W165  -----------------------------------------
+#define GPIO_PORT_W165_PWORD_Pos                              0                                                         /*!< GPIO_PORT W165: PWORD Position      */
+#define GPIO_PORT_W165_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos)                /*!< GPIO_PORT W165: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W166  -----------------------------------------
+#define GPIO_PORT_W166_PWORD_Pos                              0                                                         /*!< GPIO_PORT W166: PWORD Position      */
+#define GPIO_PORT_W166_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos)                /*!< GPIO_PORT W166: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W167  -----------------------------------------
+#define GPIO_PORT_W167_PWORD_Pos                              0                                                         /*!< GPIO_PORT W167: PWORD Position      */
+#define GPIO_PORT_W167_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos)                /*!< GPIO_PORT W167: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W168  -----------------------------------------
+#define GPIO_PORT_W168_PWORD_Pos                              0                                                         /*!< GPIO_PORT W168: PWORD Position      */
+#define GPIO_PORT_W168_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos)                /*!< GPIO_PORT W168: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W169  -----------------------------------------
+#define GPIO_PORT_W169_PWORD_Pos                              0                                                         /*!< GPIO_PORT W169: PWORD Position      */
+#define GPIO_PORT_W169_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos)                /*!< GPIO_PORT W169: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W170  -----------------------------------------
+#define GPIO_PORT_W170_PWORD_Pos                              0                                                         /*!< GPIO_PORT W170: PWORD Position      */
+#define GPIO_PORT_W170_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos)                /*!< GPIO_PORT W170: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W171  -----------------------------------------
+#define GPIO_PORT_W171_PWORD_Pos                              0                                                         /*!< GPIO_PORT W171: PWORD Position      */
+#define GPIO_PORT_W171_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos)                /*!< GPIO_PORT W171: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W172  -----------------------------------------
+#define GPIO_PORT_W172_PWORD_Pos                              0                                                         /*!< GPIO_PORT W172: PWORD Position      */
+#define GPIO_PORT_W172_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos)                /*!< GPIO_PORT W172: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W173  -----------------------------------------
+#define GPIO_PORT_W173_PWORD_Pos                              0                                                         /*!< GPIO_PORT W173: PWORD Position      */
+#define GPIO_PORT_W173_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos)                /*!< GPIO_PORT W173: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W174  -----------------------------------------
+#define GPIO_PORT_W174_PWORD_Pos                              0                                                         /*!< GPIO_PORT W174: PWORD Position      */
+#define GPIO_PORT_W174_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos)                /*!< GPIO_PORT W174: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W175  -----------------------------------------
+#define GPIO_PORT_W175_PWORD_Pos                              0                                                         /*!< GPIO_PORT W175: PWORD Position      */
+#define GPIO_PORT_W175_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos)                /*!< GPIO_PORT W175: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W176  -----------------------------------------
+#define GPIO_PORT_W176_PWORD_Pos                              0                                                         /*!< GPIO_PORT W176: PWORD Position      */
+#define GPIO_PORT_W176_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos)                /*!< GPIO_PORT W176: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W177  -----------------------------------------
+#define GPIO_PORT_W177_PWORD_Pos                              0                                                         /*!< GPIO_PORT W177: PWORD Position      */
+#define GPIO_PORT_W177_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos)                /*!< GPIO_PORT W177: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W178  -----------------------------------------
+#define GPIO_PORT_W178_PWORD_Pos                              0                                                         /*!< GPIO_PORT W178: PWORD Position      */
+#define GPIO_PORT_W178_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos)                /*!< GPIO_PORT W178: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W179  -----------------------------------------
+#define GPIO_PORT_W179_PWORD_Pos                              0                                                         /*!< GPIO_PORT W179: PWORD Position      */
+#define GPIO_PORT_W179_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos)                /*!< GPIO_PORT W179: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W180  -----------------------------------------
+#define GPIO_PORT_W180_PWORD_Pos                              0                                                         /*!< GPIO_PORT W180: PWORD Position      */
+#define GPIO_PORT_W180_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos)                /*!< GPIO_PORT W180: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W181  -----------------------------------------
+#define GPIO_PORT_W181_PWORD_Pos                              0                                                         /*!< GPIO_PORT W181: PWORD Position      */
+#define GPIO_PORT_W181_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos)                /*!< GPIO_PORT W181: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W182  -----------------------------------------
+#define GPIO_PORT_W182_PWORD_Pos                              0                                                         /*!< GPIO_PORT W182: PWORD Position      */
+#define GPIO_PORT_W182_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos)                /*!< GPIO_PORT W182: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W183  -----------------------------------------
+#define GPIO_PORT_W183_PWORD_Pos                              0                                                         /*!< GPIO_PORT W183: PWORD Position      */
+#define GPIO_PORT_W183_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos)                /*!< GPIO_PORT W183: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W184  -----------------------------------------
+#define GPIO_PORT_W184_PWORD_Pos                              0                                                         /*!< GPIO_PORT W184: PWORD Position      */
+#define GPIO_PORT_W184_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos)                /*!< GPIO_PORT W184: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W185  -----------------------------------------
+#define GPIO_PORT_W185_PWORD_Pos                              0                                                         /*!< GPIO_PORT W185: PWORD Position      */
+#define GPIO_PORT_W185_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos)                /*!< GPIO_PORT W185: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W186  -----------------------------------------
+#define GPIO_PORT_W186_PWORD_Pos                              0                                                         /*!< GPIO_PORT W186: PWORD Position      */
+#define GPIO_PORT_W186_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos)                /*!< GPIO_PORT W186: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W187  -----------------------------------------
+#define GPIO_PORT_W187_PWORD_Pos                              0                                                         /*!< GPIO_PORT W187: PWORD Position      */
+#define GPIO_PORT_W187_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos)                /*!< GPIO_PORT W187: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W188  -----------------------------------------
+#define GPIO_PORT_W188_PWORD_Pos                              0                                                         /*!< GPIO_PORT W188: PWORD Position      */
+#define GPIO_PORT_W188_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos)                /*!< GPIO_PORT W188: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W189  -----------------------------------------
+#define GPIO_PORT_W189_PWORD_Pos                              0                                                         /*!< GPIO_PORT W189: PWORD Position      */
+#define GPIO_PORT_W189_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos)                /*!< GPIO_PORT W189: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W190  -----------------------------------------
+#define GPIO_PORT_W190_PWORD_Pos                              0                                                         /*!< GPIO_PORT W190: PWORD Position      */
+#define GPIO_PORT_W190_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos)                /*!< GPIO_PORT W190: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W191  -----------------------------------------
+#define GPIO_PORT_W191_PWORD_Pos                              0                                                         /*!< GPIO_PORT W191: PWORD Position      */
+#define GPIO_PORT_W191_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos)                /*!< GPIO_PORT W191: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W192  -----------------------------------------
+#define GPIO_PORT_W192_PWORD_Pos                              0                                                         /*!< GPIO_PORT W192: PWORD Position      */
+#define GPIO_PORT_W192_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos)                /*!< GPIO_PORT W192: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W193  -----------------------------------------
+#define GPIO_PORT_W193_PWORD_Pos                              0                                                         /*!< GPIO_PORT W193: PWORD Position      */
+#define GPIO_PORT_W193_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos)                /*!< GPIO_PORT W193: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W194  -----------------------------------------
+#define GPIO_PORT_W194_PWORD_Pos                              0                                                         /*!< GPIO_PORT W194: PWORD Position      */
+#define GPIO_PORT_W194_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos)                /*!< GPIO_PORT W194: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W195  -----------------------------------------
+#define GPIO_PORT_W195_PWORD_Pos                              0                                                         /*!< GPIO_PORT W195: PWORD Position      */
+#define GPIO_PORT_W195_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos)                /*!< GPIO_PORT W195: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W196  -----------------------------------------
+#define GPIO_PORT_W196_PWORD_Pos                              0                                                         /*!< GPIO_PORT W196: PWORD Position      */
+#define GPIO_PORT_W196_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos)                /*!< GPIO_PORT W196: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W197  -----------------------------------------
+#define GPIO_PORT_W197_PWORD_Pos                              0                                                         /*!< GPIO_PORT W197: PWORD Position      */
+#define GPIO_PORT_W197_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos)                /*!< GPIO_PORT W197: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W198  -----------------------------------------
+#define GPIO_PORT_W198_PWORD_Pos                              0                                                         /*!< GPIO_PORT W198: PWORD Position      */
+#define GPIO_PORT_W198_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos)                /*!< GPIO_PORT W198: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W199  -----------------------------------------
+#define GPIO_PORT_W199_PWORD_Pos                              0                                                         /*!< GPIO_PORT W199: PWORD Position      */
+#define GPIO_PORT_W199_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos)                /*!< GPIO_PORT W199: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W200  -----------------------------------------
+#define GPIO_PORT_W200_PWORD_Pos                              0                                                         /*!< GPIO_PORT W200: PWORD Position      */
+#define GPIO_PORT_W200_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos)                /*!< GPIO_PORT W200: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W201  -----------------------------------------
+#define GPIO_PORT_W201_PWORD_Pos                              0                                                         /*!< GPIO_PORT W201: PWORD Position      */
+#define GPIO_PORT_W201_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos)                /*!< GPIO_PORT W201: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W202  -----------------------------------------
+#define GPIO_PORT_W202_PWORD_Pos                              0                                                         /*!< GPIO_PORT W202: PWORD Position      */
+#define GPIO_PORT_W202_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos)                /*!< GPIO_PORT W202: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W203  -----------------------------------------
+#define GPIO_PORT_W203_PWORD_Pos                              0                                                         /*!< GPIO_PORT W203: PWORD Position      */
+#define GPIO_PORT_W203_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos)                /*!< GPIO_PORT W203: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W204  -----------------------------------------
+#define GPIO_PORT_W204_PWORD_Pos                              0                                                         /*!< GPIO_PORT W204: PWORD Position      */
+#define GPIO_PORT_W204_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos)                /*!< GPIO_PORT W204: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W205  -----------------------------------------
+#define GPIO_PORT_W205_PWORD_Pos                              0                                                         /*!< GPIO_PORT W205: PWORD Position      */
+#define GPIO_PORT_W205_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos)                /*!< GPIO_PORT W205: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W206  -----------------------------------------
+#define GPIO_PORT_W206_PWORD_Pos                              0                                                         /*!< GPIO_PORT W206: PWORD Position      */
+#define GPIO_PORT_W206_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos)                /*!< GPIO_PORT W206: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W207  -----------------------------------------
+#define GPIO_PORT_W207_PWORD_Pos                              0                                                         /*!< GPIO_PORT W207: PWORD Position      */
+#define GPIO_PORT_W207_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos)                /*!< GPIO_PORT W207: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W208  -----------------------------------------
+#define GPIO_PORT_W208_PWORD_Pos                              0                                                         /*!< GPIO_PORT W208: PWORD Position      */
+#define GPIO_PORT_W208_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos)                /*!< GPIO_PORT W208: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W209  -----------------------------------------
+#define GPIO_PORT_W209_PWORD_Pos                              0                                                         /*!< GPIO_PORT W209: PWORD Position      */
+#define GPIO_PORT_W209_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos)                /*!< GPIO_PORT W209: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W210  -----------------------------------------
+#define GPIO_PORT_W210_PWORD_Pos                              0                                                         /*!< GPIO_PORT W210: PWORD Position      */
+#define GPIO_PORT_W210_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos)                /*!< GPIO_PORT W210: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W211  -----------------------------------------
+#define GPIO_PORT_W211_PWORD_Pos                              0                                                         /*!< GPIO_PORT W211: PWORD Position      */
+#define GPIO_PORT_W211_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos)                /*!< GPIO_PORT W211: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W212  -----------------------------------------
+#define GPIO_PORT_W212_PWORD_Pos                              0                                                         /*!< GPIO_PORT W212: PWORD Position      */
+#define GPIO_PORT_W212_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos)                /*!< GPIO_PORT W212: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W213  -----------------------------------------
+#define GPIO_PORT_W213_PWORD_Pos                              0                                                         /*!< GPIO_PORT W213: PWORD Position      */
+#define GPIO_PORT_W213_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos)                /*!< GPIO_PORT W213: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W214  -----------------------------------------
+#define GPIO_PORT_W214_PWORD_Pos                              0                                                         /*!< GPIO_PORT W214: PWORD Position      */
+#define GPIO_PORT_W214_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos)                /*!< GPIO_PORT W214: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W215  -----------------------------------------
+#define GPIO_PORT_W215_PWORD_Pos                              0                                                         /*!< GPIO_PORT W215: PWORD Position      */
+#define GPIO_PORT_W215_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos)                /*!< GPIO_PORT W215: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W216  -----------------------------------------
+#define GPIO_PORT_W216_PWORD_Pos                              0                                                         /*!< GPIO_PORT W216: PWORD Position      */
+#define GPIO_PORT_W216_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos)                /*!< GPIO_PORT W216: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W217  -----------------------------------------
+#define GPIO_PORT_W217_PWORD_Pos                              0                                                         /*!< GPIO_PORT W217: PWORD Position      */
+#define GPIO_PORT_W217_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos)                /*!< GPIO_PORT W217: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W218  -----------------------------------------
+#define GPIO_PORT_W218_PWORD_Pos                              0                                                         /*!< GPIO_PORT W218: PWORD Position      */
+#define GPIO_PORT_W218_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos)                /*!< GPIO_PORT W218: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W219  -----------------------------------------
+#define GPIO_PORT_W219_PWORD_Pos                              0                                                         /*!< GPIO_PORT W219: PWORD Position      */
+#define GPIO_PORT_W219_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos)                /*!< GPIO_PORT W219: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W220  -----------------------------------------
+#define GPIO_PORT_W220_PWORD_Pos                              0                                                         /*!< GPIO_PORT W220: PWORD Position      */
+#define GPIO_PORT_W220_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos)                /*!< GPIO_PORT W220: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W221  -----------------------------------------
+#define GPIO_PORT_W221_PWORD_Pos                              0                                                         /*!< GPIO_PORT W221: PWORD Position      */
+#define GPIO_PORT_W221_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos)                /*!< GPIO_PORT W221: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W222  -----------------------------------------
+#define GPIO_PORT_W222_PWORD_Pos                              0                                                         /*!< GPIO_PORT W222: PWORD Position      */
+#define GPIO_PORT_W222_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos)                /*!< GPIO_PORT W222: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W223  -----------------------------------------
+#define GPIO_PORT_W223_PWORD_Pos                              0                                                         /*!< GPIO_PORT W223: PWORD Position      */
+#define GPIO_PORT_W223_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos)                /*!< GPIO_PORT W223: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W224  -----------------------------------------
+#define GPIO_PORT_W224_PWORD_Pos                              0                                                         /*!< GPIO_PORT W224: PWORD Position      */
+#define GPIO_PORT_W224_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos)                /*!< GPIO_PORT W224: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W225  -----------------------------------------
+#define GPIO_PORT_W225_PWORD_Pos                              0                                                         /*!< GPIO_PORT W225: PWORD Position      */
+#define GPIO_PORT_W225_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos)                /*!< GPIO_PORT W225: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W226  -----------------------------------------
+#define GPIO_PORT_W226_PWORD_Pos                              0                                                         /*!< GPIO_PORT W226: PWORD Position      */
+#define GPIO_PORT_W226_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos)                /*!< GPIO_PORT W226: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W227  -----------------------------------------
+#define GPIO_PORT_W227_PWORD_Pos                              0                                                         /*!< GPIO_PORT W227: PWORD Position      */
+#define GPIO_PORT_W227_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos)                /*!< GPIO_PORT W227: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W228  -----------------------------------------
+#define GPIO_PORT_W228_PWORD_Pos                              0                                                         /*!< GPIO_PORT W228: PWORD Position      */
+#define GPIO_PORT_W228_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos)                /*!< GPIO_PORT W228: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W229  -----------------------------------------
+#define GPIO_PORT_W229_PWORD_Pos                              0                                                         /*!< GPIO_PORT W229: PWORD Position      */
+#define GPIO_PORT_W229_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos)                /*!< GPIO_PORT W229: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W230  -----------------------------------------
+#define GPIO_PORT_W230_PWORD_Pos                              0                                                         /*!< GPIO_PORT W230: PWORD Position      */
+#define GPIO_PORT_W230_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos)                /*!< GPIO_PORT W230: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W231  -----------------------------------------
+#define GPIO_PORT_W231_PWORD_Pos                              0                                                         /*!< GPIO_PORT W231: PWORD Position      */
+#define GPIO_PORT_W231_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos)                /*!< GPIO_PORT W231: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W232  -----------------------------------------
+#define GPIO_PORT_W232_PWORD_Pos                              0                                                         /*!< GPIO_PORT W232: PWORD Position      */
+#define GPIO_PORT_W232_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos)                /*!< GPIO_PORT W232: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W233  -----------------------------------------
+#define GPIO_PORT_W233_PWORD_Pos                              0                                                         /*!< GPIO_PORT W233: PWORD Position      */
+#define GPIO_PORT_W233_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos)                /*!< GPIO_PORT W233: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W234  -----------------------------------------
+#define GPIO_PORT_W234_PWORD_Pos                              0                                                         /*!< GPIO_PORT W234: PWORD Position      */
+#define GPIO_PORT_W234_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos)                /*!< GPIO_PORT W234: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W235  -----------------------------------------
+#define GPIO_PORT_W235_PWORD_Pos                              0                                                         /*!< GPIO_PORT W235: PWORD Position      */
+#define GPIO_PORT_W235_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos)                /*!< GPIO_PORT W235: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W236  -----------------------------------------
+#define GPIO_PORT_W236_PWORD_Pos                              0                                                         /*!< GPIO_PORT W236: PWORD Position      */
+#define GPIO_PORT_W236_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos)                /*!< GPIO_PORT W236: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W237  -----------------------------------------
+#define GPIO_PORT_W237_PWORD_Pos                              0                                                         /*!< GPIO_PORT W237: PWORD Position      */
+#define GPIO_PORT_W237_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos)                /*!< GPIO_PORT W237: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W238  -----------------------------------------
+#define GPIO_PORT_W238_PWORD_Pos                              0                                                         /*!< GPIO_PORT W238: PWORD Position      */
+#define GPIO_PORT_W238_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos)                /*!< GPIO_PORT W238: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W239  -----------------------------------------
+#define GPIO_PORT_W239_PWORD_Pos                              0                                                         /*!< GPIO_PORT W239: PWORD Position      */
+#define GPIO_PORT_W239_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos)                /*!< GPIO_PORT W239: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W240  -----------------------------------------
+#define GPIO_PORT_W240_PWORD_Pos                              0                                                         /*!< GPIO_PORT W240: PWORD Position      */
+#define GPIO_PORT_W240_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos)                /*!< GPIO_PORT W240: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W241  -----------------------------------------
+#define GPIO_PORT_W241_PWORD_Pos                              0                                                         /*!< GPIO_PORT W241: PWORD Position      */
+#define GPIO_PORT_W241_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos)                /*!< GPIO_PORT W241: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W242  -----------------------------------------
+#define GPIO_PORT_W242_PWORD_Pos                              0                                                         /*!< GPIO_PORT W242: PWORD Position      */
+#define GPIO_PORT_W242_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos)                /*!< GPIO_PORT W242: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W243  -----------------------------------------
+#define GPIO_PORT_W243_PWORD_Pos                              0                                                         /*!< GPIO_PORT W243: PWORD Position      */
+#define GPIO_PORT_W243_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos)                /*!< GPIO_PORT W243: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W244  -----------------------------------------
+#define GPIO_PORT_W244_PWORD_Pos                              0                                                         /*!< GPIO_PORT W244: PWORD Position      */
+#define GPIO_PORT_W244_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos)                /*!< GPIO_PORT W244: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W245  -----------------------------------------
+#define GPIO_PORT_W245_PWORD_Pos                              0                                                         /*!< GPIO_PORT W245: PWORD Position      */
+#define GPIO_PORT_W245_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos)                /*!< GPIO_PORT W245: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W246  -----------------------------------------
+#define GPIO_PORT_W246_PWORD_Pos                              0                                                         /*!< GPIO_PORT W246: PWORD Position      */
+#define GPIO_PORT_W246_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos)                /*!< GPIO_PORT W246: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W247  -----------------------------------------
+#define GPIO_PORT_W247_PWORD_Pos                              0                                                         /*!< GPIO_PORT W247: PWORD Position      */
+#define GPIO_PORT_W247_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos)                /*!< GPIO_PORT W247: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W248  -----------------------------------------
+#define GPIO_PORT_W248_PWORD_Pos                              0                                                         /*!< GPIO_PORT W248: PWORD Position      */
+#define GPIO_PORT_W248_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos)                /*!< GPIO_PORT W248: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W249  -----------------------------------------
+#define GPIO_PORT_W249_PWORD_Pos                              0                                                         /*!< GPIO_PORT W249: PWORD Position      */
+#define GPIO_PORT_W249_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos)                /*!< GPIO_PORT W249: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W250  -----------------------------------------
+#define GPIO_PORT_W250_PWORD_Pos                              0                                                         /*!< GPIO_PORT W250: PWORD Position      */
+#define GPIO_PORT_W250_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos)                /*!< GPIO_PORT W250: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W251  -----------------------------------------
+#define GPIO_PORT_W251_PWORD_Pos                              0                                                         /*!< GPIO_PORT W251: PWORD Position      */
+#define GPIO_PORT_W251_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos)                /*!< GPIO_PORT W251: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W252  -----------------------------------------
+#define GPIO_PORT_W252_PWORD_Pos                              0                                                         /*!< GPIO_PORT W252: PWORD Position      */
+#define GPIO_PORT_W252_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos)                /*!< GPIO_PORT W252: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W253  -----------------------------------------
+#define GPIO_PORT_W253_PWORD_Pos                              0                                                         /*!< GPIO_PORT W253: PWORD Position      */
+#define GPIO_PORT_W253_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos)                /*!< GPIO_PORT W253: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W254  -----------------------------------------
+#define GPIO_PORT_W254_PWORD_Pos                              0                                                         /*!< GPIO_PORT W254: PWORD Position      */
+#define GPIO_PORT_W254_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos)                /*!< GPIO_PORT W254: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_W255  -----------------------------------------
+#define GPIO_PORT_W255_PWORD_Pos                              0                                                         /*!< GPIO_PORT W255: PWORD Position      */
+#define GPIO_PORT_W255_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos)                /*!< GPIO_PORT W255: PWORD Mask          */
+
+// -------------------------------------  GPIO_PORT_DIR0  -----------------------------------------
+#define GPIO_PORT_DIR0_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR0: DIRP0 Position      */
+#define GPIO_PORT_DIR0_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos)                      /*!< GPIO_PORT DIR0: DIRP0 Mask          */
+#define GPIO_PORT_DIR0_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR0: DIRP1 Position      */
+#define GPIO_PORT_DIR0_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos)                      /*!< GPIO_PORT DIR0: DIRP1 Mask          */
+#define GPIO_PORT_DIR0_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR0: DIRP2 Position      */
+#define GPIO_PORT_DIR0_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos)                      /*!< GPIO_PORT DIR0: DIRP2 Mask          */
+#define GPIO_PORT_DIR0_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR0: DIRP3 Position      */
+#define GPIO_PORT_DIR0_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos)                      /*!< GPIO_PORT DIR0: DIRP3 Mask          */
+#define GPIO_PORT_DIR0_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR0: DIRP4 Position      */
+#define GPIO_PORT_DIR0_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos)                      /*!< GPIO_PORT DIR0: DIRP4 Mask          */
+#define GPIO_PORT_DIR0_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR0: DIRP5 Position      */
+#define GPIO_PORT_DIR0_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos)                      /*!< GPIO_PORT DIR0: DIRP5 Mask          */
+#define GPIO_PORT_DIR0_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR0: DIRP6 Position      */
+#define GPIO_PORT_DIR0_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos)                      /*!< GPIO_PORT DIR0: DIRP6 Mask          */
+#define GPIO_PORT_DIR0_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR0: DIRP7 Position      */
+#define GPIO_PORT_DIR0_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos)                      /*!< GPIO_PORT DIR0: DIRP7 Mask          */
+#define GPIO_PORT_DIR0_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR0: DIRP8 Position      */
+#define GPIO_PORT_DIR0_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos)                      /*!< GPIO_PORT DIR0: DIRP8 Mask          */
+#define GPIO_PORT_DIR0_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR0: DIRP9 Position      */
+#define GPIO_PORT_DIR0_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos)                      /*!< GPIO_PORT DIR0: DIRP9 Mask          */
+#define GPIO_PORT_DIR0_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR0: DIRP10 Position     */
+#define GPIO_PORT_DIR0_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos)                     /*!< GPIO_PORT DIR0: DIRP10 Mask         */
+#define GPIO_PORT_DIR0_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR0: DIRP11 Position     */
+#define GPIO_PORT_DIR0_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos)                     /*!< GPIO_PORT DIR0: DIRP11 Mask         */
+#define GPIO_PORT_DIR0_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR0: DIRP12 Position     */
+#define GPIO_PORT_DIR0_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos)                     /*!< GPIO_PORT DIR0: DIRP12 Mask         */
+#define GPIO_PORT_DIR0_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR0: DIRP13 Position     */
+#define GPIO_PORT_DIR0_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos)                     /*!< GPIO_PORT DIR0: DIRP13 Mask         */
+#define GPIO_PORT_DIR0_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR0: DIRP14 Position     */
+#define GPIO_PORT_DIR0_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos)                     /*!< GPIO_PORT DIR0: DIRP14 Mask         */
+#define GPIO_PORT_DIR0_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR0: DIRP15 Position     */
+#define GPIO_PORT_DIR0_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos)                     /*!< GPIO_PORT DIR0: DIRP15 Mask         */
+#define GPIO_PORT_DIR0_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR0: DIRP16 Position     */
+#define GPIO_PORT_DIR0_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos)                     /*!< GPIO_PORT DIR0: DIRP16 Mask         */
+#define GPIO_PORT_DIR0_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR0: DIRP17 Position     */
+#define GPIO_PORT_DIR0_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos)                     /*!< GPIO_PORT DIR0: DIRP17 Mask         */
+#define GPIO_PORT_DIR0_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR0: DIRP18 Position     */
+#define GPIO_PORT_DIR0_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos)                     /*!< GPIO_PORT DIR0: DIRP18 Mask         */
+#define GPIO_PORT_DIR0_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR0: DIRP19 Position     */
+#define GPIO_PORT_DIR0_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos)                     /*!< GPIO_PORT DIR0: DIRP19 Mask         */
+#define GPIO_PORT_DIR0_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR0: DIRP20 Position     */
+#define GPIO_PORT_DIR0_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos)                     /*!< GPIO_PORT DIR0: DIRP20 Mask         */
+#define GPIO_PORT_DIR0_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR0: DIRP21 Position     */
+#define GPIO_PORT_DIR0_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos)                     /*!< GPIO_PORT DIR0: DIRP21 Mask         */
+#define GPIO_PORT_DIR0_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR0: DIRP22 Position     */
+#define GPIO_PORT_DIR0_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos)                     /*!< GPIO_PORT DIR0: DIRP22 Mask         */
+#define GPIO_PORT_DIR0_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR0: DIRP23 Position     */
+#define GPIO_PORT_DIR0_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos)                     /*!< GPIO_PORT DIR0: DIRP23 Mask         */
+#define GPIO_PORT_DIR0_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR0: DIRP24 Position     */
+#define GPIO_PORT_DIR0_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos)                     /*!< GPIO_PORT DIR0: DIRP24 Mask         */
+#define GPIO_PORT_DIR0_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR0: DIRP25 Position     */
+#define GPIO_PORT_DIR0_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos)                     /*!< GPIO_PORT DIR0: DIRP25 Mask         */
+#define GPIO_PORT_DIR0_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR0: DIRP26 Position     */
+#define GPIO_PORT_DIR0_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos)                     /*!< GPIO_PORT DIR0: DIRP26 Mask         */
+#define GPIO_PORT_DIR0_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR0: DIRP27 Position     */
+#define GPIO_PORT_DIR0_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos)                     /*!< GPIO_PORT DIR0: DIRP27 Mask         */
+#define GPIO_PORT_DIR0_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR0: DIRP28 Position     */
+#define GPIO_PORT_DIR0_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos)                     /*!< GPIO_PORT DIR0: DIRP28 Mask         */
+#define GPIO_PORT_DIR0_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR0: DIRP29 Position     */
+#define GPIO_PORT_DIR0_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos)                     /*!< GPIO_PORT DIR0: DIRP29 Mask         */
+#define GPIO_PORT_DIR0_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR0: DIRP30 Position     */
+#define GPIO_PORT_DIR0_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos)                     /*!< GPIO_PORT DIR0: DIRP30 Mask         */
+#define GPIO_PORT_DIR0_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR0: DIRP31 Position     */
+#define GPIO_PORT_DIR0_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos)                     /*!< GPIO_PORT DIR0: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR1  -----------------------------------------
+#define GPIO_PORT_DIR1_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR1: DIRP0 Position      */
+#define GPIO_PORT_DIR1_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos)                      /*!< GPIO_PORT DIR1: DIRP0 Mask          */
+#define GPIO_PORT_DIR1_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR1: DIRP1 Position      */
+#define GPIO_PORT_DIR1_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos)                      /*!< GPIO_PORT DIR1: DIRP1 Mask          */
+#define GPIO_PORT_DIR1_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR1: DIRP2 Position      */
+#define GPIO_PORT_DIR1_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos)                      /*!< GPIO_PORT DIR1: DIRP2 Mask          */
+#define GPIO_PORT_DIR1_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR1: DIRP3 Position      */
+#define GPIO_PORT_DIR1_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos)                      /*!< GPIO_PORT DIR1: DIRP3 Mask          */
+#define GPIO_PORT_DIR1_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR1: DIRP4 Position      */
+#define GPIO_PORT_DIR1_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos)                      /*!< GPIO_PORT DIR1: DIRP4 Mask          */
+#define GPIO_PORT_DIR1_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR1: DIRP5 Position      */
+#define GPIO_PORT_DIR1_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos)                      /*!< GPIO_PORT DIR1: DIRP5 Mask          */
+#define GPIO_PORT_DIR1_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR1: DIRP6 Position      */
+#define GPIO_PORT_DIR1_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos)                      /*!< GPIO_PORT DIR1: DIRP6 Mask          */
+#define GPIO_PORT_DIR1_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR1: DIRP7 Position      */
+#define GPIO_PORT_DIR1_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos)                      /*!< GPIO_PORT DIR1: DIRP7 Mask          */
+#define GPIO_PORT_DIR1_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR1: DIRP8 Position      */
+#define GPIO_PORT_DIR1_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos)                      /*!< GPIO_PORT DIR1: DIRP8 Mask          */
+#define GPIO_PORT_DIR1_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR1: DIRP9 Position      */
+#define GPIO_PORT_DIR1_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos)                      /*!< GPIO_PORT DIR1: DIRP9 Mask          */
+#define GPIO_PORT_DIR1_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR1: DIRP10 Position     */
+#define GPIO_PORT_DIR1_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos)                     /*!< GPIO_PORT DIR1: DIRP10 Mask         */
+#define GPIO_PORT_DIR1_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR1: DIRP11 Position     */
+#define GPIO_PORT_DIR1_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos)                     /*!< GPIO_PORT DIR1: DIRP11 Mask         */
+#define GPIO_PORT_DIR1_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR1: DIRP12 Position     */
+#define GPIO_PORT_DIR1_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos)                     /*!< GPIO_PORT DIR1: DIRP12 Mask         */
+#define GPIO_PORT_DIR1_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR1: DIRP13 Position     */
+#define GPIO_PORT_DIR1_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos)                     /*!< GPIO_PORT DIR1: DIRP13 Mask         */
+#define GPIO_PORT_DIR1_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR1: DIRP14 Position     */
+#define GPIO_PORT_DIR1_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos)                     /*!< GPIO_PORT DIR1: DIRP14 Mask         */
+#define GPIO_PORT_DIR1_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR1: DIRP15 Position     */
+#define GPIO_PORT_DIR1_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos)                     /*!< GPIO_PORT DIR1: DIRP15 Mask         */
+#define GPIO_PORT_DIR1_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR1: DIRP16 Position     */
+#define GPIO_PORT_DIR1_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos)                     /*!< GPIO_PORT DIR1: DIRP16 Mask         */
+#define GPIO_PORT_DIR1_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR1: DIRP17 Position     */
+#define GPIO_PORT_DIR1_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos)                     /*!< GPIO_PORT DIR1: DIRP17 Mask         */
+#define GPIO_PORT_DIR1_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR1: DIRP18 Position     */
+#define GPIO_PORT_DIR1_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos)                     /*!< GPIO_PORT DIR1: DIRP18 Mask         */
+#define GPIO_PORT_DIR1_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR1: DIRP19 Position     */
+#define GPIO_PORT_DIR1_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos)                     /*!< GPIO_PORT DIR1: DIRP19 Mask         */
+#define GPIO_PORT_DIR1_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR1: DIRP20 Position     */
+#define GPIO_PORT_DIR1_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos)                     /*!< GPIO_PORT DIR1: DIRP20 Mask         */
+#define GPIO_PORT_DIR1_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR1: DIRP21 Position     */
+#define GPIO_PORT_DIR1_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos)                     /*!< GPIO_PORT DIR1: DIRP21 Mask         */
+#define GPIO_PORT_DIR1_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR1: DIRP22 Position     */
+#define GPIO_PORT_DIR1_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos)                     /*!< GPIO_PORT DIR1: DIRP22 Mask         */
+#define GPIO_PORT_DIR1_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR1: DIRP23 Position     */
+#define GPIO_PORT_DIR1_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos)                     /*!< GPIO_PORT DIR1: DIRP23 Mask         */
+#define GPIO_PORT_DIR1_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR1: DIRP24 Position     */
+#define GPIO_PORT_DIR1_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos)                     /*!< GPIO_PORT DIR1: DIRP24 Mask         */
+#define GPIO_PORT_DIR1_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR1: DIRP25 Position     */
+#define GPIO_PORT_DIR1_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos)                     /*!< GPIO_PORT DIR1: DIRP25 Mask         */
+#define GPIO_PORT_DIR1_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR1: DIRP26 Position     */
+#define GPIO_PORT_DIR1_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos)                     /*!< GPIO_PORT DIR1: DIRP26 Mask         */
+#define GPIO_PORT_DIR1_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR1: DIRP27 Position     */
+#define GPIO_PORT_DIR1_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos)                     /*!< GPIO_PORT DIR1: DIRP27 Mask         */
+#define GPIO_PORT_DIR1_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR1: DIRP28 Position     */
+#define GPIO_PORT_DIR1_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos)                     /*!< GPIO_PORT DIR1: DIRP28 Mask         */
+#define GPIO_PORT_DIR1_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR1: DIRP29 Position     */
+#define GPIO_PORT_DIR1_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos)                     /*!< GPIO_PORT DIR1: DIRP29 Mask         */
+#define GPIO_PORT_DIR1_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR1: DIRP30 Position     */
+#define GPIO_PORT_DIR1_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos)                     /*!< GPIO_PORT DIR1: DIRP30 Mask         */
+#define GPIO_PORT_DIR1_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR1: DIRP31 Position     */
+#define GPIO_PORT_DIR1_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos)                     /*!< GPIO_PORT DIR1: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR2  -----------------------------------------
+#define GPIO_PORT_DIR2_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR2: DIRP0 Position      */
+#define GPIO_PORT_DIR2_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos)                      /*!< GPIO_PORT DIR2: DIRP0 Mask          */
+#define GPIO_PORT_DIR2_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR2: DIRP1 Position      */
+#define GPIO_PORT_DIR2_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos)                      /*!< GPIO_PORT DIR2: DIRP1 Mask          */
+#define GPIO_PORT_DIR2_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR2: DIRP2 Position      */
+#define GPIO_PORT_DIR2_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos)                      /*!< GPIO_PORT DIR2: DIRP2 Mask          */
+#define GPIO_PORT_DIR2_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR2: DIRP3 Position      */
+#define GPIO_PORT_DIR2_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos)                      /*!< GPIO_PORT DIR2: DIRP3 Mask          */
+#define GPIO_PORT_DIR2_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR2: DIRP4 Position      */
+#define GPIO_PORT_DIR2_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos)                      /*!< GPIO_PORT DIR2: DIRP4 Mask          */
+#define GPIO_PORT_DIR2_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR2: DIRP5 Position      */
+#define GPIO_PORT_DIR2_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos)                      /*!< GPIO_PORT DIR2: DIRP5 Mask          */
+#define GPIO_PORT_DIR2_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR2: DIRP6 Position      */
+#define GPIO_PORT_DIR2_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos)                      /*!< GPIO_PORT DIR2: DIRP6 Mask          */
+#define GPIO_PORT_DIR2_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR2: DIRP7 Position      */
+#define GPIO_PORT_DIR2_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos)                      /*!< GPIO_PORT DIR2: DIRP7 Mask          */
+#define GPIO_PORT_DIR2_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR2: DIRP8 Position      */
+#define GPIO_PORT_DIR2_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos)                      /*!< GPIO_PORT DIR2: DIRP8 Mask          */
+#define GPIO_PORT_DIR2_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR2: DIRP9 Position      */
+#define GPIO_PORT_DIR2_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos)                      /*!< GPIO_PORT DIR2: DIRP9 Mask          */
+#define GPIO_PORT_DIR2_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR2: DIRP10 Position     */
+#define GPIO_PORT_DIR2_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos)                     /*!< GPIO_PORT DIR2: DIRP10 Mask         */
+#define GPIO_PORT_DIR2_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR2: DIRP11 Position     */
+#define GPIO_PORT_DIR2_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos)                     /*!< GPIO_PORT DIR2: DIRP11 Mask         */
+#define GPIO_PORT_DIR2_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR2: DIRP12 Position     */
+#define GPIO_PORT_DIR2_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos)                     /*!< GPIO_PORT DIR2: DIRP12 Mask         */
+#define GPIO_PORT_DIR2_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR2: DIRP13 Position     */
+#define GPIO_PORT_DIR2_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos)                     /*!< GPIO_PORT DIR2: DIRP13 Mask         */
+#define GPIO_PORT_DIR2_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR2: DIRP14 Position     */
+#define GPIO_PORT_DIR2_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos)                     /*!< GPIO_PORT DIR2: DIRP14 Mask         */
+#define GPIO_PORT_DIR2_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR2: DIRP15 Position     */
+#define GPIO_PORT_DIR2_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos)                     /*!< GPIO_PORT DIR2: DIRP15 Mask         */
+#define GPIO_PORT_DIR2_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR2: DIRP16 Position     */
+#define GPIO_PORT_DIR2_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos)                     /*!< GPIO_PORT DIR2: DIRP16 Mask         */
+#define GPIO_PORT_DIR2_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR2: DIRP17 Position     */
+#define GPIO_PORT_DIR2_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos)                     /*!< GPIO_PORT DIR2: DIRP17 Mask         */
+#define GPIO_PORT_DIR2_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR2: DIRP18 Position     */
+#define GPIO_PORT_DIR2_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos)                     /*!< GPIO_PORT DIR2: DIRP18 Mask         */
+#define GPIO_PORT_DIR2_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR2: DIRP19 Position     */
+#define GPIO_PORT_DIR2_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos)                     /*!< GPIO_PORT DIR2: DIRP19 Mask         */
+#define GPIO_PORT_DIR2_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR2: DIRP20 Position     */
+#define GPIO_PORT_DIR2_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos)                     /*!< GPIO_PORT DIR2: DIRP20 Mask         */
+#define GPIO_PORT_DIR2_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR2: DIRP21 Position     */
+#define GPIO_PORT_DIR2_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos)                     /*!< GPIO_PORT DIR2: DIRP21 Mask         */
+#define GPIO_PORT_DIR2_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR2: DIRP22 Position     */
+#define GPIO_PORT_DIR2_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos)                     /*!< GPIO_PORT DIR2: DIRP22 Mask         */
+#define GPIO_PORT_DIR2_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR2: DIRP23 Position     */
+#define GPIO_PORT_DIR2_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos)                     /*!< GPIO_PORT DIR2: DIRP23 Mask         */
+#define GPIO_PORT_DIR2_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR2: DIRP24 Position     */
+#define GPIO_PORT_DIR2_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos)                     /*!< GPIO_PORT DIR2: DIRP24 Mask         */
+#define GPIO_PORT_DIR2_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR2: DIRP25 Position     */
+#define GPIO_PORT_DIR2_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos)                     /*!< GPIO_PORT DIR2: DIRP25 Mask         */
+#define GPIO_PORT_DIR2_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR2: DIRP26 Position     */
+#define GPIO_PORT_DIR2_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos)                     /*!< GPIO_PORT DIR2: DIRP26 Mask         */
+#define GPIO_PORT_DIR2_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR2: DIRP27 Position     */
+#define GPIO_PORT_DIR2_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos)                     /*!< GPIO_PORT DIR2: DIRP27 Mask         */
+#define GPIO_PORT_DIR2_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR2: DIRP28 Position     */
+#define GPIO_PORT_DIR2_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos)                     /*!< GPIO_PORT DIR2: DIRP28 Mask         */
+#define GPIO_PORT_DIR2_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR2: DIRP29 Position     */
+#define GPIO_PORT_DIR2_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos)                     /*!< GPIO_PORT DIR2: DIRP29 Mask         */
+#define GPIO_PORT_DIR2_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR2: DIRP30 Position     */
+#define GPIO_PORT_DIR2_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos)                     /*!< GPIO_PORT DIR2: DIRP30 Mask         */
+#define GPIO_PORT_DIR2_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR2: DIRP31 Position     */
+#define GPIO_PORT_DIR2_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos)                     /*!< GPIO_PORT DIR2: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR3  -----------------------------------------
+#define GPIO_PORT_DIR3_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR3: DIRP0 Position      */
+#define GPIO_PORT_DIR3_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos)                      /*!< GPIO_PORT DIR3: DIRP0 Mask          */
+#define GPIO_PORT_DIR3_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR3: DIRP1 Position      */
+#define GPIO_PORT_DIR3_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos)                      /*!< GPIO_PORT DIR3: DIRP1 Mask          */
+#define GPIO_PORT_DIR3_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR3: DIRP2 Position      */
+#define GPIO_PORT_DIR3_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos)                      /*!< GPIO_PORT DIR3: DIRP2 Mask          */
+#define GPIO_PORT_DIR3_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR3: DIRP3 Position      */
+#define GPIO_PORT_DIR3_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos)                      /*!< GPIO_PORT DIR3: DIRP3 Mask          */
+#define GPIO_PORT_DIR3_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR3: DIRP4 Position      */
+#define GPIO_PORT_DIR3_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos)                      /*!< GPIO_PORT DIR3: DIRP4 Mask          */
+#define GPIO_PORT_DIR3_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR3: DIRP5 Position      */
+#define GPIO_PORT_DIR3_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos)                      /*!< GPIO_PORT DIR3: DIRP5 Mask          */
+#define GPIO_PORT_DIR3_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR3: DIRP6 Position      */
+#define GPIO_PORT_DIR3_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos)                      /*!< GPIO_PORT DIR3: DIRP6 Mask          */
+#define GPIO_PORT_DIR3_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR3: DIRP7 Position      */
+#define GPIO_PORT_DIR3_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos)                      /*!< GPIO_PORT DIR3: DIRP7 Mask          */
+#define GPIO_PORT_DIR3_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR3: DIRP8 Position      */
+#define GPIO_PORT_DIR3_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos)                      /*!< GPIO_PORT DIR3: DIRP8 Mask          */
+#define GPIO_PORT_DIR3_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR3: DIRP9 Position      */
+#define GPIO_PORT_DIR3_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos)                      /*!< GPIO_PORT DIR3: DIRP9 Mask          */
+#define GPIO_PORT_DIR3_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR3: DIRP10 Position     */
+#define GPIO_PORT_DIR3_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos)                     /*!< GPIO_PORT DIR3: DIRP10 Mask         */
+#define GPIO_PORT_DIR3_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR3: DIRP11 Position     */
+#define GPIO_PORT_DIR3_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos)                     /*!< GPIO_PORT DIR3: DIRP11 Mask         */
+#define GPIO_PORT_DIR3_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR3: DIRP12 Position     */
+#define GPIO_PORT_DIR3_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos)                     /*!< GPIO_PORT DIR3: DIRP12 Mask         */
+#define GPIO_PORT_DIR3_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR3: DIRP13 Position     */
+#define GPIO_PORT_DIR3_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos)                     /*!< GPIO_PORT DIR3: DIRP13 Mask         */
+#define GPIO_PORT_DIR3_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR3: DIRP14 Position     */
+#define GPIO_PORT_DIR3_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos)                     /*!< GPIO_PORT DIR3: DIRP14 Mask         */
+#define GPIO_PORT_DIR3_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR3: DIRP15 Position     */
+#define GPIO_PORT_DIR3_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos)                     /*!< GPIO_PORT DIR3: DIRP15 Mask         */
+#define GPIO_PORT_DIR3_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR3: DIRP16 Position     */
+#define GPIO_PORT_DIR3_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos)                     /*!< GPIO_PORT DIR3: DIRP16 Mask         */
+#define GPIO_PORT_DIR3_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR3: DIRP17 Position     */
+#define GPIO_PORT_DIR3_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos)                     /*!< GPIO_PORT DIR3: DIRP17 Mask         */
+#define GPIO_PORT_DIR3_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR3: DIRP18 Position     */
+#define GPIO_PORT_DIR3_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos)                     /*!< GPIO_PORT DIR3: DIRP18 Mask         */
+#define GPIO_PORT_DIR3_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR3: DIRP19 Position     */
+#define GPIO_PORT_DIR3_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos)                     /*!< GPIO_PORT DIR3: DIRP19 Mask         */
+#define GPIO_PORT_DIR3_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR3: DIRP20 Position     */
+#define GPIO_PORT_DIR3_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos)                     /*!< GPIO_PORT DIR3: DIRP20 Mask         */
+#define GPIO_PORT_DIR3_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR3: DIRP21 Position     */
+#define GPIO_PORT_DIR3_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos)                     /*!< GPIO_PORT DIR3: DIRP21 Mask         */
+#define GPIO_PORT_DIR3_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR3: DIRP22 Position     */
+#define GPIO_PORT_DIR3_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos)                     /*!< GPIO_PORT DIR3: DIRP22 Mask         */
+#define GPIO_PORT_DIR3_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR3: DIRP23 Position     */
+#define GPIO_PORT_DIR3_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos)                     /*!< GPIO_PORT DIR3: DIRP23 Mask         */
+#define GPIO_PORT_DIR3_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR3: DIRP24 Position     */
+#define GPIO_PORT_DIR3_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos)                     /*!< GPIO_PORT DIR3: DIRP24 Mask         */
+#define GPIO_PORT_DIR3_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR3: DIRP25 Position     */
+#define GPIO_PORT_DIR3_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos)                     /*!< GPIO_PORT DIR3: DIRP25 Mask         */
+#define GPIO_PORT_DIR3_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR3: DIRP26 Position     */
+#define GPIO_PORT_DIR3_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos)                     /*!< GPIO_PORT DIR3: DIRP26 Mask         */
+#define GPIO_PORT_DIR3_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR3: DIRP27 Position     */
+#define GPIO_PORT_DIR3_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos)                     /*!< GPIO_PORT DIR3: DIRP27 Mask         */
+#define GPIO_PORT_DIR3_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR3: DIRP28 Position     */
+#define GPIO_PORT_DIR3_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos)                     /*!< GPIO_PORT DIR3: DIRP28 Mask         */
+#define GPIO_PORT_DIR3_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR3: DIRP29 Position     */
+#define GPIO_PORT_DIR3_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos)                     /*!< GPIO_PORT DIR3: DIRP29 Mask         */
+#define GPIO_PORT_DIR3_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR3: DIRP30 Position     */
+#define GPIO_PORT_DIR3_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos)                     /*!< GPIO_PORT DIR3: DIRP30 Mask         */
+#define GPIO_PORT_DIR3_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR3: DIRP31 Position     */
+#define GPIO_PORT_DIR3_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos)                     /*!< GPIO_PORT DIR3: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR4  -----------------------------------------
+#define GPIO_PORT_DIR4_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR4: DIRP0 Position      */
+#define GPIO_PORT_DIR4_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos)                      /*!< GPIO_PORT DIR4: DIRP0 Mask          */
+#define GPIO_PORT_DIR4_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR4: DIRP1 Position      */
+#define GPIO_PORT_DIR4_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos)                      /*!< GPIO_PORT DIR4: DIRP1 Mask          */
+#define GPIO_PORT_DIR4_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR4: DIRP2 Position      */
+#define GPIO_PORT_DIR4_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos)                      /*!< GPIO_PORT DIR4: DIRP2 Mask          */
+#define GPIO_PORT_DIR4_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR4: DIRP3 Position      */
+#define GPIO_PORT_DIR4_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos)                      /*!< GPIO_PORT DIR4: DIRP3 Mask          */
+#define GPIO_PORT_DIR4_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR4: DIRP4 Position      */
+#define GPIO_PORT_DIR4_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos)                      /*!< GPIO_PORT DIR4: DIRP4 Mask          */
+#define GPIO_PORT_DIR4_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR4: DIRP5 Position      */
+#define GPIO_PORT_DIR4_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos)                      /*!< GPIO_PORT DIR4: DIRP5 Mask          */
+#define GPIO_PORT_DIR4_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR4: DIRP6 Position      */
+#define GPIO_PORT_DIR4_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos)                      /*!< GPIO_PORT DIR4: DIRP6 Mask          */
+#define GPIO_PORT_DIR4_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR4: DIRP7 Position      */
+#define GPIO_PORT_DIR4_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos)                      /*!< GPIO_PORT DIR4: DIRP7 Mask          */
+#define GPIO_PORT_DIR4_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR4: DIRP8 Position      */
+#define GPIO_PORT_DIR4_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos)                      /*!< GPIO_PORT DIR4: DIRP8 Mask          */
+#define GPIO_PORT_DIR4_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR4: DIRP9 Position      */
+#define GPIO_PORT_DIR4_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos)                      /*!< GPIO_PORT DIR4: DIRP9 Mask          */
+#define GPIO_PORT_DIR4_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR4: DIRP10 Position     */
+#define GPIO_PORT_DIR4_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos)                     /*!< GPIO_PORT DIR4: DIRP10 Mask         */
+#define GPIO_PORT_DIR4_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR4: DIRP11 Position     */
+#define GPIO_PORT_DIR4_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos)                     /*!< GPIO_PORT DIR4: DIRP11 Mask         */
+#define GPIO_PORT_DIR4_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR4: DIRP12 Position     */
+#define GPIO_PORT_DIR4_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos)                     /*!< GPIO_PORT DIR4: DIRP12 Mask         */
+#define GPIO_PORT_DIR4_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR4: DIRP13 Position     */
+#define GPIO_PORT_DIR4_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos)                     /*!< GPIO_PORT DIR4: DIRP13 Mask         */
+#define GPIO_PORT_DIR4_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR4: DIRP14 Position     */
+#define GPIO_PORT_DIR4_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos)                     /*!< GPIO_PORT DIR4: DIRP14 Mask         */
+#define GPIO_PORT_DIR4_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR4: DIRP15 Position     */
+#define GPIO_PORT_DIR4_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos)                     /*!< GPIO_PORT DIR4: DIRP15 Mask         */
+#define GPIO_PORT_DIR4_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR4: DIRP16 Position     */
+#define GPIO_PORT_DIR4_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos)                     /*!< GPIO_PORT DIR4: DIRP16 Mask         */
+#define GPIO_PORT_DIR4_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR4: DIRP17 Position     */
+#define GPIO_PORT_DIR4_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos)                     /*!< GPIO_PORT DIR4: DIRP17 Mask         */
+#define GPIO_PORT_DIR4_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR4: DIRP18 Position     */
+#define GPIO_PORT_DIR4_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos)                     /*!< GPIO_PORT DIR4: DIRP18 Mask         */
+#define GPIO_PORT_DIR4_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR4: DIRP19 Position     */
+#define GPIO_PORT_DIR4_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos)                     /*!< GPIO_PORT DIR4: DIRP19 Mask         */
+#define GPIO_PORT_DIR4_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR4: DIRP20 Position     */
+#define GPIO_PORT_DIR4_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos)                     /*!< GPIO_PORT DIR4: DIRP20 Mask         */
+#define GPIO_PORT_DIR4_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR4: DIRP21 Position     */
+#define GPIO_PORT_DIR4_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos)                     /*!< GPIO_PORT DIR4: DIRP21 Mask         */
+#define GPIO_PORT_DIR4_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR4: DIRP22 Position     */
+#define GPIO_PORT_DIR4_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos)                     /*!< GPIO_PORT DIR4: DIRP22 Mask         */
+#define GPIO_PORT_DIR4_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR4: DIRP23 Position     */
+#define GPIO_PORT_DIR4_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos)                     /*!< GPIO_PORT DIR4: DIRP23 Mask         */
+#define GPIO_PORT_DIR4_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR4: DIRP24 Position     */
+#define GPIO_PORT_DIR4_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos)                     /*!< GPIO_PORT DIR4: DIRP24 Mask         */
+#define GPIO_PORT_DIR4_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR4: DIRP25 Position     */
+#define GPIO_PORT_DIR4_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos)                     /*!< GPIO_PORT DIR4: DIRP25 Mask         */
+#define GPIO_PORT_DIR4_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR4: DIRP26 Position     */
+#define GPIO_PORT_DIR4_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos)                     /*!< GPIO_PORT DIR4: DIRP26 Mask         */
+#define GPIO_PORT_DIR4_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR4: DIRP27 Position     */
+#define GPIO_PORT_DIR4_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos)                     /*!< GPIO_PORT DIR4: DIRP27 Mask         */
+#define GPIO_PORT_DIR4_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR4: DIRP28 Position     */
+#define GPIO_PORT_DIR4_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos)                     /*!< GPIO_PORT DIR4: DIRP28 Mask         */
+#define GPIO_PORT_DIR4_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR4: DIRP29 Position     */
+#define GPIO_PORT_DIR4_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos)                     /*!< GPIO_PORT DIR4: DIRP29 Mask         */
+#define GPIO_PORT_DIR4_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR4: DIRP30 Position     */
+#define GPIO_PORT_DIR4_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos)                     /*!< GPIO_PORT DIR4: DIRP30 Mask         */
+#define GPIO_PORT_DIR4_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR4: DIRP31 Position     */
+#define GPIO_PORT_DIR4_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos)                     /*!< GPIO_PORT DIR4: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR5  -----------------------------------------
+#define GPIO_PORT_DIR5_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR5: DIRP0 Position      */
+#define GPIO_PORT_DIR5_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos)                      /*!< GPIO_PORT DIR5: DIRP0 Mask          */
+#define GPIO_PORT_DIR5_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR5: DIRP1 Position      */
+#define GPIO_PORT_DIR5_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos)                      /*!< GPIO_PORT DIR5: DIRP1 Mask          */
+#define GPIO_PORT_DIR5_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR5: DIRP2 Position      */
+#define GPIO_PORT_DIR5_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos)                      /*!< GPIO_PORT DIR5: DIRP2 Mask          */
+#define GPIO_PORT_DIR5_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR5: DIRP3 Position      */
+#define GPIO_PORT_DIR5_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos)                      /*!< GPIO_PORT DIR5: DIRP3 Mask          */
+#define GPIO_PORT_DIR5_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR5: DIRP4 Position      */
+#define GPIO_PORT_DIR5_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos)                      /*!< GPIO_PORT DIR5: DIRP4 Mask          */
+#define GPIO_PORT_DIR5_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR5: DIRP5 Position      */
+#define GPIO_PORT_DIR5_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos)                      /*!< GPIO_PORT DIR5: DIRP5 Mask          */
+#define GPIO_PORT_DIR5_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR5: DIRP6 Position      */
+#define GPIO_PORT_DIR5_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos)                      /*!< GPIO_PORT DIR5: DIRP6 Mask          */
+#define GPIO_PORT_DIR5_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR5: DIRP7 Position      */
+#define GPIO_PORT_DIR5_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos)                      /*!< GPIO_PORT DIR5: DIRP7 Mask          */
+#define GPIO_PORT_DIR5_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR5: DIRP8 Position      */
+#define GPIO_PORT_DIR5_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos)                      /*!< GPIO_PORT DIR5: DIRP8 Mask          */
+#define GPIO_PORT_DIR5_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR5: DIRP9 Position      */
+#define GPIO_PORT_DIR5_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos)                      /*!< GPIO_PORT DIR5: DIRP9 Mask          */
+#define GPIO_PORT_DIR5_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR5: DIRP10 Position     */
+#define GPIO_PORT_DIR5_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos)                     /*!< GPIO_PORT DIR5: DIRP10 Mask         */
+#define GPIO_PORT_DIR5_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR5: DIRP11 Position     */
+#define GPIO_PORT_DIR5_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos)                     /*!< GPIO_PORT DIR5: DIRP11 Mask         */
+#define GPIO_PORT_DIR5_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR5: DIRP12 Position     */
+#define GPIO_PORT_DIR5_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos)                     /*!< GPIO_PORT DIR5: DIRP12 Mask         */
+#define GPIO_PORT_DIR5_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR5: DIRP13 Position     */
+#define GPIO_PORT_DIR5_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos)                     /*!< GPIO_PORT DIR5: DIRP13 Mask         */
+#define GPIO_PORT_DIR5_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR5: DIRP14 Position     */
+#define GPIO_PORT_DIR5_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos)                     /*!< GPIO_PORT DIR5: DIRP14 Mask         */
+#define GPIO_PORT_DIR5_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR5: DIRP15 Position     */
+#define GPIO_PORT_DIR5_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos)                     /*!< GPIO_PORT DIR5: DIRP15 Mask         */
+#define GPIO_PORT_DIR5_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR5: DIRP16 Position     */
+#define GPIO_PORT_DIR5_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos)                     /*!< GPIO_PORT DIR5: DIRP16 Mask         */
+#define GPIO_PORT_DIR5_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR5: DIRP17 Position     */
+#define GPIO_PORT_DIR5_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos)                     /*!< GPIO_PORT DIR5: DIRP17 Mask         */
+#define GPIO_PORT_DIR5_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR5: DIRP18 Position     */
+#define GPIO_PORT_DIR5_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos)                     /*!< GPIO_PORT DIR5: DIRP18 Mask         */
+#define GPIO_PORT_DIR5_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR5: DIRP19 Position     */
+#define GPIO_PORT_DIR5_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos)                     /*!< GPIO_PORT DIR5: DIRP19 Mask         */
+#define GPIO_PORT_DIR5_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR5: DIRP20 Position     */
+#define GPIO_PORT_DIR5_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos)                     /*!< GPIO_PORT DIR5: DIRP20 Mask         */
+#define GPIO_PORT_DIR5_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR5: DIRP21 Position     */
+#define GPIO_PORT_DIR5_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos)                     /*!< GPIO_PORT DIR5: DIRP21 Mask         */
+#define GPIO_PORT_DIR5_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR5: DIRP22 Position     */
+#define GPIO_PORT_DIR5_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos)                     /*!< GPIO_PORT DIR5: DIRP22 Mask         */
+#define GPIO_PORT_DIR5_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR5: DIRP23 Position     */
+#define GPIO_PORT_DIR5_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos)                     /*!< GPIO_PORT DIR5: DIRP23 Mask         */
+#define GPIO_PORT_DIR5_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR5: DIRP24 Position     */
+#define GPIO_PORT_DIR5_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos)                     /*!< GPIO_PORT DIR5: DIRP24 Mask         */
+#define GPIO_PORT_DIR5_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR5: DIRP25 Position     */
+#define GPIO_PORT_DIR5_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos)                     /*!< GPIO_PORT DIR5: DIRP25 Mask         */
+#define GPIO_PORT_DIR5_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR5: DIRP26 Position     */
+#define GPIO_PORT_DIR5_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos)                     /*!< GPIO_PORT DIR5: DIRP26 Mask         */
+#define GPIO_PORT_DIR5_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR5: DIRP27 Position     */
+#define GPIO_PORT_DIR5_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos)                     /*!< GPIO_PORT DIR5: DIRP27 Mask         */
+#define GPIO_PORT_DIR5_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR5: DIRP28 Position     */
+#define GPIO_PORT_DIR5_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos)                     /*!< GPIO_PORT DIR5: DIRP28 Mask         */
+#define GPIO_PORT_DIR5_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR5: DIRP29 Position     */
+#define GPIO_PORT_DIR5_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos)                     /*!< GPIO_PORT DIR5: DIRP29 Mask         */
+#define GPIO_PORT_DIR5_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR5: DIRP30 Position     */
+#define GPIO_PORT_DIR5_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos)                     /*!< GPIO_PORT DIR5: DIRP30 Mask         */
+#define GPIO_PORT_DIR5_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR5: DIRP31 Position     */
+#define GPIO_PORT_DIR5_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos)                     /*!< GPIO_PORT DIR5: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR6  -----------------------------------------
+#define GPIO_PORT_DIR6_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR6: DIRP0 Position      */
+#define GPIO_PORT_DIR6_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos)                      /*!< GPIO_PORT DIR6: DIRP0 Mask          */
+#define GPIO_PORT_DIR6_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR6: DIRP1 Position      */
+#define GPIO_PORT_DIR6_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos)                      /*!< GPIO_PORT DIR6: DIRP1 Mask          */
+#define GPIO_PORT_DIR6_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR6: DIRP2 Position      */
+#define GPIO_PORT_DIR6_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos)                      /*!< GPIO_PORT DIR6: DIRP2 Mask          */
+#define GPIO_PORT_DIR6_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR6: DIRP3 Position      */
+#define GPIO_PORT_DIR6_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos)                      /*!< GPIO_PORT DIR6: DIRP3 Mask          */
+#define GPIO_PORT_DIR6_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR6: DIRP4 Position      */
+#define GPIO_PORT_DIR6_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos)                      /*!< GPIO_PORT DIR6: DIRP4 Mask          */
+#define GPIO_PORT_DIR6_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR6: DIRP5 Position      */
+#define GPIO_PORT_DIR6_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos)                      /*!< GPIO_PORT DIR6: DIRP5 Mask          */
+#define GPIO_PORT_DIR6_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR6: DIRP6 Position      */
+#define GPIO_PORT_DIR6_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos)                      /*!< GPIO_PORT DIR6: DIRP6 Mask          */
+#define GPIO_PORT_DIR6_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR6: DIRP7 Position      */
+#define GPIO_PORT_DIR6_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos)                      /*!< GPIO_PORT DIR6: DIRP7 Mask          */
+#define GPIO_PORT_DIR6_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR6: DIRP8 Position      */
+#define GPIO_PORT_DIR6_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos)                      /*!< GPIO_PORT DIR6: DIRP8 Mask          */
+#define GPIO_PORT_DIR6_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR6: DIRP9 Position      */
+#define GPIO_PORT_DIR6_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos)                      /*!< GPIO_PORT DIR6: DIRP9 Mask          */
+#define GPIO_PORT_DIR6_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR6: DIRP10 Position     */
+#define GPIO_PORT_DIR6_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos)                     /*!< GPIO_PORT DIR6: DIRP10 Mask         */
+#define GPIO_PORT_DIR6_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR6: DIRP11 Position     */
+#define GPIO_PORT_DIR6_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos)                     /*!< GPIO_PORT DIR6: DIRP11 Mask         */
+#define GPIO_PORT_DIR6_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR6: DIRP12 Position     */
+#define GPIO_PORT_DIR6_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos)                     /*!< GPIO_PORT DIR6: DIRP12 Mask         */
+#define GPIO_PORT_DIR6_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR6: DIRP13 Position     */
+#define GPIO_PORT_DIR6_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos)                     /*!< GPIO_PORT DIR6: DIRP13 Mask         */
+#define GPIO_PORT_DIR6_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR6: DIRP14 Position     */
+#define GPIO_PORT_DIR6_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos)                     /*!< GPIO_PORT DIR6: DIRP14 Mask         */
+#define GPIO_PORT_DIR6_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR6: DIRP15 Position     */
+#define GPIO_PORT_DIR6_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos)                     /*!< GPIO_PORT DIR6: DIRP15 Mask         */
+#define GPIO_PORT_DIR6_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR6: DIRP16 Position     */
+#define GPIO_PORT_DIR6_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos)                     /*!< GPIO_PORT DIR6: DIRP16 Mask         */
+#define GPIO_PORT_DIR6_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR6: DIRP17 Position     */
+#define GPIO_PORT_DIR6_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos)                     /*!< GPIO_PORT DIR6: DIRP17 Mask         */
+#define GPIO_PORT_DIR6_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR6: DIRP18 Position     */
+#define GPIO_PORT_DIR6_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos)                     /*!< GPIO_PORT DIR6: DIRP18 Mask         */
+#define GPIO_PORT_DIR6_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR6: DIRP19 Position     */
+#define GPIO_PORT_DIR6_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos)                     /*!< GPIO_PORT DIR6: DIRP19 Mask         */
+#define GPIO_PORT_DIR6_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR6: DIRP20 Position     */
+#define GPIO_PORT_DIR6_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos)                     /*!< GPIO_PORT DIR6: DIRP20 Mask         */
+#define GPIO_PORT_DIR6_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR6: DIRP21 Position     */
+#define GPIO_PORT_DIR6_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos)                     /*!< GPIO_PORT DIR6: DIRP21 Mask         */
+#define GPIO_PORT_DIR6_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR6: DIRP22 Position     */
+#define GPIO_PORT_DIR6_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos)                     /*!< GPIO_PORT DIR6: DIRP22 Mask         */
+#define GPIO_PORT_DIR6_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR6: DIRP23 Position     */
+#define GPIO_PORT_DIR6_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos)                     /*!< GPIO_PORT DIR6: DIRP23 Mask         */
+#define GPIO_PORT_DIR6_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR6: DIRP24 Position     */
+#define GPIO_PORT_DIR6_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos)                     /*!< GPIO_PORT DIR6: DIRP24 Mask         */
+#define GPIO_PORT_DIR6_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR6: DIRP25 Position     */
+#define GPIO_PORT_DIR6_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos)                     /*!< GPIO_PORT DIR6: DIRP25 Mask         */
+#define GPIO_PORT_DIR6_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR6: DIRP26 Position     */
+#define GPIO_PORT_DIR6_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos)                     /*!< GPIO_PORT DIR6: DIRP26 Mask         */
+#define GPIO_PORT_DIR6_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR6: DIRP27 Position     */
+#define GPIO_PORT_DIR6_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos)                     /*!< GPIO_PORT DIR6: DIRP27 Mask         */
+#define GPIO_PORT_DIR6_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR6: DIRP28 Position     */
+#define GPIO_PORT_DIR6_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos)                     /*!< GPIO_PORT DIR6: DIRP28 Mask         */
+#define GPIO_PORT_DIR6_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR6: DIRP29 Position     */
+#define GPIO_PORT_DIR6_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos)                     /*!< GPIO_PORT DIR6: DIRP29 Mask         */
+#define GPIO_PORT_DIR6_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR6: DIRP30 Position     */
+#define GPIO_PORT_DIR6_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos)                     /*!< GPIO_PORT DIR6: DIRP30 Mask         */
+#define GPIO_PORT_DIR6_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR6: DIRP31 Position     */
+#define GPIO_PORT_DIR6_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos)                     /*!< GPIO_PORT DIR6: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_DIR7  -----------------------------------------
+#define GPIO_PORT_DIR7_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR7: DIRP0 Position      */
+#define GPIO_PORT_DIR7_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos)                      /*!< GPIO_PORT DIR7: DIRP0 Mask          */
+#define GPIO_PORT_DIR7_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR7: DIRP1 Position      */
+#define GPIO_PORT_DIR7_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos)                      /*!< GPIO_PORT DIR7: DIRP1 Mask          */
+#define GPIO_PORT_DIR7_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR7: DIRP2 Position      */
+#define GPIO_PORT_DIR7_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos)                      /*!< GPIO_PORT DIR7: DIRP2 Mask          */
+#define GPIO_PORT_DIR7_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR7: DIRP3 Position      */
+#define GPIO_PORT_DIR7_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos)                      /*!< GPIO_PORT DIR7: DIRP3 Mask          */
+#define GPIO_PORT_DIR7_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR7: DIRP4 Position      */
+#define GPIO_PORT_DIR7_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos)                      /*!< GPIO_PORT DIR7: DIRP4 Mask          */
+#define GPIO_PORT_DIR7_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR7: DIRP5 Position      */
+#define GPIO_PORT_DIR7_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos)                      /*!< GPIO_PORT DIR7: DIRP5 Mask          */
+#define GPIO_PORT_DIR7_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR7: DIRP6 Position      */
+#define GPIO_PORT_DIR7_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos)                      /*!< GPIO_PORT DIR7: DIRP6 Mask          */
+#define GPIO_PORT_DIR7_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR7: DIRP7 Position      */
+#define GPIO_PORT_DIR7_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos)                      /*!< GPIO_PORT DIR7: DIRP7 Mask          */
+#define GPIO_PORT_DIR7_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR7: DIRP8 Position      */
+#define GPIO_PORT_DIR7_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos)                      /*!< GPIO_PORT DIR7: DIRP8 Mask          */
+#define GPIO_PORT_DIR7_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR7: DIRP9 Position      */
+#define GPIO_PORT_DIR7_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos)                      /*!< GPIO_PORT DIR7: DIRP9 Mask          */
+#define GPIO_PORT_DIR7_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR7: DIRP10 Position     */
+#define GPIO_PORT_DIR7_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos)                     /*!< GPIO_PORT DIR7: DIRP10 Mask         */
+#define GPIO_PORT_DIR7_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR7: DIRP11 Position     */
+#define GPIO_PORT_DIR7_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos)                     /*!< GPIO_PORT DIR7: DIRP11 Mask         */
+#define GPIO_PORT_DIR7_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR7: DIRP12 Position     */
+#define GPIO_PORT_DIR7_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos)                     /*!< GPIO_PORT DIR7: DIRP12 Mask         */
+#define GPIO_PORT_DIR7_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR7: DIRP13 Position     */
+#define GPIO_PORT_DIR7_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos)                     /*!< GPIO_PORT DIR7: DIRP13 Mask         */
+#define GPIO_PORT_DIR7_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR7: DIRP14 Position     */
+#define GPIO_PORT_DIR7_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos)                     /*!< GPIO_PORT DIR7: DIRP14 Mask         */
+#define GPIO_PORT_DIR7_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR7: DIRP15 Position     */
+#define GPIO_PORT_DIR7_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos)                     /*!< GPIO_PORT DIR7: DIRP15 Mask         */
+#define GPIO_PORT_DIR7_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR7: DIRP16 Position     */
+#define GPIO_PORT_DIR7_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos)                     /*!< GPIO_PORT DIR7: DIRP16 Mask         */
+#define GPIO_PORT_DIR7_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR7: DIRP17 Position     */
+#define GPIO_PORT_DIR7_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos)                     /*!< GPIO_PORT DIR7: DIRP17 Mask         */
+#define GPIO_PORT_DIR7_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR7: DIRP18 Position     */
+#define GPIO_PORT_DIR7_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos)                     /*!< GPIO_PORT DIR7: DIRP18 Mask         */
+#define GPIO_PORT_DIR7_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR7: DIRP19 Position     */
+#define GPIO_PORT_DIR7_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos)                     /*!< GPIO_PORT DIR7: DIRP19 Mask         */
+#define GPIO_PORT_DIR7_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR7: DIRP20 Position     */
+#define GPIO_PORT_DIR7_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos)                     /*!< GPIO_PORT DIR7: DIRP20 Mask         */
+#define GPIO_PORT_DIR7_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR7: DIRP21 Position     */
+#define GPIO_PORT_DIR7_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos)                     /*!< GPIO_PORT DIR7: DIRP21 Mask         */
+#define GPIO_PORT_DIR7_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR7: DIRP22 Position     */
+#define GPIO_PORT_DIR7_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos)                     /*!< GPIO_PORT DIR7: DIRP22 Mask         */
+#define GPIO_PORT_DIR7_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR7: DIRP23 Position     */
+#define GPIO_PORT_DIR7_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos)                     /*!< GPIO_PORT DIR7: DIRP23 Mask         */
+#define GPIO_PORT_DIR7_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR7: DIRP24 Position     */
+#define GPIO_PORT_DIR7_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos)                     /*!< GPIO_PORT DIR7: DIRP24 Mask         */
+#define GPIO_PORT_DIR7_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR7: DIRP25 Position     */
+#define GPIO_PORT_DIR7_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos)                     /*!< GPIO_PORT DIR7: DIRP25 Mask         */
+#define GPIO_PORT_DIR7_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR7: DIRP26 Position     */
+#define GPIO_PORT_DIR7_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos)                     /*!< GPIO_PORT DIR7: DIRP26 Mask         */
+#define GPIO_PORT_DIR7_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR7: DIRP27 Position     */
+#define GPIO_PORT_DIR7_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos)                     /*!< GPIO_PORT DIR7: DIRP27 Mask         */
+#define GPIO_PORT_DIR7_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR7: DIRP28 Position     */
+#define GPIO_PORT_DIR7_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos)                     /*!< GPIO_PORT DIR7: DIRP28 Mask         */
+#define GPIO_PORT_DIR7_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR7: DIRP29 Position     */
+#define GPIO_PORT_DIR7_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos)                     /*!< GPIO_PORT DIR7: DIRP29 Mask         */
+#define GPIO_PORT_DIR7_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR7: DIRP30 Position     */
+#define GPIO_PORT_DIR7_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos)                     /*!< GPIO_PORT DIR7: DIRP30 Mask         */
+#define GPIO_PORT_DIR7_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR7: DIRP31 Position     */
+#define GPIO_PORT_DIR7_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos)                     /*!< GPIO_PORT DIR7: DIRP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_MASK0  ----------------------------------------
+#define GPIO_PORT_MASK0_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK0: MASKP0 Position    */
+#define GPIO_PORT_MASK0_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos)                    /*!< GPIO_PORT MASK0: MASKP0 Mask        */
+#define GPIO_PORT_MASK0_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK0: MASKP1 Position    */
+#define GPIO_PORT_MASK0_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos)                    /*!< GPIO_PORT MASK0: MASKP1 Mask        */
+#define GPIO_PORT_MASK0_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK0: MASKP2 Position    */
+#define GPIO_PORT_MASK0_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos)                    /*!< GPIO_PORT MASK0: MASKP2 Mask        */
+#define GPIO_PORT_MASK0_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK0: MASKP3 Position    */
+#define GPIO_PORT_MASK0_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos)                    /*!< GPIO_PORT MASK0: MASKP3 Mask        */
+#define GPIO_PORT_MASK0_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK0: MASKP4 Position    */
+#define GPIO_PORT_MASK0_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos)                    /*!< GPIO_PORT MASK0: MASKP4 Mask        */
+#define GPIO_PORT_MASK0_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK0: MASKP5 Position    */
+#define GPIO_PORT_MASK0_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos)                    /*!< GPIO_PORT MASK0: MASKP5 Mask        */
+#define GPIO_PORT_MASK0_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK0: MASKP6 Position    */
+#define GPIO_PORT_MASK0_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos)                    /*!< GPIO_PORT MASK0: MASKP6 Mask        */
+#define GPIO_PORT_MASK0_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK0: MASKP7 Position    */
+#define GPIO_PORT_MASK0_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos)                    /*!< GPIO_PORT MASK0: MASKP7 Mask        */
+#define GPIO_PORT_MASK0_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK0: MASKP8 Position    */
+#define GPIO_PORT_MASK0_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos)                    /*!< GPIO_PORT MASK0: MASKP8 Mask        */
+#define GPIO_PORT_MASK0_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK0: MASKP9 Position    */
+#define GPIO_PORT_MASK0_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos)                    /*!< GPIO_PORT MASK0: MASKP9 Mask        */
+#define GPIO_PORT_MASK0_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK0: MASKP10 Position   */
+#define GPIO_PORT_MASK0_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos)                   /*!< GPIO_PORT MASK0: MASKP10 Mask       */
+#define GPIO_PORT_MASK0_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK0: MASKP11 Position   */
+#define GPIO_PORT_MASK0_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos)                   /*!< GPIO_PORT MASK0: MASKP11 Mask       */
+#define GPIO_PORT_MASK0_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK0: MASKP12 Position   */
+#define GPIO_PORT_MASK0_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos)                   /*!< GPIO_PORT MASK0: MASKP12 Mask       */
+#define GPIO_PORT_MASK0_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK0: MASKP13 Position   */
+#define GPIO_PORT_MASK0_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos)                   /*!< GPIO_PORT MASK0: MASKP13 Mask       */
+#define GPIO_PORT_MASK0_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK0: MASKP14 Position   */
+#define GPIO_PORT_MASK0_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos)                   /*!< GPIO_PORT MASK0: MASKP14 Mask       */
+#define GPIO_PORT_MASK0_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK0: MASKP15 Position   */
+#define GPIO_PORT_MASK0_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos)                   /*!< GPIO_PORT MASK0: MASKP15 Mask       */
+#define GPIO_PORT_MASK0_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK0: MASKP16 Position   */
+#define GPIO_PORT_MASK0_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos)                   /*!< GPIO_PORT MASK0: MASKP16 Mask       */
+#define GPIO_PORT_MASK0_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK0: MASKP17 Position   */
+#define GPIO_PORT_MASK0_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos)                   /*!< GPIO_PORT MASK0: MASKP17 Mask       */
+#define GPIO_PORT_MASK0_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK0: MASKP18 Position   */
+#define GPIO_PORT_MASK0_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos)                   /*!< GPIO_PORT MASK0: MASKP18 Mask       */
+#define GPIO_PORT_MASK0_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK0: MASKP19 Position   */
+#define GPIO_PORT_MASK0_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos)                   /*!< GPIO_PORT MASK0: MASKP19 Mask       */
+#define GPIO_PORT_MASK0_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK0: MASKP20 Position   */
+#define GPIO_PORT_MASK0_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos)                   /*!< GPIO_PORT MASK0: MASKP20 Mask       */
+#define GPIO_PORT_MASK0_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK0: MASKP21 Position   */
+#define GPIO_PORT_MASK0_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos)                   /*!< GPIO_PORT MASK0: MASKP21 Mask       */
+#define GPIO_PORT_MASK0_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK0: MASKP22 Position   */
+#define GPIO_PORT_MASK0_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos)                   /*!< GPIO_PORT MASK0: MASKP22 Mask       */
+#define GPIO_PORT_MASK0_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK0: MASKP23 Position   */
+#define GPIO_PORT_MASK0_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos)                   /*!< GPIO_PORT MASK0: MASKP23 Mask       */
+#define GPIO_PORT_MASK0_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK0: MASKP24 Position   */
+#define GPIO_PORT_MASK0_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos)                   /*!< GPIO_PORT MASK0: MASKP24 Mask       */
+#define GPIO_PORT_MASK0_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK0: MASKP25 Position   */
+#define GPIO_PORT_MASK0_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos)                   /*!< GPIO_PORT MASK0: MASKP25 Mask       */
+#define GPIO_PORT_MASK0_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK0: MASKP26 Position   */
+#define GPIO_PORT_MASK0_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos)                   /*!< GPIO_PORT MASK0: MASKP26 Mask       */
+#define GPIO_PORT_MASK0_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK0: MASKP27 Position   */
+#define GPIO_PORT_MASK0_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos)                   /*!< GPIO_PORT MASK0: MASKP27 Mask       */
+#define GPIO_PORT_MASK0_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK0: MASKP28 Position   */
+#define GPIO_PORT_MASK0_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos)                   /*!< GPIO_PORT MASK0: MASKP28 Mask       */
+#define GPIO_PORT_MASK0_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK0: MASKP29 Position   */
+#define GPIO_PORT_MASK0_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos)                   /*!< GPIO_PORT MASK0: MASKP29 Mask       */
+#define GPIO_PORT_MASK0_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK0: MASKP30 Position   */
+#define GPIO_PORT_MASK0_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos)                   /*!< GPIO_PORT MASK0: MASKP30 Mask       */
+#define GPIO_PORT_MASK0_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK0: MASKP31 Position   */
+#define GPIO_PORT_MASK0_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos)                   /*!< GPIO_PORT MASK0: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK1  ----------------------------------------
+#define GPIO_PORT_MASK1_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK1: MASKP0 Position    */
+#define GPIO_PORT_MASK1_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos)                    /*!< GPIO_PORT MASK1: MASKP0 Mask        */
+#define GPIO_PORT_MASK1_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK1: MASKP1 Position    */
+#define GPIO_PORT_MASK1_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos)                    /*!< GPIO_PORT MASK1: MASKP1 Mask        */
+#define GPIO_PORT_MASK1_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK1: MASKP2 Position    */
+#define GPIO_PORT_MASK1_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos)                    /*!< GPIO_PORT MASK1: MASKP2 Mask        */
+#define GPIO_PORT_MASK1_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK1: MASKP3 Position    */
+#define GPIO_PORT_MASK1_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos)                    /*!< GPIO_PORT MASK1: MASKP3 Mask        */
+#define GPIO_PORT_MASK1_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK1: MASKP4 Position    */
+#define GPIO_PORT_MASK1_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos)                    /*!< GPIO_PORT MASK1: MASKP4 Mask        */
+#define GPIO_PORT_MASK1_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK1: MASKP5 Position    */
+#define GPIO_PORT_MASK1_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos)                    /*!< GPIO_PORT MASK1: MASKP5 Mask        */
+#define GPIO_PORT_MASK1_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK1: MASKP6 Position    */
+#define GPIO_PORT_MASK1_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos)                    /*!< GPIO_PORT MASK1: MASKP6 Mask        */
+#define GPIO_PORT_MASK1_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK1: MASKP7 Position    */
+#define GPIO_PORT_MASK1_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos)                    /*!< GPIO_PORT MASK1: MASKP7 Mask        */
+#define GPIO_PORT_MASK1_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK1: MASKP8 Position    */
+#define GPIO_PORT_MASK1_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos)                    /*!< GPIO_PORT MASK1: MASKP8 Mask        */
+#define GPIO_PORT_MASK1_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK1: MASKP9 Position    */
+#define GPIO_PORT_MASK1_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos)                    /*!< GPIO_PORT MASK1: MASKP9 Mask        */
+#define GPIO_PORT_MASK1_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK1: MASKP10 Position   */
+#define GPIO_PORT_MASK1_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos)                   /*!< GPIO_PORT MASK1: MASKP10 Mask       */
+#define GPIO_PORT_MASK1_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK1: MASKP11 Position   */
+#define GPIO_PORT_MASK1_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos)                   /*!< GPIO_PORT MASK1: MASKP11 Mask       */
+#define GPIO_PORT_MASK1_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK1: MASKP12 Position   */
+#define GPIO_PORT_MASK1_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos)                   /*!< GPIO_PORT MASK1: MASKP12 Mask       */
+#define GPIO_PORT_MASK1_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK1: MASKP13 Position   */
+#define GPIO_PORT_MASK1_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos)                   /*!< GPIO_PORT MASK1: MASKP13 Mask       */
+#define GPIO_PORT_MASK1_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK1: MASKP14 Position   */
+#define GPIO_PORT_MASK1_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos)                   /*!< GPIO_PORT MASK1: MASKP14 Mask       */
+#define GPIO_PORT_MASK1_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK1: MASKP15 Position   */
+#define GPIO_PORT_MASK1_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos)                   /*!< GPIO_PORT MASK1: MASKP15 Mask       */
+#define GPIO_PORT_MASK1_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK1: MASKP16 Position   */
+#define GPIO_PORT_MASK1_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos)                   /*!< GPIO_PORT MASK1: MASKP16 Mask       */
+#define GPIO_PORT_MASK1_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK1: MASKP17 Position   */
+#define GPIO_PORT_MASK1_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos)                   /*!< GPIO_PORT MASK1: MASKP17 Mask       */
+#define GPIO_PORT_MASK1_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK1: MASKP18 Position   */
+#define GPIO_PORT_MASK1_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos)                   /*!< GPIO_PORT MASK1: MASKP18 Mask       */
+#define GPIO_PORT_MASK1_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK1: MASKP19 Position   */
+#define GPIO_PORT_MASK1_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos)                   /*!< GPIO_PORT MASK1: MASKP19 Mask       */
+#define GPIO_PORT_MASK1_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK1: MASKP20 Position   */
+#define GPIO_PORT_MASK1_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos)                   /*!< GPIO_PORT MASK1: MASKP20 Mask       */
+#define GPIO_PORT_MASK1_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK1: MASKP21 Position   */
+#define GPIO_PORT_MASK1_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos)                   /*!< GPIO_PORT MASK1: MASKP21 Mask       */
+#define GPIO_PORT_MASK1_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK1: MASKP22 Position   */
+#define GPIO_PORT_MASK1_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos)                   /*!< GPIO_PORT MASK1: MASKP22 Mask       */
+#define GPIO_PORT_MASK1_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK1: MASKP23 Position   */
+#define GPIO_PORT_MASK1_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos)                   /*!< GPIO_PORT MASK1: MASKP23 Mask       */
+#define GPIO_PORT_MASK1_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK1: MASKP24 Position   */
+#define GPIO_PORT_MASK1_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos)                   /*!< GPIO_PORT MASK1: MASKP24 Mask       */
+#define GPIO_PORT_MASK1_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK1: MASKP25 Position   */
+#define GPIO_PORT_MASK1_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos)                   /*!< GPIO_PORT MASK1: MASKP25 Mask       */
+#define GPIO_PORT_MASK1_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK1: MASKP26 Position   */
+#define GPIO_PORT_MASK1_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos)                   /*!< GPIO_PORT MASK1: MASKP26 Mask       */
+#define GPIO_PORT_MASK1_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK1: MASKP27 Position   */
+#define GPIO_PORT_MASK1_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos)                   /*!< GPIO_PORT MASK1: MASKP27 Mask       */
+#define GPIO_PORT_MASK1_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK1: MASKP28 Position   */
+#define GPIO_PORT_MASK1_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos)                   /*!< GPIO_PORT MASK1: MASKP28 Mask       */
+#define GPIO_PORT_MASK1_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK1: MASKP29 Position   */
+#define GPIO_PORT_MASK1_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos)                   /*!< GPIO_PORT MASK1: MASKP29 Mask       */
+#define GPIO_PORT_MASK1_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK1: MASKP30 Position   */
+#define GPIO_PORT_MASK1_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos)                   /*!< GPIO_PORT MASK1: MASKP30 Mask       */
+#define GPIO_PORT_MASK1_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK1: MASKP31 Position   */
+#define GPIO_PORT_MASK1_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos)                   /*!< GPIO_PORT MASK1: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK2  ----------------------------------------
+#define GPIO_PORT_MASK2_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK2: MASKP0 Position    */
+#define GPIO_PORT_MASK2_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos)                    /*!< GPIO_PORT MASK2: MASKP0 Mask        */
+#define GPIO_PORT_MASK2_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK2: MASKP1 Position    */
+#define GPIO_PORT_MASK2_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos)                    /*!< GPIO_PORT MASK2: MASKP1 Mask        */
+#define GPIO_PORT_MASK2_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK2: MASKP2 Position    */
+#define GPIO_PORT_MASK2_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos)                    /*!< GPIO_PORT MASK2: MASKP2 Mask        */
+#define GPIO_PORT_MASK2_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK2: MASKP3 Position    */
+#define GPIO_PORT_MASK2_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos)                    /*!< GPIO_PORT MASK2: MASKP3 Mask        */
+#define GPIO_PORT_MASK2_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK2: MASKP4 Position    */
+#define GPIO_PORT_MASK2_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos)                    /*!< GPIO_PORT MASK2: MASKP4 Mask        */
+#define GPIO_PORT_MASK2_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK2: MASKP5 Position    */
+#define GPIO_PORT_MASK2_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos)                    /*!< GPIO_PORT MASK2: MASKP5 Mask        */
+#define GPIO_PORT_MASK2_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK2: MASKP6 Position    */
+#define GPIO_PORT_MASK2_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos)                    /*!< GPIO_PORT MASK2: MASKP6 Mask        */
+#define GPIO_PORT_MASK2_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK2: MASKP7 Position    */
+#define GPIO_PORT_MASK2_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos)                    /*!< GPIO_PORT MASK2: MASKP7 Mask        */
+#define GPIO_PORT_MASK2_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK2: MASKP8 Position    */
+#define GPIO_PORT_MASK2_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos)                    /*!< GPIO_PORT MASK2: MASKP8 Mask        */
+#define GPIO_PORT_MASK2_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK2: MASKP9 Position    */
+#define GPIO_PORT_MASK2_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos)                    /*!< GPIO_PORT MASK2: MASKP9 Mask        */
+#define GPIO_PORT_MASK2_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK2: MASKP10 Position   */
+#define GPIO_PORT_MASK2_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos)                   /*!< GPIO_PORT MASK2: MASKP10 Mask       */
+#define GPIO_PORT_MASK2_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK2: MASKP11 Position   */
+#define GPIO_PORT_MASK2_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos)                   /*!< GPIO_PORT MASK2: MASKP11 Mask       */
+#define GPIO_PORT_MASK2_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK2: MASKP12 Position   */
+#define GPIO_PORT_MASK2_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos)                   /*!< GPIO_PORT MASK2: MASKP12 Mask       */
+#define GPIO_PORT_MASK2_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK2: MASKP13 Position   */
+#define GPIO_PORT_MASK2_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos)                   /*!< GPIO_PORT MASK2: MASKP13 Mask       */
+#define GPIO_PORT_MASK2_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK2: MASKP14 Position   */
+#define GPIO_PORT_MASK2_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos)                   /*!< GPIO_PORT MASK2: MASKP14 Mask       */
+#define GPIO_PORT_MASK2_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK2: MASKP15 Position   */
+#define GPIO_PORT_MASK2_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos)                   /*!< GPIO_PORT MASK2: MASKP15 Mask       */
+#define GPIO_PORT_MASK2_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK2: MASKP16 Position   */
+#define GPIO_PORT_MASK2_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos)                   /*!< GPIO_PORT MASK2: MASKP16 Mask       */
+#define GPIO_PORT_MASK2_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK2: MASKP17 Position   */
+#define GPIO_PORT_MASK2_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos)                   /*!< GPIO_PORT MASK2: MASKP17 Mask       */
+#define GPIO_PORT_MASK2_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK2: MASKP18 Position   */
+#define GPIO_PORT_MASK2_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos)                   /*!< GPIO_PORT MASK2: MASKP18 Mask       */
+#define GPIO_PORT_MASK2_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK2: MASKP19 Position   */
+#define GPIO_PORT_MASK2_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos)                   /*!< GPIO_PORT MASK2: MASKP19 Mask       */
+#define GPIO_PORT_MASK2_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK2: MASKP20 Position   */
+#define GPIO_PORT_MASK2_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos)                   /*!< GPIO_PORT MASK2: MASKP20 Mask       */
+#define GPIO_PORT_MASK2_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK2: MASKP21 Position   */
+#define GPIO_PORT_MASK2_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos)                   /*!< GPIO_PORT MASK2: MASKP21 Mask       */
+#define GPIO_PORT_MASK2_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK2: MASKP22 Position   */
+#define GPIO_PORT_MASK2_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos)                   /*!< GPIO_PORT MASK2: MASKP22 Mask       */
+#define GPIO_PORT_MASK2_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK2: MASKP23 Position   */
+#define GPIO_PORT_MASK2_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos)                   /*!< GPIO_PORT MASK2: MASKP23 Mask       */
+#define GPIO_PORT_MASK2_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK2: MASKP24 Position   */
+#define GPIO_PORT_MASK2_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos)                   /*!< GPIO_PORT MASK2: MASKP24 Mask       */
+#define GPIO_PORT_MASK2_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK2: MASKP25 Position   */
+#define GPIO_PORT_MASK2_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos)                   /*!< GPIO_PORT MASK2: MASKP25 Mask       */
+#define GPIO_PORT_MASK2_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK2: MASKP26 Position   */
+#define GPIO_PORT_MASK2_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos)                   /*!< GPIO_PORT MASK2: MASKP26 Mask       */
+#define GPIO_PORT_MASK2_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK2: MASKP27 Position   */
+#define GPIO_PORT_MASK2_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos)                   /*!< GPIO_PORT MASK2: MASKP27 Mask       */
+#define GPIO_PORT_MASK2_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK2: MASKP28 Position   */
+#define GPIO_PORT_MASK2_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos)                   /*!< GPIO_PORT MASK2: MASKP28 Mask       */
+#define GPIO_PORT_MASK2_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK2: MASKP29 Position   */
+#define GPIO_PORT_MASK2_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos)                   /*!< GPIO_PORT MASK2: MASKP29 Mask       */
+#define GPIO_PORT_MASK2_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK2: MASKP30 Position   */
+#define GPIO_PORT_MASK2_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos)                   /*!< GPIO_PORT MASK2: MASKP30 Mask       */
+#define GPIO_PORT_MASK2_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK2: MASKP31 Position   */
+#define GPIO_PORT_MASK2_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos)                   /*!< GPIO_PORT MASK2: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK3  ----------------------------------------
+#define GPIO_PORT_MASK3_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK3: MASKP0 Position    */
+#define GPIO_PORT_MASK3_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos)                    /*!< GPIO_PORT MASK3: MASKP0 Mask        */
+#define GPIO_PORT_MASK3_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK3: MASKP1 Position    */
+#define GPIO_PORT_MASK3_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos)                    /*!< GPIO_PORT MASK3: MASKP1 Mask        */
+#define GPIO_PORT_MASK3_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK3: MASKP2 Position    */
+#define GPIO_PORT_MASK3_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos)                    /*!< GPIO_PORT MASK3: MASKP2 Mask        */
+#define GPIO_PORT_MASK3_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK3: MASKP3 Position    */
+#define GPIO_PORT_MASK3_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos)                    /*!< GPIO_PORT MASK3: MASKP3 Mask        */
+#define GPIO_PORT_MASK3_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK3: MASKP4 Position    */
+#define GPIO_PORT_MASK3_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos)                    /*!< GPIO_PORT MASK3: MASKP4 Mask        */
+#define GPIO_PORT_MASK3_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK3: MASKP5 Position    */
+#define GPIO_PORT_MASK3_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos)                    /*!< GPIO_PORT MASK3: MASKP5 Mask        */
+#define GPIO_PORT_MASK3_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK3: MASKP6 Position    */
+#define GPIO_PORT_MASK3_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos)                    /*!< GPIO_PORT MASK3: MASKP6 Mask        */
+#define GPIO_PORT_MASK3_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK3: MASKP7 Position    */
+#define GPIO_PORT_MASK3_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos)                    /*!< GPIO_PORT MASK3: MASKP7 Mask        */
+#define GPIO_PORT_MASK3_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK3: MASKP8 Position    */
+#define GPIO_PORT_MASK3_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos)                    /*!< GPIO_PORT MASK3: MASKP8 Mask        */
+#define GPIO_PORT_MASK3_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK3: MASKP9 Position    */
+#define GPIO_PORT_MASK3_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos)                    /*!< GPIO_PORT MASK3: MASKP9 Mask        */
+#define GPIO_PORT_MASK3_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK3: MASKP10 Position   */
+#define GPIO_PORT_MASK3_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos)                   /*!< GPIO_PORT MASK3: MASKP10 Mask       */
+#define GPIO_PORT_MASK3_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK3: MASKP11 Position   */
+#define GPIO_PORT_MASK3_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos)                   /*!< GPIO_PORT MASK3: MASKP11 Mask       */
+#define GPIO_PORT_MASK3_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK3: MASKP12 Position   */
+#define GPIO_PORT_MASK3_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos)                   /*!< GPIO_PORT MASK3: MASKP12 Mask       */
+#define GPIO_PORT_MASK3_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK3: MASKP13 Position   */
+#define GPIO_PORT_MASK3_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos)                   /*!< GPIO_PORT MASK3: MASKP13 Mask       */
+#define GPIO_PORT_MASK3_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK3: MASKP14 Position   */
+#define GPIO_PORT_MASK3_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos)                   /*!< GPIO_PORT MASK3: MASKP14 Mask       */
+#define GPIO_PORT_MASK3_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK3: MASKP15 Position   */
+#define GPIO_PORT_MASK3_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos)                   /*!< GPIO_PORT MASK3: MASKP15 Mask       */
+#define GPIO_PORT_MASK3_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK3: MASKP16 Position   */
+#define GPIO_PORT_MASK3_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos)                   /*!< GPIO_PORT MASK3: MASKP16 Mask       */
+#define GPIO_PORT_MASK3_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK3: MASKP17 Position   */
+#define GPIO_PORT_MASK3_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos)                   /*!< GPIO_PORT MASK3: MASKP17 Mask       */
+#define GPIO_PORT_MASK3_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK3: MASKP18 Position   */
+#define GPIO_PORT_MASK3_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos)                   /*!< GPIO_PORT MASK3: MASKP18 Mask       */
+#define GPIO_PORT_MASK3_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK3: MASKP19 Position   */
+#define GPIO_PORT_MASK3_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos)                   /*!< GPIO_PORT MASK3: MASKP19 Mask       */
+#define GPIO_PORT_MASK3_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK3: MASKP20 Position   */
+#define GPIO_PORT_MASK3_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos)                   /*!< GPIO_PORT MASK3: MASKP20 Mask       */
+#define GPIO_PORT_MASK3_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK3: MASKP21 Position   */
+#define GPIO_PORT_MASK3_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos)                   /*!< GPIO_PORT MASK3: MASKP21 Mask       */
+#define GPIO_PORT_MASK3_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK3: MASKP22 Position   */
+#define GPIO_PORT_MASK3_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos)                   /*!< GPIO_PORT MASK3: MASKP22 Mask       */
+#define GPIO_PORT_MASK3_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK3: MASKP23 Position   */
+#define GPIO_PORT_MASK3_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos)                   /*!< GPIO_PORT MASK3: MASKP23 Mask       */
+#define GPIO_PORT_MASK3_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK3: MASKP24 Position   */
+#define GPIO_PORT_MASK3_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos)                   /*!< GPIO_PORT MASK3: MASKP24 Mask       */
+#define GPIO_PORT_MASK3_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK3: MASKP25 Position   */
+#define GPIO_PORT_MASK3_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos)                   /*!< GPIO_PORT MASK3: MASKP25 Mask       */
+#define GPIO_PORT_MASK3_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK3: MASKP26 Position   */
+#define GPIO_PORT_MASK3_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos)                   /*!< GPIO_PORT MASK3: MASKP26 Mask       */
+#define GPIO_PORT_MASK3_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK3: MASKP27 Position   */
+#define GPIO_PORT_MASK3_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos)                   /*!< GPIO_PORT MASK3: MASKP27 Mask       */
+#define GPIO_PORT_MASK3_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK3: MASKP28 Position   */
+#define GPIO_PORT_MASK3_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos)                   /*!< GPIO_PORT MASK3: MASKP28 Mask       */
+#define GPIO_PORT_MASK3_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK3: MASKP29 Position   */
+#define GPIO_PORT_MASK3_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos)                   /*!< GPIO_PORT MASK3: MASKP29 Mask       */
+#define GPIO_PORT_MASK3_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK3: MASKP30 Position   */
+#define GPIO_PORT_MASK3_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos)                   /*!< GPIO_PORT MASK3: MASKP30 Mask       */
+#define GPIO_PORT_MASK3_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK3: MASKP31 Position   */
+#define GPIO_PORT_MASK3_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos)                   /*!< GPIO_PORT MASK3: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK4  ----------------------------------------
+#define GPIO_PORT_MASK4_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK4: MASKP0 Position    */
+#define GPIO_PORT_MASK4_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos)                    /*!< GPIO_PORT MASK4: MASKP0 Mask        */
+#define GPIO_PORT_MASK4_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK4: MASKP1 Position    */
+#define GPIO_PORT_MASK4_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos)                    /*!< GPIO_PORT MASK4: MASKP1 Mask        */
+#define GPIO_PORT_MASK4_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK4: MASKP2 Position    */
+#define GPIO_PORT_MASK4_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos)                    /*!< GPIO_PORT MASK4: MASKP2 Mask        */
+#define GPIO_PORT_MASK4_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK4: MASKP3 Position    */
+#define GPIO_PORT_MASK4_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos)                    /*!< GPIO_PORT MASK4: MASKP3 Mask        */
+#define GPIO_PORT_MASK4_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK4: MASKP4 Position    */
+#define GPIO_PORT_MASK4_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos)                    /*!< GPIO_PORT MASK4: MASKP4 Mask        */
+#define GPIO_PORT_MASK4_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK4: MASKP5 Position    */
+#define GPIO_PORT_MASK4_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos)                    /*!< GPIO_PORT MASK4: MASKP5 Mask        */
+#define GPIO_PORT_MASK4_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK4: MASKP6 Position    */
+#define GPIO_PORT_MASK4_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos)                    /*!< GPIO_PORT MASK4: MASKP6 Mask        */
+#define GPIO_PORT_MASK4_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK4: MASKP7 Position    */
+#define GPIO_PORT_MASK4_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos)                    /*!< GPIO_PORT MASK4: MASKP7 Mask        */
+#define GPIO_PORT_MASK4_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK4: MASKP8 Position    */
+#define GPIO_PORT_MASK4_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos)                    /*!< GPIO_PORT MASK4: MASKP8 Mask        */
+#define GPIO_PORT_MASK4_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK4: MASKP9 Position    */
+#define GPIO_PORT_MASK4_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos)                    /*!< GPIO_PORT MASK4: MASKP9 Mask        */
+#define GPIO_PORT_MASK4_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK4: MASKP10 Position   */
+#define GPIO_PORT_MASK4_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos)                   /*!< GPIO_PORT MASK4: MASKP10 Mask       */
+#define GPIO_PORT_MASK4_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK4: MASKP11 Position   */
+#define GPIO_PORT_MASK4_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos)                   /*!< GPIO_PORT MASK4: MASKP11 Mask       */
+#define GPIO_PORT_MASK4_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK4: MASKP12 Position   */
+#define GPIO_PORT_MASK4_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos)                   /*!< GPIO_PORT MASK4: MASKP12 Mask       */
+#define GPIO_PORT_MASK4_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK4: MASKP13 Position   */
+#define GPIO_PORT_MASK4_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos)                   /*!< GPIO_PORT MASK4: MASKP13 Mask       */
+#define GPIO_PORT_MASK4_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK4: MASKP14 Position   */
+#define GPIO_PORT_MASK4_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos)                   /*!< GPIO_PORT MASK4: MASKP14 Mask       */
+#define GPIO_PORT_MASK4_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK4: MASKP15 Position   */
+#define GPIO_PORT_MASK4_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos)                   /*!< GPIO_PORT MASK4: MASKP15 Mask       */
+#define GPIO_PORT_MASK4_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK4: MASKP16 Position   */
+#define GPIO_PORT_MASK4_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos)                   /*!< GPIO_PORT MASK4: MASKP16 Mask       */
+#define GPIO_PORT_MASK4_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK4: MASKP17 Position   */
+#define GPIO_PORT_MASK4_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos)                   /*!< GPIO_PORT MASK4: MASKP17 Mask       */
+#define GPIO_PORT_MASK4_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK4: MASKP18 Position   */
+#define GPIO_PORT_MASK4_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos)                   /*!< GPIO_PORT MASK4: MASKP18 Mask       */
+#define GPIO_PORT_MASK4_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK4: MASKP19 Position   */
+#define GPIO_PORT_MASK4_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos)                   /*!< GPIO_PORT MASK4: MASKP19 Mask       */
+#define GPIO_PORT_MASK4_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK4: MASKP20 Position   */
+#define GPIO_PORT_MASK4_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos)                   /*!< GPIO_PORT MASK4: MASKP20 Mask       */
+#define GPIO_PORT_MASK4_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK4: MASKP21 Position   */
+#define GPIO_PORT_MASK4_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos)                   /*!< GPIO_PORT MASK4: MASKP21 Mask       */
+#define GPIO_PORT_MASK4_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK4: MASKP22 Position   */
+#define GPIO_PORT_MASK4_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos)                   /*!< GPIO_PORT MASK4: MASKP22 Mask       */
+#define GPIO_PORT_MASK4_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK4: MASKP23 Position   */
+#define GPIO_PORT_MASK4_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos)                   /*!< GPIO_PORT MASK4: MASKP23 Mask       */
+#define GPIO_PORT_MASK4_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK4: MASKP24 Position   */
+#define GPIO_PORT_MASK4_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos)                   /*!< GPIO_PORT MASK4: MASKP24 Mask       */
+#define GPIO_PORT_MASK4_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK4: MASKP25 Position   */
+#define GPIO_PORT_MASK4_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos)                   /*!< GPIO_PORT MASK4: MASKP25 Mask       */
+#define GPIO_PORT_MASK4_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK4: MASKP26 Position   */
+#define GPIO_PORT_MASK4_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos)                   /*!< GPIO_PORT MASK4: MASKP26 Mask       */
+#define GPIO_PORT_MASK4_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK4: MASKP27 Position   */
+#define GPIO_PORT_MASK4_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos)                   /*!< GPIO_PORT MASK4: MASKP27 Mask       */
+#define GPIO_PORT_MASK4_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK4: MASKP28 Position   */
+#define GPIO_PORT_MASK4_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos)                   /*!< GPIO_PORT MASK4: MASKP28 Mask       */
+#define GPIO_PORT_MASK4_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK4: MASKP29 Position   */
+#define GPIO_PORT_MASK4_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos)                   /*!< GPIO_PORT MASK4: MASKP29 Mask       */
+#define GPIO_PORT_MASK4_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK4: MASKP30 Position   */
+#define GPIO_PORT_MASK4_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos)                   /*!< GPIO_PORT MASK4: MASKP30 Mask       */
+#define GPIO_PORT_MASK4_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK4: MASKP31 Position   */
+#define GPIO_PORT_MASK4_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos)                   /*!< GPIO_PORT MASK4: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK5  ----------------------------------------
+#define GPIO_PORT_MASK5_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK5: MASKP0 Position    */
+#define GPIO_PORT_MASK5_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos)                    /*!< GPIO_PORT MASK5: MASKP0 Mask        */
+#define GPIO_PORT_MASK5_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK5: MASKP1 Position    */
+#define GPIO_PORT_MASK5_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos)                    /*!< GPIO_PORT MASK5: MASKP1 Mask        */
+#define GPIO_PORT_MASK5_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK5: MASKP2 Position    */
+#define GPIO_PORT_MASK5_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos)                    /*!< GPIO_PORT MASK5: MASKP2 Mask        */
+#define GPIO_PORT_MASK5_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK5: MASKP3 Position    */
+#define GPIO_PORT_MASK5_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos)                    /*!< GPIO_PORT MASK5: MASKP3 Mask        */
+#define GPIO_PORT_MASK5_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK5: MASKP4 Position    */
+#define GPIO_PORT_MASK5_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos)                    /*!< GPIO_PORT MASK5: MASKP4 Mask        */
+#define GPIO_PORT_MASK5_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK5: MASKP5 Position    */
+#define GPIO_PORT_MASK5_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos)                    /*!< GPIO_PORT MASK5: MASKP5 Mask        */
+#define GPIO_PORT_MASK5_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK5: MASKP6 Position    */
+#define GPIO_PORT_MASK5_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos)                    /*!< GPIO_PORT MASK5: MASKP6 Mask        */
+#define GPIO_PORT_MASK5_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK5: MASKP7 Position    */
+#define GPIO_PORT_MASK5_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos)                    /*!< GPIO_PORT MASK5: MASKP7 Mask        */
+#define GPIO_PORT_MASK5_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK5: MASKP8 Position    */
+#define GPIO_PORT_MASK5_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos)                    /*!< GPIO_PORT MASK5: MASKP8 Mask        */
+#define GPIO_PORT_MASK5_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK5: MASKP9 Position    */
+#define GPIO_PORT_MASK5_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos)                    /*!< GPIO_PORT MASK5: MASKP9 Mask        */
+#define GPIO_PORT_MASK5_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK5: MASKP10 Position   */
+#define GPIO_PORT_MASK5_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos)                   /*!< GPIO_PORT MASK5: MASKP10 Mask       */
+#define GPIO_PORT_MASK5_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK5: MASKP11 Position   */
+#define GPIO_PORT_MASK5_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos)                   /*!< GPIO_PORT MASK5: MASKP11 Mask       */
+#define GPIO_PORT_MASK5_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK5: MASKP12 Position   */
+#define GPIO_PORT_MASK5_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos)                   /*!< GPIO_PORT MASK5: MASKP12 Mask       */
+#define GPIO_PORT_MASK5_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK5: MASKP13 Position   */
+#define GPIO_PORT_MASK5_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos)                   /*!< GPIO_PORT MASK5: MASKP13 Mask       */
+#define GPIO_PORT_MASK5_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK5: MASKP14 Position   */
+#define GPIO_PORT_MASK5_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos)                   /*!< GPIO_PORT MASK5: MASKP14 Mask       */
+#define GPIO_PORT_MASK5_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK5: MASKP15 Position   */
+#define GPIO_PORT_MASK5_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos)                   /*!< GPIO_PORT MASK5: MASKP15 Mask       */
+#define GPIO_PORT_MASK5_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK5: MASKP16 Position   */
+#define GPIO_PORT_MASK5_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos)                   /*!< GPIO_PORT MASK5: MASKP16 Mask       */
+#define GPIO_PORT_MASK5_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK5: MASKP17 Position   */
+#define GPIO_PORT_MASK5_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos)                   /*!< GPIO_PORT MASK5: MASKP17 Mask       */
+#define GPIO_PORT_MASK5_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK5: MASKP18 Position   */
+#define GPIO_PORT_MASK5_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos)                   /*!< GPIO_PORT MASK5: MASKP18 Mask       */
+#define GPIO_PORT_MASK5_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK5: MASKP19 Position   */
+#define GPIO_PORT_MASK5_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos)                   /*!< GPIO_PORT MASK5: MASKP19 Mask       */
+#define GPIO_PORT_MASK5_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK5: MASKP20 Position   */
+#define GPIO_PORT_MASK5_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos)                   /*!< GPIO_PORT MASK5: MASKP20 Mask       */
+#define GPIO_PORT_MASK5_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK5: MASKP21 Position   */
+#define GPIO_PORT_MASK5_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos)                   /*!< GPIO_PORT MASK5: MASKP21 Mask       */
+#define GPIO_PORT_MASK5_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK5: MASKP22 Position   */
+#define GPIO_PORT_MASK5_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos)                   /*!< GPIO_PORT MASK5: MASKP22 Mask       */
+#define GPIO_PORT_MASK5_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK5: MASKP23 Position   */
+#define GPIO_PORT_MASK5_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos)                   /*!< GPIO_PORT MASK5: MASKP23 Mask       */
+#define GPIO_PORT_MASK5_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK5: MASKP24 Position   */
+#define GPIO_PORT_MASK5_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos)                   /*!< GPIO_PORT MASK5: MASKP24 Mask       */
+#define GPIO_PORT_MASK5_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK5: MASKP25 Position   */
+#define GPIO_PORT_MASK5_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos)                   /*!< GPIO_PORT MASK5: MASKP25 Mask       */
+#define GPIO_PORT_MASK5_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK5: MASKP26 Position   */
+#define GPIO_PORT_MASK5_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos)                   /*!< GPIO_PORT MASK5: MASKP26 Mask       */
+#define GPIO_PORT_MASK5_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK5: MASKP27 Position   */
+#define GPIO_PORT_MASK5_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos)                   /*!< GPIO_PORT MASK5: MASKP27 Mask       */
+#define GPIO_PORT_MASK5_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK5: MASKP28 Position   */
+#define GPIO_PORT_MASK5_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos)                   /*!< GPIO_PORT MASK5: MASKP28 Mask       */
+#define GPIO_PORT_MASK5_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK5: MASKP29 Position   */
+#define GPIO_PORT_MASK5_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos)                   /*!< GPIO_PORT MASK5: MASKP29 Mask       */
+#define GPIO_PORT_MASK5_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK5: MASKP30 Position   */
+#define GPIO_PORT_MASK5_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos)                   /*!< GPIO_PORT MASK5: MASKP30 Mask       */
+#define GPIO_PORT_MASK5_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK5: MASKP31 Position   */
+#define GPIO_PORT_MASK5_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos)                   /*!< GPIO_PORT MASK5: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK6  ----------------------------------------
+#define GPIO_PORT_MASK6_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK6: MASKP0 Position    */
+#define GPIO_PORT_MASK6_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos)                    /*!< GPIO_PORT MASK6: MASKP0 Mask        */
+#define GPIO_PORT_MASK6_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK6: MASKP1 Position    */
+#define GPIO_PORT_MASK6_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos)                    /*!< GPIO_PORT MASK6: MASKP1 Mask        */
+#define GPIO_PORT_MASK6_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK6: MASKP2 Position    */
+#define GPIO_PORT_MASK6_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos)                    /*!< GPIO_PORT MASK6: MASKP2 Mask        */
+#define GPIO_PORT_MASK6_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK6: MASKP3 Position    */
+#define GPIO_PORT_MASK6_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos)                    /*!< GPIO_PORT MASK6: MASKP3 Mask        */
+#define GPIO_PORT_MASK6_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK6: MASKP4 Position    */
+#define GPIO_PORT_MASK6_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos)                    /*!< GPIO_PORT MASK6: MASKP4 Mask        */
+#define GPIO_PORT_MASK6_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK6: MASKP5 Position    */
+#define GPIO_PORT_MASK6_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos)                    /*!< GPIO_PORT MASK6: MASKP5 Mask        */
+#define GPIO_PORT_MASK6_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK6: MASKP6 Position    */
+#define GPIO_PORT_MASK6_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos)                    /*!< GPIO_PORT MASK6: MASKP6 Mask        */
+#define GPIO_PORT_MASK6_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK6: MASKP7 Position    */
+#define GPIO_PORT_MASK6_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos)                    /*!< GPIO_PORT MASK6: MASKP7 Mask        */
+#define GPIO_PORT_MASK6_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK6: MASKP8 Position    */
+#define GPIO_PORT_MASK6_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos)                    /*!< GPIO_PORT MASK6: MASKP8 Mask        */
+#define GPIO_PORT_MASK6_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK6: MASKP9 Position    */
+#define GPIO_PORT_MASK6_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos)                    /*!< GPIO_PORT MASK6: MASKP9 Mask        */
+#define GPIO_PORT_MASK6_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK6: MASKP10 Position   */
+#define GPIO_PORT_MASK6_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos)                   /*!< GPIO_PORT MASK6: MASKP10 Mask       */
+#define GPIO_PORT_MASK6_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK6: MASKP11 Position   */
+#define GPIO_PORT_MASK6_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos)                   /*!< GPIO_PORT MASK6: MASKP11 Mask       */
+#define GPIO_PORT_MASK6_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK6: MASKP12 Position   */
+#define GPIO_PORT_MASK6_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos)                   /*!< GPIO_PORT MASK6: MASKP12 Mask       */
+#define GPIO_PORT_MASK6_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK6: MASKP13 Position   */
+#define GPIO_PORT_MASK6_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos)                   /*!< GPIO_PORT MASK6: MASKP13 Mask       */
+#define GPIO_PORT_MASK6_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK6: MASKP14 Position   */
+#define GPIO_PORT_MASK6_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos)                   /*!< GPIO_PORT MASK6: MASKP14 Mask       */
+#define GPIO_PORT_MASK6_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK6: MASKP15 Position   */
+#define GPIO_PORT_MASK6_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos)                   /*!< GPIO_PORT MASK6: MASKP15 Mask       */
+#define GPIO_PORT_MASK6_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK6: MASKP16 Position   */
+#define GPIO_PORT_MASK6_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos)                   /*!< GPIO_PORT MASK6: MASKP16 Mask       */
+#define GPIO_PORT_MASK6_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK6: MASKP17 Position   */
+#define GPIO_PORT_MASK6_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos)                   /*!< GPIO_PORT MASK6: MASKP17 Mask       */
+#define GPIO_PORT_MASK6_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK6: MASKP18 Position   */
+#define GPIO_PORT_MASK6_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos)                   /*!< GPIO_PORT MASK6: MASKP18 Mask       */
+#define GPIO_PORT_MASK6_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK6: MASKP19 Position   */
+#define GPIO_PORT_MASK6_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos)                   /*!< GPIO_PORT MASK6: MASKP19 Mask       */
+#define GPIO_PORT_MASK6_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK6: MASKP20 Position   */
+#define GPIO_PORT_MASK6_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos)                   /*!< GPIO_PORT MASK6: MASKP20 Mask       */
+#define GPIO_PORT_MASK6_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK6: MASKP21 Position   */
+#define GPIO_PORT_MASK6_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos)                   /*!< GPIO_PORT MASK6: MASKP21 Mask       */
+#define GPIO_PORT_MASK6_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK6: MASKP22 Position   */
+#define GPIO_PORT_MASK6_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos)                   /*!< GPIO_PORT MASK6: MASKP22 Mask       */
+#define GPIO_PORT_MASK6_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK6: MASKP23 Position   */
+#define GPIO_PORT_MASK6_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos)                   /*!< GPIO_PORT MASK6: MASKP23 Mask       */
+#define GPIO_PORT_MASK6_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK6: MASKP24 Position   */
+#define GPIO_PORT_MASK6_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos)                   /*!< GPIO_PORT MASK6: MASKP24 Mask       */
+#define GPIO_PORT_MASK6_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK6: MASKP25 Position   */
+#define GPIO_PORT_MASK6_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos)                   /*!< GPIO_PORT MASK6: MASKP25 Mask       */
+#define GPIO_PORT_MASK6_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK6: MASKP26 Position   */
+#define GPIO_PORT_MASK6_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos)                   /*!< GPIO_PORT MASK6: MASKP26 Mask       */
+#define GPIO_PORT_MASK6_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK6: MASKP27 Position   */
+#define GPIO_PORT_MASK6_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos)                   /*!< GPIO_PORT MASK6: MASKP27 Mask       */
+#define GPIO_PORT_MASK6_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK6: MASKP28 Position   */
+#define GPIO_PORT_MASK6_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos)                   /*!< GPIO_PORT MASK6: MASKP28 Mask       */
+#define GPIO_PORT_MASK6_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK6: MASKP29 Position   */
+#define GPIO_PORT_MASK6_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos)                   /*!< GPIO_PORT MASK6: MASKP29 Mask       */
+#define GPIO_PORT_MASK6_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK6: MASKP30 Position   */
+#define GPIO_PORT_MASK6_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos)                   /*!< GPIO_PORT MASK6: MASKP30 Mask       */
+#define GPIO_PORT_MASK6_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK6: MASKP31 Position   */
+#define GPIO_PORT_MASK6_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos)                   /*!< GPIO_PORT MASK6: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_MASK7  ----------------------------------------
+#define GPIO_PORT_MASK7_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK7: MASKP0 Position    */
+#define GPIO_PORT_MASK7_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos)                    /*!< GPIO_PORT MASK7: MASKP0 Mask        */
+#define GPIO_PORT_MASK7_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK7: MASKP1 Position    */
+#define GPIO_PORT_MASK7_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos)                    /*!< GPIO_PORT MASK7: MASKP1 Mask        */
+#define GPIO_PORT_MASK7_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK7: MASKP2 Position    */
+#define GPIO_PORT_MASK7_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos)                    /*!< GPIO_PORT MASK7: MASKP2 Mask        */
+#define GPIO_PORT_MASK7_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK7: MASKP3 Position    */
+#define GPIO_PORT_MASK7_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos)                    /*!< GPIO_PORT MASK7: MASKP3 Mask        */
+#define GPIO_PORT_MASK7_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK7: MASKP4 Position    */
+#define GPIO_PORT_MASK7_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos)                    /*!< GPIO_PORT MASK7: MASKP4 Mask        */
+#define GPIO_PORT_MASK7_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK7: MASKP5 Position    */
+#define GPIO_PORT_MASK7_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos)                    /*!< GPIO_PORT MASK7: MASKP5 Mask        */
+#define GPIO_PORT_MASK7_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK7: MASKP6 Position    */
+#define GPIO_PORT_MASK7_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos)                    /*!< GPIO_PORT MASK7: MASKP6 Mask        */
+#define GPIO_PORT_MASK7_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK7: MASKP7 Position    */
+#define GPIO_PORT_MASK7_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos)                    /*!< GPIO_PORT MASK7: MASKP7 Mask        */
+#define GPIO_PORT_MASK7_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK7: MASKP8 Position    */
+#define GPIO_PORT_MASK7_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos)                    /*!< GPIO_PORT MASK7: MASKP8 Mask        */
+#define GPIO_PORT_MASK7_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK7: MASKP9 Position    */
+#define GPIO_PORT_MASK7_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos)                    /*!< GPIO_PORT MASK7: MASKP9 Mask        */
+#define GPIO_PORT_MASK7_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK7: MASKP10 Position   */
+#define GPIO_PORT_MASK7_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos)                   /*!< GPIO_PORT MASK7: MASKP10 Mask       */
+#define GPIO_PORT_MASK7_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK7: MASKP11 Position   */
+#define GPIO_PORT_MASK7_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos)                   /*!< GPIO_PORT MASK7: MASKP11 Mask       */
+#define GPIO_PORT_MASK7_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK7: MASKP12 Position   */
+#define GPIO_PORT_MASK7_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos)                   /*!< GPIO_PORT MASK7: MASKP12 Mask       */
+#define GPIO_PORT_MASK7_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK7: MASKP13 Position   */
+#define GPIO_PORT_MASK7_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos)                   /*!< GPIO_PORT MASK7: MASKP13 Mask       */
+#define GPIO_PORT_MASK7_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK7: MASKP14 Position   */
+#define GPIO_PORT_MASK7_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos)                   /*!< GPIO_PORT MASK7: MASKP14 Mask       */
+#define GPIO_PORT_MASK7_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK7: MASKP15 Position   */
+#define GPIO_PORT_MASK7_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos)                   /*!< GPIO_PORT MASK7: MASKP15 Mask       */
+#define GPIO_PORT_MASK7_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK7: MASKP16 Position   */
+#define GPIO_PORT_MASK7_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos)                   /*!< GPIO_PORT MASK7: MASKP16 Mask       */
+#define GPIO_PORT_MASK7_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK7: MASKP17 Position   */
+#define GPIO_PORT_MASK7_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos)                   /*!< GPIO_PORT MASK7: MASKP17 Mask       */
+#define GPIO_PORT_MASK7_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK7: MASKP18 Position   */
+#define GPIO_PORT_MASK7_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos)                   /*!< GPIO_PORT MASK7: MASKP18 Mask       */
+#define GPIO_PORT_MASK7_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK7: MASKP19 Position   */
+#define GPIO_PORT_MASK7_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos)                   /*!< GPIO_PORT MASK7: MASKP19 Mask       */
+#define GPIO_PORT_MASK7_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK7: MASKP20 Position   */
+#define GPIO_PORT_MASK7_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos)                   /*!< GPIO_PORT MASK7: MASKP20 Mask       */
+#define GPIO_PORT_MASK7_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK7: MASKP21 Position   */
+#define GPIO_PORT_MASK7_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos)                   /*!< GPIO_PORT MASK7: MASKP21 Mask       */
+#define GPIO_PORT_MASK7_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK7: MASKP22 Position   */
+#define GPIO_PORT_MASK7_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos)                   /*!< GPIO_PORT MASK7: MASKP22 Mask       */
+#define GPIO_PORT_MASK7_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK7: MASKP23 Position   */
+#define GPIO_PORT_MASK7_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos)                   /*!< GPIO_PORT MASK7: MASKP23 Mask       */
+#define GPIO_PORT_MASK7_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK7: MASKP24 Position   */
+#define GPIO_PORT_MASK7_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos)                   /*!< GPIO_PORT MASK7: MASKP24 Mask       */
+#define GPIO_PORT_MASK7_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK7: MASKP25 Position   */
+#define GPIO_PORT_MASK7_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos)                   /*!< GPIO_PORT MASK7: MASKP25 Mask       */
+#define GPIO_PORT_MASK7_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK7: MASKP26 Position   */
+#define GPIO_PORT_MASK7_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos)                   /*!< GPIO_PORT MASK7: MASKP26 Mask       */
+#define GPIO_PORT_MASK7_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK7: MASKP27 Position   */
+#define GPIO_PORT_MASK7_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos)                   /*!< GPIO_PORT MASK7: MASKP27 Mask       */
+#define GPIO_PORT_MASK7_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK7: MASKP28 Position   */
+#define GPIO_PORT_MASK7_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos)                   /*!< GPIO_PORT MASK7: MASKP28 Mask       */
+#define GPIO_PORT_MASK7_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK7: MASKP29 Position   */
+#define GPIO_PORT_MASK7_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos)                   /*!< GPIO_PORT MASK7: MASKP29 Mask       */
+#define GPIO_PORT_MASK7_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK7: MASKP30 Position   */
+#define GPIO_PORT_MASK7_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos)                   /*!< GPIO_PORT MASK7: MASKP30 Mask       */
+#define GPIO_PORT_MASK7_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK7: MASKP31 Position   */
+#define GPIO_PORT_MASK7_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos)                   /*!< GPIO_PORT MASK7: MASKP31 Mask       */
+
+// -------------------------------------  GPIO_PORT_PIN0  -----------------------------------------
+#define GPIO_PORT_PIN0_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN0: PORT0 Position      */
+#define GPIO_PORT_PIN0_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT0_Pos)                      /*!< GPIO_PORT PIN0: PORT0 Mask          */
+#define GPIO_PORT_PIN0_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN0: PORT1 Position      */
+#define GPIO_PORT_PIN0_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT1_Pos)                      /*!< GPIO_PORT PIN0: PORT1 Mask          */
+#define GPIO_PORT_PIN0_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN0: PORT2 Position      */
+#define GPIO_PORT_PIN0_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT2_Pos)                      /*!< GPIO_PORT PIN0: PORT2 Mask          */
+#define GPIO_PORT_PIN0_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN0: PORT3 Position      */
+#define GPIO_PORT_PIN0_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT3_Pos)                      /*!< GPIO_PORT PIN0: PORT3 Mask          */
+#define GPIO_PORT_PIN0_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN0: PORT4 Position      */
+#define GPIO_PORT_PIN0_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT4_Pos)                      /*!< GPIO_PORT PIN0: PORT4 Mask          */
+#define GPIO_PORT_PIN0_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN0: PORT5 Position      */
+#define GPIO_PORT_PIN0_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT5_Pos)                      /*!< GPIO_PORT PIN0: PORT5 Mask          */
+#define GPIO_PORT_PIN0_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN0: PORT6 Position      */
+#define GPIO_PORT_PIN0_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT6_Pos)                      /*!< GPIO_PORT PIN0: PORT6 Mask          */
+#define GPIO_PORT_PIN0_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN0: PORT7 Position      */
+#define GPIO_PORT_PIN0_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT7_Pos)                      /*!< GPIO_PORT PIN0: PORT7 Mask          */
+#define GPIO_PORT_PIN0_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN0: PORT8 Position      */
+#define GPIO_PORT_PIN0_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT8_Pos)                      /*!< GPIO_PORT PIN0: PORT8 Mask          */
+#define GPIO_PORT_PIN0_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN0: PORT9 Position      */
+#define GPIO_PORT_PIN0_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT9_Pos)                      /*!< GPIO_PORT PIN0: PORT9 Mask          */
+#define GPIO_PORT_PIN0_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN0: PORT10 Position     */
+#define GPIO_PORT_PIN0_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT10_Pos)                     /*!< GPIO_PORT PIN0: PORT10 Mask         */
+#define GPIO_PORT_PIN0_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN0: PORT11 Position     */
+#define GPIO_PORT_PIN0_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT11_Pos)                     /*!< GPIO_PORT PIN0: PORT11 Mask         */
+#define GPIO_PORT_PIN0_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN0: PORT12 Position     */
+#define GPIO_PORT_PIN0_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT12_Pos)                     /*!< GPIO_PORT PIN0: PORT12 Mask         */
+#define GPIO_PORT_PIN0_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN0: PORT13 Position     */
+#define GPIO_PORT_PIN0_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT13_Pos)                     /*!< GPIO_PORT PIN0: PORT13 Mask         */
+#define GPIO_PORT_PIN0_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN0: PORT14 Position     */
+#define GPIO_PORT_PIN0_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT14_Pos)                     /*!< GPIO_PORT PIN0: PORT14 Mask         */
+#define GPIO_PORT_PIN0_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN0: PORT15 Position     */
+#define GPIO_PORT_PIN0_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT15_Pos)                     /*!< GPIO_PORT PIN0: PORT15 Mask         */
+#define GPIO_PORT_PIN0_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN0: PORT16 Position     */
+#define GPIO_PORT_PIN0_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT16_Pos)                     /*!< GPIO_PORT PIN0: PORT16 Mask         */
+#define GPIO_PORT_PIN0_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN0: PORT17 Position     */
+#define GPIO_PORT_PIN0_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT17_Pos)                     /*!< GPIO_PORT PIN0: PORT17 Mask         */
+#define GPIO_PORT_PIN0_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN0: PORT18 Position     */
+#define GPIO_PORT_PIN0_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT18_Pos)                     /*!< GPIO_PORT PIN0: PORT18 Mask         */
+#define GPIO_PORT_PIN0_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN0: PORT19 Position     */
+#define GPIO_PORT_PIN0_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT19_Pos)                     /*!< GPIO_PORT PIN0: PORT19 Mask         */
+#define GPIO_PORT_PIN0_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN0: PORT20 Position     */
+#define GPIO_PORT_PIN0_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT20_Pos)                     /*!< GPIO_PORT PIN0: PORT20 Mask         */
+#define GPIO_PORT_PIN0_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN0: PORT21 Position     */
+#define GPIO_PORT_PIN0_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT21_Pos)                     /*!< GPIO_PORT PIN0: PORT21 Mask         */
+#define GPIO_PORT_PIN0_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN0: PORT22 Position     */
+#define GPIO_PORT_PIN0_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT22_Pos)                     /*!< GPIO_PORT PIN0: PORT22 Mask         */
+#define GPIO_PORT_PIN0_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN0: PORT23 Position     */
+#define GPIO_PORT_PIN0_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT23_Pos)                     /*!< GPIO_PORT PIN0: PORT23 Mask         */
+#define GPIO_PORT_PIN0_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN0: PORT24 Position     */
+#define GPIO_PORT_PIN0_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT24_Pos)                     /*!< GPIO_PORT PIN0: PORT24 Mask         */
+#define GPIO_PORT_PIN0_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN0: PORT25 Position     */
+#define GPIO_PORT_PIN0_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT25_Pos)                     /*!< GPIO_PORT PIN0: PORT25 Mask         */
+#define GPIO_PORT_PIN0_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN0: PORT26 Position     */
+#define GPIO_PORT_PIN0_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT26_Pos)                     /*!< GPIO_PORT PIN0: PORT26 Mask         */
+#define GPIO_PORT_PIN0_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN0: PORT27 Position     */
+#define GPIO_PORT_PIN0_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT27_Pos)                     /*!< GPIO_PORT PIN0: PORT27 Mask         */
+#define GPIO_PORT_PIN0_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN0: PORT28 Position     */
+#define GPIO_PORT_PIN0_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT28_Pos)                     /*!< GPIO_PORT PIN0: PORT28 Mask         */
+#define GPIO_PORT_PIN0_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN0: PORT29 Position     */
+#define GPIO_PORT_PIN0_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT29_Pos)                     /*!< GPIO_PORT PIN0: PORT29 Mask         */
+#define GPIO_PORT_PIN0_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN0: PORT30 Position     */
+#define GPIO_PORT_PIN0_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT30_Pos)                     /*!< GPIO_PORT PIN0: PORT30 Mask         */
+#define GPIO_PORT_PIN0_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN0: PORT31 Position     */
+#define GPIO_PORT_PIN0_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT31_Pos)                     /*!< GPIO_PORT PIN0: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN1  -----------------------------------------
+#define GPIO_PORT_PIN1_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN1: PORT0 Position      */
+#define GPIO_PORT_PIN1_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT0_Pos)                      /*!< GPIO_PORT PIN1: PORT0 Mask          */
+#define GPIO_PORT_PIN1_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN1: PORT1 Position      */
+#define GPIO_PORT_PIN1_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT1_Pos)                      /*!< GPIO_PORT PIN1: PORT1 Mask          */
+#define GPIO_PORT_PIN1_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN1: PORT2 Position      */
+#define GPIO_PORT_PIN1_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT2_Pos)                      /*!< GPIO_PORT PIN1: PORT2 Mask          */
+#define GPIO_PORT_PIN1_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN1: PORT3 Position      */
+#define GPIO_PORT_PIN1_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT3_Pos)                      /*!< GPIO_PORT PIN1: PORT3 Mask          */
+#define GPIO_PORT_PIN1_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN1: PORT4 Position      */
+#define GPIO_PORT_PIN1_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT4_Pos)                      /*!< GPIO_PORT PIN1: PORT4 Mask          */
+#define GPIO_PORT_PIN1_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN1: PORT5 Position      */
+#define GPIO_PORT_PIN1_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT5_Pos)                      /*!< GPIO_PORT PIN1: PORT5 Mask          */
+#define GPIO_PORT_PIN1_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN1: PORT6 Position      */
+#define GPIO_PORT_PIN1_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT6_Pos)                      /*!< GPIO_PORT PIN1: PORT6 Mask          */
+#define GPIO_PORT_PIN1_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN1: PORT7 Position      */
+#define GPIO_PORT_PIN1_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT7_Pos)                      /*!< GPIO_PORT PIN1: PORT7 Mask          */
+#define GPIO_PORT_PIN1_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN1: PORT8 Position      */
+#define GPIO_PORT_PIN1_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT8_Pos)                      /*!< GPIO_PORT PIN1: PORT8 Mask          */
+#define GPIO_PORT_PIN1_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN1: PORT9 Position      */
+#define GPIO_PORT_PIN1_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT9_Pos)                      /*!< GPIO_PORT PIN1: PORT9 Mask          */
+#define GPIO_PORT_PIN1_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN1: PORT10 Position     */
+#define GPIO_PORT_PIN1_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT10_Pos)                     /*!< GPIO_PORT PIN1: PORT10 Mask         */
+#define GPIO_PORT_PIN1_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN1: PORT11 Position     */
+#define GPIO_PORT_PIN1_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT11_Pos)                     /*!< GPIO_PORT PIN1: PORT11 Mask         */
+#define GPIO_PORT_PIN1_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN1: PORT12 Position     */
+#define GPIO_PORT_PIN1_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT12_Pos)                     /*!< GPIO_PORT PIN1: PORT12 Mask         */
+#define GPIO_PORT_PIN1_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN1: PORT13 Position     */
+#define GPIO_PORT_PIN1_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT13_Pos)                     /*!< GPIO_PORT PIN1: PORT13 Mask         */
+#define GPIO_PORT_PIN1_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN1: PORT14 Position     */
+#define GPIO_PORT_PIN1_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT14_Pos)                     /*!< GPIO_PORT PIN1: PORT14 Mask         */
+#define GPIO_PORT_PIN1_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN1: PORT15 Position     */
+#define GPIO_PORT_PIN1_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT15_Pos)                     /*!< GPIO_PORT PIN1: PORT15 Mask         */
+#define GPIO_PORT_PIN1_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN1: PORT16 Position     */
+#define GPIO_PORT_PIN1_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT16_Pos)                     /*!< GPIO_PORT PIN1: PORT16 Mask         */
+#define GPIO_PORT_PIN1_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN1: PORT17 Position     */
+#define GPIO_PORT_PIN1_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT17_Pos)                     /*!< GPIO_PORT PIN1: PORT17 Mask         */
+#define GPIO_PORT_PIN1_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN1: PORT18 Position     */
+#define GPIO_PORT_PIN1_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT18_Pos)                     /*!< GPIO_PORT PIN1: PORT18 Mask         */
+#define GPIO_PORT_PIN1_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN1: PORT19 Position     */
+#define GPIO_PORT_PIN1_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT19_Pos)                     /*!< GPIO_PORT PIN1: PORT19 Mask         */
+#define GPIO_PORT_PIN1_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN1: PORT20 Position     */
+#define GPIO_PORT_PIN1_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT20_Pos)                     /*!< GPIO_PORT PIN1: PORT20 Mask         */
+#define GPIO_PORT_PIN1_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN1: PORT21 Position     */
+#define GPIO_PORT_PIN1_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT21_Pos)                     /*!< GPIO_PORT PIN1: PORT21 Mask         */
+#define GPIO_PORT_PIN1_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN1: PORT22 Position     */
+#define GPIO_PORT_PIN1_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT22_Pos)                     /*!< GPIO_PORT PIN1: PORT22 Mask         */
+#define GPIO_PORT_PIN1_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN1: PORT23 Position     */
+#define GPIO_PORT_PIN1_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT23_Pos)                     /*!< GPIO_PORT PIN1: PORT23 Mask         */
+#define GPIO_PORT_PIN1_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN1: PORT24 Position     */
+#define GPIO_PORT_PIN1_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT24_Pos)                     /*!< GPIO_PORT PIN1: PORT24 Mask         */
+#define GPIO_PORT_PIN1_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN1: PORT25 Position     */
+#define GPIO_PORT_PIN1_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT25_Pos)                     /*!< GPIO_PORT PIN1: PORT25 Mask         */
+#define GPIO_PORT_PIN1_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN1: PORT26 Position     */
+#define GPIO_PORT_PIN1_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT26_Pos)                     /*!< GPIO_PORT PIN1: PORT26 Mask         */
+#define GPIO_PORT_PIN1_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN1: PORT27 Position     */
+#define GPIO_PORT_PIN1_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT27_Pos)                     /*!< GPIO_PORT PIN1: PORT27 Mask         */
+#define GPIO_PORT_PIN1_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN1: PORT28 Position     */
+#define GPIO_PORT_PIN1_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT28_Pos)                     /*!< GPIO_PORT PIN1: PORT28 Mask         */
+#define GPIO_PORT_PIN1_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN1: PORT29 Position     */
+#define GPIO_PORT_PIN1_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT29_Pos)                     /*!< GPIO_PORT PIN1: PORT29 Mask         */
+#define GPIO_PORT_PIN1_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN1: PORT30 Position     */
+#define GPIO_PORT_PIN1_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT30_Pos)                     /*!< GPIO_PORT PIN1: PORT30 Mask         */
+#define GPIO_PORT_PIN1_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN1: PORT31 Position     */
+#define GPIO_PORT_PIN1_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT31_Pos)                     /*!< GPIO_PORT PIN1: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN2  -----------------------------------------
+#define GPIO_PORT_PIN2_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN2: PORT0 Position      */
+#define GPIO_PORT_PIN2_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT0_Pos)                      /*!< GPIO_PORT PIN2: PORT0 Mask          */
+#define GPIO_PORT_PIN2_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN2: PORT1 Position      */
+#define GPIO_PORT_PIN2_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT1_Pos)                      /*!< GPIO_PORT PIN2: PORT1 Mask          */
+#define GPIO_PORT_PIN2_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN2: PORT2 Position      */
+#define GPIO_PORT_PIN2_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT2_Pos)                      /*!< GPIO_PORT PIN2: PORT2 Mask          */
+#define GPIO_PORT_PIN2_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN2: PORT3 Position      */
+#define GPIO_PORT_PIN2_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT3_Pos)                      /*!< GPIO_PORT PIN2: PORT3 Mask          */
+#define GPIO_PORT_PIN2_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN2: PORT4 Position      */
+#define GPIO_PORT_PIN2_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT4_Pos)                      /*!< GPIO_PORT PIN2: PORT4 Mask          */
+#define GPIO_PORT_PIN2_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN2: PORT5 Position      */
+#define GPIO_PORT_PIN2_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT5_Pos)                      /*!< GPIO_PORT PIN2: PORT5 Mask          */
+#define GPIO_PORT_PIN2_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN2: PORT6 Position      */
+#define GPIO_PORT_PIN2_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT6_Pos)                      /*!< GPIO_PORT PIN2: PORT6 Mask          */
+#define GPIO_PORT_PIN2_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN2: PORT7 Position      */
+#define GPIO_PORT_PIN2_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT7_Pos)                      /*!< GPIO_PORT PIN2: PORT7 Mask          */
+#define GPIO_PORT_PIN2_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN2: PORT8 Position      */
+#define GPIO_PORT_PIN2_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT8_Pos)                      /*!< GPIO_PORT PIN2: PORT8 Mask          */
+#define GPIO_PORT_PIN2_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN2: PORT9 Position      */
+#define GPIO_PORT_PIN2_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT9_Pos)                      /*!< GPIO_PORT PIN2: PORT9 Mask          */
+#define GPIO_PORT_PIN2_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN2: PORT10 Position     */
+#define GPIO_PORT_PIN2_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT10_Pos)                     /*!< GPIO_PORT PIN2: PORT10 Mask         */
+#define GPIO_PORT_PIN2_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN2: PORT11 Position     */
+#define GPIO_PORT_PIN2_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT11_Pos)                     /*!< GPIO_PORT PIN2: PORT11 Mask         */
+#define GPIO_PORT_PIN2_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN2: PORT12 Position     */
+#define GPIO_PORT_PIN2_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT12_Pos)                     /*!< GPIO_PORT PIN2: PORT12 Mask         */
+#define GPIO_PORT_PIN2_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN2: PORT13 Position     */
+#define GPIO_PORT_PIN2_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT13_Pos)                     /*!< GPIO_PORT PIN2: PORT13 Mask         */
+#define GPIO_PORT_PIN2_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN2: PORT14 Position     */
+#define GPIO_PORT_PIN2_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT14_Pos)                     /*!< GPIO_PORT PIN2: PORT14 Mask         */
+#define GPIO_PORT_PIN2_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN2: PORT15 Position     */
+#define GPIO_PORT_PIN2_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT15_Pos)                     /*!< GPIO_PORT PIN2: PORT15 Mask         */
+#define GPIO_PORT_PIN2_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN2: PORT16 Position     */
+#define GPIO_PORT_PIN2_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT16_Pos)                     /*!< GPIO_PORT PIN2: PORT16 Mask         */
+#define GPIO_PORT_PIN2_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN2: PORT17 Position     */
+#define GPIO_PORT_PIN2_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT17_Pos)                     /*!< GPIO_PORT PIN2: PORT17 Mask         */
+#define GPIO_PORT_PIN2_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN2: PORT18 Position     */
+#define GPIO_PORT_PIN2_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT18_Pos)                     /*!< GPIO_PORT PIN2: PORT18 Mask         */
+#define GPIO_PORT_PIN2_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN2: PORT19 Position     */
+#define GPIO_PORT_PIN2_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT19_Pos)                     /*!< GPIO_PORT PIN2: PORT19 Mask         */
+#define GPIO_PORT_PIN2_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN2: PORT20 Position     */
+#define GPIO_PORT_PIN2_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT20_Pos)                     /*!< GPIO_PORT PIN2: PORT20 Mask         */
+#define GPIO_PORT_PIN2_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN2: PORT21 Position     */
+#define GPIO_PORT_PIN2_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT21_Pos)                     /*!< GPIO_PORT PIN2: PORT21 Mask         */
+#define GPIO_PORT_PIN2_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN2: PORT22 Position     */
+#define GPIO_PORT_PIN2_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT22_Pos)                     /*!< GPIO_PORT PIN2: PORT22 Mask         */
+#define GPIO_PORT_PIN2_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN2: PORT23 Position     */
+#define GPIO_PORT_PIN2_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT23_Pos)                     /*!< GPIO_PORT PIN2: PORT23 Mask         */
+#define GPIO_PORT_PIN2_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN2: PORT24 Position     */
+#define GPIO_PORT_PIN2_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT24_Pos)                     /*!< GPIO_PORT PIN2: PORT24 Mask         */
+#define GPIO_PORT_PIN2_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN2: PORT25 Position     */
+#define GPIO_PORT_PIN2_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT25_Pos)                     /*!< GPIO_PORT PIN2: PORT25 Mask         */
+#define GPIO_PORT_PIN2_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN2: PORT26 Position     */
+#define GPIO_PORT_PIN2_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT26_Pos)                     /*!< GPIO_PORT PIN2: PORT26 Mask         */
+#define GPIO_PORT_PIN2_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN2: PORT27 Position     */
+#define GPIO_PORT_PIN2_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT27_Pos)                     /*!< GPIO_PORT PIN2: PORT27 Mask         */
+#define GPIO_PORT_PIN2_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN2: PORT28 Position     */
+#define GPIO_PORT_PIN2_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT28_Pos)                     /*!< GPIO_PORT PIN2: PORT28 Mask         */
+#define GPIO_PORT_PIN2_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN2: PORT29 Position     */
+#define GPIO_PORT_PIN2_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT29_Pos)                     /*!< GPIO_PORT PIN2: PORT29 Mask         */
+#define GPIO_PORT_PIN2_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN2: PORT30 Position     */
+#define GPIO_PORT_PIN2_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT30_Pos)                     /*!< GPIO_PORT PIN2: PORT30 Mask         */
+#define GPIO_PORT_PIN2_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN2: PORT31 Position     */
+#define GPIO_PORT_PIN2_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT31_Pos)                     /*!< GPIO_PORT PIN2: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN3  -----------------------------------------
+#define GPIO_PORT_PIN3_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN3: PORT0 Position      */
+#define GPIO_PORT_PIN3_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT0_Pos)                      /*!< GPIO_PORT PIN3: PORT0 Mask          */
+#define GPIO_PORT_PIN3_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN3: PORT1 Position      */
+#define GPIO_PORT_PIN3_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT1_Pos)                      /*!< GPIO_PORT PIN3: PORT1 Mask          */
+#define GPIO_PORT_PIN3_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN3: PORT2 Position      */
+#define GPIO_PORT_PIN3_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT2_Pos)                      /*!< GPIO_PORT PIN3: PORT2 Mask          */
+#define GPIO_PORT_PIN3_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN3: PORT3 Position      */
+#define GPIO_PORT_PIN3_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT3_Pos)                      /*!< GPIO_PORT PIN3: PORT3 Mask          */
+#define GPIO_PORT_PIN3_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN3: PORT4 Position      */
+#define GPIO_PORT_PIN3_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT4_Pos)                      /*!< GPIO_PORT PIN3: PORT4 Mask          */
+#define GPIO_PORT_PIN3_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN3: PORT5 Position      */
+#define GPIO_PORT_PIN3_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT5_Pos)                      /*!< GPIO_PORT PIN3: PORT5 Mask          */
+#define GPIO_PORT_PIN3_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN3: PORT6 Position      */
+#define GPIO_PORT_PIN3_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT6_Pos)                      /*!< GPIO_PORT PIN3: PORT6 Mask          */
+#define GPIO_PORT_PIN3_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN3: PORT7 Position      */
+#define GPIO_PORT_PIN3_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT7_Pos)                      /*!< GPIO_PORT PIN3: PORT7 Mask          */
+#define GPIO_PORT_PIN3_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN3: PORT8 Position      */
+#define GPIO_PORT_PIN3_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT8_Pos)                      /*!< GPIO_PORT PIN3: PORT8 Mask          */
+#define GPIO_PORT_PIN3_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN3: PORT9 Position      */
+#define GPIO_PORT_PIN3_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT9_Pos)                      /*!< GPIO_PORT PIN3: PORT9 Mask          */
+#define GPIO_PORT_PIN3_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN3: PORT10 Position     */
+#define GPIO_PORT_PIN3_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT10_Pos)                     /*!< GPIO_PORT PIN3: PORT10 Mask         */
+#define GPIO_PORT_PIN3_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN3: PORT11 Position     */
+#define GPIO_PORT_PIN3_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT11_Pos)                     /*!< GPIO_PORT PIN3: PORT11 Mask         */
+#define GPIO_PORT_PIN3_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN3: PORT12 Position     */
+#define GPIO_PORT_PIN3_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT12_Pos)                     /*!< GPIO_PORT PIN3: PORT12 Mask         */
+#define GPIO_PORT_PIN3_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN3: PORT13 Position     */
+#define GPIO_PORT_PIN3_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT13_Pos)                     /*!< GPIO_PORT PIN3: PORT13 Mask         */
+#define GPIO_PORT_PIN3_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN3: PORT14 Position     */
+#define GPIO_PORT_PIN3_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT14_Pos)                     /*!< GPIO_PORT PIN3: PORT14 Mask         */
+#define GPIO_PORT_PIN3_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN3: PORT15 Position     */
+#define GPIO_PORT_PIN3_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT15_Pos)                     /*!< GPIO_PORT PIN3: PORT15 Mask         */
+#define GPIO_PORT_PIN3_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN3: PORT16 Position     */
+#define GPIO_PORT_PIN3_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT16_Pos)                     /*!< GPIO_PORT PIN3: PORT16 Mask         */
+#define GPIO_PORT_PIN3_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN3: PORT17 Position     */
+#define GPIO_PORT_PIN3_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT17_Pos)                     /*!< GPIO_PORT PIN3: PORT17 Mask         */
+#define GPIO_PORT_PIN3_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN3: PORT18 Position     */
+#define GPIO_PORT_PIN3_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT18_Pos)                     /*!< GPIO_PORT PIN3: PORT18 Mask         */
+#define GPIO_PORT_PIN3_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN3: PORT19 Position     */
+#define GPIO_PORT_PIN3_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT19_Pos)                     /*!< GPIO_PORT PIN3: PORT19 Mask         */
+#define GPIO_PORT_PIN3_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN3: PORT20 Position     */
+#define GPIO_PORT_PIN3_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT20_Pos)                     /*!< GPIO_PORT PIN3: PORT20 Mask         */
+#define GPIO_PORT_PIN3_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN3: PORT21 Position     */
+#define GPIO_PORT_PIN3_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT21_Pos)                     /*!< GPIO_PORT PIN3: PORT21 Mask         */
+#define GPIO_PORT_PIN3_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN3: PORT22 Position     */
+#define GPIO_PORT_PIN3_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT22_Pos)                     /*!< GPIO_PORT PIN3: PORT22 Mask         */
+#define GPIO_PORT_PIN3_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN3: PORT23 Position     */
+#define GPIO_PORT_PIN3_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT23_Pos)                     /*!< GPIO_PORT PIN3: PORT23 Mask         */
+#define GPIO_PORT_PIN3_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN3: PORT24 Position     */
+#define GPIO_PORT_PIN3_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT24_Pos)                     /*!< GPIO_PORT PIN3: PORT24 Mask         */
+#define GPIO_PORT_PIN3_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN3: PORT25 Position     */
+#define GPIO_PORT_PIN3_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT25_Pos)                     /*!< GPIO_PORT PIN3: PORT25 Mask         */
+#define GPIO_PORT_PIN3_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN3: PORT26 Position     */
+#define GPIO_PORT_PIN3_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT26_Pos)                     /*!< GPIO_PORT PIN3: PORT26 Mask         */
+#define GPIO_PORT_PIN3_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN3: PORT27 Position     */
+#define GPIO_PORT_PIN3_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT27_Pos)                     /*!< GPIO_PORT PIN3: PORT27 Mask         */
+#define GPIO_PORT_PIN3_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN3: PORT28 Position     */
+#define GPIO_PORT_PIN3_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT28_Pos)                     /*!< GPIO_PORT PIN3: PORT28 Mask         */
+#define GPIO_PORT_PIN3_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN3: PORT29 Position     */
+#define GPIO_PORT_PIN3_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT29_Pos)                     /*!< GPIO_PORT PIN3: PORT29 Mask         */
+#define GPIO_PORT_PIN3_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN3: PORT30 Position     */
+#define GPIO_PORT_PIN3_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT30_Pos)                     /*!< GPIO_PORT PIN3: PORT30 Mask         */
+#define GPIO_PORT_PIN3_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN3: PORT31 Position     */
+#define GPIO_PORT_PIN3_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT31_Pos)                     /*!< GPIO_PORT PIN3: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN4  -----------------------------------------
+#define GPIO_PORT_PIN4_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN4: PORT0 Position      */
+#define GPIO_PORT_PIN4_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT0_Pos)                      /*!< GPIO_PORT PIN4: PORT0 Mask          */
+#define GPIO_PORT_PIN4_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN4: PORT1 Position      */
+#define GPIO_PORT_PIN4_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT1_Pos)                      /*!< GPIO_PORT PIN4: PORT1 Mask          */
+#define GPIO_PORT_PIN4_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN4: PORT2 Position      */
+#define GPIO_PORT_PIN4_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT2_Pos)                      /*!< GPIO_PORT PIN4: PORT2 Mask          */
+#define GPIO_PORT_PIN4_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN4: PORT3 Position      */
+#define GPIO_PORT_PIN4_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT3_Pos)                      /*!< GPIO_PORT PIN4: PORT3 Mask          */
+#define GPIO_PORT_PIN4_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN4: PORT4 Position      */
+#define GPIO_PORT_PIN4_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT4_Pos)                      /*!< GPIO_PORT PIN4: PORT4 Mask          */
+#define GPIO_PORT_PIN4_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN4: PORT5 Position      */
+#define GPIO_PORT_PIN4_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT5_Pos)                      /*!< GPIO_PORT PIN4: PORT5 Mask          */
+#define GPIO_PORT_PIN4_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN4: PORT6 Position      */
+#define GPIO_PORT_PIN4_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT6_Pos)                      /*!< GPIO_PORT PIN4: PORT6 Mask          */
+#define GPIO_PORT_PIN4_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN4: PORT7 Position      */
+#define GPIO_PORT_PIN4_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT7_Pos)                      /*!< GPIO_PORT PIN4: PORT7 Mask          */
+#define GPIO_PORT_PIN4_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN4: PORT8 Position      */
+#define GPIO_PORT_PIN4_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT8_Pos)                      /*!< GPIO_PORT PIN4: PORT8 Mask          */
+#define GPIO_PORT_PIN4_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN4: PORT9 Position      */
+#define GPIO_PORT_PIN4_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT9_Pos)                      /*!< GPIO_PORT PIN4: PORT9 Mask          */
+#define GPIO_PORT_PIN4_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN4: PORT10 Position     */
+#define GPIO_PORT_PIN4_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT10_Pos)                     /*!< GPIO_PORT PIN4: PORT10 Mask         */
+#define GPIO_PORT_PIN4_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN4: PORT11 Position     */
+#define GPIO_PORT_PIN4_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT11_Pos)                     /*!< GPIO_PORT PIN4: PORT11 Mask         */
+#define GPIO_PORT_PIN4_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN4: PORT12 Position     */
+#define GPIO_PORT_PIN4_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT12_Pos)                     /*!< GPIO_PORT PIN4: PORT12 Mask         */
+#define GPIO_PORT_PIN4_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN4: PORT13 Position     */
+#define GPIO_PORT_PIN4_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT13_Pos)                     /*!< GPIO_PORT PIN4: PORT13 Mask         */
+#define GPIO_PORT_PIN4_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN4: PORT14 Position     */
+#define GPIO_PORT_PIN4_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT14_Pos)                     /*!< GPIO_PORT PIN4: PORT14 Mask         */
+#define GPIO_PORT_PIN4_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN4: PORT15 Position     */
+#define GPIO_PORT_PIN4_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT15_Pos)                     /*!< GPIO_PORT PIN4: PORT15 Mask         */
+#define GPIO_PORT_PIN4_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN4: PORT16 Position     */
+#define GPIO_PORT_PIN4_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT16_Pos)                     /*!< GPIO_PORT PIN4: PORT16 Mask         */
+#define GPIO_PORT_PIN4_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN4: PORT17 Position     */
+#define GPIO_PORT_PIN4_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT17_Pos)                     /*!< GPIO_PORT PIN4: PORT17 Mask         */
+#define GPIO_PORT_PIN4_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN4: PORT18 Position     */
+#define GPIO_PORT_PIN4_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT18_Pos)                     /*!< GPIO_PORT PIN4: PORT18 Mask         */
+#define GPIO_PORT_PIN4_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN4: PORT19 Position     */
+#define GPIO_PORT_PIN4_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT19_Pos)                     /*!< GPIO_PORT PIN4: PORT19 Mask         */
+#define GPIO_PORT_PIN4_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN4: PORT20 Position     */
+#define GPIO_PORT_PIN4_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT20_Pos)                     /*!< GPIO_PORT PIN4: PORT20 Mask         */
+#define GPIO_PORT_PIN4_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN4: PORT21 Position     */
+#define GPIO_PORT_PIN4_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT21_Pos)                     /*!< GPIO_PORT PIN4: PORT21 Mask         */
+#define GPIO_PORT_PIN4_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN4: PORT22 Position     */
+#define GPIO_PORT_PIN4_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT22_Pos)                     /*!< GPIO_PORT PIN4: PORT22 Mask         */
+#define GPIO_PORT_PIN4_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN4: PORT23 Position     */
+#define GPIO_PORT_PIN4_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT23_Pos)                     /*!< GPIO_PORT PIN4: PORT23 Mask         */
+#define GPIO_PORT_PIN4_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN4: PORT24 Position     */
+#define GPIO_PORT_PIN4_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT24_Pos)                     /*!< GPIO_PORT PIN4: PORT24 Mask         */
+#define GPIO_PORT_PIN4_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN4: PORT25 Position     */
+#define GPIO_PORT_PIN4_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT25_Pos)                     /*!< GPIO_PORT PIN4: PORT25 Mask         */
+#define GPIO_PORT_PIN4_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN4: PORT26 Position     */
+#define GPIO_PORT_PIN4_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT26_Pos)                     /*!< GPIO_PORT PIN4: PORT26 Mask         */
+#define GPIO_PORT_PIN4_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN4: PORT27 Position     */
+#define GPIO_PORT_PIN4_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT27_Pos)                     /*!< GPIO_PORT PIN4: PORT27 Mask         */
+#define GPIO_PORT_PIN4_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN4: PORT28 Position     */
+#define GPIO_PORT_PIN4_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT28_Pos)                     /*!< GPIO_PORT PIN4: PORT28 Mask         */
+#define GPIO_PORT_PIN4_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN4: PORT29 Position     */
+#define GPIO_PORT_PIN4_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT29_Pos)                     /*!< GPIO_PORT PIN4: PORT29 Mask         */
+#define GPIO_PORT_PIN4_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN4: PORT30 Position     */
+#define GPIO_PORT_PIN4_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT30_Pos)                     /*!< GPIO_PORT PIN4: PORT30 Mask         */
+#define GPIO_PORT_PIN4_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN4: PORT31 Position     */
+#define GPIO_PORT_PIN4_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT31_Pos)                     /*!< GPIO_PORT PIN4: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN5  -----------------------------------------
+#define GPIO_PORT_PIN5_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN5: PORT0 Position      */
+#define GPIO_PORT_PIN5_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT0_Pos)                      /*!< GPIO_PORT PIN5: PORT0 Mask          */
+#define GPIO_PORT_PIN5_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN5: PORT1 Position      */
+#define GPIO_PORT_PIN5_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT1_Pos)                      /*!< GPIO_PORT PIN5: PORT1 Mask          */
+#define GPIO_PORT_PIN5_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN5: PORT2 Position      */
+#define GPIO_PORT_PIN5_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT2_Pos)                      /*!< GPIO_PORT PIN5: PORT2 Mask          */
+#define GPIO_PORT_PIN5_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN5: PORT3 Position      */
+#define GPIO_PORT_PIN5_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT3_Pos)                      /*!< GPIO_PORT PIN5: PORT3 Mask          */
+#define GPIO_PORT_PIN5_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN5: PORT4 Position      */
+#define GPIO_PORT_PIN5_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT4_Pos)                      /*!< GPIO_PORT PIN5: PORT4 Mask          */
+#define GPIO_PORT_PIN5_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN5: PORT5 Position      */
+#define GPIO_PORT_PIN5_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT5_Pos)                      /*!< GPIO_PORT PIN5: PORT5 Mask          */
+#define GPIO_PORT_PIN5_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN5: PORT6 Position      */
+#define GPIO_PORT_PIN5_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT6_Pos)                      /*!< GPIO_PORT PIN5: PORT6 Mask          */
+#define GPIO_PORT_PIN5_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN5: PORT7 Position      */
+#define GPIO_PORT_PIN5_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT7_Pos)                      /*!< GPIO_PORT PIN5: PORT7 Mask          */
+#define GPIO_PORT_PIN5_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN5: PORT8 Position      */
+#define GPIO_PORT_PIN5_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT8_Pos)                      /*!< GPIO_PORT PIN5: PORT8 Mask          */
+#define GPIO_PORT_PIN5_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN5: PORT9 Position      */
+#define GPIO_PORT_PIN5_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT9_Pos)                      /*!< GPIO_PORT PIN5: PORT9 Mask          */
+#define GPIO_PORT_PIN5_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN5: PORT10 Position     */
+#define GPIO_PORT_PIN5_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT10_Pos)                     /*!< GPIO_PORT PIN5: PORT10 Mask         */
+#define GPIO_PORT_PIN5_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN5: PORT11 Position     */
+#define GPIO_PORT_PIN5_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT11_Pos)                     /*!< GPIO_PORT PIN5: PORT11 Mask         */
+#define GPIO_PORT_PIN5_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN5: PORT12 Position     */
+#define GPIO_PORT_PIN5_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT12_Pos)                     /*!< GPIO_PORT PIN5: PORT12 Mask         */
+#define GPIO_PORT_PIN5_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN5: PORT13 Position     */
+#define GPIO_PORT_PIN5_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT13_Pos)                     /*!< GPIO_PORT PIN5: PORT13 Mask         */
+#define GPIO_PORT_PIN5_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN5: PORT14 Position     */
+#define GPIO_PORT_PIN5_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT14_Pos)                     /*!< GPIO_PORT PIN5: PORT14 Mask         */
+#define GPIO_PORT_PIN5_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN5: PORT15 Position     */
+#define GPIO_PORT_PIN5_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT15_Pos)                     /*!< GPIO_PORT PIN5: PORT15 Mask         */
+#define GPIO_PORT_PIN5_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN5: PORT16 Position     */
+#define GPIO_PORT_PIN5_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT16_Pos)                     /*!< GPIO_PORT PIN5: PORT16 Mask         */
+#define GPIO_PORT_PIN5_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN5: PORT17 Position     */
+#define GPIO_PORT_PIN5_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT17_Pos)                     /*!< GPIO_PORT PIN5: PORT17 Mask         */
+#define GPIO_PORT_PIN5_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN5: PORT18 Position     */
+#define GPIO_PORT_PIN5_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT18_Pos)                     /*!< GPIO_PORT PIN5: PORT18 Mask         */
+#define GPIO_PORT_PIN5_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN5: PORT19 Position     */
+#define GPIO_PORT_PIN5_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT19_Pos)                     /*!< GPIO_PORT PIN5: PORT19 Mask         */
+#define GPIO_PORT_PIN5_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN5: PORT20 Position     */
+#define GPIO_PORT_PIN5_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT20_Pos)                     /*!< GPIO_PORT PIN5: PORT20 Mask         */
+#define GPIO_PORT_PIN5_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN5: PORT21 Position     */
+#define GPIO_PORT_PIN5_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT21_Pos)                     /*!< GPIO_PORT PIN5: PORT21 Mask         */
+#define GPIO_PORT_PIN5_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN5: PORT22 Position     */
+#define GPIO_PORT_PIN5_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT22_Pos)                     /*!< GPIO_PORT PIN5: PORT22 Mask         */
+#define GPIO_PORT_PIN5_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN5: PORT23 Position     */
+#define GPIO_PORT_PIN5_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT23_Pos)                     /*!< GPIO_PORT PIN5: PORT23 Mask         */
+#define GPIO_PORT_PIN5_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN5: PORT24 Position     */
+#define GPIO_PORT_PIN5_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT24_Pos)                     /*!< GPIO_PORT PIN5: PORT24 Mask         */
+#define GPIO_PORT_PIN5_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN5: PORT25 Position     */
+#define GPIO_PORT_PIN5_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT25_Pos)                     /*!< GPIO_PORT PIN5: PORT25 Mask         */
+#define GPIO_PORT_PIN5_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN5: PORT26 Position     */
+#define GPIO_PORT_PIN5_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT26_Pos)                     /*!< GPIO_PORT PIN5: PORT26 Mask         */
+#define GPIO_PORT_PIN5_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN5: PORT27 Position     */
+#define GPIO_PORT_PIN5_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT27_Pos)                     /*!< GPIO_PORT PIN5: PORT27 Mask         */
+#define GPIO_PORT_PIN5_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN5: PORT28 Position     */
+#define GPIO_PORT_PIN5_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT28_Pos)                     /*!< GPIO_PORT PIN5: PORT28 Mask         */
+#define GPIO_PORT_PIN5_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN5: PORT29 Position     */
+#define GPIO_PORT_PIN5_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT29_Pos)                     /*!< GPIO_PORT PIN5: PORT29 Mask         */
+#define GPIO_PORT_PIN5_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN5: PORT30 Position     */
+#define GPIO_PORT_PIN5_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT30_Pos)                     /*!< GPIO_PORT PIN5: PORT30 Mask         */
+#define GPIO_PORT_PIN5_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN5: PORT31 Position     */
+#define GPIO_PORT_PIN5_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT31_Pos)                     /*!< GPIO_PORT PIN5: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN6  -----------------------------------------
+#define GPIO_PORT_PIN6_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN6: PORT0 Position      */
+#define GPIO_PORT_PIN6_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT0_Pos)                      /*!< GPIO_PORT PIN6: PORT0 Mask          */
+#define GPIO_PORT_PIN6_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN6: PORT1 Position      */
+#define GPIO_PORT_PIN6_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT1_Pos)                      /*!< GPIO_PORT PIN6: PORT1 Mask          */
+#define GPIO_PORT_PIN6_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN6: PORT2 Position      */
+#define GPIO_PORT_PIN6_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT2_Pos)                      /*!< GPIO_PORT PIN6: PORT2 Mask          */
+#define GPIO_PORT_PIN6_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN6: PORT3 Position      */
+#define GPIO_PORT_PIN6_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT3_Pos)                      /*!< GPIO_PORT PIN6: PORT3 Mask          */
+#define GPIO_PORT_PIN6_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN6: PORT4 Position      */
+#define GPIO_PORT_PIN6_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT4_Pos)                      /*!< GPIO_PORT PIN6: PORT4 Mask          */
+#define GPIO_PORT_PIN6_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN6: PORT5 Position      */
+#define GPIO_PORT_PIN6_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT5_Pos)                      /*!< GPIO_PORT PIN6: PORT5 Mask          */
+#define GPIO_PORT_PIN6_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN6: PORT6 Position      */
+#define GPIO_PORT_PIN6_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT6_Pos)                      /*!< GPIO_PORT PIN6: PORT6 Mask          */
+#define GPIO_PORT_PIN6_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN6: PORT7 Position      */
+#define GPIO_PORT_PIN6_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT7_Pos)                      /*!< GPIO_PORT PIN6: PORT7 Mask          */
+#define GPIO_PORT_PIN6_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN6: PORT8 Position      */
+#define GPIO_PORT_PIN6_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT8_Pos)                      /*!< GPIO_PORT PIN6: PORT8 Mask          */
+#define GPIO_PORT_PIN6_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN6: PORT9 Position      */
+#define GPIO_PORT_PIN6_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT9_Pos)                      /*!< GPIO_PORT PIN6: PORT9 Mask          */
+#define GPIO_PORT_PIN6_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN6: PORT10 Position     */
+#define GPIO_PORT_PIN6_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT10_Pos)                     /*!< GPIO_PORT PIN6: PORT10 Mask         */
+#define GPIO_PORT_PIN6_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN6: PORT11 Position     */
+#define GPIO_PORT_PIN6_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT11_Pos)                     /*!< GPIO_PORT PIN6: PORT11 Mask         */
+#define GPIO_PORT_PIN6_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN6: PORT12 Position     */
+#define GPIO_PORT_PIN6_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT12_Pos)                     /*!< GPIO_PORT PIN6: PORT12 Mask         */
+#define GPIO_PORT_PIN6_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN6: PORT13 Position     */
+#define GPIO_PORT_PIN6_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT13_Pos)                     /*!< GPIO_PORT PIN6: PORT13 Mask         */
+#define GPIO_PORT_PIN6_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN6: PORT14 Position     */
+#define GPIO_PORT_PIN6_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT14_Pos)                     /*!< GPIO_PORT PIN6: PORT14 Mask         */
+#define GPIO_PORT_PIN6_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN6: PORT15 Position     */
+#define GPIO_PORT_PIN6_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT15_Pos)                     /*!< GPIO_PORT PIN6: PORT15 Mask         */
+#define GPIO_PORT_PIN6_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN6: PORT16 Position     */
+#define GPIO_PORT_PIN6_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT16_Pos)                     /*!< GPIO_PORT PIN6: PORT16 Mask         */
+#define GPIO_PORT_PIN6_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN6: PORT17 Position     */
+#define GPIO_PORT_PIN6_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT17_Pos)                     /*!< GPIO_PORT PIN6: PORT17 Mask         */
+#define GPIO_PORT_PIN6_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN6: PORT18 Position     */
+#define GPIO_PORT_PIN6_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT18_Pos)                     /*!< GPIO_PORT PIN6: PORT18 Mask         */
+#define GPIO_PORT_PIN6_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN6: PORT19 Position     */
+#define GPIO_PORT_PIN6_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT19_Pos)                     /*!< GPIO_PORT PIN6: PORT19 Mask         */
+#define GPIO_PORT_PIN6_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN6: PORT20 Position     */
+#define GPIO_PORT_PIN6_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT20_Pos)                     /*!< GPIO_PORT PIN6: PORT20 Mask         */
+#define GPIO_PORT_PIN6_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN6: PORT21 Position     */
+#define GPIO_PORT_PIN6_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT21_Pos)                     /*!< GPIO_PORT PIN6: PORT21 Mask         */
+#define GPIO_PORT_PIN6_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN6: PORT22 Position     */
+#define GPIO_PORT_PIN6_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT22_Pos)                     /*!< GPIO_PORT PIN6: PORT22 Mask         */
+#define GPIO_PORT_PIN6_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN6: PORT23 Position     */
+#define GPIO_PORT_PIN6_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT23_Pos)                     /*!< GPIO_PORT PIN6: PORT23 Mask         */
+#define GPIO_PORT_PIN6_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN6: PORT24 Position     */
+#define GPIO_PORT_PIN6_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT24_Pos)                     /*!< GPIO_PORT PIN6: PORT24 Mask         */
+#define GPIO_PORT_PIN6_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN6: PORT25 Position     */
+#define GPIO_PORT_PIN6_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT25_Pos)                     /*!< GPIO_PORT PIN6: PORT25 Mask         */
+#define GPIO_PORT_PIN6_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN6: PORT26 Position     */
+#define GPIO_PORT_PIN6_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT26_Pos)                     /*!< GPIO_PORT PIN6: PORT26 Mask         */
+#define GPIO_PORT_PIN6_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN6: PORT27 Position     */
+#define GPIO_PORT_PIN6_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT27_Pos)                     /*!< GPIO_PORT PIN6: PORT27 Mask         */
+#define GPIO_PORT_PIN6_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN6: PORT28 Position     */
+#define GPIO_PORT_PIN6_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT28_Pos)                     /*!< GPIO_PORT PIN6: PORT28 Mask         */
+#define GPIO_PORT_PIN6_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN6: PORT29 Position     */
+#define GPIO_PORT_PIN6_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT29_Pos)                     /*!< GPIO_PORT PIN6: PORT29 Mask         */
+#define GPIO_PORT_PIN6_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN6: PORT30 Position     */
+#define GPIO_PORT_PIN6_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT30_Pos)                     /*!< GPIO_PORT PIN6: PORT30 Mask         */
+#define GPIO_PORT_PIN6_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN6: PORT31 Position     */
+#define GPIO_PORT_PIN6_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT31_Pos)                     /*!< GPIO_PORT PIN6: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_PIN7  -----------------------------------------
+#define GPIO_PORT_PIN7_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN7: PORT0 Position      */
+#define GPIO_PORT_PIN7_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT0_Pos)                      /*!< GPIO_PORT PIN7: PORT0 Mask          */
+#define GPIO_PORT_PIN7_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN7: PORT1 Position      */
+#define GPIO_PORT_PIN7_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT1_Pos)                      /*!< GPIO_PORT PIN7: PORT1 Mask          */
+#define GPIO_PORT_PIN7_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN7: PORT2 Position      */
+#define GPIO_PORT_PIN7_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT2_Pos)                      /*!< GPIO_PORT PIN7: PORT2 Mask          */
+#define GPIO_PORT_PIN7_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN7: PORT3 Position      */
+#define GPIO_PORT_PIN7_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT3_Pos)                      /*!< GPIO_PORT PIN7: PORT3 Mask          */
+#define GPIO_PORT_PIN7_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN7: PORT4 Position      */
+#define GPIO_PORT_PIN7_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT4_Pos)                      /*!< GPIO_PORT PIN7: PORT4 Mask          */
+#define GPIO_PORT_PIN7_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN7: PORT5 Position      */
+#define GPIO_PORT_PIN7_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT5_Pos)                      /*!< GPIO_PORT PIN7: PORT5 Mask          */
+#define GPIO_PORT_PIN7_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN7: PORT6 Position      */
+#define GPIO_PORT_PIN7_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT6_Pos)                      /*!< GPIO_PORT PIN7: PORT6 Mask          */
+#define GPIO_PORT_PIN7_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN7: PORT7 Position      */
+#define GPIO_PORT_PIN7_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT7_Pos)                      /*!< GPIO_PORT PIN7: PORT7 Mask          */
+#define GPIO_PORT_PIN7_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN7: PORT8 Position      */
+#define GPIO_PORT_PIN7_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT8_Pos)                      /*!< GPIO_PORT PIN7: PORT8 Mask          */
+#define GPIO_PORT_PIN7_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN7: PORT9 Position      */
+#define GPIO_PORT_PIN7_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT9_Pos)                      /*!< GPIO_PORT PIN7: PORT9 Mask          */
+#define GPIO_PORT_PIN7_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN7: PORT10 Position     */
+#define GPIO_PORT_PIN7_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT10_Pos)                     /*!< GPIO_PORT PIN7: PORT10 Mask         */
+#define GPIO_PORT_PIN7_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN7: PORT11 Position     */
+#define GPIO_PORT_PIN7_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT11_Pos)                     /*!< GPIO_PORT PIN7: PORT11 Mask         */
+#define GPIO_PORT_PIN7_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN7: PORT12 Position     */
+#define GPIO_PORT_PIN7_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT12_Pos)                     /*!< GPIO_PORT PIN7: PORT12 Mask         */
+#define GPIO_PORT_PIN7_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN7: PORT13 Position     */
+#define GPIO_PORT_PIN7_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT13_Pos)                     /*!< GPIO_PORT PIN7: PORT13 Mask         */
+#define GPIO_PORT_PIN7_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN7: PORT14 Position     */
+#define GPIO_PORT_PIN7_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT14_Pos)                     /*!< GPIO_PORT PIN7: PORT14 Mask         */
+#define GPIO_PORT_PIN7_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN7: PORT15 Position     */
+#define GPIO_PORT_PIN7_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT15_Pos)                     /*!< GPIO_PORT PIN7: PORT15 Mask         */
+#define GPIO_PORT_PIN7_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN7: PORT16 Position     */
+#define GPIO_PORT_PIN7_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT16_Pos)                     /*!< GPIO_PORT PIN7: PORT16 Mask         */
+#define GPIO_PORT_PIN7_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN7: PORT17 Position     */
+#define GPIO_PORT_PIN7_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT17_Pos)                     /*!< GPIO_PORT PIN7: PORT17 Mask         */
+#define GPIO_PORT_PIN7_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN7: PORT18 Position     */
+#define GPIO_PORT_PIN7_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT18_Pos)                     /*!< GPIO_PORT PIN7: PORT18 Mask         */
+#define GPIO_PORT_PIN7_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN7: PORT19 Position     */
+#define GPIO_PORT_PIN7_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT19_Pos)                     /*!< GPIO_PORT PIN7: PORT19 Mask         */
+#define GPIO_PORT_PIN7_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN7: PORT20 Position     */
+#define GPIO_PORT_PIN7_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT20_Pos)                     /*!< GPIO_PORT PIN7: PORT20 Mask         */
+#define GPIO_PORT_PIN7_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN7: PORT21 Position     */
+#define GPIO_PORT_PIN7_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT21_Pos)                     /*!< GPIO_PORT PIN7: PORT21 Mask         */
+#define GPIO_PORT_PIN7_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN7: PORT22 Position     */
+#define GPIO_PORT_PIN7_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT22_Pos)                     /*!< GPIO_PORT PIN7: PORT22 Mask         */
+#define GPIO_PORT_PIN7_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN7: PORT23 Position     */
+#define GPIO_PORT_PIN7_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT23_Pos)                     /*!< GPIO_PORT PIN7: PORT23 Mask         */
+#define GPIO_PORT_PIN7_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN7: PORT24 Position     */
+#define GPIO_PORT_PIN7_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT24_Pos)                     /*!< GPIO_PORT PIN7: PORT24 Mask         */
+#define GPIO_PORT_PIN7_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN7: PORT25 Position     */
+#define GPIO_PORT_PIN7_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT25_Pos)                     /*!< GPIO_PORT PIN7: PORT25 Mask         */
+#define GPIO_PORT_PIN7_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN7: PORT26 Position     */
+#define GPIO_PORT_PIN7_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT26_Pos)                     /*!< GPIO_PORT PIN7: PORT26 Mask         */
+#define GPIO_PORT_PIN7_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN7: PORT27 Position     */
+#define GPIO_PORT_PIN7_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT27_Pos)                     /*!< GPIO_PORT PIN7: PORT27 Mask         */
+#define GPIO_PORT_PIN7_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN7: PORT28 Position     */
+#define GPIO_PORT_PIN7_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT28_Pos)                     /*!< GPIO_PORT PIN7: PORT28 Mask         */
+#define GPIO_PORT_PIN7_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN7: PORT29 Position     */
+#define GPIO_PORT_PIN7_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT29_Pos)                     /*!< GPIO_PORT PIN7: PORT29 Mask         */
+#define GPIO_PORT_PIN7_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN7: PORT30 Position     */
+#define GPIO_PORT_PIN7_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT30_Pos)                     /*!< GPIO_PORT PIN7: PORT30 Mask         */
+#define GPIO_PORT_PIN7_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN7: PORT31 Position     */
+#define GPIO_PORT_PIN7_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT31_Pos)                     /*!< GPIO_PORT PIN7: PORT31 Mask         */
+
+// -------------------------------------  GPIO_PORT_MPIN0  ----------------------------------------
+#define GPIO_PORT_MPIN0_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN0: MPORTP0 Position   */
+#define GPIO_PORT_MPIN0_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN0: MPORTP1 Position   */
+#define GPIO_PORT_MPIN0_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN0: MPORTP2 Position   */
+#define GPIO_PORT_MPIN0_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN0: MPORTP3 Position   */
+#define GPIO_PORT_MPIN0_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN0: MPORTP4 Position   */
+#define GPIO_PORT_MPIN0_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN0: MPORTP5 Position   */
+#define GPIO_PORT_MPIN0_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN0: MPORTP6 Position   */
+#define GPIO_PORT_MPIN0_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN0: MPORTP7 Position   */
+#define GPIO_PORT_MPIN0_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN0: MPORTP8 Position   */
+#define GPIO_PORT_MPIN0_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN0: MPORTP9 Position   */
+#define GPIO_PORT_MPIN0_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN0_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN0: MPORTP10 Position  */
+#define GPIO_PORT_MPIN0_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN0: MPORTP11 Position  */
+#define GPIO_PORT_MPIN0_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN0: MPORTP12 Position  */
+#define GPIO_PORT_MPIN0_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN0: MPORTP13 Position  */
+#define GPIO_PORT_MPIN0_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN0: MPORTP14 Position  */
+#define GPIO_PORT_MPIN0_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN0: MPORTP15 Position  */
+#define GPIO_PORT_MPIN0_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN0: MPORTP16 Position  */
+#define GPIO_PORT_MPIN0_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN0: MPORTP17 Position  */
+#define GPIO_PORT_MPIN0_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN0: MPORTP18 Position  */
+#define GPIO_PORT_MPIN0_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN0: MPORTP19 Position  */
+#define GPIO_PORT_MPIN0_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN0: MPORTP20 Position  */
+#define GPIO_PORT_MPIN0_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN0: MPORTP21 Position  */
+#define GPIO_PORT_MPIN0_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN0: MPORTP22 Position  */
+#define GPIO_PORT_MPIN0_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN0: MPORTP23 Position  */
+#define GPIO_PORT_MPIN0_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN0: MPORTP24 Position  */
+#define GPIO_PORT_MPIN0_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN0: MPORTP25 Position  */
+#define GPIO_PORT_MPIN0_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN0: MPORTP26 Position  */
+#define GPIO_PORT_MPIN0_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN0: MPORTP27 Position  */
+#define GPIO_PORT_MPIN0_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN0: MPORTP28 Position  */
+#define GPIO_PORT_MPIN0_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN0: MPORTP29 Position  */
+#define GPIO_PORT_MPIN0_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN0: MPORTP30 Position  */
+#define GPIO_PORT_MPIN0_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN0_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN0: MPORTP31 Position  */
+#define GPIO_PORT_MPIN0_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN1  ----------------------------------------
+#define GPIO_PORT_MPIN1_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN1: MPORTP0 Position   */
+#define GPIO_PORT_MPIN1_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN1: MPORTP1 Position   */
+#define GPIO_PORT_MPIN1_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN1: MPORTP2 Position   */
+#define GPIO_PORT_MPIN1_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN1: MPORTP3 Position   */
+#define GPIO_PORT_MPIN1_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN1: MPORTP4 Position   */
+#define GPIO_PORT_MPIN1_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN1: MPORTP5 Position   */
+#define GPIO_PORT_MPIN1_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN1: MPORTP6 Position   */
+#define GPIO_PORT_MPIN1_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN1: MPORTP7 Position   */
+#define GPIO_PORT_MPIN1_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN1: MPORTP8 Position   */
+#define GPIO_PORT_MPIN1_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN1: MPORTP9 Position   */
+#define GPIO_PORT_MPIN1_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN1_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN1: MPORTP10 Position  */
+#define GPIO_PORT_MPIN1_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN1: MPORTP11 Position  */
+#define GPIO_PORT_MPIN1_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN1: MPORTP12 Position  */
+#define GPIO_PORT_MPIN1_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN1: MPORTP13 Position  */
+#define GPIO_PORT_MPIN1_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN1: MPORTP14 Position  */
+#define GPIO_PORT_MPIN1_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN1: MPORTP15 Position  */
+#define GPIO_PORT_MPIN1_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN1: MPORTP16 Position  */
+#define GPIO_PORT_MPIN1_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN1: MPORTP17 Position  */
+#define GPIO_PORT_MPIN1_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN1: MPORTP18 Position  */
+#define GPIO_PORT_MPIN1_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN1: MPORTP19 Position  */
+#define GPIO_PORT_MPIN1_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN1: MPORTP20 Position  */
+#define GPIO_PORT_MPIN1_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN1: MPORTP21 Position  */
+#define GPIO_PORT_MPIN1_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN1: MPORTP22 Position  */
+#define GPIO_PORT_MPIN1_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN1: MPORTP23 Position  */
+#define GPIO_PORT_MPIN1_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN1: MPORTP24 Position  */
+#define GPIO_PORT_MPIN1_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN1: MPORTP25 Position  */
+#define GPIO_PORT_MPIN1_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN1: MPORTP26 Position  */
+#define GPIO_PORT_MPIN1_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN1: MPORTP27 Position  */
+#define GPIO_PORT_MPIN1_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN1: MPORTP28 Position  */
+#define GPIO_PORT_MPIN1_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN1: MPORTP29 Position  */
+#define GPIO_PORT_MPIN1_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN1: MPORTP30 Position  */
+#define GPIO_PORT_MPIN1_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN1_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN1: MPORTP31 Position  */
+#define GPIO_PORT_MPIN1_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN2  ----------------------------------------
+#define GPIO_PORT_MPIN2_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN2: MPORTP0 Position   */
+#define GPIO_PORT_MPIN2_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN2: MPORTP1 Position   */
+#define GPIO_PORT_MPIN2_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN2: MPORTP2 Position   */
+#define GPIO_PORT_MPIN2_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN2: MPORTP3 Position   */
+#define GPIO_PORT_MPIN2_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN2: MPORTP4 Position   */
+#define GPIO_PORT_MPIN2_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN2: MPORTP5 Position   */
+#define GPIO_PORT_MPIN2_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN2: MPORTP6 Position   */
+#define GPIO_PORT_MPIN2_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN2: MPORTP7 Position   */
+#define GPIO_PORT_MPIN2_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN2: MPORTP8 Position   */
+#define GPIO_PORT_MPIN2_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN2: MPORTP9 Position   */
+#define GPIO_PORT_MPIN2_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN2_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN2: MPORTP10 Position  */
+#define GPIO_PORT_MPIN2_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN2: MPORTP11 Position  */
+#define GPIO_PORT_MPIN2_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN2: MPORTP12 Position  */
+#define GPIO_PORT_MPIN2_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN2: MPORTP13 Position  */
+#define GPIO_PORT_MPIN2_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN2: MPORTP14 Position  */
+#define GPIO_PORT_MPIN2_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN2: MPORTP15 Position  */
+#define GPIO_PORT_MPIN2_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN2: MPORTP16 Position  */
+#define GPIO_PORT_MPIN2_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN2: MPORTP17 Position  */
+#define GPIO_PORT_MPIN2_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN2: MPORTP18 Position  */
+#define GPIO_PORT_MPIN2_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN2: MPORTP19 Position  */
+#define GPIO_PORT_MPIN2_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN2: MPORTP20 Position  */
+#define GPIO_PORT_MPIN2_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN2: MPORTP21 Position  */
+#define GPIO_PORT_MPIN2_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN2: MPORTP22 Position  */
+#define GPIO_PORT_MPIN2_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN2: MPORTP23 Position  */
+#define GPIO_PORT_MPIN2_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN2: MPORTP24 Position  */
+#define GPIO_PORT_MPIN2_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN2: MPORTP25 Position  */
+#define GPIO_PORT_MPIN2_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN2: MPORTP26 Position  */
+#define GPIO_PORT_MPIN2_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN2: MPORTP27 Position  */
+#define GPIO_PORT_MPIN2_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN2: MPORTP28 Position  */
+#define GPIO_PORT_MPIN2_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN2: MPORTP29 Position  */
+#define GPIO_PORT_MPIN2_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN2: MPORTP30 Position  */
+#define GPIO_PORT_MPIN2_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN2_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN2: MPORTP31 Position  */
+#define GPIO_PORT_MPIN2_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN3  ----------------------------------------
+#define GPIO_PORT_MPIN3_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN3: MPORTP0 Position   */
+#define GPIO_PORT_MPIN3_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN3: MPORTP1 Position   */
+#define GPIO_PORT_MPIN3_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN3: MPORTP2 Position   */
+#define GPIO_PORT_MPIN3_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN3: MPORTP3 Position   */
+#define GPIO_PORT_MPIN3_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN3: MPORTP4 Position   */
+#define GPIO_PORT_MPIN3_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN3: MPORTP5 Position   */
+#define GPIO_PORT_MPIN3_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN3: MPORTP6 Position   */
+#define GPIO_PORT_MPIN3_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN3: MPORTP7 Position   */
+#define GPIO_PORT_MPIN3_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN3: MPORTP8 Position   */
+#define GPIO_PORT_MPIN3_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN3: MPORTP9 Position   */
+#define GPIO_PORT_MPIN3_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN3_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN3: MPORTP10 Position  */
+#define GPIO_PORT_MPIN3_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN3: MPORTP11 Position  */
+#define GPIO_PORT_MPIN3_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN3: MPORTP12 Position  */
+#define GPIO_PORT_MPIN3_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN3: MPORTP13 Position  */
+#define GPIO_PORT_MPIN3_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN3: MPORTP14 Position  */
+#define GPIO_PORT_MPIN3_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN3: MPORTP15 Position  */
+#define GPIO_PORT_MPIN3_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN3: MPORTP16 Position  */
+#define GPIO_PORT_MPIN3_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN3: MPORTP17 Position  */
+#define GPIO_PORT_MPIN3_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN3: MPORTP18 Position  */
+#define GPIO_PORT_MPIN3_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN3: MPORTP19 Position  */
+#define GPIO_PORT_MPIN3_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN3: MPORTP20 Position  */
+#define GPIO_PORT_MPIN3_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN3: MPORTP21 Position  */
+#define GPIO_PORT_MPIN3_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN3: MPORTP22 Position  */
+#define GPIO_PORT_MPIN3_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN3: MPORTP23 Position  */
+#define GPIO_PORT_MPIN3_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN3: MPORTP24 Position  */
+#define GPIO_PORT_MPIN3_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN3: MPORTP25 Position  */
+#define GPIO_PORT_MPIN3_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN3: MPORTP26 Position  */
+#define GPIO_PORT_MPIN3_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN3: MPORTP27 Position  */
+#define GPIO_PORT_MPIN3_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN3: MPORTP28 Position  */
+#define GPIO_PORT_MPIN3_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN3: MPORTP29 Position  */
+#define GPIO_PORT_MPIN3_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN3: MPORTP30 Position  */
+#define GPIO_PORT_MPIN3_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN3_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN3: MPORTP31 Position  */
+#define GPIO_PORT_MPIN3_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN4  ----------------------------------------
+#define GPIO_PORT_MPIN4_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN4: MPORTP0 Position   */
+#define GPIO_PORT_MPIN4_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN4: MPORTP1 Position   */
+#define GPIO_PORT_MPIN4_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN4: MPORTP2 Position   */
+#define GPIO_PORT_MPIN4_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN4: MPORTP3 Position   */
+#define GPIO_PORT_MPIN4_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN4: MPORTP4 Position   */
+#define GPIO_PORT_MPIN4_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN4: MPORTP5 Position   */
+#define GPIO_PORT_MPIN4_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN4: MPORTP6 Position   */
+#define GPIO_PORT_MPIN4_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN4: MPORTP7 Position   */
+#define GPIO_PORT_MPIN4_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN4: MPORTP8 Position   */
+#define GPIO_PORT_MPIN4_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN4: MPORTP9 Position   */
+#define GPIO_PORT_MPIN4_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN4_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN4: MPORTP10 Position  */
+#define GPIO_PORT_MPIN4_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN4: MPORTP11 Position  */
+#define GPIO_PORT_MPIN4_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN4: MPORTP12 Position  */
+#define GPIO_PORT_MPIN4_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN4: MPORTP13 Position  */
+#define GPIO_PORT_MPIN4_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN4: MPORTP14 Position  */
+#define GPIO_PORT_MPIN4_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN4: MPORTP15 Position  */
+#define GPIO_PORT_MPIN4_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN4: MPORTP16 Position  */
+#define GPIO_PORT_MPIN4_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN4: MPORTP17 Position  */
+#define GPIO_PORT_MPIN4_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN4: MPORTP18 Position  */
+#define GPIO_PORT_MPIN4_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN4: MPORTP19 Position  */
+#define GPIO_PORT_MPIN4_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN4: MPORTP20 Position  */
+#define GPIO_PORT_MPIN4_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN4: MPORTP21 Position  */
+#define GPIO_PORT_MPIN4_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN4: MPORTP22 Position  */
+#define GPIO_PORT_MPIN4_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN4: MPORTP23 Position  */
+#define GPIO_PORT_MPIN4_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN4: MPORTP24 Position  */
+#define GPIO_PORT_MPIN4_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN4: MPORTP25 Position  */
+#define GPIO_PORT_MPIN4_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN4: MPORTP26 Position  */
+#define GPIO_PORT_MPIN4_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN4: MPORTP27 Position  */
+#define GPIO_PORT_MPIN4_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN4: MPORTP28 Position  */
+#define GPIO_PORT_MPIN4_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN4: MPORTP29 Position  */
+#define GPIO_PORT_MPIN4_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN4: MPORTP30 Position  */
+#define GPIO_PORT_MPIN4_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN4_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN4: MPORTP31 Position  */
+#define GPIO_PORT_MPIN4_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN5  ----------------------------------------
+#define GPIO_PORT_MPIN5_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN5: MPORTP0 Position   */
+#define GPIO_PORT_MPIN5_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN5: MPORTP1 Position   */
+#define GPIO_PORT_MPIN5_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN5: MPORTP2 Position   */
+#define GPIO_PORT_MPIN5_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN5: MPORTP3 Position   */
+#define GPIO_PORT_MPIN5_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN5: MPORTP4 Position   */
+#define GPIO_PORT_MPIN5_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN5: MPORTP5 Position   */
+#define GPIO_PORT_MPIN5_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN5: MPORTP6 Position   */
+#define GPIO_PORT_MPIN5_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN5: MPORTP7 Position   */
+#define GPIO_PORT_MPIN5_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN5: MPORTP8 Position   */
+#define GPIO_PORT_MPIN5_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN5: MPORTP9 Position   */
+#define GPIO_PORT_MPIN5_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN5_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN5: MPORTP10 Position  */
+#define GPIO_PORT_MPIN5_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN5: MPORTP11 Position  */
+#define GPIO_PORT_MPIN5_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN5: MPORTP12 Position  */
+#define GPIO_PORT_MPIN5_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN5: MPORTP13 Position  */
+#define GPIO_PORT_MPIN5_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN5: MPORTP14 Position  */
+#define GPIO_PORT_MPIN5_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN5: MPORTP15 Position  */
+#define GPIO_PORT_MPIN5_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN5: MPORTP16 Position  */
+#define GPIO_PORT_MPIN5_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN5: MPORTP17 Position  */
+#define GPIO_PORT_MPIN5_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN5: MPORTP18 Position  */
+#define GPIO_PORT_MPIN5_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN5: MPORTP19 Position  */
+#define GPIO_PORT_MPIN5_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN5: MPORTP20 Position  */
+#define GPIO_PORT_MPIN5_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN5: MPORTP21 Position  */
+#define GPIO_PORT_MPIN5_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN5: MPORTP22 Position  */
+#define GPIO_PORT_MPIN5_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN5: MPORTP23 Position  */
+#define GPIO_PORT_MPIN5_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN5: MPORTP24 Position  */
+#define GPIO_PORT_MPIN5_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN5: MPORTP25 Position  */
+#define GPIO_PORT_MPIN5_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN5: MPORTP26 Position  */
+#define GPIO_PORT_MPIN5_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN5: MPORTP27 Position  */
+#define GPIO_PORT_MPIN5_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN5: MPORTP28 Position  */
+#define GPIO_PORT_MPIN5_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN5: MPORTP29 Position  */
+#define GPIO_PORT_MPIN5_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN5: MPORTP30 Position  */
+#define GPIO_PORT_MPIN5_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN5_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN5: MPORTP31 Position  */
+#define GPIO_PORT_MPIN5_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN6  ----------------------------------------
+#define GPIO_PORT_MPIN6_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN6: MPORTP0 Position   */
+#define GPIO_PORT_MPIN6_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN6: MPORTP1 Position   */
+#define GPIO_PORT_MPIN6_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN6: MPORTP2 Position   */
+#define GPIO_PORT_MPIN6_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN6: MPORTP3 Position   */
+#define GPIO_PORT_MPIN6_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN6: MPORTP4 Position   */
+#define GPIO_PORT_MPIN6_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN6: MPORTP5 Position   */
+#define GPIO_PORT_MPIN6_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN6: MPORTP6 Position   */
+#define GPIO_PORT_MPIN6_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN6: MPORTP7 Position   */
+#define GPIO_PORT_MPIN6_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN6: MPORTP8 Position   */
+#define GPIO_PORT_MPIN6_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN6: MPORTP9 Position   */
+#define GPIO_PORT_MPIN6_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN6_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN6: MPORTP10 Position  */
+#define GPIO_PORT_MPIN6_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN6: MPORTP11 Position  */
+#define GPIO_PORT_MPIN6_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN6: MPORTP12 Position  */
+#define GPIO_PORT_MPIN6_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN6: MPORTP13 Position  */
+#define GPIO_PORT_MPIN6_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN6: MPORTP14 Position  */
+#define GPIO_PORT_MPIN6_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN6: MPORTP15 Position  */
+#define GPIO_PORT_MPIN6_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN6: MPORTP16 Position  */
+#define GPIO_PORT_MPIN6_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN6: MPORTP17 Position  */
+#define GPIO_PORT_MPIN6_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN6: MPORTP18 Position  */
+#define GPIO_PORT_MPIN6_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN6: MPORTP19 Position  */
+#define GPIO_PORT_MPIN6_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN6: MPORTP20 Position  */
+#define GPIO_PORT_MPIN6_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN6: MPORTP21 Position  */
+#define GPIO_PORT_MPIN6_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN6: MPORTP22 Position  */
+#define GPIO_PORT_MPIN6_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN6: MPORTP23 Position  */
+#define GPIO_PORT_MPIN6_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN6: MPORTP24 Position  */
+#define GPIO_PORT_MPIN6_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN6: MPORTP25 Position  */
+#define GPIO_PORT_MPIN6_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN6: MPORTP26 Position  */
+#define GPIO_PORT_MPIN6_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN6: MPORTP27 Position  */
+#define GPIO_PORT_MPIN6_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN6: MPORTP28 Position  */
+#define GPIO_PORT_MPIN6_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN6: MPORTP29 Position  */
+#define GPIO_PORT_MPIN6_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN6: MPORTP30 Position  */
+#define GPIO_PORT_MPIN6_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN6_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN6: MPORTP31 Position  */
+#define GPIO_PORT_MPIN6_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_MPIN7  ----------------------------------------
+#define GPIO_PORT_MPIN7_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN7: MPORTP0 Position   */
+#define GPIO_PORT_MPIN7_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP0 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN7: MPORTP1 Position   */
+#define GPIO_PORT_MPIN7_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP1 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN7: MPORTP2 Position   */
+#define GPIO_PORT_MPIN7_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP2 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN7: MPORTP3 Position   */
+#define GPIO_PORT_MPIN7_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP3 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN7: MPORTP4 Position   */
+#define GPIO_PORT_MPIN7_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP4 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN7: MPORTP5 Position   */
+#define GPIO_PORT_MPIN7_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP5 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN7: MPORTP6 Position   */
+#define GPIO_PORT_MPIN7_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP6 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN7: MPORTP7 Position   */
+#define GPIO_PORT_MPIN7_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP7 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN7: MPORTP8 Position   */
+#define GPIO_PORT_MPIN7_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP8 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN7: MPORTP9 Position   */
+#define GPIO_PORT_MPIN7_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP9 Mask       */
+#define GPIO_PORT_MPIN7_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN7: MPORTP10 Position  */
+#define GPIO_PORT_MPIN7_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP10 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN7: MPORTP11 Position  */
+#define GPIO_PORT_MPIN7_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP11 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN7: MPORTP12 Position  */
+#define GPIO_PORT_MPIN7_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP12 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN7: MPORTP13 Position  */
+#define GPIO_PORT_MPIN7_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP13 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN7: MPORTP14 Position  */
+#define GPIO_PORT_MPIN7_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP14 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN7: MPORTP15 Position  */
+#define GPIO_PORT_MPIN7_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP15 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN7: MPORTP16 Position  */
+#define GPIO_PORT_MPIN7_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP16 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN7: MPORTP17 Position  */
+#define GPIO_PORT_MPIN7_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP17 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN7: MPORTP18 Position  */
+#define GPIO_PORT_MPIN7_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP18 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN7: MPORTP19 Position  */
+#define GPIO_PORT_MPIN7_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP19 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN7: MPORTP20 Position  */
+#define GPIO_PORT_MPIN7_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP20 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN7: MPORTP21 Position  */
+#define GPIO_PORT_MPIN7_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP21 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN7: MPORTP22 Position  */
+#define GPIO_PORT_MPIN7_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP22 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN7: MPORTP23 Position  */
+#define GPIO_PORT_MPIN7_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP23 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN7: MPORTP24 Position  */
+#define GPIO_PORT_MPIN7_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP24 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN7: MPORTP25 Position  */
+#define GPIO_PORT_MPIN7_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP25 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN7: MPORTP26 Position  */
+#define GPIO_PORT_MPIN7_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP26 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN7: MPORTP27 Position  */
+#define GPIO_PORT_MPIN7_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP27 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN7: MPORTP28 Position  */
+#define GPIO_PORT_MPIN7_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP28 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN7: MPORTP29 Position  */
+#define GPIO_PORT_MPIN7_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP29 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN7: MPORTP30 Position  */
+#define GPIO_PORT_MPIN7_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP30 Mask      */
+#define GPIO_PORT_MPIN7_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN7: MPORTP31 Position  */
+#define GPIO_PORT_MPIN7_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP31 Mask      */
+
+// -------------------------------------  GPIO_PORT_SET0  -----------------------------------------
+#define GPIO_PORT_SET0_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET0: SETP0 Position      */
+#define GPIO_PORT_SET0_SETP0_Msk                              (0x01UL << GPIO_PORT_SET0_SETP0_Pos)                      /*!< GPIO_PORT SET0: SETP0 Mask          */
+#define GPIO_PORT_SET0_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET0: SETP1 Position      */
+#define GPIO_PORT_SET0_SETP1_Msk                              (0x01UL << GPIO_PORT_SET0_SETP1_Pos)                      /*!< GPIO_PORT SET0: SETP1 Mask          */
+#define GPIO_PORT_SET0_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET0: SETP2 Position      */
+#define GPIO_PORT_SET0_SETP2_Msk                              (0x01UL << GPIO_PORT_SET0_SETP2_Pos)                      /*!< GPIO_PORT SET0: SETP2 Mask          */
+#define GPIO_PORT_SET0_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET0: SETP3 Position      */
+#define GPIO_PORT_SET0_SETP3_Msk                              (0x01UL << GPIO_PORT_SET0_SETP3_Pos)                      /*!< GPIO_PORT SET0: SETP3 Mask          */
+#define GPIO_PORT_SET0_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET0: SETP4 Position      */
+#define GPIO_PORT_SET0_SETP4_Msk                              (0x01UL << GPIO_PORT_SET0_SETP4_Pos)                      /*!< GPIO_PORT SET0: SETP4 Mask          */
+#define GPIO_PORT_SET0_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET0: SETP5 Position      */
+#define GPIO_PORT_SET0_SETP5_Msk                              (0x01UL << GPIO_PORT_SET0_SETP5_Pos)                      /*!< GPIO_PORT SET0: SETP5 Mask          */
+#define GPIO_PORT_SET0_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET0: SETP6 Position      */
+#define GPIO_PORT_SET0_SETP6_Msk                              (0x01UL << GPIO_PORT_SET0_SETP6_Pos)                      /*!< GPIO_PORT SET0: SETP6 Mask          */
+#define GPIO_PORT_SET0_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET0: SETP7 Position      */
+#define GPIO_PORT_SET0_SETP7_Msk                              (0x01UL << GPIO_PORT_SET0_SETP7_Pos)                      /*!< GPIO_PORT SET0: SETP7 Mask          */
+#define GPIO_PORT_SET0_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET0: SETP8 Position      */
+#define GPIO_PORT_SET0_SETP8_Msk                              (0x01UL << GPIO_PORT_SET0_SETP8_Pos)                      /*!< GPIO_PORT SET0: SETP8 Mask          */
+#define GPIO_PORT_SET0_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET0: SETP9 Position      */
+#define GPIO_PORT_SET0_SETP9_Msk                              (0x01UL << GPIO_PORT_SET0_SETP9_Pos)                      /*!< GPIO_PORT SET0: SETP9 Mask          */
+#define GPIO_PORT_SET0_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET0: SETP10 Position     */
+#define GPIO_PORT_SET0_SETP10_Msk                             (0x01UL << GPIO_PORT_SET0_SETP10_Pos)                     /*!< GPIO_PORT SET0: SETP10 Mask         */
+#define GPIO_PORT_SET0_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET0: SETP11 Position     */
+#define GPIO_PORT_SET0_SETP11_Msk                             (0x01UL << GPIO_PORT_SET0_SETP11_Pos)                     /*!< GPIO_PORT SET0: SETP11 Mask         */
+#define GPIO_PORT_SET0_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET0: SETP12 Position     */
+#define GPIO_PORT_SET0_SETP12_Msk                             (0x01UL << GPIO_PORT_SET0_SETP12_Pos)                     /*!< GPIO_PORT SET0: SETP12 Mask         */
+#define GPIO_PORT_SET0_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET0: SETP13 Position     */
+#define GPIO_PORT_SET0_SETP13_Msk                             (0x01UL << GPIO_PORT_SET0_SETP13_Pos)                     /*!< GPIO_PORT SET0: SETP13 Mask         */
+#define GPIO_PORT_SET0_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET0: SETP14 Position     */
+#define GPIO_PORT_SET0_SETP14_Msk                             (0x01UL << GPIO_PORT_SET0_SETP14_Pos)                     /*!< GPIO_PORT SET0: SETP14 Mask         */
+#define GPIO_PORT_SET0_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET0: SETP15 Position     */
+#define GPIO_PORT_SET0_SETP15_Msk                             (0x01UL << GPIO_PORT_SET0_SETP15_Pos)                     /*!< GPIO_PORT SET0: SETP15 Mask         */
+#define GPIO_PORT_SET0_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET0: SETP16 Position     */
+#define GPIO_PORT_SET0_SETP16_Msk                             (0x01UL << GPIO_PORT_SET0_SETP16_Pos)                     /*!< GPIO_PORT SET0: SETP16 Mask         */
+#define GPIO_PORT_SET0_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET0: SETP17 Position     */
+#define GPIO_PORT_SET0_SETP17_Msk                             (0x01UL << GPIO_PORT_SET0_SETP17_Pos)                     /*!< GPIO_PORT SET0: SETP17 Mask         */
+#define GPIO_PORT_SET0_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET0: SETP18 Position     */
+#define GPIO_PORT_SET0_SETP18_Msk                             (0x01UL << GPIO_PORT_SET0_SETP18_Pos)                     /*!< GPIO_PORT SET0: SETP18 Mask         */
+#define GPIO_PORT_SET0_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET0: SETP19 Position     */
+#define GPIO_PORT_SET0_SETP19_Msk                             (0x01UL << GPIO_PORT_SET0_SETP19_Pos)                     /*!< GPIO_PORT SET0: SETP19 Mask         */
+#define GPIO_PORT_SET0_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET0: SETP20 Position     */
+#define GPIO_PORT_SET0_SETP20_Msk                             (0x01UL << GPIO_PORT_SET0_SETP20_Pos)                     /*!< GPIO_PORT SET0: SETP20 Mask         */
+#define GPIO_PORT_SET0_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET0: SETP21 Position     */
+#define GPIO_PORT_SET0_SETP21_Msk                             (0x01UL << GPIO_PORT_SET0_SETP21_Pos)                     /*!< GPIO_PORT SET0: SETP21 Mask         */
+#define GPIO_PORT_SET0_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET0: SETP22 Position     */
+#define GPIO_PORT_SET0_SETP22_Msk                             (0x01UL << GPIO_PORT_SET0_SETP22_Pos)                     /*!< GPIO_PORT SET0: SETP22 Mask         */
+#define GPIO_PORT_SET0_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET0: SETP23 Position     */
+#define GPIO_PORT_SET0_SETP23_Msk                             (0x01UL << GPIO_PORT_SET0_SETP23_Pos)                     /*!< GPIO_PORT SET0: SETP23 Mask         */
+#define GPIO_PORT_SET0_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET0: SETP24 Position     */
+#define GPIO_PORT_SET0_SETP24_Msk                             (0x01UL << GPIO_PORT_SET0_SETP24_Pos)                     /*!< GPIO_PORT SET0: SETP24 Mask         */
+#define GPIO_PORT_SET0_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET0: SETP25 Position     */
+#define GPIO_PORT_SET0_SETP25_Msk                             (0x01UL << GPIO_PORT_SET0_SETP25_Pos)                     /*!< GPIO_PORT SET0: SETP25 Mask         */
+#define GPIO_PORT_SET0_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET0: SETP26 Position     */
+#define GPIO_PORT_SET0_SETP26_Msk                             (0x01UL << GPIO_PORT_SET0_SETP26_Pos)                     /*!< GPIO_PORT SET0: SETP26 Mask         */
+#define GPIO_PORT_SET0_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET0: SETP27 Position     */
+#define GPIO_PORT_SET0_SETP27_Msk                             (0x01UL << GPIO_PORT_SET0_SETP27_Pos)                     /*!< GPIO_PORT SET0: SETP27 Mask         */
+#define GPIO_PORT_SET0_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET0: SETP28 Position     */
+#define GPIO_PORT_SET0_SETP28_Msk                             (0x01UL << GPIO_PORT_SET0_SETP28_Pos)                     /*!< GPIO_PORT SET0: SETP28 Mask         */
+#define GPIO_PORT_SET0_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET0: SETP29 Position     */
+#define GPIO_PORT_SET0_SETP29_Msk                             (0x01UL << GPIO_PORT_SET0_SETP29_Pos)                     /*!< GPIO_PORT SET0: SETP29 Mask         */
+#define GPIO_PORT_SET0_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET0: SETP30 Position     */
+#define GPIO_PORT_SET0_SETP30_Msk                             (0x01UL << GPIO_PORT_SET0_SETP30_Pos)                     /*!< GPIO_PORT SET0: SETP30 Mask         */
+#define GPIO_PORT_SET0_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET0: SETP31 Position     */
+#define GPIO_PORT_SET0_SETP31_Msk                             (0x01UL << GPIO_PORT_SET0_SETP31_Pos)                     /*!< GPIO_PORT SET0: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET1  -----------------------------------------
+#define GPIO_PORT_SET1_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET1: SETP0 Position      */
+#define GPIO_PORT_SET1_SETP0_Msk                              (0x01UL << GPIO_PORT_SET1_SETP0_Pos)                      /*!< GPIO_PORT SET1: SETP0 Mask          */
+#define GPIO_PORT_SET1_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET1: SETP1 Position      */
+#define GPIO_PORT_SET1_SETP1_Msk                              (0x01UL << GPIO_PORT_SET1_SETP1_Pos)                      /*!< GPIO_PORT SET1: SETP1 Mask          */
+#define GPIO_PORT_SET1_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET1: SETP2 Position      */
+#define GPIO_PORT_SET1_SETP2_Msk                              (0x01UL << GPIO_PORT_SET1_SETP2_Pos)                      /*!< GPIO_PORT SET1: SETP2 Mask          */
+#define GPIO_PORT_SET1_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET1: SETP3 Position      */
+#define GPIO_PORT_SET1_SETP3_Msk                              (0x01UL << GPIO_PORT_SET1_SETP3_Pos)                      /*!< GPIO_PORT SET1: SETP3 Mask          */
+#define GPIO_PORT_SET1_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET1: SETP4 Position      */
+#define GPIO_PORT_SET1_SETP4_Msk                              (0x01UL << GPIO_PORT_SET1_SETP4_Pos)                      /*!< GPIO_PORT SET1: SETP4 Mask          */
+#define GPIO_PORT_SET1_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET1: SETP5 Position      */
+#define GPIO_PORT_SET1_SETP5_Msk                              (0x01UL << GPIO_PORT_SET1_SETP5_Pos)                      /*!< GPIO_PORT SET1: SETP5 Mask          */
+#define GPIO_PORT_SET1_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET1: SETP6 Position      */
+#define GPIO_PORT_SET1_SETP6_Msk                              (0x01UL << GPIO_PORT_SET1_SETP6_Pos)                      /*!< GPIO_PORT SET1: SETP6 Mask          */
+#define GPIO_PORT_SET1_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET1: SETP7 Position      */
+#define GPIO_PORT_SET1_SETP7_Msk                              (0x01UL << GPIO_PORT_SET1_SETP7_Pos)                      /*!< GPIO_PORT SET1: SETP7 Mask          */
+#define GPIO_PORT_SET1_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET1: SETP8 Position      */
+#define GPIO_PORT_SET1_SETP8_Msk                              (0x01UL << GPIO_PORT_SET1_SETP8_Pos)                      /*!< GPIO_PORT SET1: SETP8 Mask          */
+#define GPIO_PORT_SET1_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET1: SETP9 Position      */
+#define GPIO_PORT_SET1_SETP9_Msk                              (0x01UL << GPIO_PORT_SET1_SETP9_Pos)                      /*!< GPIO_PORT SET1: SETP9 Mask          */
+#define GPIO_PORT_SET1_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET1: SETP10 Position     */
+#define GPIO_PORT_SET1_SETP10_Msk                             (0x01UL << GPIO_PORT_SET1_SETP10_Pos)                     /*!< GPIO_PORT SET1: SETP10 Mask         */
+#define GPIO_PORT_SET1_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET1: SETP11 Position     */
+#define GPIO_PORT_SET1_SETP11_Msk                             (0x01UL << GPIO_PORT_SET1_SETP11_Pos)                     /*!< GPIO_PORT SET1: SETP11 Mask         */
+#define GPIO_PORT_SET1_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET1: SETP12 Position     */
+#define GPIO_PORT_SET1_SETP12_Msk                             (0x01UL << GPIO_PORT_SET1_SETP12_Pos)                     /*!< GPIO_PORT SET1: SETP12 Mask         */
+#define GPIO_PORT_SET1_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET1: SETP13 Position     */
+#define GPIO_PORT_SET1_SETP13_Msk                             (0x01UL << GPIO_PORT_SET1_SETP13_Pos)                     /*!< GPIO_PORT SET1: SETP13 Mask         */
+#define GPIO_PORT_SET1_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET1: SETP14 Position     */
+#define GPIO_PORT_SET1_SETP14_Msk                             (0x01UL << GPIO_PORT_SET1_SETP14_Pos)                     /*!< GPIO_PORT SET1: SETP14 Mask         */
+#define GPIO_PORT_SET1_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET1: SETP15 Position     */
+#define GPIO_PORT_SET1_SETP15_Msk                             (0x01UL << GPIO_PORT_SET1_SETP15_Pos)                     /*!< GPIO_PORT SET1: SETP15 Mask         */
+#define GPIO_PORT_SET1_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET1: SETP16 Position     */
+#define GPIO_PORT_SET1_SETP16_Msk                             (0x01UL << GPIO_PORT_SET1_SETP16_Pos)                     /*!< GPIO_PORT SET1: SETP16 Mask         */
+#define GPIO_PORT_SET1_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET1: SETP17 Position     */
+#define GPIO_PORT_SET1_SETP17_Msk                             (0x01UL << GPIO_PORT_SET1_SETP17_Pos)                     /*!< GPIO_PORT SET1: SETP17 Mask         */
+#define GPIO_PORT_SET1_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET1: SETP18 Position     */
+#define GPIO_PORT_SET1_SETP18_Msk                             (0x01UL << GPIO_PORT_SET1_SETP18_Pos)                     /*!< GPIO_PORT SET1: SETP18 Mask         */
+#define GPIO_PORT_SET1_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET1: SETP19 Position     */
+#define GPIO_PORT_SET1_SETP19_Msk                             (0x01UL << GPIO_PORT_SET1_SETP19_Pos)                     /*!< GPIO_PORT SET1: SETP19 Mask         */
+#define GPIO_PORT_SET1_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET1: SETP20 Position     */
+#define GPIO_PORT_SET1_SETP20_Msk                             (0x01UL << GPIO_PORT_SET1_SETP20_Pos)                     /*!< GPIO_PORT SET1: SETP20 Mask         */
+#define GPIO_PORT_SET1_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET1: SETP21 Position     */
+#define GPIO_PORT_SET1_SETP21_Msk                             (0x01UL << GPIO_PORT_SET1_SETP21_Pos)                     /*!< GPIO_PORT SET1: SETP21 Mask         */
+#define GPIO_PORT_SET1_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET1: SETP22 Position     */
+#define GPIO_PORT_SET1_SETP22_Msk                             (0x01UL << GPIO_PORT_SET1_SETP22_Pos)                     /*!< GPIO_PORT SET1: SETP22 Mask         */
+#define GPIO_PORT_SET1_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET1: SETP23 Position     */
+#define GPIO_PORT_SET1_SETP23_Msk                             (0x01UL << GPIO_PORT_SET1_SETP23_Pos)                     /*!< GPIO_PORT SET1: SETP23 Mask         */
+#define GPIO_PORT_SET1_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET1: SETP24 Position     */
+#define GPIO_PORT_SET1_SETP24_Msk                             (0x01UL << GPIO_PORT_SET1_SETP24_Pos)                     /*!< GPIO_PORT SET1: SETP24 Mask         */
+#define GPIO_PORT_SET1_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET1: SETP25 Position     */
+#define GPIO_PORT_SET1_SETP25_Msk                             (0x01UL << GPIO_PORT_SET1_SETP25_Pos)                     /*!< GPIO_PORT SET1: SETP25 Mask         */
+#define GPIO_PORT_SET1_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET1: SETP26 Position     */
+#define GPIO_PORT_SET1_SETP26_Msk                             (0x01UL << GPIO_PORT_SET1_SETP26_Pos)                     /*!< GPIO_PORT SET1: SETP26 Mask         */
+#define GPIO_PORT_SET1_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET1: SETP27 Position     */
+#define GPIO_PORT_SET1_SETP27_Msk                             (0x01UL << GPIO_PORT_SET1_SETP27_Pos)                     /*!< GPIO_PORT SET1: SETP27 Mask         */
+#define GPIO_PORT_SET1_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET1: SETP28 Position     */
+#define GPIO_PORT_SET1_SETP28_Msk                             (0x01UL << GPIO_PORT_SET1_SETP28_Pos)                     /*!< GPIO_PORT SET1: SETP28 Mask         */
+#define GPIO_PORT_SET1_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET1: SETP29 Position     */
+#define GPIO_PORT_SET1_SETP29_Msk                             (0x01UL << GPIO_PORT_SET1_SETP29_Pos)                     /*!< GPIO_PORT SET1: SETP29 Mask         */
+#define GPIO_PORT_SET1_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET1: SETP30 Position     */
+#define GPIO_PORT_SET1_SETP30_Msk                             (0x01UL << GPIO_PORT_SET1_SETP30_Pos)                     /*!< GPIO_PORT SET1: SETP30 Mask         */
+#define GPIO_PORT_SET1_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET1: SETP31 Position     */
+#define GPIO_PORT_SET1_SETP31_Msk                             (0x01UL << GPIO_PORT_SET1_SETP31_Pos)                     /*!< GPIO_PORT SET1: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET2  -----------------------------------------
+#define GPIO_PORT_SET2_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET2: SETP0 Position      */
+#define GPIO_PORT_SET2_SETP0_Msk                              (0x01UL << GPIO_PORT_SET2_SETP0_Pos)                      /*!< GPIO_PORT SET2: SETP0 Mask          */
+#define GPIO_PORT_SET2_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET2: SETP1 Position      */
+#define GPIO_PORT_SET2_SETP1_Msk                              (0x01UL << GPIO_PORT_SET2_SETP1_Pos)                      /*!< GPIO_PORT SET2: SETP1 Mask          */
+#define GPIO_PORT_SET2_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET2: SETP2 Position      */
+#define GPIO_PORT_SET2_SETP2_Msk                              (0x01UL << GPIO_PORT_SET2_SETP2_Pos)                      /*!< GPIO_PORT SET2: SETP2 Mask          */
+#define GPIO_PORT_SET2_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET2: SETP3 Position      */
+#define GPIO_PORT_SET2_SETP3_Msk                              (0x01UL << GPIO_PORT_SET2_SETP3_Pos)                      /*!< GPIO_PORT SET2: SETP3 Mask          */
+#define GPIO_PORT_SET2_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET2: SETP4 Position      */
+#define GPIO_PORT_SET2_SETP4_Msk                              (0x01UL << GPIO_PORT_SET2_SETP4_Pos)                      /*!< GPIO_PORT SET2: SETP4 Mask          */
+#define GPIO_PORT_SET2_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET2: SETP5 Position      */
+#define GPIO_PORT_SET2_SETP5_Msk                              (0x01UL << GPIO_PORT_SET2_SETP5_Pos)                      /*!< GPIO_PORT SET2: SETP5 Mask          */
+#define GPIO_PORT_SET2_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET2: SETP6 Position      */
+#define GPIO_PORT_SET2_SETP6_Msk                              (0x01UL << GPIO_PORT_SET2_SETP6_Pos)                      /*!< GPIO_PORT SET2: SETP6 Mask          */
+#define GPIO_PORT_SET2_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET2: SETP7 Position      */
+#define GPIO_PORT_SET2_SETP7_Msk                              (0x01UL << GPIO_PORT_SET2_SETP7_Pos)                      /*!< GPIO_PORT SET2: SETP7 Mask          */
+#define GPIO_PORT_SET2_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET2: SETP8 Position      */
+#define GPIO_PORT_SET2_SETP8_Msk                              (0x01UL << GPIO_PORT_SET2_SETP8_Pos)                      /*!< GPIO_PORT SET2: SETP8 Mask          */
+#define GPIO_PORT_SET2_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET2: SETP9 Position      */
+#define GPIO_PORT_SET2_SETP9_Msk                              (0x01UL << GPIO_PORT_SET2_SETP9_Pos)                      /*!< GPIO_PORT SET2: SETP9 Mask          */
+#define GPIO_PORT_SET2_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET2: SETP10 Position     */
+#define GPIO_PORT_SET2_SETP10_Msk                             (0x01UL << GPIO_PORT_SET2_SETP10_Pos)                     /*!< GPIO_PORT SET2: SETP10 Mask         */
+#define GPIO_PORT_SET2_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET2: SETP11 Position     */
+#define GPIO_PORT_SET2_SETP11_Msk                             (0x01UL << GPIO_PORT_SET2_SETP11_Pos)                     /*!< GPIO_PORT SET2: SETP11 Mask         */
+#define GPIO_PORT_SET2_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET2: SETP12 Position     */
+#define GPIO_PORT_SET2_SETP12_Msk                             (0x01UL << GPIO_PORT_SET2_SETP12_Pos)                     /*!< GPIO_PORT SET2: SETP12 Mask         */
+#define GPIO_PORT_SET2_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET2: SETP13 Position     */
+#define GPIO_PORT_SET2_SETP13_Msk                             (0x01UL << GPIO_PORT_SET2_SETP13_Pos)                     /*!< GPIO_PORT SET2: SETP13 Mask         */
+#define GPIO_PORT_SET2_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET2: SETP14 Position     */
+#define GPIO_PORT_SET2_SETP14_Msk                             (0x01UL << GPIO_PORT_SET2_SETP14_Pos)                     /*!< GPIO_PORT SET2: SETP14 Mask         */
+#define GPIO_PORT_SET2_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET2: SETP15 Position     */
+#define GPIO_PORT_SET2_SETP15_Msk                             (0x01UL << GPIO_PORT_SET2_SETP15_Pos)                     /*!< GPIO_PORT SET2: SETP15 Mask         */
+#define GPIO_PORT_SET2_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET2: SETP16 Position     */
+#define GPIO_PORT_SET2_SETP16_Msk                             (0x01UL << GPIO_PORT_SET2_SETP16_Pos)                     /*!< GPIO_PORT SET2: SETP16 Mask         */
+#define GPIO_PORT_SET2_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET2: SETP17 Position     */
+#define GPIO_PORT_SET2_SETP17_Msk                             (0x01UL << GPIO_PORT_SET2_SETP17_Pos)                     /*!< GPIO_PORT SET2: SETP17 Mask         */
+#define GPIO_PORT_SET2_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET2: SETP18 Position     */
+#define GPIO_PORT_SET2_SETP18_Msk                             (0x01UL << GPIO_PORT_SET2_SETP18_Pos)                     /*!< GPIO_PORT SET2: SETP18 Mask         */
+#define GPIO_PORT_SET2_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET2: SETP19 Position     */
+#define GPIO_PORT_SET2_SETP19_Msk                             (0x01UL << GPIO_PORT_SET2_SETP19_Pos)                     /*!< GPIO_PORT SET2: SETP19 Mask         */
+#define GPIO_PORT_SET2_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET2: SETP20 Position     */
+#define GPIO_PORT_SET2_SETP20_Msk                             (0x01UL << GPIO_PORT_SET2_SETP20_Pos)                     /*!< GPIO_PORT SET2: SETP20 Mask         */
+#define GPIO_PORT_SET2_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET2: SETP21 Position     */
+#define GPIO_PORT_SET2_SETP21_Msk                             (0x01UL << GPIO_PORT_SET2_SETP21_Pos)                     /*!< GPIO_PORT SET2: SETP21 Mask         */
+#define GPIO_PORT_SET2_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET2: SETP22 Position     */
+#define GPIO_PORT_SET2_SETP22_Msk                             (0x01UL << GPIO_PORT_SET2_SETP22_Pos)                     /*!< GPIO_PORT SET2: SETP22 Mask         */
+#define GPIO_PORT_SET2_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET2: SETP23 Position     */
+#define GPIO_PORT_SET2_SETP23_Msk                             (0x01UL << GPIO_PORT_SET2_SETP23_Pos)                     /*!< GPIO_PORT SET2: SETP23 Mask         */
+#define GPIO_PORT_SET2_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET2: SETP24 Position     */
+#define GPIO_PORT_SET2_SETP24_Msk                             (0x01UL << GPIO_PORT_SET2_SETP24_Pos)                     /*!< GPIO_PORT SET2: SETP24 Mask         */
+#define GPIO_PORT_SET2_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET2: SETP25 Position     */
+#define GPIO_PORT_SET2_SETP25_Msk                             (0x01UL << GPIO_PORT_SET2_SETP25_Pos)                     /*!< GPIO_PORT SET2: SETP25 Mask         */
+#define GPIO_PORT_SET2_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET2: SETP26 Position     */
+#define GPIO_PORT_SET2_SETP26_Msk                             (0x01UL << GPIO_PORT_SET2_SETP26_Pos)                     /*!< GPIO_PORT SET2: SETP26 Mask         */
+#define GPIO_PORT_SET2_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET2: SETP27 Position     */
+#define GPIO_PORT_SET2_SETP27_Msk                             (0x01UL << GPIO_PORT_SET2_SETP27_Pos)                     /*!< GPIO_PORT SET2: SETP27 Mask         */
+#define GPIO_PORT_SET2_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET2: SETP28 Position     */
+#define GPIO_PORT_SET2_SETP28_Msk                             (0x01UL << GPIO_PORT_SET2_SETP28_Pos)                     /*!< GPIO_PORT SET2: SETP28 Mask         */
+#define GPIO_PORT_SET2_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET2: SETP29 Position     */
+#define GPIO_PORT_SET2_SETP29_Msk                             (0x01UL << GPIO_PORT_SET2_SETP29_Pos)                     /*!< GPIO_PORT SET2: SETP29 Mask         */
+#define GPIO_PORT_SET2_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET2: SETP30 Position     */
+#define GPIO_PORT_SET2_SETP30_Msk                             (0x01UL << GPIO_PORT_SET2_SETP30_Pos)                     /*!< GPIO_PORT SET2: SETP30 Mask         */
+#define GPIO_PORT_SET2_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET2: SETP31 Position     */
+#define GPIO_PORT_SET2_SETP31_Msk                             (0x01UL << GPIO_PORT_SET2_SETP31_Pos)                     /*!< GPIO_PORT SET2: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET3  -----------------------------------------
+#define GPIO_PORT_SET3_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET3: SETP0 Position      */
+#define GPIO_PORT_SET3_SETP0_Msk                              (0x01UL << GPIO_PORT_SET3_SETP0_Pos)                      /*!< GPIO_PORT SET3: SETP0 Mask          */
+#define GPIO_PORT_SET3_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET3: SETP1 Position      */
+#define GPIO_PORT_SET3_SETP1_Msk                              (0x01UL << GPIO_PORT_SET3_SETP1_Pos)                      /*!< GPIO_PORT SET3: SETP1 Mask          */
+#define GPIO_PORT_SET3_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET3: SETP2 Position      */
+#define GPIO_PORT_SET3_SETP2_Msk                              (0x01UL << GPIO_PORT_SET3_SETP2_Pos)                      /*!< GPIO_PORT SET3: SETP2 Mask          */
+#define GPIO_PORT_SET3_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET3: SETP3 Position      */
+#define GPIO_PORT_SET3_SETP3_Msk                              (0x01UL << GPIO_PORT_SET3_SETP3_Pos)                      /*!< GPIO_PORT SET3: SETP3 Mask          */
+#define GPIO_PORT_SET3_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET3: SETP4 Position      */
+#define GPIO_PORT_SET3_SETP4_Msk                              (0x01UL << GPIO_PORT_SET3_SETP4_Pos)                      /*!< GPIO_PORT SET3: SETP4 Mask          */
+#define GPIO_PORT_SET3_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET3: SETP5 Position      */
+#define GPIO_PORT_SET3_SETP5_Msk                              (0x01UL << GPIO_PORT_SET3_SETP5_Pos)                      /*!< GPIO_PORT SET3: SETP5 Mask          */
+#define GPIO_PORT_SET3_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET3: SETP6 Position      */
+#define GPIO_PORT_SET3_SETP6_Msk                              (0x01UL << GPIO_PORT_SET3_SETP6_Pos)                      /*!< GPIO_PORT SET3: SETP6 Mask          */
+#define GPIO_PORT_SET3_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET3: SETP7 Position      */
+#define GPIO_PORT_SET3_SETP7_Msk                              (0x01UL << GPIO_PORT_SET3_SETP7_Pos)                      /*!< GPIO_PORT SET3: SETP7 Mask          */
+#define GPIO_PORT_SET3_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET3: SETP8 Position      */
+#define GPIO_PORT_SET3_SETP8_Msk                              (0x01UL << GPIO_PORT_SET3_SETP8_Pos)                      /*!< GPIO_PORT SET3: SETP8 Mask          */
+#define GPIO_PORT_SET3_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET3: SETP9 Position      */
+#define GPIO_PORT_SET3_SETP9_Msk                              (0x01UL << GPIO_PORT_SET3_SETP9_Pos)                      /*!< GPIO_PORT SET3: SETP9 Mask          */
+#define GPIO_PORT_SET3_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET3: SETP10 Position     */
+#define GPIO_PORT_SET3_SETP10_Msk                             (0x01UL << GPIO_PORT_SET3_SETP10_Pos)                     /*!< GPIO_PORT SET3: SETP10 Mask         */
+#define GPIO_PORT_SET3_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET3: SETP11 Position     */
+#define GPIO_PORT_SET3_SETP11_Msk                             (0x01UL << GPIO_PORT_SET3_SETP11_Pos)                     /*!< GPIO_PORT SET3: SETP11 Mask         */
+#define GPIO_PORT_SET3_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET3: SETP12 Position     */
+#define GPIO_PORT_SET3_SETP12_Msk                             (0x01UL << GPIO_PORT_SET3_SETP12_Pos)                     /*!< GPIO_PORT SET3: SETP12 Mask         */
+#define GPIO_PORT_SET3_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET3: SETP13 Position     */
+#define GPIO_PORT_SET3_SETP13_Msk                             (0x01UL << GPIO_PORT_SET3_SETP13_Pos)                     /*!< GPIO_PORT SET3: SETP13 Mask         */
+#define GPIO_PORT_SET3_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET3: SETP14 Position     */
+#define GPIO_PORT_SET3_SETP14_Msk                             (0x01UL << GPIO_PORT_SET3_SETP14_Pos)                     /*!< GPIO_PORT SET3: SETP14 Mask         */
+#define GPIO_PORT_SET3_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET3: SETP15 Position     */
+#define GPIO_PORT_SET3_SETP15_Msk                             (0x01UL << GPIO_PORT_SET3_SETP15_Pos)                     /*!< GPIO_PORT SET3: SETP15 Mask         */
+#define GPIO_PORT_SET3_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET3: SETP16 Position     */
+#define GPIO_PORT_SET3_SETP16_Msk                             (0x01UL << GPIO_PORT_SET3_SETP16_Pos)                     /*!< GPIO_PORT SET3: SETP16 Mask         */
+#define GPIO_PORT_SET3_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET3: SETP17 Position     */
+#define GPIO_PORT_SET3_SETP17_Msk                             (0x01UL << GPIO_PORT_SET3_SETP17_Pos)                     /*!< GPIO_PORT SET3: SETP17 Mask         */
+#define GPIO_PORT_SET3_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET3: SETP18 Position     */
+#define GPIO_PORT_SET3_SETP18_Msk                             (0x01UL << GPIO_PORT_SET3_SETP18_Pos)                     /*!< GPIO_PORT SET3: SETP18 Mask         */
+#define GPIO_PORT_SET3_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET3: SETP19 Position     */
+#define GPIO_PORT_SET3_SETP19_Msk                             (0x01UL << GPIO_PORT_SET3_SETP19_Pos)                     /*!< GPIO_PORT SET3: SETP19 Mask         */
+#define GPIO_PORT_SET3_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET3: SETP20 Position     */
+#define GPIO_PORT_SET3_SETP20_Msk                             (0x01UL << GPIO_PORT_SET3_SETP20_Pos)                     /*!< GPIO_PORT SET3: SETP20 Mask         */
+#define GPIO_PORT_SET3_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET3: SETP21 Position     */
+#define GPIO_PORT_SET3_SETP21_Msk                             (0x01UL << GPIO_PORT_SET3_SETP21_Pos)                     /*!< GPIO_PORT SET3: SETP21 Mask         */
+#define GPIO_PORT_SET3_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET3: SETP22 Position     */
+#define GPIO_PORT_SET3_SETP22_Msk                             (0x01UL << GPIO_PORT_SET3_SETP22_Pos)                     /*!< GPIO_PORT SET3: SETP22 Mask         */
+#define GPIO_PORT_SET3_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET3: SETP23 Position     */
+#define GPIO_PORT_SET3_SETP23_Msk                             (0x01UL << GPIO_PORT_SET3_SETP23_Pos)                     /*!< GPIO_PORT SET3: SETP23 Mask         */
+#define GPIO_PORT_SET3_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET3: SETP24 Position     */
+#define GPIO_PORT_SET3_SETP24_Msk                             (0x01UL << GPIO_PORT_SET3_SETP24_Pos)                     /*!< GPIO_PORT SET3: SETP24 Mask         */
+#define GPIO_PORT_SET3_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET3: SETP25 Position     */
+#define GPIO_PORT_SET3_SETP25_Msk                             (0x01UL << GPIO_PORT_SET3_SETP25_Pos)                     /*!< GPIO_PORT SET3: SETP25 Mask         */
+#define GPIO_PORT_SET3_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET3: SETP26 Position     */
+#define GPIO_PORT_SET3_SETP26_Msk                             (0x01UL << GPIO_PORT_SET3_SETP26_Pos)                     /*!< GPIO_PORT SET3: SETP26 Mask         */
+#define GPIO_PORT_SET3_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET3: SETP27 Position     */
+#define GPIO_PORT_SET3_SETP27_Msk                             (0x01UL << GPIO_PORT_SET3_SETP27_Pos)                     /*!< GPIO_PORT SET3: SETP27 Mask         */
+#define GPIO_PORT_SET3_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET3: SETP28 Position     */
+#define GPIO_PORT_SET3_SETP28_Msk                             (0x01UL << GPIO_PORT_SET3_SETP28_Pos)                     /*!< GPIO_PORT SET3: SETP28 Mask         */
+#define GPIO_PORT_SET3_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET3: SETP29 Position     */
+#define GPIO_PORT_SET3_SETP29_Msk                             (0x01UL << GPIO_PORT_SET3_SETP29_Pos)                     /*!< GPIO_PORT SET3: SETP29 Mask         */
+#define GPIO_PORT_SET3_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET3: SETP30 Position     */
+#define GPIO_PORT_SET3_SETP30_Msk                             (0x01UL << GPIO_PORT_SET3_SETP30_Pos)                     /*!< GPIO_PORT SET3: SETP30 Mask         */
+#define GPIO_PORT_SET3_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET3: SETP31 Position     */
+#define GPIO_PORT_SET3_SETP31_Msk                             (0x01UL << GPIO_PORT_SET3_SETP31_Pos)                     /*!< GPIO_PORT SET3: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET4  -----------------------------------------
+#define GPIO_PORT_SET4_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET4: SETP0 Position      */
+#define GPIO_PORT_SET4_SETP0_Msk                              (0x01UL << GPIO_PORT_SET4_SETP0_Pos)                      /*!< GPIO_PORT SET4: SETP0 Mask          */
+#define GPIO_PORT_SET4_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET4: SETP1 Position      */
+#define GPIO_PORT_SET4_SETP1_Msk                              (0x01UL << GPIO_PORT_SET4_SETP1_Pos)                      /*!< GPIO_PORT SET4: SETP1 Mask          */
+#define GPIO_PORT_SET4_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET4: SETP2 Position      */
+#define GPIO_PORT_SET4_SETP2_Msk                              (0x01UL << GPIO_PORT_SET4_SETP2_Pos)                      /*!< GPIO_PORT SET4: SETP2 Mask          */
+#define GPIO_PORT_SET4_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET4: SETP3 Position      */
+#define GPIO_PORT_SET4_SETP3_Msk                              (0x01UL << GPIO_PORT_SET4_SETP3_Pos)                      /*!< GPIO_PORT SET4: SETP3 Mask          */
+#define GPIO_PORT_SET4_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET4: SETP4 Position      */
+#define GPIO_PORT_SET4_SETP4_Msk                              (0x01UL << GPIO_PORT_SET4_SETP4_Pos)                      /*!< GPIO_PORT SET4: SETP4 Mask          */
+#define GPIO_PORT_SET4_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET4: SETP5 Position      */
+#define GPIO_PORT_SET4_SETP5_Msk                              (0x01UL << GPIO_PORT_SET4_SETP5_Pos)                      /*!< GPIO_PORT SET4: SETP5 Mask          */
+#define GPIO_PORT_SET4_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET4: SETP6 Position      */
+#define GPIO_PORT_SET4_SETP6_Msk                              (0x01UL << GPIO_PORT_SET4_SETP6_Pos)                      /*!< GPIO_PORT SET4: SETP6 Mask          */
+#define GPIO_PORT_SET4_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET4: SETP7 Position      */
+#define GPIO_PORT_SET4_SETP7_Msk                              (0x01UL << GPIO_PORT_SET4_SETP7_Pos)                      /*!< GPIO_PORT SET4: SETP7 Mask          */
+#define GPIO_PORT_SET4_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET4: SETP8 Position      */
+#define GPIO_PORT_SET4_SETP8_Msk                              (0x01UL << GPIO_PORT_SET4_SETP8_Pos)                      /*!< GPIO_PORT SET4: SETP8 Mask          */
+#define GPIO_PORT_SET4_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET4: SETP9 Position      */
+#define GPIO_PORT_SET4_SETP9_Msk                              (0x01UL << GPIO_PORT_SET4_SETP9_Pos)                      /*!< GPIO_PORT SET4: SETP9 Mask          */
+#define GPIO_PORT_SET4_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET4: SETP10 Position     */
+#define GPIO_PORT_SET4_SETP10_Msk                             (0x01UL << GPIO_PORT_SET4_SETP10_Pos)                     /*!< GPIO_PORT SET4: SETP10 Mask         */
+#define GPIO_PORT_SET4_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET4: SETP11 Position     */
+#define GPIO_PORT_SET4_SETP11_Msk                             (0x01UL << GPIO_PORT_SET4_SETP11_Pos)                     /*!< GPIO_PORT SET4: SETP11 Mask         */
+#define GPIO_PORT_SET4_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET4: SETP12 Position     */
+#define GPIO_PORT_SET4_SETP12_Msk                             (0x01UL << GPIO_PORT_SET4_SETP12_Pos)                     /*!< GPIO_PORT SET4: SETP12 Mask         */
+#define GPIO_PORT_SET4_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET4: SETP13 Position     */
+#define GPIO_PORT_SET4_SETP13_Msk                             (0x01UL << GPIO_PORT_SET4_SETP13_Pos)                     /*!< GPIO_PORT SET4: SETP13 Mask         */
+#define GPIO_PORT_SET4_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET4: SETP14 Position     */
+#define GPIO_PORT_SET4_SETP14_Msk                             (0x01UL << GPIO_PORT_SET4_SETP14_Pos)                     /*!< GPIO_PORT SET4: SETP14 Mask         */
+#define GPIO_PORT_SET4_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET4: SETP15 Position     */
+#define GPIO_PORT_SET4_SETP15_Msk                             (0x01UL << GPIO_PORT_SET4_SETP15_Pos)                     /*!< GPIO_PORT SET4: SETP15 Mask         */
+#define GPIO_PORT_SET4_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET4: SETP16 Position     */
+#define GPIO_PORT_SET4_SETP16_Msk                             (0x01UL << GPIO_PORT_SET4_SETP16_Pos)                     /*!< GPIO_PORT SET4: SETP16 Mask         */
+#define GPIO_PORT_SET4_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET4: SETP17 Position     */
+#define GPIO_PORT_SET4_SETP17_Msk                             (0x01UL << GPIO_PORT_SET4_SETP17_Pos)                     /*!< GPIO_PORT SET4: SETP17 Mask         */
+#define GPIO_PORT_SET4_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET4: SETP18 Position     */
+#define GPIO_PORT_SET4_SETP18_Msk                             (0x01UL << GPIO_PORT_SET4_SETP18_Pos)                     /*!< GPIO_PORT SET4: SETP18 Mask         */
+#define GPIO_PORT_SET4_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET4: SETP19 Position     */
+#define GPIO_PORT_SET4_SETP19_Msk                             (0x01UL << GPIO_PORT_SET4_SETP19_Pos)                     /*!< GPIO_PORT SET4: SETP19 Mask         */
+#define GPIO_PORT_SET4_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET4: SETP20 Position     */
+#define GPIO_PORT_SET4_SETP20_Msk                             (0x01UL << GPIO_PORT_SET4_SETP20_Pos)                     /*!< GPIO_PORT SET4: SETP20 Mask         */
+#define GPIO_PORT_SET4_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET4: SETP21 Position     */
+#define GPIO_PORT_SET4_SETP21_Msk                             (0x01UL << GPIO_PORT_SET4_SETP21_Pos)                     /*!< GPIO_PORT SET4: SETP21 Mask         */
+#define GPIO_PORT_SET4_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET4: SETP22 Position     */
+#define GPIO_PORT_SET4_SETP22_Msk                             (0x01UL << GPIO_PORT_SET4_SETP22_Pos)                     /*!< GPIO_PORT SET4: SETP22 Mask         */
+#define GPIO_PORT_SET4_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET4: SETP23 Position     */
+#define GPIO_PORT_SET4_SETP23_Msk                             (0x01UL << GPIO_PORT_SET4_SETP23_Pos)                     /*!< GPIO_PORT SET4: SETP23 Mask         */
+#define GPIO_PORT_SET4_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET4: SETP24 Position     */
+#define GPIO_PORT_SET4_SETP24_Msk                             (0x01UL << GPIO_PORT_SET4_SETP24_Pos)                     /*!< GPIO_PORT SET4: SETP24 Mask         */
+#define GPIO_PORT_SET4_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET4: SETP25 Position     */
+#define GPIO_PORT_SET4_SETP25_Msk                             (0x01UL << GPIO_PORT_SET4_SETP25_Pos)                     /*!< GPIO_PORT SET4: SETP25 Mask         */
+#define GPIO_PORT_SET4_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET4: SETP26 Position     */
+#define GPIO_PORT_SET4_SETP26_Msk                             (0x01UL << GPIO_PORT_SET4_SETP26_Pos)                     /*!< GPIO_PORT SET4: SETP26 Mask         */
+#define GPIO_PORT_SET4_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET4: SETP27 Position     */
+#define GPIO_PORT_SET4_SETP27_Msk                             (0x01UL << GPIO_PORT_SET4_SETP27_Pos)                     /*!< GPIO_PORT SET4: SETP27 Mask         */
+#define GPIO_PORT_SET4_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET4: SETP28 Position     */
+#define GPIO_PORT_SET4_SETP28_Msk                             (0x01UL << GPIO_PORT_SET4_SETP28_Pos)                     /*!< GPIO_PORT SET4: SETP28 Mask         */
+#define GPIO_PORT_SET4_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET4: SETP29 Position     */
+#define GPIO_PORT_SET4_SETP29_Msk                             (0x01UL << GPIO_PORT_SET4_SETP29_Pos)                     /*!< GPIO_PORT SET4: SETP29 Mask         */
+#define GPIO_PORT_SET4_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET4: SETP30 Position     */
+#define GPIO_PORT_SET4_SETP30_Msk                             (0x01UL << GPIO_PORT_SET4_SETP30_Pos)                     /*!< GPIO_PORT SET4: SETP30 Mask         */
+#define GPIO_PORT_SET4_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET4: SETP31 Position     */
+#define GPIO_PORT_SET4_SETP31_Msk                             (0x01UL << GPIO_PORT_SET4_SETP31_Pos)                     /*!< GPIO_PORT SET4: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET5  -----------------------------------------
+#define GPIO_PORT_SET5_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET5: SETP0 Position      */
+#define GPIO_PORT_SET5_SETP0_Msk                              (0x01UL << GPIO_PORT_SET5_SETP0_Pos)                      /*!< GPIO_PORT SET5: SETP0 Mask          */
+#define GPIO_PORT_SET5_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET5: SETP1 Position      */
+#define GPIO_PORT_SET5_SETP1_Msk                              (0x01UL << GPIO_PORT_SET5_SETP1_Pos)                      /*!< GPIO_PORT SET5: SETP1 Mask          */
+#define GPIO_PORT_SET5_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET5: SETP2 Position      */
+#define GPIO_PORT_SET5_SETP2_Msk                              (0x01UL << GPIO_PORT_SET5_SETP2_Pos)                      /*!< GPIO_PORT SET5: SETP2 Mask          */
+#define GPIO_PORT_SET5_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET5: SETP3 Position      */
+#define GPIO_PORT_SET5_SETP3_Msk                              (0x01UL << GPIO_PORT_SET5_SETP3_Pos)                      /*!< GPIO_PORT SET5: SETP3 Mask          */
+#define GPIO_PORT_SET5_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET5: SETP4 Position      */
+#define GPIO_PORT_SET5_SETP4_Msk                              (0x01UL << GPIO_PORT_SET5_SETP4_Pos)                      /*!< GPIO_PORT SET5: SETP4 Mask          */
+#define GPIO_PORT_SET5_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET5: SETP5 Position      */
+#define GPIO_PORT_SET5_SETP5_Msk                              (0x01UL << GPIO_PORT_SET5_SETP5_Pos)                      /*!< GPIO_PORT SET5: SETP5 Mask          */
+#define GPIO_PORT_SET5_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET5: SETP6 Position      */
+#define GPIO_PORT_SET5_SETP6_Msk                              (0x01UL << GPIO_PORT_SET5_SETP6_Pos)                      /*!< GPIO_PORT SET5: SETP6 Mask          */
+#define GPIO_PORT_SET5_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET5: SETP7 Position      */
+#define GPIO_PORT_SET5_SETP7_Msk                              (0x01UL << GPIO_PORT_SET5_SETP7_Pos)                      /*!< GPIO_PORT SET5: SETP7 Mask          */
+#define GPIO_PORT_SET5_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET5: SETP8 Position      */
+#define GPIO_PORT_SET5_SETP8_Msk                              (0x01UL << GPIO_PORT_SET5_SETP8_Pos)                      /*!< GPIO_PORT SET5: SETP8 Mask          */
+#define GPIO_PORT_SET5_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET5: SETP9 Position      */
+#define GPIO_PORT_SET5_SETP9_Msk                              (0x01UL << GPIO_PORT_SET5_SETP9_Pos)                      /*!< GPIO_PORT SET5: SETP9 Mask          */
+#define GPIO_PORT_SET5_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET5: SETP10 Position     */
+#define GPIO_PORT_SET5_SETP10_Msk                             (0x01UL << GPIO_PORT_SET5_SETP10_Pos)                     /*!< GPIO_PORT SET5: SETP10 Mask         */
+#define GPIO_PORT_SET5_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET5: SETP11 Position     */
+#define GPIO_PORT_SET5_SETP11_Msk                             (0x01UL << GPIO_PORT_SET5_SETP11_Pos)                     /*!< GPIO_PORT SET5: SETP11 Mask         */
+#define GPIO_PORT_SET5_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET5: SETP12 Position     */
+#define GPIO_PORT_SET5_SETP12_Msk                             (0x01UL << GPIO_PORT_SET5_SETP12_Pos)                     /*!< GPIO_PORT SET5: SETP12 Mask         */
+#define GPIO_PORT_SET5_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET5: SETP13 Position     */
+#define GPIO_PORT_SET5_SETP13_Msk                             (0x01UL << GPIO_PORT_SET5_SETP13_Pos)                     /*!< GPIO_PORT SET5: SETP13 Mask         */
+#define GPIO_PORT_SET5_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET5: SETP14 Position     */
+#define GPIO_PORT_SET5_SETP14_Msk                             (0x01UL << GPIO_PORT_SET5_SETP14_Pos)                     /*!< GPIO_PORT SET5: SETP14 Mask         */
+#define GPIO_PORT_SET5_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET5: SETP15 Position     */
+#define GPIO_PORT_SET5_SETP15_Msk                             (0x01UL << GPIO_PORT_SET5_SETP15_Pos)                     /*!< GPIO_PORT SET5: SETP15 Mask         */
+#define GPIO_PORT_SET5_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET5: SETP16 Position     */
+#define GPIO_PORT_SET5_SETP16_Msk                             (0x01UL << GPIO_PORT_SET5_SETP16_Pos)                     /*!< GPIO_PORT SET5: SETP16 Mask         */
+#define GPIO_PORT_SET5_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET5: SETP17 Position     */
+#define GPIO_PORT_SET5_SETP17_Msk                             (0x01UL << GPIO_PORT_SET5_SETP17_Pos)                     /*!< GPIO_PORT SET5: SETP17 Mask         */
+#define GPIO_PORT_SET5_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET5: SETP18 Position     */
+#define GPIO_PORT_SET5_SETP18_Msk                             (0x01UL << GPIO_PORT_SET5_SETP18_Pos)                     /*!< GPIO_PORT SET5: SETP18 Mask         */
+#define GPIO_PORT_SET5_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET5: SETP19 Position     */
+#define GPIO_PORT_SET5_SETP19_Msk                             (0x01UL << GPIO_PORT_SET5_SETP19_Pos)                     /*!< GPIO_PORT SET5: SETP19 Mask         */
+#define GPIO_PORT_SET5_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET5: SETP20 Position     */
+#define GPIO_PORT_SET5_SETP20_Msk                             (0x01UL << GPIO_PORT_SET5_SETP20_Pos)                     /*!< GPIO_PORT SET5: SETP20 Mask         */
+#define GPIO_PORT_SET5_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET5: SETP21 Position     */
+#define GPIO_PORT_SET5_SETP21_Msk                             (0x01UL << GPIO_PORT_SET5_SETP21_Pos)                     /*!< GPIO_PORT SET5: SETP21 Mask         */
+#define GPIO_PORT_SET5_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET5: SETP22 Position     */
+#define GPIO_PORT_SET5_SETP22_Msk                             (0x01UL << GPIO_PORT_SET5_SETP22_Pos)                     /*!< GPIO_PORT SET5: SETP22 Mask         */
+#define GPIO_PORT_SET5_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET5: SETP23 Position     */
+#define GPIO_PORT_SET5_SETP23_Msk                             (0x01UL << GPIO_PORT_SET5_SETP23_Pos)                     /*!< GPIO_PORT SET5: SETP23 Mask         */
+#define GPIO_PORT_SET5_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET5: SETP24 Position     */
+#define GPIO_PORT_SET5_SETP24_Msk                             (0x01UL << GPIO_PORT_SET5_SETP24_Pos)                     /*!< GPIO_PORT SET5: SETP24 Mask         */
+#define GPIO_PORT_SET5_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET5: SETP25 Position     */
+#define GPIO_PORT_SET5_SETP25_Msk                             (0x01UL << GPIO_PORT_SET5_SETP25_Pos)                     /*!< GPIO_PORT SET5: SETP25 Mask         */
+#define GPIO_PORT_SET5_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET5: SETP26 Position     */
+#define GPIO_PORT_SET5_SETP26_Msk                             (0x01UL << GPIO_PORT_SET5_SETP26_Pos)                     /*!< GPIO_PORT SET5: SETP26 Mask         */
+#define GPIO_PORT_SET5_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET5: SETP27 Position     */
+#define GPIO_PORT_SET5_SETP27_Msk                             (0x01UL << GPIO_PORT_SET5_SETP27_Pos)                     /*!< GPIO_PORT SET5: SETP27 Mask         */
+#define GPIO_PORT_SET5_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET5: SETP28 Position     */
+#define GPIO_PORT_SET5_SETP28_Msk                             (0x01UL << GPIO_PORT_SET5_SETP28_Pos)                     /*!< GPIO_PORT SET5: SETP28 Mask         */
+#define GPIO_PORT_SET5_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET5: SETP29 Position     */
+#define GPIO_PORT_SET5_SETP29_Msk                             (0x01UL << GPIO_PORT_SET5_SETP29_Pos)                     /*!< GPIO_PORT SET5: SETP29 Mask         */
+#define GPIO_PORT_SET5_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET5: SETP30 Position     */
+#define GPIO_PORT_SET5_SETP30_Msk                             (0x01UL << GPIO_PORT_SET5_SETP30_Pos)                     /*!< GPIO_PORT SET5: SETP30 Mask         */
+#define GPIO_PORT_SET5_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET5: SETP31 Position     */
+#define GPIO_PORT_SET5_SETP31_Msk                             (0x01UL << GPIO_PORT_SET5_SETP31_Pos)                     /*!< GPIO_PORT SET5: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET6  -----------------------------------------
+#define GPIO_PORT_SET6_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET6: SETP0 Position      */
+#define GPIO_PORT_SET6_SETP0_Msk                              (0x01UL << GPIO_PORT_SET6_SETP0_Pos)                      /*!< GPIO_PORT SET6: SETP0 Mask          */
+#define GPIO_PORT_SET6_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET6: SETP1 Position      */
+#define GPIO_PORT_SET6_SETP1_Msk                              (0x01UL << GPIO_PORT_SET6_SETP1_Pos)                      /*!< GPIO_PORT SET6: SETP1 Mask          */
+#define GPIO_PORT_SET6_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET6: SETP2 Position      */
+#define GPIO_PORT_SET6_SETP2_Msk                              (0x01UL << GPIO_PORT_SET6_SETP2_Pos)                      /*!< GPIO_PORT SET6: SETP2 Mask          */
+#define GPIO_PORT_SET6_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET6: SETP3 Position      */
+#define GPIO_PORT_SET6_SETP3_Msk                              (0x01UL << GPIO_PORT_SET6_SETP3_Pos)                      /*!< GPIO_PORT SET6: SETP3 Mask          */
+#define GPIO_PORT_SET6_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET6: SETP4 Position      */
+#define GPIO_PORT_SET6_SETP4_Msk                              (0x01UL << GPIO_PORT_SET6_SETP4_Pos)                      /*!< GPIO_PORT SET6: SETP4 Mask          */
+#define GPIO_PORT_SET6_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET6: SETP5 Position      */
+#define GPIO_PORT_SET6_SETP5_Msk                              (0x01UL << GPIO_PORT_SET6_SETP5_Pos)                      /*!< GPIO_PORT SET6: SETP5 Mask          */
+#define GPIO_PORT_SET6_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET6: SETP6 Position      */
+#define GPIO_PORT_SET6_SETP6_Msk                              (0x01UL << GPIO_PORT_SET6_SETP6_Pos)                      /*!< GPIO_PORT SET6: SETP6 Mask          */
+#define GPIO_PORT_SET6_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET6: SETP7 Position      */
+#define GPIO_PORT_SET6_SETP7_Msk                              (0x01UL << GPIO_PORT_SET6_SETP7_Pos)                      /*!< GPIO_PORT SET6: SETP7 Mask          */
+#define GPIO_PORT_SET6_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET6: SETP8 Position      */
+#define GPIO_PORT_SET6_SETP8_Msk                              (0x01UL << GPIO_PORT_SET6_SETP8_Pos)                      /*!< GPIO_PORT SET6: SETP8 Mask          */
+#define GPIO_PORT_SET6_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET6: SETP9 Position      */
+#define GPIO_PORT_SET6_SETP9_Msk                              (0x01UL << GPIO_PORT_SET6_SETP9_Pos)                      /*!< GPIO_PORT SET6: SETP9 Mask          */
+#define GPIO_PORT_SET6_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET6: SETP10 Position     */
+#define GPIO_PORT_SET6_SETP10_Msk                             (0x01UL << GPIO_PORT_SET6_SETP10_Pos)                     /*!< GPIO_PORT SET6: SETP10 Mask         */
+#define GPIO_PORT_SET6_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET6: SETP11 Position     */
+#define GPIO_PORT_SET6_SETP11_Msk                             (0x01UL << GPIO_PORT_SET6_SETP11_Pos)                     /*!< GPIO_PORT SET6: SETP11 Mask         */
+#define GPIO_PORT_SET6_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET6: SETP12 Position     */
+#define GPIO_PORT_SET6_SETP12_Msk                             (0x01UL << GPIO_PORT_SET6_SETP12_Pos)                     /*!< GPIO_PORT SET6: SETP12 Mask         */
+#define GPIO_PORT_SET6_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET6: SETP13 Position     */
+#define GPIO_PORT_SET6_SETP13_Msk                             (0x01UL << GPIO_PORT_SET6_SETP13_Pos)                     /*!< GPIO_PORT SET6: SETP13 Mask         */
+#define GPIO_PORT_SET6_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET6: SETP14 Position     */
+#define GPIO_PORT_SET6_SETP14_Msk                             (0x01UL << GPIO_PORT_SET6_SETP14_Pos)                     /*!< GPIO_PORT SET6: SETP14 Mask         */
+#define GPIO_PORT_SET6_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET6: SETP15 Position     */
+#define GPIO_PORT_SET6_SETP15_Msk                             (0x01UL << GPIO_PORT_SET6_SETP15_Pos)                     /*!< GPIO_PORT SET6: SETP15 Mask         */
+#define GPIO_PORT_SET6_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET6: SETP16 Position     */
+#define GPIO_PORT_SET6_SETP16_Msk                             (0x01UL << GPIO_PORT_SET6_SETP16_Pos)                     /*!< GPIO_PORT SET6: SETP16 Mask         */
+#define GPIO_PORT_SET6_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET6: SETP17 Position     */
+#define GPIO_PORT_SET6_SETP17_Msk                             (0x01UL << GPIO_PORT_SET6_SETP17_Pos)                     /*!< GPIO_PORT SET6: SETP17 Mask         */
+#define GPIO_PORT_SET6_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET6: SETP18 Position     */
+#define GPIO_PORT_SET6_SETP18_Msk                             (0x01UL << GPIO_PORT_SET6_SETP18_Pos)                     /*!< GPIO_PORT SET6: SETP18 Mask         */
+#define GPIO_PORT_SET6_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET6: SETP19 Position     */
+#define GPIO_PORT_SET6_SETP19_Msk                             (0x01UL << GPIO_PORT_SET6_SETP19_Pos)                     /*!< GPIO_PORT SET6: SETP19 Mask         */
+#define GPIO_PORT_SET6_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET6: SETP20 Position     */
+#define GPIO_PORT_SET6_SETP20_Msk                             (0x01UL << GPIO_PORT_SET6_SETP20_Pos)                     /*!< GPIO_PORT SET6: SETP20 Mask         */
+#define GPIO_PORT_SET6_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET6: SETP21 Position     */
+#define GPIO_PORT_SET6_SETP21_Msk                             (0x01UL << GPIO_PORT_SET6_SETP21_Pos)                     /*!< GPIO_PORT SET6: SETP21 Mask         */
+#define GPIO_PORT_SET6_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET6: SETP22 Position     */
+#define GPIO_PORT_SET6_SETP22_Msk                             (0x01UL << GPIO_PORT_SET6_SETP22_Pos)                     /*!< GPIO_PORT SET6: SETP22 Mask         */
+#define GPIO_PORT_SET6_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET6: SETP23 Position     */
+#define GPIO_PORT_SET6_SETP23_Msk                             (0x01UL << GPIO_PORT_SET6_SETP23_Pos)                     /*!< GPIO_PORT SET6: SETP23 Mask         */
+#define GPIO_PORT_SET6_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET6: SETP24 Position     */
+#define GPIO_PORT_SET6_SETP24_Msk                             (0x01UL << GPIO_PORT_SET6_SETP24_Pos)                     /*!< GPIO_PORT SET6: SETP24 Mask         */
+#define GPIO_PORT_SET6_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET6: SETP25 Position     */
+#define GPIO_PORT_SET6_SETP25_Msk                             (0x01UL << GPIO_PORT_SET6_SETP25_Pos)                     /*!< GPIO_PORT SET6: SETP25 Mask         */
+#define GPIO_PORT_SET6_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET6: SETP26 Position     */
+#define GPIO_PORT_SET6_SETP26_Msk                             (0x01UL << GPIO_PORT_SET6_SETP26_Pos)                     /*!< GPIO_PORT SET6: SETP26 Mask         */
+#define GPIO_PORT_SET6_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET6: SETP27 Position     */
+#define GPIO_PORT_SET6_SETP27_Msk                             (0x01UL << GPIO_PORT_SET6_SETP27_Pos)                     /*!< GPIO_PORT SET6: SETP27 Mask         */
+#define GPIO_PORT_SET6_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET6: SETP28 Position     */
+#define GPIO_PORT_SET6_SETP28_Msk                             (0x01UL << GPIO_PORT_SET6_SETP28_Pos)                     /*!< GPIO_PORT SET6: SETP28 Mask         */
+#define GPIO_PORT_SET6_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET6: SETP29 Position     */
+#define GPIO_PORT_SET6_SETP29_Msk                             (0x01UL << GPIO_PORT_SET6_SETP29_Pos)                     /*!< GPIO_PORT SET6: SETP29 Mask         */
+#define GPIO_PORT_SET6_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET6: SETP30 Position     */
+#define GPIO_PORT_SET6_SETP30_Msk                             (0x01UL << GPIO_PORT_SET6_SETP30_Pos)                     /*!< GPIO_PORT SET6: SETP30 Mask         */
+#define GPIO_PORT_SET6_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET6: SETP31 Position     */
+#define GPIO_PORT_SET6_SETP31_Msk                             (0x01UL << GPIO_PORT_SET6_SETP31_Pos)                     /*!< GPIO_PORT SET6: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_SET7  -----------------------------------------
+#define GPIO_PORT_SET7_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET7: SETP0 Position      */
+#define GPIO_PORT_SET7_SETP0_Msk                              (0x01UL << GPIO_PORT_SET7_SETP0_Pos)                      /*!< GPIO_PORT SET7: SETP0 Mask          */
+#define GPIO_PORT_SET7_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET7: SETP1 Position      */
+#define GPIO_PORT_SET7_SETP1_Msk                              (0x01UL << GPIO_PORT_SET7_SETP1_Pos)                      /*!< GPIO_PORT SET7: SETP1 Mask          */
+#define GPIO_PORT_SET7_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET7: SETP2 Position      */
+#define GPIO_PORT_SET7_SETP2_Msk                              (0x01UL << GPIO_PORT_SET7_SETP2_Pos)                      /*!< GPIO_PORT SET7: SETP2 Mask          */
+#define GPIO_PORT_SET7_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET7: SETP3 Position      */
+#define GPIO_PORT_SET7_SETP3_Msk                              (0x01UL << GPIO_PORT_SET7_SETP3_Pos)                      /*!< GPIO_PORT SET7: SETP3 Mask          */
+#define GPIO_PORT_SET7_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET7: SETP4 Position      */
+#define GPIO_PORT_SET7_SETP4_Msk                              (0x01UL << GPIO_PORT_SET7_SETP4_Pos)                      /*!< GPIO_PORT SET7: SETP4 Mask          */
+#define GPIO_PORT_SET7_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET7: SETP5 Position      */
+#define GPIO_PORT_SET7_SETP5_Msk                              (0x01UL << GPIO_PORT_SET7_SETP5_Pos)                      /*!< GPIO_PORT SET7: SETP5 Mask          */
+#define GPIO_PORT_SET7_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET7: SETP6 Position      */
+#define GPIO_PORT_SET7_SETP6_Msk                              (0x01UL << GPIO_PORT_SET7_SETP6_Pos)                      /*!< GPIO_PORT SET7: SETP6 Mask          */
+#define GPIO_PORT_SET7_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET7: SETP7 Position      */
+#define GPIO_PORT_SET7_SETP7_Msk                              (0x01UL << GPIO_PORT_SET7_SETP7_Pos)                      /*!< GPIO_PORT SET7: SETP7 Mask          */
+#define GPIO_PORT_SET7_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET7: SETP8 Position      */
+#define GPIO_PORT_SET7_SETP8_Msk                              (0x01UL << GPIO_PORT_SET7_SETP8_Pos)                      /*!< GPIO_PORT SET7: SETP8 Mask          */
+#define GPIO_PORT_SET7_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET7: SETP9 Position      */
+#define GPIO_PORT_SET7_SETP9_Msk                              (0x01UL << GPIO_PORT_SET7_SETP9_Pos)                      /*!< GPIO_PORT SET7: SETP9 Mask          */
+#define GPIO_PORT_SET7_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET7: SETP10 Position     */
+#define GPIO_PORT_SET7_SETP10_Msk                             (0x01UL << GPIO_PORT_SET7_SETP10_Pos)                     /*!< GPIO_PORT SET7: SETP10 Mask         */
+#define GPIO_PORT_SET7_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET7: SETP11 Position     */
+#define GPIO_PORT_SET7_SETP11_Msk                             (0x01UL << GPIO_PORT_SET7_SETP11_Pos)                     /*!< GPIO_PORT SET7: SETP11 Mask         */
+#define GPIO_PORT_SET7_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET7: SETP12 Position     */
+#define GPIO_PORT_SET7_SETP12_Msk                             (0x01UL << GPIO_PORT_SET7_SETP12_Pos)                     /*!< GPIO_PORT SET7: SETP12 Mask         */
+#define GPIO_PORT_SET7_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET7: SETP13 Position     */
+#define GPIO_PORT_SET7_SETP13_Msk                             (0x01UL << GPIO_PORT_SET7_SETP13_Pos)                     /*!< GPIO_PORT SET7: SETP13 Mask         */
+#define GPIO_PORT_SET7_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET7: SETP14 Position     */
+#define GPIO_PORT_SET7_SETP14_Msk                             (0x01UL << GPIO_PORT_SET7_SETP14_Pos)                     /*!< GPIO_PORT SET7: SETP14 Mask         */
+#define GPIO_PORT_SET7_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET7: SETP15 Position     */
+#define GPIO_PORT_SET7_SETP15_Msk                             (0x01UL << GPIO_PORT_SET7_SETP15_Pos)                     /*!< GPIO_PORT SET7: SETP15 Mask         */
+#define GPIO_PORT_SET7_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET7: SETP16 Position     */
+#define GPIO_PORT_SET7_SETP16_Msk                             (0x01UL << GPIO_PORT_SET7_SETP16_Pos)                     /*!< GPIO_PORT SET7: SETP16 Mask         */
+#define GPIO_PORT_SET7_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET7: SETP17 Position     */
+#define GPIO_PORT_SET7_SETP17_Msk                             (0x01UL << GPIO_PORT_SET7_SETP17_Pos)                     /*!< GPIO_PORT SET7: SETP17 Mask         */
+#define GPIO_PORT_SET7_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET7: SETP18 Position     */
+#define GPIO_PORT_SET7_SETP18_Msk                             (0x01UL << GPIO_PORT_SET7_SETP18_Pos)                     /*!< GPIO_PORT SET7: SETP18 Mask         */
+#define GPIO_PORT_SET7_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET7: SETP19 Position     */
+#define GPIO_PORT_SET7_SETP19_Msk                             (0x01UL << GPIO_PORT_SET7_SETP19_Pos)                     /*!< GPIO_PORT SET7: SETP19 Mask         */
+#define GPIO_PORT_SET7_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET7: SETP20 Position     */
+#define GPIO_PORT_SET7_SETP20_Msk                             (0x01UL << GPIO_PORT_SET7_SETP20_Pos)                     /*!< GPIO_PORT SET7: SETP20 Mask         */
+#define GPIO_PORT_SET7_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET7: SETP21 Position     */
+#define GPIO_PORT_SET7_SETP21_Msk                             (0x01UL << GPIO_PORT_SET7_SETP21_Pos)                     /*!< GPIO_PORT SET7: SETP21 Mask         */
+#define GPIO_PORT_SET7_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET7: SETP22 Position     */
+#define GPIO_PORT_SET7_SETP22_Msk                             (0x01UL << GPIO_PORT_SET7_SETP22_Pos)                     /*!< GPIO_PORT SET7: SETP22 Mask         */
+#define GPIO_PORT_SET7_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET7: SETP23 Position     */
+#define GPIO_PORT_SET7_SETP23_Msk                             (0x01UL << GPIO_PORT_SET7_SETP23_Pos)                     /*!< GPIO_PORT SET7: SETP23 Mask         */
+#define GPIO_PORT_SET7_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET7: SETP24 Position     */
+#define GPIO_PORT_SET7_SETP24_Msk                             (0x01UL << GPIO_PORT_SET7_SETP24_Pos)                     /*!< GPIO_PORT SET7: SETP24 Mask         */
+#define GPIO_PORT_SET7_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET7: SETP25 Position     */
+#define GPIO_PORT_SET7_SETP25_Msk                             (0x01UL << GPIO_PORT_SET7_SETP25_Pos)                     /*!< GPIO_PORT SET7: SETP25 Mask         */
+#define GPIO_PORT_SET7_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET7: SETP26 Position     */
+#define GPIO_PORT_SET7_SETP26_Msk                             (0x01UL << GPIO_PORT_SET7_SETP26_Pos)                     /*!< GPIO_PORT SET7: SETP26 Mask         */
+#define GPIO_PORT_SET7_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET7: SETP27 Position     */
+#define GPIO_PORT_SET7_SETP27_Msk                             (0x01UL << GPIO_PORT_SET7_SETP27_Pos)                     /*!< GPIO_PORT SET7: SETP27 Mask         */
+#define GPIO_PORT_SET7_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET7: SETP28 Position     */
+#define GPIO_PORT_SET7_SETP28_Msk                             (0x01UL << GPIO_PORT_SET7_SETP28_Pos)                     /*!< GPIO_PORT SET7: SETP28 Mask         */
+#define GPIO_PORT_SET7_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET7: SETP29 Position     */
+#define GPIO_PORT_SET7_SETP29_Msk                             (0x01UL << GPIO_PORT_SET7_SETP29_Pos)                     /*!< GPIO_PORT SET7: SETP29 Mask         */
+#define GPIO_PORT_SET7_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET7: SETP30 Position     */
+#define GPIO_PORT_SET7_SETP30_Msk                             (0x01UL << GPIO_PORT_SET7_SETP30_Pos)                     /*!< GPIO_PORT SET7: SETP30 Mask         */
+#define GPIO_PORT_SET7_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET7: SETP31 Position     */
+#define GPIO_PORT_SET7_SETP31_Msk                             (0x01UL << GPIO_PORT_SET7_SETP31_Pos)                     /*!< GPIO_PORT SET7: SETP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_CLR0  -----------------------------------------
+#define GPIO_PORT_CLR0_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR0: CLRP00 Position     */
+#define GPIO_PORT_CLR0_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos)                     /*!< GPIO_PORT CLR0: CLRP00 Mask         */
+#define GPIO_PORT_CLR0_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR0: CLRP01 Position     */
+#define GPIO_PORT_CLR0_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos)                     /*!< GPIO_PORT CLR0: CLRP01 Mask         */
+#define GPIO_PORT_CLR0_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR0: CLRP02 Position     */
+#define GPIO_PORT_CLR0_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos)                     /*!< GPIO_PORT CLR0: CLRP02 Mask         */
+#define GPIO_PORT_CLR0_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR0: CLRP03 Position     */
+#define GPIO_PORT_CLR0_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos)                     /*!< GPIO_PORT CLR0: CLRP03 Mask         */
+#define GPIO_PORT_CLR0_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR0: CLRP04 Position     */
+#define GPIO_PORT_CLR0_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos)                     /*!< GPIO_PORT CLR0: CLRP04 Mask         */
+#define GPIO_PORT_CLR0_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR0: CLRP05 Position     */
+#define GPIO_PORT_CLR0_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos)                     /*!< GPIO_PORT CLR0: CLRP05 Mask         */
+#define GPIO_PORT_CLR0_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR0: CLRP06 Position     */
+#define GPIO_PORT_CLR0_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos)                     /*!< GPIO_PORT CLR0: CLRP06 Mask         */
+#define GPIO_PORT_CLR0_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR0: CLRP07 Position     */
+#define GPIO_PORT_CLR0_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos)                     /*!< GPIO_PORT CLR0: CLRP07 Mask         */
+#define GPIO_PORT_CLR0_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR0: CLRP08 Position     */
+#define GPIO_PORT_CLR0_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos)                     /*!< GPIO_PORT CLR0: CLRP08 Mask         */
+#define GPIO_PORT_CLR0_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR0: CLRP09 Position     */
+#define GPIO_PORT_CLR0_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos)                     /*!< GPIO_PORT CLR0: CLRP09 Mask         */
+#define GPIO_PORT_CLR0_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR0: CLRP010 Position    */
+#define GPIO_PORT_CLR0_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos)                    /*!< GPIO_PORT CLR0: CLRP010 Mask        */
+#define GPIO_PORT_CLR0_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR0: CLRP011 Position    */
+#define GPIO_PORT_CLR0_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos)                    /*!< GPIO_PORT CLR0: CLRP011 Mask        */
+#define GPIO_PORT_CLR0_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR0: CLRP012 Position    */
+#define GPIO_PORT_CLR0_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos)                    /*!< GPIO_PORT CLR0: CLRP012 Mask        */
+#define GPIO_PORT_CLR0_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR0: CLRP013 Position    */
+#define GPIO_PORT_CLR0_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos)                    /*!< GPIO_PORT CLR0: CLRP013 Mask        */
+#define GPIO_PORT_CLR0_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR0: CLRP014 Position    */
+#define GPIO_PORT_CLR0_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos)                    /*!< GPIO_PORT CLR0: CLRP014 Mask        */
+#define GPIO_PORT_CLR0_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR0: CLRP015 Position    */
+#define GPIO_PORT_CLR0_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos)                    /*!< GPIO_PORT CLR0: CLRP015 Mask        */
+#define GPIO_PORT_CLR0_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR0: CLRP016 Position    */
+#define GPIO_PORT_CLR0_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos)                    /*!< GPIO_PORT CLR0: CLRP016 Mask        */
+#define GPIO_PORT_CLR0_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR0: CLRP017 Position    */
+#define GPIO_PORT_CLR0_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos)                    /*!< GPIO_PORT CLR0: CLRP017 Mask        */
+#define GPIO_PORT_CLR0_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR0: CLRP018 Position    */
+#define GPIO_PORT_CLR0_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos)                    /*!< GPIO_PORT CLR0: CLRP018 Mask        */
+#define GPIO_PORT_CLR0_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR0: CLRP019 Position    */
+#define GPIO_PORT_CLR0_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos)                    /*!< GPIO_PORT CLR0: CLRP019 Mask        */
+#define GPIO_PORT_CLR0_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR0: CLRP020 Position    */
+#define GPIO_PORT_CLR0_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos)                    /*!< GPIO_PORT CLR0: CLRP020 Mask        */
+#define GPIO_PORT_CLR0_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR0: CLRP021 Position    */
+#define GPIO_PORT_CLR0_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos)                    /*!< GPIO_PORT CLR0: CLRP021 Mask        */
+#define GPIO_PORT_CLR0_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR0: CLRP022 Position    */
+#define GPIO_PORT_CLR0_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos)                    /*!< GPIO_PORT CLR0: CLRP022 Mask        */
+#define GPIO_PORT_CLR0_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR0: CLRP023 Position    */
+#define GPIO_PORT_CLR0_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos)                    /*!< GPIO_PORT CLR0: CLRP023 Mask        */
+#define GPIO_PORT_CLR0_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR0: CLRP024 Position    */
+#define GPIO_PORT_CLR0_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos)                    /*!< GPIO_PORT CLR0: CLRP024 Mask        */
+#define GPIO_PORT_CLR0_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR0: CLRP025 Position    */
+#define GPIO_PORT_CLR0_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos)                    /*!< GPIO_PORT CLR0: CLRP025 Mask        */
+#define GPIO_PORT_CLR0_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR0: CLRP026 Position    */
+#define GPIO_PORT_CLR0_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos)                    /*!< GPIO_PORT CLR0: CLRP026 Mask        */
+#define GPIO_PORT_CLR0_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR0: CLRP027 Position    */
+#define GPIO_PORT_CLR0_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos)                    /*!< GPIO_PORT CLR0: CLRP027 Mask        */
+#define GPIO_PORT_CLR0_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR0: CLRP028 Position    */
+#define GPIO_PORT_CLR0_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos)                    /*!< GPIO_PORT CLR0: CLRP028 Mask        */
+#define GPIO_PORT_CLR0_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR0: CLRP029 Position    */
+#define GPIO_PORT_CLR0_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos)                    /*!< GPIO_PORT CLR0: CLRP029 Mask        */
+#define GPIO_PORT_CLR0_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR0: CLRP030 Position    */
+#define GPIO_PORT_CLR0_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos)                    /*!< GPIO_PORT CLR0: CLRP030 Mask        */
+#define GPIO_PORT_CLR0_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR0: CLRP031 Position    */
+#define GPIO_PORT_CLR0_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos)                    /*!< GPIO_PORT CLR0: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR1  -----------------------------------------
+#define GPIO_PORT_CLR1_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR1: CLRP00 Position     */
+#define GPIO_PORT_CLR1_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos)                     /*!< GPIO_PORT CLR1: CLRP00 Mask         */
+#define GPIO_PORT_CLR1_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR1: CLRP01 Position     */
+#define GPIO_PORT_CLR1_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos)                     /*!< GPIO_PORT CLR1: CLRP01 Mask         */
+#define GPIO_PORT_CLR1_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR1: CLRP02 Position     */
+#define GPIO_PORT_CLR1_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos)                     /*!< GPIO_PORT CLR1: CLRP02 Mask         */
+#define GPIO_PORT_CLR1_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR1: CLRP03 Position     */
+#define GPIO_PORT_CLR1_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos)                     /*!< GPIO_PORT CLR1: CLRP03 Mask         */
+#define GPIO_PORT_CLR1_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR1: CLRP04 Position     */
+#define GPIO_PORT_CLR1_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos)                     /*!< GPIO_PORT CLR1: CLRP04 Mask         */
+#define GPIO_PORT_CLR1_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR1: CLRP05 Position     */
+#define GPIO_PORT_CLR1_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos)                     /*!< GPIO_PORT CLR1: CLRP05 Mask         */
+#define GPIO_PORT_CLR1_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR1: CLRP06 Position     */
+#define GPIO_PORT_CLR1_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos)                     /*!< GPIO_PORT CLR1: CLRP06 Mask         */
+#define GPIO_PORT_CLR1_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR1: CLRP07 Position     */
+#define GPIO_PORT_CLR1_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos)                     /*!< GPIO_PORT CLR1: CLRP07 Mask         */
+#define GPIO_PORT_CLR1_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR1: CLRP08 Position     */
+#define GPIO_PORT_CLR1_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos)                     /*!< GPIO_PORT CLR1: CLRP08 Mask         */
+#define GPIO_PORT_CLR1_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR1: CLRP09 Position     */
+#define GPIO_PORT_CLR1_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos)                     /*!< GPIO_PORT CLR1: CLRP09 Mask         */
+#define GPIO_PORT_CLR1_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR1: CLRP010 Position    */
+#define GPIO_PORT_CLR1_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos)                    /*!< GPIO_PORT CLR1: CLRP010 Mask        */
+#define GPIO_PORT_CLR1_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR1: CLRP011 Position    */
+#define GPIO_PORT_CLR1_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos)                    /*!< GPIO_PORT CLR1: CLRP011 Mask        */
+#define GPIO_PORT_CLR1_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR1: CLRP012 Position    */
+#define GPIO_PORT_CLR1_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos)                    /*!< GPIO_PORT CLR1: CLRP012 Mask        */
+#define GPIO_PORT_CLR1_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR1: CLRP013 Position    */
+#define GPIO_PORT_CLR1_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos)                    /*!< GPIO_PORT CLR1: CLRP013 Mask        */
+#define GPIO_PORT_CLR1_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR1: CLRP014 Position    */
+#define GPIO_PORT_CLR1_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos)                    /*!< GPIO_PORT CLR1: CLRP014 Mask        */
+#define GPIO_PORT_CLR1_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR1: CLRP015 Position    */
+#define GPIO_PORT_CLR1_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos)                    /*!< GPIO_PORT CLR1: CLRP015 Mask        */
+#define GPIO_PORT_CLR1_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR1: CLRP016 Position    */
+#define GPIO_PORT_CLR1_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos)                    /*!< GPIO_PORT CLR1: CLRP016 Mask        */
+#define GPIO_PORT_CLR1_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR1: CLRP017 Position    */
+#define GPIO_PORT_CLR1_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos)                    /*!< GPIO_PORT CLR1: CLRP017 Mask        */
+#define GPIO_PORT_CLR1_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR1: CLRP018 Position    */
+#define GPIO_PORT_CLR1_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos)                    /*!< GPIO_PORT CLR1: CLRP018 Mask        */
+#define GPIO_PORT_CLR1_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR1: CLRP019 Position    */
+#define GPIO_PORT_CLR1_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos)                    /*!< GPIO_PORT CLR1: CLRP019 Mask        */
+#define GPIO_PORT_CLR1_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR1: CLRP020 Position    */
+#define GPIO_PORT_CLR1_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos)                    /*!< GPIO_PORT CLR1: CLRP020 Mask        */
+#define GPIO_PORT_CLR1_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR1: CLRP021 Position    */
+#define GPIO_PORT_CLR1_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos)                    /*!< GPIO_PORT CLR1: CLRP021 Mask        */
+#define GPIO_PORT_CLR1_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR1: CLRP022 Position    */
+#define GPIO_PORT_CLR1_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos)                    /*!< GPIO_PORT CLR1: CLRP022 Mask        */
+#define GPIO_PORT_CLR1_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR1: CLRP023 Position    */
+#define GPIO_PORT_CLR1_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos)                    /*!< GPIO_PORT CLR1: CLRP023 Mask        */
+#define GPIO_PORT_CLR1_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR1: CLRP024 Position    */
+#define GPIO_PORT_CLR1_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos)                    /*!< GPIO_PORT CLR1: CLRP024 Mask        */
+#define GPIO_PORT_CLR1_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR1: CLRP025 Position    */
+#define GPIO_PORT_CLR1_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos)                    /*!< GPIO_PORT CLR1: CLRP025 Mask        */
+#define GPIO_PORT_CLR1_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR1: CLRP026 Position    */
+#define GPIO_PORT_CLR1_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos)                    /*!< GPIO_PORT CLR1: CLRP026 Mask        */
+#define GPIO_PORT_CLR1_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR1: CLRP027 Position    */
+#define GPIO_PORT_CLR1_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos)                    /*!< GPIO_PORT CLR1: CLRP027 Mask        */
+#define GPIO_PORT_CLR1_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR1: CLRP028 Position    */
+#define GPIO_PORT_CLR1_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos)                    /*!< GPIO_PORT CLR1: CLRP028 Mask        */
+#define GPIO_PORT_CLR1_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR1: CLRP029 Position    */
+#define GPIO_PORT_CLR1_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos)                    /*!< GPIO_PORT CLR1: CLRP029 Mask        */
+#define GPIO_PORT_CLR1_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR1: CLRP030 Position    */
+#define GPIO_PORT_CLR1_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos)                    /*!< GPIO_PORT CLR1: CLRP030 Mask        */
+#define GPIO_PORT_CLR1_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR1: CLRP031 Position    */
+#define GPIO_PORT_CLR1_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos)                    /*!< GPIO_PORT CLR1: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR2  -----------------------------------------
+#define GPIO_PORT_CLR2_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR2: CLRP00 Position     */
+#define GPIO_PORT_CLR2_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos)                     /*!< GPIO_PORT CLR2: CLRP00 Mask         */
+#define GPIO_PORT_CLR2_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR2: CLRP01 Position     */
+#define GPIO_PORT_CLR2_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos)                     /*!< GPIO_PORT CLR2: CLRP01 Mask         */
+#define GPIO_PORT_CLR2_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR2: CLRP02 Position     */
+#define GPIO_PORT_CLR2_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos)                     /*!< GPIO_PORT CLR2: CLRP02 Mask         */
+#define GPIO_PORT_CLR2_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR2: CLRP03 Position     */
+#define GPIO_PORT_CLR2_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos)                     /*!< GPIO_PORT CLR2: CLRP03 Mask         */
+#define GPIO_PORT_CLR2_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR2: CLRP04 Position     */
+#define GPIO_PORT_CLR2_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos)                     /*!< GPIO_PORT CLR2: CLRP04 Mask         */
+#define GPIO_PORT_CLR2_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR2: CLRP05 Position     */
+#define GPIO_PORT_CLR2_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos)                     /*!< GPIO_PORT CLR2: CLRP05 Mask         */
+#define GPIO_PORT_CLR2_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR2: CLRP06 Position     */
+#define GPIO_PORT_CLR2_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos)                     /*!< GPIO_PORT CLR2: CLRP06 Mask         */
+#define GPIO_PORT_CLR2_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR2: CLRP07 Position     */
+#define GPIO_PORT_CLR2_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos)                     /*!< GPIO_PORT CLR2: CLRP07 Mask         */
+#define GPIO_PORT_CLR2_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR2: CLRP08 Position     */
+#define GPIO_PORT_CLR2_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos)                     /*!< GPIO_PORT CLR2: CLRP08 Mask         */
+#define GPIO_PORT_CLR2_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR2: CLRP09 Position     */
+#define GPIO_PORT_CLR2_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos)                     /*!< GPIO_PORT CLR2: CLRP09 Mask         */
+#define GPIO_PORT_CLR2_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR2: CLRP010 Position    */
+#define GPIO_PORT_CLR2_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos)                    /*!< GPIO_PORT CLR2: CLRP010 Mask        */
+#define GPIO_PORT_CLR2_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR2: CLRP011 Position    */
+#define GPIO_PORT_CLR2_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos)                    /*!< GPIO_PORT CLR2: CLRP011 Mask        */
+#define GPIO_PORT_CLR2_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR2: CLRP012 Position    */
+#define GPIO_PORT_CLR2_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos)                    /*!< GPIO_PORT CLR2: CLRP012 Mask        */
+#define GPIO_PORT_CLR2_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR2: CLRP013 Position    */
+#define GPIO_PORT_CLR2_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos)                    /*!< GPIO_PORT CLR2: CLRP013 Mask        */
+#define GPIO_PORT_CLR2_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR2: CLRP014 Position    */
+#define GPIO_PORT_CLR2_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos)                    /*!< GPIO_PORT CLR2: CLRP014 Mask        */
+#define GPIO_PORT_CLR2_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR2: CLRP015 Position    */
+#define GPIO_PORT_CLR2_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos)                    /*!< GPIO_PORT CLR2: CLRP015 Mask        */
+#define GPIO_PORT_CLR2_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR2: CLRP016 Position    */
+#define GPIO_PORT_CLR2_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos)                    /*!< GPIO_PORT CLR2: CLRP016 Mask        */
+#define GPIO_PORT_CLR2_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR2: CLRP017 Position    */
+#define GPIO_PORT_CLR2_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos)                    /*!< GPIO_PORT CLR2: CLRP017 Mask        */
+#define GPIO_PORT_CLR2_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR2: CLRP018 Position    */
+#define GPIO_PORT_CLR2_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos)                    /*!< GPIO_PORT CLR2: CLRP018 Mask        */
+#define GPIO_PORT_CLR2_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR2: CLRP019 Position    */
+#define GPIO_PORT_CLR2_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos)                    /*!< GPIO_PORT CLR2: CLRP019 Mask        */
+#define GPIO_PORT_CLR2_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR2: CLRP020 Position    */
+#define GPIO_PORT_CLR2_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos)                    /*!< GPIO_PORT CLR2: CLRP020 Mask        */
+#define GPIO_PORT_CLR2_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR2: CLRP021 Position    */
+#define GPIO_PORT_CLR2_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos)                    /*!< GPIO_PORT CLR2: CLRP021 Mask        */
+#define GPIO_PORT_CLR2_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR2: CLRP022 Position    */
+#define GPIO_PORT_CLR2_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos)                    /*!< GPIO_PORT CLR2: CLRP022 Mask        */
+#define GPIO_PORT_CLR2_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR2: CLRP023 Position    */
+#define GPIO_PORT_CLR2_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos)                    /*!< GPIO_PORT CLR2: CLRP023 Mask        */
+#define GPIO_PORT_CLR2_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR2: CLRP024 Position    */
+#define GPIO_PORT_CLR2_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos)                    /*!< GPIO_PORT CLR2: CLRP024 Mask        */
+#define GPIO_PORT_CLR2_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR2: CLRP025 Position    */
+#define GPIO_PORT_CLR2_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos)                    /*!< GPIO_PORT CLR2: CLRP025 Mask        */
+#define GPIO_PORT_CLR2_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR2: CLRP026 Position    */
+#define GPIO_PORT_CLR2_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos)                    /*!< GPIO_PORT CLR2: CLRP026 Mask        */
+#define GPIO_PORT_CLR2_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR2: CLRP027 Position    */
+#define GPIO_PORT_CLR2_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos)                    /*!< GPIO_PORT CLR2: CLRP027 Mask        */
+#define GPIO_PORT_CLR2_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR2: CLRP028 Position    */
+#define GPIO_PORT_CLR2_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos)                    /*!< GPIO_PORT CLR2: CLRP028 Mask        */
+#define GPIO_PORT_CLR2_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR2: CLRP029 Position    */
+#define GPIO_PORT_CLR2_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos)                    /*!< GPIO_PORT CLR2: CLRP029 Mask        */
+#define GPIO_PORT_CLR2_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR2: CLRP030 Position    */
+#define GPIO_PORT_CLR2_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos)                    /*!< GPIO_PORT CLR2: CLRP030 Mask        */
+#define GPIO_PORT_CLR2_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR2: CLRP031 Position    */
+#define GPIO_PORT_CLR2_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos)                    /*!< GPIO_PORT CLR2: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR3  -----------------------------------------
+#define GPIO_PORT_CLR3_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR3: CLRP00 Position     */
+#define GPIO_PORT_CLR3_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos)                     /*!< GPIO_PORT CLR3: CLRP00 Mask         */
+#define GPIO_PORT_CLR3_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR3: CLRP01 Position     */
+#define GPIO_PORT_CLR3_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos)                     /*!< GPIO_PORT CLR3: CLRP01 Mask         */
+#define GPIO_PORT_CLR3_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR3: CLRP02 Position     */
+#define GPIO_PORT_CLR3_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos)                     /*!< GPIO_PORT CLR3: CLRP02 Mask         */
+#define GPIO_PORT_CLR3_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR3: CLRP03 Position     */
+#define GPIO_PORT_CLR3_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos)                     /*!< GPIO_PORT CLR3: CLRP03 Mask         */
+#define GPIO_PORT_CLR3_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR3: CLRP04 Position     */
+#define GPIO_PORT_CLR3_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos)                     /*!< GPIO_PORT CLR3: CLRP04 Mask         */
+#define GPIO_PORT_CLR3_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR3: CLRP05 Position     */
+#define GPIO_PORT_CLR3_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos)                     /*!< GPIO_PORT CLR3: CLRP05 Mask         */
+#define GPIO_PORT_CLR3_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR3: CLRP06 Position     */
+#define GPIO_PORT_CLR3_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos)                     /*!< GPIO_PORT CLR3: CLRP06 Mask         */
+#define GPIO_PORT_CLR3_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR3: CLRP07 Position     */
+#define GPIO_PORT_CLR3_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos)                     /*!< GPIO_PORT CLR3: CLRP07 Mask         */
+#define GPIO_PORT_CLR3_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR3: CLRP08 Position     */
+#define GPIO_PORT_CLR3_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos)                     /*!< GPIO_PORT CLR3: CLRP08 Mask         */
+#define GPIO_PORT_CLR3_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR3: CLRP09 Position     */
+#define GPIO_PORT_CLR3_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos)                     /*!< GPIO_PORT CLR3: CLRP09 Mask         */
+#define GPIO_PORT_CLR3_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR3: CLRP010 Position    */
+#define GPIO_PORT_CLR3_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos)                    /*!< GPIO_PORT CLR3: CLRP010 Mask        */
+#define GPIO_PORT_CLR3_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR3: CLRP011 Position    */
+#define GPIO_PORT_CLR3_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos)                    /*!< GPIO_PORT CLR3: CLRP011 Mask        */
+#define GPIO_PORT_CLR3_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR3: CLRP012 Position    */
+#define GPIO_PORT_CLR3_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos)                    /*!< GPIO_PORT CLR3: CLRP012 Mask        */
+#define GPIO_PORT_CLR3_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR3: CLRP013 Position    */
+#define GPIO_PORT_CLR3_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos)                    /*!< GPIO_PORT CLR3: CLRP013 Mask        */
+#define GPIO_PORT_CLR3_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR3: CLRP014 Position    */
+#define GPIO_PORT_CLR3_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos)                    /*!< GPIO_PORT CLR3: CLRP014 Mask        */
+#define GPIO_PORT_CLR3_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR3: CLRP015 Position    */
+#define GPIO_PORT_CLR3_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos)                    /*!< GPIO_PORT CLR3: CLRP015 Mask        */
+#define GPIO_PORT_CLR3_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR3: CLRP016 Position    */
+#define GPIO_PORT_CLR3_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos)                    /*!< GPIO_PORT CLR3: CLRP016 Mask        */
+#define GPIO_PORT_CLR3_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR3: CLRP017 Position    */
+#define GPIO_PORT_CLR3_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos)                    /*!< GPIO_PORT CLR3: CLRP017 Mask        */
+#define GPIO_PORT_CLR3_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR3: CLRP018 Position    */
+#define GPIO_PORT_CLR3_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos)                    /*!< GPIO_PORT CLR3: CLRP018 Mask        */
+#define GPIO_PORT_CLR3_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR3: CLRP019 Position    */
+#define GPIO_PORT_CLR3_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos)                    /*!< GPIO_PORT CLR3: CLRP019 Mask        */
+#define GPIO_PORT_CLR3_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR3: CLRP020 Position    */
+#define GPIO_PORT_CLR3_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos)                    /*!< GPIO_PORT CLR3: CLRP020 Mask        */
+#define GPIO_PORT_CLR3_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR3: CLRP021 Position    */
+#define GPIO_PORT_CLR3_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos)                    /*!< GPIO_PORT CLR3: CLRP021 Mask        */
+#define GPIO_PORT_CLR3_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR3: CLRP022 Position    */
+#define GPIO_PORT_CLR3_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos)                    /*!< GPIO_PORT CLR3: CLRP022 Mask        */
+#define GPIO_PORT_CLR3_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR3: CLRP023 Position    */
+#define GPIO_PORT_CLR3_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos)                    /*!< GPIO_PORT CLR3: CLRP023 Mask        */
+#define GPIO_PORT_CLR3_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR3: CLRP024 Position    */
+#define GPIO_PORT_CLR3_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos)                    /*!< GPIO_PORT CLR3: CLRP024 Mask        */
+#define GPIO_PORT_CLR3_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR3: CLRP025 Position    */
+#define GPIO_PORT_CLR3_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos)                    /*!< GPIO_PORT CLR3: CLRP025 Mask        */
+#define GPIO_PORT_CLR3_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR3: CLRP026 Position    */
+#define GPIO_PORT_CLR3_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos)                    /*!< GPIO_PORT CLR3: CLRP026 Mask        */
+#define GPIO_PORT_CLR3_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR3: CLRP027 Position    */
+#define GPIO_PORT_CLR3_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos)                    /*!< GPIO_PORT CLR3: CLRP027 Mask        */
+#define GPIO_PORT_CLR3_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR3: CLRP028 Position    */
+#define GPIO_PORT_CLR3_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos)                    /*!< GPIO_PORT CLR3: CLRP028 Mask        */
+#define GPIO_PORT_CLR3_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR3: CLRP029 Position    */
+#define GPIO_PORT_CLR3_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos)                    /*!< GPIO_PORT CLR3: CLRP029 Mask        */
+#define GPIO_PORT_CLR3_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR3: CLRP030 Position    */
+#define GPIO_PORT_CLR3_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos)                    /*!< GPIO_PORT CLR3: CLRP030 Mask        */
+#define GPIO_PORT_CLR3_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR3: CLRP031 Position    */
+#define GPIO_PORT_CLR3_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos)                    /*!< GPIO_PORT CLR3: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR4  -----------------------------------------
+#define GPIO_PORT_CLR4_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR4: CLRP00 Position     */
+#define GPIO_PORT_CLR4_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos)                     /*!< GPIO_PORT CLR4: CLRP00 Mask         */
+#define GPIO_PORT_CLR4_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR4: CLRP01 Position     */
+#define GPIO_PORT_CLR4_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos)                     /*!< GPIO_PORT CLR4: CLRP01 Mask         */
+#define GPIO_PORT_CLR4_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR4: CLRP02 Position     */
+#define GPIO_PORT_CLR4_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos)                     /*!< GPIO_PORT CLR4: CLRP02 Mask         */
+#define GPIO_PORT_CLR4_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR4: CLRP03 Position     */
+#define GPIO_PORT_CLR4_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos)                     /*!< GPIO_PORT CLR4: CLRP03 Mask         */
+#define GPIO_PORT_CLR4_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR4: CLRP04 Position     */
+#define GPIO_PORT_CLR4_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos)                     /*!< GPIO_PORT CLR4: CLRP04 Mask         */
+#define GPIO_PORT_CLR4_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR4: CLRP05 Position     */
+#define GPIO_PORT_CLR4_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos)                     /*!< GPIO_PORT CLR4: CLRP05 Mask         */
+#define GPIO_PORT_CLR4_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR4: CLRP06 Position     */
+#define GPIO_PORT_CLR4_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos)                     /*!< GPIO_PORT CLR4: CLRP06 Mask         */
+#define GPIO_PORT_CLR4_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR4: CLRP07 Position     */
+#define GPIO_PORT_CLR4_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos)                     /*!< GPIO_PORT CLR4: CLRP07 Mask         */
+#define GPIO_PORT_CLR4_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR4: CLRP08 Position     */
+#define GPIO_PORT_CLR4_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos)                     /*!< GPIO_PORT CLR4: CLRP08 Mask         */
+#define GPIO_PORT_CLR4_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR4: CLRP09 Position     */
+#define GPIO_PORT_CLR4_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos)                     /*!< GPIO_PORT CLR4: CLRP09 Mask         */
+#define GPIO_PORT_CLR4_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR4: CLRP010 Position    */
+#define GPIO_PORT_CLR4_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos)                    /*!< GPIO_PORT CLR4: CLRP010 Mask        */
+#define GPIO_PORT_CLR4_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR4: CLRP011 Position    */
+#define GPIO_PORT_CLR4_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos)                    /*!< GPIO_PORT CLR4: CLRP011 Mask        */
+#define GPIO_PORT_CLR4_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR4: CLRP012 Position    */
+#define GPIO_PORT_CLR4_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos)                    /*!< GPIO_PORT CLR4: CLRP012 Mask        */
+#define GPIO_PORT_CLR4_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR4: CLRP013 Position    */
+#define GPIO_PORT_CLR4_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos)                    /*!< GPIO_PORT CLR4: CLRP013 Mask        */
+#define GPIO_PORT_CLR4_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR4: CLRP014 Position    */
+#define GPIO_PORT_CLR4_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos)                    /*!< GPIO_PORT CLR4: CLRP014 Mask        */
+#define GPIO_PORT_CLR4_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR4: CLRP015 Position    */
+#define GPIO_PORT_CLR4_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos)                    /*!< GPIO_PORT CLR4: CLRP015 Mask        */
+#define GPIO_PORT_CLR4_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR4: CLRP016 Position    */
+#define GPIO_PORT_CLR4_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos)                    /*!< GPIO_PORT CLR4: CLRP016 Mask        */
+#define GPIO_PORT_CLR4_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR4: CLRP017 Position    */
+#define GPIO_PORT_CLR4_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos)                    /*!< GPIO_PORT CLR4: CLRP017 Mask        */
+#define GPIO_PORT_CLR4_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR4: CLRP018 Position    */
+#define GPIO_PORT_CLR4_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos)                    /*!< GPIO_PORT CLR4: CLRP018 Mask        */
+#define GPIO_PORT_CLR4_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR4: CLRP019 Position    */
+#define GPIO_PORT_CLR4_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos)                    /*!< GPIO_PORT CLR4: CLRP019 Mask        */
+#define GPIO_PORT_CLR4_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR4: CLRP020 Position    */
+#define GPIO_PORT_CLR4_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos)                    /*!< GPIO_PORT CLR4: CLRP020 Mask        */
+#define GPIO_PORT_CLR4_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR4: CLRP021 Position    */
+#define GPIO_PORT_CLR4_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos)                    /*!< GPIO_PORT CLR4: CLRP021 Mask        */
+#define GPIO_PORT_CLR4_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR4: CLRP022 Position    */
+#define GPIO_PORT_CLR4_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos)                    /*!< GPIO_PORT CLR4: CLRP022 Mask        */
+#define GPIO_PORT_CLR4_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR4: CLRP023 Position    */
+#define GPIO_PORT_CLR4_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos)                    /*!< GPIO_PORT CLR4: CLRP023 Mask        */
+#define GPIO_PORT_CLR4_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR4: CLRP024 Position    */
+#define GPIO_PORT_CLR4_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos)                    /*!< GPIO_PORT CLR4: CLRP024 Mask        */
+#define GPIO_PORT_CLR4_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR4: CLRP025 Position    */
+#define GPIO_PORT_CLR4_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos)                    /*!< GPIO_PORT CLR4: CLRP025 Mask        */
+#define GPIO_PORT_CLR4_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR4: CLRP026 Position    */
+#define GPIO_PORT_CLR4_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos)                    /*!< GPIO_PORT CLR4: CLRP026 Mask        */
+#define GPIO_PORT_CLR4_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR4: CLRP027 Position    */
+#define GPIO_PORT_CLR4_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos)                    /*!< GPIO_PORT CLR4: CLRP027 Mask        */
+#define GPIO_PORT_CLR4_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR4: CLRP028 Position    */
+#define GPIO_PORT_CLR4_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos)                    /*!< GPIO_PORT CLR4: CLRP028 Mask        */
+#define GPIO_PORT_CLR4_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR4: CLRP029 Position    */
+#define GPIO_PORT_CLR4_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos)                    /*!< GPIO_PORT CLR4: CLRP029 Mask        */
+#define GPIO_PORT_CLR4_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR4: CLRP030 Position    */
+#define GPIO_PORT_CLR4_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos)                    /*!< GPIO_PORT CLR4: CLRP030 Mask        */
+#define GPIO_PORT_CLR4_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR4: CLRP031 Position    */
+#define GPIO_PORT_CLR4_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos)                    /*!< GPIO_PORT CLR4: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR5  -----------------------------------------
+#define GPIO_PORT_CLR5_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR5: CLRP00 Position     */
+#define GPIO_PORT_CLR5_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos)                     /*!< GPIO_PORT CLR5: CLRP00 Mask         */
+#define GPIO_PORT_CLR5_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR5: CLRP01 Position     */
+#define GPIO_PORT_CLR5_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos)                     /*!< GPIO_PORT CLR5: CLRP01 Mask         */
+#define GPIO_PORT_CLR5_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR5: CLRP02 Position     */
+#define GPIO_PORT_CLR5_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos)                     /*!< GPIO_PORT CLR5: CLRP02 Mask         */
+#define GPIO_PORT_CLR5_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR5: CLRP03 Position     */
+#define GPIO_PORT_CLR5_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos)                     /*!< GPIO_PORT CLR5: CLRP03 Mask         */
+#define GPIO_PORT_CLR5_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR5: CLRP04 Position     */
+#define GPIO_PORT_CLR5_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos)                     /*!< GPIO_PORT CLR5: CLRP04 Mask         */
+#define GPIO_PORT_CLR5_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR5: CLRP05 Position     */
+#define GPIO_PORT_CLR5_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos)                     /*!< GPIO_PORT CLR5: CLRP05 Mask         */
+#define GPIO_PORT_CLR5_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR5: CLRP06 Position     */
+#define GPIO_PORT_CLR5_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos)                     /*!< GPIO_PORT CLR5: CLRP06 Mask         */
+#define GPIO_PORT_CLR5_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR5: CLRP07 Position     */
+#define GPIO_PORT_CLR5_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos)                     /*!< GPIO_PORT CLR5: CLRP07 Mask         */
+#define GPIO_PORT_CLR5_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR5: CLRP08 Position     */
+#define GPIO_PORT_CLR5_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos)                     /*!< GPIO_PORT CLR5: CLRP08 Mask         */
+#define GPIO_PORT_CLR5_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR5: CLRP09 Position     */
+#define GPIO_PORT_CLR5_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos)                     /*!< GPIO_PORT CLR5: CLRP09 Mask         */
+#define GPIO_PORT_CLR5_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR5: CLRP010 Position    */
+#define GPIO_PORT_CLR5_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos)                    /*!< GPIO_PORT CLR5: CLRP010 Mask        */
+#define GPIO_PORT_CLR5_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR5: CLRP011 Position    */
+#define GPIO_PORT_CLR5_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos)                    /*!< GPIO_PORT CLR5: CLRP011 Mask        */
+#define GPIO_PORT_CLR5_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR5: CLRP012 Position    */
+#define GPIO_PORT_CLR5_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos)                    /*!< GPIO_PORT CLR5: CLRP012 Mask        */
+#define GPIO_PORT_CLR5_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR5: CLRP013 Position    */
+#define GPIO_PORT_CLR5_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos)                    /*!< GPIO_PORT CLR5: CLRP013 Mask        */
+#define GPIO_PORT_CLR5_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR5: CLRP014 Position    */
+#define GPIO_PORT_CLR5_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos)                    /*!< GPIO_PORT CLR5: CLRP014 Mask        */
+#define GPIO_PORT_CLR5_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR5: CLRP015 Position    */
+#define GPIO_PORT_CLR5_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos)                    /*!< GPIO_PORT CLR5: CLRP015 Mask        */
+#define GPIO_PORT_CLR5_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR5: CLRP016 Position    */
+#define GPIO_PORT_CLR5_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos)                    /*!< GPIO_PORT CLR5: CLRP016 Mask        */
+#define GPIO_PORT_CLR5_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR5: CLRP017 Position    */
+#define GPIO_PORT_CLR5_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos)                    /*!< GPIO_PORT CLR5: CLRP017 Mask        */
+#define GPIO_PORT_CLR5_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR5: CLRP018 Position    */
+#define GPIO_PORT_CLR5_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos)                    /*!< GPIO_PORT CLR5: CLRP018 Mask        */
+#define GPIO_PORT_CLR5_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR5: CLRP019 Position    */
+#define GPIO_PORT_CLR5_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos)                    /*!< GPIO_PORT CLR5: CLRP019 Mask        */
+#define GPIO_PORT_CLR5_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR5: CLRP020 Position    */
+#define GPIO_PORT_CLR5_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos)                    /*!< GPIO_PORT CLR5: CLRP020 Mask        */
+#define GPIO_PORT_CLR5_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR5: CLRP021 Position    */
+#define GPIO_PORT_CLR5_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos)                    /*!< GPIO_PORT CLR5: CLRP021 Mask        */
+#define GPIO_PORT_CLR5_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR5: CLRP022 Position    */
+#define GPIO_PORT_CLR5_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos)                    /*!< GPIO_PORT CLR5: CLRP022 Mask        */
+#define GPIO_PORT_CLR5_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR5: CLRP023 Position    */
+#define GPIO_PORT_CLR5_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos)                    /*!< GPIO_PORT CLR5: CLRP023 Mask        */
+#define GPIO_PORT_CLR5_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR5: CLRP024 Position    */
+#define GPIO_PORT_CLR5_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos)                    /*!< GPIO_PORT CLR5: CLRP024 Mask        */
+#define GPIO_PORT_CLR5_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR5: CLRP025 Position    */
+#define GPIO_PORT_CLR5_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos)                    /*!< GPIO_PORT CLR5: CLRP025 Mask        */
+#define GPIO_PORT_CLR5_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR5: CLRP026 Position    */
+#define GPIO_PORT_CLR5_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos)                    /*!< GPIO_PORT CLR5: CLRP026 Mask        */
+#define GPIO_PORT_CLR5_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR5: CLRP027 Position    */
+#define GPIO_PORT_CLR5_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos)                    /*!< GPIO_PORT CLR5: CLRP027 Mask        */
+#define GPIO_PORT_CLR5_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR5: CLRP028 Position    */
+#define GPIO_PORT_CLR5_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos)                    /*!< GPIO_PORT CLR5: CLRP028 Mask        */
+#define GPIO_PORT_CLR5_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR5: CLRP029 Position    */
+#define GPIO_PORT_CLR5_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos)                    /*!< GPIO_PORT CLR5: CLRP029 Mask        */
+#define GPIO_PORT_CLR5_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR5: CLRP030 Position    */
+#define GPIO_PORT_CLR5_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos)                    /*!< GPIO_PORT CLR5: CLRP030 Mask        */
+#define GPIO_PORT_CLR5_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR5: CLRP031 Position    */
+#define GPIO_PORT_CLR5_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos)                    /*!< GPIO_PORT CLR5: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR6  -----------------------------------------
+#define GPIO_PORT_CLR6_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR6: CLRP00 Position     */
+#define GPIO_PORT_CLR6_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos)                     /*!< GPIO_PORT CLR6: CLRP00 Mask         */
+#define GPIO_PORT_CLR6_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR6: CLRP01 Position     */
+#define GPIO_PORT_CLR6_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos)                     /*!< GPIO_PORT CLR6: CLRP01 Mask         */
+#define GPIO_PORT_CLR6_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR6: CLRP02 Position     */
+#define GPIO_PORT_CLR6_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos)                     /*!< GPIO_PORT CLR6: CLRP02 Mask         */
+#define GPIO_PORT_CLR6_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR6: CLRP03 Position     */
+#define GPIO_PORT_CLR6_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos)                     /*!< GPIO_PORT CLR6: CLRP03 Mask         */
+#define GPIO_PORT_CLR6_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR6: CLRP04 Position     */
+#define GPIO_PORT_CLR6_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos)                     /*!< GPIO_PORT CLR6: CLRP04 Mask         */
+#define GPIO_PORT_CLR6_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR6: CLRP05 Position     */
+#define GPIO_PORT_CLR6_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos)                     /*!< GPIO_PORT CLR6: CLRP05 Mask         */
+#define GPIO_PORT_CLR6_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR6: CLRP06 Position     */
+#define GPIO_PORT_CLR6_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos)                     /*!< GPIO_PORT CLR6: CLRP06 Mask         */
+#define GPIO_PORT_CLR6_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR6: CLRP07 Position     */
+#define GPIO_PORT_CLR6_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos)                     /*!< GPIO_PORT CLR6: CLRP07 Mask         */
+#define GPIO_PORT_CLR6_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR6: CLRP08 Position     */
+#define GPIO_PORT_CLR6_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos)                     /*!< GPIO_PORT CLR6: CLRP08 Mask         */
+#define GPIO_PORT_CLR6_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR6: CLRP09 Position     */
+#define GPIO_PORT_CLR6_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos)                     /*!< GPIO_PORT CLR6: CLRP09 Mask         */
+#define GPIO_PORT_CLR6_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR6: CLRP010 Position    */
+#define GPIO_PORT_CLR6_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos)                    /*!< GPIO_PORT CLR6: CLRP010 Mask        */
+#define GPIO_PORT_CLR6_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR6: CLRP011 Position    */
+#define GPIO_PORT_CLR6_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos)                    /*!< GPIO_PORT CLR6: CLRP011 Mask        */
+#define GPIO_PORT_CLR6_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR6: CLRP012 Position    */
+#define GPIO_PORT_CLR6_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos)                    /*!< GPIO_PORT CLR6: CLRP012 Mask        */
+#define GPIO_PORT_CLR6_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR6: CLRP013 Position    */
+#define GPIO_PORT_CLR6_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos)                    /*!< GPIO_PORT CLR6: CLRP013 Mask        */
+#define GPIO_PORT_CLR6_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR6: CLRP014 Position    */
+#define GPIO_PORT_CLR6_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos)                    /*!< GPIO_PORT CLR6: CLRP014 Mask        */
+#define GPIO_PORT_CLR6_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR6: CLRP015 Position    */
+#define GPIO_PORT_CLR6_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos)                    /*!< GPIO_PORT CLR6: CLRP015 Mask        */
+#define GPIO_PORT_CLR6_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR6: CLRP016 Position    */
+#define GPIO_PORT_CLR6_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos)                    /*!< GPIO_PORT CLR6: CLRP016 Mask        */
+#define GPIO_PORT_CLR6_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR6: CLRP017 Position    */
+#define GPIO_PORT_CLR6_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos)                    /*!< GPIO_PORT CLR6: CLRP017 Mask        */
+#define GPIO_PORT_CLR6_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR6: CLRP018 Position    */
+#define GPIO_PORT_CLR6_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos)                    /*!< GPIO_PORT CLR6: CLRP018 Mask        */
+#define GPIO_PORT_CLR6_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR6: CLRP019 Position    */
+#define GPIO_PORT_CLR6_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos)                    /*!< GPIO_PORT CLR6: CLRP019 Mask        */
+#define GPIO_PORT_CLR6_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR6: CLRP020 Position    */
+#define GPIO_PORT_CLR6_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos)                    /*!< GPIO_PORT CLR6: CLRP020 Mask        */
+#define GPIO_PORT_CLR6_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR6: CLRP021 Position    */
+#define GPIO_PORT_CLR6_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos)                    /*!< GPIO_PORT CLR6: CLRP021 Mask        */
+#define GPIO_PORT_CLR6_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR6: CLRP022 Position    */
+#define GPIO_PORT_CLR6_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos)                    /*!< GPIO_PORT CLR6: CLRP022 Mask        */
+#define GPIO_PORT_CLR6_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR6: CLRP023 Position    */
+#define GPIO_PORT_CLR6_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos)                    /*!< GPIO_PORT CLR6: CLRP023 Mask        */
+#define GPIO_PORT_CLR6_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR6: CLRP024 Position    */
+#define GPIO_PORT_CLR6_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos)                    /*!< GPIO_PORT CLR6: CLRP024 Mask        */
+#define GPIO_PORT_CLR6_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR6: CLRP025 Position    */
+#define GPIO_PORT_CLR6_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos)                    /*!< GPIO_PORT CLR6: CLRP025 Mask        */
+#define GPIO_PORT_CLR6_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR6: CLRP026 Position    */
+#define GPIO_PORT_CLR6_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos)                    /*!< GPIO_PORT CLR6: CLRP026 Mask        */
+#define GPIO_PORT_CLR6_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR6: CLRP027 Position    */
+#define GPIO_PORT_CLR6_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos)                    /*!< GPIO_PORT CLR6: CLRP027 Mask        */
+#define GPIO_PORT_CLR6_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR6: CLRP028 Position    */
+#define GPIO_PORT_CLR6_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos)                    /*!< GPIO_PORT CLR6: CLRP028 Mask        */
+#define GPIO_PORT_CLR6_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR6: CLRP029 Position    */
+#define GPIO_PORT_CLR6_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos)                    /*!< GPIO_PORT CLR6: CLRP029 Mask        */
+#define GPIO_PORT_CLR6_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR6: CLRP030 Position    */
+#define GPIO_PORT_CLR6_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos)                    /*!< GPIO_PORT CLR6: CLRP030 Mask        */
+#define GPIO_PORT_CLR6_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR6: CLRP031 Position    */
+#define GPIO_PORT_CLR6_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos)                    /*!< GPIO_PORT CLR6: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_CLR7  -----------------------------------------
+#define GPIO_PORT_CLR7_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR7: CLRP00 Position     */
+#define GPIO_PORT_CLR7_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos)                     /*!< GPIO_PORT CLR7: CLRP00 Mask         */
+#define GPIO_PORT_CLR7_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR7: CLRP01 Position     */
+#define GPIO_PORT_CLR7_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos)                     /*!< GPIO_PORT CLR7: CLRP01 Mask         */
+#define GPIO_PORT_CLR7_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR7: CLRP02 Position     */
+#define GPIO_PORT_CLR7_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos)                     /*!< GPIO_PORT CLR7: CLRP02 Mask         */
+#define GPIO_PORT_CLR7_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR7: CLRP03 Position     */
+#define GPIO_PORT_CLR7_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos)                     /*!< GPIO_PORT CLR7: CLRP03 Mask         */
+#define GPIO_PORT_CLR7_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR7: CLRP04 Position     */
+#define GPIO_PORT_CLR7_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos)                     /*!< GPIO_PORT CLR7: CLRP04 Mask         */
+#define GPIO_PORT_CLR7_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR7: CLRP05 Position     */
+#define GPIO_PORT_CLR7_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos)                     /*!< GPIO_PORT CLR7: CLRP05 Mask         */
+#define GPIO_PORT_CLR7_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR7: CLRP06 Position     */
+#define GPIO_PORT_CLR7_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos)                     /*!< GPIO_PORT CLR7: CLRP06 Mask         */
+#define GPIO_PORT_CLR7_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR7: CLRP07 Position     */
+#define GPIO_PORT_CLR7_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos)                     /*!< GPIO_PORT CLR7: CLRP07 Mask         */
+#define GPIO_PORT_CLR7_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR7: CLRP08 Position     */
+#define GPIO_PORT_CLR7_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos)                     /*!< GPIO_PORT CLR7: CLRP08 Mask         */
+#define GPIO_PORT_CLR7_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR7: CLRP09 Position     */
+#define GPIO_PORT_CLR7_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos)                     /*!< GPIO_PORT CLR7: CLRP09 Mask         */
+#define GPIO_PORT_CLR7_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR7: CLRP010 Position    */
+#define GPIO_PORT_CLR7_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos)                    /*!< GPIO_PORT CLR7: CLRP010 Mask        */
+#define GPIO_PORT_CLR7_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR7: CLRP011 Position    */
+#define GPIO_PORT_CLR7_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos)                    /*!< GPIO_PORT CLR7: CLRP011 Mask        */
+#define GPIO_PORT_CLR7_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR7: CLRP012 Position    */
+#define GPIO_PORT_CLR7_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos)                    /*!< GPIO_PORT CLR7: CLRP012 Mask        */
+#define GPIO_PORT_CLR7_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR7: CLRP013 Position    */
+#define GPIO_PORT_CLR7_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos)                    /*!< GPIO_PORT CLR7: CLRP013 Mask        */
+#define GPIO_PORT_CLR7_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR7: CLRP014 Position    */
+#define GPIO_PORT_CLR7_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos)                    /*!< GPIO_PORT CLR7: CLRP014 Mask        */
+#define GPIO_PORT_CLR7_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR7: CLRP015 Position    */
+#define GPIO_PORT_CLR7_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos)                    /*!< GPIO_PORT CLR7: CLRP015 Mask        */
+#define GPIO_PORT_CLR7_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR7: CLRP016 Position    */
+#define GPIO_PORT_CLR7_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos)                    /*!< GPIO_PORT CLR7: CLRP016 Mask        */
+#define GPIO_PORT_CLR7_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR7: CLRP017 Position    */
+#define GPIO_PORT_CLR7_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos)                    /*!< GPIO_PORT CLR7: CLRP017 Mask        */
+#define GPIO_PORT_CLR7_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR7: CLRP018 Position    */
+#define GPIO_PORT_CLR7_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos)                    /*!< GPIO_PORT CLR7: CLRP018 Mask        */
+#define GPIO_PORT_CLR7_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR7: CLRP019 Position    */
+#define GPIO_PORT_CLR7_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos)                    /*!< GPIO_PORT CLR7: CLRP019 Mask        */
+#define GPIO_PORT_CLR7_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR7: CLRP020 Position    */
+#define GPIO_PORT_CLR7_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos)                    /*!< GPIO_PORT CLR7: CLRP020 Mask        */
+#define GPIO_PORT_CLR7_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR7: CLRP021 Position    */
+#define GPIO_PORT_CLR7_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos)                    /*!< GPIO_PORT CLR7: CLRP021 Mask        */
+#define GPIO_PORT_CLR7_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR7: CLRP022 Position    */
+#define GPIO_PORT_CLR7_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos)                    /*!< GPIO_PORT CLR7: CLRP022 Mask        */
+#define GPIO_PORT_CLR7_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR7: CLRP023 Position    */
+#define GPIO_PORT_CLR7_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos)                    /*!< GPIO_PORT CLR7: CLRP023 Mask        */
+#define GPIO_PORT_CLR7_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR7: CLRP024 Position    */
+#define GPIO_PORT_CLR7_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos)                    /*!< GPIO_PORT CLR7: CLRP024 Mask        */
+#define GPIO_PORT_CLR7_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR7: CLRP025 Position    */
+#define GPIO_PORT_CLR7_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos)                    /*!< GPIO_PORT CLR7: CLRP025 Mask        */
+#define GPIO_PORT_CLR7_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR7: CLRP026 Position    */
+#define GPIO_PORT_CLR7_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos)                    /*!< GPIO_PORT CLR7: CLRP026 Mask        */
+#define GPIO_PORT_CLR7_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR7: CLRP027 Position    */
+#define GPIO_PORT_CLR7_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos)                    /*!< GPIO_PORT CLR7: CLRP027 Mask        */
+#define GPIO_PORT_CLR7_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR7: CLRP028 Position    */
+#define GPIO_PORT_CLR7_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos)                    /*!< GPIO_PORT CLR7: CLRP028 Mask        */
+#define GPIO_PORT_CLR7_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR7: CLRP029 Position    */
+#define GPIO_PORT_CLR7_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos)                    /*!< GPIO_PORT CLR7: CLRP029 Mask        */
+#define GPIO_PORT_CLR7_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR7: CLRP030 Position    */
+#define GPIO_PORT_CLR7_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos)                    /*!< GPIO_PORT CLR7: CLRP030 Mask        */
+#define GPIO_PORT_CLR7_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR7: CLRP031 Position    */
+#define GPIO_PORT_CLR7_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos)                    /*!< GPIO_PORT CLR7: CLRP031 Mask        */
+
+// -------------------------------------  GPIO_PORT_NOT0  -----------------------------------------
+#define GPIO_PORT_NOT0_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT0: NOTP0 Position      */
+#define GPIO_PORT_NOT0_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos)                      /*!< GPIO_PORT NOT0: NOTP0 Mask          */
+#define GPIO_PORT_NOT0_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT0: NOTP1 Position      */
+#define GPIO_PORT_NOT0_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos)                      /*!< GPIO_PORT NOT0: NOTP1 Mask          */
+#define GPIO_PORT_NOT0_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT0: NOTP2 Position      */
+#define GPIO_PORT_NOT0_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos)                      /*!< GPIO_PORT NOT0: NOTP2 Mask          */
+#define GPIO_PORT_NOT0_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT0: NOTP3 Position      */
+#define GPIO_PORT_NOT0_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos)                      /*!< GPIO_PORT NOT0: NOTP3 Mask          */
+#define GPIO_PORT_NOT0_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT0: NOTP4 Position      */
+#define GPIO_PORT_NOT0_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos)                      /*!< GPIO_PORT NOT0: NOTP4 Mask          */
+#define GPIO_PORT_NOT0_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT0: NOTP5 Position      */
+#define GPIO_PORT_NOT0_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos)                      /*!< GPIO_PORT NOT0: NOTP5 Mask          */
+#define GPIO_PORT_NOT0_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT0: NOTP6 Position      */
+#define GPIO_PORT_NOT0_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos)                      /*!< GPIO_PORT NOT0: NOTP6 Mask          */
+#define GPIO_PORT_NOT0_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT0: NOTP7 Position      */
+#define GPIO_PORT_NOT0_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos)                      /*!< GPIO_PORT NOT0: NOTP7 Mask          */
+#define GPIO_PORT_NOT0_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT0: NOTP8 Position      */
+#define GPIO_PORT_NOT0_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos)                      /*!< GPIO_PORT NOT0: NOTP8 Mask          */
+#define GPIO_PORT_NOT0_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT0: NOTP9 Position      */
+#define GPIO_PORT_NOT0_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos)                      /*!< GPIO_PORT NOT0: NOTP9 Mask          */
+#define GPIO_PORT_NOT0_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT0: NOTP10 Position     */
+#define GPIO_PORT_NOT0_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos)                     /*!< GPIO_PORT NOT0: NOTP10 Mask         */
+#define GPIO_PORT_NOT0_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT0: NOTP11 Position     */
+#define GPIO_PORT_NOT0_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos)                     /*!< GPIO_PORT NOT0: NOTP11 Mask         */
+#define GPIO_PORT_NOT0_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT0: NOTP12 Position     */
+#define GPIO_PORT_NOT0_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos)                     /*!< GPIO_PORT NOT0: NOTP12 Mask         */
+#define GPIO_PORT_NOT0_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT0: NOTP13 Position     */
+#define GPIO_PORT_NOT0_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos)                     /*!< GPIO_PORT NOT0: NOTP13 Mask         */
+#define GPIO_PORT_NOT0_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT0: NOTP14 Position     */
+#define GPIO_PORT_NOT0_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos)                     /*!< GPIO_PORT NOT0: NOTP14 Mask         */
+#define GPIO_PORT_NOT0_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT0: NOTP15 Position     */
+#define GPIO_PORT_NOT0_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos)                     /*!< GPIO_PORT NOT0: NOTP15 Mask         */
+#define GPIO_PORT_NOT0_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT0: NOTP16 Position     */
+#define GPIO_PORT_NOT0_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos)                     /*!< GPIO_PORT NOT0: NOTP16 Mask         */
+#define GPIO_PORT_NOT0_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT0: NOTP17 Position     */
+#define GPIO_PORT_NOT0_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos)                     /*!< GPIO_PORT NOT0: NOTP17 Mask         */
+#define GPIO_PORT_NOT0_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT0: NOTP18 Position     */
+#define GPIO_PORT_NOT0_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos)                     /*!< GPIO_PORT NOT0: NOTP18 Mask         */
+#define GPIO_PORT_NOT0_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT0: NOTP19 Position     */
+#define GPIO_PORT_NOT0_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos)                     /*!< GPIO_PORT NOT0: NOTP19 Mask         */
+#define GPIO_PORT_NOT0_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT0: NOTP20 Position     */
+#define GPIO_PORT_NOT0_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos)                     /*!< GPIO_PORT NOT0: NOTP20 Mask         */
+#define GPIO_PORT_NOT0_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT0: NOTP21 Position     */
+#define GPIO_PORT_NOT0_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos)                     /*!< GPIO_PORT NOT0: NOTP21 Mask         */
+#define GPIO_PORT_NOT0_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT0: NOTP22 Position     */
+#define GPIO_PORT_NOT0_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos)                     /*!< GPIO_PORT NOT0: NOTP22 Mask         */
+#define GPIO_PORT_NOT0_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT0: NOTP23 Position     */
+#define GPIO_PORT_NOT0_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos)                     /*!< GPIO_PORT NOT0: NOTP23 Mask         */
+#define GPIO_PORT_NOT0_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT0: NOTP24 Position     */
+#define GPIO_PORT_NOT0_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos)                     /*!< GPIO_PORT NOT0: NOTP24 Mask         */
+#define GPIO_PORT_NOT0_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT0: NOTP25 Position     */
+#define GPIO_PORT_NOT0_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos)                     /*!< GPIO_PORT NOT0: NOTP25 Mask         */
+#define GPIO_PORT_NOT0_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT0: NOTP26 Position     */
+#define GPIO_PORT_NOT0_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos)                     /*!< GPIO_PORT NOT0: NOTP26 Mask         */
+#define GPIO_PORT_NOT0_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT0: NOTP27 Position     */
+#define GPIO_PORT_NOT0_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos)                     /*!< GPIO_PORT NOT0: NOTP27 Mask         */
+#define GPIO_PORT_NOT0_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT0: NOTP28 Position     */
+#define GPIO_PORT_NOT0_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos)                     /*!< GPIO_PORT NOT0: NOTP28 Mask         */
+#define GPIO_PORT_NOT0_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT0: NOTP29 Position     */
+#define GPIO_PORT_NOT0_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos)                     /*!< GPIO_PORT NOT0: NOTP29 Mask         */
+#define GPIO_PORT_NOT0_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT0: NOTP30 Position     */
+#define GPIO_PORT_NOT0_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos)                     /*!< GPIO_PORT NOT0: NOTP30 Mask         */
+#define GPIO_PORT_NOT0_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT0: NOTP31 Position     */
+#define GPIO_PORT_NOT0_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos)                     /*!< GPIO_PORT NOT0: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT1  -----------------------------------------
+#define GPIO_PORT_NOT1_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT1: NOTP0 Position      */
+#define GPIO_PORT_NOT1_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos)                      /*!< GPIO_PORT NOT1: NOTP0 Mask          */
+#define GPIO_PORT_NOT1_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT1: NOTP1 Position      */
+#define GPIO_PORT_NOT1_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos)                      /*!< GPIO_PORT NOT1: NOTP1 Mask          */
+#define GPIO_PORT_NOT1_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT1: NOTP2 Position      */
+#define GPIO_PORT_NOT1_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos)                      /*!< GPIO_PORT NOT1: NOTP2 Mask          */
+#define GPIO_PORT_NOT1_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT1: NOTP3 Position      */
+#define GPIO_PORT_NOT1_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos)                      /*!< GPIO_PORT NOT1: NOTP3 Mask          */
+#define GPIO_PORT_NOT1_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT1: NOTP4 Position      */
+#define GPIO_PORT_NOT1_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos)                      /*!< GPIO_PORT NOT1: NOTP4 Mask          */
+#define GPIO_PORT_NOT1_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT1: NOTP5 Position      */
+#define GPIO_PORT_NOT1_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos)                      /*!< GPIO_PORT NOT1: NOTP5 Mask          */
+#define GPIO_PORT_NOT1_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT1: NOTP6 Position      */
+#define GPIO_PORT_NOT1_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos)                      /*!< GPIO_PORT NOT1: NOTP6 Mask          */
+#define GPIO_PORT_NOT1_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT1: NOTP7 Position      */
+#define GPIO_PORT_NOT1_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos)                      /*!< GPIO_PORT NOT1: NOTP7 Mask          */
+#define GPIO_PORT_NOT1_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT1: NOTP8 Position      */
+#define GPIO_PORT_NOT1_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos)                      /*!< GPIO_PORT NOT1: NOTP8 Mask          */
+#define GPIO_PORT_NOT1_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT1: NOTP9 Position      */
+#define GPIO_PORT_NOT1_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos)                      /*!< GPIO_PORT NOT1: NOTP9 Mask          */
+#define GPIO_PORT_NOT1_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT1: NOTP10 Position     */
+#define GPIO_PORT_NOT1_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos)                     /*!< GPIO_PORT NOT1: NOTP10 Mask         */
+#define GPIO_PORT_NOT1_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT1: NOTP11 Position     */
+#define GPIO_PORT_NOT1_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos)                     /*!< GPIO_PORT NOT1: NOTP11 Mask         */
+#define GPIO_PORT_NOT1_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT1: NOTP12 Position     */
+#define GPIO_PORT_NOT1_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos)                     /*!< GPIO_PORT NOT1: NOTP12 Mask         */
+#define GPIO_PORT_NOT1_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT1: NOTP13 Position     */
+#define GPIO_PORT_NOT1_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos)                     /*!< GPIO_PORT NOT1: NOTP13 Mask         */
+#define GPIO_PORT_NOT1_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT1: NOTP14 Position     */
+#define GPIO_PORT_NOT1_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos)                     /*!< GPIO_PORT NOT1: NOTP14 Mask         */
+#define GPIO_PORT_NOT1_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT1: NOTP15 Position     */
+#define GPIO_PORT_NOT1_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos)                     /*!< GPIO_PORT NOT1: NOTP15 Mask         */
+#define GPIO_PORT_NOT1_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT1: NOTP16 Position     */
+#define GPIO_PORT_NOT1_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos)                     /*!< GPIO_PORT NOT1: NOTP16 Mask         */
+#define GPIO_PORT_NOT1_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT1: NOTP17 Position     */
+#define GPIO_PORT_NOT1_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos)                     /*!< GPIO_PORT NOT1: NOTP17 Mask         */
+#define GPIO_PORT_NOT1_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT1: NOTP18 Position     */
+#define GPIO_PORT_NOT1_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos)                     /*!< GPIO_PORT NOT1: NOTP18 Mask         */
+#define GPIO_PORT_NOT1_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT1: NOTP19 Position     */
+#define GPIO_PORT_NOT1_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos)                     /*!< GPIO_PORT NOT1: NOTP19 Mask         */
+#define GPIO_PORT_NOT1_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT1: NOTP20 Position     */
+#define GPIO_PORT_NOT1_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos)                     /*!< GPIO_PORT NOT1: NOTP20 Mask         */
+#define GPIO_PORT_NOT1_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT1: NOTP21 Position     */
+#define GPIO_PORT_NOT1_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos)                     /*!< GPIO_PORT NOT1: NOTP21 Mask         */
+#define GPIO_PORT_NOT1_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT1: NOTP22 Position     */
+#define GPIO_PORT_NOT1_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos)                     /*!< GPIO_PORT NOT1: NOTP22 Mask         */
+#define GPIO_PORT_NOT1_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT1: NOTP23 Position     */
+#define GPIO_PORT_NOT1_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos)                     /*!< GPIO_PORT NOT1: NOTP23 Mask         */
+#define GPIO_PORT_NOT1_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT1: NOTP24 Position     */
+#define GPIO_PORT_NOT1_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos)                     /*!< GPIO_PORT NOT1: NOTP24 Mask         */
+#define GPIO_PORT_NOT1_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT1: NOTP25 Position     */
+#define GPIO_PORT_NOT1_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos)                     /*!< GPIO_PORT NOT1: NOTP25 Mask         */
+#define GPIO_PORT_NOT1_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT1: NOTP26 Position     */
+#define GPIO_PORT_NOT1_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos)                     /*!< GPIO_PORT NOT1: NOTP26 Mask         */
+#define GPIO_PORT_NOT1_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT1: NOTP27 Position     */
+#define GPIO_PORT_NOT1_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos)                     /*!< GPIO_PORT NOT1: NOTP27 Mask         */
+#define GPIO_PORT_NOT1_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT1: NOTP28 Position     */
+#define GPIO_PORT_NOT1_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos)                     /*!< GPIO_PORT NOT1: NOTP28 Mask         */
+#define GPIO_PORT_NOT1_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT1: NOTP29 Position     */
+#define GPIO_PORT_NOT1_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos)                     /*!< GPIO_PORT NOT1: NOTP29 Mask         */
+#define GPIO_PORT_NOT1_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT1: NOTP30 Position     */
+#define GPIO_PORT_NOT1_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos)                     /*!< GPIO_PORT NOT1: NOTP30 Mask         */
+#define GPIO_PORT_NOT1_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT1: NOTP31 Position     */
+#define GPIO_PORT_NOT1_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos)                     /*!< GPIO_PORT NOT1: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT2  -----------------------------------------
+#define GPIO_PORT_NOT2_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT2: NOTP0 Position      */
+#define GPIO_PORT_NOT2_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos)                      /*!< GPIO_PORT NOT2: NOTP0 Mask          */
+#define GPIO_PORT_NOT2_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT2: NOTP1 Position      */
+#define GPIO_PORT_NOT2_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos)                      /*!< GPIO_PORT NOT2: NOTP1 Mask          */
+#define GPIO_PORT_NOT2_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT2: NOTP2 Position      */
+#define GPIO_PORT_NOT2_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos)                      /*!< GPIO_PORT NOT2: NOTP2 Mask          */
+#define GPIO_PORT_NOT2_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT2: NOTP3 Position      */
+#define GPIO_PORT_NOT2_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos)                      /*!< GPIO_PORT NOT2: NOTP3 Mask          */
+#define GPIO_PORT_NOT2_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT2: NOTP4 Position      */
+#define GPIO_PORT_NOT2_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos)                      /*!< GPIO_PORT NOT2: NOTP4 Mask          */
+#define GPIO_PORT_NOT2_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT2: NOTP5 Position      */
+#define GPIO_PORT_NOT2_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos)                      /*!< GPIO_PORT NOT2: NOTP5 Mask          */
+#define GPIO_PORT_NOT2_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT2: NOTP6 Position      */
+#define GPIO_PORT_NOT2_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos)                      /*!< GPIO_PORT NOT2: NOTP6 Mask          */
+#define GPIO_PORT_NOT2_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT2: NOTP7 Position      */
+#define GPIO_PORT_NOT2_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos)                      /*!< GPIO_PORT NOT2: NOTP7 Mask          */
+#define GPIO_PORT_NOT2_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT2: NOTP8 Position      */
+#define GPIO_PORT_NOT2_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos)                      /*!< GPIO_PORT NOT2: NOTP8 Mask          */
+#define GPIO_PORT_NOT2_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT2: NOTP9 Position      */
+#define GPIO_PORT_NOT2_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos)                      /*!< GPIO_PORT NOT2: NOTP9 Mask          */
+#define GPIO_PORT_NOT2_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT2: NOTP10 Position     */
+#define GPIO_PORT_NOT2_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos)                     /*!< GPIO_PORT NOT2: NOTP10 Mask         */
+#define GPIO_PORT_NOT2_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT2: NOTP11 Position     */
+#define GPIO_PORT_NOT2_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos)                     /*!< GPIO_PORT NOT2: NOTP11 Mask         */
+#define GPIO_PORT_NOT2_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT2: NOTP12 Position     */
+#define GPIO_PORT_NOT2_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos)                     /*!< GPIO_PORT NOT2: NOTP12 Mask         */
+#define GPIO_PORT_NOT2_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT2: NOTP13 Position     */
+#define GPIO_PORT_NOT2_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos)                     /*!< GPIO_PORT NOT2: NOTP13 Mask         */
+#define GPIO_PORT_NOT2_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT2: NOTP14 Position     */
+#define GPIO_PORT_NOT2_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos)                     /*!< GPIO_PORT NOT2: NOTP14 Mask         */
+#define GPIO_PORT_NOT2_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT2: NOTP15 Position     */
+#define GPIO_PORT_NOT2_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos)                     /*!< GPIO_PORT NOT2: NOTP15 Mask         */
+#define GPIO_PORT_NOT2_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT2: NOTP16 Position     */
+#define GPIO_PORT_NOT2_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos)                     /*!< GPIO_PORT NOT2: NOTP16 Mask         */
+#define GPIO_PORT_NOT2_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT2: NOTP17 Position     */
+#define GPIO_PORT_NOT2_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos)                     /*!< GPIO_PORT NOT2: NOTP17 Mask         */
+#define GPIO_PORT_NOT2_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT2: NOTP18 Position     */
+#define GPIO_PORT_NOT2_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos)                     /*!< GPIO_PORT NOT2: NOTP18 Mask         */
+#define GPIO_PORT_NOT2_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT2: NOTP19 Position     */
+#define GPIO_PORT_NOT2_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos)                     /*!< GPIO_PORT NOT2: NOTP19 Mask         */
+#define GPIO_PORT_NOT2_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT2: NOTP20 Position     */
+#define GPIO_PORT_NOT2_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos)                     /*!< GPIO_PORT NOT2: NOTP20 Mask         */
+#define GPIO_PORT_NOT2_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT2: NOTP21 Position     */
+#define GPIO_PORT_NOT2_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos)                     /*!< GPIO_PORT NOT2: NOTP21 Mask         */
+#define GPIO_PORT_NOT2_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT2: NOTP22 Position     */
+#define GPIO_PORT_NOT2_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos)                     /*!< GPIO_PORT NOT2: NOTP22 Mask         */
+#define GPIO_PORT_NOT2_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT2: NOTP23 Position     */
+#define GPIO_PORT_NOT2_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos)                     /*!< GPIO_PORT NOT2: NOTP23 Mask         */
+#define GPIO_PORT_NOT2_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT2: NOTP24 Position     */
+#define GPIO_PORT_NOT2_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos)                     /*!< GPIO_PORT NOT2: NOTP24 Mask         */
+#define GPIO_PORT_NOT2_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT2: NOTP25 Position     */
+#define GPIO_PORT_NOT2_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos)                     /*!< GPIO_PORT NOT2: NOTP25 Mask         */
+#define GPIO_PORT_NOT2_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT2: NOTP26 Position     */
+#define GPIO_PORT_NOT2_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos)                     /*!< GPIO_PORT NOT2: NOTP26 Mask         */
+#define GPIO_PORT_NOT2_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT2: NOTP27 Position     */
+#define GPIO_PORT_NOT2_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos)                     /*!< GPIO_PORT NOT2: NOTP27 Mask         */
+#define GPIO_PORT_NOT2_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT2: NOTP28 Position     */
+#define GPIO_PORT_NOT2_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos)                     /*!< GPIO_PORT NOT2: NOTP28 Mask         */
+#define GPIO_PORT_NOT2_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT2: NOTP29 Position     */
+#define GPIO_PORT_NOT2_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos)                     /*!< GPIO_PORT NOT2: NOTP29 Mask         */
+#define GPIO_PORT_NOT2_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT2: NOTP30 Position     */
+#define GPIO_PORT_NOT2_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos)                     /*!< GPIO_PORT NOT2: NOTP30 Mask         */
+#define GPIO_PORT_NOT2_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT2: NOTP31 Position     */
+#define GPIO_PORT_NOT2_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos)                     /*!< GPIO_PORT NOT2: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT3  -----------------------------------------
+#define GPIO_PORT_NOT3_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT3: NOTP0 Position      */
+#define GPIO_PORT_NOT3_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos)                      /*!< GPIO_PORT NOT3: NOTP0 Mask          */
+#define GPIO_PORT_NOT3_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT3: NOTP1 Position      */
+#define GPIO_PORT_NOT3_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos)                      /*!< GPIO_PORT NOT3: NOTP1 Mask          */
+#define GPIO_PORT_NOT3_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT3: NOTP2 Position      */
+#define GPIO_PORT_NOT3_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos)                      /*!< GPIO_PORT NOT3: NOTP2 Mask          */
+#define GPIO_PORT_NOT3_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT3: NOTP3 Position      */
+#define GPIO_PORT_NOT3_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos)                      /*!< GPIO_PORT NOT3: NOTP3 Mask          */
+#define GPIO_PORT_NOT3_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT3: NOTP4 Position      */
+#define GPIO_PORT_NOT3_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos)                      /*!< GPIO_PORT NOT3: NOTP4 Mask          */
+#define GPIO_PORT_NOT3_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT3: NOTP5 Position      */
+#define GPIO_PORT_NOT3_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos)                      /*!< GPIO_PORT NOT3: NOTP5 Mask          */
+#define GPIO_PORT_NOT3_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT3: NOTP6 Position      */
+#define GPIO_PORT_NOT3_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos)                      /*!< GPIO_PORT NOT3: NOTP6 Mask          */
+#define GPIO_PORT_NOT3_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT3: NOTP7 Position      */
+#define GPIO_PORT_NOT3_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos)                      /*!< GPIO_PORT NOT3: NOTP7 Mask          */
+#define GPIO_PORT_NOT3_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT3: NOTP8 Position      */
+#define GPIO_PORT_NOT3_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos)                      /*!< GPIO_PORT NOT3: NOTP8 Mask          */
+#define GPIO_PORT_NOT3_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT3: NOTP9 Position      */
+#define GPIO_PORT_NOT3_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos)                      /*!< GPIO_PORT NOT3: NOTP9 Mask          */
+#define GPIO_PORT_NOT3_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT3: NOTP10 Position     */
+#define GPIO_PORT_NOT3_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos)                     /*!< GPIO_PORT NOT3: NOTP10 Mask         */
+#define GPIO_PORT_NOT3_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT3: NOTP11 Position     */
+#define GPIO_PORT_NOT3_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos)                     /*!< GPIO_PORT NOT3: NOTP11 Mask         */
+#define GPIO_PORT_NOT3_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT3: NOTP12 Position     */
+#define GPIO_PORT_NOT3_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos)                     /*!< GPIO_PORT NOT3: NOTP12 Mask         */
+#define GPIO_PORT_NOT3_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT3: NOTP13 Position     */
+#define GPIO_PORT_NOT3_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos)                     /*!< GPIO_PORT NOT3: NOTP13 Mask         */
+#define GPIO_PORT_NOT3_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT3: NOTP14 Position     */
+#define GPIO_PORT_NOT3_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos)                     /*!< GPIO_PORT NOT3: NOTP14 Mask         */
+#define GPIO_PORT_NOT3_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT3: NOTP15 Position     */
+#define GPIO_PORT_NOT3_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos)                     /*!< GPIO_PORT NOT3: NOTP15 Mask         */
+#define GPIO_PORT_NOT3_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT3: NOTP16 Position     */
+#define GPIO_PORT_NOT3_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos)                     /*!< GPIO_PORT NOT3: NOTP16 Mask         */
+#define GPIO_PORT_NOT3_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT3: NOTP17 Position     */
+#define GPIO_PORT_NOT3_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos)                     /*!< GPIO_PORT NOT3: NOTP17 Mask         */
+#define GPIO_PORT_NOT3_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT3: NOTP18 Position     */
+#define GPIO_PORT_NOT3_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos)                     /*!< GPIO_PORT NOT3: NOTP18 Mask         */
+#define GPIO_PORT_NOT3_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT3: NOTP19 Position     */
+#define GPIO_PORT_NOT3_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos)                     /*!< GPIO_PORT NOT3: NOTP19 Mask         */
+#define GPIO_PORT_NOT3_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT3: NOTP20 Position     */
+#define GPIO_PORT_NOT3_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos)                     /*!< GPIO_PORT NOT3: NOTP20 Mask         */
+#define GPIO_PORT_NOT3_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT3: NOTP21 Position     */
+#define GPIO_PORT_NOT3_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos)                     /*!< GPIO_PORT NOT3: NOTP21 Mask         */
+#define GPIO_PORT_NOT3_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT3: NOTP22 Position     */
+#define GPIO_PORT_NOT3_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos)                     /*!< GPIO_PORT NOT3: NOTP22 Mask         */
+#define GPIO_PORT_NOT3_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT3: NOTP23 Position     */
+#define GPIO_PORT_NOT3_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos)                     /*!< GPIO_PORT NOT3: NOTP23 Mask         */
+#define GPIO_PORT_NOT3_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT3: NOTP24 Position     */
+#define GPIO_PORT_NOT3_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos)                     /*!< GPIO_PORT NOT3: NOTP24 Mask         */
+#define GPIO_PORT_NOT3_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT3: NOTP25 Position     */
+#define GPIO_PORT_NOT3_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos)                     /*!< GPIO_PORT NOT3: NOTP25 Mask         */
+#define GPIO_PORT_NOT3_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT3: NOTP26 Position     */
+#define GPIO_PORT_NOT3_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos)                     /*!< GPIO_PORT NOT3: NOTP26 Mask         */
+#define GPIO_PORT_NOT3_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT3: NOTP27 Position     */
+#define GPIO_PORT_NOT3_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos)                     /*!< GPIO_PORT NOT3: NOTP27 Mask         */
+#define GPIO_PORT_NOT3_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT3: NOTP28 Position     */
+#define GPIO_PORT_NOT3_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos)                     /*!< GPIO_PORT NOT3: NOTP28 Mask         */
+#define GPIO_PORT_NOT3_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT3: NOTP29 Position     */
+#define GPIO_PORT_NOT3_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos)                     /*!< GPIO_PORT NOT3: NOTP29 Mask         */
+#define GPIO_PORT_NOT3_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT3: NOTP30 Position     */
+#define GPIO_PORT_NOT3_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos)                     /*!< GPIO_PORT NOT3: NOTP30 Mask         */
+#define GPIO_PORT_NOT3_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT3: NOTP31 Position     */
+#define GPIO_PORT_NOT3_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos)                     /*!< GPIO_PORT NOT3: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT4  -----------------------------------------
+#define GPIO_PORT_NOT4_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT4: NOTP0 Position      */
+#define GPIO_PORT_NOT4_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos)                      /*!< GPIO_PORT NOT4: NOTP0 Mask          */
+#define GPIO_PORT_NOT4_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT4: NOTP1 Position      */
+#define GPIO_PORT_NOT4_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos)                      /*!< GPIO_PORT NOT4: NOTP1 Mask          */
+#define GPIO_PORT_NOT4_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT4: NOTP2 Position      */
+#define GPIO_PORT_NOT4_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos)                      /*!< GPIO_PORT NOT4: NOTP2 Mask          */
+#define GPIO_PORT_NOT4_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT4: NOTP3 Position      */
+#define GPIO_PORT_NOT4_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos)                      /*!< GPIO_PORT NOT4: NOTP3 Mask          */
+#define GPIO_PORT_NOT4_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT4: NOTP4 Position      */
+#define GPIO_PORT_NOT4_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos)                      /*!< GPIO_PORT NOT4: NOTP4 Mask          */
+#define GPIO_PORT_NOT4_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT4: NOTP5 Position      */
+#define GPIO_PORT_NOT4_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos)                      /*!< GPIO_PORT NOT4: NOTP5 Mask          */
+#define GPIO_PORT_NOT4_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT4: NOTP6 Position      */
+#define GPIO_PORT_NOT4_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos)                      /*!< GPIO_PORT NOT4: NOTP6 Mask          */
+#define GPIO_PORT_NOT4_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT4: NOTP7 Position      */
+#define GPIO_PORT_NOT4_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos)                      /*!< GPIO_PORT NOT4: NOTP7 Mask          */
+#define GPIO_PORT_NOT4_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT4: NOTP8 Position      */
+#define GPIO_PORT_NOT4_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos)                      /*!< GPIO_PORT NOT4: NOTP8 Mask          */
+#define GPIO_PORT_NOT4_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT4: NOTP9 Position      */
+#define GPIO_PORT_NOT4_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos)                      /*!< GPIO_PORT NOT4: NOTP9 Mask          */
+#define GPIO_PORT_NOT4_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT4: NOTP10 Position     */
+#define GPIO_PORT_NOT4_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos)                     /*!< GPIO_PORT NOT4: NOTP10 Mask         */
+#define GPIO_PORT_NOT4_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT4: NOTP11 Position     */
+#define GPIO_PORT_NOT4_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos)                     /*!< GPIO_PORT NOT4: NOTP11 Mask         */
+#define GPIO_PORT_NOT4_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT4: NOTP12 Position     */
+#define GPIO_PORT_NOT4_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos)                     /*!< GPIO_PORT NOT4: NOTP12 Mask         */
+#define GPIO_PORT_NOT4_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT4: NOTP13 Position     */
+#define GPIO_PORT_NOT4_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos)                     /*!< GPIO_PORT NOT4: NOTP13 Mask         */
+#define GPIO_PORT_NOT4_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT4: NOTP14 Position     */
+#define GPIO_PORT_NOT4_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos)                     /*!< GPIO_PORT NOT4: NOTP14 Mask         */
+#define GPIO_PORT_NOT4_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT4: NOTP15 Position     */
+#define GPIO_PORT_NOT4_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos)                     /*!< GPIO_PORT NOT4: NOTP15 Mask         */
+#define GPIO_PORT_NOT4_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT4: NOTP16 Position     */
+#define GPIO_PORT_NOT4_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos)                     /*!< GPIO_PORT NOT4: NOTP16 Mask         */
+#define GPIO_PORT_NOT4_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT4: NOTP17 Position     */
+#define GPIO_PORT_NOT4_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos)                     /*!< GPIO_PORT NOT4: NOTP17 Mask         */
+#define GPIO_PORT_NOT4_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT4: NOTP18 Position     */
+#define GPIO_PORT_NOT4_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos)                     /*!< GPIO_PORT NOT4: NOTP18 Mask         */
+#define GPIO_PORT_NOT4_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT4: NOTP19 Position     */
+#define GPIO_PORT_NOT4_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos)                     /*!< GPIO_PORT NOT4: NOTP19 Mask         */
+#define GPIO_PORT_NOT4_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT4: NOTP20 Position     */
+#define GPIO_PORT_NOT4_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos)                     /*!< GPIO_PORT NOT4: NOTP20 Mask         */
+#define GPIO_PORT_NOT4_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT4: NOTP21 Position     */
+#define GPIO_PORT_NOT4_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos)                     /*!< GPIO_PORT NOT4: NOTP21 Mask         */
+#define GPIO_PORT_NOT4_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT4: NOTP22 Position     */
+#define GPIO_PORT_NOT4_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos)                     /*!< GPIO_PORT NOT4: NOTP22 Mask         */
+#define GPIO_PORT_NOT4_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT4: NOTP23 Position     */
+#define GPIO_PORT_NOT4_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos)                     /*!< GPIO_PORT NOT4: NOTP23 Mask         */
+#define GPIO_PORT_NOT4_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT4: NOTP24 Position     */
+#define GPIO_PORT_NOT4_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos)                     /*!< GPIO_PORT NOT4: NOTP24 Mask         */
+#define GPIO_PORT_NOT4_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT4: NOTP25 Position     */
+#define GPIO_PORT_NOT4_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos)                     /*!< GPIO_PORT NOT4: NOTP25 Mask         */
+#define GPIO_PORT_NOT4_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT4: NOTP26 Position     */
+#define GPIO_PORT_NOT4_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos)                     /*!< GPIO_PORT NOT4: NOTP26 Mask         */
+#define GPIO_PORT_NOT4_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT4: NOTP27 Position     */
+#define GPIO_PORT_NOT4_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos)                     /*!< GPIO_PORT NOT4: NOTP27 Mask         */
+#define GPIO_PORT_NOT4_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT4: NOTP28 Position     */
+#define GPIO_PORT_NOT4_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos)                     /*!< GPIO_PORT NOT4: NOTP28 Mask         */
+#define GPIO_PORT_NOT4_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT4: NOTP29 Position     */
+#define GPIO_PORT_NOT4_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos)                     /*!< GPIO_PORT NOT4: NOTP29 Mask         */
+#define GPIO_PORT_NOT4_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT4: NOTP30 Position     */
+#define GPIO_PORT_NOT4_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos)                     /*!< GPIO_PORT NOT4: NOTP30 Mask         */
+#define GPIO_PORT_NOT4_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT4: NOTP31 Position     */
+#define GPIO_PORT_NOT4_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos)                     /*!< GPIO_PORT NOT4: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT5  -----------------------------------------
+#define GPIO_PORT_NOT5_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT5: NOTP0 Position      */
+#define GPIO_PORT_NOT5_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos)                      /*!< GPIO_PORT NOT5: NOTP0 Mask          */
+#define GPIO_PORT_NOT5_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT5: NOTP1 Position      */
+#define GPIO_PORT_NOT5_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos)                      /*!< GPIO_PORT NOT5: NOTP1 Mask          */
+#define GPIO_PORT_NOT5_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT5: NOTP2 Position      */
+#define GPIO_PORT_NOT5_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos)                      /*!< GPIO_PORT NOT5: NOTP2 Mask          */
+#define GPIO_PORT_NOT5_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT5: NOTP3 Position      */
+#define GPIO_PORT_NOT5_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos)                      /*!< GPIO_PORT NOT5: NOTP3 Mask          */
+#define GPIO_PORT_NOT5_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT5: NOTP4 Position      */
+#define GPIO_PORT_NOT5_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos)                      /*!< GPIO_PORT NOT5: NOTP4 Mask          */
+#define GPIO_PORT_NOT5_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT5: NOTP5 Position      */
+#define GPIO_PORT_NOT5_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos)                      /*!< GPIO_PORT NOT5: NOTP5 Mask          */
+#define GPIO_PORT_NOT5_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT5: NOTP6 Position      */
+#define GPIO_PORT_NOT5_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos)                      /*!< GPIO_PORT NOT5: NOTP6 Mask          */
+#define GPIO_PORT_NOT5_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT5: NOTP7 Position      */
+#define GPIO_PORT_NOT5_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos)                      /*!< GPIO_PORT NOT5: NOTP7 Mask          */
+#define GPIO_PORT_NOT5_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT5: NOTP8 Position      */
+#define GPIO_PORT_NOT5_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos)                      /*!< GPIO_PORT NOT5: NOTP8 Mask          */
+#define GPIO_PORT_NOT5_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT5: NOTP9 Position      */
+#define GPIO_PORT_NOT5_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos)                      /*!< GPIO_PORT NOT5: NOTP9 Mask          */
+#define GPIO_PORT_NOT5_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT5: NOTP10 Position     */
+#define GPIO_PORT_NOT5_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos)                     /*!< GPIO_PORT NOT5: NOTP10 Mask         */
+#define GPIO_PORT_NOT5_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT5: NOTP11 Position     */
+#define GPIO_PORT_NOT5_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos)                     /*!< GPIO_PORT NOT5: NOTP11 Mask         */
+#define GPIO_PORT_NOT5_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT5: NOTP12 Position     */
+#define GPIO_PORT_NOT5_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos)                     /*!< GPIO_PORT NOT5: NOTP12 Mask         */
+#define GPIO_PORT_NOT5_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT5: NOTP13 Position     */
+#define GPIO_PORT_NOT5_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos)                     /*!< GPIO_PORT NOT5: NOTP13 Mask         */
+#define GPIO_PORT_NOT5_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT5: NOTP14 Position     */
+#define GPIO_PORT_NOT5_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos)                     /*!< GPIO_PORT NOT5: NOTP14 Mask         */
+#define GPIO_PORT_NOT5_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT5: NOTP15 Position     */
+#define GPIO_PORT_NOT5_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos)                     /*!< GPIO_PORT NOT5: NOTP15 Mask         */
+#define GPIO_PORT_NOT5_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT5: NOTP16 Position     */
+#define GPIO_PORT_NOT5_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos)                     /*!< GPIO_PORT NOT5: NOTP16 Mask         */
+#define GPIO_PORT_NOT5_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT5: NOTP17 Position     */
+#define GPIO_PORT_NOT5_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos)                     /*!< GPIO_PORT NOT5: NOTP17 Mask         */
+#define GPIO_PORT_NOT5_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT5: NOTP18 Position     */
+#define GPIO_PORT_NOT5_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos)                     /*!< GPIO_PORT NOT5: NOTP18 Mask         */
+#define GPIO_PORT_NOT5_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT5: NOTP19 Position     */
+#define GPIO_PORT_NOT5_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos)                     /*!< GPIO_PORT NOT5: NOTP19 Mask         */
+#define GPIO_PORT_NOT5_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT5: NOTP20 Position     */
+#define GPIO_PORT_NOT5_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos)                     /*!< GPIO_PORT NOT5: NOTP20 Mask         */
+#define GPIO_PORT_NOT5_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT5: NOTP21 Position     */
+#define GPIO_PORT_NOT5_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos)                     /*!< GPIO_PORT NOT5: NOTP21 Mask         */
+#define GPIO_PORT_NOT5_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT5: NOTP22 Position     */
+#define GPIO_PORT_NOT5_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos)                     /*!< GPIO_PORT NOT5: NOTP22 Mask         */
+#define GPIO_PORT_NOT5_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT5: NOTP23 Position     */
+#define GPIO_PORT_NOT5_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos)                     /*!< GPIO_PORT NOT5: NOTP23 Mask         */
+#define GPIO_PORT_NOT5_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT5: NOTP24 Position     */
+#define GPIO_PORT_NOT5_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos)                     /*!< GPIO_PORT NOT5: NOTP24 Mask         */
+#define GPIO_PORT_NOT5_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT5: NOTP25 Position     */
+#define GPIO_PORT_NOT5_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos)                     /*!< GPIO_PORT NOT5: NOTP25 Mask         */
+#define GPIO_PORT_NOT5_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT5: NOTP26 Position     */
+#define GPIO_PORT_NOT5_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos)                     /*!< GPIO_PORT NOT5: NOTP26 Mask         */
+#define GPIO_PORT_NOT5_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT5: NOTP27 Position     */
+#define GPIO_PORT_NOT5_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos)                     /*!< GPIO_PORT NOT5: NOTP27 Mask         */
+#define GPIO_PORT_NOT5_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT5: NOTP28 Position     */
+#define GPIO_PORT_NOT5_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos)                     /*!< GPIO_PORT NOT5: NOTP28 Mask         */
+#define GPIO_PORT_NOT5_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT5: NOTP29 Position     */
+#define GPIO_PORT_NOT5_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos)                     /*!< GPIO_PORT NOT5: NOTP29 Mask         */
+#define GPIO_PORT_NOT5_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT5: NOTP30 Position     */
+#define GPIO_PORT_NOT5_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos)                     /*!< GPIO_PORT NOT5: NOTP30 Mask         */
+#define GPIO_PORT_NOT5_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT5: NOTP31 Position     */
+#define GPIO_PORT_NOT5_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos)                     /*!< GPIO_PORT NOT5: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT6  -----------------------------------------
+#define GPIO_PORT_NOT6_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT6: NOTP0 Position      */
+#define GPIO_PORT_NOT6_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos)                      /*!< GPIO_PORT NOT6: NOTP0 Mask          */
+#define GPIO_PORT_NOT6_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT6: NOTP1 Position      */
+#define GPIO_PORT_NOT6_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos)                      /*!< GPIO_PORT NOT6: NOTP1 Mask          */
+#define GPIO_PORT_NOT6_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT6: NOTP2 Position      */
+#define GPIO_PORT_NOT6_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos)                      /*!< GPIO_PORT NOT6: NOTP2 Mask          */
+#define GPIO_PORT_NOT6_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT6: NOTP3 Position      */
+#define GPIO_PORT_NOT6_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos)                      /*!< GPIO_PORT NOT6: NOTP3 Mask          */
+#define GPIO_PORT_NOT6_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT6: NOTP4 Position      */
+#define GPIO_PORT_NOT6_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos)                      /*!< GPIO_PORT NOT6: NOTP4 Mask          */
+#define GPIO_PORT_NOT6_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT6: NOTP5 Position      */
+#define GPIO_PORT_NOT6_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos)                      /*!< GPIO_PORT NOT6: NOTP5 Mask          */
+#define GPIO_PORT_NOT6_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT6: NOTP6 Position      */
+#define GPIO_PORT_NOT6_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos)                      /*!< GPIO_PORT NOT6: NOTP6 Mask          */
+#define GPIO_PORT_NOT6_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT6: NOTP7 Position      */
+#define GPIO_PORT_NOT6_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos)                      /*!< GPIO_PORT NOT6: NOTP7 Mask          */
+#define GPIO_PORT_NOT6_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT6: NOTP8 Position      */
+#define GPIO_PORT_NOT6_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos)                      /*!< GPIO_PORT NOT6: NOTP8 Mask          */
+#define GPIO_PORT_NOT6_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT6: NOTP9 Position      */
+#define GPIO_PORT_NOT6_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos)                      /*!< GPIO_PORT NOT6: NOTP9 Mask          */
+#define GPIO_PORT_NOT6_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT6: NOTP10 Position     */
+#define GPIO_PORT_NOT6_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos)                     /*!< GPIO_PORT NOT6: NOTP10 Mask         */
+#define GPIO_PORT_NOT6_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT6: NOTP11 Position     */
+#define GPIO_PORT_NOT6_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos)                     /*!< GPIO_PORT NOT6: NOTP11 Mask         */
+#define GPIO_PORT_NOT6_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT6: NOTP12 Position     */
+#define GPIO_PORT_NOT6_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos)                     /*!< GPIO_PORT NOT6: NOTP12 Mask         */
+#define GPIO_PORT_NOT6_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT6: NOTP13 Position     */
+#define GPIO_PORT_NOT6_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos)                     /*!< GPIO_PORT NOT6: NOTP13 Mask         */
+#define GPIO_PORT_NOT6_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT6: NOTP14 Position     */
+#define GPIO_PORT_NOT6_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos)                     /*!< GPIO_PORT NOT6: NOTP14 Mask         */
+#define GPIO_PORT_NOT6_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT6: NOTP15 Position     */
+#define GPIO_PORT_NOT6_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos)                     /*!< GPIO_PORT NOT6: NOTP15 Mask         */
+#define GPIO_PORT_NOT6_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT6: NOTP16 Position     */
+#define GPIO_PORT_NOT6_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos)                     /*!< GPIO_PORT NOT6: NOTP16 Mask         */
+#define GPIO_PORT_NOT6_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT6: NOTP17 Position     */
+#define GPIO_PORT_NOT6_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos)                     /*!< GPIO_PORT NOT6: NOTP17 Mask         */
+#define GPIO_PORT_NOT6_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT6: NOTP18 Position     */
+#define GPIO_PORT_NOT6_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos)                     /*!< GPIO_PORT NOT6: NOTP18 Mask         */
+#define GPIO_PORT_NOT6_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT6: NOTP19 Position     */
+#define GPIO_PORT_NOT6_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos)                     /*!< GPIO_PORT NOT6: NOTP19 Mask         */
+#define GPIO_PORT_NOT6_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT6: NOTP20 Position     */
+#define GPIO_PORT_NOT6_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos)                     /*!< GPIO_PORT NOT6: NOTP20 Mask         */
+#define GPIO_PORT_NOT6_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT6: NOTP21 Position     */
+#define GPIO_PORT_NOT6_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos)                     /*!< GPIO_PORT NOT6: NOTP21 Mask         */
+#define GPIO_PORT_NOT6_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT6: NOTP22 Position     */
+#define GPIO_PORT_NOT6_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos)                     /*!< GPIO_PORT NOT6: NOTP22 Mask         */
+#define GPIO_PORT_NOT6_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT6: NOTP23 Position     */
+#define GPIO_PORT_NOT6_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos)                     /*!< GPIO_PORT NOT6: NOTP23 Mask         */
+#define GPIO_PORT_NOT6_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT6: NOTP24 Position     */
+#define GPIO_PORT_NOT6_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos)                     /*!< GPIO_PORT NOT6: NOTP24 Mask         */
+#define GPIO_PORT_NOT6_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT6: NOTP25 Position     */
+#define GPIO_PORT_NOT6_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos)                     /*!< GPIO_PORT NOT6: NOTP25 Mask         */
+#define GPIO_PORT_NOT6_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT6: NOTP26 Position     */
+#define GPIO_PORT_NOT6_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos)                     /*!< GPIO_PORT NOT6: NOTP26 Mask         */
+#define GPIO_PORT_NOT6_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT6: NOTP27 Position     */
+#define GPIO_PORT_NOT6_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos)                     /*!< GPIO_PORT NOT6: NOTP27 Mask         */
+#define GPIO_PORT_NOT6_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT6: NOTP28 Position     */
+#define GPIO_PORT_NOT6_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos)                     /*!< GPIO_PORT NOT6: NOTP28 Mask         */
+#define GPIO_PORT_NOT6_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT6: NOTP29 Position     */
+#define GPIO_PORT_NOT6_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos)                     /*!< GPIO_PORT NOT6: NOTP29 Mask         */
+#define GPIO_PORT_NOT6_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT6: NOTP30 Position     */
+#define GPIO_PORT_NOT6_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos)                     /*!< GPIO_PORT NOT6: NOTP30 Mask         */
+#define GPIO_PORT_NOT6_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT6: NOTP31 Position     */
+#define GPIO_PORT_NOT6_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos)                     /*!< GPIO_PORT NOT6: NOTP31 Mask         */
+
+// -------------------------------------  GPIO_PORT_NOT7  -----------------------------------------
+#define GPIO_PORT_NOT7_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT7: NOTP0 Position      */
+#define GPIO_PORT_NOT7_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos)                      /*!< GPIO_PORT NOT7: NOTP0 Mask          */
+#define GPIO_PORT_NOT7_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT7: NOTP1 Position      */
+#define GPIO_PORT_NOT7_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos)                      /*!< GPIO_PORT NOT7: NOTP1 Mask          */
+#define GPIO_PORT_NOT7_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT7: NOTP2 Position      */
+#define GPIO_PORT_NOT7_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos)                      /*!< GPIO_PORT NOT7: NOTP2 Mask          */
+#define GPIO_PORT_NOT7_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT7: NOTP3 Position      */
+#define GPIO_PORT_NOT7_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos)                      /*!< GPIO_PORT NOT7: NOTP3 Mask          */
+#define GPIO_PORT_NOT7_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT7: NOTP4 Position      */
+#define GPIO_PORT_NOT7_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos)                      /*!< GPIO_PORT NOT7: NOTP4 Mask          */
+#define GPIO_PORT_NOT7_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT7: NOTP5 Position      */
+#define GPIO_PORT_NOT7_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos)                      /*!< GPIO_PORT NOT7: NOTP5 Mask          */
+#define GPIO_PORT_NOT7_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT7: NOTP6 Position      */
+#define GPIO_PORT_NOT7_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos)                      /*!< GPIO_PORT NOT7: NOTP6 Mask          */
+#define GPIO_PORT_NOT7_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT7: NOTP7 Position      */
+#define GPIO_PORT_NOT7_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos)                      /*!< GPIO_PORT NOT7: NOTP7 Mask          */
+#define GPIO_PORT_NOT7_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT7: NOTP8 Position      */
+#define GPIO_PORT_NOT7_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos)                      /*!< GPIO_PORT NOT7: NOTP8 Mask          */
+#define GPIO_PORT_NOT7_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT7: NOTP9 Position      */
+#define GPIO_PORT_NOT7_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos)                      /*!< GPIO_PORT NOT7: NOTP9 Mask          */
+#define GPIO_PORT_NOT7_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT7: NOTP10 Position     */
+#define GPIO_PORT_NOT7_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos)                     /*!< GPIO_PORT NOT7: NOTP10 Mask         */
+#define GPIO_PORT_NOT7_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT7: NOTP11 Position     */
+#define GPIO_PORT_NOT7_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos)                     /*!< GPIO_PORT NOT7: NOTP11 Mask         */
+#define GPIO_PORT_NOT7_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT7: NOTP12 Position     */
+#define GPIO_PORT_NOT7_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos)                     /*!< GPIO_PORT NOT7: NOTP12 Mask         */
+#define GPIO_PORT_NOT7_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT7: NOTP13 Position     */
+#define GPIO_PORT_NOT7_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos)                     /*!< GPIO_PORT NOT7: NOTP13 Mask         */
+#define GPIO_PORT_NOT7_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT7: NOTP14 Position     */
+#define GPIO_PORT_NOT7_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos)                     /*!< GPIO_PORT NOT7: NOTP14 Mask         */
+#define GPIO_PORT_NOT7_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT7: NOTP15 Position     */
+#define GPIO_PORT_NOT7_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos)                     /*!< GPIO_PORT NOT7: NOTP15 Mask         */
+#define GPIO_PORT_NOT7_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT7: NOTP16 Position     */
+#define GPIO_PORT_NOT7_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos)                     /*!< GPIO_PORT NOT7: NOTP16 Mask         */
+#define GPIO_PORT_NOT7_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT7: NOTP17 Position     */
+#define GPIO_PORT_NOT7_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos)                     /*!< GPIO_PORT NOT7: NOTP17 Mask         */
+#define GPIO_PORT_NOT7_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT7: NOTP18 Position     */
+#define GPIO_PORT_NOT7_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos)                     /*!< GPIO_PORT NOT7: NOTP18 Mask         */
+#define GPIO_PORT_NOT7_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT7: NOTP19 Position     */
+#define GPIO_PORT_NOT7_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos)                     /*!< GPIO_PORT NOT7: NOTP19 Mask         */
+#define GPIO_PORT_NOT7_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT7: NOTP20 Position     */
+#define GPIO_PORT_NOT7_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos)                     /*!< GPIO_PORT NOT7: NOTP20 Mask         */
+#define GPIO_PORT_NOT7_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT7: NOTP21 Position     */
+#define GPIO_PORT_NOT7_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos)                     /*!< GPIO_PORT NOT7: NOTP21 Mask         */
+#define GPIO_PORT_NOT7_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT7: NOTP22 Position     */
+#define GPIO_PORT_NOT7_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos)                     /*!< GPIO_PORT NOT7: NOTP22 Mask         */
+#define GPIO_PORT_NOT7_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT7: NOTP23 Position     */
+#define GPIO_PORT_NOT7_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos)                     /*!< GPIO_PORT NOT7: NOTP23 Mask         */
+#define GPIO_PORT_NOT7_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT7: NOTP24 Position     */
+#define GPIO_PORT_NOT7_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos)                     /*!< GPIO_PORT NOT7: NOTP24 Mask         */
+#define GPIO_PORT_NOT7_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT7: NOTP25 Position     */
+#define GPIO_PORT_NOT7_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos)                     /*!< GPIO_PORT NOT7: NOTP25 Mask         */
+#define GPIO_PORT_NOT7_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT7: NOTP26 Position     */
+#define GPIO_PORT_NOT7_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos)                     /*!< GPIO_PORT NOT7: NOTP26 Mask         */
+#define GPIO_PORT_NOT7_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT7: NOTP27 Position     */
+#define GPIO_PORT_NOT7_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos)                     /*!< GPIO_PORT NOT7: NOTP27 Mask         */
+#define GPIO_PORT_NOT7_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT7: NOTP28 Position     */
+#define GPIO_PORT_NOT7_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos)                     /*!< GPIO_PORT NOT7: NOTP28 Mask         */
+#define GPIO_PORT_NOT7_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT7: NOTP29 Position     */
+#define GPIO_PORT_NOT7_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos)                     /*!< GPIO_PORT NOT7: NOTP29 Mask         */
+#define GPIO_PORT_NOT7_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT7: NOTP30 Position     */
+#define GPIO_PORT_NOT7_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos)                     /*!< GPIO_PORT NOT7: NOTP30 Mask         */
+#define GPIO_PORT_NOT7_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT7: NOTP31 Position     */
+#define GPIO_PORT_NOT7_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos)                     /*!< GPIO_PORT NOT7: NOTP31 Mask         */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                  SPI Position & Mask                                 -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------------  SPI_CR  ---------------------------------------------
+#define SPI_CR_BITENABLE_Pos                                  2                                                         /*!< SPI CR: BITENABLE Position          */
+#define SPI_CR_BITENABLE_Msk                                  (0x01UL << SPI_CR_BITENABLE_Pos)                          /*!< SPI CR: BITENABLE Mask              */
+#define SPI_CR_CPHA_Pos                                       3                                                         /*!< SPI CR: CPHA Position               */
+#define SPI_CR_CPHA_Msk                                       (0x01UL << SPI_CR_CPHA_Pos)                               /*!< SPI CR: CPHA Mask                   */
+#define SPI_CR_CPOL_Pos                                       4                                                         /*!< SPI CR: CPOL Position               */
+#define SPI_CR_CPOL_Msk                                       (0x01UL << SPI_CR_CPOL_Pos)                               /*!< SPI CR: CPOL Mask                   */
+#define SPI_CR_MSTR_Pos                                       5                                                         /*!< SPI CR: MSTR Position               */
+#define SPI_CR_MSTR_Msk                                       (0x01UL << SPI_CR_MSTR_Pos)                               /*!< SPI CR: MSTR Mask                   */
+#define SPI_CR_LSBF_Pos                                       6                                                         /*!< SPI CR: LSBF Position               */
+#define SPI_CR_LSBF_Msk                                       (0x01UL << SPI_CR_LSBF_Pos)                               /*!< SPI CR: LSBF Mask                   */
+#define SPI_CR_SPIE_Pos                                       7                                                         /*!< SPI CR: SPIE Position               */
+#define SPI_CR_SPIE_Msk                                       (0x01UL << SPI_CR_SPIE_Pos)                               /*!< SPI CR: SPIE Mask                   */
+#define SPI_CR_BITS_Pos                                       8                                                         /*!< SPI CR: BITS Position               */
+#define SPI_CR_BITS_Msk                                       (0x0fUL << SPI_CR_BITS_Pos)                               /*!< SPI CR: BITS Mask                   */
+
+// -----------------------------------------  SPI_SR  ---------------------------------------------
+#define SPI_SR_ABRT_Pos                                       3                                                         /*!< SPI SR: ABRT Position               */
+#define SPI_SR_ABRT_Msk                                       (0x01UL << SPI_SR_ABRT_Pos)                               /*!< SPI SR: ABRT Mask                   */
+#define SPI_SR_MODF_Pos                                       4                                                         /*!< SPI SR: MODF Position               */
+#define SPI_SR_MODF_Msk                                       (0x01UL << SPI_SR_MODF_Pos)                               /*!< SPI SR: MODF Mask                   */
+#define SPI_SR_ROVR_Pos                                       5                                                         /*!< SPI SR: ROVR Position               */
+#define SPI_SR_ROVR_Msk                                       (0x01UL << SPI_SR_ROVR_Pos)                               /*!< SPI SR: ROVR Mask                   */
+#define SPI_SR_WCOL_Pos                                       6                                                         /*!< SPI SR: WCOL Position               */
+#define SPI_SR_WCOL_Msk                                       (0x01UL << SPI_SR_WCOL_Pos)                               /*!< SPI SR: WCOL Mask                   */
+#define SPI_SR_SPIF_Pos                                       7                                                         /*!< SPI SR: SPIF Position               */
+#define SPI_SR_SPIF_Msk                                       (0x01UL << SPI_SR_SPIF_Pos)                               /*!< SPI SR: SPIF Mask                   */
+
+// -----------------------------------------  SPI_DR  ---------------------------------------------
+#define SPI_DR_DATALOW_Pos                                    0                                                         /*!< SPI DR: DATALOW Position            */
+#define SPI_DR_DATALOW_Msk                                    (0x000000ffUL << SPI_DR_DATALOW_Pos)                      /*!< SPI DR: DATALOW Mask                */
+#define SPI_DR_DATAHIGH_Pos                                   8                                                         /*!< SPI DR: DATAHIGH Position           */
+#define SPI_DR_DATAHIGH_Msk                                   (0x000000ffUL << SPI_DR_DATAHIGH_Pos)                     /*!< SPI DR: DATAHIGH Mask               */
+
+// -----------------------------------------  SPI_CCR  --------------------------------------------
+#define SPI_CCR_COUNTER_Pos                                   0                                                         /*!< SPI CCR: COUNTER Position           */
+#define SPI_CCR_COUNTER_Msk                                   (0x000000ffUL << SPI_CCR_COUNTER_Pos)                     /*!< SPI CCR: COUNTER Mask               */
+
+// -----------------------------------------  SPI_TCR  --------------------------------------------
+#define SPI_TCR_TEST_Pos                                      1                                                         /*!< SPI TCR: TEST Position              */
+#define SPI_TCR_TEST_Msk                                      (0x7fUL << SPI_TCR_TEST_Pos)                              /*!< SPI TCR: TEST Mask                  */
+
+// -----------------------------------------  SPI_TSR  --------------------------------------------
+#define SPI_TSR_ABRT_Pos                                      3                                                         /*!< SPI TSR: ABRT Position              */
+#define SPI_TSR_ABRT_Msk                                      (0x01UL << SPI_TSR_ABRT_Pos)                              /*!< SPI TSR: ABRT Mask                  */
+#define SPI_TSR_MODF_Pos                                      4                                                         /*!< SPI TSR: MODF Position              */
+#define SPI_TSR_MODF_Msk                                      (0x01UL << SPI_TSR_MODF_Pos)                              /*!< SPI TSR: MODF Mask                  */
+#define SPI_TSR_ROVR_Pos                                      5                                                         /*!< SPI TSR: ROVR Position              */
+#define SPI_TSR_ROVR_Msk                                      (0x01UL << SPI_TSR_ROVR_Pos)                              /*!< SPI TSR: ROVR Mask                  */
+#define SPI_TSR_WCOL_Pos                                      6                                                         /*!< SPI TSR: WCOL Position              */
+#define SPI_TSR_WCOL_Msk                                      (0x01UL << SPI_TSR_WCOL_Pos)                              /*!< SPI TSR: WCOL Mask                  */
+#define SPI_TSR_SPIF_Pos                                      7                                                         /*!< SPI TSR: SPIF Position              */
+#define SPI_TSR_SPIF_Msk                                      (0x01UL << SPI_TSR_SPIF_Pos)                              /*!< SPI TSR: SPIF Mask                  */
+
+// -----------------------------------------  SPI_INT  --------------------------------------------
+#define SPI_INT_SPIF_Pos                                      0                                                         /*!< SPI INT: SPIF Position              */
+#define SPI_INT_SPIF_Msk                                      (0x01UL << SPI_INT_SPIF_Pos)                              /*!< SPI INT: SPIF Mask                  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 SGPIO Position & Mask                                -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG0  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG1  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG2  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG3  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG4  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG5  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG6  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG7  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG8  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG9  ---------------------------------------
+#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Mask  */
+#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Mask   */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG10  --------------------------------------
+#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG11  --------------------------------------
+#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG12  --------------------------------------
+#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG13  --------------------------------------
+#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG14  --------------------------------------
+#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Mask  */
+
+// -----------------------------------  SGPIO_OUT_MUX_CFG15  --------------------------------------
+#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Mask  */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG0  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG1  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG2  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG3  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG4  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG5  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG6  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG7  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG8  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG9  --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG10  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG11  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG12  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG13  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG14  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SGPIO_MUX_CFG15  -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG0  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG1  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG2  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG3  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG4  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG5  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG6  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG7  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG8  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG9  --------------------------------------
+#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG10  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG11  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG12  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG13  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG14  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Mask */
+
+// ----------------------------------  SGPIO_SLICE_MUX_CFG15  -------------------------------------
+#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Mask */
+
+// ---------------------------------------  SGPIO_REG0  -------------------------------------------
+#define SGPIO_REG0_REG_Pos                                    0                                                         /*!< SGPIO REG0: REG Position            */
+#define SGPIO_REG0_REG_Msk                                    (0xffffffffUL << SGPIO_REG0_REG_Pos)                      /*!< SGPIO REG0: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG1  -------------------------------------------
+#define SGPIO_REG1_REG_Pos                                    0                                                         /*!< SGPIO REG1: REG Position            */
+#define SGPIO_REG1_REG_Msk                                    (0xffffffffUL << SGPIO_REG1_REG_Pos)                      /*!< SGPIO REG1: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG2  -------------------------------------------
+#define SGPIO_REG2_REG_Pos                                    0                                                         /*!< SGPIO REG2: REG Position            */
+#define SGPIO_REG2_REG_Msk                                    (0xffffffffUL << SGPIO_REG2_REG_Pos)                      /*!< SGPIO REG2: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG3  -------------------------------------------
+#define SGPIO_REG3_REG_Pos                                    0                                                         /*!< SGPIO REG3: REG Position            */
+#define SGPIO_REG3_REG_Msk                                    (0xffffffffUL << SGPIO_REG3_REG_Pos)                      /*!< SGPIO REG3: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG4  -------------------------------------------
+#define SGPIO_REG4_REG_Pos                                    0                                                         /*!< SGPIO REG4: REG Position            */
+#define SGPIO_REG4_REG_Msk                                    (0xffffffffUL << SGPIO_REG4_REG_Pos)                      /*!< SGPIO REG4: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG5  -------------------------------------------
+#define SGPIO_REG5_REG_Pos                                    0                                                         /*!< SGPIO REG5: REG Position            */
+#define SGPIO_REG5_REG_Msk                                    (0xffffffffUL << SGPIO_REG5_REG_Pos)                      /*!< SGPIO REG5: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG6  -------------------------------------------
+#define SGPIO_REG6_REG_Pos                                    0                                                         /*!< SGPIO REG6: REG Position            */
+#define SGPIO_REG6_REG_Msk                                    (0xffffffffUL << SGPIO_REG6_REG_Pos)                      /*!< SGPIO REG6: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG7  -------------------------------------------
+#define SGPIO_REG7_REG_Pos                                    0                                                         /*!< SGPIO REG7: REG Position            */
+#define SGPIO_REG7_REG_Msk                                    (0xffffffffUL << SGPIO_REG7_REG_Pos)                      /*!< SGPIO REG7: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG8  -------------------------------------------
+#define SGPIO_REG8_REG_Pos                                    0                                                         /*!< SGPIO REG8: REG Position            */
+#define SGPIO_REG8_REG_Msk                                    (0xffffffffUL << SGPIO_REG8_REG_Pos)                      /*!< SGPIO REG8: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG9  -------------------------------------------
+#define SGPIO_REG9_REG_Pos                                    0                                                         /*!< SGPIO REG9: REG Position            */
+#define SGPIO_REG9_REG_Msk                                    (0xffffffffUL << SGPIO_REG9_REG_Pos)                      /*!< SGPIO REG9: REG Mask                */
+
+// ---------------------------------------  SGPIO_REG10  ------------------------------------------
+#define SGPIO_REG10_REG_Pos                                   0                                                         /*!< SGPIO REG10: REG Position           */
+#define SGPIO_REG10_REG_Msk                                   (0xffffffffUL << SGPIO_REG10_REG_Pos)                     /*!< SGPIO REG10: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG11  ------------------------------------------
+#define SGPIO_REG11_REG_Pos                                   0                                                         /*!< SGPIO REG11: REG Position           */
+#define SGPIO_REG11_REG_Msk                                   (0xffffffffUL << SGPIO_REG11_REG_Pos)                     /*!< SGPIO REG11: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG12  ------------------------------------------
+#define SGPIO_REG12_REG_Pos                                   0                                                         /*!< SGPIO REG12: REG Position           */
+#define SGPIO_REG12_REG_Msk                                   (0xffffffffUL << SGPIO_REG12_REG_Pos)                     /*!< SGPIO REG12: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG13  ------------------------------------------
+#define SGPIO_REG13_REG_Pos                                   0                                                         /*!< SGPIO REG13: REG Position           */
+#define SGPIO_REG13_REG_Msk                                   (0xffffffffUL << SGPIO_REG13_REG_Pos)                     /*!< SGPIO REG13: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG14  ------------------------------------------
+#define SGPIO_REG14_REG_Pos                                   0                                                         /*!< SGPIO REG14: REG Position           */
+#define SGPIO_REG14_REG_Msk                                   (0xffffffffUL << SGPIO_REG14_REG_Pos)                     /*!< SGPIO REG14: REG Mask               */
+
+// ---------------------------------------  SGPIO_REG15  ------------------------------------------
+#define SGPIO_REG15_REG_Pos                                   0                                                         /*!< SGPIO REG15: REG Position           */
+#define SGPIO_REG15_REG_Msk                                   (0xffffffffUL << SGPIO_REG15_REG_Pos)                     /*!< SGPIO REG15: REG Mask               */
+
+// --------------------------------------  SGPIO_REG_SS0  -----------------------------------------
+#define SGPIO_REG_SS0_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS0: REG_SS Position      */
+#define SGPIO_REG_SS0_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos)                /*!< SGPIO REG_SS0: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS1  -----------------------------------------
+#define SGPIO_REG_SS1_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS1: REG_SS Position      */
+#define SGPIO_REG_SS1_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos)                /*!< SGPIO REG_SS1: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS2  -----------------------------------------
+#define SGPIO_REG_SS2_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS2: REG_SS Position      */
+#define SGPIO_REG_SS2_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos)                /*!< SGPIO REG_SS2: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS3  -----------------------------------------
+#define SGPIO_REG_SS3_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS3: REG_SS Position      */
+#define SGPIO_REG_SS3_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos)                /*!< SGPIO REG_SS3: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS4  -----------------------------------------
+#define SGPIO_REG_SS4_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS4: REG_SS Position      */
+#define SGPIO_REG_SS4_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos)                /*!< SGPIO REG_SS4: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS5  -----------------------------------------
+#define SGPIO_REG_SS5_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS5: REG_SS Position      */
+#define SGPIO_REG_SS5_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos)                /*!< SGPIO REG_SS5: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS6  -----------------------------------------
+#define SGPIO_REG_SS6_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS6: REG_SS Position      */
+#define SGPIO_REG_SS6_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos)                /*!< SGPIO REG_SS6: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS7  -----------------------------------------
+#define SGPIO_REG_SS7_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS7: REG_SS Position      */
+#define SGPIO_REG_SS7_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos)                /*!< SGPIO REG_SS7: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS8  -----------------------------------------
+#define SGPIO_REG_SS8_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS8: REG_SS Position      */
+#define SGPIO_REG_SS8_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos)                /*!< SGPIO REG_SS8: REG_SS Mask          */
+
+// --------------------------------------  SGPIO_REG_SS9  -----------------------------------------
+#define SGPIO_REG_SS9_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS9: REG_SS Position      */
+#define SGPIO_REG_SS9_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos)                /*!< SGPIO REG_SS9: REG_SS Mask          */
+
+// -------------------------------------  SGPIO_REG_SS10  -----------------------------------------
+#define SGPIO_REG_SS10_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS10: REG_SS Position     */
+#define SGPIO_REG_SS10_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos)               /*!< SGPIO REG_SS10: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS11  -----------------------------------------
+#define SGPIO_REG_SS11_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS11: REG_SS Position     */
+#define SGPIO_REG_SS11_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos)               /*!< SGPIO REG_SS11: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS12  -----------------------------------------
+#define SGPIO_REG_SS12_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS12: REG_SS Position     */
+#define SGPIO_REG_SS12_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos)               /*!< SGPIO REG_SS12: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS13  -----------------------------------------
+#define SGPIO_REG_SS13_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS13: REG_SS Position     */
+#define SGPIO_REG_SS13_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos)               /*!< SGPIO REG_SS13: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS14  -----------------------------------------
+#define SGPIO_REG_SS14_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS14: REG_SS Position     */
+#define SGPIO_REG_SS14_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos)               /*!< SGPIO REG_SS14: REG_SS Mask         */
+
+// -------------------------------------  SGPIO_REG_SS15  -----------------------------------------
+#define SGPIO_REG_SS15_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS15: REG_SS Position     */
+#define SGPIO_REG_SS15_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos)               /*!< SGPIO REG_SS15: REG_SS Mask         */
+
+// --------------------------------------  SGPIO_PRESET0  -----------------------------------------
+#define SGPIO_PRESET0_PRESET_Pos                              0                                                         /*!< SGPIO PRESET0: PRESET Position      */
+#define SGPIO_PRESET0_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos)                /*!< SGPIO PRESET0: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET1  -----------------------------------------
+#define SGPIO_PRESET1_PRESET_Pos                              0                                                         /*!< SGPIO PRESET1: PRESET Position      */
+#define SGPIO_PRESET1_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos)                /*!< SGPIO PRESET1: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET2  -----------------------------------------
+#define SGPIO_PRESET2_PRESET_Pos                              0                                                         /*!< SGPIO PRESET2: PRESET Position      */
+#define SGPIO_PRESET2_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos)                /*!< SGPIO PRESET2: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET3  -----------------------------------------
+#define SGPIO_PRESET3_PRESET_Pos                              0                                                         /*!< SGPIO PRESET3: PRESET Position      */
+#define SGPIO_PRESET3_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos)                /*!< SGPIO PRESET3: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET4  -----------------------------------------
+#define SGPIO_PRESET4_PRESET_Pos                              0                                                         /*!< SGPIO PRESET4: PRESET Position      */
+#define SGPIO_PRESET4_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos)                /*!< SGPIO PRESET4: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET5  -----------------------------------------
+#define SGPIO_PRESET5_PRESET_Pos                              0                                                         /*!< SGPIO PRESET5: PRESET Position      */
+#define SGPIO_PRESET5_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos)                /*!< SGPIO PRESET5: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET6  -----------------------------------------
+#define SGPIO_PRESET6_PRESET_Pos                              0                                                         /*!< SGPIO PRESET6: PRESET Position      */
+#define SGPIO_PRESET6_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos)                /*!< SGPIO PRESET6: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET7  -----------------------------------------
+#define SGPIO_PRESET7_PRESET_Pos                              0                                                         /*!< SGPIO PRESET7: PRESET Position      */
+#define SGPIO_PRESET7_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos)                /*!< SGPIO PRESET7: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET8  -----------------------------------------
+#define SGPIO_PRESET8_PRESET_Pos                              0                                                         /*!< SGPIO PRESET8: PRESET Position      */
+#define SGPIO_PRESET8_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos)                /*!< SGPIO PRESET8: PRESET Mask          */
+
+// --------------------------------------  SGPIO_PRESET9  -----------------------------------------
+#define SGPIO_PRESET9_PRESET_Pos                              0                                                         /*!< SGPIO PRESET9: PRESET Position      */
+#define SGPIO_PRESET9_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos)                /*!< SGPIO PRESET9: PRESET Mask          */
+
+// -------------------------------------  SGPIO_PRESET10  -----------------------------------------
+#define SGPIO_PRESET10_PRESET_Pos                             0                                                         /*!< SGPIO PRESET10: PRESET Position     */
+#define SGPIO_PRESET10_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos)               /*!< SGPIO PRESET10: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET11  -----------------------------------------
+#define SGPIO_PRESET11_PRESET_Pos                             0                                                         /*!< SGPIO PRESET11: PRESET Position     */
+#define SGPIO_PRESET11_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos)               /*!< SGPIO PRESET11: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET12  -----------------------------------------
+#define SGPIO_PRESET12_PRESET_Pos                             0                                                         /*!< SGPIO PRESET12: PRESET Position     */
+#define SGPIO_PRESET12_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos)               /*!< SGPIO PRESET12: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET13  -----------------------------------------
+#define SGPIO_PRESET13_PRESET_Pos                             0                                                         /*!< SGPIO PRESET13: PRESET Position     */
+#define SGPIO_PRESET13_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos)               /*!< SGPIO PRESET13: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET14  -----------------------------------------
+#define SGPIO_PRESET14_PRESET_Pos                             0                                                         /*!< SGPIO PRESET14: PRESET Position     */
+#define SGPIO_PRESET14_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos)               /*!< SGPIO PRESET14: PRESET Mask         */
+
+// -------------------------------------  SGPIO_PRESET15  -----------------------------------------
+#define SGPIO_PRESET15_PRESET_Pos                             0                                                         /*!< SGPIO PRESET15: PRESET Position     */
+#define SGPIO_PRESET15_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos)               /*!< SGPIO PRESET15: PRESET Mask         */
+
+// --------------------------------------  SGPIO_COUNT0  ------------------------------------------
+#define SGPIO_COUNT0_COUNT_Pos                                0                                                         /*!< SGPIO COUNT0: COUNT Position        */
+#define SGPIO_COUNT0_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos)                  /*!< SGPIO COUNT0: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT1  ------------------------------------------
+#define SGPIO_COUNT1_COUNT_Pos                                0                                                         /*!< SGPIO COUNT1: COUNT Position        */
+#define SGPIO_COUNT1_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos)                  /*!< SGPIO COUNT1: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT2  ------------------------------------------
+#define SGPIO_COUNT2_COUNT_Pos                                0                                                         /*!< SGPIO COUNT2: COUNT Position        */
+#define SGPIO_COUNT2_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos)                  /*!< SGPIO COUNT2: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT3  ------------------------------------------
+#define SGPIO_COUNT3_COUNT_Pos                                0                                                         /*!< SGPIO COUNT3: COUNT Position        */
+#define SGPIO_COUNT3_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos)                  /*!< SGPIO COUNT3: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT4  ------------------------------------------
+#define SGPIO_COUNT4_COUNT_Pos                                0                                                         /*!< SGPIO COUNT4: COUNT Position        */
+#define SGPIO_COUNT4_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos)                  /*!< SGPIO COUNT4: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT5  ------------------------------------------
+#define SGPIO_COUNT5_COUNT_Pos                                0                                                         /*!< SGPIO COUNT5: COUNT Position        */
+#define SGPIO_COUNT5_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos)                  /*!< SGPIO COUNT5: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT6  ------------------------------------------
+#define SGPIO_COUNT6_COUNT_Pos                                0                                                         /*!< SGPIO COUNT6: COUNT Position        */
+#define SGPIO_COUNT6_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos)                  /*!< SGPIO COUNT6: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT7  ------------------------------------------
+#define SGPIO_COUNT7_COUNT_Pos                                0                                                         /*!< SGPIO COUNT7: COUNT Position        */
+#define SGPIO_COUNT7_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos)                  /*!< SGPIO COUNT7: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT8  ------------------------------------------
+#define SGPIO_COUNT8_COUNT_Pos                                0                                                         /*!< SGPIO COUNT8: COUNT Position        */
+#define SGPIO_COUNT8_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos)                  /*!< SGPIO COUNT8: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT9  ------------------------------------------
+#define SGPIO_COUNT9_COUNT_Pos                                0                                                         /*!< SGPIO COUNT9: COUNT Position        */
+#define SGPIO_COUNT9_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos)                  /*!< SGPIO COUNT9: COUNT Mask            */
+
+// --------------------------------------  SGPIO_COUNT10  -----------------------------------------
+#define SGPIO_COUNT10_COUNT_Pos                               0                                                         /*!< SGPIO COUNT10: COUNT Position       */
+#define SGPIO_COUNT10_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos)                 /*!< SGPIO COUNT10: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT11  -----------------------------------------
+#define SGPIO_COUNT11_COUNT_Pos                               0                                                         /*!< SGPIO COUNT11: COUNT Position       */
+#define SGPIO_COUNT11_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos)                 /*!< SGPIO COUNT11: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT12  -----------------------------------------
+#define SGPIO_COUNT12_COUNT_Pos                               0                                                         /*!< SGPIO COUNT12: COUNT Position       */
+#define SGPIO_COUNT12_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos)                 /*!< SGPIO COUNT12: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT13  -----------------------------------------
+#define SGPIO_COUNT13_COUNT_Pos                               0                                                         /*!< SGPIO COUNT13: COUNT Position       */
+#define SGPIO_COUNT13_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos)                 /*!< SGPIO COUNT13: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT14  -----------------------------------------
+#define SGPIO_COUNT14_COUNT_Pos                               0                                                         /*!< SGPIO COUNT14: COUNT Position       */
+#define SGPIO_COUNT14_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos)                 /*!< SGPIO COUNT14: COUNT Mask           */
+
+// --------------------------------------  SGPIO_COUNT15  -----------------------------------------
+#define SGPIO_COUNT15_COUNT_Pos                               0                                                         /*!< SGPIO COUNT15: COUNT Position       */
+#define SGPIO_COUNT15_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos)                 /*!< SGPIO COUNT15: COUNT Mask           */
+
+// ---------------------------------------  SGPIO_POS0  -------------------------------------------
+#define SGPIO_POS0_POS_Pos                                    0                                                         /*!< SGPIO POS0: POS Position            */
+#define SGPIO_POS0_POS_Msk                                    (0x000000ffUL << SGPIO_POS0_POS_Pos)                      /*!< SGPIO POS0: POS Mask                */
+#define SGPIO_POS0_POS_RESET_Pos                              8                                                         /*!< SGPIO POS0: POS_RESET Position      */
+#define SGPIO_POS0_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos)                /*!< SGPIO POS0: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS1  -------------------------------------------
+#define SGPIO_POS1_POS_Pos                                    0                                                         /*!< SGPIO POS1: POS Position            */
+#define SGPIO_POS1_POS_Msk                                    (0x000000ffUL << SGPIO_POS1_POS_Pos)                      /*!< SGPIO POS1: POS Mask                */
+#define SGPIO_POS1_POS_RESET_Pos                              8                                                         /*!< SGPIO POS1: POS_RESET Position      */
+#define SGPIO_POS1_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos)                /*!< SGPIO POS1: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS2  -------------------------------------------
+#define SGPIO_POS2_POS_Pos                                    0                                                         /*!< SGPIO POS2: POS Position            */
+#define SGPIO_POS2_POS_Msk                                    (0x000000ffUL << SGPIO_POS2_POS_Pos)                      /*!< SGPIO POS2: POS Mask                */
+#define SGPIO_POS2_POS_RESET_Pos                              8                                                         /*!< SGPIO POS2: POS_RESET Position      */
+#define SGPIO_POS2_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos)                /*!< SGPIO POS2: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS3  -------------------------------------------
+#define SGPIO_POS3_POS_Pos                                    0                                                         /*!< SGPIO POS3: POS Position            */
+#define SGPIO_POS3_POS_Msk                                    (0x000000ffUL << SGPIO_POS3_POS_Pos)                      /*!< SGPIO POS3: POS Mask                */
+#define SGPIO_POS3_POS_RESET_Pos                              8                                                         /*!< SGPIO POS3: POS_RESET Position      */
+#define SGPIO_POS3_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos)                /*!< SGPIO POS3: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS4  -------------------------------------------
+#define SGPIO_POS4_POS_Pos                                    0                                                         /*!< SGPIO POS4: POS Position            */
+#define SGPIO_POS4_POS_Msk                                    (0x000000ffUL << SGPIO_POS4_POS_Pos)                      /*!< SGPIO POS4: POS Mask                */
+#define SGPIO_POS4_POS_RESET_Pos                              8                                                         /*!< SGPIO POS4: POS_RESET Position      */
+#define SGPIO_POS4_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos)                /*!< SGPIO POS4: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS5  -------------------------------------------
+#define SGPIO_POS5_POS_Pos                                    0                                                         /*!< SGPIO POS5: POS Position            */
+#define SGPIO_POS5_POS_Msk                                    (0x000000ffUL << SGPIO_POS5_POS_Pos)                      /*!< SGPIO POS5: POS Mask                */
+#define SGPIO_POS5_POS_RESET_Pos                              8                                                         /*!< SGPIO POS5: POS_RESET Position      */
+#define SGPIO_POS5_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos)                /*!< SGPIO POS5: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS6  -------------------------------------------
+#define SGPIO_POS6_POS_Pos                                    0                                                         /*!< SGPIO POS6: POS Position            */
+#define SGPIO_POS6_POS_Msk                                    (0x000000ffUL << SGPIO_POS6_POS_Pos)                      /*!< SGPIO POS6: POS Mask                */
+#define SGPIO_POS6_POS_RESET_Pos                              8                                                         /*!< SGPIO POS6: POS_RESET Position      */
+#define SGPIO_POS6_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos)                /*!< SGPIO POS6: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS7  -------------------------------------------
+#define SGPIO_POS7_POS_Pos                                    0                                                         /*!< SGPIO POS7: POS Position            */
+#define SGPIO_POS7_POS_Msk                                    (0x000000ffUL << SGPIO_POS7_POS_Pos)                      /*!< SGPIO POS7: POS Mask                */
+#define SGPIO_POS7_POS_RESET_Pos                              8                                                         /*!< SGPIO POS7: POS_RESET Position      */
+#define SGPIO_POS7_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos)                /*!< SGPIO POS7: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS8  -------------------------------------------
+#define SGPIO_POS8_POS_Pos                                    0                                                         /*!< SGPIO POS8: POS Position            */
+#define SGPIO_POS8_POS_Msk                                    (0x000000ffUL << SGPIO_POS8_POS_Pos)                      /*!< SGPIO POS8: POS Mask                */
+#define SGPIO_POS8_POS_RESET_Pos                              8                                                         /*!< SGPIO POS8: POS_RESET Position      */
+#define SGPIO_POS8_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos)                /*!< SGPIO POS8: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS9  -------------------------------------------
+#define SGPIO_POS9_POS_Pos                                    0                                                         /*!< SGPIO POS9: POS Position            */
+#define SGPIO_POS9_POS_Msk                                    (0x000000ffUL << SGPIO_POS9_POS_Pos)                      /*!< SGPIO POS9: POS Mask                */
+#define SGPIO_POS9_POS_RESET_Pos                              8                                                         /*!< SGPIO POS9: POS_RESET Position      */
+#define SGPIO_POS9_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos)                /*!< SGPIO POS9: POS_RESET Mask          */
+
+// ---------------------------------------  SGPIO_POS10  ------------------------------------------
+#define SGPIO_POS10_POS_Pos                                   0                                                         /*!< SGPIO POS10: POS Position           */
+#define SGPIO_POS10_POS_Msk                                   (0x000000ffUL << SGPIO_POS10_POS_Pos)                     /*!< SGPIO POS10: POS Mask               */
+#define SGPIO_POS10_POS_RESET_Pos                             8                                                         /*!< SGPIO POS10: POS_RESET Position     */
+#define SGPIO_POS10_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos)               /*!< SGPIO POS10: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS11  ------------------------------------------
+#define SGPIO_POS11_POS_Pos                                   0                                                         /*!< SGPIO POS11: POS Position           */
+#define SGPIO_POS11_POS_Msk                                   (0x000000ffUL << SGPIO_POS11_POS_Pos)                     /*!< SGPIO POS11: POS Mask               */
+#define SGPIO_POS11_POS_RESET_Pos                             8                                                         /*!< SGPIO POS11: POS_RESET Position     */
+#define SGPIO_POS11_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos)               /*!< SGPIO POS11: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS12  ------------------------------------------
+#define SGPIO_POS12_POS_Pos                                   0                                                         /*!< SGPIO POS12: POS Position           */
+#define SGPIO_POS12_POS_Msk                                   (0x000000ffUL << SGPIO_POS12_POS_Pos)                     /*!< SGPIO POS12: POS Mask               */
+#define SGPIO_POS12_POS_RESET_Pos                             8                                                         /*!< SGPIO POS12: POS_RESET Position     */
+#define SGPIO_POS12_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos)               /*!< SGPIO POS12: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS13  ------------------------------------------
+#define SGPIO_POS13_POS_Pos                                   0                                                         /*!< SGPIO POS13: POS Position           */
+#define SGPIO_POS13_POS_Msk                                   (0x000000ffUL << SGPIO_POS13_POS_Pos)                     /*!< SGPIO POS13: POS Mask               */
+#define SGPIO_POS13_POS_RESET_Pos                             8                                                         /*!< SGPIO POS13: POS_RESET Position     */
+#define SGPIO_POS13_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos)               /*!< SGPIO POS13: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS14  ------------------------------------------
+#define SGPIO_POS14_POS_Pos                                   0                                                         /*!< SGPIO POS14: POS Position           */
+#define SGPIO_POS14_POS_Msk                                   (0x000000ffUL << SGPIO_POS14_POS_Pos)                     /*!< SGPIO POS14: POS Mask               */
+#define SGPIO_POS14_POS_RESET_Pos                             8                                                         /*!< SGPIO POS14: POS_RESET Position     */
+#define SGPIO_POS14_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos)               /*!< SGPIO POS14: POS_RESET Mask         */
+
+// ---------------------------------------  SGPIO_POS15  ------------------------------------------
+#define SGPIO_POS15_POS_Pos                                   0                                                         /*!< SGPIO POS15: POS Position           */
+#define SGPIO_POS15_POS_Msk                                   (0x000000ffUL << SGPIO_POS15_POS_Pos)                     /*!< SGPIO POS15: POS Mask               */
+#define SGPIO_POS15_POS_RESET_Pos                             8                                                         /*!< SGPIO POS15: POS_RESET Position     */
+#define SGPIO_POS15_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos)               /*!< SGPIO POS15: POS_RESET Mask         */
+
+// --------------------------------------  SGPIO_MASK_A  ------------------------------------------
+#define SGPIO_MASK_A_MASK_A0_Pos                              0                                                         /*!< SGPIO MASK_A: MASK_A0 Position      */
+#define SGPIO_MASK_A_MASK_A0_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A0_Pos)                      /*!< SGPIO MASK_A: MASK_A0 Mask          */
+#define SGPIO_MASK_A_MASK_A1_Pos                              1                                                         /*!< SGPIO MASK_A: MASK_A1 Position      */
+#define SGPIO_MASK_A_MASK_A1_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A1_Pos)                      /*!< SGPIO MASK_A: MASK_A1 Mask          */
+#define SGPIO_MASK_A_MASK_A2_Pos                              2                                                         /*!< SGPIO MASK_A: MASK_A2 Position      */
+#define SGPIO_MASK_A_MASK_A2_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A2_Pos)                      /*!< SGPIO MASK_A: MASK_A2 Mask          */
+#define SGPIO_MASK_A_MASK_A3_Pos                              3                                                         /*!< SGPIO MASK_A: MASK_A3 Position      */
+#define SGPIO_MASK_A_MASK_A3_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A3_Pos)                      /*!< SGPIO MASK_A: MASK_A3 Mask          */
+#define SGPIO_MASK_A_MASK_A4_Pos                              4                                                         /*!< SGPIO MASK_A: MASK_A4 Position      */
+#define SGPIO_MASK_A_MASK_A4_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A4_Pos)                      /*!< SGPIO MASK_A: MASK_A4 Mask          */
+#define SGPIO_MASK_A_MASK_A5_Pos                              5                                                         /*!< SGPIO MASK_A: MASK_A5 Position      */
+#define SGPIO_MASK_A_MASK_A5_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A5_Pos)                      /*!< SGPIO MASK_A: MASK_A5 Mask          */
+#define SGPIO_MASK_A_MASK_A6_Pos                              6                                                         /*!< SGPIO MASK_A: MASK_A6 Position      */
+#define SGPIO_MASK_A_MASK_A6_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A6_Pos)                      /*!< SGPIO MASK_A: MASK_A6 Mask          */
+#define SGPIO_MASK_A_MASK_A7_Pos                              7                                                         /*!< SGPIO MASK_A: MASK_A7 Position      */
+#define SGPIO_MASK_A_MASK_A7_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A7_Pos)                      /*!< SGPIO MASK_A: MASK_A7 Mask          */
+#define SGPIO_MASK_A_MASK_A8_Pos                              8                                                         /*!< SGPIO MASK_A: MASK_A8 Position      */
+#define SGPIO_MASK_A_MASK_A8_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A8_Pos)                      /*!< SGPIO MASK_A: MASK_A8 Mask          */
+#define SGPIO_MASK_A_MASK_A9_Pos                              9                                                         /*!< SGPIO MASK_A: MASK_A9 Position      */
+#define SGPIO_MASK_A_MASK_A9_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A9_Pos)                      /*!< SGPIO MASK_A: MASK_A9 Mask          */
+#define SGPIO_MASK_A_MASK_A10_Pos                             10                                                        /*!< SGPIO MASK_A: MASK_A10 Position     */
+#define SGPIO_MASK_A_MASK_A10_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A10_Pos)                     /*!< SGPIO MASK_A: MASK_A10 Mask         */
+#define SGPIO_MASK_A_MASK_A11_Pos                             11                                                        /*!< SGPIO MASK_A: MASK_A11 Position     */
+#define SGPIO_MASK_A_MASK_A11_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A11_Pos)                     /*!< SGPIO MASK_A: MASK_A11 Mask         */
+#define SGPIO_MASK_A_MASK_A12_Pos                             12                                                        /*!< SGPIO MASK_A: MASK_A12 Position     */
+#define SGPIO_MASK_A_MASK_A12_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A12_Pos)                     /*!< SGPIO MASK_A: MASK_A12 Mask         */
+#define SGPIO_MASK_A_MASK_A13_Pos                             13                                                        /*!< SGPIO MASK_A: MASK_A13 Position     */
+#define SGPIO_MASK_A_MASK_A13_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A13_Pos)                     /*!< SGPIO MASK_A: MASK_A13 Mask         */
+#define SGPIO_MASK_A_MASK_A14_Pos                             14                                                        /*!< SGPIO MASK_A: MASK_A14 Position     */
+#define SGPIO_MASK_A_MASK_A14_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A14_Pos)                     /*!< SGPIO MASK_A: MASK_A14 Mask         */
+#define SGPIO_MASK_A_MASK_A15_Pos                             15                                                        /*!< SGPIO MASK_A: MASK_A15 Position     */
+#define SGPIO_MASK_A_MASK_A15_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A15_Pos)                     /*!< SGPIO MASK_A: MASK_A15 Mask         */
+#define SGPIO_MASK_A_MASK_A16_Pos                             16                                                        /*!< SGPIO MASK_A: MASK_A16 Position     */
+#define SGPIO_MASK_A_MASK_A16_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A16_Pos)                     /*!< SGPIO MASK_A: MASK_A16 Mask         */
+#define SGPIO_MASK_A_MASK_A17_Pos                             17                                                        /*!< SGPIO MASK_A: MASK_A17 Position     */
+#define SGPIO_MASK_A_MASK_A17_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A17_Pos)                     /*!< SGPIO MASK_A: MASK_A17 Mask         */
+#define SGPIO_MASK_A_MASK_A18_Pos                             18                                                        /*!< SGPIO MASK_A: MASK_A18 Position     */
+#define SGPIO_MASK_A_MASK_A18_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A18_Pos)                     /*!< SGPIO MASK_A: MASK_A18 Mask         */
+#define SGPIO_MASK_A_MASK_A19_Pos                             19                                                        /*!< SGPIO MASK_A: MASK_A19 Position     */
+#define SGPIO_MASK_A_MASK_A19_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A19_Pos)                     /*!< SGPIO MASK_A: MASK_A19 Mask         */
+#define SGPIO_MASK_A_MASK_A20_Pos                             20                                                        /*!< SGPIO MASK_A: MASK_A20 Position     */
+#define SGPIO_MASK_A_MASK_A20_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A20_Pos)                     /*!< SGPIO MASK_A: MASK_A20 Mask         */
+#define SGPIO_MASK_A_MASK_A21_Pos                             21                                                        /*!< SGPIO MASK_A: MASK_A21 Position     */
+#define SGPIO_MASK_A_MASK_A21_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A21_Pos)                     /*!< SGPIO MASK_A: MASK_A21 Mask         */
+#define SGPIO_MASK_A_MASK_A22_Pos                             22                                                        /*!< SGPIO MASK_A: MASK_A22 Position     */
+#define SGPIO_MASK_A_MASK_A22_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A22_Pos)                     /*!< SGPIO MASK_A: MASK_A22 Mask         */
+#define SGPIO_MASK_A_MASK_A23_Pos                             23                                                        /*!< SGPIO MASK_A: MASK_A23 Position     */
+#define SGPIO_MASK_A_MASK_A23_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A23_Pos)                     /*!< SGPIO MASK_A: MASK_A23 Mask         */
+#define SGPIO_MASK_A_MASK_A24_Pos                             24                                                        /*!< SGPIO MASK_A: MASK_A24 Position     */
+#define SGPIO_MASK_A_MASK_A24_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A24_Pos)                     /*!< SGPIO MASK_A: MASK_A24 Mask         */
+#define SGPIO_MASK_A_MASK_A25_Pos                             25                                                        /*!< SGPIO MASK_A: MASK_A25 Position     */
+#define SGPIO_MASK_A_MASK_A25_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A25_Pos)                     /*!< SGPIO MASK_A: MASK_A25 Mask         */
+#define SGPIO_MASK_A_MASK_A26_Pos                             26                                                        /*!< SGPIO MASK_A: MASK_A26 Position     */
+#define SGPIO_MASK_A_MASK_A26_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A26_Pos)                     /*!< SGPIO MASK_A: MASK_A26 Mask         */
+#define SGPIO_MASK_A_MASK_A27_Pos                             27                                                        /*!< SGPIO MASK_A: MASK_A27 Position     */
+#define SGPIO_MASK_A_MASK_A27_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A27_Pos)                     /*!< SGPIO MASK_A: MASK_A27 Mask         */
+#define SGPIO_MASK_A_MASK_A28_Pos                             28                                                        /*!< SGPIO MASK_A: MASK_A28 Position     */
+#define SGPIO_MASK_A_MASK_A28_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A28_Pos)                     /*!< SGPIO MASK_A: MASK_A28 Mask         */
+#define SGPIO_MASK_A_MASK_A29_Pos                             29                                                        /*!< SGPIO MASK_A: MASK_A29 Position     */
+#define SGPIO_MASK_A_MASK_A29_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A29_Pos)                     /*!< SGPIO MASK_A: MASK_A29 Mask         */
+#define SGPIO_MASK_A_MASK_A30_Pos                             30                                                        /*!< SGPIO MASK_A: MASK_A30 Position     */
+#define SGPIO_MASK_A_MASK_A30_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A30_Pos)                     /*!< SGPIO MASK_A: MASK_A30 Mask         */
+#define SGPIO_MASK_A_MASK_A31_Pos                             31                                                        /*!< SGPIO MASK_A: MASK_A31 Position     */
+#define SGPIO_MASK_A_MASK_A31_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A31_Pos)                     /*!< SGPIO MASK_A: MASK_A31 Mask         */
+
+// --------------------------------------  SGPIO_MASK_H  ------------------------------------------
+#define SGPIO_MASK_H_MASK_H0_Pos                              0                                                         /*!< SGPIO MASK_H: MASK_H0 Position      */
+#define SGPIO_MASK_H_MASK_H0_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H0_Pos)                      /*!< SGPIO MASK_H: MASK_H0 Mask          */
+#define SGPIO_MASK_H_MASK_H1_Pos                              1                                                         /*!< SGPIO MASK_H: MASK_H1 Position      */
+#define SGPIO_MASK_H_MASK_H1_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H1_Pos)                      /*!< SGPIO MASK_H: MASK_H1 Mask          */
+#define SGPIO_MASK_H_MASK_H2_Pos                              2                                                         /*!< SGPIO MASK_H: MASK_H2 Position      */
+#define SGPIO_MASK_H_MASK_H2_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H2_Pos)                      /*!< SGPIO MASK_H: MASK_H2 Mask          */
+#define SGPIO_MASK_H_MASK_H3_Pos                              3                                                         /*!< SGPIO MASK_H: MASK_H3 Position      */
+#define SGPIO_MASK_H_MASK_H3_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H3_Pos)                      /*!< SGPIO MASK_H: MASK_H3 Mask          */
+#define SGPIO_MASK_H_MASK_H4_Pos                              4                                                         /*!< SGPIO MASK_H: MASK_H4 Position      */
+#define SGPIO_MASK_H_MASK_H4_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H4_Pos)                      /*!< SGPIO MASK_H: MASK_H4 Mask          */
+#define SGPIO_MASK_H_MASK_H5_Pos                              5                                                         /*!< SGPIO MASK_H: MASK_H5 Position      */
+#define SGPIO_MASK_H_MASK_H5_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H5_Pos)                      /*!< SGPIO MASK_H: MASK_H5 Mask          */
+#define SGPIO_MASK_H_MASK_H6_Pos                              6                                                         /*!< SGPIO MASK_H: MASK_H6 Position      */
+#define SGPIO_MASK_H_MASK_H6_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H6_Pos)                      /*!< SGPIO MASK_H: MASK_H6 Mask          */
+#define SGPIO_MASK_H_MASK_H7_Pos                              7                                                         /*!< SGPIO MASK_H: MASK_H7 Position      */
+#define SGPIO_MASK_H_MASK_H7_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H7_Pos)                      /*!< SGPIO MASK_H: MASK_H7 Mask          */
+#define SGPIO_MASK_H_MASK_H8_Pos                              8                                                         /*!< SGPIO MASK_H: MASK_H8 Position      */
+#define SGPIO_MASK_H_MASK_H8_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H8_Pos)                      /*!< SGPIO MASK_H: MASK_H8 Mask          */
+#define SGPIO_MASK_H_MASK_H9_Pos                              9                                                         /*!< SGPIO MASK_H: MASK_H9 Position      */
+#define SGPIO_MASK_H_MASK_H9_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H9_Pos)                      /*!< SGPIO MASK_H: MASK_H9 Mask          */
+#define SGPIO_MASK_H_MASK_H10_Pos                             10                                                        /*!< SGPIO MASK_H: MASK_H10 Position     */
+#define SGPIO_MASK_H_MASK_H10_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H10_Pos)                     /*!< SGPIO MASK_H: MASK_H10 Mask         */
+#define SGPIO_MASK_H_MASK_H11_Pos                             11                                                        /*!< SGPIO MASK_H: MASK_H11 Position     */
+#define SGPIO_MASK_H_MASK_H11_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H11_Pos)                     /*!< SGPIO MASK_H: MASK_H11 Mask         */
+#define SGPIO_MASK_H_MASK_H12_Pos                             12                                                        /*!< SGPIO MASK_H: MASK_H12 Position     */
+#define SGPIO_MASK_H_MASK_H12_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H12_Pos)                     /*!< SGPIO MASK_H: MASK_H12 Mask         */
+#define SGPIO_MASK_H_MASK_H13_Pos                             13                                                        /*!< SGPIO MASK_H: MASK_H13 Position     */
+#define SGPIO_MASK_H_MASK_H13_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H13_Pos)                     /*!< SGPIO MASK_H: MASK_H13 Mask         */
+#define SGPIO_MASK_H_MASK_H14_Pos                             14                                                        /*!< SGPIO MASK_H: MASK_H14 Position     */
+#define SGPIO_MASK_H_MASK_H14_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H14_Pos)                     /*!< SGPIO MASK_H: MASK_H14 Mask         */
+#define SGPIO_MASK_H_MASK_H15_Pos                             15                                                        /*!< SGPIO MASK_H: MASK_H15 Position     */
+#define SGPIO_MASK_H_MASK_H15_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H15_Pos)                     /*!< SGPIO MASK_H: MASK_H15 Mask         */
+#define SGPIO_MASK_H_MASK_H16_Pos                             16                                                        /*!< SGPIO MASK_H: MASK_H16 Position     */
+#define SGPIO_MASK_H_MASK_H16_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H16_Pos)                     /*!< SGPIO MASK_H: MASK_H16 Mask         */
+#define SGPIO_MASK_H_MASK_H17_Pos                             17                                                        /*!< SGPIO MASK_H: MASK_H17 Position     */
+#define SGPIO_MASK_H_MASK_H17_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H17_Pos)                     /*!< SGPIO MASK_H: MASK_H17 Mask         */
+#define SGPIO_MASK_H_MASK_H18_Pos                             18                                                        /*!< SGPIO MASK_H: MASK_H18 Position     */
+#define SGPIO_MASK_H_MASK_H18_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H18_Pos)                     /*!< SGPIO MASK_H: MASK_H18 Mask         */
+#define SGPIO_MASK_H_MASK_H19_Pos                             19                                                        /*!< SGPIO MASK_H: MASK_H19 Position     */
+#define SGPIO_MASK_H_MASK_H19_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H19_Pos)                     /*!< SGPIO MASK_H: MASK_H19 Mask         */
+#define SGPIO_MASK_H_MASK_H20_Pos                             20                                                        /*!< SGPIO MASK_H: MASK_H20 Position     */
+#define SGPIO_MASK_H_MASK_H20_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H20_Pos)                     /*!< SGPIO MASK_H: MASK_H20 Mask         */
+#define SGPIO_MASK_H_MASK_H21_Pos                             21                                                        /*!< SGPIO MASK_H: MASK_H21 Position     */
+#define SGPIO_MASK_H_MASK_H21_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H21_Pos)                     /*!< SGPIO MASK_H: MASK_H21 Mask         */
+#define SGPIO_MASK_H_MASK_H22_Pos                             22                                                        /*!< SGPIO MASK_H: MASK_H22 Position     */
+#define SGPIO_MASK_H_MASK_H22_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H22_Pos)                     /*!< SGPIO MASK_H: MASK_H22 Mask         */
+#define SGPIO_MASK_H_MASK_H23_Pos                             23                                                        /*!< SGPIO MASK_H: MASK_H23 Position     */
+#define SGPIO_MASK_H_MASK_H23_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H23_Pos)                     /*!< SGPIO MASK_H: MASK_H23 Mask         */
+#define SGPIO_MASK_H_MASK_H24_Pos                             24                                                        /*!< SGPIO MASK_H: MASK_H24 Position     */
+#define SGPIO_MASK_H_MASK_H24_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H24_Pos)                     /*!< SGPIO MASK_H: MASK_H24 Mask         */
+#define SGPIO_MASK_H_MASK_H25_Pos                             25                                                        /*!< SGPIO MASK_H: MASK_H25 Position     */
+#define SGPIO_MASK_H_MASK_H25_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H25_Pos)                     /*!< SGPIO MASK_H: MASK_H25 Mask         */
+#define SGPIO_MASK_H_MASK_H26_Pos                             26                                                        /*!< SGPIO MASK_H: MASK_H26 Position     */
+#define SGPIO_MASK_H_MASK_H26_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H26_Pos)                     /*!< SGPIO MASK_H: MASK_H26 Mask         */
+#define SGPIO_MASK_H_MASK_H27_Pos                             27                                                        /*!< SGPIO MASK_H: MASK_H27 Position     */
+#define SGPIO_MASK_H_MASK_H27_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H27_Pos)                     /*!< SGPIO MASK_H: MASK_H27 Mask         */
+#define SGPIO_MASK_H_MASK_H28_Pos                             28                                                        /*!< SGPIO MASK_H: MASK_H28 Position     */
+#define SGPIO_MASK_H_MASK_H28_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H28_Pos)                     /*!< SGPIO MASK_H: MASK_H28 Mask         */
+#define SGPIO_MASK_H_MASK_H29_Pos                             29                                                        /*!< SGPIO MASK_H: MASK_H29 Position     */
+#define SGPIO_MASK_H_MASK_H29_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H29_Pos)                     /*!< SGPIO MASK_H: MASK_H29 Mask         */
+#define SGPIO_MASK_H_MASK_H30_Pos                             30                                                        /*!< SGPIO MASK_H: MASK_H30 Position     */
+#define SGPIO_MASK_H_MASK_H30_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H30_Pos)                     /*!< SGPIO MASK_H: MASK_H30 Mask         */
+#define SGPIO_MASK_H_MASK_H31_Pos                             31                                                        /*!< SGPIO MASK_H: MASK_H31 Position     */
+#define SGPIO_MASK_H_MASK_H31_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H31_Pos)                     /*!< SGPIO MASK_H: MASK_H31 Mask         */
+
+// --------------------------------------  SGPIO_MASK_I  ------------------------------------------
+#define SGPIO_MASK_I_MASK_I0_Pos                              0                                                         /*!< SGPIO MASK_I: MASK_I0 Position      */
+#define SGPIO_MASK_I_MASK_I0_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I0_Pos)                      /*!< SGPIO MASK_I: MASK_I0 Mask          */
+#define SGPIO_MASK_I_MASK_I1_Pos                              1                                                         /*!< SGPIO MASK_I: MASK_I1 Position      */
+#define SGPIO_MASK_I_MASK_I1_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I1_Pos)                      /*!< SGPIO MASK_I: MASK_I1 Mask          */
+#define SGPIO_MASK_I_MASK_I2_Pos                              2                                                         /*!< SGPIO MASK_I: MASK_I2 Position      */
+#define SGPIO_MASK_I_MASK_I2_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I2_Pos)                      /*!< SGPIO MASK_I: MASK_I2 Mask          */
+#define SGPIO_MASK_I_MASK_I3_Pos                              3                                                         /*!< SGPIO MASK_I: MASK_I3 Position      */
+#define SGPIO_MASK_I_MASK_I3_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I3_Pos)                      /*!< SGPIO MASK_I: MASK_I3 Mask          */
+#define SGPIO_MASK_I_MASK_I4_Pos                              4                                                         /*!< SGPIO MASK_I: MASK_I4 Position      */
+#define SGPIO_MASK_I_MASK_I4_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I4_Pos)                      /*!< SGPIO MASK_I: MASK_I4 Mask          */
+#define SGPIO_MASK_I_MASK_I5_Pos                              5                                                         /*!< SGPIO MASK_I: MASK_I5 Position      */
+#define SGPIO_MASK_I_MASK_I5_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I5_Pos)                      /*!< SGPIO MASK_I: MASK_I5 Mask          */
+#define SGPIO_MASK_I_MASK_I6_Pos                              6                                                         /*!< SGPIO MASK_I: MASK_I6 Position      */
+#define SGPIO_MASK_I_MASK_I6_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I6_Pos)                      /*!< SGPIO MASK_I: MASK_I6 Mask          */
+#define SGPIO_MASK_I_MASK_I7_Pos                              7                                                         /*!< SGPIO MASK_I: MASK_I7 Position      */
+#define SGPIO_MASK_I_MASK_I7_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I7_Pos)                      /*!< SGPIO MASK_I: MASK_I7 Mask          */
+#define SGPIO_MASK_I_MASK_I8_Pos                              8                                                         /*!< SGPIO MASK_I: MASK_I8 Position      */
+#define SGPIO_MASK_I_MASK_I8_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I8_Pos)                      /*!< SGPIO MASK_I: MASK_I8 Mask          */
+#define SGPIO_MASK_I_MASK_I9_Pos                              9                                                         /*!< SGPIO MASK_I: MASK_I9 Position      */
+#define SGPIO_MASK_I_MASK_I9_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I9_Pos)                      /*!< SGPIO MASK_I: MASK_I9 Mask          */
+#define SGPIO_MASK_I_MASK_I10_Pos                             10                                                        /*!< SGPIO MASK_I: MASK_I10 Position     */
+#define SGPIO_MASK_I_MASK_I10_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I10_Pos)                     /*!< SGPIO MASK_I: MASK_I10 Mask         */
+#define SGPIO_MASK_I_MASK_I11_Pos                             11                                                        /*!< SGPIO MASK_I: MASK_I11 Position     */
+#define SGPIO_MASK_I_MASK_I11_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I11_Pos)                     /*!< SGPIO MASK_I: MASK_I11 Mask         */
+#define SGPIO_MASK_I_MASK_I12_Pos                             12                                                        /*!< SGPIO MASK_I: MASK_I12 Position     */
+#define SGPIO_MASK_I_MASK_I12_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I12_Pos)                     /*!< SGPIO MASK_I: MASK_I12 Mask         */
+#define SGPIO_MASK_I_MASK_I13_Pos                             13                                                        /*!< SGPIO MASK_I: MASK_I13 Position     */
+#define SGPIO_MASK_I_MASK_I13_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I13_Pos)                     /*!< SGPIO MASK_I: MASK_I13 Mask         */
+#define SGPIO_MASK_I_MASK_I14_Pos                             14                                                        /*!< SGPIO MASK_I: MASK_I14 Position     */
+#define SGPIO_MASK_I_MASK_I14_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I14_Pos)                     /*!< SGPIO MASK_I: MASK_I14 Mask         */
+#define SGPIO_MASK_I_MASK_I15_Pos                             15                                                        /*!< SGPIO MASK_I: MASK_I15 Position     */
+#define SGPIO_MASK_I_MASK_I15_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I15_Pos)                     /*!< SGPIO MASK_I: MASK_I15 Mask         */
+#define SGPIO_MASK_I_MASK_I16_Pos                             16                                                        /*!< SGPIO MASK_I: MASK_I16 Position     */
+#define SGPIO_MASK_I_MASK_I16_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I16_Pos)                     /*!< SGPIO MASK_I: MASK_I16 Mask         */
+#define SGPIO_MASK_I_MASK_I17_Pos                             17                                                        /*!< SGPIO MASK_I: MASK_I17 Position     */
+#define SGPIO_MASK_I_MASK_I17_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I17_Pos)                     /*!< SGPIO MASK_I: MASK_I17 Mask         */
+#define SGPIO_MASK_I_MASK_I18_Pos                             18                                                        /*!< SGPIO MASK_I: MASK_I18 Position     */
+#define SGPIO_MASK_I_MASK_I18_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I18_Pos)                     /*!< SGPIO MASK_I: MASK_I18 Mask         */
+#define SGPIO_MASK_I_MASK_I19_Pos                             19                                                        /*!< SGPIO MASK_I: MASK_I19 Position     */
+#define SGPIO_MASK_I_MASK_I19_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I19_Pos)                     /*!< SGPIO MASK_I: MASK_I19 Mask         */
+#define SGPIO_MASK_I_MASK_I20_Pos                             20                                                        /*!< SGPIO MASK_I: MASK_I20 Position     */
+#define SGPIO_MASK_I_MASK_I20_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I20_Pos)                     /*!< SGPIO MASK_I: MASK_I20 Mask         */
+#define SGPIO_MASK_I_MASK_I21_Pos                             21                                                        /*!< SGPIO MASK_I: MASK_I21 Position     */
+#define SGPIO_MASK_I_MASK_I21_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I21_Pos)                     /*!< SGPIO MASK_I: MASK_I21 Mask         */
+#define SGPIO_MASK_I_MASK_I22_Pos                             22                                                        /*!< SGPIO MASK_I: MASK_I22 Position     */
+#define SGPIO_MASK_I_MASK_I22_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I22_Pos)                     /*!< SGPIO MASK_I: MASK_I22 Mask         */
+#define SGPIO_MASK_I_MASK_I23_Pos                             23                                                        /*!< SGPIO MASK_I: MASK_I23 Position     */
+#define SGPIO_MASK_I_MASK_I23_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I23_Pos)                     /*!< SGPIO MASK_I: MASK_I23 Mask         */
+#define SGPIO_MASK_I_MASK_I24_Pos                             24                                                        /*!< SGPIO MASK_I: MASK_I24 Position     */
+#define SGPIO_MASK_I_MASK_I24_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I24_Pos)                     /*!< SGPIO MASK_I: MASK_I24 Mask         */
+#define SGPIO_MASK_I_MASK_I25_Pos                             25                                                        /*!< SGPIO MASK_I: MASK_I25 Position     */
+#define SGPIO_MASK_I_MASK_I25_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I25_Pos)                     /*!< SGPIO MASK_I: MASK_I25 Mask         */
+#define SGPIO_MASK_I_MASK_I26_Pos                             26                                                        /*!< SGPIO MASK_I: MASK_I26 Position     */
+#define SGPIO_MASK_I_MASK_I26_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I26_Pos)                     /*!< SGPIO MASK_I: MASK_I26 Mask         */
+#define SGPIO_MASK_I_MASK_I27_Pos                             27                                                        /*!< SGPIO MASK_I: MASK_I27 Position     */
+#define SGPIO_MASK_I_MASK_I27_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I27_Pos)                     /*!< SGPIO MASK_I: MASK_I27 Mask         */
+#define SGPIO_MASK_I_MASK_I28_Pos                             28                                                        /*!< SGPIO MASK_I: MASK_I28 Position     */
+#define SGPIO_MASK_I_MASK_I28_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I28_Pos)                     /*!< SGPIO MASK_I: MASK_I28 Mask         */
+#define SGPIO_MASK_I_MASK_I29_Pos                             29                                                        /*!< SGPIO MASK_I: MASK_I29 Position     */
+#define SGPIO_MASK_I_MASK_I29_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I29_Pos)                     /*!< SGPIO MASK_I: MASK_I29 Mask         */
+#define SGPIO_MASK_I_MASK_I30_Pos                             30                                                        /*!< SGPIO MASK_I: MASK_I30 Position     */
+#define SGPIO_MASK_I_MASK_I30_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I30_Pos)                     /*!< SGPIO MASK_I: MASK_I30 Mask         */
+#define SGPIO_MASK_I_MASK_I31_Pos                             31                                                        /*!< SGPIO MASK_I: MASK_I31 Position     */
+#define SGPIO_MASK_I_MASK_I31_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I31_Pos)                     /*!< SGPIO MASK_I: MASK_I31 Mask         */
+
+// --------------------------------------  SGPIO_MASK_P  ------------------------------------------
+#define SGPIO_MASK_P_MASK_P0_Pos                              0                                                         /*!< SGPIO MASK_P: MASK_P0 Position      */
+#define SGPIO_MASK_P_MASK_P0_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P0_Pos)                      /*!< SGPIO MASK_P: MASK_P0 Mask          */
+#define SGPIO_MASK_P_MASK_P1_Pos                              1                                                         /*!< SGPIO MASK_P: MASK_P1 Position      */
+#define SGPIO_MASK_P_MASK_P1_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P1_Pos)                      /*!< SGPIO MASK_P: MASK_P1 Mask          */
+#define SGPIO_MASK_P_MASK_P2_Pos                              2                                                         /*!< SGPIO MASK_P: MASK_P2 Position      */
+#define SGPIO_MASK_P_MASK_P2_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P2_Pos)                      /*!< SGPIO MASK_P: MASK_P2 Mask          */
+#define SGPIO_MASK_P_MASK_P3_Pos                              3                                                         /*!< SGPIO MASK_P: MASK_P3 Position      */
+#define SGPIO_MASK_P_MASK_P3_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P3_Pos)                      /*!< SGPIO MASK_P: MASK_P3 Mask          */
+#define SGPIO_MASK_P_MASK_P4_Pos                              4                                                         /*!< SGPIO MASK_P: MASK_P4 Position      */
+#define SGPIO_MASK_P_MASK_P4_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P4_Pos)                      /*!< SGPIO MASK_P: MASK_P4 Mask          */
+#define SGPIO_MASK_P_MASK_P5_Pos                              5                                                         /*!< SGPIO MASK_P: MASK_P5 Position      */
+#define SGPIO_MASK_P_MASK_P5_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P5_Pos)                      /*!< SGPIO MASK_P: MASK_P5 Mask          */
+#define SGPIO_MASK_P_MASK_P6_Pos                              6                                                         /*!< SGPIO MASK_P: MASK_P6 Position      */
+#define SGPIO_MASK_P_MASK_P6_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P6_Pos)                      /*!< SGPIO MASK_P: MASK_P6 Mask          */
+#define SGPIO_MASK_P_MASK_P7_Pos                              7                                                         /*!< SGPIO MASK_P: MASK_P7 Position      */
+#define SGPIO_MASK_P_MASK_P7_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P7_Pos)                      /*!< SGPIO MASK_P: MASK_P7 Mask          */
+#define SGPIO_MASK_P_MASK_P8_Pos                              8                                                         /*!< SGPIO MASK_P: MASK_P8 Position      */
+#define SGPIO_MASK_P_MASK_P8_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P8_Pos)                      /*!< SGPIO MASK_P: MASK_P8 Mask          */
+#define SGPIO_MASK_P_MASK_P9_Pos                              9                                                         /*!< SGPIO MASK_P: MASK_P9 Position      */
+#define SGPIO_MASK_P_MASK_P9_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P9_Pos)                      /*!< SGPIO MASK_P: MASK_P9 Mask          */
+#define SGPIO_MASK_P_MASK_P10_Pos                             10                                                        /*!< SGPIO MASK_P: MASK_P10 Position     */
+#define SGPIO_MASK_P_MASK_P10_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P10_Pos)                     /*!< SGPIO MASK_P: MASK_P10 Mask         */
+#define SGPIO_MASK_P_MASK_P11_Pos                             11                                                        /*!< SGPIO MASK_P: MASK_P11 Position     */
+#define SGPIO_MASK_P_MASK_P11_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P11_Pos)                     /*!< SGPIO MASK_P: MASK_P11 Mask         */
+#define SGPIO_MASK_P_MASK_P12_Pos                             12                                                        /*!< SGPIO MASK_P: MASK_P12 Position     */
+#define SGPIO_MASK_P_MASK_P12_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P12_Pos)                     /*!< SGPIO MASK_P: MASK_P12 Mask         */
+#define SGPIO_MASK_P_MASK_P13_Pos                             13                                                        /*!< SGPIO MASK_P: MASK_P13 Position     */
+#define SGPIO_MASK_P_MASK_P13_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P13_Pos)                     /*!< SGPIO MASK_P: MASK_P13 Mask         */
+#define SGPIO_MASK_P_MASK_P14_Pos                             14                                                        /*!< SGPIO MASK_P: MASK_P14 Position     */
+#define SGPIO_MASK_P_MASK_P14_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P14_Pos)                     /*!< SGPIO MASK_P: MASK_P14 Mask         */
+#define SGPIO_MASK_P_MASK_P15_Pos                             15                                                        /*!< SGPIO MASK_P: MASK_P15 Position     */
+#define SGPIO_MASK_P_MASK_P15_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P15_Pos)                     /*!< SGPIO MASK_P: MASK_P15 Mask         */
+#define SGPIO_MASK_P_MASK_P16_Pos                             16                                                        /*!< SGPIO MASK_P: MASK_P16 Position     */
+#define SGPIO_MASK_P_MASK_P16_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P16_Pos)                     /*!< SGPIO MASK_P: MASK_P16 Mask         */
+#define SGPIO_MASK_P_MASK_P17_Pos                             17                                                        /*!< SGPIO MASK_P: MASK_P17 Position     */
+#define SGPIO_MASK_P_MASK_P17_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P17_Pos)                     /*!< SGPIO MASK_P: MASK_P17 Mask         */
+#define SGPIO_MASK_P_MASK_P18_Pos                             18                                                        /*!< SGPIO MASK_P: MASK_P18 Position     */
+#define SGPIO_MASK_P_MASK_P18_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P18_Pos)                     /*!< SGPIO MASK_P: MASK_P18 Mask         */
+#define SGPIO_MASK_P_MASK_P19_Pos                             19                                                        /*!< SGPIO MASK_P: MASK_P19 Position     */
+#define SGPIO_MASK_P_MASK_P19_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P19_Pos)                     /*!< SGPIO MASK_P: MASK_P19 Mask         */
+#define SGPIO_MASK_P_MASK_P20_Pos                             20                                                        /*!< SGPIO MASK_P: MASK_P20 Position     */
+#define SGPIO_MASK_P_MASK_P20_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P20_Pos)                     /*!< SGPIO MASK_P: MASK_P20 Mask         */
+#define SGPIO_MASK_P_MASK_P21_Pos                             21                                                        /*!< SGPIO MASK_P: MASK_P21 Position     */
+#define SGPIO_MASK_P_MASK_P21_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P21_Pos)                     /*!< SGPIO MASK_P: MASK_P21 Mask         */
+#define SGPIO_MASK_P_MASK_P22_Pos                             22                                                        /*!< SGPIO MASK_P: MASK_P22 Position     */
+#define SGPIO_MASK_P_MASK_P22_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P22_Pos)                     /*!< SGPIO MASK_P: MASK_P22 Mask         */
+#define SGPIO_MASK_P_MASK_P23_Pos                             23                                                        /*!< SGPIO MASK_P: MASK_P23 Position     */
+#define SGPIO_MASK_P_MASK_P23_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P23_Pos)                     /*!< SGPIO MASK_P: MASK_P23 Mask         */
+#define SGPIO_MASK_P_MASK_P24_Pos                             24                                                        /*!< SGPIO MASK_P: MASK_P24 Position     */
+#define SGPIO_MASK_P_MASK_P24_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P24_Pos)                     /*!< SGPIO MASK_P: MASK_P24 Mask         */
+#define SGPIO_MASK_P_MASK_P25_Pos                             25                                                        /*!< SGPIO MASK_P: MASK_P25 Position     */
+#define SGPIO_MASK_P_MASK_P25_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P25_Pos)                     /*!< SGPIO MASK_P: MASK_P25 Mask         */
+#define SGPIO_MASK_P_MASK_P26_Pos                             26                                                        /*!< SGPIO MASK_P: MASK_P26 Position     */
+#define SGPIO_MASK_P_MASK_P26_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P26_Pos)                     /*!< SGPIO MASK_P: MASK_P26 Mask         */
+#define SGPIO_MASK_P_MASK_P27_Pos                             27                                                        /*!< SGPIO MASK_P: MASK_P27 Position     */
+#define SGPIO_MASK_P_MASK_P27_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P27_Pos)                     /*!< SGPIO MASK_P: MASK_P27 Mask         */
+#define SGPIO_MASK_P_MASK_P28_Pos                             28                                                        /*!< SGPIO MASK_P: MASK_P28 Position     */
+#define SGPIO_MASK_P_MASK_P28_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P28_Pos)                     /*!< SGPIO MASK_P: MASK_P28 Mask         */
+#define SGPIO_MASK_P_MASK_P29_Pos                             29                                                        /*!< SGPIO MASK_P: MASK_P29 Position     */
+#define SGPIO_MASK_P_MASK_P29_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P29_Pos)                     /*!< SGPIO MASK_P: MASK_P29 Mask         */
+#define SGPIO_MASK_P_MASK_P30_Pos                             30                                                        /*!< SGPIO MASK_P: MASK_P30 Position     */
+#define SGPIO_MASK_P_MASK_P30_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P30_Pos)                     /*!< SGPIO MASK_P: MASK_P30 Mask         */
+#define SGPIO_MASK_P_MASK_P31_Pos                             31                                                        /*!< SGPIO MASK_P: MASK_P31 Position     */
+#define SGPIO_MASK_P_MASK_P31_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P31_Pos)                     /*!< SGPIO MASK_P: MASK_P31 Mask         */
+
+// ------------------------------------  SGPIO_GPIO_INREG  ----------------------------------------
+#define SGPIO_GPIO_INREG_GPIO_IN0_Pos                         0                                                         /*!< SGPIO GPIO_INREG: GPIO_IN0 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN0_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN0 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN1_Pos                         1                                                         /*!< SGPIO GPIO_INREG: GPIO_IN1 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN1_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN1 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN2_Pos                         2                                                         /*!< SGPIO GPIO_INREG: GPIO_IN2 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN2_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN2 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN3_Pos                         3                                                         /*!< SGPIO GPIO_INREG: GPIO_IN3 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN3_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN3 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN4_Pos                         4                                                         /*!< SGPIO GPIO_INREG: GPIO_IN4 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN4_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN4 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN5_Pos                         5                                                         /*!< SGPIO GPIO_INREG: GPIO_IN5 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN5_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN5 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN6_Pos                         6                                                         /*!< SGPIO GPIO_INREG: GPIO_IN6 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN6_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN6 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN7_Pos                         7                                                         /*!< SGPIO GPIO_INREG: GPIO_IN7 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN7_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN7 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN8_Pos                         8                                                         /*!< SGPIO GPIO_INREG: GPIO_IN8 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN8_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN8 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN9_Pos                         9                                                         /*!< SGPIO GPIO_INREG: GPIO_IN9 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN9_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN9 Mask     */
+#define SGPIO_GPIO_INREG_GPIO_IN10_Pos                        10                                                        /*!< SGPIO GPIO_INREG: GPIO_IN10 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN10_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN10 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN11_Pos                        11                                                        /*!< SGPIO GPIO_INREG: GPIO_IN11 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN11_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN11 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN12_Pos                        12                                                        /*!< SGPIO GPIO_INREG: GPIO_IN12 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN12_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN12 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN13_Pos                        13                                                        /*!< SGPIO GPIO_INREG: GPIO_IN13 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN13_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN13 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN14_Pos                        14                                                        /*!< SGPIO GPIO_INREG: GPIO_IN14 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN14_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN14 Mask    */
+#define SGPIO_GPIO_INREG_GPIO_IN15_Pos                        15                                                        /*!< SGPIO GPIO_INREG: GPIO_IN15 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN15_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN15 Mask    */
+
+// ------------------------------------  SGPIO_GPIO_OUTREG  ---------------------------------------
+#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos                       0                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos                       1                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos                       2                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos                       3                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos                       4                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos                       5                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos                       6                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos                       7                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos                       8                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos                       9                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Mask   */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos                      10                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos                      11                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos                      12                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos                      13                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos                      14                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Mask  */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos                      15                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Mask  */
+
+// ------------------------------------  SGPIO_GPIO_OENREG  ---------------------------------------
+#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos                        0                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE0 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE0 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos                        1                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE1 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE1 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos                        2                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE2 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE2 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos                        3                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE3 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE3 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos                        4                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE4 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE4 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos                        5                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE5 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE5 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos                        6                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE6 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE6 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos                        7                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE7 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE7 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos                        8                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE8 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE8 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos                        9                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE9 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE9 Mask    */
+#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos                       10                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE10 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE10 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos                       11                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE11 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE11 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos                       12                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE12 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE12 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos                       13                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE13 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE13 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos                       14                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE14 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE14 Mask   */
+#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos                       15                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE15 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE15 Mask   */
+
+// -----------------------------------  SGPIO_CTRL_ENABLED  ---------------------------------------
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos                  0                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos                  1                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos                  2                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos                  3                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos                  4                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos                  5                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos                  6                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos                  7                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos                  8                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos                  9                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos                 10                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos                 11                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos                 12                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos                 13                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos                 14                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos                 15                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Mask */
+
+// -----------------------------------  SGPIO_CTRL_DISABLED  --------------------------------------
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos               0                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos               1                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos               2                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos               3                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos               4                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos               5                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos               6                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos               7                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos               8                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos               9                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos              10                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos              11                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos              12                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos              13                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos              14                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos              15                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_0  -----------------------------------------
+#define SGPIO_CLR_EN_0_CLR_SCI0_Pos                           0                                                         /*!< SGPIO CLR_EN_0: CLR_SCI0 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI0_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI0 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI1_Pos                           1                                                         /*!< SGPIO CLR_EN_0: CLR_SCI1 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI1_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI1 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI2_Pos                           2                                                         /*!< SGPIO CLR_EN_0: CLR_SCI2 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI2_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI2 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI3_Pos                           3                                                         /*!< SGPIO CLR_EN_0: CLR_SCI3 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI3_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI3 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI4_Pos                           4                                                         /*!< SGPIO CLR_EN_0: CLR_SCI4 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI4_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI4 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI5_Pos                           5                                                         /*!< SGPIO CLR_EN_0: CLR_SCI5 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI5_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI5 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI6_Pos                           6                                                         /*!< SGPIO CLR_EN_0: CLR_SCI6 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI6_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI6 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI7_Pos                           7                                                         /*!< SGPIO CLR_EN_0: CLR_SCI7 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI7_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI7 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI8_Pos                           8                                                         /*!< SGPIO CLR_EN_0: CLR_SCI8 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI8_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI8 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI9_Pos                           9                                                         /*!< SGPIO CLR_EN_0: CLR_SCI9 Position   */
+#define SGPIO_CLR_EN_0_CLR_SCI9_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI9 Mask       */
+#define SGPIO_CLR_EN_0_CLR_SCI10_Pos                          10                                                        /*!< SGPIO CLR_EN_0: CLR_SCI10 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI10_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI10 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI11_Pos                          11                                                        /*!< SGPIO CLR_EN_0: CLR_SCI11 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI11_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI11 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI12_Pos                          12                                                        /*!< SGPIO CLR_EN_0: CLR_SCI12 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI12_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI12 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI13_Pos                          13                                                        /*!< SGPIO CLR_EN_0: CLR_SCI13 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI13_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI13 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI14_Pos                          14                                                        /*!< SGPIO CLR_EN_0: CLR_SCI14 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI14_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI14 Mask      */
+#define SGPIO_CLR_EN_0_CLR_SCI15_Pos                          15                                                        /*!< SGPIO CLR_EN_0: CLR_SCI15 Position  */
+#define SGPIO_CLR_EN_0_CLR_SCI15_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI15 Mask      */
+
+// -------------------------------------  SGPIO_SET_EN_0  -----------------------------------------
+#define SGPIO_SET_EN_0_SET_SCI0_Pos                           0                                                         /*!< SGPIO SET_EN_0: SET_SCI0 Position   */
+#define SGPIO_SET_EN_0_SET_SCI0_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI0 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI1_Pos                           1                                                         /*!< SGPIO SET_EN_0: SET_SCI1 Position   */
+#define SGPIO_SET_EN_0_SET_SCI1_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI1 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI2_Pos                           2                                                         /*!< SGPIO SET_EN_0: SET_SCI2 Position   */
+#define SGPIO_SET_EN_0_SET_SCI2_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI2 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI3_Pos                           3                                                         /*!< SGPIO SET_EN_0: SET_SCI3 Position   */
+#define SGPIO_SET_EN_0_SET_SCI3_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI3 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI4_Pos                           4                                                         /*!< SGPIO SET_EN_0: SET_SCI4 Position   */
+#define SGPIO_SET_EN_0_SET_SCI4_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI4 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI5_Pos                           5                                                         /*!< SGPIO SET_EN_0: SET_SCI5 Position   */
+#define SGPIO_SET_EN_0_SET_SCI5_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI5 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI6_Pos                           6                                                         /*!< SGPIO SET_EN_0: SET_SCI6 Position   */
+#define SGPIO_SET_EN_0_SET_SCI6_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI6 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI7_Pos                           7                                                         /*!< SGPIO SET_EN_0: SET_SCI7 Position   */
+#define SGPIO_SET_EN_0_SET_SCI7_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI7 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI8_Pos                           8                                                         /*!< SGPIO SET_EN_0: SET_SCI8 Position   */
+#define SGPIO_SET_EN_0_SET_SCI8_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI8 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI9_Pos                           9                                                         /*!< SGPIO SET_EN_0: SET_SCI9 Position   */
+#define SGPIO_SET_EN_0_SET_SCI9_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI9 Mask       */
+#define SGPIO_SET_EN_0_SET_SCI10_Pos                          10                                                        /*!< SGPIO SET_EN_0: SET_SCI10 Position  */
+#define SGPIO_SET_EN_0_SET_SCI10_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI10 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI11_Pos                          11                                                        /*!< SGPIO SET_EN_0: SET_SCI11 Position  */
+#define SGPIO_SET_EN_0_SET_SCI11_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI11 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI12_Pos                          12                                                        /*!< SGPIO SET_EN_0: SET_SCI12 Position  */
+#define SGPIO_SET_EN_0_SET_SCI12_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI12 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI13_Pos                          13                                                        /*!< SGPIO SET_EN_0: SET_SCI13 Position  */
+#define SGPIO_SET_EN_0_SET_SCI13_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI13 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI14_Pos                          14                                                        /*!< SGPIO SET_EN_0: SET_SCI14 Position  */
+#define SGPIO_SET_EN_0_SET_SCI14_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI14 Mask      */
+#define SGPIO_SET_EN_0_SET_SCI15_Pos                          15                                                        /*!< SGPIO SET_EN_0: SET_SCI15 Position  */
+#define SGPIO_SET_EN_0_SET_SCI15_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI15 Mask      */
+
+// -------------------------------------  SGPIO_ENABLE_0  -----------------------------------------
+#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos                        0                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI0 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI0 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos                        1                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI1 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI1 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos                        2                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI2 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI2 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos                        3                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI3 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI3 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos                        4                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI4 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI4 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos                        5                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI5 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI5 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos                        6                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI6 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI6 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos                        7                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI7 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI7 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos                        8                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI8 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI8 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos                        9                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI9 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI9 Mask    */
+#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos                       10                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI10 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI10 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos                       11                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI11 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI11 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos                       12                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI12 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI12 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos                       13                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI13 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI13 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos                       14                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI14 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI14 Mask   */
+#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos                       15                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI15 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI15 Mask   */
+
+// -------------------------------------  SGPIO_STATUS_0  -----------------------------------------
+#define SGPIO_STATUS_0_STATUS_SCI0_Pos                        0                                                         /*!< SGPIO STATUS_0: STATUS_SCI0 Position */
+#define SGPIO_STATUS_0_STATUS_SCI0_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI0 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI1_Pos                        1                                                         /*!< SGPIO STATUS_0: STATUS_SCI1 Position */
+#define SGPIO_STATUS_0_STATUS_SCI1_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI1 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI2_Pos                        2                                                         /*!< SGPIO STATUS_0: STATUS_SCI2 Position */
+#define SGPIO_STATUS_0_STATUS_SCI2_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI2 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI3_Pos                        3                                                         /*!< SGPIO STATUS_0: STATUS_SCI3 Position */
+#define SGPIO_STATUS_0_STATUS_SCI3_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI3 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI4_Pos                        4                                                         /*!< SGPIO STATUS_0: STATUS_SCI4 Position */
+#define SGPIO_STATUS_0_STATUS_SCI4_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI4 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI5_Pos                        5                                                         /*!< SGPIO STATUS_0: STATUS_SCI5 Position */
+#define SGPIO_STATUS_0_STATUS_SCI5_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI5 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI6_Pos                        6                                                         /*!< SGPIO STATUS_0: STATUS_SCI6 Position */
+#define SGPIO_STATUS_0_STATUS_SCI6_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI6 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI7_Pos                        7                                                         /*!< SGPIO STATUS_0: STATUS_SCI7 Position */
+#define SGPIO_STATUS_0_STATUS_SCI7_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI7 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI8_Pos                        8                                                         /*!< SGPIO STATUS_0: STATUS_SCI8 Position */
+#define SGPIO_STATUS_0_STATUS_SCI8_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI8 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI9_Pos                        9                                                         /*!< SGPIO STATUS_0: STATUS_SCI9 Position */
+#define SGPIO_STATUS_0_STATUS_SCI9_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI9 Mask    */
+#define SGPIO_STATUS_0_STATUS_SCI10_Pos                       10                                                        /*!< SGPIO STATUS_0: STATUS_SCI10 Position */
+#define SGPIO_STATUS_0_STATUS_SCI10_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI10 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI11_Pos                       11                                                        /*!< SGPIO STATUS_0: STATUS_SCI11 Position */
+#define SGPIO_STATUS_0_STATUS_SCI11_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI11 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI12_Pos                       12                                                        /*!< SGPIO STATUS_0: STATUS_SCI12 Position */
+#define SGPIO_STATUS_0_STATUS_SCI12_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI12 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI13_Pos                       13                                                        /*!< SGPIO STATUS_0: STATUS_SCI13 Position */
+#define SGPIO_STATUS_0_STATUS_SCI13_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI13 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI14_Pos                       14                                                        /*!< SGPIO STATUS_0: STATUS_SCI14 Position */
+#define SGPIO_STATUS_0_STATUS_SCI14_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI14 Mask   */
+#define SGPIO_STATUS_0_STATUS_SCI15_Pos                       15                                                        /*!< SGPIO STATUS_0: STATUS_SCI15 Position */
+#define SGPIO_STATUS_0_STATUS_SCI15_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI15 Mask   */
+
+// -----------------------------------  SGPIO_CTR_STATUS_0  ---------------------------------------
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_0  ---------------------------------------
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_1  -----------------------------------------
+#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos                        0                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos                        1                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos                        2                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos                        3                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos                        4                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos                        5                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos                        6                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos                        7                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos                        8                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos                        9                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Mask    */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos                       10                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos                       11                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos                       12                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos                       13                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos                       14                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Mask   */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos                       15                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Mask   */
+
+// -------------------------------------  SGPIO_SET_EN_1  -----------------------------------------
+#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos                        0                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI0 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI0 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos                        1                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI1 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI1 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos                        2                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI2 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI2 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos                        3                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI3 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI3 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos                        4                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI4 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI4 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos                        5                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI5 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI5 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos                        6                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI6 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI6 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos                        7                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI7 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI7 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos                        8                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI8 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI8 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos                        9                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI9 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI9 Mask    */
+#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos                       10                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI10 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI10 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos                       11                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI11 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI11 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos                       12                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI12 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI12 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos                       13                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI13 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI13 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos                       14                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI14 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI14 Mask   */
+#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos                       15                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI15 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI15 Mask   */
+
+// -------------------------------------  SGPIO_ENABLE_1  -----------------------------------------
+#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos                        0                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI0 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI0 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos                        1                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI1 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI1 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos                        2                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI2 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI2 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos                        3                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI3 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI3 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos                        4                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI4 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI4 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos                        5                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI5 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI5 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos                        6                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI6 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI6 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos                        7                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI7 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI7 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos                        8                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI8 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI8 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos                        9                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI9 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI9 Mask    */
+#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos                       10                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI10 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI10 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos                       11                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI11 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI11 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos                       12                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI12 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI12 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos                       13                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI13 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI13 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos                       14                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI14 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI14 Mask   */
+#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos                       15                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI15 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI15 Mask   */
+
+// -------------------------------------  SGPIO_STATUS_1  -----------------------------------------
+#define SGPIO_STATUS_1_STATUS_CCI0_Pos                        0                                                         /*!< SGPIO STATUS_1: STATUS_CCI0 Position */
+#define SGPIO_STATUS_1_STATUS_CCI0_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI0 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI1_Pos                        1                                                         /*!< SGPIO STATUS_1: STATUS_CCI1 Position */
+#define SGPIO_STATUS_1_STATUS_CCI1_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI1 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI2_Pos                        2                                                         /*!< SGPIO STATUS_1: STATUS_CCI2 Position */
+#define SGPIO_STATUS_1_STATUS_CCI2_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI2 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI3_Pos                        3                                                         /*!< SGPIO STATUS_1: STATUS_CCI3 Position */
+#define SGPIO_STATUS_1_STATUS_CCI3_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI3 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI4_Pos                        4                                                         /*!< SGPIO STATUS_1: STATUS_CCI4 Position */
+#define SGPIO_STATUS_1_STATUS_CCI4_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI4 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI5_Pos                        5                                                         /*!< SGPIO STATUS_1: STATUS_CCI5 Position */
+#define SGPIO_STATUS_1_STATUS_CCI5_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI5 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI6_Pos                        6                                                         /*!< SGPIO STATUS_1: STATUS_CCI6 Position */
+#define SGPIO_STATUS_1_STATUS_CCI6_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI6 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI7_Pos                        7                                                         /*!< SGPIO STATUS_1: STATUS_CCI7 Position */
+#define SGPIO_STATUS_1_STATUS_CCI7_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI7 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI8_Pos                        8                                                         /*!< SGPIO STATUS_1: STATUS_CCI8 Position */
+#define SGPIO_STATUS_1_STATUS_CCI8_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI8 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI9_Pos                        9                                                         /*!< SGPIO STATUS_1: STATUS_CCI9 Position */
+#define SGPIO_STATUS_1_STATUS_CCI9_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI9 Mask    */
+#define SGPIO_STATUS_1_STATUS_CCI10_Pos                       10                                                        /*!< SGPIO STATUS_1: STATUS_CCI10 Position */
+#define SGPIO_STATUS_1_STATUS_CCI10_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI10 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI11_Pos                       11                                                        /*!< SGPIO STATUS_1: STATUS_CCI11 Position */
+#define SGPIO_STATUS_1_STATUS_CCI11_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI11 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI12_Pos                       12                                                        /*!< SGPIO STATUS_1: STATUS_CCI12 Position */
+#define SGPIO_STATUS_1_STATUS_CCI12_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI12 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI13_Pos                       13                                                        /*!< SGPIO STATUS_1: STATUS_CCI13 Position */
+#define SGPIO_STATUS_1_STATUS_CCI13_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI13 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI14_Pos                       14                                                        /*!< SGPIO STATUS_1: STATUS_CCI14 Position */
+#define SGPIO_STATUS_1_STATUS_CCI14_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI14 Mask   */
+#define SGPIO_STATUS_1_STATUS_CCI15_Pos                       15                                                        /*!< SGPIO STATUS_1: STATUS_CCI15 Position */
+#define SGPIO_STATUS_1_STATUS_CCI15_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI15 Mask   */
+
+// -----------------------------------  SGPIO_CTR_STATUS_1  ---------------------------------------
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_1  ---------------------------------------
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_2  -----------------------------------------
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos                       0                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos                       1                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos                       2                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos                       3                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos                       4                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos                       5                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos                       6                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos                       7                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos                       8                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos                       9                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Mask   */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos                      10                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos                      11                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos                      12                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos                      13                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos                      14                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Mask  */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos                      15                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Mask  */
+
+// -------------------------------------  SGPIO_SET_EN_2  -----------------------------------------
+#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos                        0                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI0 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI0 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos                        1                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI1 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI1 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos                        2                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI2 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI2 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos                        3                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI3 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI3 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos                        4                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI4 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI4 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos                        5                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI5 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI5 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos                        6                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI6 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI6 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos                        7                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI7 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI7 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos                        8                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI8 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI8 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos                        9                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI9 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI9 Mask    */
+#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos                       10                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI10 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI10 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos                       11                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI11 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI11 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos                       12                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI12 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI12 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos                       13                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI13 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI13 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos                       14                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI14 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI14 Mask   */
+#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos                       15                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI15 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI15 Mask   */
+
+// -------------------------------------  SGPIO_ENABLE_2  -----------------------------------------
+#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos                        0                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI0 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI0 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos                        1                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI1 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI1 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos                        2                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI2 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI2 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos                        3                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI3 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI3 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos                        4                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI4 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI4 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos                        5                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI5 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI5 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos                        6                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI6 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI6 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos                        7                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI7 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI7 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos                        8                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI8 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI8 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos                        9                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI9 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI9 Mask    */
+#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos                       10                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI10 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI10 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos                       11                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI11 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI11 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos                       12                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI12 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI12 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos                       13                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI13 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI13 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos                       14                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI14 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI14 Mask   */
+#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos                       15                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI15 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI15 Mask   */
+
+// -------------------------------------  SGPIO_STATUS_2  -----------------------------------------
+#define SGPIO_STATUS_2_STATUS_PMI0_Pos                        0                                                         /*!< SGPIO STATUS_2: STATUS_PMI0 Position */
+#define SGPIO_STATUS_2_STATUS_PMI0_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI0 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI1_Pos                        1                                                         /*!< SGPIO STATUS_2: STATUS_PMI1 Position */
+#define SGPIO_STATUS_2_STATUS_PMI1_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI1 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI2_Pos                        2                                                         /*!< SGPIO STATUS_2: STATUS_PMI2 Position */
+#define SGPIO_STATUS_2_STATUS_PMI2_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI2 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI3_Pos                        3                                                         /*!< SGPIO STATUS_2: STATUS_PMI3 Position */
+#define SGPIO_STATUS_2_STATUS_PMI3_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI3 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI4_Pos                        4                                                         /*!< SGPIO STATUS_2: STATUS_PMI4 Position */
+#define SGPIO_STATUS_2_STATUS_PMI4_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI4 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI5_Pos                        5                                                         /*!< SGPIO STATUS_2: STATUS_PMI5 Position */
+#define SGPIO_STATUS_2_STATUS_PMI5_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI5 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI6_Pos                        6                                                         /*!< SGPIO STATUS_2: STATUS_PMI6 Position */
+#define SGPIO_STATUS_2_STATUS_PMI6_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI6 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI7_Pos                        7                                                         /*!< SGPIO STATUS_2: STATUS_PMI7 Position */
+#define SGPIO_STATUS_2_STATUS_PMI7_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI7 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI8_Pos                        8                                                         /*!< SGPIO STATUS_2: STATUS_PMI8 Position */
+#define SGPIO_STATUS_2_STATUS_PMI8_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI8 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI9_Pos                        9                                                         /*!< SGPIO STATUS_2: STATUS_PMI9 Position */
+#define SGPIO_STATUS_2_STATUS_PMI9_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI9 Mask    */
+#define SGPIO_STATUS_2_STATUS_PMI10_Pos                       10                                                        /*!< SGPIO STATUS_2: STATUS_PMI10 Position */
+#define SGPIO_STATUS_2_STATUS_PMI10_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI10 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI11_Pos                       11                                                        /*!< SGPIO STATUS_2: STATUS_PMI11 Position */
+#define SGPIO_STATUS_2_STATUS_PMI11_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI11 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI12_Pos                       12                                                        /*!< SGPIO STATUS_2: STATUS_PMI12 Position */
+#define SGPIO_STATUS_2_STATUS_PMI12_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI12 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI13_Pos                       13                                                        /*!< SGPIO STATUS_2: STATUS_PMI13 Position */
+#define SGPIO_STATUS_2_STATUS_PMI13_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI13 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI14_Pos                       14                                                        /*!< SGPIO STATUS_2: STATUS_PMI14 Position */
+#define SGPIO_STATUS_2_STATUS_PMI14_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI14 Mask   */
+#define SGPIO_STATUS_2_STATUS_PMI15_Pos                       15                                                        /*!< SGPIO STATUS_2: STATUS_PMI15 Position */
+#define SGPIO_STATUS_2_STATUS_PMI15_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI15 Mask   */
+
+// -----------------------------------  SGPIO_CTR_STATUS_2  ---------------------------------------
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_2  ---------------------------------------
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Mask */
+
+// -------------------------------------  SGPIO_CLR_EN_3  -----------------------------------------
+#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos                       0                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos                       1                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos                       2                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos                       3                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos                       4                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos                       5                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos                       6                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos                       7                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos                       8                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos                       9                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Mask   */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos                      10                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos                      11                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos                      12                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos                      13                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos                      14                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Mask  */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos                      15                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Mask  */
+
+// -------------------------------------  SGPIO_SET_EN_3  -----------------------------------------
+#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos                       0                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI0 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI0 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos                       1                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI1 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI1 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos                       2                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI2 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI2 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos                       3                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI3 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI3 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos                       4                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI4 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI4 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos                       5                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI5 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI5 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos                       6                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI6 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI6 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos                       7                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI7 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI7 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos                       8                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI8 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI8 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos                       9                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI9 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI9 Mask   */
+#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos                      10                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI10 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI10 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos                      11                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI11 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI11 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos                      12                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI12 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI12 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos                      13                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI13 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI13 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos                      14                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI14 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI14 Mask  */
+#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos                      15                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI15 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI15 Mask  */
+
+// -------------------------------------  SGPIO_ENABLE_3  -----------------------------------------
+#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos                      0                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos                      1                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos                      2                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos                      3                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos                      4                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos                      5                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos                      6                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos                      7                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos                      8                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos                      9                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Mask  */
+#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos                     10                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos                     11                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos                     12                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos                     13                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos                     14                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos                     15                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Mask */
+
+// -------------------------------------  SGPIO_STATUS_3  -----------------------------------------
+#define SGPIO_STATUS_3_STATUS_INPI0_Pos                       0                                                         /*!< SGPIO STATUS_3: STATUS_INPI0 Position */
+#define SGPIO_STATUS_3_STATUS_INPI0_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI0 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI1_Pos                       1                                                         /*!< SGPIO STATUS_3: STATUS_INPI1 Position */
+#define SGPIO_STATUS_3_STATUS_INPI1_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI1 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI2_Pos                       2                                                         /*!< SGPIO STATUS_3: STATUS_INPI2 Position */
+#define SGPIO_STATUS_3_STATUS_INPI2_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI2 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI3_Pos                       3                                                         /*!< SGPIO STATUS_3: STATUS_INPI3 Position */
+#define SGPIO_STATUS_3_STATUS_INPI3_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI3 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI4_Pos                       4                                                         /*!< SGPIO STATUS_3: STATUS_INPI4 Position */
+#define SGPIO_STATUS_3_STATUS_INPI4_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI4 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI5_Pos                       5                                                         /*!< SGPIO STATUS_3: STATUS_INPI5 Position */
+#define SGPIO_STATUS_3_STATUS_INPI5_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI5 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI6_Pos                       6                                                         /*!< SGPIO STATUS_3: STATUS_INPI6 Position */
+#define SGPIO_STATUS_3_STATUS_INPI6_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI6 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI7_Pos                       7                                                         /*!< SGPIO STATUS_3: STATUS_INPI7 Position */
+#define SGPIO_STATUS_3_STATUS_INPI7_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI7 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI8_Pos                       8                                                         /*!< SGPIO STATUS_3: STATUS_INPI8 Position */
+#define SGPIO_STATUS_3_STATUS_INPI8_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI8 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI9_Pos                       9                                                         /*!< SGPIO STATUS_3: STATUS_INPI9 Position */
+#define SGPIO_STATUS_3_STATUS_INPI9_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI9 Mask   */
+#define SGPIO_STATUS_3_STATUS_INPI10_Pos                      10                                                        /*!< SGPIO STATUS_3: STATUS_INPI10 Position */
+#define SGPIO_STATUS_3_STATUS_INPI10_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI10 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI11_Pos                      11                                                        /*!< SGPIO STATUS_3: STATUS_INPI11 Position */
+#define SGPIO_STATUS_3_STATUS_INPI11_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI11 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI12_Pos                      12                                                        /*!< SGPIO STATUS_3: STATUS_INPI12 Position */
+#define SGPIO_STATUS_3_STATUS_INPI12_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI12 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI13_Pos                      13                                                        /*!< SGPIO STATUS_3: STATUS_INPI13 Position */
+#define SGPIO_STATUS_3_STATUS_INPI13_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI13 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI14_Pos                      14                                                        /*!< SGPIO STATUS_3: STATUS_INPI14 Position */
+#define SGPIO_STATUS_3_STATUS_INPI14_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI14 Mask  */
+#define SGPIO_STATUS_3_STATUS_INPI15_Pos                      15                                                        /*!< SGPIO STATUS_3: STATUS_INPI15 Position */
+#define SGPIO_STATUS_3_STATUS_INPI15_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI15 Mask  */
+
+// -----------------------------------  SGPIO_CTR_STATUS_3  ---------------------------------------
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Mask */
+
+// -----------------------------------  SGPIO_SET_STATUS_3  ---------------------------------------
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Mask */
+
+#endif
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 Peripheral memory map                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_SCT_BASE              0x40000000
+#define LPC_GPDMA_BASE            0x40002000
+#define LPC_SDMMC_BASE            0x40004000
+#define LPC_EMC_BASE              0x40005000
+#define LPC_USB0_BASE             0x40006000
+#define LPC_USB1_BASE             0x40007000
+#define LPC_LCD_BASE              0x40008000
+#define LPC_ETHERNET_BASE         0x40010000
+#define LPC_ATIMER_BASE           0x40040000
+#define LPC_REGFILE_BASE          0x40041000
+#define LPC_PMC_BASE              0x40042000
+#define LPC_CREG_BASE             0x40043000
+#define LPC_EVENTROUTER_BASE      0x40044000
+#define LPC_RTC_BASE              0x40046000
+#define LPC_CGU_BASE              0x40050000
+#define LPC_CCU1_BASE             0x40051000
+#define LPC_CCU2_BASE             0x40052000
+#define LPC_RGU_BASE              0x40053000
+#define LPC_WWDT_BASE             0x40080000
+#define LPC_USART0_BASE           0x40081000
+#define LPC_USART2_BASE           0x400C1000
+#define LPC_USART3_BASE           0x400C2000
+#define LPC_UART1_BASE            0x40082000
+#define LPC_SSP0_BASE             0x40083000
+#define LPC_SSP1_BASE             0x400C5000
+#define LPC_TIMER0_BASE           0x40084000
+#define LPC_TIMER1_BASE           0x40085000
+#define LPC_TIMER2_BASE           0x400C3000
+#define LPC_TIMER3_BASE           0x400C4000
+#define LPC_SCU_BASE              0x40086000
+#define LPC_GPIO_PIN_INT_BASE     0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
+#define LPC_MCPWM_BASE            0x400A0000
+#define LPC_I2C0_BASE             0x400A1000
+#define LPC_I2C1_BASE             0x400E0000
+#define LPC_I2S0_BASE             0x400A2000
+#define LPC_I2S1_BASE             0x400A3000
+#define LPC_C_CAN1_BASE           0x400A4000
+#define LPC_RITIMER_BASE          0x400C0000
+#define LPC_QEI_BASE              0x400C6000
+#define LPC_GIMA_BASE             0x400C7000
+#define LPC_DAC_BASE              0x400E1000
+#define LPC_C_CAN0_BASE           0x400E2000
+#define LPC_ADC0_BASE             0x400E3000
+#define LPC_ADC1_BASE             0x400E4000
+#define LPC_GPIO_PORT_BASE        0x400F4000
+#define LPC_SPI_BASE              0x40100000
+#define LPC_SGPIO_BASE            0x40101000
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                Peripheral declaration                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_SCT                   ((LPC_SCT_Type            *) LPC_SCT_BASE)
+#define LPC_GPDMA                 ((LPC_GPDMA_Type          *) LPC_GPDMA_BASE)
+#define LPC_SDMMC                 ((LPC_SDMMC_Type          *) LPC_SDMMC_BASE)
+#define LPC_EMC                   ((LPC_EMC_Type            *) LPC_EMC_BASE)
+#define LPC_USB0                  ((LPC_USB0_Type           *) LPC_USB0_BASE)
+#define LPC_USB1                  ((LPC_USB1_Type           *) LPC_USB1_BASE)
+#define LPC_LCD                   ((LPC_LCD_Type            *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((LPC_ETHERNET_Type       *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER                ((LPC_ATIMER_Type         *) LPC_ATIMER_BASE)
+#define LPC_REGFILE               ((LPC_REGFILE_Type        *) LPC_REGFILE_BASE)
+#define LPC_PMC                   ((LPC_PMC_Type            *) LPC_PMC_BASE)
+#define LPC_CREG                  ((LPC_CREG_Type           *) LPC_CREG_BASE)
+#define LPC_EVENTROUTER           ((LPC_EVENTROUTER_Type    *) LPC_EVENTROUTER_BASE)
+#define LPC_RTC                   ((LPC_RTC_Type            *) LPC_RTC_BASE)
+#define LPC_CGU                   ((LPC_CGU_Type            *) LPC_CGU_BASE)
+#define LPC_CCU1                  ((LPC_CCU1_Type           *) LPC_CCU1_BASE)
+#define LPC_CCU2                  ((LPC_CCU2_Type           *) LPC_CCU2_BASE)
+#define LPC_RGU                   ((LPC_RGU_Type            *) LPC_RGU_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
+#define LPC_USART0                ((LPC_USARTn_Type         *) LPC_USART0_BASE)
+#define LPC_USART2                ((LPC_USARTn_Type         *) LPC_USART2_BASE)
+#define LPC_USART3                ((LPC_USARTn_Type         *) LPC_USART3_BASE)
+#define LPC_UART1                 ((LPC_UART1_Type          *) LPC_UART1_BASE)
+#define LPC_SSP0                  ((LPC_SSPn_Type           *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSPn_Type           *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((LPC_TIMERn_Type         *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((LPC_TIMERn_Type         *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((LPC_TIMERn_Type         *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((LPC_TIMERn_Type         *) LPC_TIMER3_BASE)
+#define LPC_SCU                   ((LPC_SCU_Type            *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM                 ((LPC_MCPWM_Type          *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((LPC_I2Cn_Type           *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((LPC_I2Cn_Type           *) LPC_I2C1_BASE)
+#define LPC_I2S0                  ((LPC_I2Sn_Type           *) LPC_I2S0_BASE)
+#define LPC_I2S1                  ((LPC_I2Sn_Type           *) LPC_I2S1_BASE)
+#define LPC_C_CAN1                ((LPC_C_CANn_Type         *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
+#define LPC_QEI                   ((LPC_QEI_Type            *) LPC_QEI_BASE)
+#define LPC_GIMA                  ((LPC_GIMA_Type           *) LPC_GIMA_BASE)
+#define LPC_DAC                   ((LPC_DAC_Type            *) LPC_DAC_BASE)
+#define LPC_C_CAN0                ((LPC_C_CANn_Type         *) LPC_C_CAN0_BASE)
+#define LPC_ADC0                  ((LPC_ADCn_Type           *) LPC_ADC0_BASE)
+#define LPC_ADC1                  ((LPC_ADCn_Type           *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT             ((LPC_GPIO_PORT_Type      *) LPC_GPIO_PORT_BASE)
+#define LPC_SPI                   ((LPC_SPI_Type            *) LPC_SPI_BASE)
+#define LPC_SGPIO                 ((LPC_SGPIO_Type          *) LPC_SGPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC43xx */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif 
+
+
+#endif  // __LPC43xx_H__
+
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
new file mode 100644
index 0000000000..21204cc535
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
@@ -0,0 +1,33 @@
+/*********************************************************************** 
+ * $Id: fpu_enable.h 
+ * 
+ * Project: LPC43xx 
+ * 
+ * Description: fpu initialization routine header
+ * 
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ * 
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only  
+ * which provides customers with programming information regarding the  
+ * products. This software is supplied "AS IS" without any warranties.  
+ * NXP Semiconductors assumes no responsibility or liability for the 
+ * use of the software, conveys no license or title under any patent, 
+ * copyright, or mask work right to the product. NXP Semiconductors 
+ * reserves the right to make changes in the software without 
+ * notification. NXP Semiconductors also make no representation or 
+ * warranty that such application will be suitable for the specified 
+ * use without further testing or modification. 
+ **********************************************************************/
+
+#ifndef __FPU_ENABLE_H 
+#define __FPU_ENABLE_H 
+
+#if defined(__ARMCC_VERSION)
+void fpuEnable(void) __attribute__ ((section("BOOTSTRAP_CODE")));
+#else
+extern void fpuEnable(void);
+#endif
+
+#endif /* __FPU_ENABLE_H */
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
new file mode 100644
index 0000000000..5b121f1299
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
@@ -0,0 +1,29 @@
+/*********************************************************************** 
+ * $Id: fpu_init.h 
+ * 
+ * Project: LPC43xx 
+ * 
+ * Description: fpu initialization routine header
+ * 
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ * 
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only  
+ * which provides customers with programming information regarding the  
+ * products. This software is supplied "AS IS" without any warranties.  
+ * NXP Semiconductors assumes no responsibility or liability for the 
+ * use of the software, conveys no license or title under any patent, 
+ * copyright, or mask work right to the product. NXP Semiconductors 
+ * reserves the right to make changes in the software without 
+ * notification. NXP Semiconductors also make no representation or 
+ * warranty that such application will be suitable for the specified 
+ * use without further testing or modification. 
+ **********************************************************************/
+
+#ifndef __FPU_INIT_H 
+#define __FPU_INIT_H 
+
+void fpuInit(void);
+
+#endif /* __FPU_INIT_H */
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
new file mode 100644
index 0000000000..6046f8da34
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
@@ -0,0 +1,50 @@
+/**********************************************************************
+* $Id$		system_lpc43xx.h			2011-06-02
+*//**
+* @file		system_lpc43xx.h
+* @brief	Cortex-M3 Device System Header File for NXP lpc43xx Series.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __SYSTEM_lpc43xx_H
+#define __SYSTEM_lpc43xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_lpc43xx_H */
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
new file mode 100644
index 0000000000..8514f36120
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
@@ -0,0 +1,339 @@
+;/***********************************************************************
+; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
+; *
+; * Project: LPC43xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx 
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp              ; 0 Top of Stack
+                DCD     Reset_Handler             ; 1 Reset Handler
+                DCD     NMI_Handler               ; 2 NMI Handler
+                DCD     HardFault_Handler         ; 3 Hard Fault Handler
+                DCD     MemManage_Handler         ; 4 MPU Fault Handler
+                DCD     BusFault_Handler          ; 5 Bus Fault Handler
+                DCD     UsageFault_Handler        ; 6 Usage Fault Handler
+                DCD     Sign_Value                ; 7 Reserved
+                DCD     0                         ; 8 Reserved
+                DCD     0                         ; 9 Reserved
+                DCD     0                         ; 10 Reserved
+                DCD     SVC_Handler               ; 11 SVCall Handler
+                DCD     DebugMon_Handler          ; 12 Debug Monitor Handler
+                DCD     0                         ; 13 Reserved
+                DCD     PendSV_Handler            ; 14 PendSV Handler
+                DCD     SysTick_Handler           ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     DAC_IRQHandler            ; 16 D/A Converter
+                DCD     M0CORE_IRQHandler         ; 17 M0 Core
+                DCD     DMA_IRQHandler            ; 18 General Purpose DMA
+                DCD     EZH_IRQHandler            ; 19 EZH/EDM
+                DCD     FLASH_EEPROM_IRQHandler   ; 20 Reserved for Typhoon
+                DCD     ETH_IRQHandler            ; 21 Ethernet
+                DCD     SDIO_IRQHandler           ; 22 SD/MMC
+                DCD     LCD_IRQHandler            ; 23 LCD
+                DCD     USB0_IRQHandler           ; 24 USB0
+                DCD     USB1_IRQHandler           ; 25 USB1
+                DCD     SCT_IRQHandler            ; 26 State Configurable Timer
+                DCD     RIT_IRQHandler            ; 27 Repetitive Interrupt Timer
+                DCD     TIMER0_IRQHandler         ; 28 Timer0
+                DCD     TIMER1_IRQHandler         ; 29 Timer1
+                DCD     TIMER2_IRQHandler         ; 30 Timer2
+                DCD     TIMER3_IRQHandler         ; 31 Timer3
+                DCD     MCPWM_IRQHandler          ; 32 Motor Control PWM
+                DCD     ADC0_IRQHandler           ; 33 A/D Converter 0
+                DCD     I2C0_IRQHandler           ; 34 I2C0
+                DCD     I2C1_IRQHandler           ; 35 I2C1
+                DCD     SPI_IRQHandler            ; 36 SPI
+                DCD     ADC1_IRQHandler           ; 37 A/D Converter 1
+                DCD     SSP0_IRQHandler           ; 38 SSP0
+                DCD     SSP1_IRQHandler           ; 39 SSP1
+                DCD     UART0_IRQHandler          ; 40 UART0
+                DCD     UART1_IRQHandler          ; 41 UART1
+                DCD     UART2_IRQHandler          ; 42 UART2
+                DCD     UART3_IRQHandler          ; 43 UART3
+                DCD     I2S0_IRQHandler           ; 44 I2S0
+                DCD     I2S1_IRQHandler           ; 45 I2S1
+                DCD     SPIFI_IRQHandler          ; 46 SPI Flash Interface
+                DCD     SGPIO_IRQHandler          ; 47 SGPIO
+                DCD     GPIO0_IRQHandler          ; 48 GPIO0
+                DCD     GPIO1_IRQHandler          ; 49 GPIO1
+                DCD     GPIO2_IRQHandler          ; 50 GPIO2
+                DCD     GPIO3_IRQHandler          ; 51 GPIO3
+                DCD     GPIO4_IRQHandler          ; 52 GPIO4
+                DCD     GPIO5_IRQHandler          ; 53 GPIO5
+                DCD     GPIO6_IRQHandler          ; 54 GPIO6
+                DCD     GPIO7_IRQHandler          ; 55 GPIO7
+                DCD     GINT0_IRQHandler          ; 56 GINT0
+                DCD     GINT1_IRQHandler          ; 57 GINT1
+                DCD     EVRT_IRQHandler           ; 58 Event Router
+                DCD     CAN1_IRQHandler           ; 59 C_CAN1
+                DCD     0                         ; 60 Reserved
+                DCD     VADC_IRQHandler           ; 61 VADC
+                DCD     ATIMER_IRQHandler         ; 62 ATIMER
+                DCD     RTC_IRQHandler            ; 63 RTC
+                DCD     0                         ; 64 Reserved
+                DCD     WDT_IRQHandler            ; 65 WDT
+                DCD     M0s_IRQHandler            ; 66 M0s
+                DCD     CAN0_IRQHandler           ; 67 C_CAN0
+                DCD     QEI_IRQHandler            ; 68 QEI
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DAC_IRQHandler          [WEAK]
+                EXPORT  M0CORE_IRQHandler       [WEAK]
+                EXPORT  DMA_IRQHandler          [WEAK]
+                EXPORT  EZH_IRQHandler          [WEAK]
+                EXPORT  FLASH_EEPROM_IRQHandler [WEAK]
+                EXPORT  ETH_IRQHandler          [WEAK]
+                EXPORT  SDIO_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler          [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  USB1_IRQHandler         [WEAK]
+                EXPORT  SCT_IRQHandler          [WEAK]
+                EXPORT  RIT_IRQHandler          [WEAK]
+                EXPORT  TIMER0_IRQHandler       [WEAK]
+                EXPORT  TIMER1_IRQHandler       [WEAK]
+                EXPORT  TIMER2_IRQHandler       [WEAK]
+                EXPORT  TIMER3_IRQHandler       [WEAK]
+                EXPORT  MCPWM_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  SPI_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler         [WEAK]
+                EXPORT  SSP0_IRQHandler         [WEAK]
+                EXPORT  SSP1_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler        [WEAK]
+                EXPORT  UART1_IRQHandler        [WEAK]
+                EXPORT  UART2_IRQHandler        [WEAK]
+                EXPORT  UART3_IRQHandler        [WEAK]
+                EXPORT  I2S0_IRQHandler         [WEAK]
+                EXPORT  I2S1_IRQHandler         [WEAK]
+                EXPORT  SPIFI_IRQHandler        [WEAK]
+                EXPORT  SGPIO_IRQHandler        [WEAK]
+                EXPORT  GPIO0_IRQHandler        [WEAK]
+                EXPORT  GPIO1_IRQHandler        [WEAK]
+                EXPORT  GPIO2_IRQHandler        [WEAK]
+                EXPORT  GPIO3_IRQHandler        [WEAK]
+                EXPORT  GPIO4_IRQHandler        [WEAK]
+                EXPORT  GPIO5_IRQHandler        [WEAK]
+                EXPORT  GPIO6_IRQHandler        [WEAK]
+                EXPORT  GPIO7_IRQHandler        [WEAK]
+                EXPORT  GINT0_IRQHandler        [WEAK]
+                EXPORT  GINT1_IRQHandler        [WEAK]
+                EXPORT  EVRT_IRQHandler         [WEAK]
+                EXPORT  CAN1_IRQHandler         [WEAK]
+                EXPORT  VADC_IRQHandler         [WEAK]
+                EXPORT  ATIMER_IRQHandler       [WEAK]
+                EXPORT  RTC_IRQHandler          [WEAK]
+                EXPORT  WDT_IRQHandler          [WEAK]
+                EXPORT  M0s_IRQHandler          [WEAK]
+                EXPORT  CAN0_IRQHandler         [WEAK]
+                EXPORT  QEI_IRQHandler          [WEAK]
+
+DAC_IRQHandler
+M0CORE_IRQHandler
+DMA_IRQHandler
+EZH_IRQHandler
+FLASH_EEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+M0s_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                AREA    |.text|,CODE, READONLY
+getPC           PROC
+                EXPORT  getPC
+
+                MOV     R0,LR
+                BX      LR
+
+                ENDP
+
+                END
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
new file mode 100644
index 0000000000..c5a5dbefd9
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
@@ -0,0 +1,255 @@
+;/***********************************************************************
+; * $Id: startup_LPC43xx_M0.s 6473 2011-02-16 17:40:54Z nxp27266 $
+; *
+; * Project: LPC43xx CMSIS Package
+; *
+; * Description: Cortex-M0 Core Device Startup File for the NXP LPC43xx
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp                      ; 0 Top of Stack
+                DCD     Reset_Handler                  ; 1 Reset Handler
+                DCD     NMI_Handler                    ; 2 NMI Handler
+                DCD     HardFault_Handler              ; 3 Hard Fault Handler
+                DCD     0                                 ; 4 Reserved
+                DCD     0                                 ; 5 Reserved
+                DCD     0                                 ; 6 Reserved
+                DCD     0                                 ; 7 Reserved
+                DCD     0                                 ; 8 Reserved
+                DCD     0                                 ; 9 Reserved
+                DCD     0                                 ; 10 Reserved
+                DCD     SVC_Handler                    ; 11 SVCall Handler
+                DCD     DebugMon_Handler               ; 12 Debug Monitor Handler
+                DCD     0                                 ; 13 Reserved
+                DCD     PendSV_Handler                 ; 14 PendSV Handler
+                DCD     SysTick_Handler                ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     RTC_IRQHandler                 ; 16 RTC
+                DCD     M4CORE_IRQHandler              ; 17 M4 Core
+                DCD     DMA_IRQHandler                 ; 18 General Purpose DMA
+                DCD     0                                 ; 19 Reserved
+                DCD     FLASHEEPROMAT_IRQHandler       ; 20 ORed flash bank A, flash bank B, EEPROM, Atimer
+                DCD     ETH_IRQHandler                 ; 21 Ethernet
+                DCD     SDIO_IRQHandler                ; 22 SD/MMC
+                DCD     LCD_IRQHandler                 ; 23 LCD
+                DCD     USB0_IRQHandler                ; 24 USB0
+                DCD     USB1_IRQHandler                ; 25 USB1
+                DCD     SCT_IRQHandler                 ; 26 State Configurable Timer
+                DCD     RIT_OR_WWDT_IRQHandler         ; 27 Repetitive Interrupt Timer or WWDT
+                DCD     TIMER0_IRQHandler              ; 28 Timer0
+                DCD     GINT1_IRQHandler               ; 29 GPIO global interrupt 1
+                DCD     PIN_INT4_IRQHandler               ; 30 GPIO pin interrupt 4
+                DCD     TIMER3_IRQHandler              ; 31 Timer3
+                DCD     MCPWM_IRQHandler               ; 32 Motor control PWM
+                DCD     ADC0_IRQHandler                ; 33 ADC0
+                DCD     I2C0_OR_I2C1_IRQHandler        ; 34 I2C or I2C1
+                DCD     SGPIO_IRQHandler               ; 35 Serial GPIO
+                DCD     SPI_OR_DAC_IRQHandler          ; 36 SPI or DAC
+                DCD     ADC1_IRQHandler                ; 37 ADC1
+                DCD     SSP0_OR_SSP1_IRQHandler        ; 38 SSP0 or SSP1
+                DCD     EVENTROUTER_IRQHandler         ; 39 Event router
+                DCD     USART0_IRQHandler              ; 40 USART0
+                DCD     UART1_IRQHandler               ; 41 UART1/Modem
+                DCD     USART2_OR_C_CAN1_IRQHandler    ; 42 USART2 or C CAN1
+                DCD     USART3_IRQHandler              ; 43 USART3
+                DCD     I2S0_OR_I2S1_OR_QEI_IRQHandler ; 44 I2S0 or I2S1 or QEI
+                DCD     C_CAN0_IRQHandler              ; 45 C CAN0
+                DCD     0                                 ; 46 Reserved
+                DCD     0                                 ; 47 Reserved
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler\
+                PROC
+                EXPORT  Reset_Handler                    [WEAK]
+                IMPORT  __main
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler  PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+SVC_Handler  PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   RTC_IRQHandler                  [WEAK]
+                EXPORT   M4CORE_IRQHandler               [WEAK]
+                EXPORT   DMA_IRQHandler                  [WEAK]
+                EXPORT   FLASHEEPROMAT_IRQHandler        [WEAK]
+                EXPORT   ETH_IRQHandler                  [WEAK]
+                EXPORT   SDIO_IRQHandler                 [WEAK]
+                EXPORT   LCD_IRQHandler                  [WEAK]
+                EXPORT   USB0_IRQHandler                 [WEAK]
+                EXPORT   USB1_IRQHandler                 [WEAK]
+                EXPORT   SCT_IRQHandler                  [WEAK]
+                EXPORT   RIT_OR_WWDT_IRQHandler          [WEAK]
+                EXPORT   TIMER0_IRQHandler               [WEAK]
+                EXPORT   GINT1_IRQHandler                [WEAK]
+                EXPORT   PIN_INT4_IRQHandler                [WEAK]
+                EXPORT   TIMER3_IRQHandler               [WEAK]
+                EXPORT   MCPWM_IRQHandler                [WEAK]
+                EXPORT   ADC0_IRQHandler                 [WEAK]
+                EXPORT   I2C0_OR_I2C1_IRQHandler         [WEAK]
+                EXPORT   SGPIO_IRQHandler                [WEAK]
+                EXPORT   SPI_OR_DAC_IRQHandler           [WEAK]
+                EXPORT   ADC1_IRQHandler                 [WEAK]
+                EXPORT   SSP0_OR_SSP1_IRQHandler         [WEAK]
+                EXPORT   EVENTROUTER_IRQHandler          [WEAK]
+                EXPORT   USART0_IRQHandler               [WEAK]
+                EXPORT   UART1_IRQHandler                [WEAK]
+                EXPORT   USART2_OR_C_CAN1_IRQHandler     [WEAK]
+                EXPORT   USART3_IRQHandler               [WEAK]
+                EXPORT   I2S0_OR_I2S1_OR_QEI_IRQHandler  [WEAK]
+                EXPORT   C_CAN0_IRQHandler               [WEAK]
+
+
+RTC_IRQHandler
+M4CORE_IRQHandler
+DMA_IRQHandler
+FLASHEEPROMAT_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_OR_WWDT_IRQHandler
+TIMER0_IRQHandler
+GINT1_IRQHandler
+PIN_INT4_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_OR_I2C1_IRQHandler
+SGPIO_IRQHandler
+SPI_OR_DAC_IRQHandler
+ADC1_IRQHandler
+SSP0_OR_SSP1_IRQHandler
+EVENTROUTER_IRQHandler
+USART0_IRQHandler
+UART1_IRQHandler
+USART2_OR_C_CAN1_IRQHandler
+USART3_IRQHandler
+I2S0_OR_I2S1_OR_QEI_IRQHandler
+C_CAN0_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                AREA    |.text|,CODE, READONLY
+getPC           PROC
+                EXPORT  getPC
+
+                MOV     R0,LR
+                BX      LR
+
+                ENDP
+
+                END
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
new file mode 100644
index 0000000000..5dd22339f8
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
@@ -0,0 +1,502 @@
+//*****************************************************************************
+// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 140113
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013-2014
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
+#if defined (__USE_LPCOPEN)
+void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
+#endif
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
+#if defined (__USE_LPCOPEN)
+void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+#endif
+void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM4
+    &_vStackTop,                    // The initial stack pointer
+    ResetISR,                       // The reset handler
+    NMI_Handler,                    // The NMI handler
+    HardFault_Handler,              // The hard fault handler
+    MemManage_Handler,              // The MPU fault handler
+    BusFault_Handler,               // The bus fault handler
+    UsageFault_Handler,             // The usage fault handler
+    0,                              // Reserved
+    0,                              // Reserved
+    0,                              // Reserved
+    0,                              // Reserved
+    SVC_Handler,                    // SVCall handler
+    DebugMon_Handler,               // Debug monitor handler
+    0,                              // Reserved
+    PendSV_Handler,                 // The PendSV handler
+    SysTick_Handler,                // The SysTick handler
+
+    // Chip Level - LPC43 (M4)
+    DAC_IRQHandler,           // 16
+#if defined (__USE_LPCOPEN)
+    M0APP_IRQHandler,        // 17 CortexM4/M0 (LPC43XX ONLY)
+#else
+    M0CORE_IRQHandler,        // 17
+#endif
+    DMA_IRQHandler,           // 18
+    0,           // 19
+    FLASH_EEPROM_IRQHandler,   // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
+    ETH_IRQHandler,           // 21
+    SDIO_IRQHandler,          // 22
+    LCD_IRQHandler,           // 23
+    USB0_IRQHandler,          // 24
+    USB1_IRQHandler,          // 25
+    SCT_IRQHandler,           // 26
+    RIT_IRQHandler,           // 27
+    TIMER0_IRQHandler,        // 28
+    TIMER1_IRQHandler,        // 29
+    TIMER2_IRQHandler,        // 30
+    TIMER3_IRQHandler,        // 31
+    MCPWM_IRQHandler,         // 32
+    ADC0_IRQHandler,          // 33
+    I2C0_IRQHandler,          // 34
+    I2C1_IRQHandler,          // 35
+    SPI_IRQHandler,           // 36
+    ADC1_IRQHandler,          // 37
+    SSP0_IRQHandler,          // 38
+    SSP1_IRQHandler,          // 39
+    UART0_IRQHandler,         // 40
+    UART1_IRQHandler,         // 41
+    UART2_IRQHandler,         // 42
+    UART3_IRQHandler,         // 43
+    I2S0_IRQHandler,          // 44
+    I2S1_IRQHandler,          // 45
+    SPIFI_IRQHandler,         // 46
+    SGPIO_IRQHandler,         // 47
+    GPIO0_IRQHandler,         // 48
+    GPIO1_IRQHandler,         // 49
+    GPIO2_IRQHandler,         // 50
+    GPIO3_IRQHandler,         // 51
+    GPIO4_IRQHandler,         // 52
+    GPIO5_IRQHandler,         // 53
+    GPIO6_IRQHandler,         // 54
+    GPIO7_IRQHandler,         // 55
+    GINT0_IRQHandler,         // 56
+    GINT1_IRQHandler,         // 57
+    EVRT_IRQHandler,          // 58
+    CAN1_IRQHandler,          // 59
+    0,                        // 60
+#if defined (__USE_LPCOPEN)
+    ADCHS_IRQHandler,         // 61 ADCHS combined interrupt
+#else
+    VADC_IRQHandler,          // 61
+#endif
+    ATIMER_IRQHandler,        // 62
+    RTC_IRQHandler,           // 63
+    0,                        // 64
+    WDT_IRQHandler,           // 65
+    M0SUB_IRQHandler,         // 66
+    CAN0_IRQHandler,          // 67
+    QEI_IRQHandler,           // 68
+};
+
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+        __attribute__((section(".after_vectors"
+)))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//
+//*****************************************************************************
+void ResetISR(void) {
+
+// *************************************************************
+// The following conditional block of code manually resets as
+// much of the peripheral set of the LPC43 as possible. This is
+// done because the LPC43 does not provide a means of triggering
+// a full system reset under debugger control, which can cause
+// problems in certain circumstances when debugging.
+//
+// You can prevent this code block being included if you require
+// (for example when creating a final executable which you will
+// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
+//
+#ifndef DONT_RESET_ON_RESTART
+
+    // Disable interrupts
+    __asm volatile ("cpsid i");
+    // equivalent to CMSIS '__disable_irq()' function
+
+    unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
+    // LPC_RGU->RESET_CTRL0 @ 0x40053100
+    // LPC_RGU->RESET_CTRL1 @ 0x40053104
+    // Note that we do not use the CMSIS register access mechanism,
+    // as there is no guarantee that the project has been configured
+    // to use CMSIS.
+
+    // Write to LPC_RGU->RESET_CTRL0
+    *(RESET_CONTROL + 0) = 0x10DF1000;
+    // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
+    // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
+
+    // Write to LPC_RGU->RESET_CTRL1
+    *(RESET_CONTROL + 1) = 0x01DFF7FF;
+    // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
+    // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
+    // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
+    // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
+
+    // Clear all pending interrupts in the NVIC
+    volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
+    unsigned int irqpendloop;
+    for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
+        *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
+    }
+
+    // Reenable interrupts
+    __asm volatile ("cpsie i");
+    // equivalent to CMSIS '__enable_irq()' function
+
+#endif  // ifndef DONT_RESET_ON_RESTART
+// *************************************************************
+
+#if defined (__USE_LPCOPEN)
+    SystemInit();
+#endif
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_LPCOPEN)
+// LPCOpen init code deals with FP and VTOR initialisation
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    /*
+     * Code to enable the Cortex-M4 FPU only included
+     * if appropriate build options have been selected.
+     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+     */
+    // CPACR is located at address 0xE000ED88
+    asm("LDR.W R0, =0xE000ED88");
+    // Read CPACR
+    asm("LDR R1, [R0]");
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    asm(" ORR R1, R1, #(0xF << 20)");
+    // Write back the modified value to the CPACR
+    asm("STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+    // ******************************
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+
+    // Note that we do not use the CMSIS register access mechanism,
+    // as there is no guarantee that the project has been configured
+    // to use CMSIS.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
+        // CMSIS : SCB->VTOR = <address of vector table>
+        *pSCB_VTOR = (unsigned int) g_pfnVectors;
+    }
+#endif
+
+#if defined (__USE_CMSIS)
+    SystemInit();
+#endif
+
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void) {
+    while (1) {
+    }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void) {
+    while (1) {
+    }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void) {
+    while (1) {
+    }
+}
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
new file mode 100644
index 0000000000..5f6233ad0e
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
@@ -0,0 +1,463 @@
+//*****************************************************************************
+// LPC43xx (Cortex M0 SUB) Startup code for use with LPCXpresso IDE
+//
+// Version : 131115
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+  extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+void SystemInit(void);
+#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+     void ResetISR(void);
+#if defined (__USE_LPCOPEN)
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+#else
+WEAK void M0S_NMI_Handler(void);
+WEAK void M0S_HardFault_Handler (void);
+WEAK void M0S_SVC_Handler(void);
+WEAK void M0S_PendSV_Handler(void);
+WEAK void M0S_SysTick_Handler(void);
+WEAK void M0S_IntDefaultHandler(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+#if defined (__USE_LPCOPEN)
+void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_INPUT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_MATCH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_SHIFT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_POS_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S0_I2S1_QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI_ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void M0S_DAC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_M4CORE_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_DMA_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_INPUT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_MATCH_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_SHIFT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SGPIO_POS_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USB0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USB1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SCT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_RITIMER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_GINT1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_TIMER1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_TIMER2_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_PIN_INT5_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_ADC0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_MCPWM_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_I2C0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_I2C1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SPI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_ADC1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SSP0_OR_SSP1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_EVENTROUTER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USART0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_UART1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USART2_OR_C_CAN1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_USART3_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_C_CAN0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_SPIFI_OR_VADC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+void M0S_M0APP_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
+#endif
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+
+#if defined (__USE_LPCOPEN)
+    // Core Level - CM0
+    &_vStackTop,                        // The initial stack pointer
+    ResetISR,                           // 1 The reset handler
+    NMI_Handler,                    // The NMI handler
+    HardFault_Handler,              // The hard fault handler
+    0,                                  // 4 Reserved
+    0,                                  // 5 Reserved
+    0,                                  // 6 Reserved
+    0,                                  // 7 Reserved
+    0,                                  // 8 Reserved
+    0,                                  // 9 Reserved
+    0,                                  // 10 Reserved
+    SVC_Handler,                    // SVCall handler
+    0,                              // Reserved
+    0,                              // Reserved
+    PendSV_Handler,                 // The PendSV handler
+    SysTick_Handler,                // The SysTick handler
+
+    // Chip Level - 43xx M0SUB core
+    DAC_IRQHandler,                 // 16
+    M4_IRQHandler,             // 17 Interrupt from M4 Core
+    DMA_IRQHandler,                 // 18 General Purpose DMA
+    0,                              // 19 Reserved
+    SGPIO_INPUT_IRQHandler,         // 20
+    SGPIO_MATCH_IRQHandler,         // 21
+    SGPIO_SHIFT_IRQHandler,         // 22
+    SGPIO_POS_IRQHandler,           // 23
+    USB0_IRQHandler,                // 24 USB0
+    USB1_IRQHandler,                // 25 USB1
+    SCT_IRQHandler ,                // 26 State Configurable Timer
+    RIT_IRQHandler,                 // 27 Repetitive Interrupt Timer
+    GINT1_IRQHandler,               // 28 GINT1
+    TIMER1_IRQHandler,              // 29 Timer1
+    TIMER2_IRQHandler,              // 30 Timer2
+    GPIO5_IRQHandler,               // 31
+    MCPWM_IRQHandler,               // 32 Motor Control PWM
+    ADC0_IRQHandler,                // 33 ADC0
+    I2C0_IRQHandler,                // 34
+    I2C1_IRQHandler,                // 35
+    SPI_IRQHandler,                 // 36
+    ADC1_IRQHandler,                // 37
+    SSP0_SSP1_IRQHandler,           // 38
+    EVRT_IRQHandler,                // 39 Event Router
+    UART0_IRQHandler,               // 41 USART0
+    UART1_IRQHandler,               // 41 UART1
+    UART2_CAN1_IRQHandler,          // 42 USART2 or C CAN1
+    UART3_IRQHandler,               // 43 USART3
+    I2S0_I2S1_QEI_IRQHandler,       // 35 I2C0 or I2C1 or I2S1 or QEI
+    CAN0_IRQHandler,                // 45 C CAN0
+    SPIFI_ADCHS_IRQHandler,         // 46
+    M0APP_IRQHandler,               // 47 Interrupt from M0APP
+  };
+#else
+    // Core Level - CM0
+    &_vStackTop,                        // The initial stack pointer
+    ResetISR,                           // 1 The reset handler
+    M0S_NMI_Handler,                    // 2 The NMI handler
+    M0S_HardFault_Handler,              // 3 The hard fault handler
+    0,                                  // 4 Reserved
+    0,                                  // 5 Reserved
+    0,                                  // 6 Reserved
+    0,                                  // 7 Reserved
+    0,                                  // 8 Reserved
+    0,                                  // 9 Reserved
+    0,                                  // 10 Reserved
+    M0S_SVC_Handler,                    // 11 SVCall handler
+    M0S_DebugMon_Handler,               // 12 Debug monitor handler
+    0,                                  // 13 Reserved
+    M0S_PendSV_Handler,                 // 14 The PendSV handler
+    M0S_SysTick_Handler,                // 15 The SysTick handler
+
+    // Chip Level - LPC43 (CM0 SUB)
+    M0S_DAC_IRQHandler,                 // 16
+    M0S_M4CORE_IRQHandler,              // 17 Interrupt from M4 Core
+    M0S_DMA_IRQHandler,                 // 18 General Purpose DMA
+    0,                                  // 19 Reserved
+    M0S_SGPIO_INPUT_IRQHandler,         // 20
+    M0S_SGPIO_MATCH_IRQHandler,         // 21
+    M0S_SGPIO_SHIFT_IRQHandler,         // 22
+    M0S_SGPIO_POS_IRQHandler,           // 23
+    M0S_USB0_IRQHandler,                // 24 USB0
+    M0S_USB1_IRQHandler,                // 25 USB1
+    M0S_SCT_IRQHandler ,                // 26 State Configurable Timer
+    M0S_RITIMER_IRQHandler,             // 27 Repetitive Interrupt Timer
+    M0S_GINT1_IRQHandler,               // 28 GINT1
+    M0S_TIMER1_IRQHandler,              // 29 Timer1
+    M0S_TIMER2_IRQHandler,              // 30 Timer2
+    M0S_PIN_INT5_IRQHandler,            // 31
+    M0S_MCPWM_IRQHandler,               // 32 Motor Control PWM
+    M0S_ADC0_IRQHandler,                // 33 ADC0
+    M0S_I2C0_IRQHandler,                // 34
+    M0S_I2C1_IRQHandler,                // 35
+    M0S_SPI_IRQHandler,                 // 36
+    M0S_ADC1_IRQHandler,                // 37
+    M0S_SSP0_OR_SSP1_IRQHandler,        // 38
+    M0S_EVENTROUTER_IRQHandler,         // 39 Event Router
+    M0S_USART0_IRQHandler,              // 41 USART0
+    M0S_UART1_IRQHandler,               // 41 UART1
+    M0S_USART2_OR_C_CAN1_IRQHandler,    // 42 USART2 or C CAN1
+    M0S_USART3_IRQHandler,              // 43 USART3
+    M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler,
+                                        // 35 I2C0 or I2C1 or I2S1 or QEI
+    M0S_C_CAN0_IRQHandler,              // 45 C CAN0
+    M0S_SPIFI_OR_VADC_IRQHandler,       // 46
+    M0S_M0APP_IRQHandler,               // 47 Interrupt from M0APP
+  };
+#endif
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+  unsigned int *pulDest = (unsigned int*) start;
+  unsigned int *pulSrc = (unsigned int*) romstart;
+  unsigned int loop;
+  for (loop = 0; loop < len; loop = loop + 4)
+    *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+  unsigned int *pulDest = (unsigned int*) start;
+  unsigned int loop;
+  for (loop = 0; loop < len; loop = loop + 4)
+    *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//
+//*****************************************************************************
+void
+ResetISR(void) {
+
+  // ******************************
+  // Modify CREG->M0SUBMEMMAP so that M0 looks in correct place
+  // for its vector table when an exception is triggered.
+  // Note that we do not use the CMSIS register access mechanism,
+  // as there is no guarantee that the project has been configured
+  // to use CMSIS.
+  unsigned int *pCREG_M0SUBMEMMAP = (unsigned int *) 0x40043308;
+  // CMSIS : CREG->M0SUBMEMMAP = <address of vector table>
+  *pCREG_M0SUBMEMMAP = (unsigned int)g_pfnVectors;
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+  unsigned int LoadAddr, ExeAddr, SectionLen;
+  unsigned int *SectionTableAddr;
+
+  // Load base address of Global Section Table
+  SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+  while (SectionTableAddr < &__data_section_table_end) {
+    LoadAddr = *SectionTableAddr++;
+    ExeAddr = *SectionTableAddr++;
+    SectionLen = *SectionTableAddr++;
+    data_init(LoadAddr, ExeAddr, SectionLen);
+  }
+  // At this point, SectionTableAddr = &__bss_section_table;
+  // Zero fill the bss segment
+  while (SectionTableAddr < &__bss_section_table_end) {
+    ExeAddr = *SectionTableAddr++;
+    SectionLen = *SectionTableAddr++;
+    bss_init(ExeAddr, SectionLen);
+  }
+
+// **********************************************************
+// No need to call SystemInit() here, as master CM4 cpu will
+// have done the main system set up before enabling CM0.
+// **********************************************************
+
+#if defined (__cplusplus)
+  //
+  // Call C++ library initialisation
+  //
+  __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+  // Call the Redlib library, which in turn calls main()
+  __main() ;
+#else
+  main();
+#endif
+
+  //
+  // main() shouldn't return, but if it does, we'll just enter an infinite loop
+  //
+  while (1) {
+    ;
+  }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void NMI_Handler(void)
+#else
+void M0S_NMI_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void HardFault_Handler(void)
+#else
+void M0S_HardFault_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void SVC_Handler(void)
+#else
+void M0S_SVC_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void PendSV_Handler(void)
+#else
+void M0S_PendSV_Handler(void)
+#endif
+{   while(1) { }
+}
+
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void SysTick_Handler(void)
+#else
+void M0S_SysTick_Handler(void)
+#endif
+{   while(1) { }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+#if defined (__USE_LPCOPEN)
+void IntDefaultHandler(void)
+#else
+void M0S_IntDefaultHandler(void)
+#endif
+{   while(1) { }
+}
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
new file mode 100644
index 0000000000..211a67d700
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
@@ -0,0 +1,431 @@
+;/*****************************************************************************
+; * @file:    startup_LPC18xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; *           for the NXP LPC18xx Device Series
+; * @version: V1.00
+; * @date:    24. May. 2011
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+Sign_Value		EQU		0x5A5A5A5A
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     Sign_Value
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD		DAC_IRQHandler	 			; 16 D/A Converter
+	DCD		0					; 17 Event Router
+        DCD		DMA_IRQHandler				; 18 General Purpose DMA
+        DCD		0				        ; 19 Reserved
+        DCD		0				        ; 20 Reserved
+        DCD		ETH_IRQHandler				; 21 Ethernet
+        DCD		SDIO_IRQHandler				; 22 SD/MMC
+        DCD		LCD_IRQHandler				; 23 LCD
+        DCD		USB0_IRQHandler				; 24 USB0
+        DCD		USB1_IRQHandler				; 25 USB1
+        DCD		SCT_IRQHandler				; 26 State Configurable Timer
+        DCD		RIT_IRQHandler				; 27 Repetitive Interrupt Timer
+        DCD		TIMER0_IRQHandler			; 28 Timer0
+        DCD		TIMER1_IRQHandler			; 29 Timer1
+        DCD		TIMER2_IRQHandler			; 30 Timer2
+        DCD		TIMER3_IRQHandler			; 31 Timer3
+        DCD		MCPWM_IRQHandler			; 32 Motor Control PWM
+        DCD		ADC0_IRQHandler				; 33 A/D Converter 0
+        DCD		I2C0_IRQHandler				; 34 I2C0
+        DCD		I2C1_IRQHandler				; 35 I2C1
+        DCD		0					; 36 Reserved
+        DCD		ADC1_IRQHandler				; 37 A/D Converter 1
+        DCD		SSP0_IRQHandler				; 38 SSP0
+        DCD		SSP1_IRQHandler				; 39 SSP1
+        DCD		UART0_IRQHandler			; 40 UART0
+        DCD		UART1_IRQHandler			; 41 UART1
+        DCD		UART2_IRQHandler			; 42 UART2
+        DCD		UART3_IRQHandler			; 43 UART3
+	DCD		I2S0_IRQHandler				; 44 I2S0
+	DCD		I2S1_IRQHandler				; 45 I2S1
+	DCD		SPIFI_IRQHandler			; 46 SPI Flash Interface
+	DCD		SGPIO_IRQHandler			; 47 SGPIO
+	DCD		GPIO0_IRQHandler			; 48 GPIO0
+	DCD		GPIO1_IRQHandler			; 49 GPIO1
+	DCD		GPIO2_IRQHandler			; 50 GPIO2
+	DCD		GPIO3_IRQHandler			; 51 GPIO3
+	DCD		GPIO4_IRQHandler			; 52 GPIO4
+	DCD		GPIO5_IRQHandler			; 53 GPIO5
+	DCD		GPIO6_IRQHandler			; 54 GPIO6
+	DCD		GPIO7_IRQHandler			; 55 GPIO7
+	DCD		GINT0_IRQHandler			; 56 GINT0
+	DCD		GINT1_IRQHandler			; 57 GINT1
+	DCD		EVRT_IRQHandler				; 58 Event Router
+	DCD		CAN1_IRQHandler				; 59 C_CAN1
+	DCD		0							; 60 Reserved
+	DCD		0       				; 61 VADC
+	DCD		ATIMER_IRQHandler			; 62 ATIMER
+	DCD		RTC_IRQHandler				; 63 RTC
+	DCD		0							; 64 Reserved
+	DCD		WDT_IRQHandler				; 65 WDT
+	DCD		0       				; 66 M0s
+	DCD		CAN0_IRQHandler				; 67 C_CAN0
+	DCD 	QEI_IRQHandler				; 68 QEI
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+
+        PUBWEAK EVRT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EVRT_IRQHandler
+        B EVRT_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ETH_IRQHandler
+        B ETH_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+        B SDIO_IRQHandler
+
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+
+        PUBWEAK USB0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB0_IRQHandler
+        B USB0_IRQHandler
+
+        PUBWEAK USB1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB1_IRQHandler
+        B USB1_IRQHandler
+
+        PUBWEAK SCT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SCT_IRQHandler
+        B SCT_IRQHandler
+
+        PUBWEAK RIT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RIT_IRQHandler
+        B RIT_IRQHandler
+
+        PUBWEAK TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER0_IRQHandler
+        B TIMER0_IRQHandler
+
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+
+        PUBWEAK TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER2_IRQHandler
+        B TIMER2_IRQHandler
+
+        PUBWEAK TIMER3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER3_IRQHandler
+        B TIMER3_IRQHandler
+
+        PUBWEAK MCPWM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+MCPWM_IRQHandler
+        B MCPWM_IRQHandler
+
+        PUBWEAK ADC0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC0_IRQHandler
+        B ADC0_IRQHandler
+
+        PUBWEAK I2C0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C0_IRQHandler
+        B I2C0_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK SSP0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP0_IRQHandler
+        B SSP0_IRQHandler
+
+        PUBWEAK SSP1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP1_IRQHandler
+        B SSP1_IRQHandler
+
+        PUBWEAK UART0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+        B UART0_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK I2S0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2S0_IRQHandler
+        B I2S0_IRQHandler
+
+        PUBWEAK I2S1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2S1_IRQHandler
+        B I2S1_IRQHandler
+        
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK SPIFI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPIFI_IRQHandler
+        B SPIFI_IRQHandler
+
+        PUBWEAK SGPIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SGPIO_IRQHandler
+        B SGPIO_IRQHandler
+
+        PUBWEAK GPIO0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO0_IRQHandler
+        B GPIO0_IRQHandler
+
+        PUBWEAK GPIO1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO1_IRQHandler
+        B GPIO1_IRQHandler
+        
+        PUBWEAK GPIO2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO2_IRQHandler
+        B GPIO2_IRQHandler
+        
+        PUBWEAK GPIO3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO3_IRQHandler
+        B GPIO3_IRQHandler
+        
+        PUBWEAK GPIO4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO4_IRQHandler
+        B GPIO4_IRQHandler
+        
+        PUBWEAK GPIO5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO5_IRQHandler
+        B GPIO5_IRQHandler
+        
+        PUBWEAK GPIO6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO6_IRQHandler
+        B GPIO6_IRQHandler
+        
+        PUBWEAK GPIO7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GPIO7_IRQHandler
+        B GPIO7_IRQHandler
+        
+        PUBWEAK GINT0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GINT0_IRQHandler
+        B GINT0_IRQHandler
+        
+        PUBWEAK GINT1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+GINT1_IRQHandler
+        B GINT1_IRQHandler
+        
+        PUBWEAK CAN1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_IRQHandler
+        B CAN1_IRQHandler
+        
+        PUBWEAK ATIMER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ATIMER_IRQHandler
+        B ATIMER_IRQHandler
+        
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+        
+        PUBWEAK CAN0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN0_IRQHandler
+        B CAN0_IRQHandler
+        
+        PUBWEAK QEI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+QEI_IRQHandler
+        B QEI_IRQHandler
+        
+        PUBWEAK getPC
+        SECTION .text:CODE:REORDER(2)
+getPC
+      MOV   R0,LR
+      BX    LR        
+        END
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
new file mode 100644
index 0000000000..1954b91b7b
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
@@ -0,0 +1,242 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start 
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+				
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+		DCD		DAC_IRQHandler
+		DCD		M4_IRQHandler
+		DCD		DMA_IRQHandler
+		DCD		0
+		DCD		SGPIO_INPUT_IRQHandler
+		DCD		SGPIO_MATCH_IRQHandler
+		DCD		SGPIO_SHIFT_IRQHandler
+		DCD		SGPIO_POS_IRQHandler
+		DCD		USB0_IRQHandler
+		DCD		USB1_IRQHandler
+		DCD		SCT_IRQHandler
+		DCD		RIT_IRQHandler
+		DCD		GINT1_IRQHandler
+		DCD		TIMER1_IRQHandler
+		DCD		TIMER2_IRQHandler
+		DCD		GPIO5_IRQHandler
+		DCD		MCPWM_IRQHandler
+		DCD		ADC0_IRQHandler
+		DCD		I2C0_IRQHandler
+		DCD		I2C1_IRQHandler
+		DCD		SPI_IRQHandler
+		DCD		ADC1_IRQHandler
+		DCD		SSP0_SSP1_IRQHandler
+		DCD		EVRT_IRQHandler
+		DCD		UART0_IRQHandler
+		DCD		UART1_IRQHandler
+		DCD		UART2_CAN1_IRQHandler
+		DCD		UART3_IRQHandler
+		DCD		I2S0_I2S1_QEI_IRQHandler
+		DCD		CAN0_IRQHandler
+		DCD		SPIFI_ADCHS_IRQHandler
+		DCD		M0APP_IRQHandler
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+		THUMB
+
+		PUBWEAK Reset_Handler
+		SECTION .text:CODE:REORDER(2)
+Reset_Handler
+		LDR     R0, =SystemInit
+		BLX     R0
+		LDR     R0, =__iar_program_start
+		BX      R0
+  
+		PUBWEAK NMI_Handler
+		PUBWEAK HardFault_Handler
+		PUBWEAK MemManage_Handler
+		PUBWEAK BusFault_Handler
+		PUBWEAK UsageFault_Handler
+		PUBWEAK SVC_Handler
+		PUBWEAK DebugMon_Handler
+		PUBWEAK PendSV_Handler
+		PUBWEAK SysTick_Handler
+
+		PUBWEAK DAC_IRQHandler
+		PUBWEAK M4_IRQHandler
+		PUBWEAK DMA_IRQHandler
+		PUBWEAK UnHandled_Vector
+		PUBWEAK SGPIO_INPUT_IRQHandler
+		PUBWEAK SGPIO_MATCH_IRQHandler
+		PUBWEAK SGPIO_SHIFT_IRQHandler
+		PUBWEAK SGPIO_POS_IRQHandler
+		PUBWEAK USB0_IRQHandler
+		PUBWEAK USB1_IRQHandler
+		PUBWEAK SCT_IRQHandler
+		PUBWEAK RIT_IRQHandler
+		PUBWEAK GINT1_IRQHandler
+		PUBWEAK TIMER1_IRQHandler
+		PUBWEAK TIMER2_IRQHandler
+		PUBWEAK GPIO5_IRQHandler
+		PUBWEAK MCPWM_IRQHandler
+		PUBWEAK ADC0_IRQHandler
+		PUBWEAK I2C0_IRQHandler
+		PUBWEAK I2C1_IRQHandler
+		PUBWEAK SPI_IRQHandler
+		PUBWEAK ADC1_IRQHandler
+		PUBWEAK SSP0_SSP1_IRQHandler
+		PUBWEAK EVRT_IRQHandler
+		PUBWEAK UART0_IRQHandler
+		PUBWEAK UART1_IRQHandler
+		PUBWEAK UART2_CAN1_IRQHandler
+		PUBWEAK UART3_IRQHandler
+		PUBWEAK I2S0_I2S1_QEI_IRQHandler
+		PUBWEAK CAN0_IRQHandler
+		PUBWEAK SPIFI_ADCHS_IRQHandler
+		PUBWEAK M0APP_IRQHandler
+
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B .
+SVC_Handler
+        B .
+DebugMon_Handler
+        B .
+PendSV_Handler
+        B .
+SysTick_Handler
+        B .
+HardFault_Handler
+        B .
+MemManage_Handler
+        B .
+BusFault_Handler
+        B .
+UsageFault_Handler
+DAC_IRQHandler
+M4_IRQHandler
+DMA_IRQHandler
+UnHandled_Vector
+SGPIO_INPUT_IRQHandler
+SGPIO_MATCH_IRQHandler
+SGPIO_SHIFT_IRQHandler
+SGPIO_POS_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+GINT1_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+GPIO5_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_SSP1_IRQHandler
+EVRT_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_CAN1_IRQHandler
+UART3_IRQHandler
+I2S0_I2S1_QEI_IRQHandler
+CAN0_IRQHandler
+SPIFI_ADCHS_IRQHandler
+M0APP_IRQHandler
+Default_IRQHandler
+        B .
+
+/* CRP Section - not needed for flashless devices */
+
+;;;        SECTION .crp:CODE:ROOT(2)
+;;;        DATA
+/* Code Read Protection
+NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+                   - Copy RAM to flash command can not write to Sector 0.
+                   - Erase command can erase Sector 0 only when all sectors
+                     are selected for erase.
+                   - Compare command is disabled.
+                   - Read Memory command is disabled.
+CRP2    0x87654321 - Read Memory is disabled.
+                   - Write to RAM is disabled.
+                   - "Go" command is disabled.
+                   - Copy RAM to flash is disabled.
+                   - Compare is disabled.
+CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+                     by pulling PIO0_1 LOW is disabled if a valid user code is
+                     present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+;;;	    DCD	0xFFFFFFFF
+;;;
+
+        END
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
new file mode 100644
index 0000000000..3bd76f5de6
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
@@ -0,0 +1,892 @@
+/*----------------------------------------------------------------------------
+ * Name:    system_LPC43xx.c
+ * Purpose: LCP43xx clock initialisation
+ * Version: V2.51
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2005-2012 Keil Software. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "LPC43xx.h"
+
+/*----------------------------------------------------------------------------
+  This file configures the clocks as follows:
+ -----------------------------------------------------------------------------
+ Clock Unit  |  Output clock  |  Source clock  |          Note
+ -----------------------------------------------------------------------------
+   PLL0USB   |    480 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    PLL1     |    180 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    CPU      |    180 MHz     |      PLL1      | CPU Clock ==  BASE_M4_CLK
+ -----------------------------------------------------------------------------
+   IDIV A    |     60 MHz     |      PLL1      | To the USB1 peripheral
+ -----------------------------------------------------------------------------
+   IDIV B    |     25 MHz     |   ENET_TX_CLK  | ENET_TX_CLK @ 50MHz
+ -----------------------------------------------------------------------------
+   IDIV C    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV D    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV E    |    5.3 MHz     |      PLL1      | To the LCD controller
+ -----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock source selection definitions (do not change)
+ *----------------------------------------------------------------------------*/
+#define CLK_SRC_32KHZ       0x00
+#define CLK_SRC_IRC         0x01
+#define CLK_SRC_ENET_RX     0x02
+#define CLK_SRC_ENET_TX     0x03
+#define CLK_SRC_GP_CLKIN    0x04
+#define CLK_SRC_XTAL        0x06
+#define CLK_SRC_PLL0U       0x07
+#define CLK_SRC_PLL0A       0x08
+#define CLK_SRC_PLL1        0x09
+#define CLK_SRC_IDIVA       0x0C
+#define CLK_SRC_IDIVB       0x0D
+#define CLK_SRC_IDIVC       0x0E
+#define CLK_SRC_IDIVD       0x0F
+#define CLK_SRC_IDIVE       0x10
+
+
+/*----------------------------------------------------------------------------
+  Define external input frequency values
+ *----------------------------------------------------------------------------*/
+#define CLK_32KHZ            32768UL    /* 32 kHz oscillator frequency        */
+#define CLK_IRC           12000000UL    /* Internal oscillator frequency      */
+#define CLK_ENET_RX       50000000UL    /* Ethernet Rx frequency              */
+#define CLK_ENET_TX       50000000UL    /* Ethernet Tx frequency              */
+#define CLK_GP_CLKIN      12000000UL    /* General purpose clock input freq.  */
+#define CLK_XTAL          12000000UL    /* Crystal oscilator frequency        */
+
+
+/*----------------------------------------------------------------------------
+  Define clock sources
+ *----------------------------------------------------------------------------*/
+#define PLL1_CLK_SEL      CLK_SRC_XTAL    /* PLL1 input clock: XTAL           */
+#define PLL0USB_CLK_SEL   CLK_SRC_XTAL    /* PLL0USB input clock: XTAL        */
+#define IDIVA_CLK_SEL     CLK_SRC_PLL1    /* IDIVA input clock: PLL1          */
+#define IDIVB_CLK_SEL     CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX       */
+#define IDIVC_CLK_SEL     CLK_SRC_IRC     /* IDIVC input clock: IRC           */
+#define IDIVD_CLK_SEL     CLK_SRC_IRC     /* IDIVD input clock: IRC           */
+#define IDIVE_CLK_SEL     CLK_SRC_PLL1    /* IDIVD input clock: PLL1          */
+
+
+/*----------------------------------------------------------------------------
+  Configure integer divider values
+ *----------------------------------------------------------------------------*/
+#define IDIVA_IDIV        2             /* Divide input clock by 3            */
+#define IDIVB_IDIV        1             /* Divide input clock by 2            */
+#define IDIVC_IDIV        0             /* Divide input clock by 1            */
+#define IDIVD_IDIV        0             /* Divide input clock by 1            */
+#define IDIVE_IDIV       33             /* Divide input clock by 34           */
+
+
+/*----------------------------------------------------------------------------
+  Define CPU clock input
+ *----------------------------------------------------------------------------*/
+#define CPU_CLK_SEL       CLK_SRC_PLL1  /* Default CPU clock source is PLL1   */
+
+
+/*----------------------------------------------------------------------------
+  Configure external memory controller options
+ *----------------------------------------------------------------------------*/
+#define USE_EXT_STAT_MEM_CS0 1          /* Use ext. static  memory with CS0   */
+#define USE_EXT_DYN_MEM_CS0  1          /* Use ext. dynamic memory with CS0   */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL1                                                                 
+ *----------------------------------------------------------------------------
+ * Integer mode:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 1 (Feedback divider runs from PLL output)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Non-integer:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 0 (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M / (2 * P)
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Direct mode:
+ *    - PLL1_DIRECT = 1         (Post divider disabled)
+ *    - PLL1_FBSEL  = dont care (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT
+ *
+ *----------------------------------------------------------------------------
+ * PLL1 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
+ * |   FCCO    |  156MHz   |  320MHz   |                                      |
+ * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkin |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
+ * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
+ * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |
+ * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
+ * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   |
+ * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
+ * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
+ * | 204MHz | 204MHz |  1  |  17 |  x  |   1    |   0   |    0   |
+ *----------------------------------------------------------------------------
+ * Relations beetwen PLL dividers and definitions:
+ * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
+ *----------------------------------------------------------------------------*/
+
+/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x              */
+#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
+#define PLL1_MSEL  14           /* Range [0 - 255]: Feedback-divider ratio M  */
+#define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
+
+#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
+#define PLL1_DIRECT 1           /* 0: Use PSEL, 1: Don't use PSEL             */
+#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
+                                /* 1: FCLKOUT is used as PLL feedback         */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL0USB
+ *----------------------------------------------------------------------------
+ *
+ *   Normal operating mode without post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * (M / P)
+ *                        FCCO = FOUT * 2 * P
+ *
+ *   Normal operating mode without post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 1 
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M / N
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * M / (P * N)
+ *                        FCCO = FOUT * 2 * P
+ *----------------------------------------------------------------------------
+ * PLL0 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |   14kHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |   14kHz   |  150MHz   |                                      |
+ * |   FCCO    |  275MHz   |  550MHz   |                                      |
+ * |  FCLKOUT  |  4.3MHz   |  550MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkin |  Fcco  |  N  |  M  |  P  | DIRECTI | DIRECTO | BYPASS |
+ * | 120MHz | 480MHz |  x  |  20 |  2  |    1    |    0    |    0   |
+ * | 480MHz | 480MHz |  1  |  20 |  1  |    1    |    1    |    0   |
+ *----------------------------------------------------------------------------*/
+
+/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1           */
+#define PLL0USB_N       1       /* Range [1 -  256]: Pre-divider              */
+#define PLL0USB_M      20       /* Range [1 - 2^15]: Feedback-divider         */
+#define PLL0USB_P       1       /* Range [1 -   32]: Post-divider             */
+
+#define PLL0USB_DIRECTI 1       /* 0: Use N_DIV, 1: Don't use N_DIV           */
+#define PLL0USB_DIRECTO 1       /* 0: Use P_DIV, 1: Don't use P_DIV           */
+#define PLL0USB_BYPASS  0       /* 0: Use PLL, 1: PLL is bypassed             */
+
+
+/*----------------------------------------------------------------------------
+  End of configuration
+ *----------------------------------------------------------------------------*/
+
+/* PLL0 Setting Check */
+#if (PLL0USB_BYPASS == 0)
+ #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL0USB_CLKIN CLK_XTAL
+ #else
+  #define PLL0USB_CLKIN CLK_IRC
+ #endif
+
+ #if   ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #else                                                    /* Mode 1d          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #endif
+
+ #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
+  #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
+ #endif
+ #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
+  #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
+ #endif
+#endif
+
+/* PLL1 Setting Check */
+#if (PLL1_BYPASS == 0)
+ #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL1_CLKIN CLK_XTAL
+ #else
+  #define PLL1_CLKIN CLK_IRC
+ #endif
+
+ #if   (PLL1_DIRECT == 1)               /* Direct Mode                        */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #elif (PLL1_FBSEL  == 1)               /* Integer Mode                       */
+  #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #else                                  /* Noninteger Mode                    */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
+ #endif
+ #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
+  #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
+ #endif
+ #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
+  #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
+ #endif
+#endif
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CLK_IRC;    /* System Clock Frequency (Core Clock) */
+
+
+/******************************************************************************
+ * SetClock
+ ******************************************************************************/
+void SetClock (void) {
+  uint32_t x, i;
+  uint32_t selp, seli;
+
+  /* Set flash wait states to maximum                                         */
+  LPC_EMC->STATICWAITRD0  = 0x1F;
+
+  /* Switch BASE_M4_CLOCK to IRC                                              */
+  LPC_CGU->BASE_M4_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CLK_SRC_IRC << 24) ;  /* Set clock source           */
+
+  /* Configure input to crystal oscilator                                     */
+  LPC_CGU->XTAL_OSC_CTRL = (0 << 0) |   /* Enable oscillator-pad              */
+                           (0 << 1) |   /* Operation with crystal connected   */
+                           (0 << 2) ;   /* Low-frequency mode                 */
+
+#if (USE_SPIFI)
+/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
+  LPC_CGU->IDIVA_CTRL     = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IRC    << 24) ;  /* Clock source         */
+
+  LPC_CGU->BASE_SPIFI_CLK = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IDIVA  << 24) ;  /* Clock source         */
+#endif
+
+/*----------------------------------------------------------------------------
+  PLL1 Setup
+ *----------------------------------------------------------------------------*/
+  /* Power down PLL                                                           */
+  LPC_CGU->PLL1_CTRL |= 1;
+
+#if ((PLL1_FOUT >= 180000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
+  /* To run at full speed, CPU must first run at an intermediate speed        */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (0            << 1) | /* CCO out sent to post-dividers */
+                       (0            << 6) | /* PLL output used as feedback   */
+                       (1            << 7) | /* Direct on/off                 */
+                       (0            << 8) | /* PSEL                          */
+                       (0            << 11)| /* Autoblock Disabled            */
+                       (2            << 12)| /* NSEL                          */
+                       (39           << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* CPU base clock @ 160 MHz before final clock set                          */
+  LPC_CGU->BASE_M4_CLK     = (0x01 << 11) |  /* Autoblock En                  */
+                             (0x09 << 24) ;  /* Clock source: PLL1            */
+
+  for (i = 1000; i; i--);                    /* Wait about 4000 cycles        */
+#endif
+  /* Configure PLL1                                                           */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (PLL1_DIRECT  << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (1            << 11)| /* Autoblock En                  */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* Set CPU base clock source                                                */
+  LPC_CGU->BASE_M4_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CPU_CLK_SEL << 24) ;  /* Set clock source           */
+
+
+/*----------------------------------------------------------------------------
+  PLL0USB Setup
+ *----------------------------------------------------------------------------*/
+  
+  /* Power down PLL0USB                                                       */
+  LPC_CGU->PLL0USB_CTRL  |= 1;
+
+  /* M divider                                                                */
+  x = 0x00004000;
+  switch (PLL0USB_M) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00018003;
+      break;
+    case 2:  x = 0x00010003;
+      break;
+    default:
+      for (i = PLL0USB_M; i <= 0x8000; i++) {
+        x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+      }
+  }
+  
+  if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
+  else        selp = 31;
+  
+  if      (PLL0USB_M > 16384) seli = 1;
+  else if (PLL0USB_M >  8192) seli = 2;
+  else if (PLL0USB_M >  2048) seli = 4;
+  else if (PLL0USB_M >=  501) seli = 8;
+  else if (PLL0USB_M >=   60) seli = 4 * (1024 / (PLL0USB_M + 9));
+  else                        seli = (PLL0USB_M & 0x3C) + 4;
+  LPC_CGU->PLL0USB_MDIV   =  (selp   << 17) |
+                             (seli   << 22) |
+                             (x      <<  0);
+
+  /* N divider                                                                */
+  x = 0x80;
+  switch (PLL0USB_N) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000302;
+      break;
+    case 2:  x = 0x00000202;
+      break;
+    default: 
+      for (i = PLL0USB_N; i <= 0x0100; i++) {
+        x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV = (x << 12);
+  
+  /* P divider                                                                */
+  x = 0x10;
+  switch (PLL0USB_P) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000062;
+      break;
+    case 2:  x = 0x00000042;
+      break;
+    default:
+      for (i = PLL0USB_P; i <= 0x200; i++) {
+        x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
+      }
+  } 
+  LPC_CGU->PLL0USB_NP_DIV |= x;
+  
+  LPC_CGU->PLL0USB_CTRL  = (PLL0USB_CLK_SEL   << 24) | /* Clock source sel    */                             
+                           (1                 << 11) | /* Autoblock En        */
+                           (1                 << 4 ) | /* PLL0USB clock en    */
+                           (PLL0USB_DIRECTO   << 3 ) | /* Direct output       */
+                           (PLL0USB_DIRECTI   << 2 ) | /* Direct input        */
+                           (PLL0USB_BYPASS    << 1 ) | /* PLL bypass          */
+                           (0                 << 0 ) ; /* PLL0USB Enabled     */
+  while (!(LPC_CGU->PLL0USB_STAT & 1));
+
+
+/*----------------------------------------------------------------------------
+  Integer divider Setup
+ *----------------------------------------------------------------------------*/
+  
+  /* Configure integer dividers                                               */
+  LPC_CGU->IDIVA_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVA_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVA_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVB_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVB_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVB_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVC_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVC_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVC_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVD_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVD_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVD_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVE_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVE_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVE_CLK_SEL  << 24) ;  /* Clock source             */
+}
+
+
+/*----------------------------------------------------------------------------
+  Approximate delay function (must be used after SystemCoreClockUpdate() call)
+ *----------------------------------------------------------------------------*/
+#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
+
+static void WaitUs (uint32_t us) {
+  uint32_t cyc = us * CPU_NANOSEC(1000)/4;
+  while(cyc--);
+}
+
+
+/*----------------------------------------------------------------------------
+  External Memory Controller Definitions
+ *----------------------------------------------------------------------------*/
+#define SDRAM_ADDR_BASE 0x28000000      /* SDRAM base address                 */
+/* Write Mode register macro                                                  */
+#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
+
+/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
+#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
+#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
+
+#define EMC_CLK_DLY_TIM_2  (0x7777)     /* 3.5 ns delay for the EMC clock out */
+#define EMC_CLK_DLY_TIM_0  (0x0000)     /* No delay for the EMC clock out     */
+
+typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
+
+const uint16_t emcdivby2_opc[] =  {
+  0x6803,        /*      LDR  R3,[R0,#0]      ; Load CREG6          */
+  0xF443,0x3380, /*      ORR  R3,R3,#0x10000  ; Set Divided by 2    */
+  0x6003,        /*      STR  R3,[R0,#0]      ; Store CREG6         */
+  0x600A,        /*      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg    */
+  0x684B,        /* loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT    */
+  0x07DB,        /*      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0 */
+  0xD0FC,        /*      BEQ  loop            ; Jump if 0           */
+  0x4770,        /*      BX   LR              ; Exit                */
+  0,
+};
+
+#define        emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
+#define        emcdivby2_ram 0x10000000
+
+/*----------------------------------------------------------------------------
+  Initialize external memory controller
+ *----------------------------------------------------------------------------*/
+
+void SystemInit_ExtMemCtl (void) {
+  uint32_t emcdivby2_buf[emcdivby2_szw];
+  uint32_t div, n;
+
+  /* Select and enable EMC branch clock */
+  LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
+  while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
+
+  /* Set EMC clock output delay */  
+  if (SystemCoreClock < 80000000UL) {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
+  }
+  else {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
+  }
+
+  /* Configure EMC port pins */
+  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
+  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
+  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
+  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
+  LPC_SCU->SFSP1_4  = EMC_PIN_SET | 3;  /* P1_4:  BLS0                        */
+  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
+  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
+  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
+  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
+  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
+  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
+  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
+  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
+  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
+  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */
+
+  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
+  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
+  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
+  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
+  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
+  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
+  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
+  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
+  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
+  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
+  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */
+
+  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
+  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
+  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
+  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
+  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
+  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
+  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
+  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
+
+  LPC_SCU->SFSP6_1  = EMC_PIN_SET | 1;  /* P6_1:  DYCS1                       */
+  LPC_SCU->SFSP6_2  = EMC_PIN_SET | 1;  /* P6_3:  CKEOUT1                     */
+  LPC_SCU->SFSP6_3  = EMC_PIN_SET | 3;  /* P6_3:  CS1                         */
+  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
+  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
+  LPC_SCU->SFSP6_6  = EMC_PIN_SET | 1;  /* P6_6:  BLS1                        */
+  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
+  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
+  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
+  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
+  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
+  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */
+
+  LPC_SCU->SFSPA_4  = EMC_PIN_SET | 3;  /* PA_4:  A23                         */
+
+  LPC_SCU->SFSPD_0  = EMC_PIN_SET | 2;  /* PD_0:  DQMOUT2                     */
+  LPC_SCU->SFSPD_1  = EMC_PIN_SET | 2;  /* PD_1:  CKEOUT2                     */
+  LPC_SCU->SFSPD_2  = EMC_PIN_SET | 2;  /* PD_2:  D16                         */
+  LPC_SCU->SFSPD_3  = EMC_PIN_SET | 2;  /* PD_3:  D17                         */
+  LPC_SCU->SFSPD_4  = EMC_PIN_SET | 2;  /* PD_4:  D18                         */
+  LPC_SCU->SFSPD_5  = EMC_PIN_SET | 2;  /* PD_5:  D19                         */
+  LPC_SCU->SFSPD_6  = EMC_PIN_SET | 2;  /* PD_6:  D20                         */
+  LPC_SCU->SFSPD_7  = EMC_PIN_SET | 2;  /* PD_7:  D21                         */ 
+  LPC_SCU->SFSPD_8  = EMC_PIN_SET | 2;  /* PD_8:  D22                         */
+  LPC_SCU->SFSPD_9  = EMC_PIN_SET | 2;  /* PD_9:  D23                         */
+  LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2;  /* PD_10: BLS3                        */
+  LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2;  /* PD_11: CS3                         */
+  LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2;  /* PD_12: CS2                         */
+  LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2;  /* PD_13: BLS2                        */
+  LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2;  /* PD_14: DYCS2                       */
+  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
+  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */
+
+  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
+  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
+  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
+  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
+  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */
+  LPC_SCU->SFSPE_5  = EMC_PIN_SET | 3;  /* PE_5:  D24                         */
+  LPC_SCU->SFSPE_6  = EMC_PIN_SET | 3;  /* PE_6:  D25                         */
+  LPC_SCU->SFSPE_7  = EMC_PIN_SET | 3;  /* PE_7:  D26                         */
+  LPC_SCU->SFSPE_8  = EMC_PIN_SET | 3;  /* PE_8:  D27                         */
+  LPC_SCU->SFSPE_9  = EMC_PIN_SET | 3;  /* PE_9:  D28                         */
+  LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3;  /* PE_10: D29                         */
+  LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3;  /* PE_11: D30                         */
+  LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3;  /* PE_12: D31                         */
+  LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3;  /* PE_13: DQMOUT3                     */
+  LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3;  /* PE_14: DYCS3                       */
+  LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3;  /* PE_15: CKEOUT3                     */
+
+  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
+  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */
+
+  div = 0;
+  if (SystemCoreClock > 120000000UL) {
+    /* Use EMC clock divider and EMC clock output delay */
+    div = 1;
+    /* Following code must be executed in RAM to ensure stable operation      */
+    /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
+    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
+    /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));                           */
+
+    /* This code configures EMC clock divider and is executed in RAM          */
+    for (n = 0; n < emcdivby2_szw; n++) {
+      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
+      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
+    }
+    __ISB();
+    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
+    for (n = 0; n < emcdivby2_szw; n++) {
+      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
+    }
+  }
+
+  /* Configure EMC clock-out pins                                             */
+  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
+  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
+  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
+  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
+  
+  /* Static memory configuration (chip select 0)                              */
+#if (USE_EXT_STAT_MEM_CS0)
+  LPC_EMC->STATICCONFIG0  = (1 <<  7) | /* Byte lane state: use WE signal     */
+                            (2 <<  0) ; /* Memory width 32-bit                */
+  LPC_EMC->STATICWAITOEN0 = (0 <<  0) ; /* Wait output enable: No delay       */
+
+  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
+  LPC_EMC->STATICWAITRD0  = EMC_NANOSEC(90, SystemCoreClock, div);
+  LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer                      */
+#endif
+  
+  /* Dynamic memory configuration (chip select 0)                             */
+#if (USE_EXT_DYN_MEM_CS0)
+
+  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
+  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
+                               (0 << 12) |  /* AM[12]   = 0                   */
+                               (2 <<  9) |  /* AM[11:9] = 2                   */
+                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
+
+  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
+  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
+
+  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
+  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
+  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);
+
+  WaitUs (100);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
+  WaitUs (1);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (1);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
+
+  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
+  WR_MODE(((3 << 4) | 2) << 12);
+
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
+  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
+#endif
+}
+
+
+/*----------------------------------------------------------------------------
+  Measure frequency using frequency monitor
+ *----------------------------------------------------------------------------*/
+uint32_t MeasureFreq (uint32_t clk_sel) {
+  uint32_t fcnt, rcnt, fout;
+
+  /* Set register values */
+  LPC_CGU->FREQ_MON &= ~(1 << 23);                /* Stop frequency counters  */
+  LPC_CGU->FREQ_MON  = (clk_sel << 24) | 511;     /* RCNT == 511              */
+  LPC_CGU->FREQ_MON |= (1 << 23);                 /* Start RCNT and FCNT      */
+  while (LPC_CGU->FREQ_MON & (1 << 23)) {
+    fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+    rcnt = (LPC_CGU->FREQ_MON     ) & 0x01FF;
+    if (fcnt == 0 && rcnt == 0) {
+      return (0);                                 /* No input clock present   */
+    }
+  }
+  fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
+
+  return (fout);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get PLL1 (divider and multiplier) parameters
+ *----------------------------------------------------------------------------*/
+__inline uint32_t GetPLL1Param (void) {
+  uint32_t ctrl;
+  uint32_t p;
+  uint32_t div, mul;
+
+  ctrl = LPC_CGU->PLL1_CTRL;
+  div = ((ctrl >> 12) & 0x03) + 1;
+  mul = ((ctrl >> 16) & 0xFF) + 1;
+  p = 1 << ((ctrl >>  8) & 0x03);
+
+  if (ctrl & (1 << 1)) {
+    /* Bypass = 1, PLL1 input clock sent to post-dividers */
+    if (ctrl & (1 << 7)) {
+      div *= (2*p);
+    }
+  }
+  else {
+    /* Direct and integer mode */
+    if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
+      /* Non-integer mode */
+      div *= (2*p);
+    }
+  }
+  return ((div << 8) | (mul)); 
+}
+
+
+/*----------------------------------------------------------------------------
+  Get input clock source for specified clock generation block
+ *----------------------------------------------------------------------------*/
+int32_t GetClkSel (uint32_t clk_src) {
+  uint32_t reg;
+  int32_t clk_sel = -1;
+
+  switch (clk_src) {
+    case CLK_SRC_IRC:
+    case CLK_SRC_ENET_RX:
+    case CLK_SRC_ENET_TX:
+    case CLK_SRC_GP_CLKIN:
+      return (clk_src);
+
+    case CLK_SRC_32KHZ:
+      return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
+    case CLK_SRC_XTAL:
+     return  (LPC_CGU->XTAL_OSC_CTRL & 1)       ? (-1) : (CLK_SRC_XTAL);
+    
+    case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL;    break;
+    case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL;  break;
+    case CLK_SRC_PLL1:  reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
+
+    case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL;      break;
+    case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL;      break;
+    case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL;      break;
+    case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL;      break;
+    case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL;      break;
+    
+    default:
+      return (clk_sel);
+  }
+  if (!(reg & 1)) {
+    clk_sel = (reg >> 24) & 0x1F;
+  }
+  return (clk_sel);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get clock frequency for specified clock source
+ *----------------------------------------------------------------------------*/
+uint32_t GetClockFreq (uint32_t clk_src) {
+  uint32_t tmp;
+  uint32_t mul        =  1;
+  uint32_t div        =  1;
+  uint32_t main_freq  =  0;
+  int32_t  clk_sel    = clk_src;
+
+  do {
+    switch (clk_sel) {      
+      case CLK_SRC_32KHZ:    main_freq = CLK_32KHZ;     break; 
+      case CLK_SRC_IRC:      main_freq = CLK_IRC;       break;
+      case CLK_SRC_ENET_RX:  main_freq = CLK_ENET_RX;   break; 
+      case CLK_SRC_ENET_TX:  main_freq = CLK_ENET_TX;   break; 
+      case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN;  break; 
+      case CLK_SRC_XTAL:     main_freq = CLK_XTAL;      break;
+  
+      case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0x3) + 1; break;
+  
+      case CLK_SRC_PLL0U: /* Not implemented */  break;
+      case CLK_SRC_PLL0A: /* Not implemented */  break;
+      
+      case CLK_SRC_PLL1:
+        tmp = GetPLL1Param ();
+        mul *= (tmp     ) & 0xFF;       /* PLL input clock multiplier         */
+        div *= (tmp >> 8) & 0xFF;       /* PLL input clock divider            */
+        break;
+      
+      default:
+        return (0);                     /* Clock not running or not supported */
+    }
+    if (main_freq == 0) {
+      clk_sel = GetClkSel (clk_sel);
+    }
+  }
+  while (main_freq == 0);
+
+  return ((main_freq * mul) / div);
+}
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) {
+  /* Check BASE_M4_CLK connection */
+  uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
+
+  /* Update core clock frequency */
+  SystemCoreClock = GetClockFreq (base_src);
+}
+
+
+extern uint32_t getPC (void);
+
+/*----------------------------------------------------------------------------
+  Initialize the system
+ *----------------------------------------------------------------------------*/
+void SystemInit (void) {
+
+  #if (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  /* Disable SysTick timer                                                    */
+  SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+#ifdef CORE_M4
+  /* Set vector table pointer */
+  SCB->VTOR = getPC() & 0xFFF00000;
+#endif
+  /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
+  SetClock();
+
+  /* Update SystemCoreClock variable */
+  SystemCoreClockUpdate();
+
+  /* Configure External Memory Controller */
+  SystemInit_ExtMemCtl ();
+}
diff --git a/bsp/xplorer4330/Libraries/Device/SConscript b/bsp/xplorer4330/Libraries/Device/SConscript
new file mode 100644
index 0000000000..d0aac1b070
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/SConscript
@@ -0,0 +1,30 @@
+# RT-Thread building script for component
+
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Split('''
+NXP/LPC43xx/Source/Templates/system_LPC43xx.c
+''')
+CPPPATH = [cwd + '/NXP/LPC43xx/Include', cwd + '/../CMSIS/Include']
+CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
+
+# add for startup script 
+if rtconfig.USE_CORE =='CORE_M4':
+	if rtconfig.CROSS_TOOL == 'gcc':
+		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s']
+	elif rtconfig.CROSS_TOOL == 'keil':
+		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s']
+	elif rtconfig.CROSS_TOOL == 'iar':
+		src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s']
+else:
+	if rtconfig.CROSS_TOOL == 'gcc':
+		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s']
+	elif rtconfig.CROSS_TOOL == 'keil':
+		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s']
+	elif rtconfig.CROSS_TOOL == 'iar':
+		src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s']
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/xplorer4330/M0/SConscript b/bsp/xplorer4330/M0/SConscript
new file mode 100644
index 0000000000..e2c31c0755
--- /dev/null
+++ b/bsp/xplorer4330/M0/SConscript
@@ -0,0 +1,13 @@
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(os.path.join(cwd, '..'))
+
+for d in list:
+    if (d != 'M4' and d != 'M0'):
+        path = os.path.join(cwd, '..', d)
+        if os.path.isfile(os.path.join(path, 'SConscript')):
+            objs = objs + SConscript(os.path.join(path, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/xplorer4330/M0/SConstruct b/bsp/xplorer4330/M0/SConstruct
new file mode 100644
index 0000000000..f6f21f4ec4
--- /dev/null
+++ b/bsp/xplorer4330/M0/SConstruct
@@ -0,0 +1,29 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# do building 
+DoBuilding(TARGET, objs)
diff --git a/bsp/xplorer4330/M0/rtconfig.h b/bsp/xplorer4330/M0/rtconfig.h
new file mode 100644
index 0000000000..84fc28028c
--- /dev/null
+++ b/bsp/xplorer4330/M0/rtconfig.h
@@ -0,0 +1,230 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX 8
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE   4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX  32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
+#define RT_TICK_PER_SECOND  1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE  512
+// <bool name="RT_USING_MODULE" description="Using Application Module" default="true" />
+//#define RT_USING_MODULE
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
+#define RT_DEBUG_INIT   0
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+#define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO    4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE  512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND    100
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+#define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    256
+// <bool name="RT_USING_MTD_NAND" description="Using MTD NAND Framework" default="true" />
+//#define RT_USING_MTD_NAND
+// <bool name="RT_MTD_NAND_DEBUG" description="Enable MTD NAND Framework Debug" default="true" />
+//#define RT_MTD_NAND_DEBUG
+// <bool name="RT_USING_NFTL" description="Using NFTL layer" default="true" />
+//#define RT_USING_NFTL
+// <bool name="RT_USING_SPI" description="Using SPI Device Driver Framework" default="true" />
+//#define RT_USING_SPI
+// <bool name="RT_USING_I2C" description="Using I2C Device Driver Framework" default="true" />
+//#define RT_USING_I2C
+// <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" />
+//#define RT_USING_RTC
+// <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" />
+#define RT_MMCSD_THREAD_PREORITY    15
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE  128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+//#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE 4096
+// <bool name="FINSH_USING_MSH" description="Using module shell in finsh" default="true" />
+//#define FINSH_USING_MSH
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
+// #define RT_USING_NEWLIB
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+//#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+//#define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+//#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
+#define DFS_FILESYSTEM_TYPES_MAX  4
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX 4
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX           16
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" />
+#define RT_DFS_ELM_DRIVES    4
+// <bool name="RT_DFS_ELM_REENTRANT" description="Support reentrant" default="true" />
+#define RT_DFS_ELM_REENTRANT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN with static LFN working buffer">1</item>
+// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
+// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN  3
+// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
+#define RT_DFS_ELM_CODE_PAGE    936
+// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
+#define RT_DFS_ELM_CODE_PAGE_FILE
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN  256
+// <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" />
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  4096
+// <bool name="RT_DFS_ELM_USE_ERASE" description="Enable erase feature for flash" default="true" />
+#define RT_DFS_ELM_USE_ERASE
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_ROMFS" description="Using ROMFS" default="false" />
+//#define RT_USING_DFS_ROMFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS" default="false" />
+//#define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="The exported NFS host path" default="192.168.1.10:/" />
+#define RT_NFS_HOST_EXPORT  "192.168.1.20:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+//#define RT_USING_LWIP
+// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
+#define RT_USING_LWIP141
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
+#define RT_LWIP_PBUF_NUM    4
+// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
+#define RT_LWIP_TCP_PCB_NUM 3
+// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
+#define RT_LWIP_TCP_SND_BUF 4086
+// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
+#define RT_LWIP_TCP_WND 2048
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+// #define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
+#define RT_LWIP_TCP_SEG_NUM 8
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+
+
+// </RDTConfigurator>
+
+
+#endif
diff --git a/bsp/xplorer4330/M0/rtconfig.py b/bsp/xplorer4330/M0/rtconfig.py
new file mode 100644
index 0000000000..f548669122
--- /dev/null
+++ b/bsp/xplorer4330/M0/rtconfig.py
@@ -0,0 +1,139 @@
+import os
+
+# core to be use
+USE_CORE = 'CORE_M0'
+#USE_CORE = 'CORE_M4'
+
+# toolchains options
+ARCH='arm'
+
+if USE_CORE == 'CORE_M4':
+    CPU = 'cortex-m4'
+else:
+    CPU = 'cortex-m0'
+
+CROSS_TOOL='keil'
+
+
+# get setting from environment.
+if os.getenv('RTT_CC'):
+        CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM = 'gcc'
+    EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM = 'armcc'
+    EXEC_PATH = r'D:/Keil'
+elif CROSS_TOOL == 'iar':
+    PLATFORM = 'iar'
+    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    if USE_CORE == 'CORE_M4':
+        DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
+    CFLAGS = DEVICE 
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    if USE_CORE == 'CORE_M4':
+        CFLAGS += ' --cpu=Cortex-M4' 
+        CFLAGS += ' --fpu=None'
+    else:
+        CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e' 
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+    CFLAGS += ' --use_c++_inline'
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    if USE_CORE == 'CORE_M4':
+        AFLAGS += ' --cpu Cortex-M4' 
+        AFLAGS += ' --fpu None' 
+    else:
+        AFLAGS += ' --cpu Cortex-M0' 
+
+    LFLAGS = ' --config lpc43xx_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny' 
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''
diff --git a/bsp/xplorer4330/M0/template.uvproj b/bsp/xplorer4330/M0/template.uvproj
new file mode 100644
index 0000000000..12a910780f
--- /dev/null
+++ b/bsp/xplorer4330/M0/template.uvproj
@@ -0,0 +1,777 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>LPC4330 SPIFI</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4330 CM0</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx_M0.s" ("NXP LPC43xx CM0 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O910 -S8 -C1 -FO7 -FD10000000 -FC800 -FN0)</FlashDriverDll>
+          <DeviceId>6914</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>TARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>DARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>0</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>1</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>0</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x14000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x14000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+    <Target>
+      <TargetName>LPC4330 RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4330 CM0</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx_M0.s" ("NXP LPC43xx CM0 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O910 -S8 -C1 -FO7 -FD10000000 -FC800 -FN0)</FlashDriverDll>
+          <DeviceId>6914</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>TARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>DARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Dbg_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>1</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>0</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>0</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x10000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/xplorer4330/applications/SConscript b/bsp/xplorer4330/applications/SConscript
index 449a5f6ac1..01eb940dfb 100644
--- a/bsp/xplorer4330/applications/SConscript
+++ b/bsp/xplorer4330/applications/SConscript
@@ -2,10 +2,10 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
-cwd     = GetCurrentDir()
-src     = Glob('*.c')
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
 CPPPATH = [cwd, str(Dir('#'))]
 
-group = DefineGroup('applications', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/xplorer4330/applications/application.c b/bsp/xplorer4330/applications/application.c
index 295fb903bb..e40ad02e48 100644
--- a/bsp/xplorer4330/applications/application.c
+++ b/bsp/xplorer4330/applications/application.c
@@ -1,7 +1,7 @@
 /*
  * File      : application.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -9,54 +9,76 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2009-01-05     Bernard      the first version
+ * 2014-07-13     xiaonong     port for lpc43xx
  */
 
-/**
- * @addtogroup LPC4330
- */
-
-/*@{*/
-
 #include <rtthread.h>
-
-#ifdef RT_USING_COMPONENTS_INIT
-#include <components.h>
+#include <board.h>
+#include <rtdevice.h>
+#include "drv_led.h"
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
 #endif
 
-#include "board_ngx_xplorer_18304330.h"
-
-static void rt_init_thread_entry(void *parameter)
+/* thread phase init */
+void rt_init_thread_entry(void *parameter)
 {
-    Board_LED_Init();
-
-#ifdef RT_USING_COMPONENTS_INIT
-    /* initialization RT-Thread Components */
-    rt_components_init();
+#ifdef RT_USING_FINSH
+    /* initialize finsh */
+    finsh_system_init();
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-
+}
+/*the led thread*/
+ALIGN(RT_ALIGN_SIZE)
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+static void led_thread_entry(void *parameter)
+{
+    rt_uint8_t led_value = 0;
+    rt_device_t led_dev;
+    rt_led_hw_init();
+    led_dev = rt_device_find("led");
+    if (led_dev == RT_NULL)
+    {
+        rt_kprintf("can not find the led device!\n");
+        return;
+    }
     while (1)
     {
-        Board_LED_Set(0, 1);
-        rt_thread_delay(50);
-        Board_LED_Set(0, 0);
-        rt_thread_delay(50);
+        /* led0 on */
+        led_value = 1;
+        led_dev->write(led_dev, 0, &led_value, 1);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
+
+        /* led0 off */
+        led_value = 0;
+        led_dev->write(led_dev, 0, &led_value, 1);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
     }
 }
 
-void rt_application_init(void)
+int rt_application_init(void)
 {
     rt_thread_t tid;
-
+    rt_err_t result;
     tid = rt_thread_create("init",
-                           rt_init_thread_entry,
-                           RT_NULL,
-                           2048,
-                           RT_THREAD_PRIORITY_MAX / 3,
-                           20);
-
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
+                           rt_init_thread_entry, RT_NULL,
+                           2048, RT_THREAD_PRIORITY_MAX / 3, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+    /* init led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t *)&led_stack[0],
+                            sizeof(led_stack),
+                            20,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+    return 0;
 }
-
-/*@}*/
diff --git a/bsp/xplorer4330/applications/startup.c b/bsp/xplorer4330/applications/startup.c
index f4c2779078..f6cf534b03 100644
--- a/bsp/xplorer4330/applications/startup.c
+++ b/bsp/xplorer4330/applications/startup.c
@@ -1,7 +1,7 @@
 /*
  * File      : startup.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -10,67 +10,49 @@
  * Change Logs:
  * Date           Author       Notes
  * 2009-01-05     Bernard      first implementation
- * 2012-12-11     lgnq         modified for LPC4330
+ * 2014-07-13     xiaonong      for LPC43xx
  */
 
 #include <rthw.h>
 #include <rtthread.h>
 
-#include "platform.h"
+#include "board.h"
 
-/**
- * @addtogroup LPC4330
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define LPC4300_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define LPC4300_SRAM_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define LPC4300_SRAM_BEGIN    (&__bss_end)
-#endif
+extern int rt_application_init(void);
 
 /**
  * This function will startup RT-Thread RTOS.
  */
 void rtthread_startup(void)
 {
-    /* init board */
+    /* initialize board */
     rt_hw_board_init();
 
     /* show version */
     rt_show_version();
 
 #ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_system_heap_init((void *)LPC4300_SRAM_BEGIN, (void *)(0x10000000 + 1024*128));
+#if LPC_EXT_SDRAM
+    rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
+    sram_init();
+#else
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
 #endif
 
-    /* init scheduler system */
+    /* initialize scheduler system */
     rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-    /* init all device */
-    rt_device_init_all();
-#endif
-
-    /* init application */
-    rt_application_init();
-
-    /* initialize timer */
+    /* initialize system timer*/
     rt_system_timer_init();
 
-    /* init timer thread */
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize timer thread */
     rt_system_timer_thread_init();
 
-    /* init idle thread */
+    /* initialize idle thread */
     rt_thread_idle_init();
 
     /* start scheduler */
@@ -90,5 +72,3 @@ int main(void)
 
     return 0;
 }
-
-/*@}*/
diff --git a/bsp/xplorer4330/drivers/SConscript b/bsp/xplorer4330/drivers/SConscript
index 01177dc4c9..e5f4cd4945 100644
--- a/bsp/xplorer4330/drivers/SConscript
+++ b/bsp/xplorer4330/drivers/SConscript
@@ -1,16 +1,14 @@
-Import('RTT_ROOT')
-Import('rtconfig')
 from building import *
 
 cwd = GetCurrentDir()
 src = Glob('*.c')
 
 # remove no need file.
-if GetDepend('RT_USING_SERIAL') == False:
-    SrcRemove(src, 'usart.c')
+if GetDepend('RT_USING_LWIP') == False:
+	SrcRemove(src, 'drv_emac.c')
 
 CPPPATH = [cwd]
 
-group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/xplorer4330/drivers/board.c b/bsp/xplorer4330/drivers/board.c
new file mode 100644
index 0000000000..421298c19e
--- /dev/null
+++ b/bsp/xplorer4330/drivers/board.c
@@ -0,0 +1,77 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2014-06-20     xiaonong     ported to LPC43xx
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+extern void SystemCoreClockUpdate(void);
+/**
+ * This function will initial LPC43xx board.
+ */
+void rt_hw_board_init()
+{
+#ifdef CORE_M4
+    /* NVIC Configuration */
+#define NVIC_VTOR_MASK              0x3FFFFF80
+#ifdef  VECT_TAB_RAM
+    /* Set the Vector Table base location at 0x10000000 */
+    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+#else  /* VECT_TAB_FLASH  */
+    /* Set the Vector Table base location at 0x00000000 */
+    SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
+#endif
+#endif
+    /* update the core clock */
+    SystemCoreClockUpdate();
+
+    /* init systick */
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1);
+
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+
+    /* init uart device */
+    rt_hw_uart_init();
+
+    /* setup the console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#if LPC_EXT_SDRAM == 1
+    lpc_sdram_hw_init();
+    mpu_init();
+#endif
+}
+
+
+
diff --git a/bsp/xplorer4330/drivers/board.h b/bsp/xplorer4330/drivers/board.h
new file mode 100644
index 0000000000..22515a125e
--- /dev/null
+++ b/bsp/xplorer4330/drivers/board.h
@@ -0,0 +1,60 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2010-02-04     Magicoe      add board.h to LPC176x bsp
+ * 2013-12-18     Bernard      porting to LPC4088 bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "LPC43xx.h"
+#include <rtthread.h>
+
+/* disable SDRAM in default */
+#ifndef LPC_EXT_SDRAM
+#define LPC_EXT_SDRAM       0
+#endif
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
+#define LPC_EXT_SDRAM_BEGIN    0xA0000000
+// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
+#define LPC_EXT_SDRAM_END      0xA2000000
+
+// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
+#define RT_USING_UART0
+// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
+//#define RT_USING_UART1
+// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
+//#define RT_USING_UART2
+
+// </RDTConfigurator>
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+#define HEAP_END    (void*)(0x10000000 + 0x20000)
+
+void rt_hw_board_init(void);
+int  rt_hw_board_heap_init(void);
+
+
+#endif
diff --git a/bsp/xplorer4330/drivers/drv_led.c b/bsp/xplorer4330/drivers/drv_led.c
new file mode 100644
index 0000000000..d7e14eb19e
--- /dev/null
+++ b/bsp/xplorer4330/drivers/drv_led.c
@@ -0,0 +1,162 @@
+#include <rtthread.h>
+#include "board.h"
+#include "drv_led.h"
+
+
+/**
+*
+* LED1 <==> GPIO1[11]
+* LED2 <==> GPIO1[12]
+*
+**/
+
+#define LED_NUM    2
+
+#define LED1_PIN   11
+#define LED1_PORT  1
+
+#define LED2_PIN   12
+#define LED2_PORT  1
+
+struct led_ctrl
+{
+    uint8_t num;
+    uint8_t port;
+};
+
+struct lpc_led
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    struct led_ctrl ctrl[LED_NUM];
+};
+
+static struct lpc_led led;
+
+static rt_err_t rt_led_init(rt_device_t dev)
+{
+    /* Enable clock and init GPIO outputs */
+    LPC_CCU1->CLK_M4_GPIO_CFG  = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+    while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
+
+    /* set GPIO1[11] GPIO1[12] as GPIO. */
+    LPC_SCU->SFSP2_11  =  0;                              /* GPIO1[11]          */
+    LPC_SCU->SFSP2_12  =  0;                              /* GPIO1[12]          */
+    /* set GPIO1[11]  GPIO1[12]  output. */
+    LPC_GPIO_PORT->DIR[LED1_PORT] |= 0x01 << LED1_PIN;
+    LPC_GPIO_PORT->DIR[LED2_PORT] |= 0x01 << LED2_PIN;
+    /* turn off all the led */
+    LPC_GPIO_PORT->SET[LED1_PORT] |= 0x01 << LED1_PIN;
+    LPC_GPIO_PORT->SET[LED2_PORT] |= 0x01 << LED2_PIN;
+
+
+    led.ctrl[0].num = LED1_PIN;
+    led.ctrl[0].port = LED1_PORT;
+    led.ctrl[1].num = LED2_PIN;
+    led.ctrl[1].port = LED2_PORT;
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
+                             rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nr = size;
+    rt_uint8_t *value = buffer;
+
+    RT_ASSERT(dev == &led.parent);
+    RT_ASSERT((pos + size) <= LED_NUM);
+
+    for (index = 0; index < nr; index++)
+    {
+        if ((LPC_GPIO_PORT->PIN[led.ctrl[pos + index].port] & (1 << led.ctrl[pos + index].num)) != 0)
+        {
+            *value = 0;
+        }
+        else
+        {
+            *value = 1;
+        }
+        value++;
+    }
+    return index;
+}
+
+static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
+                              const void *buffer, rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nw = size;
+    const rt_uint8_t *value = buffer;
+
+    RT_ASSERT(dev == &led.parent);
+    RT_ASSERT((pos + size) <= LED_NUM);
+
+    for (index = 0; index < nw; index++)
+    {
+        if (*value++)
+        {
+            LPC_GPIO_PORT->CLR[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
+        }
+        else
+        {
+            LPC_GPIO_PORT->SET[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
+        }
+    }
+    return index;
+}
+
+static rt_err_t rt_led_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev == &led.parent);
+
+    if (cmd == LED_DEVICE_CTRL)
+    {
+        rt_uint32_t *led_num = args;
+        *led_num = LED_NUM;
+    }
+    return RT_EOK;
+}
+
+int rt_led_hw_init(void)
+{
+    led.parent.type         = RT_Device_Class_Char;
+    led.parent.rx_indicate  = RT_NULL;
+    led.parent.tx_complete  = RT_NULL;
+    led.parent.init         = rt_led_init;
+    led.parent.open         = rt_led_open;
+    led.parent.close        = rt_led_close;
+    led.parent.read         = rt_led_read;
+    led.parent.write        = rt_led_write;
+    led.parent.control      = rt_led_control;
+    led.parent.user_data    = RT_NULL;
+
+    /* register a character device */
+    rt_device_register(&led.parent, "led", RT_DEVICE_FLAG_RDWR);
+    /* init led device */
+    rt_led_init(&led.parent);
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_led_hw_init);
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led_test(rt_uint32_t led_num, rt_uint32_t value)
+{
+    rt_uint8_t led_value = value;
+    rt_led_write(&led.parent, led_num, &led_value, 1);
+}
+FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 100).)
+#endif
diff --git a/bsp/xplorer4330/drivers/drv_led.h b/bsp/xplorer4330/drivers/drv_led.h
new file mode 100644
index 0000000000..183f8256c2
--- /dev/null
+++ b/bsp/xplorer4330/drivers/drv_led.h
@@ -0,0 +1,12 @@
+#ifndef __DRV_LED_H
+#define __DRV_LED_H
+
+/* Clock Control Unit register bits */
+#define CCU_CLK_CFG_RUN   (1 << 0)
+#define CCU_CLK_CFG_AUTO  (1 << 1)
+#define CCU_CLK_STAT_RUN  (1 << 0)
+
+#define LED_DEVICE_CTRL     0x81        /*LED control command*/
+
+int rt_led_hw_init(void);
+#endif
diff --git a/bsp/xplorer4330/drivers/drv_uart.c b/bsp/xplorer4330/drivers/drv_uart.c
new file mode 100644
index 0000000000..c8242277b2
--- /dev/null
+++ b/bsp/xplorer4330/drivers/drv_uart.c
@@ -0,0 +1,315 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-18     Bernard      The first version for LPC40xx
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_uart.h"
+
+struct lpc_uart
+{
+    LPC_USARTn_Type  *USART;
+    IRQn_Type USART_IRQn;
+};
+
+static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+//    struct lpc_uart *uart;
+
+
+    RT_ASSERT(serial != RT_NULL);
+    //  uart = (struct lpc_uart *)serial->parent.user_data;
+
+
+
+    // Initialize FIFO for UART0 peripheral
+//    UART_FIFOConfig(uart->USART, &UARTFIFOConfigStruct);
+
+//    UART_TxCmd(uart->USART, ENABLE);
+
+    return RT_EOK;
+}
+
+static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct lpc_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct lpc_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        uart->USART->IER &= ~UART_IER_RBRINT_EN;
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        uart->USART->IER |= UART_IER_RBRINT_EN;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int lpc_putc(struct rt_serial_device *serial, char c)
+{
+    struct lpc_uart *uart;
+
+    uart = (struct lpc_uart *)serial->parent.user_data;
+    while (!(uart->USART->LSR & 0x20));
+    uart->USART->THR = c;
+    return 1;
+}
+
+static int lpc_getc(struct rt_serial_device *serial)
+{
+    struct lpc_uart *uart;
+
+    uart = (struct lpc_uart *)serial->parent.user_data;
+
+    if (uart->USART->LSR & 0x01)
+    {
+        return (uart->USART->RBR);
+    }
+    return -1;
+}
+
+static const struct rt_uart_ops lpc_uart_ops =
+{
+    lpc_configure,
+    lpc_control,
+    lpc_putc,
+    lpc_getc,
+};
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct serial_ringbuffer uart0_int_rx;
+struct lpc_uart uart0 =
+{
+    LPC_USART0,
+    USART0_IRQn,
+};
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+    struct lpc_uart *uart;
+   volatile uint32_t intsrc, temp;
+
+    uart = &uart0;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Determine the interrupt source */
+    intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
+
+    switch (intsrc)
+    {
+
+    case UART_IIR_INTID_RLS:                                            /* Receive Line Status interrupt*/
+        /* read the line status */
+        intsrc = uart->USART->LSR;
+        /* Receive an error data */
+        if (intsrc & UART_LSR_PE)
+        {
+            temp = LPC_USART0->RBR;
+        }
+        break;
+
+    case UART_IIR_INTID_RDA:                                            /*  Receive data               */
+    case UART_IIR_INTID_CTI:                                            /*  Receive data timeout       */
+        /* read the data to buffer  */
+        while (uart->USART->LSR & UART_LSR_RDR)
+        {
+            rt_hw_serial_isr(&serial0);
+        }
+        break;
+
+    default:
+        break;
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#if defined(RT_USING_UART2)
+/* UART2 device driver structure */
+struct serial_ringbuffer uart2_int_rx;
+struct lpc_uart uart2 =
+{
+    LPC_USART2,
+    USART2_IRQn,
+};
+struct rt_serial_device serial2;
+
+void UART2_IRQHandler(void)
+{
+    struct lpc_uart *uart;
+    uint32_t intsrc, temp;
+
+    uart = &uart2;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Determine the interrupt source */
+    intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
+
+    switch (intsrc)
+    {
+
+    case UART_IIR_INTID_RLS:                                            /* Receive Line Status interrupt*/
+        /* read the line status */
+        intsrc = uart->USART->LSR;
+        /* Receive an error data */
+        if (intsrc & UART_LSR_PE)
+        {
+            temp = LPC_USART0->RBR;
+        }
+        break;
+
+    case UART_IIR_INTID_RDA:                                            /*  Receive data               */
+    case UART_IIR_INTID_CTI:                                            /*  Receive data timeout       */
+        /* read the data to buffer  */
+        while (uart->USART->LSR & UART_LSR_RDR)
+        {
+            rt_hw_serial_isr(&serial0);
+        }
+        break;
+
+    default:
+        break;
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+void rt_hw_uart_init(void)
+{
+    struct lpc_uart *uart;
+    struct serial_configure config;
+
+#ifdef RT_USING_UART0
+    uart = &uart0;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    serial0.ops    = &lpc_uart_ops;
+    serial0.int_rx = &uart0_int_rx;
+    serial0.config = config;
+
+    /* Enable GPIO register interface clock                                     */
+    LPC_CCU1->CLK_M4_GPIO_CFG     |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_GPIO_STAT  & 0x01));
+
+    /* Enable USART1 peripheral clock                                           */
+    LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
+    while (!(LPC_CCU2->CLK_APB0_USART0_STAT & 0x01));
+
+    /* Enable USART1 register interface clock                                   */
+    LPC_CCU1->CLK_M4_USART0_CFG   |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_USART0_STAT & 0x01));
+
+    /* Init GPIO pins                                                           */
+    LPC_SCU->SFSP6_4 = (1 << 6) |         /* Input buffer enabled               */
+                       (1 << 4) |        /* Pull-up disabled                   */
+                       (2 << 0) ;        /* Pin P6_4 used as U0_TXD            */
+
+    LPC_SCU->SFSP6_5 = (1 << 6) |         /* Input buffer enabled               */
+                       (1 << 4) |        /* Pull-up disabled                   */
+                       (2 << 0) ;        /* Pin P6_5 used as U0_RXD            */
+
+    /* Init USART0                                                              */
+    LPC_USART0->LCR    = 0x83;            /* 8 bits, no Parity, 1 Stop bit      */
+    LPC_USART0->DLL    = 0x06;            /* 115200 Baudrate @ 12 MHz IRC       */
+    LPC_USART0->DLM    = 0x00;
+    LPC_USART0->FDR    = 0xC1;
+    LPC_USART0->LCR    = 0x03;            /* DLAB = 0                           */
+    /* enable the receive interrupt */
+    LPC_USART0->IER |= UART_IER_RBRINT_EN;
+    /* preemption = 1, sub-priority = 1 */
+    NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
+
+    /* Enable Interrupt for UART channel */
+    NVIC_EnableIRQ(uart->USART_IRQn);
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          uart);
+#endif
+#ifdef RT_USING_UART2
+    uart = &uart2;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    serial2.ops    = &lpc_uart_ops;
+    serial2.int_rx = &uart2_int_rx;
+    serial2.config = config;
+
+    /* Enable GPIO register interface clock                                     */
+    LPC_CCU1->CLK_M4_GPIO_CFG     |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_GPIO_STAT  & 0x01));
+
+    /* Enable USART1 peripheral clock                                           */
+    LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
+    while (!(LPC_CCU2->CLK_APB2_USART2_STAT & 0x01));
+
+    /* Enable USART2 register interface clock                                   */
+    LPC_CCU1->CLK_M4_USART0_CFG   |= 0x01;
+    while (!(LPC_CCU1->CLK_M4_USART2_STAT & 0x01));
+
+    /* Init GPIO pins                                                           */
+    LPC_SCU->SFSP1_15 = (1 << 6) |         /* Input buffer enabled               */
+                        (1 << 4) |        /* Pull-up disabled                   */
+                        (1 << 0) ;        /* Pin P1_15 used as U2_TXD            */
+
+    LPC_SCU->SFSP1_16 = (1 << 6) |         /* Input buffer enabled               */
+                        (1 << 4) |        /* Pull-up disabled                   */
+                        (1 << 0) ;        /* Pin P1_16 used as U2_RXD            */
+
+    /* Init USART2                                                              */
+    LPC_USART2->LCR    = 0x83;            /* 8 bits, no Parity, 1 Stop bit      */
+    LPC_USART2->DLL    = 0x06;            /* 115200 Baudrate @ 12 MHz IRC       */
+    LPC_USART2->DLM    = 0x00;
+    LPC_USART2->FDR    = 0xC1;
+    LPC_USART2->LCR    = 0x03;            /* DLAB = 0                           */
+    /* enable the receive interrupt */
+    LPC_USART2->IER |= UART_IER_RBRINT_EN;
+    /* preemption = 1, sub-priority = 1 */
+    NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
+
+    /* Enable Interrupt for UART channel */
+    NVIC_EnableIRQ(uart->USART_IRQn);
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          uart);
+#endif
+}
diff --git a/bsp/xplorer4330/drivers/drv_uart.h b/bsp/xplorer4330/drivers/drv_uart.h
new file mode 100644
index 0000000000..69596c6b98
--- /dev/null
+++ b/bsp/xplorer4330/drivers/drv_uart.h
@@ -0,0 +1,228 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR    (3)         /*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+#define UART_RBR_MASKBIT    ((uint8_t)0xFF)         /*!< UART Received Buffer mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+#define UART_THR_MASKBIT    ((uint8_t)0xFF)         /*!< UART Transmit Holding mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+#define UART_LOAD_DLL(div)  ((div) & 0xFF)  /**< Macro for loading least significant halfs of divisors */
+#define UART_DLL_MASKBIT    ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+#define UART_DLM_MASKBIT    ((uint8_t)0xFF)         /*!< Divisor latch MSB bit mask */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)   /**< Macro for loading most significant halfs of divisors */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+#define UART_IER_RBRINT_EN      ((uint32_t)(1<<0))  /*!< RBR Interrupt enable*/
+#define UART_IER_THREINT_EN     ((uint32_t)(1<<1))  /*!< THR Interrupt enable*/
+#define UART_IER_RLSINT_EN      ((uint32_t)(1<<2))  /*!< RX line status interrupt enable*/
+#define UART1_IER_MSINT_EN      ((uint32_t)(1<<3))  /*!< Modem status interrupt enable */
+#define UART1_IER_CTSINT_EN     ((uint32_t)(1<<7))  /*!< CTS1 signal transition interrupt enable */
+#define UART_IER_ABEOINT_EN     ((uint32_t)(1<<8))  /*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT_EN     ((uint32_t)(1<<9))  /*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK        ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
+#define UART1_IER_BITMASK       ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+#define UART_IIR_INTSTAT_PEND   ((uint32_t)(1<<0))  /*!<Interrupt Status - Active low */
+#define UART_IIR_INTID_RLS      ((uint32_t)(3<<1))  /*!<Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RDA      ((uint32_t)(2<<1))  /*!<Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_CTI      ((uint32_t)(6<<1))  /*!<Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_THRE     ((uint32_t)(1<<1))  /*!<Interrupt identification: THRE interrupt*/
+#define UART1_IIR_INTID_MODEM   ((uint32_t)(0<<1))  /*!<Interrupt identification: Modem interrupt*/
+#define UART_IIR_INTID_MASK     ((uint32_t)(7<<1))  /*!<Interrupt identification: Interrupt ID mask */
+#define UART_IIR_FIFO_EN        ((uint32_t)(3<<6))  /*!<These bits are equivalent to UnFCR[0] */
+#define UART_IIR_ABEO_INT       ((uint32_t)(1<<8))  /*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT       ((uint32_t)(1<<9))  /*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK        ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+#define UART_FCR_FIFO_EN        ((uint8_t)(1<<0))   /*!< UART FIFO enable */
+#define UART_FCR_RX_RS          ((uint8_t)(1<<1))   /*!< UART FIFO RX reset */
+#define UART_FCR_TX_RS          ((uint8_t)(1<<2))   /*!< UART FIFO TX reset */
+#define UART_FCR_DMAMODE_SEL    ((uint8_t)(1<<3))   /*!< UART DMA mode selection */
+#define UART_FCR_TRG_LEV0       ((uint8_t)(0))      /*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1       ((uint8_t)(1<<6))   /*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2       ((uint8_t)(2<<6))   /*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3       ((uint8_t)(3<<6))   /*!< UART FIFO trigger level 3: 14 character */
+#define UART_FCR_BITMASK        ((uint8_t)(0xCF))   /*!< UART FIFO control bit mask */
+#define UART_TX_FIFO_SIZE       (16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+#define UART_LCR_WLEN5          ((uint8_t)(0))          /*!< UART 5 bit data mode */
+#define UART_LCR_WLEN6          ((uint8_t)(1<<0))       /*!< UART 6 bit data mode */
+#define UART_LCR_WLEN7          ((uint8_t)(2<<0))       /*!< UART 7 bit data mode */
+#define UART_LCR_WLEN8          ((uint8_t)(3<<0))       /*!< UART 8 bit data mode */
+#define UART_LCR_STOPBIT_SEL    ((uint8_t)(1<<2))       /*!< UART Two Stop Bits Select */
+#define UART_LCR_PARITY_EN      ((uint8_t)(1<<3))       /*!< UART Parity Enable */
+#define UART_LCR_PARITY_ODD     ((uint8_t)(0))          /*!< UART Odd Parity Select */
+#define UART_LCR_PARITY_EVEN    ((uint8_t)(1<<4))       /*!< UART Even Parity Select */
+#define UART_LCR_PARITY_F_1     ((uint8_t)(2<<4))       /*!< UART force 1 stick parity */
+#define UART_LCR_PARITY_F_0     ((uint8_t)(3<<4))       /*!< UART force 0 stick parity */
+#define UART_LCR_BREAK_EN       ((uint8_t)(1<<6))       /*!< UART Transmission Break enable */
+#define UART_LCR_DLAB_EN        ((uint8_t)(1<<7))       /*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK        ((uint8_t)(0xFF))       /*!< UART line control bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+#define UART1_MCR_DTR_CTRL      ((uint8_t)(1<<0))       /*!< Source for modem output pin DTR */
+#define UART1_MCR_RTS_CTRL      ((uint8_t)(1<<1))       /*!< Source for modem output pin RTS */
+#define UART1_MCR_LOOPB_EN      ((uint8_t)(1<<4))       /*!< Loop back mode select */
+#define UART1_MCR_AUTO_RTS_EN   ((uint8_t)(1<<6))       /*!< Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN   ((uint8_t)(1<<7))       /*!< Enable Auto CTS flow-control */
+#define UART1_MCR_BITMASK       ((uint8_t)(0x0F3))      /*!< UART1 bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+#define UART_LSR_RDR        ((uint8_t)(1<<0))   /*!<Line status register: Receive data ready*/
+#define UART_LSR_OE         ((uint8_t)(1<<1))   /*!<Line status register: Overrun error*/
+#define UART_LSR_PE         ((uint8_t)(1<<2))   /*!<Line status register: Parity error*/
+#define UART_LSR_FE         ((uint8_t)(1<<3))   /*!<Line status register: Framing error*/
+#define UART_LSR_BI         ((uint8_t)(1<<4))   /*!<Line status register: Break interrupt*/
+#define UART_LSR_THRE       ((uint8_t)(1<<5))   /*!<Line status register: Transmit holding register empty*/
+#define UART_LSR_TEMT       ((uint8_t)(1<<6))   /*!<Line status register: Transmitter empty*/
+#define UART_LSR_RXFE       ((uint8_t)(1<<7))   /*!<Error in RX FIFO*/
+#define UART_LSR_BITMASK    ((uint8_t)(0xFF))   /*!<UART Line status bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+#define UART1_MSR_DELTA_CTS     ((uint8_t)(1<<0))   /*!< Set upon state change of input CTS */
+#define UART1_MSR_DELTA_DSR     ((uint8_t)(1<<1))   /*!< Set upon state change of input DSR */
+#define UART1_MSR_LO2HI_RI      ((uint8_t)(1<<2))   /*!< Set upon low to high transition of input RI */
+#define UART1_MSR_DELTA_DCD     ((uint8_t)(1<<3))   /*!< Set upon state change of input DCD */
+#define UART1_MSR_CTS           ((uint8_t)(1<<4))   /*!< Clear To Send State */
+#define UART1_MSR_DSR           ((uint8_t)(1<<5))   /*!< Data Set Ready State */
+#define UART1_MSR_RI            ((uint8_t)(1<<6))   /*!< Ring Indicator State */
+#define UART1_MSR_DCD           ((uint8_t)(1<<7))   /*!< Data Carrier Detect State */
+#define UART1_MSR_BITMASK       ((uint8_t)(0xFF))   /*!< MSR register bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+#define UART_SCR_BIMASK     ((uint8_t)(0xFF))   /*!< UART Scratch Pad bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+#define UART_ACR_START              ((uint32_t)(1<<0))  /**< UART Auto-baud start */
+#define UART_ACR_MODE               ((uint32_t)(1<<1))  /**< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART       ((uint32_t)(1<<2))  /**< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR        ((uint32_t)(1<<8))  /**< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR        ((uint32_t)(1<<9))  /**< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK            ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+#define UART_ICR_IRDAEN         ((uint32_t)(1<<0))          /**< IrDA mode enable */
+#define UART_ICR_IRDAINV        ((uint32_t)(1<<1))          /**< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN    ((uint32_t)(1<<2))          /**< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n)    ((uint32_t)((n&0x07)<<3))   /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK        ((uint32_t)(0x3F))          /*!< UART IRDA bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART half duplex register
+ **********************************************************************/
+#define UART_HDEN_HDEN          ((uint32_t)(1<<0))          /**< enable half-duplex mode*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART smart card interface control register
+ **********************************************************************/
+#define UART_SCICTRL_SCIEN      ((uint32_t)(1<<0))          /**< enable asynchronous half-duplex smart card interface*/
+#define UART_SCICTRL_NACKDIS    ((uint32_t)(1<<1))          /**< NACK response is inhibited*/
+#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2))          /**< ISO7816-3 protocol T1 is selected*/
+#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5))   /**< number of retransmission*/
+#define UART_SCICTRL_GUARDTIME(n)   ((uint32_t)((n&0xFF)<<8))   /**< Extra guard time*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART synchronous control register
+ **********************************************************************/
+#define UART_SYNCCTRL_SYNC      ((uint32_t)(1<<0))          /**< enable synchronous mode*/
+#define UART_SYNCCTRL_CSRC_MASTER   ((uint32_t)(1<<1))      /**< synchronous master mode*/
+#define UART_SYNCCTRL_FES       ((uint32_t)(1<<2))          /**< sample on falling edge*/
+#define UART_SYNCCTRL_TSBYPASS  ((uint32_t)(1<<3))          /**< to be defined*/
+#define UART_SYNCCTRL_CSCEN     ((uint32_t)(1<<4))          /**< continuous running clock enable (master mode only)*/
+#define UART_SYNCCTRL_STARTSTOPDISABLE  ((uint32_t)(1<<5))  /**< do not send start/stop bit*/
+#define UART_SYNCCTRL_CCCLR     ((uint32_t)(1<<6))          /**< stop continuous clock*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+#define UART_FDR_DIVADDVAL(n)   ((uint32_t)(n&0x0F))        /**< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n)      ((uint32_t)((n<<4)&0xF0))   /**< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK        ((uint32_t)(0xFF))          /**< UART Fractional Divider register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+#define UART1_TER_TXEN          ((uint8_t)(1<<7))       /*!< Transmit enable bit */
+#define UART1_TER_BITMASK       ((uint8_t)(0x80))       /**< UART Transmit Enable Register bit mask */
+#define UART0_2_3_TER_TXEN      ((uint8_t)(1<<0))       /*!< Transmit enable bit */
+#define UART0_2_3_TER_BITMASK   ((uint8_t)(0x01))       /**< UART Transmit Enable Register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+#define UART_RS485CTRL_NMM_EN       ((uint32_t)(1<<0))  /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
+is disabled */
+#define UART_RS485CTRL_RX_DIS       ((uint32_t)(1<<1))  /*!< The receiver is disabled */
+#define UART_RS485CTRL_AADEN        ((uint32_t)(1<<2))  /*!< Auto Address Detect (AAD) is enabled */
+#define UART_RS485CTRL_SEL_DTR      ((uint32_t)(1<<3))  /*!< If direction control is enabled
+(bit DCTRL = 1), pin DTR is used for direction control */
+#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))  /*!< Enable Auto Direction Control */
+#define UART_RS485CTRL_OINV_1       ((uint32_t)(1<<5))  /*!< This bit reverses the polarity of the direction
+control signal on the RTS (or DTR) pin. The direction control pin
+    will be driven to logic "1" when the transmitter has data to be sent */
+#define UART_RS485CTRL_BITMASK      ((uint32_t)(0x3F))  /**< RS485 control bit-mask value */
+
+    /*********************************************************************//**
+     * Macro defines for Macro defines for UART1 RS-485 Address Match register
+     **********************************************************************/
+#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF))    /**< Bit mask value */
+
+    /*********************************************************************//**
+     * Macro defines for Macro defines for UART1 RS-485 Delay value register
+     **********************************************************************/
+    /* Macro defines for UART1 RS-485 Delay value register */
+#define UART_RS485DLY_BITMASK       ((uint8_t)(0xFF))   /** Bit mask value */
+
+    /*********************************************************************//**
+     * Macro defines for Macro defines for UART FIFO Level register
+     **********************************************************************/
+#define UART_FIFOLVL_RXFIFOLVL(n)   ((uint32_t)(n&0x0F))        /**< Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n)   ((uint32_t)((n>>8)&0x0F))   /**< Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_BITMASK        ((uint32_t)(0x0F0F))        /**< UART FIFO Level Register bit mask */
+
+
+
+    void rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/xplorer4330/drivers/platform.c b/bsp/xplorer4330/drivers/platform.c
deleted file mode 100644
index 7156f95724..0000000000
--- a/bsp/xplorer4330/drivers/platform.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012 RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-12-13     lgnq         first implementation
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#include "cmsis.h"
-
-#ifdef RT_USING_SERIAL
-#include "usart.h"
-#endif
-
-/**
- * @addtogroup LPC4330
- */
-
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void SysTick_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_tick_increase();
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-/**
- * This function will initialize the LPC4330 Xplorer board.
- */
-void rt_hw_board_init(void)
-{
-    Board_Init();
-
-    /* Configure the SysTick - Generate interrupt @ 100 Hz*/
-    SysTick_Config(Chip_Clock_GetRate(CLK_MX_MXCORE) / 100);
-
-#ifdef RT_USING_SERIAL
-    rt_hw_serial_init();
-
-#ifdef RT_USING_CONSOLE
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-#endif
-}
-
-/*@}*/
diff --git a/bsp/xplorer4330/drivers/platform.h b/bsp/xplorer4330/drivers/platform.h
deleted file mode 100644
index 50bc17e071..0000000000
--- a/bsp/xplorer4330/drivers/platform.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * File      : platform.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-void rt_hw_board_init(void);
-
-#endif
diff --git a/bsp/xplorer4330/drivers/usart.c b/bsp/xplorer4330/drivers/usart.c
deleted file mode 100644
index 8866519343..0000000000
--- a/bsp/xplorer4330/drivers/usart.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * File      : usart.c
- * mb9bf506r uart driver
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-11-30     lgnq         first  version
- */
-
-#include <rtthread.h>
-#include <rtdevice.h>
-#include "usart.h"
-#include "uart_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-#if defined(RT_USING_UART0)
-/* UART0 device driver structure */
-struct serial_ringbuffer uart0_int_rx;
-struct uart_device uart0 =
-{
-    LPC_USART0,
-    USART0_IRQn,
-};
-struct rt_serial_device serial0;
-
-void UART0_IRQHandler(void)
-{
-    UART_Int_Status status;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    status = Chip_UART_GetIntStatus(LPC_USART0);
-
-    /* error */
-    if (status == UART_ERROR)
-    {
-        return;
-    }
-
-    /* ready for Read Data */
-    if (status & READY_TO_RECEIVE)
-    {
-        rt_hw_serial_isr(&serial0);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif
-
-#if defined(RT_USING_UART1)
-/* UART1 device driver structure */
-struct serial_ringbuffer uart1_int_rx;
-struct uart_device uart1 =
-{
-    LPC_UART1,
-    USART1_IRQn,
-};
-struct rt_serial_device serial1;
-
-void UART1_IRQHandler(void)
-{
-    UART_Int_Status status;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    status = Chip_UART_GetIntStatus(LPC_UART1);
-
-    /* error */
-    if (status == UART_ERROR)
-    {
-        return;
-    }
-
-    /* ready for Read Data */
-    if (status & READY_TO_RECEIVE)
-    {
-        rt_hw_serial_isr(&serial1);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif
-
-#if defined(RT_USING_UART2)
-/* UART2 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
-struct uart_device uart2 =
-{
-    LPC_USART2,
-    USART2_IRQn,
-};
-struct rt_serial_device serial2;
-
-void UART2_IRQHandler(void)
-{
-    UART_Int_Status status;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    status = Chip_UART_GetIntStatus(LPC_USART2);
-
-    /* error */
-    if (status == UART_ERROR)
-    {
-        return;
-    }
-
-    /* ready for Read Data */
-    if (status & READY_TO_RECEIVE)
-    {
-        rt_hw_serial_isr(&serial2);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif
-
-#if defined(RT_USING_UART3)
-/* UART3 device driver structure */
-struct serial_ringbuffer uart3_int_rx;
-struct uart_device uart3 =
-{
-    LPC_USART3,
-    USART3_IRQn,
-};
-struct rt_serial_device serial3;
-
-void UART3_IRQHandler(void)
-{
-    UART_Int_Status status;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    status = Chip_UART_GetIntStatus(LPC_USART3);
-
-    /* error */
-    if (status == UART_ERROR)
-    {
-        return;
-    }
-
-    /* ready for Read Data */
-    if (status & READY_TO_RECEIVE)
-    {
-        rt_hw_serial_isr(&serial3);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif
-
-void uart_pin_setup(void)
-{
-#if defined(RT_USING_UART0)
-    Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2);                   /* P6.5 : UART0_TXD */
-    Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);  /* P6.4 : UART0_RXD */
-#endif
-
-#if defined(RT_USING_UART1)
-    Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2);                  /* P1.13 : UART1_TXD */
-    Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P1.14 : UART1_RX */
-#endif
-}
-
-static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct uart_device *uart;
-    UART_DATABIT_Type   databit;
-    UART_STOPBIT_Type   stopbit;
-    UART_PARITY_Type    parity;
-
-    /* UART FIFO configuration Struct variable */
-    UART_FIFO_CFG_Type UARTFIFOConfigStruct;
-
-    RT_ASSERT(serial != RT_NULL);
-
-    uart = (struct uart_device *)serial->parent.user_data;
-
-    Chip_UART_Init(uart->uart_regs);
-
-    Chip_UART_SetBaud(uart->uart_regs, cfg->baud_rate);
-
-    /* set stop bits */
-    switch (cfg->stop_bits)
-    {
-    case STOP_BITS_1:
-        stopbit = UART_STOPBIT_1;
-        break;
-    case STOP_BITS_2:
-        stopbit = UART_STOPBIT_2;
-        break;
-    default:
-        return RT_ERROR;
-    }
-
-    /* set data bits */
-    switch (cfg->data_bits)
-    {
-    case DATA_BITS_5:
-        databit = UART_DATABIT_5;
-        break;
-    case DATA_BITS_6:
-        databit = UART_DATABIT_6;
-        break;
-    case DATA_BITS_7:
-        databit = UART_DATABIT_7;
-        break;
-    case DATA_BITS_8:
-        databit = UART_DATABIT_8;
-        break;
-    default:
-        return RT_ERROR;
-    }
-
-    /* set parity */
-    switch (cfg->parity)
-    {
-    case PARITY_NONE:
-        parity = UART_PARITY_NONE;
-        break;
-    case PARITY_EVEN:
-        parity = UART_PARITY_EVEN;
-        break;
-    case PARITY_ODD:
-        parity = UART_PARITY_ODD;
-        break;
-    default:
-        return RT_ERROR;
-    }
-
-    Chip_UART_ConfigData(uart->uart_regs, databit, parity, stopbit);
-
-    /* Enable UART Transmit */
-    Chip_UART_TxCmd(uart->uart_regs, ENABLE);
-
-    Chip_UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
-
-    /* Enable DMA mode in UART */
-    UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE;
-    /* Initialize FIFO for UART0 peripheral */
-    Chip_UART_FIFOConfig(uart->uart_regs, &UARTFIFOConfigStruct);
-
-    /* Enable UART Rx interrupt */
-    Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RBR, ENABLE);
-    /* Enable UART line status interrupt */
-    Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RLS, ENABLE);
-
-    /* Enable Interrupt for UART channel */
-    /* Priority = 1 */
-    NVIC_SetPriority(uart->irq_num, 1);
-
-    return RT_EOK;
-}
-
-static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct uart_device *)serial->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        UART_DISABLE_IRQ(uart->irq_num);
-        break;
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        UART_ENABLE_IRQ(uart->irq_num);
-        break;
-    }
-
-    return (RT_EOK);
-}
-
-static int uart_putc(struct rt_serial_device *serial, char c)
-{
-    struct uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-
-    uart = (struct uart_device *)serial->parent.user_data;
-
-    /* wait send buffer is empty */
-    while (!(uart->uart_regs->LSR & UART_LSR_THRE))
-        ;
-    /* write to send buffer */
-    uart->uart_regs->THR = c & UART_THR_MASKBIT;
-
-    return (1);
-}
-
-static int uart_getc(struct rt_serial_device *serial)
-{
-    struct uart_device *uart;
-    uint8_t ch;
-
-    RT_ASSERT(serial != RT_NULL);
-    
-    uart = (struct uart_device *)serial->parent.user_data;
-
-    /* receive buffer is full */
-    if (uart->uart_regs->LSR & UART_LSR_RDR)
-    {
-        ch = uart->uart_regs->RBR & UART_RBR_MASKBIT;
-
-        return (ch);
-    }
-    else
-        return (-1);
-}
-
-static struct rt_uart_ops uart_ops =
-{
-    uart_configure,
-    uart_control,
-    uart_putc,
-    uart_getc,
-};
-
-void rt_hw_serial_init(void)
-{
-    struct serial_configure config;
-
-    config.baud_rate = BAUD_RATE_115200;
-    config.data_bits = DATA_BITS_8;
-    config.parity    = PARITY_NONE;
-    config.stop_bits = STOP_BITS_1;
-
-    uart_pin_setup();
-
-#if defined(RT_USING_UART0)
-    serial0.ops    = &uart_ops;
-    serial0.int_rx = &uart0_int_rx;
-    serial0.config = config;
-
-    /* register UART0 device */
-    rt_hw_serial_register(&serial0,
-                          "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          &uart0);
-#endif
-
-#if defined(RT_USING_UART1)
-    serial1.ops    = &uart_ops;
-    serial1.int_rx = &uart1_int_rx;
-    serial1.config = config;
-
-    /* register UART1 device */
-    rt_hw_serial_register(&serial1,
-                          "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          &uart1);
-#endif
-
-#if defined(RT_USING_UART2)
-    serial2.ops    = &uart_ops;
-    serial2.int_rx = &uart2_int_rx;
-    serial2.config = config;
-
-    /* register UART2 device */
-    rt_hw_serial_register(&serial2,
-                          "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          &uart2);
-#endif
-
-#if defined(RT_USING_UART3)
-    serial3.ops    = &uart_ops;
-    serial3.int_rx = &uart3_int_rx;
-    serial3.config = config;
-
-    /* register UART3 device */
-    rt_hw_serial_register(&serial3,
-                          "uart3",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          &uart3);
-#endif
-}
diff --git a/bsp/xplorer4330/drivers/usart.h b/bsp/xplorer4330/drivers/usart.h
deleted file mode 100644
index e8d9c42ed9..0000000000
--- a/bsp/xplorer4330/drivers/usart.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * File      : usart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-05-15     lgnq         modified according bernard's implementaion.
- */
-
-#ifndef __USART_H__
-#define __USART_H__
-
-#include <rtthread.h>
-
-#include "chip_lpc43xx.h"
-#include "cmsis.h"
-
-/**
- *  Enable/DISABLE Interrupt Controller
- */
-#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
-#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
-
-struct uart_device
-{
-    LPC_USART_Type *uart_regs;
-
-    /* irq number */
-    IRQn_Type irq_num;
-};
-
-void rt_hw_serial_init(void);
-
-#endif
diff --git a/bsp/xplorer4330/libraries/SConscript b/bsp/xplorer4330/libraries/SConscript
index 744d8d7821..4c815c49b8 100644
--- a/bsp/xplorer4330/libraries/SConscript
+++ b/bsp/xplorer4330/libraries/SConscript
@@ -1,8 +1,9 @@
-# for module compiling
+# RT-Thread building script for bridge
+
 import os
 from building import *
 
-cwd  = GetCurrentDir()
+cwd = GetCurrentDir()
 objs = []
 list = os.listdir(cwd)
 
diff --git a/bsp/xplorer4330/libraries/lpc_board/SConscript b/bsp/xplorer4330/libraries/lpc_board/SConscript
deleted file mode 100644
index 9bd6c06726..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/SConscript
+++ /dev/null
@@ -1,44 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-
-#src = Glob('board_common/*.c')
-src  = []
-path = [cwd + '/board_common']
-
-if rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_4330':
-    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
-             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
-    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
-             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330']
-elif rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_1830':
-    src  += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
-             'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
-    path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
-             cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830']
-elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_4357':
-    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
-             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
-    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
-             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357']
-elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_1857':
-    src  += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
-             'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
-    path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
-             cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857']
-elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_4350':
-    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
-             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
-    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
-             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350']
-elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_1850':
-    src  += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
-             'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
-    path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
-             cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850']
-
-group = DefineGroup('lpc_board', src, depend = [''], CPPPATH = path)
-
-Return('group')
diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h b/bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h
deleted file mode 100644
index 4b5788a805..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * @brief Common board API functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_API_H_
-#define __BOARD_API_H_
-
-#include "lpc_types.h"
-#include <stdio.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_COMMON_API BOARD: Common board functions
- * @ingroup BOARD_Common
- * This file contains common board definitions that are shared across
- * boards and devices. All of these functions do not need to be
- * impemented for a specific board, but if they are implemented, they
- * should use this API standard.
- * @{
- */
-
-/**
- * @brief	Set up and initialize all required blocks and functions related to the board hardware.
- * @return	None
- */
-void Board_Init(void);
-
-/**
- * @brief	Initializes board UART for output, required for printf redirection
- * @return	None
- */
-void Board_Debug_Init(void);
-
-/**
- * @brief	Sends a single character on the UART, required for printf redirection
- * @param	ch	: character to send
- * @return	None
- */
-void Board_UARTPutChar(char ch);
-
-/**
- * @brief	Get a single character from the UART, required for scanf input
- * @return	EOF if not character was received, or character value
- */
-int Board_UARTGetChar(void);
-
-/**
- * @brief	Prints a string to the UART
- * @param	str	: Terminated string to output
- * @return	None
- */
-void Board_UARTPutSTR(char *str);
-
-/**
- * @brief	Initializes board LED(s)
- * @return	None
- */
-void Board_LED_Init(void);
-
-/**
- * @brief	Sets the state of a board LED to on or off
- * @param	LEDNumber	: LED number to set state for
- * @param	State		: true for on, false for off
- * @return	None
- */
-void Board_LED_Set(uint8_t LEDNumber, bool State);
-
-/**
- * @brief	Returns the current state of a board LED
- * @param	LEDNumber	: LED number to set state for
- * @return	true if the LED is on, otherwise false
- */
-bool Board_LED_Test(uint8_t LEDNumber);
-
-/**
- * @brief	Toggles the current state of a board LED
- * @param	LEDNumber	: LED number to change state for
- * @return	None
- */
-STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)
-{
-	Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));
-}
-
-
-/**
- * @brief	Current system clock rate, mainly used for sysTick
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief	Update system core clock rate, should be called if the
- *			system has a clock rate change
- * @return	None
- */
-void SystemCoreClockUpdate(void);
-
-/**
- * @brief	Turn on Board LCD Backlight
- * @param	Intensity	: Backlight intensity (0 = off, >=1 = on)
- * @return	None
- * On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
- * value will turn off or on the backlight. On some boards, a non-0 value will
- * control backlight intensity via a PWN. For PWM systems, the intensity value
- * is a percentage value between 0 and 100%.
- */
-void Board_LCD_Set_Backlight(uint8_t Intensity);
-
-/**
- * @brief Function prototype for a MS delay function. Board layers or example code may
- *        define this function as needed.
- */
-typedef void (*p_msDelay_func_t)(uint32_t);
-
-/* The DEBUG* functions are selected based on system configuration.
-   Code that uses the DEBUG* functions will have their I/O routed to
-   the UART, semihosting, or nowhere. */
-#if defined(DEBUG)
-#if defined(DEBUG_SEMIHOSTING)
-#define DEBUGINIT()
-#define DEBUGOUT(...) printf(__VA_ARGS__)
-#define DEBUGSTR(str) printf(str)
-#define DEBUGIN() (int) EOF
-
-#else
-#define DEBUGINIT() Board_Debug_Init()
-#define DEBUGOUT(...) printf(__VA_ARGS__)
-#define DEBUGSTR(str) Board_UARTPutSTR(str)
-#define DEBUGIN() Board_UARTGetChar()
-#endif /* defined(DEBUG_SEMIHOSTING) */
-
-#else
-#define DEBUGINIT()
-#define DEBUGOUT(...)
-#define DEBUGSTR(str)
-#define DEBUGIN() (int) EOF
-#endif /* defined(DEBUG) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_API_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h
deleted file mode 100644
index 89216542c0..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * @brief Common PHY functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LPC_PHY_H_
-#define __LPC_PHY_H_
-
-#include "board.h"
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers
- * @ingroup BOARD_Common
- * The simple PHY function API provides simple non-blocking PHY status
- * monitoring and initialization support for various Ethernet PHYs.
- * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires
- * several standard functions from the MAC driver for interfacing to the
- * PHY via a MII link (Chip_ENET_Start_MII_Write(), Chip_ENET_Is_MII_Busy(),
- * Chip_ENET_Start_MII_Read(), and Chip_ENET_Read_MII_Data()).
- *
- * Once initialized, just preiodically call the lpcPHYStsPoll() function
- * from the background loop or a thread and monitor the returned status
- * to determine if the PHY state has changed and the current PHY state.
- * @{
- */
-#define PHY_LINK_ERROR     (1 << 0)	/*!< PHY status bit for link error */
-#define PHY_LINK_BUSY      (1 << 1)	/*!< PHY status bit for MII link busy */
-#define PHY_LINK_CHANGED   (1 << 2)	/*!< PHY status bit for changed state (not persistent) */
-#define PHY_LINK_CONNECTED (1 << 3)	/*!< PHY status bit for connected state */
-#define PHY_LINK_SPEED100  (1 << 4)	/*!< PHY status bit for 100Mbps mode */
-#define PHY_LINK_FULLDUPLX (1 << 5)	/*!< PHY status bit for full duplex mode */
-
-/**
- * @brief	Phy status update state machine
- * @return	An Or'ed value of PHY_LINK_* statuses
- * This function can be called at any rate and will poll the the PHY status. Multiple
- * calls may be needed to determine PHY status.
- */
-uint32_t lpcPHYStsPoll(void);
-
-/**
- * @brief	Initialize the PHY
- * @param	rmii			: Initializes PHY for RMII mode if true, MII if false
- * @param	pDelayMsFunc	: Delay function (in mS) used for this driver
- * @return	PHY_LINK_ERROR or 0 on success
- * This function initializes the PHY. It will block until complete. It will not
- * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to
- * detect cable insertion.
- */
-uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_PHY_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c
deleted file mode 100644
index dbf55f2f01..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * @brief Mational DP83848 simple PHY driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "chip.h"
-#include "lpc_phy.h"
-
-/** @defgroup DP83848_PHY	BOARD: PHY status and control driver for the DP83848
- * @ingroup BOARD_PHY
- * Various functions for controlling and monitoring the status of the
- * DP83848 PHY.
- * @{
- */
-
-/** @brief  DP83848 PHY register offsets */
-#define DP8_BMCR_REG        0x0	/*!< Basic Mode Control Register */
-#define DP8_BMSR_REG        0x1	/*!< Basic Mode Status Reg */
-#define DP8_ANADV_REG       0x4	/*!< Auto_Neg Advt Reg  */
-#define DP8_ANLPA_REG       0x5	/*!< Auto_neg Link Partner Ability Reg */
-#define DP8_ANEEXP_REG      0x6	/*!< Auto-neg Expansion Reg  */
-#define DP8_PHY_STAT_REG    0x10/*!< PHY Status Register  */
-#define DP8_PHY_INT_CTL_REG 0x11/*!< PHY Interrupt Control Register */
-#define DP8_PHY_RBR_REG     0x17/*!< PHY RMII and Bypass Register  */
-#define DP8_PHY_STS_REG     0x19/*!< PHY Status Register  */
-
-/* DP83848 Control register definitions */
-#define DP8_RESET          (1 << 15)	/*!< 1= S/W Reset */
-#define DP8_LOOPBACK       (1 << 14)	/*!< 1=loopback Enabled */
-#define DP8_SPEED_SELECT   (1 << 13)	/*!< 1=Select 100MBps */
-#define DP8_AUTONEG        (1 << 12)	/*!< 1=Enable auto-negotiation */
-#define DP8_POWER_DOWN     (1 << 11)	/*!< 1=Power down PHY */
-#define DP8_ISOLATE        (1 << 10)	/*!< 1=Isolate PHY */
-#define DP8_RESTART_AUTONEG (1 << 9)	/*!< 1=Restart auto-negoatiation */
-#define DP8_DUPLEX_MODE    (1 << 8)		/*!< 1=Full duplex mode */
-#define DP8_COLLISION_TEST (1 << 7)		/*!< 1=Perform collsion test */
-
-/* DP83848 Status register definitions */
-#define DP8_100BASE_T4     (1 << 15)	/*!< T4 mode */
-#define DP8_100BASE_TX_FD  (1 << 14)	/*!< 100MBps full duplex */
-#define DP8_100BASE_TX_HD  (1 << 13)	/*!< 100MBps half duplex */
-#define DP8_10BASE_T_FD    (1 << 12)	/*!< 100Bps full duplex */
-#define DP8_10BASE_T_HD    (1 << 11)	/*!< 10MBps half duplex */
-#define DP8_MF_PREAMB_SUPPR (1 << 6)	/*!< Preamble suppress */
-#define DP8_AUTONEG_COMP   (1 << 5)		/*!< Auto-negotation complete */
-#define DP8_RMT_FAULT      (1 << 4)		/*!< Fault */
-#define DP8_AUTONEG_ABILITY (1 << 3)	/*!< Auto-negotation supported */
-#define DP8_LINK_STATUS    (1 << 2)		/*!< 1=Link active */
-#define DP8_JABBER_DETECT  (1 << 1)		/*!< Jabber detect */
-#define DP8_EXTEND_CAPAB   (1 << 0)		/*!< Supports extended capabilities */
-
-/* DP83848 PHY RBR MII dode definitions */
-#define DP8_RBR_RMII_MODE  (1 << 5)		/*!< Use RMII mode */
-
-/* DP83848 PHY status definitions */
-#define DP8_REMOTEFAULT    (1 << 6)		/*!< Remote fault */
-#define DP8_FULLDUPLEX     (1 << 2)		/*!< 1=full duplex */
-#define DP8_SPEED10MBPS    (1 << 1)		/*!< 1=10MBps speed */
-#define DP8_VALID_LINK     (1 << 0)		/*!< 1=Link active */
-
-/* DP83848 PHY ID register definitions */
-#define DP8_PHYID1_OUI     0x2000		/*!< Expected PHY ID1 */
-#define DP8_PHYID2_OUI     0x5c90		/*!< Expected PHY ID2 */
-
-/* DP83848 PHY update flags */
-static uint32_t physts, olddphysts;
-
-/* PHY update counter for state machine */
-static int32_t phyustate;
-
-/* Pointer to delay function used for this driver */
-static p_msDelay_func_t pDelayMs;
-
-/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
-   true on success, or false on failure */
-static Status lpc_mii_write(uint8_t reg, uint16_t data)
-{
-	Status sts = ERROR;
-	int32_t mst = 250;
-
-	/* Write value for register */
-	Chip_ENET_Start_MII_Write(reg, data);
-
-	/* Wait for unbusy status */
-	while (mst > 0) {
-		if (Chip_ENET_Is_MII_Busy()) {
-			mst--;
-			pDelayMs(1);
-		}
-		else {
-			mst = 0;
-			sts = SUCCESS;
-		}
-	}
-
-	return sts;
-}
-
-/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
-   true on success, or false on failure */
-static Status lpc_mii_read(uint8_t reg, uint16_t *data)
-{
-	Status sts = ERROR;
-	int32_t mst = 250;
-
-	/* Start register read */
-	Chip_ENET_Start_MII_Read(reg);
-
-	/* Wait for unbusy status */
-	while (mst > 0) {
-		if (!Chip_ENET_Is_MII_Busy()) {
-			mst = 0;
-			*data = Chip_ENET_Read_MII_Data();
-			sts = SUCCESS;
-		}
-		else {
-			mst--;
-			pDelayMs(1);
-		}
-	}
-
-	return sts;
-}
-
-/* Update PHY status from passed value */
-static void lpc_update_phy_sts(uint16_t linksts)
-{
-	/* Update link active status */
-	if (linksts & DP8_VALID_LINK) {
-		physts |= PHY_LINK_CONNECTED;
-	}
-	else {
-		physts &= ~PHY_LINK_CONNECTED;
-	}
-
-	/* Full or half duplex */
-	if (linksts & DP8_FULLDUPLEX) {
-		physts |= PHY_LINK_FULLDUPLX;
-	}
-	else {
-		physts &= ~PHY_LINK_FULLDUPLX;
-	}
-
-	/* Configure 100MBit/10MBit mode. */
-	if (linksts & DP8_SPEED10MBPS) {
-		physts &= ~PHY_LINK_SPEED100;
-	}
-	else {
-		physts |= PHY_LINK_SPEED100;
-	}
-
-	/* If the status has changed, indicate via change flag */
-	if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
-		(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
-		olddphysts = physts;
-		physts |= PHY_LINK_CHANGED;
-	}
-}
-
-/* Initialize the DP83848 PHY */
-uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
-{
-	uint16_t tmp;
-	int32_t i;
-
-	pDelayMs = pDelayMsFunc;
-
-	/* Initial states for PHY status and state machine */
-	olddphysts = physts = phyustate = 0;
-
-	/* Only first read and write are checked for failure */
-	/* Put the DP83848C in reset mode and wait for completion */
-	if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != SUCCESS) {
-		return ERROR;
-	}
-	i = 400;
-	while (i > 0) {
-		pDelayMs(1);
-		if (lpc_mii_read(DP8_BMCR_REG, &tmp) != SUCCESS) {
-			return ERROR;
-		}
-
-		if (!(tmp & (DP8_RESET | DP8_POWER_DOWN))) {
-			i = -1;
-		}
-		else {
-			i--;
-		}
-	}
-	/* Timeout? */
-	if (i == 0) {
-		return ERROR;
-	}
-
-#if 0
-	/* Setup link based on configuration options */
-#if PHY_USE_AUTONEG == 1
-	tmp = DP8_AUTONEG;
-#else
-	tmp = 0;
-#endif
-#if PHY_USE_100MBS == 1
-	tmp |= DP8_SPEED_SELECT;
-#endif
-#if PHY_USE_FULL_DUPLEX == 1
-	tmp |= DP8_DUPLEX_MODE;
-#endif
-
-#else
-	tmp = DP8_AUTONEG;
-#endif
-
-	lpc_mii_write(DP8_BMCR_REG, tmp);
-
-	/* Enable RMII mode for PHY */
-	if (rmii) {
-		lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
-	}
-
-	/* The link is not set active at this point, but will be detected
-	   later */
-
-	return SUCCESS;
-}
-
-/* Phy status update state machine */
-uint32_t lpcPHYStsPoll(void)
-{
-	switch (phyustate) {
-	default:
-	case 0:
-		/* Read BMSR to clear faults */
-		Chip_ENET_Start_MII_Read(DP8_PHY_STAT_REG);
-		physts &= ~PHY_LINK_CHANGED;
-		physts = physts | PHY_LINK_BUSY;
-		phyustate = 1;
-		break;
-
-	case 1:
-		/* Wait for read status state */
-		if (!Chip_ENET_Is_MII_Busy()) {
-			/* Update PHY status */
-			physts &= ~PHY_LINK_BUSY;
-			lpc_update_phy_sts(Chip_ENET_Read_MII_Data());
-			phyustate = 0;
-		}
-		break;
-	}
-
-	return physts;
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c
deleted file mode 100644
index b329cf5740..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * @brief SMSC 87x0 simple PHY driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "chip.h"
-#include "lpc_phy.h"
-
-/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0
- * @ingroup BOARD_PHY
- * Various functions for controlling and monitoring the status of the
- * SMSC 87x0 PHY.
- * @{
- */
-
-/* LAN8720 PHY register offsets */
-#define LAN8_BCR_REG        0x0	/*!< Basic Control Register */
-#define LAN8_BSR_REG        0x1	/*!< Basic Status Reg */
-#define LAN8_PHYID1_REG     0x2	/*!< PHY ID 1 Reg  */
-#define LAN8_PHYID2_REG     0x3	/*!< PHY ID 2 Reg */
-#define LAN8_PHYSPLCTL_REG  0x1F/*!< PHY special control/status Reg */
-
-/* LAN8720 BCR register definitions */
-#define LAN8_RESET          (1 << 15)	/*!< 1= S/W Reset */
-#define LAN8_LOOPBACK       (1 << 14)	/*!< 1=loopback Enabled */
-#define LAN8_SPEED_SELECT   (1 << 13)	/*!< 1=Select 100MBps */
-#define LAN8_AUTONEG        (1 << 12)	/*!< 1=Enable auto-negotiation */
-#define LAN8_POWER_DOWN     (1 << 11)	/*!< 1=Power down PHY */
-#define LAN8_ISOLATE        (1 << 10)	/*!< 1=Isolate PHY */
-#define LAN8_RESTART_AUTONEG (1 << 9)	/*!< 1=Restart auto-negoatiation */
-#define LAN8_DUPLEX_MODE    (1 << 8)	/*!< 1=Full duplex mode */
-
-/* LAN8720 BSR register definitions */
-#define LAN8_100BASE_T4     (1 << 15)	/*!< T4 mode */
-#define LAN8_100BASE_TX_FD  (1 << 14)	/*!< 100MBps full duplex */
-#define LAN8_100BASE_TX_HD  (1 << 13)	/*!< 100MBps half duplex */
-#define LAN8_10BASE_T_FD    (1 << 12)	/*!< 100Bps full duplex */
-#define LAN8_10BASE_T_HD    (1 << 11)	/*!< 10MBps half duplex */
-#define LAN8_AUTONEG_COMP   (1 << 5)	/*!< Auto-negotation complete */
-#define LAN8_RMT_FAULT      (1 << 4)	/*!< Fault */
-#define LAN8_AUTONEG_ABILITY (1 << 3)	/*!< Auto-negotation supported */
-#define LAN8_LINK_STATUS    (1 << 2)	/*!< 1=Link active */
-#define LAN8_JABBER_DETECT  (1 << 1)	/*!< Jabber detect */
-#define LAN8_EXTEND_CAPAB   (1 << 0)	/*!< Supports extended capabilities */
-
-/* LAN8720 PHYSPLCTL status definitions */
-#define LAN8_SPEEDMASK      (7 << 2)	/*!< Speed and duplex mask */
-#define LAN8_SPEED100F      (6 << 2)	/*!< 100BT full duplex */
-#define LAN8_SPEED10F       (5 << 2)	/*!< 10BT full duplex */
-#define LAN8_SPEED100H      (2 << 2)	/*!< 100BT half duplex */
-#define LAN8_SPEED10H       (1 << 2)	/*!< 10BT half duplex */
-
-/* LAN8720 PHY ID 1/2 register definitions */
-#define LAN8_PHYID1_OUI     0x0007		/*!< Expected PHY ID1 */
-#define LAN8_PHYID2_OUI     0xC0F0		/*!< Expected PHY ID2, except last 4 bits */
-
-/* DP83848 PHY update flags */
-static uint32_t physts, olddphysts;
-
-/* PHY update counter for state machine */
-static int32_t phyustate;
-
-/* Pointer to delay function used for this driver */
-static p_msDelay_func_t pDelayMs;
-
-/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
-   true on success, or false on failure */
-static Status lpc_mii_write(uint8_t reg, uint16_t data)
-{
-	Status sts = ERROR;
-	int32_t mst = 250;
-
-	/* Write value for register */
-	Chip_ENET_Start_MII_Write(reg, data);
-
-	/* Wait for unbusy status */
-	while (mst > 0) {
-		if (Chip_ENET_Is_MII_Busy()) {
-			mst--;
-			pDelayMs(1);
-		}
-		else {
-			mst = 0;
-			sts = SUCCESS;
-		}
-	}
-
-	return sts;
-}
-
-/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
-   true on success, or false on failure */
-static Status lpc_mii_read(uint8_t reg, uint16_t *data)
-{
-	Status sts = ERROR;
-	int32_t mst = 250;
-
-	/* Start register read */
-	Chip_ENET_Start_MII_Read(reg);
-
-	/* Wait for unbusy status */
-	while (mst > 0) {
-		if (!Chip_ENET_Is_MII_Busy()) {
-			mst = 0;
-			*data = Chip_ENET_Read_MII_Data();
-			sts = SUCCESS;
-		}
-		else {
-			mst--;
-			pDelayMs(1);
-		}
-	}
-
-	return sts;
-}
-
-/* Update PHY status from passed value */
-static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts)
-{
-	/* Update link active status */
-	if (linksts & LAN8_LINK_STATUS) {
-		physts |= PHY_LINK_CONNECTED;
-	}
-	else {
-		physts &= ~PHY_LINK_CONNECTED;
-	}
-
-	switch (sdsts & LAN8_SPEEDMASK) {
-	case LAN8_SPEED100F:
-	default:
-		physts |= PHY_LINK_SPEED100;
-		physts |= PHY_LINK_FULLDUPLX;
-		break;
-
-	case LAN8_SPEED10F:
-		physts &= ~PHY_LINK_SPEED100;
-		physts |= PHY_LINK_FULLDUPLX;
-		break;
-
-	case LAN8_SPEED100H:
-		physts |= PHY_LINK_SPEED100;
-		physts &= ~PHY_LINK_FULLDUPLX;
-		break;
-
-	case LAN8_SPEED10H:
-		physts &= ~PHY_LINK_SPEED100;
-		physts &= ~PHY_LINK_FULLDUPLX;
-		break;
-	}
-
-	/* If the status has changed, indicate via change flag */
-	if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
-		(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
-		olddphysts = physts;
-		physts |= PHY_LINK_CHANGED;
-	}
-}
-
-/* Initialize the SMSC 87x0 PHY */
-uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
-{
-	uint16_t tmp;
-	int32_t i;
-
-	pDelayMs = pDelayMsFunc;
-
-	/* Initial states for PHY status and state machine */
-	olddphysts = physts = phyustate = 0;
-
-	/* Only first read and write are checked for failure */
-	/* Put the DP83848C in reset mode and wait for completion */
-	if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) {
-		return ERROR;
-	}
-	i = 400;
-	while (i > 0) {
-		pDelayMs(1);
-		if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) {
-			return ERROR;
-		}
-
-		if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) {
-			i = -1;
-		}
-		else {
-			i--;
-		}
-	}
-	/* Timeout? */
-	if (i == 0) {
-		return ERROR;
-	}
-
-	/* Setup link */
-	lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG);
-
-	/* The link is not set active at this point, but will be detected
-	   later */
-
-	return SUCCESS;
-}
-
-/* Phy status update state machine */
-uint32_t lpcPHYStsPoll(void)
-{
-	static uint16_t sts;
-
-	switch (phyustate) {
-	default:
-	case 0:
-		/* Read BMSR to clear faults */
-		Chip_ENET_Start_MII_Read(LAN8_BSR_REG);
-		physts &= ~PHY_LINK_CHANGED;
-		physts = physts | PHY_LINK_BUSY;
-		phyustate = 1;
-		break;
-
-	case 1:
-		/* Wait for read status state */
-		if (!Chip_ENET_Is_MII_Busy()) {
-			/* Get PHY status with link state */
-			sts = Chip_ENET_Read_MII_Data();
-			Chip_ENET_Start_MII_Read(LAN8_PHYSPLCTL_REG);
-			phyustate = 2;
-		}
-		break;
-
-	case 2:
-		/* Wait for read status state */
-		if (!Chip_ENET_Is_MII_Busy()) {
-			/* Update PHY status */
-			physts &= ~PHY_LINK_BUSY;
-			smsc_update_phy_sts(sts, Chip_ENET_Read_MII_Data());
-			phyustate = 0;
-		}
-		break;
-	}
-
-	return physts;
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/retarget.c b/bsp/xplorer4330/libraries/lpc_board/board_common/retarget.c
deleted file mode 100644
index 1a796a7db1..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/board_common/retarget.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * @brief	IO redirection support
- *
- * This file adds re-direction support to the library for various
- * projects. It can be configured in one of 3 ways - no redirection,
- * redirection via a UART, or redirection via semihosting. If DEBUG
- * is not defined, all printf statements will do nothing with the
- * output being throw away. If DEBUG is defined, then the choice of
- * output is selected by the DEBUG_SEMIHOSTING define. If the
- * DEBUG_SEMIHOSTING is not defined, then output is redirected via
- * the UART. If DEBUG_SEMIHOSTING is defined, then output will be
- * attempted to be redirected via semihosting. If the UART method
- * is used, then the Board_UARTPutChar and Board_UARTGetChar
- * functions must be defined to be used by this driver and the UART
- * must already be initialized to the correct settings.
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "sys_config.h"
-#include "board.h"
-
-/* Keil (Realview) support */
-#if defined(__CC_ARM)
-
-#include <stdio.h>
-#include <rt_misc.h>
-
-#if defined(DEBUG)
-#if defined(DEBUG_SEMIHOSTING)
-#define ITM_Port8(n)    (*((volatile unsigned char *) (0xE0000000 + 4 * n)))
-#define ITM_Port16(n)   (*((volatile unsigned short *) (0xE0000000 + 4 * n)))
-#define ITM_Port32(n)   (*((volatile unsigned long *) (0xE0000000 + 4 * n)))
-
-#define DEMCR           (*((volatile unsigned long *) (0xE000EDFC)))
-#define TRCENA          0x01000000
-
-/* Write to SWO */
-void _ttywrch(int ch)
-{
-	if (DEMCR & TRCENA) {
-		while (ITM_Port32(0) == 0) {}
-		ITM_Port8(0) = ch;
-	}
-}
-
-#else
-static INLINE void BoardOutChar(char ch)
-{
-	Board_UARTPutChar(ch);
-}
-
-#endif /* defined(DEBUG_SEMIHOSTING) */
-#endif /* defined(DEBUG) */
-
-struct __FILE {
-	int handle;
-};
-
-FILE __stdout;
-FILE __stdin;
-FILE __stderr;
-
-void *_sys_open(const char *name, int openmode)
-{
-	return 0;
-}
-
-int fputc(int c, FILE *f)
-{
-#if defined(DEBUG)
-#if defined(DEBUG_SEMIHOSTING)
-	_ttywrch(c);
-#else
-	BoardOutChar((char) c);
-#endif
-#endif
-	return 0;
-}
-
-int fgetc(FILE *f)
-{
-#if defined(DEBUG) && !defined(DEBUG_SEMIHOSTING)
-	return Board_UARTGetChar();
-#else
-	return 0;
-#endif
-}
-
-int ferror(FILE *f)
-{
-	return EOF;
-}
-
-void _sys_exit(int return_code)
-{
-label:  goto label;	/* endless loop */
-}
-
-#endif /* defined (__CC_ARM) */
-
-/* IAR support */
-#if defined(__ICCARM__)
-/*******************
- *
- * Copyright 1998-2003 IAR Systems.  All rights reserved.
- *
- * $Revision: 30870 $
- *
- * This is a template implementation of the "__write" function used by
- * the standard library.  Replace it with a system-specific
- * implementation.
- *
- * The "__write" function should output "size" number of bytes from
- * "buffer" in some application-specific way.  It should return the
- * number of characters written, or _LLIO_ERROR on failure.
- *
- * If "buffer" is zero then __write should perform flushing of
- * internal buffers, if any.  In this case "handle" can be -1 to
- * indicate that all handles should be flushed.
- *
- * The template implementation below assumes that the application
- * provides the function "MyLowLevelPutchar".  It should return the
- * character written, or -1 on failure.
- *
- ********************/
-
-#include <yfuns.h>
-
-_STD_BEGIN
-
-#pragma module_name = "?__write"
-
-#if defined(DEBUG)
-#if defined(DEBUG_SEMIHOSTING)
-#error Semihosting support not yet working on IAR
-#endif /* defined(DEBUG_SEMIHOSTING) */
-#endif /* defined(DEBUG) */
-
-/*
-   If the __write implementation uses internal buffering, uncomment
-   the following line to ensure that we are called with "buffer" as 0
-   (i.e. flush) when the application terminates. */
-size_t __write(int handle, const unsigned char *buffer, size_t size)
-{
-#if defined(DEBUG)
-	size_t nChars = 0;
-
-	if (buffer == 0) {
-		/*
-		   This means that we should flush internal buffers.  Since we
-		   don't we just return.  (Remember, "handle" == -1 means that all
-		   handles should be flushed.)
-		 */
-		return 0;
-	}
-
-	/* This template only writes to "standard out" and "standard err",
-	   for all other file handles it returns failure. */
-	if (( handle != _LLIO_STDOUT) && ( handle != _LLIO_STDERR) ) {
-		return _LLIO_ERROR;
-	}
-
-	for ( /* Empty */; size != 0; --size) {
-		Board_UARTPutChar(*buffer++);
-		++nChars;
-	}
-
-	return nChars;
-#else
-	return size;
-#endif /* defined(DEBUG) */
-}
-
-_STD_END
-
-#endif /* defined (__ICCARM__) */
-
-#if defined( __GNUC__ )
-/* Include stdio.h to pull in __REDLIB_INTERFACE_VERSION__ */
-#include <stdio.h>
-
-#if (__REDLIB_INTERFACE_VERSION__ >= 20000)
-/* We are using new Redlib_v2 semihosting interface */
-	#define WRITEFUNC __sys_write
-	#define READFUNC __sys_readc
-#else
-/* We are using original Redlib semihosting interface */
-	#define WRITEFUNC __write
-	#define READFUNC __readc
-#endif
-
-#if defined(DEBUG)
-#if defined(DEBUG_SEMIHOSTING)
-/* Do nothing, semihosting is enabled by default in LPCXpresso */
-#endif /* defined(DEBUG_SEMIHOSTING) */
-#endif /* defined(DEBUG) */
-
-#if !defined(DEBUG_SEMIHOSTING)
-int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength)
-{
-#if defined(DEBUG)
-	unsigned int i;
-	for (i = 0; i < iLength; i++) {
-		Board_UARTPutChar(pcBuffer[i]);
-	}
-#endif
-
-	return iLength;
-}
-
-/* Called by bottom level of scanf routine within RedLib C library to read
-   a character. With the default semihosting stub, this would read the character
-   from the debugger console window (which acts as stdin). But this version reads
-   the character from the LPC1768/RDB1768 UART. */
-int READFUNC(void)
-{
-#if defined(DEBUG)
-	char c = Board_UARTGetChar();
-	return (int) c;
-
-#else
-	return (int) -1;
-#endif
-}
-
-#endif /* !defined(DEBUG_SEMIHOSTING) */
-#endif /* defined ( __GNUC__ ) */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox
deleted file mode 100644
index 8f54921c63..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * @brief LPCOpen 18xx/43xx board support page
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-/** @defgroup BOARDS_18XX_43XX BOARD: LPC18XX and LPC43XX boards
- * @ingroup Board_Layer
- * @{
- */
-
-/**
- * @}
- */
-
-/*!
- * @page LPCOPEN_BSP_18XX43XX Supported 18xx/43xx platforms
- *
- * <b>Device Support</b><br/>
- * All LPC18xx and LPC43xx device variants are supported.<br/><br/>
- * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=103">LPC18xx documentation links</a><br/>
- * <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=104">LPC43xx documentation links</a><br/><br/>
- * <b>Board Support</b><br/>
- * Hitex, Keil, and NGX boards for both 18xx and 43xx variants are supported.
- * Click <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco">here</a> for LPCOpen build procedures and default jumper configuration for supported boards.<br/><br/>
- * <a href="http://www.hitex.com/index.php?id=3455/">Hitex LPC1857 and LPC4357 evaluation boards </a><br/>
- * <a href="http://www.keil.com/mcb1800/">Keil MCB1800</a> and <a href="http://www.keil.com/mcb4300/">Keil MCB4300 boards</a><br/>
- * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC1830-Xplorer_Quick_Start_Guide">NGX LPC1830 Xplorer</a> and 
- * <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC4330-Xplorer_Quick_Start_Guide">NGX LPC4330 Xplorer boards</a><br/>
- *
- * <b>Toolchain Support</b><br/>
- * Code Red Xpresso, IAR EWARM, and Keil MDK are all supported. See the <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco#Supported_toolchains">build support pages</a>
- * for information on specific versions of the toolchains tested with the LPCOpen platform.<br/><br/>
- * <a href="http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/">IAR EWARM</a><br/>
- * <a href="http://www.keil.com/arm/mdk.asp">ARM MDK-ARM</a><br/>
- * <a href="http://code-red-tech.com/lpcxpresso">LPCXpresso</a>
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h
deleted file mode 100644
index 263a58d211..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * @brief Hitex EVA 1850/4350 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_H_
-#define __BOARD_H_
-
-#include "board_hitex_eva_18504350.h"
-
-#endif /* __BOARD_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c
deleted file mode 100644
index 53a83a51df..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c
+++ /dev/null
@@ -1,898 +0,0 @@
-/*
- * @brief Hitex EVA 1850/4350 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-#include "string.h"
-
-/* Include other sources files specific to this board */
-#include "lpc_phy_dp83848.c"
-#include "retarget.c"
-
-/** @ingroup BOARD_HITEX_EVA_18504350
- * @{
- */
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Port and bit mapping for LEDs on GPIOs */
-static const uint8_t ledports[] = {4, 7, 7, 7};
-static const uint8_t ledbits[] = {1, 5, 6, 8};
-
-/* TSC2046 control byte definitions */
-#define TSC_START                          (0x01 << 7)
-#define TSC_CHANNEL_X                      (0x05 << 4)		/* differential */
-#define TSC_CHANNEL_Y                      (0x01 << 4)		/* differential */
-#define TSC_CHANNEL_Z1                     (0x03 << 4)		/* differential */
-#define TSC_CHANNEL_Z2                     (0x04 << 4)		/* differential */
-#define TSC_8BIT                           (0x01 << 3)
-#define TSC_12BIT                          (0x00 << 3)
-#define TSC_PD                              0x00
-#define TSC_ADC_ON                          0x01
-#define TSC_REF_ON                          0x02
-#if (TSC2046_CONVERSION_BITS == 12)
-#define TSC_CONVERSION_MODE                 TSC_12BIT
-#else
-#define TSC_CONVERSION_MODE                 TSC_8BIT
-#endif
-
-#define TSC_SER_MODE                       (0x01 << 2)	/* Single-Ended Reference Mode */
-#define TSC_DFR_MODE                       (0x00 << 2)	/* Differential Reference Mode */
-
-#define X_MEASURE      (TSC_START | TSC_CHANNEL_X  | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
-#define Y_MEASURE      (TSC_START | TSC_CHANNEL_Y  | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
-#define Z1_MEASURE     (TSC_START | TSC_CHANNEL_Z1 | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
-#define Z2_MEASURE     (TSC_START | TSC_CHANNEL_Z2 | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON)
-#define PWRDOWN          (TSC_START | TSC_CHANNEL_Y  | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_PD)
-
-typedef struct {
-	int16_t ad_left;						/* left margin */
-	int16_t ad_right;						/* right margin */
-	int16_t ad_top;							/* top margin */
-	int16_t ad_bottom;						/* bottom margin */
-	int16_t lcd_width;						/* lcd horizontal size */
-	int16_t lcd_height;						/* lcd vertical size */
-	uint8_t swap_xy;						/* 1: swap x-y coords */
-} TSC2046_Init_Type;
-
-#define DC_CMD          (Chip_GPIO_WritePortBit(0x07, 8, false))
-#define DC_DATA         (Chip_GPIO_WritePortBit(0x07, 8, true))
-
-#define TSC2046_CONVERSION_BITS     12
-
-#if (TSC2046_CONVERSION_BITS == 12)
-#define TSC2046_COORD_MAX           (0xFFF)
-#define TSC2046_DELTA_VARIANCE      (0x50)
-#else
-#define TSC2046_COORD_MAX           (0xFF)
-#define TSC2046_DELTA_VARIANCE      (0x03)
-#endif
-#define COORD_GET_NUM                 (10)
-
-/** Local variables */
-static TSC2046_Init_Type TSC_Config = {
-	3686, 205, 3842, 267, 240, 320, 1
-};
-
-/**
- * LCD configuration data
- */
-const LCD_Config_Type EA320x240 = {
-	28,		/* Horizontal back porch in clocks */
-	10,		/* Horizontal front porch in clocks */
-	2,		/* HSYNC pulse width in clocks */
-	240,	/* Pixels per line */
-	2,		/* Vertical back porch in clocks */
-	1,		/* Vertical front porch in clocks */
-	2,		/* VSYNC pulse width in clocks */
-	320,	/* Lines per panel */
-	0,		/* Invert output enable, 1 = invert */
-	1,		/* Invert panel clock, 1 = invert */
-	1,		/* Invert HSYNC, 1 = invert */
-	1,		/* Invert VSYNC, 1 = invert */
-	1,		/* AC bias frequency in clocks (not used) */
-	6,		/* Maximum bits per pixel the display supports */
-	LCD_TFT,		/* LCD panel type */
-	LCD_COLOR_FORMAT_BGR,		/* BGR or RGB */
-	0		/* Dual panel, 1 = dual panel display */
-};
-
-/* UDA1380 Register Address */
-typedef enum {
-	UDA_EVALM_CLK = 0x00,
-	UDA_BUS_CTRL,
-	UDA_POWER_CTRL,
-	UDA_ANALOG_CTRL,
-	UDA_HPAMP_CTRL,
-	UDA_MASTER_VOL_CTRL = 0x10,
-	UDA_MIXER_VOL_CTRL,
-	UDA_MODE_CTRL,
-	UDA_MUTE_CTRL,
-	UDA_MIXER_FILTER_CTRL,
-	UDA_DEC_VOL_CTRL = 0x20,
-	UDA_PGA_CTRL,
-	UDA_ADC_CTRL,
-	UDA_AGC_CTRL,
-	UDA_TOTAL_REG
-} UDA1380_REG;
-
-#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
-#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
-
-#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE   (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
-#define UDA1380_REG_ANAMIX_DEFAULT_VALUE    0x0000
-#define UDA1380_REG_HEADAMP_DEFAULT_VALUE   ( 1 << 9 | 2)
-
-#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE   0x0000
-#define UDA1380_REG_MIXVOL_DEFAULT_VALUE    0x0000
-#define UDA1380_REG_MODEBBT_DEFAULT_VALUE   0x0000
-#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE  (2 << 8 | 2)
-#define UDA1380_REG_MIXSDO_DEFAULT_VALUE      0x0000
-
-#define UDA1380_REG_DECVOL_DEFAULT_VALUE     0xE4E4			/* Decrease Volume -28dB */
-#define UDA1380_REG_PGA_DEFAULT_VALUE         0x0000
-#define UDA1380_REG_ADC_DEFAULT_VALUE         0x0001		/* Apply 0bB VGA Gain, enable DC Filter */
-#define UDA1380_REG_AGC_DEFAULT_VALUE         0x0000
-
-#define UDA1380_REG_L3_DEFAULT_VALUE          0x0000
-
-/* System Register Data Set */
-static uint16_t UDA_sys_regs_dat[] = {
-	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
-	UDA1380_REG_I2S_DEFAULT_VALUE,
-	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
-	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
-	UDA1380_REG_HEADAMP_DEFAULT_VALUE
-};
-
-/* System Register Data Set */
-static uint16_t UDA_interfil_regs_dat[] = {
-	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
-	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
-	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
-	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
-	UDA1380_REG_MIXSDO_DEFAULT_VALUE
-};
-/* decimator Register Data Set */
-static uint16_t UDA_decimator_regs_dat[] = {
-	UDA1380_REG_DECVOL_DEFAULT_VALUE,
-	UDA1380_REG_PGA_DEFAULT_VALUE,
-	UDA1380_REG_ADC_DEFAULT_VALUE,
-	UDA1380_REG_AGC_DEFAULT_VALUE
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Very simple (inaccurate) delay function */
-static void DelayMs(uint32_t ms)
-{
-	uint32_t i;
-	for (i = 0; i < 100 * ms; i++) {}
-}
-
-/* Additional (SPI) pin configuration for LCD interface signals */
-static void lcdPinConfig(void)
-{
-	/* PC.11 connected to GPIO = SSEL_MUX_A, PC.12 connected to GPIO = SSEL_MUX_B */
-	Chip_SCU_PinMux(0xC, 11, MD_PLN, FUNC4);
-	Chip_SCU_PinMux(0xC, 12, MD_PLN, FUNC4);
-	Chip_GPIO_WriteDirBit(0x6, 10, true);
-	Chip_GPIO_WriteDirBit(0x6, 11, true);
-
-	/* Configure SSP0 pins */
-	/* PF.0 connected to SCL/SCLK */
-	Chip_SCU_PinMux(0xF, 0, MD_PLN_FAST, FUNC0);
-	/* PF.1 connected to nCS */
-	Chip_SCU_PinMux(0xF, 1, MD_PLN_FAST, FUNC2);
-	/* PF.2 connected to SO */
-	Chip_SCU_PinMux(0xF, 2, MD_PLN_FAST, FUNC2);
-	/* PF.3 connected to nSI */
-	Chip_SCU_PinMux(0xF, 3, MD_PLN_FAST, FUNC2);
-
-	/* DC PIN */
-	Chip_SCU_PinMux(0x0E, 8, MD_PUP, FUNC4);
-	Chip_GPIO_WriteDirBit(7, 8, true);
-}
-
-/* Write to a LCD register using SPI */
-static void writeToReg(uint16_t addr, uint16_t data)
-{
-	uint8_t buf[2];
-
-	Chip_GPIO_WritePortBit(0x06, 10, true);
-	Chip_GPIO_WritePortBit(0x06, 11, false);
-
-	DC_CMD;
-
-	buf[0] = 0;
-	buf[1] = (addr & 0xff);
-
-	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2);
-
-	DC_DATA;
-	buf[0] = (data >> 8);
-	buf[1] = (data & 0xff);
-	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2);
-
-	DC_CMD;
-
-	buf[0] = (0);
-	buf[1] = (0x22);
-	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2);
-}
-
-/* Initialize SSD1289 LCD Controller */
-static void ssd1289_init(void)
-{
-	writeToReg(0x00, 0x0001);
-	DelayMs(15);
-	writeToReg(0x03, 0x6E3E);	// 0xAEAC
-	writeToReg(0x0C, 0x0007);
-	writeToReg(0x0D, 0x000E);	// 0x000F
-	writeToReg(0x0E, 0x2C00);	// 0x2900
-	writeToReg(0x1E, 0x00AE);	// 0x00B3
-	DelayMs(15);
-	writeToReg(0x07, 0x0021);
-	DelayMs(50);
-	writeToReg(0x07, 0x0023);
-	DelayMs(50);
-	writeToReg(0x07, 0x0033);
-	DelayMs(50);
-
-	writeToReg(0x01, 0x2B3F);
-	writeToReg(0x02, 0x0600);
-	writeToReg(0x10, 0x0000);
-	DelayMs(15);
-	writeToReg(0x11, 0xC5B0);	// 0x65b0
-	DelayMs(20);
-	writeToReg(0x05, 0x0000);
-	writeToReg(0x06, 0x0000);
-	writeToReg(0x16, 0xEF1C);
-	writeToReg(0x17, 0x0003);
-	writeToReg(0x07, 0x0233);
-	writeToReg(0x0B, 0x5312);
-	writeToReg(0x0F, 0x0000);
-	writeToReg(0x25, 0xE000);
-	DelayMs(20);
-	writeToReg(0x41, 0x0000);
-	writeToReg(0x42, 0x0000);
-	writeToReg(0x48, 0x0000);
-	writeToReg(0x49, 0x013F);
-	writeToReg(0x44, 0xEF00);
-	writeToReg(0x45, 0x0000);
-	writeToReg(0x46, 0x013F);
-	writeToReg(0x4A, 0x0000);
-	writeToReg(0x4B, 0x0000);
-	DelayMs(20);
-	writeToReg(0x30, 0x0707);
-	writeToReg(0x31, 0x0704);
-	writeToReg(0x32, 0x0005);	// 0x0204
-	writeToReg(0x33, 0x0402);	// 0x0201
-	writeToReg(0x34, 0x0203);
-	writeToReg(0x35, 0x0204);
-	writeToReg(0x36, 0x0204);
-	writeToReg(0x37, 0x0401);	// 0x0502
-	writeToReg(0x3A, 0x0302);
-	writeToReg(0x3B, 0x0500);
-	DelayMs(20);
-	writeToReg(0x22, 0x0000);
-}
-
-/* Send/Receive data to/from TSC2046. */
-static void TSC2046_ReadWrite(uint8_t command, uint16_t *data)
-{
-	uint32_t tmp;
-	uint8_t rx_data[2], tx_data[1] = {0x00};
-
-	tx_data[0] = command;
-	Chip_GPIO_WritePortBit(6, 10, false);
-	Chip_GPIO_WritePortBit(6, 11, true);
-
-	Chip_GPIO_WritePortBit(7, 16, false);
-
-	for (tmp = 0x100; tmp; tmp--) {}
-
-	Chip_SSP_WriteFrames_Blocking(LPC_SSP0, tx_data, 1);
-	Chip_SSP_ReadFrames_Blocking(LPC_SSP0, rx_data, 2);
-
-	for (tmp = 0x100; tmp; tmp--) {}
-
-#if (TSC2046_CONVERSION_BITS == 8)
-	*data = (((rx_data[0] << 8) | (rx_data[1])) >> 7) & 0xFF;
-#else
-	*data = (((rx_data[0] << 8) | rx_data[1]) >> 3) & 0xFFF;
-#endif
-	Chip_GPIO_WritePortBit(7, 16, true);
-}
-
-/* Evaluate the coordinates received from TSC. */
-static Status EvalCoord(uint8_t command, uint16_t *coord)
-{
-	uint32_t i;
-	uint16_t Tmp = 0, previousTmp;
-	int16_t diff = 0;
-	*coord = 0;
-	for (i = 0; i < COORD_GET_NUM; i++) {
-		previousTmp = Tmp;
-		TSC2046_ReadWrite(command, &Tmp);
-		if (Tmp > TSC2046_COORD_MAX) {
-			return ERROR;
-		}
-		if (i > 0) {
-			diff = Tmp - previousTmp;
-		}
-		if (diff < 0) {
-			diff = 0 - diff;
-		}
-		if (diff > TSC2046_DELTA_VARIANCE) {
-			return ERROR;
-		}
-		*coord += Tmp;
-	}
-	*coord /= COORD_GET_NUM;
-	return SUCCESS;
-}
-
-/* Convert the coord received from TSC to a value on truly LCD */
-static int16_t TSCCalibrate(int16_t Coord, int16_t MinVal, int16_t MaxVal, int16_t TrueSize)
-{
-	int16_t tmp;
-	int16_t ret;
-	uint8_t convert = 0;
-
-	/* Swap value? */
-	if (MinVal > MaxVal) {
-		tmp = MaxVal;
-		MaxVal = MinVal;
-		MinVal = tmp;
-		convert = 1;
-	}
-
-	ret = (Coord - MinVal) * TrueSize / (MaxVal - MinVal);
-	if (convert) {
-		ret = TrueSize - ret;
-	}
-
-	return ret;
-}
-
-static void delay(uint32_t i) {
-	while (i--) {}
-}
-
-/* Write value to a UDA1380 register */
-static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
-
-	I2C_Config->tx_data[0] = reg;
-	I2C_Config->tx_data[1] = value >> 8;
-	I2C_Config->tx_data[2] = value & 0xFF;
-	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
-	delay(10000);
-}
-
-/* Read value from a UDA1380 register */
-static uint16_t UDA_Reg_read(UDA1380_REG reg) {
-	uint8_t rx_data[2];
-	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
-	return rx_data[0] << 8 | rx_data[1];
-}
-
-/* Initialize UDA1380 CODEC */
-static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
-{
-	uint16_t temp;
-	uint8_t  i;
-	/* Reset UDA1380 on board Hitex A4*/
-	/* PE_9: UDA_RST on Hitex A4 */
-	Chip_SCU_PinMux(0x0E, 9, MD_PUP, FUNC4);
-	Chip_GPIO_WriteDirBit(7, 9, true);
-	Chip_GPIO_WritePortBit(7, 9, true);
-	/* delay 1us */
-	delay(100000);
-	Chip_GPIO_WritePortBit(7, 9, false);
-	delay(100000);
-	for (i = 0; i < 5; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
-		if (temp != UDA_sys_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-
-	/* interfilter regs init */
-	for (i = 0; i < 5; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
-		if (temp != UDA_interfil_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-	/* decimator regs init */
-	for (i = 0; i < 4; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
-		if (temp != UDA_decimator_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-
-	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
-		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
-		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
-		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
-			return ERROR;
-		}
-		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
-					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
-					  I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
-		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
-			return ERROR;
-		}
-	}
-	return SUCCESS;
-
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize pin muxing for a UART */
-void Board_UART_Init(LPC_USART_Type *UARTx)
-{
-	if (UARTx == LPC_USART0) {
-		Chip_SCU_PinMux(0xF, 10, MD_PDN, FUNC1);	/* PF.10 : UART0_TXD */
-		Chip_SCU_PinMux(0xF, 11, MD_PLN | MD_EZI | MD_ZI, FUNC1);	/* PF.11 : UART0_RXD */
-	}
-	else if (UARTx == LPC_UART1) {
-		Chip_SCU_PinMux(0xC, 13, MD_PDN, FUNC2);	/* PC.13 : UART1_TXD - pin 1 of SV14 */
-		Chip_SCU_PinMux(0xC, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* PC.14 : UART1_RX - pin 2 of SV14 */
-	}
-	else if (UARTx == LPC_USART2) {
-		/* P1.15 : UART2_TXD - pin 11 of SV6, P1.16 : UART2_RXD - pin 3 of SV6 */
-		Chip_SCU_PinMux(0x1, 15, MD_PDN, FUNC1);
-		Chip_SCU_PinMux(0x1, 16, MD_PLN | MD_EZI | MD_ZI, FUNC1);
-	}
-	else if (UARTx == LPC_USART3) {
-		/* P9.3 : UART3_TXD - pin 15 of SV6, P9.4 : UART3_RXD - pin 7 of SV3 */
-		Chip_SCU_PinMux(0x9, 3, MD_PDN, FUNC7);
-		Chip_SCU_PinMux(0x9, 4, MD_PLN | MD_EZI | MD_ZI, FUNC7);
-	}
-}
-
-/* Initialize debug output via UART for board */
-void Board_Debug_Init(void)
-{
-#if defined(DEBUG_UART)
-	Board_UART_Init(DEBUG_UART);
-
-	Chip_UART_Init(DEBUG_UART);
-	Chip_UART_SetBaud(DEBUG_UART, 115200);
-	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
-
-	/* Enable UART Transmit */
-	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
-#endif
-}
-
-/* Sends a character on the UART */
-void Board_UARTPutChar(char ch)
-{
-#if defined(DEBUG_UART)
-	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
-#endif
-}
-
-/* Gets a character from the UART, returns EOF if no character is ready */
-int Board_UARTGetChar(void)
-{
-#if defined(DEBUG_UART)
-	uint8_t data;
-
-	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
-		return (int) data;
-	}
-#endif
-	return EOF;
-}
-
-/* Outputs a string on the debug UART */
-void Board_UARTPutSTR(char *str)
-{
-#if defined(DEBUG_UART)
-	while (*str != '\0') {
-		Board_UARTPutChar(*str++);
-	}
-#endif
-}
-
-/* Initializes board LED(s) */
-void Board_LED_Init()
-{
-	int i;
-
-	/* Set ports as outputs with initial states off */
-	for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) {
-		Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true);
-		Chip_GPIO_WritePortBit(ledports[i], ledbits[i], true);
-	}
-	Chip_GPIO_WritePortBit(ledports[0], ledbits[0], false);
-}
-
-/* Sets the state of a board LED to on or off */
-void Board_LED_Set(uint8_t LEDNumber, bool On)
-{
-	/* Must connect JP3 to see LED0 and JP4 to see LED1 */
-	if (LEDNumber == 0) {
-		On = !On;
-	}
-
-	if (LEDNumber < 4) {
-		Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], !On);
-	}
-}
-
-/* Returns the current state of a board LED */
-bool Board_LED_Test(uint8_t LEDNumber)
-{
-	bool On = false;
-
-	if (LEDNumber < 4) {
-		On = (bool) !Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]);
-
-		if (LEDNumber == 0) {
-			On = ~On;
-		}
-	}
-
-	return On;
-}
-
-/* Initialize button(s) interface on board */
-void Board_Buttons_Init(void)	// FIXME not functional ATM
-{
-	Chip_SCU_PinMux(0xD, 7, MD_PUP | MD_EZI, FUNC4);			// GPIO6[21]
-	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false);	// input
-}
-
-/* Returns button(s) state on board */
-uint32_t Buttons_GetStatus(void)
-{
-	uint8_t ret = NO_BUTTON_PRESSED;
-	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
-		ret |= BUTTONS_BUTTON1;
-	}
-	return ret;
-}
-
-/* Initialize joystick interface on board */
-void Board_Joystick_Init(void)
-{}
-
-/* Returns joystick states on board */
-uint8_t Joystick_GetStatus(void)
-{
-	return NO_BUTTON_PRESSED;
-}
-
-/**
- * System Clock Frequency (Core Clock)
- */
-uint32_t SystemCoreClock;
-
-/* Update system core clock rate, should be called if the system has
-   a clock rate change */
-void SystemCoreClockUpdate(void)
-{
-	/* CPU core speed */
-	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
-}
-
-/* Returns the MAC address assigned to this board */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr)
-{
-	const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
-
-	memcpy(mcaddr, boardmac, 6);
-}
-
-/* Set up and initialize all required blocks and functions related to the
-   board hardware */
-void Board_Init(void)
-{
-	/* Sets up DEBUG UART */
-	DEBUGINIT();
-
-	/* Updates SystemCoreClock global var with current clock speed */
-	SystemCoreClockUpdate();
-
-	/* Initializes GPIO */
-	Chip_GPIO_Init();
-
-	/* Setup GPIOs for USB demos */
-#if 0 /* FIXME: the following call removed on the Hitex board as it interferes with muxed MII state */
-	//	Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2);			// P9_5 USB1_VBUS_EN, USB1 VBus function
-#endif
-	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	// P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
-	Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1);			// P6_3 USB0_PWR_EN, USB0 VBus function
-}
-
-/* Sets up board specific ADC interface */
-void Board_ADC_Init(void)
-{
-	/* Analog function ADC1_2 selected on pin PF_9 */
-	Chip_SCU_ADC_Channel_Config(1, 2);
-}
-
-/* Sets up board specific I2C interface */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx)
-{
-	if (I2Cx == LPC_I2C1) {
-		/* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */
-		Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2);
-		Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2);
-	}
-}
-
-/* Initialize the LCD interface */
-void Board_LCD_Init(void)
-{
-	SSP_ConfigFormat ssp_format1;
-	/* Attach main PLL clock to divider A with a divider of 2 */
-	Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2);
-
-	/* Route divider A output to LCD base clock and enable base clock */
-	Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false);
-
-	/* Reset LCD and wait for reset to complete */
-	Chip_RGU_TriggerReset(RGU_LCD_RST);
-	while (Chip_RGU_InReset(RGU_LCD_RST)) {}
-
-	lcdPinConfig();
-	Chip_Clock_Enable(CLK_MX_SSP0);
-	Chip_SSP_Init(LPC_SSP0);
-	Chip_SSP_Set_Master(LPC_SSP0, true);
-	Chip_SSP_Set_BitRate(LPC_SSP0, 1000000);
-
-	ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
-	ssp_format1.bits = SSP_BITS_8;
-	ssp_format1.clockFormat = SSP_CLOCK_MODE0;
-
-	Chip_SSP_Set_Format(LPC_SSP0, &ssp_format1);
-	Chip_SSP_Cmd(LPC_SSP0, ENABLE);
-
-	DelayMs(200);
-
-	/* initialize LCD controller */
-	ssd1289_init();
-
-	Chip_SSP_Cmd(LPC_SSP0, DISABLE);
-	Chip_SSP_DeInit(LPC_SSP0);
-}
-
-/* Initialize TSC2046 touchscreen controller */
-void Init_Touch_Controller(void)
-{
-	uint16_t dummy_data;
-	SSP_ConfigFormat ssp_format1;
-
-	/* Configure SSP0 pins*/
-	lcdPinConfig();
-	Chip_SCU_PinMux(0xF, 1, MD_PUP, FUNC4);
-
-	Chip_GPIO_WriteDirBit(7, 16, true);
-
-	Chip_GPIO_WritePortBit(6, 10, false);
-	Chip_GPIO_WritePortBit(6, 11, true);
-
-	Chip_SSP_Init(LPC_SSP0);
-
-	Chip_SSP_Set_Master(LPC_SSP0, true);
-	Chip_SSP_Set_BitRate(LPC_SSP0, 200000);
-
-	ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
-	ssp_format1.bits = SSP_BITS_8;
-	ssp_format1.clockFormat = SSP_CLOCK_MODE0;
-
-	Chip_SSP_Set_Format(LPC_SSP0, &ssp_format1);
-	Chip_SSP_Cmd(LPC_SSP0, ENABLE);
-
-	/* Enable Touch Screen Controller */
-	TSC2046_ReadWrite(PWRDOWN, &dummy_data);
-}
-
-/* Get Touch coordinates */
-bool GetTouchPos(int16_t *pX, int16_t *pY)
-{
-	uint16_t tmp;
-	uint16_t x, y, z1, z2, z = 0;
-	Status Sts = SUCCESS;
-
-	TSC2046_ReadWrite(X_MEASURE, &x);
-	TSC2046_ReadWrite(Y_MEASURE, &y);
-	TSC2046_ReadWrite(Z1_MEASURE, &z1);
-	TSC2046_ReadWrite(Z2_MEASURE, &z2);
-
-	if (z1 != 0) {
-		z = x * ((z2 / z1) - 1);
-	}
-	if ((z <= 0) || (z > 35000)) {
-		return false;
-	}
-	/* Get X-Coordinate */
-	Sts = EvalCoord(X_MEASURE, &x);
-
-	if (Sts == ERROR) {
-		return false;
-	}
-	/* Get Y-Coordinate */
-	Sts = EvalCoord(Y_MEASURE, &y);
-	if (Sts == ERROR) {
-		return false;
-	}
-	/* Get Z1-Value */
-	Sts = EvalCoord(Z1_MEASURE, &z1);
-	if (Sts == ERROR) {
-		return false;
-	}
-	/* Get Z2-Value */
-	Sts = EvalCoord(Z2_MEASURE, &z2);
-	if (Sts == ERROR) {
-		return false;
-	}
-
-	z = x * ((z2 / z1) - 1);
-	if ((z <= 0) || (z > 35000)) {
-		return false;
-	}
-	else {
-		/* Swap, adjust to truly size of LCD */
-		if (TSC_Config.swap_xy) {
-			*pY = TSCCalibrate(x, TSC_Config.ad_top, TSC_Config.ad_bottom, TSC_Config.lcd_height);
-			*pX = TSCCalibrate(y, TSC_Config.ad_left, TSC_Config.ad_right, TSC_Config.lcd_width);
-		}
-		else {
-			*pX = TSCCalibrate(x, TSC_Config.ad_top, TSC_Config.ad_bottom, TSC_Config.lcd_width);
-			*pY = TSCCalibrate(y, TSC_Config.ad_left, TSC_Config.ad_right, TSC_Config.lcd_height);
-		}
-	}
-	TSC2046_ReadWrite(PWRDOWN, &tmp);
-
-	return true;
-}
-
-/* Turn on Board LCD Backlight */
-void Board_LCD_Set_Backlight(uint8_t Intensity)
-{
-	bool OnOff = (bool) (Intensity != 0);
-
-	Chip_GPIO_WritePortBit(3, 8, OnOff);
-}
-
-/* Initialize pin muxing for SDMMC interface */
-void Board_SDMMC_Init(void)
-{
-	Chip_SCU_PinMux(0xc, 9, MD_PLN, FUNC7);				/* Pc.9 SDIO power */
-	Chip_SCU_PinMux(0xc, 2, MD_PLN, FUNC7);				/* Pc.2 SDIO LED */
-	Chip_SCU_PinMux(0xf, 10, MD_PLN | MD_EZI, FUNC6);	/* Pf.10 SDIO WP */
-	Chip_SCU_PinMux(0xc, 8, MD_PLN | MD_EZI, FUNC7);	/* Pc.8 SDIO CD */
-	Chip_SCU_PinMux(0xc, 6, MD_PLN_FAST, FUNC7);		/* Pc.6 SDIO D2 */
-	Chip_SCU_PinMux(0xc, 5, MD_PLN_FAST, FUNC7);		/* Pc.5 SDIO D1 */
-	Chip_SCU_PinMux(0xc, 4, MD_PLN_FAST, FUNC7);		/* Pc.4 SDIO D0 */
-	Chip_SCU_PinMux(0xc, 0, MD_PLN | MD_EHS, FUNC7);	/* Pc.0 SDIO clock */
-	Chip_SCU_PinMux(0xc, 10, MD_PLN_FAST, FUNC7);		/* Pc.10 SDIO command */
-	Chip_SCU_PinMux(0xc, 7, MD_PLN_FAST, FUNC7);		/* Pc.7 SDIO D3 */
-}
-
-/* Initialize pin muxing for SSP interface */
-void Board_SSP_Init(LPC_SSP_Type *SSPx)
-{
-	if (SSPx == LPC_SSP0) {
-		/* Set up clock and muxing for SSP0 interface */
-		// #if !defined(HITEX_LCD_TERM)
-		/* PC.11 connected to GPIO = SSEL_MUX_A, PC.12 connected to GPIO = SSEL_MUX_B */
-		Chip_SCU_PinMux(0xC, 11, MD_PLN, FUNC4);
-		Chip_SCU_PinMux(0xC, 12, MD_PLN, FUNC4);
-		Chip_GPIO_WriteDirBit(0x6, 10, true);
-		Chip_GPIO_WriteDirBit(0x6, 11, true);
-		// #endif
-		/* PF.0 connected to SCL/SCLK	func2=SSP0 SCK0 */
-		Chip_SCU_PinMux(0xF, 0, MD_PLN_FAST, FUNC0);
-		/* PF.1 connected to nCS		func2=SSP0 SSEL0 */
-		Chip_SCU_PinMux(0xF, 1, MD_PLN_FAST, FUNC2);
-		/* PF.2 connected to SO			func2=SSP0 MISO0 */
-		Chip_SCU_PinMux(0xF, 2, MD_PLN | MD_EZI | MD_ZI, FUNC2);
-		/* PF.3 connected to nSI		func2=SSP0 MOSI0 */
-		Chip_SCU_PinMux(0xF, 3, MD_PLN | MD_EZI | MD_ZI, FUNC2);
-
-		Chip_Clock_Enable(CLK_MX_SSP0);
-	}
-	else if (SSPx == LPC_SSP1) {
-		/* Set up clock and muxing for SSP1 interface */
-		/* P1.19 connected to SCL/SCLK	func1=SSP1 SCK1 */
-		Chip_SCU_PinMux(0x1, 19, MD_PLN_FAST, FUNC1);
-		/* P1.20 connected to nCS		func1=SSP1 SSEL1 */
-		Chip_SCU_PinMux(0x1, 20, MD_PLN_FAST, FUNC1);
-		/* P0.0 connected to SO			func1=SSP1 MISO1 */
-		Chip_SCU_PinMux(0x0, 0, MD_PLN | MD_EZI | MD_ZI, FUNC1);
-		/* P0.1 connected to nSI		func2=SSP1 MOSI1 */
-		Chip_SCU_PinMux(0x0, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1);
-
-		Chip_Clock_Enable(CLK_MX_SSP1);
-	}
-}
-
-/* Initialize I2S interface for the board and UDA1380 */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
-{
-	uint8_t uda1380_tx_data_buf[3];
-	Chip_I2S_Audio_Format_Type I2S_Config;
-	I2C_M_SETUP_Type I2C_Config;
-	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
-	I2C_Config.retransmissions_max = 5;
-	I2C_Config.tx_length = 3;
-	I2C_Config.tx_data = uda1380_tx_data_buf;
-	I2C_Config.rx_length = 0;
-	I2C_Config.rx_data = NULL;
-
-	/* Initialize I2C to the UDA1380 CODEC */
-	Chip_I2C_Init(LPC_I2C0);
-	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
-	I2S_Config.SampleRate = 48000;
-	I2S_Config.ChannelNumber = 2;	// 1 is mono, 2 is stereo
-	I2S_Config.WordWidth =  16;	// 8, 16 or 32 bits
-	Chip_I2S_Init(LPC_I2S0);
-	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
-	/* Enable Slave I2C operation */
-	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
-	/* Init UDA1380 CODEC */
-	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
-}
-
-/* FIXME */
-void Serial_CreateStream(void *Stream)
-{
-	// implement later
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h
deleted file mode 100644
index 9a0f83814f..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * @brief Hitex EVA 1850/4350 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_HITEX_EVA_18504350_H_
-#define __BOARD_HITEX_EVA_18504350_H_
-
-#include "chip.h"
-#include "board_api.h"
-#include "lpc_phy.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_HITEX_EVA_18504350 LPC1850 and LPC4350 Hitex EVA board support functions
- * @ingroup BOARDS_18XX_43XX
- * @{
- */
-
-/** @defgroup BOARD_HITEX_EVA_18504350_OPTIONS BOARD: LPC1850 and LPC4350 Hitex EVA board builds options
- * The NGX board has options that configure it's operation at build-time.<br/>
- * CHIP_LPC*
- *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
- * DEBUG:<br/>
- * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
- * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
- * DEBUG_UART:<br/>
- *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
- * CRYSTAL_MAIN_FREQ_IN:<br/>
- *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
- * CRYSTAL_32K_FREQ_IN:<br/>
- *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
- * EXTERNAL_CLKIN_FREQ_IN:<br/>
- *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
- * MAX_CLOCK_FREQ:<br/>
- *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
- *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
- * USE_RMII:<br/>
- *  - When defined, the system will be configured for RMII mode for Ethernet<br/>
- *  - When not defined, the system will be configured for MII mode for Ethernet<br/><p>
- * BOARD_HITEX_EVA_18504350:<br/>
- *  - When building for Hitex boards, BOARD_HITEX_EVA_18504350 is defined<br/>
- * <br/><p>
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * HITEX board defintion, can be used in examples for board specific code
- */
-#define BOARD_HITEX_EVA_18504350
-
-/* For USBLIB examples */
-#define LEDS_LED1           0x01
-#define LEDS_LED2           0x02
-#define LEDS_LED3           0x04
-#define LEDS_LED4           0x08
-#define LEDS_NO_LEDS        0x00
-#define BUTTONS_BUTTON1     0x01
-#define JOY_UP              0x01
-#define JOY_DOWN            0x02
-#define JOY_LEFT            0x04
-#define JOY_RIGHT           0x08
-#define JOY_PRESS           0x10
-#define NO_BUTTON_PRESSED   0x00
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM   6
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM    21
-
-#define I2CDEV_PCA9502_ADDR     (0x9A >> 1)
-#define PCA9502_REG_IODIR       0x0A
-#define PCA9502_REG_IOSTATE     0x0B
-#define PCA9502_REG_IOINTENA    0x0C
-#define PCA9502_REG_IOCONTROL   0x0E
-#define PCA9502_REG_ADDR(x)     (((x) & 0x0F) << 3)
-
-/**
- * Address of I2C device (UDA1380 CODEC) on board
- */
-#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
-
-/**
- * Default location of LCD buffer is in DRAM
- */
-#define FRAMEBUFFER_ADDR        0x28000000
-
-/**
- * LCD configuration data
- */
-extern const LCD_Config_Type EA320x240;
-
-/**
- * Default LCD configuration data for examples
- */
-#define BOARD_LCD EA320x240
-
-/**
- * CODEC audio input sources
- */
-typedef enum {
-	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
-	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
-} Board_Audio_Input_Sel_Type;
-
-/**
- * @brief	Initialize pin muxing for a UART
- * @param	UARTx	: Pointer to UART register block for UART pins to init
- * @return	Nothing
- */
-void Board_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief	Initialize button(s) interface on board
- * @return	Nothing
- */
-void Board_Buttons_Init(void);
-
-/**
- * @brief	Returns button(s) state on board
- * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus(void);
-
-/**
- * @brief	Initialize joystick interface on board
- * @return	Nothing
- */
-void Board_Joystick_Init(void);
-
-/**
- * @brief	Returns joystick states on board
- * @return	Returns a JOY_* value, ir JOY_PRESS or JOY_UP
- */
-uint8_t Joystick_GetStatus(void);
-
-/**
- * @brief	Returns the MAC address assigned to this board
- * @param	mcaddr : Pointer to 6-byte character array to populate with MAC address
- * @return	Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief	Sets up board specific ADC interface
- * @return	Nothing
- */
-void Board_ADC_Init(void);
-
-/**
- * @brief	Sets up board specific I2C interface
- * @param	I2Cx	: Pointer to I2C interface to initialize
- * @return	Nothing
- */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Initialize the LCD interface
- * @return	Nothing
- */
-void Board_LCD_Init(void);
-
-/**
- * @brief	Initialize TSC2046 touchscreen controller
- * @return	Nothing
- */
-void Init_Touch_Controller(void);
-
-/**
- * @brief	Get Touch coordinates
- * @param	pX	: Pointer to x-Coord to populate
- * @param	pY	: Pointer to y-Coord to populate
- * @return	Nothing
- */
-bool GetTouchPos(int16_t *pX, int16_t *pY);
-
-/**
- * @brief	Initialize pin muxing for SDMMC interface
- * @return	Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief	Initialize pin muxing for SSP interface
- * @param	SSPx	: Pointer to SSP interface to initialize
- * @return	Nothing
- */
-void Board_SSP_Init(LPC_SSP_Type *SSPx);
-
-/**
- * @brief	Initialize I2S interface for the board and UDA1380
- * @param	I2Sx			: Pointer to I2S register interface used on this board
- * @param	audio_in_sel	: Audio input selection
- * @return	Nothing
- */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
-
-/**
- * @brief	FIXME
- * @param	Stream	: FIXME
- * @return	Nothing
- */
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_HITEX_EVA_18504350_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h
deleted file mode 100644
index eb70ce6328..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-// #define USE_RMII
-#define CHIP_LPC18XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
-   via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h
deleted file mode 100644
index 543f956c83..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-// #define USE_RMII
-#define CHIP_LPC43XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
-   via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (204000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c
deleted file mode 100644
index 282fde8eb3..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_HITEX_EVA_18504350_SYSINIT LPC1850 and LPC4350 Hitex EVA board System Init code
- * @ingroup BOARD_HITEX_EVA_18504350
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the Hitex EVA boards includes clock setup, default pin muxing, and
- * memory configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1850 and LPC4350 Hitex EVA setup<BR>
- *  Clocking:<BR>
- *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
- *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
- *   SPIFI FLASH clock setup for fastest speed<BR>
- *  Pin muxing:<BR>
- *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
- *   Sets up the external memory controller signals<BR>
- *  Memory:<BR>
- *   Sets up DRAM, static RAM, and NOR FLASH.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
-	uint8_t pingrp;	/* Pin group */
-	uint8_t pinnum;	/* Pin number */
-	uint8_t pincfg;	/* Pin configuration for SCU */
-	uint8_t funcnum;/* Function number */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
-	CGU_BASE_CLK_T clk;	/* Base clock */
-	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
-	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
-	bool powerdn;		/* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
-	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
-	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
-#endif
-	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
-#endif
-	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
-	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
-	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
-	{CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
-	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
-	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
-	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
-	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
-	{0x3, 3,  (MD_PLN_FAST),  FUNC3},	/* SPIFI CLK */
-	{0x3, 4,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D3 */
-	{0x3, 5,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D2 */
-	{0x3, 6,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D1 */
-	{0x3, 7,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D0 */
-	{0x3, 8,  (MD_PLN_FAST),  FUNC3}	/* SPIFI CS/SSEL */
-};
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
-	int i;
-
-	/* Switch main system clocking to crystal */
-	Chip_Clock_EnableCrystal();
-	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
-	/* Setup PLL for 100MHz and switch main system clocking */
-	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
-	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
-	/* Setup PLL for maximum clock */
-	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
-	/* Setup system base clocks and initial states. This won't enable and
-	   disable individual clocks, but sets up the base clock sources for
-	   each individual peripheral clock. */
-	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
-		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
-								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
-	}
-
-	/* Reset and enable 32Khz oscillator */
-	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
-	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
-	/* SPIFI pin setup is done prior to setting up system clocking */
-	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
-		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
-						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
-	}
-
-	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
-	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
-#if defined(USE_RMII)
-	/* RMII pin group */
-	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
-	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
-	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
-	{0xC, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
-	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
-	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
-#else
-	/* MII pin group */
-	{0x1, 19, (MD_PLN | MD_EZI),                   FUNC0},
-	{0x0, 1,  (MD_PLN),                            FUNC6},
-	{0x1, 18, (MD_PLN),                            FUNC3},
-	{0x1, 20, (MD_PLN),                            FUNC3},
-	{0x1, 17, (MD_PLN | MD_EZI),                   FUNC3},
-	{0xC, 1,  (MD_PLN),                            FUNC3},
-	{0x1, 16, (MD_PLN | MD_EZI),                   FUNC7},
-	{0x1, 15, (MD_PLN | MD_EZI),                   FUNC3},
-	{0x0, 0,  (MD_PLN | MD_EZI),                   FUNC2},
-	{0x9, 4,  (MD_PLN),                            FUNC5},
-	{0x9, 5,  (MD_PLN),                            FUNC5},
-	{0xC, 0,  (MD_PLN | MD_EZI),                   FUNC3},
-	{0x9, 0,  (MD_PLN | MD_EZI),                   FUNC5},
-	{0x9, 1,  (MD_PLN | MD_EZI),                   FUNC5},
-	{0x9, 6,  (MD_PLN | MD_EZI),                   FUNC5},
-	{0x9, 3,  (MD_PLN | MD_EZI),                   FUNC5},
-	{0x9, 2,  (MD_PLN | MD_EZI),                   FUNC5},
-	{0xC, 8,  (MD_PLN | MD_EZI),                   FUNC4},
-#endif
-	/* External data lines D0 .. D15 */
-	{0x1, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x5, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	/* Address lines A0 .. A23 */
-	{0x2, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x1, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x1, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x6, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
-	{0x6, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
-	{0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xE, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xA, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	/* EMC control signals */
-	{0x1, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
-	{0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x6, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{PINMUX_CLK, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{PINMUX_CLK, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{PINMUX_CLK, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{PINMUX_CLK, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xD, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 3,  MD_PLN_FAST,                         FUNC3},
-	{0x1, 4,  MD_PLN_FAST,                         FUNC3},
-	{0x6, 6,  MD_PLN_FAST,                         FUNC3},
-	{0x1, 5,  MD_PLN_FAST,                         FUNC3},
-	/* LCD interface, 24bpp */
-	{0x7, 7,  MD_PUP,                              FUNC3},
-	{0x4, 7,  MD_PUP,                              FUNC0},
-	{0x4, 5,  MD_PUP,                              FUNC2},
-	{0x4, 6,  MD_PUP,                              FUNC2},
-	{0x7, 6,  MD_PUP,                              FUNC3},
-	{0x4, 1,  MD_PUP,                              FUNC2},
-	{0x4, 4,  MD_PUP,                              FUNC2},
-	{0x4, 2,  MD_PUP,                              FUNC2},
-	{0x8, 7,  MD_PUP,                              FUNC3},
-	{0x8, 6,  MD_PUP,                              FUNC3},
-	{0x8, 5,  MD_PUP,                              FUNC3},
-	{0x8, 4,  MD_PUP,                              FUNC3},
-	{0x7, 5,  MD_PUP,                              FUNC3},
-	{0x4, 8,  MD_PUP,                              FUNC2},
-	{0x4, 10, MD_PUP,                              FUNC2},
-	{0x4, 9,  MD_PUP,                              FUNC2},
-	{0x8, 3,  MD_PUP,                              FUNC3},
-	{0xB, 6,  MD_PUP,                              FUNC2},
-	{0xB, 5,  MD_PUP,                              FUNC2},
-	{0xB, 4,  MD_PUP,                              FUNC2},
-	{0x7, 4,  MD_PUP,                              FUNC3},
-	{0x7, 2,  MD_PUP,                              FUNC3},
-	{0x7, 1,  MD_PUP,                              FUNC3},
-	{0xB, 3,  MD_PUP,                              FUNC2},
-	{0xB, 2,  MD_PUP,                              FUNC2},
-	{0xB, 1,  MD_PUP,                              FUNC2},
-	{0xB, 0,  MD_PUP,                              FUNC2},
-	{0x7, 0,  MD_PUP,                              FUNC3},
-	{0x4, 4,  MD_PUP,                              FUNC0},
-	{0x7, 3,  MD_PUP,                              FUNC0},
-	{0x4, 1,  MD_PUP,                              FUNC0},
-	/* Board LEDs */
-	{0x8, 1,  MD_PDN,                              FUNC0},
-	{0xE, 6,  MD_PDN,                              FUNC4},	/* GPIO7.6, green */
-	{0xE, 8,  MD_PDN,                              FUNC4},	/* GPIO7.8, blue */
-	{0xE, 5,  MD_PDN,                              FUNC4},	/* GPIO7.5, red */
-	/* Board ADC */
-	{0xF, 9,  MD_PLN,                              FUNC7},
-	/*  I2S  */
-	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
-	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
-	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
-	int i;
-
-	/* Setup system level pin muxing */
-	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
-		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
-						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
-	}
-}
-
-/* EMC clock delay */
-#define CLK0_DELAY 7
-
-/* Hitex SDRAM timing and chip Config */
-STATIC const IP_EMC_DYN_CONFIG_Type IS42S16400_config = {
-	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
-	0x01,	/* Command Delayed */
-	EMC_NANOSECOND(20),
-	EMC_NANOSECOND(60),
-	EMC_NANOSECOND(63),
-	EMC_CLOCK(0x05),
-	EMC_CLOCK(0x05),
-	EMC_CLOCK(0x04),
-	EMC_NANOSECOND(63),
-	EMC_NANOSECOND(63),
-	EMC_NANOSECOND(63),
-	EMC_NANOSECOND(14),
-	EMC_CLOCK(0x02),
-	{
-		{
-			EMC_ADDRESS_DYCS0,	/* Hitex Board uses DYCS0 for SDRAM */
-			3,	/* RAS */
-
-			EMC_DYN_MODE_WBMODE_PROGRAMMED |
-			EMC_DYN_MODE_OPMODE_STANDARD |
-			EMC_DYN_MODE_CAS_3 |
-			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
-			EMC_DYN_MODE_BURST_LEN_8,
-
-			EMC_DYN_CONFIG_DATA_BUS_16 |
-			EMC_DYN_CONFIG_LPSDRAM |
-			EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
-			EMC_DYN_CONFIG_MD_SDRAM
-		},
-		{0, 0, 0, 0},
-		{0, 0, 0, 0},
-		{0, 0, 0, 0}
-	}
-};
-
-/* Hitex Static RAM timing and chip Config */
-STATIC const IP_EMC_STATIC_CONFIG_Type IS62WV25616_config = {
-	2,
-	EMC_STATIC_CONFIG_MEM_WIDTH_16 |
-	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
-	EMC_STATIC_CONFIG_BLS_HIGH /* |
-							      EMC_CONFIG_BUFFER_ENABLE*/,
-
-	EMC_NANOSECOND(0),
-	EMC_NANOSECOND(30),
-	EMC_NANOSECOND(90),
-	EMC_NANOSECOND(55),
-	EMC_NANOSECOND(55),
-	EMC_NANOSECOND(55)
-};
-
-/* Hitex NorFlash timing and chip Config */
-STATIC const IP_EMC_STATIC_CONFIG_Type SST39VF320_config = {
-	0,
-	EMC_STATIC_CONFIG_MEM_WIDTH_16 |
-	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
-	EMC_STATIC_CONFIG_BLS_HIGH /* |
-							      EMC_CONFIG_BUFFER_ENABLE*/,
-
-	EMC_NANOSECOND(0),
-	EMC_NANOSECOND(35),
-	EMC_NANOSECOND(70),
-	EMC_NANOSECOND(70),
-	EMC_NANOSECOND(40),
-	EMC_CLOCK(4)
-};
-
-/* Setup external memories */
-STATIC void SystemSetupMemory(void)
-{
-	/* Setup EMC Delays */
-	/* Move all clock delays together */
-	LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
-
-	/* Setup EMC Clock Divider for divide by 2 */
-	Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
-	LPC_CREG->CREG6 |= (1 << 16);
-	Chip_Clock_Enable(CLK_MX_EMC);
-
-	/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
-	Chip_EMC_Init(1, 0, 0);
-	/* Init EMC Dynamic Controller */
-	Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config);
-	/* Init EMC Static Controller CS2 */
-	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config);
-	/* Init EMC Static Controller CS0 */
-	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config);
-
-	/* Enable Buffer for External Flash */
-	LPC_EMC->STATICCONFIG0 |= 1 << 19;
-}
-
-#endif
-
-/**
- * @brief	Setup the system
- *			SystemInit() is called prior to the application and sets up system
- *			clocking, memory, and any resources needed prior to the application
- *			starting.
- * @return	none
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
-	unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
-	extern void *__vector_table;
-
-	*pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
-	extern void *g_pfnVectors;
-
-	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
-	extern void *__Vectors;
-
-	*pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
-	fpuInit();
-#endif
-
-	/* Setup system clocking and memory. This is done early to allow the
-	   application and tools to clear memory and use scatter loading to
-	   external memory. */
-	SystemSetupClocking();
-	SystemSetupMuxing();
-	SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h
deleted file mode 100644
index 921fe5d419..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * @brief Keil MCB 1857/4357 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_H_
-#define __BOARD_H_
-
-#include "board_keil_mcb_18574357.h"
-
-#endif /* __BOARD_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c
deleted file mode 100644
index 085aff2343..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/*
- * @brief Keil MCB 1857/4357 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-#include "string.h"
-
-/* Keil board uses 83848 PHY and retarget */
-#include "lpc_phy_dp83848.c"
-#include "retarget.c"
-
-/** @ingroup BOARD_KEIL_MCB_18574357
- * @{
- */
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-/* Port and bit mapping for LEDs on GPIOs */
-static const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4};
-static const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14};
-
-/** UDA specified variables */
-/* System Register Data Set */
-uint16_t UDA_sys_regs_dat[] = {
-	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
-	UDA1380_REG_I2S_DEFAULT_VALUE,
-	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
-	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
-	UDA1380_REG_HEADAMP_DEFAULT_VALUE
-};
-
-/* System Register Data Set */
-uint16_t UDA_interfil_regs_dat[] = {
-	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
-	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
-	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
-	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
-	UDA1380_REG_MIXSDO_DEFAULT_VALUE
-};
-/* decimator Register Data Set */
-uint16_t UDA_decimator_regs_dat[] = {
-	UDA1380_REG_DECVOL_DEFAULT_VALUE,
-	UDA1380_REG_PGA_DEFAULT_VALUE,
-	UDA1380_REG_ADC_DEFAULT_VALUE,
-	UDA1380_REG_AGC_DEFAULT_VALUE
-};
-
-/** Private definitions for LCD */
-#define LCD_CS(x) ((x) ? (Chip_GPIO_WritePortBit(7, 16, true)) : (Chip_GPIO_WritePortBit(7, 16, false)))
-
-/** Private variables for LCD */
-uint32_t g_isPenDn;
-uint32_t g_isNewPenDn;
-const int32_t ad_left = 3813;
-const int32_t ad_top = 3805;// 237;
-const int32_t ad_right = 360;
-const int32_t ad_bottom = 237;	// 3805;
-
-const LCD_Config_Type MCB4300_LCD = {
-	8,						/*!< Horizontal back porch in clocks */
-	4,						/*!< Horizontal front porch in clocks */
-	4,						/*!< HSYNC pulse width in clocks */
-	240,					/*!< Pixels per line */
-	4,						/*!< Vertical back porch in clocks */
-	3,						/*!< Vertical front porch in clocks */
-	4,						/*!< VSYNC pulse width in clocks */
-	320,					/*!< Lines per panel */
-	0,						/*!< Invert output enable, 1 = invert */
-	1,						/*!< Invert panel clock, 1 = invert */
-	1,						/*!< Invert HSYNC, 1 = invert */
-	1,						/*!< Invert VSYNC, 1 = invert */
-	1,						/*!< AC bias frequency in clocks (not used) */
-	6,						/*!< Maximum bits per pixel the display supports */
-	LCD_TFT,				/*!< LCD panel type */
-	LCD_COLOR_FORMAT_RGB,	/*!< BGR or RGB */
-	0						/*!< Dual panel, 1 = dual panel display */
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock;
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Very simple (inaccurate) delay function */
-static void delay(uint32_t i) {
-	while (i--) {}
-}
-
-/* Write data to UDA register */
-static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
-
-	I2C_Config->tx_data[0] = reg;
-	I2C_Config->tx_data[1] = value >> 8;
-	I2C_Config->tx_data[2] = value & 0xFF;
-	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
-	delay(10000);
-}
-
-/* Read data from UDA register */
-static uint16_t UDA_Reg_read(UDA1380_REG reg) {
-	uint8_t rx_data[2];
-	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
-	return rx_data[0] << 8 | rx_data[1];
-}
-
-/* Initializes default settings for UDA1380 */
-static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
-{
-	uint16_t temp;
-	uint8_t  i;
-	/* Reset UDA1380 on board Keil */
-	Chip_SCU_PinMux(0x8, 0, MD_PUP, FUNC0);
-	Chip_GPIO_WriteDirBit(4, 0, true);
-	Chip_GPIO_WritePortBit(4, 0, true);
-	/* delay 1us */
-	delay(100000);
-	Chip_GPIO_WritePortBit(4, 0, false);
-	delay(100000);
-	for (i = 0; i < 5; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
-		if (temp != UDA_sys_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-
-	/* interfilter regs init */
-	for (i = 0; i < 5; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
-		if (temp != UDA_interfil_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-	/* decimator regs init */
-	for (i = 0; i < 4; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
-		if (temp != UDA_decimator_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-
-	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
-		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
-		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
-		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
-			return ERROR;
-		}
-		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
-					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
-					  I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
-		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
-			return ERROR;
-		}
-	}
-	return SUCCESS;
-
-}
-
-/** Private functions for LCD controller */
-/* Write to LCD controller, with A0 = 0 */
-static void LCD_X_Write00_16(uint16_t c) {
-
-	uint8_t buf[1];
-	LCD_CS(0);
-	buf[0] = 0x70;
-	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);	// Start + WR Register
-	buf[0] = (uint8_t) (c);
-	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
-	LCD_CS(1);
-}
-
-/* Write to LCD controller, with A0 = 1 */
-static void LCD_X_Write01_16(uint16_t c) {
-
-	uint8_t buf[1];
-	LCD_CS(0);
-	buf[0] = 0x72;
-	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);	/* Start + WR Data */
-	buf[0] = (uint8_t) (c >> 8);
-	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
-	buf[0] = (uint8_t) (c);
-	Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
-	LCD_CS(1);
-}
-
-/* Write to LCD controller's register */
-static void wr_reg(uint16_t reg, uint16_t dat) {
-	LCD_X_Write00_16(reg);
-	LCD_X_Write01_16(dat);
-}
-
-/* Pin configuration to communicate with LCD Controller */
-static void pinConfig(void)
-{
-	/* (DC) */
-	Chip_GPIO_WriteDirBit(7, 16, true);
-	// Chip_Clock_EnableOpts(sspclk, true, true, 1);
-}
-
-/* Writes a value to the STMPE811 register */
-static uint32_t Board_TSC_WriteReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t value)
-{
-	return Chip_I2C_MasterWriteReg(I2Cx, TSC_I2C_ADDR, regAddr, &value, 1);
-}
-
-/* Reads a value to the STMPE811 register */
-static uint32_t Board_TSC_ReadReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t *value)
-{
-	return Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, regAddr, value, 1);
-}
-
-/* Check if touch is detected or not */
-static bool Board_TSC_TouchDetect(IP_I2C_001_Type *I2Cx)
-{
-	uint8_t  CtrRegVal = 0;
-
-	if (Board_TSC_ReadReg(I2Cx, TSC_CTRL, &CtrRegVal) == 1) {
-		if (CtrRegVal & (1 << 7)) {
-			return true;
-		}
-	}
-	return false;
-}
-
-/* Get the touch coordinates from STMPE811 registers */
-static Status Board_TSC_GetTouchCoord(IP_I2C_001_Type *I2Cx, int16_t *x, int16_t *y)
-{
-	uint8_t fifo_size, tscData[4], i;
-
-	/* Read all samples except the last one */
-	Board_TSC_ReadReg(I2Cx, FIFO_SIZE, &fifo_size);
-	for (i = 0; i < fifo_size; ++i)
-		if (Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4) == 0) {
-			return ERROR;
-		}
-
-	/* Retrieve last taken sample */
-	Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4);
-	*x = (tscData[0] << 4) | ((tscData[1] & 0xF0) >> 4);
-	*y = ((tscData[1] & 0x0F) << 8) | tscData[2];
-
-	/* Clear interrupt flags */
-	Board_TSC_WriteReg(I2Cx, INT_STA, 0x1F);
-
-	return SUCCESS;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Update system core clock rate, should be called if the system has
-   a clock rate change */
-void SystemCoreClockUpdate(void)
-{
-	/* CPU core speed */
-	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
-}
-
-/* Initialize UART pins */
-void Board_UART_Init(LPC_USART_Type *UARTx)
-{
-	if (UARTx == LPC_USART0) {
-		Chip_SCU_PinMux(0x2, 0, MD_PDN, FUNC1);		/* P2.0 : UART0_TXD */
-		Chip_SCU_PinMux(0x2, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1);	/* P2.1 : UART0_RXD */
-	}
-	else if (UARTx == LPC_USART3) {
-		Chip_SCU_PinMux(0x2, 3, MD_PDN, FUNC2);			/* P2.3 : UART3_TXD */
-		Chip_SCU_PinMux(0x2, 4, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* P2.4 : UART3_RXD */
-	}
-}
-
-/* Initialize debug output via UART for board */
-void Board_Debug_Init(void)
-{
-#if defined(DEBUG_UART)
-	Board_UART_Init(DEBUG_UART);
-
-	Chip_UART_Init(DEBUG_UART);
-	Chip_UART_SetBaud(DEBUG_UART, 115200);
-	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
-
-	/* Enable UART Transmit */
-	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
-#endif
-}
-
-/* Sends a character on the UART */
-void Board_UARTPutChar(char ch)
-{
-#if defined(DEBUG_UART)
-	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
-#endif
-}
-
-/* Gets a character from the UART, returns EOF if no character is ready */
-int Board_UARTGetChar(void)
-{
-#if defined(DEBUG_UART)
-	uint8_t data;
-
-	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
-		return (int) data;
-	}
-#endif
-	return EOF;
-}
-
-/* Outputs a string on the debug UART */
-void Board_UARTPutSTR(char *str)
-{
-#if defined(DEBUG_UART)
-	while (*str != '\0') {
-		Board_UARTPutChar(*str++);
-	}
-#endif
-}
-
-/* Initializes board LED(s) */
-void Board_LED_Init()
-{
-	int i;
-
-	/* Must make sure J21 is installed to enabled LEDs */
-	/* PD.10 : LED 0 (leftmost) */
-	/* PD.11 : LED 1 */
-	/* PD.12 : LED 2 */
-	/* PD.13 : LED 3 */
-	/* PD.14 : LED 4 */
-	/* P9.0  : LED 5 */
-	/* P9.1  : LED 6 */
-	/* P9.2  : LED 7 (rightmost) */
-	for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) {
-		Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true);
-	}
-}
-
-#ifndef BOARD_LED_TEST_FUNCTION_WORKS
-	/* FIXME: temporary code for toggle LED support only */
-	static uint8_t LEDStates; /* shadow variable for LED states */
-#endif
-
-/* Sets the state of a board LED to on or off */
-void Board_LED_Set(uint8_t LEDNumber, bool On)
-{
-	if (LEDNumber <= 7) {
-		Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], On);
-#ifndef BOARD_LED_TEST_FUNCTION_WORKS
-		if (On) {
-			LEDStates |= (1 << LEDNumber); /* set the state */
-		} else {
-			LEDStates &= ~(1 << LEDNumber); /* clear the state */
-		}
-#endif		
-	}
-}
-
-/* Returns the current state of a board LED */
-bool Board_LED_Test(uint8_t LEDNumber)
-{
-	if (LEDNumber <= 7) {
-#ifndef BOARD_LED_TEST_FUNCTION_WORKS
-	if (LEDStates & (1 << LEDNumber)) { /* LED is on */
-		return true;
-	} else { /* LED is off */
-		return false;
-	}
-#else		
-		return (bool)Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]);
-#endif	
-	}
-	return false;
-}
-
-/* Returns the MAC address assigned to this board */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr)
-{
-	const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
-
-	memcpy(mcaddr, boardmac, 6);
-}
-
-/* Set up and initialize all required blocks and functions related to the
-   board hardware */
-void Board_Init(void)
-{
-	/* Sets up DEBUG UART */
-	DEBUGINIT();
-
-	/* Updates SystemCoreClock global var with current clock speed */
-	SystemCoreClockUpdate();
-
-	/* Initializes GPIO */
-	Chip_GPIO_Init();
-
-	/* Setup GPIOs for USB demos */
-	Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2);			/* P9_5 USB1_VBUS_EN, USB1 VBus function */
-	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	/* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
-	Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1);			/* P6_3 USB0_PWR_EN, USB0 VBus function */
-}
-
-/* Sets up board specific ADC interface */
-void Board_ADC_Init(void)
-{}
-
-/* Sets up board specific I2C interface */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx)
-{
-	if (I2Cx == LPC_I2C1) {
-		/* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */
-		Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2);
-		Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2);
-	}
-}
-
-/* Sets up board specific I2S interface and UDA1380 */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
-{
-	uint8_t uda1380_tx_data_buf[3];
-	Chip_I2S_Audio_Format_Type I2S_Config;
-	I2C_M_SETUP_Type I2C_Config;
-	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
-	I2C_Config.retransmissions_max = 5;
-	I2C_Config.tx_length = 3;
-	I2C_Config.tx_data = uda1380_tx_data_buf;
-	I2C_Config.rx_length = 0;
-	I2C_Config.rx_data = NULL;
-
-	/* Initialize I2C peripheral ------------------------------------*/
-	/* Init I2C */
-	Chip_I2C_Init(LPC_I2C0);
-	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
-	I2S_Config.SampleRate = 48000;
-	I2S_Config.ChannelNumber = 2;	/* 1 is mono, 2 is stereo */
-	I2S_Config.WordWidth =  16;		/* 8, 16 or 32 bits */
-	Chip_I2S_Init(LPC_I2S0);
-	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
-	/* Enable Slave I2C operation */
-	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
-	/* Init UDA1380 CODEC */
-	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
-}
-
-/* Initialize the LCD interface */
-void Board_LCD_Init(void)
-{
-	/* LCD with HX8347-D LCD Controller                                         */
-	SSP_ConfigFormat ssp_format1;
-	/* Attach main PLL clock to divider A with a divider of 2 */
-	Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2);
-
-	/* Route divider A output to LCD base clock and enable base clock */
-	Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false);
-
-	/* Reset LCD and wait for reset to complete */
-	Chip_RGU_TriggerReset(RGU_LCD_RST);
-	while (Chip_RGU_InReset(RGU_LCD_RST)) {}
-
-	/* Set backlight GPIO as an output */
-	Chip_GPIO_WriteDirBit(3, 8, true);
-
-	delay(5);
-
-	pinConfig();
-	// Chip_Clock_EnablePeripheralMax(SSP_ID);
-	/* TBD Externally */
-	Chip_SSP_Init(SSP_ID);
-	//	NVIC_EnableIRQ(SSP_ID);
-	Chip_SSP_Set_Master(SSP_ID, true);
-	Chip_SSP_Set_BitRate(SSP_ID, 1000000);
-
-	ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
-	ssp_format1.bits = SSP_BITS_8;
-	ssp_format1.clockFormat = SSP_CLOCK_MODE0;
-
-	Chip_SSP_Set_Format(SSP_ID, &ssp_format1);
-	Chip_SSP_Cmd(SSP_ID, ENABLE);
-
-	delay(200);
-
-	/* Driving ability settings ------------------------------------------------*/
-	wr_reg(0xEA, 0x00);					/* Power control internal used (1)    */
-	wr_reg(0xEB, 0x20);					/* Power control internal used (2)    */
-	wr_reg(0xEC, 0x0C);					/* Source control internal used (1)   */
-	wr_reg(0xED, 0xC7);					/* Source control internal used (2)   */
-	wr_reg(0xE8, 0x38);					/* Source output period Normal mode   */
-	wr_reg(0xE9, 0x10);					/* Source output period Idle mode     */
-	wr_reg(0xF1, 0x01);					/* RGB 18-bit interface ;0x0110       */
-	wr_reg(0xF2, 0x10);
-
-	/* Adjust the Gamma Curve --------------------------------------------------*/
-	wr_reg(0x40, 0x01);
-	wr_reg(0x41, 0x00);
-	wr_reg(0x42, 0x00);
-	wr_reg(0x43, 0x10);
-	wr_reg(0x44, 0x0E);
-	wr_reg(0x45, 0x24);
-	wr_reg(0x46, 0x04);
-	wr_reg(0x47, 0x50);
-	wr_reg(0x48, 0x02);
-	wr_reg(0x49, 0x13);
-	wr_reg(0x4A, 0x19);
-	wr_reg(0x4B, 0x19);
-	wr_reg(0x4C, 0x16);
-
-	wr_reg(0x50, 0x1B);
-	wr_reg(0x51, 0x31);
-	wr_reg(0x52, 0x2F);
-	wr_reg(0x53, 0x3F);
-	wr_reg(0x54, 0x3F);
-	wr_reg(0x55, 0x3E);
-	wr_reg(0x56, 0x2F);
-	wr_reg(0x57, 0x7B);
-	wr_reg(0x58, 0x09);
-	wr_reg(0x59, 0x06);
-	wr_reg(0x5A, 0x06);
-	wr_reg(0x5B, 0x0C);
-	wr_reg(0x5C, 0x1D);
-	wr_reg(0x5D, 0xCC);
-
-	/* Power voltage setting ---------------------------------------------------*/
-	wr_reg(0x1B, 0x1B);
-	wr_reg(0x1A, 0x01);
-	wr_reg(0x24, 0x2F);
-	wr_reg(0x25, 0x57);
-	wr_reg(0x23, 0x88);
-
-	/* Power on setting --------------------------------------------------------*/
-	wr_reg(0x18, 0x36);					/* Internal oscillator frequency adj  */
-	wr_reg(0x19, 0x01);					/* Enable internal oscillator         */
-	wr_reg(0x01, 0x00);					/* Normal mode, no scrool             */
-	wr_reg(0x1F, 0x88);					/* Power control 6 - DDVDH Off        */
-	delay(20);
-	wr_reg(0x1F, 0x82);					/* Power control 6 - Step-up: 3 x VCI */
-	delay(5);
-	wr_reg(0x1F, 0x92);					/* Power control 6 - Step-up: On      */
-	delay(5);
-	wr_reg(0x1F, 0xD2);					/* Power control 6 - VCOML active     */
-	delay(5);
-
-	/* Color selection ---------------------------------------------------------*/
-	wr_reg(0x17, 0x55);					/* RGB, System interface: 16 Bit/Pixel*/
-	wr_reg(0x00, 0x00);					/* Scrolling off, no standby          */
-
-	/* Interface config --------------------------------------------------------*/
-	wr_reg(0x2F, 0x11);					/* LCD Drive: 1-line inversion        */
-	wr_reg(0x31, 0x02);					/* Value for SPI: 0x00, RBG: 0x02     */
-	wr_reg(0x32, 0x00);					/* DPL=0, HSPL=0, VSPL=0, EPL=0       */
-
-	/* Display on setting ------------------------------------------------------*/
-	wr_reg(0x28, 0x38);					/* PT(0,0) active, VGL/VGL            */
-	delay(20);
-	wr_reg(0x28, 0x3C);					/* Display active, VGL/VGL            */
-
-	wr_reg(0x16, 0x00);					/* Mem Access Control (MX/Y/V/L,BGR)  */
-
-	/* Display scrolling settings ----------------------------------------------*/
-	wr_reg(0x0E, 0x00);					/* TFA MSB                            */
-	wr_reg(0x0F, 0x00);					/* TFA LSB                            */
-	wr_reg(0x10, 320 >> 8);				/* VSA MSB                            */
-	wr_reg(0x11, 320 &  0xFF);			/* VSA LSB                            */
-	wr_reg(0x12, 0x00);					/* BFA MSB                            */
-	wr_reg(0x13, 0x00);					/* BFA LSB                            */
-
-}
-
-/* Initializes the STMPE811 touch screen controller */
-void Init_Touch_Controller(void)
-{
-	volatile int32_t i;
-
-	/* Init I2C */
-	Chip_I2C_Init(LPC_I2C0);
-	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
-	/* Enable Slave I2C operation */
-	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
-
-	/* Reset Touch-screen controller	    */
-	Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL1, 0x02);
-
-	for (i = 0; i < 200000; i++) {}
-
-	/* Enable TSC and ADC                 */
-	Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL2, 0x0C);
-	/* Enable Touch detect, FIFO          */
-	Board_TSC_WriteReg(LPC_I2C0, INT_EN, 0x07);
-	/* Set sample time , 12-bit mode      */
-	Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL1, 0x69);
-
-	for (i = 0; i < 40000; i++) {}
-
-	/* ADC frequency 3.25 MHz             */
-	Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL2, 0x01);
-	/* Tracking index: 8, operation mode : XY only */
-	Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x22);
-	/* Detect delay 10us Settle time 500us*/
-	Board_TSC_WriteReg(LPC_I2C0, TSC_CFG, 0xC2);
-	/* Threshold for FIFO                 */
-	Board_TSC_WriteReg(LPC_I2C0, FIFO_TH, 0x01);
-	/* FIFO reset                         */
-	Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x01);
-	/* FIFO not reset	                   */
-	Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x00);
-	/* Drive 50 mA typical	              */
-	Board_TSC_WriteReg(LPC_I2C0, TSC_I_DRIVE, 0x01);
-	/* Pins are used for touchscreen	    */
-	Board_TSC_WriteReg(LPC_I2C0, GPIO_ALT_FUNCT, 0x00);
-	/* Enable TSC	                       */
-	Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x01);
-	/* Clear interrupt status	           */
-	Board_TSC_WriteReg(LPC_I2C0, INT_STA, 0xFF);
-}
-
-/* Get touch screen position */
-bool GetTouchPos(int16_t *pX, int16_t *pY)
-{
-	int16_t x, y, rng;
-	if (Board_TSC_TouchDetect(LPC_I2C0)) {
-		Board_TSC_GetTouchCoord(LPC_I2C0, &x, &y);
-		g_isPenDn = 1;
-		g_isNewPenDn = 1;
-
-		/* calibrate X */
-		rng = ad_right - ad_left;
-		if (rng < 0) {
-			rng = -rng;
-		}
-		x -= (ad_right < ad_left) ? ad_right : ad_left;
-		*pX = (x * C_GLCD_H_SIZE) / rng;
-		if (ad_left > ad_right) {
-			*pX = C_GLCD_H_SIZE - *pX;
-		}
-
-		/* calibrate Y */
-		rng = ad_bottom - ad_top;
-		if (rng < 0) {
-			rng = -rng;
-		}
-		y -= (ad_bottom < ad_top) ? ad_bottom : ad_top;
-		*pY = (y * C_GLCD_V_SIZE) / rng;
-		if (ad_top > ad_bottom) {
-			*pY = C_GLCD_V_SIZE - *pY;
-		}
-	}
-	else {
-		g_isPenDn = 0;
-	}
-
-	if (g_isNewPenDn) {
-		g_isNewPenDn = 0;
-		if (*pX < 0) {
-			*pX = -*pX;
-		}
-		if (*pY < 0) {
-			*pY = -*pY;
-		}
-		return true;
-	}
-	return false;
-}
-
-/* Turn on LCD backlight */
-void Board_LCD_Set_Backlight(uint8_t Intensity)
-{
-	bool OnOff = (bool) (Intensity != 0);
-
-	Chip_GPIO_WritePortBit(3, 8, OnOff);
-}
-
-/* Interrupt handler for GPIO0 */
-void GPIO0_IRQHandler(void)
-{
-	static bool On;
-
-	if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
-		Chip_GPIO_IntClear(0, 0);
-		On = (bool) !On;
-		Board_LED_Set(1, On);
-	}
-}
-
-/* Initializes board specific GPIO Interrupt */
-void Board_GPIO_Int_Init()
-{
-	Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0);	/* PF.9 : POTI button */
-	Chip_GPIO_WriteDirBit(7, 23, false);	/* PF.9 -> GPIO7[23] : input */
-	Chip_SCU_GPIOIntPinSel(0, 7, 23);
-	Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE);	/* Configure GPIO0[7] to interrupt pin (SW2 switch) */
-
-	NVIC_EnableIRQ(PIN_INT0_IRQn);	/* enable GPIO interrupt 0 */
-}
-
-/* Initializes SDMMC interface */
-void Board_SDMMC_Init(void)
-{
-	Chip_SCU_PinMux(0xC, 4, MD_PLN_FAST, FUNC7);	/* PC.4 connected to SDIO_D0 */
-	Chip_SCU_PinMux(0xC, 5, MD_PLN_FAST, FUNC7);	/* PC.5 connected to SDIO_D1 */
-	Chip_SCU_PinMux(0xC, 6, MD_PLN_FAST, FUNC7);	/* PC.6 connected to SDIO_D2 */
-	Chip_SCU_PinMux(0xC, 7, MD_PLN_FAST, FUNC7);	/* PC.7 connected to SDIO_D3 */
-
-	Chip_SCU_PinMux(0xC, 8, MD_PLN | MD_EZI, FUNC7);/* PC.4 connected to SDIO_CD */
-	Chip_SCU_PinMux(0xC, 10, MD_PLN_FAST, FUNC7);	/* PC.10 connected to SDIO_CMD */
-	Chip_SCU_PinMux(0xC, 0, MD_PLN | MD_EHS, FUNC7);/* PC.0 connected to SDIO_CLK */
-}
-
-/* Initializes SSP interface */
-void Board_SSP_Init(LPC_SSP_Type *SSPx)
-{
-	if (SSPx == LPC_SSP0) {
-		/* Set up clock and power for SSP0 module */
-		/* Configure SSP0 pins*/
-		Chip_SCU_PinMux(0x3, 3, MD_PLN_FAST, FUNC2);	/* P3.3 connected to SCL/SCLK	func2=SSP0 SCK0 */
-		Chip_SCU_PinMux(0x3, 6, MD_PLN_FAST, FUNC2);	/* P3.6 connected to nCS		func2=SSP0 SSEL0 */
-		Chip_SCU_PinMux(0x3, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* P3.7 connected to SO		func2=SSP0 MISO0 */
-		Chip_SCU_PinMux(0x3, 8, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* P3.8 connected to nSI	func2=SSP0 MOSI0 */
-
-		Chip_Clock_EnableOpts(CLK_MX_SSP0, true, true, 1);
-	}
-	else if (SSPx == LPC_SSP1) {
-		/* Set up clock and power for SSP1 module */
-		/* Configure SSP1 pins*/
-		Chip_SCU_PinMux(0xF, 4, MD_PLN_FAST, FUNC0);	/* PF.4 connected to SCL/SCLK	func0 = SSP1 SCK1 */
-		Chip_SCU_PinMux(0xF, 5, MD_PLN_FAST, FUNC2);	/* PF.5 connected to nCS		func2 = SSP1 SSEL1 */
-		Chip_SCU_PinMux(0xF, 6, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* PF.6 connected to SO			  func2 = SSP1 MISO1 */
-		Chip_SCU_PinMux(0xF, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2);	/* PF.7 connected to nSI		  func2 = SSP1 MOSI1 */
-
-		Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
-	}
-	else {
-		return;
-	}
-}
-
-/* Initializes board specific buttons */
-void Board_Buttons_Init(void)
-{
-	Chip_SCU_PinMux(0x4,  0, MD_PUP | MD_EZI | MD_ZI, FUNC0);	/* P9.1  : LED 6 */
-	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false);
-}
-
-/* Sets up default states for joystick */
-void Board_Joystick_Init(void)
-{
-	Chip_SCU_PinMux(0xC, 9, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_9  as GPIO6[8] */
-	Chip_SCU_PinMux(0xC, 11, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_11 as GPIO6[10] */
-	Chip_SCU_PinMux(0xC, 12, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_12 as GPIO6[11] */
-	Chip_SCU_PinMux(0xC, 13, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_13 as GPIO6[12] */
-	Chip_SCU_PinMux(0xC, 14, MD_PUP | MD_EZI | MD_ZI, FUNC4);		/* PC_14 as GPIO6[13] */
-
-	Chip_GPIO_WriteDirBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM, false);		/* input */
-	Chip_GPIO_WriteDirBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM, false);	/* input */
-	Chip_GPIO_WriteDirBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM, false);	/* input */
-	Chip_GPIO_WriteDirBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM, false);	/* input */
-	Chip_GPIO_WriteDirBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM, false);	/* input */
-}
-
-/* Gets joystick status */
-uint8_t Joystick_GetStatus(void)
-{
-
-	uint8_t ret = NO_BUTTON_PRESSED;
-
-	if (Chip_GPIO_ReadPortBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM) == 0) {
-		ret |= JOY_UP;
-	}
-	else if (Chip_GPIO_ReadPortBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM) == 0) {
-		ret |= JOY_DOWN;
-	}
-	else if (Chip_GPIO_ReadPortBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM) == 0) {
-		ret |= JOY_LEFT;
-	}
-	else if (Chip_GPIO_ReadPortBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM) == 0) {
-		ret |= JOY_RIGHT;
-	}
-	else if (Chip_GPIO_ReadPortBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM) == 0) {
-		ret |= JOY_PRESS;
-	}
-
-	return ret;
-}
-
-/* Gets buttons status */
-uint32_t Buttons_GetStatus(void)
-{
-	uint8_t ret = NO_BUTTON_PRESSED;
-
-	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
-		ret |= BUTTONS_BUTTON1;
-	}
-	return ret;
-}
-
-/* FIXME Should we remove this function? */
-void Serial_CreateStream(void *Stream)
-{
-	// implement later
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h
deleted file mode 100644
index 3e464a14d4..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * @brief Keil MCB 1857/4357 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_KEIL_MCB_18574357_H_
-#define __BOARD_KEIL_MCB_18574357_H_
-
-#include "chip.h"
-#include "board_api.h"
-#include "lpc_phy.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_KEIL_MCB_18574357 LPC1857 and LPC4357 Keil MCB board support functions
- * @ingroup BOARDS_18XX_43XX
- * @{
- */
-
-/** @defgroup BOARD_KEIL_MCB_18574357_OPTIONS BOARD: LPC1857 and LPC4357 Keil MCB board builds options
- * The NGX board has options that configure it's operation at build-time.<br/>
- * CHIP_LPC*
- *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
- * DEBUG:<br/>
- * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
- * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
- * DEBUG_UART:<br/>
- *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
- * CRYSTAL_MAIN_FREQ_IN:<br/>
- *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
- * CRYSTAL_32K_FREQ_IN:<br/>
- *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
- * EXTERNAL_CLKIN_FREQ_IN:<br/>
- *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
- * MAX_CLOCK_FREQ:<br/>
- *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
- *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
- * BOARD_HITEX_EVA_18504350:<br/>
- *  - When building for Keil boards, BOARD_KEIL_MCB_18574357 is defined<br/>
- * <br/><p>
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
- * @{
- */
-
-/**
- * @}
- */
-
-#define BOARD_KEIL_MCB_18574357
-
-#define LED_NUMBER_OF 1
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM			2
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM			0
-#define JOYSTICK_UP_GPIO_PORT_NUM               6
-#define JOYSTICK_UP_GPIO_BIT_NUM                10
-#define JOYSTICK_DOWN_GPIO_PORT_NUM             6
-#define JOYSTICK_DOWN_GPIO_BIT_NUM              11
-#define JOYSTICK_LEFT_GPIO_PORT_NUM             6
-#define JOYSTICK_LEFT_GPIO_BIT_NUM              12
-#define JOYSTICK_RIGHT_GPIO_PORT_NUM            6
-#define JOYSTICK_RIGHT_GPIO_BIT_NUM             13
-#define JOYSTICK_PRESS_GPIO_PORT_NUM            6
-#define JOYSTICK_PRESS_GPIO_BIT_NUM             8
-
-#define JOY_UP              0x01
-#define JOY_DOWN            0x02
-#define JOY_LEFT            0x04
-#define JOY_RIGHT           0x08
-#define JOY_PRESS           0x10
-#define NO_BUTTON_PRESSED   0x00
-
-#define BUTTONS_BUTTON1     0x01
-
-#define LEDS_LED1           0x01
-#define LEDS_LED2           0x02
-#define LEDS_LED3           0x04
-#define LEDS_LED4           0x08
-#define LEDS_NO_LEDS        0x00
-
-/** UDA1380 register values */
-#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
-#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
-
-#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE	(1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
-#define UDA1380_REG_ANAMIX_DEFAULT_VALUE	0x0000
-#define UDA1380_REG_HEADAMP_DEFAULT_VALUE	( 1 << 9 | 2)
-
-#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE	0x0000
-#define UDA1380_REG_MIXVOL_DEFAULT_VALUE	0x0000
-#define UDA1380_REG_MODEBBT_DEFAULT_VALUE	0x0000
-#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE	(2 << 8 | 2)
-#define UDA1380_REG_MIXSDO_DEFAULT_VALUE	0x0000
-
-#define UDA1380_REG_DECVOL_DEFAULT_VALUE	0xE4E4			/* Decrease Volume -28dB */
-#define UDA1380_REG_PGA_DEFAULT_VALUE		0x0000
-#define UDA1380_REG_ADC_DEFAULT_VALUE		0x0001			/* Apply 0bB VGA Gain, enable DC Filter */
-#define UDA1380_REG_AGC_DEFAULT_VALUE		0x0000
-
-#define UDA1380_REG_L3_DEFAULT_VALUE		0x0000
-
-/* UDA1380 address */
-#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
-
-/* UDA1380 Register Address */
-typedef enum {
-	UDA_EVALM_CLK = 0x00,
-	UDA_BUS_CTRL,
-	UDA_POWER_CTRL,
-	UDA_ANALOG_CTRL,
-	UDA_HPAMP_CTRL,
-	UDA_MASTER_VOL_CTRL = 0x10,
-	UDA_MIXER_VOL_CTRL,
-	UDA_MODE_CTRL,
-	UDA_MUTE_CTRL,
-	UDA_MIXER_FILTER_CTRL,
-	UDA_DEC_VOL_CTRL = 0x20,
-	UDA_PGA_CTRL,
-	UDA_ADC_CTRL,
-	UDA_AGC_CTRL,
-	UDA_TOTAL_REG
-} UDA1380_REG;
-
-/* Frame buffer address for lcd */
-#define FRAMEBUFFER_ADDR        0x28000000
-
-extern const LCD_Config_Type MCB4300_LCD;
-#define BOARD_LCD MCB4300_LCD
-
-/** Audio input select structure */
-typedef enum {
-	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
-	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
-} Board_Audio_Input_Sel_Type;
-
-/** LCD controller definitions */
-#define SSP_ID LPC_SSP0
-#define C_GLCD_H_SIZE   240
-#define C_GLCD_V_SIZE   320
-
-/** Private types/definitions for touch screen controller (STMPE811) */
-
-#define TSC_I2C_ADDR    (0x82 >> 1)	/* Touchscreen 7-bit I2C address */
-
-/** STMPE811 Register addresses */
-#define SYS_CTRL1       0x03
-#define SYS_CTRL2       0x04
-#define INT_CTRL        0x09
-#define INT_EN          0x0A
-#define INT_STA         0x0B
-#define GPIO_ALT_FUNCT  0x17
-#define ADC_CTRL1       0x20
-#define ADC_CTRL2       0x21
-#define TSC_CTRL        0x40
-#define TSC_CFG         0x41
-#define FIFO_TH         0x4A
-#define FIFO_STA        0x4B
-#define FIFO_SIZE       0x4C
-#define DATA_X          0x4D
-#define DATA_Y          0x4F
-#define DATA_Z          0x51
-#define TSC_FRACTION_Z  0x56
-#define TSC_I_DRIVE     0x58
-#define TSC_SHIELD      0x59
-#define DATA_XYZ        0xD7
-
-/**
- * @brief	Sets up board specific ADC interface
- * @return	Nothing
- */
-void Board_ADC_Init(void);
-
-/**
- * @brief	Sets up board specific I2C interface
- * @param	I2Cx	: Pointer to I2C interface to initialize
- * @return	Nothing
- */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Initializes board specific GPIO Interrupt
- * @return	Nothing
- */
-void Board_GPIO_Int_Init(void);
-
-/**
- * @brief	Sets up board specific SDMMC interface
- * @return	Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief	Sets up board specific SSP interface
- * @param	SSPx	: Pointer to SSP interface to initialize
- * @return	Nothing
- */
-void Board_SSP_Init(LPC_SSP_Type *SSPx);
-
-/**
- * @brief	Returns the MAC address assigned to this board
- * @param	mcaddr	: Pointer to 6-byte character array to populate with MAC address
- * @return	Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief	Initialize pin muxing for a UART
- * @param	UARTx	: Pointer to UART register block for UART pins to init
- * @return	Nothing
- */
-void Board_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief	Initialize the LCD interface
- * @return	Nothing
- */
-void Board_LCD_Init(void);
-
-/**
- * @brief	Initializes the STMPE811 touch screen controller
- * @return	Nothing
- */
-void Init_Touch_Controller(void);
-
-/**
- * @brief	Get touch screen position
- * @param	pX	: pointer to X position
- * @param	pY	: pointer to Y position
- * @return	true if touch is detected or false if otherwise
- */
-bool GetTouchPos(int16_t *pX, int16_t *pY);
-
-/**
- * @brief	Initializes board specific buttons
- * @return	Nothing
- */
-void Board_Buttons_Init (void);
-
-/**
- * @brief	Initializes board specific joystick
- * @return	Nothing
- */
-void Board_Joystick_Init (void);
-
-/**
- * @brief	Initialize joystick interface on board
- * @return	joystick status: up, down, left or right
- */
-uint8_t Joystick_GetStatus (void);
-
-/**
- * @brief	Returns button(s) state on board
- * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus(void);
-
-/**
- * @brief	Sets up board specific I2S interface and UDA1380
- * @param	I2Sx			: Pointer to I2S interface to initialize
- * @param	audio_in_sel	: audio input selection
- * @return	Nothing
- */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
-
-//FIXME Should we remove this function?
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_KEIL_MCB_18574357_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h
deleted file mode 100644
index 1bf1605fbc..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC18XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
-   via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART3
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h
deleted file mode 100644
index 79d27bd36c..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC43XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
-   via semihosting */
-// #define DEBUG_SEMIHOSTING'
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART3
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (204000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c
deleted file mode 100644
index 1e40430b2c..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_KEIL_MCB_18574357_SYSINIT LPC1857 and LPC4357 Keil MCB board System Init code
- * @ingroup BOARD_KEIL_MCB_18574357
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the Keil MCB boards includes clock setup, default pin muxing, and
- * memory configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1857 and LPC4357 Keil MCB setup<BR>
- *  Clocking:<BR>
- *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
- *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
- *   SPIFI FLASH clock setup for fastest speed<BR>
- *  Pin muxing:<BR>
- *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
- *   Sets up the external memory controller signals<BR>
- *  Memory:<BR>
- *   Sets up DRAM and NOR FLASH.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
-	uint8_t pingrp;	/* Pin group */
-	uint8_t pinnum;	/* Pin number */
-	uint8_t pincfg;	/* Pin configuration for SCU */
-	uint8_t funcnum;/* Function number */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
-	CGU_BASE_CLK_T clk;	/* Base clock */
-	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
-	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
-	bool powerdn;		/* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
-	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
-	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
-#endif
-	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
-#endif
-	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
-	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
-	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
-	{CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
-	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
-	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
-	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
-	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
-	{0x3, 3,  (MD_PLN_FAST),  FUNC3},
-	{0x3, 4,  (MD_PLN_FAST),  FUNC3},
-	{0x3, 5,  (MD_PLN_FAST),  FUNC3},
-	{0x3, 6,  (MD_PLN_FAST),  FUNC3},
-	{0x3, 7,  (MD_PLN_FAST),  FUNC3},
-	{0x3, 8,  (MD_PLN_FAST),  FUNC3}
-};
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
-	int i;
-
-	/* Setup FLASH acceleration to target clock rate prior to clock switch */
-	Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
-
-	/* Switch main system clocking to crystal */
-	Chip_Clock_EnableCrystal();
-	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
-	/* Setup PLL for 100MHz and switch main system clocking */
-	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
-	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
-	/* Setup PLL for maximum clock */
-	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
-	/* Setup system base clocks and initial states. This won't enable and
-	   disable individual clocks, but sets up the base clock sources for
-	   each individual peripheral clock. */
-	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
-		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
-								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
-	}
-
-	/* Reset and enable 32Khz oscillator */
-	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
-	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
-	/* SPIFI pin setup is done prior to setting up system clocking */
-	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
-		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
-						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
-	}
-
-	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
-	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
-	/* RMII pin group */
-	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
-	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
-	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
-	{0xC, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
-	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
-	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
-	/* External data lines D0 .. D15 */
-	{0x1, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x5, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x5, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xE, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	/* Address lines A0 .. A23 */
-	{0x2, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x1, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x1, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x2, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x2, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x6, 8,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
-	{0x6, 7,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
-	{0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xE, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xE, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xA, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	/* EMC control signals */
-	{0x1, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC1},
-	{0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0x6, 9,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 6,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 4,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 5,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{PINMUX_CLK, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{PINMUX_CLK, 1,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{PINMUX_CLK, 2,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{PINMUX_CLK, 3,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC0},
-	{0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0xD, 0,  (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC2},
-	{0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS),  FUNC3},
-	{0x1, 3,  MD_PLN_FAST,                         FUNC3},
-	{0x1, 4,  MD_PLN_FAST,                         FUNC3},
-	{0x6, 6,  MD_PLN_FAST,                         FUNC1},
-	{0x1, 5,  MD_PLN_FAST,                         FUNC3},
-	{0x1, 6,  MD_PLN_FAST,                         FUNC3},
-	/* Board LEDs */
-	{0xD, 10, (MD_PLN),                            FUNC4},
-	{0xD, 11, (MD_PLN),                            FUNC4},
-	{0xD, 12, (MD_PLN),                            FUNC4},
-	{0xD, 13, (MD_PLN),                            FUNC4},
-	{0xD, 14, (MD_PLN),                            FUNC4},
-	{0x9, 0,  (MD_PLN),                            FUNC0},
-	{0x9, 1,  (MD_PLN),                            FUNC0},
-	{0x9, 2,  (MD_PLN),                            FUNC0},
-	/* SSP0 */
-	{0xF, 0,  (MD_PLN_FAST),                       FUNC0},
-	{0xF, 1,  (MD_PLN_FAST),                       FUNC4},
-	{0xF, 2,  (MD_PLN_FAST),                       FUNC2},
-	{0xF, 3,  (MD_PLN_FAST),                       FUNC2},
-	/* LCD interface, 16bpp */
-	{0x4, 1,  MD_PUP,                              FUNC5},
-	{0x4, 2,  MD_PUP,                              FUNC2},
-	{0x4, 5,  MD_PUP,                              FUNC2},
-	{0x4, 6,  MD_PUP,                              FUNC2},
-	{0x4, 7,  MD_PUP,                              FUNC0},
-	{0x4, 9,  MD_PUP,                              FUNC2},
-	{0x4, 10, MD_PUP,                              FUNC2},
-	{0x7, 0,  MD_PUP,                              FUNC0},
-	{0x7, 6,  MD_PUP,                              FUNC3},
-	{0x8, 3,  MD_PUP,                              FUNC3},
-	{0x8, 4,  MD_PUP,                              FUNC3},
-	{0x8, 5,  MD_PUP,                              FUNC3},
-	{0x8, 6,  MD_PUP,                              FUNC3},
-	{0x8, 7,  MD_PUP,                              FUNC3},
-	{0xB, 0,  MD_PUP,                              FUNC2},
-	{0xB, 1,  MD_PUP,                              FUNC2},
-	{0xB, 2,  MD_PUP,                              FUNC2},
-	{0xB, 3,  MD_PUP,                              FUNC2},
-	{0xB, 4,  MD_PUP,                              FUNC2},
-	{0xB, 5,  MD_PUP,                              FUNC2},
-	{0xB, 6,  MD_PUP,                              FUNC2},
-	/*  I2S  */
-	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
-	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
-	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
-	int i;
-
-	/* Setup system level pin muxing */
-	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
-		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
-						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
-	}
-}
-
-/* EMC clock delay */
-#define CLK0_DELAY 7
-
-/* Keil SDRAM timing and chip Config */
-STATIC const IP_EMC_DYN_CONFIG_Type MT48LC4M32_config = {
-	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
-	0x01,	/* Command Delayed */
-	EMC_NANOSECOND(18),
-	EMC_NANOSECOND(42),
-	EMC_NANOSECOND(70),
-	EMC_CLOCK(0x01),
-	EMC_CLOCK(0x05),
-	EMC_NANOSECOND(12),
-	EMC_NANOSECOND(60),
-	EMC_NANOSECOND(60),
-	EMC_NANOSECOND(70),
-	EMC_NANOSECOND(12),
-	EMC_CLOCK(0x02),
-	{
-		{
-			EMC_ADDRESS_DYCS0,	/* Keil Board uses DYCS0 for SDRAM */
-			3,	/* RAS */
-
-			EMC_DYN_MODE_WBMODE_PROGRAMMED |
-			EMC_DYN_MODE_OPMODE_STANDARD |
-			EMC_DYN_MODE_CAS_3 |
-			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
-			EMC_DYN_MODE_BURST_LEN_4,
-
-			EMC_DYN_CONFIG_DATA_BUS_32 |
-			EMC_DYN_CONFIG_LPSDRAM |
-			EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS |
-			EMC_DYN_CONFIG_MD_SDRAM
-		},
-		{0, 0, 0, 0},
-		{0, 0, 0, 0},
-		{0, 0, 0, 0}
-	}
-};
-
-/* Keil NorFlash timing and chip Config */
-/* FIXME : Keil NOR FLASH not yet tested */
-STATIC const IP_EMC_STATIC_CONFIG_Type S29GL64N90_config = {
-	0,
-	EMC_STATIC_CONFIG_MEM_WIDTH_32 |
-	EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
-	EMC_STATIC_CONFIG_BLS_HIGH /* |
-							      EMC_CONFIG_BUFFER_ENABLE*/,
-
-	EMC_NANOSECOND(0),
-	EMC_NANOSECOND(65),
-	EMC_NANOSECOND(90),
-	EMC_NANOSECOND(90),
-	EMC_NANOSECOND(35),
-	EMC_CLOCK(4)
-};
-
-/* Setup external memories */
-STATIC void SystemSetupMemory(void)
-{
-	/* Setup EMC Delays */
-	/* Move all clock delays together */
-	LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
-
-	/* Setup EMC Clock Divider for divide by 2 */
-	Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
-	LPC_CREG->CREG6 |= (1 << 16);
-	Chip_Clock_Enable(CLK_MX_EMC);
-
-	/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
-	Chip_EMC_Init(1, 0, 0);
-	/* Init EMC Dynamic Controller */
-	Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &MT48LC4M32_config);
-	/* Init EMC Static Controller CS0 */
-	Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &S29GL64N90_config);
-
-	/* Enable Buffer for External Flash */
-	LPC_EMC->STATICCONFIG0 |= 1 << 19;
-}
-
-#endif
-
-/**
- * @brief	Setup the system
- *			SystemInit() is called prior to the application and sets up system
- *			clocking, memory, and any resources needed prior to the application
- *			starting.
- * @return	none
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
-	unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
-	extern void *__vector_table;
-
-	*pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
-	extern void *g_pfnVectors;
-
-	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
-	extern void *__Vectors;
-
-	*pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
-	fpuInit();
-#endif
-
-	/* Setup system clocking and memory. This is done early to allow the
-	   application and tools to clear memory and use scatter loading to
-	   external memory. */
-	SystemSetupClocking();
-	SystemSetupMuxing();
-	SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h
deleted file mode 100644
index f23c8b21bc..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * @brief NGX Xplorer 1830/4330 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_H_
-#define __BOARD_H_
-
-#include "board_ngx_xplorer_18304330.h"
-
-#endif /* __BOARD_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c
deleted file mode 100644
index 79834b7bce..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-#include "string.h"
-
-#include "lpc_phy_smsc87x0.c"
-#include "retarget.c"
-
-/** @ingroup BOARD_NGX_XPLORER_18304330
- * @{
- */
-
-void Board_UART_Init(LPC_USART_Type *UARTx)
-{
-	if (UARTx == LPC_USART0) {
-		Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2);					/* P6.5 : UART0_TXD */
-		Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P6.4 : UART0_RXD */
-	}
-	else if (UARTx == LPC_UART1) {
-		Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2);				/* P1.13 : UART1_TXD */
-		Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P1.14 : UART1_RX */
-	}
-}
-
-/* Initialize debug output via UART for board */
-void Board_Debug_Init(void)
-{
-#if defined(DEBUG_UART)
-	Board_UART_Init(DEBUG_UART);
-
-	Chip_UART_Init(DEBUG_UART);
-	Chip_UART_SetBaud(DEBUG_UART, 115200);
-	Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
-
-	/* Enable UART Transmit */
-	Chip_UART_TxCmd(DEBUG_UART, ENABLE);
-#endif
-}
-
-/* Sends a character on the UART */
-void Board_UARTPutChar(char ch)
-{
-#if defined(DEBUG_UART)
-	while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
-#endif
-}
-
-/* Gets a character from the UART, returns EOF if no character is ready */
-int Board_UARTGetChar(void)
-{
-#if defined(DEBUG_UART)
-	uint8_t data;
-
-	if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
-		return (int) data;
-	}
-#endif
-	return EOF;
-}
-
-/* Outputs a string on the debug UART */
-void Board_UARTPutSTR(char *str)
-{
-#if defined(DEBUG_UART)
-	while (*str != '\0') {
-		Board_UARTPutChar(*str++);
-	}
-#endif
-}
-
-void Board_LED_Init()
-{
-	/* P2.12 : LED D2 as output */
-	Chip_GPIO_WriteDirBit(1, 12, true);
-
-	/* P2.11 : LED D3 as output */
-	Chip_GPIO_WriteDirBit(1, 11, true);
-
-	/* Set initial states to off (true to disable) */
-	Chip_GPIO_WritePortBit(1, 12, (bool) true);
-	Chip_GPIO_WritePortBit(1, 11, (bool) true);
-}
-
-void Board_LED_Set(uint8_t LEDNumber, bool On)
-{
-	if (LEDNumber == 0) {
-		Chip_GPIO_WritePortBit(1, 12, (bool) !On);
-	}
-	else if (LEDNumber == 1) {
-		Chip_GPIO_WritePortBit(1, 11, (bool) !On);
-	}
-}
-
-bool Board_LED_Test(uint8_t LEDNumber)
-{
-	if (LEDNumber == 0) {
-		return (bool) !Chip_GPIO_ReadPortBit(1, 12);
-	}
-	else if (LEDNumber == 1) {
-		return (bool) !Chip_GPIO_ReadPortBit(1, 11);
-	}
-
-	return false;
-}
-
-void Board_Buttons_Init(void)	// FIXME not functional ATM
-{
-	Chip_SCU_PinMux(0x2, 7, MD_PUP | MD_EZI | MD_ZI, FUNC0);		// P2_7 as GPIO0[7]
-	Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false);	// input
-}
-
-uint32_t Buttons_GetStatus(void)
-{
-	uint8_t ret = NO_BUTTON_PRESSED;
-	if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
-		ret |= BUTTONS_BUTTON1;
-	}
-	return ret;
-}
-
-void Board_Joystick_Init(void)
-{}
-
-uint8_t Joystick_GetStatus(void)
-{
-	return NO_BUTTON_PRESSED;
-}
-
-/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock;
-
-/* Update system core clock rate, should be called if the system has
-   a clock rate change */
-void SystemCoreClockUpdate(void)
-{
-	/* CPU core speed */
-	SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
-}
-
-/* Returns the MAC address assigned to this board */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr)
-{
-	uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
-
-	memcpy(mcaddr, boardmac, 6);
-}
-
-/* Set up and initialize all required blocks and functions related to the
-   board hardware */
-void Board_Init(void)
-{
-	/* Sets up DEBUG UART */
-	DEBUGINIT();
-
-	/* Updates SystemCoreClock global var with current clock speed */
-	SystemCoreClockUpdate();
-
-	/* Initializes GPIO */
-	Chip_GPIO_Init();
-
-	/* Setup GPIOs for USB demos */
-	Chip_SCU_PinMux(0x2, 6, (MD_PUP | MD_EZI), FUNC4);			/* P2_6 USB1_PWR_EN, USB1 VBus function */
-	Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2);	/* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
-	Chip_SCU_PinMux(0x1, 7, (MD_PUP | MD_EZI), FUNC4);			/* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */
-	Chip_GPIO_WriteDirBit(5, 6, true);							/* GPIO5[6] = USB1_PWR_EN */
-	Chip_GPIO_WritePortBit(5, 6, true);							/* GPIO5[6] output high */
-}
-
-void Board_I2C_Init(LPC_I2C_Type *I2Cx)
-{
-	if (I2Cx == LPC_I2C1) {
-		/* Configure pin function for I2C1*/
-		Chip_SCU_PinMux(0x2, 3, MD_ZI | MD_EZI, FUNC1);		/* P2.3 : I2C1_SDA */
-		Chip_SCU_PinMux(0x2, 4, MD_ZI | MD_EZI, FUNC1);		/* P2.4 : I2C1_SCL */
-	}
-}
-
-void GPIO0_IRQHandler(void)
-{
-	static bool On;
-
-	if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
-		Chip_GPIO_IntClear(0, 0);
-		On = (bool) !On;
-		Board_LED_Set(1, On);
-	}
-}
-
-void Board_GPIO_Int_Init()
-{
-	Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0);	/* PF.9 : POTI button */
-	Chip_GPIO_WriteDirBit(7, 23, false);						/* PF.9 -> GPIO7[23] : input */
-	Chip_SCU_GPIOIntPinSel(0, 7, 23);
-	Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE);			/* Configure GPIO0[7] to interrupt pin (SW2 switch) */
-
-	NVIC_EnableIRQ(PIN_INT0_IRQn);	/* enable GPIO interrupt 0 */
-}
-
-void Board_SDMMC_Init(void)
-{
-	Chip_SCU_PinMux(0x1, 9, MD_PLN_FAST, FUNC7);	/* P1.9 connected to SDIO_D0 */
-	Chip_SCU_PinMux(0x1, 10, MD_PLN_FAST, FUNC7);	/* P1.10 connected to SDIO_D1 */
-	Chip_SCU_PinMux(0x1, 11, MD_PLN_FAST, FUNC7);	/* P1.11 connected to SDIO_D2 */
-	Chip_SCU_PinMux(0x1, 12, MD_PLN_FAST, FUNC7);	/* P1.12 connected to SDIO_D3 */
-
-	Chip_SCU_PinMux(PINMUX_CLK, 2, MD_PLN | MD_EZI, FUNC4);	/* CLK2 connected to SDIO_CLK */
-	Chip_SCU_PinMux(0x1, 6, MD_PLN_FAST, FUNC7);	/* P1.6 connected to SDIO_CMD */
-}
-
-void Board_SSP_Init(LPC_SSP_Type *SSPx)
-{
-	if (SSPx == LPC_SSP1) {
-		/* Set up clock and power for SSP1 module */
-		/* Configure SSP1 pins*/
-		/* SCLK comes out pin CLK0 */
-		Chip_SCU_PinMux(PINMUX_CLK, 0, MD_PLN_FAST, FUNC6);		/* CLK0 connected to CLK	func6=SSP1 CLK1  */
-		Chip_SCU_PinMux(0x1, 5, MD_PLN_FAST, FUNC5);			/* P1.5 connected to nCS	func5=SSP1 SSEL1 */
-		Chip_SCU_PinMux(0x1, 3, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.3 connected to SO		func5=SSP1 MISO1 */
-		Chip_SCU_PinMux(0x1, 4, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.4 connected to nSI	func5=SSP1 MOSI1 */
-		Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
-	}
-	else {
-		return;
-	}
-}
-
-/* System Register Data Set */
-uint16_t UDA_sys_regs_dat[] = {
-	UDA1380_REG_EVALCLK_DEFAULT_VALUE,
-	UDA1380_REG_I2S_DEFAULT_VALUE,
-	UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
-	UDA1380_REG_ANAMIX_DEFAULT_VALUE,
-	UDA1380_REG_HEADAMP_DEFAULT_VALUE
-};
-
-/* System Register Data Set */
-uint16_t UDA_interfil_regs_dat[] = {
-	UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
-	UDA1380_REG_MIXVOL_DEFAULT_VALUE,
-	UDA1380_REG_MODEBBT_DEFAULT_VALUE,
-	UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
-	UDA1380_REG_MIXSDO_DEFAULT_VALUE
-};
-/* decimator Register Data Set */
-uint16_t UDA_decimator_regs_dat[] = {
-	UDA1380_REG_DECVOL_DEFAULT_VALUE,
-	UDA1380_REG_PGA_DEFAULT_VALUE,
-	UDA1380_REG_ADC_DEFAULT_VALUE,
-	UDA1380_REG_AGC_DEFAULT_VALUE
-};
-static void delay(uint32_t i) {
-	while (i--) {}
-}
-
-static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
-
-	I2C_Config->tx_data[0] = reg;
-	I2C_Config->tx_data[1] = value >> 8;
-	I2C_Config->tx_data[2] = value & 0xFF;
-	Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
-	delay(10000);
-}
-
-static uint16_t UDA_Reg_read(UDA1380_REG reg) {
-	uint8_t rx_data[2];
-	Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
-	return rx_data[0] << 8 | rx_data[1];
-}
-
-static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
-{
-	uint16_t temp;
-	uint8_t  i;
-	/* Reset UDA1380 on board NGX Xplorer */
-	Chip_SCU_PinMux(0x2, 10, MD_PUP, FUNC0);
-	Chip_GPIO_WriteDirBit(0, 14, true);
-	Chip_GPIO_WritePortBit(0, 14, true);
-	// delay 1us
-	delay(100000);
-	Chip_GPIO_WritePortBit(0, 14, false);
-	delay(100000);
-	for (i = 0; i < 5; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
-		if (temp != UDA_sys_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-
-	/* interfilter regs init */
-	for (i = 0; i < 5; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
-		if (temp != UDA_interfil_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-	/* decimator regs init */
-	for (i = 0; i < 4; i++) {
-		UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
-		if (temp != UDA_decimator_regs_dat[i]) {
-			return ERROR;
-		}
-	}
-
-	if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
-		/* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
-		UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
-		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
-			return ERROR;
-		}
-		UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
-					  UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
-					  I2C_Config);
-		temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
-		if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
-			return ERROR;
-		}
-	}
-	return SUCCESS;
-
-}
-
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
-{
-	uint8_t uda1380_tx_data_buf[3];
-	Chip_I2S_Audio_Format_Type I2S_Config;
-	I2C_M_SETUP_Type I2C_Config;
-	I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
-	I2C_Config.retransmissions_max = 5;
-	I2C_Config.tx_length = 3;
-	I2C_Config.tx_data = uda1380_tx_data_buf;
-	I2C_Config.rx_length = 0;
-	I2C_Config.rx_data = NULL;
-
-	/* Initialize I2C peripheral ------------------------------------*/
-	/* Init I2C */
-	Chip_I2C_Init(LPC_I2C0);
-	Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
-	I2S_Config.SampleRate = 48000;
-	I2S_Config.ChannelNumber = 2;		/* 1 is mono, 2 is stereo */
-	I2S_Config.WordWidth =  16;			/* 8, 16 or 32 bits */
-	Chip_I2S_Init(LPC_I2S0);
-	Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
-	/* Enable Slave I2C operation */
-	Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
-	/* Init UDA1380 CODEC */
-	while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
-
-}
-
-/* FIXME Should we remove this function? */
-void Serial_CreateStream(void *Stream)
-{}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h
deleted file mode 100644
index ee9fa0cf90..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * @brief NGX Xplorer 1830/4330 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_NGX_XPLORER_18304330_H_
-#define __BOARD_NGX_XPLORER_18304330_H_
-
-#include "chip.h"
-#include "board_api.h"
-#include "lpc_phy.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions
- * @ingroup BOARDS_18XX_43XX
- * @{
- */
-
-/** @defgroup BOARD_NGX_XPLORER_18304330_OPTIONS BOARD: LPC1830 and LPC4330 NGX Xplorer board builds options
- * The NGX board has options that configure it's operation at build-time.<br/>
- * CHIP_LPC*
- *  - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
- * DEBUG:<br/>
- * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART<br/>
- * - When not defined, DEBUGOUT and DEBUGSTR are null functions<br/><p>
- * DEBUG_UART:<br/>
- *  - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0<br/><p>
- * CRYSTAL_MAIN_FREQ_IN:<br/>
- *  - This define specifies the crystal input clock into the chip, example: 12000000<br/><p>
- * CRYSTAL_32K_FREQ_IN:<br/>
- *  - This define specifies the RTC crystal input clock into the chip, example: 32768<br/><p>
- * EXTERNAL_CLKIN_FREQ_IN:<br/>
- *  - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000<br/><p>
- * MAX_CLOCK_FREQ:<br/>
- *  - When defined, this will be used to configure the CPU clock rate, example: 150000000<br/>
- *  - When not defined, the system will use the maximum CPU clokc rate<br/><p>
- * BOARD_HITEX_EVA_18504350:<br/>
- *  - When building for NGX boards, BOARD_NGX_XPLORER_18304330 is defined<br/>
- * <br/><p>
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
- * @{
- */
-
-/**
- * @}
- */
-
-#define BOARD_NGX_XPLORER_18304330
-
-#define I2CDEV_UDA1380_ADDR     (0x34 >> 1)
-
-#define UDA1380_REG_EVALCLK_DEFAULT_VALUE   (0xF << 8 | 0x3 << 4 | 1 << 1)
-#define UDA1380_REG_I2S_DEFAULT_VALUE           0x0000
-
-#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE   (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
-#define UDA1380_REG_ANAMIX_DEFAULT_VALUE    0x0000
-#define UDA1380_REG_HEADAMP_DEFAULT_VALUE   ( 1 << 9 | 2)
-
-#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE   0x0000
-#define UDA1380_REG_MIXVOL_DEFAULT_VALUE    0x0000
-#define UDA1380_REG_MODEBBT_DEFAULT_VALUE   0x0000
-#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE  (2 << 8 | 2)
-#define UDA1380_REG_MIXSDO_DEFAULT_VALUE      0x0000
-
-#define UDA1380_REG_DECVOL_DEFAULT_VALUE     0xE4E4			/* Decrease Volume -28dB */
-#define UDA1380_REG_PGA_DEFAULT_VALUE         0x0000
-#define UDA1380_REG_ADC_DEFAULT_VALUE         0x0001			/* Apply 0bB VGA Gain, enable DC Filter */
-#define UDA1380_REG_AGC_DEFAULT_VALUE         0x0000
-#define UDA1380_REG_L3_DEFAULT_VALUE          0x0000
-
-/* For USBLIB examples */
-#define LEDS_LED1           0x01
-#define LEDS_LED2           0x02
-#define LEDS_LED3           0x04
-#define LEDS_LED4           0x08
-#define LEDS_NO_LEDS        0x00
-#define BUTTONS_BUTTON1     0x01
-#define JOY_UP              0x01
-#define JOY_DOWN            0x02
-#define JOY_LEFT            0x04
-#define JOY_RIGHT           0x08
-#define JOY_PRESS           0x10
-#define NO_BUTTON_PRESSED   0x00
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM   0
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM    7
-#define LED1_GPIO_PORT_NUM              1
-#define LED1_GPIO_BIT_NUM               11
-#define LED2_GPIO_PORT_NUM              1
-#define LED2_GPIO_BIT_NUM               12
-
-typedef enum {
-	MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
-	MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
-} Board_Audio_Input_Sel_Type;
-
-/* UDA1380 Register Address */
-typedef enum {
-	UDA_EVALM_CLK = 0x00,
-	UDA_BUS_CTRL,
-	UDA_POWER_CTRL,
-	UDA_ANALOG_CTRL,
-	UDA_HPAMP_CTRL,
-	UDA_MASTER_VOL_CTRL = 0x10,
-	UDA_MIXER_VOL_CTRL,
-	UDA_MODE_CTRL,
-	UDA_MUTE_CTRL,
-	UDA_MIXER_FILTER_CTRL,
-	UDA_DEC_VOL_CTRL = 0x20,
-	UDA_PGA_CTRL,
-	UDA_ADC_CTRL,
-	UDA_AGC_CTRL,
-	UDA_TOTAL_REG
-} UDA1380_REG;
-
-/**
- * @brief	Sets up board specific I2C interface
- * @param	I2Cx	: Pointer to I2C interface to initialize
- * @return	Nothing
- */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Initializes board specific GPIO Interrupt
- * @return	Nothing
- */
-void Board_GPIO_Int_Init(void);
-
-/**
- * @brief	Initialize pin muxing for SSP interface
- * @param	SSPx	: Pointer to SSP interface to initialize
- * @return	Nothing
- */
-void Board_SSP_Init(LPC_SSP_Type *SSPx);
-
-/**
- * @brief	Returns the MAC address assigned to this board
- * @param	mcaddr : Pointer to 6-byte character array to populate with MAC address
- * @return	Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief	Initialize pin muxing for a UART
- * @param	UARTx	: Pointer to UART register block for UART pins to init
- * @return	Nothing
- */
-void Board_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief	Initialize pin muxing for SDMMC interface
- * @return	Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief	Initialize button(s) interface on board
- * @return	Nothing
- */
-void Board_Buttons_Init(void);
-
-/**
- * @brief	Initialize joystick interface on board
- * @return	Nothing
- */
-void Board_Joystick_Init(void);
-
-/**
- * @brief	Returns joystick states on board
- * @return	Returns a JOY_* value, ir JOY_PRESS or JOY_UP
- */
-uint8_t Joystick_GetStatus(void);
-
-/**
- * @brief	Returns button(s) state on board
- * @return	Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus (void);
-
-/**
- * @brief	Initialize I2S interface for the board and UDA1380
- * @param	I2Sx			: Pointer to I2S register interface used on this board
- * @param	audio_in_sel	: Audio input selection
- * @return	Nothing
- */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
-
-/**
- * @brief	FIXME
- * @param	Stream	: FIXME
- * @return	Nothing
- */
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_NGX_XPLORER_18304330_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h
deleted file mode 100644
index 387e8620f0..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC18XX
-
-/* Enable DEBUG for IO support via the UART */
-// #define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
-   via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h
deleted file mode 100644
index 13b676019f..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC43XX
-
-/* Enable DEBUG for IO support via the UART */
-// #define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
-   via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0	/* No port on Xplorer */
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (204000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c
deleted file mode 100644
index 7668a7c2c4..0000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code
- * @ingroup BOARD_NGX_XPLORER_18304330
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the NGX Xplorer boards includes clock setup and default pin muxing
- * configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1830 and LPC4330 NGX Xplorer setup<BR>
- *  Clocking:<BR>
- *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>
- *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>
- *   SPIFI FLASH clock setup for fastest speed<BR>
- *  Pin muxing:<BR>
- *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>
- *  Memory:<BR>
- *   There is no memory setup for this board.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
-	uint8_t pingrp;	/* Pin group */
-	uint8_t pinnum;	/* Pin number */
-	uint8_t pincfg;	/* Pin configuration for SCU */
-	uint8_t funcnum;/* Function number */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
-	CGU_BASE_CLK_T clk;	/* Base clock */
-	CGU_CLKIN_T clkin;	/* Base clock source, see UM for allowable souorces per base clock */
-	bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
-	bool powerdn;		/* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
-	{CLK_BASE_SAFE, CLKIN_IRC, true, false},
-	{CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_USB0, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
-#endif
-	{CLK_BASE_USB1, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
-#endif
-	{CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
-	{CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
-	{CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
-	{CLK_BASE_LCD, CLKIN_MAINPLL, false, true},
-#if defined(CHIP_LPC43XX)
-	{CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
-	{CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
-	{CLK_BASE_OUT, CLKINPUT_PD, true, false},
-	{CLK_BASE_APLL, CLKINPUT_PD, true, false},
-	{CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
-	{CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
-	{0x3, 3,  (MD_PLN_FAST),  FUNC3},	/* SPIFI CLK */
-	{0x3, 4,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D3 */
-	{0x3, 5,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D2 */
-	{0x3, 6,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D1 */
-	{0x3, 7,  (MD_PLN_FAST),  FUNC3},	/* SPIFI D0 */
-	{0x3, 8,  (MD_PLN_FAST),  FUNC3}	/* SPIFI CS/SSEL */
-};
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
-	int i;
-
-	/* Switch main system clocking to crystal */
-	Chip_Clock_EnableCrystal();
-	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
-	/* Setup PLL for 100MHz and switch main system clocking */
-	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
-	Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
-	/* Setup PLL for maximum clock */
-	Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
-	/* Setup system base clocks and initial states. This won't enable and
-	   disable individual clocks, but sets up the base clock sources for
-	   each individual peripheral clock. */
-	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
-		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
-								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
-	}
-
-	/* Reset and enable 32Khz oscillator */
-	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
-	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
-	/* SPIFI pin setup is done prior to setting up system clocking */
-	for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
-		Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
-						spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
-	}
-
-	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
-	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
-	/* RMII pin group */
-	{0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
-	{0x0, 0,  (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC2},
-	{0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC7},
-	{0x0, 1,  (MD_EHS | MD_PLN | MD_ZI),           FUNC6},
-	{0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC0},
-	{0x1, 18, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 20, (MD_EHS | MD_PLN | MD_ZI),           FUNC3},
-	{0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI),  FUNC3},
-	{0x2, 0,  (MD_EHS | MD_PLN | MD_ZI),           FUNC7},
-	/* Board LEDs */
-	{0x2, 11, MD_PDN,                              FUNC0},
-	{0x2, 12, MD_PDN,                              FUNC0},
-	/*  I2S  */
-	{0x3, 0,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 0,  MD_PLN_FAST,                         FUNC4},
-	{0x7, 2,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 2,  MD_PLN_FAST,                         FUNC3},
-	{0x7, 1,  MD_PLN_FAST,                         FUNC2},
-	{0x6, 1,  MD_PLN_FAST,                         FUNC3},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
-	int i;
-
-	/* Setup system level pin muxing */
-	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
-		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
-						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
-	}
-}
-
-/* Nothing to do for the Xplorer board */
-STATIC void SystemSetupMemory(void)
-{}
-
-#endif
-
-/**
- * @brief	Setup the system
- * @return	none
- * SystemInit() is called prior to the application and sets up system
- * clocking, memory, and any resources needed prior to the application
- * starting.
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
-	volatile unsigned int *pSCB_VTOR = (volatile unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
-	extern void *__vector_table;
-
-	*pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
-	extern void *g_pfnVectors;
-
-	*pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
-	extern void *__Vectors;
-
-	*pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
-	fpuInit();
-#endif
-
-	/* Setup system clocking and memory. This is done early to allow the
-	   application and tools to clear memory and use scatter loading to
-	   external memory. */
-	SystemSetupClocking();
-	SystemSetupMuxing();
-	SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/SConscript b/bsp/xplorer4330/libraries/lpc_chip/SConscript
deleted file mode 100644
index a3b3fe12df..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/SConscript
+++ /dev/null
@@ -1,15 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-
-src = Glob('chip_18xx_43xx/*.c')
-src += Glob('chip_common/*.c')
-
-path = [cwd + '/chip_18xx_43xx',
-        cwd + '/chip_common']
-
-group = DefineGroup('lpc_chip', src, depend = [], CPPPATH = path)
-
-Return('group')
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c
deleted file mode 100644
index 38f2ba0cd7..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * @brief LPC18xx/43xx A/D conversion driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "adc_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*The channel to be operated on */
-static uint8_t active_channel;
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Returns the clock for the selected ADC */
-static CCU_CLK_T Chip_ADC_GetClk(LPC_ADC_Type *pADC)
-{
-	CCU_CLK_T adcclk;
-
-	if (pADC == LPC_ADC0) {
-		adcclk = CLK_APB3_ADC0;
-	}
-	else {
-		adcclk = CLK_APB3_ADC1;
-	}
-
-	return adcclk;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the ADC peripheral and the ADC setup structure to default value */
-void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup)
-{
-	CCU_CLK_T adcclk = Chip_ADC_GetClk(pADC);
-
-	/* Enable ADC clocking */
-	Chip_Clock_EnableOpts(adcclk, true, true, 1);
-	ADCSetup->adcPerClock = Chip_Clock_GetRate(adcclk);
-
-	ADCSetup->adcRate = 400000;
-	ADCSetup->bitsAccuracy = ADC_10BITS;
-	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
-}
-
-/* Select the mode starting the AD conversion */
-void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption)
-{
-	if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
-		IP_ADC_EdgeStartConfig(pADC, (uint8_t) EdgeOption);
-	}
-	IP_ADC_SetStartMode(pADC, (uint8_t) mode);
-}
-
-/* Set the ADC Sample rate */
-void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate)
-{
-	ADCSetup->adcRate = rate;
-	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
-
-}
-
-/* Set the ADC accuracy bits */
-void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution)
-{
-	ADCSetup->bitsAccuracy = resolution;
-	IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
-}
-
-/* Enable or disable the ADC channel on ADC peripheral */
-void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState)
-{
-	IP_ADC_SetChannelNumber(pADC, channel, NewState);
-	active_channel = channel;
-}
-
-/* Enable burst mode */
-void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
-{
-	IP_ADC_SetStartMode(pADC, ADC_NO_START);
-	IP_ADC_SetBurstMode(pADC, NewState);
-}
-
-/* Read the ADC value and convert it to 8bits value */
-Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data)
-{
-	uint16_t temp;
-	Status rt;
-
-	rt = IP_ADC_Get_Val(pADC, active_channel, &temp);
-	*data = (uint8_t) temp;
-
-	return rt;
-}
-
-/* Set a channel to be read A/D data */
-void Chip_ADC_Active_Channel(uint8_t channel)
-{
-	active_channel = channel;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h
deleted file mode 100644
index f71df0a321..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * @brief LPC18xx/43xx A/D conversion driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ADC_18XX_43XX_H_
-#define __ADC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** The channels on one ADC peripheral*/
-typedef enum ADC_Channel {
-	ADC_CH0 = 0,	/**< ADC channel 0 */
-	ADC_CH1,		/**< ADC channel 1 */
-	ADC_CH2,		/**< ADC channel 2 */
-	ADC_CH3,		/**< ADC channel 3 */
-	ADC_CH4,		/**< ADC channel 4 */
-	ADC_CH5,		/**< ADC channel 5 */
-	ADC_CH6,		/**< ADC channel 6 */
-	ADC_CH7,		/**< ADC channel 7 */
-} ADC_Channel;
-
-/** The number of bits of accuracy of the result in the LS bits of ADDR*/
-typedef enum ADC_Resolution {
-	ADC_10BITS = 0,		/**< ADC 10 bits */
-	ADC_9BITS,			/**< ADC 9 bits  */
-	ADC_8BITS,			/**< ADC 8 bits  */
-	ADC_7BITS,			/**< ADC 7 bits  */
-	ADC_6BITS,			/**< ADC 6 bits  */
-	ADC_5BITS,			/**< ADC 5 bits  */
-	ADC_4BITS,			/**< ADC 4 bits  */
-	ADC_3BITS,			/**< ADC 3 bits  */
-} ADC_Resolution;
-
-/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
-typedef enum ADC_EdgeCfg {
-	ADC_TRIGGERMODE_RISING = 0,		/**< Trigger event: rising edge */
-	ADC_TRIGGERMODE_FALLING,		/**< Trigger event: falling edge */
-} ADC_EdgeCfg;
-
-/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
-typedef enum ADC_StartMode {
-	ADC_NO_START = 0,
-	ADC_START_NOW,			/*!< Start conversion now */
-	ADC_START_ON_CTOUT15,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
-	ADC_START_ON_CTOUT8,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
-	ADC_START_ON_ADCTRIG0,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
-	ADC_START_ON_ADCTRIG1,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
-	ADC_START_ON_MCOA2		/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-} ADC_StartMode;
-
-/** Clock setup structure for ADC controller passed to the initialize function */
-typedef struct {
-	uint32_t adcPerClock;	/*!< ADC peripheral Clock */
-	uint32_t adcRate;		/*!< ADC rate */
-	uint8_t  bitsAccuracy;	/*!< ADC bit accuracy */
-} ADC_Clock_Setup_Type;
-
-/**
- * @brief	Read the ADC value from a channel
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: ADC channel to read
- * @param	data		: Pointer to where to put data
- * @return	SUCCESS or ERROR if no conversion is ready
- */
-STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_Type *pADC, uint8_t channel, uint16_t *data)
-{
-	return IP_ADC_Get_Val(pADC, channel, data);
-}
-
-/**
- * @brief	Read the ADC channel status
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: ADC channel to read
- * @param	StatusType	: Status type of ADC_DR_*
- * @return	SET or RESET
- */
-STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_Type *pADC, uint8_t channel, uint32_t StatusType)
-{
-	return IP_ADC_GetStatus(pADC, channel, StatusType);
-}
-
-/**
- * @brief	Enable/Disable interrupt for ADC channel
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: ADC channel to read
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	SET or RESET
- */
-STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_Type *pADC, uint8_t channel, FunctionalState NewState)
-{
-	IP_ADC_Int_Enable(pADC, channel, NewState);
-}
-
-/**
- * @brief	Enable/Disable global interrupt for ADC channel
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	Nothing
- */
-STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
-{
-	IP_ADC_Int_Enable(pADC, 8, NewState);
-}
-
-/**
- * @brief	Shutdown ADC
- * @param	pADC	: The base of ADC peripheral on the chip
- * @return	Nothing
- */
-STATIC INLINE void Chip_ADC_DeInit(LPC_ADC_Type *pADC)
-{
-	IP_ADC_DeInit(pADC);
-}
-
-/**
- * @brief	Initialize the ADC peripheral and the ADC setup structure to default value
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	ADCSetup	: ADC setup structure to be set
- * @return	Nothing
- * Default setting for ADC is 400kHz - 10bits
- */
-void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup);
-
-/**
- * @brief	Select the mode starting the AD conversion
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	mode		: Stating mode, should be :
- *							- ADC_NO_START				: Must be set for Burst mode
- *							- ADC_START_NOW				: Start conversion now
- *							- ADC_START_ON_CTOUT15		: Start conversion when the edge selected by bit 27 occurs on CTOUT_15
- *							- ADC_START_ON_CTOUT8		: Start conversion when the edge selected by bit 27 occurs on CTOUT_8
- *							- ADC_START_ON_ADCTRIG0		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
- *							- ADC_START_ON_ADCTRIG1		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
- *							- ADC_START_ON_MCOA2		: Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
- * @param	EdgeOption	: Stating Edge Condition, should be :
- *							- ADC_TRIGGERMODE_RISING	: Trigger event on rising edge
- *							- ADC_TRIGGERMODE_FALLING	: Trigger event on falling edge
- * @return	Nothing
- */
-void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption);
-
-/**
- * @brief	Set the ADC Sample rate
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	ADCSetup	: ADC setup structure to be modified
- * @param	rate		: Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
- * @return	Nothing
- */
-void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate);
-
-/**
- * @brief	Set the ADC accuracy bits
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	ADCSetup	: ADC setup structure to be modified
- * @param	resolution	: The resolution, should be ADC_10BITS -> ADC_3BITS
- * @return	Nothing
- */
-void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution);
-
-/**
- * @brief	Enable or disable the ADC channel on ADC peripheral
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: Channel to be enable or disable
- * @param	NewState	: New state, should be:
- *								- ENABLE
- *								- DISABLE
- * @return	Nothing
- */
-void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState);
-
-/**
- * @brief	Enable burst mode
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	NewState	: New state, should be:
- *							- ENABLE
- *							- DISABLE
- * @return	Nothing
- */
-void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState);
-
-/**
- * @brief	Read the ADC value and convert it to 8bits value
- * @param	pADC	: The base of ADC peripheral on the chip
- * @param	data	: Storage for data
- * @return	Status	: ERROR or SUCCESS
- */
-Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data);
-
-/**
- * @brief	Set a channel to be read A/D data
- * @param	channel	: Channel to be active
- * @return	Nothing
- */
-void Chip_ADC_Active_Channel(uint8_t channel);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ADC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c
deleted file mode 100644
index 0fe1b6cae5..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * @brief LPC18xx/43xx ATimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "atimer_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize Alarm Timer */
-void Chip_ATIMER_Init(uint32_t PresetValue)
-{
-	Chip_ATIMER_UpdatePresetValue(PresetValue);
-	Chip_ATIMER_ClearIntStatus();
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h
deleted file mode 100644
index 230efc144f..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * @brief LPC18xx/43xx ATimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ATIMER_18XX_43XX_H_
-#define __ATIMER_18XX_43XX_H_
-
-#include "chip.h"
-
-/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Initialize Alarm Timer
- * @param PresetValue Count of 1 to 1024s for Alarm
- * @return	None
- */
-void Chip_ATIMER_Init(uint32_t PresetValue);
-
-/**
- * @brief	Close ATIMER device
- * @return	None
- */
-STATIC INLINE void Chip_ATIMER_DeInit(void)
-{
-	IP_ATIMER_DeInit(LPC_ATIMER);
-}
-
-/**
- * @brief	Enable ATIMER Interrupt
- * @return	None
- */
-STATIC INLINE void Chip_ATIMER_IntEnable(void)
-{
-	IP_ATIMER_IntEnable(LPC_ATIMER);
-}
-
-/**
- * @brief	Disable ATIMER Interrupt
- * @return	None
- */
-STATIC INLINE void Chip_ATIMER_IntDisable(void)
-{
-	IP_ATIMER_IntDisable(LPC_ATIMER);
-}
-
-/**
- * @brief	Clear ATIMER Interrupt Status
- * @return	None
- */
-STATIC INLINE void Chip_ATIMER_ClearIntStatus(void)
-{
-	IP_ATIMER_ClearIntStatus(LPC_ATIMER);
-}
-
-/**
- * @brief	Set ATIMER Interrupt Status
- * @return	None
- */
-STATIC INLINE void Chip_ATIMER_SetIntStatus(void)
-{
-	IP_ATIMER_SetIntStatus(LPC_ATIMER);
-}
-
-/**
- * @brief	Update Preset value
- * @param	PresetValue	: updated preset value
- * @return	Nothing
- */
-STATIC INLINE void Chip_ATIMER_UpdatePresetValue(uint32_t PresetValue)
-{
-	IP_ATIMER_UpdatePresetValue(LPC_ATIMER, PresetValue);
-}
-
-/**
- * @brief	Read value of preset register
- * @return	Value of capture register
- */
-STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(void)
-{
-	return IP_ATIMER_GetPresetValue(LPC_ATIMER);
-}
-
-/**
- * @}
- */
-
- #endif /* __ATIMER_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h
deleted file mode 100644
index 0881405f39..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * @brief CGU/CCU registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CGUCCU_18XX_43XX_H_
-#define __CGUCCU_18XX_43XX_H_
-
-#include "cmsis.h"
-#include "chip_clocks.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup CLOCK_18XX_43XX
- * @{
- */
-
-/**
- * @brief LPC18XX/43XX CGU register block structure
- */
-typedef struct {							/*!< (@ 0x40050000) CGU Structure          */
-	__I  uint32_t  RESERVED0[5];
-	__IO uint32_t  FREQ_MON;				/*!< (@ 0x40050014) Frequency monitor register */
-	__IO uint32_t  XTAL_OSC_CTRL;			/*!< (@ 0x40050018) Crystal oscillator control register */
-	__I  uint32_t  PLL0USB_STAT;			/*!< (@ 0x4005001C) PLL0 (USB) status register */
-	__IO uint32_t  PLL0USB_CTRL;			/*!< (@ 0x40050020) PLL0 (USB) control register */
-	__IO uint32_t  PLL0USB_MDIV;			/*!< (@ 0x40050024) PLL0 (USB) M-divider register */
-	__IO uint32_t  PLL0USB_NP_DIV;			/*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
-	__I  uint32_t  PLL0AUDIO_STAT;			/*!< (@ 0x4005002C) PLL0 (audio) status register */
-	__IO uint32_t  PLL0AUDIO_CTRL;			/*!< (@ 0x40050030) PLL0 (audio) control register */
-	__IO uint32_t  PLL0AUDIO_MDIV;			/*!< (@ 0x40050034) PLL0 (audio) M-divider register */
-	__IO uint32_t  PLL0AUDIO_NP_DIV;		/*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
-	__IO uint32_t  PLL0AUDIO_FRAC;			/*!< (@ 0x4005003C) PLL0 (audio)           */
-	__I  uint32_t  PLL1_STAT;				/*!< (@ 0x40050040) PLL1 status register   */
-	__IO uint32_t  PLL1_CTRL;				/*!< (@ 0x40050044) PLL1 control register  */
-	__IO uint32_t  IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
-	__IO uint32_t  BASE_CLK[CLK_BASE_LAST];	/*!< (@ 0x4005005C) Start of base clock registers */
-} LPC_CGU_T;
-
-/**
- * @brief CCU clock config/status register pair
- */
-typedef struct {
-	__IO uint32_t  CFG;						/*!< CCU clock configuration register */
-	__I  uint32_t  STAT;					/*!< CCU clock status register */
-} CCU_CFGSTAT_T;
-
-/**
- * @brief CCU1 register block structure
- */
-typedef struct {							/*!< (@ 0x40051000) CCU1 Structure         */
-	__IO uint32_t  PM;						/*!< (@ 0x40051000) CCU1 power mode register */
-	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40051004) CCU1 base clocks status register */
-	__I  uint32_t  RESERVED0[62];
-	CCU_CFGSTAT_T  CLKCCU[CLK_CCU1_LAST];	/*!< (@ 0x40051100) Start of CCU1 clock registers */
-} LPC_CCU1_Type;
-
-/**
- * @brief CCU2 register block structure
- */
-typedef struct {							/*!< (@ 0x40052000) CCU2 Structure         */
-	__IO uint32_t  PM;						/*!< (@ 0x40052000) Power mode register    */
-	__I  uint32_t  BASE_STAT;				/*!< (@ 0x40052004) CCU base clocks status register */
-	__I  uint32_t  RESERVED0[62];
-	CCU_CFGSTAT_T  CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST];	/*!< (@ 0x40052100) Start of CCU2 clock registers */
-} LPC_CCU2_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CGUCCU_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h
deleted file mode 100644
index acbe37a683..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * @brief Chip inclusion selector file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_H_
-#define __CHIP_H_
-
-#include "sys_config.h"
-
-#if defined(CHIP_LPC18XX)
-#include "chip_lpc18xx.h"
-
-#elif defined(CHIP_LPC43XX)
-#include "chip_lpc43xx.h"
-
-#else
-#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
-#endif
-
-#endif /* __CHIP_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox
deleted file mode 100644
index 3af83bda0a..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * @brief LPCOpen 18xx/43xx chip group page
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-/** @defgroup CHIP_18XX_43XX_Drivers LPC18XX/43XX chip specific drivers
- * @ingroup Chip_Drivers
- * @{
- */
-
-/** @defgroup CHIP_18XX_43XX_DRIVER_OPTIONS CHIP: LPC18XX/43XX Chip driver build time options
- * Some chip drivers require build-time configuration. Using a build-time
- * configuration option allows the driver to be smaller and faster. A
- * build-time option is configured by the use of a definition passed to
- * the compiler during the build.
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h
deleted file mode 100644
index aeb51f7354..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * @brief	LPC18xx/43xx chip clock list used by CGU and CCU drivers
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_CLOCKS_H_
-#define __CHIP_CLOCKS_H_
-
-#include "sys_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup CLOCK_18XX_43XX
- * @{
- */
-
-/**
- * @brief CGU clock input list
- * These are possible input clocks for the CGU and can come
- * from both external (crystal) and internal (PLL) sources. These
- * clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T).
- */
-typedef enum {
-	CLKIN_32K,		/*!< External 32KHz input */
-	CLKIN_IRC,		/*!< Internal IRC (12MHz) input */
-	CLKIN_ENET_RX,	/*!< External ENET_RX pin input */
-	CLKIN_ENET_TX,	/*!< External ENET_TX pin input */
-	CLKIN_CLKIN,	/*!< External GPCLKIN pin input */
-	CLKIN_RESERVED1,
-	CLKIN_CRYSTAL,	/*!< External (main) crystal pin input */
-	CLKIN_USBPLL,	/*!< Internal USB PLL input */
-	CLKIN_AUDIOPLL,	/*!< Internal Audio PLL input */
-	CLKIN_MAINPLL,	/*!< Internal Main PLL input */
-	CLKIN_RESERVED2,
-	CLKIN_RESERVED3,
-	CLKIN_IDIVA,	/*!< Internal divider A input */
-	CLKIN_IDIVB,	/*!< Internal divider B input */
-	CLKIN_IDIVC,	/*!< Internal divider C input */
-	CLKIN_IDIVD,	/*!< Internal divider D input */
-	CLKIN_IDIVE,	/*!< Internal divider E input */
-	CLKINPUT_PD		/*!< External 32KHz input */
-} CGU_CLKIN_T;
-
-/**
- * @brief CGU base clocks
- * CGU base clocks are clocks that are associated with a single input clock
- * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
- * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
- * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
- * CLK_PERIPH_SGPIO periphral clocks.
- */
-typedef enum {
-	CLK_BASE_SAFE,		/*!< Base clock for WDT oscillator, IRC input only */
-	CLK_BASE_USB0,		/*!< Base USB clock for USB0, USB PLL input only */
-#if defined(CHIP_LPC43XX)
-	CLK_BASE_PERIPH,	/*!< Base clock for SGPIO */
-#else
-	CLK_BASE_RESERVED1,
-#endif
-	CLK_BASE_USB1,		/*!< Base USB clock for USB1 */
-	CLK_BASE_MX,		/*!< Base clock for CPU core */
-	CLK_BASE_SPIFI,		/*!< Base clock for SPIFI */
-#if defined(CHIP_LPC43XX)
-	CLK_BASE_SPI,		/*!< Base clock for SPI */
-#else
-	CLK_BASE_RESERVED2,
-#endif
-	CLK_BASE_PHY_RX,	/*!< Base clock for PHY RX */
-	CLK_BASE_PHY_TX,	/*!< Base clock for PHY TX */
-	CLK_BASE_APB1,		/*!< Base clock for APB1 group */
-	CLK_BASE_APB3,		/*!< Base clock for APB3 group */
-	CLK_BASE_LCD,		/*!< Base clock for LCD pixel clock */
-#if defined(CHIP_LPC43XX)
-	CLK_BASE_VADC,		/*!< Base clock for VADC */
-#else
-	CLK_BASE_RESERVED3,
-#endif
-	CLK_BASE_SDIO,		/*!< Base clock for SDIO */
-	CLK_BASE_SSP0,		/*!< Base clock for SSP0 */
-	CLK_BASE_SSP1,		/*!< Base clock for SSP1 */
-	CLK_BASE_UART0,		/*!< Base clock for UART0 */
-	CLK_BASE_UART1,		/*!< Base clock for UART1 */
-	CLK_BASE_UART2,		/*!< Base clock for UART2 */
-	CLK_BASE_UART3,		/*!< Base clock for UART3 */
-	CLK_BASE_OUT,		/*!< Base clock for CLKOUT pin */
-	CLK_BASE_RESERVED4,
-	CLK_BASE_RESERVED5,
-	CLK_BASE_RESERVED6,
-	CLK_BASE_RESERVED7,
-	CLK_BASE_APLL,		/*!< Base clock for audio PLL */
-	CLK_BASE_CGU_OUT0,	/*!< Base clock for CGUOUT0 pin */
-	CLK_BASE_CGU_OUT1,	/*!< Base clock for CGUOUT1 pin */
-	CLK_BASE_LAST,
-	CLK_BASE_NONE = CLK_BASE_LAST
-} CGU_BASE_CLK_T;
-
-/**
- * @brief CGU dividers
- * CGU dividers provide an extra clock state where a specific clock can be
- * divided before being routed to a peripheral group. A divider accepts an
- * input clock and then divides it. To use the divided clock for a base clock
- * group, use the divider as the input clock for the base clock (for example,
- * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
- */
-typedef enum {
-	CLK_IDIV_A,		/*!< CGU clock divider A */
-	CLK_IDIV_B,		/*!< CGU clock divider B */
-	CLK_IDIV_C,		/*!< CGU clock divider A */
-	CLK_IDIV_D,		/*!< CGU clock divider D */
-	CLK_IDIV_E,		/*!< CGU clock divider E */
-	CLK_IDIV_LAST
-} CGU_IDIV_T;
-
-/**
- * @brief Peripheral clocks
- * Peripheral clocks are individual clocks routed to peripherals. Although
- * multiple peripherals may share a same base clock, each peripheral's clock
- * can be enabled or disabled individually. Some peripheral clocks also have
- * additional dividers associated with them.
- */
-typedef enum {
-	/* CCU1 clocks */
-	CLK_APB3_BUS,		/*!< APB3 bus clock from base clock CLK_BASE_APB3 */
-	CLK_APB3_I2C1,		/*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
-	CLK_APB3_DAC,		/*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
-	CLK_APB3_ADC0,		/*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
-	CLK_APB3_ADC1,		/*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
-	CLK_APB3_CAN0,		/*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
-	CLK_APB1_BUS = 32,	/*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
-	CLK_APB1_MOTOCON,	/*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
-	CLK_APB1_I2C0,		/*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
-	CLK_APB1_I2S,		/*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
-	CLK_APB1_CAN1,		/*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
-	CLK_SPIFI = 64,		/*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
-	CLK_MX_BUS = 96,	/*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
-	CLK_MX_SPIFI,		/*!< SPIFI register clock from base clock CLK_BASE_MX */
-	CLK_MX_GPIO,		/*!< GPIO register clock from base clock CLK_BASE_MX */
-	CLK_MX_LCD,			/*!< LCD register clock from base clock CLK_BASE_MX */
-	CLK_MX_ETHERNET,	/*!< ETHERNET register clock from base clock CLK_BASE_MX */
-	CLK_MX_USB0,		/*!< USB0 register clock from base clock CLK_BASE_MX */
-	CLK_MX_EMC,			/*!< EMC clock from base clock CLK_BASE_MX */
-	CLK_MX_SDIO,		/*!< SDIO register clock from base clock CLK_BASE_MX */
-	CLK_MX_DMA,			/*!< DMA register clock from base clock CLK_BASE_MX */
-	CLK_MX_MXCORE,		/*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
-	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
-	CLK_MX_SCT,			/*!< SCT register clock from base clock CLK_BASE_MX */
-	CLK_MX_USB1,		/*!< USB1 register clock from base clock CLK_BASE_MX */
-	CLK_MX_EMC_DIV,		/*!< ENC divider clock from base clock CLK_BASE_MX */
-	CLK_MX_FLASHA,		/*!< FLASHA bank clock from base clock CLK_BASE_MX */
-	CLK_MX_FLASHB,		/*!< FLASHB bank clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
-	CLK_M4_M0APP,		/*!< M0 app CPU core clock from base clock CLK_BASE_MX */
-	CLK_MX_VADC,		/*!< VADC clock from base clock CLK_BASE_MX */
-#else
-	CLK_RESERVED1,
-	CLK_RESERVED2,
-#endif
-	CLK_MX_EEPROM,		/*!< EEPROM clock from base clock CLK_BASE_MX */
-	CLK_MX_WWDT = 128,	/*!< WWDT register clock from base clock CLK_BASE_MX */
-	CLK_MX_UART0,		/*!< UART0 register clock from base clock CLK_BASE_MX */
-	CLK_MX_UART1,		/*!< UART1 register clock from base clock CLK_BASE_MX */
-	CLK_MX_SSP0,		/*!< SSP0 register clock from base clock CLK_BASE_MX */
-	CLK_MX_TIMER0,		/*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
-	CLK_MX_TIMER1,		/*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
-	CLK_MX_SCU,			/*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
-	CLK_MX_CREG,		/*!< CREG clock from base clock CLK_BASE_MX */
-	CLK_MX_RITIMER = 160,	/*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
-	CLK_MX_UART2,		/*!< UART3 register clock from base clock CLK_BASE_MX */
-	CLK_MX_UART3,		/*!< UART4 register clock from base clock CLK_BASE_MX */
-	CLK_MX_TIMER2,		/*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
-	CLK_MX_TIMER3,		/*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
-	CLK_MX_SSP1,		/*!< SSP1 register clock from base clock CLK_BASE_MX */
-	CLK_MX_QEI,			/*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
-	CLK_PERIPH_BUS = 192,	/*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
-	CLK_RESERVED3,
-	CLK_PERIPH_CORE,	/*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
-	CLK_PERIPH_SGPIO,	/*!< SGPIO clock from base clock CLK_BASE_PERIPH */
-#else
-	CLK_RESERVED3 = 192,
-	CLK_RESERVED3A,
-	CLK_RESERVED4,
-	CLK_RESERVED5,
-#endif
-	CLK_USB0 = 224,			/*!< USB0 clock from base clock CLK_BASE_USB0 */
-	CLK_USB1 = 256,			/*!< USB1 clock from base clock CLK_BASE_USB1 */
-#if defined(CHIP_LPC43XX)
-	CLK_SPI = 288,			/*!< SPI clock from base clock CLK_BASE_SPI */
-	CLK_VADC,				/*!< VADC clock from base clock CLK_BASE_VADC */
-#else
-	CLK_RESERVED7 = 320,
-	CLK_RESERVED8,
-#endif
-	CLK_CCU1_LAST,
-
-	/* CCU2 clocks */
-	CLK_CCU2_START,
-	CLK_APLL = CLK_CCU2_START,	/*!< Audio PLL clock from base clock CLK_BASE_APLL */
-	RESERVED_ALIGNB = CLK_CCU2_START + 31,
-	CLK_APB2_UART3,			/*!< UART3 clock from base clock CLK_BASE_UART3 */
-	RESERVED_ALIGNC = CLK_CCU2_START + 63,
-	CLK_APB2_UART2,			/*!< UART2 clock from base clock CLK_BASE_UART2 */
-	RESERVED_ALIGND = CLK_CCU2_START + 95,
-	CLK_APB0_UART1,			/*!< UART1 clock from base clock CLK_BASE_UART1 */
-	RESERVED_ALIGNE = CLK_CCU2_START + 127,
-	CLK_APB0_UART0,			/*!< UART0 clock from base clock CLK_BASE_UART0 */
-	RESERVED_ALIGNF = CLK_CCU2_START + 159,
-	CLK_APB2_SSP1,			/*!< SSP1 clock from base clock CLK_BASE_SSP1 */
-	RESERVED_ALIGNG = CLK_CCU2_START + 191,
-	CLK_APB0_SSP0,			/*!< SSP0 clock from base clock CLK_BASE_SSP0 */
-	RESERVED_ALIGNH = CLK_CCU2_START + 223,
-	CLK_APB2_SDIO,			/*!< SDIO clock from base clock CLK_BASE_SDIO */
-	CLK_CCU2_LAST
-} CCU_CLK_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_CLOCKS_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h
deleted file mode 100644
index 74ff85346c..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * @brief LPC18xx basic chip inclusion file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_LPC18XX_H_
-#define __CHIP_LPC18XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "lpc_types.h"
-#include "sys_config.h"
-
-#ifndef CORE_M3
-#error CORE_M3 is not defined for the LPC18xx architecture
-#error CORE_M3 should be defined as part of your compiler define list
-#endif
-
-#ifndef CHIP_LPC18XX
-#error The LPC18XX Chip include path is used for this build, but
-#error CHIP_LPC18XX is not defined!
-#endif
-
-#include "adc_001.h"
-#include "atimer_001.h"
-#include "ccan_001.h"
-#include "dac_001.h"
-#include "emc_001.h"
-#include "enet_001.h"
-#include "gima_001.h"
-#include "gpdma_001.h"
-#include "gpiogrpint_001.h"
-#include "gpiopinint_001.h"
-#include "gpio_001.h"
-#include "i2c_001.h"
-#include "i2s_001.h"
-#include "lcd_001.h"
-#include "mcpwm_001.h"
-#include "pmc_001.h"
-#include "qei_001.h"
-#include "regfile_001.h"
-#include "ritimer_001.h"
-#include "rtc_001.h"
-#include "sct_001.h"
-#include "sdmmc_001.h"
-#include "ssp_001.h"
-#include "timer_001.h"
-#include "usart_001.h"
-#include "usbhs_001.h"
-#include "wwdt_001.h"
-#include "spifi_001.h"
-#include "rgu_18xx_43xx.h"
-#include "cguccu_18xx_43xx.h"
-
-/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define LPC_SCT_BASE              0x40000000
-#define LPC_GPDMA_BASE            0x40002000
-#define LPC_SDMMC_BASE            0x40004000
-#define LPC_EMC_BASE              0x40005000
-#define LPC_USB0_BASE             0x40006000
-#define LPC_USB1_BASE             0x40007000
-#define LPC_LCD_BASE              0x40008000
-#define LPC_ETHERNET_BASE         0x40010000
-#define LPC_ATIMER_BASE           0x40040000
-#define LPC_REGFILE_BASE          0x40041000
-#define LPC_PMC_BASE              0x40042000
-#define LPC_CREG_BASE             0x40043000
-#define LPC_EVRT_BASE             0x40044000
-#define LPC_RTC_BASE              0x40046000
-#define LPC_CGU_BASE              0x40050000
-#define LPC_CCU1_BASE             0x40051000
-#define LPC_CCU2_BASE             0x40052000
-#define LPC_RGU_BASE              0x40053000
-#define LPC_WWDT_BASE             0x40080000
-#define LPC_USART0_BASE           0x40081000
-#define LPC_USART2_BASE           0x400C1000
-#define LPC_USART3_BASE           0x400C2000
-#define LPC_UART1_BASE            0x40082000
-#define LPC_SSP0_BASE             0x40083000
-#define LPC_SSP1_BASE             0x400C5000
-#define LPC_TIMER0_BASE           0x40084000
-#define LPC_TIMER1_BASE           0x40085000
-#define LPC_TIMER2_BASE           0x400C3000
-#define LPC_TIMER3_BASE           0x400C4000
-#define LPC_SCU_BASE              0x40086000
-#define LPC_GPIO_PIN_INT_BASE     0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
-#define LPC_MCPWM_BASE            0x400A0000
-#define LPC_I2C0_BASE             0x400A1000
-#define LPC_I2C1_BASE             0x400E0000
-#define LPC_I2S0_BASE             0x400A2000
-#define LPC_I2S1_BASE             0x400A3000
-#define LPC_C_CAN1_BASE           0x400A4000
-#define LPC_RITIMER_BASE          0x400C0000
-#define LPC_QEI_BASE              0x400C6000
-#define LPC_GIMA_BASE             0x400C7000
-#define LPC_DAC_BASE              0x400E1000
-#define LPC_C_CAN0_BASE           0x400E2000
-#define LPC_ADC0_BASE             0x400E3000
-#define LPC_ADC1_BASE             0x400E4000
-#define LPC_GPIO_PORT_BASE        0x400F4000
-#define LPC_SPI_BASE              0x40100000
-#define LPC_SGPIO_BASE            0x40101000
-
-/* Normalize types */
-typedef IP_SCT_001_Type LPC_SCT_Type;
-typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
-typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
-typedef IP_EMC_001_Type LPC_EMC_Type;
-typedef IP_USBHS_001_Type LPC_USBHS_Type;
-typedef IP_ENET_001_Type LPC_ENET_Type;
-typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
-typedef IP_REGFILE_001_T LPC_REGFILE_T;
-typedef IP_PMC_001_Type LPC_PMC_Type;
-typedef IP_RTC_001_T LPC_RTC_Type;
-typedef IP_WWDT_001_Type LPC_WWDT_Type;
-typedef IP_USART_001_Type LPC_USART_Type;
-typedef IP_SSP_001_Type LPC_SSP_Type;
-typedef IP_TIMER_001_Type LPC_TIMER_Type;
-typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
-typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
-typedef IP_I2C_001_Type LPC_I2C_Type;
-typedef IP_I2S_001_Type LPC_I2S_Type;
-typedef IP_CCAN_001_Type LPC_CCAN_Type;
-typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
-typedef IP_QEI_001_Type LPC_QEI_Type;
-typedef IP_GIMA_001_Type LPC_GIMA_Type;
-typedef IP_DAC_001_Type LPC_DAC_Type;
-typedef IP_ADC_001_Type LPC_ADC_Type;
-typedef IP_GPIO_001_Type LPC_GPIO_Type;
-typedef IP_LCD_001_Type LPC_LCD_Type;
-
-#define LPC_SCT                   ((IP_SCT_001_Type              *) LPC_SCT_BASE)
-#define LPC_GPDMA                 ((IP_GPDMA_001_Type            *) LPC_GPDMA_BASE)
-#define LPC_SDMMC                 ((IP_SDMMC_001_Type            *) LPC_SDMMC_BASE)
-#define LPC_EMC                   ((IP_EMC_001_Type              *) LPC_EMC_BASE)
-#define LPC_USB0                  ((IP_USBHS_001_Type            *) LPC_USB0_BASE)
-#define LPC_USB1                  ((IP_USBHS_001_Type            *) LPC_USB1_BASE)
-#define LPC_LCD                   ((IP_LCD_001_Type              *) LPC_LCD_BASE)
-#define LPC_ETHERNET              ((IP_ENET_001_Type             *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER                ((IP_ATIMER_001_Type           *) LPC_ATIMER_BASE)
-#define LPC_REGFILE               ((IP_REGFILE_001_T             *) LPC_REGFILE_BASE)
-#define LPC_PMC                   ((IP_PMC_001_Type              *) LPC_PMC_BASE)
-#define LPC_EVRT                  ((LPC_EVRT_Type                *) LPC_EVRT_BASE)
-#define LPC_RTC                   ((IP_RTC_001_T                 *) LPC_RTC_BASE)
-#define LPC_CGU                   ((LPC_CGU_T                    *) LPC_CGU_BASE)
-#define LPC_CCU1                  ((LPC_CCU1_Type                *) LPC_CCU1_BASE)
-#define LPC_CCU2                  ((LPC_CCU2_Type                *) LPC_CCU2_BASE)
-#define LPC_CREG                  ((LPC_CREG_T                   *) LPC_CREG_BASE)
-#define LPC_RGU                   ((LPC_RGU_T                    *) LPC_RGU_BASE)
-#define LPC_WWDT                  ((IP_WWDT_001_Type             *) LPC_WWDT_BASE)
-#define LPC_USART0                ((IP_USART_001_Type            *) LPC_USART0_BASE)
-#define LPC_USART2                ((IP_USART_001_Type            *) LPC_USART2_BASE)
-#define LPC_USART3                ((IP_USART_001_Type            *) LPC_USART3_BASE)
-#define LPC_UART1                 ((IP_USART_001_Type            *) LPC_UART1_BASE)
-#define LPC_SSP0                  ((IP_SSP_001_Type              *) LPC_SSP0_BASE)
-#define LPC_SSP1                  ((IP_SSP_001_Type              *) LPC_SSP1_BASE)
-#define LPC_TIMER0                ((IP_TIMER_001_Type            *) LPC_TIMER0_BASE)
-#define LPC_TIMER1                ((IP_TIMER_001_Type            *) LPC_TIMER1_BASE)
-#define LPC_TIMER2                ((IP_TIMER_001_Type            *) LPC_TIMER2_BASE)
-#define LPC_TIMER3                ((IP_TIMER_001_Type            *) LPC_TIMER3_BASE)
-#define LPC_SCU                   ((LPC_SCU_Type                 *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT          ((IP_GPIOPININT_001_Type       *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM                 ((IP_MCPWM_001_Type            *) LPC_MCPWM_BASE)
-#define LPC_I2C0                  ((IP_I2C_001_Type              *) LPC_I2C0_BASE)
-#define LPC_I2C1                  ((IP_I2C_001_Type              *) LPC_I2C1_BASE)
-#define LPC_I2S0                  ((IP_I2S_001_Type              *) LPC_I2S0_BASE)
-#define LPC_I2S1                  ((IP_I2S_001_Type              *) LPC_I2S1_BASE)
-#define LPC_C_CAN1                ((IP_CCAN_001_Type             *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER               ((IP_RITIMER_001_Type          *) LPC_RITIMER_BASE)
-#define LPC_QEI                   ((IP_QEI_001_Type              *) LPC_QEI_BASE)
-#define LPC_GIMA                  ((IP_GIMA_001_Type             *) LPC_GIMA_BASE)
-#define LPC_DAC                   ((IP_DAC_001_Type              *) LPC_DAC_BASE)
-#define LPC_C_CAN0                ((IP_CCAN_001_Type             *) LPC_C_CAN0_BASE)
-#define LPC_ADC0                  ((IP_ADC_001_Type              *) LPC_ADC0_BASE)
-#define LPC_ADC1                  ((IP_ADC_001_Type              *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT             ((IP_GPIO_001_Type             *) LPC_GPIO_PORT_BASE)
-
-/**
- * @}
- */
-
-#include "clock_18xx_43xx.h"
-#include "gpio_18xx_43xx.h"
-#include "uart_18xx_43xx.h"
-#include "gpdma_18xx_43xx.h"
-#include "enet_18xx_43xx.h"
-#include "i2c_18xx_43xx.h"
-#include "i2s_18xx_43xx.h"
-#include "ssp_18xx_43xx.h"
-#include "rtc_18xx_43xx.h"
-#include "evrt_18xx_43xx.h"
-#include "atimer_18xx_43xx.h"
-#include "wwdt_18xx_43xx.h"
-#include "ritimer_18xx_43xx.h"
-#include "emc_18xx_43xx.h"
-#include "lcd_18xx_43xx.h"
-#include "adc_18xx_43xx.h"
-#include "sdmmc_18xx_43xx.h"
-#include "timer_18xx_43xx.h"
-#include "creg_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_LPC18XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h
deleted file mode 100644
index 757d7bb0a1..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * @brief LPC43xx basic chip inclusion file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_LPC43XX_H_
-#define __CHIP_LPC43XX_H_
-
-#include "lpc_types.h"
-#include "sys_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(CORE_M4) && !defined(CORE_M0)
-#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture
-#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list
-#endif
-
-#ifndef CHIP_LPC43XX
-#error The LPC43XX Chip include path is used for this build, but
-#error CHIP_LPC43XX is not defined!
-#endif
-
-#include "adc_001.h"
-#include "atimer_001.h"
-#include "ccan_001.h"
-#include "dac_001.h"
-#include "emc_001.h"
-#include "enet_001.h"
-#include "gima_001.h"
-#include "gpdma_001.h"
-#include "gpiogrpint_001.h"
-#include "gpiopinint_001.h"
-#include "gpio_001.h"
-#include "i2c_001.h"
-#include "i2s_001.h"
-#include "lcd_001.h"
-#include "mcpwm_001.h"
-#include "pmc_001.h"
-#include "qei_001.h"
-#include "regfile_001.h"
-#include "ritimer_001.h"
-#include "rtc_001.h"
-#include "sct_001.h"
-#include "sdmmc_001.h"
-#include "sgpio_001.h"
-#include "spi_001.h"
-#include "ssp_001.h"
-#include "timer_001.h"
-#include "usart_001.h"
-#include "usbhs_001.h"
-#include "wwdt_001.h"
-#include "spifi_001.h"
-#include "rgu_18xx_43xx.h"
-#include "cguccu_18xx_43xx.h"
-
-/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define LPC_SCT_BASE              0x40000000
-#define LPC_GPDMA_BASE            0x40002000
-#define LPC_SDMMC_BASE            0x40004000
-#define LPC_EMC_BASE              0x40005000
-#define LPC_USB0_BASE             0x40006000
-#define LPC_USB1_BASE             0x40007000
-#define LPC_LCD_BASE              0x40008000
-#define LPC_ETHERNET_BASE         0x40010000
-#define LPC_ATIMER_BASE           0x40040000
-#define LPC_REGFILE_BASE          0x40041000
-#define LPC_PMC_BASE              0x40042000
-#define LPC_CREG_BASE             0x40043000
-#define LPC_EVRT_BASE             0x40044000
-#define LPC_RTC_BASE              0x40046000
-#define LPC_CGU_BASE              0x40050000
-#define LPC_CCU1_BASE             0x40051000
-#define LPC_CCU2_BASE             0x40052000
-#define LPC_RGU_BASE              0x40053000
-#define LPC_WWDT_BASE             0x40080000
-#define LPC_USART0_BASE           0x40081000
-#define LPC_USART2_BASE           0x400C1000
-#define LPC_USART3_BASE           0x400C2000
-#define LPC_UART1_BASE            0x40082000
-#define LPC_SSP0_BASE             0x40083000
-#define LPC_SSP1_BASE             0x400C5000
-#define LPC_TIMER0_BASE           0x40084000
-#define LPC_TIMER1_BASE           0x40085000
-#define LPC_TIMER2_BASE           0x400C3000
-#define LPC_TIMER3_BASE           0x400C4000
-#define LPC_SCU_BASE              0x40086000
-#define LPC_GPIO_PIN_INT_BASE     0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
-#define LPC_MCPWM_BASE            0x400A0000
-#define LPC_I2C0_BASE             0x400A1000
-#define LPC_I2C1_BASE             0x400E0000
-#define LPC_I2S0_BASE             0x400A2000
-#define LPC_I2S1_BASE             0x400A3000
-#define LPC_C_CAN1_BASE           0x400A4000
-#define LPC_RITIMER_BASE          0x400C0000
-#define LPC_QEI_BASE              0x400C6000
-#define LPC_GIMA_BASE             0x400C7000
-#define LPC_DAC_BASE              0x400E1000
-#define LPC_C_CAN0_BASE           0x400E2000
-#define LPC_ADC0_BASE             0x400E3000
-#define LPC_ADC1_BASE             0x400E4000
-#define LPC_GPIO_PORT_BASE        0x400F4000
-#define LPC_SPI_BASE              0x40100000
-#define LPC_SGPIO_BASE            0x40101000
-
-/* Normalize types */
-typedef IP_SCT_001_Type LPC_SCT_Type;
-typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
-typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
-typedef IP_EMC_001_Type LPC_EMC_Type;
-typedef IP_USBHS_001_Type LPC_USBHS_Type;
-typedef IP_ENET_001_Type LPC_ENET_Type;
-typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
-typedef IP_REGFILE_001_T LPC_REGFILE_Type;
-typedef IP_PMC_001_Type LPC_PMC_Type;
-typedef IP_RTC_001_T LPC_RTC_Type;
-typedef IP_WWDT_001_Type LPC_WWDT_Type;
-typedef IP_USART_001_Type LPC_USART_Type;
-typedef IP_SSP_001_Type LPC_SSP_Type;
-typedef IP_TIMER_001_Type LPC_TIMER_Type;
-typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
-typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
-typedef IP_I2C_001_Type LPC_I2C_Type;
-typedef IP_I2S_001_Type LPC_I2S_Type;
-typedef IP_CCAN_001_Type LPC_CCAN_Type;
-typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
-typedef IP_QEI_001_Type LPC_QEI_Type;
-typedef IP_GIMA_001_Type LPC_GIMA_Type;
-typedef IP_DAC_001_Type LPC_DAC_Type;
-typedef IP_ADC_001_Type LPC_ADC_Type;
-typedef IP_GPIO_001_Type LPC_GPIO_Type;
-typedef IP_SPI_001_Type LPC_SPI_Type;
-typedef IP_SGPIO_001_Type LPC_SGPIO_Type;
-typedef IP_LCD_001_Type LPC_LCD_Type;
-
-#define LPC_SCT                   ((IP_SCT_001_Type              *) LPC_SCT_BASE)
-#define LPC_GPDMA                 ((IP_GPDMA_001_Type            *) LPC_GPDMA_BASE)
-#define LPC_SDMMC                 ((IP_SDMMC_001_Type            *) LPC_SDMMC_BASE)
-#define LPC_EMC                   ((IP_EMC_001_Type              *) LPC_EMC_BASE)
-#define LPC_USB0                  ((IP_USBHS_001_Type            *) LPC_USB0_BASE)
-#define LPC_USB1                  ((IP_USBHS_001_Type            *) LPC_USB1_BASE)
-#define LPC_LCD                   ((IP_LCD_001_Type              *) LPC_LCD_BASE)
-#define LPC_ETHERNET              ((IP_ENET_001_Type             *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER                ((IP_ATIMER_001_Type           *) LPC_ATIMER_BASE)
-#define LPC_REGFILE               ((IP_REGFILE_001_T             *) LPC_REGFILE_BASE)
-#define LPC_PMC                   ((IP_PMC_001_Type              *) LPC_PMC_BASE)
-#define LPC_EVRT                  ((LPC_EVRT_Type                *) LPC_EVRT_BASE)
-#define LPC_RTC                   ((IP_RTC_001_T                 *) LPC_RTC_BASE)
-#define LPC_CGU                   ((LPC_CGU_T                    *) LPC_CGU_BASE)
-#define LPC_CCU1                  ((LPC_CCU1_Type                *) LPC_CCU1_BASE)
-#define LPC_CCU2                  ((LPC_CCU2_Type                *) LPC_CCU2_BASE)
-#define LPC_CREG                  ((LPC_CREG_T                   *) LPC_CREG_BASE)
-#define LPC_RGU                   ((LPC_RGU_T                    *) LPC_RGU_BASE)
-#define LPC_WWDT                  ((IP_WWDT_001_Type             *) LPC_WWDT_BASE)
-#define LPC_USART0                ((IP_USART_001_Type            *) LPC_USART0_BASE)
-#define LPC_USART2                ((IP_USART_001_Type            *) LPC_USART2_BASE)
-#define LPC_USART3                ((IP_USART_001_Type            *) LPC_USART3_BASE)
-#define LPC_UART1                 ((IP_USART_001_Type            *) LPC_UART1_BASE)
-#define LPC_SSP0                  ((IP_SSP_001_Type              *) LPC_SSP0_BASE)
-#define LPC_SSP1                  ((IP_SSP_001_Type              *) LPC_SSP1_BASE)
-#define LPC_TIMER0                ((IP_TIMER_001_Type            *) LPC_TIMER0_BASE)
-#define LPC_TIMER1                ((IP_TIMER_001_Type            *) LPC_TIMER1_BASE)
-#define LPC_TIMER2                ((IP_TIMER_001_Type            *) LPC_TIMER2_BASE)
-#define LPC_TIMER3                ((IP_TIMER_001_Type            *) LPC_TIMER3_BASE)
-#define LPC_SCU                   ((LPC_SCU_Type                 *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT          ((IP_GPIOPININT_001_Type       *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1       ((IP_GPIOGROUPINT_001_Type     *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM                 ((IP_MCPWM_001_Type            *) LPC_MCPWM_BASE)
-#define LPC_I2C0                  ((IP_I2C_001_Type              *) LPC_I2C0_BASE)
-#define LPC_I2C1                  ((IP_I2C_001_Type              *) LPC_I2C1_BASE)
-#define LPC_I2S0                  ((IP_I2S_001_Type              *) LPC_I2S0_BASE)
-#define LPC_I2S1                  ((IP_I2S_001_Type              *) LPC_I2S1_BASE)
-#define LPC_C_CAN1                ((IP_CCAN_001_Type             *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER               ((IP_RITIMER_001_Type          *) LPC_RITIMER_BASE)
-#define LPC_QEI                   ((IP_QEI_001_Type              *) LPC_QEI_BASE)
-#define LPC_GIMA                  ((IP_GIMA_001_Type             *) LPC_GIMA_BASE)
-#define LPC_DAC                   ((IP_DAC_001_Type              *) LPC_DAC_BASE)
-#define LPC_C_CAN0                ((IP_CCAN_001_Type             *) LPC_C_CAN0_BASE)
-#define LPC_ADC0                  ((IP_ADC_001_Type              *) LPC_ADC0_BASE)
-#define LPC_ADC1                  ((IP_ADC_001_Type              *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT             ((IP_GPIO_001_Type             *) LPC_GPIO_PORT_BASE)
-#define LPC_SPI                   ((IP_SPI_001_Type              *) LPC_SPI_BASE)
-#define LPC_SGPIO                 ((IP_SGPIO_001_Type            *) LPC_SGPIO_BASE)
-
-/**
- * @}
- */
-
-#include "clock_18xx_43xx.h"
-#include "gpio_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-#include "uart_18xx_43xx.h"
-#include "gpdma_18xx_43xx.h"
-#include "enet_18xx_43xx.h"
-#include "rgu_18xx_43xx.h"
-#include "i2c_18xx_43xx.h"
-#include "i2s_18xx_43xx.h"
-#include "ssp_18xx_43xx.h"
-#include "rtc_18xx_43xx.h"
-#include "evrt_18xx_43xx.h"
-#include "atimer_18xx_43xx.h"
-#include "wwdt_18xx_43xx.h"
-#include "ritimer_18xx_43xx.h"
-#include "emc_18xx_43xx.h"
-#include "lcd_18xx_43xx.h"
-#include "adc_18xx_43xx.h"
-#include "timer_18xx_43xx.h"
-#include "sdmmc_18xx_43xx.h"
-#include "fpu_init.h"
-#include "creg_18xx_43xx.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_LPC43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c
deleted file mode 100644
index 9f9a58930d..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*
- * @brief LPC18xx/43xx clock driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "clock_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Maps a peripheral clock to it's base clock */
-typedef struct {
-	CCU_CLK_T clkstart;
-	CCU_CLK_T clkend;
-	CGU_BASE_CLK_T clkbase;
-} CLK_PERIPH_TO_BASE_T;
-static const CLK_PERIPH_TO_BASE_T periph_to_base[] = {
-	{CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3},
-	{CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1},
-	{CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI},
-	{CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX},
-#if 0
-#if defined(CHIP_LPC43XX)
-	{CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},
-#endif
-	{CLK_USB0, CLK_USB0, CLK_BASE_USB0},
-	{CLK_USB1, CLK_USB1, CLK_BASE_USB1},
-#if defined(CHIP_LPC43XX)
-	{CLK_SPI, CLK_SPI, CLK_BASE_SPI},
-	{CLK_VADC, CLK_VADC, CLK_BASE_VADC},
-#endif
-	{CLK_APLL, CLK_APLL, CLK_BASE_APLL},
-	{CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3},
-	{CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2},
-	{CLK_APB2_UART1, CLK_APB2_UART1, CLK_BASE_UART1},
-	{CLK_APB2_UART0, CLK_APB2_UART0, CLK_BASE_UART0},
-	{CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1},
-	{CLK_APB2_SSP0, CLK_APB2_SSP0, CLK_BASE_SSP0},
-	{CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO},
-	{CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE}
-#endif
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Test PLL input values for a specific frequency range */
-static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz)
-{
-	uint32_t TestHz = TestMult * InputHz;
-
-	if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {
-		TestHz = 0;
-	}
-
-	return TestHz;
-}
-
-/* Returns clock rate out of a divider */
-static uint32_t Chip_Clock_GetDivRate(CGU_CLKIN_T clock, CGU_IDIV_T divider)
-{
-	CGU_CLKIN_T input;
-	uint32_t div;
-
-	input = Chip_Clock_GetDividerSource(divider);
-	div = Chip_Clock_GetDividerDivisor(divider);
-	return Chip_Clock_GetClockInputHz(input) / (div + 1);
-}
-
-/* Finds the base clock for the peripheral clock */
-static CGU_BASE_CLK_T Chip_Clock_FindBseClock(CCU_CLK_T clk)
-{
-	CGU_BASE_CLK_T baseclk = CLK_BASE_NONE;
-	int i = 0;
-
-	while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {
-		if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {
-			baseclk = periph_to_base[i].clkbase;
-		}
-		else {
-			i++;
-		}
-	}
-
-	return baseclk;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Enables the crystal oscillator */
-void Chip_Clock_EnableCrystal(void)
-{
-	uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL;
-
-	/* Clear bypass mode */
-	OldCrystalConfig &= (~2);
-	if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) {
-		LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
-	}
-
-	/* Enable crystal oscillator */
-	OldCrystalConfig &= (~1);
-	if (CRYSTAL_MAIN_FREQ_IN >= 20000000) {
-		OldCrystalConfig |= 4;	/* Set high frequency mode */
-
-	}
-	LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
-}
-
-/* Disables the crystal oscillator */
-void IP_Clock_DisableCrystal(void)
-{
-	/* Disable crystal oscillator */
-	LPC_CGU->XTAL_OSC_CTRL &= (~1);
-}
-
-/* Configures the main PLL */
-uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
-{
-	uint32_t freqin = Chip_Clock_GetClockInputHz(Input);
-	uint32_t Mult, LastMult, MultEnd;
-	uint32_t freqout, freqout2;
-
-	if (DesiredHz != 0xFFFFFFFF) {
-		/* Test DesiredHz rounded down */
-		Mult = DesiredHz / freqin;
-		freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
-		/* Test DesiredHz rounded up */
-		Mult++;
-		freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
-		if (freqout && !freqout2) {	/* rounding up is no good? set first multiplier */
-			Mult--;
-			return Chip_Clock_SetupMainPLLMult(Input, Mult);
-		}
-		if (!freqout && freqout2) {	/* didn't work until rounded up? set 2nd multiplier */
-			return Chip_Clock_SetupMainPLLMult(Input, Mult);
-		}
-
-		if (freqout && freqout2) {	/* either multiplier okay? choose closer one */
-			if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {
-				Mult--;
-				return Chip_Clock_SetupMainPLLMult(Input, Mult);
-			}
-			else {
-				return Chip_Clock_SetupMainPLLMult(Input, Mult);
-			}
-		}
-	}
-
-	/* Neither multiplier okay? Try to start at MinHz and increment.
-	   This should find the highest multiplier that is still good */
-	Mult = MinHz / freqin;
-	MultEnd = MaxHz / freqin;
-	LastMult = 0;
-	while (1) {
-		freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
-		if (freqout) {
-			LastMult = Mult;
-		}
-
-		if (Mult >= MultEnd) {
-			break;
-		}
-		Mult++;
-	}
-
-	if (LastMult) {
-		return Chip_Clock_SetupMainPLLMult(Input, LastMult);
-	}
-
-	return 0;
-}
-
-/* Directly set the PLL multipler */
-uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult)
-{
-	uint32_t freq = Chip_Clock_GetClockInputHz(Input);
-	uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
-	uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
-
-	freq *= mult;
-	msel = mult - 1;
-
-	PLLReg &= ~(0x1F << 24);/* clear input source bits */
-	PLLReg |= Input << 24;	/* set input source bits to parameter */
-
-	/* Clear other PLL input bits */
-	PLLReg &= ~((1 << 6) |	/* FBSEL */
-				(1 << 1) |	/* BYPASS */
-				(1 << 7) |	/* DIRECT */
-				(0x03 << 8) | (0xFF << 16) | (0x03 << 12));	/* PSEL, MSEL, NSEL- divider ratios */
-
-	if (freq < 156000000) {
-		/* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */
-		while ((2 * (pval) * freq) < 156000000) {
-			psel++;
-			pval *= 2;
-		}
-
-		PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6);	/* dividers + FBSEL */
-	}
-	else if (freq < 320000000) {
-		PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6);	/* dividers + DIRECT + FBSEL */
-	}
-	else {
-		Chip_Clock_DisableMainPLL();
-		return 0;
-	}
-	LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);
-
-	return freq;
-}
-
-/* Returns the frequency of the main PLL */
-uint32_t Chip_Clock_GetMainPLLHz(void)
-{
-	uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
-	uint32_t freq = Chip_Clock_GetClockInputHz((CGU_CLKIN_T) ((PLLReg >> 24) & 0xF));
-	uint32_t msel, nsel, psel, direct, fbsel;
-	uint32_t m, n, p;
-	const uint8_t ptab[] = {1, 2, 4, 8};
-
-	/* No lock? */
-	if (!(LPC_CGU->PLL1_STAT & 1)) {
-		return 0;
-	}
-
-	msel = (PLLReg >> 16) & 0xFF;
-	nsel = (PLLReg >> 12) & 0x3;
-	psel = (PLLReg >> 8) & 0x3;
-	direct = (PLLReg >> 7) & 0x1;
-	fbsel = (PLLReg >> 6) & 0x1;
-
-	m = msel + 1;
-	n = nsel + 1;
-	p = ptab[psel];
-
-	if (direct || fbsel) {
-		return m * (freq / n);
-	}
-
-	return (m / (2 * p)) * (freq / n);
-}
-
-/* Disables the main PLL */
-void Chip_Clock_DisableMainPLL(void)
-{
-	/* power down main PLL */
-	LPC_CGU->PLL1_CTRL |= 1;
-}
-
-/* Returns the lock status of the main PLL */
-bool Chip_Clock_MainPLLLocked(void)
-{
-	/* Return true if locked */
-	return (bool) (LPC_CGU->PLL1_STAT & 1);
-}
-
-/* Sets up a CGU clock divider and it's input clock */
-void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor)
-{
-	uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
-
-	Divisor--;
-
-	if (Input != CLKINPUT_PD) {
-		/* Mask off bits that need to changes */
-		reg &= ~((0x1F << 24) | 1 | (0xF << 2));
-
-		/* Enable autoblocking, clear PD, and set clock source & divisor */
-		LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);
-	}
-	else {
-		LPC_CGU->IDIV_CTRL[Divider] = reg | 1;	/* Power down this divider */
-	}
-}
-
-/* Gets a CGU clock divider source */
-CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider)
-{
-	uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
-
-	if (reg & 1) {	/* divider is powered down */
-		return CLKINPUT_PD;
-	}
-
-	return (CGU_CLKIN_T) ((reg >> 24) & 0x1F);
-}
-
-/* Gets a CGU clock divider divisor */
-uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider)
-{
-	return (CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & 0xF);
-}
-
-/* Returns the frequency of the specified input clock source */
-uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input)
-{
-	uint32_t rate = 0;
-
-	switch (input) {
-	case CLKIN_32K:
-		rate = CRYSTAL_32K_FREQ_IN;
-		break;
-
-	case CLKIN_IRC:
-		rate = CGU_IRC_FREQ;
-		break;
-
-	case CLKIN_ENET_RX:
-#if defined(USE_RMII)
-		/* In RMII mode, this clock is not attached */
-#else
-		/* MII mode requires 25MHz clock */
-		rate = 25000000;
-#endif
-		break;
-
-	case CLKIN_ENET_TX:
-#if defined(USE_RMII)
-		/* MII mode requires 50MHz clock */
-		rate = 50000000;
-#else
-		/* MII mode requires 25MHz clock */
-		rate = 25000000;
-#endif
-		break;
-
-	case CLKIN_CLKIN:
-#if defined(EXTERNAL_CLKIN_FREQ_IN)
-		rate = EXTERNAL_CLKIN_FREQ_IN;
-#else
-		/* Assume no clock in if a rate wasn't defined */
-#endif
-		break;
-
-	case CLKIN_CRYSTAL:
-		rate = CRYSTAL_MAIN_FREQ_IN;
-		break;
-
-	case CLKIN_USBPLL:
-		rate = 0; // FIXME
-		break;
-
-	case CLKIN_AUDIOPLL:
-		rate = 0; // FIXME
-		break;
-
-	case CLKIN_MAINPLL:
-		rate = Chip_Clock_GetMainPLLHz();
-		break;
-
-	case CLKIN_IDIVA:
-		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A);
-		break;
-
-	case CLKIN_IDIVB:
-		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B);
-		break;
-
-	case CLKIN_IDIVC:
-		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C);
-		break;
-
-	case CLKIN_IDIVD:
-		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D);
-		break;
-
-	case CLKIN_IDIVE:
-		rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E);
-		break;
-
-	case CLKINPUT_PD:
-		rate = 0;
-		break;
-
-	default:
-		break;
-	}
-
-	return rate;
-}
-
-/* Returns the frequency of the specified base clock source */
-uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock)
-{
-	return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock));
-}
-
-/* Sets a CGU Base Clock clock source */
-void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
-{
-	uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
-
-	if (BaseClock < CLK_BASE_NONE) {
-		if (Input != CLKINPUT_PD) {
-			/* Mask off fields we plan to update */
-			reg &= ~((0x1F << 24) | 1 | (1 << 11));
-
-			if (autoblocken) {
-				reg |= (1 << 11);
-			}
-			if (powerdn) {
-				reg |= (1 << 0);
-			}
-
-			/* Set clock source */
-			reg |= (Input << 24);
-
-			LPC_CGU->BASE_CLK[BaseClock] = reg;
-		}
-	}
-	else {
-		LPC_CGU->BASE_CLK[BaseClock] = reg | 1;	/* Power down this base clock */
-	}
-}
-
-/*Enables a base clock source */
-void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock)
-{
-	if (BaseClock < CLK_BASE_NONE) {
-		LPC_CGU->BASE_CLK[BaseClock] &= ~1;
-	}
-}
-
-/* Disables a base clock source */
-void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock)
-{
-	if (BaseClock < CLK_BASE_NONE) {
-		LPC_CGU->BASE_CLK[BaseClock] |= 1;
-	}
-}
-
-/* Gets a CGU Base Clock clock source */
-CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock)
-{
-	uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
-
-	if (BaseClock >= CLK_BASE_NONE) {
-		return CLKINPUT_PD;
-	}
-
-	/* base clock is powered down? */
-	if (reg & 1) {
-		return CLKINPUT_PD;
-	}
-
-	return (CGU_CLKIN_T) ((reg >> 24) & 0x1F);
-}
-
-/* Enables a peripheral clock and sets clock states */
-void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
-{
-	uint32_t reg = 1;
-
-	if (autoen) {
-		reg |= (1 << 1);
-	}
-	if (wakeupen) {
-		reg |= (1 << 2);
-	}
-
-	/* Not all clocks support a divider, but we won't check that here. Only
-	   dividers of 1 and 2 are allowed. Assume 1 if not 2 */
-	if (div == 2) {
-		reg |= (1 << 5);
-	}
-
-	/* Setup peripheral clock and start running */
-	if (clk >= CLK_CCU2_START) {
-		LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg;
-	}
-	else {
-		LPC_CCU1->CLKCCU[clk].CFG = reg;
-	}
-}
-
-/* Enables a peripheral clock */
-void Chip_Clock_Enable(CCU_CLK_T clk)
-{
-	/* Start peripheral clock running */
-	if (clk >= CLK_CCU2_START) {
-		LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1;
-	}
-	else {
-		LPC_CCU1->CLKCCU[clk].CFG |= 1;
-	}
-}
-
-/* Disables a peripheral clock */
-void Chip_Clock_Disable(CCU_CLK_T clk)
-{
-	/* Stop peripheral clock */
-	if (clk >= CLK_CCU2_START) {
-		LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1;
-	}
-	else {
-		LPC_CCU1->CLKCCU[clk].CFG &= ~1;
-	}
-}
-
-/* Returns a peripheral clock rate */
-uint32_t Chip_Clock_GetRate(CCU_CLK_T clk)
-{
-	CGU_BASE_CLK_T baseclk;
-	uint32_t reg, div, rate;
-
-	/* Get CCU config register for clock */
-	if (clk >= CLK_CCU2_START) {
-		reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG;
-	}
-	else {
-		reg = LPC_CCU1->CLKCCU[clk].CFG;
-	}
-
-	/* Is the clock enabled? */
-	if (reg & 1) {
-		/* Get base clock for this peripheral clock */
-		baseclk = Chip_Clock_FindBseClock(clk);
-
-		/* Get base clock rate */
-		rate = Chip_Clock_GetBaseClocktHz(baseclk);
-
-		/* Get divider for this clock */
-		if (((reg >> 5) & 0x7) == 0) {
-			div = 1;
-		}
-		else {
-			div = 2;/* No other dividers supported */
-
-		}
-		rate = rate / div;
-	}
-	else {
-		rate = 0;
-	}
-
-	return rate;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h
deleted file mode 100644
index a8f1f8680d..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * @brief LPC18xx/43xx clock driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CLOCK_18XX_43XX_H_
-#define __CLOCK_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options
- * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS 
- * The clock driver has options that configure it's operation at build-time.<br/>
- * MAX_CLOCK_FREQ:
- * - This define, when set, identifies the maximumCPU clock rate of the system (change this to alter running CPU speed)
- * - When this is not defined, The maximum clock rate for the CPU is used
- * <br/><p>
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
- * @{
- */
-
-/**
- * @}
- */
-
-/* Internal oscillator frequency */
-#define CGU_IRC_FREQ (12000000)
-
-#ifndef MAX_CLOCK_FREQ
-#if defined(CHIP_LPC43XX)
-#define MAX_CLOCK_FREQ (204000000)
-#else
-#define MAX_CLOCK_FREQ (180000000)
-#endif
-#endif /* MAX_CLOCK_FREQ */
-
-/**
- * @brief	Enables the crystal oscillator
- * @return	Nothing
- */
-void Chip_Clock_EnableCrystal(void);
-
-/**
- * @brief	Disables the crystal oscillator
- * @return	Nothing
- */
-void Chip_Clock_DisableCrystal(void);
-
-/**
- * @brief   Configures the main PLL
- * @param   Input		: Which clock input to use as the PLL input
- * @param   MinHz		: Minimum allowable PLL output frequency
- * @param   DesiredHz	: Desired PLL output frequency
- * @param   MaxHz		: Maximum allowable PLL output frequency
- * @return	Frequency of the PLL in Hz
- * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz
- * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if
- * the PLL is locked.
- */
-uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
-
-/**
- * @brief	Directly set the PLL multipler
- * @param   Input	: Which clock input to use as the PLL input
- * @param	mult	: How many times to multiply the input clock
- * @return	Frequency of the PLL in Hz
- */
-uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult);
-
-/**
- * @brief   Returns the frequency of the main PLL
- * @return	Frequency of the PLL in Hz
- * Returns zero if the main PLL is not running.
- */
-uint32_t Chip_Clock_GetMainPLLHz(void);
-
-/**
- * @brief	Disables the main PLL
- * @return	none
- * Make sure the main PLL is not needed to clock the part before disabling it.
- * Saves power if the main PLL is not needed.
- */
-void Chip_Clock_DisableMainPLL(void);
-
-/**
- * @brief   Returns the lock status of the main PLL
- * @return	true if the PLL is locked, otherwise false
- * The main PLL should be locked prior to using it as a clock input for a base clock.
- */
-bool Chip_Clock_MainPLLLocked(void);
-
-/**
- * @brief	Sets up a CGU clock divider and it's input clock
- * @param	Divider	: CGU_IDIV_T value indicating which divider to configure
- * @param	Input	: CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
- * @param	Divisor	: value to divide Input clock by
- * @return	Nothing
- */
-void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor);
-
-/**
- * @brief	Gets a CGU clock divider source
- * @param	Divider	: CGU_IDIV_T value indicating which divider to get the source of
- * @return	CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
- */
-CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider);
-
-/**
- * @brief	Gets a CGU clock divider divisor
- * @param	Divider	: CGU_IDIV_T value indicating which divider to get the source of
- * @return	the divider value for the divider
- */
-uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider);
-
-/**
- * @brief	Returns the frequency of the specified input clock source
- * @param	input	: Which clock input to return the frequency of
- * @return	Frequency of input source in Hz
- * This function returns an ideal frequency and not the actual frequency. Returns
- * zero if the clock source is disabled.
- */
-uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input);
-
-/**
- * @brief	Returns the frequency of the specified base clock source
- * @param	clock	: which base clock to return the frequency of.
- * @return	Frequency of base source in Hz
- * This function returns an ideal frequency and not the actual frequency. Returns
- * zero if the clock source is disabled.
- */
-uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock);
-
-/**
- * @brief	Sets a CGU Base Clock clock source
- * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to set
- * @param	Input		: CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
- * @param	autoblocken	: Enables autoblocking during frequency change if true
- * @param	powerdn		: The clock base is setup, but powered down if true
- * @return	Nothing
- */
-void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
-
-/**
- * @brief	Gets a CGU Base Clock clock source
- * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for
- * @return	CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
- */
-CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief	Enables a base clock source
- * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to enable
- * @return	Nothing
- */
-void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief	Disables a base clock source
- * @param	BaseClock	: CGU_BASE_CLK_T value indicating which base clock to disable
- * @return	Nothing
- */
-void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief	Enables a peripheral clock and sets clock states
- * @param	clk			: CCU_CLK_T value indicating which clock to enable
- * @param	autoen		: true to enable autoblocking on a clock rate change, false to disable
- * @param	wakeupen	: true to enable wakeup mechanism, false to disable
- * @param	div			: Divider for the clock, must be 1 for most clocks, 2 supported on others
- * @return	Nothing
- */
-void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
-
-/**
- * @brief	Enables a peripheral clock
- * @param	clk	: CCU_CLK_T value indicating which clock to enable
- * @return	Nothing
- */
-void Chip_Clock_Enable(CCU_CLK_T clk);
-
-/**
- * @brief	Disables a peripheral clock
- * @param	clk	: CCU_CLK_T value indicating which clock to disable
- * @return	Nothing
- */
-void Chip_Clock_Disable(CCU_CLK_T clk);
-
-/**
- * @brief	Returns a peripheral clock rate
- * @param	clk	: CCU_CLK_T value indicating which clock to get rate for
- * @return	0 if the clock is disabled, or the rate of the clock
- */
-uint32_t Chip_Clock_GetRate(CCU_CLK_T clk);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CLOCK_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h
deleted file mode 100644
index 2cbada5c27..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * @brief Basic CMSIS include file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CMSIS_H_
-#define __CMSIS_H_
-
-#include "lpc_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#if defined(__ARMCC_VERSION)
-// Kill warning "#pragma push with no matching #pragma pop"
-  #pragma diag_suppress 2525
-  #pragma push
-  #pragma anon_unions
-#elif defined(__CWCC__)
-  #pragma push
-  #pragma cpp_extensions on
-#elif defined(__GNUC__)
-/* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
-//  #pragma push // FIXME not usable for IAR
-  #pragma language=extended
-#else
-  #error Not supported compiler type
-#endif
-
-#if defined(CORE_M4)
-/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions
- * @{
- */
-
-#define __CM4_REV              0x0000		/*!< Cortex-M4 Core Revision               */
-#define __MPU_PRESENT             1			/*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
-#ifdef CHIP_LPC43XX
-#define __FPU_PRESENT             1			/*!< FPU present or not                    */
-#else
-#define __FPU_PRESENT             0			/*!< FPU present or not                    */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
-	/* -------------------------  Cortex-M4 Processor Exceptions Numbers  ----------------------------- */
-	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
-	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
-	MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
-	BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
-	UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
-	SVCall_IRQn                       =  -5,/*!<  11  System Service Call via SVC instruction */
-	DebugMonitor_IRQn                 =  -4,/*!<  12  Debug Monitor                    */
-	PendSV_IRQn                       =  -2,/*!<  14  Pendable request for system service */
-	SysTick_IRQn                      =  -1,/*!<  15  System Tick Timer                */
-
-	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
-	DAC_IRQn                          =   0,/*!<   0  DAC                              */
-	M0CORE_IRQn                       =   1,/*!<   1  M0a                              */
-	DMA_IRQn                          =   2,/*!<   2  DMA                              */
-	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
-	RESERVED2_IRQn                    =   4,
-	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
-	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
-	LCD_IRQn                          =   7,/*!<   7  LCD                              */
-	USB0_IRQn                         =   8,/*!<   8  USB0                             */
-	USB1_IRQn                         =   9,/*!<   9  USB1                             */
-	SCT_IRQn                          =  10,/*!<  10  SCT                              */
-	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
-	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
-	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
-	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
-	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
-	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
-	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
-	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
-	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
-	SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */
-	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
-	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
-	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
-	USART0_IRQn                       =  24,/*!<  24  USART0                           */
-	UART1_IRQn                        =  25,/*!<  25  UART1                            */
-	USART2_IRQn                       =  26,/*!<  26  USART2                           */
-	USART3_IRQn                       =  27,/*!<  27  USART3                           */
-	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
-	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
-	RESERVED4_IRQn                    =  30,
-	SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */
-	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
-	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
-	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
-	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
-	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
-	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
-	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
-	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
-	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
-	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
-	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
-	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
-	RESERVED6_IRQn                    =  44,
-	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
-	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
-	RTC_IRQn                          =  47,/*!<  47  RTC                              */
-	RESERVED8_IRQn                    =  48,
-	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
-	RESERVED9_IRQn                    =  50,
-	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
-	QEI_IRQn                          =  52,/*!<  52  QEI                              */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h"						/*!< Cortex-M4 processor and core peripherals */
-
-#elif defined(CORE_M3)
-/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions
- * @{
- */
-
-#define __MPU_PRESENT             1			/*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT             0			/*!< FPU present or not                    */
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
-	/* -------------------------  Cortex-M3 Processor Exceptions Numbers  ----------------------------- */
-	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
-	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
-	MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
-	BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
-	UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
-	SVCall_IRQn                       = -5,	/*!<  11  System Service Call via SVC instruction */
-	DebugMonitor_IRQn                 = -4,	/*!<  12  Debug Monitor                    */
-	PendSV_IRQn                       = -2,	/*!<  14  Pendable request for system service */
-	SysTick_IRQn                      = -1,	/*!<  15  System Tick Timer                */
-
-	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
-	DAC_IRQn                          =   0,/*!<   0  DAC                              */
-	RESERVED0_IRQn                    =   1,
-	DMA_IRQn                          =   2,/*!<   2  DMA                              */
-	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
-	RESERVED2_IRQn                    =   4,
-	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
-	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
-	LCD_IRQn                          =   7,/*!<   7  LCD                              */
-	USB0_IRQn                         =   8,/*!<   8  USB0                             */
-	USB1_IRQn                         =   9,/*!<   9  USB1                             */
-	SCT_IRQn                          =  10,/*!<  10  SCT                              */
-	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
-	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
-	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
-	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
-	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
-	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
-	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
-	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
-	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
-	RESERVED3_IRQn                    =  20,
-	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
-	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
-	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
-	USART0_IRQn                       =  24,/*!<  24  USART0                           */
-	UART1_IRQn                        =  25,/*!<  25  UART1                            */
-	USART2_IRQn                       =  26,/*!<  26  USART2                           */
-	USART3_IRQn                       =  27,/*!<  27  USART3                           */
-	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
-	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
-	RESERVED4_IRQn                    =  30,
-	RESERVED5_IRQn                    =  31,
-	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
-	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
-	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
-	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
-	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
-	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
-	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
-	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
-	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
-	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
-	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
-	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
-	RESERVED6_IRQn                    =  44,
-	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
-	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
-	RTC_IRQn                          =  47,/*!<  47  RTC                              */
-	RESERVED8_IRQn                    =  48,
-	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
-	RESERVED9_IRQn                    =  50,
-	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
-	QEI_IRQn                          =  52,/*!<  52  QEI                              */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h"						/*!< Cortex-M3 processor and core peripherals */
-
-#elif defined(CORE_M0)
-/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions
- * @{
- */
-
-#define __MPU_PRESENT             0			/*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          2			/*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT             0			/*!< FPU present or not                    */
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
-	/* -------------------------  Cortex-M0 Processor Exceptions Numbers  ----------------------------- */
-	Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */
-	NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-	HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */
-	SVCall_IRQn                       = -5,	/*!<  11  System Service Call via SVC instruction */
-	DebugMonitor_IRQn                 = -4,	/*!<  12  Debug Monitor                    */
-	PendSV_IRQn                       = -2,	/*!<  14  Pendable request for system service */
-	SysTick_IRQn                      = -1,	/*!<  15  System Tick Timer           */
-
-	/* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */
-	DAC_IRQn                          =   0,/*!<   0  DAC                              */
-	M0_M4CORE_IRQn                        =   1,/*!<   1  M0a                              */
-	DMA_IRQn                          =   2,/*!<   2  DMA                              */
-	RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */
-	RESERVED2_IRQn                    =   4,
-	ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */
-	SDIO_IRQn                         =   6,/*!<   6  SDIO                             */
-	LCD_IRQn                          =   7,/*!<   7  LCD                              */
-	USB0_IRQn                         =   8,/*!<   8  USB0                             */
-	USB1_IRQn                         =   9,/*!<   9  USB1                             */
-	SCT_IRQn                          =  10,/*!<  10  SCT                              */
-	RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */
-	TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */
-	TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */
-	TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */
-	TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */
-	MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */
-	ADC0_IRQn                         =  17,/*!<  17  ADC0                             */
-	I2C0_IRQn                         =  18,/*!<  18  I2C0                             */
-	I2C1_IRQn                         =  19,/*!<  19  I2C1                             */
-	SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */
-	ADC1_IRQn                         =  21,/*!<  21  ADC1                             */
-	SSP0_IRQn                         =  22,/*!<  22  SSP0                             */
-	SSP1_IRQn                         =  23,/*!<  23  SSP1                             */
-	USART0_IRQn                       =  24,/*!<  24  USART0                           */
-	UART1_IRQn                        =  25,/*!<  25  UART1                            */
-	USART2_IRQn                       =  26,/*!<  26  USART2                           */
-	USART3_IRQn                       =  27,/*!<  27  USART3                           */
-	I2S0_IRQn                         =  28,/*!<  28  I2S0                             */
-	I2S1_IRQn                         =  29,/*!<  29  I2S1                             */
-	RESERVED4_IRQn                    =  30,
-	SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */
-	PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */
-	PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */
-	PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */
-	PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */
-	PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */
-	PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */
-	PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */
-	PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */
-	GINT0_IRQn                        =  40,/*!<  40  GINT0                            */
-	GINT1_IRQn                        =  41,/*!<  41  GINT1                            */
-	EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */
-	C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */
-	RESERVED6_IRQn                    =  44,
-	RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */
-	ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */
-	RTC_IRQn                          =  47,/*!<  47  RTC                              */
-	RESERVED8_IRQn                    =  48,
-	WWDT_IRQn                         =  49,/*!<  49  WWDT                             */
-	RESERVED9_IRQn                    =  50,
-	C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */
-	QEI_IRQn                          =  52,/*!<  52  QEI                              */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm0.h"						/*!< Cortex-M4 processor and core peripherals */
-#else
-#error Please #define CORE_M0, CORE_M3, or CORE_M4
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMSIS_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h
deleted file mode 100644
index 1b855c5b95..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * @brief LPC18XX/43XX CREG control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CREG_18XX_43XX_H_
-#define __CREG_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief CREG Register Block
- */
-typedef struct {						/*!< CREG Structure         */
-	__I  uint32_t  RESERVED0;
-	__IO uint32_t  CREG0;				/*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
-	__I  uint32_t  RESERVED1[62];
-	__IO uint32_t  MXMEMMAP;			/*!< ARM Cortex-M3/M4 memory mapping */
-#if defined(CHIP_LPC18XX)
-	__I  uint32_t  RESERVED2[5];
-#else
-	__I  uint32_t  RESERVED2;
-	__I  uint32_t  CREG1;				/*!< Configuration Register 1 */
-	__I  uint32_t  CREG2;				/*!< Configuration Register 2 */
-	__I  uint32_t  CREG3;				/*!< Configuration Register 3 */
-	__I  uint32_t  CREG4;				/*!< Configuration Register 4 */
-#endif
-	__IO uint32_t  CREG5;				/*!< Chip configuration register 5. Controls JTAG access. */
-	__IO uint32_t  DMAMUX;				/*!< DMA muxing control     */
-	__IO uint32_t  FLASHCFGA;			/*!< Flash accelerator configuration register for flash bank A */
-	__IO uint32_t  FLASHCFGB;			/*!< Flash accelerator configuration register for flash bank B */
-	__IO uint32_t  ETBCFG;				/*!< ETB RAM configuration  */
-	__IO uint32_t  CREG6;				/*!< Chip configuration register 6. */
-#if defined(CHIP_LPC18XX)
-	__I  uint32_t  RESERVED4[52];
-#else
-	__IO uint32_t  M4TXEVENT;			/*!< M4 IPC event register */
-	__I  uint32_t  RESERVED4[51];
-#endif
-	__I  uint32_t  CHIPID;				/*!< Part ID                */
-#if defined(CHIP_LPC18XX)
-	__I  uint32_t  RESERVED5[191];
-#else
-	__I  uint32_t  RESERVED5[127];
-	__IO uint32_t  M0TXEVENT;			/*!< M0 IPC Event register */
-	__IO uint32_t  M0APPMEMMAP;			/*!< ARM Cortex M0 memory mapping */
-	__I  uint32_t  RESERVED6[62];
-#endif
-	__IO uint32_t  USB0FLADJ;			/*!< USB0 frame length adjust register */
-	__I  uint32_t  RESERVED7[63];
-	__IO uint32_t  USB1FLADJ;			/*!< USB1 frame length adjust register */
-} LPC_CREG_T;
-
-/**
- * @brief	Identifies whether on-chip flash is present
- * @return	true if on chip flash is available, otherwise false
- */
-STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
-{
-	return LPC_CREG->CHIPID != 0x3284E02B;
-}
-
-/**
- * @brief	Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
- * @param	Hz	: Current frequency in Hz of the CPU
- * @return	Nothing
- * This function should be called with the higher frequency before the clock frequency is
- * increased and it should be called with the new lower value after the clock frequency is
- * decreased.
- */
-STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
-{
-	uint32_t FAValue = Hz / 21510000;
-
-	LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
-	LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
-}
-
-/**
- * @brief	Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
- * @param	Enable	: true to enable PHY, false to disable
- * @return	Nothing
- * The USB0 PLL & clock should be configured before calling this function. This function
- * should be called before the USB0 registers are accessed.
- */
-STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
-{
-	if (Enable) {
-		LPC_CREG->CREG0 &= ~(1 << 5);
-	}
-	else {
-		LPC_CREG->CREG0 |= (1 << 5);
-	}
-}
-
-/**
- * @brief	Configures the BOD and Reset on LPC18xx/LPC43xx parts.
- * @param	BODVL	: Brown-Out Detect voltage level (0-3)
- * @param	BORVL	: Brown-Out Reset voltage level (0-3)
- * @return	Nothing
- */
-STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
-{
-	LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
-}
-
-#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
-/**
- * @brief	Configures base address of image to be run in the Cortex M0 Core.
- * @param	memaddr	: Address of the image (must be aligned to 4K)
- * @return	Nothing
- */
-STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
-{
-	LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
-}
-
-/**
- * @brief	Clear M4 IPC Event
- * @return	Nothing
- */
-STATIC INLINE void Chip_CREG_ClearM4Event(void)
-{
-	LPC_CREG->M4TXEVENT = 0;
-}
-
-/**
- * @brief	Clear M0 IPC Event
- * @return	Nothing
- */
-STATIC INLINE void Chip_CREG_ClearM0Event(void)
-{
-	LPC_CREG->M0TXEVENT = 0;
-}
-
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CREG_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c
deleted file mode 100644
index 216f1c14e8..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * @brief LPC18xx/43xx EMC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "emc_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Dyanmic memory setup */
-void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config)
-{
-	uint32_t ClkFreq;
-	uint32_t EMCDiv;
-
-	/* Note clocks must be enabled prior to this call */
-	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
-
-	/* EMC Divider readback at pos 27
-	    TODO: just checked but dont mention in UM */
-	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
-
-	/* Check EMC Divider to get real EMC clock out */
-	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
-		ClkFreq >>= 1;
-	}
-
-	IP_EMC_Dynamic_Init(LPC_EMC, Dynamic_Config, ClkFreq);
-}
-
-/* Static memory setup */
-void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config)
-{
-	uint32_t ClkFreq;
-	uint32_t EMCDiv;
-
-	/* Note clocks must be enabled prior to this call */
-	ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
-
-	/* EMC Divider readback at pos 27 */
-	EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
-
-	/* Check EMC Divider to get real EMC clock out */
-	if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
-		ClkFreq >>= 1;
-	}
-
-	IP_EMC_Static_Init(LPC_EMC, Static_Config, ClkFreq);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h
deleted file mode 100644
index eaa95899b0..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * @brief LPC18xx/43xx EMC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EMC_18XX_43XX_H_
-#define __EMC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * Dynamic Chip Select Address
- */
-#define EMC_ADDRESS_DYCS0   (0x28000000)
-#define EMC_ADDRESS_DYCS1   (0x30000000)
-#define EMC_ADDRESS_DYCS2   (0x60000000)
-#define EMC_ADDRESS_DYCS3   (0x70000000)
-
-/**
- * Static Chip Select Address
- */
-#define EMC_ADDRESS_CS0     (0x1C000000)
-#define EMC_ADDRESS_CS1     (0x1D000000)
-#define EMC_ADDRESS_CS2     (0x1E000000)
-#define EMC_ADDRESS_CS3     (0x1F000000)
-
-/**
- * @brief	Dyanmic memory setup
- * @param	Dynamic_Config	: Pointer to dynamic memory setup data
- * @return	None
- */
-void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config);
-
-/**
- * @brief	Static memory setup
- * @param	Static_Config	: Pointer to static memory setup data
- * @return	None
- */
-void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config);
-
-/**
- * @brief	Set Deep Sleep Mode for Dynamic Memory Controller
- * @param	Enable	: 1 = enter DeepSleep Mode, 0 = Normal Mode
- * @return	None
- */
-STATIC INLINE void Chip_EMC_Dynamic_DeepSleepMode(uint32_t Enable)
-{
-	IP_EMC_Dynamic_DeepSleepMode(LPC_EMC, Enable);
-}
-
-/**
- * @brief	Enable Dynamic Memory Controller
- * @param	Enable	: 1 = Enable Dynamic Memory Controller, 0 = Disable
- * @return	None
- */
-STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable)
-{
-	IP_EMC_Dynamic_Enable(LPC_EMC, Enable);
-}
-
-/**
- * @brief	Mirror CS1 to CS0 and DYCS0
- * @param	Enable	: 1 = Mirror, 0 = Normal Memory Map
- * @return	None
- */
-STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable)
-{
-	IP_EMC_Mirror(LPC_EMC, Enable);
-}
-
-/**
- * @brief	Enable EMC
- * @param	Enable	: 1 = Enable, 0 = Disable
- * @return	None
- */
-STATIC INLINE void Chip_EMC_Enable(uint8_t Enable)
-{
-	IP_EMC_Enable(LPC_EMC, Enable);
-}
-
-/**
- * @brief	Set EMC LowPower Mode
- * @param	Enable	: 1 = Enable, 0 = Disable
- * @return	None
- */
-STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable)
-{
-	IP_EMC_LowPowerMode(LPC_EMC, Enable);
-}
-
-/**
- * @brief	Initialize EMC
- * @param	Enable		: 1 = Enable, 0 = Disable
- * @param	ClockRatio	: clock out ratio, 0 = 1:1, 1 = 1:2
- * @param	EndianMode	: Endian Mode, 0 = Little, 1 = Big
- * @return	None
- */
-STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
-{
-	IP_EMC_Init(LPC_EMC, Enable, ClockRatio, EndianMode);
-}
-
-/**
- * @brief	Set Static Memory Extended Wait in Clock
- * @param	Wait16Clks	: Number of '16 clock' delay cycles
- * @return	None
- */
-STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
-{
-	IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EMC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c
deleted file mode 100644
index dd08fb8c34..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * @brief LPC18xx/43xx ethernet driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "enet_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Basic Ethernet interface initialization */
-void Chip_ENET_Init(void)
-{
-	LPC_CREG->CREG6 &= ~0x7;
-
-	/* Enable ethernet clock */
-	Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
-
-	/* PHY TX/RX base clock routing is setup as part of SystemInit() */
-
-#if defined(USE_RMII)
-	LPC_CREG->CREG6 |= 0x4;
-#endif
-
-	/* Reset ethernet and wait for reset to complete */
-	Chip_RGU_TriggerReset(RGU_ETHERNET_RST);
-	while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}
-
-	/* Reset ethernet peripheral */
-	Chip_ENET_Reset();
-
-	/* Setup MII link divider to /102 and PHY address 1 */
-	Chip_ENET_Setup_MII(4, 1);
-
-	IP_ENET_Init(LPC_ETHERNET);
-}
-
-/* Ethernet interface shutdown */
-void Chip_ENET_DeInit(void)
-{
-	IP_ENET_DeInit(LPC_ETHERNET);
-	Chip_Clock_Disable(CLK_MX_ETHERNET);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h
deleted file mode 100644
index 09f536ddee..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * @brief LPC18xx/43xx ethernet driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ENET_18XX_43XX_H_
-#define __ENET_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @defgroup ENET_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Ethernet driver build options
- * @ingroup ENET_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS
- * The ethernet driver has options that configure it's operation at build-time.<br/>
- * USE_RMII:
- * - When defined, the driver will be built for RMII operation.
- * - When not defined, the driver will be built for MII operation.
- * <br/><p>
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH<br/>
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @brief	Initialize ethernet interface
- * @return	Nothing
- * Performs basic initialization of the ethernet interface in a default
- * state. This is enough to place the interface in a usable state, but
- * may require more setup outside this function.
- */
-void Chip_ENET_Init(void);
-
-/**
- * @brief	De-initialize the ethernet interface
- * @return	Nothing
- */
-void Chip_ENET_DeInit(void);
-
-/**
- * @brief	Resets the ethernet interface
- * @return	Nothing
- * Resets the ethernet interface. This should be called prior to
- * Chip_ENET_Init with a small delay after this call.
- */
-STATIC INLINE void Chip_ENET_Reset(void)
-{
-	IP_ENET_Reset(LPC_ETHERNET);
-}
-
-/**
- * @brief	Sets the address of the interface
- * @param	macAddr	: Pointer to the 6 bytes used for the MAC address
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_SetADDR(const uint8_t *macAddr)
-{
-	IP_ENET_SetADDR(LPC_ETHERNET, macAddr);
-}
-
-/**
- * @brief	Sets up the PHY link clock divider and PHY address
- * @param	div		: Divider value, may vary per chip
- * @param	addr	: PHY address, used with MII read and write
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_Setup_MII(uint32_t div, uint8_t addr)
-{
-	IP_ENET_SetupMII(LPC_ETHERNET, div, addr);
-}
-
-/**
- * @brief	Starts a PHY write via the MII
- * @param	reg		: PHY register to write
- * @param	data	: Data to write to PHY register
- * @return	Nothing
- * Start a PHY write operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when write is complete.
- */
-STATIC INLINE void Chip_ENET_Start_MII_Write(uint8_t reg, uint16_t data)
-{
-	IP_ENET_StartMIIWrite(LPC_ETHERNET, reg, data);
-}
-
-/**
- * @brief	Starts a PHY read via the MII
- * @param	reg	: PHY register to read
- * @return	Nothing
- * Start a PHY read operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when read is complete and calling
- * IP_ENET_ReadMIIData to get the data.
- */
-STATIC INLINE void Chip_ENET_Start_MII_Read(uint8_t reg)
-{
-	IP_ENET_StartMIIRead(LPC_ETHERNET, reg);
-}
-
-/**
- * @brief	Returns MII link (PHY) busy status
- * @return	Returns true if busy, otherwise false
- */
-STATIC INLINE bool Chip_ENET_Is_MII_Busy(void)
-{
-	return IP_ENET_IsMIIBusy(LPC_ETHERNET);
-}
-
-/**
- * @brief	Returns the value read from the PHY
- * @return	Read value from PHY
- */
-STATIC INLINE uint16_t Chip_ENET_Read_MII_Data(void)
-{
-	return IP_ENET_ReadMIIData(LPC_ETHERNET);
-}
-
-/**
- * @brief	Enables or disables ethernet transmit
- * @param	Enable	: true to enable transmit, false to disable
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_TX_Enable(bool Enable)
-{
-	IP_ENET_TXEnable(LPC_ETHERNET, Enable);
-}
-
-/**
- * @brief	Enables or disables ethernet packet reception
- * @param	Enable	: true to enable receive, false to disable
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_RX_Enable(bool Enable)
-{
-	IP_ENET_RXEnable(LPC_ETHERNET, Enable);
-}
-
-/**
- * @brief	Sets full or half duplex for the interface
- * @param	full	: true to selected full duplex, false for half
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_Set_Duplex(bool full)
-{
-	IP_ENET_SetDuplex(LPC_ETHERNET, full);
-}
-
-/**
- * @brief	Sets speed for the interface
- * @param	speed100	: true to select 100Mbps mode, false for 10Mbps
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_Set_Speed(bool speed100)
-{
-	IP_ENET_SetSpeed(LPC_ETHERNET, speed100);
-}
-
-/**
- * @brief	Configures the initial ethernet descriptors
- * @param	pTXDescs	: Pointer to TX descriptor list
- * @param	pRXDescs	: Pointer to RX descriptor list
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_InitDescriptors(
-	IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs)
-{
-	IP_ENET_InitDescriptors(LPC_ETHERNET, pTXDescs, pRXDescs);
-}
-
-/**
- * @brief	Starts receive polling of RX descriptors
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_RXStart(void)
-{
-	IP_ENET_RXStart(LPC_ETHERNET);
-}
-
-/**
- * @brief	Starts transmit polling of TX descriptors
- * @return	Nothing
- */
-STATIC INLINE void Chip_ENET_TXStart(void)
-{
-	IP_ENET_TXStart(LPC_ETHERNET);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ENET_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c
deleted file mode 100644
index 050fdaffbb..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * @brief LPC18xx/43xx event router driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "evrt_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the EVRT */
-void Chip_EVRT_Init(void)
-{
-	uint8_t i = 0;
-	// Clear all register to be default
-	LPC_EVRT->HILO      = 0x0000;
-	LPC_EVRT->EDGE      = 0x0000;
-	LPC_EVRT->CLR_EN    = 0xFFFF;
-	do {
-		i++;
-		LPC_EVRT->CLR_STAT  = 0xFFFFF;
-	} while ((LPC_EVRT->STATUS != 0) && (i < 10));
-}
-
-/* Set up the type of interrupt type for a source to EVRT */
-void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type)
-{
-	switch (type) {
-	case EVRT_SRC_ACTIVE_LOW_LEVEL:
-		LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
-		LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
-		break;
-
-	case EVRT_SRC_ACTIVE_HIGH_LEVEL:
-		LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
-		LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
-		break;
-
-	case EVRT_SRC_ACTIVE_FALLING_EDGE:
-		LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
-		LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
-		break;
-
-	case EVRT_SRC_ACTIVE_RISING_EDGE:
-		LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
-		LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Enable or disable interrupt sources to EVRT */
-void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state)
-{
-	if (state == ENABLE) {
-		LPC_EVRT->SET_EN = (1 << (uint8_t) EVRT_Src);
-	}
-	else {
-		LPC_EVRT->CLR_EN = (1 << (uint8_t) EVRT_Src);
-	}
-}
-
-/* Check if a source is sending interrupt to EVRT */
-IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src)
-{
-	if (LPC_EVRT->STATUS & (1 << (uint8_t) EVRT_Src)) {
-		return SET;
-	}
-	else {return RESET; }
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h
deleted file mode 100644
index 7db552be6b..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * @brief LPC18xx/43xx event router driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EVRT_18XX_43XX_H_
-#define __EVRT_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Event Router register structure
- */
-typedef struct {						/*!< EVENTROUTER Structure  */
-	__IO uint32_t HILO;					/*!< Level configuration register */
-	__IO uint32_t EDGE;					/*!< Edge configuration     */
-	__I  uint32_t RESERVED0[1012];
-	__O  uint32_t CLR_EN;				/*!< Event clear enable register */
-	__O  uint32_t SET_EN;				/*!< Event set enable register */
-	__I  uint32_t STATUS;				/*!< Status register        */
-	__I  uint32_t ENABLE;				/*!< Enable register        */
-	__O  uint32_t CLR_STAT;				/*!< Clear register         */
-	__O  uint32_t SET_STAT;				/*!< Set register           */
-} LPC_EVRT_Type;
-
-/**
- * @brief EVRT input sources
- */
-typedef enum {
-	EVRT_SRC_WAKEUP0,			/*!< WAKEUP0 event router source		*/
-	EVRT_SRC_WAKEUP1,			/*!< WAKEUP1 event router source		*/
-	EVRT_SRC_WAKEUP2,			/*!< WAKEUP2 event router source		*/
-	EVRT_SRC_WAKEUP3,			/*!< WAKEUP3 event router source		*/
-	EVRT_SRC_ATIMER,			/*!< Alarm timer event router source	*/
-	EVRT_SRC_RTC,				/*!< RTC event router source			*/
-	EVRT_SRC_BOD1,				/*!< BOD event router source			*/
-	EVRT_SRC_WWDT,				/*!< WWDT event router source			*/
-	EVRT_SRC_ETHERNET,			/*!< Ethernet event router source		*/
-	EVRT_SRC_USB0,				/*!< USB0 event router source			*/
-	EVRT_SRC_USB1,				/*!< USB1 event router source			*/
-	EVRT_SRC_SDIO,				/*!< Reserved							*/
-	EVRT_SRC_CCAN,				/*!< C_CAN event router source			*/
-	EVRT_SRC_COMBINE_TIMER2,	/*!< Combined timer 2 event router source	*/
-	EVRT_SRC_COMBINE_TIMER6,	/*!< Combined timer 6 event router source	*/
-	EVRT_SRC_QEI,				/*!< QEI event router source			*/
-	EVRT_SRC_COMBINE_TIMER14,	/*!< Combined timer 14 event router source	*/
-	EVRT_SRC_RESERVED1,			/*!< Reserved                           */
-	EVRT_SRC_RESERVED2,			/*!< Reserved							*/
-	EVRT_SRC_RESET				/*!< Reset event router source			*/
-} Chip_EVRT_SRC_ENUM;
-
-/**
- * @brief Macro for checking for a valid EVRT source
- */
-#define PARAM_EVRT_SOURCE(n)    ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1)	\
-								 || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \
-								 || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \
-								 || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \
-								 || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \
-								 || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \
-								 || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \
-								 || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \
-								 || (n == EVRT_SRC_RESET)) \
-
-/**
- * @brief EVRT input state detecting type
- */
-typedef enum {
-	EVRT_SRC_ACTIVE_LOW_LEVEL,		/*!< Active low level       */
-	EVRT_SRC_ACTIVE_HIGH_LEVEL,		/*!< Active high level		*/
-	EVRT_SRC_ACTIVE_FALLING_EDGE,	/*!< Active falling edge	*/
-	EVRT_SRC_ACTIVE_RISING_EDGE		/*!< Active rising edge		*/
-} EVRT_SRC_ACTIVE_TYPE;
-
-/**
- * @brief Macro for checking for a valid EVRT state type
- */
-#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL)	\
-										  || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))
-
-/**
- * @brief	Initialize the EVRT
- * @return	Nothing
- */
-void Chip_EVRT_Init (void);
-
-/**
- * @brief	Set up the type of interrupt type for a source to EVRT
- * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @param	type		: EVRT type, should be one of EVRT_SRC_ACTIVE_TYPE type
- * @return	Nothing
- */
-void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
-
-/**
- * @brief	Check if a source is sending interrupt to EVRT
- * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @return	true if the interrupt from the source is pending, otherwise false
- */
-IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src);
-
-/**
- * @brief	Enable or disable interrupt sources to EVRT
- * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @param	state		: ENABLE or DISABLE to enable or disable event router source
- * @return	Nothing
- */
-void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
-
-/**
- * @brief	De-initializes the EVRT peripheral
- * @return	Nothing
- */
-STATIC INLINE void Chip_EVRT_DeInit(void)
-{
-	LPC_EVRT->CLR_EN    = 0xFFFF;
-	LPC_EVRT->CLR_STAT  = 0xFFFF;
-}
-
-/**
- * @brief	Clear pending interrupt EVRT source
- * @param	EVRT_Src	: EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @return	Nothing
- */
-STATIC INLINE void Chip_EVRT_ClrPendIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src)
-{
-	LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EVRT_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c
deleted file mode 100644
index ff9f9782eb..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * @brief LPC18xx/43xx DMA driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpdma_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Channel array to monitor free channel */
-static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS];
-
-/* Optimized Peripheral Source and Destination burst size (18xx,43xx) */
-static const uint8_t GPDMA_LUTPerBurst[] = {
-	GPDMA_BSIZE_4,	/* MEMORY             */
-	GPDMA_BSIZE_1,	/* MAT0.0             */
-	GPDMA_BSIZE_1,	/* UART0 Tx           */
-	GPDMA_BSIZE_1,	/* MAT0.1             */
-	GPDMA_BSIZE_1,	/* UART0 Rx           */
-	GPDMA_BSIZE_1,	/* MAT1.0             */
-	GPDMA_BSIZE_1,	/* UART1 Tx           */
-	GPDMA_BSIZE_1,	/* MAT1.1             */
-	GPDMA_BSIZE_1,	/* UART1 Rx           */
-	GPDMA_BSIZE_1,	/* MAT2.0             */
-	GPDMA_BSIZE_1,	/* UART2 Tx           */
-	GPDMA_BSIZE_1,	/* MAT2.1             */
-	GPDMA_BSIZE_1,	/* UART2 Rx           */
-	GPDMA_BSIZE_1,	/* MAT3.0             */
-	GPDMA_BSIZE_1,	/* UART3 Tx           */
-	0,				/* SCT timer channel 0*/
-	GPDMA_BSIZE_1,	/* MAT3.1             */
-	GPDMA_BSIZE_1,	/* UART3 Rx           */
-	0,				/* SCT timer channel 1*/
-	GPDMA_BSIZE_4,	/* SSP0 Rx            */
-	GPDMA_BSIZE_32,	/* I2S channel 0      */
-	GPDMA_BSIZE_4,	/* SSP0 Tx            */
-	GPDMA_BSIZE_32,	/* I2S channel 1      */
-	GPDMA_BSIZE_4,	/* SSP1 Rx            */
-	GPDMA_BSIZE_4,	/* SSP1 Tx            */
-	GPDMA_BSIZE_4,	/* ADC 0              */
-	GPDMA_BSIZE_4,	/* ADC 1              */
-	GPDMA_BSIZE_1,	/* DAC                */
-	GPDMA_BSIZE_32,	/* I2S channel 0      */
-	GPDMA_BSIZE_32	/* I2S channel 0      */
-};
-
-/* Optimized Peripheral Source and Destination transfer width (18xx,43xx) */
-static const uint8_t GPDMA_LUTPerWid[] = {
-	GPDMA_WIDTH_WORD,	/* MEMORY             */
-	GPDMA_WIDTH_WORD,	/* MAT0.0             */
-	GPDMA_WIDTH_BYTE,	/* UART0 Tx           */
-	GPDMA_WIDTH_WORD,	/* MAT0.1             */
-	GPDMA_WIDTH_BYTE,	/* UART0 Rx           */
-	GPDMA_WIDTH_WORD,	/* MAT1.0             */
-	GPDMA_WIDTH_BYTE,	/* UART1 Tx           */
-	GPDMA_WIDTH_WORD,	/* MAT1.1             */
-	GPDMA_WIDTH_BYTE,	/* UART1 Rx           */
-	GPDMA_WIDTH_WORD,	/* MAT2.0             */
-	GPDMA_WIDTH_BYTE,	/* UART2 Tx           */
-	GPDMA_WIDTH_WORD,	/* MAT2.1             */
-	GPDMA_WIDTH_BYTE,	/* UART2 Rx           */
-	GPDMA_WIDTH_WORD,	/* MAT3.0             */
-	GPDMA_WIDTH_BYTE,	/* UART3 Tx           */
-	0,					/* SCT timer channel 0*/
-	GPDMA_WIDTH_WORD,	/* MAT3.1             */
-	GPDMA_WIDTH_BYTE,	/* UART3 Rx           */
-	0,					/* SCT timer channel 1*/
-	GPDMA_WIDTH_BYTE,	/* SSP0 Rx            */
-	GPDMA_WIDTH_WORD,	/* I2S channel 0      */
-	GPDMA_WIDTH_BYTE,	/* SSP0 Tx            */
-	GPDMA_WIDTH_WORD,	/* I2S channel 1      */
-	GPDMA_WIDTH_BYTE,	/* SSP1 Rx            */
-	GPDMA_WIDTH_BYTE,	/* SSP1 Tx            */
-	GPDMA_WIDTH_WORD,	/* ADC 0              */
-	GPDMA_WIDTH_WORD,	/* ADC 1              */
-	GPDMA_WIDTH_WORD,	/* DAC                */
-	GPDMA_WIDTH_WORD,	/* I2S channel 0      */
-	GPDMA_WIDTH_WORD/* I2S channel 0      */
-};
-
-/* Lookup Table of Connection Type matched with (18xx,43xx) Peripheral Data (FIFO) register base address */
-volatile static const void *GPDMA_LUTPerAddr[] = {
-	NULL,							/* MEMORY             */
-	(&LPC_TIMER0->MR),				/* MAT0.0             */
-	(&LPC_USART0-> /*RBTHDLR.*/ THR),	/* UART0 Tx           */
-	((uint32_t *) &LPC_TIMER0->MR + 1),	/* MAT0.1             */
-	(&LPC_USART0-> /*RBTHDLR.*/ RBR),	/* UART0 Rx           */
-	(&LPC_TIMER1->MR),				/* MAT1.0             */
-	(&LPC_UART1-> /*RBTHDLR.*/ THR),/* UART1 Tx           */
-	((uint32_t *) &LPC_TIMER1->MR + 1),	/* MAT1.1             */
-	(&LPC_UART1-> /*RBTHDLR.*/ RBR),/* UART1 Rx           */
-	(&LPC_TIMER2->MR),				/* MAT2.0             */
-	(&LPC_USART2-> /*RBTHDLR.*/ THR),	/* UART2 Tx           */
-	((uint32_t *) &LPC_TIMER2->MR + 1),	/* MAT2.1             */
-	(&LPC_USART2-> /*RBTHDLR.*/ RBR),	/* UART2 Rx           */
-	(&LPC_TIMER3->MR),				/* MAT3.0             */
-	(&LPC_USART3-> /*RBTHDLR.*/ THR),	/* UART3 Tx           */
-	0,								/* SCT timer channel 0*/
-	((uint32_t *) &LPC_TIMER3->MR + 1),	/* MAT3.1             */
-	(&LPC_USART3-> /*RBTHDLR.*/ RBR),	/* UART3 Rx           */
-	0,								/* SCT timer channel 1*/
-	(&LPC_SSP0->DR),				/* SSP0 Rx            */
-	(&LPC_I2S0->TXFIFO),			/* I2S channel 0      */
-	(&LPC_SSP0->DR),				/* SSP0 Tx            */
-	(&LPC_I2S0->RXFIFO),			/* I2S channel 1      */
-	(&LPC_SSP1->DR),				/* SSP1 Rx            */
-	(&LPC_SSP1->DR),				/* SSP1 Tx            */
-	(&LPC_ADC0->GDR),				/* ADC 0              */
-	(&LPC_ADC1->GDR),				/* ADC 1              */
-	(&LPC_DAC->CR),					/* DAC                */
-	(&LPC_I2S0->TXFIFO),			/* I2S channel 0      */
-	(&LPC_I2S0->RXFIFO)				/* I2S channel 0      */
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Control which set of peripherals is connected to the DMA controller */
-static uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)
-{
-	uint8_t function, channel;
-
-	switch (gpdma_peripheral_connection_number) {
-	case GPDMA_CONN_MAT0_0:
-		function = 0;
-		channel = 1;
-		break;
-
-	case GPDMA_CONN_UART0_Tx:
-		function = 1;
-		channel = 1;
-		break;
-
-	case GPDMA_CONN_MAT0_1:
-		function = 0;
-		channel = 2;
-		break;
-
-	case GPDMA_CONN_UART0_Rx:
-		function = 1;
-		channel = 2;
-		break;
-
-	case GPDMA_CONN_MAT1_0:
-		function = 0;
-		channel = 3;
-		break;
-
-	case GPDMA_CONN_UART1_Tx:
-		function = 1;
-		channel = 3;
-		break;
-
-	case GPDMA_CONN_MAT1_1:
-		function = 0;
-		channel = 4;
-		break;
-
-	case GPDMA_CONN_UART1_Rx:
-		function = 1;
-		channel = 4;
-		break;
-
-	case GPDMA_CONN_MAT2_0:
-		function = 0;
-		channel = 5;
-		break;
-
-	case GPDMA_CONN_UART2_Tx:
-		function = 1;
-		channel = 5;
-		break;
-
-	case GPDMA_CONN_MAT2_1:
-		function = 0;
-		channel = 6;
-		break;
-
-	case GPDMA_CONN_UART2_Rx:
-		function = 1;
-		channel = 6;
-		break;
-
-	case GPDMA_CONN_MAT3_0:
-		function = 0;
-		channel = 7;
-		break;
-
-	case GPDMA_CONN_UART3_Tx:
-		function = 1;
-		channel = 7;
-		break;
-
-	case GPDMA_CONN_SCT_0:
-		function = 2;
-		channel = 7;
-		break;
-
-	case GPDMA_CONN_MAT3_1:
-		function = 0;
-		channel = 8;
-		break;
-
-	case GPDMA_CONN_UART3_Rx:
-		function = 1;
-		channel = 8;
-		break;
-
-	case GPDMA_CONN_SCT_1:
-		function = 2;
-		channel = 8;
-		break;
-
-	case GPDMA_CONN_SSP0_Rx:
-		function = 0;
-		channel = 9;
-		break;
-
-	case GPDMA_CONN_I2S_Tx_Channel_0:
-	case GPDMA_CONN_I2S_Rx_Channel_0:
-		function = 1;
-		channel = 9;
-		break;
-
-	case GPDMA_CONN_SSP0_Tx:
-		function = 0;
-		channel = 10;
-		break;
-
-	case GPDMA_CONN_I2S_Tx_Channel_1:
-	case GPDMA_CONN_I2S_Rx_Channel_1:
-		function = 1;
-		channel = 10;
-		break;
-
-	case GPDMA_CONN_SSP1_Rx:
-		function = 0;
-		channel = 11;
-		break;
-
-	case GPDMA_CONN_SSP1_Tx:
-		function = 0;
-		channel = 12;
-		break;
-
-	case GPDMA_CONN_ADC_0:
-		function = 0;
-		channel = 13;
-		break;
-
-	case GPDMA_CONN_ADC_1:
-		function = 0;
-		channel = 14;
-		break;
-
-	case GPDMA_CONN_DAC:
-		function = 0;
-		channel = 15;
-		break;
-
-	default:
-		function = 3;
-		channel = 15;
-		break;
-	}
-	/* Set select function to dmamux register */
-	if (0 != gpdma_peripheral_connection_number) {
-		LPC_CREG->DMAMUX &= ~(0x03 << (2 * channel));
-		LPC_CREG->DMAMUX |= (function << (2 * channel));
-	}
-	return channel;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the GPDMA */
-void Chip_GPDMA_Init(void)
-{
-	uint8_t i;
-	IP_GPDMA_Init(LPC_GPDMA);
-	/* Reset all channels are free */
-	for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++)
-		ChannelHandlerArray[i].ChannelStatus = DISABLE;
-}
-
-/* Stop a stream DMA transfer */
-void Chip_DMA_Stop(uint8_t ChannelNum)
-{
-	IP_GPDMA_ChannelCmd(LPC_GPDMA, (ChannelNum), DISABLE);
-	if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) {
-		/* Clear terminate counter Interrupt pending */
-		Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum);
-	}
-	if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) {
-		/* Clear terminate counter Interrupt pending */
-		Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum);
-	}
-	ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE;
-}
-
-/* The GPDMA stream interrupt status checking */
-Status Chip_DMA_Interrupt(uint8_t ChannelNum)
-{
-
-	if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INT, ChannelNum)) {
-		/* Check counter terminal status */
-		if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) {
-			/* Clear terminate counter Interrupt pending */
-			Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum);
-			return SUCCESS;
-		}
-		/* Check error terminal status */
-		if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) {
-			/* Clear error counter Interrupt pending */
-
-			Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum);
-			return ERROR;
-		}
-	}
-	return ERROR;
-}
-
-/* Do a DMA transfer M2M, M2P,P2M or P2P */
-void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size)
-{
-	GPDMA_Channel_CFG_Type GPDMACfg;
-	uint8_t SrcPeripheral = 0, DstPeripheral = 0;
-
-	GPDMACfg.ChannelNum = ChannelNum;
-	GPDMACfg.TransferType = TransferType;
-	GPDMACfg.TransferSize = Size;
-
-	switch (TransferType) {
-	case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
-		GPDMACfg.SrcAddr = (uint32_t) src;
-		GPDMACfg.DstAddr = (uint32_t) dst;
-		src = 0; dst = 0;
-		GPDMACfg.TransferWidth = GPDMA_WIDTH_BYTE;
-		break;
-
-	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
-	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
-		GPDMACfg.SrcAddr = (uint32_t) src;
-		src = 0;
-		GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
-		DstPeripheral = DMAMUX_Config(dst);
-		break;
-
-	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
-	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
-		GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
-		GPDMACfg.DstAddr = (uint32_t) dst;
-		SrcPeripheral = DMAMUX_Config(src);
-		dst = 0;
-		break;
-
-	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
-	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
-	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
-		GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
-		GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
-		SrcPeripheral = DMAMUX_Config(src);
-		DstPeripheral = DMAMUX_Config(dst);
-		break;
-
-	default:
-		break;
-	}
-
-	IP_GPDMA_Setup(LPC_GPDMA, &GPDMACfg, (uint32_t) GPDMA_LUTPerBurst[src], (uint32_t) GPDMA_LUTPerBurst[dst],
-				   (uint32_t) GPDMA_LUTPerWid[src], (uint32_t) GPDMA_LUTPerWid[dst], (uint32_t) GPDMA_LUTPerAddr[src],
-				   (uint32_t) GPDMA_LUTPerAddr[dst], SrcPeripheral, DstPeripheral);
-
-	/* Start the Channel */
-	IP_GPDMA_ChannelCmd(LPC_GPDMA, ChannelNum, ENABLE);
-}
-
-/* Get a free GPDMA channel for one DMA connection */
-uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID)
-{
-	uint8_t temp = 0;
-	for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++)
-		if (!Chip_GPDMA_IntGetStatus(GPDMA_STAT_ENABLED_CH,
-									 temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) {
-			ChannelHandlerArray[temp].ChannelStatus = ENABLE;
-			return temp;
-		}
-	return 0;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h
deleted file mode 100644
index d96b076847..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * @brief LPC18xx/43xx DMA driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPDMA_18XX_43XX_H_
-#define __GPDMA_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** Number of channels on GPDMA */
-#define GPDMA_NUMBER_CHANNELS 8
-
-/** DMA Connection number definitions */
-#define GPDMA_CONN_MEMORY           ((0UL))			/**< MEMORY             */
-#define GPDMA_CONN_MAT0_0           ((1UL))			/**< MAT0.0             */
-#define GPDMA_CONN_UART0_Tx         ((2UL))			/**< UART0 Tx           */
-#define GPDMA_CONN_MAT0_1           ((3UL))			/**< MAT0.1             */
-#define GPDMA_CONN_UART0_Rx         ((4UL))			/**< UART0 Rx           */
-#define GPDMA_CONN_MAT1_0           ((5UL))			/**< MAT1.0             */
-#define GPDMA_CONN_UART1_Tx         ((6UL))			/**< UART1 Tx           */
-#define GPDMA_CONN_MAT1_1           ((7UL))			/**< MAT1.1             */
-#define GPDMA_CONN_UART1_Rx         ((8UL))			/**< UART1 Rx           */
-#define GPDMA_CONN_MAT2_0           ((9UL))			/**< MAT2.0             */
-#define GPDMA_CONN_UART2_Tx         ((10UL))		/**< UART2 Tx           */
-#define GPDMA_CONN_MAT2_1           ((11UL))		/**< MAT2.1             */
-#define GPDMA_CONN_UART2_Rx         ((12UL))		/**< UART2 Rx           */
-#define GPDMA_CONN_MAT3_0           ((13UL))		/**< MAT3.0             */
-#define GPDMA_CONN_UART3_Tx         ((14UL))		/**< UART3 Tx           */
-#define GPDMA_CONN_SCT_0            ((15UL))		/**< SCT timer channel 0*/
-#define GPDMA_CONN_MAT3_1           ((16UL))		/**< MAT3.1             */
-#define GPDMA_CONN_UART3_Rx         ((17UL))		/**< UART3 Rx           */
-#define GPDMA_CONN_SCT_1            ((18UL))		/**< SCT timer channel 1*/
-#define GPDMA_CONN_SSP0_Rx          ((19UL))		/**< SSP0 Rx            */
-#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))		/**< I2S channel 0      */
-#define GPDMA_CONN_SSP0_Tx          ((21UL))		/**< SSP0 Tx            */
-#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))		/**< I2S channel 1      */
-#define GPDMA_CONN_SSP1_Rx          ((23UL))		/**< SSP1 Rx            */
-#define GPDMA_CONN_SSP1_Tx          ((24UL))		/**< SSP1 Tx            */
-#define GPDMA_CONN_ADC_0            ((25UL))		/**< ADC 0              */
-#define GPDMA_CONN_ADC_1            ((26UL))		/**< ADC 1              */
-#define GPDMA_CONN_DAC              ((27UL))		/**< DAC                */
-#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL))		/**< I2S channel 0      */
-#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL))		/**< I2S channel 0      */
-
-/** Burst size in Source and Destination definitions */
-#define GPDMA_BSIZE_1   ((0UL))	/**< Burst size = 1 */
-#define GPDMA_BSIZE_4   ((1UL))	/**< Burst size = 4 */
-#define GPDMA_BSIZE_8   ((2UL))	/**< Burst size = 8 */
-#define GPDMA_BSIZE_16  ((3UL))	/**< Burst size = 16 */
-#define GPDMA_BSIZE_32  ((4UL))	/**< Burst size = 32 */
-#define GPDMA_BSIZE_64  ((5UL))	/**< Burst size = 64 */
-#define GPDMA_BSIZE_128 ((6UL))	/**< Burst size = 128 */
-#define GPDMA_BSIZE_256 ((7UL))	/**< Burst size = 256 */
-
-/** Width in Source transfer width and Destination transfer width definitions */
-#define GPDMA_WIDTH_BYTE        ((0UL))	/**< Width = 1 byte */
-#define GPDMA_WIDTH_HALFWORD    ((1UL))	/**< Width = 2 bytes */
-#define GPDMA_WIDTH_WORD        ((2UL))	/**< Width = 4 bytes */
-
-/** Flow control definitions */
-#define DMA_CONTROLLER 0		/**< Flow control is DMA controller*/
-#define SRC_PER_CONTROLLER 1	/**< Flow control is Source peripheral controller*/
-#define DST_PER_CONTROLLER 2	/**< Flow control is Destination peripheral controller*/
-
-typedef struct {
-	FunctionalState ChannelStatus;
-} DMA_ChannelHandle_t;
-
-#define Chip_GPDMA_IntGetStatus(type, channel) IP_GPDMA_IntGetStatus(LPC_GPDMA, type, channel)
-
-#define Chip_GPDMA_ClearIntPending(type, channel) IP_GPDMA_ClearIntPending(LPC_GPDMA, type, channel)
-
-#define Chip_GPDMA_ChannelCmd(channelNum, NewState) IP_GPDMA_ChannelCmd(LPC_GPDMA, channelNum, NewState)
-
-/**
- * @brief	Initialize the GPDMA
- * @return	Nothing
- */
-void Chip_GPDMA_Init(void);
-
-/**
- * @brief	Stop a stream DMA transfer
- * @param	ChannelNum	:	Channel Number to be closed
- * @return	Nothing
- */
-void Chip_DMA_Stop(uint8_t ChannelNum);
-
-/**
- * @brief	The GPDMA stream interrupt status checking
- * @param	ChannelNum		:	Channel Number to be checked on interruption
- * @return	Status:
- *              - SUCCESS	: DMA transfer success
- *              - ERROR		: DMA transfer failed
- */
-Status  Chip_DMA_Interrupt(uint8_t ChannelNum);
-
-/**
- * @brief	Get a free GPDMA channel for one DMA connection
- * @param	PeripheralConnection_ID		:	Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )
- * @return	The channel number which is selected
- */
-uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID);
-
-/**
- * @brief	Do a DMA transfer M2M, M2P,P2M or P2P
- * @param	ChannelNum		:	Channel used for transfer
- * @param	src				:	Address of Memory or PeripheralConnection_ID which is the source
- * @param	dst				:	Address of Memory or PeripheralConnection_ID which is the destination
- * @param	TransferType	:	Select the transfer controller and the type of transfer. Should be:
- *                               - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
- *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
- *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
- *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
- *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
- *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
- *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
- *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
- * @param	Size			:	The number of DMA transfers
- * @return	Nothing
- */
-void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPDMA_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c
deleted file mode 100644
index ca28b96ddf..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/** @brief LPC18xx/43xx GPIO driver** Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpio_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Set Direction for a GPIO port */
-void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
-{
-	if (out) {
-		LPC_GPIO_PORT->DIR[portNum] |= bitValue;
-	}
-	else {
-		LPC_GPIO_PORT->DIR[portNum] &= ~bitValue;
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h
deleted file mode 100644
index 96c10d7bdd..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * @brief LPC18xx/43xx GPIO driver
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIO_18XX_43XX_H_
-#define __GPIO_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Initialize GPIO block
- * @return	Nothing
- */
-STATIC INLINE void Chip_GPIO_Init(void)
-{
-	IP_GPIO_Init(LPC_GPIO_PORT);
-}
-
-/**
- * @brief	Set a GPIO port/bit state
- * @param	Port	: GPIO port to set
- * @param	Bit		: GPIO bit to set
- * @param	Setting	: true for high, false for low
- * @return	Nothing
- */
-STATIC INLINE void Chip_GPIO_WritePortBit(uint32_t Port, uint8_t Bit, bool Setting)
-{
-	IP_GPIO_WritePortBit(LPC_GPIO_PORT, Port, Bit, Setting);
-}
-
-/**
- * @brief	Seta GPIO direction
- * @param	Port	: GPIO port to set
- * @param	Bit		: GPIO bit to set
- * @param	Setting	: true for output, false for input
- * @return	Nothing
- */
-STATIC INLINE void Chip_GPIO_WriteDirBit(uint32_t Port, uint8_t Bit, bool Setting)
-{
-	IP_GPIO_WriteDirBit(LPC_GPIO_PORT, Port, Bit, Setting);
-}
-
-/**
- * @brief	Read a GPIO state
- * @param	Port	: GPIO port to read
- * @param	Bit		: GPIO bit to read
- * @return	true of the GPIO is high, false if low
- */
-STATIC INLINE bool Chip_GPIO_ReadPortBit(uint32_t Port, uint8_t Bit)
-{
-	return IP_GPIO_ReadPortBit(LPC_GPIO_PORT, Port, Bit);
-}
-
-/**
- * @brief	Read a GPIO direction (out ot in)
- * @param	Port	: GPIO port to read
- * @param	Bit		: GPIO bit to read
- * @return	true of the GPIO is an output, false if input
- */
-STATIC INLINE bool Chip_GPIO_ReadDirBit(uint32_t Port, uint8_t Bit)
-{
-	return IP_GPIO_ReadDirBit(LPC_GPIO_PORT, Port, Bit);
-}
-
-/**
- * @brief	Enable GPIO Interrupt
- * @param	PortNum		: GPIO port number interrupt, should be: 0 to 7
- * @param	BitValue	: GPIO bit to enable (Not used)
- * @param	IntMode		: Interrupt mode, should be:
- *							0: Rising edge interrupt mode
- *							1: Falling edge interrupt mode
- *							2: Active-High interrupt mode
- *							3: Active-Low interrupt mode
- * @return	None
- */
-STATIC INLINE void Chip_GPIO_IntCmd(uint8_t PortNum, uint8_t BitValue, Gpio_PinInt_Mode_Enum IntMode)
-{
-	IP_GPIOPININT_IntCmd(LPC_GPIO_PIN_INT, PortNum, IntMode);
-}
-
-/**
- * @brief	Get GPIO Interrupt Status
- * @param	PortNum		: GPIO port number interrupt, should be: 0 to 7
- * @param	PinNum		: GPIO pin to check (Not used)
- * @param	IntMode		: Interrupt mode (Not used)
- * @return	true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool Chip_GPIO_IntGetStatus(uint8_t PortNum, uint8_t PinNum, uint8_t IntMode)
-{
-	return IP_GPIOPININT_IntGetStatus(LPC_GPIO_PIN_INT, PortNum);
-}
-
-/**
- * @brief	Clear GPIO Interrupt (Edge interrupt cases only)
- * @param	PortNum		: GPIO port number interrupt, should be: 0 to 7
- * @param	BitValue	: GPIO bit to clear (Not used)
- * @return	None
- */
-STATIC INLINE void Chip_GPIO_IntClear(uint8_t PortNum, uint8_t BitValue)
-{
-	IP_GPIOPININT_IntClear(LPC_GPIO_PIN_INT, PortNum);
-}
-
-/**
- * @brief	GPIO Group Interrupt Pin Initialization
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @param	PortComb	: GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)
- * @param	PortTrigger	: GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)
- * @return	None
- */
-STATIC INLINE void Chip_GPIOGP_IntInit(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)
-{
-	IP_GPIOGP_IntInit(pGPIOGPINT, PortComb, PortTrigger);
-}
-
-/**
- * @brief	GPIO Group Interrupt Pin Add to Group
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @param	PortNum		: GPIO port number, should be 0 to 7
- * @param	PinNum		: GPIO pin number, should be 0 to 31
- * @param	ActiveMode	: GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)
- * @return	None
- */
-STATIC INLINE void Chip_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT,
-								  uint8_t PortNum,
-								  uint8_t PinNum,
-								  bool ActiveMode)
-{
-	IP_GPIOGP_IntPinAdd(pGPIOGPINT, PortNum, PinNum, ActiveMode);
-}
-
-/**
- * @brief	GPIO Group Interrupt Pin Remove from Group
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @param	PortNum		: GPIO port number, should be 0 to 7
- * @param	PinNum		: GPIO pin number, should be 0 to 31
- * @return	None
- */
-STATIC INLINE void Chip_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)
-{
-	IP_GPIOGP_IntPinRemove(pGPIOGPINT, PortNum, PinNum);
-}
-
-/**
- * @brief	Get GPIO Group Interrupt Get Status
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @return	true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool Chip_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
-{
-	return IP_GPIOGP_IntGetStatus(pGPIOGPINT);
-}
-
-/**
- * @brief	Clear GPIO Group Interrupt
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @return	None
- */
-STATIC INLINE void Chip_GPIOGP_IntClear(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
-{
-	IP_GPIOGP_IntClear(pGPIOGPINT);
-}
-
-/**
- * @brief	Set Direction for a GPIO port
- * @param	portNum		: Port Number
- * @param	bitValue	: GPIO bit to set
- * @param	out			: Direction value, 0 = input, !0 = output
- * @return	None
- * Bits set to '0' are not altered.
- */
-void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out);
-
-/**
- * @brief	Set Direction for a GPIO port
- * @param	portNum		: Port Number
- * @param	bitValue	: GPIO bit to set
- * @param	out			: Direction value, 0 = input, !0 = output
- * @return	None
- * Bits set to '0' are not altered.
- */
-STATIC INLINE void Chip_FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
-{
-	/* Same with Chip_GPIO_SetDir() */
-	Chip_GPIO_SetDir(portNum, bitValue, out);
-}
-
-/**
- * @brief	Set a GPIO port/bit to the high state
- * @param	portNum		: Port number
- * @param	bitValue	: Bit(s) in the port to set high
- * @return	None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_FIO_SetValue(uint8_t portNum, uint32_t bitValue)
-{
-	/* Same with GPIO_SetValue() */
-	LPC_GPIO_PORT->SET[portNum] = bitValue;
-}
-
-/**
- * @brief	Set a GPIO port/bit to the low state
- * @param	portNum		: Port number
- * @param	bitValue	: Bit(s) in the port to set low
- * @return	None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_FIO_ClearValue(uint8_t portNum, uint32_t bitValue)
-{
-	/* Same with GPIO_ClearValue() */
-	LPC_GPIO_PORT->CLR[portNum] = bitValue;
-}
-
-/**
- * @brief	Read current bit states for the selected port
- * @param	portNum	: Port number to read
- * @return	Current value of GPIO port
- * The current states of the bits for the port are read, regardless of
- * whether the GPIO port bits are input or output.
- */
-STATIC INLINE uint32_t Chip_FIO_ReadValue(uint8_t portNum)
-{
-	/* Same with GPIO_ReadValue() */
-	return LPC_GPIO_PORT->PIN[portNum];
-}
-
-/**
- * @brief	Set a GPIO port/bit to the high state
- * @param	portNum		: Port number
- * @param	bitValue	: Bit(s) in the port to set high
- * @return	None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_GPIO_SetValue(uint8_t portNum, uint32_t bitValue)
-{
-	LPC_GPIO_PORT->SET[portNum] = bitValue;
-}
-
-/**
- * @brief	Set a GPIO port/bit to the low state
- * @param	portNum		: Port number
- * @param	bitValue	: Bit(s) in the port to set low
- * @return	None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)
-{
-	LPC_GPIO_PORT->CLR[portNum] = bitValue;
-}
-
-/**
- * @brief	Read current bit states for the selected port
- * @param	portNum	: Port number to read
- * @return	Current value of GPIO port
- * The current states of the bits for the port are read, regardless of
- * whether the GPIO port bits are input or output.
- */
-STATIC INLINE uint32_t Chip_GPIO_ReadValue(uint8_t portNum)
-{
-	return LPC_GPIO_PORT->PIN[portNum];
-}
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIO_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c
deleted file mode 100644
index 3504ac3c67..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2C driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "i2c_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-#define MAX_TX_BUFFER_SIZE 10	/* Maximum transmit buffer size in Chip_I2C_MasterWriteReg() function */
-
-static uint32_t i2cClockrate[2];
-static I2C_M_SETUP_Type TransferMCfg;
-static uint8_t p_regAddr;
-static uint8_t tx_buffer[MAX_TX_BUFFER_SIZE];
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Determine clock for uart BASED ON SELECTED uart */
-static CCU_CLK_T Chip_I2C_DetermineClk(LPC_I2C_Type *I2Cx) {
-
-	CCU_CLK_T i2cclk;
-
-	/* Pick clock for uart BASED ON SELECTED uart */
-	if (I2Cx == LPC_I2C0) {
-		i2cclk = CLK_APB1_I2C0;
-	}
-	else {
-		i2cclk = CLK_APB3_I2C1;
-	}
-
-	return i2cclk;
-}
-
-/* Get UART bus number BASED ON SELECTED uart */
-static I2C_ID_Type Chip_I2C_Get_BusNum(LPC_I2C_Type *I2Cx)
-{
-	if (I2Cx == LPC_I2C1) {
-		return I2C1;
-	}
-
-	return I2C0;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the LPC_I2C peripheral with specified parameter */
-void Chip_I2C_Init(LPC_I2C_Type *I2Cx)
-{
-	/* Enable I2C Clocking */
-	//	Chip_Clock_EnableOpts(Chip_I2C_DetermineClk(I2Cx), false, false, 1);
-	Chip_Clock_Enable(Chip_I2C_DetermineClk(I2Cx));
-
-	IP_I2C_Init(I2Cx);
-}
-
-/* De-initializes the I2C peripheral registers to their default reset values */
-void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx)
-{
-	IP_I2C_DeInit(I2Cx);
-
-	/* Disable UART clocking */
-	Chip_Clock_Disable(Chip_I2C_DetermineClk(I2Cx));
-}
-
-/* Set up clock rate for LPC_I2C peripheral */
-void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate)
-{
-	if (I2Cx == LPC_I2C0) {
-		i2cClockrate[0] = clockrate;
-		/* Select weather standard, fast, fast plus mode*/
-		if (clockrate >= 1000000) {	/* Fast mode plus: 1MHz, high speed 3.4MHz */
-			Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS);
-		}
-		else {					/* standard 100KHz, fast 400KHz */
-			Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
-		}
-	}
-	else if (I2Cx == LPC_I2C1) {
-		i2cClockrate[1] = clockrate;
-		/* Check if I2C1 run fast mode*/
-		if (clockrate > 400000) {
-			return;
-		}
-	}
-	else {return; }
-
-	/* Set clock rate */
-	if (clockrate < 1000) {	/* make sure SCLH,SCLL not exceed its 16bit value */
-		return;
-	}
-
-	IP_I2C_SetClockRate(I2Cx, (Chip_Clock_GetRate(Chip_I2C_DetermineClk(I2Cx)) / clockrate));
-}
-
-/* Get current clock rate for LPC_I2C peripheral */
-uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx)
-{
-	if (I2Cx == LPC_I2C0) {
-		return i2cClockrate[0];
-	}
-	else if (I2Cx == LPC_I2C1) {
-		return i2cClockrate[1];
-	}
-	return 0;
-}
-
-/* Transmit and Receive data in master mode */
-Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	TransferCfg->retransmissions_max = 3;
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-	TransferCfg->retransmissions_count = 0;
-
-	return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Transmit an array of bytes in Master mode */
-Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	TransferCfg->rx_data = NULL;
-	TransferCfg->rx_length = 0;
-	TransferCfg->retransmissions_max = 3;
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-	TransferCfg->retransmissions_count = 0;
-
-	return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Receive an array of bytes in Master mode */
-Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	TransferCfg->tx_data = NULL;
-	TransferCfg->tx_length = 0;
-	TransferCfg->retransmissions_max = 3;
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-	TransferCfg->retransmissions_count = 0;
-
-	return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Transmit one byte and continue to send an array of bytes
- * after a repeated start condition is generated in Master mode
- */
-uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx,
-								 uint32_t SlaveAddr,
-								 uint8_t regAddr,
-								 uint8_t *buffer,
-								 uint8_t buffer_len)
-{
-	uint8_t i = 0;
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	tx_buffer[0] = regAddr;
-
-	for (i = 0; i < buffer_len; i++)
-		tx_buffer[i + 1] = *(buffer + i);
-
-	TransferMCfg.sl_addr7bit = SlaveAddr;
-	TransferMCfg.tx_data = tx_buffer;
-	TransferMCfg.tx_length = buffer_len + 1;
-	TransferMCfg.rx_data = NULL;
-	TransferMCfg.rx_length = 0;
-	TransferMCfg.retransmissions_max = 3;
-	TransferMCfg.tx_count = 0;
-	TransferMCfg.rx_count = 0;
-	TransferMCfg.retransmissions_count = 0;
-	IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING);
-
-	return TransferMCfg.tx_count;
-}
-
-/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
- * This function is useful for communicating with the I2C slave registers
- */
-uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx,
-								uint32_t SlaveAddr,
-								uint8_t regAddr,
-								uint8_t *buffer,
-								uint8_t buffer_len)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	p_regAddr = regAddr;
-
-	TransferMCfg.sl_addr7bit = SlaveAddr;
-	TransferMCfg.tx_data = &p_regAddr;
-	TransferMCfg.tx_length = 1;
-	TransferMCfg.rx_data = buffer;
-	TransferMCfg.rx_length = buffer_len;
-	TransferMCfg.retransmissions_max = 3;
-	TransferMCfg.tx_count = 0;
-	TransferMCfg.rx_count = 0;
-	TransferMCfg.retransmissions_count = 0;
-	IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING);
-
-	return TransferMCfg.rx_count;
-}
-
-/* General Master Interrupt handler for I2C peripheral */
-void Chip_I2C_Interrupt_MasterHandler(LPC_I2C_Type *I2Cx)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	IP_I2C_Interrupt_MasterHandler(I2Cx, I2C_Num);
-}
-
-/* Get status of Master Transfer */
-bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	return IP_I2C_Interrupt_MasterTransferComplete(I2C_Num);
-}
-
-/* Receive and Transmit data in slave mode */
-Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-
-	return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Transmit an array of bytes in Slave mode */
-Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_data = NULL;
-	TransferCfg->rx_length = 0;
-	TransferCfg->rx_count = 0;
-
-	return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Receive an array of bytes in Slave mode */
-Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	TransferCfg->tx_data = NULL;
-	TransferCfg->tx_length = 0;
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-
-	return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* General Slave Interrupt handler for I2C peripheral */
-void Chip_I2C_Interrupt_SlaveHandler(LPC_I2C_Type *I2Cx)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	IP_I2C_Interrupt_SlaveHandler(I2Cx, I2C_Num);
-}
-
-/* Get status of Slave Transfer */
-bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx)
-{
-	I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
-	return IP_I2C_Interrupt_SlaveTransferComplete(I2C_Num);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h
deleted file mode 100644
index 460bb7a083..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2C driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef I2C_18XX_43XX_H_
-#define I2C_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup I2C_18XX_43XX CHIP: LPC18xx/43xx I2C Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Initializes the LPC_I2C peripheral with specified parameter.
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	Nothing
- */
-void Chip_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	De-initializes the I2C peripheral registers to their default reset values
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	Nothing
- */
-void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Set up clock rate for LPC_I2C peripheral.
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	clockrate	: Target clock rate value to initialized I2C peripheral (Hz)
- * @return	Nothing
- */
-void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate);
-
-/**
- * @brief	Get current clock rate for LPC_I2C peripheral.
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	the current I2Cx clock rate
- */
-uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Transmit and Receive data in master mode
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
- *                      information about the configuration for master transfer.
- * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode
- * @return	SUCCESS or ERROR
- */
-Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Transmit an array of bytes in Master mode
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
- *                      information about the	configuration for master transfer
- * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode
- * @return  SUCCESS or ERROR
- */
-Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Receive an array of bytes in Master mode
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
- *                      information about the configuration for master transfer.
- * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return	SUCCESS or ERROR
- */
-Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Write byte(s) to slave register
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	SlaveAddr	: Slave address in 7-bit mode
- * @param	regAddr		: Slave register address
- * @param	buffer		: pointer to data array needed to send
- * @param	buffer_len	: data length (number of bytes)
- * @return	Number of bytes sent
- * Transmit one byte and an array of bytes after a repeated start condition is generated in Master mode.
- * This function is useful for communicating with the I2C slave registers.
- */
-uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx,
-								 uint32_t SlaveAddr,
-								 uint8_t regAddr,
-								 uint8_t *buffer,
-								 uint8_t buffer_len);
-
-/**
- * @brief	Read slave register content
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	SlaveAddr	: Slave address in 7-bit mode
- * @param	regAddr		: Slave register address
- * @param	buffer		: pointer to data array needed to receive
- * @param	buffer_len	: data length (number of bytes)
- * @return	Number of bytes received
- * Transmit one byte and continue to receive an array of bytes after a repeated start condition is
- * generated in Master mode. This function is useful for communicating with the I2C slave registers.
- */
-uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx,
-								uint32_t SlaveAddr,
-								uint8_t regAddr,
-								uint8_t *buffer,
-								uint8_t buffer_len);
-
-/**
- * @brief	General Master Interrupt handler for I2C peripheral
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	Nothing
- */
-void Chip_I2C_Interrupt_MasterHandler (LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Get status of Master Transfer
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	Master transfer status: TRUE (transfer completed) or FALSE (not completed yet)
- */
-bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Receive and Transmit data in slave mode
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified
- *                      information about the configuration for master transfer.
- * @param	Opt			: I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return	SUCCESS or ERROR
- */
-Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Transmit an array of bytes in Slave mode
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified
- *                      information about the configuration for slave transfer.
- * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return	SUCCESS or ERROR
- */
-Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Receive an array of bytes in Slave mode
- * @param	I2Cx		: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified
- *                      information about the configuration for slave transfer.
- * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return	SUCCESS or ERROR
- */
-Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	General Slave Interrupt handler for I2C peripheral
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	Nothing
- */
-void Chip_I2C_Interrupt_SlaveHandler (LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Get status of Slave Transfer
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return	Slave transfer status: TRUE (transfer completed) or FALSE (not completed yet)
- */
-bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief	Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	OwnSlaveAddrConfigStruct : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the
- *                      configuration information for the specified I2C slave address.
- * @return	Nothing
- */
-STATIC INLINE void Chip_I2C_SetOwnSlaveAddr(LPC_I2C_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)
-{
-	IP_I2C_SetOwnSlaveAddr(I2Cx, OwnSlaveAddrConfigStruct);
-}
-
-/**
- * @brief	Enable or disable I2C peripheral's operation
- * @param	I2Cx	: I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param	Mode	: I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE
- * @param	NewState: New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE
- * @return	Nothing
- */
-STATIC INLINE void Chip_I2C_Cmd(LPC_I2C_Type *I2Cx, I2C_Mode Mode, FunctionalState NewState)
-{
-	IP_I2C_Cmd(I2Cx, Mode, NewState);
-}
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* I2C_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c
deleted file mode 100644
index 4e0c8ba203..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2S driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "i2s_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Configure I2S for Audio Format input */
-Status Chip_I2S_Config(LPC_I2S_Type *I2Sx, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format)
-{
-	uint32_t pClk;
-	uint32_t x, y;
-	uint64_t divider;
-	uint16_t dif;
-	uint16_t x_divide = 0, y_divide = 0;
-	uint32_t N;
-	uint16_t err, ErrorOptimal = 0xFFFF;
-
-	pClk = (uint64_t)Chip_Clock_GetRate(CLK_APB1_I2S);
-
-	/* divider is a fixed point number with 16 fractional bits */
-	divider = (((uint64_t)(audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk;
-	/* find N that make x/y <= 1 -> divider <= 2^16 */
-	for (N = 64; N > 0; N--) {
-		if ((divider * N) < (1 << 16)) {
-			break;
-		}
-	}
-	if (N == 0) {
-		return ERROR;
-	}
-	divider *= N;
-	for (y = 255; y > 0; y--) {
-		x = y * divider;
-		if (x & (0xFF000000)) {
-			continue;
-		}
-		dif = x & 0xFFFF;
-		if (dif > 0x8000) {
-			err = 0x10000 - dif;
-		}
-		else {
-			err = dif;
-		}
-		if (err == 0) {
-			y_divide = y;
-			break;
-		}
-		else if (err < ErrorOptimal) {
-			ErrorOptimal = err;
-			y_divide = y;
-		}
-	}
-	x_divide = ((uint64_t)y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk;
-	if (x_divide >= 256) {
-		x_divide = 0xFF;
-	}
-	if (x_divide == 0) {
-		x_divide = 1;
-	}
-	if (audio_format->WordWidth <= 8) {
-		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_8);
-	}
-	else if (audio_format->WordWidth <= 16) {
-		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_16);
-	}
-	else {
-		IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_32);
-	}
-	IP_I2S_SetMono(I2Sx, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO);
-	IP_I2S_SetMasterSlaveMode(I2Sx, TRMode, I2S_MASTER_MODE);
-	IP_I2S_SetWS_Halfperiod(I2Sx, TRMode, audio_format->WordWidth - 1);
-	IP_I2S_ModeConfig(I2Sx, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA);
-	IP_I2S_SetBitRate(I2Sx, TRMode, N - 1);
-	IP_I2S_SetXYDivider(I2Sx, TRMode, x_divide, y_divide);
-	return SUCCESS;
-}
-
-/* Enable/Disable Interrupt with a specific FIFO depth */
-void Chip_I2S_Int_Cmd(LPC_I2S_Type *I2Sx, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth)
-{
-	IP_I2S_InterruptCmd(I2Sx, TRMode, NewState);
-	IP_I2S_SetFIFODepthIRQ(I2Sx, TRMode, FIFO_Depth);
-}
-
-/* Enable/Disable DMA with a specific FIFO depth */
-void    Chip_I2S_DMA_Cmd(LPC_I2S_Type *I2Sx,
-						uint8_t TRMode,
-						uint8_t DMANum,
-						FunctionalState NewState,
-						uint8_t FIFO_Depth)
-{
-	IP_I2S_SetFIFODepthDMA(I2Sx, TRMode, (IP_I2S_DMARequestNumber_Type) DMANum, FIFO_Depth);
-	IP_I2S_DMACmd(I2Sx, (IP_I2S_DMARequestNumber_Type) DMANum, TRMode, NewState);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h
deleted file mode 100644
index ab16639618..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2S driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2S_18XX_43XX_H_
-#define __I2S_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define I2S_DMA_REQUEST_NUMBER_1 IP_I2S_DMA_REQUEST_NUMBER_1
-#define I2S_DMA_REQUEST_NUMBER_2 IP_I2S_DMA_REQUEST_NUMBER_2
-
-/**
- * @brief I2S Audio Format Structure
- */
-typedef struct {
-	uint32_t SampleRate;	/*!< Sample Rate */
-	uint8_t ChannelNumber;	/*!< Channel Number - 1 is mono, 2 is stereo */
-	uint8_t WordWidth;		/*!< Word Width - 8, 16 or 32 bits */
-} Chip_I2S_Audio_Format_Type;
-
-/**
- * @brief	Initialize for I2S
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @return	Nothing
- */
-STATIC INLINE void Chip_I2S_Init(LPC_I2S_Type *pI2S)
-{
-	IP_I2S_Init(pI2S);
-}
-
-/**
- * @brief	Shutdown I2S
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @return	Nothing
- * Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
- */
-STATIC INLINE void Chip_I2S_DeInit(LPC_I2S_Type *pI2S)
-{
-	IP_I2S_DeInit(pI2S);
-}
-
-/**
- * @brief	Send a 32-bit data to TXFIFO for transmition
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	data	: Data to be transmited
- * @return	Nothing
- * The function writes to TXFIFO without checking any condition.
- */
-STATIC INLINE void Chip_I2S_Send(LPC_I2S_Type *pI2S, uint32_t data)
-{
-	IP_I2S_Send(pI2S, data);
-}
-
-/**
- * @brief	Get received data from RXFIFO
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @return	Data received in RXFIFO
- * The function reads from RXFIFO without checking any condition.
- */
-STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_Type *pI2S)
-{
-	return IP_I2S_Receive(pI2S);
-}
-
-/**
- * @brief	Start the I2S
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- */
-STATIC INLINE void Chip_I2S_Start(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
-	IP_I2S_Start(pI2S, TRMode);
-}
-
-/**
- * @brief	Disables accesses on FIFOs, places the transmit channel in mute mode
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- */
-STATIC INLINE void Chip_I2S_Pause(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
-	IP_I2S_Pause(pI2S, TRMode);
-}
-
-/**
- * @brief	Transmit channel sends only zeroes
- * @param	pI2S		: The base of I2S peripheral on the chip
- * @param	NewState	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- * The data output from I2S transmit channel is always zeroes
- */
-STATIC INLINE void Chip_I2S_Mute(LPC_I2S_Type *pI2S, FunctionalState NewState)
-{
-	IP_I2S_Mute(pI2S, NewState);
-}
-
-/**
- * @brief	Stop I2S asynchronously
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- * Pause, resets the transmit channel and FIFO asynchronously
- */
-STATIC INLINE void Chip_I2S_Stop(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
-	IP_I2S_Stop(pI2S, TRMode);
-}
-
-/**
- * @brief	Set the I2S operating modes
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	clksel	: Clock source selection for the receive bit clock divider
- * @param	fpin	: Receive 4-pin mode selection
- * @param	mcena	: Enable for the RX_MCLK output
- * @return	Nothing
- * In addition to master and slave modes, which are independently configurable for
- * the transmitter and the receiver, several different clock sources are possible,
- * including variations that share the clock and/or WS between the transmitter and
- * receiver. It also allows using I2S with fewer pins, typically four.
- */
-STATIC INLINE void Chip_I2S_ModeConfig(LPC_I2S_Type *pI2S,
-										 uint8_t TRMode,
-										 uint32_t clksel,
-										 uint32_t fpin,
-										 uint32_t mcena)
-{
-	IP_I2S_ModeConfig(pI2S, TRMode, clksel, fpin, mcena);
-}
-
-/**
- * @brief	Get the current level of the Transmit/Receive FIFO
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Current level of the Transmit/Receive FIFO
- */
-STATIC INLINE uint8_t Chip_I2S_GetLevel(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
-	return IP_I2S_GetLevel(pI2S, TRMode);
-}
-
-/**
- * @brief   Configure I2S for Audio Format input
- * @param	pI2S			: The base I2S peripheral on the chip
- * @param	TRMode			: Mode Rx/Tx
- * @param	audio_format	: Audio Format
- * @return	SUCCESS or ERROR
- */
-Status Chip_I2S_Config(LPC_I2S_Type *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format);
-
-/**
- * @brief   Enable/Disable Interrupt with a specific FIFO depth
- * @param	pI2S			: The base I2S peripheral on the chip
- * @param	TRMode			: Mode Rx/Tx
- * @param	NewState		: ENABLE or DISABLE interrupt
- * @param	FIFO_Depth		: FIFO level creating an irq request
- * @return	Nothing
- */
-void Chip_I2S_Int_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth);
-
-/**
- * @brief   Enable/Disable DMA with a specific FIFO depth
- * @param	pI2S			: The base I2S peripheral on the chip
- * @param	TRMode			: Mode Rx/Tx
- * @param	DMANum			: Should be
- *								- IP_I2S_DMA_REQUEST_NUMBER_1 : Using DMA1
- *								- IP_I2S_DMA_REQUEST_NUMBER_2 : Using DMA2
- * @param	NewState		: ENABLE or DISABLE interrupt
- * @param	FIFO_Depth		: FIFO level creating an irq request
- * @return	Nothing
- */
-void Chip_I2S_DMA_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, uint8_t DMANum, FunctionalState NewState, uint8_t FIFO_Depth);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2S_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c
deleted file mode 100644
index e3b4443fd6..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * @brief LPC18xx/43xx LCD chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "lcd_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-static LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64;
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Configure Cursor */
-void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync)
-{
-	LCD_Cursor_Size = cursor_size;
-	IP_LCD_Cursor_Config(LPC_LCD, cursor_size, sync);
-}
-
-/* Write Cursor Image into Internal Cursor Image Buffer */
-void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image)
-{
-	int i, j;
-	uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image;
-
-	/* Check if Cursor Size was configured as 32x32 or 64x64*/
-	if (LCD_Cursor_Size == LCD_CURSOR_32x32) {
-		i = cursor_num * 64;
-		j = i + 64;
-	}
-	else {
-		i = 0;
-		j = 256;
-	}
-	fifoptr = IP_LCD_Cursor_GetImageBufferAddress(LPC_LCD, 0);
-
-	/* Copy Cursor Image content to FIFO */
-	for (; i < j; i++) {
-
-		*fifoptr = *crsr_ptr;
-		crsr_ptr++;
-		fifoptr++;
-	}
-}
-
-/* Load LCD Palette */
-void Chip_LCD_LoadPalette(void *palette) {
-	LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry;
-	uint8_t i, *pal_ptr;
-	/* This function supports loading of the color palette from
-	   the C file generated by the bmp2c utility. It expects the
-	   palette to be passed as an array of 32-bit BGR entries having
-	   the following format:
-	   2:0 - Not used
-	   7:3 - Blue
-	   10:8 - Not used
-	   15:11 - Green
-	   18:16 - Not used
-	   23:19 - Red
-	   31:24 - Not used
-	   arg = pointer to input palette table address */
-	ptr_pal_entry = &pal_entry;
-	pal_ptr = (uint8_t *) palette;
-
-	/* 256 entry in the palette table */
-	for (i = 0; i < 256 / 2; i++) {
-		pal_entry.Bl = (*pal_ptr++) >> 3;	/* blue first */
-		pal_entry.Gl = (*pal_ptr++) >> 3;	/* get green */
-		pal_entry.Rl = (*pal_ptr++) >> 3;	/* get red */
-		pal_ptr++;	/* skip over the unused byte */
-		/* do the most significant halfword of the palette */
-		pal_entry.Bu = (*pal_ptr++) >> 3;	/* blue first */
-		pal_entry.Gu = (*pal_ptr++) >> 3;	/* get green */
-		pal_entry.Ru = (*pal_ptr++) >> 3;	/* get red */
-		pal_ptr++;	/* skip over the unused byte */
-
-		IP_LCD_Color_LoadPalette(LPC_LCD, (uint32_t *) &ptr_pal_entry, i);
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h
deleted file mode 100644
index e7a08a4190..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * @brief LPC18xx/43xx LCD chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LCD_18XX_43XX_H_
-#define __LCD_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Initialize the LCD controller
- * @param	LCD_ConfigStruct	: Pointer to LCD configuration
- * @return  LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
- */
-STATIC INLINE void Chip_LCD_Init(LCD_Config_Type *LCD_ConfigStruct)
-{
-	IP_LCD_Init(LPC_LCD, LCD_ConfigStruct);
-}
-
-/**
- * @brief	Power the LCD Panel (power pin)
- * @param	OnOff	: true to power on, false to power off
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Power(FunctionalState OnOff)
-{
-	IP_LCD_Power(LPC_LCD, OnOff);
-}
-
-/**
- * @brief	Enable/Disable the LCD Controller
- * @param	EnDis	: true to enable, false to disable
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Enable(FunctionalState EnDis)
-{
-	IP_LCD_Enable(LPC_LCD, EnDis);
-}
-
-/**
- * @brief	Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
- *			Buffer for Dual Panel
- * @param	buffer	: address of buffer
- * @return	None
- */
-STATIC INLINE void Chip_LCD_SetUPFrameBuffer(void *buffer)
-{
-	IP_LCD_SetUPFrameBuffer(LPC_LCD, buffer);
-}
-
-/**
- * @brief	Set LCD Lower Panel Frame Buffer for Dual Panel
- * @param	buffer	: address of buffer
- * @return	None
- */
-STATIC INLINE void Chip_LCD_SetLPFrameBuffer(void *buffer)
-{
-	IP_LCD_SetLPFrameBuffer(LPC_LCD, buffer);
-}
-
-/**
- * @brief	Configure Cursor
- * @param	cursor_size	: specify size of cursor
- *                  - LCD_CURSOR_32x32	:cursor size is 32x32 pixels
- *                  - LCD_CURSOR_64x64	:cursor size is 64x64 pixels
- * @param	sync		: cursor sync mode
- *                  - TRUE	:cursor sync to the frame sync pulse
- *                  - FALSE	:cursor async mode
- * @return	None
- */
-void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync);
-
-/**
- * @brief	Enable Cursor
- * @param	cursor_num	: specify number of cursor is going to be written
- *							this param must < 4
- * @param	OnOff		: true to turn on LCD, false to turn off
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Cursor_Enable(uint8_t cursor_num, FunctionalState OnOff)
-{
-	IP_LCD_Cursor_Enable(LPC_LCD, cursor_num, OnOff);
-}
-
-/**
- * @brief	Load Cursor Palette
- * @param	palette_color	: cursor palette 0 value
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(uint32_t palette_color)
-{
-	IP_LCD_Cursor_LoadPalette0(LPC_LCD, palette_color);
-}
-
-/**
- * @brief	Load Cursor Palette
- * @param	palette_color	: cursor palette 1 value
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(uint32_t palette_color)
-{
-	IP_LCD_Cursor_LoadPalette1(LPC_LCD, palette_color);
-}
-
-/**
- * @brief	Set Cursor Position
- * @param	x	: horizontal position
- * @param	y	: vertical position
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Cursor_SetPos(uint16_t x, uint16_t y)
-{
-	IP_LCD_Cursor_SetPos(LPC_LCD, x, y);
-}
-
-/**
- * @brief	Set Cursor Clipping Position
- * @param	x	: horizontal position, should be in range: 0..63
- * @param	y	: vertical position, should be in range: 0..63
- * @return	None
- */
-STATIC INLINE void Chip_LCD_Cursor_SetClip(uint16_t x, uint16_t y)
-{
-	IP_LCD_Cursor_SetClip(LPC_LCD, x, y);
-}
-
-/**
- * @brief	Enable Controller Interrupt
- * @param	ints	: OR'ed interrupt bits to enable
- * @return	None
- */
-STATIC INLINE void Chip_LCD_EnableInts(uint32_t ints)
-{
-	IP_LCD_EnableInts(LPC_LCD, ints);
-}
-
-/**
- * @brief	Disable Controller Interrupt
- * @param	ints	: OR'ed interrupt bits to disable
- * @return	None
- */
-STATIC INLINE void Chip_LCD_DisableInts(uint32_t ints)
-{
-	IP_LCD_DisableInts(LPC_LCD, ints);
-}
-
-/**
- * @brief	Clear Controller Interrupt
- * @param	ints	: OR'ed interrupt bits to clear
- * @return	None
- */
-STATIC INLINE void Chip_LCD_ClearInts(uint32_t ints)
-{
-	IP_LCD_ClearInts(LPC_LCD, ints);
-}
-
-/**
- * @brief	Write Cursor Image into Internal Cursor Image Buffer
- * @param	cursor_num	: Cursor index
- * @param	Image		: Pointer to image data
- * @return	None
- */
-void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image);
-
-/**
- * @brief	Load LCD Palette
- * @param	palette	: Address of palette table to load
- * @return	None
- */
-void Chip_LCD_LoadPalette(void *palette);
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* __LCD_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c
deleted file mode 100644
index e3977d6332..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * @brief LPC18xx/43xx Reset Generator Unit driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "rgu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Trigger a peripheral reset for the selected peripheral */
-void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber)
-{
-	volatile uint32_t *p;
-
-	/* To trigger reset- write RESET_CTRLx with a 1 bit */
-	p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
-
-	/* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
-	p += ResetNumber / 32;
-
-	/* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
-	   after 1 clock cycle, so set the bit and return */
-	*p = (1 << (ResetNumber % 32));
-}
-
-/* Clears reset for the selected peripheral */
-void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber)
-{
-	volatile uint32_t *p;
-
-	/* To trigger reset- write RESET_CTRLx with a 1 bit */
-	p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
-
-	/* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
-	p += ResetNumber / 32;
-
-	/* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
-	   after 1 clock cycle, so set the bit and return */
-	*p = 0;
-}
-
-/* Checks the reset status of a peripheral */
-bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber)
-{
-	volatile uint32_t *read;
-
-	read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0);
-	read += ResetNumber / 32;
-
-	/* Reset not asserted if bit is set */
-	return (bool) ((*read & (1 << (ResetNumber % 32))) == 0);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h
deleted file mode 100644
index 50a49efefa..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * @brief LPC18xx/43xx Reset Generator Unit driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RGU_18XX_43XX_H_
-#define __RGU_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief RGU reset enumerations
- */
-typedef enum {
-	RGU_CORE_RST,
-	RGU_PERIPH_RST,
-	RGU_MASTER_RST,
-	RGU_WWDT_RST = 4,
-	RGU_CREG_RST,
-	RGU_BUS_RST = 8,
-	RGU_SCU_RST,
-	RGU_M3_RST = 13,
-	RGU_LCD_RST = 16,
-	RGU_USB0_RST,
-	RGU_USB1_RST,
-	RGU_DMA_RST,
-	RGU_SDIO_RST,
-	RGU_EMC_RST,
-	RGU_ETHERNET_RST,
-	RGU_FLASHA_RST = 25,
-	RGU_EEPROM_RST = 27,
-	RGU_GPIO_RST,
-	RGU_FLASHB_RST,
-	RGU_TIMER0_RST = 32,
-	RGU_TIMER1_RST,
-	RGU_TIMER2_RST,
-	RGU_TIMER3_RST,
-	RGU_RITIMER_RST,
-	RGU_SCT_RST,
-	RGU_MOTOCONPWM_RST,
-	RGU_QEI_RST,
-	RGU_ADC0_RST,
-	RGU_ADC1_RST,
-	RGU_DAC_RST,
-	RGU_UART0_RST = 44,
-	RGU_UART1_RST,
-	RGU_UART2_RST,
-	RGU_UART3_RST,
-	RGU_I2C0_RST,
-	RGU_I2C1_RST,
-	RGU_SSP0_RST,
-	RGU_SSP1_RST,
-	RGU_I2S_RST,
-	RGU_SPIFI_RST,
-	RGU_CAN1_RST,
-	RGU_CAN0_RST,
-#ifdef CHIP_LPC43XX
-	RGU_M0APP_RST,
-	RGU_SGPIO_RST,
-	RGU_SPI_RST,
-#endif
-	RGU_LAST_RST = 63,
-} RGU_RST_TYPE;
-
-/**
- * @brief RGU register structure
- */
-typedef struct {							/*!< RGU Structure          */
-	__I  uint32_t  RESERVED0[64];
-	__O  uint32_t  RESET_CTRL0;				/*!< Reset control register 0 */
-	__O  uint32_t  RESET_CTRL1;				/*!< Reset control register 1 */
-	__I  uint32_t  RESERVED1[2];
-	__IO uint32_t  RESET_STATUS0;			/*!< Reset status register 0 */
-	__IO uint32_t  RESET_STATUS1;			/*!< Reset status register 1 */
-	__IO uint32_t  RESET_STATUS2;			/*!< Reset status register 2 */
-	__IO uint32_t  RESET_STATUS3;			/*!< Reset status register 3 */
-	__I  uint32_t  RESERVED2[12];
-	__I  uint32_t  RESET_ACTIVE_STATUS0;	/*!< Reset active status register 0 */
-	__I  uint32_t  RESET_ACTIVE_STATUS1;	/*!< Reset active status register 1 */
-	__I  uint32_t  RESERVED3[170];
-	__IO uint32_t  RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */
-} LPC_RGU_T;
-
-/**
- * @brief	Trigger a peripheral reset for the selected peripheral
- * @param	ResetNumber	: Peripheral reset number to trigger
- * @return	Nothing
- */
-void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber);
-
-/**
- * @brief	Checks the reset status of a peripheral
- * @param	ResetNumber	: Peripheral reset number to trigger
- * @return	true if the periperal is still being reset
- */
-bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber);
-
-/**
- * @brief	Clears reset for the selected peripheral
- * @param	ResetNumber	: Peripheral reset number to trigger
- * @return	Nothing
- * Almost all peripherals will auto clear the reset bit. Only a few peripherals
- * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require
- * this function to clear the reset bit.
- */
-void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RGU_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c
deleted file mode 100644
index a00796610f..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * @brief LPC18xx/43xx RITimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "ritimer_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Set timer interval value */
-void Chip_RIT_SetTimerInterval(uint32_t time_interval)
-{
-	uint32_t clock_rate, cmp_value;
-
-	/* Get clock rate for RITimer */
-	clock_rate = Chip_Clock_GetRate(CLK_MX_RITIMER);
-
-	/* Determine aapproximate compare value based on clock rate and passed interval */
-	cmp_value = (clock_rate / 1000) * time_interval;
-
-	/* Set timer compare value */
-	Chip_RIT_SetCOMPVAL(cmp_value);
-	
-	/* Set timer enable clear bit to clear timer to 0 whenever
-	   counter value equals the contents of RICOMPVAL */
-	Chip_RIT_EnableCTRL(RIT_CTRL_ENCLR);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h
deleted file mode 100644
index 2ad32a57fe..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * @brief LPC18xx/43xx RITimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RITIMER_18XX_43XX_H_
-#define __RITIMER_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Initialize the RIT
- * @return	None
- */
-STATIC INLINE void Chip_RIT_Init(void)
-{
-	IP_RIT_Init(LPC_RITIMER);
-}
-
-/**
- * @brief	DeInitialize the RIT
- * @return	None
- */
-STATIC INLINE void Chip_RIT_DeInit(void)
-{
-	IP_RIT_DeInit(LPC_RITIMER);
-}
-
-/**
- * @brief	Enable/Disable Timer
- * @param	NewState	: ENABLE to enable timer, DISABLE to stop timer
- * @return	None
- */
-STATIC INLINE void Chip_RIT_Cmd(FunctionalState NewState)
-{
-	IP_RIT_Enable(LPC_RITIMER, NewState);
-}
-
-/**
- * @brief	Enable or disable timer debug
- * @param	NewState	: ENABLE to halt timer whenever a hardware break condition occurs
- * @return	None
- */
-STATIC INLINE void Chip_RIT_TimerDebugCmd(FunctionalState NewState)
-{
-	IP_RIT_TimerDebugCmd(LPC_RITIMER, NewState);
-}
-
-/**
- * @brief	Check whether interrupt flag is set or not
- * @return	Current interrupt status, either ET or UNSET
- */
-STATIC INLINE IntStatus Chip_RIT_GetIntStatus(void)
-{
-	return IP_RIT_GetIntStatus(LPC_RITIMER);
-}
-
-/**
- * @brief	Set a tick value for the interrupt to time out
- * @param	val	: value (in ticks) of the interrupt to be set
- * @return	None
- */
-STATIC INLINE void Chip_RIT_SetCOMPVAL(uint32_t val)
-{
-	IP_RIT_SetCOMPVAL(LPC_RITIMER, val);
-}
-
-/**
- * @brief	Enables or clears the RIT or interrupt
- * @param	val	: RIT to be set, one or more RIT_CTRL_* values
- * @return	None
- */
-STATIC INLINE void Chip_RIT_EnableCTRL(uint32_t val)
-{
-	IP_RIT_EnableCTRL(LPC_RITIMER, val);
-}
-
-/**
- * @brief	Clears the RIT interrupt
- * @return	None
- */
-STATIC INLINE void Chip_RIT_ClearInt(void)
-{
-	IP_RIT_EnableCTRL(LPC_RITIMER, RIT_CTRL_INT);
-}
-
-/**
- * @brief	Returns the current RIT Counter value
- * @return	the current timer counter value
- */
-STATIC INLINE uint32_t Chip_RIT_GetCounter(void)
-{
-	return IP_RIT_GetCounter(LPC_RITIMER);
-}
-
-/**
- * @brief	Set timer interval value
- * @param	time_interval	: timer interval value (ms)
- * @return	None
- */
-void Chip_RIT_SetTimerInterval(uint32_t time_interval);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RITIMER_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c
deleted file mode 100644
index 9db49832ee..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * @brief LPC18xx/43xx RTC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "rtc_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the RTC peripheral */
-void Chip_RTC_Init(void)
-{
-	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));	/* Reset 32Khz oscillator */
-	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);	/* Enable 32 kHz & 1 kHz on osc32k and release reset */
-	LPC_SCU->SFSCLK[0] = 1 | (0x3 << 2);/* function 1; CGU clk out, pull down */
-	IP_RTC_Init(LPC_RTC);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h
deleted file mode 100644
index 1220c4c0d5..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * @brief LPC18xx/43xx RTC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RTC_18XX_43XX_H_
-#define __RTC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx RTC driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Initialize the RTC peripheral
- * @return	None
- */
-void Chip_RTC_Init(void);
-
-/**
- * @brief	De-initialize the RTC peripheral
- * @return	None
- */
-STATIC INLINE void Chip_RTC_DeInit(void)
-{
-	IP_RTC_DeInit(LPC_RTC);
-}
-
-/**
- * @brief	Reset clock tick counter in the RTC peripheral
- * @return	None
- */
-STATIC INLINE void Chip_RTC_ResetClockTickCounter(void)
-{
-	IP_RTC_ResetClockTickCounter(LPC_RTC);
-}
-
-/**
- * @brief	Start/Stop RTC peripheral
- * @param	NewState	: New State of this function, should be:
- *							- ENABLE	:The time counters are enabled
- *							- DISABLE	:The time counters are disabled
- * @return	None
- */
-STATIC INLINE void Chip_RTC_Enable(FunctionalState NewState)
-{
-	IP_RTC_Enable(LPC_RTC, NewState);
-}
-
-/**
- * @brief	Enable/Disable Counter increment interrupt for a time type
- *			in the RTC peripheral
- * @param	cntrMask	: Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
- * @param	NewState	: ENABLE or DISABLE
- * @return	None
- */
-STATIC INLINE void Chip_RTC_CntIncrIntConfig(uint32_t cntrMask, FunctionalState NewState)
-{
-	IP_RTC_CntIncrIntConfig(LPC_RTC, cntrMask, NewState);
-}
-
-/**
- * @brief	Enable/Disable Alarm interrupt for a time type
- *			in the RTC peripheral
- * @param	alarmMask	: Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
- * @param	NewState	: ENABLE or DISABLE
- * @return	None
- */
-STATIC INLINE void Chip_RTC_AlarmIntConfig(uint32_t alarmMask, FunctionalState NewState)
-{
-	IP_RTC_AlarmIntConfig(LPC_RTC, alarmMask, NewState);
-}
-
-/**
- * @brief		Set current time value for a time type in the RTC peripheral
- * @param		Timetype	: time field index type to set
- * @param		TimeValue	: Value to palce in time field
- * @return		None
- */
-STATIC INLINE void Chip_RTC_SetTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
-{
-	IP_RTC_SetTime(LPC_RTC, Timetype, TimeValue);
-}
-
-/**
- * @brief	Get current time value for a type time type
- * @param	Timetype	: Time field index type to get
- * @return	Value of time field according to specified time type
- */
-STATIC INLINE uint32_t Chip_RTC_GetTime(IP_RTC_TIMEINDEX_T Timetype)
-{
-	return IP_RTC_GetTime(LPC_RTC, Timetype);
-}
-
-/**
- * @brief	Set full time in the RTC peripheral
- * @param	pFullTime	: Pointer to full time data
- * @return	None
- */
-STATIC INLINE void Chip_RTC_SetFullTime(IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_SetFullTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief	Get full time from the RTC peripheral
- * @param	pFullTime	: Pointer to full time record to fill
- * @return	None
- */
-STATIC INLINE void Chip_RTC_GetFullTime(IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_GetFullTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief	Set alarm time value for a time type
- * @param	Timetype	: Time index field to set
- * @param	ALValue		: Alarm time value to set
- * @return	None
- */
-STATIC INLINE void Chip_RTC_SetAlarmTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
-{
-	IP_RTC_SetAlarmTime(LPC_RTC, Timetype, ALValue);
-}
-
-/**
- * @brief	Get alarm time value for a time type
- * @param	Timetype	: Time index field to get
- * @return	Value of Alarm time according to specified time type
- */
-STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(IP_RTC_TIMEINDEX_T Timetype)
-{
-	return IP_RTC_GetAlarmTime(LPC_RTC, Timetype);
-}
-
-/**
- * @brief	Set full alarm time in the RTC peripheral
- * @param	pFullTime	: Pointer to full time record to set alarm
- * @return	None
- */
-STATIC INLINE void Chip_RTC_SetFullAlarmTime(IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_SetFullAlarmTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief	Get full alarm time in the RTC peripheral
- * @param	pFullTime	: Pointer to full time record to fill
- * @return	None
- */
-STATIC INLINE void Chip_RTC_GetFullAlarmTime(IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_GetFullAlarmTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief	Write value to General purpose registers
- * @param	index	: General purpose register index
- * @param	Value	: Value to write
- * @return	None
- * Note: These General purpose registers can be used to store important
-
- * information when the main power supply is off. The value in these
-
- * registers is not affected by chip reset. These registers are
-
- * powered in the RTC power domain.
- */
-STATIC INLINE void Chip_REGFILE_Write(uint8_t index, uint32_t Value)
-{
-	IP_REGFILE_Write(LPC_REGFILE, index, Value);
-}
-
-/**
- * @brief	Read value from General purpose registers
- * @param	index	: General purpose register index
- * @return	Read Value
- * These General purpose registers can be used to store important
-
- * information when the main power supply is off. The value in these
-
- * registers is not affected by chip reset. These registers are
-
- * powered in the RTC power domain.
- */
-STATIC INLINE uint32_t Chip_REGFILE_Read(uint8_t index)
-{
-	return IP_REGFILE_Read(LPC_REGFILE, index);
-}
-
-/**
- * @brief	Enable/Disable calibration counter in the RTC peripheral
- * @param	NewState	: New State of this function, should be:
- *							- ENABLE	:The calibration counter is enabled and counting
- *							- DISABLE	:The calibration counter is disabled and reset to zero
- * @return	None
- */
-STATIC INLINE void Chip_RTC_CalibCounterCmd(FunctionalState NewState)
-{
-	IP_RTC_CalibCounterCmd(LPC_RTC, NewState);
-}
-
-/**
- * @brief	Configures Calibration in the RTC peripheral
- * @param	CalibValue	: Calibration value, should be in range from 0 to 131,072
- * @param	CalibDir	: Calibration Direction, should be:
- *							- RTC_CALIB_DIR_FORWARD		:Forward calibration
- *							- RTC_CALIB_DIR_BACKWARD	:Backward calibration
- * @return	None
- */
-STATIC INLINE void Chip_RTC_CalibConfig(uint32_t CalibValue, uint8_t CalibDir)
-{
-	IP_RTC_CalibConfig(LPC_RTC, CalibValue, CalibDir);
-}
-
-/**
- * @brief	Clear specified Location interrupt pending in the RTC peripheral
- * @param	IntType	: Interrupt location type, should be:
- *						- RTC_INT_COUNTER_INCREASE	:Clear Counter Increment Interrupt pending.
- *						- RTC_INT_ALARM				:Clear alarm interrupt pending
- * @return	None
- */
-STATIC INLINE void Chip_RTC_ClearIntPending(uint32_t IntType)
-{
-	IP_RTC_ClearIntPending(LPC_RTC, IntType);
-}
-
-/**
- * @brief	Check whether if specified location interrupt in the
- *              RTC peripheral is set or not
- * @param	IntType	: Interrupt location type, should be:
- *						- RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
- *						- RTC_INT_ALARM: Alarm generated an interrupt.
- * @return	New state of specified Location interrupt in RTC peripheral, SET OR RESET
- */
-STATIC INLINE IntStatus Chip_RTC_GetIntPending(uint32_t IntType)
-{
-	return IP_RTC_GetIntPending(LPC_RTC, IntType);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RTC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c
deleted file mode 100644
index 091f5bd5f3..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * @brief LPC18xx/43xx System Control Unit (SCU) control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "scu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Configure pin function */
-void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
-{
-	if (port == PINMUX_CLK) {
-		LPC_SCU_CLK(((uint32_t) LPC_SCU), pin) = mode + func;
-	}
-	else {
-		LPC_SCU->SFSP[port][pin] = mode + func;
-	}
-}
-
-/* GPIO Interrupt Pin Select */
-void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum)
-{
-	uint8_t  pinInt;
-	volatile uint32_t pinSel;
-
-	pinInt = ((PortNum & 0x7) << 5) | (PinNum & 0x1F);
-	if (PortSel < 4) {
-		pinSel = LPC_SCU->PINTSEL0;
-		pinSel &= ~(0xFF << (PortSel * 8));
-		pinSel |= (pinInt << (PortSel * 8));
-		LPC_SCU->PINTSEL0 = pinSel;
-	}
-	else {
-		pinSel = LPC_SCU->PINTSEL1;
-		pinSel &= ~(0xFF << ((PortSel - 4) * 8));
-		pinSel |= (pinInt << ((PortSel - 4) * 8));
-		LPC_SCU->PINTSEL1 = pinSel;
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h
deleted file mode 100644
index c11f0cc478..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SCU_18XX_43XX_H_
-#define __SCU_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions)
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief System Control Unit register block
- */
-typedef struct {
-	__IO uint32_t  SFSP[16][32];
-	__I  uint32_t  RESERVED0[256];
-	__IO uint32_t  SFSCLK[4];			/*!< Pin configuration register for pins CLK0-3 */
-	__I  uint32_t  RESERVED16[28];
-	__IO uint32_t  SFSUSB;				/*!< Pin configuration register for USB */
-	__IO uint32_t  SFSI2C0;				/*!< Pin configuration register for I2C0-bus pins */
-	__IO uint32_t  ENAIO[3];			/*!< Analog function select registerS */
-	__I  uint32_t  RESERVED17[27];
-	__IO uint32_t  EMCDELAYCLK;			/*!< EMC clock delay register */
-	__I  uint32_t  RESERVED18[63];
-	__IO uint32_t  PINTSEL0;			/*!< Pin interrupt select register for pin interrupts 0 to 3. */
-	__IO uint32_t  PINTSEL1;			/*!< Pin interrupt select register for pin interrupts 4 to 7. */
-} LPC_SCU_Type;
-
-/** Port offset definition */
-#define PORT_OFFSET     0x80
-
-/** Pin offset definition */
-#define PIN_OFFSET      0x04
-
-/** Disable pull-down and pull-up resistor at resistor at pad */
-#define MD_PUP  (0x0 << 3)
-
-/** Enable pull-down resistor at pad */
-#define MD_BUK  (0x1 << 3)
-
-/** Enable pull-up resistor at pad */
-#define MD_PLN  (0x2 << 3)
-
-/** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define MD_PDN  (0x3 << 3)
-
-/** Enable fast slew rate */
-#define MD_EHS  (0x1 << 5)
-
-/** Input buffer enable */
-#define MD_EZI  (0x1 << 6)
-
-/** Disable input glitch filter */
-#define MD_ZI   (0x1 << 7)
-
-/** EHD driver strength low bit */
-#define MD_EHD0 (0x1 << 8)
-
-/** EHD driver strength high bit */
-#define MD_EHD1 (0x1 << 8)
-
-#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
-
-/** Pin configuration for STANDARD/FAST mode I2C */
-#define I2C0_STANDARD_FAST_MODE  (1 << 3 | 1 << 11)
-
-/** Pin configuration for Fast-mode Plus I2C */
-#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
-
-#define FUNC0           0x0				/** Pin function 0 */
-#define FUNC1           0x1				/** Pin function 1 */
-#define FUNC2           0x2				/** Pin function 2 */
-#define FUNC3           0x3				/** Pin function 3 */
-#define FUNC4           0x4				/** Pin function 4 */
-#define FUNC5           0x5				/** Pin function 5 */
-#define FUNC6           0x6				/** Pin function 6 */
-#define FUNC7           0x7				/** Pin function 7 */
-
-/** Returns the SFSP register address in the SCU for a pin and port */
-#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
-
-/** Returns the address in the SCU for a SFSCLK clock register */
-#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
-
-#define PINMUX_CLK 0xFF
-
-/**
- * @brief	Configure pin function
- * @param	port	: Port number, should be: 0..15
- * @param	pin		: Pin number, should be: 0..31
- * @param	mode	: Pin mode, should be:
- *                  - MD_PUP	:Pull-up enabled
- *                  - MD_BUK	:Plain input
- *                  - MD_PLN	:Repeater mode
- *                  - MD_PDN	:Pull-down enabled
- * @param	func	: Function mode, should be: FUNC0 to FUNC7
- * @return	None
- */
-void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
-
-/**
- * @brief	GPIO Interrupt Pin Select
- * @param	PortSel	: GPIO PINTSEL interrupt, should be: 0 to 7
- * @param	PortNum	: GPIO port number interrupt, should be: 0 to 7
- * @param	PinNum	: GPIO pin number Interrupt , should be: 0 to 31
- * @return	None
- */
-void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
-
-/**
- * @brief	I2C Pin Configuration
- * @param	I2C0Mode	: I2C0 mode, should be:
- *                  - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit
- *                  - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit
- * @return	None
- */
-STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
-{
-	LPC_SCU->SFSI2C0 = I2C0Mode;
-}
-
-/**
- * @brief	ADC Pin Configuration
- * @param	ADC_ID	: ADC number
- * @param	channel	: ADC channel
- * @return	None
- */
-STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
-{
-	LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SCU_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c
deleted file mode 100644
index da7001311f..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- * @brief LPC18xx/43xx SD/SDIO driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "sdmmc_18xx_43xx.h"
-#include "string.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Global instance of the current card */
-static mci_card_struct *g_card_info;
-
-/* Helper definition: all SD error conditions in the status word */
-#define SD_INT_ERROR (MCI_INT_RESP_ERR | MCI_INT_RCRC | MCI_INT_DCRC | \
-					  MCI_INT_RTO | MCI_INT_DTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE | \
-					  MCI_INT_SBE | MCI_INT_EBE)
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Function to execute a command */
-static int32_t sdmmc_execute_command(uint32_t cmd, uint32_t arg, uint32_t wait_status)
-{
-	int32_t step = (cmd & CMD_BIT_APP) ? 2 : 1;
-	int32_t status = 0;
-	uint32_t cmd_reg = 0;
-
-	if (!wait_status) {
-		wait_status = (cmd & CMD_MASK_RESP) ? MCI_INT_CMD_DONE : MCI_INT_DATA_OVER;
-	}
-
-	/* Clear the interrupts & FIFOs*/
-	if (cmd & CMD_BIT_DATA) {
-		IP_SDMMC_SetClearIntFifo(LPC_SDMMC);
-	}
-
-	/* also check error conditions */
-	wait_status |= MCI_INT_EBE | MCI_INT_SBE | MCI_INT_HLE | MCI_INT_RTO | MCI_INT_RCRC | MCI_INT_RESP_ERR;
-	if (wait_status & MCI_INT_DATA_OVER) {
-		wait_status |= MCI_INT_FRUN | MCI_INT_HTO | MCI_INT_DTO | MCI_INT_DCRC;
-	}
-
-	while (step) {
-		IP_SDMMC_SetClock(LPC_SDMMC, g_card_info->clk_rate, g_card_info->speed);
-
-		/* Clear the interrupts */
-		IP_SDMMC_SetRawIntStatus(LPC_SDMMC, 0xFFFFFFFF);
-
-		g_card_info->evsetup_cb(wait_status);
-
-		switch (step) {
-		case 1:	/* Execute command */
-			cmd_reg = ((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) |
-					  ((cmd & CMD_BIT_INIT)  ? MCI_CMD_INIT : 0) |
-					  ((cmd & CMD_BIT_DATA)  ? (MCI_CMD_DAT_EXP | MCI_CMD_PRV_DAT_WAIT) : 0) |
-					  (((cmd & CMD_MASK_RESP) == CMD_RESP_R2) ? MCI_CMD_RESP_LONG : 0) |
-					  ((cmd & CMD_MASK_RESP) ? MCI_CMD_RESP_EXP : 0) |
-					  ((cmd & CMD_BIT_WRITE)  ? MCI_CMD_DAT_WR : 0) |
-					  ((cmd & CMD_BIT_STREAM) ? MCI_CMD_STRM_MODE : 0) |
-					  ((cmd & CMD_BIT_BUSY) ? MCI_CMD_STOP : 0) |
-					  ((cmd & CMD_BIT_AUTO_STOP)  ? MCI_CMD_SEND_STOP : 0) |
-					  MCI_CMD_START;
-
-			/* wait for previos data finsh for select/deselect commands */
-			if (((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) == MMC_SELECT_CARD) {
-				cmd_reg |= MCI_CMD_PRV_DAT_WAIT;
-			}
-
-			/* wait for command to be accepted by CIU */
-			if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, arg) == 0) {
-				--step;
-			}
-			break;
-
-		case 0:
-			return 0;
-
-		case 2:	/* APP prefix */
-			cmd_reg = MMC_APP_CMD | MCI_CMD_RESP_EXP |
-					  ((cmd & CMD_BIT_INIT)  ? MCI_CMD_INIT : 0) |
-					  MCI_CMD_START;
-
-			if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, g_card_info->rca << 16) == 0) {
-				--step;
-			}
-			break;
-		}
-
-		/* wait for command response */
-		status = g_card_info->waitfunc_cb();
-
-		/* We return an error if there is a timeout, even if we've fetched  a response */
-		if (status & SD_INT_ERROR) {
-			return status;
-		}
-
-		if (status & MCI_INT_CMD_DONE) {
-			switch (cmd & CMD_MASK_RESP) {
-			case 0:
-				break;
-
-			case CMD_RESP_R1:
-			case CMD_RESP_R3:
-			case CMD_RESP_R2:
-				IP_SDMMC_GetResponse(LPC_SDMMC, &g_card_info->response[0]);
-				break;
-			}
-		}
-	}
-
-	return 0;
-}
-
-/* Checks whether card is acquired properly or not */
-static int32_t prv_card_acquired(void)
-{
-	return g_card_info->cid[0] != 0;
-}
-
-/* Helper function to get a bit field withing multi-word  buffer. Used to get
-   fields with-in CSD & EXT-CSD */
-static uint32_t prv_get_bits(int32_t start, int32_t end, uint32_t *data)
-{
-	uint32_t v;
-	uint32_t i = end >> 5;
-	uint32_t j = start & 0x1f;
-
-	if (i == (start >> 5)) {
-		v = (data[i] >> j);
-	}
-	else {
-		v = ((data[i] << (32 - j)) | (data[start >> 5] >> j));
-	}
-
-	return v & ((1 << (end - start + 1)) - 1);
-}
-
-/* Function to process the CSD & EXT-CSD of the card */
-static void prv_process_csd(void)
-{
-	int32_t status = 0;
-	int32_t c_size = 0;
-	int32_t c_size_mult = 0;
-	int32_t mult = 0;
-
-	/* compute block length based on CSD response */
-	g_card_info->block_len = 1 << prv_get_bits(80, 83, g_card_info->csd);
-
-	if ((g_card_info->card_type & CARD_TYPE_HC) && (g_card_info->card_type & CARD_TYPE_SD)) {
-		/* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec  an explanation for the calculation of these values */
-		c_size = prv_get_bits(48, 63, (uint32_t *) g_card_info->csd) + 1;
-		g_card_info->blocknr = c_size << 10;/* 512 byte blocks */
-	}
-	else {
-		/* See section 5.3 of the 4.1 revision of the MMC specs for  an explanation for the calculation of these values */
-		c_size = prv_get_bits(62, 73, (uint32_t *) g_card_info->csd);
-		c_size_mult = prv_get_bits(47, 49, (uint32_t *) g_card_info->csd);
-		mult = 1 << (c_size_mult + 2);
-		g_card_info->blocknr = (c_size + 1) * mult;
-
-		/* adjust blocknr to 512/block */
-		if (g_card_info->block_len > MMC_SECTOR_SIZE) {
-			g_card_info->blocknr = g_card_info->blocknr * (g_card_info->block_len >> 9);
-		}
-
-		/* get extended CSD for newer MMC cards CSD spec >= 4.0*/
-		if (((g_card_info->card_type & CARD_TYPE_SD) == 0) &&
-			(prv_get_bits(122, 125, (uint32_t *) g_card_info->csd) >= 4)) {
-			/* put card in trans state */
-			status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0);
-
-			/* set block size and byte count */
-			IP_SDMMC_SetBlockSize(LPC_SDMMC, MMC_SECTOR_SIZE);
-
-			/* send EXT_CSD command */
-			IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) g_card_info->ext_csd, MMC_SECTOR_SIZE);
-
-			status = sdmmc_execute_command(CMD_SEND_EXT_CSD, 0, 0 | MCI_INT_DATA_OVER);
-			if ((status & SD_INT_ERROR) == 0) {
-				/* check EXT_CSD_VER is greater than 1.1 */
-				if ((g_card_info->ext_csd[48] & 0xFF) > 1) {
-					g_card_info->blocknr = g_card_info->ext_csd[53];/* bytes 212:215 represent sec count */
-
-				}
-				/* switch to 52MHz clock if card type is set to 1 or else set to 26MHz */
-				if ((g_card_info->ext_csd[49] & 0xFF) == 1) {
-					/* for type 1 MMC cards high speed is 52MHz */
-					g_card_info->speed = MMC_HIGH_BUS_MAX_CLOCK;
-				}
-				else {
-					/* for type 0 MMC cards high speed is 26MHz */
-					g_card_info->speed = MMC_LOW_BUS_MAX_CLOCK;
-				}
-			}
-		}
-	}
-
-	g_card_info->device_size = g_card_info->blocknr << 9;	/* blocknr * 512 */
-}
-
-/* Puts current selected card in trans state */
-static int32_t prv_set_trans_state(void)
-{
-	uint32_t status;
-
-	/* get current state of the card */
-	status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0);
-	if (status & MCI_INT_RTO) {
-		/* unable to get the card state. So return immediatly. */
-		return -1;
-	}
-
-	/* check card state in response */
-	status = R1_CURRENT_STATE(g_card_info->response[0]);
-	switch (status) {
-	case SDMMC_STBY_ST:
-		/* put card in 'Trans' state */
-		status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0);
-		if (status != 0) {
-			/* unable to put the card in Trans state. So return immediatly. */
-			return -1;
-		}
-		break;
-
-	case SDMMC_TRAN_ST:
-		/*do nothing */
-		break;
-
-	default:
-		/* card shouldn't be in other states so return */
-		return -1;
-	}
-
-	return 0;
-}
-
-/* Sets card data width and block size */
-static int32_t prv_set_card_params(void)
-{
-	int32_t status;
-
-#if SDIO_BUS_WIDTH > 1
-	if (g_card_info->card_type & CARD_TYPE_SD) {
-		status = sdmmc_execute_command(CMD_SD_SET_WIDTH, 2, 0);
-		if (status != 0) {
-			return -1;
-		}
-
-		/* if positive response */
-		IP_SDMMC_SetCardType(LPC_SDMMC, MCI_CTYPE_4BIT);
-		LPC_SDMMC->CTYPE = MCI_CTYPE_4BIT;
-	}
-#elif SDIO_BUS_WIDTH > 4
-#error 8-bit mode not supported yet!
-#endif
-
-	/* set block length */
-	IP_SDMMC_SetBlkSize(LPC_SDMMC, MMC_SECTOR_SIZE);
-	status = sdmmc_execute_command(CMD_SET_BLOCKLEN, MMC_SECTOR_SIZE, 0);
-	if (status != 0) {
-		return -1;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Returns the current SD status, clears pending ints, and disables all ints */
-uint32_t Chip_SDMMC_GetIntStatus(void)
-{
-	uint32_t status;
-
-	/* Get status and clear interrupts */
-	status = IP_SDMMC_GetRawIntStatus(LPC_SDMMC);
-	IP_SDMMC_SetRawIntStatus(LPC_SDMMC, status);
-	IP_SDMMC_SetIntMask(LPC_SDMMC, 0);
-
-	return status;
-}
-
-/* Get card's current state (idle, transfer, program, etc.) */
-int32_t Chip_SDMMC_GetState(void)
-{
-	uint32_t status;
-
-	/* get current state of the card */
-	status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0);
-	if (status & MCI_INT_RTO) {
-		return -1;
-	}
-
-	/* check card state in response */
-	return (int32_t) R1_CURRENT_STATE(g_card_info->response[0]);
-}
-
-/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */
-uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo)
-{
-	int32_t status;
-	int32_t tries = 0;
-	uint32_t ocr = OCR_VOLTAGE_RANGE_MSK;
-	uint32_t r;
-	int32_t state = 0;
-	uint32_t command = 0;
-
-	g_card_info = pcardinfo;
-
-	/* clear card type */
-	IP_SDMMC_SetCardType(LPC_SDMMC, 0);
-
-	/* set high speed for the card as 20MHz */
-	g_card_info->speed = MMC_MAX_CLOCK;
-
-	status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE);
-
-	while (state < 100) {
-		switch (state) {
-		case 0:	/* Setup for SD */
-			/* check if it is SDHC card */
-			status = sdmmc_execute_command(CMD_SD_SEND_IF_COND, SD_SEND_IF_ARG, 0);
-			if (!(status & MCI_INT_RTO)) {
-				/* check response has same echo pattern */
-				if ((g_card_info->response[0] & SD_SEND_IF_ECHO_MSK) == SD_SEND_IF_RESP) {
-					ocr |= OCR_HC_CCS;
-				}
-			}
-
-			++state;
-			command = CMD_SD_OP_COND;
-			tries = INIT_OP_RETRIES;
-
-			/* assume SD card */
-			g_card_info->card_type |= CARD_TYPE_SD;
-			g_card_info->speed = SD_MAX_CLOCK;
-			break;
-
-		case 10:	/* Setup for MMC */
-			/* start fresh for MMC crds */
-			g_card_info->card_type &= ~CARD_TYPE_SD;
-			status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE);
-			command = CMD_MMC_OP_COND;
-			tries = INIT_OP_RETRIES;
-			ocr |= OCR_HC_CCS;
-			++state;
-
-			/* for MMC cards high speed is 20MHz */
-			g_card_info->speed = MMC_MAX_CLOCK;
-			break;
-
-		case 1:
-		case 11:
-			status = sdmmc_execute_command(command, 0, 0);
-			if (status & MCI_INT_RTO) {
-				state += 9;	/* Mode unavailable */
-			}
-			else {
-				++state;
-			}
-			break;
-
-		case 2:		/* Initial OCR check  */
-		case 12:
-			ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS);
-			if (ocr & OCR_ALL_READY) {
-				++state;
-			}
-			else {
-				state += 2;
-			}
-			break;
-
-		case 3:		/* Initial wait for OCR clear */
-		case 13:
-			while ((ocr & OCR_ALL_READY) && --tries > 0) {
-				g_card_info->msdelay_func(MS_ACQUIRE_DELAY);
-				status = sdmmc_execute_command(command, 0, 0);
-				ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS);
-			}
-			if (ocr & OCR_ALL_READY) {
-				state += 7;
-			}
-			else {
-				++state;
-			}
-			break;
-
-		case 14:
-			/* for MMC cards set high capacity bit */
-			ocr |= OCR_HC_CCS;
-
-		case 4:	/* Assign OCR */
-			tries = SET_OP_RETRIES;
-			ocr &= OCR_VOLTAGE_RANGE_MSK | OCR_HC_CCS;	/* Mask for the bits we care about */
-			do {
-				g_card_info->msdelay_func(MS_ACQUIRE_DELAY);
-				status = sdmmc_execute_command(command, ocr, 0);
-				r = g_card_info->response[0];
-			} while (!(r & OCR_ALL_READY) && --tries > 0);
-
-			if (r & OCR_ALL_READY) {
-				/* is it high capacity card */
-				g_card_info->card_type |= (r & OCR_HC_CCS);
-				++state;
-			}
-			else {
-				state += 6;
-			}
-			break;
-
-		case 5:	/* CID polling */
-		case 15:
-			status = sdmmc_execute_command(CMD_ALL_SEND_CID, 0, 0);
-			memcpy(&g_card_info->cid, &g_card_info->response[0], 16);
-			++state;
-			break;
-
-		case 6:	/* RCA send, for SD get RCA */
-			status = sdmmc_execute_command(CMD_SD_SEND_RCA, 0, 0);
-			g_card_info->rca = (g_card_info->response[0]) >> 16;
-			++state;
-			break;
-
-		case 16:	/* RCA assignment for MMC set to 1 */
-			g_card_info->rca = 1;
-			status = sdmmc_execute_command(CMD_MMC_SET_RCA, g_card_info->rca << 16, 0);
-			++state;
-			break;
-
-		case 7:
-		case 17:
-			status = sdmmc_execute_command(CMD_SEND_CSD, g_card_info->rca << 16, 0);
-			memcpy(&g_card_info->csd, &g_card_info->response[0], 16);
-			state = 100;
-			break;
-
-		default:
-			state += 100;	/* break from while loop */
-			break;
-		}
-	}
-
-	/* Compute card size, block size and no. of blocks  based on CSD response recived. */
-	if (prv_card_acquired()) {
-		prv_process_csd();
-
-		/* Setup card data width and block size (once) */
-		if (prv_set_trans_state() != 0) {
-			return 0;
-		}
-		if (prv_set_card_params() != 0) {
-			return 0;
-		}
-	}
-
-	return prv_card_acquired();
-}
-
-/* Get the device size of SD/MMC card (after enumeration) */
-int32_t Chip_SDMMC_GetDeviceSize(void)
-{
-	return g_card_info->device_size;
-}
-
-/* Performs the read of data from the SD/MMC card */
-int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks)
-{
-	int32_t cbRead = (num_blocks) * MMC_SECTOR_SIZE;
-	int32_t status = 0;
-	int32_t index;
-
-	/* if card is not acquired return immediately */
-	if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) {
-		return 0;
-	}
-
-	/* put card in trans state */
-	if (prv_set_trans_state() != 0) {
-		return 0;
-	}
-
-	/* set number of bytes to read */
-	LPC_SDMMC->BYTCNT = cbRead;
-
-	/* if high capacity card use block indexing */
-	if (g_card_info->card_type & CARD_TYPE_HC) {
-		index = start_block;
-	}
-	else {	/*fix at 512 bytes*/
-		index = start_block << 9;	// \* g_card_info->block_len;
-
-	}
-	IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbRead);
-
-	/* Select single or multiple read based on number of blocks */
-	if (num_blocks == 1) {
-		status = sdmmc_execute_command(CMD_READ_SINGLE, index, 0 | MCI_INT_DATA_OVER);
-	}
-	else {
-		status = sdmmc_execute_command(CMD_READ_MULTIPLE, index, 0 | MCI_INT_DATA_OVER);
-	}
-
-	if (status != 0) {
-		cbRead = 0;
-	}
-	/*Wait for card program to finish*/
-	while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
-
-	return cbRead;
-}
-
-/* Performs write of data to the SD/MMC card */
-int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks)
-{
-	int32_t cbWrote = num_blocks *  MMC_SECTOR_SIZE;
-	int32_t status;
-	int32_t index;
-
-	/* if card is not acquired return immediately */
-	if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) {
-		return 0;
-	}
-
-	/*Wait for card program to finish*/
-	while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
-
-	/* put card in trans state */
-	if (prv_set_trans_state() != 0) {
-		return 0;
-	}
-
-	/* set number of bytes to write */
-	LPC_SDMMC->BYTCNT = cbWrote;
-
-	/* if high capacity card use block indexing */
-	if (g_card_info->card_type & CARD_TYPE_HC) {
-		index = start_block;
-	}
-	else {	/*fix at 512 bytes*/
-		index = start_block << 9;	// * g_card_info->block_len;
-
-	}
-	IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbWrote);
-
-	/* Select single or multiple write based on number of blocks */
-	if (num_blocks == 1) {
-		status = sdmmc_execute_command(CMD_WRITE_SINGLE, index, 0 | MCI_INT_DATA_OVER);
-	}
-	else {
-		status = sdmmc_execute_command(CMD_WRITE_MULTIPLE, index, 0 | MCI_INT_DATA_OVER);
-	}
-
-	/*Wait for card program to finish*/
-	while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
-
-	if (status != 0) {
-		cbWrote = 0;
-	}
-
-	return cbWrote;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h
deleted file mode 100644
index 70b4a02dc4..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
- * @brief LPC18xx/43xx SD/SDIO driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDMMC_18XX_43XX_H_
-#define __SDMMC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/* SD/MMC commands - this matrix shows the command, response types, and
-   supported card type for that command.
-   Command                 Number Resp  SD  MMC
-   ----------------------- ------ ----- --- ---
-   Reset (go idle)         CMD0   NA    x   x
-   Send op condition       CMD1   R3        x
-   All send CID            CMD2   R2    x   x
-   Send relative address   CMD3   R1        x
-   Send relative address   CMD3   R6    x
-   Program DSR             CMD4   NA        x
-   Select/deselect card    CMD7   R1b       x
-   Select/deselect card    CMD7   R1    x
-   Send CSD                CMD9   R2    x   x
-   Send CID                CMD10  R2    x   x
-   Read data until stop    CMD11  R1    x   x
-   Stop transmission       CMD12  R1/b  x   x
-   Send status             CMD13  R1    x   x
-   Go inactive state       CMD15  NA    x   x
-   Set block length        CMD16  R1    x   x
-   Read single block       CMD17  R1    x   x
-   Read multiple blocks    CMD18  R1    x   x
-   Write data until stop   CMD20  R1        x
-   Setblock count          CMD23  R1        x
-   Write single block      CMD24  R1    x   x
-   Write multiple blocks   CMD25  R1    x   x
-   Program CID             CMD26  R1        x
-   Program CSD             CMD27  R1    x   x
-   Set write protection    CMD28  R1b   x   x
-   Clear write protection  CMD29  R1b   x   x
-   Send write protection   CMD30  R1    x   x
-   Erase block start       CMD32  R1    x
-   Erase block end         CMD33  R1    x
-   Erase block start       CMD35  R1        x
-   Erase block end         CMD36  R1        x
-   Erase blocks            CMD38  R1b       x
-   Fast IO                 CMD39  R4        x
-   Go IRQ state            CMD40  R5        x
-   Lock/unlock             CMD42  R1b       x
-   Application command     CMD55  R1        x
-   General command         CMD56  R1b       x
-
- *** SD card application commands - these must be preceded with ***
- *** MMC CMD55 application specific command first               ***
-   Set bus width           ACMD6  R1    x
-   Send SD status          ACMD13 R1    x
-   Send number WR blocks   ACMD22 R1    x
-   Set WR block erase cnt  ACMD23 R1    x
-   Send op condition       ACMD41 R3    x
-   Set clear card detect   ACMD42 R1    x
-   Send CSR                ACMD51 R1    x */
-
-/** @brief  SD/MMC command enumeration value.
- */
-typedef enum {
-	SDMMC_IDLE,				/*!<  Put card in idle mode */
-	MMC_SENDOP_COND,		/*!<  Send operating condition */
-	SDMMC_ALL_SEND_CID,		/*!<  All cards send CID */
-	SDMMC_SRA,				/*!<  Set relative address */
-	MMC_PROGRAM_DSR,		/*!<  Program DSR */
-	SDMMC_SELECT_CARD,		/*!< Select card */
-	SDMMC_SEND_CSD,			/*!< Send CSD data */
-	SDMMC_SEND_CID,			/*!< Send CID register data (with rel. addr) */
-	SDMMC_READ_UNTIL_STOP,	/*!< Read data until stop */
-	SDMMC_STOP_XFER,		/*!< Stop current transmission */
-	SDMMC_SSTAT,			/*!< Send status */
-	SDMMC_INACTIVE,			/*!< Put card in inactive state */
-	SDMMC_SET_BLEN,			/*!< Set block transfer length */
-	SDMMC_READ_SINGLE,		/*!< Read single block */
-	SDMMC_READ_MULTIPLE,	/*!< Read multiple blocks */
-	SDMMC_WRITE_UNTIL_STOP,	/*!< Write data until stop */
-	SDMMC_SET_BLOCK_COUNT,	/*!< Set block count */
-	SDMMC_WRITE_SINGLE,		/*!< Write single block */
-	SDMMC_WRITE_MULTIPLE,	/*!< Write multiple blocks */
-	MMC_PROGRAM_CID,		/*!< Program CID */
-	SDMMC_PROGRAM_CSD,		/*!< Program CSD */
-	SDMMC_SET_WR_PROT,		/*!< Set write protection */
-	SDMMC_CLEAR_WR_PROT,	/*!< Clear write protection */
-	SDMMC_SEND_WR_PROT,		/*!< Send write protection */
-	SD_ERASE_BLOCK_START,	/*!< Set starting erase block */
-	SD_ERASE_BLOCK_END,		/*!< Set ending erase block */
-	MMC_ERASE_BLOCK_START,	/*!< Set starting erase block */
-	MMC_ERASE_BLOCK_END,	/*!< Set ending erase block */
-	MMC_ERASE_BLOCKS,		/*!< Erase blocks */
-	MMC_FAST_IO,			/*!< Fast IO */
-	MMC_GO_IRQ_STATE,		/*!< Go into IRQ state */
-	MMC_LOCK_UNLOCK,		/*!< Lock/unlock */
-	SDMMC_APP_CMD,			/*!< Application specific command */
-	SDMMC_GEN_CMD,			/*!< General purpose command */
-	SDMMC_INVALID_CMD		/*!< Invalid SDMMC command */
-} SDMMC_COMMAND_T;
-
-/** @brief  SDMMC application specific commands for SD cards only - these
-   must be preceded by the SDMMC CMD55 to work correctly.
- */
-typedef enum {
-	SD_SET_BUS_WIDTH,		/*!< Set the SD bus width */
-	SD_SEND_STATUS,			/*!< Send the SD card status */
-	SD_SEND_WR_BLOCKS,		/*!< Send the number of written clocks */
-	SD_SET_ERASE_COUNT,		/*!< Set the number of blocks to pre-erase */
-	SD_SENDOP_COND,			/*!< Send the OCR register (init) */
-	SD_CLEAR_CARD_DET,		/*!< Set or clear the 50K detect pullup */
-	SD_SEND_SCR,			/*!< Send the SD configuration register */
-	SD_INVALID_APP_CMD		/*!< Invalid SD application command */
-} SD_APP_CMD_T;
-
-/** @brief  Possible SDMMC response types
- */
-typedef enum {
-	SDMMC_RESPONSE_R1,		/*!< Typical status */
-	SDMMC_RESPONSE_R1B,		/*!< Typical status with busy */
-	SDMMC_RESPONSE_R2,		/*!< CID/CSD registers (CMD2 and CMD10) */
-	SDMMC_RESPONSE_R3,		/*!< OCR register (CMD1, ACMD41) */
-	SDMMC_RESPONSE_R4,		/*!< Fast IO response word */
-	SDMMC_RESPONSE_R5,		/*!< Go IRQ state response word */
-	SDMMC_RESPONSE_R6,		/*!< Published RCA response */
-	SDMMC_RESPONSE_NONE		/*!< No response expected */
-} SDMMC_RESPONSE_T;
-
-/** @brief  Possible SDMMC card state types
- */
-typedef enum {
-	SDMMC_IDLE_ST = 0,	/*!< Idle state */
-	SDMMC_READY_ST,		/*!< Ready state */
-	SDMMC_IDENT_ST,		/*!< Identification State */
-	SDMMC_STBY_ST,		/*!< standby state */
-	SDMMC_TRAN_ST,		/*!< transfer state */
-	SDMMC_DATA_ST,		/*!< Sending-data State */
-	SDMMC_RCV_ST,		/*!< Receive-data State */
-	SDMMC_PRG_ST,		/*!< Programming State */
-	SDMMC_DIS_ST		/*!< Disconnect State */
-} SDMMC_STATE_T;
-
-/* Standard MMC commands (3.1)           type  argument     response */
-/* class 1 */
-#define MMC_GO_IDLE_STATE         0		/* bc                          */
-#define MMC_SEND_OP_COND          1		/* bcr  [31:0]  OCR        R3  */
-#define MMC_ALL_SEND_CID          2		/* bcr                     R2  */
-#define MMC_SET_RELATIVE_ADDR     3		/* ac   [31:16] RCA        R1  */
-#define MMC_SET_DSR               4		/* bc   [31:16] RCA            */
-#define MMC_SELECT_CARD           7		/* ac   [31:16] RCA        R1  */
-#define MMC_SEND_EXT_CSD          8		/* bc                      R1  */
-#define MMC_SEND_CSD              9		/* ac   [31:16] RCA        R2  */
-#define MMC_SEND_CID             10		/* ac   [31:16] RCA        R2  */
-#define MMC_STOP_TRANSMISSION    12		/* ac                      R1b */
-#define MMC_SEND_STATUS          13		/* ac   [31:16] RCA        R1  */
-#define MMC_GO_INACTIVE_STATE    15		/* ac   [31:16] RCA            */
-
-/* class 2 */
-#define MMC_SET_BLOCKLEN         16		/* ac   [31:0]  block len  R1  */
-#define MMC_READ_SINGLE_BLOCK    17		/* adtc [31:0]  data addr  R1  */
-#define MMC_READ_MULTIPLE_BLOCK  18		/* adtc [31:0]  data addr  R1  */
-
-/* class 3 */
-#define MMC_WRITE_DAT_UNTIL_STOP 20		/* adtc [31:0]  data addr  R1  */
-
-/* class 4 */
-#define MMC_SET_BLOCK_COUNT      23		/* adtc [31:0]  data addr  R1  */
-#define MMC_WRITE_BLOCK          24		/* adtc [31:0]  data addr  R1  */
-#define MMC_WRITE_MULTIPLE_BLOCK 25		/* adtc                    R1  */
-#define MMC_PROGRAM_CID          26		/* adtc                    R1  */
-#define MMC_PROGRAM_CSD          27		/* adtc                    R1  */
-
-/* class 6 */
-#define MMC_SET_WRITE_PROT       28		/* ac   [31:0]  data addr  R1b */
-#define MMC_CLR_WRITE_PROT       29		/* ac   [31:0]  data addr  R1b */
-#define MMC_SEND_WRITE_PROT      30		/* adtc [31:0]  wpdata addr R1  */
-
-/* class 5 */
-#define MMC_ERASE_GROUP_START    35		/* ac   [31:0]  data addr  R1  */
-#define MMC_ERASE_GROUP_END      36		/* ac   [31:0]  data addr  R1  */
-#define MMC_ERASE                37		/* ac                      R1b */
-
-/* class 9 */
-#define MMC_FAST_IO              39		/* ac   <Complex>          R4  */
-#define MMC_GO_IRQ_STATE         40		/* bcr                     R5  */
-
-/* class 7 */
-#define MMC_LOCK_UNLOCK          42		/* adtc                    R1b */
-
-/* class 8 */
-#define MMC_APP_CMD              55		/* ac   [31:16] RCA        R1  */
-#define MMC_GEN_CMD              56		/* adtc [0]     RD/WR      R1b */
-
-/* SD commands                           type  argument     response */
-/* class 8 */
-/* This is basically the same command as for MMC with some quirks. */
-#define SD_SEND_RELATIVE_ADDR     3		/* ac                      R6  */
-#define SD_CMD8                   8		/* bcr  [31:0]  OCR        R3  */
-
-/* Application commands */
-#define SD_APP_SET_BUS_WIDTH      6		/* ac   [1:0]   bus width  R1   */
-#define SD_APP_OP_COND           41		/* bcr  [31:0]  OCR        R1 (R4)  */
-#define SD_APP_SEND_SCR          51		/* adtc                    R1   */
-
-/*
-   MMC status in R1
-   Type
-    e : error bit
-    s : status bit
-    r : detected and set for the actual command response
-    x : detected and set during command execution. the host must poll
-        the card by sending status command in order to read these bits.
-   Clear condition
-    a : according to the card state
-    b : always related to the previous command. Reception of
-        a valid command will clear it (with a delay of one command)
-    c : clear by read
- */
-
-#define R1_OUT_OF_RANGE         (1UL << 31)		/* er, c */
-#define R1_ADDRESS_ERROR        (1 << 30)	/* erx, c */
-#define R1_BLOCK_LEN_ERROR      (1 << 29)	/* er, c */
-#define R1_ERASE_SEQ_ERROR      (1 << 28)	/* er, c */
-#define R1_ERASE_PARAM          (1 << 27)	/* ex, c */
-#define R1_WP_VIOLATION         (1 << 26)	/* erx, c */
-#define R1_CARD_IS_LOCKED       (1 << 25)	/* sx, a */
-#define R1_LOCK_UNLOCK_FAILED   (1 << 24)	/* erx, c */
-#define R1_COM_CRC_ERROR        (1 << 23)	/* er, b */
-#define R1_ILLEGAL_COMMAND      (1 << 22)	/* er, b */
-#define R1_CARD_ECC_FAILED      (1 << 21)	/* ex, c */
-#define R1_CC_ERROR             (1 << 20)	/* erx, c */
-#define R1_ERROR                (1 << 19)	/* erx, c */
-#define R1_UNDERRUN             (1 << 18)	/* ex, c */
-#define R1_OVERRUN              (1 << 17)	/* ex, c */
-#define R1_CID_CSD_OVERWRITE    (1 << 16)	/* erx, c, CID/CSD overwrite */
-#define R1_WP_ERASE_SKIP        (1 << 15)	/* sx, c */
-#define R1_CARD_ECC_DISABLED    (1 << 14)	/* sx, a */
-#define R1_ERASE_RESET          (1 << 13)	/* sr, c */
-#define R1_STATUS(x)            (x & 0xFFFFE000)
-#define R1_CURRENT_STATE(x)     ((x & 0x00001E00) >> 9)	/* sx, b (4 bits) */
-#define R1_READY_FOR_DATA       (1 << 8)/* sx, a */
-#define R1_APP_CMD              (1 << 5)/* sr, c */
-
-#define OCR_ALL_READY           (1UL << 31)		/* Card Power up status bit */
-#define OCR_HC_CCS              (1 << 30)	/* High capacity card */
-#define OCR_VOLTAGE_RANGE_MSK   0x00ff8000
-
-#define SD_SEND_IF_ARG          0x000001AA
-#define SD_SEND_IF_ECHO_MSK     0x000000FF
-#define SD_SEND_IF_RESP         0x000000AA
-
-#define CMD_MASK_RESP       (0x3UL << 28)
-#define CMD_RESP(r)         (((r) & 0x3) << 28)
-#define CMD_RESP_R0         (0 << 28)
-#define CMD_RESP_R1         (1 << 28)
-#define CMD_RESP_R2         (2 << 28)
-#define CMD_RESP_R3         (3 << 28)
-#define CMD_BIT_AUTO_STOP   (1 << 24)
-#define CMD_BIT_APP         (1 << 23)
-#define CMD_BIT_INIT        (1 << 22)
-#define CMD_BIT_BUSY        (1 << 21)
-#define CMD_BIT_LS          (1 << 20)	/* Low speed, used during acquire */
-#define CMD_BIT_DATA        (1 << 19)
-#define CMD_BIT_WRITE       (1 << 18)
-#define CMD_BIT_STREAM      (1 << 17)
-#define CMD_MASK_CMD        (0xff)
-#define CMD_SHIFT_CMD       (0)
-
-#define CMD(c, r)        ( ((c) &  CMD_MASK_CMD) | CMD_RESP((r)) )
-
-#define CMD_IDLE            CMD(MMC_GO_IDLE_STATE, 0) | CMD_BIT_LS    | CMD_BIT_INIT
-#define CMD_SD_OP_COND      CMD(SD_APP_OP_COND, 1)      | CMD_BIT_LS | CMD_BIT_APP
-#define CMD_SD_SEND_IF_COND CMD(SD_CMD8, 1)      | CMD_BIT_LS
-#define CMD_MMC_OP_COND     CMD(MMC_SEND_OP_COND, 3)    | CMD_BIT_LS | CMD_BIT_INIT
-#define CMD_ALL_SEND_CID    CMD(MMC_ALL_SEND_CID, 2)    | CMD_BIT_LS
-#define CMD_MMC_SET_RCA     CMD(MMC_SET_RELATIVE_ADDR, 1) | CMD_BIT_LS
-#define CMD_SD_SEND_RCA     CMD(SD_SEND_RELATIVE_ADDR, 1) | CMD_BIT_LS
-#define CMD_SEND_CSD        CMD(MMC_SEND_CSD, 2) | CMD_BIT_LS
-#define CMD_SEND_EXT_CSD    CMD(MMC_SEND_EXT_CSD, 1) | CMD_BIT_LS | CMD_BIT_DATA
-#define CMD_DESELECT_CARD   CMD(MMC_SELECT_CARD, 0)
-#define CMD_SELECT_CARD     CMD(MMC_SELECT_CARD, 1)
-#define CMD_SET_BLOCKLEN    CMD(MMC_SET_BLOCKLEN, 1)
-#define CMD_SEND_STATUS     CMD(MMC_SEND_STATUS, 1)
-#define CMD_READ_SINGLE     CMD(MMC_READ_SINGLE_BLOCK, 1) | CMD_BIT_DATA
-#define CMD_READ_MULTIPLE   CMD(MMC_READ_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP
-#define CMD_SD_SET_WIDTH    CMD(SD_APP_SET_BUS_WIDTH, 1) | CMD_BIT_APP
-#define CMD_STOP            CMD(MMC_STOP_TRANSMISSION, 1) | CMD_BIT_BUSY
-#define CMD_WRITE_SINGLE    CMD(MMC_WRITE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE
-#define CMD_WRITE_MULTIPLE  CMD(MMC_WRITE_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP
-
-/** @brief card type defines
- */
-#define CARD_TYPE_SD    (1 << 0)
-#define CARD_TYPE_4BIT  (1 << 1)
-#define CARD_TYPE_8BIT  (1 << 2)
-#define CARD_TYPE_HC    (OCR_HC_CCS)/*!< high capacity card > 2GB */
-
-#define MMC_SECTOR_SIZE 512
-
-/** @brief Setup options for the SDIO driver
- */
-#define US_TIMEOUT            1000000		/*!< give 1 atleast 1 sec for the card to respond */
-#define MS_ACQUIRE_DELAY      (10)			/*!< inter-command acquire oper condition delay in msec*/
-#define INIT_OP_RETRIES       50			/*!< initial OP_COND retries */
-#define SET_OP_RETRIES        1000			/*!< set OP_COND retries */
-#define SDIO_BUS_WIDTH        4				/*!< Max bus width supported */
-#define SD_MMC_ENUM_CLOCK       400000		/*!< Typical enumeration clock rate */
-#define MMC_MAX_CLOCK           20000000	/*!< Max MMC clock rate */
-#define MMC_LOW_BUS_MAX_CLOCK   26000000	/*!< Type 0 MMC card max clock rate */
-#define MMC_HIGH_BUS_MAX_CLOCK  52000000	/*!< Type 1 MMC card max clock rate */
-#define SD_MAX_CLOCK            25000000	/*!< Max SD clock rate */
-
-/* Function prototype for event setup function */
-typedef void (*MCI_EVSETUP_FUNC_T)(uint32_t);
-
-/* Function prototype for wait (for IRQ) function */
-typedef uint32_t (*MCI_WAIT_CB_FUNC_T)(void);
-
-/* Function prototype for milliSecond delay function */
-typedef void (*MCI_MSDELAY_FUNC_T)(uint32_t);
-
-/* Card specific setup data */
-typedef struct _mci_card_struct {
-	uint32_t response[4];						/*!< Most recent response */
-	uint32_t cid[4];							/*!< CID of acquired card  */
-	uint32_t csd[4];							/*!< CSD of acquired card */
-	uint32_t ext_csd[512 / 4];
-	uint32_t card_type;
-	uint32_t rca;								/*!< Relative address assigned to card */
-	uint32_t speed;
-	uint32_t block_len;							/*!< Card sector size*/
-	uint32_t device_size;
-	uint32_t blocknr;
-	uint32_t clk_rate;
-	sdif_device sdif_dev;
-	MCI_EVSETUP_FUNC_T evsetup_cb;
-	MCI_WAIT_CB_FUNC_T waitfunc_cb;
-	MCI_MSDELAY_FUNC_T msdelay_func;
-} mci_card_struct;
-
-/**
- * @brief	Detect if an SD card is inserted
- * @return	Returns 0 if a card is detected, otherwise 1
- * Detect if an SD card is inserted
- * (uses SD_CD pin, returns 0 on card detect)
- */
-STATIC INLINE int32_t Chip_SDMMC_CardNDetect(void)
-{
-	return IP_SDMMC_CardNDetect(LPC_SDMMC);
-}
-
-/**
- * @brief	Detect if write protect is enabled
- * @return	Returns 1 if card is write protected, otherwise 0
- * Detect if write protect is enabled
- * (uses SD_WP pin, returns 1 if card is write protected)
- */
-STATIC INLINE int32_t Chip_CardWpOn(void)
-{
-	return IP_SDMMC_CardWpOn(LPC_SDMMC);
-}
-
-/**
- * @brief	Initializes the MCI card controller
- * @return	None
- */
-STATIC INLINE void Chip_SDMMC_Init(void)
-{
-	IP_SDMMC_Init(LPC_SDMMC);
-}
-
-/**
- * @brief	Enable or disable slot power
- * @param	enable	: !0 to enable, or 0 to disable
- * @return	None
- * Enable or disable slot power, !0 = enable slot power
- * (Uses SD_POW pin, set to high or low based on enable parameter state)
- */
-STATIC INLINE void Chip_SDMMC_PowerOnOff(int32_t enable)
-{
-	IP_SDMMC_PowerOnOff(LPC_SDMMC, enable);
-}
-
-/**
- * @brief	Sets the SD interface interrupt mask
- * @param	iVal	: Interrupts to enable, Or'ed values MCI_INT_*
- * @return	None
- */
-STATIC INLINE void Chip_SDMMC_SetIntMask(uint32_t iVal)
-{
-	IP_SDMMC_SetIntMask(LPC_SDMMC, iVal);
-}
-
-/**
- * @brief	Returns the current SD status, clears pending ints, and disables all ints
- * @return	Current pending interrupt status of Or'ed values MCI_INT_*
- */
-uint32_t Chip_SDMMC_GetIntStatus(void);
-
-/**
- * @brief	Get card's current state (idle, transfer, program, etc.)
- * @return	Current SD card transfer state
- */
-int32_t Chip_SDMMC_GetState(void);
-
-/**
- * @brief	Function to enumerate the SD/MMC/SDHC/MMC+ cards
- * @param	pcardinfo	: Pointer to pre-allocated card info structure
- * @return	1 if a card is acquired, otherwise 0
- */
-uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo);
-
-/**
- * @brief	Get the device size of SD/MMC card (after enumeration)
- * @return	Card size (capacity)
- */
-int32_t Chip_SDMMC_GetDeviceSize(void);
-
-/**
- * @brief	Performs the read of data from the SD/MMC card
- * @param	buffer		: Pointer to data buffer to copy to
- * @param	start_block	: Start block number
- * @param	num_blocks	: Number of block to read
- * @return	Bytes read, or 0 on error
- */
-int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks);
-
-/**
- * @brief	Performs write of data to the SD/MMC card
- * @param	buffer		: Pointer to data buffer to copy to
- * @param	start_block	: Start block number
- * @param	num_blocks	: Number of block to write
- * @return	Number of bytes actually written, or 0 on error
- */
-int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SDMMC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h
deleted file mode 100644
index 5a20959261..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * @brief	SPIFI ROM driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SPIFI_ROM_API_H_
-#define __SPIFI_ROM_API_H_
-
-#include "chip.h"
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* define the symbol TESTING in the environment	if test output desired */
-
-/** @ingroup IP_SPIFI_001
- * @{
- */
-
-/* maintain LONGEST_PROT >= the length (in bytes) of the largest
-    protection block of any serial flash that this driver handles */
-#define LONGEST_PROT 68
-
-typedef uint8_t uc;
-
-#ifndef NULL
-#define NULL ((void *) 0)
-#endif
-
-/** Protection/sector descriptors */
-typedef struct {
-	uint32_t base;
-	uc flags;
-	int8_t log2;
-	uint16_t rept;
-} protEnt;
-/* bits in the flags byte */
-enum {RWPROT = 1};
-
-#if 0
-
-/* overall data structure includes # sectors, length of protection reg,
-   array of descriptors */
-typedef struct {
-	uint16_t sectors;
-	uint16_t protBytes;
-	protEnt *entries;
-} protDesc;
-#endif
-
-typedef union {
-	uint16_t hw;
-	uc byte[2];
-} stat_t;
-/** The object that spifi_init returns, and other routines use as an operand */
-typedef struct {
-	uint32_t base, regbase, devSize, memSize;
-	uc mfger, devType, devID, busy;
-	stat_t stat;
-	uint16_t reserved;
-	uint16_t set_prot, write_prot;
-	uint32_t mem_cmd, prog_cmd;
-	uint16_t sectors, protBytes;
-	uint32_t opts, errCheck;
-	uc erase_shifts[4], erase_ops[4];
-	protEnt *protEnts;
-	char prot[LONGEST_PROT];
-} SPIFIobj;
-
-/** operands of program and erase */
-typedef struct {
-	char *dest;
-	uint32_t length;
-	char *scratch;
-	int32_t protect;
-	uint32_t options;
-} SPIFIopers;
-
-/** instruction classes for wait_busy */
-typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
-
-/** @defgroup IP_SPIFI_OPTIONS IP: SPIFI configuration options
- * @ingroup IP_SPIFI_001
- * Options used to configure SPIFI
- * @{
- */
-
-/** The SCL output is high when a frame/command is not in progress.
-    Note that S_MODE3+S_FULLCLK+S_RCVCLK will not work. Use S_MODE0
-    or S_INTCLK. */
-#define S_MODE3 1
-
-/** SCL is low when a frame/command is not in progress. (default) */
-#define S_MODE0 0
-
-/** SPI mode and the slowest, most basic/compatible read operation will be used. */
-#define S_MINIMAL 2
-
-/** The fastest read operation provided by the device will be used. (default) */
-#define S_MAXIMAL 0
-
-/** Data is sampled using the SCL clock fed back from the pin. This allows
-    more time for the serial flash to present each bit or group of bits,
-    but when used with S_FULLCLK can endanger hold time for data from the
-    flash. */
-#define S_RCVCLK 0x80
-
-/** Data is sampled using the internal clock from which the SCL pin is driven. (default) */
-#define S_INTCLK 0
-
-/** Data from the serial flash is sampled on falling edges on the SCL
-    output, allowing a full clock period for the serial flash to present
-    each bit or group of bits. */
-#define S_FULLCLK 0x40
-
-/** Data from the serial flash is sampled on rising edges of the SCL
-    output, as in classic SPI applications. Suitable for slower clock rates. (default) */
-#define S_HALFCLK 0
-
-/** If the connected device can operate in dual mode (2 bits per clock),
-    dual mode will be used, else SPI mode. */
-#define S_DUAL 0x100
-
-/**
- * @}
- */
-
-/** @defgroup IP_SPIFI_OPTIONS_PROGRAM IP: SPIFI programming options
- * @ingroup IP_SPIFI_001
- * Options used to configure SPIFI programming
- * @{
- */
-
-/** All sectors in dest to dest+length will be erased */
-#define S_FORCE_ERASE 4
-
-/** Erasing is handled by the caller not by the driver */
-#define S_ERASE_NOT_REQD 8
-
-/** Erasing is handled by the caller not by the driver */
-#define S_CALLER_ERASE 8
-
-/** Erasing is done when necessary. (default) */
-#define S_ERASE_AS_REQD 0
-
-/** Data will be read back and checked after programming. */
-#define S_VERIFY_PROG 0x10
-
-/** Sectors will be read back and checked for 0xFF after erasing. */
-#define S_VERIFY_ERASE 0x20
-
-/** No reading or checking will be done. (default) */
-#define S_NO_VERIFY 0
-
-/** Write protection is handled by the caller not by the driver. */
-#define S_CALLER_PROT 0x200
-
-/** The driver removes protection before the operation, and sets it as specified thereafter. (default) */
-#define S_DRIVER_PROT 0
-
-/**
- * @}
- */
-
-/* the following values in the first post-address memory command byte work
-   for all known quad devices that support "no opcode" operation */
-#define NO_OPCODE_FOLLOWS 0xA5
-#define    OPCODE_FOLLOWS 0xFF
-
-/* basic SPI commands for serial flash */
-#define BASE_READ_CMD        (CMD_RD << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | UNL_DATA)
-#define FAST_READ_CMD (CMD_READ_FAST << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | 1 << INTLEN_SHIFT | UNL_DATA)
-#define BASE_PROG_CMD      (CMD_PROG << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | DOUT)
-
-/* the length of a standard	program command is 256 on all devices */
-#define PROG_SIZE 256
-
-/* options in obj->opts (mostly for setMulti) */
-/* used by Winbond: send 0xA3 command so hardware can read faster */
-#define OPT_SEND_A3        1
-/* used by SST: send 0x38 command to enable quad and allow full command set */
-#define OPT_SEND_38        2
-/* used by Winbond and others: read status reg 2, check it,
-    if necessary write it back with Quad Enable set */
-#define OPT_35_OR02_01     4
-/* used by Atmel: read Configuration register, if necessary set Quad Enable */
-#define OPT_3F_OR80_3E     8
-/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
-#define OPT_65_CLR_C0_61   0x10
-/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
-   to set # dummy bytes and allow XIP mode */
-#define OPT_81          0x20
-/* set for devices without full device erase command (Numonyx type 0x40) */
-#define OPT_NO_DEV_ERASE 0x40
-/* used by Macronix: status reg 2 includes selection between write-protect
-    in status reg and command-based */
-#define OPT_WPSEL       0x80
-/* set when protection data has been read into the SPIFI object */
-#define OPT_PROT_READ  0x100
-/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
-#define OPT_4BAD       0x200
-/* set if setMulti should set the Dual bit in Control reg */
-#define OPT_DUAL       0x400
-/* send "# dummy bits" in C0 command to Winbond */
-#define OPT_C0         0x800
-/* set QE for Chingis */
-#define OPT_05_OR40_01 0x1000
-/* write status does not go busy */
-#define OPT_01_NO_BUSY 0x2000
-/* protection mode bits moved from protMode byte to opts  Fri May 13 2011 */
-#define OPT_PROT_STAT 0x4000
-#define OPT_PROT_REG  0x8000
-#define OPT_PROT_CMD3 0x10000
-#define OPT_PROT_CMDE 0x20000
-#define OPT_PROT_MASK 0x3C000
-
-#define OPT_ALL_QUAD  0x40000
-
-#ifndef OMIT_ROM_TABLE
-/* interface to ROM API */
-typedef struct {
-	int32_t (*spifi_init)(SPIFIobj *obj, uint32_t csHigh, uint32_t options,
-						  uint32_t mhz);
-	int32_t (*spifi_program)(SPIFIobj *obj, char *source, SPIFIopers *opers);
-	int32_t (*spifi_erase)(SPIFIobj *obj, SPIFIopers *opers);
-	/* mode switching */
-	void (*cancel_mem_mode)(SPIFIobj *obj);
-	void (*set_mem_mode)(SPIFIobj *obj);
-
-	/* mid level functions */
-	int32_t (*checkAd)(SPIFIobj *obj, SPIFIopers *opers);
-	int32_t (*setProt)(SPIFIobj *obj, SPIFIopers *opers, char *change,
-					   char *saveProt);
-	int32_t (*check_block)(SPIFIobj *obj, char *source, SPIFIopers *opers,
-						   uint32_t check_program);
-	int32_t (*send_erase_cmd)(SPIFIobj *obj, uint8_t op, uint32_t addr);
-	uint32_t (*ck_erase)(SPIFIobj *obj, uint32_t *addr, uint32_t length);
-	int32_t (*prog_block)(SPIFIobj *obj, char *source, SPIFIopers *opers,
-						  uint32_t *left_in_page);
-	uint32_t (*ck_prog)(SPIFIobj *obj, char *source, char *dest, uint32_t length);
-
-	/* low level functions */
-	void (*setSize)(SPIFIobj *obj, int32_t value);
-	int32_t (*setDev)(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
-					  uint32_t prog_cmd);
-	uint32_t (*cmd)(uc op, uc addrLen, uc intLen, uint16_t len);
-	uint32_t (*readAd)(SPIFIobj *obj, uint32_t cmd, uint32_t addr);
-	void (*send04)(SPIFIobj *obj, uc op, uc len, uint32_t value);
-	void (*wren_sendAd)(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
-	int32_t (*write_stat)(SPIFIobj *obj, uc len, uint16_t value);
-	int32_t (*wait_busy)(SPIFIobj *obj, uc prog_or_erase);
-} SPIFI_RTNS;
-
-#define SPIFI_ROM_PTR  0x10400118
-
-#define define_spifi_romPtr(name) const SPIFI_RTNS * name = *((SPIFI_RTNS * *) SPIFI_ROM_PTR)
-#endif /* OMIT_ROM_TABLE */
-
-#ifdef USE_SPIFI_LIB
-extern SPIFI_RTNS spifi_table;
-#endif  /* USE_SPIFI_LIB */
-
-/* example of using this interface:
-   #include "spifi_rom_api.h"
-   #define CSHIGH 4
-   #define SPIFI_MHZ 80
-   #define source_data_ad (char *)1234
-
-    int32_t rc;
-    SPIFIopers opers;
-
-    define_spifi_romPtr(spifi);
-    SPIFIobj *obj = malloc(sizeof(SPIFIobj));
-    if (!obj) { can't allocate memory }
-
-    rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
-    if (rc) { investigate init error rc }
-    printf ("the serial flash contains %d bytes\n", obj->devSize);
-
-    opers.dest = where_to_program;
-    opers.length = how_many_bytes;
-    opers.scratch = NULL;			// unprogrammed data is not saved/restored
-    opers.protect = -1;				// save & restore protection
-    opers.options = S_VERIFY_PROG;
-
-    rc = spifi->spifi_program (obj, source_data_ad, &opers);
-    if (rc) { investigate program error rc }
- */
-
-/* these are for normal users, including boot code */
-int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
-
-int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
-
-int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
-
-/* these are used by the manufacturer-specific init functions */
-void setSize (SPIFIobj *obj, int32_t value);
-
-int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
-
-uint32_t read04(SPIFIobj *obj, uc op, uc len);
-
-int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
-
-void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
-
-/* needs to be defined for each platform */
-void pullMISO(int high);
-
-#ifdef TESTING
-/* used by testing code */
-unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
-
-/* predeclare a debug routine */
-void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
-
-#endif
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* __SPIFI_ROM_API_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c
deleted file mode 100644
index a6c78915fd..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- * @brief LPC18xx/43xx SSP driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "ssp_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-/** SSP macro: write 2 bytes to FIFO buffer */
-#define SSP_Write2BFifo(pSSP, \
-						xf_setup) if (xf_setup->tx_data) {IP_SSP_SendFrame(pSSP, \
-																		   (*(uint16_t *) ((uint32_t) xf_setup->tx_data	\
-																						   + xf_setup->tx_cnt))); }	\
-	else {IP_SSP_SendFrame(pSSP, 0xFFFF); }	\
-	xf_setup->tx_cnt += 2;
-
-/** SSP macro: write 1 bytes to FIFO buffer */
-#define SSP_Write1BFifo(pSSP, \
-						xf_setup) if (xf_setup->tx_data) {IP_SSP_SendFrame(pSSP, \
-																		   (*(uint8_t *) ((uint32_t) xf_setup->tx_data \
-																						  + xf_setup->tx_cnt))); } \
-	else {IP_SSP_SendFrame(pSSP, 0xFF); } \
-	xf_setup->tx_cnt++;
-
-/** SSP macro: read 1 bytes from FIFO buffer */
-#define SSP_Read2BFifo(pSSP, xf_setup, \
-					   rDat)  while (IP_SSP_GetStatus(pSSP,	\
-													  SSP_STAT_RNE) == SET && xf_setup->rx_cnt < xf_setup->length) { \
-		rDat = IP_SSP_ReceiveFrame(pSSP); \
-		if (xf_setup->rx_data) { \
-			*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;	\
-		} \
-		xf_setup->rx_cnt += 2; \
-}
-
-/** SSP macro: read 2 bytes from FIFO buffer */
-#define SSP_Read1BFifo(pSSP, xf_setup, \
-					   rDat)  while (IP_SSP_GetStatus(pSSP,	\
-													  SSP_STAT_RNE) == SET && xf_setup->rx_cnt < xf_setup->length) { \
-		rDat = IP_SSP_ReceiveFrame(pSSP); \
-		if (xf_setup->rx_data) { \
-			*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat; \
-		} \
-		xf_setup->rx_cnt++;	\
-}
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* SSP Polling Read/Write in blocking mode */
-uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup)
-{
-	uint16_t rDat;
-
-	/* Clear all remaining frames in RX FIFO */
-	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
-		IP_SSP_ReceiveFrame(pSSP);
-	}
-
-	/* Clear status */
-	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
-
-	if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
-		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
-			/* write data to buffer */
-			if (( IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
-				SSP_Write2BFifo(pSSP, xf_setup)
-			}
-
-			/* Check overrun error */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/* Check for any data available in RX FIFO */
-			SSP_Read2BFifo(pSSP, xf_setup, rDat)
-		}
-
-		if (xf_setup->tx_data) {
-			return xf_setup->tx_cnt;
-		}
-		else if (xf_setup->rx_data) {
-			return xf_setup->rx_cnt;
-		}
-		return 0;
-	}
-	else {
-		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
-			/* write data to buffer */
-			if (( IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
-				SSP_Write1BFifo(pSSP, xf_setup)
-			}
-
-			/* Check overrun error */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/* Check for any data available in RX FIFO */
-			SSP_Read1BFifo(pSSP, xf_setup, rDat)
-		}
-
-		if (xf_setup->tx_data) {
-			return xf_setup->tx_cnt;
-		}
-		else if (xf_setup->rx_data) {
-			return xf_setup->rx_cnt;
-		}
-		return 0;
-	}
-}
-
-/* SSP Polling Write in blocking mode */
-uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len)
-{
-	uint32_t tx_cnt = 0, rx_cnt = 0;
-
-	/* Clear all remaining frames in RX FIFO */
-	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
-		IP_SSP_ReceiveFrame(pSSP);
-	}
-
-	/* Clear status */
-	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
-
-	if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
-		uint16_t *wdata16;
-
-		wdata16 = (uint16_t *) buffer;
-
-		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
-			/* write data to buffer */
-			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
-				IP_SSP_SendFrame(pSSP, *wdata16);
-				wdata16++;
-				tx_cnt += 2;
-			}
-
-			/* Check overrun error */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/* Check for any data available in RX FIFO */
-			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
-				IP_SSP_ReceiveFrame(pSSP);	/* read dummy data */
-				rx_cnt += 2;
-			}
-		}
-
-		return tx_cnt;
-	}
-	else {
-		uint8_t *wdata8;
-
-		wdata8 = buffer;
-
-		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
-			/* write data to buffer */
-			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
-				IP_SSP_SendFrame(pSSP, *wdata8);
-				wdata8++;
-				tx_cnt++;
-			}
-
-			/* Check overrun error */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/* Check for any data available in RX FIFO */
-			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
-				IP_SSP_ReceiveFrame(pSSP);	/* read dummy data */
-				rx_cnt++;
-			}
-		}
-
-		return tx_cnt;
-	}
-}
-
-/* SSP Polling Read in blocking mode */
-uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len)
-{
-	uint32_t rx_cnt = 0, tx_cnt = 0;
-
-	/* Clear all remaining frames in RX FIFO */
-	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
-		IP_SSP_ReceiveFrame(pSSP);
-	}
-
-	/* Clear status */
-	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
-
-	if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
-		uint16_t *rdata16;
-
-		rdata16 = (uint16_t *) buffer;
-
-		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
-			/* write data to buffer */
-			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
-				IP_SSP_SendFrame(pSSP, 0xFFFF);	/* just send dummy data */
-				tx_cnt += 2;
-			}
-
-			/* Check overrun error */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/* Check for any data available in RX FIFO */
-			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
-				*rdata16 = IP_SSP_ReceiveFrame(pSSP);
-				rdata16++;
-				rx_cnt += 2;
-			}
-		}
-
-		return rx_cnt;
-	}
-	else {
-		uint8_t *rdata8;
-
-		rdata8 = buffer;
-
-		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
-			/* write data to buffer */
-			if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
-				IP_SSP_SendFrame(pSSP, 0xFF);	/* just send dummy data		 */
-				tx_cnt++;
-			}
-
-			/* Check overrun error */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/* Check for any data available in RX FIFO */
-			while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
-				*rdata8 = IP_SSP_ReceiveFrame(pSSP);
-				rdata8++;
-				rx_cnt++;
-			}
-		}
-
-		return rx_cnt;
-	}
-}
-
-/* Clean all data in RX FIFO of SSP */
-void Chip_SSP_Int_FlushData(LPC_SSP_Type *pSSP)
-{
-	if (IP_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
-		while (IP_SSP_GetStatus(pSSP, SSP_STAT_BSY)) ;
-	}
-
-	/* Clear all remaining frames in RX FIFO */
-	while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
-		IP_SSP_ReceiveFrame(pSSP);
-	}
-
-	/* Clear status */
-	IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
-}
-
-/* SSP Interrupt Read/Write with 8-bit frame width */
-Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup)
-{
-	uint16_t rDat;
-
-	/* Check overrun error in RIS register */
-	if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-		return ERROR;
-	}
-
-	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
-		/* check if RX FIFO contains data */
-		SSP_Read1BFifo(pSSP, xf_setup, rDat)
-
-		while ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
-			/* Write data to buffer */
-			SSP_Write1BFifo(pSSP, xf_setup)
-
-			/* Check overrun error in RIS register */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/*  Check for any data available in RX FIFO */
-			SSP_Read1BFifo(pSSP, xf_setup, rDat)
-		}
-		return SUCCESS;
-	}
-
-	return ERROR;
-}
-
-/* SSP Interrupt Read/Write with 16-bit frame width */
-Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup)
-{
-	uint16_t rDat;
-
-	/* Check overrun error in RIS register */
-	if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-		return ERROR;
-	}
-
-	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
-		/* check if RX FIFO contains data */
-		SSP_Read2BFifo(pSSP, xf_setup, rDat)
-
-		while ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
-			/* Write data to buffer */
-			SSP_Write2BFifo(pSSP, xf_setup)
-
-			/* Check overrun error in RIS register */
-			if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
-				return ERROR;
-			}
-
-			/*  Check for any data available in RX FIFO			 */
-			SSP_Read2BFifo(pSSP, xf_setup, rDat)
-		}
-		return SUCCESS;
-	}
-
-	return ERROR;
-}
-
-/* Set the SSP operating modes, master or slave */
-void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master)
-{
-	if (master) {
-		IP_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
-	}
-	else {
-		IP_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
-	}
-}
-
-/* Set the clock frequency for SSP interface */
-void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate)
-{
-	uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
-
-	if (pSSP == LPC_SSP0) {
-		ssp_clk = Chip_Clock_GetBaseClocktHz(CLK_BASE_SSP0);
-	}
-	else {
-		ssp_clk = Chip_Clock_GetBaseClocktHz(CLK_BASE_SSP1);
-	}
-
-	cr0_div = 0;
-	cmp_clk = 0xFFFFFFFF;
-	prescale = 2;
-
-	while (cmp_clk > bit_rate) {
-		cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
-		if (cmp_clk > bit_rate) {
-			cr0_div++;
-			if (cr0_div > 0xFF) {
-				cr0_div = 0;
-				prescale += 2;
-			}
-		}
-	}
-
-	IP_SSP_Set_ClockRate(pSSP, cr0_div, prescale);
-}
-
-/* Set up the SSP frame format */
-void Chip_SSP_Set_Format(LPC_SSP_Type *pSSP, SSP_ConfigFormat *format)
-{
-	IP_SSP_Set_Format(pSSP, format->bits, format->frameFormat, format->clockFormat);
-}
-
-/* Enable/Disable SSP interrupt */
-void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
-{
-	IP_SSP_Int_Enable(pSSP, SSP_TXIM, NewState);
-}
-
-/* Enable/Disable DMA */
-void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
-{
-	IP_SSP_DMA_Cmd(pSSP, SSP_DMA_RX, NewState);
-	IP_SSP_DMA_Cmd(pSSP, SSP_DMA_TX, NewState);
-}
-
-/* Initialize the SSP */
-void Chip_SSP_Init(LPC_SSP_Type *pSSP)
-{
-	IP_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
-	IP_SSP_Set_Format(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
-	Chip_SSP_Set_BitRate(pSSP, 100000);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h
deleted file mode 100644
index a5809d1691..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
- * @brief LPC18xx/43xx SSP driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SSP_18XX_43XX_H_
-#define __SSP_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SSP_18XX_43XX CHIP: LPC18xx/43xx SSP driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/*
- * @brief SSP clock format
- */
-typedef enum SSP_ClockFormat {
-	SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),		/**< CPHA = 0, CPOL = 0 */
-	SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),		/**< CPHA = 0, CPOL = 1 */
-	SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),		/**< CPHA = 1, CPOL = 0 */
-	SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),		/**< CPHA = 1, CPOL = 1 */
-	SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
-	SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
-	SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
-	SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
-} SSP_ClockFormat;
-
-/*
- * @brief SSP frame format
- */
-typedef enum SSP_FrameFormat {
-	SSP_FRAMEFORMAT_SPI = (0 << 4),			/**< Frame format: SPI */
-	SSP_FRAMEFORMAT_TI = (1u << 4),			/**< Frame format: TI SSI */
-	SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),	/**< Frame format: Microwire */
-} SSP_FrameFormat;
-
-/*
- * @brief Number of bits per frame
- */
-typedef enum SSP_Bits {
-	SSP_BITS_4 = (3u << 0),		/**< 4 bits/frame */
-	SSP_BITS_5 = (4u << 0),		/**< 5 bits/frame */
-	SSP_BITS_6 = (5u << 0),		/**< 6 bits/frame */
-	SSP_BITS_7 = (6u << 0),		/**< 7 bits/frame */
-	SSP_BITS_8 = (7u << 0),		/**< 8 bits/frame */
-	SSP_BITS_9 = (8u << 0),		/**< 9 bits/frame */
-	SSP_BITS_10 = (9u << 0),	/**< 10 bits/frame */
-	SSP_BITS_11 = (10u << 0),	/**< 11 bits/frame */
-	SSP_BITS_12 = (11u << 0),	/**< 12 bits/frame */
-	SSP_BITS_13 = (12u << 0),	/**< 13 bits/frame */
-	SSP_BITS_14 = (13u << 0),	/**< 14 bits/frame */
-	SSP_BITS_15 = (14u << 0),	/**< 15 bits/frame */
-	SSP_BITS_16 = (15u << 0),	/**< 16 bits/frame */
-} SSP_Bits;
-
-/*
- * @brief SSP config format
- */
-typedef struct SSP_ConfigFormat {
-	SSP_Bits bits;				/**< Format config: bits/frame */
-	SSP_ClockFormat clockFormat;/**< Format config: clock phase/polarity */
-	SSP_FrameFormat frameFormat;/**< Format config: SPI/TI/Microwire */
-} SSP_ConfigFormat;
-
-/*
- * @brief SSP mode
- */
-typedef enum SSP_Mode {
-	SSP_MODE_MASTER = (0 << 2),	/**< Master mode */
-	SSP_MODE_SLAVE = (1u << 2),	/**< Slave mode */
-} SSP_Mode;
-
-/*
- * @brief SPI address
- */
-typedef struct {
-	uint8_t port;
-	uint8_t pin;
-} SPI_Address_t;
-
-/*
- * @brief SSP data setup structure
- */
-typedef struct {
-	void      *tx_data;	/**< Pointer to transmit data */
-	uint32_t  tx_cnt;	/**< Transmit counter */
-	void      *rx_data;	/**< Pointer to transmit data */
-	uint32_t  rx_cnt;	/**< Receive counter */
-	uint32_t  length;	/**< Length of transfer data */
-} Chip_SSP_DATA_SETUP_Type;
-
-/** SSP configuration parameter defines */
-/** Clock phase control bit */
-#define SSP_CPHA_FIRST          SSP_CR0_CPHA_FIRST
-#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
-
-/** Clock polarity control bit */
-/* There's no bug here!!!
- * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
- * That means the active clock is in HI state.
- * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
- * high between frames. That means the active clock is in LO state.
- */
-#define SSP_CPOL_HI             SSP_CR0_CPOL_LO
-#define SSP_CPOL_LO             SSP_CR0_CPOL_HI
-
-/** SSP master mode enable */
-#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
-#define SSP_MASTER_MODE         SSP_CR1_MASTER_EN
-
-/**
- * @brief	Get the current status of SSP controller
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @param	Stat	: Type of status, should be :
- *						- SSP_STAT_TFE
- *						- SSP_STAT_TNF
- *						- SSP_STAT_RNE
- *						- SSP_STAT_RFF
- *						- SSP_STAT_BSY
- * @return	SSP controller status, SET or RESET
- */
-STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_Type *pSSP, SSP_Status_Type Stat)
-{
-	return IP_SSP_GetStatus(pSSP, Stat);
-}
-
-/**
- * @brief	Enable/Disable SSP operation
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	Nothing
- */
-STATIC INLINE void Chip_SSP_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
-{
-	IP_SSP_Cmd(pSSP, NewState);
-}
-
-/**
- * @brief	Disable SSP operation
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @return	Nothing
- * The SSP controller is disabled
- */
-STATIC INLINE void Chip_SSP_DeInit(LPC_SSP_Type *pSSP)
-{
-	IP_SSP_DeInit(pSSP);
-}
-
-/**
- * @brief	Enable/Disable loopback mode
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	Nothing
- * Serial input is taken from the serial output (MOSI or MISO) rather
- * than the serial input pin
- */
-STATIC INLINE void Chip_SSP_LoopBackCmd(LPC_SSP_Type *pSSP, FunctionalState NewState)
-{
-	IP_SSP_LoopBackCmd(pSSP, NewState);
-}
-
-/**
- * @brief   Clean all data in RX FIFO of SSP
- * @param	pSSP			: The base SSP peripheral on the chip
- * @return	Nothing
- */
-void Chip_SSP_Int_FlushData(LPC_SSP_Type *pSSP);
-
-/**
- * @brief   SSP Interrupt Read/Write with 8-bit frame width
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_Type structure that contains specified
- * 							information about transmit/receive data	configuration
- * @return	SUCCESS or ERROR
- */
-Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup);
-
-/**
- * @brief   SSP Interrupt Read/Write with 16-bit frame width
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_Type structure that contains specified
- * 							information about transmit/receive data	configuration
- * @return	SUCCESS or ERROR
- */
-Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup);
-
-/**
- * @brief   SSP Polling Read/Write in blocking mode
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_Type structure that contains specified
- * 							information about transmit/receive data	configuration
- * @return	Actual data length has been transferred
- *
- * This function can be used in both master and slave mode. It starts with writing phase and after that,
- * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
- * through xf_setup param.
- */
-uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup);
-
-/**
- * @brief   SSP Polling Write in blocking mode
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	buffer			: Buffer address
- * @param	buffer_len		: Buffer length
- * @return	Actual data length has been transferred
- *
- * This function can be used in both master and slave mode. First, a writing operation will send
- * the needed data. After that, a dummy reading operation is generated to clear data buffer
- */
-uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len);
-
-/**
- * @brief   Note here
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	buffer			: Buffer address
- * @param	buffer_len		: The length of buffer
- * @return	Actual data length has been transferred
- *
- * This function can be used in both master and slave mode. First, a dummy writing operation is generated
- * to clear data buffer. After that, a reading operation will receive the needed data
- */
-uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len);
-
-/**
- * @brief   Initialize the SSP
- * @param	pSSP			: The base SSP peripheral on the chip
- * @return	Nothing
- */
-void Chip_SSP_Init(LPC_SSP_Type *pSSP);
-
-/**
- * @brief   Set the SSP operating modes, master or slave
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	master			: 1 to set master, 0 to set slave
- * @return	Nothing
- */
-void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master);
-
-/**
- * @brief   Set the clock frequency for SSP interface
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	bit_rate		: The SSP bit rate
- * @return	Nothing
- */
-void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate);
-
-/**
- * @brief   Set up the SSP frame format
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	format			: Structure used to format frame
- * @return	Nothing
- */
-void Chip_SSP_Set_Format(LPC_SSP_Type *pSSP, SSP_ConfigFormat *format);
-
-/**
- * @brief   Enable/Disable SSP interrupt
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	NewState		: ENABLE or DISABLE interrupt
- * @return	Nothing
- */
-void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState);
-
-/**
- * @brief   Enable/Disable DMA
- * @param	pSSP			: The base SSP peripheral on the chip
- * @param	NewState		: ENABLE or DISABLE DMA
- * @return	Nothing
- */
-void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SSP_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h
deleted file mode 100644
index b7b654e1e1..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * @brief Timer/PWM control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __TIMER_18XX_43XX_H_
-#define __TIMER_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup TIMER_18XX_43XX CHIP: LPC18xx/43xx Timer driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Determine if a match interrupt is pending
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match interrupt number to check
- * @return	false if the interrupt is not pending, otherwise true
- * Determine if the match interrupt for the passed timer and match
- * counter is pending.
- */
-STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	return IP_TIMER_MatchPending(TMRx, matchnum);
-}
-
-/**
- * @brief	Determine if a capture interrupt is pending
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture interrupt number to check
- * @return	false if the interrupt is not pending, otherwise true
- * Determine if the capture interrupt for the passed capture pin is
- * pending.
- */
-STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	return IP_TIMER_CapturePending(TMRx, capnum);
-}
-
-/**
- * @brief	Clears a (pending) match interrupt
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match interrupt number to clear
- * @return	Nothing
- * Clears a pending timer match interrupt.
- */
-STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_ClearMatch(TMRx, matchnum);
-}
-
-/**
- * @brief	Clears a (pending) capture interrupt
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture interrupt number to clear
- * @return	Nothing
- * Clears a pending timer capture interrupt.
- */
-STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_ClearCapture(TMRx, capnum);
-}
-
-/**
- * @brief	Enables the timer (starts count)
- * @param	TMRx	: Pointer to timer IP register address
- * @return	Nothing
- * Enables the timer to start counting.
- */
-STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_Type *TMRx)
-{
-	IP_TIMER_Enable(TMRx);
-}
-
-/**
- * @brief	Disables the timer (stops count)
- * @param	TMRx	: Pointer to timer IP register address
- * @return	Nothing
- * Disables the timer to stop counting.
- */
-STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_Type *TMRx)
-{
-	IP_TIMER_Disable(TMRx);
-}
-
-/**
- * @brief	Returns the current timer count
- * @param	TMRx	: Pointer to timer IP register address
- * @return	Current timer terminal count value
- * Returns the current timer terminal count.
- */
-STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_Type *TMRx)
-{
-	return IP_TIMER_ReadCount(TMRx);
-}
-
-/**
- * @brief	Returns the current prescale count
- * @param	TMRx	: Pointer to timer IP register address
- * @return	Current timer prescale count value
- * Returns the current prescale count.
- */
-STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_Type *TMRx)
-{
-	return IP_TIMER_ReadPrescale(TMRx);
-}
-
-/**
- * @brief	Sets the prescaler value
- * @param	TMRx		: Pointer to timer IP register address
- * @param	prescale	: Prescale value to set the prescale register to
- * @return	Nothing
- * Sets the prescale count value.
- */
-STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_Type *TMRx, uint32_t prescale)
-{
-	IP_TIMER_PrescaleSet(TMRx, prescale);
-}
-
-/**
- * @brief	Sets a timer match value
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer to set match count for
- * @param	matchval	: Match value for the selected match count
- * @return	Nothing
- * Sets ones of the timer match values.
- */
-STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_Type *TMRx, int8_t matchnum, uint32_t matchval)
-{
-	IP_TIMER_SetMatch(TMRx, matchnum, matchval);
-}
-
-/**
- * @brief	Reads a capture register
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture register to read
- * @return	The selected capture register value
- * Returns the selected capture register value.
- */
-STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	return IP_TIMER_ReadCapture(TMRx, capnum);
-}
-
-/**
- * @brief	Resets the timer terminal and prescale counts to 0
- * @param	TMRx	: Pointer to timer IP register address
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_Reset(LPC_TIMER_Type *TMRx)
-{
-	IP_TIMER_Reset(TMRx);
-}
-
-/**
- * @brief	Enables a match interrupt that fires when the terminal count
- *			matches the match counter value.
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_MatchEnableInt(TMRx, matchnum);
-}
-
-/**
- * @brief	Disables a match interrupt for a match counter.
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_MatchDisableInt(TMRx, matchnum);
-}
-
-/**
- * @brief	For the specific match counter, enables reset of the terminal count register when a match occurs
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_ResetOnMatchEnable(TMRx, matchnum);
-}
-
-/**
- * @brief	For the specific match counter, disables reset of the terminal count register when a match occurs
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_ResetOnMatchDisable(TMRx, matchnum);
-}
-
-/**
- * @brief	Enable a match timer to stop the terminal count when a
- *			match count equals the terminal count.
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_StopOnMatchEnable(TMRx, matchnum);
-}
-
-/**
- * @brief	Disable stop on match for a match timer. Disables a match timer
- *			to stop the terminal count when a match count equals the terminal count.
- * @param	TMRx		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_Type *TMRx, int8_t matchnum)
-{
-	IP_TIMER_StopOnMatchDisable(TMRx, matchnum);
-}
-
-/**
- * @brief	Enables capture on on rising edge of selected CAP signal for the
- *			selected capture register, enables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a rising edge.
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_CaptureRisingEdgeEnable(TMRx, capnum);
-}
-
-/**
- * @brief	Disables capture on on rising edge of selected CAP signal. For the
- *			selected capture register, disables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a rising edge.
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_CaptureRisingEdgeDisable(TMRx, capnum);
-}
-
-/**
- * @brief	Enables capture on on falling edge of selected CAP signal. For the
- *			selected capture register, enables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a falling edge.
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_CaptureFallingEdgeEnable(TMRx, capnum);
-}
-
-/**
- * @brief	Disables capture on on falling edge of selected CAP signal. For the
- *			selected capture register, disables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a falling edge.
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_CaptureFallingEdgeDisable(TMRx, capnum);
-}
-
-/**
- * @brief	Enables interrupt on capture of selected CAP signal. For the
- *			selected capture register, an interrupt will be generated when the enabled
- *			rising or falling edge on CAPn.capnum is detected.
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_CaptureEnableInt(TMRx, capnum);
-}
-
-/**
- * @brief	Disables interrupt on capture of selected CAP signal
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_Type *TMRx, int8_t capnum)
-{
-	IP_TIMER_CaptureDisableInt(TMRx, capnum);
-}
-
-/**
- * @brief	Sets external match control (MATn.matchnum) pin control
- * @param	TMRx			: Pointer to timer IP register address
- * @param	initial_state	: Initial state of the pin, high(1) or low(0)
- * @param	matchState		: Selects the match state for the pin
- * @param	matchnum		: MATn.matchnum signal to use
- * @return	Nothing
- * For the pin selected with matchnum, sets the function of the pin that occurs on
- * a terminal count match for the match count.
- */
-STATIC INLINE void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_Type *TMRx, int8_t initial_state,
-												 IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum)
-{
-	IP_TIMER_ExtMatchControlSet(TMRx, initial_state, matchState, matchnum);
-}
-
-/**
- * @brief	Sets timer count source and edge with the selected passed from CapSrc
- * @param	TMRx	: Pointer to timer IP register address
- * @param	capSrc	: timer clock source and edge
- * @param	capnum	: CAPn.capnum pin to use (if used)
- * @return	Nothing
- * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
- */
-STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_Type *TMRx,
-													 IP_TIMER_CAP_SRC_STATE_Type capSrc,
-													 int8_t capnum)
-{
-	IP_TIMER_SetCountClockSrc(TMRx, capSrc, capnum);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TIMER_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c
deleted file mode 100644
index 9e77a80c67..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * @brief LPC18xx/43xx UART chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "uart_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/** UART Ring buffer declaration*/
-static UART_RingBuffer_Type rb;
-
-/** Current Tx Interrupt enable state */
-static __IO FlagStatus TxIntStat;
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Get UART number based on selected UART */
-static UART_ID_Type Chip_UART_Get_UARTNum(LPC_USART_Type *UARTx)
-{
-	if (UARTx == LPC_USART0) {
-		return UART_0;
-	}
-	else if (UARTx == LPC_UART1) {
-		return UART_1;
-	}
-	else if (UARTx == LPC_USART2) {
-		return UART_2;
-	}
-
-	return UART_3;
-}
-
-/* Determine UART clock based in selected UART */
-static CCU_CLK_T Chip_UART_DetermineClk(LPC_USART_Type *UARTx) {
-	CCU_CLK_T uartclk;
-
-	/* Pick clock for uart BASED ON SELECTED uart */
-	if (UARTx == LPC_UART1) {
-		uartclk = CLK_MX_UART1;
-	}
-	if (UARTx == LPC_USART2) {
-		uartclk = CLK_MX_UART2;
-	}
-	if (UARTx == LPC_USART3) {
-		uartclk = CLK_MX_UART3;
-	}
-	else {
-		uartclk = CLK_MX_UART0;
-	}
-
-	return uartclk;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the UARTx peripheral */
-void Chip_UART_Init(LPC_USART_Type *UARTx)
-{
-	UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
-
-	/* Enable UART clocking. UART base clock(s) must already be enabled */
-	Chip_Clock_EnableOpts(Chip_UART_DetermineClk(UARTx), true, true, 1);
-
-	IP_UART_Init(UARTx, UARTPort);
-}
-
-/* De-initializes the UARTx peripheral */
-void Chip_UART_DeInit(LPC_USART_Type *UARTx)
-{
-	UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
-
-	IP_UART_DeInit(UARTx, UARTPort);
-
-	/* Disable UART clocking */
-	Chip_Clock_Disable(Chip_UART_DetermineClk(UARTx));
-}
-
-/* Determines best dividers to get a target baud rate */
-Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate)
-{
-	uint32_t uClk;
-
-	/* Get UART clock rate */
-	uClk = Chip_Clock_GetRate(Chip_UART_DetermineClk(UARTx));
-
-	return IP_UART_SetBaud(UARTx, baudrate, uClk);
-}
-
-/* Enable/Disable transmission on UART TxD pin */
-void Chip_UART_TxCmd(LPC_USART_Type *UARTx, FunctionalState NewState)
-{
-	UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
-
-	IP_UART_TxCmd(UARTx, UARTPort, NewState);
-}
-
-/* Get Interrupt Stream Status */
-UART_Int_Status Chip_UART_GetIntStatus(LPC_USART_Type *UARTx)
-{
-	uint32_t intsrc, tmp, tmp1;
-	UART_Int_Status ret = UART_ERROR;
-
-	/* Determine the interrupt source */
-	intsrc = Chip_UART_IntGetStatus(UARTx);
-
-	tmp = intsrc & UART_IIR_INTID_MASK;
-
-	/* Receive Line Status */
-	if (tmp == UART_IIR_INTID_RLS) {
-		/* Check line status */
-		tmp1 = (uint32_t) Chip_UART_GetLineStatus(UARTx);
-		/* Mask out the Receive Ready and Transmit Holding empty status */
-		tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \
-				 | UART_LSR_BI | UART_LSR_RXFE);
-		/* If any error exist */
-		if (tmp1) {
-			return UART_ERROR;
-		}
-	}
-
-	/* Receive Data Available or Character time-out */
-	if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI)) {
-		ret |= READY_TO_RECEIVE;
-	}
-
-	/* Transmit Holding Empty */
-	if (tmp == UART_IIR_INTID_THRE) {
-		ret |= READY_TO_SEND;
-	}
-	return ret;
-}
-
-/* UART interrupt service routine */
-void Chip_UART_Interrupt_Handler(LPC_USART_Type *UARTx)
-{
-	uint8_t tmpc;
-	uint32_t rLen;
-	UART_Int_Status Sts = Chip_UART_GetIntStatus(UARTx);
-	if (Sts == UART_ERROR) {
-		return;	/* error */
-
-	}
-	if (Sts & READY_TO_RECEIVE) {	/* ready for Read Data */
-		while (1) {
-			/* Call UART read function in UART driver */
-			rLen = Chip_UART_Receive(UARTx, &tmpc, 1, NONE_BLOCKING);
-			/* If data received */
-			if (rLen) {
-				/* Check if buffer is more space
-				 * If no more space, remaining character will be trimmed out
-				 */
-				if (!__BUF_IS_FULL(rb.rx_head, rb.rx_tail)) {
-					rb.rx[rb.rx_head] = tmpc;
-					__BUF_INCR(rb.rx_head);
-				}
-			}
-			/* no more data */
-			else {
-				break;
-			}
-		}
-	}
-
-	if (Sts & READY_TO_SEND) {	/* ready for Write Data */
-		/* Disable THRE interrupt */
-		Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
-
-		/* Wait for FIFO buffer empty, transfer UART_TX_FIFO_SIZE bytes
-		 * of data or break whenever ring buffers are empty */
-		/* Wait until THR empty */
-		while (Chip_UART_CheckBusy(UARTx) == SET) ;
-
-		while (!__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
-			/* Move a piece of data into the transmit FIFO */
-			if (Chip_UART_Send(UARTx, (uint8_t *) &rb.tx[rb.tx_tail], 1, NONE_BLOCKING)) {
-				/* Update transmit ring FIFO tail pointer */
-				__BUF_INCR(rb.tx_tail);
-			}
-			else {
-				break;
-			}
-		}
-
-		/* If there is no more data to send, disable the transmit
-		   interrupt - else enable it or keep it enabled */
-		if (__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
-			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
-			// Reset Tx Interrupt state
-			TxIntStat = RESET;
-		}
-		else {
-			/* Set Tx Interrupt state */
-			TxIntStat = SET;
-			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
-		}
-	}
-}
-
-/* UART transmit function for interrupt mode (using ring buffers) */
-uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_Type *UARTx, uint8_t *txbuf, uint8_t buflen)
-{
-	uint8_t *data = (uint8_t *) txbuf;
-	uint32_t bytes = 0;
-
-	/* Temporarily lock out UART transmit interrupts during this
-	   read so the UART transmit interrupt won't cause problems
-	   with the index values */
-	Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
-
-	/* Loop until transmit run buffer is full or until n_bytes
-	   expires */
-	while ((buflen > 0) && (!__BUF_IS_FULL(rb.tx_head, rb.tx_tail))) {
-		/* Write data from buffer into ring buffer */
-		rb.tx[rb.tx_head] = *data;
-		data++;
-
-		/* Increment head pointer */
-		__BUF_INCR(rb.tx_head);
-
-		/* Increment data count and decrement buffer size count */
-		bytes++;
-		buflen--;
-	}
-
-	/*
-	 * Check if current Tx interrupt enable is reset,
-	 * that means the Tx interrupt must be re-enabled
-	 * due to call UART_IntTransmit() function to trigger
-	 * this interrupt type
-	 */
-	if (TxIntStat == RESET) {
-		// Disable THRE interrupt
-		Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
-
-		/* Wait for FIFO buffer empty, transfer UART_TX_FIFO_SIZE bytes
-		 * of data or break whenever ring buffers are empty */
-		/* Wait until THR empty */
-		while (Chip_UART_CheckBusy(UARTx) == SET) ;
-
-		while (!__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
-			/* Move a piece of data into the transmit FIFO */
-			if (Chip_UART_Send(UARTx, (uint8_t *) &rb.tx[rb.tx_tail], 1, NONE_BLOCKING)) {
-				/* Update transmit ring FIFO tail pointer */
-				__BUF_INCR(rb.tx_tail);
-			}
-			else {
-				break;
-			}
-		}
-
-		/* If there is no more data to send, disable the transmit
-		   interrupt - else enable it or keep it enabled */
-		if (__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) {
-			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
-			/* Reset Tx Interrupt state */
-			TxIntStat = RESET;
-		}
-		else {
-			/* Set Tx Interrupt state */
-			TxIntStat = SET;
-			Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
-		}
-	}
-	/*
-	 * Otherwise, re-enables Tx Interrupt
-	 */
-	else {
-		Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
-	}
-
-	return bytes;
-}
-
-/* UART read function for interrupt mode (using ring buffers) */
-uint32_t Chip_UART_Interrupt_Receive(LPC_USART_Type *UARTx, uint8_t *rxbuf, uint8_t buflen)
-{
-	uint8_t *data = (uint8_t *) rxbuf;
-	uint32_t bytes = 0;
-
-	/* Temporarily lock out UART receive interrupts during this
-	   read so the UART receive interrupt won't cause problems
-	   with the index values */
-	Chip_UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
-
-	/* Loop until receive buffer ring is empty or
-	    until max_bytes expires */
-	while ((buflen > 0) && (!(__BUF_IS_EMPTY(rb.rx_head, rb.rx_tail)))) {
-		/* Read data from ring buffer into user buffer */
-		*data = rb.rx[rb.rx_tail];
-		data++;
-
-		/* Update tail pointer */
-		__BUF_INCR(rb.rx_tail);
-
-		/* Increment data count and decrement buffer size count */
-		bytes++;
-		buflen--;
-	}
-
-	/* Re-enable UART interrupts */
-	Chip_UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
-
-	return bytes;
-}
-
-/* Reset Tx and Rx ring buffer (head and tail) */
-void Chip_UART_InitRingBuffer(void)
-{
-	TxIntStat = RESET;
-
-	/* Reset ring buf head and tail idx */
-	__BUF_RESET(rb.rx_head);
-	__BUF_RESET(rb.rx_tail);
-	__BUF_RESET(rb.tx_head);
-	__BUF_RESET(rb.tx_tail);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h
deleted file mode 100644
index 418f063fc6..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * @brief LPC18xx/43xx UART chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __UART_18XX_43XX_H_
-#define __UART_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup 18XX_43XX CHIP: LPC18xx/43xx UART Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief	Configure data width, parity mode and stop bits
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	Databits	: UART Data width, should be:
- *                          UART_DATABIT_5: UART 5 bit data mode
- *                          UART_DATABIT_6: UART 6 bit data mode
- *                          UART_DATABIT_7: UART 7 bit data mode
- *                          UART_DATABIT_8: UART 8 bit data mode
- * @param	Parity		: UART Parity mode, should be:
- *                          UART_PARITY_NONE: No parity
- *                          UART_PARITY_ODD:  Odd parity
- *                          UART_PARITY_EVEN: Even parity
- *                          UART_PARITY_SP_1: Forced "1" stick parity
- *                          UART_PARITY_SP_0: Forced "0" stick parity
- * @param	Stopbits	: Number of stop bits, should be:
- *                          UART_STOPBIT_1: One Stop Bit Select
- *                          UART_STOPBIT_2: Two Stop Bits Select
- * @return	Nothing
- */
-STATIC INLINE void Chip_UART_ConfigData(LPC_USART_Type *UARTx,
-										UART_DATABIT_Type Databits,
-										UART_PARITY_Type Parity,
-										UART_STOPBIT_Type Stopbits)
-{
-	IP_UART_ConfigData(UARTx, Databits, Parity, Stopbits);
-}
-
-/**
- * @brief	Send a block of data via UART peripheral
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	txbuf		: Pointer to Transmit buffer
- * @param	buflen		: Length of Transmit buffer
- * @param   flag		: Flag used in  UART transfer, should be NONE_BLOCKING or BLOCKING
- * @return	Number of bytes sent
- */
-STATIC INLINE uint32_t Chip_UART_Send(LPC_USART_Type *UARTx, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
-{
-	return IP_UART_Send(UARTx, txbuf, buflen, flag);
-}
-
-/**
- * @brief	Receive a block of data via UART peripheral
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	rxbuf		: Pointer to Received buffer
- * @param	buflen		: Length of Received buffer
- * @param   flag		: Flag mode, should be NONE_BLOCKING or BLOCKING
- * @return	Number of bytes received
- */
-STATIC INLINE uint32_t Chip_UART_Receive(LPC_USART_Type *UARTx,
-										 uint8_t *rxbuf,
-										 uint32_t buflen,
-										 TRANSFER_BLOCK_Type flag)
-{
-	return IP_UART_Receive(UARTx, rxbuf, buflen, flag);
-}
-
-/* UART FIFO functions ----------------------------------------------------------*/
-/**
- * @brief	Configure FIFO function on selected UART peripheral
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	FIFOCfg		: Pointer to a UART_FIFO_CFG_Type Structure that contains specified information about FIFO configuration
- * @return	Nothing
- */
-STATIC INLINE void Chip_UART_FIFOConfig(LPC_USART_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
-{
-	IP_UART_FIFOConfig(UARTx, FIFOCfg);
-}
-
-/**
- * @brief	Fills each UART_FIFOInitStruct member with its default value:
- *			- FIFO_DMAMode = DISABLE
- *			- FIFO_Level = UART_FIFO_TRGLEV0
- *			- FIFO_ResetRxBuf = ENABLE
- *			- FIFO_ResetTxBuf = ENABLE
- *			- FIFO_State = ENABLE
- * @param	UART_FIFOInitStruct	: Pointer to a UART_FIFO_CFG_Type structure which will be initialized.
- * @return	Nothing
- */
-STATIC INLINE void Chip_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
-{
-	IP_UART_FIFOConfigStructInit(UART_FIFOInitStruct);
-}
-
-/* UART operate functions -------------------------------------------------------*/
-/**
- * @brief	Enable or disable specified UART interrupt.
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	UARTIntCfg	: Specifies the interrupt flag, should be one of the following:
- *                  - UART_INTCFG_RBR   : RBR Interrupt enable
- *                  - UART_INTCFG_THRE  : THR Interrupt enable
- *                  - UART_INTCFG_RLS   : RX line status interrupt enable
- *                  - UART1_INTCFG_MS	: Modem status interrupt enable (UART1 only)
- *                  - UART1_INTCFG_CTS	: CTS1 signal transition interrupt enable (UART1 only)
- *                  - UART_INTCFG_ABEO  : Enables the end of auto-baud interrupt
- *                  - UART_INTCFG_ABTO  : Enables the auto-baud time-out interrupt
- * @param	NewState	: New state of specified UART interrupt type, should be ENALBE or DISALBE
- * @return	Nothing
- */
-STATIC INLINE void Chip_UART_IntConfig(LPC_USART_Type *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
-{
-	IP_UART_IntConfig(UARTx, UARTIntCfg, NewState);
-}
-
-/**
- * @brief	Get Source Interrupt
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Return the value of IIR register
- */
-STATIC INLINE uint32_t Chip_UART_IntGetStatus(LPC_USART_Type *UARTx)
-{
-	return IP_UART_IntGetStatus(UARTx);
-}
-
-/**
- * @brief	Get current value of Line Status register in UART peripheral.
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Current value of Line Status register in UART peripheral
- */
-STATIC INLINE uint8_t Chip_UART_GetLineStatus(LPC_USART_Type *UARTx)
-{
-	return IP_UART_GetLineStatus(UARTx);
-}
-
-/**
- * @brief	Check whether if UART is busy or not
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	RESET if UART is not busy, otherwise return SET.
- */
-STATIC INLINE FlagStatus Chip_UART_CheckBusy(LPC_USART_Type *UARTx)
-{
-	return IP_UART_CheckBusy(UARTx);
-}
-
-/**
- * @brief	Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Nothing
- */
-STATIC INLINE void Chip_UART_ForceBreak(LPC_USART_Type *UARTx)
-{
-	IP_UART_ForceBreak(UARTx);
-}
-
-/**
- * @brief	Transmit a single data through UART peripheral
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	Data		: Data to transmit (must be 8-bit long)
- * @return	Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)
- */
-STATIC INLINE Status Chip_UART_SendByte(LPC_USART_Type *UARTx, uint8_t Data)
-{
-	return IP_UART_SendByte(UARTx, Data);
-}
-
-/**
- * @brief	Receive a single data from UART peripheral
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	*Data		: Pointer to Data to receive (must be 8-bit long)
- * @return	Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)
- */
-STATIC INLINE Status Chip_UART_ReceiveByte(LPC_USART_Type *UARTx, uint8_t *Data)
-{
-	return IP_UART_ReceiveByte(UARTx, Data);
-}
-
-/**
- * @brief	Initializes the UARTx peripheral.
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Nothing
- */
-void Chip_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief	De-initializes the UARTx peripheral.
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Nothing
- */
-void Chip_UART_DeInit(LPC_USART_Type *UARTx);
-
-/**
- * @brief	Determines best dividers to get a target baud rate
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	baudrate	: Desired UART baud rate.
- * @return	Error status, could be SUCCESS or ERROR
- */
-Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate);
-
-/**
- * @brief	Enable/Disable transmission on UART TxD pin
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @param	NewState	: New State of Tx transmission function, should be ENABLE or DISABLE
- * @return Nothing
- */
-void Chip_UART_TxCmd(LPC_USART_Type *UARTx, FunctionalState NewState);
-
-/**
- * @brief	Get Interrupt Stream Status
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Return the interrupt status, should be:
- *              - UART_ERROR
- *              - READY_TO_RECEIVE
- *              - READY_TO_SEND
- */
-UART_Int_Status Chip_UART_GetIntStatus(LPC_USART_Type *UARTx);
-
-/**
- * @brief	Uart interrupt service routine (chip layer)
- * @param	UARTx		: Pointer to selected UARTx peripheral
- * @return	Nothing
- */
-void Chip_UART_Interrupt_Handler (LPC_USART_Type *UARTx);
-
-/**
- * @brief	UART transmit function for interrupt mode (using ring buffers)
- * @param	UARTx	: Selected UART peripheral used to send data, should be UART0
- * @param	txbuf	: Pointer to Transmit buffer
- * @param	buflen	: Length of Transmit buffer
- * @return	Number of bytes actually sent to the ring buffer
- */
-uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_Type *UARTx, uint8_t *txbuf, uint8_t buflen);
-
-/**
- * @brief	UART read function for interrupt mode (using ring buffers)
- * @param	UARTx	: Selected UART peripheral used to send data, should be UART0
- * @param	rxbuf	: Pointer to Received buffer
- * @param	buflen	: Length of Received buffer
- * @return	Number of bytes actually read from the ring buffer
- */
-uint32_t Chip_UART_Interrupt_Receive(LPC_USART_Type *UARTx, uint8_t *rxbuf, uint8_t buflen);
-
-/**
- * @brief	Reset Tx and Rx ring buffer (head and tail)
- * @return	Nothing
- */
-void Chip_UART_InitRingBuffer(void);
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-#endif /* __UART_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c
deleted file mode 100644
index 82b6b024f9..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * @brief LPC18xx/43xx WWDT chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "wwdt_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the Watchdog timer */
-void Chip_WWDT_Init(void)
-{
-	/* Disable watchdog */
-	LPC_WWDT->MOD       = 0;
-	LPC_WWDT->TC        = 0xFF;
-	LPC_WWDT->WARNINT   = 0xFFFF;
-	LPC_WWDT->WINDOW    = 0xFFFFFF;
-}
-
-/* Clear WWDT interrupt status flags */
-void Chip_WWDT_ClearStatusFlag(uint32_t status)
-{
-	if (status & WWDT_WDMOD_WDTOF) {
-		LPC_WWDT->MOD &= ~WWDT_WDMOD_WDTOF;
-	}
-
-	if (status & WWDT_WDMOD_WDINT) {
-		LPC_WWDT->MOD |= WWDT_WDMOD_WDINT;
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h
deleted file mode 100644
index b0818f173e..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * @brief LPC18xx/43xx WWDT chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __WWDT_18XX_43XX_H_
-#define __WWDT_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx WWDT driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** WDT oscillator frequency value */
-#define WDT_OSC     (CGU_IRC_FREQ)
-
-/** WWDT interrupt enable bit */
-#define WWDT_WDMOD_WDEN             ((uint32_t) (1 << 0))
-/** WWDT interrupt enable bit */
-#define WWDT_WDMOD_WDRESET          ((uint32_t) (1 << 1))
-/** WWDT time out flag bit */
-#define WWDT_WDMOD_WDTOF            ((uint32_t) (1 << 2))
-/** WDT Time Out flag bit */
-#define WWDT_WDMOD_WDINT            ((uint32_t) (1 << 3))
-/** WWDT Protect flag bit */
-#define WWDT_WDMOD_WDPROTECT        ((uint32_t) (1 << 4))
-
-/** Minimum tick count for timer value and window value */
-#define WWDT_TICKS_MIN 0xFF
-
-/** Maximum tick count for timer value and window value */
-#define WWDT_TICKS_MAX 0xFFFFFF
-
-/**
- * @brief	Initialize the Watchdog timer
- * @return	None
- */
-void Chip_WWDT_Init(void);
-
-/**
- * @brief	Set WDT timeout constant value used for feed
- * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
- * @return	none
- */
-STATIC INLINE void Chip_WWDT_SetTimeOut(uint32_t timeout)
-{
-	LPC_WWDT->TC = timeout;
-}
-
-/**
- * @brief	Feed watchdog timer
- * @return	None
- * If this function isn't called, a watchdog timer warning will occur.
- * After the warning, a timeout will occur if a feed has happened.
- */
-STATIC INLINE void Chip_WWDT_Feed(void)
-{
-	LPC_WWDT->FEED = 0xAA;
-	LPC_WWDT->FEED = 0x55;
-}
-
-/**
- * @brief	Set WWDT warning interrupt
- * @param	timeout	: WDT warning in ticks, between 0 and 1023
- * @return	None
- * This is the number of ticks after the watchdog interrupt that the
- * warning interrupt will be generated.
- */
-STATIC INLINE void Chip_WWDT_SetWarning(uint32_t timeout)
-{
-	LPC_WWDT->WARNINT = timeout;
-}
-
-/**
- * @brief	Set WWDT window time
- * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
- * @return	none
- * The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
- * function and this function, with this function defining the last tick before the
- * watchdog window interrupt occurs.
- */
-STATIC INLINE void Chip_WWDT_SetWindow(uint32_t timeout)
-{
-	LPC_WWDT->WINDOW = timeout;
-}
-
-/**
- * @brief	Enable watchdog timer options
- * @param	options : An or'ed set of options of values
- *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
- * @return	None
- * You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
- * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
- * are set (or unset) with no other options.
- */
-STATIC INLINE void Chip_WWDT_SetOption(uint32_t options)
-{
-	LPC_WWDT->MOD |= options;
-}
-
-/**
- * @brief	Disable/clear watchdog timer options
- * @param	options : An or'ed set of options of values
- *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
- * @return	None
- * You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
- * WWDT_WDMOD_WDTOF).
- */
-STATIC INLINE void Chip_WWDT_UnsetOption(uint32_t options)
-{
-	LPC_WWDT->MOD &= ~options;
-}
-
-/**
- * @brief	Enable WWDT activity
- * @return	None
- */
-STATIC INLINE void Chip_WWDT_Start(void)
-{
-	Chip_WWDT_SetOption(WWDT_WDMOD_WDEN);
-	Chip_WWDT_Feed();
-}
-
-/**
- * @brief	Read WWDT status flag
- * @return	Watchdog status, an Or'ed value of WWDT_WDMOD_*
- */
-STATIC INLINE uint32_t Chip_WWDT_GetStatus(void)
-{
-	return LPC_WWDT->MOD;
-}
-
-/**
- * @brief	Clear WWDT interrupt status flags
- * @param	flag	: Or'ed value of status flag(s) that you want to clear, should be:
- *              - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
- *              - WWDT_WDMOD_WDINT: Clear watchdog warning flag
- * @return	None
- */
-void Chip_WWDT_ClearStatusFlag(uint32_t status);
-
-/**
- * @brief	Get the current value of WDT
- * @return	current value of WDT
- */
-STATIC INLINE uint32_t WWDT_GetCurrentCount(void)
-{
-	return LPC_WWDT->TV;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __WWDT_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c b/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c
deleted file mode 100644
index 07c4ec05b3..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * @brief    Generic memory tests
- *           Various memory tests for testing external memory integrity. Includes
- *           inverse address, walking bit, and pattern tests.
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "mem_tests.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Walking 0 memory test */
-bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup)
-{
-	int i = 0;
-	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
-
-	/* Must be 32-bit algined */
-	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
-		return false;
-	}
-
-	/* Write walking 0 pattern */
-	while (fbytes > 0) {
-		*addr = ~(1 << i);
-
-		addr++;
-		fbytes -= 4;
-		i++;
-		if (i >= 32) {
-			i = 0;
-		}
-	}
-
-	/* Verify walking 0 pattern */
-	i = 0;
-	fbytes = pMemSetup->bytes;
-	addr = pMemSetup->start_addr;
-	while (fbytes > 0) {
-		if (*addr != ~(1 << i)) {
-			pMemSetup->fail_addr = addr;
-			pMemSetup->is_val = *addr;
-			pMemSetup->ex_val = ~(1 << i);
-			return false;
-		}
-
-		addr++;
-		fbytes -= 4;
-		i++;
-		if (i >= 32) {
-			i = 0;
-		}
-	}
-
-	return true;
-}
-
-/* Walking 1 memory test */
-bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup)
-{
-	int i = 0;
-	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
-
-	/* Must be 32-bit algined */
-	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
-		return false;
-	}
-
-	/* Write walking 1 pattern */
-	while (fbytes > 0) {
-		*addr = (1 << i);
-
-		addr++;
-		fbytes -= 4;
-		i++;
-		if (i >= 32) {
-			i = 0;
-		}
-	}
-
-	/* Verify walking 1 pattern */
-	i = 0;
-	fbytes = pMemSetup->bytes;
-	addr = pMemSetup->start_addr;
-	while (fbytes > 0) {
-		if (*addr != (1 << i)) {
-			pMemSetup->fail_addr = addr;
-			pMemSetup->is_val = *addr;
-			pMemSetup->ex_val = (1 << i);
-			return false;
-		}
-
-		addr++;
-		fbytes -= 4;
-		i++;
-		if (i >= 32) {
-			i = 0;
-		}
-	}
-
-	return true;
-}
-
-/* Address memory test */
-bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup)
-{
-	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
-
-	/* Must be 32-bit algined */
-	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
-		return false;
-	}
-
-	/* Write address for memory location */
-	while (fbytes > 0) {
-		*addr =  (uint32_t) addr;
-
-		addr++;
-		fbytes -= 4;
-	}
-
-	/* Verify address for memory location */
-	fbytes = pMemSetup->bytes;
-	addr = pMemSetup->start_addr;
-	while (fbytes > 0) {
-		if (*addr != (uint32_t) addr) {
-			pMemSetup->fail_addr = addr;
-			pMemSetup->is_val = *addr;
-			pMemSetup->ex_val = (uint32_t) addr;
-			return false;
-		}
-
-		addr++;
-		fbytes -= 4;
-	}
-
-	return true;
-}
-
-/* Inverse address memory test */
-bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup)
-{
-	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
-
-	/* Must be 32-bit algined */
-	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
-		return false;
-	}
-
-	/* Write inverse address for memory location */
-	while (fbytes > 0) {
-		*addr =  ~(uint32_t) addr;
-
-		addr++;
-		fbytes -= 4;
-	}
-
-	/* Verify inverse address for memory location */
-	fbytes = pMemSetup->bytes;
-	addr = pMemSetup->start_addr;
-	while (fbytes > 0) {
-		if (*addr != ~(uint32_t) addr) {
-			pMemSetup->fail_addr = addr;
-			pMemSetup->is_val = *addr;
-			pMemSetup->ex_val = ~(uint32_t) addr;
-			return false;
-		}
-
-		addr++;
-		fbytes -= 4;
-	}
-
-	return true;
-}
-
-/* Pattern memory test */
-bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup)
-{
-	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
-	uint32_t pattern = 0x55AA55AA;
-
-	/* Must be 32-bit algined */
-	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
-		return false;
-	}
-
-	/* Write pattern for memory location */
-	while (fbytes > 0) {
-		*addr =  pattern;
-
-		pattern = ~pattern;
-		addr++;
-		fbytes -= 4;
-	}
-
-	/* Verify pattern for memory location */
-	pattern = 0x55AA55AA;
-	fbytes = pMemSetup->bytes;
-	addr = pMemSetup->start_addr;
-	while (fbytes > 0) {
-		if (*addr != pattern) {
-			pMemSetup->fail_addr = addr;
-			pMemSetup->is_val = *addr;
-			pMemSetup->ex_val = pattern;
-			return false;
-		}
-
-		pattern = ~pattern;
-		addr++;
-		fbytes -= 4;
-	}
-
-	return true;
-}
-
-/* Pattern memory test with seed and increment value */
-bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr)
-{
-	uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr;
-	uint32_t pattern = seed;
-
-	/* Must be 32-bit algined */
-	if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) {
-		return false;
-	}
-
-	/* Write pattern for memory location */
-	while (fbytes > 0) {
-		*addr =  pattern;
-
-		pattern += incr;
-		addr++;
-		fbytes -= 4;
-	}
-
-	/* Verify pattern for memory location */
-	pattern = seed;
-	fbytes = pMemSetup->bytes;
-	addr = pMemSetup->start_addr;
-	while (fbytes > 0) {
-		if (*addr != pattern) {
-			pMemSetup->fail_addr = addr;
-			pMemSetup->is_val = *addr;
-			pMemSetup->ex_val = pattern;
-			return false;
-		}
-
-		pattern += incr;
-		addr++;
-		fbytes -= 4;
-	}
-
-	return true;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h b/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h
deleted file mode 100644
index 556f305a47..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * @brief    Generic memory tests
- *           Various memory tests for testing external memory integrity. Includes
- *           inverse address, walking bit, and pattern tests.
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __MEM_TESTS_H_
-#define __MEM_TESTS_H_
-
-#include "lpc_types.h"
-
-/** @defgroup CHIP_Memory_Tests CHIP: Various RAM memory tests
- * @ingroup CHIP_Common
- * @{
- */
-
-/**
- * @brief Memory test address/size and result structure
- */
-typedef struct {
-	uint32_t *start_addr;	/*!< Starting address for memory test */
-	uint32_t bytes;			/*!< Size in bytes for memory test */
-	uint32_t *fail_addr;	/*!< Failed address of test (returned only if failed) */
-	uint32_t is_val;		/*!< Failed value of test (returned only if failed) */
-	uint32_t ex_val;		/*!< Expected value of test (returned only if failed) */
-} MEM_TEST_SETUP_T;
-
-/**
- * @brief	Walking 0 memory test
- * @param	pMemSetup	: Memory test setup (and returned results)
- * @return	true if the test passed, or false on failure
- * Writes a shifting 0 bit pattern to the entire memory range and
- * verifies the result after all memory locations are written
- */
-bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup);
-
-/**
- * @brief	Walking 1 memory test
- * @param	pMemSetup	: Memory test setup (and returned results)
- * @return	true if the test passed, or false on failure
- * Writes a shifting 1 bit pattern to the entire memory range and
- * verifies the result after all memory locations are written
- */
-bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup);
-
-/**
- * @brief	Address memory test
- * @param	pMemSetup	: Memory test setup (and returned results)
- * @return	true if the test passed, or false on failure
- * Writes the address to each memory location and verifies the
- * result after all memory locations are written
- */
-bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup);
-
-/**
- * @brief	Inverse address memory test
- * @param	pMemSetup	: Memory test setup (and returned results)
- * @return	true if the test passed, or false on failure
- * Writes the inverse address to each memory location and verifies the
- * result after all memory locations are written
- */
-bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup);
-
-/**
- * @brief	Pattern memory test
- * @param	pMemSetup	: Memory test setup (and returned results)
- * @return	true if the test passed, or false on failure
- * Writes the an alternating 0x55/0xAA pattern to each memory location
- * and verifies the result after all memory locations are written
- */
-bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup);
-
-/**
- * @brief	Pattern memory test with seed and increment value
- * @param	pMemSetup	: Memory test setup (and returned results)
- * @param	seed		: Initial seed value for test
- * @param	incr		: Increment value for each memory location
- * @return	true if the test passed, or false on failure
- * Writes the an alternating pattern to each memory location based on a
- * passed seedn and increment value and verifies the result after all
- * memory locations are written
- */
-bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr);
-
-/**
- * @}
- */
-
-#endif /* __MEM_TESTS_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c b/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c
deleted file mode 100644
index 87caf4ac28..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * @brief Common ring buffer support functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "ring_buffer.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize ring buffer */
-void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
-{
-	RingBuff->bufferBase = RingBuff->bufferIn = RingBuff->bufferOut = buffer;
-	RingBuff->bufferLast = RingBuff->bufferBase + (itemSize * count);
-	RingBuff->count = count;
-	RingBuff->itemSize = itemSize;
-	RingBuff->used = 0;
-}
-
-/* Return empty status of ring buffer */
-bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8)
-{
-	bool full = RingBuffer_IsFull(RingBuff);
-
-	if (!full) {
-		*RingBuff->bufferIn = data8;
-		RingBuff->used++;
-		RingBuff->bufferIn++;
-		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
-			RingBuff->bufferIn = RingBuff->bufferBase;
-		}
-	}
-
-	return (bool) !full;
-}
-
-/* Insert 16-bit value in ring buffer */
-bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16)
-{
-	bool full = RingBuffer_IsFull(RingBuff);
-
-	if (!full) {
-		uint16_t *buff16 = (uint16_t *) RingBuff->bufferIn;
-		*buff16 = data16;
-		RingBuff->used++;
-		buff16++;
-		RingBuff->bufferIn = (uint8_t *) buff16;
-		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
-			RingBuff->bufferIn = RingBuff->bufferBase;
-		}
-	}
-
-	return (bool) !full;
-}
-
-/* Insert 32-bit value in ring buffer */
-bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32)
-{
-	bool full = RingBuffer_IsFull(RingBuff);
-
-	if (!full) {
-		uint32_t *buff32 = (uint32_t *) RingBuff->bufferIn;
-		*buff32 = data32;
-		RingBuff->used++;
-		buff32++;
-		RingBuff->bufferIn = (uint8_t *) buff32;
-		if (RingBuff->bufferIn >= RingBuff->bufferLast) {
-			RingBuff->bufferIn = RingBuff->bufferBase;
-		}
-	}
-
-	return (bool) !full;
-}
-
-/* Pop a 8-bit value from the ring buffer */
-bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8)
-{
-	bool empty = RingBuffer_IsEmpty(RingBuff);
-
-	if (!empty) {
-		*data8 = *RingBuff->bufferOut;
-		RingBuff->used--;
-		RingBuff->bufferOut++;
-		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
-			RingBuff->bufferOut = RingBuff->bufferBase;
-		}
-	}
-
-	return (bool) !empty;
-}
-
-/* Pop a 16-bit value from the ring buffer */
-bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16)
-{
-	bool empty = RingBuffer_IsEmpty(RingBuff);
-
-	if (!empty) {
-		uint16_t *buff16 = (uint16_t *) RingBuff->bufferOut;
-		*data16 = *buff16;
-		RingBuff->used--;
-		buff16++;
-		RingBuff->bufferOut = (uint8_t *) buff16;
-		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
-			RingBuff->bufferOut = RingBuff->bufferBase;
-		}
-	}
-
-	return (bool) !empty;
-}
-
-/* Pop a 32-bit value from the ring buffer */
-bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32)
-{
-	bool empty = RingBuffer_IsEmpty(RingBuff);
-
-	if (!empty) {
-		uint32_t *buff32 = (uint32_t *) RingBuff->bufferOut;
-		*data32 = *buff32;
-		RingBuff->used--;
-		data32++;
-		RingBuff->bufferOut = (uint8_t *) data32;
-		if (RingBuff->bufferOut >= RingBuff->bufferLast) {
-			RingBuff->bufferOut = RingBuff->bufferBase;
-		}
-	}
-
-	return (bool) !empty;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h b/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h
deleted file mode 100644
index c7badbcce8..0000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * @brief Common ring buffer support functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RING_BUFFER_H_
-#define __RING_BUFFER_H_
-
-#include "lpc_types.h"
-
-/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
- * @ingroup CHIP_Common
- * @{
- */
-
-/**
- * @brief Ring buffer structure
- */
-typedef struct {
-	uint8_t *bufferBase, *bufferLast;
-	uint8_t *bufferIn, *bufferOut;
-	int count, used, itemSize;
-} RINGBUFF_T;
-
-/**
- * @brief	Initialize ring buffer
- * @param	RingBuff	: Pointer to ring buffer to initialize
- * @param	buffer		: Pointer to buffer to associate with RingBuff
- * @param	itemSize	: Size of each buffer item size (1, 2 or 4 bytes)
- * @param	count		: Size of ring buffer
- * @return	Nothing
- */
-void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
-
-/**
- * @brief	Return number of items in the ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @return	Number of items in the ring buffer
- */
-STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
-{
-	return RingBuff->used;
-}
-
-/**
- * @brief	Return number of items in the ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @return	true if the ring buffer is full, otherwise false
- */
-STATIC INLINE bool RingBuffer_IsFull(RINGBUFF_T *RingBuff)
-{
-	return (bool) (RingBuff->used >= RingBuff->count);
-}
-
-/**
- * @brief	Return empty status of ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @return	true if the ring buffer is empty, otherwise false
- */
-STATIC INLINE bool RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
-{
-	return (bool) (RingBuff->used == 0);
-}
-
-/**
- * @brief	Insert 8-bit value in ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @param	data8		: Byte to insert in ring buffer
- * @return	true if a valid byte was inserted, or false if the ring buffer was full
- */
-bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8);
-
-/**
- * @brief	Insert 16-bit value in ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @param	data16		: 16-bit value to insert in ring buffer
- * @return	true if valid data was inserted, or false if the ring buffer was full
- */
-bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16);
-
-/**
- * @brief	Insert 32-bit value in ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @param	data32		: 32-bit value to insert in ring buffer
- * @return	true if valid data was inserted, or false if the ring buffer was full
- */
-bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32);
-
-/**
- * @brief	Pop a 8-bit value from the ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @param	data8		: Pointer to where to place value
- * @return	true if a valid byte was popped, or false if the ring buffer was empty
- */
-bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8);
-
-/**
- * @brief	Pop a 16-bit value from the ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @param	data16		: Pointer to where to place value
- * @return	true if a valid byte was popped, or false if the ring buffer was empty
- */
-bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16);
-
-/**
- * @brief	Pop a 32-bit value from the ring buffer
- * @param	RingBuff	: Pointer to ring buffer
- * @param	data32		: Pointer to where to place value
- * @return	true if a valid byte was popped, or false if the ring buffer was empty
- */
-bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32);
-
-/**
- * @}
- */
-
-#endif /* __RING_BUFFER_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/SConscript b/bsp/xplorer4330/libraries/lpc_ip/SConscript
deleted file mode 100644
index ae57400ecb..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-CPPPATH = [cwd]
-
-group = DefineGroup('lpc_ip', src, depend = [], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/xplorer4330/libraries/lpc_ip/adc_001.c b/bsp/xplorer4330/libraries/lpc_ip/adc_001.c
deleted file mode 100644
index 3e0286057c..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/adc_001.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * @brief ADC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "adc_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Configure clock for ADC */
-static void SetClock(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy)
-{
-	uint32_t temp, adcBitRate;
-
-	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
-	   A/D converter, which should be less than or equal to 4.5MHz.
-	   A fully conversion requires (bits_accuracy+1) of these clocks.
-	   ADC clock = PCLK_ADC0 / (CLKDIV + 1);
-	   ADC rate = ADC clock / (bits_accuracy+1);
-	 */
-	adcBitRate = (adcRate * (11 - bitsAccuracy));
-
-	/* Get the round value by fomular: (2*A + B)/(2*B) */
-	temp = ((adcPerClock * 2 + adcBitRate) / (adcBitRate * 2)) - 1;
-
-	/* Enable PDN bit and clock bits */
-	pADC->CR &= ~(ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07));
-	pADC->CR |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(bitsAccuracy);
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the ADC */
-void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy)
-{
-	pADC->INTEN = 0;		/* Disable all interrupts */
-	pADC->CR |= ADC_CR_PDN;	/* Set PDN bit for ADC*/
-	SetClock(pADC, adcRate, adcPerClock, bitsAccuracy);
-}
-
-/* Shutdown ADC */
-void IP_ADC_DeInit(IP_ADC_001_Type *pADC)
-{
-	pADC->INTEN = 0x00000100;
-	pADC->CR = 0;
-}
-
-/* Set burst mode for ADC */
-void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState)
-{
-	if (NewState == DISABLE) {
-		pADC->CR &= ~ADC_CR_BURST;
-	}
-	else {
-		pADC->CR |= ADC_CR_BURST;
-	}
-}
-
-/* Get the ADC value */
-Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data)
-{
-	uint32_t temp;
-	temp = pADC->DR[channel];
-	if (!ADC_DR_DONE(temp)) {
-		return ERROR;
-	}
-	//	if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST))
-	//	return ERROR;
-	*data = (uint16_t) ADC_DR_RESULT(temp);
-	return SUCCESS;
-}
-
-/* Get ADC Channel status from ADC data register */
-FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType)
-{
-	switch (StatusType) {
-	case ADC_DR_DONE_STAT:
-		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
-
-	case ADC_DR_OVERRUN_STAT:
-		channel += 8;
-		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
-
-	case ADC_DR_ADINT_STAT:
-		return pADC->STAT >> 16 ? SET : RESET;
-
-	default:
-		break;
-	}
-	return RESET;
-}
-
-/* Set the edge start condition */
-void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode)
-{
-	if (edge_mode) {
-		pADC->CR |= ADC_CR_EDGE;
-	}
-	else {
-		pADC->CR &= ~ADC_CR_EDGE;
-	}
-}
-
-/* Enable/Disable ADC channel number */
-void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pADC->CR |= ADC_CR_CH_SEL(channel);
-	}
-	else {
-		pADC->CR &= ~ADC_CR_START_MASK;
-		pADC->CR &= ~ADC_CR_CH_SEL(channel);
-	}
-}
-
-/* Set start mode for ADC */
-void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode)
-{
-	pADC->CR &= ~ADC_CR_START_MASK;
-	pADC->CR |= ADC_CR_START_MODE_SEL((uint32_t) start_mode);
-}
-
-/* Enable/Disable interrupt for ADC channel */
-void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pADC->INTEN |= (1UL << channel);
-	}
-	else {
-		pADC->INTEN &= (~(1UL << channel));
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/adc_001.h b/bsp/xplorer4330/libraries/lpc_ip/adc_001.h
deleted file mode 100644
index 7f86e72bb5..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/adc_001.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * @brief ADC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ADC_001_H_
-#define __ADC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief 10 or 12-bit ADC register block structure
- */
-typedef struct {					/*!< ADCn Structure */
-	__IO uint32_t CR;				/*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
-	__I  uint32_t GDR;				/*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
-	__I  uint32_t RESERVED0;
-	__IO uint32_t INTEN;			/*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
-	__I  uint32_t DR[8];			/*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
-	__I  uint32_t STAT;				/*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-#if !defined(CHIP_LPC18XX) && !defined(CHIP_LPC43XX)
-	__IO uint32_t ADTRM;
-#endif
-} IP_ADC_001_Type;
-
-/**
- * @brief ADC register support bitfields and mask
- */
-#define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF))	/*!< Mask for getting the ADC data read value */
-#define ADC_DR_DONE(n)          (((n) >> 31))			/*!< Mask for reading the ADC done status */
-#define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL)))	/*!< Mask for reading the ADC overrun status */
-#define ADC_CR_CH_SEL(n)        ((1UL << (n)))			/*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
-#define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))	/*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
-#define ADC_CR_BURST            ((1UL << 16))			/*!< Repeated conversions A/D enable bit */
-#define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))	/*!< Number of ADC accuracy bits */
-#define ADC_CR_PDN              ((1UL << 21))			/*!< ADC convert in power down mode */
-#define ADC_CR_START_MASK       ((7UL << 24))			/*!< ADC start mask bits */
-#define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))		/*!< Select Start Mode */
-#define ADC_CR_START_NOW        ((1UL << 24))			/*!< Start conversion now */
-#define ADC_CR_START_CTOUT15    ((2UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
-#define ADC_CR_START_CTOUT8     ((3UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
-#define ADC_CR_START_ADCTRIG0   ((4UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
-#define ADC_CR_START_ADCTRIG1   ((5UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
-#define ADC_CR_START_MCOA2      ((6UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-#define ADC_CR_EDGE             ((1UL << 27))			/*!< Start conversion on a falling edge on the selected CAP/MAT signal */
-
-/**
- * @brief	ADC status register used for IP drivers
- */
-typedef enum {
-	ADC_DR_DONE_STAT,	/*!< ADC data register staus */
-	ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
-	ADC_DR_ADINT_STAT	/*!< ADC interrupt status */
-} IP_ADC_Status;
-
-/**
- * @brief	Initialize for ADC
- * @param	pADC			: The base of ADC peripheral on the chip
- * @param	adcRate			: Sample rate of A/D converter
- * @param	adcPerClock		: The APB clock
- * @param	bitsAccuracy	: The accuracy of LSB value, should be ADC_10BITS -> ADC_3BITS
- * @return	 Nothing
- * Disable all ADC interrupts, set bit PDN, set ADC clock frequency
- * This is not the sample rate, but the clock for the ADC machine, and is usually set to
- * maximum. Applications may choose a lower frequency if they have high-impedance sources.
- * This is because a lower clock frequency produces a longer sampling time.
- */
-void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy);
-
-/**
- * @brief	Shutdown ADC
- * @param	pADC	: The base of ADC peripheral on the chip
- * @return	Nothing
- * Reset the ADC control and INTEN Register to reset values (disabled)
- */
-void IP_ADC_DeInit(IP_ADC_001_Type *pADC);
-
-/**
- * @brief	Set burst mode for ADC
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	NewState	: ENABLE for burst mode, or DISABLE for normal mode
- * @return	Nothing
- */
-void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState);
-
-/**
- * @brief	Get the ADC value
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: Channel to be read value, should be 0..7
- * @param	data		: Data buffer to store the A/D value
- * @return	Status		: SUCCESS or ERROR
- */
-Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data);
-
-/**
- * @brief	Get ADC Channel status from ADC data register
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: Channel number, should be 0..7
- * @param	StatusType	: Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT
- * @return	Channel status, SET or RESET
- */
-FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType);
-
-/**
- * @brief	Set the edge start condition
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	edge_mode	: 0 = rising, != = falling
- * @return	Nothing
- */
-void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode);
-
-/**
- * @brief	Enable/Disable ADC channel number
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: Channel number
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	Nothing
- */
-void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
-
-/**
- * @brief	Set start mode for ADC
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	start_mode	: Start mode choose one of modes in 'ADC_START_*' enumeration type definitions
- * @return	Nothing
- */
-void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode);
-
-/**
- * @brief	Enable/Disable interrupt for ADC channel
- * @param	pADC		: The base of ADC peripheral on the chip
- * @param	channel		: Channel assert the interrupt
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	Nothing
- */
-void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ADC_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/atimer_001.c b/bsp/xplorer4330/libraries/lpc_ip/atimer_001.c
deleted file mode 100644
index ae0110f47b..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/atimer_001.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * @brief Alarm Timer Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "atimer_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Close ATIMER device */
-void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer)
-{
-	IP_ATIMER_ClearIntStatus(pATimer);
-	IP_ATIMER_IntDisable(pATimer);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/atimer_001.h b/bsp/xplorer4330/libraries/lpc_ip/atimer_001.h
deleted file mode 100644
index 6ec23976da..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/atimer_001.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * @brief Alarm Timer Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ATIMER_001_H_
-#define __ATIMER_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ATIMER_001 IP: ATimer register block and driver
- * @ingroup IP_Drivers
- * Alarm timer
- * @{
- */
-
-/**
- * @brief Alarm Timer register block structure
- */
-typedef struct {					/*!< ATIMER Structure       */
-	__IO uint32_t DOWNCOUNTER;		/*!< Downcounter register   */
-	__IO uint32_t PRESET;			/*!< Preset value register  */
-	__I  uint32_t RESERVED0[1012];
-	__O  uint32_t CLR_EN;			/*!< Interrupt clear enable register */
-	__O  uint32_t SET_EN;			/*!< Interrupt set enable register */
-	__I  uint32_t STATUS;			/*!< Status register        */
-	__I  uint32_t ENABLE;			/*!< Enable register        */
-	__O  uint32_t CLR_STAT;			/*!< Clear register         */
-	__O  uint32_t SET_STAT;			/*!< Set register           */
-} IP_ATIMER_001_Type;
-
-/**
- * @brief	Close ATIMER device
- * @param	pATimer	:  Pointer to timer device
- * @return	None
- * Important: 32KHz clock must be enabled in CREG prior to this call. See
- * the User Manual for more information.
- */
-void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer);
-
-/**
- * @brief	Clear ATIMER Interrupt Status
- * @param	pATimer	: Pointer to timer device
- * @return	None
- */
-STATIC INLINE void IP_ATIMER_ClearIntStatus(IP_ATIMER_001_Type *pATimer)
-{
-	pATimer->CLR_STAT = 1;
-}
-
-/**
- * @brief	Set ATIMER Interrupt Status
- * @param	pATimer	: Pointer to timer device
- * @return	None
- */
-STATIC INLINE void IP_ATIMER_SetIntStatus(IP_ATIMER_001_Type *pATimer)
-{
-	pATimer->SET_STAT = 1;
-}
-/**
- * @brief	Enable ATIMER Interrupt
- * @param	pATimer	: Pointer to timer device
- * @return	None
- */
-STATIC INLINE void IP_ATIMER_IntEnable(IP_ATIMER_001_Type *pATimer)
-{
-	pATimer->SET_EN = 1;
-}
-
-/**
- * @brief	Disable ATIMER Interrupt
- * @param	pATimer	: Pointer to timer device
- * @return	None
- */
-STATIC INLINE void IP_ATIMER_IntDisable(IP_ATIMER_001_Type *pATimer)
-{
-	pATimer->CLR_EN = 1;
-}
-
-/**
- * @brief	Update Preset value
- * @param	pATimer	: Pointer to timer device
- * @param	PresetValue	updated preset value
- * @return	Nothing
- */
-STATIC INLINE void IP_ATIMER_UpdatePresetValue(IP_ATIMER_001_Type *pATimer, uint32_t PresetValue)
-{
-	pATimer->PRESET = PresetValue;
-}
-
-/**
- * @brief	Read value of preset register
- * @param	pATimer	: Pointer to timer/counter device
- * @return	Value of capture register
- */
-STATIC INLINE uint32_t IP_ATIMER_GetPresetValue(IP_ATIMER_001_Type *pATimer)
-{
-	return pATimer->PRESET;
-}
-
-/**
- * @brief	Returns enable state of ATimer interrupt
- * @param	pATimer	: Pointer to timer/counter device
- * @return	!0 if the ATimer interrupt is enabled, otherwise 0
- */
-STATIC INLINE uint32_t IP_ATIMER_GetIntEnableState(IP_ATIMER_001_Type *pATimer)
-{
-	return pATimer->ENABLE;
-}
-
-/**
- * @brief	Returns current pending state of ATimer interrupt
- * @param	pATimer	: Pointer to timer/counter device
- * @return	!0 if the ATimer interrupt is asserted, otherwise 0
- */
-STATIC INLINE uint32_t IP_ATIMER_GetIntPendingState(IP_ATIMER_001_Type *pATimer)
-{
-	return pATimer->STATUS;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ATIMER_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/ccan_001.h b/bsp/xplorer4330/libraries/lpc_ip/ccan_001.h
deleted file mode 100644
index 18baad03b7..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/ccan_001.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * @brief CCAN registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CCAN_001_H_
-#define __CCAN_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_CCAN_001 IP: CCAN register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief CCAN Controller Area Network register block structure
- */
-typedef struct {						/*!< C_CAN Structure       */
-	__IO uint32_t CNTL;					/*!< CAN control            */
-	__IO uint32_t STAT;					/*!< Status register        */
-	__I  uint32_t EC;					/*!< Error counter          */
-	__IO uint32_t BT;					/*!< Bit timing register    */
-	__I  uint32_t INT;					/*!< Interrupt register     */
-	__IO uint32_t TEST;					/*!< Test register          */
-	__IO uint32_t BRPE;					/*!< Baud rate prescaler extension register */
-	__I  uint32_t  RESERVED0;
-	__IO uint32_t IF1_CMDREQ;			/*!< Message interface command request  */
-	union {
-		__IO uint32_t IF1_CMDMSK_R;		/*!< Message interface command mask (read direction) */
-		__IO uint32_t IF1_CMDMSK_W;		/*!< Message interface command mask (write direction) */
-	};
-
-	__IO uint32_t IF1_MSK1;				/*!< Message interface mask 1 */
-	__IO uint32_t IF1_MSK2;				/*!< Message interface 1 mask 2 */
-	__IO uint32_t IF1_ARB1;				/*!< Message interface 1 arbitration 1 */
-	__IO uint32_t IF1_ARB2;				/*!< Message interface 1 arbitration 2 */
-	__IO uint32_t IF1_MCTRL;			/*!< Message interface 1 message control */
-	__IO uint32_t IF1_DA1;				/*!< Message interface data A1 */
-	__IO uint32_t IF1_DA2;				/*!< Message interface 1 data A2 */
-	__IO uint32_t IF1_DB1;				/*!< Message interface 1 data B1 */
-	__IO uint32_t IF1_DB2;				/*!< Message interface 1 data B2 */
-	__I  uint32_t  RESERVED1[13];
-	__IO uint32_t IF2_CMDREQ;			/*!< Message interface command request  */
-	union {
-		__IO uint32_t IF2_CMDMSK_R;		/*!< Message interface command mask (read direction) */
-		__IO uint32_t IF2_CMDMSK_W;		/*!< Message interface command mask (write direction) */
-	};
-
-	__IO uint32_t IF2_MSK1;				/*!< Message interface mask 1 */
-	__IO uint32_t IF2_MSK2;				/*!< Message interface 1 mask 2 */
-	__IO uint32_t IF2_ARB1;				/*!< Message interface 1 arbitration 1 */
-	__IO uint32_t IF2_ARB2;				/*!< Message interface 1 arbitration 2 */
-	__IO uint32_t IF2_MCTRL;			/*!< Message interface 1 message control */
-	__IO uint32_t IF2_DA1;				/*!< Message interface data A1 */
-	__IO uint32_t IF2_DA2;				/*!< Message interface 1 data A2 */
-	__IO uint32_t IF2_DB1;				/*!< Message interface 1 data B1 */
-	__IO uint32_t IF2_DB2;				/*!< Message interface 1 data B2 */
-	__I  uint32_t  RESERVED2[21];
-	__I  uint32_t TXREQ1;				/*!< Transmission request 1 */
-	__I  uint32_t TXREQ2;				/*!< Transmission request 2 */
-	__I  uint32_t  RESERVED3[6];
-	__I  uint32_t ND1;					/*!< New data 1             */
-	__I  uint32_t ND2;					/*!< New data 2             */
-	__I  uint32_t  RESERVED4[6];
-	__I  uint32_t IR1;					/*!< Interrupt pending 1    */
-	__I  uint32_t IR2;					/*!< Interrupt pending 2    */
-	__I  uint32_t  RESERVED5[6];
-	__I  uint32_t MSGV1;				/*!< Message valid 1        */
-	__I  uint32_t MSGV2;				/*!< Message valid 2        */
-	__I  uint32_t  RESERVED6[6];
-	__IO uint32_t CLKDIV;				/*!< CAN clock divider register */
-} IP_CCAN_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CCAN_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/dac_001.h b/bsp/xplorer4330/libraries/lpc_ip/dac_001.h
deleted file mode 100644
index 9fba82e190..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/dac_001.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * @brief DAC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __DAC_001_H_
-#define __DAC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_DAC_001 IP: DAC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief DAC register block structure
- */
-typedef struct {			/*!< DAC Structure          */
-	__IO uint32_t  CR;		/*!< DAC register. Holds the conversion data. */
-	__IO uint32_t  CTRL;	/*!< DAC control register.  */
-	__IO uint32_t  CNTVAL;	/*!< DAC counter value register. */
-} IP_DAC_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DAC_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/emc_001.c b/bsp/xplorer4330/libraries/lpc_ip/emc_001.c
deleted file mode 100644
index 061544abed..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/emc_001.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * @brief EMC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "emc_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* DIV function with result rounded up */
-#define EMC_DIV_ROUND_UP(x, y)  ((x + y - 1) / y)
-
-#ifndef EMC_SUPPORT_ONLY_PL172
-/* Get ARM External Memory Controller Version */
-static uint32_t EMC_GetARMPeripheralID(IP_EMC_001_Type *pEMC)
-{
-	uint32_t *RegAdd;
-	RegAdd = (uint32_t *) ((uint32_t) pEMC + 0xFE0);
-	return (RegAdd[0] & 0xFF) | ((RegAdd[1] & 0xFF) << 8) |
-		   ((RegAdd[2] & 0xFF) << 16) | (RegAdd[3] << 24);
-}
-
-#endif
-
-/* Calculate Clock Count from Timing Unit(nanoseconds) */
-static uint32_t EMC_TimingParamConvert(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust)
-{
-	uint32_t temp;
-	if (input_ns < 0) {
-		return (-input_ns) >> 8;
-	}
-	temp = EMC_Clock / 1000000;		/* MHz calculation */
-	temp = temp * input_ns / 1000;
-
-	/* round up */
-	temp += 0xFF;
-
-	/* convert to simple integer number format */
-	temp >>= 8;
-	if (temp > adjust) {
-		return temp - adjust;
-	}
-
-	return 0;
-}
-
-/* Get Dynamic Memory Device Colum len */
-static uint32_t EMC_GetColsLen(uint32_t DynConfig)
-{
-	uint32_t DevBusWidth;
-	DevBusWidth = (DynConfig >> EMC_DYN_CONFIG_DEV_BUS_BIT) & 0x03;
-	if (DevBusWidth == 2) {
-		return 8;
-	}
-	else if (DevBusWidth == 1) {
-		return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 8;
-	}
-	else if (DevBusWidth == 0) {
-		return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 9;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the Dynamic Controller according to the specified parameters
-   in the IP_EMC_DYN_CONFIG_Type */
-void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock)
-{
-	uint32_t ChipSelect, tmpclk;
-	int i;
-
-	for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
-		IP_EMC_001_Type *EMC_Reg_add = (IP_EMC_001_Type *) ((uint32_t) pEMC + (ChipSelect << 5));
-
-		EMC_Reg_add->DYNAMICRASCAS0    = Dynamic_Config->DevConfig[ChipSelect].RAS |
-										 ((Dynamic_Config->DevConfig[ChipSelect].ModeRegister <<
-										   (8 - EMC_DYN_MODE_CAS_BIT)) & 0xF00);
-		EMC_Reg_add->DYNAMICCONFIG0    = Dynamic_Config->DevConfig[ChipSelect].DynConfig;
-	}
-	pEMC->DYNAMICREADCONFIG = Dynamic_Config->ReadConfig;	/* Read strategy */
-
-	pEMC->DYNAMICRP         = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRP, 1);
-	pEMC->DYNAMICRAS        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRAS, 1);
-	pEMC->DYNAMICSREX       = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tSREX, 1);
-	pEMC->DYNAMICAPR        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tAPR, 1);
-	pEMC->DYNAMICDAL        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tDAL, 0);
-	pEMC->DYNAMICWR         = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tWR, 1);
-	pEMC->DYNAMICRC         = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRC, 1);
-	pEMC->DYNAMICRFC        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRFC, 1);
-	pEMC->DYNAMICXSR        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tXSR, 1);
-	pEMC->DYNAMICRRD        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRRD, 1);
-	pEMC->DYNAMICMRD        = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tMRD, 1);
-
-	/* TIM_Waitus(100); */
-	/*TODO: if Timer driver is ready, it should replace below "for" delay technic */
-	for (i = 0; i < 1000; i++) {	/* wait 100us */
-	}
-	pEMC->DYNAMICCONTROL    = 0x00000183;	/* Issue NOP command */
-
-	/* TIM_Waitus(200); */						   /* wait 200us */
-	/*TODO: if Timer driver is ready, it should replace below "for" delay technic */
-	for (i = 0; i < 1000; i++) {}
-	pEMC->DYNAMICCONTROL    = 0x00000103;	/* Issue PALL command */
-
-	pEMC->DYNAMICREFRESH = 2;	/* ( 2 * 16 ) -> 32 clock cycles */
-
-	/* TIM_Waitus(200); */						   /* wait 200us */
-	for (i = 0; i < 80; i++) {}
-
-	tmpclk = EMC_DIV_ROUND_UP(EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->RefreshPeriod, 0), 16);
-	pEMC->DYNAMICREFRESH    = tmpclk;
-
-	pEMC->DYNAMICCONTROL    = 0x00000083;	/* Issue MODE command */
-
-	for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
-		/*uint32_t burst_length;*/
-		uint32_t DynAddr;
-		uint8_t Col_len;
-
-		Col_len = EMC_GetColsLen(Dynamic_Config->DevConfig[ChipSelect].DynConfig);
-		/* get bus wide: if 32bit, len is 4 else if 16bit len is 2 */
-		/* burst_length = 1 << ((((Dynamic_Config->DynConfig[ChipSelect] >> 14) & 1)^1) +1); */
-		if (Dynamic_Config->DevConfig[ChipSelect].DynConfig & (1 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)) {
-			/*32bit bus */
-			/*burst_length = 2;*/
-			Col_len += 2;
-		}
-		else {
-			/*burst_length = 4;*/
-			Col_len += 1;
-		}
-		DynAddr = Dynamic_Config->DevConfig[ChipSelect].BaseAddr;
-
-		if (DynAddr != 0) {
-			uint32_t temp;
-			uint32_t ModeRegister;
-			ModeRegister = Dynamic_Config->DevConfig[ChipSelect].ModeRegister;
-			temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len)));
-			temp = temp;
-		}
-	}
-	pEMC->DYNAMICCONTROL    = 0x00000000;	/* Issue NORMAL command */
-
-	/* enable buffers */
-	pEMC->DYNAMICCONFIG0    |= 1 << 19;
-	pEMC->DYNAMICCONFIG1    |= 1 << 19;
-	pEMC->DYNAMICCONFIG2    |= 1 << 19;
-	pEMC->DYNAMICCONFIG3    |= 1 << 19;
-}
-
-/* Set Deep Sleep Mode for Dynamic Memory Controller */
-void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable)
-{
-	if (Enable) {
-		pEMC->DYNAMICCONTROL |= 1 << EMC_DYN_CONTROL_DEEPSLEEP_BIT;
-	}
-	else {
-		pEMC->DYNAMICCONTROL &= ~(1 << EMC_DYN_CONTROL_DEEPSLEEP_BIT);
-	}
-}
-
-/* Enable Dynamic Memory Controller */
-void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable)
-{
-	if (Enable) {
-		pEMC->DYNAMICCONTROL |= EMC_DYN_CONTROL_ENABLE;
-	}
-	else {
-		pEMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE;
-	}
-}
-
-/* Initializes the Static Controller according to the specified parameters
- * in the IP_EMC_STATIC_CONFIG_Type
- */
-void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock)
-{
-	IP_EMC_001_Type *EMC_Reg_add = (IP_EMC_001_Type *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5));
-	EMC_Reg_add->STATICCONFIG0      = Static_Config->Config;
-	EMC_Reg_add->STATICWAITWEN0     = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitWen, 1);
-	EMC_Reg_add->STATICWAITOEN0     = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitOen, 0);
-	EMC_Reg_add->STATICWAITRD0      = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitRd, 1);
-	EMC_Reg_add->STATICWAITPAG0     = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitPage, 1);
-	EMC_Reg_add->STATICWAITWR0      = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitWr, 2);
-	EMC_Reg_add->STATICWAITTURN0    = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitTurn, 1);
-}
-
-/* Mirror CS1 to CS0 and DYCS0 */
-void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable)
-{
-	if (Enable) {
-		pEMC->CONTROL |= 1 << 1;
-	}
-	else {
-		pEMC->CONTROL &= ~(1 << 1);
-	}
-}
-
-/* Enable EMC */
-void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable)
-{
-	if (Enable) {
-		pEMC->CONTROL |= 1;
-	}
-	else {
-		pEMC->CONTROL &= ~(1);
-	}
-}
-
-/* Set EMC LowPower Mode */
-void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable)
-{
-	if (Enable) {
-		pEMC->CONTROL |= 1 << 2;
-	}
-	else {
-		pEMC->CONTROL &= ~(1 << 2);
-	}
-}
-
-/* Initialize EMC */
-void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
-{
-	pEMC->CONFIG    = (EndianMode ? 1 : 0) | ((ClockRatio ? 1 : 0) << 8);
-
-	/* Enable EMC 001 Normal Memory Map, No low power mode */
-	pEMC->CONTROL     = (Enable ? 1 : 0);
-}
-
-/* Set Static Memory Extended Wait in Clock */
-void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks)
-{
-	pEMC->STATICEXTENDEDWAIT = Wait16Clks;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/emc_001.h b/bsp/xplorer4330/libraries/lpc_ip/emc_001.h
deleted file mode 100644
index b18405e389..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/emc_001.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * @brief EMC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EMC_001_H_
-#define __EMC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_EMC_001 IP: EMC register block and driver
- * @ingroup IP_Drivers
- * External Memory Controller
- * @{
- */
-
-/**
- * @brief External Memory Controller (EMC) register block structure
- */
-typedef struct {							/*!< EMC Structure          */
-	__IO uint32_t  CONTROL;					/*!< Controls operation of the memory controller. */
-	__I  uint32_t  STATUS;					/*!< Provides EMC status information. */
-	__IO uint32_t  CONFIG;					/*!< Configures operation of the memory controller. */
-	__I  uint32_t  RESERVED0[5];
-	__IO uint32_t  DYNAMICCONTROL;			/*!< Controls dynamic memory operation. */
-	__IO uint32_t  DYNAMICREFRESH;			/*!< Configures dynamic memory refresh operation. */
-	__IO uint32_t  DYNAMICREADCONFIG;		/*!< Configures the dynamic memory read strategy. */
-	__I  uint32_t  RESERVED1;
-	__IO uint32_t  DYNAMICRP;				/*!< Selects the precharge command period. */
-	__IO uint32_t  DYNAMICRAS;				/*!< Selects the active to precharge command period. */
-	__IO uint32_t  DYNAMICSREX;				/*!< Selects the self-refresh exit time. */
-	__IO uint32_t  DYNAMICAPR;				/*!< Selects the last-data-out to active command time. */
-	__IO uint32_t  DYNAMICDAL;				/*!< Selects the data-in to active command time. */
-	__IO uint32_t  DYNAMICWR;				/*!< Selects the write recovery time. */
-	__IO uint32_t  DYNAMICRC;				/*!< Selects the active to active command period. */
-	__IO uint32_t  DYNAMICRFC;				/*!< Selects the auto-refresh period. */
-	__IO uint32_t  DYNAMICXSR;				/*!< Selects the exit self-refresh to active command time. */
-	__IO uint32_t  DYNAMICRRD;				/*!< Selects the active bank A to active bank B latency. */
-	__IO uint32_t  DYNAMICMRD;				/*!< Selects the load mode register to active command time. */
-	__I  uint32_t  RESERVED2[9];
-	__IO uint32_t  STATICEXTENDEDWAIT;		/*!< Selects time for long static memory read and write transfers. */
-	__I  uint32_t  RESERVED3[31];
-	__IO uint32_t  DYNAMICCONFIG0;			/*!< Selects the configuration information for dynamic memory chip select n. */
-	__IO uint32_t  DYNAMICRASCAS0;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
-	__I  uint32_t  RESERVED4[6];
-	__IO uint32_t  DYNAMICCONFIG1;			/*!< Selects the configuration information for dynamic memory chip select n. */
-	__IO uint32_t  DYNAMICRASCAS1;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
-	__I  uint32_t  RESERVED5[6];
-	__IO uint32_t  DYNAMICCONFIG2;			/*!< Selects the configuration information for dynamic memory chip select n. */
-	__IO uint32_t  DYNAMICRASCAS2;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
-	__I  uint32_t  RESERVED6[6];
-	__IO uint32_t  DYNAMICCONFIG3;			/*!< Selects the configuration information for dynamic memory chip select n. */
-	__IO uint32_t  DYNAMICRASCAS3;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
-	__I  uint32_t  RESERVED7[38];
-	__IO uint32_t  STATICCONFIG0;			/*!< Selects the memory configuration for static chip select n. */
-	__IO uint32_t  STATICWAITWEN0;			/*!< Selects the delay from chip select n to write enable. */
-	__IO uint32_t  STATICWAITOEN0;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
-	__IO uint32_t  STATICWAITRD0;			/*!< Selects the delay from chip select n to a read access. */
-	__IO uint32_t  STATICWAITPAG0;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-	__IO uint32_t  STATICWAITWR0;			/*!< Selects the delay from chip select n to a write access. */
-	__IO uint32_t  STATICWAITTURN0;			/*!< Selects bus turnaround cycles */
-	__I  uint32_t  RESERVED8;
-	__IO uint32_t  STATICCONFIG1;			/*!< Selects the memory configuration for static chip select n. */
-	__IO uint32_t  STATICWAITWEN1;			/*!< Selects the delay from chip select n to write enable. */
-	__IO uint32_t  STATICWAITOEN1;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
-	__IO uint32_t  STATICWAITRD1;			/*!< Selects the delay from chip select n to a read access. */
-	__IO uint32_t  STATICWAITPAG1;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-	__IO uint32_t  STATICWAITWR1;			/*!< Selects the delay from chip select n to a write access. */
-	__IO uint32_t  STATICWAITTURN1;			/*!< Selects bus turnaround cycles */
-	__I  uint32_t  RESERVED9;
-	__IO uint32_t  STATICCONFIG2;			/*!< Selects the memory configuration for static chip select n. */
-	__IO uint32_t  STATICWAITWEN2;			/*!< Selects the delay from chip select n to write enable. */
-	__IO uint32_t  STATICWAITOEN2;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
-	__IO uint32_t  STATICWAITRD2;			/*!< Selects the delay from chip select n to a read access. */
-	__IO uint32_t  STATICWAITPAG2;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-	__IO uint32_t  STATICWAITWR2;			/*!< Selects the delay from chip select n to a write access. */
-	__IO uint32_t  STATICWAITTURN2;			/*!< Selects bus turnaround cycles */
-	__I  uint32_t  RESERVED10;
-	__IO uint32_t  STATICCONFIG3;			/*!< Selects the memory configuration for static chip select n. */
-	__IO uint32_t  STATICWAITWEN3;			/*!< Selects the delay from chip select n to write enable. */
-	__IO uint32_t  STATICWAITOEN3;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
-	__IO uint32_t  STATICWAITRD3;			/*!< Selects the delay from chip select n to a read access. */
-	__IO uint32_t  STATICWAITPAG3;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-	__IO uint32_t  STATICWAITWR3;			/*!< Selects the delay from chip select n to a write access. */
-	__IO uint32_t  STATICWAITTURN3;			/*!< Selects bus turnaround cycles */
-} IP_EMC_001_Type;
-
-/**
- * @brief EMC register support bitfields and mask
- */
-/* Reserve for extending support to ARM9 or nextgen LPC */
-#define EMC_SUPPORT_ONLY_PL172	/*!< Reserve for extending support to ARM9 or nextgen LPC */
-
-#define EMC_CONFIG_ENDIAN_LITTLE    (0)		/*!< Value for EMC to operate in Little Endian Mode */
-#define EMC_CONFIG_ENDIAN_BIG         (1)	/*!< Value for EMC to operate in Big Endian Mode */
-
-#define EMC_CONFIG_BUFFER_ENABLE    (1 << 19)	/*!< EMC Buffer enable bit in EMC Dynamic Configuration register */
-#define EMC_CONFIG_WRITE_PROTECT    (1 << 20)	/*!< EMC Write protect bit in EMC Dynamic Configuration register */
-
-/* Dynamic Memory Configuration Register Bit Definitions */
-#define EMC_DYN_CONFIG_MD_BIT             (3)								/*!< Memory device bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_MD_SDRAM         (0 << EMC_DYN_CONFIG_MD_BIT)		/*!< Select device as SDRAM in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_MD_LPSDRAM       (1 << EMC_DYN_CONFIG_MD_BIT)		/*!< Select device as LPSDRAM in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_LPSDRAM_BIT      (12)							/*!< LPSDRAM bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_LPSDRAM          (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)	/*!< LPSDRAM value in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_DEV_SIZE_BIT     (9)									/*!< Device Size starting bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_16Mb    (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 16Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_64Mb    (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 64Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 128Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 256Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 512Mb Device Size value in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_DEV_BUS_BIT      (7)									/*!< Device bus width starting bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_BUS_8        (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 8-bit bus width value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_BUS_16       (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 16-bit bus width value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_BUS_32       (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)									/*!< Device data bus width starting bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DATA_BUS_16      (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)	/*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DATA_BUS_32      (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)	/*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
-
-/*!< Memory configuration values in EMC Dynamic Configuration Register */
-#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS     ((0x0 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */
-#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS    ((0x0 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */
-#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS     ((0x1 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */
-#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS    ((0x1 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */
-#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS    ((0x1 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */
-#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */
-#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS    ((0x2 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */
-#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS    ((0x2 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */
-#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */
-#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */
-#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS    ((0x3 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */
-#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */
-#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS  ((0x4 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */
-
-/*!< Dynamic Memory Mode Register Bit Definition */
-#define EMC_DYN_MODE_BURST_LEN_BIT      (0)	/*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_1        (0)	/*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_2        (1)	/*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_4        (2)	/*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_8        (3)	/*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_FULL     (7)	/*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */
-
-#define EMC_DYN_MODE_BURST_TYPE_BIT         (3)									/*!< Burst Type bit in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL  (0 << EMC_DYN_MODE_BURST_TYPE_BIT)	/*!< Burst Type Sequential in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE  (1 << EMC_DYN_MODE_BURST_TYPE_BIT)	/*!< Burst Type Interleaved in Dynamic Memory Mode Register */
-
-/*!< CAS Latency in Dynamic Mode Register */
-#define EMC_DYN_MODE_CAS_BIT    (4)							/*!< CAS latency starting bit in Dynamic Memory Mode register */
-#define EMC_DYN_MODE_CAS_1      (1 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 1 cycle */
-#define EMC_DYN_MODE_CAS_2      (2 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 2 cycle */
-#define EMC_DYN_MODE_CAS_3      (3 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 3 cycle */
-
-/*!< Operation Mode in Dynamic Mode register */
-#define EMC_DYN_MODE_OPMODE_BIT           (7)							/*!< Dynamic Mode Operation bit */
-#define EMC_DYN_MODE_OPMODE_STANDARD    (0 << EMC_DYN_MODE_OPMODE_BIT)	/*!< Value for Dynamic standard operation Mode */
-
-/*!< Write Burst Mode in Dynamic Mode register */
-#define EMC_DYN_MODE_WBMODE_BIT             (9)							/*!< Write Burst Mode bit */
-#define EMC_DYN_MODE_WBMODE_PROGRAMMED  (0 << EMC_DYN_MODE_WBMODE_BIT)	/*!< Write Burst Mode programmed */
-#define EMC_DYN_MODE_WBMODE_SINGLE_LOC  (1 << EMC_DYN_MODE_WBMODE_BIT)	/*!< Write Burst Mode Single LOC */
-
-/*!< Dynamic Memory Control Register Bit Definitions */
-#define EMC_DYN_CONTROL_DEEPSLEEP_BIT   (13)	/*!< Deep sleep Mode bit */
-#define EMC_DYN_CONTROL_ENABLE          (0x03)	/*!< Control Enable value */
-
-/*!< Static Memory Configuration Register Bit Definitions */
-#define EMC_STATIC_CONFIG_MEM_WIDTH_8       (0)	/*!< Static Memory Configuration - 8-bit width */
-#define EMC_STATIC_CONFIG_MEM_WIDTH_16      (1)	/*!< Static Memory Configuration - 16-bit width */
-#define EMC_STATIC_CONFIG_MEM_WIDTH_32      (2)	/*!< Static Memory Configuration - 32-bit width */
-
-#define EMC_STATIC_CONFIG_PAGE_MODE_BIT         (3)										/*!< Page Mode bit No */
-#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE      (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)	/*!< Value to enable Page Mode */
-
-#define EMC_STATIC_CONFIG_CS_POL_BIT            (6)									/*!< Chip Select bit No */
-#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH    (1 << EMC_STATIC_CONFIG_CS_POL_BIT)	/*!< Chip Select polarity - Active High */
-#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW     (0 << EMC_STATIC_CONFIG_CS_POL_BIT)	/*!< Chip Select polarity - Active Low */
-
-#define EMC_STATIC_CONFIG_BLS_BIT           (7)								/*!< BLS Configuration bit No */
-#define EMC_STATIC_CONFIG_BLS_HIGH          (1 << EMC_STATIC_CONFIG_BLS_BIT)	/*!< BLS High Configuration value */
-#define EMC_STATIC_CONFIG_BLS_LOW           (0 << EMC_STATIC_CONFIG_BLS_BIT)	/*!< BLS Low Configuration value */
-
-#define EMC_STATIC_CONFIG_EW_BIT            (8)								/*!< Ext Wait bit No */
-#define EMC_STATIC_CONFIG_EW_ENABLE         (1 << EMC_STATIC_CONFIG_EW_BIT)	/*!< Ext Wait Enabled value */
-#define EMC_STATIC_CONFIG_EW_DISABLE        (0 << EMC_STATIC_CONFIG_EW_BIT)	/*!< Ext Wait Diabled value */
-
-/*!< Q24.8 Fixed Point Helper */
-#define Q24_8_FP(x) ((x) * 256)
-#define EMC_NANOSECOND(x)   Q24_8_FP(x)
-#define EMC_CLOCK(x)        Q24_8_FP(-(x))
-
-/**
- * @brief	EMC Dynamic Device Configuration structure used for IP drivers
- */
-typedef struct {
-	uint32_t    BaseAddr;		/*!< Base Address */
-	uint8_t     RAS;			/*!< RAS value */
-	uint32_t    ModeRegister;	/*!< Mode Register value */
-	uint32_t    DynConfig;		/*!< Dynamic Configuration value */
-} IP_EMC_DYN_DEVICE_CONFIG_Type;
-
-/**
- * @brief EMC Dynamic Configure Struct
- */
-typedef struct {
-	int32_t RefreshPeriod;							/*!< Refresh period */
-	uint32_t ReadConfig;							/*!< Clock*/
-	int32_t tRP;									/*!< Precharge Command Period */
-	int32_t tRAS;									/*!< Active to Precharge Command Period */
-	int32_t tSREX;									/*!< Self Refresh Exit Time */
-	int32_t tAPR;									/*!< Last Data Out to Active Time */
-	int32_t tDAL;									/*!< Data In to Active Command Time */
-	int32_t tWR;									/*!< Write Recovery Time */
-	int32_t tRC;									/*!< Active to Active Command Period */
-	int32_t tRFC;									/*!< Auto-refresh Period */
-	int32_t tXSR;									/*!< Exit Selt Refresh */
-	int32_t tRRD;									/*!< Active Bank A to Active Bank B Time */
-	int32_t tMRD;									/*!< Load Mode register command to Active Command */
-	IP_EMC_DYN_DEVICE_CONFIG_Type DevConfig[4];		/*!< Device Configuration array */
-} IP_EMC_DYN_CONFIG_Type;
-
-/**
- * @brief EMC Static Configure Structure
- */
-typedef struct {
-	uint8_t ChipSelect;		/*!< Chip select */
-	uint32_t Config;		/*!< Configuration value */
-	int32_t WaitWen;		/*!< Write Enable Wait */
-	int32_t WaitOen;		/*!< Output Enable Wait */
-	int32_t WaitRd;			/*!< Read Wait */
-	int32_t WaitPage;		/*!< Page Access Wait */
-	int32_t WaitWr;			/*!< Write Wait */
-	int32_t WaitTurn;		/*!< Turn around wait */
-} IP_EMC_STATIC_CONFIG_Type;
-
-/**
- * @brief	Initializes the Dynamic Controller
- * @param	pEMC			: Pointer to EMC peripheral
- * @param	Dynamic_Config	: Dynamic Memory Configure Struct
- * @param	EMC_Clock		: Frequency of EMC Clock Out
- * @return	None
- * Initializes the Dynamic Controller according to the specified parameters
- * in the IP_EMC_DYN_CONFIG_Type
- */
-void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock);
-
-/**
- * @brief	Set Deep Sleep Mode for Dynamic Memory Controller
- * @param	pEMC	: Pointer to EMC peripheral
- * @param	Enable	: 1 = enter DeepSleep Mode, 0 = Normal Mode
- * @return	None
- */
-void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable);
-
-/**
- * @brief	Enable Dynamic Memory Controller
- * @param	pEMC	: Pointer to EMC peripheral
- * @param	Enable	: 1 = Enable Dynamic Memory Controller, 0 = Disable
- * @return	None
- */
-void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable);
-
-/**
- * @brief	Initializes the Static Controller according to the specified
- *			parameters in the IP_EMC_STATIC_CONFIG_Type
- * @param	pEMC			: Pointer to EMC peripheral
- * @param	Static_Config	: Static Memory Configure Struct
- * @param	EMC_Clock		: Frequency of EMC Clock Out
- * @return	None
- */
-void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock);
-
-/**
- * @brief	Mirror CS1 to CS0 and DYCS0
- * @param	pEMC	: Pointer to EMC peripheral
- * @param	Enable	: 1 = Mirror, 0 = Normal Memory Map
- * @return	None
- */
-void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable);
-
-/**
- * @brief	Enable EMC
- * @param	pEMC	: Pointer to EMC peripheral
- * @param	Enable	: 1 = Enable, 0 = Disable
- * @return	None
- */
-void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable);
-
-/**
- * @brief	Set EMC LowPower Mode
- * @param	pEMC	: Pointer to EMC peripheral
- * @param	Enable	: 1 = Enable, 0 = Disable
- * @return	None
- */
-void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable);
-
-/**
- * @brief	Initialize EMC
- * @param	pEMC		: Pointer to EMC peripheral
- * @param	Enable		: 1 = Enable, 0 = Disable
- * @param	ClockRatio	: clock out ratio, 0 = 1:1, 1 = 1:2
- * @param	EndianMode	: Endian Mode, 0 = Little, 1 = Big
- * @return	None
- */
-void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
-
-/**
- * @brief	Set Static Memory Extended Wait in Clock
- * @param	pEMC		: Pointer to EMC peripheral
- * @param	Wait16Clks	: Number of '16 clock' delay cycles
- * @return	None
- */
-void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EMC_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/enet_001.c b/bsp/xplorer4330/libraries/lpc_ip/enet_001.c
deleted file mode 100644
index 7010d1544b..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/enet_001.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * @brief Ethernet control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "enet_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Saved address for PHY and clock divider */
-STATIC uint32_t phyCfg;
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Resets ethernet interface */
-void IP_ENET_Reset(IP_ENET_001_Type *LPC_ENET)
-{
-	/* This should be called prior to IP_ENET_Init. The MAC controller may
-	   not be ready for a call to init right away so a small delay should
-	   occur after this call. */
-	LPC_ENET->DMA_BUS_MODE |= DMA_BM_SWR;
-}
-
-/* Sets the address of the interface */
-void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr)
-{
-	/* Save MAC address */
-	LPC_ENET->MAC_ADDR0_LOW = ((uint32_t) macAddr[3] << 24) |
-							  ((uint32_t) macAddr[2] << 16) | ((uint32_t) macAddr[1] << 8) |
-							  ((uint32_t) macAddr[0]);
-	LPC_ENET->MAC_ADDR0_HIGH = ((uint32_t) macAddr[5] << 8) |
-							   ((uint32_t) macAddr[4]);
-}
-
-/* Initialize ethernet interface */
-void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET)
-{
-	/* Enhanced descriptors, burst length = 1 */
-	LPC_ENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1);
-
-	/* Initial MAC configuration for checksum offload, full duplex,
-	   100Mbps, disable receive own in half duplex, inter-frame gap
-	   of 64-bits */
-	LPC_ENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM |
-						   MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3);
-
-	/* Setup default filter */
-	LPC_ENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA;
-
-	/* Flush transmit FIFO */
-	LPC_ENET->DMA_OP_MODE = DMA_OM_FTF;
-
-	/* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at
-	   64 bytes */
-	LPC_ENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0);
-
-	/* Clear all MAC interrupts */
-	LPC_ENET->DMA_STAT = DMA_ST_ALL;
-
-	/* Enable MAC interrupts */
-	LPC_ENET->DMA_INT_EN = 0;
-}
-
-/* Sets up the PHY link clock divider and PHY address */
-void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr)
-{
-	/* Save clock divider and PHY address in MII address register */
-	phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div);
-}
-
-/*De-initialize the ethernet interface */
-void IP_ENET_DeInit(IP_ENET_001_Type *LPC_ENET)
-{
-	/* Disable packet reception */
-	LPC_ENET->MAC_CONFIG = 0;
-
-	/* Flush transmit FIFO */
-	LPC_ENET->DMA_OP_MODE = DMA_OM_FTF;
-
-	/* Disable receive and transmit DMA processes */
-	LPC_ENET->DMA_OP_MODE = 0;
-}
-
-/* Starts a PHY write via the MII */
-void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data)
-{
-	/* Write value at PHY address and register */
-	LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W;
-	LPC_ENET->MAC_MII_DATA = (uint32_t) data;
-	LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
-}
-
-/*Starts a PHY read via the MII */
-void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg)
-{
-	/* Read value at PHY address and register */
-	LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg);
-	LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
-}
-
-/* Returns MII link (PHY) busy status */
-bool IP_ENET_IsMIIBusy(IP_ENET_001_Type *LPC_ENET)
-{
-	if (LPC_ENET->MAC_MII_ADDR & MAC_MIIA_GB) {
-		return true;
-	}
-
-	return false;
-}
-
-/* Enables or disables ethernet transmit */
-void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable)
-{
-	if (Enable) {
-		/* Descriptor list head pointers must be setup prior to enable */
-		LPC_ENET->MAC_CONFIG |= MAC_CFG_TE;
-		LPC_ENET->DMA_OP_MODE |= DMA_OM_ST;
-	}
-	else {
-		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_TE;
-	}
-}
-
-/* Enables or disables ethernet packet reception */
-void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable)
-{
-	if (Enable) {
-		/* Descriptor list head pointers must be setup prior to enable */
-		LPC_ENET->MAC_CONFIG |= MAC_CFG_RE;
-		LPC_ENET->DMA_OP_MODE |= DMA_OM_SR;
-	}
-	else {
-		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_RE;
-	}
-}
-
-/* Sets full or half duplex for the interface */
-void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full)
-{
-	if (full) {
-		LPC_ENET->MAC_CONFIG |= MAC_CFG_DM;
-	}
-	else {
-		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_DM;
-	}
-}
-
-/* Sets speed for the interface */
-void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100)
-{
-	if (speed100) {
-		LPC_ENET->MAC_CONFIG |= MAC_CFG_FES;
-	}
-	else {
-		LPC_ENET->MAC_CONFIG &= ~MAC_CFG_FES;
-	}
-}
-
-/* Configures the initial ethernet descriptors */
-void IP_ENET_InitDescriptors(IP_ENET_001_Type *LPC_ENET,
-							 IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs)
-{
-	/* Setup descriptor list base addresses */
-	LPC_ENET->DMA_TRANS_DES_ADDR = (uint32_t) pTXDescs;
-	LPC_ENET->DMA_REC_DES_ADDR = (uint32_t) pRXDescs;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/enet_001.h b/bsp/xplorer4330/libraries/lpc_ip/enet_001.h
deleted file mode 100644
index b0bab1fb74..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/enet_001.h
+++ /dev/null
@@ -1,608 +0,0 @@
-/*
- * @brief Ethernet control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ENET_001_H_
-#define __ENET_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ENET_001 IP: Ethernet register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief 10/100 MII & RMII Ethernet with timestamping register block structure
- */
-typedef struct {							/*!< ETHERNET Structure */
-	__IO uint32_t  MAC_CONFIG;				/*!< MAC configuration register */
-	__IO uint32_t  MAC_FRAME_FILTER;		/*!< MAC frame filter */
-	__IO uint32_t  MAC_HASHTABLE_HIGH;		/*!< Hash table high register */
-	__IO uint32_t  MAC_HASHTABLE_LOW;		/*!< Hash table low register */
-	__IO uint32_t  MAC_MII_ADDR;			/*!< MII address register */
-	__IO uint32_t  MAC_MII_DATA;			/*!< MII data register */
-	__IO uint32_t  MAC_FLOW_CTRL;			/*!< Flow control register */
-	__IO uint32_t  MAC_VLAN_TAG;			/*!< VLAN tag register */
-	__I  uint32_t  RESERVED0;
-	__I  uint32_t  MAC_DEBUG;				/*!< Debug register */
-	__IO uint32_t  MAC_RWAKE_FRFLT;			/*!< Remote wake-up frame filter */
-	__IO uint32_t  MAC_PMT_CTRL_STAT;		/*!< PMT control and status */
-	__I  uint32_t  RESERVED1[2];
-	__I  uint32_t  MAC_INTR;				/*!< Interrupt status register */
-	__IO uint32_t  MAC_INTR_MASK;			/*!< Interrupt mask register */
-	__IO uint32_t  MAC_ADDR0_HIGH;			/*!< MAC address 0 high register */
-	__IO uint32_t  MAC_ADDR0_LOW;			/*!< MAC address 0 low register */
-	__I  uint32_t  RESERVED2[430];
-	__IO uint32_t  MAC_TIMESTP_CTRL;		/*!< Time stamp control register */
-	__IO uint32_t  SUBSECOND_INCR;			/*!< Sub-second increment register */
-	__I  uint32_t  SECONDS;					/*!< System time seconds register */
-	__I  uint32_t  NANOSECONDS;				/*!< System time nanoseconds register */
-	__IO uint32_t  SECONDSUPDATE;			/*!< System time seconds update register */
-	__IO uint32_t  NANOSECONDSUPDATE;		/*!< System time nanoseconds update register */
-	__IO uint32_t  ADDEND;					/*!< Time stamp addend register */
-	__IO uint32_t  TARGETSECONDS;			/*!< Target time seconds register */
-	__IO uint32_t  TARGETNANOSECONDS;		/*!< Target time nanoseconds register */
-	__IO uint32_t  HIGHWORD;				/*!< System time higher word seconds register */
-	__I  uint32_t  TIMESTAMPSTAT;			/*!< Time stamp status register */
-	__IO uint32_t  PPSCTRL;					/*!< PPS control register */
-	__I  uint32_t  AUXNANOSECONDS;			/*!< Auxiliary time stamp nanoseconds register */
-	__I  uint32_t  AUXSECONDS;				/*!< Auxiliary time stamp seconds register */
-	__I  uint32_t  RESERVED3[562];
-	__IO uint32_t  DMA_BUS_MODE;			/*!< Bus Mode Register      */
-	__IO uint32_t  DMA_TRANS_POLL_DEMAND;	/*!< Transmit poll demand register */
-	__IO uint32_t  DMA_REC_POLL_DEMAND;		/*!< Receive poll demand register */
-	__IO uint32_t  DMA_REC_DES_ADDR;		/*!< Receive descriptor list address register */
-	__IO uint32_t  DMA_TRANS_DES_ADDR;		/*!< Transmit descriptor list address register */
-	__IO uint32_t  DMA_STAT;				/*!< Status register */
-	__IO uint32_t  DMA_OP_MODE;				/*!< Operation mode register */
-	__IO uint32_t  DMA_INT_EN;				/*!< Interrupt enable register */
-	__I  uint32_t  DMA_MFRM_BUFOF;			/*!< Missed frame and buffer overflow register */
-	__IO uint32_t  DMA_REC_INT_WDT;			/*!< Receive interrupt watchdog timer register */
-	__I  uint32_t  RESERVED4[8];
-	__I  uint32_t  DMA_CURHOST_TRANS_DES;	/*!< Current host transmit descriptor register */
-	__I  uint32_t  DMA_CURHOST_REC_DES;		/*!< Current host receive descriptor register */
-	__I  uint32_t  DMA_CURHOST_TRANS_BUF;	/*!< Current host transmit buffer address register */
-	__I  uint32_t  DMA_CURHOST_REC_BUF;		/*!< Current host receive buffer address register */
-} IP_ENET_001_Type;
-
-/**
- * @brief MAC_CONFIG register bit defines
- */
-#define MAC_CFG_RE     (1 << 2)		/*!< Receiver enable */
-#define MAC_CFG_TE     (1 << 3)		/*!< Transmitter Enable */
-#define MAC_CFG_DF     (1 << 4)		/*!< Deferral Check */
-#define MAC_CFG_BL(n)  ((n) << 5)	/*!< Back-Off Limit */
-#define MAC_CFG_ACS    (1 << 7)		/*!< Automatic Pad/CRC Stripping */
-#define MAC_CFG_LUD    (1 << 8)		/*!< Link Up/Down, 1 = up */
-#define MAC_CFG_DR     (1 << 9)		/*!< Disable Retry */
-#define MAC_CFG_IPC    (1 << 10)	/*!< Checksum Offload */
-#define MAC_CFG_DM     (1 << 11)	/*!< Duplex Mode, 1 = full, 0 = half */
-#define MAC_CFG_LM     (1 << 12)	/*!< Loopback Mode */
-#define MAC_CFG_DO     (1 << 13)	/*!< Disable Receive Own */
-#define MAC_CFG_FES    (1 << 14)	/*!< Speed, 1 = 100Mbps, 0 = 10Mbos */
-#define MAC_CFG_PS     (1 << 15)	/*!< Port select, must always be 1 */
-#define MAC_CFG_DCRS   (1 << 16)	/*!< Disable carrier sense during transmission */
-#define MAC_CFG_IFG(n) ((n) << 17)	/*!< Inter-frame gap, 40..96, n incs by 8 */
-#define MAC_CFG_JE     (1 << 20)	/*!< Jumbo Frame Enable */
-#define MAC_CFG_JD     (1 << 22)	/*!< Jabber Disable */
-#define MAC_CFG_WD     (1 << 23)	/*!< Watchdog Disable */
-
-/**
- * @brief MAC_FRAME_FILTER register bit defines
- */
-#define MAC_FF_PR      (1 << 0)		/*!< Promiscuous Mode */
-#define MAC_FF_DAIF    (1 << 3)		/*!< DA Inverse Filtering */
-#define MAC_FF_PM      (1 << 4)		/*!< Pass All Multicast */
-#define MAC_FF_DBF     (1 << 5)		/*!< Disable Broadcast Frames */
-#define MAC_FF_PCF(n)  ((n) << 6)	/*!< Pass Control Frames, n = see user manual */
-#define MAC_FF_SAIF    (1 << 8)		/*!< SA Inverse Filtering */
-#define MAC_FF_SAF     (1 << 9)		/*!< Source Address Filter Enable */
-#define MAC_FF_RA      (1UL << 31)	/*!< Receive all */
-
-/**
- * @brief MAC_MII_ADDR register bit defines
- */
-#define MAC_MIIA_GB    (1 << 0)		/*!< MII busy */
-#define MAC_MIIA_W     (1 << 1)		/*!< MII write */
-#define MAC_MIIA_CR(n) ((n) << 2)	/*!< CSR clock range, n = see manual */
-#define MAC_MIIA_GR(n) ((n) << 6)	/*!< MII register. n = 0..31 */
-#define MAC_MIIA_PA(n) ((n) << 11)	/*!< Physical layer address, n = 0..31 */
-
-/**
- * @brief MAC_MII_DATA register bit defines
- */
-#define MAC_MIID_GDMSK (0xFFFF)		/*!< MII data mask */
-
-/**
- * @brief MAC_FLOW_CONTROL register bit defines
- */
-#define MAC_FC_FCB     (1 << 0)		/*!< Flow Control Busy/Backpressure Activate */
-#define MAC_FC_TFE     (1 << 1)		/*!< Transmit Flow Control Enable */
-#define MAC_FC_RFE     (1 << 2)		/*!< Receive Flow Control Enable */
-#define MAC_FC_UP      (1 << 3)		/*!< Unicast Pause Frame Detect */
-#define MAC_FC_PLT(n)  ((n) << 4)	/*!< Pause Low Threshold, n = see manual */
-#define MAC_FC_DZPQ    (1 << 7)		/*!< Disable Zero-Quanta Pause */
-#define MAC_FC_PT(n)   ((n) << 16)	/*!< Pause time */
-
-/**
- * @brief MAC_VLAN_TAG register bit defines
- */
-#define MAC_VT_VL(n)   ((n) << 0)	/*!< VLAN Tag Identifier for Receive Frames */
-#define MAC_VT_ETC     (1 << 7)		/*!< Enable 12-Bit VLAN Tag Comparison */
-
-/**
- * @brief MAC_PMT_CTRL_STAT register bit defines
- */
-#define MAC_PMT_PD     (1 << 0)		/*!< Power-down */
-#define MAC_PMT_MPE    (1 << 1)		/*!< Magic packet enable */
-#define MAC_PMT_WFE    (1 << 2)		/*!< Wake-up frame enable */
-#define MAC_PMT_MPR    (1 << 5)		/*!< Magic Packet Received */
-#define MAC_PMT_WFR    (1 << 6)		/*!< Wake-up Frame Received */
-#define MAC_PMT_GU     (1 << 9)		/*!< Global Unicast */
-#define MAC_PMT_WFFRPR (1UL << 31)	/*!< Wake-up Frame Filter Register Pointer Reset */
-
-/**
- * @brief MAC_INTR_MASK register bit defines
- */
-#define MAC_IM_PMT     (1 << 3)		/*!< PMT Interrupt Mask */
-
-/**
- * @brief MAC_ADDR0_HIGH register bit defines
- */
-#define MAC_ADRH_MO    (1UL << 31)	/*!< Always 1 when writing register */
-
-/**
- * @brief MAC_ADDR0_HIGH register bit defines
- */
-#define MAC_ADRH_MO    (1UL << 31)	/*!< Always 1 when writing register */
-
-/**
- * @brief MAC_TIMESTAMP register bit defines
- */
-#define MAC_TS_TSENA   (1 << 0)		/*!< Time Stamp Enable */
-#define MAC_TS_TSCFUP  (1 << 1)		/*!< Time Stamp Fine or Coarse Update */
-#define MAC_TS_TSINIT  (1 << 2)		/*!< Time Stamp Initialize */
-#define MAC_TS_TSUPDT  (1 << 3)		/*!< Time Stamp Update */
-#define MAC_TS_TSTRIG  (1 << 4)		/*!< Time Stamp Interrupt Trigger Enable */
-#define MAC_TS_TSADDR  (1 << 5)		/*!< Addend Reg Update */
-#define MAC_TS_TSENAL  (1 << 8)		/*!< Enable Time Stamp for All Frames */
-#define MAC_TS_TSCTRL  (1 << 9)		/*!< Time Stamp Digital or Binary rollover control */
-#define MAC_TS_TSVER2  (1 << 10)	/*!< Enable PTP packet snooping for version 2 format */
-#define MAC_TS_TSIPENA (1 << 11)	/*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */
-#define MAC_TS_TSIPV6E (1 << 12)	/*!< Enable Time Stamp Snapshot for IPv6 frames */
-#define MAC_TS_TSIPV4E (1 << 13)	/*!< Enable Time Stamp Snapshot for IPv4 frames */
-#define MAC_TS_TSEVNT  (1 << 14)	/*!< Enable Time Stamp Snapshot for Event Messages */
-#define MAC_TS_TSMSTR  (1 << 15)	/*!< Enable Snapshot for Messages Relevant to Master */
-#define MAC_TS_TSCLKT(n) ((n) << 16)	/*!< Select the type of clock node, n = see menual */
-#define MAC_TS_TSENMA  (1 << 18)	/*!< Enable MAC address for PTP frame filtering */
-
-/**
- * @brief DMA_BUS_MODE register bit defines
- */
-#define DMA_BM_SWR     (1 << 0)		/*!< Software reset */
-#define DMA_BM_DA      (1 << 1)		/*!< DMA arbitration scheme, 1 = TX has priority over TX */
-#define DMA_BM_DSL(n)  ((n) << 2)	/*!< Descriptor skip length, n = see manual */
-#define DMA_BM_ATDS    (1 << 7)		/*!< Alternate (Enhanced) descriptor size */
-#define DMA_BM_PBL(n)  ((n) << 8)	/*!< Programmable burst length, n = see manual */
-#define DMA_BM_PR(n)   ((n) << 14)	/*!< Rx-to-Tx priority ratio, n = see manual */
-#define DMA_BM_FB      (1 << 16)	/*!< Fixed burst */
-#define DMA_BM_RPBL(n) ((n) << 17)	/*!< RxDMA PBL, n = see manual */
-#define DMA_BM_USP     (1 << 23)	/*!< Use separate PBL */
-#define DMA_BM_PBL8X   (1 << 24)	/*!< 8 x PBL mode */
-#define DMA_BM_AAL     (1 << 25)	/*!< Address-aligned beats */
-#define DMA_BM_MB      (1 << 26)	/*!< Mixed burst */
-#define DMA_BM_TXPR    (1 << 27)	/*!< Transmit DMA has higher priority than receive DMA */
-
-/**
- * @brief DMA_STAT register bit defines
- */
-#define DMA_ST_TI      (1 << 0)		/*!< Transmit interrupt */
-#define DMA_ST_TPS     (1 << 1)		/*!< Transmit process stopped */
-#define DMA_ST_TU      (1 << 2)		/*!< Transmit buffer unavailable */
-#define DMA_ST_TJT     (1 << 3)		/*!< Transmit jabber timeout */
-#define DMA_ST_OVF     (1 << 4)		/*!< Receive overflow */
-#define DMA_ST_UNF     (1 << 5)		/*!< Transmit underflow */
-#define DMA_ST_RI      (1 << 6)		/*!< Receive interrupt */
-#define DMA_ST_RU      (1 << 7)		/*!< Receive buffer unavailable */
-#define DMA_ST_RPS     (1 << 8)		/*!< Received process stopped */
-#define DMA_ST_RWT     (1 << 9)		/*!< Receive watchdog timeout */
-#define DMA_ST_ETI     (1 << 10)	/*!< Early transmit interrupt */
-#define DMA_ST_FBI     (1 << 13)	/*!< Fatal bus error interrupt */
-#define DMA_ST_ERI     (1 << 14)	/*!< Early receive interrupt */
-#define DMA_ST_AIE     (1 << 15)	/*!< Abnormal interrupt summary */
-#define DMA_ST_NIS     (1 << 16)	/*!< Normal interrupt summary */
-#define DMA_ST_ALL     (0x1E7FF)	/*!< All interrupts */
-
-/**
- * @brief DMA_OP_MODE register bit defines
- */
-#define DMA_OM_SR      (1 << 1)		/*!< Start/stop receive */
-#define DMA_OM_OSF     (1 << 2)		/*!< Operate on second frame */
-#define DMA_OM_RTC(n)  ((n) << 3)	/*!< Receive threshold control, n = see manual */
-#define DMA_OM_FUF     (1 << 6)		/*!< Forward undersized good frames */
-#define DMA_OM_FEF     (1 << 7)		/*!< Forward error frames */
-#define DMA_OM_ST      (1 << 13)	/*!< Start/Stop Transmission Command */
-#define DMA_OM_TTC(n)  ((n) << 14)	/*!< Transmit threshold control, n = see manual */
-#define DMA_OM_FTF     (1 << 20)	/*!< Flush transmit FIFO */
-#define DMA_OM_TSF     (1 << 21)	/*!< Transmit store and forward */
-#define DMA_OM_DFF     (1 << 24)	/*!< Disable flushing of received frames */
-#define DMA_OM_RSF     (1 << 25)	/*!< Receive store and forward */
-#define DMA_OM_DT      (1 << 26)	/*!< Disable Dropping of TCP/IP Checksum Error Frames */
-
-/**
- * @brief DMA_INT_EN register bit defines
- */
-#define DMA_IE_TIE     (1 << 0)		/*!< Transmit interrupt enable */
-#define DMA_IE_TSE     (1 << 1)		/*!< Transmit stopped enable */
-#define DMA_IE_TUE     (1 << 2)		/*!< Transmit buffer unavailable enable */
-#define DMA_IE_TJE     (1 << 3)		/*!< Transmit jabber timeout enable */
-#define DMA_IE_OVE     (1 << 4)		/*!< Overflow interrupt enable */
-#define DMA_IE_UNE     (1 << 5)		/*!< Underflow interrupt enable */
-#define DMA_IE_RIE     (1 << 6)		/*!< Receive interrupt enable */
-#define DMA_IE_RUE     (1 << 7)		/*!< Receive buffer unavailable enable */
-#define DMA_IE_RSE     (1 << 8)		/*!< Received stopped enable */
-#define DMA_IE_RWE     (1 << 9)		/*!< Receive watchdog timeout enable */
-#define DMA_IE_ETE     (1 << 10)	/*!< Early transmit interrupt enable */
-#define DMA_IE_FBE     (1 << 13)	/*!< Fatal bus error enable */
-#define DMA_IE_ERE     (1 << 14)	/*!< Early receive interrupt enable */
-#define DMA_IE_AIE     (1 << 15)	/*!< Abnormal interrupt summary enable */
-#define DMA_IE_NIE     (1 << 16)	/*!< Normal interrupt summary enable */
-
-/**
- * @brief DMA_MFRM_BUFOF register bit defines
- */
-#define DMA_MFRM_FMCMSK (0xFFFF)	/*!< Number of frames missed mask */
-#define DMA_MFRM_OC    (1 << 16)	/*!< Overflow bit for missed frame counter */
-#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17)	/*!< Number of frames missed by the application mask/shift */
-#define DMA_MFRM_OF    (1 << 28)	/*!< Overflow bit for FIFO overflow counter */
-
-/**
- * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines
- */
-#define TDES_DB        (1 << 0)		/*!< Deferred Bit */
-#define TDES_UF        (1 << 1)		/*!< Underflow Error */
-#define TDES_ED        (1 << 2)		/*!< Excessive Deferral */
-#define TDES_CCMSK(n)  (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */
-#define TDES_VF        (1 << 7)		/*!< VLAN Frame */
-#define TDES_EC        (1 << 8)		/*!< Excessive Collision */
-#define TDES_LC        (1 << 9)		/*!< Late Collision */
-#define TDES_NC        (1 << 10)	/*!< No Carrier */
-#define TDES_LCAR      (1 << 11)	/*!< Loss of Carrier */
-#define TDES_IPE       (1 << 12)	/*!< IP Payload Error */
-#define TDES_FF        (1 << 13)	/*!< Frame Flushed */
-#define TDES_JT        (1 << 14)	/*!< Jabber Timeout */
-#define TDES_ES        (1 << 15)	/*!< Error Summary */
-#define TDES_IHE       (1 << 16)	/*!< IP Header Error */
-#define TDES_TTSS      (1 << 17)	/*!< Transmit Timestamp Status */
-#define TDES_OWN       (1UL << 31)	/*!< Own Bit */
-
-/**
- * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines
- */
-#define TDES_ENH_IC   (1UL << 30)	/*!< Interrupt on Completion, enhanced descriptor */
-#define TDES_ENH_LS   (1 << 29)		/*!< Last Segment, enhanced descriptor */
-#define TDES_ENH_FS   (1 << 28)		/*!< First Segment, enhanced descriptor */
-#define TDES_ENH_DC   (1 << 27)		/*!< Disable CRC, enhanced descriptor */
-#define TDES_ENH_DP   (1 << 26)		/*!< Disable Pad, enhanced descriptor */
-#define TDES_ENH_TTSE (1 << 25)		/*!< Transmit Timestamp Enable, enhanced descriptor */
-#define TDES_ENH_CIC(n) ((n) << 22)	/*!< Checksum Insertion Control, enhanced descriptor */
-#define TDES_ENH_TER  (1 << 21)		/*!< Transmit End of Ring, enhanced descriptor */
-#define TDES_ENH_TCH  (1 << 20)		/*!< Second Address Chained, enhanced descriptor */
-
-/**
- * @brief TRAN_DESC_T only BSIZE field bit defines
- */
-#define TDES_NORM_IC   (1UL << 31)	/*!< Interrupt on Completion, normal descriptor */
-#define TDES_NORM_FS   (1 << 30)	/*!< First Segment, normal descriptor */
-#define TDES_NORM_LS   (1 << 29)	/*!< Last Segment, normal descriptor */
-#define TDES_NORM_CIC(n) ((n) << 27)	/*!< Checksum Insertion Control, normal descriptor */
-#define TDES_NORM_DC   (1 << 26)	/*!< Disable CRC, normal descriptor */
-#define TDES_NORM_TER  (1 << 25)	/*!< Transmit End of Ring, normal descriptor */
-#define TDES_NORM_TCH  (1 << 24)	/*!< Second Address Chained, normal descriptor */
-#define TDES_NORM_DP   (1 << 23)	/*!< Disable Pad, normal descriptor */
-#define TDES_NORM_TTSE (1 << 22)	/*!< Transmit Timestamp Enable, normal descriptor */
-#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11)	/*!< Buffer 2 size, normal descriptor */
-#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0)	/*!< Buffer 1 size, normal descriptor */
-
-/**
- * @brief TRAN_DESC_ENH_T only BSIZE field bit defines
- */
-#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16)	/*!< Buffer 2 size, enhanced descriptor */
-#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0)	/*!< Buffer 1 size, enhanced descriptor */
-
-/**
- * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines
- */
-#define RDES_ESA      (1 << 0)		/*!< Extended Status Available/Rx MAC Address */
-#define RDES_CE       (1 << 1)		/*!< CRC Error */
-#define RDES_DRE      (1 << 2)		/*!< Dribble Bit Error */
-#define RDES_RE       (1 << 3)		/*!< Receive Error */
-#define RDES_RWT      (1 << 4)		/*!< Receive Watchdog Timeout */
-#define RDES_FT       (1 << 5)		/*!< Frame Type */
-#define RDES_LC       (1 << 6)		/*!< Late Collision */
-#define RDES_TSA      (1 << 7)		/*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */
-#define RDES_LS       (1 << 8)		/*!< Last Descriptor */
-#define RDES_FS       (1 << 9)		/*!< First Descriptor */
-#define RDES_VLAN     (1 << 10)		/*!< VLAN Tag */
-#define RDES_OE       (1 << 11)		/*!< Overflow Error */
-#define RDES_LE       (1 << 12)		/*!< Length Error */
-#define RDES_SAF      (1 << 13)		/*!< Source Address Filter Fail */
-#define RDES_DE       (1 << 14)		/*!< Descriptor Error */
-#define RDES_ES       (1 << 15)		/*!< ES: Error Summary */
-#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */
-#define RDES_AFM      (1 << 30)		/*!< Destination Address Filter Fail */
-#define RDES_OWN      (1UL << 31)	/*!< Own Bit */
-
-/**
- * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines
- */
-#define RDES_DINT     (1UL << 31)	/*!< Disable interrupt on completion */
-
-/**
- * @brief REC_DESC_T pnly CTRL field bit defines
- */
-#define RDES_NORM_RER (1 << 25)		/*!< Receive End of Ring, normal descriptor */
-#define RDES_NORM_RCH (1 << 24)		/*!< Second Address Chained, normal descriptor */
-#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11)	/*!< Buffer 2 size, normal descriptor */
-#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0)	/*!< Buffer 1 size, normal descriptor */
-
-/**
- * @brief REC_DESC_ENH_T only CTRL field bit defines
- */
-#define RDES_ENH_RER  (1 << 15)		/*!< Receive End of Ring, enhanced descriptor */
-#define RDES_ENH_RCH  (1 << 14)		/*!< Second Address Chained, enhanced descriptor */
-#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16)	/*!< Buffer 2 size, enhanced descriptor */
-#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0)	/*!< Buffer 1 size, enhanced descriptor */
-
-/**
- * @brief REC_DESC_ENH_T only EXTSTAT field bit defines
- */
-#define RDES_ENH_IPPL(n)  (((n) & 0x7) >> 2)	/*!< IP Payload Type mask and shift, enhanced descripto */
-#define RDES_ENH_IPHE     (1 << 3)	/*!< IP Header Error, enhanced descripto */
-#define RDES_ENH_IPPLE    (1 << 4)	/*!< IP Payload Error, enhanced descripto */
-#define RDES_ENH_IPCSB    (1 << 5)	/*!< IP Checksum Bypassed, enhanced descripto */
-#define RDES_ENH_IPV4     (1 << 6)	/*!< IPv4 Packet Received, enhanced descripto */
-#define RDES_ENH_IPV6     (1 << 7)	/*!< IPv6 Packet Received, enhanced descripto */
-#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8)	/*!< Message Type mask and shift, enhanced descripto */
-
-/**
- * @brief Maximum size of an ethernet buffer
- */
-#define EMAC_ETH_MAX_FLEN (1536)
-
-/**
- * @brief Structure of a transmit descriptor (without timestamp)
- */
-typedef struct {
-	__IO uint32_t CTRLSTAT;		/*!< TDES control and status word */
-	__IO uint32_t BSIZE;		/*!< Buffer 1/2 byte counts */
-	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
-	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
-} IP_ENET_001_TXDESC_Type;
-
-/**
- * @brief Structure of a enhanced transmit descriptor (with timestamp)
- */
-typedef struct {
-	__IO uint32_t CTRLSTAT;		/*!< TDES control and status word */
-	__IO uint32_t BSIZE;		/*!< Buffer 1/2 byte counts */
-	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
-	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
-	__IO uint32_t TDES4;		/*!< Reserved */
-	__IO uint32_t TDES5;		/*!< Reserved */
-	__IO uint32_t TTSL;			/*!< Timestamp value low */
-	__IO uint32_t TTSH;			/*!< Timestamp value high */
-} IP_ENET_001_ENHTXDESC_Type;
-
-/**
- * @brief Structure of a receive descriptor (without timestamp)
- */
-typedef struct {
-	__IO uint32_t STATUS;		/*!< RDES status word */
-	__IO uint32_t CTRL;			/*!< Buffer 1/2 byte counts and control */
-	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
-	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
-} IP_ENET_001_RXDESC_Type;
-
-/**
- * @brief Structure of a enhanced receive descriptor (with timestamp)
- */
-typedef struct {
-	__IO uint32_t STATUS;		/*!< RDES status word */
-	__IO uint32_t CTRL;			/*!< Buffer 1/2 byte counts */
-	__IO uint32_t B1ADD;		/*!< Buffer 1 address */
-	__IO uint32_t B2ADD;		/*!< Buffer 2 or next descriptor address */
-	__IO uint32_t EXTSTAT;		/*!< Extended Status */
-	__IO uint32_t RDES5;		/*!< Reserved */
-	__IO uint32_t RTSL;			/*!< Timestamp value low */
-	__IO uint32_t RTSH;			/*!< Timestamp value high */
-} IP_ENET_001_ENHRXDESC_Type;
-
-/**
- * @brief	Resets the ethernet interface
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Nothing
- * Resets the ethernet interface. This should be called prior to
- * IP_ENET_Init with a small delay after this call.
- */
-void IP_ENET_Reset(IP_ENET_001_Type *LPC_ENET);
-
-/**
- * @brief	Sets the address of the interface
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	macAddr		: Pointer to the 6 bytes used for the MAC address
- * @return	Nothing
- */
-void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr);
-
-/**
- * @brief	Initialize ethernet interface
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Nothing
- * Performs basic initialization of the ethernet interface in a default
- * state. This is enough to place the interface in a usable state, but
- * may require more setup outside this function.
- */
-void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET);
-
-/**
- * @brief	Sets up the PHY link clock divider and PHY address
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	div			: Divider value, may vary per chip
- * @param	addr		: PHY address, used with MII read and write
- * @return	Nothing
- */
-void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr);
-
-/**
- * @brief	De-initialize the ethernet interface
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Nothing
- */
-void IP_ENET_DeInit(IP_ENET_001_Type *LPC_ENET);
-
-/**
- * @brief	Starts a PHY write via the MII
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	reg			: PHY register to write
- * @param	data		: Data to write to PHY register
- * @return	Nothing
- * Start a PHY write operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when write is complete.
- */
-void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data);
-
-/**
- * @brief	Starts a PHY read via the MII
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	reg			: PHY register to read
- * @return	Nothing
- * Start a PHY read operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when read is complete and calling
- * IP_ENET_ReadMIIData to get the data.
- */
-void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg);
-
-/**
- * @brief	Returns MII link (PHY) busy status
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Returns true if busy, otherwise false
- */
-bool IP_ENET_IsMIIBusy(IP_ENET_001_Type *LPC_ENET);
-
-/**
- * @brief	Returns the value read from the PHY
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Read value from PHY
- */
-STATIC INLINE uint16_t IP_ENET_ReadMIIData(IP_ENET_001_Type *LPC_ENET)
-{
-	return LPC_ENET->MAC_MII_DATA;
-}
-
-/**
- * @brief	Enables or disables ethernet transmit
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	Enable		: true to enable transmit, false to disable
- * @return	Nothing
- */
-void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable);
-
-/**
- * @brief	Enables or disables ethernet packet reception
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	Enable		: true to enable receive, false to disable
- * @return	Nothing
- */
-void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable);
-
-/**
- * @brief	Sets full or half duplex for the interface
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	full		: true to selected full duplex, false for half
- * @return	Nothing
- */
-void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full);
-
-/**
- * @brief	Sets speed for the interface
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	speed100	: true to select 100Mbps mode, false for 10Mbps
- * @return	Nothing
- */
-void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100);
-
-/**
- * @brief	Configures the initial ethernet descriptors
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @param	pTXDescs	: Pointer to TX descriptor list
- * @param	pRXDescs	: Pointer to RX descriptor list
- * @return	Nothing
- */
-void IP_ENET_InitDescriptors(IP_ENET_001_Type *LPC_ENET,
-							 IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs);
-
-/**
- * @brief	Starts receive polling of RX descriptors
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Nothing
- */
-STATIC INLINE void IP_ENET_RXStart(IP_ENET_001_Type *LPC_ENET)
-{
-	/* Start receive polling */
-	LPC_ENET->DMA_REC_POLL_DEMAND = 1;
-}
-
-/**
- * @brief	Starts transmit polling of TX descriptors
- * @param	LPC_ENET	: Pointer to selected ENET peripheral
- * @return	Nothing
- */
-STATIC INLINE void IP_ENET_TXStart(IP_ENET_001_Type *LPC_ENET)
-{
-	/* Start transmit polling */
-	LPC_ENET->DMA_TRANS_POLL_DEMAND = 1;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ENET_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/fpu_init.c b/bsp/xplorer4330/libraries/lpc_ip/fpu_init.c
deleted file mode 100644
index b88d19977b..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/fpu_init.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * @brief FPU init code
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#if defined(CORE_M4)
-
-#include "stdint.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-#define LPC_CPACR           0xE000ED88
-
-#define SCB_MVFR0           0xE000EF40
-#define SCB_MVFR0_RESET     0x10110021
-
-#define SCB_MVFR1           0xE000EF44
-#define SCB_MVFR1_RESET     0x11000011
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Early initialization of the FPU */
-void fpuInit(void)
-{
-	// from arm trm manual:
-	//                ; CPACR is located at address 0xE000ED88
-	//                LDR.W R0, =0xE000ED88
-	//                ; Read CPACR
-	//                LDR R1, [R0]
-	//                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
-	//                ORR R1, R1, #(0xF << 20)
-	//                ; Write back the modified value to the CPACR
-	//                STR R1, [R0]
-
-	volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
-	volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
-	volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
-	volatile uint32_t Cpacr;
-	volatile uint32_t Mvfr0;
-	volatile uint32_t Mvfr1;
-	char vfpPresent = 0;
-
-	Mvfr0 = *regMvfr0;
-	Mvfr1 = *regMvfr1;
-
-	vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
-
-	if (vfpPresent) {
-		Cpacr = *regCpacr;
-		Cpacr |= (0xF << 20);
-		*regCpacr = Cpacr;	// enable CP10 and CP11 for full access
-	}
-
-}
-
-#endif /* defined(CORE_M4 */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/fpu_init.h b/bsp/xplorer4330/libraries/lpc_ip/fpu_init.h
deleted file mode 100644
index 6daa63570c..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/fpu_init.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * @brief FPU init code
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __FPU_INIT_H_
-#define __FPU_INIT_H_
-
-#if defined(CORE_M4)
-
-/**
- * @defgroup IP_FPU_CMX_001 IP: FPU initialization
- * @ingroup IP_Drivers
- * Cortex FPU initialization
- * @{
- */
-
-/**
- * @brief	Early initialization of the FPU
- * @return	Nothing
- */
-void fpuInit(void);
-
-/**
- * @}
- */
-
-#endif /* #if defined */
-
-#endif /* __FPU_INIT_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gima_001.h b/bsp/xplorer4330/libraries/lpc_ip/gima_001.h
deleted file mode 100644
index 1dc52fb2f8..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gima_001.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * @brief Global Input Multiplexer Array control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GIMA_001_H_
-#define __GIMA_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GIMA_001 IP: GIMA register block and driver
- * @ingroup IP_Drivers
- * Global Input Multiplexer Array
- * @{
- */
-
-/**
- * @brief Global Input Multiplexer Array (GIMA) register block structure
- */
-typedef struct {						/*!< GIMA Structure */
-	__IO uint32_t  CAP0_IN[4][4];		/*!< Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
-	__IO uint32_t  CTIN_IN[8];			/*!< SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
-	__IO uint32_t  VADC_TRIGGER_IN;		/*!< VADC trigger input multiplexer (GIMA output 24) */
-	__IO uint32_t  EVENTROUTER_13_IN;	/*!< Event router input 13 multiplexer (GIMA output 25) */
-	__IO uint32_t  EVENTROUTER_14_IN;	/*!< Event router input 14 multiplexer (GIMA output 26) */
-	__IO uint32_t  EVENTROUTER_16_IN;	/*!< Event router input 16 multiplexer (GIMA output 27) */
-	__IO uint32_t  ADCSTART0_IN;		/*!< ADC start0 input multiplexer (GIMA output 28) */
-	__IO uint32_t  ADCSTART1_IN;		/*!< ADC start1 input multiplexer (GIMA output 29) */
-} IP_GIMA_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GIMA_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c
deleted file mode 100644
index f72f45d27b..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * @brief GPDMA Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpdma_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the GPDMA */
-void IP_GPDMA_Init(IP_GPDMA_001_Type *pGPDMA) {
-	uint8_t i;
-	/* Reset all channel configuration register */
-	for (i = 8; i > 0; i--) {
-		pGPDMA->CH[i - 1].CONFIG = 0;
-	}
-
-	/* Clear all DMA interrupt and error flag */
-	pGPDMA->INTTCCLEAR = 0xFF;
-	pGPDMA->INTERRCLR = 0xFF;
-}
-
-/* Read the status from different registers according to the type */
-IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_Type *pGPDMA, GPDMA_Status_Type type, uint8_t channel) {
-	/**
-	 * TODO check the channel <=8 type is esxited
-	 */
-	switch (type) {
-	case GPDMA_STAT_INT:/* check status of DMA channel interrupts */
-		return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF)));
-
-	case GPDMA_STAT_INTTC:	/* check terminal count interrupt request status for DMA */
-		return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF)));
-
-	case GPDMA_STAT_INTERR:	/* check interrupt status for DMA channels */
-		return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF)));
-
-	case GPDMA_STAT_RAWINTTC:	/* check status of the terminal count interrupt for DMA channels */
-		return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF)));
-
-	case GPDMA_STAT_RAWINTERR:	/* check status of the error interrupt for DMA channels */
-		return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF)));
-
-	default:/* check enable status for DMA channels */
-		return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF)));
-	}
-}
-
-/* Clear the Interrupt Flag from different registers according to the type */
-void IP_GPDMA_ClearIntPending(IP_GPDMA_001_Type *pGPDMA, GPDMA_StateClear_Type type, uint8_t channel) {
-	if (type == GPDMA_STATCLR_INTTC) {
-		/* clears the terminal count interrupt request on DMA channel */
-		pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF));
-	}
-	else {
-		/* clear the error interrupt request */
-		pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF));
-	}
-}
-
-/* Enable or Disable the GPDMA Channel */
-void IP_GPDMA_ChannelCmd(IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState) {
-	IP_GPDMA_001_CH_Type *pDMAch;
-
-	/* Get Channel pointer */
-	pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[channelNum]);
-
-	if (NewState == ENABLE) {
-		pDMAch->CONFIG |= GPDMA_DMACCxConfig_E;
-	}
-	else {
-		pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E;
-	}
-}
-
-/* Set up the DPDMA according to the specification configuration details */
-Status IP_GPDMA_Setup(IP_GPDMA_001_Type *pGPDMA,
-					  GPDMA_Channel_CFG_Type *GPDMAChannelConfig,
-					  uint32_t GPDMA_LUTPerBurstSrcConn,
-					  uint32_t GPDMA_LUTPerBurstDstConn,
-					  uint32_t GPDMA_LUTPerWidSrcConn,
-					  uint32_t GPDMA_LUTPerWidDstConn,
-					  uint32_t GPDMA_LUTPerAddrSrcConn,
-					  uint32_t GPDMA_LUTPerAddrDstConn,
-					  uint8_t SrcPeripheral,
-					  uint8_t DstPeripheral)
-{
-	IP_GPDMA_001_CH_Type *pDMAch;
-
-	if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) {
-		/* This channel is enabled, return ERROR, need to release this channel first */
-		return ERROR;
-	}
-
-	/* Get Channel pointer */
-	pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]);
-
-	/* Reset the Interrupt status */
-	pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
-	pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
-
-	/* Assign Linker List Item value */
-	pDMAch->LLI = 0;/* Fixed to 0 (no link list) */
-
-	/* Enable DMA channels, little endian */
-	pGPDMA->CONFIG = GPDMA_DMACConfig_E;
-	while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {}
-
-	pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr;
-	pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr;
-
-	/* Configure DMA Channel, enable Error Counter and Terminate counter */
-	pDMAch->CONFIG = GPDMA_DMACCxConfig_IE
-					 | GPDMA_DMACCxConfig_ITC		/*| GPDMA_DMACCxConfig_E*/
-					 | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType)
-					 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
-					 | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);
-
-	switch (GPDMAChannelConfig->TransferType) {
-	/* Memory to memory */
-	case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
-		pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize)
-						  | GPDMA_DMACCxControl_SBSize((4UL))		/**< Burst size = 32 */
-						  | GPDMA_DMACCxControl_DBSize((4UL))		/**< Burst size = 32 */
-						  | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth)
-						  | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth)
-						  | GPDMA_DMACCxControl_SI
-						  | GPDMA_DMACCxControl_DI
-						  | GPDMA_DMACCxControl_I;
-		break;
-
-	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
-	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
-		pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
-						  | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn)
-						  | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
-						  | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn)
-						  | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
-						  | GPDMA_DMACCxControl_DestTransUseAHBMaster1
-						  | GPDMA_DMACCxControl_SI
-						  | GPDMA_DMACCxControl_I;
-		break;
-
-	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
-	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
-		pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
-						  | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
-						  | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn)
-						  | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
-						  | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn)
-						  | GPDMA_DMACCxControl_SrcTransUseAHBMaster1
-						  | GPDMA_DMACCxControl_DI
-						  | GPDMA_DMACCxControl_I;
-		break;
-
-	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
-	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
-	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
-		pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
-						  | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
-						  | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
-						  | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
-						  | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
-						  | GPDMA_DMACCxControl_SrcTransUseAHBMaster1
-						  | GPDMA_DMACCxControl_DestTransUseAHBMaster1
-						  | GPDMA_DMACCxControl_I;
-
-		break;
-
-	/* Do not support any more transfer type, return ERROR */
-	default:
-		return ERROR;
-	}
-
-	return SUCCESS;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h
deleted file mode 100644
index 34b3d787ec..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * @brief GPDMA Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPDMA_001_H_
-#define __GPDMA_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPDMA_001 IP: GPDMA register block and driver
- * @ingroup IP_Drivers
- * General Purpose DMA
- * @{
- */
-
-/**
- * @brief GPDMA Channel register block structure
- */
-typedef struct {
-	__IO uint32_t  SRCADDR;				/*!< DMA Channel Source Address Register */
-	__IO uint32_t  DESTADDR;			/*!< DMA Channel Destination Address Register */
-	__IO uint32_t  LLI;					/*!< DMA Channel Linked List Item Register */
-	__IO uint32_t  CONTROL;				/*!< DMA Channel Control Register */
-	__IO uint32_t  CONFIG;				/*!< DMA Channel Configuration Register */
-	__I  uint32_t  RESERVED1[3];
-} IP_GPDMA_001_CH_Type;
-
-#define GPDMA_CHANNELS 8
-
-/**
- * @brief GPDMA register block
- */
-typedef struct {						/*!< GPDMA Structure */
-	__I  uint32_t  INTSTAT;				/*!< DMA Interrupt Status Register */
-	__I  uint32_t  INTTCSTAT;			/*!< DMA Interrupt Terminal Count Request Status Register */
-	__O  uint32_t  INTTCCLEAR;			/*!< DMA Interrupt Terminal Count Request Clear Register */
-	__I  uint32_t  INTERRSTAT;			/*!< DMA Interrupt Error Status Register */
-	__O  uint32_t  INTERRCLR;			/*!< DMA Interrupt Error Clear Register */
-	__I  uint32_t  RAWINTTCSTAT;		/*!< DMA Raw Interrupt Terminal Count Status Register */
-	__I  uint32_t  RAWINTERRSTAT;		/*!< DMA Raw Error Interrupt Status Register */
-	__I  uint32_t  ENBLDCHNS;			/*!< DMA Enabled Channel Register */
-	__IO uint32_t  SOFTBREQ;			/*!< DMA Software Burst Request Register */
-	__IO uint32_t  SOFTSREQ;			/*!< DMA Software Single Request Register */
-	__IO uint32_t  SOFTLBREQ;			/*!< DMA Software Last Burst Request Register */
-	__IO uint32_t  SOFTLSREQ;			/*!< DMA Software Last Single Request Register */
-	__IO uint32_t  CONFIG;				/*!< DMA Configuration Register */
-	__IO uint32_t  SYNC;				/*!< DMA Synchronization Register */
-	__I  uint32_t  RESERVED0[50];
-	IP_GPDMA_001_CH_Type CH[GPDMA_CHANNELS];
-} IP_GPDMA_001_Type;
-
-/**
- * @brief Macro defines for DMA channel control registers
- */
-#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))	/**< Transfer size*/
-#define GPDMA_DMACCxControl_SBSize(n)       (((n & 0x07) << 12))	/**< Source burst size*/
-#define GPDMA_DMACCxControl_DBSize(n)       (((n & 0x07) << 15))	/**< Destination burst size*/
-#define GPDMA_DMACCxControl_SWidth(n)       (((n & 0x07) << 18))	/**< Source transfer width*/
-#define GPDMA_DMACCxControl_DWidth(n)       (((n & 0x07) << 21))	/**< Destination transfer width*/
-#define GPDMA_DMACCxControl_SI              ((1UL << 26))			/**< Source increment*/
-#define GPDMA_DMACCxControl_DI              ((1UL << 27))			/**< Destination increment*/
-#if defined(CHIP_LPC43XX) || defined(CHIP_LPC18XX)
-#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1   ((1UL << 24))	/**< Source AHB master select in 18xx43xx*/
-#define GPDMA_DMACCxControl_DestTransUseAHBMaster1  ((1UL << 25))	/**< Destination AHB master select in 18xx43xx*/
-#else
-#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1   0
-#define GPDMA_DMACCxControl_DestTransUseAHBMaster1  0
-#endif
-#define GPDMA_DMACCxControl_Prot1           ((1UL << 28))			/**< Indicates that the access is in user mode or privileged mode*/
-#define GPDMA_DMACCxControl_Prot2           ((1UL << 29))			/**< Indicates that the access is bufferable or not bufferable*/
-#define GPDMA_DMACCxControl_Prot3           ((1UL << 30))			/**< Indicates that the access is cacheable or not cacheable*/
-#define GPDMA_DMACCxControl_I               ((1UL << 31))			/**< Terminal count interrupt enable bit */
-
-/**
- * @brief Macro defines for DMA Configuration register
- */
-#define GPDMA_DMACConfig_E              ((0x01))	/**< DMA Controller enable*/
-#define GPDMA_DMACConfig_M              ((0x02))	/**< AHB Master endianness configuration*/
-#define GPDMA_DMACConfig_BITMASK        ((0x03))
-
-/**
- * @brief Macro defines for DMA Channel Configuration registers
- */
-#define GPDMA_DMACCxConfig_E                    ((1UL << 0))			/**< DMA control enable*/
-#define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n & 0x1F) << 1))		/**< Source peripheral*/
-#define GPDMA_DMACCxConfig_DestPeripheral(n)    (((n & 0x1F) << 6))		/**< Destination peripheral*/
-#define GPDMA_DMACCxConfig_TransferType(n)      (((n & 0x7) << 11))		/**< This value indicates the type of transfer*/
-#define GPDMA_DMACCxConfig_IE                   ((1UL << 14))			/**< Interrupt error mask*/
-#define GPDMA_DMACCxConfig_ITC                  ((1UL << 15))			/**< Terminal count interrupt mask*/
-#define GPDMA_DMACCxConfig_L                    ((1UL << 16))			/**< Lock*/
-#define GPDMA_DMACCxConfig_A                    ((1UL << 17))			/**< Active*/
-#define GPDMA_DMACCxConfig_H                    ((1UL << 18))			/**< Halt*/
-
-/**
- * @brief GPDMA Interrupt Clear Status
- */
-typedef enum {
-	GPDMA_STATCLR_INTTC,	/**< GPDMA Interrupt Terminal Count Request Clear */
-	GPDMA_STATCLR_INTERR	/**< GPDMA Interrupt Error Clear */
-} GPDMA_StateClear_Type;
-
-/**
- * @brief GPDMA Type of Interrupt Status
- */
-typedef enum {
-	GPDMA_STAT_INT,			/**< GPDMA Interrupt Status */
-	GPDMA_STAT_INTTC,		/**< GPDMA Interrupt Terminal Count Request Status */
-	GPDMA_STAT_INTERR,		/**< GPDMA Interrupt Error Status */
-	GPDMA_STAT_RAWINTTC,	/**< GPDMA Raw Interrupt Terminal Count Status */
-	GPDMA_STAT_RAWINTERR,	/**< GPDMA Raw Error Interrupt Status */
-	GPDMA_STAT_ENABLED_CH	/**< GPDMA Enabled Channel Status */
-} GPDMA_Status_Type;
-
-/**
- * @brief GPDMA Type of DMA controller
- */
-typedef enum {
-	GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA              = ((0UL)),	/**< Memory to memory - DMA control */
-	GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA              = ((1UL)),	/**< Memory to peripheral - DMA control */
-	GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA              = ((2UL)),	/**< Peripheral to memory - DMA control */
-	GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA              = ((3UL)),	/**< Source peripheral to destination peripheral - DMA control */
-	GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL   = ((4UL)),	/**< Source peripheral to destination peripheral - destination peripheral control */
-	GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL       = ((5UL)),	/**< Memory to peripheral - peripheral control */
-	GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL       = ((6UL)),	/**< Peripheral to memory - peripheral control */
-	GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL    = ((7UL))	/**< Source peripheral to destination peripheral - source peripheral control */
-} FlowControlType;
-
-/**
- * @brief GPDMA structure using for DMA configuration
- */
-typedef struct {
-	uint32_t ChannelNum;	/**< DMA channel number, should be in
-							 *  range from 0 to 7.
-							 *  Note: DMA channel 0 has the highest priority
-							 *  and DMA channel 7 the lowest priority.
-							 */
-	uint32_t TransferSize;	/**< Length/Size of transfer */
-	uint32_t TransferWidth;	/**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
-	uint32_t SrcAddr;	/**< Physical Source Address, used in case TransferType is chosen as
-						 *       GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
-	uint32_t DstAddr;	/**< Physical Destination Address, used in case TransferType is chosen as
-						 *       GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
-	uint32_t TransferType;	/**< Transfer Type, should be one of the following:
-							 * - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
-							 * - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
-							 * - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
-							 * - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
-							 */
-} GPDMA_Channel_CFG_Type;
-
-/**
- * @brief	Initialize the GPDMA
- * @param	pGPDMA	: The Base Address of GPDMA on the chip
- * @return	Nothing
- */
-void IP_GPDMA_Init(IP_GPDMA_001_Type *pGPDMA);
-
-/**
- * @brief	Set up the DPDMA according to the specification configuration details
- * @param	pGPDMA						: The Base Address of GPDMA on the chip
- * @param	GPDMAChannelConfig			: Configuration struct
- * @param	GPDMA_LUTPerBurstSrcConn	: Peripheral Source burst size
- * @param	GPDMA_LUTPerBurstDstConn	: Peripheral Destination burst size
- * @param	GPDMA_LUTPerWidSrcConn		: Peripheral Source transfer width
- * @param	GPDMA_LUTPerWidDstConn		: Peripheral Destination transfer width
- * @param	GPDMA_LUTPerAddrSrcConn		: Peripheral Source Address
- * @param	GPDMA_LUTPerAddrDstConn		: Peripheral Destination Address
- * @param	SrcPeripheral				: Peripheral Source ID
- * @param	DstPeripheral				: Peripheral Destination ID
- * @return	SUCCESS or ERROR on setup failure
- */
-Status IP_GPDMA_Setup(IP_GPDMA_001_Type *pGPDMA,
-					  GPDMA_Channel_CFG_Type *GPDMAChannelConfig,
-					  uint32_t GPDMA_LUTPerBurstSrcConn,
-					  uint32_t GPDMA_LUTPerBurstDstConn,
-					  uint32_t GPDMA_LUTPerWidSrcConn,
-					  uint32_t GPDMA_LUTPerWidDstConn,
-					  uint32_t GPDMA_LUTPerAddrSrcConn,
-					  uint32_t GPDMA_LUTPerAddrDstConn,
-					  uint8_t  SrcPeripheral,
-					  uint8_t  DstPeripheral);
-
-/**
- * @brief	Read the status from different registers according to the type
- * @param	pGPDMA		: The Base Address of GPDMA on the chip
- * @param	type		: Status mode, should be:
- *							- GPDMA_STAT_INT		: GPDMA Interrupt Status
- *							- GPDMA_STAT_INTTC		: GPDMA Interrupt Terminal Count Request Status
- *							- GPDMA_STAT_INTERR		: GPDMA Interrupt Error Status
- *							- GPDMA_STAT_RAWINTTC	: GPDMA Raw Interrupt Terminal Count Status
- *							- GPDMA_STAT_RAWINTERR	: GPDMA Raw Error Interrupt Status
- *							- GPDMA_STAT_ENABLED_CH	: GPDMA Enabled Channel Status
- * @param	channel		: The GPDMA channel : 0 - 7
- * @return	SET is interrupt is pending or RESET if not pending
- */
-IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_Type *pGPDMA, GPDMA_Status_Type type, uint8_t channel);
-
-/**
- * @brief	Clear the Interrupt Flag from different registers according to the type
- * @param	pGPDMA	: The Base Address of GPDMA on the chip
- * @param	type	: Flag mode, should be:
- *						- GPDMA_STATCLR_INTTC	: GPDMA Interrupt Terminal Count Request
- *						- GPDMA_STATCLR_INTERR	: GPDMA Interrupt Error
- * @param	channel	: The GPDMA channel : 0 - 7
- * @return	Nothing
- */
-void IP_GPDMA_ClearIntPending(IP_GPDMA_001_Type *pGPDMA, GPDMA_StateClear_Type type, uint8_t channel);
-
-/**
- * @brief	Enable or Disable the GPDMA Channel
- * @param	pGPDMA		: The Base Address of GPDMA on the chip
- * @param	channelNum	: The GPDMA channel : 0 - 7
- * @param	NewState	: ENABLE to enable GPDMA or DISABLE to disable GPDMA
- * @return	Nothing
- */
-void IP_GPDMA_ChannelCmd(IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPDMA_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpio_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpio_001.h
deleted file mode 100644
index 19f9fbac10..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpio_001.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * @brief GPIO Registers and Functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIO_001_H_
-#define __GPIO_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPIO_ADC_001 IP: GPIO register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-#define GPIO_PORT_BITS 32
-
-#if defined(CHIP_LPC11UXX)
-#define GPIO_PORT_COUNT 2
-#endif
-
-#if defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-#define GPIO_PORT_COUNT 6
-#endif
-
-/**
- * @brief  GPIO port register block structure
- */
-typedef struct {										/*!< GPIO_PORT Structure    */
-	__IO uint8_t B[GPIO_PORT_COUNT][32];				/*!< Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
-	__I  uint8_t RESERVED0[4096 - (GPIO_PORT_COUNT * 32 * sizeof(uint8_t))];
-	__IO uint32_t W[GPIO_PORT_COUNT][32];				/*!< Word pin registers port 0 to 5 */
-	__I  uint8_t  RESERVED1[4096 - (GPIO_PORT_COUNT * 32 * sizeof(uint32_t))];
-	__IO uint32_t DIR[GPIO_PORT_COUNT];					/*!< Direction registers port n */
-	__I  uint32_t  RESERVED2[32 - GPIO_PORT_COUNT];
-	__IO uint32_t MASK[GPIO_PORT_COUNT];				/*!< Mask register port n   */
-	__I  uint32_t  RESERVED3[32 - GPIO_PORT_COUNT];
-	__IO uint32_t PIN[GPIO_PORT_COUNT];					/*!< Portpin register port n */
-	__I  uint32_t  RESERVED4[32 - GPIO_PORT_COUNT];
-	__IO uint32_t MPIN[GPIO_PORT_COUNT];				/*!< Masked port register port n */
-	__I  uint32_t  RESERVED5[32 - GPIO_PORT_COUNT];
-	__IO uint32_t SET[GPIO_PORT_COUNT];					/*!< Write: Set register for port n Read: output bits for port n */
-	__I  uint32_t  RESERVED6[32 - GPIO_PORT_COUNT];
-	__O  uint32_t CLR[GPIO_PORT_COUNT];					/*!< Clear port n           */
-	__I  uint32_t  RESERVED7[32 - GPIO_PORT_COUNT];
-	__O  uint32_t NOT[GPIO_PORT_COUNT];					/*!< Toggle port n          */
-} IP_GPIO_001_Type;
-
-/**
- * @brief	Initialize GPIO block
- * @param	pGPIO	: The Base Address of the GPIO block
- * @return	Nothing
- */
-STATIC INLINE void IP_GPIO_Init(IP_GPIO_001_Type *pGPIO)
-{}
-
-/**
- * @brief	Set a GPIO port/bit state
- * @param	pGPIO	: The Base Address of the GPIO block
- * @param	Port	: GPIO port to set
- * @param	Bit		: GPIO bit to set
- * @param	Setting	: true for high, false for low
- * @return	Nothing
- */
-STATIC INLINE void IP_GPIO_WritePortBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit, bool Setting)
-{
-	pGPIO->B[Port][Bit] = Setting;
-}
-
-/**
- * @brief	Seta GPIO direction
- * @param	pGPIO	: The Base Address of the GPIO block
- * @param	Port	: GPIO port to set
- * @param	Bit		: GPIO bit to set
- * @param	Setting	: true for output, false for input
- * @return	Nothing
- */
-STATIC INLINE void IP_GPIO_WriteDirBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit, bool Setting)
-{
-	if (Setting) {
-		pGPIO->DIR[Port] |= 1UL << Bit;
-	}
-	else {
-		pGPIO->DIR[Port] &= ~(1UL << Bit);
-	}
-}
-
-/**
- * @brief	Read a GPIO state
- * @param	pGPIO	: The Base Address of the GPIO block
- * @param	Port	: GPIO port to read
- * @param	Bit		: GPIO bit to read
- * @return	true of the GPIO is high, false if low
- */
-STATIC INLINE bool IP_GPIO_ReadPortBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit)
-{
-	return (bool) pGPIO->B[Port][Bit];
-}
-
-/**
- * @brief	Read a GPIO direction (out ot in)
- * @param	pGPIO	: The Base Address of the GPIO block
- * @param	Port	: GPIO port to read
- * @param	Bit		: GPIO bit to read
- * @return	true of the GPIO is an output, false if input
- */
-STATIC INLINE bool IP_GPIO_ReadDirBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit)
-{
-	return (bool) (((pGPIO->DIR[Port]) >> Bit) & 1);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIO_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.c
deleted file mode 100644
index 9dba508c80..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
-* @brief GPIO Group Interrupt Registers and control functions
-*
-* @note
-* Copyright(C) NXP Semiconductors, 2012
-* All rights reserved.
-*
-* @par
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* LPC products.  This software is supplied "AS IS" without any warranties of
-* any kind, and NXP Semiconductors and its licensor disclaim any and 
-* all warranties, express or implied, including all implied warranties of 
-* merchantability, fitness for a particular purpose and non-infringement of 
-* intellectual property rights.  NXP Semiconductors assumes no responsibility
-* or liability for the use of the software, conveys no license or rights under any
-* patent, copyright, mask work right, or any other intellectual property rights in 
-* or to any products. NXP Semiconductors reserves the right to make changes
-* in the software without notification. NXP Semiconductors also makes no 
-* representation or warranty that such application will be suitable for the
-* specified use without further testing or modification.
-* 
-* @par
-* Permission to use, copy, modify, and distribute this software and its 
-* documentation is hereby granted, under NXP Semiconductors' and its 
-* licensor's relevant copyrights in the software, without fee, provided that it 
-* is used in conjunction with NXP Semiconductors microcontrollers.  This 
-* copyright, permission, and disclaimer notice must appear in all copies of 
-* this code.
-*/
-
-#include "gpiogrpint_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* GPIO Group Interrupt Pin Add to Group */
-void IP_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum, bool ActiveMode)
-{
-	volatile uint32_t wordDat;
-        bool pinstate;
-
-	/* configure to PORT_ENA register */
-	pGPIOGPINT->PORT_ENA[PortNum] |= (1<<PinNum);
-
-	/* configure to PORT_POL */
-	wordDat = pGPIOGPINT->PORT_POL[PortNum];
-        pinstate = (bool) (((wordDat>>PinNum)&0x01) != 0);
-	if (pinstate != ActiveMode) {
-		if (ActiveMode == true) { /* active HIGH */
-			wordDat |= (1<<PinNum);
-		} else { /* active LOW */
-			wordDat &= ~(1<<PinNum);
-		}
-		pGPIOGPINT->PORT_POL[PortNum] = wordDat;		
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.h
deleted file mode 100644
index de09fa52c4..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * @brief GPIO Group Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIOGRPINT_001_H_
-#define __GPIOGRPINT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIOGRPINT_001 IP: GPIO Grouped Interrupts register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO grouped interrupt register block structure
- */
-typedef struct {					/*!< GPIO_GROUP_INTn Structure */
-	__IO uint32_t  CTRL;			/*!< GPIO grouped interrupt control register */
-	__I  uint32_t  RESERVED0[7];
-	__IO uint32_t  PORT_POL[8];		/*!< GPIO grouped interrupt port polarity register */
-	__IO uint32_t  PORT_ENA[8];		/*!< GPIO grouped interrupt port m enable register */
-} IP_GPIOGROUPINT_001_Type;
-
-/**
- * @brief	GPIO Group Interrupt Pin Initialization
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @param	PortComb	: GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)
- * @param	PortTrigger	: GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)
- * @return	None
- */
-STATIC INLINE void IP_GPIOGP_IntInit(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)
-{
-	pGPIOGPINT->CTRL = ((PortTrigger & 0x1) << 2) | ((PortComb & 0x1) << 1);
-}
-
-/**
- * @brief	GPIO Group Interrupt Pin Add to Group
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @param	PortNum		: GPIO port number, should be 0 to 7
- * @param	PinNum		: GPIO pin number, should be 0 to 31
- * @param	ActiveMode	: GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)
- * @return	None
- */
-void IP_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum, bool ActiveMode);
-
-/**
- * @brief	GPIO Group Interrupt Pin Remove from Group
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @param	PortNum		: GPIO port number, should be 0 to 7
- * @param	PinNum		: GPIO pin number, should be 0 to 31
- * @return	None
- */
-STATIC INLINE void IP_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)
-{
-	/* configure to PORT_ENA register */
-	pGPIOGPINT->PORT_ENA[PortNum] &= ~(1 << PinNum);
-}
-
-/**
- * @brief	Get GPIO Group Interrupt Get Status
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @return	true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool IP_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
-{
-	return (bool) (pGPIOGPINT->CTRL & 0x01);
-}
-
-/**
- * @brief	Clear GPIO Group Interrupt
- * @param	pGPIOGPINT	: Pointer to GPIOIR register block
- * @return	None
- */
-STATIC INLINE void IP_GPIOGP_IntClear(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
-{
-	pGPIOGPINT->CTRL |= 0x01;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIOGRPINT_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.c
deleted file mode 100644
index 86c6e5f611..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * @brief GPIO Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpioint_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Enable GPIO Interrupt */
-void IP_GPIOINT_IntCmd(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue, Gpio_Int_Mode_Enum IntMode)
-{
-	if (PortNum == 0) {
-		if (IntMode == IP_GPIOINT_RISING_EDGE) {
-			pGPIOPININT->EnR0 = BitValue;
-		}
-		else {
-			pGPIOPININT->EnF0 = BitValue;
-		}
-	}
-	else if (PortNum == 2) {
-		if (IntMode == IP_GPIOINT_RISING_EDGE) {
-			pGPIOPININT->EnR2 = BitValue;
-		}
-		else {
-			pGPIOPININT->EnF2 = BitValue;
-		}
-	}
-}
-
-/*Get GPIO Interrupt Status */
-bool IP_GPIOINT_IntGetStatus(IP_GPIOINT_001_Type *pGPIOPININT,
-							 uint8_t PortNum,
-							 uint32_t PinNum,
-							 Gpio_Int_Mode_Enum IntMode)
-{
-	if (PortNum == 0) {
-		if (IntMode == IP_GPIOINT_RISING_EDGE) {
-			return (bool) ((pGPIOPININT->StatR0 >> PinNum) & 0x1);
-		}
-		else {
-			return (bool) ((pGPIOPININT->StatF0 >> PinNum) & 0x1);
-		}
-	}
-	else if (PortNum == 2) {
-		if (IntMode == IP_GPIOINT_RISING_EDGE) {
-			return (bool) ((pGPIOPININT->StatR2 >> PinNum) & 0x1);
-		}
-		else {
-			return (bool) ((pGPIOPININT->StatF2 >> PinNum) & 0x1);
-		}
-	}
-
-	return false;
-}
-
-/**
- * @brief	Clear GPIO Interrupt (Edge interrupt cases only)
- * @param	PortNum		: GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param	BitValue	: GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF
- * @return	None
- */
-void IP_GPIOINT_IntClear(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue)
-{
-	if (PortNum == 0) {
-		pGPIOPININT->Clr0 = BitValue;
-	}
-	else if (PortNum == 2) {
-		pGPIOPININT->Clr2 = BitValue;
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.h
deleted file mode 100644
index de939c0b17..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * @brief GPIO Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIOINT_001_H_
-#define __GPIOINT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIOINT_001 IP: GPIO Interrupt register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO Interrupt register block structure
- */
-typedef struct {
-	__I  uint32_t Status;		/*!< GPIO overall Interrupt Status Register */
-	__I  uint32_t StatR0;		/*!< GPIO Interrupt Status Register 0 for Rising edge */
-	__I  uint32_t StatF0;		/*!< GPIO Interrupt Status Register 0 for Falling edge */
-	__O  uint32_t Clr0;			/*!< GPIO Interrupt Clear  Register 0 */
-	__IO uint32_t EnR0;			/*!< GPIO Interrupt Enable Register 0 for Rising edge */
-	__IO uint32_t EnF0;			/*!< GPIO Interrupt Enable Register 0 for Falling edge */
-	uint32_t RESERVED0[3];
-	__I  uint32_t StatR2;		/*!< GPIO Interrupt Status Register 2 for Rising edge */
-	__I  uint32_t StatF2;		/*!< GPIO Interrupt Status Register 2 for Falling edge */
-	__O  uint32_t Clr2;			/*!< GPIO Interrupt Clear  Register 2 */
-	__IO uint32_t EnR2;			/*!< GPIO Interrupt Enable Register 2 for Rising edge */
-	__IO uint32_t EnF2;			/*!< GPIO Interrupt Enable Register 2 for Falling edge */
-} IP_GPIOINT_001_Type;
-
-typedef enum {
-	IP_GPIOINT_RISING_EDGE = 0x01,
-	IP_GPIOINT_FALLING_EDGE = 0x02
-} Gpio_Int_Mode_Enum;
-
-/**
- * @brief	Enable GPIO Interrupt
- * @param	pGPIOPININT	: Pointer to GPIO interrupt register block
- * @param	PortNum		: GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param	BitValue	: GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF
- * @param	IntMode		: Interrupt mode, 0 = rising edge, 1 = falling edge
- * @return	None
- */
-void IP_GPIOINT_IntCmd(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue, Gpio_Int_Mode_Enum IntMode);
-
-/**
- * @brief	Get GPIO Interrupt Status
- * @param	pGPIOPININT	: Pointer to GPIO interrupt register block
- * @param	PortNum		: GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param	PinNum		: Pin number, should be: 0..30(with port 0) and 0..13 (with port 2)
- * @param	IntMode		: Interrupt mode, 0 = rising edge, 1 = falling edge
- * @return	true if interrupt is pending, otherwise false
- */
-bool IP_GPIOINT_IntGetStatus(IP_GPIOINT_001_Type *pGPIOPININT,
-							 uint8_t PortNum,
-							 uint32_t PinNum,
-							 Gpio_Int_Mode_Enum IntMode);
-
-/**
- * @brief	Clear GPIO Interrupt (Edge interrupt cases only)
- * @param	pGPIOPININT	: Pointer to GPIO interrupt register block
- * @param	PortNum		: GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param	BitValue	: GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF
- * @return	None
- */
-void IP_GPIOINT_IntClear(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIOINT_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.c
deleted file mode 100644
index dc48c2d5da..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * @brief GPIO Pin Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpiopinint_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Enable GPIO Interrupt */
-void IP_GPIOPININT_IntCmd(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum, Gpio_PinInt_Mode_Enum IntMode)
-{
-	if (IntMode == IP_GPIOPININT_RISING_EDGE) {
-		pGPIOPININT->ISEL &= ~(1 << PortNum);
-		pGPIOPININT->IENR |= (1 << PortNum);
-	}
-	else if (IntMode == IP_GPIOPININT_FALLING_EDGE) {
-		pGPIOPININT->ISEL &= ~(1 << PortNum);
-		pGPIOPININT->IENF |= (1 << PortNum);
-	}
-	else if (IntMode == IP_GPIOPININT_ACTIVE_HIGH_LEVEL) {
-		pGPIOPININT->ISEL |= (1 << PortNum);
-		pGPIOPININT->IENR |= (1 << PortNum);
-		pGPIOPININT->SIENF |= (1 << PortNum);
-	}
-	else {
-		pGPIOPININT->ISEL |= (1 << PortNum);
-		pGPIOPININT->IENR |= (1 << PortNum);
-		pGPIOPININT->CIENF |= (1 << PortNum);
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.h
deleted file mode 100644
index 58b626c0cf..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * @brief GPIO Pin Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIOPININT_001_H_
-#define __GPIOPININT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIOPININT_001 IP: GPIO Pin Interrupt register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO pin interrupt register block structure
- */
-typedef struct {				/*!< GPIO_PIN_INT Structure */
-	__IO uint32_t  ISEL;		/*!< Pin Interrupt Mode register */
-	__IO uint32_t  IENR;		/*!< Pin Interrupt Enable (Rising) register */
-	__O  uint32_t  SIENR;		/*!< Set Pin Interrupt Enable (Rising) register */
-	__O  uint32_t  CIENR;		/*!< Clear Pin Interrupt Enable (Rising) register */
-	__IO uint32_t  IENF;		/*!< Pin Interrupt Enable Falling Edge / Active Level register */
-	__O  uint32_t  SIENF;		/*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
-	__O  uint32_t  CIENF;		/*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
-	__IO uint32_t  RISE;		/*!< Pin Interrupt Rising Edge register */
-	__IO uint32_t  FALL;		/*!< Pin Interrupt Falling Edge register */
-	__IO uint32_t  IST;			/*!< Pin Interrupt Status register */
-} IP_GPIOPININT_001_Type;
-
-typedef enum {
-	IP_GPIOPININT_RISING_EDGE = 0x01,
-	IP_GPIOPININT_FALLING_EDGE = 0x02,
-	IP_GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
-	IP_GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
-} Gpio_PinInt_Mode_Enum;
-
-/**
- * @brief	Enable GPIO Interrupt
- * @param	pGPIOPININT : Pointer to GPIO interrupt register block
- * @param	PortNum		: GPIO port number interrupt
- * @param	IntMode		: Interrupt mode, should be:
- *							0: Rising edge interrupt mode
- *							1: Falling edge interrupt mode
- *							2: Active-High interrupt mode
- *							3: Active-Low interrupt mode
- * @return	None
- */
-void IP_GPIOPININT_IntCmd(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum, Gpio_PinInt_Mode_Enum IntMode);
-
-/**
- * @brief	Get GPIO Interrupt Status
- * @param	pGPIOPININT : Pointer to GPIO interrupt register block
- * @param	PortNum		: GPIO port number interrupt
- * @return	true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool IP_GPIOPININT_IntGetStatus(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum)
-{
-	return (bool) (((pGPIOPININT->IST) >> PortNum) & 0x01);
-}
-
-/**
- * @brief	Clear GPIO Interrupt (Edge interrupt cases only)
- * @param	pGPIOPININT : Pointer to GPIO interrupt register block
- * @param	PortNum		: GPIO port number interrupt
- * @return	None
- */
-STATIC INLINE void IP_GPIOPININT_IntClear(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum)
-{
-	if (!(pGPIOPININT->ISEL & (1 << PortNum))) {
-		pGPIOPININT->IST |= (1 << PortNum);
-	}
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIOPININT_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2c_001.c b/bsp/xplorer4330/libraries/lpc_ip/i2c_001.c
deleted file mode 100644
index d7509470b0..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/i2c_001.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * @brief	I2C driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "i2c_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* I2C device configuration structure type */
-typedef struct {
-	union {
-		I2C_M_SETUP_Type    txrx_setup_master;		/* Transmission setup */
-		I2C_S_SETUP_Type    txrx_setup_slave;		/* Transmission setup */
-	};
-
-	int32_t     dir;	/* Current direction phase, 0 - write, 1 - read */
-} I2C_CFG_T;
-
-#define BLOCKING_TIMEOUT (0x000FFFFFUL)
-#define RESTRANSMISSION_MAX (0x000000FFUL)
-
-/* I2C driver data for I2C0, I2C1 */
-static I2C_CFG_T i2cdat[3];
-
-static bool I2C_MasterComplete[3];
-static bool I2C_SlaveComplete[3];
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Generate a start condition on I2C bus (in master mode only) */
-static uint32_t IP_I2C_Start(IP_I2C_001_Type *LPC_I2C, I2C_TRANSFER_OPT_Type Opt)
-{
-	uint32_t cnt = 0;
-	/* Reset STA, STO, SI */
-	LPC_I2C->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STOC | I2C_I2CONCLR_STAC;
-
-	/* Enter to Master Transmitter mode */
-	LPC_I2C->CONSET = I2C_I2CONSET_STA;
-
-	if (Opt == I2C_TRANSFER_POLLING) {
-		/* Wait for complete */
-		while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {
-			if (++cnt > BLOCKING_TIMEOUT) {
-				return I2C_STAT_CODE_ERROR;
-			}
-		}
-	}
-
-	return LPC_I2C->STAT & I2C_STAT_CODE_BITMASK;
-}
-
-/* Generate a stop condition on I2C bus (in master mode only) */
-static Status IP_I2C_Stop(IP_I2C_001_Type *LPC_I2C, I2C_TRANSFER_OPT_Type Opt)
-{
-	uint32_t cnt = 0;
-	/* Make sure start bit is not active */
-	if (LPC_I2C->CONSET & I2C_I2CONSET_STA) {
-		LPC_I2C->CONCLR = I2C_I2CONCLR_STAC;
-	}
-
-	LPC_I2C->CONSET = I2C_I2CONSET_STO;
-
-	LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-
-	if (Opt == I2C_TRANSFER_POLLING) {
-		/* wait for stop is sent */
-		while (LPC_I2C->CONSET & I2C_I2CONSET_STO) {
-			if (LPC_I2C->CONSET & I2C_I2CONSET_SI) {
-				LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-			}
-			if (++cnt > BLOCKING_TIMEOUT) {
-				return ERROR;
-			}
-		}
-	}
-
-	return SUCCESS;
-}
-
-/* I2C send byte subroutine */
-static uint32_t IP_I2C_SendByte(IP_I2C_001_Type *LPC_I2C, uint8_t databyte)
-{
-	uint32_t CodeStatus = LPC_I2C->STAT & I2C_STAT_CODE_BITMASK;
-
-	if ((CodeStatus != I2C_I2STAT_M_TX_START) &&
-		(CodeStatus != I2C_I2STAT_M_TX_RESTART) &&
-		(CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK)  &&
-		(CodeStatus != I2C_I2STAT_M_TX_DAT_ACK)  ) {
-		return CodeStatus;
-	}
-
-	LPC_I2C->DAT = databyte & I2C_I2DAT_BITMASK;
-
-	LPC_I2C->CONSET = I2C_I2CONSET_AA;
-
-	LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-
-	return LPC_I2C->STAT & I2C_STAT_CODE_BITMASK;
-}
-
-/* I2C get byte subroutine */
-static uint32_t IP_I2C_GetByte(IP_I2C_001_Type *LPC_I2C, uint8_t *retdat, bool ack)
-{
-	*retdat = (uint8_t) (LPC_I2C->DAT & I2C_I2DAT_BITMASK);
-
-	if (ack == true) {
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-	}
-	else {
-		LPC_I2C->CONCLR = I2C_I2CONCLR_AAC;
-	}
-
-	LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-
-	return LPC_I2C->STAT & I2C_STAT_CODE_BITMASK;
-}
-
-/* Handle I2C Master states */
-static int32_t IP_I2C_MasterHanleStates(IP_I2C_001_Type *LPC_I2C,
-										uint32_t CodeStatus,
-										I2C_M_SETUP_Type *TransferCfg,
-										I2C_TRANSFER_OPT_Type Opt)
-{
-	uint8_t *txdat;
-	uint8_t *rxdat;
-	uint8_t tmp;
-	int32_t Ret = I2C_OK;
-
-	/* get buffer to send/receive */
-	txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count];
-	rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count];
-
-	switch (CodeStatus) {
-	case I2C_I2STAT_M_TX_START:
-	case I2C_I2STAT_M_TX_RESTART:
-		// case I2C_I2STAT_M_RX_START:
-		// case I2C_I2STAT_M_RX_RESTART
-		/* Send data first */
-		if (TransferCfg->tx_count < TransferCfg->tx_length) {
-			/* Send slave address + WR direction bit = 0 ----------------------------------- */
-			IP_I2C_SendByte(LPC_I2C, (TransferCfg->sl_addr7bit << 1));
-			Ret = I2C_BYTE_SENT;
-		}
-		else if (TransferCfg->rx_count  < TransferCfg->rx_length) {
-			/* Send slave address + RD direction bit = 1 ----------------------------------- */
-			IP_I2C_SendByte(LPC_I2C, ((TransferCfg->sl_addr7bit << 1) | 0x01));
-			Ret = I2C_BYTE_SENT;
-		}
-		/* Clear STA bit after the slave address is sent */
-		LPC_I2C->CONCLR = I2C_I2CONCLR_STAC;
-		break;
-
-	case I2C_I2STAT_M_TX_SLAW_ACK:
-	case I2C_I2STAT_M_TX_DAT_ACK:
-
-		if (TransferCfg->tx_count < TransferCfg->tx_length) {
-			IP_I2C_SendByte(LPC_I2C, *txdat);
-			txdat++;
-			TransferCfg->tx_count++;
-			Ret = I2C_BYTE_SENT;
-		}
-		else {
-			if (TransferCfg->rx_count >= TransferCfg->rx_length) {
-				IP_I2C_Stop(LPC_I2C, Opt);
-			}
-			Ret = I2C_SEND_END;
-
-		}
-		break;
-
-	case I2C_I2STAT_M_TX_DAT_NACK:
-		if (TransferCfg->rx_count >= TransferCfg->rx_length) {
-			IP_I2C_Stop(LPC_I2C, Opt);
-		}
-		Ret = I2C_SEND_END;
-		break;
-
-	case I2C_I2STAT_M_RX_ARB_LOST:
-	case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL:
-	case I2C_I2STAT_S_TX_ARB_LOST_M_SLA:
-		// case I2C_I2STAT_M_TX_ARB_LOST:
-		IP_I2C_Stop(LPC_I2C, Opt);
-		Ret = I2C_ERR;
-		break;
-
-	case I2C_I2STAT_M_RX_SLAR_ACK:
-		if (TransferCfg->rx_length > 1) {
-			LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		}
-		else {
-			LPC_I2C->CONCLR = I2C_I2CONCLR_AAC;
-		}
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-
-		Ret = I2C_BYTE_RECV;
-		break;
-
-	case I2C_I2STAT_M_RX_DAT_ACK:
-		if (TransferCfg->rx_count < TransferCfg->rx_length) {
-			if ((TransferCfg->rx_length > 1) && (TransferCfg->rx_count < (TransferCfg->rx_length - 2))) {
-				IP_I2C_GetByte(LPC_I2C, &tmp, true);
-				Ret = I2C_BYTE_RECV;
-
-			}
-			else {		/* the next byte is the last byte, send NACK instead */
-				IP_I2C_GetByte(LPC_I2C, &tmp, false);
-				Ret = I2C_BYTE_RECV;
-			}
-			*rxdat++ = tmp;
-
-			TransferCfg->rx_count++;
-		}
-		else {
-			IP_I2C_Stop(LPC_I2C, Opt);
-			Ret = I2C_RECV_END;
-		}
-		break;
-
-	case I2C_I2STAT_M_RX_DAT_NACK:
-		IP_I2C_GetByte(LPC_I2C, &tmp, false);
-		if (TransferCfg->rx_count < TransferCfg->rx_length) {
-			*rxdat++ = tmp;
-			TransferCfg->rx_count++;
-		}
-		IP_I2C_Stop(LPC_I2C, Opt);
-		Ret = I2C_RECV_END;
-		break;
-
-	case I2C_I2STAT_M_RX_SLAR_NACK:
-	case I2C_I2STAT_M_TX_SLAW_NACK:
-	case I2C_I2STAT_BUS_ERROR:
-		/* Send STOP condition */
-		IP_I2C_Stop(LPC_I2C, Opt);
-		Ret = I2C_ERR;
-		break;
-
-	/* No status information */
-	case I2C_I2STAT_NO_INF:
-		if ((TransferCfg->tx_count < TransferCfg->tx_length) ||
-			(TransferCfg->rx_count < TransferCfg->rx_length)) {
-			IP_I2C_Stop(LPC_I2C, Opt);
-			Ret = I2C_ERR;
-		}
-		else {
-			Ret = I2C_RECV_END;
-		}
-		break;
-
-	default:
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		break;
-	}
-
-	return Ret;
-}
-
-/* Handle I2C Master states */
-static int32_t IP_I2C_SlaveHanleStates(IP_I2C_001_Type *LPC_I2C, uint32_t CodeStatus, I2C_S_SETUP_Type *TransferCfg)
-{
-	int32_t Ret = I2C_OK;
-	uint8_t *txdat;
-	uint8_t *rxdat;
-
-	/* get buffer to send/receive */
-	txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count];
-	rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count];
-
-	switch (CodeStatus) {
-	/* Reading phase -------------------------------------------------------- */
-	/* Own SLA+R has been received, ACK has been returned */
-	case I2C_I2STAT_S_RX_SLAW_ACK:
-
-	/* General call address has been received, ACK has been returned */
-	case I2C_I2STAT_S_RX_GENCALL_ACK:
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		break;
-
-	/* Arbitration has been lost in Slave Address + R/W bit as bus Master. General Call has
-	    been received and ACK has been returned.*/
-	case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL:
-		LPC_I2C->CONSET = I2C_I2CONSET_AA | I2C_I2CONSET_STA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		break;
-
-	/* Previously addressed with own SLA;
-	 * DATA byte has been received;
-	 * ACK has been returned */
-	case I2C_I2STAT_S_RX_ARB_LOST_M_SLA:
-	case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK:
-		/*
-		 * All data bytes that over-flow the specified receive
-		 * data length, just ignore them.
-		 */
-		if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL)) {
-			*rxdat++ = (uint8_t) LPC_I2C->DAT;
-
-			TransferCfg->rx_count++;
-
-			Ret = I2C_BYTE_RECV;
-		}
-		if (TransferCfg->rx_count == (TransferCfg->rx_length) ) {
-			LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC;
-			Ret = I2C_BYTE_RECV;
-		}
-		else {
-			LPC_I2C->CONSET = I2C_I2CONSET_AA;
-			LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		}
-
-		break;
-
-	/* DATA has been received, Only the first data byte will be received with ACK.
-	 * Additional data will be received with NOT ACK. */
-	case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK:
-		if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL)) {
-			*rxdat++ = (uint8_t) LPC_I2C->DAT;
-
-			TransferCfg->rx_count++;
-
-			Ret = I2C_BYTE_RECV;
-		}
-		LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC;
-		break;
-
-	/* Writing phase -------------------------------------------------------- */
-	/* Own SLA+R has been received, ACK has been returned */
-	case I2C_I2STAT_S_TX_SLAR_ACK:
-
-	/* Data has been transmitted, ACK has been received */
-	case I2C_I2STAT_S_TX_DAT_ACK:
-		/*
-		 * All data bytes that over-flow the specified receive
-		 * data length, just ignore them.
-		 */
-		if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL)) {
-			LPC_I2C->DAT = *txdat++;
-
-			TransferCfg->tx_count++;
-
-			Ret = I2C_BYTE_SENT;
-		}
-
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		break;
-
-	/* Arbitration lost in Slave Address and R/W bit as bus Master.
-	 * Own Slave Address + Read has been received, ACK has been returned. */
-	case I2C_I2STAT_S_TX_ARB_LOST_M_SLA:
-		if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL)) {
-			LPC_I2C->DAT = *txdat++;
-
-			TransferCfg->tx_count++;
-
-			Ret = I2C_BYTE_SENT;
-		}
-		LPC_I2C->CONSET = I2C_I2CONSET_AA | I2C_I2CONSET_STA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		break;
-
-	case I2C_I2STAT_S_TX_LAST_DAT_ACK:
-	/* Data has been transmitted, NACK has been received,
-	 * that means there's no more data to send, exit now */
-	/*
-	 * Note: Don't wait for stop event since in slave transmit mode,
-	 * since there no proof lets us know when a stop signal has been received
-	 * on slave side.
-	 */
-	case I2C_I2STAT_S_TX_DAT_NACK:
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		Ret = I2C_SEND_END;
-		break;
-
-	/* Previously addressed with own SLA;
-	 * DATA byte has been received;
-	 * NOT ACK has been returned */
-	case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK:
-
-	/* DATA has been received, NOT ACK has been returned */
-	case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK:
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		Ret = I2C_RECV_END;
-		break;
-
-	/*
-	 * Note that: Return code only let us know a stop condition mixed
-	 * with a repeat start condition in the same code value.
-	 * So we should provide a time-out. In case this is really a stop
-	 * condition, this will return back after time out condition. Otherwise,
-	 * next session that is slave receive data will be completed.
-	 */
-
-	/* A Stop or a repeat start condition */
-	case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX:
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		Ret = I2C_STA_STO_RECV;
-		break;
-
-	/* No status information */
-	case I2C_I2STAT_NO_INF:
-	/* Other status must be captured */
-	default:
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC;
-		break;
-
-	}
-
-	return Ret;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the LPC_I2C peripheral */
-void IP_I2C_Init(IP_I2C_001_Type *LPC_I2C)
-{
-	/* Set I2C operation to default */
-	LPC_I2C->CONCLR = (I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC);
-}
-
-/* De-initializes the I2C peripheral registers to their default reset values */
-void IP_I2C_DeInit(IP_I2C_001_Type *LPC_I2C)
-{
-	/* Disable I2C control */
-	LPC_I2C->CONCLR = I2C_I2CONCLR_I2ENC;
-}
-
-/* Set up clock rate for I2Cx */
-void IP_I2C_SetClockRate(IP_I2C_001_Type *LPC_I2C, uint32_t SCLValue)
-{
-	LPC_I2C->SCLH = (uint32_t) (SCLValue / 2);
-	LPC_I2C->SCLL = (uint32_t) (SCLValue - LPC_I2C->SCLH);
-}
-
-/* Enable or disable I2C peripheral's operation */
-void IP_I2C_Cmd(IP_I2C_001_Type *LPC_I2C, I2C_Mode Mode,  FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		if (Mode != I2C_SLAVE_MODE) {
-			LPC_I2C->CONSET = I2C_I2CONSET_I2EN;
-		}
-		else {
-			LPC_I2C->CONSET = I2C_I2CONSET_I2EN | I2C_I2CONSET_AA;
-		}
-	}
-	else {
-		LPC_I2C->CONCLR = I2C_I2CONCLR_I2ENC;
-	}
-}
-
-/* General Master Interrupt handler for I2C peripheral */
-void IP_I2C_Interrupt_MasterHandler(IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num)
-{
-	uint32_t returnCode;
-	I2C_M_SETUP_Type *txrx_setup;
-	int32_t Ret = I2C_OK;
-
-	txrx_setup = (I2C_M_SETUP_Type *) &i2cdat[I2C_Num].txrx_setup_master;
-
-	while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {}
-
-	returnCode = (uint32_t) (LPC_I2C->STAT & I2C_STAT_CODE_BITMASK);
-
-	/* Save current status */
-	txrx_setup->status = returnCode;
-
-	Ret = IP_I2C_MasterHanleStates(LPC_I2C, returnCode, txrx_setup, I2C_TRANSFER_INTERRUPT);
-
-	if (I2C_CheckError(Ret)) {
-		if (txrx_setup->retransmissions_count < txrx_setup->retransmissions_max) {
-			/* Retry */
-			txrx_setup->retransmissions_count++;
-			txrx_setup->tx_count = 0;
-			txrx_setup->rx_count = 0;
-			/* Reset STA, STO, SI */
-			IP_I2C_Start(LPC_I2C, I2C_TRANSFER_INTERRUPT);
-			return;
-		}
-		else {
-			goto s_int_end;
-		}
-	}
-	else if (Ret & I2C_SEND_END) {
-		/* If no need to wait for data from Slave */
-		if (txrx_setup->rx_count >= (txrx_setup->rx_length)) {
-			goto s_int_end;
-		}
-		else {	/* Start to wait for data from Slave */
-			/* Reset STA, STO, SI */
-			IP_I2C_Start(LPC_I2C, I2C_TRANSFER_INTERRUPT);
-			return;
-		}
-	}
-	else if (Ret & I2C_RECV_END) {
-		goto s_int_end;
-	}
-	else {
-		return;
-	}
-
-s_int_end:
-
-	LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
-
-	I2C_MasterComplete[I2C_Num] = true;
-}
-
-/* General Slave Interrupt handler for I2C peripheral */
-void IP_I2C_Interrupt_SlaveHandler(IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num)
-{
-	uint32_t returnCode;
-	I2C_S_SETUP_Type *txrx_setup;
-	int32_t Ret = I2C_OK;
-
-	txrx_setup = (I2C_S_SETUP_Type *) &i2cdat[I2C_Num].txrx_setup_slave;
-
-	while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {}
-
-	returnCode = (uint32_t) (LPC_I2C->STAT & I2C_STAT_CODE_BITMASK);
-	/* Save current status */
-	txrx_setup->status = returnCode;
-
-	Ret = IP_I2C_SlaveHanleStates(LPC_I2C, returnCode, txrx_setup);
-
-	if ((I2C_CheckError(Ret)) || (Ret & I2C_STA_STO_RECV) || (Ret & I2C_SEND_END)) {
-		goto s_int_end;
-	}
-	else {
-		return;
-	}
-
-s_int_end:
-	LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
-
-	I2C_SlaveComplete[I2C_Num] = true;
-}
-
-/* Transmit and Receive data in master mode */
-Status IP_I2C_MasterTransferData(IP_I2C_001_Type *LPC_I2C,
-								 I2C_ID_Type I2C_Num,
-								 I2C_M_SETUP_Type *TransferCfg,
-								 I2C_TRANSFER_OPT_Type Opt)
-{
-	uint32_t CodeStatus;
-	int32_t Ret = I2C_OK;
-
-	/* Reset I2C setup value to default state */
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-	TransferCfg->status = 0;
-
-	if (Opt == I2C_TRANSFER_POLLING) {
-		/* First Start condition -------------------------------------------------------------- */
-		TransferCfg->retransmissions_count = 0;
-retry:
-		/* Reset I2C setup value to default state */
-		TransferCfg->tx_count = 0;
-		TransferCfg->rx_count = 0;
-
-		/* Start command */
-		CodeStatus = IP_I2C_Start(LPC_I2C, I2C_TRANSFER_POLLING);
-
-		while (1) {	/* send data first and then receive data from Slave */
-			Ret = IP_I2C_MasterHanleStates(LPC_I2C, CodeStatus, TransferCfg, I2C_TRANSFER_POLLING);
-			if (I2C_CheckError(Ret)) {
-				TransferCfg->retransmissions_count++;
-				if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max) {
-					/* save status */
-					TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;
-					goto error;
-				}
-				else {
-					goto retry;
-				}
-			}
-			else if ( (Ret & I2C_BYTE_SENT) ||
-					  (Ret & I2C_BYTE_RECV)) {
-				/* Wait for sending ends/ Wait for next byte */
-				while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {}
-			}
-			else if (Ret & I2C_SEND_END) {	/* already send all data */
-				/* If no need to wait for data from Slave */
-				if (TransferCfg->rx_count >= (TransferCfg->rx_length)) {
-					break;
-				}
-				else {
-					IP_I2C_Start(LPC_I2C, I2C_TRANSFER_POLLING);
-				}
-			}
-			else if (Ret & I2C_RECV_END) {	/* already receive all data */
-				break;
-			}
-			CodeStatus = LPC_I2C->STAT & I2C_STAT_CODE_BITMASK;
-		}
-		return SUCCESS;
-error:
-		return ERROR;
-	}
-	else if (Opt == I2C_TRANSFER_INTERRUPT) {
-		I2C_MasterComplete[I2C_Num] = false;
-		/* Setup tx_rx data, callback and interrupt handler */
-		i2cdat[I2C_Num].txrx_setup_master = *TransferCfg;
-
-		/* Set direction phase, write first */
-		i2cdat[I2C_Num].dir = 0;
-
-		/* First Start condition -------------------------------------------------------------- */
-		/* Reset STA, STO, SI */
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STOC | I2C_I2CONCLR_STAC;
-		LPC_I2C->CONSET = I2C_I2CONSET_STA;
-
-		return SUCCESS;
-	}
-
-	return ERROR;
-}
-
-/* Receive and Transmit data in slave mode */
-Status IP_I2C_SlaveTransferData(IP_I2C_001_Type *LPC_I2C,
-								I2C_ID_Type I2C_Num,
-								I2C_S_SETUP_Type *TransferCfg,
-								I2C_TRANSFER_OPT_Type Opt)
-{
-	int32_t   Ret = I2C_OK;
-	uint32_t CodeStatus = 0;
-
-	/* Reset I2C setup value to default state */
-	TransferCfg->tx_count = 0;
-	TransferCfg->rx_count = 0;
-	TransferCfg->status = 0;
-
-	/* Polling option */
-	if (Opt == I2C_TRANSFER_POLLING) {
-		/* Set AA bit to ACK command on I2C bus */
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-
-		/* Clear SI bit to be ready ... */
-		LPC_I2C->CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_STOC);
-
-		while (1) {
-			/* Check SI flag ready */
-			if (LPC_I2C->CONSET & I2C_I2CONSET_SI) {
-				CodeStatus = (LPC_I2C->STAT & I2C_STAT_CODE_BITMASK);
-
-				Ret = IP_I2C_SlaveHanleStates(LPC_I2C, CodeStatus, TransferCfg);
-				if (I2C_CheckError(Ret)) {
-					goto s_error;
-				}
-				else if ((Ret & I2C_STA_STO_RECV) || (Ret & I2C_SEND_END)) {
-					goto s_end_stage;
-				}
-			}
-		}
-
-s_end_stage:
-		/* Clear AA bit to disable ACK on I2C bus */
-		LPC_I2C->CONCLR = I2C_I2CONCLR_AAC;
-
-		/* Check if there's no error during operation
-		 * Update status
-		 */
-		TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE;
-		return SUCCESS;
-
-s_error:
-		/* Clear AA bit to disable ACK on I2C bus */
-		LPC_I2C->CONCLR = I2C_I2CONCLR_AAC;
-
-		/* Update status */
-		TransferCfg->status = CodeStatus;
-		return ERROR;
-	}
-
-	else if (Opt == I2C_TRANSFER_INTERRUPT) {
-		I2C_SlaveComplete[I2C_Num] = false;
-		/* Setup tx_rx data, callback and interrupt handler */
-		i2cdat[I2C_Num].txrx_setup_slave = *TransferCfg;
-
-		/* Set direction phase, read first */
-		i2cdat[I2C_Num].dir = 1;
-
-		/* Enable AA */
-		LPC_I2C->CONSET = I2C_I2CONSET_AA;
-		LPC_I2C->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
-
-		return SUCCESS;
-	}
-
-	return ERROR;
-}
-
-/* Get status of Master Transfer */
-bool IP_I2C_Interrupt_MasterTransferComplete(I2C_ID_Type I2C_Num)
-{
-	bool retval;
-
-	retval = I2C_MasterComplete[I2C_Num];
-
-	I2C_MasterComplete[I2C_Num] = false;
-
-	return retval;
-}
-
-/* Get status of Slave Transfer */
-bool IP_I2C_Interrupt_SlaveTransferComplete(I2C_ID_Type I2C_Num)
-{
-	bool retval;
-
-	retval = I2C_SlaveComplete[I2C_Num];
-
-	I2C_SlaveComplete[I2C_Num] = false;
-
-	return retval;
-}
-
-/* Set Own slave address in I2C peripheral corresponding to	parameter specified in OwnSlaveAddrConfigStruct */
-void IP_I2C_SetOwnSlaveAddr(IP_I2C_001_Type *LPC_I2C, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)
-{
-	uint32_t tmp;
-
-	tmp = (((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1))	\
-		   | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00)) & I2C_I2ADR_BITMASK;
-	switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel) {
-	case 0:
-		LPC_I2C->ADR0 = tmp;
-		LPC_I2C->MASK[0] =
-			I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
-		break;
-
-	case 1:
-		LPC_I2C->ADR1 = tmp;
-		LPC_I2C->MASK[1] = I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
-		break;
-
-	case 2:
-		LPC_I2C->ADR2 = tmp;
-		LPC_I2C->MASK[2] = I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
-		break;
-
-	case 3:
-		LPC_I2C->ADR3 = tmp;
-		LPC_I2C->MASK[3] = I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
-		break;
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2c_001.h b/bsp/xplorer4330/libraries/lpc_ip/i2c_001.h
deleted file mode 100644
index 62fdd43161..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/i2c_001.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * @brief I2C registers and driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2C_001_H_
-#define __I2C_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_I2C_001 IP: I2C register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief I2C register block structure
- */
-typedef struct {				/*!< I2C0 Structure         */
-	__IO uint32_t CONSET;		/*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-	__I  uint32_t STAT;			/*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
-	__IO uint32_t DAT;			/*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
-	__IO uint32_t ADR0;			/*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-	__IO uint32_t SCLH;			/*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
-	__IO uint32_t SCLL;			/*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
-	__O  uint32_t CONCLR;		/*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-	__IO uint32_t MMCTRL;		/*!< Monitor mode control register. */
-	__IO uint32_t ADR1;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-	__IO uint32_t ADR2;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-	__IO uint32_t ADR3;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-	__I  uint32_t DATA_BUFFER;	/*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
-	__IO uint32_t MASK[4];		/*!< I2C Slave address mask register */
-} IP_I2C_001_Type;
-
-/**
- * @brief I2C state handle return values
- */
-#define I2C_STA_STO_RECV            0x20
-
-/**
- * @brief I2C Control Set register description
- */
-#define I2C_I2CONSET_AA             ((0x04))/*!< Assert acknowledge flag */
-#define I2C_I2CONSET_SI             ((0x08))/*!< I2C interrupt flag */
-#define I2C_I2CONSET_STO            ((0x10))/*!< STOP flag */
-#define I2C_I2CONSET_STA            ((0x20))/*!< START flag */
-#define I2C_I2CONSET_I2EN           ((0x40))/*!< I2C interface enable */
-
-/**
- * @brief I2C Control Clear register description
- */
-#define I2C_I2CONCLR_AAC            ((1 << 2))	/*!< Assert acknowledge Clear bit */
-#define I2C_I2CONCLR_SIC            ((1 << 3))	/*!< I2C interrupt Clear bit */
-#define I2C_I2CONCLR_STOC           ((1 << 4))	/*!< I2C STOP Clear bit */
-#define I2C_I2CONCLR_STAC           ((1 << 5))	/*!< START flag Clear bit */
-#define I2C_I2CONCLR_I2ENC          ((1 << 6))	/*!< I2C interface Disable bit */
-
-/**
- * @brief I2C Status Code definition (I2C Status register)
- */
-#define I2C_STAT_CODE_BITMASK       ((0xF8))/*!< Return Code mask in I2C status register */
-#define I2C_STAT_CODE_ERROR         ((0xFF))/*!< Return Code error mask in I2C status register */
-
-/**
- * @brief I2C return status code definitions
- */
-#define I2C_I2STAT_NO_INF                       ((0xF8))/*!< No relevant information */
-#define I2C_I2STAT_BUS_ERROR                    ((0x00))/*!< Bus Error */
-
-/**
- * @brief I2C Master transmit mode
- */
-#define I2C_I2STAT_M_TX_START                   ((0x08))/*!< A start condition has been transmitted */
-#define I2C_I2STAT_M_TX_RESTART                 ((0x10))/*!< A repeat start condition has been transmitted */
-#define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_TX_SLAW_NACK               ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_TX_DAT_ACK                 ((0x28))/*!< Data has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))/*!< Data has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
-
-/**
- * @brief I2C Master receive mode
- */
-#define I2C_I2STAT_M_RX_START                   ((0x08))/*!< A start condition has been transmitted */
-#define I2C_I2STAT_M_RX_RESTART                 ((0x10))/*!< A repeat start condition has been transmitted */
-#define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))/*!< Arbitration lost */
-#define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_RX_SLAR_NACK               ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_RX_DAT_ACK                 ((0x50))/*!< Data has been received, ACK has been returned */
-#define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))/*!< Data has been received, NACK has been returned */
-
-/**
- * @brief I2C Slave receive mode
- */
-#define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))/*!< Own slave address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA          ((0x68))/*!< Arbitration lost in SLA+R/W as master */
-// #define I2C_I2STAT_S_RX_SLAW_ACK				((0x68)) /*!< Own SLA+W has been received, ACK returned */
-#define I2C_I2STAT_S_RX_GENCALL_ACK             ((0x70))/*!< General call address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL      ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
-// #define I2C_I2STAT_S_RX_GENCALL_ACK				((0x78)) /*!< General call address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK         ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK     ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
-#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX   ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
-														   SLV/TRX (Slave Transmit) */
-
-/**
- * @brief I2C Slave transmit mode
- */
-#define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
-#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA          ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
-// #define I2C_I2STAT_S_TX_SLAR_ACK				((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
-#define I2C_I2STAT_S_TX_DAT_ACK                 ((0xB8))/*!< Data has been transmitted, ACK has been received */
-#define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))/*!< Data has been transmitted, NACK has been received */
-#define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
-#define I2C_SLAVE_TIME_OUT                      0x10000000UL/*!< Time out in case of using I2C slave mode */
-
-/**
- * @brief I2C Data register definition
- */
-#define I2C_I2DAT_BITMASK           ((0xFF))/*!< Mask for I2DAT register */
-#define I2C_I2DAT_IDLE_CHAR         (0xFF)	/*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
-											     its sending data length that can be supported */
-
-/**
- * @brief I2C Monitor mode control register description
- */
-#define I2C_I2MMCTRL_MM_ENA         ((1 << 0))			/**< Monitor mode enable */
-#define I2C_I2MMCTRL_ENA_SCL        ((1 << 1))			/**< SCL output enable */
-#define I2C_I2MMCTRL_MATCH_ALL      ((1 << 2))			/**< Select interrupt register match */
-#define I2C_I2MMCTRL_BITMASK        ((0x07))		/**< Mask for I2MMCTRL register */
-
-/**
- * @brief I2C Data buffer register description
- */
-#define I2DATA_BUFFER_BITMASK       ((0xFF))/*!< I2C Data buffer register bit mask */
-
-/**
- * @brief I2C Slave Address registers definition
- */
-#define I2C_I2ADR_GC                ((1 << 0))	/*!< General Call enable bit */
-#define I2C_I2ADR_BITMASK           ((0xFF))/*!< I2C Slave Address registers bit mask */
-
-/**
- * @brief I2C Mask Register definition
- */
-#define I2C_I2MASK_MASK(n)          ((n & 0xFE))/*!< I2C Mask Register mask field */
-
-/**
- * @brief I2C SCL HIGH duty cycle Register definition
- */
-#define I2C_I2SCLH_BITMASK          ((0xFFFF))	/*!< I2C SCL HIGH duty cycle Register bit mask */
-
-/**
- * @brief I2C SCL LOW duty cycle Register definition
- */
-#define I2C_I2SCLL_BITMASK          ((0xFFFF))	/*!< I2C SCL LOW duty cycle Register bit mask */
-
-/**
- * @brief I2C status values
- */
-#define I2C_SETUP_STATUS_ARBF   (1 << 8)	/**< Arbitration false */
-#define I2C_SETUP_STATUS_NOACKF (1 << 9)	/**< No ACK returned */
-#define I2C_SETUP_STATUS_DONE   (1 << 10)	/**< Status DONE */
-
-/**
- * @brief I2C state handle return values
- */
-#define I2C_OK                      0x00
-#define I2C_BYTE_SENT               0x01
-#define I2C_BYTE_RECV               0x02
-#define I2C_LAST_BYTE_RECV          0x04
-#define I2C_SEND_END                0x08
-#define I2C_RECV_END                0x10
-#define I2C_STA_STO_RECV            0x20
-
-#define I2C_ERR                     (0x10000000)
-#define I2C_NAK_RECV                (0x10000000 | 0x01)
-
-#define I2C_CheckError(ErrorCode)   (ErrorCode & 0x10000000)
-
-/**
- * @brief I2C monitor control configuration defines
- */
-#define I2C_MONITOR_CFG_SCL_OUTPUT  I2C_I2MMCTRL_ENA_SCL		/**< SCL output enable */
-#define I2C_MONITOR_CFG_MATCHALL    I2C_I2MMCTRL_MATCH_ALL		/**< Select interrupt register match */
-
-/**
- * @brief Master transfer setup data structure definitions
- */
-typedef struct {
-	uint32_t          sl_addr7bit;			/**< Slave address in 7bit mode */
-	uint8_t           *tx_data;				/**< Pointer to Transmit data - NULL if data transmit is not used */
-	uint32_t          tx_length;			/**< Transmit data length - 0 if data transmit is not used*/
-	uint32_t          tx_count;				/**< Current Transmit data counter */
-	uint8_t           *rx_data;				/**< Pointer to Receive data - NULL if data receive is not used */
-	uint32_t          rx_length;			/**< Receive data length - 0 if data receive is not used */
-	uint32_t          rx_count;				/**< Current Receive data counter */
-	uint32_t          retransmissions_max;	/**< Max Re-Transmission value */
-	uint32_t          retransmissions_count;/**< Current Re-Transmission counter */
-	uint32_t          status;				/**< Current status of I2C activity */
-} I2C_M_SETUP_Type;
-
-/**
- * @brief Slave transfer setup data structure definitions
- */
-typedef struct {
-	uint8_t           *tx_data;		/**< Pointer to transmit data - NULL if data transmit is not used */
-	uint32_t          tx_length;	/**< Transmit data length - 0 if data transmit is not used */
-	uint32_t          tx_count;		/**< Current transmit data counter	*/
-	uint8_t           *rx_data;		/**< Pointer to receive data - NULL if data received is not used */
-	uint32_t          rx_length;	/**< Receive data length - 0 if data receive is not used */
-	uint32_t          rx_count;		/**< Current receive data counter */
-	uint32_t          status;		/**< Current status of I2C activity */
-} I2C_S_SETUP_Type;
-
-/**
- * @brief Transfer option type definitions
- */
-typedef enum {
-	I2C_TRANSFER_POLLING = 0,	/**< Transfer in polling mode */
-	I2C_TRANSFER_INTERRUPT		/**< Transfer in interrupt mode */
-} I2C_TRANSFER_OPT_Type;
-
-/**
- * @brief I2C Own slave address setting structure
- */
-typedef struct {
-	uint8_t SlaveAddrChannel;	/**< Slave Address channel in I2C control, should be in range from 0..3 */
-	uint8_t SlaveAddr_7bit;		/**< Value of 7-bit slave address */
-	uint8_t GeneralCallState;	/**< Enable/Disable General Call Functionality when I2C control being in Slave mode, should be:
-								   - ENABLE: Enable General Call function.
-								   - DISABLE: Disable General Call function. */
-	uint8_t SlaveAddrMaskValue;	/**< Any bit in this 8-bit value (bit 7:1) which is set to '1' will cause an automatic compare on
-								   the corresponding bit of the received address when it is compared to the SlaveAddr_7bit value associated with this
-								   mask register. In other words, bits in SlaveAddr_7bit value which are masked are not taken into account in determining
-								   an address match */
-} I2C_OWNSLAVEADDR_CFG_Type;
-
-typedef enum {
-	I2C_MASTER_MODE,
-	I2C_SLAVE_MODE,
-	I2C_GENERAL_MODE,
-} I2C_Mode;
-
-typedef enum {
-	I2C0 = 0,
-#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-	I2C1,
-#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X)
-	I2C2,
-#endif
-#endif
-} I2C_ID_Type;
-
-/**
- * @brief	Initializes the LPC_I2C peripheral.
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @return	Nothing
- */
-void IP_I2C_Init(IP_I2C_001_Type *LPC_I2C);
-
-/**
- * @brief	De-initializes the I2C peripheral registers to their default reset values.
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @return	Nothing
- */
-void IP_I2C_DeInit(IP_I2C_001_Type *LPC_I2C);
-
-/**
- * @brief	Set up clock rate for I2Cx.
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @param	SCLValue	: Value of I2CSCL register
- * @return	Nothing
- */
-void IP_I2C_SetClockRate(IP_I2C_001_Type *LPC_I2C, uint32_t SCLValue);
-
-/**
- * @brief	Enable or disable I2C peripheral's operation
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @param	Mode		: I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE
- * @param	NewState	: New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE
- * @return	Nothing
- */
-void IP_I2C_Cmd(IP_I2C_001_Type *LPC_I2C, I2C_Mode Mode,  FunctionalState NewState);
-
-/**
- * @brief	General Master Interrupt handler for I2C peripheral
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @param	I2C_Num		: I2C port number, should be I2C0, I2C1 or I2C2
- * @return	Nothing
- */
-void IP_I2C_Interrupt_MasterHandler(IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num);
-
-/**
- * @brief	General Slave Interrupt handler for I2C peripheral
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @param	I2C_Num		: I2C port number, should be I2C0, I2C1 or I2C2
- * @return	Nothing
- */
-void IP_I2C_Interrupt_SlaveHandler (IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num);
-
-/**
- * @brief	Transmit and Receive data in master mode
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @param	I2C_Num		: I2C port number, should be I2C0, I2C1 or I2C2
- * @param	TransferCfg	: Pointer to a I2C_M_SETUP_Type structure that contains specified
- *                        information about the configuration for master transfer.
- * @param	Opt			: a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return	SUCCESS or ERROR
- *
- * Note:
- * - In case of using I2C to transmit/receive data only, either transmit/receive length set to 0
- * or transmit/receive data pointer set to NULL.
- * - In case of using I2C to transmit followed by receive data, transmit length, transmit data
- * pointer, receive length and receive data pointer should be set corresponding.
- */
-Status IP_I2C_MasterTransferData(IP_I2C_001_Type *LPC_I2C,
-								 I2C_ID_Type I2C_Num,
-								 I2C_M_SETUP_Type *TransferCfg,
-								 I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Receive and Transmit data in slave mode
- * @param	LPC_I2C		: Pointer to selected I2Cx peripheral
- * @param	I2C_Num		: I2C port number, should be I2C0, I2C1 or I2C2
- * @param	TransferCfg	: Pointer to a I2C_S_SETUP_Type structure that contains specified information
- *                        about the	configuration for master transfer.
- * @param	Opt			: I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return	SUCCESS or ERROR
- *
- * Note:
- * The mode of slave's operation depends on the command sent from master on the I2C bus. If the master
- * send a SLA+W command, this sub-routine will use receive data length and receive data pointer. If the
- * master send a SLA+R command, this sub-routine will use transmit data length and transmit data pointer.
- * If the master issue an repeat start command or a stop command, the slave will enable an time out condition,
- * during time out condition, if there's no activity on I2C bus, the slave will exit, otherwise (i.e. the master
- * send a SLA+R/W), the slave then switch to relevant operation mode. The time out should be used because the
- * return status code can not show difference from stop and repeat start command in slave operation.
- * In case of the expected data length from master is greater than data length that slave can support:
- * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR value.
- * - In case of writing operation (from master): slave will ignore remain data from master.
- */
-Status IP_I2C_SlaveTransferData(IP_I2C_001_Type *LPC_I2C,
-								I2C_ID_Type I2C_Num,
-								I2C_S_SETUP_Type *TransferCfg,
-								I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief	Get status of Master Transfer
- * @param	I2C_Num		: I2C port number, should be I2C0, I2C1 or I2C2
- * @return	Master transfer status, could be TRUE (completed) or FALSE (not completed yet)
- */
-bool    IP_I2C_Interrupt_MasterTransferComplete(I2C_ID_Type I2C_Num);
-
-/**
- * @brief	Get status of Slave Transfer
- * @param	I2C_Num		: I2C port number, should be I2C0, I2C1 or I2C2
- * @return	Slave transfer status, could be TRUE (completed) or FALSE (not completed yet)
- */
-bool    IP_I2C_Interrupt_SlaveTransferComplete(I2C_ID_Type I2C_Num);
-
-/**
- * @brief	Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.
- * @param	LPC_I2C		: I2C peripheral selected
- * @param	OwnSlaveAddrConfigStruct : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the
- *                      configuration information for the specified I2C slave address.
- * @return	Nothing
- */
-void IP_I2C_SetOwnSlaveAddr(IP_I2C_001_Type *LPC_I2C, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2C_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2s_001.c b/bsp/xplorer4330/libraries/lpc_ip/i2s_001.c
deleted file mode 100644
index c63177c6c7..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/i2s_001.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * @brief I2S Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "i2s_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize for I2S */
-void IP_I2S_Init(IP_I2S_001_Type *pI2S)
-{}
-
-/* Shutdown I2S */
-void IP_I2S_DeInit(IP_I2S_001_Type *pI2S)
-{
-	pI2S->DAI = 0x07E1;
-	pI2S->DAO = 0x87E1;
-	pI2S->IRQ = 0;
-	pI2S->TXMODE = 0;
-	pI2S->RXMODE = 0;
-	pI2S->DMA1 = 0;
-	pI2S->DMA2 = 0;
-}
-
-/* I2S configuration functions --------*/
-
-/* Selects the number of bytes in data */
-void IP_I2S_SetWordWidth(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t wordwidth)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO &= ~I2S_DAO_WORDWIDTH_MASK;
-		pI2S->DAO |= wordwidth;
-	}
-	else {
-		pI2S->DAI &= ~I2S_DAI_WORDWIDTH_MASK;
-		pI2S->DAI |= wordwidth;
-	}
-}
-
-/* Set I2S data format is monaural or stereo */
-void IP_I2S_SetMono(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mono)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO &= ~I2S_DAO_MONO;
-		pI2S->DAO |= mono;
-	}
-	else {
-		pI2S->DAI &= ~I2S_DAI_MONO;
-		pI2S->DAI |= mono;
-	}
-}
-
-/* Set I2S interface in master/slave mode */
-void IP_I2S_SetMasterSlaveMode(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mode)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO &= ~I2S_DAO_SLAVE;
-		pI2S->DAO |= mode;
-	}
-	else {
-		pI2S->DAI &= ~I2S_DAI_SLAVE;
-		pI2S->DAI |= mode;
-	}
-}
-
-/* Set the clock frequency for I2S interface */
-void IP_I2S_SetBitRate(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mclk_divider)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->TXBITRATE = mclk_divider;
-	}
-	else {
-		pI2S->RXBITRATE = mclk_divider;
-	}
-}
-
-/* Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK */
-void IP_I2S_SetXYDivider(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_divider)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->TXRATE = y_divider | (x_divider << 8);
-	}
-	else {
-		pI2S->RXRATE = y_divider | (x_divider << 8);
-	}
-}
-
-/* Set word select (WS) half period */
-void IP_I2S_SetWS_Halfperiod(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t ws_halfperiod)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO &= ~I2S_DAO_WS_HALFPERIOD_MASK;
-		pI2S->DAO |= I2S_DAO_WS_HALFPERIOD(ws_halfperiod);
-	}
-	else {
-		pI2S->DAI &= ~I2S_DAI_WS_HALFPERIOD_MASK;
-		pI2S->DAI |= I2S_DAI_WS_HALFPERIOD(ws_halfperiod);
-	}
-}
-
-/* Set the I2S operating modes */
-void IP_I2S_ModeConfig(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->TXMODE = clksel | fpin | mcena;
-	}
-	else {
-		pI2S->RXMODE = clksel | fpin | mcena;
-	}
-}
-
-/* Get the current level of the Transmit/Receive FIFO */
-uint8_t IP_I2S_GetLevel(IP_I2S_001_Type *pI2S, uint8_t TRMode)
-{
-	if (TRMode == I2S_TX_MODE) {
-		return (pI2S->STATE >> 16) & 0xF;
-	}
-	else {
-		return (pI2S->STATE >> 8) & 0xF;
-	}
-}
-
-/* I2S operate functions -------------*/
-
-/* Send a 32-bit data to TXFIFO for transmition */
-void IP_I2S_Send(IP_I2S_001_Type *pI2S, uint32_t data)
-{
-	pI2S->TXFIFO = data;
-}
-
-/* Get received data from RXFIFO */
-uint32_t IP_I2S_Receive(IP_I2S_001_Type *pI2S)
-{
-	return pI2S->RXFIFO;
-}
-
-/* Start the  I2S */
-void IP_I2S_Start(IP_I2S_001_Type *pI2S, uint8_t TRMode)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO &= ~(I2S_DAO_RESET | I2S_DAO_STOP | I2S_DAO_MUTE);
-	}
-	else {
-		pI2S->DAI &= ~(I2S_DAI_RESET | I2S_DAI_STOP);
-	}
-}
-
-/* Disables accesses on FIFOs, places the transmit channel in mute mode */
-void IP_I2S_Pause(IP_I2S_001_Type *pI2S, uint8_t TRMode)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO |= I2S_DAO_STOP;
-	}
-	else {
-		pI2S->DAI |= I2S_DAI_STOP;
-	}
-}
-
-/* Transmit channel sends only zeroes */
-void IP_I2S_Mute(IP_I2S_001_Type *pI2S, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pI2S->DAO |= I2S_DAO_MUTE;
-	}
-	else {
-		pI2S->DAO &= ~I2S_DAO_MUTE;
-	}
-}
-
-/* Pause, resets the transmit channel and FIFO asynchronously */
-void IP_I2S_Stop(IP_I2S_001_Type *pI2S, uint8_t TRMode)
-{
-	if (TRMode == I2S_TX_MODE) {
-		pI2S->DAO &= ~I2S_DAO_MUTE;
-		pI2S->DAO |= I2S_DAO_STOP | I2S_DAO_RESET;
-	}
-	else {
-		pI2S->DAI |= I2S_DAI_STOP | I2S_DAI_RESET;
-	}
-}
-
-/* I2S DMA functions ----------------*/
-
-/* Set the FIFO level on which to create an DMA request */
-void IP_I2S_DMACmd(IP_I2S_001_Type *pI2S, IP_I2S_DMARequestNumber_Type DMANum, uint8_t TRMode, FunctionalState NewState)
-{
-	if (TRMode == I2S_RX_MODE) {
-		if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) {
-			if (NewState == ENABLE) {
-				pI2S->DMA1 |= 0x01;
-			}
-			else {
-				pI2S->DMA1 &= ~0x01;
-			}
-		}
-		else {
-			if (NewState == ENABLE) {
-				pI2S->DMA2 |= 0x01;
-			}
-			else {
-				pI2S->DMA2 &= ~0x01;
-			}
-		}
-	}
-	else {
-		if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) {
-			if (NewState == ENABLE) {
-				pI2S->DMA1 |= 0x02;
-			}
-			else {
-				pI2S->DMA1 &= ~0x02;
-			}
-		}
-		else {
-			if (NewState == ENABLE) {
-				pI2S->DMA2 |= 0x02;
-			}
-			else {
-				pI2S->DMA2 &= ~0x02;
-			}
-		}
-	}
-}
-
-/* Enable/Disable DMA for the I2S */
-void IP_I2S_SetFIFODepthDMA(IP_I2S_001_Type *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_Type DMANum, uint32_t depth)
-{
-	if (TRMode == I2S_RX_MODE) {
-		if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) {
-			pI2S->DMA1 &= ~(0x0F << 8);
-			pI2S->DMA1 |= depth << 8;
-		}
-		else {
-			pI2S->DMA2 &= ~(0x0F << 8);
-			pI2S->DMA2 |= depth << 8;
-		}
-	}
-	else {
-		if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) {
-			pI2S->DMA1 &= ~(0x0F << 16);
-			pI2S->DMA1 |= depth << 16;
-		}
-		else {
-			pI2S->DMA2 &= ~(0x0F << 16);
-			pI2S->DMA2 |= depth << 16;
-		}
-	}
-}
-
-/* I2S IRQ functions ----------------*/
-
-/* Enable/Disable interrupt for the I2S */
-void IP_I2S_InterruptCmd(IP_I2S_001_Type *pI2S, uint8_t TRMode, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pI2S->IRQ |= (TRMode == I2S_RX_MODE) ? 0x01 : 0x02;
-	}
-	else {
-		pI2S->IRQ &= (TRMode == I2S_RX_MODE) ? (~0x01) : (~0x02);
-	}
-}
-
-/* Set the FIFO level on which to create an irq request */
-void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t depth)
-{
-	depth &= 0x0F;
-	if (TRMode == I2S_RX_MODE) {
-		pI2S->IRQ &= ~I2S_IRQ_RX_DEPTH_MASK;
-		pI2S->IRQ |= I2S_IRQ_RX_DEPTH(depth);
-	}
-	else {
-		pI2S->IRQ &= ~I2S_IRQ_TX_DEPTH_MASK;
-		pI2S->IRQ |= I2S_IRQ_TX_DEPTH(depth);
-	}
-}
-
-/* Get the status of I2S interrupt */
-Status IP_I2S_GetIntStatus(IP_I2S_001_Type *pI2S, uint8_t TRMode)
-{
-	if (TRMode == I2S_TX_MODE) {
-		return (Status) (((pI2S->IRQ >> 1) & 0x01) & ((pI2S->STATE) & 0x01));
-	}
-	else {
-		return (Status) (((pI2S->IRQ) & 0x01) & ((pI2S->STATE) & 0x01));
-	}
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2s_001.h b/bsp/xplorer4330/libraries/lpc_ip/i2s_001.h
deleted file mode 100644
index a1c231b03f..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/i2s_001.h
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * @brief I2S Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2S_001_H_
-#define __I2S_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_I2S_001 IP: I2S register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief I2S register block structure
- */
-typedef struct {				/*!< I2S Structure */
-	__IO uint32_t DAO;			/*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
-	__IO uint32_t DAI;			/*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
-	__O uint32_t TXFIFO;		/*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
-	__I uint32_t RXFIFO;		/*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
-	__I uint32_t STATE;			/*!< I2S Status Feedback Register. Contains status information about the I2S interface */
-	__IO uint32_t DMA1;			/*!< I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
-	__IO uint32_t DMA2;			/*!< I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
-	__IO uint32_t IRQ;			/*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
-	__IO uint32_t TXRATE;		/*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
-	__IO uint32_t RXRATE;		/*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
-	__IO uint32_t TXBITRATE;	/*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
-	__IO uint32_t RXBITRATE;	/*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
-	__IO uint32_t TXMODE;		/*!< I2S Transmit mode control */
-	__IO uint32_t RXMODE;		/*!< I2S Receive mode control */
-} IP_I2S_001_Type;
-
-/**
- * @brief I2S configuration parameter defines
- */
-/** I2S Wordwidth bit */
-#define I2S_WORDWIDTH_8     (0UL << 0)
-#define I2S_WORDWIDTH_16    (1UL << 0)
-#define I2S_WORDWIDTH_32    (3UL << 0)
-/** I2S Channel bit */
-#define I2S_STEREO          (0UL << 2)
-#define I2S_MONO            (1UL << 2)
-/** I2S Master/Slave mode bit */
-#define I2S_MASTER_MODE     (0UL << 5)
-#define I2S_SLAVE_MODE      (1UL << 5)
-/** I2S Stop bit */
-#define I2S_STOP_ENABLE     (0UL << 3)
-#define I2S_STOP_DISABLE    (1UL << 3)
-/** I2S Reset bit */
-#define I2S_RESET_ENABLE    (1UL << 4)
-#define I2S_RESET_DISABLE   (0UL << 4)
-/** I2S Mute bit */
-#define I2S_MUTE_ENABLE     (1UL << 15)
-#define I2S_MUTE_DISABLE    (0UL << 15)
-
-/**
- * @brief Macro defines for DAO-Digital Audio Output register
- */
-
-/** I2S wordwide - the number of bytes in data*/
-#define I2S_DAO_WORDWIDTH_8     ((uint32_t) (0))	/** 8 bit	*/
-#define I2S_DAO_WORDWIDTH_16    ((uint32_t) (1))	/** 16 bit	*/
-#define I2S_DAO_WORDWIDTH_32    ((uint32_t) (3))	/** 32 bit	*/
-#define I2S_DAO_WORDWIDTH_MASK  ((uint32_t) (3))
-/** I2S control mono or stereo format */
-#define I2S_DAO_MONO            ((uint32_t) (1 << 2))
-/** I2S control stop mode */
-#define I2S_DAO_STOP            ((uint32_t) (1 << 3))
-/** I2S control reset mode */
-#define I2S_DAO_RESET           ((uint32_t) (1 << 4))
-/** I2S control master/slave mode */
-#define I2S_DAO_SLAVE           ((uint32_t) (1 << 5))
-/** I2S word select half period minus one */
-#define I2S_DAO_WS_HALFPERIOD(n)    ((uint32_t) ((n & 0x1FF) << 6))
-#define I2S_DAO_WS_HALFPERIOD_MASK  ((uint32_t) ((0x1FF) << 6))
-/** I2S control mute mode */
-#define I2S_DAO_MUTE            ((uint32_t) (1 << 15))
-
-/**
- * @brief Macro defines for DAI-Digital Audio Input register
- */
-
-/** I2S wordwide - the number of bytes in data*/
-#define I2S_DAI_WORDWIDTH_8     ((uint32_t) (0))	/** 8 bit	*/
-#define I2S_DAI_WORDWIDTH_16    ((uint32_t) (1))	/** 16 bit	*/
-#define I2S_DAI_WORDWIDTH_32    ((uint32_t) (3))	/** 32 bit	*/
-#define I2S_DAI_WORDWIDTH_MASK  ((uint32_t) (3))
-/** I2S control mono or stereo format */
-#define I2S_DAI_MONO            ((uint32_t) (1 << 2))
-/** I2S control stop mode */
-#define I2S_DAI_STOP            ((uint32_t) (1 << 3))
-/** I2S control reset mode */
-#define I2S_DAI_RESET           ((uint32_t) (1 << 4))
-/** I2S control master/slave mode */
-#define I2S_DAI_SLAVE           ((uint32_t) (1 << 5))
-/** I2S word select half period minus one (9 bits)*/
-#define I2S_DAI_WS_HALFPERIOD(n)    ((uint32_t) ((n & 0x1FF) << 6))
-#define I2S_DAI_WS_HALFPERIOD_MASK  ((uint32_t) ((0x1FF) << 6))
-
-/**
- * @brief Macro defines for STAT register (Status Feedback register)
- */
-
-/** I2S Status Receive or Transmit Interrupt */
-#define I2S_STATE_IRQ       ((uint32_t) (1))
-/** I2S Status Receive or Transmit DMA1 */
-#define I2S_STATE_DMA1      ((uint32_t) (1 << 1))
-/** I2S Status Receive or Transmit DMA2 */
-#define I2S_STATE_DMA2      ((uint32_t) (1 << 2))
-/** I2S Status Current level of the Receive FIFO (5 bits)*/
-#define I2S_STATE_RX_LEVEL(n)   ((uint32_t) ((n & 1F) << 8))
-/** I2S Status Current level of the Transmit FIFO (5 bits)*/
-#define I2S_STATE_TX_LEVEL(n)   ((uint32_t) ((n & 1F) << 16))
-
-/**
- * @brief Macro defines for DMA1 register (DMA1 Configuration register)
- */
-
-/** I2S control DMA1 for I2S receive */
-#define I2S_DMA1_RX_ENABLE      ((uint32_t) (1))
-/** I2S control DMA1 for I2S transmit */
-#define I2S_DMA1_TX_ENABLE      ((uint32_t) (1 << 1))
-/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
-#define I2S_DMA1_RX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 8))
-/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
-#define I2S_DMA1_TX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 16))
-
-/**
- * @brief Macro defines for DMA2 register (DMA2 Configuration register)
- */
-
-/** I2S control DMA2 for I2S receive */
-#define I2S_DMA2_RX_ENABLE      ((uint32_t) (1))
-/** I2S control DMA1 for I2S transmit */
-#define I2S_DMA2_TX_ENABLE      ((uint32_t) (1 << 1))
-/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
-#define I2S_DMA2_RX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 8))
-/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
-#define I2S_DMA2_TX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 16))
-
-/**
- * @brief Macro defines for IRQ register (Interrupt Request Control register)
- */
-
-/** I2S control I2S receive interrupt */
-#define I2S_IRQ_RX_ENABLE       ((uint32_t) (1))
-/** I2S control I2S transmit interrupt */
-#define I2S_IRQ_TX_ENABLE       ((uint32_t) (1 << 1))
-/** I2S set the FIFO level on which to create an irq request */
-#define I2S_IRQ_RX_DEPTH(n)     ((uint32_t) ((n & 0x0F) << 8))
-#define I2S_IRQ_RX_DEPTH_MASK   ((uint32_t) ((0x0F) << 8))
-/** I2S set the FIFO level on which to create an irq request */
-#define I2S_IRQ_TX_DEPTH(n)     ((uint32_t) ((n & 0x0F) << 16))
-#define I2S_IRQ_TX_DEPTH_MASK   ((uint32_t) ((0x0F) << 16))
-
-/**
- * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
- */
-
-/** I2S Transmit MCLK rate denominator */
-#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
-/** I2S Transmit MCLK rate denominator */
-#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
-/** I2S Receive MCLK rate denominator */
-#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
-/** I2S Receive MCLK rate denominator */
-#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
-
-/**
- * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
- */
-
-#define I2S_TXBITRATE(n)    ((uint32_t) (n & 0x3F))
-#define I2S_RXBITRATE(n)    ((uint32_t) (n & 0x3F))
-
-/**
- * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
- */
-
-/** I2S Transmit select clock source (2 bits)*/
-#define I2S_TXMODE_CLKSEL(n)    ((uint32_t) (n & 0x03))
-/** I2S Transmit control 4-pin mode */
-#define I2S_TXMODE_4PIN_ENABLE  ((uint32_t) (1 << 2))
-/** I2S Transmit control the TX_MCLK output */
-#define I2S_TXMODE_MCENA        ((uint32_t) (1 << 3))
-/** I2S Receive select clock source */
-#define I2S_RXMODE_CLKSEL(n)    ((uint32_t) (n & 0x03))
-/** I2S Receive control 4-pin mode */
-#define I2S_RXMODE_4PIN_ENABLE  ((uint32_t) (1 << 2))
-/** I2S Receive control the TX_MCLK output */
-#define I2S_RXMODE_MCENA        ((uint32_t) (1 << 3))
-
-/**
- * @brief I2S transmit/receive mode for configuration
- */
-typedef enum {
-	I2S_TX_MODE,
-	I2S_RX_MODE,
-} IP_I2S_TRxMode_Type;
-
-/**
- * @brief I2S DMA request channel define
- */
-typedef enum {
-	IP_I2S_DMA_REQUEST_NUMBER_1,
-	IP_I2S_DMA_REQUEST_NUMBER_2,
-} IP_I2S_DMARequestNumber_Type;
-
-/**********************************************************************************
- * I2S Init/DeInit functions
- *********************************************************************************/
-
-/**
- * @brief	Initialize for I2S
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @return	Nothing
- */
-void IP_I2S_Init(IP_I2S_001_Type *pI2S);
-
-/**
- * @brief	Shutdown I2S
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @return	Nothing
- * Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
- */
-void IP_I2S_DeInit(IP_I2S_001_Type *pI2S);
-
-/**********************************************************************************
- * I2S configuration functions
- *********************************************************************************/
-
-/**
- * @brief	Selects the number of bytes in data
- * @param	pI2S		: The base of I2S peripheral on the chip
- * @param	TRMode		: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	wordwidth	: Data width, should be :
- *							- I2S_WORDWIDTH_8
- *							- I2S_WORDWIDTH_16
- *							- I2S_WORDWIDTH_32
- * @return	Nothing
- */
-void IP_I2S_SetWordWidth(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t wordwidth);
-
-/**
- * @brief	Set I2S data format is monaural or stereo
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	mono	: Data channel, should be
- *						- I2S_STEREO
- *						- I2S_MONO
- * @return	Nothing
- */
-void IP_I2S_SetMono(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mono);
-
-/**
- * @brief	Set I2S interface in master/slave mode
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	mode	: Interface mode, should be
- *						- I2S_MASTER_MODE
- *						- I2S_SLAVE_MODE
- * @return	Nothing
- */
-void IP_I2S_SetMasterSlaveMode(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mode);
-
-/**
- * @brief	Set the clock frequency for I2S interface
- * @param	pI2S			: The base of I2S peripheral on the chip
- * @param	TRMode			: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	mclk_divider	: Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
- * @return	 Nothing
- * The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.
- * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz
- */
-void IP_I2S_SetBitRate(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mclk_divider);
-
-/**
- * @brief	Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK
- * @param	pI2S		: The base of I2S peripheral on the chip
- * @param	TRMode		: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	x_divider	: I2S transmit MCLK rate numerator
- * @param	y_devider	: I2S transmit MCLK rate denominator
- * @return	Nothing
- * Values of the numerator (X) and the denominator (Y) must be chosen to
- * produce a frequency twice that desired for the transmitter MCLK, which
- * must be an integer multiple of the transmitter bit clock rate.
- * The equation for the fractional rate generator is:
- * MCLK = PCLK * (X/Y) /2
- * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
- * greater than or equal to X.
- */
-void IP_I2S_SetXYDivider(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider);
-
-/**
- * @brief	Set word select (WS) half period
- * @param	pI2S			: The base of I2S peripheral on the chip
- * @param	TRMode			: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	ws_halfperiod	: I2S word select half period minus one
- * @return	Nothing
- * The Word Select period is configured separately for I2S input and I2S output.
- * For example: if the WS is 64clk period -> ws_halfperiod = 31
- */
-void IP_I2S_SetWS_Halfperiod(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t ws_halfperiod);
-
-/**
- * @brief	Set the I2S operating modes
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	clksel	: Clock source selection for the receive bit clock divider
- * @param	fpin	: Receive 4-pin mode selection
- * @param	mcena	: Enable for the RX_MCLK output
- * @return	Nothing
- * In addition to master and slave modes, which are independently configurable for
- * the transmitter and the receiver, several different clock sources are possible,
- * including variations that share the clock and/or WS between the transmitter and
- * receiver. It also allows using I2S with fewer pins, typically four.
- */
-void IP_I2S_ModeConfig(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena);
-
-/**
- * @brief	Get the current level of the Transmit/Receive FIFO
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Current level of the Transmit/Receive FIFO
- */
-uint8_t IP_I2S_GetLevel(IP_I2S_001_Type *pI2S, uint8_t TRMode);
-
-/**********************************************************************************
- * I2S operate functions
- *********************************************************************************/
-
-/**
- * @brief	Send a 32-bit data to TXFIFO for transmition
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	data	: Data to be transmited
- * @return	Nothing
- * The function writes to TXFIFO without checking any condition.
- */
-void IP_I2S_Send(IP_I2S_001_Type *pI2S, uint32_t data);
-
-/**
- * @brief	Get received data from RXFIFO
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @return	Data received in RXFIFO
- * The function reads from RXFIFO without checking any condition.
- */
-uint32_t IP_I2S_Receive(IP_I2S_001_Type *pI2S);
-
-/**
- * @brief	Start the I2S
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- */
-void IP_I2S_Start(IP_I2S_001_Type *pI2S, uint8_t TRMode);
-
-/**
- * @brief	Disables accesses on FIFOs, places the transmit channel in mute mode
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- */
-void IP_I2S_Pause(IP_I2S_001_Type *pI2S, uint8_t TRMode);
-
-/**
- * @brief	Transmit channel sends only zeroes
- * @param	pI2S		: The base of I2S peripheral on the chip
- * @param	NewState	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- * The data output from I2S transmit channel is always zeroes
- */
-void IP_I2S_Mute(IP_I2S_001_Type *pI2S, FunctionalState NewState);
-
-/**
- * @brief	Stop I2S asynchronously
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	Nothing
- * Pause, resets the transmit channel and FIFO asynchronously
- */
-void IP_I2S_Stop(IP_I2S_001_Type *pI2S, uint8_t TRMode);
-
-/**********************************************************************************
- * I2S DMA functions
- *********************************************************************************/
-
-/**
- * @brief	Set the FIFO level on which to create an DMA request
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	DMANum	: I2S DMA request number, should be
- *						- IP_I2S_DMA_REQUEST_NUMBER_1
- *						- IP_I2S_DMA_REQUEST_NUMBER_2
- * @param	depth	: FIFO level on which to create an DMA request
- * @return	Nothing
- * DMA request is generated when rx_depth_dma <= rx_level or tx_depth_dma >= tx_level
- */
-void IP_I2S_SetFIFODepthDMA(IP_I2S_001_Type *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_Type DMANum, uint32_t depth);
-
-/**
- * @brief	Enable/Disable DMA for the I2S
- * @param	pI2S		: The base of I2S peripheral on the chip
- * @param	TRMode		: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	DMANum		: I2S DMA request number, should be
- *							- IP_I2S_DMA_REQUEST_NUMBER_1
- *							- IP_I2S_DMA_REQUEST_NUMBER_2
- * @param	NewState	: ENABLE or DISABLE DMA
- * @return	Nothing
- */
-void IP_I2S_DMACmd(IP_I2S_001_Type *pI2S, IP_I2S_DMARequestNumber_Type DMANum, uint8_t TRMode, FunctionalState NewState);
-
-/**********************************************************************************
- * I2S IRQ functions
- *********************************************************************************/
-
-/**
- * @brief	Enable/Disable interrupt for the I2S
- * @param	pI2S		: The base of I2S peripheral on the chip
- * @param	TRMode		: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	NewState	: ENABLE or DISABLE Interrupt
- * @return	Nothing
- * Interrupt request is generated when rx_depth_irq <= rx_level or tx_depth_irq >= tx_level
- */
-void IP_I2S_InterruptCmd(IP_I2S_001_Type *pI2S, uint8_t TRMode, FunctionalState NewState);
-
-/**
- * @brief	Set the FIFO level on which to create an irq request
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param	depth	: FIFO level on which to create an irq request
- * @return	 Nothing
- */
-void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t depth);
-
-/**
- * @brief	Get the status of I2S interrupt
- * @param	pI2S	: The base of I2S peripheral on the chip
- * @param	TRMode	: Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return	I2S interrupt status, SET or RESET
- */
-Status IP_I2S_GetIntStatus(IP_I2S_001_Type *pI2S, uint8_t TRMode);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2S_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/lcd_001.c b/bsp/xplorer4330/libraries/lpc_ip/lcd_001.c
deleted file mode 100644
index df92bef5c0..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/lcd_001.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * @brief LCD controller Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "lcd_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the LCD controller */
-void IP_LCD_Init(IP_LCD_001_Type *LCDx, LCD_Config_Type *LCD_ConfigStruct)
-{
-	uint32_t i, regValue, *pPal;
-	uint32_t pcd;
-
-	/* disable the display */
-	LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
-
-	/* Setting LCD_TIMH register */
-	regValue = ( ((((LCD_ConfigStruct->PPL / 16) - 1) & 0x3F) << 2)
-				 |         (( (LCD_ConfigStruct->HSW - 1)    & 0xFF) << 8)
-				 |         (( (LCD_ConfigStruct->HFP - 1)    & 0xFF) << 16)
-				 |         (( (LCD_ConfigStruct->HBP - 1)    & 0xFF) << 24) );
-	LCDx->TIMH = regValue;
-
-	/* Setting LCD_TIMV register */
-	regValue = ((((LCD_ConfigStruct->LPP - 1) & 0x3FF) << 0)
-				|        (((LCD_ConfigStruct->VSW - 1) & 0x03F) << 10)
-				|        (((LCD_ConfigStruct->VFP - 1) & 0x0FF) << 16)
-				|        (((LCD_ConfigStruct->VBP - 1) & 0x0FF) << 24) );
-	LCDx->TIMV = regValue;
-
-	/* Generate the clock and signal polarity control word */
-	regValue = 0;
-	regValue = (((LCD_ConfigStruct->ACB - 1) & 0x1F) << 6);
-	regValue |= (LCD_ConfigStruct->IOE & 1) << 14;
-	regValue |= (LCD_ConfigStruct->IPC & 1) << 13;
-	regValue |= (LCD_ConfigStruct->IHS & 1) << 12;
-	regValue |= (LCD_ConfigStruct->IVS & 1) << 11;
-
-	/* Compute clocks per line based on panel type */
-	switch (LCD_ConfigStruct->LCD) {
-	case LCD_MONO_4:
-		regValue |= ((((LCD_ConfigStruct->PPL / 4) - 1) & 0x3FF) << 16);
-		break;
-
-	case LCD_MONO_8:
-		regValue |= ((((LCD_ConfigStruct->PPL / 8) - 1) & 0x3FF) << 16);
-		break;
-
-	case LCD_CSTN:
-		regValue |= (((((LCD_ConfigStruct->PPL * 3) / 8) - 1) & 0x3FF) << 16);
-		break;
-
-	case LCD_TFT:
-	default:
-		regValue |=	 /*1<<26 |*/ (((LCD_ConfigStruct->PPL - 1) & 0x3FF) << 16);
-	}
-
-	/* panel clock divisor */
-	pcd = 5;// LCD_ConfigStruct->pcd;   // TODO: should be calculated from LCDDCLK
-	pcd &= 0x3FF;
-	regValue |=  ((pcd >> 5) << 27) | ((pcd) & 0x1F);
-	LCDx->POL = regValue;
-
-	/* disable interrupts */
-	LCDx->INTMSK = 0;
-
-	/* set bits per pixel */
-	regValue = LCD_ConfigStruct->BPP << 1;
-
-	/* set color format RGB */
-	regValue |= LCD_ConfigStruct->color_format << 8;
-	regValue |= LCD_ConfigStruct->LCD << 4;
-	if (LCD_ConfigStruct->Dual == 1) {
-		regValue |= 1 << 7;
-	}
-	LCDx->CTRL = regValue;
-
-	/* clear palette */
-	pPal = (uint32_t *) (&(LCDx->PAL));
-	for (i = 0; i < 128; i++) {
-		*pPal = 0;
-		pPal++;
-	}
-}
-
-/* Power the LCD Panel (power pin) */
-void IP_LCD_Power(IP_LCD_001_Type *LCDx, FunctionalState OnOff) {
-	volatile int i;
-	if (OnOff) {
-		LCDx->CTRL |= CLCDC_LCDCTRL_PWR;
-		for (i = 0; i < 1000000; i++) {}
-		LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE;
-	}
-	else {
-		LCDx->CTRL &= ~CLCDC_LCDCTRL_PWR;
-		for (i = 0; i < 1000000; i++) {}
-		LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
-	}
-}
-
-/* Enable/Disable the LCD Controller */
-void IP_LCD_Enable(IP_LCD_001_Type *LCDx, FunctionalState EnDis) {
-	if (EnDis) {
-		LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE;
-	}
-	else {
-		LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
-	}
-}
-
-/* Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame Buffer for Dual Panel */
-void IP_LCD_SetUPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer) {
-	LCDx->UPBASE = (uint32_t) buffer;
-}
-
-/* Set LCD Lower Panel Frame Buffer for Dual Panel */
-void IP_LCD_SetLPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer) {
-	LCDx->LPBASE = (uint32_t) buffer;
-}
-
-/* Configure Cursor */
-void IP_LCD_Cursor_Config(IP_LCD_001_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, bool sync) {
-	LCDx->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size;
-}
-
-/* Get Internal Cursor Image Buffer Address */
-void *IP_LCD_Cursor_GetImageBufferAddress(IP_LCD_001_Type *LCDx, uint8_t cursor_num) {
-	return (void *) &(LCDx->CRSR_IMG[cursor_num * 64]);
-}
-
-/* Enable Cursor */
-void IP_LCD_Cursor_Enable(IP_LCD_001_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff) {
-	if (OnOff) {
-		LCDx->CRSR_CTRL = (cursor_num << 4) | 1;
-	}
-	else {
-		LCDx->CRSR_CTRL = (cursor_num << 4);
-	}
-}
-
-/* Load Cursor Palette 0 */
-void IP_LCD_Cursor_LoadPalette0(IP_LCD_001_Type *LCDx, uint32_t palette_color) {
-	/* 7:0 - Red
-	   15:8 - Green
-	   23:16 - Blue
-	   31:24 - Not used*/
-	LCDx->CRSR_PAL0 = (uint32_t) palette_color;
-}
-
-/* Load Cursor Palette 1 */
-void IP_LCD_Cursor_LoadPalette1(IP_LCD_001_Type *LCDx, uint32_t palette_color) {
-	/* 7:0 - Red
-	   15:8 - Green
-	   23:16 - Blue
-	   31:24 - Not used*/
-	LCDx->CRSR_PAL1 = (uint32_t) palette_color;
-}
-
-/* Set Cursor Position */
-void IP_LCD_Cursor_SetPos(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y) {
-	LCDx->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);
-}
-
-/* Set Cursor Clipping Position */
-void IP_LCD_Cursor_SetClip(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y) {
-	LCDx->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);
-}
-
-/* Load Color Palette */
-void IP_LCD_Color_LoadPalette(IP_LCD_001_Type *LCDx, uint32_t *palette_addr, uint32_t index) {
-	LCDx->PAL[index] = *(uint32_t *) palette_addr;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/lcd_001.h b/bsp/xplorer4330/libraries/lpc_ip/lcd_001.h
deleted file mode 100644
index 480c2b60e4..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/lcd_001.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * @brief LCD controller Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LCD_001_H_
-#define __LCD_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_LCD_001 IP: LCD register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief LCD Controller register block structure
- */
-typedef struct {				/*!< LCD Structure          */
-	__IO uint32_t  TIMH;		/*!< Horizontal Timing Control register */
-	__IO uint32_t  TIMV;		/*!< Vertical Timing Control register */
-	__IO uint32_t  POL;			/*!< Clock and Signal Polarity Control register */
-	__IO uint32_t  LE;			/*!< Line End Control register */
-	__IO uint32_t  UPBASE;		/*!< Upper Panel Frame Base Address register */
-	__IO uint32_t  LPBASE;		/*!< Lower Panel Frame Base Address register */
-	__IO uint32_t  CTRL;		/*!< LCD Control register   */
-	__IO uint32_t  INTMSK;		/*!< Interrupt Mask register */
-	__I  uint32_t  INTRAW;		/*!< Raw Interrupt Status register */
-	__I  uint32_t  INTSTAT;		/*!< Masked Interrupt Status register */
-	__O  uint32_t  INTCLR;		/*!< Interrupt Clear register */
-	__I  uint32_t  UPCURR;		/*!< Upper Panel Current Address Value register */
-	__I  uint32_t  LPCURR;		/*!< Lower Panel Current Address Value register */
-	__I  uint32_t  RESERVED0[115];
-	__IO uint16_t PAL[256];		/*!< 256x16-bit Color Palette registers */
-	__I  uint32_t  RESERVED1[256];
-	__IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */
-	__IO uint32_t  CRSR_CTRL;	/*!< Cursor Control register */
-	__IO uint32_t  CRSR_CFG;	/*!< Cursor Configuration register */
-	__IO uint32_t  CRSR_PAL0;	/*!< Cursor Palette register 0 */
-	__IO uint32_t  CRSR_PAL1;	/*!< Cursor Palette register 1 */
-	__IO uint32_t  CRSR_XY;		/*!< Cursor XY Position register */
-	__IO uint32_t  CRSR_CLIP;	/*!< Cursor Clip Position register */
-	__I  uint32_t  RESERVED2[2];
-	__IO uint32_t  CRSR_INTMSK;	/*!< Cursor Interrupt Mask register */
-	__O  uint32_t  CRSR_INTCLR;	/*!< Cursor Interrupt Clear register */
-	__I  uint32_t  CRSR_INTRAW;	/*!< Cursor Raw Interrupt Status register */
-	__I  uint32_t  CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */
-} IP_LCD_001_Type;
-
-/**
- * @brief LCD Palette entry format
- */
-typedef struct {
-	uint32_t Rl : 5;
-	uint32_t Gl : 5;
-	uint32_t Bl : 5;
-	uint32_t Il : 1;
-	uint32_t Ru : 5;
-	uint32_t Gu : 5;
-	uint32_t Bu : 5;
-	uint32_t Iu : 1;
-} LCD_PALETTE_ENTRY_Type;
-
-/**
- * @brief LCD Panel type
- */
-typedef enum {
-	LCD_TFT = 0x02,		/*!< standard TFT */
-	LCD_MONO_4 = 0x01,	/*!< 4-bit STN mono */
-	LCD_MONO_8 = 0x05,	/*!< 8-bit STN mono */
-	LCD_CSTN = 0x00		/*!< color STN */
-} LCD_PANEL_OPT;
-
-/**
- * @brief LCD Color Format
- */
-typedef enum {
-	LCD_COLOR_FORMAT_RGB = 0,
-	LCD_COLOR_FORMAT_BGR
-} LCD_COLOR_FORMAT_OPT;
-
-/** LCD Interrupt control mask register bits */
-#define LCD_INTMSK_FUFIM   0x2	/*!< FIFO underflow interrupt enable */
-#define LCD_INTMSK_LNBUIM  0x4	/*!< LCD next base address update interrupt enable */
-#define LCD_INTMSK_VCOMPIM 0x8	/*!< Vertical compare interrupt enable */
-#define LCD_INTMSK_BERIM   0x10	/*!< AHB master error interrupt enable */
-
-#define CLCDC_LCDCTRL_ENABLE    _BIT(0)		/*!< LCD control enable bit */
-#define CLCDC_LCDCTRL_PWR       _BIT(11)	/*!< LCD control power enable bit */
-
-/**
- * @brief A structure for LCD Configuration
- */
-typedef struct {
-	uint8_t  HBP;	/*!< Horizontal back porch in clocks */
-	uint8_t  HFP;	/*!< Horizontal front porch in clocks */
-	uint8_t  HSW;	/*!< HSYNC pulse width in clocks */
-	uint16_t PPL;	/*!< Pixels per line */
-	uint8_t  VBP;	/*!< Vertical back porch in clocks */
-	uint8_t  VFP;	/*!< Vertical front porch in clocks */
-	uint8_t  VSW;	/*!< VSYNC pulse width in clocks */
-	uint16_t LPP;	/*!< Lines per panel */
-	uint8_t  IOE;	/*!< Invert output enable, 1 = invert */
-	uint8_t  IPC;	/*!< Invert panel clock, 1 = invert */
-	uint8_t  IHS;	/*!< Invert HSYNC, 1 = invert */
-	uint8_t  IVS;	/*!< Invert VSYNC, 1 = invert */
-	uint8_t  ACB;	/*!< AC bias frequency in clocks (not used) */
-	uint8_t  BPP;	/*!< Maximum bits per pixel the display supports */
-	LCD_PANEL_OPT  LCD;	/*!< LCD panel type */
-	LCD_COLOR_FORMAT_OPT  color_format;	/*!<BGR or RGB */
-	uint8_t  Dual;	/*!< Dual panel, 1 = dual panel display */
-} LCD_Config_Type;
-
-/**
- * @brief LCD Cursor Size
- */
-typedef enum {
-	LCD_CURSOR_32x32 = 0,
-	LCD_CURSOR_64x64
-} LCD_CURSOR_SIZE_OPT;
-
-/**
- * @brief	Enable Controller Interrupt
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	ints	: OR'ed interrupt bits to enable
- * @return	None
- */
-STATIC INLINE void IP_LCD_EnableInts(IP_LCD_001_Type *LCDx, uint32_t ints)
-{
-	LCDx->INTMSK = ints;
-}
-
-/**
- * @brief	Disable Controller Interrupt
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	ints	: OR'ed interrupt bits to disable
- * @return	None
- */
-STATIC INLINE void IP_LCD_DisableInts(IP_LCD_001_Type *LCDx, uint32_t ints)
-{
-	LCDx->INTMSK = LCDx->INTMSK & ~(ints);
-}
-
-/**
- * @brief	Clear Controller Interrupt
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	ints	: OR'ed interrupt bits to clear
- * @return	None
- */
-STATIC INLINE void IP_LCD_ClearInts(IP_LCD_001_Type *LCDx, uint32_t ints)
-{
-	LCDx->INTCLR = LCDx->INTMSK & (ints);
-}
-
-/**
- * @brief	Initialize the LCD controller
- * @param	LCDx				: pointer to LCD Controller Reg Struct
- * @param	LCD_ConfigStruct	: Pointer to LCD configuration
- * @return  LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
- */
-void IP_LCD_Init(IP_LCD_001_Type *LCDx, LCD_Config_Type *LCD_ConfigStruct);
-
-/**
- * @brief	Power the LCD Panel (power pin)
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	OnOff	: true to power on, false to power off
- * @return	None
- */
-void IP_LCD_Power(IP_LCD_001_Type *LCDx, FunctionalState OnOff);
-
-/**
- * @brief	Enable/Disable the LCD Controller
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	EnDis	: true to enable, false to disable
- * @return	None
- */
-void IP_LCD_Enable(IP_LCD_001_Type *LCDx, FunctionalState EnDis);
-
-/**
- * @brief	Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
- *			Buffer for Dual Panel
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	buffer	: address of buffer
- * @return	None
- */
-void IP_LCD_SetUPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer);
-
-/**
- * @brief	Set LCD Lower Panel Frame Buffer for Dual Panel
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	buffer	: address of buffer
- * @return	None
- */
-void IP_LCD_SetLPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer);
-
-/**
- * @brief	Configure Cursor
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	cursor_size	: specify size of cursor
- *                  - LCD_CURSOR_32x32	:cursor size is 32x32 pixels
- *                  - LCD_CURSOR_64x64	:cursor size is 64x64 pixels
- * @param	sync		: cursor sync mode
- *                  - TRUE	:cursor sync to the frame sync pulse
- *                  - FALSE	:cursor async mode
- * @return	None
- */
-void IP_LCD_Cursor_Config(IP_LCD_001_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, bool sync);
-
-/**
- * @brief	Get Internal Cursor Image Buffer Address
- * @param	LCDx		: pointer to LCD Controller Reg Struct
- * @param	cursor_num	: specify number of cursor is going to be written
- *							this param must < 4
- * @return	Cursor Image Buffer Address
- */
-void *IP_LCD_Cursor_GetImageBufferAddress(IP_LCD_001_Type *LCDx, uint8_t cursor_num);
-
-/**
- * @brief	Enable Cursor
- * @param	LCDx		: pointer to LCD Controller Reg Struct
- * @param	cursor_num	: specify number of cursor is going to be written
- *							this param must < 4
- * @param	OnOff		: true to turn on LCD, false to turn off
- * @return	None
- */
-void IP_LCD_Cursor_Enable(IP_LCD_001_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff);
-
-/**
- * @brief	Load Cursor Palette
- * @param	LCDx			: pointer to LCD Controller Reg Struct
- * @param	palette_color	: cursor palette 0 value
- * @return	None
- */
-void IP_LCD_Cursor_LoadPalette0(IP_LCD_001_Type *LCDx, uint32_t palette_color);
-
-/**
- * @brief	Load Cursor Palette
- * @param	LCDx			: pointer to LCD Controller Reg Struct
- * @param	palette_color	: cursor palette 1 value
- * @return	None
- */
-void IP_LCD_Cursor_LoadPalette1(IP_LCD_001_Type *LCDx, uint32_t palette_color);
-
-/**
- * @brief	Set Cursor Position
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	x		: horizontal position
- * @param	y		: vertical position
- * @return	None
- */
-void IP_LCD_Cursor_SetPos(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y);
-
-/**
- * @brief	Set Cursor Clipping Position
- * @param	LCDx	: pointer to LCD Controller Reg Struct
- * @param	x		: horizontal position, should be in range: 0..63
- * @param	y		: vertical position, should be in range: 0..63
- * @return	None
- */
-void IP_LCD_Cursor_SetClip(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y);
-
-/**
- * @brief	Load a color Palette entry
- * @param	LCDx			: pointer to LCD Controller Reg Struct
- * @param	palette_addr	: Address of palette table to load from
- * @param	index			: palette entry index to load
- * @return	None
- */
-void IP_LCD_Color_LoadPalette(IP_LCD_001_Type *LCDx, uint32_t *palette_addr, uint32_t index);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LCD_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/lpc_types.h b/bsp/xplorer4330/libraries/lpc_ip/lpc_types.h
deleted file mode 100644
index 2ab79575ca..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/lpc_types.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * @brief Common types used in LPC functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LPC_TYPES_H_
-#define __LPC_TYPES_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-/** @defgroup LPC_Types IP: LPC Common Types
- * @ingroup IP_Drivers
- * @{
- */
-
-/** @defgroup LPC_Types_Public_Types LPC Public Types
- * @{
- */
-
-/**
- * @brief Boolean Type definition
- */
-typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
-
-/**
- * @brief Boolean Type definition
- */
-#if !defined(__cplusplus)
-// typedef enum {false = 0, true = !false} bool;
-#endif
-
-/**
- * @brief Flag Status and Interrupt Flag Status type definition
- */
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
-#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
-
-/**
- * @brief Functional State Definition
- */
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
-
-/**
- * @ Status type definition
- */
-typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
-
-/**
- * Read/Write transfer type mode (Block or non-block)
- */
-typedef enum {
-	NONE_BLOCKING = 0,		/**< None Blocking type */
-	BLOCKING,				/**< Blocking type */
-} TRANSFER_BLOCK_Type;
-
-/** Pointer to Function returning Void (any number of parameters) */
-typedef void (*PFV)();
-
-/** Pointer to Function returning int32_t (any number of parameters) */
-typedef int32_t (*PFI)();
-
-/**
- * @}
- */
-
-/** @defgroup LPC_Types_Public_Macros  LPC Public Macros
- * @{
- */
-
-/* _BIT(n) sets the bit at position "n"
- * _BIT(n) is intended to be used in "OR" and "AND" expressions:
- * e.g., "(_BIT(3) | _BIT(7))".
- */
-#undef _BIT
-/* Set bit macro */
-#define _BIT(n) (1 << (n))
-
-/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
- * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
- * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
- */
-#undef _SBF
-/* Set bit field macro */
-#define _SBF(f, v) ((v) << (f))
-
-/* _BITMASK constructs a symbol with 'field_width' least significant
- * bits set.
- * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
- * The symbol is intended to be used to limit the bit field width
- * thusly:
- * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
- * If "any_expression" results in a value that is larger than can be
- * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
- * used with the _SBF example above, the example would be written:
- * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
- * This ensures that the value written to a_reg is no wider than
- * 16 bits, and makes the code easier to read and understand.
- */
-#undef _BITMASK
-/* Bitmask creation macro */
-#define _BITMASK(field_width) ( _BIT(field_width) - 1)
-
-/* NULL pointer */
-#ifndef NULL
-#define NULL ((void *) 0)
-#endif
-
-/* Number of elements in an array */
-#define NELEMENTS(array)  (sizeof(array) / sizeof(array[0]))
-
-/* Static data/function define */
-#define STATIC static
-/* External data/function define */
-#define EXTERN extern
-
-#if !defined(MAX)
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-#endif
-#if !defined(MIN)
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#endif
-
-/**
- * @}
- */
-
-/* Old Type Definition compatibility */
-/** @addtogroup LPC_Types_Public_Types
- * @{
- */
-
-/** LPC type for character type */
-typedef char CHAR;
-
-/** LPC type for 8 bit unsigned value */
-typedef uint8_t UNS_8;
-
-/** LPC type for 8 bit signed value */
-typedef int8_t INT_8;
-
-/** LPC type for 16 bit unsigned value */
-typedef uint16_t UNS_16;
-
-/** LPC type for 16 bit signed value */
-typedef int16_t INT_16;
-
-/** LPC type for 32 bit unsigned value */
-typedef uint32_t UNS_32;
-
-/** LPC type for 32 bit signed value */
-typedef int32_t INT_32;
-
-/** LPC type for 64 bit signed value */
-typedef int64_t INT_64;
-
-/** LPC type for 64 bit unsigned value */
-typedef uint64_t UNS_64;
-
-#ifdef __CODE_RED
-#define BOOL_32 bool
-#define BOOL_16 bool
-#define BOOL_8  bool
-#else
-/** 32 bit boolean type */
-typedef bool BOOL_32;
-
-/** 16 bit boolean type */
-typedef bool BOOL_16;
-
-/** 8 bit boolean type */
-typedef bool BOOL_8;
-#endif
-
-#ifdef __CC_ARM
-#define INLINE  __inline
-#else
-#define INLINE inline
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* __LPC_TYPES_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h b/bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h
deleted file mode 100644
index 764f44a7d7..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * @brief Motor Control PWM registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __MCPWM_001_H_
-#define __MCPWM_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_MCPWM_001 IP: MCPWM register block and driver
- * @ingroup IP_Drivers
- * Motor Control PWM
- * @{
- */
-
-/**
- * @brief Motor Control PWM register block structure
- */
-typedef struct {					/*!< MCPWM Structure        */
-	__I  uint32_t  CON;				/*!< PWM Control read address */
-	__O  uint32_t  CON_SET;			/*!< PWM Control set address */
-	__O  uint32_t  CON_CLR;			/*!< PWM Control clear address */
-	__I  uint32_t  CAPCON;			/*!< Capture Control read address */
-	__O  uint32_t  CAPCON_SET;		/*!< Capture Control set address */
-	__O  uint32_t  CAPCON_CLR;		/*!< Event Control clear address */
-	__IO uint32_t TC[3];			/*!< Timer Counter register */
-	__IO uint32_t LIM[3];			/*!< Limit register         */
-	__IO uint32_t MAT[3];			/*!< Match register         */
-	__IO uint32_t  DT;				/*!< Dead time register     */
-	__IO uint32_t  CCP;				/*!< Communication Pattern register */
-	__I  uint32_t CAP[3];			/*!< Capture register       */
-	__I  uint32_t  INTEN;			/*!< Interrupt Enable read address */
-	__O  uint32_t  INTEN_SET;		/*!< Interrupt Enable set address */
-	__O  uint32_t  INTEN_CLR;		/*!< Interrupt Enable clear address */
-	__I  uint32_t  CNTCON;			/*!< Count Control read address */
-	__O  uint32_t  CNTCON_SET;		/*!< Count Control set address */
-	__O  uint32_t  CNTCON_CLR;		/*!< Count Control clear address */
-	__I  uint32_t  INTF;			/*!< Interrupt flags read address */
-	__O  uint32_t  INTF_SET;		/*!< Interrupt flags set address */
-	__O  uint32_t  INTF_CLR;		/*!< Interrupt flags clear address */
-	__O  uint32_t  CAP_CLR;			/*!< Capture clear address  */
-} IP_MCPWM_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MCPWM_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/pmc_001.h b/bsp/xplorer4330/libraries/lpc_ip/pmc_001.h
deleted file mode 100644
index 6d6fcb3d24..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/pmc_001.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * @brief Power Management Controller registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __PMC_001_H_
-#define __PMC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_PMC_001 IP: PMC register block and driver
- * @ingroup IP_Drivers
- * Power Management Controller
- * @{
- */
-
-/**
- * @brief Power Management Controller register block structure
- */
-typedef struct {						/*!< PMC Structure          */
-	__IO uint32_t  PD0_SLEEP0_HW_ENA;	/*!< Hardware sleep event enable register */
-	__I  uint32_t  RESERVED0[6];
-	__IO uint32_t  PD0_SLEEP0_MODE;		/*!< Sleep power mode register */
-} IP_PMC_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __PMC_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/qei_001.h b/bsp/xplorer4330/libraries/lpc_ip/qei_001.h
deleted file mode 100644
index 90ec5cd513..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/qei_001.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * @brief Quadrature Encoder Interface Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __QEI_001_H_
-#define __QEI_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_QEI_001 IP: QEI register block and driver
- * @ingroup IP_Drivers
- * Quadrature Encoder Interface
- * @{
- */
-
-/**
- * @brief Quadrature Encoder Interface register block structure
- */
-typedef struct {				/*!< QEI Structure          */
-	__O  uint32_t  CON;			/*!< Control register       */
-	__I  uint32_t  STAT;		/*!< Encoder status register */
-	__IO uint32_t  CONF;		/*!< Configuration register */
-	__I  uint32_t  POS;			/*!< Position register      */
-	__IO uint32_t  MAXPOS;		/*!< Maximum position register */
-	__IO uint32_t  CMPOS0;		/*!< position compare register 0 */
-	__IO uint32_t  CMPOS1;		/*!< position compare register 1 */
-	__IO uint32_t  CMPOS2;		/*!< position compare register 2 */
-	__I  uint32_t  INXCNT;		/*!< Index count register   */
-	__IO uint32_t  INXCMP0;		/*!< Index compare register 0 */
-	__IO uint32_t  LOAD;		/*!< Velocity timer reload register */
-	__I  uint32_t  TIME;		/*!< Velocity timer register */
-	__I  uint32_t  VEL;			/*!< Velocity counter register */
-	__I  uint32_t  CAP;			/*!< Velocity capture register */
-	__IO uint32_t  VELCOMP;		/*!< Velocity compare register */
-	__IO uint32_t  FILTERPHA;	/*!< Digital filter register on input phase A (QEI_A) */
-	__IO uint32_t  FILTERPHB;	/*!< Digital filter register on input phase B (QEI_B) */
-	__IO uint32_t  FILTERINX;	/*!< Digital filter register on input index (QEI_IDX) */
-	__IO uint32_t  WINDOW;		/*!< Index acceptance window register */
-	__IO uint32_t  INXCMP1;		/*!< Index compare register 1 */
-	__IO uint32_t  INXCMP2;		/*!< Index compare register 2 */
-	__I  uint32_t  RESERVED0[993];
-	__O  uint32_t  IEC;			/*!< Interrupt enable clear register */
-	__O  uint32_t  IES;			/*!< Interrupt enable set register */
-	__I  uint32_t  INTSTAT;		/*!< Interrupt status register */
-	__I  uint32_t  IE;			/*!< Interrupt enable register */
-	__O  uint32_t  CLR;			/*!< Interrupt status clear register */
-	__O  uint32_t  SET;			/*!< Interrupt status set register */
-} IP_QEI_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __QEI_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/regfile_001.h b/bsp/xplorer4330/libraries/lpc_ip/regfile_001.h
deleted file mode 100644
index 832a0c1fd7..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/regfile_001.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * @brief Register File registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __REGFILE_001_H_
-#define __REGFILE_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_REGFILE_001 IP: REGFILE register block and driver
- * @ingroup IP_Drivers
- * Register File
- * @{
- */
-
-/**
- * @brief Register File register block structure
- */
-typedef struct {
-	__IO uint32_t REGFILE[64];	/*!< General purpose storage register */
-} IP_REGFILE_001_T;
-
-/**
- * @brief	Write value to General purpose registers
- * @param	pREG	: Pointer to regfile block
- * @param	index	: General purpose register index
- * @param	value	: Value to write
- * @return	None
- * Note: These General purpose registers can be used to store important
- * information when the main power supply is off. The value in these
- * registers is not affected by chip reset. These registers are usually
- * powered in the RTC power domain.
- */
-STATIC INLINE void IP_REGFILE_Write(IP_REGFILE_001_T *pREG, int index, uint32_t value)
-{
-	pREG->REGFILE[index] = value;
-}
-
-/**
- * @brief	Read value from General purpose registers
- * @param	pREG	: Pointer to regfile block
- * @param	index	: General purpose register index
- * @return	Read value
- * These General purpose registers can be used to store important
- * information when the main power supply is off. The value in these
- * registers is not affected by chip reset. These registers are usually
- * powered in the RTC power domain.
- */
-STATIC INLINE uint32_t IP_REGFILE_Read(IP_REGFILE_001_T *pREG, int index)
-{
-	return pREG->REGFILE[index];
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __REGFILE_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.c b/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.c
deleted file mode 100644
index 613fb7f45d..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * @brief Repetitive Interrupt Timer registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "ritimer_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the RIT */
-void IP_RIT_Init(IP_RITIMER_001_Type *RITx)
-{
-	RITx->COMPVAL = 0xFFFFFFFF;
-	RITx->MASK  = 0x00000000;
-	RITx->CTRL  = 0x0C;
-	RITx->COUNTER   = 0x00000000;
-}
-
-/* DeInitialize the RIT */
-void IP_RIT_DeInit(IP_RITIMER_001_Type *RITx)
-{
-	IP_RIT_Init(RITx);
-}
-
-/* Enable/Disable Timer */
-void IP_RIT_Enable(IP_RITIMER_001_Type *RITx, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		RITx->CTRL |= RIT_CTRL_TEN;
-	}
-	else {
-		RITx->CTRL &= ~RIT_CTRL_TEN;
-	}
-}
-
-/* Enable or disable timer debug */
-void IP_RIT_TimerDebugCmd(IP_RITIMER_001_Type *RITx, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		RITx->CTRL |= RIT_CTRL_ENBR;
-	}
-	else {
-		RITx->CTRL &= ~RIT_CTRL_ENBR;
-	}
-}
-
-/* Check whether interrupt is pending */
-IntStatus IP_RIT_GetIntStatus(IP_RITIMER_001_Type *RITx)
-{
-	uint8_t result;
-
-	if ((RITx->CTRL & RIT_CTRL_INT) == 1) {
-		result = SET;
-	}
-	else {
-		return RESET;
-	}
-
-	return (IntStatus) result;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.h b/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.h
deleted file mode 100644
index 56aaf66a84..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * @brief Repetitive Interrupt Timer registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RITIMER_001_H_
-#define __RITIMER_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_RITIMER_001 IP: RITimer register block and driver
- * @ingroup IP_Drivers
- * Repetitive Interrupt Timer
- * @{
- */
-
-/**
- * @brief Repetitive Interrupt Timer register block structure
- */
-typedef struct {				/*!< RITIMER Structure      */
-	__IO uint32_t  COMPVAL;		/*!< Compare register       */
-	__IO uint32_t  MASK;		/*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
-	__IO uint32_t  CTRL;		/*!< Control register.      */
-	__IO uint32_t  COUNTER;		/*!< 32-bit counter         */
-} IP_RITIMER_001_Type;
-
-/**
- * @brief RITIMER register support bitfields and mask
- */
-
-/*
- * RIT control register
- */
-/**	Set by H/W when the counter value equals the masked compare value */
-#define RIT_CTRL_INT    ((uint32_t) (1))
-/** Set timer enable clear to 0 when the counter value equals the masked compare value  */
-#define RIT_CTRL_ENCLR  ((uint32_t) _BIT(1))
-/** Set timer enable on debug */
-#define RIT_CTRL_ENBR   ((uint32_t) _BIT(2))
-/** Set timer enable */
-#define RIT_CTRL_TEN    ((uint32_t) _BIT(3))
-
-/**
- * @brief	Initialize the RIT
- * @param	RITx	: RIT peripheral selected
- * @return	None
- */
-void IP_RIT_Init(IP_RITIMER_001_Type *RITx);
-
-/**
- * @brief	DeInitialize the RIT
- * @param	RITx	: RIT peripheral selected
- * @return	None
- */
-void IP_RIT_DeInit(IP_RITIMER_001_Type *RITx);
-
-/**
- * @brief	Enable/Disable Timer
- * @param	RITx		: RIT peripheral selected
- * @param	NewState	: ENABLE to enable RITimer, DISABLE to disable
- * @return	None
- */
-void IP_RIT_Enable(IP_RITIMER_001_Type *RITx, FunctionalState NewState);
-
-/**
- * @brief	Timer Enable/Disable on debug
- * @param	RITx 		: RIT peripheral selected
- * @param	NewState	: ENABLE to halt timer whenever a hardware break condition occurs
- * @return	None
- */
-void IP_RIT_TimerDebugCmd(IP_RITIMER_001_Type *RITx, FunctionalState NewState);
-
-/**
- * @brief	Check whether interrupt flag is set or not
- * @param	RITx	: RIT peripheral selected
- * @return	Current interrupt status, could be SET or UNSET
- */
-IntStatus IP_RIT_GetIntStatus(IP_RITIMER_001_Type *RITx);
-
-/**
- * @brief	Set a tick value for the interrupt to time out
- * @param	RITx	: RIT peripheral selected
- * @param	val		: value (in ticks) of the interrupt to be set
- * @return	None
- */
-STATIC INLINE void IP_RIT_SetCOMPVAL(IP_RITIMER_001_Type *RITx, uint32_t val)
-{
-	RITx->COMPVAL = val;
-}
-
-/**
- * @brief	Enables or clears the RIT or interrupt
- * @param	RITx	: RIT peripheral selected
- * @param	val		: RIT to be set, one or more RIT_CTRL_* values
- * @return	None
- */
-STATIC INLINE void IP_RIT_EnableCTRL(IP_RITIMER_001_Type *RITx, uint32_t val)
-{
-	RITx->CTRL |= val;
-}
-
-/**
- * @brief	Get the RIT Counter value
- * @param	RITx	: RIT peripheral selected
- * @return	the counter value
- */
-STATIC INLINE uint32_t IP_RIT_GetCounter(IP_RITIMER_001_Type *RITx)
-{
-	return RITx->COUNTER;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RITIMER_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/rtc_001.c b/bsp/xplorer4330/libraries/lpc_ip/rtc_001.c
deleted file mode 100644
index e09e723088..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/rtc_001.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * @brief Real Time Clock registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "rtc_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the the RTC peripheral */
-void IP_RTC_Init(IP_RTC_001_T *pRTC)
-{
-	do {
-		/* Reset RTC clock*/
-		pRTC->CCR = RTC_CCR_CTCRST | RTC_CCR_CCALEN;
-	} while (pRTC->CCR != (RTC_CCR_CTCRST | RTC_CCR_CCALEN));
-	do {
-		/* Finish resetting RTC clock */
-		pRTC->CCR = RTC_CCR_CCALEN;
-	} while (pRTC->CCR != RTC_CCR_CCALEN);
-
-	/* Clear counter increment and alarm interrupt */
-	pRTC->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF;
-	while (pRTC->ILR != 0) {}
-
-	/* Clear all register to be default */
-	pRTC->CIIR = 0x00;
-	pRTC->AMR = 0xFF;
-	pRTC->CALIBRATION = 0x00;
-}
-
-/* Reset clock tick counter in the RTC peripheral */
-void IP_RTC_ResetClockTickCounter(IP_RTC_001_T *pRTC)
-{
-	pRTC->CCR |= RTC_CCR_CTCRST;
-	pRTC->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;
-}
-
-/* Start/Stop RTC peripheral */
-void IP_RTC_Enable(IP_RTC_001_T *pRTC, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		do {
-			pRTC->CCR |= RTC_CCR_CLKEN;
-		} while ((pRTC->CCR & RTC_CCR_CLKEN) == 0);
-	}
-	else {
-		pRTC->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
-	}
-}
-
-/* Enable/Disable Counter increment interrupt for a time type in the RTC peripheral */
-void IP_RTC_CntIncrIntConfig(IP_RTC_001_T *pRTC, uint32_t cntrMask,
-							 FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pRTC->CIIR |= cntrMask;
-	}
-
-	else {
-		pRTC->CIIR &= (~cntrMask) & RTC_AMR_CIIR_BITMASK;
-		while (pRTC->CIIR & cntrMask) {}
-	}
-
-}
-
-/* Enable/Disable Alarm interrupt for a time type in the RTC peripheral */
-void IP_RTC_AlarmIntConfig(IP_RTC_001_T *pRTC, uint32_t alarmMask,
-						   FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pRTC->AMR &= (~alarmMask) & RTC_AMR_CIIR_BITMASK;
-	}
-	else {
-		pRTC->AMR |= (alarmMask);
-		while ((pRTC->AMR & alarmMask) == 0) {}
-	}
-}
-
-/* Set current time value for a time type in the RTC peripheral */
-void IP_RTC_SetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
-{
-	pRTC->TIME[Timetype] = TimeValue;
-}
-
-/* Get current time value for a type time type */
-uint32_t IP_RTC_GetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype)
-{
-	return pRTC->TIME[Timetype];
-}
-
-/* Set full time in the RTC peripheral */
-void IP_RTC_SetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_TIMEINDEX_T i;
-	uint32_t secs = 0xFF;
-
-	/* Write time to registers and verify second tick didn't update during the
-	   write cycle. If it did, the time may not be consistent across all fields,
-	   so write the time again */
-	while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) {
-		/* Write seconds first */
-		for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
-			pRTC->TIME[i] = pFullTime->time[i];
-		}
-
-		secs = pRTC->TIME[RTC_TIMETYPE_SECOND];
-	}
-}
-
-/* Get full time from the RTC peripheral */
-void IP_RTC_GetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_TIMEINDEX_T i;
-	uint32_t secs = 0xFF;
-
-	/* Read full time, but verify second tick didn't change during the read. If
-	   it did, re-read the time again so it will be consistent across all fields. */
-	while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) {
-		secs = pFullTime->time[RTC_TIMETYPE_SECOND] = pRTC->TIME[RTC_TIMETYPE_SECOND];
-		for (i = RTC_TIMETYPE_MINUTE; i < RTC_TIMETYPE_LAST; i++) {
-			pFullTime->time[i] = pRTC->TIME[i];
-		}
-	}
-}
-
-/* Set alarm time value for a time type */
-void IP_RTC_SetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
-{
-	pRTC->ALRM[Timetype] = ALValue;
-}
-
-/* Get alarm time value for a time */
-uint32_t IP_RTC_GetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype)
-{
-	return pRTC->ALRM[Timetype];
-}
-
-/* Set full alarm time in the RTC peripheral */
-void IP_RTC_SetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_TIMEINDEX_T i;
-
-	for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
-		pRTC->ALRM[i] = pFullTime->time[i];
-	}
-}
-
-/* Get full alarm time in the RTC peripheral */
-void IP_RTC_GetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
-	IP_RTC_TIMEINDEX_T i;
-
-	for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
-		pFullTime->time[i] = pRTC->ALRM[i];
-	}
-}
-
-/* Enable/Disable calibration counter in the RTC peripheral */
-void IP_RTC_CalibCounterCmd(IP_RTC_001_T *pRTC, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		do {
-			pRTC->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;
-		} while (pRTC->CCR & RTC_CCR_CCALEN);
-	}
-	else {
-		pRTC->CCR |= RTC_CCR_CCALEN;
-	}
-}
-
-/* Configures Calibration in the RTC peripheral */
-void IP_RTC_CalibConfig(IP_RTC_001_T *pRTC, uint32_t CalibValue, uint8_t CalibDir)
-{
-	pRTC->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK)
-						| ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/rtc_001.h b/bsp/xplorer4330/libraries/lpc_ip/rtc_001.h
deleted file mode 100644
index 890a6af98c..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/rtc_001.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
- * @brief Real Time Clock registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RTC_001_H_
-#define __RTC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_RTC_001 IP: RTC register block and driver
- * @ingroup IP_Drivers
- * Real Time Clock
- * @{
- */
-
-/**
- * @brief RTC time type option
- */
-typedef enum {
-	RTC_TIMETYPE_SECOND,		/*!< Second */
-	RTC_TIMETYPE_MINUTE,		/*!< Month */
-	RTC_TIMETYPE_HOUR,			/*!< Hour */
-	RTC_TIMETYPE_DAYOFMONTH,	/*!< Day of month */
-	RTC_TIMETYPE_DAYOFWEEK,		/*!< Day of week */
-	RTC_TIMETYPE_DAYOFYEAR,		/*!< Day of year */
-	RTC_TIMETYPE_MONTH,			/*!< Month */
-	RTC_TIMETYPE_YEAR,			/*!< Year */
-	RTC_TIMETYPE_LAST
-} IP_RTC_TIMEINDEX_T;
-
-/**
- * @brief Real Time Clock register block structure
- */
-typedef struct {							/*!< RTC Structure          */
-	__O  uint32_t  ILR;						/*!< Interrupt Location Register */
-	__I  uint32_t  RESERVED0;
-	__IO uint32_t  CCR;						/*!< Clock Control Register */
-	__IO uint32_t  CIIR;					/*!< Counter Increment Interrupt Register */
-	__IO uint32_t  AMR;						/*!< Alarm Mask Register    */
-	__I  uint32_t  CTIME[3];				/*!< Consolidated Time Register 0,1,2 */
-	__IO uint32_t  TIME[RTC_TIMETYPE_LAST];	/*!< Timer field registers */
-	__IO uint32_t  CALIBRATION;				/*!< Calibration Value Register */
-#if defined(CHIP_LPC177X_8X)
-	__IO uint32_t GPREG[5];					/*!< General Purpose Storage Registers */
-	__IO uint32_t RTC_AUXEN;				/*!< */
-	__IO uint32_t RTC_AUX;					/*!< */
-#else
-	__I  uint32_t  RESERVED1[7];
-#endif
-	__IO uint32_t  ALRM[RTC_TIMETYPE_LAST];	/*!< Alarm field registers */
-#if defined(CHIP_LPC177X_8X)
-	__IO uint32_t ERSTATUS;
-#endif
-} IP_RTC_001_T;
-
-/**
- * @brief ILR register definitions
- */
-/** ILR register mask */
-#define RTC_ILR_BITMASK         ((0x00000003))
-/** Bit inform the source interrupt is counter increment*/
-#define RTC_IRL_RTCCIF          ((1 << 0))
-/** Bit inform the source interrupt is alarm match*/
-#define RTC_IRL_RTCALF          ((1 << 1))
-
-/**
- * @brief CCR register definitions
- */
-/** CCR register mask */
-#define RTC_CCR_BITMASK         ((0x00000013))
-/** Clock enable */
-#define RTC_CCR_CLKEN           ((1 << 0))
-/** Clock reset */
-#define RTC_CCR_CTCRST          ((1 << 1))
-/** Calibration counter enable */
-#define RTC_CCR_CCALEN          ((1 << 4))
-
-/**
- * @brief CIIR and AMR register definitions
- */
-/** Counter Increment Interrupt bit for second */
-#define RTC_AMR_CIIR_IMSEC          ((1 << 0))
-/** Counter Increment Interrupt bit for minute */
-#define RTC_AMR_CIIR_IMMIN          ((1 << 1))
-/** Counter Increment Interrupt bit for hour */
-#define RTC_AMR_CIIR_IMHOUR         ((1 << 2))
-/** Counter Increment Interrupt bit for day of month */
-#define RTC_AMR_CIIR_IMDOM          ((1 << 3))
-/** Counter Increment Interrupt bit for day of week */
-#define RTC_AMR_CIIR_IMDOW          ((1 << 4))
-/** Counter Increment Interrupt bit for day of year */
-#define RTC_AMR_CIIR_IMDOY          ((1 << 5))
-/** Counter Increment Interrupt bit for month */
-#define RTC_AMR_CIIR_IMMON          ((1 << 6))
-/** Counter Increment Interrupt bit for year */
-#define RTC_AMR_CIIR_IMYEAR         ((1 << 7))
-/** CIIR bit mask */
-#define RTC_AMR_CIIR_BITMASK        ((0xFF))
-
-/**
- * @brief RTC_AUX register definitions
- */
-/** RTC Oscillator Fail detect flag */
-#define RTC_AUX_RTC_OSCF        ((1 << 4))
-
-/**
- * @brief RTC_AUXEN register definitions
- */
-/** Oscillator Fail Detect interrupt enable*/
-#define RTC_AUXEN_RTC_OSCFEN    ((1 << 4))
-
-/**
- * @brief Consolidated Time Register 0 definitions
- */
-#define RTC_CTIME0_SECONDS_MASK     ((0x3F))
-#define RTC_CTIME0_MINUTES_MASK     ((0x3F00))
-#define RTC_CTIME0_HOURS_MASK       ((0x1F0000))
-#define RTC_CTIME0_DOW_MASK         ((0x7000000))
-
-/**
- * @brief Consolidated Time Register 1 definitions
- */
-#define RTC_CTIME1_DOM_MASK         ((0x1F))
-#define RTC_CTIME1_MONTH_MASK       ((0xF00))
-#define RTC_CTIME1_YEAR_MASK        ((0xFFF0000))
-
-/**
- * @brief Consolidated Time Register 2 definitions
- */
-#define RTC_CTIME2_DOY_MASK         ((0xFFF))
-
-/**
- * @brief Time Counter Group and Alarm register group
- */
-/** SEC register mask */
-#define RTC_SEC_MASK            (0x0000003F)
-/** MIN register mask */
-#define RTC_MIN_MASK            (0x0000003F)
-/** HOUR register mask */
-#define RTC_HOUR_MASK           (0x0000001F)
-/** DOM register mask */
-#define RTC_DOM_MASK            (0x0000001F)
-/** DOW register mask */
-#define RTC_DOW_MASK            (0x00000007)
-/** DOY register mask */
-#define RTC_DOY_MASK            (0x000001FF)
-/** MONTH register mask */
-#define RTC_MONTH_MASK          (0x0000000F)
-/** YEAR register mask */
-#define RTC_YEAR_MASK           (0x00000FFF)
-
-#define RTC_SECOND_MAX      59	/*!< Maximum value of second */
-#define RTC_MINUTE_MAX      59	/*!< Maximum value of minute*/
-#define RTC_HOUR_MAX        23	/*!< Maximum value of hour*/
-#define RTC_MONTH_MIN       1	/*!< Minimum value of month*/
-#define RTC_MONTH_MAX       12	/*!< Maximum value of month*/
-#define RTC_DAYOFMONTH_MIN  1	/*!< Minimum value of day of month*/
-#define RTC_DAYOFMONTH_MAX  31	/*!< Maximum value of day of month*/
-#define RTC_DAYOFWEEK_MAX   6	/*!< Maximum value of day of week*/
-#define RTC_DAYOFYEAR_MIN   1	/*!< Minimum value of day of year*/
-#define RTC_DAYOFYEAR_MAX   366	/*!< Maximum value of day of year*/
-#define RTC_YEAR_MAX        4095/*!< Maximum value of year*/
-
-/**
- * @brief Calibration register
- */
-/** Calibration value */
-#define RTC_CALIBRATION_CALVAL_MASK     ((0x1FFFF))
-/** Calibration direction */
-#define RTC_CALIBRATION_LIBDIR          ((1 << 17))
-/** Calibration max value */
-#define RTC_CALIBRATION_MAX             ((0x20000))
-/** Calibration definitions */
-#define RTC_CALIB_DIR_FORWARD           ((uint8_t) (0))
-#define RTC_CALIB_DIR_BACKWARD          ((uint8_t) (1))
-
-/* Check Parameter Definitions */
-/** Macro to determine if it is valid RTC peripheral */
-#define PARAM_pRTC(x)   (((uint32_t *) x) == ((uint32_t *) LPC_RTC))
-
-/* Macro check RTC interrupt type */
-#define PARAM_RTC_INT(n)    ((n == RTC_INT_COUNTER_INCREASE) || (n == RTC_INT_ALARM))
-
-/* Macro check RTC calibration type */
-#define PARAM_RTC_CALIB_DIR(n)  ((n == RTC_CALIB_DIR_FORWARD) || (n == RTC_CALIB_DIR_BACKWARD))
-
-/**
- * @brief RTC enumeration
- */
-
-/** @brief RTC interrupt source */
-typedef enum {
-	RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF,	/*!<  Counter Increment Interrupt */
-	RTC_INT_ALARM = RTC_IRL_RTCALF				/*!< The alarm interrupt */
-} IP_RTC_INT_OPT;
-
-typedef struct {
-	uint32_t time[RTC_TIMETYPE_LAST];
-} IP_RTC_TIME_T;
-
-/**
- * @brief	Initialize the RTC peripheral
- * @param	pRTC	: pointer to RTC peripheral block
- * @return	None
- */
-void IP_RTC_Init(IP_RTC_001_T *pRTC);
-
-/**
- * @brief	De-initialize the RTC peripheral
- * @param	pRTC	: pointer to RTC peripheral block
- * @return	None
- */
-STATIC INLINE void IP_RTC_DeInit(IP_RTC_001_T *pRTC)
-{
-	pRTC->CCR = 0x00;
-}
-
-/**
- * @brief	Reset clock tick counter in the RTC peripheral
- * @param	pRTC	: pointer to RTC peripheral block
- * @return	None
- */
-void IP_RTC_ResetClockTickCounter(IP_RTC_001_T *pRTC);
-
-/**
- * @brief	Start/Stop RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	NewState	:  ENABLE or DISABLE
- * @return	None
- */
-void IP_RTC_Enable(IP_RTC_001_T *pRTC, FunctionalState NewState);
-
-/**
- * @brief	Enable/Disable Counter increment interrupt for a time type in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	cntrMask	: Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
- * @param	NewState		: ENABLE or DISABLE
- * @return	None
- */
-void IP_RTC_CntIncrIntConfig(IP_RTC_001_T *pRTC, uint32_t cntrMask, FunctionalState NewState);
-
-/**
- * @brief	Enable/Disable Alarm interrupt for a time type in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	alarmMask	: Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
- * @param	NewState		: ENABLE or DISABLE
- * @return	None
- */
-void IP_RTC_AlarmIntConfig(IP_RTC_001_T *pRTC, uint32_t alarmMask, FunctionalState NewState);
-
-/**
- * @brief	Set current time value for a time type in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	Timetype	: time field index type to set
- * @param	TimeValue	: Value to palce in time field
- * @return	None
- */
-void IP_RTC_SetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue);
-
-/**
- * @brief	Get current time value for a type time type
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	Timetype	: Time field index type to get
- * @return	Value of time field according to specified time type
- */
-uint32_t IP_RTC_GetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype);
-
-/**
- * @brief	Set full time in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	pFullTime	: Pointer to full time data
- * @return	None
- */
-void IP_RTC_SetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief	Get full time from the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	pFullTime	: Pointer to full time record to fill
- * @return	None
- */
-void IP_RTC_GetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief	Set alarm time value for a time type
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	Timetype	: Time index field to set
- * @param	ALValue		: Alarm time value to set
- * @return	None
- */
-void IP_RTC_SetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue);
-
-/**
- * @brief	Get alarm time value for a time type
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	Timetype	: Time index field to get
- * @return	Value of Alarm time according to specified time type
- */
-uint32_t IP_RTC_GetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype);
-
-/**
- * @brief	Set full alarm time in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	pFullTime	: Pointer to full time record to set alarm
- * @return	None
- */
-void IP_RTC_SetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief	Get full alarm time in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	pFullTime	: Pointer to full time record to fill
- * @return	None
- */
-void IP_RTC_GetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief	Enable/Disable calibration counter in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	NewState	: New State of this function, should be:
- *							- ENABLE	:The calibration counter is enabled and counting
- *							- DISABLE	:The calibration counter is disabled and reset to zero
- * @return		None
- */
-void IP_RTC_CalibCounterCmd(IP_RTC_001_T *pRTC, FunctionalState NewState);
-
-/**
- * @brief	Configures Calibration in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	CalibValue	: Calibration value, should be in range from 0 to 131,072
- * @param	CalibDir : Calibration Direction, should be:
- *						- RTC_CALIB_DIR_FORWARD		:Forward calibration
- *						- RTC_CALIB_DIR_BACKWARD	:Backward calibration
- * @return	None
- */
-void IP_RTC_CalibConfig(IP_RTC_001_T *pRTC, uint32_t CalibValue, uint8_t CalibDir);
-
-/**
- * @brief	Clear specified Location interrupt pending in the RTC peripheral
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	IntType	: Interrupt location type, should be:
- *						- RTC_INT_COUNTER_INCREASE	:Clear Counter Increment Interrupt pending.
- *						- RTC_INT_ALARM				:Clear alarm interrupt pending
- * @return	None
- */
-STATIC INLINE void IP_RTC_ClearIntPending(IP_RTC_001_T *pRTC, uint32_t IntType)
-{
-	pRTC->ILR = IntType;
-}
-
-/**
- * @brief	Check whether if specified location interrupt in the
- *              RTC peripheral is set or not
- * @param	pRTC		: pointer to RTC peripheral block
- * @param	IntType	: Interrupt location type, should be:
- *						- RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
- *						- RTC_INT_ALARM: Alarm generated an interrupt.
- * @return	Current state of specified interrupt in RTC peripheral, SET or RESET
- */
-STATIC INLINE IntStatus IP_RTC_GetIntPending(IP_RTC_001_T *pRTC, uint32_t IntType)
-{
-	return (pRTC->ILR & IntType) ? SET : RESET;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RTC_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/sct_001.h b/bsp/xplorer4330/libraries/lpc_ip/sct_001.h
deleted file mode 100644
index cf4449fdcc..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/sct_001.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-* @brief State Configurable Timer registers and control functions
-*
-* @note
-* Copyright(C) NXP Semiconductors, 2012
-* All rights reserved.
-*
-* @par
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* LPC products.  This software is supplied "AS IS" without any warranties of
-* any kind, and NXP Semiconductors and its licensor disclaim any and 
-* all warranties, express or implied, including all implied warranties of 
-* merchantability, fitness for a particular purpose and non-infringement of 
-* intellectual property rights.  NXP Semiconductors assumes no responsibility
-* or liability for the use of the software, conveys no license or rights under any
-* patent, copyright, mask work right, or any other intellectual property rights in 
-* or to any products. NXP Semiconductors reserves the right to make changes
-* in the software without notification. NXP Semiconductors also makes no 
-* representation or warranty that such application will be suitable for the
-* specified use without further testing or modification.
-* 
-* @par
-* Permission to use, copy, modify, and distribute this software and its 
-* documentation is hereby granted, under NXP Semiconductors' and its 
-* licensor's relevant copyrights in the software, without fee, provided that it 
-* is used in conjunction with NXP Semiconductors microcontrollers.  This 
-* copyright, permission, and disclaimer notice must appear in all copies of 
-* this code.
-*/
-
-#ifndef __SCT_001_H_
-#define __SCT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-/** @defgroup IP_SCT_001 IP: SCT register block and driver
- * @ingroup IP_Drivers
- * State Configurable Timer
- * @{
- */
-
-#define CONFIG_SCT_nEV   (16)            /* Number of events */
-#define CONFIG_SCT_nRG   (16)            /* Number of match/compare registers */
-#define CONFIG_SCT_nOU   (16)            /* Number of outputs */
-
-/**
-  * @brief State Configurable Timer register block structure
-  */
-typedef struct
-{
-    __IO  uint32_t CONFIG;              /* Configuration Register */
-    union {
-        __IO uint32_t CTRL_U;           /* Control Register */
-        struct {
-            __IO uint16_t CTRL_L;       /* low control register */
-            __IO uint16_t CTRL_H;       /* high control register */
-        };
-    };
-    __IO uint16_t LIMIT_L;              /* limit register for counter L */
-    __IO uint16_t LIMIT_H;              /* limit register for counter H */
-    __IO uint16_t HALT_L;               /* halt register for counter L */
-    __IO uint16_t HALT_H;               /* halt register for counter H */
-    __IO uint16_t STOP_L;               /* stop register for counter L */
-    __IO uint16_t STOP_H;               /* stop register for counter H */
-    __IO uint16_t START_L;              /* start register for counter L */
-    __IO uint16_t START_H;              /* start register for counter H */
-         uint32_t RESERVED1[10];        /* 0x03C reserved */
-    union {
-        __IO uint32_t COUNT_U;          /* counter register */
-        struct {
-            __IO uint16_t COUNT_L;      /* counter register for counter L */
-            __IO uint16_t COUNT_H;      /* counter register for counter H */
-        };
-    };
-    __IO uint16_t STATE_L;              /* state register for counter L */
-    __IO uint16_t STATE_H;              /* state register for counter H */
-    __I  uint32_t INPUT;                /* input register */
-    __IO uint16_t REGMODE_L;            /* match - capture registers mode register L */
-    __IO uint16_t REGMODE_H;            /* match - capture registers mode register H */
-    __IO uint32_t OUTPUT;               /* output register */
-    __IO uint32_t OUTPUTDIRCTRL;        /* output counter direction Control Register */
-    __IO uint32_t RES;                  /* conflict resolution register */
-    __IO uint32_t DMA0REQUEST;          /* DMA0 Request Register */
-    __IO uint32_t DMA1REQUEST;          /* DMA1 Request Register */
-         uint32_t RESERVED2[35];
-    __IO uint32_t EVEN;                 /* event enable register */
-    __IO uint32_t EVFLAG;               /* event flag register */
-    __IO uint32_t CONEN;                /* conflict enable register */
-    __IO uint32_t CONFLAG;              /* conflict flag register */
-    union {
-        __IO union {                    /* ... Match / Capture value */
-            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
-            };
-        } MATCH[CONFIG_SCT_nRG];
-        __I union {
-            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
-            };
-        } CAP[CONFIG_SCT_nRG];
-    };
-    uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
-    union {
-        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
-        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
-    };
-    uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
-    union {
-        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
-        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
-    };
-    uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
-    union {
-        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
-            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
-            };
-        } MATCHREL[CONFIG_SCT_nRG];
-        __IO union {
-            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
-            };
-        } CAPCTRL[CONFIG_SCT_nRG];
-    };
-    uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
-    union {
-        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
-        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
-    };
-    uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
-    union {
-        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
-        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
-    };
-    uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
-    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
-        uint32_t STATE;                 /* Event State Register */
-        uint32_t CTRL;                  /* Event Control Register */
-    } EVENT[CONFIG_SCT_nEV];
-    uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
-    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
-        uint32_t SET;                   /* Output n Set Register */
-        uint32_t CLR;                   /* Output n Clear Register */
-    } OUT[CONFIG_SCT_nOU];
-    uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
-    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
-} IP_SCT_001_Type;
-
-/**
- * @}
- */
- 
-#ifdef __cplusplus
-}
-#endif 
-
-#endif /* __SCT_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c b/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c
deleted file mode 100644
index c46cf7c9ce..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * @brief	SD/SDIO (MCI) registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "sdmmc_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the MCI card controller */
-void IP_SDMMC_Init(IP_SDMMC_001_Type *pSDMMC)
-{
-	/* Software reset */
-	pSDMMC->BMOD = MCI_BMOD_SWR;
-
-	/* reset all blocks */
-	pSDMMC->CTRL = MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET;
-	while (pSDMMC->CTRL & (MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET)) {}
-
-	/* Internal DMA setup for control register */
-	pSDMMC->CTRL = MCI_CTRL_USE_INT_DMAC | MCI_CTRL_INT_ENABLE;
-	pSDMMC->INTMASK = 0;
-
-	/* Clear the interrupts for the host controller */
-	pSDMMC->RINTSTS = 0xFFFFFFFF;
-
-	/* Put in max timeout */
-	pSDMMC->TMOUT = 0xFFFFFFFF;
-
-	/* FIFO threshold settings for DMA, DMA burst of 4,   FIFO watermark at 16 */
-	pSDMMC->FIFOTH = MCI_FIFOTH_DMA_MTS_4 | MCI_FIFOTH_RX_WM((SD_FIFO_SZ / 2) - 1) | MCI_FIFOTH_TX_WM(SD_FIFO_SZ / 2);
-
-	/* Enable internal DMA, burst size of 4, fixed burst */
-	pSDMMC->BMOD = MCI_BMOD_DE | MCI_BMOD_PBL4 | MCI_BMOD_DSL(4);
-
-	/* disable clock to CIU (needs latch) */
-	pSDMMC->CLKENA = 0;
-	pSDMMC->CLKSRC = 0;
-}
-
-/* Close the MCI */
-void IP_SDMMC_DeInit(IP_SDMMC_001_Type *pSDMMC)
-{}
-
-/* Set block size for transfer */
-void IP_SDMMC_SetBlkSize(IP_SDMMC_001_Type *pSDMMC, uint32_t bytes)
-{
-	pSDMMC->BLKSIZ = bytes;
-}
-
-/* Reset card in slot */
-void IP_SDMMC_Reset(IP_SDMMC_001_Type *pSDMMC, int32_t reset)
-{
-	if (reset) {
-		pSDMMC->RST_N = 1;
-	}
-	else {
-		pSDMMC->RST_N = 0;
-	}
-}
-
-/* Enable or disable slot power */
-void IP_SDMMC_PowerOnOff(IP_SDMMC_001_Type *pSDMMC, int32_t enable)
-{
-	if (enable) {
-		pSDMMC->PWREN = 1;
-	}
-	else {
-		pSDMMC->PWREN = 0;
-	}
-}
-
-/* Detect if write protect is enabled */
-int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_Type *pSDMMC)
-{
-	if (pSDMMC->WRTPRT & 1) {
-		return 1;
-	}
-	return 0;
-}
-
-/* Detect if an SD card is inserted */
-int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_Type *pSDMMC)
-{
-	/* No card = high state in regsiter */
-	if (pSDMMC->CDETECT & 1) {
-		return 0;
-	}
-
-	return 1;
-}
-
-/* Function to send command to Card interface unit (CIU) */
-int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg)
-{
-	volatile int32_t tmo = 50;
-	volatile int delay;
-
-	/* set command arg reg*/
-	pSDMMC->CMDARG = arg;
-	pSDMMC->CMD = MCI_CMD_START | cmd;
-
-	/* poll untill command is accepted by the CIU */
-	while (--tmo && (pSDMMC->CMD & MCI_CMD_START)) {
-		if (tmo & 1) {
-			delay = 50;
-		}
-		else {
-			delay = 18000;
-		}
-
-		while (--delay > 1) {}
-	}
-
-	return (tmo < 1) ? 1 : 0;
-}
-
-/* Read the response from the last command */
-void IP_SDMMC_GetResponse(IP_SDMMC_001_Type *pSDMMC, uint32_t *resp)
-{
-	/* on this chip response is not a fifo so read all 4 regs */
-	resp[0] = pSDMMC->RESP0;
-	resp[1] = pSDMMC->RESP1;
-	resp[2] = pSDMMC->RESP2;
-	resp[3] = pSDMMC->RESP3;
-}
-
-/* Sets the SD bus clock speed */
-void IP_SDMMC_SetClock(IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed)
-{
-	/* compute SD/MMC clock dividers */
-	uint32_t div;
-
-	div = ((clk_rate / speed) + 2) >> 1;
-
-	if ((div == pSDMMC->CLKDIV) && pSDMMC->CLKENA) {
-		return;	/* Closest speed is already set */
-
-	}
-	/* disable clock */
-	pSDMMC->CLKENA = 0;
-
-	/* User divider 0 */
-	pSDMMC->CLKSRC = MCI_CLKSRC_CLKDIV0;
-
-	/* inform CIU */
-	IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0);
-
-	/* set divider 0 to desired value */
-	pSDMMC->CLKDIV = MCI_CLOCK_DIVIDER(0, div);
-
-	/* inform CIU */
-	IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0);
-
-	/* enable clock */
-	pSDMMC->CLKENA = MCI_CLKEN_ENABLE;
-
-	/* inform CIU */
-	IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0);
-}
-
-/* Function to set card type */
-void IP_SDMMC_SetCardType(IP_SDMMC_001_Type *pSDMMC, uint32_t ctype)
-{
-	pSDMMC->CTYPE = ctype;
-}
-
-/* Function to clear interrupt & FIFOs */
-void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_Type *pSDMMC)
-{
-	/* reset all blocks */
-	pSDMMC->CTRL |= MCI_CTRL_FIFO_RESET;
-
-	/* wait till resets clear */
-	while (pSDMMC->CTRL & MCI_CTRL_FIFO_RESET) {}
-
-	/* Clear interrupt status */
-	pSDMMC->RINTSTS = 0xFFFFFFFF;
-}
-
-/* Returns the raw SD interface interrupt status */
-uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_Type *pSDMMC)
-{
-	return pSDMMC->RINTSTS;
-}
-
-/* Sets the raw SD interface interrupt status */
-void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal)
-{
-	pSDMMC->RINTSTS = iVal;
-}
-
-/* Sets the SD interface interrupt mask */
-void IP_SDMMC_SetIntMask(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal)
-{
-	pSDMMC->INTMASK = iVal;
-}
-
-/* Setup DMA descriptors */
-void IP_SDMMC_DmaSetup(IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size)
-{
-	int i = 0;
-	uint32_t ctrl, maxs;
-
-	/* Reset DMA */
-	pSDMMC->CTRL |= MCI_CTRL_DMA_RESET | MCI_CTRL_FIFO_RESET;
-	while (pSDMMC->CTRL & MCI_CTRL_DMA_RESET) {}
-
-	/* Build a descriptor list using the chained DMA method */
-	while (size > 0) {
-		/* Limit size of the transfer to maximum buffer size */
-		maxs = size;
-		if (maxs > MCI_DMADES1_MAXTR) {
-			maxs = MCI_DMADES1_MAXTR;
-		}
-		size -= maxs;
-
-		/* Set buffer size */
-		psdif_dev->mci_dma_dd[i].des1 = MCI_DMADES1_BS1(maxs);
-
-		/* Setup buffer address (chained) */
-		psdif_dev->mci_dma_dd[i].des2 = addr + (i * MCI_DMADES1_MAXTR);
-
-		/* Setup basic control */
-		ctrl = MCI_DMADES0_OWN | MCI_DMADES0_CH;
-		if (i == 0) {
-			ctrl |= MCI_DMADES0_FS;	/* First DMA buffer */
-
-		}
-		/* No more data? Then this is the last descriptor */
-		if (!size) {
-			ctrl |= MCI_DMADES0_LD;
-		}
-		else {
-			ctrl |= MCI_DMADES0_DIC;
-		}
-
-		/* Another descriptor is needed */
-		psdif_dev->mci_dma_dd[i].des3 = (uint32_t) &psdif_dev->mci_dma_dd[i + 1];
-		psdif_dev->mci_dma_dd[i].des0 = ctrl;
-
-		i++;
-	}
-
-	/* Set DMA derscriptor base address */
-	pSDMMC->DBADDR = (uint32_t) &psdif_dev->mci_dma_dd[0];
-}
-
-/**
- * @brief	Sets the transfer block size
- * @param	pSDMMC		: Pointer to IP_SDMMC_001_Type structure
- * @param	blk_size	: Block Size value
- * @return	None
- */
-void IP_SDMMC_SetBlockSize(IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size)
-{
-	/* set block size and byte count */
-	pSDMMC->BLKSIZ = blk_size;
-	pSDMMC->BYTCNT = blk_size;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h b/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h
deleted file mode 100644
index 20fbe77a95..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * @brief SD/SDIO (MCI) registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDMMC_001_H_
-#define __SDMMC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SDMMC_001 IP: SDMMC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief SD/MMC & SDIO register block structure
- */
-typedef struct {				/*!< SDMMC Structure        */
-	__IO uint32_t  CTRL;		/*!< Control Register       */
-	__IO uint32_t  PWREN;		/*!< Power Enable Register  */
-	__IO uint32_t  CLKDIV;		/*!< Clock Divider Register */
-	__IO uint32_t  CLKSRC;		/*!< SD Clock Source Register */
-	__IO uint32_t  CLKENA;		/*!< Clock Enable Register  */
-	__IO uint32_t  TMOUT;		/*!< Timeout Register       */
-	__IO uint32_t  CTYPE;		/*!< Card Type Register     */
-	__IO uint32_t  BLKSIZ;		/*!< Block Size Register    */
-	__IO uint32_t  BYTCNT;		/*!< Byte Count Register    */
-	__IO uint32_t  INTMASK;		/*!< Interrupt Mask Register */
-	__IO uint32_t  CMDARG;		/*!< Command Argument Register */
-	__IO uint32_t  CMD;			/*!< Command Register       */
-	__I  uint32_t  RESP0;		/*!< Response Register 0    */
-	__I  uint32_t  RESP1;		/*!< Response Register 1    */
-	__I  uint32_t  RESP2;		/*!< Response Register 2    */
-	__I  uint32_t  RESP3;		/*!< Response Register 3    */
-	__I  uint32_t  MINTSTS;		/*!< Masked Interrupt Status Register */
-	__IO uint32_t  RINTSTS;		/*!< Raw Interrupt Status Register */
-	__I  uint32_t  STATUS;		/*!< Status Register        */
-	__IO uint32_t  FIFOTH;		/*!< FIFO Threshold Watermark Register */
-	__I  uint32_t  CDETECT;		/*!< Card Detect Register   */
-	__I  uint32_t  WRTPRT;		/*!< Write Protect Register */
-	__IO uint32_t  GPIO;		/*!< General Purpose Input/Output Register */
-	__I  uint32_t  TCBCNT;		/*!< Transferred CIU Card Byte Count Register */
-	__I  uint32_t  TBBCNT;		/*!< Transferred Host to BIU-FIFO Byte Count Register */
-	__IO uint32_t  DEBNCE;		/*!< Debounce Count Register */
-	__IO uint32_t  USRID;		/*!< User ID Register       */
-	__I  uint32_t  VERID;		/*!< Version ID Register    */
-	__I  uint32_t  RESERVED0;
-	__IO uint32_t  UHS_REG;		/*!< UHS-1 Register         */
-	__IO uint32_t  RST_N;		/*!< Hardware Reset         */
-	__I  uint32_t  RESERVED1;
-	__IO uint32_t  BMOD;		/*!< Bus Mode Register      */
-	__O  uint32_t  PLDMND;		/*!< Poll Demand Register   */
-	__IO uint32_t  DBADDR;		/*!< Descriptor List Base Address Register */
-	__IO uint32_t  IDSTS;		/*!< Internal DMAC Status Register */
-	__IO uint32_t  IDINTEN;		/*!< Internal DMAC Interrupt Enable Register */
-	__I  uint32_t  DSCADDR;		/*!< Current Host Descriptor Address Register */
-	__I  uint32_t  BUFADDR;		/*!< Current Buffer Descriptor Address Register */
-} IP_SDMMC_001_Type;
-
-/** @brief  SDIO DMA descriptor control (des0) register defines
- */
-#define MCI_DMADES0_OWN         (1UL << 31)		/*!< DMA owns descriptor bit */
-#define MCI_DMADES0_CES         (1 << 30)		/*!< Card Error Summary bit */
-#define MCI_DMADES0_ER          (1 << 5)		/*!< End of descriptopr ring bit */
-#define MCI_DMADES0_CH          (1 << 4)		/*!< Second address chained bit */
-#define MCI_DMADES0_FS          (1 << 3)		/*!< First descriptor bit */
-#define MCI_DMADES0_LD          (1 << 2)		/*!< Last descriptor bit */
-#define MCI_DMADES0_DIC         (1 << 1)		/*!< Disable interrupt on completion bit */
-
-/** @brief  SDIO DMA descriptor size (des1) register defines
- */
-#define MCI_DMADES1_BS1(x)      (x)				/*!< Size of buffer 1 */
-#define MCI_DMADES1_BS2(x)      ((x) << 13)		/*!< Size of buffer 2 */
-#define MCI_DMADES1_MAXTR       4096			/*!< Max transfer size per buffer */
-
-/** @brief  SDIO control register defines
- */
-#define MCI_CTRL_USE_INT_DMAC   (1 << 25)		/*!< Use internal DMA */
-#define MCI_CTRL_CARDV_MASK     (0x7 << 16)		/*!< SD_VOLT[2:0} pins output state mask */
-#define MCI_CTRL_CEATA_INT_EN   (1 << 11)		/*!< Enable CE-ATA interrupts */
-#define MCI_CTRL_SEND_AS_CCSD   (1 << 10)		/*!< Send auto-stop */
-#define MCI_CTRL_SEND_CCSD      (1 << 9)		/*!< Send CCSD */
-#define MCI_CTRL_ABRT_READ_DATA (1 << 8)		/*!< Abort read data */
-#define MCI_CTRL_SEND_IRQ_RESP  (1 << 7)		/*!< Send auto-IRQ response */
-#define MCI_CTRL_READ_WAIT      (1 << 6)		/*!< Assert read-wait for SDIO */
-#define MCI_CTRL_INT_ENABLE     (1 << 4)		/*!< Global interrupt enable */
-#define MCI_CTRL_DMA_RESET      (1 << 2)		/*!< Reset internal DMA */
-#define MCI_CTRL_FIFO_RESET     (1 << 1)		/*!< Reset data FIFO pointers */
-#define MCI_CTRL_RESET          (1 << 0)		/*!< Reset controller */
-
-/** @brief SDIO Power Enable register defines
- */
-#define MCI_POWER_ENABLE        0x1				/*!< Enable slot power signal (SD_POW) */
-
-/** @brief SDIO Clock divider register defines
- */
-#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8))	/*!< Set cklock divider */
-
-/** @brief SDIO Clock source register defines
- */
-#define MCI_CLKSRC_CLKDIV0      0
-#define MCI_CLKSRC_CLKDIV1      1
-#define MCI_CLKSRC_CLKDIV2      2
-#define MCI_CLKSRC_CLKDIV3      3
-#define MCI_CLK_SOURCE(clksrc)  (clksrc)		/*!< Set cklock divider source */
-
-/** @brief SDIO Clock Enable register defines
- */
-#define MCI_CLKEN_LOW_PWR       (1 << 16)		/*!< Enable clock idle for slot */
-#define MCI_CLKEN_ENABLE        (1 << 0)		/*!< Enable slot clock */
-
-/** @brief SDIO time-out register defines
- */
-#define MCI_TMOUT_DATA(clks)    ((clks) << 8)	/*!< Data timeout clocks */
-#define MCI_TMOUT_DATA_MSK      0xFFFFFF00
-#define MCI_TMOUT_RESP(clks)    ((clks) & 0xFF)	/*!< Response timeout clocks */
-#define MCI_TMOUT_RESP_MSK      0xFF
-
-/** @brief SDIO card-type register defines
- */
-#define MCI_CTYPE_8BIT          (1 << 16)		/*!< Enable 4-bit mode */
-#define MCI_CTYPE_4BIT          (1 << 0)		/*!< Enable 8-bit mode */
-
-/** @brief SDIO Interrupt status & mask register defines
- */
-#define MCI_INT_SDIO            (1 << 16)		/*!< SDIO interrupt */
-#define MCI_INT_EBE             (1 << 15)		/*!< End-bit error */
-#define MCI_INT_ACD             (1 << 14)		/*!< Auto command done */
-#define MCI_INT_SBE             (1 << 13)		/*!< Start bit error */
-#define MCI_INT_HLE             (1 << 12)		/*!< Hardware locked error */
-#define MCI_INT_FRUN            (1 << 11)		/*!< FIFO overrun/underrun error */
-#define MCI_INT_HTO             (1 << 10)		/*!< Host data starvation error */
-#define MCI_INT_DTO             (1 << 9)		/*!< Data timeout error */
-#define MCI_INT_RTO             (1 << 8)		/*!< Response timeout error */
-#define MCI_INT_DCRC            (1 << 7)		/*!< Data CRC error */
-#define MCI_INT_RCRC            (1 << 6)		/*!< Response CRC error */
-#define MCI_INT_RXDR            (1 << 5)		/*!< RX data ready */
-#define MCI_INT_TXDR            (1 << 4)		/*!< TX data needed */
-#define MCI_INT_DATA_OVER       (1 << 3)		/*!< Data transfer over */
-#define MCI_INT_CMD_DONE        (1 << 2)		/*!< Command done */
-#define MCI_INT_RESP_ERR        (1 << 1)		/*!< Command response error */
-#define MCI_INT_CD              (1 << 0)		/*!< Card detect */
-
-/** @brief SDIO Command register defines
- */
-#define MCI_CMD_START           (1UL << 31)		/*!< Start command */
-#define MCI_CMD_VOLT_SWITCH     (1 << 28)		/*!< Voltage switch bit */
-#define MCI_CMD_BOOT_MODE       (1 << 27)		/*!< Boot mode */
-#define MCI_CMD_DISABLE_BOOT    (1 << 26)		/*!< Disable boot */
-#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25)		/*!< Expect boot ack */
-#define MCI_CMD_ENABLE_BOOT     (1 << 24)		/*!< Enable boot */
-#define MCI_CMD_CCS_EXP         (1 << 23)		/*!< CCS expected */
-#define MCI_CMD_CEATA_RD        (1 << 22)		/*!< CE-ATA read in progress */
-#define MCI_CMD_UPD_CLK         (1 << 21)		/*!< Update clock register only */
-#define MCI_CMD_INIT            (1 << 15)		/*!< Send init sequence */
-#define MCI_CMD_STOP            (1 << 14)		/*!< Stop/abort command */
-#define MCI_CMD_PRV_DAT_WAIT    (1 << 13)		/*!< Wait before send */
-#define MCI_CMD_SEND_STOP       (1 << 12)		/*!< Send auto-stop */
-#define MCI_CMD_STRM_MODE       (1 << 11)		/*!< Stream transfer mode */
-#define MCI_CMD_DAT_WR          (1 << 10)		/*!< Read(0)/Write(1) selection */
-#define MCI_CMD_DAT_EXP         (1 << 9)		/*!< Data expected */
-#define MCI_CMD_RESP_CRC        (1 << 8)		/*!< Check response CRC */
-#define MCI_CMD_RESP_LONG       (1 << 7)		/*!< Response length */
-#define MCI_CMD_RESP_EXP        (1 << 6)		/*!< Response expected */
-#define MCI_CMD_INDX(n)         ((n) & 0x1F)
-
-/** @brief SDIO status register definess
- */
-#define MCI_STS_GET_FCNT(x)     (((x) >> 17) & 0x1FF)
-
-/** @brief SDIO FIFO threshold defines
- */
-#define MCI_FIFOTH_TX_WM(x)     ((x) & 0xFFF)
-#define MCI_FIFOTH_RX_WM(x)     (((x) & 0xFFF) << 16)
-#define MCI_FIFOTH_DMA_MTS_1    (0UL << 28)
-#define MCI_FIFOTH_DMA_MTS_4    (1UL << 28)
-#define MCI_FIFOTH_DMA_MTS_8    (2UL << 28)
-#define MCI_FIFOTH_DMA_MTS_16   (3UL << 28)
-#define MCI_FIFOTH_DMA_MTS_32   (4UL << 28)
-#define MCI_FIFOTH_DMA_MTS_64   (5UL << 28)
-#define MCI_FIFOTH_DMA_MTS_128  (6UL << 28)
-#define MCI_FIFOTH_DMA_MTS_256  (7UL << 28)
-
-/** @brief Bus mode register defines
- */
-#define MCI_BMOD_PBL1           (0 << 8)		/*!< Burst length = 1 */
-#define MCI_BMOD_PBL4           (1 << 8)		/*!< Burst length = 4 */
-#define MCI_BMOD_PBL8           (2 << 8)		/*!< Burst length = 8 */
-#define MCI_BMOD_PBL16          (3 << 8)		/*!< Burst length = 16 */
-#define MCI_BMOD_PBL32          (4 << 8)		/*!< Burst length = 32 */
-#define MCI_BMOD_PBL64          (5 << 8)		/*!< Burst length = 64 */
-#define MCI_BMOD_PBL128         (6 << 8)		/*!< Burst length = 128 */
-#define MCI_BMOD_PBL256         (7 << 8)		/*!< Burst length = 256 */
-#define MCI_BMOD_DE             (1 << 7)		/*!< Enable internal DMAC */
-#define MCI_BMOD_DSL(len)       ((len) << 2)	/*!< Descriptor skip length */
-#define MCI_BMOD_FB             (1 << 1)		/*!< Fixed bursts */
-#define MCI_BMOD_SWR            (1 << 0)		/*!< Software reset of internal registers */
-
-/** @brief Commonly used definitions
- */
-#define SD_FIFO_SZ              32				/*!< Size of SDIO FIFOs (32-bit wide) */
-
-/** Function prototype for SD interface IRQ callback */
-typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
-
-/** Function prototype for SD detect and write protect status check */
-typedef int32_t (*PSCHECK_FUNC_T)(void);
-
-/** Function prototype for SD slot power enable or slot reset */
-typedef void (*PS_POWER_FUNC_T)(int32_t enable);
-
-/** @brief  SDIO chained DMA descriptor
- */
-typedef struct {
-	volatile uint32_t des0;						/*!< Control and status */
-	volatile uint32_t des1;						/*!< Buffer size(s) */
-	volatile uint32_t des2;						/*!< Buffer address pointer 1 */
-	volatile uint32_t des3;						/*!< Buffer address pointer 2 */
-} pSDMMC_DMA_Type;
-
-/** @brief  SDIO device type
- */
-typedef struct _sdif_device {
-	// MCI_IRQ_CB_FUNC_T irq_cb;
-	pSDMMC_DMA_Type mci_dma_dd[1 + (0x10000 / MCI_DMADES1_MAXTR)];
-	// uint32_t sdio_clk_rate;
-	// uint32_t sdif_slot_clk_rate;
-	// int32_t clock_enabled;
-} sdif_device;
-
-/**
- * @brief	Initializes the MCI card controller
- * @param	pSDMMC Pointer to IP_SDMMC_001_Type structure
- * @return	None
- */
-void IP_SDMMC_Init(IP_SDMMC_001_Type *pSDMMC);
-
-/**
- * @brief	Close the MCI
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @return	None
- */
-void IP_SDMMC_DeInit(IP_SDMMC_001_Type *pSDMMC);
-
-/**
- * @brief	Set block size for transfer
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	bytes	: block size in bytes
- * @return	None
- */
-void IP_SDMMC_SetBlkSize(IP_SDMMC_001_Type *pSDMMC, uint32_t bytes);
-
-/**
- * @brief	Reset card in slot
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	reset	: Sets SD_RST to passed state
- * @return	None
- * Reset card in slot, must manually de-assert reset after assertion
- * (Uses SD_RST pin, set per reset parameter state)
- */
-void IP_SDMMC_Reset(IP_SDMMC_001_Type *pSDMMC, int32_t reset);
-
-/**
- * @brief	Enable or disable slot power
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	enable	: !0 to enable, or 0 to disable
- * @return	None
- * Enable or disable slot power, !0 = enable slot power
- * (Uses SD_POW pin, set to high or low based on enable parameter state)
- */
-void IP_SDMMC_PowerOnOff(IP_SDMMC_001_Type *pSDMMC, int32_t enable);
-
-/**
- * @brief	Detect if write protect is enabled
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @return	Returns 1 if card is write protected, otherwise 0
- * Detect if write protect is enabled
- * (uses SD_WP pin, returns 1 if card is write protected)
- */
-int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_Type *pSDMMC);
-
-/**
- * @brief	Detect if an SD card is inserted
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @return	Returns 0 if a card is detected, otherwise 1
- * Detect if an SD card is inserted
- * (uses SD_CD pin, returns 0 on card detect)
- */
-int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_Type *pSDMMC);
-
-/**
- * @brief	Function to send command to Card interface unit (CIU)
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	cmd		: Command with all flags set
- * @param	arg		: Argument for the command
- * @return	TRUE on times-out, otherwise FALSE
- */
-int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg);
-
-/**
- * @brief	Read the response from the last command
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	resp	: Pointer to response array to fill
- * @return	None
- */
-void IP_SDMMC_GetResponse(IP_SDMMC_001_Type *pSDMMC, uint32_t *resp);
-
-/**
- * @brief	Sets the SD bus clock speed
- * @param	pSDMMC		: Pointer to IP_SDMMC_001_Type structure
- * @param	clk_rate	: Input clock rate into the IP block
- * @param	speed		: Desired clock speed to the card
- * @return	None
- */
-void IP_SDMMC_SetClock(IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed);
-
-/**
- * @brief	Function to set card type
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	ctype	: card type
- * @return	None
- */
-void IP_SDMMC_SetCardType(IP_SDMMC_001_Type *pSDMMC, uint32_t ctype);
-
-/**
- * @brief	Function to clear interrupt & FIFOs
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @return	None
- */
-void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_Type *pSDMMC);
-
-/**
- * @brief	Returns the raw SD interface interrupt status
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @return	Raw interrupt status of Or'ed values MCI_INT_*
- */
-uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_Type *pSDMMC);
-
-/**
- * @brief	Sets the raw SD interface interrupt status
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	iVal	: Raw interrupts to set, Or'ed values MCI_INT_*
- * @return	None
- */
-void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal);
-
-/**
- * @brief	Sets the SD interface interrupt mask
- * @param	pSDMMC	: Pointer to IP_SDMMC_001_Type structure
- * @param	iVal	: Interrupts to enable, Or'ed values MCI_INT_*
- * @return	None
- */
-void IP_SDMMC_SetIntMask(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal);
-
-/**
- * @brief	Setup DMA descriptors
- * @param	pSDMMC		: Pointer to IP_SDMMC_001_Type structure
- * @param	psdif_dev	: SD interface device
- * @param	addr		: Address of buffer (source or destination)
- * @param	size		: size of buffer in bytes (64K max)
- * @return	None
- */
-void IP_SDMMC_DmaSetup(IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);
-
-/* Sets the transfer block size */
-void IP_SDMMC_SetBlockSize(IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SDMMC_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h b/bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h
deleted file mode 100644
index 2829608a77..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * @brief Serial GPIO registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SGPIO_001_H_
-#define __SGPIO_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SGPIO_001 IP: SGPIO register block and driver
- * @ingroup IP_Drivers
- * Serial GPIO
- * @{
- */
-
-/**
- * @brief Serial GPIO register block structure
- */
-typedef struct {						/*!< SGPIO Structure        */
-	__IO uint32_t  OUT_MUX_CFG[16];		/*!< Pin multiplexer configurationregisters. */
-	__IO uint32_t  SGPIO_MUX_CFG[16];	/*!< SGPIO multiplexer configuration registers. */
-	__IO uint32_t  SLICE_MUX_CFG[16];	/*!< Slice multiplexer configuration registers. */
-	__IO uint32_t  REG[16];				/*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
-	__IO uint32_t  REG_SS[16];			/*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
-	__IO uint32_t  PRESET[16];			/*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
-	__IO uint32_t  COUNT[16];			/*!< Down counter, counts down each clock cycle. */
-	__IO uint32_t  POS[16];				/*!< Each time COUNT0 reaches 0x0 */
-	__IO uint32_t  MASK_A;				/*!< Mask for pattern match function of slice A */
-	__IO uint32_t  MASK_H;				/*!< Mask for pattern match function of slice H */
-	__IO uint32_t  MASK_I;				/*!< Mask for pattern match function of slice I */
-	__IO uint32_t  MASK_P;				/*!< Mask for pattern match function of slice P */
-	__I  uint32_t  GPIO_INREG;			/*!< GPIO input status register */
-	__IO uint32_t  GPIO_OUTREG;			/*!< GPIO output control register */
-	__IO uint32_t  GPIO_OENREG;			/*!< GPIO OE control register */
-	__IO uint32_t  CTRL_ENABLED;		/*!< Enables the slice COUNT counter */
-	__IO uint32_t  CTRL_DISABLED;		/*!< Disables the slice COUNT counter */
-	__I  uint32_t  RESERVED0[823];
-	__O  uint32_t  CLR_EN_0;			/*!< Shift clock interrupt clear mask */
-	__O  uint32_t  SET_EN_0;			/*!< Shift clock interrupt set mask */
-	__I  uint32_t  ENABLE_0;			/*!< Shift clock interrupt enable */
-	__I  uint32_t  STATUS_0;			/*!< Shift clock interrupt status */
-	__O  uint32_t  CTR_STATUS_0;		/*!< Shift clock interrupt clear status */
-	__O  uint32_t  SET_STATUS_0;		/*!< Shift clock interrupt set status */
-	__I  uint32_t  RESERVED1[2];
-	__O  uint32_t  CLR_EN_1;			/*!< Capture clock interrupt clear mask */
-	__O  uint32_t  SET_EN_1;			/*!< Capture clock interrupt set mask */
-	__I  uint32_t  ENABLE_1;			/*!< Capture clock interrupt enable */
-	__I  uint32_t  STATUS_1;			/*!< Capture clock interrupt status */
-	__O  uint32_t  CTR_STATUS_1;		/*!< Capture clock interrupt clear status */
-	__O  uint32_t  SET_STATUS_1;		/*!< Capture clock interrupt set status */
-	__I  uint32_t  RESERVED2[2];
-	__O  uint32_t  CLR_EN_2;			/*!< Pattern match interrupt clear mask */
-	__O  uint32_t  SET_EN_2;			/*!< Pattern match interrupt set mask */
-	__I  uint32_t  ENABLE_2;			/*!< Pattern match interrupt enable */
-	__I  uint32_t  STATUS_2;			/*!< Pattern match interrupt status */
-	__O  uint32_t  CTR_STATUS_2;		/*!< Pattern match interrupt clear status */
-	__O  uint32_t  SET_STATUS_2;		/*!< Pattern match interrupt set status */
-	__I  uint32_t  RESERVED3[2];
-	__O  uint32_t  CLR_EN_3;			/*!< Input interrupt clear mask */
-	__O  uint32_t  SET_EN_3;			/*!< Input bit match interrupt set mask */
-	__I  uint32_t  ENABLE_3;			/*!< Input bit match interrupt enable */
-	__I  uint32_t  STATUS_3;			/*!< Input bit match interrupt status */
-	__O  uint32_t  CTR_STATUS_3;		/*!< Input bit match interrupt clear status */
-	__O  uint32_t  SET_STATUS_3;		/*!< Shift clock interrupt set status */
-} IP_SGPIO_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SGPIO_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/spi_001.h b/bsp/xplorer4330/libraries/lpc_ip/spi_001.h
deleted file mode 100644
index ace81bc74b..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/spi_001.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * @brief SPI registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SPI_001_H_
-#define __SPI_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SPI_001 IP: SPI register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief SPI register block structure
- */
-typedef struct {					/*!< SPI Structure          */
-	__IO uint32_t  CR;				/*!< SPI Control Register. This register controls the operation of the SPI. */
-	__I  uint32_t  SR;				/*!< SPI Status Register. This register shows the status of the SPI. */
-	__IO uint32_t  DR;				/*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
-	__IO uint32_t  CCR;				/*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
-	__I  uint32_t  RESERVED0[3];
-	__IO uint32_t  INT;				/*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
-} IP_SPI_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SPI_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/spifi_001.h b/bsp/xplorer4330/libraries/lpc_ip/spifi_001.h
deleted file mode 100644
index ebeefab9bc..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/spifi_001.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
-* @brief SPIFI registers and control functions
-*
-* @note
-* Copyright(C) NXP Semiconductors, 2012
-* All rights reserved.
-*
-* @par
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* LPC products.  This software is supplied "AS IS" without any warranties of
-* any kind, and NXP Semiconductors and its licensor disclaim any and 
-* all warranties, express or implied, including all implied warranties of 
-* merchantability, fitness for a particular purpose and non-infringement of 
-* intellectual property rights.  NXP Semiconductors assumes no responsibility
-* or liability for the use of the software, conveys no license or rights under any
-* patent, copyright, mask work right, or any other intellectual property rights in 
-* or to any products. NXP Semiconductors reserves the right to make changes
-* in the software without notification. NXP Semiconductors also makes no 
-* representation or warranty that such application will be suitable for the
-* specified use without further testing or modification.
-* 
-* @par
-* Permission to use, copy, modify, and distribute this software and its 
-* documentation is hereby granted, under NXP Semiconductors' and its 
-* licensor's relevant copyrights in the software, without fee, provided that it 
-* is used in conjunction with NXP Semiconductors microcontrollers.  This 
-* copyright, permission, and disclaimer notice must appear in all copies of 
-* this code.
-*/
-
-#ifndef __SPIFI_001_H_
-#define __SPIFI_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-#include "spifi_rom_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-// FIXME this file needs work and better explanations
-
-/** @defgroup IP_SPIFI_001 IP: SPIFI register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-extern void cancel_mem_mode(SPIFIobj *obj);
-extern void (*set_mem_mode)   (SPIFIobj *obj);
-
-  /* mid level functions */
-extern int32_t checkAd(SPIFIobj *obj, SPIFIopers *opers);
-extern int32_t setProt(SPIFIobj *obj, SPIFIopers *opers, char *change, 
-                        char *saveProt);
-extern int32_t check_block(SPIFIobj *obj, char *source, SPIFIopers *opers, 
-                        uint32_t check_program);
-extern int32_t send_erase_cmd(SPIFIobj *obj, uint8_t op, uint32_t addr);
-extern uint32_t ck_erase(SPIFIobj *obj, uint32_t *addr, uint32_t length);
-extern int32_t prog_block(SPIFIobj *obj, char *source, SPIFIopers *opers, 
-                        uint32_t *left_in_page);
-extern uint32_t ck_prog(SPIFIobj *obj, char *source, char *dest, uint32_t length);
-
-  /* low level functions */
-extern void setSize(SPIFIobj *obj, int32_t value);
-extern int32_t setDev(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, 
-                        uint32_t prog_cmd);
-extern uint32_t cmd(uc op, uc addrLen, uc intLen, uint16_t len);
-extern uint32_t readAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr);
-extern void send04(SPIFIobj *obj, uc op, uc len, uint32_t value);
-extern void wren_sendAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
-extern int32_t write_stat(SPIFIobj *obj, uc len, uint16_t value);
-extern int32_t wait_busy(SPIFIobj *obj, uc prog_or_erase);
-
-/** 
- * @brief 	This call sends the standardized Read JEDEC ID command to the
- *			attached serial Flash device.  If it responds, it is set up for reading
- *			in ARM memory space.
- * @param 	obj		: Pointer to uninitialized SPIFIobj structure
- * @param 	csHigh	: Value that is one less than the minimum number of clock
- *						cycles with the CS pin high, that the SPIFI should maintain between
- *						commands. Compute this from the SPIFI clock period and the minimum high
- *						time of CS from the serial flash data sheet:
- *						csHigh = ceiling( min CS high / SPIFI clock period) - 1
- * @param	options	: contains bits controlling the SPIFI behavior.	See @ref IP_SPIFI_OPTIONS
- * @param	mhz		: should be the serial clock divided by 1000000.
- * @return	A return value of zero indicates success. Non-zero error codes indicate various error states.
- */
-STATIC INLINE int32_t IP_SPIFI_Init(SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz)
-{
-	return spifi_init(obj, csHigh, options, mhz);
-}
-
-/** 
- * @brief	This call programs opers.length bytes in the serial flash. An
- *			IP_SPIFI_Program call with source equal to opers.dest and opers.options
- *			not including S_FORCE_ERASE can be used to protect or unprotect sectors
- *			depending on the value of opers.protect.
- * @param	obj		: Pointer to initialized SPIFIobj structure (from IP_SPIFI_Init)
- * @param	source	: is the address of the data to be programmed
- * @param	opers	: specifies programming and erasing options
- * @return	A return value of zero indicates success. Non-zero error codes
- *			indicate various error states.
- */
-STATIC INLINE int32_t IP_SPIFI_Program(SPIFIobj *obj, char *source, SPIFIopers *opers)
-{
-	return spifi_program(obj, source, opers);
-}
-
-/** 
- * @brief	This call erases opers.length bytes in the serial flash.
- * @param	obj		: Pointer to initialized SPIFIobj structure (from IP_SPIFI_Init)
- * @param	opers	: specifies erasing options
- * @return	A return value of zero indicates success. Non-zero error codes
- *			indicate various error states.
- */
-STATIC INLINE int32_t IP_SPIFI_Erase(SPIFIobj *obj, SPIFIopers *opers)
-{
-	return spifi_erase(obj, opers);
-}
-
-/** 
- * @brief	: This function disables the memory mapping of the external QSPI flash.
- * @param	obj	: Pointer to initialized SPIFIobj structure (from IP_SPIFI_Init)
- * @return	No return value
- */
-STATIC INLINE void IP_SPIFI_CancelMemMode(SPIFIobj *obj)
-{
-	cancel_mem_mode(obj);
-}
-
-STATIC INLINE void IP_SPIFI_SetMemMode(SPIFIobj *obj)
-{
-	set_mem_mode(obj);
-}
-
-  /* mid level functions */
-STATIC INLINE int32_t IP_SPIFI_checkAd(SPIFIobj *obj, SPIFIopers *opers)
-{
-	return checkAd(obj, opers);
-}
-
-STATIC INLINE int32_t IP_SPIFI_setProt(SPIFIobj *obj, SPIFIopers *opers, char *change, char *saveProt)
-{
-	return setProt(obj, opers, change, saveProt);
-}
-
-STATIC INLINE int32_t IP_SPIFI_CheckBlock(SPIFIobj *obj, char *source, SPIFIopers *opers,
-                        uint32_t check_program)
-{
-	return check_block(obj, source, opers, check_program);
-}
-
-STATIC INLINE int32_t IP_SPIFI_SendEraseCmd(SPIFIobj *obj, uint8_t op, uint32_t addr)
-{
-	return send_erase_cmd(obj, op, addr);
-}
-
-STATIC INLINE uint32_t IP_SPIFI_CkErase(SPIFIobj *obj, uint32_t *addr, uint32_t length)
-{
-	return ck_erase(obj, addr, length);
-}
-
-STATIC INLINE int32_t IP_SPIFI_ProgBlock(SPIFIobj *obj, char *source, SPIFIopers *opers,
-                        uint32_t *left_in_page)
-{
-	return prog_block(obj, source, opers, left_in_page);
-}
-
-STATIC INLINE uint32_t IP_SPIFI_CkProg(SPIFIobj *obj, char *source, char *dest, uint32_t length)
-{
-	return ck_prog(obj, source, dest, length);
-}
-
-  /* low level functions */
-STATIC INLINE void IP_SPIFI_SetSize(SPIFIobj *obj, int32_t value)
-{
-	setSize(obj, value);
-}
-
-STATIC INLINE int32_t IP_SPIFI_SetDev(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
-                        uint32_t prog_cmd)
-{
-	return setDev(obj, opts, mem_cmd, prog_cmd);
-}
-
-STATIC INLINE uint32_t IP_SPIFI_Cmd(uc op, uc addrLen, uc intLen, uint16_t len)
-{
-	return cmd(op, addrLen, intLen, len);
-}
-
-STATIC INLINE uint32_t IP_SPIFI_ReadAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr)
-{
-	return readAd(obj, cmd, addr);
-}
-
-STATIC INLINE void IP_SPIFI_Send04(SPIFIobj *obj, uc op, uc len, uint32_t value)
-{
-	send04(obj, op, len, value);
-}
-
-STATIC INLINE void IP_SPIFI_WrEnSendAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value)
-{
-	wren_sendAd(obj, cmd, addr, value);
-}
-
-STATIC INLINE int32_t IP_SPIFI_WriteStat(SPIFIobj *obj, uc len, uint16_t value)
-{
-	return write_stat(obj, len, value);
-}
-
-STATIC INLINE int32_t IP_SPIFI_WaitBusy(SPIFIobj *obj, uc prog_or_erase)
-{
-	return wait_busy(obj, prog_or_erase);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif 
-
-#endif /* __SPIFI_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/ssp_001.c b/bsp/xplorer4330/libraries/lpc_ip/ssp_001.c
deleted file mode 100644
index c7e98c5d42..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/ssp_001.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * @brief SSP Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "ssp_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/*Set up output clocks per bit for SSP bus*/
-void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale)
-{
-	pSSP->CR0 &= ~(SSP_CR0_SCR(0xFF));
-	pSSP->CR0 |= SSP_CR0_SCR(clk_rate);
-	pSSP->CPSR = prescale;
-}
-
-/* Set up the SSP frame format */
-void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat)
-{
-	pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockFormat;
-}
-
-/* Set the SSP working as master or slave mode */
-void IP_SSP_Set_Mode(IP_SSP_001_Type *pSSP, uint32_t mode)
-{
-	pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
-}
-
-/* Disable SSP operation */
-void IP_SSP_DeInit(IP_SSP_001_Type *pSSP)
-{
-	pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
-}
-
-/* Enable/Disable SSP operation */
-void IP_SSP_Cmd(IP_SSP_001_Type *pSSP, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pSSP->CR1 |= SSP_CR1_SSP_EN;
-	}
-	else {
-		pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
-	}
-}
-
-/* Send SSP 16-bit data */
-void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data)
-{
-	pSSP->DR = SSP_DR_BITMASK(tx_data);
-}
-
-/* Get received SSP data */
-uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_Type *pSSP)
-{
-	return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
-}
-
-/* Enable/Disable loopback mode */
-void IP_SSP_LoopBackCmd(IP_SSP_001_Type *pSSP, FunctionalState NewState)
-{
-
-	if (NewState == ENABLE) {
-		pSSP->CR1 |= SSP_CR1_LBM_EN;
-	}
-	else {
-		pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
-	}
-}
-
-/* Get the raw interrupt status */
-IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_Type *pSSP, SSP_Raw_Int_Status_Type RawInt)
-{
-	return (pSSP->RIS & RawInt) ? SET : RESET;
-}
-
-/* Get the masked interrupt status */
-uint32_t IP_SSP_GetIntStatus(IP_SSP_001_Type *pSSP)
-{
-	return pSSP->MIS;
-}
-
-/* Clear the corresponding interrupt condition(s) in the SSP controller */
-void IP_SSP_ClearIntPending(IP_SSP_001_Type *pSSP, SSP_Int_Clear_Type IntClear)
-{
-	pSSP->ICR = IntClear;
-}
-
-/* Get the current status of SSP controller */
-FlagStatus IP_SSP_GetStatus(IP_SSP_001_Type *pSSP, SSP_Status_Type Stat)
-{
-	return (pSSP->SR & Stat) ? SET : RESET;
-}
-
-/* Get the number of bits transferred in each frame */
-uint8_t IP_SSP_GetDataSize(IP_SSP_001_Type *pSSP)
-{
-	return SSP_CR0_DSS(pSSP->CR0);
-}
-
-/* Enable/Disable interrupt for the SSP */
-void IP_SSP_Int_Enable(IP_SSP_001_Type *pSSP, SSP_Int_Mask_Type IntType, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-		pSSP->IMSC |= IntType;
-	}
-	else {
-		pSSP->IMSC &= (~IntType);
-	}
-}
-
-/* Enable/Disable DMA for SSP */
-void IP_SSP_DMA_Cmd(IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState)
-{
-#if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX)
-	if (NewState == ENABLE) {
-		pSSP->DMACR |= ssp_dma_t;
-	}
-	else {
-		pSSP->DMACR &= (~ssp_dma_t);
-	}
-#endif
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/ssp_001.h b/bsp/xplorer4330/libraries/lpc_ip/ssp_001.h
deleted file mode 100644
index 5be51d5461..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/ssp_001.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * @brief SSP Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SSP_001_H_
-#define __SSP_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SSP_001 IP: SSP register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief SSP register block structure
- */
-typedef struct {			/*!< SSPn Structure         */
-	__IO uint32_t CR0;		/*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
-	__IO uint32_t CR1;		/*!< Control Register 1. Selects master/slave and other modes. */
-	__IO uint32_t DR;		/*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-	__I  uint32_t SR;		/*!< Status Register        */
-	__IO uint32_t CPSR;		/*!< Clock Prescale Register */
-	__IO uint32_t IMSC;		/*!< Interrupt Mask Set and Clear Register */
-	__I  uint32_t RIS;		/*!< Raw Interrupt Status Register */
-	__I  uint32_t MIS;		/*!< Masked Interrupt Status Register */
-	__O  uint32_t ICR;		/*!< SSPICR Interrupt Clear Register */
-#if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX)	/* no DMA on LPC11xx or LPC11Uxx */
-	__IO uint32_t DMACR;	/*!< SSPn DMA control register */
-#endif
-} IP_SSP_001_Type;
-
-/**
- * Macro defines for CR0 register
- */
-
-/** SSP data size select, must be 4 bits to 16 bits */
-#define SSP_CR0_DSS(n)          ((uint32_t) ((n) & 0xF))
-/** SSP control 0 Motorola SPI mode */
-#define SSP_CR0_FRF_SPI         ((uint32_t) (0 << 4))
-/** SSP control 0 TI synchronous serial mode */
-#define SSP_CR0_FRF_TI          ((uint32_t) (1 << 4))
-/** SSP control 0 National Micro-wire mode */
-#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
-/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
-   bus clock high between frames, (0) = low */
-#define SSP_CR0_CPOL_LO     ((uint32_t) (0))
-#define SSP_CR0_CPOL_HI     ((uint32_t) (1 << 6))
-/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
-   on the second clock transition of the frame, (0) = first */
-#define SSP_CR0_CPHA_FIRST  ((uint32_t) (0))
-#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
-/** SSP serial clock rate value load macro, divider rate is
-   PERIPH_CLK / (cpsr * (SCR + 1)) */
-#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
-/** SSP CR0 bit mask */
-#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
-/** SSP CR0 bit mask */
-#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
-/** SSP serial clock rate value load macro, divider rate is
-   PERIPH_CLK / (cpsr * (SCR + 1)) */
-#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
-
-/**
- * Macro defines for CR1 register
- */
-
-/** SSP control 1 loopback mode enable bit */
-#define SSP_CR1_LBM_EN      ((uint32_t) (1 << 0))
-/** SSP control 1 enable bit */
-#define SSP_CR1_SSP_EN      ((uint32_t) (1 << 1))
-/** SSP control 1 slave enable */
-#define SSP_CR1_SLAVE_EN    ((uint32_t) (1 << 2))
-#define SSP_CR1_MASTER_EN   ((uint32_t) (0))
-/** SSP control 1 slave out disable bit, disables transmit line in slave
-   mode */
-#define SSP_CR1_SO_DISABLE  ((uint32_t) (1 << 3))
-/** SSP CR1 bit mask */
-#define SSP_CR1_BITMASK     ((uint32_t) (0x0F))
-
-/** SSP CPSR bit mask */
-#define SSP_CPSR_BITMASK    ((uint32_t) (0xFF))
-/**
- * Macro defines for DR register
- */
-
-/** SSP data bit mask */
-#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
-
-/**
- * Macro defines for SR register
- */
-
-/** SSP SR bit mask */
-#define SSP_SR_BITMASK  ((uint32_t) (0x1F))
-
-/** ICR bit mask */
-#define SSP_ICR_BITMASK ((uint32_t) (0x03))
-
-/**
- * @brief SSP Type of Status
- */
-typedef enum {
-	SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
-	SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
-	SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
-	SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
-	SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
-} SSP_Status_Type;
-
-/**
- * @brief SSP Type of Interrupt Mask
- */
-typedef enum {
-	SSP_RORIM = ((uint32_t)(1 << 0)),	/**< Overun */
-	SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
-	SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
-	SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
-	SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
-} SSP_Int_Mask_Type;
-
-/**
- * @brief SSP Type of Mask Interrupt Status
- */
-typedef enum {
-	SSP_RORMIS = ((uint32_t)(1 << 0)),	/**< Overun */
-	SSP_RTMIS = ((uint32_t)(1 << 1)),	/**< TimeOut */
-	SSP_RXMIS = ((uint32_t)(1 << 2)),	/**< Rx FIFO is at least half full */
-	SSP_TXMIS = ((uint32_t)(1 << 3)),	/**< Tx FIFO is at least half empty */
-	SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
-} SSP_Mask_Int_Status_Type;
-
-/**
- * @brief SSP Type of Raw Interrupt Status
- */
-typedef enum {
-	SSP_RORRIS = ((uint32_t)(1 << 0)),	/**< Overun */
-	SSP_RTRIS = ((uint32_t)(1 << 1)),	/**< TimeOut */
-	SSP_RXRIS = ((uint32_t)(1 << 2)),	/**< Rx FIFO is at least half full */
-	SSP_TXRIS = ((uint32_t)(1 << 3)),	/**< Tx FIFO is at least half empty */
-	SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
-} SSP_Raw_Int_Status_Type;
-
-typedef enum {
-	SSP_RORIC = 0x0,
-	SSP_RTIC = 0x1,
-	SSP_INT_CLEAR_BITMASK = 0x3,
-} SSP_Int_Clear_Type;
-
-typedef enum SSP_DMA_Type {
-	SSP_DMA_RX = (1u),	/**< DMA RX Enable */
-	SSP_DMA_TX = (1u << 1),	/**< DMA TX Enable */
-} SSP_DMA_Type;
-
-/**
- * @brief	Disable SSP operation
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @return	 Nothing
- * The SSP controller is disabled
- */
-void IP_SSP_DeInit(IP_SSP_001_Type *pSSP);
-
-/**
- * @brief	Enable/Disable SSP operation
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	 Nothing
- */
-void IP_SSP_Cmd(IP_SSP_001_Type *pSSP, FunctionalState NewState);
-
-/**
- * @brief	Enable/Disable loopback mode
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	 Nothing
- * Serial input is taken from the serial output (MOSI or MISO) rather
- * than the serial input pin
- */
-void IP_SSP_LoopBackCmd(IP_SSP_001_Type *pSSP, FunctionalState NewState);
-
-/**
- * @brief	Get the current status of SSP controller
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @param	Stat	: Type of status, should be :
- *						- SSP_STAT_TFE
- *						- SSP_STAT_TNF
- *						- SSP_STAT_RNE
- *						- SSP_STAT_RFF
- *						- SSP_STAT_BSY
- * @return	 SSP controller status, SET or RESET
- */
-FlagStatus IP_SSP_GetStatus(IP_SSP_001_Type *pSSP, SSP_Status_Type Stat);
-
-/**
- * @brief	Get the masked interrupt status
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @return	 SSP Masked Interrupt Status Register value
- * The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
- */
-uint32_t IP_SSP_GetIntStatus(IP_SSP_001_Type *pSSP);
-
-/**
- * @brief	Get the raw interrupt status
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @param	RawInt	: Interrupt condition to be get status, shoud be :
- *						- SSP_RORRIS
- *						- SSP_RTRIS
- *						- SSP_RXRIS
- *						- SSP_TXRIS
- * @return	 Raw interrupt status corresponding to interrupt condition , SET or RESET
- * Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
- */
-IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_Type *pSSP, SSP_Raw_Int_Status_Type RawInt);
-
-/**
- * @brief	Get the number of bits transferred in each frame
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @return	 the number of bits transferred in each frame minus one
- * The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
- */
-uint8_t IP_SSP_GetDataSize(IP_SSP_001_Type *pSSP);
-
-/**
- * @brief	Clear the corresponding interrupt condition(s) in the SSP controller
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @param	IntClear: Type of cleared interrupt, should be :
- *						- SSP_RORIC
- *						- SSP_RTIC
- * @return	 Nothing
- * Software can clear one or more interrupt condition(s) in the SSP controller
- */
-void IP_SSP_ClearIntPending(IP_SSP_001_Type *pSSP, SSP_Int_Clear_Type IntClear);
-
-/**
- * @brief	Enable/Disable interrupt for the SSP
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	IntType		: Type of interrupt condition to be enable/disable, should be :
- *							- SSP_RORIM
- *							- SSP_RTIM
- *							- SSP_RXIM
- *							- SSP_TXIM
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	 Nothing
- */
-void IP_SSP_Int_Enable(IP_SSP_001_Type *pSSP, SSP_Int_Mask_Type IntType, FunctionalState NewState);
-
-/**
- * @brief	Get received SSP data
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @return	 SSP 16-bit data received
- */
-uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_Type *pSSP);
-
-/**
- * @brief	Send SSP 16-bit data
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @param	tx_data	: SSP 16-bit data to be transmited
- * @return	 Nothing
- */
-void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data);
-
-/**
- * @brief	Set up output clocks per bit for SSP bus
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	clk_rate	fs: The number of prescaler-output clocks per bit on the bus, minus one
- * @param	prescale	: The factor by which the Prescaler divides the SSP peripheral clock PCLK
- * @return	 Nothing
- * The bit frequency is PCLK / (prescale x[clk_rate+1])
- */
-void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale);
-
-/**
- * @brief	Set up the SSP frame format
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	bits		: The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
- * @param	frameFormat	: Frame format, should be :
- *							- SSP_FRAMEFORMAT_SPI
- *							- SSP_FRAMEFORMAT_TI
- *							- SSP_FRAMEFORMAT_MICROWIRE
- * @param	clockFormat	: Select Clock polarity and Clock phase, should be :
- *							- SSP_CLOCK_CPHA0_CPOL0
- *							- SSP_CLOCK_CPHA0_CPOL1
- *							- SSP_CLOCK_CPHA1_CPOL0
- *							- SSP_CLOCK_CPHA1_CPOL1
- * @return	 Nothing
- * Note: The clockFormat is only used in SPI mode
- */
-void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat);
-
-/**
- * @brief	Set the SSP working as master or slave mode
- * @param	pSSP	: The base of SSP peripheral on the chip
- * @param	mode	: Operating mode, should be
- *						- SSP_MODE_MASTER
- *						- SSP_MODE_SLAVE
- * @return	 Nothing
- */
-void IP_SSP_Set_Mode(IP_SSP_001_Type *pSSP, uint32_t mode);
-
-/**
- * @brief	Enable/Disable DMA for SSP
- * @param	pSSP		: The base of SSP peripheral on the chip
- * @param	ssp_dma_t	: DMA set up for transmit/receive SSP, should be
- *							- SSP_DMA_RX
- *							- SSP_DMA_TX
- * @param	NewState	: New state, ENABLE or DISABLE
- * @return	 Nothing
- */
-void IP_SSP_DMA_Cmd(IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SSP_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/timer_001.c b/bsp/xplorer4330/libraries/lpc_ip/timer_001.c
deleted file mode 100644
index 19fb932b3d..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/timer_001.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * @brief	32-bit Timer/PWM control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "timer_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Resets the timer terminal and prescale counts to 0 */
-void IP_TIMER_Reset(IP_TIMER_001_Type *timer)
-{
-	uint32_t reg;
-
-	/* Disable timer, set terminal count to non-0 */
-	reg = timer->TCR;
-	timer->TCR = 0;
-	timer->TC = 1;
-
-	/* Reset timer counter */
-	timer->TCR = TIMER_RESET;
-
-	/* Wait for terminal count to clear */
-	while (timer->TC != 0) {}
-
-	/* Restore timer state */
-	timer->TCR = reg;
-}
-
-/* Sets external match control (MATn.matchnum) pin control */
-void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_Type *timer, int8_t initial_state,
-								 IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum)
-{
-	timer->EMR = (((uint32_t) initial_state) << matchnum) |
-				 (((uint32_t) matchState) << (4 + (matchnum * 2)));
-}
-
-/* Sets timer count source and edge with the selected passed from CapSrc */
-void IP_TIMER_SetTimerClockSrc(IP_TIMER_001_Type *timer,
-							   IP_TIMER_CAP_SRC_STATE_Type capSrc, int8_t capnum)
-{
-	timer->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/timer_001.h b/bsp/xplorer4330/libraries/lpc_ip/timer_001.h
deleted file mode 100644
index 51bd0c0ec6..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/timer_001.h
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * @brief 32-bit Timer/PWM registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __TIMER_001_H_
-#define __TIMER_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_TIMER_001 IP: Timer register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief 32-bit Standard timer register block structure
- */
-typedef struct {					/*!< TIMERn Structure       */
-	__IO uint32_t IR;				/*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-	__IO uint32_t TCR;				/*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-	__IO uint32_t TC;				/*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-	__IO uint32_t PR;				/*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-	__IO uint32_t PC;				/*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-	__IO uint32_t MCR;				/*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-	__IO uint32_t MR[4];			/*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-	__IO uint32_t CCR;				/*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-	__IO uint32_t CR[4];			/*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
-	__IO uint32_t EMR;				/*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
-	__I  uint32_t RESERVED0[12];
-	__IO uint32_t CTCR;				/*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-} IP_TIMER_001_Type;
-
-/** Macro to clear interrupt pending */
-#define TIMER_IR_CLR(n)         _BIT(n)
-
-/** Macro for getting a timer match interrupt bit */
-#define TIMER_MATCH_INT(n)      (_BIT((n) & 0x0F))
-/** Macro for getting a capture event interrupt bit */
-#define TIMER_CAP_INT(n)        (_BIT((((n) & 0x0F) + 4)))
-
-/** Timer/counter enable bit */
-#define TIMER_ENABLE            ((uint32_t) (1 << 0))
-/** Timer/counter reset bit */
-#define TIMER_RESET             ((uint32_t) (1 << 1))
-
-/** Bit location for interrupt on MRx match, n = 0 to 3 */
-#define TIMER_INT_ON_MATCH(n)   (_BIT(((n) * 3)))
-/** Bit location for reset on MRx match, n = 0 to 3 */
-#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
-/** Bit location for stop on MRx match, n = 0 to 3 */
-#define TIMER_STOP_ON_MATCH(n)  (_BIT((((n) * 3) + 2)))
-
-/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
-#define TIMER_CAP_RISING(n)     (_BIT(((n) * 3)))
-/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
-#define TIMER_CAP_FALLING(n)    (_BIT((((n) * 3) + 1)))
-/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
-#define TIMER_INT_ON_CAP(n)     (_BIT((((n) * 3) + 2)))
-
-/**
- * @brief	Determine if a match interrupt is pending
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match interrupt number to check
- * @return	false if the interrupt is not pending, otherwise true
- * Determine if the match interrupt for the passed timer and match
- * counter is pending.
- */
-STATIC INLINE bool IP_TIMER_MatchPending(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	return (bool) ((timer->IR & TIMER_MATCH_INT(matchnum)) != 0);
-}
-
-/**
- * @brief	Determine if a capture interrupt is pending
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture interrupt number to check
- * @return	false if the interrupt is not pending, otherwise true
- * Determine if the capture interrupt for the passed capture pin is
- * pending.
- */
-STATIC INLINE bool IP_TIMER_CapturePending(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	return (bool) ((timer->IR & TIMER_CAP_INT(capnum)) != 0);
-}
-
-/**
- * @brief	Clears a (pending) match interrupt
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match interrupt number to clear
- * @return	Nothing
- * Clears a pending timer match interrupt.
- */
-STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->IR = TIMER_IR_CLR(matchnum);
-}
-
-/**
- * @brief	Clears a (pending) capture interrupt
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture interrupt number to clear
- * @return	Nothing
- * Clears a pending timer capture interrupt.
- */
-STATIC INLINE void IP_TIMER_ClearCapture(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->IR = (0x10 << capnum);
-}
-
-/**
- * @brief	Enables the timer (starts count)
- * @param	timer	: Pointer to timer IP register address
- * @return	Nothing
- * Enables the timer to start counting.
- */
-STATIC INLINE void IP_TIMER_Enable(IP_TIMER_001_Type *timer)
-{
-	timer->TCR |= TIMER_ENABLE;
-}
-
-/**
- * @brief	Disables the timer (stops count)
- * @param	timer	: Pointer to timer IP register address
- * @return	Nothing
- * Disables the timer to stop counting.
- */
-STATIC INLINE void IP_TIMER_Disable(IP_TIMER_001_Type *timer)
-{
-	timer->TCR &= ~TIMER_ENABLE;
-}
-
-/**
- * @brief	Returns the current timer count
- * @param	timer	: Pointer to timer IP register address
- * @return	Current timer terminal count value
- * Returns the current timer terminal count.
- */
-STATIC INLINE uint32_t IP_TIMER_ReadCount(IP_TIMER_001_Type *timer)
-{
-	return timer->TC;
-}
-
-/**
- * @brief  Returns the current prescale count
- * @param	timer		: Pointer to timer IP register address
- * @return Current timer prescale count value
- * Returns the current prescale count.
- */
-STATIC INLINE uint32_t IP_TIMER_ReadPrescale(IP_TIMER_001_Type *timer)
-{
-	return timer->PC;
-}
-
-/**
- * @brief	Sets the prescaler value
- * @param	timer		: Pointer to timer IP register address
- * @param	prescale	: Prescale value to set the prescale register to
- * @return	Nothing
- * Sets the prescale count value.
- */
-STATIC INLINE void IP_TIMER_PrescaleSet(IP_TIMER_001_Type *timer, uint32_t prescale)
-{
-	timer->PR = prescale;
-}
-
-/**
- * @brief	Sets a timer match value
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer to set match count for
- * @param	matchval	: Match value for the selected match count
- * @return	Nothing
- * Sets ones of the timer match values.
- */
-STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_Type *timer, int8_t matchnum, uint32_t matchval)
-{
-	timer->MR[matchnum] = matchval;
-}
-
-/**
- * @brief	Reads a capture register
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture register to read
- * @return	The selected capture register value
- * Returns the selected capture register value.
- */
-STATIC INLINE uint32_t IP_TIMER_ReadCapture(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	return timer->CR[capnum];
-}
-
-/**
- * @brief	Resets the timer terminal and prescale counts to 0
- * @param	timer	: Pointer to timer IP register address
- * @return	Nothing
- */
-void IP_TIMER_Reset(IP_TIMER_001_Type *timer);
-
-/**
- * @brief	Enables a match interrupt that fires when the terminal count
- *			matches the match counter value.
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_MatchEnableInt(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->MCR |= TIMER_INT_ON_MATCH(matchnum);
-}
-
-/**
- * @brief	Disables a match interrupt for a match counter.
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_MatchDisableInt(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
-}
-
-/**
- * @brief	For the specific match counter, enables reset of the terminal count register when a match occurs
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_ResetOnMatchEnable(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->MCR |= TIMER_RESET_ON_MATCH(matchnum);
-}
-
-/**
- * @brief	For the specific match counter, disables reset of the terminal count register when a match occurs
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_ResetOnMatchDisable(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
-}
-
-/**
- * @brief	Enable a match timer to stop the terminal count when a
- *			match count equals the terminal count.
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_StopOnMatchEnable(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->MCR |= TIMER_STOP_ON_MATCH(matchnum);
-}
-
-/**
- * @brief	Disable stop on match for a match timer. Disables a match timer
- *			to stop the terminal count when a match count equals the terminal count.
- * @param	timer		: Pointer to timer IP register address
- * @param	matchnum	: Match timer, 0 to 3
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_StopOnMatchDisable(IP_TIMER_001_Type *timer, int8_t matchnum)
-{
-	timer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
-}
-
-/**
- * @brief	Enables capture on on rising edge of selected CAP signal for the
- *			selected capture register, enables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a rising edge.
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureRisingEdgeEnable(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->CCR |= TIMER_CAP_RISING(capnum);
-}
-
-/**
- * @brief	Disables capture on on rising edge of selected CAP signal. For the
- *			selected capture register, disables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a rising edge.
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureRisingEdgeDisable(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->CCR &= ~TIMER_CAP_RISING(capnum);
-}
-
-/**
- * @brief	Enables capture on on falling edge of selected CAP signal. For the
- *			selected capture register, enables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a falling edge.
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureFallingEdgeEnable(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->CCR |= TIMER_CAP_FALLING(capnum);
-}
-
-/**
- * @brief	Disables capture on on falling edge of selected CAP signal. For the
- *			selected capture register, disables the selected CAPn.capnum signal to load
- *			the capture register with the terminal coount on a falling edge.
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureFallingEdgeDisable(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->CCR &= ~TIMER_CAP_FALLING(capnum);
-}
-
-/**
- * @brief	Enables interrupt on capture of selected CAP signal. For the
- *			selected capture register, an interrupt will be generated when the enabled
- *			rising or falling edge on CAPn.capnum is detected.
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureEnableInt(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->CCR |= TIMER_INT_ON_CAP(capnum);
-}
-
-/**
- * @brief	Disables interrupt on capture of selected CAP signal
- * @param	timer	: Pointer to timer IP register address
- * @param	capnum	: Capture signal/register to use
- * @return	Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureDisableInt(IP_TIMER_001_Type *timer, int8_t capnum)
-{
-	timer->CCR &= ~TIMER_INT_ON_CAP(capnum);
-}
-
-/**
- * @brief Standard timer initial match pin state and change state
- */
-typedef enum {
-	TIMER_EXTMATCH_DO_NOTHING = 0,	/*!< Timer match state does nothing on match pin */
-	TIMER_EXTMATCH_CLEAR      = 1,	/*!< Timer match state sets match pin low */
-	TIMER_EXTMATCH_SET        = 2,	/*!< Timer match state sets match pin high */
-	TIMER_EXTMATCH_TOGGLE     = 3	/*!< Timer match state toggles match pin */
-} IP_TIMER_PIN_MATCH_STATE_Type;
-
-/**
- * @brief	Sets external match control (MATn.matchnum) pin control
- * @param	timer			: Pointer to timer IP register address
- * @param	initial_state	: Initial state of the pin, high(1) or low(0)
- * @param	matchState		: Selects the match state for the pin
- * @param	matchnum		: MATn.matchnum signal to use
- * @return	Nothing
- * For the pin selected with matchnum, sets the function of the pin that occurs on
- * a terminal count match for the match count.
- */
-void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_Type *timer, int8_t initial_state,
-								 IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum);
-
-/**
- * @brief Standard timer clock and edge for count source
- */
-typedef enum {
-	TIMER_CAPSRC_RISING_PCLK  = 0,	/*!< Timer ticks on PCLK rising edge */
-	TIMER_CAPSRC_RISING_CAPN  = 1,	/*!< Timer ticks on CAPn.x rising edge */
-	TIMER_CAPSRC_FALLING_CAPN = 2,	/*!< Timer ticks on CAPn.x falling edge */
-	TIMER_CAPSRC_BOTH_CAPN    = 3	/*!< Timer ticks on CAPn.x both edges */
-} IP_TIMER_CAP_SRC_STATE_Type;
-
-/**
- * @brief	Sets timer count source and edge with the selected passed from CapSrc
- * @param	timer	: Pointer to timer IP register address
- * @param	capSrc	: timer clock source and edge
- * @param	capnum	: CAPn.capnum pin to use (if used)
- * @return	Nothing
- * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
- */
-void IP_TIMER_SetCountClockSrc(IP_TIMER_001_Type *timer,
-							   IP_TIMER_CAP_SRC_STATE_Type capSrc, int8_t capnum);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TIMER_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/usart_001.c b/bsp/xplorer4330/libraries/lpc_ip/usart_001.c
deleted file mode 100644
index 6f533cb467..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/usart_001.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * @brief	usart registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "usart_001.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the UARTx peripheral according to the specified parameters in
-   the UART_ConfigStruct */
-void IP_UART_Init(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort)
-{
-	volatile uint32_t tmp;
-	/* FIFOs are empty */
-	LPC_UART->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
-	/* Disable FIFO */
-	// LPC_UART->FCR = 0;
-	/* Dummy reading */
-	while (LPC_UART->LSR & UART_LSR_RDR) {
-		tmp = LPC_UART->RBR;
-	}
-#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-	switch (UARTPort) {
-#if defined(CHIP_LPC177X_8X)
-	case 4:
-#else
-	case 0:
-	case 2:
-	case 3:
-#endif
-		LPC_UART->TER2 = UART_TER2_TXEN;
-		/* Wait for current transmit complete */
-		while (!(LPC_UART->LSR & UART_LSR_THRE)) {}
-		/* Disable Tx */
-		LPC_UART->TER2 = 0;
-		break;
-
-	default:
-		break;
-	}
-#else
-	LPC_UART->TER1 = UART_TER1_TXEN;
-	/* Wait for current transmit complete */
-	while (!(LPC_UART->LSR & UART_LSR_THRE)) {}
-	/* Disable Tx */
-	LPC_UART->TER1 = 0;
-#endif
-	/* Disable interrupt */
-	LPC_UART->IER = 0;
-	/* Set LCR to default state */
-	LPC_UART->LCR = 0;
-	/* Set ACR to default state */
-	LPC_UART->ACR = 0;
-#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X)
-	if ((UARTPort == 1) || (UARTPort == 4)) {
-		/* Set RS485 control to default state */
-		LPC_UART->RS485CTRL = 0;
-		/* Set RS485 delay timer to default state */
-		LPC_UART->RS485DLY = 0;
-		/* Set RS485 addr match to default state */
-		LPC_UART->RS485ADRMATCH = 0;
-	}
-#else
-	/* Set RS485 control to default state */
-	LPC_UART->RS485CTRL = 0;
-	/* Set RS485 delay timer to default state */
-	LPC_UART->RS485DLY = 0;
-	/* Set RS485 addr match to default state */
-	LPC_UART->RS485ADRMATCH = 0;
-#endif
-
-#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-	if (UARTPort == 1) {
-#endif
-	/* Set Modem Control to default state */
-	LPC_UART->MCR = 0;
-	/*Dummy Reading to Clear Status */
-	tmp = LPC_UART->MSR;
-#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-}
-
-#endif
-
-	/* Dummy reading */
-	tmp = LPC_UART->LSR;
-	/* Set Line Control register ---------------------------- */
-	//	LPC_UART->LCR = UART_DATABIT_8  |                 /* Default: 8N1 */
-	//					UART_STOPBIT_1  |
-	//					UART_PARITY_NONE;
-	LPC_UART->FDR = 0x10;								/* No fractional divider */
-}
-
-/* De-initializes the UARTx peripheral registers to their default reset values */
-void IP_UART_DeInit(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort)
-{
-	/* For debug mode */
-
-	IP_UART_TxCmd(LPC_UART, UARTPort, DISABLE);
-
-	switch (UARTPort) {
-	default:
-		break;
-	}
-}
-
-/* Determines best dividers to get a target clock rate */
-Status IP_UART_SetBaud(IP_USART_001_Type *LPC_UART, uint32_t baudrate, uint32_t uClk)
-{
-	Status errorStatus = ERROR;
-
-	uint32_t d, m, bestd, bestm, tmp;
-	uint64_t best_divisor, divisor;
-	uint32_t current_error, best_error;
-	uint32_t recalcbaud;
-
-	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
-	 * The formula is :
-	 * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
-	 * It involves floating point calculations. That's the reason the formulae are adjusted with
-	 * Multiply and divide method.*/
-	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
-	 * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
-	best_error = 0xFFFFFFFF;/* Worst case */
-	bestd = 0;
-	bestm = 0;
-	best_divisor = 0;
-	for (m = 1; m <= 15; m++) {
-		for (d = 0; d < m; d++) {
-			divisor = ((uint64_t) uClk << 28) * m / (baudrate * (m + d));
-			current_error = divisor & 0xFFFFFFFF;
-
-			tmp = divisor >> 32;
-
-			/* Adjust error */
-			if (current_error > ((uint32_t) 1 << 31)) {
-				current_error = -current_error;
-				tmp++;
-			}
-
-			if (( tmp < 1) || ( tmp > 65536) ) {/* Out of range */
-				continue;
-			}
-
-			if ( current_error < best_error) {
-				best_error = current_error;
-				best_divisor = tmp;
-				bestd = d;
-				bestm = m;
-				if (best_error == 0) {
-					break;
-				}
-			}
-		}	/* end of inner for loop */
-
-		if (best_error == 0) {
-			break;
-		}
-	}	/* end of outer for loop  */
-
-	if (best_divisor == 0) {
-		return ERROR;					/* can not find best match */
-
-	}
-	recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
-
-	/* reuse best_error to evaluate baud error */
-	if (baudrate > recalcbaud) {
-		best_error = baudrate - recalcbaud;
-	}
-	else {best_error = recalcbaud - baudrate; }
-
-	best_error = best_error * 100 / baudrate;
-
-	if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) {
-		LPC_UART->LCR |= UART_LCR_DLAB_EN;
-		LPC_UART->DLM = UART_LOAD_DLM(best_divisor);
-		LPC_UART->DLL = UART_LOAD_DLL(best_divisor);
-		/* Then reset DLAB bit */
-		LPC_UART->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
-		LPC_UART->FDR = (UART_FDR_MULVAL(bestm)	\
-						 | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
-		errorStatus = SUCCESS;
-	}
-
-	return errorStatus;
-}
-
-/* Configure data width, parity mode and stop bits */
-void IP_UART_ConfigData(IP_USART_001_Type *LPC_UART,
-						UART_DATABIT_Type Databits,
-						UART_PARITY_Type Parity,
-						UART_STOPBIT_Type Stopbits)
-{
-	uint32_t tmp = (LPC_UART->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
-	tmp |= (uint32_t) Databits | (uint32_t) Parity | (uint32_t) Stopbits;
-	LPC_UART->LCR = (uint8_t) (tmp & UART_LCR_BITMASK);
-}
-
-/* UART Send/Recieve functions -------------------------------------------------*/
-/* Transmit a single data through UART peripheral */
-Status IP_UART_SendByte(IP_USART_001_Type *LPC_UART, uint8_t Data)
-{
-	if (!(LPC_UART->LSR & UART_LSR_THRE)) {
-		return ERROR;
-	}
-	LPC_UART->THR = Data & UART_THR_MASKBIT;
-	return SUCCESS;
-}
-
-/* Receive a single data from UART peripheral */
-Status IP_UART_ReceiveByte(IP_USART_001_Type *LPC_UART, uint8_t *Data)
-{
-	if (!(LPC_UART->LSR & UART_LSR_RDR)) {
-		return ERROR;
-	}
-	*Data = (uint8_t) (LPC_UART->RBR & UART_RBR_MASKBIT);
-	return SUCCESS;
-}
-
-/* Send a block of data via UART peripheral */
-uint32_t IP_UART_Send(IP_USART_001_Type *LPC_UART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
-{
-	uint32_t bToSend, bSent, timeOut;	// , fifo_cnt;
-	uint8_t *pChar = txbuf;
-
-	bToSend = buflen;
-
-	/* blocking mode */
-	if (flag == BLOCKING) {
-		bSent = 0;
-		while (bToSend) {
-			timeOut = UART_BLOCKING_TIMEOUT;
-			/* Wait for THR empty with timeout */
-			while (!(IP_UART_SendByte(LPC_UART, *pChar))) {
-				if (timeOut == 0) {
-					break;
-				}
-				timeOut--;
-			}
-			/* Time out! */
-			if (timeOut == 0) {
-				break;
-			}
-			pChar++;
-			bToSend--;
-			bSent++;
-		}
-	}
-	/* None blocking mode */
-	else {
-		bSent = 0;
-		while (bToSend) {
-			if (!(IP_UART_SendByte(LPC_UART, *pChar))) {
-				break;
-			}
-			pChar++;
-			bToSend--;
-			bSent++;
-		}
-	}
-	return bSent;
-}
-
-/* Receive a block of data via UART peripheral */
-uint32_t IP_UART_Receive(IP_USART_001_Type *LPC_UART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
-{
-	uint32_t bToRecv, bRecv, timeOut;
-	uint8_t *pChar = rxbuf;
-
-	bToRecv = buflen;
-
-	/* Blocking mode */
-	if (flag == BLOCKING) {
-		bRecv = 0;
-		while (bToRecv) {
-			timeOut = UART_BLOCKING_TIMEOUT;
-			while (!(IP_UART_ReceiveByte(LPC_UART, pChar))) {
-				if (timeOut == 0) {
-					break;
-				}
-				timeOut--;
-			}
-			/* Time out! */
-			if (timeOut == 0) {
-				break;
-			}
-			pChar++;
-			bToRecv--;
-			bRecv++;
-		}
-	}
-	/* None blocking mode */
-	else {
-		bRecv = 0;
-		while (bToRecv) {
-			if (!(IP_UART_ReceiveByte(LPC_UART, pChar))) {
-				break;
-			}
-			else {
-				pChar++;
-				bRecv++;
-				bToRecv--;
-			}
-		}
-	}
-	return bRecv;
-}
-
-/* Enable or disable specified UART interrupt */
-void IP_UART_IntConfig(IP_USART_001_Type *LPC_UART, UART_INT_Type UARTIntCfg, FunctionalState NewState)
-{
-	uint32_t tmp = 0;
-
-	switch (UARTIntCfg) {
-	case UART_INTCFG_RBR:
-		tmp = UART_IER_RBRINT_EN;
-		break;
-
-	case UART_INTCFG_THRE:
-		tmp = UART_IER_THREINT_EN;
-		break;
-
-	case UART_INTCFG_RLS:
-		tmp = UART_IER_RLSINT_EN;
-		break;
-
-	case UART_INTCFG_MS:
-		tmp = UART_IER_MSINT_EN;
-		break;
-
-	case UART_INTCFG_CTS:
-		tmp = UART_IER_CTSINT_EN;
-		break;
-
-	case UART_INTCFG_ABEO:
-		tmp = UART_IER_ABEOINT_EN;
-		break;
-
-	case UART_INTCFG_ABTO:
-		tmp = UART_IER_ABTOINT_EN;
-		break;
-	}
-
-	if (NewState == ENABLE) {
-		LPC_UART->IER |= tmp;
-	}
-	else {
-
-		LPC_UART->IER &= (~tmp) & UART_IER_BITMASK;
-
-	}
-}
-
-/* Get Source Interrupt */
-uint32_t IP_UART_IntGetStatus(IP_USART_001_Type *LPC_UART)
-{
-	return (LPC_UART->IIR) & UART_IIR_BITMASK;
-}
-
-/* Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0 */
-void IP_UART_ForceBreak(IP_USART_001_Type *LPC_UART)
-{
-	LPC_UART->LCR |= UART_LCR_BREAK_EN;
-}
-
-/* Get current value of Line Status register in UART peripheral */
-uint8_t IP_UART_GetLineStatus(IP_USART_001_Type *LPC_UART)
-{
-	return (LPC_UART->LSR) & UART_LSR_BITMASK;
-}
-
-/* Check whether if UART is busy or not */
-FlagStatus IP_UART_CheckBusy(IP_USART_001_Type *LPC_UART)
-{
-	if (LPC_UART->LSR & UART_LSR_TEMT) {
-		return RESET;
-	}
-	else {
-		return SET;
-	}
-}
-
-/* Enable/Disable transmission on UART TxD pin */
-void IP_UART_TxCmd(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort, FunctionalState NewState)
-{
-	if (NewState == ENABLE) {
-#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-		switch (UARTPort) {
-#if defined(CHIP_LPC177X_8X)
-		case 4:
-#else
-		case 0:
-		case 2:
-		case 3:
-#endif
-			LPC_UART->TER2 = UART_TER2_TXEN;
-			break;
-
-		default:
-			break;
-		}
-#else
-		LPC_UART->TER1 = UART_TER1_TXEN;
-#endif
-	}
-	else {
-#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-		switch (UARTPort) {
-#if defined(CHIP_LPC177X_8X)
-		case 4:
-#else
-		case 0:
-		case 2:
-		case 3:
-#endif
-			LPC_UART->TER2 &= (~UART_TER2_TXEN) & UART_TER2_BITMASK;
-			break;
-
-		default:
-			break;
-		}
-#else
-		LPC_UART->TER1 &= (~UART_TER1_TXEN) & UART_TER1_BITMASK;
-#endif
-	}
-}
-
-/* UART FIFO functions ----------------------------------------------------------*/
-/* Configure FIFO function on selected UART peripheral */
-void IP_UART_FIFOConfig(IP_USART_001_Type *LPC_UART, UART_FIFO_CFG_Type *FIFOCfg)
-{
-	uint8_t tmp = 0;
-
-	tmp |= UART_FCR_FIFO_EN;
-	switch (FIFOCfg->FIFO_Level) {
-	case UART_FIFO_TRGLEV0:
-		tmp |= UART_FCR_TRG_LEV0;
-		break;
-
-	case UART_FIFO_TRGLEV1:
-		tmp |= UART_FCR_TRG_LEV1;
-		break;
-
-	case UART_FIFO_TRGLEV2:
-		tmp |= UART_FCR_TRG_LEV2;
-		break;
-
-	case UART_FIFO_TRGLEV3:
-	default:
-		tmp |= UART_FCR_TRG_LEV3;
-		break;
-	}
-
-	if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) {
-		tmp |= UART_FCR_TX_RS;
-	}
-	if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) {
-		tmp |= UART_FCR_RX_RS;
-	}
-	if (FIFOCfg->FIFO_DMAMode == ENABLE) {
-		tmp |= UART_FCR_DMAMODE_SEL;
-	}
-
-	/* write to FIFO control register */
-	LPC_UART->FCR = tmp & UART_FCR_BITMASK;
-}
-
-/* Fills each UART_FIFOInitStruct member with its default value */
-void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
-{
-	UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
-	UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
-	UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
-	UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_ip/usart_001.h b/bsp/xplorer4330/libraries/lpc_ip/usart_001.h
deleted file mode 100644
index 5beae2cdb8..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/usart_001.h
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * @brief Usart Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __USART_001_H_
-#define __USART_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_USART_001 IP: USART register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief USART register block structure
- */
-typedef struct {							/*!< USARTn Structure       */
-
-	union {
-		__IO uint32_t  DLL;					/*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
-		__O  uint32_t  THR;					/*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
-		__I  uint32_t  RBR;					/*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
-	};
-
-	union {
-		__IO uint32_t IER;					/*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
-		__IO uint32_t DLM;					/*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
-	};
-
-	union {
-		__O  uint32_t FCR;					/*!< FIFO Control Register. Controls UART FIFO usage and modes. */
-		__I  uint32_t IIR;					/*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
-	};
-
-	__IO uint32_t LCR;						/*!< Line Control Register. Contains controls for frame formatting and break generation. */
-	__IO uint32_t MCR;						/*!< Modem Control Register. Only present on USART ports with full modem support. */
-	__I  uint32_t LSR;						/*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
-	__I  uint32_t MSR;						/*!< Modem Status Register. Only present on USART ports with full modem support. */
-	__IO uint32_t SCR;						/*!< Scratch Pad Register. Eight-bit temporary storage for software. */
-	__IO uint32_t ACR;						/*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
-	__IO uint32_t ICR;						/*!< IrDA control register (not all UARTS) */
-	__IO uint32_t FDR;						/*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
-	__IO uint32_t OSR;						/*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
-	__IO uint32_t TER1;						/*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
-	uint32_t  RESERVED0[3];
-	__IO uint32_t HDEN;						/*!< Half-duplex enable Register- only on some UARTs */
-	__I  uint32_t RESERVED1[1];
-	__IO uint32_t SCICTRL;					/*!< Smart card interface control register- only on some UARTs */
-	__IO uint32_t RS485CTRL;				/*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-	__IO uint32_t RS485ADRMATCH;			/*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-	__IO uint32_t RS485DLY;					/*!< RS-485/EIA-485 direction control delay. */
-	union {
-		__IO uint32_t SYNCCTRL;				/*!< Synchronous mode control register. Only on USARTs. */
-		__I  uint32_t FIFOLVL;				/*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
-	};
-
-	__IO uint32_t TER2;						/*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
-} IP_USART_001_Type;
-
-#define UART_BLOCKING_TIMEOUT           (0xFFFFFFFFUL)	/*!< UART time-out definitions in case of using Read/Write function with Blocking Flag mode */
-
-#define UART_ACCEPTED_BAUDRATE_ERROR    (3)				/*!< Acceptable UART baudrate error */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/**
- * @brief Macro defines for UARTn Receiver Buffer Register
- */
-#define UART_RBR_MASKBIT    ((uint8_t) 0xFF)		/*!< UART Received Buffer mask bit (8 bits) */
-
-/**
- * @brief Macro defines for UARTn Transmit Holding Register
- */
-#define UART_THR_MASKBIT    ((uint8_t) 0xFF)		/*!< UART Transmit Holding mask bit (8 bits) */
-
-/**
- * @brief Macro defines for UARTn Divisor Latch LSB register
- */
-#define UART_LOAD_DLL(div)  ((div) & 0xFF)			/*!< Macro for loading least significant halfs of divisors */
-#define UART_DLL_MASKBIT    ((uint8_t) 0xFF)		/*!< Divisor latch LSB bit mask */
-
-/**
- * @brief Macro defines for UARTn Divisor Latch MSB register
- */
-#define UART_DLM_MASKBIT    ((uint8_t) 0xFF)		/*!< Divisor latch MSB bit mask */
-#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)	/*!< Macro for loading most significant halfs of divisors */
-
-/**
- * @brief Macro defines for UART interrupt enable register
- */
-#define UART_IER_RBRINT_EN      ((uint32_t) (1 << 0))	/*!< RBR Interrupt enable*/
-#define UART_IER_THREINT_EN     ((uint32_t) (1 << 1))	/*!< THR Interrupt enable*/
-#define UART_IER_RLSINT_EN      ((uint32_t) (1 << 2))	/*!< RX line status interrupt enable*/
-#define UART_IER_MSINT_EN       ((uint32_t) (1 << 3))	/*!< Modem status interrupt enable */
-#define UART_IER_CTSINT_EN      ((uint32_t) (1 << 7))	/*!< CTS1 signal transition interrupt enable */
-#define UART_IER_ABEOINT_EN     ((uint32_t) (1 << 8))	/*!< Enables the end of auto-baud interrupt */
-#define UART_IER_ABTOINT_EN     ((uint32_t) (1 << 9))	/*!< Enables the auto-baud time-out interrupt */
-#define UART_IER_BITMASK        ((uint32_t) (0x307))	/*!< UART interrupt enable register bit mask */
-#define UART1_IER_BITMASK       ((uint32_t) (0x38F))	/*!< UART1 interrupt enable register bit mask */
-
-/**
- * @brief Macro defines for UART interrupt identification register
- */
-#define UART_IIR_INTSTAT_PEND   ((uint32_t) (1 << 0))	/*!<Interrupt Status - Active low */
-#define UART_IIR_INTID_RLS      ((uint32_t) (3 << 1))	/*!<Interrupt identification: Receive line status*/
-#define UART_IIR_INTID_RDA      ((uint32_t) (2 << 1))	/*!<Interrupt identification: Receive data available*/
-#define UART_IIR_INTID_CTI      ((uint32_t) (6 << 1))	/*!<Interrupt identification: Character time-out indicator*/
-#define UART_IIR_INTID_THRE     ((uint32_t) (1 << 1))	/*!<Interrupt identification: THRE interrupt*/
-#define UART_IIR_INTID_MODEM    ((uint32_t) (0 << 1))	/*!<Interrupt identification: Modem interrupt*/
-#define UART_IIR_INTID_MASK     ((uint32_t) (7 << 1))	/*!<Interrupt identification: Interrupt ID mask */
-#define UART_IIR_FIFO_EN        ((uint32_t) (3 << 6))	/*!<These bits are equivalent to UnFCR[0] */
-#define UART_IIR_ABEO_INT       ((uint32_t) (1 << 8))	/*!< End of auto-baud interrupt */
-#define UART_IIR_ABTO_INT       ((uint32_t) (1 << 9))	/*!< Auto-baud time-out interrupt */
-#define UART_IIR_BITMASK        ((uint32_t) (0x3CF))	/*!< UART interrupt identification register bit mask */
-
-/**
- * @brief Macro defines for UART FIFO control register
- */
-#define UART_FCR_FIFO_EN        ((uint8_t) (1 << 0))	/*!< UART FIFO enable */
-#define UART_FCR_RX_RS          ((uint8_t) (1 << 1))	/*!< UART FIFO RX reset */
-#define UART_FCR_TX_RS          ((uint8_t) (1 << 2))	/*!< UART FIFO TX reset */
-#define UART_FCR_DMAMODE_SEL    ((uint8_t) (1 << 3))	/*!< UART DMA mode selection */
-#define UART_FCR_TRG_LEV0       ((uint8_t) (0))			/*!< UART FIFO trigger level 0: 1 character */
-#define UART_FCR_TRG_LEV1       ((uint8_t) (1 << 6))	/*!< UART FIFO trigger level 1: 4 character */
-#define UART_FCR_TRG_LEV2       ((uint8_t) (2 << 6))	/*!< UART FIFO trigger level 2: 8 character */
-#define UART_FCR_TRG_LEV3       ((uint8_t) (3 << 6))	/*!< UART FIFO trigger level 3: 14 character */
-#define UART_FCR_BITMASK        ((uint8_t) (0xCF))		/*!< UART FIFO control bit mask */
-#define UART_TX_FIFO_SIZE       (16)
-
-/**
- * @brief Macro defines for UART line control register
- */
-#define UART_LCR_WLEN5          ((uint8_t) (0))				/*!< UART 5 bit data mode */
-#define UART_LCR_WLEN6          ((uint8_t) (1 << 0))		/*!< UART 6 bit data mode */
-#define UART_LCR_WLEN7          ((uint8_t) (2 << 0))		/*!< UART 7 bit data mode */
-#define UART_LCR_WLEN8          ((uint8_t) (3 << 0))		/*!< UART 8 bit data mode */
-#define UART_LCR_SBS_1BIT       ((uint8_t) (0 << 2))		/*!< UART One Stop Bit Select */
-#define UART_LCR_SBS_2BIT       ((uint8_t) (1 << 2))		/*!< UART Two Stop Bits Select */
-#define UART_LCR_PARITY_EN      ((uint8_t) (1 << 3))		/*!< UART Parity Enable */
-#define UART_LCR_PARITY_DIS     ((uint8_t) (0 << 3))		/*!< UART Parity Disable */
-#define UART_LCR_PARITY_ODD     ((uint8_t) (0))				/*!< UART Odd Parity Select */
-#define UART_LCR_PARITY_EVEN    ((uint8_t) (1 << 4))		/*!< UART Even Parity Select */
-#define UART_LCR_PARITY_F_1     ((uint8_t) (2 << 4))		/*!< UART force 1 stick parity */
-#define UART_LCR_PARITY_F_0     ((uint8_t) (3 << 4))		/*!< UART force 0 stick parity */
-#define UART_LCR_BREAK_EN       ((uint8_t) (1 << 6))		/*!< UART Transmission Break enable */
-#define UART_LCR_DLAB_EN        ((uint8_t) (1 << 7))		/*!< UART Divisor Latches Access bit enable */
-#define UART_LCR_BITMASK        ((uint8_t) (0xFF))			/*!< UART line control bit mask */
-
-/**
- * @brief Macro defines for UART Modem control register
- */
-#define UART_MCR_DTR_CTRL       ((uint8_t) (1 << 0))		/*!< Source for modem output pin DTR */
-#define UART_MCR_RTS_CTRL       ((uint8_t) (1 << 1))		/*!< Source for modem output pin RTS */
-#define UART_MCR_LOOPB_EN       ((uint8_t) (1 << 4))		/*!< Loop back mode select */
-#define UART_MCR_AUTO_RTS_EN    ((uint8_t) (1 << 6))		/*!< Enable Auto RTS flow-control */
-#define UART_MCR_AUTO_CTS_EN    ((uint8_t) (1 << 7))		/*!< Enable Auto CTS flow-control */
-#define UART_MCR_BITMASK        ((uint8_t) (0x0F3))			/*!< UART1 bit mask value */
-
-/**
- * @brief Macro defines for UART line status register
- */
-#define UART_LSR_RDR        ((uint8_t) (1 << 0))	/*!<Line status register: Receive data ready*/
-#define UART_LSR_OE         ((uint8_t) (1 << 1))	/*!<Line status register: Overrun error*/
-#define UART_LSR_PE         ((uint8_t) (1 << 2))	/*!<Line status register: Parity error*/
-#define UART_LSR_FE         ((uint8_t) (1 << 3))	/*!<Line status register: Framing error*/
-#define UART_LSR_BI         ((uint8_t) (1 << 4))	/*!<Line status register: Break interrupt*/
-#define UART_LSR_THRE       ((uint8_t) (1 << 5))	/*!<Line status register: Transmit holding register empty*/
-#define UART_LSR_TEMT       ((uint8_t) (1 << 6))	/*!<Line status register: Transmitter empty*/
-#define UART_LSR_RXFE       ((uint8_t) (1 << 7))	/*!<Error in RX FIFO*/
-#define UART_LSR_BITMASK    ((uint8_t) (0xFF))		/*!<UART Line status bit mask */
-
-/**
- * @brief Macro defines for UART Modem status register
- */
-#define UART_MSR_DELTA_CTS      ((uint8_t) (1 << 0))	/*!< Set upon state change of input CTS */
-#define UART_MSR_DELTA_DSR      ((uint8_t) (1 << 1))	/*!< Set upon state change of input DSR */
-#define UART_MSR_LO2HI_RI       ((uint8_t) (1 << 2))	/*!< Set upon low to high transition of input RI */
-#define UART_MSR_DELTA_DCD      ((uint8_t) (1 << 3))	/*!< Set upon state change of input DCD */
-#define UART_MSR_CTS            ((uint8_t) (1 << 4))	/*!< Clear To Send State */
-#define UART_MSR_DSR            ((uint8_t) (1 << 5))	/*!< Data Set Ready State */
-#define UART_MSR_RI             ((uint8_t) (1 << 6))	/*!< Ring Indicator State */
-#define UART_MSR_DCD            ((uint8_t) (1 << 7))	/*!< Data Carrier Detect State */
-#define UART_MSR_BITMASK        ((uint8_t) (0xFF))		/*!< MSR register bit-mask value */
-
-/**
- * @brief Macro defines for UART Scratch Pad register
- */
-#define UART_SCR_BIMASK     ((uint8_t) (0xFF))			/*!< UART Scratch Pad bit mask */
-
-/**
- * @brief Macro defines for UART Auto baudrate control register
- */
-#define UART_ACR_START              ((uint32_t) (1 << 0))	/*!< UART Auto-baud start */
-#define UART_ACR_MODE               ((uint32_t) (1 << 1))	/*!< UART Auto baudrate Mode 1 */
-#define UART_ACR_AUTO_RESTART       ((uint32_t) (1 << 2))	/*!< UART Auto baudrate restart */
-#define UART_ACR_ABEOINT_CLR        ((uint32_t) (1 << 8))	/*!< UART End of auto-baud interrupt clear */
-#define UART_ACR_ABTOINT_CLR        ((uint32_t) (1 << 9))	/*!< UART Auto-baud time-out interrupt clear */
-#define UART_ACR_BITMASK            ((uint32_t) (0x307))	/*!< UART Auto Baudrate register bit mask */
-
-/**
- * @brief Macro defines for UART IrDA control register
- */
-#define UART_ICR_IRDAEN         ((uint32_t) (1 << 0))			/*!< IrDA mode enable */
-#define UART_ICR_IRDAINV        ((uint32_t) (1 << 1))			/*!< IrDA serial input inverted */
-#define UART_ICR_FIXPULSE_EN    ((uint32_t) (1 << 2))			/*!< IrDA fixed pulse width mode */
-#define UART_ICR_PULSEDIV(n)    ((uint32_t) ((n & 0x07) << 3))	/*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
-#define UART_ICR_BITMASK        ((uint32_t) (0x3F))				/*!< UART IRDA bit mask */
-
-/**
- * @brief Macro defines for UART half duplex register
- */
-#define UART_HDEN_HDEN          ((uint32_t) (1 << 0))			/*!< enable half-duplex mode*/
-
-/**
- * @brief Macro defines for UART smart card interface control register
- */
-#define UART_SCICTRL_SCIEN      ((uint32_t) (1 << 0))				/*!< enable asynchronous half-duplex smart card interface*/
-#define UART_SCICTRL_NACKDIS    ((uint32_t) (1 << 1))				/*!< NACK response is inhibited*/
-#define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2))				/*!< ISO7816-3 protocol T1 is selected*/
-#define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5))		/*!< number of retransmission*/
-#define UART_SCICTRL_GUARDTIME(n)   ((uint32_t) ((n & 0xFF) << 8))	/*!< Extra guard time*/
-
-/**
- * @brief Macro defines for UART synchronous control register
- */
-#define UART_SYNCCTRL_SYNC      ((uint32_t) (1 << 0))			/*!< enable synchronous mode*/
-#define UART_SYNCCTRL_CSRC_MASTER   ((uint32_t) (1 << 1))		/*!< synchronous master mode*/
-#define UART_SYNCCTRL_FES       ((uint32_t) (1 << 2))			/*!< sample on falling edge*/
-#define UART_SYNCCTRL_TSBYPASS  ((uint32_t) (1 << 3))			/*!< to be defined*/
-#define UART_SYNCCTRL_CSCEN     ((uint32_t) (1 << 4))			/*!< continuous running clock enable (master mode only)*/
-#define UART_SYNCCTRL_STARTSTOPDISABLE  ((uint32_t) (1 << 5))	/*!< do not send start/stop bit*/
-#define UART_SYNCCTRL_CCCLR     ((uint32_t) (1 << 6))			/*!< stop continuous clock*/
-
-/**
- * @brief Macro defines for UART Fractional divider register
- */
-#define UART_FDR_DIVADDVAL(n)   ((uint32_t) (n & 0x0F))			/*!< Baud-rate generation pre-scaler divisor */
-#define UART_FDR_MULVAL(n)      ((uint32_t) ((n << 4) & 0xF0))	/*!< Baud-rate pre-scaler multiplier value */
-#define UART_FDR_BITMASK        ((uint32_t) (0xFF))				/*!< UART Fractional Divider register bit mask */
-
-/**
- * @brief Macro defines for UART Tx Enable register
- */
-#define UART_TER1_TXEN          ((uint8_t) (1 << 7))		/*!< Transmit enable bit */
-#define UART_TER1_BITMASK       ((uint8_t) (0x80))			/*!< UART Transmit Enable Register bit mask */
-#define UART_TER2_TXEN      ((uint8_t) (1 << 0))			/*!< Transmit enable bit */
-#define UART_TER2_BITMASK   ((uint8_t) (0x01))				/*!< UART Transmit Enable Register bit mask */
-
-/**
- * @brief Macro defines for UART1 RS485 Control register
- */
-#define UART_RS485CTRL_NMM_EN       ((uint32_t) (1 << 0))	/*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
-#define UART_RS485CTRL_RX_DIS       ((uint32_t) (1 << 1))	/*!< The receiver is disabled */
-#define UART_RS485CTRL_AADEN        ((uint32_t) (1 << 2))	/*!< Auto Address Detect (AAD) is enabled */
-#define UART_RS485CTRL_SEL_DTR      ((uint32_t) (1 << 3))	/*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
-															    used for direction control */
-#define UART_RS485CTRL_DCTRL_EN ((uint32_t) (1 << 4))		/*!< Enable Auto Direction Control */
-#define UART_RS485CTRL_OINV_1       ((uint32_t) (1 << 5))	/*!< This bit reverses the polarity of the direction
-															   control signal on the RTS (or DTR) pin. The direction control pin
-															   will be driven to logic "1" when the transmitter has data to be sent */
-#define UART_RS485CTRL_BITMASK      ((uint32_t) (0x3F))		/*!< RS485 control bit-mask value */
-
-/**
- * @brief Macro defines for UART1 RS-485 Address Match register
- */
-#define UART_RS485ADRMATCH_BITMASK ((uint8_t) (0xFF))		/*!< Bit mask value */
-
-/**
- * @brief Macro defines for UART1 RS-485 Delay value register
- */
-#define UART_RS485DLY_BITMASK       ((uint8_t) (0xFF))		/*!< Bit mask value */
-
-/**
- * @brief Macro defines for UART FIFO Level register
- */
-#define UART_FIFOLVL_RXFIFOLVL(n)   ((uint32_t) (n & 0x0F))			/*!< Reflects the current level of the UART receiver FIFO */
-#define UART_FIFOLVL_TXFIFOLVL(n)   ((uint32_t) ((n >> 8) & 0x0F))	/*!< Reflects the current level of the UART transmitter FIFO */
-#define UART_FIFOLVL_BITMASK        ((uint32_t) (0x0F0F))			/*!< UART FIFO Level Register bit mask */
-
-/**
- * @brief Macro defines for Ring Buffer
- */
-#define UART_RING_BUFSIZE 256															/*!< buffer size definition */
-#define __BUF_MASK (UART_RING_BUFSIZE - 1)												/*!< Buf mask */
-#define __BUF_IS_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 1) & __BUF_MASK))	/*!< Check buf is full or not */
-#define __BUF_WILL_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 2) & __BUF_MASK))	/*!< Check buf will be full in next receiving or not */
-#define __BUF_IS_EMPTY(head, tail) ((head & __BUF_MASK) == (tail & __BUF_MASK))			/*!< Check buf is empty */
-#define __BUF_RESET(bufidx) (bufidx = 0)												/*!< Reset buf */
-#define __BUF_INCR(bufidx)  (bufidx = (bufidx + 1) & __BUF_MASK)						/*!< Increase buf */
-
-/**
- * @brief UART Ring buffer structure
- */
-typedef struct {
-	__IO uint32_t tx_head;					/*!< UART Tx ring buffer head index */
-	__IO uint32_t tx_tail;					/*!< UART Tx ring buffer tail index */
-	__IO uint32_t rx_head;					/*!< UART Rx ring buffer head index */
-	__IO uint32_t rx_tail;					/*!< UART Rx ring buffer tail index */
-	__IO uint8_t  tx[UART_RING_BUFSIZE];	/*!< UART Tx data ring buffer */
-	__IO uint8_t  rx[UART_RING_BUFSIZE];	/*!< UART Rx data ring buffer */
-} UART_RingBuffer_Type;
-
-/**
- * @brief UART Line Status Type definition
- */
-typedef enum {
-	UART_LINESTAT_RDR   = UART_LSR_RDR,			/*!< Line status register: Receive data ready*/
-	UART_LINESTAT_OE    = UART_LSR_OE,			/*!< Line status register: Overrun error*/
-	UART_LINESTAT_PE    = UART_LSR_PE,			/*!< Line status register: Parity error*/
-	UART_LINESTAT_FE    = UART_LSR_FE,			/*!< Line status register: Framing error*/
-	UART_LINESTAT_BI    = UART_LSR_BI,			/*!< Line status register: Break interrupt*/
-	UART_LINESTAT_THRE  = UART_LSR_THRE,		/*!< Line status register: Transmit holding register empty*/
-	UART_LINESTAT_TEMT  = UART_LSR_TEMT,		/*!< Line status register: Transmitter empty*/
-	UART_LINESTAT_RXFE  = UART_LSR_RXFE			/*!< Error in RX FIFO*/
-} IP_UART_LS_Type;
-
-/**
- * @brief UART End of Auto-baudrate type definition
- */
-typedef enum {
-	UART_AUTOBAUD_INTSTAT_ABEO      = UART_IIR_ABEO_INT,		/*!< UART End of auto-baud interrupt  */
-	UART_AUTOBAUD_INTSTAT_ABTO      = UART_IIR_ABTO_INT			/*!< UART Auto-baud time-out interrupt  */
-} IP_UART_ABEO_Type;
-
-/**
- * @brief UART Full modem -  Signal states definition
- */
-typedef enum {
-	INACTIVE = 0,			/*!< In-active state */
-	ACTIVE = !INACTIVE		/*!< Active state */
-} IP_UART_SignalState;
-
-/**
- * @brief UART modem status type definition
- */
-typedef enum {
-	UART_MODEM_STAT_DELTA_CTS   = UART_MSR_DELTA_CTS,		/*!< Set upon state change of input CTS */
-	UART_MODEM_STAT_DELTA_DSR   = UART_MSR_DELTA_DSR,		/*!< Set upon state change of input DSR */
-	UART_MODEM_STAT_LO2HI_RI    = UART_MSR_LO2HI_RI,		/*!< Set upon low to high transition of input RI */
-	UART_MODEM_STAT_DELTA_DCD   = UART_MSR_DELTA_DCD,		/*!< Set upon state change of input DCD */
-	UART_MODEM_STAT_CTS         = UART_MSR_CTS,				/*!< Clear To Send State */
-	UART_MODEM_STAT_DSR         = UART_MSR_DSR,				/*!< Data Set Ready State */
-	UART_MODEM_STAT_RI          = UART_MSR_RI,				/*!< Ring Indicator State */
-	UART_MODEM_STAT_DCD         = UART_MSR_DCD				/*!< Data Carrier Detect State */
-} IP_UART_MODEM_STAT_type;
-
-/**
- * @brief Modem output pin type definition
- */
-typedef enum {
-	UART_MODEM_PIN_DTR          = 0,		/*!< Source for modem output pin DTR */
-	UART_MODEM_PIN_RTS						/*!< Source for modem output pin RTS */
-} IP_UART_MODEM_PIN_Type;
-
-/**
- * @brief UART Modem mode type definition
- */
-typedef enum {
-	UART_MODEM_MODE_LOOPBACK    = 0,		/*!< Loop back mode select */
-	UART_MODEM_MODE_AUTO_RTS,				/*!< Enable Auto RTS flow-control */
-	UART_MODEM_MODE_AUTO_CTS				/*!< Enable Auto CTS flow-control */
-} IP_UART_MODEM_MODE_Type;
-
-/**
- * @brief UART Interrupt Type definitions
- */
-typedef enum {
-	UART_INTCFG_RBR = 0,	/*!< RBR Interrupt enable*/
-	UART_INTCFG_THRE,		/*!< THR Interrupt enable*/
-	UART_INTCFG_RLS,		/*!< RX line status interrupt enable*/
-	UART_INTCFG_MS,			/*!< Modem status interrupt enable */
-	UART_INTCFG_CTS,		/*!< CTS1 signal transition interrupt enable */
-	UART_INTCFG_ABEO,		/*!< Enables the end of auto-baud interrupt */
-	UART_INTCFG_ABTO		/*!< Enables the auto-baud time-out interrupt */
-} UART_INT_Type;
-
-/**
- * @brief UART Parity type definitions
- */
-typedef enum {
-	UART_PARITY_NONE = 0,									/*!< No parity */
-	UART_PARITY_ODD = (4 << 3),								/*!< Odd parity */
-	UART_PARITY_EVEN = (5 << 3),							/*!< Even parity */
-	UART_PARITY_SP_1 = (6 << 3),							/*!< Forced "1" stick parity */
-	UART_PARITY_SP_0 = (7 << 3)								/*!< Forced "0" stick parity */
-} UART_PARITY_Type;
-
-/**
- * @brief FIFO Level type definitions
- */
-typedef enum {
-	UART_FIFO_TRGLEV0 = 0,	/*!< UART FIFO trigger level 0: 1 character */
-	UART_FIFO_TRGLEV1,		/*!< UART FIFO trigger level 1: 4 character */
-	UART_FIFO_TRGLEV2,		/*!< UART FIFO trigger level 2: 8 character */
-	UART_FIFO_TRGLEV3		/*!< UART FIFO trigger level 3: 14 character */
-} UART_FITO_LEVEL_Type;
-
-/**
- * @brief UART Stop bit type definitions
- */
-typedef enum {
-	UART_STOPBIT_1 = 0,							/*!< UART One Stop Bit Select */
-	UART_STOPBIT_2 = (1 << 2)					/*!< UART Two Stop Bits Select */
-} UART_STOPBIT_Type;
-
-/**
- * @brief UART Databit type definitions
- */
-typedef enum {
-	UART_DATABIT_5      = 0,			/*!< UART 5 bit data mode */
-	UART_DATABIT_6,						/*!< UART 6 bit data mode */
-	UART_DATABIT_7,						/*!< UART 7 bit data mode */
-	UART_DATABIT_8						/*!< UART 8 bit data mode */
-} UART_DATABIT_Type;
-
-/**
- * @brief UART ID
- */
-typedef enum {
-	UART_0 = 0,
-	UART_1,
-	UART_2,
-	UART_3,
-	UART_4,
-} UART_ID_Type;
-
-/**
- * @brief UART Interrupt Status
- */
-typedef enum {
-	UART_ERROR = 1,
-	READY_TO_SEND,
-	READY_TO_RECEIVE = 4,
-} UART_Int_Status;
-
-/**
- * @brief UART FIFO Configuration Structure definition
- */
-typedef struct {
-	FunctionalState FIFO_ResetRxBuf;	/*!< Reset Rx FIFO command state , should be:
-										   - ENABLE: Reset Rx FIFO in UART
-										   - DISABLE: Do not reset Rx FIFO  in UART
-										 */
-	FunctionalState FIFO_ResetTxBuf;	/*!< Reset Tx FIFO command state , should be:
-										   - ENABLE: Reset Tx FIFO in UART
-										   - DISABLE: Do not reset Tx FIFO  in UART
-										 */
-	FunctionalState FIFO_DMAMode;		/*!< DMA mode, should be:
-										   - ENABLE: Enable DMA mode in UART
-										   - DISABLE: Disable DMA mode in UART
-										 */
-	UART_FITO_LEVEL_Type FIFO_Level;	/*!< Rx FIFO trigger level, should be:
-										   - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
-										   - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
-										   - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
-										   - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
-										 */
-} UART_FIFO_CFG_Type;
-
-/**
- * @brief	Initializes the UARTx peripheral according to the specified parameters in the UART_ConfigStruct.
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	UARTPort	: UART ID type
- * @return	Nothing
- */
-void IP_UART_Init(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort);
-
-/**
- * @brief	De-initializes the UARTx peripheral registers to their default reset values.
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	UARTPort	: UART ID type
- * @return	Nothing
- */
-void IP_UART_DeInit(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort);
-
-/**
- * @brief	Determines best dividers to get a target clock rate
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	baudrate	: Desired UART baud rate.
- * @param	uClk		: Current Uart Block Clock.
- * @return	Error status, could be SUCCESS or ERROR
- */
-Status IP_UART_SetBaud(IP_USART_001_Type *LPC_UART, uint32_t baudrate, uint32_t uClk);
-
-/**
- * @brief	Configure data width, parity mode and stop bits
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	Databits	: UART Data width, should be:
- *                  		UART_DATABIT_5: UART 5 bit data mode
- *                  		UART_DATABIT_6: UART 6 bit data mode
- *                  		UART_DATABIT_7: UART 7 bit data mode
- *                  		UART_DATABIT_8: UART 8 bit data mode
- * @param	Parity		: UART Parity mode, should be:
- *                  		UART_PARITY_NONE: No parity
- *                  		UART_PARITY_ODD:  Odd parity
- *                  		UART_PARITY_EVEN: Even parity
- *                  		UART_PARITY_SP_1: Forced "1" stick parity
- *                  		UART_PARITY_SP_0: Forced "0" stick parity
- * @param	Stopbits	: Number of stop bits, should be:
- *                  		UART_STOPBIT_1: One Stop Bit Select
- *                  		UART_STOPBIT_2: Two Stop Bits Select
- * @return	Nothing
- */
-void IP_UART_ConfigData(IP_USART_001_Type *LPC_UART,
-						UART_DATABIT_Type Databits,
-						UART_PARITY_Type Parity,
-						UART_STOPBIT_Type Stopbits);
-
-/* UART Send/Receive functions -------------------------------------------------*/
-/**
- * @brief	Transmit a single data through UART peripheral
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	Data		: Data to transmit (must be 8-bit long)
- * @return	Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)
- */
-Status IP_UART_SendByte(IP_USART_001_Type *LPC_UART, uint8_t Data);
-
-/**
- * @brief	Receive a single data from UART peripheral
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	*Data		: Pointer to Data to receive (must be 8-bit long)
- * @return	Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)
- */
-Status IP_UART_ReceiveByte(IP_USART_001_Type *LPC_UART, uint8_t *Data);
-
-/**
- * @brief	Send a block of data via UART peripheral
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	txbuf		: Pointer to Transmit buffer
- * @param	buflen		: Length of Transmit buffer
- * @param   flag		: Flag used in  UART transfer, should be NONE_BLOCKING or BLOCKING
- * @return	Number of bytes sent
- *
- * Note: when using UART in BLOCKING mode, a time-out condition is used
- * via defined symbol UART_BLOCKING_TIMEOUT.
- */
-uint32_t IP_UART_Send(IP_USART_001_Type *LPC_UART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag);
-
-/**
- * @brief	Receive a block of data via UART peripheral
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	rxbuf		: Pointer to Received buffer
- * @param	buflen		: Length of Received buffer
- * @param   flag		: Flag mode, should be NONE_BLOCKING or BLOCKING
- * @return	Number of bytes received
- *
- * Note: when using UART in BLOCKING mode, a time-out condition is used
- * via defined symbol UART_BLOCKING_TIMEOUT.
- */
-uint32_t IP_UART_Receive(IP_USART_001_Type *LPC_UART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag);
-
-/* UART operate functions -------------------------------------------------------*/
-/**
- * @brief	Enable or disable specified UART interrupt.
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	UARTIntCfg	: Specifies the interrupt flag, should be one of the following:
- *                  - UART_INTCFG_RBR   : RBR Interrupt enable
- *                  - UART_INTCFG_THRE  : THR Interrupt enable
- *                  - UART_INTCFG_RLS   : RX line status interrupt enable
- *                  - UART1_INTCFG_MS	: Modem status interrupt enable (UART1 only)
- *                  - UART1_INTCFG_CTS	: CTS1 signal transition interrupt enable (UART1 only)
- *                  - UART_INTCFG_ABEO  : Enables the end of auto-baud interrupt
- *                  - UART_INTCFG_ABTO  : Enables the auto-baud time-out interrupt
- * @param	NewState	: New state of specified UART interrupt type, should be:
- *                  - ENALBE	: Enable this UART interrupt type
- *                  - DISALBE	: Disable this UART interrupt type
- * @return	Nothing
- */
-void IP_UART_IntConfig(IP_USART_001_Type *LPC_UART, UART_INT_Type UARTIntCfg, FunctionalState NewState);
-
-/**
- * @brief	Get Source Interrupt
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @return	Return the value of IIR register
-*/
-uint32_t IP_UART_IntGetStatus(IP_USART_001_Type *LPC_UART);
-
-/**
- * @brief	Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @return	Nothing
- */
-void IP_UART_ForceBreak(IP_USART_001_Type *LPC_UART);
-
-/**
- * @brief	Get current value of Line Status register in UART peripheral.
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @return	Current value of Line Status register in UART peripheral
- *
- * Note:	The return value of this function must be ANDed with each member in UART_LS_Type
- * enumeration to determine current flag status corresponding to each Line status type. Because
- * some flags in Line Status register will be cleared after reading, the next reading Line
- * Status register could not be correct. So this function used to read Line status register
- * in one time only, then the return value used to check all flags.
- */
-uint8_t IP_UART_GetLineStatus(IP_USART_001_Type *LPC_UART);
-
-/**
- * @brief	Check whether if UART is busy or not
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @return	RESET if UART is not busy, otherwise return SET.
- */
-FlagStatus IP_UART_CheckBusy(IP_USART_001_Type *LPC_UART);
-
-/**
- * @brief	Enable/Disable transmission on UART TxD pin
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	UARTPort	: UART ID type
- * @param	NewState	: New State of Tx transmission function, should be ENABLE or DISABLE
- * @return	Nothing
- */
-void IP_UART_TxCmd(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort, FunctionalState NewState);
-
-/* UART FIFO functions ----------------------------------------------------------*/
-/**
- * @brief	Configure FIFO function on selected UART peripheral
- * @param	LPC_UART	: Pointer to selected UARTx peripheral
- * @param	FIFOCfg		: Pointer to a UART_FIFO_CFG_Type Structure that contains specified information about FIFO configuration
- * @return	Nothing
- */
-void IP_UART_FIFOConfig(IP_USART_001_Type *LPC_UART, UART_FIFO_CFG_Type *FIFOCfg);
-
-/**
- * @brief	Fills each UART_FIFOInitStruct member with its default value:
- *			- FIFO_DMAMode = DISABLE
- *			- FIFO_Level = UART_FIFO_TRGLEV0
- *			- FIFO_ResetRxBuf = ENABLE
- *			- FIFO_ResetTxBuf = ENABLE
- *			- FIFO_State = ENABLE
- * @param	UART_FIFOInitStruct	: Pointer to a UART_FIFO_CFG_Type structure which will be initialized.
- * @return	Nothing
-*/
-void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USART_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h b/bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h
deleted file mode 100644
index c9b1753aad..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * @brief High-Speed USB registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __USBHS_001_H_
-#define __USBHS_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_USBHS_001 IP: USBHS Device, Host, & OTG register block and driver
- * @ingroup IP_Drivers
- * USB High-Speed Device, Host, & OTG
- * Note: On the LPC18xx and LPC43xx, only USB0 supports OTG
- * @{
- */
-
-/**
- * @brief USB High-Speed register block structure
- */
-typedef struct {							/*!< USB Structure         */
-	__I  uint32_t  RESERVED0[64];
-	__I  uint32_t  CAPLENGTH;				/*!< Capability register length */
-	__I  uint32_t  HCSPARAMS;				/*!< Host controller structural parameters */
-	__I  uint32_t  HCCPARAMS;				/*!< Host controller capability parameters */
-	__I  uint32_t  RESERVED1[5];
-	__I  uint32_t  DCIVERSION;				/*!< Device interface version number */
-	__I  uint32_t  RESERVED2[7];
-	union {
-		__IO uint32_t  USBCMD_H;			/*!< USB command (host mode) */
-		__IO uint32_t  USBCMD_D;			/*!< USB command (device mode) */
-	};
-
-	union {
-		__IO uint32_t  USBSTS_H;			/*!< USB status (host mode) */
-		__IO uint32_t  USBSTS_D;			/*!< USB status (device mode) */
-	};
-
-	union {
-		__IO uint32_t  USBINTR_H;			/*!< USB interrupt enable (host mode) */
-		__IO uint32_t  USBINTR_D;			/*!< USB interrupt enable (device mode) */
-	};
-
-	union {
-		__IO uint32_t  FRINDEX_H;			/*!< USB frame index (host mode) */
-		__I  uint32_t  FRINDEX_D;			/*!< USB frame index (device mode) */
-	};
-
-	__I  uint32_t  RESERVED3;
-	union {
-		__IO uint32_t  PERIODICLISTBASE;	/*!< Frame list base address */
-		__IO uint32_t  DEVICEADDR;			/*!< USB device address     */
-	};
-
-	union {
-		__IO uint32_t  ASYNCLISTADDR;		/*!< Address of endpoint list in memory (host mode) */
-		__IO uint32_t  ENDPOINTLISTADDR;	/*!< Address of endpoint list in memory (device mode) */
-	};
-
-	__IO uint32_t  TTCTRL;					/*!< Asynchronous buffer status for embedded TT (host mode) */
-	__IO uint32_t  BURSTSIZE;				/*!< Programmable burst size */
-	__IO uint32_t  TXFILLTUNING;			/*!< Host transmit pre-buffer packet tuning (host mode) */
-	__I  uint32_t  RESERVED4[2];
-	__IO uint32_t  ULPIVIEWPORT;			/*!< ULPI viewport          */
-	__IO uint32_t  BINTERVAL;				/*!< Length of virtual frame */
-	__IO uint32_t  ENDPTNAK;				/*!< Endpoint NAK (device mode) */
-	__IO uint32_t  ENDPTNAKEN;				/*!< Endpoint NAK Enable (device mode) */
-	__I  uint32_t  RESERVED5;
-	union {
-		__IO uint32_t  PORTSC1_H;			/*!< Port 1 status/control (host mode) */
-		__IO uint32_t  PORTSC1_D;			/*!< Port 1 status/control (device mode) */
-	};
-
-	__I  uint32_t  RESERVED6[7];
-	__IO uint32_t  OTGSC;					/*!< OTG status and control */
-	union {
-		__IO uint32_t  USBMODE_H;			/*!< USB mode (host mode)   */
-		__IO uint32_t  USBMODE_D;			/*!< USB mode (device mode) */
-	};
-
-	__IO uint32_t  ENDPTSETUPSTAT;			/*!< Endpoint setup status  */
-	__IO uint32_t  ENDPTPRIME;				/*!< Endpoint initialization */
-	__IO uint32_t  ENDPTFLUSH;				/*!< Endpoint de-initialization */
-	__I  uint32_t  ENDPTSTAT;				/*!< Endpoint status        */
-	__IO uint32_t  ENDPTCOMPLETE;			/*!< Endpoint complete      */
-	__IO uint32_t  ENDPTCTRL[6];			/*!< Endpoint control 0     */
-} IP_USBHS_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBHS_001_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h b/bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h
deleted file mode 100644
index 3d8c981224..0000000000
--- a/bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * @brief	WWDT Registers and functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products.  This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights.  NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers.  This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __WWDT_001_H_
-#define __WWDT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_WWDT_001 IP: WWDT register block and driver
- * @ingroup IP_Drivers
- * Windowed Watchdog
- * @{
- */
-
-/**
- * @brief Windowed Watchdog register block structure
- */
-typedef struct {				/*!< WWDT Structure         */
-	__IO uint32_t  MOD;			/*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
-	__IO uint32_t  TC;			/*!< Watchdog timer constant register. This register determines the time-out value. */
-	__O  uint32_t  FEED;		/*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
-	__I  uint32_t  TV;			/*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
-#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC175X_6X)
-	__IO uint32_t CLKSEL;		/*!< Watchdog clock select register. */
-#else
-	__I  uint32_t  RESERVED0;
-#endif
-#if !defined(CHIP_LPC175X_6X)
-	__IO uint32_t  WARNINT;		/*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
-	__IO uint32_t  WINDOW;		/*!< Watchdog timer window register. This register contains the Watchdog window value. */
-#endif
-} IP_WWDT_001_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __WWDT_001_H_ */
diff --git a/bsp/xplorer4330/libraries/startup_code/SConscript b/bsp/xplorer4330/libraries/startup_code/SConscript
deleted file mode 100644
index e1f355b063..0000000000
--- a/bsp/xplorer4330/libraries/startup_code/SConscript
+++ /dev/null
@@ -1,22 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-# add for startup code
-if rtconfig.CROSS_TOOL == 'gcc':
-    src = ['gcc_startup_lpc18xx43xx.s']
-elif rtconfig.CROSS_TOOL == 'keil':
-    src = ['keil_startup_lpc18xx43xx.s']
-elif rtconfig.CROSS_TOOL == 'iar':
-    src = ['iar_startup_lpc18xx43xx.s']
-
-if GetDepend(['RT_USING_BSP_CMSIS']):
-    path = [cwd + '/CM3/CoreSupport']
-    src += ['CM3/CoreSupport/core_cm3.c']
-elif GetDepend(['RT_USING_RTT_CMSIS']):
-    path = [RTT_ROOT + '/components/CMSIS/Include']
-
-CPPDEFINES = ['CORE_M4']
-group = DefineGroup('startup', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')
diff --git a/bsp/xplorer4330/libraries/startup_code/gcc_startup_lpc18xx43xx.s b/bsp/xplorer4330/libraries/startup_code/gcc_startup_lpc18xx43xx.s
deleted file mode 100644
index 56ed603169..0000000000
--- a/bsp/xplorer4330/libraries/startup_code/gcc_startup_lpc18xx43xx.s
+++ /dev/null
@@ -1,300 +0,0 @@
-/*****************************************************************************/
-/* startup_LPC18xx.s: Startup file for LPC18xx device series                 */
-/*****************************************************************************/
-/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
-/*****************************************************************************/
-
-
-/*
-//*** <<< Use Configuration Wizard in Context Menu >>> ***
-*/
-
-
-/*
-// <h> Stack Configuration
-//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Stack_Size, 0x00000200
-    .equ    Sign_Value, 0x5A5A5A5A
-    .section ".stack", "w"
-    .align  3
-    .globl  __cs3_stack_mem
-    .globl  __cs3_stack_size
-__cs3_stack_mem:
-    .if     Stack_Size
-    .space  Stack_Size
-    .endif
-    .size   __cs3_stack_mem,  . - __cs3_stack_mem
-    .set    __cs3_stack_size, . - __cs3_stack_mem
-
-
-/*
-// <h> Heap Configuration
-//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Heap_Size,  0x00001000
-
-    .section ".heap", "w"
-    .align  3
-    .globl  __cs3_heap_start
-    .globl  __cs3_heap_end
-__cs3_heap_start:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-__cs3_heap_end:
-
-
-/* Vector Table */
-
-    .section ".cs3.interrupt_vector"
-    .globl  __cs3_interrupt_vector_cortex_m
-    .type   __cs3_interrupt_vector_cortex_m, %object
-
-__cs3_interrupt_vector_cortex_m:
-    .long   _estack                     /* Top of Stack                 */
-    .long   Reset_Handler               /* Reset Handler                */
-    .long   NMI_Handler                 /* NMI Handler                  */
-    .long   HardFault_Handler           /* Hard Fault Handler           */
-    .long   MemManage_Handler           /* MPU Fault Handler            */
-    .long   BusFault_Handler            /* Bus Fault Handler            */
-    .long   UsageFault_Handler          /* Usage Fault Handler          */
-    .long   Sign_Value                  /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   SVC_Handler                 /* SVCall Handler               */
-    .long   DebugMon_Handler            /* Debug Monitor Handler        */
-    .long   0                           /* Reserved                     */
-    .long   PendSV_Handler              /* PendSV Handler               */
-    .long   SysTick_Handler             /* SysTick Handler              */
-
-    /* External Interrupts */
-    .long	DAC_IRQHandler	 			/* 16 D/A Converter */
-	.long	MX_CORE_IRQHandler			/* 17 M0/M4 IRQ handler (LPC43XX ONLY) */
-	.long	DMA_IRQHandler				/* 18 General Purpose DMA */
-	.long	UnHandled_Vector			/* 19 Reserved */
-	.long	FLASHEEPROM_IRQHandler		/* 20 ORed flash bank A, flash bank B, EEPROM interrupts */
-	.long	ETH_IRQHandler				/* 21 Ethernet */
-	.long	SDIO_IRQHandler				/* 22 SD/MMC */
-	.long	LCD_IRQHandler				/* 23 LCD */
-	.long	USB0_IRQHandler				/* 24 USB0*/
-	.long	USB1_IRQHandler				/* 25 USB1*/
-	.long	SCT_IRQHandler				/* 26 State Configurable Timer*/
-	.long	RIT_IRQHandler				/* 27 Repetitive Interrupt Timer*/
-	.long	TIMER0_IRQHandler			/* 28 Timer0*/
-	.long	TIMER1_IRQHandler			/* 29 Timer1*/
-	.long	TIMER2_IRQHandler			/* 30 Timer2*/
-	.long	TIMER3_IRQHandler			/* 31 Timer3*/
-	.long	MCPWM_IRQHandler			/* 32 Motor Control PWM*/
-	.long	ADC0_IRQHandler				/* 33 A/D Converter 0*/
-	.long	I2C0_IRQHandler				/* 34 I2C0*/
-	.long	I2C1_IRQHandler				/* 35 I2C1*/
-	.long	SPI_IRQHandler				/* 36 SPI (LPC43XX ONLY)*/
-	.long	ADC1_IRQHandler				/* 37 A/D Converter 1*/
-	.long	SSP0_IRQHandler				/* 38 SSP0*/
-	.long	SSP1_IRQHandler				/* 39 SSP1*/
-	.long	UART0_IRQHandler			/* 40 UART0*/
-	.long	UART1_IRQHandler			/* 41 UART1*/
-	.long	UART2_IRQHandler			/* 42 UART2*/
-	.long	UART3_IRQHandler			/* 43 UART3*/
-	.long	I2S0_IRQHandler				/* 44 I2S*/
-	.long 	I2S1_IRQHandler				/* 45 AES Engine*/
-	.long 	SPIFI_IRQHandler			/* 46 SPI Flash Interface*/
-	.long	SGPIO_IRQHandler			/* 47 SGPIO*/
-	.long	GPIO0_IRQHandler			/* 48 GPIO0*/
-	.long	GPIO1_IRQHandler			/* 49 GPIO1*/
-	.long	GPIO2_IRQHandler			/* 50 GPIO2*/
-	.long	GPIO3_IRQHandler			/* 51 GPIO3*/
-	.long	GPIO4_IRQHandler			/* 52 GPIO4*/
-	.long	GPIO5_IRQHandler			/* 53 GPIO5*/
-	.long	GPIO6_IRQHandler			/* 54 GPIO6*/
-	.long	GPIO7_IRQHandler			/* 55 GPIO7*/
-	.long	GINT0_IRQHandler			/* 56 GINT0*/
-	.long	GINT1_IRQHandler			/* 57 GINT1*/
-	.long	EVRT_IRQHandler				/* 58 Event Router*/
-	.long	CAN1_IRQHandler				/* 59 C_CAN1*/
-	.long	UnHandled_Vector			/* 60 Reserved*/
-	.long	VADC_IRQHandler				/* 61 VADC*/
-	.long	ATIMER_IRQHandler			/* 62 ATIMER*/
-	.long	RTC_IRQHandler				/* 63 RTC*/
-	.long	UnHandled_Vector			/* 64 Reserved*/
-	.long	WDT_IRQHandler				/* 65 WDT*/
-	.long	UnHandled_Vector			/* 66 M0s*/
-	.long	CAN0_IRQHandler				/* 67 C_CAN0*/
-	.long 	QEI_IRQHandler				/* 68 QEI*/
-
-    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
-
-
-    .thumb
-
-
-/* Reset Handler */
-
-    .section  .text.Reset_Handler
-    .thumb_func
-    .globl  Reset_Handler
-    .type  Reset_Handler, %function
-Reset_Handler:
-    .fnstart
-/* .if (RAM_MODE) */
- .if 0
-/* Clear .bss section (Zero init) */
-	MOV     R0, #0
-	LDR     R1, =__bss_start__
-	LDR     R2, =__bss_end__
-	CMP     R1,R2
-	BEQ     BSSIsEmpty
-LoopZI:
-	CMP     R1, R2
-	BHS		BSSIsEmpty
-	STR   	R0, [R1]
-	ADD		R1, #4
-	BLO     LoopZI
-BSSIsEmpty:
-    LDR     R0,=main
-    BX      R0
-.else
-    LDR     R0, =SystemInit
-    BLX     R0
-    LDR     R0,=main
-    BX      R0
-.endif
-    .pool
-    .cantunwind
-    .fnend
-    .size   Reset_Handler,.-Reset_Handler
-
-    .section ".text"
-
-/* Exception Handlers */
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   MemManage_Handler
-    .type   MemManage_Handler, %function
-MemManage_Handler:
-    B       .
-    .size   MemManage_Handler, . - MemManage_Handler
-
-    .weak   BusFault_Handler
-    .type   BusFault_Handler, %function
-BusFault_Handler:
-    B       .
-    .size   BusFault_Handler, . - BusFault_Handler
-
-    .weak   UsageFault_Handler
-    .type   UsageFault_Handler, %function
-UsageFault_Handler:
-    B       .
-    .size   UsageFault_Handler, . - UsageFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   DebugMon_Handler
-    .type   DebugMon_Handler, %function
-DebugMon_Handler:
-    B       .
-    .size   DebugMon_Handler, . - DebugMon_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-
-/* IRQ Handlers */
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .globl  UnHandled_Vector
-    .type   UnHandled_Vector, %function
-UnHandled_Vector:
-    B       .
-    .size   UnHandled_Vector, . - UnHandled_Vector
-    
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ DAC_IRQHandler
-    IRQ MX_CORE_IRQHandler
-	IRQ DMA_IRQHandler
-	IRQ FLASHEEPROM_IRQHandler
-	IRQ ETH_IRQHandler
-	IRQ SDIO_IRQHandler
-	IRQ LCD_IRQHandler
-	IRQ USB0_IRQHandler
-	IRQ USB1_IRQHandler
-	IRQ SCT_IRQHandler
-	IRQ RIT_IRQHandler
-	IRQ TIMER0_IRQHandler
-	IRQ TIMER1_IRQHandler
-	IRQ TIMER2_IRQHandler
-	IRQ TIMER3_IRQHandler
-	IRQ MCPWM_IRQHandler
-	IRQ ADC0_IRQHandler
-	IRQ I2C0_IRQHandler
-	IRQ I2C1_IRQHandler
-	IRQ SPI_IRQHandler
-	IRQ ADC1_IRQHandler
-	IRQ SSP0_IRQHandler
-	IRQ SSP1_IRQHandler
-	IRQ UART0_IRQHandler
-	IRQ UART1_IRQHandler
-	IRQ UART2_IRQHandler
-	IRQ UART3_IRQHandler
-	IRQ I2S0_IRQHandler
-	IRQ I2S1_IRQHandler
-	IRQ SPIFI_IRQHandler
-	IRQ	SGPIO_IRQHandler
-	IRQ	GPIO0_IRQHandler
-	IRQ	GPIO1_IRQHandler
-	IRQ	GPIO2_IRQHandler
-	IRQ	GPIO3_IRQHandler
-	IRQ	GPIO4_IRQHandler
-	IRQ	GPIO5_IRQHandler
-	IRQ	GPIO6_IRQHandler
-	IRQ	GPIO7_IRQHandler
-	IRQ	GINT0_IRQHandler
-	IRQ	GINT1_IRQHandler
-	IRQ	EVRT_IRQHandler
-	IRQ	CAN1_IRQHandler
-	IRQ	VADC_IRQHandler
-	IRQ	ATIMER_IRQHandler
-	IRQ	RTC_IRQHandler
-	IRQ	WDT_IRQHandler
-	IRQ	CAN0_IRQHandler
-	IRQ	QEI_IRQHandler
-    .end
diff --git a/bsp/xplorer4330/libraries/startup_code/keil_startup_lpc18xx43xx.s b/bsp/xplorer4330/libraries/startup_code/keil_startup_lpc18xx43xx.s
deleted file mode 100644
index c3cc4df734..0000000000
--- a/bsp/xplorer4330/libraries/startup_code/keil_startup_lpc18xx43xx.s
+++ /dev/null
@@ -1,327 +0,0 @@
-;/***********************************************************************
-; * Project: LPC18xx/43xx startup code
-; *
-; * Description: LPC18xx/43xx startup code
-; *
-; * Copyright(C) 2011, NXP Semiconductor
-; * All rights reserved.
-; *
-; ***********************************************************************
-; * Software that is described herein is for illustrative purposes only
-; * which provides customers with programming information regarding the
-; * products. This software is supplied "AS IS" without any warranties.
-; * NXP Semiconductors assumes no responsibility or liability for the
-; * use of the software, conveys no license or title under any patent,
-; * copyright, or mask work right to the product. NXP Semiconductors
-; * reserves the right to make changes in the software without
-; * notification. NXP Semiconductors also make no representation or
-; * warranty that such application will be suitable for the specified
-; * use without further testing or modification.
-; **********************************************************************/
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000200
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-Sign_Value      EQU     0x5A5A5A5A
-
-__Vectors       DCD     __initial_sp                    ; 0 Top of Stack
-                DCD     Reset_Handler                   ; 1 Reset Handler
-                DCD     NMI_Handler                     ; 2 NMI Handler
-                DCD     HardFault_Handler               ; 3 Hard Fault Handler
-                DCD     MemManage_Handler               ; 4 MPU Fault Handler
-                DCD     BusFault_Handler                ; 5 Bus Fault Handler
-                DCD     UsageFault_Handler              ; 6 Usage Fault Handler
-                DCD     Sign_Value                      ; 7 Reserved
-                DCD     UnHandled_Vector                ; 8 Reserved
-                DCD     UnHandled_Vector                ; 9 Reserved
-                DCD     UnHandled_Vector                ; 10 Reserved
-                DCD     SVC_Handler                     ; 11 SVCall Handler
-                DCD     DebugMon_Handler                ; 12 Debug Monitor Handler
-                DCD     UnHandled_Vector                ; 13 Reserved
-                DCD     PendSV_Handler                  ; 14 PendSV Handler
-                DCD     SysTick_Handler                 ; 15 SysTick Handler
-
-                ; External Interrupts
-                DCD     DAC_IRQHandler                  ; 16 D/A Converter
-                DCD     MX_CORE_IRQHandler              ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
-                DCD     DMA_IRQHandler                  ; 18 General Purpose DMA
-                DCD     UnHandled_Vector                ; 19 Reserved
-                DCD     FLASHEEPROM_IRQHandler          ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
-                DCD     ETH_IRQHandler                  ; 21 Ethernet
-                DCD     SDIO_IRQHandler                 ; 22 SD/MMC
-                DCD     LCD_IRQHandler                  ; 23 LCD
-                DCD     USB0_IRQHandler                 ; 24 USB0
-                DCD     USB1_IRQHandler                 ; 25 USB1
-                DCD     SCT_IRQHandler                  ; 26 State Configurable Timer
-                DCD     RIT_IRQHandler                  ; 27 Repetitive Interrupt Timer
-                DCD     TIMER0_IRQHandler               ; 28 Timer0
-                DCD     TIMER1_IRQHandler               ; 29 Timer1
-                DCD     TIMER2_IRQHandler               ; 30 Timer2
-                DCD     TIMER3_IRQHandler               ; 31 Timer3
-                DCD     MCPWM_IRQHandler                ; 32 Motor Control PWM
-                DCD     ADC0_IRQHandler                 ; 33 A/D Converter 0
-                DCD     I2C0_IRQHandler                 ; 34 I2C0
-                DCD     I2C1_IRQHandler                 ; 35 I2C1
-                DCD     SPI_IRQHandler                  ; 36 SPI (LPC43XX ONLY)
-                DCD     ADC1_IRQHandler                 ; 37 A/D Converter 1
-                DCD     SSP0_IRQHandler                 ; 38 SSP0
-                DCD     SSP1_IRQHandler                 ; 39 SSP1
-                DCD     UART0_IRQHandler                ; 40 UART0
-                DCD     UART1_IRQHandler                ; 41 UART1
-                DCD     UART2_IRQHandler                ; 42 UART2
-                DCD     UART3_IRQHandler                ; 43 UART3
-                DCD     I2S0_IRQHandler                 ; 44 I2S0
-                DCD     I2S1_IRQHandler                 ; 45 I2S1
-                DCD     SPIFI_IRQHandler                ; 46 SPI Flash Interface
-                DCD     SGPIO_IRQHandler                ; 47 SGPIO (LPC43XX ONLY)
-                DCD     GPIO0_IRQHandler                ; 48 GPIO0
-                DCD     GPIO1_IRQHandler                ; 49 GPIO1
-                DCD     GPIO2_IRQHandler                ; 50 GPIO2
-                DCD     GPIO3_IRQHandler                ; 51 GPIO3
-                DCD     GPIO4_IRQHandler                ; 52 GPIO4
-                DCD     GPIO5_IRQHandler                ; 53 GPIO5
-                DCD     GPIO6_IRQHandler                ; 54 GPIO6
-                DCD     GPIO7_IRQHandler                ; 55 GPIO7
-                DCD     GINT0_IRQHandler                ; 56 GINT0
-                DCD     GINT1_IRQHandler                ; 57 GINT1
-                DCD     EVRT_IRQHandler                 ; 58 Event Router
-                DCD     CAN1_IRQHandler                 ; 59 C_CAN1
-                DCD     UnHandled_Vector                ; 60 Reserved
-                DCD     VADC_IRQHandler                 ; 61 VADC
-                DCD     ATIMER_IRQHandler               ; 62 ATIMER
-                DCD     RTC_IRQHandler                  ; 63 RTC
-                DCD     UnHandled_Vector                ; 64 Reserved
-                DCD     WDT_IRQHandler                  ; 65 WDT
-                DCD     UnHandled_Vector                ; 66 M0s
-                DCD     CAN0_IRQHandler                 ; 67 C_CAN0
-                DCD     QEI_IRQHandler                  ; 68 QEI
-
-
-;               IF      :LNOT::DEF:NO_CRP
-;               AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-;CRP_Key        DCD     0xFFFFFFFF
-;               ENDIF
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0
-
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-UnHandled_Vector        PROC
-                EXPORT  UnHandled_Vector          [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT DAC_IRQHandler           [WEAK]
-                EXPORT MX_CORE_IRQHandler       [WEAK]
-                EXPORT DMA_IRQHandler           [WEAK]
-                EXPORT FLASHEEPROM_IRQHandler   [WEAK]
-                EXPORT ETH_IRQHandler           [WEAK]
-                EXPORT SDIO_IRQHandler          [WEAK]
-                EXPORT LCD_IRQHandler           [WEAK]
-                EXPORT USB0_IRQHandler          [WEAK]
-                EXPORT USB1_IRQHandler          [WEAK]
-                EXPORT SCT_IRQHandler           [WEAK]
-                EXPORT RIT_IRQHandler           [WEAK]
-                EXPORT TIMER0_IRQHandler        [WEAK]
-                EXPORT TIMER1_IRQHandler        [WEAK]
-                EXPORT TIMER2_IRQHandler        [WEAK]
-                EXPORT TIMER3_IRQHandler        [WEAK]
-                EXPORT MCPWM_IRQHandler         [WEAK]
-                EXPORT ADC0_IRQHandler          [WEAK]
-                EXPORT I2C0_IRQHandler          [WEAK]
-                EXPORT I2C1_IRQHandler          [WEAK]
-                EXPORT SPI_IRQHandler           [WEAK]
-                EXPORT ADC1_IRQHandler          [WEAK]
-                EXPORT SSP0_IRQHandler          [WEAK]
-                EXPORT SSP1_IRQHandler          [WEAK]
-                EXPORT UART0_IRQHandler         [WEAK]
-                EXPORT UART1_IRQHandler         [WEAK]
-                EXPORT UART2_IRQHandler         [WEAK]
-                EXPORT UART3_IRQHandler         [WEAK]
-                EXPORT I2S0_IRQHandler          [WEAK]
-                EXPORT I2S1_IRQHandler          [WEAK]
-                EXPORT SPIFI_IRQHandler         [WEAK]
-                EXPORT SGPIO_IRQHandler         [WEAK]
-                EXPORT GPIO0_IRQHandler         [WEAK]
-                EXPORT GPIO1_IRQHandler         [WEAK]
-                EXPORT GPIO2_IRQHandler         [WEAK]
-                EXPORT GPIO3_IRQHandler         [WEAK]
-                EXPORT GPIO4_IRQHandler         [WEAK]
-                EXPORT GPIO5_IRQHandler         [WEAK]
-                EXPORT GPIO6_IRQHandler         [WEAK]
-                EXPORT GPIO7_IRQHandler         [WEAK]
-                EXPORT GINT0_IRQHandler         [WEAK]
-                EXPORT GINT1_IRQHandler         [WEAK]
-                EXPORT EVRT_IRQHandler          [WEAK]
-                EXPORT CAN1_IRQHandler          [WEAK]
-                EXPORT VADC_IRQHandler          [WEAK]
-                EXPORT ATIMER_IRQHandler        [WEAK]
-                EXPORT RTC_IRQHandler           [WEAK]
-                EXPORT WDT_IRQHandler           [WEAK]
-                EXPORT CAN0_IRQHandler          [WEAK]
-                EXPORT QEI_IRQHandler           [WEAK]
-
-DAC_IRQHandler
-MX_CORE_IRQHandler
-DMA_IRQHandler
-FLASHEEPROM_IRQHandler
-ETH_IRQHandler
-SDIO_IRQHandler
-LCD_IRQHandler
-USB0_IRQHandler
-USB1_IRQHandler
-SCT_IRQHandler
-RIT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-MCPWM_IRQHandler
-ADC0_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI_IRQHandler
-ADC1_IRQHandler
-SSP0_IRQHandler
-SSP1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-I2S0_IRQHandler
-I2S1_IRQHandler
-SPIFI_IRQHandler
-SGPIO_IRQHandler
-GPIO0_IRQHandler
-GPIO1_IRQHandler
-GPIO2_IRQHandler
-GPIO3_IRQHandler
-GPIO4_IRQHandler
-GPIO5_IRQHandler
-GPIO6_IRQHandler
-GPIO7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-EVRT_IRQHandler
-CAN1_IRQHandler
-VADC_IRQHandler
-ATIMER_IRQHandler
-RTC_IRQHandler
-WDT_IRQHandler
-CAN0_IRQHandler
-QEI_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-                END
-
diff --git a/bsp/xplorer4330/m4/Internal SRAM.ini b/bsp/xplorer4330/m4/Internal SRAM.ini
deleted file mode 100644
index 34b8613392..0000000000
--- a/bsp/xplorer4330/m4/Internal SRAM.ini	
+++ /dev/null
@@ -1,10 +0,0 @@
-
-FUNC void Setup (unsigned int region) {
-  region &= 0xFFFF0000;
-  SP = _RDWORD(region);                          // Setup Stack Pointer
-  PC = _RDWORD(region + 4);                          // Setup Program Counter
-  _WDWORD(0xE000ED08, region);                   // Setup Vector Table Offset Register
-}
-
-LOAD "build\\project.axf" INCREMENTAL
-Setup(__scatterload); // Get ready to execute image in SRAM or whatever region it is in g,main
diff --git a/bsp/xplorer4330/m4/SConscript b/bsp/xplorer4330/m4/SConscript
index e8d5aac16d..e2c31c0755 100644
--- a/bsp/xplorer4330/m4/SConscript
+++ b/bsp/xplorer4330/m4/SConscript
@@ -5,7 +5,7 @@ objs = []
 list = os.listdir(os.path.join(cwd, '..'))
 
 for d in list:
-    if d!='m4':
+    if (d != 'M4' and d != 'M0'):
         path = os.path.join(cwd, '..', d)
         if os.path.isfile(os.path.join(path, 'SConscript')):
             objs = objs + SConscript(os.path.join(path, 'SConscript'))
diff --git a/bsp/xplorer4330/m4/SConstruct b/bsp/xplorer4330/m4/SConstruct
index 1554677f62..f6f21f4ec4 100644
--- a/bsp/xplorer4330/m4/SConstruct
+++ b/bsp/xplorer4330/m4/SConstruct
@@ -5,30 +5,25 @@ import rtconfig
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+    RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
 
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 
-if rtconfig.PLATFORM == 'iar':
-	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
-	env.Replace(ARFLAGS = [''])
-	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
-
 Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-# make a building
+# do building 
 DoBuilding(TARGET, objs)
diff --git a/bsp/xplorer4330/m4/SPIFI 32MB Debug.ini b/bsp/xplorer4330/m4/SPIFI 32MB Debug.ini
deleted file mode 100644
index 34b8613392..0000000000
--- a/bsp/xplorer4330/m4/SPIFI 32MB Debug.ini	
+++ /dev/null
@@ -1,10 +0,0 @@
-
-FUNC void Setup (unsigned int region) {
-  region &= 0xFFFF0000;
-  SP = _RDWORD(region);                          // Setup Stack Pointer
-  PC = _RDWORD(region + 4);                          // Setup Program Counter
-  _WDWORD(0xE000ED08, region);                   // Setup Vector Table Offset Register
-}
-
-LOAD "build\\project.axf" INCREMENTAL
-Setup(__scatterload); // Get ready to execute image in SRAM or whatever region it is in g,main
diff --git a/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.ld b/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.ld
deleted file mode 100644
index 08dc8f958e..0000000000
--- a/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.ld
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * linker script for LPC4330 (32MB SPI Flash, 264kB SRAM ) with GNU ld
- * lgnq 2012-12-12
- */
-
-/* Program Entry, set to mark it as "used" and avoid gc */
-MEMORY
-{
-    CODE (rx) : ORIGIN = 0x14000000, LENGTH = 0x00100000
-    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00020000
-}
-ENTRY(Reset_Handler)
-_system_stack_size = 0x200;
-
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        KEEP(*(.interrupt_vector))      /* Startup code */
-        . = ALIGN(4);
-        *(.text)                        /* remaining code */
-        *(.text.*)                      /* remaining code */
-        *(.rodata)                      /* read-only data (constants) */
-        *(.rodata*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.gnu.linkonce.t*)
-
-        /* section information for finsh shell */
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(4);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(4);
-
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-        . = ALIGN(4);
-
-        . = ALIGN(4);
-        _etext = .;
-    } > CODE = 0
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-
-        /* This is used by the startup in order to initialize the .data secion */
-        _sidata = .;
-    } > CODE
-    __exidx_end = .;
-
-    /* .data section which is used for initialized data */
-
-    .data : AT (_sidata)
-    {
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .data secion */
-        _sdata = . ;
-
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d*)
-
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .data secion */
-        _edata = . ;
-    } >DATA
-
-    .stack : 
-    {
-        . = . + _system_stack_size;
-        . = ALIGN(4);
-        _estack = .;
-    } >DATA
-
-    __bss_start = .;
-    .bss :
-    {
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .bss secion */
-        _sbss = .;
-
-        *(.bss)
-        *(.bss.*)
-        *(COMMON)
-
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .bss secion */
-        _ebss = . ;        
-        *(.bss.init)
-    } > DATA
-    __bss_end = .;
-
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
diff --git a/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.sct b/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.sct
deleted file mode 100644
index 079d63c6e9..0000000000
--- a/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.sct
+++ /dev/null
@@ -1,15 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x14000000 0x00100000  {    ; load region size_region
-  ER_IROM1 0x14000000 0x00100000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x10000000 0x00020000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-}
-
diff --git a/bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct b/bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct
deleted file mode 100644
index 973b81ba93..0000000000
--- a/bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct
+++ /dev/null
@@ -1,15 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x10000000 0x00018000  {    ; load region size_region
-  ER_IROM1 0x10000000 0x00018000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x10080000 0x0000A000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-}
-
diff --git a/bsp/xplorer4330/m4/project.uvopt b/bsp/xplorer4330/m4/project.uvopt
index 180e0a923b..62355f0810 100644
--- a/bsp/xplorer4330/m4/project.uvopt
+++ b/bsp/xplorer4330/m4/project.uvopt
@@ -21,13 +21,13 @@
   </DaveTm>
 
   <Target>
-    <TargetName>project</TargetName>
+    <TargetName>LPC4330 SPIFI</TargetName>
     <ToolsetNumber>0x4</ToolsetNumber>
     <ToolsetName>ARM-ADS</ToolsetName>
     <TargetOption>
       <CLKADS>12000000</CLKADS>
       <OPTTT>
-        <gFlags>0</gFlags>
+        <gFlags>1</gFlags>
         <BeepAtEnd>1</BeepAtEnd>
         <RunSim>1</RunSim>
         <RunTarget>0</RunTarget>
@@ -43,7 +43,170 @@
         <PageWidth>79</PageWidth>
         <PageLength>66</PageLength>
         <TabStop>8</TabStop>
-        <ListingPath>.\</ListingPath>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC43xx\UM10503.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC43xx\LPC4350_30_20_10.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O975 -O783 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC8000 -FN1 -FF0LPC18xx43xx_S25FL032 -FS014000000 -FL0400000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC4330 RAM</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
       </OPTLEX>
       <ListingPage>
         <CreateCListing>1</CreateCListing>
@@ -73,9 +236,31 @@
       <OPTFL>
         <tvExp>0</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
+        <IsCurrentTarget>0</IsCurrentTarget>
       </OPTFL>
       <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\NXP\LPC43xx\UM10503.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\NXP\LPC43xx\LPC4350_30_20_10.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
       <DllOpt>
         <SimDllName>SARMCM3.DLL</SimDllName>
         <SimDllArguments>-MPU</SimDllArguments>
@@ -96,11 +281,11 @@
         <sRmem>1</sRmem>
         <sRfunc>1</sRfunc>
         <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
+        <tLdApp>0</tLdApp>
         <tGomain>0</tGomain>
         <tRbreak>1</tRbreak>
         <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
+        <tRmem>0</tRmem>
         <tRfunc>0</tRfunc>
         <tRbox>1</tRbox>
         <tRtrace>0</tRtrace>
@@ -116,10 +301,20 @@
         <tDllPa></tDllPa>
         <tDlgDll></tDlgDll>
         <tDlgPa></tDlgPa>
-        <tIfile>.\SPIFI 32MB Debug.ini</tIfile>
+        <tIfile>.\Dbg_RAM.ini</tIfile>
         <pMon>BIN\UL2CM3.DLL</pMon>
       </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O783 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 </Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
       <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
       <DebugFlag>
         <trace>0</trace>
         <periodic>0</periodic>
@@ -146,16 +341,13 @@
         <newCpu>0</newCpu>
         <uProt>0</uProt>
       </DebugFlag>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
       <LintExecutable></LintExecutable>
       <LintConfigFile></LintConfigFile>
     </TargetOption>
   </Target>
 
   <Group>
-    <GroupName>applications</GroupName>
+    <GroupName>Applications</GroupName>
     <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
@@ -195,8 +387,8 @@
   </Group>
 
   <Group>
-    <GroupName>drivers</GroupName>
-    <tvExp>0</tvExp>
+    <GroupName>Drivers</GroupName>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
@@ -211,8 +403,8 @@
       <TopLine>0</TopLine>
       <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\drivers\platform.c</PathWithFileName>
-      <FilenameWithoutPath>platform.c</FilenameWithoutPath>
+      <PathWithFileName>..\drivers\board.c</PathWithFileName>
+      <FilenameWithoutPath>board.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -227,35 +419,35 @@
       <TopLine>0</TopLine>
       <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\drivers\usart.c</PathWithFileName>
-      <FilenameWithoutPath>usart.c</FilenameWithoutPath>
+      <PathWithFileName>..\drivers\drv_led.c</PathWithFileName>
+      <FilenameWithoutPath>drv_led.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>14</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>86</TopLine>
+      <CurrentLine>87</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\drivers\drv_uart.c</PathWithFileName>
+      <FilenameWithoutPath>drv_uart.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
   </Group>
 
   <Group>
-    <GroupName>lpc_board</GroupName>
+    <GroupName>CMSIS</GroupName>
     <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>3</GroupNumber>
-      <FileNumber>5</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <Focus>0</Focus>
-      <ColumnNumber>0</ColumnNumber>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>0</TopLine>
-      <CurrentLine>0</CurrentLine>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\board_ngx_xplorer_18304330.c</PathWithFileName>
-      <FilenameWithoutPath>board_ngx_xplorer_18304330.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
     <File>
       <GroupNumber>3</GroupNumber>
       <FileNumber>6</FileNumber>
@@ -267,662 +459,14 @@
       <TopLine>0</TopLine>
       <CurrentLine>0</CurrentLine>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\sysinit_ngx_xplorer_18304330.c</PathWithFileName>
-      <FilenameWithoutPath>sysinit_ngx_xplorer_18304330.c</FilenameWithoutPath>
+      <PathWithFileName>..\Libraries\Device\NXP\LPC43xx\Source\Templates\system_LPC43xx.c</PathWithFileName>
+      <FilenameWithoutPath>system_LPC43xx.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
-  </Group>
-
-  <Group>
-    <GroupName>lpc_chip</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
     <File>
-      <GroupNumber>4</GroupNumber>
+      <GroupNumber>3</GroupNumber>
       <FileNumber>7</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <Focus>0</Focus>
-      <ColumnNumber>0</ColumnNumber>
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+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\finsh_error.c</PathWithFileName>
+      <FilenameWithoutPath>finsh_error.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
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+      <PathWithFileName>..\..\..\components\finsh\finsh_heap.c</PathWithFileName>
+      <FilenameWithoutPath>finsh_heap.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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+      <GroupNumber>7</GroupNumber>
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+      <FilenameWithoutPath>finsh_init.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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+      <PathWithFileName>..\..\..\components\finsh\finsh_node.c</PathWithFileName>
+      <FilenameWithoutPath>finsh_node.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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+      <FilenameWithoutPath>finsh_ops.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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diff --git a/bsp/xplorer4330/m4/project.uvproj b/bsp/xplorer4330/m4/project.uvproj
index 95bd903e25..43e0857a48 100644
--- a/bsp/xplorer4330/m4/project.uvproj
+++ b/bsp/xplorer4330/m4/project.uvproj
@@ -7,7 +7,7 @@
 
   <Targets>
     <Target>
-      <TargetName>project</TargetName>
+      <TargetName>LPC4330 SPIFI</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
@@ -44,13 +44,13 @@
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
           <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>project</OutputName>
+          <OutputName>rtthread_lpc43xx</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
           <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\</ListingPath>
+          <ListingPath>.\build\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -73,9 +73,9 @@
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
           </BeforeMake>
           <AfterMake>
-            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>fromelf --bin -o "$L@L.bin" "$L@L.axf"</UserProg1Name>
+            <UserProg1Name></UserProg1Name>
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
@@ -130,10 +130,10 @@
           <Target>
             <UseTarget>1</UseTarget>
             <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>0</RunToMain>
+            <RunToMain>1</RunToMain>
             <RestoreBreakpoints>1</RestoreBreakpoints>
             <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
             <RestoreFunctions>0</RestoreFunctions>
             <RestoreToolbox>1</RestoreToolbox>
             <RestoreTracepoints>0</RestoreTracepoints>
@@ -152,7 +152,7 @@
             <CpuDllArguments></CpuDllArguments>
             <PeripheralDll></PeripheralDll>
             <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile>.\SPIFI 32MB Debug.ini</InitializationFile>
+            <InitializationFile></InitializationFile>
             <Driver>BIN\UL2CM3.DLL</Driver>
           </TargetDlls>
         </DebugOption>
@@ -165,6 +165,7 @@
             <Capability>1</Capability>
             <DriverSelection>4096</DriverSelection>
           </Flash1>
+          <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
           <Flash3>"" ()</Flash3>
           <Flash4></Flash4>
@@ -196,7 +197,7 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M4"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
@@ -207,10 +208,10 @@
             <hadIRAM>1</hadIRAM>
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
-            <RvdsVP>1</RvdsVP>
+            <RvdsVP>2</RvdsVP>
             <hadIRAM2>1</hadIRAM2>
             <hadIROM2>0</hadIROM2>
-            <StupSel>0</StupSel>
+            <StupSel>1</StupSel>
             <useUlib>1</useUlib>
             <EndSel>0</EndSel>
             <uLtcg>0</uLtcg>
@@ -223,7 +224,7 @@
             <NoZi3>0</NoZi3>
             <NoZi4>0</NoZi4>
             <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
+            <Ro1Chk>1</Ro1Chk>
             <Ro2Chk>0</Ro2Chk>
             <Ro3Chk>0</Ro3Chk>
             <Ir1Chk>0</Ir1Chk>
@@ -270,9 +271,9 @@
                 <Size>0x20000</Size>
               </IRAM>
               <IROM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -281,8 +282,8 @@
               </XRAM>
               <OCR_RVCT1>
                 <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
+                <StartAddress>0x14000000</StartAddress>
+                <Size>0x400000</Size>
               </OCR_RVCT1>
               <OCR_RVCT2>
                 <Type>1</Type>
@@ -348,9 +349,9 @@
             <uSurpInc>0</uSurpInc>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>CORE_M4</Define>
+              <Define>CORE_M4 USE_SPIFI</Define>
               <Undefine></Undefine>
-              <IncludePath>.;..\..\..\components\CMSIS\Include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\init;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\applications;..\drivers;..\libraries\lpc_board\board_common;..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330;..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\ngx_xplorer_4330;..\libraries\lpc_chip\chip_18xx_43xx;..\libraries\lpc_chip\chip_common;..\libraries\lpc_ip</IncludePath>
+              <IncludePath>.;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\Libraries\CMSIS\Include;..\Libraries\Device\NXP\LPC43xx\Include;..\drivers;applications</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -370,15 +371,15 @@
             </VariousControls>
           </Aads>
           <LDads>
-            <umfTarg>0</umfTarg>
+            <umfTarg>1</umfTarg>
             <Ropi>0</Ropi>
             <Rwpi>0</Rwpi>
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
+            <TextAddressRange>0x14000000</TextAddressRange>
             <DataAddressRange>0x10000000</DataAddressRange>
-            <ScatterFile>.\lpc4330_xplorer_spifi32mb.sct</ScatterFile>
+            <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc> --keep __fsym_* --keep __vsym_* </Misc>
@@ -389,7 +390,7 @@
       </TargetOption>
       <Groups>
         <Group>
-          <GroupName>applications</GroupName>
+          <GroupName>Applications</GroupName>
           <Files>
             <File>
               <FileName>application.c</FileName>
@@ -404,247 +405,37 @@
           </Files>
         </Group>
         <Group>
-          <GroupName>drivers</GroupName>
+          <GroupName>Drivers</GroupName>
           <Files>
             <File>
-              <FileName>platform.c</FileName>
+              <FileName>board.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\drivers\platform.c</FilePath>
+              <FilePath>..\drivers\board.c</FilePath>
             </File>
             <File>
-              <FileName>usart.c</FileName>
+              <FileName>drv_led.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\drivers\usart.c</FilePath>
+              <FilePath>..\drivers\drv_led.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\drivers\drv_uart.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>lpc_board</GroupName>
+          <GroupName>CMSIS</GroupName>
           <Files>
             <File>
-              <FileName>board_ngx_xplorer_18304330.c</FileName>
+              <FileName>system_LPC43xx.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\board_ngx_xplorer_18304330.c</FilePath>
+              <FilePath>..\Libraries\Device\NXP\LPC43xx\Source\Templates\system_LPC43xx.c</FilePath>
             </File>
             <File>
-              <FileName>sysinit_ngx_xplorer_18304330.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\sysinit_ngx_xplorer_18304330.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>lpc_chip</GroupName>
-          <Files>
-            <File>
-              <FileName>adc_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\adc_18xx_43xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>atimer_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\atimer_18xx_43xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>clock_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\clock_18xx_43xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>emc_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\emc_18xx_43xx.c</FilePath>
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-              <FileName>enet_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\enet_18xx_43xx.c</FilePath>
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-              <FileName>evrt_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\evrt_18xx_43xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>gpdma_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\gpdma_18xx_43xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>gpio_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\gpio_18xx_43xx.c</FilePath>
-            </File>
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-              <FileName>i2c_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\i2c_18xx_43xx.c</FilePath>
-            </File>
-            <File>
-              <FileName>i2s_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\i2s_18xx_43xx.c</FilePath>
-            </File>
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-              <FileName>lcd_18xx_43xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\lcd_18xx_43xx.c</FilePath>
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-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\rgu_18xx_43xx.c</FilePath>
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-              <FilePath>..\libraries\lpc_chip\chip_18xx_43xx\rtc_18xx_43xx.c</FilePath>
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-          <GroupName>startup</GroupName>
-          <Files>
-            <File>
-              <FileName>keil_startup_lpc18xx43xx.s</FileName>
+              <FileName>startup_LPC43xx.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\libraries\startup_code\keil_startup_lpc18xx43xx.s</FilePath>
+              <FilePath>..\Libraries\Device\NXP\LPC43xx\Source\Templates\ARM\startup_LPC43xx.s</FilePath>
             </File>
           </Files>
         </Group>
@@ -771,16 +562,36 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
             </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\portal.c</FilePath>
+            </File>
             <File>
               <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
             </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
           <GroupName>finsh</GroupName>
           <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\symbol.c</FilePath>
+            </File>
             <File>
               <FileName>cmd.c</FileName>
               <FileType>1</FileType>
@@ -821,11 +632,651 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\finsh_parser.c</FilePath>
             </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
             <File>
               <FileName>finsh_token.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\finsh_token.c</FilePath>
             </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>LPC4330 RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4330</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x1001FFFF) IRAM2(0x20000000-0x2000FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O975 -S0 -C0)</FlashDriverDll>
+          <DeviceId>6193</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Dbg_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>1</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x10000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\applications\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\applications\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\drivers\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\drivers\drv_led.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\drivers\drv_uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_LPC43xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\Device\NXP\LPC43xx\Source\Templates\system_LPC43xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_LPC43xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\Libraries\Device\NXP\LPC43xx\Source\Templates\ARM\startup_LPC43xx.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>memheap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\memheap.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M4</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\symbol.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
             <File>
               <FileName>finsh_var.c</FileName>
               <FileType>1</FileType>
@@ -837,24 +1288,9 @@
               <FilePath>..\..\..\components\finsh\finsh_vm.c</FilePath>
             </File>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>finsh_token.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
-            </File>
-            <File>
-              <FileName>symbol.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\symbol.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Components</GroupName>
-          <Files>
-            <File>
-              <FileName>components.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\init\components.c</FilePath>
+              <FilePath>..\..\..\components\finsh\finsh_token.c</FilePath>
             </File>
           </Files>
         </Group>
diff --git a/bsp/xplorer4330/m4/rtconfig.h b/bsp/xplorer4330/m4/rtconfig.h
index c2db206a3f..84fc28028c 100644
--- a/bsp/xplorer4330/m4/rtconfig.h
+++ b/bsp/xplorer4330/m4/rtconfig.h
@@ -1,22 +1,29 @@
+/* RT-Thread config file */
 #ifndef __RTTHREAD_CFG_H__
 #define __RTTHREAD_CFG_H__
 
 // <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
 
 // <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 // <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 // <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
 // <item description="8">8</item>
 // <item description="32">32</item>
 // <item description="256">256</item>
 // </integer>
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 // <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE  512
+// <bool name="RT_USING_MODULE" description="Using Application Module" default="true" />
+//#define RT_USING_MODULE
 // <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
 #define RT_DEBUG
+// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
+#define RT_DEBUG_INIT   0
 // <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
 // #define RT_THREAD_DEBUG
 // <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
@@ -25,15 +32,14 @@
 
 // <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
 #define RT_USING_HOOK
-
 // <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
-// #define RT_USING_TIMER_SOFT
+#define RT_USING_TIMER_SOFT
 // <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO	4
+#define RT_TIMER_THREAD_PRIO    4
 // <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_TICK_PER_SECOND    100
 // </section>
 
 // <section name="IPC" description="Inter-Thread communication" default="always" >
@@ -68,27 +74,32 @@
 #define RT_USING_DEVICE_IPC
 // <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
 #define RT_USING_SERIAL
-
-// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
-#define RT_USING_UART0
-
-// <bool name="RT_USING_UART3" description="Using UART3" default="true" />
-// #define RT_USING_UART3
 // <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE	64
-// </section>
-
+#define RT_UART_RX_BUFFER_SIZE    256
+// <bool name="RT_USING_MTD_NAND" description="Using MTD NAND Framework" default="true" />
+//#define RT_USING_MTD_NAND
+// <bool name="RT_MTD_NAND_DEBUG" description="Enable MTD NAND Framework Debug" default="true" />
+//#define RT_MTD_NAND_DEBUG
+// <bool name="RT_USING_NFTL" description="Using NFTL layer" default="true" />
+//#define RT_USING_NFTL
+// <bool name="RT_USING_SPI" description="Using SPI Device Driver Framework" default="true" />
+//#define RT_USING_SPI
+// <bool name="RT_USING_I2C" description="Using I2C Device Driver Framework" default="true" />
+//#define RT_USING_I2C
+// <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" />
+//#define RT_USING_RTC
+// <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" />
+#define RT_MMCSD_THREAD_PREORITY    15
 // <section name="RT_USING_CONSOLE" description="Using console" default="true" >
 #define RT_USING_CONSOLE
 // <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
-#define RT_CONSOLE_DEVICE_NAME	"uart0"
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
 // </section>
 
 // <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-#define RT_USING_COMPONENTS_INIT
-
+//#define RT_USING_COMPONENTS_INIT
 // <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
 #define RT_USING_FINSH
 // <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
@@ -96,47 +107,68 @@
 // <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
 #define FINSH_USING_DESCRIPTION
 // <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE	4096
+#define FINSH_THREAD_STACK_SIZE 4096
+// <bool name="FINSH_USING_MSH" description="Using module shell in finsh" default="true" />
+//#define FINSH_USING_MSH
 // </section>
 
 // <section name="LIBC" description="C Runtime library setting" default="always" >
 // <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
 // #define RT_USING_NEWLIB
 // <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-// #define RT_USING_PTHREADS
+//#define RT_USING_PTHREADS
 // </section>
 
 // <section name="RT_USING_DFS" description="Device file system" default="true" >
-// #define RT_USING_DFS
+//#define RT_USING_DFS
 // <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
-// #define DFS_USING_WORKDIR
+//#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
+#define DFS_FILESYSTEM_TYPES_MAX  4
 // <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX	2
+#define DFS_FILESYSTEMS_MAX 4
 // <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX	4
+#define DFS_FD_MAX           16
 // <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
 #define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" />
+#define RT_DFS_ELM_DRIVES    4
+// <bool name="RT_DFS_ELM_REENTRANT" description="Support reentrant" default="true" />
+#define RT_DFS_ELM_REENTRANT
 // <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
-// <item description="LFN1">1</item>
-// <item description="LFN1">2</item>
+// <item description="LFN with static LFN working buffer">1</item>
+// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
+// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
 // </integer>
-#define RT_DFS_ELM_USE_LFN	1
+#define RT_DFS_ELM_USE_LFN  3
+// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
+#define RT_DFS_ELM_CODE_PAGE    936
+// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
+#define RT_DFS_ELM_CODE_PAGE_FILE
 // <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
-#define RT_DFS_ELM_MAX_LFN	64
+#define RT_DFS_ELM_MAX_LFN  256
+// <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" />
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  4096
+// <bool name="RT_DFS_ELM_USE_ERASE" description="Enable erase feature for flash" default="true" />
+#define RT_DFS_ELM_USE_ERASE
 // <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
 // #define RT_USING_DFS_YAFFS2
 // <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
 // #define RT_USING_DFS_UFFS
 // <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
-// #define RT_USING_DFS_DEVFS
-// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
-// #define RT_USING_DFS_NFS
-// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_ROMFS" description="Using ROMFS" default="false" />
+//#define RT_USING_DFS_ROMFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS" default="false" />
+//#define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="The exported NFS host path" default="192.168.1.10:/" />
+#define RT_NFS_HOST_EXPORT  "192.168.1.20:/"
 // </section>
 
 // <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
-// #define RT_USING_LWIP
+//#define RT_USING_LWIP
+// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
+#define RT_USING_LWIP141
 // <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
 #define RT_LWIP_ICMP
 // <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
@@ -148,31 +180,31 @@
 // <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
 #define RT_LWIP_DNS
 // <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
-#define RT_LWIP_PBUF_NUM	4
+#define RT_LWIP_PBUF_NUM    4
 // <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
-#define RT_LWIP_TCP_PCB_NUM	3
+#define RT_LWIP_TCP_PCB_NUM 3
 // <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
-#define RT_LWIP_TCP_SND_BUF	2048
+#define RT_LWIP_TCP_SND_BUF 4086
 // <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
-#define RT_LWIP_TCP_WND	2048
+#define RT_LWIP_TCP_WND 2048
 // <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
 // #define RT_LWIP_SNMP
 // <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
 // #define RT_LWIP_DHCP
 // <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
-#define RT_LWIP_TCP_SEG_NUM	4
+#define RT_LWIP_TCP_SEG_NUM 8
 // <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
 // <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 // <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 // <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
 // <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 // <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
 // <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
 #define RT_LWIP_IPADDR0 192
 #define RT_LWIP_IPADDR1 168
@@ -190,13 +222,9 @@
 #define RT_LWIP_MSKADDR3 0
 // </section>
 
-// <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
-// #define RT_USING_CMSIS_OS
-// <bool name="RT_USING_RTT_CMSIS" description="Using CMSIS in RTT" default="true" />
-#define RT_USING_RTT_CMSIS
-// <bool name="RT_USING_BSP_CMSIS" description="Using CMSIS in BSP" default="true" />
-// #define RT_USING_BSP_CMSIS
+
 
 // </RDTConfigurator>
 
+
 #endif
diff --git a/bsp/xplorer4330/m4/rtconfig.py b/bsp/xplorer4330/m4/rtconfig.py
index 0b61eda451..d8c21c1dc8 100644
--- a/bsp/xplorer4330/m4/rtconfig.py
+++ b/bsp/xplorer4330/m4/rtconfig.py
@@ -1,38 +1,41 @@
 import os
 
+# core to be use
+#USE_CORE = 'CORE_M0'
+USE_CORE = 'CORE_M4'
+
 # toolchains options
 ARCH='arm'
-CPU='cortex-m4'
+
+if USE_CORE == 'CORE_M4':
+    CPU = 'cortex-m4'
+else:
+    CPU = 'cortex-m0'
+
 CROSS_TOOL='keil'
 
+
+# get setting from environment.
 if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
+        CROSS_TOOL = os.getenv('RTT_CC')
 
 # cross_tool provides the cross compiler
 # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
 if  CROSS_TOOL == 'gcc':
-	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= r'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
+    PLATFORM = 'gcc'
+    EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
 elif CROSS_TOOL == 'keil':
-	PLATFORM 	= 'armcc'
-	EXEC_PATH 	= r'C:/Keil'
+    PLATFORM = 'armcc'
+    EXEC_PATH = r'D:/Keil'
 elif CROSS_TOOL == 'iar':
-    print '================ERROR============================'
-    print 'Not support iar yet!'
-    print '================================================='
-    exit(0)
+    PLATFORM = 'iar'
+    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
 
 if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
 
-BUILD = 'debug'
-
-LPC43xx_BOARD = 'NGX_XPLORER_4330'
-#LPC43xx_BOARD = 'NGX_XPLORER_1830'
-#LPC43xx_BOARD = 'KEIL_MCB_4357'
-#LPC43xx_BOARD = 'KEIL_MCB_1857'
-#LPC43xx_BOARD = 'HITEX_EVA_4350'
-#LPC43xx_BOARD = 'HITEX_EVA_1850'
+#
+BUILD = 'release'
 
 if PLATFORM == 'gcc':
     # toolchains
@@ -41,15 +44,16 @@ if PLATFORM == 'gcc':
     AS = PREFIX + 'gcc'
     AR = PREFIX + 'ar'
     LINK = PREFIX + 'gcc'
-    TARGET_EXT = 'axf'
+    TARGET_EXT = 'elf'
     SIZE = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
-
-    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    if USE_CORE == 'CORE_M4':
+        DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
     CFLAGS = DEVICE 
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc4330.map,-cref,-u,Reset_Handler -T lpc4330_xplorer_spifi32mb.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
 
     CPATH = ''
     LPATH = ''
@@ -70,15 +74,15 @@ elif PLATFORM == 'armcc':
     LINK = 'armlink'
     TARGET_EXT = 'axf'
 
-    DEVICE = ' --cpu Cortex-M4'
+    DEVICE = ' --device DARMSTM'
     CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE + ' --apcs=interwork'
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter lpc4330_xplorer_sram.sct'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
 
-#    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-#    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
 
-    EXEC_PATH += '/ARM/ARMCC/bin'
+    EXEC_PATH += '/arm/bin40/'
 
     if BUILD == 'debug':
         CFLAGS += ' -g -O0'
@@ -96,10 +100,7 @@ elif PLATFORM == 'iar':
     LINK = 'ilinkarm'
     TARGET_EXT = 'out'
 
-    DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
-
-    CFLAGS = DEVICE
-    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS = ' --diag_suppress Pa050'
     CFLAGS += ' --no_cse' 
     CFLAGS += ' --no_unroll' 
     CFLAGS += ' --no_inline' 
@@ -109,9 +110,12 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --no_scheduling' 
     CFLAGS += ' --debug' 
     CFLAGS += ' --endian=little' 
-    CFLAGS += ' --cpu=Cortex-M4' 
+    if USE_CORE == 'CORE_M4':
+        CFLAGS += ' --cpu=Cortex-M4' 
+        CFLAGS += ' --fpu=None'
+    else:
+        CFLAGS += ' --cpu=Cortex-M0'
     CFLAGS += ' -e' 
-    CFLAGS += ' --fpu=None'
     CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
@@ -120,10 +124,13 @@ elif PLATFORM == 'iar':
     AFLAGS += ' -s+' 
     AFLAGS += ' -w+' 
     AFLAGS += ' -r' 
-    AFLAGS += ' --cpu Cortex-M4' 
-    AFLAGS += ' --fpu None' 
+    if USE_CORE == 'CORE_M4':
+        AFLAGS += ' --cpu Cortex-M4' 
+        AFLAGS += ' --fpu None' 
+    else:
+        AFLAGS += ' --cpu Cortex-M0' 
 
-    LFLAGS = ' --config stm32f10x_flash.icf'
+    LFLAGS = ' --config lpc43xx_flash.icf'
     LFLAGS += ' --redirect _Printf=_PrintfTiny' 
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
diff --git a/bsp/xplorer4330/m4/template.uvproj b/bsp/xplorer4330/m4/template.uvproj
index b55a288d4c..a5b77a6a0c 100644
--- a/bsp/xplorer4330/m4/template.uvproj
+++ b/bsp/xplorer4330/m4/template.uvproj
@@ -7,7 +7,7 @@
 
   <Targets>
     <Target>
-      <TargetName>project</TargetName>
+      <TargetName>LPC4330 SPIFI</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
@@ -44,13 +44,13 @@
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
           <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>project</OutputName>
+          <OutputName>rtthread_lpc43xx</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
           <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\</ListingPath>
+          <ListingPath>.\build\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -73,9 +73,9 @@
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
           </BeforeMake>
           <AfterMake>
-            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>fromelf --bin -o "$L@L.bin" "$L@L.axf"</UserProg1Name>
+            <UserProg1Name></UserProg1Name>
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
@@ -130,10 +130,10 @@
           <Target>
             <UseTarget>1</UseTarget>
             <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>0</RunToMain>
+            <RunToMain>1</RunToMain>
             <RestoreBreakpoints>1</RestoreBreakpoints>
             <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
             <RestoreFunctions>0</RestoreFunctions>
             <RestoreToolbox>1</RestoreToolbox>
             <RestoreTracepoints>0</RestoreTracepoints>
@@ -152,7 +152,7 @@
             <CpuDllArguments></CpuDllArguments>
             <PeripheralDll></PeripheralDll>
             <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile>.\SPIFI 32MB Debug.ini</InitializationFile>
+            <InitializationFile></InitializationFile>
             <Driver>BIN\UL2CM3.DLL</Driver>
           </TargetDlls>
         </DebugOption>
@@ -165,6 +165,7 @@
             <Capability>1</Capability>
             <DriverSelection>4096</DriverSelection>
           </Flash1>
+          <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
           <Flash3>"" ()</Flash3>
           <Flash4></Flash4>
@@ -196,7 +197,7 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M4"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
@@ -207,10 +208,10 @@
             <hadIRAM>1</hadIRAM>
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
-            <RvdsVP>1</RvdsVP>
+            <RvdsVP>2</RvdsVP>
             <hadIRAM2>1</hadIRAM2>
             <hadIROM2>0</hadIROM2>
-            <StupSel>0</StupSel>
+            <StupSel>1</StupSel>
             <useUlib>1</useUlib>
             <EndSel>0</EndSel>
             <uLtcg>0</uLtcg>
@@ -223,7 +224,7 @@
             <NoZi3>0</NoZi3>
             <NoZi4>0</NoZi4>
             <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
+            <Ro1Chk>1</Ro1Chk>
             <Ro2Chk>0</Ro2Chk>
             <Ro3Chk>0</Ro3Chk>
             <Ir1Chk>0</Ir1Chk>
@@ -270,9 +271,392 @@
                 <Size>0x20000</Size>
               </IRAM>
               <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
                 <Type>0</Type>
                 <StartAddress>0x0</StartAddress>
                 <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x14000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x14000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+    <Target>
+      <TargetName>LPC4330 RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC4330</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000-0x1001FFFF) IRAM2(0x20000000-0x2000FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O975 -S0 -C0)</FlashDriverDll>
+          <DeviceId>6193</DeviceId>
+          <RegisterFile>LPC43xx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
+          <DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread_lpc43xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Dbg_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>1</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -370,15 +754,15 @@
             </VariousControls>
           </Aads>
           <LDads>
-            <umfTarg>0</umfTarg>
+            <umfTarg>1</umfTarg>
             <Ropi>0</Ropi>
             <Rwpi>0</Rwpi>
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x10000000</DataAddressRange>
-            <ScatterFile>.\lpc4330_xplorer_spifi32mb.sct</ScatterFile>
+            <TextAddressRange>0x10000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc></Misc>

From 64a2902fa9d5a2cbf15873c1857c6909db13dd75 Mon Sep 17 00:00:00 2001
From: shaolin <qiuyiuestc@gmail.com>
Date: Sun, 13 Jul 2014 17:19:34 +0800
Subject: [PATCH 41/86] 1. Fix some spell error; 2. Fix data transfer size
 calculate error issue;

---
 .../drivers/include/drivers/usb_common.h      |  4 +-
 .../drivers/include/drivers/usb_device.h      |  6 +--
 .../drivers/usb/usbdevice/class/cdc_vcom.c    |  4 +-
 components/drivers/usb/usbdevice/core/core.c  | 47 ++++++++++++-------
 4 files changed, 36 insertions(+), 25 deletions(-)

diff --git a/components/drivers/include/drivers/usb_common.h b/components/drivers/include/drivers/usb_common.h
index cd6f0432f3..1e9cf3dc9f 100644
--- a/components/drivers/include/drivers/usb_common.h
+++ b/components/drivers/include/drivers/usb_common.h
@@ -373,7 +373,7 @@ struct uhid_descriptor
 };
 typedef struct uhid_descriptor* uhid_desc_t;
 
-struct ureqest
+struct urequest
 {
     rt_uint8_t request_type;
     rt_uint8_t request;
@@ -381,7 +381,7 @@ struct ureqest
     rt_uint16_t index;
     rt_uint16_t length;
 };
-typedef struct ureqest* ureq_t;
+typedef struct urequest* ureq_t;
 
 #ifndef MIN
 #define MIN(a, b) (a < b ? a : b)
diff --git a/components/drivers/include/drivers/usb_device.h b/components/drivers/include/drivers/usb_device.h
index 722251c82a..b104da6ab9 100644
--- a/components/drivers/include/drivers/usb_device.h
+++ b/components/drivers/include/drivers/usb_device.h
@@ -76,7 +76,7 @@ typedef enum
     /* request to read full count */
     UIO_REQUEST_READ_FULL,
     /* request to read any count */
-    UIO_REQUEST_READ_BEST,  
+    UIO_REQUEST_READ_MOST,  
     /* request to write full count */
     UIO_REQUEST_WRITE,
 }UIO_REQUEST_TYPE;
@@ -239,7 +239,7 @@ struct udev_msg
     union
     {
         struct ep_msg ep_msg;
-        struct ureqest setup;
+        struct urequest setup;
     } content;
 };
 typedef struct udev_msg* udev_msg_t;
@@ -292,7 +292,7 @@ rt_err_t rt_usbd_ep_set_stall(udevice_t device, uep_t ep);
 rt_err_t rt_usbd_ep_clear_stall(udevice_t device, uep_t ep);
 rt_err_t rt_usbd_ep0_set_stall(udevice_t device);
 rt_err_t rt_usbd_ep0_clear_stall(udevice_t device);
-rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct ureqest* setup);
+rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct urequest* setup);
 rt_err_t rt_usbd_ep0_in_handler(udcd_t dcd);
 rt_err_t rt_usbd_ep0_out_handler(udcd_t dcd, rt_size_t size);
 rt_err_t rt_usbd_ep_in_handler(udcd_t dcd, rt_uint8_t address);
diff --git a/components/drivers/usb/usbdevice/class/cdc_vcom.c b/components/drivers/usb/usbdevice/class/cdc_vcom.c
index 33f9f7abef..8916f3a084 100644
--- a/components/drivers/usb/usbdevice/class/cdc_vcom.c
+++ b/components/drivers/usb/usbdevice/class/cdc_vcom.c
@@ -280,7 +280,7 @@ static rt_err_t _ep_out_handler(ufunction_t func, rt_size_t size)
 
     data->ep_out->request.buffer = data->ep_out->buffer;
     data->ep_out->request.size = EP_MAXPACKET(data->ep_out);
-    data->ep_out->request.req_type = UIO_REQUEST_READ_BEST;    
+    data->ep_out->request.req_type = UIO_REQUEST_READ_MOST;    
     rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request);
 
     return RT_EOK;
@@ -435,7 +435,7 @@ static rt_err_t _function_enable(ufunction_t func)
     data->ep_out->request.buffer = data->ep_out->buffer;
     data->ep_out->request.size = EP_MAXPACKET(data->ep_out);
     
-    data->ep_out->request.req_type = UIO_REQUEST_READ_BEST;    
+    data->ep_out->request.req_type = UIO_REQUEST_READ_MOST;    
     rt_usbd_io_request(func->device, data->ep_out, &data->ep_out->request);
     
     return RT_EOK;
diff --git a/components/drivers/usb/usbdevice/core/core.c b/components/drivers/usb/usbdevice/core/core.c
index dadd81352b..b845b27c4c 100644
--- a/components/drivers/usb/usbdevice/core/core.c
+++ b/components/drivers/usb/usbdevice/core/core.c
@@ -772,10 +772,18 @@ static rt_err_t _data_notify(udevice_t device, struct ep_msg* ep_msg)
             size = dcd_ep_read(device->dcd, EP_ADDRESS(ep),
                 ep->request.buffer);
         }
-        ep->request.remain_size -= size;
-        ep->request.buffer += size;
 
-        if(ep->request.req_type == UIO_REQUEST_READ_BEST)
+        if(size > ep->request.remain_size)
+        {
+            ep->request.remain_size = 0;
+        }
+        else
+        {
+            ep->request.remain_size -= size;
+            ep->request.buffer += size;
+        }
+
+        if(ep->request.req_type == UIO_REQUEST_READ_MOST)
         {
             EP_HANDLER(ep, func, size);
         }
@@ -881,6 +889,7 @@ static rt_err_t _stop_notify(udevice_t device)
 static rt_size_t rt_usbd_ep_write(udevice_t device, uep_t ep, void *buffer, rt_size_t size)
 {
     rt_uint16_t maxpacket;
+    rt_size_t sent_size;
         
     RT_ASSERT(device != RT_NULL);    
     RT_ASSERT(device->dcd != RT_NULL);
@@ -889,18 +898,18 @@ static rt_size_t rt_usbd_ep_write(udevice_t device, uep_t ep, void *buffer, rt_s
     maxpacket = EP_MAXPACKET(ep);
     if(ep->request.remain_size >= maxpacket)
     {
-        dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, maxpacket);
-        ep->request.remain_size -= maxpacket;
+        sent_size = dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, maxpacket);
+        ep->request.remain_size -= sent_size;
         ep->request.buffer += maxpacket;    
     }
     else
     {
-        dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, 
+        sent_size = dcd_ep_write(device->dcd, EP_ADDRESS(ep), ep->request.buffer, 
             ep->request.remain_size);
-        ep->request.remain_size = 0;
+        ep->request.remain_size -= sent_size;
     }
 
-    return size;
+    return sent_size;
 }
 
 static rt_size_t rt_usbd_ep_read_prepare(udevice_t device, uep_t ep, void *buffer, rt_size_t size)
@@ -1623,7 +1632,7 @@ rt_size_t rt_usbd_io_request(udevice_t device, uep_t ep, uio_request_t req)
     {
         switch(req->req_type)
         {
-        case UIO_REQUEST_READ_BEST:
+        case UIO_REQUEST_READ_MOST:
         case UIO_REQUEST_READ_FULL:
             ep->request.remain_size = ep->request.size;
             size = rt_usbd_ep_read_prepare(device, ep, req->buffer, req->size);
@@ -1757,7 +1766,8 @@ static rt_err_t rt_usbd_ep_assign(udevice_t device, uep_t ep)
     while(device->dcd->ep_pool[i].addr != 0xFF)
     {
         if(device->dcd->ep_pool[i].status == ID_UNASSIGNED && 
-            ep->ep_desc->bmAttributes == device->dcd->ep_pool[i].type)
+            ep->ep_desc->bmAttributes == device->dcd->ep_pool[i].type &&
+            ep->ep_desc->bEndpointAddress == device->dcd->ep_pool[i].dir)
         {
             EP_ADDRESS(ep) |= device->dcd->ep_pool[i].addr;
             ep->id = &device->dcd->ep_pool[i];
@@ -1786,7 +1796,7 @@ static rt_err_t rt_usbd_ep_unassign(udevice_t device, uep_t ep)
     return RT_EOK;
 }
 
-rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct ureqest* setup)
+rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct urequest* setup)
 {
     struct udev_msg msg;
     rt_size_t size;
@@ -1796,7 +1806,7 @@ rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct ureqest* setup)
     if(setup == RT_NULL)
     {
         size = dcd_ep_read(dcd, EP0_OUT_ADDR, (void*)&msg.content.setup);
-        if(size != sizeof(struct ureqest))
+        if(size != sizeof(struct urequest))
         {
             rt_kprintf("read setup packet error\n");
             return -RT_ERROR;
@@ -1804,7 +1814,7 @@ rt_err_t rt_usbd_ep0_setup_handler(udcd_t dcd, struct ureqest* setup)
     }
     else
     {
-        rt_memcpy((void*)&msg.content.setup, (void*)setup, sizeof(struct ureqest));
+        rt_memcpy((void*)&msg.content.setup, (void*)setup, sizeof(struct urequest));
     }    
     
     msg.type = USB_MSG_SETUP_NOTIFY;
@@ -1935,6 +1945,7 @@ rt_err_t rt_usbd_sof_handler(udcd_t dcd)
 rt_size_t rt_usbd_ep0_write(udevice_t device, void *buffer, rt_size_t size)
 {
     uep_t ep0;
+    rt_size_t sent_size = 0;
 
     RT_ASSERT(device != RT_NULL);    
     RT_ASSERT(device->dcd != RT_NULL);
@@ -1947,17 +1958,17 @@ rt_size_t rt_usbd_ep0_write(udevice_t device, void *buffer, rt_size_t size)
     ep0->request.remain_size = size;
     if(ep0->request.remain_size >= ep0->id->maxpacket)
     {
-        dcd_ep_write(device->dcd, EP0_IN_ADDR, ep0->request.buffer, ep0->id->maxpacket);
-        ep0->request.remain_size -= ep0->id->maxpacket;
+        sent_size = dcd_ep_write(device->dcd, EP0_IN_ADDR, ep0->request.buffer, ep0->id->maxpacket);
+        ep0->request.remain_size -= sent_size;
         ep0->request.buffer += ep0->id->maxpacket;
     }
     else
     {
-        dcd_ep_write(device->dcd, EP0_IN_ADDR, ep0->request.buffer, ep0->request.remain_size);
-        ep0->request.remain_size = 0;
+        sent_size = dcd_ep_write(device->dcd, EP0_IN_ADDR, ep0->request.buffer, ep0->request.remain_size);
+        ep0->request.remain_size -= sent_size;        
     }
 
-    return size;
+    return sent_size;
 }
 
 rt_size_t rt_usbd_ep0_read(udevice_t device, void *buffer, rt_size_t size, 

From ff1eb2cbc9b7bb146cae957d15cccfb67285d57e Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Sun, 13 Jul 2014 18:26:48 +0800
Subject: [PATCH 42/86] ymodem: refactor _rym_read_code

Make fast path fast and slow path slow.
---
 components/utilities/ymodem/ymodem.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/components/utilities/ymodem/ymodem.c b/components/utilities/ymodem/ymodem.c
index fdd1950cc0..f5ebeab832 100644
--- a/components/utilities/ymodem/ymodem.c
+++ b/components/utilities/ymodem/ymodem.c
@@ -70,18 +70,23 @@ static enum rym_code _rym_read_code(
         struct rym_ctx *ctx,
         rt_tick_t timeout)
 {
-    /* consume the available sem and read the data in buffer if possible */
-    while (rt_sem_trytake(&ctx->sem) == RT_EOK)
-        ;
+    /* Fast path */
     if (rt_device_read(ctx->dev, 0, ctx->buf, 1) == 1)
         return *ctx->buf;
-    /* no data yet, wait for one */
-    if (rt_sem_take(&ctx->sem, timeout) != RT_EOK)
-        return RYM_CODE_NONE;
-    /* read one */
-    if (rt_device_read(ctx->dev, 0, ctx->buf, 1) == 1)
-        return *ctx->buf;
-    return RYM_CODE_NONE;
+
+    /* Slow path */
+    do {
+        rt_size_t rsz;
+
+        /* No data yet, wait for one */
+        if (rt_sem_take(&ctx->sem, timeout) != RT_EOK)
+            return RYM_CODE_NONE;
+
+        /* Try to read one */
+        rsz = rt_device_read(ctx->dev, 0, ctx->buf, 1);
+        if (rsz == 1)
+            return *ctx->buf;
+    } while (1);
 }
 
 /* the caller should at least alloc _RYM_STX_PKG_SZ buffer */

From f3016434942758c439b2c3b34aa60e3a5c224b8e Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Tue, 15 Jul 2014 07:36:59 +0800
Subject: [PATCH 43/86] [bsp] Fix compiling issue for LPC43xx

---
 .../LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c   | 3 ++-
 bsp/xplorer4330/Libraries/Device/SConscript                   | 4 ++--
 bsp/xplorer4330/{libraries => Libraries}/SConscript           | 0
 bsp/xplorer4330/{m4 => M4}/SConscript                         | 0
 bsp/xplorer4330/{m4 => M4}/SConstruct                         | 0
 bsp/xplorer4330/{m4 => M4}/project.uvopt                      | 0
 bsp/xplorer4330/{m4 => M4}/project.uvproj                     | 0
 bsp/xplorer4330/{m4 => M4}/rtconfig.h                         | 0
 bsp/xplorer4330/{m4 => M4}/rtconfig.py                        | 0
 bsp/xplorer4330/{m4 => M4}/template.uvproj                    | 0
 10 files changed, 4 insertions(+), 3 deletions(-)
 rename bsp/xplorer4330/{libraries => Libraries}/SConscript (100%)
 rename bsp/xplorer4330/{m4 => M4}/SConscript (100%)
 rename bsp/xplorer4330/{m4 => M4}/SConstruct (100%)
 rename bsp/xplorer4330/{m4 => M4}/project.uvopt (100%)
 rename bsp/xplorer4330/{m4 => M4}/project.uvproj (100%)
 rename bsp/xplorer4330/{m4 => M4}/rtconfig.h (100%)
 rename bsp/xplorer4330/{m4 => M4}/rtconfig.py (100%)
 rename bsp/xplorer4330/{m4 => M4}/template.uvproj (100%)

diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
index 5f6233ad0e..33668ef37d 100644
--- a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
@@ -73,7 +73,8 @@ WEAK void SysTick_Handler(void);
 WEAK void IntDefaultHandler(void);
 #else
 WEAK void M0S_NMI_Handler(void);
-WEAK void M0S_HardFault_Handler (void);
+WEAK void M0S_HardFault_Handler(void);
+WEAK void M0S_DebugMon_Handler(void);
 WEAK void M0S_SVC_Handler(void);
 WEAK void M0S_PendSV_Handler(void);
 WEAK void M0S_SysTick_Handler(void);
diff --git a/bsp/xplorer4330/Libraries/Device/SConscript b/bsp/xplorer4330/Libraries/Device/SConscript
index d0aac1b070..a6ea5ee936 100644
--- a/bsp/xplorer4330/Libraries/Device/SConscript
+++ b/bsp/xplorer4330/Libraries/Device/SConscript
@@ -13,14 +13,14 @@ CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
 # add for startup script 
 if rtconfig.USE_CORE =='CORE_M4':
 	if rtconfig.CROSS_TOOL == 'gcc':
-		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s']
+		src += ['NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c']
 	elif rtconfig.CROSS_TOOL == 'keil':
 		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s']
 	elif rtconfig.CROSS_TOOL == 'iar':
 		src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s']
 else:
 	if rtconfig.CROSS_TOOL == 'gcc':
-		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s']
+		src += ['NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c']
 	elif rtconfig.CROSS_TOOL == 'keil':
 		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s']
 	elif rtconfig.CROSS_TOOL == 'iar':
diff --git a/bsp/xplorer4330/libraries/SConscript b/bsp/xplorer4330/Libraries/SConscript
similarity index 100%
rename from bsp/xplorer4330/libraries/SConscript
rename to bsp/xplorer4330/Libraries/SConscript
diff --git a/bsp/xplorer4330/m4/SConscript b/bsp/xplorer4330/M4/SConscript
similarity index 100%
rename from bsp/xplorer4330/m4/SConscript
rename to bsp/xplorer4330/M4/SConscript
diff --git a/bsp/xplorer4330/m4/SConstruct b/bsp/xplorer4330/M4/SConstruct
similarity index 100%
rename from bsp/xplorer4330/m4/SConstruct
rename to bsp/xplorer4330/M4/SConstruct
diff --git a/bsp/xplorer4330/m4/project.uvopt b/bsp/xplorer4330/M4/project.uvopt
similarity index 100%
rename from bsp/xplorer4330/m4/project.uvopt
rename to bsp/xplorer4330/M4/project.uvopt
diff --git a/bsp/xplorer4330/m4/project.uvproj b/bsp/xplorer4330/M4/project.uvproj
similarity index 100%
rename from bsp/xplorer4330/m4/project.uvproj
rename to bsp/xplorer4330/M4/project.uvproj
diff --git a/bsp/xplorer4330/m4/rtconfig.h b/bsp/xplorer4330/M4/rtconfig.h
similarity index 100%
rename from bsp/xplorer4330/m4/rtconfig.h
rename to bsp/xplorer4330/M4/rtconfig.h
diff --git a/bsp/xplorer4330/m4/rtconfig.py b/bsp/xplorer4330/M4/rtconfig.py
similarity index 100%
rename from bsp/xplorer4330/m4/rtconfig.py
rename to bsp/xplorer4330/M4/rtconfig.py
diff --git a/bsp/xplorer4330/m4/template.uvproj b/bsp/xplorer4330/M4/template.uvproj
similarity index 100%
rename from bsp/xplorer4330/m4/template.uvproj
rename to bsp/xplorer4330/M4/template.uvproj

From 2aa51d42f910781cc25747347eea4e0ae6bd1b77 Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Tue, 15 Jul 2014 14:58:05 +0800
Subject: [PATCH 44/86] ymodem: increase the default RYM_CHD_INTV_TICK

Frequent 'C' on the handshake will confuse some sender(lrzsz for
example).
---
 components/utilities/ymodem/ymodem.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/utilities/ymodem/ymodem.h b/components/utilities/ymodem/ymodem.h
index daed61d15f..43ee6f5c10 100644
--- a/components/utilities/ymodem/ymodem.h
+++ b/components/utilities/ymodem/ymodem.h
@@ -52,7 +52,7 @@ enum rym_code {
 #endif
 /* how many ticks between two handshake code. */
 #ifndef RYM_CHD_INTV_TICK
-#define RYM_CHD_INTV_TICK (RT_TICK_PER_SECOND / 4)
+#define RYM_CHD_INTV_TICK (RT_TICK_PER_SECOND * 3)
 #endif
 
 enum rym_stage {

From 67e79c3e97eaca969870894deab800953ea974c3 Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@gmail.com>
Date: Tue, 15 Jul 2014 15:40:05 +0800
Subject: [PATCH 45/86] lpc43xx:update the startup code.

---
 .../Source/Templates/ARM/startup_LPC43xx.s    |  12 -
 .../Source/Templates/GCC/cr_startup_lpc43xx.c | 502 ------------------
 .../Templates/GCC/cr_startup_lpc43xx_m0sub.c  | 463 ----------------
 .../Source/Templates/GCC/startup_LPC43xx.s    | 266 ++++++++++
 .../Source/Templates/GCC/startup_LPC43xx_M0.s | 266 ++++++++++
 .../LPC43xx/Source/Templates/system_LPC43xx.c |   6 +-
 bsp/lpc43xx/Libraries/Device/SConscript       |   4 +-
 7 files changed, 535 insertions(+), 984 deletions(-)
 delete mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
 delete mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
 create mode 100644 bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s

diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
index 8514f36120..d41d7813a2 100644
--- a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
@@ -128,10 +128,6 @@ __Vectors       DCD     __initial_sp              ; 0 Top of Stack
                 DCD     QEI_IRQHandler            ; 68 QEI
 
 
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
 
                 AREA    |.text|, CODE, READONLY
 
@@ -327,13 +323,5 @@ __user_initial_stackheap
 
                 ENDIF
 
-                AREA    |.text|,CODE, READONLY
-getPC           PROC
-                EXPORT  getPC
-
-                MOV     R0,LR
-                BX      LR
-
-                ENDP
 
                 END
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
deleted file mode 100644
index 5dd22339f8..0000000000
--- a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
+++ /dev/null
@@ -1,502 +0,0 @@
-//*****************************************************************************
-// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
-//
-// Version : 140113
-//*****************************************************************************
-//
-// Copyright(C) NXP Semiconductors, 2013-2014
-// All rights reserved.
-//
-// Software that is described herein is for illustrative purposes only
-// which provides customers with programming information regarding the
-// LPC products.  This software is supplied "AS IS" without any warranties of
-// any kind, and NXP Semiconductors and its licensor disclaim any and
-// all warranties, express or implied, including all implied warranties of
-// merchantability, fitness for a particular purpose and non-infringement of
-// intellectual property rights.  NXP Semiconductors assumes no responsibility
-// or liability for the use of the software, conveys no license or rights under any
-// patent, copyright, mask work right, or any other intellectual property rights in
-// or to any products. NXP Semiconductors reserves the right to make changes
-// in the software without notification. NXP Semiconductors also makes no
-// representation or warranty that such application will be suitable for the
-// specified use without further testing or modification.
-//
-// Permission to use, copy, modify, and distribute this software and its
-// documentation is hereby granted, under NXP Semiconductors' and its
-// licensor's relevant copyrights in the software, without fee, provided that it
-// is used in conjunction with NXP Semiconductors microcontrollers.  This
-// copyright, permission, and disclaimer notice must appear in all copies of
-// this code.
-//*****************************************************************************
-
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-    extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
-// Declaration of external SystemInit function
-extern void SystemInit(void);
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-void ResetISR(void);
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void MemManage_Handler(void);
-WEAK void BusFault_Handler(void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void DebugMon_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take
-// precedence over these weak definitions
-//
-//*****************************************************************************
-void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
-#if defined (__USE_LPCOPEN)
-void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
-#endif
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
-#if defined (__USE_LPCOPEN)
-void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
-#endif
-void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-    // Core Level - CM4
-    &_vStackTop,                    // The initial stack pointer
-    ResetISR,                       // The reset handler
-    NMI_Handler,                    // The NMI handler
-    HardFault_Handler,              // The hard fault handler
-    MemManage_Handler,              // The MPU fault handler
-    BusFault_Handler,               // The bus fault handler
-    UsageFault_Handler,             // The usage fault handler
-    0,                              // Reserved
-    0,                              // Reserved
-    0,                              // Reserved
-    0,                              // Reserved
-    SVC_Handler,                    // SVCall handler
-    DebugMon_Handler,               // Debug monitor handler
-    0,                              // Reserved
-    PendSV_Handler,                 // The PendSV handler
-    SysTick_Handler,                // The SysTick handler
-
-    // Chip Level - LPC43 (M4)
-    DAC_IRQHandler,           // 16
-#if defined (__USE_LPCOPEN)
-    M0APP_IRQHandler,        // 17 CortexM4/M0 (LPC43XX ONLY)
-#else
-    M0CORE_IRQHandler,        // 17
-#endif
-    DMA_IRQHandler,           // 18
-    0,           // 19
-    FLASH_EEPROM_IRQHandler,   // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
-    ETH_IRQHandler,           // 21
-    SDIO_IRQHandler,          // 22
-    LCD_IRQHandler,           // 23
-    USB0_IRQHandler,          // 24
-    USB1_IRQHandler,          // 25
-    SCT_IRQHandler,           // 26
-    RIT_IRQHandler,           // 27
-    TIMER0_IRQHandler,        // 28
-    TIMER1_IRQHandler,        // 29
-    TIMER2_IRQHandler,        // 30
-    TIMER3_IRQHandler,        // 31
-    MCPWM_IRQHandler,         // 32
-    ADC0_IRQHandler,          // 33
-    I2C0_IRQHandler,          // 34
-    I2C1_IRQHandler,          // 35
-    SPI_IRQHandler,           // 36
-    ADC1_IRQHandler,          // 37
-    SSP0_IRQHandler,          // 38
-    SSP1_IRQHandler,          // 39
-    UART0_IRQHandler,         // 40
-    UART1_IRQHandler,         // 41
-    UART2_IRQHandler,         // 42
-    UART3_IRQHandler,         // 43
-    I2S0_IRQHandler,          // 44
-    I2S1_IRQHandler,          // 45
-    SPIFI_IRQHandler,         // 46
-    SGPIO_IRQHandler,         // 47
-    GPIO0_IRQHandler,         // 48
-    GPIO1_IRQHandler,         // 49
-    GPIO2_IRQHandler,         // 50
-    GPIO3_IRQHandler,         // 51
-    GPIO4_IRQHandler,         // 52
-    GPIO5_IRQHandler,         // 53
-    GPIO6_IRQHandler,         // 54
-    GPIO7_IRQHandler,         // 55
-    GINT0_IRQHandler,         // 56
-    GINT1_IRQHandler,         // 57
-    EVRT_IRQHandler,          // 58
-    CAN1_IRQHandler,          // 59
-    0,                        // 60
-#if defined (__USE_LPCOPEN)
-    ADCHS_IRQHandler,         // 61 ADCHS combined interrupt
-#else
-    VADC_IRQHandler,          // 61
-#endif
-    ATIMER_IRQHandler,        // 62
-    RTC_IRQHandler,           // 63
-    0,                        // 64
-    WDT_IRQHandler,           // 65
-    M0SUB_IRQHandler,         // 66
-    CAN0_IRQHandler,          // 67
-    QEI_IRQHandler,           // 68
-};
-
-
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-        __attribute__((section(".after_vectors"
-)))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int *pulSrc = (unsigned int*) romstart;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4)
-        *pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4)
-        *pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//
-//*****************************************************************************
-void ResetISR(void) {
-
-// *************************************************************
-// The following conditional block of code manually resets as
-// much of the peripheral set of the LPC43 as possible. This is
-// done because the LPC43 does not provide a means of triggering
-// a full system reset under debugger control, which can cause
-// problems in certain circumstances when debugging.
-//
-// You can prevent this code block being included if you require
-// (for example when creating a final executable which you will
-// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
-//
-#ifndef DONT_RESET_ON_RESTART
-
-    // Disable interrupts
-    __asm volatile ("cpsid i");
-    // equivalent to CMSIS '__disable_irq()' function
-
-    unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
-    // LPC_RGU->RESET_CTRL0 @ 0x40053100
-    // LPC_RGU->RESET_CTRL1 @ 0x40053104
-    // Note that we do not use the CMSIS register access mechanism,
-    // as there is no guarantee that the project has been configured
-    // to use CMSIS.
-
-    // Write to LPC_RGU->RESET_CTRL0
-    *(RESET_CONTROL + 0) = 0x10DF1000;
-    // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
-    // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
-
-    // Write to LPC_RGU->RESET_CTRL1
-    *(RESET_CONTROL + 1) = 0x01DFF7FF;
-    // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
-    // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
-    // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
-    // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
-
-    // Clear all pending interrupts in the NVIC
-    volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
-    unsigned int irqpendloop;
-    for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
-        *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
-    }
-
-    // Reenable interrupts
-    __asm volatile ("cpsie i");
-    // equivalent to CMSIS '__enable_irq()' function
-
-#endif  // ifndef DONT_RESET_ON_RESTART
-// *************************************************************
-
-#if defined (__USE_LPCOPEN)
-    SystemInit();
-#endif
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-    unsigned int LoadAddr, ExeAddr, SectionLen;
-    unsigned int *SectionTableAddr;
-
-    // Load base address of Global Section Table
-    SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-    while (SectionTableAddr < &__data_section_table_end) {
-        LoadAddr = *SectionTableAddr++;
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        data_init(LoadAddr, ExeAddr, SectionLen);
-    }
-    // At this point, SectionTableAddr = &__bss_section_table;
-    // Zero fill the bss segment
-    while (SectionTableAddr < &__bss_section_table_end) {
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        bss_init(ExeAddr, SectionLen);
-    }
-
-#if !defined (__USE_LPCOPEN)
-// LPCOpen init code deals with FP and VTOR initialisation
-#if defined (__VFP_FP__) && !defined (__SOFTFP__)
-    /*
-     * Code to enable the Cortex-M4 FPU only included
-     * if appropriate build options have been selected.
-     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
-     */
-    // CPACR is located at address 0xE000ED88
-    asm("LDR.W R0, =0xE000ED88");
-    // Read CPACR
-    asm("LDR R1, [R0]");
-    // Set bits 20-23 to enable CP10 and CP11 coprocessors
-    asm(" ORR R1, R1, #(0xF << 20)");
-    // Write back the modified value to the CPACR
-    asm("STR R1, [R0]");
-#endif // (__VFP_FP__) && !(__SOFTFP__)
-    // ******************************
-    // Check to see if we are running the code from a non-zero
-    // address (eg RAM, external flash), in which case we need
-    // to modify the VTOR register to tell the CPU that the
-    // vector table is located at a non-0x0 address.
-
-    // Note that we do not use the CMSIS register access mechanism,
-    // as there is no guarantee that the project has been configured
-    // to use CMSIS.
-    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
-    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
-        // CMSIS : SCB->VTOR = <address of vector table>
-        *pSCB_VTOR = (unsigned int) g_pfnVectors;
-    }
-#endif
-
-#if defined (__USE_CMSIS)
-    SystemInit();
-#endif
-
-#if defined (__cplusplus)
-    //
-    // Call C++ library initialisation
-    //
-    __libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-    // Call the Redlib library, which in turn calls main()
-    __main();
-#else
-    main();
-#endif
-
-    //
-    // main() shouldn't return, but if it does, we'll just enter an infinite loop
-    //
-    while (1) {
-        ;
-    }
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void NMI_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void HardFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void MemManage_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void BusFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void UsageFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SVC_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void DebugMon_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void PendSV_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SysTick_Handler(void) {
-    while (1) {
-    }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void IntDefaultHandler(void) {
-    while (1) {
-    }
-}
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
deleted file mode 100644
index 5f6233ad0e..0000000000
--- a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
+++ /dev/null
@@ -1,463 +0,0 @@
-//*****************************************************************************
-// LPC43xx (Cortex M0 SUB) Startup code for use with LPCXpresso IDE
-//
-// Version : 131115
-//*****************************************************************************
-//
-// Copyright(C) NXP Semiconductors, 2013
-// All rights reserved.
-//
-// Software that is described herein is for illustrative purposes only
-// which provides customers with programming information regarding the
-// LPC products.  This software is supplied "AS IS" without any warranties of
-// any kind, and NXP Semiconductors and its licensor disclaim any and
-// all warranties, express or implied, including all implied warranties of
-// merchantability, fitness for a particular purpose and non-infringement of
-// intellectual property rights.  NXP Semiconductors assumes no responsibility
-// or liability for the use of the software, conveys no license or rights under any
-// patent, copyright, mask work right, or any other intellectual property rights in
-// or to any products. NXP Semiconductors reserves the right to make changes
-// in the software without notification. NXP Semiconductors also makes no
-// representation or warranty that such application will be suitable for the
-// specified use without further testing or modification.
-//
-// Permission to use, copy, modify, and distribute this software and its
-// documentation is hereby granted, under NXP Semiconductors' and its
-// licensor's relevant copyrights in the software, without fee, provided that it
-// is used in conjunction with NXP Semiconductors microcontrollers.  This
-// copyright, permission, and disclaimer notice must appear in all copies of
-// this code.
-//*****************************************************************************
-
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-  extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
-void SystemInit(void);
-#endif
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-     void ResetISR(void);
-#if defined (__USE_LPCOPEN)
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-#else
-WEAK void M0S_NMI_Handler(void);
-WEAK void M0S_HardFault_Handler (void);
-WEAK void M0S_SVC_Handler(void);
-WEAK void M0S_PendSV_Handler(void);
-WEAK void M0S_SysTick_Handler(void);
-WEAK void M0S_IntDefaultHandler(void);
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take
-// precedence over these weak definitions
-//
-//*****************************************************************************
-#if defined (__USE_LPCOPEN)
-void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_INPUT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_MATCH_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_SHIFT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_POS_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S0_I2S1_QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPIFI_ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void M0S_DAC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_M4CORE_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_DMA_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_INPUT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_MATCH_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_SHIFT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_POS_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USB0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USB1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SCT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_RITIMER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_GINT1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_TIMER1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_TIMER2_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_PIN_INT5_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_ADC0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_MCPWM_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_I2C0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_I2C1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SPI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_ADC1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SSP0_OR_SSP1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_EVENTROUTER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USART0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_UART1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USART2_OR_C_CAN1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USART3_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_C_CAN0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SPIFI_OR_VADC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_M0APP_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-#endif
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-
-#if defined (__USE_LPCOPEN)
-    // Core Level - CM0
-    &_vStackTop,                        // The initial stack pointer
-    ResetISR,                           // 1 The reset handler
-    NMI_Handler,                    // The NMI handler
-    HardFault_Handler,              // The hard fault handler
-    0,                                  // 4 Reserved
-    0,                                  // 5 Reserved
-    0,                                  // 6 Reserved
-    0,                                  // 7 Reserved
-    0,                                  // 8 Reserved
-    0,                                  // 9 Reserved
-    0,                                  // 10 Reserved
-    SVC_Handler,                    // SVCall handler
-    0,                              // Reserved
-    0,                              // Reserved
-    PendSV_Handler,                 // The PendSV handler
-    SysTick_Handler,                // The SysTick handler
-
-    // Chip Level - 43xx M0SUB core
-    DAC_IRQHandler,                 // 16
-    M4_IRQHandler,             // 17 Interrupt from M4 Core
-    DMA_IRQHandler,                 // 18 General Purpose DMA
-    0,                              // 19 Reserved
-    SGPIO_INPUT_IRQHandler,         // 20
-    SGPIO_MATCH_IRQHandler,         // 21
-    SGPIO_SHIFT_IRQHandler,         // 22
-    SGPIO_POS_IRQHandler,           // 23
-    USB0_IRQHandler,                // 24 USB0
-    USB1_IRQHandler,                // 25 USB1
-    SCT_IRQHandler ,                // 26 State Configurable Timer
-    RIT_IRQHandler,                 // 27 Repetitive Interrupt Timer
-    GINT1_IRQHandler,               // 28 GINT1
-    TIMER1_IRQHandler,              // 29 Timer1
-    TIMER2_IRQHandler,              // 30 Timer2
-    GPIO5_IRQHandler,               // 31
-    MCPWM_IRQHandler,               // 32 Motor Control PWM
-    ADC0_IRQHandler,                // 33 ADC0
-    I2C0_IRQHandler,                // 34
-    I2C1_IRQHandler,                // 35
-    SPI_IRQHandler,                 // 36
-    ADC1_IRQHandler,                // 37
-    SSP0_SSP1_IRQHandler,           // 38
-    EVRT_IRQHandler,                // 39 Event Router
-    UART0_IRQHandler,               // 41 USART0
-    UART1_IRQHandler,               // 41 UART1
-    UART2_CAN1_IRQHandler,          // 42 USART2 or C CAN1
-    UART3_IRQHandler,               // 43 USART3
-    I2S0_I2S1_QEI_IRQHandler,       // 35 I2C0 or I2C1 or I2S1 or QEI
-    CAN0_IRQHandler,                // 45 C CAN0
-    SPIFI_ADCHS_IRQHandler,         // 46
-    M0APP_IRQHandler,               // 47 Interrupt from M0APP
-  };
-#else
-    // Core Level - CM0
-    &_vStackTop,                        // The initial stack pointer
-    ResetISR,                           // 1 The reset handler
-    M0S_NMI_Handler,                    // 2 The NMI handler
-    M0S_HardFault_Handler,              // 3 The hard fault handler
-    0,                                  // 4 Reserved
-    0,                                  // 5 Reserved
-    0,                                  // 6 Reserved
-    0,                                  // 7 Reserved
-    0,                                  // 8 Reserved
-    0,                                  // 9 Reserved
-    0,                                  // 10 Reserved
-    M0S_SVC_Handler,                    // 11 SVCall handler
-    M0S_DebugMon_Handler,               // 12 Debug monitor handler
-    0,                                  // 13 Reserved
-    M0S_PendSV_Handler,                 // 14 The PendSV handler
-    M0S_SysTick_Handler,                // 15 The SysTick handler
-
-    // Chip Level - LPC43 (CM0 SUB)
-    M0S_DAC_IRQHandler,                 // 16
-    M0S_M4CORE_IRQHandler,              // 17 Interrupt from M4 Core
-    M0S_DMA_IRQHandler,                 // 18 General Purpose DMA
-    0,                                  // 19 Reserved
-    M0S_SGPIO_INPUT_IRQHandler,         // 20
-    M0S_SGPIO_MATCH_IRQHandler,         // 21
-    M0S_SGPIO_SHIFT_IRQHandler,         // 22
-    M0S_SGPIO_POS_IRQHandler,           // 23
-    M0S_USB0_IRQHandler,                // 24 USB0
-    M0S_USB1_IRQHandler,                // 25 USB1
-    M0S_SCT_IRQHandler ,                // 26 State Configurable Timer
-    M0S_RITIMER_IRQHandler,             // 27 Repetitive Interrupt Timer
-    M0S_GINT1_IRQHandler,               // 28 GINT1
-    M0S_TIMER1_IRQHandler,              // 29 Timer1
-    M0S_TIMER2_IRQHandler,              // 30 Timer2
-    M0S_PIN_INT5_IRQHandler,            // 31
-    M0S_MCPWM_IRQHandler,               // 32 Motor Control PWM
-    M0S_ADC0_IRQHandler,                // 33 ADC0
-    M0S_I2C0_IRQHandler,                // 34
-    M0S_I2C1_IRQHandler,                // 35
-    M0S_SPI_IRQHandler,                 // 36
-    M0S_ADC1_IRQHandler,                // 37
-    M0S_SSP0_OR_SSP1_IRQHandler,        // 38
-    M0S_EVENTROUTER_IRQHandler,         // 39 Event Router
-    M0S_USART0_IRQHandler,              // 41 USART0
-    M0S_UART1_IRQHandler,               // 41 UART1
-    M0S_USART2_OR_C_CAN1_IRQHandler,    // 42 USART2 or C CAN1
-    M0S_USART3_IRQHandler,              // 43 USART3
-    M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler,
-                                        // 35 I2C0 or I2C1 or I2S1 or QEI
-    M0S_C_CAN0_IRQHandler,              // 45 C CAN0
-    M0S_SPIFI_OR_VADC_IRQHandler,       // 46
-    M0S_M0APP_IRQHandler,               // 47 Interrupt from M0APP
-  };
-#endif
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-  unsigned int *pulDest = (unsigned int*) start;
-  unsigned int *pulSrc = (unsigned int*) romstart;
-  unsigned int loop;
-  for (loop = 0; loop < len; loop = loop + 4)
-    *pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-  unsigned int *pulDest = (unsigned int*) start;
-  unsigned int loop;
-  for (loop = 0; loop < len; loop = loop + 4)
-    *pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//
-//*****************************************************************************
-void
-ResetISR(void) {
-
-  // ******************************
-  // Modify CREG->M0SUBMEMMAP so that M0 looks in correct place
-  // for its vector table when an exception is triggered.
-  // Note that we do not use the CMSIS register access mechanism,
-  // as there is no guarantee that the project has been configured
-  // to use CMSIS.
-  unsigned int *pCREG_M0SUBMEMMAP = (unsigned int *) 0x40043308;
-  // CMSIS : CREG->M0SUBMEMMAP = <address of vector table>
-  *pCREG_M0SUBMEMMAP = (unsigned int)g_pfnVectors;
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-  unsigned int LoadAddr, ExeAddr, SectionLen;
-  unsigned int *SectionTableAddr;
-
-  // Load base address of Global Section Table
-  SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-  while (SectionTableAddr < &__data_section_table_end) {
-    LoadAddr = *SectionTableAddr++;
-    ExeAddr = *SectionTableAddr++;
-    SectionLen = *SectionTableAddr++;
-    data_init(LoadAddr, ExeAddr, SectionLen);
-  }
-  // At this point, SectionTableAddr = &__bss_section_table;
-  // Zero fill the bss segment
-  while (SectionTableAddr < &__bss_section_table_end) {
-    ExeAddr = *SectionTableAddr++;
-    SectionLen = *SectionTableAddr++;
-    bss_init(ExeAddr, SectionLen);
-  }
-
-// **********************************************************
-// No need to call SystemInit() here, as master CM4 cpu will
-// have done the main system set up before enabling CM0.
-// **********************************************************
-
-#if defined (__cplusplus)
-  //
-  // Call C++ library initialisation
-  //
-  __libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-  // Call the Redlib library, which in turn calls main()
-  __main() ;
-#else
-  main();
-#endif
-
-  //
-  // main() shouldn't return, but if it does, we'll just enter an infinite loop
-  //
-  while (1) {
-    ;
-  }
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void NMI_Handler(void)
-#else
-void M0S_NMI_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void HardFault_Handler(void)
-#else
-void M0S_HardFault_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void SVC_Handler(void)
-#else
-void M0S_SVC_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void PendSV_Handler(void)
-#else
-void M0S_PendSV_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void SysTick_Handler(void)
-#else
-void M0S_SysTick_Handler(void)
-#endif
-{   while(1) { }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void IntDefaultHandler(void)
-#else
-void M0S_IntDefaultHandler(void)
-#endif
-{   while(1) { }
-}
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
new file mode 100644
index 0000000000..879e33872d
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
@@ -0,0 +1,266 @@
+/*****************************************************************************/
+/* startup_LPC43xx.s: Startup file for LPC43xx device series                 */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+	.syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+	
+	.word  _sidata
+	.word  _sdata
+	.word  _edata
+	.word  _sbss
+	.word  _ebss
+
+
+    .equ    Sign_Value, 0x5A5A5A5A
+
+/* Vector Table */
+
+    .section ".interrupt_vector"
+    .globl  __interrupt_vector
+    .type   __interrupt_vector, %function
+
+__interrupt_vector:
+    .long   _estack                 /* Top of Stack                 */
+    .long   Reset_Handler               /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   Sign_Value                  /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+/* External Interrupts */
+    .long   DAC_IRQHandler              /* 16 D/A Converter             */
+    .long   M0CORE_IRQHandler           /* 17 M0 Core                   */
+    .long   DMA_IRQHandler              /* 18 General Purpose DMA       */
+    .long   EZH_IRQHandler              /* 19 EZH/EDM                   */
+    .long   FLASH_EEPROM_IRQHandler     /* 20 Reserved for Typhoon      */
+    .long   ETH_IRQHandler              /* 21 Ethernet                  */
+    .long   SDIO_IRQHandler             /* 22 SD/MMC                    */
+    .long   LCD_IRQHandler              /* 23 LCD                       */
+    .long   USB0_IRQHandler             /* 24 USB0                      */
+    .long   USB1_IRQHandler             /* 25 USB1                      */
+    .long   SCT_IRQHandler              /* 26 State Configurable Timer  */
+    .long   RIT_IRQHandler              /* 27 Repetitive Interrupt Timer*/
+    .long   TIMER0_IRQHandler           /* 28 Timer0                    */
+    .long   TIMER1_IRQHandler           /* 29 Timer1                    */
+    .long   TIMER2_IRQHandler           /* 30 Timer2                    */
+    .long   TIMER3_IRQHandler           /* 31 Timer3                    */
+    .long   MCPWM_IRQHandler            /* 32 Motor Control PWM         */
+    .long   ADC0_IRQHandler             /* 33 A/D Converter 0           */
+    .long   I2C0_IRQHandler             /* 34 I2C0                      */
+    .long   I2C1_IRQHandler             /* 35 I2C1                      */
+    .long   SPI_IRQHandler              /* 36 SPI                       */
+    .long   ADC1_IRQHandler             /* 37 A/D Converter 1           */
+    .long   SSP0_IRQHandler             /* 38 SSP0                      */
+    .long   SSP1_IRQHandler             /* 39 SSP1                      */
+    .long   UART0_IRQHandler            /* 40 UART0                     */
+    .long   UART1_IRQHandler            /* 41 UART1                     */
+    .long   UART2_IRQHandler            /* 42 UART2                     */
+    .long   UART3_IRQHandler            /* 43 UART3                     */
+    .long   I2S0_IRQHandler             /* 44 I2S0                      */
+    .long   I2S1_IRQHandler             /* 45 I2S1                      */
+    .long   SPIFI_IRQHandler            /* 46 SPI Flash Interface       */
+    .long   SGPIO_IRQHandler            /* 47 SGPIO                     */
+    .long   GPIO0_IRQHandler            /* 48 GPIO0                     */
+    .long   GPIO1_IRQHandler            /* 49 GPIO1                     */
+    .long   GPIO2_IRQHandler            /* 50 GPIO2                     */
+    .long   GPIO3_IRQHandler            /* 51 GPIO3                     */
+    .long   GPIO4_IRQHandler            /* 52 GPIO4                     */
+    .long   GPIO5_IRQHandler            /* 53 GPIO5                     */
+    .long   GPIO6_IRQHandler            /* 54 GPIO6                     */
+    .long   GPIO7_IRQHandler            /* 55 GPIO7                     */
+    .long   GINT0_IRQHandler            /* 56 GINT0                     */
+    .long   GINT1_IRQHandler            /* 57 GINT1                     */
+    .long   EVRT_IRQHandler             /* 58 Event Router              */
+    .long   CAN1_IRQHandler             /* 59 C_CAN1                    */
+    .long   0                           /* 60 Reserved                  */
+    .long   VADC_IRQHandler             /* 61 VADC                      */
+    .long   ATIMER_IRQHandler           /* 62 ATIMER                    */
+    .long   RTC_IRQHandler              /* 63 RTC                       */
+    .long   0                           /* 64 Reserved                  */
+    .long   WDT_IRQHandler              /* 65 WDT                       */
+    .long   M0s_IRQHandler              /* 66 M0s                       */
+    .long   CAN0_IRQHandler             /* 67 C_CAN0                    */
+    .long   QEI_IRQHandler              /* 68 QEI                       */
+
+    .size   __interrupt_vector, . - __interrupt_vector
+
+
+    .thumb
+
+
+/* Reset Handler */
+    .section  .text.Reset_Handler
+	.weak  Reset_Handler
+	.type  Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+.ifdef RAM_MODE
+/* Clear .bss section (Zero init) */
+	mov     R0, #0
+	ldr     R1, =__bss_start__
+	ldr    R2, =__bss_end__
+	cmp     R1,R2
+	beq     BSSIsEmpty
+LoopZI:
+    cmp     R1, R2
+    bhs     BSSIsEmpty
+    str     R0, [R1]
+    add     R1, #4
+    blo     LoopZI
+BSSIsEmpty:
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.else
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.endif
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ    DAC_IRQHandler
+    IRQ    M0CORE_IRQHandler
+    IRQ    DMA_IRQHandler
+    IRQ    EZH_IRQHandler
+    IRQ    FLASH_EEPROM_IRQHandler
+    IRQ    ETH_IRQHandler
+    IRQ    SDIO_IRQHandler
+    IRQ    LCD_IRQHandler
+    IRQ    USB0_IRQHandler
+    IRQ    USB1_IRQHandler
+    IRQ    SCT_IRQHandler
+    IRQ    RIT_IRQHandler
+    IRQ    TIMER0_IRQHandler
+    IRQ    TIMER1_IRQHandler
+    IRQ    TIMER2_IRQHandler
+    IRQ    TIMER3_IRQHandler
+    IRQ    MCPWM_IRQHandler
+    IRQ    ADC0_IRQHandler
+    IRQ    I2C0_IRQHandler
+    IRQ    I2C1_IRQHandler
+    IRQ    SPI_IRQHandler
+    IRQ    ADC1_IRQHandler
+    IRQ    SSP0_IRQHandler
+    IRQ    SSP1_IRQHandler
+    IRQ    UART0_IRQHandler
+    IRQ    UART1_IRQHandler
+    IRQ    UART2_IRQHandler
+    IRQ    UART3_IRQHandler
+    IRQ    I2S0_IRQHandler
+    IRQ    I2S1_IRQHandler
+    IRQ    SPIFI_IRQHandler
+    IRQ    SGPIO_IRQHandler
+    IRQ    GPIO0_IRQHandler
+    IRQ    GPIO1_IRQHandler
+    IRQ    GPIO2_IRQHandler
+    IRQ    GPIO3_IRQHandler
+    IRQ    GPIO4_IRQHandler
+    IRQ    GPIO5_IRQHandler
+    IRQ    GPIO6_IRQHandler
+    IRQ    GPIO7_IRQHandler
+    IRQ    GINT0_IRQHandler
+    IRQ    GINT1_IRQHandler
+    IRQ    EVRT_IRQHandler
+    IRQ    CAN1_IRQHandler
+    IRQ    VADC_IRQHandler
+    IRQ    ATIMER_IRQHandler
+    IRQ    RTC_IRQHandler
+    IRQ    WDT_IRQHandler
+    IRQ    M0s_IRQHandler
+    IRQ    CAN0_IRQHandler
+    IRQ    QEI_IRQHandler
+
+    .end
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s
new file mode 100644
index 0000000000..5a7b26405d
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s
@@ -0,0 +1,266 @@
+/*****************************************************************************/
+/* startup_LPC43xx.s: Startup file for LPC43xx device series                 */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+	.syntax unified
+	.cpu cortex-m0
+	.fpu softvfp
+	.thumb
+	
+	.word  _sidata
+	.word  _sdata
+	.word  _edata
+	.word  _sbss
+	.word  _ebss
+
+
+    .equ    Sign_Value, 0x5A5A5A5A
+
+/* Vector Table */
+
+    .section ".interrupt_vector"
+    .globl  __interrupt_vector
+    .type   __interrupt_vector, %function
+
+__interrupt_vector:
+    .long   _estack                 /* Top of Stack                 */
+    .long   Reset_Handler               /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   Sign_Value                  /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+/* External Interrupts */
+    .long   DAC_IRQHandler              /* 16 D/A Converter             */
+    .long   M4CORE_IRQHandler           /* 17 M0 Core                   */
+    .long   DMA_IRQHandler              /* 18 General Purpose DMA       */
+    .long   EZH_IRQHandler              /* 19 EZH/EDM                   */
+    .long   FLASH_EEPROM_IRQHandler     /* 20 Reserved for Typhoon      */
+    .long   ETH_IRQHandler              /* 21 Ethernet                  */
+    .long   SDIO_IRQHandler             /* 22 SD/MMC                    */
+    .long   LCD_IRQHandler              /* 23 LCD                       */
+    .long   USB0_IRQHandler             /* 24 USB0                      */
+    .long   USB1_IRQHandler             /* 25 USB1                      */
+    .long   SCT_IRQHandler              /* 26 State Configurable Timer  */
+    .long   RIT_IRQHandler              /* 27 Repetitive Interrupt Timer*/
+    .long   TIMER0_IRQHandler           /* 28 Timer0                    */
+    .long   TIMER1_IRQHandler           /* 29 Timer1                    */
+    .long   TIMER2_IRQHandler           /* 30 Timer2                    */
+    .long   TIMER3_IRQHandler           /* 31 Timer3                    */
+    .long   MCPWM_IRQHandler            /* 32 Motor Control PWM         */
+    .long   ADC0_IRQHandler             /* 33 A/D Converter 0           */
+    .long   I2C0_IRQHandler             /* 34 I2C0                      */
+    .long   I2C1_IRQHandler             /* 35 I2C1                      */
+    .long   SPI_IRQHandler              /* 36 SPI                       */
+    .long   ADC1_IRQHandler             /* 37 A/D Converter 1           */
+    .long   SSP0_IRQHandler             /* 38 SSP0                      */
+    .long   SSP1_IRQHandler             /* 39 SSP1                      */
+    .long   UART0_IRQHandler            /* 40 UART0                     */
+    .long   UART1_IRQHandler            /* 41 UART1                     */
+    .long   UART2_IRQHandler            /* 42 UART2                     */
+    .long   UART3_IRQHandler            /* 43 UART3                     */
+    .long   I2S0_IRQHandler             /* 44 I2S0                      */
+    .long   I2S1_IRQHandler             /* 45 I2S1                      */
+    .long   SPIFI_IRQHandler            /* 46 SPI Flash Interface       */
+    .long   SGPIO_IRQHandler            /* 47 SGPIO                     */
+    .long   GPIO0_IRQHandler            /* 48 GPIO0                     */
+    .long   GPIO1_IRQHandler            /* 49 GPIO1                     */
+    .long   GPIO2_IRQHandler            /* 50 GPIO2                     */
+    .long   GPIO3_IRQHandler            /* 51 GPIO3                     */
+    .long   GPIO4_IRQHandler            /* 52 GPIO4                     */
+    .long   GPIO5_IRQHandler            /* 53 GPIO5                     */
+    .long   GPIO6_IRQHandler            /* 54 GPIO6                     */
+    .long   GPIO7_IRQHandler            /* 55 GPIO7                     */
+    .long   GINT0_IRQHandler            /* 56 GINT0                     */
+    .long   GINT1_IRQHandler            /* 57 GINT1                     */
+    .long   EVRT_IRQHandler             /* 58 Event Router              */
+    .long   CAN1_IRQHandler             /* 59 C_CAN1                    */
+    .long   0                           /* 60 Reserved                  */
+    .long   VADC_IRQHandler             /* 61 VADC                      */
+    .long   ATIMER_IRQHandler           /* 62 ATIMER                    */
+    .long   RTC_IRQHandler              /* 63 RTC                       */
+    .long   0                           /* 64 Reserved                  */
+    .long   WDT_IRQHandler              /* 65 WDT                       */
+    .long   M0s_IRQHandler              /* 66 M0s                       */
+    .long   CAN0_IRQHandler             /* 67 C_CAN0                    */
+    .long   QEI_IRQHandler              /* 68 QEI                       */
+
+    .size   __interrupt_vector, . - __interrupt_vector
+
+
+    .thumb
+
+
+/* Reset Handler */
+    .section  .text.Reset_Handler
+	.weak  Reset_Handler
+	.type  Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+.ifdef RAM_MODE
+/* Clear .bss section (Zero init) */
+	mov     R0, #0
+	ldr     R1, =__bss_start__
+	ldr    R2, =__bss_end__
+	cmp     R1,R2
+	beq     BSSIsEmpty
+LoopZI:
+    cmp     R1, R2
+    bhs     BSSIsEmpty
+    str     R0, [R1]
+    add     R1, #4
+    blo     LoopZI
+BSSIsEmpty:
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.else
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.endif
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ    DAC_IRQHandler
+    IRQ    M0CORE_IRQHandler
+    IRQ    DMA_IRQHandler
+    IRQ    EZH_IRQHandler
+    IRQ    FLASH_EEPROM_IRQHandler
+    IRQ    ETH_IRQHandler
+    IRQ    SDIO_IRQHandler
+    IRQ    LCD_IRQHandler
+    IRQ    USB0_IRQHandler
+    IRQ    USB1_IRQHandler
+    IRQ    SCT_IRQHandler
+    IRQ    RIT_IRQHandler
+    IRQ    TIMER0_IRQHandler
+    IRQ    TIMER1_IRQHandler
+    IRQ    TIMER2_IRQHandler
+    IRQ    TIMER3_IRQHandler
+    IRQ    MCPWM_IRQHandler
+    IRQ    ADC0_IRQHandler
+    IRQ    I2C0_IRQHandler
+    IRQ    I2C1_IRQHandler
+    IRQ    SPI_IRQHandler
+    IRQ    ADC1_IRQHandler
+    IRQ    SSP0_IRQHandler
+    IRQ    SSP1_IRQHandler
+    IRQ    UART0_IRQHandler
+    IRQ    UART1_IRQHandler
+    IRQ    UART2_IRQHandler
+    IRQ    UART3_IRQHandler
+    IRQ    I2S0_IRQHandler
+    IRQ    I2S1_IRQHandler
+    IRQ    SPIFI_IRQHandler
+    IRQ    SGPIO_IRQHandler
+    IRQ    GPIO0_IRQHandler
+    IRQ    GPIO1_IRQHandler
+    IRQ    GPIO2_IRQHandler
+    IRQ    GPIO3_IRQHandler
+    IRQ    GPIO4_IRQHandler
+    IRQ    GPIO5_IRQHandler
+    IRQ    GPIO6_IRQHandler
+    IRQ    GPIO7_IRQHandler
+    IRQ    GINT0_IRQHandler
+    IRQ    GINT1_IRQHandler
+    IRQ    EVRT_IRQHandler
+    IRQ    CAN1_IRQHandler
+    IRQ    VADC_IRQHandler
+    IRQ    ATIMER_IRQHandler
+    IRQ    RTC_IRQHandler
+    IRQ    WDT_IRQHandler
+    IRQ    M0s_IRQHandler
+    IRQ    CAN0_IRQHandler
+    IRQ    QEI_IRQHandler
+
+    .end
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
index 3bd76f5de6..c51bd1c67e 100644
--- a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
+++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
@@ -863,7 +863,6 @@ void SystemCoreClockUpdate (void) {
 }
 
 
-extern uint32_t getPC (void);
 
 /*----------------------------------------------------------------------------
   Initialize the system
@@ -877,10 +876,7 @@ void SystemInit (void) {
 
   /* Disable SysTick timer                                                    */
   SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
-#ifdef CORE_M4
-  /* Set vector table pointer */
-  SCB->VTOR = getPC() & 0xFFF00000;
-#endif
+
   /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
   SetClock();
 
diff --git a/bsp/lpc43xx/Libraries/Device/SConscript b/bsp/lpc43xx/Libraries/Device/SConscript
index d0aac1b070..47f7e04885 100644
--- a/bsp/lpc43xx/Libraries/Device/SConscript
+++ b/bsp/lpc43xx/Libraries/Device/SConscript
@@ -8,8 +8,8 @@ src = Split('''
 NXP/LPC43xx/Source/Templates/system_LPC43xx.c
 ''')
 CPPPATH = [cwd + '/NXP/LPC43xx/Include', cwd + '/../CMSIS/Include']
-CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
-
+CPPDEFINES = [rtconfig.USE_CORE]
+CPPDEFINES += ['USE_SPIFI']
 # add for startup script 
 if rtconfig.USE_CORE =='CORE_M4':
 	if rtconfig.CROSS_TOOL == 'gcc':

From 7b32a2bd318353a09c7ccb89159b8ea8da665f46 Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@gmail.com>
Date: Tue, 15 Jul 2014 15:42:22 +0800
Subject: [PATCH 46/86] lpc43xx:add the linker script file.

---
 bsp/lpc43xx/M0/rtconfig.py                |   2 +-
 bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.ld  | 133 ++++++++++++++++++++++
 bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.sct |  15 +++
 bsp/lpc43xx/M4/rtconfig.py                |   6 +-
 bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.ld  | 133 ++++++++++++++++++++++
 bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.sct |  15 +++
 6 files changed, 300 insertions(+), 4 deletions(-)
 create mode 100644 bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.ld
 create mode 100644 bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.sct
 create mode 100644 bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.ld
 create mode 100644 bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.sct

diff --git a/bsp/lpc43xx/M0/rtconfig.py b/bsp/lpc43xx/M0/rtconfig.py
index f548669122..5eef1d3ab8 100644
--- a/bsp/lpc43xx/M0/rtconfig.py
+++ b/bsp/lpc43xx/M0/rtconfig.py
@@ -53,7 +53,7 @@ if PLATFORM == 'gcc':
         DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
     CFLAGS = DEVICE 
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx_spifi.ld'
 
     CPATH = ''
     LPATH = ''
diff --git a/bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.ld b/bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.ld
new file mode 100644
index 0000000000..faf766b1ff
--- /dev/null
+++ b/bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.ld
@@ -0,0 +1,133 @@
+/*
+ * linker script for LPC43xx SPIFI (4Mb NorFlash, 32kB SRAM ) with GNU ld
+ * yiyue.fang 2012-04-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x14000000, LENGTH = 0x00400000
+    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        KEEP(*(.interrupt_vector))      /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.sct b/bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.sct
new file mode 100644
index 0000000000..cd28b68815
--- /dev/null
+++ b/bsp/lpc43xx/M0/rtthread-lpc43xx_spifi.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x14000000 0x00400000  {    ; load region size_region
+  ER_ROM1 0x14000000 0x00400000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x10000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/lpc43xx/M4/rtconfig.py b/bsp/lpc43xx/M4/rtconfig.py
index d8c21c1dc8..b19c390160 100644
--- a/bsp/lpc43xx/M4/rtconfig.py
+++ b/bsp/lpc43xx/M4/rtconfig.py
@@ -53,7 +53,7 @@ if PLATFORM == 'gcc':
         DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
     CFLAGS = DEVICE 
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx_spifi.ld'
 
     CPATH = ''
     LPATH = ''
@@ -75,8 +75,8 @@ elif PLATFORM == 'armcc':
     TARGET_EXT = 'axf'
 
     DEVICE = ' --device DARMSTM'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
+    CFLAGS = DEVICE + ' --apcs=interwork '
+    AFLAGS = DEVICE 
     LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
 
     CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
diff --git a/bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.ld b/bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.ld
new file mode 100644
index 0000000000..faf766b1ff
--- /dev/null
+++ b/bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.ld
@@ -0,0 +1,133 @@
+/*
+ * linker script for LPC43xx SPIFI (4Mb NorFlash, 32kB SRAM ) with GNU ld
+ * yiyue.fang 2012-04-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x14000000, LENGTH = 0x00400000
+    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        KEEP(*(.interrupt_vector))      /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.sct b/bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.sct
new file mode 100644
index 0000000000..cd28b68815
--- /dev/null
+++ b/bsp/lpc43xx/M4/rtthread-lpc43xx_spifi.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x14000000 0x00400000  {    ; load region size_region
+  ER_ROM1 0x14000000 0x00400000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x10000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

From 000daf03e2e80e71b9402166c940d591696730f4 Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@gmail.com>
Date: Tue, 15 Jul 2014 15:50:58 +0800
Subject: [PATCH 47/86] xplorer4330:update the startup code.

---
 .../Source/Templates/ARM/startup_LPC43xx.s    |  12 -
 .../Source/Templates/GCC/cr_startup_lpc43xx.c | 502 ------------------
 .../Templates/GCC/cr_startup_lpc43xx_m0sub.c  | 464 ----------------
 .../Source/Templates/GCC/startup_LPC43xx.s    | 266 ++++++++++
 .../Source/Templates/GCC/startup_LPC43xx_M0.s | 266 ++++++++++
 .../Source/Templates/IAR/startup_LPC43xx_M0.s | 242 +++++++++
 .../LPC43xx/Source/Templates/system_LPC43xx.c |   6 +-
 bsp/xplorer4330/Libraries/Device/SConscript   |   8 +-
 8 files changed, 779 insertions(+), 987 deletions(-)
 delete mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
 delete mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s
 create mode 100644 bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s

diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
index 8514f36120..d41d7813a2 100644
--- a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
@@ -128,10 +128,6 @@ __Vectors       DCD     __initial_sp              ; 0 Top of Stack
                 DCD     QEI_IRQHandler            ; 68 QEI
 
 
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
 
                 AREA    |.text|, CODE, READONLY
 
@@ -327,13 +323,5 @@ __user_initial_stackheap
 
                 ENDIF
 
-                AREA    |.text|,CODE, READONLY
-getPC           PROC
-                EXPORT  getPC
-
-                MOV     R0,LR
-                BX      LR
-
-                ENDP
 
                 END
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
deleted file mode 100644
index 5dd22339f8..0000000000
--- a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
+++ /dev/null
@@ -1,502 +0,0 @@
-//*****************************************************************************
-// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
-//
-// Version : 140113
-//*****************************************************************************
-//
-// Copyright(C) NXP Semiconductors, 2013-2014
-// All rights reserved.
-//
-// Software that is described herein is for illustrative purposes only
-// which provides customers with programming information regarding the
-// LPC products.  This software is supplied "AS IS" without any warranties of
-// any kind, and NXP Semiconductors and its licensor disclaim any and
-// all warranties, express or implied, including all implied warranties of
-// merchantability, fitness for a particular purpose and non-infringement of
-// intellectual property rights.  NXP Semiconductors assumes no responsibility
-// or liability for the use of the software, conveys no license or rights under any
-// patent, copyright, mask work right, or any other intellectual property rights in
-// or to any products. NXP Semiconductors reserves the right to make changes
-// in the software without notification. NXP Semiconductors also makes no
-// representation or warranty that such application will be suitable for the
-// specified use without further testing or modification.
-//
-// Permission to use, copy, modify, and distribute this software and its
-// documentation is hereby granted, under NXP Semiconductors' and its
-// licensor's relevant copyrights in the software, without fee, provided that it
-// is used in conjunction with NXP Semiconductors microcontrollers.  This
-// copyright, permission, and disclaimer notice must appear in all copies of
-// this code.
-//*****************************************************************************
-
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-    extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
-// Declaration of external SystemInit function
-extern void SystemInit(void);
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-void ResetISR(void);
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void MemManage_Handler(void);
-WEAK void BusFault_Handler(void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void DebugMon_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take
-// precedence over these weak definitions
-//
-//*****************************************************************************
-void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
-#if defined (__USE_LPCOPEN)
-void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
-#endif
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
-#if defined (__USE_LPCOPEN)
-void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
-#endif
-void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-    // Core Level - CM4
-    &_vStackTop,                    // The initial stack pointer
-    ResetISR,                       // The reset handler
-    NMI_Handler,                    // The NMI handler
-    HardFault_Handler,              // The hard fault handler
-    MemManage_Handler,              // The MPU fault handler
-    BusFault_Handler,               // The bus fault handler
-    UsageFault_Handler,             // The usage fault handler
-    0,                              // Reserved
-    0,                              // Reserved
-    0,                              // Reserved
-    0,                              // Reserved
-    SVC_Handler,                    // SVCall handler
-    DebugMon_Handler,               // Debug monitor handler
-    0,                              // Reserved
-    PendSV_Handler,                 // The PendSV handler
-    SysTick_Handler,                // The SysTick handler
-
-    // Chip Level - LPC43 (M4)
-    DAC_IRQHandler,           // 16
-#if defined (__USE_LPCOPEN)
-    M0APP_IRQHandler,        // 17 CortexM4/M0 (LPC43XX ONLY)
-#else
-    M0CORE_IRQHandler,        // 17
-#endif
-    DMA_IRQHandler,           // 18
-    0,           // 19
-    FLASH_EEPROM_IRQHandler,   // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
-    ETH_IRQHandler,           // 21
-    SDIO_IRQHandler,          // 22
-    LCD_IRQHandler,           // 23
-    USB0_IRQHandler,          // 24
-    USB1_IRQHandler,          // 25
-    SCT_IRQHandler,           // 26
-    RIT_IRQHandler,           // 27
-    TIMER0_IRQHandler,        // 28
-    TIMER1_IRQHandler,        // 29
-    TIMER2_IRQHandler,        // 30
-    TIMER3_IRQHandler,        // 31
-    MCPWM_IRQHandler,         // 32
-    ADC0_IRQHandler,          // 33
-    I2C0_IRQHandler,          // 34
-    I2C1_IRQHandler,          // 35
-    SPI_IRQHandler,           // 36
-    ADC1_IRQHandler,          // 37
-    SSP0_IRQHandler,          // 38
-    SSP1_IRQHandler,          // 39
-    UART0_IRQHandler,         // 40
-    UART1_IRQHandler,         // 41
-    UART2_IRQHandler,         // 42
-    UART3_IRQHandler,         // 43
-    I2S0_IRQHandler,          // 44
-    I2S1_IRQHandler,          // 45
-    SPIFI_IRQHandler,         // 46
-    SGPIO_IRQHandler,         // 47
-    GPIO0_IRQHandler,         // 48
-    GPIO1_IRQHandler,         // 49
-    GPIO2_IRQHandler,         // 50
-    GPIO3_IRQHandler,         // 51
-    GPIO4_IRQHandler,         // 52
-    GPIO5_IRQHandler,         // 53
-    GPIO6_IRQHandler,         // 54
-    GPIO7_IRQHandler,         // 55
-    GINT0_IRQHandler,         // 56
-    GINT1_IRQHandler,         // 57
-    EVRT_IRQHandler,          // 58
-    CAN1_IRQHandler,          // 59
-    0,                        // 60
-#if defined (__USE_LPCOPEN)
-    ADCHS_IRQHandler,         // 61 ADCHS combined interrupt
-#else
-    VADC_IRQHandler,          // 61
-#endif
-    ATIMER_IRQHandler,        // 62
-    RTC_IRQHandler,           // 63
-    0,                        // 64
-    WDT_IRQHandler,           // 65
-    M0SUB_IRQHandler,         // 66
-    CAN0_IRQHandler,          // 67
-    QEI_IRQHandler,           // 68
-};
-
-
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-        __attribute__((section(".after_vectors"
-)))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int *pulSrc = (unsigned int*) romstart;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4)
-        *pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4)
-        *pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//
-//*****************************************************************************
-void ResetISR(void) {
-
-// *************************************************************
-// The following conditional block of code manually resets as
-// much of the peripheral set of the LPC43 as possible. This is
-// done because the LPC43 does not provide a means of triggering
-// a full system reset under debugger control, which can cause
-// problems in certain circumstances when debugging.
-//
-// You can prevent this code block being included if you require
-// (for example when creating a final executable which you will
-// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
-//
-#ifndef DONT_RESET_ON_RESTART
-
-    // Disable interrupts
-    __asm volatile ("cpsid i");
-    // equivalent to CMSIS '__disable_irq()' function
-
-    unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
-    // LPC_RGU->RESET_CTRL0 @ 0x40053100
-    // LPC_RGU->RESET_CTRL1 @ 0x40053104
-    // Note that we do not use the CMSIS register access mechanism,
-    // as there is no guarantee that the project has been configured
-    // to use CMSIS.
-
-    // Write to LPC_RGU->RESET_CTRL0
-    *(RESET_CONTROL + 0) = 0x10DF1000;
-    // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
-    // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
-
-    // Write to LPC_RGU->RESET_CTRL1
-    *(RESET_CONTROL + 1) = 0x01DFF7FF;
-    // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
-    // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
-    // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
-    // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
-
-    // Clear all pending interrupts in the NVIC
-    volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
-    unsigned int irqpendloop;
-    for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
-        *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
-    }
-
-    // Reenable interrupts
-    __asm volatile ("cpsie i");
-    // equivalent to CMSIS '__enable_irq()' function
-
-#endif  // ifndef DONT_RESET_ON_RESTART
-// *************************************************************
-
-#if defined (__USE_LPCOPEN)
-    SystemInit();
-#endif
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-    unsigned int LoadAddr, ExeAddr, SectionLen;
-    unsigned int *SectionTableAddr;
-
-    // Load base address of Global Section Table
-    SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-    while (SectionTableAddr < &__data_section_table_end) {
-        LoadAddr = *SectionTableAddr++;
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        data_init(LoadAddr, ExeAddr, SectionLen);
-    }
-    // At this point, SectionTableAddr = &__bss_section_table;
-    // Zero fill the bss segment
-    while (SectionTableAddr < &__bss_section_table_end) {
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        bss_init(ExeAddr, SectionLen);
-    }
-
-#if !defined (__USE_LPCOPEN)
-// LPCOpen init code deals with FP and VTOR initialisation
-#if defined (__VFP_FP__) && !defined (__SOFTFP__)
-    /*
-     * Code to enable the Cortex-M4 FPU only included
-     * if appropriate build options have been selected.
-     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
-     */
-    // CPACR is located at address 0xE000ED88
-    asm("LDR.W R0, =0xE000ED88");
-    // Read CPACR
-    asm("LDR R1, [R0]");
-    // Set bits 20-23 to enable CP10 and CP11 coprocessors
-    asm(" ORR R1, R1, #(0xF << 20)");
-    // Write back the modified value to the CPACR
-    asm("STR R1, [R0]");
-#endif // (__VFP_FP__) && !(__SOFTFP__)
-    // ******************************
-    // Check to see if we are running the code from a non-zero
-    // address (eg RAM, external flash), in which case we need
-    // to modify the VTOR register to tell the CPU that the
-    // vector table is located at a non-0x0 address.
-
-    // Note that we do not use the CMSIS register access mechanism,
-    // as there is no guarantee that the project has been configured
-    // to use CMSIS.
-    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
-    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
-        // CMSIS : SCB->VTOR = <address of vector table>
-        *pSCB_VTOR = (unsigned int) g_pfnVectors;
-    }
-#endif
-
-#if defined (__USE_CMSIS)
-    SystemInit();
-#endif
-
-#if defined (__cplusplus)
-    //
-    // Call C++ library initialisation
-    //
-    __libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-    // Call the Redlib library, which in turn calls main()
-    __main();
-#else
-    main();
-#endif
-
-    //
-    // main() shouldn't return, but if it does, we'll just enter an infinite loop
-    //
-    while (1) {
-        ;
-    }
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void NMI_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void HardFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void MemManage_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void BusFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void UsageFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SVC_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void DebugMon_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void PendSV_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SysTick_Handler(void) {
-    while (1) {
-    }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void IntDefaultHandler(void) {
-    while (1) {
-    }
-}
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
deleted file mode 100644
index 33668ef37d..0000000000
--- a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
+++ /dev/null
@@ -1,464 +0,0 @@
-//*****************************************************************************
-// LPC43xx (Cortex M0 SUB) Startup code for use with LPCXpresso IDE
-//
-// Version : 131115
-//*****************************************************************************
-//
-// Copyright(C) NXP Semiconductors, 2013
-// All rights reserved.
-//
-// Software that is described herein is for illustrative purposes only
-// which provides customers with programming information regarding the
-// LPC products.  This software is supplied "AS IS" without any warranties of
-// any kind, and NXP Semiconductors and its licensor disclaim any and
-// all warranties, express or implied, including all implied warranties of
-// merchantability, fitness for a particular purpose and non-infringement of
-// intellectual property rights.  NXP Semiconductors assumes no responsibility
-// or liability for the use of the software, conveys no license or rights under any
-// patent, copyright, mask work right, or any other intellectual property rights in
-// or to any products. NXP Semiconductors reserves the right to make changes
-// in the software without notification. NXP Semiconductors also makes no
-// representation or warranty that such application will be suitable for the
-// specified use without further testing or modification.
-//
-// Permission to use, copy, modify, and distribute this software and its
-// documentation is hereby granted, under NXP Semiconductors' and its
-// licensor's relevant copyrights in the software, without fee, provided that it
-// is used in conjunction with NXP Semiconductors microcontrollers.  This
-// copyright, permission, and disclaimer notice must appear in all copies of
-// this code.
-//*****************************************************************************
-
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-  extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
-void SystemInit(void);
-#endif
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-     void ResetISR(void);
-#if defined (__USE_LPCOPEN)
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-#else
-WEAK void M0S_NMI_Handler(void);
-WEAK void M0S_HardFault_Handler(void);
-WEAK void M0S_DebugMon_Handler(void);
-WEAK void M0S_SVC_Handler(void);
-WEAK void M0S_PendSV_Handler(void);
-WEAK void M0S_SysTick_Handler(void);
-WEAK void M0S_IntDefaultHandler(void);
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take
-// precedence over these weak definitions
-//
-//*****************************************************************************
-#if defined (__USE_LPCOPEN)
-void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_INPUT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_MATCH_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_SHIFT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_POS_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S0_I2S1_QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPIFI_ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void M0S_DAC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_M4CORE_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_DMA_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_INPUT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_MATCH_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_SHIFT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SGPIO_POS_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USB0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USB1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SCT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_RITIMER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_GINT1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_TIMER1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_TIMER2_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_PIN_INT5_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_ADC0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_MCPWM_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_I2C0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_I2C1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SPI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_ADC1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SSP0_OR_SSP1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_EVENTROUTER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USART0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_UART1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USART2_OR_C_CAN1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_USART3_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_C_CAN0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_SPIFI_OR_VADC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-void M0S_M0APP_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
-#endif
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-
-#if defined (__USE_LPCOPEN)
-    // Core Level - CM0
-    &_vStackTop,                        // The initial stack pointer
-    ResetISR,                           // 1 The reset handler
-    NMI_Handler,                    // The NMI handler
-    HardFault_Handler,              // The hard fault handler
-    0,                                  // 4 Reserved
-    0,                                  // 5 Reserved
-    0,                                  // 6 Reserved
-    0,                                  // 7 Reserved
-    0,                                  // 8 Reserved
-    0,                                  // 9 Reserved
-    0,                                  // 10 Reserved
-    SVC_Handler,                    // SVCall handler
-    0,                              // Reserved
-    0,                              // Reserved
-    PendSV_Handler,                 // The PendSV handler
-    SysTick_Handler,                // The SysTick handler
-
-    // Chip Level - 43xx M0SUB core
-    DAC_IRQHandler,                 // 16
-    M4_IRQHandler,             // 17 Interrupt from M4 Core
-    DMA_IRQHandler,                 // 18 General Purpose DMA
-    0,                              // 19 Reserved
-    SGPIO_INPUT_IRQHandler,         // 20
-    SGPIO_MATCH_IRQHandler,         // 21
-    SGPIO_SHIFT_IRQHandler,         // 22
-    SGPIO_POS_IRQHandler,           // 23
-    USB0_IRQHandler,                // 24 USB0
-    USB1_IRQHandler,                // 25 USB1
-    SCT_IRQHandler ,                // 26 State Configurable Timer
-    RIT_IRQHandler,                 // 27 Repetitive Interrupt Timer
-    GINT1_IRQHandler,               // 28 GINT1
-    TIMER1_IRQHandler,              // 29 Timer1
-    TIMER2_IRQHandler,              // 30 Timer2
-    GPIO5_IRQHandler,               // 31
-    MCPWM_IRQHandler,               // 32 Motor Control PWM
-    ADC0_IRQHandler,                // 33 ADC0
-    I2C0_IRQHandler,                // 34
-    I2C1_IRQHandler,                // 35
-    SPI_IRQHandler,                 // 36
-    ADC1_IRQHandler,                // 37
-    SSP0_SSP1_IRQHandler,           // 38
-    EVRT_IRQHandler,                // 39 Event Router
-    UART0_IRQHandler,               // 41 USART0
-    UART1_IRQHandler,               // 41 UART1
-    UART2_CAN1_IRQHandler,          // 42 USART2 or C CAN1
-    UART3_IRQHandler,               // 43 USART3
-    I2S0_I2S1_QEI_IRQHandler,       // 35 I2C0 or I2C1 or I2S1 or QEI
-    CAN0_IRQHandler,                // 45 C CAN0
-    SPIFI_ADCHS_IRQHandler,         // 46
-    M0APP_IRQHandler,               // 47 Interrupt from M0APP
-  };
-#else
-    // Core Level - CM0
-    &_vStackTop,                        // The initial stack pointer
-    ResetISR,                           // 1 The reset handler
-    M0S_NMI_Handler,                    // 2 The NMI handler
-    M0S_HardFault_Handler,              // 3 The hard fault handler
-    0,                                  // 4 Reserved
-    0,                                  // 5 Reserved
-    0,                                  // 6 Reserved
-    0,                                  // 7 Reserved
-    0,                                  // 8 Reserved
-    0,                                  // 9 Reserved
-    0,                                  // 10 Reserved
-    M0S_SVC_Handler,                    // 11 SVCall handler
-    M0S_DebugMon_Handler,               // 12 Debug monitor handler
-    0,                                  // 13 Reserved
-    M0S_PendSV_Handler,                 // 14 The PendSV handler
-    M0S_SysTick_Handler,                // 15 The SysTick handler
-
-    // Chip Level - LPC43 (CM0 SUB)
-    M0S_DAC_IRQHandler,                 // 16
-    M0S_M4CORE_IRQHandler,              // 17 Interrupt from M4 Core
-    M0S_DMA_IRQHandler,                 // 18 General Purpose DMA
-    0,                                  // 19 Reserved
-    M0S_SGPIO_INPUT_IRQHandler,         // 20
-    M0S_SGPIO_MATCH_IRQHandler,         // 21
-    M0S_SGPIO_SHIFT_IRQHandler,         // 22
-    M0S_SGPIO_POS_IRQHandler,           // 23
-    M0S_USB0_IRQHandler,                // 24 USB0
-    M0S_USB1_IRQHandler,                // 25 USB1
-    M0S_SCT_IRQHandler ,                // 26 State Configurable Timer
-    M0S_RITIMER_IRQHandler,             // 27 Repetitive Interrupt Timer
-    M0S_GINT1_IRQHandler,               // 28 GINT1
-    M0S_TIMER1_IRQHandler,              // 29 Timer1
-    M0S_TIMER2_IRQHandler,              // 30 Timer2
-    M0S_PIN_INT5_IRQHandler,            // 31
-    M0S_MCPWM_IRQHandler,               // 32 Motor Control PWM
-    M0S_ADC0_IRQHandler,                // 33 ADC0
-    M0S_I2C0_IRQHandler,                // 34
-    M0S_I2C1_IRQHandler,                // 35
-    M0S_SPI_IRQHandler,                 // 36
-    M0S_ADC1_IRQHandler,                // 37
-    M0S_SSP0_OR_SSP1_IRQHandler,        // 38
-    M0S_EVENTROUTER_IRQHandler,         // 39 Event Router
-    M0S_USART0_IRQHandler,              // 41 USART0
-    M0S_UART1_IRQHandler,               // 41 UART1
-    M0S_USART2_OR_C_CAN1_IRQHandler,    // 42 USART2 or C CAN1
-    M0S_USART3_IRQHandler,              // 43 USART3
-    M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler,
-                                        // 35 I2C0 or I2C1 or I2S1 or QEI
-    M0S_C_CAN0_IRQHandler,              // 45 C CAN0
-    M0S_SPIFI_OR_VADC_IRQHandler,       // 46
-    M0S_M0APP_IRQHandler,               // 47 Interrupt from M0APP
-  };
-#endif
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-  unsigned int *pulDest = (unsigned int*) start;
-  unsigned int *pulSrc = (unsigned int*) romstart;
-  unsigned int loop;
-  for (loop = 0; loop < len; loop = loop + 4)
-    *pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-  unsigned int *pulDest = (unsigned int*) start;
-  unsigned int loop;
-  for (loop = 0; loop < len; loop = loop + 4)
-    *pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//
-//*****************************************************************************
-void
-ResetISR(void) {
-
-  // ******************************
-  // Modify CREG->M0SUBMEMMAP so that M0 looks in correct place
-  // for its vector table when an exception is triggered.
-  // Note that we do not use the CMSIS register access mechanism,
-  // as there is no guarantee that the project has been configured
-  // to use CMSIS.
-  unsigned int *pCREG_M0SUBMEMMAP = (unsigned int *) 0x40043308;
-  // CMSIS : CREG->M0SUBMEMMAP = <address of vector table>
-  *pCREG_M0SUBMEMMAP = (unsigned int)g_pfnVectors;
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-  unsigned int LoadAddr, ExeAddr, SectionLen;
-  unsigned int *SectionTableAddr;
-
-  // Load base address of Global Section Table
-  SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-  while (SectionTableAddr < &__data_section_table_end) {
-    LoadAddr = *SectionTableAddr++;
-    ExeAddr = *SectionTableAddr++;
-    SectionLen = *SectionTableAddr++;
-    data_init(LoadAddr, ExeAddr, SectionLen);
-  }
-  // At this point, SectionTableAddr = &__bss_section_table;
-  // Zero fill the bss segment
-  while (SectionTableAddr < &__bss_section_table_end) {
-    ExeAddr = *SectionTableAddr++;
-    SectionLen = *SectionTableAddr++;
-    bss_init(ExeAddr, SectionLen);
-  }
-
-// **********************************************************
-// No need to call SystemInit() here, as master CM4 cpu will
-// have done the main system set up before enabling CM0.
-// **********************************************************
-
-#if defined (__cplusplus)
-  //
-  // Call C++ library initialisation
-  //
-  __libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-  // Call the Redlib library, which in turn calls main()
-  __main() ;
-#else
-  main();
-#endif
-
-  //
-  // main() shouldn't return, but if it does, we'll just enter an infinite loop
-  //
-  while (1) {
-    ;
-  }
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void NMI_Handler(void)
-#else
-void M0S_NMI_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void HardFault_Handler(void)
-#else
-void M0S_HardFault_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void SVC_Handler(void)
-#else
-void M0S_SVC_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void PendSV_Handler(void)
-#else
-void M0S_PendSV_Handler(void)
-#endif
-{   while(1) { }
-}
-
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void SysTick_Handler(void)
-#else
-void M0S_SysTick_Handler(void)
-#endif
-{   while(1) { }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-#if defined (__USE_LPCOPEN)
-void IntDefaultHandler(void)
-#else
-void M0S_IntDefaultHandler(void)
-#endif
-{   while(1) { }
-}
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
new file mode 100644
index 0000000000..179be6ef25
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
@@ -0,0 +1,266 @@
+/*****************************************************************************/
+/* startup_LPC43xx.s: Startup file for LPC43xx device series                 */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+	.syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+	
+	.word  _sidata
+	.word  _sdata
+	.word  _edata
+	.word  _sbss
+	.word  _ebss
+
+
+    .equ    Sign_Value, 0x5A5A5A5A
+
+/* Vector Table */
+
+    .section ".interrupt_vector"
+    .globl  __interrupt_vector
+    .type   __interrupt_vector, %function
+
+__interrupt_vector:
+    .long   _estack                 /* Top of Stack                 */
+    .long   Reset_Handler               /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   Sign_Value                  /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+/* External Interrupts */
+    .long   DAC_IRQHandler              /* 16 D/A Converter             */
+    .long   M0CORE_IRQHandler           /* 17 M0 Core                   */
+    .long   DMA_IRQHandler              /* 18 General Purpose DMA       */
+    .long   EZH_IRQHandler              /* 19 EZH/EDM                   */
+    .long   FLASH_EEPROM_IRQHandler     /* 20 Reserved for Typhoon      */
+    .long   ETH_IRQHandler              /* 21 Ethernet                  */
+    .long   SDIO_IRQHandler             /* 22 SD/MMC                    */
+    .long   LCD_IRQHandler              /* 23 LCD                       */
+    .long   USB0_IRQHandler             /* 24 USB0                      */
+    .long   USB1_IRQHandler             /* 25 USB1                      */
+    .long   SCT_IRQHandler              /* 26 State Configurable Timer  */
+    .long   RIT_IRQHandler              /* 27 Repetitive Interrupt Timer*/
+    .long   TIMER0_IRQHandler           /* 28 Timer0                    */
+    .long   TIMER1_IRQHandler           /* 29 Timer1                    */
+    .long   TIMER2_IRQHandler           /* 30 Timer2                    */
+    .long   TIMER3_IRQHandler           /* 31 Timer3                    */
+    .long   MCPWM_IRQHandler            /* 32 Motor Control PWM         */
+    .long   ADC0_IRQHandler             /* 33 A/D Converter 0           */
+    .long   I2C0_IRQHandler             /* 34 I2C0                      */
+    .long   I2C1_IRQHandler             /* 35 I2C1                      */
+    .long   SPI_IRQHandler              /* 36 SPI                       */
+    .long   ADC1_IRQHandler             /* 37 A/D Converter 1           */
+    .long   SSP0_IRQHandler             /* 38 SSP0                      */
+    .long   SSP1_IRQHandler             /* 39 SSP1                      */
+    .long   UART0_IRQHandler            /* 40 UART0                     */
+    .long   UART1_IRQHandler            /* 41 UART1                     */
+    .long   UART2_IRQHandler            /* 42 UART2                     */
+    .long   UART3_IRQHandler            /* 43 UART3                     */
+    .long   I2S0_IRQHandler             /* 44 I2S0                      */
+    .long   I2S1_IRQHandler             /* 45 I2S1                      */
+    .long   SPIFI_IRQHandler            /* 46 SPI Flash Interface       */
+    .long   SGPIO_IRQHandler            /* 47 SGPIO                     */
+    .long   GPIO0_IRQHandler            /* 48 GPIO0                     */
+    .long   GPIO1_IRQHandler            /* 49 GPIO1                     */
+    .long   GPIO2_IRQHandler            /* 50 GPIO2                     */
+    .long   GPIO3_IRQHandler            /* 51 GPIO3                     */
+    .long   GPIO4_IRQHandler            /* 52 GPIO4                     */
+    .long   GPIO5_IRQHandler            /* 53 GPIO5                     */
+    .long   GPIO6_IRQHandler            /* 54 GPIO6                     */
+    .long   GPIO7_IRQHandler            /* 55 GPIO7                     */
+    .long   GINT0_IRQHandler            /* 56 GINT0                     */
+    .long   GINT1_IRQHandler            /* 57 GINT1                     */
+    .long   EVRT_IRQHandler             /* 58 Event Router              */
+    .long   CAN1_IRQHandler             /* 59 C_CAN1                    */
+    .long   0                           /* 60 Reserved                  */
+    .long   VADC_IRQHandler             /* 61 VADC                      */
+    .long   ATIMER_IRQHandler           /* 62 ATIMER                    */
+    .long   RTC_IRQHandler              /* 63 RTC                       */
+    .long   0                           /* 64 Reserved                  */
+    .long   WDT_IRQHandler              /* 65 WDT                       */
+    .long   M0s_IRQHandler              /* 66 M0s                       */
+    .long   CAN0_IRQHandler             /* 67 C_CAN0                    */
+    .long   QEI_IRQHandler              /* 68 QEI                       */
+
+    .size   __interrupt_vector, . - __interrupt_vector
+
+
+    .thumb
+
+
+/* Reset Handler */
+    .section  .text.Reset_Handler
+	.weak  Reset_Handler
+	.type  Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+.ifdef RAM_MODE
+/* Clear .bss section (Zero init) */
+	mov     R0, #0
+	ldr     R1, =__bss_start__
+	ldr    R2, =__bss_end__
+	cmp     R1,R2
+	beq     BSSIsEmpty
+LoopZI:
+    cmp     R1, R2
+    bhs     BSSIsEmpty
+    str     R0, [R1]
+    add     R1, #4
+    blo     LoopZI
+BSSIsEmpty:
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.else
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.endif
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ    DAC_IRQHandler
+    IRQ    M0CORE_IRQHandler
+    IRQ    DMA_IRQHandler
+    IRQ    EZH_IRQHandler
+    IRQ    FLASH_EEPROM_IRQHandler
+    IRQ    ETH_IRQHandler
+    IRQ    SDIO_IRQHandler
+    IRQ    LCD_IRQHandler
+    IRQ    USB0_IRQHandler
+    IRQ    USB1_IRQHandler
+    IRQ    SCT_IRQHandler
+    IRQ    RIT_IRQHandler
+    IRQ    TIMER0_IRQHandler
+    IRQ    TIMER1_IRQHandler
+    IRQ    TIMER2_IRQHandler
+    IRQ    TIMER3_IRQHandler
+    IRQ    MCPWM_IRQHandler
+    IRQ    ADC0_IRQHandler
+    IRQ    I2C0_IRQHandler
+    IRQ    I2C1_IRQHandler
+    IRQ    SPI_IRQHandler
+    IRQ    ADC1_IRQHandler
+    IRQ    SSP0_IRQHandler
+    IRQ    SSP1_IRQHandler
+    IRQ    UART0_IRQHandler
+    IRQ    UART1_IRQHandler
+    IRQ    UART2_IRQHandler
+    IRQ    UART3_IRQHandler
+    IRQ    I2S0_IRQHandler
+    IRQ    I2S1_IRQHandler
+    IRQ    SPIFI_IRQHandler
+    IRQ    SGPIO_IRQHandler
+    IRQ    GPIO0_IRQHandler
+    IRQ    GPIO1_IRQHandler
+    IRQ    GPIO2_IRQHandler
+    IRQ    GPIO3_IRQHandler
+    IRQ    GPIO4_IRQHandler
+    IRQ    GPIO5_IRQHandler
+    IRQ    GPIO6_IRQHandler
+    IRQ    GPIO7_IRQHandler
+    IRQ    GINT0_IRQHandler
+    IRQ    GINT1_IRQHandler
+    IRQ    EVRT_IRQHandler
+    IRQ    CAN1_IRQHandler
+    IRQ    VADC_IRQHandler
+    IRQ    ATIMER_IRQHandler
+    IRQ    RTC_IRQHandler
+    IRQ    WDT_IRQHandler
+    IRQ    M0s_IRQHandler
+    IRQ    CAN0_IRQHandler
+    IRQ    QEI_IRQHandler
+
+    .end
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s
new file mode 100644
index 0000000000..5a7b26405d
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s
@@ -0,0 +1,266 @@
+/*****************************************************************************/
+/* startup_LPC43xx.s: Startup file for LPC43xx device series                 */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+	.syntax unified
+	.cpu cortex-m0
+	.fpu softvfp
+	.thumb
+	
+	.word  _sidata
+	.word  _sdata
+	.word  _edata
+	.word  _sbss
+	.word  _ebss
+
+
+    .equ    Sign_Value, 0x5A5A5A5A
+
+/* Vector Table */
+
+    .section ".interrupt_vector"
+    .globl  __interrupt_vector
+    .type   __interrupt_vector, %function
+
+__interrupt_vector:
+    .long   _estack                 /* Top of Stack                 */
+    .long   Reset_Handler               /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   Sign_Value                  /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+/* External Interrupts */
+    .long   DAC_IRQHandler              /* 16 D/A Converter             */
+    .long   M4CORE_IRQHandler           /* 17 M0 Core                   */
+    .long   DMA_IRQHandler              /* 18 General Purpose DMA       */
+    .long   EZH_IRQHandler              /* 19 EZH/EDM                   */
+    .long   FLASH_EEPROM_IRQHandler     /* 20 Reserved for Typhoon      */
+    .long   ETH_IRQHandler              /* 21 Ethernet                  */
+    .long   SDIO_IRQHandler             /* 22 SD/MMC                    */
+    .long   LCD_IRQHandler              /* 23 LCD                       */
+    .long   USB0_IRQHandler             /* 24 USB0                      */
+    .long   USB1_IRQHandler             /* 25 USB1                      */
+    .long   SCT_IRQHandler              /* 26 State Configurable Timer  */
+    .long   RIT_IRQHandler              /* 27 Repetitive Interrupt Timer*/
+    .long   TIMER0_IRQHandler           /* 28 Timer0                    */
+    .long   TIMER1_IRQHandler           /* 29 Timer1                    */
+    .long   TIMER2_IRQHandler           /* 30 Timer2                    */
+    .long   TIMER3_IRQHandler           /* 31 Timer3                    */
+    .long   MCPWM_IRQHandler            /* 32 Motor Control PWM         */
+    .long   ADC0_IRQHandler             /* 33 A/D Converter 0           */
+    .long   I2C0_IRQHandler             /* 34 I2C0                      */
+    .long   I2C1_IRQHandler             /* 35 I2C1                      */
+    .long   SPI_IRQHandler              /* 36 SPI                       */
+    .long   ADC1_IRQHandler             /* 37 A/D Converter 1           */
+    .long   SSP0_IRQHandler             /* 38 SSP0                      */
+    .long   SSP1_IRQHandler             /* 39 SSP1                      */
+    .long   UART0_IRQHandler            /* 40 UART0                     */
+    .long   UART1_IRQHandler            /* 41 UART1                     */
+    .long   UART2_IRQHandler            /* 42 UART2                     */
+    .long   UART3_IRQHandler            /* 43 UART3                     */
+    .long   I2S0_IRQHandler             /* 44 I2S0                      */
+    .long   I2S1_IRQHandler             /* 45 I2S1                      */
+    .long   SPIFI_IRQHandler            /* 46 SPI Flash Interface       */
+    .long   SGPIO_IRQHandler            /* 47 SGPIO                     */
+    .long   GPIO0_IRQHandler            /* 48 GPIO0                     */
+    .long   GPIO1_IRQHandler            /* 49 GPIO1                     */
+    .long   GPIO2_IRQHandler            /* 50 GPIO2                     */
+    .long   GPIO3_IRQHandler            /* 51 GPIO3                     */
+    .long   GPIO4_IRQHandler            /* 52 GPIO4                     */
+    .long   GPIO5_IRQHandler            /* 53 GPIO5                     */
+    .long   GPIO6_IRQHandler            /* 54 GPIO6                     */
+    .long   GPIO7_IRQHandler            /* 55 GPIO7                     */
+    .long   GINT0_IRQHandler            /* 56 GINT0                     */
+    .long   GINT1_IRQHandler            /* 57 GINT1                     */
+    .long   EVRT_IRQHandler             /* 58 Event Router              */
+    .long   CAN1_IRQHandler             /* 59 C_CAN1                    */
+    .long   0                           /* 60 Reserved                  */
+    .long   VADC_IRQHandler             /* 61 VADC                      */
+    .long   ATIMER_IRQHandler           /* 62 ATIMER                    */
+    .long   RTC_IRQHandler              /* 63 RTC                       */
+    .long   0                           /* 64 Reserved                  */
+    .long   WDT_IRQHandler              /* 65 WDT                       */
+    .long   M0s_IRQHandler              /* 66 M0s                       */
+    .long   CAN0_IRQHandler             /* 67 C_CAN0                    */
+    .long   QEI_IRQHandler              /* 68 QEI                       */
+
+    .size   __interrupt_vector, . - __interrupt_vector
+
+
+    .thumb
+
+
+/* Reset Handler */
+    .section  .text.Reset_Handler
+	.weak  Reset_Handler
+	.type  Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+.ifdef RAM_MODE
+/* Clear .bss section (Zero init) */
+	mov     R0, #0
+	ldr     R1, =__bss_start__
+	ldr    R2, =__bss_end__
+	cmp     R1,R2
+	beq     BSSIsEmpty
+LoopZI:
+    cmp     R1, R2
+    bhs     BSSIsEmpty
+    str     R0, [R1]
+    add     R1, #4
+    blo     LoopZI
+BSSIsEmpty:
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.else
+    ldr     R0, =SystemInit
+    blx     R0
+    ldr     R0,=main
+    bx      R0
+.endif
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ    DAC_IRQHandler
+    IRQ    M0CORE_IRQHandler
+    IRQ    DMA_IRQHandler
+    IRQ    EZH_IRQHandler
+    IRQ    FLASH_EEPROM_IRQHandler
+    IRQ    ETH_IRQHandler
+    IRQ    SDIO_IRQHandler
+    IRQ    LCD_IRQHandler
+    IRQ    USB0_IRQHandler
+    IRQ    USB1_IRQHandler
+    IRQ    SCT_IRQHandler
+    IRQ    RIT_IRQHandler
+    IRQ    TIMER0_IRQHandler
+    IRQ    TIMER1_IRQHandler
+    IRQ    TIMER2_IRQHandler
+    IRQ    TIMER3_IRQHandler
+    IRQ    MCPWM_IRQHandler
+    IRQ    ADC0_IRQHandler
+    IRQ    I2C0_IRQHandler
+    IRQ    I2C1_IRQHandler
+    IRQ    SPI_IRQHandler
+    IRQ    ADC1_IRQHandler
+    IRQ    SSP0_IRQHandler
+    IRQ    SSP1_IRQHandler
+    IRQ    UART0_IRQHandler
+    IRQ    UART1_IRQHandler
+    IRQ    UART2_IRQHandler
+    IRQ    UART3_IRQHandler
+    IRQ    I2S0_IRQHandler
+    IRQ    I2S1_IRQHandler
+    IRQ    SPIFI_IRQHandler
+    IRQ    SGPIO_IRQHandler
+    IRQ    GPIO0_IRQHandler
+    IRQ    GPIO1_IRQHandler
+    IRQ    GPIO2_IRQHandler
+    IRQ    GPIO3_IRQHandler
+    IRQ    GPIO4_IRQHandler
+    IRQ    GPIO5_IRQHandler
+    IRQ    GPIO6_IRQHandler
+    IRQ    GPIO7_IRQHandler
+    IRQ    GINT0_IRQHandler
+    IRQ    GINT1_IRQHandler
+    IRQ    EVRT_IRQHandler
+    IRQ    CAN1_IRQHandler
+    IRQ    VADC_IRQHandler
+    IRQ    ATIMER_IRQHandler
+    IRQ    RTC_IRQHandler
+    IRQ    WDT_IRQHandler
+    IRQ    M0s_IRQHandler
+    IRQ    CAN0_IRQHandler
+    IRQ    QEI_IRQHandler
+
+    .end
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s
new file mode 100644
index 0000000000..1954b91b7b
--- /dev/null
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s
@@ -0,0 +1,242 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start 
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+				
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+		DCD		DAC_IRQHandler
+		DCD		M4_IRQHandler
+		DCD		DMA_IRQHandler
+		DCD		0
+		DCD		SGPIO_INPUT_IRQHandler
+		DCD		SGPIO_MATCH_IRQHandler
+		DCD		SGPIO_SHIFT_IRQHandler
+		DCD		SGPIO_POS_IRQHandler
+		DCD		USB0_IRQHandler
+		DCD		USB1_IRQHandler
+		DCD		SCT_IRQHandler
+		DCD		RIT_IRQHandler
+		DCD		GINT1_IRQHandler
+		DCD		TIMER1_IRQHandler
+		DCD		TIMER2_IRQHandler
+		DCD		GPIO5_IRQHandler
+		DCD		MCPWM_IRQHandler
+		DCD		ADC0_IRQHandler
+		DCD		I2C0_IRQHandler
+		DCD		I2C1_IRQHandler
+		DCD		SPI_IRQHandler
+		DCD		ADC1_IRQHandler
+		DCD		SSP0_SSP1_IRQHandler
+		DCD		EVRT_IRQHandler
+		DCD		UART0_IRQHandler
+		DCD		UART1_IRQHandler
+		DCD		UART2_CAN1_IRQHandler
+		DCD		UART3_IRQHandler
+		DCD		I2S0_I2S1_QEI_IRQHandler
+		DCD		CAN0_IRQHandler
+		DCD		SPIFI_ADCHS_IRQHandler
+		DCD		M0APP_IRQHandler
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+		THUMB
+
+		PUBWEAK Reset_Handler
+		SECTION .text:CODE:REORDER(2)
+Reset_Handler
+		LDR     R0, =SystemInit
+		BLX     R0
+		LDR     R0, =__iar_program_start
+		BX      R0
+  
+		PUBWEAK NMI_Handler
+		PUBWEAK HardFault_Handler
+		PUBWEAK MemManage_Handler
+		PUBWEAK BusFault_Handler
+		PUBWEAK UsageFault_Handler
+		PUBWEAK SVC_Handler
+		PUBWEAK DebugMon_Handler
+		PUBWEAK PendSV_Handler
+		PUBWEAK SysTick_Handler
+
+		PUBWEAK DAC_IRQHandler
+		PUBWEAK M4_IRQHandler
+		PUBWEAK DMA_IRQHandler
+		PUBWEAK UnHandled_Vector
+		PUBWEAK SGPIO_INPUT_IRQHandler
+		PUBWEAK SGPIO_MATCH_IRQHandler
+		PUBWEAK SGPIO_SHIFT_IRQHandler
+		PUBWEAK SGPIO_POS_IRQHandler
+		PUBWEAK USB0_IRQHandler
+		PUBWEAK USB1_IRQHandler
+		PUBWEAK SCT_IRQHandler
+		PUBWEAK RIT_IRQHandler
+		PUBWEAK GINT1_IRQHandler
+		PUBWEAK TIMER1_IRQHandler
+		PUBWEAK TIMER2_IRQHandler
+		PUBWEAK GPIO5_IRQHandler
+		PUBWEAK MCPWM_IRQHandler
+		PUBWEAK ADC0_IRQHandler
+		PUBWEAK I2C0_IRQHandler
+		PUBWEAK I2C1_IRQHandler
+		PUBWEAK SPI_IRQHandler
+		PUBWEAK ADC1_IRQHandler
+		PUBWEAK SSP0_SSP1_IRQHandler
+		PUBWEAK EVRT_IRQHandler
+		PUBWEAK UART0_IRQHandler
+		PUBWEAK UART1_IRQHandler
+		PUBWEAK UART2_CAN1_IRQHandler
+		PUBWEAK UART3_IRQHandler
+		PUBWEAK I2S0_I2S1_QEI_IRQHandler
+		PUBWEAK CAN0_IRQHandler
+		PUBWEAK SPIFI_ADCHS_IRQHandler
+		PUBWEAK M0APP_IRQHandler
+
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B .
+SVC_Handler
+        B .
+DebugMon_Handler
+        B .
+PendSV_Handler
+        B .
+SysTick_Handler
+        B .
+HardFault_Handler
+        B .
+MemManage_Handler
+        B .
+BusFault_Handler
+        B .
+UsageFault_Handler
+DAC_IRQHandler
+M4_IRQHandler
+DMA_IRQHandler
+UnHandled_Vector
+SGPIO_INPUT_IRQHandler
+SGPIO_MATCH_IRQHandler
+SGPIO_SHIFT_IRQHandler
+SGPIO_POS_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+GINT1_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+GPIO5_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_SSP1_IRQHandler
+EVRT_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_CAN1_IRQHandler
+UART3_IRQHandler
+I2S0_I2S1_QEI_IRQHandler
+CAN0_IRQHandler
+SPIFI_ADCHS_IRQHandler
+M0APP_IRQHandler
+Default_IRQHandler
+        B .
+
+/* CRP Section - not needed for flashless devices */
+
+;;;        SECTION .crp:CODE:ROOT(2)
+;;;        DATA
+/* Code Read Protection
+NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+                   - Copy RAM to flash command can not write to Sector 0.
+                   - Erase command can erase Sector 0 only when all sectors
+                     are selected for erase.
+                   - Compare command is disabled.
+                   - Read Memory command is disabled.
+CRP2    0x87654321 - Read Memory is disabled.
+                   - Write to RAM is disabled.
+                   - "Go" command is disabled.
+                   - Copy RAM to flash is disabled.
+                   - Compare is disabled.
+CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+                     by pulling PIO0_1 LOW is disabled if a valid user code is
+                     present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+;;;	    DCD	0xFFFFFFFF
+;;;
+
+        END
diff --git a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
index 3bd76f5de6..c51bd1c67e 100644
--- a/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
+++ b/bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
@@ -863,7 +863,6 @@ void SystemCoreClockUpdate (void) {
 }
 
 
-extern uint32_t getPC (void);
 
 /*----------------------------------------------------------------------------
   Initialize the system
@@ -877,10 +876,7 @@ void SystemInit (void) {
 
   /* Disable SysTick timer                                                    */
   SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
-#ifdef CORE_M4
-  /* Set vector table pointer */
-  SCB->VTOR = getPC() & 0xFFF00000;
-#endif
+
   /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
   SetClock();
 
diff --git a/bsp/xplorer4330/Libraries/Device/SConscript b/bsp/xplorer4330/Libraries/Device/SConscript
index a6ea5ee936..47f7e04885 100644
--- a/bsp/xplorer4330/Libraries/Device/SConscript
+++ b/bsp/xplorer4330/Libraries/Device/SConscript
@@ -8,19 +8,19 @@ src = Split('''
 NXP/LPC43xx/Source/Templates/system_LPC43xx.c
 ''')
 CPPPATH = [cwd + '/NXP/LPC43xx/Include', cwd + '/../CMSIS/Include']
-CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
-
+CPPDEFINES = [rtconfig.USE_CORE]
+CPPDEFINES += ['USE_SPIFI']
 # add for startup script 
 if rtconfig.USE_CORE =='CORE_M4':
 	if rtconfig.CROSS_TOOL == 'gcc':
-		src += ['NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c']
+		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s']
 	elif rtconfig.CROSS_TOOL == 'keil':
 		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s']
 	elif rtconfig.CROSS_TOOL == 'iar':
 		src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s']
 else:
 	if rtconfig.CROSS_TOOL == 'gcc':
-		src += ['NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c']
+		src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s']
 	elif rtconfig.CROSS_TOOL == 'keil':
 		src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s']
 	elif rtconfig.CROSS_TOOL == 'iar':

From 3e50b6ac67f209c88e3f7c784fe4da803773b8c1 Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@gmail.com>
Date: Tue, 15 Jul 2014 15:51:32 +0800
Subject: [PATCH 48/86] xplorer4330:add the linker script file.

---
 bsp/xplorer4330/M0/rtconfig.py                |   2 +-
 bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.ld  | 133 ++++++++++++++++++
 bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.sct |  15 ++
 bsp/xplorer4330/M4/rtconfig.py                |   6 +-
 bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.ld  | 133 ++++++++++++++++++
 bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.sct |  15 ++
 6 files changed, 300 insertions(+), 4 deletions(-)
 create mode 100644 bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.ld
 create mode 100644 bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.sct
 create mode 100644 bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.ld
 create mode 100644 bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.sct

diff --git a/bsp/xplorer4330/M0/rtconfig.py b/bsp/xplorer4330/M0/rtconfig.py
index f548669122..5eef1d3ab8 100644
--- a/bsp/xplorer4330/M0/rtconfig.py
+++ b/bsp/xplorer4330/M0/rtconfig.py
@@ -53,7 +53,7 @@ if PLATFORM == 'gcc':
         DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
     CFLAGS = DEVICE 
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx_spifi.ld'
 
     CPATH = ''
     LPATH = ''
diff --git a/bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.ld b/bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.ld
new file mode 100644
index 0000000000..faf766b1ff
--- /dev/null
+++ b/bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.ld
@@ -0,0 +1,133 @@
+/*
+ * linker script for LPC43xx SPIFI (4Mb NorFlash, 32kB SRAM ) with GNU ld
+ * yiyue.fang 2012-04-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x14000000, LENGTH = 0x00400000
+    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        KEEP(*(.interrupt_vector))      /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.sct b/bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.sct
new file mode 100644
index 0000000000..cd28b68815
--- /dev/null
+++ b/bsp/xplorer4330/M0/rtthread-lpc43xx_spifi.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x14000000 0x00400000  {    ; load region size_region
+  ER_ROM1 0x14000000 0x00400000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x10000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/xplorer4330/M4/rtconfig.py b/bsp/xplorer4330/M4/rtconfig.py
index d8c21c1dc8..b19c390160 100644
--- a/bsp/xplorer4330/M4/rtconfig.py
+++ b/bsp/xplorer4330/M4/rtconfig.py
@@ -53,7 +53,7 @@ if PLATFORM == 'gcc':
         DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
     CFLAGS = DEVICE 
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx_spifi.ld'
 
     CPATH = ''
     LPATH = ''
@@ -75,8 +75,8 @@ elif PLATFORM == 'armcc':
     TARGET_EXT = 'axf'
 
     DEVICE = ' --device DARMSTM'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
+    CFLAGS = DEVICE + ' --apcs=interwork '
+    AFLAGS = DEVICE 
     LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
 
     CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
diff --git a/bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.ld b/bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.ld
new file mode 100644
index 0000000000..faf766b1ff
--- /dev/null
+++ b/bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.ld
@@ -0,0 +1,133 @@
+/*
+ * linker script for LPC43xx SPIFI (4Mb NorFlash, 32kB SRAM ) with GNU ld
+ * yiyue.fang 2012-04-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x14000000, LENGTH = 0x00400000
+    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        KEEP(*(.interrupt_vector))      /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.sct b/bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.sct
new file mode 100644
index 0000000000..cd28b68815
--- /dev/null
+++ b/bsp/xplorer4330/M4/rtthread-lpc43xx_spifi.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x14000000 0x00400000  {    ; load region size_region
+  ER_ROM1 0x14000000 0x00400000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x10000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

From 30d68a515cf459856761325ef75b938da621a48d Mon Sep 17 00:00:00 2001
From: Grissiom <chaos.proton@gmail.com>
Date: Wed, 16 Jul 2014 22:05:02 +0800
Subject: [PATCH 49/86] src/timer: fix a compile warning

---
 src/timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/timer.c b/src/timer.c
index 9785403d8b..f71e40fcd6 100644
--- a/src/timer.c
+++ b/src/timer.c
@@ -130,6 +130,7 @@ rt_inline void _rt_timer_remove(rt_timer_t timer)
     }
 }
 
+#if RT_DEBUG_TIMER
 static int rt_timer_count_height(struct rt_timer *timer)
 {
     int i, cnt = 0;
@@ -142,7 +143,6 @@ static int rt_timer_count_height(struct rt_timer *timer)
     return cnt;
 }
 
-#if RT_DEBUG_TIMER
 void rt_timer_dump(rt_list_t timer_heads[])
 {
     rt_list_t *list;

From c45f5a249089e1e453f358bcab052ddce8a8dff7 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Fri, 18 Jul 2014 06:45:54 +0800
Subject: [PATCH 50/86] [Drivers] re-write serial framework.

---
 bsp/at91sam9260/drivers/usart.c             |  24 +-
 bsp/beaglebone/drivers/serial.c             |  36 +-
 bsp/frdm-k64f/board/drv_uart.c              |   5 +-
 bsp/lpc408x/drivers/drv_uart.c              |  10 +-
 bsp/lpc43xx/drivers/drv_uart.c              |  14 +-
 bsp/mb9bf506r/drivers/fm3_uart.c            |  40 +-
 bsp/realview-a8/drivers/serial.c            |  13 +-
 bsp/rm48x50/drivers/drv_uart.c              |   6 +-
 bsp/stm32f0x/drivers/usart.c                |  10 +-
 bsp/xplorer4330/drivers/drv_uart.c          |  16 +-
 bsp/zynq7000/drivers/uart.c                 |  11 +-
 components/drivers/include/drivers/serial.h |  67 +-
 components/drivers/serial/serial.c          | 691 ++++++++++++--------
 components/finsh/shell.c                    |   2 +-
 14 files changed, 542 insertions(+), 403 deletions(-)

diff --git a/bsp/at91sam9260/drivers/usart.c b/bsp/at91sam9260/drivers/usart.c
index 7b95ca0e4d..c47d378cb8 100644
--- a/bsp/at91sam9260/drivers/usart.c
+++ b/bsp/at91sam9260/drivers/usart.c
@@ -95,7 +95,7 @@ void rt_at91_usart_handler(int vector, void *param)
 		return;
 	}
 	rt_interrupt_enter();
-	rt_hw_serial_isr(dev);
+	rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
 	rt_interrupt_leave();
 }
 
@@ -231,7 +231,6 @@ static const struct rt_uart_ops at91_usart_ops =
 
 #if defined(RT_USING_DBGU)
 static struct rt_serial_device serial_dbgu;
-static struct serial_ringbuffer dbgu_int_rx;
 struct at91_uart dbgu = {
 	DBGU,
 	AT91_ID_SYS
@@ -241,7 +240,6 @@ struct at91_uart dbgu = {
 
 #if defined(RT_USING_UART0)
 static struct rt_serial_device serial0;
-static struct serial_ringbuffer uart0_int_rx;
 struct at91_uart uart0 = {
 	UART0,
 	AT91SAM9260_ID_US0
@@ -250,7 +248,6 @@ struct at91_uart uart0 = {
 
 #if defined(RT_USING_UART1)
 static struct rt_serial_device serial1;
-static struct serial_ringbuffer uart1_int_rx;
 struct at91_uart uart1 = {
 	UART1,
 	AT91SAM9260_ID_US1
@@ -259,7 +256,6 @@ struct at91_uart uart1 = {
 
 #if defined(RT_USING_UART2)
 static struct rt_serial_device serial2;
-static struct serial_ringbuffer uart2_int_rx;
 struct at91_uart uart2 = {
 	UART2,
 	AT91SAM9260_ID_US2
@@ -268,7 +264,6 @@ struct at91_uart uart2 = {
 
 #if defined(RT_USING_UART3)
 static struct rt_serial_device serial3;
-static struct serial_ringbuffer uart3_int_rx;
 struct at91_uart uart3 = {
 	UART3,
 	AT91SAM9260_ID_US3
@@ -337,29 +332,29 @@ void rt_hw_uart_init(void)
 
 #if defined(RT_USING_DBGU)
 	serial_dbgu.ops = &at91_usart_ops;
-    serial_dbgu.int_rx = &dbgu_int_rx;
 	serial_dbgu.config.baud_rate = BAUD_RATE_115200;
     serial_dbgu.config.bit_order = BIT_ORDER_LSB;
     serial_dbgu.config.data_bits = DATA_BITS_8;
     serial_dbgu.config.parity = PARITY_NONE;
     serial_dbgu.config.stop_bits = STOP_BITS_1;
     serial_dbgu.config.invert = NRZ_NORMAL;
+	serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial_dbgu, "dbgu",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &dbgu);
 #endif
 
 #if defined(RT_USING_UART0)
 	serial0.ops = &at91_usart_ops;
-    serial0.int_rx = &uart0_int_rx;
 	serial0.config.baud_rate = BAUD_RATE_115200;
     serial0.config.bit_order = BIT_ORDER_LSB;
     serial0.config.data_bits = DATA_BITS_8;
     serial0.config.parity = PARITY_NONE;
     serial0.config.stop_bits = STOP_BITS_1;
     serial0.config.invert = NRZ_NORMAL;
+	serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial0, "uart0",
@@ -379,10 +374,11 @@ void rt_hw_uart_init(void)
     serial1.config.parity = PARITY_NONE;
     serial1.config.stop_bits = STOP_BITS_1;
     serial1.config.invert = NRZ_NORMAL;
+	serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart1);
 	rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler, 
 							(void *)&(serial1.parent), "UART1");
@@ -391,17 +387,17 @@ void rt_hw_uart_init(void)
 
 #if defined(RT_USING_UART2)
 	serial2.ops = &at91_usart_ops;
-    serial2.int_rx = &uart2_int_rx;
 	serial2.config.baud_rate = BAUD_RATE_115200;
     serial2.config.bit_order = BIT_ORDER_LSB;
     serial2.config.data_bits = DATA_BITS_8;
     serial2.config.parity = PARITY_NONE;
     serial2.config.stop_bits = STOP_BITS_1;
     serial2.config.invert = NRZ_NORMAL;
+	serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial2, "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart2);
 	rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler, 
 							(void *)&(serial2.parent), "UART2");
@@ -410,17 +406,17 @@ void rt_hw_uart_init(void)
 
 #if defined(RT_USING_UART3)
 	serial3.ops = &at91_usart_ops;
-    serial3.int_rx = &uart3_int_rx;
 	serial3.config.baud_rate = BAUD_RATE_115200;
     serial3.config.bit_order = BIT_ORDER_LSB;
     serial3.config.data_bits = DATA_BITS_8;
     serial3.config.parity = PARITY_NONE;
     serial3.config.stop_bits = STOP_BITS_1;
     serial3.config.invert = NRZ_NORMAL;
+	serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial3, "uart3",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart3);
 	rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler, 
 							(void *)&(serial3.parent), "UART3");
diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c
index d07621080b..8dcd389123 100644
--- a/bsp/beaglebone/drivers/serial.c
+++ b/bsp/beaglebone/drivers/serial.c
@@ -41,7 +41,7 @@ static void am33xx_uart_isr(int irqno, void* param)
 
     if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
     {
-        rt_hw_serial_isr(serial);
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
     }
 }
 
@@ -165,7 +165,6 @@ static const struct rt_uart_ops am33xx_uart_ops =
 
 /* UART device driver structure */
 #ifdef RT_USING_UART0
-struct serial_ringbuffer uart0_int_rx;
 struct am33xx_uart uart0 =
 {
     UART0_BASE,
@@ -175,7 +174,6 @@ struct rt_serial_device serial0;
 #endif
 
 #ifdef RT_USING_UART1
-struct serial_ringbuffer uart1_int_rx;
 struct am33xx_uart uart1 =
 {
     UART1_BASE,
@@ -185,7 +183,6 @@ struct rt_serial_device serial1;
 #endif
 
 #ifdef RT_USING_UART2
-struct serial_ringbuffer uart2_int_rx;
 struct am33xx_uart uart2 =
 {
     UART2_BASE,
@@ -195,7 +192,6 @@ struct rt_serial_device serial2;
 #endif
 
 #ifdef RT_USING_UART3
-struct serial_ringbuffer uart3_int_rx;
 struct am33xx_uart uart3 =
 {
     UART3_BASE,
@@ -205,7 +201,6 @@ struct rt_serial_device serial3;
 #endif
 
 #ifdef RT_USING_UART4
-struct serial_ringbuffer uart4_int_rx;
 struct am33xx_uart uart4 =
 {
     UART4_BASE,
@@ -215,7 +210,6 @@ struct rt_serial_device serial4;
 #endif
 
 #ifdef RT_USING_UART5
-struct serial_ringbuffer uart5_int_rx;
 struct am33xx_uart uart5 =
 {
     UART5_BASE,
@@ -359,8 +353,9 @@ int rt_hw_serial_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+	
     serial0.ops    = &am33xx_uart_ops;
-    serial0.int_rx = &uart0_int_rx;
     serial0.config = config;
     /* enable RX interrupt */
     UART_IER_REG(uart0.base) = 0x01;
@@ -370,7 +365,7 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart0.irq);
     /* register UART0 device */
     rt_hw_serial_register(&serial0, "uart0",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
             &uart0);
 #endif
 
@@ -381,8 +376,9 @@ int rt_hw_serial_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+	
     serial1.ops    = &am33xx_uart_ops;
-    serial1.int_rx = &uart1_int_rx;
     serial1.config = config;
     /* enable RX interrupt */
     UART_IER_REG(uart1.base) = 0x01;
@@ -392,7 +388,7 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart1.irq);
     /* register UART0 device */
     rt_hw_serial_register(&serial1, "uart1",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
             &uart1);
 #endif
 
@@ -403,8 +399,9 @@ int rt_hw_serial_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+	
     serial2.ops    = &am33xx_uart_ops;
-    serial2.int_rx = &uart2_int_rx;
     serial2.config = config;
     /* enable RX interrupt */
     UART_IER_REG(uart2.base) = 0x01;
@@ -414,7 +411,7 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart2.irq);
     /* register UART2 device */
     rt_hw_serial_register(&serial2, "uart2",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
             &uart2);
 #endif
 
@@ -425,8 +422,9 @@ int rt_hw_serial_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+	
     serial3.ops    = &am33xx_uart_ops;
-    serial3.int_rx = &uart_3_int_rx;
     serial3.config = config;
     /* enable RX interrupt */
     UART_IER_REG(uart3.base) = 0x01;
@@ -436,7 +434,7 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart3.irq);
     /* register UART3 device */
     rt_hw_serial_register(&serial3, "uart3",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
             &uart3);
 #endif
 
@@ -447,9 +445,9 @@ int rt_hw_serial_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial4.ops    = &am33xx_uart_ops;
-    serial4.int_rx = &uart4_int_rx;
     serial4.config = config;
     /* enable RX interrupt */
     UART_IER_REG(uart4.base) = 0x01;
@@ -459,7 +457,7 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart4.irq);
     /* register UART4 device */
     rt_hw_serial_register(&serial4, "uart4",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
             &uart4);
 #endif
 
@@ -470,9 +468,9 @@ int rt_hw_serial_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
   
     serial5.ops    = &am33xx_uart_ops;
-    serial5.int_rx = &uart5_int_rx;
     serial5.config = config;
     /* enable RX interrupt */
     UART_IER_REG(uart5.base) = 0x01;
@@ -482,7 +480,7 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart5.irq);
     /* register UART4 device */
     rt_hw_serial_register(&serial5, "uart5",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
             &uart5);
 #endif
 
diff --git a/bsp/frdm-k64f/board/drv_uart.c b/bsp/frdm-k64f/board/drv_uart.c
index 7813b21ad7..ac9ef8d51a 100644
--- a/bsp/frdm-k64f/board/drv_uart.c
+++ b/bsp/frdm-k64f/board/drv_uart.c
@@ -16,7 +16,6 @@
 #include "drv_uart.h"
 
 static struct rt_serial_device _k64_serial;  //abstracted serial for RTT
-static struct serial_ringbuffer _k64_int_rx; //UART send buffer area
 
 struct k64_serial_device
 {
@@ -231,7 +230,7 @@ static const struct rt_uart_ops _k64_ops =
 void UART0_RX_TX_IRQHandler(void)
 {
     rt_interrupt_enter();
-    rt_hw_serial_isr((struct rt_serial_device*)&_k64_serial);
+    rt_hw_serial_isr((struct rt_serial_device*)&_k64_serial, RT_SERIAL_EVENT_RX_IND);
     rt_interrupt_leave();
 }
 
@@ -247,9 +246,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz	 = RT_SERIAL_RB_BUFSZ;
 
     _k64_serial.ops    = &_k64_ops;
-    _k64_serial.int_rx = &_k64_int_rx;
     _k64_serial.config = config;
 
     rt_hw_serial_register(&_k64_serial, "uart0",
diff --git a/bsp/lpc408x/drivers/drv_uart.c b/bsp/lpc408x/drivers/drv_uart.c
index 37213c0474..0b3756a5b9 100644
--- a/bsp/lpc408x/drivers/drv_uart.c
+++ b/bsp/lpc408x/drivers/drv_uart.c
@@ -118,7 +118,6 @@ static const struct rt_uart_ops lpc_uart_ops =
 
 #if defined(RT_USING_UART0)
 /* UART0 device driver structure */
-struct serial_ringbuffer uart0_int_rx;
 struct lpc_uart uart0 =
 {
     UART_0,
@@ -158,7 +157,7 @@ void UART0_IRQHandler(void)
     // Receive Data Available or Character time-out
     if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI))
     {
-        rt_hw_serial_isr(&serial0);
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
     }
 
     /* leave interrupt */
@@ -167,7 +166,6 @@ void UART0_IRQHandler(void)
 #endif
 #if defined(RT_USING_UART2)
 /* UART2 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
 struct lpc_uart uart2 =
 {
     UART_2,
@@ -207,7 +205,7 @@ void UART2_IRQHandler(void)
     // Receive Data Available or Character time-out
     if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI))
     {
-        rt_hw_serial_isr(&serial2);
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
     }
 
     /* leave interrupt */
@@ -227,9 +225,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial0.ops    = &lpc_uart_ops;
-    serial0.int_rx = &uart0_int_rx;
     serial0.config = config;
 
     /*
@@ -259,9 +257,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial2.ops    = &lpc_uart_ops;
-    serial2.int_rx = &uart2_int_rx;
     serial2.config = config;
 
     /*
diff --git a/bsp/lpc43xx/drivers/drv_uart.c b/bsp/lpc43xx/drivers/drv_uart.c
index 867ee32bd5..58a385b8b1 100644
--- a/bsp/lpc43xx/drivers/drv_uart.c
+++ b/bsp/lpc43xx/drivers/drv_uart.c
@@ -97,7 +97,6 @@ static const struct rt_uart_ops lpc_uart_ops =
 
 #if defined(RT_USING_UART0)
 /* UART0 device driver structure */
-struct serial_ringbuffer uart0_int_rx;
 struct lpc_uart uart0 =
 {
     LPC_USART0,
@@ -136,7 +135,7 @@ void UART0_IRQHandler(void)
         /* read the data to buffer  */
         while (uart->USART->LSR & UART_LSR_RDR)
         {
-            rt_hw_serial_isr(&serial0);
+            rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
         }
         break;
 
@@ -150,7 +149,6 @@ void UART0_IRQHandler(void)
 #endif
 #if defined(RT_USING_UART2)
 /* UART2 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
 struct lpc_uart uart2 =
 {
     LPC_USART2,
@@ -189,7 +187,7 @@ void UART2_IRQHandler(void)
         /* read the data to buffer  */
         while (uart->USART->LSR & UART_LSR_RDR)
         {
-            rt_hw_serial_isr(&serial0);
+            rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
         }
         break;
 
@@ -214,9 +212,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz	 = RT_SERIAL_RB_BUFSZ;
 
     serial0.ops    = &lpc_uart_ops;
-    serial0.int_rx = &uart0_int_rx;
     serial0.config = config;
 
     /* Enable GPIO register interface clock                                     */
@@ -256,7 +254,7 @@ void rt_hw_uart_init(void)
 
     /* register UART1 device */
     rt_hw_serial_register(&serial0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif
 #ifdef RT_USING_UART2
@@ -267,9 +265,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz	 = RT_SERIAL_RB_BUFSZ;
 
     serial2.ops    = &lpc_uart_ops;
-    serial2.int_rx = &uart2_int_rx;
     serial2.config = config;
 
     /* Enable GPIO register interface clock                                     */
@@ -309,7 +307,7 @@ void rt_hw_uart_init(void)
 
     /* register UART1 device */
     rt_hw_serial_register(&serial2, "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif
 }
diff --git a/bsp/mb9bf506r/drivers/fm3_uart.c b/bsp/mb9bf506r/drivers/fm3_uart.c
index 51fb820ed8..2c82afd288 100644
--- a/bsp/mb9bf506r/drivers/fm3_uart.c
+++ b/bsp/mb9bf506r/drivers/fm3_uart.c
@@ -20,7 +20,6 @@
 
 #if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1))
 /* UART0 device driver structure */
-struct serial_ringbuffer uart0_int_rx;
 struct uart03_device uart0 =
 {
 	FM3_MFS0_UART,
@@ -33,7 +32,7 @@ void MFS0RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial0);
+	rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -41,7 +40,6 @@ void MFS0RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1))
 /* UART1 device driver structure */
-struct serial_ringbuffer uart1_int_rx;
 struct uart03_device uart1 =
 {
 	FM3_MFS1_UART,
@@ -54,7 +52,7 @@ void MFS1RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial1);
+	rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -62,7 +60,6 @@ void MFS1RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2))
 /* UART2 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
 struct uart03_device uart2 =
 {
 	FM3_MFS2_UART,
@@ -75,7 +72,7 @@ void MFS2RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial2);
+	rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -83,7 +80,6 @@ void MFS2RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2))
 /* UART3 device driver structure */
-struct serial_ringbuffer uart3_int_rx;
 struct uart03_device uart3 =
 {
 	FM3_MFS3_UART,
@@ -96,7 +92,7 @@ void MFS3RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial3);
+	rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -104,7 +100,6 @@ void MFS3RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2))
 /* UART4 device driver structure */
-struct serial_ringbuffer uart4_int_rx;
 struct uart47_device uart4 =
 {
 	FM3_MFS4_UART,
@@ -118,7 +113,7 @@ void MFS4RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial4);
+	rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -126,7 +121,6 @@ void MFS4RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2))
 /* UART5 device driver structure */
-struct serial_ringbuffer uart5_int_rx;
 struct uart47_device uart5 =
 {
 	FM3_MFS5_UART,
@@ -140,7 +134,7 @@ void MFS5RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial5);
+	rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -148,7 +142,6 @@ void MFS5RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1))
 /* UART6 device driver structure */
-struct serial_ringbuffer uart6_int_rx;
 struct uart47_device uart6 =
 {
 	FM3_MFS6_UART,
@@ -162,7 +155,7 @@ void MFS6RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial6);
+	rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -170,7 +163,6 @@ void MFS6RX_IRQHandler(void)
 
 #if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1))
 /* UART7 device driver structure */
-struct serial_ringbuffer uart7_int_rx;
 struct uart47_device uart7 =
 {
 	FM3_MFS7_UART,
@@ -184,7 +176,7 @@ void MFS7RX_IRQHandler(void)
 {
 	/* enter interrupt */
 	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial7);
+	rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND);
 	/* leave interrupt */
 	rt_interrupt_leave();
 }
@@ -796,9 +788,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial0.ops    = &uart03_ops;
-	serial0.int_rx = &uart0_int_rx;
 	serial0.config = config;
 
 	/* register UART0 device */
@@ -814,9 +806,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial1.ops    = &uart03_ops;
-	serial1.int_rx = &uart1_int_rx;
 	serial1.config = config;
 
 	/* register UART1 device */
@@ -833,9 +825,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial2.ops    = &uart03_ops;
-	serial2.int_rx = &uart2_int_rx;
 	serial2.config = config;
 
 	/* register UART2 device */
@@ -852,9 +844,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial3.ops    = &uart03_ops;
-	serial3.int_rx = &uart3_int_rx;
 	serial3.config = config;
 
 	/* register UART3 device */
@@ -871,9 +863,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial4.ops    = &uart47_ops;
-	serial4.int_rx = &uart4_int_rx;
 	serial4.config = config;
 
 	/* register UART4 device */
@@ -890,9 +882,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial5.ops    = &uart47_ops;
-	serial5.int_rx = &uart5_int_rx;
 	serial5.config = config;
 
 	/* register UART5 device */
@@ -909,9 +901,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial6.ops    = &uart47_ops;
-	serial6.int_rx = &uart6_int_rx;
 	serial6.config = config;
 
 	/* register UART6 device */
@@ -928,9 +920,9 @@ void rt_hw_serial_init(void)
 	config.parity    = PARITY_NONE;
 	config.stop_bits = STOP_BITS_1;
 	config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
 	serial7.ops    = &uart47_ops;
-	serial7.int_rx = &uart7_int_rx;
 	serial7.config = config;
 
 	/* register UART7 device */
diff --git a/bsp/realview-a8/drivers/serial.c b/bsp/realview-a8/drivers/serial.c
index 0af03b2759..011d10fb99 100644
--- a/bsp/realview-a8/drivers/serial.c
+++ b/bsp/realview-a8/drivers/serial.c
@@ -58,7 +58,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
 {
     struct rt_serial_device *serial = (struct rt_serial_device *)param;
 
-    rt_hw_serial_isr(serial);
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
 }
 
 static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
@@ -131,7 +131,6 @@ static const struct rt_uart_ops _uart_ops =
 
 #ifdef RT_USING_UART0
 /* UART device driver structure */
-static struct serial_ringbuffer _uart0_int_rx;
 static struct hw_uart_device _uart0_device =
 {
     REALVIEW_UART0_BASE,
@@ -142,7 +141,6 @@ static struct rt_serial_device _serial0;
 
 #ifdef RT_USING_UART1
 /* UART1 device driver structure */
-static struct serial_ringbuffer _uart1_int_rx;
 static struct hw_uart_device _uart1_device =
 {
     REALVIEW_UART1_BASE,
@@ -167,7 +165,8 @@ int rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+	
 #ifdef RT_USING_UART0
     uart = &_uart0_device;
 #ifdef RT_USING_VMM
@@ -175,12 +174,11 @@ int rt_hw_uart_init(void)
 #endif
 
     _serial0.ops    = &_uart_ops;
-    _serial0.int_rx = &_uart0_int_rx;
     _serial0.config = config;
 
     /* register UART1 device */
     rt_hw_serial_register(&_serial0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
     /* enable Rx and Tx of UART */
     UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9);
@@ -192,12 +190,11 @@ int rt_hw_uart_init(void)
     uart->hw_base = vmm_find_iomap("UART1");
 #endif
     _serial1.ops = &_uart_ops;
-    _serial1.int_rx = &_uart1_int_rx;
     _serial1.config = config;
 
     /* register UART1 device */
     rt_hw_serial_register(&_serial1, "uart1",
-        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart);
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
     /* enable Rx and Tx of UART */
     UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9);
 #endif
diff --git a/bsp/rm48x50/drivers/drv_uart.c b/bsp/rm48x50/drivers/drv_uart.c
index 3f0237e648..d42a52bc6b 100644
--- a/bsp/rm48x50/drivers/drv_uart.c
+++ b/bsp/rm48x50/drivers/drv_uart.c
@@ -178,11 +178,10 @@ static const struct rt_uart_ops _sci_ops =
 
 static void _irq_wrapper(int vector, void *param)
 {
-    rt_hw_serial_isr((struct rt_serial_device*)param);
+    rt_hw_serial_isr((struct rt_serial_device*)param, RT_SERIAL_EVENT_RX_IND);
 }
 
 static struct rt_serial_device _sci2_serial;
-static struct serial_ringbuffer _sci2_int_rx;
 
 void rt_hw_uart_init(void)
 {
@@ -195,9 +194,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz	 = RT_SERIAL_RB_BUFSZ;
 
     _sci2_serial.ops    = &_sci_ops;
-    _sci2_serial.int_rx = &_sci2_int_rx;
     _sci2_serial.config = config;
 
     rt_hw_serial_register(&_sci2_serial, "sci2",
@@ -208,3 +207,4 @@ void rt_hw_uart_init(void)
     rt_hw_interrupt_install(SCI_INT_VEC, _irq_wrapper, &_sci2_serial, "sci2");
     rt_hw_interrupt_umask(SCI_INT_VEC);
 }
+
diff --git a/bsp/stm32f0x/drivers/usart.c b/bsp/stm32f0x/drivers/usart.c
index f7784ce556..7a7d3a8230 100644
--- a/bsp/stm32f0x/drivers/usart.c
+++ b/bsp/stm32f0x/drivers/usart.c
@@ -134,7 +134,6 @@ static const struct rt_uart_ops stm32_uart_ops =
 
 #if defined(RT_USING_UART1)
 /* UART1 device driver structure */
-struct serial_ringbuffer uart1_int_rx;
 struct stm32_uart uart1 =
 {
     USART1,
@@ -152,7 +151,7 @@ void USART1_IRQHandler(void)
     rt_interrupt_enter();
     if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
     {
-        rt_hw_serial_isr(&serial1);
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
         /* clear interrupt */
         USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
     }
@@ -169,7 +168,6 @@ void USART1_IRQHandler(void)
 
 #if defined(RT_USING_UART2)
 /* UART2 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
 struct stm32_uart uart2 =
 {
     USART2,
@@ -187,7 +185,7 @@ void USART2_IRQHandler(void)
     rt_interrupt_enter();
     if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
     {
-        rt_hw_serial_isr(&serial2);
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
         /* clear interrupt */
         USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
     }
@@ -281,14 +279,13 @@ void rt_hw_usart_init(void)
     config.baud_rate = BAUD_RATE_115200;
 
     serial1.ops    = &stm32_uart_ops;
-    serial1.int_rx = &uart1_int_rx;
     serial1.config = config;
 
     NVIC_Configuration(&uart1);
 
     /* register UART1 device */
     rt_hw_serial_register(&serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* RT_USING_UART1 */
 
@@ -297,7 +294,6 @@ void rt_hw_usart_init(void)
 
     config.baud_rate = BAUD_RATE_115200;
     serial2.ops    = &stm32_uart_ops;
-    serial2.int_rx = &uart2_int_rx;
     serial2.config = config;
 
     NVIC_Configuration(&uart2);
diff --git a/bsp/xplorer4330/drivers/drv_uart.c b/bsp/xplorer4330/drivers/drv_uart.c
index c8242277b2..4fa489ea06 100644
--- a/bsp/xplorer4330/drivers/drv_uart.c
+++ b/bsp/xplorer4330/drivers/drv_uart.c
@@ -97,7 +97,6 @@ static const struct rt_uart_ops lpc_uart_ops =
 
 #if defined(RT_USING_UART0)
 /* UART0 device driver structure */
-struct serial_ringbuffer uart0_int_rx;
 struct lpc_uart uart0 =
 {
     LPC_USART0,
@@ -136,7 +135,7 @@ void UART0_IRQHandler(void)
         /* read the data to buffer  */
         while (uart->USART->LSR & UART_LSR_RDR)
         {
-            rt_hw_serial_isr(&serial0);
+            rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
         }
         break;
 
@@ -150,7 +149,6 @@ void UART0_IRQHandler(void)
 #endif
 #if defined(RT_USING_UART2)
 /* UART2 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
 struct lpc_uart uart2 =
 {
     LPC_USART2,
@@ -189,7 +187,7 @@ void UART2_IRQHandler(void)
         /* read the data to buffer  */
         while (uart->USART->LSR & UART_LSR_RDR)
         {
-            rt_hw_serial_isr(&serial0);
+            rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
         }
         break;
 
@@ -214,9 +212,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-
+	config.bufsz	 = RT_SERIAL_RB_BUFSZ;
+	
     serial0.ops    = &lpc_uart_ops;
-    serial0.int_rx = &uart0_int_rx;
     serial0.config = config;
 
     /* Enable GPIO register interface clock                                     */
@@ -256,7 +254,7 @@ void rt_hw_uart_init(void)
 
     /* register UART1 device */
     rt_hw_serial_register(&serial0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif
 #ifdef RT_USING_UART2
@@ -267,9 +265,9 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz	 = RT_SERIAL_RB_BUFSZ;
 
     serial2.ops    = &lpc_uart_ops;
-    serial2.int_rx = &uart2_int_rx;
     serial2.config = config;
 
     /* Enable GPIO register interface clock                                     */
@@ -309,7 +307,7 @@ void rt_hw_uart_init(void)
 
     /* register UART1 device */
     rt_hw_serial_register(&serial2, "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif
 }
diff --git a/bsp/zynq7000/drivers/uart.c b/bsp/zynq7000/drivers/uart.c
index f10c48d330..df4250b399 100644
--- a/bsp/zynq7000/drivers/uart.c
+++ b/bsp/zynq7000/drivers/uart.c
@@ -98,7 +98,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
 {
     struct rt_serial_device *serial = (struct rt_serial_device *)param;
 
-    rt_hw_serial_isr(serial);
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
 }
 
 static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
@@ -267,9 +267,7 @@ static struct hw_uart_device _uart_device1 =
     .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C0), /* MIO48 */
 };
 
-static struct serial_ringbuffer _uart_int_rx0;
 static struct rt_serial_device _serial0;
-static struct serial_ringbuffer _uart_int_rx1;
 static struct rt_serial_device _serial1;
 
 int rt_hw_uart_init(void)
@@ -282,21 +280,20 @@ int rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
+	config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     _serial0.ops    = &_uart_ops;
-    _serial0.int_rx = &_uart_int_rx0;
     _serial0.config = config;
 
     _serial1.ops    = &_uart_ops;
-    _serial1.int_rx = &_uart_int_rx1;
     _serial1.config = config;
 
     /* register uart device */
     rt_hw_serial_register(&_serial0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &_uart_device0);
     rt_hw_serial_register(&_serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &_uart_device1);
     return 0;
 }
diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h
index 9655820736..bf2a25ae1e 100644
--- a/components/drivers/include/drivers/serial.h
+++ b/components/drivers/include/drivers/serial.h
@@ -70,6 +70,15 @@
 #define RT_DEVICE_CTRL_CLR_INT          0x11    /* disable receive irq */
 #define RT_DEVICE_CTRL_GET_INT          0x12
 
+#define RT_SERIAL_EVENT_RX_IND          0x01    /* Rx indication */
+#define RT_SERIAL_EVENT_TX_DONE         0x02    /* Tx complete   */
+#define RT_SERIAL_EVENT_RX_DMADONE      0x03    /* Rx DMA transfer done */
+#define RT_SERIAL_EVENT_TX_DMADONE      0x04    /* Tx DMA transfer done */
+#define RT_SERIAL_EVENT_RX_TIMEOUT      0x05    /* Rx timeout    */
+
+#define RT_SERIAL_DMA_RX                0x01
+#define RT_SERIAL_DMA_TX                0x02
+
 #define RT_SERIAL_RX_INT                0x01
 #define RT_SERIAL_TX_INT                0x02
 
@@ -89,24 +98,51 @@
     PARITY_NONE,      /* No parity  */     \
     BIT_ORDER_LSB,    /* LSB first sent */ \
     NRZ_NORMAL,       /* Normal mode */    \
+    RT_SERIAL_RB_BUFSZ, /* Buffer size */  \
     0                                      \
 }
 
-struct serial_ringbuffer
-{
-    rt_uint8_t  buffer[RT_SERIAL_RB_BUFSZ];
-    rt_uint16_t put_index, get_index;
-};
-
 struct serial_configure
 {
     rt_uint32_t baud_rate;
+
     rt_uint32_t data_bits               :4;
     rt_uint32_t stop_bits               :2;
     rt_uint32_t parity                  :2;
     rt_uint32_t bit_order               :1;
     rt_uint32_t invert                  :1;
-    rt_uint32_t reserved                :20;
+	rt_uint32_t bufsz					:16;
+    rt_uint32_t reserved                :4;
+};
+
+/*
+ * Serial FIFO mode 
+ */
+struct rt_serial_rx_fifo
+{
+	/* software fifo */
+	rt_uint8_t *buffer;
+
+	rt_uint16_t put_index, get_index;
+};
+
+struct rt_serial_tx_fifo
+{
+	struct rt_completion completion;
+};
+
+/* 
+ * Serial DMA mode
+ */
+struct rt_serial_rx_dma
+{
+	rt_bool_t activated;
+};
+
+struct rt_serial_tx_dma
+{
+	rt_bool_t activated;
+	struct rt_data_queue data_queue;
 };
 
 struct rt_serial_device
@@ -116,14 +152,8 @@ struct rt_serial_device
     const struct rt_uart_ops *ops;
     struct serial_configure   config;
 
-    /* rx structure */
-    struct serial_ringbuffer *int_rx;
-    /* tx structure */
-    struct serial_ringbuffer *int_tx;
-
-    struct rt_data_queue      tx_dq;              /* tx dataqueue */
-    
-    volatile rt_bool_t        dma_flag;           /* dma transfer flag */
+	void *serial_rx;
+	void *serial_tx;
 };
 typedef struct rt_serial_device rt_serial_t;
 
@@ -138,14 +168,15 @@ struct rt_uart_ops
     int (*putc)(struct rt_serial_device *serial, char c);
     int (*getc)(struct rt_serial_device *serial);
 
-    rt_size_t (*dma_transmit)(struct rt_serial_device *serial, const char *buf, rt_size_t size);
+    rt_size_t (*dma_transmit)(struct rt_serial_device *serial, const rt_uint8_t *buf, rt_size_t size, int direction);
 };
 
-void rt_hw_serial_isr(struct rt_serial_device *serial);
-void rt_hw_serial_dma_tx_isr(struct rt_serial_device *serial);
+void rt_hw_serial_isr(struct rt_serial_device *serial, int event);
+
 rt_err_t rt_hw_serial_register(struct rt_serial_device *serial,
                                const char              *name,
                                rt_uint32_t              flag,
                                void                    *data);
 
 #endif
+
diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c
index 61c03fa955..776316baf5 100644
--- a/components/drivers/serial/serial.c
+++ b/components/drivers/serial/serial.c
@@ -25,104 +25,197 @@
  * 2012-11-23     bernard      fix compiler warning.
  * 2013-02-20     bernard      use RT_SERIAL_RB_BUFSZ to define
  *                             the size of ring buffer.
+ * 2014-07-10     bernard      rewrite serial framework
  */
 
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
 
-rt_inline void serial_ringbuffer_init(struct serial_ringbuffer *rbuffer)
+/*
+ * Serial poll routines 
+ */
+rt_inline int _serial_poll_rx(struct rt_serial_device *serial, rt_uint8_t *data, int length)
 {
-    rt_memset(rbuffer->buffer, 0, sizeof(rbuffer->buffer));
-    rbuffer->put_index = 0;
-    rbuffer->get_index = 0;
+	int ch;
+	int size;
+	
+	RT_ASSERT(serial != RT_NULL);
+	size = length;
+
+	while (length)
+	{
+		ch = serial->ops->getc(serial);
+		*data = ch; 
+		data ++; length --;
+
+		if (ch == '\n') break;
+	}
+
+	return size - length;
 }
 
-rt_inline void serial_ringbuffer_putc(struct serial_ringbuffer *rbuffer,
-                                      char                      ch)
+rt_inline int _serial_poll_tx(struct rt_serial_device *serial, const rt_uint8_t *data, int length)
 {
-    rt_base_t level;
+	int size;
+	RT_ASSERT(serial != RT_NULL);
 
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
+	size = length;
+	while (length)
+	{
+		/*
+		 * to be polite with serial console add a line feed
+		 * to the carriage return character
+		 */
+		if (*data == '\n' && (serial->parent.flag & RT_DEVICE_FLAG_STREAM))
+		{
+			serial->ops->putc(serial, '\r');
+		}
+	
+		serial->ops->putc(serial, *data);
+	
+		++ data;
+		-- length;
+	}
 
-    rbuffer->buffer[rbuffer->put_index] = ch;
-    rbuffer->put_index = (rbuffer->put_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
-
-    /* if the next position is read index, discard this 'read char' */
-    if (rbuffer->put_index == rbuffer->get_index)
-    {
-        rbuffer->get_index = (rbuffer->get_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
-    }
-
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
+	return size - length;
 }
 
-rt_inline int serial_ringbuffer_putchar(struct serial_ringbuffer *rbuffer,
-                                        char                      ch)
+/*
+ * Serial interrupt routines
+ */
+rt_inline int _serial_int_rx(struct rt_serial_device *serial, rt_uint8_t *data, int length)
 {
-    rt_base_t level;
-    rt_uint16_t next_index;
+	int size;
+	struct rt_serial_rx_fifo* rx_fifo;
 
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
+	RT_ASSERT(serial != RT_NULL);
+	size = length; 
+	
+	rx_fifo = (struct rt_serial_rx_fifo*) serial->serial_rx;
+	RT_ASSERT(rx_fifo != RT_NULL);
 
-    next_index = (rbuffer->put_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
-    if (next_index != rbuffer->get_index)
-    {
-        rbuffer->buffer[rbuffer->put_index] = ch;
-        rbuffer->put_index = next_index;
-    }
-    else
-    {
-        /* enable interrupt */
-        rt_hw_interrupt_enable(level);
+	/* read from software FIFO */
+	while (length)
+	{
+		int ch;
+		rt_base_t level;
 
-        return -1;
-    }
+		/* disable interrupt */
+		level = rt_hw_interrupt_disable();
+		if (rx_fifo->get_index != rx_fifo->put_index)
+		{
+			ch = rx_fifo->buffer[rx_fifo->get_index];
+			rx_fifo->get_index += 1;
+			if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0;
+		}
+		else
+		{
+			/* no data, enable interrupt and break out */
+			rt_hw_interrupt_enable(level);
+			break;
+		}
 
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
+		/* enable interrupt */
+		rt_hw_interrupt_enable(level);
 
-    return 1;
+		*data = ch & 0xff;
+		data ++; length --;
+	}
+
+	return size - length;
 }
 
-rt_inline int serial_ringbuffer_getc(struct serial_ringbuffer *rbuffer)
+rt_inline int _serial_int_tx(struct rt_serial_device *serial, const rt_uint8_t *data, int length)
 {
-    int ch;
-    rt_base_t level;
+	int size;
+	struct rt_serial_tx_fifo *tx;
+	
+	RT_ASSERT(serial != RT_NULL);
 
-    ch = -1;
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
-    if (rbuffer->get_index != rbuffer->put_index)
-    {
-        ch = rbuffer->buffer[rbuffer->get_index];
-        rbuffer->get_index = (rbuffer->get_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
-    }
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
+	size = length;
+	tx = (struct rt_serial_tx_fifo*) serial->serial_tx;
+	RT_ASSERT(tx != RT_NULL);
 
-    return ch;
+	while (length)
+	{
+		if (serial->ops->putc(serial, *(char*)data) == -1)
+		{
+			rt_completion_wait(&(tx->completion), RT_WAITING_FOREVER);
+			continue;
+		}
+
+		data ++; length --;
+	}
+
+	return size - length;
 }
 
-rt_inline rt_uint32_t serial_ringbuffer_size(struct serial_ringbuffer *rbuffer)
+/*
+ * Serial DMA routines
+ */
+rt_inline int _serial_dma_rx(struct rt_serial_device *serial, rt_uint8_t *data, int length)
 {
-    rt_uint32_t size;
-    rt_base_t level;
+	rt_base_t level;
+	int result = RT_EOK;
+	struct rt_serial_rx_dma *rx_dma;
 
-    level = rt_hw_interrupt_disable();
-    size = (rbuffer->put_index - rbuffer->get_index) & (RT_SERIAL_RB_BUFSZ - 1);
-    rt_hw_interrupt_enable(level);
+	RT_ASSERT((serial != RT_NULL) && (data != RT_NULL));
+	rx_dma = (struct rt_serial_rx_dma*)serial->serial_rx;
+	RT_ASSERT(rx_dma != RT_NULL);
 
-    return size;
+	level = rt_hw_interrupt_disable();
+	if (rx_dma->activated != RT_TRUE)
+	{
+		rx_dma->activated = RT_TRUE;
+		serial->ops->dma_transmit(serial, data, length, RT_SERIAL_DMA_RX);
+	}
+	else result = -RT_EBUSY;
+	rt_hw_interrupt_enable(level);
+
+	if (result == RT_EOK) return length;
+
+	rt_set_errno(result);
+	return 0;
+}
+
+rt_inline int _serial_dma_tx(struct rt_serial_device *serial, const rt_uint8_t *data, int length)
+{
+	rt_base_t level;
+	rt_err_t result;
+	struct rt_serial_tx_dma *tx_dma;
+
+	tx_dma = (struct rt_serial_tx_dma*)(serial->serial_tx);
+	
+	result = rt_data_queue_push(&(tx_dma->data_queue), data, length, RT_WAITING_FOREVER); 
+	if (result == RT_EOK)
+	{
+		level = rt_hw_interrupt_disable();
+		if (tx_dma->activated != RT_TRUE)
+		{
+			tx_dma->activated = RT_TRUE;
+			rt_hw_interrupt_enable(level);
+
+			/* make a DMA transfer */
+			serial->ops->dma_transmit(serial, data, length, RT_SERIAL_DMA_TX);
+		}
+		else
+		{
+			rt_hw_interrupt_enable(level);
+		}
+
+		return length;
+	}
+	else
+	{
+		rt_set_errno(result);
+		return 0;
+	}
 }
 
 /* RT-Thread Device Interface */
-
 /*
- * This function initializes serial
+ * This function initializes serial device.
  */
 static rt_err_t rt_serial_init(struct rt_device *dev)
 {
@@ -132,58 +225,107 @@ static rt_err_t rt_serial_init(struct rt_device *dev)
     RT_ASSERT(dev != RT_NULL);
     serial = (struct rt_serial_device *)dev;
 
-    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-    {
-        /* apply configuration */
-        if (serial->ops->configure)
-            result = serial->ops->configure(serial, &serial->config);
+	/* initialize rx/tx */
+	serial->serial_rx = RT_NULL;
+	serial->serial_tx = RT_NULL;
 
-        if (result != RT_EOK)
-            return result;
+	/* apply configuration */
+	if (serial->ops->configure)
+		result = serial->ops->configure(serial, &serial->config);
 
-        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-            serial_ringbuffer_init(serial->int_rx);
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        {
-			/* not supported yet */
-			/*
-            serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_NULL);
-            serial_ringbuffer_init(serial->int_tx);
-            serial->int_sending_flag = RT_FALSE;
-			*/
-        }
-
-        if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-        {
-            serial->dma_flag = RT_FALSE;
-            
-            /* init data queue */
-            rt_data_queue_init(&(serial->tx_dq), RT_SERIAL_TX_DATAQUEUE_SIZE,
-                               RT_SERIAL_TX_DATAQUEUE_LWM, RT_NULL);
-        }
-    }
-
-    return result;
+	return result;
 }
 
 static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag)
 {
     struct rt_serial_device *serial;
-    rt_uint32_t int_flags = 0;
 
     RT_ASSERT(dev != RT_NULL);
     serial = (struct rt_serial_device *)dev;
 
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-        int_flags = RT_SERIAL_RX_INT;
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        int_flags |= RT_SERIAL_TX_INT;
+	/* check device flag with the open flag */
+	if ((oflag & RT_DEVICE_FLAG_DMA_RX) && !(dev->flag & RT_DEVICE_FLAG_DMA_RX)) 
+		return -RT_EIO;
+	if ((oflag & RT_DEVICE_FLAG_DMA_TX) && !(dev->flag & RT_DEVICE_FLAG_DMA_TX))
+		return -RT_EIO;
+	if ((oflag & RT_DEVICE_FLAG_INT_RX) && !(dev->flag & RT_DEVICE_FLAG_INT_RX))
+		return -RT_EIO;
+	if ((oflag & RT_DEVICE_FLAG_INT_TX) && !(dev->flag & RT_DEVICE_FLAG_INT_TX))
+		return -RT_EIO;
 
-    if (int_flags)
-    {
-        serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)int_flags);
-    }
+	/* get open flags */
+	dev->open_flag = oflag & 0xff;
+	
+	/* initialize the Rx/Tx structure according to open flag */
+	if (serial->serial_rx == RT_NULL)
+	{
+		if (oflag & RT_DEVICE_FLAG_DMA_RX)
+		{
+			struct rt_serial_rx_dma* rx_dma;
+
+			rx_dma = (struct rt_serial_rx_dma*) rt_malloc (sizeof(struct rt_serial_rx_dma));
+			RT_ASSERT(rx_dma != RT_NULL);
+			rx_dma->activated = RT_FALSE;
+
+			serial->serial_rx = rx_dma;
+			dev->open_flag |= RT_DEVICE_FLAG_DMA_RX;
+		}
+		else if (oflag & RT_DEVICE_FLAG_INT_RX)
+		{
+			struct rt_serial_rx_fifo* rx_fifo;
+
+			rx_fifo = (struct rt_serial_rx_fifo*) rt_malloc (sizeof(struct rt_serial_rx_fifo) + 
+				serial->config.bufsz);
+			RT_ASSERT(rx_fifo != RT_NULL);
+			rx_fifo->buffer = (rt_uint8_t*) (rx_fifo + 1);
+			rt_memset(rx_fifo->buffer, 0, RT_SERIAL_RB_BUFSZ);
+			rx_fifo->put_index = 0;
+			rx_fifo->get_index = 0;
+
+			serial->serial_rx = rx_fifo;
+			dev->open_flag |= RT_DEVICE_FLAG_INT_RX;
+			/* configure low level device */
+			serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX);
+		}
+		else
+		{
+			serial->serial_rx = RT_NULL;
+		}
+	}
+
+	if (serial->serial_tx == RT_NULL)
+	{
+		if (oflag & RT_DEVICE_FLAG_DMA_TX)
+		{
+			struct rt_serial_tx_dma* tx_dma;
+
+			tx_dma = (struct rt_serial_tx_dma*) rt_malloc (sizeof(struct rt_serial_tx_dma));
+			RT_ASSERT(tx_dma != RT_NULL);
+			
+			rt_data_queue_init(&(tx_dma->data_queue), 8, 4, RT_NULL);
+			serial->serial_tx = tx_dma;
+
+			dev->open_flag |= RT_DEVICE_FLAG_DMA_TX;
+		}
+		else if (oflag & RT_DEVICE_FLAG_INT_TX)
+		{
+			struct rt_serial_tx_fifo *tx_fifo;
+
+			tx_fifo = (struct rt_serial_tx_fifo*) rt_malloc(sizeof(struct rt_serial_tx_fifo));
+			RT_ASSERT(tx_fifo != RT_NULL);
+
+			rt_completion_init(&(tx_fifo->completion));
+			serial->serial_tx = tx_fifo;
+
+			dev->open_flag |= RT_DEVICE_FLAG_INT_TX;
+			/* configure low level device */
+			serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_TX);
+		}
+		else
+		{
+			serial->serial_tx = RT_NULL;
+		}
+	}
 
     return RT_EOK;
 }
@@ -191,20 +333,62 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag)
 static rt_err_t rt_serial_close(struct rt_device *dev)
 {
     struct rt_serial_device *serial;
-    rt_uint32_t int_flags = 0;
 
     RT_ASSERT(dev != RT_NULL);
     serial = (struct rt_serial_device *)dev;
 
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-        int_flags = RT_SERIAL_RX_INT;
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        int_flags |= RT_SERIAL_TX_INT;
+	/* this device has more reference count */
+	if (dev->ref_count > 1) return RT_EOK;
+	
+	if (dev->open_flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		struct rt_serial_rx_fifo* rx_fifo;
 
-    if (int_flags)
-    {
-        serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void *)int_flags);
-    }
+		rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx;
+		RT_ASSERT(rx_fifo != RT_NULL);
+
+		rt_free(rx_fifo);
+		serial->serial_rx = RT_NULL;
+		dev->open_flag &= ~RT_DEVICE_FLAG_INT_RX;
+		/* configure low level device */
+		serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void*)RT_DEVICE_FLAG_INT_TX);
+	}
+	else if (dev->open_flag & RT_DEVICE_FLAG_DMA_RX)
+	{
+		struct rt_serial_rx_dma* rx_dma;
+
+		rx_dma = (struct rt_serial_rx_dma*)serial->serial_tx;
+		RT_ASSERT(rx_dma != RT_NULL);
+
+		rt_free(rx_dma);
+		serial->serial_rx = RT_NULL;
+		dev->open_flag &= ~RT_DEVICE_FLAG_DMA_RX;
+	}
+
+	if (dev->open_flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		struct rt_serial_tx_fifo* tx_fifo;
+
+		tx_fifo = (struct rt_serial_tx_fifo*)serial->serial_rx;
+		RT_ASSERT(tx_fifo != RT_NULL);
+
+		rt_free(tx_fifo);
+		serial->serial_tx = RT_NULL;
+		dev->open_flag &= ~RT_DEVICE_FLAG_INT_TX;
+		/* configure low level device */
+		serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void*)RT_DEVICE_FLAG_INT_TX);
+	}
+	else if (dev->open_flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		struct rt_serial_tx_dma* tx_dma;
+
+		tx_dma = (struct rt_serial_tx_dma*)serial->serial_tx;
+		RT_ASSERT(tx_dma != RT_NULL);
+
+		rt_free(tx_dma);
+		serial->serial_tx = RT_NULL;
+		dev->open_flag &= ~RT_DEVICE_FLAG_DMA_TX;
+	}
 
     return RT_EOK;
 }
@@ -214,53 +398,23 @@ static rt_size_t rt_serial_read(struct rt_device *dev,
                                 void             *buffer,
                                 rt_size_t         size)
 {
-    rt_uint8_t *ptr;
-    rt_uint32_t read_nbytes;
     struct rt_serial_device *serial;
 
     RT_ASSERT(dev != RT_NULL);
-
-    if (size == 0)
-        return 0;
+    if (size == 0) return 0;
 
     serial = (struct rt_serial_device *)dev;
 
-    ptr = (rt_uint8_t *)buffer;
+	if (dev->open_flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		return _serial_int_rx(serial, buffer, size);
+	}
+	else if (dev->open_flag & RT_DEVICE_FLAG_DMA_RX)
+	{
+		return _serial_dma_rx(serial, buffer, size);
+	}
 
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        /* interrupt mode Rx */
-        while (size)
-        {
-            int ch;
-
-            ch = serial_ringbuffer_getc(serial->int_rx);
-            if (ch == -1)
-                break;
-
-            *ptr = ch & 0xff;
-            ptr ++;
-            size --;
-        }
-    }
-    else
-    {
-        /* polling mode */
-        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-        {
-            *ptr = serial->ops->getc(serial);
-            ptr ++;
-        }
-    }
-
-    read_nbytes = (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-    /* set error code */
-    if (read_nbytes == 0)
-    {
-        rt_set_errno(-RT_EEMPTY);
-    }
-
-    return read_nbytes;
+	return _serial_poll_rx(serial, buffer, size);
 }
 
 static rt_size_t rt_serial_write(struct rt_device *dev,
@@ -268,90 +422,23 @@ static rt_size_t rt_serial_write(struct rt_device *dev,
                                  const void       *buffer,
                                  rt_size_t         size)
 {
-    rt_uint8_t *ptr;
-    rt_size_t write_nbytes = 0;
     struct rt_serial_device *serial;
 
     RT_ASSERT(dev != RT_NULL);
-
-    if (size == 0)
-        return 0;
+    if (size == 0) return 0;
 
     serial = (struct rt_serial_device *)dev;
 
-    ptr = (rt_uint8_t*)buffer;
+	if (dev->open_flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		_serial_int_tx(serial, buffer, size);
+	}
+	else if (dev->open_flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		_serial_dma_tx(serial, buffer, size);
+	}
 
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-    {
-        /* warning: data will be discarded if buffer is full */
-        while (size)
-        {
-            if (serial_ringbuffer_putchar(serial->int_tx, *ptr) != -1)
-            {
-                ptr ++;
-                size --;
-            }
-            else
-                break;
-        }
-    }
-    else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-    {
-        rt_base_t level;
-        rt_err_t result;
-        
-        RT_ASSERT(0 == (dev->flag & RT_DEVICE_FLAG_STREAM));
-
-        result = rt_data_queue_push(&(serial->tx_dq), buffer, size, 20); 
-        if (result == RT_EOK)
-        {
-            level = rt_hw_interrupt_disable();
-            if (serial->dma_flag == RT_FALSE)
-            {
-                serial->dma_flag = RT_TRUE;
-                rt_hw_interrupt_enable(level);
-                serial->ops->dma_transmit(serial, buffer, size);
-            }
-            else
-                rt_hw_interrupt_enable(level);
-
-            return size;
-        }
-        else
-        {
-            rt_set_errno(result);
-
-            return 0;
-        }
-    }
-    else
-    {
-        /* polling mode */
-        while (size)
-        {
-            /*
-             * to be polite with serial console add a line feed
-             * to the carriage return character
-             */
-            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-            {
-                serial->ops->putc(serial, '\r');
-            }
-
-            serial->ops->putc(serial, *ptr);
-
-            ++ ptr;
-            -- size;
-        }
-    }
-
-    write_nbytes = (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-    if (write_nbytes == 0)
-    {
-        rt_set_errno(-RT_EFULL);
-    }
-
-    return write_nbytes;
+	return _serial_poll_tx(serial, buffer, size);
 }
 
 static rt_err_t rt_serial_control(struct rt_device *dev,
@@ -419,56 +506,108 @@ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial,
 }
 
 /* ISR for serial interrupt */
-void rt_hw_serial_isr(struct rt_serial_device *serial)
+void rt_hw_serial_isr(struct rt_serial_device *serial, int event)
 {
-    int ch = -1;
+	switch (event & 0xff)
+	{
+		case RT_SERIAL_EVENT_RX_IND:
+		{
+			int ch = -1;
+			rt_base_t level;
+			struct rt_serial_rx_fifo* rx_fifo;
 
-    /* interrupt mode receive */
-    RT_ASSERT(serial->parent.flag & RT_DEVICE_FLAG_INT_RX);
+			rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx;
+			RT_ASSERT(rx_fifo != RT_NULL);
+			
+			/* interrupt mode receive */
+			RT_ASSERT(serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX);
+			
+			while (1)
+			{
+				ch = serial->ops->getc(serial);
+				if (ch == -1) break;
 
-    while (1)
-    {
-        ch = serial->ops->getc(serial);
-        if (ch == -1)
-            break;
+				
+				/* disable interrupt */
+				level = rt_hw_interrupt_disable();
+				
+				rx_fifo->buffer[rx_fifo->put_index] = ch;
+				rx_fifo->put_index += 1;
+				if (rx_fifo->put_index >= serial->config.bufsz) rx_fifo->put_index = 0;
+				
+				/* if the next position is read index, discard this 'read char' */
+				if (rx_fifo->put_index == rx_fifo->get_index)
+				{
+					rx_fifo->get_index += 1;
+					if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0;
+				}
+				
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+			}
+			
+			/* invoke callback */
+			if (serial->parent.rx_indicate != RT_NULL)
+			{
+				rt_size_t rx_length;
+			
+				/* get rx length */
+				level = rt_hw_interrupt_disable();
+				rx_length = (rx_fifo->put_index >= rx_fifo->get_index)? (rx_fifo->put_index - rx_fifo->get_index):
+					(serial->config.bufsz - (rx_fifo->get_index - rx_fifo->put_index));
+				rt_hw_interrupt_enable(level);
 
-        serial_ringbuffer_putc(serial->int_rx, ch);
-    }
+				serial->parent.rx_indicate(&serial->parent, rx_length);
+			}
+			break;
+		}
+		case RT_SERIAL_EVENT_TX_DONE:
+		{
+			struct rt_serial_tx_fifo* tx_fifo;
 
-    /* invoke callback */
-    if (serial->parent.rx_indicate != RT_NULL)
-    {
-        rt_size_t rx_length;
+			tx_fifo = (struct rt_serial_tx_fifo*)serial->serial_tx;
+			rt_completion_done(&(tx_fifo->completion));
+			break;
+		}
+		case RT_SERIAL_EVENT_TX_DMADONE:
+		{
+			const void *data_ptr;
+			rt_size_t data_size;
+			const void *last_data_ptr;
+			struct rt_serial_tx_dma* tx_dma;
 
-        /* get rx length */
-        rx_length = serial_ringbuffer_size(serial->int_rx);
-        serial->parent.rx_indicate(&serial->parent, rx_length);
-    }
-}
-
-/*
- * ISR for DMA mode Tx
- */
-void rt_hw_serial_dma_tx_isr(struct rt_serial_device *serial)
-{
-    const void *data_ptr;
-    rt_size_t data_size;
-    const void *last_data_ptr;
-
-    rt_data_queue_pop(&(serial->tx_dq), &last_data_ptr, &data_size, 0);
-    if (RT_EOK == rt_data_queue_peak(&(serial->tx_dq), &data_ptr, &data_size))
-    {
-        /* transmit next data node */
-         serial->ops->dma_transmit(serial, data_ptr, data_size);
-    }
-    else
-    {
-        serial->dma_flag = RT_FALSE;
-    }
-
-    /* invoke callback */
-    if (serial->parent.tx_complete != RT_NULL)
-    {
-        serial->parent.tx_complete(&serial->parent, (void*)last_data_ptr);
-    }
+			tx_dma = (struct rt_serial_tx_dma*) serial->serial_tx;
+			
+			rt_data_queue_pop(&(tx_dma->data_queue), &last_data_ptr, &data_size, 0);
+			if (rt_data_queue_peak(&(tx_dma->data_queue), &data_ptr, &data_size) == RT_EOK)
+			{
+				/* transmit next data node */
+				tx_dma->activated = RT_TRUE;
+				serial->ops->dma_transmit(serial, data_ptr, data_size, RT_SERIAL_DMA_TX);
+			}
+			else
+			{
+				tx_dma->activated = RT_FALSE;
+			}
+			
+			/* invoke callback */
+			if (serial->parent.tx_complete != RT_NULL)
+			{
+				serial->parent.tx_complete(&serial->parent, (void*)last_data_ptr);
+			}
+			break;
+		}
+		case RT_SERIAL_EVENT_RX_DMADONE:
+		{
+			int length;
+			struct rt_serial_rx_dma* rx_dma;
+
+			rx_dma = (struct rt_serial_rx_dma*)serial->serial_rx;
+			/* get DMA rx length */
+			length = (event & (~0xff)) >> 8;
+			serial->parent.rx_indicate(&(serial->parent), length);
+			rx_dma->activated = RT_FALSE;
+			break;
+		}
+	}
 }
diff --git a/components/finsh/shell.c b/components/finsh/shell.c
index ae099e7e7c..5489cedf3d 100644
--- a/components/finsh/shell.c
+++ b/components/finsh/shell.c
@@ -306,8 +306,8 @@ void finsh_thread_entry(void* parameter)
 #ifdef RT_USING_CONSOLE
         shell->device = rt_console_get_device();
         RT_ASSERT(shell->device);
-        rt_device_open(shell->device, RT_DEVICE_OFLAG_RDWR);
         rt_device_set_rx_indicate(shell->device, finsh_rx_ind);
+        rt_device_open(shell->device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #else
         RT_ASSERT(shell->device);
 #endif

From a83558e0e25dec0da36111fa92f441097ac3f2bc Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Fri, 18 Jul 2014 06:48:37 +0800
Subject: [PATCH 51/86] [Build] Fix LPC4300 building.

---
 .travis.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index 2b9f998904..94b130fdd7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -51,7 +51,8 @@ env:
   - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
 #  - RTT_BSP='upd70f3454' # iar
 #  - RTT_BSP='x86' # x86
-  - RTT_BSP='xplorer4330/m4' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'

From 74377b2650b6d9e3d2d2e4de11ed05a5d8979d00 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Fri, 18 Jul 2014 07:21:09 +0800
Subject: [PATCH 52/86] [Drivers] re-write serial framework.

---
 bsp/stm32f10x/drivers/usart.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/bsp/stm32f10x/drivers/usart.c b/bsp/stm32f10x/drivers/usart.c
index ae47db3a14..bbaf4ec032 100644
--- a/bsp/stm32f10x/drivers/usart.c
+++ b/bsp/stm32f10x/drivers/usart.c
@@ -137,7 +137,6 @@ static const struct rt_uart_ops stm32_uart_ops =
 
 #if defined(RT_USING_UART1)
 /* UART1 device driver structure */
-struct serial_ringbuffer uart1_int_rx;
 struct stm32_uart uart1 =
 {
     USART1,
@@ -155,7 +154,7 @@ void USART1_IRQHandler(void)
     rt_interrupt_enter();
     if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
     {
-        rt_hw_serial_isr(&serial1);
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
         /* clear interrupt */
         USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
     }
@@ -172,7 +171,6 @@ void USART1_IRQHandler(void)
 
 #if defined(RT_USING_UART2)
 /* UART1 device driver structure */
-struct serial_ringbuffer uart2_int_rx;
 struct stm32_uart uart2 =
 {
     USART2,
@@ -190,7 +188,7 @@ void USART2_IRQHandler(void)
     rt_interrupt_enter();
     if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
     {
-        rt_hw_serial_isr(&serial2);
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
         /* clear interrupt */
         USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
     }
@@ -207,7 +205,6 @@ void USART2_IRQHandler(void)
 
 #if defined(RT_USING_UART3)
 /* UART1 device driver structure */
-struct serial_ringbuffer uart3_int_rx;
 struct stm32_uart uart3 =
 {
     USART3,
@@ -225,7 +222,7 @@ void USART3_IRQHandler(void)
     rt_interrupt_enter();
     if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
     {
-        rt_hw_serial_isr(&serial3);
+        rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
         /* clear interrupt */
         USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
     }
@@ -329,14 +326,13 @@ void rt_hw_usart_init(void)
     config.baud_rate = BAUD_RATE_115200;
 
     serial1.ops    = &stm32_uart_ops;
-    serial1.int_rx = &uart1_int_rx;
     serial1.config = config;
 
     NVIC_Configuration(&uart1);
 
     /* register UART1 device */
     rt_hw_serial_register(&serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* RT_USING_UART1 */
 
@@ -345,7 +341,6 @@ void rt_hw_usart_init(void)
 
     config.baud_rate = BAUD_RATE_115200;
     serial2.ops    = &stm32_uart_ops;
-    serial2.int_rx = &uart2_int_rx;
     serial2.config = config;
 
     NVIC_Configuration(&uart2);
@@ -362,7 +357,6 @@ void rt_hw_usart_init(void)
     config.baud_rate = BAUD_RATE_115200;
 
     serial3.ops    = &stm32_uart_ops;
-    serial3.int_rx = &uart3_int_rx;
     serial3.config = config;
 
     NVIC_Configuration(&uart3);

From 3a1c1c45002e420f35433544138c2c357942a349 Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Fri, 18 Jul 2014 17:17:56 +0800
Subject: [PATCH 53/86] [bsp] Add BSP for TM4C1294XL (TI Tiva C Series
 Connected LaunchPad)

---
 bsp/tm4c129x/SConscript                       |    14 +
 bsp/tm4c129x/SConstruct                       |    29 +
 bsp/tm4c129x/applications/SConscript          |    11 +
 bsp/tm4c129x/applications/application.c       |    37 +
 bsp/tm4c129x/applications/board.c             |   100 +
 bsp/tm4c129x/applications/board.h             |    52 +
 bsp/tm4c129x/applications/startup.c           |    68 +
 bsp/tm4c129x/drivers/SConscript               |    14 +
 bsp/tm4c129x/drivers/drv_uart.c               |   202 +
 bsp/tm4c129x/drivers/drv_uart.h               |    20 +
 bsp/tm4c129x/libraries/SConscript             |    31 +
 bsp/tm4c129x/libraries/driverlib/adc.c        |  2019 ++
 bsp/tm4c129x/libraries/driverlib/adc.h        |   328 +
 bsp/tm4c129x/libraries/driverlib/aes.c        |  1305 +
 bsp/tm4c129x/libraries/driverlib/aes.h        |   218 +
 bsp/tm4c129x/libraries/driverlib/can.c        |  2117 ++
 bsp/tm4c129x/libraries/driverlib/can.h        |   449 +
 bsp/tm4c129x/libraries/driverlib/comp.c       |   452 +
 bsp/tm4c129x/libraries/driverlib/comp.h       |   141 +
 bsp/tm4c129x/libraries/driverlib/cpu.c        |   457 +
 bsp/tm4c129x/libraries/driverlib/cpu.h        |    75 +
 bsp/tm4c129x/libraries/driverlib/crc.c        |   311 +
 bsp/tm4c129x/libraries/driverlib/crc.h        |   101 +
 bsp/tm4c129x/libraries/driverlib/debug.h      |    70 +
 bsp/tm4c129x/libraries/driverlib/des.c        |   807 +
 bsp/tm4c129x/libraries/driverlib/des.h        |   140 +
 bsp/tm4c129x/libraries/driverlib/eeprom.c     |  1156 +
 bsp/tm4c129x/libraries/driverlib/eeprom.h     |   284 +
 bsp/tm4c129x/libraries/driverlib/emac.c       |  4689 ++++
 bsp/tm4c129x/libraries/driverlib/emac.h       |  1025 +
 bsp/tm4c129x/libraries/driverlib/epi.c        |  2187 ++
 bsp/tm4c129x/libraries/driverlib/epi.h        |   762 +
 bsp/tm4c129x/libraries/driverlib/flash.c      |   851 +
 bsp/tm4c129x/libraries/driverlib/flash.h      |   113 +
 bsp/tm4c129x/libraries/driverlib/fpu.c        |   300 +
 bsp/tm4c129x/libraries/driverlib/fpu.h        |   113 +
 bsp/tm4c129x/libraries/driverlib/gpio.c       |  2671 ++
 bsp/tm4c129x/libraries/driverlib/gpio.h       |   196 +
 bsp/tm4c129x/libraries/driverlib/hibernate.c  |  2551 ++
 bsp/tm4c129x/libraries/driverlib/hibernate.h  |   257 +
 bsp/tm4c129x/libraries/driverlib/i2c.c        |  2143 ++
 bsp/tm4c129x/libraries/driverlib/i2c.h        |   361 +
 bsp/tm4c129x/libraries/driverlib/interrupt.c  |  1060 +
 bsp/tm4c129x/libraries/driverlib/interrupt.h  |    94 +
 bsp/tm4c129x/libraries/driverlib/lcd.c        |  1805 ++
 bsp/tm4c129x/libraries/driverlib/lcd.h        |   487 +
 bsp/tm4c129x/libraries/driverlib/mpu.c        |   459 +
 bsp/tm4c129x/libraries/driverlib/mpu.h        |   162 +
 bsp/tm4c129x/libraries/driverlib/onewire.c    |   771 +
 bsp/tm4c129x/libraries/driverlib/onewire.h    |   307 +
 bsp/tm4c129x/libraries/driverlib/pin_map.h    | 20493 ++++++++++++++++
 bsp/tm4c129x/libraries/driverlib/pwm.c        |  2162 ++
 bsp/tm4c129x/libraries/driverlib/pwm.h        |   326 +
 bsp/tm4c129x/libraries/driverlib/qei.c        |   693 +
 bsp/tm4c129x/libraries/driverlib/qei.h        |   128 +
 bsp/tm4c129x/libraries/driverlib/readme.txt   |    36 +
 bsp/tm4c129x/libraries/driverlib/rom.h        |  6990 ++++++
 bsp/tm4c129x/libraries/driverlib/rom_map.h    |  6416 +++++
 .../libraries/driverlib/rtos_bindings.h       |   108 +
 bsp/tm4c129x/libraries/driverlib/shamd5.c     |  1092 +
 bsp/tm4c129x/libraries/driverlib/shamd5.h     |   127 +
 bsp/tm4c129x/libraries/driverlib/ssi.c        |  1150 +
 bsp/tm4c129x/libraries/driverlib/ssi.h        |   157 +
 bsp/tm4c129x/libraries/driverlib/sw_crc.c     |   770 +
 bsp/tm4c129x/libraries/driverlib/sw_crc.h     |    78 +
 bsp/tm4c129x/libraries/driverlib/sysctl.c     |  3699 +++
 bsp/tm4c129x/libraries/driverlib/sysctl.h     |   655 +
 bsp/tm4c129x/libraries/driverlib/sysexc.c     |   311 +
 bsp/tm4c129x/libraries/driverlib/sysexc.h     |    89 +
 bsp/tm4c129x/libraries/driverlib/systick.c    |   277 +
 bsp/tm4c129x/libraries/driverlib/systick.h    |    78 +
 bsp/tm4c129x/libraries/driverlib/tiva_timer.c |  1895 ++
 bsp/tm4c129x/libraries/driverlib/tiva_timer.h |   301 +
 bsp/tm4c129x/libraries/driverlib/uart.c       |  1958 ++
 bsp/tm4c129x/libraries/driverlib/uart.h       |   255 +
 bsp/tm4c129x/libraries/driverlib/udma.c       |  1384 ++
 bsp/tm4c129x/libraries/driverlib/udma.h       |   899 +
 bsp/tm4c129x/libraries/driverlib/usb.c        |  5909 +++++
 bsp/tm4c129x/libraries/driverlib/usb.h        |   658 +
 bsp/tm4c129x/libraries/driverlib/watchdog.c   |   622 +
 bsp/tm4c129x/libraries/driverlib/watchdog.h   |    95 +
 bsp/tm4c129x/libraries/inc/asmdefs.h          |   227 +
 bsp/tm4c129x/libraries/inc/hw_adc.h           |  1307 +
 bsp/tm4c129x/libraries/inc/hw_aes.h           |   545 +
 bsp/tm4c129x/libraries/inc/hw_can.h           |   462 +
 bsp/tm4c129x/libraries/inc/hw_ccm.h           |   115 +
 bsp/tm4c129x/libraries/inc/hw_comp.h          |   211 +
 bsp/tm4c129x/libraries/inc/hw_des.h           |   310 +
 bsp/tm4c129x/libraries/inc/hw_eeprom.h        |   251 +
 bsp/tm4c129x/libraries/inc/hw_emac.h          |  1845 ++
 bsp/tm4c129x/libraries/inc/hw_epi.h           |   933 +
 bsp/tm4c129x/libraries/inc/hw_fan.h           |    49 +
 bsp/tm4c129x/libraries/inc/hw_flash.h         |   625 +
 bsp/tm4c129x/libraries/inc/hw_gpio.h          |   213 +
 bsp/tm4c129x/libraries/inc/hw_hibernate.h     |   483 +
 bsp/tm4c129x/libraries/inc/hw_i2c.h           |   470 +
 bsp/tm4c129x/libraries/inc/hw_ints.h          |   491 +
 bsp/tm4c129x/libraries/inc/hw_lcd.h           |   575 +
 bsp/tm4c129x/libraries/inc/hw_memmap.h        |   151 +
 bsp/tm4c129x/libraries/inc/hw_nvic.h          |  1414 ++
 bsp/tm4c129x/libraries/inc/hw_pwm.h           |  1885 ++
 bsp/tm4c129x/libraries/inc/hw_qei.h           |   178 +
 bsp/tm4c129x/libraries/inc/hw_shamd5.h        |   548 +
 bsp/tm4c129x/libraries/inc/hw_ssi.h           |   238 +
 bsp/tm4c129x/libraries/inc/hw_sysctl.h        |  3704 +++
 bsp/tm4c129x/libraries/inc/hw_sysexc.h        |   132 +
 bsp/tm4c129x/libraries/inc/hw_timer.h         |   700 +
 bsp/tm4c129x/libraries/inc/hw_types.h         |   147 +
 bsp/tm4c129x/libraries/inc/hw_uart.h          |   367 +
 bsp/tm4c129x/libraries/inc/hw_udma.h          |   414 +
 bsp/tm4c129x/libraries/inc/hw_usb.h           |  3032 +++
 bsp/tm4c129x/libraries/inc/hw_watchdog.h      |   122 +
 bsp/tm4c129x/libraries/inc/tm4c129xnczad.h    | 17263 +++++++++++++
 .../libraries/startup/startup_ewarm.c         |   299 +
 bsp/tm4c129x/libraries/startup/startup_gcc.c  |   317 +
 .../libraries/startup/startup_rvmdk.S         |   324 +
 bsp/tm4c129x/project.uvproj                   |   851 +
 bsp/tm4c129x/rtconfig.h                       |   230 +
 bsp/tm4c129x/rtconfig.py                      |    87 +
 bsp/tm4c129x/template.uvproj                  |   388 +
 bsp/tm4c129x/tm4c_rom.icf                     |    78 +
 bsp/tm4c129x/tm4c_rom.ld                      |   160 +
 bsp/tm4c129x/tm4c_rom.sct                     |    16 +
 123 files changed, 136340 insertions(+)
 create mode 100644 bsp/tm4c129x/SConscript
 create mode 100644 bsp/tm4c129x/SConstruct
 create mode 100644 bsp/tm4c129x/applications/SConscript
 create mode 100644 bsp/tm4c129x/applications/application.c
 create mode 100644 bsp/tm4c129x/applications/board.c
 create mode 100644 bsp/tm4c129x/applications/board.h
 create mode 100644 bsp/tm4c129x/applications/startup.c
 create mode 100644 bsp/tm4c129x/drivers/SConscript
 create mode 100644 bsp/tm4c129x/drivers/drv_uart.c
 create mode 100644 bsp/tm4c129x/drivers/drv_uart.h
 create mode 100644 bsp/tm4c129x/libraries/SConscript
 create mode 100644 bsp/tm4c129x/libraries/driverlib/adc.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/adc.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/aes.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/aes.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/can.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/can.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/comp.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/comp.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/cpu.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/cpu.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/crc.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/crc.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/debug.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/des.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/des.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/eeprom.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/eeprom.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/emac.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/emac.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/epi.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/epi.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/flash.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/flash.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/fpu.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/fpu.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/gpio.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/gpio.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/hibernate.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/hibernate.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/i2c.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/i2c.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/interrupt.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/interrupt.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/lcd.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/lcd.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/mpu.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/mpu.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/onewire.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/onewire.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/pin_map.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/pwm.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/pwm.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/qei.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/qei.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/readme.txt
 create mode 100644 bsp/tm4c129x/libraries/driverlib/rom.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/rom_map.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/rtos_bindings.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/shamd5.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/shamd5.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/ssi.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/ssi.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/sw_crc.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/sw_crc.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/sysctl.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/sysctl.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/sysexc.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/sysexc.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/systick.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/systick.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/tiva_timer.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/tiva_timer.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/uart.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/uart.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/udma.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/udma.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/usb.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/usb.h
 create mode 100644 bsp/tm4c129x/libraries/driverlib/watchdog.c
 create mode 100644 bsp/tm4c129x/libraries/driverlib/watchdog.h
 create mode 100644 bsp/tm4c129x/libraries/inc/asmdefs.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_adc.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_aes.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_can.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_ccm.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_comp.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_des.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_eeprom.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_emac.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_epi.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_fan.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_flash.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_gpio.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_hibernate.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_i2c.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_ints.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_lcd.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_memmap.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_nvic.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_pwm.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_qei.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_shamd5.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_ssi.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_sysctl.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_sysexc.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_timer.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_types.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_uart.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_udma.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_usb.h
 create mode 100644 bsp/tm4c129x/libraries/inc/hw_watchdog.h
 create mode 100644 bsp/tm4c129x/libraries/inc/tm4c129xnczad.h
 create mode 100644 bsp/tm4c129x/libraries/startup/startup_ewarm.c
 create mode 100644 bsp/tm4c129x/libraries/startup/startup_gcc.c
 create mode 100644 bsp/tm4c129x/libraries/startup/startup_rvmdk.S
 create mode 100644 bsp/tm4c129x/project.uvproj
 create mode 100644 bsp/tm4c129x/rtconfig.h
 create mode 100644 bsp/tm4c129x/rtconfig.py
 create mode 100644 bsp/tm4c129x/template.uvproj
 create mode 100644 bsp/tm4c129x/tm4c_rom.icf
 create mode 100644 bsp/tm4c129x/tm4c_rom.ld
 create mode 100644 bsp/tm4c129x/tm4c_rom.sct

diff --git a/bsp/tm4c129x/SConscript b/bsp/tm4c129x/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/tm4c129x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/tm4c129x/SConstruct b/bsp/tm4c129x/SConstruct
new file mode 100644
index 0000000000..16877dd5b4
--- /dev/null
+++ b/bsp/tm4c129x/SConstruct
@@ -0,0 +1,29 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/tm4c129x/applications/SConscript b/bsp/tm4c129x/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/tm4c129x/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/tm4c129x/applications/application.c b/bsp/tm4c129x/applications/application.c
new file mode 100644
index 0000000000..3c07bb6128
--- /dev/null
+++ b/bsp/tm4c129x/applications/application.c
@@ -0,0 +1,37 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-18     ArdaFu       the first version for TM4C129X
+ */
+
+#include <rtthread.h>
+#include <board.h>
+#include <components.h>
+
+/* thread phase init */
+void rt_init_thread_entry(void *parameter)
+{
+    /* Initialization RT-Thread Components */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_init();
+#endif
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry, RT_NULL,
+                           2048, RT_THREAD_PRIORITY_MAX / 3, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c
new file mode 100644
index 0000000000..e26f3f5076
--- /dev/null
+++ b/bsp/tm4c129x/applications/board.c
@@ -0,0 +1,100 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2014-07-18     ArdaFu       Port to TM4C129X
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <components.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "interrupt.h"
+#include "sysctl.h"
+#include "systick.h"
+#include "fpu.h"
+#include "driverlib/rom_map.h"
+
+#define SYS_CLOCK_DEFAULT 120000000
+uint32_t SysClock;
+
+#define FAULT_NMI               2           // NMI fault
+#define FAULT_HARD              3           // Hard fault
+#define FAULT_MPU               4           // MPU fault
+#define FAULT_BUS               5           // Bus fault
+#define FAULT_USAGE             6           // Usage fault
+#define FAULT_SVCALL            11          // SVCall
+#define FAULT_DEBUG             12          // Debug monitor
+#define FAULT_PENDSV            14          // PendSV
+#define FAULT_SYSTICK           15          // System Tick
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+extern void PendSV_Handler(void);
+extern void HardFault_Handler(void);
+
+
+/**
+ * This function will initial LPC40xx board.
+ */
+void rt_hw_board_init()
+{
+    IntRegister(FAULT_HARD, HardFault_Handler);	
+		IntRegister(FAULT_PENDSV, PendSV_Handler);
+		IntRegister(FAULT_SYSTICK, SysTick_Handler);
+	
+	  //
+    // Enable lazy stacking for interrupt handlers.  This allows floating-point
+    // instructions to be used within interrupt handlers, but at the expense of
+    // extra stack usage.
+    //
+    MAP_FPULazyStackingEnable();
+
+    //
+    // Set the clocking to run directly from the external crystal/oscillator.
+    // TODO: The SYSCTL_XTAL_ value must be changed to match the value of the
+    // crystal on your board.
+    //
+    SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480),
+                                            SYS_CLOCK_DEFAULT);
+
+	MAP_SysTickDisable();
+    MAP_SysTickPeriodSet(SysClock/ RT_TICK_PER_SECOND - 1);
+    MAP_SysTickIntEnable();
+    MAP_SysTickEnable();	
+
+
+    /* set pend exception priority */
+    //IntPrioritySet(FAULT_PENDSV, (1 << __NVIC_PRIO_BITS) - 1);
+    /*init uart device*/
+		
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    //
+    // Enable interrupts to the processor.
+    //
+	MAP_IntMasterEnable();
+}
diff --git a/bsp/tm4c129x/applications/board.h b/bsp/tm4c129x/applications/board.h
new file mode 100644
index 0000000000..f382ae4b6a
--- /dev/null
+++ b/bsp/tm4c129x/applications/board.h
@@ -0,0 +1,52 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2010-02-04     Magicoe      add board.h to LPC176x bsp
+ * 2014-07-18     ArdaFu       port it to TM4C129X bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "tm4c129xnczad.h"
+#include <rtthread.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+extern uint32_t SysClock;
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
+#define RT_USING_UART0
+// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
+//#define RT_USING_UART1
+// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
+//#define RT_USING_UART2
+
+// </RDTConfigurator>
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+#define HEAP_END    (0x20000000 + 256*1024)
+
+#define FINSH_DEVICE_NAME   RT_CONSOLE_DEVICE_NAME
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/tm4c129x/applications/startup.c b/bsp/tm4c129x/applications/startup.c
new file mode 100644
index 0000000000..97cc165490
--- /dev/null
+++ b/bsp/tm4c129x/applications/startup.c
@@ -0,0 +1,68 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2010-03-04     Magicoe      for LPC17xx
+ * 2014-07-18     ArdaFu       Port to TM4C129X
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+extern int rt_application_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+    /* initialize system timer*/
+    rt_system_timer_init();
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize timer thread */
+    rt_system_timer_thread_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
diff --git a/bsp/tm4c129x/drivers/SConscript b/bsp/tm4c129x/drivers/SConscript
new file mode 100644
index 0000000000..e5f4cd4945
--- /dev/null
+++ b/bsp/tm4c129x/drivers/SConscript
@@ -0,0 +1,14 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_LWIP') == False:
+	SrcRemove(src, 'drv_emac.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/tm4c129x/drivers/drv_uart.c b/bsp/tm4c129x/drivers/drv_uart.c
new file mode 100644
index 0000000000..eba5eff67a
--- /dev/null
+++ b/bsp/tm4c129x/drivers/drv_uart.c
@@ -0,0 +1,202 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-18     Bernard      The first version for LPC40xx
+ * 2014-07-18     ArdaFu       Port to TM4C129X
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+//#include <components.h>
+
+#include "sysctl.h"
+#include "gpio.h"
+#include "uart.h"
+#include "hw_memmap.h"
+#include "pin_map.h"
+#include "interrupt.h"
+#include "rom.h"
+#include "rom_map.h"
+typedef struct hw_uart_device
+{
+    uint32_t hw_base; // base address
+}hw_uart_t;
+
+#define GetHwUartPtr(serial) ((hw_uart_t*)(serial->parent.user_data))
+
+static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{	
+	hw_uart_t* uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = GetHwUartPtr(serial);
+	MAP_UARTDisable(uart->hw_base);
+    /* Initialize UART Configuration parameter structure to default state:
+     * Baudrate = 115200 bps
+     * 8 data bit
+     * 1 Stop bit
+     * None parity
+     */
+    // Initialize UART0 peripheral with given to corresponding parameter
+    MAP_UARTConfigSetExpClk(uart->hw_base, SysClock, cfg->baud_rate,
+													(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
+		MAP_UARTFIFOEnable(uart->hw_base);
+
+  //
+	// Enable the UART.
+	//
+	MAP_UARTEnable(uart->hw_base);
+    return RT_EOK;
+}
+
+static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+	hw_uart_t* uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = GetHwUartPtr(serial);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        MAP_UARTIntDisable(uart->hw_base, UART_INT_RX | UART_INT_RT);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        MAP_UARTIntEnable(uart->hw_base, UART_INT_RX | UART_INT_RT);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int hw_putc(struct rt_serial_device *serial, char c)
+{
+	hw_uart_t* uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = GetHwUartPtr(serial);
+	
+    MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c));
+    return 1;
+}
+
+static int hw_getc(struct rt_serial_device *serial)
+{
+	hw_uart_t* uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = GetHwUartPtr(serial);
+	
+	return MAP_UARTCharGetNonBlocking(uart->hw_base);
+}
+
+static const struct rt_uart_ops hw_uart_ops =
+{
+    hw_configure,
+    hw_control,
+    hw_putc,
+    hw_getc,
+};
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct rt_serial_device serial0;
+struct serial_ringbuffer uart0_int_rx_buf;
+hw_uart_t uart0 =
+{
+    UART0_BASE,
+};
+
+void UART0_IRQHandler(void)
+{
+	  uint32_t intsrc;
+    hw_uart_t *uart = &uart0;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Determine the interrupt source */
+    intsrc = UARTIntStatus(uart->hw_base, true);
+
+    // Receive Data Available or Character time-out
+    if (intsrc & (UART_INT_RX | UART_INT_RT))
+    {
+						UARTIntClear(UART0_BASE, intsrc);
+        rt_hw_serial_isr(&serial0);
+
+    }
+		
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+int rt_hw_uart_init(void)
+{
+    hw_uart_t* uart;
+    struct serial_configure config;
+	
+#ifdef RT_USING_UART0
+    uart = &uart0;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    serial0.ops    = &hw_uart_ops;
+    serial0.int_rx = &uart0_int_rx_buf;
+    serial0.config = config;
+
+    //
+    // Enable the peripherals used by this example.
+    // The UART itself needs to be enabled, as well as the GPIO port
+    // containing the pins that will be used.
+    //
+
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
+
+    //
+    // Configure the GPIO pin muxing for the UART function.
+    // This is only necessary if your part supports GPIO pin function muxing.
+    // Study the data sheet to see which functions are allocated per pin.
+    // TODO: change this to select the port/pin you are using
+    //
+    MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
+    MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
+
+    //
+    // Since GPIO A0 and A1 are used for the UART function, they must be
+    // configured for use as a peripheral function (instead of GPIO).
+    // TODO: change this to match the port/pin you are using
+    //
+    MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
+
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
+
+    /* preemption = 1, sub-priority = 1 */
+    //IntPrioritySet(INT_UART0, ((0x01 << 3) | 0x01));
+
+    /* Enable Interrupt for UART channel */
+	UARTIntRegister(uart->hw_base, UART0_IRQHandler);
+	MAP_IntEnable(INT_UART0);
+	MAP_UARTEnable(uart->hw_base);
+
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          uart);
+#endif
+	return 0;
+}
+//INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/tm4c129x/drivers/drv_uart.h b/bsp/tm4c129x/drivers/drv_uart.h
new file mode 100644
index 0000000000..312c6da6b3
--- /dev/null
+++ b/bsp/tm4c129x/drivers/drv_uart.h
@@ -0,0 +1,20 @@
+/*
+ * File      : drv_uart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-18     Bernard      The first version for LPC40xx
+ * 2014-07-18     ArdaFu       Port to TM4C129X
+ */
+#ifndef __UART_H__
+#define __UART_H__
+
+void rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/tm4c129x/libraries/SConscript b/bsp/tm4c129x/libraries/SConscript
new file mode 100644
index 0000000000..02874cac12
--- /dev/null
+++ b/bsp/tm4c129x/libraries/SConscript
@@ -0,0 +1,31 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+# The set of source files associated with this SConscript file.
+cwd     = GetCurrentDir()
+src = Glob('driverlib/*.c')
+SrcRemove(src, 'onewire.c')
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+	src += ['startup/startup_gcc.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+	src += ['startup/startup_rvmdk.S']
+elif rtconfig.CROSS_TOOL == 'iar':
+	src += ['startup/startup_ewarm.c']
+elif rtconfig.CROSS_TOOL == 'ccs':
+	src += ['startup/startup_ccs.c']
+
+CPPPATH = [cwd, cwd + '/inc', cwd + '/driverlib']
+
+CPPDEFINES = [rtconfig.PART_TYPE]
+if rtconfig.CROSS_TOOL == 'gcc':
+	CPPDEFINES += ['gcc'];
+	CPPDEFINES += ['uint_fast8_t=uint32_t'];
+	CPPDEFINES += ['uint_fast32_t=uint32_t'];
+	CPPDEFINES += ['int_fast8_t=int32_t'];
+	CPPDEFINES += ['uint_fast16_t=uint32_t'];
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/tm4c129x/libraries/driverlib/adc.c b/bsp/tm4c129x/libraries/driverlib/adc.c
new file mode 100644
index 0000000000..ac2000e0ba
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/adc.c
@@ -0,0 +1,2019 @@
+//*****************************************************************************
+//
+// adc.c - Driver for the ADC.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup adc_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_adc.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_sysctl.h"
+#include "driverlib/adc.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// These defines are used by the ADC driver to simplify access to the ADC
+// sequencer's registers.
+//
+//*****************************************************************************
+#define ADC_SEQ                 (ADC_O_SSMUX0)
+#define ADC_SEQ_STEP            (ADC_O_SSMUX1 - ADC_O_SSMUX0)
+#define ADC_SSMUX               (ADC_O_SSMUX0 - ADC_O_SSMUX0)
+#define ADC_SSEMUX              (ADC_O_SSEMUX0 - ADC_O_SSMUX0)
+#define ADC_SSCTL               (ADC_O_SSCTL0 - ADC_O_SSMUX0)
+#define ADC_SSFIFO              (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
+#define ADC_SSFSTAT             (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
+#define ADC_SSOP                (ADC_O_SSOP0 - ADC_O_SSMUX0)
+#define ADC_SSDC                (ADC_O_SSDC0 - ADC_O_SSMUX0)
+#define ADC_SSTSH               (ADC_O_SSTSH0 - ADC_O_SSMUX0)
+
+//*****************************************************************************
+//
+// The currently configured software oversampling factor for each of the ADC
+// sequencers.
+//
+//*****************************************************************************
+static uint8_t g_pui8OversampleFactor[3];
+
+//*****************************************************************************
+//
+//! Returns the interrupt number for a given ADC base address and sequence
+//! number.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function returns the interrupt number for the ADC module and sequence
+//! number provided in the \e ui32Base and \e ui32SequenceNum parameters.
+//!
+//! \return Returns the ADC sequence interrupt number or 0 if the interrupt
+//! does not exist.
+//
+//*****************************************************************************
+static uint_fast8_t
+_ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    uint_fast8_t ui8Int;
+
+    //
+    // Determine the interrupt to register based on the sequence number.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        ui8Int = ((ui32Base == ADC0_BASE) ?
+                  (INT_ADC0SS0_TM4C123 + ui32SequenceNum) :
+                  (INT_ADC0SS0_TM4C123 + ui32SequenceNum));
+    }
+    else if(CLASS_IS_TM4C129)
+    {
+        ui8Int = ((ui32Base == ADC0_BASE) ?
+                  (INT_ADC0SS0_TM4C129 + ui32SequenceNum) :
+                  (INT_ADC1SS0_TM4C129 + ui32SequenceNum));
+    }
+    else
+    {
+        ui8Int = 0;
+    }
+
+    return(ui8Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an ADC interrupt.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! ADC sample sequence interrupt occurs.
+//!
+//! This function sets the handler to be called when a sample sequence
+//! interrupt occurs.  This function enables the global interrupt in the
+//! interrupt controller; the sequence interrupt must be enabled with
+//! ADCIntEnable().  It is the interrupt handler's responsibility to clear the
+//! interrupt source via ADCIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
+               void (*pfnHandler)(void))
+{
+    uint_fast8_t ui8Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Determine the interrupt to register based on the sequence number.
+    //
+    ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum);
+    ASSERT(ui8Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui8Int, pfnHandler);
+
+    //
+    // Enable the timer interrupt.
+    //
+    IntEnable(ui8Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for an ADC interrupt.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function unregisters the interrupt handler.  This function disables
+//! the global interrupt in the interrupt controller; the sequence interrupt
+//! must be disabled via ADCIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    uint_fast8_t ui8Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Determine the interrupt to unregister based on the sequence number.
+    //
+    ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum);
+    ASSERT(ui8Int != 0);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui8Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui8Int);
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence interrupt.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Disable this sample sequence interrupt.
+    //
+    HWREG(ui32Base + ADC_O_IM) &= ~(1 << ui32SequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence interrupt.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence interrupt.  Any
+//! outstanding interrupts are cleared before enabling the sample sequence
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Clear any outstanding interrupts on this sample sequence.
+    //
+    HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum;
+
+    //
+    // Enable this sample sequence interrupt.
+    //
+    HWREG(ui32Base + ADC_O_IM) |= 1 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the specified sample
+//! sequence.  Either the raw interrupt status or the status of interrupts that
+//! are allowed to reflect to the processor can be returned.
+//!
+//! \return The current raw or masked interrupt status.
+//
+//*****************************************************************************
+uint32_t
+ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, bool bMasked)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        ui32Temp = HWREG(ui32Base + ADC_O_ISC) & (0x10001 << ui32SequenceNum);
+    }
+    else
+    {
+        ui32Temp = (HWREG(ui32Base + ADC_O_RIS) &
+                    (0x10000 | (1 << ui32SequenceNum)));
+
+        //
+        // If the digital comparator status bit is set, reflect it to the
+        // appropriate sequence bit.
+        //
+        if(ui32Temp & 0x10000)
+        {
+            ui32Temp |= 0xF0000;
+            ui32Temp &= ~(0x10000 << ui32SequenceNum);
+        }
+    }
+
+    //
+    // Return the interrupt status
+    //
+    return(ui32Temp);
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence interrupt source.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! The specified sample sequence interrupt is cleared, so that it no longer
+//! asserts.  This function must be called in the interrupt handler to keep
+//! the interrupt from being triggered again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Clear the interrupt.
+    //
+    HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! Allows the specified sample sequence to be captured when its trigger is
+//! detected.  A sample sequence must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Enable the specified sequence.
+    //
+    HWREG(ui32Base + ADC_O_ACTSS) |= 1 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! Prevents the specified sample sequence from being captured when its trigger
+//! is detected.  A sample sequence must be disabled before it is configured.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Disable the specified sequences.
+    //
+    HWREG(ui32Base + ADC_O_ACTSS) &= ~(1 << ui32SequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Configures the trigger source and priority of a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param ui32Trigger is the trigger source that initiates the sample
+//! sequence; must be one of the \b ADC_TRIGGER_* values.
+//! \param ui32Priority is the relative priority of the sample sequence with
+//! respect to the other sample sequences.
+//!
+//! This function configures the initiation criteria for a sample sequence.
+//! Valid sample sequencers range from zero to three; sequencer zero captures
+//! up to eight samples, sequencers one and two capture up to four samples,
+//! and sequencer three captures a single sample.  The trigger condition and
+//! priority (with respect to other sample sequencer execution) are set.
+//!
+//! The \e ui32Trigger parameter can take on the following values:
+//!
+//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
+//!                              ADCProcessorTrigger() function.
+//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
+//!                          comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
+//!                          comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
+//!                          comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
+//!                             B4 pin.  Note that some microcontrollers can
+//!                             select from any GPIO using the
+//!                             GPIOADCTriggerEnable() function.
+//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
+//!                          TimerControlTrigger().
+//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
+//!                         configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
+//!                         configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
+//!                         configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator;
+//!                         configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
+//!                           sample sequence to capture repeatedly (so long as
+//!                           there is not a higher priority source active).
+//!
+//! When \b ADC_TRIGGER_PWM0, \b ADC_TRIGGER_PWM1, \b ADC_TRIGGER_PWM2 or
+//! \b ADC_TRIGGER_PWM3 is specified, one of the following should be ORed into
+//! \e ui32Trigger to select the PWM module from which the triggers will be
+//! routed for this sequence:
+//!
+//! - \b ADC_TRIGGER_PWM_MOD0 - Selects PWM module 0 as the source of the
+//!                             PWM0 to PWM3 triggers for this sequence.
+//! - \b ADC_TRIGGER_PWM_MOD1 - Selects PWM module 1 as the source of the
+//!                             PWM0 to PWM3 triggers for this sequence.
+//!
+//! Note that not all trigger sources are available on all Tiva family
+//! members; consult the data sheet for the device in question to determine the
+//! availability of triggers.
+//!
+//! The \e ui32Priority parameter is a value between 0 and 3, where 0
+//! represents the highest priority and 3 the lowest.  Note that when
+//! programming the priority among a set of sample sequences, each must have
+//! unique priority; it is up to the caller to guarantee the uniqueness of the
+//! priorities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                     uint32_t ui32Trigger, uint32_t ui32Priority)
+{
+    //
+    // Check the arugments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+    ASSERT(((ui32Trigger & 0xF) == ADC_TRIGGER_PROCESSOR) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP0) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP1) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP2) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_EXTERNAL) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_TIMER) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM0) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM1) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM2) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM3) ||
+           ((ui32Trigger & 0xF) == ADC_TRIGGER_ALWAYS) ||
+           ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD0) ||
+           ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD1));
+    ASSERT(ui32Priority < 4);
+
+    //
+    // Compute the shift for the bits that control this sample sequence.
+    //
+    ui32SequenceNum *= 4;
+
+    //
+    // Set the trigger event for this sample sequence.
+    //
+    HWREG(ui32Base + ADC_O_EMUX) = ((HWREG(ui32Base + ADC_O_EMUX) &
+                                     ~(0xf << ui32SequenceNum)) |
+                                    ((ui32Trigger & 0xf) << ui32SequenceNum));
+
+    //
+    // Set the priority for this sample sequence.
+    //
+    HWREG(ui32Base + ADC_O_SSPRI) = ((HWREG(ui32Base + ADC_O_SSPRI) &
+                                      ~(0xf << ui32SequenceNum)) |
+                                     ((ui32Priority & 0x3) <<
+                                      ui32SequenceNum));
+
+    //
+    // Set the source PWM module for this sequence's PWM triggers.
+    //
+    ui32SequenceNum *= 2;
+    HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) &
+                                      ~(0x30 << ui32SequenceNum)) |
+                                     ((ui32Trigger & 0x30) <<
+                                      ui32SequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Configure a step of the sample sequencer.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param ui32Step is the step to be configured.
+//! \param ui32Config is the configuration of this step; must be a logical OR
+//! of \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of
+//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7).
+//!
+//! This function configures the ADC for one step of a sample sequence.  The
+//! ADC can be configured for single-ended or differential operation (the
+//! \b ADC_CTL_D bit selects differential operation when set), the channel to
+//! be sampled can be chosen (the \b ADC_CTL_CH0 through \b ADC_CTL_CH23
+//! values), and the internal temperature sensor can be selected (the
+//! \b ADC_CTL_TS bit).  Additionally, this step can be defined as the last in
+//! the sequence (the \b ADC_CTL_END bit) and it can be configured to cause an
+//! interrupt when the step is complete (the \b ADC_CTL_IE bit).  If the
+//! digital comparators are present on the device, this step may also be
+//! configured to send the ADC sample to the selected comparator using
+//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7.  The configuration is used by the
+//! ADC at the appropriate time when the trigger for this sequence occurs.
+//!
+//! \note If the Digital Comparator is present and enabled using the
+//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT
+//! written into the ADC sequence data FIFO.
+//!
+//! The \e ui32Step parameter determines the order in which the samples are
+//! captured by the ADC when the trigger occurs.  It can range from zero to
+//! seven for the first sample sequencer, from zero to three for the second and
+//! third sample sequencer, and can only be zero for the fourth sample
+//! sequencer.
+//!
+//! Differential mode only works with adjacent channel pairs (for example, 0
+//! and 1).  The channel select must be the number of the channel pair to
+//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
+//! and 3) or undefined results are returned by the ADC.  Additionally, if
+//! differential mode is selected when the temperature sensor is being sampled,
+//! undefined results are returned by the ADC.
+//!
+//! It is the responsibility of the caller to ensure that a valid configuration
+//! is specified; this function does not check the validity of the specified
+//! configuration.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                         uint32_t ui32Step, uint32_t ui32Config)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+    ASSERT(((ui32SequenceNum == 0) && (ui32Step < 8)) ||
+           ((ui32SequenceNum == 1) && (ui32Step < 4)) ||
+           ((ui32SequenceNum == 2) && (ui32Step < 4)) ||
+           ((ui32SequenceNum == 3) && (ui32Step < 1)));
+
+    //
+    // Get the offset of the sequence to be configured.
+    //
+    ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
+
+    //
+    // Compute the shift for the bits that control this step.
+    //
+    ui32Step *= 4;
+
+    //
+    // Set the analog mux value for this step.
+    //
+    HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) &
+                                    ~(0x0000000f << ui32Step)) |
+                                   ((ui32Config & 0x0f) << ui32Step));
+
+    //
+    // Set the upper bits of the analog mux value for this step.
+    //
+    HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) &
+                                     ~(0x0000000f << ui32Step)) |
+                                    (((ui32Config & 0xf00) >> 8) << ui32Step));
+
+    //
+    // Set the control value for this step.
+    //
+    HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) &
+                                    ~(0x0000000f << ui32Step)) |
+                                   (((ui32Config & 0xf0) >> 4) << ui32Step));
+
+    //
+    // Set the sample and hold time for this step.  This is not available on
+    // all devices, however on devices that do not support this feature these
+    // reserved bits are ignored on write access.
+    //
+    HWREG(ui32Base + ADC_SSTSH) = ((HWREG(ui32Base + ADC_SSTSH) &
+                                    ~(0x0000000f << ui32Step)) |
+                                (((ui32Config & 0xf00000) >> 20) << ui32Step));
+
+    //
+    // Enable digital comparator if specified in the ui32Config bit-fields.
+    //
+    if(ui32Config & 0x000F0000)
+    {
+        //
+        // Program the comparator for the specified step.
+        //
+        ui32Temp = HWREG(ui32Base + ADC_SSDC);
+        ui32Temp &= ~(0xF << ui32Step);
+        ui32Temp |= (((ui32Config & 0x00070000) >> 16) << ui32Step);
+        HWREG(ui32Base + ADC_SSDC) = ui32Temp;
+
+        //
+        // Enable the comparator.
+        //
+        HWREG(ui32Base + ADC_SSOP) |= (1 << ui32Step);
+    }
+
+    //
+    // Disable digital comparator if not specified.
+    //
+    else
+    {
+        HWREG(ui32Base + ADC_SSOP) &= ~(1 << ui32Step);
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence overflow occurred.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function determines if a sample sequence overflow has occurred.
+//! Overflow happens if the captured samples are not read from the FIFO before
+//! the next trigger occurs.
+//!
+//! \return Returns zero if there was not an overflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+int32_t
+ADCSequenceOverflow(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Determine if there was an overflow on this sequence.
+    //
+    return(HWREG(ui32Base + ADC_O_OSTAT) & (1 << ui32SequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the overflow condition on a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function clears an overflow condition on one of the sample sequences.
+//! The overflow condition must be cleared in order to detect a subsequent
+//! overflow condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceOverflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Clear the overflow condition for this sequence.
+    //
+    HWREG(ui32Base + ADC_O_OSTAT) = 1 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence underflow occurred.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function determines if a sample sequence underflow has occurred.
+//! Underflow happens if too many samples are read from the FIFO.
+//!
+//! \return Returns zero if there was not an underflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+int32_t
+ADCSequenceUnderflow(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Determine if there was an underflow on this sequence.
+    //
+    return(HWREG(ui32Base + ADC_O_USTAT) & (1 << ui32SequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the underflow condition on a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function clears an underflow condition on one of the sample
+//! sequencers.  The underflow condition must be cleared in order to detect a
+//! subsequent underflow condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceUnderflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Clear the underflow condition for this sequence.
+    //
+    HWREG(ui32Base + ADC_O_USTAT) = 1 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param pui32Buffer is the address where the data is stored.
+//!
+//! This function copies data from the specified sample sequencer output FIFO
+//! to a memory resident buffer.  The number of samples available in the
+//! hardware FIFO are copied into the buffer, which is assumed to be large
+//! enough to hold that many samples.  This function only returns the samples
+//! that are presently available, which may not be the entire sample sequence
+//! if it is in the process of being executed.
+//!
+//! \return Returns the number of samples copied to the buffer.
+//
+//*****************************************************************************
+int32_t
+ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                   uint32_t *pui32Buffer)
+{
+    uint32_t ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Get the offset of the sequence to be read.
+    //
+    ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
+
+    //
+    // Read samples from the FIFO until it is empty.
+    //
+    ui32Count = 0;
+    while(!(HWREG(ui32Base + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) &&
+          (ui32Count < 8))
+    {
+        //
+        // Read the FIFO and copy it to the destination.
+        //
+        *pui32Buffer++ = HWREG(ui32Base + ADC_SSFIFO);
+
+        //
+        // Increment the count of samples read.
+        //
+        ui32Count++;
+    }
+
+    //
+    // Return the number of samples read.
+    //
+    return(ui32Count);
+}
+
+//*****************************************************************************
+//
+//! Causes a processor trigger for a sample sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number, with
+//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it.
+//!
+//! This function triggers a processor-initiated sample sequence if the sample
+//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.  If
+//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the
+//! processor-initiated trigger is delayed until a later processor-initiated
+//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL,
+//! allowing multiple ADCs to start from a processor-initiated trigger in a
+//! synchronous manner.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Generate a processor trigger for this sample sequence.
+    //
+    HWREG(ui32Base + ADC_O_PSSI) |= ((ui32SequenceNum & 0xffff0000) |
+                                     (1 << (ui32SequenceNum & 0xf)));
+}
+
+//*****************************************************************************
+//
+//! Configures the software oversampling factor of the ADC.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param ui32Factor is the number of samples to be averaged.
+//!
+//! This function configures the software oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data.  Oversampling is
+//! accomplished by averaging multiple samples from the same analog input.
+//! Three different oversampling rates are supported; 2x, 4x, and 8x.
+//!
+//! Oversampling is only supported on the sample sequencers that are more than
+//! one sample in depth (that is, the fourth sample sequencer is not
+//! supported).  Oversampling by 2x (for example) divides the depth of the
+//! sample sequencer by two; so 2x oversampling on the first sample sequencer
+//! can only provide four samples per trigger.  This also means that 8x
+//! oversampling is only available on the first sample sequencer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                               uint32_t ui32Factor)
+{
+    uint32_t ui32Value;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 3);
+    ASSERT(((ui32Factor == 2) || (ui32Factor == 4) || (ui32Factor == 8)) &&
+           ((ui32SequenceNum == 0) || (ui32Factor != 8)));
+
+    //
+    // Convert the oversampling factor to a shift factor.
+    //
+    for(ui32Value = 0, ui32Factor >>= 1; ui32Factor;
+        ui32Value++, ui32Factor >>= 1)
+    {
+    }
+
+    //
+    // Save the shift factor.
+    //
+    g_pui8OversampleFactor[ui32SequenceNum] = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! Configures a step of the software oversampled sequencer.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param ui32Step is the step to be configured.
+//! \param ui32Config is the configuration of this step.
+//!
+//! This function configures a step of the sample sequencer when using the
+//! software oversampling feature.  The number of steps available depends on
+//! the oversampling factor set by ADCSoftwareOversampleConfigure().  The value
+//! of \e ui32Config is the same as defined for ADCSequenceStepConfigure().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                                   uint32_t ui32Step, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 3);
+    ASSERT(((ui32SequenceNum == 0) &&
+            (ui32Step < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) ||
+           (ui32Step < (4 >> g_pui8OversampleFactor[ui32SequenceNum])));
+
+    //
+    // Get the offset of the sequence to be configured.
+    //
+    ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
+
+    //
+    // Compute the shift for the bits that control this step.
+    //
+    ui32Step *= 4 << g_pui8OversampleFactor[ui32SequenceNum];
+
+    //
+    // Loop through the hardware steps that make up this step of the software
+    // oversampled sequence.
+    //
+    for(ui32SequenceNum = 1 << g_pui8OversampleFactor[ui32SequenceNum];
+        ui32SequenceNum; ui32SequenceNum--)
+    {
+        //
+        // Set the analog mux value for this step.
+        //
+        HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) &
+                                        ~(0x0000000f << ui32Step)) |
+                                       ((ui32Config & 0x0f) << ui32Step));
+
+        //
+        // Set the upper bits of the analog mux value for this step.
+        //
+        HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) &
+                                         ~(0x0000000f << ui32Step)) |
+                                        (((ui32Config & 0xf00) >> 8) <<
+                                         ui32Step));
+
+        //
+        // Set the control value for this step.
+        //
+        HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) &
+                                        ~(0x0000000f << ui32Step)) |
+                                       (((ui32Config & 0xf0) >> 4) <<
+                                        ui32Step));
+        if(ui32SequenceNum != 1)
+        {
+            HWREG(ui32Base + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
+                                              ADC_SSCTL0_END0) << ui32Step);
+        }
+
+        //
+        // Go to the next hardware step.
+        //
+        ui32Step += 4;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence using software oversampling.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//! \param pui32Buffer is the address where the data is stored.
+//! \param ui32Count is the number of samples to be read.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer with software oversampling applied.  The requested
+//! number of samples are copied into the data buffer; if there are not enough
+//! samples in the hardware FIFO to satisfy this many oversampled data items,
+//! then incorrect results are returned.  It is the caller's responsibility to
+//! read only the samples that are available and wait until enough data is
+//! available, for example as a result of receiving an interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                             uint32_t *pui32Buffer, uint32_t ui32Count)
+{
+    uint32_t ui32Idx, ui32Accum;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 3);
+    ASSERT(((ui32SequenceNum == 0) &&
+            (ui32Count < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) ||
+           (ui32Count < (4 >> g_pui8OversampleFactor[ui32SequenceNum])));
+
+    //
+    // Get the offset of the sequence to be read.
+    //
+    ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
+
+    //
+    // Read the samples from the FIFO until it is empty.
+    //
+    while(ui32Count--)
+    {
+        //
+        // Compute the sum of the samples.
+        //
+        ui32Accum = 0;
+        for(ui32Idx = 1 << g_pui8OversampleFactor[ui32SequenceNum]; ui32Idx;
+            ui32Idx--)
+        {
+            //
+            // Read the FIFO and add it to the accumulator.
+            //
+            ui32Accum += HWREG(ui32Base + ADC_SSFIFO);
+        }
+
+        //
+        // Write the averaged sample to the output buffer.
+        //
+        *pui32Buffer++ = ui32Accum >> g_pui8OversampleFactor[ui32SequenceNum];
+    }
+}
+
+//*****************************************************************************
+//
+//! Configures the hardware oversampling factor of the ADC.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Factor is the number of samples to be averaged.
+//!
+//! This function configures the hardware oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data.  Oversampling is
+//! accomplished by averaging multiple samples from the same analog input.  Six
+//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
+//! Specifying an oversampling factor of zero disables hardware
+//! oversampling.
+//!
+//! Hardware oversampling applies uniformly to all sample sequencers.  It does
+//! not reduce the depth of the sample sequencers like the software
+//! oversampling APIs; each sample written into the sample sequencer FIFO is a
+//! fully oversampled analog input reading.
+//!
+//! Enabling hardware averaging increases the precision of the ADC at the cost
+//! of throughput.  For example, enabling 4x oversampling reduces the
+//! throughput of a 250 k samples/second ADC to 62.5 k samples/second.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCHardwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32Factor)
+{
+    uint32_t ui32Value;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(((ui32Factor == 0) || (ui32Factor == 2) || (ui32Factor == 4) ||
+            (ui32Factor == 8) || (ui32Factor == 16) || (ui32Factor == 32) ||
+            (ui32Factor == 64)));
+
+    //
+    // Convert the oversampling factor to a shift factor.
+    //
+    for(ui32Value = 0, ui32Factor >>= 1; ui32Factor;
+        ui32Value++, ui32Factor >>= 1)
+    {
+    }
+
+    //
+    // Write the shift factor to the ADC to configure the hardware oversampler.
+    //
+    HWREG(ui32Base + ADC_O_SAC) = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! Configures an ADC digital comparator.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Comp is the index of the comparator to configure.
+//! \param ui32Config is the configuration of the comparator.
+//!
+//! This function configures a comparator.  The \e ui32Config parameter is
+//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
+//! \b ADC_COMP_INT_xxx values.
+//!
+//! The \b ADC_COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
+//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band.
+//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the low-band.
+//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into low-band only if ADC output has been in the
+//! high-band since the last trigger output.
+//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the mid-band.
+//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the mid-band.
+//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into high-band only if ADC output has been in the
+//! low-band since the last trigger output.
+//!
+//! The \b ADC_COMP_INT_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
+//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band.
+//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the low-band.
+//! - \b ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
+//! transitions into low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the mid-band.
+//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the mid-band.
+//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band.
+//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the high-band.
+//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
+//! transitions into high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
+                       uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32Comp < 8);
+
+    //
+    // Save the new setting.
+    //
+    HWREG(ui32Base + ADC_O_DCCTL0 + (ui32Comp * 4)) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Defines the ADC digital comparator regions.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Comp is the index of the comparator to configure.
+//! \param ui32LowRef is the reference point for the low/mid band threshold.
+//! \param ui32HighRef is the reference point for the mid/high band threshold.
+//!
+//! The ADC digital comparator operation is based on three ADC value regions:
+//! - \b low-band is defined as any ADC value less than or equal to the
+//!   \e ui32LowRef value.
+//! - \b mid-band is defined as any ADC value greater than the \e ui32LowRef
+//!   value but less than or equal to the \e ui32HighRef value.
+//! - \b high-band is defined as any ADC value greater than the \e ui32HighRef
+//!   value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
+                       uint32_t ui32LowRef, uint32_t ui32HighRef)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32Comp < 8);
+    ASSERT((ui32LowRef < 4096) && (ui32LowRef <= ui32HighRef));
+    ASSERT(ui32HighRef < 4096);
+
+    //
+    // Save the new region settings.
+    //
+    HWREG(ui32Base + ADC_O_DCCMP0 + (ui32Comp * 4)) = ((ui32HighRef << 16) |
+                                                       ui32LowRef);
+}
+
+//*****************************************************************************
+//
+//! Resets the current ADC digital comparator conditions.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Comp is the index of the comparator.
+//! \param bTrigger is the flag to indicate reset of Trigger conditions.
+//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
+//!
+//! Because the digital comparator uses current and previous ADC values, this
+//! function allows the comparator to be reset to its initial
+//! value to prevent stale data from being used when a sequence is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, bool bTrigger,
+                   bool bInterrupt)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32Comp < 8);
+
+    //
+    // Set the appropriate bits to reset the trigger and/or interrupt
+    // comparator conditions.
+    //
+    ui32Temp = 0;
+    if(bTrigger)
+    {
+        ui32Temp |= (1 << (16 + ui32Comp));
+    }
+    if(bInterrupt)
+    {
+        ui32Temp |= (1 << ui32Comp);
+    }
+
+    HWREG(ui32Base + ADC_O_DCRIC) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence comparator interrupt.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Disable this sample sequence comparator interrupt.
+    //
+    HWREG(ui32Base + ADC_O_IM) &= ~(0x10000 << ui32SequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence comparator interrupt.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Enable this sample sequence interrupt.
+    //
+    HWREG(ui32Base + ADC_O_IM) |= 0x10000 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator interrupt status.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//!
+//! This function returns the digital comparator interrupt status bits.  This
+//! status is sequence agnostic.
+//!
+//! \return The current comparator interrupt status.
+//
+//*****************************************************************************
+uint32_t
+ADCComparatorIntStatus(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Return the digital comparator interrupt status.
+    //
+    return(HWREG(ui32Base + ADC_O_DCISC));
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence comparator interrupt source.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Status is the bit-mapped interrupts status to clear.
+//!
+//! The specified interrupt status is cleared.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Clear the interrupt.
+    //
+    HWREG(ui32Base + ADC_O_DCISC) = ui32Status;
+}
+
+//*****************************************************************************
+//
+//! Disables ADC interrupt sources.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! This function disables the indicated ADC interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0.
+//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1.
+//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2.
+//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3.
+//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0.
+//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1.
+//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2.
+//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3.
+//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample
+//!   sequence 0.
+//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample
+//!   sequence 1.
+//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample
+//!   sequence 2.
+//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample
+//!   sequence 3.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Disable the requested interrupts.
+    //
+    HWREG(ui32Base + ADC_O_IM) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enables ADC interrupt sources.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! This function enables the indicated ADC interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0.
+//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1.
+//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2.
+//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3.
+//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0.
+//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1.
+//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2.
+//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3.
+//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample
+//!   sequence 0.
+//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample
+//!   sequence 1.
+//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample
+//!   sequence 2.
+//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample
+//!   sequence 3.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Enable the requested interrupts.
+    //
+    HWREG(ui32Base + ADC_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified ADC module.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status is returned.
+//!
+//! \return Returns the current interrupt status for the specified ADC module.
+//! The value returned is the logical OR of the \b ADC_INT_* values that are
+//! currently active.
+//
+//*****************************************************************************
+uint32_t
+ADCIntStatusEx(uint32_t ui32Base, bool bMasked)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Return either the masked interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        ui32Temp = HWREG(ui32Base + ADC_O_ISC);
+    }
+    else
+    {
+        //
+        // Read the Raw interrupt status to see if a digital comparator
+        // interrupt is active.
+        //
+        ui32Temp = HWREG(ui32Base + ADC_O_RIS);
+
+        //
+        // Since, the raw interrupt status only indicates that any one of the
+        // digital comparators caused an interrupt, if the raw interrupt status
+        // is set then the return value is modified to indicate that all sample
+        // sequences have a pending digital comparator interrupt.
+        // This is exactly how the hardware works so the return code is
+        // modified to match this behavior.
+        //
+        if(ui32Temp & ADC_RIS_INRDC)
+        {
+            ui32Temp |= (ADC_INT_DCON_SS3 | ADC_INT_DCON_SS2 |
+                         ADC_INT_DCON_SS1 | ADC_INT_DCON_SS0);
+        }
+    }
+    return(ui32Temp);
+}
+
+//*****************************************************************************
+//
+//! Clears the specified ADC interrupt sources.
+//!
+//! \param ui32Base is the base address of the ADC port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! Clears the interrupt for the specified interrupt source(s).
+//!
+//! The \e ui32IntFlags parameter is the logical OR of the \b ADC_INT_* values.
+//! See the ADCIntEnableEx() function for the list of possible \b ADC_INT*
+//! values.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    HWREG(ui32Base + ADC_O_ISC) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Selects the ADC reference.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Ref is the reference to use.
+//!
+//! The ADC reference is set as specified by \e ui32Ref.  It must be one of
+//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or
+//! external reference.  If \b ADC_REF_INT is chosen, then an internal 3V
+//! reference is used and no external reference is needed.  If
+//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the
+//! AVREF pin.  If \b ADC_REF_EXT_1V is chosen, then a 1V external reference
+//! must be supplied to the AVREF pin.
+//!
+//! \note The ADC reference can only be selected on parts that have an external
+//! reference.  Consult the data sheet for your part to determine if there is
+//! an external reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V) ||
+           (ui32Ref == ADC_REF_EXT_1V));
+
+    //
+    // Set the reference.
+    //
+    HWREG(ui32Base + ADC_O_CTL) =
+        (HWREG(ui32Base + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ui32Ref;
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting of the ADC reference.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//!
+//! Returns the value of the ADC reference setting.  The returned value is one
+//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V.
+//!
+//! \note The value returned by this function is only meaningful if used on a
+//! part that is capable of using an external reference.  Consult the data
+//! sheet for your part to determine if it has an external reference input.
+//!
+//! \return The current setting of the ADC reference.
+//
+//*****************************************************************************
+uint32_t
+ADCReferenceGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Return the value of the reference.
+    //
+    return(HWREG(ui32Base + ADC_O_CTL) & ADC_CTL_VREF_M);
+}
+
+//*****************************************************************************
+//
+//! Sets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32Phase is the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//!
+//! This function sets the phase delay between the detection of an ADC trigger
+//! event and the start of the sample sequence.  By selecting a different phase
+//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and
+//! \b ADC_PHASE_180) and having each ADC module sample the same analog input,
+//! it is possible to increase the sampling rate of the analog input (with
+//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1,
+//! N+3, N+5, and so on, coming from the second ADC).  The ADC module has a
+//! single phase delay that is applied to all sample sequences within that
+//! module.
+//!
+//! \note This capability is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT((ui32Phase == ADC_PHASE_0) || (ui32Phase == ADC_PHASE_22_5) ||
+           (ui32Phase == ADC_PHASE_45) || (ui32Phase == ADC_PHASE_67_5) ||
+           (ui32Phase == ADC_PHASE_90) || (ui32Phase == ADC_PHASE_112_5) ||
+           (ui32Phase == ADC_PHASE_135) || (ui32Phase == ADC_PHASE_157_5) ||
+           (ui32Phase == ADC_PHASE_180) || (ui32Phase == ADC_PHASE_202_5) ||
+           (ui32Phase == ADC_PHASE_225) || (ui32Phase == ADC_PHASE_247_5) ||
+           (ui32Phase == ADC_PHASE_270) || (ui32Phase == ADC_PHASE_292_5) ||
+           (ui32Phase == ADC_PHASE_315) || (ui32Phase == ADC_PHASE_337_5));
+
+    //
+    // Set the phase delay.
+    //
+    HWREG(ui32Base + ADC_O_SPC) = ui32Phase;
+}
+
+//*****************************************************************************
+//
+//! Gets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//!
+//! This function gets the current phase delay between the detection of an ADC
+//! trigger event and the start of the sample sequence.
+//!
+//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//
+//*****************************************************************************
+uint32_t
+ADCPhaseDelayGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Return the phase delay.
+    //
+    return(HWREG(ui32Base + ADC_O_SPC));
+}
+
+//*****************************************************************************
+//
+//! Enables DMA for sample sequencers.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! Allows DMA requests to be generated based on the FIFO level of the sample
+//! sequencer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Enable the DMA on the specified sequencer.
+    //
+    HWREG(ui32Base + ADC_O_ACTSS) |= 0x100 << ui32SequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Disables DMA for sample sequencers.
+//!
+//! \param ui32Base is the base address of the ADC module.
+//! \param ui32SequenceNum is the sample sequence number.
+//!
+//! Prevents the specified sample sequencer from generating DMA requests.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT(ui32SequenceNum < 4);
+
+    //
+    // Disable the DMA on the specified sequencer.
+    //
+    HWREG(ui32Base + ADC_O_ACTSS) &= ~(0x100 << ui32SequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Determines whether the ADC is busy or not.
+//!
+//! \param ui32Base is the base address of the ADC.
+//!
+//! This function allows the caller to determine whether or not the ADC is
+//! currently sampling .  If \b false is returned, then the ADC is not
+//! sampling data.
+//!
+//! Use this function to detect that the ADC is finished sampling data before
+//! putting the device into deep sleep.  Before using this function, it is
+//! highly recommended that the event trigger is changed to
+//! \b ADC_TRIGGER_NEVER on all enabled sequencers to prevent the ADC from
+//! starting after checking the busy status.
+//!
+//! \return Returns \b true if the ADC is sampling or \b false if all
+//! samples are complete.
+//
+//*****************************************************************************
+bool
+ADCBusy(uint32_t ui32Base)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+
+    //
+    // Determine if the ADC is busy.
+    //
+    return((HWREG(ui32Base + ADC_O_ACTSS) & ADC_ACTSS_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the clock configuration for the ADC.
+//!
+//! \param ui32Base is the base address of the ADC to configure, which must
+//! always be \b ADC0_BASE.
+//! \param ui32Config is a combination of the \b ADC_CLOCK_SRC_ and
+//! \b ADC_CLOCK_RATE_* values used to configure the ADC clock input.
+//! \param ui32ClockDiv is the input clock divider for the clock selected by
+//! the \b ADC_CLOCK_SRC value.
+//!
+//! This function is used to configure the input clock to the ADC modules.  The
+//! clock configuration is shared across ADC units so \e ui32Base must
+//! always be \b ADC0_BASE.  The \e ui32Config value is logical OR of one
+//! of the \b ADC_CLOCK_RATE_ and one of the \b ADC_CLOCK_SRC_ values defined
+//! below. The \b ADC_CLOCK_SRC_* values determine the input clock for the ADC.
+//! Not all values are available on all devices so check the device data sheet
+//! to determine value configuration options.  Regardless of the source, the
+//! final frequency for TM4C123x devices must be 16 MHz and for TM4C129x parts
+//! after dividing must be between 16 and 32 MHz.
+//!
+//! \note For TM4C123x devices, if the PLL is enabled, the PLL/25 is used as
+//! the ADC clock unless ADC_CLOCK_SRC_PIOSC is specified.  If the PLL is
+//! disabled, the MOSC is used as the clock source unless ADC_CLOCK_SRC_PIOSC
+//! is specified.
+//!
+//! - \b ADC_CLOCK_SRC_PLL - The main PLL output (TM4x129 class only).
+//! - \b ADC_CLOCK_SRC_PIOSC - The internal PIOSC at 16 MHz.
+//! - \b ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control
+//!   module (TM4x129 class only).
+//! - \b ADC_CLOCK_SRC_MOSC - The external MOSC (TM4x129 class only).
+//!
+//! \b ADC_CLOCK_RATE values control how often samples are provided back to the
+//! application.  The values are the following:
+//!
+//! - \b ADC_CLOCK_RATE_FULL - All samples.
+//! - \b ADC_CLOCK_RATE_HALF - Every other sample.
+//! - \b ADC_CLOCK_RATE_QUARTER - Every fourth sample.
+//! - \b ADC_CLOCK_RATE_EIGHTH - Every either sample.
+//!
+//! The \e ui32ClockDiv parameter allows for dividing a higher frequency down
+//! into the valid range for the ADCs.  This parameter is typically only used
+//! \b ADC_CLOCK_SRC_PLL option because it is the only clock value that can be
+//! with the in the correct range to use the divider.  The actual value ranges
+//! from 1 to 64.
+//!
+//! \b Example: ADC Clock Configurations
+//!
+//! \verbatim
+//!
+//! //
+//! // Configure the ADC to use PIOSC divided by one (16 MHz) and sample at
+//! // half the rate.
+//! //
+//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_HALF, 1);
+//!
+//! ...
+//!
+//! //
+//! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC
+//! // clock of 20 MHz.
+//! //
+//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                  uint32_t ui32ClockDiv)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ADC0_BASE);
+
+    //
+    // A rate must be supplied.
+    //
+    ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0);
+
+    //
+    // Clock must be valid divider.
+    //
+    ASSERT(((ui32ClockDiv - 1) & ~ADC_CC_CLKDIV_M) == 0);
+
+    //
+    // Write the sample conversion rate.
+    //
+    HWREG(ui32Base + ADC_O_PC) = (ui32Config >> 4) & ADC_PC_SR_M;
+
+    //
+    // Write the clock select and divider.
+    //
+    HWREG(ui32Base + ADC_O_CC) = (ui32Config & ADC_CC_CS_M) |
+                                 (((ui32ClockDiv - 1) << ADC_CC_CLKDIV_S)) ;
+}
+
+//*****************************************************************************
+//
+//! Returns the clock configuration for the ADC.
+//!
+//! \param ui32Base is the base address of the ADC to configure, which must
+//! always be \b ADC0_BASE.
+//! \param pui32ClockDiv is a pointer to the input clock divider for the clock
+//! selected by the \b ADC_CLOCK_SRC in use by the ADCs.
+//!
+//! This function returns the ADC clock configuration and the clock divider for
+//! the ADCs.
+//!
+//! \b Example: Read the current ADC clock configuration.
+//!
+//! \verbatim
+//! uint32_t ui32Config, ui32ClockDiv;
+//!
+//! //
+//! // Read the current ADC clock configuration.
+//! //
+//! ui32Config = ADCClockConfigGet(ADC0_BASE, &ui32ClockDiv);
+//! \endverbatim
+//!
+//! \return The current clock configuration of the ADC defined as a combination
+//! of one of \b ADC_CLOCK_SRC_PLL, \b ADC_CLOCK_SRC_PIOSC,
+//! \b ADC_CLOCK_SRC_MOSC, or \b ADC_CLOCK_SRC_ALTCLK logical ORed with one of
+//! \b ADC_CLOCK_RATE_FULL, \b ADC_CLOCK_RATE_HALF, \b ADC_CLOCK_RATE_QUARTER,
+//! or \b ADC_CLOCK_RATE_EIGHTH.  See ADCClockConfigSet() for more information
+//! on these values.
+//
+//*****************************************************************************
+uint32_t
+ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv)
+{
+    uint32_t ui32Config;
+
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ADC0_BASE);
+
+    //
+    // Read the current configuration.
+    //
+    ui32Config = HWREG(ui32Base + ADC_O_CC);
+
+    //
+    // If the clock divider was requested provide the current value.
+    //
+    if(pui32ClockDiv)
+    {
+        *pui32ClockDiv =
+                    ((ui32Config & ADC_CC_CLKDIV_M) >> ADC_CC_CLKDIV_S) + 1;
+    }
+
+    //
+    // Clear out the divider bits.
+    //
+    ui32Config &= ~ADC_CC_CLKDIV_M;
+
+    //
+    // Add in the sample interval to the configuration.
+    //
+    ui32Config = (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4;
+
+    return(ui32Config);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/adc.h b/bsp/tm4c129x/libraries/driverlib/adc.h
new file mode 100644
index 0000000000..a0e00e64b6
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/adc.h
@@ -0,0 +1,328 @@
+//*****************************************************************************
+//
+// adc.h - ADC headers for using the ADC driver functions.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_ADC_H__
+#define __DRIVERLIB_ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceConfigure as the ui32Trigger
+// parameter.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_PROCESSOR   0x00000000  // Processor event
+#define ADC_TRIGGER_COMP0       0x00000001  // Analog comparator 0 event
+#define ADC_TRIGGER_COMP1       0x00000002  // Analog comparator 1 event
+#define ADC_TRIGGER_COMP2       0x00000003  // Analog comparator 2 event
+#define ADC_TRIGGER_EXTERNAL    0x00000004  // External event
+#define ADC_TRIGGER_TIMER       0x00000005  // Timer event
+#define ADC_TRIGGER_PWM0        0x00000006  // PWM0 event
+#define ADC_TRIGGER_PWM1        0x00000007  // PWM1 event
+#define ADC_TRIGGER_PWM2        0x00000008  // PWM2 event
+#define ADC_TRIGGER_PWM3        0x00000009  // PWM3 event
+#define ADC_TRIGGER_NEVER       0x0000000E  // Never Trigger
+#define ADC_TRIGGER_ALWAYS      0x0000000F  // Always event
+#define ADC_TRIGGER_PWM_MOD0    0x00000000  // PWM triggers from PWM0
+#define ADC_TRIGGER_PWM_MOD1    0x00000010  // PWM triggers from PWM1
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceStepConfigure as the ui32Config
+// parameter.
+//
+//*****************************************************************************
+#define ADC_CTL_TS              0x00000080  // Temperature sensor select
+#define ADC_CTL_IE              0x00000040  // Interrupt enable
+#define ADC_CTL_END             0x00000020  // Sequence end select
+#define ADC_CTL_D               0x00000010  // Differential select
+#define ADC_CTL_CH0             0x00000000  // Input channel 0
+#define ADC_CTL_CH1             0x00000001  // Input channel 1
+#define ADC_CTL_CH2             0x00000002  // Input channel 2
+#define ADC_CTL_CH3             0x00000003  // Input channel 3
+#define ADC_CTL_CH4             0x00000004  // Input channel 4
+#define ADC_CTL_CH5             0x00000005  // Input channel 5
+#define ADC_CTL_CH6             0x00000006  // Input channel 6
+#define ADC_CTL_CH7             0x00000007  // Input channel 7
+#define ADC_CTL_CH8             0x00000008  // Input channel 8
+#define ADC_CTL_CH9             0x00000009  // Input channel 9
+#define ADC_CTL_CH10            0x0000000A  // Input channel 10
+#define ADC_CTL_CH11            0x0000000B  // Input channel 11
+#define ADC_CTL_CH12            0x0000000C  // Input channel 12
+#define ADC_CTL_CH13            0x0000000D  // Input channel 13
+#define ADC_CTL_CH14            0x0000000E  // Input channel 14
+#define ADC_CTL_CH15            0x0000000F  // Input channel 15
+#define ADC_CTL_CH16            0x00000100  // Input channel 16
+#define ADC_CTL_CH17            0x00000101  // Input channel 17
+#define ADC_CTL_CH18            0x00000102  // Input channel 18
+#define ADC_CTL_CH19            0x00000103  // Input channel 19
+#define ADC_CTL_CH20            0x00000104  // Input channel 20
+#define ADC_CTL_CH21            0x00000105  // Input channel 21
+#define ADC_CTL_CH22            0x00000106  // Input channel 22
+#define ADC_CTL_CH23            0x00000107  // Input channel 23
+#define ADC_CTL_CMP0            0x00080000  // Select Comparator 0
+#define ADC_CTL_CMP1            0x00090000  // Select Comparator 1
+#define ADC_CTL_CMP2            0x000A0000  // Select Comparator 2
+#define ADC_CTL_CMP3            0x000B0000  // Select Comparator 3
+#define ADC_CTL_CMP4            0x000C0000  // Select Comparator 4
+#define ADC_CTL_CMP5            0x000D0000  // Select Comparator 5
+#define ADC_CTL_CMP6            0x000E0000  // Select Comparator 6
+#define ADC_CTL_CMP7            0x000F0000  // Select Comparator 7
+#define ADC_CTL_SHOLD_4         0x00000000  // Sample and hold 4 ADC clocks
+#define ADC_CTL_SHOLD_8         0x00200000  // Sample and hold 8 ADC clocks
+#define ADC_CTL_SHOLD_16        0x00400000  // Sample and hold 16 ADC clocks
+#define ADC_CTL_SHOLD_32        0x00600000  // Sample and hold 32 ADC clocks
+#define ADC_CTL_SHOLD_64        0x00800000  // Sample and hold 64 ADC clocks
+#define ADC_CTL_SHOLD_128       0x00A00000  // Sample and hold 128 ADC clocks
+#define ADC_CTL_SHOLD_256       0x00C00000  // Sample and hold 256 ADC clocks
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCComparatorConfigure as part of the
+// ui32Config parameter.
+//
+//*****************************************************************************
+#define ADC_COMP_TRIG_NONE      0x00000000  // Trigger Disabled
+#define ADC_COMP_TRIG_LOW_ALWAYS \
+                                0x00001000  // Trigger Low Always
+#define ADC_COMP_TRIG_LOW_ONCE  0x00001100  // Trigger Low Once
+#define ADC_COMP_TRIG_LOW_HALWAYS \
+                                0x00001200  // Trigger Low Always (Hysteresis)
+#define ADC_COMP_TRIG_LOW_HONCE 0x00001300  // Trigger Low Once (Hysteresis)
+#define ADC_COMP_TRIG_MID_ALWAYS \
+                                0x00001400  // Trigger Mid Always
+#define ADC_COMP_TRIG_MID_ONCE  0x00001500  // Trigger Mid Once
+#define ADC_COMP_TRIG_HIGH_ALWAYS \
+                                0x00001C00  // Trigger High Always
+#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00  // Trigger High Once
+#define ADC_COMP_TRIG_HIGH_HALWAYS \
+                                0x00001E00  // Trigger High Always (Hysteresis)
+#define ADC_COMP_TRIG_HIGH_HONCE \
+                                0x00001F00  // Trigger High Once (Hysteresis)
+
+#define ADC_COMP_INT_NONE       0x00000000  // Interrupt Disabled
+#define ADC_COMP_INT_LOW_ALWAYS \
+                                0x00000010  // Interrupt Low Always
+#define ADC_COMP_INT_LOW_ONCE   0x00000011  // Interrupt Low Once
+#define ADC_COMP_INT_LOW_HALWAYS \
+                                0x00000012  // Interrupt Low Always
+                                            // (Hysteresis)
+#define ADC_COMP_INT_LOW_HONCE  0x00000013  // Interrupt Low Once (Hysteresis)
+#define ADC_COMP_INT_MID_ALWAYS \
+                                0x00000014  // Interrupt Mid Always
+#define ADC_COMP_INT_MID_ONCE   0x00000015  // Interrupt Mid Once
+#define ADC_COMP_INT_HIGH_ALWAYS \
+                                0x0000001C  // Interrupt High Always
+#define ADC_COMP_INT_HIGH_ONCE  0x0000001D  // Interrupt High Once
+#define ADC_COMP_INT_HIGH_HALWAYS \
+                                0x0000001E  // Interrupt High Always
+                                            // (Hysteresis)
+#define ADC_COMP_INT_HIGH_HONCE \
+                                0x0000001F  // Interrupt High Once (Hysteresis)
+
+//*****************************************************************************
+//
+// Values that can be used to modify the sequence number passed to
+// ADCProcessorTrigger in order to get cross-module synchronous processor
+// triggers.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_WAIT        0x08000000  // Wait for the synchronous trigger
+#define ADC_TRIGGER_SIGNAL      0x80000000  // Signal the synchronous trigger
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and
+// returned from ADCPhaseDelayGet.
+//
+//*****************************************************************************
+#define ADC_PHASE_0             0x00000000  // 0 degrees
+#define ADC_PHASE_22_5          0x00000001  // 22.5 degrees
+#define ADC_PHASE_45            0x00000002  // 45 degrees
+#define ADC_PHASE_67_5          0x00000003  // 67.5 degrees
+#define ADC_PHASE_90            0x00000004  // 90 degrees
+#define ADC_PHASE_112_5         0x00000005  // 112.5 degrees
+#define ADC_PHASE_135           0x00000006  // 135 degrees
+#define ADC_PHASE_157_5         0x00000007  // 157.5 degrees
+#define ADC_PHASE_180           0x00000008  // 180 degrees
+#define ADC_PHASE_202_5         0x00000009  // 202.5 degrees
+#define ADC_PHASE_225           0x0000000A  // 225 degrees
+#define ADC_PHASE_247_5         0x0000000B  // 247.5 degrees
+#define ADC_PHASE_270           0x0000000C  // 270 degrees
+#define ADC_PHASE_292_5         0x0000000D  // 292.5 degrees
+#define ADC_PHASE_315           0x0000000E  // 315 degrees
+#define ADC_PHASE_337_5         0x0000000F  // 337.5 degrees
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCReferenceSet as the ui32Ref parameter.
+//
+//*****************************************************************************
+#define ADC_REF_INT             0x00000000  // Internal reference
+#define ADC_REF_EXT_3V          0x00000001  // External 3V reference
+#define ADC_REF_EXT_1V          0x00000003  // External 1V reference
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
+// ADCIntClearEx() and ADCIntStatusEx().
+//
+//*****************************************************************************
+#define ADC_INT_SS0             0x00000001
+#define ADC_INT_SS1             0x00000002
+#define ADC_INT_SS2             0x00000004
+#define ADC_INT_SS3             0x00000008
+#define ADC_INT_DMA_SS0         0x00000100
+#define ADC_INT_DMA_SS1         0x00000200
+#define ADC_INT_DMA_SS2         0x00000400
+#define ADC_INT_DMA_SS3         0x00000800
+#define ADC_INT_DCON_SS0        0x00010000
+#define ADC_INT_DCON_SS1        0x00020000
+#define ADC_INT_DCON_SS2        0x00040000
+#define ADC_INT_DCON_SS3        0x00080000
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet().
+//
+//*****************************************************************************
+#define ADC_CLOCK_RATE_FULL     0x00000070
+#define ADC_CLOCK_RATE_HALF     0x00000050
+#define ADC_CLOCK_RATE_FOURTH   0x00000030
+#define ADC_CLOCK_RATE_EIGHTH   0x00000010
+#define ADC_CLOCK_SRC_PLL       0x00000000
+#define ADC_CLOCK_SRC_PIOSC     0x00000001
+#define ADC_CLOCK_SRC_ALTCLK    0x00000001
+#define ADC_CLOCK_SRC_MOSC      0x00000002
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                           void (*pfnHandler)(void));
+extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                             bool bMasked);
+extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                                 uint32_t ui32Trigger, uint32_t ui32Priority);
+extern void ADCSequenceStepConfigure(uint32_t ui32Base,
+                                     uint32_t ui32SequenceNum,
+                                     uint32_t ui32Step, uint32_t ui32Config);
+extern int32_t ADCSequenceOverflow(uint32_t ui32Base,
+                                   uint32_t ui32SequenceNum);
+extern void ADCSequenceOverflowClear(uint32_t ui32Base,
+                                     uint32_t ui32SequenceNum);
+extern int32_t ADCSequenceUnderflow(uint32_t ui32Base,
+                                    uint32_t ui32SequenceNum);
+extern void ADCSequenceUnderflowClear(uint32_t ui32Base,
+                                      uint32_t ui32SequenceNum);
+extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
+                                  uint32_t *pui32Buffer);
+extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base,
+                                           uint32_t ui32SequenceNum,
+                                           uint32_t ui32Factor);
+extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base,
+                                               uint32_t ui32SequenceNum,
+                                               uint32_t ui32Step,
+                                               uint32_t ui32Config);
+extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base,
+                                         uint32_t ui32SequenceNum,
+                                         uint32_t *pui32Buffer,
+                                         uint32_t ui32Count);
+extern void ADCHardwareOversampleConfigure(uint32_t ui32Base,
+                                           uint32_t ui32Factor);
+extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                              uint32_t ui32ClockDiv);
+extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv);
+
+extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
+                                   uint32_t ui32Config);
+extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
+                                   uint32_t ui32LowRef, uint32_t ui32HighRef);
+extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp,
+                               bool bTrigger, bool bInterrupt);
+extern void ADCComparatorIntDisable(uint32_t ui32Base,
+                                    uint32_t ui32SequenceNum);
+extern void ADCComparatorIntEnable(uint32_t ui32Base,
+                                   uint32_t ui32SequenceNum);
+extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base);
+extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status);
+extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked);
+extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
+extern bool ADCBusy(uint32_t ui32Base);
+extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref);
+extern uint32_t ADCReferenceGet(uint32_t ui32Base);
+extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase);
+extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base);
+extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock,
+                             uint32_t ui32Rate);
+extern uint32_t ADCSampleRateGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_ADC_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/aes.c b/bsp/tm4c129x/libraries/driverlib/aes.c
new file mode 100644
index 0000000000..f1d40d2b07
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/aes.c
@@ -0,0 +1,1305 @@
+//*****************************************************************************
+//
+// aes.c - Driver for the AES module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup aes_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_aes.h"
+#include "inc/hw_ccm.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/aes.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Resets the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//!
+//! This function performs a softreset the AES module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESReset(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Trigger the reset.
+    //
+    HWREG(ui32Base + AES_O_SYSCONFIG) |= AES_SYSCONFIG_SOFTRESET;
+
+    //
+    // Wait for the reset to finish.
+    //
+    while((HWREG(ui32Base + AES_O_SYSSTATUS) &
+           AES_SYSSTATUS_RESETDONE) == 0)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+//! Configures the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Config is the configuration of the AES module.
+//!
+//! This function configures the AES module based on the specified parameters.
+//! It does not change any DMA- or interrupt-related parameters.
+//!
+//! The ui32Config parameter is a bit-wise OR of a number of configuration
+//! flags.  The valid flags are grouped based on their function.
+//!
+//! The direction of the operation is specified with only of following flags:
+//!
+//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode
+//! - \b AES_CFG_DIR_DECRYPT - Decryption mode
+//!
+//! The key size is specified with only one of the following flags:
+//!
+//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits
+//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits
+//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits
+//!
+//! The mode of operation is specified with only one of the following flags.
+//!
+//! - \b AES_CFG_MODE_ECB - Electronic codebook mode
+//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode
+//! - \b AES_CFG_MODE_CFB - Cipher feedback mode
+//! - \b AES_CFG_MODE_CTR - Counter mode
+//! - \b AES_CFG_MODE_ICM - Integer counter mode
+//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode
+//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with
+//!   ciphertext stealing with previous/intermediate tweak value and j loaded
+//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with
+//!   ciphertext stealing with key2, i and j loaded
+//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with
+//!   ciphertext stealing with key2 and i loaded, j = 0
+//! - \b AES_CFG_MODE_F8 - F8 mode
+//! - \b AES_CFG_MODE_F9 - F9 mode
+//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication
+//!   code mode
+//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H
+//!   loaded, Y0-encrypted forced to zero and counter is not enabled.
+//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H
+//!   loaded, Y0-encrypted calculated internally and counter is enabled.
+//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH
+//!   (both H and Y0-encrypted calculated internally) and counter is enabled.
+//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode
+//!
+//! The following defines are used to specify the counter width.  It is only
+//! required to be defined when using CTR, CCM, or GCM modes, only one of the
+//! following defines must be used to specify the counter width length:
+//!
+//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits
+//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits
+//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits
+//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits
+//!
+//! Only one of the following defines must be used to specify the length field
+//! for CCM operations (L):
+//!
+//! - \b AES_CFG_CCM_L_1 - 1 byte
+//! - \b AES_CFG_CCM_L_2 - 2 bytes
+//! - \b AES_CFG_CCM_L_3 - 3 bytes
+//! - \b AES_CFG_CCM_L_4 - 4 bytes
+//! - \b AES_CFG_CCM_L_5 - 5 bytes
+//! - \b AES_CFG_CCM_L_6 - 6 bytes
+//! - \b AES_CFG_CCM_L_7 - 7 bytes
+//! - \b AES_CFG_CCM_L_8 - 8 bytes
+//!
+//! Only one of the following defines must be used to specify the length of the
+//! authentication field for CCM operations (M) through the \e ui32Config
+//! argument in the AESConfigSet() function:
+//!
+//! - \b AES_CFG_CCM_M_4 - 4 bytes
+//! - \b AES_CFG_CCM_M_6 - 6 bytes
+//! - \b AES_CFG_CCM_M_8 - 8 bytes
+//! - \b AES_CFG_CCM_M_10 - 10 bytes
+//! - \b AES_CFG_CCM_M_12 - 12 bytes
+//! - \b AES_CFG_CCM_M_14 - 14 bytes
+//! - \b AES_CFG_CCM_M_16 - 16 bytes
+//!
+//! \note When performing a basic GHASH operation for used with GCM mode, use
+//! the \b AES_CFG_MODE_GCM_HLY0ZERO and do not specify a direction.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) ||
+           (ui32Config & AES_CFG_DIR_DECRYPT));
+    ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) ||
+           (ui32Config & AES_CFG_KEY_SIZE_192BIT) ||
+           (ui32Config & AES_CFG_KEY_SIZE_256BIT));
+    ASSERT((ui32Config & AES_CFG_MODE_ECB) ||
+           (ui32Config & AES_CFG_MODE_CBC) ||
+           (ui32Config & AES_CFG_MODE_CTR) ||
+           (ui32Config & AES_CFG_MODE_ICM) ||
+           (ui32Config & AES_CFG_MODE_CFB) ||
+           (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) ||
+           (ui32Config & AES_CFG_MODE_XTS_K2IJL) ||
+           (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) ||
+           (ui32Config & AES_CFG_MODE_F8) ||
+           (ui32Config & AES_CFG_MODE_F9) ||
+           (ui32Config & AES_CFG_MODE_CTR) ||
+           (ui32Config & AES_CFG_MODE_CBCMAC) ||
+           (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) ||
+           (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) ||
+           (ui32Config & AES_CFG_MODE_GCM_HY0CALC) ||
+           (ui32Config & AES_CFG_MODE_CCM));
+    ASSERT(((ui32Config & AES_CFG_MODE_CTR) ||
+            (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) ||
+            (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) ||
+            (ui32Config & AES_CFG_MODE_GCM_HY0CALC) ||
+            (ui32Config & AES_CFG_MODE_CCM)) &&
+           ((ui32Config & AES_CFG_CTR_WIDTH_32) ||
+            (ui32Config & AES_CFG_CTR_WIDTH_64) ||
+            (ui32Config & AES_CFG_CTR_WIDTH_96) ||
+            (ui32Config & AES_CFG_CTR_WIDTH_128)));
+    ASSERT((ui32Config & AES_CFG_MODE_CCM) &&
+           ((ui32Config & AES_CFG_CCM_L_1) ||
+            (ui32Config & AES_CFG_CCM_L_2) ||
+            (ui32Config & AES_CFG_CCM_L_3) ||
+            (ui32Config & AES_CFG_CCM_L_4) ||
+            (ui32Config & AES_CFG_CCM_L_5) ||
+            (ui32Config & AES_CFG_CCM_L_6) ||
+            (ui32Config & AES_CFG_CCM_L_7) ||
+            (ui32Config & AES_CFG_CCM_L_8)) &&
+           ((ui32Config & AES_CFG_CCM_M_4) ||
+            (ui32Config & AES_CFG_CCM_M_6) ||
+            (ui32Config & AES_CFG_CCM_M_8) ||
+            (ui32Config & AES_CFG_CCM_M_10) ||
+            (ui32Config & AES_CFG_CCM_M_12) ||
+            (ui32Config & AES_CFG_CCM_M_14) ||
+            (ui32Config & AES_CFG_CCM_M_16)));
+
+    //
+    // Backup the save context field before updating the register.
+    //
+    if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT)
+    {
+        ui32Config |= AES_CTRL_SAVE_CONTEXT;
+    }
+
+    //
+    // Write the CTRL register with the new value
+    //
+    HWREG(ui32Base + AES_O_CTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Writes the key 1 configuration registers, which are used for encryption or
+//! decryption.
+//!
+//! \param ui32Base is the base address for the AES module.
+//! \param pui32Key is an array of 32-bit words, containing the key to be
+//! configured.  The least significant word in the 0th index.
+//! \param ui32Keysize is the size of the key, which must be one of the
+//! following values:  \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or
+//! \b AES_CFG_KEY_SIZE_256.
+//!
+//! This function writes key 1 configuration registers based on the key
+//! size.  This function is used in all modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) ||
+           (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) ||
+           (ui32Keysize == AES_CFG_KEY_SIZE_256BIT));
+
+    //
+    // With all key sizes, the first 4 words are written.
+    //
+    HWREG(ui32Base + AES_O_KEY1_0) = pui32Key[0];
+    HWREG(ui32Base + AES_O_KEY1_1) = pui32Key[1];
+    HWREG(ui32Base + AES_O_KEY1_2) = pui32Key[2];
+    HWREG(ui32Base + AES_O_KEY1_3) = pui32Key[3];
+
+    //
+    // The key is 192 or 256 bits.  Write the next 2 words.
+    //
+    if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT)
+    {
+        HWREG(ui32Base + AES_O_KEY1_4) = pui32Key[4];
+        HWREG(ui32Base + AES_O_KEY1_5) = pui32Key[5];
+    }
+
+    //
+    // The key is 256 bits.  Write the last 2 words.
+    //
+    if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT)
+    {
+        HWREG(ui32Base + AES_O_KEY1_6) = pui32Key[6];
+        HWREG(ui32Base + AES_O_KEY1_7) = pui32Key[7];
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes the key 2 configuration registers, which are used for encryption or
+//! decryption.
+//!
+//! \param ui32Base is the base address for the AES module.
+//! \param pui32Key is an array of 32-bit words, containing the key to be
+//! configured.  The least significant word in the 0th index.
+//! \param ui32Keysize is the size of the key, which must be one of the
+//! following values:  \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or
+//! \b AES_CFG_KEY_SIZE_256.
+//!
+//! This function writes the key 2 configuration registers based on the key
+//! size.  This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) ||
+           (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) ||
+           (ui32Keysize == AES_CFG_KEY_SIZE_256BIT));
+
+    //
+    // With all key sizes, the first 4 words are written.
+    //
+    HWREG(ui32Base + AES_O_KEY2_0) = pui32Key[0];
+    HWREG(ui32Base + AES_O_KEY2_1) = pui32Key[1];
+    HWREG(ui32Base + AES_O_KEY2_2) = pui32Key[2];
+    HWREG(ui32Base + AES_O_KEY2_3) = pui32Key[3];
+
+    //
+    // The key is 192 or 256 bits.  Write the next 2 words.
+    //
+    if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT)
+    {
+        HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[4];
+        HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[5];
+    }
+
+    //
+    // The key is 256 bits.  Write the last 2 words.
+    //
+    if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT)
+    {
+        HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[6];
+        HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[7];
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes key 3 configuration registers, which are used for encryption or
+//! decryption.
+//!
+//! \param ui32Base is the base address for the AES module.
+//! \param pui32Key is a pointer to an array of 4 words (128 bits), containing
+//! the key to be configured.  The least significant word is in the 0th index.
+//!
+//! This function writes the key 2 configuration registers with key 3 data
+//! used in CBC-MAC and F8 modes.  This key is always 128 bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Write the key into the upper 4 key registers
+    //
+    HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[0];
+    HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[1];
+    HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[2];
+    HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[3];
+}
+
+//*****************************************************************************
+//
+//! Writes the Initial Vector (IV) register, needed in some of the AES Modes.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32IVdata is an array of 4 words (128 bits), containing the IV
+//! value to be configured.  The least significant word is in the 0th index.
+//!
+//! This functions writes the initial vector registers in the AES module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Write the initial vector registers.
+    //
+    HWREG(ui32Base + AES_O_IV_IN_0) = pui32IVdata[0];
+    HWREG(ui32Base + AES_O_IV_IN_1) = pui32IVdata[1];
+    HWREG(ui32Base + AES_O_IV_IN_2) = pui32IVdata[2];
+    HWREG(ui32Base + AES_O_IV_IN_3) = pui32IVdata[3];
+}
+
+//*****************************************************************************
+//
+//! Saves the Initial Vector (IV) registers to a user-defined location.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32IVData is pointer to the location that stores the IV data.
+//!
+//! This function stores the IV for use with authenticated encryption and
+//! decryption operations.  It is assumed that the AES_CTRL_SAVE_CONTEXT
+//! bit is set in the AES_CTRL register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIVRead(uint32_t ui32Base, uint32_t *pui32IVData)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Wait for the output context to be ready.
+    //
+    while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+    {
+    }
+
+    //
+    // Read the tag data.
+    //
+    pui32IVData[0] = HWREG((ui32Base + AES_O_IV_IN_0));
+    pui32IVData[1] = HWREG((ui32Base + AES_O_IV_IN_1));
+    pui32IVData[2] = HWREG((ui32Base + AES_O_IV_IN_2));
+    pui32IVData[3] = HWREG((ui32Base + AES_O_IV_IN_3));
+}
+
+//*****************************************************************************
+//
+//! Saves the tag registers to a user-defined location.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32TagData is pointer to the location that stores the tag data.
+//!
+//! This function stores the tag data for use authenticated encryption and
+//! decryption operations.  It is assumed that the AES_CTRL_SAVE_CONTEXT
+//! bit is set in the AES_CTRL register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Wait for the output context to be ready.
+    //
+    while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+    {
+    }
+
+    //
+    // Read the tag data.
+    //
+    pui32TagData[0] = HWREG((ui32Base + AES_O_TAG_OUT_0));
+    pui32TagData[1] = HWREG((ui32Base + AES_O_TAG_OUT_1));
+    pui32TagData[2] = HWREG((ui32Base + AES_O_TAG_OUT_2));
+    pui32TagData[3] = HWREG((ui32Base + AES_O_TAG_OUT_3));
+}
+
+//*****************************************************************************
+//
+//! Used to set the write crypto data length in the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui64Length is the crypto data length in bytes.
+//!
+//! This function stores the cryptographic data length in blocks for all modes.
+//! Data lengths up to (2^61 - 1) bytes are allowed.  For GCM, any value up
+//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used.
+//! For basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the
+//! length field, indicating that the length is infinite.
+//!
+//! When this function is called, the engine is triggered to start using
+//! this context.
+//!
+//! \note This length does not include the authentication-only data used in
+//! some modes.  Use the AESAuthLengthSet() function to specify the
+//! authentication data length.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+AESLengthSet(uint32_t ui32Base, uint64_t ui64Length)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Write the length register by shifting the 64-bit ui64Length.
+    //
+    HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length);
+    HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32);
+}
+
+//*****************************************************************************
+//
+//! Sets the authentication data length in the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Length is the length in bytes.
+//!
+//! This function is only used to write the authentication data length in the
+//! combined modes (GCM or CCM) and XTS mode.  Supported AAD lengths for CCM
+//! are from 0 to (2^16 - 28) bytes.  For GCM, any value up to (2^32 - 1) can
+//! be used.  For XTS mode, this register is used to load j.  Loading of j is
+//! only required if j != 0.  j represents the sequential number of the 128-bit
+//! blocks inside the data unit.  Consequently, j must be multiplied by 16
+//! when passed to this function, thereby placing the block number in
+//! bits [31:4] of the register.
+//!
+//! When this function is called, the engine is triggered to start using
+//! this context for GCM and CCM.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Write the length into the register.
+    //
+    HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers without blocking.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32Dest is a pointer to an array of words of data.
+//!
+//! This function reads a block of either plaintext or ciphertext out of the
+//! AES module.  If the output data is not ready, the function returns
+//! false.  If the read completed successfully, the function returns true.
+//! A block is 16 bytes or 4 words.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Check if the output is ready before reading the data.  If it not ready,
+    // return false.
+    //
+    if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+    {
+        return(false);
+    }
+
+    //
+    // Read a block of data from the data registers
+    //
+    pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3);
+    pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2);
+    pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1);
+    pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0);
+
+    //
+    // Read successful, return true.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers with blocking.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32Dest is a pointer to an array of words.
+//!
+//! This function reads a block of either plaintext or ciphertext out of the
+//! AES module.  If the output is not ready, the function waits until it is
+//! ready.  A block is 16 bytes or 4 words.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Wait for the output to be ready before reading the data.
+    //
+    while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+    {
+    }
+
+    //
+    // Read a block of data from the data registers
+    //
+    pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3);
+    pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2);
+    pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1);
+    pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0);
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32Src is a pointer to an array of words of data.
+//!
+//! This function writes a block of either plaintext or ciphertext into the
+//! AES module.  If the input is not ready, the function returns false.  If the
+//! write completed successfully, the function returns true.  A block is 16
+//! bytes or 4 words.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Check if the input is ready.  If not, then return false.
+    //
+    if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))))
+    {
+        return(false);
+    }
+
+    //
+    // Write a block of data into the data registers.
+    //
+    HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0];
+    HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1];
+    HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2];
+    HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3];
+
+    //
+    // Write successful, return true.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers with blocking.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32Src is a pointer to an array of bytes.
+//!
+//! This function writes a block of either plaintext or ciphertext into the
+//! AES module.  If the input is not ready, the function waits until it is
+//! ready before performing the write.  A block is 16 bytes or 4 words.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Wait for input ready.
+    //
+    while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+    {
+    }
+
+    //
+    // Write a block of data into the data registers.
+    //
+    HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0];
+    HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1];
+    HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2];
+    HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3];
+}
+
+//*****************************************************************************
+//
+//! Used to process(transform) blocks of data, either encrypt or decrypt it.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32Src is a pointer to the memory location where the input data
+//! is stored.  The data must be padded to the 16-byte boundary.
+//! \param pui32Dest is a pointer to the memory location output is written.
+//! The space for written data must be rounded up to the 16-byte boundary.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//!
+//! This function iterates the encryption or decryption mechanism number over
+//! the data length.  Before calling this function, ensure that the AES
+//! module is properly configured the key, data size, mode, etc.  Only ECB,
+//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used.  The data
+//! is processed in 4-word (16-byte) blocks.
+//!
+//! \note This function only supports values of \e ui32Length less than 2^32,
+//! because the memory size is restricted to between 0 to 2^32 bytes.
+//!
+//! \return Returns true if data was processed successfully.  Returns false
+//! if data processing failed.
+//
+//*****************************************************************************
+bool
+AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest,
+               uint32_t ui32Length)
+{
+    uint32_t ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Write the length register first, which triggers the engine to start
+    // using this context.
+    //
+    AESLengthSet(AES_BASE, (uint64_t)ui32Length);
+
+    //
+    // Now loop until the blocks are written.
+    //
+    for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16)
+    {
+        //
+        // Write the data registers.
+        //
+        AESDataWrite(ui32Base, pui32Src + (ui32Count / 4));
+
+        //
+        // Read the data registers.
+        //
+        AESDataRead(ui32Base, pui32Dest + (ui32Count / 4));
+    }
+
+    //
+    // Return true to indicate successful completion of the function.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Used to authenticate blocks of data by generating a hash tag.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui32Src is a pointer to the memory location where the input data
+//! is stored.  The data must be padded to the 16-byte boundary.
+//! \param ui32Length  is the length of the cryptographic data in bytes.
+//! \param pui32Tag is a pointer to a 4-word array where the hash tag is
+//! written.
+//!
+//! This function processes data to produce a hash tag that can be used tor
+//! authentication.   Before calling this function, ensure that the AES
+//! module is properly configured the key, data size, mode, etc.  Only
+//! CBC-MAC and F9 modes should be used.
+//!
+//! \return Returns true if data was processed successfully.  Returns false
+//! if data processing failed.
+//
+//*****************************************************************************
+bool
+AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, uint32_t ui32Length,
+            uint32_t *pui32Tag)
+{
+    uint32_t ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Write the length register first, which triggers the engine to start
+    // using this context.
+    //
+    AESLengthSet(ui32Base, (uint64_t)ui32Length);
+
+    //
+    // Now loop until the blocks are written.
+    //
+    for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16)
+    {
+        //
+        // Write the data registers.
+        //
+        AESDataWrite(ui32Base, pui32Src + (ui32Count / 4));
+    }
+
+    //
+    // Read the hash tag value.
+    //
+    AESTagRead(ui32Base, pui32Tag);
+
+    //
+    // Return true to indicate successful completion of the function.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Processes and authenticates blocks of data, either encrypt it or decrypts
+//! it.
+//!
+//! \param ui32Base  is the base address of the AES module.
+//! \param pui32Src is a pointer to the memory location where the input data
+//! is stored.  The data must be padded to the 16-byte boundary.
+//! \param pui32Dest is a pointer to the memory location output is written.
+//! The space for written data must be rounded up to the 16-byte boundary.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//! \param pui32AuthSrc is a pointer to the memory location where the
+//! additional authentication data is stored.  The data must be padded to the
+//! 16-byte boundary.
+//! \param ui32AuthLength is the length of the additional authentication
+//! data in bytes.
+//! \param pui32Tag is a pointer to a 4-word array where the hash tag is
+//! written.
+//!
+//! This function encrypts or decrypts blocks of data in addition to
+//! authentication data.  A hash tag is also produced.  Before calling this
+//! function, ensure that the AES module is properly configured the key,
+//! data size, mode, etc.  Only CCM and GCM modes should be used.
+//!
+//! \return Returns true if data was processed successfully.  Returns false
+//! if data processing failed.
+//
+//*****************************************************************************
+bool
+AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src,
+                   uint32_t *pui32Dest, uint32_t ui32Length,
+                   uint32_t *pui32AuthSrc, uint32_t ui32AuthLength,
+                   uint32_t *pui32Tag)
+{
+    uint32_t ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Set the data length.
+    //
+    AESLengthSet(ui32Base, (uint64_t)ui32Length);
+
+    //
+    // Set the additional authentication data length.
+    //
+    AESAuthLengthSet(ui32Base, ui32AuthLength);
+
+    //
+    // Now loop until the authentication data blocks are written.
+    //
+    for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16)
+    {
+        //
+        // Write the data registers.
+        //
+        AESDataWrite(ui32Base, pui32AuthSrc + (ui32Count / 4));
+    }
+
+    //
+    // Now loop until the data blocks are written.
+    //
+    for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16)
+    {
+        //
+        // Write the data registers.
+        //
+        AESDataWrite(ui32Base, pui32Src + (ui32Count / 4));
+
+        //
+        //
+        // Read the data registers.
+        //
+        AESDataRead(ui32Base, pui32Dest + (ui32Count / 4));
+    }
+
+    //
+    // Read the hash tag value.
+    //
+    AESTagRead(ui32Base, pui32Tag);
+
+    //
+    // Return true to indicate successful completion of the function.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Returns the current AES module interrupt status.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! \return Returns a bit mask of the interrupt sources, which is a logical OR
+//! of any of the following:
+//!
+//! - \b AES_INT_CONTEXT_IN - Context interrupt
+//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt.
+//! - \b AES_INT_DATA_IN - Data input interrupt
+//! - \b AES_INT_DATA_OUT - Data output interrupt
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//!   interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//
+//*****************************************************************************
+uint32_t
+AESIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    uint32_t ui32Status, ui32Enable, ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Read the IRQ status register and return the value.
+    //
+    ui32Status = HWREG(ui32Base + AES_O_IRQSTATUS);
+    if(bMasked)
+    {
+        ui32Enable = HWREG(ui32Base + AES_O_IRQENABLE);
+        ui32Temp = HWREG(ui32Base + AES_O_DMAMIS);
+        return((ui32Status & ui32Enable) |
+               (((ui32Temp & 0x00000001) << 16) |
+                ((ui32Temp & 0x00000002) << 18) |
+                ((ui32Temp & 0x0000000c) << 15)));
+    }
+    else
+    {
+        ui32Temp = HWREG(ui32Base + AES_O_DMARIS);
+        return(ui32Status |
+               (((ui32Temp & 0x00000001) << 16) |
+                ((ui32Temp & 0x00000002) << 18) |
+                ((ui32Temp & 0x0000000c) << 15)));
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables AES module interrupts.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to enable.
+//!
+//! This function enables the interrupts in the AES module.  The
+//! \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_INT_CONTEXT_IN - Context interrupt
+//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt
+//! - \b AES_INT_DATA_IN - Data input interrupt
+//! - \b AES_INT_DATA_OUT - Data output interrupt
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//!   interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \note Interrupts that have been previously been enabled are not disabled
+//! when this function is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) ||
+           (ui32IntFlags == AES_INT_CONTEXT_OUT) ||
+           (ui32IntFlags == AES_INT_DATA_IN) ||
+           (ui32IntFlags == AES_INT_DATA_OUT) ||
+           (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||
+           (ui32IntFlags == AES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags == AES_INT_DMA_DATA_OUT));
+
+    //
+    // Set the flags.
+    //
+    HWREG(ui32Base + AES_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 16) |
+                                      ((ui32IntFlags & 0x00060000) >> 15) |
+                                      ((ui32IntFlags & 0x00080000) >> 18));
+    HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+}
+
+//*****************************************************************************
+//
+//! Disables AES module interrupts.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to disable.
+//!
+//! This function disables the interrupt sources in the AES module.  The
+//! \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_INT_CONTEXT_IN - Context interrupt
+//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt
+//! - \b AES_INT_DATA_IN - Data input interrupt
+//! - \b AES_INT_DATA_OUT - Data output interrupt
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//!   interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \note The DMA done interrupts are the only interrupts that can be cleared.
+//! The remaining interrupts can be disabled instead using AESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) ||
+           (ui32IntFlags == AES_INT_CONTEXT_OUT) ||
+           (ui32IntFlags == AES_INT_DATA_IN) ||
+           (ui32IntFlags == AES_INT_DATA_OUT) ||
+           (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||
+           (ui32IntFlags == AES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags == AES_INT_DMA_DATA_OUT));
+
+    //
+    // Clear the flags.
+    //
+    HWREG(ui32Base + AES_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 16) |
+                                       ((ui32IntFlags & 0x00060000) >> 15) |
+                                       ((ui32IntFlags & 0x00080000) >> 18));
+    HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+}
+
+//*****************************************************************************
+//
+//! Clears AES module interrupts.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to disable.
+//!
+//! This function clears the interrupt sources in the AES module.  The
+//! \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//!   interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \note Only the DMA done interrupts can be cleared.  The remaining
+//! interrupts should be disabled with AESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||
+           (ui32IntFlags == AES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags == AES_INT_DMA_DATA_OUT));
+
+    HWREG(ui32Base + AES_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 16) |
+                                     ((ui32IntFlags & 0x00060000) >> 15) |
+                                     ((ui32IntFlags & 0x00080000) >> 18));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled AES interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables AES interrupts on the interrupt controller; specific AES
+//! interrupt sources must be enabled using AESIntEnable().  The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! AESIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() is used to enable AES interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_AES0_TM4C129, pfnHandler);
+
+    //
+    // Enable the interrupt
+    //
+    IntEnable(INT_AES0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntUnregister(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_AES0_TM4C129);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_AES0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Enables uDMA requests for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Flags is a bit mask of the uDMA requests to be enabled.
+//!
+//! This function enables the uDMA request sources in the AES module.
+//! The \e ui32Flags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_DMA_DATA_IN
+//! - \b AES_DMA_DATA_OUT
+//! - \b AES_DMA_CONTEXT_IN
+//! - \b AES_DMA_CONTEXT_OUT
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32Flags == AES_DMA_DATA_IN) ||
+           (ui32Flags == AES_DMA_DATA_OUT) ||
+           (ui32Flags == AES_DMA_CONTEXT_IN) ||
+           (ui32Flags == AES_DMA_CONTEXT_OUT));
+
+    //
+    // Set the flags in the current register value.
+    //
+    HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags;
+}
+
+//*****************************************************************************
+//
+//! Disables uDMA requests for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Flags is a bit mask of the uDMA requests to be disabled.
+//!
+//! This function disables the uDMA request sources in the AES module.
+//! The \e ui32Flags parameter is the logical OR of any of the
+//! following:
+//!
+//! - \b AES_DMA_DATA_IN
+//! - \b AES_DMA_DATA_OUT
+//! - \b AES_DMA_CONTEXT_IN
+//! - \b AES_DMA_CONTEXT_OUT
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == AES_BASE);
+    ASSERT((ui32Flags == AES_DMA_DATA_IN) ||
+           (ui32Flags == AES_DMA_DATA_OUT) ||
+           (ui32Flags == AES_DMA_CONTEXT_IN) ||
+           (ui32Flags == AES_DMA_CONTEXT_OUT));
+
+    //
+    // Clear the flags in the current register value.
+    //
+    HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/aes.h b/bsp/tm4c129x/libraries/driverlib/aes.h
new file mode 100644
index 0000000000..0b8919f13e
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/aes.h
@@ -0,0 +1,218 @@
+//*****************************************************************************
+//
+// aes.h - Defines and Macros for the AES module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_AES_H__
+#define __DRIVERLIB_AES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operation direction in the
+// ui32Config argument in the AESConfig function.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_DIR_ENCRYPT     0x00000004
+#define AES_CFG_DIR_DECRYPT     0x00000000
+
+//*****************************************************************************
+//
+// The following defines are used to specify the key size in the ui32Config
+// argument in the AESConfig function.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_KEY_SIZE_128BIT 0x00000008
+#define AES_CFG_KEY_SIZE_192BIT 0x00000010
+#define AES_CFG_KEY_SIZE_256BIT 0x00000018
+
+//*****************************************************************************
+//
+// The following defines are used to specify the mode of operation in the
+// ui32Config argument in the AESConfig function.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_MODE_M          0x2007fe60
+#define AES_CFG_MODE_ECB        0x00000000
+#define AES_CFG_MODE_CBC        0x00000020
+#define AES_CFG_MODE_CTR        0x00000040
+#define AES_CFG_MODE_ICM        0x00000200
+#define AES_CFG_MODE_CFB        0x00000400
+#define AES_CFG_MODE_XTS_TWEAKJL \
+                                0x00000800
+#define AES_CFG_MODE_XTS_K2IJL \
+                                0x00001000
+#define AES_CFG_MODE_XTS_K2ILJ0 \
+                                0x00001800
+#define AES_CFG_MODE_F8         0x00002000
+#define AES_CFG_MODE_F9         0x20004000
+#define AES_CFG_MODE_CBCMAC     0x20008000
+#define AES_CFG_MODE_GCM_HLY0ZERO \
+                                0x20010000
+#define AES_CFG_MODE_GCM_HLY0CALC \
+                                0x20020040
+#define AES_CFG_MODE_GCM_HY0CALC \
+                                0x20030040
+#define AES_CFG_MODE_CCM        0x20040040
+
+//*****************************************************************************
+//
+// The following defines are used to specify the counter width in the
+// ui32Config argument in the AESConfig function.  It is only required to
+// be defined when using CTR, CCM, or GCM modes.  Only one length is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CTR_WIDTH_32    0x00000000
+#define AES_CFG_CTR_WIDTH_64    0x00000080
+#define AES_CFG_CTR_WIDTH_96    0x00000100
+#define AES_CFG_CTR_WIDTH_128   0x00000180
+
+//*****************************************************************************
+//
+// The following defines are used to define the width of the length field for
+// CCM operation through the ui32Config argument in the AESConfig function.
+// This value is also known as L.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CCM_L_1         0x00000000
+#define AES_CFG_CCM_L_2         0x00080000
+#define AES_CFG_CCM_L_3         0x00100000
+#define AES_CFG_CCM_L_4         0x00180000
+#define AES_CFG_CCM_L_5         0x00200000
+#define AES_CFG_CCM_L_6         0x00280000
+#define AES_CFG_CCM_L_7         0x00300000
+#define AES_CFG_CCM_L_8         0x00380000
+
+//*****************************************************************************
+//
+// The following defines are used to define the length of the authentication
+// field for CCM operations through the ui32Config argument in the AESConfig
+// function.  This value is also known as M.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CCM_M_4         0x00400000
+#define AES_CFG_CCM_M_6         0x00800000
+#define AES_CFG_CCM_M_8         0x00c00000
+#define AES_CFG_CCM_M_10        0x01000000
+#define AES_CFG_CCM_M_12        0x01400000
+#define AES_CFG_CCM_M_14        0x01800000
+#define AES_CFG_CCM_M_16        0x01c00000
+
+//*****************************************************************************
+//
+// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
+// AESIntStatus functions.
+//
+//*****************************************************************************
+#define AES_INT_CONTEXT_IN      0x00000001
+#define AES_INT_CONTEXT_OUT     0x00000008
+#define AES_INT_DATA_IN         0x00000002
+#define AES_INT_DATA_OUT        0x00000004
+#define AES_INT_DMA_CONTEXT_IN  0x00010000
+#define AES_INT_DMA_CONTEXT_OUT 0x00080000
+#define AES_INT_DMA_DATA_IN     0x00020000
+#define AES_INT_DMA_DATA_OUT    0x00040000
+
+//*****************************************************************************
+//
+// Defines used when enabling and disabling DMA requests in the
+// AESEnableDMA and AESDisableDMA functions.
+//
+//*****************************************************************************
+#define AES_DMA_DATA_IN         0x00000020
+#define AES_DMA_DATA_OUT        0x00000040
+#define AES_DMA_CONTEXT_IN      0x00000080
+#define AES_DMA_CONTEXT_OUT     0x00000100
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
+extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
+extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
+                           uint32_t *pui32Dest, uint32_t ui32Length);
+extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src,
+                        uint32_t ui32Length, uint32_t *pui32Tag);
+extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src,
+                               uint32_t *pui32Dest, uint32_t ui32Length,
+                               uint32_t *pui32AuthSrc,
+                               uint32_t ui32AuthLength, uint32_t *pui32Tag);
+extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
+extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
+extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void AESIntUnregister(uint32_t ui32Base);
+extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
+extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata);
+extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key,
+                       uint32_t ui32Keysize);
+extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key,
+                       uint32_t ui32Keysize);
+extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key);
+extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length);
+extern void AESReset(uint32_t ui32Base);
+extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_AES_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/can.c b/bsp/tm4c129x/libraries/driverlib/can.c
new file mode 100644
index 0000000000..173c216402
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/can.c
@@ -0,0 +1,2117 @@
+//*****************************************************************************
+//
+// can.c - Driver for the CAN module.
+//
+// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_can.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/can.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// This is the maximum number that can be stored as an 11bit Message
+// identifier.
+//
+//*****************************************************************************
+#define CAN_MAX_11BIT_MSG_ID    0x7ff
+
+//*****************************************************************************
+//
+// The maximum CAN bit timing divisor is 19.
+//
+//*****************************************************************************
+#define CAN_MAX_BIT_DIVISOR     19
+
+//*****************************************************************************
+//
+// The minimum CAN bit timing divisor is 4.
+//
+//*****************************************************************************
+#define CAN_MIN_BIT_DIVISOR     4
+
+//*****************************************************************************
+//
+// The maximum CAN pre-divisor is 1024.
+//
+//*****************************************************************************
+#define CAN_MAX_PRE_DIVISOR     1024
+
+//*****************************************************************************
+//
+// The minimum CAN pre-divisor is 1.
+//
+//*****************************************************************************
+#define CAN_MIN_PRE_DIVISOR     1
+
+//*****************************************************************************
+//
+// Converts a set of CAN bit timing values into the value that needs to be
+// programmed into the CAN_BIT register to achieve those timings.
+//
+//*****************************************************************************
+#define CAN_BIT_VALUE(seg1, seg2, sjw)                                        \
+                                ((((seg1 - 1) << CAN_BIT_TSEG1_S) &           \
+                                  CAN_BIT_TSEG1_M) |                          \
+                                 (((seg2 - 1) << CAN_BIT_TSEG2_S) &           \
+                                  CAN_BIT_TSEG2_M) |                          \
+                                 (((sjw - 1) << CAN_BIT_SJW_S) &              \
+                                  CAN_BIT_SJW_M))
+
+//*****************************************************************************
+//
+// This table is used by the CANBitRateSet() API as the register defaults for
+// the bit timing values.
+//
+//*****************************************************************************
+static const uint16_t g_ui16CANBitValues[] =
+{
+    CAN_BIT_VALUE(2, 1, 1),     // 4 clocks/bit
+    CAN_BIT_VALUE(3, 1, 1),     // 5 clocks/bit
+    CAN_BIT_VALUE(3, 2, 2),     // 6 clocks/bit
+    CAN_BIT_VALUE(4, 2, 2),     // 7 clocks/bit
+    CAN_BIT_VALUE(4, 3, 3),     // 8 clocks/bit
+    CAN_BIT_VALUE(5, 3, 3),     // 9 clocks/bit
+    CAN_BIT_VALUE(5, 4, 4),     // 10 clocks/bit
+    CAN_BIT_VALUE(6, 4, 4),     // 11 clocks/bit
+    CAN_BIT_VALUE(6, 5, 4),     // 12 clocks/bit
+    CAN_BIT_VALUE(7, 5, 4),     // 13 clocks/bit
+    CAN_BIT_VALUE(7, 6, 4),     // 14 clocks/bit
+    CAN_BIT_VALUE(8, 6, 4),     // 15 clocks/bit
+    CAN_BIT_VALUE(8, 7, 4),     // 16 clocks/bit
+    CAN_BIT_VALUE(9, 7, 4),     // 17 clocks/bit
+    CAN_BIT_VALUE(9, 8, 4),     // 18 clocks/bit
+    CAN_BIT_VALUE(10, 8, 4)     // 19 clocks/bit
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a CAN base address.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//!
+//! This function determines if a CAN controller base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_CANBaseValid(uint32_t ui32Base)
+{
+    return((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Returns the CAN controller interrupt number.
+//!
+//! \param ui32Base is the base address of the selected CAN controller
+//!
+//! This function returns the interrupt number for the CAN module with the base
+//! address passed in the \e ui32Base parameter.
+//!
+//! \return Returns a CAN interrupt number or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint_fast8_t
+_CANIntNumberGet(uint32_t ui32Base)
+{
+    uint_fast8_t ui8Int;
+
+    ASSERT((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE));
+
+    ui8Int = 0;
+
+    //
+    // Find the valid interrupt number for this CAN controller.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        if(ui32Base == CAN0_BASE)
+        {
+            ui8Int = INT_CAN0_TM4C123;
+        }
+        else if(ui32Base == CAN1_BASE)
+        {
+            ui8Int = INT_CAN1_TM4C123;
+        }
+    }
+    else if(CLASS_IS_TM4C129)
+    {
+        if(ui32Base == CAN0_BASE)
+        {
+            ui8Int = INT_CAN0_TM4C129;
+        }
+        else if(ui32Base == CAN1_BASE)
+        {
+            ui8Int = INT_CAN1_TM4C129;
+        }
+    }
+
+    return(ui8Int);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//! Copies data from a buffer to the CAN Data registers.
+//!
+//! \param pui8Data is a pointer to the data to be written out to the CAN
+//! controller's data registers.
+//! \param pui32Register is an uint32_t pointer to the first register of the
+//! CAN controller's data registers.  For example, in order to use the IF1
+//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b +
+//! \b CAN_O_IF1DA1.
+//! \param iSize is the number of bytes to copy into the CAN controller.
+//!
+//! This function takes the steps necessary to copy data from a contiguous
+//! buffer in memory into the non-contiguous data registers used by the CAN
+//! controller.  This function is rarely used outside of the CANMessageSet()
+//! function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+_CANDataRegWrite(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size)
+{
+    uint32_t ui32Idx, ui32Value;
+
+    //
+    // Loop always copies 1 or 2 bytes per iteration.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Size; )
+    {
+        //
+        // Write out the data 16 bits at a time since this is how the registers
+        // are aligned in memory.
+        //
+        ui32Value = pui8Data[ui32Idx++];
+
+        //
+        // Only write the second byte if needed otherwise the value is zero.
+        //
+        if(ui32Idx < ui32Size)
+        {
+            ui32Value |= (pui8Data[ui32Idx++] << 8);
+        }
+
+        HWREG(pui32Register++) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+//! \internal
+//! Copies data from a buffer to the CAN Data registers.
+//!
+//! \param pui8Data is a pointer to the location to store the data read from
+//! the CAN controller's data registers.
+//! \param pui32Register is an uint32_t pointer to the first register of the
+//! CAN controller's data registers.  For example, in order to use the IF1
+//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b +
+//! \b CAN_O_IF1DA1.
+//! \param iSize is the number of bytes to copy from the CAN controller.
+//!
+//! This function takes the steps necessary to copy data to a contiguous buffer
+//! in memory from the non-contiguous data registers used by the CAN
+//! controller.  This function is rarely used outside of the CANMessageGet()
+//! function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+_CANDataRegRead(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size)
+{
+    uint32_t ui32Idx, ui32Value;
+
+    //
+    // Loop always copies 1 or 2 bytes per iteration.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Size; )
+    {
+        //
+        // Read out the data 16 bits at a time since this is how the registers
+        // are aligned in memory.
+        //
+        ui32Value = HWREG(pui32Register++);
+
+        //
+        // Store the first byte.
+        //
+        pui8Data[ui32Idx++] = (uint8_t)ui32Value;
+
+        //
+        // Only read the second byte if needed.
+        //
+        if(ui32Idx < ui32Size)
+        {
+            pui8Data[ui32Idx++] = (uint8_t)(ui32Value >> 8);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes the CAN controller after reset.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//!
+//! After reset, the CAN controller is left in the disabled state.  However,
+//! the memory used for message objects contains undefined values and must be
+//! cleared prior to enabling the CAN controller the first time.  This prevents
+//! unwanted transmission or reception of data before the message objects are
+//! configured.  This function must be called before enabling the controller
+//! the first time.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANInit(uint32_t ui32Base)
+{
+    uint32_t ui32Msg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Place CAN controller in init state, regardless of previous state.  This
+    // puts controller in idle, and allow the message object RAM to be
+    // programmed.
+    //
+    HWREG(ui32Base + CAN_O_CTL) = CAN_CTL_INIT;
+
+    //
+    // Wait for busy bit to clear
+    //
+    while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+    {
+    }
+
+    //
+    // Clear the message value bit in the arbitration register.  This indicates
+    // the message is not valid and is a "safe" condition to leave the message
+    // object.  The same arb reg is used to program all the message objects.
+    //
+    HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB |
+                                       CAN_IF1CMSK_CONTROL);
+    HWREG(ui32Base + CAN_O_IF1ARB2) = 0;
+    HWREG(ui32Base + CAN_O_IF1MCTL) = 0;
+
+    //
+    // Loop through to program all 32 message objects
+    //
+    for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++)
+    {
+        //
+        // Wait for busy bit to clear
+        //
+        while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+        {
+        }
+
+        //
+        // Initiate programming the message object
+        //
+        HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg;
+    }
+
+    //
+    // Make sure that the interrupt and new data flags are updated for the
+    // message objects.
+    //
+    HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_NEWDAT |
+                                       CAN_IF1CMSK_CLRINTPND);
+
+    //
+    // Loop through to program all 32 message objects
+    //
+    for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++)
+    {
+        //
+        // Wait for busy bit to clear.
+        //
+        while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+        {
+        }
+
+        //
+        // Initiate programming the message object
+        //
+        HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg;
+    }
+
+    //
+    // Acknowledge any pending status interrupts.
+    //
+    HWREG(ui32Base + CAN_O_STS);
+}
+
+//*****************************************************************************
+//
+//! Enables the CAN controller.
+//!
+//! \param ui32Base is the base address of the CAN controller to enable.
+//!
+//! Enables the CAN controller for message processing.  Once enabled, the
+//! controller automatically transmits any pending frames, and processes any
+//! received frames.  The controller can be stopped by calling CANDisable().
+//! Prior to calling CANEnable(), CANInit() must have been called to
+//! initialize the controller and the CAN bus clock must be configured by
+//! calling CANBitTimingSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Clear the init bit in the control register.
+    //
+    HWREG(ui32Base + CAN_O_CTL) &= ~CAN_CTL_INIT;
+}
+
+//*****************************************************************************
+//
+//! Disables the CAN controller.
+//!
+//! \param ui32Base is the base address of the CAN controller to disable.
+//!
+//! Disables the CAN controller for message processing.  When disabled, the
+//! controller no longer automatically processes data on the CAN bus.  The
+//! controller can be restarted by calling CANEnable().  The state of the CAN
+//! controller and the message objects in the controller are left as they were
+//! before this call was made.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Set the init bit in the control register.
+    //
+    HWREG(ui32Base + CAN_O_CTL) |= CAN_CTL_INIT;
+}
+
+//*****************************************************************************
+//
+//! Reads the current settings for the CAN controller bit timing.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param psClkParms is a pointer to a structure to hold the timing
+//! parameters.
+//!
+//! This function reads the current configuration of the CAN controller bit
+//! clock timing and stores the resulting information in the structure
+//! supplied by the caller.  Refer to CANBitTimingSet() for the meaning of the
+//! values that are returned in the structure pointed to by \e psClkParms.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms)
+{
+    uint32_t ui32BitReg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT(psClkParms);
+
+    //
+    // Read out all the bit timing values from the CAN controller registers.
+    //
+    ui32BitReg = HWREG(ui32Base + CAN_O_BIT);
+
+    //
+    // Set the phase 2 segment.
+    //
+    psClkParms->ui32Phase2Seg =
+        ((ui32BitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1;
+
+    //
+    // Set the phase 1 segment.
+    //
+    psClkParms->ui32SyncPropPhase1Seg =
+        ((ui32BitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1;
+
+    //
+    // Set the synchronous jump width.
+    //
+    psClkParms->ui32SJW = ((ui32BitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1;
+
+    //
+    // Set the pre-divider for the CAN bus bit clock.
+    //
+    psClkParms->ui32QuantumPrescaler =
+        ((ui32BitReg & CAN_BIT_BRP_M) |
+         ((HWREG(ui32Base + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1;
+}
+
+//*****************************************************************************
+//
+//! Sets the CAN bit timing values to a nominal setting based on a desired
+//! bit rate.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32SourceClock is the system clock for the device in Hz.
+//! \param ui32BitRate is the desired bit rate.
+//!
+//! This function sets the CAN bit timing for the bit rate passed in the
+//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter.
+//! Because the CAN clock is based off of the system clock, the calling
+//! function must pass in the source clock rate either by retrieving it from
+//! SysCtlClockGet() or using a specific value in Hz.  The CAN bit timing is
+//! calculated assuming a minimal amount of propagation delay, which works for
+//! most cases where the network length is short.  If tighter timing
+//! requirements or longer network lengths are needed, then the
+//! CANBitTimingSet() function is available for full customization of all of
+//! the CAN bit timing values.  Because not all bit rates can be matched
+//! exactly, the bit rate is set to the value closest to the desired bit rate
+//! without being higher than the \e ui32BitRate value.
+//!
+//! \note On some devices the source clock is fixed at 8MHz so the
+//! \e ui32SourceClock must be set to 8000000.
+//!
+//! \return This function returns the bit rate that the CAN controller was
+//! configured to use or it returns 0 to indicate that the bit rate was not
+//! changed because the requested bit rate was not valid.
+//!
+//*****************************************************************************
+uint32_t
+CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
+              uint32_t ui32BitRate)
+{
+    uint32_t ui32DesiredRatio;
+    uint32_t ui32CANBits;
+    uint32_t ui32PreDivide;
+    uint32_t ui32RegValue;
+    uint16_t ui16CANCTL;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT(ui32SourceClock);
+    ASSERT(ui32BitRate);
+
+    //
+    // Calculate the desired clock rate.
+    //
+    ui32DesiredRatio = ui32SourceClock / ui32BitRate;
+
+    //
+    // Make sure that the ratio of CAN bit rate to processor clock is not too
+    // small or too large.
+    //
+    ASSERT(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR));
+    ASSERT(ui32DesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR));
+
+    //
+    // Make sure that the Desired Ratio is not too large.  This enforces the
+    // requirement that the bit rate is larger than requested.
+    //
+    if((ui32SourceClock / ui32DesiredRatio) > ui32BitRate)
+    {
+        ui32DesiredRatio += 1;
+    }
+
+    //
+    // Check all possible values to find a matching value.
+    //
+    while(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR))
+    {
+        //
+        // Loop through all possible CAN bit divisors.
+        //
+        for(ui32CANBits = CAN_MAX_BIT_DIVISOR;
+            ui32CANBits >= CAN_MIN_BIT_DIVISOR; ui32CANBits--)
+        {
+            //
+            // For a given CAN bit divisor save the pre divisor.
+            //
+            ui32PreDivide = ui32DesiredRatio / ui32CANBits;
+
+            //
+            // If the calculated divisors match the desired clock ratio then
+            // return these bit rate and set the CAN bit timing.
+            //
+            if((ui32PreDivide * ui32CANBits) == ui32DesiredRatio)
+            {
+                //
+                // Start building the bit timing value by adding the bit timing
+                // in time quanta.
+                //
+                ui32RegValue = g_ui16CANBitValues[ui32CANBits -
+                                                  CAN_MIN_BIT_DIVISOR];
+
+                //
+                // To set the bit timing register, the controller must be
+                // placed in init mode (if not already), and also configuration
+                // change bit enabled.  The state of the register must be
+                // saved so it can be restored.
+                //
+                ui16CANCTL = HWREG(ui32Base + CAN_O_CTL);
+                HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT |
+                                              CAN_CTL_CCE;
+
+                //
+                // Now add in the pre-scalar on the bit rate.
+                //
+                ui32RegValue |= ((ui32PreDivide - 1) & CAN_BIT_BRP_M);
+
+                //
+                // Set the clock bits in the and the lower bits of the
+                // pre-scalar.
+                //
+                HWREG(ui32Base + CAN_O_BIT) = ui32RegValue;
+
+                //
+                // Set the divider upper bits in the extension register.
+                //
+                HWREG(ui32Base + CAN_O_BRPE) = ((ui32PreDivide - 1) >> 6) &
+                                               CAN_BRPE_BRPE_M;
+
+                //
+                // Restore the saved CAN Control register.
+                //
+                HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL;
+
+                //
+                // Return the computed bit rate.
+                //
+                return(ui32SourceClock / (ui32PreDivide * ui32CANBits));
+            }
+        }
+
+        //
+        // Move the divisor up one and look again.  Only in rare cases are
+        // more than 2 loops required to find the value.
+        //
+        ui32DesiredRatio++;
+    }
+
+    //
+    // A valid combination could not be found, so return 0 to indicate that the
+    // bit rate was not changed.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Configures the CAN controller bit timing.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param psClkParms points to the structure with the clock parameters.
+//!
+//! Configures the various timing parameters for the CAN bus bit timing:
+//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
+//! the Synchronization Jump Width.  The values for Propagation and Phase
+//! Buffer 1 segments are derived from the combination
+//! \e psClkParms->ui32SyncPropPhase1Seg parameter.  Phase Buffer 2 is
+//! determined from the \e psClkParms->ui32Phase2Seg parameter.  These two
+//! parameters, along with \e psClkParms->ui32SJW are based in units of bit
+//! time quanta.  The actual quantum time is determined by the
+//! \e psClkParms->ui32QuantumPrescaler value, which specifies the divisor for
+//! the CAN module clock.
+//!
+//! The total bit time, in quanta, is the sum of the two Seg parameters,
+//! as follows:
+//!
+//! bit_time_q = ui32SyncPropPhase1Seg + ui32Phase2Seg + 1
+//!
+//! Note that the Sync_Seg is always one quantum in duration, and is added
+//! to derive the correct duration of Prop_Seg and Phase1_Seg.
+//!
+//! The equation to determine the actual bit rate is as follows:
+//!
+//! CAN Clock /
+//! ((\e ui32SyncPropPhase1Seg + \e ui32Phase2Seg + 1) *
+//! (\e ui32QuantumPrescaler))
+//!
+//! Thus with \e ui32SyncPropPhase1Seg = 4, \e ui32Phase2Seg = 1,
+//! \e ui32QuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is
+//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms)
+{
+    uint32_t ui32BitReg, ui32SavedInit;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT(psClkParms);
+
+    //
+    // The phase 1 segment must be in the range from 2 to 16.
+    //
+    ASSERT((psClkParms->ui32SyncPropPhase1Seg >= 2) &&
+           (psClkParms->ui32SyncPropPhase1Seg <= 16));
+
+    //
+    // The phase 2 segment must be in the range from 1 to 8.
+    //
+    ASSERT((psClkParms->ui32Phase2Seg >= 1) &&
+           (psClkParms->ui32Phase2Seg <= 8));
+
+    //
+    // The synchronous jump windows must be in the range from 1 to 4.
+    //
+    ASSERT((psClkParms->ui32SJW >= 1) && (psClkParms->ui32SJW <= 4));
+
+    //
+    // The CAN clock pre-divider must be in the range from 1 to 1024.
+    //
+    ASSERT((psClkParms->ui32QuantumPrescaler <= 1024) &&
+           (psClkParms->ui32QuantumPrescaler >= 1));
+
+    //
+    // To set the bit timing register, the controller must be placed in init
+    // mode (if not already), and also configuration change bit enabled.  State
+    // of the init bit must be saved so it can be restored at the end.
+    //
+    ui32SavedInit = HWREG(ui32Base + CAN_O_CTL);
+    HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit | CAN_CTL_INIT | CAN_CTL_CCE;
+
+    //
+    // Set the bit fields of the bit timing register according to the parms.
+    //
+    ui32BitReg = (((psClkParms->ui32Phase2Seg - 1) << CAN_BIT_TSEG2_S) &
+                  CAN_BIT_TSEG2_M);
+    ui32BitReg |= (((psClkParms->ui32SyncPropPhase1Seg - 1) <<
+                    CAN_BIT_TSEG1_S) & CAN_BIT_TSEG1_M);
+    ui32BitReg |= ((psClkParms->ui32SJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M;
+    ui32BitReg |= (psClkParms->ui32QuantumPrescaler - 1) & CAN_BIT_BRP_M;
+    HWREG(ui32Base + CAN_O_BIT) = ui32BitReg;
+
+    //
+    // Set the divider upper bits in the extension register.
+    //
+    HWREG(ui32Base + CAN_O_BRPE) =
+        ((psClkParms->ui32QuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M;
+
+    //
+    // Clear the config change bit, and restore the init bit.
+    //
+    ui32SavedInit &= ~CAN_CTL_CCE;
+
+    //
+    // If Init was not set before, then clear it.
+    //
+    if(ui32SavedInit & CAN_CTL_INIT)
+    {
+        ui32SavedInit &= ~CAN_CTL_INIT;
+    }
+
+    HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the CAN controller.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled CAN interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables CAN interrupts on the interrupt controller; specific CAN
+//! interrupt sources must be enabled using CANIntEnable().  The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! CANIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() is used to enable CAN interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint_fast8_t ui8IntNumber;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Get the actual interrupt number for this CAN controller.
+    //
+    ui8IntNumber = _CANIntNumberGet(ui32Base);
+    ASSERT(ui8IntNumber != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui8IntNumber, pfnHandler);
+
+    //
+    // Enable the Ethernet interrupt.
+    //
+    IntEnable(ui8IntNumber);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the CAN controller.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntUnregister(uint32_t ui32Base)
+{
+    uint_fast8_t ui8IntNumber;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Get the actual interrupt number for this CAN controller.
+    //
+    ui8IntNumber = _CANIntNumberGet(ui32Base);
+    ASSERT(ui8IntNumber != 0);
+
+    //
+    // Disable the CAN interrupt.
+    //
+    IntDisable(ui8IntNumber);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntUnregister(ui8IntNumber);
+}
+
+//*****************************************************************************
+//
+//! Enables individual CAN controller interrupt sources.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables specific interrupt sources of the CAN controller.
+//! Only enabled sources cause a processor interrupt.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b CAN_INT_ERROR - a controller error condition has occurred
+//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has
+//!   been detected
+//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts
+//!
+//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled.
+//! Further, for any particular transaction from a message object to generate
+//! an interrupt, that message object must have interrupts enabled (see
+//! CANMessageSet()).  \b CAN_INT_ERROR generates an interrupt if the
+//! controller enters the ``bus off'' condition, or if the error counters reach
+//! a limit.  \b CAN_INT_STATUS generates an interrupt under quite a few
+//! status conditions and may provide more interrupts than the application
+//! needs to handle.  When an interrupt occurs, use CANIntStatus() to determine
+//! the cause.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);
+
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(ui32Base + CAN_O_CTL) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual CAN controller interrupt sources.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! Disables the specified CAN controller interrupt sources.  Only enabled
+//! interrupt sources can cause a processor interrupt.
+//!
+//! The \e ui32IntFlags parameter has the same definition as in the
+//! CANIntEnable() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);
+
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(ui32Base + CAN_O_CTL) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Returns the current CAN controller interrupt status.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param eIntStsReg indicates which interrupt status register to read
+//!
+//! This function returns the value of one of two interrupt status registers.
+//! The interrupt status register read is determined by the \e eIntStsReg
+//! parameter, which can have one of the following values:
+//!
+//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt
+//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message
+//! objects
+//!
+//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register
+//! and indicates the cause of the interrupt.  The value returned is
+//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt.  In this case,
+//! the status register is read with the CANStatusGet() function.
+//! Calling this function to read the status also clears the status
+//! interrupt.  If the value of the interrupt register is in the range 1-32,
+//! then this indicates the number of the highest priority message object that
+//! has an interrupt pending.  The message object interrupt can be cleared by
+//! using the CANIntClear() function, or by reading the message using
+//! CANMessageGet() in the case of a received message.  The interrupt handler
+//! can read the interrupt status again to make sure all pending interrupts are
+//! cleared before returning from the interrupt.
+//!
+//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
+//! have pending interrupts.  This value can be used to discover all of the
+//! pending interrupts at once, as opposed to repeatedly reading the interrupt
+//! register by using \b CAN_INT_STS_CAUSE.
+//!
+//! \return Returns the value of one of the interrupt status registers.
+//
+//*****************************************************************************
+uint32_t
+CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg)
+{
+    uint32_t ui32Status;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // See which status the caller is looking for.
+    //
+    switch(eIntStsReg)
+    {
+        //
+        // The caller wants the global interrupt status for the CAN controller
+        // specified by ui32Base.
+        //
+        case CAN_INT_STS_CAUSE:
+        {
+            ui32Status = HWREG(ui32Base + CAN_O_INT);
+            break;
+        }
+
+        //
+        // The caller wants the current message status interrupt for all
+        // messages.
+        //
+        case CAN_INT_STS_OBJECT:
+        {
+            //
+            // Read and combine both 16 bit values into one 32bit status.
+            //
+            ui32Status = (HWREG(ui32Base + CAN_O_MSG1INT) &
+                          CAN_MSG1INT_INTPND_M);
+            ui32Status |= (HWREG(ui32Base + CAN_O_MSG2INT) << 16);
+            break;
+        }
+
+        //
+        // Request was for unknown status so just return 0.
+        //
+        default:
+        {
+            ui32Status = 0;
+            break;
+        }
+    }
+
+    //
+    // Return the interrupt status value
+    //
+    return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Clears a CAN interrupt source.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32IntClr is a value indicating which interrupt source to clear.
+//!
+//! This function can be used to clear a specific interrupt source.  The
+//! \e ui32IntClr parameter must be one of the following values:
+//!
+//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt.
+//! - 1-32 - Clears the specified message object interrupt
+//!
+//! It is not necessary to use this function to clear an interrupt.  This
+//! function is only used if the application wants to clear an interrupt
+//! source without taking the normal interrupt action.
+//!
+//! Normally, the status interrupt is cleared by reading the controller status
+//! using CANStatusGet().  A specific message object interrupt is normally
+//! cleared by reading the message object using CANMessageGet().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT((ui32IntClr == CAN_INT_INTID_STATUS) ||
+           ((ui32IntClr >= 1) && (ui32IntClr <= 32)));
+
+    if(ui32IntClr == CAN_INT_INTID_STATUS)
+    {
+        //
+        // Simply read and discard the status to clear the interrupt.
+        //
+        HWREG(ui32Base + CAN_O_STS);
+    }
+    else
+    {
+        //
+        // Wait to be sure that this interface is not busy.
+        //
+        while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+        {
+        }
+
+        //
+        // Only change the interrupt pending state by setting only the
+        // CAN_IF1CMSK_CLRINTPND bit.
+        //
+        HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_CLRINTPND;
+
+        //
+        // Send the clear pending interrupt command to the CAN controller.
+        //
+        HWREG(ui32Base + CAN_O_IF1CRQ) = ui32IntClr & CAN_IF1CRQ_MNUM_M;
+
+        //
+        // Wait to be sure that this interface is not busy.
+        //
+        while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+        {
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the CAN controller automatic retransmission behavior.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param bAutoRetry enables automatic retransmission.
+//!
+//! This function enables or disables automatic retransmission of messages with
+//! detected errors.  If \e bAutoRetry is \b true, then automatic
+//! retransmission is enabled, otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANRetrySet(uint32_t ui32Base, bool bAutoRetry)
+{
+    uint32_t ui32CtlReg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    ui32CtlReg = HWREG(ui32Base + CAN_O_CTL);
+
+    //
+    // Conditionally set the DAR bit to enable/disable auto-retry.
+    //
+    if(bAutoRetry)
+    {
+        //
+        // Clearing the DAR bit tells the controller to not disable the
+        // auto-retry of messages which were not transmitted or received
+        // correctly.
+        //
+        ui32CtlReg &= ~CAN_CTL_DAR;
+    }
+    else
+    {
+        //
+        // Setting the DAR bit tells the controller to disable the auto-retry
+        // of messages which were not transmitted or received correctly.
+        //
+        ui32CtlReg |= CAN_CTL_DAR;
+    }
+
+    HWREG(ui32Base + CAN_O_CTL) = ui32CtlReg;
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting for automatic retransmission.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//!
+//! This function reads the current setting for automatic retransmission in the
+//! CAN controller and returns it to the caller.
+//!
+//! \return Returns \b true if automatic retransmission is enabled, \b false
+//! otherwise.
+//
+//*****************************************************************************
+bool
+CANRetryGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Read the disable automatic retry setting from the CAN controller.
+    //
+    if(HWREG(ui32Base + CAN_O_CTL) & CAN_CTL_DAR)
+    {
+        //
+        // Automatic data retransmission is not enabled.
+        //
+        return(false);
+    }
+
+    //
+    // Automatic data retransmission is enabled.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads one of the controller status registers.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param eStatusReg is the status register to read.
+//!
+//! This function reads a status register of the CAN controller and returns it
+//! to the caller.
+//! The different status registers are:
+//!
+//! - \b CAN_STS_CONTROL - the main controller status
+//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission
+//! - \b CAN_STS_NEWDAT - bit mask of objects with new data
+//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration
+//!
+//! When reading the main controller status register, a pending status
+//! interrupt is cleared.  This parameter is used in the interrupt
+//! handler for the CAN controller if the cause is a status interrupt.  The
+//! controller status register fields are as follows:
+//!
+//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition
+//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96
+//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state
+//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of
+//!   any message filtering).
+//! - \b CAN_STATUS_TXOK - a message was successfully transmitted
+//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits)
+//! - \b CAN_STATUS_LEC_NONE - no error
+//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected
+//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part
+//!   of a message
+//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged
+//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in
+//!   recessive mode
+//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in
+//!   dominant mode
+//! - \b CAN_STATUS_LEC_CRC - CRC error in received message
+//!
+//! The remaining status registers consist of 32-bit-wide bit maps to the
+//! message objects.  They can be used to quickly obtain information about the
+//! status of all the message objects without needing to query each one.  They
+//! contain the following information:
+//!
+//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a
+//!   transmission is pending on that object.  The application can use this
+//!   information to determine which objects are still waiting to send a
+//!   message.
+//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new
+//!   message has been received in that object, and has not yet been picked up
+//!   by the host application
+//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object
+//!   has a valid configuration programmed.  The host application can use this
+//!   information to determine which message objects are empty/unused.
+//!
+//! \return Returns the value of the status register.
+//
+//*****************************************************************************
+uint32_t
+CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg)
+{
+    uint32_t ui32Status;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    switch(eStatusReg)
+    {
+        //
+        // Just return the global CAN status register since that is what was
+        // requested.
+        //
+        case CAN_STS_CONTROL:
+        {
+            ui32Status = HWREG(ui32Base + CAN_O_STS);
+            HWREG(ui32Base + CAN_O_STS) = ~(CAN_STS_RXOK | CAN_STS_TXOK |
+                                            CAN_STS_LEC_M);
+            break;
+        }
+
+        //
+        // Combine the Transmit status bits into one 32bit value.
+        //
+        case CAN_STS_TXREQUEST:
+        {
+            ui32Status = HWREG(ui32Base + CAN_O_TXRQ1);
+            ui32Status |= HWREG(ui32Base + CAN_O_TXRQ2) << 16;
+            break;
+        }
+
+        //
+        // Combine the New Data status bits into one 32bit value.
+        //
+        case CAN_STS_NEWDAT:
+        {
+            ui32Status = HWREG(ui32Base + CAN_O_NWDA1);
+            ui32Status |= HWREG(ui32Base + CAN_O_NWDA2) << 16;
+            break;
+        }
+
+        //
+        // Combine the Message valid status bits into one 32bit value.
+        //
+        case CAN_STS_MSGVAL:
+        {
+            ui32Status = HWREG(ui32Base + CAN_O_MSG1VAL);
+            ui32Status |= HWREG(ui32Base + CAN_O_MSG2VAL) << 16;
+            break;
+        }
+
+        //
+        // Unknown CAN status requested so return 0.
+        //
+        default:
+        {
+            ui32Status = 0;
+            break;
+        }
+    }
+    return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Reads the CAN controller error counter register.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param pui32RxCount is a pointer to storage for the receive error counter.
+//! \param pui32TxCount is a pointer to storage for the transmit error counter.
+//!
+//! This function reads the error counter register and returns the transmit and
+//! receive error counts to the caller along with a flag indicating if the
+//! controller receive counter has reached the error passive limit.  The values
+//! of the receive and transmit error counters are returned through the
+//! pointers provided as parameters.
+//!
+//! After this call, \e *pui32RxCount holds the current receive error count
+//! and \e *pui32TxCount holds the current transmit error count.
+//!
+//! \return Returns \b true if the receive error count has reached the error
+//! passive limit, and \b false if the error count is below the error passive
+//! limit.
+//
+//*****************************************************************************
+bool
+CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
+              uint32_t *pui32TxCount)
+{
+    uint32_t ui32CANError;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+
+    //
+    // Read the current count of transmit/receive errors.
+    //
+    ui32CANError = HWREG(ui32Base + CAN_O_ERR);
+
+    //
+    // Extract the error numbers from the register value.
+    //
+    *pui32RxCount = (ui32CANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S;
+    *pui32TxCount = (ui32CANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S;
+
+    if(ui32CANError & CAN_ERR_RP)
+    {
+        return(true);
+    }
+    return(false);
+}
+
+//*****************************************************************************
+//
+//! Configures a message object in the CAN controller.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32ObjID is the object number to configure (1-32).
+//! \param psMsgObject is a pointer to a structure containing message object
+//! settings.
+//! \param eMsgType indicates the type of message for this object.
+//!
+//! This function is used to configure any one of the 32 message objects in the
+//! CAN controller.  A message object can be configured to be any type of CAN
+//! message object as well as to use automatic transmission and reception.
+//! This call also allows the message object to be configured to generate
+//! interrupts on completion of message receipt or transmission.  The
+//! message object can also be configured with a filter/mask so that actions
+//! are only taken when a message that meets certain parameters is seen on the
+//! CAN bus.
+//!
+//! The \e eMsgType parameter must be one of the following values:
+//!
+//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object.
+//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object.
+//! - \b MSG_OBJ_TYPE_RX - CAN receive message object.
+//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object.
+//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then
+//!   transmit message object.
+//!
+//! The message object pointed to by \e psMsgObject must be populated by the
+//! caller, as follows:
+//!
+//! - \e ui32MsgID - contains the message ID, either 11 or 29 bits.
+//! - \e ui32MsgIDMask - mask of bits from \e ui32MsgID that must match if
+//!   identifier filtering is enabled.
+//! - \e ui32Flags
+//!   - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission.
+//!   - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt.
+//!   - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the
+//!     identifier mask specified by \e ui32MsgIDMask.
+//! - \e ui32MsgLen - the number of bytes in the message data.  This parameter
+//!   must be non-zero even for a remote frame; it must match the expected
+//!   bytes of data in the responding data frame.
+//! - \e pui8MsgData - points to a buffer containing up to 8 bytes of data for
+//!   a data frame.
+//!
+//! \b Example: To send a data frame or remote frame (in response to a remote
+//! request), take the following steps:
+//!
+//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX.
+//! -# Set \e psMsgObject->ui32MsgID to the message ID.
+//! -# Set \e psMsgObject->ui32Flags.  Make sure to set
+//!    \b MSG_OBJ_TX_INT_ENABLE to allow an interrupt to be generated when the
+//!    message is sent.
+//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the data frame.
+//! -# Set \e psMsgObject->pui8MsgData to point to an array containing the
+//!    bytes to send in the message.
+//! -# Call this function with \e ui32ObjID set to one of the 32 object
+//!    buffers.
+//!
+//! \b Example: To receive a specific data frame, take the following steps:
+//!
+//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX.
+//! -# Set \e psMsgObject->ui32MsgID to the full message ID, or a partial mask
+//!    to use partial ID matching.
+//! -# Set \e psMsgObject->ui32MsgIDMask bits that are used for masking
+//!    during comparison.
+//! -# Set \e psMsgObject->ui32Flags as follows:
+//!    - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data
+//!      frame is received.
+//!    - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based
+//!      filtering.
+//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the expected
+//!    data frame.
+//! -# The buffer pointed to by \e psMsgObject->pui8MsgData is not used by this
+//!    call as no data is present at the time of the call.
+//! -# Call this function with \e ui32ObjID set to one of the 32 object
+//!    buffers.
+//!
+//! If you specify a message object buffer that already contains a message
+//! definition, it is overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
+              tCANMsgObject *psMsgObject, tMsgObjType eMsgType)
+{
+    uint16_t ui16CmdMaskReg;
+    uint16_t ui16MaskReg0, ui16MaskReg1;
+    uint16_t ui16ArbReg0, ui16ArbReg1;
+    uint16_t ui16MsgCtrl;
+    bool bTransferData;
+    bool bUseExtendedID;
+
+    bTransferData = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0));
+    ASSERT((eMsgType == MSG_OBJ_TYPE_TX) ||
+           (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
+           (eMsgType == MSG_OBJ_TYPE_RX) ||
+           (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) ||
+           (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
+           (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE));
+
+    //
+    // Wait for busy bit to clear
+    //
+    while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+    {
+    }
+
+    //
+    // See if we need to use an extended identifier or not.
+    //
+    if((psMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) ||
+       (psMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID))
+    {
+        bUseExtendedID = 1;
+    }
+    else
+    {
+        bUseExtendedID = 0;
+    }
+
+    //
+    // This is always a write to the Message object as this call is setting a
+    // message object.  This call always sets all size bits so it sets
+    // both data bits.  The call uses the CONTROL register to set control
+    // bits so this bit needs to be set as well.
+    //
+    ui16CmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA |
+                      CAN_IF1CMSK_DATAB | CAN_IF1CMSK_CONTROL);
+
+    //
+    // Initialize the values to a known state before filling them in based on
+    // the type of message object that is being configured.
+    //
+    ui16ArbReg0 = 0;
+    ui16ArbReg1 = 0;
+    ui16MsgCtrl = 0;
+    ui16MaskReg0 = 0;
+    ui16MaskReg1 = 0;
+
+    switch(eMsgType)
+    {
+        //
+        // Transmit message object.
+        //
+        case MSG_OBJ_TYPE_TX:
+        {
+            //
+            // Set the TXRQST bit and the reset the rest of the register.
+            //
+            ui16MsgCtrl |= CAN_IF1MCTL_TXRQST;
+            ui16ArbReg1 = CAN_IF1ARB2_DIR;
+            bTransferData = 1;
+            break;
+        }
+
+        //
+        // Transmit remote request message object
+        //
+        case MSG_OBJ_TYPE_TX_REMOTE:
+        {
+            //
+            // Set the TXRQST bit and the reset the rest of the register.
+            //
+            ui16MsgCtrl |= CAN_IF1MCTL_TXRQST;
+            ui16ArbReg1 = 0;
+            break;
+        }
+
+        //
+        // Receive message object.
+        //
+        case MSG_OBJ_TYPE_RX:
+        {
+            //
+            // This clears the DIR bit along with everything else.  The TXRQST
+            // bit was cleared by defaulting ui16MsgCtrl to 0.
+            //
+            ui16ArbReg1 = 0;
+            break;
+        }
+
+        //
+        // Receive remote request message object.
+        //
+        case MSG_OBJ_TYPE_RX_REMOTE:
+        {
+            //
+            // The DIR bit is set to one for remote receivers.  The TXRQST bit
+            // was cleared by defaulting ui16MsgCtrl to 0.
+            //
+            ui16ArbReg1 = CAN_IF1ARB2_DIR;
+
+            //
+            // Set this object so that it only indicates that a remote frame
+            // was received and allow for software to handle it by sending back
+            // a data frame.
+            //
+            ui16MsgCtrl = CAN_IF1MCTL_UMASK;
+
+            //
+            // Use the full Identifier by default.
+            //
+            ui16MaskReg0 = 0xffff;
+            ui16MaskReg1 = 0x1fff;
+
+            //
+            // Make sure to send the mask to the message object.
+            //
+            ui16CmdMaskReg |= CAN_IF1CMSK_MASK;
+            break;
+        }
+
+        //
+        // Remote frame receive remote, with auto-transmit message object.
+        //
+        case MSG_OBJ_TYPE_RXTX_REMOTE:
+        {
+            //
+            // Oddly the DIR bit is set to one for remote receivers.
+            //
+            ui16ArbReg1 = CAN_IF1ARB2_DIR;
+
+            //
+            // Set this object to auto answer if a matching identifier is seen.
+            //
+            ui16MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK;
+
+            //
+            // The data to be returned needs to be filled in.
+            //
+            bTransferData = 1;
+            break;
+        }
+
+        //
+        // This case never happens due to the ASSERT statement at the
+        // beginning of this function.
+        //
+        default:
+        {
+            return;
+        }
+    }
+
+    //
+    // Configure the Mask Registers.
+    //
+    if(psMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER)
+    {
+        if(bUseExtendedID)
+        {
+            //
+            // Set the 29 bits of Identifier mask that were requested.
+            //
+            ui16MaskReg0 = psMsgObject->ui32MsgIDMask & CAN_IF1MSK1_IDMSK_M;
+            ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask >> 16) &
+                            CAN_IF1MSK2_IDMSK_M);
+        }
+        else
+        {
+            //
+            // Lower 16 bit are unused so set them to zero.
+            //
+            ui16MaskReg0 = 0;
+
+            //
+            // Put the 11 bit Mask Identifier into the upper bits of the field
+            // in the register.
+            //
+            ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask << 2) &
+                            CAN_IF1MSK2_IDMSK_M);
+        }
+    }
+
+    //
+    // If the caller wants to filter on the extended ID bit then set it.
+    //
+    if((psMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) ==
+       MSG_OBJ_USE_EXT_FILTER)
+    {
+        ui16MaskReg1 |= CAN_IF1MSK2_MXTD;
+    }
+
+    //
+    // The caller wants to filter on the message direction field.
+    //
+    if((psMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) ==
+       MSG_OBJ_USE_DIR_FILTER)
+    {
+        ui16MaskReg1 |= CAN_IF1MSK2_MDIR;
+    }
+
+    if(psMsgObject->ui32Flags &
+       (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER |
+        MSG_OBJ_USE_EXT_FILTER))
+    {
+        //
+        // Set the UMASK bit to enable using the mask register.
+        //
+        ui16MsgCtrl |= CAN_IF1MCTL_UMASK;
+
+        //
+        // Set the MASK bit so that this gets transferred to the Message
+        // Object.
+        //
+        ui16CmdMaskReg |= CAN_IF1CMSK_MASK;
+    }
+
+    //
+    // Set the Arb bit so that this gets transferred to the Message object.
+    //
+    ui16CmdMaskReg |= CAN_IF1CMSK_ARB;
+
+    //
+    // Configure the Arbitration registers.
+    //
+    if(bUseExtendedID)
+    {
+        //
+        // Set the 29 bit version of the Identifier for this message object.
+        //
+        ui16ArbReg0 |= psMsgObject->ui32MsgID & CAN_IF1ARB1_ID_M;
+        ui16ArbReg1 |= (psMsgObject->ui32MsgID >> 16) & CAN_IF1ARB2_ID_M;
+
+        //
+        // Mark the message as valid and set the extended ID bit.
+        //
+        ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
+    }
+    else
+    {
+        //
+        // Set the 11 bit version of the Identifier for this message object.
+        // The lower 18 bits are set to zero.
+        //
+        ui16ArbReg1 |= (psMsgObject->ui32MsgID << 2) & CAN_IF1ARB2_ID_M;
+
+        //
+        // Mark the message as valid.
+        //
+        ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL;
+    }
+
+    //
+    // Set the data length since this is set for all transfers.  This is also a
+    // single transfer and not a FIFO transfer so set EOB bit.
+    //
+    ui16MsgCtrl |= (psMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M);
+
+    //
+    // Mark this as the last entry if this is not the last entry in a FIFO.
+    //
+    if((psMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0)
+    {
+        ui16MsgCtrl |= CAN_IF1MCTL_EOB;
+    }
+
+    //
+    // Enable transmit interrupts if they should be enabled.
+    //
+    if(psMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE)
+    {
+        ui16MsgCtrl |= CAN_IF1MCTL_TXIE;
+    }
+
+    //
+    // Enable receive interrupts if they should be enabled.
+    //
+    if(psMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE)
+    {
+        ui16MsgCtrl |= CAN_IF1MCTL_RXIE;
+    }
+
+    //
+    // Write the data out to the CAN Data registers if needed.
+    //
+    if(bTransferData)
+    {
+        _CANDataRegWrite(psMsgObject->pui8MsgData,
+                         (uint32_t *)(ui32Base + CAN_O_IF1DA1),
+                         psMsgObject->ui32MsgLen);
+    }
+
+    //
+    // Write out the registers to program the message object.
+    //
+    HWREG(ui32Base + CAN_O_IF1CMSK) = ui16CmdMaskReg;
+    HWREG(ui32Base + CAN_O_IF1MSK1) = ui16MaskReg0;
+    HWREG(ui32Base + CAN_O_IF1MSK2) = ui16MaskReg1;
+    HWREG(ui32Base + CAN_O_IF1ARB1) = ui16ArbReg0;
+    HWREG(ui32Base + CAN_O_IF1ARB2) = ui16ArbReg1;
+    HWREG(ui32Base + CAN_O_IF1MCTL) = ui16MsgCtrl;
+
+    //
+    // Transfer the message object to the message object specified by
+    // ui32ObjID.
+    //
+    HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M;
+}
+
+//*****************************************************************************
+//
+//! Reads a CAN message from one of the message object buffers.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32ObjID is the object number to read (1-32).
+//! \param psMsgObject points to a structure containing message object fields.
+//! \param bClrPendingInt indicates whether an associated interrupt should be
+//! cleared.
+//!
+//! This function is used to read the contents of one of the 32 message objects
+//! in the CAN controller and return it to the caller.  The data returned is
+//! stored in the fields of the caller-supplied structure pointed to by
+//! \e psMsgObject.  The data consists of all of the parts of a CAN message,
+//! plus some control and status information.
+//!
+//! Normally, this function is used to read a message object that has received
+//! and stored a CAN message with a certain identifier.  However, this function
+//! could also be used to read the contents of a message object in order to
+//! load the fields of the structure in case only part of the structure must
+//! be changed from a previous setting.
+//!
+//! When using CANMessageGet(), all of the same fields of the structure are
+//! populated in the same way as when the CANMessageSet() function is used,
+//! with the following exceptions:
+//!
+//! \e psMsgObject->ui32Flags:
+//!
+//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it
+//!   was read
+//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on
+//!   this message object and not read by the host before being overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
+              tCANMsgObject *psMsgObject, bool bClrPendingInt)
+{
+    uint16_t ui16CmdMaskReg;
+    uint16_t ui16MaskReg0, ui16MaskReg1;
+    uint16_t ui16ArbReg0, ui16ArbReg1;
+    uint16_t ui16MsgCtrl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0));
+
+    //
+    // This is always a read to the Message object as this call is setting a
+    // message object.
+    //
+    ui16CmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB |
+                      CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK |
+                      CAN_IF1CMSK_ARB);
+
+    //
+    // Clear a pending interrupt and new data in a message object.
+    //
+    if(bClrPendingInt)
+    {
+        ui16CmdMaskReg |= CAN_IF1CMSK_CLRINTPND;
+    }
+
+    //
+    // Set up the request for data from the message object.
+    //
+    HWREG(ui32Base + CAN_O_IF2CMSK) = ui16CmdMaskReg;
+
+    //
+    // Transfer the message object to the message object specified by
+    // ui32ObjID.
+    //
+    HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M;
+
+    //
+    // Wait for busy bit to clear
+    //
+    while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY)
+    {
+    }
+
+    //
+    // Read out the IF Registers.
+    //
+    ui16MaskReg0 = HWREG(ui32Base + CAN_O_IF2MSK1);
+    ui16MaskReg1 = HWREG(ui32Base + CAN_O_IF2MSK2);
+    ui16ArbReg0 = HWREG(ui32Base + CAN_O_IF2ARB1);
+    ui16ArbReg1 = HWREG(ui32Base + CAN_O_IF2ARB2);
+    ui16MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL);
+
+    psMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS;
+
+    //
+    // Determine if this is a remote frame by checking the TXRQST and DIR bits.
+    //
+    if((!(ui16MsgCtrl & CAN_IF1MCTL_TXRQST) &&
+        (ui16ArbReg1 & CAN_IF1ARB2_DIR)) ||
+       ((ui16MsgCtrl & CAN_IF1MCTL_TXRQST) &&
+        (!(ui16ArbReg1 & CAN_IF1ARB2_DIR))))
+    {
+        psMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME;
+    }
+
+    //
+    // Get the identifier out of the register, the format depends on size of
+    // the mask.
+    //
+    if(ui16ArbReg1 & CAN_IF1ARB2_XTD)
+    {
+        //
+        // Set the 29 bit version of the Identifier for this message object.
+        //
+        psMsgObject->ui32MsgID = (((ui16ArbReg1 & CAN_IF1ARB2_ID_M) << 16) |
+                                  ui16ArbReg0);
+
+        psMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID;
+    }
+    else
+    {
+        //
+        // The Identifier is an 11 bit value.
+        //
+        psMsgObject->ui32MsgID = (ui16ArbReg1 & CAN_IF1ARB2_ID_M) >> 2;
+    }
+
+    //
+    // Indicate that we lost some data.
+    //
+    if(ui16MsgCtrl & CAN_IF1MCTL_MSGLST)
+    {
+        psMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST;
+    }
+
+    //
+    // Set the flag to indicate if ID masking was used.
+    //
+    if(ui16MsgCtrl & CAN_IF1MCTL_UMASK)
+    {
+        if(ui16ArbReg1 & CAN_IF1ARB2_XTD)
+        {
+            //
+            // The Identifier Mask is assumed to also be a 29 bit value.
+            //
+            psMsgObject->ui32MsgIDMask =
+                ((ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | ui16MaskReg0;
+
+            //
+            // If this is a fully specified Mask and a remote frame then don't
+            // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
+            // filtered.
+            //
+            if((psMsgObject->ui32MsgIDMask != 0x1fffffff) ||
+               ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0))
+            {
+                psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER;
+            }
+        }
+        else
+        {
+            //
+            // The Identifier Mask is assumed to also be an 11 bit value.
+            //
+            psMsgObject->ui32MsgIDMask =
+                (ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) >> 2;
+
+            //
+            // If this is a fully specified Mask and a remote frame then don't
+            // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
+            // filtered.
+            //
+            if((psMsgObject->ui32MsgIDMask != 0x7ff) ||
+               ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0))
+            {
+                psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER;
+            }
+        }
+
+        //
+        // Indicate if the extended bit was used in filtering.
+        //
+        if(ui16MaskReg1 & CAN_IF1MSK2_MXTD)
+        {
+            psMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER;
+        }
+
+        //
+        // Indicate if direction filtering was enabled.
+        //
+        if(ui16MaskReg1 & CAN_IF1MSK2_MDIR)
+        {
+            psMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER;
+        }
+    }
+
+    //
+    // Set the interrupt flags.
+    //
+    if(ui16MsgCtrl & CAN_IF1MCTL_TXIE)
+    {
+        psMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE;
+    }
+    if(ui16MsgCtrl & CAN_IF1MCTL_RXIE)
+    {
+        psMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE;
+    }
+
+    //
+    // See if there is new data available.
+    //
+    if(ui16MsgCtrl & CAN_IF1MCTL_NEWDAT)
+    {
+        //
+        // Get the amount of data needed to be read.
+        //
+        psMsgObject->ui32MsgLen = (ui16MsgCtrl & CAN_IF1MCTL_DLC_M);
+
+        //
+        // Don't read any data for a remote frame, there is nothing valid in
+        // that buffer anyway.
+        //
+        if((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)
+        {
+            //
+            // Read out the data from the CAN registers.
+            //
+            _CANDataRegRead(psMsgObject->pui8MsgData,
+                            (uint32_t *)(ui32Base + CAN_O_IF2DA1),
+                            psMsgObject->ui32MsgLen);
+        }
+
+        //
+        // Now clear out the new data flag.
+        //
+        HWREG(ui32Base + CAN_O_IF2CMSK) = CAN_IF1CMSK_NEWDAT;
+
+        //
+        // Transfer the message object to the message object specified by
+        // ui32ObjID.
+        //
+        HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M;
+
+        //
+        // Wait for busy bit to clear
+        //
+        while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY)
+        {
+        }
+
+        //
+        // Indicate that there is new data in this message.
+        //
+        psMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA;
+    }
+    else
+    {
+        //
+        // Along with the MSG_OBJ_NEW_DATA not being set the amount of data
+        // needs to be set to zero if none was available.
+        //
+        psMsgObject->ui32MsgLen = 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears a message object so that it is no longer used.
+//!
+//! \param ui32Base is the base address of the CAN controller.
+//! \param ui32ObjID is the message object number to disable (1-32).
+//!
+//! This function frees the specified message object from use.  Once a message
+//! object has been ``cleared,'' it no longer automatically sends or receives
+//! messages, nor does it generate interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_CANBaseValid(ui32Base));
+    ASSERT((ui32ObjID >= 1) && (ui32ObjID <= 32));
+
+    //
+    // Wait for busy bit to clear
+    //
+    while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+    {
+    }
+
+    //
+    // Clear the message value bit in the arbitration register.  This indicates
+    // the message is not valid.
+    //
+    HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB;
+    HWREG(ui32Base + CAN_O_IF1ARB1) = 0;
+    HWREG(ui32Base + CAN_O_IF1ARB2) = 0;
+
+    //
+    // Initiate programming the message object
+    //
+    HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/can.h b/bsp/tm4c129x/libraries/driverlib/can.h
new file mode 100644
index 0000000000..b89cd7e57a
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/can.h
@@ -0,0 +1,449 @@
+//*****************************************************************************
+//
+// can.h - Defines and Macros for the CAN controller.
+//
+// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CAN_H__
+#define __DRIVERLIB_CAN_H__
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Miscellaneous defines for Message ID Types
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// These are the flags used by the tCANMsgObject.ui32Flags value when calling
+// the CANMessageSet() and CANMessageGet() functions.
+//
+//*****************************************************************************
+
+//
+//! This indicates that transmit interrupts are enabled.
+//
+#define MSG_OBJ_TX_INT_ENABLE   0x00000001
+
+//
+//! This indicates that receive interrupts are enabled.
+//
+#define MSG_OBJ_RX_INT_ENABLE   0x00000002
+
+//
+//! This indicates that a message object is using an extended identifier.
+//
+#define MSG_OBJ_EXTENDED_ID     0x00000004
+
+//
+//! This indicates that a message object is using filtering based on the
+//! object's message identifier.
+//
+#define MSG_OBJ_USE_ID_FILTER   0x00000008
+
+//
+//! This indicates that new data was available in the message object.
+//
+#define MSG_OBJ_NEW_DATA        0x00000080
+
+//
+//! This indicates that data was lost since this message object was last
+//! read.
+//
+#define MSG_OBJ_DATA_LOST       0x00000100
+
+//
+//! This indicates that a message object uses or is using filtering
+//! based on the direction of the transfer.  If the direction filtering is
+//! used, then ID filtering must also be enabled.
+//
+#define MSG_OBJ_USE_DIR_FILTER  (0x00000010 | MSG_OBJ_USE_ID_FILTER)
+
+//
+//! This indicates that a message object uses or is using message
+//! identifier filtering based on the extended identifier.  If the extended
+//! identifier filtering is used, then ID filtering must also be enabled.
+//
+#define MSG_OBJ_USE_EXT_FILTER  (0x00000020 | MSG_OBJ_USE_ID_FILTER)
+
+//
+//! This indicates that a message object is a remote frame.
+//
+#define MSG_OBJ_REMOTE_FRAME    0x00000040
+
+//
+//! This indicates that this message object is part of a FIFO structure and
+//! not the final message object in a FIFO.
+//
+#define MSG_OBJ_FIFO            0x00000200
+
+//
+//! This indicates that a message object has no flags set.
+//
+#define MSG_OBJ_NO_FLAGS        0x00000000
+
+//*****************************************************************************
+//
+//! This define is used with the flag values to allow checking only status
+//! flags and not configuration flags.
+//
+//*****************************************************************************
+#define MSG_OBJ_STATUS_MASK     (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
+
+//*****************************************************************************
+//
+//! The structure used for encapsulating all the items associated with a CAN
+//! message object in the CAN controller.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The CAN message identifier used for 11 or 29 bit identifiers.
+    //
+    uint32_t ui32MsgID;
+
+    //
+    //! The message identifier mask used when identifier filtering is enabled.
+    //
+    uint32_t ui32MsgIDMask;
+
+    //
+    //! This value holds various status flags and settings specified by
+    //! tCANObjFlags.
+    //
+    uint32_t ui32Flags;
+
+    //
+    //! This value is the number of bytes of data in the message object.
+    //
+    uint32_t ui32MsgLen;
+
+    //
+    //! This is a pointer to the message object's data.
+    //
+    uint8_t *pui8MsgData;
+}
+tCANMsgObject;
+
+//*****************************************************************************
+//
+//! This structure is used for encapsulating the values associated with setting
+//! up the bit timing for a CAN controller.  The structure is used when calling
+//! the CANGetBitTiming and CANSetBitTiming functions.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This value holds the sum of the Synchronization, Propagation, and Phase
+    //! Buffer 1 segments, measured in time quanta.  The valid values for this
+    //! setting range from 2 to 16.
+    //
+    uint32_t ui32SyncPropPhase1Seg;
+
+    //
+    //! This value holds the Phase Buffer 2 segment in time quanta.  The valid
+    //! values for this setting range from 1 to 8.
+    //
+    uint32_t ui32Phase2Seg;
+
+    //
+    //! This value holds the Resynchronization Jump Width in time quanta.  The
+    //! valid values for this setting range from 1 to 4.
+    //
+    uint32_t ui32SJW;
+
+    //
+    //! This value holds the CAN_CLK divider used to determine time quanta.
+    //! The valid values for this setting range from 1 to 1023.
+    //
+    uint32_t ui32QuantumPrescaler;
+}
+tCANBitClkParms;
+
+//*****************************************************************************
+//
+//! This data type is used to identify the interrupt status register.  This is
+//! used when calling the CANIntStatus() function.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! Read the CAN interrupt status information.
+    //
+    CAN_INT_STS_CAUSE,
+
+    //
+    //! Read a message object's interrupt status.
+    //
+    CAN_INT_STS_OBJECT
+}
+tCANIntStsReg;
+
+//*****************************************************************************
+//
+//! This data type is used to identify which of several status registers to
+//! read when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! Read the full CAN controller status.
+    //
+    CAN_STS_CONTROL,
+
+    //
+    //! Read the full 32-bit mask of message objects with a transmit request
+    //! set.
+    //
+    CAN_STS_TXREQUEST,
+
+    //
+    //! Read the full 32-bit mask of message objects with new data available.
+    //
+    CAN_STS_NEWDAT,
+
+    //
+    //! Read the full 32-bit mask of message objects that are enabled.
+    //
+    CAN_STS_MSGVAL
+}
+tCANStsReg;
+
+//*****************************************************************************
+//
+// These definitions are used to specify interrupt sources to CANIntEnable()
+// and CANIntDisable().
+//
+//*****************************************************************************
+//
+//! This flag is used to allow a CAN controller to generate error
+//! interrupts.
+//
+#define CAN_INT_ERROR           0x00000008
+
+//
+//! This flag is used to allow a CAN controller to generate status
+//! interrupts.
+//
+#define CAN_INT_STATUS          0x00000004
+
+//
+//! This flag is used to allow a CAN controller to generate any CAN
+//! interrupts.  If this is not set, then no interrupts are generated
+//! by the CAN controller.
+//
+#define CAN_INT_MASTER          0x00000002
+
+//*****************************************************************************
+//
+//! This definition is used to determine the type of message object that is
+//! set up via a call to the CANMessageSet() API.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! Transmit message object.
+    //
+    MSG_OBJ_TYPE_TX,
+
+    //
+    //! Transmit remote request message object
+    //
+    MSG_OBJ_TYPE_TX_REMOTE,
+
+    //
+    //! Receive message object.
+    //
+    MSG_OBJ_TYPE_RX,
+
+    //
+    //! Receive remote request message object.
+    //
+    MSG_OBJ_TYPE_RX_REMOTE,
+
+    //
+    //! Remote frame receive remote, with auto-transmit message object.
+    //
+    MSG_OBJ_TYPE_RXTX_REMOTE
+}
+tMsgObjType;
+
+//*****************************************************************************
+//
+// The following enumeration contains all error or status indicators that can
+// be returned when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+//
+//! CAN controller has entered a Bus Off state.
+//
+#define CAN_STATUS_BUS_OFF      0x00000080
+
+//
+//! CAN controller error level has reached warning level.
+//
+#define CAN_STATUS_EWARN        0x00000040
+
+//
+//! CAN controller error level has reached error passive level.
+//
+#define CAN_STATUS_EPASS        0x00000020
+
+//
+//! A message was received successfully since the last read of this status.
+//
+#define CAN_STATUS_RXOK         0x00000010
+
+//
+//! A message was transmitted successfully since the last read of this
+//! status.
+//
+#define CAN_STATUS_TXOK         0x00000008
+
+//
+//! This is the mask for the last error code field.
+//
+#define CAN_STATUS_LEC_MSK      0x00000007
+
+//
+//! There was no error.
+//
+#define CAN_STATUS_LEC_NONE     0x00000000
+
+//
+//! A bit stuffing error has occurred.
+//
+#define CAN_STATUS_LEC_STUFF    0x00000001
+
+//
+//! A formatting error has occurred.
+//
+#define CAN_STATUS_LEC_FORM     0x00000002
+
+//
+//! An acknowledge error has occurred.
+//
+#define CAN_STATUS_LEC_ACK      0x00000003
+
+//
+//! The bus remained a bit level of 1 for longer than is allowed.
+//
+#define CAN_STATUS_LEC_BIT1     0x00000004
+
+//
+//! The bus remained a bit level of 0 for longer than is allowed.
+//
+#define CAN_STATUS_LEC_BIT0     0x00000005
+
+//
+//! A CRC error has occurred.
+//
+#define CAN_STATUS_LEC_CRC      0x00000006
+
+//
+//! This is the mask for the CAN Last Error Code (LEC).
+//
+#define CAN_STATUS_LEC_MASK     0x00000007
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
+extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
+extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
+                              uint32_t ui32BitRate);
+extern void CANDisable(uint32_t ui32Base);
+extern void CANEnable(uint32_t ui32Base);
+extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
+                          uint32_t *pui32TxCount);
+extern void CANInit(uint32_t ui32Base);
+extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
+extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
+extern void CANIntUnregister(uint32_t ui32Base);
+extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
+extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
+                          tCANMsgObject *psMsgObject, bool bClrPendingInt);
+extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
+                          tCANMsgObject *psMsgObject, tMsgObjType eMsgType);
+extern bool CANRetryGet(uint32_t ui32Base);
+extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
+extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CAN_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/comp.c b/bsp/tm4c129x/libraries/driverlib/comp.c
new file mode 100644
index 0000000000..c57dfa605c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/comp.c
@@ -0,0 +1,452 @@
+//*****************************************************************************
+//
+// comp.c - Driver for the analog comparator.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup comp_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_comp.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/comp.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Configures a comparator.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator to configure.
+//! \param ui32Config is the configuration of the comparator.
+//!
+//! This function configures a comparator.  The \e ui32Config parameter is the
+//! result of a logical OR operation between the \b COMP_TRIG_xxx,
+//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
+//!
+//! The \b COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
+//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
+//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
+//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
+//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
+//! high.
+//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
+//! or high.
+//!
+//! The \b COMP_INT_xxx term can take on the following values:
+//!
+//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
+//! high.
+//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
+//! low.
+//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
+//! low.
+//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
+//! high.
+//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
+//! low or high.
+//!
+//! The \b COMP_ASRCP_xxx term can take on the following values:
+//!
+//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
+//! voltage.
+//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
+//! the same as \b COMP_ASRCP_PIN for the comparator 0).
+//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
+//! reference voltage.
+//!
+//! The \b COMP_OUTPUT_xxx term can take on the following values:
+//!
+//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
+//! to a device pin.
+//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
+//! a device pin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Configure this comparator.
+    //
+    HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACCTL0) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the internal reference voltage.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Ref is the desired reference voltage.
+//!
+//! This function sets the internal reference voltage value.  The voltage is
+//! specified as one of the following values:
+//!
+//! - \b COMP_REF_OFF to turn off the reference voltage
+//! - \b COMP_REF_0V to set the reference voltage to 0 V
+//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
+//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
+//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
+//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
+//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
+//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
+//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
+//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
+//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
+//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
+//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
+//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
+//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
+//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
+//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
+//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
+//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
+//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
+//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
+//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
+//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
+//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
+//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
+//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
+//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
+//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
+//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+
+    //
+    // Set the voltage reference voltage as requested.
+    //
+    HWREG(ui32Base + COMP_O_ACREFCTL) = ui32Ref;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator output value.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//!
+//! This function retrieves the current value of the comparator output.
+//!
+//! \return Returns \b true if the comparator output is high and \b false if
+//! the comparator output is low.
+//
+//*****************************************************************************
+bool
+ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Return the appropriate value based on the comparator's present output
+    // value.
+    //
+    if(HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACSTAT0) &
+       COMP_ACSTAT0_OVAL)
+    {
+        return(true);
+    }
+    else
+    {
+        return(false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the comparator interrupt.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! comparator interrupt occurs.
+//!
+//! This function sets the handler to be called when the comparator interrupt
+//! occurs and enables the interrupt in the interrupt controller.  It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! ComparatorIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
+                      void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(INT_COMP0_TM4C123 + ui32Comp, pfnHandler);
+
+    //
+    // Enable the interrupt in the interrupt controller.
+    //
+    IntEnable(INT_COMP0_TM4C123 + ui32Comp);
+
+    //
+    // Enable the comparator interrupt.
+    //
+    HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp;
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a comparator interrupt.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//!
+//! This function clears the handler to be called when a comparator interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Disable the comparator interrupt.
+    //
+    HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp);
+
+    //
+    // Disable the interrupt in the interrupt controller.
+    //
+    IntDisable(INT_COMP0_TM4C123 + ui32Comp);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_COMP0_TM4C123 + ui32Comp);
+}
+
+//*****************************************************************************
+//
+//! Enables the comparator interrupt.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//!
+//! This function enables generation of an interrupt from the specified
+//! comparator.  Only enabled comparator interrupts can be reflected
+//! to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Enable the comparator interrupt.
+    //
+    HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp;
+}
+
+//*****************************************************************************
+//
+//! Disables the comparator interrupt.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//!
+//! This function disables generation of an interrupt from the specified
+//! comparator.  Only enabled comparator interrupts can be reflected
+//! to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Disable the comparator interrupt.
+    //
+    HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the comparator.  Either the
+//! raw or the masked interrupt status can be returned.
+//!
+//! \return \b true if the interrupt is asserted and \b false if it is not
+//! asserted.
+//
+//*****************************************************************************
+bool
+ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(((HWREG(ui32Base + COMP_O_ACMIS) >> ui32Comp) & 1) ? true :
+               false);
+    }
+    else
+    {
+        return(((HWREG(ui32Base + COMP_O_ACRIS) >> ui32Comp) & 1) ? true :
+               false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears a comparator interrupt.
+//!
+//! \param ui32Base is the base address of the comparator module.
+//! \param ui32Comp is the index of the comparator.
+//!
+//! The comparator interrupt is cleared, so that it no longer asserts.  This
+//! function must be called in the interrupt handler to keep the handler from
+//! being called again immediately upon exit.  Note that for a level-triggered
+//! interrupt, the interrupt cannot be cleared until it stops asserting.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == COMP_BASE);
+    ASSERT(ui32Comp < 3);
+
+    //
+    // Clear the interrupt.
+    //
+    HWREG(ui32Base + COMP_O_ACMIS) = 1 << ui32Comp;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/comp.h b/bsp/tm4c129x/libraries/driverlib/comp.h
new file mode 100644
index 0000000000..538d0c2556
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/comp.h
@@ -0,0 +1,141 @@
+//*****************************************************************************
+//
+// comp.h - Prototypes for the analog comparator driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_COMP_H__
+#define __DRIVERLIB_COMP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorConfigure() as the ui32Config
+// parameter.  For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and
+// so on), one of the values may be selected and combined together with values
+// from the other groups via a logical OR.
+//
+//*****************************************************************************
+#define COMP_TRIG_NONE          0x00000000  // No ADC trigger
+#define COMP_TRIG_HIGH          0x00000880  // Trigger when high
+#define COMP_TRIG_LOW           0x00000800  // Trigger when low
+#define COMP_TRIG_FALL          0x00000820  // Trigger on falling edge
+#define COMP_TRIG_RISE          0x00000840  // Trigger on rising edge
+#define COMP_TRIG_BOTH          0x00000860  // Trigger on both edges
+#define COMP_INT_HIGH           0x00000010  // Interrupt when high
+#define COMP_INT_LOW            0x00000000  // Interrupt when low
+#define COMP_INT_FALL           0x00000004  // Interrupt on falling edge
+#define COMP_INT_RISE           0x00000008  // Interrupt on rising edge
+#define COMP_INT_BOTH           0x0000000C  // Interrupt on both edges
+#define COMP_ASRCP_PIN          0x00000000  // Dedicated Comp+ pin
+#define COMP_ASRCP_PIN0         0x00000200  // Comp0+ pin
+#define COMP_ASRCP_REF          0x00000400  // Internal voltage reference
+#define COMP_OUTPUT_NORMAL      0x00000000  // Comparator output normal
+#define COMP_OUTPUT_INVERT      0x00000002  // Comparator output inverted
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter.
+//
+//*****************************************************************************
+#define COMP_REF_OFF            0x00000000  // Turn off the internal reference
+#define COMP_REF_0V             0x00000300  // Internal reference of 0V
+#define COMP_REF_0_1375V        0x00000301  // Internal reference of 0.1375V
+#define COMP_REF_0_275V         0x00000302  // Internal reference of 0.275V
+#define COMP_REF_0_4125V        0x00000303  // Internal reference of 0.4125V
+#define COMP_REF_0_55V          0x00000304  // Internal reference of 0.55V
+#define COMP_REF_0_6875V        0x00000305  // Internal reference of 0.6875V
+#define COMP_REF_0_825V         0x00000306  // Internal reference of 0.825V
+#define COMP_REF_0_928125V      0x00000201  // Internal reference of 0.928125V
+#define COMP_REF_0_9625V        0x00000307  // Internal reference of 0.9625V
+#define COMP_REF_1_03125V       0x00000202  // Internal reference of 1.03125V
+#define COMP_REF_1_134375V      0x00000203  // Internal reference of 1.134375V
+#define COMP_REF_1_1V           0x00000308  // Internal reference of 1.1V
+#define COMP_REF_1_2375V        0x00000309  // Internal reference of 1.2375V
+#define COMP_REF_1_340625V      0x00000205  // Internal reference of 1.340625V
+#define COMP_REF_1_375V         0x0000030A  // Internal reference of 1.375V
+#define COMP_REF_1_44375V       0x00000206  // Internal reference of 1.44375V
+#define COMP_REF_1_5125V        0x0000030B  // Internal reference of 1.5125V
+#define COMP_REF_1_546875V      0x00000207  // Internal reference of 1.546875V
+#define COMP_REF_1_65V          0x0000030C  // Internal reference of 1.65V
+#define COMP_REF_1_753125V      0x00000209  // Internal reference of 1.753125V
+#define COMP_REF_1_7875V        0x0000030D  // Internal reference of 1.7875V
+#define COMP_REF_1_85625V       0x0000020A  // Internal reference of 1.85625V
+#define COMP_REF_1_925V         0x0000030E  // Internal reference of 1.925V
+#define COMP_REF_1_959375V      0x0000020B  // Internal reference of 1.959375V
+#define COMP_REF_2_0625V        0x0000030F  // Internal reference of 2.0625V
+#define COMP_REF_2_165625V      0x0000020D  // Internal reference of 2.165625V
+#define COMP_REF_2_26875V       0x0000020E  // Internal reference of 2.26875V
+#define COMP_REF_2_371875V      0x0000020F  // Internal reference of 2.371875V
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
+                                uint32_t ui32Config);
+extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref);
+extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp);
+extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
+                                  void (*pfnHandler)(void));
+extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp);
+extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp);
+extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp);
+extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp,
+                                bool bMasked);
+extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_COMP_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/cpu.c b/bsp/tm4c129x/libraries/driverlib/cpu.c
new file mode 100644
index 0000000000..ab7efbe7ae
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/cpu.c
@@ -0,0 +1,457 @@
+//*****************************************************************************
+//
+// cpu.c - Instruction wrappers for special CPU instructions needed by the
+//         drivers.
+//
+// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "driverlib/cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+uint32_t __attribute__((naked))
+CPUcpsid(void)
+{
+    uint32_t ui32Ret;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    bx      lr\n"
+          : "=r" (ui32Ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ui32Ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    cpsid   i;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+uint32_t
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+uint32_t __attribute__((naked))
+CPUprimask(void)
+{
+    uint32_t ui32Ret;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n"
+          : "=r" (ui32Ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ui32Ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+uint32_t
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+uint32_t __attribute__((naked))
+CPUcpsie(void)
+{
+    uint32_t ui32Ret;
+
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    bx      lr\n"
+          : "=r" (ui32Ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ui32Ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    cpsie   i;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+uint32_t
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    wfi;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    msr     BASEPRI, r0;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+uint32_t __attribute__((naked))
+CPUbasepriGet(void)
+{
+    uint32_t ui32Ret;
+
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n"
+          : "=r" (ui32Ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ui32Ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    mrs     r0, BASEPRI;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+uint32_t
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
diff --git a/bsp/tm4c129x/libraries/driverlib/cpu.h b/bsp/tm4c129x/libraries/driverlib/cpu.h
new file mode 100644
index 0000000000..d87b81f612
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/cpu.h
@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CPU_H__
+#define __DRIVERLIB_CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern uint32_t CPUcpsid(void);
+extern uint32_t CPUcpsie(void);
+extern uint32_t CPUprimask(void);
+extern void CPUwfi(void);
+extern uint32_t CPUbasepriGet(void);
+extern void CPUbasepriSet(uint32_t ui32NewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CPU_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/crc.c b/bsp/tm4c129x/libraries/driverlib/crc.c
new file mode 100644
index 0000000000..0d7d2538ce
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/crc.c
@@ -0,0 +1,311 @@
+//*****************************************************************************
+//
+// crc.c - Driver for the CRC module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup crc_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ccm.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/crc.h"
+#include "driverlib/debug.h"
+
+
+//*****************************************************************************
+//
+//! Set the configuration of CRC functionality with the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32CRCConfig is the configuration of the CRC engine.
+//!
+//! This function configures the operation of the CRC engine within the EC
+//! module.  The configuration is specified with the \e ui32CRCConfig argument.
+//! It is the logical OR of any of the following options:
+//!
+//! CRC Initialization Value
+//! - \b CRC_CFG_INIT_SEED - Initialize with seed value
+//! - \b CRC_CFG_INIT_0 - Initialize to all '0s'
+//! - \b CRC_CFG_INIT_1 - Initialize to all '1s'
+//!
+//! Input Data Size
+//! - \b CRC_CFG_SIZE_8BIT - Input data size of 8 bits
+//! - \b CRC_CFG_SIZE_32BIT - Input data size of 32 bits
+//!
+//! Post Process Reverse/Inverse
+//! - \b CRC_CFG_RESINV - Result inverse enable
+//! - \b CRC_CFG_OBR - Output reverse enable
+//!
+//! Input Bit Reverse
+//! - \b CRC_CFG_IBR - Bit reverse enable
+//!
+//! Endian Control
+//! - \b CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
+//! - \b CRC_CFG_ENDIAN_SHW - Swap half-word
+//!
+//! Operation Type
+//! - \b CRC_CFG_TYPE_P8005 - Polynomial 0x8005
+//! - \b CRC_CFG_TYPE_P1021 - Polynomial 0x1021
+//! - \b CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
+//! - \b CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
+//! - \b CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == CCM0_BASE);
+    ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
+           (ui32CRCConfig & CRC_CFG_INIT_0) ||
+           (ui32CRCConfig & CRC_CFG_INIT_1) ||
+           (ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
+           (ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
+           (ui32CRCConfig & CRC_CFG_RESINV) ||
+           (ui32CRCConfig & CRC_CFG_OBR) ||
+           (ui32CRCConfig & CRC_CFG_IBR) ||
+           (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
+           (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
+
+    //
+    // Write the control register with the configuration.
+    //
+    HWREG(ui32Base + CCM_O_CRCCTRL) = ui32CRCConfig;
+}
+
+//*****************************************************************************
+//
+//! Write the seed value for CRC operations in the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32Seed is the seed value.
+//!
+//! This function writes the seed value for use with CRC operations in the
+//! EC module.  This value is the start value for CRC operations.  If this
+//! value is not written, then the residual seed from the previous operation
+//! is used as the starting value.
+//!
+//! \note The seed must be written only if \b CRC_CFG_INIT_SEED is
+//! set with the CRCConfigSet() function.
+//
+//*****************************************************************************
+void
+CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == CCM0_BASE);
+
+    //
+    // Write the seed value to the seed register.
+    //
+    HWREG(ui32Base + CCM_O_CRCSEED) = ui32Seed;
+}
+
+//*****************************************************************************
+//
+//! Write data into the EC module for CRC operations.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32Data is the data to be written.
+//!
+//! This function writes either 8 or 32 bits of data into the EC module for
+//! CRC operations.  The distinction between 8 and 32 bits of data is made
+//! when the \b CRC_CFG_SIZE_8BIT or \b CRC_CFG_SIZE_32BIT flag
+//! is set using the CRCConfigSet() function.
+//!
+//! When writing 8 bits of data, ensure the data is in the least significant
+//! byte position.  The remaining bytes should be written with zero.  For
+//! example, when writing 0xAB, \e ui32Data should be 0x000000AB.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == CCM0_BASE);
+
+    //
+    // Write the data
+    //
+    HWREG(ui32Base + CCM_O_CRCDIN) = ui32Data;
+}
+
+//*****************************************************************************
+//
+//! Reads the result of a CRC operation in the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param bPPResult is \b true to read the post-processed result, or \b false
+//! to read the unmodified result.
+//!
+//! This function reads either the unmodified CRC result or the post
+//! processed CRC result from the EC module.  The post-processing options
+//! are selectable through \b CRC_CFG_RESINV and \b CRC_CFG_OBR
+//! parameters in the CRCConfigSet() function.
+//!
+//! \return The CRC result.
+//
+//*****************************************************************************
+uint32_t
+CRCResultRead(uint32_t ui32Base, bool bPPResult)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == CCM0_BASE);
+
+    //
+    // Depending on the value of bPPResult, read the appropriate register and
+    // return value.
+    //
+    if(bPPResult)
+    {
+        return(HWREG(ui32Base + CCM_O_CRCRSLTPP));
+    }
+    else
+    {
+        return(HWREG(ui32Base + CCM_O_CRCSEED));
+    }
+}
+
+//*****************************************************************************
+//
+//! Process data to generate a CRC with the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param pui32DataIn is a pointer to an array of data that is processed.
+//! \param ui32DataLength is the number of data items that are processed
+//! to produce the CRC.
+//! \param bPPResult is \b true to read the post-processed result, or \b false
+//! to read the unmodified result.
+//!
+//! This function processes an array of data to produce a CRC result.
+//!
+//! The data in the array pointed to be \e pui32DataIn is either an array
+//! of bytes or an array or words depending on the selection of the input
+//! data size options \b CRC_CFG_SIZE_8BIT and
+//! \b CRC_CFG_SIZE_32BIT.
+//!
+//! This function returns either the unmodified CRC result or the
+//! post- processed CRC result from the EC module.  The post-processing
+//! options are selectable through \b CRC_CFG_RESINV and
+//! \b CRC_CFG_OBR parameters.
+//!
+//! \return The CRC result.
+//
+//*****************************************************************************
+uint32_t
+CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn,
+               uint32_t ui32DataLength, bool bPPResult)
+{
+    uint8_t *pui8DataIn;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == CCM0_BASE);
+
+    //
+    // See if the CRC is operating in 8-bit or 32-bit mode.
+    //
+    if(HWREG(ui32Base + CCM_O_CRCCTRL) & CCM_CRCCTRL_SIZE)
+    {
+        //
+        // The CRC is operating in 8-bit mode, so create an 8-bit pointer to
+        // the data.
+        //
+        pui8DataIn = (uint8_t *)pui32DataIn;
+
+        //
+        // Loop through the input data.
+        //
+        while(ui32DataLength--)
+        {
+            //
+            // Write the next data byte.
+            //
+            HWREG(ui32Base + CCM_O_CRCDIN) = *pui8DataIn++;
+        }
+    }
+    else
+    {
+        //
+        // The CRC is operating in 32-bit mode, so loop through the input data.
+        //
+        while(ui32DataLength--)
+        {
+            //
+            // Write the next data word.
+            //
+            HWREG(ui32Base + CCM_O_CRCDIN) = *pui32DataIn++;
+        }
+    }
+
+    //
+    // Return the result.
+    //
+    return(CRCResultRead(ui32Base, bPPResult));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/crc.h b/bsp/tm4c129x/libraries/driverlib/crc.h
new file mode 100644
index 0000000000..b6fc1f49fd
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/crc.h
@@ -0,0 +1,101 @@
+//*****************************************************************************
+//
+// crc.h - Defines and Macros for CRC module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CRC_H__
+#define __DRIVERLIB_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used in the ui32Config argument of the
+// ECConfig function.
+//
+//*****************************************************************************
+#define CRC_CFG_INIT_SEED       0x00000000  // Initialize with seed
+#define CRC_CFG_INIT_0          0x00004000  // Initialize to all '0s'
+#define CRC_CFG_INIT_1          0x00006000  // Initialize to all '1s'
+#define CRC_CFG_SIZE_8BIT       0x00001000  // Input Data Size
+#define CRC_CFG_SIZE_32BIT      0x00000000  // Input Data Size
+#define CRC_CFG_RESINV          0x00000200  // Result Inverse Enable
+#define CRC_CFG_OBR             0x00000100  // Output Reverse Enable
+#define CRC_CFG_IBR             0x00000080  // Bit reverse enable
+#define CRC_CFG_ENDIAN_SBHW     0x00000000  // Swap byte in half-word
+#define CRC_CFG_ENDIAN_SHW      0x00000010  // Swap half-word
+#define CRC_CFG_TYPE_P8005      0x00000000  // Polynomial 0x8005
+#define CRC_CFG_TYPE_P1021      0x00000001  // Polynomial 0x1021
+#define CRC_CFG_TYPE_P4C11DB7   0x00000002  // Polynomial 0x4C11DB7
+#define CRC_CFG_TYPE_P1EDC6F41  0x00000003  // Polynomial 0x1EDC6F41
+#define CRC_CFG_TYPE_TCPCHKSUM  0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+#if 0
+extern void ECClockGatingReqest(uint32_t ui32Base, uint32_t ui32ECIP,
+                                bool bGate);
+#endif
+extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
+extern uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn,
+                               uint32_t ui32DataLength, bool bPPResult);
+extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
+extern uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult);
+extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CRC_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/debug.h b/bsp/tm4c129x/libraries/driverlib/debug.h
new file mode 100644
index 0000000000..266df8d43e
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/debug.h
@@ -0,0 +1,70 @@
+//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_DEBUG_H__
+#define __DRIVERLIB_DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, uint32_t ui32Line);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) do                                                       \
+                     {                                                        \
+                         if(!(expr))                                          \
+                         {                                                    \
+                             __error__(__FILE__, __LINE__);                   \
+                         }                                                    \
+                     }                                                        \
+                     while(0)
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DRIVERLIB_DEBUG_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/des.c b/bsp/tm4c129x/libraries/driverlib/des.c
new file mode 100644
index 0000000000..1e487b507b
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/des.c
@@ -0,0 +1,807 @@
+//*****************************************************************************
+//
+// des.c - Driver for the DES data transformation.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup des_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_des.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/des.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Resets the DES Module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//!
+//! This function performs a soft-reset sequence of the DES module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESReset(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Trigger the soft reset.
+    //
+    HWREG(ui32Base + DES_O_SYSCONFIG) |= DES_SYSCONFIG_SOFTRESET;
+
+    //
+    // Wait for the reset to finish.
+    //
+    while((HWREG(ui32Base + DES_O_SYSSTATUS) &
+           DES_SYSSTATUS_RESETDONE) == 0)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+//! Configures the DES module for operation.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Config is the configuration of the DES module.
+//!
+//! This function configures the DES module for operation.
+//!
+//! The \e ui32Config parameter is a bit-wise OR of a number of configuration
+//! flags.  The valid flags are grouped below based on their function.
+//!
+//! The direction of the operation is specified with one of the following two
+//! flags.  Only one is permitted.
+//!
+//! - \b DES_CFG_DIR_ENCRYPT - Encryption
+//! - \b DES_CFG_DIR_DECRYPT - Decryption
+//!
+//! The operational mode of the DES engine is specified with one of the
+//! following flags.  Only one is permitted.
+//!
+//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode
+//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode
+//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode
+//!
+//! The selection of single DES or triple DES is specified with one of the
+//! following two flags.  Only one is permitted.
+//!
+//! - \b DES_CFG_SINGLE - Single DES
+//! - \b DES_CFG_TRIPLE - Triple DES
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Backup the save context field.
+    //
+    ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT);
+
+    //
+    // Write the control register.
+    //
+    HWREG(ui32Base + DES_O_CTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the key used for DES operations.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32Key is a pointer to an array that holds the key
+//!
+//! This function sets the key used for DES operations.
+//!
+//! \e pui32Key should be 64 bits long (2 words) if single DES is being used or
+//! 192 bits (6 words) if triple DES is being used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESKeySet(uint32_t ui32Base, uint32_t *pui32Key)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Write the first part of the key.
+    //
+    HWREG(ui32Base + DES_O_KEY1_L) = pui32Key[0];
+    HWREG(ui32Base + DES_O_KEY1_H) = pui32Key[1];
+
+    //
+    // If we are performing tripe DES, then write the key registers for
+    // the second and third rounds.
+    //
+    if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE)
+    {
+        HWREG(ui32Base + DES_O_KEY2_L) = pui32Key[2];
+        HWREG(ui32Base + DES_O_KEY2_H) = pui32Key[3];
+        HWREG(ui32Base + DES_O_KEY3_L) = pui32Key[4];
+        HWREG(ui32Base + DES_O_KEY3_H) = pui32Key[5];
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the initialization vector in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32IVdata is a pointer to an array of 64 bits (2 words) of data to
+//! be written into the initialization vectors registers.
+//!
+//! This function sets the initialization vector in the DES module.  It returns
+//! true if the registers were successfully written.  If the context registers
+//! cannot be written at the time the function was called, then false is
+//! returned.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Check to see if context registers can be overwritten.  If not, return
+    // false.
+    //
+    if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0)
+    {
+        return(false);
+    }
+
+    //
+    // Write the initialization vector registers.
+    //
+    HWREG(ui32Base + DES_O_IV_L) = pui32IVdata[0];
+    HWREG(ui32Base + DES_O_IV_H) = pui32IVdata[1];
+
+    //
+    // Return true to indicate the write was successful.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Sets the crytographic data length in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Length is the length of the data in bytes.
+//!
+//! This function writes the cryptographic data length into the DES module.
+//! When this register is written, the engine is triggered to start using this
+//! context.
+//!
+//! \note Data lengths up to (2^32 - 1) bytes are allowed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Write the length register.
+    //
+    HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32Dest is a pointer to an array of 2 words.
+//!
+//! This function returns true if the data was ready when the function was
+//! called.  If the data was not ready, false is returned.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Check to see if the data is ready to be read.
+    //
+    if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+    {
+        return(false);
+    }
+
+    //
+    // Read two words of data from the data registers.
+    //
+    pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
+    pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
+
+    //
+    // Return true to indicate a successful write.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers with blocking.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32Dest is a pointer to an array of bytes.
+//!
+//! This function waits until the DES module is finished and encrypted or
+//! decrypted data is ready.  The output data is then stored in the pui32Dest
+//! array.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Wait for data output to be ready.
+    //
+    while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0)
+    {
+    }
+
+    //
+    // Read two words of data from the data registers.
+    //
+    pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
+    pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32Src is a pointer to an array of 2 words.
+//!
+//! This function returns false if the DES module is not ready to accept
+//! data.  It returns true if the data was written successfully.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Check if the DES module is ready to encrypt or decrypt data.  If it
+    // is not, return false.
+    //
+    if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))))
+    {
+        return(false);
+    }
+
+    //
+    // Write the data.
+    //
+    HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
+    HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
+
+    //
+    // Return true to indicate a successful write.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32Src is a pointer to an array of bytes.
+//!
+//! This function waits until the DES module is ready before writing the
+//! data contained in the pui32Src array.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Wait for the input ready bit to go high.
+    //
+    while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0)
+    {
+    }
+
+    //
+    // Write the data.
+    //
+    HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
+    HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
+}
+
+//*****************************************************************************
+//
+//! Processes blocks of data through the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui32Src is a pointer to an array of words that contains the
+//! source data for processing.
+//! \param pui32Dest is a pointer to an array of words consisting of the
+//! processed data.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//! It must be a multiple of eight.
+//!
+//! This function takes the data contained in the pui32Src array and processes
+//! it using the DES engine.  The resulting data is stored in the
+//! pui32Dest array.  The function blocks until all of the data has been
+//! processed.  If processing is successful, the function returns true.
+//!
+//! \note This functions assumes that the DES module has been configured,
+//! and initialization values and keys have been written.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest,
+               uint32_t ui32Length)
+{
+    uint32_t ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32Length % 8) == 0);
+
+    //
+    // Write the length register first.  This triggers the engine to start
+    // using this context.
+    //
+    HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
+
+    //
+    // Now loop until the blocks are written.
+    //
+    for(ui32Count = 0; ui32Count < (ui32Length / 4); ui32Count += 2)
+    {
+        //
+        // Check if the input ready is fine
+        //
+        while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+        {
+        }
+
+        //
+        // Write the block data.
+        //
+        DESDataWriteNonBlocking(ui32Base, pui32Src + ui32Count);
+
+        //
+        // Wait for the output ready
+        //
+        while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+        {
+        }
+
+        //
+        // Read the processed data block.
+        //
+        DESDataReadNonBlocking(ui32Base, pui32Dest + ui32Count);
+    }
+
+    //
+    // Return true to indicate the process was successful.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Returns the current interrupt status of the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function gets the current interrupt status of the DES module.
+//! The value returned is a logical OR of the following values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT_INT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return A bit mask of the current interrupt status.
+//
+//*****************************************************************************
+uint32_t
+DESIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    uint32_t ui32Status, ui32Enable;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Read the status register and return the value.
+    //
+    ui32Status = HWREG(ui32Base + DES_O_IRQSTATUS);
+    if(bMasked)
+    {
+        ui32Enable = HWREG(ui32Base + DES_O_IRQENABLE);
+        return((ui32Status & ui32Enable) |
+               (HWREG(ui32Base + DES_O_DMAMIS) << 16));
+    }
+    else
+    {
+        return(ui32Status | (HWREG(ui32Base + DES_O_DMARIS) << 16));
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be enabled.
+//!
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DATA_OUT) ||
+           (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+    //
+    // Enable the interrupts from the flags.
+    //
+    HWREG(ui32Base + DES_O_DMAIM) |= (ui32IntFlags & 0x00070000) >> 16;
+    HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
+//!
+//! This function disables interrupt sources in the DES module.
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DATA_OUT) ||
+           (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+    //
+    // Clear the interrupts from the flags.
+    //
+    HWREG(ui32Base + DES_O_DMAIM) &= ~((ui32IntFlags & 0x00070000) >> 16);
+    HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+}
+
+//*****************************************************************************
+//
+//! Clears interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
+//!
+//! This function disables interrupt sources in the DES module.
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt
+//!
+//! \note The DMA done interrupts are the only interrupts that can be cleared.
+//! The remaining interrupts can be disabled instead using DESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+    HWREG(ui32Base + DES_O_DMAIC) = (ui32IntFlags & 0x00070000) >> 16;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled DES interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables DES interrupts on the interrupt controller; specific DES
+//! interrupt sources must be enabled using DESIntEnable().  The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! DESIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable DES interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_DES0_TM4C129, pfnHandler);
+
+    //
+    // Enable the interrupt.
+    //
+    IntEnable(INT_DES0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntUnregister(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_DES0_TM4C129);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_DES0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Enables DMA request sources in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Flags is a bit mask of the DMA requests to be enabled.
+//!
+//! This function enables DMA request sources in the DES module.  The
+//! \e ui32Flags parameter should be the logical OR of any of the following:
+//!
+//! - \b DES_DMA_CONTEXT_IN - Context In
+//! - \b DES_DMA_DATA_OUT - Data Out
+//! - \b DES_DMA_DATA_IN - Data In
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
+           (ui32Flags & DES_DMA_DATA_OUT) ||
+           (ui32Flags & DES_DMA_DATA_IN));
+
+    //
+    // Set the data in and data out DMA request enable bits.
+    //
+    HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags;
+}
+
+//*****************************************************************************
+//
+//! Disables DMA request sources in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Flags is a bit mask of the DMA requests to be disabled.
+//!
+//! This function disables DMA request sources in the DES module.  The
+//! \e ui32Flags parameter should be the logical OR of any of the following:
+//!
+//! - \b DES_DMA_CONTEXT_IN - Context In
+//! - \b DES_DMA_DATA_OUT - Data Out
+//! - \b DES_DMA_DATA_IN - Data In
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
+           (ui32Flags & DES_DMA_DATA_OUT) ||
+           (ui32Flags & DES_DMA_DATA_IN));
+
+    //
+    // Disable the DMA sources.
+    //
+    HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/des.h b/bsp/tm4c129x/libraries/driverlib/des.h
new file mode 100644
index 0000000000..5d1d229505
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/des.h
@@ -0,0 +1,140 @@
+//*****************************************************************************
+//
+// des.h - Defines and Macros for the DES module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_DES_H__
+#define __DRIVERLIB_DES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the direction with the
+// ui32Config argument in the DESConfig() function.  Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_DIR_DECRYPT     0x00000000
+#define DES_CFG_DIR_ENCRYPT     0x00000004
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operational with the
+// ui32Config argument in the DESConfig() function.  Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_MODE_ECB        0x00000000
+#define DES_CFG_MODE_CBC        0x00000010
+#define DES_CFG_MODE_CFB        0x00000020
+
+//*****************************************************************************
+//
+// The following defines are used to select between single DES and triple DES
+// with the ui32Config argument in the DESConfig() function.  Only one is
+// permitted.
+//
+//*****************************************************************************
+#define DES_CFG_SINGLE          0x00000000
+#define DES_CFG_TRIPLE          0x00000008
+
+//*****************************************************************************
+//
+// The following defines are used with the DESIntEnable(), DESIntDisable() and
+// DESIntStatus() functions.
+//
+//*****************************************************************************
+#define DES_INT_CONTEXT_IN      0x00000001
+#define DES_INT_DATA_IN         0x00000002
+#define DES_INT_DATA_OUT        0x00000004
+#define DES_INT_DMA_CONTEXT_IN  0x00010000
+#define DES_INT_DMA_DATA_IN     0x00020000
+#define DES_INT_DMA_DATA_OUT    0x00040000
+
+//*****************************************************************************
+//
+// The following defines are used with the DESEnableDMA() and DESDisableDMA()
+// functions.
+//
+//*****************************************************************************
+#define DES_DMA_CONTEXT_IN      0x00000080
+#define DES_DMA_DATA_OUT        0x00000040
+#define DES_DMA_DATA_IN         0x00000020
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
+extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
+extern bool DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
+                           uint32_t *pui32Dest, uint32_t ui32Length);
+extern void DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
+extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
+extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void DESIntUnregister(uint32_t ui32Base);
+extern bool DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
+extern void DESKeySet(uint32_t ui32Base, uint32_t *pui32Key);
+extern void DESLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern void DESReset(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_DES_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/eeprom.c b/bsp/tm4c129x/libraries/driverlib/eeprom.c
new file mode 100644
index 0000000000..bb0a99d683
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/eeprom.c
@@ -0,0 +1,1156 @@
+//*****************************************************************************
+//
+// eeprom.c - Driver for programming the on-chip EEPROM.
+//
+// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_eeprom.h"
+#include "inc/hw_flash.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/eeprom.h"
+
+//*****************************************************************************
+//
+//! \addtogroup eeprom_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Useful macros to extract the number of EEPROM blocks available on the target
+// device and the total EEPROM storage in bytes from the EESIZE register.
+//
+//*****************************************************************************
+#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >>              \
+                               EEPROM_EESIZE_BLKCNT_S)
+#define SIZE_FROM_EESIZE(x)   ((((x) & EEPROM_EESIZE_WORDCNT_M) >>            \
+                                EEPROM_EESIZE_WORDCNT_S) * 4)
+
+//*****************************************************************************
+//
+// Useful macro to extract the offset from a linear address.
+//
+//*****************************************************************************
+#define OFFSET_FROM_ADDR(x) (((x) >> 2) & 0x0F)
+
+//*****************************************************************************
+//
+// The key value required to initiate a mass erase.
+//
+//*****************************************************************************
+#define EEPROM_MASS_ERASE_KEY ((uint32_t)0xE37B << EEPROM_EEDBGME_KEY_S)
+
+//*****************************************************************************
+//
+// This function implements a workaround for a bug in Blizzard rev A silicon.
+// It ensures that only the 1KB flash sector containing a given EEPROM address
+// is erased if an erase/copy operation is required as a result of a following
+// EEPROM write.
+//
+//*****************************************************************************
+static void
+_EEPROMSectorMaskSet(uint32_t ui32Address)
+{
+    uint32_t ui32Mask;
+
+    //
+    // Determine which page contains the passed EEPROM address.  The 2KB EEPROM
+    // is implemented in 16KB of flash with each 1KB sector of flash holding
+    // values for 32 consecutive EEPROM words (or 128 bytes).
+    //
+    ui32Mask = ~(1 << (ui32Address >> 7));
+
+    SysCtlDelay(10);
+    HWREG(0x400FD0FC) = 3;
+    SysCtlDelay(10);
+    HWREG(0x400AE2C0) = ui32Mask;
+    SysCtlDelay(10);
+    HWREG(0x400FD0FC) = 0;
+    SysCtlDelay(10);
+}
+
+//*****************************************************************************
+//
+// Clear the FSM sector erase mask to ensure that any following main array
+// flash erase operations operate as expected.
+//
+//*****************************************************************************
+static void
+_EEPROMSectorMaskClear(void)
+{
+    SysCtlDelay(10);
+    HWREG(0x400FD0FC) = 3;
+    SysCtlDelay(10);
+    HWREG(0x400AE2C0) = 0;
+    SysCtlDelay(10);
+    HWREG(0x400FD0FC) = 0;
+    SysCtlDelay(10);
+}
+
+//*****************************************************************************
+//
+// Block until the EEPROM peripheral is not busy.
+//
+//*****************************************************************************
+static void
+_EEPROMWaitForDone(void)
+{
+    //
+    // Is the EEPROM still busy?
+    //
+    while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING)
+    {
+        //
+        // Spin while EEPROM is busy.
+        //
+    }
+}
+
+//*****************************************************************************
+//
+//! Performs any necessary recovery in case of power failures during write.
+//!
+//! This function \b must be called after SysCtlPeripheralEnable() and before
+//! the EEPROM is accessed.  It is used to check for errors in the EEPROM state
+//! such as from power failure during a previous write operation.  The function
+//! detects these errors and performs as much recovery as possible.
+//!
+//! If \b EEPROM_INIT_ERROR is returned, the EEPROM was unable to recover its
+//! state.  If power is stable when this occurs, this indicates a fatal
+//! error and is likely an indication that the EEPROM memory has exceeded its
+//! specified lifetime write/erase specification.  If the supply voltage is
+//! unstable when this return code is observed, retrying the operation once the
+//! voltage is stabilized may clear the error.
+//!
+//! Failure to call this function after a reset may lead to incorrect operation
+//! or permanent data loss if the EEPROM is later written.
+//!
+//! \return Returns \b EEPROM_INIT_OK if no errors were detected or \b
+//! EEPROM_INIT_ERROR if the EEPROM peripheral cannot currently recover from
+//! an interrupted write or erase operation.
+//
+//*****************************************************************************
+uint32_t
+EEPROMInit(void)
+{
+    uint32_t ui32Status;
+
+    //
+    // Insert a small delay (6 cycles + call overhead) to guard against the
+    // possibility that this function is called immediately after the EEPROM
+    // peripheral is enabled.  Without this delay, there is a slight chance
+    // that the first EEPROM register read will fault if you are using a
+    // compiler with a ridiculously good optimizer!
+    //
+    SysCtlDelay(2);
+
+    //
+    // Make sure the EEPROM has finished any ongoing processing.
+    //
+    _EEPROMWaitForDone();
+
+    //
+    // Read the EESUPP register to see if any errors have been reported.
+    //
+    ui32Status = HWREG(EEPROM_EESUPP);
+
+    //
+    // Did an error of some sort occur during initialization?
+    //
+    if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY))
+    {
+        return(EEPROM_INIT_ERROR);
+    }
+
+    //
+    // Perform a second EEPROM reset.
+    //
+    SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0);
+
+    //
+    // Wait for the EEPROM to complete its reset processing once again.
+    //
+    SysCtlDelay(2);
+    _EEPROMWaitForDone();
+
+    //
+    // Read EESUPP once again to determine if any error occurred.
+    //
+    ui32Status = HWREG(EEPROM_EESUPP);
+
+    //
+    // Was an error reported following the second reset?
+    //
+    if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY))
+    {
+        return(EEPROM_INIT_ERROR);
+    }
+
+    //
+    // The EEPROM does not indicate that any error occurred.
+    //
+    return(EEPROM_INIT_OK);
+}
+
+
+//*****************************************************************************
+//
+//! Determines the size of the EEPROM.
+//!
+//! This function returns the size of the EEPROM in bytes.
+//!
+//! \return Returns the total number of bytes in the EEPROM.
+//
+//*****************************************************************************
+uint32_t
+EEPROMSizeGet(void)
+{
+    //
+    // Return the size of the EEPROM in bytes.
+    //
+    return(SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+}
+
+//*****************************************************************************
+//
+//! Determines the number of blocks in the EEPROM.
+//!
+//! This function may be called to determine the number of blocks in the
+//! EEPROM.  Each block is the same size and the number of bytes of storage
+//! contained in a block may be determined by dividing the size of the device,
+//! obtained via a call to the EEPROMSizeGet() function, by the number of
+//! blocks returned by this function.
+//!
+//! \return Returns the total number of blocks in the device EEPROM.
+//
+//*****************************************************************************
+uint32_t
+EEPROMBlockCountGet(void)
+{
+    //
+    // Extract the number of blocks and return it to the caller.
+    //
+#ifdef EEPROM_SIZE_LIMIT
+    //
+    // If a size limit has been specified, fake the number of blocks to match.
+    //
+    return(EEPROM_SIZE_LIMIT / 48);
+#else
+    //
+    // Return the actual number of blocks supported by the hardware.
+    //
+    return(BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+#endif
+}
+
+//*****************************************************************************
+//
+//! Reads data from the EEPROM.
+//!
+//! \param pui32Data is a pointer to storage for the data read from the EEPROM.
+//! This pointer must point to at least \e ui32Count bytes of available memory.
+//! \param ui32Address is the byte address within the EEPROM from which data is
+//! to be read.  This value must be a multiple of 4.
+//! \param ui32Count is the number of bytes of data to read from the EEPROM.
+//! This value must be a multiple of 4.
+//!
+//! This function may be called to read a number of words of data from a
+//! word-aligned address within the EEPROM.  Data read is copied into the
+//! buffer pointed to by the \e pui32Data parameter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count)
+{
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(pui32Data);
+    ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT((ui32Address + ui32Count) <=
+           SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT((ui32Address & 3) == 0);
+    ASSERT((ui32Count & 3) == 0);
+
+    //
+    // Set the block and offset appropriately to read the first word.
+    //
+    HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address);
+    HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address);
+
+    //
+    // Convert the byte count to a word count.
+    //
+    ui32Count /= 4;
+
+    //
+    // Read each word in turn.
+    //
+    while(ui32Count)
+    {
+        //
+        // Read the next word through the autoincrementing register.
+        //
+        *pui32Data = HWREG(EEPROM_EERDWRINC);
+
+        //
+        // Move on to the next word.
+        //
+        pui32Data++;
+        ui32Count--;
+
+        //
+        // Do we need to move to the next block?  This is the case if the
+        // offset register has just wrapped back to 0.  Note that we only
+        // write the block register if we have more data to read.  If this
+        // register is written, the hardware expects a read or write operation
+        // next.  If a mass erase is requested instead, the mass erase will
+        // fail.
+        //
+        if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0))
+        {
+            HWREG(EEPROM_EEBLOCK) += 1;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes data to the EEPROM.
+//!
+//! \param pui32Data points to the first word of data to write to the EEPROM.
+//! \param ui32Address defines the byte address within the EEPROM that the data
+//! is to be written to.  This value must be a multiple of 4.
+//! \param ui32Count defines the number of bytes of data that is to be written.
+//! This value must be a multiple of 4.
+//!
+//! This function may be called to write data into the EEPROM at a given
+//! word-aligned address.  The call is synchronous and returns only after
+//! all data has been written or an error occurs.
+//!
+//! \return Returns 0 on success or non-zero values on failure.  Failure codes
+//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM,
+//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING.
+//
+//*****************************************************************************
+uint32_t
+EEPROMProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count)
+{
+    uint32_t ui32Status;
+
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(pui32Data);
+    ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT((ui32Address + ui32Count) <=
+           SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT((ui32Address & 3) == 0);
+    ASSERT((ui32Count & 3) == 0);
+
+    //
+    // Make sure the EEPROM is idle before we start.
+    //
+    do
+    {
+        //
+        // Read the status.
+        //
+        ui32Status = HWREG(EEPROM_EEDONE);
+    }
+    while(ui32Status & EEPROM_EEDONE_WORKING);
+
+    //
+    // Set the block and offset appropriately to program the first word.
+    //
+    HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address);
+    HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address);
+
+    //
+    // Convert the byte count to a word count.
+    //
+    ui32Count /= 4;
+
+    //
+    // Write each word in turn.
+    //
+    while(ui32Count)
+    {
+        //
+        // This is a workaround for a silicon problem on Blizzard rev A.  We
+        // need to do this before every word write to ensure that we don't
+        // have problems in multi-word writes that span multiple flash sectors.
+        //
+        if(CLASS_IS_TM4C123 && REVISION_IS_A0)
+        {
+            _EEPROMSectorMaskSet(ui32Address);
+        }
+
+        //
+        // Write the next word through the autoincrementing register.
+        //
+        HWREG(EEPROM_EERDWRINC) = *pui32Data;
+
+        //
+        // Wait a few cycles.  In some cases, the WRBUSY bit is not set
+        // immediately and this prevents us from dropping through the polling
+        // loop before the bit is set.
+        //
+        SysCtlDelay(10);
+
+        //
+        // Wait for the write to complete.
+        //
+        do
+        {
+            //
+            // Read the status.
+            //
+            ui32Status = HWREG(EEPROM_EEDONE);
+        }
+        while(ui32Status & EEPROM_EEDONE_WORKING);
+
+        //
+        // Make sure we completed the write without errors.  Note that we
+        // must check this per-word because write permission can be set per
+        // block resulting in only a section of the write not being performed.
+        //
+        if(ui32Status & EEPROM_EEDONE_NOPERM)
+        {
+            //
+            // An error was reported that would prevent the values from
+            // being written correctly.
+            //
+            if(CLASS_IS_TM4C123 && REVISION_IS_A0)
+            {
+                _EEPROMSectorMaskClear();
+            }
+            return(ui32Status);
+        }
+
+        //
+        // Move on to the next word.
+        //
+        pui32Data++;
+        ui32Count--;
+
+        //
+        // Do we need to move to the next block?  This is the case if the
+        // offset register has just wrapped back to 0.  Note that we only
+        // write the block register if we have more data to read.  If this
+        // register is written, the hardware expects a read or write operation
+        // next.  If a mass erase is requested instead, the mass erase will
+        // fail.
+        //
+        if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0))
+        {
+            HWREG(EEPROM_EEBLOCK) += 1;
+        }
+    }
+
+    //
+    // Clear the sector protection bits to prevent possible problems when
+    // programming the main flash array later.
+    //
+    if(CLASS_IS_TM4C123 && REVISION_IS_A0)
+    {
+        _EEPROMSectorMaskClear();
+    }
+
+    //
+    // Return the current status to the caller.
+    //
+    return(HWREG(EEPROM_EEDONE));
+}
+
+//*****************************************************************************
+//
+//! Writes a word to the EEPROM.
+//!
+//! \param ui32Data is the word to write to the EEPROM.
+//! \param ui32Address defines the byte address within the EEPROM to which the
+//! data is to be written.  This value must be a multiple of 4.
+//!
+//! This function is intended to allow EEPROM programming under interrupt
+//! control.  It may be called to start the process of writing a single word of
+//! data into the EEPROM at a given word-aligned address.  The call is
+//! asynchronous and returns immediately without waiting for the write to
+//! complete.  Completion of the operation is signaled by means of an
+//! interrupt from the EEPROM module.  The EEPROM peripheral shares a single
+//! interrupt vector with the flash memory subsystem, \b INT_FLASH.
+//!
+//! \return Returns status and error information in the form of a logical OR
+//! combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM,
+//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE and \b EEPROM_RC_WORKING.  Flags
+//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING are
+//! expected in normal operation and do not indicate an error.
+//
+//*****************************************************************************
+uint32_t
+EEPROMProgramNonBlocking(uint32_t ui32Data, uint32_t ui32Address)
+{
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT((ui32Address & 3) == 0);
+
+    //
+    // This is a workaround for a silicon problem on Blizzard rev A.
+    //
+    if(CLASS_IS_TM4C123 && REVISION_IS_A0)
+    {
+        _EEPROMSectorMaskSet(ui32Address);
+    }
+
+    //
+    // Set the block and offset appropriately to program the desired word.
+    //
+    HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address);
+    HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address);
+
+    //
+    // Write the new word using the auto-incrementing register just in case
+    // the caller wants to write follow-on words using direct register access
+    //
+    HWREG(EEPROM_EERDWRINC) = ui32Data;
+
+    //
+    // Return the current status to the caller.
+    //
+    return(HWREG(EEPROM_EEDONE));
+}
+
+//*****************************************************************************
+//
+//! Erases the EEPROM and returns it to the factory default condition.
+//!
+//! This function completely erases the EEPROM and removes any and
+//! all access protection on its blocks, leaving the device in the factory
+//! default condition.  After this operation, all EEPROM words contain the
+//! value 0xFFFFFFFF and all blocks are accessible for both read and write
+//! operations in all CPU modes.  No passwords are active.
+//!
+//! The function is synchronous and does not return until the erase operation
+//! has completed.
+//!
+//! \return Returns 0 on success or non-zero values on failure.  Failure codes
+//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM,
+//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING.
+//
+//*****************************************************************************
+uint32_t
+EEPROMMassErase(void)
+{
+    //
+    // This is a workaround for a silicon problem on Blizzard rev A.
+    //
+    if(CLASS_IS_TM4C123 && REVISION_IS_A0)
+    {
+        _EEPROMSectorMaskClear();
+    }
+
+    //
+    // Start the mass erase processing
+    //
+    HWREG(EEPROM_EEDBGME) = EEPROM_MASS_ERASE_KEY | EEPROM_EEDBGME_ME;
+
+    //
+    // Wait for completion.
+    //
+    _EEPROMWaitForDone();
+
+    //
+    // Reset the peripheral.  This is required so that all protection
+    // mechanisms and passwords are reset now that the EEPROM data has been
+    // scrubbed.
+    //
+    SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0);
+
+    //
+    // Wait for completion again.
+    //
+    SysCtlDelay(2);
+    _EEPROMWaitForDone();
+
+    //
+    // Pass any error codes back to the caller.
+    //
+    return(HWREG(EEPROM_EEDONE));
+}
+
+//*****************************************************************************
+//
+//! Returns the current protection level for an EEPROM block.
+//!
+//! \param ui32Block is the block number for which the protection level is to
+//! be queried.
+//!
+//! This function returns the current protection settings for a given
+//! EEPROM block.  If block 0 is currently locked, it must be unlocked prior
+//! to calling this function to query the protection setting for other blocks.
+//!
+//! \return Returns one of \b EEPROM_PROT_RW_LRO_URW, \b EEPROM_PROT_NA_LNA_URW
+//! or \b EEPROM_PROT_RO_LNA_URO optionally OR-ed with
+//! \b EEPROM_PROT_SUPERVISOR_ONLY.
+//
+//*****************************************************************************
+uint32_t
+EEPROMBlockProtectGet(uint32_t ui32Block)
+{
+    //
+    // Parameter validity check.
+    //
+    ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+
+    //
+    // Set the current block.
+    //
+    HWREG(EEPROM_EEBLOCK) = ui32Block;
+
+    //
+    // Return the protection flags for this block.
+    //
+    return(HWREG(EEPROM_EEPROT));
+}
+
+//*****************************************************************************
+//
+//! Set the current protection options for an EEPROM block.
+//!
+//! \param ui32Block is the block number for which the protection options are
+//! to be set.
+//! \param ui32Protect consists of one of the values \b EEPROM_PROT_RW_LRO_URW,
+//! \b EEPROM_PROT_NA_LNA_URW or \b EEPROM_PROT_RO_LNA_URO optionally ORed with
+//! \b EEPROM_PROT_SUPERVISOR_ONLY.
+//!
+//! This function sets the protection settings for a given EEPROM block
+//! assuming no protection settings have previously been written.  Note that
+//! protection settings applied to block 0 have special meaning and control
+//! access to the EEPROM peripheral as a whole.  Protection settings applied to
+//! blocks numbered 1 and above are layered above any protection set on block 0
+//! such that the effective protection on each block is the logical OR of the
+//! protection flags set for block 0 and for the target block.  This protocol
+//! allows global protection options to be set for the whole device via block
+//! 0 and more restrictive protection settings to be set on a block-by-block
+//! basis.
+//!
+//! The protection flags indicate access permissions as follow:
+//!
+//! \b EEPROM_PROT_SUPERVISOR_ONLY restricts access to the block to threads
+//! running in supervisor mode.  If clear, both user and supervisor threads
+//! can access the block.
+//!
+//! \b EEPROM_PROT_RW_LRO_URW provides read/write access to the block if no
+//! password is set or if a password is set and the block is unlocked.  If the
+//! block is locked, only read access is permitted.
+//!
+//! \b EEPROM_PROT_NA_LNA_URW provides neither read nor write access unless
+//! a password is set and the block is unlocked.  If the block is unlocked,
+//! both read and write access are permitted.
+//!
+//! \b EEPROM_PROT_RO_LNA_URO provides read access to the block if no password
+//! is set or if a password is set and the block is unlocked.  If the block is
+//! password protected and locked, neither read nor write access is permitted.
+//!
+//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b
+//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b
+//! EEPROM_RC_WORKING to indicate status and error conditions.
+//
+//*****************************************************************************
+uint32_t
+EEPROMBlockProtectSet(uint32_t ui32Block, uint32_t ui32Protect)
+{
+    //
+    // Parameter validity check.
+    //
+    ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+
+    //
+    // Set the current block.
+    //
+    HWREG(EEPROM_EEBLOCK) = ui32Block;
+
+    //
+    // Set the protection options for this block.
+    //
+    HWREG(EEPROM_EEPROT) = ui32Protect;
+
+    //
+    // Wait for the write to complete.
+    //
+    while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING)
+    {
+        //
+        // Still working.
+        //
+    }
+
+    //
+    // Pass any error codes back to the caller.
+    //
+    return(HWREG(EEPROM_EEDONE));
+}
+
+//*****************************************************************************
+//
+//! Sets the password used to protect an EEPROM block.
+//!
+//! \param ui32Block is the EEPROM block number for which the password is to be
+//! set.
+//! \param pui32Password points to an array of uint32_t values comprising
+//! the password to set.  Each element may be any 32-bit value other than
+//! 0xFFFFFFFF.  This array must contain the number of elements given by the
+//! \e ui32Count parameter.
+//! \param ui32Count provides the number of uint32_ts in the \e ui32Password.
+//! Valid values are 1, 2 and 3.
+//!
+//! This function allows the password used to unlock an EEPROM block to be
+//! set.  Valid passwords may be either 32, 64 or 96 bits comprising words
+//! with any value other than 0xFFFFFFFF.  The password may only be set once.
+//! Any further attempts to set the password result in an error.  Once the
+//! password is set, the block remains unlocked until EEPROMBlockLock() is
+//! called for that block or block 0, or a reset occurs.
+//!
+//! If a password is set on block 0, this affects locking of the peripheral as
+//! a whole.  When block 0 is locked, all other EEPROM blocks are inaccessible
+//! until block 0 is unlocked.  Once block 0 is unlocked, other blocks
+//! become accessible according to any passwords set on those blocks and the
+//! protection set for that block via a call to EEPROMBlockProtectSet().
+//!
+//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b
+//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b
+//! EEPROM_RC_WORKING to indicate status and error conditions.
+//
+//*****************************************************************************
+uint32_t
+EEPROMBlockPasswordSet(uint32_t ui32Block, uint32_t *pui32Password,
+                       uint32_t ui32Count)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(pui32Password);
+    ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT(ui32Count <= 3);
+
+    //
+    // Set the block number whose password we are about to write.
+    //
+    HWREG(EEPROM_EEBLOCK) = ui32Block;
+
+    //
+    // Start with the first password word.
+    //
+    ui32Reg = EEPROM_EEPASS0;
+
+    //
+    // Write the password.
+    //
+    while(ui32Count)
+    {
+        //
+        // Start the process of writing the password.
+        //
+        HWREG(ui32Reg) = *pui32Password;
+
+        //
+        // Update values in preparation for writing the next word.
+        //
+        pui32Password++;
+        ui32Reg += 4;
+        ui32Count--;
+
+        //
+        // Wait for the last word write to complete or an error to be reported.
+        //
+        while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING)
+        {
+            //
+            // Still working.
+            //
+        }
+    }
+
+    //
+    // Return the final write status.
+    //
+    return(HWREG(EEPROM_EEDONE));
+}
+
+//*****************************************************************************
+//
+//! Locks a password-protected EEPROM block.
+//!
+//! \param ui32Block is the EEPROM block number which is to be locked.
+//!
+//! This function locks an EEPROM block that has previously been protected by
+//! writing a password.  Access to the block once it is locked is determined
+//! by the protection settings applied via a previous call to the
+//! EEPROMBlockProtectSet() function.  If no password has previously been set
+//! for the block, this function has no effect.
+//!
+//! Locking block 0 has the effect of making all other blocks in the EEPROM
+//! inaccessible.
+//!
+//! \return Returns the lock state for the block on exit, 1 if unlocked (as
+//! would be the case if no password was set) or 0 if locked.
+//!
+//*****************************************************************************
+uint32_t
+EEPROMBlockLock(uint32_t ui32Block)
+{
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+
+    //
+    // Select the block we are going to lock.
+    //
+    HWREG(EEPROM_EEBLOCK) = ui32Block;
+
+    //
+    // Lock the block.
+    //
+    HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF;
+
+    //
+    // Return the current lock state.
+    //
+    return(HWREG(EEPROM_EEUNLOCK));
+}
+
+//*****************************************************************************
+//
+//! Unlocks a password-protected EEPROM block.
+//!
+//! \param ui32Block is the EEPROM block number which is to be unlocked.
+//! \param pui32Password points to an array of uint32_t values containing
+//! the password for the block.  Each element must match the password
+//! originally set via a call to EEPROMBlockPasswordSet().
+//! \param ui32Count provides the number of elements in the \e pui32Password
+//! array and must match the value originally passed to
+//! EEPROMBlockPasswordSet().  Valid values are 1, 2 and 3.
+//!
+//! This function unlocks an EEPROM block that has previously been protected by
+//! writing a password.  Access to the block once it is unlocked is determined
+//! by the protection settings applied via a previous call to the
+//! EEPROMBlockProtectSet() function.
+//!
+//! To successfully unlock an EEPROM block, the password provided must match
+//! the password provided on the original call to EEPROMBlockPasswordSet().  If
+//! an incorrect password is provided, the block remains locked.
+//!
+//! Unlocking block 0 has the effect of making all other blocks in the device
+//! accessible according to their own access protection settings.  When block
+//! 0 is locked, all other EEPROM blocks are inaccessible.
+//!
+//! \return Returns the lock state for the block on exit, 1 if unlocked or 0 if
+//! locked.
+//!
+//*****************************************************************************
+uint32_t
+EEPROMBlockUnlock(uint32_t ui32Block, uint32_t *pui32Password,
+                  uint32_t ui32Count)
+{
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(pui32Password);
+    ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+    ASSERT(ui32Count <= 3);
+
+    //
+    // Set the block that we are trying to unlock.
+    //
+    HWREG(EEPROM_EEBLOCK) = ui32Block;
+
+    //
+    // Write the unlock register with 0xFFFFFFFF to reset the unlock
+    // sequence just in case a short password was previously used to try to
+    // unlock the block.
+    //
+    HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF;
+
+    //
+    // We need to write the password words in the opposite order when unlocking
+    // compared to locking so start at the end of the array.
+    //
+    pui32Password += (ui32Count - 1);
+
+    //
+    // Write the supplied password to unlock the block.
+    //
+    while(ui32Count)
+    {
+        HWREG(EEPROM_EEUNLOCK) = *pui32Password--;
+        ui32Count--;
+    }
+
+    //
+    // Let the caller know if their password worked.
+    //
+    return(HWREG(EEPROM_EEUNLOCK));
+}
+
+//*****************************************************************************
+//
+//! Hides an EEPROM block until the next reset.
+//!
+//! \param ui32Block is the EEPROM block number which is to be hidden.
+//!
+//! This function hides an EEPROM block other than block 0.  Once hidden, a
+//! block is completely inaccessible until the next reset.  This mechanism
+//! allows initialization code to have access to data which is to be hidden
+//! from the rest of the application.  Unlike applications using passwords, an
+//! application making using of block hiding need not contain any embedded
+//! passwords which could be found through disassembly.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+EEPROMBlockHide(uint32_t ui32Block)
+{
+    //
+    // Check parameters in a debug build.
+    //
+    ASSERT(!ui32Block);
+    ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE)));
+
+    //
+    // Hide the requested block.
+    //
+    HWREG(EEPROM_EEHIDE) = (1 << ui32Block);
+}
+
+//*****************************************************************************
+//
+//! Enables the EEPROM interrupt.
+//!
+//! \param ui32IntFlags indicates which EEPROM interrupt source to enable.
+//! This must be \b EEPROM_INT_PROGRAM currently.
+//!
+//! This function enables the EEPROM interrupt.  When enabled, an interrupt
+//! is generated when any EEPROM write or erase operation completes.  The
+//! EEPROM peripheral shares a single interrupt vector with the flash memory
+//! subsystem, \b INT_FLASH.  This function is provided as a convenience but
+//! the EEPROM interrupt can also be enabled using a call to FlashIntEnable()
+//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+EEPROMIntEnable(uint32_t ui32IntFlags)
+{
+    //
+    // Look for valid interrupt sources.
+    //
+    ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM);
+
+    //
+    // Enable interrupts from the EEPROM module.
+    //
+    HWREG(EEPROM_EEINT) |= EEPROM_EEINT_INT;
+
+    //
+    // Enable the EEPROM interrupt in the flash controller module.
+    //
+    HWREG(FLASH_FCIM) |= FLASH_FCRIS_ERIS;
+}
+
+//*****************************************************************************
+//
+//! Disables the EEPROM interrupt.
+//!
+//! \param ui32IntFlags indicates which EEPROM interrupt source to disable.
+//! This must be \b EEPROM_INT_PROGRAM currently.
+//!
+//! This function disables the EEPROM interrupt and prevents calls to the
+//! interrupt vector when any EEPROM write or erase operation completes.  The
+//! EEPROM peripheral shares a single interrupt vector with the flash memory
+//! subsystem, \b INT_FLASH.  This function is provided as a convenience but
+//! the EEPROM interrupt can also be disabled using a call to FlashIntDisable()
+//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+EEPROMIntDisable(uint32_t ui32IntFlags)
+{
+    //
+    // Look for valid interrupt sources.
+    //
+    ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM);
+
+    //
+    // Disable the EEPROM interrupt in the flash controller module.
+    //
+    HWREG(FLASH_FCIM) &= ~FLASH_FCIM_EMASK;
+
+    //
+    // Disable interrupts from the EEPROM module.
+    //
+    HWREG(EEPROM_EEINT) &= ~EEPROM_EEINT_INT;
+}
+
+//*****************************************************************************
+//
+//! Reports the state of the EEPROM interrupt.
+//!
+//! \param bMasked determines whether the masked or unmasked state of the
+//! interrupt is to be returned.  If bMasked is \b true, the masked state is
+//! returned, otherwise the unmasked state is returned.
+//!
+//! This function allows an application to query the state of the EEPROM
+//! interrupt.  If active, the interrupt may be cleared by calling
+//! EEPROMIntClear().
+//!
+//! \return Returns \b EEPROM_INT_PROGRAM if an interrupt is being signaled or
+//! 0 otherwise.
+//
+//*****************************************************************************
+uint32_t
+EEPROMIntStatus(bool bMasked)
+{
+    if(bMasked)
+    {
+        //
+        // If asked for the masked interrupt status, we check to see if the
+        // relevant interrupt is pending in the flash controller then return
+        // the appropriate EEPROM flag if it is.
+        //
+        return((HWREG(FLASH_FCMISC) & FLASH_FCMISC_EMISC) ?
+               EEPROM_INT_PROGRAM : 0);
+    }
+    else
+    {
+        //
+        // If asked for the unmasked interrupt status, infer that an interrupt
+        // is pending if the WORKING bit of the EEDONE register is clear.  The
+        // actual interrupt fires on the high to low transition of this bit
+        // but we don't have access to an unmasked interrupt status for the
+        // EEPROM because it's handled via the flash controller so we have to
+        // make do with this instead.
+        //
+        return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ?
+               0 : EEPROM_INT_PROGRAM);
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the EEPROM interrupt.
+//!
+//! \param ui32IntFlags indicates which interrupt sources to clear.  Currently,
+//! the only valid value is \b EEPROM_INT_PROGRAM.
+//!
+//! This function allows an application to clear the EEPROM interrupt.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+EEPROMIntClear(uint32_t ui32IntFlags)
+{
+    //
+    // Clear the flash interrupt.
+    //
+    HWREG(FLASH_FCMISC) = FLASH_FCMISC_EMISC;
+
+    //
+    // Clear the sector protection bits to prevent possible problems when
+    // programming the main flash array later.
+    //
+    if(CLASS_IS_TM4C123 && REVISION_IS_A0)
+    {
+        _EEPROMSectorMaskClear();
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns status on the last EEPROM program or erase operation.
+//!
+//! This function returns the current status of the last program or erase
+//! operation performed by the EEPROM.  It is intended to provide error
+//! information to applications programming or setting EEPROM protection
+//! options under interrupt control.
+//!
+//! \return Returns 0 if the last program or erase operation completed without
+//! any errors.  If an operation is ongoing or an error occurred, the return
+//! value is a logical OR combination of \b EEPROM_RC_WRBUSY, \b
+//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b
+//! EEPROM_RC_WORKING.
+//!
+//*****************************************************************************
+uint32_t
+EEPROMStatusGet(void)
+{
+    return(HWREG(EEPROM_EEDONE));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/eeprom.h b/bsp/tm4c129x/libraries/driverlib/eeprom.h
new file mode 100644
index 0000000000..3ad36d3333
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/eeprom.h
@@ -0,0 +1,284 @@
+//*****************************************************************************
+//
+// eeprom.h - Prototypes for the EEPROM driver.
+//
+// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_EEPROM_H__
+#define __DRIVERLIB_EEPROM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup eeprom_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Values returned by EEPROMInit.
+//
+//*****************************************************************************
+
+//
+//! This value may be returned from a call to EEPROMInit().  It indicates that
+//! no previous write operations were interrupted by a reset event and that the
+//! EEPROM peripheral is ready for use.
+//
+#define EEPROM_INIT_OK      0
+
+//
+//! This value may be returned from a call to EEPROMInit().  It indicates that
+//! a previous data or protection write operation was interrupted by a reset
+//! event and that the EEPROM peripheral was unable to clean up after the
+//! problem.  This situation may be resolved with another reset or may be fatal
+//! depending upon the cause of the problem.  For example, if the voltage to
+//! the part is unstable, retrying once the voltage has stabilized may clear
+//! the error.
+//
+#define EEPROM_INIT_ERROR   2
+
+//*****************************************************************************
+//
+// Error indicators returned by various EEPROM API calls.  These will be ORed
+// together into the final return code.
+//
+//*****************************************************************************
+
+//
+//! This return code bit indicates that an attempt was made to read from
+//! the EEPROM while a write operation was in progress.
+//
+#define EEPROM_RC_WRBUSY            0x00000020
+
+//
+//! This return code bit indicates that an attempt was made to write a
+//! value but the destination permissions disallow write operations.  This
+//! may be due to the destination block being locked, access protection set
+//! to prohibit writes or an attempt to write a password when one is already
+//! written.
+//
+#define EEPROM_RC_NOPERM            0x00000010
+
+//
+//! This return code bit indicates that the EEPROM programming state machine
+//! is currently copying to or from the internal copy buffer to make room for
+//! a newly written value.  It is provided as a status indicator and does not
+//! indicate an error.
+//
+#define EEPROM_RC_WKCOPY            0x00000008
+
+//
+//! This return code bit indicates that the EEPROM programming state machine
+//! is currently erasing the internal copy buffer.  It is provided as a
+//! status indicator and does not indicate an error.
+//
+#define EEPROM_RC_WKERASE           0x00000004
+
+//
+//! This return code bit indicates that the EEPROM programming state machine
+//! is currently working.  No new write operations should be attempted until
+//! this bit is clear.
+//
+#define EEPROM_RC_WORKING           0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect
+// parameter, and returned by EEPROMBlockProtectGet().
+//
+//*****************************************************************************
+
+//
+//! This bit may be ORed with the protection option passed to
+//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet().  It
+//! restricts EEPROM access to threads running in supervisor mode and prevents
+//! access to an EEPROM block when the CPU is in user mode.
+//
+#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008
+
+//
+//! This value may be passed to EEPROMBlockProtectSet() or returned from
+//! EEPROMBlockProtectGet().  It indicates that the block should offer
+//! read/write access when no password is set or when a password is set and
+//! the block is unlocked, and read-only access when a password is set but
+//! the block is locked.
+//
+#define EEPROM_PROT_RW_LRO_URW      0x00000000
+
+//
+//! This value may be passed to EEPROMBlockProtectSet() or returned from
+//! EEPROMBlockProtectGet().  It indicates that the block should offer neither
+//! read nor write access unless it is protected by a password and unlocked.
+//
+#define EEPROM_PROT_NA_LNA_URW      0x00000001
+
+//
+//! This value may be passed to EEPROMBlockProtectSet() or returned from
+//! EEPROMBlockProtectGet().  It indicates that the block should offer
+//! read-only access when no password is set or when a password is set and the
+//! block is unlocked.  When a password is set and the block is locked, neither
+//! read nor write access is permitted.
+//
+#define EEPROM_PROT_RO_LNA_URO      0x00000002
+
+//*****************************************************************************
+//
+//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is
+//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being
+//! signaled.
+//
+//*****************************************************************************
+#define EEPROM_INT_PROGRAM          0x00000004
+
+//*****************************************************************************
+//
+//! Returns the EEPROM block number containing a given offset address.
+//!
+//! \param ui32Addr is the linear, byte address of the EEPROM location whose
+//! block number is to be returned.  This is a zero-based offset from the start
+//! of the EEPROM storage.
+//!
+//! This macro may be used to translate an EEPROM address offset into a
+//! block number suitable for use in any of the driver's block protection
+//! functions.  The address provided is expressed as a byte offset from the
+//! base of the EEPROM.
+//!
+//! \return Returns the zero-based block number which contains the passed
+//! address.
+//
+//*****************************************************************************
+#define EEPROMBlockFromAddr(ui32Addr) ((ui32Addr) >> 6)
+
+//*****************************************************************************
+//
+//! Returns the offset address of the first word in an EEPROM block.
+//!
+//! \param ui32Block is the index of the EEPROM block whose first word address
+//! is to be returned.
+//!
+//! This macro may be used to determine the address of the first word in a
+//! given EEPROM block.  The address returned is expressed as a byte offset
+//! from the base of EEPROM storage.
+//!
+//! \return Returns the address of the first word in the given EEPROM block.
+//
+//*****************************************************************************
+#define EEPROMAddrFromBlock(ui32Block) ((ui32Block) << 6)
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern uint32_t EEPROMInit(void);
+extern uint32_t EEPROMSizeGet(void);
+extern uint32_t EEPROMBlockCountGet(void);
+extern void EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address,
+                       uint32_t ui32Count);
+extern uint32_t EEPROMProgram(uint32_t *pui32Data,
+                              uint32_t ui32Address,
+                              uint32_t ui32Count);
+extern uint32_t EEPROMProgramNonBlocking(uint32_t ui32Data,
+                                         uint32_t ui32Address);
+extern uint32_t EEPROMStatusGet(void);
+extern uint32_t EEPROMMassErase(void);
+extern uint32_t EEPROMBlockProtectGet(uint32_t ui32Block);
+extern uint32_t EEPROMBlockProtectSet(uint32_t ui32Block,
+                                      uint32_t ui32Protect);
+extern uint32_t EEPROMBlockPasswordSet(uint32_t ui32Block,
+                                       uint32_t *pui32Password,
+                                       uint32_t ui32Count);
+extern uint32_t EEPROMBlockLock(uint32_t ui32Block);
+extern uint32_t EEPROMBlockUnlock(uint32_t ui32Block,
+                                  uint32_t *pui32Password,
+                                  uint32_t ui32Count);
+extern void EEPROMBlockHide(uint32_t ui32Block);
+extern void EEPROMIntEnable(uint32_t ui32IntFlags);
+extern void EEPROMIntDisable(uint32_t ui32IntFlags);
+extern uint32_t EEPROMIntStatus(bool bMasked);
+extern void EEPROMIntClear(uint32_t ui32IntFlags);
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The following definitions appeared in previous revisions of this file
+// but have been deprecated and should not be used by applications.
+//
+//*****************************************************************************
+
+//
+// This value used to be one of those which could be returned from a call to
+// EEPROMInit().  It transpires that it is was incorrect and has been removed
+// after EEPROMInit() was reworked for TivaWare 2.1.
+//
+#define EEPROM_INIT_RETRY   1
+
+//
+// This return code is not available from any Tiva part and has been removed.
+//
+#define EEPROM_RC_INVPL             0x00000100
+
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_EEPROM_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/emac.c b/bsp/tm4c129x/libraries/driverlib/emac.c
new file mode 100644
index 0000000000..dcedfdf657
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/emac.c
@@ -0,0 +1,4689 @@
+//*****************************************************************************
+//
+// emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class
+//          Tiva devices.
+//
+// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup emac_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_emac.h"
+#include "driverlib/debug.h"
+#include "driverlib/emac.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sw_crc.h"
+
+//*****************************************************************************
+//
+// Combined defines used in parameter validity checks.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Combined valid configuration flags.
+//
+//*****************************************************************************
+#define VALID_CONFIG_FLAGS      (EMAC_CONFIG_USE_MACADDR1 |                   \
+                                 EMAC_CONFIG_SA_INSERT |                      \
+                                 EMAC_CONFIG_SA_REPLACE |                     \
+                                 EMAC_CONFIG_2K_PACKETS |                     \
+                                 EMAC_CONFIG_STRIP_CRC |                      \
+                                 EMAC_CONFIG_JABBER_DISABLE |                 \
+                                 EMAC_CONFIG_JUMBO_ENABLE |                   \
+                                 EMAC_CONFIG_IF_GAP_MASK |                    \
+                                 EMAC_CONFIG_CS_DISABLE |                     \
+                                 EMAC_CONFIG_100MBPS |                        \
+                                 EMAC_CONFIG_RX_OWN_DISABLE |                 \
+                                 EMAC_CONFIG_LOOPBACK |                       \
+                                 EMAC_CONFIG_FULL_DUPLEX |                    \
+                                 EMAC_CONFIG_CHECKSUM_OFFLOAD |               \
+                                 EMAC_CONFIG_RETRY_DISABLE |                  \
+                                 EMAC_CONFIG_AUTO_CRC_STRIPPING |             \
+                                 EMAC_CONFIG_BO_MASK |                        \
+                                 EMAC_CONFIG_DEFERRAL_CHK_ENABLE |            \
+                                 EMAC_CONFIG_PREAMBLE_MASK)
+
+//*****************************************************************************
+//
+// Combined valid frame filter flags.
+//
+//*****************************************************************************
+#define VALID_FRMFILTER_FLAGS   (EMAC_FRMFILTER_RX_ALL |                      \
+                                 EMAC_FRMFILTER_VLAN |                        \
+                                 EMAC_FRMFILTER_HASH_AND_PERFECT |            \
+                                 EMAC_FRMFILTER_SADDR |                       \
+                                 EMAC_FRMFILTER_INV_SADDR |                   \
+                                 EMAC_FRMFILTER_PASS_NO_PAUSE |               \
+                                 EMAC_FRMFILTER_PASS_ALL_CTRL |               \
+                                 EMAC_FRMFILTER_PASS_ADDR_CTRL |              \
+                                 EMAC_FRMFILTER_BROADCAST |                   \
+                                 EMAC_FRMFILTER_PASS_MULTICAST |              \
+                                 EMAC_FRMFILTER_INV_DADDR |                   \
+                                 EMAC_FRMFILTER_HASH_MULTICAST |              \
+                                 EMAC_FRMFILTER_HASH_UNICAST |                \
+                                 EMAC_FRMFILTER_PROMISCUOUS)
+
+//*****************************************************************************
+//
+// Combined valid maskable interrupts.
+//
+//*****************************************************************************
+#define EMAC_MASKABLE_INTS      (EMAC_INT_EARLY_RECEIVE |                     \
+                                 EMAC_INT_BUS_ERROR |                         \
+                                 EMAC_INT_EARLY_TRANSMIT |                    \
+                                 EMAC_INT_RX_WATCHDOG |                       \
+                                 EMAC_INT_RX_STOPPED |                        \
+                                 EMAC_INT_RX_NO_BUFFER |                      \
+                                 EMAC_INT_RECEIVE |                           \
+                                 EMAC_INT_TX_UNDERFLOW |                      \
+                                 EMAC_INT_RX_OVERFLOW |                       \
+                                 EMAC_INT_TX_JABBER |                         \
+                                 EMAC_INT_TX_NO_BUFFER |                      \
+                                 EMAC_INT_TX_STOPPED |                        \
+                                 EMAC_INT_TRANSMIT |                          \
+                                 EMAC_INT_NORMAL_INT |                        \
+                                 EMAC_INT_ABNORMAL_INT |                      \
+                                 EMAC_INT_PHY)
+
+//*****************************************************************************
+//
+// Combined valid normal interrupts.
+//
+//*****************************************************************************
+#define EMAC_NORMAL_INTS        (EMAC_INT_TRANSMIT |                          \
+                                 EMAC_INT_RECEIVE |                           \
+                                 EMAC_INT_EARLY_RECEIVE |                     \
+                                 EMAC_INT_TX_NO_BUFFER)
+
+//*****************************************************************************
+//
+// Combined valid abnormal interrupts.
+//
+//*****************************************************************************
+#define EMAC_ABNORMAL_INTS      (EMAC_INT_TX_STOPPED |                        \
+                                 EMAC_INT_TX_JABBER |                         \
+                                 EMAC_INT_RX_OVERFLOW |                       \
+                                 EMAC_INT_TX_UNDERFLOW |                      \
+                                 EMAC_INT_RX_NO_BUFFER |                      \
+                                 EMAC_INT_RX_STOPPED |                        \
+                                 EMAC_INT_RX_WATCHDOG |                       \
+                                 EMAC_INT_EARLY_TRANSMIT |                    \
+                                 EMAC_INT_BUS_ERROR)
+
+//*****************************************************************************
+//
+// Interrupt sources reported via the DMARIS register but which are not
+// masked (or enabled) via the DMAIM register.
+//
+//*****************************************************************************
+#define EMAC_NON_MASKED_INTS    (EMAC_DMARIS_TT |                             \
+                                 EMAC_DMARIS_PMT |                            \
+                                 EMAC_DMARIS_MMC)
+
+//*****************************************************************************
+//
+// The number of MAC addresses the module can store for filtering purposes.
+//
+//*****************************************************************************
+#define NUM_MAC_ADDR            4
+
+//*****************************************************************************
+//
+// Macros aiding access to the MAC address registers.
+//
+//*****************************************************************************
+#define MAC_ADDR_OFFSET         (EMAC_O_ADDR1L - EMAC_O_ADDR0L)
+#define EMAC_O_ADDRL(n)         (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n)))
+#define EMAC_O_ADDRH(n)         (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n)))
+
+//*****************************************************************************
+//
+// A structure used to help in choosing the correct clock divisor for the MII
+// based on the current system clock rate.
+//
+//*****************************************************************************
+static const struct
+{
+    uint32_t ui32SysClockMax;
+    uint32_t ui32Divisor;
+}
+g_pi16MIIClockDiv[] =
+{
+    { 64000000, EMAC_MIIADDR_CR_35_60 },
+    { 104000000, EMAC_MIIADDR_CR_60_100 },
+    { 150000000, EMAC_MIIADDR_CR_100_150 }
+};
+
+//*****************************************************************************
+//
+// The number of clock divisors in the above table.
+//
+//*****************************************************************************
+#define NUM_CLOCK_DIVISORS      (sizeof(g_pi16MIIClockDiv) /                  \
+                                 sizeof(g_pi16MIIClockDiv[0]))
+
+//*****************************************************************************
+//
+//! Initializes the Ethernet MAC and sets bus-related DMA parameters.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//! \param ui32SysClk is the current system clock frequency in Hertz.
+//! \param ui32BusConfig defines the bus operating mode for the Ethernet MAC
+//! DMA controller.
+//! \param ui32RxBurst is the maximum receive burst size in words.
+//! \param ui32TxBurst is the maximum transmit burst size in words.
+//! \param ui32DescSkipSize is the number of 32-bit words to skip between
+//! two unchained DMA descriptors.  Values in the range 0 to 31 are valid.
+//!
+//! This function sets bus-related parameters for the Ethernet MAC DMA
+//! engines.  It must be called after EMACPHYConfigSet() and called again
+//! after any subsequent call to EMACPHYConfigSet().
+//!
+//! The \e ui32BusConfig parameter is the logical OR of various fields.  The
+//! first sets the DMA channel priority weight:
+//!
+//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_1
+//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_2
+//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_3
+//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_4
+//!
+//! The second field sets the receive and transmit priorities used when
+//! arbitrating between the Rx and Tx DMA.  The priorities are Rx:Tx unless
+//! \b EMAC_BCONFIG_TX_PRIORITY is also specified, in which case they become
+//! Tx:Rx.  The priority provided here is ignored if
+//! \b EMAC_BCONFIG_PRIORITY_FIXED is specified.
+//!
+//! - \b EMAC_BCONFIG_PRIORITY_1_1
+//! - \b EMAC_BCONFIG_PRIORITY_2_1
+//! - \b EMAC_BCONFIG_PRIORITY_3_1
+//! - \b EMAC_BCONFIG_PRIORITY_4_1
+//!
+//! The following additional flags may also be defined:
+//!
+//! - \b EMAC_BCONFIG_TX_PRIORITY indicates that the transmit DMA should be
+//! higher priority in all arbitration for the system-side bus.  If this is not
+//! defined, the receive DMA has higher priority.
+//! - \b EMAC_BCONFIG_ADDR_ALIGNED works in tandem with
+//! \b EMAC_BCONFIG_FIXED_BURST to control address alignment of AHB bursts.
+//! When both flags are specified, all bursts are aligned to the start address
+//! least significant bits.  If \b EMAC_BCONFIG_FIXED_BURST is not specified,
+//! the first burst is unaligned but subsequent bursts are aligned to the
+//! address.
+//! - \b EMAC_BCONFIG_ALT_DESCRIPTORS indicates that the DMA engine should
+//! use the alternate descriptor format as defined in type
+//! \b tEMACDMADescriptor.  If absent, the basic descriptor type is used.
+//! Alternate descriptors are required if using IEEE 1588-2008 advanced
+//! timestamping, VLAN or TCP/UDP/ICMP CRC insertion features.  Note that,
+//! for clarity, emac.h does not contain type definitions for the basic
+//! descriptor type.  Please see the part datasheet for information on basic
+//! descriptor structures.
+//! - \b EMAC_BCONFIG_PRIORITY_FIXED indicates that a fixed priority scheme
+//! should be employed when arbitrating between the transmit and receive DMA
+//! for system-side bus access.  In this case, the receive channel always has
+//! priority unless \b EMAC_BCONFIG_TX_PRIORITY is set, in which case the
+//! transmit channel has priority.  If \b EMAC_BCONFIG_PRIORITY_FIXED is not
+//! specified, a weighted round-robin arbitration scheme is used with the
+//! weighting defined using \b EMAC_BCONFIG_PRIORITY_1_1,
+//! \b EMAC_BCONFIG_PRIORITY_2_1, \b EMAC_BCONFIG_PRIORITY_3_1 or
+//! \b EMAC_BCONFIG_PRIORITY_4_1, and \b EMAC_BCONFIG_TX_PRIORITY.
+//! - \b EMAC_BCONFIG_FIXED_BURST indicates that fixed burst transfers should
+//! be used.
+//! - \b EMAC_BCONFIG_MIXED_BURST indicates that the DMA engine should use
+//! mixed burst types depending on the length of data to be transferred
+//! across the system bus.
+//!
+//! The \e ui32RxBurst and \e ui32TxBurst parameters indicate the maximum
+//! number of words that the relevant DMA should transfer in a single
+//! transaction.  Valid values are 1, 2, 4, 8, 16 and 32.  Any other value
+//! results in undefined behavior.
+//!
+//! The \e ui32DescSkipSize parameter is used when the descriptor lists are
+//! using ring mode (where descriptors are contiguous in memory with the last
+//! descriptor marked with the \b END_OF_RING flag) rather than chained mode
+//! (where each descriptor includes a field that points to the next descriptor
+//! in the list).  In ring mode, the hardware uses the \e ui32DescSkipSize to
+//! skip past any application-defined fields after the end of the hardware-
+//! defined descriptor fields.  The parameter value indicates the number of 
+//! 32-bit words to skip after the last field of the hardware-defined 
+//! descriptor to get to the first field of the next descriptor.  When using 
+//! arrays of either the \b tEMACDMADescriptor or \b tEMACAltDMADescriptor 
+//! types defined for this driver, \e ui32DescSkipSize must be set to 1 to skip
+//!  the \e pvNext pointer added to the end of each of these structures.  
+//! Applications may modify these structure definitions to include their own
+//! application-specific data and modify \e ui32DescSkipSize appropriately if
+//! desired.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig,
+         uint32_t ui32RxBurst, uint32_t ui32TxBurst, uint32_t ui32DescSkipSize)
+{
+    uint32_t ui32Val, ui32Div;
+
+    //
+    // Parameter sanity checks.
+    //
+    ASSERT(ui32DescSkipSize < 32);
+    ASSERT(ui32TxBurst < (32 * 8));
+    ASSERT(ui32RxBurst < (32 * 8));
+
+    //
+    // Make sure that the DMA software reset is clear before continuing.
+    //
+    while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR)
+    {
+    }
+
+    //
+    // Set common flags.  Note that this driver assumes we are always using
+    // 8 word descriptors so we need to OR in EMAC_DMABUSMOD_ATDS here.
+    //
+    ui32Val = (ui32BusConfig | (ui32DescSkipSize << EMAC_DMABUSMOD_DSL_S) |
+               EMAC_DMABUSMOD_ATDS);
+
+    //
+    // Do we need to use the 8X burst length multiplier?
+    //
+    if((ui32TxBurst > 32) || (ui32RxBurst > 32))
+    {
+        //
+        // Divide both burst lengths by 8 and set the 8X burst length
+        // multiplier.
+        //
+        ui32Val |= EMAC_DMABUSMOD_8XPBL;
+        ui32TxBurst >>= 3;
+        ui32RxBurst >>= 3;
+
+        //
+        // Sanity check - neither burst length should have become zero.  If
+        // they did, this indicates that the values passed are invalid.
+        //
+        ASSERT(ui32RxBurst);
+        ASSERT(ui32TxBurst);
+    }
+
+    //
+    // Are the receive and transmit burst lengths the same?
+    //
+    if(ui32RxBurst == ui32TxBurst)
+    {
+        //
+        // Yes - set up to use a single burst length.
+        //
+        ui32Val |= (ui32TxBurst << EMAC_DMABUSMOD_PBL_S);
+    }
+    else
+    {
+        //
+        // No - we need to use separate burst lengths for each.
+        //
+        ui32Val |= (EMAC_DMABUSMOD_USP |
+                    (ui32TxBurst << EMAC_DMABUSMOD_PBL_S) |
+                    (ui32RxBurst << EMAC_DMABUSMOD_RPBL_S));
+    }
+
+    //
+    // Finally, write the bus mode register.
+    //
+    HWREG(ui32Base + EMAC_O_DMABUSMOD) = ui32Val;
+
+    //
+    // Default the MII CSR clock divider based on the fastest system clock.
+    //
+    ui32Div = g_pi16MIIClockDiv[NUM_CLOCK_DIVISORS - 1].ui32Divisor;
+
+    //
+    // Find the MII CSR clock divider to use based on the current system clock.
+    //
+    for(ui32Val = 0; ui32Val < NUM_CLOCK_DIVISORS; ui32Val++)
+    {
+        if(ui32SysClk <= g_pi16MIIClockDiv[ui32Val].ui32SysClockMax)
+        {
+            ui32Div = g_pi16MIIClockDiv[ui32Val].ui32Divisor;
+            break;
+        }
+    }
+
+    //
+    // Set the MII CSR clock speed.
+    //
+    HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) &
+                                         ~EMAC_MIIADDR_CR_M) | ui32Div);
+
+    //
+    // Disable all the MMC interrupts as these are enabled by default at reset.
+    //
+    HWREG(ui32Base + EMAC_O_MMCRXIM) = 0xFFFFFFFF;
+    HWREG(ui32Base + EMAC_O_MMCTXIM) = 0xFFFFFFFF;
+}
+
+//*****************************************************************************
+//
+//! Resets the Ethernet MAC.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//!
+//! This function performs a reset of the Ethernet MAC by resetting all logic 
+//! and returning all registers to their default values.  The function returns 
+//! only after the hardware indicates that the reset has completed.
+//!
+//! \note To ensure that the reset completes, the selected PHY clock must be
+//! enabled when this function is called.  If the PHY clock is absent, this
+//! function does not return.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACReset(uint32_t ui32Base)
+{
+    //
+    // Reset the Ethernet MAC.
+    //
+    HWREG(ui32Base + EMAC_O_DMABUSMOD) |= EMAC_DMABUSMOD_SWR;
+
+    //
+    // Wait for the reset to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+//! Selects the Ethernet PHY in use.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//! \param ui32Config selects the PHY in use and, when using the internal
+//! PHY, allows various various PHY parameters to be configured.
+//!
+//! This function must be called prior to EMACInit() and EMACConfigSet() to
+//! select the Ethernet PHY to be used.  If the internal PHY is selected, the
+//! function also allows configuration of various PHY parameters.  Note that
+//! the Ethernet MAC is reset during this function call because parameters used
+//! by this function are latched by the hardware only on a MAC reset.  The call
+//! sequence to select and configure the PHY, therefore, must be as follows:
+//!
+//! \verbatim
+//!     // Enable and reset the MAC.
+//!     SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
+//!     SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
+//!     if(<using internal PHY>)
+//!     {
+//!         // Enable and reset the internal PHY.
+//!         SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
+//!         SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
+//!     }
+//!
+//!     // Ensure the MAC is completed its reset.
+//!     while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
+//!     {
+//!     }
+//!
+//!     // Set the PHY type and configuration options.
+//!     EMACPHYConfigSet(EMAC0_BASE, <config>);
+//!
+//!     // Initialize and configure the MAC.
+//!     EMACInit(EMAC0_BASE, <system clock rate>, <bus config>,
+//!              <Rx burst size>, <Tx burst size>, <desc skip>);
+//!     EMACConfigSet(EMAC0_BASE, <parameters>);
+//! \endverbatim
+//!
+//! The \e ui32Config parameter must specify one of the following values:
+//!
+//! - \b EMAC_PHY_TYPE_INTERNAL selects the internal Ethernet PHY.
+//! - \b EMAC_PHY_TYPE_EXTERNAL_MII selects an external PHY connected via the
+//! MII interface.
+//! - \b EMAC_PHY_TYPE_EXTERNAL_RMII selects an external PHY connected via the
+//! RMII interface.
+//!
+//! If \b EMAC_PHY_TYPE_INTERNAL is selected, the following flags may be ORed
+//! into \e ui32Config to control various PHY features and modes.  These flags 
+//! are ignored if an external PHY is selected.
+//!
+//! - \b EMAC_PHY_INT_NIB_TXERR_DET_DIS disables odd nibble transmit error
+//! detection (sets the default value of PHY register MR10, bit 1).
+//! - \b EMAC_PHY_INT_RX_ER_DURING_IDLE enables receive error detection during
+//! idle  (sets the default value of PHY register MR10, bit 2).
+//! - \b EMAC_PHY_INT_ISOLATE_MII_LLOSS ties the MII outputs low if no link is
+//! established in 100B-T and full duplex modes (sets the default value of PHY
+//! register MR10, bit 3).
+//! - \b EMAC_PHY_INT_LINK_LOSS_RECOVERY enables link loss recovery (sets the
+//! default value of PHY register MR9, bit 7).
+//! - \b EMAC_PHY_INT_TDRRUN enables execution of the TDR procedure after a link
+//! down event (sets the default value of PHY register MR9, bit 8).
+//! - \b EMAC_PHY_INT_LD_ON_RX_ERR_COUNT enables link down if the receiver
+//! error count reaches 32 within a 10-us interval (sets the default value of
+//! PHY register MR11 bit 3).
+//! - \b EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT enables link down if the MTL3 error
+//! count reaches 20 in a 10 us-interval (sets the default value of PHY register
+//! MR11 bit 2).
+//! - \b EMAC_PHY_INT_LD_ON_LOW_SNR enables link down if the low SNR threshold
+//! is crossed 20 times in a 10 us-interval (sets the default value of PHY
+//! register MR11 bit 1).
+//! - \b EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY enables link down if energy detector
+//! indicates Energy Loss (sets the default value of PHY register MR11 bit 0).
+//! - \b EMAC_PHY_INT_POLARITY_SWAP inverts the polarity on both TPTD and TPRD
+//! pairs (sets the default value of PHY register MR11 bit 5).
+//! - \b EMAC_PHY_INT_MDI_SWAP swaps the MDI pairs putting receive on the TPTD
+//! pair and transmit on TPRD (sets the default value of PHY register MR11 bit
+//! 6).
+//! - \b EMAC_PHY_INT_ROBUST_MDIX enables robust auto MDI-X resolution (sets the
+//! default value of PHY register MR9 bit 5).
+//! - \b EMAC_PHY_INT_FAST_MDIX enables fast auto-MDI/MDIX resolution (sets the
+//! default value of PHY register MR9 bit 6).
+//! - \b EMAC_PHY_INT_MDIX_EN enables auto-MDI/MDIX crossover (sets the
+//! default value of PHY register MR9 bit 14).
+//! - \b EMAC_PHY_INT_FAST_RXDV_DETECT enables fast RXDV detection (set the
+//! default value of PHY register MR9 bit 1).
+//! - \b EMAC_PHY_INT_FAST_L_UP_DETECT enables fast link-up time during parallel
+//! detection (sets the default value of PHY register MR10 bit 6)
+//! - \b EMAC_PHY_INT_EXT_FULL_DUPLEX forces full-duplex while working with a
+//! link partner in forced 100B-TX (sets the default value of PHY register
+//! MR10 bit 5).
+//! - \b EMAC_PHY_INT_FAST_AN_80_50_35 enables fast auto-negotiation using
+//! break link, link fail inhibit and wait timers set to 80, 50 and 35
+//! respectively (sets the default value of PHY register MR9 bits [4:2] to
+//! 3b100).
+//! - \b EMAC_PHY_INT_FAST_AN_120_75_50 enables fast auto-negotiation using
+//! break link, link fail inhibit and wait timers set to 120, 75 and 50
+//! respectively (sets the default value of PHY register MR9 bits [4:2] to
+//! 3b101).
+//! - \b EMAC_PHY_INT_FAST_AN_140_150_100 enables fast auto-negotiation using
+//! break link, link fail inhibit and wait timers set to 140, 150 and 100
+//! respectively (sets the default value of PHY register MR9 bits [4:2] to
+//! 3b110).
+//! - \b EMAC_PHY_FORCE_10B_T_HALF_DUPLEX disables auto-negotiation and forces
+//! operation in 10Base-T, half duplex mode (sets the default value of PHY
+//! register MR9 bits [13:11] to 3b000).
+//! - \b EMAC_PHY_FORCE_10B_T_FULL_DUPLEX disables auto-negotiation and forces
+//! operation in 10Base-T, full duplex mode (sets the default value of PHY
+//! register MR9 bits [13:11] to 3b001).
+//! - \b EMAC_PHY_FORCE_100B_T_HALF_DUPLEX disables auto-negotiation and forces
+//! operation in 100Base-T, half duplex mode (sets the default value of PHY
+//! register MR9 bits [13:11] to 3b010).
+//! - \b EMAC_PHY_FORCE_100B_T_FULL_DUPLEX disables auto-negotiation and forces
+//! operation in 100Base-T, full duplex mode (sets the default value of PHY
+//! register MR9 bits [13:11] to 3b011).
+//! - \b EMAC_PHY_AN_10B_T_HALF_DUPLEX enables auto-negotiation and advertises
+//! 10Base-T, half duplex mode (sets the default value of PHY register MR9 bits
+//! [13:11] to 3b100).
+//! - \b EMAC_PHY_AN_10B_T_FULL_DUPLEX enables auto-negotiation and advertises
+//! 10Base-T half or full duplex modes (sets the default value of PHY register
+//! MR9 bits [13:11] to 3b101).
+//! - \b EMAC_PHY_AN_100B_T_HALF_DUPLEX enables auto-negotiation and advertises
+//! 10Base-T half or full duplex, and 100Base-T half duplex modes (sets the
+//! default value of PHY register MR9 bits [13:11] to 3b110).
+//! - \b EMAC_PHY_AN_100B_T_FULL_DUPLEX enables auto-negotiation and advertises
+//! 10Base-T half or full duplex, and 100Base-T half or full duplex modes (sets
+//! the default value of PHY register MR9 bits [13:11] to 3b111).
+//! - \b EMAC_PHY_INT_HOLD prevents the PHY from transmitting energy on the
+//! line.
+//!
+//! As a side effect of this function, the Ethernet MAC is reset so any
+//! previous MAC configuration is lost.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Write the Ethernet PHY configuration to the peripheral configuration
+    // register.
+    //
+    HWREG(ui32Base + EMAC_O_PC) = ui32Config;
+
+    //
+    // If using the internal PHY, reset it to ensure that new configuration is
+    // latched there.
+    //
+    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
+    {
+        SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
+        while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0))
+        {
+            //
+            // Wait for the PHY reset to complete.
+            //
+        }
+
+        //
+        // Delay a bit longer to ensure that the PHY reset has completed.
+        //
+        SysCtlDelay(10000);
+    }
+
+    //
+    // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC
+    // Clock Configuration Register.
+    //
+    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII)
+    {
+        //
+        // Select and enable the external clock from the RMII PHY.
+        //
+        HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN;
+    }
+    else
+    {
+        //
+        // Disable the external clock.
+        //
+        HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN;
+    }
+
+    //
+    // Reset the MAC regardless of whether the PHY connection changed or not.
+    //
+    EMACReset(EMAC0_BASE);
+
+    SysCtlDelay(1000);
+}
+
+//*****************************************************************************
+//
+//! Configures basic Ethernet MAC operation parameters.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//! \param ui32Config provides various flags and values configuring the MAC.
+//! \param ui32ModeFlags provides configuration relating to the transmit and
+//! receive DMA engines.
+//! \param ui32RxMaxFrameSize sets the maximum receive frame size above which
+//! an error is reported.
+//!
+//! This function is called to configure basic operating parameters for the
+//! MAC and its DMA engines.
+//!
+//! The \e ui32Config parameter is the logical OR of various fields and
+//! flags.  The first field determines which MAC address is used during
+//! insertion or replacement for all transmitted frames.  Valid options are
+//!
+//! - \b EMAC_CONFIG_USE_MACADDR1 and
+//! - \b EMAC_CONFIG_USE_MACADDR0
+//!
+//! The interframe gap between transmitted frames is controlled using one of
+//! the following values:
+//!
+//! - \b EMAC_CONFIG_IF_GAP_96BITS
+//! - \b EMAC_CONFIG_IF_GAP_88BITS
+//! - \b EMAC_CONFIG_IF_GAP_80BITS
+//! - \b EMAC_CONFIG_IF_GAP_72BITS
+//! - \b EMAC_CONFIG_IF_GAP_64BITS
+//! - \b EMAC_CONFIG_IF_GAP_56BITS
+//! - \b EMAC_CONFIG_IF_GAP_48BITS
+//! - \b EMAC_CONFIG_IF_GAP_40BITS
+//!
+//! The number of bytes of preamble added to the beginning of every transmitted
+//! frame is selected using one of the following values:
+//!
+//! - \b EMAC_CONFIG_7BYTE_PREAMBLE
+//! - \b EMAC_CONFIG_5BYTE_PREAMBLE
+//! - \b EMAC_CONFIG_3BYTE_PREAMBLE
+//!
+//! The back-off limit determines the range of the random time that the MAC
+//! delays after a collision and before attempting to retransmit a frame.  One
+//! of the following values must be used to select this limit.  In each case,
+//! the retransmission delay in terms of 512 bit time slots, is the lower of 
+//! (2 ** N) and a random number between 0 and the selected backoff-limit.
+//!
+//! - \b EMAC_CONFIG_BO_LIMIT_1024
+//! - \b EMAC_CONFIG_BO_LIMIT_256
+//! - \b EMAC_CONFIG_BO_LIMIT_16
+//! - \b EMAC_CONFIG_BO_LIMIT_2
+//!
+//! Control over insertion or replacement of the source address in all
+//! transmitted frames is provided by using one of the following fields:
+//!
+//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending
+//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1
+//! was specified) to be inserted into all transmitted frames.
+//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with
+//! the selected address in all transmitted frames.
+//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address
+//! insertion or deletion to be controlled by fields in the DMA transmit
+//! descriptor, allowing control on a frame-by-frame basis.
+//!
+//! Whether the interface attempts to operate in full- or half-duplex mode is
+//! controlled by one of the following flags:
+//!
+//! - \b EMAC_CONFIG_FULL_DUPLEX
+//! - \b EMAC_CONFIG_HALF_DUPLEX
+//!
+//! The following additional flags may also be specified:
+//!
+//! - \b EMAC_CONFIG_2K_PACKETS enables IEEE802.3as support for 2K packets.
+//! When specified, the MAC considers all frames up to 2000 bytes in length as
+//! normal packets.  When \b EMAC_CONFIG_JUMBO_ENABLE is not specified, all
+//! frames larger than 2000 bytes are treated as Giant frames.  This flag is
+//! ignored if \b EMAC_CONFIG_JUMBO_ENABLE is specified.
+//! - \b EMAC_CONFIG_STRIP_CRC causes the 4-byte CRC of all Ethernet type
+//! frames to be stripped and dropped before the frame is forwarded to the
+//! application.
+//! - \b EMAC_CONFIG_JABBER_DISABLE disables the jabber timer on the
+//! transmitter and enables frames of up to 16384 bytes to be transmitted.  If
+//! this flag is absent, the MAC does not allow more than 2048 (or 10240 if
+//! \b EMAC_CONFIG_JUMBO_ENABLE is specified) bytes to be sent in any one
+//! frame.
+//! - \b EMAC_CONFIG_JUMBO_ENABLE enables Jumbo Frames, allowing frames of
+//! up to 9018 (or 9022 if using VLAN tagging) to be handled without reporting
+//! giant frame errors.
+//! - \b EMAC_CONFIG_100MBPS forces the MAC to communicate with the PHY using
+//! 100Mbps signaling.  If this option is not specified, the MAC uses 10Mbps 
+//! signaling.  This speed setting is important when using an external RMII 
+//! PHY where the selected rate must match the PHY's setting which may have 
+//! been made as a result of auto-negotiation.  When using the internal PHY 
+//! or an external MII PHY, the signaling rate is controlled by the PHY-
+//! provided transmit and receive clocks.
+//! - \b EMAC_CONFIG_CS_DISABLE disables Carrier Sense during transmission
+//! when operating in half-duplex mode.
+//! - \b EMAC_CONFIG_RX_OWN_DISABLE disables reception of transmitted frames
+//! when operating in half-duplex mode.
+//! - \b EMAC_CONFIG_LOOPBACK enables internal loopback.
+//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD enables IPv4 header checksum checking
+//! and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking.  The results
+//! of the checksum calculations are reported via status fields in the DMA
+//! receive descriptors.
+//! - \b EMAC_CONFIG_RETRY_DISABLE disables retransmission in cases where
+//! half-duplex mode is in use and a collision occurs.  This condition causes 
+//! the current frame to be ignored and a frame abort to be reported in the 
+//! transmit frame status.
+//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING strips the last 4 bytes (frame check
+//! sequence) from all Ether type frames before forwarding the frames to the
+//! application.
+//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE enables transmit deferral checking
+//! in half-duplex mode.  When enabled, the transmitter reports an error if it 
+//! is unable to transmit a frame for more than 24288 bit times (or 155680 
+//! bit times in Jumbo frame mode) due to an active carrier sense signal on
+//! the MII.
+//!
+//! The \e ui32ModeFlags parameter sets operating parameters related to the
+//! internal MAC FIFOs.  It comprises a logical OR of the following fields.
+//! The first selects the transmit FIFO threshold.  Transmission of a frame
+//! begins when this amount of data or a full frame exists in the transmit
+//! FIFO.  This field is ignored if \b EMAC_MODE_TX_STORE_FORWARD is
+//! included.  One of the following must be specified:
+//!
+//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES
+//!
+//! The second field controls the receive FIFO threshold.  DMA transfers of
+//! received data begin either when the receive FIFO contains a full frame
+//! or this number of bytes.  This field is ignored if
+//! \b EMAC_MODE_RX_STORE_FORWARD is included.  One of the following must be
+//! specified:
+//!
+//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES
+//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES
+//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES
+//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES
+//!
+//! The following additional flags may be specified:
+//!
+//! - \b EMAC_MODE_KEEP_BAD_CRC causes frames with TCP/IP checksum errors
+//! to be forwarded to the application if those frames do not have any errors
+//! (including FCS errors) in the Ethernet framing.  In these cases, the frames
+//! have errors only in the payload.  If this flag is not specified, all frames
+//! with any detected error are discarded unless \b EMAC_MODE_RX_ERROR_FRAMES
+//! is also specified.
+//! - \b EMAC_MODE_RX_STORE_FORWARD causes the receive DMA to read frames
+//! from the FIFO only after the complete frame has been written to it.  If
+//! this mode is enabled, the receive threshold is ignored.
+//! - \b EMAC_MODE_RX_FLUSH_DISABLE disables the flushing of received frames
+//! in cases where receive descriptors or buffers are unavailable.
+//! - \b EMAC_MODE_TX_STORE_FORWARD causes the transmitter to start
+//! transmitting a frame only after the whole frame has been written to the
+//! transmit FIFO.  If this mode is enabled, the transmit threshold is ignored.
+//! - \b EMAC_MODE_RX_ERROR_FRAMES causes all frames other than runt error
+//! frames to be forwarded to the receive DMA regardless of any errors detected
+//! in the frames.
+//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES causes undersized frames (frames
+//! shorter than 64 bytes but with no errors) to the application.  If this
+//! option is not selected, all undersized frames are dropped by the receiver
+//! unless it has already started transferring them to the receive FIFO due to
+//! the receive threshold setting.
+//! - \b EMAC_MODE_OPERATE_2ND_FRAME enables the transmit DMA to operate on a
+//! second frame while waiting for the previous frame to be transmitted and
+//! associated status and timestamps to be reported.  If absent, the transmit
+//! DMA works on a single frame at any one time, waiting for that frame to be
+//! transmitted and its status to be received before moving on to the next
+//! frame.
+//!
+//! The \e ui32RxMaxFrameSize parameter may be used to override the default
+//! setting for the maximum number of bytes that can be received in a frame
+//! before that frame is flagged as being in error.  If the parameter is set
+//! to 0, the default hardware settings are applied.  If non-zero, any frame
+//! received which is longer than the \e ui32RxMaxFrameSize, regardless of
+//! whether the MAC is configured for normal or Jumbo frame operation, is
+//! flagged as an error.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags,
+              uint32_t ui32RxMaxFrameSize)
+{
+    //
+    // Parameter sanity check.  Note that we allow TX_ENABLED and RX_ENABLED
+    // here because we'll mask them off before writing the value and this
+    // makes back-to-back EMACConfigGet/EMACConfigSet calls work without the
+    // caller needing to explicitly remove these bits from the parameter.
+    //
+    ASSERT((ui32Config & ~(VALID_CONFIG_FLAGS |  EMAC_CONFIG_TX_ENABLED |
+                           EMAC_CONFIG_RX_ENABLED)) == 0);
+    ASSERT(!ui32RxMaxFrameSize || ((ui32RxMaxFrameSize < 0x4000) &&
+                                   (ui32RxMaxFrameSize > 1522)));
+
+    //
+    // Set the configuration flags as specified.  Note that we unconditionally
+    // OR in the EMAC_CFG_PS bit here since this implementation supports only
+    // MII and RMII interfaces to the PHYs.
+    //
+    HWREG(ui32Base + EMAC_O_CFG) =
+        ((HWREG(ui32Base + EMAC_O_CFG) & ~VALID_CONFIG_FLAGS) | ui32Config |
+         EMAC_CFG_PS);
+
+    //
+    // Set the maximum receive frame size.  If 0 is passed, this implies
+    // that the default maximum frame size should be used so just turn off
+    // the override.
+    //
+    if(ui32RxMaxFrameSize)
+    {
+        HWREG(ui32Base + EMAC_O_WDOGTO) = ui32RxMaxFrameSize | EMAC_WDOGTO_PWE;
+    }
+    else
+    {
+        HWREG(ui32Base + EMAC_O_WDOGTO) &= ~EMAC_WDOGTO_PWE;
+    }
+
+    //
+    // Set the operating mode register.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) = ui32ModeFlags;
+}
+
+//*****************************************************************************
+//
+//! Returns the Ethernet MAC's current basic configuration parameters.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//! \param pui32Config points to storage that is written with Ethernet MAC
+//! configuration.
+//! \param pui32Mode points to storage that is written with Ethernet MAC mode
+//! information.
+//! \param pui32RxMaxFrameSize points to storage that is written with the
+//! maximum receive frame size.
+//!
+//! This function is called to query the basic operating parameters for the
+//! MAC and its DMA engines.
+//!
+//! The \e pui32Config parameter is written with the logical OR of various
+//! fields and flags.  The first field describes which MAC address is used
+//! during insertion or replacement for all transmitted frames.  Valid options
+//! are
+//!
+//! - \b EMAC_CONFIG_USE_MACADDR1
+//! - \b EMAC_CONFIG_USE_MACADDR0
+//!
+//! The interframe gap between transmitted frames is given using one of the
+//! following values:
+//!
+//! - \b EMAC_CONFIG_IF_GAP_96BITS
+//! - \b EMAC_CONFIG_IF_GAP_88BITS
+//! - \b EMAC_CONFIG_IF_GAP_80BITS
+//! - \b EMAC_CONFIG_IF_GAP_72BITS
+//! - \b EMAC_CONFIG_IF_GAP_64BITS
+//! - \b EMAC_CONFIG_IF_GAP_56BITS
+//! - \b EMAC_CONFIG_IF_GAP_48BITS
+//! - \b EMAC_CONFIG_IF_GAP_40BITS
+//!
+//! The number of bytes of preamble added to the beginning of every transmitted
+//! frame is described using one of the following values:
+//!
+//! - \b EMAC_CONFIG_7BYTE_PREAMBLE
+//! - \b EMAC_CONFIG_5BYTE_PREAMBLE
+//! - \b EMAC_CONFIG_3BYTE_PREAMBLE
+//!
+//! The back-off limit determines the range of the random time that the MAC
+//! delays after a collision and before attempting to retransmit a frame.  One
+//! of the following values provides the currently selected limit.  In each
+//! case the retransmission delay in terms of 512 bit time slots, is the
+//! lower of (2 ** N) and a random number between 0 and the reported
+//! backoff-limit.
+//!
+//! - \b EMAC_CONFIG_BO_LIMIT_1024
+//! - \b EMAC_CONFIG_BO_LIMIT_256
+//! - \b EMAC_CONFIG_BO_LIMIT_16
+//! - \b EMAC_CONFIG_BO_LIMIT_2
+//!
+//! Handling of insertion or replacement of the source address in all
+//! transmitted frames is described by one of the following fields:
+//!
+//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending
+//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1
+//! was specified) to be inserted into all transmitted frames.
+//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with
+//! the selected address in all transmitted frames.
+//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address
+//! insertion or deletion to be controlled by fields in the DMA transmit
+//! descriptor, allowing control on a frame-by-frame basis.
+//!
+//! Whether the interface attempts to operate in full- or half-duplex mode is
+//! reported by one of the following flags:
+//!
+//! - \b EMAC_CONFIG_FULL_DUPLEX
+//! - \b EMAC_CONFIG_HALF_DUPLEX
+//!
+//! The following additional flags may also be included:
+//!
+//! - \b EMAC_CONFIG_2K_PACKETS indicates that IEEE802.3as support for 2K
+//! packets is enabled.  When present, the MAC considers all frames up to 2000
+//! bytes in length as normal packets.  When \b EMAC_CONFIG_JUMBO_ENABLE is
+//! not reported, all frames larger than 2000 bytes are treated as Giant
+//! frames.  The value of this flag should be ignored if
+//! \b EMAC_CONFIG_JUMBO_ENABLE is also reported.
+//! - \b EMAC_CONFIG_STRIP_CRC indicates that the 4-byte CRC of all Ethernet
+//! type frames is being stripped and dropped before the frame is forwarded to
+//! the application.
+//! - \b EMAC_CONFIG_JABBER_DISABLE indicates that the the jabber timer on the
+//! transmitter is disabled, allowing frames of up to 16384 bytes to be
+//! transmitted.  If this flag is absent, the MAC does not allow more than 2048
+//! (or 10240 if \b EMAC_CONFIG_JUMBO_ENABLE is reported) bytes to be sent in
+//! any one frame.
+//! - \b EMAC_CONFIG_JUMBO_ENABLE indicates that Jumbo Frames of up to 9018
+//! (or 9022 if using VLAN tagging) are enabled.
+//! - \b EMAC_CONFIG_CS_DISABLE indicates that Carrier Sense is disabled
+//! during transmission when operating in half-duplex mode.
+//! - \b EMAC_CONFIG_100MBPS indicates that the MAC is using 100Mbps
+//! signaling to communicate with the PHY.
+//! - \b EMAC_CONFIG_RX_OWN_DISABLE indicates that reception of transmitted
+//! frames is disabled when operating in half-duplex mode.
+//! - \b EMAC_CONFIG_LOOPBACK indicates that internal loopback is enabled.
+//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD indicates that IPv4 header checksum
+//! checking and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking is
+//! enabled.  The results of the checksum calculations are reported via status
+//! fields in the DMA receive descriptors.
+//! - \b EMAC_CONFIG_RETRY_DISABLE indicates that retransmission is disabled
+//! in cases where half-duplex mode is in use and a collision occurs.  This
+//! condition causes the current frame to be ignored and a frame abort to be 
+//! reported in the transmit frame status.
+//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING indicates that the last 4 bytes
+//! (frame check sequence) from all Ether type frames are being stripped before
+//! frames are forwarded to the application.
+//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE indicates that transmit deferral
+//! checking is disabled in half-duplex mode.  When enabled, the transmitter
+//! reports an error if it is unable to transmit a frame for more than 24288 
+//! bit times (or 155680 bit times in Jumbo frame mode) due to an active
+//! carrier sense signal on the MII.
+//! - \b EMAC_CONFIG_TX_ENABLED indicates that the MAC transmitter is
+//! currently enabled.
+//! - \b EMAC_CONFIG_RX_ENABLED indicates that the MAC receiver is
+//! currently enabled.
+//!
+//! The \e pui32ModeFlags parameter is written with operating parameters
+//! related to the internal MAC FIFOs.  It comprises a logical OR of the
+//! following fields.  The first field reports the transmit FIFO threshold.
+//! Transmission of a frame begins when this amount of data or a full frame
+//! exists in the transmit FIFO.  This field should be ignored if
+//! \b EMAC_MODE_TX_STORE_FORWARD is also reported.  One of the following
+//! values is reported:
+//!
+//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES
+//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES
+//!
+//! The second field reports the receive FIFO threshold.  DMA transfers of
+//! received data begin either when the receive FIFO contains a full frame
+//! or this number of bytes.  This field should be ignored if
+//! \b EMAC_MODE_RX_STORE_FORWARD is included.  One of the following values
+//! is reported:
+//!
+//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES
+//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES
+//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES
+//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES
+//!
+//! The following additional flags may be included:
+//!
+//! - \b EMAC_MODE_KEEP_BAD_CRC indicates that frames with TCP/IP checksum
+//! errors are being forwarded to the application if those frames do not have
+//! any errors (including FCS errors) in the Ethernet framing.  In these cases,
+//! the frames have errors only in the payload.  If this flag is not reported,
+//! all frames with any detected error are discarded unless
+//! \b EMAC_MODE_RX_ERROR_FRAMES is also reported.
+//! - \b EMAC_MODE_RX_STORE_FORWARD indicates that the receive DMA is
+//! configured to read frames from the FIFO only after the complete frame has
+//! been written to it.  If this mode is enabled, the receive threshold is
+//! ignored.
+//! - \b EMAC_MODE_RX_FLUSH_DISABLE indicates that the flushing of received
+//! frames is disabled in cases where receive descriptors or buffers are
+//! unavailable.
+//! - \b EMAC_MODE_TX_STORE_FORWARD indicates that the transmitter is
+//! configured to transmit a frame only after the whole frame has been written
+//! to the transmit FIFO.  If this mode is enabled, the transmit threshold is
+//! ignored.
+//! - \b EMAC_MODE_RX_ERROR_FRAMES indicates that all frames other than runt
+//! error frames are being forwarded to the receive DMA regardless of any
+//! errors detected in the frames.
+//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES indicates that undersized frames
+//! (frames shorter than 64 bytes but with no errors) are being forwarded to
+//! the application.  If this option is not reported, all undersized frames are
+//! dropped by the receiver unless it has already started transferring them to
+//! the receive FIFO due to the receive threshold setting.
+//! - \b EMAC_MODE_OPERATE_2ND_FRAME indicates that the transmit DMA is
+//! configured to operate on a second frame while waiting for the previous
+//! frame to be transmitted and associated status and timestamps to be reported.
+//! If absent, the transmit DMA works on a single frame at any one time,
+//! waiting for that frame to be transmitted and its status to be received
+//! before moving on to the next frame.
+//! - \b EMAC_MODE_TX_DMA_ENABLED indicates that the transmit DMA engine is
+//! currently enabled.
+//! - \b EMAC_MODE_RX_DMA_ENABLED indicates that the receive DMA engine is
+//! currently enabled.
+//!
+//! The \e pui32RxMaxFrameSize is written with the currently configured maximum
+//! receive packet size.  Packets larger than this are flagged as being in
+//! error.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, uint32_t *pui32Mode,
+              uint32_t *pui32RxMaxFrameSize)
+{
+    uint32_t ui32Value;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(pui32Mode);
+    ASSERT(pui32Config);
+    ASSERT(pui32RxMaxFrameSize);
+
+    //
+    // Return the mode information from the operation mode register.
+    //
+    *pui32Mode = HWREG(ui32Base + EMAC_O_DMAOPMODE);
+
+    //
+    // Return the current configuration flags from the EMAC_O_CFG register.
+    //
+    *pui32Config = (HWREG(ui32Base + EMAC_O_CFG) &
+                    (VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED |
+                     EMAC_CONFIG_RX_ENABLED));
+
+    //
+    // Get the receive packet size watchdog value.
+    //
+    ui32Value = HWREG(ui32Base + EMAC_O_WDOGTO);
+    if(ui32Value & EMAC_WDOGTO_PWE)
+    {
+        //
+        // The watchdog is enables so the maximum packet length can be read
+        // from the watchdog timeout register.
+        //
+        *pui32RxMaxFrameSize = ui32Value & EMAC_WDOGTO_WTO_M;
+    }
+    else
+    {
+        //
+        // The maximum packet size override found in the watchdog timer
+        // register is not enabled so the maximum packet size is determined
+        // by whether or not jumbo frame mode is enabled.
+        //
+        if(HWREG(ui32Base + EMAC_O_CFG) & EMAC_CFG_JFEN)
+        {
+            //
+            // Jumbo frames are enabled so the watchdog kicks in at 10240
+            // bytes.
+            //
+            *pui32RxMaxFrameSize = 10240;
+        }
+        else
+        {
+            //
+            // Jumbo frames are not enabled so the watchdog kicks in at
+            // 2048 bytes.
+            //
+            *pui32RxMaxFrameSize = 2048;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the MAC address of the Ethernet controller.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//! \param ui32Index is the zero-based index of the MAC address to set.
+//! \param pui8MACAddr is the pointer to the array of MAC-48 address octets.
+//!
+//! This function programs the IEEE-defined MAC-48 address specified in
+//! \e pui8MACAddr into the Ethernet controller.  This address is used by the
+//! Ethernet controller for hardware-level filtering of incoming Ethernet
+//! packets (when promiscuous mode is not enabled).  Index 0 is used to hold
+//! the local node's MAC address which is inserted into all transmitted
+//! packets.
+//!
+//! The controller may support several Ethernet MAC address slots, each of which
+//! may be programmed independently and used to filter incoming packets.  The
+//! number of MAC addresses that the hardware supports may be queried using a
+//! call to EMACNumAddrGet().  The value of the \e ui32Index parameter must
+//! lie in the range from 0 to (number of MAC addresses - 1) inclusive.
+//!
+//! The MAC-48 address is defined as 6 octets, illustrated by the following
+//! example address.  The numbers are shown in hexadecimal format.
+//!
+//!         AC-DE-48-00-00-80
+//!
+//! In this representation, the first three octets (AC-DE-48) are the
+//! Organizationally Unique Identifier (OUI).  This is a number assigned by
+//! the IEEE to an organization that requests a block of MAC addresses.  The
+//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
+//! to uniquely identify a piece of hardware within that organization that is
+//! to be connected to the Ethernet.
+//!
+//! In this representation, the octets are transmitted from left to right,
+//! with the ``AC'' octet being transmitted first and the ``80'' octet being
+//! transmitted last.  Within an octet, the bits are transmitted LSB to MSB.
+//! For this address, the first bit to be transmitted would be ``0'', the LSB
+//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
+//! ``80''.
+//!
+//! The address passed to this function in the \e pui8MACAddr array is
+//! ordered with the first byte to be transmitted in the first array entry.
+//! For example, the address given above could be represented using the
+//! following array:
+//!
+//! uint8_t g_pui8MACAddr[] = { 0xAC, 0xDE, 0x48, 0x00, 0x00, 0x80 };
+//!
+//! If the MAC address set by this function is currently enabled, it remains
+//! enabled following this call.  Similarly, any filter configured for
+//! the MAC address remains unaffected by a change in the address.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Index < NUM_MAC_ADDR);
+    ASSERT(pui8MACAddr);
+
+    //
+    // Set the high 2 bytes of the MAC address.  Note that we must set the
+    // registers in this order since the address is latched internally
+    // on the write to EMAC_O_ADDRL.
+    //
+    HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) =
+        ((HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF0000) |
+         pui8MACAddr[4] | (pui8MACAddr[5] << 8));
+
+    //
+    // Set the first 4 bytes of the MAC address
+    //
+    HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) =
+        (pui8MACAddr[0] | (pui8MACAddr[1] << 8) | (pui8MACAddr[2] << 16) |
+         (pui8MACAddr[3] << 24));
+}
+
+//*****************************************************************************
+//
+//! Gets one of the MAC addresses stored in the Ethernet controller.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Index is the zero-based index of the MAC address to return.
+//! \param pui8MACAddr is the pointer to the location in which to store the
+//! array of MAC-48 address octets.
+//!
+//! This function reads the currently programmed MAC address into the
+//! \e pui8MACAddr buffer.  The \e ui32Index parameter defines which of the
+//! hardware's MAC addresses to return.  The number of MAC addresses supported
+//! by the controller may be queried using a call to EMACNumAddrGet().
+//! Index 0 refers to the MAC address of the local node.  Other indices are
+//! used to define MAC addresses when filtering incoming packets.
+//!
+//! The address is written to the pui8MACAddr array ordered with the first byte
+//! to be transmitted in the first array entry.  For example, if the address
+//! is written in its usual form with the Organizationally Unique Identifier
+//! (OUI) shown first as:
+//!
+//! AC-DE-48-00-00-80
+//!
+//! the data is returned with 0xAC in the first byte of the array, 0xDE in 
+//! the second, 0x48 in the third and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, uint8_t *pui8MACAddr)
+{
+    uint32_t ui32Val;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Index < NUM_MAC_ADDR);
+    ASSERT(pui8MACAddr);
+
+    //
+    // Get the first 4 bytes of the MAC address.
+    //
+    ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index));
+    pui8MACAddr[0] = ui32Val & 0xFF;
+    pui8MACAddr[1] = (ui32Val >> 8) & 0xFF;
+    pui8MACAddr[2] = (ui32Val >> 16) & 0xFF;
+    pui8MACAddr[3] = (ui32Val >> 24) & 0xFF;
+
+    //
+    // Get the last 2 bytes of the MAC address.
+    //
+    ui32Val = HWREG(ui32Base + EMAC_O_ADDRH(ui32Index));
+    pui8MACAddr[4] = ui32Val & 0xFF;
+    pui8MACAddr[5] = (ui32Val >> 8) & 0xFF;
+}
+
+//*****************************************************************************
+//
+//! Returns the number of MAC addresses supported by the Ethernet controller.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//!
+//! This function may be used to determine the number of MAC addresses that the
+//! given controller supports.  MAC address slots may be used when performing
+//! perfect (rather than hash table) filtering of packets.
+//!
+//! \return Returns the number of supported MAC addresses.
+//
+//*****************************************************************************
+uint32_t
+EMACNumAddrGet(uint32_t ui32Base)
+{
+    //
+    // The only Ethernet controller on Snowflake supports 4 MAC addresses.
+    //
+    return(NUM_MAC_ADDR);
+}
+
+//*****************************************************************************
+//
+//! Sets filtering parameters associated with one of the configured MAC
+//! addresses.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Index is the index of the MAC address slot for which the filter 
+//!        is to be set.
+//! \param ui32Config sets the filter parameters for the given MAC address.
+//!
+//! This function sets filtering parameters associated with one of the MAC
+//! address slots that the controller supports.  This configuration is used
+//! when perfect filtering (rather than hash table filtering) is selected.
+//!
+//! Valid values for \e ui32Index are from 1 to (number of MAC address 
+//! slots - 1). The number of supported MAC address slots may be found by 
+//! calling EMACNumAddrGet().  MAC index 0 is the local MAC address and does 
+//! not have filtering parameters associated with it.
+//!
+//! The \e ui32Config parameter determines how the given MAC address is used
+//! when filtering incoming Ethernet frames.  It is comprised of a logical OR
+//! of the fields:
+//!
+//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled
+//! and should be used when performing perfect filtering.  If this flag is
+//! absent, the MAC address at the given index is disabled and is not used
+//! in filtering.
+//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given
+//! index is compared to the source address of incoming frames while
+//! performing perfect filtering.  If absent, the MAC address is compared
+//! against the destination address.
+//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC should ignore the
+//! sixth byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC should ignore the
+//! fifth byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC should ignore the
+//! fourth byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC should ignore the
+//! third byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC should ignore the
+//! second byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC should ignore the
+//! first byte of the source or destination address when filtering.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config)
+{
+    uint32_t ui32Val;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Index < NUM_MAC_ADDR);
+    ASSERT((ui32Config & ~(EMAC_FILTER_BYTE_MASK_M |
+                           EMAC_FILTER_ADDR_ENABLE |
+                           EMAC_FILTER_SOURCE_ADDR)) == 0);
+    ASSERT(ui32Index);
+
+    //
+    // Set the filter configuration for a particular MAC address.
+    //
+    HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) =
+        (HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF) | ui32Config;
+
+    //
+    // Read and rewrite the low half of the MAC address register to ensure
+    // that the upper half's data is latched.
+    //
+    ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index));
+    HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! Gets filtering parameters associated with one of the configured MAC
+//! addresses.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Index is the index of the MAC address slot for which the filter 
+//!        is to be queried.
+//!
+//! This function returns filtering parameters associated with one of the MAC
+//! address slots that the controller supports.  This configuration is used
+//! when perfect filtering (rather than hash table filtering) is selected.
+//!
+//! Valid values for \e ui32Index are from 1 to (number of MAC address 
+//! slots - 1). The number of supported MAC address slots may be found by 
+//! calling EMACNumAddrGet().  MAC index 0 is the local MAC address and does 
+//! not have filtering parameters associated with it.
+//!
+//! \return Returns the filter configuration as the logical OR of the
+//! following labels:
+//!
+//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled
+//! and is used when performing perfect filtering.  If this flag is absent,
+//! the MAC address at the given index is disabled and is not used in
+//! filtering.
+//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given
+//! index is compared to the source address of incoming frames while performing
+//! perfect filtering.  If absent, the MAC address is compared against the
+//! destination address.
+//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC ignores the
+//! sixth byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC ignores the
+//! fifth byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC ignores the
+//! fourth byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC ignores the
+//! third byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC ignores the
+//! second byte of the source or destination address when filtering.
+//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC ignores the
+//! first byte of the source or destination address when filtering.
+//
+//*****************************************************************************
+uint32_t
+EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Index < NUM_MAC_ADDR);
+    ASSERT(ui32Index);
+
+    //
+    // Read and return the filter settings for the requested MAC address slot.
+    //
+    return(HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) &
+           (EMAC_FILTER_BYTE_MASK_M | EMAC_FILTER_ADDR_ENABLE |
+            EMAC_FILTER_SOURCE_ADDR));
+}
+
+//*****************************************************************************
+//
+//! Sets options related to Ethernet frame filtering.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32FilterOpts is a logical OR of flags defining the required MAC
+//! address filtering options.
+//!
+//! This function allows various filtering options to be defined and allows
+//! an application to control which frames are received based on various
+//! criteria related to the frame source and destination MAC addresses or VLAN
+//! tagging.
+//!
+//! The \e ui32FilterOpts parameter is a logical OR of any of the following
+//! flags:
+//!
+//! - \b EMAC_FRMFILTER_RX_ALL configures the MAC to pass all received frames
+//! regardless of whether or not they pass any address filter that is
+//! configured.  The receive status word in the relevant DMA descriptor is
+//! updated to indicate whether the configured filter passed or failed for
+//! the frame.
+//! - \b EMAC_FRMFILTER_VLAN configures the MAC to drop any frames that do
+//! not pass the VLAN tag comparison.
+//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT configures the MAC to filter frames
+//! based on both any perfect filters set and the hash filter if enabled using
+//! \b EMAC_FRMFILTER_HASH_UNICAST or \b EMAC_FRMFILTER_HASH_MULTICAST.  In
+//! this case, only if both filters fail is the packet rejected.  If this
+//! option is absent, only one of the filter types is used, as controlled by
+//! \b EMAC_FRMFILTER_HASH_UNICAST and \b EMAC_FRMFILTER_HASH_MULTICAST
+//! for unicast and multicast frames respectively.
+//! - \b EMAC_FRMFILTER_SADDR configures the MAC to drop received frames
+//! when the source address field in the frame does not match the values
+//! programmed into the enabled SA registers.
+//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering.
+//! When this option is specified, frames for which the SA does not match the 
+//! SA registers are marked as passing the source address filter.
+//! - \b EMAC_FRMFILTER_BROADCAST configures the MAC to discard all incoming
+//! broadcast frames.
+//! - \b EMAC_FRMFILTER_PASS_MULTICAST configures the MAC to pass all
+//! incoming frames with multicast destinations addresses.
+//! - \b EMAC_FRMFILTER_INV_DADDR inverts the sense of the destination
+//! address filtering for both unicast and multicast frames.
+//! - \b EMAC_FRMFILTER_HASH_MULTICAST enables destination address filtering
+//! of received multicast frames using the hash table.  If absent, perfect
+//! destination address filtering is used.  If used in conjunction with \b
+//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter
+//! should be used for incoming multicast packets along with the perfect
+//! filter.
+//! - \b EMAC_FRMFILTER_HASH_UNICAST enables destination address filtering
+//! of received unicast frames using the hash table.  If absent, perfect
+//! destination address filtering is used.  If used in conjunction with \b
+//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter
+//! should be used for incoming unicast packets along with the perfect filter.
+//! - \b EMAC_FRMFILTER_PROMISCUOUS configures the MAC to operate in
+//! promiscuous mode where all received frames are passed to the application
+//! and the SA and DA filter status bits of the descriptor receive status word
+//! are always cleared.
+//!
+//! Control frame filtering may be configured by ORing one of the following
+//! values into \e ui32FilterOpts:
+//!
+//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching
+//! the application.
+//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than
+//! PAUSE even if they fail the configured address filter.
+//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including
+//! PAUSE even if they fail the configured address filter.
+//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they
+//! pass the configured address filter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts)
+{
+    ASSERT((ui32FilterOpts & ~VALID_FRMFILTER_FLAGS) == 0);
+
+    //
+    // Set the Ethernet MAC frame filter according to the flags passed.
+    //
+    HWREG(ui32Base + EMAC_O_FRAMEFLTR) =
+        ((HWREG(ui32Base + EMAC_O_FRAMEFLTR) & ~VALID_FRMFILTER_FLAGS) |
+         ui32FilterOpts);
+}
+
+//*****************************************************************************
+//
+//! Returns the current Ethernet frame filtering settings.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be called to retrieve the frame filtering configuration
+//! set using a prior call to EMACFrameFilterSet().
+//!
+//! \return Returns a value comprising the logical OR of various flags
+//! indicating the frame filtering options in use.  Possible flags are:
+//!
+//! - \b EMAC_FRMFILTER_RX_ALL indicates that the MAC to is configured to
+//! pass all received frames regardless of whether or not they pass any
+//! address filter that is configured.  The receive status word in the
+//! relevant DMA descriptor is updated to indicate whether the configured
+//! filter passed or failed for the frame.
+//! - \b EMAC_FRMFILTER_VLAN indicates that the MAC is configured to drop any
+//! frames which do not pass the VLAN tag comparison.
+//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT indicates that the MAC is configured
+//! to pass frames if they match either the hash filter or the perfect filter.
+//! If this flag is absent, frames passing based on the result of a single
+//! filter, the perfect filter if \b EMAC_FRMFILTER_HASH_MULTICAST or
+//! \b EMAC_FRMFILTER_HASH_UNICAST are clear or the hash filter otherwise.
+//! - \b EMAC_FRMFILTER_SADDR indicates that the MAC is configured to drop
+//! received frames when the source address field in the frame does not match
+//! the values programmed into the enabled SA registers.
+//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering.
+//! When this option is specified, frames for which the SA does not match the 
+//! SA registers are marked as passing the source address filter.
+//! - \b EMAC_FRMFILTER_BROADCAST indicates that the MAC is configured to
+//! discard all incoming broadcast frames.
+//! - \b EMAC_FRMFILTER_PASS_MULTICAST indicates that the MAC is configured
+//! to pass all incoming frames with multicast destinations addresses.
+//! - \b EMAC_FRMFILTER_INV_DADDR indicates that the sense of the destination
+//! address filtering for both unicast and multicast frames is inverted.
+//! - \b EMAC_FRMFILTER_HASH_MULTICAST indicates that destination address
+//! filtering of received multicast frames is enabled using the hash table.  If
+//! absent, perfect destination address filtering is used.  If used in
+//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates
+//! that the hash filter should be used for incoming multicast packets along
+//! with the perfect filter.
+//! - \b EMAC_FRMFILTER_HASH_UNICAST indicates that destination address
+//! filtering of received unicast frames is enabled using the hash table.  If
+//! absent, perfect destination address filtering is used.  If used in
+//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates
+//! that the hash filter should be used for incoming unicast packets along with
+//! the perfect filter.
+//! - \b EMAC_FRMFILTER_PROMISCUOUS indicates that the MAC is configured to
+//! operate in promiscuous mode where all received frames are passed to the
+//! application and the SA and DA filter status bits of the descriptor receive
+//! status word are always cleared.
+//!
+//! Control frame filtering configuration is indicated by one of the following
+//! values which may be extracted from the returned value using the mask
+//! \b EMAC_FRMFILTER_PASS_MASK:
+//!
+//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching
+//! the application.
+//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than
+//! PAUSE even if they fail the configured address filter.
+//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including
+//! PAUSE even if they fail the configured address filter.
+//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they
+//! pass the configured address filter.
+//
+//*****************************************************************************
+uint32_t
+EMACFrameFilterGet(uint32_t ui32Base)
+{
+    //
+    // Return the current MAC frame filter setting.
+    //
+    return(HWREG(ui32Base + EMAC_O_FRAMEFLTR) & VALID_FRMFILTER_FLAGS);
+}
+
+//*****************************************************************************
+//
+//! Sets the MAC address hash filter table.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32HashHi is the upper 32 bits of the current 64-bit hash filter
+//! table to set.
+//! \param ui32HashLo is the lower 32 bits of the current 64-bit hash filter
+//! table to set.
+//!
+//! This function may be used to set the current 64-bit hash filter table
+//! used by the MAC to filter incoming packets when hash filtering is enabled.
+//! Hash filtering is enabled by passing \b EMAC_FRMFILTER_HASH_UNICAST
+//! and/or \b EMAC_FRMFILTER_HASH_MULTICAST in the \e ui32FilterOpts parameter
+//! to EMACFrameFilterSet().  The current hash filter may be retrieved
+//! by calling EMACHashFilterGet().
+//!
+//! Hash table filtering allows many different MAC addresses to be filtered
+//! simultaneously at the cost of some false-positive results (in the form of
+//! packets passing the filter when their MAC address was not one of those
+//! required).  A CRC of the packet source or destination MAC address is
+//! calculated and the bottom 6 bits are used as a bit index into the 64-bit
+//! hash filter table.  If the bit in the hash table is set, the filter is
+//! considered to have passed.  If the bit is clear, the filter fails and the
+//! packet is rejected (assuming normal rather than inverse filtering is
+//! configured).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo)
+{
+    // Set the hash table with the values provided.
+    HWREG(ui32Base + EMAC_O_HASHTBLL) = ui32HashLo;
+    HWREG(ui32Base + EMAC_O_HASHTBLH) = ui32HashHi;
+}
+
+//*****************************************************************************
+//
+//! Returns the current MAC address hash filter table.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pui32HashHi points to storage to be written with the upper 32 bits 
+//! of the current 64-bit hash filter table.
+//! \param pui32HashLo points to storage to be written with the lower 32 bits 
+//! of the current 64-bit hash filter table.
+//!
+//! This function may be used to retrieve the current 64-bit hash filter table
+//! from the MAC prior to making changes and setting the new hash filter via a
+//! call to EMACHashFilterSet().
+//!
+//! Hash table filtering allows many different MAC addresses to be filtered
+//! simultaneously at the cost of some false-positive results in the form of
+//! packets passing the filter when their MAC address was not one of those
+//! required.  A CRC of the packet source or destination MAC address is
+//! calculated and the bottom 6 bits are used as a bit index into the 64-bit
+//! hash filter table.  If the bit in the hash table is set, the filter is
+//! considered to have passed.  If the bit is clear, the filter fails and the
+//! packet is rejected (assuming normal rather than inverse filtering is
+//! configured).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi,
+                  uint32_t *pui32HashLo)
+{
+    ASSERT(pui32HashHi);
+    ASSERT(pui32HashLo);
+
+    //
+    // Get the current hash table values.
+    //
+    *pui32HashLo = HWREG(ui32Base + EMAC_O_HASHTBLL);
+    *pui32HashHi = HWREG(ui32Base + EMAC_O_HASHTBLH);
+}
+
+//*****************************************************************************
+//
+//! Returns the bit number to set in the MAC hash filter corresponding to a
+//! given MAC address.
+//!
+//! \param pui8MACAddr points to a buffer containing the 6-byte MAC address
+//!  for which the hash filter bit is to be determined.
+//!
+//! This function may be used to determine which bit in the MAC address hash
+//! filter to set to describe a given 6-byte MAC address.  The returned value is
+//! a 6-bit number where bit 5 indicates which of the two hash table words is
+//! affected and the bottom 5 bits indicate the bit number to set within that
+//! word.  For example, if 0x22 (100010b) is returned, this indicates that bit
+//! 2 of word 1 (\e ui32HashHi as passed to EMACHashFilterSet()) must be set
+//! to describe the passed MAC address.
+//!
+//! \return Returns the bit number to set in the MAC hash table to describe the
+//! passed MAC address.
+//
+//*****************************************************************************
+uint32_t
+EMACHashFilterBitCalculate(uint8_t *pui8MACAddr)
+{
+    uint32_t ui32CRC, ui32Mask, ui32Loop;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(pui8MACAddr);
+
+    //
+    // Calculate the CRC for the MAC address.
+    //
+    ui32CRC = Crc32(0xFFFFFFFF, pui8MACAddr, 6);
+    ui32CRC ^= 0xFFFFFFFF;
+
+    //
+    // Determine the hash bit to use from the calculated CRC.  This is the
+    // top 6 bits of the reversed CRC (or the bottom 6 bits of the calculated
+    // CRC with the bit order of those 6 bits reversed).
+    //
+    ui32Mask = 0;
+
+    //
+    // Reverse the order of the bottom 6 bits of the calculated CRC.
+    //
+    for(ui32Loop = 0; ui32Loop < 6; ui32Loop++)
+    {
+        ui32Mask <<= 1;
+        ui32Mask |= (ui32CRC & 1);
+        ui32CRC >>= 1;
+    }
+
+    //
+    // Return the final hash table bit index.
+    //
+    return(ui32Mask);
+}
+
+//*****************************************************************************
+//
+//! Sets the receive interrupt watchdog timer period.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//! \param ui8Timeout is the desired timeout expressed as a number of 256
+//! system clock periods.
+//!
+//! This function configures the receive interrupt watchdog timer.
+//! The \e uiTimeout parameter specifies the number of 256 system clock periods
+//! that elapse before the timer expires.  In cases where the DMA has
+//! transferred a frame using a descriptor that has
+//! \b DES1_RX_CTRL_DISABLE_INT set, the watchdog causes a receive
+//! interrupt to be generated when it times out.  The watchdog timer is reset
+//! whenever a packet is transferred to memory using a DMA descriptor that
+//! does not disable the receive interrupt.
+//!
+//! To disable the receive interrupt watchdog function, set \e ui8Timeout to 0.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout)
+{
+    //
+    // Set the receive interrupt watchdog timeout period.
+    //
+    HWREG(ui32Base + EMAC_O_RXINTWDT) = (uint32_t)ui8Timeout;
+}
+
+//*****************************************************************************
+//
+//! Returns the current Ethernet MAC status.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//!
+//! This function returns information on the current status of all the main
+//! modules in the MAC transmit and receive data paths.
+//!
+//! \return Returns the current MAC status as a logical OR of any of the
+//! following flags:
+//!
+//! - \b EMAC_STATUS_TX_NOT_EMPTY
+//! - \b EMAC_STATUS_TX_WRITING_FIFO
+//! - \b EMAC_STATUS_TX_PAUSED
+//! - \b EMAC_STATUS_MAC_NOT_IDLE
+//! - \b EMAC_STATUS_RWC_ACTIVE
+//! - \b EMAC_STATUS_RPE_ACTIVE
+//!
+//! The transmit frame controller status can be extracted from the returned 
+//! value by ANDing with \b EMAC_STATUS_TFC_STATE_MASK and is one of the 
+//! following:
+//!
+//! - \b EMAC_STATUS_TFC_STATE_IDLE
+//! - \b EMAC_STATUS_TFC_STATE_WAITING
+//! - \b EMAC_STATUS_TFC_STATE_PAUSING
+//! - \b EMAC_STATUS_TFC_STATE_WRITING
+//!
+//! The transmit FIFO read controller status can be extracted from the returned 
+//! value by ANDing with \b EMAC_STATUS_TRC_STATE_MASK and is one of the 
+//! following:
+//!
+//! - \b EMAC_STATUS_TRC_STATE_IDLE
+//! - \b EMAC_STATUS_TRC_STATE_READING
+//! - \b EMAC_STATUS_TRC_STATE_WAITING
+//! - \b EMAC_STATUS_TRC_STATE_STATUS
+//!
+//! The current receive FIFO levels can be extracted from the returned value
+//! by ANDing with \b EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the 
+//! following:
+//!
+//! - \b EMAC_STATUS_RX_FIFO_EMPTY indicating that the FIFO is empty.
+//! - \b EMAC_STATUS_RX_FIFO_BELOW indicating that the FIFO fill level is
+//! below the flow-control deactivate threshold.
+//! - \b EMAC_STATUS_RX_FIFO_ABOVE indicating that the FIFO fill level is
+//! above the flow-control activate threshold.
+//! - \b EMAC_STATUS_RX_FIFO_FULL indicating that the FIFO is full.
+//!
+//! The current receive FIFO state can be extracted from the returned value
+//! by ANDing with \b EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the 
+//! following:
+//!
+//! - \b EMAC_STATUS_RX_FIFO_IDLE
+//! - \b EMAC_STATUS_RX_FIFO_READING
+//! - \b EMAC_STATUS_RX_FIFO_STATUS
+//! - \b EMAC_STATUS_RX_FIFO_FLUSHING
+//
+//*****************************************************************************
+uint32_t
+EMACStatusGet(uint32_t ui32Base)
+{
+    //
+    // Read and return the MAC status register content.
+    //
+    return(HWREG(ui32Base + EMAC_O_STATUS));
+}
+
+//*****************************************************************************
+//
+//! Orders the MAC DMA controller to attempt to acquire the next transmit
+//! descriptor.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//!
+//! This function must be called to restart the transmitter if it has been
+//! suspended due to the current transmit DMA descriptor being owned by the
+//! host.  Once the application writes new values to the descriptor and marks
+//! it as being owned by the MAC DMA, this function causes the hardware to
+//! attempt to acquire the descriptor and start transmission of the new
+//! data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTxDMAPollDemand(uint32_t ui32Base)
+{
+    //
+    // Any write to the MACTXPOLLD register causes the transmit DMA to attempt
+    // to resume.
+    //
+    HWREG(ui32Base + EMAC_O_TXPOLLD) = 0;
+}
+
+//*****************************************************************************
+//
+//! Orders the MAC DMA controller to attempt to acquire the next receive
+//! descriptor.
+//!
+//! \param ui32Base is the base address of the Ethernet controller.
+//!
+//! This function must be called to restart the receiver if it has been
+//! suspended due to the current receive DMA descriptor being owned by the
+//! host.  Once the application reads any data from the descriptor and marks
+//! it as being owned by the MAC DMA, this function causes the hardware to
+//! attempt to acquire the descriptor before writing the next received packet
+//! into its buffer(s).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRxDMAPollDemand(uint32_t ui32Base)
+{
+    //
+    // Any write to the MACRXPOLLD register causes the receive DMA to attempt
+    // to resume.
+    //
+    HWREG(ui32Base + EMAC_O_RXPOLLD) = 0;
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA receive descriptor list pointer.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pDescriptor points to the first DMA descriptor in the list to
+//! be passed to the receive DMA engine.
+//!
+//! This function sets the Ethernet MAC's receive DMA descriptor list pointer.
+//! The \e pDescriptor pointer must point to one or more descriptor
+//! structures.
+//!
+//! When multiple descriptors are provided, they can be either chained or
+//! unchained.  Chained descriptors are indicated by setting the
+//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant
+//! word of the transmit or receive descriptor.  If this bit is clear,
+//! unchained descriptors are assumed.
+//!
+//! Chained descriptors use a link pointer in each descriptor to
+//! point to the next descriptor in the chain.
+//!
+//! Unchained descriptors are assumed to be contiguous in memory with a
+//! consistent offset between the start of one descriptor and the next.
+//! If unchained descriptors are used, the \e pvLink field in the descriptor
+//! becomes available to store a second buffer pointer, allowing each
+//! descriptor to point to two buffers rather than one.  In this case,
+//! the \e ui32DescSkipSize parameter to EMACInit() must previously have
+//! been set to the number of words between the end of one descriptor and
+//! the start of the next.  This value must be 0 in cases where a packed array
+//! of \b tEMACDMADescriptor structures is used. If the application wishes to
+//! add new state fields to the end of the descriptor structure, the skip size
+//! should be set to accommodate the newly sized structure.
+//!
+//! Applications are responsible for initializing all descriptor fields
+//! appropriately before passing the descriptor list to the hardware.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(pDescriptor);
+    ASSERT(((uint32_t)pDescriptor & 3) == 0);
+
+    //
+    // Write the supplied address to the MACRXDLADDR register.
+    //
+    HWREG(ui32Base + EMAC_O_RXDLADDR) = (uint32_t)pDescriptor;
+}
+
+//*****************************************************************************
+//
+//! Returns a pointer to the start of the DMA receive descriptor list.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function returns a pointer to the head of the Ethernet MAC's receive
+//! DMA descriptor list.  This value corresponds to the pointer originally set
+//! using a call to EMACRxDMADescriptorListSet().
+//!
+//! \return Returns a pointer to the start of the DMA receive descriptor list.
+//
+//*****************************************************************************
+tEMACDMADescriptor *
+EMACRxDMADescriptorListGet(uint32_t ui32Base)
+{
+    //
+    // Return the current receive DMA descriptor list pointer.
+    //
+    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_RXDLADDR));
+}
+
+//*****************************************************************************
+//
+//! Returns the current DMA receive descriptor pointer.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function returns a pointer to the current Ethernet receive descriptor
+//! read by the DMA.
+//!
+//! \return Returns a pointer to the start of the current receive DMA
+//! descriptor.
+//
+//*****************************************************************************
+tEMACDMADescriptor *
+EMACRxDMACurrentDescriptorGet(uint32_t ui32Base)
+{
+    //
+    // Return the address of the current receive descriptor written by the DMA.
+    //
+    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSRXDESC));
+}
+
+//*****************************************************************************
+//
+//! Returns the current DMA receive buffer pointer.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be called to determine which buffer the receive DMA
+//! engine is currently writing to.
+//!
+//! \return Returns the receive buffer address currently being written by
+//! the DMA engine.
+//
+//*****************************************************************************
+uint8_t *
+EMACRxDMACurrentBufferGet(uint32_t ui32Base)
+{
+    //
+    // Return the receive buffer address currently being written by the DMA.
+    //
+    return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSRXBA));
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA transmit descriptor list pointer.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pDescriptor points to the first DMA descriptor in the list to
+//! be passed to the transmit DMA engine.
+//!
+//! This function sets the Ethernet MAC's transmit DMA descriptor list pointer.
+//! The \e pDescriptor pointer must point to one or more descriptor
+//! structures.
+//!
+//! When multiple descriptors are provided, they can be either chained or
+//! unchained.  Chained descriptors are indicated by setting the
+//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant
+//! word of the transmit or receive descriptor.  If this bit is clear,
+//! unchained descriptors are assumed.
+//!
+//! Chained descriptors use a link pointer in each descriptor to
+//! point to the next descriptor in the chain.
+//!
+//! Unchained descriptors are assumed to be contiguous in memory with a
+//! consistent offset between the start of one descriptor and the next.
+//! If unchained descriptors are used, the \e pvLink field in the descriptor
+//! becomes available to store a second buffer pointer, allowing each
+//! descriptor to point to two buffers rather than one.  In this case,
+//! the \e ui32DescSkipSize parameter to EMACInit() must previously have
+//! been set to the number of words between the end of one descriptor and
+//! the start of the next.  This value must be 0 in cases where a packed array
+//! of \b tEMACDMADescriptor structures is used. If the application wishes to
+//! add new state fields to the end of the descriptor structure, the skip size
+//! should be set to accommodate the newly sized structure.
+//!
+//! Applications are responsible for initializing all descriptor fields
+//! appropriately before passing the descriptor list to the hardware.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(pDescriptor);
+    ASSERT(((uint32_t)pDescriptor & 3) == 0);
+
+    //
+    // Write the supplied address to the MACTXDLADDR register.
+    //
+    HWREG(ui32Base + EMAC_O_TXDLADDR) = (uint32_t)pDescriptor;
+}
+
+//*****************************************************************************
+//
+//! Returns a pointer to the start of the DMA transmit descriptor list.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function returns a pointer to the head of the Ethernet MAC's transmit
+//! DMA descriptor list.  This value corresponds to the pointer originally set 
+//! using a call to EMACTxDMADescriptorListSet().
+//!
+//! \return Returns a pointer to the start of the DMA transmit descriptor list.
+//
+//*****************************************************************************
+tEMACDMADescriptor *
+EMACTxDMADescriptorListGet(uint32_t ui32Base)
+{
+    //
+    // Return the current transmit DMA descriptor list pointer.
+    //
+    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_TXDLADDR));
+}
+
+//*****************************************************************************
+//
+//! Returns the current DMA transmit descriptor pointer.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function returns a pointer to the current Ethernet transmit descriptor
+//! read by the DMA.
+//!
+//! \return Returns a pointer to the start of the current transmit DMA
+//! descriptor.
+//
+//*****************************************************************************
+tEMACDMADescriptor *
+EMACTxDMACurrentDescriptorGet(uint32_t ui32Base)
+{
+    //
+    // Return the address of the current transmit descriptor read by the DMA.
+    //
+    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSTXDESC));
+}
+
+//*****************************************************************************
+//
+//! Returns the current DMA transmit buffer pointer.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be called to determine which buffer the transmit DMA
+//! engine is currently reading from.
+//!
+//! \return Returns the transmit buffer address currently being read by the
+//! DMA engine.
+//
+//*****************************************************************************
+uint8_t *
+EMACTxDMACurrentBufferGet(uint32_t ui32Base)
+{
+    //
+    // Return the transmit buffer address currently being read by the DMA.
+    //
+    return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSTXBA));
+}
+
+//*****************************************************************************
+//
+//! Returns the current states of the Ethernet MAC transmit and receive DMA
+//! engines.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be used to query the current states of the transmit and
+//! receive DMA engines.  The return value contains two fields, one providing
+//! the transmit state and the other the receive state.  Macros
+//! \b EMAC_TX_DMA_STATE() and \b EMAC_RX_DMA_STATE() may be used to
+//! extract these fields from the returned value.  Alternatively, masks
+//! \b EMAC_DMA_TXSTAT_MASK and \b EMAC_DMA_RXSTAT_MASK may be used
+//! directly to mask out the individual states from the returned value.
+//!
+//! \return Returns the states of the transmit and receive DMA engines.  These
+//! states are ORed together into a single word containing one of:
+//!
+//! - \b EMAC_DMA_TXSTAT_STOPPED indicating that the transmit engine is
+//! stopped.
+//! - \b EMAC_DMA_TXSTAT_RUN_FETCH_DESC indicating that the transmit engine
+//! is fetching the next descriptor.
+//! - \b EMAC_DMA_TXSTAT_RUN_WAIT_STATUS indicating that the transmit engine
+//! is waiting for status from the MAC.
+//! - \b EMAC_DMA_TXSTAT_RUN_READING indicating that the transmit engine is
+//! currently transferring data from memory to the MAC transmit FIFO.
+//! - \b EMAC_DMA_TXSTAT_RUN_CLOSE_DESC indicating that the transmit engine
+//! is closing the descriptor after transmission of the buffer data.
+//! - \b EMAC_DMA_TXSTAT_TS_WRITE indicating that the transmit engine is
+//! currently writing timestamp information to the descriptor.
+//! - \b EMAC_DMA_TXSTAT_SUSPENDED indicating that the transmit engine is
+//! suspended due to the next descriptor being unavailable (owned by the host)
+//! or a transmit buffer underflow.
+//!
+//! and one of:
+//!
+//! - \b EMAC_DMA_RXSTAT_STOPPED indicating that the receive engine is
+//! stopped.
+//! - \b EMAC_DMA_RXSTAT_RUN_FETCH_DESC indicating that the receive engine
+//! is fetching the next descriptor.
+//! - \b EMAC_DMA_RXSTAT_RUN_WAIT_PACKET indicating that the receive engine
+//! is waiting for the next packet.
+//! - \b EMAC_DMA_RXSTAT_SUSPENDED indicating that the receive engine is
+//! suspended due to the next descriptor being unavailable.
+//! - \b EMAC_DMA_RXSTAT_RUN_CLOSE_DESC indicating that the receive engine
+//! is closing the descriptor after receiving a buffer of data.
+//! - \b EMAC_DMA_RXSTAT_TS_WRITE indicating that the transmit engine is
+//! currently writing timestamp information to the descriptor.
+//! - \b EMAC_DMA_RXSTAT_RUN_RECEIVING indicating that the receive engine is
+//! currently transferring data from the MAC receive FIFO to memory.
+//!
+//! Additionally, a DMA bus error may be signaled using \b EMAC_DMA_ERROR.
+//! If this flag is present, the source of the error is identified using one
+//! of the following values which may be extracted from the return value using
+//! \b EMAC_DMA_ERR_MASK:
+//!
+//! - \b EMAC_DMA_ERR_RX_DATA_WRITE indicates that an error occurred when
+//! writing received data to memory.
+//! - \b EMAC_DMA_ERR_TX_DATA_READ indicates that an error occurred when
+//! reading data from memory for transmission.
+//! - \b EMAC_DMA_ERR_RX_DESC_WRITE indicates that an error occurred when
+//! writing to the receive descriptor.
+//! - \b EMAC_DMA_ERR_TX_DESC_WRITE indicates that an error occurred when
+//! writing to the transmit descriptor.
+//! - \b EMAC_DMA_ERR_RX_DESC_READ indicates that an error occurred when
+//! reading the receive descriptor.
+//! - \b EMAC_DMA_ERR_TX_DESC_READ indicates that an error occurred when
+//! reading the transmit descriptor.
+//
+//*****************************************************************************
+uint32_t
+EMACDMAStateGet(uint32_t ui32Base)
+{
+    //
+    // Return the status of the DMA channels.
+    //
+    return(HWREG(ui32Base + EMAC_O_DMARIS) &
+           (EMAC_DMARIS_FBI | EMAC_DMARIS_AE_M | EMAC_DMARIS_RS_M |
+            EMAC_DMARIS_TS_M));
+}
+
+//*****************************************************************************
+//
+//! Flushes the Ethernet controller transmit FIFO.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function flushes any data currently held in the Ethernet transmit
+//! FIFO.  Data that has already been passed to the MAC for transmission is
+//! transmitted, possibly resulting in a transmit underflow or runt frame
+//! transmission.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTxFlush(uint32_t ui32Base)
+{
+    //
+    // Check to make sure that the FIFO is not already empty.
+    //
+    if(HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_TXFE)
+    {
+        //
+        // Flush the transmit FIFO since it is not currently empty.
+        //
+        HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_FTF;
+
+        //
+        // Wait for the flush to complete.
+        //
+        while(HWREG(ui32Base + EMAC_O_DMAOPMODE) & EMAC_DMAOPMODE_FTF)
+        {
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables the Ethernet controller transmitter.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! When starting operations on the Ethernet interface, this function should
+//! be called to enable the transmitter after all configuration has been
+//! completed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTxEnable(uint32_t ui32Base)
+{
+    //
+    // Enable the MAC transmit path in the opmode register.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_ST;
+
+    //
+    // Enable transmission in the MAC configuration register.
+    //
+    HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_TE;
+}
+
+//*****************************************************************************
+//
+//! Disables the Ethernet controller transmitter.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! When terminating operations on the Ethernet interface, this function should
+//! be called.  This function disables the transmitter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTxDisable(uint32_t ui32Base)
+{
+    //
+    // Disable transmission in the MAC configuration register.
+    //
+    HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE;
+
+    //
+    // Disable the MAC transmit path in the opmode register.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST;
+}
+
+//*****************************************************************************
+//
+//! Enables the Ethernet controller receiver.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! When starting operations on the Ethernet interface, this function should
+//! be called to enable the receiver after all configuration has been
+//! completed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRxEnable(uint32_t ui32Base)
+{
+    //
+    // Enable the MAC receive path.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_SR;
+
+    //
+    // Enable receive in the MAC configuration register.
+    //
+    HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_RE;
+}
+
+//*****************************************************************************
+//
+//! Disables the Ethernet controller receiver.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! When terminating operations on the Ethernet interface, this function should
+//! be called.  This function disables the receiver.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRxDisable(uint32_t ui32Base)
+{
+    //
+    // Disable reception in the MAC configuration register.
+    //
+    HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_RE;
+
+    //
+    // Disable the MAC receive path.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled Ethernet interrupts occur.
+//!
+//! This function sets the handler to be called when the Ethernet interrupt
+//! occurs.  This function enables the global interrupt in the interrupt
+//! controller; specific Ethernet interrupts must be enabled via
+//! EMACIntEnable().  It is the interrupt handler's responsibility to clear
+//! the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(pfnHandler != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_EMAC0_TM4C129, pfnHandler);
+
+    //
+    // Enable the Ethernet interrupt.
+    //
+    IntEnable(INT_EMAC0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function unregisters the interrupt handler.  This function disables
+//! the global interrupt in the interrupt controller so that the interrupt
+//! handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACIntUnregister(uint32_t ui32Base)
+{
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_EMAC0_TM4C129);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_EMAC0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Enables individual Ethernet MAC interrupt sources.
+//!
+//! \param ui32Base is the base address of the Ethernet MAC.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated Ethernet MAC interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state.
+//! Software must read and write the appropriate PHY registers to enable and
+//! disable particular notifications.
+//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the
+//! first data buffer of a packet.
+//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and
+//! that the DMA engine has been disabled.
+//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has
+//! been fully written from memory into the MAC transmit FIFO.
+//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than
+//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
+//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered
+//! the stopped state.
+//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire
+//! a buffer.  The receive process is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACRxDMAPollDemand().
+//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed
+//! and all requested status has been written to the appropriate DMA receive
+//! descriptor.
+//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an
+//! underflow during transmission.  The transmit process is suspended.
+//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced
+//! during reception.
+//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired.
+//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 
+//! bytes in Jumbo Frame mode) and causes the transmit process to abort and 
+//! enter the Stopped state.
+//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's transmit descriptor list and that the DMA cannot, therefore,
+//! acquire a buffer.  Transmission is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACTxDMAPollDemand().
+//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
+//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has
+//! completed and that all requested status has been updated in the descriptor.
+//!
+//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and
+//! \b EMAC_INT_ABNORMAL_INT are enabled automatically by the driver if any
+//! of their constituent sources are enabled.  Applications do not need to
+//! explicitly enable these bits.
+//!
+//! \note Timestamp-related interrupts from the IEEE 1588 module must be
+//! enabled independently by using a call to EMACTimestampTargetIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0);
+
+    //
+    // Enable the normal interrupt if any of its individual sources are
+    // enabled.
+    //
+    if(ui32IntFlags & EMAC_NORMAL_INTS)
+    {
+        ui32IntFlags |= EMAC_INT_NORMAL_INT;
+    }
+
+    //
+    // Similarly, enable the abnormal interrupt if any of its individual
+    // sources are enabled.
+    //
+    if(ui32IntFlags & EMAC_ABNORMAL_INTS)
+    {
+        ui32IntFlags |= EMAC_INT_ABNORMAL_INT;
+    }
+
+    //
+    // Set the MAC DMA interrupt mask appropriately if any of the sources
+    // we've been asked to enable are found in that register.
+    //
+    if(ui32IntFlags & ~EMAC_INT_PHY)
+    {
+        HWREG(ui32Base + EMAC_O_DMAIM) |= ui32IntFlags & ~EMAC_INT_PHY;
+    }
+
+    //
+    // Enable the PHY interrupt if we've been asked to do this.
+    //
+    if(ui32IntFlags & EMAC_INT_PHY)
+    {
+        HWREG(ui32Base + EMAC_O_EPHYIM) |= EMAC_EPHYIM_INT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables individual Ethernet MAC interrupt sources.
+//!
+//! \param ui32Base is the base address of the Ethernet MAC.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated Ethernet MAC interrupt sources.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state.
+//! Software must read and write the appropriate PHY registers to enable and
+//! disable particular notifications.
+//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the
+//! first data buffer of a packet.
+//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and
+//! that the DMA engine has been disabled.
+//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has
+//! been fully written from memory into the MAC transmit FIFO.
+//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than
+//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
+//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered
+//! the stopped state.
+//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire
+//! a buffer.  The receive process is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACRxDMAPollDemand().
+//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed
+//! and all requested status has been written to the appropriate DMA receive
+//! descriptor.
+//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an
+//! underflow during transmission.  The transmit process is suspended.
+//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced
+//! during reception.
+//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired.
+//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 
+//! bytes in Jumbo Frame mode) and causes the transmit process to abort and 
+//! enter the Stopped state.
+//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's transmit descriptor list and that the DMA cannot, therefore,
+//! acquire a buffer.  Transmission is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACTxDMAPollDemand().
+//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
+//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has
+//! completed and that all requested status has been updated in the descriptor.
+//! - \b EMAC_INT_TIMESTAMP indicates that an interrupt from the timestamp
+//! module has occurred.  This precise source of the interrupt can be
+//! determined by calling EMACTimestampIntStatus(), which also clears this
+//! bit.
+//!
+//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and
+//! \b EMAC_INT_ABNORMAL_INT are disabled automatically by the driver if none
+//! of their constituent sources are enabled.  Applications do not need to
+//! explicitly disable these bits.
+//!
+//! \note Timestamp-related interrupts from the IEEE 1588 module must be
+//! disabled independently by using a call to EMACTimestampTargetIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    uint32_t ui32Mask;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0);
+
+    //
+    // Get the current interrupt mask.
+    //
+    ui32Mask = HWREG(ui32Base + EMAC_O_DMAIM);
+
+    //
+    // Clear the requested bits.
+    //
+    ui32Mask &= ~(ui32IntFlags & ~EMAC_INT_PHY);
+
+    //
+    // If none of the normal interrupt sources are enabled, disable the
+    // normal interrupt.
+    //
+    if(!(ui32Mask & EMAC_NORMAL_INTS))
+    {
+        ui32Mask &= ~EMAC_INT_NORMAL_INT;
+    }
+
+    //
+    // Similarly, if none of the abnormal interrupt sources are enabled,
+    // disable the abnormal interrupt.
+    //
+    if(!(ui32Mask & EMAC_ABNORMAL_INTS))
+    {
+        ui32Mask &= ~EMAC_INT_ABNORMAL_INT;
+    }
+
+    //
+    // Write the new mask back to the hardware.
+    //
+    HWREG(ui32Base + EMAC_O_DMAIM) = ui32Mask;
+
+    //
+    // Disable the PHY interrupt if we've been asked to do this.
+    //
+    if(ui32IntFlags & EMAC_INT_PHY)
+    {
+        HWREG(ui32Base + EMAC_O_EPHYIM) &= ~EMAC_EPHYIM_INT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current Ethernet MAC interrupt status.
+//!
+//! \param ui32Base is the base address of the Ethernet MAC.
+//! \param bMasked is \b true to return the masked interrupt status or \b false
+//! to return the unmasked status.
+//!
+//! This function returns the interrupt status for the Ethernet MAC.  Either
+//! the raw interrupt status or the status of interrupts that are allowed
+//! to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status as the logical OR of any of
+//! the following:
+//!
+//! - \b EMAC_INT_PHY indicates that the PHY interrupt has occurred.
+//! Software must read the relevant PHY interrupt status register to determine
+//! the cause.
+//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the
+//! first data buffer of a packet.
+//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and
+//! that the DMA engine has been disabled.  The cause of the error can be
+//! determined by calling EMACDMAStateGet().
+//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has
+//! been fully written from memory into the MAC transmit FIFO.
+//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than
+//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
+//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered
+//! the stopped state.
+//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire
+//! a buffer.  The receive process is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACRxDMAPollDemand().
+//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed
+//! and all requested status has been written to the appropriate DMA receive
+//! descriptor.
+//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an
+//! underflow during transmission.  The transmit process is suspended.
+//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced
+//! during reception.
+//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired.
+//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 
+//! bytes in Jumbo Frame mode) and causes the transmit process to abort and 
+//! enter the Stopped state.
+//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's transmit descriptor list and that the DMA cannot, therefore,
+//! acquire a buffer.  Transmission is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACTxDMAPollDemand().
+//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
+//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has
+//! completed and that all requested status has been updated in the descriptor.
+//! - \b EMAC_INT_NORMAL_INT is a summary interrupt comprising the logical
+//! OR of the masked state of \b EMAC_INT_TRANSMIT, \b EMAC_INT_RECEIVE,
+//! \b EMAC_INT_TX_NO_BUFFER and \b EMAC_INT_EARLY_RECEIVE.
+//! - \b EMAC_INT_ABNORMAL_INT is a summary interrupt comprising the logical
+//! OR of the masked state of \b EMAC_INT_TX_STOPPED, \b EMAC_INT_TX_JABBER,
+//! \b EMAC_INT_RX_OVERFLOW, \b EMAC_INT_TX_UNDERFLOW,
+//! \b EMAC_INT_RX_NO_BUFFER, \b EMAC_INT_RX_STOPPED,
+//! \b EMAC_INT_RX_WATCHDOG, \b EMAC_INT_EARLY_TRANSMIT and
+//! \b EMAC_INT_BUS_ERROR.
+//
+//*****************************************************************************
+uint32_t
+EMACIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    uint32_t ui32Val, ui32PHYStat;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Get the unmasked interrupt status and clear any unwanted status fields.
+    //
+    ui32Val = HWREG(ui32Base + EMAC_O_DMARIS);
+    ui32Val &= ~(EMAC_DMARIS_AE_M | EMAC_DMARIS_TS_M | EMAC_DMARIS_RS_M);
+
+    //
+    // This peripheral doesn't have a masked interrupt status register
+    // so perform the masking manually.  Note that only the bottom 16 bits
+    // of the register can be masked so make sure we take this into account.
+    //
+    if(bMasked)
+    {
+        ui32Val &= (EMAC_NON_MASKED_INTS | HWREG(ui32Base + EMAC_O_DMAIM));
+    }
+
+    //
+    // Read the PHY interrupt status.
+    //
+    if(bMasked)
+    {
+        ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYMISC);
+    }
+    else
+    {
+        ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYRIS);
+    }
+
+    //
+    // If the PHY interrupt is reported, add the appropriate flag to the
+    // return value.
+    //
+    if(ui32PHYStat & EMAC_EPHYMISC_INT)
+    {
+        ui32Val |= EMAC_INT_PHY;
+    }
+
+    return(ui32Val);
+}
+
+//*****************************************************************************
+//
+//! Clears individual Ethernet MAC interrupt sources.
+//!
+//! \param ui32Base is the base address of the Ethernet MAC.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared.
+//!
+//! This function disables the indicated Ethernet MAC interrupt sources.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state.
+//! Software must read and write the appropriate PHY registers to enable,
+//! disable and clear particular notifications.
+//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the
+//! first data buffer of a packet.
+//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and
+//! that the DMA engine has been disabled.
+//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has
+//! been fully written from memory into the MAC transmit FIFO.
+//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than
+//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received.
+//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered
+//! the stopped state.
+//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire
+//! a buffer.  The receive process is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACRxDMAPollDemand().
+//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed
+//! and all requested status has been written to the appropriate DMA receive
+//! descriptor.
+//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an
+//! underflow during transmission.  The transmit process is suspended.
+//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced
+//! during reception.
+//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired.
+//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 
+//! bytes in Jumbo Frame mode) and causes the transmit process to abort and 
+//! enter the Stopped state.
+//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer
+//! in the DMA's transmit descriptor list and that the DMA cannot, therefore,
+//! acquire a buffer.  Transmission is suspended and can be resumed by changing
+//! the descriptor ownership and calling EMACTxDMAPollDemand().
+//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped.
+//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has
+//! completed and that all requested status has been updated in the descriptor.
+//!
+//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and
+//! \b EMAC_INT_ABNORMAL_INT are cleared automatically by the driver if any
+//! of their constituent sources are cleared.  Applications do not need to
+//! explicitly clear these bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Mask in the normal interrupt if one of the sources it relates to is
+    // specified.
+    //
+    if(ui32IntFlags & EMAC_NORMAL_INTS)
+    {
+        ui32IntFlags |= EMAC_INT_NORMAL_INT;
+    }
+
+    //
+    // Similarly, mask in the abnormal interrupt if one of the sources it
+    // relates to is specified.
+    //
+    if(ui32IntFlags & EMAC_ABNORMAL_INTS)
+    {
+        ui32IntFlags |= EMAC_INT_ABNORMAL_INT;
+    }
+
+    //
+    // Clear the maskable interrupt sources.  We write exactly the value passed
+    // (with the summary sources added if necessary) but remember that only
+    // the bottom 17 bits of the register are actually clearable.  Only do
+    // this if some bits are actually set that refer to the DMA interrupt
+    // sources.
+    //
+    if(ui32IntFlags & ~EMAC_INT_PHY)
+    {
+        HWREG(ui32Base + EMAC_O_DMARIS) = (ui32IntFlags & ~EMAC_INT_PHY);
+    }
+
+    //
+    // Clear the PHY interrupt if we've been asked to do this.
+    //
+    if(ui32IntFlags & EMAC_INT_PHY)
+    {
+        HWREG(ui32Base + EMAC_O_EPHYMISC) |= EMAC_EPHYMISC_INT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes to the PHY register.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to access.
+//! \param ui8RegAddr is the address of the PHY register to be accessed.
+//! \param ui16Data is the data to be written to the PHY register.
+//!
+//! This function writes the \e ui16Data value to the PHY register specified by
+//! \e ui8RegAddr.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr,
+             uint16_t ui16Data)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui8PhyAddr < 32);
+
+    //
+    // Make sure the MII is idle.
+    //
+    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
+    {
+    }
+
+    //
+    // Write the value provided.
+    //
+    HWREG(ui32Base + EMAC_O_MIIDATA) = ui16Data;
+
+    //
+    // Tell the MAC to write the given PHY register.
+    //
+    HWREG(ui32Base + EMAC_O_MIIADDR) =
+        ((HWREG(ui32Base + EMAC_O_MIIADDR) &
+          EMAC_MIIADDR_CR_M) | (ui8RegAddr << EMAC_MIIADDR_MII_S) |
+         (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIW |
+         EMAC_MIIADDR_MIIB);
+
+    //
+    // Wait for the write to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads from a PHY register.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to access.
+//! \param ui8RegAddr is the address of the PHY register to be accessed.
+//!
+//! This function returns the contents of the PHY register specified by
+//! \e ui8RegAddr.
+//!
+//! \return Returns the 16-bit value read from the PHY.
+//
+//*****************************************************************************
+uint16_t
+EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui8PhyAddr < 32);
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Make sure the MII is idle.
+    //
+    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
+    {
+    }
+
+    //
+    // Tell the MAC to read the given PHY register.
+    //
+    HWREG(ui32Base + EMAC_O_MIIADDR) =
+        ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
+         (ui8RegAddr << EMAC_MIIADDR_MII_S) |
+         (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
+
+    //
+    // Wait for the read to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
+    {
+    }
+
+    //
+    // Return the result.
+    //
+    return(HWREG(ui32Base + EMAC_O_MIIDATA) & EMAC_MIIDATA_DATA_M);
+}
+
+//*****************************************************************************
+//
+//! Reads from an extended PHY register.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to access.
+//! \param ui16RegAddr is the address of the PHY extended register to be
+//! accessed.
+//!
+//! When using the internal PHY or when connected to an external PHY
+//! supporting extended registers, this function returns the contents of the
+//! extended PHY register specified by \e ui16RegAddr.
+//!
+//! \return Returns the 16-bit value read from the PHY.
+//
+//*****************************************************************************
+uint16_t
+EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                    uint16_t ui16RegAddr)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui8PhyAddr < 32);
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Set the address of the register we're about to read.
+    //
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F);
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr);
+
+    //
+    // Read the extended register value.
+    //
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F);
+    return(EMACPHYRead(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to an extended PHY register.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to access.
+//! \param ui16RegAddr is the address of the PHY extended register to be
+//! accessed.
+//! \param ui16Value is the value to write to the register.
+//!
+//! When using the internal PHY or when connected to an external PHY
+//! supporting extended registers, this function allows a value to be written
+//! to the extended PHY register specified by \e ui16RegAddr.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                     uint16_t ui16RegAddr, uint16_t ui16Value)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui8PhyAddr < 32);
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Set the address of the register we're about to write.
+    //
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F);
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr);
+
+    //
+    // Write the extended register.
+    //
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F);
+    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16Value);
+}
+
+//*****************************************************************************
+//
+//! Powers off the Ethernet PHY.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to power down.
+//!
+//! This function powers off the Ethernet PHY, reducing the current
+//! consumption of the device.  While in the powered-off state, the Ethernet
+//! controller is unable to connect to Ethernet.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr)
+{
+    //
+    // Set the PWRDN bit and clear the ANEN bit in the PHY, putting it into
+    // its low power mode.
+    //
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR,
+                 (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) &
+                  ~EPHY_BMCR_ANEN) | EPHY_BMCR_PWRDWN);
+}
+
+//*****************************************************************************
+//
+//! Powers on the Ethernet PHY.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to power up.
+//!
+//! This function powers on the Ethernet PHY, enabling it return to normal
+//! operation.  By default, the PHY is powered on, so this function is only
+//! called if EMACPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr)
+{
+    //
+    // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into
+    // normal operating mode.
+    //
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR,
+                 (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) &
+                  ~EPHY_BMCR_PWRDWN) | EPHY_BMCR_ANEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the Ethernet MAC's IEEE 1588 timestamping options.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Config contains flags selecting particular configuration
+//! options.
+//! \param ui32SubSecondInc is the number that the IEEE 1588 subsecond clock
+//! should increment on each tick.
+//!
+//! This function is used to configure the operation of the Ethernet MAC's
+//! internal timestamping clock.  This clock is used to timestamp incoming
+//! and outgoing packets and as an accurate system time reference when
+//! IEEE 1588 Precision Time Protocol is in use.
+//!
+//! The \e ui32Config parameter contains a collection of flags selecting the
+//! desired options.  Valid flags are:
+//!
+//! One of the following to determine whether IEEE 1588 version 1 or version 2
+//! packet format is to be processed:
+//!
+//! - \b EMAC_TS_PTP_VERSION_2
+//! - \b EMAC_TS_PTP_VERSION_1
+//!
+//! One of the following to determine how the IEEE 1588 clock's subsecond
+//! value should be interpreted and handled:
+//!
+//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll
+//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered
+//! as a nanosecond counter with each digit representing 1 ns.
+//! - \b EMAC_TS_BINARY_ROLLOVER causes the clock's subsecond value to roll
+//! over at 0x7FFFFFFF.  In this mode, the subsecond value counts 0.465 ns
+//! periods.
+//!
+//! One of the following to enable or disable MAC address filtering. When
+//! enabled, PTP frames are filtered unless the destination MAC address matches
+//! any of the currently programmed MAC addresses.
+//!
+//! - \b EMAC_TS_MAC_FILTER_ENABLE
+//! - \b EMAC_TS_MAC_FILTER_DISABLE
+//!
+//! One of the following to determine how the clock is updated:
+//! - \b EMAC_TS_UPDATE_COARSE causes the IEEE 1588 clock to advance by
+//! the value supplied in the \e ui32SubSecondInc parameter on each main
+//! oscillator clock cycle.
+//! - \b EMAC_TS_UPDATE_FINE selects the fine update method which causes the
+//! IEEE 1588 clock to advance by the the value supplied in the
+//! \e ui32SubSecondInc parameter each time a carry is generated from the
+//! addend accumulator register.
+//!
+//! One of the following to determine which IEEE 1588 messages are timestamped:
+//!
+//! - \b EMAC_TS_SYNC_FOLLOW_DREQ_DRESP timestamps SYNC, Follow_Up, Delay_Req
+//!   and Delay_Resp messages.
+//! - \b EMAC_TS_SYNC_ONLY timestamps only SYNC messages.
+//! - \b EMAC_TS_DELAYREQ_ONLY timestamps only Delay_Req messages.
+//! - \b EMAC_TS_ALL timestamps all IEEE 1588 messages.
+//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and
+//!   Pdelay_Resp messages.
+//! - \b EMAC_TS_DREQ_PDREQ_PDRESP timestamps only Delay_Req, Pdelay_Req and
+//!   Pdelay_Resp messages.
+//! - \b EMAC_TS_SYNC_DELAYREQ timestamps only Delay_Req messages.
+//! - \b EMAC_TS_PDREQ_PDRESP timestamps only Pdelay_Req and Pdelay_Resp
+//!   messages.
+//!
+//! Optional, additional flags are:
+//!
+//! - \b EMAC_TS_PROCESS_IPV4_UDP processes PTP packets encapsulated in UDP
+//!   over IPv4 packets.  If absent, the MAC ignores these frames.
+//! - \b EMAC_TS_PROCESS_IPV6_UDP processes PTP packets encapsulated in UDP
+//!   over IPv6 packets.  If absent, the MAC ignores these frames.
+//! - \b EMAC_TS_PROCESS_ETHERNET processes PTP packets encapsulated directly
+//!   in Ethernet frames.  If absent, the MAC ignores these frames.
+//! - \b EMAC_TS_ALL_RX_FRAMES enables timestamping for all frames received
+//!   by the MAC, regardless of type.
+//!
+//! The \e ui32SubSecondInc controls the rate at which the timestamp clock's
+//! subsecond count increments.  Its meaning depends on which of \b
+//! EMAC_TS_DIGITAL_ROLLOVER or \b EMAC_TS_BINARY_ROLLOVER and
+//! \b EMAC_TS_UPDATE_FINE or \b EMAC_TS_UPDATE_COARSE were included
+//! in \e ui32Config.
+//!
+//! The timestamp second counter is incremented each time the subsecond counter
+//! rolls over.  In digital rollover mode, the subsecond counter acts as a
+//! simple 31-bit counter, rolling over to 0 after reaching 0x7FFFFFFF.  In
+//! this case, each lsb of the subsecond counter represents 0.465 ns (assuming
+//! the definition of 1 second resolution for the seconds counter).  When
+//! binary rollover mode is selected, the subsecond counter acts as a 
+//! nanosecond counter and rolls over to 0 after reaching 999,999,999 making
+//! each lsb represent 1 nanosecond.
+//!
+//! In coarse update mode, the timestamp subsecond counter is incremented by
+//! \e ui32SubSecondInc on each main oscillator clock tick.  Setting
+//! \e ui32SubSecondInc to the main oscillator clock period in either 1 ns or
+//! 0.465 ns units ensures that the time stamp, read as seconds and
+//! subseconds, increments at the same rate as the main oscillator clock.  For
+//! example, if the main oscillator is 25 MHz, \e ui32SubSecondInc is set to 40
+//! if digital rollover mode is selected or (40 / 0.465) = 86 in binary
+//! rollover mode.
+//!
+//! In fine update mode, the subsecond increment value must be set according
+//! to the desired accuracy of the recovered IEEE 1588 clock which must be
+//! lower than the system clock rate.  Fine update mode is typically used when
+//! synchronizing the local clock to the IEEE 1588 master clock.  The subsecond
+//! counter is incremented by \e ui32SubSecondInc counts each time a 32-bit
+//! accumulator register generates a carry.  The accumulator register is
+//! incremented by the addend value on each main oscillator tick and this
+//! addend value is modified to allow fine control over the rate of change of
+//! the timestamp counter.  The addend value is calculated using the ratio of
+//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the
+//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588
+//! clock rate.  As an example, using digital rollover mode and a 25-MHz
+//! main oscillator clock with a desired IEEE 1588 clock accuracy of 12.5 MHz,
+//! we would set \e ui32SubSecondInc to the 12.5-MHz clock period of 80 ns and
+//! set the initial addend value to 0x80000000 to generate a carry on every
+//! second system clock.
+//!
+//! \sa EMACTimestampAddendSet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                       uint32_t ui32SubSecondInc)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Ensure that the PTP module clock is enabled.
+    //
+    HWREG(ui32Base + EMAC_O_CC) |= EMAC_CC_PTPCEN;
+
+    //
+    // Write the subsecond increment value.
+    //
+    HWREG(ui32Base + EMAC_O_SUBSECINC) = ((ui32SubSecondInc <<
+                                           EMAC_SUBSECINC_SSINC_S) &
+                                          EMAC_SUBSECINC_SSINC_M);
+
+    //
+    // Set the timestamp configuration.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Returns the current IEEE 1588 timestamping configuration.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pui32SubSecondInc points to storage that is written with the
+//! current subsecond increment value for the IEEE 1588 clock.
+//!
+//! This function may be used to retreive the current MAC timestamping
+//! configuration.
+//!
+//! \sa EMACTimestampConfigSet()
+//!
+//! \return Returns the current timestamping configuration as a logical OR of
+//! the following flags:
+//!
+//! - \b EMAC_TS_PTP_VERSION_2 indicates that the MAC is processing PTP
+//! version 2 messages.  If this flag is absent, PTP version 1 messages are
+//! expected.
+//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll
+//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered
+//! as a nanosecond counter with each digit representing 1 ns.  If this flag is
+//! absent, the subsecond value rolls over at 0x7FFFFFFF, effectively counting
+//! increments of 0.465 ns.
+//! - \b EMAC_TS_MAC_FILTER_ENABLE indicates that incoming PTP messages
+//! are filtered using any of the configured MAC addresses.  Messages with a
+//! destination address programmed into the MAC address filter are passed,
+//! others are discarded.  If this flag is absent, the MAC address is ignored.
+//! - \b EMAC_TS_UPDATE_FINE implements the fine update method that causes the 
+//! IEEE 1588 clock to advance by the the value returned in the
+//! \e *pui32SubSecondInc parameter each time a carry is generated from the
+//! addend accumulator register.  If this flag is absent, the coarse update
+//! method is in use and the clock is advanced by the \e *pui32SubSecondInc
+//! value on each system clock tick.
+//! - \b EMAC_TS_SYNC_ONLY indicates that timestamps are only generated for
+//! SYNC messages.
+//! - \b EMAC_TS_DELAYREQ_ONLY indicates that timestamps are only generated
+//! for Delay_Req messages.
+//! - \b EMAC_TS_ALL indicates that timestamps are generated for all
+//! IEEE 1588 messages.
+//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and
+//! Pdelay_Resp messages.
+//! - \b EMAC_TS_DREQ_PDREQ_PDRESP indicates that timestamps are only
+//! generated for Delay_Req, Pdelay_Req and Pdelay_Resp messages.
+//! - \b EMAC_TS_SYNC_DELAYREQ indicates that timestamps are only generated
+//! for Delay_Req messages.
+//! - \b EMAC_TS_PDREQ_PDRESP indicates that timestamps are only generated
+//! for Pdelay_Req and Pdelay_Resp messages.
+//! - \b EMAC_TS_PROCESS_IPV4_UDP indicates that PTP packets encapsulated in
+//! UDP over IPv4 packets are being processed.  If absent, the MAC ignores
+//! these frames.
+//! - \b EMAC_TS_PROCESS_IPV6_UDP indicates that PTP packets encapsulated in
+//! UDP over IPv6 packets are being processed.  If absent, the MAC ignores
+//! these frames.
+//! - \b EMAC_TS_PROCESS_ETHERNET indicates that PTP packets encapsulated
+//! directly in Ethernet frames are being processd.  If absent, the MAC ignores
+//! these frames.
+//! - \b EMAC_TS_ALL_RX_FRAMES indicates that timestamping is enabled for all
+//! frames received by the MAC, regardless of type.
+//!
+//! If \b EMAC_TS_ALL_RX_FRAMES and none of the options specifying subsets
+//! of PTP packets to timestamp are set, the MAC is configured to timestamp
+//! SYNC, Follow_Up, Delay_Req and Delay_Resp messages only.
+//
+//*****************************************************************************
+uint32_t
+EMACTimestampConfigGet(uint32_t ui32Base, uint32_t *pui32SubSecondInc)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(pui32SubSecondInc);
+
+    //
+    // Read the current subsecond increment value.
+    //
+    *pui32SubSecondInc = (HWREG(ui32Base + EMAC_O_SUBSECINC) &
+                          EMAC_SUBSECINC_SSINC_M) >> EMAC_SUBSECINC_SSINC_S;
+
+    //
+    // Return the current timestamp configuration.
+    //
+    return(HWREG(ui32Base + EMAC_O_TIMSTCTRL));
+}
+
+//*****************************************************************************
+//
+//! Enables packet timestamping and starts the system clock running.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function is used to enable the system clock used to timestamp
+//! Ethernet frames and to enable that timestamping.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampEnable(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Enable IEEE 1588 timestamping.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSEN;
+
+    //
+    // If necessary, initialize the timestamping system.  This bit self-clears
+    // once the system time is loaded.  Only do this if initialization is not
+    // currently ongoing.
+    //
+    if(!(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT))
+    {
+        HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables packet timestamping and stops the system clock.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function is used to stop the system clock used to timestamp
+//! Ethernet frames and to disable timestamping.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampDisable(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Disable IEEE 1588 timestamping.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_TSEN;
+}
+
+//*****************************************************************************
+//
+//! Sets the current system time.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Seconds is the seconds value of the new system clock setting.
+//! \param ui32SubSeconds is the subseconds value of the new system clock
+//! setting.
+//!
+//! This function may be used to set the current system time.  The system
+//! clock is set to the value passed in the \e ui32Seconds and
+//! \e ui32SubSeconds parameters.
+//!
+//! The meaning of \e ui32SubSeconds depends on the current system time
+//! configuration.  If EMACTimestampConfigSet() was previously called with
+//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the
+//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was
+//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds,
+                        uint32_t ui32SubSeconds)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Write the new time to the system time update registers.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds;
+    HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds;
+
+    //
+    // Wait for any previous update to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT)
+    {
+        //
+        // Spin for a while.
+        //
+    }
+
+    //
+    // Force the system clock to reset.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT;
+}
+
+//*****************************************************************************
+//
+//! Gets the current system time.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pui32Seconds points to storage for the current seconds value.
+//! \param pui32SubSeconds points to storage for the current subseconds value.
+//!
+//! This function may be used to get the current system time.
+//!
+//! The meaning of \e ui32SubSeconds depends on the current system time
+//! configuration.  If EMACTimestampConfigSet() was previously called with
+//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the
+//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was
+//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds,
+                        uint32_t *pui32SubSeconds)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(pui32Seconds);
+    ASSERT(pui32SubSeconds);
+
+    //
+    // Read the two-part system time from the seconds and nanoseconds
+    // registers.  We do this in a way that should guard against us reading
+    // the registers across a nanosecond wrap.
+    //
+    do
+    {
+        *pui32Seconds = HWREG(ui32Base + EMAC_O_TIMSEC);
+        *pui32SubSeconds = HWREG(ui32Base + EMAC_O_TIMNANO);
+    }
+    while(*pui32SubSeconds > HWREG(ui32Base + EMAC_O_TIMNANO));
+}
+
+//*****************************************************************************
+//
+//! Adjusts the current system time upwards or downwards by a given amount.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Seconds is the seconds value of the time update to apply.
+//! \param ui32SubSeconds is the subseconds value of the time update to apply.
+//! \param bInc defines the direction of the update.
+//!
+//! This function may be used to adjust the current system time either upwards
+//! or downwards by a given amount.  The size of the adjustment is given by
+//! the \e ui32Seconds and \e ui32SubSeconds parameter and the direction
+//! by the \e bInc parameter.  When \e bInc is \e true, the system time is
+//! advanced by the interval given.  When it is \e false, the time is retarded
+//! by the interval.
+//!
+//! The meaning of \e ui32SubSeconds depends on the current system time
+//! configuration.  If EMACTimestampConfigSet() was previously called with
+//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the
+//! subsecond value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was
+//! specified instead, a subsecond bit represents 0.46 ns.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds,
+                           uint32_t ui32SubSeconds, bool bInc)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Write the new time to the system time update registers.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds;
+    HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds |
+                                        (bInc ? 0 : EMAC_TIMNANOU_ADDSUB);
+
+    //
+    // Wait for any previous update to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSUPDT)
+    {
+        //
+        // Spin for a while.
+        //
+    }
+
+    //
+    // Force the system clock to update by the value provided.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSUPDT;
+}
+
+//*****************************************************************************
+//
+//! Adjusts the system time update rate when using the fine correction method.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Increment is the number to add to the accumulator register on
+//! each tick of the 25-MHz main oscillator.
+//!
+//! This function is used to control the rate of update of the system time
+//! when in fine update mode.  Fine correction mode is selected if
+//! \e EMAC_TS_UPDATE_FINE is supplied in the \e ui32Config parameter passed
+//! to a previous call to EMACTimestampConfigSet().  Fine update mode is
+//! typically used when synchronizing the local clock to the IEEE 1588 master
+//! clock.  The subsecond counter is incremented by the number passed to
+//! EMACTimestampConfigSet() in the \e ui32SubSecondInc parameter each time a
+//! 32-bit accumulator register generates a carry.  The accumulator register is
+//! incremented by the "addend" value on each main oscillator tick, and this
+//! addend value is modified to allow fine control over the rate of change of
+//! the timestamp counter.  The addend value is calculated using the ratio of
+//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the
+//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588
+//! clock rate.
+//!
+//! As an example, using digital rollover mode and a 25-MHz main oscillator
+//! clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, and having made
+//! a previous call to EMACTimestampConfigSet() with \e ui32SubSecondInc set to
+//! the 12.5-MHz clock period of 80 ns, the initial \e ui32Increment value
+//! would be set to 0x80000000 to generate a carry on every second main
+//! oscillator tick.  Because the system time updates each time the accumulator
+//! overflows, small changes in the \e ui32Increment value can be used to very
+//! finely control the system time rate.
+//!
+//! \return None.
+//!
+//! \sa EMACTimestampConfigSet()
+//
+//*****************************************************************************
+void
+EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Increment)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    HWREG(ui32Base + EMAC_O_TIMADD) = ui32Increment;
+
+    //
+    // Wait for any previous update to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_ADDREGUP)
+    {
+        //
+        // Spin for a while.
+        //
+    }
+
+    //
+    // Force the system clock to update by the value provided.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_ADDREGUP;
+}
+
+//*****************************************************************************
+//
+//! Sets the target system time at which the next Ethernet timer interrupt is
+//! generated.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Seconds is the second value of the desired target time.
+//! \param ui32SubSeconds is the subseconds value of the desired target time.
+//!
+//! This function may be used to schedule an interrupt at some future time.
+//! The time reference for the function is the IEEE 1588 time as returned by
+//! EMACTimestampSysTimeGet().  To generate an interrupt when the system
+//! time exceeds a given value, call this function to set the desired time,
+//! then EMACTimestampTargetIntEnable() to enable the interrupt.  When the
+//! system time increments past the target time, an Ethernet interrupt with
+//! status \b EMAC_INT_TIMESTAMP is generated.
+//!
+//! The accuracy of the interrupt timing depends on the Ethernet timer
+//! update frequency and the subsecond increment value currently in use.  The
+//! interrupt is generated on the first timer increment that causes the
+//! system time to be greater than or equal to the target time set.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds,
+                       uint32_t ui32SubSeconds)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Wait for any previous write to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_TARGNANO) & EMAC_TARGNANO_TRGTBUSY)
+    {
+    }
+
+    //
+    // Write the new target time.
+    //
+    HWREG(ui32Base + EMAC_O_TARGSEC) = ui32Seconds;
+    HWREG(ui32Base + EMAC_O_TARGNANO) = ui32SubSeconds;
+}
+
+//*****************************************************************************
+//
+//! Enables the Ethernet system time interrupt.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be used after EMACTimestampTargetSet() to schedule an
+//! interrupt at some future time.  The time reference for the function is
+//! the IEEE 1588 time as returned by EMACTimestampSysTimeGet().  To generate
+//! an interrupt when the system time exceeds a given value, call this function
+//! to set the desired time, then EMACTimestampTargetIntEnable() to enable the
+//! interrupt.  When the system time increments past the target time, an
+//! Ethernet interrupt with status \b EMAC_INT_TIMESTAMP is generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampTargetIntEnable(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Set the bit to enable the timestamp target interrupt.  This bit clears
+    // automatically when the interrupt fires after which point, you must
+    // set a new target time and re-enable the interrupts.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_INTTRIG;
+}
+
+//*****************************************************************************
+//
+//! Disables the Ethernet system time interrupt.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be used to disable any pending Ethernet system time
+//! interrupt previously scheduled using calls to EMACTimestampTargetSet()
+//! and EMACTimestampTargetIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampTargetIntDisable(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Clear the bit to disable the timestamp target interrupt.  This bit 
+    // clears automatically when the interrupt fires, so it only must be
+    // disabled if you want to cancel a previously-set interrupt.
+    //
+    HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_INTTRIG;
+}
+
+//*****************************************************************************
+//
+//! Reads the status of the Ethernet system time interrupt.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! When an Ethernet interrupt occurs and \b EMAC_INT_TIMESTAMP is reported
+//! bu EMACIntStatus(), this function must be called to read and clear the
+//! timer interrupt status.
+//!
+//! \return The return value is the logical OR of the values
+//! \b EMAC_TS_INT_TS_SEC_OVERFLOW and \b EMAC_TS_INT_TARGET_REACHED.
+//!
+//! - \b EMAC_TS_INT_TS_SEC_OVERFLOW indicates that the second counter in the
+//! hardware timer has rolled over.
+//! - \b EMAC_TS_INT_TARGET_REACHED indicates that the system time incremented
+//! past the value set in an earlier call to EMACTimestampTargetSet().  When
+//! this occurs, a new target time may be set and the interrupt re-enabled
+//! using calls to EMACTimestampTargetSet() and
+//! EMACTimestampTargetIntEnable().
+//
+//*****************************************************************************
+uint32_t
+EMACTimestampIntStatus(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Return the current interrupt status from the timestamp module.
+    //
+    return(HWREG(ui32Base + EMAC_O_TIMSTAT));
+}
+
+//*****************************************************************************
+//
+//! Configures the Ethernet MAC PPS output in simple mode.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32FreqConfig determines the frequency of the output generated on
+//! the PPS pin.
+//!
+//! This function configures the Ethernet MAC PPS (Pulse Per Second) engine to
+//! operate in its simple mode which allows the generation of a few, fixed
+//! frequencies and pulse widths on the PPS pin.  If more complex pulse
+//! train generation is required, the MAC also provides a command-based
+//! PPS control mode that can be selected by calling
+//! EMACTimestampPPSCommandModeSet().
+//!
+//! The \e ui32FreqConfig parameter may take one of the following values:
+//!
+//! - \b EMAC_PPS_SINGLE_PULSE generates a single high pulse on the PPS
+//! output once per second.  The pulse width is the same as the system clock
+//! period.
+//! - \b EMAC_PPS_1HZ generates a 1Hz signal on the PPS output.  This option
+//! is not available if the system time subsecond counter is currently
+//! configured to operate in binary rollover mode.
+//! - \b EMAC_PPS_2HZ, \b EMAC_PPS_4HZ, \b EMAC_PPS_8HZ,
+//!   \b EMAC_PPS_16HZ, \b EMAC_PPS_32HZ, \b EMAC_PPS_64HZ,
+//!   \b EMAC_PPS_128HZ, \b EMAC_PPS_256HZ, \b EMAC_PPS_512HZ,
+//!   \b EMAC_PPS_1024HZ, \b EMAC_PPS_2048HZ, \b EMAC_PPS_4096HZ,
+//!   \b EMAC_PPS_8192HZ, \b EMAC_PPS_16384HZ generate the requested
+//! frequency on the PPS output in both binary and digital rollover modes.
+//! - \b EMAC_PPS_32768HZ generates a 32KHz signal on the PPS output.  This
+//! option is not available if the system time subsecond counter is currently
+//! configured to operate in digital rollover mode.
+//!
+//! Except when \b EMAC_PPS_SINGLE_PULSE is specified, the signal generated
+//! on PPS has a duty cycle of 50% when binary rollover mode is used for the
+//! system time subsecond count.  In digital mode, the output frequency
+//! averages the value requested and is resynchronized each second.  For
+//! example, if \b EMAC_PPS_4HZ is selected in digital rollover mode, the
+//! output generates three clocks with 50 percent duty cycle and 268 ms
+//! period followed by a fourth clock of 195 ms period, 134 ms low and 61 ms high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, uint32_t ui32FreqConfig)
+{
+    bool bDigital;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Are we currently running the clock in digital or binary rollover mode?
+    //
+    bDigital = (HWREG(ui32Base + EMAC_O_TIMSTCTRL) &
+                EMAC_TS_DIGITAL_ROLLOVER) ? true : false;
+
+    //
+    // Weed out some unsupported frequencies.  The hardware can't produce a
+    // 1Hz output when we are in binary rollover mode and can't produce a
+    // 32KHz output when we are digital rollover mode.
+    //
+    ASSERT(bDigital || (ui32FreqConfig != EMAC_PPS_1HZ));
+    ASSERT(!bDigital || (ui32FreqConfig != EMAC_PPS_32768HZ));
+
+    //
+    // Adjust the supplied frequency if we are currently in binary update mode
+    // where the control value generates an output that is twice as fast as
+    // in digital mode.
+    //
+    if((ui32FreqConfig != EMAC_PPS_SINGLE_PULSE) && !bDigital)
+    {
+        ui32FreqConfig--;
+    }
+
+    //
+    // Write the frequency control value to the PPS control register, clearing
+    // the PPSEN0 bit to ensure that the PPS engine is in simple mode and not
+    // waiting for a command.  We also clear the TRGMODS0 field to revert to
+    // the default operation of the target time registers.
+    //
+    HWREG(ui32Base + EMAC_O_PPSCTRL) = ui32FreqConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the Ethernet MAC PPS output in command mode.
+
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Config determines how the system target time is used.
+//!
+//! The simple mode of operation offered by the PPS (Pulse Per Second) engine
+//! may be too restrictive for some applications.  The second mode, however,
+//! allows complex pulse trains to be generated using commands that tell the
+//! engine to send individual pulses or start and stop trains if pulses.  In
+//! this mode, the pulse width and period may be set arbitrarily based on
+//! ticks of the clock used to update the system time.  Commands are triggered
+//! at specific times using the target time last set using a call to
+//! EMACTimestampTargetSet().
+//!
+//! The \e ui32Config parameter may be used to control whether the target
+//! time is used to trigger commands only or can also generate an interrupt
+//! to the CPU.  Valid values are:
+//!
+//! - \b EMAC_PPS_TARGET_INT configures the target time to only raise
+//! an interrupt and not to trigger any pending PPS command.
+//! - \b EMAC_PPS_TARGET_PPS configures the target time to trigger a pending
+//! PPS command but not raise an interrupt.
+//! - \b EMAC_PPS_TARGET_BOTH configures the target time to trigger any
+//! pending PPS command and also raise an interrupt.
+//!
+//! To use command mode, an application must call this function to enable the
+//! mode, then call:
+//!
+//! - EMACTimestampPPSPeriodSet() to set the desired pulse width and period
+//! then
+//! - EMACTimestampTargetSet() to set the time at which the next command is
+//! executed, and finally
+//! - EMACTimestampPPSCommand() to send a command to cause the pulse or
+//! pulse train to be started at the required time.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampPPSCommandModeSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(!(ui32Config & (EMAC_PPS_TARGET_INT | EMAC_PPS_TARGET_PPS |
+                           EMAC_PPS_TARGET_BOTH)));
+
+    //
+    // Wait for any previous command write to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M)
+    {
+        //
+        // Wait a bit.
+        //
+    }
+
+    //
+    // Write the configuration value to the PPS control register, setting the
+    // PPSEN0 bit to ensure that the PPS engine is in command mode and
+    // clearing the command in the PPSCTRL field.
+    //
+    HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui32Config);
+}
+
+//*****************************************************************************
+//
+//! Sends a command to control the PPS output from the Ethernet MAC.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8Cmd identifies the command to be sent.
+//!
+//! This function may be used to send a command to the MAC PPS (Pulse Per
+//! Second) controller when it is operating in command mode.  Command mode
+//! is selected by calling EMACTimestampPPSCommandModeSet(). Valid
+//! commands are as follow:
+//!
+//! - \b EMAC_PPS_COMMAND_NONE indicates no command.
+//! - \b EMAC_PPS_COMMAND_START_SINGLE indicates that a single high pulse
+//! should be generated when the system time reaches the current target time.
+//! - \b EMAC_PPS_COMMAND_START_TRAIN indicates that a train of pulses
+//! should be started when the system time reaches the current target time.
+//! - \b EMAC_PPS_COMMAND_CANCEL_START cancels any pending start command if
+//! the system time has not yet reached the programmed target time.
+//! - \b EMAC_PPS_COMMAND_STOP_AT_TIME indicates that the current pulse
+//! train should be stopped when the system time reaches the current target
+//! time.
+//! - \b EMAC_PPS_COMMAND_STOP_NOW indicates that the current pulse train
+//! should be stopped immediately.
+//! - \b EMAC_PPS_COMMAND_CANCEL_STOP cancels any pending stop command if
+//! the system time has not yet reached the programmed target time.
+//!
+//! In all cases, the width of the pulses generated is governed by the
+//! \e ui32Width parameter passed to EMACTimestampPPSPeriodSet().  If a
+//! command starts a train of pulses, the period of the pulses is governed
+//! by the \e ui32Period parameter passed to the same function.
+//! Target times associated with PPS commands are set by calling
+//! EMACTimestampTargetSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Wait for any previous command write to complete.
+    //
+    while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M)
+    {
+        //
+        // Wait a bit.
+        //
+    }
+
+    //
+    // Write the command to the PPS control register.
+    //
+    HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui8Cmd);
+}
+
+//*****************************************************************************
+//
+//! Sets the period and width of the pulses on the Ethernet MAC PPS output.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Period is the period of the PPS output expressed in terms of
+//! system time update ticks.
+//! \param ui32Width is the width of the high portion of the PPS output
+//! expressed in terms of system time update ticks.
+//!
+//! This function may be used to control the period and duty cycle of the
+//! signal output on the Ethernet MAC PPS pin when the PPS generator is
+//! operating in command mode and a command to send one or more pulses has been
+//! executed.  Command mode is selected by calling
+//! EMACTimestampPPSCommandModeSet().
+//!
+//! In simple mode, the PPS output signal frequency is controlled by the
+//! \e ui32FreqConfig parameter passed to EMACTimestampPPSSimpleModeSet().
+//!
+//! The \e ui32Period and \e ui32Width parameters are expressed in terms of
+//! system time update ticks.  When the system time is operating in coarse
+//! update mode, each tick is equivalent to the system clock.  In fine update
+//! mode, a tick occurs every time the 32-bit system time accumulator overflows
+//! and this, in turn, is determined by the value passed to the function
+//! EMACTimestampAddendSet().  Regardless of the tick source, each tick
+//! increments the actual system time, queried using EMACTimestampSysTimeGet()
+//! by the subsecond increment value passed in the \e ui32SubSecondInc to
+//! EMACTimestampConfigSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period,
+                          uint32_t ui32Width)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Write the desired PPS period and pulse width.
+    //
+    HWREG(ui32Base + EMAC_O_PPS0INTVL) = ui32Period;
+    HWREG(ui32Base + EMAC_O_PPS0WIDTH) = ui32Width;
+}
+
+//*****************************************************************************
+//
+//! Sets options related to reception of VLAN-tagged frames.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui16Tag is the IEEE 802.1Q VLAN tag expected for incoming frames.
+//! \param ui32Config determines how the receiver handles VLAN-tagged frames.
+//!
+//! This function configures the receiver's handling of IEEE 802.1Q VLAN
+//! tagged frames.  Incoming tagged frames are filtered using either a perfect
+//! filter or a hash filter.  When hash filtering is disabled, VLAN frames
+//! tagged with the value of \e ui16Tag pass the filter and all others are
+//! rejected.  The tag comparison may involve all 16 bits or only the 12-bit
+//! VLAN ID portion of the tag.
+//!
+//! The \e ui32Config parameter is a logical OR of the following values:
+//!
+//! - \b EMAC_VLAN_RX_HASH_ENABLE enables hash filtering for VLAN tags.  If
+//! this flag is absent, perfect filtering using the tag supplied in \e ui16Tag
+//! is performed.  The hash filter may be set using EMACVLANHashFilterSet(),
+//! and EMACVLANHashFilterBitCalculate() may be used to determine which bits
+//! to set in the filter for given VLAN tags.
+//! - \b EMAC_VLAN_RX_SVLAN_ENABLE causes the receiver to recognize S-VLAN
+//! (Type = 0x88A8) frames as valid VLAN-tagged frames.  If absent, only
+//! frames with type 0x8100 are considered valid VLAN frames.
+//! - \b EMAC_VLAN_RX_INVERSE_MATCH causes the receiver to pass all VLAN
+//! frames for which the tags do not match the supplied \e ui16Tag value.  If 
+//! this flag is absent, only tagged frames matching \e ui16Tag are passed.
+//! - \b EMAC_VLAN_RX_12BIT_TAG causes the receiver to compare only the
+//! bottom 12 bits of \e ui16Tag when performing either perfect or hash
+//! filtering of VLAN frames.  If this flag is absent, all 16 bits of the frame
+//! tag are examined when filtering.  If this flag is set and \e ui16Tag has
+//! all bottom 12 bits clear, the receiver passes all frames with types
+//! 0x8100 or 0x88A8 regardless of the tag values they contain.
+//!
+//! \note To ensure that VLAN frames that fail the tag filter are dropped
+//! by the MAC, EMACFrameFilterSet() must be called with the \b
+//! EMAC_FRMFILTER_VLAN flag set in the \e ui32FilterOpts parameter.  If
+//! this flag is not set, failing VLAN packets are received by the
+//! application, but bit 10 of RDES0 (\b EMAC_FRMFILTER_VLAN) is clear
+//! indicating that the packet did not match the current VLAG tag filter.
+//!
+//! \sa EMACVLANRxConfigGet()
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Write the VLAN tag register.
+    //
+    HWREG(ui32Base + EMAC_O_VLANTG) =
+        ui32Config | (((uint32_t)ui16Tag) << EMAC_VLANTG_VL_S);
+}
+
+//*****************************************************************************
+//
+//! Returns the currently-set options related to reception of VLAN-tagged
+//! frames.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pui16Tag points to storage which is written with the currently
+//! configured VLAN tag used for perfect filtering.
+//!
+//! This function returns information on how the receiver is currently
+//! handling IEEE 802.1Q VLAN-tagged frames.
+//!
+//! \sa EMACVLANRxConfigSet()
+//!
+//! \return Returns flags defining how VLAN-tagged frames are handled.  The
+//! value is a logical OR of the following flags:
+//!
+//! - \b EMAC_VLAN_RX_HASH_ENABLE indicates that hash filtering is enabled
+//! for VLAN tags.  If this flag is absent, perfect filtering using the tag
+//! returned in \e *pui16Tag is performed.
+//! - \b EMAC_VLAN_RX_SVLAN_ENABLE indicates that the receiver recognizes
+//! S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames.  If absent, only
+//! frames with type 0x8100 are considered valid VLAN frames.
+//! - \b EMAC_VLAN_RX_INVERSE_MATCH indicates that the receiver passes all
+//! VLAN frames for which the tags do not match the \e *pui16Tag value.  If 
+//! this flag is absent, only tagged frames matching \e *pui16Tag are passed.
+//! - \b EMAC_VLAN_RX_12BIT_TAG indicates that the receiver is comparing only
+//! the bottom 12 bits of \e *pui16Tag when performing either perfect or hash
+//! filtering of VLAN frames.  If this flag is absent, all 16 bits of the frame
+//! tag are examined when filtering.  If this flag is set and \e *pui16Tag has
+//! all bottom 12 bits clear, the receiver passes all frames with types
+//! 0x8100 or 0x88A8 regardless of the tag values they contain.
+//
+//*****************************************************************************
+uint32_t
+EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag)
+{
+    uint32_t ui32Value;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(pui16Tag);
+
+    //
+    // Read the VLAN tag register.
+    //
+    ui32Value = HWREG(ui32Base + EMAC_O_VLANTG);
+
+    //
+    // Extract the VLAN tag from the register.
+    //
+    *pui16Tag = (ui32Value & EMAC_VLANTG_VL_M) >> EMAC_VLANTG_VL_S;
+
+    //
+    // Return the configuration flags.
+    //
+    return(ui32Value & ~EMAC_VLANTG_VL_M);
+}
+
+//*****************************************************************************
+//
+//! Sets options related to transmission of VLAN-tagged frames.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui16Tag is the VLAN tag to be used when inserting or replacing tags
+//! in transmitted frames.
+//! \param ui32Config determines the VLAN-related processing performed by
+//! the transmitter.
+//!
+//! This function is used to configure transmitter options relating to
+//! IEEE 802.1Q VLAN tagging.  The transmitter may be set to insert tagging
+//! into untagged frames or replace existing tags with new values.
+//!
+//! The \e ui16Tag parameter contains the VLAN tag to be used in outgoing
+//! tagged frames.  The \e ui32Config parameter is a logical OR of the
+//! following labels:
+//!
+//! - \b EMAC_VLAN_TX_SVLAN uses the S-VLAN type (0x88A8) when inserting or
+//! replacing tags in transmitted frames.  If this label is absent, C-VLAN
+//! type (0x8100) is used.
+//! - \b EMAC_VLAN_TX_USE_VLC informs the transmitter that the VLAN tag
+//! handling should be defined by the VLAN control (VLC) value provided in
+//! this function call.  If this tag is absent, VLAN handling is controlled
+//! by fields in the transmit descriptor.
+//!
+//! If \b EMAC_VLAN_TX_USE_VLC is set, one of the following four labels
+//! must also be included to define the transmit VLAN tag handling:
+//!
+//! - \b EMAC_VLAN_TX_VLC_NONE instructs the transmitter to perform no VLAN
+//! tag insertion, deletion or replacement.
+//! - \b EMAC_VLAN_TX_VLC_DELETE instructs the transmitter to remove VLAN
+//! tags from all transmitted frames that contain them.  As a result, bytes
+//! 13, 14, 15 and 16 are removed from all frames with types 0x8100 or 0x88A8.
+//! - \b EMAC_VLAN_TX_VLC_INSERT instructs the transmitter to insert a VLAN
+//! type and tag into all outgoing frames regardless of whether or not they
+//! already contain a VLAN tag.
+//! - \b EMAC_VLAN_TX_VLC_REPLACE instructs the transmitter to replace the
+//! VLAN tag in all frames of type 0x8100 or 0x88A8 with the value provided to
+//! this function in the \e ui16Tag parameter.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Write the VLAN Tag Inclusion or Replacement register.
+    //
+    HWREG(ui32Base + EMAC_O_VLNINCREP) =
+        ui32Config | ((uint32_t)ui16Tag << EMAC_VLNINCREP_VLT_S);
+}
+
+//*****************************************************************************
+//
+//! Returns currently-selected options related to transmission of VLAN-tagged
+//! frames.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pui16Tag points to storage that is written with the VLAN tag
+//! currently being used for insertion or replacement.
+//!
+//! This function returns information on the current settings related to VLAN
+//! tagging of transmitted frames.
+//!
+//! \sa EMACVLANTxConfigSet()
+//!
+//! \return Returns flags describing the current VLAN configuration relating
+//! to frame transmission.  The return value is a logical OR of the following
+//! values:
+//!
+//! - \b EMAC_VLAN_TX_SVLAN indicates that the S-VLAN type (0x88A8) is
+//! being used when inserting or replacing tags in transmitted frames.  If
+//! this label is absent, C-VLAN type (0x8100) is being used.
+//! - \b EMAC_VLAN_TX_USE_VLC indicates that the transmitter is processing
+//! VLAN frames according to the VLAN control (VLC) value returned here.  If
+//! this tag is absent, VLAN handling is controlled by fields in the transmit
+//! descriptor.
+//!
+//! If \b EMAC_VLAN_TX_USE_VLC is returned, one of the following four labels
+//! is also included to define the transmit VLAN tag handling.  Note that this
+//! value may be extracted from the return value using the mask \b
+//! EMAC_VLAN_TX_VLC_MASK.
+//!
+//! - \b EMAC_VLAN_TX_VLC_NONE indicates that the transmitter is not
+//! performing VLAN tag insertion, deletion or replacement.
+//! - \b EMAC_VLAN_TX_VLC_DELETE indicates that the transmitter is removing
+//! VLAN tags from all transmitted frames which contain them.
+//! - \b EMAC_VLAN_TX_VLC_INSERT indicates that the transmitter is inserting
+//! a VLAN type and tag into all outgoing frames regardless of whether or not
+//! they already contain a VLAN tag.
+//! - \b EMAC_VLAN_TX_VLC_REPLACE indicates that the transmitter is replacing
+//! the VLAN tag in all transmitted frames of type 0x8100 or 0x88A8 with the
+//! value returned in \e *pui16Tag.
+//
+//*****************************************************************************
+uint32_t
+EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag)
+{
+    uint32_t ui32Value;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(pui16Tag);
+
+    //
+    // Read the VLAN Tag Inclusion or Replacement register.
+    //
+    ui32Value = HWREG(ui32Base + EMAC_O_VLNINCREP);
+
+    //
+    // Extract the tag.
+    //
+    *pui16Tag = (uint16_t)((ui32Value & EMAC_VLNINCREP_VLT_M) >>
+                           EMAC_VLNINCREP_VLT_S);
+
+    //
+    // Return the configuration flags.
+    //
+    return(ui32Value & ~EMAC_VLNINCREP_VLT_M);
+}
+
+//*****************************************************************************
+//
+//! Returns the bit number to set in the VLAN hash filter corresponding to a
+//! given tag.
+//!
+//! \param ui16Tag is the VLAN tag for which the hash filter bit number is to 
+//! be determined.
+//!
+//! This function may be used to determine which bit in the VLAN hash filter
+//! to set to describe a given 12- or 16-bit VLAN tag.  The returned value is
+//! a 4-bit value indicating the bit number to set within the 16-bit VLAN
+//! hash filter. For example, if 0x02 is returned, this indicates that bit
+//! 2 of the hash filter must be set to pass the supplied VLAN tag.
+//!
+//! \return Returns the bit number to set in the VLAN hash filter to describe
+//! the passed tag.
+//
+//*****************************************************************************
+uint32_t
+EMACVLANHashFilterBitCalculate(uint16_t ui16Tag)
+{
+    uint32_t ui32CRC, ui32Mask, ui32Loop;
+
+    //
+    // Calculate the CRC for the MAC address.
+    //
+    ui32CRC = Crc32(0xFFFFFFFF, (uint8_t *)&ui16Tag, 2);
+    ui32CRC ^= 0xFFFFFFFF;
+
+    //
+    // Determine the hash bit to use from the calculated CRC.  This is the
+    // top 4 bits of the reversed CRC (or the bottom 4 bits of the calculated
+    // CRC with the bit order of those 4 bits reversed).
+    //
+    ui32Mask = 0;
+
+    //
+    // Reverse the order of the bottom 4 bits of the calculated CRC.
+    //
+    for(ui32Loop = 0; ui32Loop < 4; ui32Loop++)
+    {
+        ui32Mask <<= 1;
+        ui32Mask |= (ui32CRC & 1);
+        ui32CRC >>= 1;
+    }
+
+    //
+    // Return the final hash filter bit index.
+    //
+    return(ui32Mask);
+}
+
+//*****************************************************************************
+//
+//! Sets the hash filter used to control reception of VLAN-tagged frames.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Hash is the hash filter value to set.
+//!
+//! This function allows the VLAG tag hash filter to be set.  By using hash
+//! filtering, several different VLAN tags can be filtered very easily at the
+//! cost of some false positive results that must be removed by software.
+//!
+//! The hash filter value passed in \e ui32Hash may be built up by calling
+//! EMACVLANHashFilterBitCalculate() for each VLAN tag that is to pass the
+//! filter and then set each of the bits for which the numbers are returned by
+//! that function.  Care must be taken when clearing bits in the hash filter
+//! due to the fact that there is a many-to-one correspondence between VLAN
+//! tags and hash filter bits.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Write the VLAN Hash Table register.
+    //
+    HWREG(ui32Base + EMAC_O_VLANHASH) = ui32Hash;
+}
+
+//*****************************************************************************
+//
+//! Returns the current value of the hash filter used to control reception of
+//! VLAN-tagged frames.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function allows the current VLAN tag hash filter value to be returned.
+//! Additional VLAN tags may be added to this filter by setting the appropriate
+//! bits, determined by calling EMACVLANHashFilterBitCalculate(), and then
+//! calling EMACVLANHashFilterSet() to set the new filter value.
+//!
+//! \return Returns the current value of the VLAN hash filter.
+//
+//*****************************************************************************
+uint32_t
+EMACVLANHashFilterGet(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Return the VLAN Hash Table register.
+    //
+    return(HWREG(ui32Base + EMAC_O_VLANHASH));
+}
+
+//*****************************************************************************
+//
+//! Sets values defining up to four frames used to trigger a remote wake-up.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pFilter points to the structure containing remote wake-up frame
+//! filter information.
+//!
+//! This function may be used to define up to four different frames that
+//! are considered by the Ethernet MAC to be remote wake-up signals.  The
+//! data passed to the function describes a wake-up frame in terms of a CRC
+//! calculated on up to 31 payload bytes in the frame.  The actual bytes used
+//! in the CRC calculation are defined by means of a bit mask where a ``1''
+//! indicates that a byte in the frame should contribute to the CRC
+//! calculation and a ``0'' indicates that the byte should be skipped, as well 
+//! as an offset from the start of the frame to the payload byte that represents 
+//! the first byte in the 31-byte CRC-checked sequence.
+//!
+//! The \e pFilter parameter points to a structure containing the information
+//! necessary to set up the filters.  This structure contains the following
+//! fields, each of which is replicated 4 times, once for each possible wake-up
+//! frame:
+//!
+//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte
+//! sequence within the frame should contribute to the CRC calculation or not.
+//! A 1 indicates that the byte should contribute to the calculation, a 0
+//! causes the byte to be skipped.
+//! - \b pui8Command contains flags defining whether this filter is enabled
+//! and, if so, whether it refers to unicast or multicast packets.  Valid
+//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b
+//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or
+//! \b EMAC_RWU_FILTER_DISABLE.
+//! - \b pui8Offset defines the zero-based index of the byte within the frame
+//! at which CRC checking defined by \b pui32ByteMask begins.
+//! Alternatively, this value can be thought of as the number of bytes in the
+//! frame that the MAC skips before accumulating the CRC based on the pattern  
+//! in \b pui32ByteMask.
+//! - \b pui16CRC provides the value of the calculated CRC for a valid remote
+//! wake-up frame.  If the incoming frame is processed according to the filter
+//! values provided and the final CRC calculation equals this value, the
+//! frame is considered to be a valid remote wake-up frame.
+//!
+//! Note that this filter uses CRC16 rather than CRC32 as used in frame
+//! checksums. The required CRC uses a direct algorithm with polynomial 0x8005,
+//! initial seed value 0xFFFF, no final XOR and reversed data order.  CRCs
+//! for use in this function may be determined using the online calculator
+//! found at http://www.zorc.breitbandkatze.de/crc.html.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base,
+                               const tEMACWakeUpFrameFilter *pFilter)
+{
+    uint32_t *pui32Data;
+    uint32_t ui32Loop;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(pFilter);
+
+    //
+    // Make sure that the internal register counter for the frame filter
+    // is reset.  This bit automatically resets after 1 clock cycle.
+    //
+    HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST;
+
+    //
+    // Get a word pointer to the supplied structure.
+    //
+    pui32Data = (uint32_t *)pFilter;
+
+    //
+    // Write the 8 words of the wake-up filter definition to the hardware.
+    //
+    for(ui32Loop = 0; ui32Loop < 8; ui32Loop++)
+    {
+        //
+        // Write a word of the filter definition.
+        //
+        HWREG(ui32Base + EMAC_O_RWUFF) = pui32Data[ui32Loop];
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the current remote wake-up frame filter configuration.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param pFilter points to the structure that is written with the current
+//! remote wake-up frame filter information.
+//!
+//! This function may be used to read the current wake-up frame filter
+//! settings.  The data returned by the function describes wake-up frames in
+//! terms of a CRC calculated on up to 31 payload bytes in the frame.  The
+//! actual bytes used in the CRC calculation are defined by means of a bit mask
+//! where a ``1'' indicates that a byte in the frame should contribute to the
+//! CRC calculation and a ``0'' indicates that the byte should be skipped, and
+//! an offset from the start of the frame to the payload byte that represents 
+//! the first byte in the 31-byte CRC-checked sequence.
+//!
+//! The \e pFilter parameter points to storage that is written with a
+//! structure containing the information defining the frame filters.  This
+//! structure contains the following fields, each of which is replicated 4
+//! times, once for each possible wake-up frame:
+//!
+//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte
+//! sequence within the frame should contribute to the CRC calculation or not.
+//! A 1 indicates that the byte should contribute to the calculation, a 0
+//! causes the byte to be skipped.
+//! - \b pui8Command contains flags defining whether this filter is enabled
+//! and, if so, whether it refers to unicast or multicast packets.  Valid
+//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b
+//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or
+//! \b EMAC_RWU_FILTER_DISABLE.
+//! - \b pui8Offset defines the zero-based index of the byte within the frame
+//! at which CRC checking defined by \b pui32ByteMask begins.
+//! Alternatively, this value can be thought of as the number of bytes in the
+//! frame that the MAC skips before accumulating the CRC based on the pattern
+//! in \b pui32ByteMask.
+//! - \b pui16CRC provides the value of the calculated CRC for a valid remote
+//! wake-up frame.  If the incoming frame is processed according to the filter
+//! values provided and the final CRC calculation equals this value, the
+//! frame is considered to be a valid remote wake-up frame.
+//!
+//! Note that this filter uses CRC16 rather than CRC32 as used in frame
+//! checksums.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base,
+                               tEMACWakeUpFrameFilter *pFilter)
+{
+    uint32_t *pui32Data;
+    uint32_t ui32Loop;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(pFilter);
+
+    //
+    // Make sure that the internal register counter for the frame filter
+    // is reset.  This bit automatically resets after 1 clock cycle.
+    //
+    HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST;
+
+    //
+    // Get a word pointer to the supplied structure.
+    //
+    pui32Data = (uint32_t *)pFilter;
+
+    //
+    // Read the 8 words of the wake-up filter definition from the hardware.
+    //
+    for(ui32Loop = 0; ui32Loop < 8; ui32Loop++)
+    {
+        //
+        // Read a word of the filter definition.
+        //
+        pui32Data[ui32Loop] = HWREG(ui32Base + EMAC_O_RWUFF);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the Ethernet MAC remote wake-up configuration.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Flags defines which types of frame should trigger a remote
+//! wake-up and allows the MAC to be put into power-down mode.
+//!
+//! This function allows the MAC's remote wake-up features to be configured,
+//! determining which types of frame should trigger a wake-up event and
+//! allowing an application to place the MAC in power-down mode.  In this
+//! mode, the MAC ignores all received frames until one matching a
+//! configured remote wake-up frame is received, at which point the MAC
+//! automatically exits power-down mode and continues to receive frames.
+//!
+//! The \e ui32Flags parameter is a logical OR of the following flags:
+//!
+//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE instructs the MAC to wake up when any
+//! unicast frame matching the MAC destination address filter is received.
+//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE instructs the MAC to wake up when any
+//! received frame matches the remote wake-up filter configured via a call
+//! to EMACRemoteWakeUpFrameFilterSet().
+//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE instructs the MAC to wake up when a
+//! standard Wake-on-LAN "magic packet" is received.  The magic packet contains
+//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination
+//! MAC address.
+//! - \b EMAC_PMT_POWER_DOWN instructs the MAC to enter power-down mode and
+//! wait for an incoming frame matching the remote wake-up frames as described
+//! by other flags and via the remote wake-up filter.  This flag should only
+//! set set if at least one other flag is specified to configure a wake-up
+//! frame type.
+//!
+//! When the MAC is in power-down mode, software may exit the mode by calling
+//! this function with the \b EMAC_PMT_POWER_DOWN flag absent from \e ui32Flags.
+//! If a configured wake-up frame is received while in power-down mode, the
+//! \b EMAC_INT_POWER_MGMNT interrupt is signaled and may be cleared by reading
+//! the status using EMACPowerManagementStatusGet().
+//!
+//! \note While it is possible to gate the clock to the MAC while it is in
+//! power-down mode, doing so prevents the reading of the registers required
+//! to determine the interrupt status and also prevents power-down mode from
+//! exiting via another call to this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPowerManagementControlSet(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    uint32_t ui32Value;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    ASSERT(~(ui32Flags & ~(EMAC_PMT_GLOBAL_UNICAST_ENABLE |
+                           EMAC_PMT_WAKEUP_PACKET_ENABLE |
+                           EMAC_PMT_MAGIC_PACKET_ENABLE |
+                           EMAC_PMT_POWER_DOWN)));
+
+    //
+    // Read the control/status register, clear all the bits we can set, mask
+    // in the new values then rewrite the new register value.
+    //
+    ui32Value = HWREG(ui32Base + EMAC_O_PMTCTLSTAT);
+    ui32Value &= ~(EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN |
+                   EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN);
+    ui32Value |= ui32Flags;
+    HWREG(ui32Base + EMAC_O_PMTCTLSTAT) = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! Queries the current Ethernet MAC remote wake-up configuration.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function allows the MAC's remote wake-up settings to be queried.
+//! These settings determine which types of frame should trigger a remote
+//! wake-up event
+//!
+//! \return Returns a logical OR of the following flags:
+//!
+//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE indicates that the MAC wakes up when
+//! any unicast frame matching the MAC destination address filter is received.
+//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE indicates that the MAC wakes up when any
+//! received frame matches the remote wake-up filter configured via a call
+//! to EMACRemoteWakeUpFrameFilterSet().
+//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE indicates that the MAC wakes up when a
+//! standard Wake-on-LAN "magic packet" is received.  The magic packet contains
+//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination
+//! MAC address.
+//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down
+//! mode and is  waiting for an incoming frame matching the remote wake-up
+//! frames as described by other returned flags and via the remote wake-up
+//! filter.
+//
+//*****************************************************************************
+uint32_t
+EMACPowerManagementControlGet(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Read the control/status register and mask off the control bits to return
+    // them to the caller.
+    //
+    return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) &
+           (EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN |
+            EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN));
+}
+
+//*****************************************************************************
+//
+//! Queries the current Ethernet MAC remote wake-up status.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function returns information on the remote wake-up state of the
+//! Ethernet MAC. If the MAC has been woken up since the last call, the
+//! returned value indicates the type of received frame that caused the MAC
+//! to exit power-down state.
+//!
+//! \return Returns a logical OR of the following flags:
+//!
+//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down
+//! mode.
+//! - \b EMAC_PMT_WAKEUP_PACKET_RECEIVED indicates that the MAC exited
+//! power-down mode due to a remote wake-up frame being received.  This
+//! function call clears this flag.
+//! - \b EMAC_PMT_MAGIC_PACKET_RECEIVED indicates that the MAC exited
+//! power-down mode due to a wake-on-LAN magic packet being received.  This
+//! function call clears this flag.
+//
+//*****************************************************************************
+uint32_t
+EMACPowerManagementStatusGet(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Read the control/status register and mask off the status bits to return
+    // them to the caller.
+    //
+    return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) &
+           (EMAC_PMTCTLSTAT_WUPRX | EMAC_PMTCTLSTAT_MGKPRX |
+            EMAC_PMTCTLSTAT_PWRDWN));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/emac.h b/bsp/tm4c129x/libraries/driverlib/emac.h
new file mode 100644
index 0000000000..9c76ec776c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/emac.h
@@ -0,0 +1,1025 @@
+//*****************************************************************************
+//
+// emac.h - Defines and Macros for the Ethernet module on Snowflake-class
+//          devices.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_EMAC_H__
+#define __DRIVERLIB_EMAC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup emac_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The physical address of the internal PHY.  This should be in hw_emac.h.
+//
+//*****************************************************************************
+#define EMAC_PHY_ADDR 0
+
+//*****************************************************************************
+//
+// Helper Macros for Ethernet Processing
+//
+//*****************************************************************************
+//
+// htonl/ntohl - Big endian/little endian byte swapping macros for 32-bit
+// values.
+//
+//*****************************************************************************
+#ifndef htonl
+    #define htonl(a)                    \
+        ((((a) >> 24) & 0x000000ff) |   \
+         (((a) >>  8) & 0x0000ff00) |   \
+         (((a) <<  8) & 0x00ff0000) |   \
+         (((a) << 24) & 0xff000000))
+#endif
+
+#ifndef ntohl
+    #define ntohl(a)    htonl((a))
+#endif
+
+//*****************************************************************************
+//
+// htons/ntohs - Big endian/little endian byte swapping macros for 16-bit
+// values.
+//
+//*****************************************************************************
+#ifndef htons
+    #define htons(a)                \
+        ((((a) >> 8) & 0x00ff) |    \
+         (((a) << 8) & 0xff00))
+#endif
+
+#ifndef ntohs
+    #define ntohs(a)    htons((a))
+#endif
+
+//*****************************************************************************
+//
+// Forward reference to the Ethernet DMA descriptor structure.
+//
+//*****************************************************************************
+typedef struct tEMACDMADescriptor tEMACDMADescriptor;
+
+//*****************************************************************************
+//
+//! A union used to describe the two overlapping fields forming the third
+//! word of the Ethernet DMA descriptor.
+//
+//*****************************************************************************
+typedef union
+{
+    //
+    //! When DMA descriptors are used in chained mode, this field is used to
+    //! provide a link to the next descriptor.
+    //
+    tEMACDMADescriptor *pLink;
+
+    //
+    //! When the DMA descriptors are unchained, this field may be used to point
+    //! to a second buffer containing data for transmission or providing
+    //! storage for a received frame.
+    //
+    void *pvBuffer2;
+}
+tEMACDES3;
+
+//*****************************************************************************
+//
+//! A structure defining a single Ethernet DMA buffer descriptor.
+//
+//*****************************************************************************
+struct tEMACDMADescriptor
+{
+    //
+    //! The first DMA descriptor word contains various control and status bits
+    //! depending upon whether the descriptor is in the transmit or receive
+    //! queue.  Bit 31 is always the ``OWN'' bit which, when set, indicates
+    //! that the hardware has control of the descriptor.
+    //
+    volatile uint32_t ui32CtrlStatus;
+
+    //
+    //! The second descriptor word contains information on the size of the
+    //! buffer or buffers attached to the descriptor and various additional
+    //! control bits.
+    //
+    volatile uint32_t ui32Count;
+
+    //
+    //! The third descriptor word contains a pointer to the buffer containing
+    //! data to transmit or into which received data should be written.  This
+    //! pointer must refer to a buffer in internal SRAM.  Pointers to flash or
+    //! EPI-connected memory may not be used and will result in the MAC
+    //! reporting a bus error.
+    //
+    void *pvBuffer1;
+
+    //
+    //! The fourth descriptor word contains either a pointer to the next
+    //! descriptor in the ring or a pointer to a second data buffer.  The
+    //! meaning of the word is controlled by the ``CHAINED'' control bit which
+    //! appears in the first word of the transmit descriptor or the second
+    //! word of the receive descriptor.
+    //!
+    tEMACDES3 DES3;
+
+    //
+    //! The fifth descriptor word is reserved for transmit descriptors but
+    //! used to report extended status in a receive descriptor.
+    //
+    volatile uint32_t ui32ExtRxStatus;
+
+    //
+    //! The sixth descriptor word is reserved for both transmit and receive
+    //! descriptors.
+    //
+    uint32_t ui32Reserved;
+
+    //
+    //! The seventh descriptor word contains the low 32 bits of the 64-bit
+    //! timestamp captured for transmitted or received data.  The value is set
+    //! only when the transmitted or received data contains the end of a
+    //! packet.  Availability of the timestamp is indicated via a status bit
+    //! in the first descriptor word.
+    //
+    volatile uint32_t ui32IEEE1588TimeLo;
+
+    //
+    //! The eighth descriptor word contains the high 32 bits of the 64-bit
+    //! timestamp captured for transmitted or received data.
+    //
+    volatile uint32_t ui32IEEE1588TimeHi;
+};
+
+//*****************************************************************************
+//
+// Fields found in the DES0 word of the transmit descriptor (ui32CtrlStatus in
+// tEMACDMADescriptor)
+//
+//*****************************************************************************
+#define DES0_TX_CTRL_OWN                    0x80000000
+#define DES0_TX_CTRL_INTERRUPT              0x40000000
+#define DES0_TX_CTRL_LAST_SEG               0x20000000
+#define DES0_TX_CTRL_FIRST_SEG              0x10000000
+
+//
+// This value indicates that the MAC should not append a CRC to transmitted
+// packets.  If used with DES0_TX_CTRL_REPLACE_CRC, the last 4 bytes of the
+// packet passed to the transmitter are replaced with a newly calculated CRC.
+// If DES0_TX_CTRL_REPLACE_CRC is not specified, it is assumed that packets
+// transmitted have valid CRCs precomputed and included in the frame data.
+//
+// If DES0_TX_CTRL_DISABLE_CRC is not specified, the MAC will calculate the
+// CRC for all frames transmitted and append this value as the 4-byte FCS
+// after the last data byte in the frame.
+//
+#define DES0_TX_CTRL_DISABLE_CRC            0x08000000
+#define DES0_TX_CTRL_DISABLE_PADDING        0x04000000
+#define DES0_TX_CTRL_ENABLE_TS              0x02000000
+
+//
+// This value is only valid if used alongside DES0_TX_CTRL_DISABLE_CRC.  When
+// specified, the MAC will replace the last 4 bytes of a transmitted frame
+// with a newly calculated CRC.
+//
+#define DES0_TX_CTRL_REPLACE_CRC            0x01000000
+#define DES0_TX_CTRL_CHKSUM_M               0x00C00000
+#define DES0_TX_CTRL_NO_CHKSUM              0x00000000
+#define DES0_TX_CTRL_IP_HDR_CHKSUM          0x00400000
+#define DES0_TX_CTRL_IP_HDR_PAY_CHKSUM      0x00800000
+#define DES0_TX_CTRL_IP_ALL_CKHSUMS         0x00C00000
+#define DES0_TX_CTRL_END_OF_RING            0x00200000
+#define DES0_TX_CTRL_CHAINED                0x00100000
+#define DES0_TX_CTRL_VLAN_M                 0x000C0000
+#define DES0_TX_CTRL_VLAN_NONE              0x00000000
+#define DES0_TX_CTRL_VLAN_REMOVE            0x00040000
+#define DES0_TX_CTRL_VLAN_INSERT            0x00080000
+#define DES0_TX_CTRL_VLAN_REPLACE           0x000C0000
+#define DES0_TX_STAT_TS_CAPTURED            0x00020000
+#define DES0_TX_STAT_IPH_ERR                0x00010000
+#define DES0_TX_STAT_ERR                    0x00008000
+#define DES0_TX_STAT_JABBER_TO              0x00004000
+#define DES0_TX_STAT_FLUSHED                0x00002000
+#define DES0_TX_STAT_PAYLOAD_ERR            0x00001000
+#define DES0_TX_STAT_CARRIER_LOST           0x00000800
+#define DES0_TX_STAT_NO_CARRIER             0x00000400
+#define DES0_TX_STAT_TX_L_COLLISION         0x00000200
+#define DES0_TX_STAT_E_COLLISION            0x00000100
+#define DES0_TX_STAT_VLAN_FRAME             0x00000080
+#define DES0_TX_STAT_COL_COUNT_M            0x00000078
+#define DES0_TX_STAT_COL_COUNT_S            3
+#define DES0_TX_STAT_E_DEFERRAL             0x00000004
+#define DES0_TX_STAT_UNDERFLOW              0x00000002
+#define DES0_TX_STAT_DEFERRED               0x00000001
+
+//*****************************************************************************
+//
+// Fields found in the DES1 word of the transmit descriptor (ui32Count in
+// tEMACDMADescriptor)
+//
+//*****************************************************************************
+#define DES1_TX_CTRL_SADDR_MAC1             0x80000000
+#define DES1_TX_CTRL_SADDR_M                0x60000000
+#define DES1_TX_CTRL_SADDR_NONE             0x00000000
+#define DES1_TX_CTRL_SADDR_INSERT           0x20000000
+#define DES1_TX_CTRL_SADDR_REPLACE          0x40000000
+#define DES1_TX_CTRL_BUFF2_SIZE_M           0x1FFF0000
+#define DES1_TX_CTRL_BUFF1_SIZE_M           0x00001FFF
+#define DES1_TX_CTRL_BUFF2_SIZE_S           16
+#define DES1_TX_CTRL_BUFF1_SIZE_S           0
+
+//*****************************************************************************
+//
+// Fields found in the DES0 word of the receive descriptor (ui32CtrlStatus in
+// tEMACDMADescriptor)
+//
+//*****************************************************************************
+#define DES0_RX_CTRL_OWN                    0x80000000
+#define DES0_RX_STAT_DEST_ADDR_FAIL         0x40000000
+#define DES0_RX_STAT_FRAME_LENGTH_M         0x3FFF0000
+#define DES0_RX_STAT_FRAME_LENGTH_S         16
+#define DES0_RX_STAT_ERR                    0x00008000
+#define DES0_RX_STAT_DESCRIPTOR_ERR         0x00004000
+#define DES0_RX_STAT_SRC_ADDR_FAIL          0x00002000
+#define DES0_RX_STAT_LENGTH_ERR             0x00001000
+#define DES0_RX_STAT_OVERFLOW               0x00000800
+#define DES0_RX_STAT_VLAN_TAG               0x00000400
+#define DES0_RX_STAT_FIRST_DESC             0x00000200
+#define DES0_RX_STAT_LAST_DESC              0x00000100
+#define DES0_RX_STAT_TS_AVAILABLE           0x00000080
+#define DES0_RX_STAT_RX_L_COLLISION         0x00000040
+#define DES0_RX_STAT_FRAME_TYPE             0x00000020
+#define DES0_RX_STAT_WDOG_TIMEOUT           0x00000010
+#define DES0_RX_STAT_RX_ERR                 0x00000008
+#define DES0_RX_STAT_DRIBBLE_ERR            0x00000004
+#define DES0_RX_STAT_CRC_ERR                0x00000002
+#define DES0_RX_STAT_MAC_ADDR               0x00000001
+#define DES0_RX_STAT_EXT_AVAILABLE          0x00000001
+
+//*****************************************************************************
+//
+// Fields found in the DES1 word of the receive descriptor (ui32Count in
+// tEMACDMADescriptor)
+//
+//*****************************************************************************
+#define DES1_RX_CTRL_DISABLE_INT            0x80000000
+#define DES1_RX_CTRL_BUFF2_SIZE_M           0x1FFF0000
+#define DES1_RX_CTRL_BUFF2_SIZE_S           16
+#define DES1_RX_CTRL_END_OF_RING            0x00008000
+#define DES1_RX_CTRL_CHAINED                0x00004000
+#define DES1_RX_CTRL_BUFF1_SIZE_M           0x00001FFF
+#define DES1_RX_CTRL_BUFF1_SIZE_S           0
+
+//*****************************************************************************
+//
+// Fields found in the DES4 word of the receive descriptor (ui32ExtRxStatus in
+// tEMACDMADescriptor)
+//
+//*****************************************************************************
+#define DES4_RX_STAT_TS_DROPPED             0x00004000
+#define DES4_RX_STAT_PTP_VERSION2           0x00002000
+#define DES4_RX_STAT_PTP_TYPE_ETH           0x00001000
+#define DES4_RX_STAT_PTP_TYPE_UDP           0x00000000
+#define DES4_RX_STAT_PTP_MT_M               0x00000F00
+#define DES4_RX_STAT_PTP_MT_NONE            0x00000000
+#define DES4_RX_STAT_PTP_MT_SYNC            0x00000100
+#define DES4_RX_STAT_PTP_MT_FOLLOW_UP       0x00000200
+#define DES4_RX_STAT_PTP_MT_DELAY_REQ       0x00000300
+#define DES4_RX_STAT_PTP_MT_DELAY_RESP      0x00000400
+#define DES4_RX_STAT_PTP_MT_PDELAY_REQ      0x00000500
+#define DES4_RX_STAT_PTP_MT_PDELAY_RESP     0x00000600
+#define DES4_RX_STAT_PTP_MT_PDELAY_RFU      0x00000700
+#define DES4_RX_STAT_PTP_MT_ANNOUNCE        0x00000800
+#define DES4_RX_STAT_PTP_MT_SIGNALLING      0x00000A00
+#define DES4_RX_STAT_PTP_MT_RESERVED        0x00000F00
+#define DES4_RX_STAT_IPV6                   0x00000080
+#define DES4_RX_STAT_IPV4                   0x00000040
+#define DES4_RX_STAT_IP_CHK_BYPASSED        0x00000020
+#define DES4_RX_STAT_IP_PAYLOAD_ERR         0x00000010
+#define DES4_RX_STAT_IP_HEADER_ERR          0x00000008
+#define DES4_RX_STAT_PAYLOAD_M              0x00000007
+#define DES4_RX_STAT_PAYLOAD_UNKNOWN        0x00000000
+#define DES4_RX_STAT_PAYLOAD_UDP            0x00000001
+#define DES4_RX_STAT_PAYLOAD_TCP            0x00000002
+#define DES4_RX_STAT_PAYLOAD_ICMP           0x00000003
+
+//*****************************************************************************
+//
+// Values used in the ui32BusConfig parameter to EMACInit().
+//
+//***************************************************************************
+#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_M      0x30000000
+#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_1      0x00000000
+#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_2      0x10000000
+#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_3      0x20000000
+#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_4      0x30000000
+#define EMAC_BCONFIG_TX_PRIORITY            0x08000000
+#define EMAC_BCONFIG_ADDR_ALIGNED           0x02000000
+#define EMAC_BCONFIG_PRIORITY_M             0x0000C000
+#define EMAC_BCONFIG_PRIORITY_1_1           (0 << 14)
+#define EMAC_BCONFIG_PRIORITY_2_1           (1 << 14)
+#define EMAC_BCONFIG_PRIORITY_3_1           (2 << 14)
+#define EMAC_BCONFIG_PRIORITY_4_1           (3 << 14)
+#define EMAC_BCONFIG_PRIORITY_FIXED         0x00000002
+#define EMAC_BCONFIG_FIXED_BURST            0x00010000
+#define EMAC_BCONFIG_MIXED_BURST            0x04000000
+
+//*****************************************************************************
+//
+// Options used in the ui32Config parameter to EMACPHYConfigSet().
+//
+//*****************************************************************************
+#define EMAC_PHY_TYPE_INTERNAL              0x00000000
+#define EMAC_PHY_TYPE_EXTERNAL_MII          0x80000000
+#define EMAC_PHY_TYPE_EXTERNAL_RMII         0xC0000000
+#define EMAC_PHY_INT_NIB_TXERR_DET_DIS      0x01000000
+#define EMAC_PHY_INT_RX_ER_DURING_IDLE      0x00800000
+#define EMAC_PHY_INT_ISOLATE_MII_LLOSS      0x00400000
+#define EMAC_PHY_INT_LINK_LOSS_RECOVERY     0x00200000
+#define EMAC_PHY_INT_TDRRUN                 0x00100000
+#define EMAC_PHY_INT_LD_ON_RX_ERR_COUNT     0x00040000
+#define EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT   0x00020000
+#define EMAC_PHY_INT_LD_ON_LOW_SNR          0x00010000
+#define EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY    0x00008000
+#define EMAC_PHY_INT_POLARITY_SWAP          0x00004000
+#define EMAC_PHY_INT_MDI_SWAP               0x00002000
+#define EMAC_PHY_INT_ROBUST_MDIX            0x00001000
+#define EMAC_PHY_INT_FAST_MDIX              0x00000800
+#define EMAC_PHY_INT_MDIX_EN                0x00000400
+#define EMAC_PHY_INT_FAST_RXDV_DETECT       0x00000200
+#define EMAC_PHY_INT_FAST_L_UP_DETECT       0x00000100
+#define EMAC_PHY_INT_EXT_FULL_DUPLEX        0x00000080
+#define EMAC_PHY_INT_FAST_AN_80_50_35       0x00000040
+#define EMAC_PHY_INT_FAST_AN_120_75_50      0x00000050
+#define EMAC_PHY_INT_FAST_AN_140_150_100    0x00000060
+#define EMAC_PHY_FORCE_10B_T_HALF_DUPLEX    0x00000000
+#define EMAC_PHY_FORCE_10B_T_FULL_DUPLEX    0x00000002
+#define EMAC_PHY_FORCE_100B_T_HALF_DUPLEX   0x00000004
+#define EMAC_PHY_FORCE_100B_T_FULL_DUPLEX   0x00000006
+#define EMAC_PHY_AN_10B_T_HALF_DUPLEX       0x00000008
+#define EMAC_PHY_AN_10B_T_FULL_DUPLEX       0x0000000A
+#define EMAC_PHY_AN_100B_T_HALF_DUPLEX      0x0000000C
+#define EMAC_PHY_AN_100B_T_FULL_DUPLEX      0x0000000E
+#define EMAC_PHY_INT_HOLD                   0x00000001
+
+#define EMAC_PHY_TYPE_MASK                  0xC0000000
+
+//*****************************************************************************
+//
+// Options used in the ui32Config parameter to EMACConfigSet().
+//
+//*****************************************************************************
+#define EMAC_CONFIG_USE_MACADDR1          0x40000000
+#define EMAC_CONFIG_USE_MACADDR0          0x00000000
+#define EMAC_CONFIG_SA_FROM_DESCRIPTOR    0x00000000
+#define EMAC_CONFIG_SA_INSERT             0x20000000
+#define EMAC_CONFIG_SA_REPLACE            0x30000000
+#define EMAC_CONFIG_2K_PACKETS            0x08000000
+#define EMAC_CONFIG_STRIP_CRC             0x02000000
+#define EMAC_CONFIG_JABBER_DISABLE        0x00400000
+#define EMAC_CONFIG_JUMBO_ENABLE          0x00100000
+#define EMAC_CONFIG_IF_GAP_MASK           0x000E0000
+#define EMAC_CONFIG_IF_GAP_96BITS         (0x0 << 17)
+#define EMAC_CONFIG_IF_GAP_88BITS         (0x1 << 17)
+#define EMAC_CONFIG_IF_GAP_80BITS         (0x2 << 17)
+#define EMAC_CONFIG_IF_GAP_72BITS         (0x3 << 17)
+#define EMAC_CONFIG_IF_GAP_64BITS         (0x4 << 17)
+#define EMAC_CONFIG_IF_GAP_56BITS         (0x5 << 17)
+#define EMAC_CONFIG_IF_GAP_48BITS         (0x6 << 17)
+#define EMAC_CONFIG_IF_GAP_40BITS         (0x7 << 17)
+#define EMAC_CONFIG_CS_DISABLE            0x00010000
+#define EMAC_CONFIG_100MBPS               0x00004000
+#define EMAC_CONFIG_10MBPS                0x00000000
+#define EMAC_CONFIG_RX_OWN_DISABLE        0x00002000
+#define EMAC_CONFIG_LOOPBACK              0x00001000
+#define EMAC_CONFIG_FULL_DUPLEX           0x00000800
+#define EMAC_CONFIG_HALF_DUPLEX           0x00000000
+#define EMAC_CONFIG_CHECKSUM_OFFLOAD      0x00000400
+#define EMAC_CONFIG_RETRY_DISABLE         0x00000200
+#define EMAC_CONFIG_AUTO_CRC_STRIPPING    0x00000080
+#define EMAC_CONFIG_BO_MASK               0x00000060
+#define EMAC_CONFIG_BO_LIMIT_1024         (0x0 << 5)
+#define EMAC_CONFIG_BO_LIMIT_256          (0x1 << 5)
+#define EMAC_CONFIG_BO_LIMIT_16           (0x2 << 5)
+#define EMAC_CONFIG_BO_LIMIT_2            (0x3 << 5)
+#define EMAC_CONFIG_DEFERRAL_CHK_ENABLE   0x00000010
+#define EMAC_CONFIG_PREAMBLE_MASK         0x00000003
+#define EMAC_CONFIG_7BYTE_PREAMBLE        0x00000000
+#define EMAC_CONFIG_5BYTE_PREAMBLE        0x00000001
+#define EMAC_CONFIG_3BYTE_PREAMBLE        0x00000002
+
+//*****************************************************************************
+//
+// Options used in the ui32ModeFlags parameter to EMACConfigSet().
+//
+//*****************************************************************************
+#define EMAC_MODE_KEEP_BAD_CRC            0x04000000
+#define EMAC_MODE_RX_STORE_FORWARD        0x02000000
+#define EMAC_MODE_RX_FLUSH_DISABLE        0x01000000
+#define EMAC_MODE_TX_STORE_FORWARD        0x00200000
+#define EMAC_MODE_TX_THRESHOLD_16_BYTES   (7 << 14)
+#define EMAC_MODE_TX_THRESHOLD_24_BYTES   (6 << 14)
+#define EMAC_MODE_TX_THRESHOLD_32_BYTES   (5 << 14)
+#define EMAC_MODE_TX_THRESHOLD_40_BYTES   (4 << 14)
+#define EMAC_MODE_TX_THRESHOLD_64_BYTES   (0 << 14)
+#define EMAC_MODE_TX_THRESHOLD_128_BYTES  (1 << 14)
+#define EMAC_MODE_TX_THRESHOLD_192_BYTES  (2 << 14)
+#define EMAC_MODE_TX_THRESHOLD_256_BYTES  (3 << 14)
+#define EMAC_MODE_RX_ERROR_FRAMES         0x00000080
+#define EMAC_MODE_RX_UNDERSIZED_FRAMES    0x00000040
+#define EMAC_MODE_RX_THRESHOLD_64_BYTES   (0 << 3)
+#define EMAC_MODE_RX_THRESHOLD_32_BYTES   (1 << 3)
+#define EMAC_MODE_RX_THRESHOLD_96_BYTES   (2 << 3)
+#define EMAC_MODE_RX_THRESHOLD_128_BYTES  (3 << 3)
+#define EMAC_MODE_OPERATE_2ND_FRAME       0x00000002
+
+//*****************************************************************************
+//
+// These two values may be returned by EMACConfigGet() in the *pui32Config
+// parameter.  The transmitter and receiver are, however, enabled and disabled
+// using independent functions, EMACTxEnable/Disable() and
+// EMACRxEnable/Disable().
+//
+//*****************************************************************************
+#define EMAC_CONFIG_TX_ENABLED            0x00000008
+#define EMAC_CONFIG_RX_ENABLED            0x00000004
+
+//*****************************************************************************
+//
+// These two values may be returned by EMACConfigGet() in the *pui32Mode
+// parameter. The transmit and receive DMA channels are, however, enabled and
+// disabled using independent functions, EMACTxEnable/Disable() and
+// EMACRxEnable/Disable().
+//
+//*****************************************************************************
+#define EMAC_MODE_TX_DMA_ENABLED          0x00002000
+#define EMAC_MODE_RX_DMA_ENABLED          0x00000002
+
+//*****************************************************************************
+//
+// These values may be passed to EMACFrameFilterSet() in the ui32FilterOpts
+// parameter, and are returned by EMACFrameFilterGet().
+//
+//*****************************************************************************
+#define EMAC_FRMFILTER_RX_ALL             0x80000000
+#define EMAC_FRMFILTER_VLAN               0x00010000
+#define EMAC_FRMFILTER_HASH_AND_PERFECT   0x00000400
+#define EMAC_FRMFILTER_SADDR              0x00000200
+#define EMAC_FRMFILTER_INV_SADDR          0x00000100
+#define EMAC_FRMFILTER_PASS_MASK          (0x03 << 6)
+#define EMAC_FRMFILTER_PASS_NO_CTRL       (0x00 << 6)
+#define EMAC_FRMFILTER_PASS_NO_PAUSE      (0x01 << 6)
+#define EMAC_FRMFILTER_PASS_ALL_CTRL      (0x02 << 6)
+#define EMAC_FRMFILTER_PASS_ADDR_CTRL     (0x03 << 6)
+#define EMAC_FRMFILTER_BROADCAST          0x00000020
+#define EMAC_FRMFILTER_PASS_MULTICAST     0x00000010
+#define EMAC_FRMFILTER_INV_DADDR          0x00000008
+#define EMAC_FRMFILTER_HASH_MULTICAST     0x00000004
+#define EMAC_FRMFILTER_HASH_UNICAST       0x00000002
+#define EMAC_FRMFILTER_PROMISCUOUS        0x00000001
+
+//*****************************************************************************
+//
+// Values which may be returned by EMACStatusGet().
+//
+//*****************************************************************************
+#define EMAC_STATUS_TX_NOT_EMPTY          0x01000000
+#define EMAC_STATUS_TX_WRITING_FIFO       0x00400000
+#define EMAC_STATUS_TRC_STATE_MASK        0x00300000
+#define EMAC_STATUS_TRC_STATE_IDLE        (0x00 << 20)
+#define EMAC_STATUS_TRC_STATE_READING     (0x01 << 20)
+#define EMAC_STATUS_TRC_STATE_WAITING     (0x02 << 20)
+#define EMAC_STATUS_TRC_STATE_STATUS      (0x03 << 20)
+#define EMAC_STATUS_TX_PAUSED             0x00080000
+#define EMAC_STATUS_TFC_STATE_MASK        0x00060000
+#define EMAC_STATUS_TFC_STATE_IDLE        (0x00 << 17)
+#define EMAC_STATUS_TFC_STATE_WAITING     (0x01 << 17)
+#define EMAC_STATUS_TFC_STATE_PAUSING     (0x02 << 17)
+#define EMAC_STATUS_TFC_STATE_WRITING     (0x03 << 17)
+#define EMAC_STATUS_MAC_NOT_IDLE          0x00010000
+#define EMAC_STATUS_RX_FIFO_LEVEL_MASK    0x00000300
+#define EMAC_STATUS_RX_FIFO_EMPTY         (0x00 << 8)
+#define EMAC_STATUS_RX_FIFO_BELOW         (0x01 << 8)
+#define EMAC_STATUS_RX_FIFO_ABOVE         (0x02 << 8)
+#define EMAC_STATUS_RX_FIFO_FULL          (0x03 << 8)
+#define EMAC_STATUS_RX_FIFO_STATE_MASK    0x00000060
+#define EMAC_STATUS_RX_FIFO_IDLE          (0x00 << 5)
+#define EMAC_STATUS_RX_FIFO_READING       (0x01 << 5)
+#define EMAC_STATUS_RX_FIFO_STATUS        (0x02 << 5)
+#define EMAC_STATUS_RX_FIFO_FLUSHING      (0x03 << 5)
+#define EMAC_STATUS_RWC_ACTIVE            0x00000010
+#define EMAC_STATUS_RPE_ACTIVE            0x00000001
+
+//*****************************************************************************
+//
+// Values which may be returned by EMACDMAStateGet().
+//
+//*****************************************************************************
+#define EMAC_DMA_TXSTAT_MASK              (0x07 << 20)
+#define EMAC_DMA_TXSTAT_STOPPED           (0x00 << 20)
+#define EMAC_DMA_TXSTAT_RUN_FETCH_DESC    (0x01 << 20)
+#define EMAC_DMA_TXSTAT_RUN_WAIT_STATUS   (0x02 << 20)
+#define EMAC_DMA_TXSTAT_RUN_READING       (0x03 << 20)
+#define EMAC_DMA_TXSTAT_RUN_CLOSE_DESC    (0x07 << 20)
+#define EMAC_DMA_TXSTAT_TS_WRITE          (0x04 << 20)
+#define EMAC_DMA_TXSTAT_SUSPENDED         (0x06 << 20)
+
+#define EMAC_DMA_RXSTAT_MASK              (0x07 << 17)
+#define EMAC_DMA_RXSTAT_STOPPED           (0x00 << 17)
+#define EMAC_DMA_RXSTAT_RUN_FETCH_DESC    (0x01 << 17)
+#define EMAC_DMA_RXSTAT_RUN_WAIT_PACKET   (0x03 << 17)
+#define EMAC_DMA_RXSTAT_SUSPENDED         (0x04 << 17)
+#define EMAC_DMA_RXSTAT_RUN_CLOSE_DESC    (0x05 << 17)
+#define EMAC_DMA_RXSTAT_TS_WRITE          (0x06 << 17)
+#define EMAC_DMA_RXSTAT_RUN_RECEIVING     (0x07 << 17)
+
+#define EMAC_TX_DMA_STATE(x) ((x) & EMAC_DMA_TXSTAT_MASK)
+#define EMAC_RX_DMA_STATE(x) ((x) & EMAC_DMA_RXSTAT_MASK)
+
+#define EMAC_DMA_ERROR                    0x00002000
+#define EMAC_DMA_ERR_MASK                 0x03800000
+#define EMAC_DMA_ERR_RX_DATA_WRITE        0x00000000
+#define EMAC_DMA_ERR_TX_DATA_READ         0x01800000
+#define EMAC_DMA_ERR_RX_DESC_WRITE        0x02000000
+#define EMAC_DMA_ERR_TX_DESC_WRITE        0x02800000
+#define EMAC_DMA_ERR_RX_DESC_READ         0x03000000
+#define EMAC_DMA_ERR_TX_DESC_READ         0x03800000
+
+//*****************************************************************************
+//
+// Values which may be ORed together in the ui32Config parameter passed to
+// EMACAddrFilterSet and which may be returned by EMACAddrFilterGet.
+//
+//*****************************************************************************
+#define EMAC_FILTER_ADDR_ENABLE           0x80000000
+#define EMAC_FILTER_SOURCE_ADDR           0x40000000
+#define EMAC_FILTER_MASK_BYTE_6           0x20000000
+#define EMAC_FILTER_MASK_BYTE_5           0x10000000
+#define EMAC_FILTER_MASK_BYTE_4           0x08000000
+#define EMAC_FILTER_MASK_BYTE_3           0x04000000
+#define EMAC_FILTER_MASK_BYTE_2           0x03000000
+#define EMAC_FILTER_MASK_BYTE_1           0x01000000
+
+#define EMAC_FILTER_BYTE_MASK_M           0x3F000000
+#define EMAC_FILTER_BYTE_MASK_S           24
+
+//*****************************************************************************
+//
+// Flags passed to EMACTimestampConfigSet or returned from
+// EMACTimestampConfigGet.
+//
+//*****************************************************************************
+#define EMAC_TS_MAC_FILTER_ENABLE         0x00040000
+#define EMAC_TS_MAC_FILTER_DISABLE        0x00000000
+#define EMAC_TS_SYNC_FOLLOW_DREQ_DRESP    0x00000000
+#define EMAC_TS_SYNC_ONLY                 0x00004000
+#define EMAC_TS_DELAYREQ_ONLY             0x0000C000
+#define EMAC_TS_ALL                       0x00010000
+#define EMAC_TS_SYNC_PDREQ_PDRESP         0x00014000
+#define EMAC_TS_DREQ_PDREQ_PDRESP         0x0001C000
+#define EMAC_TS_SYNC_DELAYREQ             0x00020000
+#define EMAC_TS_PDREQ_PDRESP              0x00030000
+#define EMAC_TS_PROCESS_IPV4_UDP          0x00002000
+#define EMAC_TS_PROCESS_IPV6_UDP          0x00001000
+#define EMAC_TS_PROCESS_ETHERNET          0x00000800
+#define EMAC_TS_PTP_VERSION_2             0x00000400
+#define EMAC_TS_PTP_VERSION_1             0x00000000
+#define EMAC_TS_DIGITAL_ROLLOVER          0x00000200
+#define EMAC_TS_BINARY_ROLLOVER           0x00000000
+#define EMAC_TS_ALL_RX_FRAMES             0x00000100
+#define EMAC_TS_UPDATE_FINE               0x00000002
+#define EMAC_TS_UPDATE_COARSE             0x00000000
+
+//*****************************************************************************
+//
+// Some register bit definitions relating to external PHYs.  These are not
+// relevant (or available) when using the internal Ethernet PHY but having
+// the definitions here helps when using an external MII or RMII PHY.
+//
+//*****************************************************************************
+#define EPHY_SCR_INPOL_EXT                0x00000008
+#define EPHY_SCR_TINT_EXT                 0x00000004
+#define EPHY_SCR_INTEN_EXT                0x00000002
+#define EPHY_SCR_INTOE_EXT                0x00000001
+
+//*****************************************************************************
+//
+// These interrupt sources may be passed to EMACIntEnable() and
+// EMACIntDisable() to enable or disable various Ethernet interrupt sources.
+//
+//*****************************************************************************
+//
+// Note that interrupts relating to timestamping and power management must be
+// independently enabled via calls to functions EMACTimestampTargetIntEnable
+// and EMACPowerManagementControlSet.
+//
+// EMAC_INT_PHY is deliberately set to a reserved bit in the MAC interrupt
+// register.  We handle the fact that the PHY interrupt is controlled via an
+// independent register within the code.  If we didn't do this, the app would
+// have to enable the MAC interrupt then enable the PHY interrupt via a
+// different API (since they share a vector).  To further complicate matters,
+// they would have to call EMACIntStatus() and then, if it returned 0,
+// read the PHY interrupt status to see that it fired.  This would be nasty
+// and unfriendly so we hide it inside DriverLib.
+//
+//*****************************************************************************
+#define EMAC_INT_PHY                      0x80000000
+#define EMAC_INT_EARLY_RECEIVE            0x00004000
+#define EMAC_INT_BUS_ERROR                0x00002000
+#define EMAC_INT_EARLY_TRANSMIT           0x00000400
+#define EMAC_INT_RX_WATCHDOG              0x00000200
+#define EMAC_INT_RX_STOPPED               0x00000100
+#define EMAC_INT_RX_NO_BUFFER             0x00000080
+#define EMAC_INT_RECEIVE                  0x00000040
+#define EMAC_INT_TX_UNDERFLOW             0x00000020
+#define EMAC_INT_RX_OVERFLOW              0x00000010
+#define EMAC_INT_TX_JABBER                0x00000008
+#define EMAC_INT_TX_NO_BUFFER             0x00000004
+#define EMAC_INT_TX_STOPPED               0x00000002
+#define EMAC_INT_TRANSMIT                 0x00000001
+
+//
+// These interrupt sources are summary indicators.  They are readable
+// using EMACIntStatus() and must be cleared using EMACIntClear().  They
+// may be enabled or disabled independently of the group of interrupts that
+// they are derived from but offer merely a simple way to be informed of a
+// normal or abnormal condition requiring software attention.
+//
+// EMAC_INT_NORMAL_INT is the logical OR of the masked state of
+// EMAC_INT_TRANSMIT | EMAC_INT_RECEIVE | EMAC_INT_TX_NO_BUFFER |
+// EMAC_INT_EARLY_RECEIVE.
+//
+// EMAC_INT_ABNORMAL_INT is the logical OR of the masked state of
+// EMAC_INT_TX_STOPPED | EMAC_INT_TX_JABBER | EMAC_INT_RX_OVERFLOW |
+// EMAC_INT_TX_UNDERFLOW | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED |
+// EMAC_INT_RX_WATCHDOG | EMAC_INT_EARLY_TRANSMIT | EMAC_INT_BUS_ERROR.
+//
+#define EMAC_INT_NORMAL_INT               0x00010000
+#define EMAC_INT_ABNORMAL_INT             0x00008000
+
+//
+// This interrupt source is readable using EMACIntStatus but must
+// be cleared by calling the EMACTimestampIntStatus().
+//
+#define EMAC_INT_TIMESTAMP                0x20000000
+
+//
+// Interrupt sources which may be returned from EMACTimestampIntStatus().
+//
+#define EMAC_TS_INT_TARGET_REACHED        0x00000002
+#define EMAC_TS_INT_TS_SEC_OVERFLOW       0x00000001
+
+//
+// This interrupt source is readable using EMACIntStatus but must
+// be cleared by calling EMACPowerManagementStatusGet().
+//
+#define EMAC_INT_POWER_MGMNT              0x10000000
+
+//*****************************************************************************
+//
+// Configuration flags that may be passed in the ui32FreqConfig parameter to
+// EMACTimestampPPSSimpleModeSet().
+//
+//*****************************************************************************
+#define EMAC_PPS_SINGLE_PULSE             0x00000000
+#define EMAC_PPS_1HZ                      0x00000001
+#define EMAC_PPS_2HZ                      0x00000002
+#define EMAC_PPS_4HZ                      0x00000003
+#define EMAC_PPS_8HZ                      0x00000004
+#define EMAC_PPS_16HZ                     0x00000005
+#define EMAC_PPS_32HZ                     0x00000006
+#define EMAC_PPS_64HZ                     0x00000007
+#define EMAC_PPS_128HZ                    0x00000008
+#define EMAC_PPS_256HZ                    0x00000009
+#define EMAC_PPS_512HZ                    0x0000000A
+#define EMAC_PPS_1024HZ                   0x0000000B
+#define EMAC_PPS_2048HZ                   0x0000000C
+#define EMAC_PPS_4096HZ                   0x0000000D
+#define EMAC_PPS_8192HZ                   0x0000000E
+#define EMAC_PPS_16384HZ                  0x0000000F
+#define EMAC_PPS_32768HZ                  0x00000010
+
+//*****************************************************************************
+//
+// Configuration flags that may be passed in the ui32Config parameter to
+// EMACTimestampPPSCommandModeSet().
+//
+//*****************************************************************************
+#define EMAC_PPS_TARGET_INT               0x00000000
+#define EMAC_PPS_TARGET_PPS               0x00000060
+#define EMAC_PPS_TARGET_BOTH              0x00000040
+
+//*****************************************************************************
+//
+// Commands which may be passed to EMACTimestampPPSCmd.
+//
+//*****************************************************************************
+#define EMAC_PPS_COMMAND_NONE             0x00
+#define EMAC_PPS_COMMAND_START_SINGLE     0x01
+#define EMAC_PPS_COMMAND_START_TRAIN      0x02
+#define EMAC_PPS_COMMAND_CANCEL_START     0x03
+#define EMAC_PPS_COMMAND_STOP_AT_TIME     0x04
+#define EMAC_PPS_COMMAND_STOP_NOW         0x05
+#define EMAC_PPS_COMMAND_CANCEL_STOP      0x06
+
+//*****************************************************************************
+//
+// Values which may be passed to EMACVLANRxConfigSet in the ui32Config
+// parameter and which may be returned from EMACVLANRxConfigGet.
+//
+//*****************************************************************************
+#define EMAC_VLAN_RX_HASH_ENABLE          0x00080000
+#define EMAC_VLAN_RX_HASH_DISABLE         0x00000000
+#define EMAC_VLAN_RX_SVLAN_ENABLE         0x00040000
+#define EMAC_VLAN_RX_SVLAN_DISABLE        0x00000000
+#define EMAC_VLAN_RX_NORMAL_MATCH         0x00000000
+#define EMAC_VLAN_RX_INVERSE_MATCH        0x00020000
+#define EMAC_VLAN_RX_12BIT_TAG            0x00010000
+#define EMAC_VLAN_RX_16BIT_TAG            0x00000000
+
+//*****************************************************************************
+//
+// Values which may be passed to EMACVLANTxConfigSet in the ui32Config
+// parameter and which may be returned from EMACVLANTxConfigGet.
+//
+//*****************************************************************************
+#define EMAC_VLAN_TX_CVLAN                0x00000000
+#define EMAC_VLAN_TX_SVLAN                0x00080000
+#define EMAC_VLAN_TX_USE_VLC              0x00040000
+#define EMAC_VLAN_TX_VLC_NONE             0x00000000
+#define EMAC_VLAN_TX_VLC_DELETE           0x00010000
+#define EMAC_VLAN_TX_VLC_INSERT           0x00020000
+#define EMAC_VLAN_TX_VLC_REPLACE          0x00030000
+
+#define EMAC_VLAN_TX_VLC_MASK             0x00030000
+
+#define EMAC_RWU_FILTER_ENABLE            1
+#define EMAC_RWU_FILTER_DISABLE           0
+#define EMAC_RWU_FILTER_MULTICAST         8
+#define EMAC_RWU_FILTER_UNICAST           0
+
+//*****************************************************************************
+//
+// The following structure fields must be packed.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+//! This structure defines up to 4 filters that can be used to define specific
+//! frames which will cause the MAC to wake up from sleep mode.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! A byte mask for each filter defining which bytes from a sequence of
+    //! 31 (bit 31 must be clear in each mask) are used to filter incoming
+    //! packets. A 1 indicates that the relevant byte is used to update the
+    //! CRC16 for the filter, a 0 indicates that the byte is ignored.
+    //
+    uint32_t pui32ByteMask[4];
+
+    //
+    //! Defines whether each filter is enabled and, if so, whether it filters
+    //! multicast or unicast frames.  Valid values are one of
+    //! EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE ORed with one of
+    //! EMAC_RWU_FILTER_UNICAST or EMAC_RWU_FILTER_MULTICAST.
+    //
+    uint8_t pui8Command[4];
+
+    //
+    //! Determines the byte offset within the frame at which the filter starts
+    //! examining bytes.  The minimum value for each offset is 12.  The first
+    //! byte of a frame is offset 0.
+    //
+    uint8_t pui8Offset[4];
+
+    //
+    //! The CRC16 value that is expected for each filter if it passes.  The
+    //! CRC is calculated using all bytes indicated by the filter's mask.
+    //
+    uint16_t pui16CRC[4];
+}
+#if defined(ccs) ||             \
+    defined(codered) ||         \
+    defined(gcc) ||             \
+    defined(rvmdk) ||           \
+    defined(__ARMCC_VERSION) || \
+    defined(sourcerygxx)
+__attribute__ ((packed)) tEMACWakeUpFrameFilter;
+#else
+tEMACWakeUpFrameFilter;
+#endif
+
+//*****************************************************************************
+//
+// Turn off structure packing again.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// Values which may be ORed together and used in the ui32Flags parameter to
+// EMACPowerManagementControlSet.  These may also returned be from a call to
+// EMACPowerManagementControlGet.
+//
+//*****************************************************************************
+#define EMAC_PMT_GLOBAL_UNICAST_ENABLE    0x00000200
+#define EMAC_PMT_WAKEUP_PACKET_ENABLE     0x00000004
+#define EMAC_PMT_MAGIC_PACKET_ENABLE      0x00000002
+#define EMAC_PMT_POWER_DOWN               0x00000001
+
+//*****************************************************************************
+//
+// Values which may be ORed together and returned from a call to
+// EMACPowerManagementStatusGet.  This call will also return
+// EMAC_PMT_POWER_DOWN if the MAC is in power-down mode.
+//
+//*****************************************************************************
+#define EMAC_PMT_WAKEUP_PACKET_RECEIVED   0x00000040
+#define EMAC_PMT_MAGIC_PACKET_RECEIVED    0x00000020
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Public function prototypes.
+//
+//*****************************************************************************
+extern void EMACInit(uint32_t ui32Base, uint32_t ui32SysClk,
+                     uint32_t ui32BusConfig, uint32_t ui32RxBurst,
+                     uint32_t ui32TxBurst, uint32_t ui32DescSkipSize);
+extern void EMACReset(uint32_t ui32Base);
+extern void EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                          uint32_t ui32ModeFlags,
+                          uint32_t ui32RxMaxFrameSize);
+extern void EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts);
+extern uint32_t EMACFrameFilterGet(uint32_t ui32Base);
+extern void EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi,
+                              uint32_t ui32HashLo);
+extern void EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi,
+                              uint32_t *pui32HashLo);
+extern uint32_t EMACHashFilterBitCalculate(uint8_t *pui8MACAddr);
+extern void EMACTxDMAPollDemand(uint32_t ui32Base);
+extern void EMACRxDMAPollDemand(uint32_t ui32Base);
+extern void EMACRxDMADescriptorListSet(uint32_t ui32Base,
+                                       tEMACDMADescriptor *pDescriptor);
+extern tEMACDMADescriptor *EMACRxDMADescriptorListGet(uint32_t ui32Base);
+extern tEMACDMADescriptor *EMACRxDMACurrentDescriptorGet(uint32_t ui32Base);
+extern uint8_t *EMACRxDMACurrentBufferGet(uint32_t ui32Base);
+extern void EMACTxDMADescriptorListSet(uint32_t ui32Base,
+                                       tEMACDMADescriptor *pDescriptor);
+extern tEMACDMADescriptor *EMACTxDMADescriptorListGet(uint32_t ui32Base);
+extern tEMACDMADescriptor *EMACTxDMACurrentDescriptorGet(uint32_t ui32Base);
+extern uint8_t *EMACTxDMACurrentBufferGet(uint32_t ui32Base);
+extern void EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config,
+                          uint32_t *pui32Mode, uint32_t *pui32RxMaxFrameSize);
+extern void EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index,
+                        const uint8_t *pui8MACAddr);
+extern void EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index,
+                        uint8_t *pui8MACAddr);
+extern uint32_t EMACNumAddrGet(uint32_t ui32Base);
+extern void EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index,
+                              uint32_t ui32Config);
+extern uint32_t EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index);
+extern void EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout);
+extern uint32_t EMACStatusGet(uint32_t ui32Base);
+extern uint32_t EMACDMAStateGet(uint32_t ui32Base);
+extern void EMACTxFlush(uint32_t ui32Base);
+extern void EMACTxEnable(uint32_t ui32Base);
+extern void EMACTxDisable(uint32_t ui32Base);
+extern void EMACRxEnable(uint32_t ui32Base);
+extern void EMACRxDisable(uint32_t ui32Base);
+extern void EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t EMACIntStatus(uint32_t ui32Base, bool bMasked);
+extern void EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void EMACIntUnregister(uint32_t ui32Base);
+extern void EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                         uint8_t ui8RegAddr, uint16_t ui16Data);
+extern void EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                                  uint16_t ui16RegAddr, uint16_t ui16Data);
+extern uint16_t EMACPHYRead(uint32_t ui32Base,  uint8_t ui8PhyAddr,
+                            uint8_t ui8RegAddr);
+extern uint16_t EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                                    uint16_t ui16RegAddr);
+extern void EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr);
+extern void EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr);
+extern void EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                                   uint32_t ui32SubSecondInc);
+extern uint32_t EMACTimestampConfigGet(uint32_t ui32Base,
+                                       uint32_t *pui32SubSecondInc);
+extern void EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Seconds);
+extern void EMACTimestampEnable(uint32_t ui32Base);
+extern void EMACTimestampDisable(uint32_t ui32Base);
+extern void EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds,
+                                    uint32_t ui32SubSeconds);
+extern void EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds,
+                                    uint32_t *pui32SubSeconds);
+extern void EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds,
+                                         uint32_t ui32SubSeconds, bool bInc);
+extern void EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds,
+                                   uint32_t ui32Nanoseconds);
+extern void EMACTimestampTargetIntEnable(uint32_t ui32Base);
+extern void EMACTimestampTargetIntDisable(uint32_t ui32Base);
+extern uint32_t EMACTimestampIntStatus(uint32_t ui32Base);
+extern void EMACTimestampPPSSimpleModeSet(uint32_t ui32Base,
+                                          uint32_t ui32FreqConfig);
+extern void EMACTimestampPPSCommandModeSet(uint32_t ui32Base,
+                                           uint32_t ui32Config);
+extern void EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd);
+extern void EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period,
+                                      uint32_t ui32Width);
+extern void EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag,
+                                uint32_t ui32Config);
+extern uint32_t EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag);
+extern void EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag,
+                                uint32_t ui32Config);
+extern uint32_t EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag);
+extern uint32_t EMACVLANHashFilterBitCalculate(uint16_t ui16Tag);
+extern void EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash);
+extern uint32_t EMACVLANHashFilterGet(uint32_t ui32Base);
+extern void EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base,
+                                       const tEMACWakeUpFrameFilter *pFilter);
+extern void EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base,
+                                             tEMACWakeUpFrameFilter *pFilter);
+extern void EMACPowerManagementControlSet(uint32_t ui32Base,
+                                          uint32_t ui32Flags);
+extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base);
+extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_EMAC_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/epi.c b/bsp/tm4c129x/libraries/driverlib/epi.c
new file mode 100644
index 0000000000..2fc44eabb3
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/epi.c
@@ -0,0 +1,2187 @@
+//*****************************************************************************
+//
+// epi.c - Driver for the EPI module.
+//
+// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_epi.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/epi.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! \addtogroup epi_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Helper masks for chip select configuration options.
+//
+//*****************************************************************************
+#define EPI_HB8_CS_MASK         (EPI_HB8_MODE_FIFO | EPI_HB8_RDWAIT_3 |       \
+                                 EPI_HB8_WRWAIT_3 | EPI_HB8_RDHIGH |          \
+                                 EPI_HB8_WRHIGH | EPI_HB8_ALE_HIGH)
+
+#define EPI_HB16_CS_MASK        (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC)
+
+//*****************************************************************************
+//
+// Ensure that erratum workaround inline functions have a public version
+// available in exactly one object module (this one).
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Safely writes a word to the EPI 0x10000000 address space.
+//!
+//! \param pui32Addr is the address which is to be written.
+//! \param ui32Value is the 32-bit word to write.
+//!
+//! This function must be used when writing words to EPI-attached memory
+//! configured to use the address space at 0x10000000 on devices affected by
+//! the EPI#01 erratum.  Direct access to memory in these cases can cause data
+//! corruption depending upon memory accesses immediately before or after the
+//! EPI access but using this function will allow EPI accesses to complete
+//! correctly. The function is defined as ``inline'' in epi.h.
+//!
+//! Use of this function on a device not affected by the erratum is safe but
+//! will impact performance due to an additional overhead of at least 2 cycles
+//! per access.  This erratum affects only the 0x10000000 address space
+//! typically used to store the LCD controller frame buffer.  The 0x60000000
+//! address space is not affected and applications using this address mapping
+//! need not use this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value);
+
+//*****************************************************************************
+//
+//! Safely reads a word from the EPI 0x10000000 address space.
+//!
+//! \param pui32Addr is the address which is to be read.
+//!
+//! This function must be used when reading words from EPI-attached memory
+//! configured to use the address space at 0x10000000 on devices affected by
+//! the EPI#01 erratum.  Direct access to memory in these cases can cause data
+//! corruption depending upon memory accesses immediately before or after the
+//! EPI access but using this function will allow EPI accesses to complete
+//! correctly. The function is defined as ``inline'' in epi.h.
+//!
+//! Use of this function on a device not affected by the erratum is safe but
+//! will impact performance due to an additional overhead of at least 2 cycles
+//! per access.  This erratum affects only the 0x10000000 address space
+//! typically used to store the LCD controller frame buffer.  The 0x60000000
+//! address space is not affected and applications using this address mapping
+//! need not use this function.
+//!
+//! \return The 32-bit word stored at address \e pui32Addr.
+//
+//*****************************************************************************
+extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr);
+
+//*****************************************************************************
+//
+//! Safely writes a half-word to the EPI 0x10000000 address space.
+//!
+//! \param pui16Addr is the address which is to be written.
+//! \param ui16Value is the 16-bit half-word to write.
+//!
+//! This function must be used when writing half-words to EPI-attached memory
+//! configured to use the address space at 0x10000000 on devices affected by
+//! the EPI#01 erratum.  Direct access to memory in these cases can cause data
+//! corruption depending upon memory accesses immediately before or after the
+//! EPI access but using this function will allow EPI accesses to complete
+//! correctly. The function is defined as ``inline'' in epi.h.
+//!
+//! Use of this function on a device not affected by the erratum is safe but
+//! will impact performance due to an additional overhead of at least 2 cycles
+//! per access.  This erratum affects only the 0x10000000 address space
+//! typically used to store the LCD controller frame buffer.  The 0x60000000
+//! address space is not affected and applications using this address mapping
+//! need not use this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value);
+
+//*****************************************************************************
+//
+//! Safely reads a half-word from the EPI 0x10000000 address space.
+//!
+//! \param pui16Addr is the address which is to be read.
+//!
+//! This function must be used when reading half-words from EPI-attached memory
+//! configured to use the address space at 0x10000000 on devices affected by
+//! the EPI#01 erratum.  Direct access to memory in these cases can cause data
+//! corruption depending upon memory accesses immediately before or after the
+//! EPI access but using this function will allow EPI accesses to complete
+//! correctly. The function is defined as ``inline'' in epi.h.
+//!
+//! Use of this function on a device not affected by the erratum is safe but
+//! will impact performance due to an additional overhead of at least 2 cycles
+//! per access.  This erratum affects only the 0x10000000 address space
+//! typically used to store the LCD controller frame buffer.  The 0x60000000
+//! address space is not affected and applications using this address mapping
+//! need not use this function.
+//!
+//! \return The 16-bit word stored at address \e pui16Addr.
+//
+//*****************************************************************************
+extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr);
+
+//*****************************************************************************
+//
+//! Safely writes a byte to the EPI 0x10000000 address space.
+//!
+//! \param pui8Addr is the address which is to be written.
+//! \param ui8Value is the 8-bit byte to write.
+//!
+//! This function must be used when writing bytes to EPI-attached memory
+//! configured to use the address space at 0x10000000 on devices affected by
+//! the EPI#01 erratum.  Direct access to memory in these cases can cause data
+//! corruption depending upon memory accesses immediately before or after the
+//! EPI access but using this function will allow EPI accesses to complete
+//! correctly. The function is defined as ``inline'' in epi.h.
+//!
+//! Use of this function on a device not affected by the erratum is safe but
+//! will impact performance due to an additional overhead of at least 2 cycles
+//! per access.  This erratum affects only the 0x10000000 address space
+//! typically used to store the LCD controller frame buffer.  The 0x60000000
+//! address space is not affected and applications using this address mapping
+//! need not use this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value);
+
+//*****************************************************************************
+//
+//! Safely reads a byte from the EPI 0x10000000 address space.
+//!
+//! \param pui8Addr is the address which is to be read.
+//!
+//! This function must be used when reading bytes from EPI-attached memory
+//! configured to use the address space at 0x10000000 on devices affected by
+//! the EPI#01 erratum.  Direct access to memory in these cases can cause data
+//! corruption depending upon memory accesses immediately before or after the
+//! EPI access but using this function will allow EPI accesses to complete
+//! correctly. The function is defined as ``inline'' in epi.h.
+//!
+//! Use of this function on a device not affected by the erratum is safe but
+//! will impact performance due to an additional overhead of at least 2 cycles
+//! per access.  This erratum affects only the 0x10000000 address space
+//! typically used to store the LCD controller frame buffer.  The 0x60000000
+//! address space is not affected and applications using this address mapping
+//! need not use this function.
+//!
+//! \return The 8-bit byte stored at address \e pui8Addr.
+//
+//*****************************************************************************
+extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr);
+
+//*****************************************************************************
+//
+//! Sets the usage mode of the EPI module.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Mode is the usage mode of the EPI module.
+//!
+//! This functions sets the operating mode of the EPI module.  The parameter
+//! \e ui32Mode must be one of the following:
+//!
+//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation
+//! - \b EPI_MODE_SDRAM - use with SDRAM device
+//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
+//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface
+//! - \b EPI_MODE_DISABLE - disable the EPI module
+//!
+//! Selection of any of the above modes enables the EPI module, except
+//! for \b EPI_MODE_DISABLE, which is used to disable the module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT((ui32Mode == EPI_MODE_GENERAL) ||
+           (ui32Mode == EPI_MODE_SDRAM) ||
+           (ui32Mode == EPI_MODE_HB8) ||
+           (ui32Mode == EPI_MODE_HB16) ||
+           (ui32Mode == EPI_MODE_DISABLE));
+
+    //
+    // Write the mode word to the register.
+    //
+    HWREG(ui32Base + EPI_O_CFG) = ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Sets the clock divider for the EPI module's CS0n/CS1n.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Divider is the value of the clock divider to be applied to
+//! the external interface (0-65535).
+//!
+//! This function sets the clock divider(s) that is used to determine the
+//! clock rate of the external interface.  The \e ui32Divider value is used to
+//! derive the EPI clock rate from the system clock based on the following
+//! formula.
+//!
+//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
+//!
+//! For example, a divider value of 1 results in an EPI clock rate of half
+//! the system clock, value of 2 or 3 yields one quarter of the system clock
+//! and a value of 4 results in one sixth of the system clock rate.
+//!
+//! In cases where a dual chip select mode is in use and different clock rates
+//! are required for each chip select, the \e ui32Divider parameter must
+//! contain two dividers.  The lower 16 bits define the divider to be used with
+//! CS0n and the upper 16 bits define the divider for CS1n.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // Write the divider value to the register.
+    //
+    HWREG(ui32Base + EPI_O_BAUD) = ui32Divider;
+}
+
+//*****************************************************************************
+//
+//! Sets the clock divider for the specified CS in the EPI module.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select to modify and has a valid range of 0-3.
+//! \param ui32Divider is the value of the clock divider to be applied to
+//! the external interface (0-65535).
+//!
+//! This function sets the clock divider(s) for the specified CS that is used
+//! to determine the clock rate of the external interface.  The \e ui32Divider
+//! value is used to derive the EPI clock rate from the system clock based on
+//! the following formula.
+//!
+//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
+//!
+//! For example, a divider value of 1 results in an EPI clock rate of half
+//! the system clock, value of 2 or 3 yields one quarter of the system clock
+//! and a value of 4 results in one sixth of the system clock rate.
+//!
+//! \note The availability of CS2n and CS3n varies based on the Tiva part
+//! in use.  Please consult the data sheet to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS,
+                uint32_t ui32Divider)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Write the divider value to the register bitfield.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Reg = HWREG(ui32Base + EPI_O_BAUD) & ~(0xffff << (16 * ui32CS));
+        ui32Reg |= ((ui32Divider & 0xffff) << (16 * ui32CS));
+        HWREG(ui32Base + EPI_O_BAUD) = ui32Reg;
+    }
+    else
+    {
+        ui32Reg = (HWREG(ui32Base + EPI_O_BAUD2) &
+                   ~(0xffff << (16 * (ui32CS - 2))));
+        ui32Reg |= ((ui32Divider & 0xffff) << (16 * (ui32CS - 2)));
+        HWREG(ui32Base + EPI_O_BAUD2) = ui32Reg;
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer count for uDMA transmit operations on EPI.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Count is the number of units to transmit by uDMA to WRFIFO.
+//!
+//! This function is used to help configure the EPI uDMA transmit operations.
+//! A non-zero transmit count in combination with a FIFO threshold trigger
+//! asserts an EPI uDMA transmit.
+//!
+//! Note that, although the EPI peripheral can handle counts of up to 65535,
+//! a single uDMA transfer has a maximum length of 1024 units so \e ui32Count
+//! should be set to values less than or equal to 1024.
+//!
+//! \note The availability of the EPI DMA TX count varies based on the
+//! Tiva part in use.  Please consult the data sheet to determine if this
+//! feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Count <= 1024);
+
+    //
+    // Assign the DMA TX count value provided.
+    //
+    HWREG(ui32Base + EPI_O_DMATXCNT) = ui32Count & 0xffff;
+}
+
+//*****************************************************************************
+//
+//! Configures the SDRAM mode of operation.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Config is the SDRAM interface configuration.
+//! \param ui32Refresh is the refresh count in core clocks (0-2047).
+//!
+//! This function is used to configure the SDRAM interface, when the SDRAM
+//! mode is chosen with the function EPIModeSet().  The parameter
+//! \e ui32Config is the logical OR of several sets of choices:
+//!
+//! The processor core frequency must be specified with one of the following:
+//!
+//! - \b EPI_SDRAM_CORE_FREQ_0_15 defines core clock as 0 MHz < clk <= 15 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_15_30 defines core clock as 15 MHz < clk <= 30 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_30_50 defines core clock as 30 MHz < clk <= 50 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_50_100 defines core clock as 50 MHz < clk <=
+//!   100 MHz
+//!
+//! The low power mode is specified with one of the following:
+//!
+//! - \b EPI_SDRAM_LOW_POWER enter low power, self-refresh state.
+//! - \b EPI_SDRAM_FULL_POWER normal operating state.
+//!
+//! The SDRAM device size is specified with one of the following:
+//!
+//! - \b EPI_SDRAM_SIZE_64MBIT size is a 64 Mbit device (8 MB).
+//! - \b EPI_SDRAM_SIZE_128MBIT size is a 128 Mbit device (16 MB).
+//! - \b EPI_SDRAM_SIZE_256MBIT size is a 256 Mbit device (32 MB).
+//! - \b EPI_SDRAM_SIZE_512MBIT size is a 512 Mbit device (64 MB).
+//!
+//! The parameter \e ui16Refresh sets the refresh counter in units of core
+//! clock ticks.  It is an 11-bit value with a range of 0 - 2047 counts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config,
+                  uint32_t ui32Refresh)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Refresh < 2048);
+
+    //
+    // Fill in the refresh count field of the configuration word.
+    //
+    ui32Config &= ~EPI_SDRAMCFG_RFSH_M;
+    ui32Config |= ui32Refresh << EPI_SDRAMCFG_RFSH_S;
+
+    //
+    // Write the SDRAM configuration register.
+    //
+    HWREG(ui32Base + EPI_O_SDRAMCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for Host-bus 8 operation.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Config is the interface configuration.
+//! \param ui32MaxWait is the maximum number of external clocks to wait
+//! if a FIFO ready signal is holding off the transaction, 0-255.
+//!
+//! This function is used to configure the interface when used in host-bus 8
+//! operation as chosen with the function EPIModeSet().  The parameter
+//! \e ui32Config is the logical OR of the following:
+//!
+//! - Host-bus 8 submode, select one of:
+//!   - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0]
+//!   - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0]
+//!   - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address
+//!     switch for multiple reads instead of OEn strobing, D[7:0]
+//!   - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO
+//!     empty, D[7:0]
+//!
+//! - \b EPI_HB8_USE_TXEMPTY enables TXEMPTY signal with FIFO
+//! - \b EPI_HB8_USE_RXFULL enables RXFULL signal with FIFO
+//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is
+//!   active low
+//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is
+//!   active low
+//!
+//! - Write wait state when \b EPI_HB8_BAUD is used, select one of:
+//!   - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default)
+//!   - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks
+//!   - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks
+//!   - \b EPI_HB8_WRWAIT_3  sets write wait state to 8 EPI clocks
+//!
+//! - Read wait state when \b EPI_HB8_BAUD is used, select one of:
+//!   - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default)
+//!   - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks
+//!   - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks
+//!   - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks
+//!
+//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the
+//!   correct byte lanes allowing data to be stored in bits [31:8].  If absent,
+//!   all data transfers use bits [7:0].
+//!
+//! - \b EPI_HB8_CLOCK_GATE_IDLE sets the EPI clock to be held low when no data
+//!   is available to read or write
+//! - \b EPI_HB8_CLOCK_INVERT inverts the EPI clock
+//! - \b EPI_HB8_IN_READY_EN sets EPIS032 as a ready/stall signal, active high
+//! - \b EPI_HB8_IN_READY_EN_INVERT sets EPIS032 as ready/stall signal, active
+//!   low
+//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default)
+//! - \b EPI_HB8_ALE_LOW sets address latch active low
+//! - \b EPI_HB8_CSBAUD use different baud rates when accessing devices on each
+//!   chip select.  CS0n uses the baud rate specified by the lower 16 bits
+//!   of the divider passed to EPIDividerSet() and CS1n uses the divider passed
+//!   in the upper 16 bits.  If this option is absent, both chip selects use
+//!   the baud rate resulting from the divider in the lower 16 bits of the
+//!   parameter passed to EPIDividerSet().
+//!
+//! In addition, some parts support CS2n and CS3n for a total of 4 chip
+//! selects.  If \b EPI_HB8_CSBAUD is configured, EPIDividerCSSet() should be
+//! used to to configure the divider for CS2n and CS3n.  They both also use the
+//! lower 16 bits passed to EPIDividerSet() if this option is absent.
+//!
+//! The use of \b EPI_HB8_CSBAUD also allows for unique chip select
+//! configurations.  CS0n, CS1n, CS2n, and CS3n can each be configured by
+//! calling EPIConfigHB8CSSet() if \b EPI_HB8_CSBAUD is used.  Otherwise, the
+//! configuration provided in \e ui32Config is used for all chip selects
+//! enabled.
+//!
+//! - Chip select configuration, select one of:
+//!   - \b EPI_HB8_CSCFG_CS sets EPIS030 to operate as a chip select signal.
+//!   - \b EPI_HB8_CSCFG_ALE sets EPIS030 to operate as an address latch
+//!     (ALE).
+//!   - \b EPI_HB8_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027
+//!     as CS1n with the asserted chip select determined from the most
+//!     significant address bit for the respective external address map.
+//!   - \b EPI_HB8_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE),
+//!     EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select
+//!     determined from the most significant address bit for the respective
+//!     external address map.
+//!   - \b EPI_HB8_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address
+//!     latch (ALE) and EPIS027 is used as a chip select.
+//!   - \b EPI_HB8_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n,
+//!     EPIS034 as CS2n and EPIS033 as CS3n.
+//!   - \b EPI_HB8_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch (ALE),
+//!     EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n.
+//!   \note Dual or quad chip select configurations cannot be used with
+//!         EPI_HB8_MODE_SRAM.
+//!
+//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen.  If a
+//! FIFO is used aint32_t with RXFULL or TXEMPTY ready signals, then this
+//! parameter determines the maximum number of clocks to wait when the
+//! transaction is being held off by by the FIFO using one of these ready
+//! signals.  A value of 0 means to wait forever.
+//!
+//! \note  Availability of configuration options varies based on the Tiva
+//! part in use.  Please consult the data sheet to determine if the features
+//! desired are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config,
+                uint32_t ui32MaxWait)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32MaxWait < 256);
+
+    //
+    // Determine the CS and word access modes.
+    //
+    HWREG(ui32Base + EPI_O_HB8CFG2) =
+        ((ui32Config & EPI_HB8_CSBAUD) ? EPI_HB8CFG2_CSBAUD : 0) |
+        ((ui32Config & EPI_HB8_CSCFG_MASK) << 15);
+
+    //
+    // Fill in the max wait field of the configuration word.
+    //
+    ui32Config &= ~EPI_HB8CFG_MAXWAIT_M;
+    ui32Config |= ui32MaxWait << EPI_HB8CFG_MAXWAIT_S;
+
+    //
+    // Write the main HostBus8 configuration register.
+    //
+    HWREG(ui32Base + EPI_O_HB8CFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for Host-bus 16 operation.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Config is the interface configuration.
+//! \param ui32MaxWait is the maximum number of external clocks to wait
+//! if a FIFO ready signal is holding off the transaction.
+//!
+//! This function is used to configure the interface when used in Host-bus 16
+//! operation as chosen with the function EPIModeSet().  The parameter
+//! \e ui32Config is the logical OR of the following:
+//! - Host-bus 16 submode, select one of:
+//!     - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0].
+//!     - \b EPI_HB16_MODE_ADDEMUX sets up data and address as separate,
+//!       D[15:0].
+//!     - \b EPI_HB16_MODE_SRAM sets as \b EPI_HB16_MODE_ADDEMUX but uses
+//!       address switch for multiple reads instead of OEn strobing, D[15:0].
+//!     - \b EPI_HB16_MODE_FIFO addes XFIFO controls with sense of XFIFO full
+//!       and XFIFO empty, D[15:0].  This submode uses no address or ALE.
+//!
+//! - \b EPI_HB16_USE_TXEMPTY enables TXEMPTY signal with FIFO.
+//! - \b EPI_HB16_USE_RXFULL enables RXFULL signal with FIFO.
+//! - \b EPI_HB16_WRHIGH use active high write strobe, otherwise it is
+//!   active low.
+//! - \b EPI_HB16_RDHIGH use active high read strobe, otherwise it is
+//!   active low.
+//! - Write wait state, select one of:
+//!     - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks.
+//!     - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks.
+//!     - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks.
+//!     - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks.
+//!
+//! - Read wait state, select one of:
+//!     - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks.
+//!     - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks.
+//!     - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks.
+//!     - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks.
+//!
+//! - \b EPI_HB16_WORD_ACCESS use Word Access mode to route bytes to the
+//!   correct byte lanes allowing data to be stored in bits [31:16].  If
+//!   absent, all data transfers use bits [15:0].
+//!
+//! \note \b EPI_HB16_WORD_ACCESS is not available on all parts.  Please
+//! consult the data sheet to determine if this feature is available.
+//!
+//! - \b EPI_HB16_CLOCK_GATE_IDLE holds the EPI clock low when no data is
+//!   available to read or write.
+//! - \b EPI_HB16_CLOCK_INVERT inverts the EPI clock.
+//! - \b EPI_HB16_IN_READY_EN sets EPIS032 as a ready/stall signal, active
+//!   high.
+//! - \b EPI_HB16_IN_READY_EN_INVERTED sets EPIS032 as ready/stall signal,
+//!   active low.
+//! - Address latch logic, select one of:
+//!     - \b EPI_HB16_ALE_HIGH sets the address latch active high (default).
+//!     - \b EPI_HB16_ALE_LOW sets address latch active low.
+//!
+//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic.  Only valid with
+//!   \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an
+//!   ALE.
+//! - \b EPI_HB16_BSEL enables byte selects.  In this mode, two EPI signals
+//!   operate as byte selects allowing 8-bit transfers.  If this flag is not
+//!   specified, data must be read and written using only 16-bit transfers.
+//! - \b EPI_HB16_CSBAUD use different baud rates when accessing devices
+//!   on each chip select.  CS0n uses the baud rate specified by the lower 16
+//!   bits of the divider passed to EPIDividerSet() and CS1n uses the divider
+//!   passed in the upper 16 bits.  If this option is absent, both chip selects
+//!   use the baud rate resulting from the divider in the lower 16 bits of the
+//!   parameter passed to EPIDividerSet().
+//!
+//! In addition, some parts support CS2n and CS3n for a total of 4 chip
+//! selects.  If \b EPI_HB16_CSBAUD is configured, EPIDividerCSSet() should be
+//! used to to configure the divider for CS2n and CS3n.  They both also use the
+//! lower 16 bits passed to EPIDividerSet() if this option is absent.
+//!
+//! The use of \b EPI_HB16_CSBAUD also allows for unique chip select
+//! configurations.  CS0n, CS1n, CS2n, and CS3n can each be configured by
+//! calling EPIConfigHB16CSSet() if \b EPI_HB16_CSBAUD is used.  Otherwise, the
+//! configuration provided in \e ui32Config is used for all chip selects.
+//!
+//! - Chip select configuration, select one of:
+//!     - \b EPI_HB16_CSCFG_CS sets EPIS030 to operate as a chip select signal.
+//!     - \b EPI_HB16_CSCFG_ALE sets EPIS030 to operate as an address latch
+//!       (ALE).
+//!     - \b EPI_HB16_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027
+//!       as CS1n with the asserted chip select determined from the most
+//!       significant address bit for the respective external address map.
+//!     - \b EPI_HB16_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE),
+//!       EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select
+//!       determined from the most significant address bit for the respective
+//!       external address map.
+//!     - \b EPI_HB16_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address
+//!       latch (ALE) and EPIS027 is used as a chip select.
+//!     - \b EPI_HB16_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n,
+//!       EPIS034 as CS2n and EPIS033 as CS3n.
+//!     - \b EPI_HB16_CSCFG_ALE_QUAD_CS sets EPIS030 as an  address latch
+//!       (ALE), EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033
+//!       as CS3n.
+//!   \note Dual or quad chip select configurations cannot be used with
+//!         EPI_HB16_MODE_SRAM.
+//!
+//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen.  If a
+//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
+//! parameter determines the maximum number of clocks to wait when the
+//! transaction is being held off by by the FIFO using one of these ready
+//! signals.  A value of 0 means to wait forever.
+//!
+//! \note  Availability of configuration options varies based on the Tiva
+//! part in use.  Please consult the data sheet to determine if the features
+//! desired are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32MaxWait < 256);
+
+    //
+    // Determine the CS and word access modes.
+    //
+    HWREG(ui32Base + EPI_O_HB16CFG2) =
+        ((ui32Config & EPI_HB16_CSBAUD) ? EPI_HB16CFG2_CSBAUD : 0) |
+        ((ui32Config & EPI_HB16_CSCFG_MASK) << 15);
+
+    //
+    // Fill in the max wait field of the configuration word.
+    //
+    ui32Config &= ~EPI_HB16CFG_MAXWAIT_M;
+    ui32Config |= ui32MaxWait << EPI_HB16CFG_MAXWAIT_S;
+
+    //
+    // Write the main HostBus16 configuration register.
+    //
+    HWREG(ui32Base + EPI_O_HB16CFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the individual chip select configuration for the Host-bus 8 interface.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select value to configure.
+//! \param ui32Config is the configuration settings.
+//!
+//! This function is used to configure individual chip select settings for the
+//! Host-bus 8 interface mode.  EPIConfigHB8Set() must have been setup with
+//! the \b EPI_HB8_CSBAUD flag for the individual chip select configuration
+//! option to be available.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.  The parameter \e ui32Config is the logical OR of the
+//! following:
+//!
+//! - Host-bus 8 submode, select one of:
+//!     - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0].
+//!     - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0].
+//!     - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address
+//!       switch for multiple reads instead of OEn strobing, D[7:0].
+//!     - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO
+//!       empty, D[7:0].  This is only available for CS0n and CS1n.
+//!
+//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is
+//!   active low.
+//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is
+//!   active low.
+//! - Write wait state when \b EPI_HB8_BAUD is used, select one of:
+//!     - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default).
+//!     - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks.
+//!     - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks.
+//!     - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks.
+//! - Read wait state when \b EPI_HB8_BAUD is used, select one of:
+//!     - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default).
+//!     - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks.
+//!     - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks.
+//!     - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks.
+//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default).
+//! - \b EPI_HB8_ALE_LOW sets address latch active low.
+//!
+//! \note The availability of a unique chip select configuration within
+//! Host-bus 8 interface mode varies based on the Tiva part in use.
+//! Please consult the data sheet to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
+{
+    uint32_t ui32Offset, ui32Reg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Determine the register offset based on the ui32CS provided.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Offset = EPI_O_HB8CFG + (ui32CS << 2);
+    }
+    else
+    {
+        ui32Offset = EPI_O_HB8CFG3 + ((ui32CS - 2) << 2);
+    }
+
+    //
+    // Preserve the bits that will not be modified.
+    //
+    ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB8_CS_MASK;
+
+    //
+    // Write the target chip select HostBus8 configuration fields.
+    //
+    HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config);
+}
+
+//*****************************************************************************
+//
+//! Sets the individual chip select configuration for the Host-bus 16
+//! interface.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select value to configure.
+//! \param ui32Config is the configuration settings.
+//!
+//! This function is used to configure individual chip select settings for the
+//! Host-bus 16 interface mode.  EPIConfigHB16Set() must have been set up with
+//! the \b EPI_HB16_CSBAUD flag for the individual chip select configuration
+//! option to be available.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The  \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of  0-3.  The parameter \e ui32Config is the logical OR the
+//! following:
+//!
+//! - Host-bus 16 submode, select one of:
+//!     - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0].
+//!     - \b EPI_HB16_MODE_ADDEMUX sets up data and address separate, D[15:0].
+//!     - \b EPI_HB16_MODE_SRAM same as \b EPI_HB8_MODE_ADDEMUX, but uses
+//!       address switch for multiple reads instead of OEn strobing, D[15:0].
+//!     - \b EPI_HB16_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO
+//!       empty, D[15:0].  This feature is only available on CS0n and CS1n.
+//! - \b EPI_HB16_WRHIGH sets active high write strobe, otherwise it is
+//!   active low.
+//! - \b EPI_HB16_RDHIGH sets active high read strobe, otherwise it is
+//!   active low.
+//! - Write wait state when \b EPI_HB16_BAUD is used, select one of:
+//!     - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks (default).
+//!     - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks.
+//!     - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks.
+//!     - \b EPI_HB16_WRWAIT_3  sets write wait state to 8 EPI clocks.
+//! - Read wait state when \b EPI_HB16_BAUD is used, select one of:
+//!     - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks (default).
+//!     - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks.
+//!     - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks.
+//!     - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks.
+//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default).
+//! - \b EPI_HB16_ALE_LOW sets address latch active low.
+//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic.  Only valid with
+//!   \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an
+//!   ALE.
+//!
+//! \note The availability of the unique chip select configuration within the
+//! Host-bus 16 interface mode varies based on the Tiva part in use.
+//! Please consult the data sheet to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
+{
+    uint32_t ui32Offset, ui32Reg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Determine the register offset based on the ui32CS provided.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
+    }
+    else
+    {
+        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
+    }
+
+    //
+    // Preserve the bits that will not be modified.
+    //
+    ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB16_CS_MASK;
+
+    //
+    // Write the target chip select HostBus16 configuration fields.
+    //
+    HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config);
+}
+
+//*****************************************************************************
+//
+//! Sets the individual chip select timing settings for the Host-bus 8
+//! interface.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select value to configure.
+//! \param ui32Config is the configuration settings.
+//!
+//! This function is used to set individual chip select timings for the
+//! Host-bus 8 interface mode.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.  The parameter \e ui32Config is the logical OR of the
+//! following:
+//!
+//! - Input ready stall delay, select one of:
+//!     - \b EPI_HB8_IN_READY_DELAY_1 sets the stall on input ready (EPIS032)
+//!     to start 1 EPI clock after signaled.
+//!     - \b EPI_HB8_IN_READY_DELAY_2 sets the stall on input ready (EPIS032)
+//!     to start 2 EPI clocks after signaled.
+//!     - \b EPI_HB8_IN_READY_DELAY_3 sets the stall on input ready (EPIS032)
+//!     to start 3 EPI clocks after signaled.
+//!
+//! - Host bus transfer delay, select one of:
+//!     - \b EPI_HB8_CAP_WIDTH_1 defines the inter-transfer capture width to
+//!     create a delay of 1 EPI clock.
+//!     - \b EPI_HB8_CAP_WIDTH_2 defines the inter-transfer capture width
+//!     to create a delay of 2 EPI clocks.
+//!
+//! - \b EPI_HB8_WRWAIT_MINUS_DISABLE disables the additional write wait state
+//! reduction.
+//! - \b EPI_HB8_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait state
+//! reduction.
+//! - \b EPI_HB8_RDWAIT_MINUS_DISABLE disables the additional read wait state
+//! reduction.
+//! - \b EPI_HB8_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state
+//!reduction.
+//!
+//! \note The availability of unique chip select timings within Host-bus 8
+//! interface mode varies based on the Tiva part in use.  Please consult
+//! the data sheet to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Write the target chip select HostBus8 timing register.
+    //
+    HWREG(ui32Base + (EPI_O_HB8TIME + (ui32CS << 2))) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the individual chip select timing settings for the Host-bus 16
+//! interface.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select value to configure.
+//! \param ui32Config is the configuration settings.
+//!
+//! This function is used to set individual chip select timings for the
+//! Host-bus 16 interface mode.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.  The parameter \e ui32Config is the logical OR of the
+//! following:
+//!
+//! - Input ready stall delay, select one of:
+//!     - \b EPI_HB16_IN_READY_DELAY_1 sets the stall on input ready (EPIS032)
+//!     to start 1 EPI clock after signaled.
+//!     - \b EPI_HB16_IN_READY_DELAY_2 sets the stall on input ready (EPIS032)
+//!     to start 2 EPI clocks after signaled.
+//!     - \b EPI_HB16_IN_READY_DELAY_3 sets the stall on input ready (EPIS032)
+//!     to start 3 EPI clocks after signaled.
+//!
+//! - PSRAM size limitation, select one of:
+//!     - \b EPI_HB16_PSRAM_NO_LIMIT defines no row size limitation.
+//!     - \b EPI_HB16_PSRAM_128 defines the PSRAM row size to 128 bytes.
+//!     - \b EPI_HB16_PSRAM_256 defines the PSRAM row size to 256 bytes.
+//!     - \b EPI_HB16_PSRAM_512 defines the PSRAM row size to 512 bytes.
+//!     - \b EPI_HB16_PSRAM_1024 defines the PSRAM row size to 1024 bytes.
+//!     - \b EPI_HB16_PSRAM_2048 defines the PSRAM row size to 2048 bytes.
+//!     - \b EPI_HB16_PSRAM_4096 defines the PSRAM row size to 4096 bytes.
+//!     - \b EPI_HB16_PSRAM_8192 defines the PSRAM row size to 8192 bytes.
+//!
+//! - Host bus transfer delay, select one of:
+//!     - \b EPI_HB16_CAP_WIDTH_1 defines the inter-transfer capture width to
+//!     create a delay of 1 EPI clock
+//!     - \b EPI_HB16_CAP_WIDTH_2 defines the inter-transfer capture width
+//!     to create a delay of 2 EPI clocks.
+//!
+//! - Write wait state timing reduction, select one of:
+//!     - \b EPI_HB16_WRWAIT_MINUS_DISABLE disables the additional write wait
+//!     state reduction.
+//!     - \b EPI_HB16_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait
+//!     state reduction.
+//!
+//! - Read wait state timing reduction, select one of:
+//!     - \b EPI_HB16_RDWAIT_MINUS_DISABLE disables the additional read wait
+//!     state reduction.
+//!     - \b EPI_HB16_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state
+//!     reduction.
+//!
+//! \note The availability of unique chip select timings within Host-bus 16
+//! interface mode varies based on the Tiva part in use.  Please consult
+//! the data sheet to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Write the target chip select HostBus16 timing register.
+    //
+    HWREG(ui32Base + (EPI_O_HB16TIME + (ui32CS << 2))) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the PSRAM configuration register.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select target.
+//! \param ui32CR is the PSRAM configuration register value.
+//!
+//! This function sets the PSRAM's configuration register by using the PSRAM
+//! configuration register enable signal.  The Host-bus 16 interface mode
+//! should be configured prior to calling this function.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.  The parameter \e ui32CR value is determined by
+//! consulting the PSRAM's data sheet.
+//!
+//! \note The availability of PSRAM support varies based on the Tiva part
+//! in use.  Please consult the data sheet to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Determine the register offset based on the ui32CS provided.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
+    }
+    else
+    {
+        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
+    }
+
+    //
+    // Setup for the PSRAM configuration register write.  Only 21 bits are
+    // valid on a write.
+    //
+    HWREG(ui32Base + EPI_O_HBPSRAM) = (ui32CR & 0x1fffff);
+
+    //
+    // Set the PSRAM configuration register write enable.
+    //
+    HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_WRCRE;
+}
+
+//*****************************************************************************
+//
+//! Requests a configuration register read from the PSRAM.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select target.
+//!
+//! This function requests a read of the PSRAM's configuration register.  The
+//! Host-bus 16 interface mode should be configured prior to calling this
+//! function.
+//! The EPIPSRAMConfigRegGet() and EPIPSRAMConfigRegGetNonBlocking() can
+//! be used to retrieve the configuration register value.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.
+//!
+//! \note The availability of PSRAM support varies based on the Tiva part
+//! in use.  Please consult the data sheet to determine if this feature is
+//! available.
+//!
+//! \return none.
+//
+//*****************************************************************************
+void
+EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Determine the register offset based on the ui32CS provided.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
+    }
+    else
+    {
+        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
+    }
+
+    //
+    // Set the PSRAM configuration register read enable.
+    //
+    HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_RDCRE;
+}
+
+//*****************************************************************************
+//
+//! Retrieves the contents of the EPI PSRAM configuration register.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select target.
+//! \param pui32CR is the provided storage used to hold the register value.
+//!
+//! This function copies the contents of the EPI PSRAM configuration register
+//! to the provided storage if the PSRAM read configuration register enable
+//! is no longer asserted.  Otherwise the provided storage is not modified.
+//!
+//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead()
+//! should be called prior to calling this function.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.  The \e pui32CR parameter is a pointer to provided
+//! storage used to hold the register value.
+//!
+//! \note The availability of PSRAM support varies based on the Tiva part
+//! in use.  Please consult the data sheet to determine if this feature is
+//! available.
+//!
+//! \return \b true if the value was copied to the provided storage and
+//! \b false if it was not.
+//
+//*****************************************************************************
+bool
+EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS,
+                                uint32_t *pui32CR)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Determine the register offset based on the ui32CS provided.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
+    }
+    else
+    {
+        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
+    }
+
+    //
+    // Verify PSRAM read enable is not asserted.
+    //
+    if(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE)
+    {
+        return(false);
+    }
+
+    //
+    // Copy the PSRAM configuration register value to the provided storage.
+    // Only the lower 16 bits are valid on a read.
+    //
+    *pui32CR = HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff;
+
+    //
+    // Notify caller the provided storage holds the EPI PSRAM configuration
+    // register contents.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Retrieves the contents of the EPI PSRAM configuration register.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32CS is the chip select target.
+//!
+//! This function retrieves the EPI PSRAM configuration register.  The register
+//! is read once the EPI PSRAM configuration register read enable signal is
+//! de-asserted.
+//!
+//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead()
+//! should be called prior to calling this function.
+//!
+//! The \e ui32Base parameter is the base address for the EPI hardware module.
+//! The \e ui32CS parameter specifies the chip select to configure and has a
+//! valid range of 0-3.
+//!
+//! \note The availability of PSRAM support varies based on the Tiva part
+//! in use.  Please consult the data sheet to determine if this feature is
+//! available.
+//!
+//! \return none.
+//
+//*****************************************************************************
+uint32_t
+EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32CS < 4);
+
+    //
+    // Determine the register offset based on the ui32CS provided.
+    //
+    if(ui32CS < 2)
+    {
+        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
+    }
+    else
+    {
+        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
+    }
+
+    //
+    // Wait for PSRAM read enable to deassert if necessary.
+    //
+    while(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE)
+    {
+    }
+
+    //
+    // Return the EPI PSRAM configuration register contents.
+    // Only the lower 16 bits are valid on a read.
+    //
+    return(HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff);
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for general-purpose mode operation.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Config is the interface configuration.
+//! \param ui32FrameCount is the frame size in clocks, if the frame signal
+//! is used (0-15).
+//! \param ui32MaxWait is currently not used.
+//!
+//! This function is used to configure the interface when used in
+//! general-purpose operation as chosen with the function EPIModeSet().  The
+//! parameter \e ui32Config is the logical OR of the following:
+//!
+//! - \b EPI_GPMODE_CLKPIN interface clock as output on a pin.
+//! - \b EPI_GPMODE_CLKGATE clock is stopped when there is no transaction,
+//!   otherwise it is free-running.
+//! - \b EPI_GPMODE_FRAME50 framing signal is 50/50 duty cycle, otherwise it
+//!   is a pulse.
+//! - \b EPI_GPMODE_WRITE2CYCLE a two-cycle write is used, otherwise a
+//!   single-cycle write is used.
+//! - Address bus size, select one of:
+//!     - \b EPI_GPMODE_ASIZE_NONE sets no address bus.
+//!     - \b EPI_GPMODE_ASIZE_4 sets an address bus size of 4 bits.
+//!     - \b EPI_GPMODE_ASIZE_12 sets an address bus size of 12 bits.
+//!     - \b EPI_GPMODE_ASIZE_20 sets an address bus size of 20 bits.
+//! - Data bus size, select one of:
+//!     - \b EPI_GPMODE_DSIZE_8 sets a data bus size of 8 bits.
+//!     - \b EPI_GPMODE_DSIZE_16 sets a data bus size of 16 bits.
+//!     - \b EPI_GPMODE_DSIZE_24 sets a data bus size of 24 bits.
+//!     - \b EPI_GPMODE_DSIZE_32 sets a data bus size of 32 bits.
+//!
+//! The parameter \e ui32FrameCount is the number of clocks used to form the
+//! framing signal, if the framing signal is used.  The behavior depends on
+//! whether the frame signal is a pulse or a 50/50 duty cycle.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config,
+                   uint32_t ui32FrameCount, uint32_t ui32MaxWait)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32FrameCount < 16);
+    ASSERT(ui32MaxWait < 256);
+
+    //
+    // Fill in the frame count field of the configuration word.
+    //
+    ui32Config &= ~EPI_GPCFG_FRMCNT_M;
+    ui32Config |= ui32FrameCount << EPI_GPCFG_FRMCNT_S;
+
+    //
+    // Write the non-moded configuration register.
+    //
+    HWREG(ui32Base + EPI_O_GPCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Configures the address map for the external interface.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Map is the address mapping configuration.
+//!
+//! This function is used to configure the address mapping for the external
+//! interface, which then determines the base address of the external memory or
+//! device within the processor peripheral and/or memory space.
+//!
+//! The parameter \e ui32Map is the logical OR of the following:
+//!
+//! - Peripheral address space size, select one of:
+//!     - \b EPI_ADDR_PER_SIZE_256B sets the peripheral address space to 256
+//! bytes.
+//!     - \b EPI_ADDR_PER_SIZE_64KB sets the peripheral address space to 64
+//! Kbytes.
+//!     - \b EPI_ADDR_PER_SIZE_16MB sets the peripheral address space to 16
+//! Mbytes.
+//!     - \b EPI_ADDR_PER_SIZE_256MB sets the peripheral address space to 256
+//! Mbytes.
+//! - Peripheral base address, select one of:
+//!     - \b EPI_ADDR_PER_BASE_NONE sets the peripheral base address to none.
+//!     - \b EPI_ADDR_PER_BASE_A sets the peripheral base address to
+//! 0xA0000000.
+//!     - \b EPI_ADDR_PER_BASE_C sets the peripheral base address to
+//! 0xC0000000.
+//! - RAM address space, select one of:
+//!     - \b EPI_ADDR_RAM_SIZE_256B sets the RAM address space to 256 bytes.
+//!     - \b EPI_ADDR_RAM_SIZE_64KB sets the RAM address space to 64 Kbytes.
+//!     - \b EPI_ADDR_RAM_SIZE_16MB sets the RAM address space to 16 Mbytes.
+//!     - \b EPI_ADDR_RAM_SIZE_256MB sets the RAM address space to 256 Mbytes.
+//! - RAM base address, select one of:
+//!     - \b EPI_ADDR_RAM_BASE_NONE sets the RAM space address to none.
+//!     - \b EPI_ADDR_RAM_BASE_6 sets the RAM space address to 0x60000000.
+//!     - \b EPI_ADDR_RAM_BASE_8 sets the RAM space address to 0x80000000.
+//! - \b EPI_ADDR_RAM_QUAD_MODE maps CS0n to 0x60000000, CS1n to 0x80000000,
+//! CS2n to 0xA0000000, and CS3n to 0xC0000000.
+//! - \b EPI_ADDR_CODE_SIZE_256B sets an external code size of 256 bytes, range
+//! 0x00 to 0xFF.
+//! - \b EPI_ADDR_CODE_SIZE_64KB sets an external code size of 64 Kbytes, range
+//! 0x0000 to 0xFFFF.
+//! - \b EPI_ADDR_CODE_SIZE_16MB sets an external code size of 16 Mbytes, range
+//! 0x000000 to 0xFFFFFF.
+//! - \b EPI_ADDR_CODE_SIZE_256MB sets an external code size of 256 Mbytes,
+//! range 0x0000000 to 0xFFFFFFF.
+//! - \b EPI_ADDR_CODE_BASE_NONE sets external code base to not mapped.
+//! - \b EPI_ADDR_CODE_BASE_1 sets external code base to 0x10000000.
+//!
+//! \note The availability of \b EPI_ADDR_RAM_QUAD_MODE and \b EPI_ADDR_CODE_*
+//! varies based on the Tiva part in use.  Please consult the data sheet
+//! to determine if these features are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Map < 0x1000);
+
+    //
+    // Set the value of the address mapping register.
+    //
+    HWREG(ui32Base + EPI_O_ADDRMAP) = ui32Map;
+}
+
+//*****************************************************************************
+//
+//! Configures a non-blocking read transaction.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Channel is the read channel (0 or 1).
+//! \param ui32DataSize is the size of the data items to read.
+//! \param ui32Address is the starting address to read.
+//!
+//! This function is used to configure a non-blocking read channel for a
+//! transaction.  Two channels are available that can be used in a ping-pong
+//! method for continuous reading.  It is not necessary to use both channels
+//! to perform a non-blocking read.
+//!
+//! The parameter \e ui8DataSize is one of \b EPI_NBCONFIG_SIZE_8,
+//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit,
+//! or 32-bit sized data transfers.
+//!
+//! The parameter \e ui32Address is the starting address for the read, relative
+//! to the external device.  The start of the device is address 0.
+//!
+//! Once configured, the non-blocking read is started by calling
+//! EPINonBlockingReadStart().  If the addresses to be read from the device
+//! are in a sequence, it is not necessary to call this function multiple
+//! times.  Until it is changed, the EPI module stores the last address
+//! that was used for a non-blocking read (per channel).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadConfigure(uint32_t ui32Base, uint32_t ui32Channel,
+                            uint32_t ui32DataSize, uint32_t ui32Address)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Channel < 2);
+    ASSERT(ui32DataSize < 4);
+    ASSERT(ui32Address < 0x20000000);
+
+    //
+    // Compute the offset needed to select the correct channel regs.
+    //
+    ui32Offset = ui32Channel * (EPI_O_RSIZE1 - EPI_O_RSIZE0);
+
+    //
+    // Write the data size register for the channel.
+    //
+    HWREG(ui32Base + EPI_O_RSIZE0 + ui32Offset) = ui32DataSize;
+
+    //
+    // Write the starting address register for the channel.
+    //
+    HWREG(ui32Base + EPI_O_RADDR0 + ui32Offset) = ui32Address;
+}
+
+//*****************************************************************************
+//
+//! Starts a non-blocking read transaction.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Channel is the read channel (0 or 1).
+//! \param ui32Count is the number of items to read (1-4095).
+//!
+//! This function starts a non-blocking read that was previously configured
+//! with the function EPINonBlockingReadConfigure().  Once this function is
+//! called, the EPI module begins reading data from the external device
+//! into the read FIFO.  The EPI stops reading when the FIFO fills up
+//! and resumes reading when the application drains the FIFO, until the
+//! total specified count of data items has been read.
+//!
+//! Once a read transaction is completed and the FIFO drained, another
+//! transaction can be started from the next address by calling this
+//! function again.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadStart(uint32_t ui32Base, uint32_t ui32Channel,
+                        uint32_t ui32Count)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Channel < 2);
+    ASSERT(ui32Count < 4096);
+
+    //
+    // Compute the offset needed to select the correct channel regs.
+    //
+    ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+    //
+    // Write to the read count register.
+    //
+    HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = ui32Count;
+}
+
+//*****************************************************************************
+//
+//! Stops a non-blocking read transaction.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Channel is the read channel (0 or 1).
+//!
+//! This function cancels a non-blocking read transaction that is already
+//! in progress.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadStop(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Channel < 2);
+
+    //
+    // Compute the offset needed to select the correct channel regs.
+    //
+    ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+    //
+    // Write a 0 to the read count register, which cancels the transaction.
+    //
+    HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = 0;
+}
+
+//*****************************************************************************
+//
+//! Get the count remaining for a non-blocking transaction.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Channel is the read channel (0 or 1).
+//!
+//! This function gets the remaining count of items for a non-blocking read
+//! transaction.
+//!
+//! \return The number of items remaining in the non-blocking read transaction.
+//
+//*****************************************************************************
+uint32_t
+EPINonBlockingReadCount(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    uint32_t ui32Offset;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Channel < 2);
+
+    //
+    // Compute the offset needed to select the correct channel regs.
+    //
+    ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+    //
+    // Read the count remaining and return the value to the caller.
+    //
+    return(HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset));
+}
+
+//*****************************************************************************
+//
+//! Get the count of items available in the read FIFO.
+//!
+//! \param ui32Base is the EPI module base address.
+//!
+//! This function gets the number of items that are available to read in
+//! the read FIFO.  The read FIFO is filled by a non-blocking read transaction
+//! which is configured by the functions EPINonBlockingReadConfigure() and
+//! EPINonBlockingReadStart().
+//!
+//! \return The number of items available to read in the read FIFO.
+//
+//*****************************************************************************
+uint32_t
+EPINonBlockingReadAvail(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // Read the FIFO count and return it to the caller.
+    //
+    return(HWREG(ui32Base + EPI_O_RFIFOCNT));
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 32-bit data items.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Count is the maximum count of items to read.
+//! \param pui32Buf is the caller supplied buffer where the read data is
+//! stored.
+//!
+//! This function reads 32-bit data items from the read FIFO and stores
+//! the values in a caller-supplied buffer.  The function reads and stores
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ui32Count.  The actual
+//! count of items is returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+uint32_t
+EPINonBlockingReadGet32(uint32_t ui32Base, uint32_t ui32Count,
+                        uint32_t *pui32Buf)
+{
+    uint32_t ui32CountRead = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Count < 4096);
+    ASSERT(pui32Buf);
+
+    //
+    // Read from the FIFO while there are any items to read and
+    // the caller's specified count is not exceeded.
+    //
+    while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--)
+    {
+        //
+        // Read from the FIFO and store in the caller supplied buffer.
+        //
+        *pui32Buf = HWREG(ui32Base + EPI_O_READFIFO0);
+
+        //
+        // Update the caller's buffer pointer and the count of items read.
+        //
+        pui32Buf++;
+        ui32CountRead++;
+    }
+
+    //
+    // Return the count of items read to the caller.
+    //
+    return(ui32CountRead);
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 16-bit data items.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Count is the maximum count of items to read.
+//! \param pui16Buf is the caller-supplied buffer where the read data is
+//! stored.
+//!
+//! This function reads 16-bit data items from the read FIFO and stores
+//! the values in a caller-supplied buffer.  The function reads and stores
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ui32Count.  The actual
+//! count of items is returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+uint32_t
+EPINonBlockingReadGet16(uint32_t ui32Base, uint32_t ui32Count,
+                        uint16_t *pui16Buf)
+{
+    uint32_t ui32CountRead = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Count < 4096);
+    ASSERT(pui16Buf);
+
+    //
+    // Read from the FIFO while there are any items to read, and
+    // the caller's specified count is not exceeded.
+    //
+    while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--)
+    {
+        //
+        // Read from the FIFO and store in the caller-supplied buffer.
+        //
+        *pui16Buf = (uint16_t)HWREG(ui32Base + EPI_O_READFIFO0);
+
+        //
+        // Update the caller's buffer pointer and the count of items read.
+        //
+        pui16Buf++;
+        ui32CountRead++;
+    }
+
+    //
+    // Return the count of items read to the caller.
+    //
+    return(ui32CountRead);
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 8-bit data items.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Count is the maximum count of items to read.
+//! \param pui8Buf is the caller-supplied buffer where the read data is
+//! stored.
+//!
+//! This function reads 8-bit data items from the read FIFO and stores
+//! the values in a caller-supplied buffer.  The function reads and stores
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ui32Count.  The actual
+//! count of items is returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+uint32_t
+EPINonBlockingReadGet8(uint32_t ui32Base, uint32_t ui32Count,
+                       uint8_t *pui8Buf)
+{
+    uint32_t ui32CountRead = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Count < 4096);
+    ASSERT(pui8Buf);
+
+    //
+    // Read from the FIFO while there are any items to read, and
+    // the caller's specified count is not exceeded.
+    //
+    while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--)
+    {
+        //
+        // Read from the FIFO and store in the caller supplied buffer.
+        //
+        *pui8Buf = (uint8_t)HWREG(ui32Base + EPI_O_READFIFO0);
+
+        //
+        // Update the caller's buffer pointer and the count of items read.
+        //
+        pui8Buf++;
+        ui32CountRead++;
+    }
+
+    //
+    // Return the count of items read to the caller.
+    //
+    return(ui32CountRead);
+}
+
+//*****************************************************************************
+//
+//! Configures the read FIFO.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32Config is the FIFO configuration.
+//!
+//! This function configures the FIFO trigger levels and error
+//! generation.  The parameter \e ui32Config is the logical OR of the
+//! following:
+//!
+//! - \b EPI_FIFO_CONFIG_WTFULLERR enables an error interrupt when a write is
+//! attempted and the write FIFO is full
+//! - \b EPI_FIFO_CONFIG_RSTALLERR enables an error interrupt when a read is
+//! stalled due to an interleaved write or other reason
+//! - FIFO TX trigger level, select one of:
+//!     - \b EPI_FIFO_CONFIG_TX_EMPTY sets the FIFO TX trigger level to empty.
+//!     - \b EPI_FIFO_CONFIG_TX_1_4 sets the FIFO TX trigger level to 1/4.
+//!     - \b EPI_FIFO_CONFIG_TX_1_2 sets the FIFO TX trigger level to 1/2.
+//!     - \b EPI_FIFO_CONFIG_TX_3_4 sets the FIFO TX trigger level to 3/4.
+//! - FIFO RX trigger level, select one of:
+//!     - \b EPI_FIFO_CONFIG_RX_1_8 sets the FIFO RX trigger level to 1/8.
+//!     - \b EPI_FIFO_CONFIG_RX_1_4 sets the FIFO RX trigger level to 1/4.
+//!     - \b EPI_FIFO_CONFIG_RX_1_2 sets the FIFO RX trigger level to 1/2.
+//!     - \b EPI_FIFO_CONFIG_RX_3_4 sets the FIFO RX trigger level to 3/4.
+//!     - \b EPI_FIFO_CONFIG_RX_7_8 sets the FIFO RX trigger level to 7/8.
+//!     - \b EPI_FIFO_CONFIG_RX_FULL sets the FIFO RX trigger level to full.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32Config == (ui32Config & 0x00030077));
+
+    //
+    // Load the configuration into the FIFO config reg.
+    //
+    HWREG(ui32Base + EPI_O_FIFOLVL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Reads the number of empty slots in the write transaction FIFO.
+//!
+//! \param ui32Base is the EPI module base address.
+//!
+//! This function returns the number of slots available in the transaction
+//! FIFO.  It can be used in a polling method to avoid attempting a write
+//! that would stall.
+//!
+//! \return The number of empty slots in the transaction FIFO.
+//
+//*****************************************************************************
+uint32_t
+EPIWriteFIFOCountGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // Read the FIFO count and return it to the caller.
+    //
+    return(HWREG(ui32Base + EPI_O_WFIFOCNT));
+}
+
+//*****************************************************************************
+//
+//! Enables EPI interrupt sources.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the specified EPI sources to generate interrupts.
+//! The \e ui32IntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level.
+//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level.
+//! - \b EPI_INT_ERR interrupt when an error condition occurs.
+//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes.
+//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32IntFlags < 17);
+
+    //
+    // Write the interrupt flags mask to the mask register.
+    //
+    HWREG(ui32Base + EPI_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables EPI interrupt sources.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the specified EPI sources for interrupt
+//! generation.  The \e ui32IntFlags parameter can be the logical OR of any of
+//! the following values:
+//!
+//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level.
+//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level.
+//! - \b EPI_INT_ERR interrupt when an error condition occurs.
+//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes.
+//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32IntFlags < 17);
+
+    //
+    // Write the interrupt flags mask to the mask register.
+    //
+    HWREG(ui32Base + EPI_O_IM) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the EPI interrupt status.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param bMasked is set \b true to get the masked interrupt status, or
+//! \b false to get the raw interrupt status.
+//!
+//! This function returns the EPI interrupt status.  It can return either
+//! the raw or masked interrupt status.
+//!
+//! \return Returns the masked or raw EPI interrupt status, as a bit field
+//! of any of the following values:
+//!
+//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level.
+//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level.
+//! - \b EPI_INT_ERR interrupt when an error condition occurs.
+//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes.
+//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes.
+//
+//*****************************************************************************
+uint32_t
+EPIIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + EPI_O_MIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + EPI_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the EPI error interrupt status.
+//!
+//! \param ui32Base is the EPI module base address.
+//!
+//! This function returns the error status of the EPI.  If the return value of
+//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this
+//! function can be used to determine the cause of the error.
+//!
+//! \return Returns a bit mask of error flags, which can be the logical
+//! OR of any of the following:
+//!
+//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction
+//! FIFO was full
+//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled
+//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held
+//! off a transaction longer than the configured maximum wait time
+//
+//*****************************************************************************
+uint32_t
+EPIIntErrorStatus(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // Read the error status and return to caller.
+    //
+    return(HWREG(ui32Base + EPI_O_EISC));
+}
+
+//*****************************************************************************
+//
+//! Clears pending EPI error sources.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param ui32ErrFlags is a bit mask of the error sources to be cleared.
+//!
+//! This function clears the specified pending EPI errors.  The \e ui32ErrFlags
+//! parameter can be the logical OR of any of the following values:
+//!
+//! - \b EPI_INT_ERR_DMAWRIC clears the EPI_INT_DMA_TX_DONE as an interrupt
+//! source
+//! - \b EPI_INT_ERR_DMARDIC clears the EPI_INT_DMA_RX_DONE as an interrupt
+//! source
+//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction
+//! FIFO was full
+//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled
+//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held
+//! off a transaction longer than the configured maximum wait time
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(ui32ErrFlags < 0x20);
+
+    //
+    // Write the error flags to the register to clear the pending errors.
+    //
+    HWREG(ui32Base + EPI_O_EISC) = ui32ErrFlags;
+}
+
+//*****************************************************************************
+//
+//! Returns the interrupt number for a given EPI base address.
+//!
+//! \param ui32Base is the base address of the EPI module.
+//!
+//! This function returns the interrupt number for the EPI module with the base
+//! address passed in the \e ui32Base parameter.
+//!
+//! \return Returns the EPI interrupt number or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_EPIIntNumberGet(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // By default, assume EPI is not supported.
+    //
+    ui32Int = 0;
+
+    if(CLASS_IS_TM4C129)
+    {
+        ui32Int = INT_EPI0_TM4C129;
+    }
+
+    return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the EPI module.
+//!
+//! \param ui32Base is the EPI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the EPI module
+//! generates an interrupt.  Specific EPI interrupts must still be enabled
+//! with the EPIIntEnable() function.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+    ASSERT(pfnHandler);
+
+    //
+    // Get the interrupt number for the EPI interface.
+    //
+    ui32Int = _EPIIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the EPI interface interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Removes a registered interrupt handler for the EPI module.
+//!
+//! \param ui32Base is the EPI module base address.
+//!
+//! This function disables and clears the handler to be called when the
+//! EPI interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == EPI0_BASE);
+
+    //
+    // Get the interrupt number for the EPI interface.
+    //
+    ui32Int = _EPIIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the EPI interface interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/epi.h b/bsp/tm4c129x/libraries/driverlib/epi.h
new file mode 100644
index 0000000000..b6ada822f5
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/epi.h
@@ -0,0 +1,762 @@
+//*****************************************************************************
+//
+// epi.h - Prototypes and macros for the EPI module.
+//
+// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_EPI_H__
+#define __DRIVERLIB_EPI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIModeSet()
+//
+//*****************************************************************************
+#define EPI_MODE_GENERAL        0x00000010
+#define EPI_MODE_SDRAM          0x00000011
+#define EPI_MODE_HB8            0x00000012
+#define EPI_MODE_HB16           0x00000013
+#define EPI_MODE_DISABLE        0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigSDRAMSet()
+//
+//*****************************************************************************
+#define EPI_SDRAM_CORE_FREQ_0_15                                              \
+                                0x00000000
+#define EPI_SDRAM_CORE_FREQ_15_30                                             \
+                                0x40000000
+#define EPI_SDRAM_CORE_FREQ_30_50                                             \
+                                0x80000000
+#define EPI_SDRAM_CORE_FREQ_50_100                                            \
+                                0xC0000000
+#define EPI_SDRAM_LOW_POWER     0x00000200
+#define EPI_SDRAM_FULL_POWER    0x00000000
+#define EPI_SDRAM_SIZE_64MBIT   0x00000000
+#define EPI_SDRAM_SIZE_128MBIT  0x00000001
+#define EPI_SDRAM_SIZE_256MBIT  0x00000002
+#define EPI_SDRAM_SIZE_512MBIT  0x00000003
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigGPModeSet()
+//
+//*****************************************************************************
+#define EPI_GPMODE_CLKPIN       0x80000000
+#define EPI_GPMODE_CLKGATE      0x40000000
+#define EPI_GPMODE_FRAME50      0x04000000
+#define EPI_GPMODE_WRITE2CYCLE  0x00080000
+#define EPI_GPMODE_ASIZE_NONE   0x00000000
+#define EPI_GPMODE_ASIZE_4      0x00000010
+#define EPI_GPMODE_ASIZE_12     0x00000020
+#define EPI_GPMODE_ASIZE_20     0x00000030
+#define EPI_GPMODE_DSIZE_8      0x00000000
+#define EPI_GPMODE_DSIZE_16     0x00000001
+#define EPI_GPMODE_DSIZE_24     0x00000002
+#define EPI_GPMODE_DSIZE_32     0x00000003
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB8ModeSet()
+//
+//*****************************************************************************
+#define EPI_HB8_USE_TXEMPTY     0x00800000
+#define EPI_HB8_USE_RXFULL      0x00400000
+#define EPI_HB8_WRHIGH          0x00200000
+#define EPI_HB8_RDHIGH          0x00100000
+#define EPI_HB8_ALE_HIGH        0x00080000
+#define EPI_HB8_ALE_LOW         0x00000000
+#define EPI_HB8_WRWAIT_0        0x00000000
+#define EPI_HB8_WRWAIT_1        0x00000040
+#define EPI_HB8_WRWAIT_2        0x00000080
+#define EPI_HB8_WRWAIT_3        0x000000C0
+#define EPI_HB8_RDWAIT_0        0x00000000
+#define EPI_HB8_RDWAIT_1        0x00000010
+#define EPI_HB8_RDWAIT_2        0x00000020
+#define EPI_HB8_RDWAIT_3        0x00000030
+#define EPI_HB8_MODE_ADMUX      0x00000000
+#define EPI_HB8_MODE_ADDEMUX    0x00000001
+#define EPI_HB8_MODE_SRAM       0x00000002
+#define EPI_HB8_MODE_FIFO       0x00000003
+#define EPI_HB8_WORD_ACCESS     0x00000100
+#define EPI_HB8_CSCFG_ALE       0x00000000
+#define EPI_HB8_CSCFG_CS        0x00000200
+#define EPI_HB8_CSCFG_DUAL_CS   0x00000400
+#define EPI_HB8_CSCFG_ALE_DUAL_CS                                             \
+                                0x00000600
+#define EPI_HB8_CSCFG_ALE_SINGLE_CS                                           \
+                                0x00001000
+#define EPI_HB8_CSCFG_QUAD_CS   0x00001200
+#define EPI_HB8_CSCFG_ALE_QUAD_CS                                             \
+                                0x00001400
+#define EPI_HB8_CSBAUD          0x00000800
+#define EPI_HB8_CLOCK_GATE      0x80000000
+#define EPI_HB8_CLOCK_GATE_IDLE                                               \
+                                0x40000000
+#define EPI_HB8_CLOCK_INVERT    0x20000000
+#define EPI_HB8_IN_READY_EN     0x10000000
+#define EPI_HB8_IN_READY_EN_INVERT                                            \
+                                0x18000000
+#define EPI_HB8_CSCFG_MASK      0x00001600
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB16ModeSet()
+//
+//*****************************************************************************
+#define EPI_HB16_USE_TXEMPTY    0x00800000
+#define EPI_HB16_USE_RXFULL     0x00400000
+#define EPI_HB16_WRHIGH         0x00200000
+#define EPI_HB16_RDHIGH         0x00100000
+#define EPI_HB16_WRWAIT_0       0x00000000
+#define EPI_HB16_WRWAIT_1       0x00000040
+#define EPI_HB16_WRWAIT_2       0x00000080
+#define EPI_HB16_WRWAIT_3       0x000000C0
+#define EPI_HB16_RDWAIT_0       0x00000000
+#define EPI_HB16_RDWAIT_1       0x00000010
+#define EPI_HB16_RDWAIT_2       0x00000020
+#define EPI_HB16_RDWAIT_3       0x00000030
+#define EPI_HB16_MODE_ADMUX     0x00000000
+#define EPI_HB16_MODE_ADDEMUX   0x00000001
+#define EPI_HB16_MODE_SRAM      0x00000002
+#define EPI_HB16_MODE_FIFO      0x00000003
+#define EPI_HB16_BSEL           0x00000004
+#define EPI_HB16_WORD_ACCESS    0x00000100
+#define EPI_HB16_CSCFG_ALE      0x00000000
+#define EPI_HB16_CSCFG_CS       0x00000200
+#define EPI_HB16_CSCFG_DUAL_CS  0x00000400
+#define EPI_HB16_CSCFG_ALE_DUAL_CS                                            \
+                                0x00000600
+#define EPI_HB16_CSCFG_ALE_SINGLE_CS                                          \
+                                0x00001000
+#define EPI_HB16_CSCFG_QUAD_CS  0x00001200
+#define EPI_HB16_CSCFG_ALE_QUAD_CS                                            \
+                                0x00001400
+#define EPI_HB16_CLOCK_GATE     0x80000000
+#define EPI_HB16_CLOCK_GATE_IDLE                                              \
+                                0x40000000
+#define EPI_HB16_CLOCK_INVERT   0x20000000
+#define EPI_HB16_IN_READY_EN    0x10000000
+#define EPI_HB16_IN_READY_EN_INVERTED                                         \
+                                0x18000000
+#define EPI_HB16_ALE_HIGH       0x00080000
+#define EPI_HB16_ALE_LOW        0x00000000
+#define EPI_HB16_BURST_TRAFFIC  0x00010000
+#define EPI_HB16_CSBAUD         0x00000800
+#define EPI_HB16_CSCFG_MASK     0x00001600
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB8TimingSet().
+//
+//*****************************************************************************
+#define EPI_HB8_IN_READY_DELAY_1                                              \
+                                0x01000000
+#define EPI_HB8_IN_READY_DELAY_2                                              \
+                                0x02000000
+#define EPI_HB8_IN_READY_DELAY_3                                              \
+                                0x03000000
+#define EPI_HB8_CAP_WIDTH_1     0x00001000
+#define EPI_HB8_CAP_WIDTH_2     0x00002000
+#define EPI_HB8_WRWAIT_MINUS_DISABLE                                          \
+                                0x00000000
+#define EPI_HB8_WRWAIT_MINUS_ENABLE                                           \
+                                0x00000010
+#define EPI_HB8_RDWAIT_MINUS_DISABLE                                          \
+                                0x00000000
+#define EPI_HB8_RDWAIT_MINUS_ENABLE                                           \
+                                0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB16TimingSet().
+//
+//*****************************************************************************
+#define EPI_HB16_IN_READY_DELAY_1                                             \
+                                0x01000000
+#define EPI_HB16_IN_READY_DELAY_2                                             \
+                                0x02000000
+#define EPI_HB16_IN_READY_DELAY_3                                             \
+                                0x03000000
+#define EPI_HB16_PSRAM_NO_LIMIT 0x00000000
+#define EPI_HB16_PSRAM_128      0x00010000
+#define EPI_HB16_PSRAM_256      0x00020000
+#define EPI_HB16_PSRAM_512      0x00030000
+#define EPI_HB16_PSRAM_1024     0x00040000
+#define EPI_HB16_PSRAM_2048     0x00050000
+#define EPI_HB16_PSRAM_4096     0x00060000
+#define EPI_HB16_PSRAM_8192     0x00070000
+#define EPI_HB16_CAP_WIDTH_1    0x00001000
+#define EPI_HB16_CAP_WIDTH_2    0x00002000
+#define EPI_HB16_WRWAIT_MINUS_DISABLE                                         \
+                                0x00000000
+#define EPI_HB16_WRWAIT_MINUS_ENABLE                                          \
+                                0x00000008
+#define EPI_HB16_RDWAIT_MINUS_DISABLE                                         \
+                                0x00000000
+#define EPI_HB16_RDWAIT_MINUS_ENABLE                                          \
+                                0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIAddressMapSet().
+//
+//*****************************************************************************
+#define EPI_ADDR_PER_SIZE_256B  0x00000000
+#define EPI_ADDR_PER_SIZE_64KB  0x00000040
+#define EPI_ADDR_PER_SIZE_16MB  0x00000080
+#define EPI_ADDR_PER_SIZE_256MB 0x000000C0
+#define EPI_ADDR_PER_BASE_NONE  0x00000000
+#define EPI_ADDR_PER_BASE_A     0x00000010
+#define EPI_ADDR_PER_BASE_C     0x00000020
+#define EPI_ADDR_RAM_SIZE_256B  0x00000000
+#define EPI_ADDR_RAM_SIZE_64KB  0x00000004
+#define EPI_ADDR_RAM_SIZE_16MB  0x00000008
+#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C
+#define EPI_ADDR_RAM_BASE_NONE  0x00000000
+#define EPI_ADDR_RAM_BASE_6     0x00000001
+#define EPI_ADDR_RAM_BASE_8     0x00000002
+#define EPI_ADDR_QUAD_MODE      0x00000033
+#define EPI_ADDR_CODE_SIZE_256B 0x00000000
+#define EPI_ADDR_CODE_SIZE_64KB 0x00000400
+#define EPI_ADDR_CODE_SIZE_16MB 0x00000800
+#define EPI_ADDR_CODE_SIZE_256MB                                              \
+                                0x00000C00
+#define EPI_ADDR_CODE_BASE_NONE 0x00000000
+#define EPI_ADDR_CODE_BASE_1    0x00000100
+
+//*****************************************************************************
+//
+// Values that can be passed to EPINonBlockingReadConfigure()
+//
+//*****************************************************************************
+#define EPI_NBCONFIG_SIZE_8     1
+#define EPI_NBCONFIG_SIZE_16    2
+#define EPI_NBCONFIG_SIZE_32    3
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIFIFOConfig()
+//
+//*****************************************************************************
+#define EPI_FIFO_CONFIG_WTFULLERR                                             \
+                                0x00020000
+#define EPI_FIFO_CONFIG_RSTALLERR                                             \
+                                0x00010000
+#define EPI_FIFO_CONFIG_TX_EMPTY                                              \
+                                0x00000000
+#define EPI_FIFO_CONFIG_TX_1_4  0x00000020
+#define EPI_FIFO_CONFIG_TX_1_2  0x00000030
+#define EPI_FIFO_CONFIG_TX_3_4  0x00000040
+#define EPI_FIFO_CONFIG_RX_1_8  0x00000001
+#define EPI_FIFO_CONFIG_RX_1_4  0x00000002
+#define EPI_FIFO_CONFIG_RX_1_2  0x00000003
+#define EPI_FIFO_CONFIG_RX_3_4  0x00000004
+#define EPI_FIFO_CONFIG_RX_7_8  0x00000005
+#define EPI_FIFO_CONFIG_RX_FULL 0x00000006
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned
+// as flags from EPIIntStatus()
+//
+//*****************************************************************************
+#define EPI_INT_DMA_TX_DONE     0x00000010
+#define EPI_INT_DMA_RX_DONE     0x00000008
+#define EPI_INT_TXREQ           0x00000004
+#define EPI_INT_RXREQ           0x00000002
+#define EPI_INT_ERR             0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIIntErrorClear(), or returned as flags from
+// EPIIntErrorStatus()
+//
+//*****************************************************************************
+#define EPI_INT_ERR_DMAWRIC     0x00000010
+#define EPI_INT_ERR_DMARDIC     0x00000008
+#define EPI_INT_ERR_WTFULL      0x00000004
+#define EPI_INT_ERR_RSTALL      0x00000002
+#define EPI_INT_ERR_TIMEOUT     0x00000001
+
+#ifdef rvmdk
+//*****************************************************************************
+//
+// Keil case.
+//
+//*****************************************************************************
+inline void
+EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value)
+{
+  uint32_t ui32Scratch;
+
+    __asm
+    {
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        NOP
+
+        //
+        // Perform the write we're actually interested in.
+        //
+        STR ui32Value, [pui32Addr]
+
+        //
+        // Read from SRAM to ensure that we don't have an EPI write followed by
+        // a flash read.
+        //
+        LDR ui32Scratch, [__current_sp()]
+    }
+}
+
+inline uint32_t
+EPIWorkaroundWordRead(uint32_t *pui32Addr)
+{
+  uint32_t ui32Value, ui32Scratch;
+
+    __asm
+    {
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        NOP
+
+        //
+        // Perform the read we're actually interested in.
+        //
+        LDR ui32Value, [pui32Addr]
+
+        //
+        // Read from SRAM to ensure that we don't have an EPI read followed by
+        // a flash read.
+        //
+        LDR ui32Scratch, [__current_sp()]
+    }
+
+    return(ui32Value);
+}
+
+inline void
+EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value)
+{
+    uint32_t ui32Scratch;
+
+    __asm
+    {
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        NOP
+
+        //
+        // Perform the write we're actually interested in.
+        //
+        STRH ui16Value, [pui16Addr]
+
+        //
+        // Read from SRAM to ensure that we don't have an EPI write followed by
+        // a flash read.
+        //
+        LDR ui32Scratch, [__current_sp()]
+    }
+}
+
+inline uint16_t
+EPIWorkaroundHWordRead(uint16_t *pui16Addr)
+{
+    uint32_t ui32Scratch;
+    uint16_t ui16Value;
+
+    __asm
+    {
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        NOP
+
+        //
+        // Perform the read we're actually interested in.
+        //
+        LDRH ui16Value, [pui16Addr]
+
+        //
+        // Read from SRAM to ensure that we don't have an EPI read followed by
+        // a flash read.
+        //
+        LDR ui32Scratch, [__current_sp()]
+    }
+
+    return(ui16Value);
+}
+
+inline void
+EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value)
+{
+  uint32_t ui32Scratch;
+
+    __asm
+    {
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        NOP
+
+        //
+        // Perform the write we're actually interested in.
+        //
+        STRB ui8Value, [pui8Addr]
+
+        //
+        // Read from SRAM to ensure that we don't have an EPI write followed by
+        // a flash read.
+        //
+        LDR ui32Scratch, [__current_sp()]
+    }
+}
+
+inline uint8_t
+EPIWorkaroundByteRead(uint8_t *pui8Addr)
+{
+    uint32_t ui32Scratch;
+    uint8_t ui8Value;
+
+    __asm
+    {
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        NOP
+
+        //
+        // Perform the read we're actually interested in.
+        //
+        LDRB ui8Value, [pui8Addr]
+
+        //
+        // Read from SRAM to ensure that we don't have an EPI read followed by
+        // a flash read.
+        //
+        LDR ui32Scratch, [__current_sp()]
+    }
+
+    return(ui8Value);
+}
+#endif
+
+#ifdef ccs
+//*****************************************************************************
+//
+// Code Composer Studio versions of these functions can be found in separate
+// source file epi_workaround_ccs.s.
+//
+//*****************************************************************************
+extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value);
+extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr);
+extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value);
+extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr);
+extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value);
+extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr);
+
+#endif
+
+#if (defined gcc) || (defined ewarm) || (defined sourcerygxx) || \
+    (defined codered)
+//*****************************************************************************
+//
+// GCC-based toolchain and IAR case.
+//
+//*****************************************************************************
+inline void
+EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value)
+{
+    volatile register uint32_t ui32Scratch;
+
+    __asm volatile (
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        "    NOP\n"
+        "    STR %[value],[%[addr]]\n"
+        "    LDR %[scratch],[sp]\n"
+         :  [scratch] "=r" (ui32Scratch)
+         :  [addr] "r" (pui32Addr), [value] "r" (ui32Value)
+     );
+
+    //
+    // Keep the compiler from generating a warning.
+    //
+    ui32Scratch = ui32Scratch;
+}
+
+inline uint32_t
+EPIWorkaroundWordRead(uint32_t *pui32Addr)
+{
+    volatile register uint32_t ui32Data, ui32Scratch;
+
+    //
+    // ui32Scratch is not used other than to add a padding read following the
+    // "real" read.
+    //
+
+    __asm volatile(
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        "    NOP\n"
+        "    LDR %[ret],[%[addr]]\n"
+        "    LDR %[scratch],[sp]\n"
+         : [ret] "=r" (ui32Data),
+           [scratch] "=r" (ui32Scratch)
+         : [addr] "r" (pui32Addr)
+    );
+
+
+    //
+    // Keep the compiler from generating a warning.
+    //
+    ui32Scratch = ui32Scratch;
+
+    return(ui32Data);
+}
+
+inline void
+EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value)
+{
+    volatile register uint32_t ui32Scratch;
+
+    __asm volatile (
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        "    NOP\n"
+        "    STRH %[value],[%[addr]]\n"
+        "    LDR %[scratch],[sp]\n"
+         :  [scratch] "=r" (ui32Scratch)
+         :  [addr] "r" (pui16Addr), [value] "r" (ui16Value)
+     );
+
+
+    //
+    // Keep the compiler from generating a warning.
+    //
+    ui32Scratch = ui32Scratch;
+}
+
+inline uint16_t
+EPIWorkaroundHWordRead(uint16_t *pui16Addr)
+{
+    register uint16_t ui16Data;
+    register uint32_t ui32Scratch;
+
+    //
+    // ui32Scratch is not used other than to add a padding read following the
+    // "real" read.
+    //
+
+    __asm volatile(
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        "    NOP\n"
+        "    LDRH %[ret],[%[addr]]\n"
+        "    LDR %[scratch],[sp]\n"
+         : [ret] "=r" (ui16Data),
+           [scratch] "=r" (ui32Scratch)
+         : [addr] "r" (pui16Addr)
+    );
+
+    //
+    // Keep the compiler from generating a warning.
+    //
+    ui32Scratch = ui32Scratch;
+
+    return(ui16Data);
+}
+
+inline void
+EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value)
+{
+    volatile register uint32_t ui32Scratch;
+
+    __asm volatile (
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        "    NOP\n"
+        "    STRB %[value],[%[addr]]\n"
+        "    LDR %[scratch],[sp]\n"
+         :  [scratch] "=r" (ui32Scratch)
+         :  [addr] "r" (pui8Addr), [value] "r" (ui8Value)
+     );
+
+    //
+    // Keep the compiler from generating a warning.
+    //
+    ui32Scratch = ui32Scratch;
+}
+
+inline uint8_t
+EPIWorkaroundByteRead(uint8_t *pui8Addr)
+{
+    register uint8_t ui8Data;
+    register uint32_t ui32Scratch;
+
+    //
+    // ui32Scratch is not used other than to add a padding read following the
+    // "real" read.
+    //
+
+    __asm volatile(
+        //
+        // Add a NOP to ensure we don’t have a flash read immediately before
+        // the EPI read.
+        //
+        "    NOP\n"
+        "    LDRB %[ret],[%[addr]]\n"
+        "    LDR %[scratch],[sp]\n"
+         : [ret] "=r" (ui8Data),
+           [scratch] "=r" (ui32Scratch)
+         : [addr] "r" (pui8Addr)
+    );
+
+    //
+    // Keep the compiler from generating a warning.
+    //
+    ui32Scratch = ui32Scratch;
+
+    return(ui8Data);
+}
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider);
+extern void EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS,
+                            uint32_t ui32Divider);
+extern void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count);
+extern void EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config,
+                               uint32_t ui32FrameCount, uint32_t ui32MaxWait);
+extern void EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config,
+                            uint32_t ui32MaxWait);
+extern void EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config,
+                             uint32_t ui32MaxWait);
+extern void EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS,
+                               uint32_t ui32Config);
+extern void EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS,
+                                uint32_t ui32Config);
+extern void EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS,
+                                  uint32_t ui32Config);
+extern void EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS,
+                                   uint32_t ui32Config);
+extern void EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS,
+                                 uint32_t ui32CR);
+extern void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS);
+extern bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base,
+                                                uint32_t ui32CS,
+                                                uint32_t *pui32CR);
+extern uint32_t EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS);
+extern void EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config,
+                              uint32_t ui32Refresh);
+extern void EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map);
+extern void EPINonBlockingReadConfigure(uint32_t ui32Base,
+                                        uint32_t ui32Channel,
+                                        uint32_t ui32DataSize,
+                                        uint32_t ui32Address);
+extern void EPINonBlockingReadStart(uint32_t ui32Base,
+                                    uint32_t ui32Channel,
+                                    uint32_t ui32Count);
+extern void EPINonBlockingReadStop(uint32_t ui32Base,
+                                   uint32_t ui32Channel);
+extern uint32_t EPINonBlockingReadCount(uint32_t ui32Base,
+                                        uint32_t ui32Channel);
+extern uint32_t EPINonBlockingReadAvail(uint32_t ui32Base);
+extern uint32_t EPINonBlockingReadGet32(uint32_t ui32Base,
+                                        uint32_t ui32Count,
+                                        uint32_t *pui32Buf);
+extern uint32_t EPINonBlockingReadGet16(uint32_t ui32Base,
+                                        uint32_t ui32Count,
+                                        uint16_t *pui16Buf);
+extern uint32_t EPINonBlockingReadGet8(uint32_t ui32Base,
+                                       uint32_t ui32Count,
+                                       uint8_t *pui8Buf);
+extern void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config);
+extern uint32_t EPIWriteFIFOCountGet(uint32_t ui32Base);
+extern void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t EPIIntStatus(uint32_t ui32Base, bool bMasked);
+extern uint32_t EPIIntErrorStatus(uint32_t ui32Base);
+extern void EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags);
+extern void EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void EPIIntUnregister(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_EPI_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/flash.c b/bsp/tm4c129x/libraries/driverlib/flash.c
new file mode 100644
index 0000000000..d1c8554a1f
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/flash.c
@@ -0,0 +1,851 @@
+//*****************************************************************************
+//
+// flash.c - Driver for programming the on-chip flash.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_flash.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Program Enable (FMPPE) register.
+//
+//*****************************************************************************
+static const uint32_t g_pui32FMPPERegs[] =
+{
+    FLASH_FMPPE0,
+    FLASH_FMPPE1,
+    FLASH_FMPPE2,
+    FLASH_FMPPE3,
+    FLASH_FMPPE4,
+    FLASH_FMPPE5,
+    FLASH_FMPPE6,
+    FLASH_FMPPE7,
+    FLASH_FMPPE8,
+    FLASH_FMPPE9,
+    FLASH_FMPPE10,
+    FLASH_FMPPE11,
+    FLASH_FMPPE12,
+    FLASH_FMPPE13,
+    FLASH_FMPPE14,
+    FLASH_FMPPE15,
+};
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Read Enable (FMPRE) register.
+//
+//*****************************************************************************
+static const uint32_t g_pui32FMPRERegs[] =
+{
+    FLASH_FMPRE0,
+    FLASH_FMPRE1,
+    FLASH_FMPRE2,
+    FLASH_FMPRE3,
+    FLASH_FMPRE4,
+    FLASH_FMPRE5,
+    FLASH_FMPRE6,
+    FLASH_FMPRE7,
+    FLASH_FMPRE8,
+    FLASH_FMPRE9,
+    FLASH_FMPRE10,
+    FLASH_FMPRE11,
+    FLASH_FMPRE12,
+    FLASH_FMPRE13,
+    FLASH_FMPRE14,
+    FLASH_FMPRE15,
+};
+
+//*****************************************************************************
+//
+//! Erases a block of flash.
+//!
+//! \param ui32Address is the start address of the flash block to be erased.
+//!
+//! This function erases a block of the on-chip flash.  After erasing, the
+//! block is filled with 0xFF bytes.  Read-only and execute-only blocks cannot
+//! be erased.
+//!
+//! The flash block size is device-class dependent.  All TM4C123x devices use
+//! 1-KB blocks but TM4C129x devices use 16-KB blocks. Please consult the
+//! device datasheet to determine the block size in use.
+//!
+//! This function does not return until the block has been erased.
+//!
+//! \return Returns 0 on success, or -1 if an invalid block address was
+//! specified or the block is write-protected.
+//
+//*****************************************************************************
+int32_t
+FlashErase(uint32_t ui32Address)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32Address & (FLASH_ERASE_SIZE - 1)));
+
+    //
+    // Clear the flash access and error interrupts.
+    //
+    HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
+                           FLASH_FCMISC_ERMISC);
+
+    //
+    // Erase the block.
+    //
+    HWREG(FLASH_FMA) = ui32Address;
+    HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
+
+    //
+    // Wait until the block has been erased.
+    //
+    while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
+    {
+    }
+
+    //
+    // Return an error if an access violation or erase error occurred.
+    //
+    if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
+                             FLASH_FCRIS_ERRIS))
+    {
+        return(-1);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Programs flash.
+//!
+//! \param pui32Data is a pointer to the data to be programmed.
+//! \param ui32Address is the starting address in flash to be programmed.  Must
+//! be a multiple of four.
+//! \param ui32Count is the number of bytes to be programmed.  Must be a
+//! multiple of four.
+//!
+//! This function programs a sequence of words into the on-chip flash.
+//! Because the flash is programmed one word at a time, the starting address
+//! and byte count must both be multiples of four.  It is up to the caller to
+//! verify the programmed contents, if such verification is required.
+//!
+//! This function does not return until the data has been programmed.
+//!
+//! \return Returns 0 on success, or -1 if a programming error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32Address & 3));
+    ASSERT(!(ui32Count & 3));
+
+    //
+    // Clear the flash access and error interrupts.
+    //
+    HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
+                           FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC);
+
+    //
+    // Loop over the words to be programmed.
+    //
+    while(ui32Count)
+    {
+        //
+        // Set the address of this block of words.
+        //
+        HWREG(FLASH_FMA) = ui32Address & ~(0x7f);
+
+        //
+        // Loop over the words in this 32-word block.
+        //
+        while(((ui32Address & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
+              (ui32Count != 0))
+        {
+            //
+            // Write this word into the write buffer.
+            //
+            HWREG(FLASH_FWBN + (ui32Address & 0x7c)) = *pui32Data++;
+            ui32Address += 4;
+            ui32Count -= 4;
+        }
+
+        //
+        // Program the contents of the write buffer into flash.
+        //
+        HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
+
+        //
+        // Wait until the write buffer has been programmed.
+        //
+        while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
+        {
+        }
+    }
+
+    //
+    // Return an error if an access violation occurred.
+    //
+    if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
+                             FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS))
+    {
+        return(-1);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the protection setting for a block of flash.
+//!
+//! \param ui32Address is the start address of the flash block to be queried.
+//!
+//! This function gets the current protection for the specified block of flash.
+//! Refer to the device data sheet to determine the granularity for each
+//! protection option. A block can be read/write, read-only, or execute-only.
+//! Read/write blocks can be read, executed, erased, and programmed.  Read-only
+//! blocks can be read and executed.  Execute-only blocks can only be executed;
+//! processor and debugger data reads are not allowed.
+//!
+//! \return Returns the protection setting for this block.  See
+//! FlashProtectSet() for possible values.
+//
+//*****************************************************************************
+tFlashProtection
+FlashProtectGet(uint32_t ui32Address)
+{
+    uint32_t ui32FMPRE, ui32FMPPE;
+    uint32_t ui32Bank;
+
+    //
+    // Check the argument.
+    //
+    ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1)));
+
+    //
+    // Calculate the Flash Bank from Base Address, and mask off the Bank
+    // from ui32Address for subsequent reference.
+    //
+    ui32Bank = (((ui32Address / FLASH_PROTECT_SIZE) / 32) % 4);
+    ui32Address &= ((FLASH_PROTECT_SIZE * 32) - 1);
+
+    //
+    // Read the appropriate flash protection registers for the specified
+    // flash bank.
+    //
+    ui32FMPRE = HWREG(g_pui32FMPRERegs[ui32Bank]);
+    ui32FMPPE = HWREG(g_pui32FMPPERegs[ui32Bank]);
+
+    //
+    // Check the appropriate protection bits for the block of memory that
+    // is specified by the address.
+    //
+    switch((((ui32FMPRE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1) << 1) |
+           ((ui32FMPPE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1))
+    {
+        //
+        // This block is marked as execute only (that is, it can not be erased
+        // or programmed, and the only reads allowed are via the instruction
+        // fetch interface).
+        //
+        case 0:
+        case 1:
+        {
+            return(FlashExecuteOnly);
+        }
+
+        //
+        // This block is marked as read only (that is, it can not be erased or
+        // programmed).
+        //
+        case 2:
+        {
+            return(FlashReadOnly);
+        }
+
+        //
+        // This block is read/write; it can be read, erased, and programmed.
+        //
+        case 3:
+        default:
+        {
+            return(FlashReadWrite);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the protection setting for a block of flash.
+//!
+//! \param ui32Address is the start address of the flash block to be protected.
+//! \param eProtect is the protection to be applied to the block.  Can be one
+//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
+//!
+//! This function sets the protection for the specified block of flash.  Refer
+//! to the device data sheet to determine the granularity for each protection
+//! option.  Blocks that are read/write can be made read-only or execute-only.
+//! Blocks that are read-only can be made execute-only.  Blocks that are
+//! execute-only cannot have their protection modified.  Attempts to make the
+//! block protection less stringent (that is, read-only to read/write)
+//! result in a failure (and are prevented by the hardware).
+//!
+//! Changes to the flash protection are maintained only until the next reset.
+//! This protocol allows the application to be executed in the desired flash
+//! protection environment to check for inappropriate flash access (via the
+//! flash interrupt).  To make the flash protection permanent, use the
+//! FlashProtectSave() function.
+//!
+//! \return Returns 0 on success, or -1 if an invalid address or an invalid
+//! protection was specified.
+//
+//*****************************************************************************
+int32_t
+FlashProtectSet(uint32_t ui32Address, tFlashProtection eProtect)
+{
+    uint32_t ui32ProtectRE, ui32ProtectPE;
+    uint32_t ui32Bank;
+
+    //
+    // Check the argument.
+    //
+    ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1)));
+    ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
+           (eProtect == FlashExecuteOnly));
+
+    //
+    // Convert the address into a block number.
+    //
+    ui32Address /= FLASH_PROTECT_SIZE;
+
+    //
+    // ui32Address contains a "raw" block number.  Derive the Flash Bank from
+    // the "raw" block number, and convert ui32Address to a "relative"
+    // block number.
+    //
+    ui32Bank = ((ui32Address / 32) % 4);
+    ui32Address %= 32;
+
+    //
+    // Get the current protection for the specified flash bank.
+    //
+    ui32ProtectRE = HWREG(g_pui32FMPRERegs[ui32Bank]);
+    ui32ProtectPE = HWREG(g_pui32FMPPERegs[ui32Bank]);
+
+    //
+    // Set the protection based on the requested protection.
+    //
+    switch(eProtect)
+    {
+        //
+        // Make this block execute only.
+        //
+        case FlashExecuteOnly:
+        {
+            //
+            // Turn off the read and program bits for this block.
+            //
+            ui32ProtectRE &= ~(0x1 << ui32Address);
+            ui32ProtectPE &= ~(0x1 << ui32Address);
+
+            //
+            // We're done handling this protection.
+            //
+            break;
+        }
+
+        //
+        // Make this block read only.
+        //
+        case FlashReadOnly:
+        {
+            //
+            // The block can not be made read only if it is execute only.
+            //
+            if(((ui32ProtectRE >> ui32Address) & 0x1) != 0x1)
+            {
+                return(-1);
+            }
+
+            //
+            // Make this block read only.
+            //
+            ui32ProtectPE &= ~(0x1 << ui32Address);
+
+            //
+            // We're done handling this protection.
+            //
+            break;
+        }
+
+        //
+        // Make this block read/write.
+        //
+        case FlashReadWrite:
+        default:
+        {
+            //
+            // The block can not be made read/write if it is not already
+            // read/write.
+            //
+            if((((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) ||
+               (((ui32ProtectPE >> ui32Address) & 0x1) != 0x1))
+            {
+                return(-1);
+            }
+
+            //
+            // The block is already read/write, so there is nothing to do.
+            //
+            return(0);
+        }
+    }
+
+    //
+    // Set the new protection for the specified flash bank.
+    //
+    HWREG(g_pui32FMPRERegs[ui32Bank]) = ui32ProtectRE;
+    HWREG(g_pui32FMPPERegs[ui32Bank]) = ui32ProtectPE;
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the flash protection settings.
+//!
+//! This function makes the currently programmed flash protection settings
+//! permanent.  This operation is non-reversible; a chip reset or power cycle
+//! does not change the flash protection.
+//!
+//! This function does not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashProtectSave(void)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Save the entire bank of 8 flash protection registers.
+    //
+    for(ui32Temp = 0; ui32Temp < 8; ui32Temp++)
+    {
+        //
+        // Tell the flash controller to write the flash protection register.
+        //
+        HWREG(FLASH_FMA) = ui32Temp;
+        HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+        //
+        // Wait until the write has completed.
+        //
+        while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+        {
+        }
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the user registers.
+//!
+//! \param pui32User0 is a pointer to the location to store USER Register 0.
+//! \param pui32User1 is a pointer to the location to store USER Register 1.
+//!
+//! This function reads the contents of user registers 0 and 1, and
+//! stores them in the specified locations.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1)
+{
+    //
+    // Verify that the pointers are valid.
+    //
+    ASSERT(pui32User0 != 0);
+    ASSERT(pui32User1 != 0);
+
+    //
+    // Get and store the current value of the user registers.
+    //
+    *pui32User0 = HWREG(FLASH_USERREG0);
+    *pui32User1 = HWREG(FLASH_USERREG1);
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the user registers.
+//!
+//! \param ui32User0 is the value to store in USER Register 0.
+//! \param ui32User1 is the value to store in USER Register 1.
+//!
+//! This function sets the contents of the user registers 0 and 1 to
+//! the specified values.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashUserSet(uint32_t ui32User0, uint32_t ui32User1)
+{
+    //
+    // Save the new values into the user registers.
+    //
+    HWREG(FLASH_USERREG0) = ui32User0;
+    HWREG(FLASH_USERREG1) = ui32User1;
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the user registers.
+//!
+//! This function makes the currently programmed user register 0 and 1 settings
+//! permanent.  This operation is non-reversible; a chip reset or power cycle
+//! does not change the flash protection.
+//!
+//! This function does not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashUserSave(void)
+{
+    //
+    // Setting the MSB of FMA will trigger a permanent save of a USER
+    // register.  Bit 0 will indicate User 0 (0) or User 1 (1).
+    //
+    HWREG(FLASH_FMA) = 0x80000000;
+    HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+    //
+    // Wait until the write has completed.
+    //
+    while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+    {
+    }
+
+    //
+    // Tell the flash controller to write the USER1 Register.
+    //
+    HWREG(FLASH_FMA) = 0x80000001;
+    HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+    //
+    // Wait until the write has completed.
+    //
+    while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+    {
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the flash interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the flash
+//! interrupt occurs.
+//!
+//! This function sets the handler to be called when the flash interrupt
+//! occurs.  The flash controller can generate an interrupt when an invalid
+//! flash access occurs, such as trying to program or erase a read-only block,
+//! or trying to read from an execute-only block.  It can also generate an
+//! interrupt when a program or erase operation has completed.  The interrupt
+//! is automatically enabled when the handler is registered.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntRegister(void (*pfnHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(INT_FLASH_TM4C123, pfnHandler);
+
+    //
+    // Enable the flash interrupt.
+    //
+    IntEnable(INT_FLASH_TM4C123);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash interrupt.
+//!
+//! This function clears the handler to be called when the flash interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntUnregister(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_FLASH_TM4C123);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_FLASH_TM4C123);
+}
+
+//*****************************************************************************
+//
+//! Enables individual flash controller interrupt sources.
+//!
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//! The ui32IntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted
+//! on a block of flash that is marked as read-only or execute-only.
+//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes.
+//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of
+//! the EEPROM interrupt can be determined by reading the EEDONE register.
+//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during
+//! the flash operation and the operation was terminated.
+//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that
+//! contains a 0 to a 1.
+//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails.
+//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails.
+//!
+//! This function enables the indicated flash controller interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntEnable(uint32_t ui32IntFlags)
+{
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(FLASH_FCIM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual flash controller interrupt sources.
+//!
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//! The ui32IntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted
+//! on a block of flash that is marked as read-only or execute-only.
+//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes.
+//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of
+//! the EEPROM interrupt can be determined by reading the EEDONE register.
+//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during
+//! the flash operation and the operation was terminated.
+//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that
+//! contains a 0 to a 1.
+//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails.
+//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails.
+//!
+//! This function disables the indicated flash controller interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntDisable(uint32_t ui32IntFlags)
+{
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(FLASH_FCIM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the flash controller.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b FLASH_INT_ACCESS, \b FLASH_INT_PROGRAM, \b FLASH_INT_EEPROM,
+//! FLASH_INT_VOLTAGE_ERR, FLASH_INT_DATA_ERR, FLASH_INT_ERASE_ERR, and
+//! FLASH_INT_PROGRAM_ERR.
+//
+//*****************************************************************************
+uint32_t
+FlashIntStatus(bool bMasked)
+{
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(FLASH_FCMISC));
+    }
+    else
+    {
+        return(HWREG(FLASH_FCRIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears flash controller interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared.
+//!
+//! The specified flash controller interrupt sources are cleared, so that they
+//! no longer assert.  The
+//! ui32IntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted
+//! on a block of flash that is marked as read-only or execute-only.
+//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes.
+//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of
+//! the EEPROM interrupt can be determined by reading the EEDONE register.
+//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during
+//! the flash operation and the operation was terminated.
+//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that
+//! contains a 0 to a 1.
+//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails.
+//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails.
+//!
+//! This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntClear(uint32_t ui32IntFlags)
+{
+    //
+    // Clear the flash interrupt.
+    //
+    HWREG(FLASH_FCMISC) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/flash.h b/bsp/tm4c129x/libraries/driverlib/flash.h
new file mode 100644
index 0000000000..e28f25862b
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/flash.h
@@ -0,0 +1,113 @@
+//*****************************************************************************
+//
+// flash.h - Prototypes for the flash driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_FLASH_H__
+#define __DRIVERLIB_FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+    FlashReadWrite,                         // Flash can be read and written
+    FlashReadOnly,                          // Flash can only be read
+    FlashExecuteOnly                        // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_PROGRAM     0x00000002 // Programming Interrupt Mask
+#define FLASH_INT_ACCESS      0x00000001 // Access Interrupt Mask
+#define FLASH_INT_EEPROM      0x00000004 // EEPROM Interrupt Mask
+#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
+#define FLASH_INT_DATA_ERR    0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_INT_ERASE_ERR   0x00000800 // Erase Error Interrupt Mask
+#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern int32_t FlashErase(uint32_t ui32Address);
+extern int32_t FlashProgram(uint32_t *pui32Data, uint32_t ui32Address,
+                            uint32_t ui32Count);
+extern tFlashProtection FlashProtectGet(uint32_t ui32Address);
+extern int32_t FlashProtectSet(uint32_t ui32Address,
+                               tFlashProtection eProtect);
+extern int32_t FlashProtectSave(void);
+extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1);
+extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1);
+extern int32_t FlashUserSave(void);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(uint32_t ui32IntFlags);
+extern void FlashIntDisable(uint32_t ui32IntFlags);
+extern uint32_t FlashIntStatus(bool bMasked);
+extern void FlashIntClear(uint32_t ui32IntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_FLASH_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/fpu.c b/bsp/tm4c129x/libraries/driverlib/fpu.c
new file mode 100644
index 0000000000..8ada474cb2
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/fpu.c
@@ -0,0 +1,300 @@
+//*****************************************************************************
+//
+// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M
+//         processor.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup fpu_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/fpu.h"
+
+//*****************************************************************************
+//
+//! Enables the floating-point unit.
+//!
+//! This function enables the floating-point unit, allowing the floating-point
+//! instructions to be executed.  This function must be called prior to
+//! performing any hardware floating-point operations; failure to do so results
+//! in a NOCP usage fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUEnable(void)
+{
+    //
+    // Enable the coprocessors used by the floating-point unit.
+    //
+    HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
+                         ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
+                        NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
+}
+
+//*****************************************************************************
+//
+//! Disables the floating-point unit.
+//!
+//! This function disables the floating-point unit, preventing floating-point
+//! instructions from executing (generating a NOCP usage fault instead).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUDisable(void)
+{
+    //
+    // Disable the coprocessors used by the floating-point unit.
+    //
+    HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
+                         ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
+                        NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS);
+}
+
+//*****************************************************************************
+//
+//! Enables the stacking of floating-point registers.
+//!
+//! This function enables the stacking of floating-point registers s0-s15 when
+//! an interrupt is handled.  When enabled, space is reserved on the stack for
+//! the floating-point context and the floating-point state is saved into this
+//! stack space.  Upon return from the interrupt, the floating-point context is
+//! restored.
+//!
+//! If the floating-point registers are not stacked, floating-point
+//! instructions cannot be safely executed in an interrupt handler because the
+//! values of s0-s15 are not likely to be preserved for the interrupted code.
+//! On the other hand, stacking the floating-point registers increases the
+//! stacking operation from 8 words to 26 words, also increasing the interrupt
+//! response latency.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUStackingEnable(void)
+{
+    //
+    // Enable automatic state preservation for the floating-point unit, and
+    // disable lazy state preservation (meaning that the floating-point state
+    // is always stacked when floating-point instructions are used).
+    //
+    HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the lazy stacking of floating-point registers.
+//!
+//! This function enables the lazy stacking of floating-point registers s0-s15
+//! when an interrupt is handled.  When lazy stacking is enabled, space is
+//! reserved on the stack for the floating-point context, but the
+//! floating-point state is not saved.  If a floating-point instruction is
+//! executed from within the interrupt context, the floating-point context is
+//! first saved into the space reserved on the stack.  On completion of the
+//! interrupt handler, the floating-point context is only restored if it was
+//! saved (as the result of executing a floating-point instruction).
+//!
+//! This method provides a compromise between fast interrupt response (because
+//! the floating-point state is not saved on interrupt entry) and the ability
+//! to use floating-point in interrupt handlers (because the floating-point
+//! state is saved if floating-point instructions are used).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPULazyStackingEnable(void)
+{
+    //
+    // Enable automatic and lazy state preservation for the floating-point
+    // unit.
+    //
+    HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the stacking of floating-point registers.
+//!
+//! This function disables the stacking of floating-point registers s0-s15 when
+//! an interrupt is handled.  When floating-point context stacking is disabled,
+//! floating-point operations performed in an interrupt handler destroy the
+//! floating-point context of the main thread of execution.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUStackingDisable(void)
+{
+    //
+    // Disable automatic and lazy state preservation for the floating-point
+    // unit.
+    //
+    HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN);
+}
+
+//*****************************************************************************
+//
+//! Selects the format of half-precision floating-point values.
+//!
+//! \param ui32Mode is the format for half-precision floating-point value,
+//! which is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
+//!
+//! This function selects between the IEEE half-precision floating-point
+//! representation and the Cortex-M processor alternative representation.  The
+//! alternative representation has a larger range but does not have a way to
+//! encode infinity (positive or negative) or NaN (quiet or signaling).  The
+//! default setting is the IEEE format.
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUHalfPrecisionModeSet(uint32_t ui32Mode)
+{
+    //
+    // Set the half-precision floating-point format.
+    //
+    HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Selects the NaN mode.
+//!
+//! \param ui32Mode is the mode for NaN results; which is either
+//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
+//!
+//! This function selects the handling of NaN results during floating-point
+//! computations.  NaNs can either propagate (the default), or they can return
+//! the default NaN.
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUNaNModeSet(uint32_t ui32Mode)
+{
+    //
+    // Set the NaN mode.
+    //
+    HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Selects the flush-to-zero mode.
+//!
+//! \param ui32Mode is the flush-to-zero mode; which is either
+//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
+//!
+//! This function enables or disables the flush-to-zero mode of the
+//! floating-point unit.  When disabled (the default), the floating-point unit
+//! is fully IEEE compliant.  When enabled, values close to zero are treated as
+//! zero, greatly improving the execution speed at the expense of some accuracy
+//! (as well as IEEE compliance).
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPUFlushToZeroModeSet(uint32_t ui32Mode)
+{
+    //
+    // Set the flush-to-zero mode.
+    //
+    HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Selects the rounding mode for floating-point results.
+//!
+//! \param ui32Mode is the rounding mode.
+//!
+//! This function selects the rounding mode for floating-point results.  After
+//! a floating-point operation, the result is rounded toward the specified
+//! value.  The default mode is \b FPU_ROUND_NEAREST.
+//!
+//! The following rounding modes are available (as specified by \e ui32Mode):
+//!
+//! - \b FPU_ROUND_NEAREST - round toward the nearest value
+//! - \b FPU_ROUND_POS_INF - round toward positive infinity
+//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
+//! - \b FPU_ROUND_ZERO - round toward zero
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FPURoundingModeSet(uint32_t ui32Mode)
+{
+    //
+    // Set the rounding mode.
+    //
+    HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ui32Mode;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/fpu.h b/bsp/tm4c129x/libraries/driverlib/fpu.h
new file mode 100644
index 0000000000..e6010f4e7c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/fpu.h
@@ -0,0 +1,113 @@
+//*****************************************************************************
+//
+// fpu.h - Prototypes for the floatint point manipulation routines.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_FPU_H__
+#define __DRIVERLIB_FPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter.
+//
+//*****************************************************************************
+#define FPU_HALF_IEEE           0x00000000
+#define FPU_HALF_ALTERNATE      0x04000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter.
+//
+//*****************************************************************************
+#define FPU_NAN_PROPAGATE       0x00000000
+#define FPU_NAN_DEFAULT         0x02000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode
+// parameter.
+//
+//*****************************************************************************
+#define FPU_FLUSH_TO_ZERO_DIS   0x00000000
+#define FPU_FLUSH_TO_ZERO_EN    0x01000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter.
+//
+//*****************************************************************************
+#define FPU_ROUND_NEAREST       0x00000000
+#define FPU_ROUND_POS_INF       0x00400000
+#define FPU_ROUND_NEG_INF       0x00800000
+#define FPU_ROUND_ZERO          0x00c00000
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern void FPUEnable(void);
+extern void FPUDisable(void);
+extern void FPUStackingEnable(void);
+extern void FPULazyStackingEnable(void);
+extern void FPUStackingDisable(void);
+extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode);
+extern void FPUNaNModeSet(uint32_t ui32Mode);
+extern void FPUFlushToZeroModeSet(uint32_t ui32Mode);
+extern void FPURoundingModeSet(uint32_t ui32Mode);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_FPU_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/gpio.c b/bsp/tm4c129x/libraries/driverlib/gpio.c
new file mode 100644
index 0000000000..7154939246
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/gpio.c
@@ -0,0 +1,2671 @@
+//*****************************************************************************
+//
+// gpio.c - API for GPIO ports
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup gpio_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/gpio.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// A mapping of GPIO port address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32GPIOIntMapBlizzard[][2] =
+{
+    { GPIO_PORTA_BASE, INT_GPIOA_TM4C123 },
+    { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C123 },
+    { GPIO_PORTB_BASE, INT_GPIOB_TM4C123 },
+    { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C123 },
+    { GPIO_PORTC_BASE, INT_GPIOC_TM4C123 },
+    { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C123 },
+    { GPIO_PORTD_BASE,  INT_GPIOD_TM4C123 },
+    { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C123 },
+    { GPIO_PORTE_BASE, INT_GPIOE_TM4C123 },
+    { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C123 },
+    { GPIO_PORTF_BASE, INT_GPIOF_TM4C123 },
+    { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C123 },
+    { GPIO_PORTG_BASE, INT_GPIOG_TM4C123 },
+    { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C123 },
+    { GPIO_PORTH_BASE, INT_GPIOH_TM4C123 },
+    { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C123 },
+    { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C123 },
+    { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C123 },
+    { GPIO_PORTK_BASE, INT_GPIOK_TM4C123 },
+    { GPIO_PORTL_BASE, INT_GPIOL_TM4C123 },
+    { GPIO_PORTM_BASE, INT_GPIOM_TM4C123 },
+    { GPIO_PORTN_BASE, INT_GPION_TM4C123 },
+    { GPIO_PORTP_BASE, INT_GPIOP0_TM4C123 },
+    { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C123 },
+};
+static const uint_fast32_t g_ui32GPIOIntMapBlizzardRows =
+    sizeof(g_ppui32GPIOIntMapBlizzard) / sizeof(g_ppui32GPIOIntMapBlizzard[0]);
+
+static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] =
+{
+    { GPIO_PORTA_BASE, INT_GPIOA_TM4C129 },
+    { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C129 },
+    { GPIO_PORTB_BASE, INT_GPIOB_TM4C129 },
+    { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C129 },
+    { GPIO_PORTC_BASE, INT_GPIOC_TM4C129 },
+    { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C129 },
+    { GPIO_PORTD_BASE,  INT_GPIOD_TM4C129 },
+    { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C129 },
+    { GPIO_PORTE_BASE, INT_GPIOE_TM4C129 },
+    { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C129 },
+    { GPIO_PORTF_BASE, INT_GPIOF_TM4C129 },
+    { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C129 },
+    { GPIO_PORTG_BASE, INT_GPIOG_TM4C129 },
+    { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C129 },
+    { GPIO_PORTH_BASE, INT_GPIOH_TM4C129 },
+    { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C129 },
+    { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C129 },
+    { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C129 },
+    { GPIO_PORTK_BASE, INT_GPIOK_TM4C129 },
+    { GPIO_PORTL_BASE, INT_GPIOL_TM4C129 },
+    { GPIO_PORTM_BASE, INT_GPIOM_TM4C129 },
+    { GPIO_PORTN_BASE, INT_GPION_TM4C129 },
+    { GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 },
+    { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 },
+};
+static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows =
+    (sizeof(g_ppui32GPIOIntMapSnowflake) /
+     sizeof(g_ppui32GPIOIntMapSnowflake[0]));
+
+//*****************************************************************************
+//
+// The base addresses of all the GPIO modules.  Both the APB and AHB apertures
+// are provided.
+//
+//*****************************************************************************
+static const uint32_t g_pui32GPIOBaseAddrs[] =
+{
+    GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE,
+    GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE,
+    GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE,
+    GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE,
+    GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE,
+    GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE,
+    GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE,
+    GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE,
+    GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE,
+    GPIO_PORTK_BASE, GPIO_PORTK_BASE,
+    GPIO_PORTL_BASE, GPIO_PORTL_BASE,
+    GPIO_PORTM_BASE, GPIO_PORTM_BASE,
+    GPIO_PORTN_BASE, GPIO_PORTN_BASE,
+    GPIO_PORTP_BASE, GPIO_PORTP_BASE,
+    GPIO_PORTQ_BASE, GPIO_PORTQ_BASE,
+    GPIO_PORTR_BASE, GPIO_PORTR_BASE,
+    GPIO_PORTS_BASE, GPIO_PORTS_BASE,
+    GPIO_PORTT_BASE, GPIO_PORTT_BASE,
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a GPIO base address.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//!
+//! This function determines if a GPIO port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_GPIOBaseValid(uint32_t ui32Port)
+{
+    return((ui32Port == GPIO_PORTA_BASE) ||
+           (ui32Port == GPIO_PORTA_AHB_BASE) ||
+           (ui32Port == GPIO_PORTB_BASE) ||
+           (ui32Port == GPIO_PORTB_AHB_BASE) ||
+           (ui32Port == GPIO_PORTC_BASE) ||
+           (ui32Port == GPIO_PORTC_AHB_BASE) ||
+           (ui32Port == GPIO_PORTD_BASE) ||
+           (ui32Port == GPIO_PORTD_AHB_BASE) ||
+           (ui32Port == GPIO_PORTE_BASE) ||
+           (ui32Port == GPIO_PORTE_AHB_BASE) ||
+           (ui32Port == GPIO_PORTF_BASE) ||
+           (ui32Port == GPIO_PORTF_AHB_BASE) ||
+           (ui32Port == GPIO_PORTG_BASE) ||
+           (ui32Port == GPIO_PORTG_AHB_BASE) ||
+           (ui32Port == GPIO_PORTH_BASE) ||
+           (ui32Port == GPIO_PORTH_AHB_BASE) ||
+           (ui32Port == GPIO_PORTJ_BASE) ||
+           (ui32Port == GPIO_PORTJ_AHB_BASE) ||
+           (ui32Port == GPIO_PORTK_BASE) ||
+           (ui32Port == GPIO_PORTL_BASE) ||
+           (ui32Port == GPIO_PORTM_BASE) ||
+           (ui32Port == GPIO_PORTN_BASE) ||
+           (ui32Port == GPIO_PORTP_BASE) ||
+           (ui32Port == GPIO_PORTQ_BASE) ||
+           (ui32Port == GPIO_PORTR_BASE) ||
+           (ui32Port == GPIO_PORTS_BASE) ||
+           (ui32Port == GPIO_PORTT_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Gets the GPIO interrupt number.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//!
+//! Given a GPIO base address, this function returns the corresponding
+//! interrupt number.
+//!
+//! \return Returns a GPIO interrupt number, or 0 if \e ui32Port is invalid.
+//
+//*****************************************************************************
+static uint32_t
+_GPIOIntNumberGet(uint32_t ui32Port)
+{
+    uint_fast32_t ui32Idx, ui32Rows;
+    const uint32_t (*ppui32GPIOIntMap)[2];
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    ppui32GPIOIntMap = g_ppui32GPIOIntMapBlizzard;
+    ui32Rows = g_ui32GPIOIntMapBlizzardRows;
+
+    if(CLASS_IS_TM4C129)
+    {
+        ppui32GPIOIntMap = g_ppui32GPIOIntMapSnowflake;
+        ui32Rows = g_ui32GPIOIntMapSnowflakeRows;
+    }
+
+    //
+    // Loop through the table that maps I2C base addresses to interrupt
+    // numbers.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Rows; ui32Idx++)
+    {
+        //
+        // See if this base address matches.
+        //
+        if(ppui32GPIOIntMap[ui32Idx][0] == ui32Port)
+        {
+            //
+            // Return the corresponding interrupt number.
+            //
+            return(ppui32GPIOIntMap[ui32Idx][1]);
+        }
+    }
+
+    //
+    // The base address could not be found, so return an error.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the direction and mode of the specified pin(s).
+//!
+//! \param ui32Port is the base address of the GPIO port
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//! \param ui32PinIO is the pin direction and/or mode.
+//!
+//! This function configures the specified pin(s) on the selected GPIO port
+//! as either input or output under software control, or it configures the
+//! pin to be under hardware control.
+//!
+//! The parameter \e ui32PinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_DIR_MODE_IN
+//! - \b GPIO_DIR_MODE_OUT
+//! - \b GPIO_DIR_MODE_HW
+//!
+//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a
+//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is
+//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW
+//! specifies that the pin is placed under hardware control.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note GPIOPadConfigSet() must also be used to configure the corresponding
+//! pad(s) in order for them to propagate the signal to/from the GPIO.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32PinIO)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+    ASSERT((ui32PinIO == GPIO_DIR_MODE_IN) ||
+           (ui32PinIO == GPIO_DIR_MODE_OUT) ||
+           (ui32PinIO == GPIO_DIR_MODE_HW));
+
+    //
+    // Set the pin direction and mode.
+    //
+    HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ?
+                                    (HWREG(ui32Port + GPIO_O_DIR) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_DIR) & ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ?
+                                      (HWREG(ui32Port + GPIO_O_AFSEL) |
+                                       ui8Pins) :
+                                      (HWREG(ui32Port + GPIO_O_AFSEL) &
+                                       ~(ui8Pins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the direction and mode of a pin.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pin is the pin number.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port.  The pin can be configured as either an input or
+//! output under software control, or it can be under hardware control.  The
+//! type of control and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+uint32_t
+GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin)
+{
+    uint32_t ui32Dir, ui32AFSEL;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+    ASSERT(ui8Pin < 8);
+
+    //
+    // Convert from a pin number to a bit position.
+    //
+    ui8Pin = 1 << ui8Pin;
+
+    //
+    // Return the pin direction and mode.
+    //
+    ui32Dir = HWREG(ui32Port + GPIO_O_DIR);
+    ui32AFSEL = HWREG(ui32Port + GPIO_O_AFSEL);
+    return(((ui32Dir & ui8Pin) ? 1 : 0) | ((ui32AFSEL & ui8Pin) ? 2 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the interrupt type for the specified pin(s).
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//! \param ui32IntType specifies the type of interrupt trigger mechanism.
+//!
+//! This function sets up the various interrupt trigger mechanisms for the
+//! specified pin(s) on the selected GPIO port.
+//!
+//! One of the following flags can be used to define the \e ui32IntType
+//! parameter:
+//!
+//! - \b GPIO_FALLING_EDGE sets detection to edge and trigger to falling
+//! - \b GPIO_RISING_EDGE sets detection to edge and trigger to rising
+//! - \b GPIO_BOTH_EDGES sets detection to both edges
+//! - \b GPIO_LOW_LEVEL sets detection to low level
+//! - \b GPIO_HIGH_LEVEL sets detection to high level
+//!
+//! In addition to the above flags, the following flag can be OR'd in to the
+//! \e ui32IntType parameter:
+//!
+//! - \b GPIO_DISCRETE_INT sets discrete interrupts for each pin on a GPIO
+//! port.
+//!
+//! The \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports,
+//! consult the data sheet to ensure that the device and the GPIO port supports
+//! discrete interrupts.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note In order to avoid any spurious interrupts, the user must ensure that
+//! the GPIO inputs remain stable for the duration of this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
+               uint32_t ui32IntType)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+    ASSERT((ui32IntType == GPIO_FALLING_EDGE) ||
+           (ui32IntType == GPIO_RISING_EDGE) ||
+           (ui32IntType == GPIO_BOTH_EDGES) ||
+           (ui32IntType == GPIO_LOW_LEVEL) ||
+           (ui32IntType == GPIO_HIGH_LEVEL));
+
+    //
+    // Set the pin interrupt type.
+    //
+    HWREG(ui32Port + GPIO_O_IBE) = ((ui32IntType & 1) ?
+                                    (HWREG(ui32Port + GPIO_O_IBE) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_IBE) & ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_IS) = ((ui32IntType & 2) ?
+                                   (HWREG(ui32Port + GPIO_O_IS) | ui8Pins) :
+                                   (HWREG(ui32Port + GPIO_O_IS) & ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_IEV) = ((ui32IntType & 4) ?
+                                    (HWREG(ui32Port + GPIO_O_IEV) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_IEV) & ~(ui8Pins)));
+
+    //
+    // Set or clear the discrete interrupt feature.  This is not available
+    // on all parts or ports but is safe to write in all cases.
+    //
+    HWREG(ui32Port + GPIO_O_SI) = ((ui32IntType & 0x10000) ?
+                                   (HWREG(ui32Port + GPIO_O_SI) | 0x01) :
+                                   (HWREG(ui32Port + GPIO_O_SI) & ~(0x01)));
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt type for a pin.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pin is the pin number.
+//!
+//! This function gets the interrupt type for a specified pin on the selected
+//! GPIO port.  The pin can be configured as a falling-edge, rising-edge, or
+//! both-edges detected interrupt, or it can be configured as a low-level or
+//! high-level detected interrupt.  The type of interrupt detection mechanism
+//! is returned and can include the \b GPIO_DISCRETE_INT flag.
+//!
+//! \return Returns one of the flags described for GPIOIntTypeSet().
+//
+//*****************************************************************************
+uint32_t
+GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin)
+{
+    uint32_t ui32IBE, ui32IS, ui32IEV, ui32SI;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+    ASSERT(ui8Pin < 8);
+
+    //
+    // Convert from a pin number to a bit position.
+    //
+    ui8Pin = 1 << ui8Pin;
+
+    //
+    // Return the pin interrupt type.
+    //
+    ui32IBE = HWREG(ui32Port + GPIO_O_IBE);
+    ui32IS = HWREG(ui32Port + GPIO_O_IS);
+    ui32IEV = HWREG(ui32Port + GPIO_O_IEV);
+    ui32SI = HWREG(ui32Port + GPIO_O_SI);
+    return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) |
+           ((ui32IEV & ui8Pin) ? 4 : 0) | (ui32SI & 0x01) ? 0x10000 : 0);
+}
+
+//*****************************************************************************
+//
+//! Sets the pad configuration for the specified pin(s).
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//! \param ui32Strength specifies the output drive strength.
+//! \param ui32PinType specifies the pin type.
+//!
+//! This function sets the drive strength and type for the specified pin(s)
+//! on the selected GPIO port.  For pin(s) configured as input ports, the
+//! pad is configured as requested, but the only real effect on the input
+//! is the configuration of the pull-up or pull-down termination.
+//!
+//! The parameter \e ui32Strength can be one of the following values:
+//!
+//! - \b GPIO_STRENGTH_2MA
+//! - \b GPIO_STRENGTH_4MA
+//! - \b GPIO_STRENGTH_8MA
+//! - \b GPIO_STRENGTH_8MA_SC
+//! - \b GPIO_STRENGTH_6MA
+//! - \b GPIO_STRENGTH_10MA
+//! - \b GPIO_STRENGTH_12MA
+//!
+//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive
+//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with
+//! slew control.
+//!
+//! Some Tiva devices also support output drive strengths of 6, 10, and 12
+//! mA.
+//!
+//! The parameter \e ui32PinType can be one of the following values:
+//!
+//! - \b GPIO_PIN_TYPE_STD
+//! - \b GPIO_PIN_TYPE_STD_WPU
+//! - \b GPIO_PIN_TYPE_STD_WPD
+//! - \b GPIO_PIN_TYPE_OD
+//! - \b GPIO_PIN_TYPE_ANALOG
+//! - \b GPIO_PIN_TYPE_WAKE_HIGH
+//! - \b GPIO_PIN_TYPE_WAKE_LOW
+//!
+//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
+//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
+//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an analog
+//! input.
+//!
+//! The \b GPIO_PIN_TYPE_WAKE_* settings specify the pin to be used as a
+//! hibernation wake source.  The pin sense level can be high or low.  These
+//! settings are only available on some Tiva devices.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins,
+                 uint32_t ui32Strength, uint32_t ui32PinType)
+{
+    uint8_t ui8Bit;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+    ASSERT((ui32Strength == GPIO_STRENGTH_2MA) ||
+           (ui32Strength == GPIO_STRENGTH_4MA) ||
+           (ui32Strength == GPIO_STRENGTH_6MA) ||
+           (ui32Strength == GPIO_STRENGTH_8MA) ||
+           (ui32Strength == GPIO_STRENGTH_8MA_SC) ||
+           (ui32Strength == GPIO_STRENGTH_10MA) ||
+           (ui32Strength == GPIO_STRENGTH_12MA));
+    ASSERT((ui32PinType == GPIO_PIN_TYPE_STD) ||
+           (ui32PinType == GPIO_PIN_TYPE_STD_WPU) ||
+           (ui32PinType == GPIO_PIN_TYPE_STD_WPD) ||
+           (ui32PinType == GPIO_PIN_TYPE_OD) ||
+           (ui32PinType == GPIO_PIN_TYPE_WAKE_LOW) ||
+           (ui32PinType == GPIO_PIN_TYPE_WAKE_HIGH) ||
+           (ui32PinType == GPIO_PIN_TYPE_ANALOG));
+
+
+    //
+    // Set the GPIO peripheral configuration register first as required.  This
+    // register only appears in TM4E111 and later device classes, but is a
+    // harmless write on older devices. Walk pins 0-7 and clear or set the
+    // provided PC[EDMn] encoding.
+    //
+    for(ui8Bit = 0; ui8Bit < 8; ui8Bit++)
+    {
+        if(ui8Pins & (1 << ui8Bit))
+        {
+            HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) &
+                                           ~(0x3 << (2 * ui8Bit)));
+            HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) <<
+                                            (2 * ui8Bit));
+        }
+    }
+
+    //
+    // Set the output drive strength.
+    //
+    HWREG(ui32Port + GPIO_O_DR2R) = ((ui32Strength & 1) ?
+                                     (HWREG(ui32Port + GPIO_O_DR2R) |
+                                      ui8Pins) :
+                                     (HWREG(ui32Port + GPIO_O_DR2R) &
+                                      ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_DR4R) = ((ui32Strength & 2) ?
+                                     (HWREG(ui32Port + GPIO_O_DR4R) |
+                                      ui8Pins) :
+                                     (HWREG(ui32Port + GPIO_O_DR4R) &
+                                      ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_DR8R) = ((ui32Strength & 4) ?
+                                     (HWREG(ui32Port + GPIO_O_DR8R) |
+                                      ui8Pins) :
+                                     (HWREG(ui32Port + GPIO_O_DR8R) &
+                                      ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_SLR) = ((ui32Strength & 8) ?
+                                    (HWREG(ui32Port + GPIO_O_SLR) |
+                                     ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_SLR) &
+                                     ~(ui8Pins)));
+
+    //
+    // Set the 12-mA drive select register.  This register only appears in
+    // TM4E111 and later device classes, but is a harmless write on older
+    // devices.
+    //
+    HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ?
+                                      (HWREG(ui32Port + GPIO_O_DR12R) |
+                                       ui8Pins) :
+                                      (HWREG(ui32Port + GPIO_O_DR12R) &
+                                       ~(ui8Pins)));
+
+    //
+    // Set the pin type.
+    //
+    HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ?
+                                    (HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ?
+                                    (HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ?
+                                    (HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ?
+                                    (HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) :
+                                    (HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins)));
+
+    //
+    // Set the wake pin enable register and the wake level register.  These
+    // registers only appear in TM4E111 and later device classes, but are
+    // harmless writes on older devices.
+    //
+    HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ?
+                                        (HWREG(ui32Port + GPIO_O_WAKELVL) |
+                                         ui8Pins) :
+                                        (HWREG(ui32Port + GPIO_O_WAKELVL) &
+                                         ~(ui8Pins)));
+    HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ?
+                                        (HWREG(ui32Port + GPIO_O_WAKEPEN) |
+                                         ui8Pins) :
+                                        (HWREG(ui32Port + GPIO_O_WAKEPEN) &
+                                         ~(ui8Pins)));
+
+    //
+    // Set the analog mode select register.
+    //
+    HWREG(ui32Port + GPIO_O_AMSEL) =
+        ((ui32PinType == GPIO_PIN_TYPE_ANALOG) ?
+         (HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) :
+         (HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the pad configuration for a pin.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pin is the pin number.
+//! \param pui32Strength is a pointer to storage for the output drive strength.
+//! \param pui32PinType is a pointer to storage for the output drive type.
+//!
+//! This function gets the pad configuration for a specified pin on the
+//! selected GPIO port.  The values returned in \e pui32Strength and
+//! \e pui32PinType correspond to the values used in GPIOPadConfigSet().  This
+//! function also works for pin(s) configured as input pin(s); however, the
+//! only meaningful data returned is whether the pin is terminated with a
+//! pull-up or down resistor.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin,
+                 uint32_t *pui32Strength, uint32_t *pui32PinType)
+{
+    uint32_t ui32PinType, ui32Strength;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+    ASSERT(ui8Pin < 8);
+
+    //
+    // Convert from a pin number to a bit position.
+    //
+    ui8Pin = (1 << ui8Pin);
+
+    //
+    // Get the drive strength for this pin.
+    //
+    ui32Strength = ((HWREG(ui32Port + GPIO_O_DR2R) & ui8Pin) ? 1 : 0);
+    ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR4R) & ui8Pin) ? 2 : 0);
+    ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR8R) & ui8Pin) ? 4 : 0);
+    ui32Strength |= ((HWREG(ui32Port + GPIO_O_SLR) & ui8Pin) ? 8 : 0);
+    ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0);
+    ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >>
+                       (2 * ui8Pin)) & 0x3) << 5);
+    *pui32Strength = ui32Strength;
+
+    //
+    // Get the pin type.
+    //
+    ui32PinType = ((HWREG(ui32Port + GPIO_O_ODR) & ui8Pin) ? 1 : 0);
+    ui32PinType |= ((HWREG(ui32Port + GPIO_O_PUR) & ui8Pin) ? 2 : 0);
+    ui32PinType |= ((HWREG(ui32Port + GPIO_O_PDR) & ui8Pin) ? 4 : 0);
+    ui32PinType |= ((HWREG(ui32Port + GPIO_O_DEN) & ui8Pin) ? 8 : 0);
+    if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin)
+    {
+        ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ?
+                        0x200 : 0x100);
+    }
+    *pui32PinType = ui32PinType;
+}
+
+//*****************************************************************************
+//
+//! Enables the specified GPIO interrupts.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to enable.
+//!
+//! This function enables the indicated GPIO interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
+//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
+//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
+//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
+//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
+//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
+//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
+//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
+//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module.
+//!
+//! \note If this call is being used to enable summary interrupts on GPIO port
+//! P or Q (GPIOIntTypeSet() with GPIO_DISCRETE_INT not enabled), then all
+//! individual interrupts for these ports must be enabled in the GPIO module
+//! using GPIOIntEnable() and all but the interrupt for pin 0 must be disabled
+//! in the NVIC using the IntDisable() function.  The summary interrupts for
+//! the ports are routed to the INT_GPIOP0 or INT_GPIOQ0 which must be enabled
+//! to handle the interrupt.  If this is not done then any individual GPIO pin
+//! interrupts that are left enabled also trigger the individual interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Enable the interrupts.
+    //
+    HWREG(ui32Port + GPIO_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the specified GPIO interrupts.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! This function disables the indicated GPIO interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
+//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
+//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
+//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
+//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
+//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
+//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
+//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
+//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Disable the interrupts.
+    //
+    HWREG(ui32Port + GPIO_O_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified GPIO port.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status is returned.
+//!
+//! \return Returns the current interrupt status for the specified GPIO module.
+//! The value returned is the logical OR of the \b GPIO_INT_* values that are
+//! currently active.
+//
+//*****************************************************************************
+uint32_t
+GPIOIntStatus(uint32_t ui32Port, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Return the interrupt status.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Port + GPIO_O_MIS));
+    }
+    else
+    {
+        return(HWREG(ui32Port + GPIO_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the specified interrupt sources.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! Clears the interrupt for the specified interrupt source(s).
+//!
+//! The \e ui32IntFlags parameter is the logical OR of the \b GPIO_INT_*
+//! values.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Clear the interrupts.
+    //
+    HWREG(ui32Port + GPIO_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a GPIO port.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function ensures that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! GPIO port.  This function also enables the corresponding GPIO interrupt
+//! in the interrupt controller; individual pin interrupts and interrupt
+//! sources must be enabled with GPIOIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Get the interrupt number associated with the specified GPIO.
+    //
+    ui32Int = _GPIOIntNumberGet(ui32Port);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnIntHandler);
+
+    //
+    // Enable the GPIO interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for a GPIO port.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//!
+//! This function unregisters the interrupt handler for the specified
+//! GPIO port.  This function also disables the corresponding
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
+//! and interrupt sources must be disabled with GPIOIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntUnregister(uint32_t ui32Port)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Get the interrupt number associated with the specified GPIO.
+    //
+    ui32Int = _GPIOIntNumberGet(ui32Port);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the GPIO interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Reads the values present of the specified pin(s).
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The values at the specified pin(s) are read, as specified by \e ui8Pins.
+//! Values are returned for both input and output pin(s), and the value
+//! for pin(s) that are not specified by \e ui8Pins are set to 0.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return Returns a bit-packed byte providing the state of the specified
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
+//! GPIO port pin 1, and so on.  Any bit that is not specified by \e ui8Pins
+//! is returned as a 0.  Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+int32_t
+GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Return the pin value(s).
+    //
+    return(HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to the specified pin(s).
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//! \param ui8Val is the value to write to the pin(s).
+//!
+//! Writes the corresponding bit values to the output pin(s) specified by
+//! \e ui8Pins.  Writing to a pin configured as an input pin has no effect.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Write the pins.
+    //
+    HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))) = ui8Val;
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as analog-to-digital converter inputs.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The analog-to-digital converter input pins must be properly configured for
+//! the analog-to-digital peripheral to function correctly.  This function
+//! provides the proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an ADC input; it
+//! only configures an ADC input pin for proper operation.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for analog operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as a CAN device.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The CAN pins must be properly configured for the CAN peripherals to
+//! function correctly.  This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a CAN pin; it only
+//! configures a CAN pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the CAN
+//!  function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an analog comparator input.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The analog comparator input pins must be properly configured for the analog
+//! comparator to function correctly.  This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an analog
+//! comparator input; it only configures an analog comparator pin for proper
+//! operation.  Note that a GPIOPinConfigure() function call is also required
+//! to properly configure a pin for the analog comparator function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for analog operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the external peripheral interface.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The external peripheral interface pins must be properly configured for the
+//! external peripheral interface to function correctly.  This function
+//! provides a typical configuration for those pin(s); other configurations may
+//! work as well depending upon the board setup (for example, using the on-chip
+//! pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an external
+//! peripheral interface pin; it only configures an external peripheral
+//! interface pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the
+//! external peripheral interface function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Ethernet peripheral as LED signals.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The Ethernet peripheral provides four signals that can be used to drive
+//! an LED (for example, for link status/activity).  This function provides a
+//! typical configuration for the pins.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an Ethernet LED
+//! pin; it only configures an Ethernet LED pin for proper operation.  Note
+//! that a GPIOPinConfigure() function call is also required to properly
+//! configure the pin for the Ethernet LED function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Ethernet peripheral as MII signals.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The Ethernet peripheral on some parts provides a set of MII signals that
+//! are used to connect to an external PHY.  This function provides a typical
+//! configuration for the pins.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an Ethernet MII
+//! pin; it only configures an Ethernet MII pin for proper operation.  Note
+//! that a GPIOPinConfigure() function call is also required to properly
+//! configure the pin for the Ethernet MII function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO inputs.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO inputs.  This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO outputs.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs.  This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+
+    //
+    // Make the pin(s) be outputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO open drain outputs.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs.  This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+
+    //
+    // Make the pin(s) be outputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT);
+}
+
+//*****************************************************************************
+//
+//! Configures pin for use as SDA by the I2C peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin.
+//!
+//! The I2C pins must be properly configured for the I2C peripheral to function
+//! correctly.  This function provides the proper configuration for the SDA
+//! pin.
+//!
+//! The pin is specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an I2C SDA pin; it
+//! only configures an I2C SDA pin for proper operation.  Note that a
+//! GPIOPinConfigure() function call is also required to properly configure a
+//! pin for the I2C SDA function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for open-drain operation with a weak pull-up.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin for use as SCL by the I2C peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin.
+//!
+//! The I2C pins must be properly configured for the I2C peripheral to function
+//! correctly.  This function provides the proper configuration for the SCL
+//! pin.
+//!
+//! The pin is specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an I2C SCL pin; it
+//! only configures an I2C SCL pin for proper operation.  Note that a
+//! GPIOPinConfigure() function call is also required to properly configure a
+//! pin for the I2C SCL function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the LCD Controller.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The LCD controller pins must be properly configured for the LCD controller
+//! to function correctly.  This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an LCD pin; it only
+//! configures an LCD pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the LCD
+//! controller function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation and beefed up drive.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the LPC module.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The LPC pins must be properly configured for the LPC module to function
+//! correctly.  This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an LPC pin; it only
+//! configures an LPC pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the LPC
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeLPC(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures a pin for receive use by the PECI module.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The PECI receive pin must be properly configured for the PECI module to
+//! function correctly.  This function provides a typical configuration for
+//! that pin.
+//!
+//! The pin is specified using a bit-packed byte, where each bit that is set
+//! identifies the pin to be accessed, and where bit 0 of the byte represents
+//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a PECI receive pin;
+//! it only configures a PECI receive pin for proper operation.  Note that a
+//! GPIOPinConfigure() function call is also required to properly configure a
+//! pin for the PECI receive function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypePECIRx(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for analog operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures a pin for transmit use by the PECI module.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The PECI transmit pin must be properly configured for the PECI module to
+//! function correctly.  This function provides a typical configuration for
+//! that pin.
+//!
+//! The pin is specified using a bit-packed byte, where each bit that is set
+//! identifies the pin to be accessed, and where bit 0 of the byte represents
+//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a PECI transmit
+//! pin; it only configures a PECI transmit pin for proper operation.  Note
+//! that a GPIOPinConfigure() function call is also required to properly
+//! configure the pin for the PECI transmit function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypePECITx(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for analog operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the PWM peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The PWM pins must be properly configured for the PWM peripheral to function
+//! correctly.  This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a PWM pin; it only
+//! configures a PWM pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the PWM
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the QEI peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The QEI pins must be properly configured for the QEI peripheral to function
+//! correctly.  This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, not using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a QEI pin; it only
+//! configures a QEI pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the QEI
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation with a weak pull-up.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_STD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the SSI peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The SSI pins must be properly configured for the SSI peripheral to function
+//! correctly.  This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a SSI pin; it only
+//! configures a SSI pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the SSI
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Timer peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The CCP pins must be properly configured for the timer peripheral to
+//! function correctly.  This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a timer pin; it
+//! only configures a timer pin for proper operation.  Note that a
+//! GPIOPinConfigure() function call is also required to properly configure a
+//! pin for the CCP function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the UART peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The UART pins must be properly configured for the UART peripheral to
+//! function correctly.  This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a UART pin; it
+//! only configures a UART pin for proper operation.  Note that a
+//! GPIOPinConfigure() function call is also required to properly configure a
+//!  pin for the UART function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! USB analog pins must be properly configured for the USB peripheral to
+//! function correctly.  This function provides the proper configuration for
+//! any USB analog pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the USB
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for analog operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! USB digital pins must be properly configured for the USB peripheral to
+//! function correctly.  This function provides a typical configuration for
+//! the digital USB pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! This function should only be used with EPEN and PFAULT pins as all other
+//! USB pins are analog in nature or are not used in devices without OTG
+//! functionality.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the USB
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as a hibernate wake-on-high source.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! hibernate wake-high inputs.  This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for wake-high operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_WAKE_HIGH);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as a hibernate wake-on-low source.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! hibernate wake-low inputs.  This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for wake-high operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_WAKE_LOW);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as scan matrix keyboard rows (outputs).
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! scan matrix keyboard outputs.  This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a scan matrix
+//! keyboard row pin; it only configures a scan matrix keyboard row pin for
+//! proper operation.  Note that a GPIOPinConfigure() function call is also
+//! required to properly configure a pin for the scan matrix keyboard
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeKBRow(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for push/pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as scan matrix keyboard columns (inputs).
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! scan matrix keyboard inputs.  This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a scan matrix
+//! keyboard column pin; it only configures a scan matrix keyboard column pin
+//! for proper operation.  Note that a GPIOPinConfigure() function call is also
+//! required to properly configure a pin for the scan matrix keyboard
+//! function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeKBColumn(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
+                     GPIO_PIN_TYPE_STD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an LED sequencer output.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! LED sequencers.  This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into an LED sequencer
+//! output pin; it only configures an LED sequencer output pin for proper
+//! operation.  Note that a GPIOPinConfigure() function call is also
+//! required to properly configure a pin for the LED sequencer function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeLEDSeq(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for push/pull operation and 8mA strength.  The external
+    // hardware should be set up such that we sink current when the LED is
+    // turned on, hence the 8mA configuration choice.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as Consumer Infrared inputs or outputs.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! Consumer Infrared pins.  This function provides the proper configuration
+//! for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a CIR pin; it only
+//! configures a CIR pin for proper operation.  Note that a GPIOPinConfigure()
+//! function call is also required to properly configure a pin for the
+//! Consumer Infrared function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeCIR(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Retrieves the wake pins status.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//!
+//! This function returns the GPIO wake pin status values.  The returned
+//! bitfield shows low or high pin state via a value of 0 or 1.
+//!
+//! \note This function is not available on all devices, consult the data sheet
+//! to ensure that the device you are using supports GPIO wake pins.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return Returns the wake pin status.
+//
+//*****************************************************************************
+uint32_t
+GPIOPinWakeStatus(uint32_t ui32Port)
+{
+    return(ui32Port + GPIO_O_WAKESTAT);
+}
+
+//*****************************************************************************
+//
+//! Configures the alternate function of a GPIO pin.
+//!
+//! \param ui32PinConfig is the pin configuration value, specified as only one
+//! of the \b GPIO_P??_??? values.
+//!
+//! This function configures the pin mux that selects the peripheral function
+//! associated with a particular GPIO pin.  Only one peripheral function at a
+//! time can be associated with a GPIO pin, and each peripheral function should
+//! only be associated with a single GPIO pin at a time (despite the fact that
+//! many of them can be associated with more than one GPIO pin).  To fully
+//! configure a pin, a GPIOPinType*() function should also be called.
+//!
+//! The available mappings are supplied on a per-device basis in
+//! <tt>pin_map.h</tt>.  The \b PART_<partno> defines controls which set of
+//! defines are included so that they match the device that is being used.
+//! For example, \b PART_TM4C129XNCZAD must be defined in order to get the
+//! correct pin mappings for the TM4C129XNCZAD device.
+//!
+//! \note If the same signal is assigned to two different GPIO port
+//! pins, the signal is assigned to the port with the lowest letter and the
+//! assignment to the higher letter port is ignored.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinConfigure(uint32_t ui32PinConfig)
+{
+    uint32_t ui32Base, ui32Shift;
+
+    //
+    // Check the argument.
+    //
+    ASSERT(((ui32PinConfig >> 16) & 0xff) < 15);
+    ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0);
+
+    //
+    // Extract the base address index from the input value.
+    //
+    ui32Base = (ui32PinConfig >> 16) & 0xff;
+
+    //
+    // Get the base address of the GPIO module, selecting either the APB or the
+    // AHB aperture as appropriate.
+    //
+    if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ui32Base))
+    {
+        ui32Base = g_pui32GPIOBaseAddrs[(ui32Base << 1) + 1];
+    }
+    else
+    {
+        ui32Base = g_pui32GPIOBaseAddrs[ui32Base << 1];
+    }
+
+    //
+    // Extract the shift from the input value.
+    //
+    ui32Shift = (ui32PinConfig >> 8) & 0xff;
+
+    //
+    // Write the requested pin muxing value for this GPIO pin.
+    //
+    HWREG(ui32Base + GPIO_O_PCTL) = ((HWREG(ui32Base + GPIO_O_PCTL) &
+                                      ~(0xf << ui32Shift)) |
+                                     ((ui32PinConfig & 0xf) << ui32Shift));
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO pin as a trigger to start a DMA transaction.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! This function enables a GPIO pin to be used as a trigger to start a uDMA
+//! transaction.  Any GPIO pin can be configured to be an external trigger for
+//! the uDMA.  The GPIO pin still generates interrupts if the interrupt is
+//! enabled for the selected pin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Set the pin as a DMA trigger.
+    //
+    HWREG(ui32Port + GPIO_O_DMACTL) |= ui8Pins;
+}
+
+//*****************************************************************************
+//
+//! Disables a GPIO pin as a trigger to start a DMA transaction.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! This function disables a GPIO pin from being used as a trigger to start a
+//! uDMA transaction.  This function can be used to disable this feature if it
+//! was enabled via a call to GPIODMATriggerEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Set the pin as a DMA trigger.
+    //
+    HWREG(ui32Port + GPIO_O_DMACTL) &= (~ui8Pins);
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO pin as a trigger to start an ADC capture.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! This function enables a GPIO pin to be used as a trigger to start an ADC
+//! sequence.  Any GPIO pin can be configured to be an external trigger for an
+//! ADC sequence.  The GPIO pin still generates interrupts if the interrupt is
+//! enabled for the selected pin.  To enable the use of a GPIO pin to trigger
+//! the ADC module, the ADCSequenceConfigure() function must be called with the
+//! \b ADC_TRIGGER_EXTERNAL parameter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Set the pin as a DMA trigger.
+    //
+    HWREG(ui32Port + GPIO_O_ADCCTL) |= ui8Pins;
+}
+
+//*****************************************************************************
+//
+//! Disable a GPIO pin as a trigger to start an ADC capture.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! This function disables a GPIO pin to be used as a trigger to start an ADC
+//! sequence.  This function can be used to disable this feature if it was
+//! enabled via a call to GPIOADCTriggerEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Set the pin as a DMA trigger.
+    //
+    HWREG(ui32Port + GPIO_O_ADCCTL) &= (~ui8Pins);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/gpio.h b/bsp/tm4c129x/libraries/driverlib/gpio.h
new file mode 100644
index 0000000000..0cbeb987c0
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/gpio.h
@@ -0,0 +1,196 @@
+//*****************************************************************************
+//
+// gpio.h - Defines and Macros for GPIO API.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_GPIO_H__
+#define __DRIVERLIB_GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ui8Pins argument to
+// several of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0              0x00000001  // GPIO pin 0
+#define GPIO_PIN_1              0x00000002  // GPIO pin 1
+#define GPIO_PIN_2              0x00000004  // GPIO pin 2
+#define GPIO_PIN_3              0x00000008  // GPIO pin 3
+#define GPIO_PIN_4              0x00000010  // GPIO pin 4
+#define GPIO_PIN_5              0x00000020  // GPIO pin 5
+#define GPIO_PIN_6              0x00000040  // GPIO pin 6
+#define GPIO_PIN_7              0x00000080  // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output
+#define GPIO_DIR_MODE_HW        0x00000002  // Pin is a peripheral function
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter,
+// and returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge
+#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge
+#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges
+#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level
+#define GPIO_HIGH_LEVEL         0x00000006  // Interrupt on high level
+#define GPIO_DISCRETE_INT       0x00010000  // Interrupt for individual pins
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter,
+// and returned by GPIOPadConfigGet in the *pui32Strength parameter.
+//
+//*****************************************************************************
+#define GPIO_STRENGTH_2MA       0x00000001  // 2mA drive strength
+#define GPIO_STRENGTH_4MA       0x00000002  // 4mA drive strength
+#define GPIO_STRENGTH_6MA       0x00000065  // 6mA drive strength
+#define GPIO_STRENGTH_8MA       0x00000066  // 8mA drive strength
+#define GPIO_STRENGTH_8MA_SC    0x0000006E  // 8mA drive with slew rate control
+#define GPIO_STRENGTH_10MA      0x00000075  // 10mA drive strength
+#define GPIO_STRENGTH_12MA      0x00000077  // 12mA drive strength
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter,
+// and returned by GPIOPadConfigGet in the *pui32PadType parameter.
+//
+//*****************************************************************************
+#define GPIO_PIN_TYPE_STD       0x00000008  // Push-pull
+#define GPIO_PIN_TYPE_STD_WPU   0x0000000A  // Push-pull with weak pull-up
+#define GPIO_PIN_TYPE_STD_WPD   0x0000000C  // Push-pull with weak pull-down
+#define GPIO_PIN_TYPE_OD        0x00000009  // Open-drain
+#define GPIO_PIN_TYPE_ANALOG    0x00000000  // Analog comparator
+#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208  // Hibernate wake, high
+#define GPIO_PIN_TYPE_WAKE_LOW  0x00000108  // Hibernate wake, low
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
+// in the ui32IntFlags parameter.
+//
+//*****************************************************************************
+#define GPIO_INT_PIN_0          0x00000001
+#define GPIO_INT_PIN_1          0x00000002
+#define GPIO_INT_PIN_2          0x00000004
+#define GPIO_INT_PIN_3          0x00000008
+#define GPIO_INT_PIN_4          0x00000010
+#define GPIO_INT_PIN_5          0x00000020
+#define GPIO_INT_PIN_6          0x00000040
+#define GPIO_INT_PIN_7          0x00000080
+#define GPIO_INT_DMA            0x00000100
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins,
+                           uint32_t ui32PinIO);
+extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin);
+extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
+                           uint32_t ui32IntType);
+extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin);
+extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins,
+                             uint32_t ui32Strength, uint32_t ui32PadType);
+extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin,
+                             uint32_t *pui32Strength, uint32_t *pui32PadType);
+extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags);
+extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags);
+extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked);
+extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags);
+extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void));
+extern void GPIOIntUnregister(uint32_t ui32Port);
+extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val);
+extern void GPIOPinConfigure(uint32_t ui32PinConfig);
+extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins);
+extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port);
+extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_GPIO_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/hibernate.c b/bsp/tm4c129x/libraries/driverlib/hibernate.c
new file mode 100644
index 0000000000..3dd7ca2d72
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/hibernate.c
@@ -0,0 +1,2551 @@
+//*****************************************************************************
+//
+// hibernate.c - Driver for the Hibernation module
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup hibernate_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <time.h>
+#include "inc/hw_hibernate.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/hibernate.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// The delay in microseconds for writing to the Hibernation module registers.
+//
+//*****************************************************************************
+#define DELAY_USECS             95
+
+//*****************************************************************************
+//
+// The number of processor cycles to execute one pass of the delay loop.
+//
+//*****************************************************************************
+#define LOOP_CYCLES             3
+
+//*****************************************************************************
+//
+// A macro used to determine whether the target part supports Wake from IO
+// pins.
+//
+//*****************************************************************************
+#define HIBERNATE_WAKE_IO       CLASS_IS_TM4C129
+
+//*****************************************************************************
+//
+// A macro used to determine whether the target part supports Wake from IO
+// pins.
+//
+//*****************************************************************************
+#define HIBERNATE_CLOCK_OUTPUT  CLASS_IS_TM4C129
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Polls until the write complete (WRC) bit in the hibernate control register
+//! is set.
+//!
+//! \param None.
+//!
+//! The Hibernation module provides an indication when any write is completed.
+//! This mechanism is used to pace writes to the module.  This function merely
+//! polls this bit and returns as soon as it is set.  At this point, it is safe
+//! to perform another write to the module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+_HibernateWriteComplete(void)
+{
+    //
+    // Spin until the write complete bit is set.
+    //
+    while(!(HWREG(HIB_CTL) & HIB_CTL_WRC))
+    {
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables the Hibernation module for operation.
+//!
+//! \param ui32HibClk is the rate of the clock supplied to the Hibernation
+//! module.
+//!
+//! This function enables the Hibernation module for operation.  This function
+//! should be called before any of the Hibernation module features are used.
+//!
+//! The peripheral clock is the same as the processor clock.  This value is
+//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is
+//! constant and known (to save the code/execution overhead of a call to
+//! SysCtlClockGet()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateEnableExpClk(uint32_t ui32HibClk)
+{
+    //
+    // Turn on the clock enable bit.
+    //
+    HWREG(HIB_CTL) |= HIB_CTL_CLK32EN;
+
+    //
+    // Wait for write complete following register load (above).
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Disables the Hibernation module for operation.
+//!
+//! This function disables the Hibernation module.  After this function is
+//! called, none of the Hibernation module features are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDisable(void)
+{
+    //
+    // Turn off the clock enable bit.
+    //
+    HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Configures the clock input for the Hibernation module.
+//!
+//! \param ui32Config is one of the possible configuration options for the
+//! clock input listed below.
+//!
+//! This function is used to configure the clock input for the Hibernation
+//! module.  The \e ui32Config parameter can be one of the following values:
+//!
+//! - \b HIBERNATE_OSC_DISABLE specifies that the internal oscillator
+//! is powered off.  This option is used when an externally supplied oscillator
+//! is connected to the XOSC0 pin or to save power when the LFIOSC is used in
+//! devices that have an LFIOSC in the Hibernation module.
+//! - \b HIBERNATE_OSC_HIGHDRIVE specifies a higher drive strength when a 24-pF
+//! filter capacitor is used with a crystal.
+//! - \b HIBERNATE_OSC_LOWDRIVE specifies a lower drive strength when a 12-pF
+//! filter capacitor is used with a crystal.
+//!
+//! On some devices, there is an option to use an internal low frequency
+//! oscillator (LFIOSC) as the clock source for the Hibernation module.
+//! Because of the low accuracy of this oscillator, this option should not be
+//! used when the system requires a real time counter.  Adding the
+//! \b HIBERNATE_OSC_LFIOSC value enables the LFIOSC as the clock source to
+//! the Hibernation module.
+//!
+//! - \b HIBERNATE_OSC_LFIOSC enables the Hibernation module's internal low
+//! frequency oscillator as the clock to the Hibernation module.
+//!
+//! This \e ui32Config also configures how the clock output from the
+//! hibernation is used to clock other peripherals in the system.  The ALT
+//! clock settings allow clocking a subset of the peripherals.  See the
+//! hibernate section in the datasheet to determine which peripherals can be
+//! clocked by the ALT clock outputs from the Hibernation module.
+//! The \e ui32Config parameter can have any combination of the following
+//! values:
+//!
+//! - \b HIBERNATE_OUT_SYSCLK enables the hibernate clock output to the system
+//!      clock.
+//!
+//! The \b HIBERNATE_OSC_DISABLE option is used to disable and power down the
+//! internal oscillator if an external clock source or no clock source is used
+//! instead of a 32.768-kHz crystal.  In the case where an external crystal is
+//! used, either the \b HIBERNATE_OSC_HIGHDRIVE or \b HIBERNATE_OSC_LOWDRIVE is
+//! used.  These settings optimizes the oscillator drive strength to match the
+//! size of the filter capacitor that is used with the external crystal
+//! circuit.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateClockConfig(uint32_t ui32Config)
+{
+    uint32_t ui32HIBCtl;
+
+    ASSERT((ui32Config & ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE |
+                           HIBERNATE_OSC_DISABLE)) == 0);
+
+    ui32HIBCtl = HWREG(HIB_CTL);
+
+    //
+    // Clear the current configuration bits.
+    //
+    ui32HIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE |
+                    HIBERNATE_OSC_LFIOSC | HIBERNATE_OSC_DISABLE);
+
+    //
+    // Set the new configuration bits.
+    //
+    ui32HIBCtl |= ui32Config & (HIBERNATE_OSC_HIGHDRIVE |
+                                HIBERNATE_OSC_LOWDRIVE |
+                                HIBERNATE_OSC_LFIOSC |
+                                HIBERNATE_OSC_DISABLE);
+
+    //
+    // Must be sure that the 32KHz clock is enabled if the hibernate is about
+    // to switch to it.
+    //
+    if(ui32Config & HIBERNATE_OSC_LFIOSC)
+    {
+        ui32HIBCtl |= HIB_CTL_CLK32EN;
+    }
+
+    //
+    // Set the hibernation clocking configuration.
+    //
+    HWREG(HIB_CTL) = ui32HIBCtl;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Write the output clock configuration for devices that support
+    // controlling the output clocks from the hibernate module.
+    //
+    if(HIBERNATE_CLOCK_OUTPUT)
+    {
+        HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK |
+                                      HIBERNATE_OUT_ALT1CLK);
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables the RTC feature of the Hibernation module.
+//!
+//! This function enables the RTC in the Hibernation module.  The RTC can be
+//! used to wake the processor from hibernation at a certain time, or to
+//! generate interrupts at certain times.  This function must be called before
+//! using any of the RTC features of the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCEnable(void)
+{
+    //
+    // Turn on the RTC enable bit.
+    //
+    HWREG(HIB_CTL) |= HIB_CTL_RTCEN;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Disables the RTC feature of the Hibernation module.
+//!
+//! This function disables the RTC in the Hibernation module.  After calling
+//! this function, the RTC features of the Hibernation module are not
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCDisable(void)
+{
+    //
+    // Turn off the RTC enable bit.
+    //
+    HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Forces the Hibernation module to initiate a check of the battery voltage.
+//!
+//! This function forces the Hibernation module to initiate a check of the
+//! battery voltage immediately rather than waiting for the next check interval
+//! to pass.  After calling this function, the application should call the
+//! HibernateBatCheckDone() function and wait for the function to return a zero
+//! value before calling the HibernateIntStatus() to check if the return code
+//! has the \b HIBERNATE_INT_LOW_BAT set.  If \b HIBERNATE_INT_LOW_BAT is set,
+//! the battery level is low.  The application can also enable the
+//! \b HIBERNATE_INT_LOW_BAT interrupt and wait for an interrupt to indicate
+//! that the battery level is low.
+//!
+//! \note A hibernation request is held off if a battery check is in progress.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateBatCheckStart(void)
+{
+    //
+    // Initiated a forced battery check.
+    //
+    HWREG(HIB_CTL) |= HIB_CTL_BATCHK;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Determines whether or not a forced battery check has completed.
+//!
+//! This function determines whether the forced battery check initiated by a
+//! call to the HibernateBatCheckStart() function has completed.  This function
+//! returns a non-zero value until the battery level check has completed.  Once
+//! this function returns a value of zero, the Hibernation module has completed
+//! the battery check and the HibernateIntStatus() function can be used to
+//! check if the battery was low by checking if the value returned has the
+//! \b HIBERNATE_INT_LOW_BAT set.
+//!
+//! \return The value is zero when the battery level check has completed or
+//! non-zero if the check is still in process.
+//
+//*****************************************************************************
+uint32_t
+HibernateBatCheckDone(void)
+{
+    //
+    // Read the current state of the battery check.
+    //
+    return(HWREG(HIB_CTL) & HIB_CTL_BATCHK);
+}
+
+//*****************************************************************************
+//
+//! Configures the wake conditions for the Hibernation module.
+//!
+//! \param ui32WakeFlags specifies which conditions should be used for waking.
+//!
+//! This function enables the conditions under which the Hibernation module
+//! wakes.  The \e ui32WakeFlags parameter is the logical OR of any combination
+//! of the following:
+//!
+//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
+//! - \b HIBERNATE_WAKE_RTC - wake when the RTC match occurs.
+//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low-battery
+//! level being detected.
+//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted.
+//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted.
+//!
+//! If the \b HIBERNATE_WAKE_GPIO flag is set, then one of the GPIO
+//! configuration functions GPIOPinTypeWakeHigh() or GPIOPinTypeWakeLow() must
+//! be called to properly configure and enable a GPIO as a wake source for
+//! hibernation.
+//!
+//! \note The \b HIBERNATE_WAKE_GPIO and \b HIBERNATE_WAKE_RESET parameters are
+//! only available on some Tiva devices.
+//!
+//! \note On some Tiva devices a tamper event acts as a wake source for the
+//! Hibernation module.  Refer the function \b HibernateTamperEventsConfig() to
+//! wake from hibernation on a tamper event.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateWakeSet(uint32_t ui32WakeFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32WakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC |
+                               HIBERNATE_WAKE_GPIO | HIBERNATE_WAKE_RESET |
+                               HIBERNATE_WAKE_LOW_BAT)));
+
+    //
+    // Set the specified wake flags in the control register.
+    //
+    HWREG(HIB_CTL) = (ui32WakeFlags | (HWREG(HIB_CTL) &
+                                       ~(HIBERNATE_WAKE_PIN |
+                                         HIBERNATE_WAKE_RTC |
+                                         HIBERNATE_WAKE_LOW_BAT)));
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Write the hibernate IO register if requested.
+    //
+    if(HIBERNATE_WAKE_IO)
+    {
+        //
+        // If the reset or GPIOs are begin used as a wake source then the
+        // the VDD3ON needs to be set to allow the pads to remained
+        // powered.
+        //
+        if((ui32WakeFlags & (HIBERNATE_WAKE_RESET | HIBERNATE_WAKE_GPIO)) &&
+           ((HWREG(HIB_CTL) & HIB_CTL_VDD3ON) == 0))
+        {
+            //
+            // Make sure that VDD3ON mode is enabled so that the pads can
+            // retain their state.
+            //
+            HWREG(HIB_CTL) |= HIB_CTL_VDD3ON;
+
+            //
+            // Wait for write completion
+            //
+            _HibernateWriteComplete();
+        }
+
+        //
+        // Set the requested flags.
+        //
+        HWREG(HIB_IO) = (ui32WakeFlags >> 16) | HIB_IO_WUUNLK;
+
+        //
+        // Spin until the write complete bit is set.
+        //
+        while((HWREG(HIB_IO) & HIB_IO_IOWRC) == 0)
+        {
+        }
+
+        //
+        // Clear the write unlock bit.
+        //
+        HWREG(HIB_IO) &= ~HIB_IO_WUUNLK;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the currently configured wake conditions for the Hibernation module.
+//!
+//! This function returns the flags representing the wake configuration for the
+//! Hibernation module.  The return value is a combination of the following
+//! flags:
+//!
+//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted
+//! - \b HIBERNATE_WAKE_RTC - wake when the RTC matches occurs
+//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernation due to a low-battery
+//! level being detected
+//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted
+//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted
+//!
+//! \note The \b HIBERNATE_WAKE_LOW_BAT, \b HIBERNATE_WAKE_GPIO, and
+//! \b HIBERNATE_WAKE_RESET parameters are only available on some Tiva devices.
+//!
+//! \note On some Tiva devices a tamper event acts as a wake source for the
+//! Hibernation module.  Refer the function \b HibernateTamperEventsConfig() to
+//! wake from hibernation on a tamper event.
+//!
+//! \return Returns flags indicating the configured wake conditions.
+//
+//*****************************************************************************
+uint32_t
+HibernateWakeGet(void)
+{
+    uint32_t ui32Ctrl;
+
+    //
+    // Read the wake bits from the control register and return those bits to
+    // the caller.
+    //
+    if(HIBERNATE_WAKE_IO)
+    {
+        ui32Ctrl = HWREG(HIB_CTL);
+        return((ui32Ctrl & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC |
+                            HIBERNATE_WAKE_LOW_BAT)) |
+               ((HWREG(HIB_IO) << 16) & (HIBERNATE_WAKE_RESET |
+                                         HIBERNATE_WAKE_GPIO)));
+    }
+    else
+    {
+        return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC |
+                                 HIBERNATE_WAKE_LOW_BAT));
+    }
+}
+
+//*****************************************************************************
+//
+//! Configures the low-battery detection.
+//!
+//! \param ui32LowBatFlags specifies behavior of low-battery detection.
+//!
+//! This function enables the low-battery detection and whether hibernation is
+//! allowed if a low battery is detected.  If low-battery detection is enabled,
+//! then a low-battery condition is indicated in the raw interrupt status
+//! register, which can be enabled to trigger an interrupt.  Optionally,
+//! hibernation can be aborted if a low battery condition is detected.
+//!
+//! The \e ui32LowBatFlags parameter is one of the following values:
+//!
+//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low-battery condition
+//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low-battery condition and abort
+//!   hibernation if low-battery is detected
+//!
+//! The other setting in the \e ui32LowBatFlags allows the caller to set one of
+//! the following voltage level trigger values :
+//!
+//! - \b HIBERNATE_LOW_BAT_1_9V - voltage low level is 1.9 V
+//! - \b HIBERNATE_LOW_BAT_2_1V - voltage low level is 2.1 V
+//! - \b HIBERNATE_LOW_BAT_2_3V - voltage low level is 2.3 V
+//! - \b HIBERNATE_LOW_BAT_2_5V - voltage low level is 2.5 V
+//!
+//! \b Example: Abort hibernate if the voltage level is below 2.1 V.
+//!
+//! \verbatim
+//! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateLowBatSet(uint32_t ui32LowBatFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32LowBatFlags &
+             ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)));
+
+    //
+    // Set the low-battery detect and abort bits in the control register,
+    // according to the parameter.
+    //
+    HWREG(HIB_CTL) = (ui32LowBatFlags |
+                      (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M |
+                                          HIBERNATE_LOW_BAT_ABORT)));
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Gets the currently configured low-battery detection behavior.
+//!
+//! This function returns a value representing the currently configured low
+//! battery detection behavior.
+//!
+//! The return value is a combination of the values described in the
+//! HibernateLowBatSet() function.
+//!
+//! \return Returns a value indicating the configured low-battery detection.
+//
+//*****************************************************************************
+uint32_t
+HibernateLowBatGet(void)
+{
+    //
+    // Read the supported low bat bits from the control register and return
+    // those bits to the caller.
+    //
+    return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the real time clock (RTC) counter.
+//!
+//! \param ui32RTCValue is the new value for the RTC.
+//!
+//! This function sets the value of the RTC.  The RTC counter contains the
+//! count in seconds when a 32.768kHz clock source is in use.  The RTC must be
+//! enabled by calling HibernateRTCEnable() before calling this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCSet(uint32_t ui32RTCValue)
+{
+    //
+    // Load register requires unlock.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Write the new RTC value to the RTC load register.
+    //
+    HWREG(HIB_RTCLD) = ui32RTCValue;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Unlock.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the real time clock (RTC) counter.
+//!
+//! This function gets the value of the RTC and returns it to the caller.
+//!
+//! \return Returns the value of the RTC counter in seconds.
+//
+//*****************************************************************************
+uint32_t
+HibernateRTCGet(void)
+{
+    //
+    // Return the value of the RTC counter register to the caller.
+    //
+    return(HWREG(HIB_RTCC));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC match register.
+//!
+//! \param ui32Match is the index of the match register.
+//! \param ui32Value is the value for the match register.
+//!
+//! This function sets a match register for the RTC.  The Hibernation
+//! module can be configured to wake from hibernation, and/or generate an
+//! interrupt when the value of the RTC counter is the same as the match
+//! register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value)
+{
+    ASSERT(ui32Match == 0);
+
+    //
+    // Write the new match value to the match register.
+    //
+    HWREG(HIB_RTCM0) = ui32Value;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the requested RTC match register.
+//!
+//! \param ui32Match is the index of the match register.
+//!
+//! This function gets the value of the match register for the RTC.  The only
+//! value that can be used with the \e ui32Match parameter is zero, other
+//! values are reserved for future use.
+//!
+//! \return Returns the value of the requested match register.
+//
+//*****************************************************************************
+uint32_t
+HibernateRTCMatchGet(uint32_t ui32Match)
+{
+    ASSERT(ui32Match == 0);
+
+    //
+    // Return the value of the match register to the caller.
+    //
+    return(HWREG(HIB_RTCM0));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC sub second match register.
+//!
+//! \param ui32Match is the index of the match register.
+//! \param ui32Value is the value for the sub second match register.
+//!
+//! This function sets the sub second match register for the RTC in 1/32768
+//! of a second increments.  The Hibernation module can be configured to wake
+//! from hibernation, and/or generate an interrupt when the value of the RTC
+//! counter is the same as the match combined with the sub second match
+//! register.  The only value that can be used with the \e ui32Match
+//! parameter is zero, other values are reserved for future use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value)
+{
+    ASSERT(ui32Match == 0);
+
+    //
+    // Write the new sub second match value to the sub second match register.
+    //
+    HWREG(HIB_RTCSS) = ui32Value << HIB_RTCSS_RTCSSM_S;
+
+    //
+    // Wait for write complete to be signaled on later devices.
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Returns the value of the requested RTC sub second match register.
+//!
+//! \param ui32Match is the index of the match register.
+//!
+//! This function returns the current value of the sub second match register
+//! for the RTC.  The value returned is in 1/32768 second increments.  The only
+//! value that can be used with the \e ui32Match parameter is zero, other
+//! values are reserved for future use.
+//!
+//! \return Returns the value of the requested sub section match register.
+//
+//*****************************************************************************
+uint32_t
+HibernateRTCSSMatchGet(uint32_t ui32Match)
+{
+    ASSERT(ui32Match == 0);
+
+    //
+    // Read the current second RTC count.
+    //
+    return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S);
+}
+
+//*****************************************************************************
+//
+//! Returns the current value of the RTC sub second count.
+//!
+//! This function returns the current value of the sub second count for the RTC
+//! in 1/32768 of a second increments.  The only value that can be used with
+//! the \e ui32Match parameter is zero, other values are reserved for future
+//! use.
+//!
+//! \return The current RTC sub second count in 1/32768 seconds.
+//
+//*****************************************************************************
+uint32_t
+HibernateRTCSSGet(void)
+{
+    //
+    // Read the current second RTC count.
+    //
+    return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M);
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC pre-divider trim register.
+//!
+//! \param ui32Trim is the new value for the pre-divider trim register.
+//!
+//! This function sets the value of the pre-divider trim register.  The input
+//! time source is divided by the pre-divider to achieve a one-second clock
+//! rate.  Once every 64 seconds, the value of the pre-divider trim register is
+//! applied to the pre-divider to allow fine-tuning of the RTC rate, in order
+//! to make corrections to the rate.  The software application can make
+//! adjustments to the pre-divider trim register to account for variations in
+//! the accuracy of the input time source.  The nominal value is 0x7FFF, and it
+//! can be adjusted up or down in order to fine-tune the RTC rate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCTrimSet(uint32_t ui32Trim)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Trim < 0x10000);
+
+    //
+    // Write the new trim value to the trim register.
+    //
+    HWREG(HIB_RTCT) = ui32Trim;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC pre-divider trim register.
+//!
+//! This function gets the value of the pre-divider trim register.  This
+//! function can be used to get the current value of the trim register prior
+//! to making an adjustment by using the HibernateRTCTrimSet() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+HibernateRTCTrimGet(void)
+{
+    //
+    // Return the value of the trim register to the caller.
+    //
+    return(HWREG(HIB_RTCT));
+}
+
+//*****************************************************************************
+//
+//! Stores data in the battery-backed memory of the Hibernation module.
+//!
+//! \param pui32Data points to the data that the caller wants to store in the
+//! memory of the Hibernation module.
+//! \param ui32Count is the count of 32-bit words to store.
+//!
+//! Stores a set of data in the Hibernation module battery-backed memory.
+//! This memory is preserved when the power to the processor is turned off
+//! and can be used to store application state information that is needed when
+//! the processor wakes.  Up to 16 32-bit words can be stored in the
+//! battery-backed memory.  The data can be restored by calling the
+//! HibernateDataGet() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count)
+{
+    uint32_t ui32Idx;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Count <= 64);
+    ASSERT(pui32Data != 0);
+
+    //
+    // Loop through all the words to be stored, storing one at a time.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
+    {
+        //
+        // Write a word to the battery-backed storage area.
+        //
+        HWREG(HIB_DATA + (ui32Idx * 4)) = pui32Data[ui32Idx];
+
+        //
+        // Wait for write completion
+        //
+        _HibernateWriteComplete();
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads a set of data from the battery-backed memory of the Hibernation
+//! module.
+//!
+//! \param pui32Data points to a location where the data that is read from the
+//! Hibernation module is stored.
+//! \param ui32Count is the count of 32-bit words to read.
+//!
+//! This function retrieves a set of data from the Hibernation module
+//! battery-backed memory that was previously stored with the
+//! HibernateDataSet() function.  The caller must ensure that \e pui32Data
+//! points to a large enough memory block to hold all the data that is read
+//! from the battery-backed memory.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count)
+{
+    uint32_t ui32Idx;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Count <= 64);
+    ASSERT(pui32Data != 0);
+
+    //
+    // Loop through all the words to be restored, reading one at a time.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
+    {
+        //
+        // Read a word from the battery-backed storage area.  No delay is
+        // required between reads.
+        //
+        pui32Data[ui32Idx] = HWREG(HIB_DATA + (ui32Idx * 4));
+    }
+}
+
+//*****************************************************************************
+//
+//! Requests hibernation mode.
+//!
+//! This function requests the Hibernation module to disable the external
+//! regulator, thus removing power from the processor and all peripherals.  The
+//! Hibernation module remains powered from the battery or auxiliary power
+//! supply.
+//!
+//! The Hibernation module re-enables the external regulator when one of
+//! the configured wake conditions occurs (such as RTC match or external
+//! \b WAKE pin).  When the power is restored, the processor goes through a
+//! power-on reset although the Hibernation module is not reset.  The processor
+//! can retrieve saved state information with the HibernateDataGet() function.
+//! Prior to calling the function to request hibernation mode, the conditions
+//! for waking must have already been set by using the HibernateWakeSet()
+//! function.
+//!
+//! Note that this function may return because some time may elapse before the
+//! power is actually removed, or it may not be removed at all.  For this
+//! reason, the processor continues to execute instructions for some time,
+//! and the caller should be prepared for this function to return.  There are
+//! various reasons why the power may not be removed.  For example, if the
+//! HibernateLowBatSet() function was used to configure an abort if low
+//! battery is detected, then the power is not removed if the battery
+//! voltage is too low.  There may be other reasons related to the external
+//! circuit design, that a request for hibernation may not actually occur.
+//!
+//! For all these reasons, the caller must be prepared for this function to
+//! return.  The simplest way to handle it is to just enter an infinite loop
+//! and wait for the power to be removed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRequest(void)
+{
+    //
+    // Set the bit in the control register to cut main power to the processor.
+    //
+    HWREG(HIB_CTL) |= HIB_CTL_HIBREQ;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts for the Hibernation module.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupts to be enabled.
+//!
+//! This function enables the specified interrupt sources from the Hibernation
+//! module.
+//!
+//! The \e ui32IntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b HIBERNATE_INT_WR_COMPLETE - write complete interrupt
+//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt
+//! - \b HIBERNATE_INT_LOW_BAT - low-battery interrupt
+//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt
+//! - \b HIBERNATE_INT_VDDFAIL - supply failure interrupt.
+//! - \b HIBERNATE_INT_RESET_WAKE - wake from reset pin interrupt
+//! - \b HIBERNATE_INT_GPIO_WAKE - wake from GPIO pin or reset pin interrupt.
+//!
+//! \note The \b HIBERNATE_INT_RESET_WAKE, \b HIBERNATE_INT_GPIO_WAKE, and
+//! \b HIBERNATE_INT_VDDFAIL settings are not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you are using to
+//! determine if these interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntEnable(uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+                              HIBERNATE_INT_VDDFAIL |
+                              HIBERNATE_INT_RESET_WAKE |
+                              HIBERNATE_INT_GPIO_WAKE |
+                              HIBERNATE_INT_RTC_MATCH_0 |
+                              HIBERNATE_INT_WR_COMPLETE)));
+
+    //
+    // Set the specified interrupt mask bits.
+    //
+    HWREG(HIB_IM) |= ui32IntFlags;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the Hibernation module.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupts to be disabled.
+//!
+//! This function disables the specified interrupt sources from the
+//! Hibernation module.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to the HibernateIntEnable() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntDisable(uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+                              HIBERNATE_INT_VDDFAIL |
+                              HIBERNATE_INT_RESET_WAKE |
+                              HIBERNATE_INT_GPIO_WAKE |
+                              HIBERNATE_INT_RTC_MATCH_0 |
+                              HIBERNATE_INT_WR_COMPLETE)));
+
+    //
+    // Clear the specified interrupt mask bits.
+    //
+    HWREG(HIB_IM) &= ~ui32IntFlags;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Returns the hibernate module interrupt number.
+//!
+//! This function returns the interrupt number for the hibernate module.
+//!
+//! \return Returns a hibernate interrupt number or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_HibernateIntNumberGet(void)
+{
+    uint32_t ui32Int;
+
+    //
+    // Find the valid interrupt number for the hibernate module.
+    //
+    if(CLASS_IS_TM4C129)
+    {
+        ui32Int = INT_HIBERNATE_TM4C129;
+    }
+    else
+    {
+        ui32Int = INT_HIBERNATE_TM4C123;
+    }
+
+    return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the Hibernation module interrupt.
+//!
+//! \param pfnHandler points to the function to be called when a hibernation
+//! interrupt occurs.
+//!
+//! This function registers the interrupt handler in the system interrupt
+//! controller.  The interrupt is enabled at the global level, but individual
+//! interrupt sources must still be enabled with a call to
+//! HibernateIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntRegister(void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Get the interrupt number for the Hibernate module.
+    //
+    ui32Int = _HibernateIntNumberGet();
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the hibernate module interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the Hibernation module interrupt.
+//!
+//! This function unregisters the interrupt handler in the system interrupt
+//! controller.  The interrupt is disabled at the global level, and the
+//! interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntUnregister(void)
+{
+    uint32_t ui32Int;
+
+    //
+    // Get the interrupt number for the Hibernate module.
+    //
+    ui32Int = _HibernateIntNumberGet();
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the hibernate interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status of the Hibernation module.
+//!
+//! \param bMasked is false to retrieve the raw interrupt status, and true to
+//! retrieve the masked interrupt status.
+//!
+//! This function returns the interrupt status of the Hibernation module.  The
+//! caller can use this function to determine the cause of a hibernation
+//! interrupt.  Either the masked or raw interrupt status can be returned.
+//!
+//! \note A wake from reset pin also signals a wake from GPIO pin with the
+//! value returned being HIBERNATE_INT_GPIO_WAKE | HIBERNATE_INT_RESET_WAKE.
+//! Hence a wake from reset pin should take priority over wake from GPIO pin.
+//!
+//! \return Returns the interrupt status as a bit field with the values as
+//! described in the HibernateIntEnable() function.
+//
+//*****************************************************************************
+uint32_t
+HibernateIntStatus(bool bMasked)
+{
+    //
+    // Read and return the Hibernation module raw or masked interrupt status.
+    //
+    if(bMasked == true)
+    {
+        return(HWREG(HIB_MIS));
+    }
+    else
+    {
+        return(HWREG(HIB_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears pending interrupts from the Hibernation module.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupts to be cleared.
+//!
+//! This function clears the specified interrupt sources.  This function must
+//! be called within the interrupt handler or else the handler is called again
+//! upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to the HibernateIntEnable() function.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntClear(uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+                              HIBERNATE_INT_VDDFAIL |
+                              HIBERNATE_INT_RESET_WAKE |
+                              HIBERNATE_INT_GPIO_WAKE |
+                              HIBERNATE_INT_RTC_MATCH_0 |
+                              HIBERNATE_INT_WR_COMPLETE)));
+
+    //
+    // Write the specified interrupt bits into the interrupt clear register.
+    //
+    HWREG(HIB_IC) |= ui32IntFlags;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Checks to see if the Hibernation module is already powered up.
+//!
+//! This function queries the control register to determine if the module is
+//! already active.  This function can be called at a power-on reset to help
+//! determine if the reset is due to a wake from hibernation or a cold start.
+//! If the Hibernation module is already active, then it does not need to be
+//! re-enabled, and its status can be queried immediately.
+//!
+//! The software application should also use the HibernateIntStatus() function
+//! to read the raw interrupt status to determine the cause of the wake.  The
+//! HibernateDataGet() function can be used to restore state.  These
+//! combinations of functions can be used by the software to determine if the
+//! processor is waking from hibernation and the appropriate action to take as
+//! a result.
+//!
+//! \return Returns \b true if the module is already active, and \b false if
+//! not.
+//
+//*****************************************************************************
+uint32_t
+HibernateIsActive(void)
+{
+    //
+    // Read the control register, and return true if the module is enabled.
+    //
+    return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0);
+}
+
+//*****************************************************************************
+//
+//! Enables GPIO retention after wake from hibernation.
+//!
+//! This function enables the GPIO pin state to be maintained during
+//! hibernation and remain active even when waking from hibernation.  The GPIO
+//! module itself is reset upon entering hibernation and no longer controls the
+//! output pins.  To maintain the current output level after waking from
+//! hibernation, the GPIO module must be reconfigured and then the
+//! HibernateGPIORetentionDisable() function must be called to return control
+//! of the GPIO pin to the GPIO module.
+//!
+//! \note The hibernation GPIO retention setting is not available on all
+//! Tiva devices.  Please consult the data sheet to determine if the
+//! device you are using supports this feature in the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateGPIORetentionEnable(void)
+{
+    //
+    // Enable power to the pads and enable GPIO retention during hibernate.
+    //
+    HWREG(HIB_CTL) |= HIB_CTL_VDD3ON | HIB_CTL_RETCLR;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Disables GPIO retention after wake from hibernation.
+//!
+//! This function disables the retention of the GPIO pin state during
+//! hibernation and allows the GPIO pins to be controlled by the system.  If
+//! the HibernateGPIORetentionEnable() function is called before entering
+//! hibernation, this function must be called after returning from hibernation
+//! to allow the GPIO pins to be controlled by GPIO module.
+//!
+//! \note The hibernate GPIO retention setting is not available on all
+//! Tiva devices.  Please consult the data sheet to determine if the
+//! device you are using supports this feature in the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateGPIORetentionDisable(void)
+{
+    //
+    // Reset the GPIO configuration after waking from hibernate and disable
+    // the hibernate power to the pads.
+    //
+    HWREG(HIB_CTL) &= ~(HIB_CTL_RETCLR | HIB_CTL_VDD3ON);
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting for GPIO retention.
+//!
+//! This function returns the current setting for GPIO retention in the
+//! hibernate module.
+//!
+//! \note The hibernation GPIO retention setting is not available on all
+//! Tiva devices.  Please consult the data sheet to determine if the
+//! device you are using supports this feature in the Hibernation module.
+//!
+//! \return Returns true if GPIO retention is enabled and false if GPIO
+//! retention is disabled.
+//
+//*****************************************************************************
+bool
+HibernateGPIORetentionGet(void)
+{
+    //
+    // Read the current GPIO retention configuration.
+    //
+    if((HWREG(HIB_CTL) & (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) ==
+       (HIB_CTL_RETCLR | HIB_CTL_VDD3ON))
+    {
+        return(true);
+    }
+    return(false);
+}
+
+//*****************************************************************************
+//
+//! Configures the Hibernation module's internal counter mode.
+//!
+//! \param ui32Config is the configuration to use for the Hibernation module's
+//! counter.
+//!
+//! This function configures the Hibernate module's counter mode to operate
+//! as a standard RTC counter or to operate in a calendar mode.  The
+//! \e ui32Config parameter is used to provide the configuration for
+//! the counter and must include only one of the following values:
+//!
+//! - \b HIBERNATE_COUNTER_24HR specifies 24-hour calendar mode.
+//! - \b HIBERNATE_COUNTER_12HR specifies 12-hour AM/PM calendar mode.
+//! - \b HIBERNATE_COUNTER_RTC specifies RTC counter mode.
+//!
+//! The HibernateCalendar functions can only be called when either
+//! \b HIBERNATE_COUNTER_24HR or \b HIBERNATE_COUNTER_12HR is specified.
+//!
+//! \b Example: Configure hibernate counter to 24-hour calendar mode.
+//!
+//! \verbatim
+//!
+//! //
+//! // Configure the hibernate module counter to 24-hour calendar mode.
+//! //
+//! HibernateCounterMode(HIBERNATE_COUNTER_24HR);
+//!
+//! \endverbatim
+//!
+//! \note The hibernate calendar mode is not available on all Tiva
+//! devices.  Please consult the data sheet to determine if the device you are
+//! using supports this feature in the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateCounterMode(uint32_t ui32Config)
+{
+    //
+    // Set the requested configuration.
+    //
+    HWREG(HIB_CALCTL) = ui32Config;
+
+    //
+    // Wait for write completion
+    //
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+// Internal function to parse the time structure to set the calendar fields.
+//
+//*****************************************************************************
+static void
+_HibernateCalendarSet(uint32_t ui32Reg, struct tm *psTime)
+{
+    uint32_t ui32Time, ui32Date;
+
+    ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN);
+
+    //
+    // Minutes and seconds are consistent in all modes.
+    //
+    ui32Time = (((psTime->tm_min << HIB_CALLD0_MIN_S) & HIB_CALLD0_MIN_M) |
+                ((psTime->tm_sec << HIB_CALLD0_SEC_S) & HIB_CALLD0_SEC_M));
+
+    //
+    // 24 Hour time is used directly for Calendar set.
+    //
+    if(HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24)
+    {
+        ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S);
+
+        //
+        // for Calendar match, if it is every hour, AMPM bit should be clear
+        //
+        if((ui32Reg == HIB_CALM0) && (psTime->tm_hour == 0xFF) )
+        {
+            //
+            // clear AMPM bit
+            //
+            ui32Time &= ~HIB_CAL0_AMPM;
+        }
+    }
+    else
+    {
+        //
+        // In AM/PM time hours have to be capped at 12.
+        // If the hours are all 1s, it means the match for the hour is
+        // always true.  We need to set 1F in the hw field.
+        //
+        if(psTime->tm_hour == 0xFF)
+        {
+            //
+            // Match every hour.
+            //
+            ui32Time |= HIB_CALLD0_HR_M;
+        }
+        else if(psTime->tm_hour >= 12)
+        {
+            //
+            // Need to set the PM bit if it is noon or later.
+            //
+            ui32Time |= (((psTime->tm_hour - 12) << HIB_CALLD0_HR_S) |
+                         HIB_CAL0_AMPM);
+        }
+        else
+        {
+            //
+            // All other times are normal and AM.
+            //
+            ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S);
+        }
+    }
+
+    //
+    // Create the date in the correct register format.
+    //
+    if(ui32Reg == HIB_CAL0)
+    {
+        //
+        // We must add 1 to the month, since the time structure lists
+        // the month from 0 to 11 and the HIB lists it from 1 to 12.
+        //
+        ui32Date = ((psTime->tm_mday << HIB_CAL1_DOM_S) |
+                    ((psTime->tm_mon + 1) << HIB_CAL1_MON_S) |
+                    (psTime->tm_wday << HIB_CAL1_DOW_S) |
+                    ((psTime->tm_year - 100) << HIB_CAL1_YEAR_S));
+    }
+    else
+    {
+        //
+        // Wday, month and year are not included in the match
+        // Functionality.
+        //
+        if(psTime->tm_mday == 0xFF)
+        {
+            //
+            // program 0 to match every day
+            //
+            ui32Date = 0 << HIB_CAL1_DOM_M;
+        }
+        else
+        {
+            ui32Date = (psTime->tm_mday << HIB_CAL1_DOM_S);
+        }
+    }
+
+    //
+    // Load register requires unlock.
+    //
+    if(ui32Reg == HIB_CAL0)
+    {
+        //
+        // Unlock the hibernate counter load registers.
+        //
+        HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+        _HibernateWriteComplete();
+    }
+
+    //
+    // Set the requested time and date.
+    //
+    if(ui32Reg == HIB_CAL0)
+    {
+        HWREG(HIB_CALLD0) = ui32Time;
+        _HibernateWriteComplete();
+        HWREG(HIB_CALLD1) = ui32Date;
+        _HibernateWriteComplete();
+    }
+    else
+    {
+        HWREG(HIB_CALM0) = ui32Time;
+        _HibernateWriteComplete();
+        HWREG(HIB_CALM1) = ui32Date;
+        _HibernateWriteComplete();
+    }
+
+    //
+    // Load register requires unlock.
+    //
+    if(ui32Reg == HIB_CAL0)
+    {
+        //
+        // Lock the hibernate counter load registers.
+        //
+        HWREG(HIB_LOCK) = 0;
+        _HibernateWriteComplete();
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the Hibernation module's date and time in calendar mode.
+//!
+//! \param psTime is the structure that holds the information for the current
+//! date and time.
+//!
+//! This function uses the \e psTime parameter to set the current date and
+//! time when the Hibernation module is in calendar mode.  Regardless of
+//! whether 24-hour or 12-hour mode is in use, the \e psTime structure uses a
+//! 24-hour representation of the time.  This function can only be called when
+//! the hibernate counter is configured in calendar mode using the
+//! HibernateCounterMode() function with one of the calendar modes.
+//!
+//! \note The hibernate calendar mode is not available on all Tiva
+//! devices.  Please consult the data sheet to determine if the device you are
+//! using supports this feature in the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateCalendarSet(struct tm *psTime)
+{
+    //
+    // Load a new date/time.
+    //
+    _HibernateCalendarSet(HIB_CAL0, psTime);
+}
+
+//*****************************************************************************
+//
+//! Returns the Hibernation module's date and time in calendar mode.
+//!
+//! \param psTime is the structure that is filled with the current date and
+//! time.
+//!
+//! This function returns the current date and time in the structure provided
+//! by the \e psTime parameter.  Regardless of the calendar mode, the
+//! \e psTime parameter uses a 24-hour representation of the time.  This
+//! function can only be called when the Hibernation module is configured in
+//! calendar mode using the HibernateCounterMode() function with one of the
+//! calendar modes.
+//!
+//! The only case where this function fails and returns a non-zero value is
+//! when the function detects that the counter is passing from the last second
+//! of the day to the first second of the next day.  This exception must be
+//! handled in the application by waiting at least one second before calling
+//! again to get the updated calendar information.
+//!
+//! \note The hibernate calendar mode is not available on all Tiva
+//! devices.  Please consult the data sheet to determine if the device you are
+//! using supports this feature in the Hibernation module.
+//!
+//! \return Returns zero if the time and date were read successfully and
+//! returns a non-zero value if the \e psTime structure was not updated.
+//
+//*****************************************************************************
+int
+HibernateCalendarGet(struct tm *psTime)
+{
+    uint32_t ui32Date, ui32Time;
+
+    ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN);
+
+    //
+    // Wait for the value to be valid, this should never be more than a few
+    // loops and should never hang.
+    //
+    do
+    {
+        ui32Date = HWREG(HIB_CAL1);
+    }
+    while((ui32Date & HIB_CAL1_VALID) == 0);
+
+    //
+    // Wait for the value to be valid, this should never be more than a few
+    // loops and should never hang.
+    //
+    do
+    {
+        ui32Time = HWREG(HIB_CAL0);
+    }
+    while((ui32Time & HIB_CAL0_VALID) == 0);
+
+    //
+    // The date changed after reading the time so fail this call and let the
+    // application call again since it knows how int32_t to wait until another
+    // second passes.
+    //
+    if(ui32Date != HWREG(HIB_CAL1))
+    {
+        return(-1);
+    }
+
+    //
+    // Populate the date and time fields in the psTime structure.
+    // We must subtract 1 from the month, since the time structure lists
+    // the month from 0 to 11 and the HIB lists it from 1 to 12.
+    //
+    psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S;
+    psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S;
+    psTime->tm_mon = (((ui32Date & HIB_CAL1_MON_M) >> HIB_CAL1_MON_S) - 1);
+    psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S;
+    psTime->tm_wday = (ui32Date & HIB_CAL1_DOW_M) >> HIB_CAL1_DOW_S;
+    psTime->tm_year = ((ui32Date & HIB_CAL1_YEAR_M) >> HIB_CAL1_YEAR_S) + 100;
+    psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S;
+
+    //
+    // Fix up the hour in the non-24-hour mode and the time is in PM.
+    //
+    if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) &&
+       (ui32Time & HIB_CAL0_AMPM))
+    {
+        psTime->tm_hour += 12;
+    }
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the Hibernation module's date and time match value in calendar mode.
+//!
+//! \param ui32Index indicates which match register to access.
+//! \param psTime is the structure that holds all of the information to set
+//! the current date and time match values.
+//!
+//! This function uses the \e psTime parameter to set the current date and time
+//! match value in the Hibernation module's calendar.  Regardless of the mode,
+//! the \e psTime parameter uses a 24-hour clock representation of time.
+//! This function can only be called when the Hibernation module is
+//! configured in calendar mode using the HibernateCounterMode()
+//! function.  The \e ui32Index value is reserved for future use and should
+//! always be zero.
+//! Calendar match can be enabled for every day, every hour, every minute or
+//! every second, setting any of these fields to 0xFF causes a match for
+//! that field.  For example, setting the day of month field to 0xFF
+//! results in a calendar match daily at the same time.
+//!
+//! \note The hibernate calendar mode is not available on all Tiva
+//! devices.  Please consult the data sheet to determine if the device you are
+//! using supports this feature in the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime)
+{
+    //
+    // Set the Match value.
+    //
+    _HibernateCalendarSet(HIB_CALM0, psTime);
+}
+
+//*****************************************************************************
+//
+//! Returns the Hibernation module's date and time match value in calendar
+//! mode.
+//!
+//! \param ui32Index indicates which match register to access.
+//! \param psTime is the structure to fill with the current date and time
+//! match value.
+//!
+//! This function returns the current date and time match value in the
+//! structure provided by the \e psTime parameter.  Regardless of the mode, the
+//! \e psTime parameter uses a 24-hour clock representation of time.
+//! This function can only be called when the Hibernation module is configured
+//! in calendar mode using the HibernateCounterMode() function.
+//! The \e ui32Index value is reserved for future use and should always be
+//! zero.
+//!
+//! \note The hibernate calendar mode is not available on all Tiva
+//! devices.  Please consult the data sheet to determine if the device you are
+//! using supports this feature in the Hibernation module.
+//!
+//! \return Returns zero if the time and date match value were read
+//! successfully and returns a non-zero value if the psTime structure was not
+//! updated.
+//
+//*****************************************************************************
+void
+HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime)
+{
+    uint32_t ui32Date, ui32Time;
+
+    ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN);
+
+    //
+    // Get the date field.
+    //
+    ui32Date = HWREG(HIB_CALM1);
+
+    //
+    // Get the time field.
+    //
+    ui32Time = HWREG(HIB_CALM0);
+
+    //
+    // Populate the date and time fields in the psTime structure.
+    //
+    if((ui32Time & HIB_CAL0_MIN_M) == HIB_CAL0_MIN_M)
+    {
+        //
+        // Match every minute
+        //
+        psTime->tm_min = 0xFF;
+    }
+    else
+    {
+        psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S;
+    }
+
+    if((ui32Time & HIB_CAL0_SEC_M) == HIB_CAL0_SEC_M)
+    {
+        //
+        // Match every second
+        //
+        psTime->tm_sec = 0xFF;
+    }
+    else
+    {
+        psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S;
+    }
+
+    if((ui32Time & HIB_CAL0_HR_M) == HIB_CAL0_HR_M)
+    {
+        //
+        // Match every hour
+        //
+        psTime->tm_hour = 0xFF;
+    }
+    else
+    {
+        psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S;
+    }
+
+    if((ui32Date & HIB_CAL1_DOM_M) == 0)
+    {
+        //
+        // Match every day
+        //
+        psTime->tm_mday = 0xFF;
+    }
+    else
+    {
+        psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S;
+    }
+
+    //
+    // Fix up the hour in the non-24-hour mode and the time is in PM.
+    //
+    if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) &&
+       (ui32Time & HIB_CAL0_AMPM))
+    {
+        psTime->tm_hour += 12;
+    }
+}
+
+//*****************************************************************************
+//
+//! Configures the tamper feature event response.
+//!
+//! \param ui32Config specifies the configuration options for tamper events.
+//!
+//! This function is used to configure the event response options for the
+//! tamper feature.  The \e ui32Config parameter provides a combination of the
+//! \b HIBERNATE_TAMPER_EVENTS_* features to set these options.  The
+//! application should choose from the following set of defines to determine
+//! what happens to the system when a tamper event occurs:
+//!
+//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM all of the Hibernation
+//! module's battery-backed RAM is cleared due to a tamper event
+//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM the upper half of the
+//! Hibernation module's battery-backed RAM is cleared due to a tamper event
+//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM the lower half of the
+//! Hibernation module's battery-backed RAM is cleared due to a tamper event
+//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_NO_HIB_MEM the Hibernation module's
+//! battery-backed RAM is not changed due to a tamper event
+//! - \b HIBERNATE_TAMPER_EVENTS_HIB_WAKE a tamper event wakes the MCU from
+//! hibernation
+//! - \b HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE a tamper event does not wake the
+//! MCU from hibernation
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperEventsConfig(uint32_t ui32Config)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Mask out the on-event configuration options.
+    //
+    ui32Temp = (HWREG(HIB_TPCTL) & ~HIB_TPCTL_MEMCLR_M);
+
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Set the on-event configuration.
+    //
+    HWREG(HIB_TPCTL) = (ui32Temp | ui32Config);
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Enables the tamper feature.
+//!
+//! This function is used to enable the tamper feature functionality.  This
+//! function should only be called after the global configuration is set with
+//! a call to HibernateTamperEventsConfig() and the tamper inputs have been
+//! configured with a call to HibernateTamperIOEnable().
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperEnable(void)
+{
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Set the tamper enable bit.
+    //
+    HWREG(HIB_TPCTL) |= HIB_TPCTL_TPEN;
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Disables the tamper feature.
+//!
+//! This function is used to disable the tamper feature functionality.  All
+//! other configuration settings are left unmodified, allowing a call to
+//! HibernateTamperEnable() to quickly enable the tamper feature with its
+//! previous configuration.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperDisable(void)
+{
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Clear the tamper enable bit.
+    //
+    HWREG(HIB_TPCTL) &= ~HIB_TPCTL_TPEN;
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Configures an input to the tamper feature.
+//!
+//! \param ui32Input is the tamper input to configure.
+//! \param ui32Config holds the configuration options for a given input to the
+//! tamper feature.
+//!
+//! This function is used to configure an input to the tamper feature.  The
+//! \e ui32Input parameter specifies the tamper signal to configure and has a
+//! valid range of 0-3.  The \e ui32Config parameter provides the set of tamper
+//! features in the \b HIBERNATE_TAMPER_IO_* values.  The values that are valid
+//! in the \e ui32Config parameter are:
+//!
+//! - \b HIBERNATE_TAMPER_IO_MATCH_SHORT configures the trigger to match after
+//! 2 hibernation clocks
+//! - \b HIBERNATE_TAMPER_IO_MATCH_LONG configures the trigger to match after
+//! 3071 hibernation clocks
+//! - \b HIBERNATE_TAMPER_IO_WPU_ENABLED turns on an internal weak pull up
+//! - \b HIBERNATE_TAMPER_IO_WPU_DISABLED turns off an internal weak pull up
+//! - \b HIBERNATE_TAMPER_IO_TRIGGER_HIGH sets the tamper event to active high
+//! - \b HIBERNATE_TAMPER_IO_TRIGGER_LOW sets the tamper event to active low
+//!
+//! \note None of the GPIO API functions are needed to configure the tamper
+//! pins.  The tamper pins configured by using this function overrides any
+//! configuration by GPIO APIs.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config)
+{
+    uint32_t ui32Temp, ui32Mask;
+
+    //
+    // Verify parameters.
+    //
+    ASSERT(ui32Input < 4);
+
+    //
+    // Read the current tamper I/O configuration.
+    //
+    ui32Temp = HWREG(HIB_TPIO);
+
+    //
+    // Mask out configuration options for the requested input.
+    //
+    ui32Mask = (ui32Temp & (~((HIB_TPIO_GFLTR0 | HIB_TPIO_PUEN0 |
+                               HIB_TPIO_LEV0 | HIB_TPIO_EN0) <<
+                              (ui32Input << 3))));
+
+    //
+    // Set tamper I/O configuration for the requested input.
+    //
+    ui32Temp |= (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3)));
+
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Write to the register.
+    //
+    HWREG(HIB_TPIO) = ui32Temp;
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Disables an input to the tamper feature.
+//!
+//! \param ui32Input is the tamper input to disable.
+//!
+//! This function is used to disable an input to the tamper feature.  The
+//! \e ui32Input parameter specifies the tamper signal to disable and has a
+//! valid range of 0-3.
+//!
+//! \note None of the GPIO API functions are needed to configure the tamper
+//! pins.  The tamper pins configured by using this function overrides any
+//! configuration by GPIO APIs.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperIODisable(uint32_t ui32Input)
+{
+    //
+    // Verify parameters.
+    //
+    ASSERT(ui32Input < 4);
+
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Clear the I/O enable bit.
+    //
+    HWREG(HIB_TPIO) &= ((~HIB_TPIO_EN0) << (ui32Input << 3));
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Clears the tamper feature events.
+//!
+//! This function is used to clear all tamper events.  This function always
+//! clears the tamper feature event state indicator along with all tamper log
+//! entries.  Logged event data should be retrieved with
+//! HibernateTamperEventsGet() prior to requesting a event clear.
+//!
+//! HibernateTamperEventsClear() should be called prior to clearing the system
+//! control NMI that resulted from the tamper event.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperEventsClear(void)
+{
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Set the tamper event clear bit.
+    //
+    HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR;
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Clears the tamper feature events without Unlock and Lock.
+//!
+//! This function is used to clear all tamper events without unlock/locking
+//! the tamper control registers, so API HibernateTamperUnLock() should be
+//! called before this function, and API HibernateTamperLock() should be
+//! called after to ensure that tamper control registers are locked.
+//!
+//! This function doesn't block until the write is complete.
+//! Therefore, care must be taken to ensure the next immediate write will
+//! occure only after the write complete bit is set.
+//!
+//! This function is used to implement a software workaround in NMI interrupt
+//! handler to fix an issue when a new tamper event could be missed during
+//! the clear of current tamper event.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperEventsClearNoLock(void)
+{
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Set the tamper event clear bit.
+    //
+    HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR;
+
+}
+
+//*****************************************************************************
+//
+//! Unlock temper registers.
+//!
+//! This function is used to unlock the temper control registers.  This
+//! function should be only used before calling API
+//! HibernateTamperEventsClearNoLock().
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperUnLock(void)
+{
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Lock temper registers.
+//!
+//! This function is used to lock the temper control registers.  This
+//! function should be used after calling API
+//! HibernateTamperEventsClearNoLock().
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperLock(void)
+{
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Returns the current tamper feature status.
+//!
+//! This function is used to return the tamper feature status.  This function
+//! returns one of the values from this group of options:
+//!
+//! - \b HIBERNATE_TAMPER_STATUS_INACTIVE indicates tamper detection is
+//! disabled
+//! - \b HIBERNATE_TAMPER_STATUS_ACTIVE indicates tamper detection is enabled
+//! and ready
+//! - \b HIBERNATE_TAMPER_STATUS_EVENT indicates tamper event was detected
+//!
+//! In addition, one of the values is included from this group:
+//!
+//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE indicates the external
+//! oscillator is not active
+//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE indicates the external
+//! oscillator is active
+//!
+//! And one of the values is included from this group:
+//!
+//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED indicates the external
+//! oscillator signal has transitioned from valid to invalid
+//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID indicates the external
+//! oscillator is providing a valid signal
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return Returns a combination of the \b HIBERNATE_TAMPER_STATUS_* values.
+//
+//*****************************************************************************
+uint32_t
+HibernateTamperStatusGet(void)
+{
+    uint32_t ui32Status, ui32Reg;
+
+    //
+    // Retrieve the raw register value.
+    //
+    ui32Reg = HWREG(HIB_TPSTAT);
+
+    //
+    // Setup the oscillator status indicators.
+    //
+    ui32Status = (ui32Reg & (HIB_TPSTAT_XOSCST | HIB_TPSTAT_XOSCFAIL));
+    ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCST) ? 0 :
+                   HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE);
+    ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCFAIL) ? 0 :
+                   HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID);
+
+    //
+    // Retrieve the tamper status indicators.
+    //
+    ui32Status |= ((ui32Reg & HIB_TPSTAT_STATE_M) << 3);
+
+    //
+    // The HW shows "disabled" with a zero value, use bit[0] as a flag
+    // for this purpose.
+    //
+    if((ui32Reg & HIB_TPSTAT_STATE_M) == 0)
+    {
+        ui32Status |= HIBERNATE_TAMPER_STATUS_INACTIVE;
+    }
+
+    //
+    // Return the API status flags.
+    //
+    return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Returns a tamper log entry.
+//!
+//! \param ui32Index is the index of the log entry to return.
+//! \param pui32RTC is a pointer to the memory to store the logged RTC data.
+//! \param pui32Event is a pointer to the memory to store the logged tamper
+//! event.
+//!
+//! This function is used to return a tamper log entry from the hibernate
+//! feature.  The \e ui32Index specifies the zero-based index of the log entry
+//! to query and has a valid range of 0-3.
+//!
+//! When this function returns, the \e pui32RTC value contains the time value
+//! and \e pui32Event parameter contains the tamper I/O event that triggered
+//! this log.
+//!
+//! The format of the returned \e pui32RTC data is dependent on the
+//! configuration of the RTC within the Hibernation module.  If the RTC is
+//! configured for counter mode, the returned data contains counted seconds
+//! from the RTC enable.  If the RTC is configured for calendar mode, the data
+//! returned is formatted as follows:
+//!
+//! \verbatim
+//! +----------------------------------------------------------------------+
+//! |  31:26  |  25:22  |     21:17      |  16:12  |   11:6    |    5:0    |
+//! +----------------------------------------------------------------------+
+//! |  year   |  month  |  day of month  |  hours  |  minutes  |  seconds  |
+//! +----------------------------------------------------------------------+
+//! \endverbatim
+//!
+//! The data returned in the \e pui32Events parameter could include any of the
+//! following flags:
+//!
+//! - \b HIBERNATE_TAMPER_EVENT_0 indicates a tamper event was triggered on I/O
+//! signal 0
+//! - \b HIBERNATE_TAMPER_EVENT_1 indicates a tamper event was triggered on I/O
+//! signal 1
+//! - \b HIBERNATE_TAMPER_EVENT_2 indicates a tamper event was triggered on I/O
+//! signal 2
+//! - \b HIBERNATE_TAMPER_EVENT_3 indicates a tamper event was triggered on I/O
+//! signal 3
+//! - \b HIBERNATE_TAMPER_EVENT_XOSC indicates an external oscillator failure
+//! triggered the tamper event
+//!
+//! \note Tamper event logs are not consumed when read and remain available
+//! until cleared.  Events are only logged if unused log space is available.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return Returns \b true if the \e pui32RTC and \e pui32Events were updated
+//! successfully and returns \b false if the values were not updated.
+//
+//*****************************************************************************
+bool
+HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC,
+                         uint32_t *pui32Event)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Verify parameters.
+    //
+    ASSERT(pui32RTC);
+    ASSERT(pui32Event);
+    ASSERT(ui32Index < 4);
+
+    //
+    // Retrieve the event log data for the requested index if available.
+    //
+    ui32Reg = HWREG(HIB_TPLOG0 + ((ui32Index << 3) + 4));
+    if(ui32Reg == 0)
+    {
+        //
+        // No event data is available for this index.
+        //
+        return(false);
+    }
+
+    //
+    // Store the event data in the provided location.
+    //
+    *pui32Event = ui32Reg;
+
+    //
+    // Retrieve the calendar information.
+    //
+    *pui32RTC = HWREG(HIB_TPLOG0 + (ui32Index << 3));
+
+    //
+    // Convert the hour to 24hr mode if the Calendar is enabled
+    // and in 24hr mode.
+    //
+    if((HWREG(HIB_CALCTL) & (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) ==
+       (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24))
+    {
+        if(HWREG(HIB_CAL0) & HIB_CAL0_AMPM)
+        {
+            //
+            // Add 12 hour since it is PM
+            //
+            ui32Reg = ((*pui32RTC & 0X0001f000) + (12<<12)) & 0X0001f000;
+            *pui32RTC &= ~0X0001f000;
+            *pui32RTC |= ui32Reg;
+        }
+    }
+
+    //
+    // Return success.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Attempts to recover the external oscillator.
+//!
+//! This function is used to attempt to recover the external oscillator after a
+//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status is reported.  This
+//! function must not be called if the external oscillator is not used as
+//! the hibernation clock input.  HibernateTamperExtOscValid() should be called
+//! before calling this function.
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateTamperExtOscRecover(void)
+{
+    //
+    // Unlock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
+    _HibernateWriteComplete();
+
+    //
+    // Set the XOSCFAIL clear bit.
+    //
+    HWREG(HIB_TPSTAT) |= HIB_TPSTAT_XOSCFAIL;
+
+    //
+    // Wait for write completion.
+    //
+    _HibernateWriteComplete();
+
+    //
+    // Lock the tamper registers.
+    //
+    HWREG(HIB_LOCK) = 0;
+    _HibernateWriteComplete();
+}
+
+//*****************************************************************************
+//
+//! Reports if the external oscillator signal is active and stable.
+//!
+//! This function should be used to verify the external oscillator is active
+//! and valid before attempting to recover from a
+//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status by calling
+//! HibernateTamperExtOscRecover().
+//!
+//! \note The hibernate tamper feature is not available on all Tiva
+//! devices.  Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return Returns \b true if the external oscillator is both active and
+//! stable, otherwise a \b false indicator is returned.
+//
+//*****************************************************************************
+bool
+HibernateTamperExtOscValid(void)
+{
+    if(HibernateTamperStatusGet() & (HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE |
+                                     HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID))
+    {
+        return(true);
+    }
+
+    return(false);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/hibernate.h b/bsp/tm4c129x/libraries/driverlib/hibernate.h
new file mode 100644
index 0000000000..7c3b449a75
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/hibernate.h
@@ -0,0 +1,257 @@
+//*****************************************************************************
+//
+// hibernate.h - API definition for the Hibernation module.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_HIBERNATE_H__
+#define __DRIVERLIB_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macros need to configure wake events for HibernateWakeSet()
+//
+//*****************************************************************************
+#define HIBERNATE_WAKE_PIN      0x00000010
+#define HIBERNATE_WAKE_RTC      0x00000008
+#define HIBERNATE_WAKE_LOW_BAT  0x00000200
+#define HIBERNATE_WAKE_GPIO     0x00000010
+#define HIBERNATE_WAKE_RESET    0x00100010
+#define HIBERNATE_WAKE_TAMPER   0x08000010
+
+//*****************************************************************************
+//
+// Macros needed to configure low battery detect for HibernateLowBatSet()
+//
+//*****************************************************************************
+#define HIBERNATE_LOW_BAT_DETECT                                              \
+                                0x00000020
+#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
+#define HIBERNATE_LOW_BAT_1_9V  0x00000000
+#define HIBERNATE_LOW_BAT_2_1V  0x00002000
+#define HIBERNATE_LOW_BAT_2_3V  0x00004000
+#define HIBERNATE_LOW_BAT_2_5V  0x00006000
+
+//*****************************************************************************
+//
+// Macros defining interrupt source bits for the interrupt functions.
+//
+//*****************************************************************************
+#define HIBERNATE_INT_VDDFAIL   0x00000080
+#define HIBERNATE_INT_RESET_WAKE                                              \
+                                0x00000040
+#define HIBERNATE_INT_GPIO_WAKE 0x00000020
+#define HIBERNATE_INT_WR_COMPLETE                                             \
+                                0x00000010
+#define HIBERNATE_INT_PIN_WAKE  0x00000008
+#define HIBERNATE_INT_LOW_BAT   0x00000004
+#define HIBERNATE_INT_RTC_MATCH_0                                             \
+                                0x00000001
+
+//*****************************************************************************
+//
+// Macros defining oscillator configuration options for the
+// HibernateClockConfig() function.
+//
+//*****************************************************************************
+#define HIBERNATE_OSC_LFIOSC    0x00080000
+#define HIBERNATE_OSC_LOWDRIVE  0x00000000
+#define HIBERNATE_OSC_HIGHDRIVE 0x00020000
+#define HIBERNATE_OSC_DISABLE   0x00010000
+#define HIBERNATE_OUT_WRSTALL   0x20000000
+#define HIBERNATE_OUT_SYSCLK    0x00000001
+#define HIBERNATE_OUT_ALT1CLK   0x00000002
+
+//*****************************************************************************
+//
+// The following defines are used with the HibernateCounterMode() API.
+//
+//*****************************************************************************
+#define HIBERNATE_COUNTER_RTC   0x00000000
+#define HIBERNATE_COUNTER_12HR  0x00000001
+#define HIBERNATE_COUNTER_24HR  0x00000005
+
+//*****************************************************************************
+//
+// Tamper event configuration options used with HibernateTamperEventsConfig().
+//
+//*****************************************************************************
+#define HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE                                   \
+                                0x00000000
+#define HIBERNATE_TAMPER_EVENTS_HIB_WAKE                                      \
+                                0x00000800
+#define HIBERNATE_TAMPER_EVENTS_NO_ERASE_HIB_MEM                              \
+                                0x00000000
+#define HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM                             \
+                                0x00000100
+#define HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM                            \
+                                0x00000200
+#define HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM                             \
+                                0x00000300
+
+//*****************************************************************************
+//
+// Status flags returned by the HibernateTamperStatus() function.
+//
+//*****************************************************************************
+#define HIBERNATE_TAMPER_STATUS_INACTIVE                                      \
+                                0x00000010
+#define HIBERNATE_TAMPER_STATUS_ACTIVE                                        \
+                                0x00000020
+#define HIBERNATE_TAMPER_STATUS_EVENT                                         \
+                                0x00000040
+#define HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE                                \
+                                0x00000008
+#define HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE                              \
+                                0x00000002
+#define HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID                                 \
+                                0x00000004
+#define HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED                                \
+                                0x00000001
+
+//*****************************************************************************
+//
+// Configuration options used with HibernateTamperIOEnable().
+//
+//*****************************************************************************
+#define HIBERNATE_TAMPER_IO_TRIGGER_LOW                                       \
+                                0x00000000
+#define HIBERNATE_TAMPER_IO_TRIGGER_HIGH                                      \
+                                0x00000002
+#define HIBERNATE_TAMPER_IO_WPU_DISABLED                                      \
+                                0x00000000
+#define HIBERNATE_TAMPER_IO_WPU_ENABLED                                       \
+                                0x00000004
+#define HIBERNATE_TAMPER_IO_MATCH_SHORT                                       \
+                                0x00000000
+#define HIBERNATE_TAMPER_IO_MATCH_LONG                                        \
+                                0x00000008
+
+//*****************************************************************************
+//
+// Tamper log event flags.
+//
+//*****************************************************************************
+#define HIBERNATE_TAMPER_EVENT_0                                              \
+                                0x00000001
+#define HIBERNATE_TAMPER_EVENT_1                                              \
+                                0x00000002
+#define HIBERNATE_TAMPER_EVENT_2                                              \
+                                0x00000004
+#define HIBERNATE_TAMPER_EVENT_3                                              \
+                                0x00000008
+#define HIBERNATE_TAMPER_EVENT_EXT_OSC                                        \
+                                0x00010000
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void HibernateGPIORetentionEnable(void);
+extern void HibernateGPIORetentionDisable(void);
+extern bool HibernateGPIORetentionGet(void);
+extern void HibernateEnableExpClk(uint32_t ui32HibClk);
+extern void HibernateDisable(void);
+extern void HibernateRTCEnable(void);
+extern void HibernateRTCDisable(void);
+extern void HibernateWakeSet(uint32_t ui32WakeFlags);
+extern uint32_t HibernateWakeGet(void);
+extern void HibernateLowBatSet(uint32_t ui32LowBatFlags);
+extern uint32_t HibernateLowBatGet(void);
+extern void HibernateRTCSet(uint32_t ui32RTCValue);
+extern uint32_t HibernateRTCGet(void);
+extern void HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value);
+extern uint32_t HibernateRTCMatchGet(uint32_t ui32Match);
+extern void HibernateRTCTrimSet(uint32_t ui32Trim);
+extern uint32_t HibernateRTCTrimGet(void);
+extern void HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count);
+extern void HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count);
+extern void HibernateRequest(void);
+extern void HibernateIntEnable(uint32_t ui32IntFlags);
+extern void HibernateIntDisable(uint32_t ui32IntFlags);
+extern void HibernateIntRegister(void (*pfnHandler)(void));
+extern void HibernateIntUnregister(void);
+extern uint32_t HibernateIntStatus(bool bMasked);
+extern void HibernateIntClear(uint32_t ui32IntFlags);
+extern uint32_t HibernateIsActive(void);
+extern void HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value);
+extern uint32_t HibernateRTCSSMatchGet(uint32_t ui32Match);
+extern uint32_t HibernateRTCSSGet(void);
+extern void HibernateClockConfig(uint32_t ui32Config);
+extern void HibernateBatCheckStart(void);
+extern uint32_t HibernateBatCheckDone(void);
+extern void HibernateCounterMode(uint32_t ui32Config);
+extern void HibernateCalendarSet(struct tm *psTime);
+extern int HibernateCalendarGet(struct tm *psTime);
+extern void HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime);
+extern void HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime);
+extern void HibernateTamperEnable(void);
+extern void HibernateTamperEventsConfig(uint32_t ui32Config);
+extern bool HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC,
+                                       uint32_t *pui32Event);
+extern void HibernateTamperEventsClear(void);
+extern void HibernateTamperEventsClearNoLock(void);
+extern void HibernateTamperUnLock(void);
+extern void HibernateTamperLock(void);
+extern void HibernateTamperDisable(void);
+extern void HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config);
+extern void HibernateTamperIODisable(uint32_t ui32Input);
+extern uint32_t HibernateTamperStatusGet(void);
+extern void HibernateTamperExtOscRecover(void);
+extern bool HibernateTamperExtOscValid(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __DRIVERLIB_HIBERNATE_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/i2c.c b/bsp/tm4c129x/libraries/driverlib/i2c.c
new file mode 100644
index 0000000000..05ebede8dc
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/i2c.c
@@ -0,0 +1,2143 @@
+//*****************************************************************************
+//
+// i2c.c - Driver for Inter-IC (I2C) bus block.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup i2c_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_i2c.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/i2c.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// A mapping of I2C base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32I2CIntMap[][2] =
+{
+    { I2C0_BASE, INT_I2C0_TM4C123 },
+    { I2C1_BASE, INT_I2C1_TM4C123 },
+    { I2C2_BASE, INT_I2C2_TM4C123 },
+    { I2C3_BASE, INT_I2C3_TM4C123 },
+    { I2C4_BASE, INT_I2C4_TM4C123 },
+    { I2C5_BASE, INT_I2C5_TM4C123 },
+};
+
+static const int_fast8_t g_i8I2CIntMapRows =
+    sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]);
+
+static const uint32_t g_ppui32I2CIntMapSnowflake[][2] =
+{
+    { I2C0_BASE, INT_I2C0_TM4C129 },
+    { I2C1_BASE, INT_I2C1_TM4C129 },
+    { I2C2_BASE, INT_I2C2_TM4C129 },
+    { I2C3_BASE, INT_I2C3_TM4C129 },
+    { I2C4_BASE, INT_I2C4_TM4C129 },
+    { I2C5_BASE, INT_I2C5_TM4C129 },
+    { I2C6_BASE, INT_I2C6_TM4C129 },
+    { I2C7_BASE, INT_I2C7_TM4C129 },
+    { I2C8_BASE, INT_I2C8_TM4C129 },
+    { I2C9_BASE, INT_I2C9_TM4C129 },
+};
+static const int_fast8_t g_i8I2CIntMapSnowflakeRows =
+    sizeof(g_ppui32I2CIntMapSnowflake) / sizeof(g_ppui32I2CIntMapSnowflake[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks an I2C base address.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function determines if a I2C module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_I2CBaseValid(uint32_t ui32Base)
+{
+    return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) ||
+           (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) ||
+           (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) ||
+           (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) ||
+           (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the I2C interrupt number.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! Given a I2C base address, this function returns the corresponding
+//! interrupt number.
+//!
+//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid.
+//
+//*****************************************************************************
+static uint32_t
+_I2CIntNumberGet(uint32_t ui32Base)
+{
+    int_fast8_t i8Idx, i8Rows;
+    const uint32_t (*ppui32I2CIntMap)[2];
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    ppui32I2CIntMap = g_ppui32I2CIntMap;
+    i8Rows = g_i8I2CIntMapRows;
+
+    if(CLASS_IS_TM4C129)
+    {
+        ppui32I2CIntMap = g_ppui32I2CIntMapSnowflake;
+        i8Rows = g_i8I2CIntMapSnowflakeRows;
+    }
+
+    //
+    // Loop through the table that maps I2C base addresses to interrupt
+    // numbers.
+    //
+    for(i8Idx = 0; i8Idx < i8Rows; i8Idx++)
+    {
+        //
+        // See if this base address matches.
+        //
+        if(ppui32I2CIntMap[i8Idx][0] == ui32Base)
+        {
+            //
+            // Return the corresponding interrupt number.
+            //
+            return(ppui32I2CIntMap[i8Idx][1]);
+        }
+    }
+
+    //
+    // The base address could not be found, so return an error.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Initializes the I2C Master block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32I2CClk is the rate of the clock supplied to the I2C module.
+//! \param bFast set up for fast data transfers.
+//!
+//! This function initializes operation of the I2C Master block by configuring
+//! the bus speed for the master and enabling the I2C Master block.
+//!
+//! If the parameter \e bFast is \b true, then the master block is set up to
+//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at
+//! 100 Kbps.  If Fast Mode Plus (1 Mbps) is desired, software should manually
+//! write the I2CMTPR after calling this function.  For High Speed (3.4 Mbps)
+//! mode, a specific command is used to switch to the faster clocks after the
+//! initial communication with the slave is done at either 100 Kbps or
+//! 400 Kbps.
+//!
+//! The peripheral clock is the same as the processor clock.  This value is
+//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
+//! constant and known (to save the code/execution overhead of a call to
+//! SysCtlClockGet()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
+                    bool bFast)
+{
+    uint32_t ui32SCLFreq;
+    uint32_t ui32TPR;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Must enable the device before doing anything else.
+    //
+    I2CMasterEnable(ui32Base);
+
+    //
+    // Get the desired SCL speed.
+    //
+    if(bFast == true)
+    {
+        ui32SCLFreq = 400000;
+    }
+    else
+    {
+        ui32SCLFreq = 100000;
+    }
+
+    //
+    // Compute the clock divider that achieves the fastest speed less than or
+    // equal to the desired speed.  The numerator is biased to favor a larger
+    // clock divider so that the resulting clock is always less than or equal
+    // to the desired clock, never greater.
+    //
+    ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) /
+               (2 * 10 * ui32SCLFreq)) - 1;
+    HWREG(ui32Base + I2C_O_MTPR) = ui32TPR;
+
+    //
+    // Check to see if this I2C peripheral is High-Speed enabled.  If yes, also
+    // choose the fastest speed that is less than or equal to 3.4 Mbps.
+    //
+    if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS)
+    {
+        ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) /
+                   (2 * 3 * 3400000)) - 1;
+        HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR;
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes the I2C Slave block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8SlaveAddr 7-bit slave address
+//!
+//! This function initializes operation of the I2C Slave block by configuring
+//! the slave address and enabling the I2C Slave block.
+//!
+//! The parameter \e ui8SlaveAddr is the value that is compared against the
+//! slave address sent by an I2C master.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+    ASSERT(!(ui8SlaveAddr & 0x80));
+
+    //
+    // Must enable the device before doing anything else.
+    //
+    I2CSlaveEnable(ui32Base);
+
+    //
+    // Set up the slave address.
+    //
+    HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
+}
+
+//*****************************************************************************
+//
+//! Sets the I2C slave address.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8AddrNum determines which slave address is set.
+//! \param ui8SlaveAddr is the 7-bit slave address
+//!
+//! This function writes the specified slave address.  The \e ui32AddrNum field
+//! dictates which slave address is configured.  For example, a value of 0
+//! configures the primary address and a value of 1 configures the secondary.
+//!
+//! \note Not all Tiva devices support a secondary address.  Please
+//! consult the device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+    ASSERT(!(ui8AddrNum > 1));
+    ASSERT(!(ui8SlaveAddr & 0x80));
+
+    //
+    // Determine which slave address is being set.
+    //
+    switch(ui8AddrNum)
+    {
+        //
+        // Set up the primary slave address.
+        //
+        case 0:
+        {
+            HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
+            break;
+        }
+
+        //
+        // Set up and enable the secondary slave address.
+        //
+        case 1:
+        {
+            HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr;
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function enables operation of the I2C Master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the master block.
+    //
+    HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This fucntion enables operation of the I2C Slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the clock to the slave block.
+    //
+    HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE;
+
+    //
+    // Enable the slave.
+    //
+    HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C master block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function disables operation of the I2C master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable the master block.
+    //
+    HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE);
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C slave block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function disables operation of the I2C slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable the slave.
+    //
+    HWREG(ui32Base + I2C_O_SCSR) = 0;
+
+    //
+    // Disable the clock to the slave block.
+    //
+    HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the I2C module.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2C interrupt occurs.
+//!
+//! This function sets the handler to be called when an I2C interrupt occurs.
+//! This function enables the global interrupt in the interrupt controller;
+//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and
+//! I2CSlaveIntEnable().  If necessary, it is the interrupt handler's
+//! responsibility to clear the interrupt source via I2CMasterIntClear() and
+//! I2CSlaveIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Determine the interrupt number based on the I2C port.
+    //
+    ui32Int = _I2CIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the I2C interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the I2C module.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function clears the handler to be called when an I2C interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt r
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Determine the interrupt number based on the I2C port.
+    //
+    ui32Int = _I2CIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master interrupt.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function enables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the master interrupt.
+    //
+    HWREG(ui32Base + I2C_O_MIMR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated I2C Master interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt
+//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
+//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt
+//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt
+//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt
+//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt
+//! - \b I2C_MASTER_INT_START - Start Condition interrupt
+//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt
+//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt
+//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt
+//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt
+//! - \b I2C_MASTER_INT_DATA - Data interrupt
+//!
+//! \note Not all Tiva devices support all of the listed interrupt
+//! sources.  Please consult the device data sheet to determine if these
+//! features are supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the master interrupt.
+    //
+    HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave interrupt.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function enables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the slave interrupt.
+    //
+    HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated I2C Slave interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt
+//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
+//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt
+//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt
+//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt
+//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt
+//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
+//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
+//! - \b I2C_SLAVE_INT_DATA - Data interrupt
+//!
+//! \note Not all Tiva devices support the all of the listed interrupts.
+//! Please consult the device data sheet to determine if these features are
+//! supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the slave interrupt.
+    //
+    HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Master interrupt.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function disables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable the master interrupt.
+    //
+    HWREG(ui32Base + I2C_O_MIMR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//!        disabled.
+//!
+//! This function disables the indicated I2C Master interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CMasterIntEnableEx().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable the master interrupt.
+    //
+    HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Slave interrupt.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function disables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable the slave interrupt.
+    //
+    HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//!        disabled.
+//!
+//! This function disables the indicated I2C Slave interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable the slave interrupt.
+    //
+    HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Master interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+bool
+I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);
+    }
+    else
+    {
+        return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Master interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in I2CMasterIntEnableEx().
+//
+//*****************************************************************************
+uint32_t
+I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + I2C_O_MMIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + I2C_O_MRIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C Slave.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+bool
+I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false);
+    }
+    else
+    {
+        return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C Slave.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in I2CSlaveIntEnableEx().
+//
+//*****************************************************************************
+uint32_t
+I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + I2C_O_SMIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + I2C_O_SRIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! The I2C Master interrupt source is cleared, so that it no longer
+//! asserts.  This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntClear(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Clear the I2C master interrupt source.
+    //
+    HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;
+
+    //
+    // Workaround for I2C master interrupt clear errata for rev B Tiva
+    // devices.  For later devices, this write is ignored and therefore
+    // harmless (other than the slight performance hit).
+    //
+    HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2C Master interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep the interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CMasterIntEnableEx().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Clear the I2C master interrupt source.
+    //
+    HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
+//! This function must be called in the interrupt handler to keep the interrupt
+//! from being triggered again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClear(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Clear the I2C slave interrupt source.
+    //
+    HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2C Slave interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep the interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Clear the I2C slave interrupt source.
+    //
+    HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Sets the address that the I2C Master places on the bus.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8SlaveAddr 7-bit slave address
+//! \param bReceive flag indicating the type of communication with the slave
+//!
+//! This function configures the address that the I2C Master places on the
+//! bus when initiating a transaction.  When the \e bReceive parameter is set
+//! to \b true, the address indicates that the I2C Master is initiating a
+//! read from the slave; otherwise the address indicates that the I2C
+//! Master is initiating a write to the slave.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
+                      bool bReceive)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+    ASSERT(!(ui8SlaveAddr & 0x80));
+
+    //
+    // Set the address of the slave with which the master will communicate.
+    //
+    HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
+}
+
+//*****************************************************************************
+//
+//! Reads the state of the SDA and SCL pins.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function returns the state of the I2C bus by providing the real time
+//! values of the SDA and SCL pins.
+//!
+//! \note Not all Tiva devices support this function.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return Returns the state of the bus with SDA in bit position 1 and SCL in
+//! bit position 0.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterLineStateGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return the line state.
+    //
+    return(HWREG(ui32Base + I2C_O_MBMON));
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C Master is busy.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function returns an indication of whether or not the I2C Master is
+//! busy transmitting or receiving data.
+//!
+//! \return Returns \b true if the I2C Master is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+bool
+I2CMasterBusy(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return the busy status.
+    //
+    if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY)
+    {
+        return(true);
+    }
+    else
+    {
+        return(false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C bus is busy.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function returns an indication of whether or not the I2C bus is busy.
+//! This function can be used in a multi-master environment to determine if
+//! another master is currently using the bus.
+//!
+//! \return Returns \b true if the I2C bus is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+bool
+I2CMasterBusBusy(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return the bus busy status.
+    //
+    if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY)
+    {
+        return(true);
+    }
+    else
+    {
+        return(false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Controls the state of the I2C Master.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Cmd command to be issued to the I2C Master.
+//!
+//! This function is used to control the state of the Master send and
+//! receive operations.  The \e ui8Cmd parameter can be one of the following
+//! values:
+//!
+//! - \b I2C_MASTER_CMD_SINGLE_SEND
+//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
+//! - \b I2C_MASTER_CMD_BURST_SEND_START
+//! - \b I2C_MASTER_CMD_BURST_SEND_CONT
+//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
+//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
+//! - \b I2C_MASTER_CMD_QUICK_COMMAND
+//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND
+//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND
+//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP
+//!
+//! \note Not all Tiva devices have an I2C FIFO and support the FIFO
+//! commands.  Please consult the device data sheet to determine if this
+//! feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+    ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
+           (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
+           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) ||
+           (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) ||
+           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) ||
+           (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND));
+
+    //
+    // Send the command.
+    //
+    HWREG(ui32Base + I2C_O_MCS) = ui32Cmd;
+}
+
+//*****************************************************************************
+//
+//! Gets the error status of the I2C Master.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function is used to obtain the error status of the Master send
+//! and receive operations.
+//!
+//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
+//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
+//! \b I2C_MASTER_ERR_ARB_LOST.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterErr(uint32_t ui32Base)
+{
+    uint32_t ui32Err;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Get the raw error state
+    //
+    ui32Err = HWREG(ui32Base + I2C_O_MCS);
+
+    //
+    // If the I2C master is busy, then all the other bit are invalid, and
+    // don't have an error to report.
+    //
+    if(ui32Err & I2C_MCS_BUSY)
+    {
+        return(I2C_MASTER_ERR_NONE);
+    }
+
+    //
+    // Check for errors.
+    //
+    if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
+    {
+        return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
+    }
+    else
+    {
+        return(I2C_MASTER_ERR_NONE);
+    }
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Master.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8Data data to be transmitted from the I2C Master.
+//!
+//! This function places the supplied data into I2C Master Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Write the byte.
+    //
+    HWREG(ui32Base + I2C_O_MDR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Master.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function reads a byte of data from the I2C Master Data Register.
+//!
+//! \return Returns the byte received from by the I2C Master, cast as an
+//! uint32_t.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterDataGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Read a byte.
+    //
+    return(HWREG(ui32Base + I2C_O_MDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the Master clock timeout value.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Value is the number of I2C clocks before the timeout is
+//!        asserted.
+//!
+//! This function enables and configures the clock low timeout feature in the
+//! I2C peripheral.  This feature is implemented as a 12-bit counter, with the
+//! upper 8-bits being programmable.  For example, to program a timeout of 20ms
+//! with a 100-kHz SCL frequency, \e ui32Value is 0x7d.
+//!
+//! \note Not all Tiva devices support this function.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Write the timeout value.
+    //
+    HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! Configures ACK override behavior of the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param bEnable enables or disables ACK override.
+//!
+//! This function enables or disables ACK override, allowing the user
+//! application to drive the value on SDA during the ACK cycle.
+//!
+//! \note Not all Tiva devices support this function.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable or disable based on bEnable.
+    //
+    if(bEnable)
+    {
+        HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN;
+    }
+    else
+    {
+        HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN;
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes the ACK value.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer.
+//!
+//! This function puts the desired ACK value on SDA during the ACK cycle.  The
+//! value written is only valid when ACK override is enabled using
+//! I2CSlaveACKOverride().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // ACK or NACK based on the value of bACK.
+    //
+    if(bACK)
+    {
+        HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL;
+    }
+    else
+    {
+        HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the I2C Slave status
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function returns the action requested from a master, if any.
+//! Possible values are:
+//!
+//! - \b I2C_SLAVE_ACT_NONE
+//! - \b I2C_SLAVE_ACT_RREQ
+//! - \b I2C_SLAVE_ACT_TREQ
+//! - \b I2C_SLAVE_ACT_RREQ_FBR
+//! - \b I2C_SLAVE_ACT_OWN2SEL
+//! - \b I2C_SLAVE_ACT_QCMD
+//! - \b I2C_SLAVE_ACT_QCMD_DATA
+//!
+//! \note Not all Tiva devices support the second I2C slave's own address
+//! or the quick command function.  Please consult the device data sheet to
+//! determine if these features are supported.
+//!
+//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
+//! requested of the I2C Slave, \b I2C_SLAVE_ACT_RREQ to indicate that
+//! an I2C master has sent data to the I2C Slave, \b I2C_SLAVE_ACT_TREQ
+//! to indicate that an I2C master has requested that the I2C Slave send
+//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
+//! data to the I2C slave and the first byte following the slave's own address
+//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C
+//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick
+//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the
+//! data bit was set when the quick command was received.
+//
+//*****************************************************************************
+uint32_t
+I2CSlaveStatus(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return the slave status.
+    //
+    return(HWREG(ui32Base + I2C_O_SCSR));
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8Data is the data to be transmitted from the I2C Slave
+//!
+//! This function places the supplied data into I2C Slave Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Write the byte.
+    //
+    HWREG(ui32Base + I2C_O_SDR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function reads a byte of data from the I2C Slave Data Register.
+//!
+//! \return Returns the byte received from by the I2C Slave, cast as an
+//! uint32_t.
+//
+//*****************************************************************************
+uint32_t
+I2CSlaveDataGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Read a byte.
+    //
+    return(HWREG(ui32Base + I2C_O_SDR));
+}
+
+//*****************************************************************************
+//
+//! Configures the I2C transmit (TX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Config is the configuration of the FIFO using specified macros.
+//!
+//! This configures the I2C peripheral's transmit FIFO.  The transmit FIFO can
+//! be used by the master or slave, but not both.  The following macros are
+//! used to configure the TX FIFO behavior for master or slave, with or without
+//! DMA:
+//!
+//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE,
+//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA
+//!
+//! To select the trigger level, one of the following macros should be used:
+//!
+//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2,
+//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4,
+//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6,
+//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Clear transmit configuration data.
+    //
+    HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000;
+
+    //
+    // Store new transmit configuration data.
+    //
+    HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Flushes the transmit (TX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function flushes the I2C transmit FIFO.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CTxFIFOFlush(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Flush the TX FIFO.
+    //
+    HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH;
+}
+
+//*****************************************************************************
+//
+//! Configures the I2C receive (RX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Config is the configuration of the FIFO using specified macros.
+//!
+//! This configures the I2C peripheral's receive FIFO.  The receive FIFO can be
+//! used by the master or slave, but not both.  The following macros are used
+//! to configure the RX FIFO behavior for master or slave, with or without DMA:
+//!
+//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE,
+//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA
+//!
+//! To select the trigger level, one of the following macros should be used:
+//!
+//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2,
+//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4,
+//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6,
+//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Clear receive configuration data.
+    //
+    HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff;
+
+    //
+    // Store new receive configuration data.
+    //
+    HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Flushes the receive (RX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function flushes the I2C receive FIFO.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CRxFIFOFlush(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Flush the TX FIFO.
+    //
+    HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH;
+}
+
+//*****************************************************************************
+//
+//! Gets the current FIFO status.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function retrieves the status for both the transmit (TX) and receive
+//! (RX) FIFOs.  The trigger level for the transmit FIFO is set using
+//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet().
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return Returns the FIFO status, enumerated as a bit field containing
+//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY,
+//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and
+//! \b I2C_FIFO_TX_EMPTY.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFOStatus(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Return the contents of the FIFO status register.
+    //
+    return(HWREG(ui32Base + I2C_O_FIFOSTATUS));
+}
+
+//*****************************************************************************
+//
+//! Writes a data byte to the I2C transmit FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8Data is the data to be placed into the transmit FIFO.
+//!
+//! This function adds a byte of data to the I2C transmit FIFO.  If there is
+//! no space available in the FIFO,  this function waits for space to become
+//! available before returning.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Wait until there is space.
+    //
+    while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
+    {
+    }
+
+    //
+    // Place data into the FIFO.
+    //
+    HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! Writes a data byte to the I2C transmit FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8Data is the data to be placed into the transmit FIFO.
+//!
+//! This function adds a byte of data to the I2C transmit FIFO.  If there is
+//! no space available in the FIFO, this function returns a zero.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return The number of elements added to the I2C transmit FIFO.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // If FIFO is full, return zero.
+    //
+    if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
+    {
+        return(0);
+    }
+    else
+    {
+        HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
+        return(1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads a byte from the I2C receive FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function reads a byte of data from I2C receive FIFO and places it in
+//! the location specified by the \e pui8Data parameter.  If there is no data
+//! available, this function waits until data is received before returning.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return The data byte.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFODataGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Wait until there is data to read.
+    //
+    while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
+    {
+    }
+
+    //
+    // Read a byte.
+    //
+    return(HWREG(ui32Base + I2C_O_FIFODATA));
+}
+
+//*****************************************************************************
+//
+//! Reads a byte from the I2C receive FIFO.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param pui8Data is a pointer where the read data is stored.
+//!
+//! This function reads a byte of data from I2C receive FIFO and places it in
+//! the location specified by the \e pui8Data parameter.  If there is no data
+//! available, this functions returns 0.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return The number of elements read from the I2C receive FIFO.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // If nothing in the FIFO, return zero.
+    //
+    if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
+    {
+        return(0);
+    }
+    else
+    {
+        *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA);
+        return(1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Set the burst length for a I2C master FIFO operation.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8Length is the length of the burst transfer.
+//!
+//! This function configures the burst length for a I2C Master FIFO operation.
+//! The burst field is limited to 8 bits or 256 bytes.  The burst length
+//! applies to a single I2CMCS BURST operation meaning that it specifies the
+//! burst length for only the current operation (can be TX or RX).  Each burst
+//! operation must configure the burst length prior to writing the BURST bit
+//! in the I2CMCS using I2CMasterControl().
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255));
+
+    //
+    // Set the burst length.
+    //
+    HWREG(ui32Base + I2C_O_MBLEN) = ui8Length;
+}
+
+//*****************************************************************************
+//
+//! Returns the current value of the burst transfer counter.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function returns the current value of the burst transfer counter that
+//! is used by the FIFO mechanism.  Software can use this value to determine
+//! how many bytes remain in a transfer, or where in the transfer the burst
+//! operation was if an error has occurred.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterBurstCountGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Get burst count.
+    //
+    return(HWREG(ui32Base + I2C_O_MBCNT));
+}
+
+//*****************************************************************************
+//
+//! Configures the I2C Master glitch filter.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Config is the glitch filter configuration.
+//!
+//! This function configures the I2C Master glitch filter.  The value passed in
+//! to \e ui32Config determines the sampling range of the glitch filter, which
+//! is configurable between 1 and 32 system clock cycles.  The default
+//! configuration of the glitch filter is 0 system clock cycles, which means
+//! that it's disabled.
+//!
+//! The \e ui32Config field should be any of the following values:
+//!
+//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED
+//! - \b I2C_MASTER_GLITCH_FILTER_1
+//! - \b I2C_MASTER_GLITCH_FILTER_2
+//! - \b I2C_MASTER_GLITCH_FILTER_3
+//! - \b I2C_MASTER_GLITCH_FILTER_4
+//! - \b I2C_MASTER_GLITCH_FILTER_8
+//! - \b I2C_MASTER_GLITCH_FILTER_16
+//! - \b I2C_MASTER_GLITCH_FILTER_32
+//!
+//! \note Not all Tiva devices support this function.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Configure the glitch filter field of MTPR.
+    //
+    HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Enables FIFO usage for the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Config is the desired FIFO configuration of the I2C Slave.
+//!
+//! This function configures the I2C Slave to use the FIFO(s).  This
+//! function should be used in combination with I2CTxFIFOConfigSet() and/or
+//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell
+//! the FIFO hardware whether to interact with the I2C Master or Slave.  The
+//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and
+//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config
+//! field.
+//!
+//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(),
+//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration.
+//! Therefore, application software should call I2CSlaveEnable() followed by
+//! I2CSlaveFIFOEnable() with the desired FIFO configuration.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Enable the FIFOs for the slave.
+    //
+    HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+//! Disable FIFO usage for the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function disables the FIFOs for the I2C Slave.  After calling this
+//! this function, the FIFOs are disabled, but the Slave remains active.
+//!
+//! \note Not all Tiva devices have an I2C FIFO.  Please consult the
+//! device data sheet to determine if this feature is supported.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveFIFODisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Disable slave FIFOs.
+    //
+    HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/i2c.h b/bsp/tm4c129x/libraries/driverlib/i2c.h
new file mode 100644
index 0000000000..042862be63
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/i2c.h
@@ -0,0 +1,361 @@
+//*****************************************************************************
+//
+// i2c.h - Prototypes for the I2C Driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_I2C_H__
+#define __DRIVERLIB_I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines for the API.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Interrupt defines.
+//
+//*****************************************************************************
+#define I2C_INT_MASTER          0x00000001
+#define I2C_INT_SLAVE           0x00000002
+
+//*****************************************************************************
+//
+// I2C Master commands.
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND                                            \
+                                0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE                                         \
+                                0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START                                       \
+                                0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT                                        \
+                                0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH                                      \
+                                0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_STOP                                        \
+                                0x00000004
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP                                  \
+                                0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START                                    \
+                                0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT                                     \
+                                0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH                                   \
+                                0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP                               \
+                                0x00000004
+#define I2C_MASTER_CMD_QUICK_COMMAND                                          \
+                                0x00000027
+#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND                                    \
+                                0x00000013
+#define I2C_MASTER_CMD_FIFO_SINGLE_SEND                                       \
+                                0x00000046
+#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE                                    \
+                                0x00000046
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_START                                  \
+                                0x00000042
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT                                   \
+                                0x00000040
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH                                 \
+                                0x00000044
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP                             \
+                                0x00000004
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START                               \
+                                0x0000004a
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT                                \
+                                0x00000048
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH                              \
+                                0x00000044
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP                          \
+                                0x00000004
+
+//*****************************************************************************
+//
+// I2C Master glitch filter configuration.
+//
+//*****************************************************************************
+#define I2C_MASTER_GLITCH_FILTER_DISABLED                                     \
+                                0
+#define I2C_MASTER_GLITCH_FILTER_1                                            \
+                                0x00010000
+#define I2C_MASTER_GLITCH_FILTER_2                                            \
+                                0x00020000
+#define I2C_MASTER_GLITCH_FILTER_3                                            \
+                                0x00030000
+#define I2C_MASTER_GLITCH_FILTER_4                                            \
+                                0x00040000
+#define I2C_MASTER_GLITCH_FILTER_8                                            \
+                                0x00050000
+#define I2C_MASTER_GLITCH_FILTER_16                                           \
+                                0x00060000
+#define I2C_MASTER_GLITCH_FILTER_32                                           \
+                                0x00070000
+
+//*****************************************************************************
+//
+// I2C Master error status.
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE     0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE      0
+#define I2C_SLAVE_ACT_RREQ      0x00000001  // Master has sent data
+#define I2C_SLAVE_ACT_TREQ      0x00000002  // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR  0x00000005  // Master has sent first byte
+#define I2C_SLAVE_ACT_OWN2SEL   0x00000008  // Master requested secondary slave
+#define I2C_SLAVE_ACT_QCMD      0x00000010  // Master has sent a Quick Command
+#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020  // Master Quick Command value
+
+//*****************************************************************************
+//
+// Miscellaneous I2C driver definitions.
+//
+//*****************************************************************************
+#define I2C_MASTER_MAX_RETRIES  1000        // Number of retries
+
+//*****************************************************************************
+//
+// I2C Master interrupts.
+//
+//*****************************************************************************
+#define I2C_MASTER_INT_RX_FIFO_FULL                                           \
+                                0x00000800  // RX FIFO Full Interrupt
+#define I2C_MASTER_INT_TX_FIFO_EMPTY                                          \
+                                0x00000400  // TX FIFO Empty Interrupt
+#define I2C_MASTER_INT_RX_FIFO_REQ                                            \
+                                0x00000200  // RX FIFO Request Interrupt
+#define I2C_MASTER_INT_TX_FIFO_REQ                                            \
+                                0x00000100  // TX FIFO Request Interrupt
+#define I2C_MASTER_INT_ARB_LOST                                               \
+                                0x00000080  // Arb Lost Interrupt
+#define I2C_MASTER_INT_STOP     0x00000040  // Stop Condition Interrupt
+#define I2C_MASTER_INT_START    0x00000020  // Start Condition Interrupt
+#define I2C_MASTER_INT_NACK     0x00000010  // Addr/Data NACK Interrupt
+#define I2C_MASTER_INT_TX_DMA_DONE                                            \
+                                0x00000008  // TX DMA Complete Interrupt
+#define I2C_MASTER_INT_RX_DMA_DONE                                            \
+                                0x00000004  // RX DMA Complete Interrupt
+#define I2C_MASTER_INT_TIMEOUT  0x00000002  // Clock Timeout Interrupt
+#define I2C_MASTER_INT_DATA     0x00000001  // Data Interrupt
+
+//*****************************************************************************
+//
+// I2C Slave interrupts.
+//
+//*****************************************************************************
+#define I2C_SLAVE_INT_RX_FIFO_FULL                                            \
+                                0x00000100  // RX FIFO Full Interrupt
+#define I2C_SLAVE_INT_TX_FIFO_EMPTY                                           \
+                                0x00000080  // TX FIFO Empty Interrupt
+#define I2C_SLAVE_INT_RX_FIFO_REQ                                             \
+                                0x00000040  // RX FIFO Request Interrupt
+#define I2C_SLAVE_INT_TX_FIFO_REQ                                             \
+                                0x00000020  // TX FIFO Request Interrupt
+#define I2C_SLAVE_INT_TX_DMA_DONE                                             \
+                                0x00000010  // TX DMA Complete Interrupt
+#define I2C_SLAVE_INT_RX_DMA_DONE                                             \
+                                0x00000008  // RX DMA Complete Interrupt
+#define I2C_SLAVE_INT_STOP      0x00000004  // Stop Condition Interrupt
+#define I2C_SLAVE_INT_START     0x00000002  // Start Condition Interrupt
+#define I2C_SLAVE_INT_DATA      0x00000001  // Data Interrupt
+
+//*****************************************************************************
+//
+// I2C Slave FIFO configuration macros.
+//
+//*****************************************************************************
+#define I2C_SLAVE_TX_FIFO_ENABLE                                              \
+                                0x00000002
+#define I2C_SLAVE_RX_FIFO_ENABLE                                              \
+                                0x00000004
+
+//*****************************************************************************
+//
+// I2C FIFO configuration macros.
+//
+//*****************************************************************************
+#define I2C_FIFO_CFG_TX_MASTER  0x00000000
+#define I2C_FIFO_CFG_TX_SLAVE   0x00008000
+#define I2C_FIFO_CFG_RX_MASTER  0x00000000
+#define I2C_FIFO_CFG_RX_SLAVE   0x80000000
+#define I2C_FIFO_CFG_TX_MASTER_DMA                                            \
+                                0x00002000
+#define I2C_FIFO_CFG_TX_SLAVE_DMA                                             \
+                                0x0000a000
+#define I2C_FIFO_CFG_RX_MASTER_DMA                                            \
+                                0x20000000
+#define I2C_FIFO_CFG_RX_SLAVE_DMA                                             \
+                                0xa0000000
+#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
+#define I2C_FIFO_CFG_TX_TRIG_1  0x00000001
+#define I2C_FIFO_CFG_TX_TRIG_2  0x00000002
+#define I2C_FIFO_CFG_TX_TRIG_3  0x00000003
+#define I2C_FIFO_CFG_TX_TRIG_4  0x00000004
+#define I2C_FIFO_CFG_TX_TRIG_5  0x00000005
+#define I2C_FIFO_CFG_TX_TRIG_6  0x00000006
+#define I2C_FIFO_CFG_TX_TRIG_7  0x00000007
+#define I2C_FIFO_CFG_TX_TRIG_8  0x00000008
+#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
+#define I2C_FIFO_CFG_RX_TRIG_1  0x00010000
+#define I2C_FIFO_CFG_RX_TRIG_2  0x00020000
+#define I2C_FIFO_CFG_RX_TRIG_3  0x00030000
+#define I2C_FIFO_CFG_RX_TRIG_4  0x00040000
+#define I2C_FIFO_CFG_RX_TRIG_5  0x00050000
+#define I2C_FIFO_CFG_RX_TRIG_6  0x00060000
+#define I2C_FIFO_CFG_RX_TRIG_7  0x00070000
+#define I2C_FIFO_CFG_RX_TRIG_8  0x00080000
+
+//*****************************************************************************
+//
+// I2C FIFO status.
+//
+//*****************************************************************************
+#define I2C_FIFO_RX_BELOW_TRIG_LEVEL                                          \
+                                0x00040000
+#define I2C_FIFO_RX_FULL        0x00020000
+#define I2C_FIFO_RX_EMPTY       0x00010000
+#define I2C_FIFO_TX_BELOW_TRIG_LEVEL                                          \
+                                0x00000004
+#define I2C_FIFO_TX_FULL        0x00000002
+#define I2C_FIFO_TX_EMPTY       0x00000001
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
+extern void I2CIntUnregister(uint32_t ui32Base);
+extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CTxFIFOFlush(uint32_t ui32Base);
+extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CRxFIFOFlush(uint32_t ui32Base);
+extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
+extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
+                                          uint8_t ui8Data);
+extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
+extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
+                                          uint8_t *pui8Data);
+extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
+                                    uint8_t ui8Length);
+extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
+extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
+                                           uint32_t ui32Config);
+extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CSlaveFIFODisable(uint32_t ui32Base);
+extern bool I2CMasterBusBusy(uint32_t ui32Base);
+extern bool I2CMasterBusy(uint32_t ui32Base);
+extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
+extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
+extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern void I2CMasterDisable(uint32_t ui32Base);
+extern void I2CMasterEnable(uint32_t ui32Base);
+extern uint32_t I2CMasterErr(uint32_t ui32Base);
+extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
+                                bool bFast);
+extern void I2CMasterIntClear(uint32_t ui32Base);
+extern void I2CMasterIntDisable(uint32_t ui32Base);
+extern void I2CMasterIntEnable(uint32_t ui32Base);
+extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
+extern void I2CMasterIntEnableEx(uint32_t ui32Base,
+                                 uint32_t ui32IntFlags);
+extern void I2CMasterIntDisableEx(uint32_t ui32Base,
+                                  uint32_t ui32IntFlags);
+extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
+                                       bool bMasked);
+extern void I2CMasterIntClearEx(uint32_t ui32Base,
+                                uint32_t ui32IntFlags);
+extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
+extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
+extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
+extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
+extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
+                                  uint8_t ui8SlaveAddr,
+                                  bool bReceive);
+extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
+extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern void I2CSlaveDisable(uint32_t ui32Base);
+extern void I2CSlaveEnable(uint32_t ui32Base);
+extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
+extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
+                                 uint8_t ui8SlaveAddr);
+extern void I2CSlaveIntClear(uint32_t ui32Base);
+extern void I2CSlaveIntDisable(uint32_t ui32Base);
+extern void I2CSlaveIntEnable(uint32_t ui32Base);
+extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
+                                 uint32_t ui32IntFlags);
+extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
+extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
+                                      bool bMasked);
+extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_I2C_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/interrupt.c b/bsp/tm4c129x/libraries/driverlib/interrupt.c
new file mode 100644
index 0000000000..55aaa801a1
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/interrupt.c
@@ -0,0 +1,1060 @@
+//*****************************************************************************
+//
+// interrupt.c - Driver for the NVIC Interrupt Controller.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Priority[] =
+{
+    NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+    NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
+    NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Regs[] =
+{
+    0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
+    NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
+    NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
+    NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
+    NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
+    NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
+    NVIC_PRI32, NVIC_PRI33, NVIC_PRI34
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt enable for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pui32EnRegs[] =
+{
+    NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt disable for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Dii16Regs[] =
+{
+    NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt pend for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pui32PendRegs[] =
+{
+    NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt unpend for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pui32UnpendRegs[] =
+{
+    NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts.  It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger.  Since interrupts must be disabled before unregistering the
+//! corresponding handler, this should never be called during normal operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+_IntDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// The processor vector table.
+//
+// This contains a list of the handlers for the various interrupt sources in
+// the system.  The layout of this list is defined by the hardware; assertion
+// of an interrupt causes the processor to start executing directly at the
+// address given in the corresponding location in this list.
+//
+//*****************************************************************************
+//
+// Set the size of the vector table to the largest number of interrupts of
+// any device
+//
+#undef NUM_INTERRUPTS
+#define NUM_INTERRUPTS                          155
+#if defined(ewarm)
+#pragma data_alignment=1024
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
+#elif defined(sourcerygxx)
+static __attribute__((section(".cs3.region-head.ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
+#elif defined(ccs) || defined(DOXYGEN)
+#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#else
+static __attribute__((section("vtable")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(1024)));
+#endif
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! This function allows the processor to respond to interrupts.  This function
+//! does not affect the set of interrupts enabled in the interrupt controller;
+//! it just gates the single interrupt from the controller to the processor.
+//!
+//! \b Example: Enable interrupts to the processor.
+//!
+//! \verbatim
+//! //
+//! // Enable interrupts to the processor.
+//! //
+//! IntMasterEnable();
+//!
+//! \endverbatim
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+bool
+IntMasterEnable(void)
+{
+    //
+    // Enable processor interrupts.
+    //
+    return(CPUcpsie());
+}
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! This function prevents the processor from receiving interrupts.  This
+//! function does not affect the set of interrupts enabled in the interrupt
+//! controller; it just gates the single interrupt from the controller to the
+//! processor.
+//!
+//! \note Previously, this function had no return value.  As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>.  Now that the return is a
+//! <tt>bool</tt>, a compiler error occurs in this case.  The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \b Example: Disable interrupts to the processor.
+//!
+//! \verbatim
+//! //
+//! // Disable interrupts to the processor.
+//! //
+//! IntMasterDisable();
+//!
+//! \endverbatim
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+bool
+IntMasterDisable(void)
+{
+    //
+    // Disable processor interrupts.
+    //
+    return(CPUcpsid());
+}
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param ui32Interrupt specifies the interrupt in question.
+//! \param pfnHandler is a pointer to the function to be called.
+//!
+//! This function is used to specify the handler function to be called when the
+//! given interrupt is asserted to the processor.  The \e ui32Interrupt
+//! parameter must be one of the valid \b INT_* values listed in Peripheral
+//! Driver Library User's Guide and defined in the inc/hw_ints.h header file.
+//! When the interrupt occurs, if it is enabled (via IntEnable()), the handler
+//! function is called in interrupt context.  Because the handler function can
+//! preempt other code, care must be taken to protect memory or peripherals
+//! that are accessed by the handler and other non-handler code.
+//!
+//! \note The use of this function (directly or indirectly via a peripheral
+//! driver interrupt register function) moves the interrupt vector table from
+//! flash to SRAM.  Therefore, care must be taken when linking the application
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;
+//! otherwise the NVIC does not look in the correct portion of memory for the
+//! vector table (it requires the vector table be on a 1 kB memory alignment).
+//! Normally, the SRAM vector table is so placed via the use of linker scripts.
+//! See the discussion of compile-time versus run-time interrupt handler
+//! registration in the introduction to this chapter.
+//!
+//! \b Example: Set the UART 0 interrupt handler.
+//!
+//! \verbatim
+//!
+//! //
+//! // UART 0 interrupt handler.
+//! //
+//! void
+//! UART0Handler(void)
+//! {
+//!     //
+//!     // Handle interrupt.
+//!     //
+//! }
+//!
+//! //
+//! // Set the UART 0 interrupt handler.
+//! //
+//! IntRegister(INT_UART0, UART0Handler);
+//!
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void))
+{
+    uint32_t ui32Idx, ui32Value;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Make sure that the RAM vector table is correctly aligned.
+    //
+    ASSERT(((uint32_t)g_pfnRAMVectors & 0x000003ff) == 0);
+
+    //
+    // See if the RAM vector table has been initialized.
+    //
+    if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors)
+    {
+        //
+        // Copy the vector table from the beginning of FLASH to the RAM vector
+        // table.
+        //
+        ui32Value = HWREG(NVIC_VTABLE);
+        for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++)
+        {
+            g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) +
+                                                             ui32Value);
+        }
+
+        //
+        // Point the NVIC at the RAM vector table.
+        //
+        HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors;
+    }
+
+    //
+    // Save the interrupt handler.
+    //
+    g_pfnRAMVectors[ui32Interrupt] = pfnHandler;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param ui32Interrupt specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler is called when the
+//! given interrupt is asserted to the processor.  The \e ui32Interrupt
+//! parameter must be one of the valid \b INT_* values listed in Peripheral
+//! Driver Library User's Guide and defined in the inc/hw_ints.h header file.
+//! The interrupt source is automatically disabled (via IntDisable()) if
+//! necessary.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \b Example: Reset the UART 0 interrupt handler to the default handler.
+//!
+//! \verbatim
+//! //
+//! // Reset the UART 0 interrupt handler to the default handler.
+//! //
+//! IntUnregister(INT_UART0);
+//!
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntUnregister(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Reset the interrupt handler.
+    //
+    g_pfnRAMVectors[ui32Interrupt] = _IntDefaultHandler;
+}
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param ui32Bits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! sub-priority levels in the interrupt priority specification.  The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the Tiva C and E Series family, three bits are available for hardware
+//! interrupt prioritization and therefore priority grouping values of three
+//! through seven have the same effect.
+//!
+//! \b Example: Set the priority grouping for the interrupt controller.
+//!
+//! \verbatim
+//! //
+//! // Set the priority grouping for the interrupt controller to 2 bits.
+//! //
+//! IntPriorityGroupingSet(2);
+//!
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityGroupingSet(uint32_t ui32Bits)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Bits < NUM_PRIORITY);
+
+    //
+    // Set the priority grouping.
+    //
+    HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits];
+}
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! sub-priority levels in the interrupt priority specification.
+//!
+//! \b Example: Get the priority grouping for the interrupt controller.
+//!
+//! \verbatim
+//! //
+//! // Get the priority grouping for the interrupt controller.
+//! //
+//! IntPriorityGroupingGet();
+//!
+//! \endverbatim
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+uint32_t
+IntPriorityGroupingGet(void)
+{
+    uint32_t ui32Loop, ui32Value;
+
+    //
+    // Read the priority grouping.
+    //
+    ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
+
+    //
+    // Loop through the priority grouping values.
+    //
+    for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++)
+    {
+        //
+        // Stop looping if this value matches.
+        //
+        if(ui32Value == g_pui32Priority[ui32Loop])
+        {
+            break;
+        }
+    }
+
+    //
+    // Return the number of priority bits.
+    //
+    return(ui32Loop);
+}
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt in question.
+//! \param ui8Priority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt.  The
+//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed
+//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h
+//! header file.  The \e ui8Priority parameter specifies the interrupts
+//! hardware priority level of the interrupt in the interrupt controller.
+//! When multiple interrupts are asserted simultaneously, the ones with the
+//! highest priority are processed before the lower priority interrupts.
+//! Smaller numbers correspond to higher interrupt priorities; priority 0 is
+//! the highest interrupt priority.
+//!
+//! \note The hardware priority mechanism only looks at the upper 3 bits of the
+//! priority level, so any prioritization must be performed in those bits.  The
+//! remaining bits can be used to sub-prioritize the interrupt sources, and may
+//! be used by the hardware priority mechanism on a future part.  This
+//! arrangement allows priorities to migrate to different NVIC implementations
+//! without changing the gross prioritization of the interrupts.
+//!
+//! \b Example: Set priorities for UART 0 and USB interrupts.
+//!
+//! \verbatim
+//! //
+//! // Set the UART 0 interrupt priority to the lowest priority.
+//! //
+//! IntPrioritySet(INT_UART0, 0xE0);
+//!
+//! //
+//! // Set the USB 0 interrupt priority to the highest priority.
+//! //
+//! IntPrioritySet(INT_USB0, 0);
+//!
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
+
+    //
+    // Set the interrupt priority.
+    //
+    ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);
+    ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));
+    ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));
+    HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt.  The \e ui32Interrupt
+//! parameter must be one of the valid \b INT_* values listed in Peripheral
+//! Driver Library User's Guide and defined in the inc/hw_ints.h header file.
+//! See IntPrioritySet() for a full definition of the priority value.
+//!
+//! \b Example: Get the current UART 0 interrupt priority.
+//!
+//! \verbatim
+//! //
+//! // Get the current UART 0 interrupt priority.
+//! //
+//! IntPriorityGet(INT_UART0);
+//!
+//! \endverbatim
+//!
+//! \return Returns the interrupt priority for the given interrupt.
+//
+//*****************************************************************************
+int32_t
+IntPriorityGet(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
+
+    //
+    // Return the interrupt priority.
+    //
+    return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >>
+            (8 * (ui32Interrupt & 3))) & 0xFF);
+}
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller.  The
+//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed
+//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h
+//! header file. Other enables for the interrupt (such as at the peripheral
+//! level) are unaffected by this function.
+//!
+//! \b Example: Enable the UART 0 interrupt.
+//!
+//! \verbatim
+//! //
+//! // Enable the UART 0 interrupt in the interrupt controller.
+//! //
+//! IntEnable(INT_UART0);
+//!
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntEnable(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to enable.
+    //
+    if(ui32Interrupt == FAULT_MPU)
+    {
+        //
+        // Enable the MemManage interrupt.
+        //
+        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
+    }
+    else if(ui32Interrupt == FAULT_BUS)
+    {
+        //
+        // Enable the bus fault interrupt.
+        //
+        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
+    }
+    else if(ui32Interrupt == FAULT_USAGE)
+    {
+        //
+        // Enable the usage fault interrupt.
+        //
+        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
+    }
+    else if(ui32Interrupt == FAULT_SYSTICK)
+    {
+        //
+        // Enable the System Tick interrupt.
+        //
+        HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+    }
+    else if(ui32Interrupt >= 16)
+    {
+        //
+        // Enable the general interrupt.
+        //
+        HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) =
+            1 << ((ui32Interrupt - 16) & 31);
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller.  The
+//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed
+//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h
+//! header file.  Other enables for the interrupt (such as at the peripheral
+//! level) are unaffected by this function.
+//!
+//! \b Example: Disable the UART 0 interrupt.
+//!
+//! \verbatim
+//! //
+//! // Disable the UART 0 interrupt in the interrupt controller.
+//! //
+//! IntDisable(INT_UART0);
+//!
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntDisable(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to disable.
+    //
+    if(ui32Interrupt == FAULT_MPU)
+    {
+        //
+        // Disable the MemManage interrupt.
+        //
+        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
+    }
+    else if(ui32Interrupt == FAULT_BUS)
+    {
+        //
+        // Disable the bus fault interrupt.
+        //
+        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
+    }
+    else if(ui32Interrupt == FAULT_USAGE)
+    {
+        //
+        // Disable the usage fault interrupt.
+        //
+        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
+    }
+    else if(ui32Interrupt == FAULT_SYSTICK)
+    {
+        //
+        // Disable the System Tick interrupt.
+        //
+        HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+    }
+    else if(ui32Interrupt >= 16)
+    {
+        //
+        // Disable the general interrupt.
+        //
+        HWREG(g_pui32Dii16Regs[(ui32Interrupt - 16) / 32]) =
+            1 << ((ui32Interrupt - 16) & 31);
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns if a peripheral interrupt is enabled.
+//!
+//! \param ui32Interrupt specifies the interrupt to check.
+//!
+//! This function checks if the specified interrupt is enabled in the interrupt
+//! controller.  The \e ui32Interrupt parameter must be one of the valid
+//! \b INT_* values listed in Peripheral Driver Library User's Guide and
+//! defined in the inc/hw_ints.h header file.
+//!
+//! \b Example: Disable the UART 0 interrupt if it is enabled.
+//!
+//! \verbatim
+//! //
+//! // Disable the UART 0 interrupt if it is enabled.
+//! //
+//! if(IntIsEnabled(INT_UART0))
+//! {
+//!     IntDisable(INT_UART0);
+//! }
+//! \endverbatim
+//!
+//! \return A non-zero value if the interrupt is enabled.
+//
+//*****************************************************************************
+uint32_t
+IntIsEnabled(uint32_t ui32Interrupt)
+{
+    uint32_t ui32Ret;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Initialize the return value.
+    //
+    ui32Ret = 0;
+
+    //
+    // Determine the interrupt to disable.
+    //
+    if(ui32Interrupt == FAULT_MPU)
+    {
+        //
+        // Check the MemManage interrupt.
+        //
+        ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM;
+    }
+    else if(ui32Interrupt == FAULT_BUS)
+    {
+        //
+        // Check the bus fault interrupt.
+        //
+        ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS;
+    }
+    else if(ui32Interrupt == FAULT_USAGE)
+    {
+        //
+        // Check the usage fault interrupt.
+        //
+        ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE;
+    }
+    else if(ui32Interrupt == FAULT_SYSTICK)
+    {
+        //
+        // Check the System Tick interrupt.
+        //
+        ui32Ret = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN;
+    }
+    else if(ui32Interrupt >= 16)
+    {
+        //
+        // Check the general interrupt.
+        //
+        ui32Ret = HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) &
+                  (1 << ((ui32Interrupt - 16) & 31));
+    }
+    return(ui32Ret);
+}
+
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller.  The
+//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed
+//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h
+//! header file.  Pending an interrupt causes the interrupt controller to
+//! execute the corresponding interrupt handler at the next available time,
+//! based on the current interrupt state priorities.  For example, if called by
+//! a higher priority interrupt handler, the specified interrupt handler is not
+//! called until after the current interrupt handler has completed execution.
+//! The interrupt must have been enabled for it to be called.
+//!
+//! \b Example: Pend a UART 0 interrupt.
+//!
+//! \verbatim
+//! //
+//! // Pend a UART 0 interrupt.
+//! //
+//! IntPendSet(INT_UART0);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendSet(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to pend.
+    //
+    if(ui32Interrupt == FAULT_NMI)
+    {
+        //
+        // Pend the NMI interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
+    }
+    else if(ui32Interrupt == FAULT_PENDSV)
+    {
+        //
+        // Pend the PendSV interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
+    }
+    else if(ui32Interrupt == FAULT_SYSTICK)
+    {
+        //
+        // Pend the SysTick interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
+    }
+    else if(ui32Interrupt >= 16)
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG(g_pui32PendRegs[(ui32Interrupt - 16) / 32]) =
+            1 << ((ui32Interrupt - 16) & 31);
+    }
+}
+
+//*****************************************************************************
+//
+//! Un-pends an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be un-pended.  The
+//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed
+//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h
+//! header file.
+//!
+//! The specified interrupt is un-pended in the interrupt controller.  This
+//! causes any previously generated interrupts that have not been handled
+//! yet (due to higher priority interrupts or the interrupt not having been
+//! enabled yet) to be discarded.
+//!
+//! \b Example: Un-pend a UART 0 interrupt.
+//!
+//! \verbatim
+//! //
+//! // Un-pend a UART 0 interrupt.
+//! //
+//! IntPendClear(INT_UART0);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendClear(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to unpend.
+    //
+    if(ui32Interrupt == FAULT_PENDSV)
+    {
+        //
+        // Unpend the PendSV interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
+    }
+    else if(ui32Interrupt == FAULT_SYSTICK)
+    {
+        //
+        // Unpend the SysTick interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
+    }
+    else if(ui32Interrupt >= 16)
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG(g_pui32UnpendRegs[(ui32Interrupt - 16) / 32]) =
+            1 << ((ui32Interrupt - 16) & 31);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param ui32PriorityMask is the priority level that is masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level are masked.  Masking
+//! interrupts can be used to globally disable a set of interrupts with
+//! priority below a predetermined threshold.  A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 allows interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater are blocked.
+//!
+//! \note The hardware priority mechanism only looks at the upper 3 bits of the
+//! priority level, so any prioritization must be performed in those bits.
+//!
+//! \b Example: Mask of interrupt priorities greater than or equal to 0x80.
+//!
+//! \verbatim
+//! //
+//! // Mask of interrupt priorities greater than or equal to 0x80.
+//! //
+//! IntPriorityMaskSet(0x80);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityMaskSet(uint32_t ui32PriorityMask)
+{
+    //
+    // Set the priority mask.
+    //
+    CPUbasepriSet(ui32PriorityMask);
+}
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level.  The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked.  A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 allows interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater are blocked.
+//!
+//! The hardware priority mechanism only looks at the upper 3 bits of the
+//! priority level, so any prioritization must be performed in those bits.
+//!
+//! \b Example: Get the current interrupt priority mask.
+//!
+//! \verbatim
+//! //
+//! // Get the current interrupt priority mask.
+//! //
+//! IntPriorityMaskGet();
+//! \endverbatim
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+uint32_t
+IntPriorityMaskGet(void)
+{
+    //
+    // Return the current priority mask.
+    //
+    return(CPUbasepriGet());
+}
+
+//*****************************************************************************
+//
+//! Triggers an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be triggered.
+//!
+//! This function performs a software trigger of an interrupt.  The
+//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed
+//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h
+//! header file.  The interrupt controller behaves as if the corresponding
+//! interrupt line was asserted, and the interrupt is handled in the same
+//! manner (meaning that it must be enabled in order to be processed, and the
+//! processing is based on its priority with respect to other unhandled
+//! interrupts).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntTrigger(uint32_t ui32Interrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Interrupt >= 16) && (ui32Interrupt < NUM_INTERRUPTS));
+
+    //
+    // Trigger this interrupt.
+    //
+    HWREG(NVIC_SW_TRIG) = ui32Interrupt - 16;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/interrupt.h b/bsp/tm4c129x/libraries/driverlib/interrupt.h
new file mode 100644
index 0000000000..650a56fd1f
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/interrupt.h
@@ -0,0 +1,94 @@
+//*****************************************************************************
+//
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_INTERRUPT_H__
+#define __DRIVERLIB_INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern bool IntMasterEnable(void);
+extern bool IntMasterDisable(void);
+extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
+extern void IntUnregister(uint32_t ui32Interrupt);
+extern void IntPriorityGroupingSet(uint32_t ui32Bits);
+extern uint32_t IntPriorityGroupingGet(void);
+extern void IntPrioritySet(uint32_t ui32Interrupt,
+                           uint8_t ui8Priority);
+extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
+extern void IntEnable(uint32_t ui32Interrupt);
+extern void IntDisable(uint32_t ui32Interrupt);
+extern uint32_t IntIsEnabled(uint32_t ui32Interrupt);
+extern void IntPendSet(uint32_t ui32Interrupt);
+extern void IntPendClear(uint32_t ui32Interrupt);
+extern void IntPriorityMaskSet(uint32_t ui32PriorityMask);
+extern uint32_t IntPriorityMaskGet(void);
+extern void IntTrigger(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_INTERRUPT_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/lcd.c b/bsp/tm4c129x/libraries/driverlib/lcd.c
new file mode 100644
index 0000000000..db5af4fcd6
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/lcd.c
@@ -0,0 +1,1805 @@
+//*****************************************************************************
+//
+// lcd.c - Defines and Macros for the LCD Controller module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup lcd_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_lcd.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/lcd.h"
+#include "driverlib/debug.h"
+
+//*****************************************************************************
+//
+// These are currently missing from hw_lcd.h and included here as a stopgap
+// until the hardware header is updated.
+//
+//*****************************************************************************
+#ifndef LCD_RASTRTIM0_MSBPPL_S
+#define LCD_RASTRTIM0_MSBPPL_S   3
+#endif
+#ifndef LCD_RASTRTIM2_MSBLPP_S
+#define LCD_RASTRTIM2_MSBLPP_S   26
+#endif
+
+//*****************************************************************************
+//
+//! Configures the basic operating mode and clock rate for the LCD controller.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui8Mode specifies the basic operating mode to be used.
+//! \param ui32PixClk specifies the desired LCD controller pixel or master
+//! clock rate in Hz.
+//! \param ui32SysClk specifies the current system clock rate in Hz.
+//!
+//! This function sets the basic operating mode of the LCD controller and also
+//! its master clock. The \e ui8Mode parameter may be set to either \b
+//! LCD_MODE_LIDD or \b LCD_MODE_RASTER. \b LCD_MODE_LIDD is used to select
+//! LCD Interface Display Driver mode for character panels connected via
+//! an asynchronous interface (CS, WE, OE, ALE, data) and \b LCD_MODE_RASTER
+//! is used to communicate with panels via a synchronous video interface using
+//! data and sync signals.  Additionally, \b LCD_MODE_AUTO_UFLOW_RESTART may
+//! be ORed with either of these modes to indicate that the hardware should
+//! restart automatically if a data underflow occurs.
+//!
+//! The \e ui32PixClk parameter specifies the desired master clock for the
+//! the LCD controller.  In LIDD mode, this value controls the MCLK used in
+//! communication with the display and valid values are between \e ui32SysClk
+//! and \e ui32SysClk/255.  In raster mode, \e ui32PixClk specifies the pixel
+//! clock rate for the raster interface and valid values are between \e
+//! ui32SysClk/2 and \e ui32SysClk/255.  The actual clock rate set may differ
+//! slightly from the desired rate due to the fact that only integer dividers
+//! are supported.  The rate set will, however, be no higher than the requested
+//! value.
+//!
+//! The \e ui32SysClk parameter provides the current system clock rate and is
+//! used to allow the LCD controller clock rate divisor to be correctly set
+//! to give the desired \e ui32PixClk rate.
+//!
+//! \return Returns the actual LCD controller pixel clock or MCLK rate set.
+//
+//*****************************************************************************
+uint32_t
+LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, uint32_t ui32PixClk,
+           uint32_t ui32SysClk)
+{
+    uint32_t ui32Div;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui8Mode & ~(LCD_MODE_RASTER | LCD_MODE_LIDD |
+                        LCD_MODE_AUTO_UFLOW_RESTART)) == 0);
+
+    //
+    // Enable clocks to the LCD controller submodules.
+    //
+    HWREG(ui32Base + LCD_O_CLKEN) = (LCD_CLKEN_DMA | LCD_CLKEN_CORE |
+                                     LCD_CLKEN_LIDD);
+
+    //
+    // Determine the clock divider to use to get as close as possible to the
+    // desired pixel clock.  Note that we set the division up so that we
+    // round the divisor up and ensure that the clock used is never faster
+    // than the requested rate.
+    //
+    ui32Div = (ui32SysClk + (ui32PixClk - 1)) / ui32PixClk;
+
+    //
+    // Check that the calculated value is valid.
+    //
+    ASSERT(ui32Div);
+    ASSERT(ui32Div < 256);
+    ASSERT(!((ui8Mode & LCD_MODE_RASTER) && (ui32Div < 2)));
+
+    //
+    // Write the LCDCTL register to set the mode.
+    //
+    HWREG(ui32Base + LCD_O_CTL) = (uint32_t)ui8Mode |
+                                  (ui32Div << LCD_CTL_CLKDIV_S);
+
+    //
+    // Return the selected clock rate.  Finding ui32Div set to 0 should not
+    // happen unless someone passed pathological arguments and builds without
+    // the ASSERTS, but we guard against it just in case.
+    //
+    return(ui32Div ? (ui32SysClk / ui32Div) : ui32SysClk);
+}
+
+//*****************************************************************************
+//
+//! Resets one or more of the LCD controller clock domains.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32Clocks defines the subset of clock domains to be reset.
+//!
+//! This function allows sub-modules of the LCD controller to be reset under
+//! software control.  The \e ui32Clocks parameter is the logical OR of the
+//! following clocks:
+//!
+//! - \b LCD_CLOCK_MAIN causes the entire LCD controller module to be reset.
+//! - \b LCD_CLOCK_DMA causes the DMA controller submodule to be reset.
+//! - \b LCD_CLOCK_LIDD causes the LIDD submodule to be reset.
+//! - \b LCD_CLOCK_CORE causes the core module, including the raster logic to
+//! be reset.
+//!
+//! In all cases, LCD controller register values are preserved across these
+//! resets.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32Clocks & ~(LCD_CLOCK_MAIN | LCD_CLOCK_LIDD | LCD_CLOCK_DMA |
+                            LCD_CLOCK_CORE)));
+
+    //
+    // Reset the required LCD controller sub-module(s).
+    //
+    HWREG(LCD0_BASE + 0x70) = ui32Clocks;
+
+    //
+    // Wait a while.
+    //
+    SysCtlDelay(10);
+
+    //
+    // Remove software reset.
+    //
+    HWREG(LCD0_BASE + 0x70) = 0x00000000;
+
+    //
+    // Wait a while.
+    //
+    SysCtlDelay(10);
+}
+
+//*****************************************************************************
+//
+//! Sets the LCD controller communication parameters when in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32Config defines the display interface configuration.
+//!
+//! This function is used when the LCD controller is configured in LIDD
+//! mode and specifies the configuration of the interface between the
+//! controller and the display panel.  The \e ui32Config parameter is
+//! comprised of one of the following modes:
+//!
+//! - \b LIDD_CONFIG_SYNC_MPU68 selects Sync MPU68 mode.  LCDCP = EN, LCDLP =
+//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK.
+//! - \b LIDD_CONFIG_ASYNC_MPU68 selects Async MPU68 mode.  LCDCP = EN, LCDLP =
+//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1.
+//! - \b LIDD_CONFIG_SYNC_MPU80 selects Sync MPU80 mode.  LCDCP = RS, LCDLP =
+//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK.
+//! - \b LIDD_CONFIG_ASYNC_MPU80 selects Async MPU80 mode.  LCDCP = RS, LCDLP =
+//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1.
+//! - \b LIDD_CONFIG_ASYNC_HITACHI selects Hitachi (async) mode.  LCDCP = N/C,
+//! LCDLP = DIR, LCDFP = ALE, LCDAC = E0, LCDMCLK = E1.
+//!
+//! Additional flags may be ORed into \e ui32Config to control the polarities
+//! of various control signals:
+//!
+//! - \b LIDD_CONFIG_INVERT_ALE - Address Latch Enable (ALE) polarity control.
+//! By default, ALE is active low.  If this flag is set, it becomes active
+//! high.
+//! - \b LIDD_CONFIG_INVERT_RS_EN - Read Strobe/Enable polarity control.  By
+//! default, RS is active low and Enable is active high. If this flag is set,
+//! RS becomes active high and Enable active low.
+//! - \b LIDD_CONFIG_INVERT_WS_DIR - Write Strobe/Direction polarity control.
+//! By default, WS is active low and Direction write low/read high. If this
+//! flag is set, WS becomes active high and Direction becomes write high/read
+//! low.
+//! - \b LIDD_CONFIG_INVERT_CS0 - Chip Select 0/Enable 0 polarity control.  By
+//! default, CS0 and E0 are active high.  If this flag is set, they become
+//! active low.
+//! - \b LIDD_CONFIG_INVERT_CS1 - Chip Select 1/Enable 1 polarity control.  By
+//! default, CS1 and E1 are active high.  If this flag is set, they become
+//! active low.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32Config & ~(LIDD_CONFIG_SYNC_MPU68 | LIDD_CONFIG_ASYNC_MPU68 |
+                            LIDD_CONFIG_SYNC_MPU80 | LIDD_CONFIG_ASYNC_MPU80 |
+                            LIDD_CONFIG_ASYNC_HITACHI |
+                            LIDD_CONFIG_INVERT_ALE |
+                            LIDD_CONFIG_INVERT_RS_EN |
+                            LIDD_CONFIG_INVERT_WS_DIR |
+                            LIDD_CONFIG_INVERT_CS0 | LIDD_CONFIG_INVERT_CS1)));
+
+    //
+    // Write the LIDD Control Register.
+    //
+    HWREG(ui32Base + LCD_O_LIDDCTL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the LCD controller interface timing when in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select whose timings are to be set.
+//! \param pTiming points to a structure containing the desired timing
+//! parameters.
+//!
+//! This function is used in LIDD mode to set the setup, strobe and hold times
+//! for the various interface control signals.  Independent timings are stored
+//! for each of the two supported chip selects offered by the LCD controller.
+//!
+//! For a definition of the timing parameters required, see the definition of
+//! tLCDIDDTiming.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS,
+                const tLCDIDDTiming *pTiming)
+{
+    uint32_t ui32Val;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+    ASSERT(pTiming);
+    ASSERT(pTiming->ui8WSSetup < 32);
+    ASSERT(pTiming->ui8WSDuration && (pTiming->ui8WSDuration < 64));
+    ASSERT(pTiming->ui8WSHold && (pTiming->ui8WSHold < 16));
+    ASSERT(pTiming->ui8RSSetup < 32);
+    ASSERT(pTiming->ui8RSDuration && (pTiming->ui8RSDuration < 64));
+    ASSERT(pTiming->ui8RSHold && (pTiming->ui8RSHold < 16));
+    ASSERT(pTiming->ui8DelayCycles && (pTiming->ui8DelayCycles < 5));
+
+    //
+    // Convert the timings provided into a value ready for the register.
+    //
+    ui32Val =
+        (((uint32_t)(pTiming->ui8WSSetup) << LCD_LIDDCS0CFG_WRSU_S) |
+         ((uint32_t)(pTiming->ui8WSDuration) << LCD_LIDDCS0CFG_WRDUR_S) |
+         ((uint32_t)(pTiming->ui8WSHold) << LCD_LIDDCS0CFG_WRHOLD_S) |
+         ((uint32_t)(pTiming->ui8RSSetup) << LCD_LIDDCS0CFG_RDSU_S) |
+         ((uint32_t)(pTiming->ui8RSDuration) << LCD_LIDDCS0CFG_RDDUR_S) |
+         ((uint32_t)(pTiming->ui8RSHold) << LCD_LIDDCS0CFG_RDHOLD_S) |
+         ((uint32_t)(pTiming->ui8DelayCycles - 1) << LCD_LIDDCS0CFG_GAP_S));
+
+    //
+    // Write the appropriate LCD LIDD CS configuration register.
+    //
+    if(!ui32CS)
+    {
+        HWREG(ui32Base + LCD_O_LIDDCS0CFG) = ui32Val;
+    }
+    else
+    {
+        HWREG(ui32Base + LCD_O_LIDDCS1CFG) = ui32Val;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables internal DMA operation when the LCD controller is in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//!
+//! When the LCD controller is operating in LCD Interface Display Driver mode,
+//! this function must be called after completion of a DMA transaction and
+//! before calling LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(),
+//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead() to disable
+//! DMA mode and allow CPU-initiated transactions to the display.
+//!
+//! \note LIDD DMA mode is enabled automatically when LCDIDDDMAWrite() is
+//! called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIDDDMADisable(uint32_t ui32Base)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Disable DMA.
+    //
+    HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN;
+}
+
+//*****************************************************************************
+//
+//! Writes a command to the display when the LCD controller is in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//! \param ui16Cmd is the 16-bit command word to write.
+//!
+//! This function writes a 16-bit command word to the display when the LCD
+//! controller is in LIDD mode.  A command write occurs with the ALE signal
+//! active.
+//!
+//! This function must not be called if the LIDD interface is currently
+//! configured to expect DMA transactions.  If DMA was previously used to
+//! write to the panel, LCDIDDDMADisable() must be called before this function
+//! can be used.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Cmd)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+
+    //
+    // Determine the register to write based on the CS value supplied.
+    //
+    ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;
+
+    //
+    // Write the command/address to the register.
+    //
+    HWREG(ui32Base + ui32Reg) = ui16Cmd;
+}
+
+//*****************************************************************************
+//
+//! Writes a data value to the display when the LCD controller is in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//! \param ui16Data is the 16-bit data word to write.
+//!
+//! This function writes a 16-bit data word to the display when the LCD
+//! controller is in LIDD mode.  A data write occurs with the ALE signal
+//! inactive.
+//!
+//! This function must not be called if the LIDD interface is currently
+//! configured to expect DMA transactions.  If DMA was previously used to
+//! write to the panel, LCDIDDDMADisable() must be called before this function
+//! can be used.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Data)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+
+    //
+    // Determine the register to write based on the CS value supplied.
+    //
+    ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;
+
+    //
+    // Write the data value to the register.
+    //
+    HWREG(ui32Base + ui32Reg) = ui16Data;
+}
+
+//*****************************************************************************
+//
+//! Writes data to a given display register when the LCD controller is in LIDD
+//! mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//! \param ui16Addr is the address of the display register to write.
+//! \param ui16Data is the data to write.
+//!
+//! This function writes a 16-bit data word to a register in the display when
+//! the LCD controller is in LIDD mode and configured to use either the
+//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or
+//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes
+//! that employ an external address latch.
+//!
+//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this
+//! function should not be used.  In this case the functions
+//! LCDIDDCommandWrite() and LCDIDDDataWrite() may be used to transfer
+//! command and data bytes to the panel.
+//!
+//! This function must not be called if the LIDD interface is currently
+//! configured to expect DMA transactions.  If DMA was previously used to
+//! write to the panel, LCDIDDDMADisable() must be called before this function
+//! can be used.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr,
+                   uint16_t ui16Data)
+{
+    uint32_t ui32Addr;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+
+    //
+    // Determine the address register to write.
+    //
+    ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;
+
+    //
+    // Write the address.
+    //
+    HWREG(ui32Base + ui32Addr) = ui16Addr;
+
+    //
+    // Determine the data register to write.
+    //
+    ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;
+
+    //
+    // Write the data.
+    //
+    HWREG(ui32Base + ui32Addr) = ui16Data;
+}
+
+//*****************************************************************************
+//
+//! Reads a status word from the display when the LCD controller is in LIDD
+//! mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//!
+//! This function reads the 16-bit status word from the display when the LCD
+//! controller is in LIDD mode.  A status read occurs with the ALE signal
+//! active.  If the interface is configured in Hitachi mode (\b
+//! LIDD_CONFIG_ASYNC_HITACHI), this operation corresponds to a command mode
+//! read.
+//!
+//! This function must not be called if the LIDD interface is currently
+//! configured to expect DMA transactions.  If DMA was previously used to
+//! write to the panel, LCDIDDDMADisable() must be called before this function
+//! can be used.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return Returns the status word read from the display panel.
+//
+//*****************************************************************************
+uint16_t
+LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+
+    //
+    // Determine the register to read based on the CS value supplied.
+    //
+    ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;
+
+    //
+    // Read the relevant status register.
+    //
+    return((uint16_t)HWREG(ui32Base + ui32Reg));
+}
+
+//*****************************************************************************
+//
+//! Reads a data word from the display when the LCD controller is in LIDD
+//! mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//!
+//! This function reads the 16-bit data word from the display when the LCD
+//! controller is in LIDD mode.  A data read occurs with the ALE signal
+//! inactive.
+//!
+//! This function must not be called if the LIDD interface is currently
+//! configured to expect DMA transactions.  If DMA was previously used to
+//! write to the panel, LCDIDDDMADisable() must be called before this function
+//! can be used.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return Returns the status word read from the display panel.
+//
+//*****************************************************************************
+uint16_t
+LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS)
+{
+    uint32_t ui32Reg;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+
+    //
+    // Determine the register to read based on the CS value supplied.
+    //
+    ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;
+
+    //
+    // Read the relevant data register.
+    //
+    return((uint16_t)HWREG(ui32Base + ui32Reg));
+}
+
+//*****************************************************************************
+//
+//! Reads a given display register when the LCD controller is in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//! \param ui16Addr is the address of the display register to read.
+//!
+//! This function reads a 16-bit word from a register in the display when
+//! the LCD controller is in LIDD mode and configured to use either the
+//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or
+//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes
+//! that employ an external address latch.
+//!
+//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this
+//! function should not be used.  In this case, the functions
+//! LCDIDDStatusRead() and LCDIDDDataRead() may be used to read status
+//! and data bytes from the panel.
+//!
+//! This function must not be called if the LIDD interface is currently
+//! configured to expect DMA transactions.  If DMA was previously used to
+//! write to the panel, LCDIDDDMADisable() must be called before this function
+//! can be used.
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint16_t
+LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr)
+{
+    uint32_t ui32Addr;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+
+    //
+    // Determine the address register to write.
+    //
+    ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;
+
+    //
+    // Write the address.
+    //
+    HWREG(ui32Base + ui32Addr) = ui16Addr;
+
+    //
+    // Determine the data register to read.
+    //
+    ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;
+
+    //
+    // Return the data read.
+    //
+    return((uint16_t)HWREG(ui32Base + ui32Addr));
+}
+
+//*****************************************************************************
+//
+//! Writes a block of data to the display using DMA when the LCD controller is
+//! in LIDD mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1.
+//! \param pui32Data is the address of the first 16-bit word to write.  This
+//! address must be aligned on a 32-bit word boundary.
+//! \param ui32Count is the number of 16-bit words to write.  This value must
+//! be a multiple of 2.
+//!
+//! This function writes a block of 16-bit data words to the display using
+//! DMA.  It is only valid when the LCD controller is in LIDD mode.
+//! Completion of the DMA transfer is signaled by the \b
+//! LCD_INT_DMA_DONE interrupt.
+//!
+//! This function enables DMA mode prior to starting the transfer.  The
+//! caller is responsible for ensuring that any earlier DMA transfer has
+//! completed before initiating another transfer.
+//!
+//! During the time that DMA is enabled, none of the other LCD LIDD data
+//! transfer functions may be called.  When the DMA transfer is complete and
+//! the application wishes to use the CPU to communicate with the display,
+//! LCDIDDDMADisable() must be called to disable DMA access prior to calling
+//! LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(),
+//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead().
+//!
+//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80
+//! modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, const uint32_t *pui32Data,
+               uint32_t ui32Count)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32CS == 0) || (ui32CS == 1));
+    ASSERT(!((uint32_t)pui32Data & 3));
+    ASSERT(!(ui32Count & 1));
+
+    //
+    // Make sure DMA is disabled so that enabling it triggers this new
+    // transfer.
+    //
+    HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN;
+
+    //
+    // Set up the transfer.  Note that the ceiling register must contain the
+    // address of the last word which contains data we want transfered and NOT
+    // the first location after the data we want written.
+    //
+    HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Data;
+    HWREG(ui32Base + LCD_O_DMACAFB0) = ((uint32_t)pui32Data +
+                                        (ui32Count * 2) - 4);
+
+    //
+    // Tell the controller which CS to use for the DMA transaction.
+    //
+    if(!ui32CS)
+    {
+        //
+        // Use CS0.
+        //
+        HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMACS;
+    }
+    else
+    {
+        //
+        // Use CS1.
+        //
+        HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMACS;
+    }
+
+    //
+    // Enable the DMA engine and start the transaction.
+    //
+    HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMAEN;
+}
+
+//*****************************************************************************
+//
+//! Sets the LCD controller interface timing when in raster mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param ui32Config specifies properties of the raster interface and the
+//! attached display panel.
+//! \param ui8PalLoadDelay specifies the number of system clocks to wait
+//! between each 16 halfword (16-bit) burst when loading the palette from
+//! SRAM into the internal palette RAM of the controller.
+//!
+//! This function configures the basic operating mode of the raster interface
+//! and specifies the type of panel that the controller is to drive.
+//!
+//! The \e ui32Config parameter must be defined as one of the following to
+//! select the required target panel type and output pixel format:
+//!
+//! - \b RASTER_FMT_ACTIVE_24BPP_PACKED selects an active matrix display
+//! and uses a packed 24-bit per pixel packet frame buffer where 4 pixels
+//! are described within 3 consecutive 32-bit words.
+//! - \b RASTER_FMT_ACTIVE_24BPP_UNPACKED selects an active matrix display
+//! and uses an unpacked 24-bit per pixel packet frame buffer where each
+//! 32-bit word contains a single pixel and 8 bits of padding.
+//! - \b RASTER_FMT_ACTIVE_16BPP selects an active matrix display
+//! and uses a 16-bit per pixel frame buffer with 2 pixels in each 32-bit
+//! word.
+//! - \b RASTER_FMT_ACTIVE_PALETTIZED_12BIT selects an active matrix display
+//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup.  Output color
+//! data is described in 12-bit format using bits 11:0 of the data bus.  The
+//! frame buffer pixel format is defined by the value passed in the \e ui32Type
+//! parameter to LCDRasterPaletteSet().
+//! - \b RASTER_FMT_ACTIVE_PALETTIZED_16BIT selects an active matrix display
+//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup.  Output color
+//! data is described in 16-bit 5:6:5 format.  The frame buffer pixel format is
+//! defined by the value passed in the \e ui32Type parameter to
+//! LCDRasterPaletteSet().
+//! - \b RASTER_FMT_PASSIVE_MONO_4PIX selects a monochrome, passive matrix
+//! display that outputs 4 pixels on each pixel clock.
+//! - \b RASTER_FMT_PASSIVE_MONO_8PIX selects a monochrome, passive matrix
+//! display that outputs 8 pixels on each pixel clock.
+//! - \b RASTER_FMT_PASSIVE_COLOR_12BIT selects a passive matrix display
+//! and uses a 12bpp frame buffer.  The palette is bypassed and 12-bit pixel
+//! data is sent to the grayscaler for the display.
+//! - \b RASTER_FMT_PASSIVE_COLOR_16BIT selects a passive matrix display
+//! and uses a 16bpp frame buffer with pixels in 5:6:5 format.  Only the 4
+//! most significant bits of each color component are sent to the grayscaler
+//! for the display.
+//!
+//! Additionally, the following flags may be ORed into \e ui32Config:
+//!
+//! - \b RASTER_ACTVID_DURING_BLANK sets Actvid to toggle during vertical
+//! blanking.
+//! - \b RASTER_NIBBLE_MODE_ENABLED enables nibble mode.  This parameter works
+//! with \b RASTER_READ_ORDER_REVERSED to determine how 1, 2 and 4bpp pixels
+//! are extracted from words read from the frame buffer.  If specified, words
+//! read from the frame buffer are byte swapped prior to individual pixels
+//! being parsed from them.
+//! - \b RASTER_LOAD_DATA_ONLY tells the controller to read only pixel data
+//! from the frame buffer and to use the last palette read.  No palette load
+//! is performed.
+//! - \b RASTER_LOAD_PALETTE_ONLY tells the controller to read only the palette
+//! data from the frame buffer.
+//! - \b RASTER_READ_ORDER_REVERSED when using 1, 2, 4 and 8bpp frame buffers,
+//! this option reverses the order in which frame buffer words are parsed.
+//! When this option is specified, the leftmost pixel in a word is taken from
+//! the most significant bits.  When absent, the leftmost pixel is parsed from
+//! the least significant bits.
+//!
+//! If the LCD controller's raster engine is enabled when this function is
+//! called, it is disabled as a result of the call.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                   uint8_t ui8PalLoadDelay)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32Config & ~(RASTER_FMT_ACTIVE_24BPP_PACKED |
+                            RASTER_FMT_ACTIVE_24BPP_UNPACKED |
+                            RASTER_FMT_ACTIVE_PALETTIZED_12BIT |
+                            RASTER_FMT_ACTIVE_PALETTIZED_16BIT |
+                            RASTER_FMT_PASSIVE_MONO_4PIX |
+                            RASTER_FMT_PASSIVE_MONO_8PIX |
+                            RASTER_FMT_PASSIVE_PALETTIZED |
+                            RASTER_FMT_PASSIVE_COLOR_12BIT |
+                            RASTER_FMT_PASSIVE_COLOR_16BIT |
+                            RASTER_ACTVID_DURING_BLANK |
+                            RASTER_NIBBLE_MODE_ENABLED |
+                            RASTER_LOAD_DATA_ONLY |
+                            RASTER_LOAD_PALETTE_ONLY |
+                            RASTER_READ_ORDER_REVERSED)));
+
+    //
+    // Write the raster control register.
+    //
+    HWREG(ui32Base + LCD_O_RASTRCTL) = (ui32Config |
+                                        ((uint32_t)ui8PalLoadDelay <<
+                                         LCD_RASTRCTL_REQDLY_S));
+}
+
+//*****************************************************************************
+//
+//! Sets the LCD controller interface timing when in raster mode.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param pTiming points to a structure containing the desired timing
+//! parameters.
+//!
+//! This function is used in raster mode to set the panel size and sync timing
+//! parameters.
+//!
+//! For a definition of the timing parameters required, see the definition of
+//! tLCDRasterTiming.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+LCDRasterTimingSet(uint32_t ui32Base, const tLCDRasterTiming *pTiming)
+{
+    uint32_t ui32T0, ui32T1, ui32T2;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(pTiming);
+    ASSERT(!(pTiming->ui32Flags & ~(RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK |
+                                    RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK |
+                                    RASTER_TIMING_SYNCS_ON_RISING_PIXCLK |
+                                    RASTER_TIMING_ACTIVE_LOW_OE |
+                                    RASTER_TIMING_ACTIVE_LOW_PIXCLK |
+                                    RASTER_TIMING_ACTIVE_LOW_HSYNC |
+                                    RASTER_TIMING_ACTIVE_LOW_VSYNC)));
+    ASSERT(pTiming->ui16PanelWidth && (pTiming->ui16PanelWidth <= 2048) &&
+           ((pTiming->ui16PanelWidth % 16) == 0));
+    ASSERT(pTiming->ui16PanelHeight && (pTiming->ui16PanelHeight <= 2048));
+    ASSERT(pTiming->ui16HFrontPorch && (pTiming->ui16HFrontPorch <= 1024));
+    ASSERT(pTiming->ui16HBackPorch && (pTiming->ui16HBackPorch <= 1024));
+    ASSERT(pTiming->ui16HSyncWidth && (pTiming->ui16HSyncWidth <= 1024));
+    ASSERT(pTiming->ui8VSyncWidth && (pTiming->ui8VSyncWidth <= 64));
+
+    //
+    // Construct the values we need for the three raster timing registers.
+    //
+    ui32T0 = ((uint32_t)((pTiming->ui16HBackPorch - 1) & 0xFF) <<
+              LCD_RASTRTIM0_HBP_S) |
+             ((uint32_t)((pTiming->ui16HFrontPorch - 1) & 0xFF) <<
+              LCD_RASTRTIM0_HFP_S) |
+             ((uint32_t)((pTiming->ui16HSyncWidth - 1) & 0x3F) <<
+              LCD_RASTRTIM0_HSW_S) |
+             (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x3F0) >> 4) <<
+              LCD_RASTRTIM0_PPL_S) |
+             (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x400) >> 10) <<
+              LCD_RASTRTIM0_MSBPPL_S);
+    ui32T1 = ((uint32_t)pTiming->ui8VBackPorch << LCD_RASTRTIM1_VBP_S) |
+             ((uint32_t)pTiming->ui8VFrontPorch << LCD_RASTRTIM1_VFP_S) |
+             ((uint32_t)((pTiming->ui8VSyncWidth - 1) & 0x3F) <<
+              LCD_RASTRTIM1_VSW_S) |
+             ((uint32_t)(pTiming->ui16PanelHeight - 1) & 0x3FF) <<
+             LCD_RASTRTIM1_LPP_S;
+    ui32T2 = pTiming->ui32Flags |
+             ((((pTiming->ui16HSyncWidth - 1) & 0x3C0) >> 6) <<
+              LCD_RASTRTIM2_HSW_S) |
+             ((((pTiming->ui16PanelHeight - 1) & 0x400) >> 10) <<
+              LCD_RASTRTIM2_MSBLPP_S) |
+             ((((pTiming->ui16HBackPorch - 1) & 0x300) >> 8) <<
+              LCD_RASTRTIM2_MSBHBP_S) |
+             ((((pTiming->ui16HFrontPorch - 1) & 0x300) >> 8) <<
+              LCD_RASTRTIM2_MSBHFP_S) |
+             (pTiming->ui8ACBiasLineCount << LCD_RASTRTIM2_ACBF_S);
+
+    //
+    // Write the timing registers, taking care to preserve any existing value
+    // in the AC Bias interrupt field of RASTRTIM2.
+    //
+    HWREG(ui32Base + LCD_O_RASTRTIM0) = ui32T0;
+    HWREG(ui32Base + LCD_O_RASTRTIM1) = ui32T1;
+    HWREG(ui32Base + LCD_O_RASTRTIM2) = (HWREG(ui32Base + LCD_O_RASTRTIM2) &
+                                         LCD_RASTRTIM2_ACBI_M) | ui32T2;
+}
+
+//*****************************************************************************
+//
+//! Sets the number of AC bias pin transitions per interrupt.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8Count is the number of AC bias pin transitions to count before
+//! the AC bias count interrupt is asserted.  Valid values are from 0 to 15.
+//!
+//! This function is used to set the number of AC bias transitions between
+//! each AC bias count interrupt (\b LCD_INT_AC_BIAS_CNT).  If \e ui8Count is
+//! 0, no AC bias count interrupt is generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count)
+{
+    uint32_t ui32Val;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(ui8Count < 16);
+
+    //
+    // Get the existing raster timing 2 register value and mask in the new
+    // AC Bias interrupt count.
+    //
+    ui32Val = HWREG(ui32Base + LCD_O_RASTRTIM2);
+    ui32Val &= ~LCD_RASTRTIM2_ACBI_M;
+    ui32Val |= ((ui8Count << LCD_RASTRTIM2_ACBI_S) & LCD_RASTRTIM2_ACBI_M);
+
+    //
+    // Write the new value back to the register.
+    //
+    HWREG(ui32Base + LCD_O_RASTRTIM2) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! Enables the raster output.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function enables the LCD controller raster output and starts
+//! displaying the content of the current frame buffer on the attached panel.
+//! Prior to enabling the raster output, LCDModeSet(), LCDRasterConfigSet(),
+//! LCDDMAConfigSet(), LCDRasterTimingSet(), LCDRasterPaletteSet() and
+//! LCDRasterFrameBufferSet() must have been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterEnable(uint32_t ui32Base)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Reset the module prior to starting the raster.  This is required to
+    // ensure correct operation of the raster engine.
+    //
+    LCDClockReset(ui32Base, LCD_CLOCK_MAIN);
+
+    //
+    // Enable the raster engine.
+    //
+    HWREG(ui32Base + LCD_O_RASTRCTL) |= LCD_RASTRCTL_LCDEN;
+}
+
+//*****************************************************************************
+//
+//! Determines whether or not the raster output is currently enabled.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be used to query whether or not the raster output is
+//! currently enabled.
+//!
+//! \return Returns \b true if the raster is enabled or \b false if it is
+//! disabled.
+//
+//*****************************************************************************
+bool
+LCDRasterEnabled(uint32_t ui32Base)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Return the current raster engine status.
+    //
+    return((HWREG(ui32Base + LCD_O_RASTRCTL) & LCD_RASTRCTL_LCDEN) ?
+           true : false);
+}
+
+//*****************************************************************************
+//
+//! Disables the raster output.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function disables the LCD controller raster output and stops driving
+//! the attached display.
+//!
+//! \note Once disabled, the raster engine continues to scan data until the
+//! end of the current frame. If the display is to be re-enabled, wait until
+//! after the final \b LCD_INT_RASTER_FRAME_DONE has been received, indicating
+//! that the raster engine has stopped.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterDisable(uint32_t ui32Base)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Disable the raster engine.
+    //
+    HWREG(ui32Base + LCD_O_RASTRCTL) &= ~LCD_RASTRCTL_LCDEN;
+}
+
+//*****************************************************************************
+//
+//! Sets the position and size of the subpanel on the raster display.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Flags may be either \b LCD_SUBPANEL_AT_TOP to show frame buffer
+//! image data in the top portion of the display and default color in the
+//! bottom portion, or \b LCD_SUBPANEL_AT_BOTTOM to show image data at the
+//! bottom of the display and default color at the top.
+//! \param ui32BottomLines defines the number of lines comprising the bottom
+//! portion of the display.  If \b LCD_SUBPANEL_AT_TOP is set in \e ui32Flags,
+//! these lines contain the default pixel color when the subpanel is
+//! enabled, otherwise they contain image data.
+//! \param ui32DefaultPixel is the 24-bit RGB color to show in the portion of
+//! the display not configured to show image data.
+//!
+//! The LCD controller provides a feature that allows a portion of the display
+//! to be filled with a default color rather than image data from the frame
+//! buffer. This feature reduces SRAM bandwidth requirements because no data
+//! is fetched for lines containing the default color.  This feature is only
+//! available when the LCD controller is in raster mode and configured to drive
+//! an active matrix display.
+//!
+//! The subpanel area containing image data from the frame buffer may be
+//! positioned either at the top or bottom of the display as controlled by
+//! the value of \e ui32Flags.  The height of the bottom portion of the display
+//! is defined by \e ui32BottomLines.
+//!
+//! When a subpanel is configured, the application must also reconfigure the
+//! frame buffer to ensure that it contains the correct number of lines for
+//! the subpanel size in use.  This configuration can be achieved by calling
+//! LCDRasterFrameBufferSet() with the \e ui32NumBytes parameter set
+//! appropriately to describe the required number of active video lines in
+//! the subpanel area.
+//!
+//! The subpanel display mode is not enabled using this function.  To enable
+//! the subpanel once it has been configured, call LCDRasterSubPanelEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags,
+                           uint32_t ui32BottomLines, uint32_t ui32DefaultPixel)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT((ui32Flags == LCD_SUBPANEL_AT_TOP) ||
+           (ui32Flags == LCD_SUBPANEL_AT_BOTTOM));
+    ASSERT(ui32BottomLines && (ui32BottomLines <= 2048));
+
+    //
+    // Adjust the line count into the 0-2047 range.
+    //
+    ui32BottomLines--;
+
+    //
+    // Set the first subpanel configuration register, taking care to leave the
+    // subpanel enabled if it already was.
+    //
+    HWREG(ui32Base + LCD_O_RASTRSUBP1) = (HWREG(ui32Base + LCD_O_RASTRSUBP1) &
+                                          LCD_RASTRSUBP1_SPEN) | ui32Flags |
+                                         ((ui32DefaultPixel & 0xFFFF) <<
+                                          LCD_RASTRSUBP1_DPDLSB_S) |
+                                         ((ui32BottomLines <<
+                                           LCD_RASTRSUBP1_LPPT_S) &
+                                          LCD_RASTRSUBP1_LPPT_M);
+
+    //
+    // Set the second subpanel configuration register.
+    //
+    HWREG(ui32Base + LCD_O_RASTRSUBP2) =
+        ((ui32DefaultPixel >> 16) & LCD_RASTRSUBP2_DPDMSB_M) |
+        (((ui32BottomLines >> LCD_RASTRSUBP1_LPPT_S) & 1) << 8);
+}
+
+//*****************************************************************************
+//
+//! Enables subpanel display mode.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function enables subpanel display mode and displays a default color
+//! rather than image data in the number of lines and at the position specified
+//! by a previous call to LCDRasterSubPanelConfigSet().  Prior to calling
+//! LCDRasterSubPanelEnable(), the frame buffer should have been reconfigured
+//! to match the desired subpanel size using a call to
+//! LCDRasterFrameBufferSet().
+//!
+//! Subpanel display is only possible when the LCD controller is in raster
+//! mode and is configured to drive an active matrix display.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterSubPanelEnable(uint32_t ui32Base)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Enable the subpanel.
+    //
+    HWREG(ui32Base + LCD_O_RASTRSUBP1) |= LCD_RASTRSUBP1_SPEN;
+}
+
+//*****************************************************************************
+//
+//! Disables subpanel display mode.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function disables subpanel display mode and reverts to showing the
+//! entire frame buffer image on the display.  After the subpanel is disabled,
+//! the frame buffer size must be reconfigured to match the full dimensions of
+//! the display area by calling LCDRasterFrameBufferSet() with an appropriate
+//! value for the \e ui32NumBytes parameter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterSubPanelDisable(uint32_t ui32Base)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Disable the subpanel.
+    //
+    HWREG(ui32Base + LCD_O_RASTRSUBP1) &= ~LCD_RASTRSUBP1_SPEN;
+}
+
+//*****************************************************************************
+//
+//! Configures the LCD controller's internal DMA engine.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Config provides flags defining the desired DMA parameters.
+//!
+//! This function is used to configure the DMA engine within the LCD
+//! controller.  This engine is responsible for performing bulk data transfers
+//! to the display when in LIDD mode or for transferring palette and pixel data
+//! from SRAM to the display panel when in raster mode.
+//!
+//! The \e ui32Config parameter is a logical OR of various flags. It must
+//! contain one value from each of the following groups.
+//!
+//! The first group of flags set the number of words that have to be in the
+//! FIFO before it signals that it is ready:
+//!
+//! - \b LCD_DMA_FIFORDY_8_WORDS
+//! - \b LCD_DMA_FIFORDY_16_WORDS
+//! - \b LCD_DMA_FIFORDY_32_WORDS
+//! - \b LCD_DMA_FIFORDY_64_WORDS
+//! - \b LCD_DMA_FIFORDY_128_WORDS
+//! - \b LCD_DMA_FIFORDY_256_WORDS
+//! - \b LCD_DMA_FIFORDY_512_WORDS
+//!
+//! The second group of flags set the number of 32-bit words in each DMA burst
+//! transfer:
+//!
+//! - \b LCD_DMA_BURST_1
+//! - \b LCD_DMA_BURST_2
+//! - \b LCD_DMA_BURST_4
+//! - \b LCD_DMA_BURST_8
+//! - \b LCD_DMA_BURST_16
+//!
+//! The final group of flags set internal byte lane controls and allow byte
+//! swapping within the DMA engine.  The label represents the output byte order
+//! for an input 32-bit word ordered ``0123''.
+//!
+//! - \b LCD_DMA_BYTE_ORDER_0123
+//! - \b LCD_DMA_BYTE_ORDER_1023
+//! - \b LCD_DMA_BYTE_ORDER_3210
+//! - \b LCD_DMA_BYTE_ORDER_2301
+//!
+//! Additionally, \b LCD_DMA_PING_PONG may be specified.  This flag configures
+//! the controller to operate in double-buffered mode.  When data is scanned
+//! out from the first frame buffer, the DMA engine immediately moves to
+//! the second frame buffer and scans from there before moving back to the
+//! first.  If this flag is clear, the DMA engine uses a single frame buffer,
+//! restarting the scan from the beginning of the buffer each time it completes
+//! a frame.
+//!
+//! \note DMA burst size \b LCD_DMA_BURST_16 should be set when using frame
+//! buffers in external, EPI-connected memory.  Using a smaller burst size in
+//! this case is likely to result in occasional FIFO underflows and associated
+//! display glitches.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32Config & ~(LCD_DMACTL_FIFORDY_M | LCD_DMACTL_BURSTSZ_M |
+                            LCD_DMACTL_BYTESWAP | LCD_DMACTL_BIGDEND |
+                            LCD_DMACTL_FMODE)));
+
+    //
+    // Write the DMA control register.
+    //
+    HWREG(ui32Base + LCD_O_DMACTL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Initializes the color palette in a frame buffer.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32Type specifies the type of pixel data to be held in the frame
+//! buffer and also the format of the source color values passed.
+//! \param pui32Addr points to the start of the frame buffer into which the
+//! palette information is to be written.
+//! \param pui32SrcColors points to the first color value that is to be
+//! written into the frame buffer palette.
+//! \param ui32Start specifies the index of the first color in the palette
+//! to update.
+//! \param ui32Count specifies the number of source colors to be copied into
+//! the frame buffer palette.
+//!
+//! This function is used to initialize the color palette stored at the
+//! beginning of a frame buffer.  It writes the relevant pixel type into the
+//! first entry of the frame buffer and copies the requested number of colors
+//! from a source buffer into the palette starting at the required index,
+//! optionally converting them from 24-bit color format into the 12-bit format
+//! used by the LCD controller.
+//!
+//! \e ui32Type must be set to one of the following values to indicate the
+//! type of frame buffer for which the palette is being initialized:
+//!
+//! - \b LCD_PALETTE_TYPE_1BPP indicates a 1 bit per pixel
+//! (monochrome) frame buffer.  This format requires a 2 entry palette.
+//! - \b LCD_PALETTE_TYPE_2BPP indicates a 2 bit per pixel frame
+//! buffer. This format requires a 4 entry palette.
+//! - \b LCD_PALETTE_TYPE_4BPP indicates a 4 bit per pixel frame
+//! buffer. This format requires a 4 entry palette.
+//! - \b LCD_PALETTE_TYPE_8BPP indicates an 8 bit per pixel frame
+//! buffer. This format requires a 256 entry palette.
+//! - \b LCD_PALETTE_TYPE_DIRECT indicates a direct color (12, 16 or
+//! 24 bit per pixel).  The color palette is not used in these modes, but the
+//! frame buffer type must still be initialized to ensure that the hardware
+//! uses the correct pixel type.  When this value is used, the format of the
+//! pixels in the frame buffer is defined by the \e ui32Config parameter
+//! previously passed to LCDRasterConfigSet().
+//!
+//! Optionally, the \b LCD_PALETTE_SRC_24BIT flag may be ORed into \e ui32Type
+//! to indicate that the supplied colors in the \e pui32SrcColors array are in
+//! the 24-bit format as used by the TivaWare Graphics Library with one color
+//! stored in each 32-bit word.  In this case, the colors read from the source
+//! array are converted to the 12-bit format used by the LCD controller before
+//! being written into the frame buffer palette.
+//!
+//! If \b LCD_PALETTE_SRC_24BIT is not present, it is assumed that the
+//! \e pui32SrcColors array contains 12-bit colors in the format required by
+//! the LCD controller with 2 colors stored in each 32-bit word.  In this case,
+//! the values are copied directly into the frame buffer palette without any
+//! reformatting.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, uint32_t *pui32Addr,
+                    const uint32_t *pui32SrcColors, uint32_t ui32Start,
+                    uint32_t ui32Count)
+{
+    uint16_t *pui16Pal;
+    uint16_t *pui16Src;
+    uint32_t ui32Loop;
+
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(ui32Start < 256);
+    ASSERT((ui32Start + ui32Count) <= 256);
+    ASSERT(pui32Addr);
+    ASSERT((pui32SrcColors) || (ui32Count == 0));
+    ASSERT(!(ui32Type & ~(LCD_PALETTE_SRC_24BIT | LCD_PALETTE_TYPE_DIRECT |
+                          LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_4BPP |
+                          LCD_PALETTE_TYPE_2BPP | LCD_PALETTE_TYPE_1BPP)));
+
+    //
+    // Get a pointer to the start of the palette.
+    //
+    pui16Pal = (uint16_t *)pui32Addr;
+
+    //
+    // Are we converting the palette color format?
+    //
+    if(ui32Type & LCD_PALETTE_SRC_24BIT)
+    {
+        //
+        // Yes - loop through each of the supplied 24-bit colors converting
+        // and storing each.
+        //
+        ui32Loop = 0;
+        while(ui32Count)
+        {
+            pui16Pal[ui32Start + ui32Loop] =
+                PAL_FROM_RGB(pui32SrcColors[ui32Loop]);
+            ui32Loop++;
+            ui32Count--;
+        }
+    }
+    else
+    {
+        //
+        // No - loop through the supplied 12-bit colors storing each.
+        //
+
+        pui16Src = (uint16_t *)pui32SrcColors;
+        while(ui32Count)
+        {
+            pui16Pal[ui32Start] = pui16Src[ui32Start];
+            ui32Start++;
+            ui32Count--;
+        }
+    }
+
+    //
+    // Write the pixel type into the first palette entry.
+    //
+    pui16Pal[0] &= ~(LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_DIRECT);
+    pui16Pal[0] |= (ui32Type & ~LCD_PALETTE_SRC_24BIT);
+}
+
+//*****************************************************************************
+//
+//! Sets the LCD controller frame buffer start address and size in raster mode.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8Buffer specifies which frame buffer to configure.  Valid values
+//! are 0 and 1.
+//! \param pui32Addr points to the first byte of the frame buffer.  This
+//! pointer must be aligned on a 32-bit (word) boundary.
+//! \param ui32NumBytes specifies the size of the frame buffer in bytes.  This
+//! value must be a multiple of 4.
+//!
+//! This function is used to configure the position and size of one of the
+//! two supported frame buffers while in raster mode.  The second frame buffer
+//! (configured when ui8Buffer is set to 1) is only used if the controller
+//! is set to operate in ping-pong mode (by specifying the \b LCD_DMA_PING_PONG
+//! configuration flag on a call to LCDDMAConfigSet()).
+//!
+//! The format of the frame buffer depends on the image type in use and
+//! the current raster configuration settings.  If \b RASTER_LOAD_DATA_ONLY
+//! was specified in a previous call to LCDRasterConfigSet(), the frame buffer
+//! contains only packed pixel data in the required bit depth and format.
+//! In other cases, the frame buffer comprises a palette of either 8 or 128
+//! 32-bit words followed by the packed pixel data.  The palette size is 8
+//! words (16 16-bit entries) for all pixel formats other than 8bpp which
+//! uses a palette of 128 words (256 16-bit entries).  Note that the 8 word
+//! palette is still present even for 12, 16 and 24-bit formats, which do not
+//! use the lookup table.
+//!
+//! The frame buffer size, specified using the \e ui32NumBytes parameter, must
+//! be the palette size (if any) plus the size of the image bitmap required
+//! for the currently configured display resolution.
+//!
+//! \e ui32NumBytes = (Palette Size) + ((Width * Height) * BPP) / 8)
+//!
+//! If \b RASTER_LOAD_DATA_ONLY is not specified, frame buffers passed to this
+//! function must be initialized using a call to LCDRasterPaletteSet() prior to
+//! enabling the raster output.  If this is not done, the pixel format
+//! identifier and color table required by the hardware is not present
+//! and the results are unpredictable.
+//!
+//! \return None.
+//*****************************************************************************
+void
+LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer,
+                        uint32_t *pui32Addr, uint32_t ui32NumBytes)
+{
+    //
+    // Sanity check parameters.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!((uint32_t)pui32Addr & 3));
+    ASSERT(!(ui32NumBytes & 3));
+    ASSERT(ui8Buffer < 2);
+
+    //
+    // Are we setting the values for frame buffer 0?
+    //
+    if(!ui8Buffer)
+    {
+        //
+        // Yes - set the registers for frame buffer 0.
+        //
+        HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Addr;
+        HWREG(ui32Base + LCD_O_DMACAFB0) = (uint32_t)pui32Addr +
+                                           ui32NumBytes - 4;
+    }
+    else
+    {
+        //
+        // No - set the registers for frame buffer 1.
+        //
+        HWREG(ui32Base + LCD_O_DMABAFB1) = (uint32_t)pui32Addr;
+        HWREG(ui32Base + LCD_O_DMACAFB1) = (uint32_t)pui32Addr +
+                                           ui32NumBytes - 4;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables individual LCD controller interrupt sources.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated LCD controller interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete.
+//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is
+//! complete.
+//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost.
+//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter
+//! has decremented to zero and is is valid for passive matrix panels only.
+//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded
+//! but remains disabled until this interrupt is cleared.
+//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The
+//! internal FIFO was empty when the output logic attempted to read data to
+//! send to the display.
+//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded.
+//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been
+//! signaled.
+//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been
+//! signaled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST |
+                              LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW |
+                              LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 |
+                              LCD_INT_RASTER_FRAME_DONE)));
+
+    //
+    // Enable the interrupt sources by setting the appropriate bits in the
+    // mask register.
+    //
+    HWREG(ui32Base + LCD_O_IM) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual LCD controller interrupt sources.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated LCD controller interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete.
+//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is
+//! complete.
+//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost.
+//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter
+//! has decremented to zero and is is valid for passive matrix panels only.
+//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded
+//! but remains disabled until this interrupt is cleared.
+//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The
+//! internal FIFO was empty when the output logic attempted to read data to
+//! send to the display.
+//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded.
+//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been
+//! signaled.
+//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been
+//! signaled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST |
+                              LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW |
+                              LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 |
+                              LCD_INT_RASTER_FRAME_DONE)));
+
+    //
+    // Disable the interrupt sources by clearing the appropriate bits in the
+    // mask register.
+    //
+    HWREG(ui32Base + LCD_O_IENC) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current LCD controller interrupt status.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param bMasked is false if the raw interrupt status is required and true
+//! if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the LCD controller.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status as the logical OR of any of
+//! the following:
+//!
+//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete.
+//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is
+//! complete.
+//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost.
+//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter
+//! has decremented to zero and is is valid for passive matrix panels only.
+//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded
+//! but remains disabled until this interrupt is cleared.
+//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The
+//! internal FIFO was empty when the output logic attempted to read data to
+//! send to the display.
+//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded.
+//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been
+//! signaled.
+//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been
+//! signaled.
+//
+//*****************************************************************************
+uint32_t
+LCDIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Were we asked for the masked or raw interrupt status?
+    //
+    if(bMasked)
+    {
+        //
+        // Return the masked interrupt status.
+        //
+        return(HWREG(ui32Base + LCD_O_MISCLR));
+    }
+    else
+    {
+        //
+        // Return the raw interrupts status.
+        //
+        return(HWREG(ui32Base + LCD_O_RISSET));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears LCD controller interrupt sources.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified LCD controller interrupt sources are cleared so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep the interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete.
+//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is
+//! complete.
+//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost.
+//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter
+//! has decremented to zero and is is valid for passive matrix panels only.
+//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded
+//! but remains disabled until this interrupt is cleared.
+//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The
+//! internal FIFO was empty when the output logic attempted to read data to
+//! send to the display.
+//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded.
+//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been
+//! signaled.
+//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been
+//! signaled.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST |
+                              LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW |
+                              LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 |
+                              LCD_INT_RASTER_FRAME_DONE)));
+
+    //
+    // Clear the requested interrupts.
+    //
+    HWREG(ui32Base + LCD_O_MISCLR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the LCD controller module.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//! \param pfnHandler is a pointer to the function to be called when the LCD
+//! controller interrupt occurs.
+//!
+//! This function registers the handler to be called when the LCD controller
+//! module interrupt occurs.
+//!
+//! \note This function need not be called if the appropriate interrupt vector
+//! is statically linked into the vector table in the application startup code.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+    ASSERT(pfnHandler);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_LCD0_TM4C129, pfnHandler);
+
+    //
+    // Enable the interrupt in the interrupt controller.
+    //
+    IntEnable(INT_LCD0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the LCD controller module.
+//!
+//! \param ui32Base specifies the LCD controller module base address.
+//!
+//! This function unregisters the interrupt handler and disables the global LCD
+//! controller interrupt in the interrupt controller.
+//!
+//! \note This function need not be called if the appropriate interrupt vector
+//! is statically linked into the vector table in the application startup code.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+LCDIntUnregister(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == LCD0_BASE);
+
+    //
+    // Disable the interrupt in the interrupt controller.
+    //
+    IntDisable(INT_LCD0_TM4C129);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_LCD0_TM4C129);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/lcd.h b/bsp/tm4c129x/libraries/driverlib/lcd.h
new file mode 100644
index 0000000000..d47451f2a0
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/lcd.h
@@ -0,0 +1,487 @@
+//*****************************************************************************
+//
+// lcd.h - Defines and Macros for the LCD Controller module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_LCD_H__
+#define __DRIVERLIB_LCD_H__
+
+//*****************************************************************************
+//
+//! \addtogroup lcd_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! This macro can be used to convert a 24-bit RGB color value as used by the
+//! TivaWare Graphics Library into a 12-bit LCD controller color palette
+//! entry.
+//
+//*****************************************************************************
+#define PAL_FROM_RGB(ui32RGBColor) (((ui32RGBColor & 0xF0) >> 4) |            \
+                                    ((ui32RGBColor & 0xF000) >> 8) |          \
+                                    ((ui32RGBColor & 0xF00000) >> 12))
+
+//*****************************************************************************
+//
+//! This macro can be used to convert from time in microseconds to periods of
+//! the supplied clock in Hertz as required when setting up the LIDD and raster
+//! timing structures.  The calculation will round such that the number of
+//! cycles returned represents no longer a time than specified in the
+//! ui32Time_uS parameter.  Values of ui32Time_uS less than or equal to
+//! 4294967uS (4.29 seconds) are supported by the macro.  Larger values will
+//! cause arithmetic overflow and yield incorrect values.  It is further
+//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz).
+//
+//*****************************************************************************
+#define CYCLES_FROM_TIME_US(ui32ClockFreq, ui32Time_uS)                       \
+    (((ui32Time_uS) == 0) ? 0 :                                               \
+    (((ui32ClockFreq) / 1000000) * ((((ui32Time_uS) * 1000) - 1) / 1000)) + 1)
+
+//*****************************************************************************
+//
+//! This macro can be used to convert from time in nanoseconds to periods of
+//! the supplied clock in Hertz as required when setting up the LIDD and raster
+//! timing structures.  The calculation will round such that the number of
+//! cycles returned represents no longer a time than specified in the
+//! ui32Time_nS parameter.  Values of ui32Time_nS less than or equal to
+//! 35791394 (35.79 milliseconds) are supported by the macro.  Larger values
+//! will cause arithmetic overflow and yield incorrect values.  It is further
+//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz).
+//
+//*****************************************************************************
+#define CYCLES_FROM_TIME_NS(ui32ClockFreq, ui32Time_nS)                       \
+    (((ui32Time_nS) == 0) ? 0 :                                               \
+    ((((((ui32ClockFreq) / 1000000) * ((ui32Time_nS) - 1)) / 1000)) + 1))
+
+//*****************************************************************************
+//
+//! A structure containing timing parameters for the LIDD (LCD Interface
+//! Display Driver) interface.  This is used with the LCDIDDTimingSet function.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Write Strobe Set-Up cycles.  When performing a write access, this
+    //! field defines the number of MCLK cycles that Data Bus/Pad Output
+    //! Enable, ALE, the Direction bit, and Chip Select have to be ready before
+    //! the Write Strobe is asserted.  Valid values are from 0 to 31.
+    //
+    uint8_t ui8WSSetup;
+
+    //
+    //! Write Strobe Duration cycles.  Field value defines the number of MCLK
+    //! cycles for which the Write Strobe is held active when performing a
+    //! write access.  Valid values are from 1 to 63.
+    //
+    uint8_t ui8WSDuration;
+
+    //
+    //! Write Strobe Hold cycles.  Field value defines the number of MCLK
+    //! cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit,
+    //! and Chip Select are held after the Write Strobe is deasserted when
+    //! performing a write access.  Valid values are from 1 to 15.
+    //
+    uint8_t ui8WSHold;
+
+    //
+    //! Read Strobe Set-Up cycles.  When performing a read access, this field
+    //! defines the number of MCLK cycles that Data Bus/Pad Output Enable, ALE,
+    //! the Direction bit, and Chip Select have to be ready before the Read
+    //! Strobe is asserted.  Valid values are from 0 to 31.
+    //
+    uint8_t ui8RSSetup;
+
+    //
+    //! Read Strobe Duration cycles.  Field value defines the number of MCLK
+    //! cycles for which the Read Strobe is held active when performing a read
+    //! access.  Valid values are from 1 to 63.
+    //
+    uint8_t ui8RSDuration;
+
+    //
+    //! Read Strobe Hold cycles.  Field value defines the number of MCLK cycles
+    //! for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip
+    //! Select are held after the Read Strobe is deasserted when performing a
+    //! read access.  Valid values are from 1 to 15.
+    //
+    uint8_t ui8RSHold;
+
+    //
+    //! Field value defines the number of MCLK cycles between the end of one
+    //! device access and the start of another device access using the same
+    //! Chip Select unless the two accesses are both Reads.  In this case,
+    //! this delay is not incurred.  Valid vales are from 1 to 4.
+    //
+    uint8_t ui8DelayCycles;
+}
+tLCDIDDTiming;
+
+//
+// Values which can be ORed together within the ui32Flags field of the
+// tLCDRasterTiming structure.
+//
+#define RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK                                   \
+                                0x00000000
+#define RASTER_TIMING_SYNCS_ON_RISING_PIXCLK                                  \
+                                0x02000000
+#define RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK                                 \
+                                0x03000000
+#define RASTER_TIMING_ACTIVE_HIGH_OE                                          \
+                                0x00000000
+#define RASTER_TIMING_ACTIVE_LOW_OE                                           \
+                                0x00800000
+#define RASTER_TIMING_ACTIVE_HIGH_PIXCLK                                      \
+                                0x00000000
+#define RASTER_TIMING_ACTIVE_LOW_PIXCLK                                       \
+                                0x00400000
+#define RASTER_TIMING_ACTIVE_HIGH_HSYNC                                       \
+                                0x00000000
+#define RASTER_TIMING_ACTIVE_LOW_HSYNC                                        \
+                                0x00200000
+#define RASTER_TIMING_ACTIVE_HIGH_VSYNC                                       \
+                                0x00000000
+#define RASTER_TIMING_ACTIVE_LOW_VSYNC                                        \
+                                0x00100000
+
+//
+//! A structure containing timing parameters for the raster interface.  This is
+//! used with the LCDRasterTimingSet function.
+//
+typedef struct
+{
+    //
+    //! Flags configuring the polarity and active edges of the various signals
+    //! in the raster interface.  This field is comprised of a logical OR of
+    //! the labels with prefix  ``RASTER_TIMING_''.
+    //
+    uint32_t ui32Flags;
+
+    //
+    //! The number of pixels contained within each line on the LCD display.
+    //! Valid values are multiple of 16 less than or equal to 2048.
+    //
+    uint16_t ui16PanelWidth;
+
+    //
+    //! The number of lines on the LCD display.  Valid values are from 1 to
+    //! 2048.
+    //
+    uint16_t ui16PanelHeight;
+
+    //
+    //! A value from 1 to 1024 that specifies the number of pixel clock periods
+    //! to add to the end of each line after active video has ended.
+    //
+    uint16_t ui16HFrontPorch;
+
+    //
+    //! A value from 1 to 1024 that specifies the number of pixel clock periods
+    //! to add to the beginning of a line before active video is asserted.
+    //
+    uint16_t ui16HBackPorch;
+
+    //
+    //! A value from 1 to 1024 that specifies the number of pixel clock periods
+    //! to pulse the line clock at the end of each line.
+    //
+    uint16_t ui16HSyncWidth;
+
+    //
+    //! A value from 0 to 255 that specifies the number of line clock periods
+    //! to add to the end of each frame after the last active line.
+    //
+    uint8_t ui8VFrontPorch;
+
+    //
+    //! A value from 0 to 255 that specifies the number of line clock periods
+    //! to add to the beginning of a frame before the first active line is
+    //! output to the display.
+    //
+    uint8_t ui8VBackPorch;
+
+    //
+    //! In active mode, a value from 1 to 64 that specifies the number of
+    //! line clock periods to set the lcd_fp pin active at the end of each
+    //! frame after the vertical front porch period elapses.  The number of
+    //! The frame clock is used as the VSYNC signal in active mode.
+    //!
+    //! In passive mode, a value from 1 to 64 that specifies the number of
+    //! extra line clock periods to insert after the vertical front porch
+    //! period has elapsed.  Note that the width of lcd_fp is not affected by
+    //! this value in passive mode.
+    //
+    uint8_t ui8VSyncWidth;
+
+    //
+    //! A value from 0 to 255 that specifies the number of line clocks to
+    //! count before transitioning the AC Bias pin.  This pin is used to
+    //! periodically invert the polarity of the power supply to prevent DC
+    //! charge build-up within the display.
+    //
+    uint8_t ui8ACBiasLineCount;
+}
+tLCDRasterTiming;
+
+//*****************************************************************************
+//
+// Possible values for the ui8Mode parameter to LCDModeSet().  The label
+// LCD_MODE_AUTO_UFLOW_RESTART may be ORed with either of the other two.
+//
+//*****************************************************************************
+#define LCD_MODE_LIDD           ((uint8_t)0x00)
+#define LCD_MODE_RASTER         ((uint8_t)0x01)
+#define LCD_MODE_AUTO_UFLOW_RESTART                                           \
+                                ((uint8_t)0x02)
+
+//*****************************************************************************
+//
+// Values used to construct the ui32Config parameter to LCDIDDConfigSet().
+//
+//*****************************************************************************
+#define LIDD_CONFIG_SYNC_MPU68  0x00000000
+#define LIDD_CONFIG_ASYNC_MPU68 0x00000001
+#define LIDD_CONFIG_SYNC_MPU80  0x00000002
+#define LIDD_CONFIG_ASYNC_MPU80 0x00000003
+#define LIDD_CONFIG_ASYNC_HITACHI                                             \
+                                0x00000004
+#define LIDD_CONFIG_INVERT_ALE  0x00000008
+#define LIDD_CONFIG_INVERT_RS_EN                                              \
+                                0x00000010
+#define LIDD_CONFIG_INVERT_WS_DIR                                             \
+                                0x00000020
+#define LIDD_CONFIG_INVERT_CS0  0x00000040
+#define LIDD_CONFIG_INVERT_CS1  0x00000080
+
+//*****************************************************************************
+//
+// Values used to construct the ui32Config parameter to
+// LCDRasterConfigSet().  Valid parameters contain one of the RASTER_FMT_xxx
+// labels optionally ORed with the other flags.  Only one of
+// RASTER_LOAD_DATA_ONLY and RASTER_LOAD_PALETTE_ONLY may be specified (if
+// neither is specified, the controller will load both palette and data when
+// scanning out the frame buffer).
+//
+//*****************************************************************************
+#define RASTER_FMT_ACTIVE_24BPP_PACKED                                        \
+                                0x02000080
+#define RASTER_FMT_ACTIVE_24BPP_UNPACKED                                      \
+                                0x06000080
+#define RASTER_FMT_ACTIVE_PALETTIZED_12BIT                                    \
+                                0x00000080
+#define RASTER_FMT_ACTIVE_PALETTIZED_16BIT                                    \
+                                0x00800080
+#define RASTER_FMT_PASSIVE_MONO_4PIX                                          \
+                                0x00000002
+#define RASTER_FMT_PASSIVE_MONO_8PIX                                          \
+                                0x00000202
+#define RASTER_FMT_PASSIVE_PALETTIZED                                         \
+                                0x00000000
+#define RASTER_FMT_PASSIVE_COLOR_12BIT                                        \
+                                0x00000000
+#define RASTER_FMT_PASSIVE_COLOR_16BIT                                        \
+                                0x01000000
+#define RASTER_ACTVID_DURING_BLANK                                            \
+                                0x08000000
+#define RASTER_NIBBLE_MODE_ENABLED                                            \
+                                0x00400000
+#define RASTER_LOAD_DATA_ONLY   0x00200000
+#define RASTER_LOAD_PALETTE_ONLY                                              \
+                                0x00100000
+#define RASTER_READ_ORDER_REVERSED                                            \
+                                0x00000100
+
+//*****************************************************************************
+//
+// Interrupt sources for the LCD controller.  These may be ORed together and
+// passed to LCDIntEnable(), LCDIntDisable() and LCDIntClear().  They are also
+// returned by LCDIntStatus().
+//
+//*****************************************************************************
+#define LCD_INT_DMA_DONE        0x00000001
+#define LCD_INT_RASTER_FRAME_DONE                                             \
+                                0x00000002
+#define LCD_INT_SYNC_LOST       0x00000004
+#define LCD_INT_AC_BIAS_CNT     0x00000008
+#define LCD_INT_UNDERFLOW       0x00000020
+#define LCD_INT_PAL_LOAD        0x00000040
+#define LCD_INT_EOF0            0x00000100
+#define LCD_INT_EOF1            0x00000200
+
+//*****************************************************************************
+//
+// Configuration values used with LCDDMAConfigSet().
+//
+//*****************************************************************************
+#define LCD_DMA_FIFORDY_8_WORDS 0x00000000
+#define LCD_DMA_FIFORDY_16_WORDS                                              \
+                                0x00000100
+#define LCD_DMA_FIFORDY_32_WORDS                                              \
+                                0x00000200
+#define LCD_DMA_FIFORDY_64_WORDS                                              \
+                                0x00000300
+#define LCD_DMA_FIFORDY_128_WORDS                                             \
+                                0x00000400
+#define LCD_DMA_FIFORDY_256_WORDS                                             \
+                                0x00000500
+#define LCD_DMA_FIFORDY_512_WORDS                                             \
+                                0x00000600
+#define LCD_DMA_BURST_1         0x00000010
+#define LCD_DMA_BURST_2         0x00000010
+#define LCD_DMA_BURST_4         0x00000020
+#define LCD_DMA_BURST_8         0x00000030
+#define LCD_DMA_BURST_16        0x00000040
+#define LCD_DMA_BYTE_ORDER_0123 0x00000000
+#define LCD_DMA_BYTE_ORDER_1023 0x00000008
+#define LCD_DMA_BYTE_ORDER_3210 0x00000002
+#define LCD_DMA_BYTE_ORDER_2301 0x0000000A
+#define LCD_DMA_PING_PONG       0x00000001
+
+//*****************************************************************************
+//
+// Type values used with LCDRasterPaletteSet().
+//
+//*****************************************************************************
+#define LCD_PALETTE_TYPE_1BPP   0x00000000
+#define LCD_PALETTE_TYPE_2BPP   0x00001000
+#define LCD_PALETTE_TYPE_4BPP   0x00002000
+#define LCD_PALETTE_TYPE_8BPP   0x00003000
+#define LCD_PALETTE_TYPE_DIRECT 0x00004000
+#define LCD_PALETTE_SRC_24BIT   0x80000000
+
+//*****************************************************************************
+//
+// Flags used in the ui32Clocks parameter to LCDClockReset().
+//
+//*****************************************************************************
+#define LCD_CLOCK_MAIN          0x00000008
+#define LCD_CLOCK_DMA           0x00000004
+#define LCD_CLOCK_LIDD          0x00000002
+#define LCD_CLOCK_CORE          0x00000001
+
+//*****************************************************************************
+//
+// Flags used in with LCDSubPanelConfigSet().
+//
+//*****************************************************************************
+#define LCD_SUBPANEL_AT_TOP     0x20000000
+#define LCD_SUBPANEL_AT_BOTTOM  0x00000000
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Function Prototypes.
+//
+//*****************************************************************************
+extern uint32_t LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode,
+                           uint32_t ui32PixClk, uint32_t ui32SysClk);
+extern void LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks);
+extern void LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS,
+                            const tLCDIDDTiming *pTiming);
+extern void LCDIDDDMADisable(uint32_t ui32Base);
+extern void LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS,
+                               uint16_t ui16Cmd);
+extern void LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS,
+                            uint16_t ui16Data);
+extern void LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS,
+                               uint16_t ui16Addr, uint16_t ui16Data);
+extern uint16_t LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS);
+extern uint16_t LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS);
+extern uint16_t LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS,
+                                  uint16_t ui16Addr);
+extern void LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS,
+                           const uint32_t *pui32Data, uint32_t ui32Count);
+extern void LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config,
+                               uint8_t ui8PalLoadDelay);
+extern void LCDRasterTimingSet(uint32_t ui32Base,
+                               const tLCDRasterTiming *pTiming);
+extern void LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count);
+extern void LCDRasterEnable(uint32_t ui32Base);
+extern bool LCDRasterEnabled(uint32_t ui32Base);
+extern void LCDRasterDisable(uint32_t ui32Base);
+extern void LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags,
+                                       uint32_t ui32BottomLines,
+                                       uint32_t ui32DefaultPixel);
+extern void LCDRasterSubPanelEnable(uint32_t ui32Base);
+extern void LCDRasterSubPanelDisable(uint32_t ui32Base);
+extern void LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type,
+                                uint32_t *pui32PalAddr,
+                                const uint32_t *pui32SrcColors,
+                                uint32_t ui32Start,
+                                uint32_t ui32Count);
+extern void LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer,
+                                    uint32_t *pui32Addr,
+                                    uint32_t ui32NumBytes);
+extern void LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t LCDIntStatus(uint32_t ui32Base, bool bMasked);
+extern void LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void LCDIntUnregister(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_LCD_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/mpu.c b/bsp/tm4c129x/libraries/driverlib/mpu.c
new file mode 100644
index 0000000000..e776356926
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/mpu.c
@@ -0,0 +1,459 @@
+//*****************************************************************************
+//
+// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup mpu_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/mpu.h"
+
+//*****************************************************************************
+//
+//! Enables and configures the MPU for use.
+//!
+//! \param ui32MPUConfig is the logical OR of the possible configurations.
+//!
+//! This function enables the Cortex-M memory protection unit.  It also
+//! configures the default behavior when in privileged mode and while handling
+//! a hard fault or NMI.  Prior to enabling the MPU, at least one region must
+//! be set by calling MPURegionSet() or else by enabling the default region for
+//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
+//! MPUEnable().  Once the MPU is enabled, a memory management fault is
+//! generated for memory access violations.
+//!
+//! The \e ui32MPUConfig parameter should be the logical OR of any of the
+//! following:
+//!
+//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
+//! privileged mode and when no other regions are defined.  If this option
+//! is not enabled, then there must be at least one valid region already
+//! defined when the MPU is enabled.
+//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
+//! exception handler.  If this option is not enabled, then the MPU is
+//! disabled while in one of these exception handlers and the default
+//! memory map is applied.
+//! - \b MPU_CONFIG_NONE chooses none of the above options.  In this case,
+//! no default memory map is provided in privileged mode, and the MPU is not
+//! enabled in the fault handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUEnable(uint32_t ui32MPUConfig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
+                               MPU_CONFIG_HARDFLT_NMI)));
+
+    //
+    // Set the MPU control bits according to the flags passed by the user,
+    // and also set the enable bit.
+    //
+    HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the MPU for use.
+//!
+//! This function disables the Cortex-M memory protection unit.  When the
+//! MPU is disabled, the default memory map is used and memory management
+//! faults are not generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUDisable(void)
+{
+    //
+    // Turn off the MPU enable bit.
+    //
+    HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Gets the count of regions supported by the MPU.
+//!
+//! This function is used to get the total number of regions that are supported
+//! by the MPU, including regions that are already programmed.
+//!
+//! \return The number of memory protection regions that are available
+//! for programming using MPURegionSet().
+//
+//*****************************************************************************
+uint32_t
+MPURegionCountGet(void)
+{
+    //
+    // Read the DREGION field of the MPU type register and mask off
+    // the bits of interest to get the count of regions.
+    //
+    return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >>
+           NVIC_MPU_TYPE_DREGION_S);
+}
+
+//*****************************************************************************
+//
+//! Enables a specific region.
+//!
+//! \param ui32Region is the region number to enable.
+//!
+//! This function is used to enable a memory protection region.  The region
+//! should already be configured with the MPURegionSet() function.  Once
+//! enabled, the memory protection rules of the region are applied and access
+//! violations cause a memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionEnable(uint32_t ui32Region)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Region < 8);
+
+    //
+    // Select the region to modify.
+    //
+    HWREG(NVIC_MPU_NUMBER) = ui32Region;
+
+    //
+    // Modify the enable bit in the region attributes.
+    //
+    HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables a specific region.
+//!
+//! \param ui32Region is the region number to disable.
+//!
+//! This function is used to disable a previously enabled memory protection
+//! region.  The region remains configured if it is not overwritten with
+//! another call to MPURegionSet(), and can be enabled again by calling
+//! MPURegionEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionDisable(uint32_t ui32Region)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Region < 8);
+
+    //
+    // Select the region to modify.
+    //
+    HWREG(NVIC_MPU_NUMBER) = ui32Region;
+
+    //
+    // Modify the enable bit in the region attributes.
+    //
+    HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Sets up the access rules for a specific region.
+//!
+//! \param ui32Region is the region number to set up.
+//! \param ui32Addr is the base address of the region.  It must be aligned
+//! according to the size of the region specified in ui32Flags.
+//! \param ui32Flags is a set of flags to define the attributes of the region.
+//!
+//! This function sets up the protection rules for a region.  The region has
+//! a base address and a set of attributes including the size.  The base
+//! address parameter, \e ui32Addr, must be aligned according to the size, and
+//! the size must be a power of 2.
+//!
+//! The \e ui32Flags parameter is the logical OR of all of the attributes
+//! of the region.  It is a combination of choices for region size,
+//! execute permission, read/write permissions, disabled sub-regions,
+//! and a flag to determine if the region is enabled.
+//!
+//! The size flag determines the size of a region and must be one of the
+//! following:
+//!
+//! - \b MPU_RGN_SIZE_32B
+//! - \b MPU_RGN_SIZE_64B
+//! - \b MPU_RGN_SIZE_128B
+//! - \b MPU_RGN_SIZE_256B
+//! - \b MPU_RGN_SIZE_512B
+//! - \b MPU_RGN_SIZE_1K
+//! - \b MPU_RGN_SIZE_2K
+//! - \b MPU_RGN_SIZE_4K
+//! - \b MPU_RGN_SIZE_8K
+//! - \b MPU_RGN_SIZE_16K
+//! - \b MPU_RGN_SIZE_32K
+//! - \b MPU_RGN_SIZE_64K
+//! - \b MPU_RGN_SIZE_128K
+//! - \b MPU_RGN_SIZE_256K
+//! - \b MPU_RGN_SIZE_512K
+//! - \b MPU_RGN_SIZE_1M
+//! - \b MPU_RGN_SIZE_2M
+//! - \b MPU_RGN_SIZE_4M
+//! - \b MPU_RGN_SIZE_8M
+//! - \b MPU_RGN_SIZE_16M
+//! - \b MPU_RGN_SIZE_32M
+//! - \b MPU_RGN_SIZE_64M
+//! - \b MPU_RGN_SIZE_128M
+//! - \b MPU_RGN_SIZE_256M
+//! - \b MPU_RGN_SIZE_512M
+//! - \b MPU_RGN_SIZE_1G
+//! - \b MPU_RGN_SIZE_2G
+//! - \b MPU_RGN_SIZE_4G
+//!
+//! The execute permission flag must be one of the following:
+//!
+//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
+//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
+//!
+//! The read/write access permissions are applied separately for the
+//! privileged and user modes.  The read/write access flags must be one
+//! of the following:
+//!
+//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
+//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
+//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
+//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
+//!
+//! The region is automatically divided into 8 equally-sized sub-regions by
+//! the MPU.  Sub-regions can only be used in regions of size 256 bytes
+//! or larger.  Any of these 8 sub-regions can be disabled, allowing for
+//! creation of ``holes'' in a region which can be left open, or overlaid
+//! by another region with different attributes.  Any of the 8 sub-regions
+//! can be disabled with a logical OR of any of the following flags:
+//!
+//! - \b MPU_SUB_RGN_DISABLE_0
+//! - \b MPU_SUB_RGN_DISABLE_1
+//! - \b MPU_SUB_RGN_DISABLE_2
+//! - \b MPU_SUB_RGN_DISABLE_3
+//! - \b MPU_SUB_RGN_DISABLE_4
+//! - \b MPU_SUB_RGN_DISABLE_5
+//! - \b MPU_SUB_RGN_DISABLE_6
+//! - \b MPU_SUB_RGN_DISABLE_7
+//!
+//! Finally, the region can be initially enabled or disabled with one of
+//! the following flags:
+//!
+//! - \b MPU_RGN_ENABLE
+//! - \b MPU_RGN_DISABLE
+//!
+//! As an example, to set a region with the following attributes: size of
+//! 32 KB, execution enabled, read-only for both privileged and user, one
+//! sub-region disabled, and initially enabled; the \e ui32Flags parameter
+//! would have the following value:
+//!
+//! <code>
+//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
+//!  MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
+//! </code>
+//!
+//! \note This function writes to multiple registers and is not protected
+//! from interrupts.  It is possible that an interrupt which accesses a
+//! region may occur while that region is in the process of being changed.
+//! The safest way to handle this is to disable a region before changing it.
+//! Refer to the discussion of this in the API Detailed Description section.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Region < 8);
+    ASSERT(ui32Addr ==
+           (ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1)));
+
+    //
+    // Program the base address, use the region field to select the
+    // region at the same time.
+    //
+    HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID;
+
+    //
+    // Program the region attributes.  Set the TEX field and the S, C,
+    // and B bits to fixed values that are suitable for all Tiva C and
+    // E Series memory.
+    //
+    HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M |
+                                           NVIC_MPU_ATTR_CACHEABLE)) |
+                            NVIC_MPU_ATTR_SHAREABLE | NVIC_MPU_ATTR_BUFFRABLE);
+}
+
+//*****************************************************************************
+//
+//! Gets the current settings for a specific region.
+//!
+//! \param ui32Region is the region number to get.
+//! \param pui32Addr points to storage for the base address of the region.
+//! \param pui32Flags points to the attribute flags for the region.
+//!
+//! This function retrieves the configuration of a specific region.  The
+//! meanings and format of the parameters is the same as that of the
+//! MPURegionSet() function.
+//!
+//! This function can be used to save the configuration of a region for later
+//! use with the MPURegionSet() function.  The region's enable state is
+//! preserved in the attributes that are saved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Region < 8);
+    ASSERT(pui32Addr);
+    ASSERT(pui32Flags);
+
+    //
+    // Select the region to get.
+    //
+    HWREG(NVIC_MPU_NUMBER) = ui32Region;
+
+    //
+    // Read and store the base address for the region.
+    //
+    *pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M;
+
+    //
+    // Read and store the region attributes.
+    //
+    *pui32Flags = HWREG(NVIC_MPU_ATTR);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the memory management fault.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! memory management fault occurs.
+//!
+//! This function sets and enables the handler to be called when the MPU
+//! generates a memory management fault due to a protection region access
+//! violation.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUIntRegister(void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(pfnHandler);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(FAULT_MPU, pfnHandler);
+
+    //
+    // Enable the memory management fault.
+    //
+    IntEnable(FAULT_MPU);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the memory management fault.
+//!
+//! This function disables and clears the handler to be called when a
+//! memory management fault occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUIntUnregister(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(FAULT_MPU);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(FAULT_MPU);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/mpu.h b/bsp/tm4c129x/libraries/driverlib/mpu.h
new file mode 100644
index 0000000000..a45435c92d
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/mpu.h
@@ -0,0 +1,162 @@
+//*****************************************************************************
+//
+// mpu.h - Defines and Macros for the memory protection unit.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_MPU_H__
+#define __DRIVERLIB_MPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPUEnable.
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT     4
+#define MPU_CONFIG_HARDFLT_NMI      2
+#define MPU_CONFIG_NONE             0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B            (4 << 1)
+#define MPU_RGN_SIZE_64B            (5 << 1)
+#define MPU_RGN_SIZE_128B           (6 << 1)
+#define MPU_RGN_SIZE_256B           (7 << 1)
+#define MPU_RGN_SIZE_512B           (8 << 1)
+
+#define MPU_RGN_SIZE_1K             (9 << 1)
+#define MPU_RGN_SIZE_2K             (10 << 1)
+#define MPU_RGN_SIZE_4K             (11 << 1)
+#define MPU_RGN_SIZE_8K             (12 << 1)
+#define MPU_RGN_SIZE_16K            (13 << 1)
+#define MPU_RGN_SIZE_32K            (14 << 1)
+#define MPU_RGN_SIZE_64K            (15 << 1)
+#define MPU_RGN_SIZE_128K           (16 << 1)
+#define MPU_RGN_SIZE_256K           (17 << 1)
+#define MPU_RGN_SIZE_512K           (18 << 1)
+
+#define MPU_RGN_SIZE_1M             (19 << 1)
+#define MPU_RGN_SIZE_2M             (20 << 1)
+#define MPU_RGN_SIZE_4M             (21 << 1)
+#define MPU_RGN_SIZE_8M             (22 << 1)
+#define MPU_RGN_SIZE_16M            (23 << 1)
+#define MPU_RGN_SIZE_32M            (24 << 1)
+#define MPU_RGN_SIZE_64M            (25 << 1)
+#define MPU_RGN_SIZE_128M           (26 << 1)
+#define MPU_RGN_SIZE_256M           (27 << 1)
+#define MPU_RGN_SIZE_512M           (28 << 1)
+
+#define MPU_RGN_SIZE_1G             (29 << 1)
+#define MPU_RGN_SIZE_2G             (30 << 1)
+#define MPU_RGN_SIZE_4G             (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC           0x00000000
+#define MPU_RGN_PERM_NOEXEC         0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO  0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO  0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO  0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW  0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO  0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO  0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0       0x00000100
+#define MPU_SUB_RGN_DISABLE_1       0x00000200
+#define MPU_SUB_RGN_DISABLE_2       0x00000400
+#define MPU_SUB_RGN_DISABLE_3       0x00000800
+#define MPU_SUB_RGN_DISABLE_4       0x00001000
+#define MPU_SUB_RGN_DISABLE_5       0x00002000
+#define MPU_SUB_RGN_DISABLE_6       0x00004000
+#define MPU_SUB_RGN_DISABLE_7       0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE              1
+#define MPU_RGN_DISABLE             0
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void MPUEnable(uint32_t ui32MPUConfig);
+extern void MPUDisable(void);
+extern uint32_t MPURegionCountGet(void);
+extern void MPURegionEnable(uint32_t ui32Region);
+extern void MPURegionDisable(uint32_t ui32Region);
+extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr,
+                         uint32_t ui32Flags);
+extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr,
+                         uint32_t *pui32Flags);
+extern void MPUIntRegister(void (*pfnHandler)(void));
+extern void MPUIntUnregister(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_MPU_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/onewire.c b/bsp/tm4c129x/libraries/driverlib/onewire.c
new file mode 100644
index 0000000000..b2f6e2300f
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/onewire.c
@@ -0,0 +1,771 @@
+//*****************************************************************************
+//
+// onewire.c - Driver for OneWire master module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup onewire_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_onewire.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/onewire.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// A bit mask for all transaction related fields in the 1-Wire control
+// register.
+//
+//*****************************************************************************
+#define ONEWIRE_TXN_MASK        (ONEWIRE_CS_OP_M | ONEWIRE_CS_SZ_M |          \
+                                 ONEWIRE_CS_BSIZE_M)
+
+//*****************************************************************************
+//
+// Left-shift value for the control register's transaction size.
+//
+//*****************************************************************************
+#define ONEWIRE_TXN_SIZE_LSHIFT 3
+
+//*****************************************************************************
+//
+// Left-shift value for the control register's last byte bit size.
+//
+//*****************************************************************************
+#define ONEWIRE_TXN_BSIZE_LSHIFT                                              \
+                                16
+
+//*****************************************************************************
+//
+//! Initializes the 1-Wire module.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param ui32InitFlags provides the initialization flags.
+//!
+//! This function configures and initializes the 1-Wire interface for use.
+//!
+//! The \e ui32InitFlags parameter is a combination of the following:
+//!
+//! - \b ONEWIRE_INIT_SPD_STD - standard speed bus timings
+//! - \b ONEWIRE_INIT_SPD_OD - overdrive speed bus timings
+//! - \b ONEWIRE_INIT_READ_STD - standard read sampling timing
+//! - \b ONEWIRE_INIT_READ_LATE - late read sampling timing
+//! - \b ONEWIRE_INIT_ATR - standard answer-to-reset presence detect
+//! - \b ONEWIRE_INIT_NO_ATR - no answer-to-reset presence detect
+//! - \b ONEWIRE_INIT_STD_POL - normal signal polarity
+//! - \b ONEWIRE_INIT_ALT_POL - alternate (reverse) signal polarity
+//! - \b ONEWIRE_INIT_1_WIRE_CFG - standard 1-Wire (1 data pin) setup
+//! - \b ONEWIRE_INIT_2_WIRE_CFG - alternate 2-Wire (2 data pin) setup
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+
+    //
+    // Initialize control register.
+    //
+    HWREG(ui32Base + ONEWIRE_O_CS) = ui32InitFlags;
+}
+
+//*****************************************************************************
+//
+//! Issues a reset on the 1-Wire bus.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//!
+//! This function causes the 1-Wire module to generate a reset signal on the
+//! 1-Wire bus.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireBusReset(uint32_t ui32Base)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+
+    //
+    // Issue a bus reset.
+    //
+    HWREG(ui32Base + ONEWIRE_O_CS) |= ONEWIRE_CS_RST;
+}
+
+//*****************************************************************************
+//
+//! Retrieves the 1-Wire bus condition status.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//!
+//! This function returns the 1-Wire bus conditions reported by the 1-Wire
+//! module.  These conditions could be a logical OR of any of the following:
+//!
+//! - \b ONEWIRE_BUS_STATUS_BUSY - A read, write, or reset is active.
+//! - \b ONEWIRE_BUS_STATUS_NO_SLAVE - No slave presence pulses detected.
+//! - \b ONEWIRE_BUS_STATUS_STUCK - The bus is being held low by non-master.
+//!
+//! \return Returns the 1-Wire bus conditions if detected else zero.
+//
+//*****************************************************************************
+uint32_t
+OneWireBusStatus(uint32_t ui32Base)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+
+    //
+    // Return the status bits from control and status register.
+    //
+    return(HWREG(ui32Base + ONEWIRE_O_CS) & (ONEWIRE_CS_BUSY |
+                                             ONEWIRE_CS_NOATR |
+                                             ONEWIRE_CS_STUCK));
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the 1-Wire interface.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param pui32Data is a pointer to storage to hold the read data.
+//!
+//! This function reads data from the 1-Wire module once all active bus
+//! operations are completed.  By protocol definition, bit data defaults to
+//! a 1.  Thus if a slave did not signal any 0-bit data, this read returns
+//! 0xffffffff.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireDataGet(uint32_t ui32Base, uint32_t *pui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT(pui32Data);
+
+    //
+    // Wait for any active operations to complete.
+    //
+    while(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY)
+    {
+    }
+
+    //
+    // Copy the data into the provided storage.
+    //
+    *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR);
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the 1-Wire interface.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param pui32Data is a pointer to storage to hold the read data.
+//!
+//! This function reads data from the 1-Wire module if there are no active
+//! operations on the bus.  Otherwise it returns without reading the data from
+//! the module.
+//!
+//! By protocol definition, bit data defaults to a 1.  Thus if a slave did
+//! not signal any 0-bit data, this read returns 0xffffffff.
+//!
+//! \return Returns \b true if a data read was performed, or \b false if the
+//! bus was not idle and no data was read.
+//
+//*****************************************************************************
+bool
+OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT(pui32Data);
+
+    //
+    // If the bus is busy, return without reading.
+    //
+    if(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY)
+    {
+        return(false);
+    }
+
+    //
+    // Copy the data into the provided storage.
+    //
+    *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR);
+
+    //
+    // Notify the caller data was read from the read register.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Clears the 1-Wire module interrupt sources.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified 1-Wire interrupt sources so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep the interrupts from being triggered again immediately upon exit.  The
+//! \e ui32IntFlags parameter can be a logical OR of any of the following:
+//!
+//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
+//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed.  If a
+//!   combined write and read operation was set up, the interrupt signals the
+//!   read is done.
+//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
+//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
+//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA |
+                             ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0);
+
+    //
+    // Clear the requested interrupts.
+    //
+    HWREG(ui32Base + ONEWIRE_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual 1-Wire module interrupt sources.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated 1-Wire interrupt sources.  The
+//! \e ui32IntFlags parameter can be a logical OR of any of the following:
+//!
+//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
+//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed.  If a
+//!   combined write and read operation was set up, the interrupt signals the
+//!   read is done.
+//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
+//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
+//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA |
+                             ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0);
+
+    //
+    // Disable the requested interrupts.
+    //
+    HWREG(ui32Base + ONEWIRE_O_IM) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enables individual 1-Wire module interrupt sources.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated 1-Wire interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.  The \e ui32IntFlags
+//! parameter can be a logical OR of any of the following:
+//!
+//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
+//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed.  If a
+//!   combined write and read operation was set up, the interrupt signals the
+//!   read is done.
+//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
+//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
+//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA |
+                             ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0);
+
+    //
+    // Enable the requested interrupts.
+    //
+    HWREG(ui32Base + ONEWIRE_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current 1-Wire interrupt status.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param bMasked is \b false if the raw interrupt status is required or
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the 1-Wire module.  Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the masked or raw 1-Wire interrupt status, as a bit field
+//! of any of the following values:
+//!
+//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
+//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed.
+//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
+//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
+//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed
+//
+//*****************************************************************************
+uint32_t
+OneWireIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + ONEWIRE_O_MIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + ONEWIRE_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the 1-Wire controller interrupt number.
+//!
+//! \param ui32Base specifies the 1-Wire module base address.
+//!
+//! This function returns the interrupt number for the 1-Wire module with the
+//! base address passed in the \e ui32Base parameter.
+//!
+//! \return Returns a 1-Wire interrupt number or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_OneWireIntNumberGet(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+
+    ui32Int = 0;
+
+    //
+    // Find the valid interrupt number for the 1-Wire module.
+    //
+    if(CLASS_IS_TM4E111)
+    {
+        ui32Int = INT_ONEWIRE0_TM4E111;
+    }
+    if(CLASS_IS_TM4C129)
+    {
+        ui32Int = INT_ONEWIRE0_TM4C129;
+    }
+
+    return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the 1-Wire module.
+//!
+//! \param ui32Base is the base address of the 1-Wire module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! 1-Wire interrupt occurs.
+//!
+//! This function sets the handler to be called when a 1-Wire interrupt occurs.
+//! This function enables the global interrupt in the interrupt controller;
+//! specific 1-Wire interrupts must be enabled via OneWireIntEnable().  If
+//! necessary, it is the interrupt handler's responsibility to clear the
+//! interrupt source via OneWireIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT(pfnHandler);
+
+    //
+    // Get the actual interrupt number for the 1-Wire module.
+    //
+    ui32Int = _OneWireIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the 1-Wire peripheral interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the 1-Wire module.
+//!
+//! \param ui32Base is the base address of the 1-Wire module.
+//!
+//! This function clears the handler to be called when an 1-Wire interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the argument.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+
+    //
+    // Get the actual interrupt number for the 1-Wire module.
+    //
+    ui32Int = _OneWireIntNumberGet(ui32Base);
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the 1-Wire peripheral interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Disables 1-Wire DMA operations.
+//!
+//! \param ui32Base is the base address of the 1-Wire module.
+//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable 1-Wire DMA features that were enabled
+//! by OneWireDMAEnable().  The specified 1-Wire DMA features are disabled.
+//! The \e ui32DMAFlags parameter is a combination of the following:
+//!
+//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting
+//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction
+//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write
+//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read
+//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each
+//!   completion
+//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits
+//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits
+//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT(ui32DMAFlags > 0);
+
+    //
+    // Clear the transaction size bits
+    //
+    HWREG(ui32Base + ONEWIRE_O_CS) = (HWREG(ui32Base + ONEWIRE_O_CS) &
+                                      ~(ONEWIRE_TXN_MASK));
+
+    //
+    // Disable the DMA features as requested.
+    //
+    HWREG(ui32Base + ONEWIRE_O_DMA) &= ~(ui32DMAFlags & 0xff);
+}
+
+//*****************************************************************************
+//
+//! Enables 1-Wire DMA operations.
+//!
+//! \param ui32Base is the base address of the 1-Wire module.
+//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
+//!
+//! This function enables the specified 1-Wire DMA features.  The 1-Wire module
+//! can be configured for write operations, read operations, small write and
+//! read operations, and scatter-gather support of mixed operations.
+//!
+//! The \e ui32DMAFlags parameter is a combination of the following:
+//!
+//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting
+//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction
+//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write
+//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read
+//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each
+//!   completion
+//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits
+//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits
+//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits
+//!
+//! \note The uDMA controller must be properly configured before DMA can be
+//! used with the 1-Wire module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT(ui32DMAFlags > 0);
+
+    //
+    // set up the transaction size.
+    //
+    HWREG(ui32Base + ONEWIRE_O_CS) = ((HWREG(ui32Base + ONEWIRE_O_CS) &
+                                       ~(ONEWIRE_TXN_MASK)) |
+                                      (ui32DMAFlags >> 8));
+
+    //
+    // Enable DMA with the parameters provided.
+    //
+    HWREG(ui32Base + ONEWIRE_O_DMA) = (ui32DMAFlags & 0xf);
+
+    //
+    // If a read transaction was requested, seed the write data register.  This
+    // will trigger the DMA reads to start.  This should not be done for
+    // scatter-gather operations.
+    //
+    if((ui32DMAFlags & (ONEWIRE_DMA_DMAOP_RDSNG | ONEWIRE_DMA_DMAOP_RDMUL)) &&
+       !(ui32DMAFlags & ONEWIRE_DMA_SG))
+    {
+        //
+        // Workaround for Snowflake DMA receive trigger errata.
+        //
+        if(CLASS_IS_TM4C129)
+        {
+            SysCtlDelay(9);
+        }
+
+        //
+        // Write DATW to trigger DMA receive start.
+        //
+        HWREG(ui32Base + ONEWIRE_O_DATW) = 0xffffffff;
+    }
+}
+
+//*****************************************************************************
+//
+//! Performs a 1-Wire protocol transaction on the bus.
+//!
+//! \param ui32Base specifies the base address of the 1-Wire module.
+//! \param ui32OpMode sets the transaction type.
+//! \param ui32Data is the data for a write operation.
+//! \param ui32BitCnt specifies the number of valid bits (1-32) for the
+//! operation.
+//!
+//! This function performs a 1-Wire protocol transaction, read and/or write, on
+//! the bus.  The application should confirm the bus is idle before starting a
+//! read or write transaction.
+//!
+//! The \e ui32OpMode defines the activity for the bus operations and is a
+//! logical OR of the following:
+//!
+//! - \b ONEWIRE_OP_RESET - Indicates the operation should be started with
+//!   a bus reset.
+//! - \b ONEWIRE_OP_WRITE - A write operation
+//! - \b ONEWIRE_OP_READ - A read operation
+//!
+//! \note If both a read and write operation are requested, the write will be
+//! performed prior to the read.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpMode, uint32_t ui32Data,
+                   uint32_t ui32BitCnt)
+{
+    uint32_t ui32Transaction;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == ONEWIRE0_BASE);
+    ASSERT((ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE |
+                          ONEWIRE_OP_READ)) > 0);
+    ASSERT((ui32BitCnt >= 1) && (ui32BitCnt <= 32));
+
+    //
+    // Read the control register and clear any transaction related
+    // bit fields.
+    //
+    ui32Transaction = HWREG(ui32Base + ONEWIRE_O_CS) & ~(ONEWIRE_TXN_MASK);
+
+    //
+    // Add the user specified operation flags.
+    //
+    ui32Transaction |= (ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE |
+                                      ONEWIRE_OP_READ));
+
+    //
+    // set up for a read or write transaction.
+    //
+    if(ui32Transaction & (ONEWIRE_CS_OP_WR | ONEWIRE_CS_OP_RD))
+    {
+        //
+        // Configure the 1-Wire module for the transaction size.  This is
+        // specified as 1-4 bytes and the specific bit size for the last
+        // byte therein.
+        //
+        ui32Transaction |= ((((ui32BitCnt % 8) ? (ui32BitCnt / 8) + 1 :
+                              (ui32BitCnt / 8)) - 1) <<
+                            ONEWIRE_TXN_SIZE_LSHIFT);
+        ui32Transaction |= ((ui32BitCnt % 8) << ONEWIRE_TXN_BSIZE_LSHIFT);
+
+        //
+        // Write specific setup.
+        //
+        if(ui32Transaction & ONEWIRE_CS_OP_WR)
+        {
+            //
+            // Load the data into the write register.
+            //
+            HWREG(ui32Base + ONEWIRE_O_DATW) = ui32Data;
+        }
+    }
+
+    //
+    // Start the transaction.
+    //
+    HWREG(ui32Base + ONEWIRE_O_CS) = ui32Transaction;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/onewire.h b/bsp/tm4c129x/libraries/driverlib/onewire.h
new file mode 100644
index 0000000000..6751f78d95
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/onewire.h
@@ -0,0 +1,307 @@
+//*****************************************************************************
+//
+// onewire.h - Prototypes for the OneWire Driver.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_ONEWIRE_H__
+#define __DRIVERLIB_ONEWIRE_H__
+
+//*****************************************************************************
+//
+//! \addtogroup onewire_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines used in the OneWireInit() function call.
+//
+//*****************************************************************************
+
+//
+// This define is used in initialization to request standard speed bus
+// timings.  This is the default.
+//
+#define ONEWIRE_INIT_SPD_STD    0x00000000
+
+//
+// This define is used in initialization to request overdrive speed bus
+// timings.
+//
+#define ONEWIRE_INIT_SPD_OD     0x00000020
+
+//
+// This define is used in initialization to request standard read sampling
+// timing (2us for ONEWIRE_INIT_SPD_OD and 16us for ONEWIRE_INIT_SPD_STD).
+// This is the default.
+//
+#define ONEWIRE_INIT_READ_STD   0x00000000
+
+//
+// This define is used in initialization to request late read sampling
+// timing (7us for ONEWIRE_INIT_SPD_OD and 50us for ONEWIRE_INIT_SPD_STD).
+//
+#define ONEWIRE_INIT_READ_LATE  0x00000040
+
+//
+// This define is used in initialization to request a standard
+// Answer-to-Reset (presence detect) monitor.  This is the default.
+//
+#define ONEWIRE_INIT_ATR        0x00000000
+
+//
+// This define is used in initialization to request no Answer-to-Reset
+// (presence detect) monitor.  The module will delay operations after a bus
+// reset for the expected presence detect period in this case.
+//
+#define ONEWIRE_INIT_NO_ATR     0x00000080
+
+//
+// This define is used in initialization to request standard signal polarity
+// on the 1-Wire bus (pin is driven low to drive bus low).  This is the
+// default.
+//
+#define ONEWIRE_INIT_STD_POL    0x00000000
+
+//
+// This define is used in initialization to request alternate signal polarity
+// on the 1-Wire bus (pin is driven high to drive bus low).
+//
+#define ONEWIRE_INIT_ALT_POL    0x40000000
+
+//
+// This define is used in initialization to request normal 1-Wire operational
+// mode.  This is the default.
+//
+#define ONEWIRE_INIT_1_WIRE_CFG 0x00000000
+
+//
+// This define is used in initialization to request a 2 pin operational
+// mode where one pin is used exclusively for TX operations and the other
+// for RX.
+//
+#define ONEWIRE_INIT_2_WIRE_CFG 0x80000000
+
+//*****************************************************************************
+//
+// Defines for bus status conditions.  These values can be returned by
+// OneWireBusStatus().
+//
+//*****************************************************************************
+
+//
+// This will be set if the bus is busy handling a Read, Write or
+// Reset activity.
+//
+#define ONEWIRE_BUS_STATUS_BUSY 0x00000100
+
+//
+// This will be set if the module did not detect any slave presence pulses
+// after a bus reset.
+//
+#define ONEWIRE_BUS_STATUS_NO_SLAVE                                           \
+                                0x00000200
+
+//
+// This will be set if the bus is being held low outside of a normal Read,
+// Write or Reset activity.
+//
+#define ONEWIRE_BUS_STATUS_STUCK                                              \
+                                0x00000400
+
+//*****************************************************************************
+//
+// OneWire operation modes used with OneWireTransaction().
+//
+//*****************************************************************************
+
+//
+// This mode flag indicates a single reset should be issued prior to a write
+// and/or read operation.
+//
+#define ONEWIRE_OP_RESET        0x00000001
+
+//
+// This mode flag indicates a read operation.
+//
+#define ONEWIRE_OP_READ         0x00000002
+
+//
+// This mode flag indicates a write operation.
+//
+#define ONEWIRE_OP_WRITE        0x00000004
+
+//*****************************************************************************
+//
+// OneWire DMA used with OneWireDMAEnable().
+//
+//*****************************************************************************
+
+//
+// This indicates the DMA should issue a 1-Wire bus reset before starting.
+//
+#define ONEWIRE_DMA_BUS_RESET   0x00000001
+
+//
+// The DMA operation will be a single Read after each module transaction.
+//
+#define ONEWIRE_DMA_OP_READ     0x00000002
+
+//
+// The DMA will write values to the 1-Wire interface as each previous DMA
+// write operation completes.
+//
+#define ONEWIRE_DMA_OP_MULTI_WRITE                                            \
+                                0x00000004
+
+//
+// The DMA will read values from the 1-Wire interface as each previous DMA
+// read operation completes.
+//
+#define ONEWIRE_DMA_OP_MULTI_READ                                             \
+                                0x00000006
+
+//
+// This Scatter Gather DMA mode is paired with ONEWIRE_DMA_OP_READ to instruct
+// the 1-Wire DMA to initiate an operation at the start of and then on each
+// transition completion thereafter.
+//
+#define ONEWIRE_DMA_MODE_SG     0x00000008
+
+//
+// DMA expects a Read/Write bus operation size of 8 bits.  This should match
+// the uDMA channel setup.
+//
+#define ONEWIRE_DMA_OP_SZ_8     0x00000000
+
+//
+// DMA expects a Read/Write bus operation size of 16 bits.  This should match
+// the uDMA channel setup.
+//
+#define ONEWIRE_DMA_OP_SZ_16    0x00000800
+
+//
+// DMA expects a Read/Write bus operation size of 32 bits.  This should match
+// the uDMA channel setup.
+//
+#define ONEWIRE_DMA_OP_SZ_32    0x00001800
+
+//*****************************************************************************
+//
+// OneWire interrupt defines.  Use in calls to OneWireIntEnable(),
+// OneWireIntDisable(), OneWireIntClear() and returned by OneWireIntStatus().
+//
+//*****************************************************************************
+
+//
+// This interrupt indicates a bus reset has just completed.
+//
+#define ONEWIRE_INT_RESET_DONE  0x00000001
+
+//
+// The interrupt indicates a Read or Write master initiated operation
+// has just completed.
+//
+#define ONEWIRE_INT_OP_DONE     0x00000002
+
+//
+// This interrupt indicates that no presence detect was signaled by a slave
+// on the bus after a reset.
+//
+#define ONEWIRE_INT_NO_SLAVE    0x00000004
+
+//
+// This interrupt indicates the bus is being held low outside of normal
+// operations.
+//
+#define ONEWIRE_INT_STUCK       0x00000008
+
+//
+// This interrupt indicates a OneWire DMA operation has completed.
+//
+#define ONEWIRE_INT_DMA_DONE    0x00000010
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void OneWireBusReset(uint32_t ui32Base);
+extern uint32_t OneWireBusStatus(uint32_t ui32Base);
+extern void OneWireDataGet(uint32_t u3i2Base, uint32_t *pui32Data);
+extern bool OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data);
+extern void OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags);
+extern void OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void OneWireIntUnregister(uint32_t ui32Base);
+extern uint32_t OneWireIntStatus(uint32_t ui32Base, bool bMasked);
+extern void OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpFlags,
+                               uint32_t ui32Data, uint32_t ui32BitCnt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_ONEWIRE_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/pin_map.h b/bsp/tm4c129x/libraries/driverlib/pin_map.h
new file mode 100644
index 0000000000..a2c94f46e7
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/pin_map.h
@@ -0,0 +1,20493 @@
+//*****************************************************************************
+//
+// pin_map.h - Mapping of peripherals to pins for all parts.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_PIN_MAP_H__
+#define __DRIVERLIB_PIN_MAP_H__
+
+//*****************************************************************************
+//
+// TM4C1230C3PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1230C3PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1230C3PM
+
+//*****************************************************************************
+//
+// TM4C1230D5PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1230D5PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1230D5PM
+
+//*****************************************************************************
+//
+// TM4C1230E6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1230E6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1230E6PM
+
+//*****************************************************************************
+//
+// TM4C1230H6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1230H6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1230H6PM
+
+//*****************************************************************************
+//
+// TM4C1231C3PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231C3PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1231C3PM
+
+//*****************************************************************************
+//
+// TM4C1231D5PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231D5PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1231D5PM
+
+//*****************************************************************************
+//
+// TM4C1231D5PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231D5PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1231D5PZ
+
+//*****************************************************************************
+//
+// TM4C1231E6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231E6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1231E6PM
+
+//*****************************************************************************
+//
+// TM4C1231E6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231E6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1231E6PZ
+
+//*****************************************************************************
+//
+// TM4C1231H6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231H6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1231H6PM
+
+//*****************************************************************************
+//
+// TM4C1231H6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231H6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1231H6PZ
+
+//*****************************************************************************
+//
+// TM4C1232C3PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1232C3PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1232C3PM
+
+//*****************************************************************************
+//
+// TM4C1232D5PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1232D5PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1232D5PM
+
+//*****************************************************************************
+//
+// TM4C1232E6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1232E6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1232E6PM
+
+//*****************************************************************************
+//
+// TM4C1232H6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1232H6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C1232H6PM
+
+//*****************************************************************************
+//
+// TM4C1233C3PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233C3PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1233C3PM
+
+//*****************************************************************************
+//
+// TM4C1233D5PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233D5PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1233D5PM
+
+//*****************************************************************************
+//
+// TM4C1233D5PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233D5PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1233D5PZ
+
+//*****************************************************************************
+//
+// TM4C1233E6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233E6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1233E6PM
+
+//*****************************************************************************
+//
+// TM4C1233E6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233E6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1233E6PZ
+
+//*****************************************************************************
+//
+// TM4C1233H6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233H6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C1233H6PM
+
+//*****************************************************************************
+//
+// TM4C1233H6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233H6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1233H6PZ
+
+//*****************************************************************************
+//
+// TM4C1236D5PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1236D5PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#endif // PART_TM4C1236D5PM
+
+//*****************************************************************************
+//
+// TM4C1236E6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1236E6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#endif // PART_TM4C1236E6PM
+
+//*****************************************************************************
+//
+// TM4C1236H6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1236H6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#endif // PART_TM4C1236H6PM
+
+//*****************************************************************************
+//
+// TM4C1237D5PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237D5PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#endif // PART_TM4C1237D5PM
+
+//*****************************************************************************
+//
+// TM4C1237D5PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237D5PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1237D5PZ
+
+//*****************************************************************************
+//
+// TM4C1237E6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237E6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#endif // PART_TM4C1237E6PM
+
+//*****************************************************************************
+//
+// TM4C1237E6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237E6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1237E6PZ
+
+//*****************************************************************************
+//
+// TM4C1237H6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237H6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#endif // PART_TM4C1237H6PM
+
+//*****************************************************************************
+//
+// TM4C1237H6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237H6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#endif // PART_TM4C1237H6PZ
+
+//*****************************************************************************
+//
+// TM4C123AE6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123AE6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C123AE6PM
+
+//*****************************************************************************
+//
+// TM4C123AH6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123AH6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#endif // PART_TM4C123AH6PM
+
+//*****************************************************************************
+//
+// TM4C123BE6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123BE6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C123BE6PM
+
+//*****************************************************************************
+//
+// TM4C123BE6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123BE6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#endif // PART_TM4C123BE6PZ
+
+//*****************************************************************************
+//
+// TM4C123BH6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123BH6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+
+#endif // PART_TM4C123BH6PM
+
+//*****************************************************************************
+//
+// TM4C123BH6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123BH6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#endif // PART_TM4C123BH6PZ
+
+//*****************************************************************************
+//
+// TM4C123FE6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123FE6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#endif // PART_TM4C123FE6PM
+
+//*****************************************************************************
+//
+// TM4C123FH6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123FH6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#endif // PART_TM4C123FH6PM
+
+//*****************************************************************************
+//
+// TM4C123GE6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GE6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#endif // PART_TM4C123GE6PM
+
+//*****************************************************************************
+//
+// TM4C123GE6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GE6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#endif // PART_TM4C123GE6PZ
+
+//*****************************************************************************
+//
+// TM4C123GH6PM Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GH6PM
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+
+#endif // PART_TM4C123GH6PM
+
+//*****************************************************************************
+//
+// TM4C123GH6PZ Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GH6PZ
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#endif // PART_TM4C123GH6PZ
+
+//*****************************************************************************
+//
+// TM4C1231H6PGE Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1231H6PGE
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#endif // PART_TM4C1231H6PGE
+
+//*****************************************************************************
+//
+// TM4C1233H6PGE Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1233H6PGE
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#endif // PART_TM4C1233H6PGE
+
+//*****************************************************************************
+//
+// TM4C1237H6PGE Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1237H6PGE
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE7_U1RI           0x00041C01
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+
+#define GPIO_PK2_SSI3RX         0x00090802
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#endif // PART_TM4C1237H6PGE
+
+//*****************************************************************************
+//
+// TM4C123BH6PGE Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123BH6PGE
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_M0FAULT0       0x00091006
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_M0FAULT1       0x00091406
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_M0FAULT2       0x00091806
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_M0FAULT3       0x00091C06
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_M0PWM4         0x000B1802
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_M0PWM5         0x000B1C02
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_M0PWM6         0x000C0802
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_M0PWM7         0x000C0C02
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_M1PWM4         0x000C1002
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_M1PWM5         0x000C1402
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_M1PWM6         0x000C1802
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_M1PWM7         0x000C1C02
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_M0PWM0         0x000D0001
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_M0PWM1         0x000D0401
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_M0PWM2         0x000D0801
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#endif // PART_TM4C123BH6PGE
+
+//*****************************************************************************
+//
+// TM4C123BH6ZRB Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123BH6ZRB
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_M0FAULT0       0x00091006
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_M0FAULT1       0x00091406
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_M0FAULT2       0x00091806
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_M0FAULT3       0x00091C06
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_M0PWM4         0x000B1802
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_M0PWM5         0x000B1C02
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_M0PWM6         0x000C0802
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_M0PWM7         0x000C0C02
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_M1PWM4         0x000C1002
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_M1PWM5         0x000C1402
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_M1PWM6         0x000C1802
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_M1PWM7         0x000C1C02
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_M0PWM0         0x000D0001
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_M0PWM1         0x000D0401
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_M0PWM2         0x000D0801
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#define GPIO_PP3_M0PWM3         0x000D0C01
+#define GPIO_PP3_T5CCP1         0x000D0C07
+
+#define GPIO_PP4_M0PWM4         0x000D1001
+#define GPIO_PP4_WT0CCP0        0x000D1007
+
+#define GPIO_PP5_M0PWM5         0x000D1401
+#define GPIO_PP5_WT0CCP1        0x000D1407
+
+#define GPIO_PP6_M0PWM6         0x000D1801
+#define GPIO_PP6_WT1CCP0        0x000D1807
+
+#define GPIO_PP7_M0PWM7         0x000D1C01
+#define GPIO_PP7_WT1CCP1        0x000D1C07
+
+#define GPIO_PQ0_M1PWM0         0x000E0001
+#define GPIO_PQ0_WT2CCP0        0x000E0007
+
+#define GPIO_PQ1_M1PWM1         0x000E0401
+#define GPIO_PQ1_WT2CCP1        0x000E0407
+
+#define GPIO_PQ2_M1PWM2         0x000E0801
+#define GPIO_PQ2_WT3CCP0        0x000E0807
+
+#define GPIO_PQ3_M1PWM3         0x000E0C01
+#define GPIO_PQ3_WT3CCP1        0x000E0C07
+
+#define GPIO_PQ4_M1PWM4         0x000E1001
+#define GPIO_PQ4_WT4CCP0        0x000E1007
+
+#define GPIO_PQ5_M1PWM5         0x000E1401
+#define GPIO_PQ5_WT4CCP1        0x000E1407
+
+#define GPIO_PQ6_M1PWM6         0x000E1801
+#define GPIO_PQ6_WT5CCP0        0x000E1807
+
+#define GPIO_PQ7_M1PWM7         0x000E1C01
+#define GPIO_PQ7_WT5CCP1        0x000E1C07
+
+#endif // PART_TM4C123BH6ZRB
+
+//*****************************************************************************
+//
+// TM4C123GH6PGE Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GH6PGE
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_M0FAULT0       0x00091006
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_M0FAULT1       0x00091406
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_M0FAULT2       0x00091806
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_M0FAULT3       0x00091C06
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_M0PWM4         0x000B1802
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_M0PWM5         0x000B1C02
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_M0PWM6         0x000C0802
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_M0PWM7         0x000C0C02
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_M1PWM4         0x000C1002
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_M1PWM5         0x000C1402
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_M1PWM6         0x000C1802
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_M1PWM7         0x000C1C02
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_M0PWM0         0x000D0001
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_M0PWM1         0x000D0401
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_M0PWM2         0x000D0801
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#endif // PART_TM4C123GH6PGE
+
+//*****************************************************************************
+//
+// TM4C123GH6ZRB Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GH6ZRB
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_M0FAULT0       0x00091006
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_M0FAULT1       0x00091406
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_M0FAULT2       0x00091806
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_M0FAULT3       0x00091C06
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_M0PWM4         0x000B1802
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_M0PWM5         0x000B1C02
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_M0PWM6         0x000C0802
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_M0PWM7         0x000C0C02
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_M1PWM4         0x000C1002
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_M1PWM5         0x000C1402
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_M1PWM6         0x000C1802
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_M1PWM7         0x000C1C02
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_M0PWM0         0x000D0001
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_M0PWM1         0x000D0401
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_M0PWM2         0x000D0801
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#define GPIO_PP3_M0PWM3         0x000D0C01
+#define GPIO_PP3_T5CCP1         0x000D0C07
+
+#define GPIO_PP4_M0PWM4         0x000D1001
+#define GPIO_PP4_WT0CCP0        0x000D1007
+
+#define GPIO_PP5_M0PWM5         0x000D1401
+#define GPIO_PP5_WT0CCP1        0x000D1407
+
+#define GPIO_PP6_M0PWM6         0x000D1801
+#define GPIO_PP6_WT1CCP0        0x000D1807
+
+#define GPIO_PP7_M0PWM7         0x000D1C01
+#define GPIO_PP7_WT1CCP1        0x000D1C07
+
+#define GPIO_PQ0_M1PWM0         0x000E0001
+#define GPIO_PQ0_WT2CCP0        0x000E0007
+
+#define GPIO_PQ1_M1PWM1         0x000E0401
+#define GPIO_PQ1_WT2CCP1        0x000E0407
+
+#define GPIO_PQ2_M1PWM2         0x000E0801
+#define GPIO_PQ2_WT3CCP0        0x000E0807
+
+#define GPIO_PQ3_M1PWM3         0x000E0C01
+#define GPIO_PQ3_WT3CCP1        0x000E0C07
+
+#define GPIO_PQ4_M1PWM4         0x000E1001
+#define GPIO_PQ4_WT4CCP0        0x000E1007
+
+#define GPIO_PQ5_M1PWM5         0x000E1401
+#define GPIO_PQ5_WT4CCP1        0x000E1407
+
+#define GPIO_PQ6_M1PWM6         0x000E1801
+#define GPIO_PQ6_WT5CCP0        0x000E1807
+
+#define GPIO_PQ7_M1PWM7         0x000E1C01
+#define GPIO_PQ7_WT5CCP1        0x000E1C07
+
+#endif // PART_TM4C123GH6ZRB
+
+//*****************************************************************************
+//
+// TM4C1290NCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1290NCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#endif // PART_TM4C1290NCPDT
+
+//*****************************************************************************
+//
+// TM4C1290NCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1290NCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+
+#define GPIO_PJ4_U3RTS          0x00081001
+
+#define GPIO_PJ5_U3CTS          0x00081401
+
+#define GPIO_PJ6_U4RTS          0x00081801
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+
+#endif // PART_TM4C1290NCZAD
+
+//*****************************************************************************
+//
+// TM4C1292NCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1292NCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EN0RXCK        0x0000180E
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_EN0MDC         0x00010805
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_EN0MDIO        0x00010C05
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_EN0MDC         0x00050805
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_EN0MDIO        0x00050C05
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_EN0TXCK        0x0006080E
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_EN0TXEN        0x00060C0E
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_EN0TXD0        0x0006100E
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_EN0TXD1        0x0006140E
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_EN0RXER        0x0006180E
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_EN0RXDV        0x00061C0E
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EN0INTRN       0x00091007
+#define GPIO_PK4_EN0RXD3        0x0009100E
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EN0RXD2        0x0009140E
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EN0TXD2        0x0009180E
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EN0TXD3        0x00091C0E
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+#define GPIO_PM4_EN0RREF_CLK    0x000B100E
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+#define GPIO_PM6_EN0CRS         0x000B180E
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+#define GPIO_PM7_EN0COL         0x000B1C0E
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_EN0INTRN       0x000D0007
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+#define GPIO_PQ5_EN0RXD0        0x000E140E
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+#define GPIO_PQ6_EN0RXD1        0x000E180E
+
+#endif // PART_TM4C1292NCPDT
+
+//*****************************************************************************
+//
+// TM4C1292NCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1292NCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EN0RXCK        0x0000180E
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_EN0MDC         0x00010805
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_EN0MDIO        0x00010C05
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_EN0MDC         0x00050805
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_EN0MDIO        0x00050C05
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_EN0TXCK        0x0006080E
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_EN0TXEN        0x00060C0E
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_EN0TXD0        0x0006100E
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_EN0TXD1        0x0006140E
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_EN0RXER        0x0006180E
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_EN0RXDV        0x00061C0E
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+
+#define GPIO_PJ4_U3RTS          0x00081001
+
+#define GPIO_PJ5_U3CTS          0x00081401
+
+#define GPIO_PJ6_U4RTS          0x00081801
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EN0INTRN       0x00091007
+#define GPIO_PK4_EN0RXD3        0x0009100E
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EN0RXD2        0x0009140E
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EN0TXD2        0x0009180E
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EN0TXD3        0x00091C0E
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+#define GPIO_PM4_EN0RREF_CLK    0x000B100E
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+#define GPIO_PM6_EN0CRS         0x000B180E
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+#define GPIO_PM7_EN0COL         0x000B1C0E
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_EN0TXER        0x000C180E
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_EN0INTRN       0x000D0007
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+#define GPIO_PQ5_EN0RXD0        0x000E140E
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+#define GPIO_PQ6_EN0RXD1        0x000E180E
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_EN0TXEN        0x000F1C0E
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_EN0TXD0        0x0010100E
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_EN0TXD1        0x0010140E
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_EN0RXER        0x0010180E
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_EN0RXDV        0x00101C0E
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_EN0RXD0        0x0011000E
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_EN0RXD1        0x0011040E
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+
+#endif // PART_TM4C1292NCZAD
+
+//*****************************************************************************
+//
+// TM4C1294KCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1294KCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#endif // PART_TM4C1294KCPDT
+
+//*****************************************************************************
+//
+// TM4C1294NCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1294NCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#endif // PART_TM4C1294NCPDT
+
+//*****************************************************************************
+//
+// TM4C1294NCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1294NCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+
+#define GPIO_PJ4_U3RTS          0x00081001
+
+#define GPIO_PJ5_U3CTS          0x00081401
+
+#define GPIO_PJ6_U4RTS          0x00081801
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+
+#endif // PART_TM4C1294NCZAD
+
+//*****************************************************************************
+//
+// TM4C1297NCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1297NCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PF6_LCDMCLK        0x0005180F
+
+#define GPIO_PF7_LCDDATA02      0x00051C0F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+#define GPIO_PJ2_LCDDATA14      0x0008080F
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+#define GPIO_PJ3_LCDDATA15      0x00080C0F
+
+#define GPIO_PJ4_U3RTS          0x00081001
+#define GPIO_PJ4_LCDDATA16      0x0008100F
+
+#define GPIO_PJ5_U3CTS          0x00081401
+#define GPIO_PJ5_LCDDATA17      0x0008140F
+
+#define GPIO_PJ6_U4RTS          0x00081801
+#define GPIO_PJ6_LCDAC          0x0008180F
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_LCDDATA13      0x000C180F
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+#define GPIO_PN7_LCDDATA12      0x000C1C0F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+#define GPIO_PR0_LCDCP          0x000F000F
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+#define GPIO_PR1_LCDFP          0x000F040F
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+#define GPIO_PR2_LCDLP          0x000F080F
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+#define GPIO_PR3_LCDDATA03      0x000F0C0F
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+#define GPIO_PR4_LCDDATA00      0x000F100F
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+#define GPIO_PR5_LCDDATA01      0x000F140F
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+#define GPIO_PR6_LCDDATA04      0x000F180F
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_LCDDATA05      0x000F1C0F
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+#define GPIO_PS0_LCDDATA20      0x0010000F
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+#define GPIO_PS1_LCDDATA21      0x0010040F
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+#define GPIO_PS2_LCDDATA22      0x0010080F
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+#define GPIO_PS3_LCDDATA23      0x00100C0F
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_LCDDATA06      0x0010100F
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_LCDDATA07      0x0010140F
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_LCDDATA08      0x0010180F
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_LCDDATA09      0x00101C0F
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_LCDDATA10      0x0011000F
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_LCDDATA11      0x0011040F
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+#define GPIO_PT2_LCDDATA18      0x0011080F
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+#define GPIO_PT3_LCDDATA19      0x00110C0F
+
+#endif // PART_TM4C1297NCZAD
+
+//*****************************************************************************
+//
+// TM4C1299KCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1299KCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PF6_LCDMCLK        0x0005180F
+
+#define GPIO_PF7_LCDDATA02      0x00051C0F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+#define GPIO_PJ2_LCDDATA14      0x0008080F
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+#define GPIO_PJ3_LCDDATA15      0x00080C0F
+
+#define GPIO_PJ4_U3RTS          0x00081001
+#define GPIO_PJ4_LCDDATA16      0x0008100F
+
+#define GPIO_PJ5_U3CTS          0x00081401
+#define GPIO_PJ5_LCDDATA17      0x0008140F
+
+#define GPIO_PJ6_U4RTS          0x00081801
+#define GPIO_PJ6_LCDAC          0x0008180F
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_LCDDATA13      0x000C180F
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+#define GPIO_PN7_LCDDATA12      0x000C1C0F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+#define GPIO_PR0_LCDCP          0x000F000F
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+#define GPIO_PR1_LCDFP          0x000F040F
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+#define GPIO_PR2_LCDLP          0x000F080F
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+#define GPIO_PR3_LCDDATA03      0x000F0C0F
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+#define GPIO_PR4_LCDDATA00      0x000F100F
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+#define GPIO_PR5_LCDDATA01      0x000F140F
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+#define GPIO_PR6_LCDDATA04      0x000F180F
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_LCDDATA05      0x000F1C0F
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+#define GPIO_PS0_LCDDATA20      0x0010000F
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+#define GPIO_PS1_LCDDATA21      0x0010040F
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+#define GPIO_PS2_LCDDATA22      0x0010080F
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+#define GPIO_PS3_LCDDATA23      0x00100C0F
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_LCDDATA06      0x0010100F
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_LCDDATA07      0x0010140F
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_LCDDATA08      0x0010180F
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_LCDDATA09      0x00101C0F
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_LCDDATA10      0x0011000F
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_LCDDATA11      0x0011040F
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+#define GPIO_PT2_LCDDATA18      0x0011080F
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+#define GPIO_PT3_LCDDATA19      0x00110C0F
+
+#endif // PART_TM4C1299KCZAD
+
+//*****************************************************************************
+//
+// TM4C1299NCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C1299NCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PF6_LCDMCLK        0x0005180F
+
+#define GPIO_PF7_LCDDATA02      0x00051C0F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+#define GPIO_PJ2_LCDDATA14      0x0008080F
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+#define GPIO_PJ3_LCDDATA15      0x00080C0F
+
+#define GPIO_PJ4_U3RTS          0x00081001
+#define GPIO_PJ4_LCDDATA16      0x0008100F
+
+#define GPIO_PJ5_U3CTS          0x00081401
+#define GPIO_PJ5_LCDDATA17      0x0008140F
+
+#define GPIO_PJ6_U4RTS          0x00081801
+#define GPIO_PJ6_LCDAC          0x0008180F
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_LCDDATA13      0x000C180F
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+#define GPIO_PN7_LCDDATA12      0x000C1C0F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+#define GPIO_PR0_LCDCP          0x000F000F
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+#define GPIO_PR1_LCDFP          0x000F040F
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+#define GPIO_PR2_LCDLP          0x000F080F
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+#define GPIO_PR3_LCDDATA03      0x000F0C0F
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+#define GPIO_PR4_LCDDATA00      0x000F100F
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+#define GPIO_PR5_LCDDATA01      0x000F140F
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+#define GPIO_PR6_LCDDATA04      0x000F180F
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_LCDDATA05      0x000F1C0F
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+#define GPIO_PS0_LCDDATA20      0x0010000F
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+#define GPIO_PS1_LCDDATA21      0x0010040F
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+#define GPIO_PS2_LCDDATA22      0x0010080F
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+#define GPIO_PS3_LCDDATA23      0x00100C0F
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_LCDDATA06      0x0010100F
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_LCDDATA07      0x0010140F
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_LCDDATA08      0x0010180F
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_LCDDATA09      0x00101C0F
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_LCDDATA10      0x0011000F
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_LCDDATA11      0x0011040F
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+#define GPIO_PT2_LCDDATA18      0x0011080F
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+#define GPIO_PT3_LCDDATA19      0x00110C0F
+
+#endif // PART_TM4C1299NCZAD
+
+//*****************************************************************************
+//
+// TM4C129CNCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129CNCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#endif // PART_TM4C129CNCPDT
+
+//*****************************************************************************
+//
+// TM4C129CNCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129CNCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+
+#define GPIO_PJ4_U3RTS          0x00081001
+
+#define GPIO_PJ5_U3CTS          0x00081401
+
+#define GPIO_PJ6_U4RTS          0x00081801
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+
+#endif // PART_TM4C129CNCZAD
+
+//*****************************************************************************
+//
+// TM4C129DNCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129DNCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EN0RXCK        0x0000180E
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_EN0MDC         0x00010805
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_EN0MDIO        0x00010C05
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_EN0MDC         0x00050805
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_EN0MDIO        0x00050C05
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_EN0TXCK        0x0006080E
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_EN0TXEN        0x00060C0E
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_EN0TXD0        0x0006100E
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_EN0TXD1        0x0006140E
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_EN0RXER        0x0006180E
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_EN0RXDV        0x00061C0E
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EN0INTRN       0x00091007
+#define GPIO_PK4_EN0RXD3        0x0009100E
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EN0RXD2        0x0009140E
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EN0TXD2        0x0009180E
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EN0TXD3        0x00091C0E
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+#define GPIO_PM4_EN0RREF_CLK    0x000B100E
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+#define GPIO_PM6_EN0CRS         0x000B180E
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+#define GPIO_PM7_EN0COL         0x000B1C0E
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_EN0INTRN       0x000D0007
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+#define GPIO_PQ5_EN0RXD0        0x000E140E
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+#define GPIO_PQ6_EN0RXD1        0x000E180E
+
+#endif // PART_TM4C129DNCPDT
+
+//*****************************************************************************
+//
+// TM4C129DNCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129DNCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EN0RXCK        0x0000180E
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_EN0MDC         0x00010805
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_EN0MDIO        0x00010C05
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_EN0MDC         0x00050805
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_EN0MDIO        0x00050C05
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_EN0TXCK        0x0006080E
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_EN0TXEN        0x00060C0E
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_EN0TXD0        0x0006100E
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_EN0TXD1        0x0006140E
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_EN0RXER        0x0006180E
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_EN0RXDV        0x00061C0E
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+
+#define GPIO_PJ4_U3RTS          0x00081001
+
+#define GPIO_PJ5_U3CTS          0x00081401
+
+#define GPIO_PJ6_U4RTS          0x00081801
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EN0INTRN       0x00091007
+#define GPIO_PK4_EN0RXD3        0x0009100E
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EN0RXD2        0x0009140E
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EN0TXD2        0x0009180E
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EN0TXD3        0x00091C0E
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+#define GPIO_PM4_EN0RREF_CLK    0x000B100E
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+#define GPIO_PM6_EN0CRS         0x000B180E
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+#define GPIO_PM7_EN0COL         0x000B1C0E
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_EN0TXER        0x000C180E
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_EN0INTRN       0x000D0007
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+#define GPIO_PQ5_EN0RXD0        0x000E140E
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+#define GPIO_PQ6_EN0RXD1        0x000E180E
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_EN0TXEN        0x000F1C0E
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_EN0TXD0        0x0010100E
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_EN0TXD1        0x0010140E
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_EN0RXER        0x0010180E
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_EN0RXDV        0x00101C0E
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_EN0RXD0        0x0011000E
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_EN0RXD1        0x0011040E
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+
+#endif // PART_TM4C129DNCZAD
+
+//*****************************************************************************
+//
+// TM4C129EKCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129EKCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#endif // PART_TM4C129EKCPDT
+
+//*****************************************************************************
+//
+// TM4C129ENCPDT Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129ENCPDT
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#endif // PART_TM4C129ENCPDT
+
+//*****************************************************************************
+//
+// TM4C129ENCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129ENCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+
+#define GPIO_PJ4_U3RTS          0x00081001
+
+#define GPIO_PJ5_U3CTS          0x00081401
+
+#define GPIO_PJ6_U4RTS          0x00081801
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+
+#endif // PART_TM4C129ENCZAD
+
+//*****************************************************************************
+//
+// TM4C129LNCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129LNCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PF6_LCDMCLK        0x0005180F
+
+#define GPIO_PF7_LCDDATA02      0x00051C0F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+#define GPIO_PJ2_LCDDATA14      0x0008080F
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+#define GPIO_PJ3_LCDDATA15      0x00080C0F
+
+#define GPIO_PJ4_U3RTS          0x00081001
+#define GPIO_PJ4_LCDDATA16      0x0008100F
+
+#define GPIO_PJ5_U3CTS          0x00081401
+#define GPIO_PJ5_LCDDATA17      0x0008140F
+
+#define GPIO_PJ6_U4RTS          0x00081801
+#define GPIO_PJ6_LCDAC          0x0008180F
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_LCDDATA13      0x000C180F
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+#define GPIO_PN7_LCDDATA12      0x000C1C0F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+#define GPIO_PR0_LCDCP          0x000F000F
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+#define GPIO_PR1_LCDFP          0x000F040F
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+#define GPIO_PR2_LCDLP          0x000F080F
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+#define GPIO_PR3_LCDDATA03      0x000F0C0F
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+#define GPIO_PR4_LCDDATA00      0x000F100F
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+#define GPIO_PR5_LCDDATA01      0x000F140F
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+#define GPIO_PR6_LCDDATA04      0x000F180F
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_LCDDATA05      0x000F1C0F
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+#define GPIO_PS0_LCDDATA20      0x0010000F
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+#define GPIO_PS1_LCDDATA21      0x0010040F
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+#define GPIO_PS2_LCDDATA22      0x0010080F
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+#define GPIO_PS3_LCDDATA23      0x00100C0F
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_LCDDATA06      0x0010100F
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_LCDDATA07      0x0010140F
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_LCDDATA08      0x0010180F
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_LCDDATA09      0x00101C0F
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_LCDDATA10      0x0011000F
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_LCDDATA11      0x0011040F
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+#define GPIO_PT2_LCDDATA18      0x0011080F
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+#define GPIO_PT3_LCDDATA19      0x00110C0F
+
+#endif // PART_TM4C129LNCZAD
+
+//*****************************************************************************
+//
+// TM4C129XKCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129XKCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EN0RXCK        0x0000180E
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_EN0MDC         0x00010805
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_EN0MDIO        0x00010C05
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+#define GPIO_PE3_OWIRE          0x00040C05
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_EN0MDC         0x00050805
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_EN0MDIO        0x00050C05
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PF6_LCDMCLK        0x0005180F
+
+#define GPIO_PF7_LCDDATA02      0x00051C0F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_EN0TXCK        0x0006080E
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_EN0TXEN        0x00060C0E
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_OWIRE          0x00061005
+#define GPIO_PG4_EN0TXD0        0x0006100E
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_OWALT          0x00061405
+#define GPIO_PG5_EN0TXD1        0x0006140E
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_OWIRE          0x00061805
+#define GPIO_PG6_EN0RXER        0x0006180E
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_OWIRE          0x00061C05
+#define GPIO_PG7_EN0RXDV        0x00061C0E
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+#define GPIO_PJ2_LCDDATA14      0x0008080F
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+#define GPIO_PJ3_LCDDATA15      0x00080C0F
+
+#define GPIO_PJ4_U3RTS          0x00081001
+#define GPIO_PJ4_LCDDATA16      0x0008100F
+
+#define GPIO_PJ5_U3CTS          0x00081401
+#define GPIO_PJ5_LCDDATA17      0x0008140F
+
+#define GPIO_PJ6_U4RTS          0x00081801
+#define GPIO_PJ6_LCDAC          0x0008180F
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EN0INTRN       0x00091007
+#define GPIO_PK4_EN0RXD3        0x0009100E
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EN0RXD2        0x0009140E
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EN0TXD2        0x0009180E
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EN0TXD3        0x00091C0E
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+#define GPIO_PM4_EN0RREF_CLK    0x000B100E
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+#define GPIO_PM6_EN0CRS         0x000B180E
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+#define GPIO_PM7_EN0COL         0x000B1C0E
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_EN0TXER        0x000C180E
+#define GPIO_PN6_LCDDATA13      0x000C180F
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+#define GPIO_PN7_LCDDATA12      0x000C1C0F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_EN0INTRN       0x000D0007
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_OWIRE          0x000D1004
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_OWALT          0x000D1404
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PP7_OWIRE          0x000D1C05
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+#define GPIO_PQ5_EN0RXD0        0x000E140E
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+#define GPIO_PQ6_EN0RXD1        0x000E180E
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+#define GPIO_PR0_LCDCP          0x000F000F
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+#define GPIO_PR1_LCDFP          0x000F040F
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+#define GPIO_PR2_LCDLP          0x000F080F
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+#define GPIO_PR3_LCDDATA03      0x000F0C0F
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+#define GPIO_PR4_LCDDATA00      0x000F100F
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+#define GPIO_PR5_LCDDATA01      0x000F140F
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+#define GPIO_PR6_LCDDATA04      0x000F180F
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_EN0TXEN        0x000F1C0E
+#define GPIO_PR7_LCDDATA05      0x000F1C0F
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+#define GPIO_PS0_LCDDATA20      0x0010000F
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+#define GPIO_PS1_LCDDATA21      0x0010040F
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+#define GPIO_PS2_LCDDATA22      0x0010080F
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+#define GPIO_PS3_LCDDATA23      0x00100C0F
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_EN0TXD0        0x0010100E
+#define GPIO_PS4_LCDDATA06      0x0010100F
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_EN0TXD1        0x0010140E
+#define GPIO_PS5_LCDDATA07      0x0010140F
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_EN0RXER        0x0010180E
+#define GPIO_PS6_LCDDATA08      0x0010180F
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_EN0RXDV        0x00101C0E
+#define GPIO_PS7_LCDDATA09      0x00101C0F
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_EN0RXD0        0x0011000E
+#define GPIO_PT0_LCDDATA10      0x0011000F
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_EN0RXD1        0x0011040E
+#define GPIO_PT1_LCDDATA11      0x0011040F
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+#define GPIO_PT2_LCDDATA18      0x0011080F
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+#define GPIO_PT3_LCDDATA19      0x00110C0F
+
+#endif // PART_TM4C129XKCZAD
+
+//*****************************************************************************
+//
+// TM4C129XNCZAD Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C129XNCZAD
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C9SCL        0x00000002
+#define GPIO_PA0_T0CCP0         0x00000003
+#define GPIO_PA0_CAN0RX         0x00000007
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C9SDA        0x00000402
+#define GPIO_PA1_T0CCP1         0x00000403
+#define GPIO_PA1_CAN0TX         0x00000407
+
+#define GPIO_PA2_U4RX           0x00000801
+#define GPIO_PA2_I2C8SCL        0x00000802
+#define GPIO_PA2_T1CCP0         0x00000803
+#define GPIO_PA2_SSI0CLK        0x0000080F
+
+#define GPIO_PA3_U4TX           0x00000C01
+#define GPIO_PA3_I2C8SDA        0x00000C02
+#define GPIO_PA3_T1CCP1         0x00000C03
+#define GPIO_PA3_SSI0FSS        0x00000C0F
+
+#define GPIO_PA4_U3RX           0x00001001
+#define GPIO_PA4_T2CCP0         0x00001003
+#define GPIO_PA4_I2C7SCL        0x00001002
+#define GPIO_PA4_SSI0XDAT0      0x0000100F
+
+#define GPIO_PA5_U3TX           0x00001401
+#define GPIO_PA5_T2CCP1         0x00001403
+#define GPIO_PA5_I2C7SDA        0x00001402
+#define GPIO_PA5_SSI0XDAT1      0x0000140F
+
+#define GPIO_PA6_U2RX           0x00001801
+#define GPIO_PA6_I2C6SCL        0x00001802
+#define GPIO_PA6_T3CCP0         0x00001803
+#define GPIO_PA6_USB0EPEN       0x00001805
+#define GPIO_PA6_SSI0XDAT2      0x0000180D
+#define GPIO_PA6_EN0RXCK        0x0000180E
+#define GPIO_PA6_EPI0S8         0x0000180F
+
+#define GPIO_PA7_U2TX           0x00001C01
+#define GPIO_PA7_I2C6SDA        0x00001C02
+#define GPIO_PA7_T3CCP1         0x00001C03
+#define GPIO_PA7_USB0PFLT       0x00001C05
+#define GPIO_PA7_USB0EPEN       0x00001C0B
+#define GPIO_PA7_SSI0XDAT3      0x00001C0D
+#define GPIO_PA7_EPI0S9         0x00001C0F
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_I2C5SCL        0x00010002
+#define GPIO_PB0_CAN1RX         0x00010007
+#define GPIO_PB0_T4CCP0         0x00010003
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_I2C5SDA        0x00010402
+#define GPIO_PB1_CAN1TX         0x00010407
+#define GPIO_PB1_T4CCP1         0x00010403
+
+#define GPIO_PB2_T5CCP0         0x00010803
+#define GPIO_PB2_I2C0SCL        0x00010802
+#define GPIO_PB2_EN0MDC         0x00010805
+#define GPIO_PB2_USB0STP        0x0001080E
+#define GPIO_PB2_EPI0S27        0x0001080F
+
+#define GPIO_PB3_I2C0SDA        0x00010C02
+#define GPIO_PB3_T5CCP1         0x00010C03
+#define GPIO_PB3_EN0MDIO        0x00010C05
+#define GPIO_PB3_USB0CLK        0x00010C0E
+#define GPIO_PB3_EPI0S28        0x00010C0F
+
+#define GPIO_PB4_U0CTS          0x00011001
+#define GPIO_PB4_I2C5SCL        0x00011002
+#define GPIO_PB4_SSI1FSS        0x0001100F
+
+#define GPIO_PB5_U0RTS          0x00011401
+#define GPIO_PB5_I2C5SDA        0x00011402
+#define GPIO_PB5_SSI1CLK        0x0001140F
+
+#define GPIO_PB6_I2C6SCL        0x00011802
+#define GPIO_PB6_T6CCP0         0x00011803
+
+#define GPIO_PB7_I2C6SDA        0x00011C02
+#define GPIO_PB7_T6CCP1         0x00011C03
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+
+#define GPIO_PC2_TDI            0x00020801
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+
+#define GPIO_PC4_U7RX           0x00021001
+#define GPIO_PC4_T7CCP0         0x00021003
+#define GPIO_PC4_EPI0S7         0x0002100F
+
+#define GPIO_PC5_U7TX           0x00021401
+#define GPIO_PC5_T7CCP1         0x00021403
+#define GPIO_PC5_RTCCLK         0x00021407
+#define GPIO_PC5_EPI0S6         0x0002140F
+
+#define GPIO_PC6_U5RX           0x00021801
+#define GPIO_PC6_EPI0S5         0x0002180F
+
+#define GPIO_PC7_U5TX           0x00021C01
+#define GPIO_PC7_EPI0S4         0x00021C0F
+
+#define GPIO_PD0_I2C7SCL        0x00030002
+#define GPIO_PD0_T0CCP0         0x00030003
+#define GPIO_PD0_C0O            0x00030005
+#define GPIO_PD0_SSI2XDAT1      0x0003000F
+
+#define GPIO_PD1_I2C7SDA        0x00030402
+#define GPIO_PD1_T0CCP1         0x00030403
+#define GPIO_PD1_C1O            0x00030405
+#define GPIO_PD1_SSI2XDAT0      0x0003040F
+
+#define GPIO_PD2_I2C8SCL        0x00030802
+#define GPIO_PD2_T1CCP0         0x00030803
+#define GPIO_PD2_C2O            0x00030805
+#define GPIO_PD2_SSI2FSS        0x0003080F
+
+#define GPIO_PD3_I2C8SDA        0x00030C02
+#define GPIO_PD3_T1CCP1         0x00030C03
+#define GPIO_PD3_SSI2CLK        0x00030C0F
+
+#define GPIO_PD4_U2RX           0x00031001
+#define GPIO_PD4_T3CCP0         0x00031003
+#define GPIO_PD4_SSI1XDAT2      0x0003100F
+
+#define GPIO_PD5_U2TX           0x00031401
+#define GPIO_PD5_T3CCP1         0x00031403
+#define GPIO_PD5_SSI1XDAT3      0x0003140F
+
+#define GPIO_PD6_U2RTS          0x00031801
+#define GPIO_PD6_T4CCP0         0x00031803
+#define GPIO_PD6_USB0EPEN       0x00031805
+#define GPIO_PD6_SSI2XDAT3      0x0003180F
+
+#define GPIO_PD7_U2CTS          0x00031C01
+#define GPIO_PD7_T4CCP1         0x00031C03
+#define GPIO_PD7_USB0PFLT       0x00031C05
+#define GPIO_PD7_NMI            0x00031C08
+#define GPIO_PD7_SSI2XDAT2      0x00031C0F
+
+#define GPIO_PE0_U1RTS          0x00040001
+
+#define GPIO_PE1_U1DSR          0x00040401
+
+#define GPIO_PE2_U1DCD          0x00040801
+
+#define GPIO_PE3_U1DTR          0x00040C01
+#define GPIO_PE3_OWIRE          0x00040C05
+
+#define GPIO_PE4_U1RI           0x00041001
+#define GPIO_PE4_SSI1XDAT0      0x0004100F
+
+#define GPIO_PE5_SSI1XDAT1      0x0004140F
+
+#define GPIO_PE6_U0CTS          0x00041801
+#define GPIO_PE6_I2C9SCL        0x00041802
+
+#define GPIO_PE7_U0RTS          0x00041C01
+#define GPIO_PE7_I2C9SDA        0x00041C02
+#define GPIO_PE7_NMI            0x00041C08
+
+#define GPIO_PF0_EN0LED0        0x00050005
+#define GPIO_PF0_M0PWM0         0x00050006
+#define GPIO_PF0_SSI3XDAT1      0x0005000E
+#define GPIO_PF0_TRD2           0x0005000F
+
+#define GPIO_PF1_EN0LED2        0x00050405
+#define GPIO_PF1_M0PWM1         0x00050406
+#define GPIO_PF1_SSI3XDAT0      0x0005040E
+#define GPIO_PF1_TRD1           0x0005040F
+
+#define GPIO_PF2_EN0MDC         0x00050805
+#define GPIO_PF2_M0PWM2         0x00050806
+#define GPIO_PF2_SSI3FSS        0x0005080E
+#define GPIO_PF2_TRD0           0x0005080F
+
+#define GPIO_PF3_EN0MDIO        0x00050C05
+#define GPIO_PF3_M0PWM3         0x00050C06
+#define GPIO_PF3_SSI3CLK        0x00050C0E
+#define GPIO_PF3_TRCLK          0x00050C0F
+
+#define GPIO_PF4_EN0LED1        0x00051005
+#define GPIO_PF4_M0FAULT0       0x00051006
+#define GPIO_PF4_SSI3XDAT2      0x0005100E
+#define GPIO_PF4_TRD3           0x0005100F
+
+#define GPIO_PF5_SSI3XDAT3      0x0005140E
+
+#define GPIO_PF6_LCDMCLK        0x0005180F
+
+#define GPIO_PF7_LCDDATA02      0x00051C0F
+
+#define GPIO_PG0_I2C1SCL        0x00060002
+#define GPIO_PG0_EN0PPS         0x00060005
+#define GPIO_PG0_M0PWM4         0x00060006
+#define GPIO_PG0_EPI0S11        0x0006000F
+
+#define GPIO_PG1_I2C1SDA        0x00060402
+#define GPIO_PG1_M0PWM5         0x00060406
+#define GPIO_PG1_EPI0S10        0x0006040F
+
+#define GPIO_PG2_I2C2SCL        0x00060802
+#define GPIO_PG2_EN0TXCK        0x0006080E
+#define GPIO_PG2_SSI2XDAT3      0x0006080F
+
+#define GPIO_PG3_I2C2SDA        0x00060C02
+#define GPIO_PG3_EN0TXEN        0x00060C0E
+#define GPIO_PG3_SSI2XDAT2      0x00060C0F
+
+#define GPIO_PG4_U0CTS          0x00061001
+#define GPIO_PG4_I2C3SCL        0x00061002
+#define GPIO_PG4_OWIRE          0x00061005
+#define GPIO_PG4_EN0TXD0        0x0006100E
+#define GPIO_PG4_SSI2XDAT1      0x0006100F
+
+#define GPIO_PG5_U0RTS          0x00061401
+#define GPIO_PG5_I2C3SDA        0x00061402
+#define GPIO_PG5_OWALT          0x00061405
+#define GPIO_PG5_EN0TXD1        0x0006140E
+#define GPIO_PG5_SSI2XDAT0      0x0006140F
+
+#define GPIO_PG6_I2C4SCL        0x00061802
+#define GPIO_PG6_OWIRE          0x00061805
+#define GPIO_PG6_EN0RXER        0x0006180E
+#define GPIO_PG6_SSI2FSS        0x0006180F
+
+#define GPIO_PG7_I2C4SDA        0x00061C02
+#define GPIO_PG7_OWIRE          0x00061C05
+#define GPIO_PG7_EN0RXDV        0x00061C0E
+#define GPIO_PG7_SSI2CLK        0x00061C0F
+
+#define GPIO_PH0_U0RTS          0x00070001
+#define GPIO_PH0_EPI0S0         0x0007000F
+
+#define GPIO_PH1_U0CTS          0x00070401
+#define GPIO_PH1_EPI0S1         0x0007040F
+
+#define GPIO_PH2_U0DCD          0x00070801
+#define GPIO_PH2_EPI0S2         0x0007080F
+
+#define GPIO_PH3_U0DSR          0x00070C01
+#define GPIO_PH3_EPI0S3         0x00070C0F
+
+#define GPIO_PH4_U0DTR          0x00071001
+
+#define GPIO_PH5_U0RI           0x00071401
+#define GPIO_PH5_EN0PPS         0x00071405
+
+#define GPIO_PH6_U5RX           0x00071801
+#define GPIO_PH6_U7RX           0x00071802
+
+#define GPIO_PH7_U5TX           0x00071C01
+#define GPIO_PH7_U7TX           0x00071C02
+
+#define GPIO_PJ0_U3RX           0x00080001
+#define GPIO_PJ0_EN0PPS         0x00080005
+
+#define GPIO_PJ1_U3TX           0x00080401
+
+#define GPIO_PJ2_U2RTS          0x00080801
+#define GPIO_PJ2_LCDDATA14      0x0008080F
+
+#define GPIO_PJ3_U2CTS          0x00080C01
+#define GPIO_PJ3_LCDDATA15      0x00080C0F
+
+#define GPIO_PJ4_U3RTS          0x00081001
+#define GPIO_PJ4_LCDDATA16      0x0008100F
+
+#define GPIO_PJ5_U3CTS          0x00081401
+#define GPIO_PJ5_LCDDATA17      0x0008140F
+
+#define GPIO_PJ6_U4RTS          0x00081801
+#define GPIO_PJ6_LCDAC          0x0008180F
+
+#define GPIO_PJ7_U4CTS          0x00081C01
+
+#define GPIO_PK0_U4RX           0x00090001
+#define GPIO_PK0_EPI0S0         0x0009000F
+
+#define GPIO_PK1_U4TX           0x00090401
+#define GPIO_PK1_EPI0S1         0x0009040F
+
+#define GPIO_PK2_U4RTS          0x00090801
+#define GPIO_PK2_EPI0S2         0x0009080F
+
+#define GPIO_PK3_U4CTS          0x00090C01
+#define GPIO_PK3_EPI0S3         0x00090C0F
+
+#define GPIO_PK4_I2C3SCL        0x00091002
+#define GPIO_PK4_EN0LED0        0x00091005
+#define GPIO_PK4_M0PWM6         0x00091006
+#define GPIO_PK4_EN0INTRN       0x00091007
+#define GPIO_PK4_EN0RXD3        0x0009100E
+#define GPIO_PK4_EPI0S32        0x0009100F
+
+#define GPIO_PK5_I2C3SDA        0x00091402
+#define GPIO_PK5_EN0LED2        0x00091405
+#define GPIO_PK5_M0PWM7         0x00091406
+#define GPIO_PK5_EN0RXD2        0x0009140E
+#define GPIO_PK5_EPI0S31        0x0009140F
+
+#define GPIO_PK6_I2C4SCL        0x00091802
+#define GPIO_PK6_EN0LED1        0x00091805
+#define GPIO_PK6_M0FAULT1       0x00091806
+#define GPIO_PK6_EN0TXD2        0x0009180E
+#define GPIO_PK6_EPI0S25        0x0009180F
+
+#define GPIO_PK7_U0RI           0x00091C01
+#define GPIO_PK7_I2C4SDA        0x00091C02
+#define GPIO_PK7_RTCCLK         0x00091C05
+#define GPIO_PK7_M0FAULT2       0x00091C06
+#define GPIO_PK7_EN0TXD3        0x00091C0E
+#define GPIO_PK7_EPI0S24        0x00091C0F
+
+#define GPIO_PL0_I2C2SDA        0x000A0002
+#define GPIO_PL0_M0FAULT3       0x000A0006
+#define GPIO_PL0_USB0D0         0x000A000E
+#define GPIO_PL0_EPI0S16        0x000A000F
+
+#define GPIO_PL1_I2C2SCL        0x000A0402
+#define GPIO_PL1_PHA0           0x000A0406
+#define GPIO_PL1_USB0D1         0x000A040E
+#define GPIO_PL1_EPI0S17        0x000A040F
+
+#define GPIO_PL2_C0O            0x000A0805
+#define GPIO_PL2_PHB0           0x000A0806
+#define GPIO_PL2_USB0D2         0x000A080E
+#define GPIO_PL2_EPI0S18        0x000A080F
+
+#define GPIO_PL3_C1O            0x000A0C05
+#define GPIO_PL3_IDX0           0x000A0C06
+#define GPIO_PL3_USB0D3         0x000A0C0E
+#define GPIO_PL3_EPI0S19        0x000A0C0F
+
+#define GPIO_PL4_T0CCP0         0x000A1003
+#define GPIO_PL4_USB0D4         0x000A100E
+#define GPIO_PL4_EPI0S26        0x000A100F
+
+#define GPIO_PL5_T0CCP1         0x000A1403
+#define GPIO_PL5_EPI0S33        0x000A140F
+#define GPIO_PL5_USB0D5         0x000A140E
+
+#define GPIO_PL6_T1CCP0         0x000A1803
+
+#define GPIO_PL7_T1CCP1         0x000A1C03
+
+#define GPIO_PM0_T2CCP0         0x000B0003
+#define GPIO_PM0_EPI0S15        0x000B000F
+
+#define GPIO_PM1_T2CCP1         0x000B0403
+#define GPIO_PM1_EPI0S14        0x000B040F
+
+#define GPIO_PM2_T3CCP0         0x000B0803
+#define GPIO_PM2_EPI0S13        0x000B080F
+
+#define GPIO_PM3_T3CCP1         0x000B0C03
+#define GPIO_PM3_EPI0S12        0x000B0C0F
+
+#define GPIO_PM4_U0CTS          0x000B1001
+#define GPIO_PM4_T4CCP0         0x000B1003
+#define GPIO_PM4_EN0RREF_CLK    0x000B100E
+
+#define GPIO_PM5_U0DCD          0x000B1401
+#define GPIO_PM5_T4CCP1         0x000B1403
+
+#define GPIO_PM6_U0DSR          0x000B1801
+#define GPIO_PM6_T5CCP0         0x000B1803
+#define GPIO_PM6_EN0CRS         0x000B180E
+
+#define GPIO_PM7_U0RI           0x000B1C01
+#define GPIO_PM7_T5CCP1         0x000B1C03
+#define GPIO_PM7_EN0COL         0x000B1C0E
+
+#define GPIO_PN0_U1RTS          0x000C0001
+
+#define GPIO_PN1_U1CTS          0x000C0401
+
+#define GPIO_PN2_U1DCD          0x000C0801
+#define GPIO_PN2_U2RTS          0x000C0802
+#define GPIO_PN2_EPI0S29        0x000C080F
+
+#define GPIO_PN3_U1DSR          0x000C0C01
+#define GPIO_PN3_U2CTS          0x000C0C02
+#define GPIO_PN3_EPI0S30        0x000C0C0F
+
+#define GPIO_PN4_U1DTR          0x000C1001
+#define GPIO_PN4_U3RTS          0x000C1002
+#define GPIO_PN4_I2C2SDA        0x000C1003
+#define GPIO_PN4_EPI0S34        0x000C100F
+
+#define GPIO_PN5_U1RI           0x000C1401
+#define GPIO_PN5_U3CTS          0x000C1402
+#define GPIO_PN5_I2C2SCL        0x000C1403
+#define GPIO_PN5_EPI0S35        0x000C140F
+
+#define GPIO_PN6_U4RTS          0x000C1802
+#define GPIO_PN6_EN0TXER        0x000C180E
+#define GPIO_PN6_LCDDATA13      0x000C180F
+
+#define GPIO_PN7_U1RTS          0x000C1C01
+#define GPIO_PN7_U4CTS          0x000C1C02
+#define GPIO_PN7_LCDDATA12      0x000C1C0F
+
+#define GPIO_PP0_U6RX           0x000D0001
+#define GPIO_PP0_T6CCP0         0x000D0005
+#define GPIO_PP0_EN0INTRN       0x000D0007
+#define GPIO_PP0_SSI3XDAT2      0x000D000F
+
+#define GPIO_PP1_U6TX           0x000D0401
+#define GPIO_PP1_T6CCP1         0x000D0405
+#define GPIO_PP1_SSI3XDAT3      0x000D040F
+
+#define GPIO_PP2_U0DTR          0x000D0801
+#define GPIO_PP2_USB0NXT        0x000D080E
+#define GPIO_PP2_EPI0S29        0x000D080F
+
+#define GPIO_PP3_U1CTS          0x000D0C01
+#define GPIO_PP3_U0DCD          0x000D0C02
+#define GPIO_PP3_RTCCLK         0x000D0C07
+#define GPIO_PP3_USB0DIR        0x000D0C0E
+#define GPIO_PP3_EPI0S30        0x000D0C0F
+
+#define GPIO_PP4_U3RTS          0x000D1001
+#define GPIO_PP4_U0DSR          0x000D1002
+#define GPIO_PP4_OWIRE          0x000D1004
+#define GPIO_PP4_USB0D7         0x000D100E
+
+#define GPIO_PP5_U3CTS          0x000D1401
+#define GPIO_PP5_I2C2SCL        0x000D1402
+#define GPIO_PP5_OWALT          0x000D1404
+#define GPIO_PP5_USB0D6         0x000D140E
+
+#define GPIO_PP6_U1DCD          0x000D1801
+#define GPIO_PP6_I2C2SDA        0x000D1802
+
+#define GPIO_PP7_OWIRE          0x000D1C05
+
+#define GPIO_PQ0_T6CCP0         0x000E0003
+#define GPIO_PQ0_SSI3CLK        0x000E000E
+#define GPIO_PQ0_EPI0S20        0x000E000F
+
+#define GPIO_PQ1_T6CCP1         0x000E0403
+#define GPIO_PQ1_SSI3FSS        0x000E040E
+#define GPIO_PQ1_EPI0S21        0x000E040F
+
+#define GPIO_PQ2_T7CCP0         0x000E0803
+#define GPIO_PQ2_SSI3XDAT0      0x000E080E
+#define GPIO_PQ2_EPI0S22        0x000E080F
+
+#define GPIO_PQ3_T7CCP1         0x000E0C03
+#define GPIO_PQ3_SSI3XDAT1      0x000E0C0E
+#define GPIO_PQ3_EPI0S23        0x000E0C0F
+
+#define GPIO_PQ4_U1RX           0x000E1001
+#define GPIO_PQ4_DIVSCLK        0x000E1007
+
+#define GPIO_PQ5_U1TX           0x000E1401
+#define GPIO_PQ5_EN0RXD0        0x000E140E
+
+#define GPIO_PQ6_U1DTR          0x000E1801
+#define GPIO_PQ6_EN0RXD1        0x000E180E
+
+#define GPIO_PQ7_U1RI           0x000E1C01
+
+#define GPIO_PR0_U4TX           0x000F0001
+#define GPIO_PR0_I2C1SCL        0x000F0002
+#define GPIO_PR0_M0PWM0         0x000F0006
+#define GPIO_PR0_LCDCP          0x000F000F
+
+#define GPIO_PR1_U4RX           0x000F0401
+#define GPIO_PR1_I2C1SDA        0x000F0402
+#define GPIO_PR1_M0PWM1         0x000F0406
+#define GPIO_PR1_LCDFP          0x000F040F
+
+#define GPIO_PR2_I2C2SCL        0x000F0802
+#define GPIO_PR2_M0PWM2         0x000F0806
+#define GPIO_PR2_LCDLP          0x000F080F
+
+#define GPIO_PR3_I2C2SDA        0x000F0C02
+#define GPIO_PR3_M0PWM3         0x000F0C06
+#define GPIO_PR3_LCDDATA03      0x000F0C0F
+
+#define GPIO_PR4_I2C3SCL        0x000F1002
+#define GPIO_PR4_T0CCP0         0x000F1003
+#define GPIO_PR4_M0PWM4         0x000F1006
+#define GPIO_PR4_LCDDATA00      0x000F100F
+
+#define GPIO_PR5_U1RX           0x000F1401
+#define GPIO_PR5_I2C3SDA        0x000F1402
+#define GPIO_PR5_T0CCP1         0x000F1403
+#define GPIO_PR5_M0PWM5         0x000F1406
+#define GPIO_PR5_LCDDATA01      0x000F140F
+
+#define GPIO_PR6_U1TX           0x000F1801
+#define GPIO_PR6_I2C4SCL        0x000F1802
+#define GPIO_PR6_T1CCP0         0x000F1803
+#define GPIO_PR6_M0PWM6         0x000F1806
+#define GPIO_PR6_LCDDATA04      0x000F180F
+
+#define GPIO_PR7_I2C4SDA        0x000F1C02
+#define GPIO_PR7_T1CCP1         0x000F1C03
+#define GPIO_PR7_M0PWM7         0x000F1C06
+#define GPIO_PR7_EN0TXEN        0x000F1C0E
+#define GPIO_PR7_LCDDATA05      0x000F1C0F
+
+#define GPIO_PS0_T2CCP0         0x00100003
+#define GPIO_PS0_M0FAULT0       0x00100006
+#define GPIO_PS0_LCDDATA20      0x0010000F
+
+#define GPIO_PS1_T2CCP1         0x00100403
+#define GPIO_PS1_M0FAULT1       0x00100406
+#define GPIO_PS1_LCDDATA21      0x0010040F
+
+#define GPIO_PS2_U1DSR          0x00100801
+#define GPIO_PS2_T3CCP0         0x00100803
+#define GPIO_PS2_M0FAULT2       0x00100806
+#define GPIO_PS2_LCDDATA22      0x0010080F
+
+#define GPIO_PS3_T3CCP1         0x00100C03
+#define GPIO_PS3_M0FAULT3       0x00100C06
+#define GPIO_PS3_LCDDATA23      0x00100C0F
+
+#define GPIO_PS4_T4CCP0         0x00101003
+#define GPIO_PS4_PHA0           0x00101006
+#define GPIO_PS4_EN0TXD0        0x0010100E
+#define GPIO_PS4_LCDDATA06      0x0010100F
+
+#define GPIO_PS5_T4CCP1         0x00101403
+#define GPIO_PS5_PHB0           0x00101406
+#define GPIO_PS5_EN0TXD1        0x0010140E
+#define GPIO_PS5_LCDDATA07      0x0010140F
+
+#define GPIO_PS6_T5CCP0         0x00101803
+#define GPIO_PS6_IDX0           0x00101806
+#define GPIO_PS6_EN0RXER        0x0010180E
+#define GPIO_PS6_LCDDATA08      0x0010180F
+
+#define GPIO_PS7_T5CCP1         0x00101C03
+#define GPIO_PS7_EN0RXDV        0x00101C0E
+#define GPIO_PS7_LCDDATA09      0x00101C0F
+
+#define GPIO_PT0_T6CCP0         0x00110003
+#define GPIO_PT0_CAN0RX         0x00110007
+#define GPIO_PT0_EN0RXD0        0x0011000E
+#define GPIO_PT0_LCDDATA10      0x0011000F
+
+#define GPIO_PT1_T6CCP1         0x00110403
+#define GPIO_PT1_CAN0TX         0x00110407
+#define GPIO_PT1_EN0RXD1        0x0011040E
+#define GPIO_PT1_LCDDATA11      0x0011040F
+
+#define GPIO_PT2_T7CCP0         0x00110803
+#define GPIO_PT2_CAN1RX         0x00110807
+#define GPIO_PT2_LCDDATA18      0x0011080F
+
+#define GPIO_PT3_T7CCP1         0x00110C03
+#define GPIO_PT3_CAN1TX         0x00110C07
+#define GPIO_PT3_LCDDATA19      0x00110C0F
+
+#endif // PART_TM4C129XNCZAD
+
+#endif // __DRIVERLIB_PIN_MAP_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/pwm.c b/bsp/tm4c129x/libraries/driverlib/pwm.c
new file mode 100644
index 0000000000..b74417ba8a
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/pwm.c
@@ -0,0 +1,2162 @@
+//*****************************************************************************
+//
+// pwm.c - API for the PWM modules
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup pwm_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_pwm.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/pwm.h"
+
+//*****************************************************************************
+//
+// Misc macros for manipulating the encoded generator and output defines used
+// by the API.
+//
+//*****************************************************************************
+#define PWM_GEN_BADDR(_mod_, _gen_)                                           \
+                                ((_mod_) + (_gen_))
+#define PWM_GEN_EXT_BADDR(_mod_, _gen_)                                       \
+                                ((_mod_) + PWM_GEN_EXT_0 +                    \
+                                 ((_gen_) - PWM_GEN_0) * 2)
+#define PWM_OUT_BADDR(_mod_, _out_)                                           \
+                                ((_mod_) + ((_out_) & 0xFFFFFFC0))
+#define PWM_IS_OUTPUT_ODD(_out_)                                              \
+                                ((_out_) & 0x00000001)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM generator number.
+//!
+//! \param ui32Gen is the generator number.
+//!
+//! This function determines if a PWM generator number is valid.
+//!
+//! \return Returnes \b true if the generator number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_PWMGenValid(uint32_t ui32Gen)
+{
+    return((ui32Gen == PWM_GEN_0) || (ui32Gen == PWM_GEN_1) ||
+           (ui32Gen == PWM_GEN_2) || (ui32Gen == PWM_GEN_3));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM output number.
+//!
+//! \param ui32PWMOut is the output number.
+//!
+//! This function determines if a PWM output number is valid.
+//!
+//! \return Returns \b true if the output number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_PWMOutValid(uint32_t ui32PWMOut)
+{
+    return((ui32PWMOut == PWM_OUT_0) || (ui32PWMOut == PWM_OUT_1) ||
+           (ui32PWMOut == PWM_OUT_2) || (ui32PWMOut == PWM_OUT_3) ||
+           (ui32PWMOut == PWM_OUT_4) || (ui32PWMOut == PWM_OUT_5) ||
+           (ui32PWMOut == PWM_OUT_6) || (ui32PWMOut == PWM_OUT_7));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Configures a PWM generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to configure.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32Config is the configuration for the PWM generator.
+//!
+//! This function is used to set the mode of operation for a PWM generator.
+//! The counting mode, synchronization mode, and debug behavior are all
+//! configured.  After configuration, the generator is left in the disabled
+//! state.
+//!
+//! A PWM generator can count in two different modes:  count down mode or count
+//! up/down mode.  In count down mode, it counts from a value down to zero,
+//! and then resets to the preset value, producing left-aligned PWM
+//! signals (that is, the rising edge of the two PWM signals produced by the
+//! generator occur at the same time).  In count up/down mode, it counts up
+//! from zero to the preset value, counts back down to zero, and then repeats
+//! the process, producing center-aligned PWM signals (that is,
+//! the middle of the high/low period of the PWM signals produced by the
+//! generator occurs at the same time).
+//!
+//! When the PWM generator parameters (period and pulse width) are modified,
+//! their effect on the output PWM signals can be delayed.  In synchronous
+//! mode, the parameter updates are not applied until a synchronization event
+//! occurs.  This mode allows multiple parameters to be modified and take
+//! effect simultaneously, instead of one at a time.  Additionally, parameters
+//! to multiple PWM generators in synchronous mode can be updated
+//! simultaneously, allowing them to be treated as if they were a unified
+//! generator.  In non-synchronous mode, the parameter updates are not delayed
+//! until a synchronization event.  In either mode, the parameter updates only
+//! occur when the counter is at zero to help prevent oddly formed PWM signals
+//! during the update (that is, a PWM pulse that is too short or too long).
+//!
+//! The PWM generator can either pause or continue running when the processor
+//! is stopped via the debugger.  If configured to pause, it continues to
+//! count until it reaches zero, at which point it pauses until the
+//! processor is restarted.  If configured to continue running, it keeps
+//! counting as if nothing had happened.
+//!
+//! The \e ui32Config parameter contains the desired configuration.  It is the
+//! logical OR of the following:
+//!
+//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting
+//!   mode
+//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter
+//!   load and comparator update synchronization mode
+//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
+//!   behavior
+//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or
+//!   \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization
+//!   mode for generator counting mode changes
+//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or
+//!   \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter
+//!   synchronization mode
+//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to
+//!   specify whether fault conditions are latched or not
+//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to
+//!   specify whether minimum fault period support is required
+//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify
+//!   whether extended fault source selection support is enabled or not
+//!
+//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the
+//! minimum duration of a PWM fault signal.  Faults are signaled for at
+//! least this time even if the external fault pin deasserts earlier.  Care
+//! should be taken when using this mode because during the fault signal
+//! period, the fault interrupt from the PWM generator remains asserted.  The
+//! fault interrupt handler may, therefore, reenter immediately if it exits
+//! prior to expiration of the fault timer.
+//!
+//! \note Changes to the counter mode affect the period of the PWM signals
+//! produced.  PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
+//! any changes to the counter mode of a generator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen,
+                uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen);
+
+    //
+    // Change the global configuration of the generator.
+    //
+    HWREG(ui32Gen + PWM_O_X_CTL) = ((HWREG(ui32Gen + PWM_O_X_CTL) &
+                                     ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
+                                       PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER |
+                                       PWM_X_CTL_FLTSRC |
+                                       PWM_X_CTL_DBFALLUPD_M |
+                                       PWM_X_CTL_DBRISEUPD_M |
+                                       PWM_X_CTL_DBCTLUPD_M |
+                                       PWM_X_CTL_GENBUPD_M |
+                                       PWM_X_CTL_GENAUPD_M |
+                                       PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
+                                       PWM_X_CTL_CMPBUPD)) | ui32Config);
+
+    //
+    // Set the individual PWM generator controls.
+    //
+    if(ui32Config & PWM_X_CTL_MODE)
+    {
+        //
+        // In up/down count mode, set the signal high on up count comparison
+        // and low on down count comparison (that is, center align the
+        // signals).
+        //
+        HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE |
+                                         PWM_X_GENA_ACTCMPAD_ZERO);
+        HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE |
+                                         PWM_X_GENB_ACTCMPBD_ZERO);
+    }
+    else
+    {
+        //
+        // In down count mode, set the signal high on load and low on count
+        // comparison (that is, left align the signals).
+        //
+        HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE |
+                                         PWM_X_GENA_ACTCMPAD_ZERO);
+        HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE |
+                                         PWM_X_GENB_ACTCMPBD_ZERO);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the period of a PWM generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to be modified.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32Period specifies the period of PWM generator output, measured
+//! in clock ticks.
+//!
+//! This function sets the period of the specified PWM generator block, where
+//! the period of the generator block is defined as the number of PWM clock
+//! ticks between pulses on the generator block zero signal.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen,
+                uint32_t ui32Period)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen);
+
+    //
+    // Set the reload register based on the mode.
+    //
+    if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+    {
+        //
+        // In up/down count mode, set the reload register to half the requested
+        // period.
+        //
+        ASSERT((ui32Period / 2) < 65536);
+        HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period / 2;
+    }
+    else
+    {
+        //
+        // In down count mode, set the reload register to the requested period
+        // minus one.
+        //
+        ASSERT((ui32Period <= 65536) && (ui32Period != 0));
+        HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period - 1;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the period of a PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to query.  This parameter must be one
+//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function gets the period of the specified PWM generator block.  The
+//! period of the generator block is defined as the number of PWM clock ticks
+//! between pulses on the generator block zero signal.
+//!
+//! If the update of the counter for the specified PWM generator has yet
+//! to be completed, the value returned may not be the active period.  The
+//! value returned is the programmed period, measured in PWM clock ticks.
+//!
+//! \return Returns the programmed period of the specified generator block
+//! in PWM clock ticks.
+//
+//*****************************************************************************
+uint32_t
+PWMGenPeriodGet(uint32_t ui32Base, uint32_t ui32Gen)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen);
+
+    //
+    // Figure out the counter mode.
+    //
+    if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+    {
+        //
+        // The period is twice the reload register value.
+        //
+        return(HWREG(ui32Gen + PWM_O_X_LOAD) * 2);
+    }
+    else
+    {
+        //
+        // The period is the reload register value plus one.
+        //
+        return(HWREG(ui32Gen + PWM_O_X_LOAD) + 1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables the timer/counter for a PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to be enabled.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function allows the PWM clock to drive the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Enable the PWM generator.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the timer/counter for a PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to be disabled.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function blocks the PWM clock from driving the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Disable the PWM generator.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) &=
+        ~(PWM_X_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Sets the pulse width for the specified PWM output.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOut is the PWM output to modify.  This parameter must be one
+//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4,
+//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7.
+//! \param ui32Width specifies the width of the positive portion of the pulse.
+//!
+//! This function sets the pulse width for the specified PWM output, where the
+//! pulse width is defined as the number of PWM clock ticks.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut,
+                 uint32_t ui32Width)
+{
+    uint32_t ui32GenBase, ui32Reg;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMOutValid(ui32PWMOut));
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut);
+
+    //
+    // If the counter is in up/down count mode, divide the width by two.
+    //
+    if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+    {
+        ui32Width /= 2;
+    }
+
+    //
+    // Get the period.
+    //
+    ui32Reg = HWREG(ui32GenBase + PWM_O_X_LOAD);
+
+    //
+    // Make sure the width is not too large.
+    //
+    ASSERT(ui32Width < ui32Reg);
+
+    //
+    // Compute the compare value.
+    //
+    ui32Reg = ui32Reg - ui32Width;
+
+    //
+    // Write to the appropriate registers.
+    //
+    if(PWM_IS_OUTPUT_ODD(ui32PWMOut))
+    {
+        HWREG(ui32GenBase + PWM_O_X_CMPB) = ui32Reg;
+    }
+    else
+    {
+        HWREG(ui32GenBase + PWM_O_X_CMPA) = ui32Reg;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the pulse width of a PWM output.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOut is the PWM output to query.  This parameter must be one
+//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4,
+//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7.
+//!
+//! This function gets the currently programmed pulse width for the specified
+//! PWM output.  If the update of the comparator for the specified output has
+//! yet to be completed, the value returned may not be the active pulse width.
+//! The value returned is the programmed pulse width, measured in PWM clock
+//! ticks.
+//!
+//! \return Returns the width of the pulse in PWM clock ticks.
+//
+//*****************************************************************************
+uint32_t
+PWMPulseWidthGet(uint32_t ui32Base, uint32_t ui32PWMOut)
+{
+    uint32_t ui32GenBase, ui32Reg, ui32Load;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMOutValid(ui32PWMOut));
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut);
+
+    //
+    // Then compute the pulse width.  If mode is UpDown, set
+    // width = (load - compare) * 2.  Otherwise, set width = load - compare.
+    //
+    ui32Load = HWREG(ui32GenBase + PWM_O_X_LOAD);
+    if(PWM_IS_OUTPUT_ODD(ui32PWMOut))
+    {
+        ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPB);
+    }
+    else
+    {
+        ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPA);
+    }
+    ui32Reg = ui32Load - ui32Reg;
+
+    //
+    // If in up/down count mode, double the pulse width.
+    //
+    if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+    {
+        ui32Reg = ui32Reg * 2;
+    }
+
+    //
+    // Return the pulse width.
+    //
+    return(ui32Reg);
+}
+
+//*****************************************************************************
+//
+//! Enables the PWM dead band output and sets the dead band delays.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to modify.  This parameter must be one
+//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui16Rise specifies the width of delay from the rising edge.
+//! \param ui16Fall specifies the width of delay from the falling edge.
+//!
+//! This function sets the dead bands for the specified PWM generator, where
+//! the dead bands are defined as the number of \b PWM clock ticks from the
+//! rising or falling edge of the generator's \b OutA signal.  Note that this
+//! function causes the coupling of \b OutB to \b OutA.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen,
+                  uint16_t ui16Rise, uint16_t ui16Fall)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT(ui16Rise < 4096);
+    ASSERT(ui16Fall < 4096);
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen);
+
+    //
+    // Write the dead band delay values.
+    //
+    HWREG(ui32Gen + PWM_O_X_DBRISE) = ui16Rise;
+    HWREG(ui32Gen + PWM_O_X_DBFALL) = ui16Fall;
+
+    //
+    // Enable the deadband functionality.
+    //
+    HWREG(ui32Gen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the PWM dead band output.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to modify.  This parameter must be one
+//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function disables the dead band mode for the specified PWM generator.
+//! Doing so decouples the \b OutA and \b OutB signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Disable the deadband functionality.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_DBCTL) &=
+        ~(PWM_X_DBCTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Synchronizes all pending updates.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32GenBits are the PWM generator blocks to be updated.  This
+//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT,
+//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM generators, this function causes all queued updates to
+//! the period or pulse width to be applied the next time the corresponding
+//! counter becomes zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+                             PWM_GEN_3_BIT)));
+
+    //
+    // Synchronize pending PWM register changes.
+    //
+    HWREG(ui32Base + PWM_O_CTL) = ui32GenBits;
+}
+
+//*****************************************************************************
+//
+//! Synchronizes the counters in one or multiple PWM generator blocks.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32GenBits are the PWM generator blocks to be synchronized.  This
+//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT,
+//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM module, this function synchronizes the time base of
+//! the generator blocks by causing the specified generator counters to be
+//! reset to zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+                             PWM_GEN_3_BIT)));
+
+    //
+    // Synchronize the counters in the specified generators by writing to the
+    // module's synchronization register.
+    //
+    HWREG(ui32Base + PWM_O_SYNC) = ui32GenBits;
+}
+
+//*****************************************************************************
+//
+//! Enables or disables PWM outputs.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOutBits are the PWM outputs to be modified.  This parameter
+//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT,
+//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT,
+//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT.
+//! \param bEnable determines if the signal is enabled or disabled.
+//!
+//! This function enables or disables the selected PWM outputs.  The outputs
+//! are selected using the parameter \e ui32PWMOutBits.  The parameter \e
+//! bEnable determines the state of the selected outputs.  If \e bEnable is
+//! \b true, then the selected PWM outputs are enabled, or placed in the active
+//! state.  If \e bEnable is \b false, then the selected outputs are disabled
+//! or placed in the inactive state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+               bool bEnable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+                                PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+                                PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+    //
+    // Read the module's ENABLE output control register and set or clear the
+    // requested bits.
+    //
+    if(bEnable == true)
+    {
+        HWREG(ui32Base + PWM_O_ENABLE) |= ui32PWMOutBits;
+    }
+    else
+    {
+        HWREG(ui32Base + PWM_O_ENABLE) &= ~(ui32PWMOutBits);
+    }
+}
+
+//*****************************************************************************
+//
+//! Selects the inversion mode for PWM outputs.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOutBits are the PWM outputs to be modified.  This parameter
+//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT,
+//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT,
+//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT.
+//! \param bInvert determines if the signal is inverted or passed through.
+//!
+//! This function is used to select the inversion mode for the selected PWM
+//! outputs.  The outputs are selected using the parameter \e ui32PWMOutBits.
+//! The parameter \e bInvert determines the inversion mode for the selected
+//! outputs.  If \e bInvert is \b true, this function causes the specified
+//! PWM output signals to be inverted or made active low.  If \e bInvert is
+//! \b false, the specified outputs are passed through as is or made active
+//! high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+                bool bInvert)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+                                PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+                                PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+    //
+    // Read the module's INVERT output control register and set or clear the
+    // requested bits.
+    //
+    if(bInvert == true)
+    {
+        HWREG(ui32Base + PWM_O_INVERT) |= ui32PWMOutBits;
+    }
+    else
+    {
+        HWREG(ui32Base + PWM_O_INVERT) &= ~(ui32PWMOutBits);
+    }
+}
+
+//*****************************************************************************
+//
+//! Specifies the level of PWM outputs suppressed in response to a fault
+//! condition.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOutBits are the PWM outputs to be modified.  This parameter
+//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT,
+//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT,
+//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT.
+//! \param bDriveHigh determines if the signal is driven high or low during an
+//! active fault condition.
+//!
+//! This function determines whether a PWM output pin that is suppressed in
+//! response to a fault condition is driven high or low.  The affected outputs
+//! are selected using the parameter \e ui32PWMOutBits.  The parameter
+//! \e bDriveHigh determines the output level for the pins identified by
+//! \e ui32PWMOutBits.  If \e bDriveHigh is \b true then the selected outputs
+//! are driven high when a fault is detected.  If it is \e false, the pins are
+//! driven low.
+//!
+//! In a fault condition, pins which have not been configured to be suppressed
+//! via a call to PWMOutputFault() are unaffected by this function.
+//!
+//! \note This function is available only on devices which support extended
+//! PWM fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFaultLevel(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+                    bool bDriveHigh)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+                                PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+                                PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+    //
+    // Read the module's FAULT output control register and set or clear the
+    // requested bits.
+    //
+    if(bDriveHigh == true)
+    {
+        HWREG(ui32Base + PWM_O_FAULTVAL) |= ui32PWMOutBits;
+    }
+    else
+    {
+        HWREG(ui32Base + PWM_O_FAULTVAL) &= ~(ui32PWMOutBits);
+    }
+}
+
+//*****************************************************************************
+//
+//! Specifies the state of PWM outputs in response to a fault condition.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOutBits are the PWM outputs to be modified.  This parameter
+//! must be the  logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT,
+//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT,
+//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT.
+//! \param bFaultSuppress determines if the signal is suppressed or passed
+//! through during an active fault condition.
+//!
+//! This function sets the fault handling characteristics of the selected PWM
+//! outputs.  The outputs are selected using the parameter \e ui32PWMOutBits.
+//! The parameter \e bFaultSuppress determines the fault handling
+//! characteristics for the selected outputs.  If \e bFaultSuppress is \b true,
+//! then the selected outputs are made inactive.  If \e bFaultSuppress is
+//! \b false, then the selected outputs are unaffected by the detected fault.
+//!
+//! On devices supporting extended PWM fault handling, the state the affected
+//! output pins are driven to can be configured with PWMOutputFaultLevel().  If
+//! not configured, or if the device does not support extended PWM fault
+//! handling, affected outputs are driven low on a fault condition.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+               bool bFaultSuppress)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+                                PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+                                PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+    //
+    // Read the module's FAULT output control register and set or clear the
+    // requested bits.
+    //
+    if(bFaultSuppress == true)
+    {
+        HWREG(ui32Base + PWM_O_FAULT) |= ui32PWMOutBits;
+    }
+    else
+    {
+        HWREG(ui32Base + PWM_O_FAULT) &= ~(ui32PWMOutBits);
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the PWM generator interrupt number.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator in question.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function returns the interrupt number of the corresponding PWM
+//! generator.
+//!
+//! \return Returns the interrupt number.
+//
+//*****************************************************************************
+static uint32_t
+_PWMGenIntNumberGet(uint32_t ui32Base, uint32_t ui32Gen)
+{
+    //
+    // Determine the generator and PWM module in question.
+    //
+    switch(ui32Base + ui32Gen)
+    {
+        //
+        // The first PWM generator in the first PWM module.
+        //
+        case PWM0_BASE + PWM_GEN_0:
+        {
+            if(CLASS_IS_TM4C123)
+            {
+                return(INT_PWM0_0_TM4C123);
+            }
+            else if(CLASS_IS_TM4C129)
+            {
+                return(INT_PWM0_0_TM4C129);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The second PWM generator in the first PWM module.
+        //
+        case PWM0_BASE + PWM_GEN_1:
+        {
+            if(CLASS_IS_TM4C129)
+            {
+                return(INT_PWM0_1_TM4C129);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The third PWM generator in the first PWM module.
+        //
+        case PWM0_BASE + PWM_GEN_2:
+        {
+            if(CLASS_IS_TM4C129)
+            {
+                return(INT_PWM0_2_TM4C129);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The fourth PWM generator in the first PWM module.
+        //
+        case PWM0_BASE + PWM_GEN_3:
+        {
+            if(CLASS_IS_TM4C129)
+            {
+                return(INT_PWM0_3_TM4C129);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The first PWM generator in the second PWM module.
+        //
+        case PWM1_BASE + PWM_GEN_0:
+        {
+            if(CLASS_IS_TM4C123)
+            {
+                return(INT_PWM1_0_TM4C123);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The first PWM generator in the second PWM module.
+        //
+        case PWM1_BASE + PWM_GEN_1:
+        {
+            if(CLASS_IS_TM4C123)
+            {
+                return(INT_PWM1_1_TM4C123);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The first PWM generator in the second PWM module.
+        //
+        case PWM1_BASE + PWM_GEN_2:
+        {
+            if(CLASS_IS_TM4C123)
+            {
+                return(INT_PWM1_2_TM4C123);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // The first PWM generator in the second PWM module.
+        //
+        case PWM1_BASE + PWM_GEN_3:
+        {
+            if(CLASS_IS_TM4C123)
+            {
+                return(INT_PWM1_3_TM4C123);
+            }
+            else
+            {
+                return(0);
+            }
+        }
+
+        //
+        // An unknown PWM module/generator was specified.
+        //
+        default:
+        {
+            return(0);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the specified PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator in question.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! generator interrupt occurs.
+//!
+//! This function ensures that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected for the specified
+//! PWM generator block.  This function also enables the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be enabled with PWMIntEnable() and
+//! PWMGenIntTrigEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen,
+                  void (*pfnIntHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Get the interrupt number associated with the specified generator.
+    //
+    ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnIntHandler);
+
+    //
+    // Enable the PWMx interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for the specified PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator in question.  This parameter must be
+//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function unregisters the interrupt handler for the specified
+//! PWM generator block.  This function also disables the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be disabled with PWMIntDisable() and
+//! PWMGenIntTrigDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Get the interrupt number associated with the specified generator.
+    //
+    ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the PWMx interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Gets the PWM fault interrupt number.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//!
+//! This function returns the fault interrupt number of the corresponding
+//! PWM module.
+//!
+//! \return Returns the interrupt number.
+//
+//*****************************************************************************
+static uint32_t
+_PWMFaultIntNumberGet(uint32_t ui32Base)
+{
+    //
+    // Return the fault interrupt number.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C123 :
+               INT_PWM1_FAULT_TM4C123);
+    }
+    else if(CLASS_IS_TM4C129)
+    {
+        return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C129 : 0);
+    }
+    else
+    {
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a fault condition detected in a PWM
+//! module.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! fault interrupt occurs.
+//!
+//! This function ensures that the interrupt handler specified by
+//! \e pfnIntHandler is called when a fault interrupt is detected for the
+//! selected PWM module.  This function also enables the PWM fault
+//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
+//! module level using PWMIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntRegister(uint32_t ui32Base, void (*pfnIntHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+
+    //
+    // Get the interrupt number associated with the specified module.
+    //
+    ui32Int = _PWMFaultIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler, returning an error if one occurs.
+    //
+    IntRegister(ui32Int, pfnIntHandler);
+
+    //
+    // Enable the PWM fault interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Removes the PWM fault condition interrupt handler.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//!
+//! This function removes the interrupt handler for a PWM fault interrupt
+//! from the selected PWM module.  This function also disables the PWM
+//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
+//! at the module level using PWMIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+
+    //
+    // Get the interrupt number associated with the specified module.
+    //
+    ui32Int = _PWMFaultIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the PWM fault interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler, returning an error if one occurs.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts and triggers for the specified PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to have interrupts and triggers
+//! enabled.  This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1,
+//! \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32IntTrig specifies the interrupts and triggers to be enabled.
+//!
+//! This function unmasks the specified interrupt(s) and trigger(s) by setting
+//! the specified bits of the interrupt/trigger enable register for the
+//! specified PWM generator.  The \e ui32IntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen,
+                    uint32_t ui32IntTrig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+                            PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+                            PWM_INT_CNT_BD | PWM_TR_CNT_ZERO |
+                            PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD |
+                            PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0);
+
+    //
+    // Enable the specified interrupts/triggers.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) |= ui32IntTrig;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to have interrupts and triggers
+//! disabled.  This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1,
+//! \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32IntTrig specifies the interrupts and triggers to be disabled.
+//!
+//! This function masks the specified interrupt(s) and trigger(s) by clearing
+//! the specified bits of the interrupt/trigger enable register for the
+//! specified PWM generator.  The \e ui32IntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen,
+                     uint32_t ui32IntTrig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+                            PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+                            PWM_INT_CNT_BD | PWM_TR_CNT_ZERO |
+                            PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD |
+                            PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0);
+
+    //
+    // Disable the specified interrupts/triggers.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) &= ~(ui32IntTrig);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to query.  This parameter must be one
+//! of \b PWM_GEN_0,  \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status is returned.
+//!
+//! \return Returns the contents of the interrupt status register or the
+//! contents of the raw interrupt status register for the specified
+//! PWM generator.
+//
+//*****************************************************************************
+uint32_t
+PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+
+    //
+    // Compute the generator's base address.
+    //
+    ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen);
+
+    //
+    // Read and return the specified generator's raw or enabled interrupt
+    // status.
+    //
+    if(bMasked == true)
+    {
+        return(HWREG(ui32Gen + PWM_O_X_ISC));
+    }
+    else
+    {
+        return(HWREG(ui32Gen + PWM_O_X_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the specified interrupt(s) for the specified PWM generator block.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator to query.  This parameter must be one
+//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32Ints specifies the interrupts to be cleared.
+//!
+//! This function clears the specified interrupt(s) by writing a 1 to the
+//! specified bits of the interrupt status register for the specified PWM
+//! generator.  The \e ui32Ints parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Ints)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32Ints &
+            ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU |
+              PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == 0);
+
+    //
+    // Clear the requested interrupts by writing ones to the specified bit
+    // of the module's interrupt enable register.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_ISC) = ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Enables generator and fault interrupts for a PWM module.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32GenFault contains the interrupts to be enabled.  This parameter
+//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1,
+//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
+//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
+//!
+//! This function unmasks the specified interrupt(s) by setting the specified
+//! bits of the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+                             PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+                             PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+    //
+    // Read the module's interrupt enable register and enable interrupts
+    // for the specified PWM generators.
+    //
+    HWREG(ui32Base + PWM_O_INTEN) |= ui32GenFault;
+}
+
+//*****************************************************************************
+//
+//! Disables generator and fault interrupts for a PWM module.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32GenFault contains the interrupts to be disabled.  This parameter
+//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1,
+//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
+//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
+//!
+//! This function masks the specified interrupt(s) by clearing the specified
+//! bits of the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+                             PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+                             PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+    //
+    // Read the module's interrupt enable register and disable interrupts
+    // for the specified PWM generators.
+    //
+    HWREG(ui32Base + PWM_O_INTEN) &= ~(ui32GenFault);
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//!
+//! This function clears the fault interrupt by writing to the appropriate bit
+//! of the interrupt status register for the selected PWM module.
+//!
+//! This function clears only the FAULT0 interrupt and is retained for
+//! backwards compatibility.  It is recommended that PWMFaultIntClearExt() be
+//! used instead because it supports all fault interrupts supported on devices
+//! with and without extended PWM fault handling support.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClear(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+
+    //
+    // Write the only writeable bit in the module's interrupt register.
+    //
+    HWREG(ui32Base + PWM_O_ISC) = PWM_ISC_INTFAULT0;
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt status for a PWM module.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status is returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3,
+//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and
+//! \b PWM_INT_FAULT3.
+//!
+//*****************************************************************************
+uint32_t
+PWMIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+
+    //
+    // Read and return either the module's raw or enabled interrupt status.
+    //
+    if(bMasked == true)
+    {
+        return(HWREG(ui32Base + PWM_O_ISC));
+    }
+    else
+    {
+        return(HWREG(ui32Base + PWM_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32FaultInts specifies the fault interrupts to clear.
+//!
+//! This function clears one or more fault interrupts by writing to the
+//!  appropriate bit of the PWM interrupt status register.  The parameter
+//! \e ui32FaultInts must be the logical OR of any of \b PWM_INT_FAULT0,
+//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
+//!
+//! The fault interrupts are derived by performing a logical OR of each of the 
+//! configured fault trigger signals for a given generator.  Therefore, these
+//! interrupts are not directly related to the four possible FAULTn inputs to 
+//! the device but indicate that a fault has been signaled to one of the four 
+//! possible PWM generators. 
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClearExt(uint32_t ui32Base, uint32_t ui32FaultInts)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT((ui32FaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+                              PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+    //
+    // Clear the supplied fault bits.
+    //
+    HWREG(ui32Base + PWM_O_ISC) = ui32FaultInts;
+}
+
+//*****************************************************************************
+//
+//! Configures the minimum fault period and fault pin senses for a given
+//! PWM generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator for which fault configuration is being
+//! set.  This function must be one of \b PWM_GEN_0, \b PWM_GEN_1,
+//! \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32MinFaultPeriod is the minimum fault active period expressed in
+//! PWM clock cycles.
+//! \param ui32FaultSenses indicates which sense of each FAULT input should be
+//! considered the ``asserted'' state.  Valid values are logical OR
+//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW.
+//!
+//! This function configures the minimum fault period for a given generator
+//! along with the sense of each of the 4 possible fault inputs.  The minimum
+//! fault period is expressed in PWM clock cycles and takes effect only if
+//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the
+//! \e ui32Config parameter.  When a fault input is asserted, the minimum fault
+//! period timer ensures that it remains asserted for at least the number of
+//! clock cycles specified.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen,
+                     uint32_t ui32MinFaultPeriod,
+                     uint32_t ui32FaultSenses)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT(ui32MinFaultPeriod < PWM_X_MINFLTPER_M);
+    ASSERT((ui32FaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW |
+                                PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW |
+                                PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW |
+                                PWM_FAULT3_SENSE_HIGH |
+                                PWM_FAULT3_SENSE_LOW)) == 0);
+
+    //
+    // Write the minimum fault period.
+    //
+    HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_MINFLTPER) =
+        ui32MinFaultPeriod;
+
+    //
+    // Write the fault senses.
+    //
+    HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSEN) =
+        ui32FaultSenses;
+}
+
+//*****************************************************************************
+//
+//! Configures the set of fault triggers for a given PWM generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator for which fault triggers are being set.
+//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ui32Group indicates the subset of possible faults that are to be
+//! configured.  This parameter must be \b PWM_FAULT_GROUP_0 or
+//! \b PWM_FAULT_GROUP_1.
+//! \param ui32FaultTriggers defines the set of inputs that are to contribute
+//! towards generation of the fault signal to the given PWM generator.  For
+//! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0,
+//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.  For
+//! \b PWM_FAULT_GROUP_1, this is the logical OR of \b PWM_FAULT_DCMP0,
+//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3,
+//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or
+//! \b PWM_FAULT_DCMP7.
+//!
+//! This function allows selection of the set of fault inputs that is combined
+//! to generate a fault condition to a given PWM generator.  By default, all
+//! generators use only FAULT0 (for backwards compatibility) but if
+//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the
+//! \e ui32Config parameter, extended fault handling is enabled and this
+//! function must be called to configure the fault triggers.
+//!
+//! The fault signal to the PWM generator is generated by ORing together each
+//! of the signals specified in the \e ui32FaultTriggers parameter after having
+//! adjusted the sense of each FAULTn input based on the configuration
+//! previously set using a call to PWMGenFaultConfigure().
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen,
+                      uint32_t ui32Group, uint32_t ui32FaultTriggers)
+{
+    //
+    // Check for valid parameters.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_0) ||
+           (ui32Group == PWM_FAULT_GROUP_1));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_0) &&
+           ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+                                   PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) ==
+            0));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_1) &&
+           ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+                                   PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+                                   PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+                                   PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
+
+    //
+    // Write the fault triggers to the appropriate register.
+    //
+    if(ui32Group == PWM_FAULT_GROUP_0)
+    {
+        HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0) =
+            ui32FaultTriggers;
+    }
+    else
+    {
+        HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1) =
+            ui32FaultTriggers;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the set of fault triggers currently configured for a given PWM
+//! generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator for which fault triggers are being
+//! queried.  This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1,
+//! \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32Group indicates the subset of faults that are being queried.
+//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//!
+//! This function allows an application to query the current set of inputs that
+//! contribute to the generation of a fault condition to a given PWM generator.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current fault triggers configured for the fault group
+//! provided.  For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of
+//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3.  For \b PWM_FAULT_GROUP_1, the return value is the
+//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1,
+//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4,
+//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
+//
+//*****************************************************************************
+uint32_t
+PWMGenFaultTriggerGet(uint32_t ui32Base, uint32_t ui32Gen,
+                      uint32_t ui32Group)
+{
+    //
+    // Check for valid parameters.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_0) ||
+           (ui32Group == PWM_FAULT_GROUP_1));
+
+    //
+    // Return the current fault triggers.
+    //
+    if(ui32Group == PWM_FAULT_GROUP_0)
+    {
+        return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0));
+    }
+    else
+    {
+        return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1));
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the current state of the fault triggers for a given PWM generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator for which fault trigger states are
+//! being queried.  This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1,
+//! \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32Group indicates the subset of faults that are being queried.
+//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//!
+//! This function allows an application to query the current state of each of
+//! the fault trigger inputs to a given PWM generator.  The current state of
+//! each fault trigger input is returned unless PWMGenConfigure() has
+//! previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in the
+//! \e ui32Config parameter, in which case the returned status is the latched
+//! fault trigger status.
+//!
+//! If latched faults are configured, the application must call
+//! PWMGenFaultClear() to clear each trigger.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current state of the fault triggers for the given PWM
+//! generator.  A set bit indicates that the associated trigger is active.
+//! For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of
+//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3.  For \b PWM_FAULT_GROUP_1, the return value is the
+//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1,
+//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4,
+//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
+//
+//*****************************************************************************
+uint32_t
+PWMGenFaultStatus(uint32_t ui32Base, uint32_t ui32Gen,
+                  uint32_t ui32Group)
+{
+    //
+    // Check for valid parameters.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_0) ||
+           (ui32Group == PWM_FAULT_GROUP_1));
+
+    //
+    // Return the current fault status.
+    //
+    if(ui32Group == PWM_FAULT_GROUP_0)
+    {
+        return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0));
+    }
+    else
+    {
+        return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears one or more latched fault triggers for a given PWM generator.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Gen is the PWM generator for which fault trigger states are
+//! being queried.  This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1,
+//! \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ui32Group indicates the subset of faults that are being queried.
+//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//! \param ui32FaultTriggers is the set of fault triggers which are to be
+//! cleared.
+//!
+//! This function allows an application to clear the fault triggers for a
+//! given PWM generator.  This function is only required if PWMGenConfigure()
+//! has previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in
+//! parameter \e ui32Config.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen,
+                 uint32_t ui32Group, uint32_t ui32FaultTriggers)
+{
+    //
+    // Check for valid parameters.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(_PWMGenValid(ui32Gen));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_0) ||
+           (ui32Group == PWM_FAULT_GROUP_1));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_0) &&
+           ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+                                   PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) ==
+            0));
+    ASSERT((ui32Group == PWM_FAULT_GROUP_1) &&
+           ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+                                   PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+                                   PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+                                   PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
+
+    //
+    // Clear the given faults.
+    //
+    if(ui32Group == PWM_FAULT_GROUP_0)
+    {
+        HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0) =
+            ui32FaultTriggers;
+    }
+    else
+    {
+        HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1) =
+            ui32FaultTriggers;
+    }
+}
+
+//*****************************************************************************
+///
+//! Sets the PWM clock configuration.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32Config is the configuration for the PWM clock; it must be one of
+//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4,
+//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, or
+//! \b PWM_SYSCLK_DIV_64.
+//!
+//! This function sets the PWM clock divider as the PWM clock source.  It also
+//! configures the clock frequency to the PWM module as a division of the
+//! system clock.  This clock is used by the PWM module to generate PWM
+//! signals; its rate forms the basis for all PWM signals.
+//!
+//! \note This function should not be used with TM4C123 devices.  For
+//! TM4C123 devices, the SysCtlPWMClockGet() function should be used.
+//!
+//! \note The clocking of the PWM is dependent upon the system clock rate as
+//! configured by SysCtlClockFreqSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMClockSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT((ui32Config == PWM_SYSCLK_DIV_2) ||
+           (ui32Config == PWM_SYSCLK_DIV_4) ||
+           (ui32Config == PWM_SYSCLK_DIV_8) ||
+           (ui32Config == PWM_SYSCLK_DIV_16) ||
+           (ui32Config == PWM_SYSCLK_DIV_32) ||
+           (ui32Config == PWM_SYSCLK_DIV_64));
+
+    //
+    // Set the PWM clock configuration into the PWM clock configuration
+    // register.
+    //
+    HWREG(ui32Base + PWM_O_CC) = ((HWREG(ui32Base + PWM_O_CC) &
+                                   ~(PWM_CC_USEPWM | PWM_CC_PWMDIV_M)) |
+                                  ui32Config);
+}
+
+//*****************************************************************************
+//
+//! Gets the current PWM clock configuration.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//!
+//! This function returns the current PWM clock configuration.
+//!
+//! \note This function should not be used with TM4C123 devices.  For
+//! TM4C123 devices, the SysCtlPWMClockGet() function should be used.
+//!
+//! \return Returns the current PWM clock configuration; is one of
+//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4,
+//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32,
+//! or \b PWM_SYSCLK_DIV_64.
+//
+//*****************************************************************************
+uint32_t
+PWMClockGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+
+    //
+    // Return the current PWM clock configuration.  Make sure that
+    // PWM_SYSCLK_DIV_1 is returned in all cases where the divider is disabled.
+    //
+    if(!(HWREG(ui32Base + PWM_O_CC) & PWM_CC_USEPWM))
+    {
+        //
+        // The divider is not active so reflect this in the value we return.
+        //
+        return(PWM_SYSCLK_DIV_1);
+    }
+    else
+    {
+        //
+        // The divider is active so directly return the masked register value.
+        //
+        return(HWREG(ui32Base + PWM_O_CC) & (PWM_CC_USEPWM | PWM_CC_PWMDIV_M));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the update mode or synchronization mode to the PWM outputs.
+//!
+//! \param ui32Base is the base address of the PWM module.
+//! \param ui32PWMOutBits are the PWM outputs to be modified.  This parameter
+//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT,
+//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT,
+//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT.
+//! \param ui32Mode specifies the enable update mode to use when enabling or
+//! disabling PWM outputs.
+//!
+//! This function sets one of three possible update modes to enable or disable
+//! the requested PWM outputs.  The \e ui32Mode parameter controls when changes
+//! made via calls to PWMOutputState() take effect.  Possible values are:
+//!
+//! - \b PWM_OUTPUT_MODE_NO_SYNC, which enables/disables changes to take effect
+//! immediately.
+//! - \b PWM_OUTPUT_MODE_SYNC_LOCAL, which causes changes to take effect when
+//! the local PWM generator's count next reaches 0.
+//! - \b PWM_OUTPUT_MODE_SYNC_GLOBAL, which causes changes to take effect when
+//! the local PWM generator's count next reaches 0 following a call to
+//! PWMSyncUpdate() which specifies the same generator in its \e ui32GenBits
+//! parameter.
+//!
+//! \note This function is only available on Snowflake class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputUpdateMode(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+                    uint32_t ui32Mode)
+{
+    uint_fast8_t ui8Index;
+    uint32_t ui32PWMOutputMask;
+    uint32_t ui32UpdateValueMask;
+    uint32_t ui32UpdateValue;
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE));
+    ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+                                PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+                                PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+    ASSERT((ui32Mode == PWM_OUTPUT_MODE_NO_SYNC) ||
+           (ui32Mode == PWM_OUTPUT_MODE_SYNC_LOCAL) ||
+           (ui32Mode == PWM_OUTPUT_MODE_SYNC_GLOBAL));
+
+    //
+    // Initialize the local variables
+    //
+    ui8Index = 0;
+    ui32PWMOutputMask = 1;
+    ui32UpdateValue = 0;
+    ui32UpdateValueMask = 0;
+
+    //
+    // Loop to find out which PWM outputs are to be modified.
+    //
+    while(ui8Index < 8)
+    {
+        //
+        // Check if this PWM output is to be modified.
+        //
+        if(ui32PWMOutputMask & ui32PWMOutBits)
+        {
+            //
+            // Set the update mode value for the requested PWM output by
+            // writing to the appropriate field.
+            //
+            ui32UpdateValue |= ui32Mode << (ui8Index * 2);
+
+            //
+            // Compute the mask for the bits to be updated.
+            //
+            ui32UpdateValueMask |= 3 << (ui8Index * 2);
+        }
+
+        //
+        // Update the PWM output to be checked and the index.
+        //
+        ui32PWMOutputMask = ui32PWMOutputMask << 1;
+        ui8Index++;
+    }
+
+    //
+    // Read the Enable Update register and mask the bits that are to be
+    // updated.
+    //
+    ui32Temp = ~ui32UpdateValueMask & HWREG(ui32Base + PWM_O_ENUPD);
+
+    //
+    // Write the updated values to Enable Update register.
+    //
+    HWREG(ui32Base + PWM_O_ENUPD) = ui32Temp | ui32UpdateValue;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/pwm.h b/bsp/tm4c129x/libraries/driverlib/pwm.h
new file mode 100644
index 0000000000..823b853bcc
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/pwm.h
@@ -0,0 +1,326 @@
+//*****************************************************************************
+//
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_PWM_H__
+#define __DRIVERLIB_PWM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are passed to PWMGenConfigure() as the ui32Config
+// parameter and specify the configuration of the PWM generator.
+//
+//*****************************************************************************
+#define PWM_GEN_MODE_DOWN       0x00000000  // Down count mode
+#define PWM_GEN_MODE_UP_DOWN    0x00000002  // Up/Down count mode
+#define PWM_GEN_MODE_SYNC       0x00000038  // Synchronous updates
+#define PWM_GEN_MODE_NO_SYNC    0x00000000  // Immediate updates
+#define PWM_GEN_MODE_DBG_RUN    0x00000004  // Continue running in debug mode
+#define PWM_GEN_MODE_DBG_STOP   0x00000000  // Stop running in debug mode
+#define PWM_GEN_MODE_FAULT_LATCHED \
+                                0x00040000  // Fault is latched
+#define PWM_GEN_MODE_FAULT_UNLATCHED \
+                                0x00000000  // Fault is not latched
+#define PWM_GEN_MODE_FAULT_MINPER \
+                                0x00020000  // Enable min fault period
+#define PWM_GEN_MODE_FAULT_NO_MINPER \
+                                0x00000000  // Disable min fault period
+#define PWM_GEN_MODE_FAULT_EXT  0x00010000  // Enable extended fault support
+#define PWM_GEN_MODE_FAULT_LEGACY \
+                                0x00000000  // Disable extended fault support
+#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000  // Deadband updates occur
+                                            // immediately
+#define PWM_GEN_MODE_DB_SYNC_LOCAL \
+                                0x0000A800  // Deadband updates locally
+                                            // synchronized
+#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
+                                0x0000FC00  // Deadband updates globally
+                                            // synchronized
+#define PWM_GEN_MODE_GEN_NO_SYNC \
+                                0x00000000  // Generator mode updates occur
+                                            // immediately
+#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
+                                0x00000280  // Generator mode updates locally
+                                            // synchronized
+#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
+                                0x000003C0  // Generator mode updates globally
+                                            // synchronized
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM generator interrupts and
+// triggers.
+//
+//*****************************************************************************
+#define PWM_INT_CNT_ZERO        0x00000001  // Int if COUNT = 0
+#define PWM_INT_CNT_LOAD        0x00000002  // Int if COUNT = LOAD
+#define PWM_INT_CNT_AU          0x00000004  // Int if COUNT = CMPA U
+#define PWM_INT_CNT_AD          0x00000008  // Int if COUNT = CMPA D
+#define PWM_INT_CNT_BU          0x00000010  // Int if COUNT = CMPA U
+#define PWM_INT_CNT_BD          0x00000020  // Int if COUNT = CMPA D
+#define PWM_TR_CNT_ZERO         0x00000100  // Trig if COUNT = 0
+#define PWM_TR_CNT_LOAD         0x00000200  // Trig if COUNT = LOAD
+#define PWM_TR_CNT_AU           0x00000400  // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_AD           0x00000800  // Trig if COUNT = CMPA D
+#define PWM_TR_CNT_BU           0x00001000  // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_BD           0x00002000  // Trig if COUNT = CMPA D
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM interrupts.
+//
+//*****************************************************************************
+#define PWM_INT_GEN_0           0x00000001  // Generator 0 interrupt
+#define PWM_INT_GEN_1           0x00000002  // Generator 1 interrupt
+#define PWM_INT_GEN_2           0x00000004  // Generator 2 interrupt
+#define PWM_INT_GEN_3           0x00000008  // Generator 3 interrupt
+#define PWM_INT_FAULT0          0x00010000  // Fault0 interrupt
+#define PWM_INT_FAULT1          0x00020000  // Fault1 interrupt
+#define PWM_INT_FAULT2          0x00040000  // Fault2 interrupt
+#define PWM_INT_FAULT3          0x00080000  // Fault3 interrupt
+#define PWM_INT_FAULT_M         0x000F0000  // Fault interrupt source mask
+
+//*****************************************************************************
+//
+// Defines to identify the generators within a module.
+//
+//*****************************************************************************
+#define PWM_GEN_0               0x00000040  // Offset address of Gen0
+#define PWM_GEN_1               0x00000080  // Offset address of Gen1
+#define PWM_GEN_2               0x000000C0  // Offset address of Gen2
+#define PWM_GEN_3               0x00000100  // Offset address of Gen3
+
+#define PWM_GEN_0_BIT           0x00000001  // Bit-wise ID for Gen0
+#define PWM_GEN_1_BIT           0x00000002  // Bit-wise ID for Gen1
+#define PWM_GEN_2_BIT           0x00000004  // Bit-wise ID for Gen2
+#define PWM_GEN_3_BIT           0x00000008  // Bit-wise ID for Gen3
+
+#define PWM_GEN_EXT_0           0x00000800  // Offset of Gen0 ext address range
+#define PWM_GEN_EXT_1           0x00000880  // Offset of Gen1 ext address range
+#define PWM_GEN_EXT_2           0x00000900  // Offset of Gen2 ext address range
+#define PWM_GEN_EXT_3           0x00000980  // Offset of Gen3 ext address range
+
+//*****************************************************************************
+//
+// Defines to identify the outputs within a module.
+//
+//*****************************************************************************
+#define PWM_OUT_0               0x00000040  // Encoded offset address of PWM0
+#define PWM_OUT_1               0x00000041  // Encoded offset address of PWM1
+#define PWM_OUT_2               0x00000082  // Encoded offset address of PWM2
+#define PWM_OUT_3               0x00000083  // Encoded offset address of PWM3
+#define PWM_OUT_4               0x000000C4  // Encoded offset address of PWM4
+#define PWM_OUT_5               0x000000C5  // Encoded offset address of PWM5
+#define PWM_OUT_6               0x00000106  // Encoded offset address of PWM6
+#define PWM_OUT_7               0x00000107  // Encoded offset address of PWM7
+
+#define PWM_OUT_0_BIT           0x00000001  // Bit-wise ID for PWM0
+#define PWM_OUT_1_BIT           0x00000002  // Bit-wise ID for PWM1
+#define PWM_OUT_2_BIT           0x00000004  // Bit-wise ID for PWM2
+#define PWM_OUT_3_BIT           0x00000008  // Bit-wise ID for PWM3
+#define PWM_OUT_4_BIT           0x00000010  // Bit-wise ID for PWM4
+#define PWM_OUT_5_BIT           0x00000020  // Bit-wise ID for PWM5
+#define PWM_OUT_6_BIT           0x00000040  // Bit-wise ID for PWM6
+#define PWM_OUT_7_BIT           0x00000080  // Bit-wise ID for PWM7
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_0.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_0       0
+
+#define PWM_FAULT_FAULT0        0x00000001
+#define PWM_FAULT_FAULT1        0x00000002
+#define PWM_FAULT_FAULT2        0x00000004
+#define PWM_FAULT_FAULT3        0x00000008
+#define PWM_FAULT_ACMP0         0x00010000
+#define PWM_FAULT_ACMP1         0x00020000
+#define PWM_FAULT_ACMP2         0x00040000
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_1.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_1       1
+
+#define PWM_FAULT_DCMP0         0x00000001
+#define PWM_FAULT_DCMP1         0x00000002
+#define PWM_FAULT_DCMP2         0x00000004
+#define PWM_FAULT_DCMP3         0x00000008
+#define PWM_FAULT_DCMP4         0x00000010
+#define PWM_FAULT_DCMP5         0x00000020
+#define PWM_FAULT_DCMP6         0x00000040
+#define PWM_FAULT_DCMP7         0x00000080
+
+//*****************************************************************************
+//
+// Defines to identify the sense of each of the external FAULTn signals
+//
+//*****************************************************************************
+#define PWM_FAULT0_SENSE_HIGH   0x00000000
+#define PWM_FAULT0_SENSE_LOW    0x00000001
+#define PWM_FAULT1_SENSE_HIGH   0x00000000
+#define PWM_FAULT1_SENSE_LOW    0x00000002
+#define PWM_FAULT2_SENSE_HIGH   0x00000000
+#define PWM_FAULT2_SENSE_LOW    0x00000004
+#define PWM_FAULT3_SENSE_HIGH   0x00000000
+#define PWM_FAULT3_SENSE_LOW    0x00000008
+
+//*****************************************************************************
+//
+// Defines that can be passed to the PWMClockSet() API as the ui32Config
+// parameter, and can be returned by the PWMClockGet() API.
+//
+//*****************************************************************************
+#define PWM_SYSCLK_DIV_1        0x00000000  // PWM clock is system clock
+#define PWM_SYSCLK_DIV_2        0x00000100  // PWM clock is system clock /2
+#define PWM_SYSCLK_DIV_4        0x00000101  // PWM clock is system clock /4
+#define PWM_SYSCLK_DIV_8        0x00000102  // PWM clock is system clock /8
+#define PWM_SYSCLK_DIV_16       0x00000103  // PWM clock is system clock /16
+#define PWM_SYSCLK_DIV_32       0x00000104  // PWM clock is system clock /32
+#define PWM_SYSCLK_DIV_64       0x00000105  // PWM clock is system clock /64
+
+//*****************************************************************************
+//
+// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode
+// to use when enabling or disabling outputs using PWMOutputState().
+//
+//*****************************************************************************
+#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately
+#define PWM_OUTPUT_MODE_SYNC_LOCAL \
+                                0x00000002 // Updates are locally synchronized
+#define PWM_OUTPUT_MODE_SYNC_GLOBAL \
+                                0x00000003 // Updates are globally synchronized
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen,
+                            uint32_t ui32Config);
+extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen,
+                            uint32_t ui32Period);
+extern uint32_t PWMGenPeriodGet(uint32_t ui32Base,
+                                uint32_t ui32Gen);
+extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen);
+extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen);
+extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut,
+                             uint32_t ui32Width);
+extern uint32_t PWMPulseWidthGet(uint32_t ui32Base,
+                                 uint32_t ui32PWMOut);
+extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen,
+                              uint16_t ui16Rise, uint16_t ui16Fall);
+extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen);
+extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits);
+extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits);
+extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+                           bool bEnable);
+extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+                            bool bInvert);
+extern void PWMOutputFaultLevel(uint32_t ui32Base,
+                                uint32_t ui32PWMOutBits,
+                                bool bDriveHigh);
+extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits,
+                           bool bFaultSuppress);
+extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen,
+                              void (*pfnIntHandler)(void));
+extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen);
+extern void PWMFaultIntRegister(uint32_t ui32Base,
+                                void (*pfnIntHandler)(void));
+extern void PWMFaultIntUnregister(uint32_t ui32Base);
+extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen,
+                                uint32_t ui32IntTrig);
+extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen,
+                                 uint32_t ui32IntTrig);
+extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen,
+                                bool bMasked);
+extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen,
+                           uint32_t ui32Ints);
+extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault);
+extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault);
+extern void PWMFaultIntClear(uint32_t ui32Base);
+extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked);
+extern void PWMFaultIntClearExt(uint32_t ui32Base,
+                                uint32_t ui32FaultInts);
+extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen,
+                                 uint32_t ui32MinFaultPeriod,
+                                 uint32_t ui32FaultSenses);
+extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen,
+                                  uint32_t ui32Group,
+                                  uint32_t ui32FaultTriggers);
+extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base,
+                                      uint32_t ui32Gen,
+                                      uint32_t ui32Group);
+extern uint32_t PWMGenFaultStatus(uint32_t ui32Base,
+                                  uint32_t ui32Gen,
+                                  uint32_t ui32Group);
+extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen,
+                             uint32_t ui32Group,
+                             uint32_t ui32FaultTriggers);
+extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config);
+extern uint32_t PWMClockGet(uint32_t ui32Base);
+extern void PWMOutputUpdateMode(uint32_t ui32Base,
+                                uint32_t ui32PWMOutBits,
+                                uint32_t ui32Mode);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_PWM_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/qei.c b/bsp/tm4c129x/libraries/driverlib/qei.c
new file mode 100644
index 0000000000..d450615fb6
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/qei.c
@@ -0,0 +1,693 @@
+//*****************************************************************************
+//
+// qei.c - Driver for the Quadrature Encoder with Index.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup qei_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_qei.h"
+#include "inc/hw_types.h"
+#include "inc/hw_sysctl.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/qei.h"
+
+//*****************************************************************************
+//
+//! Enables the quadrature encoder.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function enables operation of the quadrature encoder module.  The
+//! module must be configured before it is enabled.
+//!
+//! \sa QEIConfigure()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Enable the QEI module.
+    //
+    HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the quadrature encoder.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function disables operation of the quadrature encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Disable the QEI module.
+    //
+    HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Configures the quadrature encoder.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32Config is the configuration for the quadrature encoder.  See
+//! below for a description of this parameter.
+//! \param ui32MaxPosition specifies the maximum position value.
+//!
+//! This function configures the operation of the quadrature encoder.  The
+//! \e ui32Config parameter provides the configuration of the encoder and is
+//! the logical OR of several values:
+//!
+//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges
+//!   on channel A or on both channels A and B should be counted by the
+//!   position integrator and velocity accumulator.
+//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the
+//!   position integrator should be reset when the index pulse is detected.
+//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if
+//!   quadrature signals are being provided on ChA and ChB, or if a direction
+//!   signal and a clock are being provided instead.
+//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
+//!   provided on ChA and ChB should be swapped before being processed.
+//!
+//! \e ui32MaxPosition is the maximum value of the position integrator and is
+//! the value used to reset the position capture when in index reset mode and
+//! moving in the reverse (negative) direction.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIConfigure(uint32_t ui32Base, uint32_t ui32Config,
+             uint32_t ui32MaxPosition)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Write the new configuration to the hardware.
+    //
+    HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) &
+                                    ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
+                                      QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
+                                   ui32Config);
+
+    //
+    // Set the maximum position.
+    //
+    HWREG(ui32Base + QEI_O_MAXPOS) = ui32MaxPosition;
+}
+
+//*****************************************************************************
+//
+//! Gets the current encoder position.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function returns the current position of the encoder.  Depending upon
+//! the configuration of the encoder, and the incident of an index pulse, this
+//! value may or may not contain the expected data (that is, if in reset on
+//! index mode, if an index pulse has not been encountered, the position
+//! counter is not yet aligned with the index pulse).
+//!
+//! \return The current position of the encoder.
+//
+//*****************************************************************************
+uint32_t
+QEIPositionGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Return the current position counter.
+    //
+    return(HWREG(ui32Base + QEI_O_POS));
+}
+
+//*****************************************************************************
+//
+//! Sets the current encoder position.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32Position is the new position for the encoder.
+//!
+//! This function sets the current position of the encoder; the encoder
+//! position is then measured relative to this value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Set the position counter.
+    //
+    HWREG(ui32Base + QEI_O_POS) = ui32Position;
+}
+
+//*****************************************************************************
+//
+//! Gets the current direction of rotation.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function returns the current direction of rotation.  In this case,
+//! current means the most recently detected direction of the encoder; it may
+//! not be presently moving but this is the direction it last moved before it
+//! stopped.
+//!
+//! \return Returns 1 if moving in the forward direction or -1 if moving in the
+//! reverse direction.
+//
+//*****************************************************************************
+int32_t
+QEIDirectionGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Return the direction of rotation.
+    //
+    return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the encoder error indicator.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function returns the error indicator for the quadrature encoder.  It
+//! is an error for both of the signals of the quadrature input to change at
+//! the same time.
+//!
+//! \return Returns \b true if an error has occurred and \b false otherwise.
+//
+//*****************************************************************************
+bool
+QEIErrorGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Return the error indicator.
+    //
+    return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Enables the velocity capture.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function enables operation of the velocity capture in the quadrature
+//! encoder module.  The module must be configured before velocity capture is
+//! enabled.
+//!
+//! \sa QEIVelocityConfigure() and QEIEnable()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Enable the velocity capture.
+    //
+    HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_VELEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the velocity capture.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function disables operation of the velocity capture in the quadrature
+//! encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Disable the velocity capture.
+    //
+    HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the velocity capture.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32PreDiv specifies the predivider applied to the input quadrature
+//! signal before it is counted; can be one of \b QEI_VELDIV_1,
+//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16,
+//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128.
+//! \param ui32Period specifies the number of clock ticks over which to measure
+//! the velocity; must be non-zero.
+//!
+//! This function configures the operation of the velocity capture portion of
+//! the quadrature encoder.  The position increment signal is predivided as
+//! specified by \e ui32PreDiv before being accumulated by the velocity
+//! capture.  The divided signal is accumulated over \e ui32Period system clock
+//! before being saved and resetting the accumulator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,
+                     uint32_t ui32Period)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+    ASSERT(!(ui32PreDiv & ~(QEI_CTL_VELDIV_M)));
+    ASSERT(ui32Period != 0);
+
+    //
+    // Set the velocity predivider.
+    //
+    HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) &
+                                    ~(QEI_CTL_VELDIV_M)) | ui32PreDiv);
+
+    //
+    // Set the timer period.
+    //
+    HWREG(ui32Base + QEI_O_LOAD) = ui32Period - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the current encoder speed.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function returns the current speed of the encoder.  The value returned
+//! is the number of pulses detected in the specified time period; this number
+//! can be multiplied by the number of time periods per second and divided by
+//! the number of pulses per revolution to obtain the number of revolutions per
+//! second.
+//!
+//! \return Returns the number of pulses captured in the given time period.
+//
+//*****************************************************************************
+uint32_t
+QEIVelocityGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Return the speed capture value.
+    //
+    return(HWREG(ui32Base + QEI_O_SPEED));
+}
+
+//*****************************************************************************
+//
+//! Returns the quadrature encoder interrupt number.
+//!
+//! \param ui32Base is the base address of the selected quadrature encoder
+//!
+//! This function returns the interrupt number for the quadrature encoder with
+//! the base address passed in the \e ui32Base parameter.
+//!
+//! \return Returns a quadrature encoder interrupt number or 0 if the interrupt
+//! does not exist.
+//
+//*****************************************************************************
+static uint32_t
+_QEIIntNumberGet(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Find the valid interrupt number for this quadrature encoder.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        if(ui32Base == QEI0_BASE)
+        {
+            ui32Int = INT_QEI0_TM4C123;
+        }
+        else
+        {
+            ui32Int = INT_QEI1_TM4C123;
+        }
+    }
+    else if(CLASS_IS_TM4C129)
+    {
+        if(ui32Base == QEI0_BASE)
+        {
+            ui32Int = INT_QEI0_TM4C129;
+        }
+        else
+        {
+            ui32Int = 0;
+        }
+    }
+    else
+    {
+        ui32Int = 0;
+    }
+
+    return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the quadrature encoder interrupt.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! quadrature encoder interrupt occurs.
+//!
+//! This function registers the handler to be called when a quadrature encoder
+//! interrupt occurs.  This function enables the global interrupt in the
+//! interrupt controller; specific quadrature encoder interrupts must be
+//! enabled via QEIIntEnable().  It is the interrupt handler's responsibility
+//! to clear the interrupt source via QEIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Determine the interrupt number based on the QEI module.
+    //
+    ui32Int = _QEIIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the quadrature encoder interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the quadrature encoder interrupt.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function unregisters the handler to be called when a quadrature
+//! encoder interrupt occurs.  This function also masks off the interrupt in
+//! the interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Determine the interrupt number based on the QEI module.
+    //
+    ui32Int = _QEIIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual quadrature encoder interrupt sources.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! This function enables the indicated quadrature encoder interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(ui32Base + QEI_O_INTEN) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual quadrature encoder interrupt sources.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
+//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
+//!
+//! This function disables the indicated quadrature encoder interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(ui32Base + QEI_O_INTEN) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the quadrature encoder
+//! module.  Either the raw interrupt status or the status of interrupts that
+//! are allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
+//
+//*****************************************************************************
+uint32_t
+QEIIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + QEI_O_ISC));
+    }
+    else
+    {
+        return(HWREG(ui32Base + QEI_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears quadrature encoder interrupt sources.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
+//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
+//!
+//! The specified quadrature encoder interrupt sources are cleared, so that
+//! they no longer assert.  This function must be called in the interrupt
+//! handler to keep the interrupt from being triggered again immediately upon
+//! exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(ui32Base + QEI_O_ISC) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/qei.h b/bsp/tm4c129x/libraries/driverlib/qei.h
new file mode 100644
index 0000000000..3ede01c933
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/qei.h
@@ -0,0 +1,128 @@
+//*****************************************************************************
+//
+// qei.h - Prototypes for the Quadrature Encoder Driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_QEI_H__
+#define __DRIVERLIB_QEI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIConfigure as the ui32Config paramater.
+//
+//*****************************************************************************
+#define QEI_CONFIG_CAPTURE_A    0x00000000  // Count on ChA edges only
+#define QEI_CONFIG_CAPTURE_A_B  0x00000008  // Count on ChA and ChB edges
+#define QEI_CONFIG_NO_RESET     0x00000000  // Do not reset on index pulse
+#define QEI_CONFIG_RESET_IDX    0x00000010  // Reset position on index pulse
+#define QEI_CONFIG_QUADRATURE   0x00000000  // ChA and ChB are quadrature
+#define QEI_CONFIG_CLOCK_DIR    0x00000004  // ChA and ChB are clock and dir
+#define QEI_CONFIG_NO_SWAP      0x00000000  // Do not swap ChA and ChB
+#define QEI_CONFIG_SWAP         0x00000002  // Swap ChA and ChB
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv
+// parameter.
+//
+//*****************************************************************************
+#define QEI_VELDIV_1            0x00000000  // Predivide by 1
+#define QEI_VELDIV_2            0x00000040  // Predivide by 2
+#define QEI_VELDIV_4            0x00000080  // Predivide by 4
+#define QEI_VELDIV_8            0x000000C0  // Predivide by 8
+#define QEI_VELDIV_16           0x00000100  // Predivide by 16
+#define QEI_VELDIV_32           0x00000140  // Predivide by 32
+#define QEI_VELDIV_64           0x00000180  // Predivide by 64
+#define QEI_VELDIV_128          0x000001C0  // Predivide by 128
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
+// as the ui32IntFlags parameter, and returned by QEIGetIntStatus.
+//
+//*****************************************************************************
+#define QEI_INTERROR            0x00000008  // Phase error detected
+#define QEI_INTDIR              0x00000004  // Direction change
+#define QEI_INTTIMER            0x00000002  // Velocity timer expired
+#define QEI_INTINDEX            0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void QEIEnable(uint32_t ui32Base);
+extern void QEIDisable(uint32_t ui32Base);
+extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config,
+                         uint32_t ui32MaxPosition);
+extern uint32_t QEIPositionGet(uint32_t ui32Base);
+extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position);
+extern int32_t QEIDirectionGet(uint32_t ui32Base);
+extern bool QEIErrorGet(uint32_t ui32Base);
+extern void QEIVelocityEnable(uint32_t ui32Base);
+extern void QEIVelocityDisable(uint32_t ui32Base);
+extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,
+                                 uint32_t ui32Period);
+extern uint32_t QEIVelocityGet(uint32_t ui32Base);
+extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void QEIIntUnregister(uint32_t ui32Base);
+extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked);
+extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_QEI_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/readme.txt b/bsp/tm4c129x/libraries/driverlib/readme.txt
new file mode 100644
index 0000000000..719ddfcd9c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/readme.txt
@@ -0,0 +1,36 @@
+This project will build the TivaWare Peripheral Driver Library.
+
+-------------------------------------------------------------------------------
+
+Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+Software License Agreement
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+
+  Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the  
+  distribution.
+
+  Neither the name of Texas Instruments Incorporated nor the names of
+  its contributors may be used to endorse or promote products derived
+  from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
diff --git a/bsp/tm4c129x/libraries/driverlib/rom.h b/bsp/tm4c129x/libraries/driverlib/rom.h
new file mode 100644
index 0000000000..ba01104676
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/rom.h
@@ -0,0 +1,6990 @@
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_ROM_H__
+#define __DRIVERLIB_ROM_H__
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// ROM selection labels changed between TivaWare 2.0.1 and 2.1.  The following
+// labels are intended to ensure backwards compatibility for applications
+// which have not yet been updated to use the replacement labels.
+//
+//*****************************************************************************
+#ifdef TARGET_IS_SNOWFLAKE_RA0
+#define TARGET_IS_TM4C129_RA0
+#endif
+#ifdef TARGET_IS_SNOWFLAKE_RA1
+#define TARGET_IS_TM4C129_RA1
+#endif
+#ifdef TARGET_IS_BLIZZARD_RA1
+#define TARGET_IS_TM4C123_RA1
+#endif
+#ifdef TARGET_IS_BLIZZARD_RA2
+#define TARGET_IS_TM4C123_RA2
+#endif
+#ifdef TARGET_IS_BLIZZARD_RA3
+#define TARGET_IS_TM4C123_RA3
+#endif
+#ifdef TARGET_IS_BLIZZARD_RB0
+#define TARGET_IS_TM4C123_RB0
+#endif
+#ifdef TARGET_IS_BLIZZARD_RB1
+#define TARGET_IS_TM4C123_RB1
+#endif
+#endif
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE            ((uint32_t *)0x01000010)
+#define ROM_VERSION             (ROM_APITABLE[0])
+#define ROM_UARTTABLE           ((uint32_t *)(ROM_APITABLE[1]))
+#define ROM_SSITABLE            ((uint32_t *)(ROM_APITABLE[2]))
+#define ROM_I2CTABLE            ((uint32_t *)(ROM_APITABLE[3]))
+#define ROM_GPIOTABLE           ((uint32_t *)(ROM_APITABLE[4]))
+#define ROM_ADCTABLE            ((uint32_t *)(ROM_APITABLE[5]))
+#define ROM_COMPARATORTABLE     ((uint32_t *)(ROM_APITABLE[6]))
+#define ROM_FLASHTABLE          ((uint32_t *)(ROM_APITABLE[7]))
+#define ROM_PWMTABLE            ((uint32_t *)(ROM_APITABLE[8]))
+#define ROM_QEITABLE            ((uint32_t *)(ROM_APITABLE[9]))
+#define ROM_SYSTICKTABLE        ((uint32_t *)(ROM_APITABLE[10]))
+#define ROM_TIMERTABLE          ((uint32_t *)(ROM_APITABLE[11]))
+#define ROM_WATCHDOGTABLE       ((uint32_t *)(ROM_APITABLE[12]))
+#define ROM_SYSCTLTABLE         ((uint32_t *)(ROM_APITABLE[13]))
+#define ROM_INTERRUPTTABLE      ((uint32_t *)(ROM_APITABLE[14]))
+#define ROM_USBTABLE            ((uint32_t *)(ROM_APITABLE[16]))
+#define ROM_UDMATABLE           ((uint32_t *)(ROM_APITABLE[17]))
+#define ROM_CANTABLE            ((uint32_t *)(ROM_APITABLE[18]))
+#define ROM_HIBERNATETABLE      ((uint32_t *)(ROM_APITABLE[19]))
+#define ROM_MPUTABLE            ((uint32_t *)(ROM_APITABLE[20]))
+#define ROM_SOFTWARETABLE       ((uint32_t *)(ROM_APITABLE[21]))
+#define ROM_EPITABLE            ((uint32_t *)(ROM_APITABLE[23]))
+#define ROM_EEPROMTABLE         ((uint32_t *)(ROM_APITABLE[24]))
+#define ROM_FPUTABLE            ((uint32_t *)(ROM_APITABLE[26]))
+#define ROM_SMBUSTABLE          ((uint32_t *)(ROM_APITABLE[29]))
+#define ROM_SYSEXCTABLE         ((uint32_t *)(ROM_APITABLE[30]))
+#define ROM_ONEWIRETABLE        ((uint32_t *)(ROM_APITABLE[34]))
+#define ROM_SPIFLASHTABLE       ((uint32_t *)(ROM_APITABLE[38]))
+#define ROM_LCDTABLE            ((uint32_t *)(ROM_APITABLE[41]))
+#define ROM_EMACTABLE           ((uint32_t *)(ROM_APITABLE[42]))
+#define ROM_AESTABLE            ((uint32_t *)(ROM_APITABLE[43]))
+#define ROM_CRCTABLE            ((uint32_t *)(ROM_APITABLE[44]))
+#define ROM_DESTABLE            ((uint32_t *)(ROM_APITABLE[45]))
+#define ROM_SHAMD5TABLE         ((uint32_t *)(ROM_APITABLE[46]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceDataGet                                                \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32SequenceNum,                               \
+                      uint32_t *pui32Buffer))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32SequenceNum,                              \
+                       bool bMasked))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceEnable                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceDisable                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceConfigure                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum,                                  \
+                   uint32_t ui32Trigger,                                      \
+                   uint32_t ui32Priority))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceStepConfigure                                          \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum,                                  \
+                   uint32_t ui32Step,                                         \
+                   uint32_t ui32Config))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceOverflow                                               \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32SequenceNum))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceOverflowClear                                          \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceUnderflow                                              \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32SequenceNum))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceUnderflowClear                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCProcessorTrigger                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCHardwareOversampleConfigure                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Factor))ROM_ADCTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorConfigure                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp,                                         \
+                   uint32_t ui32Config))ROM_ADCTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorRegionSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp,                                         \
+                   uint32_t ui32LowRef,                                       \
+                   uint32_t ui32HighRef))ROM_ADCTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorReset                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp,                                         \
+                   bool bTrigger,                                             \
+                   bool bInterrupt))ROM_ADCTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorIntDisable                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorIntEnable                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorIntStatus                                            \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCComparatorIntClear                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Status))ROM_ADCTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCReferenceSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Ref))ROM_ADCTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCReferenceGet                                                   \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCPhaseDelaySet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Phase))ROM_ADCTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCPhaseDelayGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntClearEx                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_ADCTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntDisableEx                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_ADCTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntEnableEx                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_ADCTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCIntStatusEx                                                    \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_ADCTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceDMAEnable                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCSequenceDMADisable                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SequenceNum))ROM_ADCTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ADCBusy                                                           \
+        ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the AES API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_AESTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESAuthLengthSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Length))ROM_AESTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESConfigSet                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_AESTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataAuth                                                       \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src,                                        \
+                   uint32_t ui32Length,                                       \
+                   uint32_t *pui32Tag))ROM_AESTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataProcess                                                    \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src,                                        \
+                   uint32_t *pui32Dest,                                       \
+                   uint32_t ui32Length))ROM_AESTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataProcessAuth                                                \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src,                                        \
+                   uint32_t *pui32Dest,                                       \
+                   uint32_t ui32Length,                                       \
+                   uint32_t *pui32AuthSrc,                                    \
+                   uint32_t ui32AuthLength,                                   \
+                   uint32_t *pui32Tag))ROM_AESTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataRead                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Dest))ROM_AESTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataReadNonBlocking                                            \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Dest))ROM_AESTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataWrite                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_AESTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDataWriteNonBlocking                                           \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_AESTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDMADisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags))ROM_AESTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESDMAEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags))ROM_AESTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_AESTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_AESTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_AESTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESIVSet                                                          \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32IVdata))ROM_AESTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESKey1Set                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Key,                                        \
+                   uint32_t ui32Keysize))ROM_AESTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESKey2Set                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Key,                                        \
+                   uint32_t ui32Keysize))ROM_AESTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESKey3Set                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Key))ROM_AESTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESLengthSet                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint64_t ui64Length))ROM_AESTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESReset                                                          \
+        ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESTagRead                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32TagData))ROM_AESTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_AESIVRead                                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32IVdata))ROM_AESTABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAN API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntClr))ROM_CANTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANInit                                                           \
+        ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANEnable                                                         \
+        ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANDisable                                                        \
+        ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANBitTimingSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   tCANBitClkParms *psClkParms))ROM_CANTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANBitTimingGet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   tCANBitClkParms *psClkParms))ROM_CANTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANMessageSet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32ObjID,                                        \
+                   tCANMsgObject *psMsgObject,                                \
+                   tMsgObjType eMsgType))ROM_CANTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANMessageGet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32ObjID,                                        \
+                   tCANMsgObject *psMsgObject,                                \
+                   bool bClrPendingInt))ROM_CANTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANStatusGet                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       tCANStsReg eStatusReg))ROM_CANTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANMessageClear                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32ObjID))ROM_CANTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_CANTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_CANTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANRetryGet                                                       \
+        ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANRetrySet                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bAutoRetry))ROM_CANTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANErrCntrGet                                                     \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32RxCount,                                    \
+                   uint32_t *pui32TxCount))ROM_CANTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CANBitRateSet                                                     \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32SourceClock,                              \
+                       uint32_t ui32BitRate))ROM_CANTABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comparator API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorIntClear                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp))ROM_COMPARATORTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorConfigure                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp,                                         \
+                   uint32_t ui32Config))ROM_COMPARATORTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorRefSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Ref))ROM_COMPARATORTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorValueGet                                                \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp))ROM_COMPARATORTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorIntEnable                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp))ROM_COMPARATORTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorIntDisable                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp))ROM_COMPARATORTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_ComparatorIntStatus                                               \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Comp,                                         \
+                   bool bMasked))ROM_COMPARATORTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CRC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CRCConfigSet                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CRCConfig))ROM_CRCTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CRCDataProcess                                                    \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t *pui32DataIn,                                 \
+                       uint32_t ui32DataLength,                               \
+                       bool bPPResult))ROM_CRCTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CRCDataWrite                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Data))ROM_CRCTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CRCResultRead                                                     \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bPPResult))ROM_CRCTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_CRCSeedSet                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Seed))ROM_CRCTABLE[4])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the DES API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_DESTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESConfigSet                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_DESTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDataRead                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Dest))ROM_DESTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDataReadNonBlocking                                            \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Dest))ROM_DESTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDataProcess                                                    \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src,                                        \
+                   uint32_t *pui32Dest,                                       \
+                   uint32_t ui32Length))ROM_DESTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDataWrite                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_DESTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDataWriteNonBlocking                                           \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_DESTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDMADisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags))ROM_DESTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESDMAEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags))ROM_DESTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_DESTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_DESTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_DESTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESIVSet                                                          \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32IVdata))ROM_DESTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESKeySet                                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Key))ROM_DESTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESLengthSet                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Length))ROM_DESTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_DESReset                                                          \
+        ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the EEPROM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMRead                                                        \
+        ((void (*)(uint32_t *pui32Data,                                       \
+                   uint32_t ui32Address,                                      \
+                   uint32_t ui32Count))ROM_EEPROMTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockCountGet                                               \
+        ((uint32_t (*)(void))ROM_EEPROMTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockHide                                                   \
+        ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockLock                                                   \
+        ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockPasswordSet                                            \
+        ((uint32_t (*)(uint32_t ui32Block,                                    \
+                       uint32_t *pui32Password,                               \
+                       uint32_t ui32Count))ROM_EEPROMTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockProtectGet                                             \
+        ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockProtectSet                                             \
+        ((uint32_t (*)(uint32_t ui32Block,                                    \
+                       uint32_t ui32Protect))ROM_EEPROMTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMBlockUnlock                                                 \
+        ((uint32_t (*)(uint32_t ui32Block,                                    \
+                       uint32_t *pui32Password,                               \
+                       uint32_t ui32Count))ROM_EEPROMTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMIntClear                                                    \
+        ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMIntDisable                                                  \
+        ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMIntEnable                                                   \
+        ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMIntStatus                                                   \
+        ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_EEPROMMassErase                                                   \
+        ((uint32_t (*)(void))ROM_EEPROMTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMProgram                                                     \
+        ((uint32_t (*)(uint32_t *pui32Data,                                   \
+                       uint32_t ui32Address,                                  \
+                       uint32_t ui32Count))ROM_EEPROMTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMProgramNonBlocking                                          \
+        ((uint32_t (*)(uint32_t ui32Data,                                     \
+                       uint32_t ui32Address))ROM_EEPROMTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMSizeGet                                                     \
+        ((uint32_t (*)(void))ROM_EEPROMTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMStatusGet                                                   \
+        ((uint32_t (*)(void))ROM_EEPROMTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EEPROMInit                                                        \
+        ((uint32_t (*)(void))ROM_EEPROMTABLE[17])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the EPI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_EPITABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIModeSet                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Mode))ROM_EPITABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIDividerSet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Divider))ROM_EPITABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigSDRAMSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32Refresh))ROM_EPITABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigGPModeSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32FrameCount,                                   \
+                   uint32_t ui32MaxWait))ROM_EPITABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigHB8Set                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32MaxWait))ROM_EPITABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigHB16Set                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32MaxWait))ROM_EPITABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIAddressMapSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Map))ROM_EPITABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadConfigure                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel,                                      \
+                   uint32_t ui32DataSize,                                     \
+                   uint32_t ui32Address))ROM_EPITABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadStart                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel,                                      \
+                   uint32_t ui32Count))ROM_EPITABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadStop                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel))ROM_EPITABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadCount                                           \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Channel))ROM_EPITABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadAvail                                           \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadGet32                                           \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Count,                                    \
+                       uint32_t *pui32Buf))ROM_EPITABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadGet16                                           \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Count,                                    \
+                       uint16_t *pui16Buf))ROM_EPITABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPINonBlockingReadGet8                                            \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Count,                                    \
+                       uint8_t *pui8Buf))ROM_EPITABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIFIFOConfig                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_EPITABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIWriteFIFOCountGet                                              \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_EPITABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_EPITABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIIntErrorStatus                                                 \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIIntErrorClear                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32ErrFlags))ROM_EPITABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIDividerCSSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t ui32Divider))ROM_EPITABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIDMATxCount                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Count))ROM_EPITABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigHB8CSSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t ui32Config))ROM_EPITABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigHB16CSSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t ui32Config))ROM_EPITABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigHB8TimingSet                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t ui32Config))ROM_EPITABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIConfigHB16TimingSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t ui32Config))ROM_EPITABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIPSRAMConfigRegSet                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t ui32CR))ROM_EPITABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIPSRAMConfigRegRead                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS))ROM_EPITABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIPSRAMConfigRegGetNonBlocking                                   \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint32_t *pui32CR))ROM_EPITABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EPIPSRAMConfigRegGet                                              \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32CS))ROM_EPITABLE[31])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the EMAC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACIntStatus                                                     \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_EMACTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACAddrGet                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Index,                                        \
+                   uint8_t *pui8MACAddr))ROM_EMACTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACAddrSet                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Index,                                        \
+                   const uint8_t *pui8MACAddr))ROM_EMACTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACConfigGet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Config,                                     \
+                   uint32_t *pui32Mode,                                       \
+                   uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACConfigSet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32ModeFlags,                                    \
+                   uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACDMAStateGet                                                   \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACFrameFilterGet                                                \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACFrameFilterSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32FilterOpts))ROM_EMACTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACInit                                                          \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SysClk,                                       \
+                   uint32_t ui32BusConfig,                                    \
+                   uint32_t ui32RxBurst,                                      \
+                   uint32_t ui32TxBurst,                                      \
+                   uint32_t ui32DescSkipSize))ROM_EMACTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACIntClear                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_EMACTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACIntDisable                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_EMACTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACIntEnable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_EMACTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYConfigSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_EMACTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYPowerOff                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8PhyAddr))ROM_EMACTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYPowerOn                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8PhyAddr))ROM_EMACTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYRead                                                       \
+        ((uint16_t (*)(uint32_t ui32Base,                                     \
+                        uint8_t ui8PhyAddr,                                   \
+                       uint8_t ui8RegAddr))ROM_EMACTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYWrite                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8PhyAddr,                                        \
+                   uint8_t ui8RegAddr,                                        \
+                   uint16_t ui16Data))ROM_EMACTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACReset                                                         \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxDisable                                                     \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxDMACurrentBufferGet                                         \
+        ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxDMACurrentDescriptorGet                                     \
+        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxDMADescriptorListGet                                        \
+        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxDMADescriptorListSet                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxDMAPollDemand                                               \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxEnable                                                      \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRxWatchdogTimerSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Timeout))ROM_EMACTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACStatusGet                                                     \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxDisable                                                     \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxDMACurrentBufferGet                                         \
+        ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxDMACurrentDescriptorGet                                     \
+        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxDMADescriptorListGet                                        \
+        ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxDMADescriptorListSet                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxDMAPollDemand                                               \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxEnable                                                      \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTxFlush                                                       \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACAddrFilterGet                                                 \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Index))ROM_EMACTABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACAddrFilterSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Index,                                        \
+                   uint32_t ui32Config))ROM_EMACTABLE[36])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACHashFilterBitCalculate                                        \
+        ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACHashFilterGet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32HashHi,                                     \
+                   uint32_t *pui32HashLo))ROM_EMACTABLE[38])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACHashFilterSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32HashHi,                                       \
+                   uint32_t ui32HashLo))ROM_EMACTABLE[39])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACNumAddrGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYExtendedRead                                               \
+        ((uint16_t (*)(uint32_t ui32Base,                                     \
+                       uint8_t ui8PhyAddr,                                    \
+                       uint16_t ui16RegAddr))ROM_EMACTABLE[41])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPHYExtendedWrite                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8PhyAddr,                                        \
+                   uint16_t ui16RegAddr,                                      \
+                   uint16_t ui16Data))ROM_EMACTABLE[42])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPowerManagementControlGet                                     \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPowerManagementControlSet                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags))ROM_EMACTABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACPowerManagementStatusGet                                      \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRemoteWakeUpFrameFilterGet                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACRemoteWakeUpFrameFilterSet                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampAddendSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Seconds))ROM_EMACTABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampConfigGet                                            \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampConfigSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32SubSecondInc))ROM_EMACTABLE[50])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampDisable                                              \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampEnable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampIntStatus                                            \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampPPSCommand                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Cmd))ROM_EMACTABLE[54])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampPPSCommandModeSet                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_EMACTABLE[55])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampPPSPeriodSet                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Period,                                       \
+                   uint32_t ui32Width))ROM_EMACTABLE[56])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampPPSSimpleModeSet                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32FreqConfig))ROM_EMACTABLE[57])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampSysTimeGet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Seconds,                                    \
+                   uint32_t *pui32SubSeconds))ROM_EMACTABLE[58])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampSysTimeSet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Seconds,                                      \
+                   uint32_t ui32SubSeconds))ROM_EMACTABLE[59])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampSysTimeUpdate                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Seconds,                                      \
+                   uint32_t ui32SubSeconds,                                   \
+                   bool bInc))ROM_EMACTABLE[60])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampTargetIntDisable                                     \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampTargetIntEnable                                      \
+        ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACTimestampTargetSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Seconds,                                      \
+                   uint32_t ui32Nanoseconds))ROM_EMACTABLE[63])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANHashFilterBitCalculate                                    \
+        ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANHashFilterGet                                             \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANHashFilterSet                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Hash))ROM_EMACTABLE[66])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANRxConfigGet                                               \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint16_t *pui16Tag))ROM_EMACTABLE[67])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANRxConfigSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint16_t ui16Tag,                                          \
+                   uint32_t ui32Config))ROM_EMACTABLE[68])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANTxConfigGet                                               \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint16_t *pui16Tag))ROM_EMACTABLE[69])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_EMACVLANTxConfigSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint16_t ui16Tag,                                          \
+                   uint32_t ui32Config))ROM_EMACTABLE[70])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UpdateEMAC                                                        \
+        ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashProgram                                                      \
+        ((int32_t (*)(uint32_t *pui32Data,                                    \
+                      uint32_t ui32Address,                                   \
+                      uint32_t ui32Count))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashErase                                                        \
+        ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashProtectGet                                                   \
+        ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashProtectSet                                                   \
+        ((int32_t (*)(uint32_t ui32Address,                                   \
+                      tFlashProtection eProtect))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashProtectSave                                                  \
+        ((int32_t (*)(void))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashUserGet                                                      \
+        ((int32_t (*)(uint32_t *pui32User0,                                   \
+                      uint32_t *pui32User1))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashUserSet                                                      \
+        ((int32_t (*)(uint32_t ui32User0,                                     \
+                      uint32_t ui32User1))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashUserSave                                                     \
+        ((int32_t (*)(void))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashIntEnable                                                    \
+        ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashIntDisable                                                   \
+        ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashIntStatus                                                    \
+        ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FlashIntClear                                                     \
+        ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the FPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUEnable                                                         \
+        ((void (*)(void))ROM_FPUTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUDisable                                                        \
+        ((void (*)(void))ROM_FPUTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUFlushToZeroModeSet                                             \
+        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUHalfPrecisionModeSet                                           \
+        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPULazyStackingEnable                                             \
+        ((void (*)(void))ROM_FPUTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUNaNModeSet                                                     \
+        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPURoundingModeSet                                                \
+        ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUStackingDisable                                                \
+        ((void (*)(void))ROM_FPUTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_FPUStackingEnable                                                 \
+        ((void (*)(void))ROM_FPUTABLE[8])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinWrite                                                      \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins,                                           \
+                   uint8_t ui8Val))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIODirModeSet                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins,                                           \
+                   uint32_t ui32PinIO))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIODirModeGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Port,                                     \
+                       uint8_t ui8Pin))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOIntTypeSet                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins,                                           \
+                   uint32_t ui32IntType))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOIntTypeGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Port,                                     \
+                       uint8_t ui8Pin))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_GPIOPadConfigSet                                                  \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins,                                           \
+                   uint32_t ui32Strength,                                     \
+                   uint32_t ui32PadType))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPadConfigGet                                                  \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pin,                                            \
+                   uint32_t *pui32Strength,                                   \
+                   uint32_t *pui32PadType))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinRead                                                       \
+        ((int32_t (*)(uint32_t ui32Port,                                      \
+                      uint8_t ui8Pins))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_GPIOPinTypeCAN                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeComparator                                             \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeGPIOInput                                              \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeGPIOOutput                                             \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeI2C                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypePWM                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeQEI                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeSSI                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeTimer                                                  \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeUART                                                   \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeGPIOOutputOD                                           \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeADC                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeUSBDigital                                             \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinConfigure                                                  \
+        ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeUSBAnalog                                              \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIODMATriggerEnable                                              \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIODMATriggerDisable                                             \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOADCTriggerEnable                                              \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOADCTriggerDisable                                             \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeI2CSCL                                                 \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[39])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeOneWire                                                \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeWakeHigh                                               \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinTypeWakeLow                                                \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint8_t ui8Pins))ROM_GPIOTABLE[49])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOIntClear                                                      \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint32_t ui32IntFlags))ROM_GPIOTABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOIntDisable                                                    \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint32_t ui32IntFlags))ROM_GPIOTABLE[52])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOIntEnable                                                     \
+        ((void (*)(uint32_t ui32Port,                                         \
+                   uint32_t ui32IntFlags))ROM_GPIOTABLE[53])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOIntStatus                                                     \
+        ((uint32_t (*)(uint32_t ui32Port,                                     \
+                       bool bMasked))ROM_GPIOTABLE[54])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_GPIOPinWakeStatus                                                 \
+        ((uint32_t (*)(uint32_t ui32Port))ROM_GPIOTABLE[55])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Hibernate API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateIntClear                                                 \
+        ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateEnableExpClk                                             \
+        ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateDisable                                                  \
+        ((void (*)(void))ROM_HIBERNATETABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCEnable                                                \
+        ((void (*)(void))ROM_HIBERNATETABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCDisable                                               \
+        ((void (*)(void))ROM_HIBERNATETABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateWakeSet                                                  \
+        ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateWakeGet                                                  \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateLowBatSet                                                \
+        ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateLowBatGet                                                \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCSet                                                   \
+        ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCGet                                                   \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCTrimSet                                               \
+        ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCTrimGet                                               \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateDataSet                                                  \
+        ((void (*)(uint32_t *pui32Data,                                       \
+                   uint32_t ui32Count))ROM_HIBERNATETABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateDataGet                                                  \
+        ((void (*)(uint32_t *pui32Data,                                       \
+                   uint32_t ui32Count))ROM_HIBERNATETABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRequest                                                  \
+        ((void (*)(void))ROM_HIBERNATETABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateIntEnable                                                \
+        ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateIntDisable                                               \
+        ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateIntStatus                                                \
+        ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateIsActive                                                 \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCSSGet                                                 \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateClockConfig                                              \
+        ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateBatCheckStart                                            \
+        ((void (*)(void))ROM_HIBERNATETABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateBatCheckDone                                             \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateGPIORetentionEnable                                      \
+        ((void (*)(void))ROM_HIBERNATETABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateGPIORetentionDisable                                     \
+        ((void (*)(void))ROM_HIBERNATETABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateGPIORetentionGet                                         \
+        ((bool (*)(void))ROM_HIBERNATETABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateCounterMode                                              \
+        ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateCalendarSet                                              \
+        ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateCalendarGet                                              \
+        ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateCalendarMatchSet                                         \
+        ((void (*)(uint32_t ui32Index,                                        \
+                   struct tm *psTime))ROM_HIBERNATETABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateCalendarMatchGet                                         \
+        ((void (*)(uint32_t ui32Index,                                        \
+                   struct tm *psTime))ROM_HIBERNATETABLE[38])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperDisable                                            \
+        ((void (*)(void))ROM_HIBERNATETABLE[39])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperEnable                                             \
+        ((void (*)(void))ROM_HIBERNATETABLE[40])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperEventsClear                                        \
+        ((void (*)(void))ROM_HIBERNATETABLE[41])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperEventsConfig                                       \
+        ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperEventsGet                                          \
+        ((bool (*)(uint32_t ui32Index,                                        \
+                   uint32_t *pui32RTC,                                        \
+                   uint32_t *pui32Event))ROM_HIBERNATETABLE[43])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperExtOscValid                                        \
+        ((bool (*)(void))ROM_HIBERNATETABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperExtOscRecover                                      \
+        ((void (*)(void))ROM_HIBERNATETABLE[45])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperIODisable                                          \
+        ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperIOEnable                                           \
+        ((void (*)(uint32_t ui32Input,                                        \
+                   uint32_t ui32Config))ROM_HIBERNATETABLE[47])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateTamperStatusGet                                          \
+        ((uint32_t (*)(void))ROM_HIBERNATETABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCMatchGet                                              \
+        ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCMatchSet                                              \
+        ((void (*)(uint32_t ui32Match,                                        \
+                   uint32_t ui32Value))ROM_HIBERNATETABLE[50])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCSSMatchGet                                            \
+        ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_HibernateRTCSSMatchSet                                            \
+        ((void (*)(uint32_t ui32Match,                                        \
+                   uint32_t ui32Value))ROM_HIBERNATETABLE[52])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterDataPut                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Data))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterInitExpClk                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32I2CClk,                                       \
+                   bool bFast))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveInit                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8SlaveAddr))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterEnable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveEnable                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterDisable                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveDisable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntEnable                                                \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntEnable                                                 \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntDisable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntDisable                                                \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntStatus                                                \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   bool bMasked))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntStatus                                                 \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   bool bMasked))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntClear                                                 \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntClear                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterSlaveAddrSet                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8SlaveAddr,                                      \
+                   bool bReceive))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterBusy                                                     \
+        ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterBusBusy                                                  \
+        ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterControl                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Cmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterErr                                                      \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterDataGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveStatus                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveDataPut                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Data))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveDataGet                                                   \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UpdateI2C                                                         \
+        ((void (*)(void))ROM_I2CTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntEnableEx                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_I2CTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntDisableEx                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_I2CTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntStatusEx                                               \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_I2CTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveIntClearEx                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_I2CTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntEnableEx                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_I2CTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntDisableEx                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_I2CTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntStatusEx                                              \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_I2CTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterIntClearEx                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_I2CTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterTimeoutSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Value))ROM_I2CTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveACKOverride                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bEnable))ROM_I2CTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveACKValueSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bACK))ROM_I2CTABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveAddressSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8AddrNum,                                        \
+                   uint8_t ui8SlaveAddr))ROM_I2CTABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterLineStateGet                                             \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CTxFIFOConfigSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_I2CTABLE[39])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CTxFIFOFlush                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CRxFIFOConfigSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_I2CTABLE[41])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CRxFIFOFlush                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CFIFOStatus                                                     \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CFIFODataPut                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Data))ROM_I2CTABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CFIFODataPutNonBlocking                                         \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint8_t ui8Data))ROM_I2CTABLE[45])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CFIFODataGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CFIFODataGetNonBlocking                                         \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint8_t *pui8Data))ROM_I2CTABLE[47])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterBurstLengthSet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Length))ROM_I2CTABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterBurstCountGet                                            \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveFIFODisable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CSlaveFIFOEnable                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_I2CTABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_I2CMasterGlitchFilterConfigSet                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_I2CTABLE[54])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntEnable                                                         \
+        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntMasterEnable                                                   \
+        ((bool (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntMasterDisable                                                  \
+        ((bool (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntDisable                                                        \
+        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPriorityGroupingSet                                            \
+        ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPriorityGroupingGet                                            \
+        ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPrioritySet                                                    \
+        ((void (*)(uint32_t ui32Interrupt,                                    \
+                   uint8_t ui8Priority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPriorityGet                                                    \
+        ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPendSet                                                        \
+        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPendClear                                                      \
+        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPriorityMaskSet                                                \
+        ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntPriorityMaskGet                                                \
+        ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntIsEnabled                                                      \
+        ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_IntTrigger                                                        \
+        ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the LCD API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_LCDTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDClockReset                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Clocks))ROM_LCDTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDDMAConfigSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_LCDTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDCommandWrite                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint16_t ui16Cmd))ROM_LCDTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDConfigSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_LCDTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDDataRead                                                    \
+        ((uint16_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32CS))ROM_LCDTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDDataWrite                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint16_t ui16Data))ROM_LCDTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDDMADisable                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDDMAWrite                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   const uint32_t *pui32Data,                                 \
+                   uint32_t ui32Count))ROM_LCDTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDIndexedRead                                                 \
+        ((uint16_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32CS,                                       \
+                       uint16_t ui16Addr))ROM_LCDTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDIndexedWrite                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   uint16_t ui16Addr,                                         \
+                   uint16_t ui16Data))ROM_LCDTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDStatusRead                                                  \
+        ((uint16_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32CS))ROM_LCDTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIDDTimingSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32CS,                                           \
+                   const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_LCDTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_LCDTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_LCDTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDModeSet                                                        \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint8_t ui8Mode,                                       \
+                       uint32_t ui32PixClk,                                   \
+                       uint32_t ui32SysClk))ROM_LCDTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterACBiasIntCountSet                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Count))ROM_LCDTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterConfigSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterDisable                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterEnable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterFrameBufferSet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Buffer,                                         \
+                   uint32_t *pui32Addr,                                       \
+                   uint32_t ui32NumBytes))ROM_LCDTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterPaletteSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Type,                                         \
+                   uint32_t *pui32PalAddr,                                    \
+                   const uint32_t *pui32SrcColors,                            \
+                   uint32_t ui32Start,                                        \
+                   uint32_t ui32Count))ROM_LCDTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterSubPanelConfigSet                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags,                                        \
+                   uint32_t ui32BottomLines,                                  \
+                   uint32_t ui32DefaultPixel))ROM_LCDTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterSubPanelDisable                                          \
+        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterSubPanelEnable                                           \
+        ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterTimingSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_LCDRasterEnabled                                                  \
+        ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the MPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPUEnable                                                         \
+        ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPUDisable                                                        \
+        ((void (*)(void))ROM_MPUTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPURegionCountGet                                                 \
+        ((uint32_t (*)(void))ROM_MPUTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPURegionEnable                                                   \
+        ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPURegionDisable                                                  \
+        ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPURegionSet                                                      \
+        ((void (*)(uint32_t ui32Region,                                       \
+                   uint32_t ui32Addr,                                         \
+                   uint32_t ui32Flags))ROM_MPUTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_MPURegionGet                                                      \
+        ((void (*)(uint32_t ui32Region,                                       \
+                   uint32_t *pui32Addr,                                       \
+                   uint32_t *pui32Flags))ROM_MPUTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the OneWire API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireIntStatus                                                  \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_ONEWIRETABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireBusReset                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireBusStatus                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireDataGet                                                    \
+        ((void (*)(uint32_t u3i2Base,                                         \
+                   uint32_t *pui32Data))ROM_ONEWIRETABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireDataGetNonBlocking                                         \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Data))ROM_ONEWIRETABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireInit                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireIntClear                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireIntDisable                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireIntEnable                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireTransaction                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32OpFlags,                                      \
+                   uint32_t ui32Data,                                         \
+                   uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireDMADisable                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_OneWireDMAEnable                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PWM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMPulseWidthSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PWMOut,                                       \
+                   uint32_t ui32Width))ROM_PWMTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenConfigure                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32Config))ROM_PWMTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenPeriodSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32Period))ROM_PWMTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenPeriodGet                                                   \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Gen))ROM_PWMTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen))ROM_PWMTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen))ROM_PWMTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMPulseWidthGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32PWMOut))ROM_PWMTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMDeadBandEnable                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint16_t ui16Rise,                                         \
+                   uint16_t ui16Fall))ROM_PWMTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMDeadBandDisable                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen))ROM_PWMTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMSyncUpdate                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32GenBits))ROM_PWMTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMSyncTimeBase                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32GenBits))ROM_PWMTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMOutputState                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PWMOutBits,                                   \
+                   bool bEnable))ROM_PWMTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMOutputInvert                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PWMOutBits,                                   \
+                   bool bInvert))ROM_PWMTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMOutputFault                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PWMOutBits,                                   \
+                   bool bFaultSuppress))ROM_PWMTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenIntTrigEnable                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32IntTrig))ROM_PWMTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenIntTrigDisable                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32IntTrig))ROM_PWMTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenIntStatus                                                   \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Gen,                                      \
+                       bool bMasked))ROM_PWMTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenIntClear                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32Ints))ROM_PWMTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32GenFault))ROM_PWMTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32GenFault))ROM_PWMTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMFaultIntClear                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_PWMTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMOutputFaultLevel                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PWMOutBits,                                   \
+                   bool bDriveHigh))ROM_PWMTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMFaultIntClearExt                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32FaultInts))ROM_PWMTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenFaultConfigure                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32MinFaultPeriod,                               \
+                   uint32_t ui32FaultSenses))ROM_PWMTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenFaultTriggerSet                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32Group,                                        \
+                   uint32_t ui32FaultTriggers))ROM_PWMTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenFaultTriggerGet                                             \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Gen,                                      \
+                       uint32_t ui32Group))ROM_PWMTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenFaultStatus                                                 \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Gen,                                      \
+                       uint32_t ui32Group))ROM_PWMTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMGenFaultClear                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Gen,                                          \
+                   uint32_t ui32Group,                                        \
+                   uint32_t ui32FaultTriggers))ROM_PWMTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMClockSet                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_PWMTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMClockGet                                                       \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_PWMOutputUpdateMode                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PWMOutBits,                                   \
+                   uint32_t ui32Mode))ROM_PWMTABLE[31])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the QEI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIPositionGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIEnable                                                         \
+        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIDisable                                                        \
+        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIConfigure                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config,                                       \
+                   uint32_t ui32MaxPosition))ROM_QEITABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIPositionSet                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Position))ROM_QEITABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIDirectionGet                                                   \
+        ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIErrorGet                                                       \
+        ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIVelocityEnable                                                 \
+        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIVelocityDisable                                                \
+        ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIVelocityConfigure                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32PreDiv,                                       \
+                   uint32_t ui32Period))ROM_QEITABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIVelocityGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_QEITABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_QEITABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_QEITABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_QEIIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_QEITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SHAMD5 API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5IntStatus                                                   \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_SHAMD5TABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5ConfigSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Mode))ROM_SHAMD5TABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5DataProcess                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32DataSrc,                                    \
+                   uint32_t ui32DataLength,                                   \
+                   uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5DataWrite                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_SHAMD5TABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5DataWriteNonBlocking                                        \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_SHAMD5TABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5DMADisable                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5DMAEnable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5HashLengthSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Length))ROM_SHAMD5TABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5HMACKeySet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_SHAMD5TABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5HMACPPKeyGenerate                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Key,                                        \
+                   uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5HMACPPKeySet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Src))ROM_SHAMD5TABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5HMACProcess                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32DataSrc,                                    \
+                   uint32_t ui32DataLength,                                   \
+                   uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5IntClear                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5IntDisable                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5IntEnable                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5Reset                                                       \
+        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SHAMD5ResultRead                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Dest))ROM_SHAMD5TABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SMBus API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterIntProcess                                             \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusARPDisable                                                   \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusARPEnable                                                    \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusARPUDIDPacketDecode                                          \
+        ((void (*)(tSMBusUDID *pUDID,                                         \
+                   uint8_t *pui8Address,                                      \
+                   uint8_t *pui8Data))ROM_SMBUSTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusARPUDIDPacketEncode                                          \
+        ((void (*)(tSMBusUDID *pUDID,                                         \
+                   uint8_t ui8Address,                                        \
+                   uint8_t *pui8Data))ROM_SMBUSTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPAssignAddress                                       \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPGetUDIDDir                                          \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPGetUDIDGen                                          \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPNotifyMaster                                        \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPPrepareToARP                                        \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPResetDeviceDir                                      \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterARPResetDeviceGen                                      \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterBlockProcessCall                                       \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Command,                                \
+                           uint8_t *pui8TxData,                               \
+                           uint8_t ui8TxSize,                                 \
+                           uint8_t *pui8RxData))ROM_SMBUSTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterBlockRead                                              \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Command,                                \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterBlockWrite                                             \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Command,                                \
+                           uint8_t *pui8Data,                                 \
+                           uint8_t ui8Size))ROM_SMBUSTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterByteReceive                                            \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterByteSend                                               \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Data))ROM_SMBUSTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterByteWordRead                                           \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Command,                                \
+                           uint8_t *pui8Data,                                 \
+                           uint8_t ui8Size))ROM_SMBUSTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterByteWordWrite                                          \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Command,                                \
+                           uint8_t *pui8Data,                                 \
+                           uint8_t ui8Size))ROM_SMBUSTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterHostNotify                                             \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8OwnSlaveAddress,                        \
+                           uint8_t *pui8Data))ROM_SMBUSTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterI2CRead                                                \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t *pui8Data,                                 \
+                           uint8_t ui8Size))ROM_SMBUSTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterI2CWrite                                               \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t *pui8Data,                                 \
+                           uint8_t ui8Size))ROM_SMBUSTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterI2CWriteRead                                           \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t *pui8TxData,                               \
+                           uint8_t ui8TxSize,                                 \
+                           uint8_t *pui8RxData,                               \
+                           uint8_t ui8RxSize))ROM_SMBUSTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterInit                                                   \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   uint32_t ui32I2CBase,                                      \
+                   uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterIntEnable                                              \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterProcessCall                                            \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           uint8_t ui8Command,                                \
+                           uint8_t *pui8TxData,                               \
+                           uint8_t *pui8RxData))ROM_SMBUSTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusMasterQuickCommand                                           \
+        ((tSMBusStatus (*)(tSMBus *psSMBus,                                   \
+                           uint8_t ui8TargetAddress,                          \
+                           bool bData))ROM_SMBUSTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusPECDisable                                                   \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusPECEnable                                                    \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusRxPacketSizeGet                                              \
+        ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveACKSend                                                 \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   bool bACK))ROM_SMBUSTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveAddressSet                                              \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   uint8_t ui8AddressNum,                                     \
+                   uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveARPFlagARGet                                            \
+        ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveARPFlagARSet                                            \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   bool bValue))ROM_SMBUSTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveARPFlagAVGet                                            \
+        ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveARPFlagAVSet                                            \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   bool bValue))ROM_SMBUSTABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveBlockTransferDisable                                    \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveBlockTransferEnable                                     \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveCommandGet                                              \
+        ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveI2CDisable                                              \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveI2CEnable                                               \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveInit                                                    \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   uint32_t ui32I2CBase))ROM_SMBUSTABLE[41])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveIntAddressGet                                           \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveIntEnable                                               \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveIntProcess                                              \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveManualACKDisable                                        \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveManualACKEnable                                         \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveManualACKStatusGet                                      \
+        ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveProcessCallDisable                                      \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveProcessCallEnable                                       \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveRxBufferSet                                             \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   uint8_t *pui8Data,                                         \
+                   uint8_t ui8Size))ROM_SMBUSTABLE[50])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveTransferInit                                            \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveTxBufferSet                                             \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   uint8_t *pui8Data,                                         \
+                   uint8_t ui8Size))ROM_SMBUSTABLE[52])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveUDIDSet                                                 \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   tSMBusUDID *pUDID))ROM_SMBUSTABLE[53])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusStatusGet                                                    \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusSlaveDataSend                                                \
+        ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusFIFOEnable                                                   \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusFIFODisable                                                  \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusDMAEnable                                                    \
+        ((void (*)(tSMBus *psSMBus,                                           \
+                   uint8_t ui8TxChannel,                                      \
+                   uint8_t ui8RxChannel))ROM_SMBUSTABLE[58])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SMBusDMADisable                                                   \
+        ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SPIFlash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashIntHandler                                                \
+        ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashInit                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Clock,                                        \
+                   uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashWriteStatus                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Status))ROM_SPIFLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashPageProgram                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   const uint8_t *pui8Data,                                   \
+                   uint32_t ui32Count))ROM_SPIFLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashPageProgramNonBlocking                                    \
+        ((void (*)(tSPIFlashState *pState,                                    \
+                   uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   const uint8_t *pui8Data,                                   \
+                   uint32_t ui32Count,                                        \
+                   bool bUseDMA,                                              \
+                   uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashRead                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count))ROM_SPIFLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashReadNonBlocking                                           \
+        ((void (*)(tSPIFlashState *pState,                                    \
+                   uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count,                                        \
+                   bool bUseDMA,                                              \
+                   uint32_t ui32TxChannel,                                    \
+                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashWriteDisable                                              \
+        ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashReadStatus                                                \
+        ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashWriteEnable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashFastRead                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count))ROM_SPIFLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashFastReadNonBlocking                                       \
+        ((void (*)(tSPIFlashState *pState,                                    \
+                   uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count,                                        \
+                   bool bUseDMA,                                              \
+                   uint32_t ui32TxChannel,                                    \
+                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashSectorErase                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr))ROM_SPIFLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashDualRead                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count))ROM_SPIFLASHTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashDualReadNonBlocking                                       \
+        ((void (*)(tSPIFlashState *pState,                                    \
+                   uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count,                                        \
+                   bool bUseDMA,                                              \
+                   uint32_t ui32TxChannel,                                    \
+                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashBlockErase32                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr))ROM_SPIFLASHTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashQuadRead                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count))ROM_SPIFLASHTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashQuadReadNonBlocking                                       \
+        ((void (*)(tSPIFlashState *pState,                                    \
+                   uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr,                                         \
+                   uint8_t *pui8Data,                                         \
+                   uint32_t ui32Count,                                        \
+                   bool bUseDMA,                                              \
+                   uint32_t ui32TxChannel,                                    \
+                   uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashReadID                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t *pui8ManufacturerID,                               \
+                   uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashChipErase                                                 \
+        ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SPIFlashBlockErase64                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Addr))ROM_SPIFLASHTABLE[20])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SSI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDataPut                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Data))ROM_SSITABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIConfigSetExpClk                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32SSIClk,                                       \
+                   uint32_t ui32Protocol,                                     \
+                   uint32_t ui32Mode,                                         \
+                   uint32_t ui32BitRate,                                      \
+                   uint32_t ui32DataWidth))ROM_SSITABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIEnable                                                         \
+        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDisable                                                        \
+        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIIntEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_SSITABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIIntDisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_SSITABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIIntStatus                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_SSITABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIIntClear                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_SSITABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDataPutNonBlocking                                             \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32Data))ROM_SSITABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDataGet                                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32Data))ROM_SSITABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDataGetNonBlocking                                             \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t *pui32Data))ROM_SSITABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UpdateSSI                                                         \
+        ((void (*)(void))ROM_SSITABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDMAEnable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAFlags))ROM_SSITABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIDMADisable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAFlags))ROM_SSITABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIBusy                                                           \
+        ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIClockSourceGet                                                 \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIClockSourceSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Source))ROM_SSITABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIAdvModeSet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Mode))ROM_SSITABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIAdvDataPutFrameEnd                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Data))ROM_SSITABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIAdvDataPutFrameEndNonBlocking                                  \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32Data))ROM_SSITABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIAdvFrameHoldEnable                                             \
+        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SSIAdvFrameHoldDisable                                            \
+        ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlSleep                                                       \
+        ((void (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlSRAMSizeGet                                                 \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlFlashSizeGet                                                \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralPresent                                           \
+        ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralReset                                             \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralEnable                                            \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralDisable                                           \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralSleepEnable                                       \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralSleepDisable                                      \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralDeepSleepEnable                                   \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralDeepSleepDisable                                  \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralClockGating                                       \
+        ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlIntEnable                                                   \
+        ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlIntDisable                                                  \
+        ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlIntClear                                                    \
+        ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlIntStatus                                                   \
+        ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlReset                                                       \
+        ((void (*)(void))ROM_SYSCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlDeepSleep                                                   \
+        ((void (*)(void))ROM_SYSCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlResetCauseGet                                               \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlResetCauseClear                                             \
+        ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlClockSet                                                    \
+        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlClockGet                                                    \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlPWMClockSet                                                 \
+        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlPWMClockGet                                                 \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlUSBPLLEnable                                                \
+        ((void (*)(void))ROM_SYSCTLTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlUSBPLLDisable                                               \
+        ((void (*)(void))ROM_SYSCTLTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlDelay                                                       \
+        ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralReady                                             \
+        ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralPowerOn                                           \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPeripheralPowerOff                                          \
+        ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlMOSCConfigSet                                               \
+        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlPIOSCCalibrate                                              \
+        ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_SysCtlDeepSleepClockSet                                           \
+        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlDeepSleepClockConfigSet                                     \
+        ((void (*)(uint32_t ui32Div,                                          \
+                   uint32_t ui32Config))ROM_SYSCTLTABLE[47])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlClockFreqSet                                                \
+        ((uint32_t (*)(uint32_t ui32Config,                                   \
+                       uint32_t ui32SysClock))ROM_SYSCTLTABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlResetBehaviorSet                                            \
+        ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlResetBehaviorGet                                            \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[52])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlFlashSectorSizeGet                                          \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[54])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlVoltageEventConfig                                          \
+        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlVoltageEventStatus                                          \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[56])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlVoltageEventClear                                           \
+        ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlNMIStatus                                                   \
+        ((uint32_t (*)(void))ROM_SYSCTLTABLE[58])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlNMIClear                                                    \
+        ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlClockOutConfig                                              \
+        ((void (*)(uint32_t ui32Config,                                       \
+                   uint32_t ui32Div))ROM_SYSCTLTABLE[60])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysCtlAltClkConfig                                                \
+        ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysExc API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysExcIntStatus                                                   \
+        ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysExcIntClear                                                    \
+        ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysExcIntDisable                                                  \
+        ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysExcIntEnable                                                   \
+        ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickValueGet                                                   \
+        ((uint32_t (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickEnable                                                     \
+        ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickDisable                                                    \
+        ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickIntEnable                                                  \
+        ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickIntDisable                                                 \
+        ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickPeriodSet                                                  \
+        ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_SysTickPeriodGet                                                  \
+        ((uint32_t (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerIntClear                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerEnable                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerDisable                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerConfigure                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerControlLevel                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   bool bInvert))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerControlTrigger                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   bool bEnable))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerControlEvent                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   uint32_t ui32Event))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerControlStall                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   bool bStall))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerRTCEnable                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerRTCDisable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerPrescaleSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   uint32_t ui32Value))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerPrescaleGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Timer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerPrescaleMatchSet                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   uint32_t ui32Value))ROM_TIMERTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerPrescaleMatchGet                                             \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Timer))ROM_TIMERTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerLoadSet                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   uint32_t ui32Value))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerLoadGet                                                      \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Timer))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerValueGet                                                     \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Timer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerMatchSet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   uint32_t ui32Value))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerMatchGet                                                     \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Timer))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerIntEnable                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerIntDisable                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerIntStatus                                                    \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_TIMERTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerControlWaitOnTrigger                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timer,                                        \
+                   bool bWait))ROM_TIMERTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_TimerLoadSet64                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint64_t ui64Value))ROM_TIMERTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_TimerLoadGet64                                                    \
+        ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_TimerValueGet64                                                   \
+        ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_TimerMatchSet64                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint64_t ui64Value))ROM_TIMERTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1)
+#define ROM_TimerMatchGet64                                                   \
+        ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerClockSourceGet                                               \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerClockSourceSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Source))ROM_TIMERTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerADCEventGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerADCEventSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32ADCEvent))ROM_TIMERTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerDMAEventGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerDMAEventSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAEvent))ROM_TIMERTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_TimerSynchronize                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Timers))ROM_TIMERTABLE[34])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTCharPut                                                       \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   unsigned char ucData))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTParityModeSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Parity))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTParityModeGet                                                 \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTFIFOLevelSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32TxLevel,                                      \
+                   uint32_t ui32RxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTFIFOLevelGet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t *pui32TxLevel,                                    \
+                   uint32_t *pui32RxLevel))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTConfigSetExpClk                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32UARTClk,                                      \
+                   uint32_t ui32Baud,                                         \
+                   uint32_t ui32Config))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTConfigGetExpClk                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32UARTClk,                                      \
+                   uint32_t *pui32Baud,                                       \
+                   uint32_t *pui32Config))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTEnable                                                        \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTDisable                                                       \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTEnableSIR                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bLowPower))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTDisableSIR                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTCharsAvail                                                    \
+        ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTSpaceAvail                                                    \
+        ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTCharGetNonBlocking                                            \
+        ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTCharGet                                                       \
+        ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTCharPutNonBlocking                                            \
+        ((bool (*)(uint32_t ui32Base,                                         \
+                   unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTBreakCtl                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTIntEnable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTIntDisable                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTIntStatus                                                     \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTIntClear                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UpdateUART                                                        \
+        ((void (*)(void))ROM_UARTTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTDMAEnable                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAFlags))ROM_UARTTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTDMADisable                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32DMAFlags))ROM_UARTTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTFIFOEnable                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTFIFODisable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTBusy                                                          \
+        ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTTxIntModeSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Mode))ROM_UARTTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTTxIntModeGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTRxErrorGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTRxErrorClear                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTClockSourceSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Source))ROM_UARTTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTClockSourceGet                                                \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UART9BitEnable                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UART9BitDisable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UART9BitAddrSet                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Addr,                                           \
+                   uint8_t ui8Mask))ROM_UARTTABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UART9BitAddrSend                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Addr))ROM_UARTTABLE[36])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTSmartCardDisable                                              \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTSmartCardEnable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTModemControlClear                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Control))ROM_UARTTABLE[39])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTModemControlGet                                               \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTModemControlSet                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Control))ROM_UARTTABLE[41])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTModemStatusGet                                                \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTFlowControlGet                                                \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UARTFlowControlSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Mode))ROM_UARTTABLE[44])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelTransferSet                                            \
+        ((void (*)(uint32_t ui32ChannelStructIndex,                           \
+                   uint32_t ui32Mode,                                         \
+                   void *pvSrcAddr,                                           \
+                   void *pvDstAddr,                                           \
+                   uint32_t ui32TransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAEnable                                                        \
+        ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMADisable                                                       \
+        ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAErrorStatusGet                                                \
+        ((uint32_t (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAErrorStatusClear                                              \
+        ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelEnable                                                 \
+        ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelDisable                                                \
+        ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelIsEnabled                                              \
+        ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAControlBaseSet                                                \
+        ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAControlBaseGet                                                \
+        ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelRequest                                                \
+        ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelAttributeEnable                                        \
+        ((void (*)(uint32_t ui32ChannelNum,                                   \
+                   uint32_t ui32Attr))ROM_UDMATABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelAttributeDisable                                       \
+        ((void (*)(uint32_t ui32ChannelNum,                                   \
+                   uint32_t ui32Attr))ROM_UDMATABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelAttributeGet                                           \
+        ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelControlSet                                             \
+        ((void (*)(uint32_t ui32ChannelStructIndex,                           \
+                   uint32_t ui32Control))ROM_UDMATABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelSizeGet                                                \
+        ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelModeGet                                                \
+        ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelSelectSecondary                                        \
+        ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelSelectDefault                                          \
+        ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAIntStatus                                                     \
+        ((uint32_t (*)(void))ROM_UDMATABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAIntClear                                                      \
+        ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAControlAlternateBaseGet                                       \
+        ((void * (*)(void))ROM_UDMATABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelScatterGatherSet                                       \
+        ((void (*)(uint32_t ui32ChannelNum,                                   \
+                   uint32_t ui32TaskCount,                                    \
+                   void *pvTaskList,                                          \
+                   uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_uDMAChannelAssign                                                 \
+        ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the USB API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevAddrGet                                                     \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevAddrSet                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Address))ROM_USBTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevConnect                                                     \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevDisconnect                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevEndpointConfigSet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32MaxPacketSize,                                \
+                   uint32_t ui32Flags))ROM_USBTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevEndpointDataAck                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   bool bIsLastPacket))ROM_USBTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevEndpointStall                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevEndpointStallClear                                          \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevEndpointStatusClear                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDataGet                                                \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32Endpoint,                                  \
+                      uint8_t *pui8Data,                                      \
+                      uint32_t *pui32Size))ROM_USBTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDataPut                                                \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32Endpoint,                                  \
+                      uint8_t *pui8Data,                                      \
+                      uint32_t ui32Size))ROM_USBTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDataSend                                               \
+        ((int32_t (*)(uint32_t ui32Base,                                      \
+                      uint32_t ui32Endpoint,                                  \
+                      uint32_t ui32TransType))ROM_USBTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDataToggleClear                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointStatus                                                 \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Endpoint))ROM_USBTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBFIFOAddrGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Endpoint))ROM_USBTABLE[15])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBFIFOConfigGet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t *pui32FIFOAddress,                                \
+                   uint32_t *pui32FIFOSize,                                   \
+                   uint32_t ui32Flags))ROM_USBTABLE[16])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBFIFOConfigSet                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32FIFOAddress,                                  \
+                   uint32_t ui32FIFOSize,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[17])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBFIFOFlush                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[18])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBFrameNumberGet                                                 \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostAddrGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Endpoint,                                 \
+                       uint32_t ui32Flags))ROM_USBTABLE[20])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostAddrSet                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Addr,                                         \
+                   uint32_t ui32Flags))ROM_USBTABLE[21])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostEndpointConfig                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32MaxPacketSize,                                \
+                   uint32_t ui32NAKPollInterval,                              \
+                   uint32_t ui32TargetEndpoint,                               \
+                   uint32_t ui32Flags))ROM_USBTABLE[22])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostEndpointDataAck                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint))ROM_USBTABLE[23])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostEndpointDataToggle                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   bool bDataToggle,                                          \
+                   uint32_t ui32Flags))ROM_USBTABLE[24])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostEndpointStatusClear                                        \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[25])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostHubAddrGet                                                 \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Endpoint,                                 \
+                       uint32_t ui32Flags))ROM_USBTABLE[26])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostHubAddrSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Addr,                                         \
+                   uint32_t ui32Flags))ROM_USBTABLE[27])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostPwrDisable                                                 \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostPwrEnable                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostPwrConfig                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Flags))ROM_USBTABLE[30])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostPwrFaultDisable                                            \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostPwrFaultEnable                                             \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostRequestIN                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint))ROM_USBTABLE[33])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostRequestStatus                                              \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostReset                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bStart))ROM_USBTABLE[35])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostResume                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bStart))ROM_USBTABLE[36])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostSpeedGet                                                   \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostSuspend                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevEndpointConfigGet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t *pui32MaxPacketSize,                              \
+                   uint32_t *pui32Flags))ROM_USBTABLE[41])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDMAEnable                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[42])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDMADisable                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[43])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDataAvail                                              \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Endpoint))ROM_USBTABLE[44])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBOTGHostRequest                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bHNP))ROM_USBTABLE[45])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBModeGet                                                        \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDMAChannel                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Channel))ROM_USBTABLE[47])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBIntDisableControl                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_USBTABLE[48])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBIntEnableControl                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_USBTABLE[49])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBIntStatusControl                                               \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBIntDisableEndpoint                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_USBTABLE[51])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBIntEnableEndpoint                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32IntFlags))ROM_USBTABLE[52])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBIntStatusEndpoint                                              \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostMode                                                       \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevMode                                                        \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBPHYPowerOff                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBPHYPowerOn                                                     \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57])
+#endif
+#if defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_UpdateUSB                                                         \
+        ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBOTGMode                                                        \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostRequestINClear                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint))ROM_USBTABLE[60])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBNumEndpointsGet                                                \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBClockDisable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBClockEnable                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Div,                                          \
+                   uint32_t ui32Flags))ROM_USBTABLE[63])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBControllerVersion                                              \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevLPMConfig                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_USBTABLE[65])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevLPMDisable                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66])
+#endif
+#if defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevLPMEnable                                                   \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevLPMRemoteWake                                               \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDevSpeedGet                                                    \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelAddressGet                                           \
+        ((void * (*)(uint32_t ui32Base,                                       \
+                     uint32_t ui32Channel))ROM_USBTABLE[70])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelAddressSet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel,                                      \
+                   void *pvAddress))ROM_USBTABLE[71])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelConfigSet                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel,                                      \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Config))ROM_USBTABLE[72])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelDisable                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel))ROM_USBTABLE[73])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelEnable                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel))ROM_USBTABLE[74])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelIntDisable                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel))ROM_USBTABLE[75])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelIntEnable                                            \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel))ROM_USBTABLE[76])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelCountGet                                             \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Channel))ROM_USBTABLE[77])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelCountSet                                             \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Count,                                        \
+                   uint32_t ui32Channel))ROM_USBTABLE[78])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelIntStatus                                            \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelStatus                                               \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       uint32_t ui32Channel))ROM_USBTABLE[80])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMAChannelStatusClear                                          \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Channel,                                      \
+                   uint32_t ui32Status))ROM_USBTABLE[81])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHighSpeed                                                      \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bEnable))ROM_USBTABLE[82])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostEndpointPing                                               \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   bool bEnable))ROM_USBTABLE[83])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostEndpointSpeed                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Flags))ROM_USBTABLE[84])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostLPMConfig                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32ResumeTime,                                   \
+                   uint32_t ui32Config))ROM_USBTABLE[85])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostLPMResume                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBHostLPMSend                                                    \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Address,                                      \
+                   uint32_t uiEndpoint))ROM_USBTABLE[87])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBLPMIntDisable                                                  \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Ints))ROM_USBTABLE[88])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBLPMIntEnable                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Ints))ROM_USBTABLE[89])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBLPMIntStatus                                                   \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBLPMLinkStateGet                                                \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointPacketCountSet                                         \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Count))ROM_USBTABLE[92])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBULPIConfig                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Config))ROM_USBTABLE[93])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBULPIDisable                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBULPIEnable                                                     \
+        ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBULPIRegRead                                                    \
+        ((uint8_t (*)(uint32_t ui32Base,                                      \
+                      uint8_t ui8Reg))ROM_USBTABLE[96])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBULPIRegWrite                                                   \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint8_t ui8Reg,                                            \
+                   uint8_t ui8Data))ROM_USBTABLE[97])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBOTGSessionRequest                                              \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   bool bStart))ROM_USBTABLE[98])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBDMANumChannels                                                 \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBEndpointDMAConfigSet                                           \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Endpoint,                                     \
+                   uint32_t ui32Config))ROM_USBTABLE[100])
+#endif
+#if defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBLPMRemoteWakeEnabled                                           \
+        ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_USBModeConfig                                                     \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Mode))ROM_USBTABLE[103])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogIntClear                                                  \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogRunning                                                   \
+        ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogEnable                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogResetEnable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogResetDisable                                              \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogLock                                                      \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogUnlock                                                    \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogLockState                                                 \
+        ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogReloadSet                                                 \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogReloadGet                                                 \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogValueGet                                                  \
+        ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogIntEnable                                                 \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogIntStatus                                                 \
+        ((uint32_t (*)(uint32_t ui32Base,                                     \
+                       bool bMasked))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogStallEnable                                               \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogStallDisable                                              \
+        ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_WatchdogIntTypeSet                                                \
+        ((void (*)(uint32_t ui32Base,                                         \
+                   uint32_t ui32Type))ROM_WATCHDOGTABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Software API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_Crc16Array                                                        \
+        ((uint16_t (*)(uint32_t ui32WordLen,                                  \
+                       const uint32_t *pui32Data))ROM_SOFTWARETABLE[1])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_Crc16Array3                                                       \
+        ((void (*)(uint32_t ui32WordLen,                                      \
+                   const uint32_t *pui32Data,                                 \
+                   uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_Crc16                                                             \
+        ((uint16_t (*)(uint16_t ui16Crc,                                      \
+                       const uint8_t *pui8Data,                               \
+                       uint32_t ui32Count))ROM_SOFTWARETABLE[3])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_Crc8CCITT                                                         \
+        ((uint8_t (*)(uint8_t ui8Crc,                                         \
+                      const uint8_t *pui8Data,                                \
+                      uint32_t ui32Count))ROM_SOFTWARETABLE[4])
+#endif
+#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_Crc32                                                             \
+        ((uint32_t (*)(uint32_t ui32Crc,                                      \
+                       const uint8_t *pui8Data,                               \
+                       uint32_t ui32Count))ROM_SOFTWARETABLE[5])
+#endif
+#if defined(TARGET_IS_TM4C123_RA1) ||                                         \
+    defined(TARGET_IS_TM4C123_RA3) ||                                         \
+    defined(TARGET_IS_TM4C123_RB1) ||                                         \
+    defined(TARGET_IS_TM4C129_RA0) ||                                         \
+    defined(TARGET_IS_TM4C129_RA1)
+#define ROM_pvAESTable                                                        \
+        ((void *)&(ROM_SOFTWARETABLE[7]))
+#endif
+
+#endif // __DRIVERLIB_ROM_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/rom_map.h b/bsp/tm4c129x/libraries/driverlib/rom_map.h
new file mode 100644
index 0000000000..f7bcb0feed
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/rom_map.h
@@ -0,0 +1,6416 @@
+//*****************************************************************************
+//
+// rom_map.h - Macros to facilitate calling functions in the ROM when they are
+//             available and in flash otherwise.
+//
+// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_ROM_MAP_H__
+#define __DRIVERLIB_ROM_MAP_H__
+
+//*****************************************************************************
+//
+// Macros for the ADC API.
+//
+//*****************************************************************************
+#ifdef ROM_ADCSequenceDataGet
+#define MAP_ADCSequenceDataGet                                                \
+        ROM_ADCSequenceDataGet
+#else
+#define MAP_ADCSequenceDataGet                                                \
+        ADCSequenceDataGet
+#endif
+#ifdef ROM_ADCIntDisable
+#define MAP_ADCIntDisable                                                     \
+        ROM_ADCIntDisable
+#else
+#define MAP_ADCIntDisable                                                     \
+        ADCIntDisable
+#endif
+#ifdef ROM_ADCIntEnable
+#define MAP_ADCIntEnable                                                      \
+        ROM_ADCIntEnable
+#else
+#define MAP_ADCIntEnable                                                      \
+        ADCIntEnable
+#endif
+#ifdef ROM_ADCIntStatus
+#define MAP_ADCIntStatus                                                      \
+        ROM_ADCIntStatus
+#else
+#define MAP_ADCIntStatus                                                      \
+        ADCIntStatus
+#endif
+#ifdef ROM_ADCIntClear
+#define MAP_ADCIntClear                                                       \
+        ROM_ADCIntClear
+#else
+#define MAP_ADCIntClear                                                       \
+        ADCIntClear
+#endif
+#ifdef ROM_ADCSequenceEnable
+#define MAP_ADCSequenceEnable                                                 \
+        ROM_ADCSequenceEnable
+#else
+#define MAP_ADCSequenceEnable                                                 \
+        ADCSequenceEnable
+#endif
+#ifdef ROM_ADCSequenceDisable
+#define MAP_ADCSequenceDisable                                                \
+        ROM_ADCSequenceDisable
+#else
+#define MAP_ADCSequenceDisable                                                \
+        ADCSequenceDisable
+#endif
+#ifdef ROM_ADCSequenceConfigure
+#define MAP_ADCSequenceConfigure                                              \
+        ROM_ADCSequenceConfigure
+#else
+#define MAP_ADCSequenceConfigure                                              \
+        ADCSequenceConfigure
+#endif
+#ifdef ROM_ADCSequenceStepConfigure
+#define MAP_ADCSequenceStepConfigure                                          \
+        ROM_ADCSequenceStepConfigure
+#else
+#define MAP_ADCSequenceStepConfigure                                          \
+        ADCSequenceStepConfigure
+#endif
+#ifdef ROM_ADCSequenceOverflow
+#define MAP_ADCSequenceOverflow                                               \
+        ROM_ADCSequenceOverflow
+#else
+#define MAP_ADCSequenceOverflow                                               \
+        ADCSequenceOverflow
+#endif
+#ifdef ROM_ADCSequenceOverflowClear
+#define MAP_ADCSequenceOverflowClear                                          \
+        ROM_ADCSequenceOverflowClear
+#else
+#define MAP_ADCSequenceOverflowClear                                          \
+        ADCSequenceOverflowClear
+#endif
+#ifdef ROM_ADCSequenceUnderflow
+#define MAP_ADCSequenceUnderflow                                              \
+        ROM_ADCSequenceUnderflow
+#else
+#define MAP_ADCSequenceUnderflow                                              \
+        ADCSequenceUnderflow
+#endif
+#ifdef ROM_ADCSequenceUnderflowClear
+#define MAP_ADCSequenceUnderflowClear                                         \
+        ROM_ADCSequenceUnderflowClear
+#else
+#define MAP_ADCSequenceUnderflowClear                                         \
+        ADCSequenceUnderflowClear
+#endif
+#ifdef ROM_ADCProcessorTrigger
+#define MAP_ADCProcessorTrigger                                               \
+        ROM_ADCProcessorTrigger
+#else
+#define MAP_ADCProcessorTrigger                                               \
+        ADCProcessorTrigger
+#endif
+#ifdef ROM_ADCHardwareOversampleConfigure
+#define MAP_ADCHardwareOversampleConfigure                                    \
+        ROM_ADCHardwareOversampleConfigure
+#else
+#define MAP_ADCHardwareOversampleConfigure                                    \
+        ADCHardwareOversampleConfigure
+#endif
+#ifdef ROM_ADCComparatorConfigure
+#define MAP_ADCComparatorConfigure                                            \
+        ROM_ADCComparatorConfigure
+#else
+#define MAP_ADCComparatorConfigure                                            \
+        ADCComparatorConfigure
+#endif
+#ifdef ROM_ADCComparatorRegionSet
+#define MAP_ADCComparatorRegionSet                                            \
+        ROM_ADCComparatorRegionSet
+#else
+#define MAP_ADCComparatorRegionSet                                            \
+        ADCComparatorRegionSet
+#endif
+#ifdef ROM_ADCComparatorReset
+#define MAP_ADCComparatorReset                                                \
+        ROM_ADCComparatorReset
+#else
+#define MAP_ADCComparatorReset                                                \
+        ADCComparatorReset
+#endif
+#ifdef ROM_ADCComparatorIntDisable
+#define MAP_ADCComparatorIntDisable                                           \
+        ROM_ADCComparatorIntDisable
+#else
+#define MAP_ADCComparatorIntDisable                                           \
+        ADCComparatorIntDisable
+#endif
+#ifdef ROM_ADCComparatorIntEnable
+#define MAP_ADCComparatorIntEnable                                            \
+        ROM_ADCComparatorIntEnable
+#else
+#define MAP_ADCComparatorIntEnable                                            \
+        ADCComparatorIntEnable
+#endif
+#ifdef ROM_ADCComparatorIntStatus
+#define MAP_ADCComparatorIntStatus                                            \
+        ROM_ADCComparatorIntStatus
+#else
+#define MAP_ADCComparatorIntStatus                                            \
+        ADCComparatorIntStatus
+#endif
+#ifdef ROM_ADCComparatorIntClear
+#define MAP_ADCComparatorIntClear                                             \
+        ROM_ADCComparatorIntClear
+#else
+#define MAP_ADCComparatorIntClear                                             \
+        ADCComparatorIntClear
+#endif
+#ifdef ROM_ADCReferenceSet
+#define MAP_ADCReferenceSet                                                   \
+        ROM_ADCReferenceSet
+#else
+#define MAP_ADCReferenceSet                                                   \
+        ADCReferenceSet
+#endif
+#ifdef ROM_ADCReferenceGet
+#define MAP_ADCReferenceGet                                                   \
+        ROM_ADCReferenceGet
+#else
+#define MAP_ADCReferenceGet                                                   \
+        ADCReferenceGet
+#endif
+#ifdef ROM_ADCPhaseDelaySet
+#define MAP_ADCPhaseDelaySet                                                  \
+        ROM_ADCPhaseDelaySet
+#else
+#define MAP_ADCPhaseDelaySet                                                  \
+        ADCPhaseDelaySet
+#endif
+#ifdef ROM_ADCPhaseDelayGet
+#define MAP_ADCPhaseDelayGet                                                  \
+        ROM_ADCPhaseDelayGet
+#else
+#define MAP_ADCPhaseDelayGet                                                  \
+        ADCPhaseDelayGet
+#endif
+#ifdef ROM_ADCIntClearEx
+#define MAP_ADCIntClearEx                                                     \
+        ROM_ADCIntClearEx
+#else
+#define MAP_ADCIntClearEx                                                     \
+        ADCIntClearEx
+#endif
+#ifdef ROM_ADCIntDisableEx
+#define MAP_ADCIntDisableEx                                                   \
+        ROM_ADCIntDisableEx
+#else
+#define MAP_ADCIntDisableEx                                                   \
+        ADCIntDisableEx
+#endif
+#ifdef ROM_ADCIntEnableEx
+#define MAP_ADCIntEnableEx                                                    \
+        ROM_ADCIntEnableEx
+#else
+#define MAP_ADCIntEnableEx                                                    \
+        ADCIntEnableEx
+#endif
+#ifdef ROM_ADCIntStatusEx
+#define MAP_ADCIntStatusEx                                                    \
+        ROM_ADCIntStatusEx
+#else
+#define MAP_ADCIntStatusEx                                                    \
+        ADCIntStatusEx
+#endif
+#ifdef ROM_ADCSequenceDMAEnable
+#define MAP_ADCSequenceDMAEnable                                              \
+        ROM_ADCSequenceDMAEnable
+#else
+#define MAP_ADCSequenceDMAEnable                                              \
+        ADCSequenceDMAEnable
+#endif
+#ifdef ROM_ADCSequenceDMADisable
+#define MAP_ADCSequenceDMADisable                                             \
+        ROM_ADCSequenceDMADisable
+#else
+#define MAP_ADCSequenceDMADisable                                             \
+        ADCSequenceDMADisable
+#endif
+#ifdef ROM_ADCBusy
+#define MAP_ADCBusy                                                           \
+        ROM_ADCBusy
+#else
+#define MAP_ADCBusy                                                           \
+        ADCBusy
+#endif
+
+//*****************************************************************************
+//
+// Macros for the AES API.
+//
+//*****************************************************************************
+#ifdef ROM_AESIntStatus
+#define MAP_AESIntStatus                                                      \
+        ROM_AESIntStatus
+#else
+#define MAP_AESIntStatus                                                      \
+        AESIntStatus
+#endif
+#ifdef ROM_AESAuthLengthSet
+#define MAP_AESAuthLengthSet                                                  \
+        ROM_AESAuthLengthSet
+#else
+#define MAP_AESAuthLengthSet                                                  \
+        AESAuthLengthSet
+#endif
+#ifdef ROM_AESConfigSet
+#define MAP_AESConfigSet                                                      \
+        ROM_AESConfigSet
+#else
+#define MAP_AESConfigSet                                                      \
+        AESConfigSet
+#endif
+#ifdef ROM_AESDataAuth
+#define MAP_AESDataAuth                                                       \
+        ROM_AESDataAuth
+#else
+#define MAP_AESDataAuth                                                       \
+        AESDataAuth
+#endif
+#ifdef ROM_AESDataProcess
+#define MAP_AESDataProcess                                                    \
+        ROM_AESDataProcess
+#else
+#define MAP_AESDataProcess                                                    \
+        AESDataProcess
+#endif
+#ifdef ROM_AESDataProcessAuth
+#define MAP_AESDataProcessAuth                                                \
+        ROM_AESDataProcessAuth
+#else
+#define MAP_AESDataProcessAuth                                                \
+        AESDataProcessAuth
+#endif
+#ifdef ROM_AESDataRead
+#define MAP_AESDataRead                                                       \
+        ROM_AESDataRead
+#else
+#define MAP_AESDataRead                                                       \
+        AESDataRead
+#endif
+#ifdef ROM_AESDataReadNonBlocking
+#define MAP_AESDataReadNonBlocking                                            \
+        ROM_AESDataReadNonBlocking
+#else
+#define MAP_AESDataReadNonBlocking                                            \
+        AESDataReadNonBlocking
+#endif
+#ifdef ROM_AESDataWrite
+#define MAP_AESDataWrite                                                      \
+        ROM_AESDataWrite
+#else
+#define MAP_AESDataWrite                                                      \
+        AESDataWrite
+#endif
+#ifdef ROM_AESDataWriteNonBlocking
+#define MAP_AESDataWriteNonBlocking                                           \
+        ROM_AESDataWriteNonBlocking
+#else
+#define MAP_AESDataWriteNonBlocking                                           \
+        AESDataWriteNonBlocking
+#endif
+#ifdef ROM_AESDMADisable
+#define MAP_AESDMADisable                                                     \
+        ROM_AESDMADisable
+#else
+#define MAP_AESDMADisable                                                     \
+        AESDMADisable
+#endif
+#ifdef ROM_AESDMAEnable
+#define MAP_AESDMAEnable                                                      \
+        ROM_AESDMAEnable
+#else
+#define MAP_AESDMAEnable                                                      \
+        AESDMAEnable
+#endif
+#ifdef ROM_AESIntClear
+#define MAP_AESIntClear                                                       \
+        ROM_AESIntClear
+#else
+#define MAP_AESIntClear                                                       \
+        AESIntClear
+#endif
+#ifdef ROM_AESIntDisable
+#define MAP_AESIntDisable                                                     \
+        ROM_AESIntDisable
+#else
+#define MAP_AESIntDisable                                                     \
+        AESIntDisable
+#endif
+#ifdef ROM_AESIntEnable
+#define MAP_AESIntEnable                                                      \
+        ROM_AESIntEnable
+#else
+#define MAP_AESIntEnable                                                      \
+        AESIntEnable
+#endif
+#ifdef ROM_AESIVSet
+#define MAP_AESIVSet                                                          \
+        ROM_AESIVSet
+#else
+#define MAP_AESIVSet                                                          \
+        AESIVSet
+#endif
+#ifdef ROM_AESKey1Set
+#define MAP_AESKey1Set                                                        \
+        ROM_AESKey1Set
+#else
+#define MAP_AESKey1Set                                                        \
+        AESKey1Set
+#endif
+#ifdef ROM_AESKey2Set
+#define MAP_AESKey2Set                                                        \
+        ROM_AESKey2Set
+#else
+#define MAP_AESKey2Set                                                        \
+        AESKey2Set
+#endif
+#ifdef ROM_AESKey3Set
+#define MAP_AESKey3Set                                                        \
+        ROM_AESKey3Set
+#else
+#define MAP_AESKey3Set                                                        \
+        AESKey3Set
+#endif
+#ifdef ROM_AESLengthSet
+#define MAP_AESLengthSet                                                      \
+        ROM_AESLengthSet
+#else
+#define MAP_AESLengthSet                                                      \
+        AESLengthSet
+#endif
+#ifdef ROM_AESReset
+#define MAP_AESReset                                                          \
+        ROM_AESReset
+#else
+#define MAP_AESReset                                                          \
+        AESReset
+#endif
+#ifdef ROM_AESTagRead
+#define MAP_AESTagRead                                                        \
+        ROM_AESTagRead
+#else
+#define MAP_AESTagRead                                                        \
+        AESTagRead
+#endif
+#ifdef ROM_AESIVRead
+#define MAP_AESIVRead                                                         \
+        ROM_AESIVRead
+#else
+#define MAP_AESIVRead                                                         \
+        AESIVRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CAN API.
+//
+//*****************************************************************************
+#ifdef ROM_CANIntClear
+#define MAP_CANIntClear                                                       \
+        ROM_CANIntClear
+#else
+#define MAP_CANIntClear                                                       \
+        CANIntClear
+#endif
+#ifdef ROM_CANInit
+#define MAP_CANInit                                                           \
+        ROM_CANInit
+#else
+#define MAP_CANInit                                                           \
+        CANInit
+#endif
+#ifdef ROM_CANEnable
+#define MAP_CANEnable                                                         \
+        ROM_CANEnable
+#else
+#define MAP_CANEnable                                                         \
+        CANEnable
+#endif
+#ifdef ROM_CANDisable
+#define MAP_CANDisable                                                        \
+        ROM_CANDisable
+#else
+#define MAP_CANDisable                                                        \
+        CANDisable
+#endif
+#ifdef ROM_CANBitTimingSet
+#define MAP_CANBitTimingSet                                                   \
+        ROM_CANBitTimingSet
+#else
+#define MAP_CANBitTimingSet                                                   \
+        CANBitTimingSet
+#endif
+#ifdef ROM_CANBitTimingGet
+#define MAP_CANBitTimingGet                                                   \
+        ROM_CANBitTimingGet
+#else
+#define MAP_CANBitTimingGet                                                   \
+        CANBitTimingGet
+#endif
+#ifdef ROM_CANMessageSet
+#define MAP_CANMessageSet                                                     \
+        ROM_CANMessageSet
+#else
+#define MAP_CANMessageSet                                                     \
+        CANMessageSet
+#endif
+#ifdef ROM_CANMessageGet
+#define MAP_CANMessageGet                                                     \
+        ROM_CANMessageGet
+#else
+#define MAP_CANMessageGet                                                     \
+        CANMessageGet
+#endif
+#ifdef ROM_CANStatusGet
+#define MAP_CANStatusGet                                                      \
+        ROM_CANStatusGet
+#else
+#define MAP_CANStatusGet                                                      \
+        CANStatusGet
+#endif
+#ifdef ROM_CANMessageClear
+#define MAP_CANMessageClear                                                   \
+        ROM_CANMessageClear
+#else
+#define MAP_CANMessageClear                                                   \
+        CANMessageClear
+#endif
+#ifdef ROM_CANIntEnable
+#define MAP_CANIntEnable                                                      \
+        ROM_CANIntEnable
+#else
+#define MAP_CANIntEnable                                                      \
+        CANIntEnable
+#endif
+#ifdef ROM_CANIntDisable
+#define MAP_CANIntDisable                                                     \
+        ROM_CANIntDisable
+#else
+#define MAP_CANIntDisable                                                     \
+        CANIntDisable
+#endif
+#ifdef ROM_CANIntStatus
+#define MAP_CANIntStatus                                                      \
+        ROM_CANIntStatus
+#else
+#define MAP_CANIntStatus                                                      \
+        CANIntStatus
+#endif
+#ifdef ROM_CANRetryGet
+#define MAP_CANRetryGet                                                       \
+        ROM_CANRetryGet
+#else
+#define MAP_CANRetryGet                                                       \
+        CANRetryGet
+#endif
+#ifdef ROM_CANRetrySet
+#define MAP_CANRetrySet                                                       \
+        ROM_CANRetrySet
+#else
+#define MAP_CANRetrySet                                                       \
+        CANRetrySet
+#endif
+#ifdef ROM_CANErrCntrGet
+#define MAP_CANErrCntrGet                                                     \
+        ROM_CANErrCntrGet
+#else
+#define MAP_CANErrCntrGet                                                     \
+        CANErrCntrGet
+#endif
+#ifdef ROM_CANBitRateSet
+#define MAP_CANBitRateSet                                                     \
+        ROM_CANBitRateSet
+#else
+#define MAP_CANBitRateSet                                                     \
+        CANBitRateSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Comparator API.
+//
+//*****************************************************************************
+#ifdef ROM_ComparatorIntClear
+#define MAP_ComparatorIntClear                                                \
+        ROM_ComparatorIntClear
+#else
+#define MAP_ComparatorIntClear                                                \
+        ComparatorIntClear
+#endif
+#ifdef ROM_ComparatorConfigure
+#define MAP_ComparatorConfigure                                               \
+        ROM_ComparatorConfigure
+#else
+#define MAP_ComparatorConfigure                                               \
+        ComparatorConfigure
+#endif
+#ifdef ROM_ComparatorRefSet
+#define MAP_ComparatorRefSet                                                  \
+        ROM_ComparatorRefSet
+#else
+#define MAP_ComparatorRefSet                                                  \
+        ComparatorRefSet
+#endif
+#ifdef ROM_ComparatorValueGet
+#define MAP_ComparatorValueGet                                                \
+        ROM_ComparatorValueGet
+#else
+#define MAP_ComparatorValueGet                                                \
+        ComparatorValueGet
+#endif
+#ifdef ROM_ComparatorIntEnable
+#define MAP_ComparatorIntEnable                                               \
+        ROM_ComparatorIntEnable
+#else
+#define MAP_ComparatorIntEnable                                               \
+        ComparatorIntEnable
+#endif
+#ifdef ROM_ComparatorIntDisable
+#define MAP_ComparatorIntDisable                                              \
+        ROM_ComparatorIntDisable
+#else
+#define MAP_ComparatorIntDisable                                              \
+        ComparatorIntDisable
+#endif
+#ifdef ROM_ComparatorIntStatus
+#define MAP_ComparatorIntStatus                                               \
+        ROM_ComparatorIntStatus
+#else
+#define MAP_ComparatorIntStatus                                               \
+        ComparatorIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CRC API.
+//
+//*****************************************************************************
+#ifdef ROM_CRCConfigSet
+#define MAP_CRCConfigSet                                                      \
+        ROM_CRCConfigSet
+#else
+#define MAP_CRCConfigSet                                                      \
+        CRCConfigSet
+#endif
+#ifdef ROM_CRCDataProcess
+#define MAP_CRCDataProcess                                                    \
+        ROM_CRCDataProcess
+#else
+#define MAP_CRCDataProcess                                                    \
+        CRCDataProcess
+#endif
+#ifdef ROM_CRCDataWrite
+#define MAP_CRCDataWrite                                                      \
+        ROM_CRCDataWrite
+#else
+#define MAP_CRCDataWrite                                                      \
+        CRCDataWrite
+#endif
+#ifdef ROM_CRCResultRead
+#define MAP_CRCResultRead                                                     \
+        ROM_CRCResultRead
+#else
+#define MAP_CRCResultRead                                                     \
+        CRCResultRead
+#endif
+#ifdef ROM_CRCSeedSet
+#define MAP_CRCSeedSet                                                        \
+        ROM_CRCSeedSet
+#else
+#define MAP_CRCSeedSet                                                        \
+        CRCSeedSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the DES API.
+//
+//*****************************************************************************
+#ifdef ROM_DESIntStatus
+#define MAP_DESIntStatus                                                      \
+        ROM_DESIntStatus
+#else
+#define MAP_DESIntStatus                                                      \
+        DESIntStatus
+#endif
+#ifdef ROM_DESConfigSet
+#define MAP_DESConfigSet                                                      \
+        ROM_DESConfigSet
+#else
+#define MAP_DESConfigSet                                                      \
+        DESConfigSet
+#endif
+#ifdef ROM_DESDataRead
+#define MAP_DESDataRead                                                       \
+        ROM_DESDataRead
+#else
+#define MAP_DESDataRead                                                       \
+        DESDataRead
+#endif
+#ifdef ROM_DESDataReadNonBlocking
+#define MAP_DESDataReadNonBlocking                                            \
+        ROM_DESDataReadNonBlocking
+#else
+#define MAP_DESDataReadNonBlocking                                            \
+        DESDataReadNonBlocking
+#endif
+#ifdef ROM_DESDataProcess
+#define MAP_DESDataProcess                                                    \
+        ROM_DESDataProcess
+#else
+#define MAP_DESDataProcess                                                    \
+        DESDataProcess
+#endif
+#ifdef ROM_DESDataWrite
+#define MAP_DESDataWrite                                                      \
+        ROM_DESDataWrite
+#else
+#define MAP_DESDataWrite                                                      \
+        DESDataWrite
+#endif
+#ifdef ROM_DESDataWriteNonBlocking
+#define MAP_DESDataWriteNonBlocking                                           \
+        ROM_DESDataWriteNonBlocking
+#else
+#define MAP_DESDataWriteNonBlocking                                           \
+        DESDataWriteNonBlocking
+#endif
+#ifdef ROM_DESDMADisable
+#define MAP_DESDMADisable                                                     \
+        ROM_DESDMADisable
+#else
+#define MAP_DESDMADisable                                                     \
+        DESDMADisable
+#endif
+#ifdef ROM_DESDMAEnable
+#define MAP_DESDMAEnable                                                      \
+        ROM_DESDMAEnable
+#else
+#define MAP_DESDMAEnable                                                      \
+        DESDMAEnable
+#endif
+#ifdef ROM_DESIntClear
+#define MAP_DESIntClear                                                       \
+        ROM_DESIntClear
+#else
+#define MAP_DESIntClear                                                       \
+        DESIntClear
+#endif
+#ifdef ROM_DESIntDisable
+#define MAP_DESIntDisable                                                     \
+        ROM_DESIntDisable
+#else
+#define MAP_DESIntDisable                                                     \
+        DESIntDisable
+#endif
+#ifdef ROM_DESIntEnable
+#define MAP_DESIntEnable                                                      \
+        ROM_DESIntEnable
+#else
+#define MAP_DESIntEnable                                                      \
+        DESIntEnable
+#endif
+#ifdef ROM_DESIVSet
+#define MAP_DESIVSet                                                          \
+        ROM_DESIVSet
+#else
+#define MAP_DESIVSet                                                          \
+        DESIVSet
+#endif
+#ifdef ROM_DESKeySet
+#define MAP_DESKeySet                                                         \
+        ROM_DESKeySet
+#else
+#define MAP_DESKeySet                                                         \
+        DESKeySet
+#endif
+#ifdef ROM_DESLengthSet
+#define MAP_DESLengthSet                                                      \
+        ROM_DESLengthSet
+#else
+#define MAP_DESLengthSet                                                      \
+        DESLengthSet
+#endif
+#ifdef ROM_DESReset
+#define MAP_DESReset                                                          \
+        ROM_DESReset
+#else
+#define MAP_DESReset                                                          \
+        DESReset
+#endif
+
+//*****************************************************************************
+//
+// Macros for the EEPROM API.
+//
+//*****************************************************************************
+#ifdef ROM_EEPROMRead
+#define MAP_EEPROMRead                                                        \
+        ROM_EEPROMRead
+#else
+#define MAP_EEPROMRead                                                        \
+        EEPROMRead
+#endif
+#ifdef ROM_EEPROMBlockCountGet
+#define MAP_EEPROMBlockCountGet                                               \
+        ROM_EEPROMBlockCountGet
+#else
+#define MAP_EEPROMBlockCountGet                                               \
+        EEPROMBlockCountGet
+#endif
+#ifdef ROM_EEPROMBlockHide
+#define MAP_EEPROMBlockHide                                                   \
+        ROM_EEPROMBlockHide
+#else
+#define MAP_EEPROMBlockHide                                                   \
+        EEPROMBlockHide
+#endif
+#ifdef ROM_EEPROMBlockLock
+#define MAP_EEPROMBlockLock                                                   \
+        ROM_EEPROMBlockLock
+#else
+#define MAP_EEPROMBlockLock                                                   \
+        EEPROMBlockLock
+#endif
+#ifdef ROM_EEPROMBlockPasswordSet
+#define MAP_EEPROMBlockPasswordSet                                            \
+        ROM_EEPROMBlockPasswordSet
+#else
+#define MAP_EEPROMBlockPasswordSet                                            \
+        EEPROMBlockPasswordSet
+#endif
+#ifdef ROM_EEPROMBlockProtectGet
+#define MAP_EEPROMBlockProtectGet                                             \
+        ROM_EEPROMBlockProtectGet
+#else
+#define MAP_EEPROMBlockProtectGet                                             \
+        EEPROMBlockProtectGet
+#endif
+#ifdef ROM_EEPROMBlockProtectSet
+#define MAP_EEPROMBlockProtectSet                                             \
+        ROM_EEPROMBlockProtectSet
+#else
+#define MAP_EEPROMBlockProtectSet                                             \
+        EEPROMBlockProtectSet
+#endif
+#ifdef ROM_EEPROMBlockUnlock
+#define MAP_EEPROMBlockUnlock                                                 \
+        ROM_EEPROMBlockUnlock
+#else
+#define MAP_EEPROMBlockUnlock                                                 \
+        EEPROMBlockUnlock
+#endif
+#ifdef ROM_EEPROMIntClear
+#define MAP_EEPROMIntClear                                                    \
+        ROM_EEPROMIntClear
+#else
+#define MAP_EEPROMIntClear                                                    \
+        EEPROMIntClear
+#endif
+#ifdef ROM_EEPROMIntDisable
+#define MAP_EEPROMIntDisable                                                  \
+        ROM_EEPROMIntDisable
+#else
+#define MAP_EEPROMIntDisable                                                  \
+        EEPROMIntDisable
+#endif
+#ifdef ROM_EEPROMIntEnable
+#define MAP_EEPROMIntEnable                                                   \
+        ROM_EEPROMIntEnable
+#else
+#define MAP_EEPROMIntEnable                                                   \
+        EEPROMIntEnable
+#endif
+#ifdef ROM_EEPROMIntStatus
+#define MAP_EEPROMIntStatus                                                   \
+        ROM_EEPROMIntStatus
+#else
+#define MAP_EEPROMIntStatus                                                   \
+        EEPROMIntStatus
+#endif
+#ifdef ROM_EEPROMMassErase
+#define MAP_EEPROMMassErase                                                   \
+        ROM_EEPROMMassErase
+#else
+#define MAP_EEPROMMassErase                                                   \
+        EEPROMMassErase
+#endif
+#ifdef ROM_EEPROMProgram
+#define MAP_EEPROMProgram                                                     \
+        ROM_EEPROMProgram
+#else
+#define MAP_EEPROMProgram                                                     \
+        EEPROMProgram
+#endif
+#ifdef ROM_EEPROMProgramNonBlocking
+#define MAP_EEPROMProgramNonBlocking                                          \
+        ROM_EEPROMProgramNonBlocking
+#else
+#define MAP_EEPROMProgramNonBlocking                                          \
+        EEPROMProgramNonBlocking
+#endif
+#ifdef ROM_EEPROMSizeGet
+#define MAP_EEPROMSizeGet                                                     \
+        ROM_EEPROMSizeGet
+#else
+#define MAP_EEPROMSizeGet                                                     \
+        EEPROMSizeGet
+#endif
+#ifdef ROM_EEPROMStatusGet
+#define MAP_EEPROMStatusGet                                                   \
+        ROM_EEPROMStatusGet
+#else
+#define MAP_EEPROMStatusGet                                                   \
+        EEPROMStatusGet
+#endif
+#ifdef ROM_EEPROMInit
+#define MAP_EEPROMInit                                                        \
+        ROM_EEPROMInit
+#else
+#define MAP_EEPROMInit                                                        \
+        EEPROMInit
+#endif
+
+//*****************************************************************************
+//
+// Macros for the EPI API.
+//
+//*****************************************************************************
+#ifdef ROM_EPIIntStatus
+#define MAP_EPIIntStatus                                                      \
+        ROM_EPIIntStatus
+#else
+#define MAP_EPIIntStatus                                                      \
+        EPIIntStatus
+#endif
+#ifdef ROM_EPIModeSet
+#define MAP_EPIModeSet                                                        \
+        ROM_EPIModeSet
+#else
+#define MAP_EPIModeSet                                                        \
+        EPIModeSet
+#endif
+#ifdef ROM_EPIDividerSet
+#define MAP_EPIDividerSet                                                     \
+        ROM_EPIDividerSet
+#else
+#define MAP_EPIDividerSet                                                     \
+        EPIDividerSet
+#endif
+#ifdef ROM_EPIConfigSDRAMSet
+#define MAP_EPIConfigSDRAMSet                                                 \
+        ROM_EPIConfigSDRAMSet
+#else
+#define MAP_EPIConfigSDRAMSet                                                 \
+        EPIConfigSDRAMSet
+#endif
+#ifdef ROM_EPIConfigGPModeSet
+#define MAP_EPIConfigGPModeSet                                                \
+        ROM_EPIConfigGPModeSet
+#else
+#define MAP_EPIConfigGPModeSet                                                \
+        EPIConfigGPModeSet
+#endif
+#ifdef ROM_EPIConfigHB8Set
+#define MAP_EPIConfigHB8Set                                                   \
+        ROM_EPIConfigHB8Set
+#else
+#define MAP_EPIConfigHB8Set                                                   \
+        EPIConfigHB8Set
+#endif
+#ifdef ROM_EPIConfigHB16Set
+#define MAP_EPIConfigHB16Set                                                  \
+        ROM_EPIConfigHB16Set
+#else
+#define MAP_EPIConfigHB16Set                                                  \
+        EPIConfigHB16Set
+#endif
+#ifdef ROM_EPIAddressMapSet
+#define MAP_EPIAddressMapSet                                                  \
+        ROM_EPIAddressMapSet
+#else
+#define MAP_EPIAddressMapSet                                                  \
+        EPIAddressMapSet
+#endif
+#ifdef ROM_EPINonBlockingReadConfigure
+#define MAP_EPINonBlockingReadConfigure                                       \
+        ROM_EPINonBlockingReadConfigure
+#else
+#define MAP_EPINonBlockingReadConfigure                                       \
+        EPINonBlockingReadConfigure
+#endif
+#ifdef ROM_EPINonBlockingReadStart
+#define MAP_EPINonBlockingReadStart                                           \
+        ROM_EPINonBlockingReadStart
+#else
+#define MAP_EPINonBlockingReadStart                                           \
+        EPINonBlockingReadStart
+#endif
+#ifdef ROM_EPINonBlockingReadStop
+#define MAP_EPINonBlockingReadStop                                            \
+        ROM_EPINonBlockingReadStop
+#else
+#define MAP_EPINonBlockingReadStop                                            \
+        EPINonBlockingReadStop
+#endif
+#ifdef ROM_EPINonBlockingReadCount
+#define MAP_EPINonBlockingReadCount                                           \
+        ROM_EPINonBlockingReadCount
+#else
+#define MAP_EPINonBlockingReadCount                                           \
+        EPINonBlockingReadCount
+#endif
+#ifdef ROM_EPINonBlockingReadAvail
+#define MAP_EPINonBlockingReadAvail                                           \
+        ROM_EPINonBlockingReadAvail
+#else
+#define MAP_EPINonBlockingReadAvail                                           \
+        EPINonBlockingReadAvail
+#endif
+#ifdef ROM_EPINonBlockingReadGet32
+#define MAP_EPINonBlockingReadGet32                                           \
+        ROM_EPINonBlockingReadGet32
+#else
+#define MAP_EPINonBlockingReadGet32                                           \
+        EPINonBlockingReadGet32
+#endif
+#ifdef ROM_EPINonBlockingReadGet16
+#define MAP_EPINonBlockingReadGet16                                           \
+        ROM_EPINonBlockingReadGet16
+#else
+#define MAP_EPINonBlockingReadGet16                                           \
+        EPINonBlockingReadGet16
+#endif
+#ifdef ROM_EPINonBlockingReadGet8
+#define MAP_EPINonBlockingReadGet8                                            \
+        ROM_EPINonBlockingReadGet8
+#else
+#define MAP_EPINonBlockingReadGet8                                            \
+        EPINonBlockingReadGet8
+#endif
+#ifdef ROM_EPIFIFOConfig
+#define MAP_EPIFIFOConfig                                                     \
+        ROM_EPIFIFOConfig
+#else
+#define MAP_EPIFIFOConfig                                                     \
+        EPIFIFOConfig
+#endif
+#ifdef ROM_EPIWriteFIFOCountGet
+#define MAP_EPIWriteFIFOCountGet                                              \
+        ROM_EPIWriteFIFOCountGet
+#else
+#define MAP_EPIWriteFIFOCountGet                                              \
+        EPIWriteFIFOCountGet
+#endif
+#ifdef ROM_EPIIntEnable
+#define MAP_EPIIntEnable                                                      \
+        ROM_EPIIntEnable
+#else
+#define MAP_EPIIntEnable                                                      \
+        EPIIntEnable
+#endif
+#ifdef ROM_EPIIntDisable
+#define MAP_EPIIntDisable                                                     \
+        ROM_EPIIntDisable
+#else
+#define MAP_EPIIntDisable                                                     \
+        EPIIntDisable
+#endif
+#ifdef ROM_EPIIntErrorStatus
+#define MAP_EPIIntErrorStatus                                                 \
+        ROM_EPIIntErrorStatus
+#else
+#define MAP_EPIIntErrorStatus                                                 \
+        EPIIntErrorStatus
+#endif
+#ifdef ROM_EPIIntErrorClear
+#define MAP_EPIIntErrorClear                                                  \
+        ROM_EPIIntErrorClear
+#else
+#define MAP_EPIIntErrorClear                                                  \
+        EPIIntErrorClear
+#endif
+#ifdef ROM_EPIDividerCSSet
+#define MAP_EPIDividerCSSet                                                   \
+        ROM_EPIDividerCSSet
+#else
+#define MAP_EPIDividerCSSet                                                   \
+        EPIDividerCSSet
+#endif
+#ifdef ROM_EPIDMATxCount
+#define MAP_EPIDMATxCount                                                     \
+        ROM_EPIDMATxCount
+#else
+#define MAP_EPIDMATxCount                                                     \
+        EPIDMATxCount
+#endif
+#ifdef ROM_EPIConfigHB8CSSet
+#define MAP_EPIConfigHB8CSSet                                                 \
+        ROM_EPIConfigHB8CSSet
+#else
+#define MAP_EPIConfigHB8CSSet                                                 \
+        EPIConfigHB8CSSet
+#endif
+#ifdef ROM_EPIConfigHB16CSSet
+#define MAP_EPIConfigHB16CSSet                                                \
+        ROM_EPIConfigHB16CSSet
+#else
+#define MAP_EPIConfigHB16CSSet                                                \
+        EPIConfigHB16CSSet
+#endif
+#ifdef ROM_EPIConfigHB8TimingSet
+#define MAP_EPIConfigHB8TimingSet                                             \
+        ROM_EPIConfigHB8TimingSet
+#else
+#define MAP_EPIConfigHB8TimingSet                                             \
+        EPIConfigHB8TimingSet
+#endif
+#ifdef ROM_EPIConfigHB16TimingSet
+#define MAP_EPIConfigHB16TimingSet                                            \
+        ROM_EPIConfigHB16TimingSet
+#else
+#define MAP_EPIConfigHB16TimingSet                                            \
+        EPIConfigHB16TimingSet
+#endif
+#ifdef ROM_EPIPSRAMConfigRegSet
+#define MAP_EPIPSRAMConfigRegSet                                              \
+        ROM_EPIPSRAMConfigRegSet
+#else
+#define MAP_EPIPSRAMConfigRegSet                                              \
+        EPIPSRAMConfigRegSet
+#endif
+#ifdef ROM_EPIPSRAMConfigRegRead
+#define MAP_EPIPSRAMConfigRegRead                                             \
+        ROM_EPIPSRAMConfigRegRead
+#else
+#define MAP_EPIPSRAMConfigRegRead                                             \
+        EPIPSRAMConfigRegRead
+#endif
+#ifdef ROM_EPIPSRAMConfigRegGetNonBlocking
+#define MAP_EPIPSRAMConfigRegGetNonBlocking                                   \
+        ROM_EPIPSRAMConfigRegGetNonBlocking
+#else
+#define MAP_EPIPSRAMConfigRegGetNonBlocking                                   \
+        EPIPSRAMConfigRegGetNonBlocking
+#endif
+#ifdef ROM_EPIPSRAMConfigRegGet
+#define MAP_EPIPSRAMConfigRegGet                                              \
+        ROM_EPIPSRAMConfigRegGet
+#else
+#define MAP_EPIPSRAMConfigRegGet                                              \
+        EPIPSRAMConfigRegGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the EMAC API.
+//
+//*****************************************************************************
+#ifdef ROM_EMACIntStatus
+#define MAP_EMACIntStatus                                                     \
+        ROM_EMACIntStatus
+#else
+#define MAP_EMACIntStatus                                                     \
+        EMACIntStatus
+#endif
+#ifdef ROM_EMACAddrGet
+#define MAP_EMACAddrGet                                                       \
+        ROM_EMACAddrGet
+#else
+#define MAP_EMACAddrGet                                                       \
+        EMACAddrGet
+#endif
+#ifdef ROM_EMACAddrSet
+#define MAP_EMACAddrSet                                                       \
+        ROM_EMACAddrSet
+#else
+#define MAP_EMACAddrSet                                                       \
+        EMACAddrSet
+#endif
+#ifdef ROM_EMACConfigGet
+#define MAP_EMACConfigGet                                                     \
+        ROM_EMACConfigGet
+#else
+#define MAP_EMACConfigGet                                                     \
+        EMACConfigGet
+#endif
+#ifdef ROM_EMACConfigSet
+#define MAP_EMACConfigSet                                                     \
+        ROM_EMACConfigSet
+#else
+#define MAP_EMACConfigSet                                                     \
+        EMACConfigSet
+#endif
+#ifdef ROM_EMACDMAStateGet
+#define MAP_EMACDMAStateGet                                                   \
+        ROM_EMACDMAStateGet
+#else
+#define MAP_EMACDMAStateGet                                                   \
+        EMACDMAStateGet
+#endif
+#ifdef ROM_EMACFrameFilterGet
+#define MAP_EMACFrameFilterGet                                                \
+        ROM_EMACFrameFilterGet
+#else
+#define MAP_EMACFrameFilterGet                                                \
+        EMACFrameFilterGet
+#endif
+#ifdef ROM_EMACFrameFilterSet
+#define MAP_EMACFrameFilterSet                                                \
+        ROM_EMACFrameFilterSet
+#else
+#define MAP_EMACFrameFilterSet                                                \
+        EMACFrameFilterSet
+#endif
+#ifdef ROM_EMACInit
+#define MAP_EMACInit                                                          \
+        ROM_EMACInit
+#else
+#define MAP_EMACInit                                                          \
+        EMACInit
+#endif
+#ifdef ROM_EMACIntClear
+#define MAP_EMACIntClear                                                      \
+        ROM_EMACIntClear
+#else
+#define MAP_EMACIntClear                                                      \
+        EMACIntClear
+#endif
+#ifdef ROM_EMACIntDisable
+#define MAP_EMACIntDisable                                                    \
+        ROM_EMACIntDisable
+#else
+#define MAP_EMACIntDisable                                                    \
+        EMACIntDisable
+#endif
+#ifdef ROM_EMACIntEnable
+#define MAP_EMACIntEnable                                                     \
+        ROM_EMACIntEnable
+#else
+#define MAP_EMACIntEnable                                                     \
+        EMACIntEnable
+#endif
+#ifdef ROM_EMACPHYConfigSet
+#define MAP_EMACPHYConfigSet                                                  \
+        ROM_EMACPHYConfigSet
+#else
+#define MAP_EMACPHYConfigSet                                                  \
+        EMACPHYConfigSet
+#endif
+#ifdef ROM_EMACPHYPowerOff
+#define MAP_EMACPHYPowerOff                                                   \
+        ROM_EMACPHYPowerOff
+#else
+#define MAP_EMACPHYPowerOff                                                   \
+        EMACPHYPowerOff
+#endif
+#ifdef ROM_EMACPHYPowerOn
+#define MAP_EMACPHYPowerOn                                                    \
+        ROM_EMACPHYPowerOn
+#else
+#define MAP_EMACPHYPowerOn                                                    \
+        EMACPHYPowerOn
+#endif
+#ifdef ROM_EMACPHYRead
+#define MAP_EMACPHYRead                                                       \
+        ROM_EMACPHYRead
+#else
+#define MAP_EMACPHYRead                                                       \
+        EMACPHYRead
+#endif
+#ifdef ROM_EMACPHYWrite
+#define MAP_EMACPHYWrite                                                      \
+        ROM_EMACPHYWrite
+#else
+#define MAP_EMACPHYWrite                                                      \
+        EMACPHYWrite
+#endif
+#ifdef ROM_EMACReset
+#define MAP_EMACReset                                                         \
+        ROM_EMACReset
+#else
+#define MAP_EMACReset                                                         \
+        EMACReset
+#endif
+#ifdef ROM_EMACRxDisable
+#define MAP_EMACRxDisable                                                     \
+        ROM_EMACRxDisable
+#else
+#define MAP_EMACRxDisable                                                     \
+        EMACRxDisable
+#endif
+#ifdef ROM_EMACRxDMACurrentBufferGet
+#define MAP_EMACRxDMACurrentBufferGet                                         \
+        ROM_EMACRxDMACurrentBufferGet
+#else
+#define MAP_EMACRxDMACurrentBufferGet                                         \
+        EMACRxDMACurrentBufferGet
+#endif
+#ifdef ROM_EMACRxDMACurrentDescriptorGet
+#define MAP_EMACRxDMACurrentDescriptorGet                                     \
+        ROM_EMACRxDMACurrentDescriptorGet
+#else
+#define MAP_EMACRxDMACurrentDescriptorGet                                     \
+        EMACRxDMACurrentDescriptorGet
+#endif
+#ifdef ROM_EMACRxDMADescriptorListGet
+#define MAP_EMACRxDMADescriptorListGet                                        \
+        ROM_EMACRxDMADescriptorListGet
+#else
+#define MAP_EMACRxDMADescriptorListGet                                        \
+        EMACRxDMADescriptorListGet
+#endif
+#ifdef ROM_EMACRxDMADescriptorListSet
+#define MAP_EMACRxDMADescriptorListSet                                        \
+        ROM_EMACRxDMADescriptorListSet
+#else
+#define MAP_EMACRxDMADescriptorListSet                                        \
+        EMACRxDMADescriptorListSet
+#endif
+#ifdef ROM_EMACRxDMAPollDemand
+#define MAP_EMACRxDMAPollDemand                                               \
+        ROM_EMACRxDMAPollDemand
+#else
+#define MAP_EMACRxDMAPollDemand                                               \
+        EMACRxDMAPollDemand
+#endif
+#ifdef ROM_EMACRxEnable
+#define MAP_EMACRxEnable                                                      \
+        ROM_EMACRxEnable
+#else
+#define MAP_EMACRxEnable                                                      \
+        EMACRxEnable
+#endif
+#ifdef ROM_EMACRxWatchdogTimerSet
+#define MAP_EMACRxWatchdogTimerSet                                            \
+        ROM_EMACRxWatchdogTimerSet
+#else
+#define MAP_EMACRxWatchdogTimerSet                                            \
+        EMACRxWatchdogTimerSet
+#endif
+#ifdef ROM_EMACStatusGet
+#define MAP_EMACStatusGet                                                     \
+        ROM_EMACStatusGet
+#else
+#define MAP_EMACStatusGet                                                     \
+        EMACStatusGet
+#endif
+#ifdef ROM_EMACTxDisable
+#define MAP_EMACTxDisable                                                     \
+        ROM_EMACTxDisable
+#else
+#define MAP_EMACTxDisable                                                     \
+        EMACTxDisable
+#endif
+#ifdef ROM_EMACTxDMACurrentBufferGet
+#define MAP_EMACTxDMACurrentBufferGet                                         \
+        ROM_EMACTxDMACurrentBufferGet
+#else
+#define MAP_EMACTxDMACurrentBufferGet                                         \
+        EMACTxDMACurrentBufferGet
+#endif
+#ifdef ROM_EMACTxDMACurrentDescriptorGet
+#define MAP_EMACTxDMACurrentDescriptorGet                                     \
+        ROM_EMACTxDMACurrentDescriptorGet
+#else
+#define MAP_EMACTxDMACurrentDescriptorGet                                     \
+        EMACTxDMACurrentDescriptorGet
+#endif
+#ifdef ROM_EMACTxDMADescriptorListGet
+#define MAP_EMACTxDMADescriptorListGet                                        \
+        ROM_EMACTxDMADescriptorListGet
+#else
+#define MAP_EMACTxDMADescriptorListGet                                        \
+        EMACTxDMADescriptorListGet
+#endif
+#ifdef ROM_EMACTxDMADescriptorListSet
+#define MAP_EMACTxDMADescriptorListSet                                        \
+        ROM_EMACTxDMADescriptorListSet
+#else
+#define MAP_EMACTxDMADescriptorListSet                                        \
+        EMACTxDMADescriptorListSet
+#endif
+#ifdef ROM_EMACTxDMAPollDemand
+#define MAP_EMACTxDMAPollDemand                                               \
+        ROM_EMACTxDMAPollDemand
+#else
+#define MAP_EMACTxDMAPollDemand                                               \
+        EMACTxDMAPollDemand
+#endif
+#ifdef ROM_EMACTxEnable
+#define MAP_EMACTxEnable                                                      \
+        ROM_EMACTxEnable
+#else
+#define MAP_EMACTxEnable                                                      \
+        EMACTxEnable
+#endif
+#ifdef ROM_EMACTxFlush
+#define MAP_EMACTxFlush                                                       \
+        ROM_EMACTxFlush
+#else
+#define MAP_EMACTxFlush                                                       \
+        EMACTxFlush
+#endif
+#ifdef ROM_EMACAddrFilterGet
+#define MAP_EMACAddrFilterGet                                                 \
+        ROM_EMACAddrFilterGet
+#else
+#define MAP_EMACAddrFilterGet                                                 \
+        EMACAddrFilterGet
+#endif
+#ifdef ROM_EMACAddrFilterSet
+#define MAP_EMACAddrFilterSet                                                 \
+        ROM_EMACAddrFilterSet
+#else
+#define MAP_EMACAddrFilterSet                                                 \
+        EMACAddrFilterSet
+#endif
+#ifdef ROM_EMACHashFilterBitCalculate
+#define MAP_EMACHashFilterBitCalculate                                        \
+        ROM_EMACHashFilterBitCalculate
+#else
+#define MAP_EMACHashFilterBitCalculate                                        \
+        EMACHashFilterBitCalculate
+#endif
+#ifdef ROM_EMACHashFilterGet
+#define MAP_EMACHashFilterGet                                                 \
+        ROM_EMACHashFilterGet
+#else
+#define MAP_EMACHashFilterGet                                                 \
+        EMACHashFilterGet
+#endif
+#ifdef ROM_EMACHashFilterSet
+#define MAP_EMACHashFilterSet                                                 \
+        ROM_EMACHashFilterSet
+#else
+#define MAP_EMACHashFilterSet                                                 \
+        EMACHashFilterSet
+#endif
+#ifdef ROM_EMACNumAddrGet
+#define MAP_EMACNumAddrGet                                                    \
+        ROM_EMACNumAddrGet
+#else
+#define MAP_EMACNumAddrGet                                                    \
+        EMACNumAddrGet
+#endif
+#ifdef ROM_EMACPHYExtendedRead
+#define MAP_EMACPHYExtendedRead                                               \
+        ROM_EMACPHYExtendedRead
+#else
+#define MAP_EMACPHYExtendedRead                                               \
+        EMACPHYExtendedRead
+#endif
+#ifdef ROM_EMACPHYExtendedWrite
+#define MAP_EMACPHYExtendedWrite                                              \
+        ROM_EMACPHYExtendedWrite
+#else
+#define MAP_EMACPHYExtendedWrite                                              \
+        EMACPHYExtendedWrite
+#endif
+#ifdef ROM_EMACPowerManagementControlGet
+#define MAP_EMACPowerManagementControlGet                                     \
+        ROM_EMACPowerManagementControlGet
+#else
+#define MAP_EMACPowerManagementControlGet                                     \
+        EMACPowerManagementControlGet
+#endif
+#ifdef ROM_EMACPowerManagementControlSet
+#define MAP_EMACPowerManagementControlSet                                     \
+        ROM_EMACPowerManagementControlSet
+#else
+#define MAP_EMACPowerManagementControlSet                                     \
+        EMACPowerManagementControlSet
+#endif
+#ifdef ROM_EMACPowerManagementStatusGet
+#define MAP_EMACPowerManagementStatusGet                                      \
+        ROM_EMACPowerManagementStatusGet
+#else
+#define MAP_EMACPowerManagementStatusGet                                      \
+        EMACPowerManagementStatusGet
+#endif
+#ifdef ROM_EMACRemoteWakeUpFrameFilterGet
+#define MAP_EMACRemoteWakeUpFrameFilterGet                                    \
+        ROM_EMACRemoteWakeUpFrameFilterGet
+#else
+#define MAP_EMACRemoteWakeUpFrameFilterGet                                    \
+        EMACRemoteWakeUpFrameFilterGet
+#endif
+#ifdef ROM_EMACRemoteWakeUpFrameFilterSet
+#define MAP_EMACRemoteWakeUpFrameFilterSet                                    \
+        ROM_EMACRemoteWakeUpFrameFilterSet
+#else
+#define MAP_EMACRemoteWakeUpFrameFilterSet                                    \
+        EMACRemoteWakeUpFrameFilterSet
+#endif
+#ifdef ROM_EMACTimestampAddendSet
+#define MAP_EMACTimestampAddendSet                                            \
+        ROM_EMACTimestampAddendSet
+#else
+#define MAP_EMACTimestampAddendSet                                            \
+        EMACTimestampAddendSet
+#endif
+#ifdef ROM_EMACTimestampConfigGet
+#define MAP_EMACTimestampConfigGet                                            \
+        ROM_EMACTimestampConfigGet
+#else
+#define MAP_EMACTimestampConfigGet                                            \
+        EMACTimestampConfigGet
+#endif
+#ifdef ROM_EMACTimestampConfigSet
+#define MAP_EMACTimestampConfigSet                                            \
+        ROM_EMACTimestampConfigSet
+#else
+#define MAP_EMACTimestampConfigSet                                            \
+        EMACTimestampConfigSet
+#endif
+#ifdef ROM_EMACTimestampDisable
+#define MAP_EMACTimestampDisable                                              \
+        ROM_EMACTimestampDisable
+#else
+#define MAP_EMACTimestampDisable                                              \
+        EMACTimestampDisable
+#endif
+#ifdef ROM_EMACTimestampEnable
+#define MAP_EMACTimestampEnable                                               \
+        ROM_EMACTimestampEnable
+#else
+#define MAP_EMACTimestampEnable                                               \
+        EMACTimestampEnable
+#endif
+#ifdef ROM_EMACTimestampIntStatus
+#define MAP_EMACTimestampIntStatus                                            \
+        ROM_EMACTimestampIntStatus
+#else
+#define MAP_EMACTimestampIntStatus                                            \
+        EMACTimestampIntStatus
+#endif
+#ifdef ROM_EMACTimestampPPSCommand
+#define MAP_EMACTimestampPPSCommand                                           \
+        ROM_EMACTimestampPPSCommand
+#else
+#define MAP_EMACTimestampPPSCommand                                           \
+        EMACTimestampPPSCommand
+#endif
+#ifdef ROM_EMACTimestampPPSCommandModeSet
+#define MAP_EMACTimestampPPSCommandModeSet                                    \
+        ROM_EMACTimestampPPSCommandModeSet
+#else
+#define MAP_EMACTimestampPPSCommandModeSet                                    \
+        EMACTimestampPPSCommandModeSet
+#endif
+#ifdef ROM_EMACTimestampPPSPeriodSet
+#define MAP_EMACTimestampPPSPeriodSet                                         \
+        ROM_EMACTimestampPPSPeriodSet
+#else
+#define MAP_EMACTimestampPPSPeriodSet                                         \
+        EMACTimestampPPSPeriodSet
+#endif
+#ifdef ROM_EMACTimestampPPSSimpleModeSet
+#define MAP_EMACTimestampPPSSimpleModeSet                                     \
+        ROM_EMACTimestampPPSSimpleModeSet
+#else
+#define MAP_EMACTimestampPPSSimpleModeSet                                     \
+        EMACTimestampPPSSimpleModeSet
+#endif
+#ifdef ROM_EMACTimestampSysTimeGet
+#define MAP_EMACTimestampSysTimeGet                                           \
+        ROM_EMACTimestampSysTimeGet
+#else
+#define MAP_EMACTimestampSysTimeGet                                           \
+        EMACTimestampSysTimeGet
+#endif
+#ifdef ROM_EMACTimestampSysTimeSet
+#define MAP_EMACTimestampSysTimeSet                                           \
+        ROM_EMACTimestampSysTimeSet
+#else
+#define MAP_EMACTimestampSysTimeSet                                           \
+        EMACTimestampSysTimeSet
+#endif
+#ifdef ROM_EMACTimestampSysTimeUpdate
+#define MAP_EMACTimestampSysTimeUpdate                                        \
+        ROM_EMACTimestampSysTimeUpdate
+#else
+#define MAP_EMACTimestampSysTimeUpdate                                        \
+        EMACTimestampSysTimeUpdate
+#endif
+#ifdef ROM_EMACTimestampTargetIntDisable
+#define MAP_EMACTimestampTargetIntDisable                                     \
+        ROM_EMACTimestampTargetIntDisable
+#else
+#define MAP_EMACTimestampTargetIntDisable                                     \
+        EMACTimestampTargetIntDisable
+#endif
+#ifdef ROM_EMACTimestampTargetIntEnable
+#define MAP_EMACTimestampTargetIntEnable                                      \
+        ROM_EMACTimestampTargetIntEnable
+#else
+#define MAP_EMACTimestampTargetIntEnable                                      \
+        EMACTimestampTargetIntEnable
+#endif
+#ifdef ROM_EMACTimestampTargetSet
+#define MAP_EMACTimestampTargetSet                                            \
+        ROM_EMACTimestampTargetSet
+#else
+#define MAP_EMACTimestampTargetSet                                            \
+        EMACTimestampTargetSet
+#endif
+#ifdef ROM_EMACVLANHashFilterBitCalculate
+#define MAP_EMACVLANHashFilterBitCalculate                                    \
+        ROM_EMACVLANHashFilterBitCalculate
+#else
+#define MAP_EMACVLANHashFilterBitCalculate                                    \
+        EMACVLANHashFilterBitCalculate
+#endif
+#ifdef ROM_EMACVLANHashFilterGet
+#define MAP_EMACVLANHashFilterGet                                             \
+        ROM_EMACVLANHashFilterGet
+#else
+#define MAP_EMACVLANHashFilterGet                                             \
+        EMACVLANHashFilterGet
+#endif
+#ifdef ROM_EMACVLANHashFilterSet
+#define MAP_EMACVLANHashFilterSet                                             \
+        ROM_EMACVLANHashFilterSet
+#else
+#define MAP_EMACVLANHashFilterSet                                             \
+        EMACVLANHashFilterSet
+#endif
+#ifdef ROM_EMACVLANRxConfigGet
+#define MAP_EMACVLANRxConfigGet                                               \
+        ROM_EMACVLANRxConfigGet
+#else
+#define MAP_EMACVLANRxConfigGet                                               \
+        EMACVLANRxConfigGet
+#endif
+#ifdef ROM_EMACVLANRxConfigSet
+#define MAP_EMACVLANRxConfigSet                                               \
+        ROM_EMACVLANRxConfigSet
+#else
+#define MAP_EMACVLANRxConfigSet                                               \
+        EMACVLANRxConfigSet
+#endif
+#ifdef ROM_EMACVLANTxConfigGet
+#define MAP_EMACVLANTxConfigGet                                               \
+        ROM_EMACVLANTxConfigGet
+#else
+#define MAP_EMACVLANTxConfigGet                                               \
+        EMACVLANTxConfigGet
+#endif
+#ifdef ROM_EMACVLANTxConfigSet
+#define MAP_EMACVLANTxConfigSet                                               \
+        ROM_EMACVLANTxConfigSet
+#else
+#define MAP_EMACVLANTxConfigSet                                               \
+        EMACVLANTxConfigSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Flash API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashProgram
+#define MAP_FlashProgram                                                      \
+        ROM_FlashProgram
+#else
+#define MAP_FlashProgram                                                      \
+        FlashProgram
+#endif
+#ifdef ROM_FlashErase
+#define MAP_FlashErase                                                        \
+        ROM_FlashErase
+#else
+#define MAP_FlashErase                                                        \
+        FlashErase
+#endif
+#ifdef ROM_FlashProtectGet
+#define MAP_FlashProtectGet                                                   \
+        ROM_FlashProtectGet
+#else
+#define MAP_FlashProtectGet                                                   \
+        FlashProtectGet
+#endif
+#ifdef ROM_FlashProtectSet
+#define MAP_FlashProtectSet                                                   \
+        ROM_FlashProtectSet
+#else
+#define MAP_FlashProtectSet                                                   \
+        FlashProtectSet
+#endif
+#ifdef ROM_FlashProtectSave
+#define MAP_FlashProtectSave                                                  \
+        ROM_FlashProtectSave
+#else
+#define MAP_FlashProtectSave                                                  \
+        FlashProtectSave
+#endif
+#ifdef ROM_FlashUserGet
+#define MAP_FlashUserGet                                                      \
+        ROM_FlashUserGet
+#else
+#define MAP_FlashUserGet                                                      \
+        FlashUserGet
+#endif
+#ifdef ROM_FlashUserSet
+#define MAP_FlashUserSet                                                      \
+        ROM_FlashUserSet
+#else
+#define MAP_FlashUserSet                                                      \
+        FlashUserSet
+#endif
+#ifdef ROM_FlashUserSave
+#define MAP_FlashUserSave                                                     \
+        ROM_FlashUserSave
+#else
+#define MAP_FlashUserSave                                                     \
+        FlashUserSave
+#endif
+#ifdef ROM_FlashIntEnable
+#define MAP_FlashIntEnable                                                    \
+        ROM_FlashIntEnable
+#else
+#define MAP_FlashIntEnable                                                    \
+        FlashIntEnable
+#endif
+#ifdef ROM_FlashIntDisable
+#define MAP_FlashIntDisable                                                   \
+        ROM_FlashIntDisable
+#else
+#define MAP_FlashIntDisable                                                   \
+        FlashIntDisable
+#endif
+#ifdef ROM_FlashIntStatus
+#define MAP_FlashIntStatus                                                    \
+        ROM_FlashIntStatus
+#else
+#define MAP_FlashIntStatus                                                    \
+        FlashIntStatus
+#endif
+#ifdef ROM_FlashIntClear
+#define MAP_FlashIntClear                                                     \
+        ROM_FlashIntClear
+#else
+#define MAP_FlashIntClear                                                     \
+        FlashIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the FPU API.
+//
+//*****************************************************************************
+#ifdef ROM_FPUEnable
+#define MAP_FPUEnable                                                         \
+        ROM_FPUEnable
+#else
+#define MAP_FPUEnable                                                         \
+        FPUEnable
+#endif
+#ifdef ROM_FPUDisable
+#define MAP_FPUDisable                                                        \
+        ROM_FPUDisable
+#else
+#define MAP_FPUDisable                                                        \
+        FPUDisable
+#endif
+#ifdef ROM_FPUFlushToZeroModeSet
+#define MAP_FPUFlushToZeroModeSet                                             \
+        ROM_FPUFlushToZeroModeSet
+#else
+#define MAP_FPUFlushToZeroModeSet                                             \
+        FPUFlushToZeroModeSet
+#endif
+#ifdef ROM_FPUHalfPrecisionModeSet
+#define MAP_FPUHalfPrecisionModeSet                                           \
+        ROM_FPUHalfPrecisionModeSet
+#else
+#define MAP_FPUHalfPrecisionModeSet                                           \
+        FPUHalfPrecisionModeSet
+#endif
+#ifdef ROM_FPULazyStackingEnable
+#define MAP_FPULazyStackingEnable                                             \
+        ROM_FPULazyStackingEnable
+#else
+#define MAP_FPULazyStackingEnable                                             \
+        FPULazyStackingEnable
+#endif
+#ifdef ROM_FPUNaNModeSet
+#define MAP_FPUNaNModeSet                                                     \
+        ROM_FPUNaNModeSet
+#else
+#define MAP_FPUNaNModeSet                                                     \
+        FPUNaNModeSet
+#endif
+#ifdef ROM_FPURoundingModeSet
+#define MAP_FPURoundingModeSet                                                \
+        ROM_FPURoundingModeSet
+#else
+#define MAP_FPURoundingModeSet                                                \
+        FPURoundingModeSet
+#endif
+#ifdef ROM_FPUStackingDisable
+#define MAP_FPUStackingDisable                                                \
+        ROM_FPUStackingDisable
+#else
+#define MAP_FPUStackingDisable                                                \
+        FPUStackingDisable
+#endif
+#ifdef ROM_FPUStackingEnable
+#define MAP_FPUStackingEnable                                                 \
+        ROM_FPUStackingEnable
+#else
+#define MAP_FPUStackingEnable                                                 \
+        FPUStackingEnable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIOPinWrite
+#define MAP_GPIOPinWrite                                                      \
+        ROM_GPIOPinWrite
+#else
+#define MAP_GPIOPinWrite                                                      \
+        GPIOPinWrite
+#endif
+#ifdef ROM_GPIODirModeSet
+#define MAP_GPIODirModeSet                                                    \
+        ROM_GPIODirModeSet
+#else
+#define MAP_GPIODirModeSet                                                    \
+        GPIODirModeSet
+#endif
+#ifdef ROM_GPIODirModeGet
+#define MAP_GPIODirModeGet                                                    \
+        ROM_GPIODirModeGet
+#else
+#define MAP_GPIODirModeGet                                                    \
+        GPIODirModeGet
+#endif
+#ifdef ROM_GPIOIntTypeSet
+#define MAP_GPIOIntTypeSet                                                    \
+        ROM_GPIOIntTypeSet
+#else
+#define MAP_GPIOIntTypeSet                                                    \
+        GPIOIntTypeSet
+#endif
+#ifdef ROM_GPIOIntTypeGet
+#define MAP_GPIOIntTypeGet                                                    \
+        ROM_GPIOIntTypeGet
+#else
+#define MAP_GPIOIntTypeGet                                                    \
+        GPIOIntTypeGet
+#endif
+#ifdef ROM_GPIOPadConfigSet
+#define MAP_GPIOPadConfigSet                                                  \
+        ROM_GPIOPadConfigSet
+#else
+#define MAP_GPIOPadConfigSet                                                  \
+        GPIOPadConfigSet
+#endif
+#ifdef ROM_GPIOPadConfigGet
+#define MAP_GPIOPadConfigGet                                                  \
+        ROM_GPIOPadConfigGet
+#else
+#define MAP_GPIOPadConfigGet                                                  \
+        GPIOPadConfigGet
+#endif
+#ifdef ROM_GPIOPinRead
+#define MAP_GPIOPinRead                                                       \
+        ROM_GPIOPinRead
+#else
+#define MAP_GPIOPinRead                                                       \
+        GPIOPinRead
+#endif
+#ifdef ROM_GPIOPinTypeCAN
+#define MAP_GPIOPinTypeCAN                                                    \
+        ROM_GPIOPinTypeCAN
+#else
+#define MAP_GPIOPinTypeCAN                                                    \
+        GPIOPinTypeCAN
+#endif
+#ifdef ROM_GPIOPinTypeComparator
+#define MAP_GPIOPinTypeComparator                                             \
+        ROM_GPIOPinTypeComparator
+#else
+#define MAP_GPIOPinTypeComparator                                             \
+        GPIOPinTypeComparator
+#endif
+#ifdef ROM_GPIOPinTypeGPIOInput
+#define MAP_GPIOPinTypeGPIOInput                                              \
+        ROM_GPIOPinTypeGPIOInput
+#else
+#define MAP_GPIOPinTypeGPIOInput                                              \
+        GPIOPinTypeGPIOInput
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutput
+#define MAP_GPIOPinTypeGPIOOutput                                             \
+        ROM_GPIOPinTypeGPIOOutput
+#else
+#define MAP_GPIOPinTypeGPIOOutput                                             \
+        GPIOPinTypeGPIOOutput
+#endif
+#ifdef ROM_GPIOPinTypeI2C
+#define MAP_GPIOPinTypeI2C                                                    \
+        ROM_GPIOPinTypeI2C
+#else
+#define MAP_GPIOPinTypeI2C                                                    \
+        GPIOPinTypeI2C
+#endif
+#ifdef ROM_GPIOPinTypePWM
+#define MAP_GPIOPinTypePWM                                                    \
+        ROM_GPIOPinTypePWM
+#else
+#define MAP_GPIOPinTypePWM                                                    \
+        GPIOPinTypePWM
+#endif
+#ifdef ROM_GPIOPinTypeQEI
+#define MAP_GPIOPinTypeQEI                                                    \
+        ROM_GPIOPinTypeQEI
+#else
+#define MAP_GPIOPinTypeQEI                                                    \
+        GPIOPinTypeQEI
+#endif
+#ifdef ROM_GPIOPinTypeSSI
+#define MAP_GPIOPinTypeSSI                                                    \
+        ROM_GPIOPinTypeSSI
+#else
+#define MAP_GPIOPinTypeSSI                                                    \
+        GPIOPinTypeSSI
+#endif
+#ifdef ROM_GPIOPinTypeTimer
+#define MAP_GPIOPinTypeTimer                                                  \
+        ROM_GPIOPinTypeTimer
+#else
+#define MAP_GPIOPinTypeTimer                                                  \
+        GPIOPinTypeTimer
+#endif
+#ifdef ROM_GPIOPinTypeUART
+#define MAP_GPIOPinTypeUART                                                   \
+        ROM_GPIOPinTypeUART
+#else
+#define MAP_GPIOPinTypeUART                                                   \
+        GPIOPinTypeUART
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutputOD
+#define MAP_GPIOPinTypeGPIOOutputOD                                           \
+        ROM_GPIOPinTypeGPIOOutputOD
+#else
+#define MAP_GPIOPinTypeGPIOOutputOD                                           \
+        GPIOPinTypeGPIOOutputOD
+#endif
+#ifdef ROM_GPIOPinTypeADC
+#define MAP_GPIOPinTypeADC                                                    \
+        ROM_GPIOPinTypeADC
+#else
+#define MAP_GPIOPinTypeADC                                                    \
+        GPIOPinTypeADC
+#endif
+#ifdef ROM_GPIOPinTypeUSBDigital
+#define MAP_GPIOPinTypeUSBDigital                                             \
+        ROM_GPIOPinTypeUSBDigital
+#else
+#define MAP_GPIOPinTypeUSBDigital                                             \
+        GPIOPinTypeUSBDigital
+#endif
+#ifdef ROM_GPIOPinConfigure
+#define MAP_GPIOPinConfigure                                                  \
+        ROM_GPIOPinConfigure
+#else
+#define MAP_GPIOPinConfigure                                                  \
+        GPIOPinConfigure
+#endif
+#ifdef ROM_GPIOPinTypeUSBAnalog
+#define MAP_GPIOPinTypeUSBAnalog                                              \
+        ROM_GPIOPinTypeUSBAnalog
+#else
+#define MAP_GPIOPinTypeUSBAnalog                                              \
+        GPIOPinTypeUSBAnalog
+#endif
+#ifdef ROM_GPIODMATriggerEnable
+#define MAP_GPIODMATriggerEnable                                              \
+        ROM_GPIODMATriggerEnable
+#else
+#define MAP_GPIODMATriggerEnable                                              \
+        GPIODMATriggerEnable
+#endif
+#ifdef ROM_GPIODMATriggerDisable
+#define MAP_GPIODMATriggerDisable                                             \
+        ROM_GPIODMATriggerDisable
+#else
+#define MAP_GPIODMATriggerDisable                                             \
+        GPIODMATriggerDisable
+#endif
+#ifdef ROM_GPIOADCTriggerEnable
+#define MAP_GPIOADCTriggerEnable                                              \
+        ROM_GPIOADCTriggerEnable
+#else
+#define MAP_GPIOADCTriggerEnable                                              \
+        GPIOADCTriggerEnable
+#endif
+#ifdef ROM_GPIOADCTriggerDisable
+#define MAP_GPIOADCTriggerDisable                                             \
+        ROM_GPIOADCTriggerDisable
+#else
+#define MAP_GPIOADCTriggerDisable                                             \
+        GPIOADCTriggerDisable
+#endif
+#ifdef ROM_GPIOPinTypeI2CSCL
+#define MAP_GPIOPinTypeI2CSCL                                                 \
+        ROM_GPIOPinTypeI2CSCL
+#else
+#define MAP_GPIOPinTypeI2CSCL                                                 \
+        GPIOPinTypeI2CSCL
+#endif
+#ifdef ROM_GPIOPinTypeOneWire
+#define MAP_GPIOPinTypeOneWire                                                \
+        ROM_GPIOPinTypeOneWire
+#else
+#define MAP_GPIOPinTypeOneWire                                                \
+        GPIOPinTypeOneWire
+#endif
+#ifdef ROM_GPIOPinTypeWakeHigh
+#define MAP_GPIOPinTypeWakeHigh                                               \
+        ROM_GPIOPinTypeWakeHigh
+#else
+#define MAP_GPIOPinTypeWakeHigh                                               \
+        GPIOPinTypeWakeHigh
+#endif
+#ifdef ROM_GPIOPinTypeWakeLow
+#define MAP_GPIOPinTypeWakeLow                                                \
+        ROM_GPIOPinTypeWakeLow
+#else
+#define MAP_GPIOPinTypeWakeLow                                                \
+        GPIOPinTypeWakeLow
+#endif
+#ifdef ROM_GPIOIntClear
+#define MAP_GPIOIntClear                                                      \
+        ROM_GPIOIntClear
+#else
+#define MAP_GPIOIntClear                                                      \
+        GPIOIntClear
+#endif
+#ifdef ROM_GPIOIntDisable
+#define MAP_GPIOIntDisable                                                    \
+        ROM_GPIOIntDisable
+#else
+#define MAP_GPIOIntDisable                                                    \
+        GPIOIntDisable
+#endif
+#ifdef ROM_GPIOIntEnable
+#define MAP_GPIOIntEnable                                                     \
+        ROM_GPIOIntEnable
+#else
+#define MAP_GPIOIntEnable                                                     \
+        GPIOIntEnable
+#endif
+#ifdef ROM_GPIOIntStatus
+#define MAP_GPIOIntStatus                                                     \
+        ROM_GPIOIntStatus
+#else
+#define MAP_GPIOIntStatus                                                     \
+        GPIOIntStatus
+#endif
+#ifdef ROM_GPIOPinWakeStatus
+#define MAP_GPIOPinWakeStatus                                                 \
+        ROM_GPIOPinWakeStatus
+#else
+#define MAP_GPIOPinWakeStatus                                                 \
+        GPIOPinWakeStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Hibernate API.
+//
+//*****************************************************************************
+#ifdef ROM_HibernateIntClear
+#define MAP_HibernateIntClear                                                 \
+        ROM_HibernateIntClear
+#else
+#define MAP_HibernateIntClear                                                 \
+        HibernateIntClear
+#endif
+#ifdef ROM_HibernateEnableExpClk
+#define MAP_HibernateEnableExpClk                                             \
+        ROM_HibernateEnableExpClk
+#else
+#define MAP_HibernateEnableExpClk                                             \
+        HibernateEnableExpClk
+#endif
+#ifdef ROM_HibernateDisable
+#define MAP_HibernateDisable                                                  \
+        ROM_HibernateDisable
+#else
+#define MAP_HibernateDisable                                                  \
+        HibernateDisable
+#endif
+#ifdef ROM_HibernateRTCEnable
+#define MAP_HibernateRTCEnable                                                \
+        ROM_HibernateRTCEnable
+#else
+#define MAP_HibernateRTCEnable                                                \
+        HibernateRTCEnable
+#endif
+#ifdef ROM_HibernateRTCDisable
+#define MAP_HibernateRTCDisable                                               \
+        ROM_HibernateRTCDisable
+#else
+#define MAP_HibernateRTCDisable                                               \
+        HibernateRTCDisable
+#endif
+#ifdef ROM_HibernateWakeSet
+#define MAP_HibernateWakeSet                                                  \
+        ROM_HibernateWakeSet
+#else
+#define MAP_HibernateWakeSet                                                  \
+        HibernateWakeSet
+#endif
+#ifdef ROM_HibernateWakeGet
+#define MAP_HibernateWakeGet                                                  \
+        ROM_HibernateWakeGet
+#else
+#define MAP_HibernateWakeGet                                                  \
+        HibernateWakeGet
+#endif
+#ifdef ROM_HibernateLowBatSet
+#define MAP_HibernateLowBatSet                                                \
+        ROM_HibernateLowBatSet
+#else
+#define MAP_HibernateLowBatSet                                                \
+        HibernateLowBatSet
+#endif
+#ifdef ROM_HibernateLowBatGet
+#define MAP_HibernateLowBatGet                                                \
+        ROM_HibernateLowBatGet
+#else
+#define MAP_HibernateLowBatGet                                                \
+        HibernateLowBatGet
+#endif
+#ifdef ROM_HibernateRTCSet
+#define MAP_HibernateRTCSet                                                   \
+        ROM_HibernateRTCSet
+#else
+#define MAP_HibernateRTCSet                                                   \
+        HibernateRTCSet
+#endif
+#ifdef ROM_HibernateRTCGet
+#define MAP_HibernateRTCGet                                                   \
+        ROM_HibernateRTCGet
+#else
+#define MAP_HibernateRTCGet                                                   \
+        HibernateRTCGet
+#endif
+#ifdef ROM_HibernateRTCTrimSet
+#define MAP_HibernateRTCTrimSet                                               \
+        ROM_HibernateRTCTrimSet
+#else
+#define MAP_HibernateRTCTrimSet                                               \
+        HibernateRTCTrimSet
+#endif
+#ifdef ROM_HibernateRTCTrimGet
+#define MAP_HibernateRTCTrimGet                                               \
+        ROM_HibernateRTCTrimGet
+#else
+#define MAP_HibernateRTCTrimGet                                               \
+        HibernateRTCTrimGet
+#endif
+#ifdef ROM_HibernateDataSet
+#define MAP_HibernateDataSet                                                  \
+        ROM_HibernateDataSet
+#else
+#define MAP_HibernateDataSet                                                  \
+        HibernateDataSet
+#endif
+#ifdef ROM_HibernateDataGet
+#define MAP_HibernateDataGet                                                  \
+        ROM_HibernateDataGet
+#else
+#define MAP_HibernateDataGet                                                  \
+        HibernateDataGet
+#endif
+#ifdef ROM_HibernateRequest
+#define MAP_HibernateRequest                                                  \
+        ROM_HibernateRequest
+#else
+#define MAP_HibernateRequest                                                  \
+        HibernateRequest
+#endif
+#ifdef ROM_HibernateIntEnable
+#define MAP_HibernateIntEnable                                                \
+        ROM_HibernateIntEnable
+#else
+#define MAP_HibernateIntEnable                                                \
+        HibernateIntEnable
+#endif
+#ifdef ROM_HibernateIntDisable
+#define MAP_HibernateIntDisable                                               \
+        ROM_HibernateIntDisable
+#else
+#define MAP_HibernateIntDisable                                               \
+        HibernateIntDisable
+#endif
+#ifdef ROM_HibernateIntStatus
+#define MAP_HibernateIntStatus                                                \
+        ROM_HibernateIntStatus
+#else
+#define MAP_HibernateIntStatus                                                \
+        HibernateIntStatus
+#endif
+#ifdef ROM_HibernateIsActive
+#define MAP_HibernateIsActive                                                 \
+        ROM_HibernateIsActive
+#else
+#define MAP_HibernateIsActive                                                 \
+        HibernateIsActive
+#endif
+#ifdef ROM_HibernateRTCSSGet
+#define MAP_HibernateRTCSSGet                                                 \
+        ROM_HibernateRTCSSGet
+#else
+#define MAP_HibernateRTCSSGet                                                 \
+        HibernateRTCSSGet
+#endif
+#ifdef ROM_HibernateClockConfig
+#define MAP_HibernateClockConfig                                              \
+        ROM_HibernateClockConfig
+#else
+#define MAP_HibernateClockConfig                                              \
+        HibernateClockConfig
+#endif
+#ifdef ROM_HibernateBatCheckStart
+#define MAP_HibernateBatCheckStart                                            \
+        ROM_HibernateBatCheckStart
+#else
+#define MAP_HibernateBatCheckStart                                            \
+        HibernateBatCheckStart
+#endif
+#ifdef ROM_HibernateBatCheckDone
+#define MAP_HibernateBatCheckDone                                             \
+        ROM_HibernateBatCheckDone
+#else
+#define MAP_HibernateBatCheckDone                                             \
+        HibernateBatCheckDone
+#endif
+#ifdef ROM_HibernateGPIORetentionEnable
+#define MAP_HibernateGPIORetentionEnable                                      \
+        ROM_HibernateGPIORetentionEnable
+#else
+#define MAP_HibernateGPIORetentionEnable                                      \
+        HibernateGPIORetentionEnable
+#endif
+#ifdef ROM_HibernateGPIORetentionDisable
+#define MAP_HibernateGPIORetentionDisable                                     \
+        ROM_HibernateGPIORetentionDisable
+#else
+#define MAP_HibernateGPIORetentionDisable                                     \
+        HibernateGPIORetentionDisable
+#endif
+#ifdef ROM_HibernateGPIORetentionGet
+#define MAP_HibernateGPIORetentionGet                                         \
+        ROM_HibernateGPIORetentionGet
+#else
+#define MAP_HibernateGPIORetentionGet                                         \
+        HibernateGPIORetentionGet
+#endif
+#ifdef ROM_HibernateCounterMode
+#define MAP_HibernateCounterMode                                              \
+        ROM_HibernateCounterMode
+#else
+#define MAP_HibernateCounterMode                                              \
+        HibernateCounterMode
+#endif
+#ifdef ROM_HibernateCalendarSet
+#define MAP_HibernateCalendarSet                                              \
+        ROM_HibernateCalendarSet
+#else
+#define MAP_HibernateCalendarSet                                              \
+        HibernateCalendarSet
+#endif
+#ifdef ROM_HibernateCalendarGet
+#define MAP_HibernateCalendarGet                                              \
+        ROM_HibernateCalendarGet
+#else
+#define MAP_HibernateCalendarGet                                              \
+        HibernateCalendarGet
+#endif
+#ifdef ROM_HibernateCalendarMatchSet
+#define MAP_HibernateCalendarMatchSet                                         \
+        ROM_HibernateCalendarMatchSet
+#else
+#define MAP_HibernateCalendarMatchSet                                         \
+        HibernateCalendarMatchSet
+#endif
+#ifdef ROM_HibernateCalendarMatchGet
+#define MAP_HibernateCalendarMatchGet                                         \
+        ROM_HibernateCalendarMatchGet
+#else
+#define MAP_HibernateCalendarMatchGet                                         \
+        HibernateCalendarMatchGet
+#endif
+#ifdef ROM_HibernateTamperDisable
+#define MAP_HibernateTamperDisable                                            \
+        ROM_HibernateTamperDisable
+#else
+#define MAP_HibernateTamperDisable                                            \
+        HibernateTamperDisable
+#endif
+#ifdef ROM_HibernateTamperEnable
+#define MAP_HibernateTamperEnable                                             \
+        ROM_HibernateTamperEnable
+#else
+#define MAP_HibernateTamperEnable                                             \
+        HibernateTamperEnable
+#endif
+#ifdef ROM_HibernateTamperEventsClear
+#define MAP_HibernateTamperEventsClear                                        \
+        ROM_HibernateTamperEventsClear
+#else
+#define MAP_HibernateTamperEventsClear                                        \
+        HibernateTamperEventsClear
+#endif
+#ifdef ROM_HibernateTamperEventsConfig
+#define MAP_HibernateTamperEventsConfig                                       \
+        ROM_HibernateTamperEventsConfig
+#else
+#define MAP_HibernateTamperEventsConfig                                       \
+        HibernateTamperEventsConfig
+#endif
+#ifdef ROM_HibernateTamperEventsGet
+#define MAP_HibernateTamperEventsGet                                          \
+        ROM_HibernateTamperEventsGet
+#else
+#define MAP_HibernateTamperEventsGet                                          \
+        HibernateTamperEventsGet
+#endif
+#ifdef ROM_HibernateTamperExtOscValid
+#define MAP_HibernateTamperExtOscValid                                        \
+        ROM_HibernateTamperExtOscValid
+#else
+#define MAP_HibernateTamperExtOscValid                                        \
+        HibernateTamperExtOscValid
+#endif
+#ifdef ROM_HibernateTamperExtOscRecover
+#define MAP_HibernateTamperExtOscRecover                                      \
+        ROM_HibernateTamperExtOscRecover
+#else
+#define MAP_HibernateTamperExtOscRecover                                      \
+        HibernateTamperExtOscRecover
+#endif
+#ifdef ROM_HibernateTamperIODisable
+#define MAP_HibernateTamperIODisable                                          \
+        ROM_HibernateTamperIODisable
+#else
+#define MAP_HibernateTamperIODisable                                          \
+        HibernateTamperIODisable
+#endif
+#ifdef ROM_HibernateTamperIOEnable
+#define MAP_HibernateTamperIOEnable                                           \
+        ROM_HibernateTamperIOEnable
+#else
+#define MAP_HibernateTamperIOEnable                                           \
+        HibernateTamperIOEnable
+#endif
+#ifdef ROM_HibernateTamperStatusGet
+#define MAP_HibernateTamperStatusGet                                          \
+        ROM_HibernateTamperStatusGet
+#else
+#define MAP_HibernateTamperStatusGet                                          \
+        HibernateTamperStatusGet
+#endif
+#ifdef ROM_HibernateRTCMatchGet
+#define MAP_HibernateRTCMatchGet                                              \
+        ROM_HibernateRTCMatchGet
+#else
+#define MAP_HibernateRTCMatchGet                                              \
+        HibernateRTCMatchGet
+#endif
+#ifdef ROM_HibernateRTCMatchSet
+#define MAP_HibernateRTCMatchSet                                              \
+        ROM_HibernateRTCMatchSet
+#else
+#define MAP_HibernateRTCMatchSet                                              \
+        HibernateRTCMatchSet
+#endif
+#ifdef ROM_HibernateRTCSSMatchGet
+#define MAP_HibernateRTCSSMatchGet                                            \
+        ROM_HibernateRTCSSMatchGet
+#else
+#define MAP_HibernateRTCSSMatchGet                                            \
+        HibernateRTCSSMatchGet
+#endif
+#ifdef ROM_HibernateRTCSSMatchSet
+#define MAP_HibernateRTCSSMatchSet                                            \
+        ROM_HibernateRTCSSMatchSet
+#else
+#define MAP_HibernateRTCSSMatchSet                                            \
+        HibernateRTCSSMatchSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2CMasterDataPut
+#define MAP_I2CMasterDataPut                                                  \
+        ROM_I2CMasterDataPut
+#else
+#define MAP_I2CMasterDataPut                                                  \
+        I2CMasterDataPut
+#endif
+#ifdef ROM_I2CMasterInitExpClk
+#define MAP_I2CMasterInitExpClk                                               \
+        ROM_I2CMasterInitExpClk
+#else
+#define MAP_I2CMasterInitExpClk                                               \
+        I2CMasterInitExpClk
+#endif
+#ifdef ROM_I2CSlaveInit
+#define MAP_I2CSlaveInit                                                      \
+        ROM_I2CSlaveInit
+#else
+#define MAP_I2CSlaveInit                                                      \
+        I2CSlaveInit
+#endif
+#ifdef ROM_I2CMasterEnable
+#define MAP_I2CMasterEnable                                                   \
+        ROM_I2CMasterEnable
+#else
+#define MAP_I2CMasterEnable                                                   \
+        I2CMasterEnable
+#endif
+#ifdef ROM_I2CSlaveEnable
+#define MAP_I2CSlaveEnable                                                    \
+        ROM_I2CSlaveEnable
+#else
+#define MAP_I2CSlaveEnable                                                    \
+        I2CSlaveEnable
+#endif
+#ifdef ROM_I2CMasterDisable
+#define MAP_I2CMasterDisable                                                  \
+        ROM_I2CMasterDisable
+#else
+#define MAP_I2CMasterDisable                                                  \
+        I2CMasterDisable
+#endif
+#ifdef ROM_I2CSlaveDisable
+#define MAP_I2CSlaveDisable                                                   \
+        ROM_I2CSlaveDisable
+#else
+#define MAP_I2CSlaveDisable                                                   \
+        I2CSlaveDisable
+#endif
+#ifdef ROM_I2CMasterIntEnable
+#define MAP_I2CMasterIntEnable                                                \
+        ROM_I2CMasterIntEnable
+#else
+#define MAP_I2CMasterIntEnable                                                \
+        I2CMasterIntEnable
+#endif
+#ifdef ROM_I2CSlaveIntEnable
+#define MAP_I2CSlaveIntEnable                                                 \
+        ROM_I2CSlaveIntEnable
+#else
+#define MAP_I2CSlaveIntEnable                                                 \
+        I2CSlaveIntEnable
+#endif
+#ifdef ROM_I2CMasterIntDisable
+#define MAP_I2CMasterIntDisable                                               \
+        ROM_I2CMasterIntDisable
+#else
+#define MAP_I2CMasterIntDisable                                               \
+        I2CMasterIntDisable
+#endif
+#ifdef ROM_I2CSlaveIntDisable
+#define MAP_I2CSlaveIntDisable                                                \
+        ROM_I2CSlaveIntDisable
+#else
+#define MAP_I2CSlaveIntDisable                                                \
+        I2CSlaveIntDisable
+#endif
+#ifdef ROM_I2CMasterIntStatus
+#define MAP_I2CMasterIntStatus                                                \
+        ROM_I2CMasterIntStatus
+#else
+#define MAP_I2CMasterIntStatus                                                \
+        I2CMasterIntStatus
+#endif
+#ifdef ROM_I2CSlaveIntStatus
+#define MAP_I2CSlaveIntStatus                                                 \
+        ROM_I2CSlaveIntStatus
+#else
+#define MAP_I2CSlaveIntStatus                                                 \
+        I2CSlaveIntStatus
+#endif
+#ifdef ROM_I2CMasterIntClear
+#define MAP_I2CMasterIntClear                                                 \
+        ROM_I2CMasterIntClear
+#else
+#define MAP_I2CMasterIntClear                                                 \
+        I2CMasterIntClear
+#endif
+#ifdef ROM_I2CSlaveIntClear
+#define MAP_I2CSlaveIntClear                                                  \
+        ROM_I2CSlaveIntClear
+#else
+#define MAP_I2CSlaveIntClear                                                  \
+        I2CSlaveIntClear
+#endif
+#ifdef ROM_I2CMasterSlaveAddrSet
+#define MAP_I2CMasterSlaveAddrSet                                             \
+        ROM_I2CMasterSlaveAddrSet
+#else
+#define MAP_I2CMasterSlaveAddrSet                                             \
+        I2CMasterSlaveAddrSet
+#endif
+#ifdef ROM_I2CMasterBusy
+#define MAP_I2CMasterBusy                                                     \
+        ROM_I2CMasterBusy
+#else
+#define MAP_I2CMasterBusy                                                     \
+        I2CMasterBusy
+#endif
+#ifdef ROM_I2CMasterBusBusy
+#define MAP_I2CMasterBusBusy                                                  \
+        ROM_I2CMasterBusBusy
+#else
+#define MAP_I2CMasterBusBusy                                                  \
+        I2CMasterBusBusy
+#endif
+#ifdef ROM_I2CMasterControl
+#define MAP_I2CMasterControl                                                  \
+        ROM_I2CMasterControl
+#else
+#define MAP_I2CMasterControl                                                  \
+        I2CMasterControl
+#endif
+#ifdef ROM_I2CMasterErr
+#define MAP_I2CMasterErr                                                      \
+        ROM_I2CMasterErr
+#else
+#define MAP_I2CMasterErr                                                      \
+        I2CMasterErr
+#endif
+#ifdef ROM_I2CMasterDataGet
+#define MAP_I2CMasterDataGet                                                  \
+        ROM_I2CMasterDataGet
+#else
+#define MAP_I2CMasterDataGet                                                  \
+        I2CMasterDataGet
+#endif
+#ifdef ROM_I2CSlaveStatus
+#define MAP_I2CSlaveStatus                                                    \
+        ROM_I2CSlaveStatus
+#else
+#define MAP_I2CSlaveStatus                                                    \
+        I2CSlaveStatus
+#endif
+#ifdef ROM_I2CSlaveDataPut
+#define MAP_I2CSlaveDataPut                                                   \
+        ROM_I2CSlaveDataPut
+#else
+#define MAP_I2CSlaveDataPut                                                   \
+        I2CSlaveDataPut
+#endif
+#ifdef ROM_I2CSlaveDataGet
+#define MAP_I2CSlaveDataGet                                                   \
+        ROM_I2CSlaveDataGet
+#else
+#define MAP_I2CSlaveDataGet                                                   \
+        I2CSlaveDataGet
+#endif
+#ifdef ROM_I2CSlaveIntEnableEx
+#define MAP_I2CSlaveIntEnableEx                                               \
+        ROM_I2CSlaveIntEnableEx
+#else
+#define MAP_I2CSlaveIntEnableEx                                               \
+        I2CSlaveIntEnableEx
+#endif
+#ifdef ROM_I2CSlaveIntDisableEx
+#define MAP_I2CSlaveIntDisableEx                                              \
+        ROM_I2CSlaveIntDisableEx
+#else
+#define MAP_I2CSlaveIntDisableEx                                              \
+        I2CSlaveIntDisableEx
+#endif
+#ifdef ROM_I2CSlaveIntStatusEx
+#define MAP_I2CSlaveIntStatusEx                                               \
+        ROM_I2CSlaveIntStatusEx
+#else
+#define MAP_I2CSlaveIntStatusEx                                               \
+        I2CSlaveIntStatusEx
+#endif
+#ifdef ROM_I2CSlaveIntClearEx
+#define MAP_I2CSlaveIntClearEx                                                \
+        ROM_I2CSlaveIntClearEx
+#else
+#define MAP_I2CSlaveIntClearEx                                                \
+        I2CSlaveIntClearEx
+#endif
+#ifdef ROM_I2CMasterIntEnableEx
+#define MAP_I2CMasterIntEnableEx                                              \
+        ROM_I2CMasterIntEnableEx
+#else
+#define MAP_I2CMasterIntEnableEx                                              \
+        I2CMasterIntEnableEx
+#endif
+#ifdef ROM_I2CMasterIntDisableEx
+#define MAP_I2CMasterIntDisableEx                                             \
+        ROM_I2CMasterIntDisableEx
+#else
+#define MAP_I2CMasterIntDisableEx                                             \
+        I2CMasterIntDisableEx
+#endif
+#ifdef ROM_I2CMasterIntStatusEx
+#define MAP_I2CMasterIntStatusEx                                              \
+        ROM_I2CMasterIntStatusEx
+#else
+#define MAP_I2CMasterIntStatusEx                                              \
+        I2CMasterIntStatusEx
+#endif
+#ifdef ROM_I2CMasterIntClearEx
+#define MAP_I2CMasterIntClearEx                                               \
+        ROM_I2CMasterIntClearEx
+#else
+#define MAP_I2CMasterIntClearEx                                               \
+        I2CMasterIntClearEx
+#endif
+#ifdef ROM_I2CMasterTimeoutSet
+#define MAP_I2CMasterTimeoutSet                                               \
+        ROM_I2CMasterTimeoutSet
+#else
+#define MAP_I2CMasterTimeoutSet                                               \
+        I2CMasterTimeoutSet
+#endif
+#ifdef ROM_I2CSlaveACKOverride
+#define MAP_I2CSlaveACKOverride                                               \
+        ROM_I2CSlaveACKOverride
+#else
+#define MAP_I2CSlaveACKOverride                                               \
+        I2CSlaveACKOverride
+#endif
+#ifdef ROM_I2CSlaveACKValueSet
+#define MAP_I2CSlaveACKValueSet                                               \
+        ROM_I2CSlaveACKValueSet
+#else
+#define MAP_I2CSlaveACKValueSet                                               \
+        I2CSlaveACKValueSet
+#endif
+#ifdef ROM_I2CSlaveAddressSet
+#define MAP_I2CSlaveAddressSet                                                \
+        ROM_I2CSlaveAddressSet
+#else
+#define MAP_I2CSlaveAddressSet                                                \
+        I2CSlaveAddressSet
+#endif
+#ifdef ROM_I2CMasterLineStateGet
+#define MAP_I2CMasterLineStateGet                                             \
+        ROM_I2CMasterLineStateGet
+#else
+#define MAP_I2CMasterLineStateGet                                             \
+        I2CMasterLineStateGet
+#endif
+#ifdef ROM_I2CTxFIFOConfigSet
+#define MAP_I2CTxFIFOConfigSet                                                \
+        ROM_I2CTxFIFOConfigSet
+#else
+#define MAP_I2CTxFIFOConfigSet                                                \
+        I2CTxFIFOConfigSet
+#endif
+#ifdef ROM_I2CTxFIFOFlush
+#define MAP_I2CTxFIFOFlush                                                    \
+        ROM_I2CTxFIFOFlush
+#else
+#define MAP_I2CTxFIFOFlush                                                    \
+        I2CTxFIFOFlush
+#endif
+#ifdef ROM_I2CRxFIFOConfigSet
+#define MAP_I2CRxFIFOConfigSet                                                \
+        ROM_I2CRxFIFOConfigSet
+#else
+#define MAP_I2CRxFIFOConfigSet                                                \
+        I2CRxFIFOConfigSet
+#endif
+#ifdef ROM_I2CRxFIFOFlush
+#define MAP_I2CRxFIFOFlush                                                    \
+        ROM_I2CRxFIFOFlush
+#else
+#define MAP_I2CRxFIFOFlush                                                    \
+        I2CRxFIFOFlush
+#endif
+#ifdef ROM_I2CFIFOStatus
+#define MAP_I2CFIFOStatus                                                     \
+        ROM_I2CFIFOStatus
+#else
+#define MAP_I2CFIFOStatus                                                     \
+        I2CFIFOStatus
+#endif
+#ifdef ROM_I2CFIFODataPut
+#define MAP_I2CFIFODataPut                                                    \
+        ROM_I2CFIFODataPut
+#else
+#define MAP_I2CFIFODataPut                                                    \
+        I2CFIFODataPut
+#endif
+#ifdef ROM_I2CFIFODataPutNonBlocking
+#define MAP_I2CFIFODataPutNonBlocking                                         \
+        ROM_I2CFIFODataPutNonBlocking
+#else
+#define MAP_I2CFIFODataPutNonBlocking                                         \
+        I2CFIFODataPutNonBlocking
+#endif
+#ifdef ROM_I2CFIFODataGet
+#define MAP_I2CFIFODataGet                                                    \
+        ROM_I2CFIFODataGet
+#else
+#define MAP_I2CFIFODataGet                                                    \
+        I2CFIFODataGet
+#endif
+#ifdef ROM_I2CFIFODataGetNonBlocking
+#define MAP_I2CFIFODataGetNonBlocking                                         \
+        ROM_I2CFIFODataGetNonBlocking
+#else
+#define MAP_I2CFIFODataGetNonBlocking                                         \
+        I2CFIFODataGetNonBlocking
+#endif
+#ifdef ROM_I2CMasterBurstLengthSet
+#define MAP_I2CMasterBurstLengthSet                                           \
+        ROM_I2CMasterBurstLengthSet
+#else
+#define MAP_I2CMasterBurstLengthSet                                           \
+        I2CMasterBurstLengthSet
+#endif
+#ifdef ROM_I2CMasterBurstCountGet
+#define MAP_I2CMasterBurstCountGet                                            \
+        ROM_I2CMasterBurstCountGet
+#else
+#define MAP_I2CMasterBurstCountGet                                            \
+        I2CMasterBurstCountGet
+#endif
+#ifdef ROM_I2CSlaveFIFODisable
+#define MAP_I2CSlaveFIFODisable                                               \
+        ROM_I2CSlaveFIFODisable
+#else
+#define MAP_I2CSlaveFIFODisable                                               \
+        I2CSlaveFIFODisable
+#endif
+#ifdef ROM_I2CSlaveFIFOEnable
+#define MAP_I2CSlaveFIFOEnable                                                \
+        ROM_I2CSlaveFIFOEnable
+#else
+#define MAP_I2CSlaveFIFOEnable                                                \
+        I2CSlaveFIFOEnable
+#endif
+#ifdef ROM_I2CMasterGlitchFilterConfigSet
+#define MAP_I2CMasterGlitchFilterConfigSet                                    \
+        ROM_I2CMasterGlitchFilterConfigSet
+#else
+#define MAP_I2CMasterGlitchFilterConfigSet                                    \
+        I2CMasterGlitchFilterConfigSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_IntEnable
+#define MAP_IntEnable                                                         \
+        ROM_IntEnable
+#else
+#define MAP_IntEnable                                                         \
+        IntEnable
+#endif
+#ifdef ROM_IntMasterEnable
+#define MAP_IntMasterEnable                                                   \
+        ROM_IntMasterEnable
+#else
+#define MAP_IntMasterEnable                                                   \
+        IntMasterEnable
+#endif
+#ifdef ROM_IntMasterDisable
+#define MAP_IntMasterDisable                                                  \
+        ROM_IntMasterDisable
+#else
+#define MAP_IntMasterDisable                                                  \
+        IntMasterDisable
+#endif
+#ifdef ROM_IntDisable
+#define MAP_IntDisable                                                        \
+        ROM_IntDisable
+#else
+#define MAP_IntDisable                                                        \
+        IntDisable
+#endif
+#ifdef ROM_IntPriorityGroupingSet
+#define MAP_IntPriorityGroupingSet                                            \
+        ROM_IntPriorityGroupingSet
+#else
+#define MAP_IntPriorityGroupingSet                                            \
+        IntPriorityGroupingSet
+#endif
+#ifdef ROM_IntPriorityGroupingGet
+#define MAP_IntPriorityGroupingGet                                            \
+        ROM_IntPriorityGroupingGet
+#else
+#define MAP_IntPriorityGroupingGet                                            \
+        IntPriorityGroupingGet
+#endif
+#ifdef ROM_IntPrioritySet
+#define MAP_IntPrioritySet                                                    \
+        ROM_IntPrioritySet
+#else
+#define MAP_IntPrioritySet                                                    \
+        IntPrioritySet
+#endif
+#ifdef ROM_IntPriorityGet
+#define MAP_IntPriorityGet                                                    \
+        ROM_IntPriorityGet
+#else
+#define MAP_IntPriorityGet                                                    \
+        IntPriorityGet
+#endif
+#ifdef ROM_IntPendSet
+#define MAP_IntPendSet                                                        \
+        ROM_IntPendSet
+#else
+#define MAP_IntPendSet                                                        \
+        IntPendSet
+#endif
+#ifdef ROM_IntPendClear
+#define MAP_IntPendClear                                                      \
+        ROM_IntPendClear
+#else
+#define MAP_IntPendClear                                                      \
+        IntPendClear
+#endif
+#ifdef ROM_IntPriorityMaskSet
+#define MAP_IntPriorityMaskSet                                                \
+        ROM_IntPriorityMaskSet
+#else
+#define MAP_IntPriorityMaskSet                                                \
+        IntPriorityMaskSet
+#endif
+#ifdef ROM_IntPriorityMaskGet
+#define MAP_IntPriorityMaskGet                                                \
+        ROM_IntPriorityMaskGet
+#else
+#define MAP_IntPriorityMaskGet                                                \
+        IntPriorityMaskGet
+#endif
+#ifdef ROM_IntIsEnabled
+#define MAP_IntIsEnabled                                                      \
+        ROM_IntIsEnabled
+#else
+#define MAP_IntIsEnabled                                                      \
+        IntIsEnabled
+#endif
+#ifdef ROM_IntTrigger
+#define MAP_IntTrigger                                                        \
+        ROM_IntTrigger
+#else
+#define MAP_IntTrigger                                                        \
+        IntTrigger
+#endif
+
+//*****************************************************************************
+//
+// Macros for the LCD API.
+//
+//*****************************************************************************
+#ifdef ROM_LCDIntStatus
+#define MAP_LCDIntStatus                                                      \
+        ROM_LCDIntStatus
+#else
+#define MAP_LCDIntStatus                                                      \
+        LCDIntStatus
+#endif
+#ifdef ROM_LCDClockReset
+#define MAP_LCDClockReset                                                     \
+        ROM_LCDClockReset
+#else
+#define MAP_LCDClockReset                                                     \
+        LCDClockReset
+#endif
+#ifdef ROM_LCDDMAConfigSet
+#define MAP_LCDDMAConfigSet                                                   \
+        ROM_LCDDMAConfigSet
+#else
+#define MAP_LCDDMAConfigSet                                                   \
+        LCDDMAConfigSet
+#endif
+#ifdef ROM_LCDIDDCommandWrite
+#define MAP_LCDIDDCommandWrite                                                \
+        ROM_LCDIDDCommandWrite
+#else
+#define MAP_LCDIDDCommandWrite                                                \
+        LCDIDDCommandWrite
+#endif
+#ifdef ROM_LCDIDDConfigSet
+#define MAP_LCDIDDConfigSet                                                   \
+        ROM_LCDIDDConfigSet
+#else
+#define MAP_LCDIDDConfigSet                                                   \
+        LCDIDDConfigSet
+#endif
+#ifdef ROM_LCDIDDDataRead
+#define MAP_LCDIDDDataRead                                                    \
+        ROM_LCDIDDDataRead
+#else
+#define MAP_LCDIDDDataRead                                                    \
+        LCDIDDDataRead
+#endif
+#ifdef ROM_LCDIDDDataWrite
+#define MAP_LCDIDDDataWrite                                                   \
+        ROM_LCDIDDDataWrite
+#else
+#define MAP_LCDIDDDataWrite                                                   \
+        LCDIDDDataWrite
+#endif
+#ifdef ROM_LCDIDDDMADisable
+#define MAP_LCDIDDDMADisable                                                  \
+        ROM_LCDIDDDMADisable
+#else
+#define MAP_LCDIDDDMADisable                                                  \
+        LCDIDDDMADisable
+#endif
+#ifdef ROM_LCDIDDDMAWrite
+#define MAP_LCDIDDDMAWrite                                                    \
+        ROM_LCDIDDDMAWrite
+#else
+#define MAP_LCDIDDDMAWrite                                                    \
+        LCDIDDDMAWrite
+#endif
+#ifdef ROM_LCDIDDIndexedRead
+#define MAP_LCDIDDIndexedRead                                                 \
+        ROM_LCDIDDIndexedRead
+#else
+#define MAP_LCDIDDIndexedRead                                                 \
+        LCDIDDIndexedRead
+#endif
+#ifdef ROM_LCDIDDIndexedWrite
+#define MAP_LCDIDDIndexedWrite                                                \
+        ROM_LCDIDDIndexedWrite
+#else
+#define MAP_LCDIDDIndexedWrite                                                \
+        LCDIDDIndexedWrite
+#endif
+#ifdef ROM_LCDIDDStatusRead
+#define MAP_LCDIDDStatusRead                                                  \
+        ROM_LCDIDDStatusRead
+#else
+#define MAP_LCDIDDStatusRead                                                  \
+        LCDIDDStatusRead
+#endif
+#ifdef ROM_LCDIDDTimingSet
+#define MAP_LCDIDDTimingSet                                                   \
+        ROM_LCDIDDTimingSet
+#else
+#define MAP_LCDIDDTimingSet                                                   \
+        LCDIDDTimingSet
+#endif
+#ifdef ROM_LCDIntClear
+#define MAP_LCDIntClear                                                       \
+        ROM_LCDIntClear
+#else
+#define MAP_LCDIntClear                                                       \
+        LCDIntClear
+#endif
+#ifdef ROM_LCDIntDisable
+#define MAP_LCDIntDisable                                                     \
+        ROM_LCDIntDisable
+#else
+#define MAP_LCDIntDisable                                                     \
+        LCDIntDisable
+#endif
+#ifdef ROM_LCDIntEnable
+#define MAP_LCDIntEnable                                                      \
+        ROM_LCDIntEnable
+#else
+#define MAP_LCDIntEnable                                                      \
+        LCDIntEnable
+#endif
+#ifdef ROM_LCDModeSet
+#define MAP_LCDModeSet                                                        \
+        ROM_LCDModeSet
+#else
+#define MAP_LCDModeSet                                                        \
+        LCDModeSet
+#endif
+#ifdef ROM_LCDRasterACBiasIntCountSet
+#define MAP_LCDRasterACBiasIntCountSet                                        \
+        ROM_LCDRasterACBiasIntCountSet
+#else
+#define MAP_LCDRasterACBiasIntCountSet                                        \
+        LCDRasterACBiasIntCountSet
+#endif
+#ifdef ROM_LCDRasterConfigSet
+#define MAP_LCDRasterConfigSet                                                \
+        ROM_LCDRasterConfigSet
+#else
+#define MAP_LCDRasterConfigSet                                                \
+        LCDRasterConfigSet
+#endif
+#ifdef ROM_LCDRasterDisable
+#define MAP_LCDRasterDisable                                                  \
+        ROM_LCDRasterDisable
+#else
+#define MAP_LCDRasterDisable                                                  \
+        LCDRasterDisable
+#endif
+#ifdef ROM_LCDRasterEnable
+#define MAP_LCDRasterEnable                                                   \
+        ROM_LCDRasterEnable
+#else
+#define MAP_LCDRasterEnable                                                   \
+        LCDRasterEnable
+#endif
+#ifdef ROM_LCDRasterFrameBufferSet
+#define MAP_LCDRasterFrameBufferSet                                           \
+        ROM_LCDRasterFrameBufferSet
+#else
+#define MAP_LCDRasterFrameBufferSet                                           \
+        LCDRasterFrameBufferSet
+#endif
+#ifdef ROM_LCDRasterPaletteSet
+#define MAP_LCDRasterPaletteSet                                               \
+        ROM_LCDRasterPaletteSet
+#else
+#define MAP_LCDRasterPaletteSet                                               \
+        LCDRasterPaletteSet
+#endif
+#ifdef ROM_LCDRasterSubPanelConfigSet
+#define MAP_LCDRasterSubPanelConfigSet                                        \
+        ROM_LCDRasterSubPanelConfigSet
+#else
+#define MAP_LCDRasterSubPanelConfigSet                                        \
+        LCDRasterSubPanelConfigSet
+#endif
+#ifdef ROM_LCDRasterSubPanelDisable
+#define MAP_LCDRasterSubPanelDisable                                          \
+        ROM_LCDRasterSubPanelDisable
+#else
+#define MAP_LCDRasterSubPanelDisable                                          \
+        LCDRasterSubPanelDisable
+#endif
+#ifdef ROM_LCDRasterSubPanelEnable
+#define MAP_LCDRasterSubPanelEnable                                           \
+        ROM_LCDRasterSubPanelEnable
+#else
+#define MAP_LCDRasterSubPanelEnable                                           \
+        LCDRasterSubPanelEnable
+#endif
+#ifdef ROM_LCDRasterTimingSet
+#define MAP_LCDRasterTimingSet                                                \
+        ROM_LCDRasterTimingSet
+#else
+#define MAP_LCDRasterTimingSet                                                \
+        LCDRasterTimingSet
+#endif
+#ifdef ROM_LCDRasterEnabled
+#define MAP_LCDRasterEnabled                                                  \
+        ROM_LCDRasterEnabled
+#else
+#define MAP_LCDRasterEnabled                                                  \
+        LCDRasterEnabled
+#endif
+
+//*****************************************************************************
+//
+// Macros for the MPU API.
+//
+//*****************************************************************************
+#ifdef ROM_MPUEnable
+#define MAP_MPUEnable                                                         \
+        ROM_MPUEnable
+#else
+#define MAP_MPUEnable                                                         \
+        MPUEnable
+#endif
+#ifdef ROM_MPUDisable
+#define MAP_MPUDisable                                                        \
+        ROM_MPUDisable
+#else
+#define MAP_MPUDisable                                                        \
+        MPUDisable
+#endif
+#ifdef ROM_MPURegionCountGet
+#define MAP_MPURegionCountGet                                                 \
+        ROM_MPURegionCountGet
+#else
+#define MAP_MPURegionCountGet                                                 \
+        MPURegionCountGet
+#endif
+#ifdef ROM_MPURegionEnable
+#define MAP_MPURegionEnable                                                   \
+        ROM_MPURegionEnable
+#else
+#define MAP_MPURegionEnable                                                   \
+        MPURegionEnable
+#endif
+#ifdef ROM_MPURegionDisable
+#define MAP_MPURegionDisable                                                  \
+        ROM_MPURegionDisable
+#else
+#define MAP_MPURegionDisable                                                  \
+        MPURegionDisable
+#endif
+#ifdef ROM_MPURegionSet
+#define MAP_MPURegionSet                                                      \
+        ROM_MPURegionSet
+#else
+#define MAP_MPURegionSet                                                      \
+        MPURegionSet
+#endif
+#ifdef ROM_MPURegionGet
+#define MAP_MPURegionGet                                                      \
+        ROM_MPURegionGet
+#else
+#define MAP_MPURegionGet                                                      \
+        MPURegionGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the OneWire API.
+//
+//*****************************************************************************
+#ifdef ROM_OneWireIntStatus
+#define MAP_OneWireIntStatus                                                  \
+        ROM_OneWireIntStatus
+#else
+#define MAP_OneWireIntStatus                                                  \
+        OneWireIntStatus
+#endif
+#ifdef ROM_OneWireBusReset
+#define MAP_OneWireBusReset                                                   \
+        ROM_OneWireBusReset
+#else
+#define MAP_OneWireBusReset                                                   \
+        OneWireBusReset
+#endif
+#ifdef ROM_OneWireBusStatus
+#define MAP_OneWireBusStatus                                                  \
+        ROM_OneWireBusStatus
+#else
+#define MAP_OneWireBusStatus                                                  \
+        OneWireBusStatus
+#endif
+#ifdef ROM_OneWireDataGet
+#define MAP_OneWireDataGet                                                    \
+        ROM_OneWireDataGet
+#else
+#define MAP_OneWireDataGet                                                    \
+        OneWireDataGet
+#endif
+#ifdef ROM_OneWireDataGetNonBlocking
+#define MAP_OneWireDataGetNonBlocking                                         \
+        ROM_OneWireDataGetNonBlocking
+#else
+#define MAP_OneWireDataGetNonBlocking                                         \
+        OneWireDataGetNonBlocking
+#endif
+#ifdef ROM_OneWireInit
+#define MAP_OneWireInit                                                       \
+        ROM_OneWireInit
+#else
+#define MAP_OneWireInit                                                       \
+        OneWireInit
+#endif
+#ifdef ROM_OneWireIntClear
+#define MAP_OneWireIntClear                                                   \
+        ROM_OneWireIntClear
+#else
+#define MAP_OneWireIntClear                                                   \
+        OneWireIntClear
+#endif
+#ifdef ROM_OneWireIntDisable
+#define MAP_OneWireIntDisable                                                 \
+        ROM_OneWireIntDisable
+#else
+#define MAP_OneWireIntDisable                                                 \
+        OneWireIntDisable
+#endif
+#ifdef ROM_OneWireIntEnable
+#define MAP_OneWireIntEnable                                                  \
+        ROM_OneWireIntEnable
+#else
+#define MAP_OneWireIntEnable                                                  \
+        OneWireIntEnable
+#endif
+#ifdef ROM_OneWireTransaction
+#define MAP_OneWireTransaction                                                \
+        ROM_OneWireTransaction
+#else
+#define MAP_OneWireTransaction                                                \
+        OneWireTransaction
+#endif
+#ifdef ROM_OneWireDMADisable
+#define MAP_OneWireDMADisable                                                 \
+        ROM_OneWireDMADisable
+#else
+#define MAP_OneWireDMADisable                                                 \
+        OneWireDMADisable
+#endif
+#ifdef ROM_OneWireDMAEnable
+#define MAP_OneWireDMAEnable                                                  \
+        ROM_OneWireDMAEnable
+#else
+#define MAP_OneWireDMAEnable                                                  \
+        OneWireDMAEnable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PWM API.
+//
+//*****************************************************************************
+#ifdef ROM_PWMPulseWidthSet
+#define MAP_PWMPulseWidthSet                                                  \
+        ROM_PWMPulseWidthSet
+#else
+#define MAP_PWMPulseWidthSet                                                  \
+        PWMPulseWidthSet
+#endif
+#ifdef ROM_PWMGenConfigure
+#define MAP_PWMGenConfigure                                                   \
+        ROM_PWMGenConfigure
+#else
+#define MAP_PWMGenConfigure                                                   \
+        PWMGenConfigure
+#endif
+#ifdef ROM_PWMGenPeriodSet
+#define MAP_PWMGenPeriodSet                                                   \
+        ROM_PWMGenPeriodSet
+#else
+#define MAP_PWMGenPeriodSet                                                   \
+        PWMGenPeriodSet
+#endif
+#ifdef ROM_PWMGenPeriodGet
+#define MAP_PWMGenPeriodGet                                                   \
+        ROM_PWMGenPeriodGet
+#else
+#define MAP_PWMGenPeriodGet                                                   \
+        PWMGenPeriodGet
+#endif
+#ifdef ROM_PWMGenEnable
+#define MAP_PWMGenEnable                                                      \
+        ROM_PWMGenEnable
+#else
+#define MAP_PWMGenEnable                                                      \
+        PWMGenEnable
+#endif
+#ifdef ROM_PWMGenDisable
+#define MAP_PWMGenDisable                                                     \
+        ROM_PWMGenDisable
+#else
+#define MAP_PWMGenDisable                                                     \
+        PWMGenDisable
+#endif
+#ifdef ROM_PWMPulseWidthGet
+#define MAP_PWMPulseWidthGet                                                  \
+        ROM_PWMPulseWidthGet
+#else
+#define MAP_PWMPulseWidthGet                                                  \
+        PWMPulseWidthGet
+#endif
+#ifdef ROM_PWMDeadBandEnable
+#define MAP_PWMDeadBandEnable                                                 \
+        ROM_PWMDeadBandEnable
+#else
+#define MAP_PWMDeadBandEnable                                                 \
+        PWMDeadBandEnable
+#endif
+#ifdef ROM_PWMDeadBandDisable
+#define MAP_PWMDeadBandDisable                                                \
+        ROM_PWMDeadBandDisable
+#else
+#define MAP_PWMDeadBandDisable                                                \
+        PWMDeadBandDisable
+#endif
+#ifdef ROM_PWMSyncUpdate
+#define MAP_PWMSyncUpdate                                                     \
+        ROM_PWMSyncUpdate
+#else
+#define MAP_PWMSyncUpdate                                                     \
+        PWMSyncUpdate
+#endif
+#ifdef ROM_PWMSyncTimeBase
+#define MAP_PWMSyncTimeBase                                                   \
+        ROM_PWMSyncTimeBase
+#else
+#define MAP_PWMSyncTimeBase                                                   \
+        PWMSyncTimeBase
+#endif
+#ifdef ROM_PWMOutputState
+#define MAP_PWMOutputState                                                    \
+        ROM_PWMOutputState
+#else
+#define MAP_PWMOutputState                                                    \
+        PWMOutputState
+#endif
+#ifdef ROM_PWMOutputInvert
+#define MAP_PWMOutputInvert                                                   \
+        ROM_PWMOutputInvert
+#else
+#define MAP_PWMOutputInvert                                                   \
+        PWMOutputInvert
+#endif
+#ifdef ROM_PWMOutputFault
+#define MAP_PWMOutputFault                                                    \
+        ROM_PWMOutputFault
+#else
+#define MAP_PWMOutputFault                                                    \
+        PWMOutputFault
+#endif
+#ifdef ROM_PWMGenIntTrigEnable
+#define MAP_PWMGenIntTrigEnable                                               \
+        ROM_PWMGenIntTrigEnable
+#else
+#define MAP_PWMGenIntTrigEnable                                               \
+        PWMGenIntTrigEnable
+#endif
+#ifdef ROM_PWMGenIntTrigDisable
+#define MAP_PWMGenIntTrigDisable                                              \
+        ROM_PWMGenIntTrigDisable
+#else
+#define MAP_PWMGenIntTrigDisable                                              \
+        PWMGenIntTrigDisable
+#endif
+#ifdef ROM_PWMGenIntStatus
+#define MAP_PWMGenIntStatus                                                   \
+        ROM_PWMGenIntStatus
+#else
+#define MAP_PWMGenIntStatus                                                   \
+        PWMGenIntStatus
+#endif
+#ifdef ROM_PWMGenIntClear
+#define MAP_PWMGenIntClear                                                    \
+        ROM_PWMGenIntClear
+#else
+#define MAP_PWMGenIntClear                                                    \
+        PWMGenIntClear
+#endif
+#ifdef ROM_PWMIntEnable
+#define MAP_PWMIntEnable                                                      \
+        ROM_PWMIntEnable
+#else
+#define MAP_PWMIntEnable                                                      \
+        PWMIntEnable
+#endif
+#ifdef ROM_PWMIntDisable
+#define MAP_PWMIntDisable                                                     \
+        ROM_PWMIntDisable
+#else
+#define MAP_PWMIntDisable                                                     \
+        PWMIntDisable
+#endif
+#ifdef ROM_PWMFaultIntClear
+#define MAP_PWMFaultIntClear                                                  \
+        ROM_PWMFaultIntClear
+#else
+#define MAP_PWMFaultIntClear                                                  \
+        PWMFaultIntClear
+#endif
+#ifdef ROM_PWMIntStatus
+#define MAP_PWMIntStatus                                                      \
+        ROM_PWMIntStatus
+#else
+#define MAP_PWMIntStatus                                                      \
+        PWMIntStatus
+#endif
+#ifdef ROM_PWMOutputFaultLevel
+#define MAP_PWMOutputFaultLevel                                               \
+        ROM_PWMOutputFaultLevel
+#else
+#define MAP_PWMOutputFaultLevel                                               \
+        PWMOutputFaultLevel
+#endif
+#ifdef ROM_PWMFaultIntClearExt
+#define MAP_PWMFaultIntClearExt                                               \
+        ROM_PWMFaultIntClearExt
+#else
+#define MAP_PWMFaultIntClearExt                                               \
+        PWMFaultIntClearExt
+#endif
+#ifdef ROM_PWMGenFaultConfigure
+#define MAP_PWMGenFaultConfigure                                              \
+        ROM_PWMGenFaultConfigure
+#else
+#define MAP_PWMGenFaultConfigure                                              \
+        PWMGenFaultConfigure
+#endif
+#ifdef ROM_PWMGenFaultTriggerSet
+#define MAP_PWMGenFaultTriggerSet                                             \
+        ROM_PWMGenFaultTriggerSet
+#else
+#define MAP_PWMGenFaultTriggerSet                                             \
+        PWMGenFaultTriggerSet
+#endif
+#ifdef ROM_PWMGenFaultTriggerGet
+#define MAP_PWMGenFaultTriggerGet                                             \
+        ROM_PWMGenFaultTriggerGet
+#else
+#define MAP_PWMGenFaultTriggerGet                                             \
+        PWMGenFaultTriggerGet
+#endif
+#ifdef ROM_PWMGenFaultStatus
+#define MAP_PWMGenFaultStatus                                                 \
+        ROM_PWMGenFaultStatus
+#else
+#define MAP_PWMGenFaultStatus                                                 \
+        PWMGenFaultStatus
+#endif
+#ifdef ROM_PWMGenFaultClear
+#define MAP_PWMGenFaultClear                                                  \
+        ROM_PWMGenFaultClear
+#else
+#define MAP_PWMGenFaultClear                                                  \
+        PWMGenFaultClear
+#endif
+#ifdef ROM_PWMClockSet
+#define MAP_PWMClockSet                                                       \
+        ROM_PWMClockSet
+#else
+#define MAP_PWMClockSet                                                       \
+        PWMClockSet
+#endif
+#ifdef ROM_PWMClockGet
+#define MAP_PWMClockGet                                                       \
+        ROM_PWMClockGet
+#else
+#define MAP_PWMClockGet                                                       \
+        PWMClockGet
+#endif
+#ifdef ROM_PWMOutputUpdateMode
+#define MAP_PWMOutputUpdateMode                                               \
+        ROM_PWMOutputUpdateMode
+#else
+#define MAP_PWMOutputUpdateMode                                               \
+        PWMOutputUpdateMode
+#endif
+
+//*****************************************************************************
+//
+// Macros for the QEI API.
+//
+//*****************************************************************************
+#ifdef ROM_QEIPositionGet
+#define MAP_QEIPositionGet                                                    \
+        ROM_QEIPositionGet
+#else
+#define MAP_QEIPositionGet                                                    \
+        QEIPositionGet
+#endif
+#ifdef ROM_QEIEnable
+#define MAP_QEIEnable                                                         \
+        ROM_QEIEnable
+#else
+#define MAP_QEIEnable                                                         \
+        QEIEnable
+#endif
+#ifdef ROM_QEIDisable
+#define MAP_QEIDisable                                                        \
+        ROM_QEIDisable
+#else
+#define MAP_QEIDisable                                                        \
+        QEIDisable
+#endif
+#ifdef ROM_QEIConfigure
+#define MAP_QEIConfigure                                                      \
+        ROM_QEIConfigure
+#else
+#define MAP_QEIConfigure                                                      \
+        QEIConfigure
+#endif
+#ifdef ROM_QEIPositionSet
+#define MAP_QEIPositionSet                                                    \
+        ROM_QEIPositionSet
+#else
+#define MAP_QEIPositionSet                                                    \
+        QEIPositionSet
+#endif
+#ifdef ROM_QEIDirectionGet
+#define MAP_QEIDirectionGet                                                   \
+        ROM_QEIDirectionGet
+#else
+#define MAP_QEIDirectionGet                                                   \
+        QEIDirectionGet
+#endif
+#ifdef ROM_QEIErrorGet
+#define MAP_QEIErrorGet                                                       \
+        ROM_QEIErrorGet
+#else
+#define MAP_QEIErrorGet                                                       \
+        QEIErrorGet
+#endif
+#ifdef ROM_QEIVelocityEnable
+#define MAP_QEIVelocityEnable                                                 \
+        ROM_QEIVelocityEnable
+#else
+#define MAP_QEIVelocityEnable                                                 \
+        QEIVelocityEnable
+#endif
+#ifdef ROM_QEIVelocityDisable
+#define MAP_QEIVelocityDisable                                                \
+        ROM_QEIVelocityDisable
+#else
+#define MAP_QEIVelocityDisable                                                \
+        QEIVelocityDisable
+#endif
+#ifdef ROM_QEIVelocityConfigure
+#define MAP_QEIVelocityConfigure                                              \
+        ROM_QEIVelocityConfigure
+#else
+#define MAP_QEIVelocityConfigure                                              \
+        QEIVelocityConfigure
+#endif
+#ifdef ROM_QEIVelocityGet
+#define MAP_QEIVelocityGet                                                    \
+        ROM_QEIVelocityGet
+#else
+#define MAP_QEIVelocityGet                                                    \
+        QEIVelocityGet
+#endif
+#ifdef ROM_QEIIntEnable
+#define MAP_QEIIntEnable                                                      \
+        ROM_QEIIntEnable
+#else
+#define MAP_QEIIntEnable                                                      \
+        QEIIntEnable
+#endif
+#ifdef ROM_QEIIntDisable
+#define MAP_QEIIntDisable                                                     \
+        ROM_QEIIntDisable
+#else
+#define MAP_QEIIntDisable                                                     \
+        QEIIntDisable
+#endif
+#ifdef ROM_QEIIntStatus
+#define MAP_QEIIntStatus                                                      \
+        ROM_QEIIntStatus
+#else
+#define MAP_QEIIntStatus                                                      \
+        QEIIntStatus
+#endif
+#ifdef ROM_QEIIntClear
+#define MAP_QEIIntClear                                                       \
+        ROM_QEIIntClear
+#else
+#define MAP_QEIIntClear                                                       \
+        QEIIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SHAMD5 API.
+//
+//*****************************************************************************
+#ifdef ROM_SHAMD5IntStatus
+#define MAP_SHAMD5IntStatus                                                   \
+        ROM_SHAMD5IntStatus
+#else
+#define MAP_SHAMD5IntStatus                                                   \
+        SHAMD5IntStatus
+#endif
+#ifdef ROM_SHAMD5ConfigSet
+#define MAP_SHAMD5ConfigSet                                                   \
+        ROM_SHAMD5ConfigSet
+#else
+#define MAP_SHAMD5ConfigSet                                                   \
+        SHAMD5ConfigSet
+#endif
+#ifdef ROM_SHAMD5DataProcess
+#define MAP_SHAMD5DataProcess                                                 \
+        ROM_SHAMD5DataProcess
+#else
+#define MAP_SHAMD5DataProcess                                                 \
+        SHAMD5DataProcess
+#endif
+#ifdef ROM_SHAMD5DataWrite
+#define MAP_SHAMD5DataWrite                                                   \
+        ROM_SHAMD5DataWrite
+#else
+#define MAP_SHAMD5DataWrite                                                   \
+        SHAMD5DataWrite
+#endif
+#ifdef ROM_SHAMD5DataWriteNonBlocking
+#define MAP_SHAMD5DataWriteNonBlocking                                        \
+        ROM_SHAMD5DataWriteNonBlocking
+#else
+#define MAP_SHAMD5DataWriteNonBlocking                                        \
+        SHAMD5DataWriteNonBlocking
+#endif
+#ifdef ROM_SHAMD5DMADisable
+#define MAP_SHAMD5DMADisable                                                  \
+        ROM_SHAMD5DMADisable
+#else
+#define MAP_SHAMD5DMADisable                                                  \
+        SHAMD5DMADisable
+#endif
+#ifdef ROM_SHAMD5DMAEnable
+#define MAP_SHAMD5DMAEnable                                                   \
+        ROM_SHAMD5DMAEnable
+#else
+#define MAP_SHAMD5DMAEnable                                                   \
+        SHAMD5DMAEnable
+#endif
+#ifdef ROM_SHAMD5HashLengthSet
+#define MAP_SHAMD5HashLengthSet                                               \
+        ROM_SHAMD5HashLengthSet
+#else
+#define MAP_SHAMD5HashLengthSet                                               \
+        SHAMD5HashLengthSet
+#endif
+#ifdef ROM_SHAMD5HMACKeySet
+#define MAP_SHAMD5HMACKeySet                                                  \
+        ROM_SHAMD5HMACKeySet
+#else
+#define MAP_SHAMD5HMACKeySet                                                  \
+        SHAMD5HMACKeySet
+#endif
+#ifdef ROM_SHAMD5HMACPPKeyGenerate
+#define MAP_SHAMD5HMACPPKeyGenerate                                           \
+        ROM_SHAMD5HMACPPKeyGenerate
+#else
+#define MAP_SHAMD5HMACPPKeyGenerate                                           \
+        SHAMD5HMACPPKeyGenerate
+#endif
+#ifdef ROM_SHAMD5HMACPPKeySet
+#define MAP_SHAMD5HMACPPKeySet                                                \
+        ROM_SHAMD5HMACPPKeySet
+#else
+#define MAP_SHAMD5HMACPPKeySet                                                \
+        SHAMD5HMACPPKeySet
+#endif
+#ifdef ROM_SHAMD5HMACProcess
+#define MAP_SHAMD5HMACProcess                                                 \
+        ROM_SHAMD5HMACProcess
+#else
+#define MAP_SHAMD5HMACProcess                                                 \
+        SHAMD5HMACProcess
+#endif
+#ifdef ROM_SHAMD5IntClear
+#define MAP_SHAMD5IntClear                                                    \
+        ROM_SHAMD5IntClear
+#else
+#define MAP_SHAMD5IntClear                                                    \
+        SHAMD5IntClear
+#endif
+#ifdef ROM_SHAMD5IntDisable
+#define MAP_SHAMD5IntDisable                                                  \
+        ROM_SHAMD5IntDisable
+#else
+#define MAP_SHAMD5IntDisable                                                  \
+        SHAMD5IntDisable
+#endif
+#ifdef ROM_SHAMD5IntEnable
+#define MAP_SHAMD5IntEnable                                                   \
+        ROM_SHAMD5IntEnable
+#else
+#define MAP_SHAMD5IntEnable                                                   \
+        SHAMD5IntEnable
+#endif
+#ifdef ROM_SHAMD5Reset
+#define MAP_SHAMD5Reset                                                       \
+        ROM_SHAMD5Reset
+#else
+#define MAP_SHAMD5Reset                                                       \
+        SHAMD5Reset
+#endif
+#ifdef ROM_SHAMD5ResultRead
+#define MAP_SHAMD5ResultRead                                                  \
+        ROM_SHAMD5ResultRead
+#else
+#define MAP_SHAMD5ResultRead                                                  \
+        SHAMD5ResultRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SMBus API.
+//
+//*****************************************************************************
+#ifdef ROM_SMBusMasterIntProcess
+#define MAP_SMBusMasterIntProcess                                             \
+        ROM_SMBusMasterIntProcess
+#else
+#define MAP_SMBusMasterIntProcess                                             \
+        SMBusMasterIntProcess
+#endif
+#ifdef ROM_SMBusARPDisable
+#define MAP_SMBusARPDisable                                                   \
+        ROM_SMBusARPDisable
+#else
+#define MAP_SMBusARPDisable                                                   \
+        SMBusARPDisable
+#endif
+#ifdef ROM_SMBusARPEnable
+#define MAP_SMBusARPEnable                                                    \
+        ROM_SMBusARPEnable
+#else
+#define MAP_SMBusARPEnable                                                    \
+        SMBusARPEnable
+#endif
+#ifdef ROM_SMBusARPUDIDPacketDecode
+#define MAP_SMBusARPUDIDPacketDecode                                          \
+        ROM_SMBusARPUDIDPacketDecode
+#else
+#define MAP_SMBusARPUDIDPacketDecode                                          \
+        SMBusARPUDIDPacketDecode
+#endif
+#ifdef ROM_SMBusARPUDIDPacketEncode
+#define MAP_SMBusARPUDIDPacketEncode                                          \
+        ROM_SMBusARPUDIDPacketEncode
+#else
+#define MAP_SMBusARPUDIDPacketEncode                                          \
+        SMBusARPUDIDPacketEncode
+#endif
+#ifdef ROM_SMBusMasterARPAssignAddress
+#define MAP_SMBusMasterARPAssignAddress                                       \
+        ROM_SMBusMasterARPAssignAddress
+#else
+#define MAP_SMBusMasterARPAssignAddress                                       \
+        SMBusMasterARPAssignAddress
+#endif
+#ifdef ROM_SMBusMasterARPGetUDIDDir
+#define MAP_SMBusMasterARPGetUDIDDir                                          \
+        ROM_SMBusMasterARPGetUDIDDir
+#else
+#define MAP_SMBusMasterARPGetUDIDDir                                          \
+        SMBusMasterARPGetUDIDDir
+#endif
+#ifdef ROM_SMBusMasterARPGetUDIDGen
+#define MAP_SMBusMasterARPGetUDIDGen                                          \
+        ROM_SMBusMasterARPGetUDIDGen
+#else
+#define MAP_SMBusMasterARPGetUDIDGen                                          \
+        SMBusMasterARPGetUDIDGen
+#endif
+#ifdef ROM_SMBusMasterARPNotifyMaster
+#define MAP_SMBusMasterARPNotifyMaster                                        \
+        ROM_SMBusMasterARPNotifyMaster
+#else
+#define MAP_SMBusMasterARPNotifyMaster                                        \
+        SMBusMasterARPNotifyMaster
+#endif
+#ifdef ROM_SMBusMasterARPPrepareToARP
+#define MAP_SMBusMasterARPPrepareToARP                                        \
+        ROM_SMBusMasterARPPrepareToARP
+#else
+#define MAP_SMBusMasterARPPrepareToARP                                        \
+        SMBusMasterARPPrepareToARP
+#endif
+#ifdef ROM_SMBusMasterARPResetDeviceDir
+#define MAP_SMBusMasterARPResetDeviceDir                                      \
+        ROM_SMBusMasterARPResetDeviceDir
+#else
+#define MAP_SMBusMasterARPResetDeviceDir                                      \
+        SMBusMasterARPResetDeviceDir
+#endif
+#ifdef ROM_SMBusMasterARPResetDeviceGen
+#define MAP_SMBusMasterARPResetDeviceGen                                      \
+        ROM_SMBusMasterARPResetDeviceGen
+#else
+#define MAP_SMBusMasterARPResetDeviceGen                                      \
+        SMBusMasterARPResetDeviceGen
+#endif
+#ifdef ROM_SMBusMasterBlockProcessCall
+#define MAP_SMBusMasterBlockProcessCall                                       \
+        ROM_SMBusMasterBlockProcessCall
+#else
+#define MAP_SMBusMasterBlockProcessCall                                       \
+        SMBusMasterBlockProcessCall
+#endif
+#ifdef ROM_SMBusMasterBlockRead
+#define MAP_SMBusMasterBlockRead                                              \
+        ROM_SMBusMasterBlockRead
+#else
+#define MAP_SMBusMasterBlockRead                                              \
+        SMBusMasterBlockRead
+#endif
+#ifdef ROM_SMBusMasterBlockWrite
+#define MAP_SMBusMasterBlockWrite                                             \
+        ROM_SMBusMasterBlockWrite
+#else
+#define MAP_SMBusMasterBlockWrite                                             \
+        SMBusMasterBlockWrite
+#endif
+#ifdef ROM_SMBusMasterByteReceive
+#define MAP_SMBusMasterByteReceive                                            \
+        ROM_SMBusMasterByteReceive
+#else
+#define MAP_SMBusMasterByteReceive                                            \
+        SMBusMasterByteReceive
+#endif
+#ifdef ROM_SMBusMasterByteSend
+#define MAP_SMBusMasterByteSend                                               \
+        ROM_SMBusMasterByteSend
+#else
+#define MAP_SMBusMasterByteSend                                               \
+        SMBusMasterByteSend
+#endif
+#ifdef ROM_SMBusMasterByteWordRead
+#define MAP_SMBusMasterByteWordRead                                           \
+        ROM_SMBusMasterByteWordRead
+#else
+#define MAP_SMBusMasterByteWordRead                                           \
+        SMBusMasterByteWordRead
+#endif
+#ifdef ROM_SMBusMasterByteWordWrite
+#define MAP_SMBusMasterByteWordWrite                                          \
+        ROM_SMBusMasterByteWordWrite
+#else
+#define MAP_SMBusMasterByteWordWrite                                          \
+        SMBusMasterByteWordWrite
+#endif
+#ifdef ROM_SMBusMasterHostNotify
+#define MAP_SMBusMasterHostNotify                                             \
+        ROM_SMBusMasterHostNotify
+#else
+#define MAP_SMBusMasterHostNotify                                             \
+        SMBusMasterHostNotify
+#endif
+#ifdef ROM_SMBusMasterI2CRead
+#define MAP_SMBusMasterI2CRead                                                \
+        ROM_SMBusMasterI2CRead
+#else
+#define MAP_SMBusMasterI2CRead                                                \
+        SMBusMasterI2CRead
+#endif
+#ifdef ROM_SMBusMasterI2CWrite
+#define MAP_SMBusMasterI2CWrite                                               \
+        ROM_SMBusMasterI2CWrite
+#else
+#define MAP_SMBusMasterI2CWrite                                               \
+        SMBusMasterI2CWrite
+#endif
+#ifdef ROM_SMBusMasterI2CWriteRead
+#define MAP_SMBusMasterI2CWriteRead                                           \
+        ROM_SMBusMasterI2CWriteRead
+#else
+#define MAP_SMBusMasterI2CWriteRead                                           \
+        SMBusMasterI2CWriteRead
+#endif
+#ifdef ROM_SMBusMasterInit
+#define MAP_SMBusMasterInit                                                   \
+        ROM_SMBusMasterInit
+#else
+#define MAP_SMBusMasterInit                                                   \
+        SMBusMasterInit
+#endif
+#ifdef ROM_SMBusMasterIntEnable
+#define MAP_SMBusMasterIntEnable                                              \
+        ROM_SMBusMasterIntEnable
+#else
+#define MAP_SMBusMasterIntEnable                                              \
+        SMBusMasterIntEnable
+#endif
+#ifdef ROM_SMBusMasterProcessCall
+#define MAP_SMBusMasterProcessCall                                            \
+        ROM_SMBusMasterProcessCall
+#else
+#define MAP_SMBusMasterProcessCall                                            \
+        SMBusMasterProcessCall
+#endif
+#ifdef ROM_SMBusMasterQuickCommand
+#define MAP_SMBusMasterQuickCommand                                           \
+        ROM_SMBusMasterQuickCommand
+#else
+#define MAP_SMBusMasterQuickCommand                                           \
+        SMBusMasterQuickCommand
+#endif
+#ifdef ROM_SMBusPECDisable
+#define MAP_SMBusPECDisable                                                   \
+        ROM_SMBusPECDisable
+#else
+#define MAP_SMBusPECDisable                                                   \
+        SMBusPECDisable
+#endif
+#ifdef ROM_SMBusPECEnable
+#define MAP_SMBusPECEnable                                                    \
+        ROM_SMBusPECEnable
+#else
+#define MAP_SMBusPECEnable                                                    \
+        SMBusPECEnable
+#endif
+#ifdef ROM_SMBusRxPacketSizeGet
+#define MAP_SMBusRxPacketSizeGet                                              \
+        ROM_SMBusRxPacketSizeGet
+#else
+#define MAP_SMBusRxPacketSizeGet                                              \
+        SMBusRxPacketSizeGet
+#endif
+#ifdef ROM_SMBusSlaveACKSend
+#define MAP_SMBusSlaveACKSend                                                 \
+        ROM_SMBusSlaveACKSend
+#else
+#define MAP_SMBusSlaveACKSend                                                 \
+        SMBusSlaveACKSend
+#endif
+#ifdef ROM_SMBusSlaveAddressSet
+#define MAP_SMBusSlaveAddressSet                                              \
+        ROM_SMBusSlaveAddressSet
+#else
+#define MAP_SMBusSlaveAddressSet                                              \
+        SMBusSlaveAddressSet
+#endif
+#ifdef ROM_SMBusSlaveARPFlagARGet
+#define MAP_SMBusSlaveARPFlagARGet                                            \
+        ROM_SMBusSlaveARPFlagARGet
+#else
+#define MAP_SMBusSlaveARPFlagARGet                                            \
+        SMBusSlaveARPFlagARGet
+#endif
+#ifdef ROM_SMBusSlaveARPFlagARSet
+#define MAP_SMBusSlaveARPFlagARSet                                            \
+        ROM_SMBusSlaveARPFlagARSet
+#else
+#define MAP_SMBusSlaveARPFlagARSet                                            \
+        SMBusSlaveARPFlagARSet
+#endif
+#ifdef ROM_SMBusSlaveARPFlagAVGet
+#define MAP_SMBusSlaveARPFlagAVGet                                            \
+        ROM_SMBusSlaveARPFlagAVGet
+#else
+#define MAP_SMBusSlaveARPFlagAVGet                                            \
+        SMBusSlaveARPFlagAVGet
+#endif
+#ifdef ROM_SMBusSlaveARPFlagAVSet
+#define MAP_SMBusSlaveARPFlagAVSet                                            \
+        ROM_SMBusSlaveARPFlagAVSet
+#else
+#define MAP_SMBusSlaveARPFlagAVSet                                            \
+        SMBusSlaveARPFlagAVSet
+#endif
+#ifdef ROM_SMBusSlaveBlockTransferDisable
+#define MAP_SMBusSlaveBlockTransferDisable                                    \
+        ROM_SMBusSlaveBlockTransferDisable
+#else
+#define MAP_SMBusSlaveBlockTransferDisable                                    \
+        SMBusSlaveBlockTransferDisable
+#endif
+#ifdef ROM_SMBusSlaveBlockTransferEnable
+#define MAP_SMBusSlaveBlockTransferEnable                                     \
+        ROM_SMBusSlaveBlockTransferEnable
+#else
+#define MAP_SMBusSlaveBlockTransferEnable                                     \
+        SMBusSlaveBlockTransferEnable
+#endif
+#ifdef ROM_SMBusSlaveCommandGet
+#define MAP_SMBusSlaveCommandGet                                              \
+        ROM_SMBusSlaveCommandGet
+#else
+#define MAP_SMBusSlaveCommandGet                                              \
+        SMBusSlaveCommandGet
+#endif
+#ifdef ROM_SMBusSlaveI2CDisable
+#define MAP_SMBusSlaveI2CDisable                                              \
+        ROM_SMBusSlaveI2CDisable
+#else
+#define MAP_SMBusSlaveI2CDisable                                              \
+        SMBusSlaveI2CDisable
+#endif
+#ifdef ROM_SMBusSlaveI2CEnable
+#define MAP_SMBusSlaveI2CEnable                                               \
+        ROM_SMBusSlaveI2CEnable
+#else
+#define MAP_SMBusSlaveI2CEnable                                               \
+        SMBusSlaveI2CEnable
+#endif
+#ifdef ROM_SMBusSlaveInit
+#define MAP_SMBusSlaveInit                                                    \
+        ROM_SMBusSlaveInit
+#else
+#define MAP_SMBusSlaveInit                                                    \
+        SMBusSlaveInit
+#endif
+#ifdef ROM_SMBusSlaveIntAddressGet
+#define MAP_SMBusSlaveIntAddressGet                                           \
+        ROM_SMBusSlaveIntAddressGet
+#else
+#define MAP_SMBusSlaveIntAddressGet                                           \
+        SMBusSlaveIntAddressGet
+#endif
+#ifdef ROM_SMBusSlaveIntEnable
+#define MAP_SMBusSlaveIntEnable                                               \
+        ROM_SMBusSlaveIntEnable
+#else
+#define MAP_SMBusSlaveIntEnable                                               \
+        SMBusSlaveIntEnable
+#endif
+#ifdef ROM_SMBusSlaveIntProcess
+#define MAP_SMBusSlaveIntProcess                                              \
+        ROM_SMBusSlaveIntProcess
+#else
+#define MAP_SMBusSlaveIntProcess                                              \
+        SMBusSlaveIntProcess
+#endif
+#ifdef ROM_SMBusSlaveManualACKDisable
+#define MAP_SMBusSlaveManualACKDisable                                        \
+        ROM_SMBusSlaveManualACKDisable
+#else
+#define MAP_SMBusSlaveManualACKDisable                                        \
+        SMBusSlaveManualACKDisable
+#endif
+#ifdef ROM_SMBusSlaveManualACKEnable
+#define MAP_SMBusSlaveManualACKEnable                                         \
+        ROM_SMBusSlaveManualACKEnable
+#else
+#define MAP_SMBusSlaveManualACKEnable                                         \
+        SMBusSlaveManualACKEnable
+#endif
+#ifdef ROM_SMBusSlaveManualACKStatusGet
+#define MAP_SMBusSlaveManualACKStatusGet                                      \
+        ROM_SMBusSlaveManualACKStatusGet
+#else
+#define MAP_SMBusSlaveManualACKStatusGet                                      \
+        SMBusSlaveManualACKStatusGet
+#endif
+#ifdef ROM_SMBusSlaveProcessCallDisable
+#define MAP_SMBusSlaveProcessCallDisable                                      \
+        ROM_SMBusSlaveProcessCallDisable
+#else
+#define MAP_SMBusSlaveProcessCallDisable                                      \
+        SMBusSlaveProcessCallDisable
+#endif
+#ifdef ROM_SMBusSlaveProcessCallEnable
+#define MAP_SMBusSlaveProcessCallEnable                                       \
+        ROM_SMBusSlaveProcessCallEnable
+#else
+#define MAP_SMBusSlaveProcessCallEnable                                       \
+        SMBusSlaveProcessCallEnable
+#endif
+#ifdef ROM_SMBusSlaveRxBufferSet
+#define MAP_SMBusSlaveRxBufferSet                                             \
+        ROM_SMBusSlaveRxBufferSet
+#else
+#define MAP_SMBusSlaveRxBufferSet                                             \
+        SMBusSlaveRxBufferSet
+#endif
+#ifdef ROM_SMBusSlaveTransferInit
+#define MAP_SMBusSlaveTransferInit                                            \
+        ROM_SMBusSlaveTransferInit
+#else
+#define MAP_SMBusSlaveTransferInit                                            \
+        SMBusSlaveTransferInit
+#endif
+#ifdef ROM_SMBusSlaveTxBufferSet
+#define MAP_SMBusSlaveTxBufferSet                                             \
+        ROM_SMBusSlaveTxBufferSet
+#else
+#define MAP_SMBusSlaveTxBufferSet                                             \
+        SMBusSlaveTxBufferSet
+#endif
+#ifdef ROM_SMBusSlaveUDIDSet
+#define MAP_SMBusSlaveUDIDSet                                                 \
+        ROM_SMBusSlaveUDIDSet
+#else
+#define MAP_SMBusSlaveUDIDSet                                                 \
+        SMBusSlaveUDIDSet
+#endif
+#ifdef ROM_SMBusStatusGet
+#define MAP_SMBusStatusGet                                                    \
+        ROM_SMBusStatusGet
+#else
+#define MAP_SMBusStatusGet                                                    \
+        SMBusStatusGet
+#endif
+#ifdef ROM_SMBusSlaveDataSend
+#define MAP_SMBusSlaveDataSend                                                \
+        ROM_SMBusSlaveDataSend
+#else
+#define MAP_SMBusSlaveDataSend                                                \
+        SMBusSlaveDataSend
+#endif
+#ifdef ROM_SMBusFIFOEnable
+#define MAP_SMBusFIFOEnable                                                   \
+        ROM_SMBusFIFOEnable
+#else
+#define MAP_SMBusFIFOEnable                                                   \
+        SMBusFIFOEnable
+#endif
+#ifdef ROM_SMBusFIFODisable
+#define MAP_SMBusFIFODisable                                                  \
+        ROM_SMBusFIFODisable
+#else
+#define MAP_SMBusFIFODisable                                                  \
+        SMBusFIFODisable
+#endif
+#ifdef ROM_SMBusDMAEnable
+#define MAP_SMBusDMAEnable                                                    \
+        ROM_SMBusDMAEnable
+#else
+#define MAP_SMBusDMAEnable                                                    \
+        SMBusDMAEnable
+#endif
+#ifdef ROM_SMBusDMADisable
+#define MAP_SMBusDMADisable                                                   \
+        ROM_SMBusDMADisable
+#else
+#define MAP_SMBusDMADisable                                                   \
+        SMBusDMADisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SPIFlash API.
+//
+//*****************************************************************************
+#ifdef ROM_SPIFlashIntHandler
+#define MAP_SPIFlashIntHandler                                                \
+        ROM_SPIFlashIntHandler
+#else
+#define MAP_SPIFlashIntHandler                                                \
+        SPIFlashIntHandler
+#endif
+#ifdef ROM_SPIFlashInit
+#define MAP_SPIFlashInit                                                      \
+        ROM_SPIFlashInit
+#else
+#define MAP_SPIFlashInit                                                      \
+        SPIFlashInit
+#endif
+#ifdef ROM_SPIFlashWriteStatus
+#define MAP_SPIFlashWriteStatus                                               \
+        ROM_SPIFlashWriteStatus
+#else
+#define MAP_SPIFlashWriteStatus                                               \
+        SPIFlashWriteStatus
+#endif
+#ifdef ROM_SPIFlashPageProgram
+#define MAP_SPIFlashPageProgram                                               \
+        ROM_SPIFlashPageProgram
+#else
+#define MAP_SPIFlashPageProgram                                               \
+        SPIFlashPageProgram
+#endif
+#ifdef ROM_SPIFlashPageProgramNonBlocking
+#define MAP_SPIFlashPageProgramNonBlocking                                    \
+        ROM_SPIFlashPageProgramNonBlocking
+#else
+#define MAP_SPIFlashPageProgramNonBlocking                                    \
+        SPIFlashPageProgramNonBlocking
+#endif
+#ifdef ROM_SPIFlashRead
+#define MAP_SPIFlashRead                                                      \
+        ROM_SPIFlashRead
+#else
+#define MAP_SPIFlashRead                                                      \
+        SPIFlashRead
+#endif
+#ifdef ROM_SPIFlashReadNonBlocking
+#define MAP_SPIFlashReadNonBlocking                                           \
+        ROM_SPIFlashReadNonBlocking
+#else
+#define MAP_SPIFlashReadNonBlocking                                           \
+        SPIFlashReadNonBlocking
+#endif
+#ifdef ROM_SPIFlashWriteDisable
+#define MAP_SPIFlashWriteDisable                                              \
+        ROM_SPIFlashWriteDisable
+#else
+#define MAP_SPIFlashWriteDisable                                              \
+        SPIFlashWriteDisable
+#endif
+#ifdef ROM_SPIFlashReadStatus
+#define MAP_SPIFlashReadStatus                                                \
+        ROM_SPIFlashReadStatus
+#else
+#define MAP_SPIFlashReadStatus                                                \
+        SPIFlashReadStatus
+#endif
+#ifdef ROM_SPIFlashWriteEnable
+#define MAP_SPIFlashWriteEnable                                               \
+        ROM_SPIFlashWriteEnable
+#else
+#define MAP_SPIFlashWriteEnable                                               \
+        SPIFlashWriteEnable
+#endif
+#ifdef ROM_SPIFlashFastRead
+#define MAP_SPIFlashFastRead                                                  \
+        ROM_SPIFlashFastRead
+#else
+#define MAP_SPIFlashFastRead                                                  \
+        SPIFlashFastRead
+#endif
+#ifdef ROM_SPIFlashFastReadNonBlocking
+#define MAP_SPIFlashFastReadNonBlocking                                       \
+        ROM_SPIFlashFastReadNonBlocking
+#else
+#define MAP_SPIFlashFastReadNonBlocking                                       \
+        SPIFlashFastReadNonBlocking
+#endif
+#ifdef ROM_SPIFlashSectorErase
+#define MAP_SPIFlashSectorErase                                               \
+        ROM_SPIFlashSectorErase
+#else
+#define MAP_SPIFlashSectorErase                                               \
+        SPIFlashSectorErase
+#endif
+#ifdef ROM_SPIFlashDualRead
+#define MAP_SPIFlashDualRead                                                  \
+        ROM_SPIFlashDualRead
+#else
+#define MAP_SPIFlashDualRead                                                  \
+        SPIFlashDualRead
+#endif
+#ifdef ROM_SPIFlashDualReadNonBlocking
+#define MAP_SPIFlashDualReadNonBlocking                                       \
+        ROM_SPIFlashDualReadNonBlocking
+#else
+#define MAP_SPIFlashDualReadNonBlocking                                       \
+        SPIFlashDualReadNonBlocking
+#endif
+#ifdef ROM_SPIFlashBlockErase32
+#define MAP_SPIFlashBlockErase32                                              \
+        ROM_SPIFlashBlockErase32
+#else
+#define MAP_SPIFlashBlockErase32                                              \
+        SPIFlashBlockErase32
+#endif
+#ifdef ROM_SPIFlashQuadRead
+#define MAP_SPIFlashQuadRead                                                  \
+        ROM_SPIFlashQuadRead
+#else
+#define MAP_SPIFlashQuadRead                                                  \
+        SPIFlashQuadRead
+#endif
+#ifdef ROM_SPIFlashQuadReadNonBlocking
+#define MAP_SPIFlashQuadReadNonBlocking                                       \
+        ROM_SPIFlashQuadReadNonBlocking
+#else
+#define MAP_SPIFlashQuadReadNonBlocking                                       \
+        SPIFlashQuadReadNonBlocking
+#endif
+#ifdef ROM_SPIFlashReadID
+#define MAP_SPIFlashReadID                                                    \
+        ROM_SPIFlashReadID
+#else
+#define MAP_SPIFlashReadID                                                    \
+        SPIFlashReadID
+#endif
+#ifdef ROM_SPIFlashChipErase
+#define MAP_SPIFlashChipErase                                                 \
+        ROM_SPIFlashChipErase
+#else
+#define MAP_SPIFlashChipErase                                                 \
+        SPIFlashChipErase
+#endif
+#ifdef ROM_SPIFlashBlockErase64
+#define MAP_SPIFlashBlockErase64                                              \
+        ROM_SPIFlashBlockErase64
+#else
+#define MAP_SPIFlashBlockErase64                                              \
+        SPIFlashBlockErase64
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SSI API.
+//
+//*****************************************************************************
+#ifdef ROM_SSIDataPut
+#define MAP_SSIDataPut                                                        \
+        ROM_SSIDataPut
+#else
+#define MAP_SSIDataPut                                                        \
+        SSIDataPut
+#endif
+#ifdef ROM_SSIConfigSetExpClk
+#define MAP_SSIConfigSetExpClk                                                \
+        ROM_SSIConfigSetExpClk
+#else
+#define MAP_SSIConfigSetExpClk                                                \
+        SSIConfigSetExpClk
+#endif
+#ifdef ROM_SSIEnable
+#define MAP_SSIEnable                                                         \
+        ROM_SSIEnable
+#else
+#define MAP_SSIEnable                                                         \
+        SSIEnable
+#endif
+#ifdef ROM_SSIDisable
+#define MAP_SSIDisable                                                        \
+        ROM_SSIDisable
+#else
+#define MAP_SSIDisable                                                        \
+        SSIDisable
+#endif
+#ifdef ROM_SSIIntEnable
+#define MAP_SSIIntEnable                                                      \
+        ROM_SSIIntEnable
+#else
+#define MAP_SSIIntEnable                                                      \
+        SSIIntEnable
+#endif
+#ifdef ROM_SSIIntDisable
+#define MAP_SSIIntDisable                                                     \
+        ROM_SSIIntDisable
+#else
+#define MAP_SSIIntDisable                                                     \
+        SSIIntDisable
+#endif
+#ifdef ROM_SSIIntStatus
+#define MAP_SSIIntStatus                                                      \
+        ROM_SSIIntStatus
+#else
+#define MAP_SSIIntStatus                                                      \
+        SSIIntStatus
+#endif
+#ifdef ROM_SSIIntClear
+#define MAP_SSIIntClear                                                       \
+        ROM_SSIIntClear
+#else
+#define MAP_SSIIntClear                                                       \
+        SSIIntClear
+#endif
+#ifdef ROM_SSIDataPutNonBlocking
+#define MAP_SSIDataPutNonBlocking                                             \
+        ROM_SSIDataPutNonBlocking
+#else
+#define MAP_SSIDataPutNonBlocking                                             \
+        SSIDataPutNonBlocking
+#endif
+#ifdef ROM_SSIDataGet
+#define MAP_SSIDataGet                                                        \
+        ROM_SSIDataGet
+#else
+#define MAP_SSIDataGet                                                        \
+        SSIDataGet
+#endif
+#ifdef ROM_SSIDataGetNonBlocking
+#define MAP_SSIDataGetNonBlocking                                             \
+        ROM_SSIDataGetNonBlocking
+#else
+#define MAP_SSIDataGetNonBlocking                                             \
+        SSIDataGetNonBlocking
+#endif
+#ifdef ROM_SSIDMAEnable
+#define MAP_SSIDMAEnable                                                      \
+        ROM_SSIDMAEnable
+#else
+#define MAP_SSIDMAEnable                                                      \
+        SSIDMAEnable
+#endif
+#ifdef ROM_SSIDMADisable
+#define MAP_SSIDMADisable                                                     \
+        ROM_SSIDMADisable
+#else
+#define MAP_SSIDMADisable                                                     \
+        SSIDMADisable
+#endif
+#ifdef ROM_SSIBusy
+#define MAP_SSIBusy                                                           \
+        ROM_SSIBusy
+#else
+#define MAP_SSIBusy                                                           \
+        SSIBusy
+#endif
+#ifdef ROM_SSIClockSourceGet
+#define MAP_SSIClockSourceGet                                                 \
+        ROM_SSIClockSourceGet
+#else
+#define MAP_SSIClockSourceGet                                                 \
+        SSIClockSourceGet
+#endif
+#ifdef ROM_SSIClockSourceSet
+#define MAP_SSIClockSourceSet                                                 \
+        ROM_SSIClockSourceSet
+#else
+#define MAP_SSIClockSourceSet                                                 \
+        SSIClockSourceSet
+#endif
+#ifdef ROM_SSIAdvModeSet
+#define MAP_SSIAdvModeSet                                                     \
+        ROM_SSIAdvModeSet
+#else
+#define MAP_SSIAdvModeSet                                                     \
+        SSIAdvModeSet
+#endif
+#ifdef ROM_SSIAdvDataPutFrameEnd
+#define MAP_SSIAdvDataPutFrameEnd                                             \
+        ROM_SSIAdvDataPutFrameEnd
+#else
+#define MAP_SSIAdvDataPutFrameEnd                                             \
+        SSIAdvDataPutFrameEnd
+#endif
+#ifdef ROM_SSIAdvDataPutFrameEndNonBlocking
+#define MAP_SSIAdvDataPutFrameEndNonBlocking                                  \
+        ROM_SSIAdvDataPutFrameEndNonBlocking
+#else
+#define MAP_SSIAdvDataPutFrameEndNonBlocking                                  \
+        SSIAdvDataPutFrameEndNonBlocking
+#endif
+#ifdef ROM_SSIAdvFrameHoldEnable
+#define MAP_SSIAdvFrameHoldEnable                                             \
+        ROM_SSIAdvFrameHoldEnable
+#else
+#define MAP_SSIAdvFrameHoldEnable                                             \
+        SSIAdvFrameHoldEnable
+#endif
+#ifdef ROM_SSIAdvFrameHoldDisable
+#define MAP_SSIAdvFrameHoldDisable                                            \
+        ROM_SSIAdvFrameHoldDisable
+#else
+#define MAP_SSIAdvFrameHoldDisable                                            \
+        SSIAdvFrameHoldDisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysCtl API.
+//
+//*****************************************************************************
+#ifdef ROM_SysCtlSleep
+#define MAP_SysCtlSleep                                                       \
+        ROM_SysCtlSleep
+#else
+#define MAP_SysCtlSleep                                                       \
+        SysCtlSleep
+#endif
+#ifdef ROM_SysCtlSRAMSizeGet
+#define MAP_SysCtlSRAMSizeGet                                                 \
+        ROM_SysCtlSRAMSizeGet
+#else
+#define MAP_SysCtlSRAMSizeGet                                                 \
+        SysCtlSRAMSizeGet
+#endif
+#ifdef ROM_SysCtlFlashSizeGet
+#define MAP_SysCtlFlashSizeGet                                                \
+        ROM_SysCtlFlashSizeGet
+#else
+#define MAP_SysCtlFlashSizeGet                                                \
+        SysCtlFlashSizeGet
+#endif
+#ifdef ROM_SysCtlPeripheralPresent
+#define MAP_SysCtlPeripheralPresent                                           \
+        ROM_SysCtlPeripheralPresent
+#else
+#define MAP_SysCtlPeripheralPresent                                           \
+        SysCtlPeripheralPresent
+#endif
+#ifdef ROM_SysCtlPeripheralReset
+#define MAP_SysCtlPeripheralReset                                             \
+        ROM_SysCtlPeripheralReset
+#else
+#define MAP_SysCtlPeripheralReset                                             \
+        SysCtlPeripheralReset
+#endif
+#ifdef ROM_SysCtlPeripheralEnable
+#define MAP_SysCtlPeripheralEnable                                            \
+        ROM_SysCtlPeripheralEnable
+#else
+#define MAP_SysCtlPeripheralEnable                                            \
+        SysCtlPeripheralEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDisable
+#define MAP_SysCtlPeripheralDisable                                           \
+        ROM_SysCtlPeripheralDisable
+#else
+#define MAP_SysCtlPeripheralDisable                                           \
+        SysCtlPeripheralDisable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepEnable
+#define MAP_SysCtlPeripheralSleepEnable                                       \
+        ROM_SysCtlPeripheralSleepEnable
+#else
+#define MAP_SysCtlPeripheralSleepEnable                                       \
+        SysCtlPeripheralSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepDisable
+#define MAP_SysCtlPeripheralSleepDisable                                      \
+        ROM_SysCtlPeripheralSleepDisable
+#else
+#define MAP_SysCtlPeripheralSleepDisable                                      \
+        SysCtlPeripheralSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepEnable
+#define MAP_SysCtlPeripheralDeepSleepEnable                                   \
+        ROM_SysCtlPeripheralDeepSleepEnable
+#else
+#define MAP_SysCtlPeripheralDeepSleepEnable                                   \
+        SysCtlPeripheralDeepSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepDisable
+#define MAP_SysCtlPeripheralDeepSleepDisable                                  \
+        ROM_SysCtlPeripheralDeepSleepDisable
+#else
+#define MAP_SysCtlPeripheralDeepSleepDisable                                  \
+        SysCtlPeripheralDeepSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralClockGating
+#define MAP_SysCtlPeripheralClockGating                                       \
+        ROM_SysCtlPeripheralClockGating
+#else
+#define MAP_SysCtlPeripheralClockGating                                       \
+        SysCtlPeripheralClockGating
+#endif
+#ifdef ROM_SysCtlIntEnable
+#define MAP_SysCtlIntEnable                                                   \
+        ROM_SysCtlIntEnable
+#else
+#define MAP_SysCtlIntEnable                                                   \
+        SysCtlIntEnable
+#endif
+#ifdef ROM_SysCtlIntDisable
+#define MAP_SysCtlIntDisable                                                  \
+        ROM_SysCtlIntDisable
+#else
+#define MAP_SysCtlIntDisable                                                  \
+        SysCtlIntDisable
+#endif
+#ifdef ROM_SysCtlIntClear
+#define MAP_SysCtlIntClear                                                    \
+        ROM_SysCtlIntClear
+#else
+#define MAP_SysCtlIntClear                                                    \
+        SysCtlIntClear
+#endif
+#ifdef ROM_SysCtlIntStatus
+#define MAP_SysCtlIntStatus                                                   \
+        ROM_SysCtlIntStatus
+#else
+#define MAP_SysCtlIntStatus                                                   \
+        SysCtlIntStatus
+#endif
+#ifdef ROM_SysCtlReset
+#define MAP_SysCtlReset                                                       \
+        ROM_SysCtlReset
+#else
+#define MAP_SysCtlReset                                                       \
+        SysCtlReset
+#endif
+#ifdef ROM_SysCtlDeepSleep
+#define MAP_SysCtlDeepSleep                                                   \
+        ROM_SysCtlDeepSleep
+#else
+#define MAP_SysCtlDeepSleep                                                   \
+        SysCtlDeepSleep
+#endif
+#ifdef ROM_SysCtlResetCauseGet
+#define MAP_SysCtlResetCauseGet                                               \
+        ROM_SysCtlResetCauseGet
+#else
+#define MAP_SysCtlResetCauseGet                                               \
+        SysCtlResetCauseGet
+#endif
+#ifdef ROM_SysCtlResetCauseClear
+#define MAP_SysCtlResetCauseClear                                             \
+        ROM_SysCtlResetCauseClear
+#else
+#define MAP_SysCtlResetCauseClear                                             \
+        SysCtlResetCauseClear
+#endif
+#ifdef ROM_SysCtlClockSet
+#define MAP_SysCtlClockSet                                                    \
+        ROM_SysCtlClockSet
+#else
+#define MAP_SysCtlClockSet                                                    \
+        SysCtlClockSet
+#endif
+#ifdef ROM_SysCtlClockGet
+#define MAP_SysCtlClockGet                                                    \
+        ROM_SysCtlClockGet
+#else
+#define MAP_SysCtlClockGet                                                    \
+        SysCtlClockGet
+#endif
+#ifdef ROM_SysCtlPWMClockSet
+#define MAP_SysCtlPWMClockSet                                                 \
+        ROM_SysCtlPWMClockSet
+#else
+#define MAP_SysCtlPWMClockSet                                                 \
+        SysCtlPWMClockSet
+#endif
+#ifdef ROM_SysCtlPWMClockGet
+#define MAP_SysCtlPWMClockGet                                                 \
+        ROM_SysCtlPWMClockGet
+#else
+#define MAP_SysCtlPWMClockGet                                                 \
+        SysCtlPWMClockGet
+#endif
+#ifdef ROM_SysCtlUSBPLLEnable
+#define MAP_SysCtlUSBPLLEnable                                                \
+        ROM_SysCtlUSBPLLEnable
+#else
+#define MAP_SysCtlUSBPLLEnable                                                \
+        SysCtlUSBPLLEnable
+#endif
+#ifdef ROM_SysCtlUSBPLLDisable
+#define MAP_SysCtlUSBPLLDisable                                               \
+        ROM_SysCtlUSBPLLDisable
+#else
+#define MAP_SysCtlUSBPLLDisable                                               \
+        SysCtlUSBPLLDisable
+#endif
+#ifdef ROM_SysCtlDelay
+#define MAP_SysCtlDelay                                                       \
+        ROM_SysCtlDelay
+#else
+#define MAP_SysCtlDelay                                                       \
+        SysCtlDelay
+#endif
+#ifdef ROM_SysCtlPeripheralReady
+#define MAP_SysCtlPeripheralReady                                             \
+        ROM_SysCtlPeripheralReady
+#else
+#define MAP_SysCtlPeripheralReady                                             \
+        SysCtlPeripheralReady
+#endif
+#ifdef ROM_SysCtlPeripheralPowerOn
+#define MAP_SysCtlPeripheralPowerOn                                           \
+        ROM_SysCtlPeripheralPowerOn
+#else
+#define MAP_SysCtlPeripheralPowerOn                                           \
+        SysCtlPeripheralPowerOn
+#endif
+#ifdef ROM_SysCtlPeripheralPowerOff
+#define MAP_SysCtlPeripheralPowerOff                                          \
+        ROM_SysCtlPeripheralPowerOff
+#else
+#define MAP_SysCtlPeripheralPowerOff                                          \
+        SysCtlPeripheralPowerOff
+#endif
+#ifdef ROM_SysCtlMOSCConfigSet
+#define MAP_SysCtlMOSCConfigSet                                               \
+        ROM_SysCtlMOSCConfigSet
+#else
+#define MAP_SysCtlMOSCConfigSet                                               \
+        SysCtlMOSCConfigSet
+#endif
+#ifdef ROM_SysCtlPIOSCCalibrate
+#define MAP_SysCtlPIOSCCalibrate                                              \
+        ROM_SysCtlPIOSCCalibrate
+#else
+#define MAP_SysCtlPIOSCCalibrate                                              \
+        SysCtlPIOSCCalibrate
+#endif
+#ifdef ROM_SysCtlDeepSleepClockSet
+#define MAP_SysCtlDeepSleepClockSet                                           \
+        ROM_SysCtlDeepSleepClockSet
+#else
+#define MAP_SysCtlDeepSleepClockSet                                           \
+        SysCtlDeepSleepClockSet
+#endif
+#ifdef ROM_SysCtlDeepSleepClockConfigSet
+#define MAP_SysCtlDeepSleepClockConfigSet                                     \
+        ROM_SysCtlDeepSleepClockConfigSet
+#else
+#define MAP_SysCtlDeepSleepClockConfigSet                                     \
+        SysCtlDeepSleepClockConfigSet
+#endif
+#ifdef ROM_SysCtlClockFreqSet
+#define MAP_SysCtlClockFreqSet                                                \
+        ROM_SysCtlClockFreqSet
+#else
+#define MAP_SysCtlClockFreqSet                                                \
+        SysCtlClockFreqSet
+#endif
+#ifdef ROM_SysCtlResetBehaviorSet
+#define MAP_SysCtlResetBehaviorSet                                            \
+        ROM_SysCtlResetBehaviorSet
+#else
+#define MAP_SysCtlResetBehaviorSet                                            \
+        SysCtlResetBehaviorSet
+#endif
+#ifdef ROM_SysCtlResetBehaviorGet
+#define MAP_SysCtlResetBehaviorGet                                            \
+        ROM_SysCtlResetBehaviorGet
+#else
+#define MAP_SysCtlResetBehaviorGet                                            \
+        SysCtlResetBehaviorGet
+#endif
+#ifdef ROM_SysCtlFlashSectorSizeGet
+#define MAP_SysCtlFlashSectorSizeGet                                          \
+        ROM_SysCtlFlashSectorSizeGet
+#else
+#define MAP_SysCtlFlashSectorSizeGet                                          \
+        SysCtlFlashSectorSizeGet
+#endif
+#ifdef ROM_SysCtlVoltageEventConfig
+#define MAP_SysCtlVoltageEventConfig                                          \
+        ROM_SysCtlVoltageEventConfig
+#else
+#define MAP_SysCtlVoltageEventConfig                                          \
+        SysCtlVoltageEventConfig
+#endif
+#ifdef ROM_SysCtlVoltageEventStatus
+#define MAP_SysCtlVoltageEventStatus                                          \
+        ROM_SysCtlVoltageEventStatus
+#else
+#define MAP_SysCtlVoltageEventStatus                                          \
+        SysCtlVoltageEventStatus
+#endif
+#ifdef ROM_SysCtlVoltageEventClear
+#define MAP_SysCtlVoltageEventClear                                           \
+        ROM_SysCtlVoltageEventClear
+#else
+#define MAP_SysCtlVoltageEventClear                                           \
+        SysCtlVoltageEventClear
+#endif
+#ifdef ROM_SysCtlNMIStatus
+#define MAP_SysCtlNMIStatus                                                   \
+        ROM_SysCtlNMIStatus
+#else
+#define MAP_SysCtlNMIStatus                                                   \
+        SysCtlNMIStatus
+#endif
+#ifdef ROM_SysCtlNMIClear
+#define MAP_SysCtlNMIClear                                                    \
+        ROM_SysCtlNMIClear
+#else
+#define MAP_SysCtlNMIClear                                                    \
+        SysCtlNMIClear
+#endif
+#ifdef ROM_SysCtlClockOutConfig
+#define MAP_SysCtlClockOutConfig                                              \
+        ROM_SysCtlClockOutConfig
+#else
+#define MAP_SysCtlClockOutConfig                                              \
+        SysCtlClockOutConfig
+#endif
+#ifdef ROM_SysCtlAltClkConfig
+#define MAP_SysCtlAltClkConfig                                                \
+        ROM_SysCtlAltClkConfig
+#else
+#define MAP_SysCtlAltClkConfig                                                \
+        SysCtlAltClkConfig
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysExc API.
+//
+//*****************************************************************************
+#ifdef ROM_SysExcIntStatus
+#define MAP_SysExcIntStatus                                                   \
+        ROM_SysExcIntStatus
+#else
+#define MAP_SysExcIntStatus                                                   \
+        SysExcIntStatus
+#endif
+#ifdef ROM_SysExcIntClear
+#define MAP_SysExcIntClear                                                    \
+        ROM_SysExcIntClear
+#else
+#define MAP_SysExcIntClear                                                    \
+        SysExcIntClear
+#endif
+#ifdef ROM_SysExcIntDisable
+#define MAP_SysExcIntDisable                                                  \
+        ROM_SysExcIntDisable
+#else
+#define MAP_SysExcIntDisable                                                  \
+        SysExcIntDisable
+#endif
+#ifdef ROM_SysExcIntEnable
+#define MAP_SysExcIntEnable                                                   \
+        ROM_SysExcIntEnable
+#else
+#define MAP_SysExcIntEnable                                                   \
+        SysExcIntEnable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysTick API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTickValueGet
+#define MAP_SysTickValueGet                                                   \
+        ROM_SysTickValueGet
+#else
+#define MAP_SysTickValueGet                                                   \
+        SysTickValueGet
+#endif
+#ifdef ROM_SysTickEnable
+#define MAP_SysTickEnable                                                     \
+        ROM_SysTickEnable
+#else
+#define MAP_SysTickEnable                                                     \
+        SysTickEnable
+#endif
+#ifdef ROM_SysTickDisable
+#define MAP_SysTickDisable                                                    \
+        ROM_SysTickDisable
+#else
+#define MAP_SysTickDisable                                                    \
+        SysTickDisable
+#endif
+#ifdef ROM_SysTickIntEnable
+#define MAP_SysTickIntEnable                                                  \
+        ROM_SysTickIntEnable
+#else
+#define MAP_SysTickIntEnable                                                  \
+        SysTickIntEnable
+#endif
+#ifdef ROM_SysTickIntDisable
+#define MAP_SysTickIntDisable                                                 \
+        ROM_SysTickIntDisable
+#else
+#define MAP_SysTickIntDisable                                                 \
+        SysTickIntDisable
+#endif
+#ifdef ROM_SysTickPeriodSet
+#define MAP_SysTickPeriodSet                                                  \
+        ROM_SysTickPeriodSet
+#else
+#define MAP_SysTickPeriodSet                                                  \
+        SysTickPeriodSet
+#endif
+#ifdef ROM_SysTickPeriodGet
+#define MAP_SysTickPeriodGet                                                  \
+        ROM_SysTickPeriodGet
+#else
+#define MAP_SysTickPeriodGet                                                  \
+        SysTickPeriodGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer API.
+//
+//*****************************************************************************
+#ifdef ROM_TimerIntClear
+#define MAP_TimerIntClear                                                     \
+        ROM_TimerIntClear
+#else
+#define MAP_TimerIntClear                                                     \
+        TimerIntClear
+#endif
+#ifdef ROM_TimerEnable
+#define MAP_TimerEnable                                                       \
+        ROM_TimerEnable
+#else
+#define MAP_TimerEnable                                                       \
+        TimerEnable
+#endif
+#ifdef ROM_TimerDisable
+#define MAP_TimerDisable                                                      \
+        ROM_TimerDisable
+#else
+#define MAP_TimerDisable                                                      \
+        TimerDisable
+#endif
+#ifdef ROM_TimerConfigure
+#define MAP_TimerConfigure                                                    \
+        ROM_TimerConfigure
+#else
+#define MAP_TimerConfigure                                                    \
+        TimerConfigure
+#endif
+#ifdef ROM_TimerControlLevel
+#define MAP_TimerControlLevel                                                 \
+        ROM_TimerControlLevel
+#else
+#define MAP_TimerControlLevel                                                 \
+        TimerControlLevel
+#endif
+#ifdef ROM_TimerControlTrigger
+#define MAP_TimerControlTrigger                                               \
+        ROM_TimerControlTrigger
+#else
+#define MAP_TimerControlTrigger                                               \
+        TimerControlTrigger
+#endif
+#ifdef ROM_TimerControlEvent
+#define MAP_TimerControlEvent                                                 \
+        ROM_TimerControlEvent
+#else
+#define MAP_TimerControlEvent                                                 \
+        TimerControlEvent
+#endif
+#ifdef ROM_TimerControlStall
+#define MAP_TimerControlStall                                                 \
+        ROM_TimerControlStall
+#else
+#define MAP_TimerControlStall                                                 \
+        TimerControlStall
+#endif
+#ifdef ROM_TimerRTCEnable
+#define MAP_TimerRTCEnable                                                    \
+        ROM_TimerRTCEnable
+#else
+#define MAP_TimerRTCEnable                                                    \
+        TimerRTCEnable
+#endif
+#ifdef ROM_TimerRTCDisable
+#define MAP_TimerRTCDisable                                                   \
+        ROM_TimerRTCDisable
+#else
+#define MAP_TimerRTCDisable                                                   \
+        TimerRTCDisable
+#endif
+#ifdef ROM_TimerPrescaleSet
+#define MAP_TimerPrescaleSet                                                  \
+        ROM_TimerPrescaleSet
+#else
+#define MAP_TimerPrescaleSet                                                  \
+        TimerPrescaleSet
+#endif
+#ifdef ROM_TimerPrescaleGet
+#define MAP_TimerPrescaleGet                                                  \
+        ROM_TimerPrescaleGet
+#else
+#define MAP_TimerPrescaleGet                                                  \
+        TimerPrescaleGet
+#endif
+#ifdef ROM_TimerPrescaleMatchSet
+#define MAP_TimerPrescaleMatchSet                                             \
+        ROM_TimerPrescaleMatchSet
+#else
+#define MAP_TimerPrescaleMatchSet                                             \
+        TimerPrescaleMatchSet
+#endif
+#ifdef ROM_TimerPrescaleMatchGet
+#define MAP_TimerPrescaleMatchGet                                             \
+        ROM_TimerPrescaleMatchGet
+#else
+#define MAP_TimerPrescaleMatchGet                                             \
+        TimerPrescaleMatchGet
+#endif
+#ifdef ROM_TimerLoadSet
+#define MAP_TimerLoadSet                                                      \
+        ROM_TimerLoadSet
+#else
+#define MAP_TimerLoadSet                                                      \
+        TimerLoadSet
+#endif
+#ifdef ROM_TimerLoadGet
+#define MAP_TimerLoadGet                                                      \
+        ROM_TimerLoadGet
+#else
+#define MAP_TimerLoadGet                                                      \
+        TimerLoadGet
+#endif
+#ifdef ROM_TimerValueGet
+#define MAP_TimerValueGet                                                     \
+        ROM_TimerValueGet
+#else
+#define MAP_TimerValueGet                                                     \
+        TimerValueGet
+#endif
+#ifdef ROM_TimerMatchSet
+#define MAP_TimerMatchSet                                                     \
+        ROM_TimerMatchSet
+#else
+#define MAP_TimerMatchSet                                                     \
+        TimerMatchSet
+#endif
+#ifdef ROM_TimerMatchGet
+#define MAP_TimerMatchGet                                                     \
+        ROM_TimerMatchGet
+#else
+#define MAP_TimerMatchGet                                                     \
+        TimerMatchGet
+#endif
+#ifdef ROM_TimerIntEnable
+#define MAP_TimerIntEnable                                                    \
+        ROM_TimerIntEnable
+#else
+#define MAP_TimerIntEnable                                                    \
+        TimerIntEnable
+#endif
+#ifdef ROM_TimerIntDisable
+#define MAP_TimerIntDisable                                                   \
+        ROM_TimerIntDisable
+#else
+#define MAP_TimerIntDisable                                                   \
+        TimerIntDisable
+#endif
+#ifdef ROM_TimerIntStatus
+#define MAP_TimerIntStatus                                                    \
+        ROM_TimerIntStatus
+#else
+#define MAP_TimerIntStatus                                                    \
+        TimerIntStatus
+#endif
+#ifdef ROM_TimerControlWaitOnTrigger
+#define MAP_TimerControlWaitOnTrigger                                         \
+        ROM_TimerControlWaitOnTrigger
+#else
+#define MAP_TimerControlWaitOnTrigger                                         \
+        TimerControlWaitOnTrigger
+#endif
+#ifdef ROM_TimerLoadSet64
+#define MAP_TimerLoadSet64                                                    \
+        ROM_TimerLoadSet64
+#else
+#define MAP_TimerLoadSet64                                                    \
+        TimerLoadSet64
+#endif
+#ifdef ROM_TimerLoadGet64
+#define MAP_TimerLoadGet64                                                    \
+        ROM_TimerLoadGet64
+#else
+#define MAP_TimerLoadGet64                                                    \
+        TimerLoadGet64
+#endif
+#ifdef ROM_TimerValueGet64
+#define MAP_TimerValueGet64                                                   \
+        ROM_TimerValueGet64
+#else
+#define MAP_TimerValueGet64                                                   \
+        TimerValueGet64
+#endif
+#ifdef ROM_TimerMatchSet64
+#define MAP_TimerMatchSet64                                                   \
+        ROM_TimerMatchSet64
+#else
+#define MAP_TimerMatchSet64                                                   \
+        TimerMatchSet64
+#endif
+#ifdef ROM_TimerMatchGet64
+#define MAP_TimerMatchGet64                                                   \
+        ROM_TimerMatchGet64
+#else
+#define MAP_TimerMatchGet64                                                   \
+        TimerMatchGet64
+#endif
+#ifdef ROM_TimerClockSourceGet
+#define MAP_TimerClockSourceGet                                               \
+        ROM_TimerClockSourceGet
+#else
+#define MAP_TimerClockSourceGet                                               \
+        TimerClockSourceGet
+#endif
+#ifdef ROM_TimerClockSourceSet
+#define MAP_TimerClockSourceSet                                               \
+        ROM_TimerClockSourceSet
+#else
+#define MAP_TimerClockSourceSet                                               \
+        TimerClockSourceSet
+#endif
+#ifdef ROM_TimerADCEventGet
+#define MAP_TimerADCEventGet                                                  \
+        ROM_TimerADCEventGet
+#else
+#define MAP_TimerADCEventGet                                                  \
+        TimerADCEventGet
+#endif
+#ifdef ROM_TimerADCEventSet
+#define MAP_TimerADCEventSet                                                  \
+        ROM_TimerADCEventSet
+#else
+#define MAP_TimerADCEventSet                                                  \
+        TimerADCEventSet
+#endif
+#ifdef ROM_TimerDMAEventGet
+#define MAP_TimerDMAEventGet                                                  \
+        ROM_TimerDMAEventGet
+#else
+#define MAP_TimerDMAEventGet                                                  \
+        TimerDMAEventGet
+#endif
+#ifdef ROM_TimerDMAEventSet
+#define MAP_TimerDMAEventSet                                                  \
+        ROM_TimerDMAEventSet
+#else
+#define MAP_TimerDMAEventSet                                                  \
+        TimerDMAEventSet
+#endif
+#ifdef ROM_TimerSynchronize
+#define MAP_TimerSynchronize                                                  \
+        ROM_TimerSynchronize
+#else
+#define MAP_TimerSynchronize                                                  \
+        TimerSynchronize
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UARTCharPut
+#define MAP_UARTCharPut                                                       \
+        ROM_UARTCharPut
+#else
+#define MAP_UARTCharPut                                                       \
+        UARTCharPut
+#endif
+#ifdef ROM_UARTParityModeSet
+#define MAP_UARTParityModeSet                                                 \
+        ROM_UARTParityModeSet
+#else
+#define MAP_UARTParityModeSet                                                 \
+        UARTParityModeSet
+#endif
+#ifdef ROM_UARTParityModeGet
+#define MAP_UARTParityModeGet                                                 \
+        ROM_UARTParityModeGet
+#else
+#define MAP_UARTParityModeGet                                                 \
+        UARTParityModeGet
+#endif
+#ifdef ROM_UARTFIFOLevelSet
+#define MAP_UARTFIFOLevelSet                                                  \
+        ROM_UARTFIFOLevelSet
+#else
+#define MAP_UARTFIFOLevelSet                                                  \
+        UARTFIFOLevelSet
+#endif
+#ifdef ROM_UARTFIFOLevelGet
+#define MAP_UARTFIFOLevelGet                                                  \
+        ROM_UARTFIFOLevelGet
+#else
+#define MAP_UARTFIFOLevelGet                                                  \
+        UARTFIFOLevelGet
+#endif
+#ifdef ROM_UARTConfigSetExpClk
+#define MAP_UARTConfigSetExpClk                                               \
+        ROM_UARTConfigSetExpClk
+#else
+#define MAP_UARTConfigSetExpClk                                               \
+        UARTConfigSetExpClk
+#endif
+#ifdef ROM_UARTConfigGetExpClk
+#define MAP_UARTConfigGetExpClk                                               \
+        ROM_UARTConfigGetExpClk
+#else
+#define MAP_UARTConfigGetExpClk                                               \
+        UARTConfigGetExpClk
+#endif
+#ifdef ROM_UARTEnable
+#define MAP_UARTEnable                                                        \
+        ROM_UARTEnable
+#else
+#define MAP_UARTEnable                                                        \
+        UARTEnable
+#endif
+#ifdef ROM_UARTDisable
+#define MAP_UARTDisable                                                       \
+        ROM_UARTDisable
+#else
+#define MAP_UARTDisable                                                       \
+        UARTDisable
+#endif
+#ifdef ROM_UARTEnableSIR
+#define MAP_UARTEnableSIR                                                     \
+        ROM_UARTEnableSIR
+#else
+#define MAP_UARTEnableSIR                                                     \
+        UARTEnableSIR
+#endif
+#ifdef ROM_UARTDisableSIR
+#define MAP_UARTDisableSIR                                                    \
+        ROM_UARTDisableSIR
+#else
+#define MAP_UARTDisableSIR                                                    \
+        UARTDisableSIR
+#endif
+#ifdef ROM_UARTCharsAvail
+#define MAP_UARTCharsAvail                                                    \
+        ROM_UARTCharsAvail
+#else
+#define MAP_UARTCharsAvail                                                    \
+        UARTCharsAvail
+#endif
+#ifdef ROM_UARTSpaceAvail
+#define MAP_UARTSpaceAvail                                                    \
+        ROM_UARTSpaceAvail
+#else
+#define MAP_UARTSpaceAvail                                                    \
+        UARTSpaceAvail
+#endif
+#ifdef ROM_UARTCharGetNonBlocking
+#define MAP_UARTCharGetNonBlocking                                            \
+        ROM_UARTCharGetNonBlocking
+#else
+#define MAP_UARTCharGetNonBlocking                                            \
+        UARTCharGetNonBlocking
+#endif
+#ifdef ROM_UARTCharGet
+#define MAP_UARTCharGet                                                       \
+        ROM_UARTCharGet
+#else
+#define MAP_UARTCharGet                                                       \
+        UARTCharGet
+#endif
+#ifdef ROM_UARTCharPutNonBlocking
+#define MAP_UARTCharPutNonBlocking                                            \
+        ROM_UARTCharPutNonBlocking
+#else
+#define MAP_UARTCharPutNonBlocking                                            \
+        UARTCharPutNonBlocking
+#endif
+#ifdef ROM_UARTBreakCtl
+#define MAP_UARTBreakCtl                                                      \
+        ROM_UARTBreakCtl
+#else
+#define MAP_UARTBreakCtl                                                      \
+        UARTBreakCtl
+#endif
+#ifdef ROM_UARTIntEnable
+#define MAP_UARTIntEnable                                                     \
+        ROM_UARTIntEnable
+#else
+#define MAP_UARTIntEnable                                                     \
+        UARTIntEnable
+#endif
+#ifdef ROM_UARTIntDisable
+#define MAP_UARTIntDisable                                                    \
+        ROM_UARTIntDisable
+#else
+#define MAP_UARTIntDisable                                                    \
+        UARTIntDisable
+#endif
+#ifdef ROM_UARTIntStatus
+#define MAP_UARTIntStatus                                                     \
+        ROM_UARTIntStatus
+#else
+#define MAP_UARTIntStatus                                                     \
+        UARTIntStatus
+#endif
+#ifdef ROM_UARTIntClear
+#define MAP_UARTIntClear                                                      \
+        ROM_UARTIntClear
+#else
+#define MAP_UARTIntClear                                                      \
+        UARTIntClear
+#endif
+#ifdef ROM_UARTDMAEnable
+#define MAP_UARTDMAEnable                                                     \
+        ROM_UARTDMAEnable
+#else
+#define MAP_UARTDMAEnable                                                     \
+        UARTDMAEnable
+#endif
+#ifdef ROM_UARTDMADisable
+#define MAP_UARTDMADisable                                                    \
+        ROM_UARTDMADisable
+#else
+#define MAP_UARTDMADisable                                                    \
+        UARTDMADisable
+#endif
+#ifdef ROM_UARTFIFOEnable
+#define MAP_UARTFIFOEnable                                                    \
+        ROM_UARTFIFOEnable
+#else
+#define MAP_UARTFIFOEnable                                                    \
+        UARTFIFOEnable
+#endif
+#ifdef ROM_UARTFIFODisable
+#define MAP_UARTFIFODisable                                                   \
+        ROM_UARTFIFODisable
+#else
+#define MAP_UARTFIFODisable                                                   \
+        UARTFIFODisable
+#endif
+#ifdef ROM_UARTBusy
+#define MAP_UARTBusy                                                          \
+        ROM_UARTBusy
+#else
+#define MAP_UARTBusy                                                          \
+        UARTBusy
+#endif
+#ifdef ROM_UARTTxIntModeSet
+#define MAP_UARTTxIntModeSet                                                  \
+        ROM_UARTTxIntModeSet
+#else
+#define MAP_UARTTxIntModeSet                                                  \
+        UARTTxIntModeSet
+#endif
+#ifdef ROM_UARTTxIntModeGet
+#define MAP_UARTTxIntModeGet                                                  \
+        ROM_UARTTxIntModeGet
+#else
+#define MAP_UARTTxIntModeGet                                                  \
+        UARTTxIntModeGet
+#endif
+#ifdef ROM_UARTRxErrorGet
+#define MAP_UARTRxErrorGet                                                    \
+        ROM_UARTRxErrorGet
+#else
+#define MAP_UARTRxErrorGet                                                    \
+        UARTRxErrorGet
+#endif
+#ifdef ROM_UARTRxErrorClear
+#define MAP_UARTRxErrorClear                                                  \
+        ROM_UARTRxErrorClear
+#else
+#define MAP_UARTRxErrorClear                                                  \
+        UARTRxErrorClear
+#endif
+#ifdef ROM_UARTClockSourceSet
+#define MAP_UARTClockSourceSet                                                \
+        ROM_UARTClockSourceSet
+#else
+#define MAP_UARTClockSourceSet                                                \
+        UARTClockSourceSet
+#endif
+#ifdef ROM_UARTClockSourceGet
+#define MAP_UARTClockSourceGet                                                \
+        ROM_UARTClockSourceGet
+#else
+#define MAP_UARTClockSourceGet                                                \
+        UARTClockSourceGet
+#endif
+#ifdef ROM_UART9BitEnable
+#define MAP_UART9BitEnable                                                    \
+        ROM_UART9BitEnable
+#else
+#define MAP_UART9BitEnable                                                    \
+        UART9BitEnable
+#endif
+#ifdef ROM_UART9BitDisable
+#define MAP_UART9BitDisable                                                   \
+        ROM_UART9BitDisable
+#else
+#define MAP_UART9BitDisable                                                   \
+        UART9BitDisable
+#endif
+#ifdef ROM_UART9BitAddrSet
+#define MAP_UART9BitAddrSet                                                   \
+        ROM_UART9BitAddrSet
+#else
+#define MAP_UART9BitAddrSet                                                   \
+        UART9BitAddrSet
+#endif
+#ifdef ROM_UART9BitAddrSend
+#define MAP_UART9BitAddrSend                                                  \
+        ROM_UART9BitAddrSend
+#else
+#define MAP_UART9BitAddrSend                                                  \
+        UART9BitAddrSend
+#endif
+#ifdef ROM_UARTSmartCardDisable
+#define MAP_UARTSmartCardDisable                                              \
+        ROM_UARTSmartCardDisable
+#else
+#define MAP_UARTSmartCardDisable                                              \
+        UARTSmartCardDisable
+#endif
+#ifdef ROM_UARTSmartCardEnable
+#define MAP_UARTSmartCardEnable                                               \
+        ROM_UARTSmartCardEnable
+#else
+#define MAP_UARTSmartCardEnable                                               \
+        UARTSmartCardEnable
+#endif
+#ifdef ROM_UARTModemControlClear
+#define MAP_UARTModemControlClear                                             \
+        ROM_UARTModemControlClear
+#else
+#define MAP_UARTModemControlClear                                             \
+        UARTModemControlClear
+#endif
+#ifdef ROM_UARTModemControlGet
+#define MAP_UARTModemControlGet                                               \
+        ROM_UARTModemControlGet
+#else
+#define MAP_UARTModemControlGet                                               \
+        UARTModemControlGet
+#endif
+#ifdef ROM_UARTModemControlSet
+#define MAP_UARTModemControlSet                                               \
+        ROM_UARTModemControlSet
+#else
+#define MAP_UARTModemControlSet                                               \
+        UARTModemControlSet
+#endif
+#ifdef ROM_UARTModemStatusGet
+#define MAP_UARTModemStatusGet                                                \
+        ROM_UARTModemStatusGet
+#else
+#define MAP_UARTModemStatusGet                                                \
+        UARTModemStatusGet
+#endif
+#ifdef ROM_UARTFlowControlGet
+#define MAP_UARTFlowControlGet                                                \
+        ROM_UARTFlowControlGet
+#else
+#define MAP_UARTFlowControlGet                                                \
+        UARTFlowControlGet
+#endif
+#ifdef ROM_UARTFlowControlSet
+#define MAP_UARTFlowControlSet                                                \
+        ROM_UARTFlowControlSet
+#else
+#define MAP_UARTFlowControlSet                                                \
+        UARTFlowControlSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the uDMA API.
+//
+//*****************************************************************************
+#ifdef ROM_uDMAChannelTransferSet
+#define MAP_uDMAChannelTransferSet                                            \
+        ROM_uDMAChannelTransferSet
+#else
+#define MAP_uDMAChannelTransferSet                                            \
+        uDMAChannelTransferSet
+#endif
+#ifdef ROM_uDMAEnable
+#define MAP_uDMAEnable                                                        \
+        ROM_uDMAEnable
+#else
+#define MAP_uDMAEnable                                                        \
+        uDMAEnable
+#endif
+#ifdef ROM_uDMADisable
+#define MAP_uDMADisable                                                       \
+        ROM_uDMADisable
+#else
+#define MAP_uDMADisable                                                       \
+        uDMADisable
+#endif
+#ifdef ROM_uDMAErrorStatusGet
+#define MAP_uDMAErrorStatusGet                                                \
+        ROM_uDMAErrorStatusGet
+#else
+#define MAP_uDMAErrorStatusGet                                                \
+        uDMAErrorStatusGet
+#endif
+#ifdef ROM_uDMAErrorStatusClear
+#define MAP_uDMAErrorStatusClear                                              \
+        ROM_uDMAErrorStatusClear
+#else
+#define MAP_uDMAErrorStatusClear                                              \
+        uDMAErrorStatusClear
+#endif
+#ifdef ROM_uDMAChannelEnable
+#define MAP_uDMAChannelEnable                                                 \
+        ROM_uDMAChannelEnable
+#else
+#define MAP_uDMAChannelEnable                                                 \
+        uDMAChannelEnable
+#endif
+#ifdef ROM_uDMAChannelDisable
+#define MAP_uDMAChannelDisable                                                \
+        ROM_uDMAChannelDisable
+#else
+#define MAP_uDMAChannelDisable                                                \
+        uDMAChannelDisable
+#endif
+#ifdef ROM_uDMAChannelIsEnabled
+#define MAP_uDMAChannelIsEnabled                                              \
+        ROM_uDMAChannelIsEnabled
+#else
+#define MAP_uDMAChannelIsEnabled                                              \
+        uDMAChannelIsEnabled
+#endif
+#ifdef ROM_uDMAControlBaseSet
+#define MAP_uDMAControlBaseSet                                                \
+        ROM_uDMAControlBaseSet
+#else
+#define MAP_uDMAControlBaseSet                                                \
+        uDMAControlBaseSet
+#endif
+#ifdef ROM_uDMAControlBaseGet
+#define MAP_uDMAControlBaseGet                                                \
+        ROM_uDMAControlBaseGet
+#else
+#define MAP_uDMAControlBaseGet                                                \
+        uDMAControlBaseGet
+#endif
+#ifdef ROM_uDMAChannelRequest
+#define MAP_uDMAChannelRequest                                                \
+        ROM_uDMAChannelRequest
+#else
+#define MAP_uDMAChannelRequest                                                \
+        uDMAChannelRequest
+#endif
+#ifdef ROM_uDMAChannelAttributeEnable
+#define MAP_uDMAChannelAttributeEnable                                        \
+        ROM_uDMAChannelAttributeEnable
+#else
+#define MAP_uDMAChannelAttributeEnable                                        \
+        uDMAChannelAttributeEnable
+#endif
+#ifdef ROM_uDMAChannelAttributeDisable
+#define MAP_uDMAChannelAttributeDisable                                       \
+        ROM_uDMAChannelAttributeDisable
+#else
+#define MAP_uDMAChannelAttributeDisable                                       \
+        uDMAChannelAttributeDisable
+#endif
+#ifdef ROM_uDMAChannelAttributeGet
+#define MAP_uDMAChannelAttributeGet                                           \
+        ROM_uDMAChannelAttributeGet
+#else
+#define MAP_uDMAChannelAttributeGet                                           \
+        uDMAChannelAttributeGet
+#endif
+#ifdef ROM_uDMAChannelControlSet
+#define MAP_uDMAChannelControlSet                                             \
+        ROM_uDMAChannelControlSet
+#else
+#define MAP_uDMAChannelControlSet                                             \
+        uDMAChannelControlSet
+#endif
+#ifdef ROM_uDMAChannelSizeGet
+#define MAP_uDMAChannelSizeGet                                                \
+        ROM_uDMAChannelSizeGet
+#else
+#define MAP_uDMAChannelSizeGet                                                \
+        uDMAChannelSizeGet
+#endif
+#ifdef ROM_uDMAChannelModeGet
+#define MAP_uDMAChannelModeGet                                                \
+        ROM_uDMAChannelModeGet
+#else
+#define MAP_uDMAChannelModeGet                                                \
+        uDMAChannelModeGet
+#endif
+#ifdef ROM_uDMAChannelSelectSecondary
+#define MAP_uDMAChannelSelectSecondary                                        \
+        ROM_uDMAChannelSelectSecondary
+#else
+#define MAP_uDMAChannelSelectSecondary                                        \
+        uDMAChannelSelectSecondary
+#endif
+#ifdef ROM_uDMAChannelSelectDefault
+#define MAP_uDMAChannelSelectDefault                                          \
+        ROM_uDMAChannelSelectDefault
+#else
+#define MAP_uDMAChannelSelectDefault                                          \
+        uDMAChannelSelectDefault
+#endif
+#ifdef ROM_uDMAIntStatus
+#define MAP_uDMAIntStatus                                                     \
+        ROM_uDMAIntStatus
+#else
+#define MAP_uDMAIntStatus                                                     \
+        uDMAIntStatus
+#endif
+#ifdef ROM_uDMAIntClear
+#define MAP_uDMAIntClear                                                      \
+        ROM_uDMAIntClear
+#else
+#define MAP_uDMAIntClear                                                      \
+        uDMAIntClear
+#endif
+#ifdef ROM_uDMAControlAlternateBaseGet
+#define MAP_uDMAControlAlternateBaseGet                                       \
+        ROM_uDMAControlAlternateBaseGet
+#else
+#define MAP_uDMAControlAlternateBaseGet                                       \
+        uDMAControlAlternateBaseGet
+#endif
+#ifdef ROM_uDMAChannelScatterGatherSet
+#define MAP_uDMAChannelScatterGatherSet                                       \
+        ROM_uDMAChannelScatterGatherSet
+#else
+#define MAP_uDMAChannelScatterGatherSet                                       \
+        uDMAChannelScatterGatherSet
+#endif
+#ifdef ROM_uDMAChannelAssign
+#define MAP_uDMAChannelAssign                                                 \
+        ROM_uDMAChannelAssign
+#else
+#define MAP_uDMAChannelAssign                                                 \
+        uDMAChannelAssign
+#endif
+
+//*****************************************************************************
+//
+// Macros for the USB API.
+//
+//*****************************************************************************
+#ifdef ROM_USBDevAddrGet
+#define MAP_USBDevAddrGet                                                     \
+        ROM_USBDevAddrGet
+#else
+#define MAP_USBDevAddrGet                                                     \
+        USBDevAddrGet
+#endif
+#ifdef ROM_USBDevAddrSet
+#define MAP_USBDevAddrSet                                                     \
+        ROM_USBDevAddrSet
+#else
+#define MAP_USBDevAddrSet                                                     \
+        USBDevAddrSet
+#endif
+#ifdef ROM_USBDevConnect
+#define MAP_USBDevConnect                                                     \
+        ROM_USBDevConnect
+#else
+#define MAP_USBDevConnect                                                     \
+        USBDevConnect
+#endif
+#ifdef ROM_USBDevDisconnect
+#define MAP_USBDevDisconnect                                                  \
+        ROM_USBDevDisconnect
+#else
+#define MAP_USBDevDisconnect                                                  \
+        USBDevDisconnect
+#endif
+#ifdef ROM_USBDevEndpointConfigSet
+#define MAP_USBDevEndpointConfigSet                                           \
+        ROM_USBDevEndpointConfigSet
+#else
+#define MAP_USBDevEndpointConfigSet                                           \
+        USBDevEndpointConfigSet
+#endif
+#ifdef ROM_USBDevEndpointDataAck
+#define MAP_USBDevEndpointDataAck                                             \
+        ROM_USBDevEndpointDataAck
+#else
+#define MAP_USBDevEndpointDataAck                                             \
+        USBDevEndpointDataAck
+#endif
+#ifdef ROM_USBDevEndpointStall
+#define MAP_USBDevEndpointStall                                               \
+        ROM_USBDevEndpointStall
+#else
+#define MAP_USBDevEndpointStall                                               \
+        USBDevEndpointStall
+#endif
+#ifdef ROM_USBDevEndpointStallClear
+#define MAP_USBDevEndpointStallClear                                          \
+        ROM_USBDevEndpointStallClear
+#else
+#define MAP_USBDevEndpointStallClear                                          \
+        USBDevEndpointStallClear
+#endif
+#ifdef ROM_USBDevEndpointStatusClear
+#define MAP_USBDevEndpointStatusClear                                         \
+        ROM_USBDevEndpointStatusClear
+#else
+#define MAP_USBDevEndpointStatusClear                                         \
+        USBDevEndpointStatusClear
+#endif
+#ifdef ROM_USBEndpointDataGet
+#define MAP_USBEndpointDataGet                                                \
+        ROM_USBEndpointDataGet
+#else
+#define MAP_USBEndpointDataGet                                                \
+        USBEndpointDataGet
+#endif
+#ifdef ROM_USBEndpointDataPut
+#define MAP_USBEndpointDataPut                                                \
+        ROM_USBEndpointDataPut
+#else
+#define MAP_USBEndpointDataPut                                                \
+        USBEndpointDataPut
+#endif
+#ifdef ROM_USBEndpointDataSend
+#define MAP_USBEndpointDataSend                                               \
+        ROM_USBEndpointDataSend
+#else
+#define MAP_USBEndpointDataSend                                               \
+        USBEndpointDataSend
+#endif
+#ifdef ROM_USBEndpointDataToggleClear
+#define MAP_USBEndpointDataToggleClear                                        \
+        ROM_USBEndpointDataToggleClear
+#else
+#define MAP_USBEndpointDataToggleClear                                        \
+        USBEndpointDataToggleClear
+#endif
+#ifdef ROM_USBEndpointStatus
+#define MAP_USBEndpointStatus                                                 \
+        ROM_USBEndpointStatus
+#else
+#define MAP_USBEndpointStatus                                                 \
+        USBEndpointStatus
+#endif
+#ifdef ROM_USBFIFOAddrGet
+#define MAP_USBFIFOAddrGet                                                    \
+        ROM_USBFIFOAddrGet
+#else
+#define MAP_USBFIFOAddrGet                                                    \
+        USBFIFOAddrGet
+#endif
+#ifdef ROM_USBFIFOConfigGet
+#define MAP_USBFIFOConfigGet                                                  \
+        ROM_USBFIFOConfigGet
+#else
+#define MAP_USBFIFOConfigGet                                                  \
+        USBFIFOConfigGet
+#endif
+#ifdef ROM_USBFIFOConfigSet
+#define MAP_USBFIFOConfigSet                                                  \
+        ROM_USBFIFOConfigSet
+#else
+#define MAP_USBFIFOConfigSet                                                  \
+        USBFIFOConfigSet
+#endif
+#ifdef ROM_USBFIFOFlush
+#define MAP_USBFIFOFlush                                                      \
+        ROM_USBFIFOFlush
+#else
+#define MAP_USBFIFOFlush                                                      \
+        USBFIFOFlush
+#endif
+#ifdef ROM_USBFrameNumberGet
+#define MAP_USBFrameNumberGet                                                 \
+        ROM_USBFrameNumberGet
+#else
+#define MAP_USBFrameNumberGet                                                 \
+        USBFrameNumberGet
+#endif
+#ifdef ROM_USBHostAddrGet
+#define MAP_USBHostAddrGet                                                    \
+        ROM_USBHostAddrGet
+#else
+#define MAP_USBHostAddrGet                                                    \
+        USBHostAddrGet
+#endif
+#ifdef ROM_USBHostAddrSet
+#define MAP_USBHostAddrSet                                                    \
+        ROM_USBHostAddrSet
+#else
+#define MAP_USBHostAddrSet                                                    \
+        USBHostAddrSet
+#endif
+#ifdef ROM_USBHostEndpointConfig
+#define MAP_USBHostEndpointConfig                                             \
+        ROM_USBHostEndpointConfig
+#else
+#define MAP_USBHostEndpointConfig                                             \
+        USBHostEndpointConfig
+#endif
+#ifdef ROM_USBHostEndpointDataAck
+#define MAP_USBHostEndpointDataAck                                            \
+        ROM_USBHostEndpointDataAck
+#else
+#define MAP_USBHostEndpointDataAck                                            \
+        USBHostEndpointDataAck
+#endif
+#ifdef ROM_USBHostEndpointDataToggle
+#define MAP_USBHostEndpointDataToggle                                         \
+        ROM_USBHostEndpointDataToggle
+#else
+#define MAP_USBHostEndpointDataToggle                                         \
+        USBHostEndpointDataToggle
+#endif
+#ifdef ROM_USBHostEndpointStatusClear
+#define MAP_USBHostEndpointStatusClear                                        \
+        ROM_USBHostEndpointStatusClear
+#else
+#define MAP_USBHostEndpointStatusClear                                        \
+        USBHostEndpointStatusClear
+#endif
+#ifdef ROM_USBHostHubAddrGet
+#define MAP_USBHostHubAddrGet                                                 \
+        ROM_USBHostHubAddrGet
+#else
+#define MAP_USBHostHubAddrGet                                                 \
+        USBHostHubAddrGet
+#endif
+#ifdef ROM_USBHostHubAddrSet
+#define MAP_USBHostHubAddrSet                                                 \
+        ROM_USBHostHubAddrSet
+#else
+#define MAP_USBHostHubAddrSet                                                 \
+        USBHostHubAddrSet
+#endif
+#ifdef ROM_USBHostPwrDisable
+#define MAP_USBHostPwrDisable                                                 \
+        ROM_USBHostPwrDisable
+#else
+#define MAP_USBHostPwrDisable                                                 \
+        USBHostPwrDisable
+#endif
+#ifdef ROM_USBHostPwrEnable
+#define MAP_USBHostPwrEnable                                                  \
+        ROM_USBHostPwrEnable
+#else
+#define MAP_USBHostPwrEnable                                                  \
+        USBHostPwrEnable
+#endif
+#ifdef ROM_USBHostPwrConfig
+#define MAP_USBHostPwrConfig                                                  \
+        ROM_USBHostPwrConfig
+#else
+#define MAP_USBHostPwrConfig                                                  \
+        USBHostPwrConfig
+#endif
+#ifdef ROM_USBHostPwrFaultDisable
+#define MAP_USBHostPwrFaultDisable                                            \
+        ROM_USBHostPwrFaultDisable
+#else
+#define MAP_USBHostPwrFaultDisable                                            \
+        USBHostPwrFaultDisable
+#endif
+#ifdef ROM_USBHostPwrFaultEnable
+#define MAP_USBHostPwrFaultEnable                                             \
+        ROM_USBHostPwrFaultEnable
+#else
+#define MAP_USBHostPwrFaultEnable                                             \
+        USBHostPwrFaultEnable
+#endif
+#ifdef ROM_USBHostRequestIN
+#define MAP_USBHostRequestIN                                                  \
+        ROM_USBHostRequestIN
+#else
+#define MAP_USBHostRequestIN                                                  \
+        USBHostRequestIN
+#endif
+#ifdef ROM_USBHostRequestStatus
+#define MAP_USBHostRequestStatus                                              \
+        ROM_USBHostRequestStatus
+#else
+#define MAP_USBHostRequestStatus                                              \
+        USBHostRequestStatus
+#endif
+#ifdef ROM_USBHostReset
+#define MAP_USBHostReset                                                      \
+        ROM_USBHostReset
+#else
+#define MAP_USBHostReset                                                      \
+        USBHostReset
+#endif
+#ifdef ROM_USBHostResume
+#define MAP_USBHostResume                                                     \
+        ROM_USBHostResume
+#else
+#define MAP_USBHostResume                                                     \
+        USBHostResume
+#endif
+#ifdef ROM_USBHostSpeedGet
+#define MAP_USBHostSpeedGet                                                   \
+        ROM_USBHostSpeedGet
+#else
+#define MAP_USBHostSpeedGet                                                   \
+        USBHostSpeedGet
+#endif
+#ifdef ROM_USBHostSuspend
+#define MAP_USBHostSuspend                                                    \
+        ROM_USBHostSuspend
+#else
+#define MAP_USBHostSuspend                                                    \
+        USBHostSuspend
+#endif
+#ifdef ROM_USBDevEndpointConfigGet
+#define MAP_USBDevEndpointConfigGet                                           \
+        ROM_USBDevEndpointConfigGet
+#else
+#define MAP_USBDevEndpointConfigGet                                           \
+        USBDevEndpointConfigGet
+#endif
+#ifdef ROM_USBEndpointDMAEnable
+#define MAP_USBEndpointDMAEnable                                              \
+        ROM_USBEndpointDMAEnable
+#else
+#define MAP_USBEndpointDMAEnable                                              \
+        USBEndpointDMAEnable
+#endif
+#ifdef ROM_USBEndpointDMADisable
+#define MAP_USBEndpointDMADisable                                             \
+        ROM_USBEndpointDMADisable
+#else
+#define MAP_USBEndpointDMADisable                                             \
+        USBEndpointDMADisable
+#endif
+#ifdef ROM_USBEndpointDataAvail
+#define MAP_USBEndpointDataAvail                                              \
+        ROM_USBEndpointDataAvail
+#else
+#define MAP_USBEndpointDataAvail                                              \
+        USBEndpointDataAvail
+#endif
+#ifdef ROM_USBOTGHostRequest
+#define MAP_USBOTGHostRequest                                                 \
+        ROM_USBOTGHostRequest
+#else
+#define MAP_USBOTGHostRequest                                                 \
+        USBOTGHostRequest
+#endif
+#ifdef ROM_USBModeGet
+#define MAP_USBModeGet                                                        \
+        ROM_USBModeGet
+#else
+#define MAP_USBModeGet                                                        \
+        USBModeGet
+#endif
+#ifdef ROM_USBEndpointDMAChannel
+#define MAP_USBEndpointDMAChannel                                             \
+        ROM_USBEndpointDMAChannel
+#else
+#define MAP_USBEndpointDMAChannel                                             \
+        USBEndpointDMAChannel
+#endif
+#ifdef ROM_USBIntDisableControl
+#define MAP_USBIntDisableControl                                              \
+        ROM_USBIntDisableControl
+#else
+#define MAP_USBIntDisableControl                                              \
+        USBIntDisableControl
+#endif
+#ifdef ROM_USBIntEnableControl
+#define MAP_USBIntEnableControl                                               \
+        ROM_USBIntEnableControl
+#else
+#define MAP_USBIntEnableControl                                               \
+        USBIntEnableControl
+#endif
+#ifdef ROM_USBIntStatusControl
+#define MAP_USBIntStatusControl                                               \
+        ROM_USBIntStatusControl
+#else
+#define MAP_USBIntStatusControl                                               \
+        USBIntStatusControl
+#endif
+#ifdef ROM_USBIntDisableEndpoint
+#define MAP_USBIntDisableEndpoint                                             \
+        ROM_USBIntDisableEndpoint
+#else
+#define MAP_USBIntDisableEndpoint                                             \
+        USBIntDisableEndpoint
+#endif
+#ifdef ROM_USBIntEnableEndpoint
+#define MAP_USBIntEnableEndpoint                                              \
+        ROM_USBIntEnableEndpoint
+#else
+#define MAP_USBIntEnableEndpoint                                              \
+        USBIntEnableEndpoint
+#endif
+#ifdef ROM_USBIntStatusEndpoint
+#define MAP_USBIntStatusEndpoint                                              \
+        ROM_USBIntStatusEndpoint
+#else
+#define MAP_USBIntStatusEndpoint                                              \
+        USBIntStatusEndpoint
+#endif
+#ifdef ROM_USBHostMode
+#define MAP_USBHostMode                                                       \
+        ROM_USBHostMode
+#else
+#define MAP_USBHostMode                                                       \
+        USBHostMode
+#endif
+#ifdef ROM_USBDevMode
+#define MAP_USBDevMode                                                        \
+        ROM_USBDevMode
+#else
+#define MAP_USBDevMode                                                        \
+        USBDevMode
+#endif
+#ifdef ROM_USBPHYPowerOff
+#define MAP_USBPHYPowerOff                                                    \
+        ROM_USBPHYPowerOff
+#else
+#define MAP_USBPHYPowerOff                                                    \
+        USBPHYPowerOff
+#endif
+#ifdef ROM_USBPHYPowerOn
+#define MAP_USBPHYPowerOn                                                     \
+        ROM_USBPHYPowerOn
+#else
+#define MAP_USBPHYPowerOn                                                     \
+        USBPHYPowerOn
+#endif
+#ifdef ROM_USBOTGMode
+#define MAP_USBOTGMode                                                        \
+        ROM_USBOTGMode
+#else
+#define MAP_USBOTGMode                                                        \
+        USBOTGMode
+#endif
+#ifdef ROM_USBHostRequestINClear
+#define MAP_USBHostRequestINClear                                             \
+        ROM_USBHostRequestINClear
+#else
+#define MAP_USBHostRequestINClear                                             \
+        USBHostRequestINClear
+#endif
+#ifdef ROM_USBNumEndpointsGet
+#define MAP_USBNumEndpointsGet                                                \
+        ROM_USBNumEndpointsGet
+#else
+#define MAP_USBNumEndpointsGet                                                \
+        USBNumEndpointsGet
+#endif
+#ifdef ROM_USBClockDisable
+#define MAP_USBClockDisable                                                   \
+        ROM_USBClockDisable
+#else
+#define MAP_USBClockDisable                                                   \
+        USBClockDisable
+#endif
+#ifdef ROM_USBClockEnable
+#define MAP_USBClockEnable                                                    \
+        ROM_USBClockEnable
+#else
+#define MAP_USBClockEnable                                                    \
+        USBClockEnable
+#endif
+#ifdef ROM_USBControllerVersion
+#define MAP_USBControllerVersion                                              \
+        ROM_USBControllerVersion
+#else
+#define MAP_USBControllerVersion                                              \
+        USBControllerVersion
+#endif
+#ifdef ROM_USBDevLPMConfig
+#define MAP_USBDevLPMConfig                                                   \
+        ROM_USBDevLPMConfig
+#else
+#define MAP_USBDevLPMConfig                                                   \
+        USBDevLPMConfig
+#endif
+#ifdef ROM_USBDevLPMDisable
+#define MAP_USBDevLPMDisable                                                  \
+        ROM_USBDevLPMDisable
+#else
+#define MAP_USBDevLPMDisable                                                  \
+        USBDevLPMDisable
+#endif
+#ifdef ROM_USBDevLPMEnable
+#define MAP_USBDevLPMEnable                                                   \
+        ROM_USBDevLPMEnable
+#else
+#define MAP_USBDevLPMEnable                                                   \
+        USBDevLPMEnable
+#endif
+#ifdef ROM_USBDevLPMRemoteWake
+#define MAP_USBDevLPMRemoteWake                                               \
+        ROM_USBDevLPMRemoteWake
+#else
+#define MAP_USBDevLPMRemoteWake                                               \
+        USBDevLPMRemoteWake
+#endif
+#ifdef ROM_USBDevSpeedGet
+#define MAP_USBDevSpeedGet                                                    \
+        ROM_USBDevSpeedGet
+#else
+#define MAP_USBDevSpeedGet                                                    \
+        USBDevSpeedGet
+#endif
+#ifdef ROM_USBDMAChannelAddressGet
+#define MAP_USBDMAChannelAddressGet                                           \
+        ROM_USBDMAChannelAddressGet
+#else
+#define MAP_USBDMAChannelAddressGet                                           \
+        USBDMAChannelAddressGet
+#endif
+#ifdef ROM_USBDMAChannelAddressSet
+#define MAP_USBDMAChannelAddressSet                                           \
+        ROM_USBDMAChannelAddressSet
+#else
+#define MAP_USBDMAChannelAddressSet                                           \
+        USBDMAChannelAddressSet
+#endif
+#ifdef ROM_USBDMAChannelConfigSet
+#define MAP_USBDMAChannelConfigSet                                            \
+        ROM_USBDMAChannelConfigSet
+#else
+#define MAP_USBDMAChannelConfigSet                                            \
+        USBDMAChannelConfigSet
+#endif
+#ifdef ROM_USBDMAChannelDisable
+#define MAP_USBDMAChannelDisable                                              \
+        ROM_USBDMAChannelDisable
+#else
+#define MAP_USBDMAChannelDisable                                              \
+        USBDMAChannelDisable
+#endif
+#ifdef ROM_USBDMAChannelEnable
+#define MAP_USBDMAChannelEnable                                               \
+        ROM_USBDMAChannelEnable
+#else
+#define MAP_USBDMAChannelEnable                                               \
+        USBDMAChannelEnable
+#endif
+#ifdef ROM_USBDMAChannelIntDisable
+#define MAP_USBDMAChannelIntDisable                                           \
+        ROM_USBDMAChannelIntDisable
+#else
+#define MAP_USBDMAChannelIntDisable                                           \
+        USBDMAChannelIntDisable
+#endif
+#ifdef ROM_USBDMAChannelIntEnable
+#define MAP_USBDMAChannelIntEnable                                            \
+        ROM_USBDMAChannelIntEnable
+#else
+#define MAP_USBDMAChannelIntEnable                                            \
+        USBDMAChannelIntEnable
+#endif
+#ifdef ROM_USBDMAChannelCountGet
+#define MAP_USBDMAChannelCountGet                                             \
+        ROM_USBDMAChannelCountGet
+#else
+#define MAP_USBDMAChannelCountGet                                             \
+        USBDMAChannelCountGet
+#endif
+#ifdef ROM_USBDMAChannelCountSet
+#define MAP_USBDMAChannelCountSet                                             \
+        ROM_USBDMAChannelCountSet
+#else
+#define MAP_USBDMAChannelCountSet                                             \
+        USBDMAChannelCountSet
+#endif
+#ifdef ROM_USBDMAChannelIntStatus
+#define MAP_USBDMAChannelIntStatus                                            \
+        ROM_USBDMAChannelIntStatus
+#else
+#define MAP_USBDMAChannelIntStatus                                            \
+        USBDMAChannelIntStatus
+#endif
+#ifdef ROM_USBDMAChannelStatus
+#define MAP_USBDMAChannelStatus                                               \
+        ROM_USBDMAChannelStatus
+#else
+#define MAP_USBDMAChannelStatus                                               \
+        USBDMAChannelStatus
+#endif
+#ifdef ROM_USBDMAChannelStatusClear
+#define MAP_USBDMAChannelStatusClear                                          \
+        ROM_USBDMAChannelStatusClear
+#else
+#define MAP_USBDMAChannelStatusClear                                          \
+        USBDMAChannelStatusClear
+#endif
+#ifdef ROM_USBHighSpeed
+#define MAP_USBHighSpeed                                                      \
+        ROM_USBHighSpeed
+#else
+#define MAP_USBHighSpeed                                                      \
+        USBHighSpeed
+#endif
+#ifdef ROM_USBHostEndpointPing
+#define MAP_USBHostEndpointPing                                               \
+        ROM_USBHostEndpointPing
+#else
+#define MAP_USBHostEndpointPing                                               \
+        USBHostEndpointPing
+#endif
+#ifdef ROM_USBHostEndpointSpeed
+#define MAP_USBHostEndpointSpeed                                              \
+        ROM_USBHostEndpointSpeed
+#else
+#define MAP_USBHostEndpointSpeed                                              \
+        USBHostEndpointSpeed
+#endif
+#ifdef ROM_USBHostLPMConfig
+#define MAP_USBHostLPMConfig                                                  \
+        ROM_USBHostLPMConfig
+#else
+#define MAP_USBHostLPMConfig                                                  \
+        USBHostLPMConfig
+#endif
+#ifdef ROM_USBHostLPMResume
+#define MAP_USBHostLPMResume                                                  \
+        ROM_USBHostLPMResume
+#else
+#define MAP_USBHostLPMResume                                                  \
+        USBHostLPMResume
+#endif
+#ifdef ROM_USBHostLPMSend
+#define MAP_USBHostLPMSend                                                    \
+        ROM_USBHostLPMSend
+#else
+#define MAP_USBHostLPMSend                                                    \
+        USBHostLPMSend
+#endif
+#ifdef ROM_USBLPMIntDisable
+#define MAP_USBLPMIntDisable                                                  \
+        ROM_USBLPMIntDisable
+#else
+#define MAP_USBLPMIntDisable                                                  \
+        USBLPMIntDisable
+#endif
+#ifdef ROM_USBLPMIntEnable
+#define MAP_USBLPMIntEnable                                                   \
+        ROM_USBLPMIntEnable
+#else
+#define MAP_USBLPMIntEnable                                                   \
+        USBLPMIntEnable
+#endif
+#ifdef ROM_USBLPMIntStatus
+#define MAP_USBLPMIntStatus                                                   \
+        ROM_USBLPMIntStatus
+#else
+#define MAP_USBLPMIntStatus                                                   \
+        USBLPMIntStatus
+#endif
+#ifdef ROM_USBLPMLinkStateGet
+#define MAP_USBLPMLinkStateGet                                                \
+        ROM_USBLPMLinkStateGet
+#else
+#define MAP_USBLPMLinkStateGet                                                \
+        USBLPMLinkStateGet
+#endif
+#ifdef ROM_USBEndpointPacketCountSet
+#define MAP_USBEndpointPacketCountSet                                         \
+        ROM_USBEndpointPacketCountSet
+#else
+#define MAP_USBEndpointPacketCountSet                                         \
+        USBEndpointPacketCountSet
+#endif
+#ifdef ROM_USBULPIConfig
+#define MAP_USBULPIConfig                                                     \
+        ROM_USBULPIConfig
+#else
+#define MAP_USBULPIConfig                                                     \
+        USBULPIConfig
+#endif
+#ifdef ROM_USBULPIDisable
+#define MAP_USBULPIDisable                                                    \
+        ROM_USBULPIDisable
+#else
+#define MAP_USBULPIDisable                                                    \
+        USBULPIDisable
+#endif
+#ifdef ROM_USBULPIEnable
+#define MAP_USBULPIEnable                                                     \
+        ROM_USBULPIEnable
+#else
+#define MAP_USBULPIEnable                                                     \
+        USBULPIEnable
+#endif
+#ifdef ROM_USBULPIRegRead
+#define MAP_USBULPIRegRead                                                    \
+        ROM_USBULPIRegRead
+#else
+#define MAP_USBULPIRegRead                                                    \
+        USBULPIRegRead
+#endif
+#ifdef ROM_USBULPIRegWrite
+#define MAP_USBULPIRegWrite                                                   \
+        ROM_USBULPIRegWrite
+#else
+#define MAP_USBULPIRegWrite                                                   \
+        USBULPIRegWrite
+#endif
+#ifdef ROM_USBOTGSessionRequest
+#define MAP_USBOTGSessionRequest                                              \
+        ROM_USBOTGSessionRequest
+#else
+#define MAP_USBOTGSessionRequest                                              \
+        USBOTGSessionRequest
+#endif
+#ifdef ROM_USBDMANumChannels
+#define MAP_USBDMANumChannels                                                 \
+        ROM_USBDMANumChannels
+#else
+#define MAP_USBDMANumChannels                                                 \
+        USBDMANumChannels
+#endif
+#ifdef ROM_USBEndpointDMAConfigSet
+#define MAP_USBEndpointDMAConfigSet                                           \
+        ROM_USBEndpointDMAConfigSet
+#else
+#define MAP_USBEndpointDMAConfigSet                                           \
+        USBEndpointDMAConfigSet
+#endif
+#ifdef ROM_USBLPMRemoteWakeEnabled
+#define MAP_USBLPMRemoteWakeEnabled                                           \
+        ROM_USBLPMRemoteWakeEnabled
+#else
+#define MAP_USBLPMRemoteWakeEnabled                                           \
+        USBLPMRemoteWakeEnabled
+#endif
+#ifdef ROM_USBModeConfig
+#define MAP_USBModeConfig                                                     \
+        ROM_USBModeConfig
+#else
+#define MAP_USBModeConfig                                                     \
+        USBModeConfig
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Watchdog API.
+//
+//*****************************************************************************
+#ifdef ROM_WatchdogIntClear
+#define MAP_WatchdogIntClear                                                  \
+        ROM_WatchdogIntClear
+#else
+#define MAP_WatchdogIntClear                                                  \
+        WatchdogIntClear
+#endif
+#ifdef ROM_WatchdogRunning
+#define MAP_WatchdogRunning                                                   \
+        ROM_WatchdogRunning
+#else
+#define MAP_WatchdogRunning                                                   \
+        WatchdogRunning
+#endif
+#ifdef ROM_WatchdogEnable
+#define MAP_WatchdogEnable                                                    \
+        ROM_WatchdogEnable
+#else
+#define MAP_WatchdogEnable                                                    \
+        WatchdogEnable
+#endif
+#ifdef ROM_WatchdogResetEnable
+#define MAP_WatchdogResetEnable                                               \
+        ROM_WatchdogResetEnable
+#else
+#define MAP_WatchdogResetEnable                                               \
+        WatchdogResetEnable
+#endif
+#ifdef ROM_WatchdogResetDisable
+#define MAP_WatchdogResetDisable                                              \
+        ROM_WatchdogResetDisable
+#else
+#define MAP_WatchdogResetDisable                                              \
+        WatchdogResetDisable
+#endif
+#ifdef ROM_WatchdogLock
+#define MAP_WatchdogLock                                                      \
+        ROM_WatchdogLock
+#else
+#define MAP_WatchdogLock                                                      \
+        WatchdogLock
+#endif
+#ifdef ROM_WatchdogUnlock
+#define MAP_WatchdogUnlock                                                    \
+        ROM_WatchdogUnlock
+#else
+#define MAP_WatchdogUnlock                                                    \
+        WatchdogUnlock
+#endif
+#ifdef ROM_WatchdogLockState
+#define MAP_WatchdogLockState                                                 \
+        ROM_WatchdogLockState
+#else
+#define MAP_WatchdogLockState                                                 \
+        WatchdogLockState
+#endif
+#ifdef ROM_WatchdogReloadSet
+#define MAP_WatchdogReloadSet                                                 \
+        ROM_WatchdogReloadSet
+#else
+#define MAP_WatchdogReloadSet                                                 \
+        WatchdogReloadSet
+#endif
+#ifdef ROM_WatchdogReloadGet
+#define MAP_WatchdogReloadGet                                                 \
+        ROM_WatchdogReloadGet
+#else
+#define MAP_WatchdogReloadGet                                                 \
+        WatchdogReloadGet
+#endif
+#ifdef ROM_WatchdogValueGet
+#define MAP_WatchdogValueGet                                                  \
+        ROM_WatchdogValueGet
+#else
+#define MAP_WatchdogValueGet                                                  \
+        WatchdogValueGet
+#endif
+#ifdef ROM_WatchdogIntEnable
+#define MAP_WatchdogIntEnable                                                 \
+        ROM_WatchdogIntEnable
+#else
+#define MAP_WatchdogIntEnable                                                 \
+        WatchdogIntEnable
+#endif
+#ifdef ROM_WatchdogIntStatus
+#define MAP_WatchdogIntStatus                                                 \
+        ROM_WatchdogIntStatus
+#else
+#define MAP_WatchdogIntStatus                                                 \
+        WatchdogIntStatus
+#endif
+#ifdef ROM_WatchdogStallEnable
+#define MAP_WatchdogStallEnable                                               \
+        ROM_WatchdogStallEnable
+#else
+#define MAP_WatchdogStallEnable                                               \
+        WatchdogStallEnable
+#endif
+#ifdef ROM_WatchdogStallDisable
+#define MAP_WatchdogStallDisable                                              \
+        ROM_WatchdogStallDisable
+#else
+#define MAP_WatchdogStallDisable                                              \
+        WatchdogStallDisable
+#endif
+#ifdef ROM_WatchdogIntTypeSet
+#define MAP_WatchdogIntTypeSet                                                \
+        ROM_WatchdogIntTypeSet
+#else
+#define MAP_WatchdogIntTypeSet                                                \
+        WatchdogIntTypeSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Software API.
+//
+//*****************************************************************************
+#ifdef ROM_Crc16Array
+#define MAP_Crc16Array                                                        \
+        ROM_Crc16Array
+#else
+#define MAP_Crc16Array                                                        \
+        Crc16Array
+#endif
+#ifdef ROM_Crc16Array3
+#define MAP_Crc16Array3                                                       \
+        ROM_Crc16Array3
+#else
+#define MAP_Crc16Array3                                                       \
+        Crc16Array3
+#endif
+#ifdef ROM_Crc16
+#define MAP_Crc16                                                             \
+        ROM_Crc16
+#else
+#define MAP_Crc16                                                             \
+        Crc16
+#endif
+#ifdef ROM_Crc8CCITT
+#define MAP_Crc8CCITT                                                         \
+        ROM_Crc8CCITT
+#else
+#define MAP_Crc8CCITT                                                         \
+        Crc8CCITT
+#endif
+#ifdef ROM_Crc32
+#define MAP_Crc32                                                             \
+        ROM_Crc32
+#else
+#define MAP_Crc32                                                             \
+        Crc32
+#endif
+
+#endif // __DRIVERLIB_ROM_MAP_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h b/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h
new file mode 100644
index 0000000000..d796ff0618
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h
@@ -0,0 +1,108 @@
+//*****************************************************************************
+//
+// rtos_bindings.h - Macros intended to aid porting of TivaWare modules
+//                   for use with an RTOS.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_RTOS_BINDINGS_H__
+#define __DRIVERLIB_RTOS_BINDINGS_H__
+
+#ifdef USE_RTOS
+//*****************************************************************************
+//
+// If an RTOS is in use, implement a header file called "tiva_rtos.h"
+// which contains RTOS-specific versions of each of the macros defined below
+// and make sure it appears on the include path set when you build your
+// project.
+//
+// Note that there is no default implementation of this header file included
+// in TivaWare - it is your responsibility to create it specifically for
+// your RTOS.
+//
+//*****************************************************************************
+#include "tiva_rtos.h"
+
+#else
+//*****************************************************************************
+//
+// When no RTOS is in use, the follow macros compile to either nothing or a
+// minimal implementation that works in a bare-metal environment.
+//
+// Each of these macros must be redefined in tiva_rtos.h if you are using
+// TivaWare under an RTOS.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A simple macro used to yield within polling loops.  In the default, non-RTOS
+// implementation, this compiles to nothing.
+//
+//*****************************************************************************
+#define OS_YIELD()
+
+//*****************************************************************************
+//
+// A simple macro around the SysCtlDelay function.  The parameter is the number
+// of 3 cycle loops to wait before returning (as for SysCtlDelay).  In an RTOS
+// implementation, this could be replaced with an OS delay call with
+// appropriate parameter scaling.
+//
+//*****************************************************************************
+#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles)
+
+//*****************************************************************************
+//
+// Wrappers around low level interrupt control functions.  For information
+// on each of these functions, please see the appropriate API documentation
+// for the DriverLib Interrupt driver.
+//
+// The macros defined here represent interrupt-control functions that may be
+// called from within TivaWare code.  It is expected that application
+// code will use RTOS-specific functions to control interrupt priority, to
+// pend interrupts and to perform runtime vector manipulation.  As a result,
+// no macros are defined to wrap any of these functions from interrupt.c.
+//
+//*****************************************************************************
+#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable()
+#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable()
+#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID)
+#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID)
+
+#endif // USE_RTOS
+
+#endif // __DRIVERLIB_RTOS_BINDINGS_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/shamd5.c b/bsp/tm4c129x/libraries/driverlib/shamd5.c
new file mode 100644
index 0000000000..f04e07851a
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/shamd5.c
@@ -0,0 +1,1092 @@
+//*****************************************************************************
+//
+// shamd5.c - Driver for the SHA/MD5 module.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_shamd5.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/shamd5.h"
+
+//*****************************************************************************
+//
+//! \addtogroup shamd5_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Resets the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function performs a soft-reset of the SHA/MD5 module using the
+//! SYSCONFIG register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5Reset(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Set the soft-reset bit.
+    //
+    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_SOFTRESET;
+
+    //
+    // Wait for the reset to complete.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_SYSSTATUS) &
+           SHAMD5_SYSSTATUS_RESETDONE) == 0)
+    {
+    }
+
+    //
+    // Force idle mode.
+    //
+    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) =
+        ((HWREG(ui32Base + SHAMD5_O_SYSCONFIG) & ~SHAMD5_SYSCONFIG_SIDLE_M) |
+         SHAMD5_SYSCONFIG_SIDLE_FORCE);
+}
+
+//*****************************************************************************
+//
+//! Enables the uDMA requests in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function configures the DMA options of the SHA/MD5 module.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5DMAEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Write the new configuration into the register.
+    //
+    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |=
+        SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA requests in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function configures the DMA options of the SHA/MD5 module.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5DMADisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Write the new configuration into the register.
+    //
+    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &=
+        ~(SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN);
+}
+
+//*****************************************************************************
+//
+//! Get the interrupt status of the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the current value of the IRQSTATUS register.  The
+//! value will be a logical OR of the following:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//!   a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return Interrupt status
+//
+//*****************************************************************************
+uint32_t
+SHAMD5IntStatus(uint32_t ui32Base, bool bMasked)
+{
+    uint32_t ui32Status, ui32Enable, ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Return the value of the IRQSTATUS register.
+    //
+    ui32Status = HWREG(ui32Base + SHAMD5_O_IRQSTATUS);
+    if(bMasked)
+    {
+        ui32Enable = HWREG(ui32Base + SHAMD5_O_IRQENABLE);
+        ui32Temp = HWREG(ui32Base + SHAMD5_O_DMAMIS);
+        return((ui32Status & ui32Enable) |
+               ((ui32Temp & 0x00000001) << 19) |
+               ((ui32Temp & 0x00000002) << 16) |
+               ((ui32Temp & 0x00000004) << 14));
+    }
+    else
+    {
+        ui32Temp = HWREG(ui32Base + SHAMD5_O_DMARIS);
+        return(ui32Status |
+               ((ui32Temp & 0x00000001) << 19) |
+               ((ui32Temp & 0x00000002) << 16) |
+               ((ui32Temp & 0x00000004) << 14));
+    }
+}
+
+//*****************************************************************************
+//
+//! Enable interrupt sources in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32IntFlags contains desired interrupts to enable.
+//!
+//! This function enables interrupt sources in the SHA/MD5 module.
+//! ui32IntFlags must be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//!   a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
+           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
+           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
+           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
+
+    //
+    // Enable the interrupt sources.
+    //
+    HWREG(ui32Base + SHAMD5_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 14) |
+                                         ((ui32IntFlags & 0x00020000) >> 16) |
+                                         ((ui32IntFlags & 0x00040000) >> 19));
+    HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+
+    //
+    // Enable all interrupts.
+    //
+    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_IT_EN;
+}
+
+//*****************************************************************************
+//
+//! Disable interrupt sources in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32IntFlags contains desired interrupts to disable.
+//!
+//! \e ui32IntFlags must be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//!   a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
+           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
+           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
+           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
+
+    //
+    // Clear the corresponding flags disabling the interrupt sources.
+    //
+    HWREG(ui32Base + SHAMD5_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 14) |
+                                          ((ui32IntFlags & 0x00020000) >> 16) |
+                                          ((ui32IntFlags & 0x00040000) >> 19));
+    HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+
+    //
+    // If there are no interrupts enabled, then disable all interrupts.
+    //
+    if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0)
+    {
+        HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_IT_EN;
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears interrupt sources in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32IntFlags contains desired interrupts to disable.
+//!
+//! \e ui32IntFlags must be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//!   a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
+           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
+           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
+           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
+
+    //
+    // Clear the corresponding flags disabling the interrupt sources.
+    //
+    HWREG(ui32Base + SHAMD5_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 14) |
+                                        ((ui32IntFlags & 0x00020000) >> 16) |
+                                        ((ui32IntFlags & 0x00040000) >> 19));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled SHA/MD5 interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables SHA/MD5 interrupts on the interrupt controller;
+//! specific SHA/MD5 interrupt sources must be enabled using
+//! SHAMD5IntEnable().  The interrupt handler being registered must clear
+//! the source of the interrupt using SHAMD5IntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_SHA0_TM4C129, pfnHandler);
+
+    //
+    // Enable the interrupt
+    //
+    IntEnable(INT_SHA0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntUnregister(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_SHA0_TM4C129);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_SHA0_TM4C129);
+}
+
+//*****************************************************************************
+//
+//! Write the hash length to the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32Length is the hash length in bytes.
+//!
+//! This function writes the length of the hash data of the current operation
+//! to the SHA/MD5 module.  The value must be a multiple of 64 if the close
+//! hash is not set in the mode register.
+//!
+//! \note When this register is written, hash processing is triggered.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Set the LENGTH register and start processing.
+    //
+    HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Writes the mode in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32Mode is the mode of the SHA/MD5 module.
+//!
+//! This function writes the mode register configuring the SHA/MD5 module.
+//!
+//! The ui32Mode parameter is a bit-wise OR of values:
+//!
+//! - \b SHAMD5_ALGO_MD5 - Regular hash with MD5
+//! - \b SHAMD5_ALGO_SHA1 - Regular hash with SHA-1
+//! - \b SHAMD5_ALGO_SHA224 - Regular hash with SHA-224
+//! - \b SHAMD5_ALGO_SHA256 - Regular hash with SHA-256
+//! - \b SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5
+//! - \b SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1
+//! - \b SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224
+//! - \b SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+    ASSERT((ui32Mode == SHAMD5_ALGO_MD5) ||
+           (ui32Mode == SHAMD5_ALGO_SHA1) ||
+           (ui32Mode == SHAMD5_ALGO_SHA224) ||
+           (ui32Mode == SHAMD5_ALGO_SHA256) ||
+           (ui32Mode == SHAMD5_ALGO_HMAC_MD5) ||
+           (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) ||
+           (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) ||
+           (ui32Mode == SHAMD5_ALGO_HMAC_SHA256));
+
+    //
+    // Write the value in the MODE register.
+    //
+    HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Perform a non-blocking write of 16 words of data to the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32Src is the pointer to the 16-word array of data that will be
+//! written.
+//!
+//! This function writes 16 words of data into the data register regardless
+//! of whether or not the module is ready to accept the data.
+//!
+//! \return This function returns true if the write completed successfully.
+//! It returns false if the module was not ready.
+//
+//*****************************************************************************
+bool
+SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    uint32_t ui32Counter;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Check that the SHA/MD5 module is ready for data.  If not, return false.
+    //
+    if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
+    {
+        return(false);
+    }
+
+    //
+    // Write the 16 words of data.
+    //
+    for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4)
+    {
+        HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++;
+    }
+
+    //
+    // Return true as a sign of successfully completing the function.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Perform a blocking write of 16 words of data to the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32Src is the pointer to the 16-word array of data that will be
+//! written.
+//!
+//! This function does not return until the module is ready to accept data and
+//! the data has been written.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    uint32_t ui32Counter;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Wait for the module to be ready to accept data.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
+    {
+    }
+
+    //
+    // Write the 16 words of data.
+    //
+    for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4)
+    {
+        HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++;
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads the result of a hashing operation.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32Dest is the pointer to the 16-word array of data that will be
+//! written.
+//!
+//! This function does not return until the module is ready to accept data and
+//! the data has been written.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest)
+{
+    uint32_t ui32Idx, ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Determine the number of bytes in the result, based on the hash type.
+    //
+    switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M)
+    {
+        //
+        // The MD5 hash is being used.
+        //
+        case SHAMD5_MODE_ALGO_MD5:
+        {
+            //
+            // There are 16 bytes in the MD5 hash.
+            //
+            ui32Count = 16;
+
+            //
+            // Done.
+            //
+            break;
+        }
+
+        //
+        // The SHA-1 hash is being used.
+        //
+        case SHAMD5_MODE_ALGO_SHA1:
+        {
+            //
+            // There are 20 bytes in the SHA-1 hash.
+            //
+            ui32Count = 20;
+
+            //
+            // Done.
+            //
+            break;
+        }
+
+        //
+        // The SHA-224 hash is being used.
+        //
+        case SHAMD5_MODE_ALGO_SHA224:
+        {
+            //
+            // There are 28 bytes in the SHA-224 hash.
+            //
+            ui32Count = 28;
+
+            //
+            // Done.
+            //
+            break;
+        }
+
+        //
+        // The SHA-256 hash is being used.
+        //
+        case SHAMD5_MODE_ALGO_SHA256:
+        {
+            //
+            // There are 32 bytes in the SHA-256 hash.
+            //
+            ui32Count = 32;
+
+            //
+            // Done.
+            //
+            break;
+        }
+
+        //
+        // The hash type is not recognized.
+        //
+        default:
+        {
+            //
+            // Return without reading a result since the hardware appears to be
+            // misconfigured.
+            //
+            return;
+        }
+    }
+
+    //
+    // Read the hash result.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
+    {
+        *pui32Dest++ = HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx);
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes multiple words of data into the SHA/MD5 data registers.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32DataSrc is a pointer to an array of data to be written.
+//! \param ui32DataLength is the length of the data to be written in bytes.
+//!
+//! This function writes a variable number of words into the SHA/MD5 data
+//! registers.  The function waits for each block of data to be processed
+//! before another is written.  The \e ui32DataLength parameter must be a
+//! multiple of 4 to fall on a word boundry.
+//!
+//! \note This function is used by SHAMD5DataProcess() and SHAMD5HMACProcess()
+//! to process data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+_SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                         uint32_t ui32DataLength)
+{
+    uint32_t ui32Idx, ui32Count;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Calculate the number of blocks of data.
+    //
+    ui32Count = ui32DataLength / 64;
+
+    //
+    // Loop through all the blocks and write them into the data registers
+    // making sure to block additional operations until we can write the
+    // next 16 words.
+    //
+    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
+    {
+        //
+        // Write the block of data.
+        //
+        SHAMD5DataWrite(ui32Base, pui32DataSrc);
+
+        //
+        // Increment the pointer to next block of data.
+        //
+        pui32DataSrc += 16;
+    }
+
+    //
+    // Calculate the remaining bytes of data that don't make up a full block.
+    //
+    ui32Count = ui32DataLength % 64;
+
+    //
+    // If there are bytes that do not make up a whole block, then
+    // write them separately.
+    //
+    if(ui32Count)
+    {
+        //
+        // Wait until the engine has finished processing the previous block.
+        //
+        while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) &
+               SHAMD5_INT_INPUT_READY) == 0)
+        {
+        }
+
+        //
+        // Loop through the remaining words.
+        //
+        for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
+        {
+            //
+            // Write the word into the data register.
+            //
+            HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Idx) = *pui32DataSrc++;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Compute a hash using the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32DataSrc is a pointer to an array of data that contains the
+//! data that will be hashed.
+//! \param ui32DataLength specifies the length of the data to be hashed in
+//! bytes.
+//! \param pui32HashResult is a pointer to an array that holds the result
+//! of the hashing operation.
+//!
+//! This function computes the hash of an array of data using the SHA/MD5
+//! module.
+//!
+//! The length of the hash result is dependent on the algorithm that is in use.
+//! The following table shows the correct array size for each algorithm:
+//!
+//! -----------------------------------------
+//! | Algorithm | Number of Words in Result |
+//! -----------------------------------------
+//! | MD5       | 4 Words (128 bits)        |
+//! | SHA-1     | 5 Words (160 bits)        |
+//! | SHA-224   | 7 Words (224 bits)        |
+//! | SHA-256   | 8 Words (256 bits)        |
+//! -----------------------------------------
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                  uint32_t ui32DataLength, uint32_t *pui32HashResult)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+    ASSERT((ui32DataLength % 64) == 0);
+
+    //
+    // Wait for the context to be ready before writing the mode.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
+          0)
+    {
+    }
+
+    //
+    // Write the length.
+    //
+    SHAMD5HashLengthSet(ui32Base, ui32DataLength);
+
+    //
+    // Write the data.
+    //
+    _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength);
+
+    //
+    // Wait for the output to be ready.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
+          0)
+    {
+    }
+
+    //
+    // Read the result.
+    //
+    SHAMD5ResultRead(ui32Base, pui32HashResult);
+}
+
+//*****************************************************************************
+//
+//! Compute a HMAC with key pre-processing using the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32DataSrc is a pointer to an array of data that contains the
+//! data that is to be hashed.
+//! \param ui32DataLength specifies the length of the data to be hashed in
+//! bytes.
+//! \param pui32HashResult is a pointer to an array that holds the result
+//! of the hashing operation.
+//!
+//! This function computes a HMAC with the given data using the SHA/MD5
+//! module with a preprocessed key.
+//!
+//! The length of the hash result is dependent on the algorithm that is
+//! selected with the \e ui32Algo argument.  The following table shows the
+//! correct array size for each algorithm:
+//!
+//! -----------------------------------------
+//! | Algorithm | Number of Words in Result |
+//! -----------------------------------------
+//! | MD5       | 4 Words (128 bits)        |
+//! | SHA-1     | 5 Words (160 bits)        |
+//! | SHA-224   | 7 Words (224 bits)        |
+//! | SHA-256   | 8 Words (256 bits)        |
+//! -----------------------------------------
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                  uint32_t ui32DataLength, uint32_t *pui32HashResult)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Wait for the context to be ready before writing the mode.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
+          0)
+    {
+    }
+
+    //
+    // Write the length.
+    //
+    SHAMD5HashLengthSet(ui32Base, ui32DataLength);
+
+    //
+    // Write the data in the registers.
+    //
+    _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength);
+
+    //
+    // Wait for the output to be ready.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
+          0)
+    {
+    }
+
+    //
+    // Read the result.
+    //
+    SHAMD5ResultRead(ui32Base, pui32HashResult);
+}
+
+//*****************************************************************************
+//
+//! Process an HMAC key using the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32Key is a pointer to an array that contains the key to be
+//! processed.
+//! \param pui32PPKey is the pointer to the array that contains the
+//! pre-processed key.
+//!
+//! This function processes an HMAC key using the SHA/MD5.  The resultant
+//! pre-processed key can then be used with later HMAC operations to speed
+//! processing time.
+//!
+//! The \e pui32Key array must be 16 words (512 bits) long.  If the key is less
+//! than 512 bits, it must be padded with zeros.  The \e pui32PPKey array must
+//! each be 16 words (512 bits) long.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key,
+                        uint32_t *pui32PPKey)
+{
+    uint32_t ui32Index;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Wait for the context to be ready before writing the mode.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
+          0)
+    {
+    }
+
+    //
+    // Write the HMAC key.
+    //
+    for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
+    {
+        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) = *pui32Key++;
+    }
+
+    //
+    // Set the flag to cause the HMAC key to be pre-processed.
+    //
+    HWREG(ui32Base + SHAMD5_O_MODE) |= SHAMD5_MODE_HMAC_KEY_PROC;
+
+    //
+    // Set the length to zero to start the HMAC key pre-processing.
+    //
+    HWREG(ui32Base + SHAMD5_O_LENGTH) = 0;
+
+    //
+    // Wait for key to be processed.
+    //
+    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
+          0)
+    {
+    }
+
+    //
+    // Read the pre-processed key from the SHA/MD5 module.
+    //
+    for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
+    {
+        *pui32PPKey++ = HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index);
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes an HMAC key to the digest registers in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32Src is the pointer to the 16-word array of the HMAC key.
+//!
+//! This function is used to write HMAC key to the digest registers for
+//! key preprocessing.  The size of pui32Src must be 512 bytes.  If the key is
+//! less than 512 bytes, then it must be padded with zeros.
+//!
+//! \note It is recommended to use the SHAMD5IntStatus() function to check
+//! whether the context is ready before writing the key.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    uint32_t ui32Idx;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Write the key to the digest registers.
+    //
+    for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
+    {
+        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++;
+    }
+
+    //
+    // Configure the SHA engine for HMAC operation.
+    //
+    HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH |
+                                        SHAMD5_MODE_HMAC_KEY_PROC |
+                                        SHAMD5_MODE_CLOSE_HASH);
+}
+
+//*****************************************************************************
+//
+//! Writes a pre-processed HMAC key to the digest registers in the SHA/MD5
+//! module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui32Src is the pointer to the 16-word array of the HMAC key.
+//!
+//! This function is used to write HMAC key to the digest registers for
+//! key preprocessing.  The size of pui32Src must be 512 bytes.  If the key is
+//! less than 512 bytes, then it must be padded with zeros.
+//!
+//! \note It is recommended to use the SHAMD5IntStatus() function to check
+//! whether the context is ready before writing the key.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src)
+{
+    uint32_t ui32Idx;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == SHAMD5_BASE);
+
+    //
+    // Write the key to the digest registers.
+    //
+    for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
+    {
+        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++;
+    }
+
+    //
+    // Configure the SHA engine to continue the HMAC.
+    //
+    HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH |
+                                        SHAMD5_MODE_CLOSE_HASH);
+
+    //
+    // Write the digest count to 64 to account for the preprocessed key.
+    //
+    HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/shamd5.h b/bsp/tm4c129x/libraries/driverlib/shamd5.h
new file mode 100644
index 0000000000..f6091f8b46
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/shamd5.h
@@ -0,0 +1,127 @@
+//*****************************************************************************
+//
+// shamd5.h - Defines and Macros for the SHA/MD5.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SHAMD5_H__
+#define __DRIVERLIB_SHAMD5_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the algorithm in use in the
+// SHA/MD5 module.
+//
+//*****************************************************************************
+#define SHAMD5_ALGO_MD5         0x00000018
+#define SHAMD5_ALGO_SHA1        0x0000001a
+#define SHAMD5_ALGO_SHA224      0x0000001c
+#define SHAMD5_ALGO_SHA256      0x0000001e
+#define SHAMD5_ALGO_HMAC_MD5    0x00000000
+#define SHAMD5_ALGO_HMAC_SHA1   0x00000002
+#define SHAMD5_ALGO_HMAC_SHA224 0x00000004
+#define SHAMD5_ALGO_HMAC_SHA256 0x00000006
+
+//*****************************************************************************
+//
+// The following defines are used to represent the different interrupt sources
+// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
+// SHAMD5BlockOnIntStatus() functions.
+//
+//*****************************************************************************
+#define SHAMD5_INT_CONTEXT_READY \
+                                0x00000008
+#define SHAMD5_INT_PARTHASH_READY \
+                                0x00000004
+#define SHAMD5_INT_INPUT_READY  0x00000002
+#define SHAMD5_INT_OUTPUT_READY 0x00000001
+#define SHAMD5_INT_DMA_CONTEXT_IN \
+                                0x00080000
+#define SHAMD5_INT_DMA_DATA_IN  0x00020000
+#define SHAMD5_INT_DMA_CONTEXT_OUT \
+                                0x00010000
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern void SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                              uint32_t ui32DataLength,
+                              uint32_t *pui32HashResult);
+extern void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src);
+extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
+extern void SHAMD5DMADisable(uint32_t ui32Base);
+extern void SHAMD5DMAEnable(uint32_t ui32Base);
+extern void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src);
+extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key,
+                                    uint32_t *pui32PPKey);
+extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src);
+extern void SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                              uint32_t ui32DataLength,
+                              uint32_t *pui32HashResult);
+extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
+extern void SHAMD5IntUnregister(uint32_t ui32Base);
+extern void SHAMD5Reset(uint32_t ui32Base);
+extern void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SHAMD5_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/ssi.c b/bsp/tm4c129x/libraries/driverlib/ssi.c
new file mode 100644
index 0000000000..edfec5589c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/ssi.c
@@ -0,0 +1,1150 @@
+//*****************************************************************************
+//
+// ssi.c - Driver for Synchronous Serial Interface.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ssi_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/ssi.h"
+
+//*****************************************************************************
+//
+// A mapping of timer base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32SSIIntMap[][2] =
+{
+    { SSI0_BASE, INT_SSI0_TM4C123 },
+    { SSI1_BASE, INT_SSI1_TM4C123 },
+    { SSI2_BASE, INT_SSI2_TM4C123 },
+    { SSI3_BASE, INT_SSI3_TM4C123 },
+};
+static const uint_fast8_t g_ui8SSIIntMapRows =
+    sizeof(g_ppui32SSIIntMap) / sizeof(g_ppui32SSIIntMap[0]);
+
+static const uint32_t g_ppui32SSIIntMapSnowflake[][2] =
+{
+    { SSI0_BASE, INT_SSI0_TM4C129 },
+    { SSI1_BASE, INT_SSI1_TM4C129 },
+    { SSI2_BASE, INT_SSI2_TM4C129 },
+    { SSI3_BASE, INT_SSI3_TM4C129 },
+};
+static const uint_fast8_t g_ui8SSIIntMapSnowflakeRows =
+    sizeof(g_ppui32SSIIntMapSnowflake) / sizeof(g_ppui32SSIIntMapSnowflake[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks an SSI base address.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function determines if a SSI module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_SSIBaseValid(uint32_t ui32Base)
+{
+    return((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE) ||
+           (ui32Base == SSI2_BASE) || (ui32Base == SSI3_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Returns the interrupt number of SSI module .
+//!
+//! \param ui32Base is the base address of the SSI module.
+//!
+//! This function returns the interrupt number for the SSI module with the base
+//! address passed in the \e ui32Base parameter.
+//!
+//! \return Returns an SSI interrupt number, or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_SSIIntNumberGet(uint32_t ui32Base)
+{
+    uint_fast8_t ui8Idx, ui8Rows;
+    const uint32_t (*ppui32SSIIntMap)[2];
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    ppui32SSIIntMap = g_ppui32SSIIntMap;
+    ui8Rows = g_ui8SSIIntMapRows;
+
+    if(CLASS_IS_TM4C129)
+    {
+        ppui32SSIIntMap = g_ppui32SSIIntMapSnowflake;
+        ui8Rows = g_ui8SSIIntMapSnowflakeRows;
+    }
+
+    //
+    // Loop through the table that maps SSI base addresses to interrupt
+    // numbers.
+    //
+    for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
+    {
+        //
+        // See if this base address matches.
+        //
+        if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
+        {
+            //
+            // Return the corresponding interrupt number.
+            //
+            return(ppui32SSIIntMap[ui8Idx][1]);
+        }
+    }
+
+    //
+    // The base address could not be found, so return an error.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Configures the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32SSIClk is the rate of the clock supplied to the SSI module.
+//! \param ui32Protocol specifies the data transfer protocol.
+//! \param ui32Mode specifies the mode of operation.
+//! \param ui32BitRate specifies the clock rate.
+//! \param ui32DataWidth specifies number of bits transferred per frame.
+//!
+//! This function configures the synchronous serial interface.  It sets
+//! the SSI protocol, mode of operation, bit rate, and data width.
+//!
+//! The \e ui32Protocol parameter defines the data frame format.  The
+//! \e ui32Protocol parameter can be one of the following values:
+//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
+//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. Note that 
+//! the \b SSI_FRF_NMW option is only available on some devices. Refer to the
+//! device data sheet to determine if the Microwire format is supported on 
+//! a particular device.  The Motorola  frame formats encode the following
+//! polarity and phase configurations:
+//!
+//! <pre>
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//! </pre>
+//!
+//! The \e ui32Mode parameter defines the operating mode of the SSI module.
+//! The SSI module can operate as a master or slave; if it is a slave, the SSI
+//! can be configured to disable output on its serial output line.  The
+//! \e ui32Mode parameter can be one of the following values:
+//! \b SSI_MODE_MASTER, \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
+//!
+//! The \e ui32BitRate parameter defines the bit rate for the SSI.  This bit
+//! rate must satisfy the following clock ratio criteria:
+//!
+//! - FSSI >= 2 * bit rate (master mode)
+//! - FSSI >= 12 * bit rate (slave modes)
+//!
+//! where FSSI is the frequency of the clock supplied to the SSI module. Note
+//! that there are frequency limits for FSSI that are described in the Bit Rate
+//! Generation section of the SSI chapter in the data sheet.
+//!
+//! The \e ui32DataWidth parameter defines the width of the data transfers and
+//! can be a value between 4 and 16, inclusive.
+//!
+//! The peripheral clock is the same as the processor clock.  This value is
+//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
+//! constant and known (to save the code/execution overhead of a call to
+//! SysCtlClockGet()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+                   uint32_t ui32Protocol, uint32_t ui32Mode,
+                   uint32_t ui32BitRate, uint32_t ui32DataWidth)
+{
+    uint32_t ui32MaxBitRate;
+    uint32_t ui32RegVal;
+    uint32_t ui32PreDiv;
+    uint32_t ui32SCR;
+    uint32_t ui32SPH_SPO;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) ||
+           (ui32Protocol == SSI_FRF_MOTO_MODE_1) ||
+           (ui32Protocol == SSI_FRF_MOTO_MODE_2) ||
+           (ui32Protocol == SSI_FRF_MOTO_MODE_3) ||
+           (ui32Protocol == SSI_FRF_TI) ||
+           (ui32Protocol == SSI_FRF_NMW));
+    ASSERT((ui32Mode == SSI_MODE_MASTER) ||
+           (ui32Mode == SSI_MODE_SLAVE) ||
+           (ui32Mode == SSI_MODE_SLAVE_OD));
+    ASSERT(((ui32Mode == SSI_MODE_MASTER) &&
+            (ui32BitRate <= (ui32SSIClk / 2))) ||
+           ((ui32Mode != SSI_MODE_MASTER) &&
+            (ui32BitRate <= (ui32SSIClk / 12))));
+    ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256));
+    ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16));
+
+    //
+    // Set the mode.
+    //
+    ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+    ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
+    HWREG(ui32Base + SSI_O_CR1) = ui32RegVal;
+
+    //
+    // Set the clock predivider.
+    //
+    ui32MaxBitRate = ui32SSIClk / ui32BitRate;
+    ui32PreDiv = 0;
+    do
+    {
+        ui32PreDiv += 2;
+        ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1;
+    }
+    while(ui32SCR > 255);
+    HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv;
+
+    //
+    // Set protocol and clock rate.
+    //
+    ui32SPH_SPO = (ui32Protocol & 3) << 6;
+    ui32Protocol &= SSI_CR0_FRF_M;
+    ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol |
+                 (ui32DataWidth - 1);
+    HWREG(ui32Base + SSI_O_CR0) = ui32RegVal;
+}
+
+//*****************************************************************************
+//
+//! Enables the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function enables operation of the synchronous serial interface.  The
+//! synchronous serial interface must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Read-modify-write the enable bit.
+    //
+    HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE;
+}
+
+//*****************************************************************************
+//
+//! Disables the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function disables operation of the synchronous serial interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Read-modify-write the enable bit.
+    //
+    HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! synchronous serial interface interrupt occurs.
+//!
+//! This function registers the handler to be called when an SSI interrupt
+//! occurs.  This function enables the global interrupt in the interrupt
+//! controller; specific SSI interrupts must be enabled via SSIIntEnable().  If
+//! necessary, it is the interrupt handler's responsibility to clear the
+//! interrupt source via SSIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Determine the interrupt number based on the SSI module.
+    //
+    ui32Int = _SSIIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the synchronous serial interface interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function clears the handler to be called when an SSI interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Determine the interrupt number based on the SSI module.
+    //
+    ui32Int = _SSIIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated SSI interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.  The \e ui32IntFlags
+//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or
+//! \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(ui32Base + SSI_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated SSI interrupt sources.  The
+//! \e ui32IntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF,
+//!  \b SSI_RXTO, or \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(ui32Base + SSI_O_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param bMasked is \b false if the raw interrupt status is required or
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the SSI module.  Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
+//
+//*****************************************************************************
+uint32_t
+SSIIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + SSI_O_MIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + SSI_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified SSI interrupt sources so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep the interrupts from being triggered again immediately upon exit.  The
+//! \e ui32IntFlags parameter can consist of either or both the \b SSI_RXTO and
+//! \b SSI_RXOR values.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.  If there is no space available in the transmit FIFO,
+//! this function waits until there is space available before returning.
+//!
+//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk().  For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ui32Data are discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataPut(uint32_t ui32Base, uint32_t ui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
+                                       SSI_CR0_DSS_M))) == 0);
+
+    //
+    // Wait until there is space.
+    //
+    while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF))
+    {
+    }
+
+    //
+    // Write the data to the SSI.
+    //
+    HWREG(ui32Base + SSI_O_DR) = ui32Data;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.  If there is no space in the FIFO, then this function
+//! returns a zero.
+//!
+//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk().  For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ui32Data are discarded.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+int32_t
+SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
+                                       SSI_CR0_DSS_M))) == 0);
+
+    //
+    // Check for space to write.
+    //
+    if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)
+    {
+        HWREG(ui32Base + SSI_O_DR) = ui32Data;
+        return(1);
+    }
+    else
+    {
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pui32Data is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! This function gets received data from the receive FIFO of the specified
+//! SSI module and places that data into the location specified by the
+//! \e pui32Data parameter.  If there is no data available, this function waits
+//! until data is received before returning.
+//!
+//! \note Only the lower N bits of the value written to \e pui32Data contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk().  For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to
+//! \e pui32Data contain valid data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Wait until there is data to be read.
+    //
+    while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE))
+    {
+    }
+
+    //
+    // Read data from SSI.
+    //
+    *pui32Data = HWREG(ui32Base + SSI_O_DR);
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pui32Data is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! This function gets received data from the receive FIFO of the specified SSI
+//! module and places that data into the location specified by the \e ui32Data
+//! parameter.  If there is no data in the FIFO, then this function returns a
+//! zero.
+//!
+//! \note Only the lower N bits of the value written to \e pui32Data contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk().  For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to
+//! \e pui32Data contain valid data.
+//!
+//! \return Returns the number of elements read from the SSI receive FIFO.
+//
+//*****************************************************************************
+int32_t
+SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Check for data to read.
+    //
+    if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)
+    {
+        *pui32Data = HWREG(ui32Base + SSI_O_DR);
+        return(1);
+    }
+    else
+    {
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables SSI DMA operation.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
+//!
+//! This function enables the specified SSI DMA features.  The SSI can be
+//! configured to use DMA for transmit and/or receive data transfers.
+//! The \e ui32DMAFlags parameter is the logical OR of any of the following
+//! values:
+//!
+//! - SSI_DMA_RX - enable DMA for receive
+//! - SSI_DMA_TX - enable DMA for transmit
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the SSI.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Set the requested bits in the SSI DMA control register.
+    //
+    HWREG(ui32Base + SSI_O_DMACTL) |= ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables SSI DMA operation.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable SSI DMA features that were enabled
+//! by SSIDMAEnable().  The specified SSI DMA features are disabled.  The
+//! \e ui32DMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - SSI_DMA_RX - disable DMA for receive
+//! - SSI_DMA_TX - disable DMA for transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Clear the requested bits in the SSI DMA control register.
+    //
+    HWREG(ui32Base + SSI_O_DMACTL) &= ~ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Determines whether the SSI transmitter is busy or not.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//!
+//! This function allows the caller to determine whether all transmitted bytes
+//! have cleared the transmitter hardware.  If \b false is returned, then the
+//! transmit FIFO is empty and all bits of the last transmitted word have left
+//! the hardware shift register.
+//!
+//! \return Returns \b true if the SSI is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+bool
+SSIBusy(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Determine if the SSI is busy.
+    //
+    return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the data clock source for the specified SSI peripheral.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//! \param ui32Source is the baud clock source for the SSI.
+//!
+//! This function allows the baud clock source for the SSI to be selected.
+//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
+//!
+//! Changing the baud clock source changes the data rate generated by the
+//! SSI.  Therefore, the data rate should be reconfigured after any change to
+//! the SSI clock source.
+//!
+//! \note The ability to specify the SSI baud clock source varies with the
+//! Tiva part and SSI in use.  Please consult the data sheet for the part
+//! in use to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Source == SSI_CLOCK_SYSTEM) ||
+           (ui32Source == SSI_CLOCK_PIOSC));
+
+    //
+    // Set the SSI clock source.
+    //
+    HWREG(ui32Base + SSI_O_CC) = ui32Source;
+}
+
+//*****************************************************************************
+//
+//! Gets the data clock source for the specified SSI peripheral.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//!
+//! This function returns the data clock source for the specified SSI.
+//!
+//! \note The ability to specify the SSI data clock source varies with the
+//! Tiva part and SSI in use.  Please consult the data sheet for the part
+//! in use to determine whether this support is available.
+//!
+//! \return Returns the current clock source, which is either
+//! \b SSI_CLOCK_SYSTEM or \b SSI_CLOCK_PIOSC.
+//
+//*****************************************************************************
+uint32_t
+SSIClockSourceGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Return the SSI clock source.
+    //
+    return(HWREG(ui32Base + SSI_O_CC));
+}
+
+//*****************************************************************************
+//
+//! Selects the advanced mode of operation for the SSI module.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//! \param ui32Mode is the mode of operation to use.
+//!
+//! This function selects the mode of operation for the SSI module, which is
+//! needed when using the advanced operation modes (Bi- or Quad-SPI).  One of
+//! the following modes can be selected:
+//!
+//! - \b SSI_ADV_MODE_LEGACY - Disables the advanced modes of operation,
+//!   resulting in legacy, or backwards-compatible, operation.  When this mode
+//!   is selected, it is not valid to switch to Bi- or Quad-SPI operation.
+//!   This mode is the default.
+//! - \b SSI_ADV_MODE_WRITE - The advanced mode of operation where data is only
+//!   written to the slave; any data clocked in via the \b SSIRx pin is thrown
+//!   away (instead of being placed into the SSI Rx FIFO).
+//! - \b SSI_ADV_MODE_READ_WRITE - The advanced mode of operation where data is
+//!   written to and read from the slave; this mode is the same as
+//!   \b SSI_ADV_MODE_LEGACY but allows transitions to Bi- or Quad-SPI
+//!   operation.
+//! - \b SSI_ADV_MODE_BI_READ - The advanced mode of operation where data is
+//!   read from the slave in Bi-SPI mode, with two bits of data read on every
+//!   SSI clock.
+//! - \b SSI_ADV_MODE_BI_WRITE - The advanced mode of operation where data is
+//!   written to the slave in Bi-SPI mode, with two bits of data written on
+//!   every SSI clock.
+//! - \b SSI_ADV_MODE_QUAD_READ - The advanced mode of operation where data is
+//!   read from the slave in Quad-SPI mode, with four bits of data read on
+//!   every SSI clock.
+//! - \b SSI_ADV_MODE_QUAD_WRITE - The advanced mode of operation where data is
+//!   written to the slave in Quad-SPI mode, with four bits of data written on
+//!   every SSI clock.
+//!
+//! The following mode transitions are valid (other transitions produce
+//! undefined results):
+//!
+//! \verbatim
+//! +----------+-------------------------------------------------------------+
+//! |FROM      |                             TO                              |
+//! |          |Legacy|Write|Read Write|Bi Read|Bi Write|Quad Read|Quad Write|
+//! +----------+------+-----+----------+-------+--------+---------+----------+
+//! |Legacy    | yes  | yes |   yes    |       |        |         |          |
+//! |Write     | yes  | yes |   yes    |  yes  |  yes   |   yes   |   yes    |
+//! |Read/Write| yes  | yes |   yes    |  yes  |  yes   |   yes   |   yes    |
+//! |Bi Read   |      | yes |   yes    |  yes  |  yes   |         |          |
+//! |Bi write  |      | yes |   yes    |  yes  |  yes   |         |          |
+//! |Quad read |      | yes |   yes    |       |        |   yes   |   yes    |
+//! |Quad write|      | yes |   yes    |       |        |   yes   |   yes    |
+//! +----------+------+-----+----------+-------+--------+---------+----------+
+//! \endverbatim
+//!
+//! When using an advanced mode of operation, the SSI module must have been
+//! configured for eight data bits and the \b SSI_FRF_MOTO_MODE_0 protocol.
+//! The advanced mode operation that is selected applies only to data newly
+//! written into the FIFO; the data that is already present in the FIFO is
+//! handled using the advanced mode of operation in effect when that data was
+//! written.
+//!
+//! Switching into and out of legacy mode should only occur when the FIFO is
+//! empty.
+//!
+//! \note The availability of the advanced mode of SSI operation varies with
+//! the Tiva part and SSI in use.  Please consult the data sheet for the
+//! part in use to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Mode == SSI_ADV_MODE_LEGACY) ||
+           (ui32Mode == SSI_ADV_MODE_WRITE) ||
+           (ui32Mode == SSI_ADV_MODE_READ_WRITE) ||
+           (ui32Mode == SSI_ADV_MODE_BI_READ) ||
+           (ui32Mode == SSI_ADV_MODE_BI_WRITE) ||
+           (ui32Mode == SSI_ADV_MODE_QUAD_READ) ||
+           (ui32Mode == SSI_ADV_MODE_QUAD_WRITE));
+
+    //
+    // Set the SSI mode of operation.
+    //
+    HWREG(ui32Base + SSI_O_CR1) =
+        ((HWREG(ui32Base + SSI_O_CR1) & ~(SSI_CR1_DIR | SSI_CR1_MODE_M)) |
+         ui32Mode);
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO as the end of a frame.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module, marking it as the end of a frame.  If there is no
+//! space available in the transmit FIFO, this function waits until there is
+//! space available before returning.  After this byte is transmitted by the
+//! SSI module, the FSS signal de-asserts for at least one SSI clock.
+//!
+//! \note The upper 24 bits of \e ui32Data are discarded by the hardware.
+//!
+//! \note The availability of the advanced mode of SSI operation varies with
+//! the Tiva part and SSI in use.  Please consult the data sheet for the
+//! part in use to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Data & 0xff) == 0);
+
+    //
+    // Wait until there is space.
+    //
+    while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF))
+    {
+    }
+
+    //
+    // Write the data to the SSI.
+    //
+    HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM;
+    HWREG(ui32Base + SSI_O_DR) = ui32Data;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO as the end of a frame.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module, marking it as the end of a frame.  After this byte is
+//! transmitted by the SSI module, the FSS signal de-asserts for at least one
+//! SSI clock.  If there is no space in the FIFO, then this function returns a
+//! zero.
+//!
+//! \note The upper 24 bits of \e ui32Data are discarded by the hardware.
+//!
+//! \note The availability of the advanced mode of SSI operation varies with
+//! the Tiva part and SSI in use.  Please consult the data sheet for the
+//! part in use to determine whether this support is available.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+int32_t
+SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, uint32_t ui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+    ASSERT((ui32Data & 0xff) == 0);
+
+    //
+    // Check for space to write.
+    //
+    if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)
+    {
+        HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM;
+        HWREG(ui32Base + SSI_O_DR) = ui32Data;
+        return(1);
+    }
+    else
+    {
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Configures the SSI advanced mode to hold the SSIFss signal during the full
+//! transfer.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//!
+//! This function configures the SSI module to de-assert the SSIFss signal
+//! during the entire data transfer when using one of the advanced modes
+//! (instead of briefly de-asserting it after every byte).  When using this
+//! mode, SSIFss can be directly controlled via SSIAdvDataPutFrameEnd() and
+//! SSIAdvDataPutFrameEndNonBlocking().
+//!
+//! \note The availability of the advanced mode of SSI operation varies with
+//! the Tiva part and SSI in use.  Please consult the data sheet for the
+//! part in use to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIAdvFrameHoldEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Set the hold frame bit.
+    //
+    HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_FSSHLDFRM;
+}
+
+//*****************************************************************************
+//
+//! Configures the SSI advanced mode to de-assert the SSIFss signal after every 
+//! byte transfer.
+//!
+//! \param ui32Base is the base address of the SSI module.
+//!
+//! This function configures the SSI module to de-assert the SSIFss signal
+//! for one SSI clock cycle after every byte is transferred using one of the
+//! advanced modes (instead of leaving it asserted for the entire transfer).
+//! This mode is the default operation.
+//!
+//! \note The availability of the advanced mode of SSI operation varies with
+//! the Tiva part and SSI in use.  Please consult the data sheet for the
+//! part in use to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIAdvFrameHoldDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SSIBaseValid(ui32Base));
+
+    //
+    // Clear the hold frame bit.
+    //
+    HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_FSSHLDFRM);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/ssi.h b/bsp/tm4c129x/libraries/driverlib/ssi.h
new file mode 100644
index 0000000000..e27f2f6739
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/ssi.h
@@ -0,0 +1,157 @@
+//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SSI_H__
+#define __DRIVERLIB_SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ui32IntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXEOT               0x00000040  // Transmit FIFO is empty
+#define SSI_DMATX               0x00000020  // DMA Transmit complete
+#define SSI_DMARX               0x00000010  // DMA Receive complete
+#define SSI_TXFF                0x00000008  // TX FIFO half full or less
+#define SSI_RXFF                0x00000004  // RX FIFO half full or more
+#define SSI_RXTO                0x00000002  // RX timeout
+#define SSI_RXOR                0x00000001  // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0     0x00000000  // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1     0x00000002  // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2     0x00000001  // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3     0x00000003  // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI              0x00000010  // TI frame format
+#define SSI_FRF_NMW             0x00000020  // National MicroWire frame format
+
+#define SSI_MODE_MASTER         0x00000000  // SSI master
+#define SSI_MODE_SLAVE          0x00000001  // SSI slave
+#define SSI_MODE_SLAVE_OD       0x00000002  // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX              0x00000002  // Enable DMA for transmit
+#define SSI_DMA_RX              0x00000001  // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIClockSourceSet() or returned from
+// SSIClockSourceGet().
+//
+//*****************************************************************************
+#define SSI_CLOCK_SYSTEM        0x00000000
+#define SSI_CLOCK_PIOSC         0x00000005
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIAdvModeSet().
+//
+//*****************************************************************************
+#define SSI_ADV_MODE_LEGACY     0x00000000
+#define SSI_ADV_MODE_READ_WRITE 0x000001c0
+#define SSI_ADV_MODE_WRITE      0x000000c0
+#define SSI_ADV_MODE_BI_READ    0x00000140
+#define SSI_ADV_MODE_BI_WRITE   0x00000040
+#define SSI_ADV_MODE_QUAD_READ  0x00000180
+#define SSI_ADV_MODE_QUAD_WRITE 0x00000080
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+                               uint32_t ui32Protocol, uint32_t ui32Mode,
+                               uint32_t ui32BitRate,
+                               uint32_t ui32DataWidth);
+extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data);
+extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base,
+                                  uint32_t *pui32Data);
+extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
+extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data);
+extern void SSIDisable(uint32_t ui32Base);
+extern void SSIEnable(uint32_t ui32Base);
+extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked);
+extern void SSIIntUnregister(uint32_t ui32Base);
+extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern bool SSIBusy(uint32_t ui32Base);
+extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
+extern uint32_t SSIClockSourceGet(uint32_t ui32Base);
+extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data);
+extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base,
+                                             uint32_t ui32Data);
+extern void SSIAdvFrameHoldEnable(uint32_t ui32Base);
+extern void SSIAdvFrameHoldDisable(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SSI_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/sw_crc.c b/bsp/tm4c129x/libraries/driverlib/sw_crc.c
new file mode 100644
index 0000000000..9d4ead59bf
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/sw_crc.c
@@ -0,0 +1,770 @@
+//*****************************************************************************
+//
+// sw_crc.c - Software CRC functions.
+//
+// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sw_crc_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "driverlib/sw_crc.h"
+
+//*****************************************************************************
+//
+// The CRC table for the polynomial C(x) = x^8 + x^2 + x + 1 (CRC-8-CCITT).
+//
+//*****************************************************************************
+static const uint8_t g_pui8Crc8CCITT[256] =
+{
+    0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
+    0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
+    0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
+    0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
+    0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
+    0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
+    0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
+    0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
+    0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
+    0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
+    0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
+    0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
+    0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
+    0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
+    0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
+    0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
+    0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
+    0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
+    0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
+    0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
+    0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
+    0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
+    0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
+    0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
+    0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
+    0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
+    0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
+    0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
+    0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
+    0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
+    0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
+    0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
+};
+
+//*****************************************************************************
+//
+// The CRC-16 table for the polynomial C(x) = x^16 + x^15 + x^2 + 1 (standard
+// CRC-16, also known as CRC-16-IBM and CRC-16-ANSI).
+//
+//*****************************************************************************
+static const uint16_t g_pui16Crc16[256] =
+{
+    0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+    0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+    0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+    0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+    0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+    0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+    0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+    0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+    0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+    0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+    0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+    0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+    0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+    0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+    0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+    0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+    0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+    0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+    0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+    0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+    0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+    0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+    0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+    0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+    0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+    0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+    0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+    0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+    0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+    0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+    0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+    0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+//*****************************************************************************
+//
+// The CRC-32 table for the polynomial C(x) = x^32 + x^26 + x^23 + x^22 +
+// x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 (standard
+// CRC32 as used in Ethernet, MPEG-2, PNG, etc.).
+//
+//*****************************************************************************
+static const uint32_t g_pui32Crc32[] =
+{
+    0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
+    0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+    0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+    0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+    0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
+    0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+    0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
+    0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+    0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+    0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+    0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
+    0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+    0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
+    0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+    0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+    0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+    0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
+    0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+    0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
+    0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+    0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+    0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+    0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
+    0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+    0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
+    0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+    0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+    0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+    0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
+    0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+    0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
+    0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+    0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+    0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
+    0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
+    0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+    0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
+    0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+    0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+    0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+    0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
+    0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+    0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
+    0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+    0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+    0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+    0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
+    0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+    0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
+    0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+    0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+    0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
+    0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
+    0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+    0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
+    0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+    0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+    0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+    0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
+    0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+    0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
+    0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+    0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+    0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+
+//*****************************************************************************
+//
+// This macro executes one iteration of the CRC-8-CCITT.
+//
+//*****************************************************************************
+#define CRC8_ITER(crc, data)    g_pui8Crc8CCITT[(uint8_t)((crc) ^ (data))]
+
+//*****************************************************************************
+//
+// This macro executes one iteration of the CRC-16.
+//
+//*****************************************************************************
+#define CRC16_ITER(crc, data)   (((crc) >> 8) ^                               \
+                                 g_pui16Crc16[(uint8_t)((crc) ^ (data))])
+
+//*****************************************************************************
+//
+// This macro executes one iteration of the CRC-32.
+//
+//*****************************************************************************
+#define CRC32_ITER(crc, data)   (((crc) >> 8) ^                               \
+                                 g_pui32Crc32[(uint8_t)((crc & 0xFF) ^        \
+                                                        (data))])
+
+//*****************************************************************************
+//
+//! Calculates the CRC-8-CCITT of an array of bytes.
+//!
+//! \param ui8Crc is the starting CRC-8-CCITT value.
+//! \param pui8Data is a pointer to the data buffer.
+//! \param ui32Count is the number of bytes in the data buffer.
+//!
+//! This function is used to calculate the CRC-8-CCITT of the input buffer.
+//! The CRC-8-CCITT is computed in a running fashion, meaning that the entire
+//! data block that is to have its CRC-8-CCITT computed does not need to be
+//! supplied all at once.  If the input buffer contains the entire block of
+//! data, then \b ui8Crc should be set to 0.  If, however, the entire block of
+//! data is not available, then \b ui8Crc should be set to 0 for the first
+//! portion of the data, and then the returned value should be passed back in
+//! as \b ui8Crc for the next portion of the data.
+//!
+//! For example, to compute the CRC-8-CCITT of a block that has been split into
+//! three pieces, use the following:
+//!
+//! \verbatim
+//!     ui8Crc = Crc8CCITT(0, pui8Data1, ui32Len1);
+//!     ui8Crc = Crc8CCITT(ui8Crc, pui8Data2, ui32Len2);
+//!     ui8Crc = Crc8CCITT(ui8Crc, pui8Data3, ui32Len3);
+//! \endverbatim
+//!
+//! Computing a CRC-8-CCITT in a running fashion is useful in cases where the
+//! data is arriving via a serial link (for example) and is therefore not all
+//! available at one time.
+//!
+//! \return The CRC-8-CCITT of the input data.
+//
+//*****************************************************************************
+uint8_t
+Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, uint32_t ui32Count)
+{
+    uint32_t ui32Temp;
+
+    //
+    // If the data buffer is not 16 bit-aligned, then perform a single step of
+    // the CRC to make it 16 bit-aligned.
+    //
+    if((uint32_t)pui8Data & 1)
+    {
+        //
+        // Perform the CRC on this input byte.
+        //
+        ui8Crc = CRC8_ITER(ui8Crc, *pui8Data);
+
+        //
+        // Skip this input byte.
+        //
+        pui8Data++;
+        ui32Count--;
+    }
+
+    //
+    // If the data buffer is not word-aligned and there are at least two bytes
+    // of data left, then perform two steps of the CRC to make it word-aligned.
+    //
+    if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
+    {
+        //
+        // Read the next 16 bits.
+        //
+        ui32Temp = *(uint16_t *)pui8Data;
+
+        //
+        // Perform the CRC on these two bytes.
+        //
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 2;
+        ui32Count -= 2;
+    }
+
+    //
+    // While there is at least a word remaining in the data buffer, perform
+    // four steps of the CRC to consume a word.
+    //
+    while(ui32Count > 3)
+    {
+        //
+        // Read the next word.
+        //
+        ui32Temp = *(uint32_t *)pui8Data;
+
+        //
+        // Perform the CRC on these four bytes.
+        //
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 16);
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 24);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 4;
+        ui32Count -= 4;
+    }
+
+    //
+    // If there are 16 bits left in the input buffer, then perform two steps of
+    // the CRC.
+    //
+    if(ui32Count > 1)
+    {
+        //
+        // Read the 16 bits.
+        //
+        ui32Temp = *(uint16_t *)pui8Data;
+
+        //
+        // Perform the CRC on these two bytes.
+        //
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
+        ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 2;
+        ui32Count -= 2;
+    }
+
+    //
+    // If there is a final byte remaining in the input buffer, then perform a
+    // single step of the CRC.
+    //
+    if(ui32Count != 0)
+    {
+        ui8Crc = CRC8_ITER(ui8Crc, *pui8Data);
+    }
+
+    //
+    // Return the resulting CRC-8-CCITT value.
+    //
+    return(ui8Crc);
+}
+
+//*****************************************************************************
+//
+//! Calculates the CRC-16 of an array of bytes.
+//!
+//! \param ui16Crc is the starting CRC-16 value.
+//! \param pui8Data is a pointer to the data buffer.
+//! \param ui32Count is the number of bytes in the data buffer.
+//!
+//! This function is used to calculate the CRC-16 of the input buffer.  The
+//! CRC-16 is computed in a running fashion, meaning that the entire data block
+//! that is to have its CRC-16 computed does not need to be supplied all at
+//! once.  If the input buffer contains the entire block of data, then
+//! \b ui16Crc should be set to 0.  If, however, the entire block of data is
+//! not available, then \b ui16Crc should be set to 0 for the first portion of
+//! the data, and then the returned value should be passed back in as
+//! \b ui16Crc for the next portion of the data.
+//!
+//! For example, to compute the CRC-16 of a block that has been split into
+//! three pieces, use the following:
+//!
+//! \verbatim
+//!     ui16Crc = Crc16(0, pui8Data1, ui32Len1);
+//!     ui16Crc = Crc16(ui16Crc, pui8Data2, ui32Len2);
+//!     ui16Crc = Crc16(ui16Crc, pui8Data3, ui32Len3);
+//! \endverbatim
+//!
+//! Computing a CRC-16 in a running fashion is useful in cases where the data
+//! is arriving via a serial link (for example) and is therefore not all
+//! available at one time.
+//!
+//! \return The CRC-16 of the input data.
+//
+//*****************************************************************************
+uint16_t
+Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, uint32_t ui32Count)
+{
+    uint32_t ui32Temp;
+
+    //
+    // If the data buffer is not 16 bit-aligned, then perform a single step of
+    // the CRC to make it 16 bit-aligned.
+    //
+    if((uint32_t)pui8Data & 1)
+    {
+        //
+        // Perform the CRC on this input byte.
+        //
+        ui16Crc = CRC16_ITER(ui16Crc, *pui8Data);
+
+        //
+        // Skip this input byte.
+        //
+        pui8Data++;
+        ui32Count--;
+    }
+
+    //
+    // If the data buffer is not word-aligned and there are at least two bytes
+    // of data left, then perform two steps of the CRC to make it word-aligned.
+    //
+    if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
+    {
+        //
+        // Read the next 16 bits.
+        //
+        ui32Temp = *(uint16_t *)pui8Data;
+
+        //
+        // Perform the CRC on these two bytes.
+        //
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 2;
+        ui32Count -= 2;
+    }
+
+    //
+    // While there is at least a word remaining in the data buffer, perform
+    // four steps of the CRC to consume a word.
+    //
+    while(ui32Count > 3)
+    {
+        //
+        // Read the next word.
+        //
+        ui32Temp = *(uint32_t *)pui8Data;
+
+        //
+        // Perform the CRC on these four bytes.
+        //
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 4;
+        ui32Count -= 4;
+    }
+
+    //
+    // If there are two bytes left in the input buffer, then perform two steps
+    // of the CRC.
+    //
+    if(ui32Count > 1)
+    {
+        //
+        // Read the two bytes.
+        //
+        ui32Temp = *(uint16_t *)pui8Data;
+
+        //
+        // Perform the CRC on these two bytes.
+        //
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 2;
+        ui32Count -= 2;
+    }
+
+    //
+    // If there is a final byte remaining in the input buffer, then perform a
+    // single step of the CRC.
+    //
+    if(ui32Count != 0)
+    {
+        ui16Crc = CRC16_ITER(ui16Crc, *pui8Data);
+    }
+
+    //
+    // Return the resulting CRC-16 value.
+    //
+    return(ui16Crc);
+}
+
+//*****************************************************************************
+//
+//! Calculates the CRC-16 of an array of words.
+//!
+//! \param ui32WordLen is the length of the array in words (the number of bytes
+//! divided by 4).
+//! \param pui32Data is a pointer to the data buffer.
+//!
+//! This function is a wrapper around the running CRC-16 function, providing
+//! the CRC-16 for a single block of data.
+//!
+//! \return The CRC-16 of the input data.
+//
+//*****************************************************************************
+uint16_t
+Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data)
+{
+    //
+    // Calculate and return the CRC-16 of this array of words.
+    //
+    return(Crc16(0, (const uint8_t *)pui32Data, ui32WordLen * 4));
+}
+
+//*****************************************************************************
+//
+//! Calculates three CRC-16s of an array of words.
+//!
+//! \param ui32WordLen is the length of the array in words (the number of bytes
+//! divided by 4).
+//! \param pui32Data is a pointer to the data buffer.
+//! \param pui16Crc3 is a pointer to an array in which to place the three
+//! CRC-16 values.
+//!
+//! This function is used to calculate three CRC-16s of the input buffer; the
+//! first uses every byte from the array, the second uses only the even-index
+//! bytes from the array (in other words, bytes 0, 2, 4, etc.), and the third
+//! uses only the odd-index bytes from the array (in other words, bytes 1, 3,
+//! 5, etc.).
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
+            uint16_t *pui16Crc3)
+{
+    uint16_t ui16Crc, ui16Cri8Odd, ui16Cri8Even;
+    uint32_t ui32Temp;
+
+    //
+    // Initialize the CRC values to zero.
+    //
+    ui16Crc = 0;
+    ui16Cri8Odd = 0;
+    ui16Cri8Even = 0;
+
+    //
+    // Loop while there are more words in the data buffer.
+    //
+    while(ui32WordLen--)
+    {
+        //
+        // Read the next word.
+        //
+        ui32Temp = *pui32Data++;
+
+        //
+        // Perform the first CRC on all four data bytes.
+        //
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16);
+        ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24);
+
+        //
+        // Perform the second CRC on only the even-index data bytes.
+        //
+        ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp);
+        ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp >> 16);
+
+        //
+        // Perform the third CRC on only the odd-index data bytes.
+        //
+        ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 8);
+        ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 24);
+    }
+
+    //
+    // Return the resulting CRC-16 values.
+    //
+    pui16Crc3[0] = ui16Crc;
+    pui16Crc3[1] = ui16Cri8Even;
+    pui16Crc3[2] = ui16Cri8Odd;
+}
+
+//*****************************************************************************
+//
+//! Calculates the CRC-32 of an array of bytes.
+//!
+//! \param ui32Crc is the starting CRC-32 value.
+//! \param pui8Data is a pointer to the data buffer.
+//! \param ui32Count is the number of bytes in the data buffer.
+//!
+//! This function is used to calculate the CRC-32 of the input buffer.  The
+//! CRC-32 is computed in a running fashion, meaning that the entire data block
+//! that is to have its CRC-32 computed does not need to be supplied all at
+//! once.  If the input buffer contains the entire block of data, then
+//! \b ui32Crc should be set to 0xFFFFFFFF.  If, however, the entire block of
+//! data is not available, then \b ui32Crc should be set to 0xFFFFFFFF for the
+//! first portion of the data, and then the returned value should be passed
+//! back in as \b ui32Crc for the next portion of the data.  Once all data has
+//! been passed to the function, the final CRC-32 can be obtained by inverting
+//! the last returned value.
+//!
+//! For example, to compute the CRC-32 of a block that has been split into
+//! three pieces, use the following:
+//!
+//! \verbatim
+//!     ui32Crc = Crc32(0xFFFFFFFF, pui8Data1, ui32Len1);
+//!     ui32Crc = Crc32(ui32Crc, pui8Data2, ui32Len2);
+//!     ui32Crc = Crc32(ui32Crc, pui8Data3, ui32Len3);
+//!     ui32Crc ^= 0xFFFFFFFF;
+//! \endverbatim
+//!
+//! Computing a CRC-32 in a running fashion is useful in cases where the data
+//! is arriving via a serial link (for example) and is therefore not all
+//! available at one time.
+//!
+//! \return The accumulated CRC-32 of the input data.
+//
+//*****************************************************************************
+uint32_t
+Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, uint32_t ui32Count)
+{
+    uint32_t ui32Temp;
+
+    //
+    // If the data buffer is not 16 bit-aligned, then perform a single step
+    // of the CRC to make it 16 bit-aligned.
+    //
+    if((uint32_t)pui8Data & 1)
+    {
+        //
+        // Perform the CRC on this input byte.
+        //
+        ui32Crc = CRC32_ITER(ui32Crc, *pui8Data);
+
+        //
+        // Skip this input byte.
+        //
+        pui8Data++;
+        ui32Count--;
+    }
+
+    //
+    // If the data buffer is not word-aligned and there are at least two bytes
+    // of data left, then perform two steps of the CRC to make it word-aligned.
+    //
+    if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
+    {
+        //
+        // Read the next int16_t.
+        //
+        ui32Temp = *(uint16_t *)pui8Data;
+
+        //
+        // Perform the CRC on these two bytes.
+        //
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 2;
+        ui32Count -= 2;
+    }
+
+    //
+    // While there is at least a word remaining in the data buffer, perform
+    // four steps of the CRC to consume a word.
+    //
+    while(ui32Count > 3)
+    {
+        //
+        // Read the next word.
+        //
+        ui32Temp = *(uint32_t *)pui8Data;
+
+        //
+        // Perform the CRC on these four bytes.
+        //
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 16);
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 24);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 4;
+        ui32Count -= 4;
+    }
+
+    //
+    // If there are 16 bits left in the input buffer, then perform two steps of
+    // the CRC.
+    //
+    if(ui32Count > 1)
+    {
+        //
+        // Read the two bytes.
+        //
+        ui32Temp = *(uint16_t *)pui8Data;
+
+        //
+        // Perform the CRC on these two bytes.
+        //
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
+        ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
+
+        //
+        // Skip these input bytes.
+        //
+        pui8Data += 2;
+        ui32Count -= 2;
+    }
+
+    //
+    // If there is a final byte remaining in the input buffer, then perform a
+    // single step of the CRC.
+    //
+    if(ui32Count != 0)
+    {
+        ui32Crc = CRC32_ITER(ui32Crc, *pui8Data);
+    }
+
+    //
+    // Return the resulting CRC-32 value.
+    //
+    return(ui32Crc);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/sw_crc.h b/bsp/tm4c129x/libraries/driverlib/sw_crc.h
new file mode 100644
index 0000000000..6fd23b3310
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/sw_crc.h
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// sw_crc.h - Prototypes for the software CRC functions.
+//
+// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SW_CRC_H__
+#define __DRIVERLIB_SW_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the functions.
+//
+//*****************************************************************************
+extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data,
+                         uint32_t ui32Count);
+extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data,
+                      uint32_t ui32Count);
+extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data);
+extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
+                        uint16_t *pui16Crc3);
+extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data,
+                      uint32_t ui32Count);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SW_CRC_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/sysctl.c b/bsp/tm4c129x/libraries/driverlib/sysctl.c
new file mode 100644
index 0000000000..8eb57ff864
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/sysctl.c
@@ -0,0 +1,3699 @@
+//*****************************************************************************
+//
+// sysctl.c - Driver for the system controller.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_flash.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// The flash shift used in the math to calculate the flash sector size.
+//
+//*****************************************************************************
+#ifndef FLASH_PP_MAINSS_S
+#define FLASH_PP_MAINSS_S       16
+#endif
+
+//*****************************************************************************
+//
+// This macro converts the XTAL value provided in the ui32Config parameter to
+// an index to the g_pui32Xtals array.
+//
+//*****************************************************************************
+#define SysCtlXtalCfgToIndex(a) ((a & 0x7c0) >> 6)
+
+//*****************************************************************************
+//
+// An array that maps the crystal number in RCC to a frequency.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Xtals[] =
+{
+    1000000,
+    1843200,
+    2000000,
+    2457600,
+    3579545,
+    3686400,
+    4000000,
+    4096000,
+    4915200,
+    5000000,
+    5120000,
+    6000000,
+    6144000,
+    7372800,
+    8000000,
+    8192000,
+    10000000,
+    12000000,
+    12288000,
+    13560000,
+    14318180,
+    16000000,
+    16384000,
+    18000000,
+    20000000,
+    24000000,
+    25000000
+};
+
+//*****************************************************************************
+//
+// Maximum number of VCO entries in the g_pui32XTALtoVCO and
+// g_pui32VCOFrequencies structures for a device.
+//
+//*****************************************************************************
+#define MAX_VCO_ENTRIES         2
+#define MAX_XTAL_ENTRIES        18
+
+//*****************************************************************************
+//
+// These macros are used in the g_pui32XTALtoVCO table to make it more
+// readable.
+//
+//*****************************************************************************
+#define PLL_M_TO_REG(mi, mf)                                                  \
+        ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S))
+#define PLL_N_TO_REG(n)                                                       \
+        ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S)
+
+//*****************************************************************************
+//
+// Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers.
+//
+//*****************************************************************************
+static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][2] =
+{
+    {
+        //
+        // VCO 320 MHz
+        //
+        { PLL_M_TO_REG(64, 0),   PLL_N_TO_REG(1) },     // 5 MHz
+        { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1) },     // 5.12 MHz
+        { PLL_M_TO_REG(160, 0),  PLL_N_TO_REG(3) },     // 6 MHz
+        { PLL_M_TO_REG(52, 85),  PLL_N_TO_REG(1) },     // 6.144 MHz
+        { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1) },     // 7.3728 MHz
+        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(1) },     // 8 MHz
+        { PLL_M_TO_REG(39, 64),  PLL_N_TO_REG(1) },     // 8.192 MHz
+        { PLL_M_TO_REG(32, 0),   PLL_N_TO_REG(1) },     // 10 MHz
+        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(3) },     // 12 MHz
+        { PLL_M_TO_REG(26, 43),  PLL_N_TO_REG(1) },     // 12.288 MHz
+        { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1) },     // 13.56 MHz
+        { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1) },     // 14.318180 MHz
+        { PLL_M_TO_REG(20, 0),   PLL_N_TO_REG(1) },     // 16 MHz
+        { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1) },     // 16.384 MHz
+        { PLL_M_TO_REG(160, 0),  PLL_N_TO_REG(9) },     // 18 MHz
+        { PLL_M_TO_REG(16, 0),   PLL_N_TO_REG(1) },     // 20 MHz
+        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(3) },     // 24 MHz
+        { PLL_M_TO_REG(64, 0),   PLL_N_TO_REG(5) },     // 25 MHz
+    },
+    {
+        //
+        // VCO 480 MHz
+        //
+        { PLL_M_TO_REG(96, 0),   PLL_N_TO_REG(1) },     // 5 MHz
+        { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1) },     // 5.12 MHz
+        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(1) },     // 6 MHz
+        { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1) },     // 6.144 MHz
+        { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1) },     // 7.3728 MHz
+        { PLL_M_TO_REG(60, 0),   PLL_N_TO_REG(1) },     // 8 MHz
+        { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1) },     // 8.192 MHz
+        { PLL_M_TO_REG(48, 0),   PLL_N_TO_REG(1) },     // 10 MHz
+        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(1) },     // 12 MHz
+        { PLL_M_TO_REG(39, 64),  PLL_N_TO_REG(1) },     // 12.288 MHz
+        { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1) },     // 13.56 MHz
+        { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1) },     // 14.318180 MHz
+        { PLL_M_TO_REG(30, 0),   PLL_N_TO_REG(1) },     // 16 MHz
+        { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1) },     // 16.384 MHz
+        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(3) },     // 18 MHz
+        { PLL_M_TO_REG(24, 0),   PLL_N_TO_REG(1) },     // 20 MHz
+        { PLL_M_TO_REG(20, 0),   PLL_N_TO_REG(1) },     // 24 MHz
+        { PLL_M_TO_REG(96, 0),   PLL_N_TO_REG(5) },     // 25 MHz
+    },
+};
+
+//*****************************************************************************
+//
+// The mapping of system clock frequency to flash memory timing parameters.
+//
+//*****************************************************************************
+static const struct
+{
+    uint32_t ui32Frequency;
+    uint32_t ui32MemTiming;
+}
+g_sXTALtoMEMTIM[] =
+{
+    { 16000000, (SYSCTL_MEMTIM0_FBCHT_0_5 | SYSCTL_MEMTIM0_FBCE |
+                 (0 << SYSCTL_MEMTIM0_FWS_S) |
+                 SYSCTL_MEMTIM0_EBCHT_0_5 | SYSCTL_MEMTIM0_EBCE |
+                 (0 << SYSCTL_MEMTIM0_EWS_S) |
+                 SYSCTL_MEMTIM0_MB1) },
+    { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) |
+                 SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) |
+                 SYSCTL_MEMTIM0_MB1) },
+    { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) |
+                 SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) |
+                 SYSCTL_MEMTIM0_MB1) },
+    { 80000000, (SYSCTL_MEMTIM0_FBCHT_2_5 | (3 << SYSCTL_MEMTIM0_FWS_S) |
+                 SYSCTL_MEMTIM0_EBCHT_2_5 | (3 << SYSCTL_MEMTIM0_EWS_S) |
+                 SYSCTL_MEMTIM0_MB1) },
+    { 100000000, (SYSCTL_MEMTIM0_FBCHT_3 | (4 << SYSCTL_MEMTIM0_FWS_S) |
+                  SYSCTL_MEMTIM0_EBCHT_3 | (4 << SYSCTL_MEMTIM0_EWS_S) |
+                  SYSCTL_MEMTIM0_MB1) },
+    { 120000000, (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) |
+                  SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) |
+                  SYSCTL_MEMTIM0_MB1) },
+};
+
+//*****************************************************************************
+//
+// Get the correct memory timings for a given system clock value.
+//
+//*****************************************************************************
+static uint32_t
+_SysCtlMemTimingGet(uint32_t ui32SysClock)
+{
+    uint_fast8_t ui8Idx;
+
+    //
+    // Loop through the flash memory timings.
+    //
+    for(ui8Idx = 0;
+        ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0]));
+        ui8Idx++)
+    {
+        //
+        // See if the system clock frequency is less than the maximum frequency
+        // for this flash memory timing.
+        //
+        if(ui32SysClock <= g_sXTALtoMEMTIM[ui8Idx].ui32Frequency)
+        {
+            //
+            // This flash memory timing is the best choice for the system clock
+            // frequency, so return it now.
+            //
+            return(g_sXTALtoMEMTIM[ui8Idx].ui32MemTiming);
+        }
+    }
+
+    //
+    // An appropriate flash memory timing could not be found, so the device is
+    // being clocked too fast.  Return the default flash memory timing.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+// Calculate the system frequency from the register settings base on the
+// oscillator input.
+//
+//*****************************************************************************
+static uint32_t
+_SysCtlFrequencyGet(uint32_t ui32Xtal)
+{
+    uint32_t ui32Result;
+    uint_fast16_t ui16F1, ui16F2;
+    uint_fast16_t ui16PInt, ui16PFract;
+    uint_fast8_t ui8Q, ui8N;
+
+    //
+    // Extract all of the values from the hardware registers.
+    //
+    ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >>
+                  SYSCTL_PLLFREQ0_MFRAC_S);
+    ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M;
+    ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >>
+             SYSCTL_PLLFREQ1_Q_S) + 1);
+    ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >>
+             SYSCTL_PLLFREQ1_N_S) + 1);
+
+    //
+    // Divide the crystal value by N.
+    //
+    ui32Xtal /= (uint32_t)ui8N;
+
+    //
+    // Calculate the multiplier for bits 9:5.
+    //
+    ui16F1 = ui16PFract / 32;
+
+    //
+    // Calculate the multiplier for bits 4:0.
+    //
+    ui16F2 = ui16PFract - (ui16F1 * 32);
+
+    //
+    // Get the integer portion.
+    //
+    ui32Result = ui32Xtal * (uint32_t)ui16PInt;
+
+    //
+    // Add first fractional bits portion(9:0).
+    //
+    ui32Result += (ui32Xtal * (uint32_t)ui16F1) / 32;
+
+    //
+    // Add the second fractional bits portion(4:0).
+    //
+    ui32Result += (ui32Xtal * (uint32_t)ui16F2) / 1024;
+
+    //
+    // Divide the result by Q.
+    //
+    ui32Result = ui32Result / (uint32_t)ui8Q;
+
+    //
+    // Return the resulting PLL frequency.
+    //
+    return(ui32Result);
+}
+
+//*****************************************************************************
+//
+// Look up of the possible VCO frequencies.
+//
+//*****************************************************************************
+static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] =
+{
+    320000000,                              // VCO 320
+    480000000,                              // VCO 480
+};
+
+//*****************************************************************************
+//
+// The base addresses of the various peripheral control registers.
+//
+//*****************************************************************************
+#define SYSCTL_PPBASE           0x400fe300
+#define SYSCTL_SRBASE           0x400fe500
+#define SYSCTL_RCGCBASE         0x400fe600
+#define SYSCTL_SCGCBASE         0x400fe700
+#define SYSCTL_DCGCBASE         0x400fe800
+#define SYSCTL_PCBASE           0x400fe900
+#define SYSCTL_PRBASE           0x400fea00
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a peripheral identifier.
+//!
+//! \param ui32Peripheral is the peripheral identifier.
+//!
+//! This function determines if a peripheral identifier is valid.
+//!
+//! \return Returns \b true if the peripheral identifier is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_SysCtlPeripheralValid(uint32_t ui32Peripheral)
+{
+    return((ui32Peripheral == SYSCTL_PERIPH_ADC0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_ADC1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_CAN0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_CAN1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_COMP0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_CCM0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_EEPROM0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_EPHY0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_EMAC0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_EPI0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_FAN0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOA) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOB) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOC) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOD) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOE) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOF) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOG) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOH) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOJ) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOK) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOL) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOM) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPION) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOP) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOQ) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOR) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOS) ||
+           (ui32Peripheral == SYSCTL_PERIPH_GPIOT) ||
+           (ui32Peripheral == SYSCTL_PERIPH_HIBERNATE) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C2) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C3) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C4) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C5) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C6) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C7) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C8) ||
+           (ui32Peripheral == SYSCTL_PERIPH_I2C9) ||
+           (ui32Peripheral == SYSCTL_PERIPH_LCD0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_PWM0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_PWM1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_QEI0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_QEI1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_SSI0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_SSI1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_SSI2) ||
+           (ui32Peripheral == SYSCTL_PERIPH_SSI3) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER2) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER3) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER4) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER5) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART2) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART3) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART4) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART5) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART6) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UART7) ||
+           (ui32Peripheral == SYSCTL_PERIPH_UDMA) ||
+           (ui32Peripheral == SYSCTL_PERIPH_USB0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WDOG0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WDOG1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WTIMER0) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WTIMER1) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WTIMER2) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WTIMER3) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WTIMER4) ||
+           (ui32Peripheral == SYSCTL_PERIPH_WTIMER5));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! This function determines the size of the SRAM on the Tiva device.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+uint32_t
+SysCtlSRAMSizeGet(void)
+{
+    return((HWREG(FLASH_SSIZE) + 1) * 256);
+}
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! This function determines the size of the flash on the Tiva device.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+uint32_t
+SysCtlFlashSizeGet(void)
+{
+
+    //
+    // TM4C123 devices report the flash size in DC0.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        //
+        // Compute the size of the flash.
+        //
+        return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
+    }
+    else
+    {
+        //
+        // Get the flash size from the FLASH_PP register.
+        //
+        return(2048 * ((HWREG(FLASH_PP) & FLASH_PP_SIZE_M) + 1));
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the size of a single eraseable sector of flash.
+//!
+//! This function determines the flash sector size on the Tiva device.
+//! This size determines the erase granularity of the device flash.
+//!
+//! \return The number of bytes in a single flash sector.
+//
+//*****************************************************************************
+uint32_t
+SysCtlFlashSectorSizeGet(void)
+{
+    //
+    // TM4C129 devices store the value in a different register.
+    //
+    if(CLASS_IS_TM4C129)
+    {
+        //
+        // Get the flash sector size from the FLASH_PP register.
+        //
+        return(1 << (10 +
+                     ((HWREG(FLASH_PP) &
+                       FLASH_PP_MAINSS_M) >> FLASH_PP_MAINSS_S)));
+    }
+    else
+    {
+        //
+        // The sector size is fixed at 1KB.
+        //
+        return(1024);
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is present.
+//!
+//! \param ui32Peripheral is the peripheral in question.
+//!
+//! This function determines if a particular peripheral is present in the
+//! device.  Each member of the Tiva family has a different peripheral
+//! set; this function determines which peripherals are present on this device.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return Returns \b true if the specified peripheral is present and \b false
+//! if it is not.
+//
+//*****************************************************************************
+bool
+SysCtlPeripheralPresent(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // See if this peripheral is present.
+    //
+    return(HWREGBITW(SYSCTL_PPBASE + ((ui32Peripheral & 0xff00) >> 8),
+                     ui32Peripheral & 0xff));
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is ready.
+//!
+//! \param ui32Peripheral is the peripheral in question.
+//!
+//! This function determines if a particular peripheral is ready to be
+//! accessed.  The peripheral may be in a non-ready state if it is not enabled,
+//! is being held in reset, or is in the process of becoming ready after being
+//! enabled or taken out of reset.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \note The ability to check for a peripheral being ready varies based on the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine if this feature is available.
+//!
+//! \return Returns \b true if the specified peripheral is ready and \b false
+//! if it is not.
+//
+//*****************************************************************************
+bool
+SysCtlPeripheralReady(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // See if this peripheral is ready.
+    //
+    return(HWREGBITW(SYSCTL_PRBASE + ((ui32Peripheral & 0xff00) >> 8),
+                     ui32Peripheral & 0xff));
+}
+
+//*****************************************************************************
+//
+//! Powers on a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to be powered on.
+//!
+//! This function turns on the power to a peripheral.  The peripheral continues
+//! to receive power even when its clock is not enabled.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC,
+//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0
+//!
+//! \note The ability to power off a peripheral varies based on the Tiva
+//! part in use.  Please consult the data sheet for the part you are using to
+//! determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralPowerOn(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Power on this peripheral.
+    //
+    HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Powers off a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to be powered off.
+//!
+//! This function allows the power to a peripheral to be turned off.  The
+//! peripheral continues to receive power when its clock is enabled, but
+//! the power is removed when its clock is disabled.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC,
+//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0
+//!
+//! \note The ability to power off a peripheral varies based on the Tiva
+//! part in use.  Please consult the data sheet for the part you are using to
+//! determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralPowerOff(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Power off this peripheral.
+    //
+    HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to reset.
+//!
+//! This function performs a software reset of the specified peripheral.  An
+//! individual peripheral reset signal is asserted for a brief period and then
+//! de-asserted, returning the internal state of the peripheral to its reset
+//! condition.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralReset(uint32_t ui32Peripheral)
+{
+    volatile uint_fast8_t ui8Delay;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Put the peripheral into the reset state.
+    //
+    HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 1;
+
+    //
+    // Delay for a little bit.
+    //
+    for(ui8Delay = 0; ui8Delay < 16; ui8Delay++)
+    {
+    }
+
+    //
+    // Take the peripheral out of the reset state.
+    //
+    HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to enable.
+//!
+//! This function enables a peripheral.  At power-up, all peripherals are
+//! disabled; they must be enabled in order to operate or respond to register
+//! reads/writes.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \note It takes five clock cycles after the write to enable a peripheral
+//! before the the peripheral is actually enabled.  During this time, attempts
+//! to access the peripheral result in a bus fault.  Care should be taken
+//! to ensure that the peripheral is not accessed during this brief time
+//! period.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralEnable(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Enable this peripheral.
+    //
+    HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to disable.
+//!
+//! This function disables a peripheral.  Once disabled, they do not operate or
+//! respond to register reads/writes.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDisable(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Disable this peripheral.
+    //
+    HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to enable in sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into sleep mode.  Because the clocking configuration of the device
+//! does not change, any peripheral can safely continue operating while the
+//! processor is in sleep mode and can therefore wake the processor from sleep
+//! mode.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Enable this peripheral in sleep mode.
+    //
+    HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to disable in sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into sleep mode.  Disabling peripherals while in sleep mode helps to lower
+//! the current draw of the device.  If enabled (via SysCtlPeripheralEnable()),
+//! the peripheral automatically resumes operation when the processor
+//! leaves sleep mode, maintaining its entire state from before sleep mode was
+//! entered.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Disable this peripheral in sleep mode.
+    //
+    HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in deep-sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into deep-sleep mode.  Because the clocking configuration of the
+//! device may change, not all peripherals can safely continue operating while
+//! the processor is in deep-sleep mode.  Those that must run at a particular
+//! frequency (such as a UART) do not work as expected if the clock changes.
+//! It is the responsibility of the caller to make sensible choices.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Enable this peripheral in deep-sleep mode.
+    //
+    HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in deep-sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into deep-sleep mode.  Disabling peripherals while in deep-sleep mode helps
+//! to lower the current draw of the device, and can keep peripherals that
+//! require a particular clock frequency from operating when the clock changes
+//! as a result of entering deep-sleep mode.  If enabled (via
+//! SysCtlPeripheralEnable()), the peripheral automatically resumes
+//! operation when the processor leaves deep-sleep mode, maintaining its entire
+//! state from before deep-sleep mode was entered.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
+//! \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
+//! \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
+//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
+//! \b SYSCTL_PERIPH_ONEWIRE0,
+//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
+//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
+//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
+//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
+//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+    //
+    // Disable this peripheral in deep-sleep mode.
+    //
+    HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+              ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Controls peripheral clock gating in sleep and deep-sleep mode.
+//!
+//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
+//! peripheral configuration should be used and \b false if not.
+//!
+//! This function controls how peripherals are clocked when the processor goes
+//! into sleep or deep-sleep mode.  By default, the peripherals are clocked the
+//! same as in run mode; if peripheral clock gating is enabled, they are
+//! clocked according to the configuration set by
+//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(),
+//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralClockGating(bool bEnable)
+{
+    if(CLASS_IS_TM4C123)
+    {
+        //
+        // Enable peripheral clock gating as requested.
+        //
+        if(bEnable)
+        {
+            HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
+        }
+        else
+        {
+            HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
+        }
+    }
+    else
+    {
+        //
+        // Enable peripheral clock gating as requested.
+        //
+        if(bEnable)
+        {
+            HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_ACG;
+        }
+        else
+        {
+            HWREG(SYSCTL_RSCLKCFG) &= ~SYSCTL_RSCLKCFG_ACG;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system control interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! control interrupt occurs.
+//!
+//! This function registers the handler to be called when a system control
+//! interrupt occurs.  This function enables the global interrupt in the
+//! interrupt controller; specific system control interrupts must be enabled
+//! via SysCtlIntEnable().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via SysCtlIntClear().
+//!
+//! System control can generate interrupts when the PLL achieves lock, if the
+//! internal LDO current limit is exceeded, if the internal oscillator fails,
+//! if the main oscillator fails, if the internal LDO output voltage droops too
+//! much, if the external voltage droops too much, or if the PLL fails.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The events that cause system control interrupts vary based on the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntRegister(void (*pfnHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(INT_SYSCTL_TM4C123, pfnHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    IntEnable(INT_SYSCTL_TM4C123);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the system control interrupt.
+//!
+//! This function unregisters the handler to be called when a system control
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntUnregister(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_SYSCTL_TM4C123);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_SYSCTL_TM4C123);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system control interrupt sources.
+//!
+//! \param ui32Ints is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
+//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
+//! \b SYSCTL_INT_BOR1.
+//!
+//! This function enables the indicated system control interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntEnable(uint32_t ui32Ints)
+{
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(SYSCTL_IMC) |= ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system control interrupt sources.
+//!
+//! \param ui32Ints is a bit mask of the interrupt sources to be disabled.
+//! Must be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
+//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
+//! \b SYSCTL_INT_BOR1.
+//!
+//! This function disables the indicated system control interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntDisable(uint32_t ui32Ints)
+{
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(SYSCTL_IMC) &= ~(ui32Ints);
+}
+
+//*****************************************************************************
+//
+//! Clears system control interrupt sources.
+//!
+//! \param ui32Ints is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
+//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
+//! \b SYSCTL_INT_BOR1.
+//!
+//! The specified system control interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately on exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntClear(uint32_t ui32Ints)
+{
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(SYSCTL_MISC) = ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the system controller.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
+//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
+//! \b SYSCTL_INT_BOR1.
+//
+//*****************************************************************************
+uint32_t
+SysCtlIntStatus(bool bMasked)
+{
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(SYSCTL_MISC));
+    }
+    else
+    {
+        return(HWREG(SYSCTL_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the output voltage of the LDO when the device enters sleep mode.
+//!
+//! \param ui32Voltage is the required output voltage from the LDO while in
+//! sleep mode.
+//!
+//! This function sets the output voltage of the LDO while in sleep mode.
+//! The \e ui32Voltage parameter must be one of the following values:
+//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V,
+//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or
+//! \b SYSCTL_LDO_1_20V.
+//!
+//! \note The availability of this feature, the default LDO voltage, and the
+//! adjustment range varies with the Tiva part in use.  Please consult the
+//! data sheet for the part you are using to determine whether this support is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOSleepSet(uint32_t ui32Voltage)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) ||
+           (ui32Voltage == SYSCTL_LDO_0_95V) ||
+           (ui32Voltage == SYSCTL_LDO_1_00V) ||
+           (ui32Voltage == SYSCTL_LDO_1_05V) ||
+           (ui32Voltage == SYSCTL_LDO_1_10V) ||
+           (ui32Voltage == SYSCTL_LDO_1_15V) ||
+           (ui32Voltage == SYSCTL_LDO_1_20V));
+
+    //
+    // Set the sleep-mode LDO voltage to the requested value.
+    //
+    HWREG(SYSCTL_LDOSPCTL) = ui32Voltage;
+}
+
+//*****************************************************************************
+//
+//! Returns the output voltage of the LDO when the device enters sleep mode.
+//!
+//! This function determines the output voltage of the LDO while in sleep mode,
+//! as specified by the control register.
+//!
+//! \note The availability of this feature, the default LDO voltage, and the
+//! adjustment range varies with the Tiva part in use.  Please consult the
+//! data sheet for the part you are using to determine whether this support is
+//! available.
+//!
+//! \return Returns the sleep-mode voltage of the LDO and is one of
+//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V,
+//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or
+//! \b SYSCTL_LDO_1_20V.
+//
+//*****************************************************************************
+uint32_t
+SysCtlLDOSleepGet(void)
+{
+    //
+    // Return the sleep-mode LDO voltage setting.
+    //
+    return(HWREG(SYSCTL_LDOSPCTL));
+}
+
+//*****************************************************************************
+//
+//! Sets the output voltage of the LDO when the device enters deep-sleep
+//! mode.
+//!
+//! \param ui32Voltage is the required output voltage from the LDO while in
+//! deep-sleep mode.
+//!
+//! This function sets the output voltage of the LDO while in deep-sleep mode.
+//! The \e ui32Voltage parameter specifies the output voltage of the LDO and
+//! must be one of the following values: \b SYSCTL_LDO_0_90V,
+//! \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, \b SYSCTL_LDO_1_05V,
+//! \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or \b SYSCTL_LDO_1_20V.
+//!
+//! \note The availability of this feature, the default LDO voltage, and the
+//! adjustment range varies with the Tiva part in use.  Please consult the
+//! data sheet for the part you are using to determine whether this support is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDODeepSleepSet(uint32_t ui32Voltage)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) ||
+           (ui32Voltage == SYSCTL_LDO_0_95V) ||
+           (ui32Voltage == SYSCTL_LDO_1_00V) ||
+           (ui32Voltage == SYSCTL_LDO_1_05V) ||
+           (ui32Voltage == SYSCTL_LDO_1_10V) ||
+           (ui32Voltage == SYSCTL_LDO_1_15V) ||
+           (ui32Voltage == SYSCTL_LDO_1_20V));
+
+    //
+    // Set the deep-sleep LDO voltage to the requested value.
+    //
+    HWREG(SYSCTL_LDODPCTL) = ui32Voltage;
+}
+
+//*****************************************************************************
+//
+//! Returns the output voltage of the LDO when the device enters deep-sleep
+//! mode.
+//!
+//! This function returns the output voltage of the LDO when the device is
+//! in deep-sleep mode, as specified by the control register.
+//!
+//! \note The availability of this feature, the default LDO voltage, and the
+//! adjustment range varies with the Tiva part in use.  Please consult the
+//! data sheet for the part you are using to determine whether this support is
+//! available.
+//!
+//! \return Returns the deep-sleep-mode voltage of the LDO; is one of
+//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V,
+//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or
+//! \b SYSCTL_LDO_1_20V.
+//
+//*****************************************************************************
+uint32_t
+SysCtlLDODeepSleepGet(void)
+{
+    //
+    // Return the deep-sleep-mode LDO voltage setting.
+    //
+    return(HWREG(SYSCTL_LDODPCTL));
+}
+
+//*****************************************************************************
+//
+//! Configures the power to the flash and SRAM while in sleep mode.
+//!
+//! \param ui32Config is the required flash and SRAM power configuration.
+//!
+//! This function allows the power configuration of the flash and SRAM while in
+//! sleep mode to be set.  The \e ui32Config parameter is the logical OR of the
+//! flash power configuration and the SRAM power configuration.
+//!
+//! The flash power configuration is specified as either:
+//!
+//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode,
+//!    providing fast wake-up time but higher power consumption.
+//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing
+//!   reduced power consumption but longer wake-up time.
+//!
+//! The SRAM power configuration is specified as one of:
+//!
+//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing
+//!   fast wake-up time but higher power consumption.
+//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode,
+//!   providing reduced power consumption but longer wake-up time.
+//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode,
+//!   providing further reduced power consumption but longer wake-up time.
+//!
+//! \note The availability of this feature varies with the Tiva part in
+//! use.  Please consult the data sheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlSleepPowerSet(uint32_t ui32Config)
+{
+    //
+    // Set the sleep-mode flash and SRAM power configuration.
+    //
+    HWREG(SYSCTL_SLPPWRCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Configures the power to the flash and SRAM while in deep-sleep mode.
+//!
+//! \param ui32Config is the required flash and SRAM power configuration.
+//!
+//! This function allows the power configuration of the flash and SRAM while in
+//! deep-sleep mode to be set.  The \e ui32Config parameter is the logical OR
+//! of the flash power configuration and the SRAM power configuration.
+//!
+//! The flash power configuration is specified as either:
+//!
+//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode,
+//!    providing fast wake-up time but higher power consumption.
+//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing
+//!   reduced power consumption but longer wake-up time.
+//!
+//! The SRAM power configuration is specified as one of:
+//!
+//! - \b SYSCTL_LDO_SLEEP - The LDO is in sleep mode.
+//! - \b SYSCTL_TEMP_LOW_POWER - The temperature sensor in low power mode.
+//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing
+//!   fast wake-up time but higher power consumption.
+//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode,
+//!   providing reduced power consumption but longer wake-up time.
+//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode,
+//!   providing further reduced power consumption but longer wake-up time.
+//!
+//! \note The availability of this feature varies with the Tiva part in
+//! use.  Please consult the data sheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleepPowerSet(uint32_t ui32Config)
+{
+    //
+    // Set the deep-sleep-mode flash and SRAM power configuration.
+    //
+    HWREG(SYSCTL_DSLPPWRCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Resets the device.
+//!
+//! This function performs a software reset of the entire device.  The
+//! processor and all peripherals are reset and all device registers are
+//! returned to their default values (with the exception of the reset cause
+//! register, which maintains its current value but has the software reset
+//! bit set as well).
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+void
+SysCtlReset(void)
+{
+    //
+    // Perform a software reset request.  This request causes the device to
+    // reset, no further code is executed.
+    //
+    HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
+
+    //
+    // The device should have reset, so this should never be reached.  Just in
+    // case, loop forever.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into sleep mode.
+//!
+//! This function places the processor into sleep mode; it does not return
+//! until the processor returns to run mode.  The peripherals that are enabled
+//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
+//! processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlSleep(void)
+{
+    //
+    // Wait for an interrupt.
+    //
+    CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into deep-sleep mode.
+//!
+//! This function places the processor into deep-sleep mode; it does not return
+//! until the processor returns to run mode.  The peripherals that are enabled
+//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
+//! the processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleep(void)
+{
+    //
+    // Enable deep-sleep.
+    //
+    HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
+
+    //
+    // Wait for an interrupt.
+    //
+    CPUwfi();
+
+    //
+    // Disable deep-sleep so that a future sleep works correctly.
+    //
+    HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function returns the reason(s) for a reset.  Because the reset
+//! reasons are sticky until either cleared by software or a power-on reset,
+//! multiple reset reasons may be returned if multiple resets have occurred.
+//! The reset reason is a logical OR of \b SYSCTL_CAUSE_HSRVREQ,
+//! \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, \b SYSCTL_CAUSE_SW,
+//! \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR,
+//! and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! \return Returns the reason(s) for a reset.
+//
+//*****************************************************************************
+uint32_t
+SysCtlResetCauseGet(void)
+{
+    //
+    // Return the reset reasons.
+    //
+    return(HWREG(SYSCTL_RESC));
+}
+
+//*****************************************************************************
+//
+//! Clears reset reasons.
+//!
+//! \param ui32Causes are the reset causes to be cleared; must be a logical OR
+//! of \b SYSCTL_CAUSE_HSRVREQ, \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1,
+//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR,
+//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! This function clears the specified sticky reset reasons.  Once cleared,
+//! another reset for the same reason can be detected, and a reset for a
+//! different reason can be distinguished (instead of having two reset causes
+//! set).  If the reset reason is used by an application, all reset causes
+//! should be cleared after they are retrieved with SysCtlResetCauseGet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlResetCauseClear(uint32_t ui32Causes)
+{
+    //
+    // Clear the given reset reasons.
+    //
+    HWREG(SYSCTL_RESC) &= ~(ui32Causes);
+}
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ui32Count is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a delay by executing a simple
+//! 3 instruction cycle loop a given number of times.  It is written in
+//! assembly to keep the loop instruction count consistent across tool chains.
+//!
+//! It is important to note that this function does NOT provide an accurate
+//! timing mechanism.  Although the delay loop is 3 instruction cycles long,
+//! the execution time of the loop will vary dramatically depending upon the
+//! application's interrupt environment (the loop will be interrupted unless
+//! run with interrupts disabled and this is generally an unwise thing to do)
+//! and also the current system clock rate and flash timings (wait states and
+//! the operation of the prefetch buffer affect the timing).
+//!
+//! For better accuracy, the ROM version of this function may be used.  This
+//! version will not suffer from flash- and prefect buffer-related timing
+//! variability but will still be delayed by interrupt service routines.
+//!
+//! For best accuracy, a system timer should be used with code either polling
+//! for a particular timer value being exceeded or processing the timer
+//! interrupt to determine when a particular time period has elapsed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+SysCtlDelay(uint32_t ui32Count)
+{
+    __asm("    subs    r0, #1\n"
+          "    bne.n   SysCtlDelay\n"
+          "    bx      lr");
+}
+#endif
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+SysCtlDelay(uint32_t ui32Count)
+{
+    __asm("    subs    r0, #1\n"
+          "    bne     SysCtlDelay\n"
+          "    bx      lr");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+SysCtlDelay(uint32_t ui32Count)
+{
+    subs    r0, #1;
+    bne     SysCtlDelay;
+    bx      lr;
+}
+#endif
+//
+// For CCS implement this function in pure assembly.  This prevents the TI
+// compiler from doing funny things with the optimizer.
+//
+#if defined(ccs)
+__asm("    .sect \".text:SysCtlDelay\"\n"
+      "    .clink\n"
+      "    .thumbfunc SysCtlDelay\n"
+      "    .thumb\n"
+      "    .global SysCtlDelay\n"
+      "SysCtlDelay:\n"
+      "    subs r0, #1\n"
+      "    bne.n SysCtlDelay\n"
+      "    bx lr\n");
+#endif
+
+//*****************************************************************************
+//
+//! Sets the configuration of the main oscillator (MOSC) control.
+//!
+//! \param ui32Config is the required configuration of the MOSC control.
+//!
+//! This function configures the control of the main oscillator.  The
+//! \e ui32Config is specified as the logical OR of the following values:
+//!
+//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that
+//!   detects a failure of the main oscillator (such as a loss of the clock).
+//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an
+//!   interrupt instead of resetting the processor.
+//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal or oscillator
+//!   connected to the OSC0/OSC1 pins, allowing power consumption to be
+//!   reduced.
+//! - \b SYSCTL_MOSC_PWR_DIS disable power to the main oscillator.  If this
+//!   parameter is not specified, the MOSC input remains powered.
+//! - \b SYSCTL_MOSC_LOWFREQ MOSC is less than 10 MHz.
+//! - \b SYSCTL_MOSC_HIGHFREQ MOSC is greater than 10 MHz.
+//! - \b SYSCTL_MOSC_SESRC specifies that the MOSC is a single-ended
+//!   oscillator connected to OSC0.  If this parameter is not specified, the
+//!   input is assumed to be a crystal.
+//!
+//! \note The availability of MOSC control varies based on the Tiva part
+//! in use.  Please consult the data sheet for the part you are using to
+//! determine whether this support is available.  In addition, the capability
+//! of MOSC control varies based on the Tiva part in use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlMOSCConfigSet(uint32_t ui32Config)
+{
+    //
+    // Configure the MOSC control.
+    //
+    HWREG(SYSCTL_MOSCCTL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Calibrates the precision internal oscillator.
+//!
+//! \param ui32Type is the type of calibration to perform.
+//!
+//! This function performs a calibration of the PIOSC.  There are three types
+//! of calibration available; the desired calibration type as specified in
+//! \e ui32Type is one of:
+//!
+//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the
+//!   32-kHz clock from the hibernate module as a reference.  This type is
+//!   only possible on parts that have a hibernate module, and then only if
+//!   it is enabled, a 32.768-kHz clock source is attached to the XOSC0/1
+//!   pins and the hibernate module's RTC is also enabled.
+//!
+//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory
+//!   provided calibration.
+//!
+//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied
+//!   value.  The value to be used is ORed into the lower 7-bits of this value,
+//!   with 0x40 being the ``nominal'' value (in other words, if everything were
+//!   perfect, 0x40 provides exactly 16 MHz).  Values larger than 0x40
+//!   slow down PIOSC, and values smaller than 0x40 speed up PIOSC.
+//!
+//! \return Returns 1 if the calibration was successful and 0 if it failed.
+//
+//*****************************************************************************
+uint32_t
+SysCtlPIOSCCalibrate(uint32_t ui32Type)
+{
+    //
+    // Perform the requested calibration.  If performing user calibration, the
+    // UTEN bit must be set with one write, then the UT field in a second
+    // write, and the UPDATE bit in a final write.  For other calibration
+    // types, a single write to set UPDATE or CAL is all that is required.
+    //
+    if(ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE))
+    {
+        HWREG(SYSCTL_PIOSCCAL) = ui32Type & SYSCTL_PIOSCCAL_UTEN;
+        HWREG(SYSCTL_PIOSCCAL) =
+            ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M);
+    }
+    HWREG(SYSCTL_PIOSCCAL) = ui32Type;
+
+    //
+    // See if an automatic calibration was requested.
+    //
+    if(ui32Type & SYSCTL_PIOSCCAL_CAL)
+    {
+        //
+        // Wait for the automatic calibration to complete.
+        //
+        while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0)
+        {
+        }
+
+        //
+        // If the automatic calibration failed, return an error.
+        //
+        if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) !=
+           SYSCTL_PIOSCSTAT_CRPASS)
+        {
+            return(0);
+        }
+    }
+
+    //
+    // The calibration was successful.
+    //
+    return(1);
+}
+
+//*****************************************************************************
+//
+//! Sets the type of reset issued due to certain reset events.
+//!
+//! \param ui32Behavior specifies the types of resets for each of the
+//! configurable reset events.
+//!
+//! This function sets the types of reset issued when a configurable reset
+//! event occurs.  The reset events that are configurable are: Watchdog 0 or 1,
+//! a brown out and the external RSTn pin.  The valid actions are either a
+//! system reset or a full POR sequence.  See the data sheet for more
+//! information on the differences between a full POR and a system reset.  All
+//! reset behaviors can be configured with a single call using the logical OR
+//! of the values defined below.  Any reset option that is not specifically set
+//! remains configured for its default behavior. Either POR or system reset
+//! can be selected for each reset cause.
+//!
+//! Valid values are logical combinations of the following:
+//!
+//! - \b SYSCTL_ONRST_WDOG0_POR configures a Watchdog 0 reset to perform a full
+//!   POR.
+//! - \b SYSCTL_ONRST_WDOG0_SYS configures a Watchdog 0 reset to perform a
+//!   system reset.
+//! - \b SYSCTL_ONRST_WDOG1_POR configures a Watchdog 1 reset to perform a full
+//!   POR.
+//! - \b SYSCTL_ONRST_WDOG1_SYS configures a Watchdog 1 reset to perform a
+//!   system reset.
+//! - \b SYSCTL_ONRST_BOR_POR configures a brown-out reset to perform a full
+//!   POR.
+//! - \b SYSCTL_ONRST_BOR_SYS configures a brown-out reset to perform a system
+//!   reset.
+//! - \b SYSCTL_ONRST_EXT_POR configures an external pin reset to perform a
+//!   full POR.
+//! - \b SYSCTL_ONRST_EXT_SYS configures an external pin reset to perform a
+//!   system reset.
+//!
+//! \b Example: Set Watchdog 0 reset to trigger a POR and a brown-out reset
+//! to trigger a system reset while leaving the remaining resets with their
+//! default behaviors.
+//!
+//! \verbatim
+//! SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_POR | SYSCTL_ONRST_BOR_SYS);
+//! \endverbatim
+//!
+//! \note This function cannot be used with TM4C123 devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlResetBehaviorSet(uint32_t ui32Behavior)
+{
+    HWREG(SYSCTL_RESBEHAVCTL) = ui32Behavior;
+}
+
+//*****************************************************************************
+//
+//! Returns the current types of reset issued due to reset events.
+//!
+//! This function returns the types of resets issued when a configurable reset
+//! occurs.  The value returned is a logical OR combination of the valid values
+//! that are described in the documentation for the \e ui32Behavior parameter
+//! of the SysCtlResetBehaviorSet() function.
+//!
+//! \note This function should only be used with Flurry-class devices.
+//!
+//! \return The reset behaviors for all configurable resets.
+//
+//*****************************************************************************
+uint32_t
+SysCtlResetBehaviorGet(void)
+{
+    return(HWREG(SYSCTL_RESBEHAVCTL));
+}
+
+//*****************************************************************************
+//
+//! Configures the system clock.
+//!
+//! \param ui32Config is the required configuration of the device clocking.
+//! \param ui32SysClock is the requested processor frequency.
+//!
+//! This function configures the main system clocking for the device.  The
+//! input frequency, oscillator source, whether or not to enable the PLL, and
+//! the system clock divider are all configured with this function.  This
+//! function configures the system frequency to the closest available divisor
+//! of one of the fixed PLL VCO settings provided in the \e ui32Config
+//! parameter.  The caller sets the \e ui32SysClock parameter to request the
+//! system clock frequency, and this function then attempts to match this using
+//! the values provided in the \e ui32Config parameter.  If this function
+//! cannot exactly match the requested frequency, it picks the closest
+//! frequency that is lower than the requested frequency.  The \e ui32Config
+//! parameter provides the remaining configuration options using a set of
+//! defines that are a logical OR of several different values, many of which
+//! are grouped into sets where only one of the set can be chosen.  This
+//! function returns the current system frequency which may not match the
+//! requested frequency.
+//!
+//! The oscillator source is chosen with one of the following values:
+//!
+//! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator.
+//! - \b SYSCTL_OSC_INT to use the 16-MHz precision internal oscillator.
+//! - \b SYSCTL_OSC_INT30 to use the internal low frequency oscillator.
+//! - \b SYSCTL_OSC_EXT32 to use the hibernate modules 32.786-kHz oscillator.
+//! This option is only available on devices that include the hibernation
+//! module.
+//!
+//! The system clock source is chosen with one of the following values:
+//!
+//! - \b SYSCTL_USE_PLL is used to select the PLL output as the system clock.
+//! - \b SYSCTL_USE_OSC is used to choose one of the oscillators as the
+//! system clock.
+//!
+//! The PLL VCO frequency is chosen with one of the the following values:
+//!
+//! - \b SYSCTL_CFG_VCO_480 to set the PLL VCO output to 480-MHz
+//! - \b SYSCTL_CFG_VCO_320 to set the PLL VCO output to 320-MHz
+//!
+//! Example: Configure the system clocking to be 40 MHz with a 320-MHz PLL
+//! setting using the 16-MHz internal oscillator.
+//!
+//! \verbatim
+//! SysCtlClockFreqSet(SYSCTL_OSC_INT | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320,
+//!                    40000000);
+//! \endverbatim
+//!
+//! \note This function cannot be used with TM4C123 devices.  For TM4C123
+//! devices use the SysCtlClockSet() function.
+//!
+//! \return The actual configured system clock frequency in Hz or zero if the
+//! value could not be changed due to a parameter error or PLL lock failure.
+//
+//*****************************************************************************
+uint32_t
+SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
+{
+    int32_t i32Timeout, i32VCOIdx, i32XtalIdx;
+    uint32_t ui32MOSCCTL;
+    uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig;
+    bool bNewPLL;
+
+    //
+    // TM4C123 devices should not use this function.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        return(0);
+    }
+
+    //
+    // Get the index of the crystal from the ui32Config parameter.
+    //
+    i32XtalIdx = SysCtlXtalCfgToIndex(ui32Config);
+
+    //
+    // Determine which non-PLL source was selected.
+    //
+    if((ui32Config & 0x38) == SYSCTL_OSC_INT)
+    {
+        //
+        // Use the nominal frequency for the PIOSC oscillator and set the
+        // crystal select.
+        //
+        ui32Osc = 16000000;
+        ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC;
+        ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_PIOSC;
+
+        //
+        // Force the crystal index to the value for 16-MHz.
+        //
+        i32XtalIdx = SysCtlXtalCfgToIndex(SYSCTL_XTAL_16MHZ);
+    }
+    else if((ui32Config & 0x38) == SYSCTL_OSC_INT30)
+    {
+        //
+        // Use the nominal frequency for the low frequency oscillator.
+        //
+        ui32Osc = 30000;
+        ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_LFIOSC;
+    }
+    else if((ui32Config & 0x38) == (SYSCTL_OSC_EXT32 & 0x38))
+    {
+        //
+        // Use the RTC frequency.
+        //
+        ui32Osc = 32768;
+        ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_RTC;
+    }
+    else if((ui32Config & 0x38) == SYSCTL_OSC_MAIN)
+    {
+        //
+        // Bounds check the source frequency for the main oscillator.  The is
+        // because the PLL tables in the g_pppui32XTALtoVCO structure range
+        // from 5MHz to 25MHz.
+        //
+        if((i32XtalIdx > (SysCtlXtalCfgToIndex(SYSCTL_XTAL_25MHZ))) ||
+           (i32XtalIdx < (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ))))
+        {
+            return(0);
+        }
+
+        ui32Osc = g_pui32Xtals[i32XtalIdx];
+
+        //
+        // Set the PLL source select to MOSC.
+        //
+        ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_MOSC;
+        ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_MOSC;
+
+        //
+        // Clear MOSC power down, high oscillator range setting, and no crystal
+        // present setting.
+        //
+        ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) &
+                      ~(SYSCTL_MOSCCTL_OSCRNG | SYSCTL_MOSCCTL_PWRDN |
+                        SYSCTL_MOSCCTL_NOXTAL);
+
+        //
+        // Increase the drive strength for MOSC of 10 MHz and above.
+        //
+        if(i32XtalIdx >= (SysCtlXtalCfgToIndex(SYSCTL_XTAL_10MHZ) -
+                          (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ))))
+        {
+            ui32MOSCCTL |= SYSCTL_MOSCCTL_OSCRNG;
+        }
+
+        HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL;
+    }
+    else
+    {
+        //
+        // This was an invalid request because no oscillator source was
+        // indicated.
+        //
+        ui32Osc = 0;
+        ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC;
+    }
+
+    //
+    // Check if the running with the PLL enabled was requested.
+    //
+    if((ui32Config & SYSCTL_USE_OSC) == SYSCTL_USE_PLL)
+    {
+        //
+        // ui32Config must be SYSCTL_OSC_MAIN or SYSCTL_OSC_INT.
+        //
+        if(((ui32Config & 0x38) != SYSCTL_OSC_MAIN) &&
+           ((ui32Config & 0x38) != SYSCTL_OSC_INT))
+        {
+            return(0);
+        }
+
+        //
+        // Get the VCO index out of the ui32Config parameter.
+        //
+        i32VCOIdx = (ui32Config >> 24) & 7;
+
+        //
+        // Check that the VCO index is not out of bounds.
+        //
+        ASSERT(i32VCOIdx < MAX_VCO_ENTRIES);
+
+        //
+        // Set the memory timings for the maximum external frequency since
+        // this could be a switch to PIOSC or possibly to MOSC which can be
+        // up to 25MHz.
+        //
+        HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(25000000);
+
+        //
+        // Clear the old PLL divider and source in case it was set.
+        //
+        ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) &
+                          ~(SYSCTL_RSCLKCFG_PSYSDIV_M |
+                            SYSCTL_RSCLKCFG_OSCSRC_M |
+                            SYSCTL_RSCLKCFG_PLLSRC_M | SYSCTL_RSCLKCFG_USEPLL);
+
+        //
+        // Update the memory timings to match running from PIOSC.
+        //
+        ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
+
+        //
+        // Update clock configuration to switch back to PIOSC.
+        //
+        HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
+
+        //
+        // The table starts at 5 MHz so modify the index to match this.
+        //
+        i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ);
+
+        //
+        // If there were no changes to the PLL do not force the PLL to lock by
+        // writing the PLL settings.
+        //
+        if((HWREG(SYSCTL_PLLFREQ1) !=
+            g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]) ||
+           (HWREG(SYSCTL_PLLFREQ0) !=
+            (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
+             SYSCTL_PLLFREQ0_PLLPWR)))
+        {
+            bNewPLL = true;
+        }
+        else
+        {
+            bNewPLL = false;
+        }
+
+        //
+        // If there are new PLL settings write them.
+        //
+        if(bNewPLL)
+        {
+            //
+            // Set the oscillator source.
+            //
+            HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect;
+
+            //
+            // Set the M, N and Q values provided from the table and preserve
+            // the power state of the main PLL.
+            //
+            HWREG(SYSCTL_PLLFREQ1) =
+                g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1];
+            HWREG(SYSCTL_PLLFREQ0) =
+                (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
+                 (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR));
+        }
+
+        //
+        // Calculate the System divider such that we get a frequency that is
+        // the closest to the requested frequency without going over.
+        //
+        ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) /
+                     ui32SysClock;
+
+        //
+        // Calculate the actual system clock.
+        //
+        ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / ui32SysDiv;
+
+        //
+        // Set the Flash and EEPROM timing values.
+        //
+        HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock);
+
+        //
+        // Check if the PLL is already powered up.
+        //
+        if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)
+        {
+            if(bNewPLL == true)
+            {
+                //
+                // Trigger the PLL to lock to the new frequency.
+                //
+                HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ;
+            }
+        }
+        else
+        {
+            //
+            // Power up the PLL.
+            //
+            HWREG(SYSCTL_PLLFREQ0) |= SYSCTL_PLLFREQ0_PLLPWR;
+        }
+
+        //
+        // Wait until the PLL has locked.
+        //
+        for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--)
+        {
+            if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK))
+            {
+                break;
+            }
+        }
+
+        //
+        // If the loop above did not timeout then switch over to the PLL
+        //
+        if(i32Timeout)
+        {
+            ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
+            ui32RSClkConfig |= ((ui32SysDiv - 1) <<
+                                SYSCTL_RSCLKCFG_PSYSDIV_S) | ui32OscSelect |
+                               SYSCTL_RSCLKCFG_USEPLL;
+            ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
+
+            //
+            // Set the new clock configuration.
+            //
+            HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
+        }
+        else
+        {
+            ui32SysClock = 0;
+        }
+    }
+    else
+    {
+        //
+        // Set the Flash and EEPROM timing values for PIOSC.
+        //
+        HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000);
+
+        //
+        // Make sure that the PLL is powered down since it is not being used.
+        //
+        HWREG(SYSCTL_PLLFREQ0) &= ~SYSCTL_PLLFREQ0_PLLPWR;
+
+        //
+        // Clear the old PLL divider and source in case it was set.
+        //
+        ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
+        ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M |
+                             SYSCTL_RSCLKCFG_OSCSRC_M |
+                             SYSCTL_RSCLKCFG_USEPLL);
+
+        //
+        // Update the memory timings.
+        //
+        ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
+
+        //
+        // Set the new clock configuration.
+        //
+        HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
+
+        //
+        // If zero given as the system clock then default to divide by 1.
+        //
+        if(ui32SysClock == 0)
+        {
+            ui32SysDiv = 0;
+        }
+        else
+        {
+            //
+            // Calculate the System divider based on the requested
+            // frequency.
+            //
+            ui32SysDiv = ui32Osc / ui32SysClock;
+
+            //
+            // If the system divisor is not already zero, subtract one to
+            // set the value in the register which requires the value to
+            // be n-1.
+            //
+            if(ui32SysDiv != 0)
+            {
+                ui32SysDiv -= 1;
+            }
+
+            //
+            // Calculate the system clock.
+            //
+            ui32SysClock = ui32Osc / (ui32SysDiv + 1);
+        }
+
+        //
+        // Set the memory timing values for the new system clock.
+        //
+        HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock);
+
+        //
+        // Set the new system clock values.
+        //
+        ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
+        ui32RSClkConfig |= (ui32SysDiv << SYSCTL_RSCLKCFG_OSYSDIV_S) |
+                           ui32OscSelect;
+
+        //
+        // Update the memory timings.
+        //
+        ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
+
+        //
+        // Set the new clock configuration.
+        //
+        HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
+    }
+
+    return(ui32SysClock);
+}
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device.
+//!
+//! \param ui32Config is the required configuration of the device clocking.
+//!
+//! This function configures the clocking of the device.  The input crystal
+//! frequency, oscillator to be used, use of the PLL, and the system clock
+//! divider are all configured with this function.
+//!
+//! The \e ui32Config parameter is the logical OR of several different values,
+//! many of which are grouped into sets where only one can be chosen.
+//!
+//! The system clock divider is chosen with one of the following values:
+//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
+//! \b SYSCTL_SYSDIV_64.
+//!
+//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
+//! \b SYSCTL_USE_OSC.
+//!
+//! The external crystal frequency is chosen with one of the following values:
+//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
+//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
+//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
+//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
+//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
+//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ,
+//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz.
+//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in
+//! operation.
+//!
+//! The oscillator source is chosen with one of the following values:
+//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
+//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32.  \b SYSCTL_OSC_EXT32 is only
+//! available on devices with the hibernate module, and then only when the
+//! hibernate module has been enabled.
+//!
+//! The internal and main oscillators are disabled with the
+//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
+//! The external oscillator must be enabled in order to use an external clock
+//! source.  Note that attempts to disable the oscillator used to clock the
+//! device is prevented by the hardware.
+//!
+//! To clock the system from an external source (such as an external crystal
+//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN.  To clock the
+//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
+//! \b SYSCTL_OSC_MAIN.  To clock the system from the PLL, use
+//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
+//! crystal with one of the \b SYSCTL_XTAL_xxx values.
+//!
+//! \note This function should only be called on TM4C123 devices.  For
+//! all other devices use the SysCtlClockFreqSet() function.
+//!
+//! \note If selecting the PLL as the system clock source (that is, via
+//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to
+//! determine when the PLL has locked.  If an interrupt handler for the
+//! system control interrupt is in place, and it responds to and clears the
+//! PLL lock interrupt, this function delays until its timeout has occurred
+//! instead of completing as soon as PLL lock is achieved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClockSet(uint32_t ui32Config)
+{
+    uint32_t ui32Delay, ui32RCC, ui32RCC2;
+
+    //
+    // Get the current value of the RCC and RCC2 registers.
+    //
+    ui32RCC = HWREG(SYSCTL_RCC);
+    ui32RCC2 = HWREG(SYSCTL_RCC2);
+
+    //
+    // Bypass the PLL and system clock dividers for now.
+    //
+    ui32RCC |= SYSCTL_RCC_BYPASS;
+    ui32RCC &= ~(SYSCTL_RCC_USESYSDIV);
+    ui32RCC2 |= SYSCTL_RCC2_BYPASS2;
+
+    //
+    // Write the new RCC value.
+    //
+    HWREG(SYSCTL_RCC) = ui32RCC;
+    HWREG(SYSCTL_RCC2) = ui32RCC2;
+
+    //
+    // See if the oscillator needs to be enabled.
+    //
+    if((ui32RCC & SYSCTL_RCC_MOSCDIS) && !(ui32Config & SYSCTL_MAIN_OSC_DIS))
+    {
+        //
+        // Make sure that the required oscillators are enabled.  For now, the
+        // previously enabled oscillators must be enabled along with the newly
+        // requested oscillators.
+        //
+        ui32RCC &= (~SYSCTL_RCC_MOSCDIS | (ui32Config & SYSCTL_MAIN_OSC_DIS));
+
+        //
+        // Clear the MOSC power up raw interrupt status to be sure it is not
+        // set when waiting below.
+        //
+        HWREG(SYSCTL_MISC) = SYSCTL_MISC_MOSCPUPMIS;
+
+        //
+        // Write the new RCC value.
+        //
+        HWREG(SYSCTL_RCC) = ui32RCC;
+
+        //
+        // Timeout using the legacy delay value.
+        //
+        ui32Delay = 524288;
+
+        while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0)
+        {
+            ui32Delay--;
+
+            if(ui32Delay == 0)
+            {
+                break;
+            }
+        }
+
+        //
+        // If the main oscillator failed to start up then do not switch to
+        // it and return.
+        //
+        if(ui32Delay == 0)
+        {
+            return;
+        }
+
+    }
+
+    //
+    // Set the new crystal value and oscillator source.  Because the OSCSRC2
+    // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a
+    // special encoding within ui32Config to avoid the overlap.
+    //
+    ui32RCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M);
+    ui32RCC |= ui32Config & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M);
+    ui32RCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M);
+    ui32RCC2 |= ui32Config & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M);
+    ui32RCC2 |= (ui32Config & 0x00000008) << 3;
+
+    //
+    // Write the new RCC value.
+    //
+    HWREG(SYSCTL_RCC) = ui32RCC;
+    HWREG(SYSCTL_RCC2) = ui32RCC2;
+
+    //
+    // Set the PLL configuration.
+    //
+    ui32RCC &= ~SYSCTL_RCC_PWRDN;
+    ui32RCC |= ui32Config & SYSCTL_RCC_PWRDN;
+    ui32RCC2 &= ~SYSCTL_RCC2_PWRDN2;
+    ui32RCC2 |= ui32Config & SYSCTL_RCC2_PWRDN2;
+
+    //
+    // Clear the PLL lock interrupt.
+    //
+    HWREG(SYSCTL_MISC) = SYSCTL_MISC_PLLLMIS;
+
+    //
+    // Write the new RCC value.
+    //
+    if(ui32RCC2 & SYSCTL_RCC2_USERCC2)
+    {
+        HWREG(SYSCTL_RCC2) = ui32RCC2;
+        HWREG(SYSCTL_RCC) = ui32RCC;
+    }
+    else
+    {
+        HWREG(SYSCTL_RCC) = ui32RCC;
+        HWREG(SYSCTL_RCC2) = ui32RCC2;
+    }
+
+    //
+    // Set the requested system divider and disable the appropriate
+    // oscillators.  This value is not written immediately.
+    //
+    ui32RCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+                 SYSCTL_RCC_MOSCDIS);
+    ui32RCC |= ui32Config & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+                             SYSCTL_RCC_MOSCDIS);
+    ui32RCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
+    ui32RCC2 |= ui32Config & SYSCTL_RCC2_SYSDIV2_M;
+    if(ui32Config & SYSCTL_RCC2_DIV400)
+    {
+        ui32RCC |= SYSCTL_RCC_USESYSDIV;
+        ui32RCC2 &= ~(SYSCTL_RCC_USESYSDIV);
+        ui32RCC2 |= ui32Config & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB);
+    }
+    else
+    {
+        ui32RCC2 &= ~(SYSCTL_RCC2_DIV400);
+    }
+
+    //
+    // See if the PLL output is being used to clock the system.
+    //
+    if(!(ui32Config & SYSCTL_RCC_BYPASS))
+    {
+        //
+        // Wait until the PLL has locked.
+        //
+        for(ui32Delay = 32768; ui32Delay > 0; ui32Delay--)
+        {
+            if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK))
+            {
+                break;
+            }
+        }
+
+        //
+        // Enable use of the PLL.
+        //
+        ui32RCC &= ~(SYSCTL_RCC_BYPASS);
+        ui32RCC2 &= ~(SYSCTL_RCC2_BYPASS2);
+    }
+
+    //
+    // Write the final RCC value.
+    //
+    HWREG(SYSCTL_RCC) = ui32RCC;
+    HWREG(SYSCTL_RCC2) = ui32RCC2;
+
+    //
+    // Delay for a little bit so that the system divider takes effect.
+    //
+    SysCtlDelay(16);
+}
+
+//*****************************************************************************
+//
+//! Gets the processor clock rate.
+//!
+//! This function determines the clock rate of the processor clock, which is
+//! also the clock rate of the peripheral modules (with the exception of
+//! PWM, which has its own clock divider; other peripherals may have different
+//! clocking, see the device data sheet for details).
+//!
+//! \note This cannot return accurate results if SysCtlClockSet() has not
+//! been called to configure the clocking of the device, or if the device is
+//! directly clocked from a crystal (or a clock source) that is not one of the
+//! supported crystal frequencies.  In the latter case, this function should be
+//! modified to directly return the correct system clock rate.
+//!
+//! \note This function can only be called on TM4C123 devices.  For TM4C129
+//! devices, the return value from SysCtlClockFreqSet() indicates the system
+//! clock frequency.
+//!
+//! \return The processor clock rate for TM4C123 devices only.
+//
+//*****************************************************************************
+uint32_t
+SysCtlClockGet(void)
+{
+    uint32_t ui32RCC, ui32RCC2, ui32PLL, ui32Clk, ui32Max;
+    uint32_t ui32PLL1;
+
+    //
+    // This function is only valid on TM4C123 devices.
+    //
+    ASSERT(CLASS_IS_TM4C123);
+
+    //
+    // Read RCC and RCC2.
+    //
+    ui32RCC = HWREG(SYSCTL_RCC);
+    ui32RCC2 = HWREG(SYSCTL_RCC2);
+
+    //
+    // Get the base clock rate.
+    //
+    switch((ui32RCC2 & SYSCTL_RCC2_USERCC2) ?
+           (ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) :
+           (ui32RCC & SYSCTL_RCC_OSCSRC_M))
+    {
+        //
+        // The main oscillator is the clock source.  Determine its rate from
+        // the crystal setting field.
+        //
+        case SYSCTL_RCC_OSCSRC_MAIN:
+        {
+            ui32Clk = g_pui32Xtals[(ui32RCC & SYSCTL_RCC_XTAL_M) >>
+                                   SYSCTL_RCC_XTAL_S];
+            break;
+        }
+
+        //
+        // The internal oscillator is the source clock.
+        //
+        case SYSCTL_RCC_OSCSRC_INT:
+        {
+            //
+            // The internal oscillator on all devices is 16 MHz.
+            //
+            ui32Clk = 16000000;
+            break;
+        }
+
+        //
+        // The internal oscillator divided by four is the source clock.
+        //
+        case SYSCTL_RCC_OSCSRC_INT4:
+        {
+            //
+            // The internal oscillator on all devices is 16 MHz.
+            //
+            ui32Clk = 16000000 / 4;
+            break;
+        }
+
+        //
+        // The internal 30-KHz oscillator is the source clock.
+        //
+        case SYSCTL_RCC_OSCSRC_30:
+        {
+            //
+            // The internal 30-KHz oscillator has an accuracy of +/- 30%.
+            //
+            ui32Clk = 30000;
+            break;
+        }
+
+        //
+        // The 32.768-KHz clock from the hibernate module is the source clock.
+        //
+        case SYSCTL_RCC2_OSCSRC2_32:
+        {
+            ui32Clk = 32768;
+            break;
+        }
+
+        //
+        // An unknown setting, so return a zero clock (that is, an unknown
+        // clock rate).
+        //
+        default:
+        {
+            return(0);
+        }
+    }
+
+    //
+    // Default the maximum frequency to the maximum 32-bit unsigned value.
+    //
+    ui32Max = 0xffffffff;
+
+    //
+    // See if the PLL is being used.
+    //
+    if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+        !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) ||
+       (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && !(ui32RCC & SYSCTL_RCC_BYPASS)))
+    {
+        //
+        // Read the two PLL frequency registers.  The formula for a
+        // TM4C123 device is "(xtal * m) / ((q + 1) * (n + 1))".
+        //
+        ui32PLL = HWREG(SYSCTL_PLLFREQ0);
+        ui32PLL1 = HWREG(SYSCTL_PLLFREQ1);
+
+        //
+        // Divide the input clock by the dividers.
+        //
+        ui32Clk /= ((((ui32PLL1 & SYSCTL_PLLFREQ1_Q_M) >>
+                      SYSCTL_PLLFREQ1_Q_S) + 1) *
+                    (((ui32PLL1 & SYSCTL_PLLFREQ1_N_M) >>
+                      SYSCTL_PLLFREQ1_N_S) + 1) * 2);
+
+        //
+        // Multiply the clock by the multiplier, which is split into an
+        // integer part and a fractional part.
+        //
+        ui32Clk = ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MINT_M) >>
+                               SYSCTL_PLLFREQ0_MINT_S)) +
+                   ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MFRAC_M) >>
+                                SYSCTL_PLLFREQ0_MFRAC_S)) >> 10));
+
+        //
+        // Force the system divider to be enabled.  It is always used when
+        // using the PLL, but in some cases it does not read as being enabled.
+        //
+        ui32RCC |= SYSCTL_RCC_USESYSDIV;
+
+        //
+        // Calculate the maximum system frequency.
+        //
+        switch(HWREG(SYSCTL_DC1) & SYSCTL_DC1_MINSYSDIV_M)
+        {
+            case SYSCTL_DC1_MINSYSDIV_80:
+            {
+                ui32Max = 80000000;
+                break;
+            }
+            case SYSCTL_DC1_MINSYSDIV_66:
+            {
+                ui32Max = 66666666;
+                break;
+            }
+            case SYSCTL_DC1_MINSYSDIV_50:
+            {
+                ui32Max = 50000000;
+                break;
+            }
+            case SYSCTL_DC1_MINSYSDIV_40:
+            {
+                ui32Max = 40000000;
+                break;
+            }
+            case SYSCTL_DC1_MINSYSDIV_25:
+            {
+                ui32Max = 25000000;
+                break;
+            }
+            case SYSCTL_DC1_MINSYSDIV_20:
+            {
+                ui32Max = 20000000;
+                break;
+            }
+            default:
+            {
+                break;
+            }
+        }
+    }
+
+    //
+    // See if the system divider is being used.
+    //
+    if(ui32RCC & SYSCTL_RCC_USESYSDIV)
+    {
+        //
+        // Adjust the clock rate by the system clock divider.
+        //
+        if(ui32RCC2 & SYSCTL_RCC2_USERCC2)
+        {
+            if((ui32RCC2 & SYSCTL_RCC2_DIV400) &&
+               (((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+                 !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) ||
+                (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+                 !(ui32RCC & SYSCTL_RCC_BYPASS))))
+
+            {
+                ui32Clk = ((ui32Clk * 2) / (((ui32RCC2 &
+                                              (SYSCTL_RCC2_SYSDIV2_M |
+                                               SYSCTL_RCC2_SYSDIV2LSB)) >>
+                                             (SYSCTL_RCC2_SYSDIV2_S - 1)) +
+                                            1));
+            }
+            else
+            {
+                ui32Clk /= (((ui32RCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
+                             SYSCTL_RCC2_SYSDIV2_S) + 1);
+            }
+        }
+        else
+        {
+            ui32Clk /= (((ui32RCC & SYSCTL_RCC_SYSDIV_M) >>
+                         SYSCTL_RCC_SYSDIV_S) + 1);
+        }
+    }
+
+    //
+    // Limit the maximum clock to the maximum clock frequency.
+    //
+    if(ui32Max < ui32Clk)
+    {
+        ui32Clk = ui32Max;
+    }
+
+    //
+    // Return the computed clock rate.
+    //
+    return(ui32Clk);
+}
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device while in deep-sleep mode.
+//!
+//! \param ui32Config is the required configuration of the device clocking
+//! while in deep-sleep mode.
+//!
+//! This function configures the clocking of the device while in deep-sleep
+//! mode.  The oscillator to be used and the system clock divider are
+//! configured with this function.
+//!
+//! The \e ui32Config parameter is the logical OR of the following values:
+//!
+//! The system clock divider is chosen from one of the following values:
+//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ...
+//! \b SYSCTL_DSLP_DIV_64.
+//!
+//! The oscillator source is chosen from one of the following values:
+//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30,
+//! or \b SYSCTL_DSLP_OSC_EXT32.  \b SYSCTL_OSC_EXT32 is only available on
+//! devices with the hibernation module, and then only when the hibernation
+//! module has been enabled.
+//!
+//! The precision internal oscillator can be powered down in deep-sleep mode by
+//! specifying \b SYSCTL_DSLP_PIOSC_PD.  The precision internal oscillator is
+//! not powered down if it is required for operation while in deep-sleep
+//! (based on other configuration settings.)
+//!
+//! \note This function should only be called on TM4C123 devices.  For
+//! other devices use the SysCtlDeepSleepClockConfigSet() function.
+//!
+//! \note The availability of deep-sleep clocking configuration varies with the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleepClockSet(uint32_t ui32Config)
+{
+    //
+    // Set the deep-sleep clock configuration.
+    //
+    HWREG(SYSCTL_DSLPCLKCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the clock configuration of the device while in deep-sleep mode.
+//!
+//! \param ui32Div is the clock divider when in deep-sleep mode.
+//! \param ui32Config is the configuration of the device clocking while
+//! in deep-sleep mode.
+//!
+//! This function configures the clocking of the device while in deep-sleep
+//! mode.  The \e ui32Config parameter selects the oscillator and the
+//! \e ui32Div parameter sets the clock divider used in deep-sleep mode.  The
+//! valid values for the \e ui32Div parameter range from 1 to 1024, however not
+//! all Tiva microcontrollers support this full range.  This function
+//! replaces the SysCtlDeepSleepClockSet() function and can be used on
+//! Tiva devices that support deep-sleep mode.
+//!
+//! The oscillator source is chosen from one of the following values:
+//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30,
+//! or \b SYSCTL_DSLP_OSC_EXT32.  The \b SYSCTL_DSLP_OSC_EXT32 option is only
+//! available on devices with the hibernation module, and then only when the
+//! hibernation module is enabled.
+//!
+//! The precision internal oscillator can be powered down in deep-sleep mode by
+//! specifying \b SYSCTL_DSLP_PIOSC_PD.  The precision internal oscillator is
+//! not powered down if it is required for operation while in deep-sleep
+//! (based on other configuration settings).
+//!
+//! The main oscillator can be powered down in deep-sleep mode by
+//! specifying \b SYSCTL_DSLP_MOSC_PD.  The main oscillator is
+//! not powered down if it is required for operation while in deep-sleep
+//! (based on other configuration settings).
+//!
+//! \note The availability of deep-sleep clocking configuration and the
+//! configuration values vary with the Tiva device in use.  Please consult
+//! the data sheet for the device you are using to determine whether the
+//! desired configuration options are available and to determine the valid
+//! range for the clock divider.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, uint32_t ui32Config)
+{
+    uint32_t ui32Value;
+
+    ASSERT(ui32Div != 0);
+
+    if(CLASS_IS_TM4C123)
+    {
+        //
+        // Set the deep-sleep clock configuration.
+        //
+        HWREG(SYSCTL_DSLPCLKCFG) = (ui32Config & ~SYSCTL_DSLPCLKCFG_D_M) |
+                                   ((ui32Div - 1) << SYSCTL_DSLPCLKCFG_D_S);
+    }
+    else
+    {
+        //
+        // Initialize the value with the divider.
+        //
+        ui32Value = ui32Div - 1;
+
+        //
+        // Set the clock source selection based on the defines used for
+        // SysCtlDeepSleepClockSet() function so that there is some backwards
+        // compatibility.
+        //
+        switch(ui32Config & SYSCTL_DSLPCLKCFG_O_M)
+        {
+            //
+            // Choose the main external oscillator.
+            //
+            case SYSCTL_DSLP_OSC_MAIN:
+            {
+                ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_MOSC;
+
+                break;
+            }
+
+            //
+            // Choose the low frequency oscillator.
+            //
+            case SYSCTL_DSLP_OSC_INT30:
+            {
+                ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC;
+
+                break;
+            }
+
+            //
+            // Choose the low frequency oscillator.
+            //
+            case SYSCTL_DSLP_OSC_EXT32:
+            {
+                ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_RTC;
+
+                break;
+            }
+            //
+            // The zero value uses the PIOSC as the clock source.
+            //
+            case SYSCTL_DSLP_OSC_INT:
+            default:
+            {
+                break;
+            }
+        }
+
+        //
+        // Set the PIOSC power down bit.
+        //
+        if(ui32Config & SYSCTL_DSLP_PIOSC_PD)
+        {
+            ui32Value |= SYSCTL_DSCLKCFG_PIOSCPD;
+        }
+
+        //
+        // Set the PIOSC power down bit.
+        //
+        if(ui32Config & SYSCTL_DSLP_MOSC_PD)
+        {
+            ui32Value |= SYSCTL_DSCLKCFG_MOSCDPD;
+        }
+
+        //
+        // Update the deep-sleep clock configuration.
+        //
+        HWREG(SYSCTL_DSCLKCFG) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the PWM clock configuration.
+//!
+//! \param ui32Config is the configuration for the PWM clock; it must be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//!
+//! This function configures the rate of the clock provided to the PWM module
+//! as a ratio of the processor clock.  This clock is used by the PWM module to
+//! generate PWM signals; its rate forms the basis for all PWM signals.
+//!
+//! \note This function should only be used with TM4C123 devices.  For
+//! other TM4C devices, the PWMClockSet() function should be used.
+//!
+//! \note The clocking of the PWM is dependent on the system clock rate as
+//! configured by SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPWMClockSet(uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Config == SYSCTL_PWMDIV_1) ||
+           (ui32Config == SYSCTL_PWMDIV_2) ||
+           (ui32Config == SYSCTL_PWMDIV_4) ||
+           (ui32Config == SYSCTL_PWMDIV_8) ||
+           (ui32Config == SYSCTL_PWMDIV_16) ||
+           (ui32Config == SYSCTL_PWMDIV_32) ||
+           (ui32Config == SYSCTL_PWMDIV_64));
+
+    //
+    // Check that there is a PWM block on this part.
+    //
+    ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1));
+
+    //
+    // Set the PWM clock configuration into the run-mode clock configuration
+    // register.
+    //
+    HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
+                          ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
+                         ui32Config);
+}
+
+//*****************************************************************************
+//
+//! Gets the current PWM clock configuration.
+//!
+//! This function returns the current PWM clock configuration.
+//!
+//! \return Returns the current PWM clock configuration; is one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//!
+//! \note This function should only be used with TM4C123 devices.  For
+//! other TM4C devices, the PWMClockGet() function should be used.
+//
+//*****************************************************************************
+uint32_t
+SysCtlPWMClockGet(void)
+{
+    //
+    // Check that there is a PWM block on this part.
+    //
+    ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1));
+
+    //
+    // Return the current PWM clock configuration.  Make sure that
+    // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
+    //
+    if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
+    {
+        //
+        // The divider is not active so reflect this in the value we return.
+        //
+        return(SYSCTL_PWMDIV_1);
+    }
+    else
+    {
+        //
+        // The divider is active so directly return the masked register value.
+        //
+        return(HWREG(SYSCTL_RCC) &
+               (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables access to a GPIO peripheral via the AHB.
+//!
+//! \param ui32GPIOPeripheral is the GPIO peripheral to enable.
+//!
+//! This function is used to enable the specified GPIO peripheral to be
+//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
+//! Peripheral Bus (APB).  When a GPIO peripheral is enabled for AHB access,
+//! the \b _AHB_BASE form of the base address should be used for GPIO
+//! functions.  For example, instead of using \b GPIO_PORTA_BASE as the base
+//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
+//!
+//! The \e ui32GPIOPeripheral argument must be only one of the following
+//! values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ.
+//!
+//! \note On some devices, all GPIO ports are only available on AHB.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+    //
+    // Enable this GPIO for AHB access.
+    //
+    HWREG(SYSCTL_GPIOHBCTL) |= (1 << (ui32GPIOPeripheral & 0xF));
+}
+
+//*****************************************************************************
+//
+//! Disables access to a GPIO peripheral via the AHB.
+//!
+//! \param ui32GPIOPeripheral is the GPIO peripheral to disable.
+//!
+//! This function disables the specified GPIO peripheral for access from the
+//! Advanced Host Bus (AHB).  Once disabled, the GPIO peripheral is accessed
+//! from the legacy Advanced Peripheral Bus (APB).
+//!
+//! The \b ui32GPIOPeripheral argument must be only one of the following
+//! values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ.
+//!
+//! \note Some devices allow disabling AHB access to GPIO ports that are only
+//! present on the AHB.  Disabling AHB access to these ports will disable
+//! access to these GPIO ports. On some devices, all GPIO ports are only
+//! available on AHB.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+           (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+    //
+    // Disable this GPIO for AHB access.
+    //
+    HWREG(SYSCTL_GPIOHBCTL) &= ~(1 << (ui32GPIOPeripheral & 0xF));
+}
+
+//*****************************************************************************
+//
+//! Powers up the USB PLL.
+//!
+//! This function enables the USB controller's PLL, which is used by its
+//! physical layer.  This call is necessary before connecting to any external
+//! devices.
+//!
+//! \note This function should only be called on TM4C123 devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLEnable(void)
+{
+    //
+    // Turn on the USB PLL.
+    //
+    HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Powers down the USB PLL.
+//!
+//! This function disables the USB controller's PLL, which is used by its
+//! physical layer.  The USB registers are still accessible, but the physical
+//! layer no longer functions.
+//!
+//! \note This function should only be called on TM4C123 devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLDisable(void)
+{
+    //
+    // Turn off the USB PLL.
+    //
+    HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Configures the response to system voltage events.
+//!
+//! \param ui32Config holds the configuration options for the voltage events.
+//!
+//! This function configures the response to voltage-related events.
+//! These events are triggered when the voltage rails drop below certain
+//! levels.  The \e ui32Config parameter provides the configuration for the
+//! voltage events and is a combination of the \b SYSCTL_VEVENT_* values.
+//!
+//! The response to a brown out on the VDDA rail is set by using one of the
+//! following values:
+//! - \b SYSCTL_VEVENT_VDDABO_NONE - There is no action taken on a VDDA
+//!      brown out.
+//! - \b SYSCTL_VEVENT_VDDABO_INT - A system interrupt is generated when a
+//!      VDDA brown out occurs.
+//! - \b SYSCTL_VEVENT_VDDABO_NMI - An NMI is generated when a VDDA brown out
+//!      occurs.
+//! - \b SYSCTL_VEVENT_VDDABO_RST - A reset is generated when a VDDA brown out
+//!      occurs.  The type of reset that is generated is controller by the
+//!      \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet()
+//!      function.
+//!
+//! The response to a brown out on the VDD rail is set by using one of the
+//! following values:
+//! - \b SYSCTL_VEVENT_VDDBO_NONE - There is no action taken on a VDD
+//!      brown out.
+//! - \b SYSCTL_VEVENT_VDDBO_INT - A system interrupt is generated when a
+//!      VDD brown out occurs.
+//! - \b SYSCTL_VEVENT_VDDBO_NMI - An NMI is generated when a VDD brown out
+//!      occurs.
+//! - \b SYSCTL_VEVENT_VDDBO_RST - A reset is generated when a VDD brown out
+//!      occurs.  The type of reset that is generated is controller by the
+//!      \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet()
+//!      function.
+//!
+//! \b Example: Configure the voltage events to trigger an interrupt on a VDDA
+//! brown out, an NMI on a VDDC brown out and a reset on a VDD brown out.
+//!
+//! \verbatim
+//!
+//! //
+//! // Configure the BOR rest to trigger a full POR.  This is needed because
+//! // the SysCtlVoltageEventConfig() call is triggering a reset so the type
+//! // of reset is specified by this call.
+//! //
+//! SysCtlResetBehaviorSet(SYSCTL_ONRST_BOR_POR);
+//!
+//! //
+//! // Trigger an interrupt on a VDDA brown out and a reset on a VDD brown out.
+//! //
+//! SysCtlVoltageEventConfig(SYSCTL_VEVENT_VDDABO_INT |
+//!                          SYSCTL_VEVENT_VDDBO_RST);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlVoltageEventConfig(uint32_t ui32Config)
+{
+    //
+    // Set the requested events.
+    //
+    HWREG(SYSCTL_PTBOCTL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Returns the voltage event status.
+//!
+//! This function returns the voltage event status for the system controller.
+//! The value returned is a logical OR of the following values:
+//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail.
+//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail.
+//!
+//! The values returned from this function can be passed to the
+//! SysCtlVoltageEventClear() to clear the current voltage event status.
+//! Because voltage events are not cleared due to a reset, the voltage event
+//! status must be cleared by calling SysCtlVoltageEventClear().
+//!
+//! \b Example: Clear the current voltage event status.
+//!
+//! \verbatim
+//! uint32_t ui32VoltageEvents;
+//!
+//! //
+//! // Read the current voltage event status.
+//! //
+//! ui32VoltageEvents = SysCtlVoltageEventStatus();
+//!
+//! //
+//! // Clear all the current voltage events.
+//! //
+//! SysCtlVoltageEventClear(ui32VoltageEvents);
+//! \endverbatim
+//!
+//! \return The current voltage event status.
+//!
+//! \note The availability of voltage events varies with the Tiva part
+//! in use.  Please consult the data sheet for the part you are using to
+//! determine which interrupt sources are available.
+//
+//*****************************************************************************
+uint32_t
+SysCtlVoltageEventStatus(void)
+{
+    //
+    // Return the current voltage event status.
+    //
+    return(HWREG(SYSCTL_PWRTC));
+}
+
+//*****************************************************************************
+//
+//! Clears the voltage event status.
+//!
+//! \param ui32Status is a bit mask of the voltage events to clear.
+//!
+//! This function clears the current voltage events status for the values
+//! specified in the \e ui32Status parameter.  The \e ui32Status value must be
+//! a logical OR of the following values:
+//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail.
+//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail.
+//!
+//! \b Example: Clear the current voltage event status.
+//!
+//! \verbatim
+//! //
+//! // Clear all the current voltage events.
+//! //
+//! SysCtlVoltageEventClear(SysCtlVoltageEventStatus());
+//! \endverbatim
+//!
+//! \note The availability of voltage event status varies with the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlVoltageEventClear(uint32_t ui32Status)
+{
+    //
+    // Clear the requested voltage events.
+    //
+    HWREG(SYSCTL_PWRTC) |= ui32Status;
+}
+
+//*****************************************************************************
+//
+//! Returns the current NMI status.
+//!
+//! This function returns the NMI status for the system controller.  The valid
+//! values for the \e ui32Ints parameter are a logical OR of the following
+//! values:
+//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not
+//!   start.
+//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected.
+//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout.
+//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout.
+//! - \b SYSCTL_NMI_POWER a power event occurred.
+//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted.
+//!
+//! \b Example: Clear all current NMI status flags.
+//!
+//! \verbatim
+//!
+//! //
+//! // Clear all the current NMI sources.
+//! //
+//! SysCtlNMIClear(SysCtlNMIStatus());
+//! \endverbatim
+//!
+//! \note The availability of the NMI status varies with the Tiva part in
+//! use.  Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return The current NMI status.
+//
+//*****************************************************************************
+uint32_t
+SysCtlNMIStatus(void)
+{
+    return(HWREG(SYSCTL_NMIC));
+}
+
+//*****************************************************************************
+//
+//! Clears NMI sources.
+//!
+//! \param ui32Ints is a bit mask of the non-maskable interrupt sources.
+//!
+//! This function clears the current NMI status specified in the \e ui32Ints
+//! parameter.  The valid values for the \e ui32Ints parameter are a logical OR
+//! of the following values:
+//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not
+//!   start.
+//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected.
+//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout.
+//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout.
+//! - \b SYSCTL_NMI_POWER a power event occurred.
+//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted.
+//!
+//! \b Example: Clear all current NMI status flags.
+//!
+//! \verbatim
+//!
+//! //
+//! // Clear all the current NMI sources.
+//! //
+//! SysCtlNMIClear(SysCtlNMIStatus());
+//! \endverbatim
+//!
+//! \note The availability of the NMI status varies with the Tiva part in
+//! use.  Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlNMIClear(uint32_t ui32Ints)
+{
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(SYSCTL_NMIC) &= ~ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Configures and enables or disables the clock output on the DIVSCLK pin.
+//!
+//! \param ui32Config holds the configuration options including enabling or
+//! disabling the clock output on the DIVSCLK pin.
+//! \param ui32Div is the divisor for the clock selected in the \e ui32Config
+//! parameter.
+//!
+//! This function selects the source for the DIVSCLK, enables or disables
+//! the clock output and provides an output divider value.  The \e ui32Div
+//! parameter specifies the divider for the selected clock source and has a
+//! valid range of 1-256.  The \e ui32Config parameter configures
+//! the DIVSCLK output based on the following settings:
+//!
+//! The first setting allows the output to be enabled or disabled.
+//! - \b SYSCTL_CLKOUT_EN - enable the DIVSCLK output.
+//! - \b SYSCTL_CLKOUT_DIS - disable the DIVSCLK output (default).
+//!
+//! The next group of settings selects the source for the DIVSCLK.
+//! - \b SYSCTL_CLKOUT_SYSCLK - use the current system clock as the
+//!      source (default).
+//! - \b SYSCTL_CLKOUT_PIOSC - use the PIOSC as the source.
+//! - \b SYSCTL_CLKOUT_MOSC - use the MOSC as the source.
+//!
+//! \b Example: Enable the PIOSC divided by 4 as the DIVSCLK output.
+//!
+//! \verbatim
+//!
+//! //
+//! // Enable the PIOSC divided by 4 as the DIVSCLK output.
+//! //
+//! SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4);
+//! \endverbatim
+//!
+//! \note The availability of the DIVSCLK output varies with the Tiva part
+//! in use.  Please consult the data sheet for the part you are using to
+//! determine which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div)
+{
+    ASSERT(ui32Div != 0);
+    ASSERT((ui32Config & ~(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_DIS |
+                           SYSCTL_CLKOUT_SYSCLK | SYSCTL_CLKOUT_PIOSC |
+                           SYSCTL_CLKOUT_MOSC)) == 0);
+
+    //
+    // Set the requested configuration and divisor.
+    //
+    HWREG(SYSCTL_DIVSCLK) = ui32Config | ((ui32Div - 1) &
+                                          SYSCTL_DIVSCLK_DIV_M);
+}
+
+//*****************************************************************************
+//
+//! Configures the alternate peripheral clock source.
+//!
+//! \param ui32Config holds the configuration options for the alternate
+//! peripheral clock.
+//!
+//! This function configures the alternate peripheral clock.  The alternate
+//! peripheral clock is used to provide a known clock in all operating modes
+//! to peripherals that support using the alternate peripheral clock as an
+//! input clock.  The \e ui32Config parameter value provides the clock input
+//! source using one of the following values:
+//! - \b SYSCTL_ALTCLK_PIOSC - use the PIOSC as the alternate clock
+//!      source (default).
+//! - \b SYSCTL_ALTCLK_RTCOSC - use the Hibernate module RTC clock as the
+//!      alternate clock source.
+//! - \b SYSCTL_ALTCLK_LFIOSC - use the low-frequency internal oscillator as
+//!      the alternate clock source.
+//!
+//! \b Example: Select the Hibernate module RTC clock as the alternate clock
+//! source.
+//!
+//! \verbatim
+//!
+//! //
+//! // Select the Hibernate module RTC clock as the alternate clock source.
+//! //
+//! SysCtlAltClkConfig(SYSCTL_ALTCLK_RTCOSC);
+//! \endverbatim
+//!
+//! \note The availability of the alternate peripheral clock varies with the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlAltClkConfig(uint32_t ui32Config)
+{
+    //
+    // Set the requested configuration and divisor.
+    //
+    HWREG(SYSCTL_ALTCLKCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/sysctl.h b/bsp/tm4c129x/libraries/driverlib/sysctl.h
new file mode 100644
index 0000000000..c19d214b27
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/sysctl.h
@@ -0,0 +1,655 @@
+//*****************************************************************************
+//
+// sysctl.h - Prototypes for the system control driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SYSCTL_H__
+#define __DRIVERLIB_SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ui32Peripheral parameter.  The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_ADC0      0xf0003800  // ADC 0
+#define SYSCTL_PERIPH_ADC1      0xf0003801  // ADC 1
+#define SYSCTL_PERIPH_CAN0      0xf0003400  // CAN 0
+#define SYSCTL_PERIPH_CAN1      0xf0003401  // CAN 1
+#define SYSCTL_PERIPH_COMP0     0xf0003c00  // Analog Comparator Module 0
+#define SYSCTL_PERIPH_EMAC0     0xf0009c00  // Ethernet MAC0
+#define SYSCTL_PERIPH_EPHY0     0xf0003000  // Ethernet PHY0
+#define SYSCTL_PERIPH_EPI0      0xf0001000  // EPI0
+#define SYSCTL_PERIPH_GPIOA     0xf0000800  // GPIO A
+#define SYSCTL_PERIPH_GPIOB     0xf0000801  // GPIO B
+#define SYSCTL_PERIPH_GPIOC     0xf0000802  // GPIO C
+#define SYSCTL_PERIPH_GPIOD     0xf0000803  // GPIO D
+#define SYSCTL_PERIPH_GPIOE     0xf0000804  // GPIO E
+#define SYSCTL_PERIPH_GPIOF     0xf0000805  // GPIO F
+#define SYSCTL_PERIPH_GPIOG     0xf0000806  // GPIO G
+#define SYSCTL_PERIPH_GPIOH     0xf0000807  // GPIO H
+#define SYSCTL_PERIPH_GPIOJ     0xf0000808  // GPIO J
+#define SYSCTL_PERIPH_HIBERNATE 0xf0001400  // Hibernation module
+#define SYSCTL_PERIPH_CCM0      0xf0007400  // CCM 0
+#define SYSCTL_PERIPH_EEPROM0   0xf0005800  // EEPROM 0
+#define SYSCTL_PERIPH_FAN0      0xf0005400  // FAN 0
+#define SYSCTL_PERIPH_FAN1      0xf0005401  // FAN 1
+#define SYSCTL_PERIPH_GPIOK     0xf0000809  // GPIO K
+#define SYSCTL_PERIPH_GPIOL     0xf000080a  // GPIO L
+#define SYSCTL_PERIPH_GPIOM     0xf000080b  // GPIO M
+#define SYSCTL_PERIPH_GPION     0xf000080c  // GPIO N
+#define SYSCTL_PERIPH_GPIOP     0xf000080d  // GPIO P
+#define SYSCTL_PERIPH_GPIOQ     0xf000080e  // GPIO Q
+#define SYSCTL_PERIPH_GPIOR     0xf000080f  // GPIO R
+#define SYSCTL_PERIPH_GPIOS     0xf0000810  // GPIO S
+#define SYSCTL_PERIPH_GPIOT     0xf0000811  // GPIO T
+#define SYSCTL_PERIPH_I2C0      0xf0002000  // I2C 0
+#define SYSCTL_PERIPH_I2C1      0xf0002001  // I2C 1
+#define SYSCTL_PERIPH_I2C2      0xf0002002  // I2C 2
+#define SYSCTL_PERIPH_I2C3      0xf0002003  // I2C 3
+#define SYSCTL_PERIPH_I2C4      0xf0002004  // I2C 4
+#define SYSCTL_PERIPH_I2C5      0xf0002005  // I2C 5
+#define SYSCTL_PERIPH_I2C6      0xf0002006  // I2C 6
+#define SYSCTL_PERIPH_I2C7      0xf0002007  // I2C 7
+#define SYSCTL_PERIPH_I2C8      0xf0002008  // I2C 8
+#define SYSCTL_PERIPH_I2C9      0xf0002009  // I2C 9
+#define SYSCTL_PERIPH_LCD0      0xf0009000  // LCD 0
+#define SYSCTL_PERIPH_ONEWIRE0  0xf0009800  // One Wire 0
+#define SYSCTL_PERIPH_PWM0      0xf0004000  // PWM 0
+#define SYSCTL_PERIPH_PWM1      0xf0004001  // PWM 1
+#define SYSCTL_PERIPH_QEI0      0xf0004400  // QEI 0
+#define SYSCTL_PERIPH_QEI1      0xf0004401  // QEI 1
+#define SYSCTL_PERIPH_SSI0      0xf0001c00  // SSI 0
+#define SYSCTL_PERIPH_SSI1      0xf0001c01  // SSI 1
+#define SYSCTL_PERIPH_SSI2      0xf0001c02  // SSI 2
+#define SYSCTL_PERIPH_SSI3      0xf0001c03  // SSI 3
+#define SYSCTL_PERIPH_TIMER0    0xf0000400  // Timer 0
+#define SYSCTL_PERIPH_TIMER1    0xf0000401  // Timer 1
+#define SYSCTL_PERIPH_TIMER2    0xf0000402  // Timer 2
+#define SYSCTL_PERIPH_TIMER3    0xf0000403  // Timer 3
+#define SYSCTL_PERIPH_TIMER4    0xf0000404  // Timer 4
+#define SYSCTL_PERIPH_TIMER5    0xf0000405  // Timer 5
+#define SYSCTL_PERIPH_TIMER6    0xf0000406  // Timer 6
+#define SYSCTL_PERIPH_TIMER7    0xf0000407  // Timer 7
+#define SYSCTL_PERIPH_UART0     0xf0001800  // UART 0
+#define SYSCTL_PERIPH_UART1     0xf0001801  // UART 1
+#define SYSCTL_PERIPH_UART2     0xf0001802  // UART 2
+#define SYSCTL_PERIPH_UART3     0xf0001803  // UART 3
+#define SYSCTL_PERIPH_UART4     0xf0001804  // UART 4
+#define SYSCTL_PERIPH_UART5     0xf0001805  // UART 5
+#define SYSCTL_PERIPH_UART6     0xf0001806  // UART 6
+#define SYSCTL_PERIPH_UART7     0xf0001807  // UART 7
+#define SYSCTL_PERIPH_UDMA      0xf0000c00  // uDMA
+#define SYSCTL_PERIPH_USB0      0xf0002800  // USB 0
+#define SYSCTL_PERIPH_WDOG0     0xf0000000  // Watchdog 0
+#define SYSCTL_PERIPH_WDOG1     0xf0000001  // Watchdog 1
+#define SYSCTL_PERIPH_WTIMER0   0xf0005c00  // Wide Timer 0
+#define SYSCTL_PERIPH_WTIMER1   0xf0005c01  // Wide Timer 1
+#define SYSCTL_PERIPH_WTIMER2   0xf0005c02  // Wide Timer 2
+#define SYSCTL_PERIPH_WTIMER3   0xf0005c03  // Wide Timer 3
+#define SYSCTL_PERIPH_WTIMER4   0xf0005c04  // Wide Timer 4
+#define SYSCTL_PERIPH_WTIMER5   0xf0005c05  // Wide Timer 5
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOSleepSet() and
+// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the
+// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs.
+//
+//*****************************************************************************
+#define SYSCTL_LDO_0_90V        0x80000012  // LDO output of 0.90V
+#define SYSCTL_LDO_0_95V        0x80000013  // LDO output of 0.95V
+#define SYSCTL_LDO_1_00V        0x80000014  // LDO output of 1.00V
+#define SYSCTL_LDO_1_05V        0x80000015  // LDO output of 1.05V
+#define SYSCTL_LDO_1_10V        0x80000016  // LDO output of 1.10V
+#define SYSCTL_LDO_1_15V        0x80000017  // LDO output of 1.15V
+#define SYSCTL_LDO_1_20V        0x80000018  // LDO output of 1.20V
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlIntEnable(),
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
+// by the SysCtlIntStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_INT_BOR0         0x00000800  // VDD under BOR0
+#define SYSCTL_INT_VDDA_OK      0x00000400  // VDDA Power OK
+#define SYSCTL_INT_MOSC_PUP     0x00000100  // MOSC power-up interrupt
+#define SYSCTL_INT_USBPLL_LOCK  0x00000080  // USB PLL lock interrupt
+#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt
+#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int
+#define SYSCTL_INT_BOR1         0x00000002  // VDD under BOR1
+#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlResetCauseClear()
+// API or returned by the SysCtlResetCauseGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_CAUSE_HSRVREQ    0x00001000  // Hardware System Service Request
+#define SYSCTL_CAUSE_HIB        0x00000040  // Hibernate reset
+#define SYSCTL_CAUSE_WDOG1      0x00000020  // Watchdog 1 reset
+#define SYSCTL_CAUSE_SW         0x00000010  // Software reset
+#define SYSCTL_CAUSE_WDOG0      0x00000008  // Watchdog 0 reset
+#ifndef DEPRECATED
+#define SYSCTL_CAUSE_WDOG       SYSCTL_CAUSE_WDOG0
+                                            // Watchdog reset(Deprecated)
+#endif
+#define SYSCTL_CAUSE_BOR        0x00000004  // Brown-out reset
+#define SYSCTL_CAUSE_POR        0x00000002  // Power on reset
+#define SYSCTL_CAUSE_EXT        0x00000001  // External reset
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()
+// API as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_BOR_RESET        0x00000002  // Reset instead of interrupting
+#define SYSCTL_BOR_RESAMPLE     0x00000001  // Resample BOR before asserting
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPWMClockSet() API
+// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_PWMDIV_1         0x00000000  // PWM clock is processor clock /1
+#define SYSCTL_PWMDIV_2         0x00100000  // PWM clock is processor clock /2
+#define SYSCTL_PWMDIV_4         0x00120000  // PWM clock is processor clock /4
+#define SYSCTL_PWMDIV_8         0x00140000  // PWM clock is processor clock /8
+#define SYSCTL_PWMDIV_16        0x00160000  // PWM clock is processor clock /16
+#define SYSCTL_PWMDIV_32        0x00180000  // PWM clock is processor clock /32
+#define SYSCTL_PWMDIV_64        0x001A0000  // PWM clock is processor clock /64
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_1         0x07800000  // Processor clock is osc/pll /1
+#define SYSCTL_SYSDIV_2         0x00C00000  // Processor clock is osc/pll /2
+#define SYSCTL_SYSDIV_3         0x01400000  // Processor clock is osc/pll /3
+#define SYSCTL_SYSDIV_4         0x01C00000  // Processor clock is osc/pll /4
+#define SYSCTL_SYSDIV_5         0x02400000  // Processor clock is osc/pll /5
+#define SYSCTL_SYSDIV_6         0x02C00000  // Processor clock is osc/pll /6
+#define SYSCTL_SYSDIV_7         0x03400000  // Processor clock is osc/pll /7
+#define SYSCTL_SYSDIV_8         0x03C00000  // Processor clock is osc/pll /8
+#define SYSCTL_SYSDIV_9         0x04400000  // Processor clock is osc/pll /9
+#define SYSCTL_SYSDIV_10        0x04C00000  // Processor clock is osc/pll /10
+#define SYSCTL_SYSDIV_11        0x05400000  // Processor clock is osc/pll /11
+#define SYSCTL_SYSDIV_12        0x05C00000  // Processor clock is osc/pll /12
+#define SYSCTL_SYSDIV_13        0x06400000  // Processor clock is osc/pll /13
+#define SYSCTL_SYSDIV_14        0x06C00000  // Processor clock is osc/pll /14
+#define SYSCTL_SYSDIV_15        0x07400000  // Processor clock is osc/pll /15
+#define SYSCTL_SYSDIV_16        0x07C00000  // Processor clock is osc/pll /16
+#define SYSCTL_SYSDIV_17        0x88400000  // Processor clock is osc/pll /17
+#define SYSCTL_SYSDIV_18        0x88C00000  // Processor clock is osc/pll /18
+#define SYSCTL_SYSDIV_19        0x89400000  // Processor clock is osc/pll /19
+#define SYSCTL_SYSDIV_20        0x89C00000  // Processor clock is osc/pll /20
+#define SYSCTL_SYSDIV_21        0x8A400000  // Processor clock is osc/pll /21
+#define SYSCTL_SYSDIV_22        0x8AC00000  // Processor clock is osc/pll /22
+#define SYSCTL_SYSDIV_23        0x8B400000  // Processor clock is osc/pll /23
+#define SYSCTL_SYSDIV_24        0x8BC00000  // Processor clock is osc/pll /24
+#define SYSCTL_SYSDIV_25        0x8C400000  // Processor clock is osc/pll /25
+#define SYSCTL_SYSDIV_26        0x8CC00000  // Processor clock is osc/pll /26
+#define SYSCTL_SYSDIV_27        0x8D400000  // Processor clock is osc/pll /27
+#define SYSCTL_SYSDIV_28        0x8DC00000  // Processor clock is osc/pll /28
+#define SYSCTL_SYSDIV_29        0x8E400000  // Processor clock is osc/pll /29
+#define SYSCTL_SYSDIV_30        0x8EC00000  // Processor clock is osc/pll /30
+#define SYSCTL_SYSDIV_31        0x8F400000  // Processor clock is osc/pll /31
+#define SYSCTL_SYSDIV_32        0x8FC00000  // Processor clock is osc/pll /32
+#define SYSCTL_SYSDIV_33        0x90400000  // Processor clock is osc/pll /33
+#define SYSCTL_SYSDIV_34        0x90C00000  // Processor clock is osc/pll /34
+#define SYSCTL_SYSDIV_35        0x91400000  // Processor clock is osc/pll /35
+#define SYSCTL_SYSDIV_36        0x91C00000  // Processor clock is osc/pll /36
+#define SYSCTL_SYSDIV_37        0x92400000  // Processor clock is osc/pll /37
+#define SYSCTL_SYSDIV_38        0x92C00000  // Processor clock is osc/pll /38
+#define SYSCTL_SYSDIV_39        0x93400000  // Processor clock is osc/pll /39
+#define SYSCTL_SYSDIV_40        0x93C00000  // Processor clock is osc/pll /40
+#define SYSCTL_SYSDIV_41        0x94400000  // Processor clock is osc/pll /41
+#define SYSCTL_SYSDIV_42        0x94C00000  // Processor clock is osc/pll /42
+#define SYSCTL_SYSDIV_43        0x95400000  // Processor clock is osc/pll /43
+#define SYSCTL_SYSDIV_44        0x95C00000  // Processor clock is osc/pll /44
+#define SYSCTL_SYSDIV_45        0x96400000  // Processor clock is osc/pll /45
+#define SYSCTL_SYSDIV_46        0x96C00000  // Processor clock is osc/pll /46
+#define SYSCTL_SYSDIV_47        0x97400000  // Processor clock is osc/pll /47
+#define SYSCTL_SYSDIV_48        0x97C00000  // Processor clock is osc/pll /48
+#define SYSCTL_SYSDIV_49        0x98400000  // Processor clock is osc/pll /49
+#define SYSCTL_SYSDIV_50        0x98C00000  // Processor clock is osc/pll /50
+#define SYSCTL_SYSDIV_51        0x99400000  // Processor clock is osc/pll /51
+#define SYSCTL_SYSDIV_52        0x99C00000  // Processor clock is osc/pll /52
+#define SYSCTL_SYSDIV_53        0x9A400000  // Processor clock is osc/pll /53
+#define SYSCTL_SYSDIV_54        0x9AC00000  // Processor clock is osc/pll /54
+#define SYSCTL_SYSDIV_55        0x9B400000  // Processor clock is osc/pll /55
+#define SYSCTL_SYSDIV_56        0x9BC00000  // Processor clock is osc/pll /56
+#define SYSCTL_SYSDIV_57        0x9C400000  // Processor clock is osc/pll /57
+#define SYSCTL_SYSDIV_58        0x9CC00000  // Processor clock is osc/pll /58
+#define SYSCTL_SYSDIV_59        0x9D400000  // Processor clock is osc/pll /59
+#define SYSCTL_SYSDIV_60        0x9DC00000  // Processor clock is osc/pll /60
+#define SYSCTL_SYSDIV_61        0x9E400000  // Processor clock is osc/pll /61
+#define SYSCTL_SYSDIV_62        0x9EC00000  // Processor clock is osc/pll /62
+#define SYSCTL_SYSDIV_63        0x9F400000  // Processor clock is osc/pll /63
+#define SYSCTL_SYSDIV_64        0x9FC00000  // Processor clock is osc/pll /64
+#define SYSCTL_SYSDIV_2_5       0xC1000000  // Processor clock is pll / 2.5
+#define SYSCTL_SYSDIV_3_5       0xC1800000  // Processor clock is pll / 3.5
+#define SYSCTL_SYSDIV_4_5       0xC2000000  // Processor clock is pll / 4.5
+#define SYSCTL_SYSDIV_5_5       0xC2800000  // Processor clock is pll / 5.5
+#define SYSCTL_SYSDIV_6_5       0xC3000000  // Processor clock is pll / 6.5
+#define SYSCTL_SYSDIV_7_5       0xC3800000  // Processor clock is pll / 7.5
+#define SYSCTL_SYSDIV_8_5       0xC4000000  // Processor clock is pll / 8.5
+#define SYSCTL_SYSDIV_9_5       0xC4800000  // Processor clock is pll / 9.5
+#define SYSCTL_SYSDIV_10_5      0xC5000000  // Processor clock is pll / 10.5
+#define SYSCTL_SYSDIV_11_5      0xC5800000  // Processor clock is pll / 11.5
+#define SYSCTL_SYSDIV_12_5      0xC6000000  // Processor clock is pll / 12.5
+#define SYSCTL_SYSDIV_13_5      0xC6800000  // Processor clock is pll / 13.5
+#define SYSCTL_SYSDIV_14_5      0xC7000000  // Processor clock is pll / 14.5
+#define SYSCTL_SYSDIV_15_5      0xC7800000  // Processor clock is pll / 15.5
+#define SYSCTL_SYSDIV_16_5      0xC8000000  // Processor clock is pll / 16.5
+#define SYSCTL_SYSDIV_17_5      0xC8800000  // Processor clock is pll / 17.5
+#define SYSCTL_SYSDIV_18_5      0xC9000000  // Processor clock is pll / 18.5
+#define SYSCTL_SYSDIV_19_5      0xC9800000  // Processor clock is pll / 19.5
+#define SYSCTL_SYSDIV_20_5      0xCA000000  // Processor clock is pll / 20.5
+#define SYSCTL_SYSDIV_21_5      0xCA800000  // Processor clock is pll / 21.5
+#define SYSCTL_SYSDIV_22_5      0xCB000000  // Processor clock is pll / 22.5
+#define SYSCTL_SYSDIV_23_5      0xCB800000  // Processor clock is pll / 23.5
+#define SYSCTL_SYSDIV_24_5      0xCC000000  // Processor clock is pll / 24.5
+#define SYSCTL_SYSDIV_25_5      0xCC800000  // Processor clock is pll / 25.5
+#define SYSCTL_SYSDIV_26_5      0xCD000000  // Processor clock is pll / 26.5
+#define SYSCTL_SYSDIV_27_5      0xCD800000  // Processor clock is pll / 27.5
+#define SYSCTL_SYSDIV_28_5      0xCE000000  // Processor clock is pll / 28.5
+#define SYSCTL_SYSDIV_29_5      0xCE800000  // Processor clock is pll / 29.5
+#define SYSCTL_SYSDIV_30_5      0xCF000000  // Processor clock is pll / 30.5
+#define SYSCTL_SYSDIV_31_5      0xCF800000  // Processor clock is pll / 31.5
+#define SYSCTL_SYSDIV_32_5      0xD0000000  // Processor clock is pll / 32.5
+#define SYSCTL_SYSDIV_33_5      0xD0800000  // Processor clock is pll / 33.5
+#define SYSCTL_SYSDIV_34_5      0xD1000000  // Processor clock is pll / 34.5
+#define SYSCTL_SYSDIV_35_5      0xD1800000  // Processor clock is pll / 35.5
+#define SYSCTL_SYSDIV_36_5      0xD2000000  // Processor clock is pll / 36.5
+#define SYSCTL_SYSDIV_37_5      0xD2800000  // Processor clock is pll / 37.5
+#define SYSCTL_SYSDIV_38_5      0xD3000000  // Processor clock is pll / 38.5
+#define SYSCTL_SYSDIV_39_5      0xD3800000  // Processor clock is pll / 39.5
+#define SYSCTL_SYSDIV_40_5      0xD4000000  // Processor clock is pll / 40.5
+#define SYSCTL_SYSDIV_41_5      0xD4800000  // Processor clock is pll / 41.5
+#define SYSCTL_SYSDIV_42_5      0xD5000000  // Processor clock is pll / 42.5
+#define SYSCTL_SYSDIV_43_5      0xD5800000  // Processor clock is pll / 43.5
+#define SYSCTL_SYSDIV_44_5      0xD6000000  // Processor clock is pll / 44.5
+#define SYSCTL_SYSDIV_45_5      0xD6800000  // Processor clock is pll / 45.5
+#define SYSCTL_SYSDIV_46_5      0xD7000000  // Processor clock is pll / 46.5
+#define SYSCTL_SYSDIV_47_5      0xD7800000  // Processor clock is pll / 47.5
+#define SYSCTL_SYSDIV_48_5      0xD8000000  // Processor clock is pll / 48.5
+#define SYSCTL_SYSDIV_49_5      0xD8800000  // Processor clock is pll / 49.5
+#define SYSCTL_SYSDIV_50_5      0xD9000000  // Processor clock is pll / 50.5
+#define SYSCTL_SYSDIV_51_5      0xD9800000  // Processor clock is pll / 51.5
+#define SYSCTL_SYSDIV_52_5      0xDA000000  // Processor clock is pll / 52.5
+#define SYSCTL_SYSDIV_53_5      0xDA800000  // Processor clock is pll / 53.5
+#define SYSCTL_SYSDIV_54_5      0xDB000000  // Processor clock is pll / 54.5
+#define SYSCTL_SYSDIV_55_5      0xDB800000  // Processor clock is pll / 55.5
+#define SYSCTL_SYSDIV_56_5      0xDC000000  // Processor clock is pll / 56.5
+#define SYSCTL_SYSDIV_57_5      0xDC800000  // Processor clock is pll / 57.5
+#define SYSCTL_SYSDIV_58_5      0xDD000000  // Processor clock is pll / 58.5
+#define SYSCTL_SYSDIV_59_5      0xDD800000  // Processor clock is pll / 59.5
+#define SYSCTL_SYSDIV_60_5      0xDE000000  // Processor clock is pll / 60.5
+#define SYSCTL_SYSDIV_61_5      0xDE800000  // Processor clock is pll / 61.5
+#define SYSCTL_SYSDIV_62_5      0xDF000000  // Processor clock is pll / 62.5
+#define SYSCTL_SYSDIV_63_5      0xDF800000  // Processor clock is pll / 63.5
+#define SYSCTL_CFG_VCO_480      0xF1000000  // VCO is 480 MHz
+#define SYSCTL_CFG_VCO_320      0xF0000000  // VCO is 320 MHz
+#define SYSCTL_USE_PLL          0x00000000  // System clock is the PLL clock
+#define SYSCTL_USE_OSC          0x00003800  // System clock is the osc clock
+#define SYSCTL_XTAL_1MHZ        0x00000000  // External crystal is 1MHz
+#define SYSCTL_XTAL_1_84MHZ     0x00000040  // External crystal is 1.8432MHz
+#define SYSCTL_XTAL_2MHZ        0x00000080  // External crystal is 2MHz
+#define SYSCTL_XTAL_2_45MHZ     0x000000C0  // External crystal is 2.4576MHz
+#define SYSCTL_XTAL_3_57MHZ     0x00000100  // External crystal is 3.579545MHz
+#define SYSCTL_XTAL_3_68MHZ     0x00000140  // External crystal is 3.6864MHz
+#define SYSCTL_XTAL_4MHZ        0x00000180  // External crystal is 4MHz
+#define SYSCTL_XTAL_4_09MHZ     0x000001C0  // External crystal is 4.096MHz
+#define SYSCTL_XTAL_4_91MHZ     0x00000200  // External crystal is 4.9152MHz
+#define SYSCTL_XTAL_5MHZ        0x00000240  // External crystal is 5MHz
+#define SYSCTL_XTAL_5_12MHZ     0x00000280  // External crystal is 5.12MHz
+#define SYSCTL_XTAL_6MHZ        0x000002C0  // External crystal is 6MHz
+#define SYSCTL_XTAL_6_14MHZ     0x00000300  // External crystal is 6.144MHz
+#define SYSCTL_XTAL_7_37MHZ     0x00000340  // External crystal is 7.3728MHz
+#define SYSCTL_XTAL_8MHZ        0x00000380  // External crystal is 8MHz
+#define SYSCTL_XTAL_8_19MHZ     0x000003C0  // External crystal is 8.192MHz
+#define SYSCTL_XTAL_10MHZ       0x00000400  // External crystal is 10 MHz
+#define SYSCTL_XTAL_12MHZ       0x00000440  // External crystal is 12 MHz
+#define SYSCTL_XTAL_12_2MHZ     0x00000480  // External crystal is 12.288 MHz
+#define SYSCTL_XTAL_13_5MHZ     0x000004C0  // External crystal is 13.56 MHz
+#define SYSCTL_XTAL_14_3MHZ     0x00000500  // External crystal is 14.31818 MHz
+#define SYSCTL_XTAL_16MHZ       0x00000540  // External crystal is 16 MHz
+#define SYSCTL_XTAL_16_3MHZ     0x00000580  // External crystal is 16.384 MHz
+#define SYSCTL_XTAL_18MHZ       0x000005C0  // External crystal is 18.0 MHz
+#define SYSCTL_XTAL_20MHZ       0x00000600  // External crystal is 20.0 MHz
+#define SYSCTL_XTAL_24MHZ       0x00000640  // External crystal is 24.0 MHz
+#define SYSCTL_XTAL_25MHZ       0x00000680  // External crystal is 25.0 MHz
+#define SYSCTL_OSC_MAIN         0x00000000  // Osc source is main osc
+#define SYSCTL_OSC_INT          0x00000010  // Osc source is int. osc
+#define SYSCTL_OSC_INT4         0x00000020  // Osc source is int. osc /4
+#define SYSCTL_OSC_INT30        0x00000030  // Osc source is int. 30 KHz
+#define SYSCTL_OSC_EXT32        0x80000038  // Osc source is ext. 32 KHz
+#define SYSCTL_INT_OSC_DIS      0x00000002  // Disable internal oscillator
+#define SYSCTL_MAIN_OSC_DIS     0x00000001  // Disable main oscillator
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlDeepSleepClockSet()
+// API as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_DSLP_DIV_1       0x00000000  // Deep-sleep clock is osc /1
+#define SYSCTL_DSLP_DIV_2       0x00800000  // Deep-sleep clock is osc /2
+#define SYSCTL_DSLP_DIV_3       0x01000000  // Deep-sleep clock is osc /3
+#define SYSCTL_DSLP_DIV_4       0x01800000  // Deep-sleep clock is osc /4
+#define SYSCTL_DSLP_DIV_5       0x02000000  // Deep-sleep clock is osc /5
+#define SYSCTL_DSLP_DIV_6       0x02800000  // Deep-sleep clock is osc /6
+#define SYSCTL_DSLP_DIV_7       0x03000000  // Deep-sleep clock is osc /7
+#define SYSCTL_DSLP_DIV_8       0x03800000  // Deep-sleep clock is osc /8
+#define SYSCTL_DSLP_DIV_9       0x04000000  // Deep-sleep clock is osc /9
+#define SYSCTL_DSLP_DIV_10      0x04800000  // Deep-sleep clock is osc /10
+#define SYSCTL_DSLP_DIV_11      0x05000000  // Deep-sleep clock is osc /11
+#define SYSCTL_DSLP_DIV_12      0x05800000  // Deep-sleep clock is osc /12
+#define SYSCTL_DSLP_DIV_13      0x06000000  // Deep-sleep clock is osc /13
+#define SYSCTL_DSLP_DIV_14      0x06800000  // Deep-sleep clock is osc /14
+#define SYSCTL_DSLP_DIV_15      0x07000000  // Deep-sleep clock is osc /15
+#define SYSCTL_DSLP_DIV_16      0x07800000  // Deep-sleep clock is osc /16
+#define SYSCTL_DSLP_DIV_17      0x08000000  // Deep-sleep clock is osc /17
+#define SYSCTL_DSLP_DIV_18      0x08800000  // Deep-sleep clock is osc /18
+#define SYSCTL_DSLP_DIV_19      0x09000000  // Deep-sleep clock is osc /19
+#define SYSCTL_DSLP_DIV_20      0x09800000  // Deep-sleep clock is osc /20
+#define SYSCTL_DSLP_DIV_21      0x0A000000  // Deep-sleep clock is osc /21
+#define SYSCTL_DSLP_DIV_22      0x0A800000  // Deep-sleep clock is osc /22
+#define SYSCTL_DSLP_DIV_23      0x0B000000  // Deep-sleep clock is osc /23
+#define SYSCTL_DSLP_DIV_24      0x0B800000  // Deep-sleep clock is osc /24
+#define SYSCTL_DSLP_DIV_25      0x0C000000  // Deep-sleep clock is osc /25
+#define SYSCTL_DSLP_DIV_26      0x0C800000  // Deep-sleep clock is osc /26
+#define SYSCTL_DSLP_DIV_27      0x0D000000  // Deep-sleep clock is osc /27
+#define SYSCTL_DSLP_DIV_28      0x0D800000  // Deep-sleep clock is osc /28
+#define SYSCTL_DSLP_DIV_29      0x0E000000  // Deep-sleep clock is osc /29
+#define SYSCTL_DSLP_DIV_30      0x0E800000  // Deep-sleep clock is osc /30
+#define SYSCTL_DSLP_DIV_31      0x0F000000  // Deep-sleep clock is osc /31
+#define SYSCTL_DSLP_DIV_32      0x0F800000  // Deep-sleep clock is osc /32
+#define SYSCTL_DSLP_DIV_33      0x10000000  // Deep-sleep clock is osc /33
+#define SYSCTL_DSLP_DIV_34      0x10800000  // Deep-sleep clock is osc /34
+#define SYSCTL_DSLP_DIV_35      0x11000000  // Deep-sleep clock is osc /35
+#define SYSCTL_DSLP_DIV_36      0x11800000  // Deep-sleep clock is osc /36
+#define SYSCTL_DSLP_DIV_37      0x12000000  // Deep-sleep clock is osc /37
+#define SYSCTL_DSLP_DIV_38      0x12800000  // Deep-sleep clock is osc /38
+#define SYSCTL_DSLP_DIV_39      0x13000000  // Deep-sleep clock is osc /39
+#define SYSCTL_DSLP_DIV_40      0x13800000  // Deep-sleep clock is osc /40
+#define SYSCTL_DSLP_DIV_41      0x14000000  // Deep-sleep clock is osc /41
+#define SYSCTL_DSLP_DIV_42      0x14800000  // Deep-sleep clock is osc /42
+#define SYSCTL_DSLP_DIV_43      0x15000000  // Deep-sleep clock is osc /43
+#define SYSCTL_DSLP_DIV_44      0x15800000  // Deep-sleep clock is osc /44
+#define SYSCTL_DSLP_DIV_45      0x16000000  // Deep-sleep clock is osc /45
+#define SYSCTL_DSLP_DIV_46      0x16800000  // Deep-sleep clock is osc /46
+#define SYSCTL_DSLP_DIV_47      0x17000000  // Deep-sleep clock is osc /47
+#define SYSCTL_DSLP_DIV_48      0x17800000  // Deep-sleep clock is osc /48
+#define SYSCTL_DSLP_DIV_49      0x18000000  // Deep-sleep clock is osc /49
+#define SYSCTL_DSLP_DIV_50      0x18800000  // Deep-sleep clock is osc /50
+#define SYSCTL_DSLP_DIV_51      0x19000000  // Deep-sleep clock is osc /51
+#define SYSCTL_DSLP_DIV_52      0x19800000  // Deep-sleep clock is osc /52
+#define SYSCTL_DSLP_DIV_53      0x1A000000  // Deep-sleep clock is osc /53
+#define SYSCTL_DSLP_DIV_54      0x1A800000  // Deep-sleep clock is osc /54
+#define SYSCTL_DSLP_DIV_55      0x1B000000  // Deep-sleep clock is osc /55
+#define SYSCTL_DSLP_DIV_56      0x1B800000  // Deep-sleep clock is osc /56
+#define SYSCTL_DSLP_DIV_57      0x1C000000  // Deep-sleep clock is osc /57
+#define SYSCTL_DSLP_DIV_58      0x1C800000  // Deep-sleep clock is osc /58
+#define SYSCTL_DSLP_DIV_59      0x1D000000  // Deep-sleep clock is osc /59
+#define SYSCTL_DSLP_DIV_60      0x1D800000  // Deep-sleep clock is osc /60
+#define SYSCTL_DSLP_DIV_61      0x1E000000  // Deep-sleep clock is osc /61
+#define SYSCTL_DSLP_DIV_62      0x1E800000  // Deep-sleep clock is osc /62
+#define SYSCTL_DSLP_DIV_63      0x1F000000  // Deep-sleep clock is osc /63
+#define SYSCTL_DSLP_DIV_64      0x1F800000  // Deep-sleep clock is osc /64
+#define SYSCTL_DSLP_OSC_MAIN    0x00000000  // Osc source is main osc
+#define SYSCTL_DSLP_OSC_INT     0x00000010  // Osc source is int. osc
+#define SYSCTL_DSLP_OSC_INT30   0x00000030  // Osc source is int. 30 KHz
+#define SYSCTL_DSLP_OSC_EXT32   0x00000070  // Osc source is ext. 32 KHz
+#define SYSCTL_DSLP_PIOSC_PD    0x00000002  // Power down PIOSC in deep-sleep
+#define SYSCTL_DSLP_MOSC_PD     0x40000000  // Power down MOSC in deep-sleep
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPIOSCCalibrate()
+// API as the ui32Type parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSC_CAL_AUTO   0x00000200  // Automatic calibration
+#define SYSCTL_PIOSC_CAL_FACT   0x00000100  // Factory calibration
+#define SYSCTL_PIOSC_CAL_USER   0x80000100  // User-supplied calibration
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlMOSCConfigSet() API
+// as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_MOSC_VALIDATE    0x00000001  // Enable MOSC validation
+#define SYSCTL_MOSC_INTERRUPT   0x00000002  // Generate interrupt on MOSC fail
+#define SYSCTL_MOSC_NO_XTAL     0x00000004  // No crystal is attached to MOSC
+#define SYSCTL_MOSC_PWR_DIS     0x00000008  // Power down the MOSC.
+#define SYSCTL_MOSC_LOWFREQ     0x00000000  // MOSC is less than 10MHz
+#define SYSCTL_MOSC_HIGHFREQ    0x00000010  // MOSC is greater than 10MHz
+#define SYSCTL_MOSC_SESRC       0x00000020  // Singled ended oscillator source.
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlSleepPowerSet() and
+// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_LDO_SLEEP        0x00000200  // LDO in sleep mode
+                                            // (Deep Sleep Only)
+#define SYSCTL_TEMP_LOW_POWER   0x00000100  // Temp sensor in low power mode
+                                            // (Deep Sleep Only)
+#define SYSCTL_FLASH_NORMAL     0x00000000  // Flash in normal mode
+#define SYSCTL_FLASH_LOW_POWER  0x00000020  // Flash in low power mode
+#define SYSCTL_SRAM_NORMAL      0x00000000  // SRAM in normal mode
+#define SYSCTL_SRAM_STANDBY     0x00000001  // SRAM in standby mode
+#define SYSCTL_SRAM_LOW_POWER   0x00000003  // SRAM in low power mode
+
+//*****************************************************************************
+//
+// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs.
+//
+//*****************************************************************************
+#define SYSCTL_ONRST_WDOG0_POR  0x00000030
+#define SYSCTL_ONRST_WDOG0_SYS  0x00000020
+#define SYSCTL_ONRST_WDOG1_POR  0x000000C0
+#define SYSCTL_ONRST_WDOG1_SYS  0x00000080
+#define SYSCTL_ONRST_BOR_POR    0x0000000C
+#define SYSCTL_ONRST_BOR_SYS    0x00000008
+#define SYSCTL_ONRST_EXT_POR    0x00000003
+#define SYSCTL_ONRST_EXT_SYS    0x00000002
+
+//*****************************************************************************
+//
+// Values used with the SysCtlVoltageEventConfig() API.
+//
+//*****************************************************************************
+#define SYSCTL_VEVENT_VDDABO_NONE                                             \
+                                0x00000000
+#define SYSCTL_VEVENT_VDDABO_INT                                              \
+                                0x00000100
+#define SYSCTL_VEVENT_VDDABO_NMI                                              \
+                                0x00000200
+#define SYSCTL_VEVENT_VDDABO_RST                                              \
+                                0x00000300
+#define SYSCTL_VEVENT_VDDBO_NONE                                              \
+                                0x00000000
+#define SYSCTL_VEVENT_VDDBO_INT 0x00000001
+#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002
+#define SYSCTL_VEVENT_VDDBO_RST 0x00000003
+
+//*****************************************************************************
+//
+// Values used with the SysCtlVoltageEventStatus() and
+// SysCtlVoltageEventClear() APIs.
+//
+//*****************************************************************************
+#define SYSCTL_VESTAT_VDDBOR    0x00000040
+#define SYSCTL_VESTAT_VDDABOR   0x00000010
+
+//*****************************************************************************
+//
+// Values used with the SysCtlNMIStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_NMI_MOSCFAIL     0x00010000
+#define SYSCTL_NMI_TAMPER       0x00000200
+#define SYSCTL_NMI_WDT1         0x00000020
+#define SYSCTL_NMI_WDT0         0x00000008
+#define SYSCTL_NMI_POWER        0x00000004
+#define SYSCTL_NMI_EXTERNAL     0x00000001
+
+//*****************************************************************************
+//
+// The defines for the SysCtlClockOutConfig() API.
+//
+//*****************************************************************************
+#define SYSCTL_CLKOUT_EN        0x80000000
+#define SYSCTL_CLKOUT_DIS       0x00000000
+#define SYSCTL_CLKOUT_SYSCLK    0x00000000
+#define SYSCTL_CLKOUT_PIOSC     0x00010000
+#define SYSCTL_CLKOUT_MOSC      0x00020000
+
+//*****************************************************************************
+//
+// The following defines are used with the SysCtlAltClkConfig() function.
+//
+//*****************************************************************************
+#define SYSCTL_ALTCLK_PIOSC     0x00000000
+#define SYSCTL_ALTCLK_RTCOSC    0x00000003
+#define SYSCTL_ALTCLK_LFIOSC    0x00000004
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern uint32_t SysCtlSRAMSizeGet(void);
+extern uint32_t SysCtlFlashSizeGet(void);
+extern uint32_t SysCtlFlashSectorSizeGet(void);
+extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral);
+extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralReset(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralClockGating(bool bEnable);
+extern void SysCtlIntRegister(void (*pfnHandler)(void));
+extern void SysCtlIntUnregister(void);
+extern void SysCtlIntEnable(uint32_t ui32Ints);
+extern void SysCtlIntDisable(uint32_t ui32Ints);
+extern void SysCtlIntClear(uint32_t ui32Ints);
+extern uint32_t SysCtlIntStatus(bool bMasked);
+extern void SysCtlLDOSleepSet(uint32_t ui32Voltage);
+extern uint32_t SysCtlLDOSleepGet(void);
+extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage);
+extern uint32_t SysCtlLDODeepSleepGet(void);
+extern void SysCtlSleepPowerSet(uint32_t ui32Config);
+extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config);
+extern void SysCtlReset(void);
+extern void SysCtlSleep(void);
+extern void SysCtlDeepSleep(void);
+extern uint32_t SysCtlResetCauseGet(void);
+extern void SysCtlResetCauseClear(uint32_t ui32Causes);
+extern void SysCtlBrownOutConfigSet(uint32_t ui32Config,
+                                    uint32_t ui32Delay);
+extern void SysCtlDelay(uint32_t ui32Count);
+extern void SysCtlMOSCConfigSet(uint32_t ui32Config);
+extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type);
+extern void SysCtlClockSet(uint32_t ui32Config);
+extern uint32_t SysCtlClockGet(void);
+extern void SysCtlDeepSleepClockSet(uint32_t ui32Config);
+extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div,
+                                          uint32_t ui32Config);
+extern void SysCtlPWMClockSet(uint32_t ui32Config);
+extern uint32_t SysCtlPWMClockGet(void);
+extern void SysCtlIOSCVerificationSet(bool bEnable);
+extern void SysCtlMOSCVerificationSet(bool bEnable);
+extern void SysCtlPLLVerificationSet(bool bEnable);
+extern void SysCtlClkVerificationClear(void);
+extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral);
+extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config,
+                                   uint32_t ui32SysClock);
+extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior);
+extern uint32_t SysCtlResetBehaviorGet(void);
+extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div);
+extern void SysCtlAltClkConfig(uint32_t ui32Config);
+extern uint32_t SysCtlNMIStatus(void);
+extern void SysCtlNMIClear(uint32_t ui32Status);
+extern void SysCtlVoltageEventConfig(uint32_t ui32Config);
+extern uint32_t SysCtlVoltageEventStatus(void);
+extern void SysCtlVoltageEventClear(uint32_t ui32Status);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SYSCTL_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/sysexc.c b/bsp/tm4c129x/libraries/driverlib/sysexc.c
new file mode 100644
index 0000000000..c34d73be33
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/sysexc.c
@@ -0,0 +1,311 @@
+//*****************************************************************************
+//
+// sysexc.c - Routines for the System Exception Module.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysexc_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_sysexc.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Returns the interrupt number for a system exception.
+//!
+//! This function returns the interrupt number for a system exception.
+//!
+//! \return Returns the system exception interrupt number.
+//
+//*****************************************************************************
+static uint32_t
+_SysExcIntNumberGet(void)
+{
+    uint32_t ui32Int;
+
+    //
+    // Get the interrupt number based on the class.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        ui32Int = INT_SYSEXC_TM4C123;
+    }
+    else if(CLASS_IS_TM4C129)
+    {
+        ui32Int = INT_SYSEXC_TM4C129;
+    }
+    else
+    {
+        ui32Int = 0;
+    }
+    return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system exception interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! exception interrupt occurs.
+//!
+//! This function places the address of the system exception interrupt handler
+//! into the interrupt vector table in SRAM.  This function also enables the
+//! global interrupt in the interrupt controller; specific system exception
+//! interrupts must be enabled via SysExcIntEnable().  It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntRegister(void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Get the system exception interrupt number.
+    //
+    ui32Int = _SysExcIntNumberGet();
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the system exception interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the system exception interrupt handler.
+//!
+//! This function removes the system exception interrupt handler from the
+//! vector table in SRAM.  This function also masks off the system exception
+//! interrupt in the interrupt controller so that the interrupt handler is no
+//! longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntUnregister(void)
+{
+    uint32_t ui32Int;
+
+    //
+    // Get the system exception interrupt number.
+    //
+    ui32Int = _SysExcIntNumberGet();
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the system exception interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the system exception interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system exception interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated system exception interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
+//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
+//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
+//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
+//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
+//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntEnable(uint32_t ui32IntFlags)
+{
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(SYSEXC_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system exception interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated system exception interrupt sources.
+//! Only sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
+//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
+//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
+//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
+//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
+//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntDisable(uint32_t ui32IntFlags)
+{
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(SYSEXC_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current system exception interrupt status.
+//!
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the system exception interrupt status.  Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current system exception interrupt status, enumerated
+//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC,
+//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and
+//! \b SYSEXC_INT_FP_IDC.
+//
+//*****************************************************************************
+uint32_t
+SysExcIntStatus(bool bMasked)
+{
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(SYSEXC_MIS));
+    }
+    else
+    {
+        return(HWREG(SYSEXC_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears system exception interrupt sources.
+//!
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified system exception interrupt sources, so
+//! that they no longer assert.  This function must be called in the interrupt
+//! handler to keep the interrupt from being recognized again immediately upon
+//! exit.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
+//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
+//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
+//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
+//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
+//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntClear(uint32_t ui32IntFlags)
+{
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(SYSEXC_IC) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/sysexc.h b/bsp/tm4c129x/libraries/driverlib/sysexc.h
new file mode 100644
index 0000000000..10febaa333
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/sysexc.h
@@ -0,0 +1,89 @@
+//*****************************************************************************
+//
+// sysexc.h - Prototypes for the System Exception Module routines.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SYSEXC_H__
+#define __DRIVERLIB_SYSEXC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
+// SysExcIntClear as the ui32IntFlags parameter, and returned from
+// SysExcIntStatus.
+//
+//*****************************************************************************
+#define SYSEXC_INT_FP_IXC       0x00000020  // FP Inexact exception interrupt
+#define SYSEXC_INT_FP_OFC       0x00000010  // FP Overflow exception interrupt
+#define SYSEXC_INT_FP_UFC       0x00000008  // FP Underflow exception interrupt
+#define SYSEXC_INT_FP_IOC       0x00000004  // FP Invalid operation interrupt
+#define SYSEXC_INT_FP_DZC       0x00000002  // FP Divide by zero exception int
+#define SYSEXC_INT_FP_IDC       0x00000001  // FP Input denormal exception int
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern void SysExcIntRegister(void (*pfnHandler)(void));
+extern void SysExcIntUnregister(void);
+extern void SysExcIntEnable(uint32_t ui32IntFlags);
+extern void SysExcIntDisable(uint32_t ui32IntFlags);
+extern uint32_t SysExcIntStatus(bool bMasked);
+extern void SysExcIntClear(uint32_t ui32IntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SYSEXC_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/systick.c b/bsp/tm4c129x/libraries/driverlib/systick.c
new file mode 100644
index 0000000000..e8b45b2f5b
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/systick.c
@@ -0,0 +1,277 @@
+//*****************************************************************************
+//
+// systick.c - Driver for the SysTick timer in NVIC.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/systick.h"
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This function starts the SysTick counter.  If an interrupt handler has been
+//! registered, it is called when the SysTick counter rolls over.
+//!
+//! \note Calling this function causes the SysTick counter to (re)commence
+//! counting from its current value.  The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet().  If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force the reload.  Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+    //
+    // Enable SysTick.
+    //
+    HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This function stops the SysTick counter.  If an interrupt handler has been
+//! registered, it is not called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+    //
+    // Disable SysTick.
+    //
+    HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This function registers the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(FAULT_SYSTICK, pfnHandler);
+
+    //
+    // Enable the SysTick interrupt.
+    //
+    HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function unregisters the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+    //
+    // Disable the SysTick interrupt.
+    //
+    HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(FAULT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function enables the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler is not required to clear the SysTick
+//! interrupt source because it is cleared automatically by the NVIC when the
+//! interrupt handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+    //
+    // Enable the SysTick interrupt.
+    //
+    HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function disables the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+    //
+    // Disable the SysTick interrupt.
+    //
+    HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ui32Period is the number of clock ticks in each period of the
+//! SysTick counter and must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately.  If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written.  Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the \e ui32Period supplied here on
+//! the next clock after SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(uint32_t ui32Period)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Period > 0) && (ui32Period <= 16777216));
+
+    //
+    // Set the period of the SysTick counter.
+    //
+    HWREG(NVIC_ST_RELOAD) = ui32Period - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+uint32_t
+SysTickPeriodGet(void)
+{
+    //
+    // Return the period of the SysTick counter.
+    //
+    return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter, which is
+//! a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+uint32_t
+SysTickValueGet(void)
+{
+    //
+    // Return the current value of the SysTick counter.
+    //
+    return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/systick.h b/bsp/tm4c129x/libraries/driverlib/systick.h
new file mode 100644
index 0000000000..513f1ebdaa
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/systick.h
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// systick.h - Prototypes for the SysTick driver.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SYSTICK_H__
+#define __DRIVERLIB_SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(uint32_t ui32Period);
+extern uint32_t SysTickPeriodGet(void);
+extern uint32_t SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SYSTICK_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/tiva_timer.c b/bsp/tm4c129x/libraries/driverlib/tiva_timer.c
new file mode 100644
index 0000000000..7f1db43753
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/tiva_timer.c
@@ -0,0 +1,1895 @@
+//*****************************************************************************
+//
+// timer.c - Driver for the timer module.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_types.h"
+#include "inc/hw_sysctl.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/tiva_timer.h"
+
+//*****************************************************************************
+//
+// A macro used to determine whether the target part supports new
+// configuration and control options.
+//
+//*****************************************************************************
+#define NEW_TIMER_CONFIGURATION CLASS_IS_TM4C129
+
+//*****************************************************************************
+//
+// A mapping of timer base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32TimerIntMap[][2] =
+{
+    { TIMER0_BASE, INT_TIMER0A_TM4C123 },
+    { TIMER1_BASE, INT_TIMER1A_TM4C123 },
+    { TIMER2_BASE, INT_TIMER2A_TM4C123 },
+    { TIMER3_BASE, INT_TIMER3A_TM4C123 },
+    { TIMER4_BASE, INT_TIMER4A_TM4C123 },
+    { TIMER5_BASE, INT_TIMER5A_TM4C123 },
+    { WTIMER0_BASE, INT_WTIMER0A_TM4C123 },
+    { WTIMER1_BASE, INT_WTIMER1A_TM4C123 },
+    { WTIMER2_BASE, INT_WTIMER2A_TM4C123 },
+    { WTIMER3_BASE, INT_WTIMER3A_TM4C123 },
+    { WTIMER4_BASE, INT_WTIMER4A_TM4C123 },
+    { WTIMER5_BASE, INT_WTIMER5A_TM4C123 },
+};
+static const uint_fast8_t g_ui8TimerIntMapRows =
+    sizeof(g_ppui32TimerIntMap) / sizeof(g_ppui32TimerIntMap[0]);
+
+static const uint32_t g_ppui32TimerIntMapSnowflake[][2] =
+{
+    { TIMER0_BASE, INT_TIMER0A_TM4C129 },
+    { TIMER1_BASE, INT_TIMER1A_TM4C129 },
+    { TIMER2_BASE, INT_TIMER2A_TM4C129 },
+    { TIMER3_BASE, INT_TIMER3A_TM4C129 },
+    { TIMER4_BASE, INT_TIMER4A_TM4C129 },
+    { TIMER5_BASE, INT_TIMER5A_TM4C129 },
+    { TIMER6_BASE, INT_TIMER6A_TM4C129 },
+    { TIMER7_BASE, INT_TIMER7A_TM4C129 },
+};
+static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake =
+    sizeof(g_ppui32TimerIntMapSnowflake) /
+    sizeof(g_ppui32TimerIntMapSnowflake[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a timer base address.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_TimerBaseValid(uint32_t ui32Base)
+{
+    return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) ||
+           (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) ||
+           (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) ||
+           (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) ||
+           (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) ||
+           (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Returns a timer modules interrupt number.
+//!
+//! \param ui32Base is the base address of the selected timer.
+//! \param ui32Timer specifies the timer(s) to enable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function returns the interrupt number for a given timer module
+//! specified by the \e ui32Base and \e ui32Timer parameter.
+//!
+//! \return Returns a timer module's interrupt number or 0 if the interrupt
+//! does not exist.
+//
+//*****************************************************************************
+static uint32_t
+_TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    uint32_t ui32Int;
+    uint_fast8_t ui8Idx, ui8Rows;
+    const uint32_t (*ppui32SSIIntMap)[2];
+
+    //
+    // Default interrupt map.
+    //
+    ppui32SSIIntMap = g_ppui32TimerIntMap;
+    ui8Rows = g_ui8TimerIntMapRows;
+
+    if(CLASS_IS_TM4C129)
+    {
+        ppui32SSIIntMap = g_ppui32TimerIntMapSnowflake;
+        ui8Rows = g_ui8TimerIntMapRowsSnowflake;
+    }
+
+    //
+    // Loop through the table that maps timer base addresses to interrupt
+    // numbers.
+    //
+    for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
+    {
+        //
+        // See if this base address matches.
+        //
+        if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
+        {
+            ui32Int = ppui32SSIIntMap[ui8Idx][1];
+
+            if(ui32Timer == TIMER_B)
+            {
+                ui32Int += 1;
+            }
+
+            //
+            // Return the corresponding interrupt number.
+            //
+            return(ui32Int);
+        }
+    }
+
+    //
+    // The base address could not be found, so return an error.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Enables the timer(s).
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to enable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function enables operation of the timer module.  The timer must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerEnable(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Enable the timer(s) module.
+    //
+    HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN |
+                                                  TIMER_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! Disables the timer(s).
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to disable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function disables operation of the timer module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDisable(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Disable the timer module.
+    //
+    HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer &
+                                       (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! Configures the timer(s).
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Config is the configuration for the timer.
+//!
+//! This function configures the operating mode of the timer(s).  The timer
+//! module is disabled before being configured and is left in the disabled
+//! state.  The timer can be configured to be a single full-width timer
+//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the
+//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ui32Config
+//! parameter.
+//!
+//! The configuration is specified in \e ui32Config as one of the following
+//! values:
+//!
+//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer
+//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up
+//!   instead of down (not available on all parts)
+//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer
+//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up
+//!   instead of down (not available on all parts)
+//! - \b TIMER_CFG_RTC - Full-width real time clock timer
+//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers
+//!
+//! When configured for a pair of half-width timers, each timer is separately
+//! configured.  The first timer is configured by setting \e ui32Config to
+//! the result of a logical OR operation between one of the following values
+//! and \e ui32Config:
+//!
+//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up
+//!   instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer
+//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up
+//!   instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture
+//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts
+//!   up instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture
+//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up
+//!   instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_PWM - Half-width PWM output
+//!
+//! Some Tiva devices also allow configuring an action when the timers
+//! reach their timeout.  Please consult the data sheet for the part you are
+//! using to determine whether configuring actions on timers is available.
+//!
+//! One of the following can be combined with the  \b TIMER_CFG_* values to
+//! enable an action on timer A:
+//!
+//! - \b TIMER_CFG_A_ACT_TOINTD - masks the timeout interrupt of timer A.
+//! - \b TIMER_CFG_A_ACT_NONE - no additional action on timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_TOGGLE - toggle CCP on timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_SETTO - set CCP on timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_CLRTO - clear CCP on timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_SETTOGTO - set CCP immediately and then toggle it on
+//!      timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_CLRTOGTO - clear CCP immediately and then toggle it on
+//!      timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_SETCLRTO - set CCP immediately and then clear it on
+//!      timeout of timer A.
+//! - \b TIMER_CFG_A_ACT_CLRSETTO - clear CCP immediately and then set it on
+//!      timeout of timer A.
+//!
+//! One of the following can be combined with the \b TIMER_CFG_* values to
+//! enable an action on timer B:
+//!
+//! - \b TIMER_CFG_B_ACT_TOINTD - masks the timeout interrupt of timer B.
+//! - \b TIMER_CFG_B_ACT_NONE - no additional action on timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_TOGGLE - toggle CCP on timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_SETTO - set CCP on timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_CLRTO - clear CCP on timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_SETTOGTO - set CCP immediately and then toggle it on
+//!      timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_CLRTOGTO - clear CCP immediately and then toggle it on
+//!      timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_SETCLRTO - set CCP immediately and then clear it on
+//!      timeout of timer B.
+//! - \b TIMER_CFG_B_ACT_CLRSETTO - clear CCP immediately and then set it on
+//!      timeout of timer B.
+//!
+//! Similarly, the second timer is configured by setting \e ui32Config to
+//! the result of a logical OR operation between one of the corresponding
+//! \b TIMER_CFG_B_* values and \e ui32Config.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
+           (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
+           (ui32Config == TIMER_CFG_PERIODIC) ||
+           (ui32Config == TIMER_CFG_PERIODIC_UP) ||
+           (ui32Config == TIMER_CFG_RTC) ||
+           ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
+    ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
+           ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) &&
+            (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
+             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM))));
+
+    //
+    // Disable the timers.
+    //
+    HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+
+    //
+    // Set the global timer configuration.
+    //
+    HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24;
+
+    //
+    // Set the configuration of the A and B timers and set the TxPWMIE bit.
+    // Note that the B timer configuration is ignored by the hardware in 32-bit
+    // modes.
+    //
+    if(NEW_TIMER_CONFIGURATION)
+    {
+        HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) |
+                                          (ui32Config & 0xff) |
+                                          TIMER_TAMR_TAPWMIE);
+        HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) |
+                                          ((ui32Config >> 8) & 0xff) |
+                                          TIMER_TBMR_TBPWMIE);
+    }
+    else
+    {
+        HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) |
+                                          TIMER_TAMR_TAPWMIE);
+        HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) |
+                                          TIMER_TBMR_TBPWMIE);
+    }
+}
+
+//*****************************************************************************
+//
+//! Controls the output level.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bInvert specifies the output level.
+//!
+//! This function configures the PWM output level for the specified timer.  If
+//! the \e bInvert parameter is \b true, then the timer's output is made active
+//! low; otherwise, it is made active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Set the output levels as requested.
+    //
+    ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
+    HWREG(ui32Base + TIMER_O_CTL) = (bInvert ?
+                                     (HWREG(ui32Base + TIMER_O_CTL) |
+                                      ui32Timer) :
+                                     (HWREG(ui32Base + TIMER_O_CTL) &
+                                      ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+//! Enables or disables the ADC trigger output.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bEnable specifies the desired ADC trigger state.
+//!
+//! This function controls the ADC trigger output for the specified timer.  If
+//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is
+//! enabled; otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+                    bool bEnable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // On newer devices the Timer time out ADC trigger enable must also
+    // be set.
+    //
+    if(NEW_TIMER_CONFIGURATION)
+    {
+        uint32_t ui32Val;
+
+        //
+        // Determine which bits to set or clear in GPTMADCEV.
+        //
+        ui32Val = (TIMER_ADCEV_TATOADCEN | TIMER_ADCEV_TBTOADCEN);
+        ui32Val &= ui32Timer;
+
+        //
+        // Write the GPTM ADC Event register to enable or disable the trigger
+        // to the ADC.
+        //
+        HWREG(ui32Base + TIMER_O_ADCEV) = (bEnable ?
+                                           (HWREG(ui32Base + TIMER_O_ADCEV) |
+                                            ui32Val) :
+                                           (HWREG(ui32Base + TIMER_O_ADCEV) &
+                                            ~(ui32Val)));
+    }
+
+    //
+    // Set the trigger output as requested.
+    // Set the ADC trigger output as requested.
+    //
+    ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
+    HWREG(ui32Base + TIMER_O_CTL) = (bEnable ?
+                                     (HWREG(ui32Base + TIMER_O_CTL) |
+                                      ui32Timer) :
+                                     (HWREG(ui32Base + TIMER_O_CTL) &
+                                      ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the event type.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Event specifies the type of event; must be one of
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
+//! \b TIMER_EVENT_BOTH_EDGES.
+//!
+//! This function configures the signal edge(s) that triggers the timer when
+//! in capture mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer,
+                  uint32_t ui32Event)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Set the event type.
+    //
+    ui32Timer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M;
+    HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) &
+                                      ~ui32Timer) | (ui32Event & ui32Timer));
+}
+
+//*****************************************************************************
+//
+//! Controls the stall handling.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bStall specifies the response to a stall signal.
+//!
+//! This function controls the stall response for the specified timer.  If the
+//! \e bStall parameter is \b true, then the timer stops counting if the
+//! processor enters debug mode; otherwise the timer keeps running while in
+//! debug mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer,
+                  bool bStall)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Set the stall mode.
+    //
+    ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
+    HWREG(ui32Base + TIMER_O_CTL) = (bStall ?
+                                     (HWREG(ui32Base + TIMER_O_CTL) |
+                                      ui32Timer) :
+                                     (HWREG(ui32Base + TIMER_O_CTL) &
+                                      ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the wait on trigger handling.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bWait specifies if the timer should wait for a trigger input.
+//!
+//! This function controls whether or not a timer waits for a trigger input to
+//! start counting.  When enabled, the previous timer in the trigger chain must
+//! count to its timeout in order for this timer to start counting.  Refer to
+//! the part's data sheet for a description of the trigger chain.
+//!
+//! \note This functionality is not available on all parts.  This function
+//! should not be used for Timer 0A or Wide Timer 0A.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+                          bool bWait)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Set the wait on trigger mode for timer A.
+    //
+    if((ui32Timer & TIMER_A) != 0)
+    {
+        if(bWait)
+        {
+            HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
+        }
+        else
+        {
+            HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
+        }
+    }
+
+    //
+    // Set the wait on trigger mode for timer B.
+    //
+    if((ui32Timer & TIMER_B) != 0)
+    {
+        if(bWait)
+        {
+            HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
+        }
+        else
+        {
+            HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables RTC counting.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function causes the timer to start counting when in RTC mode.  If not
+//! configured for RTC mode, this function does nothing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Enable RTC counting.
+    //
+    HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disables RTC counting.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function causes the timer to stop counting when in RTC mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Disable RTC counting.
+    //
+    HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the clock source for the specified timer module.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Source is the clock source for the timer module.
+//!
+//! This function sets the clock source for both timer A and timer B for the
+//! given timer module.  The possible clock sources are the system clock
+//! (\b TIMER_CLOCK_SYSTEM) or the precision internal oscillator
+//! (\b TIMER_CLOCK_PIOSC).
+//!
+//! \note The ability to specify the timer clock source varies with the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Source == TIMER_CLOCK_SYSTEM) ||
+           (ui32Source == TIMER_CLOCK_PIOSC));
+
+    //
+    // Set the timer clock source.
+    //
+    HWREG(ui32Base + TIMER_O_CC) = ui32Source;
+}
+
+//*****************************************************************************
+//
+//! Returns the clock source for the specified timer module.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function returns the clock source for the specified timer module.  The
+//! possible clock sources are the system clock (\b TIMER_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b TIMER_CLOCK_PIOSC).
+//!
+//! \note The ability to specify the timer clock source varies with the
+//! Tiva part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns either \b TIMER_CLOCK_SYSTEM or \b TIMER_CLOCK_PIOSC.
+//
+//*****************************************************************************
+uint32_t
+TimerClockSourceGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Return the timer clock source.
+    //
+    return(HWREG(ui32Base + TIMER_O_CC));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer prescale value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Value is the timer prescale value which must be between 0 and
+//! 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive)
+//! for 32/64-bit timers.
+//!
+//! This function configures the value of the input clock prescaler.  The
+//! prescaler is only operational when in half-width mode and is used to extend
+//! the range of the half-width timer modes.  The prescaler provides the least
+//! significant bits when counting down in periodic and one-shot modes; in all
+//! other modes, the prescaler provides the most significant bits.
+//!
+//! \note The availability of the prescaler varies with the Tiva part and
+//! timer mode in use.  Please consult the datasheet for the part you are using
+//! to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+    ASSERT(ui32Value < 256);
+
+    //
+    // Set the timer A prescaler if requested.
+    //
+    if(ui32Timer & TIMER_A)
+    {
+        HWREG(ui32Base + TIMER_O_TAPR) = ui32Value;
+    }
+
+    //
+    // Set the timer B prescaler if requested.
+    //
+    if(ui32Timer & TIMER_B)
+    {
+        HWREG(ui32Base + TIMER_O_TBPR) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer prescale value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler.  The prescaler
+//! is only operational when in half-width mode and is used to extend the range
+//! of the half-width timer modes.  The prescaler provides the least
+//! significant bits when counting down in periodic and one-shot modes; in all
+//! other modes, the prescaler provides the most significant bits.
+//!
+//! \note The availability of the prescaler varies with the Tiva part and
+//! timer mode in use.  Please consult the datasheet for the part you are using
+//! to determine whether this support is available.
+//!
+//! \return The value of the timer prescaler.
+//
+//*****************************************************************************
+uint32_t
+TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Return the appropriate prescale value.
+    //
+    return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) :
+           HWREG(ui32Base + TIMER_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer prescale match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Value is the timer prescale match value which must be between 0
+//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535
+//! (inclusive) for 32/64-bit timers.
+//!
+//! This function configures the value of the input clock prescaler match
+//! value.  When in a half-width mode that uses the counter match and the
+//! prescaler, the prescale match effectively extends the range of the match.
+//! The prescaler provides the least significant bits when counting down in
+//! periodic and one-shot modes; in all other modes, the prescaler provides the
+//! most significant bits.
+//!
+//! \note The availability of the prescaler match varies with the Tiva
+//! part and timer mode in use.  Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+                      uint32_t ui32Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+    ASSERT(ui32Value < 256);
+
+    //
+    // Set the timer A prescale match if requested.
+    //
+    if(ui32Timer & TIMER_A)
+    {
+        HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value;
+    }
+
+    //
+    // Set the timer B prescale match if requested.
+    //
+    if(ui32Timer & TIMER_B)
+    {
+        HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer prescale match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a half-width mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the match.  The prescaler
+//! provides the least significant bits when counting down in periodic and
+//! one-shot modes; in all other modes, the prescaler provides the most
+//! significant bits.
+//!
+//! \note The availability of the prescaler match varies with the Tiva
+//! part and timer mode in use.  Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return The value of the timer prescale match.
+//
+//*****************************************************************************
+uint32_t
+TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Return the appropriate prescale match value.
+    //
+    return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) :
+           HWREG(ui32Base + TIMER_O_TBPMR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.  Only \b TIMER_A should be used
+//! when the timer is configured for full-width operation.
+//! \param ui32Value is the load value.
+//!
+//! This function configures the timer load value; if the timer is running then
+//! the value is immediately loaded into the timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers.  Use
+//! TimerLoadSet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Set the timer A load value if requested.
+    //
+    if(ui32Timer & TIMER_A)
+    {
+        HWREG(ui32Base + TIMER_O_TAILR) = ui32Value;
+    }
+
+    //
+    // Set the timer B load value if requested.
+    //
+    if(ui32Timer & TIMER_B)
+    {
+        HWREG(ui32Base + TIMER_O_TBILR) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers.  Use
+//! TimerLoadGet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+uint32_t
+TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+    //
+    // Return the appropriate load value.
+    //
+    return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) :
+           HWREG(ui32Base + TIMER_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui64Value is the load value.
+//!
+//! This function configures the timer load value for a 64-bit timer; if the
+//! timer is running, then the value is immediately loaded into the timer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Set the timer load value.  The upper 32-bits must be written before the
+    // lower 32-bits in order to adhere to the hardware interlocks on the
+    // 64-bit value.
+    //
+    HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32;
+    HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff;
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified 64-bit timer.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+uint64_t
+TimerLoadGet64(uint32_t ui32Base)
+{
+    uint32_t ui32High1, ui32High2, ui32Low;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Read the 64-bit load value.  A read of the low 32-bits is performed
+    // between two reads of the upper 32-bits; if the upper 32-bit values match
+    // then the 64-bit value is consistent.  If they do not match, then the
+    // read is performed again until they do match (it should never execute the
+    // loop body more than twice).
+    //
+    do
+    {
+        ui32High1 = HWREG(ui32Base + TIMER_O_TBILR);
+        ui32Low = HWREG(ui32Base + TIMER_O_TAILR);
+        ui32High2 = HWREG(ui32Base + TIMER_O_TBILR);
+    }
+    while(ui32High1 != ui32High2);
+
+    //
+    // Return the load value.
+    //
+    return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
+}
+
+//*****************************************************************************
+//
+//! Gets the current timer value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers.  Use
+//! TimerValueGet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+uint32_t
+TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+    //
+    // Return the appropriate timer value.
+    //
+    return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) :
+           HWREG(ui32Base + TIMER_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! Gets the current 64-bit timer value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+uint64_t
+TimerValueGet64(uint32_t ui32Base)
+{
+    uint32_t ui32High1, ui32High2, ui32Low;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Read the 64-bit timer value.  A read of the low 32-bits is performed
+    // between two reads of the upper 32-bits; if the upper 32-bit values match
+    // then the 64-bit value is consistent.  If they do not match, then the
+    // read is performed again until they do match (it should never execute the
+    // loop body more than twice).
+    //
+    do
+    {
+        ui32High1 = HWREG(ui32Base + TIMER_O_TBR);
+        ui32Low = HWREG(ui32Base + TIMER_O_TAR);
+        ui32High2 = HWREG(ui32Base + TIMER_O_TBR);
+    }
+    while(ui32High1 != ui32High2);
+
+    //
+    // Return the timer value.
+    //
+    return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.  Only \b TIMER_A should be used
+//! when the timer is configured for full-width operation.
+//! \param ui32Value is the match value.
+//!
+//! This function configures the match value for a timer.  This value is used
+//! in capture count mode to determine when to interrupt the processor and in
+//! PWM mode to determine the duty cycle of the output signal.  On some
+//! Tiva devices, match interrupts can also be generated in periodic and
+//! one-shot modes.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers.  Use
+//! TimerMatchSet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+              uint32_t ui32Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Set the timer A match value if requested.
+    //
+    if(ui32Timer & TIMER_A)
+    {
+        HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value;
+    }
+
+    //
+    // Set the timer B match value if requested.
+    //
+    if(ui32Timer & TIMER_B)
+    {
+        HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers.  Use
+//! TimerMatchGet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+uint32_t
+TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+    //
+    // Return the appropriate match value.
+    //
+    return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) :
+           HWREG(ui32Base + TIMER_O_TBMATCHR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui64Value is the match value.
+//!
+//! This function configures the match value for a timer.  This value is used
+//! in capture count mode to determine when to interrupt the processor and in
+//! PWM mode to determine the duty cycle of the output signal.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Set the timer match value.  The upper 32-bits must be written before the
+    // lower 32-bits in order to adhere to the hardware interlocks on the
+    // 64-bit value.
+    //
+    HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32;
+    HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff;
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+uint64_t
+TimerMatchGet64(uint32_t ui32Base)
+{
+    uint32_t ui32High1, ui32High2, ui32Low;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Read the 64-bit match value.  A read of the low 32-bits is performed
+    // between two reads of the upper 32-bits; if the upper 32-bit values match
+    // then the 64-bit value is consistent.  If they do not match, then the
+    // read is performed again until they do match (it should never execute the
+    // loop body more than twice).
+    //
+    do
+    {
+        ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR);
+        ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR);
+        ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR);
+    }
+    while(ui32High1 != ui32High2);
+
+    //
+    // Return the match value.
+    //
+    return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer interrupt.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! This function registers the handler to be called when a timer interrupt
+//! occurs.  In addition, this function enables the global interrupt in the
+//! interrupt controller; specific timer interrupts must be enabled via
+//! TimerIntEnable().  It is the interrupt handler's responsibility to clear
+//! the interrupt source via TimerIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
+                 void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Get the interrupt number for this timer module.
+    //
+    ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the timer interrupt.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function unregisters the handler to be called when a timer interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+    ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+           (ui32Timer == TIMER_BOTH));
+
+    //
+    // Get the interrupt number for this timer module.
+    //
+    ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual timer interrupt sources.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated timer interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b TIMER_TIMB_DMA - Timer B uDMA complete
+//! - \b TIMER_TIMA_DMA - Timer A uDMA complete
+//! - \b TIMER_CAPB_EVENT  - Capture B event interrupt
+//! - \b TIMER_CAPB_MATCH  - Capture B match interrupt
+//! - \b TIMER_TIMB_TIMEOUT  - Timer B timeout interrupt
+//! - \b TIMER_RTC_MATCH  - RTC interrupt mask
+//! - \b TIMER_CAPA_EVENT  - Capture A event interrupt
+//! - \b TIMER_CAPA_MATCH  - Capture A match interrupt
+//! - \b TIMER_TIMA_TIMEOUT  - Timer A timeout interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual timer interrupt sources.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated timer interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to TimerIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the timer module.  Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! values described in TimerIntEnable().
+//
+//*****************************************************************************
+uint32_t
+TimerIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) :
+           HWREG(ui32Base + TIMER_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! Clears timer interrupt sources.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to TimerIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Synchronizes the counters in a set of timers.
+//!
+//! \param ui32Base is the base address of the timer module.  This parameter
+//! must be the base address of Timer0 (in other words, \b TIMER0_BASE).
+//! \param ui32Timers is the set of timers to synchronize.
+//!
+//! This function synchronizes the counters in a specified set of timers.
+//! When a timer is running in half-width mode, each half can be included or
+//! excluded in the synchronization event.  When a timer is running in
+//! full-width mode, only the A timer can be synchronized (specifying the B
+//! timer has no effect).
+//!
+//! The \e ui32Timers parameter is the logical OR of any of the following
+//! defines:
+//!
+//! - \b TIMER_0A_SYNC
+//! - \b TIMER_0B_SYNC
+//! - \b TIMER_1A_SYNC
+//! - \b TIMER_1B_SYNC
+//! - \b TIMER_2A_SYNC
+//! - \b TIMER_2B_SYNC
+//! - \b TIMER_3A_SYNC
+//! - \b TIMER_3B_SYNC
+//! - \b TIMER_4A_SYNC
+//! - \b TIMER_4B_SYNC
+//! - \b TIMER_5A_SYNC
+//! - \b TIMER_5B_SYNC
+//! - \b WTIMER_0A_SYNC
+//! - \b WTIMER_0B_SYNC
+//! - \b WTIMER_1A_SYNC
+//! - \b WTIMER_1B_SYNC
+//! - \b WTIMER_2A_SYNC
+//! - \b WTIMER_2B_SYNC
+//! - \b WTIMER_3A_SYNC
+//! - \b WTIMER_3B_SYNC
+//! - \b WTIMER_4A_SYNC
+//! - \b WTIMER_4B_SYNC
+//! - \b WTIMER_5A_SYNC
+//! - \b WTIMER_5B_SYNC
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == TIMER0_BASE);
+
+    //
+    // Synchronize the specified timers.
+    //
+    HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers;
+}
+
+//*****************************************************************************
+//
+//! Enables the events that can cause an ADC trigger event.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32ADCEvent is a bit mask of the events that can cause an ADC
+//!        trigger event.
+//!
+//! This function enables the timer events that can cause an ADC trigger event.
+//! The ADC trigger events are specified in the \e ui32ADCEvent parameter by
+//! passing in the logical OR of any of the following values:
+//!
+//! - \b TIMER_ADC_MODEMATCH_B - Enables the mode match ADC trigger for timer
+//!   B.
+//! - \b TIMER_ADC_CAPEVENT_B - Enables the capture event ADC trigger for
+//!   timer B.
+//! - \b TIMER_ADC_CAPMATCH_B - Enables the capture match ADC trigger for
+//!   timer B.
+//! - \b TIMER_ADC_TIMEOUT_B - Enables the timeout ADC trigger for timer B.
+//! - \b TIMER_ADC_MODEMATCH_A - Enables the mode match ADC trigger for timer
+//!   A.
+//! - \b TIMER_ADC_RTC_A - Enables the RTC ADC trigger for timer A.
+//! - \b TIMER_ADC_CAPEVENT_A - Enables the capture event ADC trigger for
+//!   timer A.
+//! - \b TIMER_ADC_CAPMATCH_A - Enables the capture match ADC trigger for
+//!   timer A.
+//! - \b TIMER_ADC_TIMEOUT_A - Enables the timeout ADC trigger for timer A.
+//!
+//! \note The ability to specify ADC event triggers varies with the Tiva
+//! part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Set the ADC triggers.
+    //
+    HWREG(ui32Base + TIMER_O_ADCEV) = ui32ADCEvent;
+}
+
+//*****************************************************************************
+//
+//! Returns the events that can cause an ADC trigger event.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function returns the timer events that can cause an ADC trigger event.
+//! The ADC trigger events are the logical OR of any of the following values:
+//!
+//! - \b TIMER_ADC_MODEMATCH_B - The mode match ADC trigger for timer B is
+//!   enabled.
+//! - \b TIMER_ADC_CAPEVENT_B - The capture event ADC trigger for timer B is
+//!   enabled.
+//! - \b TIMER_ADC_CAPMATCH_B - The capture match ADC trigger for timer B is
+//!   enabled.
+//! - \b TIMER_ADC_TIMEOUT_B - The timeout ADC trigger for timer B is enabled.
+//! - \b TIMER_ADC_MODEMATCH_A - The mode match ADC trigger for timer A is
+//!   enabled.
+//! - \b TIMER_ADC_RTC_A - The RTC ADC trigger for timer A is enabled.
+//! - \b TIMER_ADC_CAPEVENT_A - The capture event ADC trigger for timer A is
+//!   enabled.
+//! - \b TIMER_ADC_CAPMATCH_A - The capture match ADC trigger for timer A is
+//!   enabled.
+//! - \b TIMER_ADC_TIMEOUT_A - The timeout ADC trigger for timer A is enabled.
+//!
+//! \note The ability to specify ADC event triggers varies with the Tiva
+//! part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return The timer events that trigger the ADC.
+//
+//*****************************************************************************
+uint32_t
+TimerADCEventGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Return the current ADC triggers.
+    //
+    return(HWREG(ui32Base + TIMER_O_ADCEV));
+}
+
+//*****************************************************************************
+//
+//! Enables the events that can trigger a uDMA request.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32DMAEvent is a bit mask of the events that can trigger uDMA.
+//!
+//! This function enables the timer events that can trigger the start of a uDMA
+//! sequence.  The uDMA trigger events are specified in the \e ui32DMAEvent
+//! parameter by passing in the logical OR of the following values:
+//!
+//! - \b TIMER_DMA_MODEMATCH_B - The mode match uDMA trigger for timer B is
+//!   enabled.
+//! - \b TIMER_DMA_CAPEVENT_B - The capture event uDMA trigger for timer B is
+//!   enabled.
+//! - \b TIMER_DMA_CAPMATCH_B - The capture match uDMA trigger for timer B is
+//!   enabled.
+//! - \b TIMER_DMA_TIMEOUT_B - The timeout uDMA trigger for timer B is enabled.
+//! - \b TIMER_DMA_MODEMATCH_A - The mode match uDMA trigger for timer A is
+//!   enabled.
+//! - \b TIMER_DMA_RTC_A - The RTC uDMA trigger for timer A is enabled.
+//! - \b TIMER_DMA_CAPEVENT_A - The capture event uDMA trigger for timer A is
+//!   enabled.
+//! - \b TIMER_DMA_CAPMATCH_A - The capture match uDMA trigger for timer A is
+//!   enabled.
+//! - \b TIMER_DMA_TIMEOUT_A - The timeout uDMA trigger for timer A is enabled.
+//!
+//! \note The ability to specify uDMA event triggers varies with the Tiva
+//! part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Set the uDMA triggers.
+    //
+    HWREG(ui32Base + TIMER_O_DMAEV) = ui32DMAEvent;
+}
+
+//*****************************************************************************
+//
+//! Returns the events that can trigger a uDMA request.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function returns the timer events that can trigger the start of a uDMA
+//! sequence.  The uDMA trigger events are the logical OR of the following
+//! values:
+//!
+//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match uDMA trigger for timer
+//!   B.
+//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event uDMA trigger for
+//!   timer B.
+//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match uDMA trigger for
+//!   timer B.
+//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout uDMA trigger for timer B.
+//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match uDMA trigger for timer
+//!   A.
+//! - \b TIMER_DMA_RTC_A - Enables the RTC uDMA trigger for timer A.
+//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event uDMA trigger for
+//!   timer A.
+//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match uDMA trigger for
+//!   timer A.
+//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout uDMA trigger for timer A.
+//!
+//! \note The ability to specify uDMA event triggers varies with the Tiva
+//! part in use.  Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return The timer events that trigger the uDMA.
+//
+//*****************************************************************************
+uint32_t
+TimerDMAEventGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_TimerBaseValid(ui32Base));
+
+    //
+    // Return the current uDMA triggers.
+    //
+    return(HWREG(ui32Base + TIMER_O_DMAEV));
+}
+
+//*****************************************************************************
+//
+//! This function configures the update of timer load and match settings.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Config is a combination of the updates methods for the timers
+//! specified in the \e ui32Timer parameter.
+//!
+//! This function configures how the timer updates the timer load and match
+//! values for the timers.  The \e ui32Timer values can be \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH to apply the settings in \e ui32Config to
+//! either timer or both timers.  If the timer is not split then the \b TIMER_A
+//! should be used.  The \e ui32Config values affects when the TimerLoadSet()
+//! and TimerLoadSet64() values take effect.
+//!
+//! - \b TIMER_UP_LOAD_IMMEDIATE is the default mode that causes the
+//! TimerLoadSet() or TimerLoadSet64() to update the timer counter immediately.
+//! - \b TIMER_UP_LOAD_TIMEOUT causes the TimerLoadSet() or TimerLoadSet64() to
+//! update the timer when it counts down to zero.
+//!
+//! Similarly the \e ui32Config value affects when the TimerMatchSet() and
+//! TimerMatchSet64() values take effect.
+//!
+//! - \b TIMER_UP_MATCH_IMMEDIATE is the default mode that causes the
+//! TimerMatchSet() or TimerMatchSet64() to update the timer match value
+//! immediately.
+//! - \b TIMER_UP_MATCH_TIMEOUT causes the TimerMatchSet() or TimerMatchSet64()
+//! to update the timer match value when it counts down to zero.
+//!
+//! \note These settings have no effect if the timer is not in count down mode
+//! and are mostly useful when operating in PWM mode to allow for synchronous
+//! update of timer match and load values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Config)
+{
+    uint32_t ui32Value;
+
+    if((ui32Timer & TIMER_A) == TIMER_A)
+    {
+        ui32Value = HWREG(ui32Base + TIMER_O_TAMR) & ~(0x00000500);
+        ui32Value |= ui32Config;
+        HWREG(ui32Base + TIMER_O_TAMR) = ui32Value;
+    }
+
+    if((ui32Timer & TIMER_B) == TIMER_B)
+    {
+        ui32Value = HWREG(ui32Base + TIMER_O_TBMR) & ~(0x00000500);
+        ui32Value |= ui32Config;
+        HWREG(ui32Base + TIMER_O_TBMR) = ui32Value;
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/tiva_timer.h b/bsp/tm4c129x/libraries/driverlib/tiva_timer.h
new file mode 100644
index 0000000000..3b52a8eba4
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/tiva_timer.h
@@ -0,0 +1,301 @@
+//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_TIVA_TIMER_H__
+#define __DRIVERLIB_TIVA_TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ui32Config parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_ONE_SHOT       0x00000021  // Full-width one-shot timer
+#define TIMER_CFG_ONE_SHOT_UP    0x00000031  // Full-width one-shot up-count
+                                            // timer
+#define TIMER_CFG_PERIODIC       0x00000022  // Full-width periodic timer
+#define TIMER_CFG_PERIODIC_UP    0x00000032  // Full-width periodic up-count
+                                            // timer
+#define TIMER_CFG_RTC            0x01000000  // Full-width RTC timer
+#define TIMER_CFG_SPLIT_PAIR     0x04000000  // Two half-width timers
+#define TIMER_CFG_A_ONE_SHOT     0x00000021  // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP  0x00000031  // Timer A one-shot up-count timer
+#define TIMER_CFG_A_PERIODIC     0x00000022  // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP  0x00000032  // Timer A periodic up-count timer
+#define TIMER_CFG_A_CAP_COUNT    0x00000003  // Timer A event counter
+#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013  // Timer A event up-counter
+#define TIMER_CFG_A_CAP_TIME     0x00000007  // Timer A event timer
+#define TIMER_CFG_A_CAP_TIME_UP  0x00000017  // Timer A event up-count timer
+#define TIMER_CFG_A_PWM          0x0000000A  // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT     0x00002100  // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP  0x00003100  // Timer B one-shot up-count timer
+#define TIMER_CFG_B_PERIODIC     0x00002200  // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP  0x00003200  // Timer B periodic up-count timer
+#define TIMER_CFG_B_CAP_COUNT    0x00000300  // Timer B event counter
+#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300  // Timer B event up-counter
+#define TIMER_CFG_B_CAP_TIME     0x00000700  // Timer B event timer
+#define TIMER_CFG_B_CAP_TIME_UP  0x00001700  // Timer B event up-count timer
+#define TIMER_CFG_B_PWM          0x00000A00  // Timer B PWM output
+#define TIMER_CFG_A_ACT_TOINTD   0x00010000  // Timer A compare action disable
+                                             // time-out interrupt.
+#define TIMER_CFG_A_ACT_NONE     0x00000000  // Timer A compare action none.
+#define TIMER_CFG_A_ACT_TOGGLE   0x00020000  // Timer A compare action toggle.
+#define TIMER_CFG_A_ACT_CLRTO    0x00040000  // Timer A compare action CCP
+                                             // clear on time-out.
+#define TIMER_CFG_A_ACT_SETTO    0x00060000  // Timer A compare action CCP set
+                                             // on time-out.
+#define TIMER_CFG_A_ACT_SETTOGTO 0x00080000  // Timer A compare action set CCP
+                                             // toggle on time-out.
+#define TIMER_CFG_A_ACT_CLRTOGTO 0x000A0000  // Timer A compare action clear
+                                             // CCP toggle on time-out.
+#define TIMER_CFG_A_ACT_SETCLRTO 0x000C0000  // Timer A compare action set CCP
+                                             // clear on time-out.
+#define TIMER_CFG_A_ACT_CLRSETTO 0x000E0000  // Timer A compare action clear
+                                             // CCP set on time-out.
+#define TIMER_CFG_B_ACT_TOINTD   0x00100000  // Timer B compare action disable
+                                             // time-out interrupt.
+#define TIMER_CFG_B_ACT_NONE     0x00000000  // Timer A compare action none.
+#define TIMER_CFG_B_ACT_TOGGLE   0x00200000  // Timer A compare action toggle.
+#define TIMER_CFG_B_ACT_CLRTO    0x00400000  // Timer A compare action CCP
+                                             // clear on time-out.
+#define TIMER_CFG_B_ACT_SETTO    0x00600000  // Timer A compare action CCP set
+                                             // on time-out.
+#define TIMER_CFG_B_ACT_SETTOGTO 0x00800000  // Timer A compare action set CCP
+                                             // toggle on time-out.
+#define TIMER_CFG_B_ACT_CLRTOGTO 0x00A00000  // Timer A compare action clear
+                                             // CCP toggle on time-out.
+#define TIMER_CFG_B_ACT_SETCLRTO 0x00C00000  // Timer A compare action set CCP
+                                             // clear on time-out.
+#define TIMER_CFG_B_ACT_CLRSETTO 0x0000E000  // Timer A compare action clear
+                                             // CCP set on time-out.
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ui32IntFlags parameter, and returned from
+// TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_TIMB_DMA          0x00002000 // TimerB DMA Complete Interrupt.
+#define TIMER_TIMB_MATCH        0x00000800  // TimerB match interrupt
+#define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt
+#define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt
+#define TIMER_TIMA_DMA          0x00000020 // TimerA DMA Complete Interrupt.
+#define TIMER_TIMA_MATCH        0x00000010  // TimerA match interrupt
+#define TIMER_RTC_MATCH         0x00000008  // RTC interrupt mask
+#define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt
+#define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT      0x00000001  // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ui32Event parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE    0x00000000  // Count positive edges
+#define TIMER_EVENT_NEG_EDGE    0x00000404  // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES  0x00000C0C  // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ui32Timer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A                 0x000000ff  // Timer A
+#define TIMER_B                 0x0000ff00  // Timer B
+#define TIMER_BOTH              0x0000ffff  // Timer Both
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerSynchronize as the ui32Timers parameter.
+//
+//*****************************************************************************
+#define TIMER_0A_SYNC           0x00000001  // Synchronize Timer 0A
+#define TIMER_0B_SYNC           0x00000002  // Synchronize Timer 0B
+#define TIMER_1A_SYNC           0x00000004  // Synchronize Timer 1A
+#define TIMER_1B_SYNC           0x00000008  // Synchronize Timer 1B
+#define TIMER_2A_SYNC           0x00000010  // Synchronize Timer 2A
+#define TIMER_2B_SYNC           0x00000020  // Synchronize Timer 2B
+#define TIMER_3A_SYNC           0x00000040  // Synchronize Timer 3A
+#define TIMER_3B_SYNC           0x00000080  // Synchronize Timer 3B
+#define TIMER_4A_SYNC           0x00000100  // Synchronize Timer 4A
+#define TIMER_4B_SYNC           0x00000200  // Synchronize Timer 4B
+#define TIMER_5A_SYNC           0x00000400  // Synchronize Timer 5A
+#define TIMER_5B_SYNC           0x00000800  // Synchronize Timer 5B
+#define WTIMER_0A_SYNC          0x00001000  // Synchronize Wide Timer 0A
+#define WTIMER_0B_SYNC          0x00002000  // Synchronize Wide Timer 0B
+#define WTIMER_1A_SYNC          0x00004000  // Synchronize Wide Timer 1A
+#define WTIMER_1B_SYNC          0x00008000  // Synchronize Wide Timer 1B
+#define WTIMER_2A_SYNC          0x00010000  // Synchronize Wide Timer 2A
+#define WTIMER_2B_SYNC          0x00020000  // Synchronize Wide Timer 2B
+#define WTIMER_3A_SYNC          0x00040000  // Synchronize Wide Timer 3A
+#define WTIMER_3B_SYNC          0x00080000  // Synchronize Wide Timer 3B
+#define WTIMER_4A_SYNC          0x00100000  // Synchronize Wide Timer 4A
+#define WTIMER_4B_SYNC          0x00200000  // Synchronize Wide Timer 4B
+#define WTIMER_5A_SYNC          0x00400000  // Synchronize Wide Timer 5A
+#define WTIMER_5B_SYNC          0x00800000  // Synchronize Wide Timer 5B
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerClockSourceSet() or returned from
+// TimerClockSourceGet().
+//
+//*****************************************************************************
+#define TIMER_CLOCK_SYSTEM      0x00000000
+#define TIMER_CLOCK_PIOSC       0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerDMAEventSet() or returned from
+// TimerDMAEventGet().
+//
+//*****************************************************************************
+#define TIMER_DMA_MODEMATCH_B   0x00000800
+#define TIMER_DMA_CAPEVENT_B    0x00000400
+#define TIMER_DMA_CAPMATCH_B    0x00000200
+#define TIMER_DMA_TIMEOUT_B     0x00000100
+#define TIMER_DMA_MODEMATCH_A   0x00000010
+#define TIMER_DMA_RTC_A         0x00000008
+#define TIMER_DMA_CAPEVENT_A    0x00000004
+#define TIMER_DMA_CAPMATCH_A    0x00000002
+#define TIMER_DMA_TIMEOUT_A     0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerADCEventSet() or returned from
+// TimerADCEventGet().
+//
+//*****************************************************************************
+#define TIMER_ADC_MODEMATCH_B   0x00000800
+#define TIMER_ADC_CAPEVENT_B    0x00000400
+#define TIMER_ADC_CAPMATCH_B    0x00000200
+#define TIMER_ADC_TIMEOUT_B     0x00000100
+#define TIMER_ADC_MODEMATCH_A   0x00000010
+#define TIMER_ADC_RTC_A         0x00000008
+#define TIMER_ADC_CAPEVENT_A    0x00000004
+#define TIMER_ADC_CAPMATCH_A    0x00000002
+#define TIMER_ADC_TIMEOUT_A     0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerUpdateMode().
+//
+//*****************************************************************************
+#define TIMER_UP_LOAD_IMMEDIATE 0x00000000
+#define TIMER_UP_LOAD_TIMEOUT   0x00000100
+#define TIMER_UP_MATCH_IMMEDIATE                                              \
+                                0x00000000
+#define TIMER_UP_MATCH_TIMEOUT  0x00000400
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config);
+extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer,
+                              bool bInvert);
+extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+                                bool bEnable);
+extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer,
+                              uint32_t ui32Event);
+extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer,
+                              bool bStall);
+extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+                                      bool bWait);
+extern void TimerRTCEnable(uint32_t ui32Base);
+extern void TimerRTCDisable(uint32_t ui32Base);
+extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer,
+                             uint32_t ui32Value);
+extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+                                  uint32_t ui32Value);
+extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer,
+                         uint32_t ui32Value);
+extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value);
+extern uint64_t TimerLoadGet64(uint32_t ui32Base);
+extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern uint64_t TimerValueGet64(uint32_t ui32Base);
+extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+                          uint32_t ui32Value);
+extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value);
+extern uint64_t TimerMatchGet64(uint32_t ui32Base);
+extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
+                             void (*pfnHandler)(void));
+extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked);
+extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers);
+extern uint32_t TimerClockSourceGet(uint32_t ui32Base);
+extern void TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
+extern uint32_t TimerADCEventGet(uint32_t ui32Base);
+extern void TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent);
+extern uint32_t TimerDMAEventGet(uint32_t ui32Base);
+extern void TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent);
+extern void TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer,
+                            uint32_t ui32Config);
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_TIMER_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/uart.c b/bsp/tm4c129x/libraries/driverlib/uart.c
new file mode 100644
index 0000000000..9e31963cf6
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/uart.c
@@ -0,0 +1,1958 @@
+//*****************************************************************************
+//
+// uart.c - Driver for the UART.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_uart.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/uart.h"
+
+//*****************************************************************************
+//
+// The system clock divider defining the maximum baud rate supported by the
+// UART.
+//
+//*****************************************************************************
+#define UART_CLK_DIVIDER        8
+
+//*****************************************************************************
+//
+// A mapping of UART base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32UARTIntMap[][2] =
+{
+    { UART0_BASE, INT_UART0_TM4C123 },
+    { UART1_BASE, INT_UART1_TM4C123 },
+    { UART2_BASE, INT_UART2_TM4C123 },
+    { UART3_BASE, INT_UART3_TM4C123 },
+    { UART4_BASE, INT_UART4_TM4C123 },
+    { UART5_BASE, INT_UART5_TM4C123 },
+    { UART6_BASE, INT_UART6_TM4C123 },
+    { UART7_BASE, INT_UART7_TM4C123 },
+};
+static const uint_fast8_t g_ui8UARTIntMapRows =
+    sizeof(g_ppui32UARTIntMap) / sizeof(g_ppui32UARTIntMap[0]);
+static const uint32_t g_ppui32UARTIntMapSnowflake[][2] =
+{
+    { UART0_BASE, INT_UART0_TM4C129 },
+    { UART1_BASE, INT_UART1_TM4C129 },
+    { UART2_BASE, INT_UART2_TM4C129 },
+    { UART3_BASE, INT_UART3_TM4C129 },
+    { UART4_BASE, INT_UART4_TM4C129 },
+    { UART5_BASE, INT_UART5_TM4C129 },
+    { UART6_BASE, INT_UART6_TM4C129 },
+    { UART7_BASE, INT_UART7_TM4C129 },
+};
+static const uint_fast8_t g_ui8UARTIntMapRowsSnowflake =
+    sizeof(g_ppui32UARTIntMapSnowflake) /
+    sizeof(g_ppui32UARTIntMapSnowflake[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a UART base address.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_UARTBaseValid(uint32_t ui32Base)
+{
+    return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) ||
+           (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) ||
+           (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) ||
+           (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the UART interrupt number.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! Given a UART base address, this function returns the corresponding
+//! interrupt number.
+//!
+//! \return Returns a UART interrupt number, or 0 if \e ui32Base is invalid.
+//
+//*****************************************************************************
+static uint32_t
+_UARTIntNumberGet(uint32_t ui32Base)
+{
+    uint_fast8_t ui8Idx, ui8Rows;
+    const uint32_t (*ppui32UARTIntMap)[2];
+
+    //
+    // Default interrupt map.
+    //
+    ppui32UARTIntMap = g_ppui32UARTIntMap;
+    ui8Rows = g_ui8UARTIntMapRows;
+
+    if(CLASS_IS_TM4C129)
+    {
+        ppui32UARTIntMap = g_ppui32UARTIntMapSnowflake;
+        ui8Rows = g_ui8UARTIntMapRowsSnowflake;
+    }
+
+    //
+    // Loop through the table that maps UART base addresses to interrupt
+    // numbers.
+    //
+    for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
+    {
+        //
+        // See if this base address matches.
+        //
+        if(ppui32UARTIntMap[ui8Idx][0] == ui32Base)
+        {
+            //
+            // Return the corresponding interrupt number.
+            //
+            return(ppui32UARTIntMap[ui8Idx][1]);
+        }
+    }
+
+    //
+    // The base address could not be found, so return an error.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the type of parity.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Parity specifies the type of parity to use.
+//!
+//! This function configures the type of parity to use for transmitting and
+//! expect when receiving.  The \e ui32Parity parameter must be one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.  The last two
+//! parameters allow direct control of the parity bit; it is always either one
+//! or zero based on the mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+    ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) ||
+           (ui32Parity == UART_CONFIG_PAR_EVEN) ||
+           (ui32Parity == UART_CONFIG_PAR_ODD) ||
+           (ui32Parity == UART_CONFIG_PAR_ONE) ||
+           (ui32Parity == UART_CONFIG_PAR_ZERO));
+
+    //
+    // Set the parity mode.
+    //
+    HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) &
+                                      ~(UART_LCRH_SPS | UART_LCRH_EPS |
+                                        UART_LCRH_PEN)) | ui32Parity);
+}
+
+//*****************************************************************************
+//
+//! Gets the type of parity currently being used.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function gets the type of parity used for transmitting data and
+//! expected when receiving data.
+//!
+//! \return Returns the current parity settings, specified as one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
+//
+//*****************************************************************************
+uint32_t
+UARTParityModeGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return the current parity setting.
+    //
+    return(HWREG(ui32Base + UART_O_LCRH) &
+           (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which interrupts are generated.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one
+//! of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
+//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of
+//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
+//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function configures the FIFO level at which transmit and receive
+//! interrupts are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
+                 uint32_t ui32RxLevel)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+    ASSERT((ui32TxLevel == UART_FIFO_TX1_8) ||
+           (ui32TxLevel == UART_FIFO_TX2_8) ||
+           (ui32TxLevel == UART_FIFO_TX4_8) ||
+           (ui32TxLevel == UART_FIFO_TX6_8) ||
+           (ui32TxLevel == UART_FIFO_TX7_8));
+    ASSERT((ui32RxLevel == UART_FIFO_RX1_8) ||
+           (ui32RxLevel == UART_FIFO_RX2_8) ||
+           (ui32RxLevel == UART_FIFO_RX4_8) ||
+           (ui32RxLevel == UART_FIFO_RX6_8) ||
+           (ui32RxLevel == UART_FIFO_RX7_8));
+
+    //
+    // Set the FIFO interrupt levels.
+    //
+    HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which interrupts are generated.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param pui32RxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
+//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
+                 uint32_t *pui32RxLevel)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Read the FIFO level register.
+    //
+    ui32Temp = HWREG(ui32Base + UART_O_IFLS);
+
+    //
+    // Extract the transmit and receive FIFO levels.
+    //
+    *pui32TxLevel = ui32Temp & UART_IFLS_TX_M;
+    *pui32RxLevel = ui32Temp & UART_IFLS_RX_M;
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of a UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
+//! \param ui32Baud is the desired baud rate.
+//! \param ui32Config is the data format for the port (number of data bits,
+//! number of stop bits, and parity).
+//!
+//! This function configures the UART for operation in the specified data
+//! format.  The baud rate is provided in the \e ui32Baud parameter and the
+//! data format in the \e ui32Config parameter.
+//!
+//! The \e ui32Config parameter is the logical OR of three values: the number
+//! of data bits, the number of stop bits, and the parity.
+//! \b UART_CONFIG_WLEN_8, \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and
+//! \b UART_CONFIG_WLEN_5 select from eight to five data bits per byte
+//! (respectively).  \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select
+//! one or two stop bits (respectively).  \b UART_CONFIG_PAR_NONE,
+//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
+//! and \b UART_CONFIG_PAR_ZERO select the parity mode (no parity bit, even
+//! parity bit, odd parity bit, parity bit always one, and parity bit always
+//! zero, respectively).
+//!
+//! The peripheral clock is the same as the processor clock.  The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
+//!
+//! For Tiva parts that have the ability to specify the UART baud clock
+//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
+//! PIOSC.  In this case, the peripheral clock should be specified as
+//! 16,000,000 (the nominal rate of PIOSC).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+                    uint32_t ui32Baud, uint32_t ui32Config)
+{
+    uint32_t ui32Div;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+    ASSERT(ui32Baud != 0);
+    ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER));
+
+    //
+    // Stop the UART.
+    //
+    UARTDisable(ui32Base);
+
+    //
+    // Is the required baud rate greater than the maximum rate supported
+    // without the use of high speed mode?
+    //
+    if((ui32Baud * 16) > ui32UARTClk)
+    {
+        //
+        // Enable high speed mode.
+        //
+        HWREG(ui32Base + UART_O_CTL) |= UART_CTL_HSE;
+
+        //
+        // Half the supplied baud rate to compensate for enabling high speed
+        // mode.  This allows the following code to be common to both cases.
+        //
+        ui32Baud /= 2;
+    }
+    else
+    {
+        //
+        // Disable high speed mode.
+        //
+        HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_HSE);
+    }
+
+    //
+    // Compute the fractional baud rate divider.
+    //
+    ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2;
+
+    //
+    // Set the baud rate.
+    //
+    HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64;
+    HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64;
+
+    //
+    // Set parity, data length, and number of stop bits.
+    //
+    HWREG(ui32Base + UART_O_LCRH) = ui32Config;
+
+    //
+    // Clear the flags register.
+    //
+    HWREG(ui32Base + UART_O_FR) = 0;
+
+    //
+    // Start the UART.
+    //
+    UARTEnable(ui32Base);
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of a UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
+//! \param pui32Baud is a pointer to storage for the baud rate.
+//! \param pui32Config is a pointer to storage for the data format.
+//!
+//! This function determines the baud rate and data format for the UART, given
+//! an explicitly provided peripheral clock (hence the ExpClk suffix).  The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an ``official'' baud rate.  The data format returned in
+//! \e pui32Config is enumerated the same as the \e ui32Config parameter of
+//! UARTConfigSetExpClk().
+//!
+//! The peripheral clock is the same as the processor clock.  The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
+//!
+//! For Tiva parts that have the ability to specify the UART baud clock
+//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
+//! PIOSC.  In this case, the peripheral clock should be specified as
+//! 16,000,000 (the nominal rate of PIOSC).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+                    uint32_t *pui32Baud, uint32_t *pui32Config)
+{
+    uint32_t ui32Int, ui32Frac;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Compute the baud rate.
+    //
+    ui32Int = HWREG(ui32Base + UART_O_IBRD);
+    ui32Frac = HWREG(ui32Base + UART_O_FBRD);
+    *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac);
+
+    //
+    // See if high speed mode enabled.
+    //
+    if(HWREG(ui32Base + UART_O_CTL) & UART_CTL_HSE)
+    {
+        //
+        // High speed mode is enabled so the actual baud rate is actually
+        // double what was just calculated.
+        //
+        *pui32Baud *= 2;
+    }
+
+    //
+    // Get the parity, data length, and number of stop bits.
+    //
+    *pui32Config = (HWREG(ui32Base + UART_O_LCRH) &
+                    (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+                     UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Enables transmitting and receiving.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function enables the UART and its transmit and receive FIFOs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Enable the FIFO.
+    //
+    HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN;
+
+    //
+    // Enable RX, TX, and the UART.
+    //
+    HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+                                     UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Disables transmitting and receiving.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables the UART, waits for the end of transmission of the
+//! current character, and flushes the transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Wait for end of TX.
+    //
+    while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY)
+    {
+    }
+
+    //
+    // Disable the FIFO.
+    //
+    HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+    //
+    // Disable the UART.
+    //
+    HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+                                      UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and receive FIFOs.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Enable the FIFO.
+    //
+    HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and receive FIFOs.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFODisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Disable the FIFO.
+    //
+    HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! Enables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bLowPower indicates if SIR Low Power Mode is to be used.
+//!
+//! This function enables SIR (IrDA) mode on the UART.  If the \e bLowPower
+//! flag is set, then SIR low power mode will be selected as well.  This
+//! function only has an effect if the UART has not been enabled by a call to
+//! UARTEnable().  The call UARTEnableSIR() must be made before a call to
+//! UARTConfigSetExpClk() because the UARTConfigSetExpClk() function calls the
+//! UARTEnable() function.  Another option is to call UARTDisable() followed by
+//! UARTEnableSIR() and then enable the UART by calling UARTEnable().
+//!
+//! \note The availability of SIR (IrDA) operation varies with the Tiva
+//! part in use.  Please consult the datasheet for the part you are using to
+//! determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnableSIR(uint32_t ui32Base, bool bLowPower)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Enable SIR and SIRLP (if appropriate).
+    //
+    if(bLowPower)
+    {
+        HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
+    }
+    else
+    {
+        HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN);
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables SIR(IrDA) mode on the UART.  This function only has
+//! an effect if the UART has not been enabled by a call to UARTEnable().  The
+//! call UARTEnableSIR() must be made before a call to UARTConfigSetExpClk()
+//! because the UARTConfigSetExpClk() function calls the UARTEnable() function.
+//! Another option is to call UARTDisable() followed by UARTEnableSIR() and
+//! then enable the UART by calling UARTEnable().
+//!
+//! \note The availability of SIR (IrDA) operation varies with the Tiva
+//! part in use.  Please consult the datasheet for the part you are using to
+//! determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisableSIR(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Disable SIR and SIRLP (if appropriate).
+    //
+    HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
+}
+
+//*****************************************************************************
+//
+//! Enables ISO7816 smart card mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function enables the SMART control bit for the ISO7816 smart card mode
+//! on the UART.  This call also sets 8-bit word length and even parity as
+//! required by ISO7816.
+//!
+//! \note The availability of ISO7816 smart card mode varies with the Tiva
+//! part and UART in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardEnable(uint32_t ui32Base)
+{
+    uint32_t ui32Val;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Set 8-bit word length, even parity, 2 stop bits (note that although the
+    // STP2 bit is ignored when in smartcard mode, this code lets the caller
+    // read back the actual setting in use).
+    //
+    ui32Val = HWREG(ui32Base + UART_O_LCRH);
+    ui32Val &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
+                 UART_LCRH_WLEN_M);
+    ui32Val |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS |
+               UART_LCRH_STP2;
+    HWREG(ui32Base + UART_O_LCRH) = ui32Val;
+
+    //
+    // Enable SMART mode.
+    //
+    HWREG(ui32Base + UART_O_CTL) |= UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Disables ISO7816 smart card mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function clears the SMART (ISO7816 smart card) bit in the UART
+//! control register.
+//!
+//! \note The availability of ISO7816 smart card mode varies with the Tiva
+//! part and UART in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Disable the SMART bit.
+    //
+    HWREG(ui32Base + UART_O_CTL) &= ~UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Sets the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Control is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! This function configures the states of the DTR or RTS modem handshake
+//! outputs from the UART.
+//!
+//! The \e ui32Control parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The modem control DTR signal
+//! - \b UART_OUTPUT_RTS - The modem control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use.  Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == UART1_BASE);
+    ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+    //
+    // Set the appropriate modem control output bits.
+    //
+    ui32Temp = HWREG(ui32Base + UART_O_CTL);
+    ui32Temp |= (ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+    HWREG(ui32Base + UART_O_CTL) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+//! Clears the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Control is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! This function clears the states of the DTR or RTS modem handshake outputs
+//! from the UART.
+//!
+//! The \e ui32Control parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The modem control DTR signal
+//! - \b UART_OUTPUT_RTS - The modem control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use.  Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control)
+{
+    uint32_t ui32Temp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == UART1_BASE);
+    ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+    //
+    // Set the appropriate modem control output bits.
+    //
+    ui32Temp = HWREG(ui32Base + UART_O_CTL);
+    ui32Temp &= ~(ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+    HWREG(ui32Base + UART_O_CTL) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the DTR and RTS modem control signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current states of each of the two UART modem
+//! control signals, DTR and RTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use.  Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals.  This value is
+//! a logical OR combination of values \b UART_OUTPUT_RTS and
+//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
+//! associated signal is asserted.
+//
+//*****************************************************************************
+uint32_t
+UARTModemControlGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == UART1_BASE);
+
+    return(HWREG(ui32Base + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the RI, DCD, DSR and CTS modem status signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current states of each of the four UART modem
+//! status signals, RI, DCD, DSR and CTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use.  Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals.  This value
+//! is a logical OR combination of values \b UART_INPUT_RI,
+//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
+//! presence of each flag indicates that the associated signal is asserted.
+//
+//*****************************************************************************
+uint32_t
+UARTModemStatusGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == UART1_BASE);
+
+    return(HWREG(ui32Base + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
+                                          UART_INPUT_CTS | UART_INPUT_DSR));
+}
+
+//*****************************************************************************
+//
+//! Sets the UART hardware flow control mode to be used.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Mode indicates the flow control modes to be used.  This
+//! parameter is a logical OR combination of values \b UART_FLOWCONTROL_TX and
+//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
+//!
+//! This function configures the required hardware flow control modes.  If
+//! \e ui32Mode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted
+//! if the incoming CTS signal is asserted.  If \e ui32Mode contains flag
+//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
+//! asserted only when there is space available in the receive FIFO.  If no
+//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
+//! passed.
+//!
+//! \note The availability of hardware flow control varies with the Tiva
+//! part and UART in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+    ASSERT((ui32Mode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
+
+    //
+    // Set the flow control mode as requested.
+    //
+    HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) &
+                                     ~(UART_FLOWCONTROL_TX |
+                                       UART_FLOWCONTROL_RX)) | ui32Mode);
+}
+
+//*****************************************************************************
+//
+//! Returns the UART hardware flow control mode currently in use.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current hardware flow control mode.
+//!
+//! \note The availability of hardware flow control varies with the Tiva
+//! part and UART in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns the current flow control mode in use.  This value is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
+//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
+//! flow control is in use.  If hardware flow control is disabled,
+//! \b UART_FLOWCONTROL_NONE is returned.
+//
+//*****************************************************************************
+uint32_t
+UARTFlowControlGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    return(HWREG(ui32Base + UART_O_CTL) & (UART_FLOWCONTROL_TX |
+                                           UART_FLOWCONTROL_RX));
+}
+
+//*****************************************************************************
+//
+//! Sets the operating mode for the UART transmit interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Mode is the operating mode for the transmit interrupt.  It may
+//! be \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is
+//! idle or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit
+//! FIFO level.
+//!
+//! This function allows the mode of the UART transmit interrupt to be set.  By
+//! default, the transmit interrupt is asserted when the FIFO level falls past
+//! a threshold set via a call to UARTFIFOLevelSet().  Alternatively, if this
+//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the
+//! transmit interrupt is asserted once the transmitter is completely idle -
+//! the transmit FIFO is empty and all bits, including any stop bits, have
+//! cleared the transmitter.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Tiva part in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+    ASSERT((ui32Mode == UART_TXINT_MODE_EOT) ||
+           (ui32Mode == UART_TXINT_MODE_FIFO));
+
+    //
+    // Set or clear the EOT bit of the UART control register as appropriate.
+    //
+    HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) &
+                                     ~(UART_TXINT_MODE_EOT |
+                                       UART_TXINT_MODE_FIFO)) | ui32Mode);
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode for the UART transmit interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current operating mode for the UART transmit
+//! interrupt.  The return value is \b UART_TXINT_MODE_EOT if the transmit
+//! interrupt is currently configured to be asserted once the transmitter is
+//! completely idle - the transmit FIFO is empty and all bits, including any
+//! stop bits, have cleared the transmitter.  The return value is
+//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based
+//! on the level of the transmit FIFO.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Tiva part in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
+//
+//*****************************************************************************
+uint32_t
+UARTTxIntModeGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return the current transmit interrupt mode.
+    //
+    return(HWREG(ui32Base + UART_O_CTL) & (UART_TXINT_MODE_EOT |
+                                           UART_TXINT_MODE_FIFO));
+}
+
+//*****************************************************************************
+//
+//! Determines if there are any characters in the receive FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \return Returns \b true if there is data in the receive FIFO or \b false
+//! if there is no data in the receive FIFO.
+//
+//*****************************************************************************
+bool
+UARTCharsAvail(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return the availability of characters.
+    //
+    return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Determines if there is any space in the transmit FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \return Returns \b true if there is space available in the transmit FIFO
+//! or \b false if there is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+bool
+UARTSpaceAvail(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return the availability of space.
+    //
+    return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Receives a character from the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e int32_t.  A \b -1 is returned if there are no characters present in the
+//! receive FIFO.  The UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//
+//*****************************************************************************
+int32_t
+UARTCharGetNonBlocking(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // See if there are any characters in the receive FIFO.
+    //
+    if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE))
+    {
+        //
+        // Read and return the next character.
+        //
+        return(HWREG(ui32Base + UART_O_DR));
+    }
+    else
+    {
+        //
+        // There are no characters, so return a failure.
+        //
+        return(-1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Waits for a character from the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port.  If there are no characters available, this function waits until a
+//! character is received before returning.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e int32_t.
+//
+//*****************************************************************************
+int32_t
+UARTCharGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Wait until a char is available.
+    //
+    while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)
+    {
+    }
+
+    //
+    // Now get the char.
+    //
+    return(HWREG(ui32Base + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+//! Sends a character to the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! This function writes the character \e ucData to the transmit FIFO for the
+//! specified port.  This function does not block, so if there is no space
+//! available, then a \b false is returned and the application must retry the
+//! function later.
+//!
+//! \return Returns \b true if the character was successfully placed in the
+//! transmit FIFO or \b false if there was no space available in the transmit
+//! FIFO.
+//
+//*****************************************************************************
+bool
+UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // See if there is space in the transmit FIFO.
+    //
+    if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF))
+    {
+        //
+        // Write this character to the transmit FIFO.
+        //
+        HWREG(ui32Base + UART_O_DR) = ucData;
+
+        //
+        // Success.
+        //
+        return(true);
+    }
+    else
+    {
+        //
+        // There is no space in the transmit FIFO, so return a failure.
+        //
+        return(false);
+    }
+}
+
+//*****************************************************************************
+//
+//! Waits to send a character from the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! This function sends the character \e ucData to the transmit FIFO for the
+//! specified port.  If there is no space available in the transmit FIFO, this
+//! function waits until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTCharPut(uint32_t ui32Base, unsigned char ucData)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Wait until space is available.
+    //
+    while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)
+    {
+    }
+
+    //
+    // Send the char.
+    //
+    HWREG(ui32Base + UART_O_DR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Causes a BREAK to be sent.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//!
+//! Calling this function with \e bBreakState set to \b true asserts a break
+//! condition on the UART.  Calling this function with \e bBreakState set to
+//! \b false removes the break condition.  For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTBreakCtl(uint32_t ui32Base, bool bBreakState)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Set the break condition as requested.
+    //
+    HWREG(ui32Base + UART_O_LCRH) =
+        (bBreakState ?
+         (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) :
+         (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! Determines whether the UART transmitter is busy or not.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function allows the caller to determine whether all transmitted bytes
+//! have cleared the transmitter hardware.  If \b false is returned, the
+//! transmit FIFO is empty and all bits of the last transmitted character,
+//! including all stop bits, have left the hardware shift register.
+//!
+//! \return Returns \b true if the UART is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+bool
+UARTBusy(uint32_t ui32Base)
+{
+    //
+    // Check the argument.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Determine if the UART is busy.
+    //
+    return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a UART interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler.  This
+//! function enables the global interrupt in the interrupt controller; specific
+//! UART interrupts must be enabled via UARTIntEnable().  It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Determine the interrupt number based on the UART port.
+    //
+    ui32Int = _UARTIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the UART interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a UART interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function does the actual unregistering of the interrupt handler.  It
+//! clears the handler to be called when a UART interrupt occurs.  This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Determine the interrupt number based on the UART port.
+    //
+    ui32Int = _UARTIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated UART interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b UART_INT_9BIT - 9-bit Address Match interrupt
+//! - \b UART_INT_OE - Overrun Error interrupt
+//! - \b UART_INT_BE - Break Error interrupt
+//! - \b UART_INT_PE - Parity Error interrupt
+//! - \b UART_INT_FE - Framing Error interrupt
+//! - \b UART_INT_RT - Receive Timeout interrupt
+//! - \b UART_INT_TX - Transmit interrupt
+//! - \b UART_INT_RX - Receive interrupt
+//! - \b UART_INT_DSR - DSR interrupt
+//! - \b UART_INT_DCD - DCD interrupt
+//! - \b UART_INT_CTS - CTS interrupt
+//! - \b UART_INT_RI - RI interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Enable the specified interrupts.
+    //
+    HWREG(ui32Base + UART_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated UART interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to UARTIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Disable the specified interrupts.
+    //
+    HWREG(ui32Base + UART_O_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the specified UART.  Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in UARTIntEnable().
+//
+//*****************************************************************************
+uint32_t
+UARTIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + UART_O_MIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + UART_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to UARTIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Clear the requested interrupt sources.
+    //
+    HWREG(ui32Base + UART_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enable UART uDMA operation.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32DMAFlags is a bit mask of the uDMA features to enable.
+//!
+//! The specified UART uDMA features are enabled.  The UART can be
+//! configured to use uDMA for transmit or receive and to disable
+//! receive if an error occurs.  The \e ui32DMAFlags parameter is the
+//! logical OR of any of the following values:
+//!
+//! - \b UART_DMA_RX - enable uDMA for receive
+//! - \b UART_DMA_TX - enable uDMA for transmit
+//! - \b UART_DMA_ERR_RXSTOP - disable uDMA receive on UART error
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Set the requested bits in the UART uDMA control register.
+    //
+    HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable UART uDMA operation.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32DMAFlags is a bit mask of the uDMA features to disable.
+//!
+//! This function is used to disable UART uDMA features that were enabled
+//! by UARTDMAEnable().  The specified UART uDMA features are disabled.  The
+//! \e ui32DMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - \b UART_DMA_RX - disable uDMA for receive
+//! - \b UART_DMA_TX - disable uDMA for transmit
+//! - \b UART_DMA_ERR_RXSTOP - do not disable uDMA receive on UART error
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Clear the requested bits in the UART uDMA control register.
+    //
+    HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets current receiver errors.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources.  The returned errors are equivalent to the four error bits
+//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately when the
+//! overrun occurs rather than when a character is next read.
+//!
+//! \return Returns a logical OR combination of the receiver error flags,
+//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
+//! and \b UART_RXERROR_OVERRUN.
+//
+//*****************************************************************************
+uint32_t
+UARTRxErrorGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return the current value of the receive status register.
+    //
+    return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Clears all reported receiver errors.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! UARTRxErrorGet().  If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTRxErrorClear(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Any write to the Error Clear Register clears all bits which are
+    // currently set.
+    //
+    HWREG(ui32Base + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Sets the baud clock source for the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Source is the baud clock source for the UART.
+//!
+//! This function allows the baud clock source for the UART to be selected.
+//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
+//!
+//! Changing the baud clock source changes the baud rate generated by the
+//! UART.  Therefore, the baud rate should be reconfigured after any change to
+//! the baud clock source.
+//!
+//! \note The ability to specify the UART baud clock source varies with the
+//! Tiva part in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+    ASSERT((ui32Source == UART_CLOCK_SYSTEM) ||
+           (ui32Source == UART_CLOCK_PIOSC));
+
+    //
+    // Set the UART clock source.
+    //
+    HWREG(ui32Base + UART_O_CC) = ui32Source;
+}
+
+//*****************************************************************************
+//
+//! Gets the baud clock source for the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the baud clock source for the specified UART.  The
+//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
+//!
+//! \note The ability to specify the UART baud clock source varies with the
+//! Tiva part in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+UARTClockSourceGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Return the UART clock source.
+    //
+    return(HWREG(ui32Base + UART_O_CC));
+}
+
+//*****************************************************************************
+//
+//! Enables 9-bit mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function enables the 9-bit operational mode of the UART.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Enable 9-bit mode.
+    //
+    HWREG(ui32Base + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN;
+}
+
+//*****************************************************************************
+//
+//! Disables 9-bit mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables the 9-bit operational mode of the UART.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Disable 9-bit mode.
+    //
+    HWREG(ui32Base + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN;
+}
+
+//*****************************************************************************
+//
+//! Sets the device address(es) for 9-bit mode.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui8Addr is the device address.
+//! \param ui8Mask is the device address mask.
+//!
+//! This function configures the device address or range of device addresses
+//! that respond to requests on the 9-bit UART port.  The received address is
+//! masked with the mask and then compared against the given address, allowing
+//! either a single address (if \b ui8Mask is 0xff) or a set of addresses to be
+//! matched.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr,
+                uint8_t ui8Mask)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Set the address and mask.
+    //
+    HWREG(ui32Base + UART_O_9BITADDR) = ui8Addr << UART_9BITADDR_ADDR_S;
+    HWREG(ui32Base + UART_O_9BITAMASK) = ui8Mask << UART_9BITAMASK_MASK_S;
+}
+
+//*****************************************************************************
+//
+//! Sends an address character from the specified port when operating in 9-bit
+//! mode.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui8Addr is the address to be transmitted.
+//!
+//! This function waits until all data has been sent from the specified port
+//! and then sends the given address as an address byte.  It then waits until
+//! the address byte has been transmitted before returning.
+//!
+//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(),
+//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive
+//! data characters in 9-bit mode.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr)
+{
+    uint32_t ui32LCRH;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Wait until the FIFO is empty and the UART is not busy.
+    //
+    while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) !=
+          UART_FR_TXFE)
+    {
+    }
+
+    //
+    // Force the address/data bit to 1 to indicate this is an address byte.
+    //
+    ui32LCRH = HWREG(ui32Base + UART_O_LCRH);
+    HWREG(ui32Base + UART_O_LCRH) = ((ui32LCRH & ~UART_LCRH_EPS) |
+                                     UART_LCRH_SPS | UART_LCRH_PEN);
+
+    //
+    // Send the address.
+    //
+    HWREG(ui32Base + UART_O_DR) = ui8Addr;
+
+    //
+    // Wait until the address has been sent.
+    //
+    while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) !=
+          UART_FR_TXFE)
+    {
+    }
+
+    //
+    // Restore the address/data setting.
+    //
+    HWREG(ui32Base + UART_O_LCRH) = ui32LCRH;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/uart.h b/bsp/tm4c129x/libraries/driverlib/uart.h
new file mode 100644
index 0000000000..d898b6c4d8
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/uart.h
@@ -0,0 +1,255 @@
+//*****************************************************************************
+//
+// uart.h - Defines and Macros for the UART.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_UART_H__
+#define __DRIVERLIB_UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ui32IntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_DMATX          0x20000     // DMA TX interrupt
+#define UART_INT_DMARX          0x10000     // DMA RX interrupt
+#define UART_INT_9BIT           0x1000      // 9-bit address match interrupt
+#define UART_INT_OE             0x400       // Overrun Error Interrupt Mask
+#define UART_INT_BE             0x200       // Break Error Interrupt Mask
+#define UART_INT_PE             0x100       // Parity Error Interrupt Mask
+#define UART_INT_FE             0x080       // Framing Error Interrupt Mask
+#define UART_INT_RT             0x040       // Receive Timeout Interrupt Mask
+#define UART_INT_TX             0x020       // Transmit Interrupt Mask
+#define UART_INT_RX             0x010       // Receive Interrupt Mask
+#define UART_INT_DSR            0x008       // DSR Modem Interrupt Mask
+#define UART_INT_DCD            0x004       // DCD Modem Interrupt Mask
+#define UART_INT_CTS            0x002       // CTS Modem Interrupt Mask
+#define UART_INT_RI             0x001       // RI Modem Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter
+// and returned by UARTConfigGetExpClk in the pui32Config parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ui32Parity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK   0x00000060  // Mask for extracting word length
+#define UART_CONFIG_WLEN_8      0x00000060  // 8 bit data
+#define UART_CONFIG_WLEN_7      0x00000040  // 7 bit data
+#define UART_CONFIG_WLEN_6      0x00000020  // 6 bit data
+#define UART_CONFIG_WLEN_5      0x00000000  // 5 bit data
+#define UART_CONFIG_STOP_MASK   0x00000008  // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE    0x00000000  // One stop bit
+#define UART_CONFIG_STOP_TWO    0x00000008  // Two stop bits
+#define UART_CONFIG_PAR_MASK    0x00000086  // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE    0x00000000  // No parity
+#define UART_CONFIG_PAR_EVEN    0x00000006  // Even parity
+#define UART_CONFIG_PAR_ODD     0x00000002  // Odd parity
+#define UART_CONFIG_PAR_ONE     0x00000082  // Parity bit is one
+#define UART_CONFIG_PAR_ZERO    0x00000086  // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter
+// and returned by UARTFIFOLevelGet in the pui32TxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8         0x00000000  // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8         0x00000001  // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8         0x00000002  // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8         0x00000003  // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8         0x00000004  // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter
+// and returned by UARTFIFOLevelGet in the pui32RxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8         0x00000000  // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8         0x00000008  // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8         0x00000010  // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8         0x00000018  // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8         0x00000020  // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP     0x00000004  // Stop DMA receive if UART error
+#define UART_DMA_TX             0x00000002  // Enable DMA for transmit
+#define UART_DMA_RX             0x00000001  // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN    0x00000008
+#define UART_RXERROR_BREAK      0x00000004
+#define UART_RXERROR_PARITY     0x00000002
+#define UART_RXERROR_FRAMING    0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTHandshakeOutputsSet() or returned from
+// UARTHandshakeOutputGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS         0x00000800
+#define UART_OUTPUT_DTR         0x00000400
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTHandshakeInputsGet().
+//
+//*****************************************************************************
+#define UART_INPUT_RI           0x00000100
+#define UART_INPUT_DCD          0x00000004
+#define UART_INPUT_DSR          0x00000002
+#define UART_INPUT_CTS          0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX     0x00008000
+#define UART_FLOWCONTROL_RX     0x00004000
+#define UART_FLOWCONTROL_NONE   0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO    0x00000000
+#define UART_TXINT_MODE_EOT     0x00000010
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTClockSourceSet() or returned from
+// UARTClockSourceGet().
+//
+//*****************************************************************************
+#define UART_CLOCK_SYSTEM       0x00000000
+#define UART_CLOCK_PIOSC        0x00000005
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity);
+extern uint32_t UARTParityModeGet(uint32_t ui32Base);
+extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
+                             uint32_t ui32RxLevel);
+extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
+                             uint32_t *pui32RxLevel);
+extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+                                uint32_t ui32Baud, uint32_t ui32Config);
+extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+                                uint32_t *pui32Baud, uint32_t *pui32Config);
+extern void UARTEnable(uint32_t ui32Base);
+extern void UARTDisable(uint32_t ui32Base);
+extern void UARTFIFOEnable(uint32_t ui32Base);
+extern void UARTFIFODisable(uint32_t ui32Base);
+extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower);
+extern void UARTDisableSIR(uint32_t ui32Base);
+extern bool UARTCharsAvail(uint32_t ui32Base);
+extern bool UARTSpaceAvail(uint32_t ui32Base);
+extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base);
+extern int32_t UARTCharGet(uint32_t ui32Base);
+extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData);
+extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData);
+extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState);
+extern bool UARTBusy(uint32_t ui32Base);
+extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void UARTIntUnregister(uint32_t ui32Base);
+extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked);
+extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern uint32_t UARTRxErrorGet(uint32_t ui32Base);
+extern void UARTRxErrorClear(uint32_t ui32Base);
+extern void UARTSmartCardEnable(uint32_t ui32Base);
+extern void UARTSmartCardDisable(uint32_t ui32Base);
+extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control);
+extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control);
+extern uint32_t UARTModemControlGet(uint32_t ui32Base);
+extern uint32_t UARTModemStatusGet(uint32_t ui32Base);
+extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern uint32_t UARTFlowControlGet(uint32_t ui32Base);
+extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern uint32_t UARTTxIntModeGet(uint32_t ui32Base);
+extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
+extern uint32_t UARTClockSourceGet(uint32_t ui32Base);
+extern void UART9BitEnable(uint32_t ui32Base);
+extern void UART9BitDisable(uint32_t ui32Base);
+extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr,
+                            uint8_t ui8Mask);
+extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_UART_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/udma.c b/bsp/tm4c129x/libraries/driverlib/udma.c
new file mode 100644
index 0000000000..c019a7dba5
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/udma.c
@@ -0,0 +1,1384 @@
+//*****************************************************************************
+//
+// udma.c - Driver for the micro-DMA controller.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_udma.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+
+//*****************************************************************************
+//
+//! Enables the uDMA controller for use.
+//!
+//! This function enables the uDMA controller.  The uDMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAEnable(void)
+{
+    //
+    // Set the master enable bit in the config register.
+    //
+    HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA controller for use.
+//!
+//! This function disables the uDMA controller.  Once disabled, the uDMA
+//! controller cannot operate until re-enabled with uDMAEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMADisable(void)
+{
+    //
+    // Clear the master enable bit in the config register.
+    //
+    HWREG(UDMA_CFG) = 0;
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA error status.
+//!
+//! This function returns the uDMA error status.  It should be called from
+//! within the uDMA error interrupt handler to determine if a uDMA error
+//! occurred.
+//!
+//! \return Returns non-zero if a uDMA error is pending.
+//
+//*****************************************************************************
+uint32_t
+uDMAErrorStatusGet(void)
+{
+    //
+    // Return the uDMA error status.
+    //
+    return(HWREG(UDMA_ERRCLR));
+}
+
+//*****************************************************************************
+//
+//! Clears the uDMA error interrupt.
+//!
+//! This function clears a pending uDMA error interrupt.  This function should
+//! be called from within the uDMA error interrupt handler to clear the
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAErrorStatusClear(void)
+{
+    //
+    // Clear the uDMA error interrupt.
+    //
+    HWREG(UDMA_ERRCLR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables a uDMA channel for operation.
+//!
+//! \param ui32ChannelNum is the channel number to enable.
+//!
+//! This function enables a specific uDMA channel for use.  This function must
+//! be used to enable a channel before it can be used to perform a uDMA
+//! transfer.
+//!
+//! When a uDMA transfer is completed, the channel is automatically disabled by
+//! the uDMA controller.  Therefore, this function should be called prior to
+//! starting up any new transfer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelEnable(uint32_t ui32ChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+    //
+    // Set the bit for this channel in the enable set register.
+    //
+    HWREG(UDMA_ENASET) = 1 << (ui32ChannelNum & 0x1f);
+}
+
+//*****************************************************************************
+//
+//! Disables a uDMA channel for operation.
+//!
+//! \param ui32ChannelNum is the channel number to disable.
+//!
+//! This function disables a specific uDMA channel.  Once disabled, a channel
+//! cannot respond to uDMA transfer requests until re-enabled via
+//! uDMAChannelEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelDisable(uint32_t ui32ChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+    //
+    // Set the bit for this channel in the enable clear register.
+    //
+    HWREG(UDMA_ENACLR) = 1 << (ui32ChannelNum & 0x1f);
+}
+
+//*****************************************************************************
+//
+//! Checks if a uDMA channel is enabled for operation.
+//!
+//! \param ui32ChannelNum is the channel number to check.
+//!
+//! This function checks to see if a specific uDMA channel is enabled.  This
+//! function can be used to check the status of a transfer, as the channel is
+//! automatically disabled at the end of a transfer.
+//!
+//! \return Returns \b true if the channel is enabled, \b false if disabled.
+//
+//*****************************************************************************
+bool
+uDMAChannelIsEnabled(uint32_t ui32ChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+    //
+    // AND the specified channel bit with the enable register and return the
+    // result.
+    //
+    return((HWREG(UDMA_ENASET) & (1 << (ui32ChannelNum & 0x1f))) ? true :
+           false);
+}
+
+//*****************************************************************************
+//
+//! Sets the base address for the channel control table.
+//!
+//! \param psControlTable is a pointer to the 1024-byte-aligned base address
+//! of the uDMA channel control table.
+//!
+//! This function configures the base address of the channel control table.
+//! This table resides in system memory and holds control information for each
+//! uDMA channel.  The table must be aligned on a 1024-byte boundary.  The base
+//! address must be configured before any of the channel functions can be used.
+//!
+//! The size of the channel control table depends on the number of uDMA
+//! channels and the transfer modes that are used.  Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAControlBaseSet(void *psControlTable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(((uint32_t)psControlTable & ~0x3FF) ==
+           (uint32_t)psControlTable);
+    ASSERT((uint32_t)psControlTable >= 0x20000000);
+
+    //
+    // Program the base address into the register.
+    //
+    HWREG(UDMA_CTLBASE) = (uint32_t)psControlTable;
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table.  This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlBaseGet(void)
+{
+    //
+    // Read the current value of the control base register and return it to
+    // the caller.
+    //
+    return((void *)HWREG(UDMA_CTLBASE));
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table alternate structures.
+//!
+//! This function gets the base address of the second half of the channel
+//! control table that holds the alternate control structures for each channel.
+//!
+//! \return Returns a pointer to the base address of the second half of the
+//! channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlAlternateBaseGet(void)
+{
+    //
+    // Read the current value of the control base register and return it to
+    // the caller.
+    //
+    return((void *)HWREG(UDMA_ALTBASE));
+}
+
+//*****************************************************************************
+//
+//! Requests a uDMA channel to start a transfer.
+//!
+//! \param ui32ChannelNum is the channel number on which to request a uDMA
+//! transfer.
+//!
+//! This function allows software to request a uDMA channel to begin a
+//! transfer.  This function could be used for performing a memory-to-memory
+//! transfer, or if for some reason a transfer needs to be initiated by
+//! software instead of the peripheral associated with that channel.
+//!
+//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then
+//! the completion is signaled on the uDMA dedicated interrupt.  If a
+//! peripheral channel is used, then the completion is signaled on the
+//! peripheral's interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelRequest(uint32_t ui32ChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+    //
+    // Set the bit for this channel in the software uDMA request register.
+    //
+    HWREG(UDMA_SWREQ) = 1 << (ui32ChannelNum & 0x1f);
+}
+
+//*****************************************************************************
+//
+//! Enables attributes of a uDMA channel.
+//!
+//! \param ui32ChannelNum is the channel to configure.
+//! \param ui32Attr is a combination of attributes for the channel.
+//!
+//! This function is used to enable attributes of a uDMA channel.
+//!
+//! The \e ui32Attr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel (it is very unlikely that this flag should be used).
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+    ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+                         UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    ui32ChannelNum &= 0x1f;
+
+    //
+    // Set the useburst bit for this channel if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_USEBURST)
+    {
+        HWREG(UDMA_USEBURSTSET) = 1 << ui32ChannelNum;
+    }
+
+    //
+    // Set the alternate control select bit for this channel,
+    // if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_ALTSELECT)
+    {
+        HWREG(UDMA_ALTSET) = 1 << ui32ChannelNum;
+    }
+
+    //
+    // Set the high priority bit for this channel, if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        HWREG(UDMA_PRIOSET) = 1 << ui32ChannelNum;
+    }
+
+    //
+    // Set the request mask bit for this channel, if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_REQMASK)
+    {
+        HWREG(UDMA_REQMASKSET) = 1 << ui32ChannelNum;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables attributes of a uDMA channel.
+//!
+//! \param ui32ChannelNum is the channel to configure.
+//! \param ui32Attr is a combination of attributes for the channel.
+//!
+//! This function is used to disable attributes of a uDMA channel.
+//!
+//! The \e ui32Attr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+    ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+                         UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    ui32ChannelNum &= 0x1f;
+
+    //
+    // Clear the useburst bit for this channel if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_USEBURST)
+    {
+        HWREG(UDMA_USEBURSTCLR) = 1 << ui32ChannelNum;
+    }
+
+    //
+    // Clear the alternate control select bit for this channel, if set in
+    // ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_ALTSELECT)
+    {
+        HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum;
+    }
+
+    //
+    // Clear the high priority bit for this channel, if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        HWREG(UDMA_PRIOCLR) = 1 << ui32ChannelNum;
+    }
+
+    //
+    // Clear the request mask bit for this channel, if set in ui32Config.
+    //
+    if(ui32Attr & UDMA_ATTR_REQMASK)
+    {
+        HWREG(UDMA_REQMASKCLR) = 1 << ui32ChannelNum;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the enabled attributes of a uDMA channel.
+//!
+//! \param ui32ChannelNum is the channel to configure.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the uDMA channel.
+//!
+//! \return Returns the logical OR of the attributes of the uDMA channel, which
+//! can be any of the following:
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelAttributeGet(uint32_t ui32ChannelNum)
+{
+    uint32_t ui32Attr = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    ui32ChannelNum &= 0x1f;
+
+    //
+    // Check to see if useburst bit is set for this channel.
+    //
+    if(HWREG(UDMA_USEBURSTSET) & (1 << ui32ChannelNum))
+    {
+        ui32Attr |= UDMA_ATTR_USEBURST;
+    }
+
+    //
+    // Check to see if the alternate control bit is set for this channel.
+    //
+    if(HWREG(UDMA_ALTSET) & (1 << ui32ChannelNum))
+    {
+        ui32Attr |= UDMA_ATTR_ALTSELECT;
+    }
+
+    //
+    // Check to see if the high priority bit is set for this channel.
+    //
+    if(HWREG(UDMA_PRIOSET) & (1 << ui32ChannelNum))
+    {
+        ui32Attr |= UDMA_ATTR_HIGH_PRIORITY;
+    }
+
+    //
+    // Check to see if the request mask bit is set for this channel.
+    //
+    if(HWREG(UDMA_REQMASKSET) & (1 << ui32ChannelNum))
+    {
+        ui32Attr |= UDMA_ATTR_REQMASK;
+    }
+
+    //
+    // Return the configuration flags.
+    //
+    return(ui32Attr);
+}
+
+//*****************************************************************************
+//
+//! Sets the control parameters for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ui32Control is logical OR of several control values to set the
+//! control parameters for the channel.
+//!
+//! This function is used to set control parameters for a uDMA transfer.  These
+//! parameters are typically not changed often.
+//!
+//! The \e ui32ChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ui32Control parameter is the logical OR of five values: the data
+//! size, the source address increment, the destination address increment, the
+//! arbitration size, and the use burst flag.  The choices available for each
+//! of these values is described below.
+//!
+//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or
+//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.
+//!
+//! Choose the source address increment from one of \b UDMA_SRC_INC_8,
+//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! Choose the destination address increment from one of \b UDMA_DST_INC_8,
+//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! The arbitration size determines how many items are transferred before
+//! the uDMA controller re-arbitrates for the bus.  Choose the arbitration size
+//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8,
+//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024
+//! items, in powers of 2.
+//!
+//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only
+//! respond to burst requests at the tail end of a scatter-gather transfer.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
+{
+    tDMAControlTable *psCtl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    ui32ChannelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    psCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off the fields to be
+    // changed, then OR in the new settings.
+    //
+    psCtl[ui32ChannelStructIndex].ui32Control =
+        ((psCtl[ui32ChannelStructIndex].ui32Control &
+          ~(UDMA_CHCTL_DSTINC_M |
+            UDMA_CHCTL_DSTSIZE_M |
+            UDMA_CHCTL_SRCINC_M |
+            UDMA_CHCTL_SRCSIZE_M |
+            UDMA_CHCTL_ARBSIZE_M |
+            UDMA_CHCTL_NXTUSEBURST)) |
+         ui32Control);
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer parameters for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ui32Mode is the type of uDMA transfer.
+//! \param pvSrcAddr is the source address for the transfer.
+//! \param pvDstAddr is the destination address for the transfer.
+//! \param ui32TransferSize is the number of data items to transfer.
+//!
+//! This function is used to configure the parameters for a uDMA transfer.
+//! These parameters are not typically changed often.  The function
+//! uDMAChannelControlSet() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \e ui32ChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ui32Mode parameter should be one of the following values:
+//!
+//! - \b UDMA_MODE_STOP stops the uDMA transfer.  The controller sets the mode
+//!   to this value at the end of a transfer.
+//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request.
+//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once
+//!   started even if the request is removed.
+//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the
+//!   primary and alternate control structures for the channel.  This mode
+//!   allows use of ping-pong buffering for uDMA transfers.
+//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather
+//!   transfer.
+//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather
+//!   transfer.
+//!
+//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first
+//! location of the data to be transferred.  These addresses should be aligned
+//! according to the item size.  The compiler takes care of this alignment if
+//! the pointers are pointing to storage of the appropriate data type.
+//!
+//! The \e ui32TransferSize parameter is the number of data items, not the
+//! number of bytes.
+//!
+//! The two scatter-gather modes, memory and peripheral, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected.  This function looks for the \b UDMA_PRI_SELECT and
+//! \b UDMA_ALT_SELECT flag along with the channel number and sets the
+//! scatter-gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using uDMAChannelEnable() after calling
+//! this function.  The transfer does not begin until the channel has been
+//! configured and enabled.  Note that the channel is automatically disabled
+//! after the transfer is completed, meaning that uDMAChannelEnable() must be
+//! called again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results are unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP.  For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode,
+                       void *pvSrcAddr, void *pvDstAddr,
+                       uint32_t ui32TransferSize)
+{
+    tDMAControlTable *psControlTable;
+    uint32_t ui32Control;
+    uint32_t ui32Inc;
+    uint32_t ui32BufferBytes;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+    ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER);
+    ASSERT((uint32_t)pvSrcAddr >= 0x20000000);
+    ASSERT((uint32_t)pvDstAddr >= 0x20000000);
+    ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= 1024));
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    ui32ChannelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off the mode and size
+    // fields.
+    //
+    ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
+                   ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // Adjust the mode if the alt control structure is selected.
+    //
+    if(ui32ChannelStructIndex & UDMA_ALT_SELECT)
+    {
+        if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+           (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            ui32Mode |= UDMA_MODE_ALT_SELECT;
+        }
+    }
+
+    //
+    // Set the transfer size and mode in the control word (but don't write the
+    // control word yet as it could kick off a transfer).
+    //
+    ui32Control |= ui32Mode | ((ui32TransferSize - 1) << 4);
+
+    //
+    // Get the address increment value for the source, from the control word.
+    //
+    ui32Inc = (ui32Control & UDMA_CHCTL_SRCINC_M);
+
+    //
+    // Compute the ending source address of the transfer.  If the source
+    // increment is set to none, then the ending address is the same as the
+    // beginning.
+    //
+    if(ui32Inc != UDMA_SRC_INC_NONE)
+    {
+        ui32Inc = ui32Inc >> 26;
+        ui32BufferBytes = ui32TransferSize << ui32Inc;
+        pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1);
+    }
+
+    //
+    // Load the source ending address into the control block.
+    //
+    psControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr;
+
+    //
+    // Get the address increment value for the destination, from the control
+    // word.
+    //
+    ui32Inc = ui32Control & UDMA_CHCTL_DSTINC_M;
+
+    //
+    // Compute the ending destination address of the transfer.  If the
+    // destination increment is set to none, then the ending address is the
+    // same as the beginning.
+    //
+    if(ui32Inc != UDMA_DST_INC_NONE)
+    {
+        //
+        // There is a special case if this is setting up a scatter-gather
+        // transfer.  The destination pointer must point to the end of
+        // the alternate structure for this channel instead of calculating
+        // the end of the buffer in the normal way.
+        //
+        if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+           (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            pvDstAddr =
+                (void *)&psControlTable[ui32ChannelStructIndex |
+                                        UDMA_ALT_SELECT].ui32Spare;
+        }
+        //
+        // Not a scatter-gather transfer, calculate end pointer normally.
+        //
+        else
+        {
+            ui32Inc = ui32Inc >> 30;
+            ui32BufferBytes = ui32TransferSize << ui32Inc;
+            pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1);
+        }
+    }
+
+    //
+    // Load the destination ending address into the control block.
+    //
+    psControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr;
+
+    //
+    // Write the new control word value.
+    //
+    psControlTable[ui32ChannelStructIndex].ui32Control = ui32Control;
+}
+
+//*****************************************************************************
+//
+//! Configures a uDMA channel for scatter-gather mode.
+//!
+//! \param ui32ChannelNum is the uDMA channel number.
+//! \param ui32TaskCount is the number of scatter-gather tasks to execute.
+//! \param pvTaskList is a pointer to the beginning of the scatter-gather
+//! task list.
+//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral
+//! scatter-gather transfer (else it is memory scatter-gather transfer)
+//!
+//! This function is used to configure a channel for scatter-gather mode.
+//! The caller must have already set up a task list and must pass a pointer to
+//! the start of the task list as the \e pvTaskList parameter.  The
+//! \e ui32TaskCount parameter is the count of tasks in the task list, not the
+//! size of the task list.  The flag \e bIsPeriphSG should be used to indicate
+//! if scatter-gather should be configured for peripheral or memory
+//! operation.
+//!
+//! \sa uDMATaskStructEntry
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount,
+                            void *pvTaskList, uint32_t ui32IsPeriphSG)
+{
+    tDMAControlTable *psControlTable;
+    tDMAControlTable *psTaskTable;
+
+    //
+    // Check the parameters
+    //
+    ASSERT((ui32ChannelNum & 0xffff) < 32);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+    ASSERT(pvTaskList != 0);
+    ASSERT(ui32TaskCount <= 1024);
+    ASSERT(ui32TaskCount != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    ui32ChannelNum &= 0x1f;
+
+    //
+    // Get the base address of the control table.
+    //
+    psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get a handy pointer to the task list
+    //
+    psTaskTable = (tDMAControlTable *)pvTaskList;
+
+    //
+    // Compute the ending address for the source pointer.  This address is the
+    // last element of the last task in the task table
+    //
+    psControlTable[ui32ChannelNum].pvSrcEndAddr =
+        &psTaskTable[ui32TaskCount - 1].ui32Spare;
+
+    //
+    // Compute the ending address for the destination pointer.  This address
+    // is the end of the alternate structure for this channel.
+    //
+    psControlTable[ui32ChannelNum].pvDstEndAddr =
+        &psControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare;
+
+    //
+    // Compute the control word.  Most configurable items are fixed for
+    // scatter-gather.  Item and increment sizes are all 32-bit and arb
+    // size must be 4.  The count is the number of items in the task list
+    // times 4 (4 words per task).
+    //
+    psControlTable[ui32ChannelNum].ui32Control =
+        (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 |
+         UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 |
+         UDMA_CHCTL_ARBSIZE_4 |
+         (((ui32TaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) |
+         (ui32IsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG :
+          UDMA_CHCTL_XFERMODE_MEM_SG));
+
+    //
+    // Scatter-gather operations can leave the alt bit set.  So if doing
+    // back to back scatter-gather transfers, the second attempt may not
+    // work correctly because the alt bit is set.  Therefore, clear the
+    // alt bit here to ensure that it is always cleared before a new SG
+    // transfer is started.
+    //
+    HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current transfer size for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the uDMA transfer size for a channel.  The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits.  If a partial transfer has already occurred,
+//! then the number of remaining items is returned.  If the transfer is
+//! complete, then 0 is returned.
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex)
+{
+    tDMAControlTable *psControlTable;
+    uint32_t ui32Control;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    ui32ChannelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off all but the size field
+    // and the mode field.
+    //
+    ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
+                   (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // If the size field and mode field are 0 then the transfer is finished
+    // and there are no more items to transfer
+    //
+    if(ui32Control == 0)
+    {
+        return(0);
+    }
+
+    //
+    // Otherwise, if either the size field or more field is non-zero, then
+    // not all the items have been transferred.
+    //
+    else
+    {
+        //
+        // Shift the size field and add one, then return to user.
+        //
+        return((ui32Control >> 4) + 1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the transfer mode for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the transfer mode for the uDMA channel and
+//! to query the status of a transfer on a channel.  When the transfer is
+//! complete the mode is \b UDMA_MODE_STOP.
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which is one of the following values: \b UDMA_MODE_STOP,
+//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelModeGet(uint32_t ui32ChannelStructIndex)
+{
+    tDMAControlTable *psControlTable;
+    uint32_t ui32Control;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the ui32ChannelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    ui32ChannelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off all but the mode field.
+    //
+    ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
+                   UDMA_CHCTL_XFERMODE_M);
+
+    //
+    // Check if scatter/gather mode, and if so, mask off the alt bit.
+    //
+    if(((ui32Control & ~UDMA_MODE_ALT_SELECT) ==
+        UDMA_MODE_MEM_SCATTER_GATHER) ||
+       ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
+    {
+        ui32Control &= ~UDMA_MODE_ALT_SELECT;
+    }
+
+    //
+    // Return the mode to the caller.
+    //
+    return(ui32Control);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the uDMA controller.
+//!
+//! \param ui32IntChannel identifies which uDMA interrupt is to be registered.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This function registers and enables the handler to be called when the uDMA
+//! controller generates an interrupt.  The \e ui32IntChannel parameter should
+//! be one of the following:
+//!
+//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts
+//!   from the uDMA software channel (UDMA_CHANNEL_SW)
+//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error
+//!   interrupts
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The interrupt handler for the uDMA is for transfer completion when
+//! the channel UDMA_CHANNEL_SW is used and for error interrupts.  The
+//! interrupts for each peripheral channel are handled through the individual
+//! peripheral interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(pfnHandler);
+    ASSERT((ui32IntChannel == UDMA_INT_SW) ||
+           (ui32IntChannel == UDMA_INT_ERR));
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32IntChannel, pfnHandler);
+
+    //
+    // Enable the memory management fault.
+    //
+    IntEnable(ui32IntChannel);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the uDMA controller.
+//!
+//! \param ui32IntChannel identifies which uDMA interrupt to unregister.
+//!
+//! This function disables and unregisters the handler to be called for the
+//! specified uDMA interrupt.  The \e ui32IntChannel parameter should be one of
+//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function
+//! uDMAIntRegister().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntUnregister(uint32_t ui32IntChannel)
+{
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ui32IntChannel);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32IntChannel);
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA controller channel interrupt status.
+//!
+//! This function is used to get the interrupt status of the uDMA controller.
+//! The returned value is a 32-bit bit mask that indicates which channels are
+//! requesting an interrupt.  This function can be used from within an
+//! interrupt handler to determine or confirm which uDMA channel has requested
+//! an interrupt.
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Interrupt Status Register (DMACHIS).  Please consult the data sheet for
+//! your part.
+//!
+//! \return Returns a 32-bit mask which indicates requesting uDMA channels.
+//! There is a bit for each channel and a 1 indicates that the channel
+//! is requesting an interrupt.  Multiple bits can be set.
+//
+//*****************************************************************************
+uint32_t
+uDMAIntStatus(void)
+{
+    //
+    // Return the value of the uDMA interrupt status register
+    //
+    return(HWREG(UDMA_CHIS));
+}
+
+//*****************************************************************************
+//
+//! Clears uDMA interrupt status.
+//!
+//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel.
+//!
+//! This function clears bits in the uDMA interrupt status register according
+//! to which bits are set in \e ui32ChanMask.  There is one bit for each
+//! channel.  If a a bit is set in \e ui32ChanMask, then that corresponding
+//! channel's interrupt status is cleared (if it was set).
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Interrupt Status Register (DMACHIS).  Please consult the data sheet for
+//! your part. Devices without the DMACHIS register have uDMA done status in
+//! the interrupt registers in the peripheral memory maps.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntClear(uint32_t ui32ChanMask)
+{
+    //
+    // Clear the requested bits in the uDMA interrupt status register
+    //
+    HWREG(UDMA_CHIS) = ui32ChanMask;
+}
+
+//*****************************************************************************
+//
+//! Assigns a peripheral mapping for a uDMA channel.
+//!
+//! \param ui32Mapping is a macro specifying the peripheral assignment for
+//! a channel.
+//!
+//! This function assigns a peripheral mapping to a uDMA channel.  It is
+//! used to select which peripheral is used for a uDMA channel.  The parameter
+//! \e ui32Mapping should be one of the macros named \b UDMA_CHn_tttt from the
+//! header file \e udma.h.  For example, to assign uDMA channel 0 to the
+//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX.
+//!
+//! Please consult the Tiva data sheet for a table showing all the
+//! possible peripheral assignments for the uDMA channels for a particular
+//! device.
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Map Select registers (DMACHMAP0-3).  Please consult the data sheet for
+//! your part.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAssign(uint32_t ui32Mapping)
+{
+    uint32_t ui32MapReg;
+    uint_fast8_t ui8MapShift;
+    uint_fast8_t ui8ChannelNum;
+
+    //
+    // Check the parameters
+    //
+    ASSERT((ui32Mapping & 0xffffff00) < 0x00050000);
+
+    //
+    // Extract the channel number and map encoding value from the parameter.
+    //
+    ui8ChannelNum = ui32Mapping & 0xff;
+    ui32Mapping = ui32Mapping >> 16;
+
+    //
+    // Find the uDMA channel mapping register and shift value to use for this
+    // channel
+    //
+    ui32MapReg = UDMA_CHMAP0 + (uint32_t)((ui8ChannelNum / 8) * 4);
+    ui8MapShift = (ui8ChannelNum % 8) * 4;
+
+    //
+    // Set the channel map encoding for this channel
+    //
+    HWREG(ui32MapReg) = (HWREG(ui32MapReg) & ~(0xf << ui8MapShift)) |
+                        ui32Mapping << ui8MapShift;
+}
+
+//*****************************************************************************
+//
+// The following functions are deprecated.  Use uDMAChannelAssign() instead
+// to accomplish the same end.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+//! Selects the secondary peripheral for a set of uDMA channels.
+//!
+//! \param ui32SecPeriphs is the logical OR of the uDMA channels for which to
+//! use the secondary peripheral, instead of the default peripheral.
+//!
+//! This function is used to select the secondary peripheral assignment for a
+//! set of uDMA channels.  By selecting the secondary peripheral assignment for
+//! a channel, the default peripheral assignment is no longer available for
+//! that channel.
+//!
+//! The parameter \e ui32SecPeriphs can be the logical OR of any of the
+//! following macros.  If one of the macros below is in the list passed to this
+//! function, then the secondary peripheral (marked as \b _SEC_) is selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs)
+{
+    //
+    // Select the secondary peripheral for the specified channels.
+    //
+    HWREG(UDMA_CHASGN) |= ui32SecPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Selects the default peripheral for a set of uDMA channels.
+//!
+//! \param ui32DefPeriphs is the logical OR of the uDMA channels for which to
+//! use the default peripheral, instead of the secondary peripheral.
+//!
+//! This function is used to select the default peripheral assignment for a set
+//! of uDMA channels.
+//!
+//! The parameter \e ui32DefPeriphs can be the logical OR of any of the
+//! following macros.  If one of the macros below is in the list passed to this
+//! function, then the default peripheral (marked as \b _DEF_) is selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectDefault(uint32_t ui32DefPeriphs)
+{
+    //
+    // Select the default peripheral for the specified channels.
+    //
+    HWREG(UDMA_CHASGN) &= ~ui32DefPeriphs;
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/udma.h b/bsp/tm4c129x/libraries/driverlib/udma.h
new file mode 100644
index 0000000000..3412c84ba7
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/udma.h
@@ -0,0 +1,899 @@
+//*****************************************************************************
+//
+// udma.h - Prototypes and macros for the uDMA controller.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_UDMA_H__
+#define __DRIVERLIB_UDMA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A structure that defines an entry in the channel control table.  These
+// fields are used by the uDMA controller and normally it is not necessary for
+// software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // The ending source address of the data transfer.
+    //
+    volatile void *pvSrcEndAddr;
+
+    //
+    // The ending destination address of the data transfer.
+    //
+    volatile void *pvDstEndAddr;
+
+    //
+    // The channel control mode.
+    //
+    volatile uint32_t ui32Control;
+
+    //
+    // An unused location.
+    //
+    volatile uint32_t ui32Spare;
+}
+tDMAControlTable;
+
+//*****************************************************************************
+//
+//! A helper macro for building scatter-gather task table entries.
+//!
+//! \param ui32TransferCount is the count of items to transfer for this task.
+//! \param ui32ItemSize is the bit size of the items to transfer for this task.
+//! \param ui32SrcIncrement is the bit size increment for source data.
+//! \param pvSrcAddr is the starting address of the data to transfer.
+//! \param ui32DstIncrement is the bit size increment for destination data.
+//! \param pvDstAddr is the starting address of the destination data.
+//! \param ui32ArbSize is the arbitration size to use for the transfer task.
+//! \param ui32Mode is the transfer mode for this task.
+//!
+//! This macro is intended to be used to help populate a table of uDMA tasks
+//! for a scatter-gather transfer.  This macro will calculate the values for
+//! the fields of a task structure entry based on the input parameters.
+//!
+//! There are specific requirements for the values of each parameter.  No
+//! checking is done so it is up to the caller to ensure that correct values
+//! are used for the parameters.
+//!
+//! The \e ui32TransferCount parameter is the number of items that will be
+//! transferred by this task.  It must be in the range 1-1024.
+//!
+//! The \e ui32ItemSize parameter is the bit size of the transfer data.  It
+//! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
+//!
+//! The \e ui32SrcIncrement parameter is the increment size for the source
+//! data.  It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
+//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
+//!
+//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
+//! data.
+//!
+//! The \e ui32DstIncrement parameter is the increment size for the destination
+//! data.  It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
+//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
+//!
+//! The \e pvDstAddr parameter is a void pointer to the beginning of the
+//! location where the data will be transferred.
+//!
+//! The \e ui32ArbSize parameter is the arbitration size for the transfer, and
+//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
+//! up to \b UDMA_ARB_1024.  This is used to select the arbitration size in
+//! powers of 2, from 1 to 1024.
+//!
+//! The \e ui32Mode parameter is the mode to use for this transfer task.  It
+//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.  Note
+//! that normally all tasks will be one of the scatter-gather modes while the
+//! last task is a task list will be AUTO or BASIC.
+//!
+//! This macro is intended to be used to initialize individual entries of
+//! a structure of tDMAControlTable type, like this:
+//!
+//! \verbatim
+//!     tDMAControlTable MyTaskList[] =
+//!     {
+//!         uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
+//!                             UDMA_SRC_INC_8, MySourceBuf,
+//!                             UDMA_DST_INC_8, MyDestBuf,
+//!                             UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
+//!         uDMATaskStructEntry(Task2Count, ...),
+//!     }
+//! \endverbatim
+//!
+//! \return Nothing; this is not a function.
+//
+//*****************************************************************************
+#define uDMATaskStructEntry(ui32TransferCount,                                \
+                            ui32ItemSize,                                     \
+                            ui32SrcIncrement,                                 \
+                            pvSrcAddr,                                        \
+                            ui32DstIncrement,                                 \
+                            pvDstAddr,                                        \
+                            ui32ArbSize,                                      \
+                            ui32Mode)                                         \
+    {                                                                         \
+        (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) :    \
+            ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) <<       \
+                                         ((ui32SrcIncrement) >> 26)) - 1]))), \
+            (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\
+            ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) <<       \
+                                         ((ui32DstIncrement) >> 30)) - 1]))), \
+        (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) |            \
+            (ui32ArbSize) |                                                   \
+        (((ui32TransferCount) - 1) << 4) |                                    \
+        ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) ||                     \
+          ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ?                     \
+                (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0            \
+    }
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Flags that can be passed to uDMAChannelAttributeEnable(),
+// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST      0x00000001
+#define UDMA_ATTR_ALTSELECT     0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK       0x00000008
+#define UDMA_ATTR_ALL           0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to uDMAModeSet() and returned
+// uDMAModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP          0x00000000
+#define UDMA_MODE_BASIC         0x00000001
+#define UDMA_MODE_AUTO          0x00000002
+#define UDMA_MODE_PINGPONG      0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER                                          \
+                                0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER                                          \
+                                0x00000006
+#define UDMA_MODE_ALT_SELECT    0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to uDMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8          0x00000000
+#define UDMA_DST_INC_16         0x40000000
+#define UDMA_DST_INC_32         0x80000000
+#define UDMA_DST_INC_NONE       0xc0000000
+#define UDMA_SRC_INC_8          0x00000000
+#define UDMA_SRC_INC_16         0x04000000
+#define UDMA_SRC_INC_32         0x08000000
+#define UDMA_SRC_INC_NONE       0x0c000000
+#define UDMA_SIZE_8             0x00000000
+#define UDMA_SIZE_16            0x11000000
+#define UDMA_SIZE_32            0x22000000
+#define UDMA_DST_PROT_PRIV      0x00200000
+#define UDMA_SRC_PROT_PRIV      0x00040000
+#define UDMA_ARB_1              0x00000000
+#define UDMA_ARB_2              0x00004000
+#define UDMA_ARB_4              0x00008000
+#define UDMA_ARB_8              0x0000c000
+#define UDMA_ARB_16             0x00010000
+#define UDMA_ARB_32             0x00014000
+#define UDMA_ARB_64             0x00018000
+#define UDMA_ARB_128            0x0001c000
+#define UDMA_ARB_256            0x00020000
+#define UDMA_ARB_512            0x00024000
+#define UDMA_ARB_1024           0x00028000
+#define UDMA_NEXT_USEBURST      0x00000008
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.
+//
+//*****************************************************************************
+#define UDMA_CHANNEL_USBEP1RX   0
+#define UDMA_CHANNEL_USBEP1TX   1
+#define UDMA_CHANNEL_USBEP2RX   2
+#define UDMA_CHANNEL_USBEP2TX   3
+#define UDMA_CHANNEL_USBEP3RX   4
+#define UDMA_CHANNEL_USBEP3TX   5
+#define UDMA_CHANNEL_ETH0RX     6
+#define UDMA_CHANNEL_ETH0TX     7
+#define UDMA_CHANNEL_UART0RX    8
+#define UDMA_CHANNEL_UART0TX    9
+#define UDMA_CHANNEL_SSI0RX     10
+#define UDMA_CHANNEL_SSI0TX     11
+#define UDMA_CHANNEL_ADC0       14
+#define UDMA_CHANNEL_ADC1       15
+#define UDMA_CHANNEL_ADC2       16
+#define UDMA_CHANNEL_ADC3       17
+#define UDMA_CHANNEL_TMR0A      18
+#define UDMA_CHANNEL_TMR0B      19
+#define UDMA_CHANNEL_TMR1A      20
+#define UDMA_CHANNEL_TMR1B      21
+#define UDMA_CHANNEL_UART1RX    22
+#define UDMA_CHANNEL_UART1TX    23
+#define UDMA_CHANNEL_SSI1RX     24
+#define UDMA_CHANNEL_SSI1TX     25
+#define UDMA_CHANNEL_I2S0RX     28
+#define UDMA_CHANNEL_I2S0TX     29
+#define UDMA_CHANNEL_SW         30
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT         0x00000000
+#define UDMA_ALT_SELECT         0x00000020
+
+//*****************************************************************************
+//
+// uDMA interrupt sources, to be passed to uDMAIntRegister() and
+// uDMAIntUnregister().
+//
+//*****************************************************************************
+#define UDMA_INT_SW             62
+#define UDMA_INT_ERR            63
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.  These are for secondary peripheral assignments.
+//
+//*****************************************************************************
+#define UDMA_SEC_CHANNEL_UART2RX_0                                            \
+                                0
+#define UDMA_SEC_CHANNEL_UART2TX_1                                            \
+                                1
+#define UDMA_SEC_CHANNEL_TMR3A  2
+#define UDMA_SEC_CHANNEL_TMR3B  3
+#define UDMA_SEC_CHANNEL_TMR2A_4                                              \
+                                4
+#define UDMA_SEC_CHANNEL_TMR2B_5                                              \
+                                5
+#define UDMA_SEC_CHANNEL_TMR2A_6                                              \
+                                6
+#define UDMA_SEC_CHANNEL_TMR2B_7                                              \
+                                7
+#define UDMA_SEC_CHANNEL_UART1RX                                              \
+                                8
+#define UDMA_SEC_CHANNEL_UART1TX                                              \
+                                9
+#define UDMA_SEC_CHANNEL_SSI1RX 10
+#define UDMA_SEC_CHANNEL_SSI1TX 11
+#define UDMA_SEC_CHANNEL_UART2RX_12                                           \
+                                12
+#define UDMA_SEC_CHANNEL_UART2TX_13                                           \
+                                13
+#define UDMA_SEC_CHANNEL_TMR2A_14                                             \
+                                14
+#define UDMA_SEC_CHANNEL_TMR2B_15                                             \
+                                15
+#define UDMA_SEC_CHANNEL_TMR1A  18
+#define UDMA_SEC_CHANNEL_TMR1B  19
+#define UDMA_SEC_CHANNEL_EPI0RX 20
+#define UDMA_SEC_CHANNEL_EPI0TX 21
+#define UDMA_SEC_CHANNEL_ADC10  24
+#define UDMA_SEC_CHANNEL_ADC11  25
+#define UDMA_SEC_CHANNEL_ADC12  26
+#define UDMA_SEC_CHANNEL_ADC13  27
+#define UDMA_SEC_CHANNEL_SW     30
+
+//*****************************************************************************
+//
+// Values that can be passed to uDMAChannelAssign() to select peripheral
+// mapping for each channel.  The channels named RESERVED may be assigned
+// to a peripheral in future parts.
+//
+//*****************************************************************************
+//
+// Channel 0
+//
+#define UDMA_CH0_USB0EP1RX          0x00000000
+#define UDMA_CH0_UART2RX            0x00010000
+#define UDMA_CH0_RESERVED2          0x00020000
+#define UDMA_CH0_TIMER4A            0x00030000
+#define UDMA_CH0_RESERVED4          0x00040000
+#define UDMA_CH0_RESERVED5          0x00050000
+#define UDMA_CH0_I2C0RX             0x00060000
+#define UDMA_CH0_RESERVED7          0x00070000
+#define UDMA_CH0_RESERVED8          0x00080000
+
+//
+// Channel 1
+//
+#define UDMA_CH1_USB0EP1TX          0x00000001
+#define UDMA_CH1_UART2TX            0x00010001
+#define UDMA_CH1_RESERVED2          0x00020001
+#define UDMA_CH1_TIMER4B            0x00030001
+#define UDMA_CH1_RESERVED4          0x00040001
+#define UDMA_CH1_RESERVED5          0x00050001
+#define UDMA_CH1_I2C0TX             0x00060001
+#define UDMA_CH1_RESERVED7          0x00070001
+#define UDMA_CH1_RESERVED8          0x00080001
+
+//
+// Channel 2
+//
+#define UDMA_CH2_USB0EP2RX          0x00000002
+#define UDMA_CH2_TIMER3A            0x00010002
+#define UDMA_CH2_RESERVED2          0x00020002
+#define UDMA_CH2_RESERVED3          0x00030002
+#define UDMA_CH2_RESERVED4          0x00040002
+#define UDMA_CH2_RESERVED5          0x00050002
+#define UDMA_CH2_I2C1RX             0x00060002
+#define UDMA_CH2_RESERVED7          0x00070002
+#define UDMA_CH2_RESERVED8          0x00080002
+
+//
+// Channel 3
+//
+#define UDMA_CH3_USB0EP2TX          0x00000003
+#define UDMA_CH3_TIMER3B            0x00010003
+#define UDMA_CH3_RESERVED2          0x00020003
+#define UDMA_CH3_LPC0_3             0x00030003
+#define UDMA_CH3_RESERVED4          0x00040003
+#define UDMA_CH3_RESERVED5          0x00050003
+#define UDMA_CH3_I2C1TX             0x00060003
+#define UDMA_CH3_RESERVED7          0x00070003
+#define UDMA_CH3_RESERVED8          0x00080003
+
+//
+// Channel 4
+//
+#define UDMA_CH4_USB0EP3RX          0x00000004
+#define UDMA_CH4_TIMER2A            0x00010004
+#define UDMA_CH4_RESERVED2          0x00020004
+#define UDMA_CH4_GPIOA              0x00030004
+#define UDMA_CH4_RESERVED4          0x00040004
+#define UDMA_CH4_SHAMD50CIN         0x00050004
+#define UDMA_CH4_I2C2RX             0x00060004
+#define UDMA_CH4_RESERVED7          0x00070004
+#define UDMA_CH4_RESERVED8          0x00080004
+
+//
+// Channel 5
+//
+#define UDMA_CH5_USB0EP3TX          0x00000005
+#define UDMA_CH5_TIMER2B            0x00010005
+#define UDMA_CH5_RESERVED2          0x00020005
+#define UDMA_CH5_GPIOB              0x00030005
+#define UDMA_CH5_RESERVED4          0x00040005
+#define UDMA_CH5_SHAMD50DIN         0x00050005
+#define UDMA_CH5_I2C2TX             0x00060005
+#define UDMA_CH5_RESERVED7          0x00070005
+#define UDMA_CH5_RESERVED8          0x00080005
+
+//
+// Channel 6
+//
+#define UDMA_CH6_RESERVED0          0x00000006
+#define UDMA_CH6_ETH0RX             0x00000006
+#define UDMA_CH6_TIMER2A            0x00010006
+#define UDMA_CH6_UART5RX            0x00020006
+#define UDMA_CH6_GPIOC              0x00030006
+#define UDMA_CH6_I2C0RX             0x00040006
+#define UDMA_CH6_SHAMD50COUT        0x00050006
+#define UDMA_CH6_RESERVED6          0x00060006
+#define UDMA_CH6_RESERVED7          0x00070006
+#define UDMA_CH6_RESERVED8          0x00080006
+
+//
+// Channel 7
+//
+#define UDMA_CH7_RESERVED0          0x00000007
+#define UDMA_CH7_ETH0TX             0x00000007
+#define UDMA_CH7_TIMER2B            0x00010007
+#define UDMA_CH7_UART5TX            0x00020007
+#define UDMA_CH7_GPIOD              0x00030007
+#define UDMA_CH7_I2C0TX             0x00040007
+#define UDMA_CH7_RESERVED5          0x00050007
+#define UDMA_CH7_RESERVED6          0x00060007
+#define UDMA_CH7_RESERVED7          0x00070007
+#define UDMA_CH7_RESERVED8          0x00080007
+
+//
+// Channel 8
+//
+#define UDMA_CH8_UART0RX            0x00000008
+#define UDMA_CH8_UART1RX            0x00010008
+#define UDMA_CH8_RESERVED2          0x00020008
+#define UDMA_CH8_TIMER5A            0x00030008
+#define UDMA_CH8_I2C1RX             0x00040008
+#define UDMA_CH8_RESERVED5          0x00050008
+#define UDMA_CH8_RESERVED6          0x00060008
+#define UDMA_CH8_RESERVED7          0x00070008
+#define UDMA_CH8_RESERVED8          0x00080008
+
+//
+// Channel 9
+//
+#define UDMA_CH9_UART0TX            0x00000009
+#define UDMA_CH9_UART1TX            0x00010009
+#define UDMA_CH9_RESERVED2          0x00020009
+#define UDMA_CH9_TIMER5B            0x00030009
+#define UDMA_CH9_I2C1TX             0x00040009
+#define UDMA_CH9_RESERVED5          0x00050009
+#define UDMA_CH9_RESERVED6          0x00060009
+#define UDMA_CH9_RESERVED7          0x00070009
+#define UDMA_CH9_RESERVED8          0x00080009
+
+//
+// Channel 10
+//
+#define UDMA_CH10_SSI0RX            0x0000000A
+#define UDMA_CH10_SSI1RX            0x0001000A
+#define UDMA_CH10_UART6RX           0x0002000A
+#define UDMA_CH10_WTIMER0A          0x0003000A
+#define UDMA_CH10_I2C2RX            0x0004000A
+#define UDMA_CH10_RESERVED5         0x0005000A
+#define UDMA_CH10_RESERVED6         0x0006000A
+#define UDMA_CH10_TIMER6A           0x0007000A
+#define UDMA_CH10_RESERVED8         0x0008000A
+
+//
+// Channel 11
+//
+#define UDMA_CH11_SSI0TX            0x0000000B
+#define UDMA_CH11_SSI1TX            0x0001000B
+#define UDMA_CH11_UART6TX           0x0002000B
+#define UDMA_CH11_WTIMER0B          0x0003000B
+#define UDMA_CH11_I2C2TX            0x0004000B
+#define UDMA_CH11_RESERVED5         0x0005000B
+#define UDMA_CH11_RESERVED6         0x0006000B
+#define UDMA_CH11_TIMER6B           0x0007000B
+#define UDMA_CH11_RESERVED8         0x0008000B
+
+//
+// Channel 12
+//
+#define UDMA_CH12_RESERVED0         0x0000000C
+#define UDMA_CH12_UART2RX           0x0001000C
+#define UDMA_CH12_SSI2RX            0x0002000C
+#define UDMA_CH12_WTIMER1A          0x0003000C
+#define UDMA_CH12_GPIOK             0x0004000C
+#define UDMA_CH12_AES0CIN           0x0005000C
+#define UDMA_CH12_RESERVED6         0x0006000C
+#define UDMA_CH12_TIMER7A           0x0007000C
+#define UDMA_CH12_RESERVED8         0x0008000C
+
+//
+// Channel 13
+//
+#define UDMA_CH13_RESERVED0         0x0000000D
+#define UDMA_CH13_UART2TX           0x0001000D
+#define UDMA_CH13_SSI2TX            0x0002000D
+#define UDMA_CH13_WTIMER1B          0x0003000D
+#define UDMA_CH13_GPIOL             0x0004000D
+#define UDMA_CH13_AES0COUT          0x0005000D
+#define UDMA_CH13_RESERVED6         0x0006000D
+#define UDMA_CH13_TIMER7B           0x0007000D
+#define UDMA_CH13_RESERVED8         0x0008000D
+
+//
+// Channel 14
+//
+#define UDMA_CH14_ADC0_0            0x0000000E
+#define UDMA_CH14_TIMER2A           0x0001000E
+#define UDMA_CH14_SSI3RX            0x0002000E
+#define UDMA_CH14_GPIOE             0x0003000E
+#define UDMA_CH14_GPIOM             0x0004000E
+#define UDMA_CH14_AES0DIN           0x0005000E
+#define UDMA_CH14_RESERVED6         0x0006000E
+#define UDMA_CH14_RESERVED7         0x0007000E
+#define UDMA_CH14_RESERVED8         0x0008000E
+
+//
+// Channel 15
+//
+#define UDMA_CH15_ADC0_1            0x0000000F
+#define UDMA_CH15_TIMER2B           0x0001000F
+#define UDMA_CH15_SSI3TX            0x0002000F
+#define UDMA_CH15_GPIOF             0x0003000F
+#define UDMA_CH15_GPION             0x0004000F
+#define UDMA_CH15_AES0DOUT          0x0005000F
+#define UDMA_CH15_RESERVED6         0x0006000F
+#define UDMA_CH15_RESERVED7         0x0007000F
+#define UDMA_CH15_RESERVED8         0x0008000F
+
+//
+// Channel 16
+//
+#define UDMA_CH16_ADC0_2            0x00000010
+#define UDMA_CH16_RESERVED1         0x00010010
+#define UDMA_CH16_UART3RX           0x00020010
+#define UDMA_CH16_WTIMER2A          0x00030010
+#define UDMA_CH16_GPIOP             0x00040010
+#define UDMA_CH16_RESERVED5         0x00050010
+#define UDMA_CH16_RESERVED6         0x00060010
+#define UDMA_CH16_RESERVED7         0x00070010
+#define UDMA_CH16_RESERVED8         0x00080010
+
+//
+// Channel 17
+//
+#define UDMA_CH17_ADC0_3            0x00000011
+#define UDMA_CH17_RESERVED1         0x00010011
+#define UDMA_CH17_UART3TX           0x00020011
+#define UDMA_CH17_WTIMER2B          0x00030011
+#define UDMA_CH17_RESERVED4         0x00040011
+#define UDMA_CH17_RESERVED5         0x00050011
+#define UDMA_CH17_RESERVED6         0x00060011
+#define UDMA_CH17_RESERVED7         0x00070011
+#define UDMA_CH17_RESERVED8         0x00080011
+
+//
+// Channel 18
+//
+#define UDMA_CH18_TIMER0A           0x00000012
+#define UDMA_CH18_TIMER1A           0x00010012
+#define UDMA_CH18_UART4RX           0x00020012
+#define UDMA_CH18_GPIOB             0x00030012
+#define UDMA_CH18_I2C3RX            0x00040012
+#define UDMA_CH18_RESERVED5         0x00050012
+#define UDMA_CH18_RESERVED6         0x00060012
+#define UDMA_CH18_RESERVED7         0x00070012
+#define UDMA_CH18_RESERVED8         0x00080012
+
+//
+// Channel 19
+//
+#define UDMA_CH19_TIMER0B           0x00000013
+#define UDMA_CH19_TIMER1B           0x00010013
+#define UDMA_CH19_UART4TX           0x00020013
+#define UDMA_CH19_GPIOG             0x00030013
+#define UDMA_CH19_I2C3TX            0x00040013
+#define UDMA_CH19_RESERVED5         0x00050013
+#define UDMA_CH19_RESERVED6         0x00060013
+#define UDMA_CH19_RESERVED7         0x00070013
+#define UDMA_CH19_RESERVED8         0x00080013
+
+//
+// Channel 20
+//
+#define UDMA_CH20_TIMER1A           0x00000014
+#define UDMA_CH20_RESERVED1         0x00010014
+#define UDMA_CH20_EPI0RX            0x00010014
+#define UDMA_CH20_UART7RX           0x00020014
+#define UDMA_CH20_GPIOH             0x00030014
+#define UDMA_CH20_I2C4RX            0x00040014
+#define UDMA_CH20_DES0CIN           0x00050014
+#define UDMA_CH20_RESERVED6         0x00060014
+#define UDMA_CH20_RESERVED7         0x00070014
+#define UDMA_CH20_RESERVED8         0x00080014
+
+//
+// Channel 21
+//
+#define UDMA_CH21_TIMER1B           0x00000015
+#define UDMA_CH21_RESERVED1         0x00010015
+#define UDMA_CH21_EPI0TX            0x00010015
+#define UDMA_CH21_UART7TX           0x00020015
+#define UDMA_CH21_GPIOJ             0x00030015
+#define UDMA_CH21_I2C4TX            0x00040015
+#define UDMA_CH21_DES0DIN           0x00050015
+#define UDMA_CH21_RESERVED6         0x00060015
+#define UDMA_CH21_RESERVED7         0x00070015
+#define UDMA_CH21_RESERVED8         0x00080015
+
+//
+// Channel 22
+//
+#define UDMA_CH22_UART1RX           0x00000016
+#define UDMA_CH22_RESERVED1         0x00010016
+#define UDMA_CH22_RESERVED2         0x00020016
+#define UDMA_CH22_LPC0_2            0x00030016
+#define UDMA_CH22_I2C5RX            0x00040016
+#define UDMA_CH22_DES0DOUT          0x00050016
+#define UDMA_CH22_RESERVED6         0x00060016
+#define UDMA_CH22_RESERVED7         0x00070016
+#define UDMA_CH22_I2C8RX            0x00080016
+
+//
+// Channel 23
+//
+#define UDMA_CH23_UART1TX           0x00000017
+#define UDMA_CH23_RESERVED1         0x00010017
+#define UDMA_CH23_RESERVED2         0x00020017
+#define UDMA_CH23_LPC0_1            0x00030017
+#define UDMA_CH23_I2C5TX            0x00040017
+#define UDMA_CH23_RESERVED5         0x00050017
+#define UDMA_CH23_RESERVED6         0x00060017
+#define UDMA_CH23_RESERVED7         0x00070017
+#define UDMA_CH23_I2C8TX            0x00080017
+
+//
+// Channel 24
+//
+#define UDMA_CH24_SSI1RX            0x00000018
+#define UDMA_CH24_ADC1_0            0x00010018
+#define UDMA_CH24_RESERVED2         0x00020018
+#define UDMA_CH24_WTIMER3A          0x00030018
+#define UDMA_CH24_GPIOQ             0x00040018
+#define UDMA_CH24_RESERVED5         0x00050018
+#define UDMA_CH24_RESERVED6         0x00060018
+#define UDMA_CH24_RESERVED7         0x00070018
+#define UDMA_CH24_I2C9RX            0x00080018
+
+//
+// Channel 25
+//
+#define UDMA_CH25_SSI1TX            0x00000019
+#define UDMA_CH25_ADC1_1            0x00010019
+#define UDMA_CH25_RESERVED2         0x00020019
+#define UDMA_CH25_WTIMER3B          0x00030019
+#define UDMA_CH25_RESERVED4         0x00040019
+#define UDMA_CH25_RESERVED5         0x00050019
+#define UDMA_CH25_RESERVED6         0x00060019
+#define UDMA_CH25_RESERVED7         0x00070019
+#define UDMA_CH25_I2C9TX            0x00080019
+
+//
+// Channel 26
+//
+#define UDMA_CH26_RESERVED0         0x0000001A
+#define UDMA_CH26_ADC1_2            0x0001001A
+#define UDMA_CH26_RESERVED2         0x0002001A
+#define UDMA_CH26_WTIMER4A          0x0003001A
+#define UDMA_CH26_RESERVED4         0x0004001A
+#define UDMA_CH26_RESERVED5         0x0005001A
+#define UDMA_CH26_RESERVED6         0x0006001A
+#define UDMA_CH26_RESERVED7         0x0007001A
+#define UDMA_CH26_I2C6RX            0x0008001A
+
+//
+// Channel 27
+//
+#define UDMA_CH27_RESERVED0         0x0000001B
+#define UDMA_CH27_ADC1_3            0x0001001B
+#define UDMA_CH27_RESERVED2         0x0002001B
+#define UDMA_CH27_WTIMER4B          0x0003001B
+#define UDMA_CH27_RESERVED4         0x0004001B
+#define UDMA_CH27_RESERVED5         0x0005001B
+#define UDMA_CH27_RESERVED6         0x0006001B
+#define UDMA_CH27_RESERVED7         0x0007001B
+#define UDMA_CH27_I2C6TX            0x0008001B
+
+//
+// Channel 28
+//
+#define UDMA_CH28_RESERVED0         0x0000001C
+#define UDMA_CH28_RESERVED1         0x0001001C
+#define UDMA_CH28_RESERVED2         0x0002001C
+#define UDMA_CH28_WTIMER5A          0x0003001C
+#define UDMA_CH28_RESERVED4         0x0004001C
+#define UDMA_CH28_RESERVED5         0x0005001C
+#define UDMA_CH28_RESERVED6         0x0006001C
+#define UDMA_CH28_RESERVED7         0x0007001C
+#define UDMA_CH28_I2C7RX            0x0008001C
+
+//
+// Channel 29
+//
+#define UDMA_CH29_RESERVED0         0x0000001D
+#define UDMA_CH29_RESERVED1         0x0001001D
+#define UDMA_CH29_RESERVED2         0x0002001D
+#define UDMA_CH29_WTIMER5B          0x0003001D
+#define UDMA_CH29_RESERVED4         0x0004001D
+#define UDMA_CH29_RESERVED5         0x0005001D
+#define UDMA_CH29_RESERVED6         0x0006001D
+#define UDMA_CH29_RESERVED7         0x0007001D
+#define UDMA_CH29_I2C7TX            0x0008001D
+
+//
+// Channel 30
+//
+#define UDMA_CH30_SW                0x0000001E
+#define UDMA_CH30_RESERVED1         0x0001001E
+#define UDMA_CH30_RESERVED2         0x0002001E
+#define UDMA_CH30_RESERVED3         0x0003001E
+#define UDMA_CH30_RESERVED4         0x0004001E
+#define UDMA_CH30_RESERVED5         0x0005001E
+#define UDMA_CH30_RESERVED6         0x0006001E
+#define UDMA_CH30_EPI0RX            0x0007001E
+#define UDMA_CH30_1WIRE0            0x0008001E
+
+//
+// Channel 31
+//
+#define UDMA_CH31_RESERVED0         0x0000001F
+#define UDMA_CH31_RESERVED1         0x0001001F
+#define UDMA_CH31_RESERVED2         0x0002001F
+#define UDMA_CH31_LPC0_0            0x0003001F
+#define UDMA_CH31_RESERVED4         0x0004001F
+#define UDMA_CH31_RESERVED5         0x0005001F
+#define UDMA_CH31_RESERVED6         0x0006001F
+#define UDMA_CH31_EPI0RX            0x0007001F
+#define UDMA_CH31_RESERVED8         0x0008001F
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void uDMAEnable(void);
+extern void uDMADisable(void);
+extern uint32_t uDMAErrorStatusGet(void);
+extern void uDMAErrorStatusClear(void);
+extern void uDMAChannelEnable(uint32_t ui32ChannelNum);
+extern void uDMAChannelDisable(uint32_t ui32ChannelNum);
+extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum);
+extern void uDMAControlBaseSet(void *pControlTable);
+extern void *uDMAControlBaseGet(void);
+extern void *uDMAControlAlternateBaseGet(void);
+extern void uDMAChannelRequest(uint32_t ui32ChannelNum);
+extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum,
+                                       uint32_t ui32Attr);
+extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum,
+                                        uint32_t ui32Attr);
+extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum);
+extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex,
+                                  uint32_t ui32Control);
+extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex,
+                                   uint32_t ui32Mode, void *pvSrcAddr,
+                                   void *pvDstAddr, uint32_t ui32TransferSize);
+extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum,
+                                        uint32_t ui32TaskCount,
+                                        void *pvTaskList,
+                                        uint32_t ui32IsPeriphSG);
+extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex);
+extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex);
+extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void));
+extern void uDMAIntUnregister(uint32_t ui32IntChannel);
+extern uint32_t uDMAIntStatus(void);
+extern void uDMAIntClear(uint32_t ui32ChanMask);
+extern void uDMAChannelAssign(uint32_t ui32Mapping);
+
+//*****************************************************************************
+//
+// The following functions and definitions are deprecated and will be removed
+// from the API in the future.  Use uDMAChannelAssign() instead to accomplish
+// the same end.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// uDMA default/secondary peripheral selections, to be passed to
+// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
+//
+//*****************************************************************************
+#define UDMA_DEF_USBEP1RX_SEC_UART2RX                                         \
+                                0x00000001
+#define UDMA_DEF_USBEP1TX_SEC_UART2TX                                         \
+                                0x00000002
+#define UDMA_DEF_USBEP2RX_SEC_TMR3A                                           \
+                                0x00000004
+#define UDMA_DEF_USBEP2TX_SEC_TMR3B                                           \
+                                0x00000008
+#define UDMA_DEF_USBEP3RX_SEC_TMR2A                                           \
+                                0x00000010
+#define UDMA_DEF_USBEP3TX_SEC_TMR2B                                           \
+                                0x00000020
+#define UDMA_DEF_ETH0RX_SEC_TMR2A                                             \
+                                0x00000040
+#define UDMA_DEF_ETH0TX_SEC_TMR2B                                             \
+                                0x00000080
+#define UDMA_DEF_UART0RX_SEC_UART1RX                                          \
+                                0x00000100
+#define UDMA_DEF_UART0TX_SEC_UART1TX                                          \
+                                0x00000200
+#define UDMA_DEF_SSI0RX_SEC_SSI1RX                                            \
+                                0x00000400
+#define UDMA_DEF_SSI0TX_SEC_SSI1TX                                            \
+                                0x00000800
+#define UDMA_DEF_RESERVED_SEC_UART2RX                                         \
+                                0x00001000
+#define UDMA_DEF_RESERVED_SEC_UART2TX                                         \
+                                0x00002000
+#define UDMA_DEF_ADC00_SEC_TMR2A                                              \
+                                0x00004000
+#define UDMA_DEF_ADC01_SEC_TMR2B                                              \
+                                0x00008000
+#define UDMA_DEF_ADC02_SEC_RESERVED                                           \
+                                0x00010000
+#define UDMA_DEF_ADC03_SEC_RESERVED                                           \
+                                0x00020000
+#define UDMA_DEF_TMR0A_SEC_TMR1A                                              \
+                                0x00040000
+#define UDMA_DEF_TMR0B_SEC_TMR1B                                              \
+                                0x00080000
+#define UDMA_DEF_TMR1A_SEC_EPI0RX                                             \
+                                0x00100000
+#define UDMA_DEF_TMR1B_SEC_EPI0TX                                             \
+                                0x00200000
+#define UDMA_DEF_UART1RX_SEC_RESERVED                                         \
+                                0x00400000
+#define UDMA_DEF_UART1TX_SEC_RESERVED                                         \
+                                0x00800000
+#define UDMA_DEF_SSI1RX_SEC_ADC10                                             \
+                                0x01000000
+#define UDMA_DEF_SSI1TX_SEC_ADC11                                             \
+                                0x02000000
+#define UDMA_DEF_RESERVED_SEC_ADC12                                           \
+                                0x04000000
+#define UDMA_DEF_RESERVED_SEC_ADC13                                           \
+                                0x08000000
+#define UDMA_DEF_I2S0RX_SEC_RESERVED                                          \
+                                0x10000000
+#define UDMA_DEF_I2S0TX_SEC_RESERVED                                          \
+                                0x20000000
+
+extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs);
+extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs);
+
+#endif
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_UDMA_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/usb.c b/bsp/tm4c129x/libraries/driverlib/usb.c
new file mode 100644
index 0000000000..0f221f4448
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/usb.c
@@ -0,0 +1,5909 @@
+//*****************************************************************************
+//
+// usb.c - Driver for the USB Interface.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usb_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_usb.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/udma.h"
+#include "driverlib/usb.h"
+
+//*****************************************************************************
+//
+// Amount to shift the RX interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#define USB_INTEP_RX_SHIFT      16
+
+//*****************************************************************************
+//
+// Amount to shift the RX endpoint status sources by in the flags used in the
+// calls.
+//
+//*****************************************************************************
+#define USB_RX_EPSTATUS_SHIFT   16
+
+//*****************************************************************************
+//
+// Converts from an endpoint specifier to the offset of the endpoint's
+// control/status registers.
+//
+//*****************************************************************************
+#define EP_OFFSET(Endpoint)     (Endpoint - 0x10)
+
+//*****************************************************************************
+//
+// Sets one of the indexed registers.
+//
+// \param ui32Base specifies the USB module base address.
+// \param ui32Endpoint is the endpoint index to target for this write.
+// \param ui32IndexedReg is the indexed register to write to.
+// \param ui8Value is the value to write to the register.
+//
+// This function is used to access the indexed registers for each endpoint.
+// The only registers that are indexed are the FIFO configuration registers,
+// which are not used after configuration.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint,
+               uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size)
+{
+    uint32_t ui32Index;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) ||
+           (ui32Endpoint == 3));
+    ASSERT((ui32Size == 1) || (ui32Size == 2));
+
+    //
+    // Save the old index in case it was in use.
+    //
+    ui32Index = HWREGB(ui32Base + USB_O_EPIDX);
+
+    //
+    // Set the index.
+    //
+    HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint;
+
+    //
+    // Determine the size of the register value.
+    //
+    if(ui32Size == 1)
+    {
+        //
+        // Set the value.
+        //
+        HWREGB(ui32Base + ui32IndexedReg) = ui32Value;
+    }
+    else
+    {
+        //
+        // Set the value.
+        //
+        HWREGH(ui32Base + ui32IndexedReg) = ui32Value;
+    }
+
+    //
+    // Restore the old index in case it was in use.
+    //
+    HWREGB(ui32Base + USB_O_EPIDX) = ui32Index;
+}
+
+//*****************************************************************************
+//
+// Reads one of the indexed registers.
+//
+// \param ui32Base specifies the USB module base address.
+// \param ui32Endpoint is the endpoint index to target for this write.
+// \param ui32IndexedReg is the indexed register to write to.
+//
+// This function is used internally to access the indexed registers for each
+// endpoint.  The only registers that are indexed are the FIFO configuration
+// registers, which are not used after configuration.
+//
+// \return The value in the register requested.
+//
+//*****************************************************************************
+static uint32_t
+_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint,
+              uint32_t ui32IndexedReg, uint32_t ui32Size)
+{
+    uint8_t ui8Index;
+    uint8_t ui8Value;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) ||
+           (ui32Endpoint == 3));
+    ASSERT((ui32Size == 1) || (ui32Size == 2));
+
+    //
+    // Save the old index in case it was in use.
+    //
+    ui8Index = HWREGB(ui32Base + USB_O_EPIDX);
+
+    //
+    // Set the index.
+    //
+    HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint;
+
+    //
+    // Determine the size of the register value.
+    //
+    if(ui32Size == 1)
+    {
+        //
+        // Get the value.
+        //
+        ui8Value = HWREGB(ui32Base + ui32IndexedReg);
+    }
+    else
+    {
+        //
+        // Get the value.
+        //
+        ui8Value = HWREGH(ui32Base + ui32IndexedReg);
+    }
+
+    //
+    // Restore the old index in case it was in use.
+    //
+    HWREGB(ui32Base + USB_O_EPIDX) = ui8Index;
+
+    //
+    // Return the register's value.
+    //
+    return(ui8Value);
+}
+
+//*****************************************************************************
+//
+//! Puts the USB bus in a suspended state.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! When used in host mode, this function puts the USB bus in the suspended
+//! state.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostSuspend(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Send the suspend signaling to the USB bus.
+    //
+    HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND;
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus reset condition.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bStart specifies whether to start or stop signaling reset on the USB
+//! bus.
+//!
+//! When this function is called with the \e bStart parameter set to \b true,
+//! this function causes the start of a reset condition on the USB bus.
+//! The caller must then delay at least 20ms before calling this function
+//! again with the \e bStart parameter set to \b false.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostReset(uint32_t ui32Base, bool bStart)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Send a reset signal to the bus.
+    //
+    if(bStart)
+    {
+        HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET;
+    }
+    else
+    {
+        HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables or disables USB high-speed negotiation.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bEnable specifies whether to enable or disable high-speed
+//! negotiation.
+//!
+//! High-speed negotiations for both host and device mode are enabled when this
+//! function is called with the \e bEnable parameter set to \b true.  In device
+//! mode this causes the device to negotiate for high speed when the
+//! USB controller receives a reset from the host.  In host mode, the USB host
+//! enables high-speed negotiations when resetting the connected device.  If
+//! \e bEnable is set to \b false the controller only operates only in
+//! full-speed or low-speed.
+//!
+//! \b Example: Enable USB high-speed mode.
+//!
+//! \verbatim
+//! //
+//! // Enable USB high-speed mode.
+//! //
+//! USBHighSpeed(USB0_BASE, true);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices and should only be
+//! called when the USB is connected to an external ULPI PHY.  Please
+//! check the data sheet to determine if the USB controller can interface with
+//! a ULPI PHY.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHighSpeed(uint32_t ui32Base, bool bEnable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    if(bEnable)
+    {
+        //
+        // Enable high speed mode negotiations in hosts or device mode.
+        //
+        HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_HSENAB;
+    }
+    else
+    {
+        //
+        // Enable high speed mode negotiations in hosts or device mode.
+        //
+        HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_HSENAB;
+    }
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus resume condition.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bStart specifies if the USB controller is entering or leaving the
+//! resume signaling state.
+//!
+//! When in device mode, this function brings the USB controller out of the
+//! suspend state.  This call must first be made with the \e bStart parameter
+//! set to \b true to start resume signaling.  The device application must
+//! then delay at least 10ms but not more than 15ms before calling this
+//! function with the \e bStart parameter set to \b false.
+//!
+//! When in host mode, this function signals devices to leave the suspend
+//! state.  This call must first be made with the \e bStart parameter set to
+//! \b true to start resume signaling.  The host application must then delay
+//! at least 20ms before calling this function with the \e bStart parameter set
+//! to \b false.  This action causes the controller to complete the resume
+//! signaling on the USB bus.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostResume(uint32_t ui32Base, bool bStart)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Send a resume signal to the bus.
+    //
+    if(bStart)
+    {
+        HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME;
+    }
+    else
+    {
+        HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the current speed of the USB device connected.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current speed of the USB bus in host mode.
+//!
+//! \b Example: Get the USB connection speed.
+//!
+//! \verbatim
+//! //
+//! // Get the connection speed of the device connected to the USB controller.
+//! //
+//! USBHostSpeedGet(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED,
+//! \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED.
+//
+//*****************************************************************************
+uint32_t
+USBHostSpeedGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // If the Full Speed device bit is set, then this is a full speed device.
+    //
+    if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE)
+    {
+        return(USB_HIGH_SPEED);
+    }
+
+    //
+    // If the Full Speed device bit is set, then this is a full speed device.
+    //
+    if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV)
+    {
+        return(USB_FULL_SPEED);
+    }
+
+    //
+    // If the Low Speed device bit is set, then this is a low speed device.
+    //
+    if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV)
+    {
+        return(USB_LOW_SPEED);
+    }
+
+    //
+    // The device speed is not known.
+    //
+    return(USB_UNDEF_SPEED);
+}
+
+//*****************************************************************************
+//
+//! Returns the current speed of the USB controller in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the operating speed of the connection to the USB host
+//! controller.  This function returns either \b USB_HIGH_SPEED or
+//! \b USB_FULL_SPEED to indicate the connection speed in device mode.
+//!
+//! \b Example: Get the USB connection speed.
+//!
+//! \verbatim
+//! //
+//! // Get the connection speed of the USB controller.
+//! //
+//! USBDevSpeedGet(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return Returns either \b USB_HIGH_SPEED or \b USB_FULL_SPEED.
+//
+//*****************************************************************************
+uint32_t
+USBDevSpeedGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // If the Full Speed device bit is set, then this is a full speed device.
+    //
+    if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE)
+    {
+        return(USB_HIGH_SPEED);
+    }
+
+    return(USB_FULL_SPEED);
+}
+
+//*****************************************************************************
+//
+//! Disables control interrupts on a specified USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which control interrupts to disable.
+//!
+//! This function disables the control interrupts for the USB controller
+//! specified by the \e ui32Base parameter.  The \e ui32Flags parameter
+//! specifies which control interrupts to disable.  The flags passed in the
+//! \e ui32Flags parameters must be the definitions that start with
+//! \b USB_INTCTRL_* and not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0);
+
+    //
+    // If any general interrupts were disabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ui32Flags & USB_INTCTRL_STATUS)
+    {
+        HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS);
+    }
+
+    //
+    // Disable the power fault interrupt.
+    //
+    if(ui32Flags & USB_INTCTRL_POWER_FAULT)
+    {
+        HWREG(ui32Base + USB_O_EPCIM) = 0;
+    }
+
+    //
+    // Disable the ID pin detect interrupt.
+    //
+    if(ui32Flags & USB_INTCTRL_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables control interrupts on a specified USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which control interrupts to enable.
+//!
+//! This function enables the control interrupts for the USB controller
+//! specified by the \e ui32Base parameter.  The \e ui32Flags parameter
+//! specifies which control interrupts to enable.  The flags passed in the
+//! \e ui32Flags parameters must be the definitions that start with
+//! \b USB_INTCTRL_* and not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0);
+
+    //
+    // If any general interrupts were enabled, then write the general
+    // interrupt settings out to the hardware.
+    //
+    if(ui32Flags & USB_INTCTRL_STATUS)
+    {
+        HWREGB(ui32Base + USB_O_IE) |= ui32Flags;
+    }
+
+    //
+    // Enable the power fault interrupt.
+    //
+    if(ui32Flags & USB_INTCTRL_POWER_FAULT)
+    {
+        HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF;
+    }
+
+    //
+    // Enable the ID pin detect interrupt.
+    //
+    if(ui32Flags & USB_INTCTRL_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the control interrupt status on a specified USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function reads control interrupt status for a USB controller.  This
+//! call returns the current status for control interrupts only, the endpoint
+//! interrupt status is retrieved by calling USBIntStatusEndpoint().  The bit
+//! values returned are compared against the \b USB_INTCTRL_* values.
+//!
+//! The following are the meanings of all \b USB_INCTRL_ flags and the modes
+//! for which they are valid.  These values apply to any calls to
+//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl().
+//! Some of these flags are only valid in the following modes as indicated in
+//! the parentheses:  Host, Device, and OTG.
+//!
+//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources.
+//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only).
+//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable
+//!                            (OTG Only).
+//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only)
+//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only)
+//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only)
+//! - \b USB_INTCTRL_SOF - Start of Frame Detected.
+//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past
+//!                           the end of a frame (Host Only)
+//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only)
+//! - \b USB_INTCTRL_RESUME - Resume signaling detected.
+//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device
+//!                            Only)
+//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed
+//!                                (OTG Only)
+//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only)
+//!
+//! \note This call clears the source of all of the control status interrupts.
+//!
+//! \return Returns the status of the control interrupts for a USB controller.
+//
+//*****************************************************************************
+uint32_t
+USBIntStatusControl(uint32_t ui32Base)
+{
+    uint32_t ui32Status;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Get the general interrupt status, these bits go into the upper 8 bits
+    // of the returned value.
+    //
+    ui32Status = HWREGB(ui32Base + USB_O_IS);
+
+    //
+    // Add the power fault status.
+    //
+    if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF)
+    {
+        //
+        // Indicate a power fault was detected.
+        //
+        ui32Status |= USB_INTCTRL_POWER_FAULT;
+
+        //
+        // Clear the power fault interrupt.
+        //
+        HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF;
+    }
+
+    if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+    {
+        //
+        // Indicate an id detection.
+        //
+        ui32Status |= USB_INTCTRL_MODE_DETECT;
+
+        //
+        // Clear the id detection interrupt.
+        //
+        HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+    }
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Disables endpoint interrupts on a specified USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which endpoint interrupts to disable.
+//!
+//! This function disables endpoint interrupts for the USB controller specified
+//! by the \e ui32Base parameter.  The \e ui32Flags parameter specifies which
+//! endpoint interrupts to disable.  The flags passed in the \e ui32Flags
+//! parameters must be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // If any transmit interrupts were disabled, then write the transmit
+    // interrupt settings out to the hardware.
+    //
+    HWREGH(ui32Base + USB_O_TXIE) &=
+        ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
+
+    //
+    // If any receive interrupts were disabled, then write the receive
+    // interrupt settings out to the hardware.
+    //
+    HWREGH(ui32Base + USB_O_RXIE) &=
+        ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+          USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Enables endpoint interrupts on a specified USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which endpoint interrupts to enable.
+//!
+//! This function enables endpoint interrupts for the USB controller specified
+//! by the \e ui32Base parameter.  The \e ui32Flags parameter specifies which
+//! endpoint interrupts to enable.  The flags passed in the \e ui32Flags
+//! parameters must be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable any transmit endpoint interrupts.
+    //
+    HWREGH(ui32Base + USB_O_TXIE) |=
+        ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
+
+    //
+    // Enable any receive endpoint interrupts.
+    //
+    HWREGH(ui32Base + USB_O_RXIE) |=
+        ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+         USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Returns the endpoint interrupt status on a specified USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function reads endpoint interrupt status for a USB controller.  This
+//! call returns the current status for endpoint interrupts only, the control
+//! interrupt status is retrieved by calling USBIntStatusControl().  The bit
+//! values returned are compared against the \b USB_INTEP_* values.
+//! These values are grouped into classes for \b USB_INTEP_HOST_* and
+//! \b USB_INTEP_DEV_* values to handle both host and device modes with all
+//! endpoints.
+//!
+//! \note This call clears the source of all of the endpoint interrupts.
+//!
+//! \return Returns the status of the endpoint interrupts for a USB controller.
+//
+//*****************************************************************************
+uint32_t
+USBIntStatusEndpoint(uint32_t ui32Base)
+{
+    uint32_t ui32Status;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Get the transmit interrupt status.
+    //
+    ui32Status = HWREGH(ui32Base + USB_O_TXIS);
+    ui32Status |= (HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT);
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Returns the interrupt number for a specified USB module.
+//!
+//! \param ui32Base is the base address of the USB module.
+//!
+//! This function returns the interrupt number for the USB module with the base
+//! address passed in the \e ui32Base parameter.
+//!
+//! \return Returns the USB interrupt number or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_USBIntNumberGet(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    if(CLASS_IS_TM4C123)
+    {
+        ui32Int = INT_USB0_TM4C123;
+    }
+    else if(CLASS_IS_TM4C129)
+    {
+        ui32Int = INT_USB0_TM4C129;
+    }
+    else
+    {
+        ui32Int = 0;
+    }
+    return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param pfnHandler is a pointer to the function to be called when a USB
+//! interrupt occurs.
+//!
+//! This function registers the handler to be called when a USB interrupt
+//! occurs and enables the global USB interrupt in the interrupt controller.
+//! The specific desired USB interrupts must be enabled via a separate call to
+//! USBIntEnable().  It is the interrupt handler's responsibility to clear the
+//! interrupt sources via calls to USBIntStatusControl() and
+//! USBIntStatusEndpoint().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    ui32Int = _USBIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ui32Int, pfnHandler);
+
+    //
+    // Enable the USB interrupt.
+    //
+    IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function unregisters the interrupt handler.  This function also
+//! disables the USB interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering or
+//! unregistering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntUnregister(uint32_t ui32Base)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    ui32Int = _USBIntNumberGet(ui32Base);
+
+    ASSERT(ui32Int != 0);
+
+    //
+    // Disable the USB interrupt.
+    //
+    IntDisable(ui32Int);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Returns the current status of an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function returns the status of a specified endpoint.  If any of these
+//! status bits must be cleared, then the USBDevEndpointStatusClear() or the
+//! USBHostEndpointStatusClear() functions must be called.
+//!
+//! The following are the status flags for host mode:
+//!
+//! - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint.
+//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request.
+//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint.
+//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN
+//!   endpoint in Isochronous mode.
+//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than
+//!   the specified timeout period.
+//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN
+//!   endpoint.
+//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full.
+//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint.
+//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than
+//!   the specified timeout period.
+//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT
+//!   request.
+//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint.
+//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this
+//!   OUT endpoint.
+//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty.
+//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not
+//!   completed.
+//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the
+//!   specified timeout period.
+//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on
+//!   endpoint zero.
+//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an
+//!   IN transaction.
+//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN
+//!   transaction.
+//!
+//! The following are the status flags for device mode:
+//!
+//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint.
+//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT
+//!   endpoint.
+//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO.
+//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full.
+//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT
+//!   endpoint's FIFO.
+//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come.
+//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint.
+//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no
+//!   data was ready.
+//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty.
+//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not
+//!   completed.
+//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End
+//!   condition was sent.
+//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero.
+//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not
+//!   completed.
+//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint
+//!   zero's OUT FIFO.
+//!
+//! \return The current status flags for the endpoint depending on mode.
+//
+//*****************************************************************************
+uint32_t
+USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+    uint32_t ui32Status;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Get the TX portion of the endpoint status.
+    //
+    ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1);
+
+    //
+    // Get the RX portion of the endpoint status.
+    //
+    ui32Status |=
+        ((HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) <<
+         USB_RX_EPSTATUS_SHIFT);
+
+    //
+    // Return the endpoint status.
+    //
+    return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags are the status bits that are cleared.
+//!
+//! This function clears the status of any bits that are passed in the
+//! \e ui32Flags parameter.  The \e ui32Flags parameter can take the value
+//! returned from the USBEndpointStatus() call.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+                           uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Clear the specified flags for the endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags;
+    }
+    else
+    {
+        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~ui32Flags;
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT);
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags are the status bits that are cleared.
+//!
+//! This function clears the status of any bits that are passed in the
+//! \e ui32Flags parameter.  The \e ui32Flags parameter can take the value
+//! returned from the USBEndpointStatus() call.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+                          uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // If this is endpoint 0, then the bits have different meaning and map
+    // into the TX memory location.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
+        //
+        if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY)
+        {
+            HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
+        }
+
+        //
+        // Set the serviced Setup End bit to clear the SetupEnd status.
+        //
+        if(ui32Flags & USB_DEV_EP0_SETUP_END)
+        {
+            HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
+        }
+
+        //
+        // Clear the Sent Stall status flag.
+        //
+        if(ui32Flags & USB_DEV_EP0_SENT_STALL)
+        {
+            HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
+        }
+    }
+    else
+    {
+        //
+        // Clear out any TX flags that were passed in.  Only
+        // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared.
+        //
+        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
+
+        //
+        // Clear out valid RX flags that were passed in.  Only
+        // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
+        // must be cleared.
+        //
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
+                            USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the value data toggle on an endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to reset the data toggle.
+//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1.
+//! \param ui32Flags specifies whether to set the IN or OUT endpoint.
+//!
+//! This function is used to force the state of the data toggle in host mode.
+//! If the value passed in the \e bDataToggle parameter is \b false, then the
+//! data toggle is set to the DATA0 state, and if it is \b true it is set to
+//! the DATA1 state.  The \e ui32Flags parameter can be \b USB_EP_HOST_IN or
+//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint.  The
+//! \e ui32Flags parameter is ignored for endpoint zero.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint,
+                          bool bDataToggle, uint32_t ui32Flags)
+{
+    uint32_t ui32DataToggle;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // The data toggle defaults to DATA0.
+    //
+    ui32DataToggle = 0;
+
+    //
+    // See if the data toggle must be set to DATA1.
+    //
+    if(bDataToggle)
+    {
+        //
+        // Select the data toggle bit based on the endpoint.
+        //
+        if(ui32Endpoint == USB_EP_0)
+        {
+            ui32DataToggle = USB_CSRH0_DT;
+        }
+        else if(ui32Flags == USB_EP_HOST_IN)
+        {
+            ui32DataToggle = USB_RXCSRH1_DT;
+        }
+        else
+        {
+            ui32DataToggle = USB_TXCSRH1_DT;
+        }
+    }
+
+    //
+    // Set the data toggle based on the endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Set the write enable and the bit value for endpoint zero.
+        //
+        HWREGB(ui32Base + USB_O_CSRH0) =
+            ((HWREGB(ui32Base + USB_O_CSRH0) &
+              ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
+             (ui32DataToggle | USB_CSRH0_DTWE));
+    }
+    else if(ui32Flags == USB_EP_HOST_IN)
+    {
+        //
+        // Set the Write enable and the bit value for an IN endpoint.
+        //
+        HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) =
+            ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) &
+              ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
+             (ui32DataToggle | USB_RXCSRH1_DTWE));
+    }
+    else
+    {
+        //
+        // Set the Write enable and the bit value for an OUT endpoint.
+        //
+        HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) =
+            ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) &
+              ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
+             (ui32DataToggle | USB_TXCSRH1_DTWE));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the data toggle on an endpoint to zero.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to reset the data toggle.
+//! \param ui32Flags specifies whether to access the IN or OUT endpoint.
+//!
+//! This function causes the USB controller to clear the data toggle for an
+//! endpoint.  This call is not valid for endpoint zero and can be made with
+//! host or device controllers.
+//!
+//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+                           uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+           (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the transmit or receive data toggle must be cleared.
+    //
+    if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+    {
+        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+            USB_TXCSRL1_CLRDT;
+    }
+    else
+    {
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+            USB_RXCSRL1_CLRDT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables or disables ping tokens for an endpoint using high-speed control
+//! transfers in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to enable/disable ping tokens.
+//! \param bEnable specifies whether enable or disable ping tokens.
+//!
+//! This function configures the USB controller to either send or not send ping
+//! tokens during the data and status phase of high speed control transfers.
+//! The only supported value for \e ui32Endpoint is \b USB_EP_0 because all
+//! control transfers are handled using this endpoint.  If the \e bEnable is
+//! \b true then ping tokens are enabled, if \b false then ping tokens are
+//! disabled.  This must be used if the controller must support
+//! communications with devices that do not support ping tokens in high speed
+//! mode.
+//!
+//! \b Example: Disable ping transactions in host mode on endpoint 0.
+//!
+//! \verbatim
+//! //
+//! // Disable ping transaction on endpoint 0.
+//! //
+//! USBHostEndpointPing(USB0_BASE, USB_EP_0, false);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, bool bEnable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0));
+
+    //
+    // Handle the endpoint 0 case separately.
+    //
+    if(bEnable)
+    {
+        HWREGB(USB0_BASE + USB_O_CSRH0) &= ~USB_CSRH0_DISPING;
+    }
+    else
+    {
+        HWREGB(USB0_BASE + USB_O_CSRH0) |= USB_CSRH0_DISPING;
+    }
+}
+
+//*****************************************************************************
+//
+//! Stalls the specified endpoint in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to stall.
+//! \param ui32Flags specifies whether to stall the IN or OUT endpoint.
+//!
+//! This function causes the endpoint number passed in to go into a stall
+//! condition.  If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the
+//! stall is issued on the IN portion of this endpoint.  If the \e ui32Flags
+//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion
+//! of this endpoint.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint,
+                    uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Determine how to stall this endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Perform a stall on endpoint zero.
+        //
+        HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC;
+    }
+    else if(ui32Flags == USB_EP_DEV_IN)
+    {
+        //
+        // Perform a stall on an IN endpoint.
+        //
+        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+            USB_TXCSRL1_STALL;
+    }
+    else
+    {
+        //
+        // Perform a stall on an OUT endpoint.
+        //
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+            USB_RXCSRL1_STALL;
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the stall condition on the specified endpoint in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies which endpoint to remove the stall condition.
+//! \param ui32Flags specifies whether to remove the stall condition from the
+//! IN or the OUT portion of this endpoint.
+//!
+//! This function causes the endpoint number passed in to exit the stall
+//! condition.  If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the
+//! stall is cleared on the IN portion of this endpoint.  If the \e ui32Flags
+//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+                         uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+    ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0);
+
+    //
+    // Determine how to clear the stall on this endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Clear the stall on endpoint zero.
+        //
+        HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
+    }
+    else if(ui32Flags == USB_EP_DEV_IN)
+    {
+        //
+        // Clear the stall on an IN endpoint.
+        //
+        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
+
+        //
+        // Reset the data toggle.
+        //
+        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+            USB_TXCSRL1_CLRDT;
+    }
+    else
+    {
+        //
+        // Clear the stall on an OUT endpoint.
+        //
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
+
+        //
+        // Reset the data toggle.
+        //
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+            USB_RXCSRL1_CLRDT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Connects the USB controller to the bus in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function causes the soft connect feature of the USB controller to
+//! be enabled.  Call USBDevDisconnect() to remove the USB device from the bus.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevConnect(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable connection to the USB bus.
+    //
+    HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN;
+}
+
+//*****************************************************************************
+//
+//! Removes the USB controller from the bus in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function causes the soft connect feature of the USB controller to
+//! remove the device from the USB bus.  A call to USBDevConnect() is needed to
+//! reconnect to the bus.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevDisconnect(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Disable connection to the USB bus.
+    //
+    HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
+}
+
+//*****************************************************************************
+//
+//! Sets the address in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Address is the address to use for a device.
+//!
+//! This function configures the device address on the USB bus.  This address
+//! was likely received via a SET ADDRESS command from the host controller.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Set the function address in the correct location.
+    //
+    HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address;
+}
+
+//*****************************************************************************
+//
+//! Returns the current device address in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current device address.  This address was set
+//! by a call to USBDevAddrSet().
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return The current device address.
+//
+//*****************************************************************************
+uint32_t
+USBDevAddrGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Return the function address.
+    //
+    return(HWREGB(ui32Base + USB_O_FADDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the base configuration for a host endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32MaxPayload is the maximum payload for this endpoint.
+//! \param ui32NAKPollInterval is the either the NAK timeout limit or the
+//! polling interval, depending on the type of endpoint.
+//! \param ui32TargetEndpoint is the endpoint that the host endpoint is
+//! targeting.
+//! \param ui32Flags are used to configure other endpoint settings.
+//!
+//! This function sets the basic configuration for the transmit or receive
+//! portion of an endpoint in host mode.  The \e ui32Flags parameter determines
+//! some of the configuration while the other parameters provide the rest.  The
+//! \e ui32Flags parameter determines whether this is an IN endpoint
+//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint
+//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed
+//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint
+//! (\b USB_EP_SPEED_LOW).
+//!
+//! The \b USB_EP_MODE_ flags control the type of the endpoint.
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \e ui32NAKPollInterval parameter has different meanings based on the
+//! \b USB_EP_MODE value and whether or not this call is being made for
+//! endpoint zero or another endpoint.  For endpoint zero or any Bulk
+//! endpoints, this value always indicates the number of frames to allow a
+//! device to NAK before considering it a timeout.  If this endpoint is an
+//! isochronous or interrupt endpoint, this value is the polling interval for
+//! this endpoint.
+//!
+//! For interrupt endpoints, the polling interval is the number of frames
+//! between interrupt IN requests to an endpoint and has a range of 1 to 255.
+//! For isochronous endpoints this value represents a polling interval of
+//! 2 ^ (\e ui32NAKPollInterval - 1) frames.  When used as a NAK timeout, the
+//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1)
+//! frames before issuing a time out.
+//!
+//! There are two special time out values that can be specified when setting
+//! the \e ui32NAKPollInterval value.  The first is \b MAX_NAK_LIMIT, which is
+//! the maximum value that can be passed in this variable.  The other is
+//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the
+//! number of NAKs.
+//!
+//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the
+//! endpoint data FIFOs.  The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used.  See the ``Using USB
+//! with the uDMA Controller'' or the ''Using the integrated USB DMA
+//! Controller'' section for more information on DMA configuration depending
+//! on the type of DMA that is supported by the USB controller.
+//!
+//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit
+//! is specified to cause the transmission of data on the USB bus to start
+//! as soon as the number of bytes specified by \e ui32MaxPayload has been
+//! written into the OUT FIFO for this endpoint.
+//!
+//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST
+//! bit can be specified to trigger the request for more data once the FIFO has
+//! been drained enough to fit \e ui32MaxPayload bytes.  The
+//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag
+//! automatically once the data has been read from the FIFO.  If this option is
+//! not used, this flag must be manually cleared via a call to
+//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear().
+//!
+//! For interrupt endpoints in low or full speed mode, the polling interval
+//! (\e ui32NAKPollInterval) is the number of frames between interrupt IN
+//! requests to an endpoint and has a range of 1 to 255.  For interrupt
+//! endpoints in high speed mode the polling interval is
+//! 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests
+//! to an endpoint and has a range of 1 to 16.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint,
+                      uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval,
+                      uint32_t ui32TargetEndpoint, uint32_t ui32Flags)
+{
+    uint32_t ui32Register;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+    ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT);
+
+    //
+    // Endpoint zero is configured differently than the other endpoints, so see
+    // if this is endpoint zero.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Set the NAK timeout.
+        //
+        HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval;
+
+        //
+        // Set the transfer type information.
+        //
+        //
+        // Set the speed of this endpoint.
+        //
+        if(ui32Flags & USB_EP_SPEED_HIGH)
+        {
+            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH;
+        }
+        else if(ui32Flags & USB_EP_SPEED_FULL)
+        {
+            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL;
+        }
+        else
+        {
+            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW;
+        }
+    }
+    else
+    {
+        //
+        // Start with the target endpoint.
+        //
+        ui32Register = ui32TargetEndpoint;
+
+        //
+        // Set the speed for the device using this endpoint.
+        //
+        if(ui32Flags & USB_EP_SPEED_HIGH)
+        {
+            ui32Register |= USB_TXTYPE1_SPEED_HIGH;
+        }
+        else if(ui32Flags & USB_EP_SPEED_FULL)
+        {
+            ui32Register |= USB_TXTYPE1_SPEED_FULL;
+        }
+        else
+        {
+            ui32Register |= USB_TXTYPE1_SPEED_LOW;
+        }
+
+        //
+        // Set the protocol for the device using this endpoint.
+        //
+        switch(ui32Flags & USB_EP_MODE_MASK)
+        {
+            //
+            // The bulk protocol is being used.
+            //
+            case USB_EP_MODE_BULK:
+            {
+                ui32Register |= USB_TXTYPE1_PROTO_BULK;
+                break;
+            }
+
+            //
+            // The isochronous protocol is being used.
+            //
+            case USB_EP_MODE_ISOC:
+            {
+                ui32Register |= USB_TXTYPE1_PROTO_ISOC;
+                break;
+            }
+
+            //
+            // The interrupt protocol is being used.
+            //
+            case USB_EP_MODE_INT:
+            {
+                ui32Register |= USB_TXTYPE1_PROTO_INT;
+                break;
+            }
+
+            //
+            // The control protocol is being used.
+            //
+            case USB_EP_MODE_CTRL:
+            {
+                ui32Register |= USB_TXTYPE1_PROTO_CTRL;
+                break;
+            }
+        }
+
+        //
+        // See if the transmit or receive endpoint is being configured.
+        //
+        if(ui32Flags & USB_EP_HOST_OUT)
+        {
+            //
+            // Set the transfer type information.
+            //
+            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) =
+                ui32Register;
+
+            //
+            // Set the NAK timeout or polling interval.
+            //
+            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) =
+                ui32NAKPollInterval;
+
+            //
+            // Set the Maximum Payload per transaction.
+            //
+            HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) =
+                ui32MaxPayload;
+
+            //
+            // Set the transmit control value to zero.
+            //
+            ui32Register = 0;
+
+            //
+            // Allow auto setting of TxPktRdy when max packet size has been
+            // loaded into the FIFO.
+            //
+            if(ui32Flags & USB_EP_AUTO_SET)
+            {
+                ui32Register |= USB_TXCSRH1_AUTOSET;
+            }
+
+            //
+            // Configure the DMA Mode.
+            //
+            if(ui32Flags & USB_EP_DMA_MODE_1)
+            {
+                ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+            }
+            else if(ui32Flags & USB_EP_DMA_MODE_0)
+            {
+                ui32Register |= USB_TXCSRH1_DMAEN;
+            }
+
+            //
+            // Write out the transmit control value.
+            //
+            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
+                (uint8_t)ui32Register;
+        }
+        else
+        {
+            //
+            // Set the transfer type information.
+            //
+            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) =
+                ui32Register;
+
+            //
+            // Set the NAK timeout or polling interval.
+            //
+            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) =
+                ui32NAKPollInterval;
+
+            //
+            // Set the Maximum Payload per transaction.
+            //
+            HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) =
+                ui32MaxPayload;
+
+            //
+            // Set the receive control value to zero.
+            //
+            ui32Register = 0;
+
+            //
+            // Allow auto clearing of RxPktRdy when packet of size max packet
+            // has been unloaded from the FIFO.
+            //
+            if(ui32Flags & USB_EP_AUTO_CLEAR)
+            {
+                ui32Register |= USB_RXCSRH1_AUTOCL;
+            }
+
+            //
+            // Allow auto generation of DMA requests.
+            //
+            if(ui32Flags & USB_EP_AUTO_REQUEST)
+            {
+                ui32Register |= USB_RXCSRH1_AUTORQ;
+            }
+
+            //
+            // Configure the DMA Mode.
+            //
+            if(ui32Flags & USB_EP_DMA_MODE_1)
+            {
+                ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+            }
+            else if(ui32Flags & USB_EP_DMA_MODE_0)
+            {
+                ui32Register |= USB_RXCSRH1_DMAEN;
+            }
+
+            //
+            // Write out the receive control value.
+            //
+            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
+                (uint8_t)ui32Register;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Changes the speed of the connection for a host endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags are used to configure other endpoint settings.
+//!
+//! This function sets the USB speed for an IN or OUT endpoint in host mode.
+//! The \e ui32Flags parameter specifies the speed using one of the following
+//! values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH.
+//! The \e ui32Flags parameter also specifies which direction is set by
+//! adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT.
+//! All other flags are ignored.  This function is typically only used for
+//! endpoint 0, but could be used with other endpoints as well.
+//!
+//! \b Example: Set host transactions on endpoint 0 to full speed..
+//!
+//! \verbatim
+//! //
+//! // Set host endpoint 0 transactions to full speed.
+//! //
+//! USBHostEndpointSpeed(USB0_BASE, USB_EP_0, USB_EP_SPEED_FULL);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint,
+                     uint32_t ui32Flags)
+{
+    uint32_t ui32Reg;
+    uint32_t ui32Speed;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Create the register speed value.
+    //
+    if(ui32Flags & USB_EP_SPEED_HIGH)
+    {
+        ui32Speed = USB_TYPE0_SPEED_HIGH;
+    }
+    else if(ui32Flags & USB_EP_SPEED_FULL)
+    {
+        ui32Speed = USB_TYPE0_SPEED_FULL;
+    }
+    else
+    {
+        ui32Speed = USB_TYPE0_SPEED_LOW;
+    }
+
+    //
+    // Endpoint 0 is handled differently as it is bi-directional.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        HWREGB(ui32Base + USB_O_TYPE0) = ui32Speed;
+    }
+    else if(ui32Flags & USB_EP_HOST_OUT)
+    {
+        //
+        // Clear the current speed and set the new speed.
+        //
+        ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) &
+                   ~(USB_TXTYPE1_SPEED_M));
+        ui32Reg |= ui32Speed;
+
+        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) |= ui32Reg;
+    }
+    else
+    {
+        //
+        // Clear the current speed and set the new speed.
+        //
+        ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) &
+                   ~(USB_RXTYPE1_SPEED_M));
+        ui32Reg |= ui32Speed;
+
+        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) |= ui32Reg;
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32MaxPacketSize is the maximum packet size for this endpoint.
+//! \param ui32Flags are used to configure other endpoint settings.
+//!
+//! This function sets the basic configuration for an endpoint in device mode.
+//! Endpoint zero does not have a dynamic configuration, so this function
+//! must not be called for endpoint zero.  The \e ui32Flags parameter
+//! determines some of the configuration while the other parameters provide the
+//! rest.
+//!
+//! The \b USB_EP_MODE_ flags define what the type is for the specified endpoint.
+//!
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the
+//! endpoint data FIFOs.  The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used.  See the ``Using USB
+//! with the uDMA Controller'' or the ''Using the integrated USB DMA
+//! Controller'' section for more information on DMA configuration depending
+//! on the type of DMA that is supported by the USB controller.
+//!
+//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be
+//! specified to cause the automatic transmission of data on the USB bus as
+//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for
+//! this endpoint.  This option is commonly used with DMA (both on devices
+//! with integrated USB DMA as well as those that use uDMA) as no interaction
+//! is required to start the transmission of data.
+//!
+//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is
+//! specified to trigger the request for more data once the FIFO has been
+//! drained enough to receive \e ui32MaxPacketSize more bytes of data.  Also
+//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the
+//! data packet ready flag automatically once the data has been read from the
+//! FIFO.  If this option is not used, this flag must be manually cleared via a
+//! call to USBDevEndpointStatusClear().  Both of these settings can be used to
+//! remove the need for extra calls when using the controller with DMA.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                        uint32_t ui32MaxPacketSize, uint32_t ui32Flags)
+{
+    uint32_t ui32Register;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+           (ui32Endpoint == USB_EP_7));
+
+    //
+    // Determine if a transmit or receive endpoint is being configured.
+    //
+    if(ui32Flags & USB_EP_DEV_IN)
+    {
+        //
+        // Set the maximum packet size.
+        //
+        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) =
+            ui32MaxPacketSize;
+
+        //
+        // The transmit control value is zero unless options are enabled.
+        //
+        ui32Register = 0;
+
+        //
+        // Allow auto setting of TxPktRdy when max packet size has been loaded
+        // into the FIFO.
+        //
+        if(ui32Flags & USB_EP_AUTO_SET)
+        {
+            ui32Register |= USB_TXCSRH1_AUTOSET;
+        }
+
+        //
+        // Configure the DMA mode.
+        //
+        if(ui32Flags & USB_EP_DMA_MODE_1)
+        {
+            ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+        }
+        else if(ui32Flags & USB_EP_DMA_MODE_0)
+        {
+            ui32Register |= USB_TXCSRH1_DMAEN;
+        }
+
+        //
+        // Enable isochronous mode if requested.
+        //
+        if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+        {
+            ui32Register |= USB_TXCSRH1_ISO;
+        }
+
+        //
+        // Write the transmit control value.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
+            (uint8_t)ui32Register;
+
+        //
+        // Reset the Data toggle to zero.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) =
+            USB_TXCSRL1_CLRDT;
+    }
+    else
+    {
+        //
+        // Set the MaxPacketSize.
+        //
+        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) =
+            ui32MaxPacketSize;
+
+        //
+        // The receive control value is zero unless options are enabled.
+        //
+        ui32Register = 0;
+
+        //
+        // Allow auto clearing of RxPktRdy when packet of size max packet
+        // has been unloaded from the FIFO.
+        //
+        if(ui32Flags & USB_EP_AUTO_CLEAR)
+        {
+            ui32Register = USB_RXCSRH1_AUTOCL;
+        }
+
+        //
+        // Configure the DMA mode.
+        //
+        if(ui32Flags & USB_EP_DMA_MODE_1)
+        {
+            ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+        }
+        else if(ui32Flags & USB_EP_DMA_MODE_0)
+        {
+            ui32Register |= USB_RXCSRH1_DMAEN;
+        }
+
+        //
+        // If requested, disable NYET responses for high-speed bulk and
+        // interrupt endpoints.
+        //
+        if(ui32Flags & USB_EP_DIS_NYET)
+        {
+            ui32Register |= USB_RXCSRH1_DISNYET;
+        }
+
+        //
+        // Enable isochronous mode if requested.
+        //
+        if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+        {
+            ui32Register |= USB_RXCSRH1_ISO;
+        }
+
+        //
+        // Write the receive control value.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
+            (uint8_t)ui32Register;
+
+        //
+        // Reset the Data toggle to zero.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) =
+            USB_RXCSRL1_CLRDT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui32MaxPacketSize is a pointer which is written with the maximum
+//! packet size for this endpoint.
+//! \param pui32Flags is a pointer which is written with the current endpoint
+//! settings.  On entry to the function, this pointer must contain either
+//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT
+//! endpoint is to be queried.
+//!
+//! This function returns the basic configuration for an endpoint in device
+//! mode.  The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are
+//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed
+//! to USBDevEndpointConfigSet() for this endpoint.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                        uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags)
+{
+    uint32_t ui32Register;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(pui32MaxPacketSize && pui32Flags);
+    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+           (ui32Endpoint == USB_EP_7));
+
+    //
+    // Determine if a transmit or receive endpoint is being queried.
+    //
+    if(*pui32Flags & USB_EP_DEV_IN)
+    {
+        //
+        // Clear the flags other than the direction bit.
+        //
+        *pui32Flags = USB_EP_DEV_IN;
+
+        //
+        // Get the maximum packet size.
+        //
+        *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base +
+                                               EP_OFFSET(ui32Endpoint) +
+                                               USB_O_TXMAXP1);
+
+        //
+        // Get the current transmit control register value.
+        //
+        ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) +
+                                        USB_O_TXCSRH1);
+
+        //
+        // Are we allowing auto setting of TxPktRdy when max packet size has
+        // been loaded into the FIFO?
+        //
+        if(ui32Register & USB_TXCSRH1_AUTOSET)
+        {
+            *pui32Flags |= USB_EP_AUTO_SET;
+        }
+
+        //
+        // Get the DMA mode.
+        //
+        if(ui32Register & USB_TXCSRH1_DMAEN)
+        {
+            if(ui32Register & USB_TXCSRH1_DMAMOD)
+            {
+                *pui32Flags |= USB_EP_DMA_MODE_1;
+            }
+            else
+            {
+                *pui32Flags |= USB_EP_DMA_MODE_0;
+            }
+        }
+
+        //
+        // Are we in isochronous mode?
+        //
+        if(ui32Register & USB_TXCSRH1_ISO)
+        {
+            *pui32Flags |= USB_EP_MODE_ISOC;
+        }
+        else
+        {
+            //
+            // The hardware doesn't differentiate between bulk, interrupt
+            // and control mode for the endpoint so we just set something
+            // that isn't isochronous.  This protocol ensures that anyone
+            // modifying the returned flags in preparation for a call to
+            // USBDevEndpointConfigSet do not see an unexpected mode change.
+            // If they decode the returned mode, however, they may be in for
+            // a surprise.
+            //
+            *pui32Flags |= USB_EP_MODE_BULK;
+        }
+    }
+    else
+    {
+        //
+        // Clear the flags other than the direction bit.
+        //
+        *pui32Flags = USB_EP_DEV_OUT;
+
+        //
+        // Get the MaxPacketSize.
+        //
+        *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base +
+                                               EP_OFFSET(ui32Endpoint) +
+                                               USB_O_RXMAXP1);
+
+        //
+        // Get the current receive control register value.
+        //
+        ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) +
+                                        USB_O_RXCSRH1);
+
+        //
+        // Are we allowing auto clearing of RxPktRdy when packet of size max
+        // packet has been unloaded from the FIFO?
+        //
+        if(ui32Register & USB_RXCSRH1_AUTOCL)
+        {
+            *pui32Flags |= USB_EP_AUTO_CLEAR;
+        }
+
+        //
+        // Get the DMA mode.
+        //
+        if(ui32Register & USB_RXCSRH1_DMAEN)
+        {
+            if(ui32Register & USB_RXCSRH1_DMAMOD)
+            {
+                *pui32Flags |= USB_EP_DMA_MODE_1;
+            }
+            else
+            {
+                *pui32Flags |= USB_EP_DMA_MODE_0;
+            }
+        }
+
+        //
+        // Are we in isochronous mode?
+        //
+        if(ui32Register & USB_RXCSRH1_ISO)
+        {
+            *pui32Flags |= USB_EP_MODE_ISOC;
+        }
+        else
+        {
+            //
+            // The hardware doesn't differentiate between bulk, interrupt
+            // and control mode for the endpoint so we just set something
+            // that isn't isochronous.  This protocol ensures that anyone
+            // modifying the returned flags in preparation for a call to
+            // USBDevEndpointConfigSet do not see an unexpected mode change.
+            // If they decode the returned mode, however, they may be in for
+            // a surprise.
+            //
+            *pui32Flags |= USB_EP_MODE_BULK;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32FIFOAddress is the starting address for the FIFO.
+//! \param ui32FIFOSize is the size of the FIFO specified by one of the
+//! \b USB_FIFO_SZ_ values.
+//! \param ui32Flags specifies what information to set in the FIFO
+//! configuration.
+//!
+//! This function configures the starting FIFO RAM address and size of the FIFO
+//! for a specified endpoint.  Endpoint zero does not have a dynamically
+//! configurable FIFO, so this function must not be called for endpoint zero.
+//! The \e ui32FIFOSize parameter must be one of the values in the
+//! \b USB_FIFO_SZ_ values.
+//!
+//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly
+//! indicates the starting address in the USB controller's FIFO RAM.  For
+//! example, a value of 64 indicates that the FIFO starts 64 bytes into
+//! the USB controller's FIFO memory.  The \e ui32Flags value specifies whether
+//! the endpoint's OUT or IN FIFO must be configured.  If in host mode, use
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use
+//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                 uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
+                 uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+           (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the transmit or receive FIFO is being configured.
+    //
+    if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+    {
+        //
+        // Set the transmit FIFO location and size for this endpoint.
+        //
+        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ,
+                       ui32FIFOSize, 1);
+        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD,
+                       ui32FIFOAddress >> 3, 2);
+    }
+    else
+    {
+        //
+        // Set the receive FIFO location and size for this endpoint.
+        //
+        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ,
+                       ui32FIFOSize, 1);
+        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD,
+                       ui32FIFOAddress >> 3, 2);
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the FIFO configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui32FIFOAddress is the starting address for the FIFO.
+//! \param pui32FIFOSize is the size of the FIFO as specified by one of the
+//! \b USB_FIFO_SZ_ values.
+//! \param ui32Flags specifies what information to retrieve from the FIFO
+//! configuration.
+//!
+//! This function returns the starting address and size of the FIFO for a
+//! specified endpoint.  Endpoint zero does not have a dynamically configurable
+//! FIFO, so this function must not be called for endpoint zero.  The
+//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must
+//! be read.  If in host mode, the \e ui32Flags parameter must be
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the
+//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or
+//! \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                 uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize,
+                 uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+           (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the transmit or receive FIFO is being configured.
+    //
+    if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+    {
+        //
+        // Get the transmit FIFO location and size for this endpoint.
+        //
+        *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4,
+                                           (uint32_t)USB_O_TXFIFOADD,
+                                           2)) << 3;
+        *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4,
+                                       (uint32_t)USB_O_TXFIFOSZ, 1);
+    }
+    else
+    {
+        //
+        // Get the receive FIFO location and size for this endpoint.
+        //
+        *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4,
+                                           (uint32_t)USB_O_RXFIFOADD,
+                                           2)) << 3;
+        *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4,
+                                       (uint32_t)USB_O_RXFIFOSZ, 1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Configure the DMA settings for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Config specifies the configuration options for an endpoint.
+//!
+//! This function configures the DMA settings for a specified endpoint without
+//! changing other options that may already be configured.  In order for the
+//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be
+//! called before starting the DMA transfer.  The configuration
+//! options are passed in the \e ui32Config parameter and can have the values
+//! described below.
+//!
+//! One of the following values to specify direction:
+//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with
+//!   DMA transfers from memory to the USB controller.
+//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with
+//!   DMA transfers from the USB controller to memory.
+//!
+//! One of the following values:
+//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for
+//!   transfers that do not span multiple packets or when interrupts are
+//!   required for each packet.
+//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for
+//!   transfers that span multiple packets and do not require interrupts
+//!   between packets.
+//!
+//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN:
+//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers
+//!   to automatically be sent when a full packet is loaded into a FIFO.
+//!   This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go
+//!   out when the FIFO becomes full and the DMA has more data to send.
+//!
+//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT:
+//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA
+//!   transfers to automatically be acknowledged as they are received.  This is
+//!   needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to
+//!   be received and acknowledged when the FIFO is emptied by the DMA
+//!   transfer.
+//!
+//! Values only used with \b USB_EP_HOST_IN:
+//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA
+//!   transfers to automatically request a new IN transaction when the
+//!   previous transfer has emptied the FIFO.  This is typically used in
+//!   conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers
+//!   can continue without interrupting the main processor.
+//!
+//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge
+//! request and automatically generate a new IN request in host mode.
+//!
+//! \verbatim
+//! //
+//! // Configure endpoint 1 for receiving multiple packets using DMA.
+//! //
+//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN |
+//!                                              USB_EP_DMA_MODE_1 |
+//!                                              USB_EP_AUTO_CLEAR |
+//!                                              USB_EP_AUTO_REQUEST);
+//! \endverbatim
+//!
+//! \b Example: Set endpoint 2 transmit endpoint to automatically send each
+//! packet in host mode when spanning multiple packets.
+//!
+//! \verbatim
+//! //
+//! // Configure endpoint 1 for transmitting multiple packets using DMA.
+//! //
+//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT |
+//!                                              USB_EP_DMA_MODE_1 |
+//!                                              USB_EP_AUTO_SET);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                        uint32_t ui32Config)
+{
+    uint32_t ui32NewConfig;
+
+    if(ui32Config & USB_EP_HOST_OUT)
+    {
+        //
+        // Clear mode and DMA enable.
+        //
+        ui32NewConfig =
+            (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &
+             ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET));
+
+        if(ui32Config & USB_EP_DMA_MODE_1)
+        {
+            ui32NewConfig |= USB_TXCSRH1_DMAMOD;
+        }
+
+        if(ui32Config & USB_EP_AUTO_SET)
+        {
+            ui32NewConfig |= USB_TXCSRH1_AUTOSET;
+        }
+
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
+            ui32NewConfig;
+    }
+    else
+    {
+        ui32NewConfig =
+            (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &
+             ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD));
+
+        if(ui32Config & USB_EP_DMA_MODE_1)
+        {
+            ui32NewConfig |= USB_RXCSRH1_DMAMOD;
+        }
+
+        if(ui32Config & USB_EP_AUTO_CLEAR)
+        {
+            ui32NewConfig |= USB_RXCSRH1_AUTOCL;
+        }
+        if(ui32Config & USB_EP_AUTO_REQUEST)
+        {
+            ui32NewConfig |= USB_RXCSRH1_AUTORQ;
+        }
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
+            ui32NewConfig;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enable DMA on a specified endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags specifies which direction and what mode to use when
+//! enabling DMA.
+//!
+//! This function enables DMA on a specified endpoint and configures the mode
+//! according to the values in the \e ui32Flags parameter.  The \e ui32Flags
+//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set.  Once this
+//! function is called the only DMA or error interrupts are generated by the
+//! USB controller.
+//!
+//! \note If this function is called when an endpoint is configured in DMA
+//! mode 0 the USB controller does not generate an interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint,
+                     uint32_t ui32Flags)
+{
+    //
+    // See if the transmit DMA is being enabled.
+    //
+    if(ui32Flags & USB_EP_DEV_IN)
+    {
+        //
+        // Enable DMA on the transmit endpoint.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |=
+            USB_TXCSRH1_DMAEN;
+    }
+    else
+    {
+        //
+        // Enable DMA on the receive endpoint.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |=
+            USB_RXCSRH1_DMAEN;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disable DMA on a specified endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags specifies which direction to disable.
+//!
+//! This function disables DMA on a specified endpoint to allow non-DMA USB
+//! transactions to generate interrupts normally.  The \e ui32Flags parameter
+//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint,
+                      uint32_t ui32Flags)
+{
+    //
+    // If this was a request to disable DMA on the IN portion of the endpoint
+    // then handle it.
+    //
+    if(ui32Flags & USB_EP_DEV_IN)
+    {
+        //
+        // Just disable DMA leave the mode setting.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &=
+            ~USB_TXCSRH1_DMAEN;
+    }
+    else
+    {
+        //
+        // Just disable DMA leave the mode setting.
+        //
+        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &=
+            ~USB_RXCSRH1_DMAEN;
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines the number of bytes of data available in a specified endpoint's
+//! FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function returns the number of bytes of data currently available in
+//! the FIFO for the specified receive (OUT) endpoint.  It may be used prior to
+//! calling USBEndpointDataGet() to determine the size of buffer required to
+//! hold the newly-received packet.
+//!
+//! \return This call returns the number of bytes available in a specified endpoint
+//! FIFO.
+//
+//*****************************************************************************
+uint32_t
+USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+    uint32_t ui32Register;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Get the address of the receive status register to use, based on the
+    // endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        ui32Register = USB_O_CSRL0;
+    }
+    else
+    {
+        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+    }
+
+    //
+    // Is there a packet ready in the FIFO?
+    //
+    if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0)
+    {
+        return(0);
+    }
+
+    //
+    // Return the byte count in the FIFO.
+    //
+    return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint));
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the specified endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui8Data is a pointer to the data area used to return the data from
+//! the FIFO.
+//! \param pui32Size is initially the size of the buffer passed into this call
+//! via the \e pui8Data parameter.  It is set to the amount of data returned in
+//! the buffer.
+//!
+//! This function returns the data from the FIFO for the specified endpoint.
+//! The \e pui32Size parameter indicates the size of the buffer passed in
+//! the \e pui32Data parameter.  The data in the \e pui32Size parameter is
+//! changed to match the amount of data returned in the \e pui8Data parameter.
+//! If a zero-byte packet is received, this call does not return an error but
+//! instead just returns a zero in the \e pui32Size parameter.  The only error
+//! case occurs when there is no data packet available.
+//!
+//! \return This call returns 0, or -1 if no packet was received.
+//
+//*****************************************************************************
+int32_t
+USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                   uint8_t *pui8Data, uint32_t *pui32Size)
+{
+    uint32_t ui32Register, ui32ByteCount, ui32FIFO;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Get the address of the receive status register to use, based on the
+    // endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        ui32Register = USB_O_CSRL0;
+    }
+    else
+    {
+        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+    }
+
+    //
+    // Don't allow reading of data if the RxPktRdy bit is not set.
+    //
+    if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0)
+    {
+        //
+        // Can't read the data because none is available.
+        //
+        *pui32Size = 0;
+
+        //
+        // Return a failure since there is no data to read.
+        //
+        return(-1);
+    }
+
+    //
+    // Get the byte count in the FIFO.
+    //
+    ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint);
+
+    //
+    // Determine how many bytes are copied.
+    //
+    ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size;
+
+    //
+    // Return the number of bytes we are going to read.
+    //
+    *pui32Size = ui32ByteCount;
+
+    //
+    // Calculate the FIFO address.
+    //
+    ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2);
+
+    //
+    // Read the data out of the FIFO.
+    //
+    for(; ui32ByteCount > 0; ui32ByteCount--)
+    {
+        //
+        // Read a byte at a time from the FIFO.
+        //
+        *pui8Data++ = HWREGB(ui32FIFO);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the specified endpoint's FIFO in device
+//! mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param bIsLastPacket indicates if this packet is the last one.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! The \e bIsLastPacket parameter is set to a \b true value if this is the
+//! last in a series of data packets on endpoint zero.  The \e bIsLastPacket
+//! parameter is not used for endpoints other than endpoint zero.  This call
+//! can be used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint,
+                      bool bIsLastPacket)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Determine which endpoint is being acked.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Clear RxPktRdy, and optionally DataEnd, on endpoint zero.
+        //
+        HWREGB(ui32Base + USB_O_CSRL0) =
+            USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0);
+    }
+    else
+    {
+        //
+        // Clear RxPktRdy on all other endpoints.
+        //
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~(USB_RXCSRL1_RXRDY);
+    }
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the specified endpoint's FIFO in host
+//! mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! This call is used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Clear RxPktRdy.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY;
+    }
+    else
+    {
+        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+            ~(USB_RXCSRL1_RXRDY);
+    }
+}
+
+//*****************************************************************************
+//
+//! Puts data into the specified endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui8Data is a pointer to the data area used as the source for the
+//! data to put into the FIFO.
+//! \param ui32Size is the amount of data to put into the FIFO.
+//!
+//! This function puts the data from the \e pui8Data parameter into the FIFO
+//! for this endpoint.  If a packet is already pending for transmission, then
+//! this call does not put any of the data into the FIFO and returns -1.  Care
+//! must be taken to not write more data than can fit into the FIFO
+//! allocated by the call to USBFIFOConfigSet().
+//!
+//! \return This call returns 0 on success, or -1 to indicate that the FIFO
+//! is in use and cannot be written.
+//
+//*****************************************************************************
+int32_t
+USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint,
+                   uint8_t *pui8Data, uint32_t ui32Size)
+{
+    uint32_t ui32FIFO;
+    uint8_t ui8TxPktRdy;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Get the bit position of TxPktRdy based on the endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        ui8TxPktRdy = USB_CSRL0_TXRDY;
+    }
+    else
+    {
+        ui8TxPktRdy = USB_TXCSRL1_TXRDY;
+    }
+
+    //
+    // Don't allow transmit of data if the TxPktRdy bit is already set.
+    //
+    if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy)
+    {
+        return(-1);
+    }
+
+    //
+    // Calculate the FIFO address.
+    //
+    ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2);
+
+    //
+    // Write the data to the FIFO.
+    //
+    for(; ui32Size > 0; ui32Size--)
+    {
+        HWREGB(ui32FIFO) = *pui8Data++;
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Starts the transfer of data from an endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32TransType is set to indicate what type of data is being sent.
+//!
+//! This function starts the transfer of data from the FIFO for a specified
+//! endpoint.  This function is called if the \b USB_EP_AUTO_SET bit was
+//! not enabled for the endpoint.  Setting the \e ui32TransType parameter
+//! allows the appropriate signaling on the USB bus for the type of transaction
+//! being requested.  The \e ui32TransType parameter must be one of the
+//! following:
+//!
+//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode.
+//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode.
+//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a
+//!   sequence of IN transactions.
+//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero.
+//! - \b USB_TRANS_STATUS for status results on endpoint zero.
+//!
+//! \return This call returns 0 on success, or -1 if a transmission is already
+//! in progress.
+//
+//*****************************************************************************
+int32_t
+USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint,
+                    uint32_t ui32TransType)
+{
+    uint32_t ui32TxPktRdy;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Get the bit position of TxPktRdy based on the endpoint.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Don't allow transmit of data if the TxPktRdy bit is already set.
+        //
+        if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY)
+        {
+            return(-1);
+        }
+
+        ui32TxPktRdy = ui32TransType & 0xff;
+    }
+    else
+    {
+        //
+        // Don't allow transmit of data if the TxPktRdy bit is already set.
+        //
+        if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY)
+        {
+            return(-1);
+        }
+
+        ui32TxPktRdy = (ui32TransType >> 8) & 0xff;
+    }
+
+    //
+    // Set TxPktRdy in order to send the data.
+    //
+    HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy;
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Forces a flush of an endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags specifies if the IN or OUT endpoint is accessed.
+//!
+//! This function forces the USB controller to flush out the data in the FIFO.
+//! The function can be called with either host or device controllers and
+//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Endpoint zero has a different register set for FIFO flushing.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        //
+        // Nothing in the FIFO if neither of these bits are set.
+        //
+        if((HWREGB(ui32Base + USB_O_CSRL0) &
+            (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
+        {
+            //
+            // Hit the Flush FIFO bit.
+            //
+            HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH;
+        }
+    }
+    else
+    {
+        //
+        // Only reset the IN or OUT FIFO.
+        //
+        if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+        {
+            //
+            // Make sure the FIFO is not empty.
+            //
+            if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &
+               USB_TXCSRL1_TXRDY)
+            {
+                //
+                // Hit the Flush FIFO bit.
+                //
+                HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+                    USB_TXCSRL1_FLUSH;
+            }
+        }
+        else
+        {
+            //
+            // Make sure that the FIFO is not empty.
+            //
+            if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &
+               USB_RXCSRL1_RXRDY)
+            {
+                //
+                // Hit the Flush FIFO bit.
+                //
+                HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+                    USB_RXCSRL1_FLUSH;
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Schedules a request for an IN transaction on an endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function schedules a request for an IN transaction.  When the USB
+//! device being communicated with responds with the data, the data can be
+//! retrieved by calling USBEndpointDataGet() or via a DMA transfer.
+//!
+//! \note This function must only be called in host mode and only for IN
+//! endpoints.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+    uint32_t ui32Register;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Endpoint zero uses a different offset than the other endpoints.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        ui32Register = USB_O_CSRL0;
+    }
+    else
+    {
+        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+    }
+
+    //
+    // Set the request for an IN transaction.
+    //
+    HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Clears a scheduled IN transaction for an endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function clears a previously scheduled IN transaction if it is still
+//! pending.  This function is used to safely disable any scheduled IN
+//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured
+//! for communications with other devices.
+//!
+//! \note This function must only be called in host mode and only for IN
+//! endpoints.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+    uint32_t ui32Register;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // Endpoint zero uses a different offset than the other endpoints.
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        ui32Register = USB_O_CSRL0;
+    }
+    else
+    {
+        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+    }
+
+    //
+    // Clear the request for an IN transaction.
+    //
+    HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Issues a request for a status IN transaction on endpoint zero.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function is used to cause a request for a status IN transaction from
+//! a device on endpoint zero.  This function can only be used with endpoint
+//! zero as that is the only control endpoint that supports this ability.  This
+//! function is used to complete the last phase of a control transaction to a
+//! device and an interrupt is signaled when the status packet has been
+//! received.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestStatus(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Set the request for a status IN transaction.
+    //
+    HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
+}
+
+//*****************************************************************************
+//
+//! Sets the functional address for the device that is connected to an
+//! endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Addr is the functional address for the controller to use for
+//! this endpoint.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function configures the functional address for a device that is using
+//! this endpoint for communication.  This \e ui32Addr parameter is the address
+//! of the target device that this endpoint is communicating with.  The
+//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr,
+               uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the transmit or receive address is set.
+    //
+    if(ui32Flags & USB_EP_HOST_OUT)
+    {
+        //
+        // Set the transmit address.
+        //
+        HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr;
+    }
+    else
+    {
+        //
+        // Set the receive address.
+        //
+        HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) =
+            ui32Addr;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current functional device address for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current functional address that an endpoint is
+//! using to communicate with a device.  The \e ui32Flags parameter determines
+//! if the IN or OUT endpoint's device address is returned.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return Returns the current function address being used by an endpoint.
+//
+//*****************************************************************************
+uint32_t
+USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the transmit or receive address is returned.
+    //
+    if(ui32Flags & USB_EP_HOST_OUT)
+    {
+        //
+        // Return this endpoint's transmit address.
+        //
+        return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)));
+    }
+    else
+    {
+        //
+        // Return this endpoint's receive address.
+        //
+        return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the hub address for the device that is connected to an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Addr is the hub address and port for the device using this
+//! endpoint.  The hub address must be defined in bits 0 through 6 with the
+//! port number in bits 8 through 14.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function configures the hub address for a device that is using this
+//! endpoint for communication.  The \e ui32Flags parameter determines if the
+//! device address for the IN or the OUT endpoint is configured by this call
+//! and sets the speed of the downstream device.  Valid values are one of
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with
+//! \b USB_EP_SPEED_LOW.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr,
+                  uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the hub transmit or receive address is being set.
+    //
+    if(ui32Flags & USB_EP_HOST_OUT)
+    {
+        //
+        // Set the hub transmit address and port number for this endpoint.
+        //
+        HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr;
+    }
+    else
+    {
+        //
+        // Set the hub receive address and port number for this endpoint.
+        //
+        HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) =
+            ui32Addr;
+    }
+
+    //
+    // Set the speed of communication for endpoint 0.  This configuration is
+    // done here because it changes on a transaction-by-transaction basis for
+    // EP0.  For other endpoints, this is set in USBHostEndpointConfig().
+    //
+    if(ui32Endpoint == USB_EP_0)
+    {
+        if(ui32Flags & USB_EP_SPEED_FULL)
+        {
+            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL;
+        }
+        else if(ui32Flags & USB_EP_SPEED_HIGH)
+        {
+            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH;
+        }
+        else
+        {
+            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current device hub address for this endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current hub address that an endpoint is using
+//! to communicate with a device.  The \e ui32Flags parameter determines if the
+//! device address for the IN or OUT endpoint is returned.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return This function returns the current hub address being used by an
+//! endpoint.
+//
+//*****************************************************************************
+uint32_t
+USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+    //
+    // See if the hub transmit or receive address is returned.
+    //
+    if(ui32Flags & USB_EP_HOST_OUT)
+    {
+        //
+        // Return the hub transmit address for this endpoint.
+        //
+        return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)));
+    }
+    else
+    {
+        //
+        // Return the hub receive address for this endpoint.
+        //
+        return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for USB power fault.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies the configuration of the power fault.
+//!
+//! This function controls how the USB controller uses its external power
+//! control pins (USBnPFLT and USBnEPEN).  The flags specify the power
+//! fault level sensitivity, the power fault action, and the power enable level
+//! and source.
+//!
+//! One of the following can be selected as the power fault level sensitivity:
+//!
+//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin
+//!                            being driven low.
+//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin
+//!                             being driven high.
+//!
+//! One of the following can be selected as the power fault action:
+//!
+//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault
+//!   detected.
+//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a
+//!                               power fault.
+//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a
+//!                               power fault.
+//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a
+//!                                power fault.
+//!
+//! One of the following can be selected as the power enable level and source:
+//!
+//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller
+//!                               when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB
+//!                                controller when USBHostPwrEnable() is
+//!                                called.
+//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller
+//!                               automatically if USBOTGSessionRequest() has
+//!                               enabled a session.
+//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB
+//!                                controller automatically if
+//!                                USBOTGSessionRequest() has enabled a
+//!                                session.
+//!
+//! When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be
+//! addded to ignore small, short drops in VBUS level caused by high power
+//! consumption.  This feature is mainly used to avoid causing VBUS errors
+//! caused by devices with high in-rush current.
+//!
+//! \note This function must only be called on microcontrollers that support
+//! host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and
+//! \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that
+//! support OTG operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M |
+                          USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH |
+                          USB_EPC_EPEN_M)) == 0);
+
+    //
+    // If requested, enable VBUS droop detection on parts that support this
+    // feature.
+    //
+    HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16;
+
+    //
+    // Set the power fault configuration as specified.  This configuration
+    // does not change whether fault detection is enabled or not.
+    //
+    HWREGH(ui32Base + USB_O_EPC) =
+        (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) &
+                      ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
+                        USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)));
+}
+
+//*****************************************************************************
+//
+//! Enables power fault detection.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function enables power fault detection in the USB controller.  If the
+//! USBnPFLT pin is not in use, this function must not be used.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable power fault input.
+    //
+    HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables power fault detection.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables power fault detection in the USB controller.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable power fault input.
+    //
+    HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the external power pin.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function enables the USBnEPEN signal, which enables an external power
+//! supply in host mode operation.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable the external power supply enable signal.
+    //
+    HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Disables the external power pin.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables the USBnEPEN signal, which disables an external
+//! power supply in host mode operation.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Disable the external power supply enable signal.
+    //
+    HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Gets the current frame number.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the last frame number received.
+//!
+//! \return The last frame number received.
+//
+//*****************************************************************************
+uint32_t
+USBFrameNumberGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Return the most recent frame number.
+    //
+    return(HWREGH(ui32Base + USB_O_FRAME));
+}
+
+//*****************************************************************************
+//
+//! Starts or ends a session.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bStart specifies if this call starts or ends a session.
+//!
+//! This function is used in OTG mode to start a session request or end a
+//! session.  If the \e bStart parameter is set to \b true, then this function
+//! starts a session and if it is \b false it ends a session.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGSessionRequest(uint32_t ui32Base, bool bStart)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Start or end the session as directed.
+    //
+    if(bStart)
+    {
+        HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION;
+    }
+    else
+    {
+        HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the absolute FIFO address for a specified endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies which endpoint's FIFO address to return.
+//!
+//! This function returns the actual physical address of the FIFO.  This
+//! address is needed when the USB is going to be used with the uDMA
+//! controller and the source or destination address must be set to the
+//! physical FIFO address for a specified endpoint. This function can also be
+//! used to provide the physical address to manually read data from an
+//! endpoints FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+    //
+    // Return the FIFO address for this endpoint.
+    //
+    return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2));
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode of the controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current operating mode on USB controllers with
+//! OTG or Dual mode functionality.
+//!
+//! For OTG controllers:
+//!
+//! The function returns one of the following values on OTG controllers:
+//!
+//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode
+//! on the B-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode
+//! on the B-side of the cable.  If an OTG session request is started with no
+//! cable in place, this mode is the default.
+//!
+//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to
+//! determine its role in the system.
+//!
+//! For Dual Mode controllers:
+//!
+//! The function returns one of the following values:
+//!
+//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host.
+//!
+//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device.
+//!
+//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as
+//! either a host or device.
+//!
+//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//
+//*****************************************************************************
+uint32_t
+USBModeGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Checks the current mode in the USB_O_DEVCTL and returns the current
+    // mode.
+    //
+    // USB_OTG_MODE_ASIDE_HOST:  USB_DEVCTL_HOST | USB_DEVCTL_SESSION
+    // USB_OTG_MODE_ASIDE_DEV:   USB_DEVCTL_SESSION
+    // USB_OTG_MODE_BSIDE_HOST:  USB_DEVCTL_DEV | USB_DEVCTL_SESSION |
+    //                           USB_DEVCTL_HOST
+    // USB_OTG_MODE_BSIDE_DEV:   USB_DEVCTL_DEV | USB_DEVCTL_SESSION
+    // USB_OTG_MODE_NONE:        USB_DEVCTL_DEV
+    //
+    return(HWREGB(ui32Base + USB_O_DEVCTL) &
+           (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION |
+            USB_DEVCTL_VBUS_M));
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA channel to use for a specified endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies which endpoint's FIFO address to return.
+//! \param ui32Channel specifies which DMA channel to use for which endpoint.
+//!
+//! This function is used to configure which DMA channel to use with a specified
+//! endpoint.  Receive DMA channels can only be used with receive endpoints
+//! and transmit DMA channels can only be used with transmit endpoints.  As a
+//! result, the 3 receive and 3 transmit DMA channels can be mapped to any
+//! endpoint other than 0.  The values that are passed into the
+//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h.
+//!
+//! \note This function only has an effect on microcontrollers that have the
+//! ability to change the DMA channel for an endpoint.  Calling this function
+//! on other devices has no effect.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint,
+                      uint32_t ui32Channel)
+{
+    uint32_t ui32Mask;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+           (ui32Endpoint == USB_EP_7));
+    ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX);
+
+    //
+    // The input select mask must be shifted into the correct position
+    // based on the channel.
+    //
+    ui32Mask = 0xf << (ui32Channel * 4);
+
+    //
+    // Clear out the current selection for the channel.
+    //
+    ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask);
+
+    //
+    // The input select is now shifted into the correct position based on the
+    // channel.
+    //
+    ui32Mask |= (USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4);
+
+    //
+    // Write the value out to the register.
+    //
+    HWREG(ui32Base + USB_O_DMASEL) = ui32Mask;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to host.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to host mode.
+//!
+//! \note This function must only be called on microcontrollers that support
+//! OTG operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostMode(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Force mode in OTG parts that support forcing USB controller mode.
+    // This bit is not writable in USB controllers that do not support
+    // forcing the mode.  Not setting the USB_GPCS_DEVMOD bit makes this a
+    // force of host mode.
+    //
+    HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to device.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to device mode.
+//!
+//! \note This function must only be called on microcontrollers that support
+//! OTG operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevMode(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Set the USB controller mode to device.
+    //
+    HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD;
+}
+
+//*****************************************************************************
+//
+//! Changes the mode of the USB controller to OTG.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to OTG mode.  This
+//! function is only valid on microcontrollers that have the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGMode(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Disable the override of the USB controller mode when running on an OTG
+    // device.
+    //
+    HWREGB(ui32Base + USB_O_GPCS) = 0;
+}
+
+//*****************************************************************************
+//
+//! Change the operating mode of the USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Mode specifies the operating mode of the USB OTG pins.
+//!
+//! This function changes the operating modes of the USB controller.  When
+//! operating in full OTG mode, the USB controller uses the VBUS and ID pins to
+//! detect mode and voltage changes.  While these pins are primarily used in
+//! OTG mode, they can also affect the operation of host and device modes.  In
+//! device mode, the USB controller can be configured to monitor or ignore
+//! VBUS. Monitoring VBUS allows the controller to determine if it has been
+//! disconnected from the host.  In host mode, the USB controller uses the
+//! VBUS pin to detect loss of VBUS caused by excessive power draw due to a
+//! drop in the VBUS voltage.  This call takes the place of USBHostMode(),
+//! USBDevMode(), and USBOTGMode().  The \e ui32Mode value should be one of
+//! the following values:
+//!
+//! - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are
+//!   used by the controller.
+//! - \b USB_MODE_HOST enables operating only as a host with no monitoring of
+//!   VBUS or ID pins.
+//! - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of
+//!   VBUS pin.  This configuration enables detection of VBUS droop while still
+//!   forcing host mode.
+//! - \b USB_MODE_DEVICE enables operating only as a device with no monitoring
+//!   of VBUS or ID pins.
+//! - \b USB_MODE_DEVICE_VBUS enables operating only as a device with
+//!   monitoring of VBUS pin.  This configuration enables disconnect detection
+//!   while still forcing device mode.
+//!
+//! \note Some of the options above are not available on some Tiva devices.
+//! Please check the data sheet to determine if the USB controller supports a
+//! particular mode.
+//!
+//! \b Example: Force device mode but allow monitoring of the USB VBUS pin.
+//!
+//! \verbatim
+//! //
+//! // Force device mode but allow monitoring of VBUS for disconnect.
+//! //
+//! USBModeConfig(USB_MODE_DEVICE_VBUS);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == USB0_BASE);
+
+    HWREG(ui32Base + USB_O_GPCS) = ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Powers off the internal USB PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function powers off the internal USB PHY, reducing the current
+//! consumption of the device.  While in the powered-off state, the USB
+//! controller is unable to operate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOff(uint32_t ui32Base)
+{
+    //
+    // Set the PWRDNPHY bit in the PHY, putting it into its low power mode.
+    //
+    HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+//! Powers on the internal USB PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function powers on the internal USB PHY, enabling it return to normal
+//! operation.  By default, the PHY is powered on, so this function must
+//! only be called if USBPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOn(uint32_t ui32Base)
+{
+    //
+    // Clear the PWRDNPHY bit in the PHY, putting it into normal operating
+    // mode.
+    //
+    HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+//! Sets the number of packets to request when transferring multiple bulk
+//! packets.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint index to target for this write.
+//! \param ui32Count is the number of packets to request.
+//!
+//! This function sets the number of consecutive bulk packets to request
+//! when transferring multiple bulk packets with DMA.
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                          uint32_t ui32Count)
+{
+    HWREG(ui32Base + USB_O_RQPKTCOUNT1 +
+          (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count;
+}
+
+//*****************************************************************************
+//
+//! Returns the number of USB endpoint pairs on the device.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the number of endpoint pairs supported by the USB
+//! controller corresponding to the passed base address.  The value returned is
+//! the number of IN or OUT endpoints available and does not include endpoint 0
+//! (the control endpoint).  For example, if 15 is returned, there are 15 IN
+//! and 15 OUT endpoints available in addition to endpoint 0.
+//!
+//! \return Returns the number of IN or OUT endpoints available.
+//
+//*****************************************************************************
+uint32_t
+USBNumEndpointsGet(uint32_t ui32Base)
+{
+    //
+    // Read the number of endpoints from the hardware.  The number of TX and
+    // RX endpoints are always the same.
+    //
+    return(HWREGB(ui32Base + USB_O_EPINFO) & USB_EPINFO_TXEP_M);
+}
+
+//*****************************************************************************
+//
+//! Returns the version of the USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the version number of the USB controller, which can
+//! be be used to adjust for slight differences between the USB controllers in
+//! the Tiva family.  The values that are returned are
+//! \b USB_CONTROLLER_VER_0 and \b USB_CONTROLLER_VER_1.
+//!
+//! \note The most significant difference between \b USB_CONTROLLER_VER_0 and
+//! \b USB_CONTROLLER_VER_1 is that \b USB_CONTROLLER_VER_1 supports the USB
+//! controller's own bus master DMA controller, while the
+//! \b USB_CONTROLLER_VER_0 only supports using the uDMA controller with the
+//! USB module.
+//!
+//! \b Example: Get the version of the Tiva USB controller.
+//!
+//! \verbatim
+//! uint32_t ui32Version;
+//!
+//! //
+//! // Retrieve the version of the Tiva USB controller.
+//! //
+//! ui32Version = USBControllerVersion(USB0_BASE);
+//! \endverbatim
+//!
+//! \return This function returns one of the \b USB_CONTROLLER_VER_ values.
+//
+//*****************************************************************************
+uint32_t
+USBControllerVersion(uint32_t ui32Base)
+{
+    //
+    // Return the type field of the peripheral properties.  This returns
+    // zero for all parts that did not have a peripheral property.
+    //
+    return(HWREG(ui32Base + USB_O_PP) & USB_PP_TYPE_M);
+}
+
+//*****************************************************************************
+//
+//! Configures and enables the clocking to the USB controller's PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Div specifies the divider for the internal USB PHY clock.
+//! \param ui32Flags configures the internal USB PHY clock and specifies the
+//!  clock source for a ULPI-connected PHY.
+//!
+//! This function configures and enables the USB PHY clock. In addition, for
+//! systems that use a ULPI-connected external PHY, this function configures
+//! the source for the PHY clock. The \e ui32Flags parameter specifies the
+//! clock source with the following values:
+//!
+//! - \b USB_CLOCK_INTERNAL uses the internal PLL combined with the \e ui32Div
+//! value to generate the USB clock that is used by the internal USB PHY. In
+//! addition, when using an external ULPI-connected USB PHY, the specified
+//! clock is output on the USB0CLK pin.
+//! - \b USB_CLOCK_EXTERNAL specifies that USB0CLK is an input from the
+//! ULPI-connected external PHY.
+//!
+//! The \e ui32Div parameter is used to specify a divider for the internal
+//! clock if the \b USB_CLOCK_INTERNAL is specified and is ignored if
+//! \b USB_CLOCK_EXTERNAL is specified.  When the \b USB_CLOCK_INTERNAL is
+//! specified, the \e ui32Div value must be set so that the PLL_VCO/\e ui32Div
+//! results in a 60-MHz clock.
+//!
+//! \b Example: Enable the USB clock with a 480-MHz PLL setting.
+//!
+//! \verbatim
+//! //
+//! // Enable the USB clock using a 480-MHz PLL.
+//! // (480-MHz/8 = 60-MHz)
+//! //
+//! USBClockEnable(USB0_BASE, 8, USB_CLOCK_INTERNAL);
+//! \endverbatim
+//!
+//! \note The ability to configure the USB PHY clock is not available on
+//! all Tiva devices.  Please consult the data sheet for the Tiva
+//! device that you are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, uint32_t ui32Flags)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Configure and enable the USB clock input.
+    //
+    HWREG(ui32Base + USB_O_CC) = (ui32Div - 1) | ui32Flags;
+}
+
+//*****************************************************************************
+//
+//! Disables the clocking of the USB controller's PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables the USB PHY clock. This function should not be
+//! called in applications where the USB controller is used.
+//!
+//! \b Example: Disable the USB PHY clock input.
+//!
+//! \verbatim
+//! //
+//! // Disable clocking of the USB controller's PHY.
+//! //
+//! USBClockDisable(USB0_BASE);
+//! \endverbatim
+//!
+//! \note The ability to configure the USB PHY clock is not available on all
+//! Tiva devices.  Please consult the data sheet for the Tiva device
+//! that you are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBClockDisable(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Disable the USB clock input.
+    //
+    HWREG(ui32Base + USB_O_CC) = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+//! \addtogroup usb_dma
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enable interrupts for a specified integrated USB DMA channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel interrupt to enable.
+//!
+//! This function enables the USB DMA channel interrupt based on the
+//! \e ui32Channel parameter.  The \e ui32Channel value is a zero-based
+//! index of the USB DMA channel.  Once enabled, the USBDMAChannelIntStatus()
+//! function returns if a DMA channel has generated an interrupt.
+//!
+//! \b Example: Enable the USB DMA channel 3 interrupt.
+//!
+//! \verbatim
+//! //
+//! // Enable the USB DMA channel 3 interrupt
+//! //
+//! USBDMAChannelIntEnable(USB0_BASE, 3);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Enable the specified DMA channel interrupts.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= USB_DMACTL0_IE;
+}
+
+//*****************************************************************************
+//
+//! Disable interrupts for a specified integrated USB DMA channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which USB DMA channel interrupt to disable.
+//!
+//! This function disables the USB DMA channel interrupt based on the
+//! \e ui32Channel parameter.  The \e ui32Channel value is a zero-based
+//! index of the USB DMA channel.
+//!
+//! \b Example: Disable the USB DMA channel 3 interrupt.
+//!
+//! \verbatim
+//! //
+//! // Disable the USB DMA channel 3 interrupt
+//! //
+//! USBDMAChannelIntDisable(USB0_BASE, 3);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Enable the specified DMA channel interrupts.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~USB_DMACTL0_IE;
+}
+
+//*****************************************************************************
+//
+//! Return the current status of the integrated USB DMA interrupts.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current bit-mapped interrupt status for all USB
+//! DMA channel interrupt sources.  Calling this function automatically clears
+//! all currently pending USB DMA interrupts.
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \b Example: Get the pending USB DMA interrupts.
+//!
+//! \verbatim
+//! uint32_t ui32Ints;
+//!
+//! //
+//! // Get the pending USB DMA interrupts.
+//! //
+//! ui32Ints = USBDMAChannelIntStatus(USB0_BASE);
+//! \endverbatim
+//!
+//! \return The bit-mapped interrupts for the DMA channels.
+//
+//*****************************************************************************
+uint32_t
+USBDMAChannelIntStatus(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    return(HWREG(ui32Base + USB_O_DMAINTR));
+}
+
+//*****************************************************************************
+//
+//! Enables integrated USB DMA for a specified channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies the USB DMA channel to enable.
+//!
+//! This function enables the USB DMA channel passed in the \e ui32Channel
+//! parameter.  The \e ui32Channel value is a zero-based index of the USB DMA
+//! channel.
+//!
+//! \b Example: Enable USB DMA channel 2.
+//!
+//! \verbatim
+//! //
+//! // Enable USB DMA channel 2.
+//! //
+//! USBDMAChannelEnable(2);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Enable the USB DMA channel.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |=
+        USB_DMACTL0_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables integrated USB DMA for a specified channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies the USB DMA channel to disable.
+//!
+//! This function disables the USB DMA channel passed in the \e ui32Channel
+//! parameter.  The \e ui32Channel parameter is a zero-based index of the DMA
+//! channel.
+//!
+//! \b Example: Disable USB DMA channel 2.
+//!
+//! \verbatim
+//! //
+//! // Disable USB DMA channel 2.
+//! //
+//! USBDMAChannelDisable(2);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Disable the USB DMA channel.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &=
+        ~USB_DMACTL0_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Assigns and configures an endpoint to a specified integrated USB DMA
+//! channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel to access.
+//! \param ui32Endpoint is the endpoint to assign to the USB DMA channel.
+//! \param ui32Config is used to specify the configuration of the USB DMA
+//! channel.
+//!
+//! This function assigns an endpoint and configures the settings for a
+//! USB DMA channel.  The \e ui32Endpoint parameter is one of the
+//! \b USB_EP_* values and the \e ui32Channel value is a zero-based index of
+//! the DMA channel to configure.  The \e ui32Config parameter is a combination
+//! of the \b USB_DMA_CFG_* values using the following guidelines.
+//!
+//! Use one of the following to set the DMA burst mode:
+//! - \b USB_DMA_CFG_BURST_NONE disables bursting.
+//! - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words.
+//! - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words.
+//! - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words.
+//!
+//! Use one of the following to set the DMA mode:
+//! - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is
+//!   being sent via DMA and triggers one completion interrupt per packet.
+//! - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being
+//!   sent via DMA and triggers one completion interrupt per transfer.
+//!
+//! Use one of the following to set the direction of the transfer:
+//! - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a
+//!   memory location.
+//! - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a
+//!   memory location.
+//!
+//! The following two optional settings allow an application to immediately
+//! enable the DMA transfer and/or DMA interrupts when configuring the DMA
+//! channel:
+//! - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so
+//!   that an added call to USBDMAChannelIntEnable() is not necessary.
+//! - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added
+//!   call to USBDMAChannelEnable() is not necessary.
+//!
+//! \b Example: Assign channel 0 to endpoint 1 in DMA mode 0, 4 word burst,
+//!    enable interrupts and immediately enable the transfer.
+//!
+//! \verbatim
+//! //
+//! // Assign channel 0 to endpoint 1 in DMA mode 0, 4 word bursts,
+//! // enable interrupts and immediately enable the transfer.
+//! //
+//! USBDMAChannelConfigSet(USB0_BASE, 0, USB_EP_1,
+//!                        (USB_DMA_CFG_BURST_4 | USB_DMA_CFG_MODE0 |
+//!                         USB_DMA_CFG_DIR_RX | USB_DMA_CFG_INT_EN |
+//!                         USB_DMA_CFG_EN));
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel,
+                       uint32_t ui32Endpoint, uint32_t ui32Config)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+    ASSERT((ui32Endpoint & ~USB_EP_7) == 0);
+
+    //
+    // Reset this USB DMA channel.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = 0;
+
+    //
+    // Set the configuration of the requested channel.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) =
+        ui32Config | ui32Endpoint;
+}
+
+//*****************************************************************************
+//
+//! Returns the current status for an integrated USB DMA channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel to query.
+//!
+//! This function returns the current status for the USB DMA channel specified
+//! by the \e ui32Channel parameter.  The \e ui32Channel value is a zero-based
+//! index of the USB DMA channel to query.
+//!
+//! \b Example: Get the current USB DMA status for channel 2.
+//!
+//! \verbatim
+//! uint32_t ui32Status;
+//!
+//! //
+//! // Get the current USB DMA status for channel 2.
+//! //
+//! ui32Status = USBDMAChannelStatus(USB0_BASE, 2);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return Returns zero or \b USB_DMACTL0_ERR if there is a pending error
+//! condition on a DMA channel.
+//
+//*****************************************************************************
+uint32_t
+USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Return a non-zero value if there is a pending error condition.
+    //
+    return(HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &
+           USB_DMACTL0_ERR);
+}
+
+//*****************************************************************************
+//
+//! Clears the integrated USB DMA status for a specified channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel to clear.
+//! \param ui32Status holds the status bits to clear.
+//!
+//! This function clears the USB DMA channel status for the channel specified
+//! by the \e ui32Channel parameter.  The \e ui32Channel value is a zero-based
+//! index of the USB DMA channel to query.  The \e ui32Status parameter
+//! specifies the status bits to clear and must be the valid values that are
+//! returned from a call to the USBDMAChannelStatus() function.
+//!
+//! \b Example: Clear the current USB DMA status for channel 2.
+//!
+//! \verbatim
+//! //
+//! // Clear the any pending USB DMA status for channel 2.
+//! //
+//! USBDMAChannelStatusClear(USB0_BASE, 2, USBDMAChannelStatus(USB0_BASE, 2));
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel,
+                         uint32_t ui32Status)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // The only status is the error bit.
+    //
+    ui32Status &= USB_DMACTL0_ERR;
+
+    //
+    // Clear the specified error condition.
+    //
+    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~ui32Status;
+}
+
+//*****************************************************************************
+//
+//! Sets the source or destination address for an integrated USB DMA transfer
+//! on a specified channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel to configure.
+//! \param pvAddress specifies the source or destination address for the USB
+//! DMA transfer.
+//!
+//! This function sets the source or destination address for the USB DMA
+//! channel number specified in the \e ui32Channel parameter.  The
+//! \e ui32Channel value is a zero-based index of the USB DMA channel.  The
+//! \e pvAddress parameter is a source address if the transfer type for the DMA
+//! channel is transmit and a destination address if the transfer type is
+//! receive.
+//!
+//! \b Example: Set the transfer address for USB DMA channel 1.
+//!
+//! \verbatim
+//! void *pvBuffer;
+//!
+//! //
+//! // Set the address for USB DMA channel 1.
+//! //
+//! USBDMAChannelAddressSet(USB0_BASE, 1, pvBuffer);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel,
+                        void *pvAddress)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Set the DMA address.
+    //
+    HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)) =
+        (uint32_t)pvAddress;
+}
+
+//*****************************************************************************
+//
+//! Returns the source or destination address for the specified integrated USB
+//! DMA channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies the USB DMA channel.
+//!
+//! This function returns the DMA address for the channel number specified
+//! in the \e ui32Channel parameter.  The \e ui32Channel value is a zero-based
+//! index of the DMA channel to query.  This function must not be used on
+//! devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion()
+//! function.
+//!
+//! \b Example: Get the transfer address for USB DMA channel 1.
+//!
+//! \verbatim
+//! void *pvBuffer;
+//!
+//! //
+//! // Retrieve the current DMA address for channel 1.
+//! //
+//! pvBuffer = USBDMAChannelAddressGet(USB0_BASE, 1);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return The current DMA address for a USB DMA channel.
+//
+//*****************************************************************************
+void *
+USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Return the current DMA address.
+    //
+    return((void *)HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)));
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer count for an integrated USB DMA channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel to access.
+//! \param ui32Count specifies the number of bytes to transfer.
+//!
+//! This function sets the USB DMA transfer count in bytes for the channel
+//! number specified in the \e ui32Channel parameter.  The \e ui32Channel
+//! value is a zero-based index of the DMA channel.
+//!
+//! \b Example: Set the transfer count to 512 bytes for USB DMA channel 1.
+//!
+//! \verbatim
+//! //
+//! // Set the transfer count to 512 bytes for USB DMA channel 1.
+//! //
+//! USBDMAChannelCountSet(USB0_BASE, 1, 512);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Channel,
+                      uint32_t ui32Count)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Set the USB DMA count for the channel.
+    //
+    HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)) = ui32Count;
+}
+
+//*****************************************************************************
+//
+//! Returns the transfer count for an integrated USB DMA channel.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Channel specifies which DMA channel to access.
+//!
+//! This function returns the USB DMA transfer count in bytes for the channel
+//! number specified in the \e ui32Channel parameter.  The \e ui32Channel value
+//! is a zero-based index of the DMA channel to query.
+//!
+//! \b Example: Get the transfer count for USB DMA channel 1.
+//!
+//! \verbatim
+//! uint32_t ui32Count;
+//!
+//! //
+//! // Get the transfer count for USB DMA channel 1.
+//! //
+//! ui32Count = USBDMAChannelCountGet(USB0_BASE, 1);
+//! \endverbatim
+//!
+//! \note This feature is not available on all Tiva devices.  Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return The current count for a USB DMA channel.
+//
+//*****************************************************************************
+uint32_t
+USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Channel < 8);
+
+    //
+    // Return the current DMA count.
+    //
+    return(HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)));
+}
+
+//*****************************************************************************
+//
+//! Returns the available number of integrated USB DMA channels.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the total number of DMA channels available when using
+//! the integrated USB DMA controller.  This function returns 0 if the
+//! integrated controller is not present.
+//!
+//! \b Example: Get the number of integrated DMA channels.
+//!
+//! \verbatim
+//! uint32_t ui32Count;
+//!
+//! //
+//! // Get the number of integrated DMA channels.
+//! //
+//! ui32Count = USBDMANumChannels(USB0_BASE);
+//! \endverbatim
+//!
+//! \return The number of integrated USB DMA channels or zero if the
+//! integrated USB DMA controller is not present.
+//
+//*****************************************************************************
+uint32_t
+USBDMANumChannels(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Return the number of DMA channels for the integrated DMA controller.
+    //
+    return(HWREG(ui32Base + USB_O_RAMINFO) >> USB_RAMINFO_DMACHAN_S);
+}
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+//! \addtogroup usb_ulpi
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Configures the USB controller's ULPI function.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Config contains the configuration options.
+//!
+//! This function is used to configure the USB controller's ULPI function.
+//! The configuration options are set in the \e ui32Config parameter and are a
+//! logical OR of the following values:
+//!
+//! - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS
+//!   signaling.
+//! - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external
+//!   VBUS over-current condition.
+//!
+//! \b Example: Enable ULPI PHY with full VBUS control.
+//!
+//! \verbatim
+//! //
+//! // Enable ULPI PHY with full VBUS control.
+//! //
+//! USBULPIConfig(USB0_BASE, USB_ULPI_EXTVBUS | USB_ULPI_EXTVBUS_IND);
+//! \endverbatim
+//!
+//! \note The USB ULPI feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config)
+{
+    HWREGB(ui32Base + USB_O_ULPIVBUSCTL) = (uint8_t)ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Enables the USB controller's ULPI function.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function enables the USB controller's ULPI function and must be
+//! called before attempting to access an external ULPI-connected USB PHY.
+//!
+//! \b Example: Enable ULPI function.
+//!
+//! \verbatim
+//! //
+//! // Enable ULPI function.
+//! //
+//! USBULPIEnable(USB0_BASE);
+//! \endverbatim
+//!
+//! \note The USB ULPI feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBULPIEnable(uint32_t ui32Base)
+{
+    HWREG(ui32Base + USB_O_PC) |= USB_PC_ULPIEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the USB controller's ULPI function.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables the USB controller's ULPI function.  Accesses to
+//! the external ULPI-connected PHY cannot succeed after this function has been
+//! called.
+//!
+//! \b Example: Disable ULPI function.
+//!
+//! \verbatim
+//! //
+//! // Disable ULPI function.
+//! //
+//! USBULPIDisable(USB0_BASE);
+//! \endverbatim
+//!
+//! \note The USB ULPI feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBULPIDisable(uint32_t ui32Base)
+{
+    HWREG(ui32Base + USB_O_PC) &= ~USB_PC_ULPIEN;
+}
+
+//*****************************************************************************
+//
+//! Reads a register from an external ULPI-connected USB PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui8Reg specifies the register address to read.
+//!
+//! This function reads the register address specified in the \e ui8Reg
+//! parameter using the ULPI function.  This function is blocking and only
+//! returns when the read access completes.  The function does not return if
+//! there is not a ULPI-connected USB PHY present.
+//!
+//! \b Example: Read a register from the ULPI PHY.
+//!
+//! \verbatim
+//! uint8_t ui8Value;
+//!
+//! //
+//! // Read a register from the ULPI PHY register at 0x10.
+//! //
+//! ui8Value = USBULPIRegRead(USB0_BASE, 0x10);
+//! \endverbatim
+//!
+//! \note The USB ULPI feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return The value of the requested ULPI register.
+//
+//*****************************************************************************
+uint8_t
+USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Set the register address and initiate a read access.
+    //
+    HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg;
+    HWREGB(ui32Base + USB_O_ULPIREGCTL) =
+        USB_ULPIREGCTL_RDWR | USB_ULPIREGCTL_REGACC;
+
+    //
+    // Wait for the access to complete.
+    //
+    while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0)
+    {
+    }
+
+    //
+    // Clear the register access complete flag.
+    //
+    HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0;
+
+    return(HWREGB(ui32Base + USB_O_ULPIREGDATA));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to a register on an external ULPI-connected USB PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui8Reg specifies the register address to write.
+//! \param ui8Data specifies the data to write.
+//!
+//! This function writes the register address specified in the \e ui8Reg
+//! parameter with the value specified in the \e ui8Data parameter using the
+//! ULPI function.  This function is blocking and only returns when the
+//! write access completes.  The function does not return if there is not a
+//! ULPI-connected USB PHY present.
+//!
+//! \b Example: Write a register from the external ULPI PHY.
+//!
+//! \verbatim
+//! //
+//! // Write the ULPI PHY register at 0x10 with 0x20.
+//! //
+//! USBULPIRegWrite(USB0_BASE, 0x10, 0x20);
+//! \endverbatim
+//!
+//! \note The USB ULPI feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, uint8_t ui8Data)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Set the register address and initiate a read access.
+    //
+    HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg;
+    HWREGB(ui32Base + USB_O_ULPIREGDATA) = ui8Data;
+    HWREGB(ui32Base + USB_O_ULPIREGCTL) = USB_ULPIREGCTL_REGACC;
+
+    //
+    // Wait for the access to complete.
+    //
+    while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0)
+    {
+    }
+
+    //
+    // Clear the register access complete flag.
+    //
+    HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+//! \addtogroup usb_lpm
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Sends an LPM request to a device at a specified address and endpoint number.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Address is the target device address for the LPM request.
+//! \param ui32Endpoint is the target endpoint for the LPM request.
+//!
+//! This function sends an LPM request to a connected device in host mode.
+//! The \e ui32Address parameter specifies the device address and has a range
+//! of values from 1 to 127.   The \e ui32Endpoint parameter specifies the
+//! endpoint on the device to which to send the LPM request and must be one of
+//! the \b USB_EP_* values. The function returns before the LPM request is
+//! sent, requiring the caller to poll the USBLPMIntStatus() function or wait
+//! for an interrupt to signal completion of the LPM transaction.  This
+//! function must only be called after the USBHostLPMConfig() has configured
+//! the LPM transaction settings.
+//!
+//! \b Example: Send an LPM request to the device at address 1 on endpoint 0.
+//!
+//! \verbatim
+//! //
+//! // Send an LPM request to the device at address 1 on endpoint 0.
+//! //
+//! USBHostLPMSend(USB0_BASE, 1, USB_EP_0);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, uint32_t ui32Endpoint)
+{
+    uint32_t ui32Reg;
+
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32Address < 127);
+
+    //
+    // Set the address and endpoint.
+    //
+    HWREGB(ui32Base + USB_O_LPMFADDR) = ui32Address;
+
+    ui32Reg = HWREGH(ui32Base + USB_O_LPMATTR) & ~USB_LPMATTR_ENDPT_M;
+    ui32Reg |= (USBEPToIndex(ui32Endpoint) << USB_LPMATTR_ENDPT_S);
+
+    HWREGH(ui32Base + USB_O_LPMATTR) = ui32Reg;
+
+    //
+    // Send the LPM transaction.
+    //
+    HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_TXLPM;
+}
+
+//*****************************************************************************
+//
+//! Sets the global configuration for all LPM requests.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32ResumeTime specifies the resume signaling duration in 75us
+//! increments.
+//! \param ui32Config specifies the combination of configuration options for
+//! LPM transactions.
+//!
+//! This function sets the global configuration options for LPM transactions
+//! and must be called at least once before ever calling USBHostLPMSend().  The
+//! \e ui32ResumeTime specifies the length of time that the host drives resume
+//! signaling on the bus in microseconds.  The valid values
+//! for \e ui32ResumeTime are from 50us to 1175us in 75us increments.  The
+//! remaining configuration is specified by the \e ui32Config parameter and
+//! includes the following options:
+//!
+//! - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from
+//!   the LPM state.
+//! - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included
+//!   in the configuration.
+//!
+//! \b Example: Set the LPM configuration to allow remote wake with a resume
+//! duration of 500us.
+//!
+//! \verbatim
+//! //
+//! // Set the LPM configuration to allow remote wake with a resume
+//! // duration of 500us.
+//! //
+//! USBHostLPMConfig(USB0_BASE, 500, USB_HOST_LPM_RMTWAKE | USB_HOST_LPM_L1);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime,
+                 uint32_t ui32Config)
+{
+    ASSERT(ui32Base == USB0_BASE);
+    ASSERT(ui32ResumeTime <= 1175);
+    ASSERT(ui32ResumeTime >= 50);
+
+    //
+    // Set the Host Initiated Resume Duration, Remote wake and Suspend mode.
+    //
+    HWREGH(ui32Base + USB_O_LPMATTR) =
+        ui32Config | ((ui32ResumeTime - 50) / 75) << USB_LPMATTR_HIRD_S;
+}
+
+//*****************************************************************************
+//
+//! Initiates resume signaling to wake a device from LPM suspend mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! In host mode, this function initiates resume signaling to wake a device
+//! that has entered an LPM-triggered low power mode.  This LPM-triggered low
+//! power mode is entered when the USBHostLPMSend() is called to put a specific
+//! device into a low power state.
+//!
+//! \b Example: Initiate resume signaling.
+//!
+//! \verbatim
+//! //
+//! // Initiate resume signaling.
+//! //
+//! USBHostLPMResume(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostLPMResume(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Send Resume signaling.
+    //
+    HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES;
+}
+
+//*****************************************************************************
+//
+//! Initiates remote wake signaling to request the device to leave LPM
+//! suspend mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function initiates remote wake signaling to request that the host
+//! wake a device that has entered an LPM-triggered low power mode.
+//!
+//! \b Example: Initiate remote wake signaling.
+//!
+//! \verbatim
+//! //
+//! // Initiate remote wake signaling.
+//! //
+//! USBDevLPMRemoteWake(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in device mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevLPMRemoteWake(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Send remote wake signaling.
+    //
+    HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES;
+}
+
+//*****************************************************************************
+//
+//! Configures the USB device mode response to LPM requests.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Config is the combination of configuration options for LPM
+//! transactions in device mode.
+//!
+//! This function sets the global configuration options for LPM
+//! transactions in device mode and must be called before ever calling
+//! USBDevLPMEnable() to set the configuration for LPM transactions.  The
+//! configuration options in device mode are specified in the \e ui32Config
+//! parameter and include one of the following:
+//!
+//! - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM
+//!   transactions.
+//! - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM
+//!   and extended transactions.
+//! - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to
+//!   extended transactions, but not LPM transactions.
+//!
+//! The \e ui32Config option can also optionally include the
+//! \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all
+//! transactions other than an LPM transaction once the USB controller is in
+//! LPM suspend mode.  If this value is not included in the \e ui32Config
+//! parameter, the USB controller does not respond in suspend mode.
+//!
+//! The USB controller does not enter LPM suspend mode until the application
+//! calls the USBDevLPMEnable() function.
+//!
+//! \b Example: Enable LPM transactions and NAK while in LPM suspend mode.
+//!
+//! \verbatim
+//! //
+//! // Enable LPM transactions and NAK while in LPM suspend mode.
+//! //
+//! USBDevLPMConfig(USB0_BASE, USB_DEV_LPM_NAK | USB_DEV_LPM_EN);
+//! \endverbatim
+//!
+//! \note This function must only be called in device mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Set the device LPM configuration.
+    //
+    HWREGB(ui32Base + USB_O_LPMCNTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Enables the USB controller to respond to LPM suspend requests.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function is used to automatically respond to an LPM sleep request from
+//! the USB host controller.  If there is no data pending in any transmit
+//! FIFOs, then the USB controller acknowledges the packet and enters the
+//! LPM L1 state and generates the \b USB_INTLPM_ACK interrupt.  If the USB
+//! controller has pending transmit data in at least one FIFO, then the USB
+//! controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or
+//! \b USB_INTLPM_NYET depending on if data is pending in receive or transmit
+//! FIFOs.  A call to USBDevLPMEnable() is required after every
+//! LPM resume event to re-enable LPM mode.
+//!
+//! \b Example: Enable LPM suspend mode.
+//!
+//! \verbatim
+//!     //
+//!     // Enable LPM suspend mode.
+//!     //
+//!     USBDevLPMEnable(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in device mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevLPMEnable(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable L1 mode on the next LPM transaction.
+    //
+    HWREGB(ui32Base + USB_O_LPMCNTRL) |=
+        USB_LPMCNTRL_EN_LPMEXT | USB_LPMCNTRL_TXLPM;
+}
+
+//*****************************************************************************
+//
+//! Disables the USB controller from responding to LPM suspend requests.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables the USB controller from responding to LPM
+//! transactions.  When the device enters LPM L1 mode, the USB controller
+//! automatically disables responding to further LPM transactions.
+//!
+//! \note If LPM transactions were enabled before calling this function, then
+//! an LPM request can still occur before this function returns.  As a result,
+//! the application must continue to handle LPM requests until this function
+//! returns.
+//!
+//! \b Example: Disable LPM suspend mode.
+//!
+//! \verbatim
+//!     //
+//!     // Disable LPM suspend mode.
+//!     //
+//!     USBDevLPMDisable(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in device mode. The USB LPM feature
+//! is not available on all Tiva devices. Please consult the data sheet for
+//! the Tiva device that you are using to determine if this feature is
+//! available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevLPMDisable(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Disable auto entering L1 mode on LPM transactions.
+    //
+    HWREGB(ui32Base + USB_O_LPMCNTRL) &= ~USB_LPMCNTRL_TXLPM;
+}
+
+//*****************************************************************************
+//
+//! Returns the current link state setting.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current link state setting for the USB
+//! controller.  When the controller is operating as a host, this link
+//! state is sent with an LPM request.  When the controller is acting
+//! as a device, this link state was received by the last LPM transaction
+//! whether it was acknowledged or stalled because the requested
+//! LPM mode is not supported.
+//!
+//! \b Example: Get the link state for the last LPM transaction.
+//!
+//! \verbatim
+//! uint32_t ui32LinkState;
+//!
+//! //
+//! // Get the endpoint number that received the LPM request.
+//! //
+//! ui32LinkState = USBLPMLinkStateGet(USB0_BASE);
+//!
+//! //
+//! // Check if this was a supported link state.
+//! //
+//! if(ui32LinkState == USB_HOST_LPM_L1)
+//! {
+//!     //
+//!     // Handle the supported L1 link state.
+//!     //
+//! }
+//! else
+//! {
+//!     //
+//!     // Handle the unsupported link state.
+//!     //
+//! }
+//! \endverbatim
+//!
+//! \note The USB LPM feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return The current LPM link state.
+//
+//*****************************************************************************
+uint32_t
+USBLPMLinkStateGet(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    return(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_LS_M);
+}
+
+//*****************************************************************************
+//
+//! Returns the current LPM endpoint value.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current LPM endpoint value.  The meaning of the
+//! value depends on the mode of operation of the USB controller.  When in
+//! device mode, the value returned is the endpoint that received the last
+//! LPM transaction.  When in host mode this is the endpoint that was last
+//! sent an LPM transaction, or the endpoint that is configured to be sent when
+//! the LPM transaction is triggered.  The value returned is in the
+//! \b USB_EP_[0-7] value and a direct endpoint index.
+//!
+//! \b Example: Get the endpoint for the last LPM transaction.
+//!
+//! \verbatim
+//! uint32_t ui32Endpoint;
+//!
+//! //
+//! // Get the endpoint number that received the LPM request.
+//! //
+//! ui32LinkState = USBLPMEndpointGet(USB0_BASE);
+//!
+//! \endverbatim
+//!
+//! \note The USB LPM feature is not available on all Tiva devices. Please
+//! consult the data sheet for the Tiva device that you are using to determine
+//! if this feature is available.
+//!
+//! \return The last endpoint to receive an LPM request in device mode or the
+//! endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7]
+//! values.
+//
+//*****************************************************************************
+uint32_t
+USBLPMEndpointGet(uint32_t ui32Base)
+{
+    uint32_t ui32Endpoint;
+
+    ASSERT(ui32Base == USB0_BASE);
+
+    ui32Endpoint = (HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_ENDPT_M) >>
+                   USB_LPMATTR_ENDPT_S;
+
+    return(IndexToUSBEP(ui32Endpoint));
+}
+
+//*****************************************************************************
+//
+//! Returns if remote wake is currently enabled.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current state of the remote wake setting for host
+//! or device mode operation.  If the controller is acting as a host this
+//! returns the current setting that is sent to devices when LPM requests are
+//! sent to a device.  If the controller is in device mode, this function
+//! returns the state of the last LPM request sent from the host and indicates
+//! if the host enabled remote wakeup.
+//!
+//! \b Example: Issue remote wake if remote wake is enabled.
+//!
+//! \verbatim
+//!
+//! if(USBLPMRemoteWakeEnabled(USB0_BASE))
+//! {
+//!     USBDevLPMRemoteWake(USB0_BASE);
+//! }
+//!
+//! \endverbatim
+//!
+//! \note The USB LPM feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return The \b true if remote wake is enabled or \b false if it is not.
+//
+//*****************************************************************************
+bool
+USBLPMRemoteWakeEnabled(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    if(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_RMTWAK)
+    {
+        return(true);
+    }
+    return(false);
+}
+
+//*****************************************************************************
+//
+//! Returns the current LPM interrupt status.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current LPM interrupt status for the USB
+//! controller.
+//!
+//! The valid interrupt status bits when the USB controller is acting as a host
+//! are the following:
+//!
+//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM
+//!   transaction.
+//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low
+//!   power state.
+//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout
+//!   occurred or there were bit errors in the response for three attempts.
+//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction.
+//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM
+//!   transaction.
+//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction.
+//!
+//! The valid interrupt status bits when the USB controller is acting as a
+//! device are the following:
+//!
+//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an
+//!   unsupported link state field.  The transaction was stalled, but the
+//!   requested link state can still be read using the USBLPMLinkStateGet()
+//!   function.
+//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low
+//!   power state.
+//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM
+//!   transaction with a NYET because data was still in the transmit FIFOs.
+//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and
+//!   is now in the LPM suspend mode.
+//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction
+//!   with a NYET because LPM transactions are not yet enabled by a call to
+//!   USBDevLPMEnable().
+//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM
+//!   transaction.
+//!
+//! \note This call clears the source of all LPM status interrupts, so the
+//! caller must take care to save the value returned because a subsequent call
+//! to USBLPMIntStatus() does not return the previous value.
+//!
+//! \b Example: Get the current LPM interrupt status.
+//!
+//! \verbatim
+//! uint32_t ui32LPMIntStatus;
+//!
+//! //
+//! // Get the current LPM interrupt status.
+//! //
+//! ui32LPMIntStatus = USBLPMIntStatus(USB0_BASE);
+//!
+//! //
+//! // Check if an LPM transaction was acknowledged.
+//! //
+//! if(ui32LPMIntStatus & USB_INTLPM_ACK)
+//! {
+//!     //
+//!     // Handle entering LPM suspend mode.
+//!     //
+//!     ...
+//! }
+//! \endverbatim
+//!
+//! \note The USB LPM feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return The current LPM interrupt status.
+//
+//*****************************************************************************
+uint32_t
+USBLPMIntStatus(uint32_t ui32Base)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Return the current raw interrupt status.
+    //
+    return(HWREGB(ui32Base + USB_O_LPMRIS));
+}
+
+//*****************************************************************************
+//
+//! Enables LPM interrupts.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Ints specifies which LPM interrupts to enable.
+//!
+//! This function enables a set of LPM interrupts so that they can trigger a
+//! USB interrupt.  The \e ui32Ints parameter specifies which of the
+//! \b USB_INTLPM_* to enable.
+//!
+//! The valid interrupt status bits when the USB controller is acting as a host
+//! are the following:
+//!
+//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM
+//!   transaction.
+//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power
+//!   state.
+//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout
+//!   occurred or there were bit errors in the response for three attempts.
+//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction.
+//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM
+//!   transaction.
+//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction.
+//!
+//! The valid interrupt status bits when the USB controller is acting as a
+//! device are the following:
+//!
+//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an
+//!   unsupported link state field.  The transaction was stalled, but the
+//!   requested link state can still be read using the USBLPMLinkStateGet()
+//!   function.
+//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low
+//!   power state.
+//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM
+//!   transaction with a NYET because data was still in the transmit FIFOs.
+//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and
+//!   is now in the LPM suspend mode.
+//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction
+//!   with a NYET because LPM transactions are not yet enabled by a call to
+//!   USBDevLPMEnable().
+//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM
+//!   transaction.
+//!
+//! \b Example: Enable all LPM interrupt sources.
+//!
+//! \verbatim
+//! //
+//! // Enable all LPM interrupt sources.
+//! //
+//! USBLPMIntEnable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME |
+//!                            USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK |
+//!                            USB_INTLPM_NYET | USB_INTLPM_STALL);
+//! \endverbatim
+//!
+//! \note The USB LPM feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Enable the requested interrupts.
+    //
+    HWREGB(ui32Base + USB_O_LPMIM) |= ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Disables LPM interrupts.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Ints specifies which LPM interrupts to disable.
+//!
+//! This function disables the LPM interrupts specified in the \e ui32Ints
+//! parameter, preventing them from triggering a USB interrupt.
+//!
+//! The valid interrupt status bits when the USB controller is acting as a host
+//! are the following:
+//!
+//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM
+//!   transaction.
+//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power
+//!   state.
+//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout
+//!   occurred or there were bit errors in the response for three attempts.
+//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction.
+//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM
+//!   transaction.
+//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction.
+//!
+//! The valid interrupt status bits when the USB controller is acting as a
+//! device are the following:
+//!
+//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an
+//!   unsupported link state field.  The transaction was stalled, but the
+//!   requested link state can still be read using the USBLPMLinkStateGet()
+//!   function.
+//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low
+//!   power state.
+//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM
+//!   transaction with a NYET because data was still in the transmit FIFOs.
+//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and
+//!   is now in the LPM suspend mode.
+//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction
+//!   with a NYET because LPM transactions are not yet enabled by a call to
+//!   USBDevLPMEnable().
+//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM
+//!   transaction.
+//!
+//! \b Example: Disable all LPM interrupt sources.
+//!
+//! \verbatim
+//! //
+//! // Disable all LPM interrupt sources.
+//! //
+//! USBLPMIntDisable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME |
+//!                             USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK |
+//!                             USB_INTLPM_NYET | USB_INTLPM_STALL);
+//! \endverbatim
+//!
+//! \note The USB LPM feature is not available on all Tiva devices.
+//! Please consult the data sheet for the Tiva device that you
+//! are using to determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints)
+{
+    ASSERT(ui32Base == USB0_BASE);
+
+    //
+    // Disable the requested interrupts.
+    //
+    HWREGB(ui32Base + USB_O_LPMIM) &= ~ui32Ints;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/usb.h b/bsp/tm4c129x/libraries/driverlib/usb.h
new file mode 100644
index 0000000000..4ebad9d9a1
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/usb.h
@@ -0,0 +1,658 @@
+//*****************************************************************************
+//
+// usb.h - Prototypes for the USB Interface Driver.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_USB_H__
+#define __DRIVERLIB_USB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableControl() and
+// USBIntDisableControl() as the ui32Flags parameter, and are returned from
+// USBIntStatusControl().
+//
+//*****************************************************************************
+#define USB_INTCTRL_ALL         0x000003FF  // All control interrupt sources
+#define USB_INTCTRL_STATUS      0x000000FF  // Status Interrupts
+#define USB_INTCTRL_VBUS_ERR    0x00000080  // VBUS Error
+#define USB_INTCTRL_SESSION     0x00000040  // Session Start Detected
+#define USB_INTCTRL_SESSION_END 0x00000040  // Session End Detected
+#define USB_INTCTRL_DISCONNECT  0x00000020  // Disconnect Detected
+#define USB_INTCTRL_CONNECT     0x00000010  // Device Connect Detected
+#define USB_INTCTRL_SOF         0x00000008  // Start of Frame Detected
+#define USB_INTCTRL_BABBLE      0x00000004  // Babble signaled
+#define USB_INTCTRL_RESET       0x00000004  // Reset signaled
+#define USB_INTCTRL_RESUME      0x00000002  // Resume detected
+#define USB_INTCTRL_SUSPEND     0x00000001  // Suspend detected
+#define USB_INTCTRL_MODE_DETECT 0x00000200  // Mode value valid
+#define USB_INTCTRL_POWER_FAULT 0x00000100  // Power Fault detected
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableEndpoint() and
+// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from
+// USBIntStatusEndpoint().
+//
+//*****************************************************************************
+#define USB_INTEP_ALL           0xFFFFFFFF  // Host IN Interrupts
+#define USB_INTEP_HOST_IN       0xFFFE0000  // Host IN Interrupts
+#define USB_INTEP_HOST_IN_15    0x80000000  // Endpoint 15 Host IN Interrupt
+#define USB_INTEP_HOST_IN_14    0x40000000  // Endpoint 14 Host IN Interrupt
+#define USB_INTEP_HOST_IN_13    0x20000000  // Endpoint 13 Host IN Interrupt
+#define USB_INTEP_HOST_IN_12    0x10000000  // Endpoint 12 Host IN Interrupt
+#define USB_INTEP_HOST_IN_11    0x08000000  // Endpoint 11 Host IN Interrupt
+#define USB_INTEP_HOST_IN_10    0x04000000  // Endpoint 10 Host IN Interrupt
+#define USB_INTEP_HOST_IN_9     0x02000000  // Endpoint 9 Host IN Interrupt
+#define USB_INTEP_HOST_IN_8     0x01000000  // Endpoint 8 Host IN Interrupt
+#define USB_INTEP_HOST_IN_7     0x00800000  // Endpoint 7 Host IN Interrupt
+#define USB_INTEP_HOST_IN_6     0x00400000  // Endpoint 6 Host IN Interrupt
+#define USB_INTEP_HOST_IN_5     0x00200000  // Endpoint 5 Host IN Interrupt
+#define USB_INTEP_HOST_IN_4     0x00100000  // Endpoint 4 Host IN Interrupt
+#define USB_INTEP_HOST_IN_3     0x00080000  // Endpoint 3 Host IN Interrupt
+#define USB_INTEP_HOST_IN_2     0x00040000  // Endpoint 2 Host IN Interrupt
+#define USB_INTEP_HOST_IN_1     0x00020000  // Endpoint 1 Host IN Interrupt
+
+#define USB_INTEP_DEV_OUT       0xFFFE0000  // Device OUT Interrupts
+#define USB_INTEP_DEV_OUT_15    0x80000000  // Endpoint 15 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_14    0x40000000  // Endpoint 14 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_13    0x20000000  // Endpoint 13 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_12    0x10000000  // Endpoint 12 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_11    0x08000000  // Endpoint 11 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_10    0x04000000  // Endpoint 10 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_9     0x02000000  // Endpoint 9 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_8     0x01000000  // Endpoint 8 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_7     0x00800000  // Endpoint 7 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_6     0x00400000  // Endpoint 6 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_5     0x00200000  // Endpoint 5 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_4     0x00100000  // Endpoint 4 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_3     0x00080000  // Endpoint 3 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_2     0x00040000  // Endpoint 2 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_1     0x00020000  // Endpoint 1 Device OUT Interrupt
+
+#define USB_INTEP_HOST_OUT      0x0000FFFE  // Host OUT Interrupts
+#define USB_INTEP_HOST_OUT_15   0x00008000  // Endpoint 15 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_14   0x00004000  // Endpoint 14 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_13   0x00002000  // Endpoint 13 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_12   0x00001000  // Endpoint 12 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_11   0x00000800  // Endpoint 11 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_10   0x00000400  // Endpoint 10 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_9    0x00000200  // Endpoint 9 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_8    0x00000100  // Endpoint 8 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_7    0x00000080  // Endpoint 7 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_6    0x00000040  // Endpoint 6 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_5    0x00000020  // Endpoint 5 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_4    0x00000010  // Endpoint 4 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_3    0x00000008  // Endpoint 3 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_2    0x00000004  // Endpoint 2 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_1    0x00000002  // Endpoint 1 Host OUT Interrupt
+
+#define USB_INTEP_DEV_IN        0x0000FFFE  // Device IN Interrupts
+#define USB_INTEP_DEV_IN_15     0x00008000  // Endpoint 15 Device IN Interrupt
+#define USB_INTEP_DEV_IN_14     0x00004000  // Endpoint 14 Device IN Interrupt
+#define USB_INTEP_DEV_IN_13     0x00002000  // Endpoint 13 Device IN Interrupt
+#define USB_INTEP_DEV_IN_12     0x00001000  // Endpoint 12 Device IN Interrupt
+#define USB_INTEP_DEV_IN_11     0x00000800  // Endpoint 11 Device IN Interrupt
+#define USB_INTEP_DEV_IN_10     0x00000400  // Endpoint 10 Device IN Interrupt
+#define USB_INTEP_DEV_IN_9      0x00000200  // Endpoint 9 Device IN Interrupt
+#define USB_INTEP_DEV_IN_8      0x00000100  // Endpoint 8 Device IN Interrupt
+#define USB_INTEP_DEV_IN_7      0x00000080  // Endpoint 7 Device IN Interrupt
+#define USB_INTEP_DEV_IN_6      0x00000040  // Endpoint 6 Device IN Interrupt
+#define USB_INTEP_DEV_IN_5      0x00000020  // Endpoint 5 Device IN Interrupt
+#define USB_INTEP_DEV_IN_4      0x00000010  // Endpoint 4 Device IN Interrupt
+#define USB_INTEP_DEV_IN_3      0x00000008  // Endpoint 3 Device IN Interrupt
+#define USB_INTEP_DEV_IN_2      0x00000004  // Endpoint 2 Device IN Interrupt
+#define USB_INTEP_DEV_IN_1      0x00000002  // Endpoint 1 Device IN Interrupt
+
+#define USB_INTEP_0             0x00000001  // Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBSpeedGet().
+//
+//*****************************************************************************
+#define USB_UNDEF_SPEED         0x80000000  // Current speed is undefined
+#define USB_HIGH_SPEED          0x00000002  // Current speed is High Speed
+#define USB_FULL_SPEED          0x00000001  // Current speed is Full Speed
+#define USB_LOW_SPEED           0x00000000  // Current speed is Low Speed
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBEndpointStatus().  The
+// USB_HOST_* values are used when the USB controller is in host mode and the
+// USB_DEV_* values are used when the USB controller is in device mode.
+//
+//*****************************************************************************
+#define USB_HOST_IN_STATUS      0x114F0000  // Mask of all host IN interrupts
+#define USB_HOST_IN_PID_ERROR   0x10000000  // Stall on this endpoint received
+#define USB_HOST_IN_NOT_COMP    0x01000000  // Device failed to respond
+#define USB_HOST_IN_STALL       0x00400000  // Stall on this endpoint received
+#define USB_HOST_IN_DATA_ERROR  0x00080000  // CRC or bit-stuff error
+                                            // (ISOC Mode)
+#define USB_HOST_IN_NAK_TO      0x00080000  // NAK received for more than the
+                                            // specified timeout period
+#define USB_HOST_IN_ERROR       0x00040000  // Failed to communicate with a
+                                            // device
+#define USB_HOST_IN_FIFO_FULL   0x00020000  // RX FIFO full
+#define USB_HOST_IN_PKTRDY      0x00010000  // Data packet ready
+#define USB_HOST_OUT_STATUS     0x000000A7  // Mask of all host OUT interrupts
+#define USB_HOST_OUT_NAK_TO     0x00000080  // NAK received for more than the
+                                            // specified timeout period
+#define USB_HOST_OUT_NOT_COMP   0x00000080  // No response from device
+                                            // (ISOC mode)
+#define USB_HOST_OUT_STALL      0x00000020  // Stall on this endpoint received
+#define USB_HOST_OUT_ERROR      0x00000004  // Failed to communicate with a
+                                            // device
+#define USB_HOST_OUT_FIFO_NE    0x00000002  // TX FIFO is not empty
+#define USB_HOST_OUT_PKTPEND    0x00000001  // Transmit still being transmitted
+#define USB_HOST_EP0_NAK_TO     0x00000080  // NAK received for more than the
+                                            // specified timeout period
+#define USB_HOST_EP0_STATUS     0x00000040  // This was a status packet
+#define USB_HOST_EP0_ERROR      0x00000010  // Failed to communicate with a
+                                            // device
+#define USB_HOST_EP0_RX_STALL   0x00000004  // Stall on this endpoint received
+#define USB_HOST_EP0_RXPKTRDY   0x00000001  // Receive data packet ready
+#define USB_DEV_RX_PID_ERROR    0x01000000  // PID error in isochronous
+                                            // transfer
+#define USB_DEV_RX_SENT_STALL   0x00400000  // Stall was sent on this endpoint
+#define USB_DEV_RX_DATA_ERROR   0x00080000  // CRC error on the data
+#define USB_DEV_RX_OVERRUN      0x00040000  // OUT packet was not loaded due to
+                                            // a full FIFO
+#define USB_DEV_RX_FIFO_FULL    0x00020000  // RX FIFO full
+#define USB_DEV_RX_PKT_RDY      0x00010000  // Data packet ready
+#define USB_DEV_TX_NOT_COMP     0x00000080  // Large packet split up, more data
+                                            // to come
+#define USB_DEV_TX_SENT_STALL   0x00000020  // Stall was sent on this endpoint
+#define USB_DEV_TX_UNDERRUN     0x00000004  // IN received with no data ready
+#define USB_DEV_TX_FIFO_NE      0x00000002  // The TX FIFO is not empty
+#define USB_DEV_TX_TXPKTRDY     0x00000001  // Transmit still being transmitted
+#define USB_DEV_EP0_SETUP_END   0x00000010  // Control transaction ended before
+                                            // Data End seen
+#define USB_DEV_EP0_SENT_STALL  0x00000004  // Stall was sent on this endpoint
+#define USB_DEV_EP0_IN_PKTPEND  0x00000002  // Transmit data packet pending
+#define USB_DEV_EP0_OUT_PKTRDY  0x00000001  // Receive data packet ready
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostEndpointConfig() and
+// USBDevEndpointConfigSet() as the ui32Flags parameter.
+//
+//*****************************************************************************
+#define USB_EP_AUTO_SET         0x00000001  // Auto set feature enabled
+#define USB_EP_AUTO_REQUEST     0x00000002  // Auto request feature enabled
+#define USB_EP_AUTO_CLEAR       0x00000004  // Auto clear feature enabled
+#define USB_EP_DMA_MODE_0       0x00000008  // Enable DMA access using mode 0
+#define USB_EP_DMA_MODE_1       0x00000010  // Enable DMA access using mode 1
+#define USB_EP_DIS_NYET         0x00000020  // Disable NYET response for
+                                            // high-speed Bulk and Interrupt
+                                            // endpoints in device mode.
+#define USB_EP_MODE_ISOC        0x00000000  // Isochronous endpoint
+#define USB_EP_MODE_BULK        0x00000100  // Bulk endpoint
+#define USB_EP_MODE_INT         0x00000200  // Interrupt endpoint
+#define USB_EP_MODE_CTRL        0x00000300  // Control endpoint
+#define USB_EP_MODE_MASK        0x00000300  // Mode Mask
+#define USB_EP_SPEED_LOW        0x00000000  // Low Speed
+#define USB_EP_SPEED_FULL       0x00001000  // Full Speed
+#define USB_EP_SPEED_HIGH       0x00004000  // High Speed
+#define USB_EP_HOST_IN          0x00000000  // Host IN endpoint
+#define USB_EP_HOST_OUT         0x00002000  // Host OUT endpoint
+#define USB_EP_DEV_IN           0x00002000  // Device IN endpoint
+#define USB_EP_DEV_OUT          0x00000000  // Device OUT endpoint
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostPwrConfig() as the
+// ui32Flags parameter.
+//
+//*****************************************************************************
+#define USB_HOST_PWRFLT_LOW     0x00000010
+#define USB_HOST_PWRFLT_HIGH    0x00000030
+#define USB_HOST_PWRFLT_EP_NONE 0x00000000
+#define USB_HOST_PWRFLT_EP_TRI  0x00000140
+#define USB_HOST_PWRFLT_EP_LOW  0x00000240
+#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
+#define USB_HOST_PWREN_MAN_LOW  0x00000000
+#define USB_HOST_PWREN_MAN_HIGH 0x00000001
+#define USB_HOST_PWREN_AUTOLOW  0x00000002
+#define USB_HOST_PWREN_AUTOHIGH 0x00000003
+#define USB_HOST_PWREN_FILTER   0x00010000
+
+//*****************************************************************************
+//
+// The following are the valid values that can be passed to the
+// USBHostLPMConfig() function in the ui32Config parameter.
+//
+//*****************************************************************************
+#define USB_HOST_LPM_RMTWAKE    0x00000100
+#define USB_HOST_LPM_L1         0x00000001
+
+//*****************************************************************************
+//
+// The following are the valid values that can be passed to the
+// USBDevLPMConfig() function in the ui32Config parameter.
+//
+//*****************************************************************************
+#define USB_DEV_LPM_NAK         0x00000010
+#define USB_DEV_LPM_NONE        0x00000000
+#define USB_DEV_LPM_EN          0x0000000c
+#define USB_DEV_LPM_EXTONLY     0x00000004
+
+//*****************************************************************************
+//
+// The following are the valid values that are returned from the
+// USBLPMLinkStateGet() function.
+//
+//*****************************************************************************
+#define USB_DEV_LPM_LS_RMTWAKE  0x00000100
+#define USB_DEV_LPM_LS_L1       0x00000001
+
+//*****************************************************************************
+//
+// The following are the valid values that are passed to the USBLPMIntEnable()
+// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus()
+// function.
+//
+//*****************************************************************************
+#define USB_INTLPM_ERROR        0x00000020
+#define USB_INTLPM_RESUME       0x00000010
+#define USB_INTLPM_INCOMPLETE   0x00000008
+#define USB_INTLPM_ACK          0x00000004
+#define USB_INTLPM_NYET         0x00000002
+#define USB_INTLPM_STALL        0x00000001
+
+//*****************************************************************************
+//
+// The following are the valid values that are passed to the USBClockEnable()
+// functions.
+//
+//*****************************************************************************
+#define USB_CLOCK_INTERNAL      0x00000200
+#define USB_CLOCK_EXTERNAL      0x00000300
+
+//*****************************************************************************
+//
+// The configuration options used with the USBULPIConfig() API.
+//
+//*****************************************************************************
+#define USB_ULPI_EXTVBUS        0x00000001
+#define USB_ULPI_EXTVBUS_IND    0x00000002
+
+//*****************************************************************************
+//
+// The following are special values that can be passed to
+// USBHostEndpointConfig() as the ui32NAKPollInterval parameter.
+//
+//*****************************************************************************
+#define MAX_NAK_LIMIT           31          // Maximum NAK interval
+#define DISABLE_NAK_LIMIT       0           // No NAK timeouts
+
+//*****************************************************************************
+//
+// This value specifies the maximum size of transfers on endpoint 0 as 64
+// bytes.  This value is fixed in hardware as the FIFO size for endpoint 0.
+//
+//*****************************************************************************
+#define MAX_PACKET_SIZE_EP0     64
+
+//*****************************************************************************
+//
+// These values are used to indicate which endpoint to access.
+//
+//*****************************************************************************
+#define USB_EP_0                0x00000000  // Endpoint 0
+#define USB_EP_1                0x00000010  // Endpoint 1
+#define USB_EP_2                0x00000020  // Endpoint 2
+#define USB_EP_3                0x00000030  // Endpoint 3
+#define USB_EP_4                0x00000040  // Endpoint 4
+#define USB_EP_5                0x00000050  // Endpoint 5
+#define USB_EP_6                0x00000060  // Endpoint 6
+#define USB_EP_7                0x00000070  // Endpoint 7
+#define NUM_USB_EP              8           // Number of supported endpoints
+
+//*****************************************************************************
+//
+// These macros allow conversion between 0-based endpoint indices and the
+// USB_EP_x values required when calling various USB APIs.
+//
+//*****************************************************************************
+#define IndexToUSBEP(x)         ((x) << 4)
+#define USBEPToIndex(x)         ((x) >> 4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBFIFOConfigSet() as the
+// ui32FIFOSize parameter.
+//
+//*****************************************************************************
+#define USB_FIFO_SZ_8           0x00000000  // 8 byte FIFO
+#define USB_FIFO_SZ_16          0x00000001  // 16 byte FIFO
+#define USB_FIFO_SZ_32          0x00000002  // 32 byte FIFO
+#define USB_FIFO_SZ_64          0x00000003  // 64 byte FIFO
+#define USB_FIFO_SZ_128         0x00000004  // 128 byte FIFO
+#define USB_FIFO_SZ_256         0x00000005  // 256 byte FIFO
+#define USB_FIFO_SZ_512         0x00000006  // 512 byte FIFO
+#define USB_FIFO_SZ_1024        0x00000007  // 1024 byte FIFO
+#define USB_FIFO_SZ_2048        0x00000008  // 2048 byte FIFO
+
+//*****************************************************************************
+//
+// This macro allow conversion from a FIFO size label as defined above to
+// a number of bytes
+//
+//*****************************************************************************
+#define USBFIFOSizeToBytes(x)   (8 << (x))
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBEndpointDataSend() as the
+// ui32TransType parameter.
+//
+//*****************************************************************************
+#define USB_TRANS_OUT           0x00000102  // Normal OUT transaction
+#define USB_TRANS_IN            0x00000102  // Normal IN transaction
+#define USB_TRANS_IN_LAST       0x0000010a  // Final IN transaction (for
+                                            // endpoint 0 in device mode)
+#define USB_TRANS_SETUP         0x0000110a  // Setup transaction (for endpoint
+                                            // 0)
+#define USB_TRANS_STATUS        0x00000142  // Status transaction (for endpoint
+                                            // 0)
+
+//*****************************************************************************
+//
+// The following are values are returned by the USBModeGet function.
+//
+//*****************************************************************************
+#define USB_DUAL_MODE_HOST      0x00000001  // Dual mode controller is in Host
+                                            // mode.
+#define USB_DUAL_MODE_DEVICE    0x00000081  // Dual mode controller is in
+                                            // Device mode.
+#define USB_DUAL_MODE_NONE      0x00000080  // Dual mode controller mode is not
+                                            // set.
+#define USB_OTG_MODE_ASIDE_HOST 0x0000001d  // OTG controller on the A side of
+                                            // the cable.
+#define USB_OTG_MODE_ASIDE_NPWR 0x00000001  // OTG controller on the A side of
+                                            // the cable.
+#define USB_OTG_MODE_ASIDE_SESS 0x00000009  // OTG controller on the A side of
+                                            // the cable Session Valid.
+#define USB_OTG_MODE_ASIDE_AVAL 0x00000011  // OTG controller on the A side of
+                                            // the cable A valid.
+#define USB_OTG_MODE_ASIDE_DEV  0x00000019  // OTG controller on the A side of
+                                            // the cable.
+#define USB_OTG_MODE_BSIDE_HOST 0x0000009d  // OTG controller on the B side of
+                                            // the cable.
+#define USB_OTG_MODE_BSIDE_DEV  0x00000099  // OTG controller on the B side of
+                                            // the cable.
+#define USB_OTG_MODE_BSIDE_NPWR 0x00000081  // OTG controller on the B side of
+                                            // the cable.
+#define USB_OTG_MODE_NONE       0x00000080  // OTG controller mode is not set.
+
+//*****************************************************************************
+//
+// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus()
+// APIs.
+//
+//*****************************************************************************
+#define USB_DMA_INT_CH8         0x00000080
+#define USB_DMA_INT_CH7         0x00000040
+#define USB_DMA_INT_CH6         0x00000020
+#define USB_DMA_INT_CH5         0x00000010
+#define USB_DMA_INT_CH4         0x00000008
+#define USB_DMA_INT_CH3         0x00000004
+#define USB_DMA_INT_CH2         0x00000002
+#define USB_DMA_INT_CH1         0x00000001
+
+//*****************************************************************************
+//
+// The values for the USBDMAChannelStatus() API.
+//
+//*****************************************************************************
+#define USB_DMA_STATUS_ERROR    0x00000100
+
+//*****************************************************************************
+//
+// The valid return values for the USBControllerVersion() API.
+//
+//*****************************************************************************
+#define USB_CONTROLLER_VER_0    0x00000000  // This is for Blizzard class
+                                            // devices.
+#define USB_CONTROLLER_VER_1    0x00000001  // This is for Snowflake class
+                                            // devices.
+
+//*****************************************************************************
+//
+// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or
+// USBDMAChannelConfig().
+//
+//*****************************************************************************
+#define USB_DMA_CFG_BURST_NONE  0x00000000
+#define USB_DMA_CFG_BURST_4     0x00000200
+#define USB_DMA_CFG_BURST_8     0x00000400
+#define USB_DMA_CFG_BURST_16    0x00000600
+#define USB_DMA_CFG_INT_EN      0x00000008
+#define USB_DMA_CFG_MODE_0      0x00000000
+#define USB_DMA_CFG_MODE_1      0x00000004
+#define USB_DMA_CFG_DIR_RX      0x00000000
+#define USB_DMA_CFG_DIR_TX      0x00000002
+#define USB_DMA_CFG_EN          0x00000001
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBModeConfig() as the
+// ui3Mode parameter.
+//
+//*****************************************************************************
+#define USB_MODE_HOST_VBUS      0x00000004
+#define USB_MODE_HOST           0x00000002
+#define USB_MODE_DEV_VBUS       0x00000005
+#define USB_MODE_DEV            0x00000003
+#define USB_MODE_OTG            0x00000000
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern uint32_t USBDevAddrGet(uint32_t ui32Base);
+extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address);
+extern void USBDevConnect(uint32_t ui32Base);
+extern void USBDevDisconnect(uint32_t ui32Base);
+extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                    uint32_t ui32MaxPacketSize,
+                                    uint32_t ui32Flags);
+extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                    uint32_t *pui32MaxPacketSize,
+                                    uint32_t *pui32Flags);
+extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  bool bIsLastPacket);
+extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                uint32_t ui32Flags);
+extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                     uint32_t ui32Flags);
+extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                      uint32_t ui32Flags);
+extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                 uint32_t ui32Flags);
+extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  uint32_t ui32Flags);
+extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                    uint32_t ui32Config);
+extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  uint8_t *pui8Data, uint32_t *pui32Size);
+extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  uint8_t *pui8Data, uint32_t ui32Size);
+extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                   uint32_t ui32TransType);
+extern void USBEndpointDataToggleClear(uint32_t ui32Base,
+                                       uint32_t ui32Endpoint,
+                                       uint32_t ui32Flags);
+extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                      uint32_t ui32Count);
+extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                             uint32_t *pui32FIFOAddress,
+                             uint32_t *pui32FIFOSize, uint32_t ui32Flags);
+extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                             uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
+                             uint32_t ui32Flags);
+extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint,
+                         uint32_t ui32Flags);
+extern uint32_t USBFrameNumberGet(uint32_t ui32Base);
+extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                               uint32_t ui32Flags);
+extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                           uint32_t ui32Addr, uint32_t ui32Flags);
+extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  uint32_t ui32MaxPacketSize,
+                                  uint32_t ui32NAKPollInterval,
+                                  uint32_t ui32TargetEndpoint,
+                                  uint32_t ui32Flags);
+extern void USBHostEndpointDataAck(uint32_t ui32Base,
+                                   uint32_t ui32Endpoint);
+extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                      bool bDataToggle, uint32_t ui32Flags);
+extern void USBHostEndpointStatusClear(uint32_t ui32Base,
+                                       uint32_t ui32Endpoint,
+                                       uint32_t ui32Flags);
+extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  uint32_t ui32Flags);
+extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+                              uint32_t ui32Addr, uint32_t ui32Flags);
+extern void USBHostPwrDisable(uint32_t ui32Base);
+extern void USBHostPwrEnable(uint32_t ui32Base);
+extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags);
+extern void USBHostPwrFaultDisable(uint32_t ui32Base);
+extern void USBHostPwrFaultEnable(uint32_t ui32Base);
+extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBHostRequestStatus(uint32_t ui32Base);
+extern void USBHostReset(uint32_t ui32Base, bool bStart);
+extern void USBHostResume(uint32_t ui32Base, bool bStart);
+extern uint32_t USBHostSpeedGet(uint32_t ui32Base);
+extern void USBHostSuspend(uint32_t ui32Base);
+extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t USBIntStatusControl(uint32_t ui32Base);
+extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base);
+extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void USBIntUnregister(uint32_t ui32Base);
+extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart);
+extern uint32_t USBModeGet(uint32_t ui32Base);
+extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                  uint32_t ui32Channel);
+extern uint32_t USBControllerVersion(uint32_t ui32Base);
+extern uint32_t USBDMAChannelIntStatus(uint32_t ui32Base);
+extern void USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel,
+                                   uint32_t ui32Endpoint, uint32_t ui32Config);
+extern void USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel,
+                                    void *pvAddress);
+extern void *USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel);
+extern void USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Count,
+                                  uint32_t ui32Channel);
+extern uint32_t USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel);
+extern uint32_t USBDMANumChannels(uint32_t ui32Base);
+extern void USBDMAChannelAssign(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                uint32_t ui32Channel, uint32_t ui32Flags);
+extern void USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel);
+extern void USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel);
+extern void USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel);
+extern void USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel);
+extern uint32_t USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel);
+extern void USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel,
+                                     uint32_t ui32Status);
+extern void USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                 uint32_t ui32Flags);
+extern void USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint,
+                                bool bEnable);
+extern void USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address,
+                           uint32_t uiEndpoint);
+extern void USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime,
+                             uint32_t ui32Config);
+extern bool USBLPMRemoteWakeEnabled(uint32_t ui32Base);
+extern void USBHostLPMResume(uint32_t ui32Base);
+extern void USBDevLPMRemoteWake(uint32_t ui32Base);
+extern void USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config);
+extern void USBDevLPMEnable(uint32_t ui32Base);
+extern void USBDevLPMDisable(uint32_t ui32Base);
+extern uint32_t USBLPMLinkStateGet(uint32_t ui32Base);
+extern uint32_t USBLPMEndpointGet(uint32_t ui32Base);
+extern uint32_t USBLPMIntStatus(uint32_t ui32Base);
+extern void USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints);
+extern void USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints);
+extern void USBHighSpeed(uint32_t ui32Base, bool bEnable);
+extern uint32_t USBDevSpeedGet(uint32_t ui32Base);
+extern void USBClockEnable(uint32_t ui32Base, uint32_t ui32Div,
+                           uint32_t ui32Flags);
+extern void USBClockDisable(uint32_t ui32Base);
+extern void USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config);
+extern void USBULPIEnable(uint32_t ui32Base);
+extern void USBULPIDisable(uint32_t ui32Base);
+extern uint8_t USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg);
+extern void USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg,
+                            uint8_t ui8Data);
+extern void USBHostMode(uint32_t ui32Base);
+extern void USBDevMode(uint32_t ui32Base);
+extern void USBOTGMode(uint32_t ui32Base);
+extern void USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode);
+extern void USBPHYPowerOff(uint32_t ui32Base);
+extern void USBPHYPowerOn(uint32_t ui32Base);
+extern uint32_t USBNumEndpointsGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_USB_H__
diff --git a/bsp/tm4c129x/libraries/driverlib/watchdog.c b/bsp/tm4c129x/libraries/driverlib/watchdog.c
new file mode 100644
index 0000000000..62be8592df
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/watchdog.c
@@ -0,0 +1,622 @@
+//*****************************************************************************
+//
+// watchdog.c - Driver for the Watchdog Timer Module.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup watchdog_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_watchdog.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/watchdog.h"
+
+//*****************************************************************************
+//
+//! Determines if the watchdog timer is enabled.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function checks to see if the watchdog timer is enabled.
+//!
+//! \return Returns \b true if the watchdog timer is enabled and \b false
+//! if it is not.
+//
+//*****************************************************************************
+bool
+WatchdogRunning(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // See if the watchdog timer module is enabled, and return.
+    //
+    return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables the watchdog timer counter and interrupt.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Enable the watchdog timer module.
+    //
+    HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer reset.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables the capability of the watchdog timer to issue a reset
+//! to the processor after a second timeout condition.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Enable the watchdog reset.
+    //
+    HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer reset.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function disables the capability of the watchdog timer to issue a
+//! reset to the processor after a second timeout condition.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Disable the watchdog reset.
+    //
+    HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer lock mechanism.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function locks out write access to the watchdog timer registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogLock(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Lock out watchdog register writes.  Writing anything to the WDT_O_LOCK
+    // register causes the lock to go into effect.
+    //
+    HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer lock mechanism.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables write access to the watchdog timer registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogUnlock(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Unlock watchdog register writes.
+    //
+    HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
+}
+
+//*****************************************************************************
+//
+//! Gets the state of the watchdog timer lock mechanism.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function returns the lock state of the watchdog timer registers.
+//!
+//! \return Returns \b true if the watchdog timer registers are locked, and
+//! \b false if they are not locked.
+//
+//*****************************************************************************
+bool
+WatchdogLockState(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Get the lock state.
+    //
+    return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the watchdog timer reload value.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param ui32LoadVal is the load value for the watchdog timer.
+//!
+//! This function configures the value to load into the watchdog timer when the
+//! count reaches zero for the first time; if the watchdog timer is running
+//! when this function is called, then the value is immediately loaded into the
+//! watchdog timer counter.  If the \e ui32LoadVal parameter is 0, then an
+//! interrupt is immediately generated.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Set the load register.
+    //
+    HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal;
+}
+
+//*****************************************************************************
+//
+//! Gets the watchdog timer reload value.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function gets the value that is loaded into the watchdog timer when
+//! the count reaches zero for the first time.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+WatchdogReloadGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Get the load register.
+    //
+    return(HWREG(ui32Base + WDT_O_LOAD));
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer value.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function reads the current value of the watchdog timer.
+//!
+//! \return Returns the current value of the watchdog timer.
+//
+//*****************************************************************************
+uint32_t
+WatchdogValueGet(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Get the current watchdog timer register value.
+    //
+    return(HWREG(ui32Base + WDT_O_VALUE));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! watchdog timer interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler.  This
+//! function also enables the global interrupt in the interrupt controller; the
+//! watchdog timer interrupt must be enabled via WatchdogEnable().  It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! WatchdogIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note For parts with a watchdog timer module that has the ability to
+//! generate an NMI instead of a standard interrupt, this function registers
+//! the standard watchdog interrupt handler.  To register the NMI watchdog
+//! handler, use IntRegister() to register the handler for the
+//! \b FAULT_NMI interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_WATCHDOG_TM4C123, pfnHandler);
+
+    //
+    // Enable the watchdog timer interrupt.
+    //
+    IntEnable(INT_WATCHDOG_TM4C123);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function does the actual unregistering of the interrupt handler.  This
+//! function clears the handler to be called when a watchdog timer interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note For parts with a watchdog timer module that has the ability to
+//! generate an NMI instead of a standard interrupt, this function unregisters
+//! the standard watchdog interrupt handler.  To unregister the NMI watchdog
+//! handler, use IntUnregister() to unregister the handler for the
+//! \b FAULT_NMI interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntUnregister(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_WATCHDOG_TM4C123);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_WATCHDOG_TM4C123);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables the watchdog timer interrupt.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Enable the watchdog interrupt.
+    //
+    HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer interrupt status.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the watchdog timer module.
+//! Either the raw interrupt status or the status of interrupt that is allowed
+//! to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, where a 1 indicates that the
+//! watchdog interrupt is active, and a 0 indicates that it is not active.
+//
+//*****************************************************************************
+uint32_t
+WatchdogIntStatus(uint32_t ui32Base, bool bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Return either the interrupt status or the raw interrupt status as
+    // requested.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ui32Base + WDT_O_MIS));
+    }
+    else
+    {
+        return(HWREG(ui32Base + WDT_O_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! The watchdog timer interrupt source is cleared, so that it no longer
+//! asserts.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted). This function has no effect if the watchdog
+//! timer has been locked. 
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntClear(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Clear the interrupt source.
+    //
+    HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS;
+}
+
+//*****************************************************************************
+//
+//! Sets the type of interrupt generated by the watchdog.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param ui32Type is the type of interrupt to generate.
+//!
+//! This function sets the type of interrupt that is generated if the watchdog
+//! timer expires.  \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to
+//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to
+//! generate a non-maskable interrupt (NMI).
+//!
+//! When configured to generate an NMI, the watchdog interrupt must still be
+//! enabled with WatchdogIntEnable(), and it must still be cleared inside the
+//! NMI handler with WatchdogIntClear().
+//!
+//! \note The ability to select an NMI interrupt varies with the Tiva part
+//! in use.  Please consult the datasheet for the part you are using to
+//! determine whether this support is available. This function has no effect if
+//! the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+    ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) ||
+           (ui32Type == WATCHDOG_INT_TYPE_NMI));
+
+    //
+    // Set the interrupt type.
+    //
+    HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) &
+                                   ~WDT_CTL_INTTYPE) | ui32Type;
+}
+
+//*****************************************************************************
+//
+//! Enables stalling of the watchdog timer during debug events.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function allows the watchdog timer to stop counting when the processor
+//! is stopped by the debugger.  By doing so, the watchdog is prevented from
+//! expiring (typically almost immediately from a human time perspective) and
+//! resetting the system (if reset is enabled).  The watchdog instead expires
+//! after the appropriate number of processor cycles have been executed while
+//! debugging (or at the appropriate time after the processor has been
+//! restarted).
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Enable timer stalling.
+    //
+    HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL;
+}
+
+//*****************************************************************************
+//
+//! Disables stalling of the watchdog timer during debug events.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function disables the debug mode stall of the watchdog timer.  By
+//! doing so, the watchdog timer continues to count regardless of the processor
+//! debug state.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+    //
+    // Disable timer stalling.
+    //
+    HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/tm4c129x/libraries/driverlib/watchdog.h b/bsp/tm4c129x/libraries/driverlib/watchdog.h
new file mode 100644
index 0000000000..b4dd66183c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/driverlib/watchdog.h
@@ -0,0 +1,95 @@
+//*****************************************************************************
+//
+// watchdog.h - Prototypes for the Watchdog Timer API
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_WATCHDOG_H__
+#define __DRIVERLIB_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The type of interrupt that can be generated by the watchdog.
+//
+//*****************************************************************************
+#define WATCHDOG_INT_TYPE_INT   0x00000000
+#define WATCHDOG_INT_TYPE_NMI   0x00000004
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern bool WatchdogRunning(uint32_t ui32Base);
+extern void WatchdogEnable(uint32_t ui32Base);
+extern void WatchdogResetEnable(uint32_t ui32Base);
+extern void WatchdogResetDisable(uint32_t ui32Base);
+extern void WatchdogLock(uint32_t ui32Base);
+extern void WatchdogUnlock(uint32_t ui32Base);
+extern bool WatchdogLockState(uint32_t ui32Base);
+extern void WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal);
+extern uint32_t WatchdogReloadGet(uint32_t ui32Base);
+extern uint32_t WatchdogValueGet(uint32_t ui32Base);
+extern void WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void WatchdogIntUnregister(uint32_t ui32Base);
+extern void WatchdogIntEnable(uint32_t ui32Base);
+extern uint32_t WatchdogIntStatus(uint32_t ui32Base, bool bMasked);
+extern void WatchdogIntClear(uint32_t ui32Base);
+extern void WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type);
+extern void WatchdogStallEnable(uint32_t ui32Base);
+extern void WatchdogStallDisable(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_WATCHDOG_H__
diff --git a/bsp/tm4c129x/libraries/inc/asmdefs.h b/bsp/tm4c129x/libraries/inc/asmdefs.h
new file mode 100644
index 0000000000..dca0b2f0e0
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/asmdefs.h
@@ -0,0 +1,227 @@
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__             module
+#define __TEXT__                rseg CODE:CODE(2)
+#define __DATA__                rseg DATA:DATA(2)
+#define __BSS__                 rseg DATA:DATA(2)
+#define __TEXT_NOROOT__         rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               alignrom 2
+#define __END__                 end
+#define __EXPORT__              export
+#define __IMPORT__              import
+#define __LABEL__
+#define __STR__                 dcb
+#define __THUMB_LABEL__         thumb
+#define __WORD__                dcd
+#define __INLINE_DATA__         data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    thumb
+    require8
+    preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__             ;
+#define __TEXT__                area ||.text||, code, readonly, align=2
+#define __DATA__                area ||.data||, data, align=2
+#define __BSS__                 area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__         area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               align 4
+#define __END__                 end
+#define __EXPORT__              export
+#define __IMPORT__              import
+#define __LABEL__
+#define __STR__                 dcb
+#define __THUMB_LABEL__
+#define __WORD__                dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_adc.h b/bsp/tm4c129x/libraries/inc/hw_adc.h
new file mode 100644
index 0000000000..615bb7225a
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_adc.h
@@ -0,0 +1,1307 @@
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS             0x00000000  // ADC Active Sample Sequencer
+#define ADC_O_RIS               0x00000004  // ADC Raw Interrupt Status
+#define ADC_O_IM                0x00000008  // ADC Interrupt Mask
+#define ADC_O_ISC               0x0000000C  // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT             0x00000010  // ADC Overflow Status
+#define ADC_O_EMUX              0x00000014  // ADC Event Multiplexer Select
+#define ADC_O_USTAT             0x00000018  // ADC Underflow Status
+#define ADC_O_TSSEL             0x0000001C  // ADC Trigger Source Select
+#define ADC_O_SSPRI             0x00000020  // ADC Sample Sequencer Priority
+#define ADC_O_SPC               0x00000024  // ADC Sample Phase Control
+#define ADC_O_PSSI              0x00000028  // ADC Processor Sample Sequence
+                                            // Initiate
+#define ADC_O_SAC               0x00000030  // ADC Sample Averaging Control
+#define ADC_O_DCISC             0x00000034  // ADC Digital Comparator Interrupt
+                                            // Status and Clear
+#define ADC_O_CTL               0x00000038  // ADC Control
+#define ADC_O_SSMUX0            0x00000040  // ADC Sample Sequence Input
+                                            // Multiplexer Select 0
+#define ADC_O_SSCTL0            0x00000044  // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0           0x00000048  // ADC Sample Sequence Result FIFO
+                                            // 0
+#define ADC_O_SSFSTAT0          0x0000004C  // ADC Sample Sequence FIFO 0
+                                            // Status
+#define ADC_O_SSOP0             0x00000050  // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0             0x00000054  // ADC Sample Sequence 0 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX0           0x00000058  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 0
+#define ADC_O_SSTSH0            0x0000005C  // ADC Sample Sequence 0 Sample and
+                                            // Hold Time
+#define ADC_O_SSMUX1            0x00000060  // ADC Sample Sequence Input
+                                            // Multiplexer Select 1
+#define ADC_O_SSCTL1            0x00000064  // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1           0x00000068  // ADC Sample Sequence Result FIFO
+                                            // 1
+#define ADC_O_SSFSTAT1          0x0000006C  // ADC Sample Sequence FIFO 1
+                                            // Status
+#define ADC_O_SSOP1             0x00000070  // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1             0x00000074  // ADC Sample Sequence 1 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX1           0x00000078  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 1
+#define ADC_O_SSTSH1            0x0000007C  // ADC Sample Sequence 1 Sample and
+                                            // Hold Time
+#define ADC_O_SSMUX2            0x00000080  // ADC Sample Sequence Input
+                                            // Multiplexer Select 2
+#define ADC_O_SSCTL2            0x00000084  // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2           0x00000088  // ADC Sample Sequence Result FIFO
+                                            // 2
+#define ADC_O_SSFSTAT2          0x0000008C  // ADC Sample Sequence FIFO 2
+                                            // Status
+#define ADC_O_SSOP2             0x00000090  // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2             0x00000094  // ADC Sample Sequence 2 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX2           0x00000098  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 2
+#define ADC_O_SSTSH2            0x0000009C  // ADC Sample Sequence 2 Sample and
+                                            // Hold Time
+#define ADC_O_SSMUX3            0x000000A0  // ADC Sample Sequence Input
+                                            // Multiplexer Select 3
+#define ADC_O_SSCTL3            0x000000A4  // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3           0x000000A8  // ADC Sample Sequence Result FIFO
+                                            // 3
+#define ADC_O_SSFSTAT3          0x000000AC  // ADC Sample Sequence FIFO 3
+                                            // Status
+#define ADC_O_SSOP3             0x000000B0  // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3             0x000000B4  // ADC Sample Sequence 3 Digital
+                                            // Comparator Select
+#define ADC_O_SSEMUX3           0x000000B8  // ADC Sample Sequence Extended
+                                            // Input Multiplexer Select 3
+#define ADC_O_SSTSH3            0x000000BC  // ADC Sample Sequence 3 Sample and
+                                            // Hold Time
+#define ADC_O_DCRIC             0x00000D00  // ADC Digital Comparator Reset
+                                            // Initial Conditions
+#define ADC_O_DCCTL0            0x00000E00  // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1            0x00000E04  // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2            0x00000E08  // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3            0x00000E0C  // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4            0x00000E10  // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5            0x00000E14  // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6            0x00000E18  // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7            0x00000E1C  // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0            0x00000E40  // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1            0x00000E44  // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2            0x00000E48  // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3            0x00000E4C  // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4            0x00000E50  // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5            0x00000E54  // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6            0x00000E58  // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7            0x00000E5C  // ADC Digital Comparator Range 7
+#define ADC_O_PP                0x00000FC0  // ADC Peripheral Properties
+#define ADC_O_PC                0x00000FC4  // ADC Peripheral Configuration
+#define ADC_O_CC                0x00000FC8  // ADC Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_BUSY          0x00010000  // ADC Busy
+#define ADC_ACTSS_ADEN3         0x00000800  // ADC SS3 DMA Enable
+#define ADC_ACTSS_ADEN2         0x00000400  // ADC SS2 DMA Enable
+#define ADC_ACTSS_ADEN1         0x00000200  // ADC SS1 DMA Enable
+#define ADC_ACTSS_ADEN0         0x00000100  // ADC SS1 DMA Enable
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
+                                            // Status
+#define ADC_RIS_DMAINR3         0x00000800  // SS3 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR2         0x00000400  // SS2 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR1         0x00000200  // SS1 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR0         0x00000100  // SS0 DMA Raw Interrupt Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
+                                            // SS3
+#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
+                                            // SS2
+#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
+                                            // SS1
+#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
+                                            // SS0
+#define ADC_IM_DMAMASK3         0x00000800  // SS3 DMA Interrupt Mask
+#define ADC_IM_DMAMASK2         0x00000400  // SS2 DMA Interrupt Mask
+#define ADC_IM_DMAMASK1         0x00000200  // SS1 DMA Interrupt Mask
+#define ADC_IM_DMAMASK0         0x00000100  // SS0 DMA Interrupt Mask
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
+                                            // Status on SS3
+#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
+                                            // Status on SS2
+#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
+                                            // Status on SS1
+#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
+                                            // Status on SS0
+#define ADC_ISC_DMAIN3          0x00000800  // SS3 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN2          0x00000400  // SS2 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN1          0x00000200  // SS1 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN0          0x00000100  // SS0 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO Pins)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM generator 0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM generator 1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM generator 2
+#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM generator 3
+#define ADC_EMUX_EM3_NEVER      0x0000E000  // Never Trigger
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO Pins)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM generator 0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM generator 1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM generator 2
+#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM generator 3
+#define ADC_EMUX_EM2_NEVER      0x00000E00  // Never Trigger
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO Pins)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM generator 0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM generator 1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM generator 2
+#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM generator 3
+#define ADC_EMUX_EM1_NEVER      0x000000E0  // Never Trigger
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO Pins)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM generator 0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM generator 1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM generator 2
+#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM generator 3
+#define ADC_EMUX_EM0_NEVER      0x0000000E  // Never Trigger
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M         0x30000000  // Generator 3 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS3_0         0x00000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS3_1         0x10000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS2_M         0x00300000  // Generator 2 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS2_0         0x00000000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS2_1         0x00100000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS1_M         0x00003000  // Generator 1 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS1_0         0x00000000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS1_1         0x00001000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS0_M         0x00000030  // Generator 0 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS0_0         0x00000000  // Use Generator 0 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS0_1         0x00000010  // Use Generator 0 (and its
+                                            // trigger) in PWM module 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_DITHER          0x00000040  // Dither Mode Enable
+#define ADC_CTL_VREF_M          0x00000003  // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL   0x00000000  // VDDA and GNDA are the voltage
+                                            // references
+#define ADC_CTL_VREF_EXT_3V     0x00000001  // The external VREFA+ and VREFA-
+                                            // inputs are the voltage
+                                            // references
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_S     24
+#define ADC_SSDC0_S5DCSEL_S     20
+#define ADC_SSDC0_S4DCSEL_S     16
+#define ADC_SSDC0_S3DCSEL_S     12
+#define ADC_SSDC0_S2DCSEL_S     8
+#define ADC_SSDC0_S1DCSEL_S     4
+#define ADC_SSDC0_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7       0x10000000  // 8th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX6       0x01000000  // 7th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX5       0x00100000  // 6th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX4       0x00010000  // 5th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH0 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH0_TSH7_M       0xF0000000  // 8th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH6_M       0x0F000000  // 7th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH5_M       0x00F00000  // 6th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH4_M       0x000F0000  // 5th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH7_S       28
+#define ADC_SSTSH0_TSH6_S       24
+#define ADC_SSTSH0_TSH5_S       20
+#define ADC_SSTSH0_TSH4_S       16
+#define ADC_SSTSH0_TSH3_S       12
+#define ADC_SSTSH0_TSH2_S       8
+#define ADC_SSTSH0_TSH1_S       4
+#define ADC_SSTSH0_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_S     8
+#define ADC_SSDC1_S1DCSEL_S     4
+#define ADC_SSDC1_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH1 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH1_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH3_S       12
+#define ADC_SSTSH1_TSH2_S       8
+#define ADC_SSTSH1_TSH1_S       4
+#define ADC_SSTSH1_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_S     8
+#define ADC_SSDC2_S1DCSEL_S     4
+#define ADC_SSDC2_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH2 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH2_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH3_S       12
+#define ADC_SSTSH2_TSH2_S       8
+#define ADC_SSTSH2_TSH1_S       4
+#define ADC_SSTSH2_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // Sample Differential Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH3 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH3_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH3_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP0_COMP1_S      16
+#define ADC_DCCMP0_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP1_COMP1_S      16
+#define ADC_DCCMP1_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP2_COMP1_S      16
+#define ADC_DCCMP2_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP3_COMP1_S      16
+#define ADC_DCCMP3_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP4_COMP1_S      16
+#define ADC_DCCMP4_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP5_COMP1_S      16
+#define ADC_DCCMP5_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP6_COMP1_S      16
+#define ADC_DCCMP6_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP7_COMP1_S      16
+#define ADC_DCCMP7_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_APSHT            0x01000000  // Application-Programmable
+                                            // Sample-and-Hold Time
+#define ADC_PP_TS               0x00800000  // Temperature Sensor
+#define ADC_PP_RSL_M            0x007C0000  // Resolution
+#define ADC_PP_TYPE_M           0x00030000  // ADC Architecture
+#define ADC_PP_TYPE_SAR         0x00000000  // SAR
+#define ADC_PP_DC_M             0x0000FC00  // Digital Comparator Count
+#define ADC_PP_CH_M             0x000003F0  // ADC Channel Count
+#define ADC_PP_MCR_M            0x0000000F  // Maximum Conversion Rate
+#define ADC_PP_MCR_FULL         0x00000007  // Full conversion rate (FCONV) as
+                                            // defined by TADC and NSH
+#define ADC_PP_MSR_M            0x0000000F  // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K         0x00000001  // 125 ksps
+#define ADC_PP_MSR_250K         0x00000003  // 250 ksps
+#define ADC_PP_MSR_500K         0x00000005  // 500 ksps
+#define ADC_PP_MSR_1M           0x00000007  // 1 Msps
+#define ADC_PP_RSL_S            18
+#define ADC_PP_DC_S             10
+#define ADC_PP_CH_S             4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M             0x0000000F  // ADC Sample Rate
+#define ADC_PC_SR_125K          0x00000001  // 125 ksps
+#define ADC_PC_SR_250K          0x00000003  // 250 ksps
+#define ADC_PC_SR_500K          0x00000005  // 500 ksps
+#define ADC_PC_SR_1M            0x00000007  // 1 Msps
+#define ADC_PC_MCR_M            0x0000000F  // Conversion Rate
+#define ADC_PC_MCR_1_8          0x00000001  // Eighth conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 112 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_1_4          0x00000003  // Quarter conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 48 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_1_2          0x00000005  // Half conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 16 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_FULL         0x00000007  // Full conversion rate (FCONV) as
+                                            // defined by TADC and NSH
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CLKDIV_M         0x000003F0  // PLL VCO Clock Divisor
+#define ADC_CC_CS_M             0x0000000F  // ADC Clock Source
+#define ADC_CC_CS_SYSPLL        0x00000000  // PLL VCO divided by CLKDIV
+#define ADC_CC_CS_PIOSC         0x00000001  // PIOSC
+#define ADC_CC_CS_MOSC          0x00000002  // MOSC
+#define ADC_CC_CLKDIV_S         4
+
+#endif // __HW_ADC_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_aes.h b/bsp/tm4c129x/libraries/inc/hw_aes.h
new file mode 100644
index 0000000000..25e9bd95cc
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_aes.h
@@ -0,0 +1,545 @@
+//*****************************************************************************
+//
+// hw_aes.h - Macros used when accessing the AES hardware.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_AES_H__
+#define __HW_AES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the AES register offsets.
+//
+//*****************************************************************************
+#define AES_O_KEY2_6            0x00000000  // AES Key 2_6
+#define AES_O_KEY2_7            0x00000004  // AES Key 2_7
+#define AES_O_KEY2_4            0x00000008  // AES Key 2_4
+#define AES_O_KEY2_5            0x0000000C  // AES Key 2_5
+#define AES_O_KEY2_2            0x00000010  // AES Key 2_2
+#define AES_O_KEY2_3            0x00000014  // AES Key 2_3
+#define AES_O_KEY2_0            0x00000018  // AES Key 2_0
+#define AES_O_KEY2_1            0x0000001C  // AES Key 2_1
+#define AES_O_KEY1_6            0x00000020  // AES Key 1_6
+#define AES_O_KEY1_7            0x00000024  // AES Key 1_7
+#define AES_O_KEY1_4            0x00000028  // AES Key 1_4
+#define AES_O_KEY1_5            0x0000002C  // AES Key 1_5
+#define AES_O_KEY1_2            0x00000030  // AES Key 1_2
+#define AES_O_KEY1_3            0x00000034  // AES Key 1_3
+#define AES_O_KEY1_0            0x00000038  // AES Key 1_0
+#define AES_O_KEY1_1            0x0000003C  // AES Key 1_1
+#define AES_O_IV_IN_0           0x00000040  // AES Initialization Vector Input
+                                            // 0
+#define AES_O_IV_IN_1           0x00000044  // AES Initialization Vector Input
+                                            // 1
+#define AES_O_IV_IN_2           0x00000048  // AES Initialization Vector Input
+                                            // 2
+#define AES_O_IV_IN_3           0x0000004C  // AES Initialization Vector Input
+                                            // 3
+#define AES_O_CTRL              0x00000050  // AES Control
+#define AES_O_C_LENGTH_0        0x00000054  // AES Crypto Data Length 0
+#define AES_O_C_LENGTH_1        0x00000058  // AES Crypto Data Length 1
+#define AES_O_AUTH_LENGTH       0x0000005C  // AES Authentication Data Length
+#define AES_O_DATA_IN_0         0x00000060  // AES Data RW Plaintext/Ciphertext
+                                            // 0
+#define AES_O_DATA_IN_1         0x00000064  // AES Data RW Plaintext/Ciphertext
+                                            // 1
+#define AES_O_DATA_IN_2         0x00000068  // AES Data RW Plaintext/Ciphertext
+                                            // 2
+#define AES_O_DATA_IN_3         0x0000006C  // AES Data RW Plaintext/Ciphertext
+                                            // 3
+#define AES_O_TAG_OUT_0         0x00000070  // AES Hash Tag Out 0
+#define AES_O_TAG_OUT_1         0x00000074  // AES Hash Tag Out 1
+#define AES_O_TAG_OUT_2         0x00000078  // AES Hash Tag Out 2
+#define AES_O_TAG_OUT_3         0x0000007C  // AES Hash Tag Out 3
+#define AES_O_REVISION          0x00000080  // AES IP Revision Identifier
+#define AES_O_SYSCONFIG         0x00000084  // AES System Configuration
+#define AES_O_SYSSTATUS         0x00000088  // AES System Status
+#define AES_O_IRQSTATUS         0x0000008C  // AES Interrupt Status
+#define AES_O_IRQENABLE         0x00000090  // AES Interrupt Enable
+#define AES_O_DIRTYBITS         0x00000094  // AES Dirty Bits
+#define AES_O_DMAIM             0xFFFFA020  // AES DMA Interrupt Mask
+#define AES_O_DMARIS            0xFFFFA024  // AES DMA Raw Interrupt Status
+#define AES_O_DMAMIS            0xFFFFA028  // AES DMA Masked Interrupt Status
+#define AES_O_DMAIC             0xFFFFA02C  // AES DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_6 register.
+//
+//*****************************************************************************
+#define AES_KEY2_6_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_6_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_7 register.
+//
+//*****************************************************************************
+#define AES_KEY2_7_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_7_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_4 register.
+//
+//*****************************************************************************
+#define AES_KEY2_4_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_4_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_5 register.
+//
+//*****************************************************************************
+#define AES_KEY2_5_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_5_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_2 register.
+//
+//*****************************************************************************
+#define AES_KEY2_2_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_2_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_3 register.
+//
+//*****************************************************************************
+#define AES_KEY2_3_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_3_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_0 register.
+//
+//*****************************************************************************
+#define AES_KEY2_0_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_0_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_1 register.
+//
+//*****************************************************************************
+#define AES_KEY2_1_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_1_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_6 register.
+//
+//*****************************************************************************
+#define AES_KEY1_6_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_6_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_7 register.
+//
+//*****************************************************************************
+#define AES_KEY1_7_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_7_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_4 register.
+//
+//*****************************************************************************
+#define AES_KEY1_4_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_4_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_5 register.
+//
+//*****************************************************************************
+#define AES_KEY1_5_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_5_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_2 register.
+//
+//*****************************************************************************
+#define AES_KEY1_2_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_2_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_3 register.
+//
+//*****************************************************************************
+#define AES_KEY1_3_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_3_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_0 register.
+//
+//*****************************************************************************
+#define AES_KEY1_0_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_0_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_1 register.
+//
+//*****************************************************************************
+#define AES_KEY1_1_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_1_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_0_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_1_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_2_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_3_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_CTRL register.
+//
+//*****************************************************************************
+#define AES_CTRL_CTXTRDY        0x80000000  // Context Data Registers Ready
+#define AES_CTRL_SVCTXTRDY      0x40000000  // AES TAG/IV Block(s) Ready
+#define AES_CTRL_SAVE_CONTEXT   0x20000000  // TAG or Result IV Save
+#define AES_CTRL_CCM_M_M        0x01C00000  // Counter with CBC-MAC (CCM)
+#define AES_CTRL_CCM_L_M        0x00380000  // L Value
+#define AES_CTRL_CCM_L_2        0x00080000  // width = 2
+#define AES_CTRL_CCM_L_4        0x00180000  // width = 4
+#define AES_CTRL_CCM_L_8        0x00380000  // width = 8
+#define AES_CTRL_CCM            0x00040000  // AES-CCM Mode Enable
+#define AES_CTRL_GCM_M          0x00030000  // AES-GCM Mode Enable
+#define AES_CTRL_GCM_NOP        0x00000000  // No operation
+#define AES_CTRL_GCM_HLY0ZERO   0x00010000  // GHASH with H loaded and
+                                            // Y0-encrypted forced to zero
+#define AES_CTRL_GCM_HLY0CALC   0x00020000  // GHASH with H loaded and
+                                            // Y0-encrypted calculated
+                                            // internally
+#define AES_CTRL_GCM_HY0CALC    0x00030000  // Autonomous GHASH (both H and
+                                            // Y0-encrypted calculated
+                                            // internally)
+#define AES_CTRL_CBCMAC         0x00008000  // AES-CBC MAC Enable
+#define AES_CTRL_F9             0x00004000  // AES f9 Mode Enable
+#define AES_CTRL_F8             0x00002000  // AES f8 Mode Enable
+#define AES_CTRL_XTS_M          0x00001800  // AES-XTS Operation Enabled
+#define AES_CTRL_XTS_NOP        0x00000000  // No operation
+#define AES_CTRL_XTS_TWEAKJL    0x00000800  // Previous/intermediate tweak
+                                            // value and j loaded (value is
+                                            // loaded via IV, j is loaded via
+                                            // the AAD length register)
+#define AES_CTRL_XTS_K2IJL      0x00001000  // Key2, n and j are loaded (n is
+                                            // loaded via IV, j is loaded via
+                                            // the AAD length register)
+#define AES_CTRL_XTS_K2ILJ0     0x00001800  // Key2 and n are loaded; j=0 (n is
+                                            // loaded via IV)
+#define AES_CTRL_CFB            0x00000400  // Full block AES cipher feedback
+                                            // mode (CFB128) Enable
+#define AES_CTRL_ICM            0x00000200  // AES Integer Counter Mode (ICM)
+                                            // Enable
+#define AES_CTRL_CTR_WIDTH_M    0x00000180  // AES-CTR Mode Counter Width
+#define AES_CTRL_CTR_WIDTH_32   0x00000000  // Counter is 32 bits
+#define AES_CTRL_CTR_WIDTH_64   0x00000080  // Counter is 64 bits
+#define AES_CTRL_CTR_WIDTH_96   0x00000100  // Counter is 96 bits
+#define AES_CTRL_CTR_WIDTH_128  0x00000180  // Counter is 128 bits
+#define AES_CTRL_CTR            0x00000040  // Counter Mode
+#define AES_CTRL_MODE           0x00000020  // ECB/CBC Mode
+#define AES_CTRL_KEY_SIZE_M     0x00000018  // Key Size
+#define AES_CTRL_KEY_SIZE_128   0x00000008  // Key is 128 bits
+#define AES_CTRL_KEY_SIZE_192   0x00000010  // Key is 192 bits
+#define AES_CTRL_KEY_SIZE_256   0x00000018  // Key is 256 bits
+#define AES_CTRL_DIRECTION      0x00000004  // Encryption/Decryption Selection
+#define AES_CTRL_INPUT_READY    0x00000002  // Input Ready Status
+#define AES_CTRL_OUTPUT_READY   0x00000001  // Output Ready Status
+#define AES_CTRL_CCM_M_S        22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_0
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF  // Data Length
+#define AES_C_LENGTH_0_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_1
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF  // Data Length
+#define AES_C_LENGTH_1_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_AUTH_LENGTH
+// register.
+//
+//*****************************************************************************
+#define AES_AUTH_LENGTH_AUTH_M  0xFFFFFFFF  // Authentication Data Length
+#define AES_AUTH_LENGTH_AUTH_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_0
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_0_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_0_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_1
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_1_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_2
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_2_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_3
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_3_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_0
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_0_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_0_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_1
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_1_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_1_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_2
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_2_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_2_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_3
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_3_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_3_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_REVISION register.
+//
+//*****************************************************************************
+#define AES_REVISION_M          0xFFFFFFFF  // Revision number
+#define AES_REVISION_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define AES_SYSCONFIG_K3        0x00001000  // K3 Select
+#define AES_SYSCONFIG_KEYENC    0x00000800  // Key Encoding
+#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT                             \
+                                0x00000200  // Map Context Out on Data Out
+                                            // Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN                                  \
+                                0x00000100  // DMA Request Context Out Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN                                   \
+                                0x00000080  // DMA Request Context In Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN                                     \
+                                0x00000040  // DMA Request Data Out Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN                                      \
+                                0x00000020  // DMA Request Data In Enable
+#define AES_SYSCONFIG_SOFTRESET 0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_SYSSTATUS_RESETDONE 0x00000001  // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_IRQSTATUS_CONTEXT_OUT                                             \
+                                0x00000008  // Context Output Interrupt Status
+#define AES_IRQSTATUS_DATA_OUT  0x00000004  // Data Out Interrupt Status
+#define AES_IRQSTATUS_DATA_IN   0x00000002  // Data In Interrupt Status
+#define AES_IRQSTATUS_CONTEXT_IN                                              \
+                                0x00000001  // Context In Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define AES_IRQENABLE_CONTEXT_OUT                                             \
+                                0x00000008  // Context Out Interrupt Enable
+#define AES_IRQENABLE_DATA_OUT  0x00000004  // Data Out Interrupt Enable
+#define AES_IRQENABLE_DATA_IN   0x00000002  // Data In Interrupt Enable
+#define AES_IRQENABLE_CONTEXT_IN                                              \
+                                0x00000001  // Context In Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define AES_DIRTYBITS_S_DIRTY   0x00000002  // AES Dirty Bit
+#define AES_DIRTYBITS_S_ACCESS  0x00000001  // AES Access Bit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIM register.
+//
+//*****************************************************************************
+#define AES_DMAIM_DOUT          0x00000008  // Data Out DMA Done Interrupt Mask
+#define AES_DMAIM_DIN           0x00000004  // Data In DMA Done Interrupt Mask
+#define AES_DMAIM_COUT          0x00000002  // Context Out DMA Done Interrupt
+                                            // Mask
+#define AES_DMAIM_CIN           0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMARIS register.
+//
+//*****************************************************************************
+#define AES_DMARIS_DOUT         0x00000008  // Data Out DMA Done Raw Interrupt
+                                            // Status
+#define AES_DMARIS_DIN          0x00000004  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define AES_DMARIS_COUT         0x00000002  // Context Out DMA Done Raw
+                                            // Interrupt Status
+#define AES_DMARIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define AES_DMAMIS_DOUT         0x00000008  // Data Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_DIN          0x00000004  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_COUT         0x00000002  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIC register.
+//
+//*****************************************************************************
+#define AES_DMAIC_DOUT          0x00000008  // Data Out DMA Done Interrupt
+                                            // Clear
+#define AES_DMAIC_DIN           0x00000004  // Data In DMA Done Interrupt Clear
+#define AES_DMAIC_COUT          0x00000002  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAIC_CIN           0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+#endif // __HW_AES_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_can.h b/bsp/tm4c129x/libraries/inc/hw_can.h
new file mode 100644
index 0000000000..604024a39d
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_can.h
@@ -0,0 +1,462 @@
+//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
+//
+// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL               0x00000000  // CAN Control
+#define CAN_O_STS               0x00000004  // CAN Status
+#define CAN_O_ERR               0x00000008  // CAN Error Counter
+#define CAN_O_BIT               0x0000000C  // CAN Bit Timing
+#define CAN_O_INT               0x00000010  // CAN Interrupt
+#define CAN_O_TST               0x00000014  // CAN Test
+#define CAN_O_BRPE              0x00000018  // CAN Baud Rate Prescaler
+                                            // Extension
+#define CAN_O_IF1CRQ            0x00000020  // CAN IF1 Command Request
+#define CAN_O_IF1CMSK           0x00000024  // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1           0x00000028  // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2           0x0000002C  // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1           0x00000030  // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2           0x00000034  // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL           0x00000038  // CAN IF1 Message Control
+#define CAN_O_IF1DA1            0x0000003C  // CAN IF1 Data A1
+#define CAN_O_IF1DA2            0x00000040  // CAN IF1 Data A2
+#define CAN_O_IF1DB1            0x00000044  // CAN IF1 Data B1
+#define CAN_O_IF1DB2            0x00000048  // CAN IF1 Data B2
+#define CAN_O_IF2CRQ            0x00000080  // CAN IF2 Command Request
+#define CAN_O_IF2CMSK           0x00000084  // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1           0x00000088  // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2           0x0000008C  // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1           0x00000090  // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2           0x00000094  // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL           0x00000098  // CAN IF2 Message Control
+#define CAN_O_IF2DA1            0x0000009C  // CAN IF2 Data A1
+#define CAN_O_IF2DA2            0x000000A0  // CAN IF2 Data A2
+#define CAN_O_IF2DB1            0x000000A4  // CAN IF2 Data B1
+#define CAN_O_IF2DB2            0x000000A8  // CAN IF2 Data B2
+#define CAN_O_TXRQ1             0x00000100  // CAN Transmission Request 1
+#define CAN_O_TXRQ2             0x00000104  // CAN Transmission Request 2
+#define CAN_O_NWDA1             0x00000120  // CAN New Data 1
+#define CAN_O_NWDA2             0x00000124  // CAN New Data 2
+#define CAN_O_MSG1INT           0x00000140  // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT           0x00000144  // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL           0x00000160  // CAN Message 1 Valid
+#define CAN_O_MSG2VAL           0x00000164  // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF1CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF2CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+#endif // __HW_CAN_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_ccm.h b/bsp/tm4c129x/libraries/inc/hw_ccm.h
new file mode 100644
index 0000000000..1d134572ca
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_ccm.h
@@ -0,0 +1,115 @@
+//*****************************************************************************
+//
+// hw_ccm.h - Macros used when accessing the CCM hardware.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CCM_H__
+#define __HW_CCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EC register offsets.
+//
+//*****************************************************************************
+#define CCM_O_CRCCTRL           0x00000400  // CRC Control
+#define CCM_O_CRCSEED           0x00000410  // CRC SEED/Context
+#define CCM_O_CRCDIN            0x00000414  // CRC Data Input
+#define CCM_O_CRCRSLTPP         0x00000418  // CRC Post Processing Result
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
+//
+//*****************************************************************************
+#define CCM_CRCCTRL_INIT_M      0x00006000  // CRC Initialization
+#define CCM_CRCCTRL_INIT_SEED   0x00000000  // Use the CRCSEED register context
+                                            // as the starting value
+#define CCM_CRCCTRL_INIT_0      0x00004000  // Initialize to all '0s'
+#define CCM_CRCCTRL_INIT_1      0x00006000  // Initialize to all '1s'
+#define CCM_CRCCTRL_SIZE        0x00001000  // Input Data Size
+#define CCM_CRCCTRL_RESINV      0x00000200  // Result Inverse Enable
+#define CCM_CRCCTRL_OBR         0x00000100  // Output Reverse Enable
+#define CCM_CRCCTRL_BR          0x00000080  // Bit reverse enable
+#define CCM_CRCCTRL_ENDIAN_M    0x00000030  // Endian Control
+#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000  // Configuration unchanged. (B3,
+                                            // B2, B1, B0)
+#define CCM_CRCCTRL_ENDIAN_SHW  0x00000010  // Bytes are swapped in half-words
+                                            // but half-words are not swapped
+                                            // (B2, B3, B0, B1)
+#define CCM_CRCCTRL_ENDIAN_SHWNB                                              \
+                                0x00000020  // Half-words are swapped but bytes
+                                            // are not swapped in half-word.
+                                            // (B1, B0, B3, B2)
+#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030  // Bytes are swapped in half-words
+                                            // and half-words are swapped. (B0,
+                                            // B1, B2, B3)
+#define CCM_CRCCTRL_TYPE_M      0x0000000F  // Operation Type
+#define CCM_CRCCTRL_TYPE_P8055  0x00000000  // Polynomial 0x8005
+#define CCM_CRCCTRL_TYPE_P1021  0x00000001  // Polynomial 0x1021
+#define CCM_CRCCTRL_TYPE_P4C11DB7                                             \
+                                0x00000002  // Polynomial 0x4C11DB7
+#define CCM_CRCCTRL_TYPE_P1EDC6F41                                            \
+                                0x00000003  // Polynomial 0x1EDC6F41
+#define CCM_CRCCTRL_TYPE_TCPCHKSUM                                            \
+                                0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCSEED register.
+//
+//*****************************************************************************
+#define CCM_CRCSEED_SEED_M      0xFFFFFFFF  // SEED/Context Value
+#define CCM_CRCSEED_SEED_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCDIN register.
+//
+//*****************************************************************************
+#define CCM_CRCDIN_DATAIN_M     0xFFFFFFFF  // Data Input
+#define CCM_CRCDIN_DATAIN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
+// register.
+//
+//*****************************************************************************
+#define CCM_CRCRSLTPP_RSLTPP_M  0xFFFFFFFF  // Post Processing Result
+#define CCM_CRCRSLTPP_RSLTPP_S  0
+
+#endif // __HW_CCM_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_comp.h b/bsp/tm4c129x/libraries/inc/hw_comp.h
new file mode 100644
index 0000000000..1d1a2a8731
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_comp.h
@@ -0,0 +1,211 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS            0x00000000  // Analog Comparator Masked
+                                            // Interrupt Status
+#define COMP_O_ACRIS            0x00000004  // Analog Comparator Raw Interrupt
+                                            // Status
+#define COMP_O_ACINTEN          0x00000008  // Analog Comparator Interrupt
+                                            // Enable
+#define COMP_O_ACREFCTL         0x00000010  // Analog Comparator Reference
+                                            // Voltage Control
+#define COMP_O_ACSTAT0          0x00000020  // Analog Comparator Status 0
+#define COMP_O_ACCTL0           0x00000024  // Analog Comparator Control 0
+#define COMP_O_ACSTAT1          0x00000040  // Analog Comparator Status 1
+#define COMP_O_ACCTL1           0x00000044  // Analog Comparator Control 1
+#define COMP_O_ACSTAT2          0x00000060  // Analog Comparator Status 2
+#define COMP_O_ACCTL2           0x00000064  // Analog Comparator Control 2
+#define COMP_O_PP               0x00000FC0  // Analog Comparator Peripheral
+                                            // Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O             0x00040000  // Comparator Output 2 Present
+#define COMP_PP_C1O             0x00020000  // Comparator Output 1 Present
+#define COMP_PP_C0O             0x00010000  // Comparator Output 0 Present
+#define COMP_PP_CMP2            0x00000004  // Comparator 2 Present
+#define COMP_PP_CMP1            0x00000002  // Comparator 1 Present
+#define COMP_PP_CMP0            0x00000001  // Comparator 0 Present
+
+#endif // __HW_COMP_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_des.h b/bsp/tm4c129x/libraries/inc/hw_des.h
new file mode 100644
index 0000000000..f958d8f279
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_des.h
@@ -0,0 +1,310 @@
+//*****************************************************************************
+//
+// hw_des.h - Macros used when accessing the DES hardware.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_DES_H__
+#define __HW_DES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the DES register offsets.
+//
+//*****************************************************************************
+#define DES_O_KEY3_L            0x00000000  // DES Key 3 LSW for 192-Bit Key
+#define DES_O_KEY3_H            0x00000004  // DES Key 3 MSW for 192-Bit Key
+#define DES_O_KEY2_L            0x00000008  // DES Key 2 LSW for 128-Bit Key
+#define DES_O_KEY2_H            0x0000000C  // DES Key 2 MSW for 128-Bit Key
+#define DES_O_KEY1_L            0x00000010  // DES Key 1 LSW for 64-Bit Key
+#define DES_O_KEY1_H            0x00000014  // DES Key 1 MSW for 64-Bit Key
+#define DES_O_IV_L              0x00000018  // DES Initialization Vector
+#define DES_O_IV_H              0x0000001C  // DES Initialization Vector
+#define DES_O_CTRL              0x00000020  // DES Control
+#define DES_O_LENGTH            0x00000024  // DES Cryptographic Data Length
+#define DES_O_DATA_L            0x00000028  // DES LSW Data RW
+#define DES_O_DATA_H            0x0000002C  // DES MSW Data RW
+#define DES_O_REVISION          0x00000030  // DES Revision Number
+#define DES_O_SYSCONFIG         0x00000034  // DES System Configuration
+#define DES_O_SYSSTATUS         0x00000038  // DES System Status
+#define DES_O_IRQSTATUS         0x0000003C  // DES Interrupt Status
+#define DES_O_IRQENABLE         0x00000040  // DES Interrupt Enable
+#define DES_O_DIRTYBITS         0x00000044  // DES Dirty Bits
+#define DES_O_DMAIM             0xFFFF8030  // DES DMA Interrupt Mask
+#define DES_O_DMARIS            0xFFFF8034  // DES DMA Raw Interrupt Status
+#define DES_O_DMAMIS            0xFFFF8038  // DES DMA Masked Interrupt Status
+#define DES_O_DMAIC             0xFFFF803C  // DES DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_L register.
+//
+//*****************************************************************************
+#define DES_KEY3_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY3_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_H register.
+//
+//*****************************************************************************
+#define DES_KEY3_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY3_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_L register.
+//
+//*****************************************************************************
+#define DES_KEY2_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY2_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_H register.
+//
+//*****************************************************************************
+#define DES_KEY2_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY2_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_L register.
+//
+//*****************************************************************************
+#define DES_KEY1_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY1_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_H register.
+//
+//*****************************************************************************
+#define DES_KEY1_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY1_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_L register.
+//
+//*****************************************************************************
+#define DES_IV_L_M              0xFFFFFFFF  // Initialization vector for CBC,
+                                            // CFB modes (LSW)
+#define DES_IV_L_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_H register.
+//
+//*****************************************************************************
+#define DES_IV_H_M              0xFFFFFFFF  // Initialization vector for CBC,
+                                            // CFB modes (MSW)
+#define DES_IV_H_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_CTRL register.
+//
+//*****************************************************************************
+#define DES_CTRL_CONTEXT        0x80000000  // If 1, this read-only status bit
+                                            // indicates that the context data
+                                            // registers can be overwritten and
+                                            // the host is permitted to write
+                                            // the next context
+#define DES_CTRL_MODE_M         0x00000030  // Select CBC, ECB or CFB mode0x0:
+                                            // ECB mode0x1: CBC mode0x2: CFB
+                                            // mode0x3: reserved
+#define DES_CTRL_TDES           0x00000008  // Select DES or triple DES
+                                            // encryption/decryption
+#define DES_CTRL_DIRECTION      0x00000004  // Select encryption/decryption
+                                            // 0x0: decryption is selected0x1:
+                                            // Encryption is selected
+#define DES_CTRL_INPUT_READY    0x00000002  // When 1, ready to encrypt/decrypt
+                                            // data
+#define DES_CTRL_OUTPUT_READY   0x00000001  // When 1, Data decrypted/encrypted
+                                            // ready
+#define DES_CTRL_MODE_S         4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_LENGTH register.
+//
+//*****************************************************************************
+#define DES_LENGTH_M            0xFFFFFFFF  // Cryptographic data length in
+                                            // bytes for all modes
+#define DES_LENGTH_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_L register.
+//
+//*****************************************************************************
+#define DES_DATA_L_M            0xFFFFFFFF  // Data for encryption/decryption,
+                                            // LSW
+#define DES_DATA_L_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_H register.
+//
+//*****************************************************************************
+#define DES_DATA_H_M            0xFFFFFFFF  // Data for encryption/decryption,
+                                            // MSW
+#define DES_DATA_H_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_REVISION register.
+//
+//*****************************************************************************
+#define DES_REVISION_M          0xFFFFFFFF  // Revision number
+#define DES_REVISION_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN                                   \
+                                0x00000080  // DMA Request Context In Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN                                     \
+                                0x00000040  // DMA Request Data Out Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN                                      \
+                                0x00000020  // DMA Request Data In Enable
+#define DES_SYSCONFIG_SIDLE_M   0x0000000C  // Sidle mode
+#define DES_SYSCONFIG_SIDLE_FORCE                                             \
+                                0x00000000  // Force-idle mode
+#define DES_SYSCONFIG_SOFTRESET 0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_SYSSTATUS_RESETDONE 0x00000001  // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_IRQSTATUS_DATA_OUT  0x00000004  // This bit indicates data output
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+#define DES_IRQSTATUS_DATA_IN   0x00000002  // This bit indicates data input
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+#define DES_IRQSTATUS_CONTEX_IN 0x00000001  // This bit indicates context
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define DES_IRQENABLE_M_DATA_OUT                                              \
+                                0x00000004  // If this bit is set to 1 the data
+                                            // output interrupt is enabled
+#define DES_IRQENABLE_M_DATA_IN 0x00000002  // If this bit is set to 1 the data
+                                            // input interrupt is enabled
+#define DES_IRQENABLE_M_CONTEX_IN                                             \
+                                0x00000001  // If this bit is set to 1 the
+                                            // context interrupt is enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define DES_DIRTYBITS_S_DIRTY   0x00000002  // This bit is set to 1 by the
+                                            // module if any of the DES_*
+                                            // registers is written
+#define DES_DIRTYBITS_S_ACCESS  0x00000001  // This bit is set to 1 by the
+                                            // module if any of the DES_*
+                                            // registers is read
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIM register.
+//
+//*****************************************************************************
+#define DES_DMAIM_DOUT          0x00000004  // Data Out DMA Done Interrupt Mask
+#define DES_DMAIM_DIN           0x00000002  // Data In DMA Done Interrupt Mask
+#define DES_DMAIM_CIN           0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMARIS register.
+//
+//*****************************************************************************
+#define DES_DMARIS_DOUT         0x00000004  // Data Out DMA Done Raw Interrupt
+                                            // Status
+#define DES_DMARIS_DIN          0x00000002  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define DES_DMARIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define DES_DMAMIS_DOUT         0x00000004  // Data Out DMA Done Masked
+                                            // Interrupt Status
+#define DES_DMAMIS_DIN          0x00000002  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define DES_DMAMIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIC register.
+//
+//*****************************************************************************
+#define DES_DMAIC_DOUT          0x00000004  // Data Out DMA Done Interrupt
+                                            // Clear
+#define DES_DMAIC_DIN           0x00000002  // Data In DMA Done Interrupt Clear
+#define DES_DMAIC_CIN           0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+#endif // __HW_DES_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_eeprom.h b/bsp/tm4c129x/libraries/inc/hw_eeprom.h
new file mode 100644
index 0000000000..4aeae0ba98
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_eeprom.h
@@ -0,0 +1,251 @@
+//*****************************************************************************
+//
+// hw_eeprom.h - Macros used when accessing the EEPROM controller.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EEPROM_H__
+#define __HW_EEPROM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE           0x400AF000  // EEPROM Size Information
+#define EEPROM_EEBLOCK          0x400AF004  // EEPROM Current Block
+#define EEPROM_EEOFFSET         0x400AF008  // EEPROM Current Offset
+#define EEPROM_EERDWR           0x400AF010  // EEPROM Read-Write
+#define EEPROM_EERDWRINC        0x400AF014  // EEPROM Read-Write with Increment
+#define EEPROM_EEDONE           0x400AF018  // EEPROM Done Status
+#define EEPROM_EESUPP           0x400AF01C  // EEPROM Support Control and
+                                            // Status
+#define EEPROM_EEUNLOCK         0x400AF020  // EEPROM Unlock
+#define EEPROM_EEPROT           0x400AF030  // EEPROM Protection
+#define EEPROM_EEPASS0          0x400AF034  // EEPROM Password
+#define EEPROM_EEPASS1          0x400AF038  // EEPROM Password
+#define EEPROM_EEPASS2          0x400AF03C  // EEPROM Password
+#define EEPROM_EEINT            0x400AF040  // EEPROM Interrupt
+#define EEPROM_EEHIDE0          0x400AF050  // EEPROM Block Hide 0
+#define EEPROM_EEHIDE           0x400AF050  // EEPROM Block Hide
+#define EEPROM_EEHIDE1          0x400AF054  // EEPROM Block Hide 1
+#define EEPROM_EEHIDE2          0x400AF058  // EEPROM Block Hide 2
+#define EEPROM_EEDBGME          0x400AF080  // EEPROM Debug Mass Erase
+#define EEPROM_PP               0x400AFFC0  // EEPROM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF  // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_M  0x07FF0000  // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_S 0
+#define EEPROM_EESIZE_BLKCNT_S  16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M  0x0000FFFF  // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M                                              \
+                                0x0000000F  // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF  // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M                                              \
+                                0xFFFFFFFF  // EEPROM Read or Write Data with
+                                            // Increment
+#define EEPROM_EERDWRINC_VALUE_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WORKING   0x00000001  // EEPROM Working
+#define EEPROM_EEDONE_WKERASE   0x00000004  // Working on an Erase
+#define EEPROM_EEDONE_WKCOPY    0x00000008  // Working on a Copy
+#define EEPROM_EEDONE_NOPERM    0x00000010  // Write Without Permission
+#define EEPROM_EEDONE_WRBUSY    0x00000020  // Write Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_ERETRY    0x00000004  // Erase Must Be Retried
+#define EEPROM_EESUPP_PRETRY    0x00000008  // Programming Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M                                              \
+                                0xFFFFFFFF  // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_PROT_M    0x00000007  // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW                                              \
+                                0x00000000  // This setting is the default. If
+                                            // there is no password, the block
+                                            // is not protected and is readable
+                                            // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001  // If there is a password, the
+                                            // block is readable or writable
+                                            // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW                                              \
+                                0x00000002  // If there is no password, the
+                                            // block is readable, not writable
+#define EEPROM_EEPROT_ACC       0x00000008  // Access Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS0_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS1_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS2_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT        0x00000001  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE0_HN_M     0xFFFFFFFE  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M      0xFFFFFFFE  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE1_HN_M     0xFFFFFFFF  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE2_HN_M     0xFFFFFFFF  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_ME       0x00000001  // Mass Erase
+#define EEPROM_EEDBGME_KEY_M    0xFFFF0000  // Erase Key
+#define EEPROM_EEDBGME_KEY_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M        0x0000FFFF  // EEPROM Size
+#define EEPROM_PP_SIZE_64       0x00000000  // 64 bytes of EEPROM
+#define EEPROM_PP_SIZE_128      0x00000001  // 128 bytes of EEPROM
+#define EEPROM_PP_SIZE_256      0x00000003  // 256 bytes of EEPROM
+#define EEPROM_PP_SIZE_512      0x00000007  // 512 bytes of EEPROM
+#define EEPROM_PP_SIZE_1K       0x0000000F  // 1 KB of EEPROM
+#define EEPROM_PP_SIZE_2K       0x0000001F  // 2 KB of EEPROM
+#define EEPROM_PP_SIZE_3K       0x0000003F  // 3 KB of EEPROM
+#define EEPROM_PP_SIZE_4K       0x0000007F  // 4 KB of EEPROM
+#define EEPROM_PP_SIZE_5K       0x000000FF  // 5 KB of EEPROM
+#define EEPROM_PP_SIZE_6K       0x000001FF  // 6 KB of EEPROM
+#define EEPROM_PP_SIZE_S        0
+
+#endif // __HW_EEPROM_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_emac.h b/bsp/tm4c129x/libraries/inc/hw_emac.h
new file mode 100644
index 0000000000..ec5e7b309a
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_emac.h
@@ -0,0 +1,1845 @@
+//*****************************************************************************
+//
+// hw_emac.h - Macros used when accessing the EMAC hardware.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EMAC_H__
+#define __HW_EMAC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EMAC register offsets.
+//
+//*****************************************************************************
+#define EMAC_O_CFG              0x00000000  // Ethernet MAC Configuration
+#define EMAC_O_FRAMEFLTR        0x00000004  // Ethernet MAC Frame Filter
+#define EMAC_O_HASHTBLH         0x00000008  // Ethernet MAC Hash Table High
+#define EMAC_O_HASHTBLL         0x0000000C  // Ethernet MAC Hash Table Low
+#define EMAC_O_MIIADDR          0x00000010  // Ethernet MAC MII Address
+#define EMAC_O_MIIDATA          0x00000014  // Ethernet MAC MII Data Register
+#define EMAC_O_FLOWCTL          0x00000018  // Ethernet MAC Flow Control
+#define EMAC_O_VLANTG           0x0000001C  // Ethernet MAC VLAN Tag
+#define EMAC_O_STATUS           0x00000024  // Ethernet MAC Status
+#define EMAC_O_RWUFF            0x00000028  // Ethernet MAC Remote Wake-Up
+                                            // Frame Filter
+#define EMAC_O_PMTCTLSTAT       0x0000002C  // Ethernet MAC PMT Control and
+                                            // Status Register
+#define EMAC_O_RIS              0x00000038  // Ethernet MAC Raw Interrupt
+                                            // Status
+#define EMAC_O_IM               0x0000003C  // Ethernet MAC Interrupt Mask
+#define EMAC_O_ADDR0H           0x00000040  // Ethernet MAC Address 0 High
+#define EMAC_O_ADDR0L           0x00000044  // Ethernet MAC Address 0 Low
+                                            // Register
+#define EMAC_O_ADDR1H           0x00000048  // Ethernet MAC Address 1 High
+#define EMAC_O_ADDR1L           0x0000004C  // Ethernet MAC Address 1 Low
+#define EMAC_O_ADDR2H           0x00000050  // Ethernet MAC Address 2 High
+#define EMAC_O_ADDR2L           0x00000054  // Ethernet MAC Address 2 Low
+#define EMAC_O_ADDR3H           0x00000058  // Ethernet MAC Address 3 High
+#define EMAC_O_ADDR3L           0x0000005C  // Ethernet MAC Address 3 Low
+#define EMAC_O_WDOGTO           0x000000DC  // Ethernet MAC Watchdog Timeout
+#define EMAC_O_MMCCTRL          0x00000100  // Ethernet MAC MMC Control
+#define EMAC_O_MMCRXRIS         0x00000104  // Ethernet MAC MMC Receive Raw
+                                            // Interrupt Status
+#define EMAC_O_MMCTXRIS         0x00000108  // Ethernet MAC MMC Transmit Raw
+                                            // Interrupt Status
+#define EMAC_O_MMCRXIM          0x0000010C  // Ethernet MAC MMC Receive
+                                            // Interrupt Mask
+#define EMAC_O_MMCTXIM          0x00000110  // Ethernet MAC MMC Transmit
+                                            // Interrupt Mask
+#define EMAC_O_TXCNTGB          0x00000118  // Ethernet MAC Transmit Frame
+                                            // Count for Good and Bad Frames
+#define EMAC_O_TXCNTSCOL        0x0000014C  // Ethernet MAC Transmit Frame
+                                            // Count for Frames Transmitted
+                                            // after Single Collision
+#define EMAC_O_TXCNTMCOL        0x00000150  // Ethernet MAC Transmit Frame
+                                            // Count for Frames Transmitted
+                                            // after Multiple Collisions
+#define EMAC_O_TXOCTCNTG        0x00000164  // Ethernet MAC Transmit Octet
+                                            // Count Good
+#define EMAC_O_RXCNTGB          0x00000180  // Ethernet MAC Receive Frame Count
+                                            // for Good and Bad Frames
+#define EMAC_O_RXCNTCRCERR      0x00000194  // Ethernet MAC Receive Frame Count
+                                            // for CRC Error Frames
+#define EMAC_O_RXCNTALGNERR     0x00000198  // Ethernet MAC Receive Frame Count
+                                            // for Alignment Error Frames
+#define EMAC_O_RXCNTGUNI        0x000001C4  // Ethernet MAC Receive Frame Count
+                                            // for Good Unicast Frames
+#define EMAC_O_VLNINCREP        0x00000584  // Ethernet MAC VLAN Tag Inclusion
+                                            // or Replacement
+#define EMAC_O_VLANHASH         0x00000588  // Ethernet MAC VLAN Hash Table
+#define EMAC_O_TIMSTCTRL        0x00000700  // Ethernet MAC Timestamp Control
+#define EMAC_O_SUBSECINC        0x00000704  // Ethernet MAC Sub-Second
+                                            // Increment
+#define EMAC_O_TIMSEC           0x00000708  // Ethernet MAC System Time -
+                                            // Seconds
+#define EMAC_O_TIMNANO          0x0000070C  // Ethernet MAC System Time -
+                                            // Nanoseconds
+#define EMAC_O_TIMSECU          0x00000710  // Ethernet MAC System Time -
+                                            // Seconds Update
+#define EMAC_O_TIMNANOU         0x00000714  // Ethernet MAC System Time -
+                                            // Nanoseconds Update
+#define EMAC_O_TIMADD           0x00000718  // Ethernet MAC Timestamp Addend
+#define EMAC_O_TARGSEC          0x0000071C  // Ethernet MAC Target Time Seconds
+#define EMAC_O_TARGNANO         0x00000720  // Ethernet MAC Target Time
+                                            // Nanoseconds
+#define EMAC_O_HWORDSEC         0x00000724  // Ethernet MAC System Time-Higher
+                                            // Word Seconds
+#define EMAC_O_TIMSTAT          0x00000728  // Ethernet MAC Timestamp Status
+#define EMAC_O_PPSCTRL          0x0000072C  // Ethernet MAC PPS Control
+#define EMAC_O_PPS0INTVL        0x00000760  // Ethernet MAC PPS0 Interval
+#define EMAC_O_PPS0WIDTH        0x00000764  // Ethernet MAC PPS0 Width
+#define EMAC_O_DMABUSMOD        0x00000C00  // Ethernet MAC DMA Bus Mode
+#define EMAC_O_TXPOLLD          0x00000C04  // Ethernet MAC Transmit Poll
+                                            // Demand
+#define EMAC_O_RXPOLLD          0x00000C08  // Ethernet MAC Receive Poll Demand
+#define EMAC_O_RXDLADDR         0x00000C0C  // Ethernet MAC Receive Descriptor
+                                            // List Address
+#define EMAC_O_TXDLADDR         0x00000C10  // Ethernet MAC Transmit Descriptor
+                                            // List Address
+#define EMAC_O_DMARIS           0x00000C14  // Ethernet MAC DMA Interrupt
+                                            // Status
+#define EMAC_O_DMAOPMODE        0x00000C18  // Ethernet MAC DMA Operation Mode
+#define EMAC_O_DMAIM            0x00000C1C  // Ethernet MAC DMA Interrupt Mask
+                                            // Register
+#define EMAC_O_MFBOC            0x00000C20  // Ethernet MAC Missed Frame and
+                                            // Buffer Overflow Counter
+#define EMAC_O_RXINTWDT         0x00000C24  // Ethernet MAC Receive Interrupt
+                                            // Watchdog Timer
+#define EMAC_O_HOSTXDESC        0x00000C48  // Ethernet MAC Current Host
+                                            // Transmit Descriptor
+#define EMAC_O_HOSRXDESC        0x00000C4C  // Ethernet MAC Current Host
+                                            // Receive Descriptor
+#define EMAC_O_HOSTXBA          0x00000C50  // Ethernet MAC Current Host
+                                            // Transmit Buffer Address
+#define EMAC_O_HOSRXBA          0x00000C54  // Ethernet MAC Current Host
+                                            // Receive Buffer Address
+#define EMAC_O_PP               0x00000FC0  // Ethernet MAC Peripheral Property
+                                            // Register
+#define EMAC_O_PC               0x00000FC4  // Ethernet MAC Peripheral
+                                            // Configuration Register
+#define EMAC_O_CC               0x00000FC8  // Ethernet MAC Clock Configuration
+                                            // Register
+#define EMAC_O_EPHYRIS          0x00000FD0  // Ethernet PHY Raw Interrupt
+                                            // Status
+#define EMAC_O_EPHYIM           0x00000FD4  // Ethernet PHY Interrupt Mask
+#define EMAC_O_EPHYMISC         0x00000FD8  // Ethernet PHY Masked Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_CFG register.
+//
+//*****************************************************************************
+#define EMAC_CFG_TWOKPEN        0x08000000  // IEEE 802
+#define EMAC_CFG_CST            0x02000000  // CRC Stripping for Type Frames
+#define EMAC_CFG_WDDIS          0x00800000  // Watchdog Disable
+#define EMAC_CFG_JD             0x00400000  // Jabber Disable
+#define EMAC_CFG_JFEN           0x00100000  // Jumbo Frame Enable
+#define EMAC_CFG_IFG_M          0x000E0000  // Inter-Frame Gap (IFG)
+#define EMAC_CFG_IFG_96         0x00000000  // 96 bit times
+#define EMAC_CFG_IFG_88         0x00020000  // 88 bit times
+#define EMAC_CFG_IFG_80         0x00040000  // 80 bit times
+#define EMAC_CFG_IFG_72         0x00060000  // 72 bit times
+#define EMAC_CFG_IFG_64         0x00080000  // 64 bit times
+#define EMAC_CFG_IFG_56         0x000A0000  // 56 bit times
+#define EMAC_CFG_IFG_48         0x000C0000  // 48 bit times
+#define EMAC_CFG_IFG_40         0x000E0000  // 40 bit times
+#define EMAC_CFG_DISCRS         0x00010000  // Disable Carrier Sense During
+                                            // Transmission
+#define EMAC_CFG_PS             0x00008000  // Port Select
+#define EMAC_CFG_FES            0x00004000  // Speed
+#define EMAC_CFG_DRO            0x00002000  // Disable Receive Own
+#define EMAC_CFG_LOOPBM         0x00001000  // Loopback Mode
+#define EMAC_CFG_DUPM           0x00000800  // Duplex Mode
+#define EMAC_CFG_IPC            0x00000400  // Checksum Offload
+#define EMAC_CFG_DR             0x00000200  // Disable Retry
+#define EMAC_CFG_ACS            0x00000080  // Automatic Pad or CRC Stripping
+#define EMAC_CFG_BL_M           0x00000060  // Back-Off Limit
+#define EMAC_CFG_BL_1024        0x00000000  // k = min (n,10)
+#define EMAC_CFG_BL_256         0x00000020  // k = min (n,8)
+#define EMAC_CFG_BL_8           0x00000040  // k = min (n,4)
+#define EMAC_CFG_BL_2           0x00000060  // k = min (n,1)
+#define EMAC_CFG_DC             0x00000010  // Deferral Check
+#define EMAC_CFG_TE             0x00000008  // Transmitter Enable
+#define EMAC_CFG_RE             0x00000004  // Receiver Enable
+#define EMAC_CFG_PRELEN_M       0x00000003  // Preamble Length for Transmit
+                                            // Frames
+#define EMAC_CFG_PRELEN_7       0x00000000  // 7 bytes of preamble
+#define EMAC_CFG_PRELEN_5       0x00000001  // 5 bytes of preamble
+#define EMAC_CFG_PRELEN_3       0x00000002  // 3 bytes of preamble
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR
+// register.
+//
+//*****************************************************************************
+#define EMAC_FRAMEFLTR_RA       0x80000000  // Receive All
+#define EMAC_FRAMEFLTR_VTFE     0x00010000  // VLAN Tag Filter Enable
+#define EMAC_FRAMEFLTR_HPF      0x00000400  // Hash or Perfect Filter
+#define EMAC_FRAMEFLTR_SAF      0x00000200  // Source Address Filter Enable
+#define EMAC_FRAMEFLTR_SAIF     0x00000100  // Source Address (SA) Inverse
+                                            // Filtering
+#define EMAC_FRAMEFLTR_PCF_M    0x000000C0  // Pass Control Frames
+#define EMAC_FRAMEFLTR_PCF_ALL  0x00000000  // The MAC filters all control
+                                            // frames from reaching application
+#define EMAC_FRAMEFLTR_PCF_PAUSE                                              \
+                                0x00000040  // MAC forwards all control frames
+                                            // except PAUSE control frames to
+                                            // application even if they fail
+                                            // the address filter
+#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080  // MAC forwards all control frames
+                                            // to application even if they fail
+                                            // the address Filter
+#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0  // MAC forwards control frames that
+                                            // pass the address Filter
+#define EMAC_FRAMEFLTR_DBF      0x00000020  // Disable Broadcast Frames
+#define EMAC_FRAMEFLTR_PM       0x00000010  // Pass All Multicast
+#define EMAC_FRAMEFLTR_DAIF     0x00000008  // Destination Address (DA) Inverse
+                                            // Filtering
+#define EMAC_FRAMEFLTR_HMC      0x00000004  // Hash Multicast
+#define EMAC_FRAMEFLTR_HUC      0x00000002  // Hash Unicast
+#define EMAC_FRAMEFLTR_PR       0x00000001  // Promiscuous Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HASHTBLH
+// register.
+//
+//*****************************************************************************
+#define EMAC_HASHTBLH_HTH_M     0xFFFFFFFF  // Hash Table High
+#define EMAC_HASHTBLH_HTH_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HASHTBLL
+// register.
+//
+//*****************************************************************************
+#define EMAC_HASHTBLL_HTL_M     0xFFFFFFFF  // Hash Table Low
+#define EMAC_HASHTBLL_HTL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MIIADDR register.
+//
+//*****************************************************************************
+#define EMAC_MIIADDR_PLA_M      0x0000F800  // Physical Layer Address
+#define EMAC_MIIADDR_MII_M      0x000007C0  // MII Register
+#define EMAC_MIIADDR_CR_M       0x0000003C  // Clock Reference Frequency
+                                            // Selection
+#define EMAC_MIIADDR_CR_60_100  0x00000000  // The frequency of the System
+                                            // Clock is 60 to 100 MHz providing
+                                            // a MDIO clock of SYSCLK/42
+#define EMAC_MIIADDR_CR_100_150 0x00000004  // The frequency of the System
+                                            // Clock is 100 to 150 MHz
+                                            // providing a MDIO clock of
+                                            // SYSCLK/62
+#define EMAC_MIIADDR_CR_20_35   0x00000008  // The frequency of the System
+                                            // Clock is 20-35 MHz providing a
+                                            // MDIO clock of System Clock/16
+#define EMAC_MIIADDR_CR_35_60   0x0000000C  // The frequency of the System
+                                            // Clock is 35 to 60 MHz providing
+                                            // a MDIO clock of System Clock/26
+#define EMAC_MIIADDR_MIIW       0x00000002  // MII Write
+#define EMAC_MIIADDR_MIIB       0x00000001  // MII Busy
+#define EMAC_MIIADDR_PLA_S      11
+#define EMAC_MIIADDR_MII_S      6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MIIDATA register.
+//
+//*****************************************************************************
+#define EMAC_MIIDATA_DATA_M     0x0000FFFF  // MII Data
+#define EMAC_MIIDATA_DATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_FLOWCTL register.
+//
+//*****************************************************************************
+#define EMAC_FLOWCTL_PT_M       0xFFFF0000  // Pause Time
+#define EMAC_FLOWCTL_DZQP       0x00000080  // Disable Zero-Quanta Pause
+#define EMAC_FLOWCTL_PLT_M      0x00000030  // Pause Low Threshold
+#define EMAC_FLOWCTL_PLT_4      0x00000000  // The threshold is Pause time
+                                            // minus 4 slot times (PT - 4 slot
+                                            // times)
+#define EMAC_FLOWCTL_PLT_28     0x00000010  // The threshold is Pause time
+                                            // minus 28 slot times (PT - 28
+                                            // slot times)
+#define EMAC_FLOWCTL_PLT_144    0x00000020  // The threshold is Pause time
+                                            // minus 144 slot times (PT - 144
+                                            // slot times)
+#define EMAC_FLOWCTL_PLT_156    0x00000030  // The threshold is Pause time
+                                            // minus 256 slot times (PT - 256
+                                            // slot times)
+#define EMAC_FLOWCTL_UP         0x00000008  // Unicast Pause Frame Detect
+#define EMAC_FLOWCTL_RFE        0x00000004  // Receive Flow Control Enable
+#define EMAC_FLOWCTL_TFE        0x00000002  // Transmit Flow Control Enable
+#define EMAC_FLOWCTL_FCBBPA     0x00000001  // Flow Control Busy or
+                                            // Back-pressure Activate
+#define EMAC_FLOWCTL_PT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLANTG register.
+//
+//*****************************************************************************
+#define EMAC_VLANTG_VTHM        0x00080000  // VLAN Tag Hash Table Match Enable
+#define EMAC_VLANTG_ESVL        0x00040000  // Enable S-VLAN
+#define EMAC_VLANTG_VTIM        0x00020000  // VLAN Tag Inverse Match Enable
+#define EMAC_VLANTG_ETV         0x00010000  // Enable 12-Bit VLAN Tag
+                                            // Comparison
+#define EMAC_VLANTG_VL_M        0x0000FFFF  // VLAN Tag Identifier for Receive
+                                            // Frames
+#define EMAC_VLANTG_VL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_STATUS register.
+//
+//*****************************************************************************
+#define EMAC_STATUS_TXFF        0x02000000  // TX/RX Controller TX FIFO Full
+                                            // Status
+#define EMAC_STATUS_TXFE        0x01000000  // TX/RX Controller TX FIFO Not
+                                            // Empty Status
+#define EMAC_STATUS_TWC         0x00400000  // TX/RX Controller TX FIFO Write
+                                            // Controller Active Status
+#define EMAC_STATUS_TRC_M       0x00300000  // TX/RX Controller's TX FIFO Read
+                                            // Controller Status
+#define EMAC_STATUS_TRC_IDLE    0x00000000  // IDLE state
+#define EMAC_STATUS_TRC_READ    0x00100000  // READ state (transferring data to
+                                            // MAC transmitter)
+#define EMAC_STATUS_TRC_WAIT    0x00200000  // Waiting for TX Status from MAC
+                                            // transmitter
+#define EMAC_STATUS_TRC_WRFLUSH 0x00300000  // Writing the received TX Status
+                                            // or flushing the TX FIFO
+#define EMAC_STATUS_TXPAUSED    0x00080000  // MAC Transmitter PAUSE
+#define EMAC_STATUS_TFC_M       0x00060000  // MAC Transmit Frame Controller
+                                            // Status
+#define EMAC_STATUS_TFC_IDLE    0x00000000  // IDLE state
+#define EMAC_STATUS_TFC_STATUS  0x00020000  // Waiting for status of previous
+                                            // frame or IFG or backoff period
+                                            // to be over
+#define EMAC_STATUS_TFC_PAUSE   0x00040000  // Generating and transmitting a
+                                            // PAUSE control frame (in the
+                                            // full-duplex mode)
+#define EMAC_STATUS_TFC_INPUT   0x00060000  // Transferring input frame for
+                                            // transmission
+#define EMAC_STATUS_TPE         0x00010000  // MAC MII Transmit Protocol Engine
+                                            // Status
+#define EMAC_STATUS_RXF_M       0x00000300  // TX/RX Controller RX FIFO
+                                            // Fill-level Status
+#define EMAC_STATUS_RXF_EMPTY   0x00000000  // RX FIFO Empty
+#define EMAC_STATUS_RXF_BELOW   0x00000100  // RX FIFO fill level is below the
+                                            // flow-control deactivate
+                                            // threshold
+#define EMAC_STATUS_RXF_ABOVE   0x00000200  // RX FIFO fill level is above the
+                                            // flow-control activate threshold
+#define EMAC_STATUS_RXF_FULL    0x00000300  // RX FIFO Full
+#define EMAC_STATUS_RRC_M       0x00000060  // TX/RX Controller Read Controller
+                                            // State
+#define EMAC_STATUS_RRC_IDLE    0x00000000  // IDLE state
+#define EMAC_STATUS_RRC_STATUS  0x00000020  // Reading frame data
+#define EMAC_STATUS_RRC_DATA    0x00000040  // Reading frame status (or
+                                            // timestamp)
+#define EMAC_STATUS_RRC_FLUSH   0x00000060  // Flushing the frame data and
+                                            // status
+#define EMAC_STATUS_RWC         0x00000010  // TX/RX Controller RX FIFO Write
+                                            // Controller Active Status
+#define EMAC_STATUS_RFCFC_M     0x00000006  // MAC Receive Frame Controller
+                                            // FIFO Status
+#define EMAC_STATUS_RPE         0x00000001  // MAC MII Receive Protocol Engine
+                                            // Status
+#define EMAC_STATUS_RFCFC_S     1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RWUFF register.
+//
+//*****************************************************************************
+#define EMAC_RWUFF_WAKEUPFIL_M  0xFFFFFFFF  // Remote Wake-Up Frame Filter
+#define EMAC_RWUFF_WAKEUPFIL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT
+// register.
+//
+//*****************************************************************************
+#define EMAC_PMTCTLSTAT_WUPFRRST                                              \
+                                0x80000000  // Wake-Up Frame Filter Register
+                                            // Pointer Reset
+#define EMAC_PMTCTLSTAT_RWKPTR_M                                              \
+                                0x07000000  // Remote Wake-Up FIFO Pointer
+#define EMAC_PMTCTLSTAT_GLBLUCAST                                             \
+                                0x00000200  // Global Unicast
+#define EMAC_PMTCTLSTAT_WUPRX   0x00000040  // Wake-Up Frame Received
+#define EMAC_PMTCTLSTAT_MGKPRX  0x00000020  // Magic Packet Received
+#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004  // Wake-Up Frame Enable
+#define EMAC_PMTCTLSTAT_MGKPKTEN                                              \
+                                0x00000002  // Magic Packet Enable
+#define EMAC_PMTCTLSTAT_PWRDWN  0x00000001  // Power Down
+#define EMAC_PMTCTLSTAT_RWKPTR_S                                              \
+                                24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RIS register.
+//
+//*****************************************************************************
+#define EMAC_RIS_TS             0x00000200  // Timestamp Interrupt Status
+#define EMAC_RIS_MMCTX          0x00000040  // MMC Transmit Interrupt Status
+#define EMAC_RIS_MMCRX          0x00000020  // MMC Receive Interrupt Status
+#define EMAC_RIS_MMC            0x00000010  // MMC Interrupt Status
+#define EMAC_RIS_PMT            0x00000008  // PMT Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_IM register.
+//
+//*****************************************************************************
+#define EMAC_IM_TSI             0x00000200  // Timestamp Interrupt Mask
+#define EMAC_IM_PMT             0x00000008  // PMT Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR0H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR0H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR0H_ADDRHI_M    0x0000FFFF  // MAC Address0 [47:32]
+#define EMAC_ADDR0H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR0L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR0L_ADDRLO_M    0xFFFFFFFF  // MAC Address0 [31:0]
+#define EMAC_ADDR0L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR1H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR1H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR1H_SA          0x40000000  // Source Address
+#define EMAC_ADDR1H_MBC_M       0x3F000000  // Mask Byte Control
+#define EMAC_ADDR1H_ADDRHI_M    0x0000FFFF  // MAC Address1 [47:32]
+#define EMAC_ADDR1H_MBC_S       24
+#define EMAC_ADDR1H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR1L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR1L_ADDRLO_M    0xFFFFFFFF  // MAC Address1 [31:0]
+#define EMAC_ADDR1L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR2H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR2H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR2H_SA          0x40000000  // Source Address
+#define EMAC_ADDR2H_MBC_M       0x3F000000  // Mask Byte Control
+#define EMAC_ADDR2H_ADDRHI_M    0x0000FFFF  // MAC Address2 [47:32]
+#define EMAC_ADDR2H_MBC_S       24
+#define EMAC_ADDR2H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR2L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR2L_ADDRLO_M    0xFFFFFFFF  // MAC Address2 [31:0]
+#define EMAC_ADDR2L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR3H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR3H_AE          0x80000000  // Address Enable
+#define EMAC_ADDR3H_SA          0x40000000  // Source Address
+#define EMAC_ADDR3H_MBC_M       0x3F000000  // Mask Byte Control
+#define EMAC_ADDR3H_ADDRHI_M    0x0000FFFF  // MAC Address3 [47:32]
+#define EMAC_ADDR3H_MBC_S       24
+#define EMAC_ADDR3H_ADDRHI_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR3L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR3L_ADDRLO_M    0xFFFFFFFF  // MAC Address3 [31:0]
+#define EMAC_ADDR3L_ADDRLO_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_WDOGTO register.
+//
+//*****************************************************************************
+#define EMAC_WDOGTO_PWE         0x00010000  // Programmable Watchdog Enable
+#define EMAC_WDOGTO_WTO_M       0x00003FFF  // Watchdog Timeout
+#define EMAC_WDOGTO_WTO_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCCTRL register.
+//
+//*****************************************************************************
+#define EMAC_MMCCTRL_UCDBC      0x00000100  // Update MMC Counters for Dropped
+                                            // Broadcast Frames
+#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020  // Full/Half Preset Level Value
+#define EMAC_MMCCTRL_CNTPRST    0x00000010  // Counters Preset
+#define EMAC_MMCCTRL_CNTFREEZ   0x00000008  // MMC Counter Freeze
+#define EMAC_MMCCTRL_RSTONRD    0x00000004  // Reset on Read
+#define EMAC_MMCCTRL_CNTSTPRO   0x00000002  // Counters Stop Rollover
+#define EMAC_MMCCTRL_CNTRST     0x00000001  // Counters Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCRXRIS
+// register.
+//
+//*****************************************************************************
+#define EMAC_MMCRXRIS_UCGF      0x00020000  // MMC Receive Unicast Good Frame
+                                            // Counter Interrupt Status
+#define EMAC_MMCRXRIS_ALGNERR   0x00000040  // MMC Receive Alignment Error
+                                            // Frame Counter Interrupt Status
+#define EMAC_MMCRXRIS_CRCERR    0x00000020  // MMC Receive CRC Error Frame
+                                            // Counter Interrupt Status
+#define EMAC_MMCRXRIS_GBF       0x00000001  // MMC Receive Good Bad Frame
+                                            // Counter Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCTXRIS
+// register.
+//
+//*****************************************************************************
+#define EMAC_MMCTXRIS_OCTCNT    0x00100000  // Octet Counter Interrupt Status
+#define EMAC_MMCTXRIS_MCOLLGF   0x00008000  // MMC Transmit Multiple Collision
+                                            // Good Frame Counter Interrupt
+                                            // Status
+#define EMAC_MMCTXRIS_SCOLLGF   0x00004000  // MMC Transmit Single Collision
+                                            // Good Frame Counter Interrupt
+                                            // Status
+#define EMAC_MMCTXRIS_GBF       0x00000002  // MMC Transmit Good Bad Frame
+                                            // Counter Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCRXIM register.
+//
+//*****************************************************************************
+#define EMAC_MMCRXIM_UCGF       0x00020000  // MMC Receive Unicast Good Frame
+                                            // Counter Interrupt Mask
+#define EMAC_MMCRXIM_ALGNERR    0x00000040  // MMC Receive Alignment Error
+                                            // Frame Counter Interrupt Mask
+#define EMAC_MMCRXIM_CRCERR     0x00000020  // MMC Receive CRC Error Frame
+                                            // Counter Interrupt Mask
+#define EMAC_MMCRXIM_GBF        0x00000001  // MMC Receive Good Bad Frame
+                                            // Counter Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCTXIM register.
+//
+//*****************************************************************************
+#define EMAC_MMCTXIM_OCTCNT     0x00100000  // MMC Transmit Good Octet Counter
+                                            // Interrupt Mask
+#define EMAC_MMCTXIM_MCOLLGF    0x00008000  // MMC Transmit Multiple Collision
+                                            // Good Frame Counter Interrupt
+                                            // Mask
+#define EMAC_MMCTXIM_SCOLLGF    0x00004000  // MMC Transmit Single Collision
+                                            // Good Frame Counter Interrupt
+                                            // Mask
+#define EMAC_MMCTXIM_GBF        0x00000002  // MMC Transmit Good Bad Frame
+                                            // Counter Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTGB register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTGB_TXFRMGB_M  0xFFFFFFFF  // This field indicates the number
+                                            // of good and bad frames
+                                            // transmitted, exclusive of
+                                            // retried frames
+#define EMAC_TXCNTGB_TXFRMGB_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTSCOL_TXSNGLCOLG_M                                           \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of successfully transmitted
+                                            // frames after a single collision
+                                            // in the half-duplex mode
+#define EMAC_TXCNTSCOL_TXSNGLCOLG_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTMCOL_TXMULTCOLG_M                                           \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of successfully transmitted
+                                            // frames after multiple collisions
+                                            // in the half-duplex mode
+#define EMAC_TXCNTMCOL_TXMULTCOLG_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF  // This field indicates the number
+                                            // of bytes transmitted, exclusive
+                                            // of preamble, in good frames
+#define EMAC_TXOCTCNTG_TXOCTG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTGB register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTGB_RXFRMGB_M  0xFFFFFFFF  // This field indicates the number
+                                            // of received good and bad frames
+#define EMAC_RXCNTGB_RXFRMGB_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTCRCERR_RXCRCERR_M                                           \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of frames received with CRC
+                                            // error
+#define EMAC_RXCNTCRCERR_RXCRCERR_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTALGNERR_RXALGNERR_M                                         \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of frames received with
+                                            // alignment (dribble) error
+#define EMAC_RXCNTALGNERR_RXALGNERR_S                                         \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTGUNI_RXUCASTG_M                                             \
+                                0xFFFFFFFF  // This field indicates the number
+                                            // of received good unicast frames
+#define EMAC_RXCNTGUNI_RXUCASTG_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLNINCREP
+// register.
+//
+//*****************************************************************************
+#define EMAC_VLNINCREP_CSVL     0x00080000  // C-VLAN or S-VLAN
+#define EMAC_VLNINCREP_VLP      0x00040000  // VLAN Priority Control
+#define EMAC_VLNINCREP_VLC_M    0x00030000  // VLAN Tag Control in Transmit
+                                            // Frames
+#define EMAC_VLNINCREP_VLC_NONE 0x00000000  // No VLAN tag deletion, insertion,
+                                            // or replacement
+#define EMAC_VLNINCREP_VLC_TAGDEL                                             \
+                                0x00010000  // VLAN tag deletion
+#define EMAC_VLNINCREP_VLC_TAGINS                                             \
+                                0x00020000  // VLAN tag insertion
+#define EMAC_VLNINCREP_VLC_TAGREP                                             \
+                                0x00030000  // VLAN tag replacement
+#define EMAC_VLNINCREP_VLT_M    0x0000FFFF  // VLAN Tag for Transmit Frames
+#define EMAC_VLNINCREP_VLT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLANHASH
+// register.
+//
+//*****************************************************************************
+#define EMAC_VLANHASH_VLHT_M    0x0000FFFF  // VLAN Hash Table
+#define EMAC_VLANHASH_VLHT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TIMSTCTRL_PTPFLTR  0x00040000  // Enable MAC address for PTP Frame
+                                            // Filtering
+#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000  // Select PTP packets for Taking
+                                            // Snapshots
+#define EMAC_TIMSTCTRL_TSMAST   0x00008000  // Enable Snapshot for Messages
+                                            // Relevant to Master
+#define EMAC_TIMSTCTRL_TSEVNT   0x00004000  // Enable Timestamp Snapshot for
+                                            // Event Messages
+#define EMAC_TIMSTCTRL_PTPIPV4  0x00002000  // Enable Processing of PTP Frames
+                                            // Sent over IPv4-UDP
+#define EMAC_TIMSTCTRL_PTPIPV6  0x00001000  // Enable Processing of PTP Frames
+                                            // Sent Over IPv6-UDP
+#define EMAC_TIMSTCTRL_PTPETH   0x00000800  // Enable Processing of PTP Over
+                                            // Ethernet Frames
+#define EMAC_TIMSTCTRL_PTPVER2  0x00000400  // Enable PTP Packet Processing For
+                                            // Version 2 Format
+#define EMAC_TIMSTCTRL_DGTLBIN  0x00000200  // Timestamp Digital or Binary
+                                            // Rollover Control
+#define EMAC_TIMSTCTRL_ALLF     0x00000100  // Enable Timestamp For All Frames
+#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020  // Addend Register Update
+#define EMAC_TIMSTCTRL_INTTRIG  0x00000010  // Timestamp Interrupt Trigger
+                                            // Enable
+#define EMAC_TIMSTCTRL_TSUPDT   0x00000008  // Timestamp Update
+#define EMAC_TIMSTCTRL_TSINIT   0x00000004  // Timestamp Initialize
+#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002  // Timestamp Fine or Coarse Update
+#define EMAC_TIMSTCTRL_TSEN     0x00000001  // Timestamp Enable
+#define EMAC_TIMSTCTRL_SELPTP_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_SUBSECINC
+// register.
+//
+//*****************************************************************************
+#define EMAC_SUBSECINC_SSINC_M  0x000000FF  // Sub-second Increment Value
+#define EMAC_SUBSECINC_SSINC_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSEC register.
+//
+//*****************************************************************************
+#define EMAC_TIMSEC_TSS_M       0xFFFFFFFF  // Timestamp Second
+#define EMAC_TIMSEC_TSS_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMNANO register.
+//
+//*****************************************************************************
+#define EMAC_TIMNANO_TSSS_M     0x7FFFFFFF  // Timestamp Sub-Seconds
+#define EMAC_TIMNANO_TSSS_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSECU register.
+//
+//*****************************************************************************
+#define EMAC_TIMSECU_TSS_M      0xFFFFFFFF  // Timestamp Second
+#define EMAC_TIMSECU_TSS_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMNANOU
+// register.
+//
+//*****************************************************************************
+#define EMAC_TIMNANOU_ADDSUB    0x80000000  // Add or subtract time
+#define EMAC_TIMNANOU_TSSS_M    0x7FFFFFFF  // Timestamp Sub-Second
+#define EMAC_TIMNANOU_TSSS_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMADD register.
+//
+//*****************************************************************************
+#define EMAC_TIMADD_TSAR_M      0xFFFFFFFF  // Timestamp Addend Register
+#define EMAC_TIMADD_TSAR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TARGSEC register.
+//
+//*****************************************************************************
+#define EMAC_TARGSEC_TSTR_M     0xFFFFFFFF  // Target Time Seconds Register
+#define EMAC_TARGSEC_TSTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TARGNANO
+// register.
+//
+//*****************************************************************************
+#define EMAC_TARGNANO_TRGTBUSY  0x80000000  // Target Time Register Busy
+#define EMAC_TARGNANO_TTSLO_M   0x7FFFFFFF  // Target Timestamp Low Register
+#define EMAC_TARGNANO_TTSLO_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HWORDSEC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HWORDSEC_TSHWR_M   0x0000FFFF  // Target Timestamp Higher Word
+                                            // Register
+#define EMAC_HWORDSEC_TSHWR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSTAT register.
+//
+//*****************************************************************************
+#define EMAC_TIMSTAT_TSTARGT    0x00000002  // Timestamp Target Time Reached
+#define EMAC_TIMSTAT_TSSOVF     0x00000001  // Timestamp Seconds Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPSCTRL register.
+//
+//*****************************************************************************
+#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060  // Target Time Register Mode for
+                                            // PPS0 Output
+#define EMAC_PPSCTRL_TRGMODS0_INTONLY                                         \
+                                0x00000000  // Indicates that the Target Time
+                                            // registers are programmed only
+                                            // for generating the interrupt
+                                            // event
+#define EMAC_PPSCTRL_TRGMODS0_INTPPS0                                         \
+                                0x00000040  // Indicates that the Target Time
+                                            // registers are programmed for
+                                            // generating the interrupt event
+                                            // and starting or stopping the
+                                            // generation of the EN0PPS output
+                                            // signal
+#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY                                        \
+                                0x00000060  // Indicates that the Target Time
+                                            // registers are programmed only
+                                            // for starting or stopping the
+                                            // generation of the EN0PPS output
+                                            // signal. No interrupt is asserted
+#define EMAC_PPSCTRL_PPSEN0     0x00000010  // Flexible PPS Output Mode Enable
+#define EMAC_PPSCTRL_PPSCTRL_M  0x0000000F  // EN0PPS Output Frequency Control
+                                            // (PPSCTRL) or Command Control
+                                            // (PPSCMD)
+#define EMAC_PPSCTRL_PPSCTRL_1HZ                                              \
+                                0x00000000  // When the PPSEN0 bit = 0x0, the
+                                            // EN0PPS signal is 1 pulse of the
+                                            // PTP reference clock.(of width
+                                            // clk_ptp_i) every second
+#define EMAC_PPSCTRL_PPSCTRL_2HZ                                              \
+                                0x00000001  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 2 Hz, and the
+                                            // digital rollover is 1 Hz
+#define EMAC_PPSCTRL_PPSCTRL_4HZ                                              \
+                                0x00000002  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 4 Hz, and the
+                                            // digital rollover is 2 Hz
+#define EMAC_PPSCTRL_PPSCTRL_8HZ                                              \
+                                0x00000003  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 8 Hz, and the
+                                            // digital rollover is 4 Hz,
+#define EMAC_PPSCTRL_PPSCTRL_16HZ                                             \
+                                0x00000004  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 16 Hz, and
+                                            // the digital rollover is 8 Hz
+#define EMAC_PPSCTRL_PPSCTRL_32HZ                                             \
+                                0x00000005  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 32 Hz, and
+                                            // the digital rollover is 16 Hz
+#define EMAC_PPSCTRL_PPSCTRL_64HZ                                             \
+                                0x00000006  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 64 Hz, and
+                                            // the digital rollover is 32 Hz
+#define EMAC_PPSCTRL_PPSCTRL_128HZ                                            \
+                                0x00000007  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 128 Hz, and
+                                            // the digital rollover is 64 Hz
+#define EMAC_PPSCTRL_PPSCTRL_256HZ                                            \
+                                0x00000008  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 256 Hz, and
+                                            // the digital rollover is 128 Hz
+#define EMAC_PPSCTRL_PPSCTRL_512HZ                                            \
+                                0x00000009  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 512 Hz, and
+                                            // the digital rollover is 256 Hz
+#define EMAC_PPSCTRL_PPSCTRL_1024HZ                                           \
+                                0x0000000A  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 1.024 kHz,
+                                            // and the digital rollover is 512
+                                            // Hz
+#define EMAC_PPSCTRL_PPSCTRL_2048HZ                                           \
+                                0x0000000B  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 2.048 kHz,
+                                            // and the digital rollover is
+                                            // 1.024 kHz
+#define EMAC_PPSCTRL_PPSCTRL_4096HZ                                           \
+                                0x0000000C  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 4.096 kHz,
+                                            // and the digital rollover is
+                                            // 2.048 kHz
+#define EMAC_PPSCTRL_PPSCTRL_8192HZ                                           \
+                                0x0000000D  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 8.192 kHz,
+                                            // and the digital rollover is
+                                            // 4.096 kHz
+#define EMAC_PPSCTRL_PPSCTRL_16384HZ                                          \
+                                0x0000000E  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 16.384 kHz,
+                                            // and the digital rollover is
+                                            // 8.092 kHz
+#define EMAC_PPSCTRL_PPSCTRL_32768HZ                                          \
+                                0x0000000F  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 32.768 KHz,
+                                            // and the digital rollover is
+                                            // 16.384 KHz
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPS0INTVL
+// register.
+//
+//*****************************************************************************
+#define EMAC_PPS0INTVL_PPS0INT_M                                              \
+                                0xFFFFFFFF  // PPS0 Output Signal Interval
+#define EMAC_PPS0INTVL_PPS0INT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH
+// register.
+//
+//*****************************************************************************
+#define EMAC_PPS0WIDTH_M        0xFFFFFFFF  // EN0PPS Output Signal Width
+#define EMAC_PPS0WIDTH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMABUSMOD
+// register.
+//
+//*****************************************************************************
+#define EMAC_DMABUSMOD_RIB      0x80000000  // Rebuild Burst
+#define EMAC_DMABUSMOD_TXPR     0x08000000  // Transmit Priority
+#define EMAC_DMABUSMOD_MB       0x04000000  // Mixed Burst
+#define EMAC_DMABUSMOD_AAL      0x02000000  // Address Aligned Beats
+#define EMAC_DMABUSMOD_8XPBL    0x01000000  // 8 x Programmable Burst Length
+                                            // (PBL) Mode
+#define EMAC_DMABUSMOD_USP      0x00800000  // Use Separate Programmable Burst
+                                            // Length (PBL)
+#define EMAC_DMABUSMOD_RPBL_M   0x007E0000  // RX DMA Programmable Burst Length
+                                            // (PBL)
+#define EMAC_DMABUSMOD_FB       0x00010000  // Fixed Burst
+#define EMAC_DMABUSMOD_PR_M     0x0000C000  // Priority Ratio
+#define EMAC_DMABUSMOD_PBL_M    0x00003F00  // Programmable Burst Length
+#define EMAC_DMABUSMOD_ATDS     0x00000080  // Alternate Descriptor Size
+#define EMAC_DMABUSMOD_DSL_M    0x0000007C  // Descriptor Skip Length
+#define EMAC_DMABUSMOD_DA       0x00000002  // DMA Arbitration Scheme
+#define EMAC_DMABUSMOD_SWR      0x00000001  // DMA Software Reset
+#define EMAC_DMABUSMOD_RPBL_S   17
+#define EMAC_DMABUSMOD_PR_S     14
+#define EMAC_DMABUSMOD_PBL_S    8
+#define EMAC_DMABUSMOD_DSL_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXPOLLD register.
+//
+//*****************************************************************************
+#define EMAC_TXPOLLD_TPD_M      0xFFFFFFFF  // Transmit Poll Demand
+#define EMAC_TXPOLLD_TPD_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXPOLLD register.
+//
+//*****************************************************************************
+#define EMAC_RXPOLLD_RPD_M      0xFFFFFFFF  // Receive Poll Demand
+#define EMAC_RXPOLLD_RPD_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXDLADDR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXDLADDR_STRXLIST_M                                              \
+                                0xFFFFFFFC  // Start of Receive List
+#define EMAC_RXDLADDR_STRXLIST_S                                              \
+                                2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXDLADDR
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXDLADDR_TXDLADDR_M                                              \
+                                0xFFFFFFFC  // Start of Transmit List Base
+                                            // Address
+#define EMAC_TXDLADDR_TXDLADDR_S                                              \
+                                2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMARIS register.
+//
+//*****************************************************************************
+#define EMAC_DMARIS_TT          0x20000000  // Timestamp Trigger Interrupt
+                                            // Status
+#define EMAC_DMARIS_PMT         0x10000000  // MAC PMT Interrupt Status
+#define EMAC_DMARIS_MMC         0x08000000  // MAC MMC Interrupt
+#define EMAC_DMARIS_AE_M        0x03800000  // Access Error
+#define EMAC_DMARIS_AE_RXDMAWD  0x00000000  // Error during RX DMA Write Data
+                                            // Transfer
+#define EMAC_DMARIS_AE_TXDMARD  0x01800000  // Error during TX DMA Read Data
+                                            // Transfer
+#define EMAC_DMARIS_AE_RXDMADW  0x02000000  // Error during RX DMA Descriptor
+                                            // Write Access
+#define EMAC_DMARIS_AE_TXDMADW  0x02800000  // Error during TX DMA Descriptor
+                                            // Write Access
+#define EMAC_DMARIS_AE_RXDMADR  0x03000000  // Error during RX DMA Descriptor
+                                            // Read Access
+#define EMAC_DMARIS_AE_TXDMADR  0x03800000  // Error during TX DMA Descriptor
+                                            // Read Access
+#define EMAC_DMARIS_TS_M        0x00700000  // Transmit Process State
+#define EMAC_DMARIS_TS_STOP     0x00000000  // Stopped; Reset or Stop transmit
+                                            // command processed
+#define EMAC_DMARIS_TS_RUNTXTD  0x00100000  // Running; Fetching transmit
+                                            // transfer descriptor
+#define EMAC_DMARIS_TS_STATUS   0x00200000  // Running; Waiting for status
+#define EMAC_DMARIS_TS_RUNTX    0x00300000  // Running; Reading data from host
+                                            // memory buffer and queuing it to
+                                            // transmit buffer (TX FIFO)
+#define EMAC_DMARIS_TS_TSTAMP   0x00400000  // Writing Timestamp
+#define EMAC_DMARIS_TS_SUSPEND  0x00600000  // Suspended; Transmit descriptor
+                                            // unavailable or transmit buffer
+                                            // underflow
+#define EMAC_DMARIS_TS_RUNCTD   0x00700000  // Running; Closing transmit
+                                            // descriptor
+#define EMAC_DMARIS_RS_M        0x000E0000  // Received Process State
+#define EMAC_DMARIS_RS_STOP     0x00000000  // Stopped: Reset or stop receive
+                                            // command issued
+#define EMAC_DMARIS_RS_RUNRXTD  0x00020000  // Running: Fetching receive
+                                            // transfer descriptor
+#define EMAC_DMARIS_RS_RUNRXD   0x00060000  // Running: Waiting for receive
+                                            // packet
+#define EMAC_DMARIS_RS_SUSPEND  0x00080000  // Suspended: Receive descriptor
+                                            // unavailable
+#define EMAC_DMARIS_RS_RUNCRD   0x000A0000  // Running: Closing receive
+                                            // descriptor
+#define EMAC_DMARIS_RS_TSWS     0x000C0000  // Writing Timestamp
+#define EMAC_DMARIS_RS_RUNTXD   0x000E0000  // Running: Transferring the
+                                            // receive packet data from receive
+                                            // buffer to host memory
+#define EMAC_DMARIS_NIS         0x00010000  // Normal Interrupt Summary
+#define EMAC_DMARIS_AIS         0x00008000  // Abnormal Interrupt Summary
+#define EMAC_DMARIS_ERI         0x00004000  // Early Receive Interrupt
+#define EMAC_DMARIS_FBI         0x00002000  // Fatal Bus Error Interrupt
+#define EMAC_DMARIS_ETI         0x00000400  // Early Transmit Interrupt
+#define EMAC_DMARIS_RWT         0x00000200  // Receive Watchdog Timeout
+#define EMAC_DMARIS_RPS         0x00000100  // Receive Process Stopped
+#define EMAC_DMARIS_RU          0x00000080  // Receive Buffer Unavailable
+#define EMAC_DMARIS_RI          0x00000040  // Receive Interrupt
+#define EMAC_DMARIS_UNF         0x00000020  // Transmit Underflow
+#define EMAC_DMARIS_OVF         0x00000010  // Receive Overflow
+#define EMAC_DMARIS_TJT         0x00000008  // Transmit Jabber Timeout
+#define EMAC_DMARIS_TU          0x00000004  // Transmit Buffer Unavailable
+#define EMAC_DMARIS_TPS         0x00000002  // Transmit Process Stopped
+#define EMAC_DMARIS_TI          0x00000001  // Transmit Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMAOPMODE
+// register.
+//
+//*****************************************************************************
+#define EMAC_DMAOPMODE_DT       0x04000000  // Disable Dropping of TCP/IP
+                                            // Checksum Error Frames
+#define EMAC_DMAOPMODE_RSF      0x02000000  // Receive Store and Forward
+#define EMAC_DMAOPMODE_DFF      0x01000000  // Disable Flushing of Received
+                                            // Frames
+#define EMAC_DMAOPMODE_TSF      0x00200000  // Transmit Store and Forward
+#define EMAC_DMAOPMODE_FTF      0x00100000  // Flush Transmit FIFO
+#define EMAC_DMAOPMODE_TTC_M    0x0001C000  // Transmit Threshold Control
+#define EMAC_DMAOPMODE_TTC_64   0x00000000  // 64 bytes
+#define EMAC_DMAOPMODE_TTC_128  0x00004000  // 128 bytes
+#define EMAC_DMAOPMODE_TTC_192  0x00008000  // 192 bytes
+#define EMAC_DMAOPMODE_TTC_256  0x0000C000  // 256 bytes
+#define EMAC_DMAOPMODE_TTC_40   0x00010000  // 40 bytes
+#define EMAC_DMAOPMODE_TTC_32   0x00014000  // 32 bytes
+#define EMAC_DMAOPMODE_TTC_24   0x00018000  // 24 bytes
+#define EMAC_DMAOPMODE_TTC_16   0x0001C000  // 16 bytes
+#define EMAC_DMAOPMODE_ST       0x00002000  // Start or Stop Transmission
+                                            // Command
+#define EMAC_DMAOPMODE_FEF      0x00000080  // Forward Error Frames
+#define EMAC_DMAOPMODE_FUF      0x00000040  // Forward Undersized Good Frames
+#define EMAC_DMAOPMODE_DGF      0x00000020  // Drop Giant Frame Enable
+#define EMAC_DMAOPMODE_RTC_M    0x00000018  // Receive Threshold Control
+#define EMAC_DMAOPMODE_RTC_64   0x00000000  // 64 bytes
+#define EMAC_DMAOPMODE_RTC_32   0x00000008  // 32 bytes
+#define EMAC_DMAOPMODE_RTC_96   0x00000010  // 96 bytes
+#define EMAC_DMAOPMODE_RTC_128  0x00000018  // 128 bytes
+#define EMAC_DMAOPMODE_OSF      0x00000004  // Operate on Second Frame
+#define EMAC_DMAOPMODE_SR       0x00000002  // Start or Stop Receive
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMAIM register.
+//
+//*****************************************************************************
+#define EMAC_DMAIM_NIE          0x00010000  // Normal Interrupt Summary Enable
+#define EMAC_DMAIM_AIE          0x00008000  // Abnormal Interrupt Summary
+                                            // Enable
+#define EMAC_DMAIM_ERE          0x00004000  // Early Receive Interrupt Enable
+#define EMAC_DMAIM_FBE          0x00002000  // Fatal Bus Error Enable
+#define EMAC_DMAIM_ETE          0x00000400  // Early Transmit Interrupt Enable
+#define EMAC_DMAIM_RWE          0x00000200  // Receive Watchdog Timeout Enable
+#define EMAC_DMAIM_RSE          0x00000100  // Receive Stopped Enable
+#define EMAC_DMAIM_RUE          0x00000080  // Receive Buffer Unavailable
+                                            // Enable
+#define EMAC_DMAIM_RIE          0x00000040  // Receive Interrupt Enable
+#define EMAC_DMAIM_UNE          0x00000020  // Underflow Interrupt Enable
+#define EMAC_DMAIM_OVE          0x00000010  // Overflow Interrupt Enable
+#define EMAC_DMAIM_TJE          0x00000008  // Transmit Jabber Timeout Enable
+#define EMAC_DMAIM_TUE          0x00000004  // Transmit Buffer Unvailable
+                                            // Enable
+#define EMAC_DMAIM_TSE          0x00000002  // Transmit Stopped Enable
+#define EMAC_DMAIM_TIE          0x00000001  // Transmit Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MFBOC register.
+//
+//*****************************************************************************
+#define EMAC_MFBOC_OVFCNTOVF    0x10000000  // Overflow Bit for FIFO Overflow
+                                            // Counter
+#define EMAC_MFBOC_OVFFRMCNT_M  0x0FFE0000  // Overflow Frame Counter
+#define EMAC_MFBOC_MISCNTOVF    0x00010000  // Overflow bit for Missed Frame
+                                            // Counter
+#define EMAC_MFBOC_MISFRMCNT_M  0x0000FFFF  // Missed Frame Counter
+#define EMAC_MFBOC_OVFFRMCNT_S  17
+#define EMAC_MFBOC_MISFRMCNT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXINTWDT
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXINTWDT_RIWT_M    0x000000FF  // Receive Interrupt Watchdog Timer
+                                            // Count
+#define EMAC_RXINTWDT_RIWT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSTXDESC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HOSTXDESC_CURTXDESC_M                                            \
+                                0xFFFFFFFF  // Host Transmit Descriptor Address
+                                            // Pointer
+#define EMAC_HOSTXDESC_CURTXDESC_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSRXDESC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HOSRXDESC_CURRXDESC_M                                            \
+                                0xFFFFFFFF  // Host Receive Descriptor Address
+                                            // Pointer
+#define EMAC_HOSRXDESC_CURRXDESC_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSTXBA register.
+//
+//*****************************************************************************
+#define EMAC_HOSTXBA_CURTXBUFA_M                                              \
+                                0xFFFFFFFF  // Host Transmit Buffer Address
+                                            // Pointer
+#define EMAC_HOSTXBA_CURTXBUFA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSRXBA register.
+//
+//*****************************************************************************
+#define EMAC_HOSRXBA_CURRXBUFA_M                                              \
+                                0xFFFFFFFF  // Host Receive Buffer Address
+                                            // Pointer
+#define EMAC_HOSRXBA_CURRXBUFA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PP register.
+//
+//*****************************************************************************
+#define EMAC_PP_MACTYPE_M       0x00000700  // Ethernet MAC Type
+#define EMAC_PP_MACTYPE_1       0x00000100  // Tiva TM4E129x-class MAC
+#define EMAC_PP_PHYTYPE_M       0x00000007  // Ethernet PHY Type
+#define EMAC_PP_PHYTYPE_NONE    0x00000000  // No PHY
+#define EMAC_PP_PHYTYPE_1       0x00000003  // Snowflake class PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PC register.
+//
+//*****************************************************************************
+#define EMAC_PC_PHYEXT          0x80000000  // PHY Select
+#define EMAC_PC_PINTFS_M        0x70000000  // Ethernet Interface Select
+#define EMAC_PC_PINTFS_IMII     0x00000000  // MII (default) Used for internal
+                                            // PHY or external PHY connected
+                                            // via MII
+#define EMAC_PC_PINTFS_RMII     0x40000000  // RMII: Used for external PHY
+                                            // connected via RMII
+#define EMAC_PC_DIGRESTART      0x02000000  // PHY Soft Restart
+#define EMAC_PC_NIBDETDIS       0x01000000  // Odd Nibble TXER Detection
+                                            // Disable
+#define EMAC_PC_RXERIDLE        0x00800000  // RXER Detection During Idle
+#define EMAC_PC_ISOMIILL        0x00400000  // Isolate MII in Link Loss
+#define EMAC_PC_LRR             0x00200000  // Link Loss Recovery
+#define EMAC_PC_TDRRUN          0x00100000  // TDR Auto Run
+#define EMAC_PC_FASTLDMODE_M    0x000F8000  // Fast Link Down Mode
+#define EMAC_PC_POLSWAP         0x00004000  // Polarity Swap
+#define EMAC_PC_MDISWAP         0x00002000  // MDI Swap
+#define EMAC_PC_RBSTMDIX        0x00001000  // Robust Auto MDI-X
+#define EMAC_PC_FASTMDIX        0x00000800  // Fast Auto MDI-X
+#define EMAC_PC_MDIXEN          0x00000400  // MDIX Enable
+#define EMAC_PC_FASTRXDV        0x00000200  // Fast RXDV Detection
+#define EMAC_PC_FASTLUPD        0x00000100  // FAST Link-Up in Parallel Detect
+#define EMAC_PC_EXTFD           0x00000080  // Extended Full Duplex Ability
+#define EMAC_PC_FASTANEN        0x00000040  // Fast Auto Negotiation Enable
+#define EMAC_PC_FASTANSEL_M     0x00000030  // Fast Auto Negotiation Select
+#define EMAC_PC_ANEN            0x00000008  // Auto Negotiation Enable
+#define EMAC_PC_ANMODE_M        0x00000006  // Auto Negotiation Mode
+#define EMAC_PC_ANMODE_10HD     0x00000000  // When ANEN = 0x0, the mode is
+                                            // 10Base-T, Half-Duplex
+#define EMAC_PC_ANMODE_10FD     0x00000002  // When ANEN = 0x0, the mode is
+                                            // 10Base-T, Full-Duplex
+#define EMAC_PC_ANMODE_100HD    0x00000004  // When ANEN = 0x0, the mode is
+                                            // 100Base-TX, Half-Duplex
+#define EMAC_PC_ANMODE_100FD    0x00000006  // When ANEN = 0x0, the mode is
+                                            // 100Base-TX, Full-Duplex
+#define EMAC_PC_PHYHOLD         0x00000001  // Ethernet PHY Hold
+#define EMAC_PC_FASTLDMODE_S    15
+#define EMAC_PC_FASTANSEL_S     4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_CC register.
+//
+//*****************************************************************************
+#define EMAC_CC_PTPCEN          0x00040000  // PTP Clock Reference Enable
+#define EMAC_CC_POL             0x00020000  // LED Polarity Control
+#define EMAC_CC_CLKEN           0x00010000  // EN0RREF_CLK Signal Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYRIS register.
+//
+//*****************************************************************************
+#define EMAC_EPHYRIS_INT        0x00000001  // Ethernet PHY Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYIM register.
+//
+//*****************************************************************************
+#define EMAC_EPHYIM_INT         0x00000001  // Ethernet PHY Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYMISC
+// register.
+//
+//*****************************************************************************
+#define EMAC_EPHYMISC_INT       0x00000001  // Ethernet PHY Status and Clear
+                                            // register
+
+//*****************************************************************************
+//
+// The following are defines for the EPHY register offsets.
+//
+//*****************************************************************************
+#define EPHY_BMCR               0x00000000  // Ethernet PHY Basic Mode Control
+#define EPHY_BMSR               0x00000001  // Ethernet PHY Basic Mode Status
+#define EPHY_ID1                0x00000002  // Ethernet PHY Identifier Register
+                                            // 1
+#define EPHY_ID2                0x00000003  // Ethernet PHY Identifier Register
+                                            // 2
+#define EPHY_ANA                0x00000004  // Ethernet PHY Auto-Negotiation
+                                            // Advertisement
+#define EPHY_ANLPA              0x00000005  // Ethernet PHY Auto-Negotiation
+                                            // Link Partner Ability
+#define EPHY_ANER               0x00000006  // Ethernet PHY Auto-Negotiation
+                                            // Expansion
+#define EPHY_ANNPTR             0x00000007  // Ethernet PHY Auto-Negotiation
+                                            // Next Page TX
+#define EPHY_ANLNPTR            0x00000008  // Ethernet PHY Auto-Negotiation
+                                            // Link Partner Ability Next Page
+#define EPHY_CFG1               0x00000009  // Ethernet PHY Configuration 1
+#define EPHY_CFG2               0x0000000A  // Ethernet PHY Configuration 2
+#define EPHY_CFG3               0x0000000B  // Ethernet PHY Configuration 3
+#define EPHY_REGCTL             0x0000000D  // Ethernet PHY Register Control
+#define EPHY_ADDAR              0x0000000E  // Ethernet PHY Address or Data
+#define EPHY_STS                0x00000010  // Ethernet PHY Status
+#define EPHY_SCR                0x00000011  // Ethernet PHY Specific Control
+#define EPHY_MISR1              0x00000012  // Ethernet PHY MII Interrupt
+                                            // Status 1
+#define EPHY_MISR2              0x00000013  // Ethernet PHY MII Interrupt
+                                            // Status 2
+#define EPHY_FCSCR              0x00000014  // Ethernet PHY False Carrier Sense
+                                            // Counter
+#define EPHY_RXERCNT            0x00000015  // Ethernet PHY Receive Error Count
+#define EPHY_BISTCR             0x00000016  // Ethernet PHY BIST Control
+#define EPHY_LEDCR              0x00000018  // Ethernet PHY LED Control
+#define EPHY_CTL                0x00000019  // Ethernet PHY Control
+#define EPHY_10BTSC             0x0000001A  // Ethernet PHY 10Base-T
+                                            // Status/Control - MR26
+#define EPHY_BICSR1             0x0000001B  // Ethernet PHY BIST Control and
+                                            // Status 1
+#define EPHY_BICSR2             0x0000001C  // Ethernet PHY BIST Control and
+                                            // Status 2
+#define EPHY_CDCR               0x0000001E  // Ethernet PHY Cable Diagnostic
+                                            // Control
+#define EPHY_RCR                0x0000001F  // Ethernet PHY Reset Control
+#define EPHY_LEDCFG             0x00000025  // Ethernet PHY LED Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BMCR register.
+//
+//*****************************************************************************
+#define EPHY_BMCR_MIIRESET      0x00008000  // MII Register reset
+#define EPHY_BMCR_MIILOOPBK     0x00004000  // MII Loopback
+#define EPHY_BMCR_SPEED         0x00002000  // Speed Select
+#define EPHY_BMCR_ANEN          0x00001000  // Auto-Negotiate Enable
+#define EPHY_BMCR_PWRDWN        0x00000800  // Power Down
+#define EPHY_BMCR_ISOLATE       0x00000400  // Port Isolate
+#define EPHY_BMCR_RESTARTAN     0x00000200  // Restart Auto-Negotiation
+#define EPHY_BMCR_DUPLEXM       0x00000100  // Duplex Mode
+#define EPHY_BMCR_COLLTST       0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BMSR register.
+//
+//*****************************************************************************
+#define EPHY_BMSR_100BTXFD      0x00004000  // 100Base-TX Full Duplex Capable
+#define EPHY_BMSR_100BTXHD      0x00002000  // 100Base-TX Half Duplex Capable
+#define EPHY_BMSR_10BTFD        0x00001000  // 10 Base-T Full Duplex Capable
+#define EPHY_BMSR_10BTHD        0x00000800  // 10 Base-T Half Duplex Capable
+#define EPHY_BMSR_MFPRESUP      0x00000040  // Preamble Suppression Capable
+#define EPHY_BMSR_ANC           0x00000020  // Auto-Negotiation Complete
+#define EPHY_BMSR_RFAULT        0x00000010  // Remote Fault
+#define EPHY_BMSR_ANEN          0x00000008  // Auto Negotiation Enabled
+#define EPHY_BMSR_LINKSTAT      0x00000004  // Link Status
+#define EPHY_BMSR_JABBER        0x00000002  // Jabber Detect
+#define EPHY_BMSR_EXTEN         0x00000001  // Extended Capability Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ID1 register.
+//
+//*****************************************************************************
+#define EPHY_ID1_OUIMSB_M       0x0000FFFF  // OUI Most Significant Bits
+#define EPHY_ID1_OUIMSB_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ID2 register.
+//
+//*****************************************************************************
+#define EPHY_ID2_OUILSB_M       0x0000FC00  // OUI Least Significant Bits
+#define EPHY_ID2_VNDRMDL_M      0x000003F0  // Vendor Model Number
+#define EPHY_ID2_MDLREV_M       0x0000000F  // Model Revision Number
+#define EPHY_ID2_OUILSB_S       10
+#define EPHY_ID2_VNDRMDL_S      4
+#define EPHY_ID2_MDLREV_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANA register.
+//
+//*****************************************************************************
+#define EPHY_ANA_NP             0x00008000  // Next Page Indication
+#define EPHY_ANA_RF             0x00002000  // Remote Fault
+#define EPHY_ANA_ASMDUP         0x00000800  // Asymmetric PAUSE support for
+                                            // Full Duplex Links
+#define EPHY_ANA_PAUSE          0x00000400  // PAUSE Support for Full Duplex
+                                            // Links
+#define EPHY_ANA_100BT4         0x00000200  // 100Base-T4 Support
+#define EPHY_ANA_100BTXFD       0x00000100  // 100Base-TX Full Duplex Support
+#define EPHY_ANA_100BTX         0x00000080  // 100Base-TX Support
+#define EPHY_ANA_10BTFD         0x00000040  // 10Base-T Full Duplex Support
+#define EPHY_ANA_10BT           0x00000020  // 10Base-T Support
+#define EPHY_ANA_SELECT_M       0x0000001F  // Protocol Selection
+#define EPHY_ANA_SELECT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANLPA register.
+//
+//*****************************************************************************
+#define EPHY_ANLPA_NP           0x00008000  // Next Page Indication
+#define EPHY_ANLPA_ACK          0x00004000  // Acknowledge
+#define EPHY_ANLPA_RF           0x00002000  // Remote Fault
+#define EPHY_ANLPA_ASMDUP       0x00000800  // Asymmetric PAUSE
+#define EPHY_ANLPA_PAUSE        0x00000400  // PAUSE
+#define EPHY_ANLPA_100BT4       0x00000200  // 100Base-T4 Support
+#define EPHY_ANLPA_100BTXFD     0x00000100  // 100Base-TX Full Duplex Support
+#define EPHY_ANLPA_100BTX       0x00000080  // 100Base-TX Support
+#define EPHY_ANLPA_10BTFD       0x00000040  // 10Base-T Full Duplex Support
+#define EPHY_ANLPA_10BT         0x00000020  // 10Base-T Support
+#define EPHY_ANLPA_SELECT_M     0x0000001F  // Protocol Selection
+#define EPHY_ANLPA_SELECT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANER register.
+//
+//*****************************************************************************
+#define EPHY_ANER_PDF           0x00000010  // Parallel Detection Fault
+#define EPHY_ANER_LPNPABLE      0x00000008  // Link Partner Next Page Able
+#define EPHY_ANER_NPABLE        0x00000004  // Next Page Able
+#define EPHY_ANER_PAGERX        0x00000002  // Link Code Word Page Received
+#define EPHY_ANER_LPANABLE      0x00000001  // Link Partner Auto-Negotiation
+                                            // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANNPTR register.
+//
+//*****************************************************************************
+#define EPHY_ANNPTR_NP          0x00008000  // Next Page Indication
+#define EPHY_ANNPTR_MP          0x00002000  // Message Page
+#define EPHY_ANNPTR_ACK2        0x00001000  // Acknowledge 2
+#define EPHY_ANNPTR_TOGTX       0x00000800  // Toggle
+#define EPHY_ANNPTR_CODE_M      0x000007FF  // Code
+#define EPHY_ANNPTR_CODE_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANLNPTR register.
+//
+//*****************************************************************************
+#define EPHY_ANLNPTR_NP         0x00008000  // Next Page Indication
+#define EPHY_ANLNPTR_ACK        0x00004000  // Acknowledge
+#define EPHY_ANLNPTR_MP         0x00002000  // Message Page
+#define EPHY_ANLNPTR_ACK2       0x00001000  // Acknowledge 2
+#define EPHY_ANLNPTR_TOG        0x00000800  // Toggle
+#define EPHY_ANLNPTR_CODE_M     0x000007FF  // Code
+#define EPHY_ANLNPTR_CODE_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG1 register.
+//
+//*****************************************************************************
+#define EPHY_CFG1_DONE          0x00008000  // Configuration Done
+#define EPHY_CFG1_TDRAR         0x00000100  // TDR Auto-Run at Link Down
+#define EPHY_CFG1_LLR           0x00000080  // Link Loss Recovery
+#define EPHY_CFG1_FAMDIX        0x00000040  // Fast Auto MDI/MDIX
+#define EPHY_CFG1_RAMDIX        0x00000020  // Robust Auto MDI/MDIX
+#define EPHY_CFG1_FASTANEN      0x00000010  // Fast Auto Negotiation Enable
+#define EPHY_CFG1_FANSEL_M      0x0000000C  // Fast Auto-Negotiation Select
+                                            // Configuration
+#define EPHY_CFG1_FANSEL_BLT80  0x00000000  // Break Link Timer: 80 ms
+#define EPHY_CFG1_FANSEL_BLT120 0x00000004  // Break Link Timer: 120 ms
+#define EPHY_CFG1_FANSEL_BLT240 0x00000008  // Break Link Timer: 240 ms
+#define EPHY_CFG1_FRXDVDET      0x00000002  // FAST RXDV Detection
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG2 register.
+//
+//*****************************************************************************
+#define EPHY_CFG2_FLUPPD        0x00000040  // Fast Link-Up in Parallel Detect
+                                            // Mode
+#define EPHY_CFG2_EXTFD         0x00000020  // Extended Full-Duplex Ability
+#define EPHY_CFG2_ENLEDLINK     0x00000010  // Enhanced LED Functionality
+#define EPHY_CFG2_ISOMIILL      0x00000008  // Isolate MII outputs when
+                                            // Enhanced Link is not Achievable
+#define EPHY_CFG2_RXERRIDLE     0x00000004  // Detection of Receive Symbol
+                                            // Error During IDLE State
+#define EPHY_CFG2_ODDNDETDIS    0x00000002  // Detection of Transmit Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG3 register.
+//
+//*****************************************************************************
+#define EPHY_CFG3_POLSWAP       0x00000080  // Polarity Swap
+#define EPHY_CFG3_MDIMDIXS      0x00000040  // MDI/MDIX Swap
+#define EPHY_CFG3_FLDWNM_M      0x0000001F  // Fast Link Down Modes
+#define EPHY_CFG3_FLDWNM_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_REGCTL register.
+//
+//*****************************************************************************
+#define EPHY_REGCTL_FUNC_M      0x0000C000  // Function
+#define EPHY_REGCTL_FUNC_ADDR   0x00000000  // Address
+#define EPHY_REGCTL_FUNC_DATANI 0x00004000  // Data, no post increment
+#define EPHY_REGCTL_FUNC_DATAPIRW                                             \
+                                0x00008000  // Data, post increment on read and
+                                            // write
+#define EPHY_REGCTL_FUNC_DATAPIWO                                             \
+                                0x0000C000  // Data, post increment on write
+                                            // only
+#define EPHY_REGCTL_DEVAD_M     0x0000001F  // Device Address
+#define EPHY_REGCTL_DEVAD_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ADDAR register.
+//
+//*****************************************************************************
+#define EPHY_ADDAR_ADDRDATA_M   0x0000FFFF  // Address or Data
+#define EPHY_ADDAR_ADDRDATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_STS register.
+//
+//*****************************************************************************
+#define EPHY_STS_MDIXM          0x00004000  // MDI-X Mode
+#define EPHY_STS_RXLERR         0x00002000  // Receive Error Latch
+#define EPHY_STS_POLSTAT        0x00001000  // Polarity Status
+#define EPHY_STS_FCSL           0x00000800  // False Carrier Sense Latch
+#define EPHY_STS_SD             0x00000400  // Signal Detect
+#define EPHY_STS_DL             0x00000200  // Descrambler Lock
+#define EPHY_STS_PAGERX         0x00000100  // Link Code Page Received
+#define EPHY_STS_MIIREQ         0x00000080  // MII Interrupt Pending
+#define EPHY_STS_RF             0x00000040  // Remote Fault
+#define EPHY_STS_JD             0x00000020  // Jabber Detect
+#define EPHY_STS_ANS            0x00000010  // Auto-Negotiation Status
+#define EPHY_STS_MIILB          0x00000008  // MII Loopback Status
+#define EPHY_STS_DUPLEX         0x00000004  // Duplex Status
+#define EPHY_STS_SPEED          0x00000002  // Speed Status
+#define EPHY_STS_LINK           0x00000001  // Link Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_SCR register.
+//
+//*****************************************************************************
+#define EPHY_SCR_DISCLK         0x00008000  // Disable CLK
+#define EPHY_SCR_PSEN           0x00004000  // Power Saving Modes Enable
+#define EPHY_SCR_PSMODE_M       0x00003000  // Power Saving Modes
+#define EPHY_SCR_PSMODE_NORMAL  0x00000000  // Normal: Normal operation mode.
+                                            // PHY is fully functional
+#define EPHY_SCR_PSMODE_LOWPWR  0x00001000  // IEEE Power Down
+#define EPHY_SCR_PSMODE_ACTWOL  0x00002000  // Active Sleep
+#define EPHY_SCR_PSMODE_PASWOL  0x00003000  // Passive Sleep
+#define EPHY_SCR_SBPYASS        0x00000800  // Scrambler Bypass
+#define EPHY_SCR_LBFIFO_M       0x00000300  // Loopback FIFO Depth
+#define EPHY_SCR_LBFIFO_4       0x00000000  // Four nibble FIFO
+#define EPHY_SCR_LBFIFO_5       0x00000100  // Five nibble FIFO
+#define EPHY_SCR_LBFIFO_6       0x00000200  // Six nibble FIFO
+#define EPHY_SCR_LBFIFO_8       0x00000300  // Eight nibble FIFO
+#define EPHY_SCR_COLFDM         0x00000010  // Collision in Full-Duplex Mode
+#define EPHY_SCR_TINT           0x00000004  // Test Interrupt
+#define EPHY_SCR_INTEN          0x00000002  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_MISR1 register.
+//
+//*****************************************************************************
+#define EPHY_MISR1_LINKSTAT     0x00002000  // Change of Link Status Interrupt
+#define EPHY_MISR1_SPEED        0x00001000  // Change of Speed Status Interrupt
+#define EPHY_MISR1_DUPLEXM      0x00000800  // Change of Duplex Status
+                                            // Interrupt
+#define EPHY_MISR1_ANC          0x00000400  // Auto-Negotiation Complete
+                                            // Interrupt
+#define EPHY_MISR1_FCHF         0x00000200  // False Carrier Counter Half-Full
+                                            // Interrupt
+#define EPHY_MISR1_RXHF         0x00000100  // Receive Error Counter Half-Full
+                                            // Interrupt
+#define EPHY_MISR1_LINKSTATEN   0x00000020  // Link Status Interrupt Enable
+#define EPHY_MISR1_SPEEDEN      0x00000010  // Speed Change Interrupt Enable
+#define EPHY_MISR1_DUPLEXMEN    0x00000008  // Duplex Status Interrupt Enable
+#define EPHY_MISR1_ANCEN        0x00000004  // Auto-Negotiation Complete
+                                            // Interrupt Enable
+#define EPHY_MISR1_FCHFEN       0x00000002  // False Carrier Counter Register
+                                            // half-full Interrupt Enable
+#define EPHY_MISR1_RXHFEN       0x00000001  // Receive Error Counter Register
+                                            // Half-Full Event Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_MISR2 register.
+//
+//*****************************************************************************
+#define EPHY_MISR2_ANERR        0x00004000  // Auto-Negotiation Error Interrupt
+#define EPHY_MISR2_PAGERX       0x00002000  // Page Receive Interrupt
+#define EPHY_MISR2_LBFIFO       0x00001000  // Loopback FIFO Overflow/Underflow
+                                            // Event Interrupt
+#define EPHY_MISR2_MDICO        0x00000800  // MDI/MDIX Crossover Status
+                                            // Changed Interrupt
+#define EPHY_MISR2_SLEEP        0x00000400  // Sleep Mode Event Interrupt
+#define EPHY_MISR2_POLINT       0x00000200  // Polarity Changed Interrupt
+#define EPHY_MISR2_JABBER       0x00000100  // Jabber Detect Event Interrupt
+#define EPHY_MISR2_ANERREN      0x00000040  // Auto-Negotiation Error Interrupt
+                                            // Enable
+#define EPHY_MISR2_PAGERXEN     0x00000020  // Page Receive Interrupt Enable
+#define EPHY_MISR2_LBFIFOEN     0x00000010  // Loopback FIFO Overflow/Underflow
+                                            // Interrupt Enable
+#define EPHY_MISR2_MDICOEN      0x00000008  // MDI/MDIX Crossover Status
+                                            // Changed Interrupt Enable
+#define EPHY_MISR2_SLEEPEN      0x00000004  // Sleep Mode Event Interrupt
+                                            // Enable
+#define EPHY_MISR2_POLINTEN     0x00000002  // Polarity Changed Interrupt
+                                            // Enable
+#define EPHY_MISR2_JABBEREN     0x00000001  // Jabber Detect Event Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_FCSCR register.
+//
+//*****************************************************************************
+#define EPHY_FCSCR_FCSCNT_M     0x000000FF  // False Carrier Event Counter
+#define EPHY_FCSCR_FCSCNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_RXERCNT register.
+//
+//*****************************************************************************
+#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF  // Receive Error Count
+#define EPHY_RXERCNT_RXERRCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BISTCR register.
+//
+//*****************************************************************************
+#define EPHY_BISTCR_PRBSM       0x00004000  // PRBS Single/Continuous Mode
+#define EPHY_BISTCR_PRBSPKT     0x00002000  // Generated PRBS Packets
+#define EPHY_BISTCR_PKTEN       0x00001000  // Packet Generation Enable
+#define EPHY_BISTCR_PRBSCHKLK   0x00000800  // PRBS Checker Lock Indication
+#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400  // PRBS Checker Lock Sync Loss
+                                            // Indication
+#define EPHY_BISTCR_PKTGENSTAT  0x00000200  // Packet Generator Status
+                                            // Indication
+#define EPHY_BISTCR_PWRMODE     0x00000100  // Power Mode Indication
+#define EPHY_BISTCR_TXMIILB     0x00000040  // Transmit Data in MII Loopback
+                                            // Mode
+#define EPHY_BISTCR_LBMODE_M    0x0000001F  // Loopback Mode Select
+#define EPHY_BISTCR_LBMODE_NPCSIN                                             \
+                                0x00000001  // Near-end loopback: PCS Input
+                                            // Loopback
+#define EPHY_BISTCR_LBMODE_NPCSOUT                                            \
+                                0x00000002  // Near-end loopback: PCS Output
+                                            // Loopback (In 100Base-TX only)
+#define EPHY_BISTCR_LBMODE_NDIG 0x00000004  // Near-end loopback: Digital
+                                            // Loopback
+#define EPHY_BISTCR_LBMODE_NANA 0x00000008  // Near-end loopback: Analog
+                                            // Loopback (requires 100 Ohm
+                                            // termination)
+#define EPHY_BISTCR_LBMODE_FREV 0x00000010  // Far-end Loopback: Reverse
+                                            // Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_LEDCR register.
+//
+//*****************************************************************************
+#define EPHY_LEDCR_BLINKRATE_M  0x00000600  // LED Blinking Rate (ON/OFF
+                                            // duration):
+#define EPHY_LEDCR_BLINKRATE_20HZ                                             \
+                                0x00000000  // 20 Hz (50 ms)
+#define EPHY_LEDCR_BLINKRATE_10HZ                                             \
+                                0x00000200  // 10 Hz (100 ms)
+#define EPHY_LEDCR_BLINKRATE_5HZ                                              \
+                                0x00000400  // 5 Hz (200 ms)
+#define EPHY_LEDCR_BLINKRATE_2HZ                                              \
+                                0x00000600  // 2 Hz (500 ms)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CTL register.
+//
+//*****************************************************************************
+#define EPHY_CTL_AUTOMDI        0x00008000  // Auto-MDIX Enable
+#define EPHY_CTL_FORCEMDI       0x00004000  // Force MDIX
+#define EPHY_CTL_PAUSERX        0x00002000  // Pause Receive Negotiated Status
+#define EPHY_CTL_PAUSETX        0x00001000  // Pause Transmit Negotiated Status
+#define EPHY_CTL_MIILNKSTAT     0x00000800  // MII Link Status
+#define EPHY_CTL_BYPLEDSTRCH    0x00000080  // Bypass LED Stretching
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_10BTSC register.
+//
+//*****************************************************************************
+#define EPHY_10BTSC_RXTHEN      0x00002000  // Lower Receiver Threshold Enable
+#define EPHY_10BTSC_SQUELCH_M   0x00001E00  // Squelch Configuration
+#define EPHY_10BTSC_NLPDIS      0x00000080  // Normal Link Pulse (NLP)
+                                            // Transmission Control
+#define EPHY_10BTSC_POLSTAT     0x00000010  // 10 Mb Polarity Status
+#define EPHY_10BTSC_JABBERD     0x00000001  // Jabber Disable
+#define EPHY_10BTSC_SQUELCH_S   9
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BICSR1 register.
+//
+//*****************************************************************************
+#define EPHY_BICSR1_ERRCNT_M    0x0000FF00  // BIST Error Count
+#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF  // BIST IPG Length
+#define EPHY_BICSR1_ERRCNT_S    8
+#define EPHY_BICSR1_IPGLENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BICSR2 register.
+//
+//*****************************************************************************
+#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF  // BIST Packet Length
+#define EPHY_BICSR2_PKTLENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CDCR register.
+//
+//*****************************************************************************
+#define EPHY_CDCR_START         0x00008000  // Cable Diagnostic Process Start
+#define EPHY_CDCR_LINKQUAL_M    0x00000300  // Link Quality Indication
+#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100  // Good Quality Link Indication
+#define EPHY_CDCR_LINKQUAL_MILD 0x00000200  // Mid- Quality Link Indication
+#define EPHY_CDCR_LINKQUAL_POOR 0x00000300  // Poor Quality Link Indication
+#define EPHY_CDCR_DONE          0x00000002  // Cable Diagnostic Process Done
+#define EPHY_CDCR_FAIL          0x00000001  // Cable Diagnostic Process Fail
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_RCR register.
+//
+//*****************************************************************************
+#define EPHY_RCR_SWRST          0x00008000  // Software Reset
+#define EPHY_RCR_SWRESTART      0x00004000  // Software Restart
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_LEDCFG register.
+//
+//*****************************************************************************
+#define EPHY_LEDCFG_LED2_M      0x00000F00  // LED2 Configuration
+#define EPHY_LEDCFG_LED2_LINK   0x00000000  // Link OK
+#define EPHY_LEDCFG_LED2_RXTX   0x00000100  // RX/TX Activity
+#define EPHY_LEDCFG_LED2_TX     0x00000200  // TX Activity
+#define EPHY_LEDCFG_LED2_RX     0x00000300  // RX Activity
+#define EPHY_LEDCFG_LED2_COL    0x00000400  // Collision
+#define EPHY_LEDCFG_LED2_100BT  0x00000500  // 100-Base TX
+#define EPHY_LEDCFG_LED2_10BT   0x00000600  // 10-Base TX
+#define EPHY_LEDCFG_LED2_FD     0x00000700  // Full Duplex
+#define EPHY_LEDCFG_LED2_LINKTXRX                                             \
+                                0x00000800  // Link OK/Blink on TX/RX Activity
+#define EPHY_LEDCFG_LED1_M      0x000000F0  // LED1 Configuration
+#define EPHY_LEDCFG_LED1_LINK   0x00000000  // Link OK
+#define EPHY_LEDCFG_LED1_RXTX   0x00000010  // RX/TX Activity
+#define EPHY_LEDCFG_LED1_TX     0x00000020  // TX Activity
+#define EPHY_LEDCFG_LED1_RX     0x00000030  // RX Activity
+#define EPHY_LEDCFG_LED1_COL    0x00000040  // Collision
+#define EPHY_LEDCFG_LED1_100BT  0x00000050  // 100-Base TX
+#define EPHY_LEDCFG_LED1_10BT   0x00000060  // 10-Base TX
+#define EPHY_LEDCFG_LED1_FD     0x00000070  // Full Duplex
+#define EPHY_LEDCFG_LED1_LINKTXRX                                             \
+                                0x00000080  // Link OK/Blink on TX/RX Activity
+#define EPHY_LEDCFG_LED0_M      0x0000000F  // LED0 Configuration
+#define EPHY_LEDCFG_LED0_LINK   0x00000000  // Link OK
+#define EPHY_LEDCFG_LED0_RXTX   0x00000001  // RX/TX Activity
+#define EPHY_LEDCFG_LED0_TX     0x00000002  // TX Activity
+#define EPHY_LEDCFG_LED0_RX     0x00000003  // RX Activity
+#define EPHY_LEDCFG_LED0_COL    0x00000004  // Collision
+#define EPHY_LEDCFG_LED0_100BT  0x00000005  // 100-Base TX
+#define EPHY_LEDCFG_LED0_10BT   0x00000006  // 10-Base TX
+#define EPHY_LEDCFG_LED0_FD     0x00000007  // Full Duplex
+#define EPHY_LEDCFG_LED0_LINKTXRX                                             \
+                                0x00000008  // Link OK/Blink on TX/RX Activity
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EMAC_O_CC
+// register.
+//
+//*****************************************************************************
+#define EMAC_CC_CS_PA7          0x00000001  // GPIO
+
+#endif
+
+#endif // __HW_EMAC_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_epi.h b/bsp/tm4c129x/libraries/inc/hw_epi.h
new file mode 100644
index 0000000000..7a90282e38
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_epi.h
@@ -0,0 +1,933 @@
+//*****************************************************************************
+//
+// hw_epi.h - Macros for use in accessing the EPI registers.
+//
+// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EPI_H__
+#define __HW_EPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the External Peripheral Interface register
+// offsets.
+//
+//*****************************************************************************
+#define EPI_O_CFG               0x00000000  // EPI Configuration
+#define EPI_O_BAUD              0x00000004  // EPI Main Baud Rate
+#define EPI_O_BAUD2             0x00000008  // EPI Main Baud Rate
+#define EPI_O_HB16CFG           0x00000010  // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG             0x00000010  // EPI General-Purpose
+                                            // Configuration
+#define EPI_O_SDRAMCFG          0x00000010  // EPI SDRAM Configuration
+#define EPI_O_HB8CFG            0x00000010  // EPI Host-Bus 8 Configuration
+#define EPI_O_HB8CFG2           0x00000014  // EPI Host-Bus 8 Configuration 2
+#define EPI_O_HB16CFG2          0x00000014  // EPI Host-Bus 16 Configuration 2
+#define EPI_O_ADDRMAP           0x0000001C  // EPI Address Map
+#define EPI_O_RSIZE0            0x00000020  // EPI Read Size 0
+#define EPI_O_RADDR0            0x00000024  // EPI Read Address 0
+#define EPI_O_RPSTD0            0x00000028  // EPI Non-Blocking Read Data 0
+#define EPI_O_RSIZE1            0x00000030  // EPI Read Size 1
+#define EPI_O_RADDR1            0x00000034  // EPI Read Address 1
+#define EPI_O_RPSTD1            0x00000038  // EPI Non-Blocking Read Data 1
+#define EPI_O_STAT              0x00000060  // EPI Status
+#define EPI_O_RFIFOCNT          0x0000006C  // EPI Read FIFO Count
+#define EPI_O_READFIFO0         0x00000070  // EPI Read FIFO
+#define EPI_O_READFIFO1         0x00000074  // EPI Read FIFO Alias 1
+#define EPI_O_READFIFO2         0x00000078  // EPI Read FIFO Alias 2
+#define EPI_O_READFIFO3         0x0000007C  // EPI Read FIFO Alias 3
+#define EPI_O_READFIFO4         0x00000080  // EPI Read FIFO Alias 4
+#define EPI_O_READFIFO5         0x00000084  // EPI Read FIFO Alias 5
+#define EPI_O_READFIFO6         0x00000088  // EPI Read FIFO Alias 6
+#define EPI_O_READFIFO7         0x0000008C  // EPI Read FIFO Alias 7
+#define EPI_O_FIFOLVL           0x00000200  // EPI FIFO Level Selects
+#define EPI_O_WFIFOCNT          0x00000204  // EPI Write FIFO Count
+#define EPI_O_DMATXCNT          0x00000208  // EPI DMA Transmit Count
+#define EPI_O_IM                0x00000210  // EPI Interrupt Mask
+#define EPI_O_RIS               0x00000214  // EPI Raw Interrupt Status
+#define EPI_O_MIS               0x00000218  // EPI Masked Interrupt Status
+#define EPI_O_EISC              0x0000021C  // EPI Error and Interrupt Status
+                                            // and Clear
+#define EPI_O_HB8CFG3           0x00000308  // EPI Host-Bus 8 Configuration 3
+#define EPI_O_HB16CFG3          0x00000308  // EPI Host-Bus 16 Configuration 3
+#define EPI_O_HB16CFG4          0x0000030C  // EPI Host-Bus 16 Configuration 4
+#define EPI_O_HB8CFG4           0x0000030C  // EPI Host-Bus 8 Configuration 4
+#define EPI_O_HB8TIME           0x00000310  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME          0x00000310  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB8TIME2          0x00000314  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME2         0x00000314  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB16TIME3         0x00000318  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB8TIME3          0x00000318  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB8TIME4          0x0000031C  // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME4         0x0000031C  // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HBPSRAM           0x00000360  // EPI Host-Bus PSRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_INTDIV          0x00000100  // Integer Clock Divider Enable
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
+#define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
+#define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
+#define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD2 register.
+//
+//*****************************************************************************
+#define EPI_BAUD2_COUNT1_M      0xFFFF0000  // CS3n Baud Rate Counter 1
+#define EPI_BAUD2_COUNT0_M      0x0000FFFF  // CS2n Baud Rate Counter 0
+#define EPI_BAUD2_COUNT1_S      16
+#define EPI_BAUD2_COUNT0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_CLKGATE     0x80000000  // Clock Gated
+#define EPI_HB16CFG_CLKGATEI    0x40000000  // Clock Gated Idle
+#define EPI_HB16CFG_CLKINV      0x20000000  // Invert Output Clock Enable
+#define EPI_HB16CFG_RDYEN       0x10000000  // Input Ready Enable
+#define EPI_HB16CFG_IRDYINV     0x08000000  // Input Ready Invert
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_ALEHIGH     0x00080000  // ALE Strobe Polarity
+#define EPI_HB16CFG_WRCRE       0x00040000  // PSRAM Configuration Register
+                                            // Write
+#define EPI_HB16CFG_RDCRE       0x00020000  // PSRAM Configuration Register
+                                            // Read
+#define EPI_HB16CFG_BURST       0x00010000  // Burst Mode
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // Write Wait States
+#define EPI_HB16CFG_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG_RDWS_M      0x00000030  // Read Wait States
+#define EPI_HB16CFG_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S      22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // EPI Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_CLKGATE      0x80000000  // Clock Gated
+#define EPI_HB8CFG_CLKGATEI     0x40000000  // Clock Gated when Idle
+#define EPI_HB8CFG_CLKINV       0x20000000  // Invert Output Clock Enable
+#define EPI_HB8CFG_RDYEN        0x10000000  // Input Ready Enable
+#define EPI_HB8CFG_IRDYINV      0x08000000  // Input Ready Invert
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // READ Strobe Polarity
+#define EPI_HB8CFG_ALEHIGH      0x00080000  // ALE Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
+#define EPI_HB8CFG_WRWS_2       0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG_WRWS_4       0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG_WRWS_6       0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG_WRWS_8       0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
+#define EPI_HB8CFG_RDWS_2       0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG_RDWS_4       0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG_RDWS_6       0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG_RDWS_8       0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S    8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_CSCFGEXT    0x08000000  // Chip Select Extended
+                                            // Configuration
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate and
+                                            // Multiple Sub-Mode Configuration
+                                            // enable
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH      0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH      0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_ALEHIGH     0x00080000  // CS1n ALE Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M      0x000000C0  // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG2_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG2_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG2_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG2_RDWS_M      0x00000030  // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG2_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG2_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG2_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG2_MODE_M      0x00000003  // CS1n Host Bus Sub-Mode
+#define EPI_HB8CFG2_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG2_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_CSCFGEXT   0x08000000  // Chip Select Extended
+                                            // Configuration
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate and
+                                            // Multiple Sub-Mode Configuration
+                                            // enable
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH     0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH     0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_ALEHIGH    0x00080000  // CS1n ALE Strobe Polarity
+#define EPI_HB16CFG2_WRCRE      0x00040000  // CS1n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG2_RDCRE      0x00020000  // CS1n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG2_BURST      0x00010000  // CS1n Burst Mode
+#define EPI_HB16CFG2_WRWS_M     0x000000C0  // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG2_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG2_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG2_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG2_RDWS_M     0x00000030  // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG2_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG2_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG2_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG2_MODE_M     0x00000003  // CS1n Host Bus Sub-Mode
+#define EPI_HB16CFG2_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG2_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_ECSZ_M      0x00000C00  // External Code Size
+#define EPI_ADDRMAP_ECSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ECSZ_64KB   0x00000400  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ECSZ_16MB   0x00000800  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ECSZ_256MB  0x00000C00  // 256MB; lower address range:
+                                            // 0x000.0000 to 0x0FFF.FFFF
+#define EPI_ADDRMAP_ECADR_M     0x00000300  // External Code Address
+#define EPI_ADDRMAP_ECADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ECADR_1000  0x00000100  // At 0x1000.0000
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
+#define EPI_ADDRMAP_EPADR_HBQS  0x00000030  // Only to be used with Host Bus
+                                            // quad chip select. In quad chip
+                                            // select mode, CS2n maps to
+                                            // 0xA000.0000 and CS3n maps to
+                                            // 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
+#define EPI_ADDRMAP_ERADR_HBQS  0x00000003  // Only to be used with Host Bus
+                                            // quad chip select. In quad chip
+                                            // select mode, CS0n maps to
+                                            // 0x6000.0000 and CS1n maps to
+                                            // 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M       0xFFFFFFFF  // Current Address
+#define EPI_RADDR0_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD0_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M       0xFFFFFFFF  // Current Address
+#define EPI_RADDR1_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD1_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M    0x0000000F  // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO0
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO0_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO0_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO4_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO5_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO6_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO7_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Interrupt is triggered while
+                                            // WRFIFO is empty.
+#define EPI_FIFOLVL_WRFIFO_2    0x00000020  // Interrupt is triggered until
+                                            // there are only two slots
+                                            // available. Thus, trigger is
+                                            // deasserted when there are two
+                                            // WRFIFO entries present. This
+                                            // configuration is optimized for
+                                            // bursts of 2
+#define EPI_FIFOLVL_WRFIFO_1    0x00000030  // Interrupt is triggered until
+                                            // there is one WRFIFO entry
+                                            // available. This configuration
+                                            // expects only single writes
+#define EPI_FIFOLVL_WRFIFO_NFULL                                              \
+                                0x00000040  // Trigger interrupt when WRFIFO is
+                                            // not full, meaning trigger will
+                                            // continue to assert until there
+                                            // are four entries in the WRFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000  // Empty
+#define EPI_FIFOLVL_RDFIFO_1    0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_2    0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_4    0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_6    0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7    0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_8    0x00000006  // Trigger when there are 8 entries
+                                            // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_DMATXCNT register.
+//
+//*****************************************************************************
+#define EPI_DMATXCNT_TXCNT_M    0x0000FFFF  // DMA Count
+#define EPI_DMATXCNT_TXCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_DMAWRIM          0x00000010  // Write uDMA Interrupt Mask
+#define EPI_IM_DMARDIM          0x00000008  // Read uDMA Interrupt Mask
+#define EPI_IM_WRIM             0x00000004  // Write FIFO Empty Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read FIFO Full Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_DMAWRRIS        0x00000010  // Write uDMA Raw Interrupt Status
+#define EPI_RIS_DMARDRIS        0x00000008  // Read uDMA Raw Interrupt Status
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_DMAWRMIS        0x00000010  // Write uDMA Masked Interrupt
+                                            // Status
+#define EPI_MIS_DMARDMIS        0x00000008  // Read uDMA Masked Interrupt
+                                            // Status
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_DMAWRIC        0x00000010  // Write uDMA Interrupt Clear
+#define EPI_EISC_DMARDIC        0x00000008  // Read uDMA Interrupt Clear
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG3_WRHIGH      0x00200000  // CS2n WRITE Strobe Polarity
+#define EPI_HB8CFG3_RDHIGH      0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB8CFG3_ALEHIGH     0x00080000  // CS2n ALE Strobe Polarity
+#define EPI_HB8CFG3_WRWS_M      0x000000C0  // CS2n Write Wait States
+#define EPI_HB8CFG3_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG3_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG3_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG3_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG3_RDWS_M      0x00000030  // CS2n Read Wait States
+#define EPI_HB8CFG3_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG3_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG3_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG3_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG3_MODE_M      0x00000003  // CS2n Host Bus Sub-Mode
+#define EPI_HB8CFG3_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG3_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG3_WRHIGH     0x00200000  // CS2n WRITE Strobe Polarity
+#define EPI_HB16CFG3_RDHIGH     0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB16CFG3_ALEHIGH    0x00080000  // CS2n ALE Strobe Polarity
+#define EPI_HB16CFG3_WRCRE      0x00040000  // CS2n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG3_RDCRE      0x00020000  // CS2n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG3_BURST      0x00010000  // CS2n Burst Mode
+#define EPI_HB16CFG3_WRWS_M     0x000000C0  // CS2n Write Wait States
+#define EPI_HB16CFG3_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG3_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG3_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG3_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG3_RDWS_M     0x00000030  // CS2n Read Wait States
+#define EPI_HB16CFG3_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG3_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG3_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG3_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG3_MODE_M     0x00000003  // CS2n Host Bus Sub-Mode
+#define EPI_HB16CFG3_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG3_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG4_WRHIGH     0x00200000  // CS3n WRITE Strobe Polarity
+#define EPI_HB16CFG4_RDHIGH     0x00100000  // CS3n READ Strobe Polarity
+#define EPI_HB16CFG4_ALEHIGH    0x00080000  // CS3n ALE Strobe Polarity
+#define EPI_HB16CFG4_WRCRE      0x00040000  // CS3n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG4_RDCRE      0x00020000  // CS3n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG4_BURST      0x00010000  // CS3n Burst Mode
+#define EPI_HB16CFG4_WRWS_M     0x000000C0  // CS3n Write Wait States
+#define EPI_HB16CFG4_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG4_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG4_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG4_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG4_RDWS_M     0x00000030  // CS3n Read Wait States
+#define EPI_HB16CFG4_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG4_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG4_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG4_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG4_MODE_M     0x00000003  // CS3n Host Bus Sub-Mode
+#define EPI_HB16CFG4_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG4_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG4_WRHIGH      0x00200000  // CS3n WRITE Strobe Polarity
+#define EPI_HB8CFG4_RDHIGH      0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB8CFG4_ALEHIGH     0x00080000  // CS3n ALE Strobe Polarity
+#define EPI_HB8CFG4_WRWS_M      0x000000C0  // CS3n Write Wait States
+#define EPI_HB8CFG4_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG4_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG4_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG4_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG4_RDWS_M      0x00000030  // CS3n Read Wait States
+#define EPI_HB8CFG4_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG4_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG4_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG4_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG4_MODE_M      0x00000003  // CS3n Host Bus Sub-Mode
+#define EPI_HB8CFG4_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG4_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME_IRDYDLY_M   0x03000000  // CS0n Input Ready Delay
+#define EPI_HB8TIME_CAPWIDTH_M  0x00003000  // CS0n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME_WRWSM       0x00000010  // Write Wait State Minus One
+#define EPI_HB8TIME_RDWSM       0x00000001  // Read Wait State Minus One
+#define EPI_HB8TIME_IRDYDLY_S   24
+#define EPI_HB8TIME_CAPWIDTH_S  12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME_IRDYDLY_M  0x03000000  // CS0n Input Ready Delay
+#define EPI_HB16TIME_PSRAMSZ_M  0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME_PSRAMSZ_0  0x00000000  // No row size limitation
+#define EPI_HB16TIME_PSRAMSZ_128B                                             \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME_PSRAMSZ_256B                                             \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME_PSRAMSZ_512B                                             \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME_PSRAMSZ_1KB                                              \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME_PSRAMSZ_2KB                                              \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME_PSRAMSZ_4KB                                              \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME_PSRAMSZ_8KB                                              \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME_CAPWIDTH_M 0x00003000  // CS0n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME_WRWSM      0x00000010  // Write Wait State Minus One
+#define EPI_HB16TIME_RDWSM      0x00000001  // Read Wait State Minus One
+#define EPI_HB16TIME_IRDYDLY_S  24
+#define EPI_HB16TIME_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME2 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME2_IRDYDLY_M  0x03000000  // CS1n Input Ready Delay
+#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000  // CS1n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME2_WRWSM      0x00000010  // CS1n Write Wait State Minus One
+#define EPI_HB8TIME2_RDWSM      0x00000001  // CS1n Read Wait State Minus One
+#define EPI_HB8TIME2_IRDYDLY_S  24
+#define EPI_HB8TIME2_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME2
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME2_IRDYDLY_M 0x03000000  // CS1n Input Ready Delay
+#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME2_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME2_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME2_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME2_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME2_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME2_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME2_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME2_CAPWIDTH_M                                              \
+                                0x00003000  // CS1n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME2_WRWSM     0x00000010  // CS1n Write Wait State Minus One
+#define EPI_HB16TIME2_RDWSM     0x00000001  // CS1n Read Wait State Minus One
+#define EPI_HB16TIME2_IRDYDLY_S 24
+#define EPI_HB16TIME2_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME3
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME3_IRDYDLY_M 0x03000000  // CS2n Input Ready Delay
+#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME3_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME3_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME3_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME3_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME3_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME3_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME3_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME3_CAPWIDTH_M                                              \
+                                0x00003000  // CS2n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME3_WRWSM     0x00000010  // CS2n Write Wait State Minus One
+#define EPI_HB16TIME3_RDWSM     0x00000001  // CS2n Read Wait State Minus One
+#define EPI_HB16TIME3_IRDYDLY_S 24
+#define EPI_HB16TIME3_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME3 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME3_IRDYDLY_M  0x03000000  // CS2n Input Ready Delay
+#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000  // CS2n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME3_WRWSM      0x00000010  // CS2n Write Wait State Minus One
+#define EPI_HB8TIME3_RDWSM      0x00000001  // CS2n Read Wait State Minus One
+#define EPI_HB8TIME3_IRDYDLY_S  24
+#define EPI_HB8TIME3_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME4 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME4_IRDYDLY_M  0x03000000  // CS3n Input Ready Delay
+#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000  // CS3n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME4_WRWSM      0x00000010  // CS3n Write Wait State Minus One
+#define EPI_HB8TIME4_RDWSM      0x00000001  // CS3n Read Wait State Minus One
+#define EPI_HB8TIME4_IRDYDLY_S  24
+#define EPI_HB8TIME4_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME4
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME4_IRDYDLY_M 0x03000000  // CS3n Input Ready Delay
+#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME4_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME4_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME4_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME4_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME4_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME4_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME4_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME4_CAPWIDTH_M                                              \
+                                0x00003000  // CS3n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME4_WRWSM     0x00000010  // CS3n Write Wait State Minus One
+#define EPI_HB16TIME4_RDWSM     0x00000001  // CS3n Read Wait State Minus One
+#define EPI_HB16TIME4_IRDYDLY_S 24
+#define EPI_HB16TIME4_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HBPSRAM register.
+//
+//*****************************************************************************
+#define EPI_HBPSRAM_CR_M        0x001FFFFF  // PSRAM Config Register
+#define EPI_HBPSRAM_CR_S        0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL
+// register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // Trigger when there are up to 3
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // Trigger when there are up to 2
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // Trigger when there is 1 space
+                                            // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006  // Trigger when there are 8 entries
+                                            // in the NBRFIFO
+
+#endif
+
+#endif // __HW_EPI_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_fan.h b/bsp/tm4c129x/libraries/inc/hw_fan.h
new file mode 100644
index 0000000000..1332996170
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_fan.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_fan.h - Macros used when accessing the fan control hardware.
+//
+// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FAN_H__
+#define __HW_FAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Fan Control register offsets.
+//
+//*****************************************************************************
+
+#endif // __HW_FAN_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_flash.h b/bsp/tm4c129x/libraries/inc/hw_flash.h
new file mode 100644
index 0000000000..971d4e0c27
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_flash.h
@@ -0,0 +1,625 @@
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA               0x400FD000  // Flash Memory Address
+#define FLASH_FMD               0x400FD004  // Flash Memory Data
+#define FLASH_FMC               0x400FD008  // Flash Memory Control
+#define FLASH_FCRIS             0x400FD00C  // Flash Controller Raw Interrupt
+                                            // Status
+#define FLASH_FCIM              0x400FD010  // Flash Controller Interrupt Mask
+#define FLASH_FCMISC            0x400FD014  // Flash Controller Masked
+                                            // Interrupt Status and Clear
+#define FLASH_FMC2              0x400FD020  // Flash Memory Control 2
+#define FLASH_FWBVAL            0x400FD030  // Flash Write Buffer Valid
+#define FLASH_FLPEKEY           0x400FD03C  // Flash Program/Erase Key
+#define FLASH_FWBN              0x400FD100  // Flash Write Buffer n
+#define FLASH_PP                0x400FDFC0  // Flash Peripheral Properties
+#define FLASH_FSIZE             0x400FDFC0  // Flash Size
+#define FLASH_SSIZE             0x400FDFC4  // SRAM Size
+#define FLASH_CONF              0x400FDFC8  // Flash Configuration Register
+#define FLASH_ROMSWMAP          0x400FDFCC  // ROM Software Map
+#define FLASH_DMASZ             0x400FDFD0  // Flash DMA Address Size
+#define FLASH_DMAST             0x400FDFD4  // Flash DMA Starting Address
+#define FLASH_RVP               0x400FE0D4  // Reset Vector Pointer
+#define FLASH_RMCTL             0x400FE0F0  // ROM Control
+#define FLASH_BOOTCFG           0x400FE1D0  // Boot Configuration
+#define FLASH_USERREG0          0x400FE1E0  // User Register 0
+#define FLASH_USERREG1          0x400FE1E4  // User Register 1
+#define FLASH_USERREG2          0x400FE1E8  // User Register 2
+#define FLASH_USERREG3          0x400FE1EC  // User Register 3
+#define FLASH_FMPRE0            0x400FE200  // Flash Memory Protection Read
+                                            // Enable 0
+#define FLASH_FMPRE1            0x400FE204  // Flash Memory Protection Read
+                                            // Enable 1
+#define FLASH_FMPRE2            0x400FE208  // Flash Memory Protection Read
+                                            // Enable 2
+#define FLASH_FMPRE3            0x400FE20C  // Flash Memory Protection Read
+                                            // Enable 3
+#define FLASH_FMPRE4            0x400FE210  // Flash Memory Protection Read
+                                            // Enable 4
+#define FLASH_FMPRE5            0x400FE214  // Flash Memory Protection Read
+                                            // Enable 5
+#define FLASH_FMPRE6            0x400FE218  // Flash Memory Protection Read
+                                            // Enable 6
+#define FLASH_FMPRE7            0x400FE21C  // Flash Memory Protection Read
+                                            // Enable 7
+#define FLASH_FMPRE8            0x400FE220  // Flash Memory Protection Read
+                                            // Enable 8
+#define FLASH_FMPRE9            0x400FE224  // Flash Memory Protection Read
+                                            // Enable 9
+#define FLASH_FMPRE10           0x400FE228  // Flash Memory Protection Read
+                                            // Enable 10
+#define FLASH_FMPRE11           0x400FE22C  // Flash Memory Protection Read
+                                            // Enable 11
+#define FLASH_FMPRE12           0x400FE230  // Flash Memory Protection Read
+                                            // Enable 12
+#define FLASH_FMPRE13           0x400FE234  // Flash Memory Protection Read
+                                            // Enable 13
+#define FLASH_FMPRE14           0x400FE238  // Flash Memory Protection Read
+                                            // Enable 14
+#define FLASH_FMPRE15           0x400FE23C  // Flash Memory Protection Read
+                                            // Enable 15
+#define FLASH_FMPPE0            0x400FE400  // Flash Memory Protection Program
+                                            // Enable 0
+#define FLASH_FMPPE1            0x400FE404  // Flash Memory Protection Program
+                                            // Enable 1
+#define FLASH_FMPPE2            0x400FE408  // Flash Memory Protection Program
+                                            // Enable 2
+#define FLASH_FMPPE3            0x400FE40C  // Flash Memory Protection Program
+                                            // Enable 3
+#define FLASH_FMPPE4            0x400FE410  // Flash Memory Protection Program
+                                            // Enable 4
+#define FLASH_FMPPE5            0x400FE414  // Flash Memory Protection Program
+                                            // Enable 5
+#define FLASH_FMPPE6            0x400FE418  // Flash Memory Protection Program
+                                            // Enable 6
+#define FLASH_FMPPE7            0x400FE41C  // Flash Memory Protection Program
+                                            // Enable 7
+#define FLASH_FMPPE8            0x400FE420  // Flash Memory Protection Program
+                                            // Enable 8
+#define FLASH_FMPPE9            0x400FE424  // Flash Memory Protection Program
+                                            // Enable 9
+#define FLASH_FMPPE10           0x400FE428  // Flash Memory Protection Program
+                                            // Enable 10
+#define FLASH_FMPPE11           0x400FE42C  // Flash Memory Protection Program
+                                            // Enable 11
+#define FLASH_FMPPE12           0x400FE430  // Flash Memory Protection Program
+                                            // Enable 12
+#define FLASH_FMPPE13           0x400FE434  // Flash Memory Protection Program
+                                            // Enable 13
+#define FLASH_FMPPE14           0x400FE438  // Flash Memory Protection Program
+                                            // Enable 14
+#define FLASH_FMPPE15           0x400FE43C  // Flash Memory Protection Program
+                                            // Enable 15
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x000FFFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS     0x00002000  // Program Verify Error Raw
+                                            // Interrupt Status
+#define FLASH_FCRIS_ERRIS       0x00000800  // Erase Verify Error Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_INVDRIS     0x00000400  // Invalid Data Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_VOLTRIS     0x00000200  // Pump Voltage Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_ERIS        0x00000004  // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK     0x00002000  // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK       0x00000800  // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK     0x00000400  // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK     0x00000200  // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK        0x00000004  // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC   0x00002000  // PROGVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_ERMISC     0x00000800  // ERVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_INVDMISC   0x00000400  // Invalid Data Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_VOLTMISC   0x00000200  // VOLT Masked Interrupt Status and
+                                            // Clear
+#define FLASH_FCMISC_EMISC      0x00000004  // EEPROM Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FLPEKEY register.
+//
+//*****************************************************************************
+#define FLASH_FLPEKEY_PEKEY_M   0x0000FFFF  // Key Value
+#define FLASH_FLPEKEY_PEKEY_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_PP register.
+//
+//*****************************************************************************
+#define FLASH_PP_PFC            0x40000000  // Prefetch Buffer Mode
+#define FLASH_PP_FMM            0x20000000  // Flash Mirror Mode
+#define FLASH_PP_DFA            0x10000000  // DMA Flash Access
+#define FLASH_PP_EESS_M         0x00780000  // EEPROM Sector Size of the
+                                            // physical bank
+#define FLASH_PP_EESS_1KB       0x00000000  // 1 KB
+#define FLASH_PP_EESS_2KB       0x00080000  // 2 KB
+#define FLASH_PP_EESS_4KB       0x00100000  // 4 KB
+#define FLASH_PP_EESS_8KB       0x00180000  // 8 KB
+#define FLASH_PP_MAINSS_M       0x00070000  // Flash Sector Size of the
+                                            // physical bank
+#define FLASH_PP_MAINSS_1KB     0x00000000  // 1 KB
+#define FLASH_PP_MAINSS_2KB     0x00010000  // 2 KB
+#define FLASH_PP_MAINSS_4KB     0x00020000  // 4 KB
+#define FLASH_PP_MAINSS_8KB     0x00030000  // 8 KB
+#define FLASH_PP_MAINSS_16KB    0x00040000  // 16 KB
+#define FLASH_PP_SIZE_M         0x0000FFFF  // Flash Size
+#define FLASH_PP_SIZE_512KB     0x000000FF  // 512 KB of Flash
+#define FLASH_PP_SIZE_1MB       0x000001FF  // 1024 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M      0x0000FFFF  // Flash Size
+#define FLASH_FSIZE_SIZE_32KB   0x0000000F  // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB   0x0000001F  // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB  0x0000003F  // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB  0x0000007F  // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M      0x0000FFFF  // SRAM Size
+#define FLASH_SSIZE_SIZE_12KB   0x0000002F  // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB   0x0000005F  // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB   0x0000007F  // 32 KB of SRAM
+#define FLASH_SSIZE_SIZE_256KB  0x000003FF  // 256 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CONF register.
+//
+//*****************************************************************************
+#define FLASH_CONF_FMME         0x40000000  // Flash Mirror Mode Enable
+#define FLASH_CONF_SPFE         0x20000000  // Single Prefetch Mode Enable
+#define FLASH_CONF_CLRTV        0x00100000  // Clear Valid Tags
+#define FLASH_CONF_FPFON        0x00020000  // Force Prefetch On
+#define FLASH_CONF_FPFOFF       0x00010000  // Force Prefetch Off
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001  // SafeRTOS Present
+#define FLASH_ROMSWMAP_SW0EN_M  0x00000003  // ROM SW Region 0 Availability
+#define FLASH_ROMSWMAP_SW0EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW0EN_CORE                                             \
+                                0x00000001  // Region available to core
+#define FLASH_ROMSWMAP_SW1EN_M  0x0000000C  // ROM SW Region 1 Availability
+#define FLASH_ROMSWMAP_SW1EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW1EN_CORE                                             \
+                                0x00000004  // Region available to core
+#define FLASH_ROMSWMAP_SW2EN_M  0x00000030  // ROM SW Region 2 Availability
+#define FLASH_ROMSWMAP_SW2EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW2EN_CORE                                             \
+                                0x00000010  // Region available to core
+#define FLASH_ROMSWMAP_SW3EN_M  0x000000C0  // ROM SW Region 3 Availability
+#define FLASH_ROMSWMAP_SW3EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW3EN_CORE                                             \
+                                0x00000040  // Region available to core
+#define FLASH_ROMSWMAP_SW4EN_M  0x00000300  // ROM SW Region 4 Availability
+#define FLASH_ROMSWMAP_SW4EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW4EN_CORE                                             \
+                                0x00000100  // Region available to core
+#define FLASH_ROMSWMAP_SW5EN_M  0x00000C00  // ROM SW Region 5 Availability
+#define FLASH_ROMSWMAP_SW5EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW5EN_CORE                                             \
+                                0x00000400  // Region available to core
+#define FLASH_ROMSWMAP_SW6EN_M  0x00003000  // ROM SW Region 6 Availability
+#define FLASH_ROMSWMAP_SW6EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW6EN_CORE                                             \
+                                0x00001000  // Region available to core
+#define FLASH_ROMSWMAP_SW7EN_M  0x0000C000  // ROM SW Region 7 Availability
+#define FLASH_ROMSWMAP_SW7EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW7EN_CORE                                             \
+                                0x00004000  // Region available to core
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMASZ register.
+//
+//*****************************************************************************
+#define FLASH_DMASZ_SIZE_M      0x0003FFFF  // uDMA-accessible Memory Size
+#define FLASH_DMASZ_SIZE_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMAST register.
+//
+//*****************************************************************************
+#define FLASH_DMAST_ADDR_M      0x1FFFF800  // Contains the starting address of
+                                            // the flash region accessible by
+                                            // uDMA if the FLASHPP register DFA
+                                            // bit is set
+#define FLASH_DMAST_ADDR_S      11
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RVP register.
+//
+//*****************************************************************************
+#define FLASH_RVP_RV_M          0xFFFFFFFF  // Reset Vector Pointer Address
+#define FLASH_RVP_RV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY       0x00000010  // KEY Select
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG3_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE8_READ_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE8_READ_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE9_READ_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE9_READ_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE10_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE10_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE11_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE11_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE12_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE12_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE13_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE13_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE14_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE14_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE15_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE15_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE8_PROG_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE8_PROG_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE9_PROG_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE9_PROG_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE10_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE10_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE11_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE11_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE12_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE12_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE13_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE13_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE14_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE14_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE15_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE15_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE      0x00000800
+#define FLASH_ERASE_SIZE        0x00000400
+
+#endif // __HW_FLASH_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_gpio.h b/bsp/tm4c129x/libraries/inc/hw_gpio.h
new file mode 100644
index 0000000000..471ddd90c9
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_gpio.h
@@ -0,0 +1,213 @@
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA             0x00000000  // GPIO Data
+#define GPIO_O_DIR              0x00000400  // GPIO Direction
+#define GPIO_O_IS               0x00000404  // GPIO Interrupt Sense
+#define GPIO_O_IBE              0x00000408  // GPIO Interrupt Both Edges
+#define GPIO_O_IEV              0x0000040C  // GPIO Interrupt Event
+#define GPIO_O_IM               0x00000410  // GPIO Interrupt Mask
+#define GPIO_O_RIS              0x00000414  // GPIO Raw Interrupt Status
+#define GPIO_O_MIS              0x00000418  // GPIO Masked Interrupt Status
+#define GPIO_O_ICR              0x0000041C  // GPIO Interrupt Clear
+#define GPIO_O_AFSEL            0x00000420  // GPIO Alternate Function Select
+#define GPIO_O_DR2R             0x00000500  // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R             0x00000504  // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R             0x00000508  // GPIO 8-mA Drive Select
+#define GPIO_O_ODR              0x0000050C  // GPIO Open Drain Select
+#define GPIO_O_PUR              0x00000510  // GPIO Pull-Up Select
+#define GPIO_O_PDR              0x00000514  // GPIO Pull-Down Select
+#define GPIO_O_SLR              0x00000518  // GPIO Slew Rate Control Select
+#define GPIO_O_DEN              0x0000051C  // GPIO Digital Enable
+#define GPIO_O_LOCK             0x00000520  // GPIO Lock
+#define GPIO_O_CR               0x00000524  // GPIO Commit
+#define GPIO_O_AMSEL            0x00000528  // GPIO Analog Mode Select
+#define GPIO_O_PCTL             0x0000052C  // GPIO Port Control
+#define GPIO_O_ADCCTL           0x00000530  // GPIO ADC Control
+#define GPIO_O_DMACTL           0x00000534  // GPIO DMA Control
+#define GPIO_O_SI               0x00000538  // GPIO Select Interrupt
+#define GPIO_O_DR12R            0x0000053C  // GPIO 12-mA Drive Select
+#define GPIO_O_WAKEPEN          0x00000540  // GPIO Wake Pin Enable
+#define GPIO_O_WAKELVL          0x00000544  // GPIO Wake Level
+#define GPIO_O_WAKESTAT         0x00000548  // GPIO Wake Status
+#define GPIO_O_PP               0x00000FC0  // GPIO Peripheral Property
+#define GPIO_O_PC               0x00000FC4  // GPIO Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_DMAIME          0x00000100  // GPIO uDMA Done Interrupt Mask
+                                            // Enable
+#define GPIO_IM_GPIO_M          0x000000FF  // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_DMARIS         0x00000100  // GPIO uDMA Done Interrupt Raw
+                                            // Status
+#define GPIO_RIS_GPIO_M         0x000000FF  // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_DMAMIS         0x00000100  // GPIO uDMA Done Masked Interrupt
+                                            // Status
+#define GPIO_MIS_GPIO_M         0x000000FF  // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_DMAIC          0x00000100  // GPIO uDMA Interrupt Clear
+#define GPIO_ICR_GPIO_M         0x000000FF  // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
+#define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM             0x00000001  // Summary Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_DR12R register.
+//
+//*****************************************************************************
+#define GPIO_DR12R_DRV12_M      0x000000FF  // Output Pad 12-mA Drive Enable
+#define GPIO_DR12R_DRV12_12MA   0x00000001  // The corresponding GPIO pin has
+                                            // 12-mA drive. This encoding is
+                                            // only valid if the GPIOPP EDE bit
+                                            // is set and the appropriate
+                                            // GPIOPC EDM bit field is
+                                            // programmed to 0x3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
+//
+//*****************************************************************************
+#define GPIO_WAKEPEN_WAKEP4     0x00000010  // P[4] Wake Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
+//
+//*****************************************************************************
+#define GPIO_WAKELVL_WAKELVL4   0x00000010  // P[4] Wake Level
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKESTAT
+// register.
+//
+//*****************************************************************************
+#define GPIO_WAKESTAT_STAT4     0x00000010  // P[4] Wake Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_PP register.
+//
+//*****************************************************************************
+#define GPIO_PP_EDE             0x00000001  // Extended Drive Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_PC register.
+//
+//*****************************************************************************
+#define GPIO_PC_EDM7_M          0x0000C000  // Extended Drive Mode Bit 7
+#define GPIO_PC_EDM6_M          0x00003000  // Extended Drive Mode Bit 6
+#define GPIO_PC_EDM5_M          0x00000C00  // Extended Drive Mode Bit 5
+#define GPIO_PC_EDM4_M          0x00000300  // Extended Drive Mode Bit 4
+#define GPIO_PC_EDM3_M          0x000000C0  // Extended Drive Mode Bit 3
+#define GPIO_PC_EDM2_M          0x00000030  // Extended Drive Mode Bit 2
+#define GPIO_PC_EDM1_M          0x0000000C  // Extended Drive Mode Bit 1
+#define GPIO_PC_EDM0_M          0x00000003  // Extended Drive Mode Bit 0
+#define GPIO_PC_EDM0_DISABLE    0x00000000  // Drive values of 2, 4 and 8 mA
+                                            // are maintained. GPIO n Drive
+                                            // Select (GPIODRnR) registers
+                                            // function as normal
+#define GPIO_PC_EDM0_6MA        0x00000001  // An additional 6 mA option is
+                                            // provided
+#define GPIO_PC_EDM0_PLUS2MA    0x00000003  // A 2 mA driver is always enabled;
+                                            // setting the corresponding
+                                            // GPIODR4R register bit adds 2 mA
+                                            // and setting the corresponding
+                                            // GPIODR8R of GPIODR12R register
+                                            // bit adds an additional 4 mA
+#define GPIO_PC_EDM7_S          14
+#define GPIO_PC_EDM6_S          12
+#define GPIO_PC_EDM5_S          10
+#define GPIO_PC_EDM4_S          8
+#define GPIO_PC_EDM3_S          6
+#define GPIO_PC_EDM2_S          4
+#define GPIO_PC_EDM1_S          2
+
+#endif // __HW_GPIO_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_hibernate.h b/bsp/tm4c129x/libraries/inc/hw_hibernate.h
new file mode 100644
index 0000000000..e5d36d887b
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_hibernate.h
@@ -0,0 +1,483 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC                0x400FC000  // Hibernation RTC Counter
+#define HIB_RTCM0               0x400FC004  // Hibernation RTC Match 0
+#define HIB_RTCLD               0x400FC00C  // Hibernation RTC Load
+#define HIB_CTL                 0x400FC010  // Hibernation Control
+#define HIB_IM                  0x400FC014  // Hibernation Interrupt Mask
+#define HIB_RIS                 0x400FC018  // Hibernation Raw Interrupt Status
+#define HIB_MIS                 0x400FC01C  // Hibernation Masked Interrupt
+                                            // Status
+#define HIB_IC                  0x400FC020  // Hibernation Interrupt Clear
+#define HIB_RTCT                0x400FC024  // Hibernation RTC Trim
+#define HIB_RTCSS               0x400FC028  // Hibernation RTC Sub Seconds
+#define HIB_IO                  0x400FC02C  // Hibernation IO Configuration
+#define HIB_DATA                0x400FC030  // Hibernation Data
+#define HIB_CALCTL              0x400FC300  // Hibernation Calendar Control
+#define HIB_CAL0                0x400FC310  // Hibernation Calendar 0
+#define HIB_CAL1                0x400FC314  // Hibernation Calendar 1
+#define HIB_CALLD0              0x400FC320  // Hibernation Calendar Load 0
+#define HIB_CALLD1              0x400FC324  // Hibernation Calendar Load
+#define HIB_CALM0               0x400FC330  // Hibernation Calendar Match 0
+#define HIB_CALM1               0x400FC334  // Hibernation Calendar Match 1
+#define HIB_LOCK                0x400FC360  // Hibernation Lock
+#define HIB_TPCTL               0x400FC400  // HIB Tamper Control
+#define HIB_TPSTAT              0x400FC404  // HIB Tamper Status
+#define HIB_TPIO                0x400FC410  // HIB Tamper I/O Control
+#define HIB_TPLOG0              0x400FC4E0  // HIB Tamper Log 0
+#define HIB_TPLOG1              0x400FC4E4  // HIB Tamper Log 1
+#define HIB_TPLOG2              0x400FC4E8  // HIB Tamper Log 2
+#define HIB_TPLOG3              0x400FC4EC  // HIB Tamper Log 3
+#define HIB_TPLOG4              0x400FC4F0  // HIB Tamper Log 4
+#define HIB_TPLOG5              0x400FC4F4  // HIB Tamper Log 5
+#define HIB_TPLOG6              0x400FC4F8  // HIB Tamper Log 6
+#define HIB_TPLOG7              0x400FC4FC  // HIB Tamper Log 7
+#define HIB_PP                  0x400FCFC0  // Hibernation Peripheral
+                                            // Properties
+#define HIB_CC                  0x400FCFC8  // Hibernation Clock Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
+#define HIB_RTCC_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
+#define HIB_RTCM0_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
+#define HIB_RTCLD_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable
+#define HIB_CTL_RETCLR          0x40000000  // GPIO Retention/Clear
+#define HIB_CTL_OSCSEL          0x00080000  // Oscillator Select
+#define HIB_CTL_OSCDRV          0x00020000  // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP          0x00010000  // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M       0x00006000  // Select for Low-Battery
+                                            // Comparator
+#define HIB_CTL_VBATSEL_1_9V    0x00000000  // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V    0x00002000  // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V    0x00004000  // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V    0x00006000  // 2.5 Volts
+#define HIB_CTL_BATCHK          0x00000400  // Check Battery Status
+#define HIB_CTL_BATWKEN         0x00000200  // Wake on Low Battery
+#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_PINWEN          0x00000010  // External Wake Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_VDDFAIL          0x00000080  // VDD Fail Interrupt Mask
+#define HIB_IM_RSTWK            0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Mask
+#define HIB_IM_PADIOWK          0x00000020  // Pad I/O Wake-Up Interrupt Mask
+#define HIB_IM_WC               0x00000010  // External Write Complete/Capable
+                                            // Interrupt Mask
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_VDDFAIL         0x00000080  // VDD Fail Raw Interrupt Status
+#define HIB_RIS_RSTWK           0x00000040  // Reset Pad I/O Wake-Up Raw
+                                            // Interrupt Status
+#define HIB_RIS_PADIOWK         0x00000020  // Pad I/O Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_WC              0x00000010  // Write Complete/Capable Raw
+                                            // Interrupt Status
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_VDDFAIL         0x00000080  // VDD Fail Interrupt Mask
+#define HIB_MIS_RSTWK           0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Mask
+#define HIB_MIS_PADIOWK         0x00000020  // Pad I/O Wake-Up Interrupt Mask
+#define HIB_MIS_WC              0x00000010  // Write Complete/Capable Masked
+                                            // Interrupt Status
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_VDDFAIL          0x00000080  // VDD Fail Interrupt Clear
+#define HIB_IC_RSTWK            0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Clear
+#define HIB_IC_PADIOWK          0x00000020  // Pad I/O Wake-Up Interrupt Clear
+#define HIB_IC_WC               0x00000010  // Write Complete/Capable Interrupt
+                                            // Clear
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
+#define HIB_RTCT_TRIM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M      0x7FFF0000  // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M      0x00007FFF  // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S      16
+#define HIB_RTCSS_RTCSSC_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IO register.
+//
+//*****************************************************************************
+#define HIB_IO_IOWRC            0x80000000  // I/O Write Complete
+#define HIB_IO_WURSTEN          0x00000010  // Reset Wake Source Enable
+#define HIB_IO_WUUNLK           0x00000001  // I/O Wake Pad Configuration
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
+#define HIB_DATA_RTD_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALCTL register.
+//
+//*****************************************************************************
+#define HIB_CALCTL_CAL24        0x00000004  // Calendar Mode
+#define HIB_CALCTL_CALEN        0x00000001  // RTC Calendar/Counter Mode Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL0 register.
+//
+//*****************************************************************************
+#define HIB_CAL0_VALID          0x80000000  // Valid Calendar Load
+#define HIB_CAL0_AMPM           0x00400000  // AM/PM Designation
+#define HIB_CAL0_HR_M           0x001F0000  // Hours
+#define HIB_CAL0_MIN_M          0x00003F00  // Minutes
+#define HIB_CAL0_SEC_M          0x0000003F  // Seconds
+#define HIB_CAL0_HR_S           16
+#define HIB_CAL0_MIN_S          8
+#define HIB_CAL0_SEC_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL1 register.
+//
+//*****************************************************************************
+#define HIB_CAL1_VALID          0x80000000  // Valid Calendar Load
+#define HIB_CAL1_DOW_M          0x07000000  // Day of Week
+#define HIB_CAL1_YEAR_M         0x007F0000  // Year Value
+#define HIB_CAL1_MON_M          0x00000F00  // Month
+#define HIB_CAL1_DOM_M          0x0000001F  // Day of Month
+#define HIB_CAL1_DOW_S          24
+#define HIB_CAL1_YEAR_S         16
+#define HIB_CAL1_MON_S          8
+#define HIB_CAL1_DOM_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD0 register.
+//
+//*****************************************************************************
+#define HIB_CALLD0_AMPM         0x00400000  // AM/PM Designation
+#define HIB_CALLD0_HR_M         0x001F0000  // Hours
+#define HIB_CALLD0_MIN_M        0x00003F00  // Minutes
+#define HIB_CALLD0_SEC_M        0x0000003F  // Seconds
+#define HIB_CALLD0_HR_S         16
+#define HIB_CALLD0_MIN_S        8
+#define HIB_CALLD0_SEC_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD1 register.
+//
+//*****************************************************************************
+#define HIB_CALLD1_DOW_M        0x07000000  // Day of Week
+#define HIB_CALLD1_YEAR_M       0x007F0000  // Year Value
+#define HIB_CALLD1_MON_M        0x00000F00  // Month
+#define HIB_CALLD1_DOM_M        0x0000001F  // Day of Month
+#define HIB_CALLD1_DOW_S        24
+#define HIB_CALLD1_YEAR_S       16
+#define HIB_CALLD1_MON_S        8
+#define HIB_CALLD1_DOM_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM0 register.
+//
+//*****************************************************************************
+#define HIB_CALM0_AMPM          0x00400000  // AM/PM Designation
+#define HIB_CALM0_HR_M          0x001F0000  // Hours
+#define HIB_CALM0_MIN_M         0x00003F00  // Minutes
+#define HIB_CALM0_SEC_M         0x0000003F  // Seconds
+#define HIB_CALM0_HR_S          16
+#define HIB_CALM0_MIN_S         8
+#define HIB_CALM0_SEC_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM1 register.
+//
+//*****************************************************************************
+#define HIB_CALM1_DOM_M         0x0000001F  // Day of Month
+#define HIB_CALM1_DOM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_LOCK register.
+//
+//*****************************************************************************
+#define HIB_LOCK_HIBLOCK_M      0xFFFFFFFF  // HIbernate Lock
+#define HIB_LOCK_HIBLOCK_KEY    0xA3359554  // Hibernate Lock Key
+#define HIB_LOCK_HIBLOCK_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPCTL register.
+//
+//*****************************************************************************
+#define HIB_TPCTL_WAKE          0x00000800  // Wake from Hibernate on a Tamper
+                                            // Event
+#define HIB_TPCTL_MEMCLR_M      0x00000300  // HIB Memory Clear on Tamper Event
+#define HIB_TPCTL_MEMCLR_NONE   0x00000000  // Do not Clear HIB memory on
+                                            // tamper event
+#define HIB_TPCTL_MEMCLR_LOW32  0x00000100  // Clear Lower 32 Bytes of HIB
+                                            // memory on tamper event
+#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200  // Clear upper 32 Bytes of HIB
+                                            // memory on tamper event
+#define HIB_TPCTL_MEMCLR_ALL    0x00000300  // Clear all HIB memory on tamper
+                                            // event
+#define HIB_TPCTL_TPCLR         0x00000010  // Tamper Event Clear
+#define HIB_TPCTL_TPEN          0x00000001  // Tamper Module Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPSTAT register.
+//
+//*****************************************************************************
+#define HIB_TPSTAT_STATE_M      0x0000000C  // Tamper Module Status
+#define HIB_TPSTAT_STATE_DISABLED                                             \
+                                0x00000000  // Tamper disabled
+#define HIB_TPSTAT_STATE_CONFIGED                                             \
+                                0x00000004  // Tamper configured
+#define HIB_TPSTAT_STATE_ERROR  0x00000008  // Tamper pin event occurred
+#define HIB_TPSTAT_XOSCST       0x00000002  // External Oscillator Status
+#define HIB_TPSTAT_XOSCFAIL     0x00000001  // External Oscillator Failure
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPIO register.
+//
+//*****************************************************************************
+#define HIB_TPIO_GFLTR3         0x08000000  // TMPR3 Glitch Filtering
+#define HIB_TPIO_PUEN3          0x04000000  // TMPR3 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV3           0x02000000  // TMPR3 Trigger Level
+#define HIB_TPIO_EN3            0x01000000  // TMPR3 Enable
+#define HIB_TPIO_GFLTR2         0x00080000  // TMPR2 Glitch Filtering
+#define HIB_TPIO_PUEN2          0x00040000  // TMPR2 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV2           0x00020000  // TMPR2 Trigger Level
+#define HIB_TPIO_EN2            0x00010000  // TMPR2 Enable
+#define HIB_TPIO_GFLTR1         0x00000800  // TMPR1 Glitch Filtering
+#define HIB_TPIO_PUEN1          0x00000400  // TMPR1 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV1           0x00000200  // TMPR1 Trigger Level
+#define HIB_TPIO_EN1            0x00000100  // TMPR1Enable
+#define HIB_TPIO_GFLTR0         0x00000008  // TMPR0 Glitch Filtering
+#define HIB_TPIO_PUEN0          0x00000004  // TMPR0 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV0           0x00000002  // TMPR0 Trigger Level
+#define HIB_TPIO_EN0            0x00000001  // TMPR0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG0 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG0_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG0_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG1 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG1_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG1_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG1_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG1_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG1_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG2 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG2_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG2_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG3 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG3_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG3_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG3_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG3_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG3_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG4 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG4_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG4_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG5 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG5_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG5_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG5_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG5_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG5_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG6 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG6_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG6_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG7 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG7_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG7_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG7_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG7_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG7_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_PP register.
+//
+//*****************************************************************************
+#define HIB_PP_TAMPER           0x00000002  // Tamper Pin Presence
+#define HIB_PP_WAKENC           0x00000001  // Wake Pin Presence
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CC register.
+//
+//*****************************************************************************
+#define HIB_CC_SYSCLKEN         0x00000001  // RTCOSC to System Clock Enable
+
+#endif // __HW_HIBERNATE_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_i2c.h b/bsp/tm4c129x/libraries/inc/hw_i2c.h
new file mode 100644
index 0000000000..8544faaf46
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_i2c.h
@@ -0,0 +1,470 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA               0x00000000  // I2C Master Slave Address
+#define I2C_O_MCS               0x00000004  // I2C Master Control/Status
+#define I2C_O_MDR               0x00000008  // I2C Master Data
+#define I2C_O_MTPR              0x0000000C  // I2C Master Timer Period
+#define I2C_O_MIMR              0x00000010  // I2C Master Interrupt Mask
+#define I2C_O_MRIS              0x00000014  // I2C Master Raw Interrupt Status
+#define I2C_O_MMIS              0x00000018  // I2C Master Masked Interrupt
+                                            // Status
+#define I2C_O_MICR              0x0000001C  // I2C Master Interrupt Clear
+#define I2C_O_MCR               0x00000020  // I2C Master Configuration
+#define I2C_O_MCLKOCNT          0x00000024  // I2C Master Clock Low Timeout
+                                            // Count
+#define I2C_O_MBMON             0x0000002C  // I2C Master Bus Monitor
+#define I2C_O_MBLEN             0x00000030  // I2C Master Burst Length
+#define I2C_O_MBCNT             0x00000034  // I2C Master Burst Count
+#define I2C_O_MCR2              0x00000038  // I2C Master Configuration 2
+#define I2C_O_SOAR              0x00000800  // I2C Slave Own Address
+#define I2C_O_SCSR              0x00000804  // I2C Slave Control/Status
+#define I2C_O_SDR               0x00000808  // I2C Slave Data
+#define I2C_O_SIMR              0x0000080C  // I2C Slave Interrupt Mask
+#define I2C_O_SRIS              0x00000810  // I2C Slave Raw Interrupt Status
+#define I2C_O_SMIS              0x00000814  // I2C Slave Masked Interrupt
+                                            // Status
+#define I2C_O_SICR              0x00000818  // I2C Slave Interrupt Clear
+#define I2C_O_SOAR2             0x0000081C  // I2C Slave Own Address 2
+#define I2C_O_SACKCTL           0x00000820  // I2C Slave ACK Control
+#define I2C_O_FIFODATA          0x00000F00  // I2C FIFO Data
+#define I2C_O_FIFOCTL           0x00000F04  // I2C FIFO Control
+#define I2C_O_FIFOSTATUS        0x00000F08  // I2C FIFO Status
+#define I2C_O_PP                0x00000FC0  // I2C Peripheral Properties
+#define I2C_O_PC                0x00000FC4  // I2C Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_ACTDMARX        0x80000000  // DMA RX Active Status
+#define I2C_MCS_ACTDMATX        0x40000000  // DMA TX Active Status
+#define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error
+#define I2C_MCS_BURST           0x00000040  // Burst Enable
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_QCMD            0x00000020  // Quick Command
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_HS              0x00000010  // High-Speed Enable
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // This byte contains the data
+                                            // transferred during a transaction
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_PULSEL_M       0x00070000  // Glitch Suppression Pulse Width
+#define I2C_MTPR_PULSEL_BYPASS  0x00000000  // Bypass
+#define I2C_MTPR_PULSEL_1       0x00010000  // 1 clock
+#define I2C_MTPR_PULSEL_2       0x00020000  // 2 clocks
+#define I2C_MTPR_PULSEL_3       0x00030000  // 3 clocks
+#define I2C_MTPR_PULSEL_4       0x00040000  // 4 clocks
+#define I2C_MTPR_PULSEL_8       0x00050000  // 8 clocks
+#define I2C_MTPR_PULSEL_16      0x00060000  // 16 clocks
+#define I2C_MTPR_PULSEL_31      0x00070000  // 31 clocks
+#define I2C_MTPR_HS             0x00000080  // High-Speed Enable
+#define I2C_MTPR_TPR_M          0x0000007F  // Timer Period
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_RXFFIM         0x00000800  // Receive FIFO Full Interrupt Mask
+#define I2C_MIMR_TXFEIM         0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_MIMR_RXIM           0x00000200  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_MIMR_TXIM           0x00000100  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_MIMR_ARBLOSTIM      0x00000080  // Arbitration Lost Interrupt Mask
+#define I2C_MIMR_STOPIM         0x00000040  // STOP Detection Interrupt Mask
+#define I2C_MIMR_STARTIM        0x00000020  // START Detection Interrupt Mask
+#define I2C_MIMR_NACKIM         0x00000010  // Address/Data NACK Interrupt Mask
+#define I2C_MIMR_DMATXIM        0x00000008  // Transmit DMA Interrupt Mask
+#define I2C_MIMR_DMARXIM        0x00000004  // Receive DMA Interrupt Mask
+#define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RXFFRIS        0x00000800  // Receive FIFO Full Raw Interrupt
+                                            // Status
+#define I2C_MRIS_TXFERIS        0x00000400  // Transmit FIFO Empty Raw
+                                            // Interrupt Status
+#define I2C_MRIS_RXRIS          0x00000200  // Receive FIFO Request Raw
+                                            // Interrupt Status
+#define I2C_MRIS_TXRIS          0x00000100  // Transmit Request Raw Interrupt
+                                            // Status
+#define I2C_MRIS_ARBLOSTRIS     0x00000080  // Arbitration Lost Raw Interrupt
+                                            // Status
+#define I2C_MRIS_STOPRIS        0x00000040  // STOP Detection Raw Interrupt
+                                            // Status
+#define I2C_MRIS_STARTRIS       0x00000020  // START Detection Raw Interrupt
+                                            // Status
+#define I2C_MRIS_NACKRIS        0x00000010  // Address/Data NACK Raw Interrupt
+                                            // Status
+#define I2C_MRIS_DMATXRIS       0x00000008  // Transmit DMA Raw Interrupt
+                                            // Status
+#define I2C_MRIS_DMARXRIS       0x00000004  // Receive DMA Raw Interrupt Status
+#define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt
+                                            // Status
+#define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_RXFFMIS        0x00000800  // Receive FIFO Full Interrupt Mask
+#define I2C_MMIS_TXFEMIS        0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_MMIS_RXMIS          0x00000200  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_MMIS_TXMIS          0x00000100  // Transmit Request Interrupt Mask
+#define I2C_MMIS_ARBLOSTMIS     0x00000080  // Arbitration Lost Interrupt Mask
+#define I2C_MMIS_STOPMIS        0x00000040  // STOP Detection Interrupt Mask
+#define I2C_MMIS_STARTMIS       0x00000020  // START Detection Interrupt Mask
+#define I2C_MMIS_NACKMIS        0x00000010  // Address/Data NACK Interrupt Mask
+#define I2C_MMIS_DMATXMIS       0x00000008  // Transmit DMA Interrupt Status
+#define I2C_MMIS_DMARXMIS       0x00000004  // Receive DMA Interrupt Status
+#define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt
+                                            // Status
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_RXFFIC         0x00000800  // Receive FIFO Full Interrupt
+                                            // Clear
+#define I2C_MICR_TXFEIC         0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Clear
+#define I2C_MICR_RXIC           0x00000200  // Receive FIFO Request Interrupt
+                                            // Clear
+#define I2C_MICR_TXIC           0x00000100  // Transmit FIFO Request Interrupt
+                                            // Clear
+#define I2C_MICR_ARBLOSTIC      0x00000080  // Arbitration Lost Interrupt Clear
+#define I2C_MICR_STOPIC         0x00000040  // STOP Detection Interrupt Clear
+#define I2C_MICR_STARTIC        0x00000020  // START Detection Interrupt Clear
+#define I2C_MICR_NACKIC         0x00000010  // Address/Data NACK Interrupt
+                                            // Clear
+#define I2C_MICR_DMATXIC        0x00000008  // Transmit DMA Interrupt Clear
+#define I2C_MICR_DMARXIC        0x00000004  // Receive DMA Interrupt Clear
+#define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC             0x00000001  // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_GFE             0x00000040  // I2C Glitch Filter Enable
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M     0x000000FF  // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA           0x00000002  // I2C SDA Status
+#define I2C_MBMON_SCL           0x00000001  // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBLEN register.
+//
+//*****************************************************************************
+#define I2C_MBLEN_CNTL_M        0x000000FF  // I2C Burst Length
+#define I2C_MBLEN_CNTL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBCNT register.
+//
+//*****************************************************************************
+#define I2C_MBCNT_CNTL_M        0x000000FF  // I2C Master Burst Count
+#define I2C_MBCNT_CNTL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR2 register.
+//
+//*****************************************************************************
+#define I2C_MCR2_GFPW_M         0x00000070  // I2C Glitch Filter Pulse Width
+#define I2C_MCR2_GFPW_BYPASS    0x00000000  // Bypass
+#define I2C_MCR2_GFPW_1         0x00000010  // 1 clock
+#define I2C_MCR2_GFPW_2         0x00000020  // 2 clocks
+#define I2C_MCR2_GFPW_3         0x00000030  // 3 clocks
+#define I2C_MCR2_GFPW_4         0x00000040  // 4 clocks
+#define I2C_MCR2_GFPW_8         0x00000050  // 8 clocks
+#define I2C_MCR2_GFPW_16        0x00000060  // 16 clocks
+#define I2C_MCR2_GFPW_31        0x00000070  // 31 clocks
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_ACTDMARX       0x80000000  // DMA RX Active Status
+#define I2C_SCSR_ACTDMATX       0x40000000  // DMA TX Active Status
+#define I2C_SCSR_QCMDRW         0x00000020  // Quick Command Read / Write
+#define I2C_SCSR_QCMDST         0x00000010  // Quick Command Status
+#define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_RXFIFO         0x00000004  // RX FIFO Enable
+#define I2C_SCSR_TXFIFO         0x00000002  // TX FIFO Enable
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_RXFFIM         0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SIMR_TXFEIM         0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SIMR_RXIM           0x00000040  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_SIMR_TXIM           0x00000020  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_SIMR_DMATXIM        0x00000010  // Transmit DMA Interrupt Mask
+#define I2C_SIMR_DMARXIM        0x00000008  // Receive DMA Interrupt Mask
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RXFFRIS        0x00000100  // Receive FIFO Full Raw Interrupt
+                                            // Status
+#define I2C_SRIS_TXFERIS        0x00000080  // Transmit FIFO Empty Raw
+                                            // Interrupt Status
+#define I2C_SRIS_RXRIS          0x00000040  // Receive FIFO Request Raw
+                                            // Interrupt Status
+#define I2C_SRIS_TXRIS          0x00000020  // Transmit Request Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DMATXRIS       0x00000010  // Transmit DMA Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DMARXRIS       0x00000008  // Receive DMA Raw Interrupt Status
+#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_RXFFMIS        0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SMIS_TXFEMIS        0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SMIS_RXMIS          0x00000040  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_SMIS_TXMIS          0x00000020  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_SMIS_DMATXMIS       0x00000010  // Transmit DMA Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DMARXMIS       0x00000008  // Receive DMA Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_RXFFIC         0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SICR_TXFEIC         0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SICR_RXIC           0x00000040  // Receive Request Interrupt Mask
+#define I2C_SICR_TXIC           0x00000020  // Transmit Request Interrupt Mask
+#define I2C_SICR_DMATXIC        0x00000010  // Transmit DMA Interrupt Clear
+#define I2C_SICR_DMARXIC        0x00000008  // Receive DMA Interrupt Clear
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M        0x0000007F  // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFODATA register.
+//
+//*****************************************************************************
+#define I2C_FIFODATA_DATA_M     0x000000FF  // I2C TX FIFO Write Data Byte
+#define I2C_FIFODATA_DATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
+//
+//*****************************************************************************
+#define I2C_FIFOCTL_RXASGNMT    0x80000000  // RX Control Assignment
+#define I2C_FIFOCTL_RXFLUSH     0x40000000  // RX FIFO Flush
+#define I2C_FIFOCTL_DMARXENA    0x20000000  // DMA RX Channel Enable
+#define I2C_FIFOCTL_RXTRIG_M    0x00070000  // RX FIFO Trigger
+#define I2C_FIFOCTL_TXASGNMT    0x00008000  // TX Control Assignment
+#define I2C_FIFOCTL_TXFLUSH     0x00004000  // TX FIFO Flush
+#define I2C_FIFOCTL_DMATXENA    0x00002000  // DMA TX Channel Enable
+#define I2C_FIFOCTL_TXTRIG_M    0x00000007  // TX FIFO Trigger
+#define I2C_FIFOCTL_RXTRIG_S    16
+#define I2C_FIFOCTL_TXTRIG_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOSTATUS
+// register.
+//
+//*****************************************************************************
+#define I2C_FIFOSTATUS_RXABVTRIG                                              \
+                                0x00040000  // RX FIFO Above Trigger Level
+#define I2C_FIFOSTATUS_RXFF     0x00020000  // RX FIFO Full
+#define I2C_FIFOSTATUS_RXFE     0x00010000  // RX FIFO Empty
+#define I2C_FIFOSTATUS_TXBLWTRIG                                              \
+                                0x00000004  // TX FIFO Below Trigger Level
+#define I2C_FIFOSTATUS_TXFF     0x00000002  // TX FIFO Full
+#define I2C_FIFOSTATUS_TXFE     0x00000001  // TX FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS               0x00000001  // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS               0x00000001  // High-Speed Capable
+
+#endif // __HW_I2C_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_ints.h b/bsp/tm4c129x/libraries/inc/hw_ints.h
new file mode 100644
index 0000000000..df1a716690
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_ints.h
@@ -0,0 +1,491 @@
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
+// MCUs.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI               2           // NMI fault
+#define FAULT_HARD              3           // Hard fault
+#define FAULT_MPU               4           // MPU fault
+#define FAULT_BUS               5           // Bus fault
+#define FAULT_USAGE             6           // Usage fault
+#define FAULT_SVCALL            11          // SVCall
+#define FAULT_DEBUG             12          // Debug monitor
+#define FAULT_PENDSV            14          // PendSV
+#define FAULT_SYSTICK           15          // System Tick
+
+//*****************************************************************************
+//
+// TM4C123 Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_TM4C123       16          // GPIO Port A
+#define INT_GPIOB_TM4C123       17          // GPIO Port B
+#define INT_GPIOC_TM4C123       18          // GPIO Port C
+#define INT_GPIOD_TM4C123       19          // GPIO Port D
+#define INT_GPIOE_TM4C123       20          // GPIO Port E
+#define INT_UART0_TM4C123       21          // UART0
+#define INT_UART1_TM4C123       22          // UART1
+#define INT_SSI0_TM4C123        23          // SSI0
+#define INT_I2C0_TM4C123        24          // I2C0
+#define INT_PWM0_FAULT_TM4C123  25          // PWM0 Fault
+#define INT_PWM0_0_TM4C123      26          // PWM0 Generator 0
+#define INT_PWM0_1_TM4C123      27          // PWM0 Generator 1
+#define INT_PWM0_2_TM4C123      28          // PWM0 Generator 2
+#define INT_QEI0_TM4C123        29          // QEI0
+#define INT_ADC0SS0_TM4C123     30          // ADC0 Sequence 0
+#define INT_ADC0SS1_TM4C123     31          // ADC0 Sequence 1
+#define INT_ADC0SS2_TM4C123     32          // ADC0 Sequence 2
+#define INT_ADC0SS3_TM4C123     33          // ADC0 Sequence 3
+#define INT_WATCHDOG_TM4C123    34          // Watchdog Timers 0 and 1
+#define INT_TIMER0A_TM4C123     35          // 16/32-Bit Timer 0A
+#define INT_TIMER0B_TM4C123     36          // 16/32-Bit Timer 0B
+#define INT_TIMER1A_TM4C123     37          // 16/32-Bit Timer 1A
+#define INT_TIMER1B_TM4C123     38          // 16/32-Bit Timer 1B
+#define INT_TIMER2A_TM4C123     39          // 16/32-Bit Timer 2A
+#define INT_TIMER2B_TM4C123     40          // 16/32-Bit Timer 2B
+#define INT_COMP0_TM4C123       41          // Analog Comparator 0
+#define INT_COMP1_TM4C123       42          // Analog Comparator 1
+#define INT_COMP2_TM4C123       43          // Analog Comparator 2
+#define INT_SYSCTL_TM4C123      44          // System Control
+#define INT_FLASH_TM4C123       45          // Flash Memory Control and EEPROM
+                                            // Control
+#define INT_GPIOF_TM4C123       46          // GPIO Port F
+#define INT_GPIOG_TM4C123       47          // GPIO Port G
+#define INT_GPIOH_TM4C123       48          // GPIO Port H
+#define INT_UART2_TM4C123       49          // UART2
+#define INT_SSI1_TM4C123        50          // SSI1
+#define INT_TIMER3A_TM4C123     51          // 16/32-Bit Timer 3A
+#define INT_TIMER3B_TM4C123     52          // Timer 3B
+#define INT_I2C1_TM4C123        53          // I2C1
+#define INT_QEI1_TM4C123        54          // QEI1
+#define INT_CAN0_TM4C123        55          // CAN0
+#define INT_CAN1_TM4C123        56          // CAN1
+#define INT_HIBERNATE_TM4C123   59          // Hibernation Module
+#define INT_USB0_TM4C123        60          // USB
+#define INT_PWM0_3_TM4C123      61          // PWM Generator 3
+#define INT_UDMA_TM4C123        62          // uDMA Software
+#define INT_UDMAERR_TM4C123     63          // uDMA Error
+#define INT_ADC1SS0_TM4C123     64          // ADC1 Sequence 0
+#define INT_ADC1SS1_TM4C123     65          // ADC1 Sequence 1
+#define INT_ADC1SS2_TM4C123     66          // ADC1 Sequence 2
+#define INT_ADC1SS3_TM4C123     67          // ADC1 Sequence 3
+#define INT_GPIOJ_TM4C123       70          // GPIO Port J
+#define INT_GPIOK_TM4C123       71          // GPIO Port K
+#define INT_GPIOL_TM4C123       72          // GPIO Port L
+#define INT_SSI2_TM4C123        73          // SSI2
+#define INT_SSI3_TM4C123        74          // SSI3
+#define INT_UART3_TM4C123       75          // UART3
+#define INT_UART4_TM4C123       76          // UART4
+#define INT_UART5_TM4C123       77          // UART5
+#define INT_UART6_TM4C123       78          // UART6
+#define INT_UART7_TM4C123       79          // UART7
+#define INT_I2C2_TM4C123        84          // I2C2
+#define INT_I2C3_TM4C123        85          // I2C3
+#define INT_TIMER4A_TM4C123     86          // 16/32-Bit Timer 4A
+#define INT_TIMER4B_TM4C123     87          // 16/32-Bit Timer 4B
+#define INT_TIMER5A_TM4C123     108         // 16/32-Bit Timer 5A
+#define INT_TIMER5B_TM4C123     109         // 16/32-Bit Timer 5B
+#define INT_WTIMER0A_TM4C123    110         // 32/64-Bit Timer 0A
+#define INT_WTIMER0B_TM4C123    111         // 32/64-Bit Timer 0B
+#define INT_WTIMER1A_TM4C123    112         // 32/64-Bit Timer 1A
+#define INT_WTIMER1B_TM4C123    113         // 32/64-Bit Timer 1B
+#define INT_WTIMER2A_TM4C123    114         // 32/64-Bit Timer 2A
+#define INT_WTIMER2B_TM4C123    115         // 32/64-Bit Timer 2B
+#define INT_WTIMER3A_TM4C123    116         // 32/64-Bit Timer 3A
+#define INT_WTIMER3B_TM4C123    117         // 32/64-Bit Timer 3B
+#define INT_WTIMER4A_TM4C123    118         // 32/64-Bit Timer 4A
+#define INT_WTIMER4B_TM4C123    119         // 32/64-Bit Timer 4B
+#define INT_WTIMER5A_TM4C123    120         // 32/64-Bit Timer 5A
+#define INT_WTIMER5B_TM4C123    121         // 32/64-Bit Timer 5B
+#define INT_SYSEXC_TM4C123      122         // System Exception (imprecise)
+#define INT_I2C4_TM4C123        125         // I2C4
+#define INT_I2C5_TM4C123        126         // I2C5
+#define INT_GPIOM_TM4C123       127         // GPIO Port M
+#define INT_GPION_TM4C123       128         // GPIO Port N
+#define INT_GPIOP0_TM4C123      132         // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_TM4C123      133         // GPIO Port P1
+#define INT_GPIOP2_TM4C123      134         // GPIO Port P2
+#define INT_GPIOP3_TM4C123      135         // GPIO Port P3
+#define INT_GPIOP4_TM4C123      136         // GPIO Port P4
+#define INT_GPIOP5_TM4C123      137         // GPIO Port P5
+#define INT_GPIOP6_TM4C123      138         // GPIO Port P6
+#define INT_GPIOP7_TM4C123      139         // GPIO Port P7
+#define INT_GPIOQ0_TM4C123      140         // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_TM4C123      141         // GPIO Port Q1
+#define INT_GPIOQ2_TM4C123      142         // GPIO Port Q2
+#define INT_GPIOQ3_TM4C123      143         // GPIO Port Q3
+#define INT_GPIOQ4_TM4C123      144         // GPIO Port Q4
+#define INT_GPIOQ5_TM4C123      145         // GPIO Port Q5
+#define INT_GPIOQ6_TM4C123      146         // GPIO Port Q6
+#define INT_GPIOQ7_TM4C123      147         // GPIO Port Q7
+#define INT_PWM1_0_TM4C123      150         // PWM1 Generator 0
+#define INT_PWM1_1_TM4C123      151         // PWM1 Generator 1
+#define INT_PWM1_2_TM4C123      152         // PWM1 Generator 2
+#define INT_PWM1_3_TM4C123      153         // PWM1 Generator 3
+#define INT_PWM1_FAULT_TM4C123  154         // PWM1 Fault
+#define NUM_INTERRUPTS_TM4C123  155
+
+//*****************************************************************************
+//
+// TM4C129 Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_TM4C129       16          // GPIO Port A
+#define INT_GPIOB_TM4C129       17          // GPIO Port B
+#define INT_GPIOC_TM4C129       18          // GPIO Port C
+#define INT_GPIOD_TM4C129       19          // GPIO Port D
+#define INT_GPIOE_TM4C129       20          // GPIO Port E
+#define INT_UART0_TM4C129       21          // UART0
+#define INT_UART1_TM4C129       22          // UART1
+#define INT_SSI0_TM4C129        23          // SSI0
+#define INT_I2C0_TM4C129        24          // I2C0
+#define INT_PWM0_FAULT_TM4C129  25          // PWM Fault
+#define INT_PWM0_0_TM4C129      26          // PWM Generator 0
+#define INT_PWM0_1_TM4C129      27          // PWM Generator 1
+#define INT_PWM0_2_TM4C129      28          // PWM Generator 2
+#define INT_QEI0_TM4C129        29          // QEI0
+#define INT_ADC0SS0_TM4C129     30          // ADC0 Sequence 0
+#define INT_ADC0SS1_TM4C129     31          // ADC0 Sequence 1
+#define INT_ADC0SS2_TM4C129     32          // ADC0 Sequence 2
+#define INT_ADC0SS3_TM4C129     33          // ADC0 Sequence 3
+#define INT_WATCHDOG_TM4C129    34          // Watchdog Timers 0 and 1
+#define INT_TIMER0A_TM4C129     35          // 16/32-Bit Timer 0A
+#define INT_TIMER0B_TM4C129     36          // 16/32-Bit Timer 0B
+#define INT_TIMER1A_TM4C129     37          // 16/32-Bit Timer 1A
+#define INT_TIMER1B_TM4C129     38          // 16/32-Bit Timer 1B
+#define INT_TIMER2A_TM4C129     39          // 16/32-Bit Timer 2A
+#define INT_TIMER2B_TM4C129     40          // 16/32-Bit Timer 2B
+#define INT_COMP0_TM4C129       41          // Analog Comparator 0
+#define INT_COMP1_TM4C129       42          // Analog Comparator 1
+#define INT_COMP2_TM4C129       43          // Analog Comparator 2
+#define INT_SYSCTL_TM4C129      44          // System Control
+#define INT_FLASH_TM4C129       45          // Flash Memory Control
+#define INT_GPIOF_TM4C129       46          // GPIO Port F
+#define INT_GPIOG_TM4C129       47          // GPIO Port G
+#define INT_GPIOH_TM4C129       48          // GPIO Port H
+#define INT_UART2_TM4C129       49          // UART2
+#define INT_SSI1_TM4C129        50          // SSI1
+#define INT_TIMER3A_TM4C129     51          // 16/32-Bit Timer 3A
+#define INT_TIMER3B_TM4C129     52          // 16/32-Bit Timer 3B
+#define INT_I2C1_TM4C129        53          // I2C1
+#define INT_CAN0_TM4C129        54          // CAN 0
+#define INT_CAN1_TM4C129        55          // CAN1
+#define INT_EMAC0_TM4C129       56          // Ethernet MAC
+#define INT_HIBERNATE_TM4C129   57          // HIB
+#define INT_USB0_TM4C129        58          // USB MAC
+#define INT_PWM0_3_TM4C129      59          // PWM Generator 3
+#define INT_UDMA_TM4C129        60          // uDMA 0 Software
+#define INT_UDMAERR_TM4C129     61          // uDMA 0 Error
+#define INT_ADC1SS0_TM4C129     62          // ADC1 Sequence 0
+#define INT_ADC1SS1_TM4C129     63          // ADC1 Sequence 1
+#define INT_ADC1SS2_TM4C129     64          // ADC1 Sequence 2
+#define INT_ADC1SS3_TM4C129     65          // ADC1 Sequence 3
+#define INT_EPI0_TM4C129        66          // EPI 0
+#define INT_GPIOJ_TM4C129       67          // GPIO Port J
+#define INT_GPIOK_TM4C129       68          // GPIO Port K
+#define INT_GPIOL_TM4C129       69          // GPIO Port L
+#define INT_SSI2_TM4C129        70          // SSI 2
+#define INT_SSI3_TM4C129        71          // SSI 3
+#define INT_UART3_TM4C129       72          // UART 3
+#define INT_UART4_TM4C129       73          // UART 4
+#define INT_UART5_TM4C129       74          // UART 5
+#define INT_UART6_TM4C129       75          // UART 6
+#define INT_UART7_TM4C129       76          // UART 7
+#define INT_I2C2_TM4C129        77          // I2C 2
+#define INT_I2C3_TM4C129        78          // I2C 3
+#define INT_TIMER4A_TM4C129     79          // Timer 4A
+#define INT_TIMER4B_TM4C129     80          // Timer 4B
+#define INT_TIMER5A_TM4C129     81          // Timer 5A
+#define INT_TIMER5B_TM4C129     82          // Timer 5B
+#define INT_SYSEXC_TM4C129      83          // Floating-Point Exception
+                                            // (imprecise)
+#define INT_I2C4_TM4C129        86          // I2C 4
+#define INT_I2C5_TM4C129        87          // I2C 5
+#define INT_GPIOM_TM4C129       88          // GPIO Port M
+#define INT_GPION_TM4C129       89          // GPIO Port N
+#define INT_TAMPER0_TM4C129     91          // Tamper
+#define INT_GPIOP0_TM4C129      92          // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_TM4C129      93          // GPIO Port P1
+#define INT_GPIOP2_TM4C129      94          // GPIO Port P2
+#define INT_GPIOP3_TM4C129      95          // GPIO Port P3
+#define INT_GPIOP4_TM4C129      96          // GPIO Port P4
+#define INT_GPIOP5_TM4C129      97          // GPIO Port P5
+#define INT_GPIOP6_TM4C129      98          // GPIO Port P6
+#define INT_GPIOP7_TM4C129      99          // GPIO Port P7
+#define INT_GPIOQ0_TM4C129      100         // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_TM4C129      101         // GPIO Port Q1
+#define INT_GPIOQ2_TM4C129      102         // GPIO Port Q2
+#define INT_GPIOQ3_TM4C129      103         // GPIO Port Q3
+#define INT_GPIOQ4_TM4C129      104         // GPIO Port Q4
+#define INT_GPIOQ5_TM4C129      105         // GPIO Port Q5
+#define INT_GPIOQ6_TM4C129      106         // GPIO Port Q6
+#define INT_GPIOQ7_TM4C129      107         // GPIO Port Q7
+#define INT_GPIOR_TM4C129       108         // GPIO Port R
+#define INT_GPIOS_TM4C129       109         // GPIO Port S
+#define INT_SHA0_TM4C129        110         // SHA/MD5
+#define INT_AES0_TM4C129        111         // AES
+#define INT_DES0_TM4C129        112         // DES
+#define INT_LCD0_TM4C129        113         // LCD
+#define INT_TIMER6A_TM4C129     114         // 16/32-Bit Timer 6A
+#define INT_TIMER6B_TM4C129     115         // 16/32-Bit Timer 6B
+#define INT_TIMER7A_TM4C129     116         // 16/32-Bit Timer 7A
+#define INT_TIMER7B_TM4C129     117         // 16/32-Bit Timer 7B
+#define INT_I2C6_TM4C129        118         // I2C 6
+#define INT_I2C7_TM4C129        119         // I2C 7
+#define INT_ONEWIRE0_TM4C129    121         // 1-Wire
+#define INT_I2C8_TM4C129        125         // I2C 8
+#define INT_I2C9_TM4C129        126         // I2C 9
+#define INT_GPIOT_TM4C129       127         // GPIO T
+#define NUM_INTERRUPTS_TM4C129  129
+
+//*****************************************************************************
+//
+// TM4C123 Interrupt Class Definition
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \
+    defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \
+    defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \
+    defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
+    defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
+    defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
+    defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
+    defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
+    defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
+    defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
+    defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
+    defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
+    defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
+    defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
+    defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
+    defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
+    defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
+    defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
+    defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
+    defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
+    defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
+    defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
+    defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
+    defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
+    defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
+    defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
+    defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
+    defined(PART_TM4C123GH6ZRB)
+#define INT_RESOLVE(intname, class) intname##TM4C123
+
+//*****************************************************************************
+//
+// TM4C129 Interrupt Class Definition
+//
+//*****************************************************************************
+#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \
+    defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \
+    defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \
+    defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \
+    defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \
+    defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \
+    defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \
+    defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \
+    defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \
+    defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \
+    defined(PART_TM4C129XNCZAD)
+#define INT_RESOLVE(intname, class) intname##TM4C129
+#else
+#define INT_DEVICE_CLASS        "UNKNOWN"
+#endif
+
+//*****************************************************************************
+//
+// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
+//
+//*****************************************************************************
+#define INT_CONCAT(intname, class)  INT_RESOLVE(intname, class)
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_ADC0SS0             INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
+#define INT_ADC0SS1             INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
+#define INT_ADC0SS2             INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
+#define INT_ADC0SS3             INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
+#define INT_ADC1SS0             INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
+#define INT_ADC1SS1             INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
+#define INT_ADC1SS2             INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
+#define INT_ADC1SS3             INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
+#define INT_AES0                INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS)
+#define INT_CAN0                INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
+#define INT_CAN1                INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
+#define INT_COMP0               INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
+#define INT_COMP1               INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
+#define INT_COMP2               INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
+#define INT_DES0                INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS)
+#define INT_EMAC0               INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS)
+#define INT_EPI0                INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS)
+#define INT_FLASH               INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
+#define INT_GPIOA               INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
+#define INT_GPIOB               INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
+#define INT_GPIOC               INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
+#define INT_GPIOD               INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
+#define INT_GPIOE               INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
+#define INT_GPIOF               INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
+#define INT_GPIOG               INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
+#define INT_GPIOH               INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
+#define INT_GPIOJ               INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
+#define INT_GPIOK               INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
+#define INT_GPIOL               INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
+#define INT_GPIOM               INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
+#define INT_GPION               INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
+#define INT_GPIOP0              INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
+#define INT_GPIOP1              INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
+#define INT_GPIOP2              INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
+#define INT_GPIOP3              INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
+#define INT_GPIOP4              INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
+#define INT_GPIOP5              INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
+#define INT_GPIOP6              INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
+#define INT_GPIOP7              INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
+#define INT_GPIOQ0              INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
+#define INT_GPIOQ1              INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
+#define INT_GPIOQ2              INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
+#define INT_GPIOQ3              INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
+#define INT_GPIOQ4              INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
+#define INT_GPIOQ5              INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
+#define INT_GPIOQ6              INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
+#define INT_GPIOQ7              INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
+#define INT_GPIOR               INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS)
+#define INT_GPIOS               INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS)
+#define INT_GPIOT               INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS)
+#define INT_HIBERNATE           INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
+#define INT_I2C0                INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
+#define INT_I2C1                INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
+#define INT_I2C2                INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
+#define INT_I2C3                INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
+#define INT_I2C4                INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
+#define INT_I2C5                INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
+#define INT_I2C6                INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS)
+#define INT_I2C7                INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS)
+#define INT_I2C8                INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS)
+#define INT_I2C9                INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS)
+#define INT_LCD0                INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS)
+#define INT_ONEWIRE0            INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS)
+#define INT_PWM0_0              INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
+#define INT_PWM0_1              INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
+#define INT_PWM0_2              INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
+#define INT_PWM0_3              INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
+#define INT_PWM0_FAULT          INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
+#define INT_PWM1_0              INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
+#define INT_PWM1_1              INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
+#define INT_PWM1_2              INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
+#define INT_PWM1_3              INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
+#define INT_PWM1_FAULT          INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
+#define INT_QEI0                INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
+#define INT_QEI1                INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
+#define INT_SHA0                INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS)
+#define INT_SSI0                INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
+#define INT_SSI1                INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
+#define INT_SSI2                INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
+#define INT_SSI3                INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
+#define INT_SYSCTL              INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
+#define INT_SYSEXC              INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
+#define INT_TAMPER0             INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS)
+#define INT_TIMER0A             INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
+#define INT_TIMER0B             INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
+#define INT_TIMER1A             INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
+#define INT_TIMER1B             INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
+#define INT_TIMER2A             INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
+#define INT_TIMER2B             INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
+#define INT_TIMER3A             INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
+#define INT_TIMER3B             INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
+#define INT_TIMER4A             INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
+#define INT_TIMER4B             INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
+#define INT_TIMER5A             INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
+#define INT_TIMER5B             INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
+#define INT_TIMER6A             INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS)
+#define INT_TIMER6B             INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS)
+#define INT_TIMER7A             INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS)
+#define INT_TIMER7B             INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS)
+#define INT_UART0               INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
+#define INT_UART1               INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
+#define INT_UART2               INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
+#define INT_UART3               INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
+#define INT_UART4               INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
+#define INT_UART5               INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
+#define INT_UART6               INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
+#define INT_UART7               INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
+#define INT_UDMA                INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
+#define INT_UDMAERR             INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
+#define INT_USB0                INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
+#define INT_WATCHDOG            INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
+#define INT_WTIMER0A            INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
+#define INT_WTIMER0B            INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
+#define INT_WTIMER1A            INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
+#define INT_WTIMER1B            INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
+#define INT_WTIMER2A            INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
+#define INT_WTIMER2B            INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
+#define INT_WTIMER3A            INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
+#define INT_WTIMER3B            INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
+#define INT_WTIMER4A            INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
+#define INT_WTIMER4B            INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
+#define INT_WTIMER5A            INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
+#define INT_WTIMER5B            INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS          INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY            8
+#define NUM_PRIORITY_BITS       3
+
+#endif // __HW_INTS_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_lcd.h b/bsp/tm4c129x/libraries/inc/hw_lcd.h
new file mode 100644
index 0000000000..e2f80e08a0
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_lcd.h
@@ -0,0 +1,575 @@
+//*****************************************************************************
+//
+// hw_lcd.h - Defines and macros used when accessing the LCD controller.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_LCD_H__
+#define __HW_LCD_H__
+
+//*****************************************************************************
+//
+// The following are defines for the LCD register offsets.
+//
+//*****************************************************************************
+#define LCD_O_PID               0x00000000  // LCD PID Register Format
+#define LCD_O_CTL               0x00000004  // LCD Control
+#define LCD_O_LIDDCTL           0x0000000C  // LCD LIDD Control
+#define LCD_O_LIDDCS0CFG        0x00000010  // LCD LIDD CS0 Configuration
+#define LCD_O_LIDDCS0ADDR       0x00000014  // LIDD CS0 Read/Write Address
+#define LCD_O_LIDDCS0DATA       0x00000018  // LIDD CS0 Data Read/Write
+                                            // Initiation
+#define LCD_O_LIDDCS1CFG        0x0000001C  // LIDD CS1 Configuration
+#define LCD_O_LIDDCS1ADDR       0x00000020  // LIDD CS1 Address Read/Write
+                                            // Initiation
+#define LCD_O_LIDDCS1DATA       0x00000024  // LIDD CS1 Data Read/Write
+                                            // Initiation
+#define LCD_O_RASTRCTL          0x00000028  // LCD Raster Control
+#define LCD_O_RASTRTIM0         0x0000002C  // LCD Raster Timing 0
+#define LCD_O_RASTRTIM1         0x00000030  // LCD Raster Timing 1
+#define LCD_O_RASTRTIM2         0x00000034  // LCD Raster Timing 2
+#define LCD_O_RASTRSUBP1        0x00000038  // LCD Raster Subpanel Display 1
+#define LCD_O_RASTRSUBP2        0x0000003C  // LCD Raster Subpanel Display 2
+#define LCD_O_DMACTL            0x00000040  // LCD DMA Control
+#define LCD_O_DMABAFB0          0x00000044  // LCD DMA Frame Buffer 0 Base
+                                            // Address
+#define LCD_O_DMACAFB0          0x00000048  // LCD DMA Frame Buffer 0 Ceiling
+                                            // Address
+#define LCD_O_DMABAFB1          0x0000004C  // LCD DMA Frame Buffer 1 Base
+                                            // Address
+#define LCD_O_DMACAFB1          0x00000050  // LCD DMA Frame Buffer 1 Ceiling
+                                            // Address
+#define LCD_O_SYSCFG            0x00000054  // LCD System Configuration
+                                            // Register
+#define LCD_O_RISSET            0x00000058  // LCD Interrupt Raw Status and Set
+                                            // Register
+#define LCD_O_MISCLR            0x0000005C  // LCD Interrupt Status and Clear
+#define LCD_O_IM                0x00000060  // LCD Interrupt Mask
+#define LCD_O_IENC              0x00000064  // LCD Interrupt Enable Clear
+#define LCD_O_CLKEN             0x0000006C  // LCD Clock Enable
+#define LCD_O_CLKRESET          0x00000070  // LCD Clock Resets
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_PID register.
+//
+//*****************************************************************************
+#define LCD_PID_MAJOR_M         0x00000700  // Major Release Number
+#define LCD_PID_MINOR_M         0x0000003F  // Minor Release Number
+#define LCD_PID_MAJOR_S         8
+#define LCD_PID_MINOR_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CTL register.
+//
+//*****************************************************************************
+#define LCD_CTL_CLKDIV_M        0x0000FF00  // Clock Divisor
+#define LCD_CTL_UFLOWRST        0x00000002  // Underflow Restart
+#define LCD_CTL_LCDMODE         0x00000001  // LCD Mode Select
+#define LCD_CTL_CLKDIV_S        8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCTL register.
+//
+//*****************************************************************************
+#define LCD_LIDDCTL_DMACS       0x00000200  // CS0/CS1 Select for LIDD DMA
+                                            // Writes
+#define LCD_LIDDCTL_DMAEN       0x00000100  // LIDD DMA Enable
+#define LCD_LIDDCTL_CS1E1       0x00000080  // Chip Select 1 (CS1)/Enable 1(E1)
+                                            // Polarity Control
+#define LCD_LIDDCTL_CS0E0       0x00000040  // Chip Select 0 (CS0)/Enable 0
+                                            // (E0) Polarity Control
+#define LCD_LIDDCTL_WRDIRINV    0x00000020  // Write Strobe (WR) /Direction
+                                            // (DIR) Polarity Control
+#define LCD_LIDDCTL_RDEN        0x00000010  // Read Strobe (RD) /Direct Enable
+                                            // (EN) Polarity Control
+#define LCD_LIDDCTL_ALE         0x00000008  // Address Latch Enable (ALE)
+                                            // Polarity Control
+#define LCD_LIDDCTL_MODE_M      0x00000007  // LIDD Mode Select
+#define LCD_LIDDCTL_MODE_SYNCM68                                              \
+                                0x00000000  // Synchronous Motorola 6800 Mode
+#define LCD_LIDDCTL_MODE_ASYNCM68                                             \
+                                0x00000001  // Asynchronous Motorola 6800 Mode
+#define LCD_LIDDCTL_MODE_SYNCM80                                              \
+                                0x00000002  // Synchronous Intel 8080 mode
+#define LCD_LIDDCTL_MODE_ASYNCM80                                             \
+                                0x00000003  // Asynchronous Intel 8080 mode
+#define LCD_LIDDCTL_MODE_ASYNCHIT                                             \
+                                0x00000004  // Asynchronous Hitachi mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0CFG_WRSU_M   0xF8000000  // Write Strobe (WR) Set-Up Cycles
+#define LCD_LIDDCS0CFG_WRDUR_M  0x07E00000  // Write Strobe (WR) Duration
+                                            // Cycles
+#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000  // Write Strobe (WR) Hold cycles
+#define LCD_LIDDCS0CFG_RDSU_M   0x0001F000  // Read Strobe (RD) Set-Up cycles
+#define LCD_LIDDCS0CFG_RDDUR_M  0x00000FC0  // Read Strobe (RD) Duration cycles
+#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C  // Read Strobe (RD) Hold cycles
+#define LCD_LIDDCS0CFG_GAP_M    0x00000003  // Field value defines the number
+                                            // of LCDMCLK cycles (GAP +1)
+                                            // between the end of one CS0
+                                            // (LCDAC) device access and the
+                                            // start of another CS0 (LCDAC)
+                                            // device access unless the two
+                                            // accesses are both reads
+#define LCD_LIDDCS0CFG_WRSU_S   27
+#define LCD_LIDDCS0CFG_WRDUR_S  21
+#define LCD_LIDDCS0CFG_WRHOLD_S 17
+#define LCD_LIDDCS0CFG_RDSU_S   12
+#define LCD_LIDDCS0CFG_RDDUR_S  6
+#define LCD_LIDDCS0CFG_RDHOLD_S 2
+#define LCD_LIDDCS0CFG_GAP_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0ADDR_CS0ADDR_M                                             \
+                                0x0000FFFF  // LCD Address
+#define LCD_LIDDCS0ADDR_CS0ADDR_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0DATA_CS0DATA_M                                             \
+                                0x0000FFFF  // LCD Data Read/Write
+#define LCD_LIDDCS0DATA_CS0DATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1CFG_WRSU_M   0xF8000000  // Write Strobe (WR) Set-Up Cycles
+#define LCD_LIDDCS1CFG_WRDUR_M  0x07E00000  // Write Strobe (WR) Duration
+                                            // Cycles
+#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000  // Write Strobe (WR) Hold cycles
+#define LCD_LIDDCS1CFG_RDSU_M   0x0001F000  // Read Strobe (RD) Set-Up cycles
+#define LCD_LIDDCS1CFG_RDDUR_M  0x00000FC0  // Read Strobe (RD) Duration cycles
+#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C  // Read Strobe (RD) Hold cycles
+#define LCD_LIDDCS1CFG_GAP_M    0x00000003  // Field value defines the number
+                                            // of LCDMCLK cycles (GAP + 1)
+                                            // between the end of one CS1
+                                            // (LCDAC) device access and the
+                                            // start of another CS0 (LCDAC)
+                                            // device access unless the two
+                                            // accesses are both reads
+#define LCD_LIDDCS1CFG_WRSU_S   27
+#define LCD_LIDDCS1CFG_WRDUR_S  21
+#define LCD_LIDDCS1CFG_WRHOLD_S 17
+#define LCD_LIDDCS1CFG_RDSU_S   12
+#define LCD_LIDDCS1CFG_RDDUR_S  6
+#define LCD_LIDDCS1CFG_RDHOLD_S 2
+#define LCD_LIDDCS1CFG_GAP_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1ADDR_CS1ADDR_M                                             \
+                                0x0000FFFF  // LCD Address Bus
+#define LCD_LIDDCS1ADDR_CS1ADDR_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1DATA_CS0DATA_M                                             \
+                                0x0000FFFF  // LCD Data Read/Write Initiation
+#define LCD_LIDDCS1DATA_CS0DATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRCTL register.
+//
+//*****************************************************************************
+#define LCD_RASTRCTL_TFT24UPCK  0x04000000  // 24-bit TFT Mode Packing
+#define LCD_RASTRCTL_TFT24      0x02000000  // 24-Bit TFT Mode
+#define LCD_RASTRCTL_FRMBUFSZ   0x01000000  // Frame Buffer Select
+#define LCD_RASTRCTL_TFTMAP     0x00800000  // TFT Mode Alternate Signal
+                                            // Mapping for Palettized
+                                            // Framebuffer
+#define LCD_RASTRCTL_NIBMODE    0x00400000  // Nibble Mode
+#define LCD_RASTRCTL_PALMODE_M  0x00300000  // Pallette Loading Mode
+#define LCD_RASTRCTL_PALMODE_PALDAT                                           \
+                                0x00000000  // Palette and data loading, reset
+                                            // value
+#define LCD_RASTRCTL_PALMODE_PAL                                              \
+                                0x00100000  // Palette loading only
+#define LCD_RASTRCTL_PALMODE_DAT                                              \
+                                0x00200000  // Data loading only
+#define LCD_RASTRCTL_REQDLY_M   0x000FF000  // Palette Loading Delay
+#define LCD_RASTRCTL_MONO8B     0x00000200  // Mono 8-Bit
+#define LCD_RASTRCTL_RDORDER    0x00000100  // Raster Data Order Select
+#define LCD_RASTRCTL_LCDTFT     0x00000080  // LCD TFT
+#define LCD_RASTRCTL_LCDBW      0x00000002  // LCD Monochrome
+#define LCD_RASTRCTL_LCDEN      0x00000001  // LCD Controller Enable for Raster
+                                            // Operations
+#define LCD_RASTRCTL_REQDLY_S   12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM0
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM0_HBP_M     0xFF000000  // Horizontal Back Porch Lowbits
+#define LCD_RASTRTIM0_HFP_M     0x00FF0000  // Horizontal Front Porch Lowbits
+#define LCD_RASTRTIM0_HSW_M     0x0000FC00  // Horizontal Sync Pulse Width
+                                            // Lowbits
+#define LCD_RASTRTIM0_PPL_M     0x000003F0  // Pixels-per-line LSB[9:4]
+#define LCD_RASTRTIM0_MSBPPL    0x00000008  // Pixels-per-line MSB[10]
+#define LCD_RASTRTIM0_HBP_S     24
+#define LCD_RASTRTIM0_HFP_S     16
+#define LCD_RASTRTIM0_HSW_S     10
+#define LCD_RASTRTIM0_PPL_S     4
+#define LCD_RASTRTIM0_MSBPPL_S  3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM1
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM1_VBP_M     0xFF000000  // Vertical Back Porch
+#define LCD_RASTRTIM1_VFP_M     0x00FF0000  // Vertical Front Porch
+#define LCD_RASTRTIM1_VSW_M     0x0000FC00  // Vertical Sync Width Pulse
+#define LCD_RASTRTIM1_LPP_M     0x000003FF  // Lines Per Panel
+#define LCD_RASTRTIM1_VBP_S     24
+#define LCD_RASTRTIM1_VFP_S     16
+#define LCD_RASTRTIM1_VSW_S     10
+#define LCD_RASTRTIM1_LPP_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM2
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM2_HSW_M     0x78000000  // Bits 9:6 of the horizontal sync
+                                            // width field
+#define LCD_RASTRTIM2_MSBLPP    0x04000000  // MSB of Lines Per Panel
+#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000  // Hsync/Vsync Pixel Clock Control
+                                            // On/Off
+#define LCD_RASTRTIM2_PSYNCRF   0x01000000  // Program HSYNC/VSYNC Rise or Fall
+#define LCD_RASTRTIM2_INVOE     0x00800000  // Invert Output Enable
+#define LCD_RASTRTIM2_INVPXLCLK 0x00400000  // Invert Pixel Clock
+#define LCD_RASTRTIM2_IHS       0x00200000  // Invert Hysync
+#define LCD_RASTRTIM2_IVS       0x00100000  // Invert Vsync
+#define LCD_RASTRTIM2_ACBI_M    0x000F0000  // AC Bias Pins Transitions per
+                                            // Interrupt
+#define LCD_RASTRTIM2_ACBF_M    0x0000FF00  // AC Bias Pin Frequency
+#define LCD_RASTRTIM2_MSBHBP_M  0x00000030  // Bits 9:8 of the horizontal back
+                                            // porch field
+#define LCD_RASTRTIM2_MSBHFP_M  0x00000003  // Bits 9:8 of the horizontal front
+                                            // porch field
+#define LCD_RASTRTIM2_HSW_S     27
+#define LCD_RASTRTIM2_MSBLPP_S  26
+#define LCD_RASTRTIM2_ACBI_S    16
+#define LCD_RASTRTIM2_ACBF_S    8
+#define LCD_RASTRTIM2_MSBHBP_S  4
+#define LCD_RASTRTIM2_MSBHFP_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRSUBP1
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRSUBP1_SPEN     0x80000000  // Sub Panel Enable
+#define LCD_RASTRSUBP1_HOLS     0x20000000  // High or Low Signal
+#define LCD_RASTRSUBP1_LPPT_M   0x03FF0000  // Line Per Panel Threshold
+#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF  // Default Pixel Data LSB[15:0]
+#define LCD_RASTRSUBP1_LPPT_S   16
+#define LCD_RASTRSUBP1_DPDLSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRSUBP2
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRSUBP2_LPPTMSB  0x00000100  // Lines Per Panel Threshold Bit 10
+#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF  // Default Pixel Data MSB [23:16]
+#define LCD_RASTRSUBP2_DPDMSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACTL register.
+//
+//*****************************************************************************
+#define LCD_DMACTL_FIFORDY_M    0x00000700  // DMA FIFO threshold
+#define LCD_DMACTL_FIFORDY_8    0x00000000  // 8 words
+#define LCD_DMACTL_FIFORDY_16   0x00000100  // 16 words
+#define LCD_DMACTL_FIFORDY_32   0x00000200  // 32 words
+#define LCD_DMACTL_FIFORDY_64   0x00000300  // 64 words
+#define LCD_DMACTL_FIFORDY_128  0x00000400  // 128 words
+#define LCD_DMACTL_FIFORDY_256  0x00000500  // 256 words
+#define LCD_DMACTL_FIFORDY_512  0x00000600  // 512 words
+#define LCD_DMACTL_BURSTSZ_M    0x00000070  // Burst Size setting for DMA
+                                            // transfers (all DMA transfers are
+                                            // 32 bits wide):
+#define LCD_DMACTL_BURSTSZ_4    0x00000020  // burst size of 4
+#define LCD_DMACTL_BURSTSZ_8    0x00000030  // burst size of 8
+#define LCD_DMACTL_BURSTSZ_16   0x00000040  // burst size of 16
+#define LCD_DMACTL_BYTESWAP     0x00000008  // This bit controls the bytelane
+                                            // ordering of the data on the
+                                            // output of the DMA module
+#define LCD_DMACTL_BIGDEND      0x00000002  // Big Endian Enable
+#define LCD_DMACTL_FMODE        0x00000001  // Frame Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
+//
+//*****************************************************************************
+#define LCD_DMABAFB0_FB0BA_M    0xFFFFFFFC  // Frame Buffer 0 Base Address
+                                            // pointer
+#define LCD_DMABAFB0_FB0BA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
+//
+//*****************************************************************************
+#define LCD_DMACAFB0_FB0CA_M    0xFFFFFFFC  // Frame Buffer 0 Ceiling Address
+                                            // pointer
+#define LCD_DMACAFB0_FB0CA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
+//
+//*****************************************************************************
+#define LCD_DMABAFB1_FB1BA_M    0xFFFFFFFC  // Frame Buffer 1 Base Address
+                                            // pointer
+#define LCD_DMABAFB1_FB1BA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
+//
+//*****************************************************************************
+#define LCD_DMACAFB1_FB1CA_M    0xFFFFFFFC  // Frame Buffer 1 Ceiling Address
+                                            // pointer
+#define LCD_DMACAFB1_FB1CA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_SYSCFG register.
+//
+//*****************************************************************************
+#define LCD_SYSCFG_STDBY_M      0x00000030  // Standby Mode
+#define LCD_SYSCFG_STDBY_FORCE  0x00000000  // Force-standby mode: local
+                                            // initiator is unconditionally
+                                            // placed in standby state. Backup
+                                            // mode, for debug only
+#define LCD_SYSCFG_STDBY_NONE   0x00000010  // No-standby mode: local initiator
+                                            // is unconditionally placed out of
+                                            // standby state. Backup mode, for
+                                            // debug only
+#define LCD_SYSCFG_STDBY_SMART  0x00000020  // Smart-standby mode: local
+                                            // initiator standby status depends
+                                            // on local conditions, that is,
+                                            // the module's functional
+                                            // requirement from the initiator.
+                                            // IP module shall not generate
+                                            // (initiator-related) wakeup
+                                            // events
+#define LCD_SYSCFG_IDLEMODE_M   0x0000000C  // Idle Mode
+#define LCD_SYSCFG_IDLEMODE_FORCE                                             \
+                                0x00000000  // Force-idle mode: local target's
+                                            // idle state follows
+                                            // (acknowledges) the system's idle
+                                            // requests unconditionally, that
+                                            // is, regardless of the IP
+                                            // module's internal requirements.
+                                            // Backup mode, for debug only
+#define LCD_SYSCFG_IDLEMODE_NONE                                              \
+                                0x00000004  // No-idle mode: local target never
+                                            // enters idle state. Backup mode,
+                                            // for debug only
+#define LCD_SYSCFG_IDLEMODE_SMART                                             \
+                                0x00000008  // Smart-idle mode: local target's
+                                            // idle state eventually follows
+                                            // (acknowledges) the system's idle
+                                            // requests, depending on the IP
+                                            // module's internal requirements.
+                                            // IP module shall not generate
+                                            // (IRQ- or DMA-requestrelated)
+                                            // wakeup events
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RISSET register.
+//
+//*****************************************************************************
+#define LCD_RISSET_EOF1         0x00000200  // DMA End-of-Frame 1 Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_EOF0         0x00000100  // DMA End-of-Frame 0 Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_PALLOAD      0x00000040  // DMA Palette Loaded Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_FIFOU        0x00000020  // DMA FIFO Underflow Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_ACBS         0x00000008  // AC Bias Count Raw Interrupt
+                                            // Status and Set
+#define LCD_RISSET_SYNCS        0x00000004  // Frame Synchronization Lost Raw
+                                            // Interrupt Status and Set
+#define LCD_RISSET_RRASTRDONE   0x00000002  // Raster Mode Frame Done interrupt
+#define LCD_RISSET_DONE         0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled) Raw
+                                            // Interrupt Status and Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_MISCLR register.
+//
+//*****************************************************************************
+#define LCD_MISCLR_EOF1         0x00000200  // DMA End-of-Frame 1 Enabled
+                                            // Interrupt and Clear
+#define LCD_MISCLR_EOF0         0x00000100  // DMA End-of-Frame 0 Raw Interrupt
+                                            // and Clear
+#define LCD_MISCLR_PALLOAD      0x00000040  // DMA Palette Loaded Enabled
+                                            // Interrupt and Clear
+#define LCD_MISCLR_FIFOU        0x00000020  // DMA FIFO Underflow Enabled
+                                            // Interrupt and Clear
+#define LCD_MISCLR_ACBS         0x00000008  // AC Bias Count Enabled Interrupt
+                                            // and Clear
+#define LCD_MISCLR_SYNCS        0x00000004  // Frame Synchronization Lost
+                                            // Enabled Interrupt and Clear
+#define LCD_MISCLR_RRASTRDONE   0x00000002  // Raster Mode Frame Done interrupt
+#define LCD_MISCLR_DONE         0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled)
+                                            // Enabled Interrupt and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_IM register.
+//
+//*****************************************************************************
+#define LCD_IM_EOF1             0x00000200  // DMA End-of-Frame 1 Interrupt
+                                            // Enable Set
+#define LCD_IM_EOF0             0x00000100  // DMA End-of-Frame 0 Interrupt
+                                            // Enable Set
+#define LCD_IM_PALLOAD          0x00000040  // DMA Palette Loaded Interrupt
+                                            // Enable Set
+#define LCD_IM_FIFOU            0x00000020  // DMA FIFO Underflow Interrupt
+                                            // Enable Set
+#define LCD_IM_ACBS             0x00000008  // AC Bias Count Interrupt Enable
+                                            // Set
+#define LCD_IM_SYNCS            0x00000004  // Frame Synchronization Lost
+                                            // Interrupt Enable Set
+#define LCD_IM_RRASTRDONE       0x00000002  // Raster Mode Frame Done Interrupt
+                                            // Enable Set
+#define LCD_IM_DONE             0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled)
+                                            // Interrupt Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_IENC register.
+//
+//*****************************************************************************
+#define LCD_IENC_EOF1           0x00000200  // DMA End-of-Frame 1 Interrupt
+                                            // Enable Clear
+#define LCD_IENC_EOF0           0x00000100  // DMA End-of-Frame 0 Interrupt
+                                            // Enable Clear
+#define LCD_IENC_PALLOAD        0x00000040  // DMA Palette Loaded Interrupt
+                                            // Enable Clear
+#define LCD_IENC_FIFOU          0x00000020  // DMA FIFO Underflow Interrupt
+                                            // Enable Clear
+#define LCD_IENC_ACBS           0x00000008  // AC Bias Count Interrupt Enable
+                                            // Clear
+#define LCD_IENC_SYNCS          0x00000004  // Frame Synchronization Lost
+                                            // Interrupt Enable Clear
+#define LCD_IENC_RRASTRDONE     0x00000002  // Raster Mode Frame Done Interrupt
+                                            // Enable Clear
+#define LCD_IENC_DONE           0x00000001  // Raster or LIDD Frame Done
+                                            // (shared, depends on whether
+                                            // Raster or LIDD mode enabled)
+                                            // Interrupt Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CLKEN register.
+//
+//*****************************************************************************
+#define LCD_CLKEN_DMA           0x00000004  // DMA Clock Enable
+#define LCD_CLKEN_LIDD          0x00000002  // LIDD Submodule Clock Enable
+#define LCD_CLKEN_CORE          0x00000001  // LCD Core Clock Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CLKRESET register.
+//
+//*****************************************************************************
+#define LCD_CLKRESET_MAIN       0x00000008  // Software Reset for the entire
+                                            // LCD module
+#define LCD_CLKRESET_DMA        0x00000004  // Software Reset for the DMA
+                                            // submodule
+#define LCD_CLKRESET_LIDD       0x00000002  // Software Reset for the LIDD
+                                            // submodule (character displays)
+#define LCD_CLKRESET_CORE       0x00000001  // Software Reset for the Core,
+                                            // which encompasses the Raster
+                                            // Active Matrix and Passive Matrix
+                                            // logic
+
+#endif // __HW_LCD_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_memmap.h b/bsp/tm4c129x/libraries/inc/hw_memmap.h
new file mode 100644
index 0000000000..b604c6cea3
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_memmap.h
@@ -0,0 +1,151 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of the device.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE              0x00000000  // FLASH memory
+#define SRAM_BASE               0x20000000  // SRAM memory
+#define WATCHDOG0_BASE          0x40000000  // Watchdog0
+#define WATCHDOG1_BASE          0x40001000  // Watchdog1
+#define GPIO_PORTA_BASE         0x40004000  // GPIO Port A
+#define GPIO_PORTB_BASE         0x40005000  // GPIO Port B
+#define GPIO_PORTC_BASE         0x40006000  // GPIO Port C
+#define GPIO_PORTD_BASE         0x40007000  // GPIO Port D
+#define SSI0_BASE               0x40008000  // SSI0
+#define SSI1_BASE               0x40009000  // SSI1
+#define SSI2_BASE               0x4000A000  // SSI2
+#define SSI3_BASE               0x4000B000  // SSI3
+#define UART0_BASE              0x4000C000  // UART0
+#define UART1_BASE              0x4000D000  // UART1
+#define UART2_BASE              0x4000E000  // UART2
+#define UART3_BASE              0x4000F000  // UART3
+#define UART4_BASE              0x40010000  // UART4
+#define UART5_BASE              0x40011000  // UART5
+#define UART6_BASE              0x40012000  // UART6
+#define UART7_BASE              0x40013000  // UART7
+#define I2C0_BASE               0x40020000  // I2C0
+#define I2C1_BASE               0x40021000  // I2C1
+#define I2C2_BASE               0x40022000  // I2C2
+#define I2C3_BASE               0x40023000  // I2C3
+#define GPIO_PORTE_BASE         0x40024000  // GPIO Port E
+#define GPIO_PORTF_BASE         0x40025000  // GPIO Port F
+#define GPIO_PORTG_BASE         0x40026000  // GPIO Port G
+#define GPIO_PORTH_BASE         0x40027000  // GPIO Port H
+#define PWM0_BASE               0x40028000  // Pulse Width Modulator (PWM)
+#define PWM1_BASE               0x40029000  // Pulse Width Modulator (PWM)
+#define QEI0_BASE               0x4002C000  // QEI0
+#define QEI1_BASE               0x4002D000  // QEI1
+#define TIMER0_BASE             0x40030000  // Timer0
+#define TIMER1_BASE             0x40031000  // Timer1
+#define TIMER2_BASE             0x40032000  // Timer2
+#define TIMER3_BASE             0x40033000  // Timer3
+#define TIMER4_BASE             0x40034000  // Timer4
+#define TIMER5_BASE             0x40035000  // Timer5
+#define WTIMER0_BASE            0x40036000  // Wide Timer0
+#define WTIMER1_BASE            0x40037000  // Wide Timer1
+#define ADC0_BASE               0x40038000  // ADC0
+#define ADC1_BASE               0x40039000  // ADC1
+#define COMP_BASE               0x4003C000  // Analog comparators
+#define GPIO_PORTJ_BASE         0x4003D000  // GPIO Port J
+#define CAN0_BASE               0x40040000  // CAN0
+#define CAN1_BASE               0x40041000  // CAN1
+#define WTIMER2_BASE            0x4004C000  // Wide Timer2
+#define WTIMER3_BASE            0x4004D000  // Wide Timer3
+#define WTIMER4_BASE            0x4004E000  // Wide Timer4
+#define WTIMER5_BASE            0x4004F000  // Wide Timer5
+#define USB0_BASE               0x40050000  // USB 0 Controller
+#define GPIO_PORTA_AHB_BASE     0x40058000  // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE     0x40059000  // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE     0x4005A000  // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE     0x4005B000  // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE     0x4005C000  // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE     0x4005D000  // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE     0x4005E000  // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE     0x4005F000  // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE     0x40060000  // GPIO Port J (high speed)
+#define GPIO_PORTK_BASE         0x40061000  // GPIO Port K
+#define GPIO_PORTL_BASE         0x40062000  // GPIO Port L
+#define GPIO_PORTM_BASE         0x40063000  // GPIO Port M
+#define GPIO_PORTN_BASE         0x40064000  // GPIO Port N
+#define GPIO_PORTP_BASE         0x40065000  // GPIO Port P
+#define GPIO_PORTQ_BASE         0x40066000  // GPIO Port Q
+#define GPIO_PORTR_BASE         0x40067000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define GPIO_PORTS_BASE         0x40068000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define GPIO_PORTT_BASE         0x40069000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define EEPROM_BASE             0x400AF000  // EEPROM memory
+#define ONEWIRE0_BASE           0x400B6000  // 1-Wire Master Module
+#define I2C8_BASE               0x400B8000  // I2C8
+#define I2C9_BASE               0x400B9000  // I2C9
+#define I2C4_BASE               0x400C0000  // I2C4
+#define I2C5_BASE               0x400C1000  // I2C5
+#define I2C6_BASE               0x400C2000  // I2C6
+#define I2C7_BASE               0x400C3000  // I2C7
+#define EPI0_BASE               0x400D0000  // EPI0
+#define TIMER6_BASE             0x400E0000  // General-Purpose Timers
+#define TIMER7_BASE             0x400E1000  // General-Purpose Timers
+#define EMAC0_BASE              0x400EC000  // Ethernet Controller
+#define SYSEXC_BASE             0x400F9000  // System Exception Module
+#define HIB_BASE                0x400FC000  // Hibernation Module
+#define FLASH_CTRL_BASE         0x400FD000  // FLASH Controller
+#define SYSCTL_BASE             0x400FE000  // System Control
+#define UDMA_BASE               0x400FF000  // uDMA Controller
+#define CCM0_BASE               0x44030000  // Cyclical Redundancy Check (CRC)
+#define SHAMD5_BASE             0x44034000  // SHA/MD5 Accelerator
+#define AES_BASE                0x44036000  // Advance Encryption
+                                            // Hardware-Accelerated Module
+#define DES_BASE                0x44038000  // Data Encryption Standard
+                                            // Accelerator (DES)
+#define LCD0_BASE               0x44050000  // LCD Controller
+#define ITM_BASE                0xE0000000  // Instrumentation Trace Macrocell
+#define DWT_BASE                0xE0001000  // Data Watchpoint and Trace
+#define FPB_BASE                0xE0002000  // FLASH Patch and Breakpoint
+#define NVIC_BASE               0xE000E000  // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE               0xE0040000  // Trace Port Interface Unit
+
+#endif // __HW_MEMMAP_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_nvic.h b/bsp/tm4c129x/libraries/inc/hw_nvic.h
new file mode 100644
index 0000000000..7811347721
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_nvic.h
@@ -0,0 +1,1414 @@
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_ACTLR              0xE000E008  // Auxiliary Control
+#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status
+                                            // Register
+#define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
+#define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
+#define NVIC_EN0                0xE000E100  // Interrupt 0-31 Set Enable
+#define NVIC_EN1                0xE000E104  // Interrupt 32-63 Set Enable
+#define NVIC_EN2                0xE000E108  // Interrupt 64-95 Set Enable
+#define NVIC_EN3                0xE000E10C  // Interrupt 96-127 Set Enable
+#define NVIC_EN4                0xE000E110  // Interrupt 128-159 Set Enable
+#define NVIC_DIS0               0xE000E180  // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1               0xE000E184  // Interrupt 32-63 Clear Enable
+#define NVIC_DIS2               0xE000E188  // Interrupt 64-95 Clear Enable
+#define NVIC_DIS3               0xE000E18C  // Interrupt 96-127 Clear Enable
+#define NVIC_DIS4               0xE000E190  // Interrupt 128-159 Clear Enable
+#define NVIC_PEND0              0xE000E200  // Interrupt 0-31 Set Pending
+#define NVIC_PEND1              0xE000E204  // Interrupt 32-63 Set Pending
+#define NVIC_PEND2              0xE000E208  // Interrupt 64-95 Set Pending
+#define NVIC_PEND3              0xE000E20C  // Interrupt 96-127 Set Pending
+#define NVIC_PEND4              0xE000E210  // Interrupt 128-159 Set Pending
+#define NVIC_UNPEND0            0xE000E280  // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1            0xE000E284  // Interrupt 32-63 Clear Pending
+#define NVIC_UNPEND2            0xE000E288  // Interrupt 64-95 Clear Pending
+#define NVIC_UNPEND3            0xE000E28C  // Interrupt 96-127 Clear Pending
+#define NVIC_UNPEND4            0xE000E290  // Interrupt 128-159 Clear Pending
+#define NVIC_ACTIVE0            0xE000E300  // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1            0xE000E304  // Interrupt 32-63 Active Bit
+#define NVIC_ACTIVE2            0xE000E308  // Interrupt 64-95 Active Bit
+#define NVIC_ACTIVE3            0xE000E30C  // Interrupt 96-127 Active Bit
+#define NVIC_ACTIVE4            0xE000E310  // Interrupt 128-159 Active Bit
+#define NVIC_PRI0               0xE000E400  // Interrupt 0-3 Priority
+#define NVIC_PRI1               0xE000E404  // Interrupt 4-7 Priority
+#define NVIC_PRI2               0xE000E408  // Interrupt 8-11 Priority
+#define NVIC_PRI3               0xE000E40C  // Interrupt 12-15 Priority
+#define NVIC_PRI4               0xE000E410  // Interrupt 16-19 Priority
+#define NVIC_PRI5               0xE000E414  // Interrupt 20-23 Priority
+#define NVIC_PRI6               0xE000E418  // Interrupt 24-27 Priority
+#define NVIC_PRI7               0xE000E41C  // Interrupt 28-31 Priority
+#define NVIC_PRI8               0xE000E420  // Interrupt 32-35 Priority
+#define NVIC_PRI9               0xE000E424  // Interrupt 36-39 Priority
+#define NVIC_PRI10              0xE000E428  // Interrupt 40-43 Priority
+#define NVIC_PRI11              0xE000E42C  // Interrupt 44-47 Priority
+#define NVIC_PRI12              0xE000E430  // Interrupt 48-51 Priority
+#define NVIC_PRI13              0xE000E434  // Interrupt 52-55 Priority
+#define NVIC_PRI14              0xE000E438  // Interrupt 56-59 Priority
+#define NVIC_PRI15              0xE000E43C  // Interrupt 60-63 Priority
+#define NVIC_PRI16              0xE000E440  // Interrupt 64-67 Priority
+#define NVIC_PRI17              0xE000E444  // Interrupt 68-71 Priority
+#define NVIC_PRI18              0xE000E448  // Interrupt 72-75 Priority
+#define NVIC_PRI19              0xE000E44C  // Interrupt 76-79 Priority
+#define NVIC_PRI20              0xE000E450  // Interrupt 80-83 Priority
+#define NVIC_PRI21              0xE000E454  // Interrupt 84-87 Priority
+#define NVIC_PRI22              0xE000E458  // Interrupt 88-91 Priority
+#define NVIC_PRI23              0xE000E45C  // Interrupt 92-95 Priority
+#define NVIC_PRI24              0xE000E460  // Interrupt 96-99 Priority
+#define NVIC_PRI25              0xE000E464  // Interrupt 100-103 Priority
+#define NVIC_PRI26              0xE000E468  // Interrupt 104-107 Priority
+#define NVIC_PRI27              0xE000E46C  // Interrupt 108-111 Priority
+#define NVIC_PRI28              0xE000E470  // Interrupt 112-115 Priority
+#define NVIC_PRI29              0xE000E474  // Interrupt 116-119 Priority
+#define NVIC_PRI30              0xE000E478  // Interrupt 120-123 Priority
+#define NVIC_PRI31              0xE000E47C  // Interrupt 124-127 Priority
+#define NVIC_PRI32              0xE000E480  // Interrupt 128-131 Priority
+#define NVIC_PRI33              0xE000E484  // Interrupt 132-135 Priority
+#define NVIC_PRI34              0xE000E488  // Interrupt 136-139 Priority
+#define NVIC_CPUID              0xE000ED00  // CPU ID Base
+#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control and State
+#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset
+#define NVIC_APINT              0xE000ED0C  // Application Interrupt and Reset
+                                            // Control
+#define NVIC_SYS_CTRL           0xE000ED10  // System Control
+#define NVIC_CFG_CTRL           0xE000ED14  // Configuration and Control
+#define NVIC_SYS_PRI1           0xE000ED18  // System Handler Priority 1
+#define NVIC_SYS_PRI2           0xE000ED1C  // System Handler Priority 2
+#define NVIC_SYS_PRI3           0xE000ED20  // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
+#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status
+#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status
+#define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
+#define NVIC_MM_ADDR            0xE000ED34  // Memory Management Fault Address
+#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address
+#define NVIC_CPAC               0xE000ED88  // Coprocessor Access Control
+#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type
+#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control
+#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number
+#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address
+#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1          0xE000EDA4  // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1          0xE000EDA8  // MPU Region Attribute and Size
+                                            // Alias 1
+#define NVIC_MPU_BASE2          0xE000EDAC  // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2          0xE000EDB0  // MPU Region Attribute and Size
+                                            // Alias 2
+#define NVIC_MPU_BASE3          0xE000EDB4  // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3          0xE000EDB8  // MPU Region Attribute and Size
+                                            // Alias 3
+#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg
+#define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
+#define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt
+#define NVIC_FPCC               0xE000EF34  // Floating-Point Context Control
+#define NVIC_FPCA               0xE000EF38  // Floating-Point Context Address
+#define NVIC_FPDSC              0xE000EF3C  // Floating-Point Default Status
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP      0x00000200  // Disable Out-Of-Order Floating
+                                            // Point
+#define NVIC_ACTLR_DISFPCA      0x00000100  // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M          0x000007FF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M         0x000007FF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M        0x000007FF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M      0x000007FF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M      0x000007FF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M       0xE0000000  // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M       0x00E00000  // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M       0x0000E000  // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M       0x000000E0  // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S       29
+#define NVIC_PRI14_INTC_S       21
+#define NVIC_PRI14_INTB_S       13
+#define NVIC_PRI14_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M       0xE0000000  // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M       0x00E00000  // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M       0x0000E000  // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M       0x000000E0  // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S       29
+#define NVIC_PRI15_INTC_S       21
+#define NVIC_PRI15_INTB_S       13
+#define NVIC_PRI15_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M       0xE0000000  // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M       0x00E00000  // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M       0x0000E000  // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M       0x000000E0  // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S       29
+#define NVIC_PRI16_INTC_S       21
+#define NVIC_PRI16_INTB_S       13
+#define NVIC_PRI16_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M       0xE0000000  // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M       0x00E00000  // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M       0x0000E000  // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M       0x000000E0  // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S       29
+#define NVIC_PRI17_INTC_S       21
+#define NVIC_PRI17_INTB_S       13
+#define NVIC_PRI17_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M       0xE0000000  // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M       0x00E00000  // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M       0x0000E000  // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M       0x000000E0  // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S       29
+#define NVIC_PRI18_INTC_S       21
+#define NVIC_PRI18_INTB_S       13
+#define NVIC_PRI18_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M       0xE0000000  // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M       0x00E00000  // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M       0x0000E000  // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M       0x000000E0  // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S       29
+#define NVIC_PRI19_INTC_S       21
+#define NVIC_PRI19_INTB_S       13
+#define NVIC_PRI19_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M       0xE0000000  // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M       0x00E00000  // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M       0x0000E000  // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M       0x000000E0  // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S       29
+#define NVIC_PRI20_INTC_S       21
+#define NVIC_PRI20_INTB_S       13
+#define NVIC_PRI20_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M       0xE0000000  // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M       0x00E00000  // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M       0x0000E000  // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M       0x000000E0  // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S       29
+#define NVIC_PRI21_INTC_S       21
+#define NVIC_PRI21_INTB_S       13
+#define NVIC_PRI21_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M       0xE0000000  // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M       0x00E00000  // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M       0x0000E000  // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M       0x000000E0  // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S       29
+#define NVIC_PRI22_INTC_S       21
+#define NVIC_PRI22_INTB_S       13
+#define NVIC_PRI22_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M       0xE0000000  // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M       0x00E00000  // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M       0x0000E000  // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M       0x000000E0  // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S       29
+#define NVIC_PRI23_INTC_S       21
+#define NVIC_PRI23_INTB_S       13
+#define NVIC_PRI23_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M       0xE0000000  // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M       0x00E00000  // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M       0x0000E000  // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M       0x000000E0  // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S       29
+#define NVIC_PRI24_INTC_S       21
+#define NVIC_PRI24_INTB_S       13
+#define NVIC_PRI24_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M       0xE0000000  // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M       0x00E00000  // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M       0x0000E000  // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M       0x000000E0  // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S       29
+#define NVIC_PRI25_INTC_S       21
+#define NVIC_PRI25_INTB_S       13
+#define NVIC_PRI25_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M       0xE0000000  // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M       0x00E00000  // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M       0x0000E000  // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M       0x000000E0  // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S       29
+#define NVIC_PRI26_INTC_S       21
+#define NVIC_PRI26_INTB_S       13
+#define NVIC_PRI26_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M       0xE0000000  // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M       0x00E00000  // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M       0x0000E000  // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M       0x000000E0  // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S       29
+#define NVIC_PRI27_INTC_S       21
+#define NVIC_PRI27_INTB_S       13
+#define NVIC_PRI27_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M       0xE0000000  // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M       0x00E00000  // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M       0x0000E000  // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M       0x000000E0  // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S       29
+#define NVIC_PRI28_INTC_S       21
+#define NVIC_PRI28_INTB_S       13
+#define NVIC_PRI28_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M       0xE0000000  // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M       0x00E00000  // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M       0x0000E000  // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M       0x000000E0  // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S       29
+#define NVIC_PRI29_INTC_S       21
+#define NVIC_PRI29_INTB_S       13
+#define NVIC_PRI29_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M       0xE0000000  // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M       0x00E00000  // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M       0x0000E000  // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M       0x000000E0  // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S       29
+#define NVIC_PRI30_INTC_S       21
+#define NVIC_PRI30_INTB_S       13
+#define NVIC_PRI30_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M       0xE0000000  // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M       0x00E00000  // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M       0x0000E000  // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M       0x000000E0  // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S       29
+#define NVIC_PRI31_INTC_S       21
+#define NVIC_PRI31_INTB_S       13
+#define NVIC_PRI31_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M       0xE0000000  // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M       0x00E00000  // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M       0x0000E000  // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M       0x000000E0  // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S       29
+#define NVIC_PRI32_INTC_S       21
+#define NVIC_PRI32_INTB_S       13
+#define NVIC_PRI32_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M       0xE0000000  // Interrupt Priority for Interrupt
+                                            // [4n+3]
+#define NVIC_PRI33_INTC_M       0x00E00000  // Interrupt Priority for Interrupt
+                                            // [4n+2]
+#define NVIC_PRI33_INTB_M       0x0000E000  // Interrupt Priority for Interrupt
+                                            // [4n+1]
+#define NVIC_PRI33_INTA_M       0x000000E0  // Interrupt Priority for Interrupt
+                                            // [4n]
+#define NVIC_PRI33_INTD_S       29
+#define NVIC_PRI33_INTC_S       21
+#define NVIC_PRI33_INTB_S       13
+#define NVIC_PRI33_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M       0xE0000000  // Interrupt Priority for Interrupt
+                                            // [4n+3]
+#define NVIC_PRI34_INTC_M       0x00E00000  // Interrupt Priority for Interrupt
+                                            // [4n+2]
+#define NVIC_PRI34_INTB_M       0x0000E000  // Interrupt Priority for Interrupt
+                                            // [4n+1]
+#define NVIC_PRI34_INTA_M       0x000000E0  // Interrupt Priority for Interrupt
+                                            // [4n]
+#define NVIC_PRI34_INTD_S       29
+#define NVIC_PRI34_INTC_S       21
+#define NVIC_PRI34_INTB_S       13
+#define NVIC_PRI34_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM4   0x0000C240  // Cortex-M4 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI                                             \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD                                            \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM                                             \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS                                             \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG                                             \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC                                             \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV                                           \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK                                            \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_OFFSET_M    0xFFFFFC00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP                                              \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000  // Bus Fault on Floating-Point Lazy
+                                            // State Preservation
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020  // Memory Management Fault on
+                                            // Floating-Point Lazy State
+                                            // Preservation
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M        0x00C00000  // CP11 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP11_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP11_PRIV     0x00400000  // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL     0x00C00000  // Full Access
+#define NVIC_CPAC_CP10_M        0x00300000  // CP10 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP10_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP10_PRIV     0x00100000  // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL     0x00300000  // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3     0x00000800  // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4     0x00001000  // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E  // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010  // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K   0x00000012  // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K   0x00000014  // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K   0x00000016  // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K   0x00000018  // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K  0x0000001A  // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K  0x0000001C  // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K  0x0000001E  // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020  // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022  // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024  // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M   0x00000026  // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M   0x00000028  // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M   0x0000002A  // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M   0x0000002C  // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M  0x0000002E  // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M  0x00000030  // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M  0x00000032  // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034  // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036  // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038  // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST                                              \
+                                0x02000000  // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST                                             \
+                                0x01000000  // Core has executed insruction
+                                            // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL                                             \
+                                0x00000020  // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x000000FF  // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN         0x80000000  // Automatic State Preservation
+                                            // Enable
+#define NVIC_FPCC_LSPEN         0x40000000  // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY        0x00000100  // Monitor Ready
+#define NVIC_FPCC_BFRDY         0x00000040  // Bus Fault Ready
+#define NVIC_FPCC_MMRDY         0x00000020  // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY         0x00000010  // Hard Fault Ready
+#define NVIC_FPCC_THREAD        0x00000008  // Thread Mode
+#define NVIC_FPCC_USER          0x00000002  // User Privilege Level
+#define NVIC_FPCC_LSPACT        0x00000001  // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M     0xFFFFFFF8  // Address
+#define NVIC_FPCA_ADDRESS_S     3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP          0x04000000  // AHP Bit Default
+#define NVIC_FPDSC_DN           0x02000000  // DN Bit Default
+#define NVIC_FPDSC_FZ           0x01000000  // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M      0x00C00000  // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN     0x00000000  // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP     0x00400000  // Round towards Plus Infinity (RP)
+                                            // mode
+#define NVIC_FPDSC_RMODE_RM     0x00800000  // Round towards Minus Infinity
+                                            // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ     0x00C00000  // Round towards Zero (RZ) mode
+
+#endif // __HW_NVIC_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_pwm.h b/bsp/tm4c129x/libraries/inc/hw_pwm.h
new file mode 100644
index 0000000000..0ad6bf6284
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_pwm.h
@@ -0,0 +1,1885 @@
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL               0x00000000  // PWM Master Control
+#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync
+#define PWM_O_ENABLE            0x00000008  // PWM Output Enable
+#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion
+#define PWM_O_FAULT             0x00000010  // PWM Output Fault
+#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable
+#define PWM_O_RIS               0x00000018  // PWM Raw Interrupt Status
+#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status and Clear
+#define PWM_O_STATUS            0x00000020  // PWM Status
+#define PWM_O_FAULTVAL          0x00000024  // PWM Fault Condition Value
+#define PWM_O_ENUPD             0x00000028  // PWM Enable Update
+#define PWM_O_0_CTL             0x00000040  // PWM0 Control
+#define PWM_O_0_INTEN           0x00000044  // PWM0 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_0_RIS             0x00000048  // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC             0x0000004C  // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD            0x00000050  // PWM0 Load
+#define PWM_O_0_COUNT           0x00000054  // PWM0 Counter
+#define PWM_O_0_CMPA            0x00000058  // PWM0 Compare A
+#define PWM_O_0_CMPB            0x0000005C  // PWM0 Compare B
+#define PWM_O_0_GENA            0x00000060  // PWM0 Generator A Control
+#define PWM_O_0_GENB            0x00000064  // PWM0 Generator B Control
+#define PWM_O_0_DBCTL           0x00000068  // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE          0x0000006C  // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL          0x00000070  // PWM0 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0         0x00000074  // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1         0x00000078  // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER       0x0000007C  // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL             0x00000080  // PWM1 Control
+#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_1_RIS             0x00000088  // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC             0x0000008C  // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD            0x00000090  // PWM1 Load
+#define PWM_O_1_COUNT           0x00000094  // PWM1 Counter
+#define PWM_O_1_CMPA            0x00000098  // PWM1 Compare A
+#define PWM_O_1_CMPB            0x0000009C  // PWM1 Compare B
+#define PWM_O_1_GENA            0x000000A0  // PWM1 Generator A Control
+#define PWM_O_1_GENB            0x000000A4  // PWM1 Generator B Control
+#define PWM_O_1_DBCTL           0x000000A8  // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE          0x000000AC  // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL          0x000000B0  // PWM1 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0         0x000000B4  // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1         0x000000B8  // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER       0x000000BC  // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL             0x000000C0  // PWM2 Control
+#define PWM_O_2_INTEN           0x000000C4  // PWM2 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_2_RIS             0x000000C8  // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC             0x000000CC  // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD            0x000000D0  // PWM2 Load
+#define PWM_O_2_COUNT           0x000000D4  // PWM2 Counter
+#define PWM_O_2_CMPA            0x000000D8  // PWM2 Compare A
+#define PWM_O_2_CMPB            0x000000DC  // PWM2 Compare B
+#define PWM_O_2_GENA            0x000000E0  // PWM2 Generator A Control
+#define PWM_O_2_GENB            0x000000E4  // PWM2 Generator B Control
+#define PWM_O_2_DBCTL           0x000000E8  // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE          0x000000EC  // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL          0x000000F0  // PWM2 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0         0x000000F4  // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1         0x000000F8  // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER       0x000000FC  // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL             0x00000100  // PWM3 Control
+#define PWM_O_3_INTEN           0x00000104  // PWM3 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_3_RIS             0x00000108  // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC             0x0000010C  // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD            0x00000110  // PWM3 Load
+#define PWM_O_3_COUNT           0x00000114  // PWM3 Counter
+#define PWM_O_3_CMPA            0x00000118  // PWM3 Compare A
+#define PWM_O_3_CMPB            0x0000011C  // PWM3 Compare B
+#define PWM_O_3_GENA            0x00000120  // PWM3 Generator A Control
+#define PWM_O_3_GENB            0x00000124  // PWM3 Generator B Control
+#define PWM_O_3_DBCTL           0x00000128  // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE          0x0000012C  // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL          0x00000130  // PWM3 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0         0x00000134  // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1         0x00000138  // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER       0x0000013C  // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN          0x00000800  // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0        0x00000804  // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1        0x00000808  // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN          0x00000880  // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0        0x00000884  // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1        0x00000888  // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN          0x00000900  // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0        0x00000904  // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1        0x00000908  // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN          0x00000980  // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0        0x00000984  // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1        0x00000988  // PWM3 Fault Status 1
+#define PWM_O_PP                0x00000FC0  // PWM Peripheral Properties
+#define PWM_O_CC                0x00000FC8  // PWM Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // MnPWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // MnPWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // MnPWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // MnPWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // MnPWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // MnPWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // MnPWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // MnPWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert MnPWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert MnPWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert MnPWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert MnPWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert MnPWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert MnPWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert MnPWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert MnPWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // MnPWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // MnPWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // MnPWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // MnPWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // MnPWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // MnPWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // MnPWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // MnPWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // MnPWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // MnPWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // MnPWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // MnPWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // MnPWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // MnPWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // MnPWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // MnPWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // MnPWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // MnPWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // MnPWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // MnPWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // MnPWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // MnPWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // MnPWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // MnPWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_0_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_0_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_0_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_0_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_0_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_0_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_0_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_0_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_0_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_0_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_0_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_0_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_0_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_0_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_0_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_0_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_0_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_0_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_0_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_0_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_0_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_0_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_1_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_1_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_1_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_1_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_1_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_1_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_1_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_1_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_1_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_1_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_1_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_1_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_1_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_1_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_1_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_1_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_1_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_1_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_1_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_1_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_1_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_2_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_2_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_2_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_2_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_2_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_2_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_2_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_2_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_2_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_2_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_2_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_2_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_2_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_2_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_2_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_2_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_2_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_2_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_2_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_2_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_2_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_2_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_3_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_3_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_3_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_3_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_3_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_3_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_3_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_3_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_3_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_3_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_3_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_3_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_3_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_3_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_3_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_3_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_3_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_3_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_3_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_3_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_3_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_3_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_3_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_3_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_GCNT_M           0x0000000F  // Generators
+#define PWM_PP_FCNT_M           0x000000F0  // Fault Inputs (per PWM unit)
+#define PWM_PP_ESYNC            0x00000100  // Extended Synchronization
+#define PWM_PP_EFAULT           0x00000200  // Extended Fault
+#define PWM_PP_ONE              0x00000400  // One-Shot Mode
+#define PWM_PP_GCNT_S           0
+#define PWM_PP_FCNT_S           4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CC register.
+//
+//*****************************************************************************
+#define PWM_CC_USEPWM           0x00000100  // Use PWM Clock Divisor
+#define PWM_CC_PWMDIV_M         0x00000007  // PWM Clock Divider
+#define PWM_CC_PWMDIV_2         0x00000000  // /2
+#define PWM_CC_PWMDIV_4         0x00000001  // /4
+#define PWM_CC_PWMDIV_8         0x00000002  // /8
+#define PWM_CC_PWMDIV_16        0x00000003  // /16
+#define PWM_CC_PWMDIV_32        0x00000004  // /32
+#define PWM_CC_PWMDIV_64        0x00000005  // /64
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL             0x00000000  // Gen Control Reg
+#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg
+#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg
+#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg
+#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg
+#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg
+#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg
+#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0         0x00000034  // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1         0x00000038  // Digital comparator condition
+#define PWM_O_X_MINFLTPER       0x0000003C  // Fault minimum period extension
+#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base
+#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base
+#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
+#define PWM_GEN_3_OFFSET        0x00000100  // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_X_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_X_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_X_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_X_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_X_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN          0x00000000  // Fault logic sense
+#define PWM_O_X_FLTSTAT0        0x00000004  // Pin and comparator status
+#define PWM_O_X_FLTSTAT1        0x00000008  // Digital comparator status
+#define PWM_EXT_0_OFFSET        0x00000800  // PWM0 extended base
+#define PWM_EXT_1_OFFSET        0x00000880  // PWM1 extended base
+#define PWM_EXT_2_OFFSET        0x00000900  // PWM2 extended base
+#define PWM_EXT_3_OFFSET        0x00000980  // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+#endif // __HW_PWM_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_qei.h b/bsp/tm4c129x/libraries/inc/hw_qei.h
new file mode 100644
index 0000000000..693596805d
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_qei.h
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL               0x00000000  // QEI Control
+#define QEI_O_STAT              0x00000004  // QEI Status
+#define QEI_O_POS               0x00000008  // QEI Position
+#define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
+#define QEI_O_LOAD              0x00000010  // QEI Timer Load
+#define QEI_O_TIME              0x00000014  // QEI Timer
+#define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
+#define QEI_O_SPEED             0x0000001C  // QEI Velocity
+#define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
+#define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
+#define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+#endif // __HW_QEI_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_shamd5.h b/bsp/tm4c129x/libraries/inc/hw_shamd5.h
new file mode 100644
index 0000000000..bdb31cd87c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_shamd5.h
@@ -0,0 +1,548 @@
+//*****************************************************************************
+//
+// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware.
+//
+// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SHAMD5_H__
+#define __HW_SHAMD5_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SHA/MD5 register offsets.
+//
+//*****************************************************************************
+#define SHAMD5_O_ODIGEST_A      0x00000000  // SHA Outer Digest A
+#define SHAMD5_O_ODIGEST_B      0x00000004  // SHA Outer Digest B
+#define SHAMD5_O_ODIGEST_C      0x00000008  // SHA Outer Digest C
+#define SHAMD5_O_ODIGEST_D      0x0000000C  // SHA Outer Digest D
+#define SHAMD5_O_ODIGEST_E      0x00000010  // SHA Outer Digest E
+#define SHAMD5_O_ODIGEST_F      0x00000014  // SHA Outer Digest F
+#define SHAMD5_O_ODIGEST_G      0x00000018  // SHA Outer Digest G
+#define SHAMD5_O_ODIGEST_H      0x0000001C  // SHA Outer Digest H
+#define SHAMD5_O_IDIGEST_A      0x00000020  // SHA Inner Digest A
+#define SHAMD5_O_IDIGEST_B      0x00000024  // SHA Inner Digest B
+#define SHAMD5_O_IDIGEST_C      0x00000028  // SHA Inner Digest C
+#define SHAMD5_O_IDIGEST_D      0x0000002C  // SHA Inner Digest D
+#define SHAMD5_O_IDIGEST_E      0x00000030  // SHA Inner Digest E
+#define SHAMD5_O_IDIGEST_F      0x00000034  // SHA Inner Digest F
+#define SHAMD5_O_IDIGEST_G      0x00000038  // SHA Inner Digest G
+#define SHAMD5_O_IDIGEST_H      0x0000003C  // SHA Inner Digest H
+#define SHAMD5_O_DIGEST_COUNT   0x00000040  // SHA Digest Count
+#define SHAMD5_O_MODE           0x00000044  // SHA Mode
+#define SHAMD5_O_LENGTH         0x00000048  // SHA Length
+#define SHAMD5_O_DATA_0_IN      0x00000080  // SHA Data 0 Input
+#define SHAMD5_O_DATA_1_IN      0x00000084  // SHA Data 1 Input
+#define SHAMD5_O_DATA_2_IN      0x00000088  // SHA Data 2 Input
+#define SHAMD5_O_DATA_3_IN      0x0000008C  // SHA Data 3 Input
+#define SHAMD5_O_DATA_4_IN      0x00000090  // SHA Data 4 Input
+#define SHAMD5_O_DATA_5_IN      0x00000094  // SHA Data 5 Input
+#define SHAMD5_O_DATA_6_IN      0x00000098  // SHA Data 6 Input
+#define SHAMD5_O_DATA_7_IN      0x0000009C  // SHA Data 7 Input
+#define SHAMD5_O_DATA_8_IN      0x000000A0  // SHA Data 8 Input
+#define SHAMD5_O_DATA_9_IN      0x000000A4  // SHA Data 9 Input
+#define SHAMD5_O_DATA_10_IN     0x000000A8  // SHA Data 10 Input
+#define SHAMD5_O_DATA_11_IN     0x000000AC  // SHA Data 11 Input
+#define SHAMD5_O_DATA_12_IN     0x000000B0  // SHA Data 12 Input
+#define SHAMD5_O_DATA_13_IN     0x000000B4  // SHA Data 13 Input
+#define SHAMD5_O_DATA_14_IN     0x000000B8  // SHA Data 14 Input
+#define SHAMD5_O_DATA_15_IN     0x000000BC  // SHA Data 15 Input
+#define SHAMD5_O_REVISION       0x00000100  // SHA Revision
+#define SHAMD5_O_SYSCONFIG      0x00000110  // SHA System Configuration
+#define SHAMD5_O_SYSSTATUS      0x00000114  // SHA System Status
+#define SHAMD5_O_IRQSTATUS      0x00000118  // SHA Interrupt Status
+#define SHAMD5_O_IRQENABLE      0x0000011C  // SHA Interrupt Enable
+#define SHAMD5_O_DMAIM          0xFFFFC010  // SHA DMA Interrupt Mask
+#define SHAMD5_O_DMARIS         0xFFFFC014  // SHA DMA Raw Interrupt Status
+#define SHAMD5_O_DMAMIS         0xFFFFC018  // SHA DMA Masked Interrupt Status
+#define SHAMD5_O_DMAIC          0xFFFFC01C  // SHA DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DIGEST_COUNT_M   0xFFFFFFFF  // Digest Count
+#define SHAMD5_DIGEST_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_MODE register.
+//
+//*****************************************************************************
+#define SHAMD5_MODE_HMAC_OUTER_HASH                                           \
+                                0x00000080  // HMAC Outer Hash Processing
+                                            // Enable
+#define SHAMD5_MODE_HMAC_KEY_PROC                                             \
+                                0x00000020  // HMAC Key Processing Enable
+#define SHAMD5_MODE_CLOSE_HASH  0x00000010  // Performs the padding, the
+                                            // Hash/HMAC will be 'closed' at
+                                            // the end of the block, as per
+                                            // MD5/SHA-1/SHA-2 specification
+#define SHAMD5_MODE_ALGO_CONSTANT                                             \
+                                0x00000008  // The initial digest register will
+                                            // be overwritten with the
+                                            // algorithm constants for the
+                                            // selected algorithm when hashing
+                                            // and the initial digest count
+                                            // register will be reset to 0
+#define SHAMD5_MODE_ALGO_M      0x00000007  // Hash Algorithm
+#define SHAMD5_MODE_ALGO_MD5    0x00000000  // MD5
+#define SHAMD5_MODE_ALGO_SHA1   0x00000002  // SHA-1
+#define SHAMD5_MODE_ALGO_SHA224 0x00000004  // SHA-224
+#define SHAMD5_MODE_ALGO_SHA256 0x00000006  // SHA-256
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_LENGTH
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_LENGTH_M         0xFFFFFFFF  // Block Length/Remaining Byte
+                                            // Count
+#define SHAMD5_LENGTH_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_0_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_1_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_2_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_3_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_4_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_5_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_6_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_7_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_8_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_9_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_10_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_10_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_11_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_11_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_12_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_12_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_13_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_13_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_14_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_14_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_15_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_15_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_REVISION
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_REVISION_M       0xFFFFFFFF  // Revision Number
+#define SHAMD5_REVISION_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSCONFIG_SADVANCED                                            \
+                                0x00000080  // Advanced Mode Enable
+#define SHAMD5_SYSCONFIG_SIDLE_M                                              \
+                                0x00000030  // Sidle mode
+#define SHAMD5_SYSCONFIG_SIDLE_FORCE                                          \
+                                0x00000000  // Force-idle mode
+#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008  // uDMA Request Enable
+#define SHAMD5_SYSCONFIG_IT_EN  0x00000004  // Interrupt Enable
+#define SHAMD5_SYSCONFIG_SOFTRESET                                            \
+                                0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSSTATUS_RESETDONE                                            \
+                                0x00000001  // Reset done status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQSTATUS_CONTEXT_READY                                        \
+                                0x00000008  // Context Ready Status
+#define SHAMD5_IRQSTATUS_INPUT_READY                                          \
+                                0x00000002  // Input Ready Status
+#define SHAMD5_IRQSTATUS_OUTPUT_READY                                         \
+                                0x00000001  // Output Ready Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQENABLE_CONTEXT_READY                                        \
+                                0x00000008  // Mask for context ready interrupt
+#define SHAMD5_IRQENABLE_INPUT_READY                                          \
+                                0x00000002  // Mask for input ready interrupt
+#define SHAMD5_IRQENABLE_OUTPUT_READY                                         \
+                                0x00000001  // Mask for output ready interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIM register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIM_COUT       0x00000004  // Context Out DMA Done Interrupt
+                                            // Mask
+#define SHAMD5_DMAIM_DIN        0x00000002  // Data In DMA Done Interrupt Mask
+#define SHAMD5_DMAIM_CIN        0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMARIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMARIS_COUT      0x00000004  // Context Out DMA Done Raw
+                                            // Interrupt Status
+#define SHAMD5_DMARIS_DIN       0x00000002  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define SHAMD5_DMARIS_CIN       0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAMIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAMIS_COUT      0x00000004  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAMIS_DIN       0x00000002  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAMIS_CIN       0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIC register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIC_COUT       0x00000004  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAIC_DIN        0x00000002  // Data In DMA Done Interrupt Clear
+#define SHAMD5_DMAIC_CIN        0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+#endif // __HW_SHAMD5_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_ssi.h b/bsp/tm4c129x/libraries/inc/hw_ssi.h
new file mode 100644
index 0000000000..c58c795fc3
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_ssi.h
@@ -0,0 +1,238 @@
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0               0x00000000  // SSI Control 0
+#define SSI_O_CR1               0x00000004  // SSI Control 1
+#define SSI_O_DR                0x00000008  // SSI Data
+#define SSI_O_SR                0x0000000C  // SSI Status
+#define SSI_O_CPSR              0x00000010  // SSI Clock Prescale
+#define SSI_O_IM                0x00000014  // SSI Interrupt Mask
+#define SSI_O_RIS               0x00000018  // SSI Raw Interrupt Status
+#define SSI_O_MIS               0x0000001C  // SSI Masked Interrupt Status
+#define SSI_O_ICR               0x00000020  // SSI Interrupt Clear
+#define SSI_O_DMACTL            0x00000024  // SSI DMA Control
+#define SSI_O_PP                0x00000FC0  // SSI Peripheral Properties
+#define SSI_O_CC                0x00000FC8  // SSI Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Synchronous Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOM             0x00000800  // Stop Frame (End of Message)
+#define SSI_CR1_FSSHLDFRM       0x00000400  // FSS Hold Frame
+#define SSI_CR1_HSCLKEN         0x00000200  // High Speed Clock Enable
+#define SSI_CR1_DIR             0x00000100  // SSI Direction of Operation
+#define SSI_CR1_MODE_M          0x000000C0  // SSI Mode
+#define SSI_CR1_MODE_LEGACY     0x00000000  // Legacy SSI mode
+#define SSI_CR1_MODE_BI         0x00000040  // Bi-SSI mode
+#define SSI_CR1_MODE_QUAD       0x00000080  // Quad-SSI Mode
+#define SSI_CR1_MODE_ADVANCED   0x000000C0  // Advanced SSI Mode with 8-bit
+                                            // packet size
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_EOTIM            0x00000040  // End of Transmit Interrupt Mask
+#define SSI_IM_DMATXIM          0x00000020  // SSI Transmit DMA Interrupt Mask
+#define SSI_IM_DMARXIM          0x00000010  // SSI Receive DMA Interrupt Mask
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_EOTRIS          0x00000040  // End of Transmit Raw Interrupt
+                                            // Status
+#define SSI_RIS_DMATXRIS        0x00000020  // SSI Transmit DMA Raw Interrupt
+                                            // Status
+#define SSI_RIS_DMARXRIS        0x00000010  // SSI Receive DMA Raw Interrupt
+                                            // Status
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_EOTMIS          0x00000040  // End of Transmit Masked Interrupt
+                                            // Status
+#define SSI_MIS_DMATXMIS        0x00000020  // SSI Transmit DMA Masked
+                                            // Interrupt Status
+#define SSI_MIS_DMARXMIS        0x00000010  // SSI Receive DMA Masked Interrupt
+                                            // Status
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_EOTIC           0x00000040  // End of Transmit Interrupt Clear
+#define SSI_ICR_DMATXIC         0x00000020  // SSI Transmit DMA Interrupt Clear
+#define SSI_ICR_DMARXIC         0x00000010  // SSI Receive DMA Interrupt Clear
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_PP register.
+//
+//*****************************************************************************
+#define SSI_PP_FSSHLDFRM        0x00000008  // FSS Hold Frame Capability
+#define SSI_PP_MODE_M           0x00000006  // Mode of Operation
+#define SSI_PP_MODE_LEGACY      0x00000000  // Legacy SSI mode
+#define SSI_PP_MODE_ADVBI       0x00000002  // Legacy mode, Advanced SSI mode
+                                            // and Bi-SSI mode enabled
+#define SSI_PP_MODE_ADVBIQUAD   0x00000004  // Legacy mode, Advanced mode,
+                                            // Bi-SSI and Quad-SSI mode enabled
+#define SSI_PP_HSCLK            0x00000001  // High Speed Capability
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL        0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define SSI_CC_CS_PIOSC         0x00000005  // PIOSC
+
+#endif // __HW_SSI_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_sysctl.h b/bsp/tm4c129x/libraries/inc/hw_sysctl.h
new file mode 100644
index 0000000000..47d81911ab
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_sysctl.h
@@ -0,0 +1,3704 @@
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0             0x400FE000  // Device Identification 0
+#define SYSCTL_DID1             0x400FE004  // Device Identification 1
+#define SYSCTL_DC0              0x400FE008  // Device Capabilities 0
+#define SYSCTL_DC1              0x400FE010  // Device Capabilities 1
+#define SYSCTL_DC2              0x400FE014  // Device Capabilities 2
+#define SYSCTL_DC3              0x400FE018  // Device Capabilities 3
+#define SYSCTL_DC4              0x400FE01C  // Device Capabilities 4
+#define SYSCTL_DC5              0x400FE020  // Device Capabilities 5
+#define SYSCTL_DC6              0x400FE024  // Device Capabilities 6
+#define SYSCTL_DC7              0x400FE028  // Device Capabilities 7
+#define SYSCTL_DC8              0x400FE02C  // Device Capabilities 8
+#define SYSCTL_PBORCTL          0x400FE030  // Brown-Out Reset Control
+#define SYSCTL_PTBOCTL          0x400FE038  // Power-Temp Brown Out Control
+#define SYSCTL_SRCR0            0x400FE040  // Software Reset Control 0
+#define SYSCTL_SRCR1            0x400FE044  // Software Reset Control 1
+#define SYSCTL_SRCR2            0x400FE048  // Software Reset Control 2
+#define SYSCTL_RIS              0x400FE050  // Raw Interrupt Status
+#define SYSCTL_IMC              0x400FE054  // Interrupt Mask Control
+#define SYSCTL_MISC             0x400FE058  // Masked Interrupt Status and
+                                            // Clear
+#define SYSCTL_RESC             0x400FE05C  // Reset Cause
+#define SYSCTL_PWRTC            0x400FE060  // Power-Temperature Cause
+#define SYSCTL_RCC              0x400FE060  // Run-Mode Clock Configuration
+#define SYSCTL_NMIC             0x400FE064  // NMI Cause Register
+#define SYSCTL_GPIOHBCTL        0x400FE06C  // GPIO High-Performance Bus
+                                            // Control
+#define SYSCTL_RCC2             0x400FE070  // Run-Mode Clock Configuration 2
+#define SYSCTL_MOSCCTL          0x400FE07C  // Main Oscillator Control
+#define SYSCTL_RSCLKCFG         0x400FE0B0  // Run and Sleep Mode Configuration
+                                            // Register
+#define SYSCTL_MEMTIM0          0x400FE0C0  // Memory Timing Parameter Register
+                                            // 0 for Main Flash and EEPROM
+#define SYSCTL_RCGC0            0x400FE100  // Run Mode Clock Gating Control
+                                            // Register 0
+#define SYSCTL_RCGC1            0x400FE104  // Run Mode Clock Gating Control
+                                            // Register 1
+#define SYSCTL_RCGC2            0x400FE108  // Run Mode Clock Gating Control
+                                            // Register 2
+#define SYSCTL_SCGC0            0x400FE110  // Sleep Mode Clock Gating Control
+                                            // Register 0
+#define SYSCTL_SCGC1            0x400FE114  // Sleep Mode Clock Gating Control
+                                            // Register 1
+#define SYSCTL_SCGC2            0x400FE118  // Sleep Mode Clock Gating Control
+                                            // Register 2
+#define SYSCTL_DCGC0            0x400FE120  // Deep Sleep Mode Clock Gating
+                                            // Control Register 0
+#define SYSCTL_DCGC1            0x400FE124  // Deep-Sleep Mode Clock Gating
+                                            // Control Register 1
+#define SYSCTL_DCGC2            0x400FE128  // Deep Sleep Mode Clock Gating
+                                            // Control Register 2
+#define SYSCTL_ALTCLKCFG        0x400FE138  // Alternate Clock Configuration
+#define SYSCTL_DSLPCLKCFG       0x400FE144  // Deep Sleep Clock Configuration
+#define SYSCTL_DSCLKCFG         0x400FE144  // Deep Sleep Clock Configuration
+                                            // Register
+#define SYSCTL_DIVSCLK          0x400FE148  // Divisor and Source Clock
+                                            // Configuration
+#define SYSCTL_SYSPROP          0x400FE14C  // System Properties
+#define SYSCTL_PIOSCCAL         0x400FE150  // Precision Internal Oscillator
+                                            // Calibration
+#define SYSCTL_PIOSCSTAT        0x400FE154  // Precision Internal Oscillator
+                                            // Statistics
+#define SYSCTL_PLLFREQ0         0x400FE160  // PLL Frequency 0
+#define SYSCTL_PLLFREQ1         0x400FE164  // PLL Frequency 1
+#define SYSCTL_PLLSTAT          0x400FE168  // PLL Status
+#define SYSCTL_SLPPWRCFG        0x400FE188  // Sleep Power Configuration
+#define SYSCTL_DSLPPWRCFG       0x400FE18C  // Deep-Sleep Power Configuration
+#define SYSCTL_DC9              0x400FE190  // Device Capabilities 9
+#define SYSCTL_NVMSTAT          0x400FE1A0  // Non-Volatile Memory Information
+#define SYSCTL_LDOSPCTL         0x400FE1B4  // LDO Sleep Power Control
+#define SYSCTL_LDODPCTL         0x400FE1BC  // LDO Deep-Sleep Power Control
+#define SYSCTL_RESBEHAVCTL      0x400FE1D8  // Reset Behavior Control Register
+#define SYSCTL_HSSR             0x400FE1F4  // Hardware System Service Request
+#define SYSCTL_USBPDS           0x400FE280  // USB Power Domain Status
+#define SYSCTL_USBMPC           0x400FE284  // USB Memory Power Control
+#define SYSCTL_EMACPDS          0x400FE288  // Ethernet MAC Power Domain Status
+#define SYSCTL_EMACMPC          0x400FE28C  // Ethernet MAC Memory Power
+                                            // Control
+#define SYSCTL_LCDMPC           0x400FE294  // LCD Memory Power Control
+#define SYSCTL_PPWD             0x400FE300  // Watchdog Timer Peripheral
+                                            // Present
+#define SYSCTL_PPTIMER          0x400FE304  // 16/32-Bit General-Purpose Timer
+                                            // Peripheral Present
+#define SYSCTL_PPGPIO           0x400FE308  // General-Purpose Input/Output
+                                            // Peripheral Present
+#define SYSCTL_PPDMA            0x400FE30C  // Micro Direct Memory Access
+                                            // Peripheral Present
+#define SYSCTL_PPEPI            0x400FE310  // EPI Peripheral Present
+#define SYSCTL_PPHIB            0x400FE314  // Hibernation Peripheral Present
+#define SYSCTL_PPUART           0x400FE318  // Universal Asynchronous
+                                            // Receiver/Transmitter Peripheral
+                                            // Present
+#define SYSCTL_PPSSI            0x400FE31C  // Synchronous Serial Interface
+                                            // Peripheral Present
+#define SYSCTL_PPI2C            0x400FE320  // Inter-Integrated Circuit
+                                            // Peripheral Present
+#define SYSCTL_PPUSB            0x400FE328  // Universal Serial Bus Peripheral
+                                            // Present
+#define SYSCTL_PPEPHY           0x400FE330  // Ethernet PHY Peripheral Present
+#define SYSCTL_PPCAN            0x400FE334  // Controller Area Network
+                                            // Peripheral Present
+#define SYSCTL_PPADC            0x400FE338  // Analog-to-Digital Converter
+                                            // Peripheral Present
+#define SYSCTL_PPACMP           0x400FE33C  // Analog Comparator Peripheral
+                                            // Present
+#define SYSCTL_PPPWM            0x400FE340  // Pulse Width Modulator Peripheral
+                                            // Present
+#define SYSCTL_PPQEI            0x400FE344  // Quadrature Encoder Interface
+                                            // Peripheral Present
+#define SYSCTL_PPLPC            0x400FE348  // Low Pin Count Interface
+                                            // Peripheral Present
+#define SYSCTL_PPPECI           0x400FE350  // Platform Environment Control
+                                            // Interface Peripheral Present
+#define SYSCTL_PPFAN            0x400FE354  // Fan Control Peripheral Present
+#define SYSCTL_PPEEPROM         0x400FE358  // EEPROM Peripheral Present
+#define SYSCTL_PPWTIMER         0x400FE35C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Peripheral Present
+#define SYSCTL_PPRTS            0x400FE370  // Remote Temperature Sensor
+                                            // Peripheral Present
+#define SYSCTL_PPCCM            0x400FE374  // CRC and Cryptographic Modules
+                                            // Peripheral Present
+#define SYSCTL_PPLCD            0x400FE390  // LCD Peripheral Present
+#define SYSCTL_PPOWIRE          0x400FE398  // 1-Wire Peripheral Present
+#define SYSCTL_PPEMAC           0x400FE39C  // Ethernet MAC Peripheral Present
+#define SYSCTL_PPHIM            0x400FE3A4  // Human Interface Master
+                                            // Peripheral Present
+#define SYSCTL_SRWD             0x400FE500  // Watchdog Timer Software Reset
+#define SYSCTL_SRTIMER          0x400FE504  // 16/32-Bit General-Purpose Timer
+                                            // Software Reset
+#define SYSCTL_SRGPIO           0x400FE508  // General-Purpose Input/Output
+                                            // Software Reset
+#define SYSCTL_SRDMA            0x400FE50C  // Micro Direct Memory Access
+                                            // Software Reset
+#define SYSCTL_SREPI            0x400FE510  // EPI Software Reset
+#define SYSCTL_SRHIB            0x400FE514  // Hibernation Software Reset
+#define SYSCTL_SRUART           0x400FE518  // Universal Asynchronous
+                                            // Receiver/Transmitter Software
+                                            // Reset
+#define SYSCTL_SRSSI            0x400FE51C  // Synchronous Serial Interface
+                                            // Software Reset
+#define SYSCTL_SRI2C            0x400FE520  // Inter-Integrated Circuit
+                                            // Software Reset
+#define SYSCTL_SRUSB            0x400FE528  // Universal Serial Bus Software
+                                            // Reset
+#define SYSCTL_SREPHY           0x400FE530  // Ethernet PHY Software Reset
+#define SYSCTL_SRCAN            0x400FE534  // Controller Area Network Software
+                                            // Reset
+#define SYSCTL_SRADC            0x400FE538  // Analog-to-Digital Converter
+                                            // Software Reset
+#define SYSCTL_SRACMP           0x400FE53C  // Analog Comparator Software Reset
+#define SYSCTL_SRPWM            0x400FE540  // Pulse Width Modulator Software
+                                            // Reset
+#define SYSCTL_SRQEI            0x400FE544  // Quadrature Encoder Interface
+                                            // Software Reset
+#define SYSCTL_SREEPROM         0x400FE558  // EEPROM Software Reset
+#define SYSCTL_SRWTIMER         0x400FE55C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Software Reset
+#define SYSCTL_SRCCM            0x400FE574  // CRC and Cryptographic Modules
+                                            // Software Reset
+#define SYSCTL_SRLCD            0x400FE590  // LCD Controller Software Reset
+#define SYSCTL_SROWIRE          0x400FE598  // 1-Wire Software Reset
+#define SYSCTL_SREMAC           0x400FE59C  // Ethernet MAC Software Reset
+#define SYSCTL_RCGCWD           0x400FE600  // Watchdog Timer Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCTIMER        0x400FE604  // 16/32-Bit General-Purpose Timer
+                                            // Run Mode Clock Gating Control
+#define SYSCTL_RCGCGPIO         0x400FE608  // General-Purpose Input/Output Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCDMA          0x400FE60C  // Micro Direct Memory Access Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCEPI          0x400FE610  // EPI Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCHIB          0x400FE614  // Hibernation Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART         0x400FE618  // Universal Asynchronous
+                                            // Receiver/Transmitter Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCSSI          0x400FE61C  // Synchronous Serial Interface Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCI2C          0x400FE620  // Inter-Integrated Circuit Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCUSB          0x400FE628  // Universal Serial Bus Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCEPHY         0x400FE630  // Ethernet PHY Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCCAN          0x400FE634  // Controller Area Network Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCADC          0x400FE638  // Analog-to-Digital Converter Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCACMP         0x400FE63C  // Analog Comparator Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCPWM          0x400FE640  // Pulse Width Modulator Run Mode
+                                            // Clock Gating Control
+#define SYSCTL_RCGCQEI          0x400FE644  // Quadrature Encoder Interface Run
+                                            // Mode Clock Gating Control
+#define SYSCTL_RCGCEEPROM       0x400FE658  // EEPROM Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER       0x400FE65C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCCCM          0x400FE674  // CRC and Cryptographic Modules
+                                            // Run Mode Clock Gating Control
+#define SYSCTL_RCGCLCD          0x400FE690  // LCD Controller Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCOWIRE        0x400FE698  // 1-Wire Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCEMAC         0x400FE69C  // Ethernet MAC Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCWD           0x400FE700  // Watchdog Timer Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCTIMER        0x400FE704  // 16/32-Bit General-Purpose Timer
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCGPIO         0x400FE708  // General-Purpose Input/Output
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCDMA          0x400FE70C  // Micro Direct Memory Access Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_SCGCEPI          0x400FE710  // EPI Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCHIB          0x400FE714  // Hibernation Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART         0x400FE718  // Universal Asynchronous
+                                            // Receiver/Transmitter Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCSSI          0x400FE71C  // Synchronous Serial Interface
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCI2C          0x400FE720  // Inter-Integrated Circuit Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_SCGCUSB          0x400FE728  // Universal Serial Bus Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCEPHY         0x400FE730  // Ethernet PHY Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCCAN          0x400FE734  // Controller Area Network Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_SCGCADC          0x400FE738  // Analog-to-Digital Converter
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCACMP         0x400FE73C  // Analog Comparator Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCPWM          0x400FE740  // Pulse Width Modulator Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCQEI          0x400FE744  // Quadrature Encoder Interface
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCEEPROM       0x400FE758  // EEPROM Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER       0x400FE75C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCCCM          0x400FE774  // CRC and Cryptographic Modules
+                                            // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCLCD          0x400FE790  // LCD Controller Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCOWIRE        0x400FE798  // 1-Wire Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCEMAC         0x400FE79C  // Ethernet MAC Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWD           0x400FE800  // Watchdog Timer Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCTIMER        0x400FE804  // 16/32-Bit General-Purpose Timer
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCGPIO         0x400FE808  // General-Purpose Input/Output
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCDMA          0x400FE80C  // Micro Direct Memory Access
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCEPI          0x400FE810  // EPI Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCHIB          0x400FE814  // Hibernation Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART         0x400FE818  // Universal Asynchronous
+                                            // Receiver/Transmitter Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCSSI          0x400FE81C  // Synchronous Serial Interface
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCI2C          0x400FE820  // Inter-Integrated Circuit
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCUSB          0x400FE828  // Universal Serial Bus Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCEPHY         0x400FE830  // Ethernet PHY Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCCAN          0x400FE834  // Controller Area Network
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCADC          0x400FE838  // Analog-to-Digital Converter
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCACMP         0x400FE83C  // Analog Comparator Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCPWM          0x400FE840  // Pulse Width Modulator Deep-Sleep
+                                            // Mode Clock Gating Control
+#define SYSCTL_DCGCQEI          0x400FE844  // Quadrature Encoder Interface
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCEEPROM       0x400FE858  // EEPROM Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER       0x400FE85C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCCCM          0x400FE874  // CRC and Cryptographic Modules
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCLCD          0x400FE890  // LCD Controller Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCOWIRE        0x400FE898  // 1-Wire Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCEMAC         0x400FE89C  // Ethernet MAC Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_PCWD             0x400FE900  // Watchdog Timer Power Control
+#define SYSCTL_PCTIMER          0x400FE904  // 16/32-Bit General-Purpose Timer
+                                            // Power Control
+#define SYSCTL_PCGPIO           0x400FE908  // General-Purpose Input/Output
+                                            // Power Control
+#define SYSCTL_PCDMA            0x400FE90C  // Micro Direct Memory Access Power
+                                            // Control
+#define SYSCTL_PCEPI            0x400FE910  // External Peripheral Interface
+                                            // Power Control
+#define SYSCTL_PCHIB            0x400FE914  // Hibernation Power Control
+#define SYSCTL_PCUART           0x400FE918  // Universal Asynchronous
+                                            // Receiver/Transmitter Power
+                                            // Control
+#define SYSCTL_PCSSI            0x400FE91C  // Synchronous Serial Interface
+                                            // Power Control
+#define SYSCTL_PCI2C            0x400FE920  // Inter-Integrated Circuit Power
+                                            // Control
+#define SYSCTL_PCUSB            0x400FE928  // Universal Serial Bus Power
+                                            // Control
+#define SYSCTL_PCEPHY           0x400FE930  // Ethernet PHY Power Control
+#define SYSCTL_PCCAN            0x400FE934  // Controller Area Network Power
+                                            // Control
+#define SYSCTL_PCADC            0x400FE938  // Analog-to-Digital Converter
+                                            // Power Control
+#define SYSCTL_PCACMP           0x400FE93C  // Analog Comparator Power Control
+#define SYSCTL_PCPWM            0x400FE940  // Pulse Width Modulator Power
+                                            // Control
+#define SYSCTL_PCQEI            0x400FE944  // Quadrature Encoder Interface
+                                            // Power Control
+#define SYSCTL_PCEEPROM         0x400FE958  // EEPROM Power Control
+#define SYSCTL_PCCCM            0x400FE974  // CRC and Cryptographic Modules
+                                            // Power Control
+#define SYSCTL_PCLCD            0x400FE990  // LCD Controller Power Control
+#define SYSCTL_PCOWIRE          0x400FE998  // 1-Wire Power Control
+#define SYSCTL_PCEMAC           0x400FE99C  // Ethernet MAC Power Control
+#define SYSCTL_PRWD             0x400FEA00  // Watchdog Timer Peripheral Ready
+#define SYSCTL_PRTIMER          0x400FEA04  // 16/32-Bit General-Purpose Timer
+                                            // Peripheral Ready
+#define SYSCTL_PRGPIO           0x400FEA08  // General-Purpose Input/Output
+                                            // Peripheral Ready
+#define SYSCTL_PRDMA            0x400FEA0C  // Micro Direct Memory Access
+                                            // Peripheral Ready
+#define SYSCTL_PREPI            0x400FEA10  // EPI Peripheral Ready
+#define SYSCTL_PRHIB            0x400FEA14  // Hibernation Peripheral Ready
+#define SYSCTL_PRUART           0x400FEA18  // Universal Asynchronous
+                                            // Receiver/Transmitter Peripheral
+                                            // Ready
+#define SYSCTL_PRSSI            0x400FEA1C  // Synchronous Serial Interface
+                                            // Peripheral Ready
+#define SYSCTL_PRI2C            0x400FEA20  // Inter-Integrated Circuit
+                                            // Peripheral Ready
+#define SYSCTL_PRUSB            0x400FEA28  // Universal Serial Bus Peripheral
+                                            // Ready
+#define SYSCTL_PREPHY           0x400FEA30  // Ethernet PHY Peripheral Ready
+#define SYSCTL_PRCAN            0x400FEA34  // Controller Area Network
+                                            // Peripheral Ready
+#define SYSCTL_PRADC            0x400FEA38  // Analog-to-Digital Converter
+                                            // Peripheral Ready
+#define SYSCTL_PRACMP           0x400FEA3C  // Analog Comparator Peripheral
+                                            // Ready
+#define SYSCTL_PRPWM            0x400FEA40  // Pulse Width Modulator Peripheral
+                                            // Ready
+#define SYSCTL_PRQEI            0x400FEA44  // Quadrature Encoder Interface
+                                            // Peripheral Ready
+#define SYSCTL_PREEPROM         0x400FEA58  // EEPROM Peripheral Ready
+#define SYSCTL_PRWTIMER         0x400FEA5C  // 32/64-Bit Wide General-Purpose
+                                            // Timer Peripheral Ready
+#define SYSCTL_PRCCM            0x400FEA74  // CRC and Cryptographic Modules
+                                            // Peripheral Ready
+#define SYSCTL_PRLCD            0x400FEA90  // LCD Controller Peripheral Ready
+#define SYSCTL_PROWIRE          0x400FEA98  // 1-Wire Peripheral Ready
+#define SYSCTL_PREMAC           0x400FEA9C  // Ethernet MAC Peripheral Ready
+#define SYSCTL_CCMCGREQ         0x44030204  // Cryptographic Modules Clock
+                                            // Gating Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format.
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_TM4C123                                             \
+                                0x00050000  // Tiva TM4C123x and TM4E123x
+                                            // microcontrollers
+#define SYSCTL_DID0_CLASS_TM4C129                                             \
+                                0x000A0000  // Tiva(TM) TM4C129-class
+                                            // microcontrollers
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
+#define SYSCTL_DID1_VER_1       0x10000000  // fury_ib
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
+#define SYSCTL_DID1_FAM_TIVA    0x00000000  // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C1230C3PM                                        \
+                                0x00220000  // TM4C1230C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1230D5PM                                        \
+                                0x00230000  // TM4C1230D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1230E6PM                                        \
+                                0x00200000  // TM4C1230E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1230H6PM                                        \
+                                0x00210000  // TM4C1230H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231C3PM                                        \
+                                0x00180000  // TM4C1231C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PM                                        \
+                                0x00190000  // TM4C1231D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ                                        \
+                                0x00360000  // TM4C1231D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PM                                        \
+                                0x00100000  // TM4C1231E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ                                        \
+                                0x00300000  // TM4C1231E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE                                       \
+                                0x00350000  // TM4C1231H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PM                                        \
+                                0x00110000  // TM4C1231H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ                                        \
+                                0x00310000  // TM4C1231H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1232C3PM                                        \
+                                0x00080000  // TM4C1232C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1232D5PM                                        \
+                                0x00090000  // TM4C1232D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1232E6PM                                        \
+                                0x000A0000  // TM4C1232E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1232H6PM                                        \
+                                0x000B0000  // TM4C1232H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233C3PM                                        \
+                                0x00010000  // TM4C1233C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PM                                        \
+                                0x00020000  // TM4C1233D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ                                        \
+                                0x00D00000  // TM4C1233D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PM                                        \
+                                0x00030000  // TM4C1233E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ                                        \
+                                0x00D10000  // TM4C1233E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE                                       \
+                                0x00D60000  // TM4C1233H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PM                                        \
+                                0x00040000  // TM4C1233H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ                                        \
+                                0x00D20000  // TM4C1233H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1236D5PM                                        \
+                                0x00520000  // TM4C1236D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1236E6PM                                        \
+                                0x00500000  // TM4C1236E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1236H6PM                                        \
+                                0x00510000  // TM4C1236H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PM                                        \
+                                0x00480000  // TM4C1237D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ                                        \
+                                0x00660000  // TM4C1237D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PM                                        \
+                                0x00400000  // TM4C1237E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ                                        \
+                                0x00600000  // TM4C1237E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE                                       \
+                                0x00650000  // TM4C1237H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PM                                        \
+                                0x00410000  // TM4C1237H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ                                        \
+                                0x00610000  // TM4C1237H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123AE6PM                                        \
+                                0x00800000  // TM4C123AE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123AH6PM                                        \
+                                0x00830000  // TM4C123AH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PM                                        \
+                                0x00700000  // TM4C123BE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ                                        \
+                                0x00C30000  // TM4C123BE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE                                       \
+                                0x00C60000  // TM4C123BH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PM                                        \
+                                0x00730000  // TM4C123BH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ                                        \
+                                0x00C40000  // TM4C123BH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB                                       \
+                                0x00E90000  // TM4C123BH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C123FE6PM                                        \
+                                0x00B00000  // TM4C123FE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123FH6PM                                        \
+                                0x00B10000  // TM4C123FH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PM                                        \
+                                0x00A00000  // TM4C123GE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ                                        \
+                                0x00C00000  // TM4C123GE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE                                       \
+                                0x00C50000  // TM4C123GH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PM                                        \
+                                0x00A10000  // TM4C123GH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ                                        \
+                                0x00C10000  // TM4C123GH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB                                       \
+                                0x00E30000  // TM4C123GH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT                                       \
+                                0x00190000  // TM4C1290NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD                                       \
+                                0x001B0000  // TM4C1290NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT                                       \
+                                0x001C0000  // TM4C1292NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD                                       \
+                                0x001E0000  // TM4C1292NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT                                       \
+                                0x00340000  // TM4C1294KCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT                                       \
+                                0x001F0000  // TM4C1294NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD                                       \
+                                0x00210000  // TM4C1294NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD                                       \
+                                0x00220000  // TM4C1297NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD                                       \
+                                0x00360000  // TM4C1299KCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD                                       \
+                                0x00230000  // TM4C1299NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT                                       \
+                                0x00240000  // TM4C129CNCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD                                       \
+                                0x00260000  // TM4C129CNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT                                       \
+                                0x00270000  // TM4C129DNCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD                                       \
+                                0x00290000  // TM4C129DNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT                                       \
+                                0x00350000  // TM4C129EKCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT                                       \
+                                0x002D0000  // TM4C129ENCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD                                       \
+                                0x002F0000  // TM4C129ENCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD                                       \
+                                0x00300000  // TM4C129LNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD                                       \
+                                0x00370000  // TM4C129XKCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD                                       \
+                                0x00320000  // TM4C129XNCZAD
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin LQFP package
+#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin LQFP package
+#define SYSCTL_DID1_PINCNT_144  0x00008000  // 144-pin LQFP package
+#define SYSCTL_DID1_PINCNT_157  0x0000A000  // 157-pin BGA package
+#define SYSCTL_DID1_PINCNT_128  0x0000C000  // 128-pin TQFP package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range
+#define SYSCTL_DID1_TEMP_IE     0x00000060  // Available in both industrial
+                                            // temperature range (-40C to 85C)
+                                            // and extended temperature range
+                                            // (-40C to 105C) devices. See
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // QFP package
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000  // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB  0x002F0000  // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB  0x004F0000  // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB  0x005F0000  // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F  // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1         0x00200000  // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0         0x00100000  // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_80 0x00001000  // Specifies an 80-MHz CPU clock
+                                            // with a PLL divider of 2.5
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Specifies a 66-MHz CPU clock
+                                            // with a PLL divider of 3
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000  // Specifies a 40-MHz CPU clock
+                                            // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
+                                            // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
+                                            // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000  // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400  // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800  // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000  // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100  // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200  // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS       0x00008000  // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS       0x00002000  // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // T2CCP1 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // T2CCP0 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // T1CCP1 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // T1CCP0 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // T0CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // T0CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7         0x00008000  // T3CCP1 Pin Present
+#define SYSCTL_DC4_CCP6         0x00004000  // T3CCP0 Pin Present
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV     0x00000001  // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30      0x40000000  // DMA Channel 30
+#define SYSCTL_DC7_DMACH29      0x20000000  // DMA Channel 29
+#define SYSCTL_DC7_DMACH28      0x10000000  // DMA Channel 28
+#define SYSCTL_DC7_DMACH27      0x08000000  // DMA Channel 27
+#define SYSCTL_DC7_DMACH26      0x04000000  // DMA Channel 26
+#define SYSCTL_DC7_DMACH25      0x02000000  // DMA Channel 25
+#define SYSCTL_DC7_DMACH24      0x01000000  // DMA Channel 24
+#define SYSCTL_DC7_DMACH23      0x00800000  // DMA Channel 23
+#define SYSCTL_DC7_DMACH22      0x00400000  // DMA Channel 22
+#define SYSCTL_DC7_DMACH21      0x00200000  // DMA Channel 21
+#define SYSCTL_DC7_DMACH20      0x00100000  // DMA Channel 20
+#define SYSCTL_DC7_DMACH19      0x00080000  // DMA Channel 19
+#define SYSCTL_DC7_DMACH18      0x00040000  // DMA Channel 18
+#define SYSCTL_DC7_DMACH17      0x00020000  // DMA Channel 17
+#define SYSCTL_DC7_DMACH16      0x00010000  // DMA Channel 16
+#define SYSCTL_DC7_DMACH15      0x00008000  // DMA Channel 15
+#define SYSCTL_DC7_DMACH14      0x00004000  // DMA Channel 14
+#define SYSCTL_DC7_DMACH13      0x00002000  // DMA Channel 13
+#define SYSCTL_DC7_DMACH12      0x00001000  // DMA Channel 12
+#define SYSCTL_DC7_DMACH11      0x00000800  // DMA Channel 11
+#define SYSCTL_DC7_DMACH10      0x00000400  // DMA Channel 10
+#define SYSCTL_DC7_DMACH9       0x00000200  // DMA Channel 9
+#define SYSCTL_DC7_DMACH8       0x00000100  // DMA Channel 8
+#define SYSCTL_DC7_DMACH7       0x00000080  // DMA Channel 7
+#define SYSCTL_DC7_DMACH6       0x00000040  // DMA Channel 6
+#define SYSCTL_DC7_DMACH5       0x00000020  // DMA Channel 5
+#define SYSCTL_DC7_DMACH4       0x00000010  // DMA Channel 4
+#define SYSCTL_DC7_DMACH3       0x00000008  // DMA Channel 3
+#define SYSCTL_DC7_DMACH2       0x00000004  // DMA Channel 2
+#define SYSCTL_DC7_DMACH1       0x00000002  // DMA Channel 1
+#define SYSCTL_DC7_DMACH0       0x00000001  // DMA Channel 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR0     0x00000004  // VDD under BOR0 Event Action
+#define SYSCTL_PBORCTL_BOR1     0x00000002  // VDD under BOR1 Event Action
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PTBOCTL_VDDA_UBOR_M                                            \
+                                0x00000300  // VDDA under BOR Event Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE                                         \
+                                0x00000000  // No Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT                                       \
+                                0x00000100  // System control interrupt
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI                                          \
+                                0x00000200  // NMI
+#define SYSCTL_PTBOCTL_VDDA_UBOR_RST                                          \
+                                0x00000300  // Reset
+#define SYSCTL_PTBOCTL_VDD_UBOR_M                                             \
+                                0x00000003  // VDD (VDDS) under BOR Event
+                                            // Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_NONE                                          \
+                                0x00000000  // No Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT                                        \
+                                0x00000001  // System control interrupt
+#define SYSCTL_PTBOCTL_VDD_UBOR_NMI                                           \
+                                0x00000002  // NMI
+#define SYSCTL_PTBOCTL_VDD_UBOR_RST                                           \
+                                0x00000003  // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0       0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_BOR0RIS      0x00000800  // VDD under BOR0 Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_VDDARIS      0x00000400  // VDDA Power OK Event Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Failure Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_BOR1RIS      0x00000002  // VDD under BOR1 Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_BOR0IM       0x00000800  // VDD under BOR0 Interrupt Mask
+#define SYSCTL_IMC_VDDAIM       0x00000400  // VDDA Power OK Interrupt Mask
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Failure
+                                            // Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
+#define SYSCTL_IMC_BOR1IM       0x00000002  // VDD under BOR1 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_BOR0MIS     0x00000800  // VDD under BOR0 Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_VDDAMIS     0x00000400  // VDDA Power OK Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Failure Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
+#define SYSCTL_MISC_BOR1MIS     0x00000002  // VDD under BOR1 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_HSSR        0x00001000  // HSSR Reset
+#define SYSCTL_RESC_HIB         0x00000040  // HIB Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PWRTC register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR  0x00000010  // VDDA Under BOR Status
+#define SYSCTL_PWRTC_VDD_UBOR   0x00000001  // VDD Under BOR Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ   0x000005C0  // 18.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_20MHZ   0x00000600  // 20.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_24MHZ   0x00000640  // 24.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_25MHZ   0x00000680  // 25.0 MHz (USB)
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // LFIOSC
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
+#define SYSCTL_RCC_XTAL_S       6           // Shift to the XTAL field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NMIC register.
+//
+//*****************************************************************************
+#define SYSCTL_NMIC_MOSCFAIL    0x00010000  // MOSC Failure NMI
+#define SYSCTL_NMIC_TAMPER      0x00000200  // Tamper Event NMI
+#define SYSCTL_NMIC_WDT1        0x00000020  // Watch Dog Timer (WDT) 1 NMI
+#define SYSCTL_NMIC_WDT0        0x00000008  // Watch Dog Timer (WDT) 0 NMI
+#define SYSCTL_NMIC_POWER       0x00000004  // Power/Brown Out Event NMI
+#define SYSCTL_NMIC_EXTERNAL    0x00000001  // External Pin NMI
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
+                                            // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
+                                            // MHz
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // LFIOSC
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_OSCRNG   0x00000010  // Oscillator Range
+#define SYSCTL_MOSCCTL_PWRDN    0x00000008  // Power Down
+#define SYSCTL_MOSCCTL_NOXTAL   0x00000004  // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM   0x00000002  // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000  // Memory Timing Register Update
+#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000  // New PLLFREQ Accept
+#define SYSCTL_RSCLKCFG_ACG     0x20000000  // Auto Clock Gating
+#define SYSCTL_RSCLKCFG_USEPLL  0x10000000  // Use PLL
+#define SYSCTL_RSCLKCFG_PLLSRC_M                                              \
+                                0x0F000000  // PLL Source
+#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC                                          \
+                                0x00000000  // PIOSC is PLL input clock source
+#define SYSCTL_RSCLKCFG_PLLSRC_MOSC                                           \
+                                0x03000000  // MOSC is the PLL input clock
+                                            // source
+#define SYSCTL_RSCLKCFG_OSCSRC_M                                              \
+                                0x00F00000  // Oscillator Source
+#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC                                          \
+                                0x00000000  // PIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC                                         \
+                                0x00200000  // LFIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_MOSC                                           \
+                                0x00300000  // MOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_RTC                                            \
+                                0x00400000  // Hibernation Module RTC
+                                            // Oscillator (RTCOSC)
+#define SYSCTL_RSCLKCFG_OSYSDIV_M                                             \
+                                0x000FFC00  // Oscillator System Clock Divisor
+#define SYSCTL_RSCLKCFG_PSYSDIV_M                                             \
+                                0x000003FF  // PLL System Clock Divisor
+#define SYSCTL_RSCLKCFG_OSYSDIV_S                                             \
+                                10
+#define SYSCTL_RSCLKCFG_PSYSDIV_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
+//
+//*****************************************************************************
+#define SYSCTL_MEMTIM0_EBCHT_M  0x03C00000  // EEPROM Clock High Time
+#define SYSCTL_MEMTIM0_EBCHT_0_5                                              \
+                                0x00000000  // 1/2 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1  0x00400000  // 1 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1_5                                              \
+                                0x00800000  // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2  0x00C00000  // 2 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2_5                                              \
+                                0x01000000  // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3  0x01400000  // 3 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3_5                                              \
+                                0x01800000  // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4  0x01C00000  // 4 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4_5                                              \
+                                0x02000000  // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCE     0x00200000  // EEPROM Bank Clock Edge
+#define SYSCTL_MEMTIM0_MB1      0x00100010  // Must be one
+#define SYSCTL_MEMTIM0_EWS_M    0x000F0000  // EEPROM Wait States
+#define SYSCTL_MEMTIM0_FBCHT_M  0x000003C0  // Flash Bank Clock High Time
+#define SYSCTL_MEMTIM0_FBCHT_0_5                                              \
+                                0x00000000  // 1/2 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1  0x00000040  // 1 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1_5                                              \
+                                0x00000080  // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2  0x000000C0  // 2 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2_5                                              \
+                                0x00000100  // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3  0x00000140  // 3 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3_5                                              \
+                                0x00000180  // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4  0x000001C0  // 4 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4_5                                              \
+                                0x00000200  // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCE     0x00000020  // Flash Bank Clock Edge
+#define SYSCTL_MEMTIM0_FWS_M    0x0000000F  // Flash Wait State
+#define SYSCTL_MEMTIM0_EWS_S    16
+#define SYSCTL_MEMTIM0_FWS_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K                                             \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K                                             \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K                                             \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K                                             \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K                                             \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K                                             \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_ALTCLKCFG_ALTCLK_M                                             \
+                                0x0000000F  // Alternate Clock Source
+#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC                                         \
+                                0x00000000  // PIOSC
+#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC                                        \
+                                0x00000003  // Hibernation Module Real-time
+                                            // clock output (RTCOSC)
+#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC                                        \
+                                0x00000004  // Low-frequency internal
+                                            // oscillator (LFIOSC)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // LFIOSC
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_PIOSCPD                                             \
+                                0x00000002  // PIOSC Power Down Request
+#define SYSCTL_DSLPCLKCFG_D_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000  // PIOSC Power Down
+#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000  // MOSC Disable Power Down
+#define SYSCTL_DSCLKCFG_DSOSCSRC_M                                            \
+                                0x00F00000  // Deep Sleep Oscillator Source
+#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC                                        \
+                                0x00000000  // PIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC                                       \
+                                0x00200000  // LFIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC                                         \
+                                0x00300000  // MOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC                                          \
+                                0x00400000  // Hibernation Module RTCOSC
+#define SYSCTL_DSCLKCFG_DSSYSDIV_M                                            \
+                                0x000003FF  // Deep Sleep Clock Divisor
+#define SYSCTL_DSCLKCFG_DSSYSDIV_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
+//
+//*****************************************************************************
+#define SYSCTL_DIVSCLK_EN       0x80000000  // DIVSCLK Enable
+#define SYSCTL_DIVSCLK_SRC_M    0x00030000  // Clock Source
+#define SYSCTL_DIVSCLK_SRC_SYSCLK                                             \
+                                0x00000000  // System Clock
+#define SYSCTL_DIVSCLK_SRC_PIOSC                                              \
+                                0x00010000  // PIOSC
+#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000  // MOSC
+#define SYSCTL_DIVSCLK_DIV_M    0x000000FF  // Divisor Value
+#define SYSCTL_DIVSCLK_DIV_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU      0x00000001  // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000  // Calibration has not been
+                                            // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100  // The last calibration operation
+                                            // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200  // The last calibration operation
+                                            // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S   16
+#define SYSCTL_PIOSCSTAT_CT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_PLLPWR  0x00800000  // PLL Power
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00  // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M  0x000003FF  // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M     0x00001F00  // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M     0x0000001F  // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S     8
+#define SYSCTL_PLLFREQ1_N_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK     0x00000001  // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SLPPWRCFG_FLASHPM_M                                            \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_SLPPWRCFG_FLASHPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_FLASHPM_SLP                                          \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_M                                             \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_SLPPWRCFG_SRAMPM_NRM                                           \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_SBY                                           \
+                                0x00000001  // Standby Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_LP                                            \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200  // LDO Sleep Mode
+#define SYSCTL_DSLPPWRCFG_TSPD  0x00000100  // Temperature Sense Power Down
+#define SYSCTL_DSLPPWRCFG_FLASHPM_M                                           \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM                                         \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP                                         \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_M                                            \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY                                          \
+                                0x00000001  // Standby Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_LP                                           \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
+                                            // Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOSPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDOSPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDOSPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDOSPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDOSPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDOSPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDOSPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDOSPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDOSPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDODPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDODPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDODPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDODPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDODPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDODPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDODPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDODPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDODPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDODPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+#define SYSCTL_LDODPCTL_VLDO_1_25V                                            \
+                                0x00000019  // 1.25 V
+#define SYSCTL_LDODPCTL_VLDO_1_30V                                            \
+                                0x0000001A  // 1.30 V
+#define SYSCTL_LDODPCTL_VLDO_1_35V                                            \
+                                0x0000001B  // 1.35 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESBEHAVCTL_WDOG1_M                                            \
+                                0x000000C0  // Watchdog 1 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST                                       \
+                                0x00000080  // Watchdog 1 issues a system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG1_POR                                          \
+                                0x000000C0  // Watchdog 1 issues a simulated
+                                            // POR sequence. Application starts
+                                            // less than 500 us after
+                                            // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_WDOG0_M                                            \
+                                0x00000030  // Watchdog 0 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST                                       \
+                                0x00000020  // Watchdog 0 issues a system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG0_POR                                          \
+                                0x00000030  // Watchdog 0 issues a simulated
+                                            // POR sequence. Application starts
+                                            // less than 500 us after
+                                            // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_BOR_M                                              \
+                                0x0000000C  // BOR Reset operation
+#define SYSCTL_RESBEHAVCTL_BOR_SYSRST                                         \
+                                0x00000008  // Brown Out Reset issues system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_BOR_POR                                            \
+                                0x0000000C  // Brown Out Reset issues a
+                                            // simulated POR sequence. The
+                                            // application starts less than 500
+                                            // us after deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_EXTRES_M                                           \
+                                0x00000003  // External RST Pin Operation
+#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST                                      \
+                                0x00000002  // External RST assertion issues a
+                                            // system reset. The application
+                                            // starts within 10 us
+#define SYSCTL_RESBEHAVCTL_EXTRES_POR                                         \
+                                0x00000003  // External RST assertion issues a
+                                            // simulated POR sequence.
+                                            // Application starts less than 500
+                                            // us after deassertion (Default)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_HSSR register.
+//
+//*****************************************************************************
+#define SYSCTL_HSSR_KEY_M       0xFF000000  // Write Key
+#define SYSCTL_HSSR_CDOFF_M     0x00FFFFFF  // Command Descriptor Pointer
+#define SYSCTL_HSSR_KEY_S       24
+#define SYSCTL_HSSR_CDOFF_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C  // Memory Array Power Status
+#define SYSCTL_USBPDS_MEMSTAT_OFF                                             \
+                                0x00000000  // Array OFF
+#define SYSCTL_USBPDS_MEMSTAT_RETAIN                                          \
+                                0x00000004  // SRAM Retention
+#define SYSCTL_USBPDS_MEMSTAT_ON                                              \
+                                0x0000000C  // Array On
+#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003  // Power Domain Status
+#define SYSCTL_USBPDS_PWRSTAT_OFF                                             \
+                                0x00000000  // OFF
+#define SYSCTL_USBPDS_PWRSTAT_ON                                              \
+                                0x00000003  // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_USBMPC_PWRCTL_M  0x00000003  // Memory Array Power Control
+#define SYSCTL_USBMPC_PWRCTL_OFF                                              \
+                                0x00000000  // Array OFF
+#define SYSCTL_USBMPC_PWRCTL_RETAIN                                           \
+                                0x00000001  // SRAM Retention
+#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACPDS_MEMSTAT_M                                              \
+                                0x0000000C  // Memory Array Power Status
+#define SYSCTL_EMACPDS_MEMSTAT_OFF                                            \
+                                0x00000000  // Array OFF
+#define SYSCTL_EMACPDS_MEMSTAT_ON                                             \
+                                0x0000000C  // Array On
+#define SYSCTL_EMACPDS_PWRSTAT_M                                              \
+                                0x00000003  // Power Domain Status
+#define SYSCTL_EMACPDS_PWRSTAT_OFF                                            \
+                                0x00000000  // OFF
+#define SYSCTL_EMACPDS_PWRSTAT_ON                                             \
+                                0x00000003  // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003  // Memory Array Power Control
+#define SYSCTL_EMACMPC_PWRCTL_OFF                                             \
+                                0x00000000  // Array OFF
+#define SYSCTL_EMACMPC_PWRCTL_ON                                              \
+                                0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LCDMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_LCDMPC_PWRCTL_M  0x00000003  // Memory Array Power Control
+#define SYSCTL_LCDMPC_PWRCTL_OFF                                              \
+                                0x00000000  // Array OFF
+#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1          0x00000002  // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0          0x00000001  // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Present
+#define SYSCTL_PPTIMER_P6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Present
+#define SYSCTL_PPTIMER_P5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Present
+#define SYSCTL_PPTIMER_P4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Present
+#define SYSCTL_PPTIMER_P3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Present
+#define SYSCTL_PPTIMER_P2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Present
+#define SYSCTL_PPTIMER_P1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Present
+#define SYSCTL_PPTIMER_P0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P17       0x00020000  // GPIO Port T Present
+#define SYSCTL_PPGPIO_P16       0x00010000  // GPIO Port S Present
+#define SYSCTL_PPGPIO_P15       0x00008000  // GPIO Port R Present
+#define SYSCTL_PPGPIO_P14       0x00004000  // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13       0x00002000  // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12       0x00001000  // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11       0x00000800  // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10       0x00000400  // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9        0x00000200  // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8        0x00000100  // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7        0x00000080  // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6        0x00000040  // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5        0x00000020  // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4        0x00000010  // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3        0x00000008  // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2        0x00000004  // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1        0x00000002  // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0         0x00000001  // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPI_P0         0x00000001  // EPI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0         0x00000001  // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7        0x00000080  // UART Module 7 Present
+#define SYSCTL_PPUART_P6        0x00000040  // UART Module 6 Present
+#define SYSCTL_PPUART_P5        0x00000020  // UART Module 5 Present
+#define SYSCTL_PPUART_P4        0x00000010  // UART Module 4 Present
+#define SYSCTL_PPUART_P3        0x00000008  // UART Module 3 Present
+#define SYSCTL_PPUART_P2        0x00000004  // UART Module 2 Present
+#define SYSCTL_PPUART_P1        0x00000002  // UART Module 1 Present
+#define SYSCTL_PPUART_P0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3         0x00000008  // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2         0x00000004  // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1         0x00000002  // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0         0x00000001  // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P9         0x00000200  // I2C Module 9 Present
+#define SYSCTL_PPI2C_P8         0x00000100  // I2C Module 8 Present
+#define SYSCTL_PPI2C_P7         0x00000080  // I2C Module 7 Present
+#define SYSCTL_PPI2C_P6         0x00000040  // I2C Module 6 Present
+#define SYSCTL_PPI2C_P5         0x00000020  // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4         0x00000010  // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3         0x00000008  // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2         0x00000004  // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1         0x00000002  // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0         0x00000001  // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0         0x00000001  // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPHY_P0        0x00000001  // Ethernet PHY Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1         0x00000002  // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0         0x00000001  // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1         0x00000002  // ADC Module 1 Present
+#define SYSCTL_PPADC_P0         0x00000001  // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0        0x00000001  // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1         0x00000002  // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0         0x00000001  // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1         0x00000002  // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0         0x00000001  // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLPC_P0         0x00000001  // LPC Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPECI_P0        0x00000001  // PECI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPFAN_P0         0x00000001  // FAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0      0x00000001  // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Present
+#define SYSCTL_PPWTIMER_P4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Present
+#define SYSCTL_PPWTIMER_P3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Present
+#define SYSCTL_PPWTIMER_P2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Present
+#define SYSCTL_PPWTIMER_P1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Present
+#define SYSCTL_PPWTIMER_P0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPRTS register.
+//
+//*****************************************************************************
+#define SYSCTL_PPRTS_P0         0x00000001  // RTS Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCCM_P0         0x00000001  // CRC and Cryptographic Modules
+                                            // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLCD_P0         0x00000001  // LCD Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PPOWIRE_P0       0x00000001  // 1-Wire Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEMAC_P0        0x00000001  // Ethernet Controller Module
+                                            // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIM_P0         0x00000001  // HIM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1          0x00000002  // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0          0x00000001  // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Software Reset
+#define SYSCTL_SRTIMER_R6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Software Reset
+#define SYSCTL_SRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Software Reset
+#define SYSCTL_SRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Software Reset
+#define SYSCTL_SRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Software Reset
+#define SYSCTL_SRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Software Reset
+#define SYSCTL_SRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Software Reset
+#define SYSCTL_SRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R17       0x00020000  // GPIO Port T Software Reset
+#define SYSCTL_SRGPIO_R16       0x00010000  // GPIO Port S Software Reset
+#define SYSCTL_SRGPIO_R15       0x00008000  // GPIO Port R Software Reset
+#define SYSCTL_SRGPIO_R14       0x00004000  // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13       0x00002000  // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12       0x00001000  // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11       0x00000800  // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10       0x00000400  // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9        0x00000200  // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8        0x00000100  // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7        0x00000080  // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6        0x00000040  // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5        0x00000020  // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4        0x00000010  // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3        0x00000008  // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2        0x00000004  // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1        0x00000002  // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0        0x00000001  // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0         0x00000001  // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPI_R0         0x00000001  // EPI Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0         0x00000001  // Hibernation Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7        0x00000080  // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6        0x00000040  // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5        0x00000020  // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4        0x00000010  // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3        0x00000008  // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2        0x00000004  // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1        0x00000002  // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0        0x00000001  // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3         0x00000008  // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2         0x00000004  // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1         0x00000002  // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0         0x00000001  // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R9         0x00000200  // I2C Module 9 Software Reset
+#define SYSCTL_SRI2C_R8         0x00000100  // I2C Module 8 Software Reset
+#define SYSCTL_SRI2C_R7         0x00000080  // I2C Module 7 Software Reset
+#define SYSCTL_SRI2C_R6         0x00000040  // I2C Module 6 Software Reset
+#define SYSCTL_SRI2C_R5         0x00000020  // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4         0x00000010  // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3         0x00000008  // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2         0x00000004  // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1         0x00000002  // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0         0x00000001  // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0         0x00000001  // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPHY_R0        0x00000001  // Ethernet PHY Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1         0x00000002  // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0         0x00000001  // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1         0x00000002  // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0         0x00000001  // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1         0x00000002  // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0         0x00000001  // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1         0x00000002  // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0         0x00000001  // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0      0x00000001  // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCCM_R0         0x00000001  // CRC and Cryptographic Modules
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRLCD_R0         0x00000001  // LCD Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_SROWIRE_R0       0x00000001  // 1-Wire Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_SREMAC_R0        0x00000001  // Ethernet Controller MAC Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1        0x00000002  // Watchdog Timer 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCWD_R0        0x00000001  // Watchdog Timer 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R17     0x00020000  // GPIO Port T Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R16     0x00010000  // GPIO Port S Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R15     0x00008000  // GPIO Port R Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R14     0x00004000  // GPIO Port Q Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R13     0x00002000  // GPIO Port P Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R12     0x00001000  // GPIO Port N Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R11     0x00000800  // GPIO Port M Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R10     0x00000400  // GPIO Port L Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R9      0x00000200  // GPIO Port K Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R8      0x00000100  // GPIO Port J Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R7      0x00000080  // GPIO Port H Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R6      0x00000040  // GPIO Port G Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R5      0x00000020  // GPIO Port F Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R4      0x00000010  // GPIO Port E Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R3      0x00000008  // GPIO Port D Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R2      0x00000004  // GPIO Port C Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R1      0x00000002  // GPIO Port B Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R0      0x00000001  // GPIO Port A Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0       0x00000001  // uDMA Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPI_R0       0x00000001  // EPI Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0       0x00000001  // Hibernation Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7      0x00000080  // UART Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R6      0x00000040  // UART Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R5      0x00000020  // UART Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R4      0x00000010  // UART Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R3      0x00000008  // UART Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R2      0x00000004  // UART Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R1      0x00000002  // UART Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R0      0x00000001  // UART Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3       0x00000008  // SSI Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R2       0x00000004  // SSI Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R1       0x00000002  // SSI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R0       0x00000001  // SSI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R9       0x00000200  // I2C Module 9 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R8       0x00000100  // I2C Module 8 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R7       0x00000080  // I2C Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R6       0x00000040  // I2C Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R5       0x00000020  // I2C Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R4       0x00000010  // I2C Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R3       0x00000008  // I2C Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R2       0x00000004  // I2C Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R1       0x00000002  // I2C Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R0       0x00000001  // I2C Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0       0x00000001  // USB Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPHY_R0      0x00000001  // Ethernet PHY Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1       0x00000002  // CAN Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCCAN_R0       0x00000001  // CAN Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0      0x00000001  // Analog Comparator Module 0 Run
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1       0x00000002  // PWM Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCPWM_R0       0x00000001  // PWM Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1       0x00000002  // QEI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCQEI_R0       0x00000001  // QEI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0    0x00000001  // EEPROM Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCCM_R0       0x00000001  // CRC and Cryptographic Modules
+                                            // Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCLCD_R0       0x00000001  // LCD Controller Module 0 Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCOWIRE_R0     0x00000001  // 1-Wire Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEMAC_R0      0x00000001  // Ethernet MAC Module 0 Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1        0x00000002  // Watchdog Timer 1 Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCWD_S0        0x00000001  // Watchdog Timer 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S17     0x00020000  // GPIO Port T Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S16     0x00010000  // GPIO Port S Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S15     0x00008000  // GPIO Port R Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S14     0x00004000  // GPIO Port Q Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S13     0x00002000  // GPIO Port P Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S12     0x00001000  // GPIO Port N Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S11     0x00000800  // GPIO Port M Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S10     0x00000400  // GPIO Port L Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S9      0x00000200  // GPIO Port K Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S8      0x00000100  // GPIO Port J Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S7      0x00000080  // GPIO Port H Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S6      0x00000040  // GPIO Port G Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S5      0x00000020  // GPIO Port F Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S4      0x00000010  // GPIO Port E Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S3      0x00000008  // GPIO Port D Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S2      0x00000004  // GPIO Port C Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S1      0x00000002  // GPIO Port B Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S0      0x00000001  // GPIO Port A Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0       0x00000001  // uDMA Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPI_S0       0x00000001  // EPI Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0       0x00000001  // Hibernation Module Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7      0x00000080  // UART Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S6      0x00000040  // UART Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S5      0x00000020  // UART Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S4      0x00000010  // UART Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S3      0x00000008  // UART Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S2      0x00000004  // UART Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S1      0x00000002  // UART Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S0      0x00000001  // UART Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3       0x00000008  // SSI Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S2       0x00000004  // SSI Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S1       0x00000002  // SSI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S0       0x00000001  // SSI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S9       0x00000200  // I2C Module 9 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S8       0x00000100  // I2C Module 8 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S7       0x00000080  // I2C Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S6       0x00000040  // I2C Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S5       0x00000020  // I2C Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S4       0x00000010  // I2C Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S3       0x00000008  // I2C Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S2       0x00000004  // I2C Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S1       0x00000002  // I2C Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S0       0x00000001  // I2C Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0       0x00000001  // USB Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPHY_S0      0x00000001  // PHY Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1       0x00000002  // CAN Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCCAN_S0       0x00000001  // CAN Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1       0x00000002  // ADC Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCADC_S0       0x00000001  // ADC Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0      0x00000001  // Analog Comparator Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1       0x00000002  // PWM Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCPWM_S0       0x00000001  // PWM Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1       0x00000002  // QEI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCQEI_S0       0x00000001  // QEI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0    0x00000001  // EEPROM Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCCM_S0       0x00000001  // CRC and Cryptographic Modules
+                                            // Sleep Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCLCD_S0       0x00000001  // LCD Controller Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCOWIRE_S0     0x00000001  // 1-Wire Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEMAC_S0      0x00000001  // Ethernet MAC Module 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1        0x00000002  // Watchdog Timer 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCWD_D0        0x00000001  // Watchdog Timer 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D17     0x00020000  // GPIO Port T Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D16     0x00010000  // GPIO Port S Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D15     0x00008000  // GPIO Port R Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D14     0x00004000  // GPIO Port Q Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13     0x00002000  // GPIO Port P Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12     0x00001000  // GPIO Port N Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11     0x00000800  // GPIO Port M Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10     0x00000400  // GPIO Port L Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9      0x00000200  // GPIO Port K Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8      0x00000100  // GPIO Port J Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7      0x00000080  // GPIO Port H Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6      0x00000040  // GPIO Port G Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5      0x00000020  // GPIO Port F Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4      0x00000010  // GPIO Port E Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3      0x00000008  // GPIO Port D Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2      0x00000004  // GPIO Port C Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1      0x00000002  // GPIO Port B Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0      0x00000001  // GPIO Port A Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0       0x00000001  // uDMA Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPI_D0       0x00000001  // EPI Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0       0x00000001  // Hibernation Module Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7      0x00000080  // UART Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D6      0x00000040  // UART Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D5      0x00000020  // UART Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D4      0x00000010  // UART Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D3      0x00000008  // UART Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D2      0x00000004  // UART Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D1      0x00000002  // UART Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D0      0x00000001  // UART Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3       0x00000008  // SSI Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2       0x00000004  // SSI Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1       0x00000002  // SSI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0       0x00000001  // SSI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D9       0x00000200  // I2C Module 9 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D8       0x00000100  // I2C Module 8 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D7       0x00000080  // I2C Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D6       0x00000040  // I2C Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D5       0x00000020  // I2C Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4       0x00000010  // I2C Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3       0x00000008  // I2C Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2       0x00000004  // I2C Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1       0x00000002  // I2C Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0       0x00000001  // I2C Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0       0x00000001  // USB Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPHY_D0      0x00000001  // PHY Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1       0x00000002  // CAN Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0       0x00000001  // CAN Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1       0x00000002  // ADC Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCADC_D0       0x00000001  // ADC Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0      0x00000001  // Analog Comparator Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1       0x00000002  // PWM Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0       0x00000001  // PWM Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1       0x00000002  // QEI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0       0x00000001  // QEI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0    0x00000001  // EEPROM Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCCM_D0       0x00000001  // CRC and Cryptographic Modules
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCLCD_D0       0x00000001  // LCD Controller Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCOWIRE_D0     0x00000001  // 1-Wire Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEMAC_D0      0x00000001  // Ethernet MAC Module 0 Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWD_P1          0x00000002  // Watchdog Timer 1 Power Control
+#define SYSCTL_PCWD_P0          0x00000001  // Watchdog Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PCTIMER_P7       0x00000080  // General-Purpose Timer 7 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P6       0x00000040  // General-Purpose Timer 6 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P5       0x00000020  // General-Purpose Timer 5 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P4       0x00000010  // General-Purpose Timer 4 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P3       0x00000008  // General-Purpose Timer 3 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P2       0x00000004  // General-Purpose Timer 2 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P1       0x00000002  // General-Purpose Timer 1 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P0       0x00000001  // General-Purpose Timer 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PCGPIO_P17       0x00020000  // GPIO Port T Power Control
+#define SYSCTL_PCGPIO_P16       0x00010000  // GPIO Port S Power Control
+#define SYSCTL_PCGPIO_P15       0x00008000  // GPIO Port R Power Control
+#define SYSCTL_PCGPIO_P14       0x00004000  // GPIO Port Q Power Control
+#define SYSCTL_PCGPIO_P13       0x00002000  // GPIO Port P Power Control
+#define SYSCTL_PCGPIO_P12       0x00001000  // GPIO Port N Power Control
+#define SYSCTL_PCGPIO_P11       0x00000800  // GPIO Port M Power Control
+#define SYSCTL_PCGPIO_P10       0x00000400  // GPIO Port L Power Control
+#define SYSCTL_PCGPIO_P9        0x00000200  // GPIO Port K Power Control
+#define SYSCTL_PCGPIO_P8        0x00000100  // GPIO Port J Power Control
+#define SYSCTL_PCGPIO_P7        0x00000080  // GPIO Port H Power Control
+#define SYSCTL_PCGPIO_P6        0x00000040  // GPIO Port G Power Control
+#define SYSCTL_PCGPIO_P5        0x00000020  // GPIO Port F Power Control
+#define SYSCTL_PCGPIO_P4        0x00000010  // GPIO Port E Power Control
+#define SYSCTL_PCGPIO_P3        0x00000008  // GPIO Port D Power Control
+#define SYSCTL_PCGPIO_P2        0x00000004  // GPIO Port C Power Control
+#define SYSCTL_PCGPIO_P1        0x00000002  // GPIO Port B Power Control
+#define SYSCTL_PCGPIO_P0        0x00000001  // GPIO Port A Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PCDMA_P0         0x00000001  // uDMA Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPI_P0         0x00000001  // EPI Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCHIB_P0         0x00000001  // Hibernation Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUART_P7        0x00000080  // UART Module 7 Power Control
+#define SYSCTL_PCUART_P6        0x00000040  // UART Module 6 Power Control
+#define SYSCTL_PCUART_P5        0x00000020  // UART Module 5 Power Control
+#define SYSCTL_PCUART_P4        0x00000010  // UART Module 4 Power Control
+#define SYSCTL_PCUART_P3        0x00000008  // UART Module 3 Power Control
+#define SYSCTL_PCUART_P2        0x00000004  // UART Module 2 Power Control
+#define SYSCTL_PCUART_P1        0x00000002  // UART Module 1 Power Control
+#define SYSCTL_PCUART_P0        0x00000001  // UART Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCSSI_P3         0x00000008  // SSI Module 3 Power Control
+#define SYSCTL_PCSSI_P2         0x00000004  // SSI Module 2 Power Control
+#define SYSCTL_PCSSI_P1         0x00000002  // SSI Module 1 Power Control
+#define SYSCTL_PCSSI_P0         0x00000001  // SSI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PCI2C_P9         0x00000200  // I2C Module 9 Power Control
+#define SYSCTL_PCI2C_P8         0x00000100  // I2C Module 8 Power Control
+#define SYSCTL_PCI2C_P7         0x00000080  // I2C Module 7 Power Control
+#define SYSCTL_PCI2C_P6         0x00000040  // I2C Module 6 Power Control
+#define SYSCTL_PCI2C_P5         0x00000020  // I2C Module 5 Power Control
+#define SYSCTL_PCI2C_P4         0x00000010  // I2C Module 4 Power Control
+#define SYSCTL_PCI2C_P3         0x00000008  // I2C Module 3 Power Control
+#define SYSCTL_PCI2C_P2         0x00000004  // I2C Module 2 Power Control
+#define SYSCTL_PCI2C_P1         0x00000002  // I2C Module 1 Power Control
+#define SYSCTL_PCI2C_P0         0x00000001  // I2C Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUSB_P0         0x00000001  // USB Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPHY_P0        0x00000001  // Ethernet PHY Module Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCAN_P1         0x00000002  // CAN Module 1 Power Control
+#define SYSCTL_PCCAN_P0         0x00000001  // CAN Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCADC_P1         0x00000002  // ADC Module 1 Power Control
+#define SYSCTL_PCADC_P0         0x00000001  // ADC Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PCACMP_P0        0x00000001  // Analog Comparator Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCPWM_P0         0x00000001  // PWM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCQEI_P0         0x00000001  // QEI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEEPROM_P0      0x00000001  // EEPROM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCCM_P0         0x00000001  // CRC and Cryptographic Modules
+                                            // Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCLCD_P0         0x00000001  // LCD Controller Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PCOWIRE_P0       0x00000001  // 1-Wire Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEMAC_P0        0x00000001  // Ethernet MAC Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1          0x00000002  // Watchdog Timer 1 Peripheral
+                                            // Ready
+#define SYSCTL_PRWD_R0          0x00000001  // Watchdog Timer 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Peripheral Ready
+#define SYSCTL_PRTIMER_R6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Peripheral Ready
+#define SYSCTL_PRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R17       0x00020000  // GPIO Port T Peripheral Ready
+#define SYSCTL_PRGPIO_R16       0x00010000  // GPIO Port S Peripheral Ready
+#define SYSCTL_PRGPIO_R15       0x00008000  // GPIO Port R Peripheral Ready
+#define SYSCTL_PRGPIO_R14       0x00004000  // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13       0x00002000  // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12       0x00001000  // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11       0x00000800  // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10       0x00000400  // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9        0x00000200  // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8        0x00000100  // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7        0x00000080  // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6        0x00000040  // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5        0x00000020  // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4        0x00000010  // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3        0x00000008  // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2        0x00000004  // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1        0x00000002  // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0        0x00000001  // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0         0x00000001  // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPI_R0         0x00000001  // EPI Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0         0x00000001  // Hibernation Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7        0x00000080  // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6        0x00000040  // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5        0x00000020  // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4        0x00000010  // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3        0x00000008  // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2        0x00000004  // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1        0x00000002  // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0        0x00000001  // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3         0x00000008  // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2         0x00000004  // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1         0x00000002  // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0         0x00000001  // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R9         0x00000200  // I2C Module 9 Peripheral Ready
+#define SYSCTL_PRI2C_R8         0x00000100  // I2C Module 8 Peripheral Ready
+#define SYSCTL_PRI2C_R7         0x00000080  // I2C Module 7 Peripheral Ready
+#define SYSCTL_PRI2C_R6         0x00000040  // I2C Module 6 Peripheral Ready
+#define SYSCTL_PRI2C_R5         0x00000020  // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4         0x00000010  // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3         0x00000008  // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2         0x00000004  // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1         0x00000002  // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0         0x00000001  // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0         0x00000001  // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPHY_R0        0x00000001  // Ethernet PHY Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1         0x00000002  // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0         0x00000001  // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1         0x00000002  // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0         0x00000001  // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1         0x00000002  // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0         0x00000001  // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0      0x00000001  // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCCM_R0         0x00000001  // CRC and Cryptographic Modules
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRLCD_R0         0x00000001  // LCD Controller Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PROWIRE_R0       0x00000001  // 1-Wire Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PREMAC_R0        0x00000001  // Ethernet MAC Module 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CCMCGREQ
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_CCMCGREQ_DESCFG  0x00000004  // DES Clock Gating Request
+#define SYSCTL_CCMCGREQ_AESCFG  0x00000002  // AES Clock Gating Request
+#define SYSCTL_CCMCGREQ_SHACFG  0x00000001  // SHA/MD5 Clock Gating Request
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_CLASS_BLIZZARD                                            \
+                                0x00050000  // Tiva(TM) C Series TM4C123-class
+                                            // microcontrollers
+#define SYSCTL_DID0_CLASS_SNOWFLAKE                                           \
+                                0x000A0000  // Tiva(TM) C Series TM4C129-class
+                                            // microcontrollers
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010  // VDDA Under BOR0 Status
+#define SYSCTL_PWRTC_VDD_UBOR0  0x00000001  // VDD Under BOR0 Status
+
+#endif
+
+#endif // __HW_SYSCTL_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_sysexc.h b/bsp/tm4c129x/libraries/inc/hw_sysexc.h
new file mode 100644
index 0000000000..99ac066877
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_sysexc.h
@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+// hw_sysexc.h - Macros used when accessing the system exception module.
+//
+// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSEXC_H__
+#define __HW_SYSEXC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Exception Module register
+// addresses.
+//
+//*****************************************************************************
+#define SYSEXC_RIS              0x400F9000  // System Exception Raw Interrupt
+                                            // Status
+#define SYSEXC_IM               0x400F9004  // System Exception Interrupt Mask
+#define SYSEXC_MIS              0x400F9008  // System Exception Masked
+                                            // Interrupt Status
+#define SYSEXC_IC               0x400F900C  // System Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPUFCMIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIOCMIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIDCMIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Clear
+
+#endif // __HW_SYSEXC_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_timer.h b/bsp/tm4c129x/libraries/inc/hw_timer.h
new file mode 100644
index 0000000000..af1750d812
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_timer.h
@@ -0,0 +1,700 @@
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG             0x00000000  // GPTM Configuration
+#define TIMER_O_TAMR            0x00000004  // GPTM Timer A Mode
+#define TIMER_O_TBMR            0x00000008  // GPTM Timer B Mode
+#define TIMER_O_CTL             0x0000000C  // GPTM Control
+#define TIMER_O_SYNC            0x00000010  // GPTM Synchronize
+#define TIMER_O_IMR             0x00000018  // GPTM Interrupt Mask
+#define TIMER_O_RIS             0x0000001C  // GPTM Raw Interrupt Status
+#define TIMER_O_MIS             0x00000020  // GPTM Masked Interrupt Status
+#define TIMER_O_ICR             0x00000024  // GPTM Interrupt Clear
+#define TIMER_O_TAILR           0x00000028  // GPTM Timer A Interval Load
+#define TIMER_O_TBILR           0x0000002C  // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR        0x00000030  // GPTM Timer A Match
+#define TIMER_O_TBMATCHR        0x00000034  // GPTM Timer B Match
+#define TIMER_O_TAPR            0x00000038  // GPTM Timer A Prescale
+#define TIMER_O_TBPR            0x0000003C  // GPTM Timer B Prescale
+#define TIMER_O_TAPMR           0x00000040  // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR           0x00000044  // GPTM TimerB Prescale Match
+#define TIMER_O_TAR             0x00000048  // GPTM Timer A
+#define TIMER_O_TBR             0x0000004C  // GPTM Timer B
+#define TIMER_O_TAV             0x00000050  // GPTM Timer A Value
+#define TIMER_O_TBV             0x00000054  // GPTM Timer B Value
+#define TIMER_O_RTCPD           0x00000058  // GPTM RTC Predivide
+#define TIMER_O_TAPS            0x0000005C  // GPTM Timer A Prescale Snapshot
+#define TIMER_O_TBPS            0x00000060  // GPTM Timer B Prescale Snapshot
+#define TIMER_O_TAPV            0x00000064  // GPTM Timer A Prescale Value
+#define TIMER_O_TBPV            0x00000068  // GPTM Timer B Prescale Value
+#define TIMER_O_DMAEV           0x0000006C  // GPTM DMA Event
+#define TIMER_O_ADCEV           0x00000070  // GPTM ADC Event
+#define TIMER_O_PP              0x00000FC0  // GPTM Peripheral Properties
+#define TIMER_O_CC              0x00000FC8  // GPTM Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit timer
+                                            // configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit
+                                            // real-time clock (RTC) counter
+                                            // configuration
+#define TIMER_CFG_16_BIT        0x00000004  // For a 16/32-bit timer, this
+                                            // value selects the 16-bit timer
+                                            // configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TCACT_M      0x0000E000  // Timer Compare Action Select
+#define TIMER_TAMR_TCACT_NONE   0x00000000  // Disable compare operations
+#define TIMER_TAMR_TCACT_TOGGLE 0x00002000  // Toggle State on Time-Out
+#define TIMER_TAMR_TCACT_CLRTO  0x00004000  // Clear CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTO  0x00006000  // Set CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTOGTO                                             \
+                                0x00008000  // Set CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TAMR_TCACT_CLRTOGTO                                             \
+                                0x0000A000  // Clear CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TAMR_TCACT_SETCLRTO                                             \
+                                0x0000C000  // Set CCP immediately and clear on
+                                            // Time-Out
+#define TIMER_TAMR_TCACT_CLRSETTO                                             \
+                                0x0000E000  // Clear CCP immediately and set on
+                                            // Time-Out
+#define TIMER_TAMR_TACINTD      0x00001000  // One-shot/Periodic Interrupt
+                                            // Disable
+#define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
+                                            // Operation
+#define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
+                                            // Update
+#define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
+                                            // Enable
+#define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TCACT_M      0x0000E000  // Timer Compare Action Select
+#define TIMER_TBMR_TCACT_NONE   0x00000000  // Disable compare operations
+#define TIMER_TBMR_TCACT_TOGGLE 0x00002000  // Toggle State on Time-Out
+#define TIMER_TBMR_TCACT_CLRTO  0x00004000  // Clear CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTO  0x00006000  // Set CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTOGTO                                             \
+                                0x00008000  // Set CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TBMR_TCACT_CLRTOGTO                                             \
+                                0x0000A000  // Clear CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TBMR_TCACT_SETCLRTO                                             \
+                                0x0000C000  // Set CCP immediately and clear on
+                                            // Time-Out
+#define TIMER_TBMR_TCACT_CLRSETTO                                             \
+                                0x0000E000  // Clear CCP immediately and set on
+                                            // Time-Out
+#define TIMER_TBMR_TBCINTD      0x00001000  // One-Shot/Periodic Interrupt
+                                            // Disable
+#define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
+                                            // Operation
+#define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
+                                            // Update
+#define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M    0x00C00000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000  // GPTM 32/64-Bit Timer 5 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT5_TA   0x00400000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT5_TB   0x00800000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M    0x00300000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000  // GPTM 32/64-Bit Timer 4 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT4_TA   0x00100000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT4_TB   0x00200000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M    0x000C0000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000  // GPTM 32/64-Bit Timer 3 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT3_TA   0x00040000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT3_TB   0x00080000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M    0x00030000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000  // GPTM 32/64-Bit Timer 2 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT2_TA   0x00010000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT2_TB   0x00020000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT7_M     0x0000C000  // Synchronize GPTM Timer 7
+#define TIMER_SYNC_SYNCT7_NONE  0x00000000  // GPT7 is not affected
+#define TIMER_SYNC_SYNCT7_TA    0x00004000  // A timeout event for Timer A of
+                                            // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TB    0x00008000  // A timeout event for Timer B of
+                                            // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TATB  0x0000C000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM7 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_M    0x0000C000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000  // GPTM 32/64-Bit Timer 1 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT1_TA   0x00004000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_TB   0x00008000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M    0x00003000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000  // GPTM 32/64-Bit Timer 0 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT0_TA   0x00001000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 0 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT0_TB   0x00002000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 0 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT6_M     0x00003000  // Synchronize GPTM Timer 6
+#define TIMER_SYNC_SYNCT6_NONE  0x00000000  // GPTM6 is not affected
+#define TIMER_SYNC_SYNCT6_TA    0x00001000  // A timeout event for Timer A of
+                                            // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TB    0x00002000  // A timeout event for Timer B of
+                                            // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TATB  0x00003000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM6 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT5_M     0x00000C00  // Synchronize GPTM Timer 5
+#define TIMER_SYNC_SYNCT5_NONE  0x00000000  // GPTM5 is not affected
+#define TIMER_SYNC_SYNCT5_TA    0x00000400  // A timeout event for Timer A of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TB    0x00000800  // A timeout event for Timer B of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TATB  0x00000C00  // A timeout event for both Timer A
+                                            // and Timer B of GPTM5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT4_M     0x00000300  // Synchronize GPTM Timer 4
+#define TIMER_SYNC_SYNCT4_NONE  0x00000000  // GPTM4 is not affected
+#define TIMER_SYNC_SYNCT4_TA    0x00000100  // A timeout event for Timer A of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TB    0x00000200  // A timeout event for Timer B of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TATB  0x00000300  // A timeout event for both Timer A
+                                            // and Timer B of GPTM4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT3_M     0x000000C0  // Synchronize GPTM Timer 3
+#define TIMER_SYNC_SYNCT3_NONE  0x00000000  // GPTM3 is not affected
+#define TIMER_SYNC_SYNCT3_TA    0x00000040  // A timeout event for Timer A of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TB    0x00000080  // A timeout event for Timer B of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TATB  0x000000C0  // A timeout event for both Timer A
+                                            // and Timer B of GPTM3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT2_M     0x00000030  // Synchronize GPTM Timer 2
+#define TIMER_SYNC_SYNCT2_NONE  0x00000000  // GPTM2 is not affected
+#define TIMER_SYNC_SYNCT2_TA    0x00000010  // A timeout event for Timer A of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TB    0x00000020  // A timeout event for Timer B of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TATB  0x00000030  // A timeout event for both Timer A
+                                            // and Timer B of GPTM2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT1_M     0x0000000C  // Synchronize GPTM Timer 1
+#define TIMER_SYNC_SYNCT1_NONE  0x00000000  // GPTM1 is not affected
+#define TIMER_SYNC_SYNCT1_TA    0x00000004  // A timeout event for Timer A of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TB    0x00000008  // A timeout event for Timer B of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TATB  0x0000000C  // A timeout event for both Timer A
+                                            // and Timer B of GPTM1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT0_M     0x00000003  // Synchronize GPTM Timer 0
+#define TIMER_SYNC_SYNCT0_NONE  0x00000000  // GPTM0 is not affected
+#define TIMER_SYNC_SYNCT0_TA    0x00000001  // A timeout event for Timer A of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TB    0x00000002  // A timeout event for Timer B of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TATB  0x00000003  // A timeout event for both Timer A
+                                            // and Timer B of GPTM0 is
+                                            // triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Interrupt Mask
+#define TIMER_IMR_DMABIM        0x00002000  // GPTM Timer B DMA Done Interrupt
+                                            // Mask
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_DMAAIM        0x00000020  // GPTM Timer A DMA Done Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Raw Interrupt Status
+#define TIMER_RIS_DMABRIS       0x00002000  // GPTM Timer B DMA Done Raw
+                                            // Interrupt Status
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_DMAARIS       0x00000020  // GPTM Timer A DMA Done Raw
+                                            // Interrupt Status
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Masked Interrupt Status
+#define TIMER_MIS_DMABMIS       0x00002000  // GPTM Timer B DMA Done Masked
+                                            // Interrupt
+#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_DMAAMIS       0x00000020  // GPTM Timer A DMA Done Masked
+                                            // Interrupt
+#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Interrupt Clear
+#define TIMER_ICR_DMABINT       0x00002000  // GPTM Timer B DMA Done Interrupt
+                                            // Clear
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_DMAAINT       0x00000020  // GPTM Timer A DMA Done Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
+                                            // Register
+#define TIMER_TAILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S     8
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S     8
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High
+                                            // Byte
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S   8
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High
+                                            // Byte
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S   8
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
+#define TIMER_TAR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
+#define TIMER_TBR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
+#define TIMER_TAV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
+#define TIMER_TBV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_DMAEV register.
+//
+//*****************************************************************************
+#define TIMER_DMAEV_TBMDMAEN    0x00000800  // GPTM B Mode Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_CBEDMAEN    0x00000400  // GPTM B Capture Event DMA Trigger
+                                            // Enable
+#define TIMER_DMAEV_CBMDMAEN    0x00000200  // GPTM B Capture Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TBTODMAEN   0x00000100  // GPTM B Time-Out Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TAMDMAEN    0x00000010  // GPTM A Mode Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_RTCDMAEN    0x00000008  // GPTM A RTC Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_CAEDMAEN    0x00000004  // GPTM A Capture Event DMA Trigger
+                                            // Enable
+#define TIMER_DMAEV_CAMDMAEN    0x00000002  // GPTM A Capture Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TATODMAEN   0x00000001  // GPTM A Time-Out Event DMA
+                                            // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ADCEV register.
+//
+//*****************************************************************************
+#define TIMER_ADCEV_TBMADCEN    0x00000800  // GPTM B Mode Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_CBEADCEN    0x00000400  // GPTM B Capture Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CBMADCEN    0x00000200  // GPTM B Capture Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TBTOADCEN   0x00000100  // GPTM B Time-Out Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TAMADCEN    0x00000010  // GPTM A Mode Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_RTCADCEN    0x00000008  // GPTM RTC Match Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CAEADCEN    0x00000004  // GPTM A Capture Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CAMADCEN    0x00000002  // GPTM A Capture Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TATOADCEN   0x00000001  // GPTM A Time-Out Event ADC
+                                            // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_ALTCLK         0x00000040  // Alternate Clock Source
+#define TIMER_PP_SYNCCNT        0x00000020  // Synchronize Start
+#define TIMER_PP_CHAIN          0x00000010  // Chain with Other Timers
+#define TIMER_PP_SIZE_M         0x0000000F  // Count Size
+#define TIMER_PP_SIZE_16        0x00000000  // Timer A and Timer B counters are
+                                            // 16 bits each with an 8-bit
+                                            // prescale counter
+#define TIMER_PP_SIZE_32        0x00000001  // Timer A and Timer B counters are
+                                            // 32 bits each with a 16-bit
+                                            // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CC register.
+//
+//*****************************************************************************
+#define TIMER_CC_ALTCLK         0x00000001  // Alternate Clock Source
+
+#endif // __HW_TIMER_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_types.h b/bsp/tm4c129x/libraries/inc/hw_types.h
new file mode 100644
index 0000000000..1f358757bb
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_types.h
@@ -0,0 +1,147 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x)                                                              \
+        (*((volatile uint32_t *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile uint16_t *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile uint8_t *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                     \
+              (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b)                                                       \
+        HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                    \
+               (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b)                                                       \
+        HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                    \
+               (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Tiva silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+//     if(CLASS_IS_TM4C123)
+//     {
+//         do some TM4C123-class specific code here.
+//     }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Tiva family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Tiva silicon.  Many compilers will then
+// detect the "hard-coded" conditionals, and appropriately optimize the code
+// blocks, eliminating any "unreachable" code.  This would result in a smaller
+// Driverlib, thus producing a smaller final application size, but at the cost
+// of limiting the Driverlib binary to a specific Tiva silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_TM4C123
+#define CLASS_IS_TM4C123                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123))
+#endif
+
+#ifndef CLASS_IS_TM4C129
+#define CLASS_IS_TM4C129                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+//*****************************************************************************
+//
+// For TivaWare 2.1, we removed all references to Tiva IC codenames from the
+// source.  To ensure that existing customer code doesn't break as a result
+// of this change, make sure that the old definitions are still available at
+// least for the time being.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123
+#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_uart.h b/bsp/tm4c129x/libraries/inc/hw_uart.h
new file mode 100644
index 0000000000..8480ae4f5b
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_uart.h
@@ -0,0 +1,367 @@
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR               0x00000000  // UART Data
+#define UART_O_RSR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_ECR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_FR               0x00000018  // UART Flag
+#define UART_O_ILPR             0x00000020  // UART IrDA Low-Power Register
+#define UART_O_IBRD             0x00000024  // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD             0x00000028  // UART Fractional Baud-Rate
+                                            // Divisor
+#define UART_O_LCRH             0x0000002C  // UART Line Control
+#define UART_O_CTL              0x00000030  // UART Control
+#define UART_O_IFLS             0x00000034  // UART Interrupt FIFO Level Select
+#define UART_O_IM               0x00000038  // UART Interrupt Mask
+#define UART_O_RIS              0x0000003C  // UART Raw Interrupt Status
+#define UART_O_MIS              0x00000040  // UART Masked Interrupt Status
+#define UART_O_ICR              0x00000044  // UART Interrupt Clear
+#define UART_O_DMACTL           0x00000048  // UART DMA Control
+#define UART_O_9BITADDR         0x000000A4  // UART 9-Bit Self Address
+#define UART_O_9BITAMASK        0x000000A8  // UART 9-Bit Self Address Mask
+#define UART_O_PP               0x00000FC0  // UART Peripheral Properties
+#define UART_O_CC               0x00000FC8  // UART Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_DMATXIM         0x00020000  // Transmit DMA Interrupt Mask
+#define UART_IM_DMARXIM         0x00010000  // Receive DMA Interrupt Mask
+#define UART_IM_9BITIM          0x00001000  // 9-Bit Mode Interrupt Mask
+#define UART_IM_EOTIM           0x00000800  // End of Transmission Interrupt
+                                            // Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Mask
+#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Mask
+#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Mask
+#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_DMATXRIS       0x00020000  // Transmit DMA Raw Interrupt
+                                            // Status
+#define UART_RIS_DMARXRIS       0x00010000  // Receive DMA Raw Interrupt Status
+#define UART_RIS_9BITRIS        0x00001000  // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_EOTRIS         0x00000800  // End of Transmission Raw
+                                            // Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
+#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_DMATXMIS       0x00020000  // Transmit DMA Masked Interrupt
+                                            // Status
+#define UART_MIS_DMARXMIS       0x00010000  // Receive DMA Masked Interrupt
+                                            // Status
+#define UART_MIS_9BITMIS        0x00001000  // 9-Bit Mode Masked Interrupt
+                                            // Status
+#define UART_MIS_EOTMIS         0x00000800  // End of Transmission Masked
+                                            // Interrupt Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
+#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_DMATXIC        0x00020000  // Transmit DMA Interrupt Clear
+#define UART_ICR_DMARXIC        0x00010000  // Receive DMA Interrupt Clear
+#define UART_ICR_9BITIC         0x00001000  // 9-Bit Mode Interrupt Clear
+#define UART_ICR_EOTIC          0x00000800  // End of Transmission Interrupt
+                                            // Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
+#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Clear
+#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN    0x00008000  // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M    0x000000FF  // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M   0x000000FF  // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_MSE             0x00000008  // Modem Support Extended
+#define UART_PP_MS              0x00000004  // Modem Support
+#define UART_PP_NB              0x00000002  // 9-Bit Support
+#define UART_PP_SC              0x00000001  // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M            0x0000000F  // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK       0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define UART_CC_CS_PIOSC        0x00000005  // PIOSC
+
+#endif // __HW_UART_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_udma.h b/bsp/tm4c129x/libraries/inc/hw_udma.h
new file mode 100644
index 0000000000..ea6cbbce4c
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_udma.h
@@ -0,0 +1,414 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
+//
+//*****************************************************************************
+#define UDMA_STAT               0x400FF000  // DMA Status
+#define UDMA_CFG                0x400FF004  // DMA Configuration
+#define UDMA_CTLBASE            0x400FF008  // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE            0x400FF00C  // DMA Alternate Channel Control
+                                            // Base Pointer
+#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait-on-Request
+                                            // Status
+#define UDMA_SWREQ              0x400FF014  // DMA Channel Software Request
+#define UDMA_USEBURSTSET        0x400FF018  // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR        0x400FF01C  // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET         0x400FF020  // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR         0x400FF024  // DMA Channel Request Mask Clear
+#define UDMA_ENASET             0x400FF028  // DMA Channel Enable Set
+#define UDMA_ENACLR             0x400FF02C  // DMA Channel Enable Clear
+#define UDMA_ALTSET             0x400FF030  // DMA Channel Primary Alternate
+                                            // Set
+#define UDMA_ALTCLR             0x400FF034  // DMA Channel Primary Alternate
+                                            // Clear
+#define UDMA_PRIOSET            0x400FF038  // DMA Channel Priority Set
+#define UDMA_PRIOCLR            0x400FF03C  // DMA Channel Priority Clear
+#define UDMA_ERRCLR             0x400FF04C  // DMA Bus Error Clear
+#define UDMA_CHASGN             0x400FF500  // DMA Channel Assignment
+#define UDMA_CHIS               0x400FF504  // DMA Channel Interrupt Status
+#define UDMA_CHMAP0             0x400FF510  // DMA Channel Map Select 0
+#define UDMA_CHMAP1             0x400FF514  // DMA Channel Map Select 1
+#define UDMA_CHMAP2             0x400FF518  // DMA Channel Map Select 2
+#define UDMA_CHMAP3             0x400FF51C  // DMA Channel Map Select 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP                                            \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP                                            \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT                                             \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT                                             \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M    0xF0000000  // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M    0x0F000000  // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M    0x00F00000  // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M    0x000F0000  // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M    0x0000F000  // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M    0x00000F00  // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M    0x000000F0  // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M    0x0000000F  // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S    28
+#define UDMA_CHMAP0_CH6SEL_S    24
+#define UDMA_CHMAP0_CH5SEL_S    20
+#define UDMA_CHMAP0_CH4SEL_S    16
+#define UDMA_CHMAP0_CH3SEL_S    12
+#define UDMA_CHMAP0_CH2SEL_S    8
+#define UDMA_CHMAP0_CH1SEL_S    4
+#define UDMA_CHMAP0_CH0SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M   0xF0000000  // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M   0x0F000000  // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M   0x00F00000  // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M   0x000F0000  // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M   0x0000F000  // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M   0x00000F00  // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M    0x000000F0  // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M    0x0000000F  // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S   28
+#define UDMA_CHMAP1_CH14SEL_S   24
+#define UDMA_CHMAP1_CH13SEL_S   20
+#define UDMA_CHMAP1_CH12SEL_S   16
+#define UDMA_CHMAP1_CH11SEL_S   12
+#define UDMA_CHMAP1_CH10SEL_S   8
+#define UDMA_CHMAP1_CH9SEL_S    4
+#define UDMA_CHMAP1_CH8SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M   0xF0000000  // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M   0x0F000000  // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M   0x00F00000  // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M   0x000F0000  // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M   0x0000F000  // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M   0x00000F00  // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M   0x000000F0  // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M   0x0000000F  // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S   28
+#define UDMA_CHMAP2_CH22SEL_S   24
+#define UDMA_CHMAP2_CH21SEL_S   20
+#define UDMA_CHMAP2_CH20SEL_S   16
+#define UDMA_CHMAP2_CH19SEL_S   12
+#define UDMA_CHMAP2_CH18SEL_S   8
+#define UDMA_CHMAP2_CH17SEL_S   4
+#define UDMA_CHMAP2_CH16SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M   0xF0000000  // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M   0x0F000000  // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M   0x00F00000  // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M   0x000F0000  // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M   0x0000F000  // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M   0x00000F00  // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M   0x000000F0  // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M   0x0000000F  // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S   28
+#define UDMA_CHMAP3_CH30SEL_S   24
+#define UDMA_CHMAP3_CH29SEL_S   20
+#define UDMA_CHMAP3_CH28SEL_S   16
+#define UDMA_CHMAP3_CH27SEL_S   12
+#define UDMA_CHMAP3_CH26SEL_S   8
+#define UDMA_CHMAP3_CH25SEL_S   4
+#define UDMA_CHMAP3_CH24SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_O_DSTENDP          0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_O_CHCTL            0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_DSTPROT0     0x00200000  // Destination Privilege Access
+#define UDMA_CHCTL_SRCPROT0     0x00040000  // Source Privilege Access
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP                                              \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC                                             \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO                                              \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG                                          \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG                                            \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA                                           \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG                                            \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA                                           \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
+
+#endif // __HW_UDMA_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_usb.h b/bsp/tm4c129x/libraries/inc/hw_usb.h
new file mode 100644
index 0000000000..059ca12514
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_usb.h
@@ -0,0 +1,3032 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus register offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR             0x00000000  // USB Device Functional Address
+#define USB_O_POWER             0x00000001  // USB Power
+#define USB_O_TXIS              0x00000002  // USB Transmit Interrupt Status
+#define USB_O_RXIS              0x00000004  // USB Receive Interrupt Status
+#define USB_O_TXIE              0x00000006  // USB Transmit Interrupt Enable
+#define USB_O_RXIE              0x00000008  // USB Receive Interrupt Enable
+#define USB_O_IS                0x0000000A  // USB General Interrupt Status
+#define USB_O_IE                0x0000000B  // USB Interrupt Enable
+#define USB_O_FRAME             0x0000000C  // USB Frame Value
+#define USB_O_EPIDX             0x0000000E  // USB Endpoint Index
+#define USB_O_TEST              0x0000000F  // USB Test Mode
+#define USB_O_FIFO0             0x00000020  // USB FIFO Endpoint 0
+#define USB_O_FIFO1             0x00000024  // USB FIFO Endpoint 1
+#define USB_O_FIFO2             0x00000028  // USB FIFO Endpoint 2
+#define USB_O_FIFO3             0x0000002C  // USB FIFO Endpoint 3
+#define USB_O_FIFO4             0x00000030  // USB FIFO Endpoint 4
+#define USB_O_FIFO5             0x00000034  // USB FIFO Endpoint 5
+#define USB_O_FIFO6             0x00000038  // USB FIFO Endpoint 6
+#define USB_O_FIFO7             0x0000003C  // USB FIFO Endpoint 7
+#define USB_O_DEVCTL            0x00000060  // USB Device Control
+#define USB_O_CCONF             0x00000061  // USB Common Configuration
+#define USB_O_TXFIFOSZ          0x00000062  // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ          0x00000063  // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD         0x00000064  // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD         0x00000066  // USB Receive FIFO Start Address
+#define USB_O_ULPIVBUSCTL       0x00000070  // USB ULPI VBUS Control
+#define USB_O_ULPIREGDATA       0x00000074  // USB ULPI Register Data
+#define USB_O_ULPIREGADDR       0x00000075  // USB ULPI Register Address
+#define USB_O_ULPIREGCTL        0x00000076  // USB ULPI Register Control
+#define USB_O_EPINFO            0x00000078  // USB Endpoint Information
+#define USB_O_RAMINFO           0x00000079  // USB RAM Information
+#define USB_O_CONTIM            0x0000007A  // USB Connect Timing
+#define USB_O_VPLEN             0x0000007B  // USB OTG VBUS Pulse Timing
+#define USB_O_HSEOF             0x0000007C  // USB High-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_FSEOF             0x0000007D  // USB Full-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_LSEOF             0x0000007E  // USB Low-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_TXFUNCADDR0       0x00000080  // USB Transmit Functional Address
+                                            // Endpoint 0
+#define USB_O_TXHUBADDR0        0x00000082  // USB Transmit Hub Address
+                                            // Endpoint 0
+#define USB_O_TXHUBPORT0        0x00000083  // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1       0x00000088  // USB Transmit Functional Address
+                                            // Endpoint 1
+#define USB_O_TXHUBADDR1        0x0000008A  // USB Transmit Hub Address
+                                            // Endpoint 1
+#define USB_O_TXHUBPORT1        0x0000008B  // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1       0x0000008C  // USB Receive Functional Address
+                                            // Endpoint 1
+#define USB_O_RXHUBADDR1        0x0000008E  // USB Receive Hub Address Endpoint
+                                            // 1
+#define USB_O_RXHUBPORT1        0x0000008F  // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2       0x00000090  // USB Transmit Functional Address
+                                            // Endpoint 2
+#define USB_O_TXHUBADDR2        0x00000092  // USB Transmit Hub Address
+                                            // Endpoint 2
+#define USB_O_TXHUBPORT2        0x00000093  // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2       0x00000094  // USB Receive Functional Address
+                                            // Endpoint 2
+#define USB_O_RXHUBADDR2        0x00000096  // USB Receive Hub Address Endpoint
+                                            // 2
+#define USB_O_RXHUBPORT2        0x00000097  // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3       0x00000098  // USB Transmit Functional Address
+                                            // Endpoint 3
+#define USB_O_TXHUBADDR3        0x0000009A  // USB Transmit Hub Address
+                                            // Endpoint 3
+#define USB_O_TXHUBPORT3        0x0000009B  // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3       0x0000009C  // USB Receive Functional Address
+                                            // Endpoint 3
+#define USB_O_RXHUBADDR3        0x0000009E  // USB Receive Hub Address Endpoint
+                                            // 3
+#define USB_O_RXHUBPORT3        0x0000009F  // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4       0x000000A0  // USB Transmit Functional Address
+                                            // Endpoint 4
+#define USB_O_TXHUBADDR4        0x000000A2  // USB Transmit Hub Address
+                                            // Endpoint 4
+#define USB_O_TXHUBPORT4        0x000000A3  // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4       0x000000A4  // USB Receive Functional Address
+                                            // Endpoint 4
+#define USB_O_RXHUBADDR4        0x000000A6  // USB Receive Hub Address Endpoint
+                                            // 4
+#define USB_O_RXHUBPORT4        0x000000A7  // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5       0x000000A8  // USB Transmit Functional Address
+                                            // Endpoint 5
+#define USB_O_TXHUBADDR5        0x000000AA  // USB Transmit Hub Address
+                                            // Endpoint 5
+#define USB_O_TXHUBPORT5        0x000000AB  // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5       0x000000AC  // USB Receive Functional Address
+                                            // Endpoint 5
+#define USB_O_RXHUBADDR5        0x000000AE  // USB Receive Hub Address Endpoint
+                                            // 5
+#define USB_O_RXHUBPORT5        0x000000AF  // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6       0x000000B0  // USB Transmit Functional Address
+                                            // Endpoint 6
+#define USB_O_TXHUBADDR6        0x000000B2  // USB Transmit Hub Address
+                                            // Endpoint 6
+#define USB_O_TXHUBPORT6        0x000000B3  // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6       0x000000B4  // USB Receive Functional Address
+                                            // Endpoint 6
+#define USB_O_RXHUBADDR6        0x000000B6  // USB Receive Hub Address Endpoint
+                                            // 6
+#define USB_O_RXHUBPORT6        0x000000B7  // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7       0x000000B8  // USB Transmit Functional Address
+                                            // Endpoint 7
+#define USB_O_TXHUBADDR7        0x000000BA  // USB Transmit Hub Address
+                                            // Endpoint 7
+#define USB_O_TXHUBPORT7        0x000000BB  // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7       0x000000BC  // USB Receive Functional Address
+                                            // Endpoint 7
+#define USB_O_RXHUBADDR7        0x000000BE  // USB Receive Hub Address Endpoint
+                                            // 7
+#define USB_O_RXHUBPORT7        0x000000BF  // USB Receive Hub Port Endpoint 7
+#define USB_O_CSRL0             0x00000102  // USB Control and Status Endpoint
+                                            // 0 Low
+#define USB_O_CSRH0             0x00000103  // USB Control and Status Endpoint
+                                            // 0 High
+#define USB_O_COUNT0            0x00000108  // USB Receive Byte Count Endpoint
+                                            // 0
+#define USB_O_TYPE0             0x0000010A  // USB Type Endpoint 0
+#define USB_O_NAKLMT            0x0000010B  // USB NAK Limit
+#define USB_O_TXMAXP1           0x00000110  // USB Maximum Transmit Data
+                                            // Endpoint 1
+#define USB_O_TXCSRL1           0x00000112  // USB Transmit Control and Status
+                                            // Endpoint 1 Low
+#define USB_O_TXCSRH1           0x00000113  // USB Transmit Control and Status
+                                            // Endpoint 1 High
+#define USB_O_RXMAXP1           0x00000114  // USB Maximum Receive Data
+                                            // Endpoint 1
+#define USB_O_RXCSRL1           0x00000116  // USB Receive Control and Status
+                                            // Endpoint 1 Low
+#define USB_O_RXCSRH1           0x00000117  // USB Receive Control and Status
+                                            // Endpoint 1 High
+#define USB_O_RXCOUNT1          0x00000118  // USB Receive Byte Count Endpoint
+                                            // 1
+#define USB_O_TXTYPE1           0x0000011A  // USB Host Transmit Configure Type
+                                            // Endpoint 1
+#define USB_O_TXINTERVAL1       0x0000011B  // USB Host Transmit Interval
+                                            // Endpoint 1
+#define USB_O_RXTYPE1           0x0000011C  // USB Host Configure Receive Type
+                                            // Endpoint 1
+#define USB_O_RXINTERVAL1       0x0000011D  // USB Host Receive Polling
+                                            // Interval Endpoint 1
+#define USB_O_TXMAXP2           0x00000120  // USB Maximum Transmit Data
+                                            // Endpoint 2
+#define USB_O_TXCSRL2           0x00000122  // USB Transmit Control and Status
+                                            // Endpoint 2 Low
+#define USB_O_TXCSRH2           0x00000123  // USB Transmit Control and Status
+                                            // Endpoint 2 High
+#define USB_O_RXMAXP2           0x00000124  // USB Maximum Receive Data
+                                            // Endpoint 2
+#define USB_O_RXCSRL2           0x00000126  // USB Receive Control and Status
+                                            // Endpoint 2 Low
+#define USB_O_RXCSRH2           0x00000127  // USB Receive Control and Status
+                                            // Endpoint 2 High
+#define USB_O_RXCOUNT2          0x00000128  // USB Receive Byte Count Endpoint
+                                            // 2
+#define USB_O_TXTYPE2           0x0000012A  // USB Host Transmit Configure Type
+                                            // Endpoint 2
+#define USB_O_TXINTERVAL2       0x0000012B  // USB Host Transmit Interval
+                                            // Endpoint 2
+#define USB_O_RXTYPE2           0x0000012C  // USB Host Configure Receive Type
+                                            // Endpoint 2
+#define USB_O_RXINTERVAL2       0x0000012D  // USB Host Receive Polling
+                                            // Interval Endpoint 2
+#define USB_O_TXMAXP3           0x00000130  // USB Maximum Transmit Data
+                                            // Endpoint 3
+#define USB_O_TXCSRL3           0x00000132  // USB Transmit Control and Status
+                                            // Endpoint 3 Low
+#define USB_O_TXCSRH3           0x00000133  // USB Transmit Control and Status
+                                            // Endpoint 3 High
+#define USB_O_RXMAXP3           0x00000134  // USB Maximum Receive Data
+                                            // Endpoint 3
+#define USB_O_RXCSRL3           0x00000136  // USB Receive Control and Status
+                                            // Endpoint 3 Low
+#define USB_O_RXCSRH3           0x00000137  // USB Receive Control and Status
+                                            // Endpoint 3 High
+#define USB_O_RXCOUNT3          0x00000138  // USB Receive Byte Count Endpoint
+                                            // 3
+#define USB_O_TXTYPE3           0x0000013A  // USB Host Transmit Configure Type
+                                            // Endpoint 3
+#define USB_O_TXINTERVAL3       0x0000013B  // USB Host Transmit Interval
+                                            // Endpoint 3
+#define USB_O_RXTYPE3           0x0000013C  // USB Host Configure Receive Type
+                                            // Endpoint 3
+#define USB_O_RXINTERVAL3       0x0000013D  // USB Host Receive Polling
+                                            // Interval Endpoint 3
+#define USB_O_TXMAXP4           0x00000140  // USB Maximum Transmit Data
+                                            // Endpoint 4
+#define USB_O_TXCSRL4           0x00000142  // USB Transmit Control and Status
+                                            // Endpoint 4 Low
+#define USB_O_TXCSRH4           0x00000143  // USB Transmit Control and Status
+                                            // Endpoint 4 High
+#define USB_O_RXMAXP4           0x00000144  // USB Maximum Receive Data
+                                            // Endpoint 4
+#define USB_O_RXCSRL4           0x00000146  // USB Receive Control and Status
+                                            // Endpoint 4 Low
+#define USB_O_RXCSRH4           0x00000147  // USB Receive Control and Status
+                                            // Endpoint 4 High
+#define USB_O_RXCOUNT4          0x00000148  // USB Receive Byte Count Endpoint
+                                            // 4
+#define USB_O_TXTYPE4           0x0000014A  // USB Host Transmit Configure Type
+                                            // Endpoint 4
+#define USB_O_TXINTERVAL4       0x0000014B  // USB Host Transmit Interval
+                                            // Endpoint 4
+#define USB_O_RXTYPE4           0x0000014C  // USB Host Configure Receive Type
+                                            // Endpoint 4
+#define USB_O_RXINTERVAL4       0x0000014D  // USB Host Receive Polling
+                                            // Interval Endpoint 4
+#define USB_O_TXMAXP5           0x00000150  // USB Maximum Transmit Data
+                                            // Endpoint 5
+#define USB_O_TXCSRL5           0x00000152  // USB Transmit Control and Status
+                                            // Endpoint 5 Low
+#define USB_O_TXCSRH5           0x00000153  // USB Transmit Control and Status
+                                            // Endpoint 5 High
+#define USB_O_RXMAXP5           0x00000154  // USB Maximum Receive Data
+                                            // Endpoint 5
+#define USB_O_RXCSRL5           0x00000156  // USB Receive Control and Status
+                                            // Endpoint 5 Low
+#define USB_O_RXCSRH5           0x00000157  // USB Receive Control and Status
+                                            // Endpoint 5 High
+#define USB_O_RXCOUNT5          0x00000158  // USB Receive Byte Count Endpoint
+                                            // 5
+#define USB_O_TXTYPE5           0x0000015A  // USB Host Transmit Configure Type
+                                            // Endpoint 5
+#define USB_O_TXINTERVAL5       0x0000015B  // USB Host Transmit Interval
+                                            // Endpoint 5
+#define USB_O_RXTYPE5           0x0000015C  // USB Host Configure Receive Type
+                                            // Endpoint 5
+#define USB_O_RXINTERVAL5       0x0000015D  // USB Host Receive Polling
+                                            // Interval Endpoint 5
+#define USB_O_TXMAXP6           0x00000160  // USB Maximum Transmit Data
+                                            // Endpoint 6
+#define USB_O_TXCSRL6           0x00000162  // USB Transmit Control and Status
+                                            // Endpoint 6 Low
+#define USB_O_TXCSRH6           0x00000163  // USB Transmit Control and Status
+                                            // Endpoint 6 High
+#define USB_O_RXMAXP6           0x00000164  // USB Maximum Receive Data
+                                            // Endpoint 6
+#define USB_O_RXCSRL6           0x00000166  // USB Receive Control and Status
+                                            // Endpoint 6 Low
+#define USB_O_RXCSRH6           0x00000167  // USB Receive Control and Status
+                                            // Endpoint 6 High
+#define USB_O_RXCOUNT6          0x00000168  // USB Receive Byte Count Endpoint
+                                            // 6
+#define USB_O_TXTYPE6           0x0000016A  // USB Host Transmit Configure Type
+                                            // Endpoint 6
+#define USB_O_TXINTERVAL6       0x0000016B  // USB Host Transmit Interval
+                                            // Endpoint 6
+#define USB_O_RXTYPE6           0x0000016C  // USB Host Configure Receive Type
+                                            // Endpoint 6
+#define USB_O_RXINTERVAL6       0x0000016D  // USB Host Receive Polling
+                                            // Interval Endpoint 6
+#define USB_O_TXMAXP7           0x00000170  // USB Maximum Transmit Data
+                                            // Endpoint 7
+#define USB_O_TXCSRL7           0x00000172  // USB Transmit Control and Status
+                                            // Endpoint 7 Low
+#define USB_O_TXCSRH7           0x00000173  // USB Transmit Control and Status
+                                            // Endpoint 7 High
+#define USB_O_RXMAXP7           0x00000174  // USB Maximum Receive Data
+                                            // Endpoint 7
+#define USB_O_RXCSRL7           0x00000176  // USB Receive Control and Status
+                                            // Endpoint 7 Low
+#define USB_O_RXCSRH7           0x00000177  // USB Receive Control and Status
+                                            // Endpoint 7 High
+#define USB_O_RXCOUNT7          0x00000178  // USB Receive Byte Count Endpoint
+                                            // 7
+#define USB_O_TXTYPE7           0x0000017A  // USB Host Transmit Configure Type
+                                            // Endpoint 7
+#define USB_O_TXINTERVAL7       0x0000017B  // USB Host Transmit Interval
+                                            // Endpoint 7
+#define USB_O_RXTYPE7           0x0000017C  // USB Host Configure Receive Type
+                                            // Endpoint 7
+#define USB_O_RXINTERVAL7       0x0000017D  // USB Host Receive Polling
+                                            // Interval Endpoint 7
+#define USB_O_DMAINTR           0x00000200  // USB DMA Interrupt
+#define USB_O_DMACTL0           0x00000204  // USB DMA Control 0
+#define USB_O_DMAADDR0          0x00000208  // USB DMA Address 0
+#define USB_O_DMACOUNT0         0x0000020C  // USB DMA Count 0
+#define USB_O_DMACTL1           0x00000214  // USB DMA Control 1
+#define USB_O_DMAADDR1          0x00000218  // USB DMA Address 1
+#define USB_O_DMACOUNT1         0x0000021C  // USB DMA Count 1
+#define USB_O_DMACTL2           0x00000224  // USB DMA Control 2
+#define USB_O_DMAADDR2          0x00000228  // USB DMA Address 2
+#define USB_O_DMACOUNT2         0x0000022C  // USB DMA Count 2
+#define USB_O_DMACTL3           0x00000234  // USB DMA Control 3
+#define USB_O_DMAADDR3          0x00000238  // USB DMA Address 3
+#define USB_O_DMACOUNT3         0x0000023C  // USB DMA Count 3
+#define USB_O_DMACTL4           0x00000244  // USB DMA Control 4
+#define USB_O_DMAADDR4          0x00000248  // USB DMA Address 4
+#define USB_O_DMACOUNT4         0x0000024C  // USB DMA Count 4
+#define USB_O_DMACTL5           0x00000254  // USB DMA Control 5
+#define USB_O_DMAADDR5          0x00000258  // USB DMA Address 5
+#define USB_O_DMACOUNT5         0x0000025C  // USB DMA Count 5
+#define USB_O_DMACTL6           0x00000264  // USB DMA Control 6
+#define USB_O_DMAADDR6          0x00000268  // USB DMA Address 6
+#define USB_O_DMACOUNT6         0x0000026C  // USB DMA Count 6
+#define USB_O_DMACTL7           0x00000274  // USB DMA Control 7
+#define USB_O_DMAADDR7          0x00000278  // USB DMA Address 7
+#define USB_O_DMACOUNT7         0x0000027C  // USB DMA Count 7
+#define USB_O_RQPKTCOUNT1       0x00000304  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2       0x00000308  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3       0x0000030C  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4       0x00000310  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5       0x00000314  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6       0x00000318  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7       0x0000031C  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 7
+#define USB_O_RXDPKTBUFDIS      0x00000340  // USB Receive Double Packet Buffer
+                                            // Disable
+#define USB_O_TXDPKTBUFDIS      0x00000342  // USB Transmit Double Packet
+                                            // Buffer Disable
+#define USB_O_CTO               0x00000344  // USB Chirp Timeout
+#define USB_O_HHSRTN            0x00000346  // USB High Speed to UTM Operating
+                                            // Delay
+#define USB_O_HSBT              0x00000348  // USB High Speed Time-out Adder
+#define USB_O_LPMATTR           0x00000360  // USB LPM Attributes
+#define USB_O_LPMCNTRL          0x00000362  // USB LPM Control
+#define USB_O_LPMIM             0x00000363  // USB LPM Interrupt Mask
+#define USB_O_LPMRIS            0x00000364  // USB LPM Raw Interrupt Status
+#define USB_O_LPMFADDR          0x00000365  // USB LPM Function Address
+#define USB_O_EPC               0x00000400  // USB External Power Control
+#define USB_O_EPCRIS            0x00000404  // USB External Power Control Raw
+                                            // Interrupt Status
+#define USB_O_EPCIM             0x00000408  // USB External Power Control
+                                            // Interrupt Mask
+#define USB_O_EPCISC            0x0000040C  // USB External Power Control
+                                            // Interrupt Status and Clear
+#define USB_O_DRRIS             0x00000410  // USB Device RESUME Raw Interrupt
+                                            // Status
+#define USB_O_DRIM              0x00000414  // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC             0x00000418  // USB Device RESUME Interrupt
+                                            // Status and Clear
+#define USB_O_GPCS              0x0000041C  // USB General-Purpose Control and
+                                            // Status
+#define USB_O_VDC               0x00000430  // USB VBUS Droop Control
+#define USB_O_VDCRIS            0x00000434  // USB VBUS Droop Control Raw
+                                            // Interrupt Status
+#define USB_O_VDCIM             0x00000438  // USB VBUS Droop Control Interrupt
+                                            // Mask
+#define USB_O_VDCISC            0x0000043C  // USB VBUS Droop Control Interrupt
+                                            // Status and Clear
+#define USB_O_IDVRIS            0x00000444  // USB ID Valid Detect Raw
+                                            // Interrupt Status
+#define USB_O_IDVIM             0x00000448  // USB ID Valid Detect Interrupt
+                                            // Mask
+#define USB_O_IDVISC            0x0000044C  // USB ID Valid Detect Interrupt
+                                            // Status and Clear
+#define USB_O_DMASEL            0x00000450  // USB DMA Select
+#define USB_O_PP                0x00000FC0  // USB Peripheral Properties
+#define USB_O_PC                0x00000FC4  // USB Peripheral Configuration
+#define USB_O_CC                0x00000FC8  // USB Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_HSENAB        0x00000020  // High Speed Enable
+#define USB_POWER_HSMODE        0x00000010  // High Speed Enable
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)
+#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG
+                                            // only)
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG
+                                            // only)
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
+#define USB_TEST_FORCEHS        0x00000010  // Force High-Speed Mode
+#define USB_TEST_TESTPKT        0x00000008  // Test Packet Mode Enable
+#define USB_TEST_TESTK          0x00000004  // Test_K Mode Enable
+#define USB_TEST_TESTJ          0x00000002  // Test_J Mode Enable
+#define USB_TEST_TESTSE0NAK     0x00000001  // Test_SE0_NAK Test Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CCONF register.
+//
+//*****************************************************************************
+#define USB_CCONF_TXEDMA        0x00000002  // TX Early DMA Enable
+#define USB_CCONF_RXEDMA        0x00000001  // TX Early DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIVBUSCTL_USEEXTVBUSIND                                         \
+                                0x00000002  // Use External VBUS Indicator
+#define USB_ULPIVBUSCTL_USEEXTVBUS                                            \
+                                0x00000001  // Use External VBUS
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGDATA
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGDATA_REGDATA_M                                             \
+                                0x000000FF  // Register Data
+#define USB_ULPIREGDATA_REGDATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGADDR
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGADDR_ADDR_M  0x000000FF  // Register Address
+#define USB_ULPIREGADDR_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGCTL_RDWR     0x00000004  // Read/Write Control
+#define USB_ULPIREGCTL_REGCMPLT 0x00000002  // Register Access Complete
+#define USB_ULPIREGCTL_REGACC   0x00000001  // Initiate Register Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPINFO register.
+//
+//*****************************************************************************
+#define USB_EPINFO_RXEP_M       0x000000F0  // RX Endpoints
+#define USB_EPINFO_TXEP_M       0x0000000F  // TX Endpoints
+#define USB_EPINFO_RXEP_S       4
+#define USB_EPINFO_TXEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RAMINFO register.
+//
+//*****************************************************************************
+#define USB_RAMINFO_DMACHAN_M   0x000000F0  // DMA Channels
+#define USB_RAMINFO_RAMBITS_M   0x0000000F  // RAM Address Bus Width
+#define USB_RAMINFO_DMACHAN_S   4
+#define USB_RAMINFO_RAMBITS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSEOF register.
+//
+//*****************************************************************************
+#define USB_HSEOF_HSEOFG_M      0x000000FF  // HIgh-Speed End-of-Frame Gap
+#define USB_HSEOF_HSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DISPING       0x00000008  // PING Disable
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
+#define USB_TYPE0_SPEED_HIGH    0x00000040  // High
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH1_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH2_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH3_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH4_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH5_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL5_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL5_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH6_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL6_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL6_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH7_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAINTR register.
+//
+//*****************************************************************************
+#define USB_DMAINTR_CH7         0x00000080  // Channel 7 DMA Interrupt
+#define USB_DMAINTR_CH6         0x00000040  // Channel 6 DMA Interrupt
+#define USB_DMAINTR_CH5         0x00000020  // Channel 5 DMA Interrupt
+#define USB_DMAINTR_CH4         0x00000010  // Channel 4 DMA Interrupt
+#define USB_DMAINTR_CH3         0x00000008  // Channel 3 DMA Interrupt
+#define USB_DMAINTR_CH2         0x00000004  // Channel 2 DMA Interrupt
+#define USB_DMAINTR_CH1         0x00000002  // Channel 1 DMA Interrupt
+#define USB_DMAINTR_CH0         0x00000001  // Channel 0 DMA Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+//
+//*****************************************************************************
+#define USB_DMACTL0_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL0_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL0_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL0_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL0_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL0_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL0_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL0_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL0_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL0_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL0_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL0_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR0_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT0_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL1 register.
+//
+//*****************************************************************************
+#define USB_DMACTL1_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL1_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL1_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL1_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL1_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL1_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL1_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL1_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL1_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL1_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL1_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL1_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR1_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR1_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT1_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT1_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL2 register.
+//
+//*****************************************************************************
+#define USB_DMACTL2_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL2_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL2_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL2_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL2_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL2_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL2_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL2_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL2_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL2_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL2_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL2_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR2_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR2_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT2_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT2_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL3 register.
+//
+//*****************************************************************************
+#define USB_DMACTL3_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL3_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL3_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL3_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL3_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL3_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL3_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL3_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL3_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL3_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL3_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL3_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR3_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR3_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT3_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT3_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL4 register.
+//
+//*****************************************************************************
+#define USB_DMACTL4_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL4_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL4_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL4_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL4_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL4_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL4_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL4_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL4_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL4_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL4_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL4_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR4_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR4_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT4_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT4_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL5 register.
+//
+//*****************************************************************************
+#define USB_DMACTL5_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL5_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL5_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL5_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL5_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL5_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL5_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL5_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL5_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL5_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL5_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL5_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR5_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR5_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT5_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT5_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL6 register.
+//
+//*****************************************************************************
+#define USB_DMACTL6_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL6_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL6_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL6_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL6_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL6_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL6_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL6_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL6_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL6_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL6_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL6_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR6_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR6_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT6_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT6_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL7 register.
+//
+//*****************************************************************************
+#define USB_DMACTL7_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL7_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL7_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL7_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL7_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL7_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL7_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL7_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL7_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL7_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL7_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL7_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR7_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR7_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT7_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT7_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CTO register.
+//
+//*****************************************************************************
+#define USB_CTO_CCTV_M          0x0000FFFF  // Configurable Chirp Timeout Value
+#define USB_CTO_CCTV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HHSRTN register.
+//
+//*****************************************************************************
+#define USB_HHSRTN_HHSRTN_M     0x0000FFFF  // HIgh Speed to UTM Operating
+                                            // Delay
+#define USB_HHSRTN_HHSRTN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSBT register.
+//
+//*****************************************************************************
+#define USB_HSBT_HSBT_M         0x0000000F  // High Speed Timeout Adder
+#define USB_HSBT_HSBT_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMATTR register.
+//
+//*****************************************************************************
+#define USB_LPMATTR_ENDPT_M     0x0000F000  // Endpoint
+#define USB_LPMATTR_RMTWAK      0x00000100  // Remote Wake
+#define USB_LPMATTR_HIRD_M      0x000000F0  // Host Initiated Resume Duration
+#define USB_LPMATTR_LS_M        0x0000000F  // Link State
+#define USB_LPMATTR_LS_L1       0x00000001  // Sleep State (L1)
+#define USB_LPMATTR_ENDPT_S     12
+#define USB_LPMATTR_HIRD_S      4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
+//
+//*****************************************************************************
+#define USB_LPMCNTRL_NAK        0x00000010  // LPM NAK
+#define USB_LPMCNTRL_EN_M       0x0000000C  // LPM Enable
+#define USB_LPMCNTRL_EN_NONE    0x00000000  // LPM and Extended transactions
+                                            // are not supported. In this case,
+                                            // the USB does not respond to LPM
+                                            // transactions and LPM
+                                            // transactions cause a timeout
+#define USB_LPMCNTRL_EN_EXT     0x00000004  // LPM is not supported but
+                                            // extended transactions are
+                                            // supported. In this case, the USB
+                                            // does respond to an LPM
+                                            // transaction with a STALL
+#define USB_LPMCNTRL_EN_LPMEXT  0x0000000C  // The USB supports LPM extended
+                                            // transactions. In this case, the
+                                            // USB responds with a NYET or an
+                                            // ACK as determined by the value
+                                            // of TXLPM and other conditions
+#define USB_LPMCNTRL_RES        0x00000002  // LPM Resume
+#define USB_LPMCNTRL_TXLPM      0x00000001  // Transmit LPM Transaction Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMIM register.
+//
+//*****************************************************************************
+#define USB_LPMIM_ERR           0x00000020  // LPM Error Interrupt Mask
+#define USB_LPMIM_RES           0x00000010  // LPM Resume Interrupt Mask
+#define USB_LPMIM_NC            0x00000008  // LPM NC Interrupt Mask
+#define USB_LPMIM_ACK           0x00000004  // LPM ACK Interrupt Mask
+#define USB_LPMIM_NY            0x00000002  // LPM NY Interrupt Mask
+#define USB_LPMIM_STALL         0x00000001  // LPM STALL Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMRIS register.
+//
+//*****************************************************************************
+#define USB_LPMRIS_ERR          0x00000020  // LPM Interrupt Status
+#define USB_LPMRIS_RES          0x00000010  // LPM Resume Interrupt Status
+#define USB_LPMRIS_NC           0x00000008  // LPM NC Interrupt Status
+#define USB_LPMRIS_ACK          0x00000004  // LPM ACK Interrupt Status
+#define USB_LPMRIS_NY           0x00000002  // LPM NY Interrupt Status
+#define USB_LPMRIS_LPMST        0x00000001  // LPM STALL Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMFADDR register.
+//
+//*****************************************************************************
+#define USB_LPMFADDR_ADDR_M     0x0000007F  // LPM Function Address
+#define USB_LPMFADDR_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+                                            // (OTG only)
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+                                            // (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD_M       0x00000007  // Device Mode
+#define USB_GPCS_DEVMOD_OTG     0x00000000  // Use USB0VBUS and USB0ID pin
+#define USB_GPCS_DEVMOD_HOST    0x00000002  // Force USB0VBUS and USB0ID low
+#define USB_GPCS_DEVMOD_DEV     0x00000003  // Force USB0VBUS and USB0ID high
+#define USB_GPCS_DEVMOD_HOSTVBUS                                              \
+                                0x00000004  // Use USB0VBUS and force USB0ID
+                                            // low
+#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005  // Use USB0VBUS and force USB0ID
+                                            // high
+#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
+#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
+#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
+#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
+#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
+#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
+#define USB_DMASEL_DMACTX_S     20
+#define USB_DMASEL_DMACRX_S     16
+#define USB_DMASEL_DMABTX_S     12
+#define USB_DMASEL_DMABRX_S     8
+#define USB_DMASEL_DMAATX_S     4
+#define USB_DMASEL_DMAARX_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
+#define USB_PP_USB_M            0x000000C0  // USB Capability
+#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
+#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
+#define USB_PP_USB_OTG          0x000000C0  // OTG
+#define USB_PP_ULPI             0x00000020  // ULPI Present
+#define USB_PP_PHY              0x00000010  // PHY Present
+#define USB_PP_TYPE_M           0x0000000F  // Controller Type
+#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
+                                            // controller
+#define USB_PP_TYPE_1           0x00000001  // Second-generation USB
+                                            // controller.The controller
+                                            // implemented in post Icestorm
+                                            // devices that use the 3.0 version
+                                            // of the Mentor controller
+#define USB_PP_ECNT_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PC register.
+//
+//*****************************************************************************
+#define USB_PC_ULPIEN           0x00010000  // ULPI Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CC register.
+//
+//*****************************************************************************
+#define USB_CC_CLKEN            0x00000200  // USB Clock Enable
+#define USB_CC_CSD              0x00000100  // Clock Source/Direction
+#define USB_CC_CLKDIV_M         0x0000000F  // PLL Clock Divisor
+#define USB_CC_CLKDIV_S         0
+
+#endif // __HW_USB_H__
diff --git a/bsp/tm4c129x/libraries/inc/hw_watchdog.h b/bsp/tm4c129x/libraries/inc/hw_watchdog.h
new file mode 100644
index 0000000000..d1e9b4d267
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/hw_watchdog.h
@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD              0x00000000  // Watchdog Load
+#define WDT_O_VALUE             0x00000004  // Watchdog Value
+#define WDT_O_CTL               0x00000008  // Watchdog Control
+#define WDT_O_ICR               0x0000000C  // Watchdog Interrupt Clear
+#define WDT_O_RIS               0x00000010  // Watchdog Raw Interrupt Status
+#define WDT_O_MIS               0x00000014  // Watchdog Masked Interrupt Status
+#define WDT_O_TEST              0x00000418  // Watchdog Test
+#define WDT_O_LOCK              0x00000C00  // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+
+#endif // __HW_WATCHDOG_H__
diff --git a/bsp/tm4c129x/libraries/inc/tm4c129xnczad.h b/bsp/tm4c129x/libraries/inc/tm4c129xnczad.h
new file mode 100644
index 0000000000..cb5d91d22d
--- /dev/null
+++ b/bsp/tm4c129x/libraries/inc/tm4c129xnczad.h
@@ -0,0 +1,17263 @@
+//*****************************************************************************
+//
+// tm4c129xnczad.h - TM4C129XNCZAD Register Definitions
+//
+// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __TM4C129XNCZAD_H__
+#define __TM4C129XNCZAD_H__
+
+//*****************************************************************************
+//
+// Interrupt assignments
+//
+//*****************************************************************************
+#define INT_GPIOA               16          // GPIO Port A
+#define INT_GPIOB               17          // GPIO Port B
+#define INT_GPIOC               18          // GPIO Port C
+#define INT_GPIOD               19          // GPIO Port D
+#define INT_GPIOE               20          // GPIO Port E
+#define INT_UART0               21          // UART0
+#define INT_UART1               22          // UART1
+#define INT_SSI0                23          // SSI0
+#define INT_I2C0                24          // I2C0
+#define INT_PWM0_FAULT          25          // PWM Fault
+#define INT_PWM0_0              26          // PWM Generator 0
+#define INT_PWM0_1              27          // PWM Generator 1
+#define INT_PWM0_2              28          // PWM Generator 2
+#define INT_QEI0                29          // QEI0
+#define INT_ADC0SS0             30          // ADC0 Sequence 0
+#define INT_ADC0SS1             31          // ADC0 Sequence 1
+#define INT_ADC0SS2             32          // ADC0 Sequence 2
+#define INT_ADC0SS3             33          // ADC0 Sequence 3
+#define INT_WATCHDOG            34          // Watchdog Timers 0 and 1
+#define INT_TIMER0A             35          // 16/32-Bit Timer 0A
+#define INT_TIMER0B             36          // 16/32-Bit Timer 0B
+#define INT_TIMER1A             37          // 16/32-Bit Timer 1A
+#define INT_TIMER1B             38          // 16/32-Bit Timer 1B
+#define INT_TIMER2A             39          // 16/32-Bit Timer 2A
+#define INT_TIMER2B             40          // 16/32-Bit Timer 2B
+#define INT_COMP0               41          // Analog Comparator 0
+#define INT_COMP1               42          // Analog Comparator 1
+#define INT_COMP2               43          // Analog Comparator 2
+#define INT_SYSCTL              44          // System Control
+#define INT_FLASH               45          // Flash Memory Control
+#define INT_GPIOF               46          // GPIO Port F
+#define INT_GPIOG               47          // GPIO Port G
+#define INT_GPIOH               48          // GPIO Port H
+#define INT_UART2               49          // UART2
+#define INT_SSI1                50          // SSI1
+#define INT_TIMER3A             51          // 16/32-Bit Timer 3A
+#define INT_TIMER3B             52          // 16/32-Bit Timer 3B
+#define INT_I2C1                53          // I2C1
+#define INT_CAN0                54          // CAN 0
+#define INT_CAN1                55          // CAN1
+#define INT_EMAC0               56          // Ethernet MAC
+#define INT_HIBERNATE           57          // HIB
+#define INT_USB0                58          // USB MAC
+#define INT_PWM0_3              59          // PWM Generator 3
+#define INT_UDMA                60          // uDMA 0 Software
+#define INT_UDMAERR             61          // uDMA 0 Error
+#define INT_ADC1SS0             62          // ADC1 Sequence 0
+#define INT_ADC1SS1             63          // ADC1 Sequence 1
+#define INT_ADC1SS2             64          // ADC1 Sequence 2
+#define INT_ADC1SS3             65          // ADC1 Sequence 3
+#define INT_EPI0                66          // EPI 0
+#define INT_GPIOJ               67          // GPIO Port J
+#define INT_GPIOK               68          // GPIO Port K
+#define INT_GPIOL               69          // GPIO Port L
+#define INT_SSI2                70          // SSI 2
+#define INT_SSI3                71          // SSI 3
+#define INT_UART3               72          // UART 3
+#define INT_UART4               73          // UART 4
+#define INT_UART5               74          // UART 5
+#define INT_UART6               75          // UART 6
+#define INT_UART7               76          // UART 7
+#define INT_I2C2                77          // I2C 2
+#define INT_I2C3                78          // I2C 3
+#define INT_TIMER4A             79          // Timer 4A
+#define INT_TIMER4B             80          // Timer 4B
+#define INT_TIMER5A             81          // Timer 5A
+#define INT_TIMER5B             82          // Timer 5B
+#define INT_SYSEXC              83          // Floating-Point Exception
+                                            // (imprecise)
+#define INT_I2C4                86          // I2C 4
+#define INT_I2C5                87          // I2C 5
+#define INT_GPIOM               88          // GPIO Port M
+#define INT_GPION               89          // GPIO Port N
+#define INT_TAMPER0             91          // Tamper
+#define INT_GPIOP0              92          // GPIO Port P (Summary or P0)
+#define INT_GPIOP1              93          // GPIO Port P1
+#define INT_GPIOP2              94          // GPIO Port P2
+#define INT_GPIOP3              95          // GPIO Port P3
+#define INT_GPIOP4              96          // GPIO Port P4
+#define INT_GPIOP5              97          // GPIO Port P5
+#define INT_GPIOP6              98          // GPIO Port P6
+#define INT_GPIOP7              99          // GPIO Port P7
+#define INT_GPIOQ0              100         // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1              101         // GPIO Port Q1
+#define INT_GPIOQ2              102         // GPIO Port Q2
+#define INT_GPIOQ3              103         // GPIO Port Q3
+#define INT_GPIOQ4              104         // GPIO Port Q4
+#define INT_GPIOQ5              105         // GPIO Port Q5
+#define INT_GPIOQ6              106         // GPIO Port Q6
+#define INT_GPIOQ7              107         // GPIO Port Q7
+#define INT_GPIOR               108         // GPIO Port R
+#define INT_GPIOS               109         // GPIO Port S
+#define INT_SHA0                110         // SHA/MD5
+#define INT_AES0                111         // AES
+#define INT_DES0                112         // DES
+#define INT_LCD0                113         // LCD
+#define INT_TIMER6A             114         // 16/32-Bit Timer 6A
+#define INT_TIMER6B             115         // 16/32-Bit Timer 6B
+#define INT_TIMER7A             116         // 16/32-Bit Timer 7A
+#define INT_TIMER7B             117         // 16/32-Bit Timer 7B
+#define INT_I2C6                118         // I2C 6
+#define INT_I2C7                119         // I2C 7
+#define INT_ONEWIRE0            121         // 1-Wire
+#define INT_I2C8                125         // I2C 8
+#define INT_I2C9                126         // I2C 9
+#define INT_GPIOT               127         // GPIO T
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R        (*((volatile uint32_t *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile uint32_t *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile uint32_t *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile uint32_t *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile uint32_t *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile uint32_t *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile uint32_t *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile uint32_t *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R        (*((volatile uint32_t *)0x40001000))
+#define WATCHDOG1_VALUE_R       (*((volatile uint32_t *)0x40001004))
+#define WATCHDOG1_CTL_R         (*((volatile uint32_t *)0x40001008))
+#define WATCHDOG1_ICR_R         (*((volatile uint32_t *)0x4000100C))
+#define WATCHDOG1_RIS_R         (*((volatile uint32_t *)0x40001010))
+#define WATCHDOG1_MIS_R         (*((volatile uint32_t *)0x40001014))
+#define WATCHDOG1_TEST_R        (*((volatile uint32_t *)0x40001418))
+#define WATCHDOG1_LOCK_R        (*((volatile uint32_t *)0x40001C00))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R              (*((volatile uint32_t *)0x40008000))
+#define SSI0_CR1_R              (*((volatile uint32_t *)0x40008004))
+#define SSI0_DR_R               (*((volatile uint32_t *)0x40008008))
+#define SSI0_SR_R               (*((volatile uint32_t *)0x4000800C))
+#define SSI0_CPSR_R             (*((volatile uint32_t *)0x40008010))
+#define SSI0_IM_R               (*((volatile uint32_t *)0x40008014))
+#define SSI0_RIS_R              (*((volatile uint32_t *)0x40008018))
+#define SSI0_MIS_R              (*((volatile uint32_t *)0x4000801C))
+#define SSI0_ICR_R              (*((volatile uint32_t *)0x40008020))
+#define SSI0_DMACTL_R           (*((volatile uint32_t *)0x40008024))
+#define SSI0_PP_R               (*((volatile uint32_t *)0x40008FC0))
+#define SSI0_CC_R               (*((volatile uint32_t *)0x40008FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R              (*((volatile uint32_t *)0x40009000))
+#define SSI1_CR1_R              (*((volatile uint32_t *)0x40009004))
+#define SSI1_DR_R               (*((volatile uint32_t *)0x40009008))
+#define SSI1_SR_R               (*((volatile uint32_t *)0x4000900C))
+#define SSI1_CPSR_R             (*((volatile uint32_t *)0x40009010))
+#define SSI1_IM_R               (*((volatile uint32_t *)0x40009014))
+#define SSI1_RIS_R              (*((volatile uint32_t *)0x40009018))
+#define SSI1_MIS_R              (*((volatile uint32_t *)0x4000901C))
+#define SSI1_ICR_R              (*((volatile uint32_t *)0x40009020))
+#define SSI1_DMACTL_R           (*((volatile uint32_t *)0x40009024))
+#define SSI1_PP_R               (*((volatile uint32_t *)0x40009FC0))
+#define SSI1_CC_R               (*((volatile uint32_t *)0x40009FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI2)
+//
+//*****************************************************************************
+#define SSI2_CR0_R              (*((volatile uint32_t *)0x4000A000))
+#define SSI2_CR1_R              (*((volatile uint32_t *)0x4000A004))
+#define SSI2_DR_R               (*((volatile uint32_t *)0x4000A008))
+#define SSI2_SR_R               (*((volatile uint32_t *)0x4000A00C))
+#define SSI2_CPSR_R             (*((volatile uint32_t *)0x4000A010))
+#define SSI2_IM_R               (*((volatile uint32_t *)0x4000A014))
+#define SSI2_RIS_R              (*((volatile uint32_t *)0x4000A018))
+#define SSI2_MIS_R              (*((volatile uint32_t *)0x4000A01C))
+#define SSI2_ICR_R              (*((volatile uint32_t *)0x4000A020))
+#define SSI2_DMACTL_R           (*((volatile uint32_t *)0x4000A024))
+#define SSI2_PP_R               (*((volatile uint32_t *)0x4000AFC0))
+#define SSI2_CC_R               (*((volatile uint32_t *)0x4000AFC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI3)
+//
+//*****************************************************************************
+#define SSI3_CR0_R              (*((volatile uint32_t *)0x4000B000))
+#define SSI3_CR1_R              (*((volatile uint32_t *)0x4000B004))
+#define SSI3_DR_R               (*((volatile uint32_t *)0x4000B008))
+#define SSI3_SR_R               (*((volatile uint32_t *)0x4000B00C))
+#define SSI3_CPSR_R             (*((volatile uint32_t *)0x4000B010))
+#define SSI3_IM_R               (*((volatile uint32_t *)0x4000B014))
+#define SSI3_RIS_R              (*((volatile uint32_t *)0x4000B018))
+#define SSI3_MIS_R              (*((volatile uint32_t *)0x4000B01C))
+#define SSI3_ICR_R              (*((volatile uint32_t *)0x4000B020))
+#define SSI3_DMACTL_R           (*((volatile uint32_t *)0x4000B024))
+#define SSI3_PP_R               (*((volatile uint32_t *)0x4000BFC0))
+#define SSI3_CC_R               (*((volatile uint32_t *)0x4000BFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R              (*((volatile uint32_t *)0x4000C000))
+#define UART0_RSR_R             (*((volatile uint32_t *)0x4000C004))
+#define UART0_ECR_R             (*((volatile uint32_t *)0x4000C004))
+#define UART0_FR_R              (*((volatile uint32_t *)0x4000C018))
+#define UART0_ILPR_R            (*((volatile uint32_t *)0x4000C020))
+#define UART0_IBRD_R            (*((volatile uint32_t *)0x4000C024))
+#define UART0_FBRD_R            (*((volatile uint32_t *)0x4000C028))
+#define UART0_LCRH_R            (*((volatile uint32_t *)0x4000C02C))
+#define UART0_CTL_R             (*((volatile uint32_t *)0x4000C030))
+#define UART0_IFLS_R            (*((volatile uint32_t *)0x4000C034))
+#define UART0_IM_R              (*((volatile uint32_t *)0x4000C038))
+#define UART0_RIS_R             (*((volatile uint32_t *)0x4000C03C))
+#define UART0_MIS_R             (*((volatile uint32_t *)0x4000C040))
+#define UART0_ICR_R             (*((volatile uint32_t *)0x4000C044))
+#define UART0_DMACTL_R          (*((volatile uint32_t *)0x4000C048))
+#define UART0_9BITADDR_R        (*((volatile uint32_t *)0x4000C0A4))
+#define UART0_9BITAMASK_R       (*((volatile uint32_t *)0x4000C0A8))
+#define UART0_PP_R              (*((volatile uint32_t *)0x4000CFC0))
+#define UART0_CC_R              (*((volatile uint32_t *)0x4000CFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R              (*((volatile uint32_t *)0x4000D000))
+#define UART1_RSR_R             (*((volatile uint32_t *)0x4000D004))
+#define UART1_ECR_R             (*((volatile uint32_t *)0x4000D004))
+#define UART1_FR_R              (*((volatile uint32_t *)0x4000D018))
+#define UART1_ILPR_R            (*((volatile uint32_t *)0x4000D020))
+#define UART1_IBRD_R            (*((volatile uint32_t *)0x4000D024))
+#define UART1_FBRD_R            (*((volatile uint32_t *)0x4000D028))
+#define UART1_LCRH_R            (*((volatile uint32_t *)0x4000D02C))
+#define UART1_CTL_R             (*((volatile uint32_t *)0x4000D030))
+#define UART1_IFLS_R            (*((volatile uint32_t *)0x4000D034))
+#define UART1_IM_R              (*((volatile uint32_t *)0x4000D038))
+#define UART1_RIS_R             (*((volatile uint32_t *)0x4000D03C))
+#define UART1_MIS_R             (*((volatile uint32_t *)0x4000D040))
+#define UART1_ICR_R             (*((volatile uint32_t *)0x4000D044))
+#define UART1_DMACTL_R          (*((volatile uint32_t *)0x4000D048))
+#define UART1_9BITADDR_R        (*((volatile uint32_t *)0x4000D0A4))
+#define UART1_9BITAMASK_R       (*((volatile uint32_t *)0x4000D0A8))
+#define UART1_PP_R              (*((volatile uint32_t *)0x4000DFC0))
+#define UART1_CC_R              (*((volatile uint32_t *)0x4000DFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R              (*((volatile uint32_t *)0x4000E000))
+#define UART2_RSR_R             (*((volatile uint32_t *)0x4000E004))
+#define UART2_ECR_R             (*((volatile uint32_t *)0x4000E004))
+#define UART2_FR_R              (*((volatile uint32_t *)0x4000E018))
+#define UART2_ILPR_R            (*((volatile uint32_t *)0x4000E020))
+#define UART2_IBRD_R            (*((volatile uint32_t *)0x4000E024))
+#define UART2_FBRD_R            (*((volatile uint32_t *)0x4000E028))
+#define UART2_LCRH_R            (*((volatile uint32_t *)0x4000E02C))
+#define UART2_CTL_R             (*((volatile uint32_t *)0x4000E030))
+#define UART2_IFLS_R            (*((volatile uint32_t *)0x4000E034))
+#define UART2_IM_R              (*((volatile uint32_t *)0x4000E038))
+#define UART2_RIS_R             (*((volatile uint32_t *)0x4000E03C))
+#define UART2_MIS_R             (*((volatile uint32_t *)0x4000E040))
+#define UART2_ICR_R             (*((volatile uint32_t *)0x4000E044))
+#define UART2_DMACTL_R          (*((volatile uint32_t *)0x4000E048))
+#define UART2_9BITADDR_R        (*((volatile uint32_t *)0x4000E0A4))
+#define UART2_9BITAMASK_R       (*((volatile uint32_t *)0x4000E0A8))
+#define UART2_PP_R              (*((volatile uint32_t *)0x4000EFC0))
+#define UART2_CC_R              (*((volatile uint32_t *)0x4000EFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART3)
+//
+//*****************************************************************************
+#define UART3_DR_R              (*((volatile uint32_t *)0x4000F000))
+#define UART3_RSR_R             (*((volatile uint32_t *)0x4000F004))
+#define UART3_ECR_R             (*((volatile uint32_t *)0x4000F004))
+#define UART3_FR_R              (*((volatile uint32_t *)0x4000F018))
+#define UART3_ILPR_R            (*((volatile uint32_t *)0x4000F020))
+#define UART3_IBRD_R            (*((volatile uint32_t *)0x4000F024))
+#define UART3_FBRD_R            (*((volatile uint32_t *)0x4000F028))
+#define UART3_LCRH_R            (*((volatile uint32_t *)0x4000F02C))
+#define UART3_CTL_R             (*((volatile uint32_t *)0x4000F030))
+#define UART3_IFLS_R            (*((volatile uint32_t *)0x4000F034))
+#define UART3_IM_R              (*((volatile uint32_t *)0x4000F038))
+#define UART3_RIS_R             (*((volatile uint32_t *)0x4000F03C))
+#define UART3_MIS_R             (*((volatile uint32_t *)0x4000F040))
+#define UART3_ICR_R             (*((volatile uint32_t *)0x4000F044))
+#define UART3_DMACTL_R          (*((volatile uint32_t *)0x4000F048))
+#define UART3_9BITADDR_R        (*((volatile uint32_t *)0x4000F0A4))
+#define UART3_9BITAMASK_R       (*((volatile uint32_t *)0x4000F0A8))
+#define UART3_PP_R              (*((volatile uint32_t *)0x4000FFC0))
+#define UART3_CC_R              (*((volatile uint32_t *)0x4000FFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART4)
+//
+//*****************************************************************************
+#define UART4_DR_R              (*((volatile uint32_t *)0x40010000))
+#define UART4_RSR_R             (*((volatile uint32_t *)0x40010004))
+#define UART4_ECR_R             (*((volatile uint32_t *)0x40010004))
+#define UART4_FR_R              (*((volatile uint32_t *)0x40010018))
+#define UART4_ILPR_R            (*((volatile uint32_t *)0x40010020))
+#define UART4_IBRD_R            (*((volatile uint32_t *)0x40010024))
+#define UART4_FBRD_R            (*((volatile uint32_t *)0x40010028))
+#define UART4_LCRH_R            (*((volatile uint32_t *)0x4001002C))
+#define UART4_CTL_R             (*((volatile uint32_t *)0x40010030))
+#define UART4_IFLS_R            (*((volatile uint32_t *)0x40010034))
+#define UART4_IM_R              (*((volatile uint32_t *)0x40010038))
+#define UART4_RIS_R             (*((volatile uint32_t *)0x4001003C))
+#define UART4_MIS_R             (*((volatile uint32_t *)0x40010040))
+#define UART4_ICR_R             (*((volatile uint32_t *)0x40010044))
+#define UART4_DMACTL_R          (*((volatile uint32_t *)0x40010048))
+#define UART4_9BITADDR_R        (*((volatile uint32_t *)0x400100A4))
+#define UART4_9BITAMASK_R       (*((volatile uint32_t *)0x400100A8))
+#define UART4_PP_R              (*((volatile uint32_t *)0x40010FC0))
+#define UART4_CC_R              (*((volatile uint32_t *)0x40010FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART5)
+//
+//*****************************************************************************
+#define UART5_DR_R              (*((volatile uint32_t *)0x40011000))
+#define UART5_RSR_R             (*((volatile uint32_t *)0x40011004))
+#define UART5_ECR_R             (*((volatile uint32_t *)0x40011004))
+#define UART5_FR_R              (*((volatile uint32_t *)0x40011018))
+#define UART5_ILPR_R            (*((volatile uint32_t *)0x40011020))
+#define UART5_IBRD_R            (*((volatile uint32_t *)0x40011024))
+#define UART5_FBRD_R            (*((volatile uint32_t *)0x40011028))
+#define UART5_LCRH_R            (*((volatile uint32_t *)0x4001102C))
+#define UART5_CTL_R             (*((volatile uint32_t *)0x40011030))
+#define UART5_IFLS_R            (*((volatile uint32_t *)0x40011034))
+#define UART5_IM_R              (*((volatile uint32_t *)0x40011038))
+#define UART5_RIS_R             (*((volatile uint32_t *)0x4001103C))
+#define UART5_MIS_R             (*((volatile uint32_t *)0x40011040))
+#define UART5_ICR_R             (*((volatile uint32_t *)0x40011044))
+#define UART5_DMACTL_R          (*((volatile uint32_t *)0x40011048))
+#define UART5_9BITADDR_R        (*((volatile uint32_t *)0x400110A4))
+#define UART5_9BITAMASK_R       (*((volatile uint32_t *)0x400110A8))
+#define UART5_PP_R              (*((volatile uint32_t *)0x40011FC0))
+#define UART5_CC_R              (*((volatile uint32_t *)0x40011FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART6)
+//
+//*****************************************************************************
+#define UART6_DR_R              (*((volatile uint32_t *)0x40012000))
+#define UART6_RSR_R             (*((volatile uint32_t *)0x40012004))
+#define UART6_ECR_R             (*((volatile uint32_t *)0x40012004))
+#define UART6_FR_R              (*((volatile uint32_t *)0x40012018))
+#define UART6_ILPR_R            (*((volatile uint32_t *)0x40012020))
+#define UART6_IBRD_R            (*((volatile uint32_t *)0x40012024))
+#define UART6_FBRD_R            (*((volatile uint32_t *)0x40012028))
+#define UART6_LCRH_R            (*((volatile uint32_t *)0x4001202C))
+#define UART6_CTL_R             (*((volatile uint32_t *)0x40012030))
+#define UART6_IFLS_R            (*((volatile uint32_t *)0x40012034))
+#define UART6_IM_R              (*((volatile uint32_t *)0x40012038))
+#define UART6_RIS_R             (*((volatile uint32_t *)0x4001203C))
+#define UART6_MIS_R             (*((volatile uint32_t *)0x40012040))
+#define UART6_ICR_R             (*((volatile uint32_t *)0x40012044))
+#define UART6_DMACTL_R          (*((volatile uint32_t *)0x40012048))
+#define UART6_9BITADDR_R        (*((volatile uint32_t *)0x400120A4))
+#define UART6_9BITAMASK_R       (*((volatile uint32_t *)0x400120A8))
+#define UART6_PP_R              (*((volatile uint32_t *)0x40012FC0))
+#define UART6_CC_R              (*((volatile uint32_t *)0x40012FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART7)
+//
+//*****************************************************************************
+#define UART7_DR_R              (*((volatile uint32_t *)0x40013000))
+#define UART7_RSR_R             (*((volatile uint32_t *)0x40013004))
+#define UART7_ECR_R             (*((volatile uint32_t *)0x40013004))
+#define UART7_FR_R              (*((volatile uint32_t *)0x40013018))
+#define UART7_ILPR_R            (*((volatile uint32_t *)0x40013020))
+#define UART7_IBRD_R            (*((volatile uint32_t *)0x40013024))
+#define UART7_FBRD_R            (*((volatile uint32_t *)0x40013028))
+#define UART7_LCRH_R            (*((volatile uint32_t *)0x4001302C))
+#define UART7_CTL_R             (*((volatile uint32_t *)0x40013030))
+#define UART7_IFLS_R            (*((volatile uint32_t *)0x40013034))
+#define UART7_IM_R              (*((volatile uint32_t *)0x40013038))
+#define UART7_RIS_R             (*((volatile uint32_t *)0x4001303C))
+#define UART7_MIS_R             (*((volatile uint32_t *)0x40013040))
+#define UART7_ICR_R             (*((volatile uint32_t *)0x40013044))
+#define UART7_DMACTL_R          (*((volatile uint32_t *)0x40013048))
+#define UART7_9BITADDR_R        (*((volatile uint32_t *)0x400130A4))
+#define UART7_9BITAMASK_R       (*((volatile uint32_t *)0x400130A8))
+#define UART7_PP_R              (*((volatile uint32_t *)0x40013FC0))
+#define UART7_CC_R              (*((volatile uint32_t *)0x40013FC8))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0)
+//
+//*****************************************************************************
+#define I2C0_MSA_R              (*((volatile uint32_t *)0x40020000))
+#define I2C0_MCS_R              (*((volatile uint32_t *)0x40020004))
+#define I2C0_MDR_R              (*((volatile uint32_t *)0x40020008))
+#define I2C0_MTPR_R             (*((volatile uint32_t *)0x4002000C))
+#define I2C0_MIMR_R             (*((volatile uint32_t *)0x40020010))
+#define I2C0_MRIS_R             (*((volatile uint32_t *)0x40020014))
+#define I2C0_MMIS_R             (*((volatile uint32_t *)0x40020018))
+#define I2C0_MICR_R             (*((volatile uint32_t *)0x4002001C))
+#define I2C0_MCR_R              (*((volatile uint32_t *)0x40020020))
+#define I2C0_MCLKOCNT_R         (*((volatile uint32_t *)0x40020024))
+#define I2C0_MBMON_R            (*((volatile uint32_t *)0x4002002C))
+#define I2C0_MBLEN_R            (*((volatile uint32_t *)0x40020030))
+#define I2C0_MBCNT_R            (*((volatile uint32_t *)0x40020034))
+#define I2C0_SOAR_R             (*((volatile uint32_t *)0x40020800))
+#define I2C0_SCSR_R             (*((volatile uint32_t *)0x40020804))
+#define I2C0_SDR_R              (*((volatile uint32_t *)0x40020808))
+#define I2C0_SIMR_R             (*((volatile uint32_t *)0x4002080C))
+#define I2C0_SRIS_R             (*((volatile uint32_t *)0x40020810))
+#define I2C0_SMIS_R             (*((volatile uint32_t *)0x40020814))
+#define I2C0_SICR_R             (*((volatile uint32_t *)0x40020818))
+#define I2C0_SOAR2_R            (*((volatile uint32_t *)0x4002081C))
+#define I2C0_SACKCTL_R          (*((volatile uint32_t *)0x40020820))
+#define I2C0_FIFODATA_R         (*((volatile uint32_t *)0x40020F00))
+#define I2C0_FIFOCTL_R          (*((volatile uint32_t *)0x40020F04))
+#define I2C0_FIFOSTATUS_R       (*((volatile uint32_t *)0x40020F08))
+#define I2C0_PP_R               (*((volatile uint32_t *)0x40020FC0))
+#define I2C0_PC_R               (*((volatile uint32_t *)0x40020FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1)
+//
+//*****************************************************************************
+#define I2C1_MSA_R              (*((volatile uint32_t *)0x40021000))
+#define I2C1_MCS_R              (*((volatile uint32_t *)0x40021004))
+#define I2C1_MDR_R              (*((volatile uint32_t *)0x40021008))
+#define I2C1_MTPR_R             (*((volatile uint32_t *)0x4002100C))
+#define I2C1_MIMR_R             (*((volatile uint32_t *)0x40021010))
+#define I2C1_MRIS_R             (*((volatile uint32_t *)0x40021014))
+#define I2C1_MMIS_R             (*((volatile uint32_t *)0x40021018))
+#define I2C1_MICR_R             (*((volatile uint32_t *)0x4002101C))
+#define I2C1_MCR_R              (*((volatile uint32_t *)0x40021020))
+#define I2C1_MCLKOCNT_R         (*((volatile uint32_t *)0x40021024))
+#define I2C1_MBMON_R            (*((volatile uint32_t *)0x4002102C))
+#define I2C1_MBLEN_R            (*((volatile uint32_t *)0x40021030))
+#define I2C1_MBCNT_R            (*((volatile uint32_t *)0x40021034))
+#define I2C1_SOAR_R             (*((volatile uint32_t *)0x40021800))
+#define I2C1_SCSR_R             (*((volatile uint32_t *)0x40021804))
+#define I2C1_SDR_R              (*((volatile uint32_t *)0x40021808))
+#define I2C1_SIMR_R             (*((volatile uint32_t *)0x4002180C))
+#define I2C1_SRIS_R             (*((volatile uint32_t *)0x40021810))
+#define I2C1_SMIS_R             (*((volatile uint32_t *)0x40021814))
+#define I2C1_SICR_R             (*((volatile uint32_t *)0x40021818))
+#define I2C1_SOAR2_R            (*((volatile uint32_t *)0x4002181C))
+#define I2C1_SACKCTL_R          (*((volatile uint32_t *)0x40021820))
+#define I2C1_FIFODATA_R         (*((volatile uint32_t *)0x40021F00))
+#define I2C1_FIFOCTL_R          (*((volatile uint32_t *)0x40021F04))
+#define I2C1_FIFOSTATUS_R       (*((volatile uint32_t *)0x40021F08))
+#define I2C1_PP_R               (*((volatile uint32_t *)0x40021FC0))
+#define I2C1_PC_R               (*((volatile uint32_t *)0x40021FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C2)
+//
+//*****************************************************************************
+#define I2C2_MSA_R              (*((volatile uint32_t *)0x40022000))
+#define I2C2_MCS_R              (*((volatile uint32_t *)0x40022004))
+#define I2C2_MDR_R              (*((volatile uint32_t *)0x40022008))
+#define I2C2_MTPR_R             (*((volatile uint32_t *)0x4002200C))
+#define I2C2_MIMR_R             (*((volatile uint32_t *)0x40022010))
+#define I2C2_MRIS_R             (*((volatile uint32_t *)0x40022014))
+#define I2C2_MMIS_R             (*((volatile uint32_t *)0x40022018))
+#define I2C2_MICR_R             (*((volatile uint32_t *)0x4002201C))
+#define I2C2_MCR_R              (*((volatile uint32_t *)0x40022020))
+#define I2C2_MCLKOCNT_R         (*((volatile uint32_t *)0x40022024))
+#define I2C2_MBMON_R            (*((volatile uint32_t *)0x4002202C))
+#define I2C2_MBLEN_R            (*((volatile uint32_t *)0x40022030))
+#define I2C2_MBCNT_R            (*((volatile uint32_t *)0x40022034))
+#define I2C2_SOAR_R             (*((volatile uint32_t *)0x40022800))
+#define I2C2_SCSR_R             (*((volatile uint32_t *)0x40022804))
+#define I2C2_SDR_R              (*((volatile uint32_t *)0x40022808))
+#define I2C2_SIMR_R             (*((volatile uint32_t *)0x4002280C))
+#define I2C2_SRIS_R             (*((volatile uint32_t *)0x40022810))
+#define I2C2_SMIS_R             (*((volatile uint32_t *)0x40022814))
+#define I2C2_SICR_R             (*((volatile uint32_t *)0x40022818))
+#define I2C2_SOAR2_R            (*((volatile uint32_t *)0x4002281C))
+#define I2C2_SACKCTL_R          (*((volatile uint32_t *)0x40022820))
+#define I2C2_FIFODATA_R         (*((volatile uint32_t *)0x40022F00))
+#define I2C2_FIFOCTL_R          (*((volatile uint32_t *)0x40022F04))
+#define I2C2_FIFOSTATUS_R       (*((volatile uint32_t *)0x40022F08))
+#define I2C2_PP_R               (*((volatile uint32_t *)0x40022FC0))
+#define I2C2_PC_R               (*((volatile uint32_t *)0x40022FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C3)
+//
+//*****************************************************************************
+#define I2C3_MSA_R              (*((volatile uint32_t *)0x40023000))
+#define I2C3_MCS_R              (*((volatile uint32_t *)0x40023004))
+#define I2C3_MDR_R              (*((volatile uint32_t *)0x40023008))
+#define I2C3_MTPR_R             (*((volatile uint32_t *)0x4002300C))
+#define I2C3_MIMR_R             (*((volatile uint32_t *)0x40023010))
+#define I2C3_MRIS_R             (*((volatile uint32_t *)0x40023014))
+#define I2C3_MMIS_R             (*((volatile uint32_t *)0x40023018))
+#define I2C3_MICR_R             (*((volatile uint32_t *)0x4002301C))
+#define I2C3_MCR_R              (*((volatile uint32_t *)0x40023020))
+#define I2C3_MCLKOCNT_R         (*((volatile uint32_t *)0x40023024))
+#define I2C3_MBMON_R            (*((volatile uint32_t *)0x4002302C))
+#define I2C3_MBLEN_R            (*((volatile uint32_t *)0x40023030))
+#define I2C3_MBCNT_R            (*((volatile uint32_t *)0x40023034))
+#define I2C3_SOAR_R             (*((volatile uint32_t *)0x40023800))
+#define I2C3_SCSR_R             (*((volatile uint32_t *)0x40023804))
+#define I2C3_SDR_R              (*((volatile uint32_t *)0x40023808))
+#define I2C3_SIMR_R             (*((volatile uint32_t *)0x4002380C))
+#define I2C3_SRIS_R             (*((volatile uint32_t *)0x40023810))
+#define I2C3_SMIS_R             (*((volatile uint32_t *)0x40023814))
+#define I2C3_SICR_R             (*((volatile uint32_t *)0x40023818))
+#define I2C3_SOAR2_R            (*((volatile uint32_t *)0x4002381C))
+#define I2C3_SACKCTL_R          (*((volatile uint32_t *)0x40023820))
+#define I2C3_FIFODATA_R         (*((volatile uint32_t *)0x40023F00))
+#define I2C3_FIFOCTL_R          (*((volatile uint32_t *)0x40023F04))
+#define I2C3_FIFOSTATUS_R       (*((volatile uint32_t *)0x40023F08))
+#define I2C3_PP_R               (*((volatile uint32_t *)0x40023FC0))
+#define I2C3_PC_R               (*((volatile uint32_t *)0x40023FC4))
+
+//*****************************************************************************
+//
+// PWM registers (PWM0)
+//
+//*****************************************************************************
+#define PWM0_CTL_R              (*((volatile uint32_t *)0x40028000))
+#define PWM0_SYNC_R             (*((volatile uint32_t *)0x40028004))
+#define PWM0_ENABLE_R           (*((volatile uint32_t *)0x40028008))
+#define PWM0_INVERT_R           (*((volatile uint32_t *)0x4002800C))
+#define PWM0_FAULT_R            (*((volatile uint32_t *)0x40028010))
+#define PWM0_INTEN_R            (*((volatile uint32_t *)0x40028014))
+#define PWM0_RIS_R              (*((volatile uint32_t *)0x40028018))
+#define PWM0_ISC_R              (*((volatile uint32_t *)0x4002801C))
+#define PWM0_STATUS_R           (*((volatile uint32_t *)0x40028020))
+#define PWM0_FAULTVAL_R         (*((volatile uint32_t *)0x40028024))
+#define PWM0_ENUPD_R            (*((volatile uint32_t *)0x40028028))
+#define PWM0_0_CTL_R            (*((volatile uint32_t *)0x40028040))
+#define PWM0_0_INTEN_R          (*((volatile uint32_t *)0x40028044))
+#define PWM0_0_RIS_R            (*((volatile uint32_t *)0x40028048))
+#define PWM0_0_ISC_R            (*((volatile uint32_t *)0x4002804C))
+#define PWM0_0_LOAD_R           (*((volatile uint32_t *)0x40028050))
+#define PWM0_0_COUNT_R          (*((volatile uint32_t *)0x40028054))
+#define PWM0_0_CMPA_R           (*((volatile uint32_t *)0x40028058))
+#define PWM0_0_CMPB_R           (*((volatile uint32_t *)0x4002805C))
+#define PWM0_0_GENA_R           (*((volatile uint32_t *)0x40028060))
+#define PWM0_0_GENB_R           (*((volatile uint32_t *)0x40028064))
+#define PWM0_0_DBCTL_R          (*((volatile uint32_t *)0x40028068))
+#define PWM0_0_DBRISE_R         (*((volatile uint32_t *)0x4002806C))
+#define PWM0_0_DBFALL_R         (*((volatile uint32_t *)0x40028070))
+#define PWM0_0_FLTSRC0_R        (*((volatile uint32_t *)0x40028074))
+#define PWM0_0_FLTSRC1_R        (*((volatile uint32_t *)0x40028078))
+#define PWM0_0_MINFLTPER_R      (*((volatile uint32_t *)0x4002807C))
+#define PWM0_1_CTL_R            (*((volatile uint32_t *)0x40028080))
+#define PWM0_1_INTEN_R          (*((volatile uint32_t *)0x40028084))
+#define PWM0_1_RIS_R            (*((volatile uint32_t *)0x40028088))
+#define PWM0_1_ISC_R            (*((volatile uint32_t *)0x4002808C))
+#define PWM0_1_LOAD_R           (*((volatile uint32_t *)0x40028090))
+#define PWM0_1_COUNT_R          (*((volatile uint32_t *)0x40028094))
+#define PWM0_1_CMPA_R           (*((volatile uint32_t *)0x40028098))
+#define PWM0_1_CMPB_R           (*((volatile uint32_t *)0x4002809C))
+#define PWM0_1_GENA_R           (*((volatile uint32_t *)0x400280A0))
+#define PWM0_1_GENB_R           (*((volatile uint32_t *)0x400280A4))
+#define PWM0_1_DBCTL_R          (*((volatile uint32_t *)0x400280A8))
+#define PWM0_1_DBRISE_R         (*((volatile uint32_t *)0x400280AC))
+#define PWM0_1_DBFALL_R         (*((volatile uint32_t *)0x400280B0))
+#define PWM0_1_FLTSRC0_R        (*((volatile uint32_t *)0x400280B4))
+#define PWM0_1_FLTSRC1_R        (*((volatile uint32_t *)0x400280B8))
+#define PWM0_1_MINFLTPER_R      (*((volatile uint32_t *)0x400280BC))
+#define PWM0_2_CTL_R            (*((volatile uint32_t *)0x400280C0))
+#define PWM0_2_INTEN_R          (*((volatile uint32_t *)0x400280C4))
+#define PWM0_2_RIS_R            (*((volatile uint32_t *)0x400280C8))
+#define PWM0_2_ISC_R            (*((volatile uint32_t *)0x400280CC))
+#define PWM0_2_LOAD_R           (*((volatile uint32_t *)0x400280D0))
+#define PWM0_2_COUNT_R          (*((volatile uint32_t *)0x400280D4))
+#define PWM0_2_CMPA_R           (*((volatile uint32_t *)0x400280D8))
+#define PWM0_2_CMPB_R           (*((volatile uint32_t *)0x400280DC))
+#define PWM0_2_GENA_R           (*((volatile uint32_t *)0x400280E0))
+#define PWM0_2_GENB_R           (*((volatile uint32_t *)0x400280E4))
+#define PWM0_2_DBCTL_R          (*((volatile uint32_t *)0x400280E8))
+#define PWM0_2_DBRISE_R         (*((volatile uint32_t *)0x400280EC))
+#define PWM0_2_DBFALL_R         (*((volatile uint32_t *)0x400280F0))
+#define PWM0_2_FLTSRC0_R        (*((volatile uint32_t *)0x400280F4))
+#define PWM0_2_FLTSRC1_R        (*((volatile uint32_t *)0x400280F8))
+#define PWM0_2_MINFLTPER_R      (*((volatile uint32_t *)0x400280FC))
+#define PWM0_3_CTL_R            (*((volatile uint32_t *)0x40028100))
+#define PWM0_3_INTEN_R          (*((volatile uint32_t *)0x40028104))
+#define PWM0_3_RIS_R            (*((volatile uint32_t *)0x40028108))
+#define PWM0_3_ISC_R            (*((volatile uint32_t *)0x4002810C))
+#define PWM0_3_LOAD_R           (*((volatile uint32_t *)0x40028110))
+#define PWM0_3_COUNT_R          (*((volatile uint32_t *)0x40028114))
+#define PWM0_3_CMPA_R           (*((volatile uint32_t *)0x40028118))
+#define PWM0_3_CMPB_R           (*((volatile uint32_t *)0x4002811C))
+#define PWM0_3_GENA_R           (*((volatile uint32_t *)0x40028120))
+#define PWM0_3_GENB_R           (*((volatile uint32_t *)0x40028124))
+#define PWM0_3_DBCTL_R          (*((volatile uint32_t *)0x40028128))
+#define PWM0_3_DBRISE_R         (*((volatile uint32_t *)0x4002812C))
+#define PWM0_3_DBFALL_R         (*((volatile uint32_t *)0x40028130))
+#define PWM0_3_FLTSRC0_R        (*((volatile uint32_t *)0x40028134))
+#define PWM0_3_FLTSRC1_R        (*((volatile uint32_t *)0x40028138))
+#define PWM0_3_MINFLTPER_R      (*((volatile uint32_t *)0x4002813C))
+#define PWM0_0_FLTSEN_R         (*((volatile uint32_t *)0x40028800))
+#define PWM0_0_FLTSTAT0_R       (*((volatile uint32_t *)0x40028804))
+#define PWM0_0_FLTSTAT1_R       (*((volatile uint32_t *)0x40028808))
+#define PWM0_1_FLTSEN_R         (*((volatile uint32_t *)0x40028880))
+#define PWM0_1_FLTSTAT0_R       (*((volatile uint32_t *)0x40028884))
+#define PWM0_1_FLTSTAT1_R       (*((volatile uint32_t *)0x40028888))
+#define PWM0_2_FLTSEN_R         (*((volatile uint32_t *)0x40028900))
+#define PWM0_2_FLTSTAT0_R       (*((volatile uint32_t *)0x40028904))
+#define PWM0_2_FLTSTAT1_R       (*((volatile uint32_t *)0x40028908))
+#define PWM0_3_FLTSEN_R         (*((volatile uint32_t *)0x40028980))
+#define PWM0_3_FLTSTAT0_R       (*((volatile uint32_t *)0x40028984))
+#define PWM0_3_FLTSTAT1_R       (*((volatile uint32_t *)0x40028988))
+#define PWM0_PP_R               (*((volatile uint32_t *)0x40028FC0))
+#define PWM0_CC_R               (*((volatile uint32_t *)0x40028FC8))
+
+//*****************************************************************************
+//
+// QEI registers (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R              (*((volatile uint32_t *)0x4002C000))
+#define QEI0_STAT_R             (*((volatile uint32_t *)0x4002C004))
+#define QEI0_POS_R              (*((volatile uint32_t *)0x4002C008))
+#define QEI0_MAXPOS_R           (*((volatile uint32_t *)0x4002C00C))
+#define QEI0_LOAD_R             (*((volatile uint32_t *)0x4002C010))
+#define QEI0_TIME_R             (*((volatile uint32_t *)0x4002C014))
+#define QEI0_COUNT_R            (*((volatile uint32_t *)0x4002C018))
+#define QEI0_SPEED_R            (*((volatile uint32_t *)0x4002C01C))
+#define QEI0_INTEN_R            (*((volatile uint32_t *)0x4002C020))
+#define QEI0_RIS_R              (*((volatile uint32_t *)0x4002C024))
+#define QEI0_ISC_R              (*((volatile uint32_t *)0x4002C028))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R            (*((volatile uint32_t *)0x40030000))
+#define TIMER0_TAMR_R           (*((volatile uint32_t *)0x40030004))
+#define TIMER0_TBMR_R           (*((volatile uint32_t *)0x40030008))
+#define TIMER0_CTL_R            (*((volatile uint32_t *)0x4003000C))
+#define TIMER0_SYNC_R           (*((volatile uint32_t *)0x40030010))
+#define TIMER0_IMR_R            (*((volatile uint32_t *)0x40030018))
+#define TIMER0_RIS_R            (*((volatile uint32_t *)0x4003001C))
+#define TIMER0_MIS_R            (*((volatile uint32_t *)0x40030020))
+#define TIMER0_ICR_R            (*((volatile uint32_t *)0x40030024))
+#define TIMER0_TAILR_R          (*((volatile uint32_t *)0x40030028))
+#define TIMER0_TBILR_R          (*((volatile uint32_t *)0x4003002C))
+#define TIMER0_TAMATCHR_R       (*((volatile uint32_t *)0x40030030))
+#define TIMER0_TBMATCHR_R       (*((volatile uint32_t *)0x40030034))
+#define TIMER0_TAPR_R           (*((volatile uint32_t *)0x40030038))
+#define TIMER0_TBPR_R           (*((volatile uint32_t *)0x4003003C))
+#define TIMER0_TAPMR_R          (*((volatile uint32_t *)0x40030040))
+#define TIMER0_TBPMR_R          (*((volatile uint32_t *)0x40030044))
+#define TIMER0_TAR_R            (*((volatile uint32_t *)0x40030048))
+#define TIMER0_TBR_R            (*((volatile uint32_t *)0x4003004C))
+#define TIMER0_TAV_R            (*((volatile uint32_t *)0x40030050))
+#define TIMER0_TBV_R            (*((volatile uint32_t *)0x40030054))
+#define TIMER0_RTCPD_R          (*((volatile uint32_t *)0x40030058))
+#define TIMER0_TAPS_R           (*((volatile uint32_t *)0x4003005C))
+#define TIMER0_TBPS_R           (*((volatile uint32_t *)0x40030060))
+#define TIMER0_DMAEV_R          (*((volatile uint32_t *)0x4003006C))
+#define TIMER0_ADCEV_R          (*((volatile uint32_t *)0x40030070))
+#define TIMER0_PP_R             (*((volatile uint32_t *)0x40030FC0))
+#define TIMER0_CC_R             (*((volatile uint32_t *)0x40030FC8))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R            (*((volatile uint32_t *)0x40031000))
+#define TIMER1_TAMR_R           (*((volatile uint32_t *)0x40031004))
+#define TIMER1_TBMR_R           (*((volatile uint32_t *)0x40031008))
+#define TIMER1_CTL_R            (*((volatile uint32_t *)0x4003100C))
+#define TIMER1_SYNC_R           (*((volatile uint32_t *)0x40031010))
+#define TIMER1_IMR_R            (*((volatile uint32_t *)0x40031018))
+#define TIMER1_RIS_R            (*((volatile uint32_t *)0x4003101C))
+#define TIMER1_MIS_R            (*((volatile uint32_t *)0x40031020))
+#define TIMER1_ICR_R            (*((volatile uint32_t *)0x40031024))
+#define TIMER1_TAILR_R          (*((volatile uint32_t *)0x40031028))
+#define TIMER1_TBILR_R          (*((volatile uint32_t *)0x4003102C))
+#define TIMER1_TAMATCHR_R       (*((volatile uint32_t *)0x40031030))
+#define TIMER1_TBMATCHR_R       (*((volatile uint32_t *)0x40031034))
+#define TIMER1_TAPR_R           (*((volatile uint32_t *)0x40031038))
+#define TIMER1_TBPR_R           (*((volatile uint32_t *)0x4003103C))
+#define TIMER1_TAPMR_R          (*((volatile uint32_t *)0x40031040))
+#define TIMER1_TBPMR_R          (*((volatile uint32_t *)0x40031044))
+#define TIMER1_TAR_R            (*((volatile uint32_t *)0x40031048))
+#define TIMER1_TBR_R            (*((volatile uint32_t *)0x4003104C))
+#define TIMER1_TAV_R            (*((volatile uint32_t *)0x40031050))
+#define TIMER1_TBV_R            (*((volatile uint32_t *)0x40031054))
+#define TIMER1_RTCPD_R          (*((volatile uint32_t *)0x40031058))
+#define TIMER1_TAPS_R           (*((volatile uint32_t *)0x4003105C))
+#define TIMER1_TBPS_R           (*((volatile uint32_t *)0x40031060))
+#define TIMER1_DMAEV_R          (*((volatile uint32_t *)0x4003106C))
+#define TIMER1_ADCEV_R          (*((volatile uint32_t *)0x40031070))
+#define TIMER1_PP_R             (*((volatile uint32_t *)0x40031FC0))
+#define TIMER1_CC_R             (*((volatile uint32_t *)0x40031FC8))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R            (*((volatile uint32_t *)0x40032000))
+#define TIMER2_TAMR_R           (*((volatile uint32_t *)0x40032004))
+#define TIMER2_TBMR_R           (*((volatile uint32_t *)0x40032008))
+#define TIMER2_CTL_R            (*((volatile uint32_t *)0x4003200C))
+#define TIMER2_SYNC_R           (*((volatile uint32_t *)0x40032010))
+#define TIMER2_IMR_R            (*((volatile uint32_t *)0x40032018))
+#define TIMER2_RIS_R            (*((volatile uint32_t *)0x4003201C))
+#define TIMER2_MIS_R            (*((volatile uint32_t *)0x40032020))
+#define TIMER2_ICR_R            (*((volatile uint32_t *)0x40032024))
+#define TIMER2_TAILR_R          (*((volatile uint32_t *)0x40032028))
+#define TIMER2_TBILR_R          (*((volatile uint32_t *)0x4003202C))
+#define TIMER2_TAMATCHR_R       (*((volatile uint32_t *)0x40032030))
+#define TIMER2_TBMATCHR_R       (*((volatile uint32_t *)0x40032034))
+#define TIMER2_TAPR_R           (*((volatile uint32_t *)0x40032038))
+#define TIMER2_TBPR_R           (*((volatile uint32_t *)0x4003203C))
+#define TIMER2_TAPMR_R          (*((volatile uint32_t *)0x40032040))
+#define TIMER2_TBPMR_R          (*((volatile uint32_t *)0x40032044))
+#define TIMER2_TAR_R            (*((volatile uint32_t *)0x40032048))
+#define TIMER2_TBR_R            (*((volatile uint32_t *)0x4003204C))
+#define TIMER2_TAV_R            (*((volatile uint32_t *)0x40032050))
+#define TIMER2_TBV_R            (*((volatile uint32_t *)0x40032054))
+#define TIMER2_RTCPD_R          (*((volatile uint32_t *)0x40032058))
+#define TIMER2_TAPS_R           (*((volatile uint32_t *)0x4003205C))
+#define TIMER2_TBPS_R           (*((volatile uint32_t *)0x40032060))
+#define TIMER2_DMAEV_R          (*((volatile uint32_t *)0x4003206C))
+#define TIMER2_ADCEV_R          (*((volatile uint32_t *)0x40032070))
+#define TIMER2_PP_R             (*((volatile uint32_t *)0x40032FC0))
+#define TIMER2_CC_R             (*((volatile uint32_t *)0x40032FC8))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R            (*((volatile uint32_t *)0x40033000))
+#define TIMER3_TAMR_R           (*((volatile uint32_t *)0x40033004))
+#define TIMER3_TBMR_R           (*((volatile uint32_t *)0x40033008))
+#define TIMER3_CTL_R            (*((volatile uint32_t *)0x4003300C))
+#define TIMER3_SYNC_R           (*((volatile uint32_t *)0x40033010))
+#define TIMER3_IMR_R            (*((volatile uint32_t *)0x40033018))
+#define TIMER3_RIS_R            (*((volatile uint32_t *)0x4003301C))
+#define TIMER3_MIS_R            (*((volatile uint32_t *)0x40033020))
+#define TIMER3_ICR_R            (*((volatile uint32_t *)0x40033024))
+#define TIMER3_TAILR_R          (*((volatile uint32_t *)0x40033028))
+#define TIMER3_TBILR_R          (*((volatile uint32_t *)0x4003302C))
+#define TIMER3_TAMATCHR_R       (*((volatile uint32_t *)0x40033030))
+#define TIMER3_TBMATCHR_R       (*((volatile uint32_t *)0x40033034))
+#define TIMER3_TAPR_R           (*((volatile uint32_t *)0x40033038))
+#define TIMER3_TBPR_R           (*((volatile uint32_t *)0x4003303C))
+#define TIMER3_TAPMR_R          (*((volatile uint32_t *)0x40033040))
+#define TIMER3_TBPMR_R          (*((volatile uint32_t *)0x40033044))
+#define TIMER3_TAR_R            (*((volatile uint32_t *)0x40033048))
+#define TIMER3_TBR_R            (*((volatile uint32_t *)0x4003304C))
+#define TIMER3_TAV_R            (*((volatile uint32_t *)0x40033050))
+#define TIMER3_TBV_R            (*((volatile uint32_t *)0x40033054))
+#define TIMER3_RTCPD_R          (*((volatile uint32_t *)0x40033058))
+#define TIMER3_TAPS_R           (*((volatile uint32_t *)0x4003305C))
+#define TIMER3_TBPS_R           (*((volatile uint32_t *)0x40033060))
+#define TIMER3_DMAEV_R          (*((volatile uint32_t *)0x4003306C))
+#define TIMER3_ADCEV_R          (*((volatile uint32_t *)0x40033070))
+#define TIMER3_PP_R             (*((volatile uint32_t *)0x40033FC0))
+#define TIMER3_CC_R             (*((volatile uint32_t *)0x40033FC8))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER4)
+//
+//*****************************************************************************
+#define TIMER4_CFG_R            (*((volatile uint32_t *)0x40034000))
+#define TIMER4_TAMR_R           (*((volatile uint32_t *)0x40034004))
+#define TIMER4_TBMR_R           (*((volatile uint32_t *)0x40034008))
+#define TIMER4_CTL_R            (*((volatile uint32_t *)0x4003400C))
+#define TIMER4_SYNC_R           (*((volatile uint32_t *)0x40034010))
+#define TIMER4_IMR_R            (*((volatile uint32_t *)0x40034018))
+#define TIMER4_RIS_R            (*((volatile uint32_t *)0x4003401C))
+#define TIMER4_MIS_R            (*((volatile uint32_t *)0x40034020))
+#define TIMER4_ICR_R            (*((volatile uint32_t *)0x40034024))
+#define TIMER4_TAILR_R          (*((volatile uint32_t *)0x40034028))
+#define TIMER4_TBILR_R          (*((volatile uint32_t *)0x4003402C))
+#define TIMER4_TAMATCHR_R       (*((volatile uint32_t *)0x40034030))
+#define TIMER4_TBMATCHR_R       (*((volatile uint32_t *)0x40034034))
+#define TIMER4_TAPR_R           (*((volatile uint32_t *)0x40034038))
+#define TIMER4_TBPR_R           (*((volatile uint32_t *)0x4003403C))
+#define TIMER4_TAPMR_R          (*((volatile uint32_t *)0x40034040))
+#define TIMER4_TBPMR_R          (*((volatile uint32_t *)0x40034044))
+#define TIMER4_TAR_R            (*((volatile uint32_t *)0x40034048))
+#define TIMER4_TBR_R            (*((volatile uint32_t *)0x4003404C))
+#define TIMER4_TAV_R            (*((volatile uint32_t *)0x40034050))
+#define TIMER4_TBV_R            (*((volatile uint32_t *)0x40034054))
+#define TIMER4_RTCPD_R          (*((volatile uint32_t *)0x40034058))
+#define TIMER4_TAPS_R           (*((volatile uint32_t *)0x4003405C))
+#define TIMER4_TBPS_R           (*((volatile uint32_t *)0x40034060))
+#define TIMER4_DMAEV_R          (*((volatile uint32_t *)0x4003406C))
+#define TIMER4_ADCEV_R          (*((volatile uint32_t *)0x40034070))
+#define TIMER4_PP_R             (*((volatile uint32_t *)0x40034FC0))
+#define TIMER4_CC_R             (*((volatile uint32_t *)0x40034FC8))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER5)
+//
+//*****************************************************************************
+#define TIMER5_CFG_R            (*((volatile uint32_t *)0x40035000))
+#define TIMER5_TAMR_R           (*((volatile uint32_t *)0x40035004))
+#define TIMER5_TBMR_R           (*((volatile uint32_t *)0x40035008))
+#define TIMER5_CTL_R            (*((volatile uint32_t *)0x4003500C))
+#define TIMER5_SYNC_R           (*((volatile uint32_t *)0x40035010))
+#define TIMER5_IMR_R            (*((volatile uint32_t *)0x40035018))
+#define TIMER5_RIS_R            (*((volatile uint32_t *)0x4003501C))
+#define TIMER5_MIS_R            (*((volatile uint32_t *)0x40035020))
+#define TIMER5_ICR_R            (*((volatile uint32_t *)0x40035024))
+#define TIMER5_TAILR_R          (*((volatile uint32_t *)0x40035028))
+#define TIMER5_TBILR_R          (*((volatile uint32_t *)0x4003502C))
+#define TIMER5_TAMATCHR_R       (*((volatile uint32_t *)0x40035030))
+#define TIMER5_TBMATCHR_R       (*((volatile uint32_t *)0x40035034))
+#define TIMER5_TAPR_R           (*((volatile uint32_t *)0x40035038))
+#define TIMER5_TBPR_R           (*((volatile uint32_t *)0x4003503C))
+#define TIMER5_TAPMR_R          (*((volatile uint32_t *)0x40035040))
+#define TIMER5_TBPMR_R          (*((volatile uint32_t *)0x40035044))
+#define TIMER5_TAR_R            (*((volatile uint32_t *)0x40035048))
+#define TIMER5_TBR_R            (*((volatile uint32_t *)0x4003504C))
+#define TIMER5_TAV_R            (*((volatile uint32_t *)0x40035050))
+#define TIMER5_TBV_R            (*((volatile uint32_t *)0x40035054))
+#define TIMER5_RTCPD_R          (*((volatile uint32_t *)0x40035058))
+#define TIMER5_TAPS_R           (*((volatile uint32_t *)0x4003505C))
+#define TIMER5_TBPS_R           (*((volatile uint32_t *)0x40035060))
+#define TIMER5_DMAEV_R          (*((volatile uint32_t *)0x4003506C))
+#define TIMER5_ADCEV_R          (*((volatile uint32_t *)0x40035070))
+#define TIMER5_PP_R             (*((volatile uint32_t *)0x40035FC0))
+#define TIMER5_CC_R             (*((volatile uint32_t *)0x40035FC8))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R            (*((volatile uint32_t *)0x40038000))
+#define ADC0_RIS_R              (*((volatile uint32_t *)0x40038004))
+#define ADC0_IM_R               (*((volatile uint32_t *)0x40038008))
+#define ADC0_ISC_R              (*((volatile uint32_t *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile uint32_t *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile uint32_t *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile uint32_t *)0x40038018))
+#define ADC0_TSSEL_R            (*((volatile uint32_t *)0x4003801C))
+#define ADC0_SSPRI_R            (*((volatile uint32_t *)0x40038020))
+#define ADC0_SPC_R              (*((volatile uint32_t *)0x40038024))
+#define ADC0_PSSI_R             (*((volatile uint32_t *)0x40038028))
+#define ADC0_SAC_R              (*((volatile uint32_t *)0x40038030))
+#define ADC0_DCISC_R            (*((volatile uint32_t *)0x40038034))
+#define ADC0_CTL_R              (*((volatile uint32_t *)0x40038038))
+#define ADC0_SSMUX0_R           (*((volatile uint32_t *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile uint32_t *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile uint32_t *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile uint32_t *)0x4003804C))
+#define ADC0_SSOP0_R            (*((volatile uint32_t *)0x40038050))
+#define ADC0_SSDC0_R            (*((volatile uint32_t *)0x40038054))
+#define ADC0_SSEMUX0_R          (*((volatile uint32_t *)0x40038058))
+#define ADC0_SSTSH0_R           (*((volatile uint32_t *)0x4003805C))
+#define ADC0_SSMUX1_R           (*((volatile uint32_t *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile uint32_t *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile uint32_t *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile uint32_t *)0x4003806C))
+#define ADC0_SSOP1_R            (*((volatile uint32_t *)0x40038070))
+#define ADC0_SSDC1_R            (*((volatile uint32_t *)0x40038074))
+#define ADC0_SSEMUX1_R          (*((volatile uint32_t *)0x40038078))
+#define ADC0_SSTSH1_R           (*((volatile uint32_t *)0x4003807C))
+#define ADC0_SSMUX2_R           (*((volatile uint32_t *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile uint32_t *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile uint32_t *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile uint32_t *)0x4003808C))
+#define ADC0_SSOP2_R            (*((volatile uint32_t *)0x40038090))
+#define ADC0_SSDC2_R            (*((volatile uint32_t *)0x40038094))
+#define ADC0_SSEMUX2_R          (*((volatile uint32_t *)0x40038098))
+#define ADC0_SSTSH2_R           (*((volatile uint32_t *)0x4003809C))
+#define ADC0_SSMUX3_R           (*((volatile uint32_t *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile uint32_t *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile uint32_t *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile uint32_t *)0x400380AC))
+#define ADC0_SSOP3_R            (*((volatile uint32_t *)0x400380B0))
+#define ADC0_SSDC3_R            (*((volatile uint32_t *)0x400380B4))
+#define ADC0_SSEMUX3_R          (*((volatile uint32_t *)0x400380B8))
+#define ADC0_SSTSH3_R           (*((volatile uint32_t *)0x400380BC))
+#define ADC0_DCRIC_R            (*((volatile uint32_t *)0x40038D00))
+#define ADC0_DCCTL0_R           (*((volatile uint32_t *)0x40038E00))
+#define ADC0_DCCTL1_R           (*((volatile uint32_t *)0x40038E04))
+#define ADC0_DCCTL2_R           (*((volatile uint32_t *)0x40038E08))
+#define ADC0_DCCTL3_R           (*((volatile uint32_t *)0x40038E0C))
+#define ADC0_DCCTL4_R           (*((volatile uint32_t *)0x40038E10))
+#define ADC0_DCCTL5_R           (*((volatile uint32_t *)0x40038E14))
+#define ADC0_DCCTL6_R           (*((volatile uint32_t *)0x40038E18))
+#define ADC0_DCCTL7_R           (*((volatile uint32_t *)0x40038E1C))
+#define ADC0_DCCMP0_R           (*((volatile uint32_t *)0x40038E40))
+#define ADC0_DCCMP1_R           (*((volatile uint32_t *)0x40038E44))
+#define ADC0_DCCMP2_R           (*((volatile uint32_t *)0x40038E48))
+#define ADC0_DCCMP3_R           (*((volatile uint32_t *)0x40038E4C))
+#define ADC0_DCCMP4_R           (*((volatile uint32_t *)0x40038E50))
+#define ADC0_DCCMP5_R           (*((volatile uint32_t *)0x40038E54))
+#define ADC0_DCCMP6_R           (*((volatile uint32_t *)0x40038E58))
+#define ADC0_DCCMP7_R           (*((volatile uint32_t *)0x40038E5C))
+#define ADC0_PP_R               (*((volatile uint32_t *)0x40038FC0))
+#define ADC0_PC_R               (*((volatile uint32_t *)0x40038FC4))
+#define ADC0_CC_R               (*((volatile uint32_t *)0x40038FC8))
+
+//*****************************************************************************
+//
+// ADC registers (ADC1)
+//
+//*****************************************************************************
+#define ADC1_ACTSS_R            (*((volatile uint32_t *)0x40039000))
+#define ADC1_RIS_R              (*((volatile uint32_t *)0x40039004))
+#define ADC1_IM_R               (*((volatile uint32_t *)0x40039008))
+#define ADC1_ISC_R              (*((volatile uint32_t *)0x4003900C))
+#define ADC1_OSTAT_R            (*((volatile uint32_t *)0x40039010))
+#define ADC1_EMUX_R             (*((volatile uint32_t *)0x40039014))
+#define ADC1_USTAT_R            (*((volatile uint32_t *)0x40039018))
+#define ADC1_TSSEL_R            (*((volatile uint32_t *)0x4003901C))
+#define ADC1_SSPRI_R            (*((volatile uint32_t *)0x40039020))
+#define ADC1_SPC_R              (*((volatile uint32_t *)0x40039024))
+#define ADC1_PSSI_R             (*((volatile uint32_t *)0x40039028))
+#define ADC1_SAC_R              (*((volatile uint32_t *)0x40039030))
+#define ADC1_DCISC_R            (*((volatile uint32_t *)0x40039034))
+#define ADC1_CTL_R              (*((volatile uint32_t *)0x40039038))
+#define ADC1_SSMUX0_R           (*((volatile uint32_t *)0x40039040))
+#define ADC1_SSCTL0_R           (*((volatile uint32_t *)0x40039044))
+#define ADC1_SSFIFO0_R          (*((volatile uint32_t *)0x40039048))
+#define ADC1_SSFSTAT0_R         (*((volatile uint32_t *)0x4003904C))
+#define ADC1_SSOP0_R            (*((volatile uint32_t *)0x40039050))
+#define ADC1_SSDC0_R            (*((volatile uint32_t *)0x40039054))
+#define ADC1_SSEMUX0_R          (*((volatile uint32_t *)0x40039058))
+#define ADC1_SSTSH0_R           (*((volatile uint32_t *)0x4003905C))
+#define ADC1_SSMUX1_R           (*((volatile uint32_t *)0x40039060))
+#define ADC1_SSCTL1_R           (*((volatile uint32_t *)0x40039064))
+#define ADC1_SSFIFO1_R          (*((volatile uint32_t *)0x40039068))
+#define ADC1_SSFSTAT1_R         (*((volatile uint32_t *)0x4003906C))
+#define ADC1_SSOP1_R            (*((volatile uint32_t *)0x40039070))
+#define ADC1_SSDC1_R            (*((volatile uint32_t *)0x40039074))
+#define ADC1_SSEMUX1_R          (*((volatile uint32_t *)0x40039078))
+#define ADC1_SSTSH1_R           (*((volatile uint32_t *)0x4003907C))
+#define ADC1_SSMUX2_R           (*((volatile uint32_t *)0x40039080))
+#define ADC1_SSCTL2_R           (*((volatile uint32_t *)0x40039084))
+#define ADC1_SSFIFO2_R          (*((volatile uint32_t *)0x40039088))
+#define ADC1_SSFSTAT2_R         (*((volatile uint32_t *)0x4003908C))
+#define ADC1_SSOP2_R            (*((volatile uint32_t *)0x40039090))
+#define ADC1_SSDC2_R            (*((volatile uint32_t *)0x40039094))
+#define ADC1_SSEMUX2_R          (*((volatile uint32_t *)0x40039098))
+#define ADC1_SSTSH2_R           (*((volatile uint32_t *)0x4003909C))
+#define ADC1_SSMUX3_R           (*((volatile uint32_t *)0x400390A0))
+#define ADC1_SSCTL3_R           (*((volatile uint32_t *)0x400390A4))
+#define ADC1_SSFIFO3_R          (*((volatile uint32_t *)0x400390A8))
+#define ADC1_SSFSTAT3_R         (*((volatile uint32_t *)0x400390AC))
+#define ADC1_SSOP3_R            (*((volatile uint32_t *)0x400390B0))
+#define ADC1_SSDC3_R            (*((volatile uint32_t *)0x400390B4))
+#define ADC1_SSEMUX3_R          (*((volatile uint32_t *)0x400390B8))
+#define ADC1_SSTSH3_R           (*((volatile uint32_t *)0x400390BC))
+#define ADC1_DCRIC_R            (*((volatile uint32_t *)0x40039D00))
+#define ADC1_DCCTL0_R           (*((volatile uint32_t *)0x40039E00))
+#define ADC1_DCCTL1_R           (*((volatile uint32_t *)0x40039E04))
+#define ADC1_DCCTL2_R           (*((volatile uint32_t *)0x40039E08))
+#define ADC1_DCCTL3_R           (*((volatile uint32_t *)0x40039E0C))
+#define ADC1_DCCTL4_R           (*((volatile uint32_t *)0x40039E10))
+#define ADC1_DCCTL5_R           (*((volatile uint32_t *)0x40039E14))
+#define ADC1_DCCTL6_R           (*((volatile uint32_t *)0x40039E18))
+#define ADC1_DCCTL7_R           (*((volatile uint32_t *)0x40039E1C))
+#define ADC1_DCCMP0_R           (*((volatile uint32_t *)0x40039E40))
+#define ADC1_DCCMP1_R           (*((volatile uint32_t *)0x40039E44))
+#define ADC1_DCCMP2_R           (*((volatile uint32_t *)0x40039E48))
+#define ADC1_DCCMP3_R           (*((volatile uint32_t *)0x40039E4C))
+#define ADC1_DCCMP4_R           (*((volatile uint32_t *)0x40039E50))
+#define ADC1_DCCMP5_R           (*((volatile uint32_t *)0x40039E54))
+#define ADC1_DCCMP6_R           (*((volatile uint32_t *)0x40039E58))
+#define ADC1_DCCMP7_R           (*((volatile uint32_t *)0x40039E5C))
+#define ADC1_PP_R               (*((volatile uint32_t *)0x40039FC0))
+#define ADC1_PC_R               (*((volatile uint32_t *)0x40039FC4))
+#define ADC1_CC_R               (*((volatile uint32_t *)0x40039FC8))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R            (*((volatile uint32_t *)0x4003C000))
+#define COMP_ACRIS_R            (*((volatile uint32_t *)0x4003C004))
+#define COMP_ACINTEN_R          (*((volatile uint32_t *)0x4003C008))
+#define COMP_ACREFCTL_R         (*((volatile uint32_t *)0x4003C010))
+#define COMP_ACSTAT0_R          (*((volatile uint32_t *)0x4003C020))
+#define COMP_ACCTL0_R           (*((volatile uint32_t *)0x4003C024))
+#define COMP_ACSTAT1_R          (*((volatile uint32_t *)0x4003C040))
+#define COMP_ACCTL1_R           (*((volatile uint32_t *)0x4003C044))
+#define COMP_ACSTAT2_R          (*((volatile uint32_t *)0x4003C060))
+#define COMP_ACCTL2_R           (*((volatile uint32_t *)0x4003C064))
+#define COMP_PP_R               (*((volatile uint32_t *)0x4003CFC0))
+
+//*****************************************************************************
+//
+// CAN registers (CAN0)
+//
+//*****************************************************************************
+#define CAN0_CTL_R              (*((volatile uint32_t *)0x40040000))
+#define CAN0_STS_R              (*((volatile uint32_t *)0x40040004))
+#define CAN0_ERR_R              (*((volatile uint32_t *)0x40040008))
+#define CAN0_BIT_R              (*((volatile uint32_t *)0x4004000C))
+#define CAN0_INT_R              (*((volatile uint32_t *)0x40040010))
+#define CAN0_TST_R              (*((volatile uint32_t *)0x40040014))
+#define CAN0_BRPE_R             (*((volatile uint32_t *)0x40040018))
+#define CAN0_IF1CRQ_R           (*((volatile uint32_t *)0x40040020))
+#define CAN0_IF1CMSK_R          (*((volatile uint32_t *)0x40040024))
+#define CAN0_IF1MSK1_R          (*((volatile uint32_t *)0x40040028))
+#define CAN0_IF1MSK2_R          (*((volatile uint32_t *)0x4004002C))
+#define CAN0_IF1ARB1_R          (*((volatile uint32_t *)0x40040030))
+#define CAN0_IF1ARB2_R          (*((volatile uint32_t *)0x40040034))
+#define CAN0_IF1MCTL_R          (*((volatile uint32_t *)0x40040038))
+#define CAN0_IF1DA1_R           (*((volatile uint32_t *)0x4004003C))
+#define CAN0_IF1DA2_R           (*((volatile uint32_t *)0x40040040))
+#define CAN0_IF1DB1_R           (*((volatile uint32_t *)0x40040044))
+#define CAN0_IF1DB2_R           (*((volatile uint32_t *)0x40040048))
+#define CAN0_IF2CRQ_R           (*((volatile uint32_t *)0x40040080))
+#define CAN0_IF2CMSK_R          (*((volatile uint32_t *)0x40040084))
+#define CAN0_IF2MSK1_R          (*((volatile uint32_t *)0x40040088))
+#define CAN0_IF2MSK2_R          (*((volatile uint32_t *)0x4004008C))
+#define CAN0_IF2ARB1_R          (*((volatile uint32_t *)0x40040090))
+#define CAN0_IF2ARB2_R          (*((volatile uint32_t *)0x40040094))
+#define CAN0_IF2MCTL_R          (*((volatile uint32_t *)0x40040098))
+#define CAN0_IF2DA1_R           (*((volatile uint32_t *)0x4004009C))
+#define CAN0_IF2DA2_R           (*((volatile uint32_t *)0x400400A0))
+#define CAN0_IF2DB1_R           (*((volatile uint32_t *)0x400400A4))
+#define CAN0_IF2DB2_R           (*((volatile uint32_t *)0x400400A8))
+#define CAN0_TXRQ1_R            (*((volatile uint32_t *)0x40040100))
+#define CAN0_TXRQ2_R            (*((volatile uint32_t *)0x40040104))
+#define CAN0_NWDA1_R            (*((volatile uint32_t *)0x40040120))
+#define CAN0_NWDA2_R            (*((volatile uint32_t *)0x40040124))
+#define CAN0_MSG1INT_R          (*((volatile uint32_t *)0x40040140))
+#define CAN0_MSG2INT_R          (*((volatile uint32_t *)0x40040144))
+#define CAN0_MSG1VAL_R          (*((volatile uint32_t *)0x40040160))
+#define CAN0_MSG2VAL_R          (*((volatile uint32_t *)0x40040164))
+
+//*****************************************************************************
+//
+// CAN registers (CAN1)
+//
+//*****************************************************************************
+#define CAN1_CTL_R              (*((volatile uint32_t *)0x40041000))
+#define CAN1_STS_R              (*((volatile uint32_t *)0x40041004))
+#define CAN1_ERR_R              (*((volatile uint32_t *)0x40041008))
+#define CAN1_BIT_R              (*((volatile uint32_t *)0x4004100C))
+#define CAN1_INT_R              (*((volatile uint32_t *)0x40041010))
+#define CAN1_TST_R              (*((volatile uint32_t *)0x40041014))
+#define CAN1_BRPE_R             (*((volatile uint32_t *)0x40041018))
+#define CAN1_IF1CRQ_R           (*((volatile uint32_t *)0x40041020))
+#define CAN1_IF1CMSK_R          (*((volatile uint32_t *)0x40041024))
+#define CAN1_IF1MSK1_R          (*((volatile uint32_t *)0x40041028))
+#define CAN1_IF1MSK2_R          (*((volatile uint32_t *)0x4004102C))
+#define CAN1_IF1ARB1_R          (*((volatile uint32_t *)0x40041030))
+#define CAN1_IF1ARB2_R          (*((volatile uint32_t *)0x40041034))
+#define CAN1_IF1MCTL_R          (*((volatile uint32_t *)0x40041038))
+#define CAN1_IF1DA1_R           (*((volatile uint32_t *)0x4004103C))
+#define CAN1_IF1DA2_R           (*((volatile uint32_t *)0x40041040))
+#define CAN1_IF1DB1_R           (*((volatile uint32_t *)0x40041044))
+#define CAN1_IF1DB2_R           (*((volatile uint32_t *)0x40041048))
+#define CAN1_IF2CRQ_R           (*((volatile uint32_t *)0x40041080))
+#define CAN1_IF2CMSK_R          (*((volatile uint32_t *)0x40041084))
+#define CAN1_IF2MSK1_R          (*((volatile uint32_t *)0x40041088))
+#define CAN1_IF2MSK2_R          (*((volatile uint32_t *)0x4004108C))
+#define CAN1_IF2ARB1_R          (*((volatile uint32_t *)0x40041090))
+#define CAN1_IF2ARB2_R          (*((volatile uint32_t *)0x40041094))
+#define CAN1_IF2MCTL_R          (*((volatile uint32_t *)0x40041098))
+#define CAN1_IF2DA1_R           (*((volatile uint32_t *)0x4004109C))
+#define CAN1_IF2DA2_R           (*((volatile uint32_t *)0x400410A0))
+#define CAN1_IF2DB1_R           (*((volatile uint32_t *)0x400410A4))
+#define CAN1_IF2DB2_R           (*((volatile uint32_t *)0x400410A8))
+#define CAN1_TXRQ1_R            (*((volatile uint32_t *)0x40041100))
+#define CAN1_TXRQ2_R            (*((volatile uint32_t *)0x40041104))
+#define CAN1_NWDA1_R            (*((volatile uint32_t *)0x40041120))
+#define CAN1_NWDA2_R            (*((volatile uint32_t *)0x40041124))
+#define CAN1_MSG1INT_R          (*((volatile uint32_t *)0x40041140))
+#define CAN1_MSG2INT_R          (*((volatile uint32_t *)0x40041144))
+#define CAN1_MSG1VAL_R          (*((volatile uint32_t *)0x40041160))
+#define CAN1_MSG2VAL_R          (*((volatile uint32_t *)0x40041164))
+
+//*****************************************************************************
+//
+// Univeral Serial Bus registers (USB0)
+//
+//*****************************************************************************
+#define USB0_FADDR_R            (*((volatile uint8_t *)0x40050000))
+#define USB0_POWER_R            (*((volatile uint8_t *)0x40050001))
+#define USB0_TXIS_R             (*((volatile uint16_t *)0x40050002))
+#define USB0_RXIS_R             (*((volatile uint16_t *)0x40050004))
+#define USB0_TXIE_R             (*((volatile uint16_t *)0x40050006))
+#define USB0_RXIE_R             (*((volatile uint16_t *)0x40050008))
+#define USB0_IS_R               (*((volatile uint8_t *)0x4005000A))
+#define USB0_IE_R               (*((volatile uint8_t *)0x4005000B))
+#define USB0_FRAME_R            (*((volatile uint16_t *)0x4005000C))
+#define USB0_EPIDX_R            (*((volatile uint8_t *)0x4005000E))
+#define USB0_TEST_R             (*((volatile uint8_t *)0x4005000F))
+#define USB0_FIFO0_R            (*((volatile uint32_t *)0x40050020))
+#define USB0_FIFO1_R            (*((volatile uint32_t *)0x40050024))
+#define USB0_FIFO2_R            (*((volatile uint32_t *)0x40050028))
+#define USB0_FIFO3_R            (*((volatile uint32_t *)0x4005002C))
+#define USB0_FIFO4_R            (*((volatile uint32_t *)0x40050030))
+#define USB0_FIFO5_R            (*((volatile uint32_t *)0x40050034))
+#define USB0_FIFO6_R            (*((volatile uint32_t *)0x40050038))
+#define USB0_FIFO7_R            (*((volatile uint32_t *)0x4005003C))
+#define USB0_DEVCTL_R           (*((volatile uint8_t *)0x40050060))
+#define USB0_CCONF_R            (*((volatile uint8_t *)0x40050061))
+#define USB0_TXFIFOSZ_R         (*((volatile uint8_t *)0x40050062))
+#define USB0_RXFIFOSZ_R         (*((volatile uint8_t *)0x40050063))
+#define USB0_TXFIFOADD_R        (*((volatile uint16_t *)0x40050064))
+#define USB0_RXFIFOADD_R        (*((volatile uint16_t *)0x40050066))
+#define USB0_ULPIVBUSCTL_R      (*((volatile uint8_t *)0x40050070))
+#define USB0_ULPIREGDATA_R      (*((volatile uint8_t *)0x40050074))
+#define USB0_ULPIREGADDR_R      (*((volatile uint8_t *)0x40050075))
+#define USB0_ULPIREGCTL_R       (*((volatile uint8_t *)0x40050076))
+#define USB0_EPINFO_R           (*((volatile uint8_t *)0x40050078))
+#define USB0_RAMINFO_R          (*((volatile uint8_t *)0x40050079))
+#define USB0_CONTIM_R           (*((volatile uint8_t *)0x4005007A))
+#define USB0_VPLEN_R            (*((volatile uint8_t *)0x4005007B))
+#define USB0_HSEOF_R            (*((volatile uint8_t *)0x4005007C))
+#define USB0_FSEOF_R            (*((volatile uint8_t *)0x4005007D))
+#define USB0_LSEOF_R            (*((volatile uint8_t *)0x4005007E))
+#define USB0_TXFUNCADDR0_R      (*((volatile uint8_t *)0x40050080))
+#define USB0_TXHUBADDR0_R       (*((volatile uint8_t *)0x40050082))
+#define USB0_TXHUBPORT0_R       (*((volatile uint8_t *)0x40050083))
+#define USB0_TXFUNCADDR1_R      (*((volatile uint8_t *)0x40050088))
+#define USB0_TXHUBADDR1_R       (*((volatile uint8_t *)0x4005008A))
+#define USB0_TXHUBPORT1_R       (*((volatile uint8_t *)0x4005008B))
+#define USB0_RXFUNCADDR1_R      (*((volatile uint8_t *)0x4005008C))
+#define USB0_RXHUBADDR1_R       (*((volatile uint8_t *)0x4005008E))
+#define USB0_RXHUBPORT1_R       (*((volatile uint8_t *)0x4005008F))
+#define USB0_TXFUNCADDR2_R      (*((volatile uint8_t *)0x40050090))
+#define USB0_TXHUBADDR2_R       (*((volatile uint8_t *)0x40050092))
+#define USB0_TXHUBPORT2_R       (*((volatile uint8_t *)0x40050093))
+#define USB0_RXFUNCADDR2_R      (*((volatile uint8_t *)0x40050094))
+#define USB0_RXHUBADDR2_R       (*((volatile uint8_t *)0x40050096))
+#define USB0_RXHUBPORT2_R       (*((volatile uint8_t *)0x40050097))
+#define USB0_TXFUNCADDR3_R      (*((volatile uint8_t *)0x40050098))
+#define USB0_TXHUBADDR3_R       (*((volatile uint8_t *)0x4005009A))
+#define USB0_TXHUBPORT3_R       (*((volatile uint8_t *)0x4005009B))
+#define USB0_RXFUNCADDR3_R      (*((volatile uint8_t *)0x4005009C))
+#define USB0_RXHUBADDR3_R       (*((volatile uint8_t *)0x4005009E))
+#define USB0_RXHUBPORT3_R       (*((volatile uint8_t *)0x4005009F))
+#define USB0_TXFUNCADDR4_R      (*((volatile uint8_t *)0x400500A0))
+#define USB0_TXHUBADDR4_R       (*((volatile uint8_t *)0x400500A2))
+#define USB0_TXHUBPORT4_R       (*((volatile uint8_t *)0x400500A3))
+#define USB0_RXFUNCADDR4_R      (*((volatile uint8_t *)0x400500A4))
+#define USB0_RXHUBADDR4_R       (*((volatile uint8_t *)0x400500A6))
+#define USB0_RXHUBPORT4_R       (*((volatile uint8_t *)0x400500A7))
+#define USB0_TXFUNCADDR5_R      (*((volatile uint8_t *)0x400500A8))
+#define USB0_TXHUBADDR5_R       (*((volatile uint8_t *)0x400500AA))
+#define USB0_TXHUBPORT5_R       (*((volatile uint8_t *)0x400500AB))
+#define USB0_RXFUNCADDR5_R      (*((volatile uint8_t *)0x400500AC))
+#define USB0_RXHUBADDR5_R       (*((volatile uint8_t *)0x400500AE))
+#define USB0_RXHUBPORT5_R       (*((volatile uint8_t *)0x400500AF))
+#define USB0_TXFUNCADDR6_R      (*((volatile uint8_t *)0x400500B0))
+#define USB0_TXHUBADDR6_R       (*((volatile uint8_t *)0x400500B2))
+#define USB0_TXHUBPORT6_R       (*((volatile uint8_t *)0x400500B3))
+#define USB0_RXFUNCADDR6_R      (*((volatile uint8_t *)0x400500B4))
+#define USB0_RXHUBADDR6_R       (*((volatile uint8_t *)0x400500B6))
+#define USB0_RXHUBPORT6_R       (*((volatile uint8_t *)0x400500B7))
+#define USB0_TXFUNCADDR7_R      (*((volatile uint8_t *)0x400500B8))
+#define USB0_TXHUBADDR7_R       (*((volatile uint8_t *)0x400500BA))
+#define USB0_TXHUBPORT7_R       (*((volatile uint8_t *)0x400500BB))
+#define USB0_RXFUNCADDR7_R      (*((volatile uint8_t *)0x400500BC))
+#define USB0_RXHUBADDR7_R       (*((volatile uint8_t *)0x400500BE))
+#define USB0_RXHUBPORT7_R       (*((volatile uint8_t *)0x400500BF))
+#define USB0_CSRL0_R            (*((volatile uint8_t *)0x40050102))
+#define USB0_CSRH0_R            (*((volatile uint8_t *)0x40050103))
+#define USB0_COUNT0_R           (*((volatile uint8_t *)0x40050108))
+#define USB0_TYPE0_R            (*((volatile uint8_t *)0x4005010A))
+#define USB0_NAKLMT_R           (*((volatile uint8_t *)0x4005010B))
+#define USB0_TXMAXP1_R          (*((volatile uint16_t *)0x40050110))
+#define USB0_TXCSRL1_R          (*((volatile uint8_t *)0x40050112))
+#define USB0_TXCSRH1_R          (*((volatile uint8_t *)0x40050113))
+#define USB0_RXMAXP1_R          (*((volatile uint16_t *)0x40050114))
+#define USB0_RXCSRL1_R          (*((volatile uint8_t *)0x40050116))
+#define USB0_RXCSRH1_R          (*((volatile uint8_t *)0x40050117))
+#define USB0_RXCOUNT1_R         (*((volatile uint16_t *)0x40050118))
+#define USB0_TXTYPE1_R          (*((volatile uint8_t *)0x4005011A))
+#define USB0_TXINTERVAL1_R      (*((volatile uint8_t *)0x4005011B))
+#define USB0_RXTYPE1_R          (*((volatile uint8_t *)0x4005011C))
+#define USB0_RXINTERVAL1_R      (*((volatile uint8_t *)0x4005011D))
+#define USB0_TXMAXP2_R          (*((volatile uint16_t *)0x40050120))
+#define USB0_TXCSRL2_R          (*((volatile uint8_t *)0x40050122))
+#define USB0_TXCSRH2_R          (*((volatile uint8_t *)0x40050123))
+#define USB0_RXMAXP2_R          (*((volatile uint16_t *)0x40050124))
+#define USB0_RXCSRL2_R          (*((volatile uint8_t *)0x40050126))
+#define USB0_RXCSRH2_R          (*((volatile uint8_t *)0x40050127))
+#define USB0_RXCOUNT2_R         (*((volatile uint16_t *)0x40050128))
+#define USB0_TXTYPE2_R          (*((volatile uint8_t *)0x4005012A))
+#define USB0_TXINTERVAL2_R      (*((volatile uint8_t *)0x4005012B))
+#define USB0_RXTYPE2_R          (*((volatile uint8_t *)0x4005012C))
+#define USB0_RXINTERVAL2_R      (*((volatile uint8_t *)0x4005012D))
+#define USB0_TXMAXP3_R          (*((volatile uint16_t *)0x40050130))
+#define USB0_TXCSRL3_R          (*((volatile uint8_t *)0x40050132))
+#define USB0_TXCSRH3_R          (*((volatile uint8_t *)0x40050133))
+#define USB0_RXMAXP3_R          (*((volatile uint16_t *)0x40050134))
+#define USB0_RXCSRL3_R          (*((volatile uint8_t *)0x40050136))
+#define USB0_RXCSRH3_R          (*((volatile uint8_t *)0x40050137))
+#define USB0_RXCOUNT3_R         (*((volatile uint16_t *)0x40050138))
+#define USB0_TXTYPE3_R          (*((volatile uint8_t *)0x4005013A))
+#define USB0_TXINTERVAL3_R      (*((volatile uint8_t *)0x4005013B))
+#define USB0_RXTYPE3_R          (*((volatile uint8_t *)0x4005013C))
+#define USB0_RXINTERVAL3_R      (*((volatile uint8_t *)0x4005013D))
+#define USB0_TXMAXP4_R          (*((volatile uint16_t *)0x40050140))
+#define USB0_TXCSRL4_R          (*((volatile uint8_t *)0x40050142))
+#define USB0_TXCSRH4_R          (*((volatile uint8_t *)0x40050143))
+#define USB0_RXMAXP4_R          (*((volatile uint16_t *)0x40050144))
+#define USB0_RXCSRL4_R          (*((volatile uint8_t *)0x40050146))
+#define USB0_RXCSRH4_R          (*((volatile uint8_t *)0x40050147))
+#define USB0_RXCOUNT4_R         (*((volatile uint16_t *)0x40050148))
+#define USB0_TXTYPE4_R          (*((volatile uint8_t *)0x4005014A))
+#define USB0_TXINTERVAL4_R      (*((volatile uint8_t *)0x4005014B))
+#define USB0_RXTYPE4_R          (*((volatile uint8_t *)0x4005014C))
+#define USB0_RXINTERVAL4_R      (*((volatile uint8_t *)0x4005014D))
+#define USB0_TXMAXP5_R          (*((volatile uint16_t *)0x40050150))
+#define USB0_TXCSRL5_R          (*((volatile uint8_t *)0x40050152))
+#define USB0_TXCSRH5_R          (*((volatile uint8_t *)0x40050153))
+#define USB0_RXMAXP5_R          (*((volatile uint16_t *)0x40050154))
+#define USB0_RXCSRL5_R          (*((volatile uint8_t *)0x40050156))
+#define USB0_RXCSRH5_R          (*((volatile uint8_t *)0x40050157))
+#define USB0_RXCOUNT5_R         (*((volatile uint16_t *)0x40050158))
+#define USB0_TXTYPE5_R          (*((volatile uint8_t *)0x4005015A))
+#define USB0_TXINTERVAL5_R      (*((volatile uint8_t *)0x4005015B))
+#define USB0_RXTYPE5_R          (*((volatile uint8_t *)0x4005015C))
+#define USB0_RXINTERVAL5_R      (*((volatile uint8_t *)0x4005015D))
+#define USB0_TXMAXP6_R          (*((volatile uint16_t *)0x40050160))
+#define USB0_TXCSRL6_R          (*((volatile uint8_t *)0x40050162))
+#define USB0_TXCSRH6_R          (*((volatile uint8_t *)0x40050163))
+#define USB0_RXMAXP6_R          (*((volatile uint16_t *)0x40050164))
+#define USB0_RXCSRL6_R          (*((volatile uint8_t *)0x40050166))
+#define USB0_RXCSRH6_R          (*((volatile uint8_t *)0x40050167))
+#define USB0_RXCOUNT6_R         (*((volatile uint16_t *)0x40050168))
+#define USB0_TXTYPE6_R          (*((volatile uint8_t *)0x4005016A))
+#define USB0_TXINTERVAL6_R      (*((volatile uint8_t *)0x4005016B))
+#define USB0_RXTYPE6_R          (*((volatile uint8_t *)0x4005016C))
+#define USB0_RXINTERVAL6_R      (*((volatile uint8_t *)0x4005016D))
+#define USB0_TXMAXP7_R          (*((volatile uint16_t *)0x40050170))
+#define USB0_TXCSRL7_R          (*((volatile uint8_t *)0x40050172))
+#define USB0_TXCSRH7_R          (*((volatile uint8_t *)0x40050173))
+#define USB0_RXMAXP7_R          (*((volatile uint16_t *)0x40050174))
+#define USB0_RXCSRL7_R          (*((volatile uint8_t *)0x40050176))
+#define USB0_RXCSRH7_R          (*((volatile uint8_t *)0x40050177))
+#define USB0_RXCOUNT7_R         (*((volatile uint16_t *)0x40050178))
+#define USB0_TXTYPE7_R          (*((volatile uint8_t *)0x4005017A))
+#define USB0_TXINTERVAL7_R      (*((volatile uint8_t *)0x4005017B))
+#define USB0_RXTYPE7_R          (*((volatile uint8_t *)0x4005017C))
+#define USB0_RXINTERVAL7_R      (*((volatile uint8_t *)0x4005017D))
+#define USB0_DMAINTR_R          (*((volatile uint8_t *)0x40050200))
+#define USB0_DMACTL0_R          (*((volatile uint16_t *)0x40050204))
+#define USB0_DMAADDR0_R         (*((volatile uint32_t *)0x40050208))
+#define USB0_DMACOUNT0_R        (*((volatile uint32_t *)0x4005020C))
+#define USB0_DMACTL1_R          (*((volatile uint16_t *)0x40050214))
+#define USB0_DMAADDR1_R         (*((volatile uint32_t *)0x40050218))
+#define USB0_DMACOUNT1_R        (*((volatile uint32_t *)0x4005021C))
+#define USB0_DMACTL2_R          (*((volatile uint16_t *)0x40050224))
+#define USB0_DMAADDR2_R         (*((volatile uint32_t *)0x40050228))
+#define USB0_DMACOUNT2_R        (*((volatile uint32_t *)0x4005022C))
+#define USB0_DMACTL3_R          (*((volatile uint16_t *)0x40050234))
+#define USB0_DMAADDR3_R         (*((volatile uint32_t *)0x40050238))
+#define USB0_DMACOUNT3_R        (*((volatile uint32_t *)0x4005023C))
+#define USB0_DMACTL4_R          (*((volatile uint16_t *)0x40050244))
+#define USB0_DMAADDR4_R         (*((volatile uint32_t *)0x40050248))
+#define USB0_DMACOUNT4_R        (*((volatile uint32_t *)0x4005024C))
+#define USB0_DMACTL5_R          (*((volatile uint16_t *)0x40050254))
+#define USB0_DMAADDR5_R         (*((volatile uint32_t *)0x40050258))
+#define USB0_DMACOUNT5_R        (*((volatile uint32_t *)0x4005025C))
+#define USB0_DMACTL6_R          (*((volatile uint16_t *)0x40050264))
+#define USB0_DMAADDR6_R         (*((volatile uint32_t *)0x40050268))
+#define USB0_DMACOUNT6_R        (*((volatile uint32_t *)0x4005026C))
+#define USB0_DMACTL7_R          (*((volatile uint16_t *)0x40050274))
+#define USB0_DMAADDR7_R         (*((volatile uint32_t *)0x40050278))
+#define USB0_DMACOUNT7_R        (*((volatile uint32_t *)0x4005027C))
+#define USB0_RQPKTCOUNT1_R      (*((volatile uint16_t *)0x40050304))
+#define USB0_RQPKTCOUNT2_R      (*((volatile uint16_t *)0x40050308))
+#define USB0_RQPKTCOUNT3_R      (*((volatile uint16_t *)0x4005030C))
+#define USB0_RQPKTCOUNT4_R      (*((volatile uint16_t *)0x40050310))
+#define USB0_RQPKTCOUNT5_R      (*((volatile uint16_t *)0x40050314))
+#define USB0_RQPKTCOUNT6_R      (*((volatile uint16_t *)0x40050318))
+#define USB0_RQPKTCOUNT7_R      (*((volatile uint16_t *)0x4005031C))
+#define USB0_RXDPKTBUFDIS_R     (*((volatile uint16_t *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R     (*((volatile uint16_t *)0x40050342))
+#define USB0_CTO_R              (*((volatile uint16_t *)0x40050344))
+#define USB0_HHSRTN_R           (*((volatile uint16_t *)0x40050346))
+#define USB0_HSBT_R             (*((volatile uint16_t *)0x40050348))
+#define USB0_LPMATTR_R          (*((volatile uint16_t *)0x40050360))
+#define USB0_LPMCNTRL_R         (*((volatile uint8_t *)0x40050362))
+#define USB0_LPMIM_R            (*((volatile uint8_t *)0x40050363))
+#define USB0_LPMRIS_R           (*((volatile uint8_t *)0x40050364))
+#define USB0_LPMFADDR_R         (*((volatile uint8_t *)0x40050365))
+#define USB0_EPC_R              (*((volatile uint32_t *)0x40050400))
+#define USB0_EPCRIS_R           (*((volatile uint32_t *)0x40050404))
+#define USB0_EPCIM_R            (*((volatile uint32_t *)0x40050408))
+#define USB0_EPCISC_R           (*((volatile uint32_t *)0x4005040C))
+#define USB0_DRRIS_R            (*((volatile uint32_t *)0x40050410))
+#define USB0_DRIM_R             (*((volatile uint32_t *)0x40050414))
+#define USB0_DRISC_R            (*((volatile uint32_t *)0x40050418))
+#define USB0_GPCS_R             (*((volatile uint32_t *)0x4005041C))
+#define USB0_VDC_R              (*((volatile uint32_t *)0x40050430))
+#define USB0_VDCRIS_R           (*((volatile uint32_t *)0x40050434))
+#define USB0_VDCIM_R            (*((volatile uint32_t *)0x40050438))
+#define USB0_VDCISC_R           (*((volatile uint32_t *)0x4005043C))
+#define USB0_PP_R               (*((volatile uint32_t *)0x40050FC0))
+#define USB0_PC_R               (*((volatile uint32_t *)0x40050FC4))
+#define USB0_CC_R               (*((volatile uint32_t *)0x40050FC8))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTA_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x40058000)
+#define GPIO_PORTA_AHB_DATA_R   (*((volatile uint32_t *)0x400583FC))
+#define GPIO_PORTA_AHB_DIR_R    (*((volatile uint32_t *)0x40058400))
+#define GPIO_PORTA_AHB_IS_R     (*((volatile uint32_t *)0x40058404))
+#define GPIO_PORTA_AHB_IBE_R    (*((volatile uint32_t *)0x40058408))
+#define GPIO_PORTA_AHB_IEV_R    (*((volatile uint32_t *)0x4005840C))
+#define GPIO_PORTA_AHB_IM_R     (*((volatile uint32_t *)0x40058410))
+#define GPIO_PORTA_AHB_RIS_R    (*((volatile uint32_t *)0x40058414))
+#define GPIO_PORTA_AHB_MIS_R    (*((volatile uint32_t *)0x40058418))
+#define GPIO_PORTA_AHB_ICR_R    (*((volatile uint32_t *)0x4005841C))
+#define GPIO_PORTA_AHB_AFSEL_R  (*((volatile uint32_t *)0x40058420))
+#define GPIO_PORTA_AHB_DR2R_R   (*((volatile uint32_t *)0x40058500))
+#define GPIO_PORTA_AHB_DR4R_R   (*((volatile uint32_t *)0x40058504))
+#define GPIO_PORTA_AHB_DR8R_R   (*((volatile uint32_t *)0x40058508))
+#define GPIO_PORTA_AHB_ODR_R    (*((volatile uint32_t *)0x4005850C))
+#define GPIO_PORTA_AHB_PUR_R    (*((volatile uint32_t *)0x40058510))
+#define GPIO_PORTA_AHB_PDR_R    (*((volatile uint32_t *)0x40058514))
+#define GPIO_PORTA_AHB_SLR_R    (*((volatile uint32_t *)0x40058518))
+#define GPIO_PORTA_AHB_DEN_R    (*((volatile uint32_t *)0x4005851C))
+#define GPIO_PORTA_AHB_LOCK_R   (*((volatile uint32_t *)0x40058520))
+#define GPIO_PORTA_AHB_CR_R     (*((volatile uint32_t *)0x40058524))
+#define GPIO_PORTA_AHB_AMSEL_R  (*((volatile uint32_t *)0x40058528))
+#define GPIO_PORTA_AHB_PCTL_R   (*((volatile uint32_t *)0x4005852C))
+#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530))
+#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534))
+#define GPIO_PORTA_AHB_SI_R     (*((volatile uint32_t *)0x40058538))
+#define GPIO_PORTA_AHB_DR12R_R  (*((volatile uint32_t *)0x4005853C))
+#define GPIO_PORTA_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x40058540))
+#define GPIO_PORTA_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x40058544))
+#define GPIO_PORTA_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x40058548))
+#define GPIO_PORTA_AHB_PP_R     (*((volatile uint32_t *)0x40058FC0))
+#define GPIO_PORTA_AHB_PC_R     (*((volatile uint32_t *)0x40058FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x40059000)
+#define GPIO_PORTB_AHB_DATA_R   (*((volatile uint32_t *)0x400593FC))
+#define GPIO_PORTB_AHB_DIR_R    (*((volatile uint32_t *)0x40059400))
+#define GPIO_PORTB_AHB_IS_R     (*((volatile uint32_t *)0x40059404))
+#define GPIO_PORTB_AHB_IBE_R    (*((volatile uint32_t *)0x40059408))
+#define GPIO_PORTB_AHB_IEV_R    (*((volatile uint32_t *)0x4005940C))
+#define GPIO_PORTB_AHB_IM_R     (*((volatile uint32_t *)0x40059410))
+#define GPIO_PORTB_AHB_RIS_R    (*((volatile uint32_t *)0x40059414))
+#define GPIO_PORTB_AHB_MIS_R    (*((volatile uint32_t *)0x40059418))
+#define GPIO_PORTB_AHB_ICR_R    (*((volatile uint32_t *)0x4005941C))
+#define GPIO_PORTB_AHB_AFSEL_R  (*((volatile uint32_t *)0x40059420))
+#define GPIO_PORTB_AHB_DR2R_R   (*((volatile uint32_t *)0x40059500))
+#define GPIO_PORTB_AHB_DR4R_R   (*((volatile uint32_t *)0x40059504))
+#define GPIO_PORTB_AHB_DR8R_R   (*((volatile uint32_t *)0x40059508))
+#define GPIO_PORTB_AHB_ODR_R    (*((volatile uint32_t *)0x4005950C))
+#define GPIO_PORTB_AHB_PUR_R    (*((volatile uint32_t *)0x40059510))
+#define GPIO_PORTB_AHB_PDR_R    (*((volatile uint32_t *)0x40059514))
+#define GPIO_PORTB_AHB_SLR_R    (*((volatile uint32_t *)0x40059518))
+#define GPIO_PORTB_AHB_DEN_R    (*((volatile uint32_t *)0x4005951C))
+#define GPIO_PORTB_AHB_LOCK_R   (*((volatile uint32_t *)0x40059520))
+#define GPIO_PORTB_AHB_CR_R     (*((volatile uint32_t *)0x40059524))
+#define GPIO_PORTB_AHB_AMSEL_R  (*((volatile uint32_t *)0x40059528))
+#define GPIO_PORTB_AHB_PCTL_R   (*((volatile uint32_t *)0x4005952C))
+#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530))
+#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534))
+#define GPIO_PORTB_AHB_SI_R     (*((volatile uint32_t *)0x40059538))
+#define GPIO_PORTB_AHB_DR12R_R  (*((volatile uint32_t *)0x4005953C))
+#define GPIO_PORTB_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x40059540))
+#define GPIO_PORTB_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x40059544))
+#define GPIO_PORTB_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x40059548))
+#define GPIO_PORTB_AHB_PP_R     (*((volatile uint32_t *)0x40059FC0))
+#define GPIO_PORTB_AHB_PC_R     (*((volatile uint32_t *)0x40059FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTC_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005A000)
+#define GPIO_PORTC_AHB_DATA_R   (*((volatile uint32_t *)0x4005A3FC))
+#define GPIO_PORTC_AHB_DIR_R    (*((volatile uint32_t *)0x4005A400))
+#define GPIO_PORTC_AHB_IS_R     (*((volatile uint32_t *)0x4005A404))
+#define GPIO_PORTC_AHB_IBE_R    (*((volatile uint32_t *)0x4005A408))
+#define GPIO_PORTC_AHB_IEV_R    (*((volatile uint32_t *)0x4005A40C))
+#define GPIO_PORTC_AHB_IM_R     (*((volatile uint32_t *)0x4005A410))
+#define GPIO_PORTC_AHB_RIS_R    (*((volatile uint32_t *)0x4005A414))
+#define GPIO_PORTC_AHB_MIS_R    (*((volatile uint32_t *)0x4005A418))
+#define GPIO_PORTC_AHB_ICR_R    (*((volatile uint32_t *)0x4005A41C))
+#define GPIO_PORTC_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005A420))
+#define GPIO_PORTC_AHB_DR2R_R   (*((volatile uint32_t *)0x4005A500))
+#define GPIO_PORTC_AHB_DR4R_R   (*((volatile uint32_t *)0x4005A504))
+#define GPIO_PORTC_AHB_DR8R_R   (*((volatile uint32_t *)0x4005A508))
+#define GPIO_PORTC_AHB_ODR_R    (*((volatile uint32_t *)0x4005A50C))
+#define GPIO_PORTC_AHB_PUR_R    (*((volatile uint32_t *)0x4005A510))
+#define GPIO_PORTC_AHB_PDR_R    (*((volatile uint32_t *)0x4005A514))
+#define GPIO_PORTC_AHB_SLR_R    (*((volatile uint32_t *)0x4005A518))
+#define GPIO_PORTC_AHB_DEN_R    (*((volatile uint32_t *)0x4005A51C))
+#define GPIO_PORTC_AHB_LOCK_R   (*((volatile uint32_t *)0x4005A520))
+#define GPIO_PORTC_AHB_CR_R     (*((volatile uint32_t *)0x4005A524))
+#define GPIO_PORTC_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005A528))
+#define GPIO_PORTC_AHB_PCTL_R   (*((volatile uint32_t *)0x4005A52C))
+#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530))
+#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534))
+#define GPIO_PORTC_AHB_SI_R     (*((volatile uint32_t *)0x4005A538))
+#define GPIO_PORTC_AHB_DR12R_R  (*((volatile uint32_t *)0x4005A53C))
+#define GPIO_PORTC_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x4005A540))
+#define GPIO_PORTC_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x4005A544))
+#define GPIO_PORTC_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x4005A548))
+#define GPIO_PORTC_AHB_PP_R     (*((volatile uint32_t *)0x4005AFC0))
+#define GPIO_PORTC_AHB_PC_R     (*((volatile uint32_t *)0x4005AFC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTD_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005B000)
+#define GPIO_PORTD_AHB_DATA_R   (*((volatile uint32_t *)0x4005B3FC))
+#define GPIO_PORTD_AHB_DIR_R    (*((volatile uint32_t *)0x4005B400))
+#define GPIO_PORTD_AHB_IS_R     (*((volatile uint32_t *)0x4005B404))
+#define GPIO_PORTD_AHB_IBE_R    (*((volatile uint32_t *)0x4005B408))
+#define GPIO_PORTD_AHB_IEV_R    (*((volatile uint32_t *)0x4005B40C))
+#define GPIO_PORTD_AHB_IM_R     (*((volatile uint32_t *)0x4005B410))
+#define GPIO_PORTD_AHB_RIS_R    (*((volatile uint32_t *)0x4005B414))
+#define GPIO_PORTD_AHB_MIS_R    (*((volatile uint32_t *)0x4005B418))
+#define GPIO_PORTD_AHB_ICR_R    (*((volatile uint32_t *)0x4005B41C))
+#define GPIO_PORTD_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005B420))
+#define GPIO_PORTD_AHB_DR2R_R   (*((volatile uint32_t *)0x4005B500))
+#define GPIO_PORTD_AHB_DR4R_R   (*((volatile uint32_t *)0x4005B504))
+#define GPIO_PORTD_AHB_DR8R_R   (*((volatile uint32_t *)0x4005B508))
+#define GPIO_PORTD_AHB_ODR_R    (*((volatile uint32_t *)0x4005B50C))
+#define GPIO_PORTD_AHB_PUR_R    (*((volatile uint32_t *)0x4005B510))
+#define GPIO_PORTD_AHB_PDR_R    (*((volatile uint32_t *)0x4005B514))
+#define GPIO_PORTD_AHB_SLR_R    (*((volatile uint32_t *)0x4005B518))
+#define GPIO_PORTD_AHB_DEN_R    (*((volatile uint32_t *)0x4005B51C))
+#define GPIO_PORTD_AHB_LOCK_R   (*((volatile uint32_t *)0x4005B520))
+#define GPIO_PORTD_AHB_CR_R     (*((volatile uint32_t *)0x4005B524))
+#define GPIO_PORTD_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005B528))
+#define GPIO_PORTD_AHB_PCTL_R   (*((volatile uint32_t *)0x4005B52C))
+#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530))
+#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534))
+#define GPIO_PORTD_AHB_SI_R     (*((volatile uint32_t *)0x4005B538))
+#define GPIO_PORTD_AHB_DR12R_R  (*((volatile uint32_t *)0x4005B53C))
+#define GPIO_PORTD_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x4005B540))
+#define GPIO_PORTD_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x4005B544))
+#define GPIO_PORTD_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x4005B548))
+#define GPIO_PORTD_AHB_PP_R     (*((volatile uint32_t *)0x4005BFC0))
+#define GPIO_PORTD_AHB_PC_R     (*((volatile uint32_t *)0x4005BFC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTE_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005C000)
+#define GPIO_PORTE_AHB_DATA_R   (*((volatile uint32_t *)0x4005C3FC))
+#define GPIO_PORTE_AHB_DIR_R    (*((volatile uint32_t *)0x4005C400))
+#define GPIO_PORTE_AHB_IS_R     (*((volatile uint32_t *)0x4005C404))
+#define GPIO_PORTE_AHB_IBE_R    (*((volatile uint32_t *)0x4005C408))
+#define GPIO_PORTE_AHB_IEV_R    (*((volatile uint32_t *)0x4005C40C))
+#define GPIO_PORTE_AHB_IM_R     (*((volatile uint32_t *)0x4005C410))
+#define GPIO_PORTE_AHB_RIS_R    (*((volatile uint32_t *)0x4005C414))
+#define GPIO_PORTE_AHB_MIS_R    (*((volatile uint32_t *)0x4005C418))
+#define GPIO_PORTE_AHB_ICR_R    (*((volatile uint32_t *)0x4005C41C))
+#define GPIO_PORTE_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005C420))
+#define GPIO_PORTE_AHB_DR2R_R   (*((volatile uint32_t *)0x4005C500))
+#define GPIO_PORTE_AHB_DR4R_R   (*((volatile uint32_t *)0x4005C504))
+#define GPIO_PORTE_AHB_DR8R_R   (*((volatile uint32_t *)0x4005C508))
+#define GPIO_PORTE_AHB_ODR_R    (*((volatile uint32_t *)0x4005C50C))
+#define GPIO_PORTE_AHB_PUR_R    (*((volatile uint32_t *)0x4005C510))
+#define GPIO_PORTE_AHB_PDR_R    (*((volatile uint32_t *)0x4005C514))
+#define GPIO_PORTE_AHB_SLR_R    (*((volatile uint32_t *)0x4005C518))
+#define GPIO_PORTE_AHB_DEN_R    (*((volatile uint32_t *)0x4005C51C))
+#define GPIO_PORTE_AHB_LOCK_R   (*((volatile uint32_t *)0x4005C520))
+#define GPIO_PORTE_AHB_CR_R     (*((volatile uint32_t *)0x4005C524))
+#define GPIO_PORTE_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005C528))
+#define GPIO_PORTE_AHB_PCTL_R   (*((volatile uint32_t *)0x4005C52C))
+#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530))
+#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534))
+#define GPIO_PORTE_AHB_SI_R     (*((volatile uint32_t *)0x4005C538))
+#define GPIO_PORTE_AHB_DR12R_R  (*((volatile uint32_t *)0x4005C53C))
+#define GPIO_PORTE_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x4005C540))
+#define GPIO_PORTE_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x4005C544))
+#define GPIO_PORTE_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x4005C548))
+#define GPIO_PORTE_AHB_PP_R     (*((volatile uint32_t *)0x4005CFC0))
+#define GPIO_PORTE_AHB_PC_R     (*((volatile uint32_t *)0x4005CFC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTF_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005D000)
+#define GPIO_PORTF_AHB_DATA_R   (*((volatile uint32_t *)0x4005D3FC))
+#define GPIO_PORTF_AHB_DIR_R    (*((volatile uint32_t *)0x4005D400))
+#define GPIO_PORTF_AHB_IS_R     (*((volatile uint32_t *)0x4005D404))
+#define GPIO_PORTF_AHB_IBE_R    (*((volatile uint32_t *)0x4005D408))
+#define GPIO_PORTF_AHB_IEV_R    (*((volatile uint32_t *)0x4005D40C))
+#define GPIO_PORTF_AHB_IM_R     (*((volatile uint32_t *)0x4005D410))
+#define GPIO_PORTF_AHB_RIS_R    (*((volatile uint32_t *)0x4005D414))
+#define GPIO_PORTF_AHB_MIS_R    (*((volatile uint32_t *)0x4005D418))
+#define GPIO_PORTF_AHB_ICR_R    (*((volatile uint32_t *)0x4005D41C))
+#define GPIO_PORTF_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005D420))
+#define GPIO_PORTF_AHB_DR2R_R   (*((volatile uint32_t *)0x4005D500))
+#define GPIO_PORTF_AHB_DR4R_R   (*((volatile uint32_t *)0x4005D504))
+#define GPIO_PORTF_AHB_DR8R_R   (*((volatile uint32_t *)0x4005D508))
+#define GPIO_PORTF_AHB_ODR_R    (*((volatile uint32_t *)0x4005D50C))
+#define GPIO_PORTF_AHB_PUR_R    (*((volatile uint32_t *)0x4005D510))
+#define GPIO_PORTF_AHB_PDR_R    (*((volatile uint32_t *)0x4005D514))
+#define GPIO_PORTF_AHB_SLR_R    (*((volatile uint32_t *)0x4005D518))
+#define GPIO_PORTF_AHB_DEN_R    (*((volatile uint32_t *)0x4005D51C))
+#define GPIO_PORTF_AHB_LOCK_R   (*((volatile uint32_t *)0x4005D520))
+#define GPIO_PORTF_AHB_CR_R     (*((volatile uint32_t *)0x4005D524))
+#define GPIO_PORTF_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005D528))
+#define GPIO_PORTF_AHB_PCTL_R   (*((volatile uint32_t *)0x4005D52C))
+#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530))
+#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534))
+#define GPIO_PORTF_AHB_SI_R     (*((volatile uint32_t *)0x4005D538))
+#define GPIO_PORTF_AHB_DR12R_R  (*((volatile uint32_t *)0x4005D53C))
+#define GPIO_PORTF_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x4005D540))
+#define GPIO_PORTF_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x4005D544))
+#define GPIO_PORTF_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x4005D548))
+#define GPIO_PORTF_AHB_PP_R     (*((volatile uint32_t *)0x4005DFC0))
+#define GPIO_PORTF_AHB_PC_R     (*((volatile uint32_t *)0x4005DFC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTG_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005E000)
+#define GPIO_PORTG_AHB_DATA_R   (*((volatile uint32_t *)0x4005E3FC))
+#define GPIO_PORTG_AHB_DIR_R    (*((volatile uint32_t *)0x4005E400))
+#define GPIO_PORTG_AHB_IS_R     (*((volatile uint32_t *)0x4005E404))
+#define GPIO_PORTG_AHB_IBE_R    (*((volatile uint32_t *)0x4005E408))
+#define GPIO_PORTG_AHB_IEV_R    (*((volatile uint32_t *)0x4005E40C))
+#define GPIO_PORTG_AHB_IM_R     (*((volatile uint32_t *)0x4005E410))
+#define GPIO_PORTG_AHB_RIS_R    (*((volatile uint32_t *)0x4005E414))
+#define GPIO_PORTG_AHB_MIS_R    (*((volatile uint32_t *)0x4005E418))
+#define GPIO_PORTG_AHB_ICR_R    (*((volatile uint32_t *)0x4005E41C))
+#define GPIO_PORTG_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005E420))
+#define GPIO_PORTG_AHB_DR2R_R   (*((volatile uint32_t *)0x4005E500))
+#define GPIO_PORTG_AHB_DR4R_R   (*((volatile uint32_t *)0x4005E504))
+#define GPIO_PORTG_AHB_DR8R_R   (*((volatile uint32_t *)0x4005E508))
+#define GPIO_PORTG_AHB_ODR_R    (*((volatile uint32_t *)0x4005E50C))
+#define GPIO_PORTG_AHB_PUR_R    (*((volatile uint32_t *)0x4005E510))
+#define GPIO_PORTG_AHB_PDR_R    (*((volatile uint32_t *)0x4005E514))
+#define GPIO_PORTG_AHB_SLR_R    (*((volatile uint32_t *)0x4005E518))
+#define GPIO_PORTG_AHB_DEN_R    (*((volatile uint32_t *)0x4005E51C))
+#define GPIO_PORTG_AHB_LOCK_R   (*((volatile uint32_t *)0x4005E520))
+#define GPIO_PORTG_AHB_CR_R     (*((volatile uint32_t *)0x4005E524))
+#define GPIO_PORTG_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005E528))
+#define GPIO_PORTG_AHB_PCTL_R   (*((volatile uint32_t *)0x4005E52C))
+#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530))
+#define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534))
+#define GPIO_PORTG_AHB_SI_R     (*((volatile uint32_t *)0x4005E538))
+#define GPIO_PORTG_AHB_DR12R_R  (*((volatile uint32_t *)0x4005E53C))
+#define GPIO_PORTG_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x4005E540))
+#define GPIO_PORTG_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x4005E544))
+#define GPIO_PORTG_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x4005E548))
+#define GPIO_PORTG_AHB_PP_R     (*((volatile uint32_t *)0x4005EFC0))
+#define GPIO_PORTG_AHB_PC_R     (*((volatile uint32_t *)0x4005EFC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTH AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTH_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005F000)
+#define GPIO_PORTH_AHB_DATA_R   (*((volatile uint32_t *)0x4005F3FC))
+#define GPIO_PORTH_AHB_DIR_R    (*((volatile uint32_t *)0x4005F400))
+#define GPIO_PORTH_AHB_IS_R     (*((volatile uint32_t *)0x4005F404))
+#define GPIO_PORTH_AHB_IBE_R    (*((volatile uint32_t *)0x4005F408))
+#define GPIO_PORTH_AHB_IEV_R    (*((volatile uint32_t *)0x4005F40C))
+#define GPIO_PORTH_AHB_IM_R     (*((volatile uint32_t *)0x4005F410))
+#define GPIO_PORTH_AHB_RIS_R    (*((volatile uint32_t *)0x4005F414))
+#define GPIO_PORTH_AHB_MIS_R    (*((volatile uint32_t *)0x4005F418))
+#define GPIO_PORTH_AHB_ICR_R    (*((volatile uint32_t *)0x4005F41C))
+#define GPIO_PORTH_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005F420))
+#define GPIO_PORTH_AHB_DR2R_R   (*((volatile uint32_t *)0x4005F500))
+#define GPIO_PORTH_AHB_DR4R_R   (*((volatile uint32_t *)0x4005F504))
+#define GPIO_PORTH_AHB_DR8R_R   (*((volatile uint32_t *)0x4005F508))
+#define GPIO_PORTH_AHB_ODR_R    (*((volatile uint32_t *)0x4005F50C))
+#define GPIO_PORTH_AHB_PUR_R    (*((volatile uint32_t *)0x4005F510))
+#define GPIO_PORTH_AHB_PDR_R    (*((volatile uint32_t *)0x4005F514))
+#define GPIO_PORTH_AHB_SLR_R    (*((volatile uint32_t *)0x4005F518))
+#define GPIO_PORTH_AHB_DEN_R    (*((volatile uint32_t *)0x4005F51C))
+#define GPIO_PORTH_AHB_LOCK_R   (*((volatile uint32_t *)0x4005F520))
+#define GPIO_PORTH_AHB_CR_R     (*((volatile uint32_t *)0x4005F524))
+#define GPIO_PORTH_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005F528))
+#define GPIO_PORTH_AHB_PCTL_R   (*((volatile uint32_t *)0x4005F52C))
+#define GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530))
+#define GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534))
+#define GPIO_PORTH_AHB_SI_R     (*((volatile uint32_t *)0x4005F538))
+#define GPIO_PORTH_AHB_DR12R_R  (*((volatile uint32_t *)0x4005F53C))
+#define GPIO_PORTH_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x4005F540))
+#define GPIO_PORTH_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x4005F544))
+#define GPIO_PORTH_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x4005F548))
+#define GPIO_PORTH_AHB_PP_R     (*((volatile uint32_t *)0x4005FFC0))
+#define GPIO_PORTH_AHB_PC_R     (*((volatile uint32_t *)0x4005FFC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTJ AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x40060000)
+#define GPIO_PORTJ_AHB_DATA_R   (*((volatile uint32_t *)0x400603FC))
+#define GPIO_PORTJ_AHB_DIR_R    (*((volatile uint32_t *)0x40060400))
+#define GPIO_PORTJ_AHB_IS_R     (*((volatile uint32_t *)0x40060404))
+#define GPIO_PORTJ_AHB_IBE_R    (*((volatile uint32_t *)0x40060408))
+#define GPIO_PORTJ_AHB_IEV_R    (*((volatile uint32_t *)0x4006040C))
+#define GPIO_PORTJ_AHB_IM_R     (*((volatile uint32_t *)0x40060410))
+#define GPIO_PORTJ_AHB_RIS_R    (*((volatile uint32_t *)0x40060414))
+#define GPIO_PORTJ_AHB_MIS_R    (*((volatile uint32_t *)0x40060418))
+#define GPIO_PORTJ_AHB_ICR_R    (*((volatile uint32_t *)0x4006041C))
+#define GPIO_PORTJ_AHB_AFSEL_R  (*((volatile uint32_t *)0x40060420))
+#define GPIO_PORTJ_AHB_DR2R_R   (*((volatile uint32_t *)0x40060500))
+#define GPIO_PORTJ_AHB_DR4R_R   (*((volatile uint32_t *)0x40060504))
+#define GPIO_PORTJ_AHB_DR8R_R   (*((volatile uint32_t *)0x40060508))
+#define GPIO_PORTJ_AHB_ODR_R    (*((volatile uint32_t *)0x4006050C))
+#define GPIO_PORTJ_AHB_PUR_R    (*((volatile uint32_t *)0x40060510))
+#define GPIO_PORTJ_AHB_PDR_R    (*((volatile uint32_t *)0x40060514))
+#define GPIO_PORTJ_AHB_SLR_R    (*((volatile uint32_t *)0x40060518))
+#define GPIO_PORTJ_AHB_DEN_R    (*((volatile uint32_t *)0x4006051C))
+#define GPIO_PORTJ_AHB_LOCK_R   (*((volatile uint32_t *)0x40060520))
+#define GPIO_PORTJ_AHB_CR_R     (*((volatile uint32_t *)0x40060524))
+#define GPIO_PORTJ_AHB_AMSEL_R  (*((volatile uint32_t *)0x40060528))
+#define GPIO_PORTJ_AHB_PCTL_R   (*((volatile uint32_t *)0x4006052C))
+#define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530))
+#define GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534))
+#define GPIO_PORTJ_AHB_SI_R     (*((volatile uint32_t *)0x40060538))
+#define GPIO_PORTJ_AHB_DR12R_R  (*((volatile uint32_t *)0x4006053C))
+#define GPIO_PORTJ_AHB_WAKEPEN_R                                              \
+                                (*((volatile uint32_t *)0x40060540))
+#define GPIO_PORTJ_AHB_WAKELVL_R                                              \
+                                (*((volatile uint32_t *)0x40060544))
+#define GPIO_PORTJ_AHB_WAKESTAT_R                                             \
+                                (*((volatile uint32_t *)0x40060548))
+#define GPIO_PORTJ_AHB_PP_R     (*((volatile uint32_t *)0x40060FC0))
+#define GPIO_PORTJ_AHB_PC_R     (*((volatile uint32_t *)0x40060FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTK)
+//
+//*****************************************************************************
+#define GPIO_PORTK_DATA_BITS_R  ((volatile uint32_t *)0x40061000)
+#define GPIO_PORTK_DATA_R       (*((volatile uint32_t *)0x400613FC))
+#define GPIO_PORTK_DIR_R        (*((volatile uint32_t *)0x40061400))
+#define GPIO_PORTK_IS_R         (*((volatile uint32_t *)0x40061404))
+#define GPIO_PORTK_IBE_R        (*((volatile uint32_t *)0x40061408))
+#define GPIO_PORTK_IEV_R        (*((volatile uint32_t *)0x4006140C))
+#define GPIO_PORTK_IM_R         (*((volatile uint32_t *)0x40061410))
+#define GPIO_PORTK_RIS_R        (*((volatile uint32_t *)0x40061414))
+#define GPIO_PORTK_MIS_R        (*((volatile uint32_t *)0x40061418))
+#define GPIO_PORTK_ICR_R        (*((volatile uint32_t *)0x4006141C))
+#define GPIO_PORTK_AFSEL_R      (*((volatile uint32_t *)0x40061420))
+#define GPIO_PORTK_DR2R_R       (*((volatile uint32_t *)0x40061500))
+#define GPIO_PORTK_DR4R_R       (*((volatile uint32_t *)0x40061504))
+#define GPIO_PORTK_DR8R_R       (*((volatile uint32_t *)0x40061508))
+#define GPIO_PORTK_ODR_R        (*((volatile uint32_t *)0x4006150C))
+#define GPIO_PORTK_PUR_R        (*((volatile uint32_t *)0x40061510))
+#define GPIO_PORTK_PDR_R        (*((volatile uint32_t *)0x40061514))
+#define GPIO_PORTK_SLR_R        (*((volatile uint32_t *)0x40061518))
+#define GPIO_PORTK_DEN_R        (*((volatile uint32_t *)0x4006151C))
+#define GPIO_PORTK_LOCK_R       (*((volatile uint32_t *)0x40061520))
+#define GPIO_PORTK_CR_R         (*((volatile uint32_t *)0x40061524))
+#define GPIO_PORTK_AMSEL_R      (*((volatile uint32_t *)0x40061528))
+#define GPIO_PORTK_PCTL_R       (*((volatile uint32_t *)0x4006152C))
+#define GPIO_PORTK_ADCCTL_R     (*((volatile uint32_t *)0x40061530))
+#define GPIO_PORTK_DMACTL_R     (*((volatile uint32_t *)0x40061534))
+#define GPIO_PORTK_SI_R         (*((volatile uint32_t *)0x40061538))
+#define GPIO_PORTK_DR12R_R      (*((volatile uint32_t *)0x4006153C))
+#define GPIO_PORTK_WAKEPEN_R    (*((volatile uint32_t *)0x40061540))
+#define GPIO_PORTK_WAKELVL_R    (*((volatile uint32_t *)0x40061544))
+#define GPIO_PORTK_WAKESTAT_R   (*((volatile uint32_t *)0x40061548))
+#define GPIO_PORTK_PP_R         (*((volatile uint32_t *)0x40061FC0))
+#define GPIO_PORTK_PC_R         (*((volatile uint32_t *)0x40061FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTL)
+//
+//*****************************************************************************
+#define GPIO_PORTL_DATA_BITS_R  ((volatile uint32_t *)0x40062000)
+#define GPIO_PORTL_DATA_R       (*((volatile uint32_t *)0x400623FC))
+#define GPIO_PORTL_DIR_R        (*((volatile uint32_t *)0x40062400))
+#define GPIO_PORTL_IS_R         (*((volatile uint32_t *)0x40062404))
+#define GPIO_PORTL_IBE_R        (*((volatile uint32_t *)0x40062408))
+#define GPIO_PORTL_IEV_R        (*((volatile uint32_t *)0x4006240C))
+#define GPIO_PORTL_IM_R         (*((volatile uint32_t *)0x40062410))
+#define GPIO_PORTL_RIS_R        (*((volatile uint32_t *)0x40062414))
+#define GPIO_PORTL_MIS_R        (*((volatile uint32_t *)0x40062418))
+#define GPIO_PORTL_ICR_R        (*((volatile uint32_t *)0x4006241C))
+#define GPIO_PORTL_AFSEL_R      (*((volatile uint32_t *)0x40062420))
+#define GPIO_PORTL_DR2R_R       (*((volatile uint32_t *)0x40062500))
+#define GPIO_PORTL_DR4R_R       (*((volatile uint32_t *)0x40062504))
+#define GPIO_PORTL_DR8R_R       (*((volatile uint32_t *)0x40062508))
+#define GPIO_PORTL_ODR_R        (*((volatile uint32_t *)0x4006250C))
+#define GPIO_PORTL_PUR_R        (*((volatile uint32_t *)0x40062510))
+#define GPIO_PORTL_PDR_R        (*((volatile uint32_t *)0x40062514))
+#define GPIO_PORTL_SLR_R        (*((volatile uint32_t *)0x40062518))
+#define GPIO_PORTL_DEN_R        (*((volatile uint32_t *)0x4006251C))
+#define GPIO_PORTL_LOCK_R       (*((volatile uint32_t *)0x40062520))
+#define GPIO_PORTL_CR_R         (*((volatile uint32_t *)0x40062524))
+#define GPIO_PORTL_AMSEL_R      (*((volatile uint32_t *)0x40062528))
+#define GPIO_PORTL_PCTL_R       (*((volatile uint32_t *)0x4006252C))
+#define GPIO_PORTL_ADCCTL_R     (*((volatile uint32_t *)0x40062530))
+#define GPIO_PORTL_DMACTL_R     (*((volatile uint32_t *)0x40062534))
+#define GPIO_PORTL_SI_R         (*((volatile uint32_t *)0x40062538))
+#define GPIO_PORTL_DR12R_R      (*((volatile uint32_t *)0x4006253C))
+#define GPIO_PORTL_WAKEPEN_R    (*((volatile uint32_t *)0x40062540))
+#define GPIO_PORTL_WAKELVL_R    (*((volatile uint32_t *)0x40062544))
+#define GPIO_PORTL_WAKESTAT_R   (*((volatile uint32_t *)0x40062548))
+#define GPIO_PORTL_PP_R         (*((volatile uint32_t *)0x40062FC0))
+#define GPIO_PORTL_PC_R         (*((volatile uint32_t *)0x40062FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTM)
+//
+//*****************************************************************************
+#define GPIO_PORTM_DATA_BITS_R  ((volatile uint32_t *)0x40063000)
+#define GPIO_PORTM_DATA_R       (*((volatile uint32_t *)0x400633FC))
+#define GPIO_PORTM_DIR_R        (*((volatile uint32_t *)0x40063400))
+#define GPIO_PORTM_IS_R         (*((volatile uint32_t *)0x40063404))
+#define GPIO_PORTM_IBE_R        (*((volatile uint32_t *)0x40063408))
+#define GPIO_PORTM_IEV_R        (*((volatile uint32_t *)0x4006340C))
+#define GPIO_PORTM_IM_R         (*((volatile uint32_t *)0x40063410))
+#define GPIO_PORTM_RIS_R        (*((volatile uint32_t *)0x40063414))
+#define GPIO_PORTM_MIS_R        (*((volatile uint32_t *)0x40063418))
+#define GPIO_PORTM_ICR_R        (*((volatile uint32_t *)0x4006341C))
+#define GPIO_PORTM_AFSEL_R      (*((volatile uint32_t *)0x40063420))
+#define GPIO_PORTM_DR2R_R       (*((volatile uint32_t *)0x40063500))
+#define GPIO_PORTM_DR4R_R       (*((volatile uint32_t *)0x40063504))
+#define GPIO_PORTM_DR8R_R       (*((volatile uint32_t *)0x40063508))
+#define GPIO_PORTM_ODR_R        (*((volatile uint32_t *)0x4006350C))
+#define GPIO_PORTM_PUR_R        (*((volatile uint32_t *)0x40063510))
+#define GPIO_PORTM_PDR_R        (*((volatile uint32_t *)0x40063514))
+#define GPIO_PORTM_SLR_R        (*((volatile uint32_t *)0x40063518))
+#define GPIO_PORTM_DEN_R        (*((volatile uint32_t *)0x4006351C))
+#define GPIO_PORTM_LOCK_R       (*((volatile uint32_t *)0x40063520))
+#define GPIO_PORTM_CR_R         (*((volatile uint32_t *)0x40063524))
+#define GPIO_PORTM_AMSEL_R      (*((volatile uint32_t *)0x40063528))
+#define GPIO_PORTM_PCTL_R       (*((volatile uint32_t *)0x4006352C))
+#define GPIO_PORTM_ADCCTL_R     (*((volatile uint32_t *)0x40063530))
+#define GPIO_PORTM_DMACTL_R     (*((volatile uint32_t *)0x40063534))
+#define GPIO_PORTM_SI_R         (*((volatile uint32_t *)0x40063538))
+#define GPIO_PORTM_DR12R_R      (*((volatile uint32_t *)0x4006353C))
+#define GPIO_PORTM_WAKEPEN_R    (*((volatile uint32_t *)0x40063540))
+#define GPIO_PORTM_WAKELVL_R    (*((volatile uint32_t *)0x40063544))
+#define GPIO_PORTM_WAKESTAT_R   (*((volatile uint32_t *)0x40063548))
+#define GPIO_PORTM_PP_R         (*((volatile uint32_t *)0x40063FC0))
+#define GPIO_PORTM_PC_R         (*((volatile uint32_t *)0x40063FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTN)
+//
+//*****************************************************************************
+#define GPIO_PORTN_DATA_BITS_R  ((volatile uint32_t *)0x40064000)
+#define GPIO_PORTN_DATA_R       (*((volatile uint32_t *)0x400643FC))
+#define GPIO_PORTN_DIR_R        (*((volatile uint32_t *)0x40064400))
+#define GPIO_PORTN_IS_R         (*((volatile uint32_t *)0x40064404))
+#define GPIO_PORTN_IBE_R        (*((volatile uint32_t *)0x40064408))
+#define GPIO_PORTN_IEV_R        (*((volatile uint32_t *)0x4006440C))
+#define GPIO_PORTN_IM_R         (*((volatile uint32_t *)0x40064410))
+#define GPIO_PORTN_RIS_R        (*((volatile uint32_t *)0x40064414))
+#define GPIO_PORTN_MIS_R        (*((volatile uint32_t *)0x40064418))
+#define GPIO_PORTN_ICR_R        (*((volatile uint32_t *)0x4006441C))
+#define GPIO_PORTN_AFSEL_R      (*((volatile uint32_t *)0x40064420))
+#define GPIO_PORTN_DR2R_R       (*((volatile uint32_t *)0x40064500))
+#define GPIO_PORTN_DR4R_R       (*((volatile uint32_t *)0x40064504))
+#define GPIO_PORTN_DR8R_R       (*((volatile uint32_t *)0x40064508))
+#define GPIO_PORTN_ODR_R        (*((volatile uint32_t *)0x4006450C))
+#define GPIO_PORTN_PUR_R        (*((volatile uint32_t *)0x40064510))
+#define GPIO_PORTN_PDR_R        (*((volatile uint32_t *)0x40064514))
+#define GPIO_PORTN_SLR_R        (*((volatile uint32_t *)0x40064518))
+#define GPIO_PORTN_DEN_R        (*((volatile uint32_t *)0x4006451C))
+#define GPIO_PORTN_LOCK_R       (*((volatile uint32_t *)0x40064520))
+#define GPIO_PORTN_CR_R         (*((volatile uint32_t *)0x40064524))
+#define GPIO_PORTN_AMSEL_R      (*((volatile uint32_t *)0x40064528))
+#define GPIO_PORTN_PCTL_R       (*((volatile uint32_t *)0x4006452C))
+#define GPIO_PORTN_ADCCTL_R     (*((volatile uint32_t *)0x40064530))
+#define GPIO_PORTN_DMACTL_R     (*((volatile uint32_t *)0x40064534))
+#define GPIO_PORTN_SI_R         (*((volatile uint32_t *)0x40064538))
+#define GPIO_PORTN_DR12R_R      (*((volatile uint32_t *)0x4006453C))
+#define GPIO_PORTN_WAKEPEN_R    (*((volatile uint32_t *)0x40064540))
+#define GPIO_PORTN_WAKELVL_R    (*((volatile uint32_t *)0x40064544))
+#define GPIO_PORTN_WAKESTAT_R   (*((volatile uint32_t *)0x40064548))
+#define GPIO_PORTN_PP_R         (*((volatile uint32_t *)0x40064FC0))
+#define GPIO_PORTN_PC_R         (*((volatile uint32_t *)0x40064FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTP)
+//
+//*****************************************************************************
+#define GPIO_PORTP_DATA_BITS_R  ((volatile uint32_t *)0x40065000)
+#define GPIO_PORTP_DATA_R       (*((volatile uint32_t *)0x400653FC))
+#define GPIO_PORTP_DIR_R        (*((volatile uint32_t *)0x40065400))
+#define GPIO_PORTP_IS_R         (*((volatile uint32_t *)0x40065404))
+#define GPIO_PORTP_IBE_R        (*((volatile uint32_t *)0x40065408))
+#define GPIO_PORTP_IEV_R        (*((volatile uint32_t *)0x4006540C))
+#define GPIO_PORTP_IM_R         (*((volatile uint32_t *)0x40065410))
+#define GPIO_PORTP_RIS_R        (*((volatile uint32_t *)0x40065414))
+#define GPIO_PORTP_MIS_R        (*((volatile uint32_t *)0x40065418))
+#define GPIO_PORTP_ICR_R        (*((volatile uint32_t *)0x4006541C))
+#define GPIO_PORTP_AFSEL_R      (*((volatile uint32_t *)0x40065420))
+#define GPIO_PORTP_DR2R_R       (*((volatile uint32_t *)0x40065500))
+#define GPIO_PORTP_DR4R_R       (*((volatile uint32_t *)0x40065504))
+#define GPIO_PORTP_DR8R_R       (*((volatile uint32_t *)0x40065508))
+#define GPIO_PORTP_ODR_R        (*((volatile uint32_t *)0x4006550C))
+#define GPIO_PORTP_PUR_R        (*((volatile uint32_t *)0x40065510))
+#define GPIO_PORTP_PDR_R        (*((volatile uint32_t *)0x40065514))
+#define GPIO_PORTP_SLR_R        (*((volatile uint32_t *)0x40065518))
+#define GPIO_PORTP_DEN_R        (*((volatile uint32_t *)0x4006551C))
+#define GPIO_PORTP_LOCK_R       (*((volatile uint32_t *)0x40065520))
+#define GPIO_PORTP_CR_R         (*((volatile uint32_t *)0x40065524))
+#define GPIO_PORTP_AMSEL_R      (*((volatile uint32_t *)0x40065528))
+#define GPIO_PORTP_PCTL_R       (*((volatile uint32_t *)0x4006552C))
+#define GPIO_PORTP_ADCCTL_R     (*((volatile uint32_t *)0x40065530))
+#define GPIO_PORTP_DMACTL_R     (*((volatile uint32_t *)0x40065534))
+#define GPIO_PORTP_SI_R         (*((volatile uint32_t *)0x40065538))
+#define GPIO_PORTP_DR12R_R      (*((volatile uint32_t *)0x4006553C))
+#define GPIO_PORTP_WAKEPEN_R    (*((volatile uint32_t *)0x40065540))
+#define GPIO_PORTP_WAKELVL_R    (*((volatile uint32_t *)0x40065544))
+#define GPIO_PORTP_WAKESTAT_R   (*((volatile uint32_t *)0x40065548))
+#define GPIO_PORTP_PP_R         (*((volatile uint32_t *)0x40065FC0))
+#define GPIO_PORTP_PC_R         (*((volatile uint32_t *)0x40065FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTQ)
+//
+//*****************************************************************************
+#define GPIO_PORTQ_DATA_BITS_R  ((volatile uint32_t *)0x40066000)
+#define GPIO_PORTQ_DATA_R       (*((volatile uint32_t *)0x400663FC))
+#define GPIO_PORTQ_DIR_R        (*((volatile uint32_t *)0x40066400))
+#define GPIO_PORTQ_IS_R         (*((volatile uint32_t *)0x40066404))
+#define GPIO_PORTQ_IBE_R        (*((volatile uint32_t *)0x40066408))
+#define GPIO_PORTQ_IEV_R        (*((volatile uint32_t *)0x4006640C))
+#define GPIO_PORTQ_IM_R         (*((volatile uint32_t *)0x40066410))
+#define GPIO_PORTQ_RIS_R        (*((volatile uint32_t *)0x40066414))
+#define GPIO_PORTQ_MIS_R        (*((volatile uint32_t *)0x40066418))
+#define GPIO_PORTQ_ICR_R        (*((volatile uint32_t *)0x4006641C))
+#define GPIO_PORTQ_AFSEL_R      (*((volatile uint32_t *)0x40066420))
+#define GPIO_PORTQ_DR2R_R       (*((volatile uint32_t *)0x40066500))
+#define GPIO_PORTQ_DR4R_R       (*((volatile uint32_t *)0x40066504))
+#define GPIO_PORTQ_DR8R_R       (*((volatile uint32_t *)0x40066508))
+#define GPIO_PORTQ_ODR_R        (*((volatile uint32_t *)0x4006650C))
+#define GPIO_PORTQ_PUR_R        (*((volatile uint32_t *)0x40066510))
+#define GPIO_PORTQ_PDR_R        (*((volatile uint32_t *)0x40066514))
+#define GPIO_PORTQ_SLR_R        (*((volatile uint32_t *)0x40066518))
+#define GPIO_PORTQ_DEN_R        (*((volatile uint32_t *)0x4006651C))
+#define GPIO_PORTQ_LOCK_R       (*((volatile uint32_t *)0x40066520))
+#define GPIO_PORTQ_CR_R         (*((volatile uint32_t *)0x40066524))
+#define GPIO_PORTQ_AMSEL_R      (*((volatile uint32_t *)0x40066528))
+#define GPIO_PORTQ_PCTL_R       (*((volatile uint32_t *)0x4006652C))
+#define GPIO_PORTQ_ADCCTL_R     (*((volatile uint32_t *)0x40066530))
+#define GPIO_PORTQ_DMACTL_R     (*((volatile uint32_t *)0x40066534))
+#define GPIO_PORTQ_SI_R         (*((volatile uint32_t *)0x40066538))
+#define GPIO_PORTQ_DR12R_R      (*((volatile uint32_t *)0x4006653C))
+#define GPIO_PORTQ_WAKEPEN_R    (*((volatile uint32_t *)0x40066540))
+#define GPIO_PORTQ_WAKELVL_R    (*((volatile uint32_t *)0x40066544))
+#define GPIO_PORTQ_WAKESTAT_R   (*((volatile uint32_t *)0x40066548))
+#define GPIO_PORTQ_PP_R         (*((volatile uint32_t *)0x40066FC0))
+#define GPIO_PORTQ_PC_R         (*((volatile uint32_t *)0x40066FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTR)
+//
+//*****************************************************************************
+#define GPIO_PORTR_DATA_BITS_R  ((volatile uint32_t *)0x40067000)
+#define GPIO_PORTR_DATA_R       (*((volatile uint32_t *)0x400673FC))
+#define GPIO_PORTR_DIR_R        (*((volatile uint32_t *)0x40067400))
+#define GPIO_PORTR_IS_R         (*((volatile uint32_t *)0x40067404))
+#define GPIO_PORTR_IBE_R        (*((volatile uint32_t *)0x40067408))
+#define GPIO_PORTR_IEV_R        (*((volatile uint32_t *)0x4006740C))
+#define GPIO_PORTR_IM_R         (*((volatile uint32_t *)0x40067410))
+#define GPIO_PORTR_RIS_R        (*((volatile uint32_t *)0x40067414))
+#define GPIO_PORTR_MIS_R        (*((volatile uint32_t *)0x40067418))
+#define GPIO_PORTR_ICR_R        (*((volatile uint32_t *)0x4006741C))
+#define GPIO_PORTR_AFSEL_R      (*((volatile uint32_t *)0x40067420))
+#define GPIO_PORTR_DR2R_R       (*((volatile uint32_t *)0x40067500))
+#define GPIO_PORTR_DR4R_R       (*((volatile uint32_t *)0x40067504))
+#define GPIO_PORTR_DR8R_R       (*((volatile uint32_t *)0x40067508))
+#define GPIO_PORTR_ODR_R        (*((volatile uint32_t *)0x4006750C))
+#define GPIO_PORTR_PUR_R        (*((volatile uint32_t *)0x40067510))
+#define GPIO_PORTR_PDR_R        (*((volatile uint32_t *)0x40067514))
+#define GPIO_PORTR_SLR_R        (*((volatile uint32_t *)0x40067518))
+#define GPIO_PORTR_DEN_R        (*((volatile uint32_t *)0x4006751C))
+#define GPIO_PORTR_LOCK_R       (*((volatile uint32_t *)0x40067520))
+#define GPIO_PORTR_CR_R         (*((volatile uint32_t *)0x40067524))
+#define GPIO_PORTR_AMSEL_R      (*((volatile uint32_t *)0x40067528))
+#define GPIO_PORTR_PCTL_R       (*((volatile uint32_t *)0x4006752C))
+#define GPIO_PORTR_ADCCTL_R     (*((volatile uint32_t *)0x40067530))
+#define GPIO_PORTR_DMACTL_R     (*((volatile uint32_t *)0x40067534))
+#define GPIO_PORTR_SI_R         (*((volatile uint32_t *)0x40067538))
+#define GPIO_PORTR_DR12R_R      (*((volatile uint32_t *)0x4006753C))
+#define GPIO_PORTR_WAKEPEN_R    (*((volatile uint32_t *)0x40067540))
+#define GPIO_PORTR_WAKELVL_R    (*((volatile uint32_t *)0x40067544))
+#define GPIO_PORTR_WAKESTAT_R   (*((volatile uint32_t *)0x40067548))
+#define GPIO_PORTR_PP_R         (*((volatile uint32_t *)0x40067FC0))
+#define GPIO_PORTR_PC_R         (*((volatile uint32_t *)0x40067FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTS)
+//
+//*****************************************************************************
+#define GPIO_PORTS_DATA_BITS_R  ((volatile uint32_t *)0x40068000)
+#define GPIO_PORTS_DATA_R       (*((volatile uint32_t *)0x400683FC))
+#define GPIO_PORTS_DIR_R        (*((volatile uint32_t *)0x40068400))
+#define GPIO_PORTS_IS_R         (*((volatile uint32_t *)0x40068404))
+#define GPIO_PORTS_IBE_R        (*((volatile uint32_t *)0x40068408))
+#define GPIO_PORTS_IEV_R        (*((volatile uint32_t *)0x4006840C))
+#define GPIO_PORTS_IM_R         (*((volatile uint32_t *)0x40068410))
+#define GPIO_PORTS_RIS_R        (*((volatile uint32_t *)0x40068414))
+#define GPIO_PORTS_MIS_R        (*((volatile uint32_t *)0x40068418))
+#define GPIO_PORTS_ICR_R        (*((volatile uint32_t *)0x4006841C))
+#define GPIO_PORTS_AFSEL_R      (*((volatile uint32_t *)0x40068420))
+#define GPIO_PORTS_DR2R_R       (*((volatile uint32_t *)0x40068500))
+#define GPIO_PORTS_DR4R_R       (*((volatile uint32_t *)0x40068504))
+#define GPIO_PORTS_DR8R_R       (*((volatile uint32_t *)0x40068508))
+#define GPIO_PORTS_ODR_R        (*((volatile uint32_t *)0x4006850C))
+#define GPIO_PORTS_PUR_R        (*((volatile uint32_t *)0x40068510))
+#define GPIO_PORTS_PDR_R        (*((volatile uint32_t *)0x40068514))
+#define GPIO_PORTS_SLR_R        (*((volatile uint32_t *)0x40068518))
+#define GPIO_PORTS_DEN_R        (*((volatile uint32_t *)0x4006851C))
+#define GPIO_PORTS_LOCK_R       (*((volatile uint32_t *)0x40068520))
+#define GPIO_PORTS_CR_R         (*((volatile uint32_t *)0x40068524))
+#define GPIO_PORTS_AMSEL_R      (*((volatile uint32_t *)0x40068528))
+#define GPIO_PORTS_PCTL_R       (*((volatile uint32_t *)0x4006852C))
+#define GPIO_PORTS_ADCCTL_R     (*((volatile uint32_t *)0x40068530))
+#define GPIO_PORTS_DMACTL_R     (*((volatile uint32_t *)0x40068534))
+#define GPIO_PORTS_SI_R         (*((volatile uint32_t *)0x40068538))
+#define GPIO_PORTS_DR12R_R      (*((volatile uint32_t *)0x4006853C))
+#define GPIO_PORTS_WAKEPEN_R    (*((volatile uint32_t *)0x40068540))
+#define GPIO_PORTS_WAKELVL_R    (*((volatile uint32_t *)0x40068544))
+#define GPIO_PORTS_WAKESTAT_R   (*((volatile uint32_t *)0x40068548))
+#define GPIO_PORTS_PP_R         (*((volatile uint32_t *)0x40068FC0))
+#define GPIO_PORTS_PC_R         (*((volatile uint32_t *)0x40068FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTT)
+//
+//*****************************************************************************
+#define GPIO_PORTT_DATA_BITS_R  ((volatile uint32_t *)0x40069000)
+#define GPIO_PORTT_DATA_R       (*((volatile uint32_t *)0x400693FC))
+#define GPIO_PORTT_DIR_R        (*((volatile uint32_t *)0x40069400))
+#define GPIO_PORTT_IS_R         (*((volatile uint32_t *)0x40069404))
+#define GPIO_PORTT_IBE_R        (*((volatile uint32_t *)0x40069408))
+#define GPIO_PORTT_IEV_R        (*((volatile uint32_t *)0x4006940C))
+#define GPIO_PORTT_IM_R         (*((volatile uint32_t *)0x40069410))
+#define GPIO_PORTT_RIS_R        (*((volatile uint32_t *)0x40069414))
+#define GPIO_PORTT_MIS_R        (*((volatile uint32_t *)0x40069418))
+#define GPIO_PORTT_ICR_R        (*((volatile uint32_t *)0x4006941C))
+#define GPIO_PORTT_AFSEL_R      (*((volatile uint32_t *)0x40069420))
+#define GPIO_PORTT_DR2R_R       (*((volatile uint32_t *)0x40069500))
+#define GPIO_PORTT_DR4R_R       (*((volatile uint32_t *)0x40069504))
+#define GPIO_PORTT_DR8R_R       (*((volatile uint32_t *)0x40069508))
+#define GPIO_PORTT_ODR_R        (*((volatile uint32_t *)0x4006950C))
+#define GPIO_PORTT_PUR_R        (*((volatile uint32_t *)0x40069510))
+#define GPIO_PORTT_PDR_R        (*((volatile uint32_t *)0x40069514))
+#define GPIO_PORTT_SLR_R        (*((volatile uint32_t *)0x40069518))
+#define GPIO_PORTT_DEN_R        (*((volatile uint32_t *)0x4006951C))
+#define GPIO_PORTT_LOCK_R       (*((volatile uint32_t *)0x40069520))
+#define GPIO_PORTT_CR_R         (*((volatile uint32_t *)0x40069524))
+#define GPIO_PORTT_AMSEL_R      (*((volatile uint32_t *)0x40069528))
+#define GPIO_PORTT_PCTL_R       (*((volatile uint32_t *)0x4006952C))
+#define GPIO_PORTT_ADCCTL_R     (*((volatile uint32_t *)0x40069530))
+#define GPIO_PORTT_DMACTL_R     (*((volatile uint32_t *)0x40069534))
+#define GPIO_PORTT_SI_R         (*((volatile uint32_t *)0x40069538))
+#define GPIO_PORTT_DR12R_R      (*((volatile uint32_t *)0x4006953C))
+#define GPIO_PORTT_WAKEPEN_R    (*((volatile uint32_t *)0x40069540))
+#define GPIO_PORTT_WAKELVL_R    (*((volatile uint32_t *)0x40069544))
+#define GPIO_PORTT_WAKESTAT_R   (*((volatile uint32_t *)0x40069548))
+#define GPIO_PORTT_PP_R         (*((volatile uint32_t *)0x40069FC0))
+#define GPIO_PORTT_PC_R         (*((volatile uint32_t *)0x40069FC4))
+#define GPIO_PCTL_PR_R          (*((volatile uint32_t *)0x00012000))
+#define GPIO_PCTL_PS_R          (*((volatile uint32_t *)0x00013000))
+#define GPIO_PCTL_PT_R          (*((volatile uint32_t *)0x00014000))
+
+//*****************************************************************************
+//
+// EEPROM registers (EEPROM)
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_R         (*((volatile uint32_t *)0x400AF000))
+#define EEPROM_EEBLOCK_R        (*((volatile uint32_t *)0x400AF004))
+#define EEPROM_EEOFFSET_R       (*((volatile uint32_t *)0x400AF008))
+#define EEPROM_EERDWR_R         (*((volatile uint32_t *)0x400AF010))
+#define EEPROM_EERDWRINC_R      (*((volatile uint32_t *)0x400AF014))
+#define EEPROM_EEDONE_R         (*((volatile uint32_t *)0x400AF018))
+#define EEPROM_EESUPP_R         (*((volatile uint32_t *)0x400AF01C))
+#define EEPROM_EEUNLOCK_R       (*((volatile uint32_t *)0x400AF020))
+#define EEPROM_EEPROT_R         (*((volatile uint32_t *)0x400AF030))
+#define EEPROM_EEPASS0_R        (*((volatile uint32_t *)0x400AF034))
+#define EEPROM_EEPASS1_R        (*((volatile uint32_t *)0x400AF038))
+#define EEPROM_EEPASS2_R        (*((volatile uint32_t *)0x400AF03C))
+#define EEPROM_EEINT_R          (*((volatile uint32_t *)0x400AF040))
+#define EEPROM_EEHIDE0_R        (*((volatile uint32_t *)0x400AF050))
+#define EEPROM_EEHIDE1_R        (*((volatile uint32_t *)0x400AF054))
+#define EEPROM_EEHIDE2_R        (*((volatile uint32_t *)0x400AF058))
+#define EEPROM_EEDBGME_R        (*((volatile uint32_t *)0x400AF080))
+#define EEPROM_PP_R             (*((volatile uint32_t *)0x400AFFC0))
+
+//*****************************************************************************
+//
+// One wire registers (ONEWIRE0)
+//
+//*****************************************************************************
+#define ONEWIRE0_CS_R           (*((volatile uint32_t *)0x400B6000))
+#define ONEWIRE0_TIM_R          (*((volatile uint32_t *)0x400B6004))
+#define ONEWIRE0_DATW_R         (*((volatile uint32_t *)0x400B6008))
+#define ONEWIRE0_DATR_R         (*((volatile uint32_t *)0x400B600C))
+#define ONEWIRE0_IM_R           (*((volatile uint32_t *)0x400B6100))
+#define ONEWIRE0_RIS_R          (*((volatile uint32_t *)0x400B6104))
+#define ONEWIRE0_MIS_R          (*((volatile uint32_t *)0x400B6108))
+#define ONEWIRE0_ICR_R          (*((volatile uint32_t *)0x400B610C))
+#define ONEWIRE0_DMA_R          (*((volatile uint32_t *)0x400B6120))
+#define ONEWIRE0_PP_R           (*((volatile uint32_t *)0x400B6FC0))
+
+//*****************************************************************************
+//
+// I2C registers (I2C8)
+//
+//*****************************************************************************
+#define I2C8_MSA_R              (*((volatile uint32_t *)0x400B8000))
+#define I2C8_MCS_R              (*((volatile uint32_t *)0x400B8004))
+#define I2C8_MDR_R              (*((volatile uint32_t *)0x400B8008))
+#define I2C8_MTPR_R             (*((volatile uint32_t *)0x400B800C))
+#define I2C8_MIMR_R             (*((volatile uint32_t *)0x400B8010))
+#define I2C8_MRIS_R             (*((volatile uint32_t *)0x400B8014))
+#define I2C8_MMIS_R             (*((volatile uint32_t *)0x400B8018))
+#define I2C8_MICR_R             (*((volatile uint32_t *)0x400B801C))
+#define I2C8_MCR_R              (*((volatile uint32_t *)0x400B8020))
+#define I2C8_MCLKOCNT_R         (*((volatile uint32_t *)0x400B8024))
+#define I2C8_MBMON_R            (*((volatile uint32_t *)0x400B802C))
+#define I2C8_MBLEN_R            (*((volatile uint32_t *)0x400B8030))
+#define I2C8_MBCNT_R            (*((volatile uint32_t *)0x400B8034))
+#define I2C8_SOAR_R             (*((volatile uint32_t *)0x400B8800))
+#define I2C8_SCSR_R             (*((volatile uint32_t *)0x400B8804))
+#define I2C8_SDR_R              (*((volatile uint32_t *)0x400B8808))
+#define I2C8_SIMR_R             (*((volatile uint32_t *)0x400B880C))
+#define I2C8_SRIS_R             (*((volatile uint32_t *)0x400B8810))
+#define I2C8_SMIS_R             (*((volatile uint32_t *)0x400B8814))
+#define I2C8_SICR_R             (*((volatile uint32_t *)0x400B8818))
+#define I2C8_SOAR2_R            (*((volatile uint32_t *)0x400B881C))
+#define I2C8_SACKCTL_R          (*((volatile uint32_t *)0x400B8820))
+#define I2C8_FIFODATA_R         (*((volatile uint32_t *)0x400B8F00))
+#define I2C8_FIFOCTL_R          (*((volatile uint32_t *)0x400B8F04))
+#define I2C8_FIFOSTATUS_R       (*((volatile uint32_t *)0x400B8F08))
+#define I2C8_PP_R               (*((volatile uint32_t *)0x400B8FC0))
+#define I2C8_PC_R               (*((volatile uint32_t *)0x400B8FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C9)
+//
+//*****************************************************************************
+#define I2C9_MSA_R              (*((volatile uint32_t *)0x400B9000))
+#define I2C9_MCS_R              (*((volatile uint32_t *)0x400B9004))
+#define I2C9_MDR_R              (*((volatile uint32_t *)0x400B9008))
+#define I2C9_MTPR_R             (*((volatile uint32_t *)0x400B900C))
+#define I2C9_MIMR_R             (*((volatile uint32_t *)0x400B9010))
+#define I2C9_MRIS_R             (*((volatile uint32_t *)0x400B9014))
+#define I2C9_MMIS_R             (*((volatile uint32_t *)0x400B9018))
+#define I2C9_MICR_R             (*((volatile uint32_t *)0x400B901C))
+#define I2C9_MCR_R              (*((volatile uint32_t *)0x400B9020))
+#define I2C9_MCLKOCNT_R         (*((volatile uint32_t *)0x400B9024))
+#define I2C9_MBMON_R            (*((volatile uint32_t *)0x400B902C))
+#define I2C9_MBLEN_R            (*((volatile uint32_t *)0x400B9030))
+#define I2C9_MBCNT_R            (*((volatile uint32_t *)0x400B9034))
+#define I2C9_SOAR_R             (*((volatile uint32_t *)0x400B9800))
+#define I2C9_SCSR_R             (*((volatile uint32_t *)0x400B9804))
+#define I2C9_SDR_R              (*((volatile uint32_t *)0x400B9808))
+#define I2C9_SIMR_R             (*((volatile uint32_t *)0x400B980C))
+#define I2C9_SRIS_R             (*((volatile uint32_t *)0x400B9810))
+#define I2C9_SMIS_R             (*((volatile uint32_t *)0x400B9814))
+#define I2C9_SICR_R             (*((volatile uint32_t *)0x400B9818))
+#define I2C9_SOAR2_R            (*((volatile uint32_t *)0x400B981C))
+#define I2C9_SACKCTL_R          (*((volatile uint32_t *)0x400B9820))
+#define I2C9_FIFODATA_R         (*((volatile uint32_t *)0x400B9F00))
+#define I2C9_FIFOCTL_R          (*((volatile uint32_t *)0x400B9F04))
+#define I2C9_FIFOSTATUS_R       (*((volatile uint32_t *)0x400B9F08))
+#define I2C9_PP_R               (*((volatile uint32_t *)0x400B9FC0))
+#define I2C9_PC_R               (*((volatile uint32_t *)0x400B9FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C4)
+//
+//*****************************************************************************
+#define I2C4_MSA_R              (*((volatile uint32_t *)0x400C0000))
+#define I2C4_MCS_R              (*((volatile uint32_t *)0x400C0004))
+#define I2C4_MDR_R              (*((volatile uint32_t *)0x400C0008))
+#define I2C4_MTPR_R             (*((volatile uint32_t *)0x400C000C))
+#define I2C4_MIMR_R             (*((volatile uint32_t *)0x400C0010))
+#define I2C4_MRIS_R             (*((volatile uint32_t *)0x400C0014))
+#define I2C4_MMIS_R             (*((volatile uint32_t *)0x400C0018))
+#define I2C4_MICR_R             (*((volatile uint32_t *)0x400C001C))
+#define I2C4_MCR_R              (*((volatile uint32_t *)0x400C0020))
+#define I2C4_MCLKOCNT_R         (*((volatile uint32_t *)0x400C0024))
+#define I2C4_MBMON_R            (*((volatile uint32_t *)0x400C002C))
+#define I2C4_MBLEN_R            (*((volatile uint32_t *)0x400C0030))
+#define I2C4_MBCNT_R            (*((volatile uint32_t *)0x400C0034))
+#define I2C4_SOAR_R             (*((volatile uint32_t *)0x400C0800))
+#define I2C4_SCSR_R             (*((volatile uint32_t *)0x400C0804))
+#define I2C4_SDR_R              (*((volatile uint32_t *)0x400C0808))
+#define I2C4_SIMR_R             (*((volatile uint32_t *)0x400C080C))
+#define I2C4_SRIS_R             (*((volatile uint32_t *)0x400C0810))
+#define I2C4_SMIS_R             (*((volatile uint32_t *)0x400C0814))
+#define I2C4_SICR_R             (*((volatile uint32_t *)0x400C0818))
+#define I2C4_SOAR2_R            (*((volatile uint32_t *)0x400C081C))
+#define I2C4_SACKCTL_R          (*((volatile uint32_t *)0x400C0820))
+#define I2C4_FIFODATA_R         (*((volatile uint32_t *)0x400C0F00))
+#define I2C4_FIFOCTL_R          (*((volatile uint32_t *)0x400C0F04))
+#define I2C4_FIFOSTATUS_R       (*((volatile uint32_t *)0x400C0F08))
+#define I2C4_PP_R               (*((volatile uint32_t *)0x400C0FC0))
+#define I2C4_PC_R               (*((volatile uint32_t *)0x400C0FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C5)
+//
+//*****************************************************************************
+#define I2C5_MSA_R              (*((volatile uint32_t *)0x400C1000))
+#define I2C5_MCS_R              (*((volatile uint32_t *)0x400C1004))
+#define I2C5_MDR_R              (*((volatile uint32_t *)0x400C1008))
+#define I2C5_MTPR_R             (*((volatile uint32_t *)0x400C100C))
+#define I2C5_MIMR_R             (*((volatile uint32_t *)0x400C1010))
+#define I2C5_MRIS_R             (*((volatile uint32_t *)0x400C1014))
+#define I2C5_MMIS_R             (*((volatile uint32_t *)0x400C1018))
+#define I2C5_MICR_R             (*((volatile uint32_t *)0x400C101C))
+#define I2C5_MCR_R              (*((volatile uint32_t *)0x400C1020))
+#define I2C5_MCLKOCNT_R         (*((volatile uint32_t *)0x400C1024))
+#define I2C5_MBMON_R            (*((volatile uint32_t *)0x400C102C))
+#define I2C5_MBLEN_R            (*((volatile uint32_t *)0x400C1030))
+#define I2C5_MBCNT_R            (*((volatile uint32_t *)0x400C1034))
+#define I2C5_SOAR_R             (*((volatile uint32_t *)0x400C1800))
+#define I2C5_SCSR_R             (*((volatile uint32_t *)0x400C1804))
+#define I2C5_SDR_R              (*((volatile uint32_t *)0x400C1808))
+#define I2C5_SIMR_R             (*((volatile uint32_t *)0x400C180C))
+#define I2C5_SRIS_R             (*((volatile uint32_t *)0x400C1810))
+#define I2C5_SMIS_R             (*((volatile uint32_t *)0x400C1814))
+#define I2C5_SICR_R             (*((volatile uint32_t *)0x400C1818))
+#define I2C5_SOAR2_R            (*((volatile uint32_t *)0x400C181C))
+#define I2C5_SACKCTL_R          (*((volatile uint32_t *)0x400C1820))
+#define I2C5_FIFODATA_R         (*((volatile uint32_t *)0x400C1F00))
+#define I2C5_FIFOCTL_R          (*((volatile uint32_t *)0x400C1F04))
+#define I2C5_FIFOSTATUS_R       (*((volatile uint32_t *)0x400C1F08))
+#define I2C5_PP_R               (*((volatile uint32_t *)0x400C1FC0))
+#define I2C5_PC_R               (*((volatile uint32_t *)0x400C1FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C6)
+//
+//*****************************************************************************
+#define I2C6_MSA_R              (*((volatile uint32_t *)0x400C2000))
+#define I2C6_MCS_R              (*((volatile uint32_t *)0x400C2004))
+#define I2C6_MDR_R              (*((volatile uint32_t *)0x400C2008))
+#define I2C6_MTPR_R             (*((volatile uint32_t *)0x400C200C))
+#define I2C6_MIMR_R             (*((volatile uint32_t *)0x400C2010))
+#define I2C6_MRIS_R             (*((volatile uint32_t *)0x400C2014))
+#define I2C6_MMIS_R             (*((volatile uint32_t *)0x400C2018))
+#define I2C6_MICR_R             (*((volatile uint32_t *)0x400C201C))
+#define I2C6_MCR_R              (*((volatile uint32_t *)0x400C2020))
+#define I2C6_MCLKOCNT_R         (*((volatile uint32_t *)0x400C2024))
+#define I2C6_MBMON_R            (*((volatile uint32_t *)0x400C202C))
+#define I2C6_MBLEN_R            (*((volatile uint32_t *)0x400C2030))
+#define I2C6_MBCNT_R            (*((volatile uint32_t *)0x400C2034))
+#define I2C6_SOAR_R             (*((volatile uint32_t *)0x400C2800))
+#define I2C6_SCSR_R             (*((volatile uint32_t *)0x400C2804))
+#define I2C6_SDR_R              (*((volatile uint32_t *)0x400C2808))
+#define I2C6_SIMR_R             (*((volatile uint32_t *)0x400C280C))
+#define I2C6_SRIS_R             (*((volatile uint32_t *)0x400C2810))
+#define I2C6_SMIS_R             (*((volatile uint32_t *)0x400C2814))
+#define I2C6_SICR_R             (*((volatile uint32_t *)0x400C2818))
+#define I2C6_SOAR2_R            (*((volatile uint32_t *)0x400C281C))
+#define I2C6_SACKCTL_R          (*((volatile uint32_t *)0x400C2820))
+#define I2C6_FIFODATA_R         (*((volatile uint32_t *)0x400C2F00))
+#define I2C6_FIFOCTL_R          (*((volatile uint32_t *)0x400C2F04))
+#define I2C6_FIFOSTATUS_R       (*((volatile uint32_t *)0x400C2F08))
+#define I2C6_PP_R               (*((volatile uint32_t *)0x400C2FC0))
+#define I2C6_PC_R               (*((volatile uint32_t *)0x400C2FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C7)
+//
+//*****************************************************************************
+#define I2C7_MSA_R              (*((volatile uint32_t *)0x400C3000))
+#define I2C7_MCS_R              (*((volatile uint32_t *)0x400C3004))
+#define I2C7_MDR_R              (*((volatile uint32_t *)0x400C3008))
+#define I2C7_MTPR_R             (*((volatile uint32_t *)0x400C300C))
+#define I2C7_MIMR_R             (*((volatile uint32_t *)0x400C3010))
+#define I2C7_MRIS_R             (*((volatile uint32_t *)0x400C3014))
+#define I2C7_MMIS_R             (*((volatile uint32_t *)0x400C3018))
+#define I2C7_MICR_R             (*((volatile uint32_t *)0x400C301C))
+#define I2C7_MCR_R              (*((volatile uint32_t *)0x400C3020))
+#define I2C7_MCLKOCNT_R         (*((volatile uint32_t *)0x400C3024))
+#define I2C7_MBMON_R            (*((volatile uint32_t *)0x400C302C))
+#define I2C7_MBLEN_R            (*((volatile uint32_t *)0x400C3030))
+#define I2C7_MBCNT_R            (*((volatile uint32_t *)0x400C3034))
+#define I2C7_SOAR_R             (*((volatile uint32_t *)0x400C3800))
+#define I2C7_SCSR_R             (*((volatile uint32_t *)0x400C3804))
+#define I2C7_SDR_R              (*((volatile uint32_t *)0x400C3808))
+#define I2C7_SIMR_R             (*((volatile uint32_t *)0x400C380C))
+#define I2C7_SRIS_R             (*((volatile uint32_t *)0x400C3810))
+#define I2C7_SMIS_R             (*((volatile uint32_t *)0x400C3814))
+#define I2C7_SICR_R             (*((volatile uint32_t *)0x400C3818))
+#define I2C7_SOAR2_R            (*((volatile uint32_t *)0x400C381C))
+#define I2C7_SACKCTL_R          (*((volatile uint32_t *)0x400C3820))
+#define I2C7_FIFODATA_R         (*((volatile uint32_t *)0x400C3F00))
+#define I2C7_FIFOCTL_R          (*((volatile uint32_t *)0x400C3F04))
+#define I2C7_FIFOSTATUS_R       (*((volatile uint32_t *)0x400C3F08))
+#define I2C7_PP_R               (*((volatile uint32_t *)0x400C3FC0))
+#define I2C7_PC_R               (*((volatile uint32_t *)0x400C3FC4))
+
+//*****************************************************************************
+//
+// External Peripheral Interface registers (EPI0)
+//
+//*****************************************************************************
+#define EPI0_CFG_R              (*((volatile uint32_t *)0x400D0000))
+#define EPI0_BAUD_R             (*((volatile uint32_t *)0x400D0004))
+#define EPI0_BAUD2_R            (*((volatile uint32_t *)0x400D0008))
+#define EPI0_HB16CFG_R          (*((volatile uint32_t *)0x400D0010))
+#define EPI0_GPCFG_R            (*((volatile uint32_t *)0x400D0010))
+#define EPI0_SDRAMCFG_R         (*((volatile uint32_t *)0x400D0010))
+#define EPI0_HB8CFG_R           (*((volatile uint32_t *)0x400D0010))
+#define EPI0_HB8CFG2_R          (*((volatile uint32_t *)0x400D0014))
+#define EPI0_HB16CFG2_R         (*((volatile uint32_t *)0x400D0014))
+#define EPI0_ADDRMAP_R          (*((volatile uint32_t *)0x400D001C))
+#define EPI0_RSIZE0_R           (*((volatile uint32_t *)0x400D0020))
+#define EPI0_RADDR0_R           (*((volatile uint32_t *)0x400D0024))
+#define EPI0_RPSTD0_R           (*((volatile uint32_t *)0x400D0028))
+#define EPI0_RSIZE1_R           (*((volatile uint32_t *)0x400D0030))
+#define EPI0_RADDR1_R           (*((volatile uint32_t *)0x400D0034))
+#define EPI0_RPSTD1_R           (*((volatile uint32_t *)0x400D0038))
+#define EPI0_STAT_R             (*((volatile uint32_t *)0x400D0060))
+#define EPI0_RFIFOCNT_R         (*((volatile uint32_t *)0x400D006C))
+#define EPI0_READFIFO0_R        (*((volatile uint32_t *)0x400D0070))
+#define EPI0_READFIFO1_R        (*((volatile uint32_t *)0x400D0074))
+#define EPI0_READFIFO2_R        (*((volatile uint32_t *)0x400D0078))
+#define EPI0_READFIFO3_R        (*((volatile uint32_t *)0x400D007C))
+#define EPI0_READFIFO4_R        (*((volatile uint32_t *)0x400D0080))
+#define EPI0_READFIFO5_R        (*((volatile uint32_t *)0x400D0084))
+#define EPI0_READFIFO6_R        (*((volatile uint32_t *)0x400D0088))
+#define EPI0_READFIFO7_R        (*((volatile uint32_t *)0x400D008C))
+#define EPI0_FIFOLVL_R          (*((volatile uint32_t *)0x400D0200))
+#define EPI0_WFIFOCNT_R         (*((volatile uint32_t *)0x400D0204))
+#define EPI0_DMATXCNT_R         (*((volatile uint32_t *)0x400D0208))
+#define EPI0_IM_R               (*((volatile uint32_t *)0x400D0210))
+#define EPI0_RIS_R              (*((volatile uint32_t *)0x400D0214))
+#define EPI0_MIS_R              (*((volatile uint32_t *)0x400D0218))
+#define EPI0_EISC_R             (*((volatile uint32_t *)0x400D021C))
+#define EPI0_HB8CFG3_R          (*((volatile uint32_t *)0x400D0308))
+#define EPI0_HB16CFG3_R         (*((volatile uint32_t *)0x400D0308))
+#define EPI0_HB16CFG4_R         (*((volatile uint32_t *)0x400D030C))
+#define EPI0_HB8CFG4_R          (*((volatile uint32_t *)0x400D030C))
+#define EPI0_HB8TIME_R          (*((volatile uint32_t *)0x400D0310))
+#define EPI0_HB16TIME_R         (*((volatile uint32_t *)0x400D0310))
+#define EPI0_HB8TIME2_R         (*((volatile uint32_t *)0x400D0314))
+#define EPI0_HB16TIME2_R        (*((volatile uint32_t *)0x400D0314))
+#define EPI0_HB16TIME3_R        (*((volatile uint32_t *)0x400D0318))
+#define EPI0_HB8TIME3_R         (*((volatile uint32_t *)0x400D0318))
+#define EPI0_HB8TIME4_R         (*((volatile uint32_t *)0x400D031C))
+#define EPI0_HB16TIME4_R        (*((volatile uint32_t *)0x400D031C))
+#define EPI0_HBPSRAM_R          (*((volatile uint32_t *)0x400D0360))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER6)
+//
+//*****************************************************************************
+#define TIMER6_CFG_R            (*((volatile uint32_t *)0x400E0000))
+#define TIMER6_TAMR_R           (*((volatile uint32_t *)0x400E0004))
+#define TIMER6_TBMR_R           (*((volatile uint32_t *)0x400E0008))
+#define TIMER6_CTL_R            (*((volatile uint32_t *)0x400E000C))
+#define TIMER6_SYNC_R           (*((volatile uint32_t *)0x400E0010))
+#define TIMER6_IMR_R            (*((volatile uint32_t *)0x400E0018))
+#define TIMER6_RIS_R            (*((volatile uint32_t *)0x400E001C))
+#define TIMER6_MIS_R            (*((volatile uint32_t *)0x400E0020))
+#define TIMER6_ICR_R            (*((volatile uint32_t *)0x400E0024))
+#define TIMER6_TAILR_R          (*((volatile uint32_t *)0x400E0028))
+#define TIMER6_TBILR_R          (*((volatile uint32_t *)0x400E002C))
+#define TIMER6_TAMATCHR_R       (*((volatile uint32_t *)0x400E0030))
+#define TIMER6_TBMATCHR_R       (*((volatile uint32_t *)0x400E0034))
+#define TIMER6_TAPR_R           (*((volatile uint32_t *)0x400E0038))
+#define TIMER6_TBPR_R           (*((volatile uint32_t *)0x400E003C))
+#define TIMER6_TAPMR_R          (*((volatile uint32_t *)0x400E0040))
+#define TIMER6_TBPMR_R          (*((volatile uint32_t *)0x400E0044))
+#define TIMER6_TAR_R            (*((volatile uint32_t *)0x400E0048))
+#define TIMER6_TBR_R            (*((volatile uint32_t *)0x400E004C))
+#define TIMER6_TAV_R            (*((volatile uint32_t *)0x400E0050))
+#define TIMER6_TBV_R            (*((volatile uint32_t *)0x400E0054))
+#define TIMER6_RTCPD_R          (*((volatile uint32_t *)0x400E0058))
+#define TIMER6_TAPS_R           (*((volatile uint32_t *)0x400E005C))
+#define TIMER6_TBPS_R           (*((volatile uint32_t *)0x400E0060))
+#define TIMER6_DMAEV_R          (*((volatile uint32_t *)0x400E006C))
+#define TIMER6_ADCEV_R          (*((volatile uint32_t *)0x400E0070))
+#define TIMER6_PP_R             (*((volatile uint32_t *)0x400E0FC0))
+#define TIMER6_CC_R             (*((volatile uint32_t *)0x400E0FC8))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER7)
+//
+//*****************************************************************************
+#define TIMER7_CFG_R            (*((volatile uint32_t *)0x400E1000))
+#define TIMER7_TAMR_R           (*((volatile uint32_t *)0x400E1004))
+#define TIMER7_TBMR_R           (*((volatile uint32_t *)0x400E1008))
+#define TIMER7_CTL_R            (*((volatile uint32_t *)0x400E100C))
+#define TIMER7_SYNC_R           (*((volatile uint32_t *)0x400E1010))
+#define TIMER7_IMR_R            (*((volatile uint32_t *)0x400E1018))
+#define TIMER7_RIS_R            (*((volatile uint32_t *)0x400E101C))
+#define TIMER7_MIS_R            (*((volatile uint32_t *)0x400E1020))
+#define TIMER7_ICR_R            (*((volatile uint32_t *)0x400E1024))
+#define TIMER7_TAILR_R          (*((volatile uint32_t *)0x400E1028))
+#define TIMER7_TBILR_R          (*((volatile uint32_t *)0x400E102C))
+#define TIMER7_TAMATCHR_R       (*((volatile uint32_t *)0x400E1030))
+#define TIMER7_TBMATCHR_R       (*((volatile uint32_t *)0x400E1034))
+#define TIMER7_TAPR_R           (*((volatile uint32_t *)0x400E1038))
+#define TIMER7_TBPR_R           (*((volatile uint32_t *)0x400E103C))
+#define TIMER7_TAPMR_R          (*((volatile uint32_t *)0x400E1040))
+#define TIMER7_TBPMR_R          (*((volatile uint32_t *)0x400E1044))
+#define TIMER7_TAR_R            (*((volatile uint32_t *)0x400E1048))
+#define TIMER7_TBR_R            (*((volatile uint32_t *)0x400E104C))
+#define TIMER7_TAV_R            (*((volatile uint32_t *)0x400E1050))
+#define TIMER7_TBV_R            (*((volatile uint32_t *)0x400E1054))
+#define TIMER7_RTCPD_R          (*((volatile uint32_t *)0x400E1058))
+#define TIMER7_TAPS_R           (*((volatile uint32_t *)0x400E105C))
+#define TIMER7_TBPS_R           (*((volatile uint32_t *)0x400E1060))
+#define TIMER7_DMAEV_R          (*((volatile uint32_t *)0x400E106C))
+#define TIMER7_ADCEV_R          (*((volatile uint32_t *)0x400E1070))
+#define TIMER7_PP_R             (*((volatile uint32_t *)0x400E1FC0))
+#define TIMER7_CC_R             (*((volatile uint32_t *)0x400E1FC8))
+
+//*****************************************************************************
+//
+// EMAC registers (EMAC0)
+//
+//*****************************************************************************
+#define EMAC0_CFG_R             (*((volatile uint32_t *)0x400EC000))
+#define EMAC0_FRAMEFLTR_R       (*((volatile uint32_t *)0x400EC004))
+#define EMAC0_HASHTBLH_R        (*((volatile uint32_t *)0x400EC008))
+#define EMAC0_HASHTBLL_R        (*((volatile uint32_t *)0x400EC00C))
+#define EMAC0_MIIADDR_R         (*((volatile uint32_t *)0x400EC010))
+#define EMAC0_MIIDATA_R         (*((volatile uint32_t *)0x400EC014))
+#define EMAC0_FLOWCTL_R         (*((volatile uint32_t *)0x400EC018))
+#define EMAC0_VLANTG_R          (*((volatile uint32_t *)0x400EC01C))
+#define EMAC0_STATUS_R          (*((volatile uint32_t *)0x400EC024))
+#define EMAC0_RWUFF_R           (*((volatile uint32_t *)0x400EC028))
+#define EMAC0_PMTCTLSTAT_R      (*((volatile uint32_t *)0x400EC02C))
+#define EMAC0_RIS_R             (*((volatile uint32_t *)0x400EC038))
+#define EMAC0_IM_R              (*((volatile uint32_t *)0x400EC03C))
+#define EMAC0_ADDR0H_R          (*((volatile uint32_t *)0x400EC040))
+#define EMAC0_ADDR0L_R          (*((volatile uint32_t *)0x400EC044))
+#define EMAC0_ADDR1H_R          (*((volatile uint32_t *)0x400EC048))
+#define EMAC0_ADDR1L_R          (*((volatile uint32_t *)0x400EC04C))
+#define EMAC0_ADDR2H_R          (*((volatile uint32_t *)0x400EC050))
+#define EMAC0_ADDR2L_R          (*((volatile uint32_t *)0x400EC054))
+#define EMAC0_ADDR3H_R          (*((volatile uint32_t *)0x400EC058))
+#define EMAC0_ADDR3L_R          (*((volatile uint32_t *)0x400EC05C))
+#define EMAC0_WDOGTO_R          (*((volatile uint32_t *)0x400EC0DC))
+#define EMAC0_MMCCTRL_R         (*((volatile uint32_t *)0x400EC100))
+#define EMAC0_MMCRXRIS_R        (*((volatile uint32_t *)0x400EC104))
+#define EMAC0_MMCTXRIS_R        (*((volatile uint32_t *)0x400EC108))
+#define EMAC0_MMCRXIM_R         (*((volatile uint32_t *)0x400EC10C))
+#define EMAC0_MMCTXIM_R         (*((volatile uint32_t *)0x400EC110))
+#define EMAC0_TXCNTGB_R         (*((volatile uint32_t *)0x400EC118))
+#define EMAC0_TXCNTSCOL_R       (*((volatile uint32_t *)0x400EC14C))
+#define EMAC0_TXCNTMCOL_R       (*((volatile uint32_t *)0x400EC150))
+#define EMAC0_TXOCTCNTG_R       (*((volatile uint32_t *)0x400EC164))
+#define EMAC0_RXCNTGB_R         (*((volatile uint32_t *)0x400EC180))
+#define EMAC0_RXCNTCRCERR_R     (*((volatile uint32_t *)0x400EC194))
+#define EMAC0_RXCNTALGNERR_R    (*((volatile uint32_t *)0x400EC198))
+#define EMAC0_RXCNTGUNI_R       (*((volatile uint32_t *)0x400EC1C4))
+#define EMAC0_VLNINCREP_R       (*((volatile uint32_t *)0x400EC584))
+#define EMAC0_VLANHASH_R        (*((volatile uint32_t *)0x400EC588))
+#define EMAC0_TIMSTCTRL_R       (*((volatile uint32_t *)0x400EC700))
+#define EMAC0_SUBSECINC_R       (*((volatile uint32_t *)0x400EC704))
+#define EMAC0_TIMSEC_R          (*((volatile uint32_t *)0x400EC708))
+#define EMAC0_TIMNANO_R         (*((volatile uint32_t *)0x400EC70C))
+#define EMAC0_TIMSECU_R         (*((volatile uint32_t *)0x400EC710))
+#define EMAC0_TIMNANOU_R        (*((volatile uint32_t *)0x400EC714))
+#define EMAC0_TIMADD_R          (*((volatile uint32_t *)0x400EC718))
+#define EMAC0_TARGSEC_R         (*((volatile uint32_t *)0x400EC71C))
+#define EMAC0_TARGNANO_R        (*((volatile uint32_t *)0x400EC720))
+#define EMAC0_HWORDSEC_R        (*((volatile uint32_t *)0x400EC724))
+#define EMAC0_TIMSTAT_R         (*((volatile uint32_t *)0x400EC728))
+#define EMAC0_PPSCTRL_R         (*((volatile uint32_t *)0x400EC72C))
+#define EMAC0_PPS0INTVL_R       (*((volatile uint32_t *)0x400EC760))
+#define EMAC0_PPS0WIDTH_R       (*((volatile uint32_t *)0x400EC764))
+#define EMAC0_DMABUSMOD_R       (*((volatile uint32_t *)0x400ECC00))
+#define EMAC0_TXPOLLD_R         (*((volatile uint32_t *)0x400ECC04))
+#define EMAC0_RXPOLLD_R         (*((volatile uint32_t *)0x400ECC08))
+#define EMAC0_RXDLADDR_R        (*((volatile uint32_t *)0x400ECC0C))
+#define EMAC0_TXDLADDR_R        (*((volatile uint32_t *)0x400ECC10))
+#define EMAC0_DMARIS_R          (*((volatile uint32_t *)0x400ECC14))
+#define EMAC0_DMAOPMODE_R       (*((volatile uint32_t *)0x400ECC18))
+#define EMAC0_DMAIM_R           (*((volatile uint32_t *)0x400ECC1C))
+#define EMAC0_MFBOC_R           (*((volatile uint32_t *)0x400ECC20))
+#define EMAC0_RXINTWDT_R        (*((volatile uint32_t *)0x400ECC24))
+#define EMAC0_HOSTXDESC_R       (*((volatile uint32_t *)0x400ECC48))
+#define EMAC0_HOSRXDESC_R       (*((volatile uint32_t *)0x400ECC4C))
+#define EMAC0_HOSTXBA_R         (*((volatile uint32_t *)0x400ECC50))
+#define EMAC0_HOSRXBA_R         (*((volatile uint32_t *)0x400ECC54))
+#define EMAC0_PP_R              (*((volatile uint32_t *)0x400ECFC0))
+#define EMAC0_PC_R              (*((volatile uint32_t *)0x400ECFC4))
+#define EMAC0_CC_R              (*((volatile uint32_t *)0x400ECFC8))
+#define EMAC0_EPHYRIS_R         (*((volatile uint32_t *)0x400ECFD0))
+#define EMAC0_EPHYIM_R          (*((volatile uint32_t *)0x400ECFD4))
+#define EMAC0_EPHYMISC_R        (*((volatile uint32_t *)0x400ECFD8))
+
+//*****************************************************************************
+//
+// EPHY registers (EMAC0)
+//
+//*****************************************************************************
+#define EPHY_BMCR               0x00000000  // Ethernet PHY Basic Mode Control
+#define EPHY_BMSR               0x00000001  // Ethernet PHY Basic Mode Status
+#define EPHY_ID1                0x00000002  // Ethernet PHY Identifier Register
+                                            // 1
+#define EPHY_ID2                0x00000003  // Ethernet PHY Identifier Register
+                                            // 2
+#define EPHY_ANA                0x00000004  // Ethernet PHY Auto-Negotiation
+                                            // Advertisement
+#define EPHY_ANLPA              0x00000005  // Ethernet PHY Auto-Negotiation
+                                            // Link Partner Ability
+#define EPHY_ANER               0x00000006  // Ethernet PHY Auto-Negotiation
+                                            // Expansion
+#define EPHY_ANNPTR             0x00000007  // Ethernet PHY Auto-Negotiation
+                                            // Next Page TX
+#define EPHY_ANLNPTR            0x00000008  // Ethernet PHY Auto-Negotiation
+                                            // Link Partner Ability Next Page
+#define EPHY_CFG1               0x00000009  // Ethernet PHY Configuration 1
+#define EPHY_CFG2               0x0000000A  // Ethernet PHY Configuration 2
+#define EPHY_CFG3               0x0000000B  // Ethernet PHY Configuration 3
+#define EPHY_REGCTL             0x0000000D  // Ethernet PHY Register Control
+#define EPHY_ADDAR              0x0000000E  // Ethernet PHY Address or Data
+#define EPHY_STS                0x00000010  // Ethernet PHY Status
+#define EPHY_SCR                0x00000011  // Ethernet PHY Specific Control
+#define EPHY_MISR1              0x00000012  // Ethernet PHY MII Interrupt
+                                            // Status 1
+#define EPHY_MISR2              0x00000013  // Ethernet PHY MII Interrupt
+                                            // Status 2
+#define EPHY_FCSCR              0x00000014  // Ethernet PHY False Carrier Sense
+                                            // Counter
+#define EPHY_RXERCNT            0x00000015  // Ethernet PHY Receive Error Count
+#define EPHY_BISTCR             0x00000016  // Ethernet PHY BIST Control
+#define EPHY_LEDCR              0x00000018  // Ethernet PHY LED Control
+#define EPHY_CTL                0x00000019  // Ethernet PHY Control
+#define EPHY_10BTSC             0x0000001A  // Ethernet PHY 10Base-T
+                                            // Status/Control - MR26
+#define EPHY_BICSR1             0x0000001B  // Ethernet PHY BIST Control and
+                                            // Status 1
+#define EPHY_BICSR2             0x0000001C  // Ethernet PHY BIST Control and
+                                            // Status 2
+#define EPHY_CDCR               0x0000001E  // Ethernet PHY Cable Diagnostic
+                                            // Control
+#define EPHY_RCR                0x0000001F  // Ethernet PHY Reset Control
+#define EPHY_LEDCFG             0x00000025  // Ethernet PHY LED Configuration
+
+//*****************************************************************************
+//
+// System Exception Module registers (SYSEXC)
+//
+//*****************************************************************************
+#define SYSEXC_RIS_R            (*((volatile uint32_t *)0x400F9000))
+#define SYSEXC_IM_R             (*((volatile uint32_t *)0x400F9004))
+#define SYSEXC_MIS_R            (*((volatile uint32_t *)0x400F9008))
+#define SYSEXC_IC_R             (*((volatile uint32_t *)0x400F900C))
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R              (*((volatile uint32_t *)0x400FC000))
+#define HIB_RTCM0_R             (*((volatile uint32_t *)0x400FC004))
+#define HIB_RTCLD_R             (*((volatile uint32_t *)0x400FC00C))
+#define HIB_CTL_R               (*((volatile uint32_t *)0x400FC010))
+#define HIB_IM_R                (*((volatile uint32_t *)0x400FC014))
+#define HIB_RIS_R               (*((volatile uint32_t *)0x400FC018))
+#define HIB_MIS_R               (*((volatile uint32_t *)0x400FC01C))
+#define HIB_IC_R                (*((volatile uint32_t *)0x400FC020))
+#define HIB_RTCT_R              (*((volatile uint32_t *)0x400FC024))
+#define HIB_RTCSS_R             (*((volatile uint32_t *)0x400FC028))
+#define HIB_IO_R                (*((volatile uint32_t *)0x400FC02C))
+#define HIB_DATA_R              (*((volatile uint32_t *)0x400FC030))
+#define HIB_CALCTL_R            (*((volatile uint32_t *)0x400FC300))
+#define HIB_CAL0_R              (*((volatile uint32_t *)0x400FC310))
+#define HIB_CAL1_R              (*((volatile uint32_t *)0x400FC314))
+#define HIB_CALLD0_R            (*((volatile uint32_t *)0x400FC320))
+#define HIB_CALLD1_R            (*((volatile uint32_t *)0x400FC324))
+#define HIB_CALM0_R             (*((volatile uint32_t *)0x400FC330))
+#define HIB_CALM1_R             (*((volatile uint32_t *)0x400FC334))
+#define HIB_LOCK_R              (*((volatile uint32_t *)0x400FC360))
+#define HIB_TPCTL_R             (*((volatile uint32_t *)0x400FC400))
+#define HIB_TPSTAT_R            (*((volatile uint32_t *)0x400FC404))
+#define HIB_TPIO_R              (*((volatile uint32_t *)0x400FC410))
+#define HIB_TPLOG0_R            (*((volatile uint32_t *)0x400FC4E0))
+#define HIB_TPLOG1_R            (*((volatile uint32_t *)0x400FC4E4))
+#define HIB_TPLOG2_R            (*((volatile uint32_t *)0x400FC4E8))
+#define HIB_TPLOG3_R            (*((volatile uint32_t *)0x400FC4EC))
+#define HIB_TPLOG4_R            (*((volatile uint32_t *)0x400FC4F0))
+#define HIB_TPLOG5_R            (*((volatile uint32_t *)0x400FC4F4))
+#define HIB_TPLOG6_R            (*((volatile uint32_t *)0x400FC4F8))
+#define HIB_TPLOG7_R            (*((volatile uint32_t *)0x400FC4FC))
+#define HIB_PP_R                (*((volatile uint32_t *)0x400FCFC0))
+#define HIB_CC_R                (*((volatile uint32_t *)0x400FCFC8))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R             (*((volatile uint32_t *)0x400FD000))
+#define FLASH_FMD_R             (*((volatile uint32_t *)0x400FD004))
+#define FLASH_FMC_R             (*((volatile uint32_t *)0x400FD008))
+#define FLASH_FCRIS_R           (*((volatile uint32_t *)0x400FD00C))
+#define FLASH_FCIM_R            (*((volatile uint32_t *)0x400FD010))
+#define FLASH_FCMISC_R          (*((volatile uint32_t *)0x400FD014))
+#define FLASH_FMC2_R            (*((volatile uint32_t *)0x400FD020))
+#define FLASH_FWBVAL_R          (*((volatile uint32_t *)0x400FD030))
+#define FLASH_FLPEKEY_R         (*((volatile uint32_t *)0x400FD03C))
+#define FLASH_FWBN_R            (*((volatile uint32_t *)0x400FD100))
+#define FLASH_PP_R              (*((volatile uint32_t *)0x400FDFC0))
+#define FLASH_SSIZE_R           (*((volatile uint32_t *)0x400FDFC4))
+#define FLASH_CONF_R            (*((volatile uint32_t *)0x400FDFC8))
+#define FLASH_ROMSWMAP_R        (*((volatile uint32_t *)0x400FDFCC))
+#define FLASH_DMASZ_R           (*((volatile uint32_t *)0x400FDFD0))
+#define FLASH_DMAST_R           (*((volatile uint32_t *)0x400FDFD4))
+#define FLASH_RVP_R             (*((volatile uint32_t *)0x400FE0D4))
+#define FLASH_BOOTCFG_R         (*((volatile uint32_t *)0x400FE1D0))
+#define FLASH_USERREG0_R        (*((volatile uint32_t *)0x400FE1E0))
+#define FLASH_USERREG1_R        (*((volatile uint32_t *)0x400FE1E4))
+#define FLASH_USERREG2_R        (*((volatile uint32_t *)0x400FE1E8))
+#define FLASH_USERREG3_R        (*((volatile uint32_t *)0x400FE1EC))
+#define FLASH_FMPRE0_R          (*((volatile uint32_t *)0x400FE200))
+#define FLASH_FMPRE1_R          (*((volatile uint32_t *)0x400FE204))
+#define FLASH_FMPRE2_R          (*((volatile uint32_t *)0x400FE208))
+#define FLASH_FMPRE3_R          (*((volatile uint32_t *)0x400FE20C))
+#define FLASH_FMPRE4_R          (*((volatile uint32_t *)0x400FE210))
+#define FLASH_FMPRE5_R          (*((volatile uint32_t *)0x400FE214))
+#define FLASH_FMPRE6_R          (*((volatile uint32_t *)0x400FE218))
+#define FLASH_FMPRE7_R          (*((volatile uint32_t *)0x400FE21C))
+#define FLASH_FMPRE8_R          (*((volatile uint32_t *)0x400FE220))
+#define FLASH_FMPRE9_R          (*((volatile uint32_t *)0x400FE224))
+#define FLASH_FMPRE10_R         (*((volatile uint32_t *)0x400FE228))
+#define FLASH_FMPRE11_R         (*((volatile uint32_t *)0x400FE22C))
+#define FLASH_FMPRE12_R         (*((volatile uint32_t *)0x400FE230))
+#define FLASH_FMPRE13_R         (*((volatile uint32_t *)0x400FE234))
+#define FLASH_FMPRE14_R         (*((volatile uint32_t *)0x400FE238))
+#define FLASH_FMPRE15_R         (*((volatile uint32_t *)0x400FE23C))
+#define FLASH_FMPPE0_R          (*((volatile uint32_t *)0x400FE400))
+#define FLASH_FMPPE1_R          (*((volatile uint32_t *)0x400FE404))
+#define FLASH_FMPPE2_R          (*((volatile uint32_t *)0x400FE408))
+#define FLASH_FMPPE3_R          (*((volatile uint32_t *)0x400FE40C))
+#define FLASH_FMPPE4_R          (*((volatile uint32_t *)0x400FE410))
+#define FLASH_FMPPE5_R          (*((volatile uint32_t *)0x400FE414))
+#define FLASH_FMPPE6_R          (*((volatile uint32_t *)0x400FE418))
+#define FLASH_FMPPE7_R          (*((volatile uint32_t *)0x400FE41C))
+#define FLASH_FMPPE8_R          (*((volatile uint32_t *)0x400FE420))
+#define FLASH_FMPPE9_R          (*((volatile uint32_t *)0x400FE424))
+#define FLASH_FMPPE10_R         (*((volatile uint32_t *)0x400FE428))
+#define FLASH_FMPPE11_R         (*((volatile uint32_t *)0x400FE42C))
+#define FLASH_FMPPE12_R         (*((volatile uint32_t *)0x400FE430))
+#define FLASH_FMPPE13_R         (*((volatile uint32_t *)0x400FE434))
+#define FLASH_FMPPE14_R         (*((volatile uint32_t *)0x400FE438))
+#define FLASH_FMPPE15_R         (*((volatile uint32_t *)0x400FE43C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R           (*((volatile uint32_t *)0x400FE000))
+#define SYSCTL_DID1_R           (*((volatile uint32_t *)0x400FE004))
+#define SYSCTL_PTBOCTL_R        (*((volatile uint32_t *)0x400FE038))
+#define SYSCTL_RIS_R            (*((volatile uint32_t *)0x400FE050))
+#define SYSCTL_IMC_R            (*((volatile uint32_t *)0x400FE054))
+#define SYSCTL_MISC_R           (*((volatile uint32_t *)0x400FE058))
+#define SYSCTL_RESC_R           (*((volatile uint32_t *)0x400FE05C))
+#define SYSCTL_PWRTC_R          (*((volatile uint32_t *)0x400FE060))
+#define SYSCTL_NMIC_R           (*((volatile uint32_t *)0x400FE064))
+#define SYSCTL_MOSCCTL_R        (*((volatile uint32_t *)0x400FE07C))
+#define SYSCTL_RSCLKCFG_R       (*((volatile uint32_t *)0x400FE0B0))
+#define SYSCTL_MEMTIM0_R        (*((volatile uint32_t *)0x400FE0C0))
+#define SYSCTL_ALTCLKCFG_R      (*((volatile uint32_t *)0x400FE138))
+#define SYSCTL_DSCLKCFG_R       (*((volatile uint32_t *)0x400FE144))
+#define SYSCTL_DIVSCLK_R        (*((volatile uint32_t *)0x400FE148))
+#define SYSCTL_SYSPROP_R        (*((volatile uint32_t *)0x400FE14C))
+#define SYSCTL_PIOSCCAL_R       (*((volatile uint32_t *)0x400FE150))
+#define SYSCTL_PIOSCSTAT_R      (*((volatile uint32_t *)0x400FE154))
+#define SYSCTL_PLLFREQ0_R       (*((volatile uint32_t *)0x400FE160))
+#define SYSCTL_PLLFREQ1_R       (*((volatile uint32_t *)0x400FE164))
+#define SYSCTL_PLLSTAT_R        (*((volatile uint32_t *)0x400FE168))
+#define SYSCTL_SLPPWRCFG_R      (*((volatile uint32_t *)0x400FE188))
+#define SYSCTL_DSLPPWRCFG_R     (*((volatile uint32_t *)0x400FE18C))
+#define SYSCTL_NVMSTAT_R        (*((volatile uint32_t *)0x400FE1A0))
+#define SYSCTL_LDOSPCTL_R       (*((volatile uint32_t *)0x400FE1B4))
+#define SYSCTL_LDODPCTL_R       (*((volatile uint32_t *)0x400FE1BC))
+#define SYSCTL_RESBEHAVCTL_R    (*((volatile uint32_t *)0x400FE1D8))
+#define SYSCTL_HSSR_R           (*((volatile uint32_t *)0x400FE1F4))
+#define SYSCTL_USBPDS_R         (*((volatile uint32_t *)0x400FE280))
+#define SYSCTL_USBMPC_R         (*((volatile uint32_t *)0x400FE284))
+#define SYSCTL_EMACPDS_R        (*((volatile uint32_t *)0x400FE288))
+#define SYSCTL_EMACMPC_R        (*((volatile uint32_t *)0x400FE28C))
+#define SYSCTL_LCDMPC_R         (*((volatile uint32_t *)0x400FE294))
+#define SYSCTL_PPWD_R           (*((volatile uint32_t *)0x400FE300))
+#define SYSCTL_PPTIMER_R        (*((volatile uint32_t *)0x400FE304))
+#define SYSCTL_PPGPIO_R         (*((volatile uint32_t *)0x400FE308))
+#define SYSCTL_PPDMA_R          (*((volatile uint32_t *)0x400FE30C))
+#define SYSCTL_PPEPI_R          (*((volatile uint32_t *)0x400FE310))
+#define SYSCTL_PPHIB_R          (*((volatile uint32_t *)0x400FE314))
+#define SYSCTL_PPUART_R         (*((volatile uint32_t *)0x400FE318))
+#define SYSCTL_PPSSI_R          (*((volatile uint32_t *)0x400FE31C))
+#define SYSCTL_PPI2C_R          (*((volatile uint32_t *)0x400FE320))
+#define SYSCTL_PPUSB_R          (*((volatile uint32_t *)0x400FE328))
+#define SYSCTL_PPEPHY_R         (*((volatile uint32_t *)0x400FE330))
+#define SYSCTL_PPCAN_R          (*((volatile uint32_t *)0x400FE334))
+#define SYSCTL_PPADC_R          (*((volatile uint32_t *)0x400FE338))
+#define SYSCTL_PPACMP_R         (*((volatile uint32_t *)0x400FE33C))
+#define SYSCTL_PPPWM_R          (*((volatile uint32_t *)0x400FE340))
+#define SYSCTL_PPQEI_R          (*((volatile uint32_t *)0x400FE344))
+#define SYSCTL_PPLPC_R          (*((volatile uint32_t *)0x400FE348))
+#define SYSCTL_PPPECI_R         (*((volatile uint32_t *)0x400FE350))
+#define SYSCTL_PPFAN_R          (*((volatile uint32_t *)0x400FE354))
+#define SYSCTL_PPEEPROM_R       (*((volatile uint32_t *)0x400FE358))
+#define SYSCTL_PPWTIMER_R       (*((volatile uint32_t *)0x400FE35C))
+#define SYSCTL_PPRTS_R          (*((volatile uint32_t *)0x400FE370))
+#define SYSCTL_PPCCM_R          (*((volatile uint32_t *)0x400FE374))
+#define SYSCTL_PPLCD_R          (*((volatile uint32_t *)0x400FE390))
+#define SYSCTL_PPOWIRE_R        (*((volatile uint32_t *)0x400FE398))
+#define SYSCTL_PPEMAC_R         (*((volatile uint32_t *)0x400FE39C))
+#define SYSCTL_PPHIM_R          (*((volatile uint32_t *)0x400FE3A4))
+#define SYSCTL_SRWD_R           (*((volatile uint32_t *)0x400FE500))
+#define SYSCTL_SRTIMER_R        (*((volatile uint32_t *)0x400FE504))
+#define SYSCTL_SRGPIO_R         (*((volatile uint32_t *)0x400FE508))
+#define SYSCTL_SRDMA_R          (*((volatile uint32_t *)0x400FE50C))
+#define SYSCTL_SREPI_R          (*((volatile uint32_t *)0x400FE510))
+#define SYSCTL_SRHIB_R          (*((volatile uint32_t *)0x400FE514))
+#define SYSCTL_SRUART_R         (*((volatile uint32_t *)0x400FE518))
+#define SYSCTL_SRSSI_R          (*((volatile uint32_t *)0x400FE51C))
+#define SYSCTL_SRI2C_R          (*((volatile uint32_t *)0x400FE520))
+#define SYSCTL_SRUSB_R          (*((volatile uint32_t *)0x400FE528))
+#define SYSCTL_SREPHY_R         (*((volatile uint32_t *)0x400FE530))
+#define SYSCTL_SRCAN_R          (*((volatile uint32_t *)0x400FE534))
+#define SYSCTL_SRADC_R          (*((volatile uint32_t *)0x400FE538))
+#define SYSCTL_SRACMP_R         (*((volatile uint32_t *)0x400FE53C))
+#define SYSCTL_SRPWM_R          (*((volatile uint32_t *)0x400FE540))
+#define SYSCTL_SRQEI_R          (*((volatile uint32_t *)0x400FE544))
+#define SYSCTL_SREEPROM_R       (*((volatile uint32_t *)0x400FE558))
+#define SYSCTL_SRCCM_R          (*((volatile uint32_t *)0x400FE574))
+#define SYSCTL_SRLCD_R          (*((volatile uint32_t *)0x400FE590))
+#define SYSCTL_SROWIRE_R        (*((volatile uint32_t *)0x400FE598))
+#define SYSCTL_SREMAC_R         (*((volatile uint32_t *)0x400FE59C))
+#define SYSCTL_RCGCWD_R         (*((volatile uint32_t *)0x400FE600))
+#define SYSCTL_RCGCTIMER_R      (*((volatile uint32_t *)0x400FE604))
+#define SYSCTL_RCGCGPIO_R       (*((volatile uint32_t *)0x400FE608))
+#define SYSCTL_RCGCDMA_R        (*((volatile uint32_t *)0x400FE60C))
+#define SYSCTL_RCGCEPI_R        (*((volatile uint32_t *)0x400FE610))
+#define SYSCTL_RCGCHIB_R        (*((volatile uint32_t *)0x400FE614))
+#define SYSCTL_RCGCUART_R       (*((volatile uint32_t *)0x400FE618))
+#define SYSCTL_RCGCSSI_R        (*((volatile uint32_t *)0x400FE61C))
+#define SYSCTL_RCGCI2C_R        (*((volatile uint32_t *)0x400FE620))
+#define SYSCTL_RCGCUSB_R        (*((volatile uint32_t *)0x400FE628))
+#define SYSCTL_RCGCEPHY_R       (*((volatile uint32_t *)0x400FE630))
+#define SYSCTL_RCGCCAN_R        (*((volatile uint32_t *)0x400FE634))
+#define SYSCTL_RCGCADC_R        (*((volatile uint32_t *)0x400FE638))
+#define SYSCTL_RCGCACMP_R       (*((volatile uint32_t *)0x400FE63C))
+#define SYSCTL_RCGCPWM_R        (*((volatile uint32_t *)0x400FE640))
+#define SYSCTL_RCGCQEI_R        (*((volatile uint32_t *)0x400FE644))
+#define SYSCTL_RCGCEEPROM_R     (*((volatile uint32_t *)0x400FE658))
+#define SYSCTL_RCGCCCM_R        (*((volatile uint32_t *)0x400FE674))
+#define SYSCTL_RCGCLCD_R        (*((volatile uint32_t *)0x400FE690))
+#define SYSCTL_RCGCOWIRE_R      (*((volatile uint32_t *)0x400FE698))
+#define SYSCTL_RCGCEMAC_R       (*((volatile uint32_t *)0x400FE69C))
+#define SYSCTL_SCGCWD_R         (*((volatile uint32_t *)0x400FE700))
+#define SYSCTL_SCGCTIMER_R      (*((volatile uint32_t *)0x400FE704))
+#define SYSCTL_SCGCGPIO_R       (*((volatile uint32_t *)0x400FE708))
+#define SYSCTL_SCGCDMA_R        (*((volatile uint32_t *)0x400FE70C))
+#define SYSCTL_SCGCEPI_R        (*((volatile uint32_t *)0x400FE710))
+#define SYSCTL_SCGCHIB_R        (*((volatile uint32_t *)0x400FE714))
+#define SYSCTL_SCGCUART_R       (*((volatile uint32_t *)0x400FE718))
+#define SYSCTL_SCGCSSI_R        (*((volatile uint32_t *)0x400FE71C))
+#define SYSCTL_SCGCI2C_R        (*((volatile uint32_t *)0x400FE720))
+#define SYSCTL_SCGCUSB_R        (*((volatile uint32_t *)0x400FE728))
+#define SYSCTL_SCGCEPHY_R       (*((volatile uint32_t *)0x400FE730))
+#define SYSCTL_SCGCCAN_R        (*((volatile uint32_t *)0x400FE734))
+#define SYSCTL_SCGCADC_R        (*((volatile uint32_t *)0x400FE738))
+#define SYSCTL_SCGCACMP_R       (*((volatile uint32_t *)0x400FE73C))
+#define SYSCTL_SCGCPWM_R        (*((volatile uint32_t *)0x400FE740))
+#define SYSCTL_SCGCQEI_R        (*((volatile uint32_t *)0x400FE744))
+#define SYSCTL_SCGCEEPROM_R     (*((volatile uint32_t *)0x400FE758))
+#define SYSCTL_SCGCCCM_R        (*((volatile uint32_t *)0x400FE774))
+#define SYSCTL_SCGCLCD_R        (*((volatile uint32_t *)0x400FE790))
+#define SYSCTL_SCGCOWIRE_R      (*((volatile uint32_t *)0x400FE798))
+#define SYSCTL_SCGCEMAC_R       (*((volatile uint32_t *)0x400FE79C))
+#define SYSCTL_DCGCWD_R         (*((volatile uint32_t *)0x400FE800))
+#define SYSCTL_DCGCTIMER_R      (*((volatile uint32_t *)0x400FE804))
+#define SYSCTL_DCGCGPIO_R       (*((volatile uint32_t *)0x400FE808))
+#define SYSCTL_DCGCDMA_R        (*((volatile uint32_t *)0x400FE80C))
+#define SYSCTL_DCGCEPI_R        (*((volatile uint32_t *)0x400FE810))
+#define SYSCTL_DCGCHIB_R        (*((volatile uint32_t *)0x400FE814))
+#define SYSCTL_DCGCUART_R       (*((volatile uint32_t *)0x400FE818))
+#define SYSCTL_DCGCSSI_R        (*((volatile uint32_t *)0x400FE81C))
+#define SYSCTL_DCGCI2C_R        (*((volatile uint32_t *)0x400FE820))
+#define SYSCTL_DCGCUSB_R        (*((volatile uint32_t *)0x400FE828))
+#define SYSCTL_DCGCEPHY_R       (*((volatile uint32_t *)0x400FE830))
+#define SYSCTL_DCGCCAN_R        (*((volatile uint32_t *)0x400FE834))
+#define SYSCTL_DCGCADC_R        (*((volatile uint32_t *)0x400FE838))
+#define SYSCTL_DCGCACMP_R       (*((volatile uint32_t *)0x400FE83C))
+#define SYSCTL_DCGCPWM_R        (*((volatile uint32_t *)0x400FE840))
+#define SYSCTL_DCGCQEI_R        (*((volatile uint32_t *)0x400FE844))
+#define SYSCTL_DCGCEEPROM_R     (*((volatile uint32_t *)0x400FE858))
+#define SYSCTL_DCGCCCM_R        (*((volatile uint32_t *)0x400FE874))
+#define SYSCTL_DCGCLCD_R        (*((volatile uint32_t *)0x400FE890))
+#define SYSCTL_DCGCOWIRE_R      (*((volatile uint32_t *)0x400FE898))
+#define SYSCTL_DCGCEMAC_R       (*((volatile uint32_t *)0x400FE89C))
+#define SYSCTL_PCWD_R           (*((volatile uint32_t *)0x400FE900))
+#define SYSCTL_PCTIMER_R        (*((volatile uint32_t *)0x400FE904))
+#define SYSCTL_PCGPIO_R         (*((volatile uint32_t *)0x400FE908))
+#define SYSCTL_PCDMA_R          (*((volatile uint32_t *)0x400FE90C))
+#define SYSCTL_PCEPI_R          (*((volatile uint32_t *)0x400FE910))
+#define SYSCTL_PCHIB_R          (*((volatile uint32_t *)0x400FE914))
+#define SYSCTL_PCUART_R         (*((volatile uint32_t *)0x400FE918))
+#define SYSCTL_PCSSI_R          (*((volatile uint32_t *)0x400FE91C))
+#define SYSCTL_PCI2C_R          (*((volatile uint32_t *)0x400FE920))
+#define SYSCTL_PCUSB_R          (*((volatile uint32_t *)0x400FE928))
+#define SYSCTL_PCEPHY_R         (*((volatile uint32_t *)0x400FE930))
+#define SYSCTL_PCCAN_R          (*((volatile uint32_t *)0x400FE934))
+#define SYSCTL_PCADC_R          (*((volatile uint32_t *)0x400FE938))
+#define SYSCTL_PCACMP_R         (*((volatile uint32_t *)0x400FE93C))
+#define SYSCTL_PCPWM_R          (*((volatile uint32_t *)0x400FE940))
+#define SYSCTL_PCQEI_R          (*((volatile uint32_t *)0x400FE944))
+#define SYSCTL_PCEEPROM_R       (*((volatile uint32_t *)0x400FE958))
+#define SYSCTL_PCCCM_R          (*((volatile uint32_t *)0x400FE974))
+#define SYSCTL_PCLCD_R          (*((volatile uint32_t *)0x400FE990))
+#define SYSCTL_PCOWIRE_R        (*((volatile uint32_t *)0x400FE998))
+#define SYSCTL_PCEMAC_R         (*((volatile uint32_t *)0x400FE99C))
+#define SYSCTL_PRWD_R           (*((volatile uint32_t *)0x400FEA00))
+#define SYSCTL_PRTIMER_R        (*((volatile uint32_t *)0x400FEA04))
+#define SYSCTL_PRGPIO_R         (*((volatile uint32_t *)0x400FEA08))
+#define SYSCTL_PRDMA_R          (*((volatile uint32_t *)0x400FEA0C))
+#define SYSCTL_PREPI_R          (*((volatile uint32_t *)0x400FEA10))
+#define SYSCTL_PRHIB_R          (*((volatile uint32_t *)0x400FEA14))
+#define SYSCTL_PRUART_R         (*((volatile uint32_t *)0x400FEA18))
+#define SYSCTL_PRSSI_R          (*((volatile uint32_t *)0x400FEA1C))
+#define SYSCTL_PRI2C_R          (*((volatile uint32_t *)0x400FEA20))
+#define SYSCTL_PRUSB_R          (*((volatile uint32_t *)0x400FEA28))
+#define SYSCTL_PREPHY_R         (*((volatile uint32_t *)0x400FEA30))
+#define SYSCTL_PRCAN_R          (*((volatile uint32_t *)0x400FEA34))
+#define SYSCTL_PRADC_R          (*((volatile uint32_t *)0x400FEA38))
+#define SYSCTL_PRACMP_R         (*((volatile uint32_t *)0x400FEA3C))
+#define SYSCTL_PRPWM_R          (*((volatile uint32_t *)0x400FEA40))
+#define SYSCTL_PRQEI_R          (*((volatile uint32_t *)0x400FEA44))
+#define SYSCTL_PREEPROM_R       (*((volatile uint32_t *)0x400FEA58))
+#define SYSCTL_PRCCM_R          (*((volatile uint32_t *)0x400FEA74))
+#define SYSCTL_PRLCD_R          (*((volatile uint32_t *)0x400FEA90))
+#define SYSCTL_PROWIRE_R        (*((volatile uint32_t *)0x400FEA98))
+#define SYSCTL_PREMAC_R         (*((volatile uint32_t *)0x400FEA9C))
+#define SYSCTL_CCMCGREQ_R       (*((volatile uint32_t *)0x44030204))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access registers (UDMA)
+//
+//*****************************************************************************
+#define UDMA_STAT_R             (*((volatile uint32_t *)0x400FF000))
+#define UDMA_CFG_R              (*((volatile uint32_t *)0x400FF004))
+#define UDMA_CTLBASE_R          (*((volatile uint32_t *)0x400FF008))
+#define UDMA_ALTBASE_R          (*((volatile uint32_t *)0x400FF00C))
+#define UDMA_WAITSTAT_R         (*((volatile uint32_t *)0x400FF010))
+#define UDMA_SWREQ_R            (*((volatile uint32_t *)0x400FF014))
+#define UDMA_USEBURSTSET_R      (*((volatile uint32_t *)0x400FF018))
+#define UDMA_USEBURSTCLR_R      (*((volatile uint32_t *)0x400FF01C))
+#define UDMA_REQMASKSET_R       (*((volatile uint32_t *)0x400FF020))
+#define UDMA_REQMASKCLR_R       (*((volatile uint32_t *)0x400FF024))
+#define UDMA_ENASET_R           (*((volatile uint32_t *)0x400FF028))
+#define UDMA_ENACLR_R           (*((volatile uint32_t *)0x400FF02C))
+#define UDMA_ALTSET_R           (*((volatile uint32_t *)0x400FF030))
+#define UDMA_ALTCLR_R           (*((volatile uint32_t *)0x400FF034))
+#define UDMA_PRIOSET_R          (*((volatile uint32_t *)0x400FF038))
+#define UDMA_PRIOCLR_R          (*((volatile uint32_t *)0x400FF03C))
+#define UDMA_ERRCLR_R           (*((volatile uint32_t *)0x400FF04C))
+#define UDMA_CHASGN_R           (*((volatile uint32_t *)0x400FF500))
+#define UDMA_CHMAP0_R           (*((volatile uint32_t *)0x400FF510))
+#define UDMA_CHMAP1_R           (*((volatile uint32_t *)0x400FF514))
+#define UDMA_CHMAP2_R           (*((volatile uint32_t *)0x400FF518))
+#define UDMA_CHMAP3_R           (*((volatile uint32_t *)0x400FF51C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets (UDMA)
+//
+//*****************************************************************************
+#define UDMA_SRCENDP            0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_DSTENDP            0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_CHCTL              0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// EC registers (CCM0)
+//
+//*****************************************************************************
+#define CCM0_CRCCTRL_R          (*((volatile uint32_t *)0x44030400))
+#define CCM0_CRCSEED_R          (*((volatile uint32_t *)0x44030410))
+#define CCM0_CRCDIN_R           (*((volatile uint32_t *)0x44030414))
+#define CCM0_CRCRSLTPP_R        (*((volatile uint32_t *)0x44030418))
+
+//*****************************************************************************
+//
+// SHA/MD5 registers (SHAMD5)
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_A_R      (*((volatile uint32_t *)0x44034000))
+#define SHAMD5_ODIGEST_B_R      (*((volatile uint32_t *)0x44034004))
+#define SHAMD5_ODIGEST_C_R      (*((volatile uint32_t *)0x44034008))
+#define SHAMD5_ODIGEST_D_R      (*((volatile uint32_t *)0x4403400C))
+#define SHAMD5_ODIGEST_E_R      (*((volatile uint32_t *)0x44034010))
+#define SHAMD5_ODIGEST_F_R      (*((volatile uint32_t *)0x44034014))
+#define SHAMD5_ODIGEST_G_R      (*((volatile uint32_t *)0x44034018))
+#define SHAMD5_ODIGEST_H_R      (*((volatile uint32_t *)0x4403401C))
+#define SHAMD5_IDIGEST_A_R      (*((volatile uint32_t *)0x44034020))
+#define SHAMD5_IDIGEST_B_R      (*((volatile uint32_t *)0x44034024))
+#define SHAMD5_IDIGEST_C_R      (*((volatile uint32_t *)0x44034028))
+#define SHAMD5_IDIGEST_D_R      (*((volatile uint32_t *)0x4403402C))
+#define SHAMD5_IDIGEST_E_R      (*((volatile uint32_t *)0x44034030))
+#define SHAMD5_IDIGEST_F_R      (*((volatile uint32_t *)0x44034034))
+#define SHAMD5_IDIGEST_G_R      (*((volatile uint32_t *)0x44034038))
+#define SHAMD5_IDIGEST_H_R      (*((volatile uint32_t *)0x4403403C))
+#define SHAMD5_DIGEST_COUNT_R   (*((volatile uint32_t *)0x44034040))
+#define SHAMD5_MODE_R           (*((volatile uint32_t *)0x44034044))
+#define SHAMD5_LENGTH_R         (*((volatile uint32_t *)0x44034048))
+#define SHAMD5_DATA_0_IN_R      (*((volatile uint32_t *)0x44034080))
+#define SHAMD5_DATA_1_IN_R      (*((volatile uint32_t *)0x44034084))
+#define SHAMD5_DATA_2_IN_R      (*((volatile uint32_t *)0x44034088))
+#define SHAMD5_DATA_3_IN_R      (*((volatile uint32_t *)0x4403408C))
+#define SHAMD5_DATA_4_IN_R      (*((volatile uint32_t *)0x44034090))
+#define SHAMD5_DATA_5_IN_R      (*((volatile uint32_t *)0x44034094))
+#define SHAMD5_DATA_6_IN_R      (*((volatile uint32_t *)0x44034098))
+#define SHAMD5_DATA_7_IN_R      (*((volatile uint32_t *)0x4403409C))
+#define SHAMD5_DATA_8_IN_R      (*((volatile uint32_t *)0x440340A0))
+#define SHAMD5_DATA_9_IN_R      (*((volatile uint32_t *)0x440340A4))
+#define SHAMD5_DATA_10_IN_R     (*((volatile uint32_t *)0x440340A8))
+#define SHAMD5_DATA_11_IN_R     (*((volatile uint32_t *)0x440340AC))
+#define SHAMD5_DATA_12_IN_R     (*((volatile uint32_t *)0x440340B0))
+#define SHAMD5_DATA_13_IN_R     (*((volatile uint32_t *)0x440340B4))
+#define SHAMD5_DATA_14_IN_R     (*((volatile uint32_t *)0x440340B8))
+#define SHAMD5_DATA_15_IN_R     (*((volatile uint32_t *)0x440340BC))
+#define SHAMD5_REVISION_R       (*((volatile uint32_t *)0x44034100))
+#define SHAMD5_SYSCONFIG_R      (*((volatile uint32_t *)0x44034110))
+#define SHAMD5_SYSSTATUS_R      (*((volatile uint32_t *)0x44034114))
+#define SHAMD5_IRQSTATUS_R      (*((volatile uint32_t *)0x44034118))
+#define SHAMD5_IRQENABLE_R      (*((volatile uint32_t *)0x4403411C))
+#define SHAMD5_DMAIM_R          (*((volatile uint32_t *)0x144030010))
+#define SHAMD5_DMARIS_R         (*((volatile uint32_t *)0x144030014))
+#define SHAMD5_DMAMIS_R         (*((volatile uint32_t *)0x144030018))
+#define SHAMD5_DMAIC_R          (*((volatile uint32_t *)0x14403001C))
+
+//*****************************************************************************
+//
+// AES registers (AES)
+//
+//*****************************************************************************
+#define AES_KEY2_6_R            (*((volatile uint32_t *)0x44036000))
+#define AES_KEY2_7_R            (*((volatile uint32_t *)0x44036004))
+#define AES_KEY2_4_R            (*((volatile uint32_t *)0x44036008))
+#define AES_KEY2_5_R            (*((volatile uint32_t *)0x4403600C))
+#define AES_KEY2_2_R            (*((volatile uint32_t *)0x44036010))
+#define AES_KEY2_3_R            (*((volatile uint32_t *)0x44036014))
+#define AES_KEY2_0_R            (*((volatile uint32_t *)0x44036018))
+#define AES_KEY2_1_R            (*((volatile uint32_t *)0x4403601C))
+#define AES_KEY1_6_R            (*((volatile uint32_t *)0x44036020))
+#define AES_KEY1_7_R            (*((volatile uint32_t *)0x44036024))
+#define AES_KEY1_4_R            (*((volatile uint32_t *)0x44036028))
+#define AES_KEY1_5_R            (*((volatile uint32_t *)0x4403602C))
+#define AES_KEY1_2_R            (*((volatile uint32_t *)0x44036030))
+#define AES_KEY1_3_R            (*((volatile uint32_t *)0x44036034))
+#define AES_KEY1_0_R            (*((volatile uint32_t *)0x44036038))
+#define AES_KEY1_1_R            (*((volatile uint32_t *)0x4403603C))
+#define AES_IV_IN_0_R           (*((volatile uint32_t *)0x44036040))
+#define AES_IV_IN_1_R           (*((volatile uint32_t *)0x44036044))
+#define AES_IV_IN_2_R           (*((volatile uint32_t *)0x44036048))
+#define AES_IV_IN_3_R           (*((volatile uint32_t *)0x4403604C))
+#define AES_CTRL_R              (*((volatile uint32_t *)0x44036050))
+#define AES_C_LENGTH_0_R        (*((volatile uint32_t *)0x44036054))
+#define AES_C_LENGTH_1_R        (*((volatile uint32_t *)0x44036058))
+#define AES_AUTH_LENGTH_R       (*((volatile uint32_t *)0x4403605C))
+#define AES_DATA_IN_0_R         (*((volatile uint32_t *)0x44036060))
+#define AES_DATA_IN_1_R         (*((volatile uint32_t *)0x44036064))
+#define AES_DATA_IN_2_R         (*((volatile uint32_t *)0x44036068))
+#define AES_DATA_IN_3_R         (*((volatile uint32_t *)0x4403606C))
+#define AES_TAG_OUT_0_R         (*((volatile uint32_t *)0x44036070))
+#define AES_TAG_OUT_1_R         (*((volatile uint32_t *)0x44036074))
+#define AES_TAG_OUT_2_R         (*((volatile uint32_t *)0x44036078))
+#define AES_TAG_OUT_3_R         (*((volatile uint32_t *)0x4403607C))
+#define AES_REVISION_R          (*((volatile uint32_t *)0x44036080))
+#define AES_SYSCONFIG_R         (*((volatile uint32_t *)0x44036084))
+#define AES_SYSSTATUS_R         (*((volatile uint32_t *)0x44036088))
+#define AES_IRQSTATUS_R         (*((volatile uint32_t *)0x4403608C))
+#define AES_IRQENABLE_R         (*((volatile uint32_t *)0x44036090))
+#define AES_DIRTYBITS_R         (*((volatile uint32_t *)0x44036094))
+#define AES_DMAIM_R             (*((volatile uint32_t *)0x144030020))
+#define AES_DMARIS_R            (*((volatile uint32_t *)0x144030024))
+#define AES_DMAMIS_R            (*((volatile uint32_t *)0x144030028))
+#define AES_DMAIC_R             (*((volatile uint32_t *)0x14403002C))
+
+//*****************************************************************************
+//
+// DES registers (DES)
+//
+//*****************************************************************************
+#define DES_KEY3_L_R            (*((volatile uint32_t *)0x44038000))
+#define DES_KEY3_H_R            (*((volatile uint32_t *)0x44038004))
+#define DES_KEY2_L_R            (*((volatile uint32_t *)0x44038008))
+#define DES_KEY2_H_R            (*((volatile uint32_t *)0x4403800C))
+#define DES_KEY1_L_R            (*((volatile uint32_t *)0x44038010))
+#define DES_KEY1_H_R            (*((volatile uint32_t *)0x44038014))
+#define DES_IV_L_R              (*((volatile uint32_t *)0x44038018))
+#define DES_IV_H_R              (*((volatile uint32_t *)0x4403801C))
+#define DES_CTRL_R              (*((volatile uint32_t *)0x44038020))
+#define DES_LENGTH_R            (*((volatile uint32_t *)0x44038024))
+#define DES_DATA_L_R            (*((volatile uint32_t *)0x44038028))
+#define DES_DATA_H_R            (*((volatile uint32_t *)0x4403802C))
+#define DES_REVISION_R          (*((volatile uint32_t *)0x44038030))
+#define DES_SYSCONFIG_R         (*((volatile uint32_t *)0x44038034))
+#define DES_SYSSTATUS_R         (*((volatile uint32_t *)0x44038038))
+#define DES_IRQSTATUS_R         (*((volatile uint32_t *)0x4403803C))
+#define DES_IRQENABLE_R         (*((volatile uint32_t *)0x44038040))
+#define DES_DIRTYBITS_R         (*((volatile uint32_t *)0x44038044))
+#define DES_DMAIM_R             (*((volatile uint32_t *)0x144030030))
+#define DES_DMARIS_R            (*((volatile uint32_t *)0x144030034))
+#define DES_DMAMIS_R            (*((volatile uint32_t *)0x144030038))
+#define DES_DMAIC_R             (*((volatile uint32_t *)0x14403003C))
+
+//*****************************************************************************
+//
+// LCD registers (LCD0)
+//
+//*****************************************************************************
+#define LCD0_PID_R              (*((volatile uint32_t *)0x44050000))
+#define LCD0_CTL_R              (*((volatile uint32_t *)0x44050004))
+#define LCD0_LIDDCTL_R          (*((volatile uint32_t *)0x4405000C))
+#define LCD0_LIDDCS0CFG_R       (*((volatile uint32_t *)0x44050010))
+#define LCD0_LIDDCS0ADDR_R      (*((volatile uint32_t *)0x44050014))
+#define LCD0_LIDDCS0DATA_R      (*((volatile uint32_t *)0x44050018))
+#define LCD0_LIDDCS1CFG_R       (*((volatile uint32_t *)0x4405001C))
+#define LCD0_LIDDCS1ADDR_R      (*((volatile uint32_t *)0x44050020))
+#define LCD0_LIDDCS1DATA_R      (*((volatile uint32_t *)0x44050024))
+#define LCD0_RASTRCTL_R         (*((volatile uint32_t *)0x44050028))
+#define LCD0_RASTRTIM0_R        (*((volatile uint32_t *)0x4405002C))
+#define LCD0_RASTRTIM1_R        (*((volatile uint32_t *)0x44050030))
+#define LCD0_RASTRTIM2_R        (*((volatile uint32_t *)0x44050034))
+#define LCD0_RASTRSUBP1_R       (*((volatile uint32_t *)0x44050038))
+#define LCD0_RASTRSUBP2_R       (*((volatile uint32_t *)0x4405003C))
+#define LCD0_DMACTL_R           (*((volatile uint32_t *)0x44050040))
+#define LCD0_DMABAFB0_R         (*((volatile uint32_t *)0x44050044))
+#define LCD0_DMACAFB0_R         (*((volatile uint32_t *)0x44050048))
+#define LCD0_DMABAFB1_R         (*((volatile uint32_t *)0x4405004C))
+#define LCD0_DMACAFB1_R         (*((volatile uint32_t *)0x44050050))
+#define LCD0_SYSCFG_R           (*((volatile uint32_t *)0x44050054))
+#define LCD0_RISSET_R           (*((volatile uint32_t *)0x44050058))
+#define LCD0_MISCLR_R           (*((volatile uint32_t *)0x4405005C))
+#define LCD0_IM_R               (*((volatile uint32_t *)0x44050060))
+#define LCD0_IENC_R             (*((volatile uint32_t *)0x44050064))
+#define LCD0_CLKEN_R            (*((volatile uint32_t *)0x4405006C))
+#define LCD0_CLKRESET_R         (*((volatile uint32_t *)0x44050070))
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_ACTLR_R            (*((volatile uint32_t *)0xE000E008))
+#define NVIC_ST_CTRL_R          (*((volatile uint32_t *)0xE000E010))
+#define NVIC_ST_RELOAD_R        (*((volatile uint32_t *)0xE000E014))
+#define NVIC_ST_CURRENT_R       (*((volatile uint32_t *)0xE000E018))
+#define NVIC_EN0_R              (*((volatile uint32_t *)0xE000E100))
+#define NVIC_EN1_R              (*((volatile uint32_t *)0xE000E104))
+#define NVIC_EN2_R              (*((volatile uint32_t *)0xE000E108))
+#define NVIC_EN3_R              (*((volatile uint32_t *)0xE000E10C))
+#define NVIC_DIS0_R             (*((volatile uint32_t *)0xE000E180))
+#define NVIC_DIS1_R             (*((volatile uint32_t *)0xE000E184))
+#define NVIC_DIS2_R             (*((volatile uint32_t *)0xE000E188))
+#define NVIC_DIS3_R             (*((volatile uint32_t *)0xE000E18C))
+#define NVIC_PEND0_R            (*((volatile uint32_t *)0xE000E200))
+#define NVIC_PEND1_R            (*((volatile uint32_t *)0xE000E204))
+#define NVIC_PEND2_R            (*((volatile uint32_t *)0xE000E208))
+#define NVIC_PEND3_R            (*((volatile uint32_t *)0xE000E20C))
+#define NVIC_UNPEND0_R          (*((volatile uint32_t *)0xE000E280))
+#define NVIC_UNPEND1_R          (*((volatile uint32_t *)0xE000E284))
+#define NVIC_UNPEND2_R          (*((volatile uint32_t *)0xE000E288))
+#define NVIC_UNPEND3_R          (*((volatile uint32_t *)0xE000E28C))
+#define NVIC_ACTIVE0_R          (*((volatile uint32_t *)0xE000E300))
+#define NVIC_ACTIVE1_R          (*((volatile uint32_t *)0xE000E304))
+#define NVIC_ACTIVE2_R          (*((volatile uint32_t *)0xE000E308))
+#define NVIC_ACTIVE3_R          (*((volatile uint32_t *)0xE000E30C))
+#define NVIC_PRI0_R             (*((volatile uint32_t *)0xE000E400))
+#define NVIC_PRI1_R             (*((volatile uint32_t *)0xE000E404))
+#define NVIC_PRI2_R             (*((volatile uint32_t *)0xE000E408))
+#define NVIC_PRI3_R             (*((volatile uint32_t *)0xE000E40C))
+#define NVIC_PRI4_R             (*((volatile uint32_t *)0xE000E410))
+#define NVIC_PRI5_R             (*((volatile uint32_t *)0xE000E414))
+#define NVIC_PRI6_R             (*((volatile uint32_t *)0xE000E418))
+#define NVIC_PRI7_R             (*((volatile uint32_t *)0xE000E41C))
+#define NVIC_PRI8_R             (*((volatile uint32_t *)0xE000E420))
+#define NVIC_PRI9_R             (*((volatile uint32_t *)0xE000E424))
+#define NVIC_PRI10_R            (*((volatile uint32_t *)0xE000E428))
+#define NVIC_PRI11_R            (*((volatile uint32_t *)0xE000E42C))
+#define NVIC_PRI12_R            (*((volatile uint32_t *)0xE000E430))
+#define NVIC_PRI13_R            (*((volatile uint32_t *)0xE000E434))
+#define NVIC_PRI14_R            (*((volatile uint32_t *)0xE000E438))
+#define NVIC_PRI15_R            (*((volatile uint32_t *)0xE000E43C))
+#define NVIC_PRI16_R            (*((volatile uint32_t *)0xE000E440))
+#define NVIC_PRI17_R            (*((volatile uint32_t *)0xE000E444))
+#define NVIC_PRI18_R            (*((volatile uint32_t *)0xE000E448))
+#define NVIC_PRI19_R            (*((volatile uint32_t *)0xE000E44C))
+#define NVIC_PRI20_R            (*((volatile uint32_t *)0xE000E450))
+#define NVIC_PRI21_R            (*((volatile uint32_t *)0xE000E454))
+#define NVIC_PRI22_R            (*((volatile uint32_t *)0xE000E458))
+#define NVIC_PRI23_R            (*((volatile uint32_t *)0xE000E45C))
+#define NVIC_PRI24_R            (*((volatile uint32_t *)0xE000E460))
+#define NVIC_PRI25_R            (*((volatile uint32_t *)0xE000E464))
+#define NVIC_PRI26_R            (*((volatile uint32_t *)0xE000E468))
+#define NVIC_PRI27_R            (*((volatile uint32_t *)0xE000E46C))
+#define NVIC_PRI28_R            (*((volatile uint32_t *)0xE000E470))
+#define NVIC_CPUID_R            (*((volatile uint32_t *)0xE000ED00))
+#define NVIC_INT_CTRL_R         (*((volatile uint32_t *)0xE000ED04))
+#define NVIC_VTABLE_R           (*((volatile uint32_t *)0xE000ED08))
+#define NVIC_APINT_R            (*((volatile uint32_t *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R         (*((volatile uint32_t *)0xE000ED10))
+#define NVIC_CFG_CTRL_R         (*((volatile uint32_t *)0xE000ED14))
+#define NVIC_SYS_PRI1_R         (*((volatile uint32_t *)0xE000ED18))
+#define NVIC_SYS_PRI2_R         (*((volatile uint32_t *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R         (*((volatile uint32_t *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R     (*((volatile uint32_t *)0xE000ED24))
+#define NVIC_FAULT_STAT_R       (*((volatile uint32_t *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R      (*((volatile uint32_t *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R       (*((volatile uint32_t *)0xE000ED30))
+#define NVIC_MM_ADDR_R          (*((volatile uint32_t *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R       (*((volatile uint32_t *)0xE000ED38))
+#define NVIC_CPAC_R             (*((volatile uint32_t *)0xE000ED88))
+#define NVIC_MPU_TYPE_R         (*((volatile uint32_t *)0xE000ED90))
+#define NVIC_MPU_CTRL_R         (*((volatile uint32_t *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R       (*((volatile uint32_t *)0xE000ED98))
+#define NVIC_MPU_BASE_R         (*((volatile uint32_t *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R         (*((volatile uint32_t *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile uint32_t *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile uint32_t *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile uint32_t *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile uint32_t *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile uint32_t *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile uint32_t *)0xE000EDB8))
+#define NVIC_DBG_CTRL_R         (*((volatile uint32_t *)0xE000EDF0))
+#define NVIC_DBG_XFER_R         (*((volatile uint32_t *)0xE000EDF4))
+#define NVIC_DBG_DATA_R         (*((volatile uint32_t *)0xE000EDF8))
+#define NVIC_DBG_INT_R          (*((volatile uint32_t *)0xE000EDFC))
+#define NVIC_SW_TRIG_R          (*((volatile uint32_t *)0xE000EF00))
+#define NVIC_FPCC_R             (*((volatile uint32_t *)0xE000EF34))
+#define NVIC_FPCA_R             (*((volatile uint32_t *)0xE000EF38))
+#define NVIC_FPDSC_R            (*((volatile uint32_t *)0xE000EF3C))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Synchronous Serial Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOM             0x00000800  // Stop Frame (End of Message)
+#define SSI_CR1_FSSHLDFRM       0x00000400  // FSS Hold Frame
+#define SSI_CR1_HSCLKEN         0x00000200  // High Speed Clock Enable
+#define SSI_CR1_DIR             0x00000100  // SSI Direction of Operation
+#define SSI_CR1_MODE_M          0x000000C0  // SSI Mode
+#define SSI_CR1_MODE_LEGACY     0x00000000  // Legacy SSI mode
+#define SSI_CR1_MODE_BI         0x00000040  // Bi-SSI mode
+#define SSI_CR1_MODE_QUAD       0x00000080  // Quad-SSI Mode
+#define SSI_CR1_MODE_ADVANCED   0x000000C0  // Advanced SSI Mode with 8-bit
+                                            // packet size
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_EOTIM            0x00000040  // End of Transmit Interrupt Mask
+#define SSI_IM_DMATXIM          0x00000020  // SSI Transmit DMA Interrupt Mask
+#define SSI_IM_DMARXIM          0x00000010  // SSI Receive DMA Interrupt Mask
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_EOTRIS          0x00000040  // End of Transmit Raw Interrupt
+                                            // Status
+#define SSI_RIS_DMATXRIS        0x00000020  // SSI Transmit DMA Raw Interrupt
+                                            // Status
+#define SSI_RIS_DMARXRIS        0x00000010  // SSI Receive DMA Raw Interrupt
+                                            // Status
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_EOTMIS          0x00000040  // End of Transmit Masked Interrupt
+                                            // Status
+#define SSI_MIS_DMATXMIS        0x00000020  // SSI Transmit DMA Masked
+                                            // Interrupt Status
+#define SSI_MIS_DMARXMIS        0x00000010  // SSI Receive DMA Masked Interrupt
+                                            // Status
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_EOTIC           0x00000040  // End of Transmit Interrupt Clear
+#define SSI_ICR_DMATXIC         0x00000020  // SSI Transmit DMA Interrupt Clear
+#define SSI_ICR_DMARXIC         0x00000010  // SSI Receive DMA Interrupt Clear
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_PP register.
+//
+//*****************************************************************************
+#define SSI_PP_FSSHLDFRM        0x00000008  // FSS Hold Frame Capability
+#define SSI_PP_MODE_M           0x00000006  // Mode of Operation
+#define SSI_PP_MODE_LEGACY      0x00000000  // Legacy SSI mode
+#define SSI_PP_MODE_ADVBI       0x00000002  // Legacy mode, Advanced SSI mode
+                                            // and Bi-SSI mode enabled
+#define SSI_PP_MODE_ADVBIQUAD   0x00000004  // Legacy mode, Advanced mode,
+                                            // Bi-SSI and Quad-SSI mode enabled
+#define SSI_PP_HSCLK            0x00000001  // High Speed Capability
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL        0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define SSI_CC_CS_PIOSC         0x00000005  // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_DMATXIM         0x00020000  // Transmit DMA Interrupt Mask
+#define UART_IM_DMARXIM         0x00010000  // Receive DMA Interrupt Mask
+#define UART_IM_9BITIM          0x00001000  // 9-Bit Mode Interrupt Mask
+#define UART_IM_EOTIM           0x00000800  // End of Transmission Interrupt
+                                            // Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Mask
+#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Mask
+#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Mask
+#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_DMATXRIS       0x00020000  // Transmit DMA Raw Interrupt
+                                            // Status
+#define UART_RIS_DMARXRIS       0x00010000  // Receive DMA Raw Interrupt Status
+#define UART_RIS_9BITRIS        0x00001000  // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_EOTRIS         0x00000800  // End of Transmission Raw
+                                            // Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
+#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_DMATXMIS       0x00020000  // Transmit DMA Masked Interrupt
+                                            // Status
+#define UART_MIS_DMARXMIS       0x00010000  // Receive DMA Masked Interrupt
+                                            // Status
+#define UART_MIS_9BITMIS        0x00001000  // 9-Bit Mode Masked Interrupt
+                                            // Status
+#define UART_MIS_EOTMIS         0x00000800  // End of Transmission Masked
+                                            // Interrupt Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
+#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_DMATXIC        0x00020000  // Transmit DMA Interrupt Clear
+#define UART_ICR_DMARXIC        0x00010000  // Receive DMA Interrupt Clear
+#define UART_ICR_9BITIC         0x00001000  // 9-Bit Mode Interrupt Clear
+#define UART_ICR_EOTIC          0x00000800  // End of Transmission Interrupt
+                                            // Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
+#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Clear
+#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN    0x00008000  // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M    0x000000FF  // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M   0x000000FF  // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_MSE             0x00000008  // Modem Support Extended
+#define UART_PP_MS              0x00000004  // Modem Support
+#define UART_PP_NB              0x00000002  // 9-Bit Support
+#define UART_PP_SC              0x00000001  // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M            0x0000000F  // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK       0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define UART_CC_CS_PIOSC        0x00000005  // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_ACTDMARX        0x80000000  // DMA RX Active Status
+#define I2C_MCS_ACTDMATX        0x40000000  // DMA TX Active Status
+#define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error
+#define I2C_MCS_BURST           0x00000040  // Burst Enable
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_QCMD            0x00000020  // Quick Command
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_HS              0x00000010  // High-Speed Enable
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // This byte contains the data
+                                            // transferred during a transaction
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_PULSEL_M       0x00070000  // Glitch Suppression Pulse Width
+#define I2C_MTPR_PULSEL_BYPASS  0x00000000  // Bypass
+#define I2C_MTPR_PULSEL_1       0x00010000  // 1 clock
+#define I2C_MTPR_PULSEL_2       0x00020000  // 2 clocks
+#define I2C_MTPR_PULSEL_3       0x00030000  // 3 clocks
+#define I2C_MTPR_PULSEL_4       0x00040000  // 4 clocks
+#define I2C_MTPR_PULSEL_8       0x00050000  // 8 clocks
+#define I2C_MTPR_PULSEL_16      0x00060000  // 16 clocks
+#define I2C_MTPR_PULSEL_31      0x00070000  // 31 clocks
+#define I2C_MTPR_HS             0x00000080  // High-Speed Enable
+#define I2C_MTPR_TPR_M          0x0000007F  // Timer Period
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_RXFFIM         0x00000800  // Receive FIFO Full Interrupt Mask
+#define I2C_MIMR_TXFEIM         0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_MIMR_RXIM           0x00000200  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_MIMR_TXIM           0x00000100  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_MIMR_ARBLOSTIM      0x00000080  // Arbitration Lost Interrupt Mask
+#define I2C_MIMR_STOPIM         0x00000040  // STOP Detection Interrupt Mask
+#define I2C_MIMR_STARTIM        0x00000020  // START Detection Interrupt Mask
+#define I2C_MIMR_NACKIM         0x00000010  // Address/Data NACK Interrupt Mask
+#define I2C_MIMR_DMATXIM        0x00000008  // Transmit DMA Interrupt Mask
+#define I2C_MIMR_DMARXIM        0x00000004  // Receive DMA Interrupt Mask
+#define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RXFFRIS        0x00000800  // Receive FIFO Full Raw Interrupt
+                                            // Status
+#define I2C_MRIS_TXFERIS        0x00000400  // Transmit FIFO Empty Raw
+                                            // Interrupt Status
+#define I2C_MRIS_RXRIS          0x00000200  // Receive FIFO Request Raw
+                                            // Interrupt Status
+#define I2C_MRIS_TXRIS          0x00000100  // Transmit Request Raw Interrupt
+                                            // Status
+#define I2C_MRIS_ARBLOSTRIS     0x00000080  // Arbitration Lost Raw Interrupt
+                                            // Status
+#define I2C_MRIS_STOPRIS        0x00000040  // STOP Detection Raw Interrupt
+                                            // Status
+#define I2C_MRIS_STARTRIS       0x00000020  // START Detection Raw Interrupt
+                                            // Status
+#define I2C_MRIS_NACKRIS        0x00000010  // Address/Data NACK Raw Interrupt
+                                            // Status
+#define I2C_MRIS_DMATXRIS       0x00000008  // Transmit DMA Raw Interrupt
+                                            // Status
+#define I2C_MRIS_DMARXRIS       0x00000004  // Receive DMA Raw Interrupt Status
+#define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt
+                                            // Status
+#define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_RXFFMIS        0x00000800  // Receive FIFO Full Interrupt Mask
+#define I2C_MMIS_TXFEMIS        0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_MMIS_RXMIS          0x00000200  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_MMIS_TXMIS          0x00000100  // Transmit Request Interrupt Mask
+#define I2C_MMIS_ARBLOSTMIS     0x00000080  // Arbitration Lost Interrupt Mask
+#define I2C_MMIS_STOPMIS        0x00000040  // STOP Detection Interrupt Mask
+#define I2C_MMIS_STARTMIS       0x00000020  // START Detection Interrupt Mask
+#define I2C_MMIS_NACKMIS        0x00000010  // Address/Data NACK Interrupt Mask
+#define I2C_MMIS_DMATXMIS       0x00000008  // Transmit DMA Interrupt Status
+#define I2C_MMIS_DMARXMIS       0x00000004  // Receive DMA Interrupt Status
+#define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt
+                                            // Status
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_RXFFIC         0x00000800  // Receive FIFO Full Interrupt
+                                            // Clear
+#define I2C_MICR_TXFEIC         0x00000400  // Transmit FIFO Empty Interrupt
+                                            // Clear
+#define I2C_MICR_RXIC           0x00000200  // Receive FIFO Request Interrupt
+                                            // Clear
+#define I2C_MICR_TXIC           0x00000100  // Transmit FIFO Request Interrupt
+                                            // Clear
+#define I2C_MICR_ARBLOSTIC      0x00000080  // Arbitration Lost Interrupt Clear
+#define I2C_MICR_STOPIC         0x00000040  // STOP Detection Interrupt Clear
+#define I2C_MICR_STARTIC        0x00000020  // START Detection Interrupt Clear
+#define I2C_MICR_NACKIC         0x00000010  // Address/Data NACK Interrupt
+                                            // Clear
+#define I2C_MICR_DMATXIC        0x00000008  // Transmit DMA Interrupt Clear
+#define I2C_MICR_DMARXIC        0x00000004  // Receive DMA Interrupt Clear
+#define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC             0x00000001  // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M     0x000000FF  // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA           0x00000002  // I2C SDA Status
+#define I2C_MBMON_SCL           0x00000001  // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBLEN register.
+//
+//*****************************************************************************
+#define I2C_MBLEN_CNTL_M        0x000000FF  // I2C Burst Length
+#define I2C_MBLEN_CNTL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBCNT register.
+//
+//*****************************************************************************
+#define I2C_MBCNT_CNTL_M        0x000000FF  // I2C Master Burst Count
+#define I2C_MBCNT_CNTL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_ACTDMARX       0x80000000  // DMA RX Active Status
+#define I2C_SCSR_ACTDMATX       0x40000000  // DMA TX Active Status
+#define I2C_SCSR_QCMDRW         0x00000020  // Quick Command Read / Write
+#define I2C_SCSR_QCMDST         0x00000010  // Quick Command Status
+#define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_RXFIFO         0x00000004  // RX FIFO Enable
+#define I2C_SCSR_TXFIFO         0x00000002  // TX FIFO Enable
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_RXFFIM         0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SIMR_TXFEIM         0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SIMR_RXIM           0x00000040  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_SIMR_TXIM           0x00000020  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_SIMR_DMATXIM        0x00000010  // Transmit DMA Interrupt Mask
+#define I2C_SIMR_DMARXIM        0x00000008  // Receive DMA Interrupt Mask
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RXFFRIS        0x00000100  // Receive FIFO Full Raw Interrupt
+                                            // Status
+#define I2C_SRIS_TXFERIS        0x00000080  // Transmit FIFO Empty Raw
+                                            // Interrupt Status
+#define I2C_SRIS_RXRIS          0x00000040  // Receive FIFO Request Raw
+                                            // Interrupt Status
+#define I2C_SRIS_TXRIS          0x00000020  // Transmit Request Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DMATXRIS       0x00000010  // Transmit DMA Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DMARXRIS       0x00000008  // Receive DMA Raw Interrupt Status
+#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_RXFFMIS        0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SMIS_TXFEMIS        0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SMIS_RXMIS          0x00000040  // Receive FIFO Request Interrupt
+                                            // Mask
+#define I2C_SMIS_TXMIS          0x00000020  // Transmit FIFO Request Interrupt
+                                            // Mask
+#define I2C_SMIS_DMATXMIS       0x00000010  // Transmit DMA Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DMARXMIS       0x00000008  // Receive DMA Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_RXFFIC         0x00000100  // Receive FIFO Full Interrupt Mask
+#define I2C_SICR_TXFEIC         0x00000080  // Transmit FIFO Empty Interrupt
+                                            // Mask
+#define I2C_SICR_RXIC           0x00000040  // Receive Request Interrupt Mask
+#define I2C_SICR_TXIC           0x00000020  // Transmit Request Interrupt Mask
+#define I2C_SICR_DMATXIC        0x00000010  // Transmit DMA Interrupt Clear
+#define I2C_SICR_DMARXIC        0x00000008  // Receive DMA Interrupt Clear
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M        0x0000007F  // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFODATA register.
+//
+//*****************************************************************************
+#define I2C_FIFODATA_DATA_M     0x000000FF  // I2C TX FIFO Write Data Byte
+#define I2C_FIFODATA_DATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
+//
+//*****************************************************************************
+#define I2C_FIFOCTL_RXASGNMT    0x80000000  // RX Control Assignment
+#define I2C_FIFOCTL_RXFLUSH     0x40000000  // RX FIFO Flush
+#define I2C_FIFOCTL_DMARXENA    0x20000000  // DMA RX Channel Enable
+#define I2C_FIFOCTL_RXTRIG_M    0x00070000  // RX FIFO Trigger
+#define I2C_FIFOCTL_TXASGNMT    0x00008000  // TX Control Assignment
+#define I2C_FIFOCTL_TXFLUSH     0x00004000  // TX FIFO Flush
+#define I2C_FIFOCTL_DMATXENA    0x00002000  // DMA TX Channel Enable
+#define I2C_FIFOCTL_TXTRIG_M    0x00000007  // TX FIFO Trigger
+#define I2C_FIFOCTL_RXTRIG_S    16
+#define I2C_FIFOCTL_TXTRIG_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOSTATUS
+// register.
+//
+//*****************************************************************************
+#define I2C_FIFOSTATUS_RXABVTRIG                                              \
+                                0x00040000  // RX FIFO Above Trigger Level
+#define I2C_FIFOSTATUS_RXFF     0x00020000  // RX FIFO Full
+#define I2C_FIFOSTATUS_RXFE     0x00010000  // RX FIFO Empty
+#define I2C_FIFOSTATUS_TXBLWTRIG                                              \
+                                0x00000004  // TX FIFO Below Trigger Level
+#define I2C_FIFOSTATUS_TXFF     0x00000002  // TX FIFO Full
+#define I2C_FIFOSTATUS_TXFE     0x00000001  // TX FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS               0x00000001  // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS               0x00000001  // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // MnPWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // MnPWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // MnPWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // MnPWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // MnPWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // MnPWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // MnPWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // MnPWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert MnPWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert MnPWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert MnPWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert MnPWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert MnPWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert MnPWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert MnPWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert MnPWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // MnPWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // MnPWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // MnPWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // MnPWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // MnPWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // MnPWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // MnPWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // MnPWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // MnPWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // MnPWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // MnPWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // MnPWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // MnPWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // MnPWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // MnPWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // MnPWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // MnPWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // MnPWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // MnPWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // MnPWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // MnPWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // MnPWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // MnPWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // MnPWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_0_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_0_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_0_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_0_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_0_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_0_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_0_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_0_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_0_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_0_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_0_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_0_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_0_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_0_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_0_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_0_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_0_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_0_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_0_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_0_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_0_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_0_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_1_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_1_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_1_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_1_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_1_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_1_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_1_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_1_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_1_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_1_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_1_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_1_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_1_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_1_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_1_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_1_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_1_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_1_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_1_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_1_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_1_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_2_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_2_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_2_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_2_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_2_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_2_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_2_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_2_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_2_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_2_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_2_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_2_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_2_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_2_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_2_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_2_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_2_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_2_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_2_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_2_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_2_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_2_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_3_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_3_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_3_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_3_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_3_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_3_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_3_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_3_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_3_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_3_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_3_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_3_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_3_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_3_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_3_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_3_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_3_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_3_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_3_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_3_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_3_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_3_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_3_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_3_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_ONE              0x00000400  // One-Shot Mode
+#define PWM_PP_EFAULT           0x00000200  // Extended Fault
+#define PWM_PP_ESYNC            0x00000100  // Extended Synchronization
+#define PWM_PP_FCNT_M           0x000000F0  // Fault Inputs (per PWM unit)
+#define PWM_PP_GCNT_M           0x0000000F  // Generators
+#define PWM_PP_FCNT_S           4
+#define PWM_PP_GCNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CC register.
+//
+//*****************************************************************************
+#define PWM_CC_USEPWM           0x00000100  // Use PWM Clock Divisor
+#define PWM_CC_PWMDIV_M         0x00000007  // PWM Clock Divider
+#define PWM_CC_PWMDIV_2         0x00000000  // /2
+#define PWM_CC_PWMDIV_4         0x00000001  // /4
+#define PWM_CC_PWMDIV_8         0x00000002  // /8
+#define PWM_CC_PWMDIV_16        0x00000003  // /16
+#define PWM_CC_PWMDIV_32        0x00000004  // /32
+#define PWM_CC_PWMDIV_64        0x00000005  // /64
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit timer
+                                            // configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit
+                                            // real-time clock (RTC) counter
+                                            // configuration
+#define TIMER_CFG_16_BIT        0x00000004  // For a 16/32-bit timer, this
+                                            // value selects the 16-bit timer
+                                            // configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TCACT_M      0x0000E000  // Timer Compare Action Select
+#define TIMER_TAMR_TCACT_NONE   0x00000000  // Disable compare operations
+#define TIMER_TAMR_TCACT_TOGGLE 0x00002000  // Toggle State on Time-Out
+#define TIMER_TAMR_TCACT_CLRTO  0x00004000  // Clear CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTO  0x00006000  // Set CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTOGTO                                             \
+                                0x00008000  // Set CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TAMR_TCACT_CLRTOGTO                                             \
+                                0x0000A000  // Clear CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TAMR_TCACT_SETCLRTO                                             \
+                                0x0000C000  // Set CCP immediately and clear on
+                                            // Time-Out
+#define TIMER_TAMR_TCACT_CLRSETTO                                             \
+                                0x0000E000  // Clear CCP immediately and set on
+                                            // Time-Out
+#define TIMER_TAMR_TACINTD      0x00001000  // One-shot/Periodic Interrupt
+                                            // Disable
+#define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
+                                            // Operation
+#define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
+                                            // Update
+#define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
+                                            // Enable
+#define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TCACT_M      0x0000E000  // Timer Compare Action Select
+#define TIMER_TBMR_TCACT_NONE   0x00000000  // Disable compare operations
+#define TIMER_TBMR_TCACT_TOGGLE 0x00002000  // Toggle State on Time-Out
+#define TIMER_TBMR_TCACT_CLRTO  0x00004000  // Clear CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTO  0x00006000  // Set CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTOGTO                                             \
+                                0x00008000  // Set CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TBMR_TCACT_CLRTOGTO                                             \
+                                0x0000A000  // Clear CCP immediately and toggle
+                                            // on Time-Out
+#define TIMER_TBMR_TCACT_SETCLRTO                                             \
+                                0x0000C000  // Set CCP immediately and clear on
+                                            // Time-Out
+#define TIMER_TBMR_TCACT_CLRSETTO                                             \
+                                0x0000E000  // Clear CCP immediately and set on
+                                            // Time-Out
+#define TIMER_TBMR_TBCINTD      0x00001000  // One-Shot/Periodic Interrupt
+                                            // Disable
+#define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
+                                            // Operation
+#define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
+                                            // Update
+#define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCT7_M     0x0000C000  // Synchronize GPTM Timer 7
+#define TIMER_SYNC_SYNCT7_NONE  0x00000000  // GPT7 is not affected
+#define TIMER_SYNC_SYNCT7_TA    0x00004000  // A timeout event for Timer A of
+                                            // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TB    0x00008000  // A timeout event for Timer B of
+                                            // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TATB  0x0000C000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM7 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT6_M     0x00003000  // Synchronize GPTM Timer 6
+#define TIMER_SYNC_SYNCT6_NONE  0x00000000  // GPTM6 is not affected
+#define TIMER_SYNC_SYNCT6_TA    0x00001000  // A timeout event for Timer A of
+                                            // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TB    0x00002000  // A timeout event for Timer B of
+                                            // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TATB  0x00003000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM6 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT5_M     0x00000C00  // Synchronize GPTM Timer 5
+#define TIMER_SYNC_SYNCT5_NONE  0x00000000  // GPTM5 is not affected
+#define TIMER_SYNC_SYNCT5_TA    0x00000400  // A timeout event for Timer A of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TB    0x00000800  // A timeout event for Timer B of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TATB  0x00000C00  // A timeout event for both Timer A
+                                            // and Timer B of GPTM5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT4_M     0x00000300  // Synchronize GPTM Timer 4
+#define TIMER_SYNC_SYNCT4_NONE  0x00000000  // GPTM4 is not affected
+#define TIMER_SYNC_SYNCT4_TA    0x00000100  // A timeout event for Timer A of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TB    0x00000200  // A timeout event for Timer B of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TATB  0x00000300  // A timeout event for both Timer A
+                                            // and Timer B of GPTM4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT3_M     0x000000C0  // Synchronize GPTM Timer 3
+#define TIMER_SYNC_SYNCT3_NONE  0x00000000  // GPTM3 is not affected
+#define TIMER_SYNC_SYNCT3_TA    0x00000040  // A timeout event for Timer A of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TB    0x00000080  // A timeout event for Timer B of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TATB  0x000000C0  // A timeout event for both Timer A
+                                            // and Timer B of GPTM3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT2_M     0x00000030  // Synchronize GPTM Timer 2
+#define TIMER_SYNC_SYNCT2_NONE  0x00000000  // GPTM2 is not affected
+#define TIMER_SYNC_SYNCT2_TA    0x00000010  // A timeout event for Timer A of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TB    0x00000020  // A timeout event for Timer B of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TATB  0x00000030  // A timeout event for both Timer A
+                                            // and Timer B of GPTM2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT1_M     0x0000000C  // Synchronize GPTM Timer 1
+#define TIMER_SYNC_SYNCT1_NONE  0x00000000  // GPTM1 is not affected
+#define TIMER_SYNC_SYNCT1_TA    0x00000004  // A timeout event for Timer A of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TB    0x00000008  // A timeout event for Timer B of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TATB  0x0000000C  // A timeout event for both Timer A
+                                            // and Timer B of GPTM1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT0_M     0x00000003  // Synchronize GPTM Timer 0
+#define TIMER_SYNC_SYNCT0_NONE  0x00000000  // GPTM0 is not affected
+#define TIMER_SYNC_SYNCT0_TA    0x00000001  // A timeout event for Timer A of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TB    0x00000002  // A timeout event for Timer B of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TATB  0x00000003  // A timeout event for both Timer A
+                                            // and Timer B of GPTM0 is
+                                            // triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_DMABIM        0x00002000  // GPTM Timer B DMA Done Interrupt
+                                            // Mask
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_DMAAIM        0x00000020  // GPTM Timer A DMA Done Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_DMABRIS       0x00002000  // GPTM Timer B DMA Done Raw
+                                            // Interrupt Status
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_DMAARIS       0x00000020  // GPTM Timer A DMA Done Raw
+                                            // Interrupt Status
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_DMABMIS       0x00002000  // GPTM Timer B DMA Done Masked
+                                            // Interrupt
+#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_DMAAMIS       0x00000020  // GPTM Timer A DMA Done Masked
+                                            // Interrupt
+#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_DMABINT       0x00002000  // GPTM Timer B DMA Done Interrupt
+                                            // Clear
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_DMAAINT       0x00000020  // GPTM Timer A DMA Done Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
+                                            // Register
+#define TIMER_TAILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
+#define TIMER_TAR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
+#define TIMER_TBR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
+#define TIMER_TAV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
+#define TIMER_TBV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_DMAEV register.
+//
+//*****************************************************************************
+#define TIMER_DMAEV_TBMDMAEN    0x00000800  // GPTM B Mode Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_CBEDMAEN    0x00000400  // GPTM B Capture Event DMA Trigger
+                                            // Enable
+#define TIMER_DMAEV_CBMDMAEN    0x00000200  // GPTM B Capture Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TBTODMAEN   0x00000100  // GPTM B Time-Out Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TAMDMAEN    0x00000010  // GPTM A Mode Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_RTCDMAEN    0x00000008  // GPTM A RTC Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_CAEDMAEN    0x00000004  // GPTM A Capture Event DMA Trigger
+                                            // Enable
+#define TIMER_DMAEV_CAMDMAEN    0x00000002  // GPTM A Capture Match Event DMA
+                                            // Trigger Enable
+#define TIMER_DMAEV_TATODMAEN   0x00000001  // GPTM A Time-Out Event DMA
+                                            // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ADCEV register.
+//
+//*****************************************************************************
+#define TIMER_ADCEV_TBMADCEN    0x00000800  // GPTM B Mode Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_CBEADCEN    0x00000400  // GPTM B Capture Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CBMADCEN    0x00000200  // GPTM B Capture Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TBTOADCEN   0x00000100  // GPTM B Time-Out Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TAMADCEN    0x00000010  // GPTM A Mode Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_RTCADCEN    0x00000008  // GPTM RTC Match Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CAEADCEN    0x00000004  // GPTM A Capture Event ADC Trigger
+                                            // Enable
+#define TIMER_ADCEV_CAMADCEN    0x00000002  // GPTM A Capture Match Event ADC
+                                            // Trigger Enable
+#define TIMER_ADCEV_TATOADCEN   0x00000001  // GPTM A Time-Out Event ADC
+                                            // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_ALTCLK         0x00000040  // Alternate Clock Source
+#define TIMER_PP_SYNCCNT        0x00000020  // Synchronize Start
+#define TIMER_PP_CHAIN          0x00000010  // Chain with Other Timers
+#define TIMER_PP_SIZE_M         0x0000000F  // Count Size
+#define TIMER_PP_SIZE_16        0x00000000  // Timer A and Timer B counters are
+                                            // 16 bits each with an 8-bit
+                                            // prescale counter
+#define TIMER_PP_SIZE_32        0x00000001  // Timer A and Timer B counters are
+                                            // 32 bits each with a 16-bit
+                                            // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CC register.
+//
+//*****************************************************************************
+#define TIMER_CC_ALTCLK         0x00000001  // Alternate Clock Source
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_BUSY          0x00010000  // ADC Busy
+#define ADC_ACTSS_ADEN3         0x00000800  // ADC SS3 DMA Enable
+#define ADC_ACTSS_ADEN2         0x00000400  // ADC SS2 DMA Enable
+#define ADC_ACTSS_ADEN1         0x00000200  // ADC SS1 DMA Enable
+#define ADC_ACTSS_ADEN0         0x00000100  // ADC SS1 DMA Enable
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
+                                            // Status
+#define ADC_RIS_DMAINR3         0x00000800  // SS3 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR2         0x00000400  // SS2 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR1         0x00000200  // SS1 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR0         0x00000100  // SS0 DMA Raw Interrupt Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
+                                            // SS3
+#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
+                                            // SS2
+#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
+                                            // SS1
+#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
+                                            // SS0
+#define ADC_IM_DMAMASK3         0x00000800  // SS3 DMA Interrupt Mask
+#define ADC_IM_DMAMASK2         0x00000400  // SS2 DMA Interrupt Mask
+#define ADC_IM_DMAMASK1         0x00000200  // SS1 DMA Interrupt Mask
+#define ADC_IM_DMAMASK0         0x00000100  // SS0 DMA Interrupt Mask
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
+                                            // Status on SS3
+#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
+                                            // Status on SS2
+#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
+                                            // Status on SS1
+#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
+                                            // Status on SS0
+#define ADC_ISC_DMAIN3          0x00000800  // SS3 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN2          0x00000400  // SS2 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN1          0x00000200  // SS1 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_DMAIN0          0x00000100  // SS0 DMA Interrupt Status and
+                                            // Clear
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO Pins)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM generator 0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM generator 1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM generator 2
+#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM generator 3
+#define ADC_EMUX_EM3_NEVER      0x0000E000  // Never Trigger
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO Pins)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM generator 0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM generator 1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM generator 2
+#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM generator 3
+#define ADC_EMUX_EM2_NEVER      0x00000E00  // Never Trigger
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO Pins)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM generator 0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM generator 1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM generator 2
+#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM generator 3
+#define ADC_EMUX_EM1_NEVER      0x000000E0  // Never Trigger
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO Pins)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM generator 0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM generator 1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM generator 2
+#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM generator 3
+#define ADC_EMUX_EM0_NEVER      0x0000000E  // Never Trigger
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M         0x30000000  // Generator 3 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS3_0         0x00000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS2_M         0x00300000  // Generator 2 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS2_0         0x00000000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS1_M         0x00003000  // Generator 1 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS1_0         0x00000000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS0_M         0x00000030  // Generator 0 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS0_0         0x00000000  // Use Generator 0 (and its
+                                            // trigger) in PWM module 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_DITHER          0x00000040  // Dither Mode Enable
+#define ADC_CTL_VREF_M          0x00000001  // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL   0x00000000  // VDDA and GNDA are the voltage
+                                            // references
+#define ADC_CTL_VREF_EXT_3V     0x00000001  // The external VREFA+ and VREFA-
+                                            // inputs are the voltage
+                                            // references
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_S     24
+#define ADC_SSDC0_S5DCSEL_S     20
+#define ADC_SSDC0_S4DCSEL_S     16
+#define ADC_SSDC0_S3DCSEL_S     12
+#define ADC_SSDC0_S2DCSEL_S     8
+#define ADC_SSDC0_S1DCSEL_S     4
+#define ADC_SSDC0_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7       0x10000000  // 8th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX6       0x01000000  // 7th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX5       0x00100000  // 6th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX4       0x00010000  // 5th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX0_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH0 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH0_TSH7_M       0xF0000000  // 8th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH6_M       0x0F000000  // 7th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH5_M       0x00F00000  // 6th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH4_M       0x000F0000  // 5th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH0_TSH7_S       28
+#define ADC_SSTSH0_TSH6_S       24
+#define ADC_SSTSH0_TSH5_S       20
+#define ADC_SSTSH0_TSH4_S       16
+#define ADC_SSTSH0_TSH3_S       12
+#define ADC_SSTSH0_TSH2_S       8
+#define ADC_SSTSH0_TSH1_S       4
+#define ADC_SSTSH0_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_S     8
+#define ADC_SSDC1_S1DCSEL_S     4
+#define ADC_SSDC1_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX1_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH1 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH1_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH1_TSH3_S       12
+#define ADC_SSTSH1_TSH2_S       8
+#define ADC_SSTSH1_TSH1_S       4
+#define ADC_SSTSH1_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_S     8
+#define ADC_SSDC2_S1DCSEL_S     4
+#define ADC_SSDC2_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3       0x00001000  // 4th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX2       0x00000100  // 3rd Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX1       0x00000010  // 2th Sample Input Select (Upper
+                                            // Bit)
+#define ADC_SSEMUX2_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH2 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH2_TSH3_M       0x0000F000  // 4th Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH2_M       0x00000F00  // 3rd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH1_M       0x000000F0  // 2nd Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH2_TSH3_S       12
+#define ADC_SSTSH2_TSH2_S       8
+#define ADC_SSTSH2_TSH1_S       4
+#define ADC_SSTSH2_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // Sample Differential Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0       0x00000001  // 1st Sample Input Select (Upper
+                                            // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH3 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH3_TSH0_M       0x0000000F  // 1st Sample and Hold Period
+                                            // Select
+#define ADC_SSTSH3_TSH0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP0_COMP1_S      16
+#define ADC_DCCMP0_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP1_COMP1_S      16
+#define ADC_DCCMP1_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP2_COMP1_S      16
+#define ADC_DCCMP2_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP3_COMP1_S      16
+#define ADC_DCCMP3_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP4_COMP1_S      16
+#define ADC_DCCMP4_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP5_COMP1_S      16
+#define ADC_DCCMP5_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP6_COMP1_S      16
+#define ADC_DCCMP6_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP7_COMP1_S      16
+#define ADC_DCCMP7_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_APSHT            0x01000000  // Application-Programmable
+                                            // Sample-and-Hold Time
+#define ADC_PP_TS               0x00800000  // Temperature Sensor
+#define ADC_PP_RSL_M            0x007C0000  // Resolution
+#define ADC_PP_TYPE_M           0x00030000  // ADC Architecture
+#define ADC_PP_TYPE_SAR         0x00000000  // SAR
+#define ADC_PP_DC_M             0x0000FC00  // Digital Comparator Count
+#define ADC_PP_CH_M             0x000003F0  // ADC Channel Count
+#define ADC_PP_MCR_M            0x0000000F  // Maximum Conversion Rate
+#define ADC_PP_MCR_FULL         0x00000007  // Full conversion rate (FCONV) as
+                                            // defined by TADC and NSH
+#define ADC_PP_RSL_S            18
+#define ADC_PP_DC_S             10
+#define ADC_PP_CH_S             4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_MCR_M            0x0000000F  // Conversion Rate
+#define ADC_PC_MCR_1_8          0x00000001  // Eighth conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 112 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_1_4          0x00000003  // Quarter conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 48 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_1_2          0x00000005  // Half conversion rate. After a
+                                            // conversion completes, the logic
+                                            // pauses for 16 TADC periods
+                                            // before starting the next
+                                            // conversion
+#define ADC_PC_MCR_FULL         0x00000007  // Full conversion rate (FCONV) as
+                                            // defined by TADC and NSH
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CLKDIV_M         0x000003F0  // PLL VCO Clock Divisor
+#define ADC_CC_CS_M             0x0000000F  // ADC Clock Source
+#define ADC_CC_CS_SYSPLL        0x00000000  // PLL VCO divided by CLKDIV
+#define ADC_CC_CS_PIOSC         0x00000001  // PIOSC
+#define ADC_CC_CS_MOSC          0x00000002  // MOSC
+#define ADC_CC_CLKDIV_S         4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O             0x00040000  // Comparator Output 2 Present
+#define COMP_PP_C1O             0x00020000  // Comparator Output 1 Present
+#define COMP_PP_C0O             0x00010000  // Comparator Output 0 Present
+#define COMP_PP_CMP2            0x00000004  // Comparator 2 Present
+#define COMP_PP_CMP1            0x00000002  // Comparator 1 Present
+#define COMP_PP_CMP0            0x00000001  // Comparator 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF1CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF2CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_HSENAB        0x00000020  // High Speed Enable
+#define USB_POWER_HSMODE        0x00000010  // High Speed Enable
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)
+#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG
+                                            // only)
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG
+                                            // only)
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
+#define USB_TEST_FORCEHS        0x00000010  // Force High-Speed Mode
+#define USB_TEST_TESTPKT        0x00000008  // Test Packet Mode Enable
+#define USB_TEST_TESTK          0x00000004  // Test_K Mode Enable
+#define USB_TEST_TESTJ          0x00000002  // Test_J Mode Enable
+#define USB_TEST_TESTSE0NAK     0x00000001  // Test_SE0_NAK Test Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CCONF register.
+//
+//*****************************************************************************
+#define USB_CCONF_TXEDMA        0x00000002  // TX Early DMA Enable
+#define USB_CCONF_RXEDMA        0x00000001  // TX Early DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIVBUSCTL_USEEXTVBUSIND                                         \
+                                0x00000002  // Use External VBUS Indicator
+#define USB_ULPIVBUSCTL_USEEXTVBUS                                            \
+                                0x00000001  // Use External VBUS
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGDATA
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGDATA_REGDATA_M                                             \
+                                0x000000FF  // Register Data
+#define USB_ULPIREGDATA_REGDATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGADDR
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGADDR_ADDR_M  0x000000FF  // Register Address
+#define USB_ULPIREGADDR_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGCTL_RDWR     0x00000004  // Read/Write Control
+#define USB_ULPIREGCTL_REGCMPLT 0x00000002  // Register Access Complete
+#define USB_ULPIREGCTL_REGACC   0x00000001  // Initiate Register Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPINFO register.
+//
+//*****************************************************************************
+#define USB_EPINFO_RXEP_M       0x000000F0  // RX Endpoints
+#define USB_EPINFO_TXEP_M       0x0000000F  // TX Endpoints
+#define USB_EPINFO_RXEP_S       4
+#define USB_EPINFO_TXEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RAMINFO register.
+//
+//*****************************************************************************
+#define USB_RAMINFO_DMACHAN_M   0x000000F0  // DMA Channels
+#define USB_RAMINFO_RAMBITS_M   0x0000000F  // RAM Address Bus Width
+#define USB_RAMINFO_DMACHAN_S   4
+#define USB_RAMINFO_RAMBITS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSEOF register.
+//
+//*****************************************************************************
+#define USB_HSEOF_HSEOFG_M      0x000000FF  // HIgh-Speed End-of-Frame Gap
+#define USB_HSEOF_HSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DISPING       0x00000008  // PING Disable
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
+#define USB_TYPE0_SPEED_HIGH    0x00000040  // High
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH1_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH2_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH3_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH4_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH5_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL5_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL5_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH6_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL6_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL6_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH7_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAINTR register.
+//
+//*****************************************************************************
+#define USB_DMAINTR_CH7         0x00000080  // Channel 7 DMA Interrupt
+#define USB_DMAINTR_CH6         0x00000040  // Channel 6 DMA Interrupt
+#define USB_DMAINTR_CH5         0x00000020  // Channel 5 DMA Interrupt
+#define USB_DMAINTR_CH4         0x00000010  // Channel 4 DMA Interrupt
+#define USB_DMAINTR_CH3         0x00000008  // Channel 3 DMA Interrupt
+#define USB_DMAINTR_CH2         0x00000004  // Channel 2 DMA Interrupt
+#define USB_DMAINTR_CH1         0x00000002  // Channel 1 DMA Interrupt
+#define USB_DMAINTR_CH0         0x00000001  // Channel 0 DMA Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+//
+//*****************************************************************************
+#define USB_DMACTL0_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL0_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL0_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL0_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL0_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL0_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL0_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL0_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL0_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL0_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL0_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL0_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR0_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT0_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL1 register.
+//
+//*****************************************************************************
+#define USB_DMACTL1_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL1_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL1_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL1_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL1_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL1_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL1_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL1_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL1_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL1_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL1_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL1_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR1_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR1_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT1_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT1_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL2 register.
+//
+//*****************************************************************************
+#define USB_DMACTL2_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL2_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL2_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL2_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL2_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL2_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL2_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL2_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL2_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL2_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL2_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL2_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR2_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR2_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT2_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT2_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL3 register.
+//
+//*****************************************************************************
+#define USB_DMACTL3_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL3_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL3_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL3_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL3_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL3_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL3_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL3_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL3_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL3_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL3_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL3_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR3_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR3_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT3_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT3_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL4 register.
+//
+//*****************************************************************************
+#define USB_DMACTL4_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL4_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL4_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL4_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL4_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL4_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL4_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL4_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL4_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL4_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL4_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL4_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR4_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR4_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT4_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT4_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL5 register.
+//
+//*****************************************************************************
+#define USB_DMACTL5_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL5_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL5_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL5_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL5_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL5_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL5_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL5_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL5_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL5_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL5_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL5_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR5_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR5_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT5_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT5_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL6 register.
+//
+//*****************************************************************************
+#define USB_DMACTL6_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL6_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL6_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL6_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL6_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL6_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL6_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL6_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL6_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL6_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL6_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL6_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR6_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR6_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT6_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT6_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL7 register.
+//
+//*****************************************************************************
+#define USB_DMACTL7_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL7_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL7_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL7_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL7_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL7_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL7_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL7_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL7_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL7_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL7_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL7_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR7_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR7_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT7_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT7_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CTO register.
+//
+//*****************************************************************************
+#define USB_CTO_CCTV_M          0x0000FFFF  // Configurable Chirp Timeout Value
+#define USB_CTO_CCTV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HHSRTN register.
+//
+//*****************************************************************************
+#define USB_HHSRTN_HHSRTN_M     0x0000FFFF  // HIgh Speed to UTM Operating
+                                            // Delay
+#define USB_HHSRTN_HHSRTN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSBT register.
+//
+//*****************************************************************************
+#define USB_HSBT_HSBT_M         0x0000000F  // High Speed Timeout Adder
+#define USB_HSBT_HSBT_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMATTR register.
+//
+//*****************************************************************************
+#define USB_LPMATTR_ENDPT_M     0x0000F000  // Endpoint
+#define USB_LPMATTR_RMTWAK      0x00000100  // Remote Wake
+#define USB_LPMATTR_HIRD_M      0x000000F0  // Host Initiated Resume Duration
+#define USB_LPMATTR_LS_M        0x0000000F  // Link State
+#define USB_LPMATTR_LS_L1       0x00000001  // Sleep State (L1)
+#define USB_LPMATTR_ENDPT_S     12
+#define USB_LPMATTR_HIRD_S      4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
+//
+//*****************************************************************************
+#define USB_LPMCNTRL_NAK        0x00000010  // LPM NAK
+#define USB_LPMCNTRL_EN_M       0x0000000C  // LPM Enable
+#define USB_LPMCNTRL_EN_NONE    0x00000000  // LPM and Extended transactions
+                                            // are not supported. In this case,
+                                            // the USB does not respond to LPM
+                                            // transactions and LPM
+                                            // transactions cause a timeout
+#define USB_LPMCNTRL_EN_EXT     0x00000004  // LPM is not supported but
+                                            // extended transactions are
+                                            // supported. In this case, the USB
+                                            // does respond to an LPM
+                                            // transaction with a STALL
+#define USB_LPMCNTRL_EN_LPMEXT  0x0000000C  // The USB supports LPM extended
+                                            // transactions. In this case, the
+                                            // USB responds with a NYET or an
+                                            // ACK as determined by the value
+                                            // of TXLPM and other conditions
+#define USB_LPMCNTRL_RES        0x00000002  // LPM Resume
+#define USB_LPMCNTRL_TXLPM      0x00000001  // Transmit LPM Transaction Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMIM register.
+//
+//*****************************************************************************
+#define USB_LPMIM_ERR           0x00000020  // LPM Error Interrupt Mask
+#define USB_LPMIM_RES           0x00000010  // LPM Resume Interrupt Mask
+#define USB_LPMIM_NC            0x00000008  // LPM NC Interrupt Mask
+#define USB_LPMIM_ACK           0x00000004  // LPM ACK Interrupt Mask
+#define USB_LPMIM_NY            0x00000002  // LPM NY Interrupt Mask
+#define USB_LPMIM_STALL         0x00000001  // LPM STALL Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMRIS register.
+//
+//*****************************************************************************
+#define USB_LPMRIS_ERR          0x00000020  // LPM Interrupt Status
+#define USB_LPMRIS_RES          0x00000010  // LPM Resume Interrupt Status
+#define USB_LPMRIS_NC           0x00000008  // LPM NC Interrupt Status
+#define USB_LPMRIS_ACK          0x00000004  // LPM ACK Interrupt Status
+#define USB_LPMRIS_NY           0x00000002  // LPM NY Interrupt Status
+#define USB_LPMRIS_LPMST        0x00000001  // LPM STALL Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMFADDR register.
+//
+//*****************************************************************************
+#define USB_LPMFADDR_ADDR_M     0x0000007F  // LPM Function Address
+#define USB_LPMFADDR_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+                                            // (OTG only)
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+                                            // (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD_M       0x00000007  // Device Mode
+#define USB_GPCS_DEVMOD_OTG     0x00000000  // Use USB0VBUS and USB0ID pin
+#define USB_GPCS_DEVMOD_HOST    0x00000002  // Force USB0VBUS and USB0ID low
+#define USB_GPCS_DEVMOD_DEV     0x00000003  // Force USB0VBUS and USB0ID high
+#define USB_GPCS_DEVMOD_HOSTVBUS                                              \
+                                0x00000004  // Use USB0VBUS and force USB0ID
+                                            // low
+#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005  // Use USB0VBUS and force USB0ID
+                                            // high
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
+#define USB_PP_USB_M            0x000000C0  // USB Capability
+#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
+#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
+#define USB_PP_USB_OTG          0x000000C0  // OTG
+#define USB_PP_ULPI             0x00000020  // ULPI Present
+#define USB_PP_PHY              0x00000010  // PHY Present
+#define USB_PP_TYPE_M           0x0000000F  // Controller Type
+#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
+                                            // controller
+#define USB_PP_TYPE_1           0x00000001  // Second-generation USB
+                                            // controller.The controller
+                                            // implemented in post Icestorm
+                                            // devices that use the 3.0 version
+                                            // of the Mentor controller
+#define USB_PP_ECNT_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PC register.
+//
+//*****************************************************************************
+#define USB_PC_ULPIEN           0x00010000  // ULPI Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CC register.
+//
+//*****************************************************************************
+#define USB_CC_CLKEN            0x00000200  // USB Clock Enable
+#define USB_CC_CSD              0x00000100  // Clock Source/Direction
+#define USB_CC_CLKDIV_M         0x0000000F  // PLL Clock Divisor
+#define USB_CC_CLKDIV_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_BLKCNT_M  0x07FF0000  // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF  // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_S  16
+#define EEPROM_EESIZE_WORDCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M  0x0000FFFF  // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M                                              \
+                                0x0000000F  // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF  // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M                                              \
+                                0xFFFFFFFF  // EEPROM Read or Write Data with
+                                            // Increment
+#define EEPROM_EERDWRINC_VALUE_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WRBUSY    0x00000020  // Write Busy
+#define EEPROM_EEDONE_NOPERM    0x00000010  // Write Without Permission
+#define EEPROM_EEDONE_WKCOPY    0x00000008  // Working on a Copy
+#define EEPROM_EEDONE_WKERASE   0x00000004  // Working on an Erase
+#define EEPROM_EEDONE_WORKING   0x00000001  // EEPROM Working
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_PRETRY    0x00000008  // Programming Must Be Retried
+#define EEPROM_EESUPP_ERETRY    0x00000004  // Erase Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M                                              \
+                                0xFFFFFFFF  // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_ACC       0x00000008  // Access Control
+#define EEPROM_EEPROT_PROT_M    0x00000007  // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW                                              \
+                                0x00000000  // This setting is the default. If
+                                            // there is no password, the block
+                                            // is not protected and is readable
+                                            // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001  // If there is a password, the
+                                            // block is readable or writable
+                                            // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW                                              \
+                                0x00000002  // If there is no password, the
+                                            // block is readable, not writable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS0_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS1_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS2_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT        0x00000001  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE0_HN_M     0xFFFFFFFE  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE1_HN_M     0xFFFFFFFF  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE2_HN_M     0xFFFFFFFF  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_KEY_M    0xFFFF0000  // Erase Key
+#define EEPROM_EEDBGME_ME       0x00000001  // Mass Erase
+#define EEPROM_EEDBGME_KEY_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M        0x0000FFFF  // EEPROM Size
+#define EEPROM_PP_SIZE_64       0x00000000  // 64 bytes of EEPROM
+#define EEPROM_PP_SIZE_128      0x00000001  // 128 bytes of EEPROM
+#define EEPROM_PP_SIZE_256      0x00000003  // 256 bytes of EEPROM
+#define EEPROM_PP_SIZE_512      0x00000007  // 512 bytes of EEPROM
+#define EEPROM_PP_SIZE_1K       0x0000000F  // 1 KB of EEPROM
+#define EEPROM_PP_SIZE_2K       0x0000001F  // 2 KB of EEPROM
+#define EEPROM_PP_SIZE_3K       0x0000003F  // 3 KB of EEPROM
+#define EEPROM_PP_SIZE_4K       0x0000007F  // 4 KB of EEPROM
+#define EEPROM_PP_SIZE_5K       0x000000FF  // 5 KB of EEPROM
+#define EEPROM_PP_SIZE_6K       0x000001FF  // 6 KB of EEPROM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_INTDIV          0x00000100  // Integer Clock Divider Enable
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
+#define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
+#define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
+#define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD2 register.
+//
+//*****************************************************************************
+#define EPI_BAUD2_COUNT1_M      0xFFFF0000  // CS3n Baud Rate Counter 1
+#define EPI_BAUD2_COUNT0_M      0x0000FFFF  // CS2n Baud Rate Counter 0
+#define EPI_BAUD2_COUNT1_S      16
+#define EPI_BAUD2_COUNT0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_CLKGATE     0x80000000  // Clock Gated
+#define EPI_HB16CFG_CLKGATEI    0x40000000  // Clock Gated Idle
+#define EPI_HB16CFG_CLKINV      0x20000000  // Invert Output Clock Enable
+#define EPI_HB16CFG_RDYEN       0x10000000  // Input Ready Enable
+#define EPI_HB16CFG_IRDYINV     0x08000000  // Input Ready Invert
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_ALEHIGH     0x00080000  // ALE Strobe Polarity
+#define EPI_HB16CFG_WRCRE       0x00040000  // PSRAM Configuration Register
+                                            // Write
+#define EPI_HB16CFG_RDCRE       0x00020000  // PSRAM Configuration Register
+                                            // Read
+#define EPI_HB16CFG_BURST       0x00010000  // Burst Mode
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // Write Wait States
+#define EPI_HB16CFG_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG_RDWS_M      0x00000030  // Read Wait States
+#define EPI_HB16CFG_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S      22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // EPI Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_CLKGATE      0x80000000  // Clock Gated
+#define EPI_HB8CFG_CLKGATEI     0x40000000  // Clock Gated when Idle
+#define EPI_HB8CFG_CLKINV       0x20000000  // Invert Output Clock Enable
+#define EPI_HB8CFG_RDYEN        0x10000000  // Input Ready Enable
+#define EPI_HB8CFG_IRDYINV      0x08000000  // Input Ready Invert
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // READ Strobe Polarity
+#define EPI_HB8CFG_ALEHIGH      0x00080000  // ALE Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
+#define EPI_HB8CFG_WRWS_2       0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG_WRWS_4       0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG_WRWS_6       0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG_WRWS_8       0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
+#define EPI_HB8CFG_RDWS_2       0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG_RDWS_4       0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG_RDWS_6       0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG_RDWS_8       0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S    8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_CSCFGEXT    0x08000000  // Chip Select Extended
+                                            // Configuration
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate and
+                                            // Multiple Sub-Mode Configuration
+                                            // enable
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH      0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH      0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_ALEHIGH     0x00080000  // CS1n ALE Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M      0x000000C0  // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG2_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG2_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG2_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG2_RDWS_M      0x00000030  // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG2_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG2_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG2_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG2_MODE_M      0x00000003  // CS1n Host Bus Sub-Mode
+#define EPI_HB8CFG2_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG2_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_CSCFGEXT   0x08000000  // Chip Select Extended
+                                            // Configuration
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate and
+                                            // Multiple Sub-Mode Configuration
+                                            // enable
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH     0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH     0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_ALEHIGH    0x00080000  // CS1n ALE Strobe Polarity
+#define EPI_HB16CFG2_WRCRE      0x00040000  // CS1n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG2_RDCRE      0x00020000  // CS1n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG2_BURST      0x00010000  // CS1n Burst Mode
+#define EPI_HB16CFG2_WRWS_M     0x000000C0  // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG2_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG2_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG2_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG2_RDWS_M     0x00000030  // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG2_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG2_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG2_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG2_MODE_M     0x00000003  // CS1n Host Bus Sub-Mode
+#define EPI_HB16CFG2_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG2_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_ECSZ_M      0x00000C00  // External Code Size
+#define EPI_ADDRMAP_ECSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ECSZ_64KB   0x00000400  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ECSZ_16MB   0x00000800  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ECSZ_256MB  0x00000C00  // 256MB; lower address range:
+                                            // 0x000.0000 to 0x0FFF.FFFF
+#define EPI_ADDRMAP_ECADR_M     0x00000300  // External Code Address
+#define EPI_ADDRMAP_ECADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ECADR_1000  0x00000100  // At 0x1000.0000
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
+#define EPI_ADDRMAP_EPADR_HBQS  0x00000030  // Only to be used with Host Bus
+                                            // quad chip select. In quad chip
+                                            // select mode, CS2n maps to
+                                            // 0xA000.0000 and CS3n maps to
+                                            // 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
+#define EPI_ADDRMAP_ERADR_HBQS  0x00000003  // Only to be used with Host Bus
+                                            // quad chip select. In quad chip
+                                            // select mode, CS0n maps to
+                                            // 0x6000.0000 and CS1n maps to
+                                            // 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M       0xFFFFFFFF  // Current Address
+#define EPI_RADDR0_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD0_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M       0xFFFFFFFF  // Current Address
+#define EPI_RADDR1_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD1_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M    0x0000000F  // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO0
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO0_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO0_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO4_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO5_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO6_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO7_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Interrupt is triggered while
+                                            // WRFIFO is empty.
+#define EPI_FIFOLVL_WRFIFO_2    0x00000020  // Interrupt is triggered until
+                                            // there are only two slots
+                                            // available. Thus, trigger is
+                                            // deasserted when there are two
+                                            // WRFIFO entries present. This
+                                            // configuration is optimized for
+                                            // bursts of 2
+#define EPI_FIFOLVL_WRFIFO_1    0x00000030  // Interrupt is triggered until
+                                            // there is one WRFIFO entry
+                                            // available. This configuration
+                                            // expects only single writes
+#define EPI_FIFOLVL_WRFIFO_NFULL                                              \
+                                0x00000040  // Trigger interrupt when WRFIFO is
+                                            // not full, meaning trigger will
+                                            // continue to assert until there
+                                            // are four entries in the WRFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_1    0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_2    0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_4    0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_6    0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7    0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_8    0x00000006  // Trigger when there are 8 entries
+                                            // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_DMATXCNT register.
+//
+//*****************************************************************************
+#define EPI_DMATXCNT_TXCNT_M    0x0000FFFF  // DMA Count
+#define EPI_DMATXCNT_TXCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_DMAWRIM          0x00000010  // Write uDMA Interrupt Mask
+#define EPI_IM_DMARDIM          0x00000008  // Read uDMA Interrupt Mask
+#define EPI_IM_WRIM             0x00000004  // Write FIFO Empty Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read FIFO Full Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_DMAWRRIS        0x00000010  // Write uDMA Raw Interrupt Status
+#define EPI_RIS_DMARDRIS        0x00000008  // Read uDMA Raw Interrupt Status
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_DMAWRMIS        0x00000010  // Write uDMA Masked Interrupt
+                                            // Status
+#define EPI_MIS_DMARDMIS        0x00000008  // Read uDMA Masked Interrupt
+                                            // Status
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_DMAWRIC        0x00000010  // Write uDMA Interrupt Clear
+#define EPI_EISC_DMARDIC        0x00000008  // Read uDMA Interrupt Clear
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG3_WRHIGH      0x00200000  // CS2n WRITE Strobe Polarity
+#define EPI_HB8CFG3_RDHIGH      0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB8CFG3_ALEHIGH     0x00080000  // CS2n ALE Strobe Polarity
+#define EPI_HB8CFG3_WRWS_M      0x000000C0  // CS2n Write Wait States
+#define EPI_HB8CFG3_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG3_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG3_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG3_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG3_RDWS_M      0x00000030  // CS2n Read Wait States
+#define EPI_HB8CFG3_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG3_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG3_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG3_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG3_MODE_M      0x00000003  // CS2n Host Bus Sub-Mode
+#define EPI_HB8CFG3_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG3_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG3_WRHIGH     0x00200000  // CS2n WRITE Strobe Polarity
+#define EPI_HB16CFG3_RDHIGH     0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB16CFG3_ALEHIGH    0x00080000  // CS2n ALE Strobe Polarity
+#define EPI_HB16CFG3_WRCRE      0x00040000  // CS2n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG3_RDCRE      0x00020000  // CS2n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG3_BURST      0x00010000  // CS2n Burst Mode
+#define EPI_HB16CFG3_WRWS_M     0x000000C0  // CS2n Write Wait States
+#define EPI_HB16CFG3_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG3_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG3_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG3_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG3_RDWS_M     0x00000030  // CS2n Read Wait States
+#define EPI_HB16CFG3_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG3_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG3_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG3_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG3_MODE_M     0x00000003  // CS2n Host Bus Sub-Mode
+#define EPI_HB16CFG3_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG3_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG4_WRHIGH     0x00200000  // CS3n WRITE Strobe Polarity
+#define EPI_HB16CFG4_RDHIGH     0x00100000  // CS3n READ Strobe Polarity
+#define EPI_HB16CFG4_ALEHIGH    0x00080000  // CS3n ALE Strobe Polarity
+#define EPI_HB16CFG4_WRCRE      0x00040000  // CS3n PSRAM Configuration
+                                            // Register Write
+#define EPI_HB16CFG4_RDCRE      0x00020000  // CS3n PSRAM Configuration
+                                            // Register Read
+#define EPI_HB16CFG4_BURST      0x00010000  // CS3n Burst Mode
+#define EPI_HB16CFG4_WRWS_M     0x000000C0  // CS3n Write Wait States
+#define EPI_HB16CFG4_WRWS_2     0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG4_WRWS_4     0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG4_WRWS_6     0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG4_WRWS_8     0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG4_RDWS_M     0x00000030  // CS3n Read Wait States
+#define EPI_HB16CFG4_RDWS_2     0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG4_RDWS_4     0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG4_RDWS_6     0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG4_RDWS_8     0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG4_MODE_M     0x00000003  // CS3n Host Bus Sub-Mode
+#define EPI_HB16CFG4_MODE_ADMUX 0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG4_MODE_AD    0x00000001  // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG4_WRHIGH      0x00200000  // CS3n WRITE Strobe Polarity
+#define EPI_HB8CFG4_RDHIGH      0x00100000  // CS2n READ Strobe Polarity
+#define EPI_HB8CFG4_ALEHIGH     0x00080000  // CS3n ALE Strobe Polarity
+#define EPI_HB8CFG4_WRWS_M      0x000000C0  // CS3n Write Wait States
+#define EPI_HB8CFG4_WRWS_2      0x00000000  // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG4_WRWS_4      0x00000040  // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG4_WRWS_6      0x00000080  // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG4_WRWS_8      0x000000C0  // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG4_RDWS_M      0x00000030  // CS3n Read Wait States
+#define EPI_HB8CFG4_RDWS_2      0x00000000  // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG4_RDWS_4      0x00000010  // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG4_RDWS_6      0x00000020  // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG4_RDWS_8      0x00000030  // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG4_MODE_M      0x00000003  // CS3n Host Bus Sub-Mode
+#define EPI_HB8CFG4_MODE_ADMUX  0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG4_MODE_AD     0x00000001  // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME_IRDYDLY_M   0x03000000  // CS0n Input Ready Delay
+#define EPI_HB8TIME_CAPWIDTH_M  0x00003000  // CS0n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME_WRWSM       0x00000010  // Write Wait State Minus One
+#define EPI_HB8TIME_RDWSM       0x00000001  // Read Wait State Minus One
+#define EPI_HB8TIME_IRDYDLY_S   24
+#define EPI_HB8TIME_CAPWIDTH_S  12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME_IRDYDLY_M  0x03000000  // CS0n Input Ready Delay
+#define EPI_HB16TIME_PSRAMSZ_M  0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME_PSRAMSZ_0  0x00000000  // No row size limitation
+#define EPI_HB16TIME_PSRAMSZ_128B                                             \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME_PSRAMSZ_256B                                             \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME_PSRAMSZ_512B                                             \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME_PSRAMSZ_1KB                                              \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME_PSRAMSZ_2KB                                              \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME_PSRAMSZ_4KB                                              \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME_PSRAMSZ_8KB                                              \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME_CAPWIDTH_M 0x00003000  // CS0n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME_WRWSM      0x00000010  // Write Wait State Minus One
+#define EPI_HB16TIME_RDWSM      0x00000001  // Read Wait State Minus One
+#define EPI_HB16TIME_IRDYDLY_S  24
+#define EPI_HB16TIME_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME2 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME2_IRDYDLY_M  0x03000000  // CS1n Input Ready Delay
+#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000  // CS1n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME2_WRWSM      0x00000010  // CS1n Write Wait State Minus One
+#define EPI_HB8TIME2_RDWSM      0x00000001  // CS1n Read Wait State Minus One
+#define EPI_HB8TIME2_IRDYDLY_S  24
+#define EPI_HB8TIME2_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME2
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME2_IRDYDLY_M 0x03000000  // CS1n Input Ready Delay
+#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME2_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME2_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME2_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME2_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME2_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME2_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME2_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME2_CAPWIDTH_M                                              \
+                                0x00003000  // CS1n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME2_WRWSM     0x00000010  // CS1n Write Wait State Minus One
+#define EPI_HB16TIME2_RDWSM     0x00000001  // CS1n Read Wait State Minus One
+#define EPI_HB16TIME2_IRDYDLY_S 24
+#define EPI_HB16TIME2_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME3
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME3_IRDYDLY_M 0x03000000  // CS2n Input Ready Delay
+#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME3_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME3_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME3_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME3_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME3_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME3_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME3_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME3_CAPWIDTH_M                                              \
+                                0x00003000  // CS2n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME3_WRWSM     0x00000010  // CS2n Write Wait State Minus One
+#define EPI_HB16TIME3_RDWSM     0x00000001  // CS2n Read Wait State Minus One
+#define EPI_HB16TIME3_IRDYDLY_S 24
+#define EPI_HB16TIME3_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME3 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME3_IRDYDLY_M  0x03000000  // CS2n Input Ready Delay
+#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000  // CS2n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME3_WRWSM      0x00000010  // CS2n Write Wait State Minus One
+#define EPI_HB8TIME3_RDWSM      0x00000001  // CS2n Read Wait State Minus One
+#define EPI_HB8TIME3_IRDYDLY_S  24
+#define EPI_HB8TIME3_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME4 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME4_IRDYDLY_M  0x03000000  // CS3n Input Ready Delay
+#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000  // CS3n Inter-transfer Capture
+                                            // Width
+#define EPI_HB8TIME4_WRWSM      0x00000010  // CS3n Write Wait State Minus One
+#define EPI_HB8TIME4_RDWSM      0x00000001  // CS3n Read Wait State Minus One
+#define EPI_HB8TIME4_IRDYDLY_S  24
+#define EPI_HB8TIME4_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME4
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME4_IRDYDLY_M 0x03000000  // CS3n Input Ready Delay
+#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000  // PSRAM Row Size
+#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000  // No row size limitation
+#define EPI_HB16TIME4_PSRAMSZ_128B                                            \
+                                0x00010000  // 128 B
+#define EPI_HB16TIME4_PSRAMSZ_256B                                            \
+                                0x00020000  // 256 B
+#define EPI_HB16TIME4_PSRAMSZ_512B                                            \
+                                0x00030000  // 512 B
+#define EPI_HB16TIME4_PSRAMSZ_1KB                                             \
+                                0x00040000  // 1024 B
+#define EPI_HB16TIME4_PSRAMSZ_2KB                                             \
+                                0x00050000  // 2048 B
+#define EPI_HB16TIME4_PSRAMSZ_4KB                                             \
+                                0x00060000  // 4096 B
+#define EPI_HB16TIME4_PSRAMSZ_8KB                                             \
+                                0x00070000  // 8192 B
+#define EPI_HB16TIME4_CAPWIDTH_M                                              \
+                                0x00003000  // CS3n Inter-transfer Capture
+                                            // Width
+#define EPI_HB16TIME4_WRWSM     0x00000010  // CS3n Write Wait State Minus One
+#define EPI_HB16TIME4_RDWSM     0x00000001  // CS3n Read Wait State Minus One
+#define EPI_HB16TIME4_IRDYDLY_S 24
+#define EPI_HB16TIME4_CAPWIDTH_S                                              \
+                                12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HBPSRAM register.
+//
+//*****************************************************************************
+#define EPI_HBPSRAM_CR_M        0x001FFFFF  // PSRAM Config Register
+#define EPI_HBPSRAM_CR_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPUFCMIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIOCMIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIDCMIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
+#define HIB_RTCC_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
+#define HIB_RTCM0_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
+#define HIB_RTCLD_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable
+#define HIB_CTL_RETCLR          0x40000000  // GPIO Retention/Clear
+#define HIB_CTL_OSCSEL          0x00080000  // Oscillator Select
+#define HIB_CTL_OSCDRV          0x00020000  // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP          0x00010000  // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M       0x00006000  // Select for Low-Battery
+                                            // Comparator
+#define HIB_CTL_VBATSEL_1_9V    0x00000000  // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V    0x00002000  // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V    0x00004000  // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V    0x00006000  // 2.5 Volts
+#define HIB_CTL_BATCHK          0x00000400  // Check Battery Status
+#define HIB_CTL_BATWKEN         0x00000200  // Wake on Low Battery
+#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_PINWEN          0x00000010  // External Wake Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_VDDFAIL          0x00000080  // VDD Fail Interrupt Mask
+#define HIB_IM_RSTWK            0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Mask
+#define HIB_IM_PADIOWK          0x00000020  // Pad I/O Wake-Up Interrupt Mask
+#define HIB_IM_WC               0x00000010  // External Write Complete/Capable
+                                            // Interrupt Mask
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_VDDFAIL         0x00000080  // VDD Fail Raw Interrupt Status
+#define HIB_RIS_RSTWK           0x00000040  // Reset Pad I/O Wake-Up Raw
+                                            // Interrupt Status
+#define HIB_RIS_PADIOWK         0x00000020  // Pad I/O Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_WC              0x00000010  // Write Complete/Capable Raw
+                                            // Interrupt Status
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_VDDFAIL         0x00000080  // VDD Fail Interrupt Mask
+#define HIB_MIS_RSTWK           0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Mask
+#define HIB_MIS_PADIOWK         0x00000020  // Pad I/O Wake-Up Interrupt Mask
+#define HIB_MIS_WC              0x00000010  // Write Complete/Capable Masked
+                                            // Interrupt Status
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_VDDFAIL          0x00000080  // VDD Fail Interrupt Clear
+#define HIB_IC_RSTWK            0x00000040  // Reset Pad I/O Wake-Up Interrupt
+                                            // Clear
+#define HIB_IC_PADIOWK          0x00000020  // Pad I/O Wake-Up Interrupt Clear
+#define HIB_IC_WC               0x00000010  // Write Complete/Capable Interrupt
+                                            // Clear
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
+#define HIB_RTCT_TRIM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M      0x7FFF0000  // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M      0x00007FFF  // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S      16
+#define HIB_RTCSS_RTCSSC_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IO register.
+//
+//*****************************************************************************
+#define HIB_IO_IOWRC            0x80000000  // I/O Write Complete
+#define HIB_IO_WURSTEN          0x00000010  // Reset Wake Source Enable
+#define HIB_IO_WUUNLK           0x00000001  // I/O Wake Pad Configuration
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
+#define HIB_DATA_RTD_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALCTL register.
+//
+//*****************************************************************************
+#define HIB_CALCTL_CAL24        0x00000004  // Calendar Mode
+#define HIB_CALCTL_CALEN        0x00000001  // RTC Calendar/Counter Mode Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL0 register.
+//
+//*****************************************************************************
+#define HIB_CAL0_VALID          0x80000000  // Valid Calendar Load
+#define HIB_CAL0_AMPM           0x00400000  // AM/PM Designation
+#define HIB_CAL0_HR_M           0x001F0000  // Hours
+#define HIB_CAL0_MIN_M          0x00003F00  // Minutes
+#define HIB_CAL0_SEC_M          0x0000003F  // Seconds
+#define HIB_CAL0_HR_S           16
+#define HIB_CAL0_MIN_S          8
+#define HIB_CAL0_SEC_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL1 register.
+//
+//*****************************************************************************
+#define HIB_CAL1_VALID          0x80000000  // Valid Calendar Load
+#define HIB_CAL1_DOW_M          0x07000000  // Day of Week
+#define HIB_CAL1_YEAR_M         0x007F0000  // Year Value
+#define HIB_CAL1_MON_M          0x00000F00  // Month
+#define HIB_CAL1_DOM_M          0x0000001F  // Day of Month
+#define HIB_CAL1_DOW_S          24
+#define HIB_CAL1_YEAR_S         16
+#define HIB_CAL1_MON_S          8
+#define HIB_CAL1_DOM_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD0 register.
+//
+//*****************************************************************************
+#define HIB_CALLD0_AMPM         0x00400000  // AM/PM Designation
+#define HIB_CALLD0_HR_M         0x001F0000  // Hours
+#define HIB_CALLD0_MIN_M        0x00003F00  // Minutes
+#define HIB_CALLD0_SEC_M        0x0000003F  // Seconds
+#define HIB_CALLD0_HR_S         16
+#define HIB_CALLD0_MIN_S        8
+#define HIB_CALLD0_SEC_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD1 register.
+//
+//*****************************************************************************
+#define HIB_CALLD1_DOW_M        0x07000000  // Day of Week
+#define HIB_CALLD1_YEAR_M       0x007F0000  // Year Value
+#define HIB_CALLD1_MON_M        0x00000F00  // Month
+#define HIB_CALLD1_DOM_M        0x0000001F  // Day of Month
+#define HIB_CALLD1_DOW_S        24
+#define HIB_CALLD1_YEAR_S       16
+#define HIB_CALLD1_MON_S        8
+#define HIB_CALLD1_DOM_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM0 register.
+//
+//*****************************************************************************
+#define HIB_CALM0_AMPM          0x00400000  // AM/PM Designation
+#define HIB_CALM0_HR_M          0x001F0000  // Hours
+#define HIB_CALM0_MIN_M         0x00003F00  // Minutes
+#define HIB_CALM0_SEC_M         0x0000003F  // Seconds
+#define HIB_CALM0_HR_S          16
+#define HIB_CALM0_MIN_S         8
+#define HIB_CALM0_SEC_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM1 register.
+//
+//*****************************************************************************
+#define HIB_CALM1_DOM_M         0x0000001F  // Day of Month
+#define HIB_CALM1_DOM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_LOCK register.
+//
+//*****************************************************************************
+#define HIB_LOCK_HIBLOCK_M      0xFFFFFFFF  // HIbernate Lock
+#define HIB_LOCK_HIBLOCK_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPCTL register.
+//
+//*****************************************************************************
+#define HIB_TPCTL_WAKE          0x00000800  // Wake from Hibernate on a Tamper
+                                            // Event
+#define HIB_TPCTL_MEMCLR_M      0x00000300  // HIB Memory Clear on Tamper Event
+#define HIB_TPCTL_MEMCLR_NONE   0x00000000  // Do not Clear HIB memory on
+                                            // tamper event
+#define HIB_TPCTL_MEMCLR_LOW32  0x00000100  // Clear Lower 32 Bytes of HIB
+                                            // memory on tamper event
+#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200  // Clear upper 32 Bytes of HIB
+                                            // memory on tamper event
+#define HIB_TPCTL_MEMCLR_ALL    0x00000300  // Clear all HIB memory on tamper
+                                            // event
+#define HIB_TPCTL_TPCLR         0x00000010  // Tamper Event Clear
+#define HIB_TPCTL_TPEN          0x00000001  // Tamper Module Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPSTAT register.
+//
+//*****************************************************************************
+#define HIB_TPSTAT_STATE_M      0x0000000C  // Tamper Module Status
+#define HIB_TPSTAT_STATE_DISABLED                                             \
+                                0x00000000  // Tamper disabled
+#define HIB_TPSTAT_STATE_CONFIGED                                             \
+                                0x00000004  // Tamper configured
+#define HIB_TPSTAT_STATE_ERROR  0x00000008  // Tamper pin event occurred
+#define HIB_TPSTAT_XOSCST       0x00000002  // External Oscillator Status
+#define HIB_TPSTAT_XOSCFAIL     0x00000001  // External Oscillator Failure
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPIO register.
+//
+//*****************************************************************************
+#define HIB_TPIO_GFLTR3         0x08000000  // TMPR3 Glitch Filtering
+#define HIB_TPIO_PUEN3          0x04000000  // TMPR3 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV3           0x02000000  // TMPR3 Trigger Level
+#define HIB_TPIO_EN3            0x01000000  // TMPR3 Enable
+#define HIB_TPIO_GFLTR2         0x00080000  // TMPR2 Glitch Filtering
+#define HIB_TPIO_PUEN2          0x00040000  // TMPR2 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV2           0x00020000  // TMPR2 Trigger Level
+#define HIB_TPIO_EN2            0x00010000  // TMPR2 Enable
+#define HIB_TPIO_GFLTR1         0x00000800  // TMPR1 Glitch Filtering
+#define HIB_TPIO_PUEN1          0x00000400  // TMPR1 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV1           0x00000200  // TMPR1 Trigger Level
+#define HIB_TPIO_EN1            0x00000100  // TMPR1Enable
+#define HIB_TPIO_GFLTR0         0x00000008  // TMPR0 Glitch Filtering
+#define HIB_TPIO_PUEN0          0x00000004  // TMPR0 Internal Weak Pull-up
+                                            // Enable
+#define HIB_TPIO_LEV0           0x00000002  // TMPR0 Trigger Level
+#define HIB_TPIO_EN0            0x00000001  // TMPR0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG0 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG0_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG0_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG1 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG1_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG1_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG1_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG1_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG1_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG2 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG2_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG2_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG3 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG3_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG3_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG3_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG3_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG3_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG4 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG4_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG4_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG5 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG5_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG5_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG5_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG5_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG5_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG6 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG6_TIME_M       0xFFFFFFFF  // Tamper Log Calendar Information
+#define HIB_TPLOG6_TIME_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG7 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG7_XOSC         0x00010000  // Status of external 32
+#define HIB_TPLOG7_TRIG3        0x00000008  // Status of TMPR[3] Trigger
+#define HIB_TPLOG7_TRIG2        0x00000004  // Status of TMPR[2] Trigger
+#define HIB_TPLOG7_TRIG1        0x00000002  // Status of TMPR[1] Trigger
+#define HIB_TPLOG7_TRIG0        0x00000001  // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_PP register.
+//
+//*****************************************************************************
+#define HIB_PP_TAMPER           0x00000002  // Tamper Pin Presence
+#define HIB_PP_WAKENC           0x00000001  // Wake Pin Presence
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CC register.
+//
+//*****************************************************************************
+#define HIB_CC_SYSCLKEN         0x00000001  // RTCOSC to System Clock Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x000FFFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS     0x00002000  // Program Verify Error Raw
+                                            // Interrupt Status
+#define FLASH_FCRIS_ERRIS       0x00000800  // Erase Verify Error Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_INVDRIS     0x00000400  // Invalid Data Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_VOLTRIS     0x00000200  // Pump Voltage Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_ERIS        0x00000004  // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK     0x00002000  // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK       0x00000800  // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK     0x00000400  // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK     0x00000200  // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK        0x00000004  // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC   0x00002000  // PROGVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_ERMISC     0x00000800  // ERVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_INVDMISC   0x00000400  // Invalid Data Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_VOLTMISC   0x00000200  // VOLT Masked Interrupt Status and
+                                            // Clear
+#define FLASH_FCMISC_EMISC      0x00000004  // EEPROM Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FLPEKEY register.
+//
+//*****************************************************************************
+#define FLASH_FLPEKEY_PEKEY_M   0x0000FFFF  // Key Value
+#define FLASH_FLPEKEY_PEKEY_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_PP register.
+//
+//*****************************************************************************
+#define FLASH_PP_PFC            0x40000000  // Prefetch Buffer Mode
+#define FLASH_PP_FMM            0x20000000  // Flash Mirror Mode
+#define FLASH_PP_DFA            0x10000000  // DMA Flash Access
+#define FLASH_PP_EESS_M         0x00780000  // EEPROM Sector Size of the
+                                            // physical bank
+#define FLASH_PP_EESS_1KB       0x00000000  // 1 KB
+#define FLASH_PP_EESS_2KB       0x00080000  // 2 KB
+#define FLASH_PP_EESS_4KB       0x00100000  // 4 KB
+#define FLASH_PP_EESS_8KB       0x00180000  // 8 KB
+#define FLASH_PP_MAINSS_M       0x00070000  // Flash Sector Size of the
+                                            // physical bank
+#define FLASH_PP_MAINSS_1KB     0x00000000  // 1 KB
+#define FLASH_PP_MAINSS_2KB     0x00010000  // 2 KB
+#define FLASH_PP_MAINSS_4KB     0x00020000  // 4 KB
+#define FLASH_PP_MAINSS_8KB     0x00030000  // 8 KB
+#define FLASH_PP_MAINSS_16KB    0x00040000  // 16 KB
+#define FLASH_PP_SIZE_M         0x0000FFFF  // Flash Size
+#define FLASH_PP_SIZE_1MB       0x000001FF  // 1024 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M      0x0000FFFF  // SRAM Size
+#define FLASH_SSIZE_SIZE_256KB  0x000003FF  // 256 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CONF register.
+//
+//*****************************************************************************
+#define FLASH_CONF_FMME         0x40000000  // Flash Mirror Mode Enable
+#define FLASH_CONF_SPFE         0x20000000  // Single Prefetch Mode Enable
+#define FLASH_CONF_CLRTV        0x00100000  // Clear Valid Tags
+#define FLASH_CONF_FPFON        0x00020000  // Force Prefetch On
+#define FLASH_CONF_FPFOFF       0x00010000  // Force Prefetch Off
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SW7EN_M  0x0000C000  // ROM SW Region 7 Availability
+#define FLASH_ROMSWMAP_SW7EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW7EN_CORE                                             \
+                                0x00004000  // Region available to core
+#define FLASH_ROMSWMAP_SW6EN_M  0x00003000  // ROM SW Region 6 Availability
+#define FLASH_ROMSWMAP_SW6EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW6EN_CORE                                             \
+                                0x00001000  // Region available to core
+#define FLASH_ROMSWMAP_SW5EN_M  0x00000C00  // ROM SW Region 5 Availability
+#define FLASH_ROMSWMAP_SW5EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW5EN_CORE                                             \
+                                0x00000400  // Region available to core
+#define FLASH_ROMSWMAP_SW4EN_M  0x00000300  // ROM SW Region 4 Availability
+#define FLASH_ROMSWMAP_SW4EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW4EN_CORE                                             \
+                                0x00000100  // Region available to core
+#define FLASH_ROMSWMAP_SW3EN_M  0x000000C0  // ROM SW Region 3 Availability
+#define FLASH_ROMSWMAP_SW3EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW3EN_CORE                                             \
+                                0x00000040  // Region available to core
+#define FLASH_ROMSWMAP_SW2EN_M  0x00000030  // ROM SW Region 2 Availability
+#define FLASH_ROMSWMAP_SW2EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW2EN_CORE                                             \
+                                0x00000010  // Region available to core
+#define FLASH_ROMSWMAP_SW1EN_M  0x0000000C  // ROM SW Region 1 Availability
+#define FLASH_ROMSWMAP_SW1EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW1EN_CORE                                             \
+                                0x00000004  // Region available to core
+#define FLASH_ROMSWMAP_SW0EN_M  0x00000003  // ROM SW Region 0 Availability
+#define FLASH_ROMSWMAP_SW0EN_NOTVIS                                           \
+                                0x00000000  // Software region not available to
+                                            // the core
+#define FLASH_ROMSWMAP_SW0EN_CORE                                             \
+                                0x00000001  // Region available to core
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMASZ register.
+//
+//*****************************************************************************
+#define FLASH_DMASZ_SIZE_M      0x0003FFFF  // uDMA-accessible Memory Size
+#define FLASH_DMASZ_SIZE_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMAST register.
+//
+//*****************************************************************************
+#define FLASH_DMAST_ADDR_M      0x1FFFF800  // Contains the starting address of
+                                            // the flash region accessible by
+                                            // uDMA if the FLASHPP register DFA
+                                            // bit is set
+#define FLASH_DMAST_ADDR_S      11
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RVP register.
+//
+//*****************************************************************************
+#define FLASH_RVP_RV_M          0xFFFFFFFF  // Reset Vector Pointer Address
+#define FLASH_RVP_RV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY       0x00000010  // KEY Select
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG3_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE8_READ_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE8_READ_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE9_READ_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE9_READ_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE10_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE10_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE11_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE11_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE12_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE12_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE13_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE13_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE14_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE14_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE15_READ_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Read Enable
+#define FLASH_FMPRE15_READ_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE8_PROG_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE8_PROG_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE9_PROG_ENABLE_M                                            \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE9_PROG_ENABLE_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE10_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE10_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE11_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE11_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE12_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE12_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE13_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE13_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE14_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE14_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE15_PROG_ENABLE_M                                           \
+                                0xFFFFFFFF  // Flash Programming Enable
+#define FLASH_FMPPE15_PROG_ENABLE_S                                           \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format.
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_TM4C129                                             \
+                                0x000A0000  // Tiva(TM) TM4C129-class
+                                            // microcontrollers
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
+#define SYSCTL_DID1_VER_1       0x10000000  // fury_ib
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
+#define SYSCTL_DID1_FAM_TIVA    0x00000000  // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD                                       \
+                                0x00320000  // TM4C129XNCZAD
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin LQFP package
+#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin LQFP package
+#define SYSCTL_DID1_PINCNT_144  0x00008000  // 144-pin LQFP package
+#define SYSCTL_DID1_PINCNT_157  0x0000A000  // 157-pin BGA package
+#define SYSCTL_DID1_PINCNT_128  0x0000C000  // 128-pin TQFP package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // QFP package
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PTBOCTL_VDDA_UBOR_M                                            \
+                                0x00000300  // VDDA under BOR Event Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE                                         \
+                                0x00000000  // No Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT                                       \
+                                0x00000100  // System control interrupt
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI                                          \
+                                0x00000200  // NMI
+#define SYSCTL_PTBOCTL_VDDA_UBOR_RST                                          \
+                                0x00000300  // Reset
+#define SYSCTL_PTBOCTL_VDD_UBOR_M                                             \
+                                0x00000003  // VDD (VDDS) under BOR Event
+                                            // Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_NONE                                          \
+                                0x00000000  // No Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT                                        \
+                                0x00000001  // System control interrupt
+#define SYSCTL_PTBOCTL_VDD_UBOR_NMI                                           \
+                                0x00000002  // NMI
+#define SYSCTL_PTBOCTL_VDD_UBOR_RST                                           \
+                                0x00000003  // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Failure Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Failure
+                                            // Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Failure Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_HSSR        0x00001000  // HSSR Reset
+#define SYSCTL_RESC_HIB         0x00000040  // HIB Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PWRTC register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR  0x00000010  // VDDA Under BOR Status
+#define SYSCTL_PWRTC_VDD_UBOR   0x00000001  // VDD Under BOR Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NMIC register.
+//
+//*****************************************************************************
+#define SYSCTL_NMIC_MOSCFAIL    0x00010000  // MOSC Failure NMI
+#define SYSCTL_NMIC_TAMPER      0x00000200  // Tamper Event NMI
+#define SYSCTL_NMIC_WDT1        0x00000020  // Watch Dog Timer (WDT) 1 NMI
+#define SYSCTL_NMIC_WDT0        0x00000008  // Watch Dog Timer (WDT) 0 NMI
+#define SYSCTL_NMIC_POWER       0x00000004  // Power/Brown Out Event NMI
+#define SYSCTL_NMIC_EXTERNAL    0x00000001  // External Pin NMI
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_OSCRNG   0x00000010  // Oscillator Range
+#define SYSCTL_MOSCCTL_PWRDN    0x00000008  // Power Down
+#define SYSCTL_MOSCCTL_NOXTAL   0x00000004  // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM   0x00000002  // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000  // Memory Timing Register Update
+#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000  // New PLLFREQ Accept
+#define SYSCTL_RSCLKCFG_ACG     0x20000000  // Auto Clock Gating
+#define SYSCTL_RSCLKCFG_USEPLL  0x10000000  // Use PLL
+#define SYSCTL_RSCLKCFG_PLLSRC_M                                              \
+                                0x0F000000  // PLL Source
+#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC                                          \
+                                0x00000000  // PIOSC is PLL input clock source
+#define SYSCTL_RSCLKCFG_PLLSRC_MOSC                                           \
+                                0x03000000  // MOSC is the PLL input clock
+                                            // source
+#define SYSCTL_RSCLKCFG_OSCSRC_M                                              \
+                                0x00F00000  // Oscillator Source
+#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC                                          \
+                                0x00000000  // PIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC                                         \
+                                0x00200000  // LFIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_MOSC                                           \
+                                0x00300000  // MOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_RTC                                            \
+                                0x00400000  // Hibernation Module RTC
+                                            // Oscillator (RTCOSC)
+#define SYSCTL_RSCLKCFG_OSYSDIV_M                                             \
+                                0x000FFC00  // Oscillator System Clock Divisor
+#define SYSCTL_RSCLKCFG_PSYSDIV_M                                             \
+                                0x000003FF  // PLL System Clock Divisor
+#define SYSCTL_RSCLKCFG_OSYSDIV_S                                             \
+                                10
+#define SYSCTL_RSCLKCFG_PSYSDIV_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
+//
+//*****************************************************************************
+#define SYSCTL_MEMTIM0_EBCHT_M  0x03C00000  // EEPROM Clock High Time
+#define SYSCTL_MEMTIM0_EBCHT_0_5                                              \
+                                0x00000000  // 1/2 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1  0x00400000  // 1 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1_5                                              \
+                                0x00800000  // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2  0x00C00000  // 2 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2_5                                              \
+                                0x01000000  // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3  0x01400000  // 3 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3_5                                              \
+                                0x01800000  // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4  0x01C00000  // 4 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4_5                                              \
+                                0x02000000  // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCE     0x00200000  // EEPROM Bank Clock Edge
+#define SYSCTL_MEMTIM0_EWS_M    0x000F0000  // EEPROM Wait States
+#define SYSCTL_MEMTIM0_FBCHT_M  0x000003C0  // Flash Bank Clock High Time
+#define SYSCTL_MEMTIM0_FBCHT_0_5                                              \
+                                0x00000000  // 1/2 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1  0x00000040  // 1 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1_5                                              \
+                                0x00000080  // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2  0x000000C0  // 2 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2_5                                              \
+                                0x00000100  // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3  0x00000140  // 3 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3_5                                              \
+                                0x00000180  // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4  0x000001C0  // 4 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4_5                                              \
+                                0x00000200  // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCE     0x00000020  // Flash Bank Clock Edge
+#define SYSCTL_MEMTIM0_FWS_M    0x0000000F  // Flash Wait State
+#define SYSCTL_MEMTIM0_EWS_S    16
+#define SYSCTL_MEMTIM0_FWS_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_ALTCLKCFG_ALTCLK_M                                             \
+                                0x0000000F  // Alternate Clock Source
+#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC                                         \
+                                0x00000000  // PIOSC
+#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC                                        \
+                                0x00000003  // Hibernation Module Real-time
+                                            // clock output (RTCOSC)
+#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC                                        \
+                                0x00000004  // Low-frequency internal
+                                            // oscillator (LFIOSC)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000  // PIOSC Power Down
+#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000  // MOSC Disable Power Down
+#define SYSCTL_DSCLKCFG_DSOSCSRC_M                                            \
+                                0x00F00000  // Deep Sleep Oscillator Source
+#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC                                        \
+                                0x00000000  // PIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC                                       \
+                                0x00200000  // LFIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC                                         \
+                                0x00300000  // MOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC                                          \
+                                0x00400000  // Hibernation Module RTCOSC
+#define SYSCTL_DSCLKCFG_DSSYSDIV_M                                            \
+                                0x000003FF  // Deep Sleep Clock Divisor
+#define SYSCTL_DSCLKCFG_DSSYSDIV_S                                            \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
+//
+//*****************************************************************************
+#define SYSCTL_DIVSCLK_EN       0x80000000  // DIVSCLK Enable
+#define SYSCTL_DIVSCLK_SRC_M    0x00030000  // Clock Source
+#define SYSCTL_DIVSCLK_SRC_SYSCLK                                             \
+                                0x00000000  // System Clock
+#define SYSCTL_DIVSCLK_SRC_PIOSC                                              \
+                                0x00010000  // PIOSC
+#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000  // MOSC
+#define SYSCTL_DIVSCLK_DIV_M    0x000000FF  // Divisor Value
+#define SYSCTL_DIVSCLK_DIV_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU      0x00000001  // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000  // Calibration has not been
+                                            // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100  // The last calibration operation
+                                            // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200  // The last calibration operation
+                                            // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S   16
+#define SYSCTL_PIOSCSTAT_CT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_PLLPWR  0x00800000  // PLL Power
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00  // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M  0x000003FF  // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M     0x00001F00  // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M     0x0000001F  // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S     8
+#define SYSCTL_PLLFREQ1_N_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK     0x00000001  // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SLPPWRCFG_FLASHPM_M                                            \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_SLPPWRCFG_FLASHPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_FLASHPM_SLP                                          \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_M                                             \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_SLPPWRCFG_SRAMPM_NRM                                           \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_SBY                                           \
+                                0x00000001  // Standby Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_LP                                            \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200  // LDO Sleep Mode
+#define SYSCTL_DSLPPWRCFG_TSPD  0x00000100  // Temperature Sense Power Down
+#define SYSCTL_DSLPPWRCFG_FLASHPM_M                                           \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM                                         \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP                                         \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_M                                            \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY                                          \
+                                0x00000001  // Standby Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_LP                                           \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
+                                            // Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOSPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDOSPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDOSPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDOSPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDOSPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDOSPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDOSPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDOSPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDOSPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDODPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDODPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDODPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDODPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDODPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDODPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDODPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDODPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDODPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDODPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+#define SYSCTL_LDODPCTL_VLDO_1_25V                                            \
+                                0x00000019  // 1.25 V
+#define SYSCTL_LDODPCTL_VLDO_1_30V                                            \
+                                0x0000001A  // 1.30 V
+#define SYSCTL_LDODPCTL_VLDO_1_35V                                            \
+                                0x0000001B  // 1.35 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESBEHAVCTL_WDOG1_M                                            \
+                                0x000000C0  // Watchdog 1 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST                                       \
+                                0x00000080  // Watchdog 1 issues a system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG1_POR                                          \
+                                0x000000C0  // Watchdog 1 issues a simulated
+                                            // POR sequence. Application starts
+                                            // less than 500 us after
+                                            // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_WDOG0_M                                            \
+                                0x00000030  // Watchdog 0 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST                                       \
+                                0x00000020  // Watchdog 0 issues a system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG0_POR                                          \
+                                0x00000030  // Watchdog 0 issues a simulated
+                                            // POR sequence. Application starts
+                                            // less than 500 us after
+                                            // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_BOR_M                                              \
+                                0x0000000C  // BOR Reset operation
+#define SYSCTL_RESBEHAVCTL_BOR_SYSRST                                         \
+                                0x00000008  // Brown Out Reset issues system
+                                            // reset. The application starts
+                                            // within 10 us
+#define SYSCTL_RESBEHAVCTL_BOR_POR                                            \
+                                0x0000000C  // Brown Out Reset issues a
+                                            // simulated POR sequence. The
+                                            // application starts less than 500
+                                            // us after deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_EXTRES_M                                           \
+                                0x00000003  // External RST Pin Operation
+#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST                                      \
+                                0x00000002  // External RST assertion issues a
+                                            // system reset. The application
+                                            // starts within 10 us
+#define SYSCTL_RESBEHAVCTL_EXTRES_POR                                         \
+                                0x00000003  // External RST assertion issues a
+                                            // simulated POR sequence.
+                                            // Application starts less than 500
+                                            // us after deassertion (Default)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_HSSR register.
+//
+//*****************************************************************************
+#define SYSCTL_HSSR_KEY_M       0xFF000000  // Write Key
+#define SYSCTL_HSSR_CDOFF_M     0x00FFFFFF  // Command Descriptor Pointer
+#define SYSCTL_HSSR_KEY_S       24
+#define SYSCTL_HSSR_CDOFF_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C  // Memory Array Power Status
+#define SYSCTL_USBPDS_MEMSTAT_OFF                                             \
+                                0x00000000  // Array OFF
+#define SYSCTL_USBPDS_MEMSTAT_RETAIN                                          \
+                                0x00000004  // SRAM Retention
+#define SYSCTL_USBPDS_MEMSTAT_ON                                              \
+                                0x0000000C  // Array On
+#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003  // Power Domain Status
+#define SYSCTL_USBPDS_PWRSTAT_OFF                                             \
+                                0x00000000  // OFF
+#define SYSCTL_USBPDS_PWRSTAT_ON                                              \
+                                0x00000003  // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_USBMPC_PWRCTL_M  0x00000003  // Memory Array Power Control
+#define SYSCTL_USBMPC_PWRCTL_OFF                                              \
+                                0x00000000  // Array OFF
+#define SYSCTL_USBMPC_PWRCTL_RETAIN                                           \
+                                0x00000001  // SRAM Retention
+#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACPDS_MEMSTAT_M                                              \
+                                0x0000000C  // Memory Array Power Status
+#define SYSCTL_EMACPDS_MEMSTAT_OFF                                            \
+                                0x00000000  // Array OFF
+#define SYSCTL_EMACPDS_MEMSTAT_ON                                             \
+                                0x0000000C  // Array On
+#define SYSCTL_EMACPDS_PWRSTAT_M                                              \
+                                0x00000003  // Power Domain Status
+#define SYSCTL_EMACPDS_PWRSTAT_OFF                                            \
+                                0x00000000  // OFF
+#define SYSCTL_EMACPDS_PWRSTAT_ON                                             \
+                                0x00000003  // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003  // Memory Array Power Control
+#define SYSCTL_EMACMPC_PWRCTL_OFF                                             \
+                                0x00000000  // Array OFF
+#define SYSCTL_EMACMPC_PWRCTL_ON                                              \
+                                0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LCDMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_LCDMPC_PWRCTL_M  0x00000003  // Memory Array Power Control
+#define SYSCTL_LCDMPC_PWRCTL_OFF                                              \
+                                0x00000000  // Array OFF
+#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003  // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1          0x00000002  // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0          0x00000001  // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Present
+#define SYSCTL_PPTIMER_P6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Present
+#define SYSCTL_PPTIMER_P5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Present
+#define SYSCTL_PPTIMER_P4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Present
+#define SYSCTL_PPTIMER_P3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Present
+#define SYSCTL_PPTIMER_P2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Present
+#define SYSCTL_PPTIMER_P1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Present
+#define SYSCTL_PPTIMER_P0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P17       0x00020000  // GPIO Port T Present
+#define SYSCTL_PPGPIO_P16       0x00010000  // GPIO Port S Present
+#define SYSCTL_PPGPIO_P15       0x00008000  // GPIO Port R Present
+#define SYSCTL_PPGPIO_P14       0x00004000  // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13       0x00002000  // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12       0x00001000  // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11       0x00000800  // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10       0x00000400  // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9        0x00000200  // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8        0x00000100  // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7        0x00000080  // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6        0x00000040  // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5        0x00000020  // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4        0x00000010  // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3        0x00000008  // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2        0x00000004  // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1        0x00000002  // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0         0x00000001  // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPI_P0         0x00000001  // EPI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0         0x00000001  // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7        0x00000080  // UART Module 7 Present
+#define SYSCTL_PPUART_P6        0x00000040  // UART Module 6 Present
+#define SYSCTL_PPUART_P5        0x00000020  // UART Module 5 Present
+#define SYSCTL_PPUART_P4        0x00000010  // UART Module 4 Present
+#define SYSCTL_PPUART_P3        0x00000008  // UART Module 3 Present
+#define SYSCTL_PPUART_P2        0x00000004  // UART Module 2 Present
+#define SYSCTL_PPUART_P1        0x00000002  // UART Module 1 Present
+#define SYSCTL_PPUART_P0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3         0x00000008  // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2         0x00000004  // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1         0x00000002  // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0         0x00000001  // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P9         0x00000200  // I2C Module 9 Present
+#define SYSCTL_PPI2C_P8         0x00000100  // I2C Module 8 Present
+#define SYSCTL_PPI2C_P7         0x00000080  // I2C Module 7 Present
+#define SYSCTL_PPI2C_P6         0x00000040  // I2C Module 6 Present
+#define SYSCTL_PPI2C_P5         0x00000020  // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4         0x00000010  // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3         0x00000008  // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2         0x00000004  // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1         0x00000002  // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0         0x00000001  // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0         0x00000001  // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPHY_P0        0x00000001  // Ethernet PHY Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1         0x00000002  // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0         0x00000001  // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1         0x00000002  // ADC Module 1 Present
+#define SYSCTL_PPADC_P0         0x00000001  // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0        0x00000001  // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P0         0x00000001  // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P0         0x00000001  // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLPC_P0         0x00000001  // LPC Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPECI_P0        0x00000001  // PECI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPFAN_P0         0x00000001  // FAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0      0x00000001  // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPRTS register.
+//
+//*****************************************************************************
+#define SYSCTL_PPRTS_P0         0x00000001  // RTS Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCCM_P0         0x00000001  // CRC and Cryptographic Modules
+                                            // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLCD_P0         0x00000001  // LCD Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PPOWIRE_P0       0x00000001  // 1-Wire Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEMAC_P0        0x00000001  // Ethernet Controller Module
+                                            // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIM_P0         0x00000001  // HIM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1          0x00000002  // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0          0x00000001  // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Software Reset
+#define SYSCTL_SRTIMER_R6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Software Reset
+#define SYSCTL_SRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Software Reset
+#define SYSCTL_SRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Software Reset
+#define SYSCTL_SRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Software Reset
+#define SYSCTL_SRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Software Reset
+#define SYSCTL_SRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Software Reset
+#define SYSCTL_SRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R17       0x00020000  // GPIO Port T Software Reset
+#define SYSCTL_SRGPIO_R16       0x00010000  // GPIO Port S Software Reset
+#define SYSCTL_SRGPIO_R15       0x00008000  // GPIO Port R Software Reset
+#define SYSCTL_SRGPIO_R14       0x00004000  // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13       0x00002000  // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12       0x00001000  // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11       0x00000800  // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10       0x00000400  // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9        0x00000200  // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8        0x00000100  // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7        0x00000080  // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6        0x00000040  // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5        0x00000020  // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4        0x00000010  // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3        0x00000008  // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2        0x00000004  // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1        0x00000002  // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0        0x00000001  // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0         0x00000001  // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPI_R0         0x00000001  // EPI Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0         0x00000001  // Hibernation Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7        0x00000080  // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6        0x00000040  // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5        0x00000020  // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4        0x00000010  // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3        0x00000008  // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2        0x00000004  // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1        0x00000002  // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0        0x00000001  // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3         0x00000008  // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2         0x00000004  // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1         0x00000002  // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0         0x00000001  // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R9         0x00000200  // I2C Module 9 Software Reset
+#define SYSCTL_SRI2C_R8         0x00000100  // I2C Module 8 Software Reset
+#define SYSCTL_SRI2C_R7         0x00000080  // I2C Module 7 Software Reset
+#define SYSCTL_SRI2C_R6         0x00000040  // I2C Module 6 Software Reset
+#define SYSCTL_SRI2C_R5         0x00000020  // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4         0x00000010  // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3         0x00000008  // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2         0x00000004  // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1         0x00000002  // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0         0x00000001  // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0         0x00000001  // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPHY_R0        0x00000001  // Ethernet PHY Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1         0x00000002  // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0         0x00000001  // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1         0x00000002  // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0         0x00000001  // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R0         0x00000001  // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R0         0x00000001  // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0      0x00000001  // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCCM_R0         0x00000001  // CRC and Cryptographic Modules
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRLCD_R0         0x00000001  // LCD Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_SROWIRE_R0       0x00000001  // 1-Wire Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_SREMAC_R0        0x00000001  // Ethernet Controller MAC Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1        0x00000002  // Watchdog Timer 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCWD_R0        0x00000001  // Watchdog Timer 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R17     0x00020000  // GPIO Port T Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R16     0x00010000  // GPIO Port S Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R15     0x00008000  // GPIO Port R Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R14     0x00004000  // GPIO Port Q Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R13     0x00002000  // GPIO Port P Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R12     0x00001000  // GPIO Port N Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R11     0x00000800  // GPIO Port M Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R10     0x00000400  // GPIO Port L Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R9      0x00000200  // GPIO Port K Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R8      0x00000100  // GPIO Port J Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R7      0x00000080  // GPIO Port H Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R6      0x00000040  // GPIO Port G Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R5      0x00000020  // GPIO Port F Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R4      0x00000010  // GPIO Port E Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R3      0x00000008  // GPIO Port D Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R2      0x00000004  // GPIO Port C Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R1      0x00000002  // GPIO Port B Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R0      0x00000001  // GPIO Port A Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0       0x00000001  // uDMA Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPI_R0       0x00000001  // EPI Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0       0x00000001  // Hibernation Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7      0x00000080  // UART Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R6      0x00000040  // UART Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R5      0x00000020  // UART Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R4      0x00000010  // UART Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R3      0x00000008  // UART Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R2      0x00000004  // UART Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R1      0x00000002  // UART Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R0      0x00000001  // UART Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3       0x00000008  // SSI Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R2       0x00000004  // SSI Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R1       0x00000002  // SSI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R0       0x00000001  // SSI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R9       0x00000200  // I2C Module 9 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R8       0x00000100  // I2C Module 8 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R7       0x00000080  // I2C Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R6       0x00000040  // I2C Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R5       0x00000020  // I2C Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R4       0x00000010  // I2C Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R3       0x00000008  // I2C Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R2       0x00000004  // I2C Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R1       0x00000002  // I2C Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R0       0x00000001  // I2C Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0       0x00000001  // USB Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPHY_R0      0x00000001  // Ethernet PHY Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1       0x00000002  // CAN Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCCAN_R0       0x00000001  // CAN Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0      0x00000001  // Analog Comparator Module 0 Run
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R0       0x00000001  // PWM Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R0       0x00000001  // QEI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0    0x00000001  // EEPROM Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCCM_R0       0x00000001  // CRC and Cryptographic Modules
+                                            // Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCLCD_R0       0x00000001  // LCD Controller Module 0 Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCOWIRE_R0     0x00000001  // 1-Wire Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEMAC_R0      0x00000001  // Ethernet MAC Module 0 Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1        0x00000002  // Watchdog Timer 1 Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCWD_S0        0x00000001  // Watchdog Timer 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S17     0x00020000  // GPIO Port T Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S16     0x00010000  // GPIO Port S Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S15     0x00008000  // GPIO Port R Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S14     0x00004000  // GPIO Port Q Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S13     0x00002000  // GPIO Port P Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S12     0x00001000  // GPIO Port N Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S11     0x00000800  // GPIO Port M Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S10     0x00000400  // GPIO Port L Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S9      0x00000200  // GPIO Port K Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S8      0x00000100  // GPIO Port J Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S7      0x00000080  // GPIO Port H Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S6      0x00000040  // GPIO Port G Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S5      0x00000020  // GPIO Port F Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S4      0x00000010  // GPIO Port E Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S3      0x00000008  // GPIO Port D Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S2      0x00000004  // GPIO Port C Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S1      0x00000002  // GPIO Port B Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S0      0x00000001  // GPIO Port A Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0       0x00000001  // uDMA Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPI_S0       0x00000001  // EPI Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0       0x00000001  // Hibernation Module Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7      0x00000080  // UART Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S6      0x00000040  // UART Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S5      0x00000020  // UART Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S4      0x00000010  // UART Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S3      0x00000008  // UART Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S2      0x00000004  // UART Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S1      0x00000002  // UART Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S0      0x00000001  // UART Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3       0x00000008  // SSI Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S2       0x00000004  // SSI Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S1       0x00000002  // SSI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S0       0x00000001  // SSI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S9       0x00000200  // I2C Module 9 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S8       0x00000100  // I2C Module 8 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S7       0x00000080  // I2C Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S6       0x00000040  // I2C Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S5       0x00000020  // I2C Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S4       0x00000010  // I2C Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S3       0x00000008  // I2C Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S2       0x00000004  // I2C Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S1       0x00000002  // I2C Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S0       0x00000001  // I2C Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0       0x00000001  // USB Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPHY_S0      0x00000001  // PHY Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1       0x00000002  // CAN Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCCAN_S0       0x00000001  // CAN Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1       0x00000002  // ADC Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCADC_S0       0x00000001  // ADC Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0      0x00000001  // Analog Comparator Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S0       0x00000001  // PWM Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S0       0x00000001  // QEI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0    0x00000001  // EEPROM Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCCM_S0       0x00000001  // CRC and Cryptographic Modules
+                                            // Sleep Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCLCD_S0       0x00000001  // LCD Controller Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCOWIRE_S0     0x00000001  // 1-Wire Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEMAC_S0      0x00000001  // Ethernet MAC Module 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1        0x00000002  // Watchdog Timer 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCWD_D0        0x00000001  // Watchdog Timer 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D7     0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D6     0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D17     0x00020000  // GPIO Port T Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D16     0x00010000  // GPIO Port S Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D15     0x00008000  // GPIO Port R Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D14     0x00004000  // GPIO Port Q Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13     0x00002000  // GPIO Port P Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12     0x00001000  // GPIO Port N Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11     0x00000800  // GPIO Port M Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10     0x00000400  // GPIO Port L Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9      0x00000200  // GPIO Port K Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8      0x00000100  // GPIO Port J Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7      0x00000080  // GPIO Port H Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6      0x00000040  // GPIO Port G Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5      0x00000020  // GPIO Port F Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4      0x00000010  // GPIO Port E Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3      0x00000008  // GPIO Port D Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2      0x00000004  // GPIO Port C Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1      0x00000002  // GPIO Port B Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0      0x00000001  // GPIO Port A Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0       0x00000001  // uDMA Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPI_D0       0x00000001  // EPI Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0       0x00000001  // Hibernation Module Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7      0x00000080  // UART Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D6      0x00000040  // UART Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D5      0x00000020  // UART Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D4      0x00000010  // UART Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D3      0x00000008  // UART Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D2      0x00000004  // UART Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D1      0x00000002  // UART Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D0      0x00000001  // UART Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3       0x00000008  // SSI Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2       0x00000004  // SSI Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1       0x00000002  // SSI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0       0x00000001  // SSI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D9       0x00000200  // I2C Module 9 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D8       0x00000100  // I2C Module 8 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D7       0x00000080  // I2C Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D6       0x00000040  // I2C Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D5       0x00000020  // I2C Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4       0x00000010  // I2C Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3       0x00000008  // I2C Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2       0x00000004  // I2C Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1       0x00000002  // I2C Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0       0x00000001  // I2C Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0       0x00000001  // USB Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPHY_D0      0x00000001  // PHY Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1       0x00000002  // CAN Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0       0x00000001  // CAN Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1       0x00000002  // ADC Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCADC_D0       0x00000001  // ADC Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0      0x00000001  // Analog Comparator Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D0       0x00000001  // PWM Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D0       0x00000001  // QEI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0    0x00000001  // EEPROM Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCCM_D0       0x00000001  // CRC and Cryptographic Modules
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCLCD_D0       0x00000001  // LCD Controller Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCOWIRE_D0     0x00000001  // 1-Wire Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEMAC_D0      0x00000001  // Ethernet MAC Module 0 Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWD_P1          0x00000002  // Watchdog Timer 1 Power Control
+#define SYSCTL_PCWD_P0          0x00000001  // Watchdog Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PCTIMER_P7       0x00000080  // General-Purpose Timer 7 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P6       0x00000040  // General-Purpose Timer 6 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P5       0x00000020  // General-Purpose Timer 5 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P4       0x00000010  // General-Purpose Timer 4 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P3       0x00000008  // General-Purpose Timer 3 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P2       0x00000004  // General-Purpose Timer 2 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P1       0x00000002  // General-Purpose Timer 1 Power
+                                            // Control
+#define SYSCTL_PCTIMER_P0       0x00000001  // General-Purpose Timer 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PCGPIO_P17       0x00020000  // GPIO Port T Power Control
+#define SYSCTL_PCGPIO_P16       0x00010000  // GPIO Port S Power Control
+#define SYSCTL_PCGPIO_P15       0x00008000  // GPIO Port R Power Control
+#define SYSCTL_PCGPIO_P14       0x00004000  // GPIO Port Q Power Control
+#define SYSCTL_PCGPIO_P13       0x00002000  // GPIO Port P Power Control
+#define SYSCTL_PCGPIO_P12       0x00001000  // GPIO Port N Power Control
+#define SYSCTL_PCGPIO_P11       0x00000800  // GPIO Port M Power Control
+#define SYSCTL_PCGPIO_P10       0x00000400  // GPIO Port L Power Control
+#define SYSCTL_PCGPIO_P9        0x00000200  // GPIO Port K Power Control
+#define SYSCTL_PCGPIO_P8        0x00000100  // GPIO Port J Power Control
+#define SYSCTL_PCGPIO_P7        0x00000080  // GPIO Port H Power Control
+#define SYSCTL_PCGPIO_P6        0x00000040  // GPIO Port G Power Control
+#define SYSCTL_PCGPIO_P5        0x00000020  // GPIO Port F Power Control
+#define SYSCTL_PCGPIO_P4        0x00000010  // GPIO Port E Power Control
+#define SYSCTL_PCGPIO_P3        0x00000008  // GPIO Port D Power Control
+#define SYSCTL_PCGPIO_P2        0x00000004  // GPIO Port C Power Control
+#define SYSCTL_PCGPIO_P1        0x00000002  // GPIO Port B Power Control
+#define SYSCTL_PCGPIO_P0        0x00000001  // GPIO Port A Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PCDMA_P0         0x00000001  // uDMA Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPI_P0         0x00000001  // EPI Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCHIB_P0         0x00000001  // Hibernation Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUART_P7        0x00000080  // UART Module 7 Power Control
+#define SYSCTL_PCUART_P6        0x00000040  // UART Module 6 Power Control
+#define SYSCTL_PCUART_P5        0x00000020  // UART Module 5 Power Control
+#define SYSCTL_PCUART_P4        0x00000010  // UART Module 4 Power Control
+#define SYSCTL_PCUART_P3        0x00000008  // UART Module 3 Power Control
+#define SYSCTL_PCUART_P2        0x00000004  // UART Module 2 Power Control
+#define SYSCTL_PCUART_P1        0x00000002  // UART Module 1 Power Control
+#define SYSCTL_PCUART_P0        0x00000001  // UART Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCSSI_P3         0x00000008  // SSI Module 3 Power Control
+#define SYSCTL_PCSSI_P2         0x00000004  // SSI Module 2 Power Control
+#define SYSCTL_PCSSI_P1         0x00000002  // SSI Module 1 Power Control
+#define SYSCTL_PCSSI_P0         0x00000001  // SSI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PCI2C_P9         0x00000200  // I2C Module 9 Power Control
+#define SYSCTL_PCI2C_P8         0x00000100  // I2C Module 8 Power Control
+#define SYSCTL_PCI2C_P7         0x00000080  // I2C Module 7 Power Control
+#define SYSCTL_PCI2C_P6         0x00000040  // I2C Module 6 Power Control
+#define SYSCTL_PCI2C_P5         0x00000020  // I2C Module 5 Power Control
+#define SYSCTL_PCI2C_P4         0x00000010  // I2C Module 4 Power Control
+#define SYSCTL_PCI2C_P3         0x00000008  // I2C Module 3 Power Control
+#define SYSCTL_PCI2C_P2         0x00000004  // I2C Module 2 Power Control
+#define SYSCTL_PCI2C_P1         0x00000002  // I2C Module 1 Power Control
+#define SYSCTL_PCI2C_P0         0x00000001  // I2C Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUSB_P0         0x00000001  // USB Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPHY_P0        0x00000001  // Ethernet PHY Module Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCAN_P1         0x00000002  // CAN Module 1 Power Control
+#define SYSCTL_PCCAN_P0         0x00000001  // CAN Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCADC_P1         0x00000002  // ADC Module 1 Power Control
+#define SYSCTL_PCADC_P0         0x00000001  // ADC Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PCACMP_P0        0x00000001  // Analog Comparator Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCPWM_P0         0x00000001  // PWM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCQEI_P0         0x00000001  // QEI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEEPROM_P0      0x00000001  // EEPROM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCCM_P0         0x00000001  // CRC and Cryptographic Modules
+                                            // Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCLCD_P0         0x00000001  // LCD Controller Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PCOWIRE_P0       0x00000001  // 1-Wire Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEMAC_P0        0x00000001  // Ethernet MAC Module 0 Power
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1          0x00000002  // Watchdog Timer 1 Peripheral
+                                            // Ready
+#define SYSCTL_PRWD_R0          0x00000001  // Watchdog Timer 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R7       0x00000080  // 16/32-Bit General-Purpose Timer
+                                            // 7 Peripheral Ready
+#define SYSCTL_PRTIMER_R6       0x00000040  // 16/32-Bit General-Purpose Timer
+                                            // 6 Peripheral Ready
+#define SYSCTL_PRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R17       0x00020000  // GPIO Port T Peripheral Ready
+#define SYSCTL_PRGPIO_R16       0x00010000  // GPIO Port S Peripheral Ready
+#define SYSCTL_PRGPIO_R15       0x00008000  // GPIO Port R Peripheral Ready
+#define SYSCTL_PRGPIO_R14       0x00004000  // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13       0x00002000  // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12       0x00001000  // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11       0x00000800  // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10       0x00000400  // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9        0x00000200  // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8        0x00000100  // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7        0x00000080  // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6        0x00000040  // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5        0x00000020  // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4        0x00000010  // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3        0x00000008  // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2        0x00000004  // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1        0x00000002  // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0        0x00000001  // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0         0x00000001  // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPI_R0         0x00000001  // EPI Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0         0x00000001  // Hibernation Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7        0x00000080  // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6        0x00000040  // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5        0x00000020  // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4        0x00000010  // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3        0x00000008  // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2        0x00000004  // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1        0x00000002  // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0        0x00000001  // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3         0x00000008  // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2         0x00000004  // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1         0x00000002  // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0         0x00000001  // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R9         0x00000200  // I2C Module 9 Peripheral Ready
+#define SYSCTL_PRI2C_R8         0x00000100  // I2C Module 8 Peripheral Ready
+#define SYSCTL_PRI2C_R7         0x00000080  // I2C Module 7 Peripheral Ready
+#define SYSCTL_PRI2C_R6         0x00000040  // I2C Module 6 Peripheral Ready
+#define SYSCTL_PRI2C_R5         0x00000020  // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4         0x00000010  // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3         0x00000008  // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2         0x00000004  // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1         0x00000002  // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0         0x00000001  // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0         0x00000001  // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPHY_R0        0x00000001  // Ethernet PHY Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1         0x00000002  // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0         0x00000001  // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R0         0x00000001  // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R0         0x00000001  // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0      0x00000001  // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCCM_R0         0x00000001  // CRC and Cryptographic Modules
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRLCD_R0         0x00000001  // LCD Controller Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PROWIRE_R0       0x00000001  // 1-Wire Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PREMAC_R0        0x00000001  // Ethernet MAC Module 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CCMCGREQ
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_CCMCGREQ_DESCFG  0x00000004  // DES Clock Gating Request
+#define SYSCTL_CCMCGREQ_AESCFG  0x00000002  // AES Clock Gating Request
+#define SYSCTL_CCMCGREQ_SHACFG  0x00000001  // SHA/MD5 Clock Gating Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP                                            \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP                                            \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT                                             \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT                                             \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M    0xF0000000  // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M    0x0F000000  // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M    0x00F00000  // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M    0x000F0000  // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M    0x0000F000  // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M    0x00000F00  // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M    0x000000F0  // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M    0x0000000F  // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S    28
+#define UDMA_CHMAP0_CH6SEL_S    24
+#define UDMA_CHMAP0_CH5SEL_S    20
+#define UDMA_CHMAP0_CH4SEL_S    16
+#define UDMA_CHMAP0_CH3SEL_S    12
+#define UDMA_CHMAP0_CH2SEL_S    8
+#define UDMA_CHMAP0_CH1SEL_S    4
+#define UDMA_CHMAP0_CH0SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M   0xF0000000  // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M   0x0F000000  // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M   0x00F00000  // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M   0x000F0000  // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M   0x0000F000  // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M   0x00000F00  // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M    0x000000F0  // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M    0x0000000F  // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S   28
+#define UDMA_CHMAP1_CH14SEL_S   24
+#define UDMA_CHMAP1_CH13SEL_S   20
+#define UDMA_CHMAP1_CH12SEL_S   16
+#define UDMA_CHMAP1_CH11SEL_S   12
+#define UDMA_CHMAP1_CH10SEL_S   8
+#define UDMA_CHMAP1_CH9SEL_S    4
+#define UDMA_CHMAP1_CH8SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M   0xF0000000  // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M   0x0F000000  // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M   0x00F00000  // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M   0x000F0000  // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M   0x0000F000  // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M   0x00000F00  // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M   0x000000F0  // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M   0x0000000F  // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S   28
+#define UDMA_CHMAP2_CH22SEL_S   24
+#define UDMA_CHMAP2_CH21SEL_S   20
+#define UDMA_CHMAP2_CH20SEL_S   16
+#define UDMA_CHMAP2_CH19SEL_S   12
+#define UDMA_CHMAP2_CH18SEL_S   8
+#define UDMA_CHMAP2_CH17SEL_S   4
+#define UDMA_CHMAP2_CH16SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M   0xF0000000  // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M   0x0F000000  // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M   0x00F00000  // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M   0x000F0000  // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M   0x0000F000  // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M   0x00000F00  // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M   0x000000F0  // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M   0x0000000F  // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S   28
+#define UDMA_CHMAP3_CH30SEL_S   24
+#define UDMA_CHMAP3_CH29SEL_S   20
+#define UDMA_CHMAP3_CH28SEL_S   16
+#define UDMA_CHMAP3_CH27SEL_S   12
+#define UDMA_CHMAP3_CH26SEL_S   8
+#define UDMA_CHMAP3_CH25SEL_S   4
+#define UDMA_CHMAP3_CH24SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_DSTPROT0     0x00200000  // Destination Privilege Access
+#define UDMA_CHCTL_SRCPROT0     0x00040000  // Source Privilege Access
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP                                              \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC                                             \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO                                              \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG                                          \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG                                            \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA                                           \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG                                            \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA                                           \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
+//
+//*****************************************************************************
+#define CCM_CRCCTRL_INIT_M      0x00006000  // CRC Initialization
+#define CCM_CRCCTRL_INIT_SEED   0x00000000  // Use the CRCSEED register context
+                                            // as the starting value
+#define CCM_CRCCTRL_INIT_0      0x00004000  // Initialize to all '0s'
+#define CCM_CRCCTRL_INIT_1      0x00006000  // Initialize to all '1s'
+#define CCM_CRCCTRL_SIZE        0x00001000  // Input Data Size
+#define CCM_CRCCTRL_RESINV      0x00000200  // Result Inverse Enable
+#define CCM_CRCCTRL_OBR         0x00000100  // Output Reverse Enable
+#define CCM_CRCCTRL_BR          0x00000080  // Bit reverse enable
+#define CCM_CRCCTRL_ENDIAN_M    0x00000030  // Endian Control
+#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000  // Configuration unchanged. (B3,
+                                            // B2, B1, B0)
+#define CCM_CRCCTRL_ENDIAN_SHW  0x00000010  // Bytes are swapped in half-words
+                                            // but half-words are not swapped
+                                            // (B2, B3, B0, B1)
+#define CCM_CRCCTRL_ENDIAN_SHWNB                                              \
+                                0x00000020  // Half-words are swapped but bytes
+                                            // are not swapped in half-word.
+                                            // (B1, B0, B3, B2)
+#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030  // Bytes are swapped in half-words
+                                            // and half-words are swapped. (B0,
+                                            // B1, B2, B3)
+#define CCM_CRCCTRL_TYPE_M      0x0000000F  // Operation Type
+#define CCM_CRCCTRL_TYPE_P8055  0x00000000  // Polynomial 0x8005
+#define CCM_CRCCTRL_TYPE_P1021  0x00000001  // Polynomial 0x1021
+#define CCM_CRCCTRL_TYPE_P4C11DB7                                             \
+                                0x00000002  // Polynomial 0x4C11DB7
+#define CCM_CRCCTRL_TYPE_P1EDC6F41                                            \
+                                0x00000003  // Polynomial 0x1EDC6F41
+#define CCM_CRCCTRL_TYPE_TCPCHKSUM                                            \
+                                0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCSEED register.
+//
+//*****************************************************************************
+#define CCM_CRCSEED_SEED_M      0xFFFFFFFF  // SEED/Context Value
+#define CCM_CRCSEED_SEED_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCDIN register.
+//
+//*****************************************************************************
+#define CCM_CRCDIN_DATAIN_M     0xFFFFFFFF  // Data Input
+#define CCM_CRCDIN_DATAIN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
+// register.
+//
+//*****************************************************************************
+#define CCM_CRCRSLTPP_RSLTPP_M  0xFFFFFFFF  // Post Processing Result
+#define CCM_CRCRSLTPP_RSLTPP_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_ODIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_IDIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DIGEST_COUNT_M   0xFFFFFFFF  // Digest Count
+#define SHAMD5_DIGEST_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_MODE register.
+//
+//*****************************************************************************
+#define SHAMD5_MODE_HMAC_OUTER_HASH                                           \
+                                0x00000080  // HMAC Outer Hash Processing
+                                            // Enable
+#define SHAMD5_MODE_HMAC_KEY_PROC                                             \
+                                0x00000020  // HMAC Key Processing Enable
+#define SHAMD5_MODE_CLOSE_HASH  0x00000010  // Performs the padding, the
+                                            // Hash/HMAC will be 'closed' at
+                                            // the end of the block, as per
+                                            // MD5/SHA-1/SHA-2 specification
+#define SHAMD5_MODE_ALGO_CONSTANT                                             \
+                                0x00000008  // The initial digest register will
+                                            // be overwritten with the
+                                            // algorithm constants for the
+                                            // selected algorithm when hashing
+                                            // and the initial digest count
+                                            // register will be reset to 0
+#define SHAMD5_MODE_ALGO_M      0x00000007  // Hash Algorithm
+#define SHAMD5_MODE_ALGO_MD5    0x00000000  // MD5
+#define SHAMD5_MODE_ALGO_SHA1   0x00000002  // SHA-1
+#define SHAMD5_MODE_ALGO_SHA224 0x00000004  // SHA-224
+#define SHAMD5_MODE_ALGO_SHA256 0x00000006  // SHA-256
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_LENGTH
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_LENGTH_M         0xFFFFFFFF  // Block Length/Remaining Byte
+                                            // Count
+#define SHAMD5_LENGTH_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_0_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_1_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_2_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_3_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_4_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_5_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_6_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_7_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_8_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_9_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_10_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_10_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_11_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_11_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_12_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_12_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_13_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_13_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_14_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_14_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_15_IN_DATA_M                                              \
+                                0xFFFFFFFF  // Digest/Key Data
+#define SHAMD5_DATA_15_IN_DATA_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_REVISION
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_REVISION_M       0xFFFFFFFF  // Revision Number
+#define SHAMD5_REVISION_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSCONFIG_SADVANCED                                            \
+                                0x00000080  // Advanced Mode Enable
+#define SHAMD5_SYSCONFIG_SIDLE_M                                              \
+                                0x00000030  // Sidle mode
+#define SHAMD5_SYSCONFIG_SIDLE_FORCE                                          \
+                                0x00000000  // Force-idle mode
+#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008  // uDMA Request Enable
+#define SHAMD5_SYSCONFIG_IT_EN  0x00000004  // Interrupt Enable
+#define SHAMD5_SYSCONFIG_SOFTRESET                                            \
+                                0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSSTATUS_RESETDONE                                            \
+                                0x00000001  // Reset done status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQSTATUS_CONTEXT_READY                                        \
+                                0x00000008  // Context Ready Status
+#define SHAMD5_IRQSTATUS_INPUT_READY                                          \
+                                0x00000002  // Input Ready Status
+#define SHAMD5_IRQSTATUS_OUTPUT_READY                                         \
+                                0x00000001  // Output Ready Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQENABLE_CONTEXT_READY                                        \
+                                0x00000008  // Mask for context ready interrupt
+#define SHAMD5_IRQENABLE_INPUT_READY                                          \
+                                0x00000002  // Mask for input ready interrupt
+#define SHAMD5_IRQENABLE_OUTPUT_READY                                         \
+                                0x00000001  // Mask for output ready interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIM register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIM_COUT       0x00000004  // Context Out DMA Done Interrupt
+                                            // Mask
+#define SHAMD5_DMAIM_DIN        0x00000002  // Data In DMA Done Interrupt Mask
+#define SHAMD5_DMAIM_CIN        0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMARIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMARIS_COUT      0x00000004  // Context Out DMA Done Raw
+                                            // Interrupt Status
+#define SHAMD5_DMARIS_DIN       0x00000002  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define SHAMD5_DMARIS_CIN       0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAMIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAMIS_COUT      0x00000004  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAMIS_DIN       0x00000002  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAMIS_CIN       0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIC register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIC_COUT       0x00000004  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define SHAMD5_DMAIC_DIN        0x00000002  // Data In DMA Done Interrupt Clear
+#define SHAMD5_DMAIC_CIN        0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_6 register.
+//
+//*****************************************************************************
+#define AES_KEY2_6_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_6_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_7 register.
+//
+//*****************************************************************************
+#define AES_KEY2_7_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_7_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_4 register.
+//
+//*****************************************************************************
+#define AES_KEY2_4_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_4_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_5 register.
+//
+//*****************************************************************************
+#define AES_KEY2_5_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_5_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_2 register.
+//
+//*****************************************************************************
+#define AES_KEY2_2_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_2_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_3 register.
+//
+//*****************************************************************************
+#define AES_KEY2_3_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_3_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_0 register.
+//
+//*****************************************************************************
+#define AES_KEY2_0_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_0_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_1 register.
+//
+//*****************************************************************************
+#define AES_KEY2_1_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY2_1_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_6 register.
+//
+//*****************************************************************************
+#define AES_KEY1_6_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_6_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_7 register.
+//
+//*****************************************************************************
+#define AES_KEY1_7_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_7_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_4 register.
+//
+//*****************************************************************************
+#define AES_KEY1_4_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_4_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_5 register.
+//
+//*****************************************************************************
+#define AES_KEY1_5_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_5_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_2 register.
+//
+//*****************************************************************************
+#define AES_KEY1_2_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_2_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_3 register.
+//
+//*****************************************************************************
+#define AES_KEY1_3_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_3_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_0 register.
+//
+//*****************************************************************************
+#define AES_KEY1_0_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_0_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_1 register.
+//
+//*****************************************************************************
+#define AES_KEY1_1_KEY_M        0xFFFFFFFF  // Key Data
+#define AES_KEY1_1_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_0_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_1_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_2_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_3_DATA_M      0xFFFFFFFF  // Initialization Vector Input
+#define AES_IV_IN_3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_CTRL register.
+//
+//*****************************************************************************
+#define AES_CTRL_CTXTRDY        0x80000000  // Context Data Registers Ready
+#define AES_CTRL_SVCTXTRDY      0x40000000  // AES TAG/IV Block(s) Ready
+#define AES_CTRL_SAVE_CONTEXT   0x20000000  // TAG or Result IV Save
+#define AES_CTRL_CCM_M_M        0x01C00000  // Counter with CBC-MAC (CCM)
+#define AES_CTRL_CCM_L_M        0x00380000  // L Value
+#define AES_CTRL_CCM_L_2        0x00080000  // width = 2
+#define AES_CTRL_CCM_L_4        0x00180000  // width = 4
+#define AES_CTRL_CCM_L_8        0x00380000  // width = 8
+#define AES_CTRL_CCM            0x00040000  // AES-CCM Mode Enable
+#define AES_CTRL_GCM_M          0x00030000  // AES-GCM Mode Enable
+#define AES_CTRL_GCM_NOP        0x00000000  // No operation
+#define AES_CTRL_GCM_HLY0ZERO   0x00010000  // GHASH with H loaded and
+                                            // Y0-encrypted forced to zero
+#define AES_CTRL_GCM_HLY0CALC   0x00020000  // GHASH with H loaded and
+                                            // Y0-encrypted calculated
+                                            // internally
+#define AES_CTRL_GCM_HY0CALC    0x00030000  // Autonomous GHASH (both H and
+                                            // Y0-encrypted calculated
+                                            // internally)
+#define AES_CTRL_CBCMAC         0x00008000  // AES-CBC MAC Enable
+#define AES_CTRL_F9             0x00004000  // AES f9 Mode Enable
+#define AES_CTRL_F8             0x00002000  // AES f8 Mode Enable
+#define AES_CTRL_XTS_M          0x00001800  // AES-XTS Operation Enabled
+#define AES_CTRL_XTS_NOP        0x00000000  // No operation
+#define AES_CTRL_XTS_TWEAKJL    0x00000800  // Previous/intermediate tweak
+                                            // value and j loaded (value is
+                                            // loaded via IV, j is loaded via
+                                            // the AAD length register)
+#define AES_CTRL_XTS_K2IJL      0x00001000  // Key2, n and j are loaded (n is
+                                            // loaded via IV, j is loaded via
+                                            // the AAD length register)
+#define AES_CTRL_XTS_K2ILJ0     0x00001800  // Key2 and n are loaded; j=0 (n is
+                                            // loaded via IV)
+#define AES_CTRL_CFB            0x00000400  // Full block AES cipher feedback
+                                            // mode (CFB128) Enable
+#define AES_CTRL_ICM            0x00000200  // AES Integer Counter Mode (ICM)
+                                            // Enable
+#define AES_CTRL_CTR_WIDTH_M    0x00000180  // AES-CTR Mode Counter Width
+#define AES_CTRL_CTR_WIDTH_32   0x00000000  // Counter is 32 bits
+#define AES_CTRL_CTR_WIDTH_64   0x00000080  // Counter is 64 bits
+#define AES_CTRL_CTR_WIDTH_96   0x00000100  // Counter is 96 bits
+#define AES_CTRL_CTR_WIDTH_128  0x00000180  // Counter is 128 bits
+#define AES_CTRL_CTR            0x00000040  // Counter Mode
+#define AES_CTRL_MODE           0x00000020  // ECB/CBC Mode
+#define AES_CTRL_KEY_SIZE_M     0x00000018  // Key Size
+#define AES_CTRL_KEY_SIZE_128   0x00000008  // Key is 128 bits
+#define AES_CTRL_KEY_SIZE_192   0x00000010  // Key is 192 bits
+#define AES_CTRL_KEY_SIZE_256   0x00000018  // Key is 256 bits
+#define AES_CTRL_DIRECTION      0x00000004  // Encryption/Decryption Selection
+#define AES_CTRL_INPUT_READY    0x00000002  // Input Ready Status
+#define AES_CTRL_OUTPUT_READY   0x00000001  // Output Ready Status
+#define AES_CTRL_CCM_M_S        22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_0
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF  // Data Length
+#define AES_C_LENGTH_0_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_1
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF  // Data Length
+#define AES_C_LENGTH_1_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_AUTH_LENGTH
+// register.
+//
+//*****************************************************************************
+#define AES_AUTH_LENGTH_AUTH_M  0xFFFFFFFF  // Authentication Data Length
+#define AES_AUTH_LENGTH_AUTH_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_0
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_0_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_0_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_1
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_1_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_2
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_2_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_3
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_3_DATA_M    0xFFFFFFFF  // Secure Data RW
+                                            // Plaintext/Ciphertext
+#define AES_DATA_IN_3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_0
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_0_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_0_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_1
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_1_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_1_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_2
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_2_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_2_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_3
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_3_HASH_M    0xFFFFFFFF  // Hash Result
+#define AES_TAG_OUT_3_HASH_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_REVISION register.
+//
+//*****************************************************************************
+#define AES_REVISION_M          0xFFFFFFFF  // Revision number
+#define AES_REVISION_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define AES_SYSCONFIG_K3        0x00001000  // K3 Select
+#define AES_SYSCONFIG_KEYENC    0x00000800  // Key Encoding
+#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT                             \
+                                0x00000200  // Map Context Out on Data Out
+                                            // Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN                                  \
+                                0x00000100  // DMA Request Context Out Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN                                   \
+                                0x00000080  // DMA Request Context In Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN                                     \
+                                0x00000040  // DMA Request Data Out Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN                                      \
+                                0x00000020  // DMA Request Data In Enable
+#define AES_SYSCONFIG_SOFTRESET 0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_SYSSTATUS_RESETDONE 0x00000001  // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_IRQSTATUS_CONTEXT_OUT                                             \
+                                0x00000008  // Context Output Interrupt Status
+#define AES_IRQSTATUS_DATA_OUT  0x00000004  // Data Out Interrupt Status
+#define AES_IRQSTATUS_DATA_IN   0x00000002  // Data In Interrupt Status
+#define AES_IRQSTATUS_CONTEXT_IN                                              \
+                                0x00000001  // Context In Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define AES_IRQENABLE_CONTEXT_OUT                                             \
+                                0x00000008  // Context Out Interrupt Enable
+#define AES_IRQENABLE_DATA_OUT  0x00000004  // Data Out Interrupt Enable
+#define AES_IRQENABLE_DATA_IN   0x00000002  // Data In Interrupt Enable
+#define AES_IRQENABLE_CONTEXT_IN                                              \
+                                0x00000001  // Context In Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define AES_DIRTYBITS_S_DIRTY   0x00000002  // AES Dirty Bit
+#define AES_DIRTYBITS_S_ACCESS  0x00000001  // AES Access Bit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIM register.
+//
+//*****************************************************************************
+#define AES_DMAIM_DOUT          0x00000008  // Data Out DMA Done Interrupt Mask
+#define AES_DMAIM_DIN           0x00000004  // Data In DMA Done Interrupt Mask
+#define AES_DMAIM_COUT          0x00000002  // Context Out DMA Done Interrupt
+                                            // Mask
+#define AES_DMAIM_CIN           0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMARIS register.
+//
+//*****************************************************************************
+#define AES_DMARIS_DOUT         0x00000008  // Data Out DMA Done Raw Interrupt
+                                            // Status
+#define AES_DMARIS_DIN          0x00000004  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define AES_DMARIS_COUT         0x00000002  // Context Out DMA Done Raw
+                                            // Interrupt Status
+#define AES_DMARIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define AES_DMAMIS_DOUT         0x00000008  // Data Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_DIN          0x00000004  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_COUT         0x00000002  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAMIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIC register.
+//
+//*****************************************************************************
+#define AES_DMAIC_DOUT          0x00000008  // Data Out DMA Done Interrupt
+                                            // Clear
+#define AES_DMAIC_DIN           0x00000004  // Data In DMA Done Interrupt Clear
+#define AES_DMAIC_COUT          0x00000002  // Context Out DMA Done Masked
+                                            // Interrupt Status
+#define AES_DMAIC_CIN           0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_L register.
+//
+//*****************************************************************************
+#define DES_KEY3_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY3_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_H register.
+//
+//*****************************************************************************
+#define DES_KEY3_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY3_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_L register.
+//
+//*****************************************************************************
+#define DES_KEY2_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY2_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_H register.
+//
+//*****************************************************************************
+#define DES_KEY2_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY2_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_L register.
+//
+//*****************************************************************************
+#define DES_KEY1_L_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY1_L_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_H register.
+//
+//*****************************************************************************
+#define DES_KEY1_H_KEY_M        0xFFFFFFFF  // Key Data
+#define DES_KEY1_H_KEY_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_L register.
+//
+//*****************************************************************************
+#define DES_IV_L_M              0xFFFFFFFF  // Initialization vector for CBC,
+                                            // CFB modes (LSW)
+#define DES_IV_L_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_H register.
+//
+//*****************************************************************************
+#define DES_IV_H_M              0xFFFFFFFF  // Initialization vector for CBC,
+                                            // CFB modes (MSW)
+#define DES_IV_H_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_CTRL register.
+//
+//*****************************************************************************
+#define DES_CTRL_CONTEXT        0x80000000  // If 1, this read-only status bit
+                                            // indicates that the context data
+                                            // registers can be overwritten and
+                                            // the host is permitted to write
+                                            // the next context
+#define DES_CTRL_MODE_M         0x00000030  // Select CBC, ECB or CFB mode0x0:
+                                            // ECB mode0x1: CBC mode0x2: CFB
+                                            // mode0x3: reserved
+#define DES_CTRL_TDES           0x00000008  // Select DES or triple DES
+                                            // encryption/decryption
+#define DES_CTRL_DIRECTION      0x00000004  // Select encryption/decryption
+                                            // 0x0: decryption is selected0x1:
+                                            // Encryption is selected
+#define DES_CTRL_INPUT_READY    0x00000002  // When 1, ready to encrypt/decrypt
+                                            // data
+#define DES_CTRL_OUTPUT_READY   0x00000001  // When 1, Data decrypted/encrypted
+                                            // ready
+#define DES_CTRL_MODE_S         4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_LENGTH register.
+//
+//*****************************************************************************
+#define DES_LENGTH_M            0xFFFFFFFF  // Cryptographic data length in
+                                            // bytes for all modes
+#define DES_LENGTH_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_L register.
+//
+//*****************************************************************************
+#define DES_DATA_L_M            0xFFFFFFFF  // Data for encryption/decryption,
+                                            // LSW
+#define DES_DATA_L_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_H register.
+//
+//*****************************************************************************
+#define DES_DATA_H_M            0xFFFFFFFF  // Data for encryption/decryption,
+                                            // MSW
+#define DES_DATA_H_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_REVISION register.
+//
+//*****************************************************************************
+#define DES_REVISION_M          0xFFFFFFFF  // Revision number
+#define DES_REVISION_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN                                   \
+                                0x00000080  // DMA Request Context In Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN                                     \
+                                0x00000040  // DMA Request Data Out Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN                                      \
+                                0x00000020  // DMA Request Data In Enable
+#define DES_SYSCONFIG_SIDLE_M   0x0000000C  // Sidle mode
+#define DES_SYSCONFIG_SIDLE_FORCE                                             \
+                                0x00000000  // Force-idle mode
+#define DES_SYSCONFIG_SOFTRESET 0x00000002  // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_SYSSTATUS_RESETDONE 0x00000001  // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_IRQSTATUS_DATA_OUT  0x00000004  // This bit indicates data output
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+#define DES_IRQSTATUS_DATA_IN   0x00000002  // This bit indicates data input
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+#define DES_IRQSTATUS_CONTEX_IN 0x00000001  // This bit indicates context
+                                            // interrupt is active and triggers
+                                            // the interrupt output
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define DES_IRQENABLE_M_DATA_OUT                                              \
+                                0x00000004  // If this bit is set to 1 the data
+                                            // output interrupt is enabled
+#define DES_IRQENABLE_M_DATA_IN 0x00000002  // If this bit is set to 1 the data
+                                            // input interrupt is enabled
+#define DES_IRQENABLE_M_CONTEX_IN                                             \
+                                0x00000001  // If this bit is set to 1 the
+                                            // context interrupt is enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define DES_DIRTYBITS_S_DIRTY   0x00000002  // This bit is set to 1 by the
+                                            // module if any of the DES_*
+                                            // registers is written
+#define DES_DIRTYBITS_S_ACCESS  0x00000001  // This bit is set to 1 by the
+                                            // module if any of the DES_*
+                                            // registers is read
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIM register.
+//
+//*****************************************************************************
+#define DES_DMAIM_DOUT          0x00000004  // Data Out DMA Done Interrupt Mask
+#define DES_DMAIM_DIN           0x00000002  // Data In DMA Done Interrupt Mask
+#define DES_DMAIM_CIN           0x00000001  // Context In DMA Done Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMARIS register.
+//
+//*****************************************************************************
+#define DES_DMARIS_DOUT         0x00000004  // Data Out DMA Done Raw Interrupt
+                                            // Status
+#define DES_DMARIS_DIN          0x00000002  // Data In DMA Done Raw Interrupt
+                                            // Status
+#define DES_DMARIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define DES_DMAMIS_DOUT         0x00000004  // Data Out DMA Done Masked
+                                            // Interrupt Status
+#define DES_DMAMIS_DIN          0x00000002  // Data In DMA Done Masked
+                                            // Interrupt Status
+#define DES_DMAMIS_CIN          0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIC register.
+//
+//*****************************************************************************
+#define DES_DMAIC_DOUT          0x00000004  // Data Out DMA Done Interrupt
+                                            // Clear
+#define DES_DMAIC_DIN           0x00000002  // Data In DMA Done Interrupt Clear
+#define DES_DMAIC_CIN           0x00000001  // Context In DMA Done Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP      0x00000200  // Disable Out-Of-Order Floating
+                                            // Point
+#define NVIC_ACTLR_DISFPCA      0x00000100  // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M       0xE0000000  // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M       0x00E00000  // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M       0x0000E000  // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M       0x000000E0  // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S       29
+#define NVIC_PRI14_INTC_S       21
+#define NVIC_PRI14_INTB_S       13
+#define NVIC_PRI14_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M       0xE0000000  // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M       0x00E00000  // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M       0x0000E000  // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M       0x000000E0  // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S       29
+#define NVIC_PRI15_INTC_S       21
+#define NVIC_PRI15_INTB_S       13
+#define NVIC_PRI15_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M       0xE0000000  // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M       0x00E00000  // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M       0x0000E000  // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M       0x000000E0  // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S       29
+#define NVIC_PRI16_INTC_S       21
+#define NVIC_PRI16_INTB_S       13
+#define NVIC_PRI16_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M       0xE0000000  // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M       0x00E00000  // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M       0x0000E000  // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M       0x000000E0  // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S       29
+#define NVIC_PRI17_INTC_S       21
+#define NVIC_PRI17_INTB_S       13
+#define NVIC_PRI17_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M       0xE0000000  // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M       0x00E00000  // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M       0x0000E000  // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M       0x000000E0  // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S       29
+#define NVIC_PRI18_INTC_S       21
+#define NVIC_PRI18_INTB_S       13
+#define NVIC_PRI18_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M       0xE0000000  // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M       0x00E00000  // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M       0x0000E000  // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M       0x000000E0  // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S       29
+#define NVIC_PRI19_INTC_S       21
+#define NVIC_PRI19_INTB_S       13
+#define NVIC_PRI19_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M       0xE0000000  // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M       0x00E00000  // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M       0x0000E000  // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M       0x000000E0  // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S       29
+#define NVIC_PRI20_INTC_S       21
+#define NVIC_PRI20_INTB_S       13
+#define NVIC_PRI20_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M       0xE0000000  // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M       0x00E00000  // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M       0x0000E000  // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M       0x000000E0  // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S       29
+#define NVIC_PRI21_INTC_S       21
+#define NVIC_PRI21_INTB_S       13
+#define NVIC_PRI21_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M       0xE0000000  // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M       0x00E00000  // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M       0x0000E000  // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M       0x000000E0  // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S       29
+#define NVIC_PRI22_INTC_S       21
+#define NVIC_PRI22_INTB_S       13
+#define NVIC_PRI22_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M       0xE0000000  // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M       0x00E00000  // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M       0x0000E000  // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M       0x000000E0  // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S       29
+#define NVIC_PRI23_INTC_S       21
+#define NVIC_PRI23_INTB_S       13
+#define NVIC_PRI23_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M       0xE0000000  // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M       0x00E00000  // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M       0x0000E000  // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M       0x000000E0  // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S       29
+#define NVIC_PRI24_INTC_S       21
+#define NVIC_PRI24_INTB_S       13
+#define NVIC_PRI24_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M       0xE0000000  // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M       0x00E00000  // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M       0x0000E000  // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M       0x000000E0  // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S       29
+#define NVIC_PRI25_INTC_S       21
+#define NVIC_PRI25_INTB_S       13
+#define NVIC_PRI25_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M       0xE0000000  // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M       0x00E00000  // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M       0x0000E000  // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M       0x000000E0  // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S       29
+#define NVIC_PRI26_INTC_S       21
+#define NVIC_PRI26_INTB_S       13
+#define NVIC_PRI26_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M       0xE0000000  // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M       0x00E00000  // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M       0x0000E000  // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M       0x000000E0  // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S       29
+#define NVIC_PRI27_INTC_S       21
+#define NVIC_PRI27_INTB_S       13
+#define NVIC_PRI27_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M       0xE0000000  // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M       0x00E00000  // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M       0x0000E000  // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M       0x000000E0  // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S       29
+#define NVIC_PRI28_INTC_S       21
+#define NVIC_PRI28_INTB_S       13
+#define NVIC_PRI28_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM4   0x0000C240  // Cortex-M4 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI                                             \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD                                            \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM                                             \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS                                             \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG                                             \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC                                             \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV                                           \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK                                            \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_OFFSET_M    0xFFFFFC00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP                                              \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000  // Bus Fault on Floating-Point Lazy
+                                            // State Preservation
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020  // Memory Management Fault on
+                                            // Floating-Point Lazy State
+                                            // Preservation
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M        0x00C00000  // CP11 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP11_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP11_PRIV     0x00400000  // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL     0x00C00000  // Full Access
+#define NVIC_CPAC_CP10_M        0x00300000  // CP10 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP10_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP10_PRIV     0x00100000  // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL     0x00300000  // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST                                              \
+                                0x02000000  // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST                                             \
+                                0x01000000  // Core has executed insruction
+                                            // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL                                             \
+                                0x00000020  // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x000000FF  // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN         0x80000000  // Automatic State Preservation
+                                            // Enable
+#define NVIC_FPCC_LSPEN         0x40000000  // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY        0x00000100  // Monitor Ready
+#define NVIC_FPCC_BFRDY         0x00000040  // Bus Fault Ready
+#define NVIC_FPCC_MMRDY         0x00000020  // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY         0x00000010  // Hard Fault Ready
+#define NVIC_FPCC_THREAD        0x00000008  // Thread Mode
+#define NVIC_FPCC_USER          0x00000002  // User Privilege Level
+#define NVIC_FPCC_LSPACT        0x00000001  // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M     0xFFFFFFF8  // Address
+#define NVIC_FPCA_ADDRESS_S     3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP          0x04000000  // AHP Bit Default
+#define NVIC_FPDSC_DN           0x02000000  // DN Bit Default
+#define NVIC_FPDSC_FZ           0x01000000  // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M      0x00C00000  // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN     0x00000000  // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP     0x00400000  // Round towards Plus Infinity (RP)
+                                            // mode
+#define NVIC_FPDSC_RMODE_RM     0x00800000  // Round towards Minus Infinity
+                                            // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ     0x00C00000  // Round towards Zero (RZ) mode
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define SYSCTL_DID0_CLASS_SNOWFLAKE                                           \
+                                0x000A0000  // Tiva(TM) C Series TM4C129-class
+                                            // microcontrollers
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_PWRTC register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010  // VDDA Under BOR0 Status
+#define SYSCTL_PWRTC_VDD_UBOR0  0x00000001  // VDD Under BOR0 Status
+
+#endif
+
+#endif // __TM4C129XNCZAD_H__
diff --git a/bsp/tm4c129x/libraries/startup/startup_ewarm.c b/bsp/tm4c129x/libraries/startup/startup_ewarm.c
new file mode 100644
index 0000000000..eb852f59a2
--- /dev/null
+++ b/bsp/tm4c129x/libraries/startup/startup_ewarm.c
@@ -0,0 +1,299 @@
+//*****************************************************************************
+//
+// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench,
+//                   version 5.
+//
+// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+
+//*****************************************************************************
+//
+// Enable the IAR extensions for this source file.
+//
+//*****************************************************************************
+#pragma language=extended
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+void ResetISR(void);
+static void NmiSR(void);
+static void FaultISR(void);
+static void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// The entry point for the application startup code.
+//
+//*****************************************************************************
+extern void __iar_program_start(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+static uint32_t pui32Stack[64] @ ".noinit";
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table.  The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+    void (*pfnHandler)(void);
+    uint32_t ui32Ptr;
+}
+uVectorEntry;
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+__root const uVectorEntry __vector_table[] @ ".intvec" =
+{
+    { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) },
+                                            // The initial stack pointer
+    ResetISR,                               // The reset handler
+    NmiSR,                                  // The NMI handler
+    FaultISR,                               // The hard fault handler
+    IntDefaultHandler,                      // The MPU fault handler
+    IntDefaultHandler,                      // The bus fault handler
+    IntDefaultHandler,                      // The usage fault handler
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    IntDefaultHandler,                      // SVCall handler
+    IntDefaultHandler,                      // Debug monitor handler
+    0,                                      // Reserved
+    IntDefaultHandler,                      // The PendSV handler
+    IntDefaultHandler,                      // The SysTick handler
+    IntDefaultHandler,                      // GPIO Port A
+    IntDefaultHandler,                      // GPIO Port B
+    IntDefaultHandler,                      // GPIO Port C
+    IntDefaultHandler,                      // GPIO Port D
+    IntDefaultHandler,                      // GPIO Port E
+    IntDefaultHandler,                      // UART0 Rx and Tx
+    IntDefaultHandler,                      // UART1 Rx and Tx
+    IntDefaultHandler,                      // SSI0 Rx and Tx
+    IntDefaultHandler,                      // I2C0 Master and Slave
+    IntDefaultHandler,                      // PWM Fault
+    IntDefaultHandler,                      // PWM Generator 0
+    IntDefaultHandler,                      // PWM Generator 1
+    IntDefaultHandler,                      // PWM Generator 2
+    IntDefaultHandler,                      // Quadrature Encoder 0
+    IntDefaultHandler,                      // ADC Sequence 0
+    IntDefaultHandler,                      // ADC Sequence 1
+    IntDefaultHandler,                      // ADC Sequence 2
+    IntDefaultHandler,                      // ADC Sequence 3
+    IntDefaultHandler,                      // Watchdog timer
+    IntDefaultHandler,                      // Timer 0 subtimer A
+    IntDefaultHandler,                      // Timer 0 subtimer B
+    IntDefaultHandler,                      // Timer 1 subtimer A
+    IntDefaultHandler,                      // Timer 1 subtimer B
+    IntDefaultHandler,                      // Timer 2 subtimer A
+    IntDefaultHandler,                      // Timer 2 subtimer B
+    IntDefaultHandler,                      // Analog Comparator 0
+    IntDefaultHandler,                      // Analog Comparator 1
+    IntDefaultHandler,                      // Analog Comparator 2
+    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
+    IntDefaultHandler,                      // FLASH Control
+    IntDefaultHandler,                      // GPIO Port F
+    IntDefaultHandler,                      // GPIO Port G
+    IntDefaultHandler,                      // GPIO Port H
+    IntDefaultHandler,                      // UART2 Rx and Tx
+    IntDefaultHandler,                      // SSI1 Rx and Tx
+    IntDefaultHandler,                      // Timer 3 subtimer A
+    IntDefaultHandler,                      // Timer 3 subtimer B
+    IntDefaultHandler,                      // I2C1 Master and Slave
+    IntDefaultHandler,                      // CAN0
+    IntDefaultHandler,                      // CAN1
+    IntDefaultHandler,                      // Ethernet
+    IntDefaultHandler,                      // Hibernate
+    IntDefaultHandler,                      // USB0
+    IntDefaultHandler,                      // PWM Generator 3
+    IntDefaultHandler,                      // uDMA Software Transfer
+    IntDefaultHandler,                      // uDMA Error
+    IntDefaultHandler,                      // ADC1 Sequence 0
+    IntDefaultHandler,                      // ADC1 Sequence 1
+    IntDefaultHandler,                      // ADC1 Sequence 2
+    IntDefaultHandler,                      // ADC1 Sequence 3
+    IntDefaultHandler,                      // External Bus Interface 0
+    IntDefaultHandler,                      // GPIO Port J
+    IntDefaultHandler,                      // GPIO Port K
+    IntDefaultHandler,                      // GPIO Port L
+    IntDefaultHandler,                      // SSI2 Rx and Tx
+    IntDefaultHandler,                      // SSI3 Rx and Tx
+    IntDefaultHandler,                      // UART3 Rx and Tx
+    IntDefaultHandler,                      // UART4 Rx and Tx
+    IntDefaultHandler,                      // UART5 Rx and Tx
+    IntDefaultHandler,                      // UART6 Rx and Tx
+    IntDefaultHandler,                      // UART7 Rx and Tx
+    IntDefaultHandler,                      // I2C2 Master and Slave
+    IntDefaultHandler,                      // I2C3 Master and Slave
+    IntDefaultHandler,                      // Timer 4 subtimer A
+    IntDefaultHandler,                      // Timer 4 subtimer B
+    IntDefaultHandler,                      // Timer 5 subtimer A
+    IntDefaultHandler,                      // Timer 5 subtimer B
+    IntDefaultHandler,                      // FPU
+    0,                                      // Reserved
+    0,                                      // Reserved
+    IntDefaultHandler,                      // I2C4 Master and Slave
+    IntDefaultHandler,                      // I2C5 Master and Slave
+    IntDefaultHandler,                      // GPIO Port M
+    IntDefaultHandler,                      // GPIO Port N
+    0,                                      // Reserved
+    IntDefaultHandler,                      // Tamper
+    IntDefaultHandler,                      // GPIO Port P (Summary or P0)
+    IntDefaultHandler,                      // GPIO Port P1
+    IntDefaultHandler,                      // GPIO Port P2
+    IntDefaultHandler,                      // GPIO Port P3
+    IntDefaultHandler,                      // GPIO Port P4
+    IntDefaultHandler,                      // GPIO Port P5
+    IntDefaultHandler,                      // GPIO Port P6
+    IntDefaultHandler,                      // GPIO Port P7
+    IntDefaultHandler,                      // GPIO Port Q (Summary or Q0)
+    IntDefaultHandler,                      // GPIO Port Q1
+    IntDefaultHandler,                      // GPIO Port Q2
+    IntDefaultHandler,                      // GPIO Port Q3
+    IntDefaultHandler,                      // GPIO Port Q4
+    IntDefaultHandler,                      // GPIO Port Q5
+    IntDefaultHandler,                      // GPIO Port Q6
+    IntDefaultHandler,                      // GPIO Port Q7
+    IntDefaultHandler,                      // GPIO Port R
+    IntDefaultHandler,                      // GPIO Port S
+    IntDefaultHandler,                      // SHA/MD5 0
+    IntDefaultHandler,                      // AES 0
+    IntDefaultHandler,                      // DES3DES 0
+    IntDefaultHandler,                      // LCD Controller 0
+    IntDefaultHandler,                      // Timer 6 subtimer A
+    IntDefaultHandler,                      // Timer 6 subtimer B
+    IntDefaultHandler,                      // Timer 7 subtimer A
+    IntDefaultHandler,                      // Timer 7 subtimer B
+    IntDefaultHandler,                      // I2C6 Master and Slave
+    IntDefaultHandler,                      // I2C7 Master and Slave
+    IntDefaultHandler,                      // HIM Scan Matrix Keyboard 0
+    IntDefaultHandler,                      // One Wire 0
+    IntDefaultHandler,                      // HIM PS/2 0
+    IntDefaultHandler,                      // HIM LED Sequencer 0
+    IntDefaultHandler,                      // HIM Consumer IR 0
+    IntDefaultHandler,                      // I2C8 Master and Slave
+    IntDefaultHandler,                      // I2C9 Master and Slave
+    IntDefaultHandler                       // GPIO Port T
+};
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event.  Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called.  Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+void
+ResetISR(void)
+{
+    //
+    // Enable the floating-point unit.  This must be done here to handle the
+    // case where main() uses floating-point and the function prologue saves
+    // floating-point registers (which will fault if floating-point is not
+    // enabled).  Any configuration of the floating-point unit using DriverLib
+    // APIs must be done here prior to the floating-point unit being enabled.
+    //
+    // Note that this does not use DriverLib since it might not be included in
+    // this project.
+    //
+    HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
+                         ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
+                        NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
+
+    //
+    // Call the application's entry point.
+    //
+    __iar_program_start();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI.  This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+static void
+NmiSR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+FaultISR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
diff --git a/bsp/tm4c129x/libraries/startup/startup_gcc.c b/bsp/tm4c129x/libraries/startup/startup_gcc.c
new file mode 100644
index 0000000000..8bba1ae36d
--- /dev/null
+++ b/bsp/tm4c129x/libraries/startup/startup_gcc.c
@@ -0,0 +1,317 @@
+//*****************************************************************************
+//
+// startup_gcc.c - Startup code for use with GNU tools.
+//
+// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+void ResetISR(void);
+static void NmiSR(void);
+static void FaultISR(void);
+static void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern int main(void);
+
+extern void SysTick_Handler(void);
+extern void PendSV_Handler(void);
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+static uint32_t pui32Stack[64];
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) =
+{
+    (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)),
+                                            // The initial stack pointer
+    ResetISR,                               // The reset handler
+    NmiSR,                                  // The NMI handler
+    FaultISR,                               // The hard fault handler
+    IntDefaultHandler,                      // The MPU fault handler
+    IntDefaultHandler,                      // The bus fault handler
+    IntDefaultHandler,                      // The usage fault handler
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    IntDefaultHandler,                      // SVCall handler
+    IntDefaultHandler,                      // Debug monitor handler
+    0,                                      // Reserved
+    PendSV_Handler,                         // The PendSV handler
+    SysTick_Handler,                        // The SysTick handler
+    IntDefaultHandler,                      // GPIO Port A
+    IntDefaultHandler,                      // GPIO Port B
+    IntDefaultHandler,                      // GPIO Port C
+    IntDefaultHandler,                      // GPIO Port D
+    IntDefaultHandler,                      // GPIO Port E
+    IntDefaultHandler,                      // UART0 Rx and Tx
+    IntDefaultHandler,                      // UART1 Rx and Tx
+    IntDefaultHandler,                      // SSI0 Rx and Tx
+    IntDefaultHandler,                      // I2C0 Master and Slave
+    IntDefaultHandler,                      // PWM Fault
+    IntDefaultHandler,                      // PWM Generator 0
+    IntDefaultHandler,                      // PWM Generator 1
+    IntDefaultHandler,                      // PWM Generator 2
+    IntDefaultHandler,                      // Quadrature Encoder 0
+    IntDefaultHandler,                      // ADC Sequence 0
+    IntDefaultHandler,                      // ADC Sequence 1
+    IntDefaultHandler,                      // ADC Sequence 2
+    IntDefaultHandler,                      // ADC Sequence 3
+    IntDefaultHandler,                      // Watchdog timer
+    IntDefaultHandler,                      // Timer 0 subtimer A
+    IntDefaultHandler,                      // Timer 0 subtimer B
+    IntDefaultHandler,                      // Timer 1 subtimer A
+    IntDefaultHandler,                      // Timer 1 subtimer B
+    IntDefaultHandler,                      // Timer 2 subtimer A
+    IntDefaultHandler,                      // Timer 2 subtimer B
+    IntDefaultHandler,                      // Analog Comparator 0
+    IntDefaultHandler,                      // Analog Comparator 1
+    IntDefaultHandler,                      // Analog Comparator 2
+    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
+    IntDefaultHandler,                      // FLASH Control
+    IntDefaultHandler,                      // GPIO Port F
+    IntDefaultHandler,                      // GPIO Port G
+    IntDefaultHandler,                      // GPIO Port H
+    IntDefaultHandler,                      // UART2 Rx and Tx
+    IntDefaultHandler,                      // SSI1 Rx and Tx
+    IntDefaultHandler,                      // Timer 3 subtimer A
+    IntDefaultHandler,                      // Timer 3 subtimer B
+    IntDefaultHandler,                      // I2C1 Master and Slave
+    IntDefaultHandler,                      // CAN0
+    IntDefaultHandler,                      // CAN1
+    IntDefaultHandler,                      // Ethernet
+    IntDefaultHandler,                      // Hibernate
+    IntDefaultHandler,                      // USB0
+    IntDefaultHandler,                      // PWM Generator 3
+    IntDefaultHandler,                      // uDMA Software Transfer
+    IntDefaultHandler,                      // uDMA Error
+    IntDefaultHandler,                      // ADC1 Sequence 0
+    IntDefaultHandler,                      // ADC1 Sequence 1
+    IntDefaultHandler,                      // ADC1 Sequence 2
+    IntDefaultHandler,                      // ADC1 Sequence 3
+    IntDefaultHandler,                      // External Bus Interface 0
+    IntDefaultHandler,                      // GPIO Port J
+    IntDefaultHandler,                      // GPIO Port K
+    IntDefaultHandler,                      // GPIO Port L
+    IntDefaultHandler,                      // SSI2 Rx and Tx
+    IntDefaultHandler,                      // SSI3 Rx and Tx
+    IntDefaultHandler,                      // UART3 Rx and Tx
+    IntDefaultHandler,                      // UART4 Rx and Tx
+    IntDefaultHandler,                      // UART5 Rx and Tx
+    IntDefaultHandler,                      // UART6 Rx and Tx
+    IntDefaultHandler,                      // UART7 Rx and Tx
+    IntDefaultHandler,                      // I2C2 Master and Slave
+    IntDefaultHandler,                      // I2C3 Master and Slave
+    IntDefaultHandler,                      // Timer 4 subtimer A
+    IntDefaultHandler,                      // Timer 4 subtimer B
+    IntDefaultHandler,                      // Timer 5 subtimer A
+    IntDefaultHandler,                      // Timer 5 subtimer B
+    IntDefaultHandler,                      // FPU
+    0,                                      // Reserved
+    0,                                      // Reserved
+    IntDefaultHandler,                      // I2C4 Master and Slave
+    IntDefaultHandler,                      // I2C5 Master and Slave
+    IntDefaultHandler,                      // GPIO Port M
+    IntDefaultHandler,                      // GPIO Port N
+    0,                                      // Reserved
+    IntDefaultHandler,                      // Tamper
+    IntDefaultHandler,                      // GPIO Port P (Summary or P0)
+    IntDefaultHandler,                      // GPIO Port P1
+    IntDefaultHandler,                      // GPIO Port P2
+    IntDefaultHandler,                      // GPIO Port P3
+    IntDefaultHandler,                      // GPIO Port P4
+    IntDefaultHandler,                      // GPIO Port P5
+    IntDefaultHandler,                      // GPIO Port P6
+    IntDefaultHandler,                      // GPIO Port P7
+    IntDefaultHandler,                      // GPIO Port Q (Summary or Q0)
+    IntDefaultHandler,                      // GPIO Port Q1
+    IntDefaultHandler,                      // GPIO Port Q2
+    IntDefaultHandler,                      // GPIO Port Q3
+    IntDefaultHandler,                      // GPIO Port Q4
+    IntDefaultHandler,                      // GPIO Port Q5
+    IntDefaultHandler,                      // GPIO Port Q6
+    IntDefaultHandler,                      // GPIO Port Q7
+    IntDefaultHandler,                      // GPIO Port R
+    IntDefaultHandler,                      // GPIO Port S
+    IntDefaultHandler,                      // SHA/MD5 0
+    IntDefaultHandler,                      // AES 0
+    IntDefaultHandler,                      // DES3DES 0
+    IntDefaultHandler,                      // LCD Controller 0
+    IntDefaultHandler,                      // Timer 6 subtimer A
+    IntDefaultHandler,                      // Timer 6 subtimer B
+    IntDefaultHandler,                      // Timer 7 subtimer A
+    IntDefaultHandler,                      // Timer 7 subtimer B
+    IntDefaultHandler,                      // I2C6 Master and Slave
+    IntDefaultHandler,                      // I2C7 Master and Slave
+    IntDefaultHandler,                      // HIM Scan Matrix Keyboard 0
+    IntDefaultHandler,                      // One Wire 0
+    IntDefaultHandler,                      // HIM PS/2 0
+    IntDefaultHandler,                      // HIM LED Sequencer 0
+    IntDefaultHandler,                      // HIM Consumer IR 0
+    IntDefaultHandler,                      // I2C8 Master and Slave
+    IntDefaultHandler,                      // I2C9 Master and Slave
+    IntDefaultHandler                       // GPIO Port T
+};
+
+//*****************************************************************************
+//
+// The following are constructs created by the linker, indicating where the
+// the "data" and "bss" segments reside in memory.  The initializers for the
+// for the "data" segment resides immediately following the "text" segment.
+//
+//*****************************************************************************
+extern uint32_t _etext;
+extern uint32_t _data;
+extern uint32_t _edata;
+extern uint32_t _bss;
+extern uint32_t _ebss;
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event.  Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called.  Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+void
+ResetISR(void)
+{
+    uint32_t *pui32Src, *pui32Dest;
+
+    //
+    // Copy the data segment initializers from flash to SRAM.
+    //
+    pui32Src = &_etext;
+    for(pui32Dest = &_data; pui32Dest < &_edata; )
+    {
+        *pui32Dest++ = *pui32Src++;
+    }
+
+    //
+    // Zero fill the bss segment.
+    //
+    __asm("    ldr     r0, =_bss\n"
+          "    ldr     r1, =_ebss\n"
+          "    mov     r2, #0\n"
+          "    .thumb_func\n"
+          "zero_loop:\n"
+          "        cmp     r0, r1\n"
+          "        it      lt\n"
+          "        strlt   r2, [r0], #4\n"
+          "        blt     zero_loop");
+
+    //
+    // Enable the floating-point unit.  This must be done here to handle the
+    // case where main() uses floating-point and the function prologue saves
+    // floating-point registers (which will fault if floating-point is not
+    // enabled).  Any configuration of the floating-point unit using DriverLib
+    // APIs must be done here prior to the floating-point unit being enabled.
+    //
+    // Note that this does not use DriverLib since it might not be included in
+    // this project.
+    //
+    HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
+                         ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
+                        NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
+
+    //
+    // Call the application's entry point.
+    //
+    main();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI.  This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+static void
+NmiSR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+FaultISR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
diff --git a/bsp/tm4c129x/libraries/startup/startup_rvmdk.S b/bsp/tm4c129x/libraries/startup/startup_rvmdk.S
new file mode 100644
index 0000000000..5bc77ad795
--- /dev/null
+++ b/bsp/tm4c129x/libraries/startup/startup_rvmdk.S
@@ -0,0 +1,324 @@
+; <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;
+; startup_rvmdk.S - Startup code for use with Keil's uVision.
+;
+; Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+; Software License Agreement
+; 
+; Texas Instruments (TI) is supplying this software for use solely and
+; exclusively on TI's microcontroller products. The software is owned by
+; TI and/or its suppliers, and is protected under applicable copyright
+; laws. You may not combine this software with "viral" open-source
+; software in order to form a larger program.
+; 
+; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+; DAMAGES, FOR ANY REASON WHATSOEVER.
+; 
+; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
+;
+;******************************************************************************
+
+;******************************************************************************
+;
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+;******************************************************************************
+Stack   EQU     0x00000100
+
+;******************************************************************************
+;
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+;******************************************************************************
+Heap    EQU     0x00000000
+
+;******************************************************************************
+;
+; Allocate space for the stack.
+;
+;******************************************************************************
+        AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+        SPACE   Stack
+__initial_sp
+
+;******************************************************************************
+;
+; Allocate space for the heap.
+;
+;******************************************************************************
+        AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+        SPACE   Heap
+__heap_limit
+
+;******************************************************************************
+;
+; Indicate that the code in this file preserves 8-byte alignment of the stack.
+;
+;******************************************************************************
+        PRESERVE8
+
+;******************************************************************************
+;
+; Place code into the reset code section.
+;
+;******************************************************************************
+        AREA    RESET, CODE, READONLY
+        THUMB
+
+;******************************************************************************
+;
+; The vector table.
+;
+;******************************************************************************
+        EXPORT  __Vectors
+__Vectors
+        DCD     StackMem + Stack            ; Top of Stack
+        DCD     Reset_Handler               ; Reset Handler
+        DCD     NmiSR                       ; NMI Handler
+        DCD     FaultISR                    ; Hard Fault Handler
+        DCD     IntDefaultHandler           ; The MPU fault handler
+        DCD     IntDefaultHandler           ; The bus fault handler
+        DCD     IntDefaultHandler           ; The usage fault handler
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     IntDefaultHandler           ; SVCall handler
+        DCD     IntDefaultHandler           ; Debug monitor handler
+        DCD     0                           ; Reserved
+        DCD     IntDefaultHandler           ; The PendSV handler
+        DCD     IntDefaultHandler           ; The SysTick handler
+        DCD     IntDefaultHandler           ; GPIO Port A
+        DCD     IntDefaultHandler           ; GPIO Port B
+        DCD     IntDefaultHandler           ; GPIO Port C
+        DCD     IntDefaultHandler           ; GPIO Port D
+        DCD     IntDefaultHandler           ; GPIO Port E
+        DCD     IntDefaultHandler           ; UART0 Rx and Tx
+        DCD     IntDefaultHandler           ; UART1 Rx and Tx
+        DCD     IntDefaultHandler           ; SSI0 Rx and Tx
+        DCD     IntDefaultHandler           ; I2C0 Master and Slave
+        DCD     IntDefaultHandler           ; PWM Fault
+        DCD     IntDefaultHandler           ; PWM Generator 0
+        DCD     IntDefaultHandler           ; PWM Generator 1
+        DCD     IntDefaultHandler           ; PWM Generator 2
+        DCD     IntDefaultHandler           ; Quadrature Encoder 0
+        DCD     IntDefaultHandler           ; ADC Sequence 0
+        DCD     IntDefaultHandler           ; ADC Sequence 1
+        DCD     IntDefaultHandler           ; ADC Sequence 2
+        DCD     IntDefaultHandler           ; ADC Sequence 3
+        DCD     IntDefaultHandler           ; Watchdog timer
+        DCD     IntDefaultHandler           ; Timer 0 subtimer A
+        DCD     IntDefaultHandler           ; Timer 0 subtimer B
+        DCD     IntDefaultHandler           ; Timer 1 subtimer A
+        DCD     IntDefaultHandler           ; Timer 1 subtimer B
+        DCD     IntDefaultHandler           ; Timer 2 subtimer A
+        DCD     IntDefaultHandler           ; Timer 2 subtimer B
+        DCD     IntDefaultHandler           ; Analog Comparator 0
+        DCD     IntDefaultHandler           ; Analog Comparator 1
+        DCD     IntDefaultHandler           ; Analog Comparator 2
+        DCD     IntDefaultHandler           ; System Control (PLL, OSC, BO)
+        DCD     IntDefaultHandler           ; FLASH Control
+        DCD     IntDefaultHandler           ; GPIO Port F
+        DCD     IntDefaultHandler           ; GPIO Port G
+        DCD     IntDefaultHandler           ; GPIO Port H
+        DCD     IntDefaultHandler           ; UART2 Rx and Tx
+        DCD     IntDefaultHandler           ; SSI1 Rx and Tx
+        DCD     IntDefaultHandler           ; Timer 3 subtimer A
+        DCD     IntDefaultHandler           ; Timer 3 subtimer B
+        DCD     IntDefaultHandler           ; I2C1 Master and Slave
+        DCD     IntDefaultHandler           ; CAN0
+        DCD     IntDefaultHandler           ; CAN1
+        DCD     IntDefaultHandler           ; Ethernet
+        DCD     IntDefaultHandler           ; Hibernate
+        DCD     IntDefaultHandler           ; USB0
+        DCD     IntDefaultHandler           ; PWM Generator 3
+        DCD     IntDefaultHandler           ; uDMA Software Transfer
+        DCD     IntDefaultHandler           ; uDMA Error
+        DCD     IntDefaultHandler           ; ADC1 Sequence 0
+        DCD     IntDefaultHandler           ; ADC1 Sequence 1
+        DCD     IntDefaultHandler           ; ADC1 Sequence 2
+        DCD     IntDefaultHandler           ; ADC1 Sequence 3
+        DCD     IntDefaultHandler           ; External Bus Interface 0
+        DCD     IntDefaultHandler           ; GPIO Port J
+        DCD     IntDefaultHandler           ; GPIO Port K
+        DCD     IntDefaultHandler           ; GPIO Port L
+        DCD     IntDefaultHandler           ; SSI2 Rx and Tx
+        DCD     IntDefaultHandler           ; SSI3 Rx and Tx
+        DCD     IntDefaultHandler           ; UART3 Rx and Tx
+        DCD     IntDefaultHandler           ; UART4 Rx and Tx
+        DCD     IntDefaultHandler           ; UART5 Rx and Tx
+        DCD     IntDefaultHandler           ; UART6 Rx and Tx
+        DCD     IntDefaultHandler           ; UART7 Rx and Tx
+        DCD     IntDefaultHandler           ; I2C2 Master and Slave
+        DCD     IntDefaultHandler           ; I2C3 Master and Slave
+        DCD     IntDefaultHandler           ; Timer 4 subtimer A
+        DCD     IntDefaultHandler           ; Timer 4 subtimer B
+        DCD     IntDefaultHandler           ; Timer 5 subtimer A
+        DCD     IntDefaultHandler           ; Timer 5 subtimer B
+        DCD     IntDefaultHandler           ; FPU
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     IntDefaultHandler           ; I2C4 Master and Slave
+        DCD     IntDefaultHandler           ; I2C5 Master and Slave
+        DCD     IntDefaultHandler           ; GPIO Port M
+        DCD     IntDefaultHandler           ; GPIO Port N
+        DCD     0                           ; Reserved
+        DCD     IntDefaultHandler           ; Tamper
+        DCD     IntDefaultHandler           ; GPIO Port P (Summary or P0)
+        DCD     IntDefaultHandler           ; GPIO Port P1
+        DCD     IntDefaultHandler           ; GPIO Port P2
+        DCD     IntDefaultHandler           ; GPIO Port P3
+        DCD     IntDefaultHandler           ; GPIO Port P4
+        DCD     IntDefaultHandler           ; GPIO Port P5
+        DCD     IntDefaultHandler           ; GPIO Port P6
+        DCD     IntDefaultHandler           ; GPIO Port P7
+        DCD     IntDefaultHandler           ; GPIO Port Q (Summary or Q0)
+        DCD     IntDefaultHandler           ; GPIO Port Q1
+        DCD     IntDefaultHandler           ; GPIO Port Q2
+        DCD     IntDefaultHandler           ; GPIO Port Q3
+        DCD     IntDefaultHandler           ; GPIO Port Q4
+        DCD     IntDefaultHandler           ; GPIO Port Q5
+        DCD     IntDefaultHandler           ; GPIO Port Q6
+        DCD     IntDefaultHandler           ; GPIO Port Q7
+        DCD     IntDefaultHandler           ; GPIO Port R
+        DCD     IntDefaultHandler           ; GPIO Port S
+        DCD     IntDefaultHandler           ; SHA/MD5 0
+        DCD     IntDefaultHandler           ; AES 0
+        DCD     IntDefaultHandler           ; DES3DES 0
+        DCD     IntDefaultHandler           ; LCD Controller 0
+        DCD     IntDefaultHandler           ; Timer 6 subtimer A
+        DCD     IntDefaultHandler           ; Timer 6 subtimer B
+        DCD     IntDefaultHandler           ; Timer 7 subtimer A
+        DCD     IntDefaultHandler           ; Timer 7 subtimer B
+        DCD     IntDefaultHandler           ; I2C6 Master and Slave
+        DCD     IntDefaultHandler           ; I2C7 Master and Slave
+        DCD     IntDefaultHandler           ; HIM Scan Matrix Keyboard 0
+        DCD     IntDefaultHandler           ; One Wire 0
+        DCD     IntDefaultHandler           ; HIM PS/2 0
+        DCD     IntDefaultHandler           ; HIM LED Sequencer 0
+        DCD     IntDefaultHandler           ; HIM Consumer IR 0
+        DCD     IntDefaultHandler           ; I2C8 Master and Slave
+        DCD     IntDefaultHandler           ; I2C9 Master and Slave
+        DCD     IntDefaultHandler           ; GPIO Port T
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor first starts execution
+; following a reset event.
+;
+;******************************************************************************
+        EXPORT  Reset_Handler
+Reset_Handler
+        ;
+        ; Enable the floating-point unit.  This must be done here to handle the
+        ; case where main() uses floating-point and the function prologue saves
+        ; floating-point registers (which will fault if floating-point is not
+        ; enabled).  Any configuration of the floating-point unit using
+        ; DriverLib APIs must be done here prior to the floating-point unit
+        ; being enabled.
+        ;
+        ; Note that this does not use DriverLib since it might not be included
+        ; in this project.
+        ;
+        MOVW    R0, #0xED88
+        MOVT    R0, #0xE000
+        LDR     R1, [R0]
+        ORR     R1, #0x00F00000
+        STR     R1, [R0]
+
+        ;
+        ; Call the C library enty point that handles startup.  This will copy
+        ; the .data section initializers from flash to SRAM and zero fill the
+        ; .bss section.
+        ;
+        IMPORT  __main
+        B       __main
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor receives a NMI.  This
+; simply enters an infinite loop, preserving the system state for examination
+; by a debugger.
+;
+;******************************************************************************
+NmiSR
+        B       NmiSR
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor receives a fault
+; interrupt.  This simply enters an infinite loop, preserving the system state
+; for examination by a debugger.
+;
+;******************************************************************************
+FaultISR
+        B       FaultISR
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor receives an unexpected
+; interrupt.  This simply enters an infinite loop, preserving the system state
+; for examination by a debugger.
+;
+;******************************************************************************
+IntDefaultHandler
+        B       IntDefaultHandler
+
+;******************************************************************************
+;
+; Make sure the end of this section is aligned.
+;
+;******************************************************************************
+        ALIGN
+
+;******************************************************************************
+;
+; Some code in the normal code section for initializing the heap and stack.
+;
+;******************************************************************************
+        AREA    |.text|, CODE, READONLY
+
+;******************************************************************************
+;
+; The function expected of the C library startup code for defining the stack
+; and heap memory locations.  For the C library version of the startup code,
+; provide this function so that the C library initialization code can find out
+; the location of the stack and heap.
+;
+;******************************************************************************
+    IF :DEF: __MICROLIB
+        EXPORT  __initial_sp
+        EXPORT  __heap_base
+        EXPORT  __heap_limit
+    ELSE
+        IMPORT  __use_two_region_memory
+        EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+        LDR     R0, =HeapMem
+        LDR     R1, =(StackMem + Stack)
+        LDR     R2, =(HeapMem + Heap)
+        LDR     R3, =StackMem
+        BX      LR
+    ENDIF
+
+;******************************************************************************
+;
+; Make sure the end of this section is aligned.
+;
+;******************************************************************************
+        ALIGN
+
+;******************************************************************************
+;
+; Tell the assembler that we're done.
+;
+;******************************************************************************
+        END
diff --git a/bsp/tm4c129x/project.uvproj b/bsp/tm4c129x/project.uvproj
new file mode 100644
index 0000000000..ea427a1500
--- /dev/null
+++ b/bsp/tm4c129x/project.uvproj
@@ -0,0 +1,851 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target 1</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>TM4C1294NCZAD</Device>
+          <Vendor>Texas Instruments</Vendor>
+          <Cpu>IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCZAD$Flash\TM4C129_1024.FLM))</FlashDriverDll>
+          <DeviceId>7089</DeviceId>
+          <RegisterFile>$$Device:TM4C1294NCZAD$Device\Include\TM4C129\TM4C129.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc>-DTM4C1294NCZAD</SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:TM4C1294NCZAD$SVD\TM4C129\TM4C1294NCZAD.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\keil_bulid\</OutputDirectory>
+          <OutputName>project</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\keil_bulid\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>1</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>3</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\lmidk-agdi.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x40000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>PART_TM4C129XNCZAD</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\src;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include\drivers;..\..\components\finsh;..\tm4c129x;.\libraries\driverlib;.\libraries\inc;.\libraries\startup;.\libraries;.\drivers;.\applications;..\..\components\init</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>PART_TM4C129XNCZAD</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>1</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>project.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>applcaitions</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\applications\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\applications\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\applications\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\drivers\drv_uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>aes.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\aes.c</FilePath>
+            </File>
+            <File>
+              <FileName>can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\can.c</FilePath>
+            </File>
+            <File>
+              <FileName>comp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\comp.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\cpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>des.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\des.c</FilePath>
+            </File>
+            <File>
+              <FileName>eeprom.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\eeprom.c</FilePath>
+            </File>
+            <File>
+              <FileName>emac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\emac.c</FilePath>
+            </File>
+            <File>
+              <FileName>epi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\epi.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>fpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\fpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>hibernate.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\hibernate.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>lcd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\lcd.c</FilePath>
+            </File>
+            <File>
+              <FileName>mpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\mpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>pwm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\pwm.c</FilePath>
+            </File>
+            <File>
+              <FileName>qei.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\qei.c</FilePath>
+            </File>
+            <File>
+              <FileName>shamd5.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\shamd5.c</FilePath>
+            </File>
+            <File>
+              <FileName>ssi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\ssi.c</FilePath>
+            </File>
+            <File>
+              <FileName>sw_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\sw_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>sysctl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\sysctl.c</FilePath>
+            </File>
+            <File>
+              <FileName>sysexc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\sysexc.c</FilePath>
+            </File>
+            <File>
+              <FileName>systick.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\systick.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>udma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\udma.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\usb.c</FilePath>
+            </File>
+            <File>
+              <FileName>watchdog.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\watchdog.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_rvmdk.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\libraries\startup\startup_rvmdk.S</FilePath>
+            </File>
+            <File>
+              <FileName>tiva_timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\libraries\driverlib\tiva_timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>rt_core</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>memheap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\memheap.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>module.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\module.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>slab.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\slab.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>rt_hw</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>rt_components</GroupName>
+          <Files>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\init\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtconfig.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\rtconfig.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>cpusupport</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/tm4c129x/rtconfig.h b/bsp/tm4c129x/rtconfig.h
new file mode 100644
index 0000000000..50cde4df7f
--- /dev/null
+++ b/bsp/tm4c129x/rtconfig.h
@@ -0,0 +1,230 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX 8
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE   4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX  32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
+#define RT_TICK_PER_SECOND  100
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE  512
+// <bool name="RT_USING_MODULE" description="Using Application Module" default="true" />
+//#define RT_USING_MODULE
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
+#define RT_DEBUG_INIT   0
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+#define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO    4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE  512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND    100
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+#define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    256
+// <bool name="RT_USING_MTD_NAND" description="Using MTD NAND Framework" default="true" />
+//#define RT_USING_MTD_NAND
+// <bool name="RT_MTD_NAND_DEBUG" description="Enable MTD NAND Framework Debug" default="true" />
+//#define RT_MTD_NAND_DEBUG
+// <bool name="RT_USING_NFTL" description="Using NFTL layer" default="true" />
+//#define RT_USING_NFTL
+// <bool name="RT_USING_SPI" description="Using SPI Device Driver Framework" default="true" />
+//#define RT_USING_SPI
+// <bool name="RT_USING_I2C" description="Using I2C Device Driver Framework" default="true" />
+//#define RT_USING_I2C
+// <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" />
+//#define RT_USING_RTC
+// <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" />
+#define RT_MMCSD_THREAD_PREORITY    15
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE  128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE 4096
+// <bool name="FINSH_USING_MSH" description="Using module shell in finsh" default="true" />
+//#define FINSH_USING_MSH
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
+// #define RT_USING_NEWLIB
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+//#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+//#define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+//#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
+#define DFS_FILESYSTEM_TYPES_MAX  4
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX 4
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX           16
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" />
+#define RT_DFS_ELM_DRIVES    4
+// <bool name="RT_DFS_ELM_REENTRANT" description="Support reentrant" default="true" />
+#define RT_DFS_ELM_REENTRANT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN with static LFN working buffer">1</item>
+// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
+// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN  3
+// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
+#define RT_DFS_ELM_CODE_PAGE    936
+// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
+#define RT_DFS_ELM_CODE_PAGE_FILE
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN  256
+// <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" />
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  4096
+// <bool name="RT_DFS_ELM_USE_ERASE" description="Enable erase feature for flash" default="true" />
+#define RT_DFS_ELM_USE_ERASE
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_ROMFS" description="Using ROMFS" default="false" />
+//#define RT_USING_DFS_ROMFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS" default="false" />
+//#define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="The exported NFS host path" default="192.168.1.10:/" />
+#define RT_NFS_HOST_EXPORT  "192.168.1.20:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+//#define RT_USING_LWIP
+// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
+#define RT_USING_LWIP141
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
+#define RT_LWIP_PBUF_NUM    4
+// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
+#define RT_LWIP_TCP_PCB_NUM 3
+// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
+#define RT_LWIP_TCP_SND_BUF 4086
+// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
+#define RT_LWIP_TCP_WND 2048
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+// #define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
+#define RT_LWIP_TCP_SEG_NUM 8
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+
+
+// </RDTConfigurator>
+
+
+#endif
diff --git a/bsp/tm4c129x/rtconfig.py b/bsp/tm4c129x/rtconfig.py
new file mode 100644
index 0000000000..fb370aed47
--- /dev/null
+++ b/bsp/tm4c129x/rtconfig.py
@@ -0,0 +1,87 @@
+# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad	(REV D)
+
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+	
+#device options
+PART_TYPE = 'PART_TM4C129XNCZAD'
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= r'D:\ArdaArmTools\Sourcery_Lite\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= r'C:\Keil_v5'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)	
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # tool-chains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+	
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -std=gnu11 -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-tm4c129x.map,-cref,-u,Reset_Handler -T tm4c_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter tm4c_rom.sct --info sizes --info totals --info unused --info veneers --list rtthread-tm4c129x.map --strict'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB'
+	
+    EXEC_PATH += '/arm/armcc/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
diff --git a/bsp/tm4c129x/template.uvproj b/bsp/tm4c129x/template.uvproj
new file mode 100644
index 0000000000..22d359c599
--- /dev/null
+++ b/bsp/tm4c129x/template.uvproj
@@ -0,0 +1,388 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread_lm4f232</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LM4F232H5QD</Device>
+          <Vendor>Texas Instruments</Vendor>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0-0x3FFFF) CLOCK(16000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\Luminary\Startup.s" ("Luminary Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_256 -FS00 -FL040000)</FlashDriverDll>
+          <DeviceId>5931</DeviceId>
+          <RegisterFile>LM4Fxxxx.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\Luminary\LM4F232H5QD.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Luminary\</RegisterFilePath>
+          <DBRegisterFilePath>Luminary\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>project</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>4</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\lmidk-agdi.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4097</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\lmidk-agdi.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/tm4c129x/tm4c_rom.icf b/bsp/tm4c129x/tm4c_rom.icf
new file mode 100644
index 0000000000..38c73c9e28
--- /dev/null
+++ b/bsp/tm4c129x/tm4c_rom.icf
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// blinky.icf - Linker configuration file for blinky.
+//
+// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
+//
+//*****************************************************************************
+
+//
+// Define a memory region that covers the entire 4 GB addressible space of the
+// processor.
+//
+define memory mem with size = 4G;
+
+//
+// Define a region for the on-chip flash.
+//
+define region FLASH = mem:[from 0x00000000 to 0x000fffff];
+
+//
+// Define a region for the on-chip SRAM.
+//
+define region SRAM = mem:[from 0x20000000 to 0x2003ffff];
+
+//
+// Define a block for the heap.  The size should be set to something other
+// than zero if things in the C library that require the heap are used.
+//
+define block HEAP with alignment = 8, size = 0x00000000 { };
+
+//
+// Indicate that the read/write values should be initialized by copying from
+// flash.
+//
+initialize by copy { readwrite };
+
+//
+// Indicate that the noinit values should be left alone.  This includes the
+// stack, which if initialized will destroy the return address from the
+// initialization code, causing the processor to branch to zero and fault.
+//
+do not initialize { section .noinit };
+
+//
+// Place the interrupt vectors at the start of flash.
+//
+place at start of FLASH { readonly section .intvec };
+
+//
+// Place the remainder of the read-only items into flash.
+//
+place in FLASH { readonly };
+
+//
+// Place the RAM vector table at the start of SRAM.
+//
+place at start of SRAM { section VTABLE };
+
+//
+// Place all read/write items into SRAM.
+//
+place in SRAM { readwrite, block HEAP };
diff --git a/bsp/tm4c129x/tm4c_rom.ld b/bsp/tm4c129x/tm4c_rom.ld
new file mode 100644
index 0000000000..dfdde3ac9d
--- /dev/null
+++ b/bsp/tm4c129x/tm4c_rom.ld
@@ -0,0 +1,160 @@
+/******************************************************************************
+ *
+ * blinky.ld - Linker configuration file for blinky.
+ *
+ * Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+ * Software License Agreement
+ * 
+ * Texas Instruments (TI) is supplying this software for use solely and
+ * exclusively on TI's microcontroller products. The software is owned by
+ * TI and/or its suppliers, and is protected under applicable copyright
+ * laws. You may not combine this software with "viral" open-source
+ * software in order to form a larger program.
+ * 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+ * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+ * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+ * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, FOR ANY REASON WHATSOEVER.
+ * 
+ * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
+    DATA (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
+}
+ENTRY(ResetISR)
+_system_stack_size = 0x100;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _data = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _bss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/tm4c129x/tm4c_rom.sct b/bsp/tm4c129x/tm4c_rom.sct
new file mode 100644
index 0000000000..727cfddbfb
--- /dev/null
+++ b/bsp/tm4c129x/tm4c_rom.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00040000  {  ; RW data
+   *(vtable, +First)           ; for using IntRegister().
+   .ANY (+RW +ZI)
+  }
+}
+

From 26118499e0ba7630d67dcbbe6f945136be2d8797 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 19 Jul 2014 06:50:00 +0800
Subject: [PATCH 54/86] [BSP] remove rt_device_init_all() invoking.

---
 bsp/at91sam9260/applications/application.c |  2 --
 bsp/avr32uc3b0/startup.c                   |  1 -
 bsp/bf533/startup.c                        |  3 ---
 bsp/efm32/startup.c                        |  3 ---
 bsp/lm3s8962/applications/startup.c        |  2 --
 bsp/lm3s9b9x/applications/startup.c        |  2 --
 bsp/lm4f232/applications/startup.c         |  2 --
 bsp/lpc176x/applications/startup.c         | 21 +++------------------
 bsp/lpc178x/applications/application.c     |  6 +-----
 bsp/lpc2148/applications/startup.c         |  3 ---
 bsp/ls1bdev/applications/application.c     | 11 ++++-------
 bsp/ls1bdev/applications/startup.c         |  7 +------
 bsp/ls1bdev/ls1b_ram.lds                   |  2 +-
 bsp/m16c62p/applications/startup.c         |  5 -----
 bsp/mb9bf500r/application.c                |  5 +----
 bsp/mb9bf506r/applications/startup.c       |  8 ++------
 bsp/microblaze/startup.c                   |  2 --
 bsp/mini2440/application.c                 |  9 ---------
 bsp/mini2440/startup.c                     |  3 ---
 bsp/mini4020/applications/startup.c        |  7 +------
 bsp/sam7x/applications/startup.c           |  3 ---
 bsp/sep6200/application/startup.c          | 14 --------------
 bsp/simulator/applications/startup.c       |  4 ----
 bsp/stm32f0x/applications/startup.c        |  5 -----
 bsp/stm32f107/applications/startup.c       |  3 ---
 bsp/stm32f10x/applications/application.c   |  3 ---
 bsp/stm32f20x/applications/application.c   |  5 +----
 bsp/stm32f20x/applications/startup.c       |  3 ---
 bsp/stm32f40x/applications/application.c   |  2 --
 bsp/stm32f40x/applications/startup.c       |  3 ---
 bsp/upd70f3454/applications/startup.c      |  5 -----
 31 files changed, 15 insertions(+), 139 deletions(-)

diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c
index fa2f06377b..1fd9324cd2 100644
--- a/bsp/at91sam9260/applications/application.c
+++ b/bsp/at91sam9260/applications/application.c
@@ -138,8 +138,6 @@ void rt_init_thread_entry(void* parameter)
 		/* register ethernetif device */
 		eth_system_device_init();
 		rt_hw_macb_init();
-		/* re-init device driver */
-		rt_device_init_all();
 		/* init lwip system */
 		lwip_sys_init();
 	}
diff --git a/bsp/avr32uc3b0/startup.c b/bsp/avr32uc3b0/startup.c
index 79098bd311..481ff1448a 100644
--- a/bsp/avr32uc3b0/startup.c
+++ b/bsp/avr32uc3b0/startup.c
@@ -39,7 +39,6 @@ int main(void)
 #endif
 
 	rt_system_scheduler_init();
-	rt_device_init_all();
 	rt_application_init();
 
 #ifdef RT_USING_FINSH
diff --git a/bsp/bf533/startup.c b/bsp/bf533/startup.c
index a3cd60dd61..b1bf9884c2 100644
--- a/bsp/bf533/startup.c
+++ b/bsp/bf533/startup.c
@@ -62,9 +62,6 @@ void rtthread_startup(void)
         RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
         &uart0);
 
-    /* init all device */
-    rt_device_init_all();
-
     rt_console_set_device("uart0");
 #endif
 
diff --git a/bsp/efm32/startup.c b/bsp/efm32/startup.c
index 3e95603be3..f997c6aadd 100644
--- a/bsp/efm32/startup.c
+++ b/bsp/efm32/startup.c
@@ -114,9 +114,6 @@ void rtthread_startup(void)
     /* init scheduler system */
     rt_system_scheduler_init();
 
-    /* init all devices */
-    rt_device_init_all();
-
     /* init finsh */
 #ifdef RT_USING_FINSH
     finsh_system_init();
diff --git a/bsp/lm3s8962/applications/startup.c b/bsp/lm3s8962/applications/startup.c
index a38733494f..7f34aeef95 100644
--- a/bsp/lm3s8962/applications/startup.c
+++ b/bsp/lm3s8962/applications/startup.c
@@ -118,8 +118,6 @@ void rtthread_startup(void)
 	/* init sd card device */
 	rt_hw_sdcard_init();
 #endif
-	/* init all device */
-	rt_device_init_all();
 
 	/* init application */
 	rt_application_init();
diff --git a/bsp/lm3s9b9x/applications/startup.c b/bsp/lm3s9b9x/applications/startup.c
index 9f72d9c8df..c13e80da50 100644
--- a/bsp/lm3s9b9x/applications/startup.c
+++ b/bsp/lm3s9b9x/applications/startup.c
@@ -118,8 +118,6 @@ void rtthread_startup(void)
 	/* init sd card device */
 	rt_hw_sdcard_init();
 #endif
-	/* init all device */
-	rt_device_init_all();
 
 	/* init application */
 	rt_application_init();
diff --git a/bsp/lm4f232/applications/startup.c b/bsp/lm4f232/applications/startup.c
index 4572ab350d..b22095f06e 100644
--- a/bsp/lm4f232/applications/startup.c
+++ b/bsp/lm4f232/applications/startup.c
@@ -118,8 +118,6 @@ void rtthread_startup(void)
 	/* init sd card device */
 	rt_hw_sdcard_init();
 #endif
-	/* init all device */
-	rt_device_init_all();
 
 	/* init application */
 	rt_application_init();
diff --git a/bsp/lpc176x/applications/startup.c b/bsp/lpc176x/applications/startup.c
index f332155b17..9c08294569 100644
--- a/bsp/lpc176x/applications/startup.c
+++ b/bsp/lpc176x/applications/startup.c
@@ -16,20 +16,13 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#include "LPC17xx.h"
-#include "board.h"
-
-#ifdef RT_USING_DFS
-#include "sd.h"
-#endif
-
 /**
- * @addtogroup LPC17
+ * @addtogroup LPC176x
  */
 
 /*@{*/
-
-extern int  rt_application_init(void);
+#include <board.h>
+extern int rt_application_init(void);
 
 #ifdef __CC_ARM
 extern int Image$$RW_IRAM1$$ZI$$Limit;
@@ -84,14 +77,6 @@ void rtthread_startup(void)
 	/* initialize scheduler system */
 	rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-#ifdef RT_USING_DFS
-	rt_hw_sdcard_init();
-#endif
-	/* initialize all device */
-	rt_device_init_all();
-#endif
-
 	/* initialize application */
 	rt_application_init();
 
diff --git a/bsp/lpc178x/applications/application.c b/bsp/lpc178x/applications/application.c
index c5ab98da32..e2086fb400 100644
--- a/bsp/lpc178x/applications/application.c
+++ b/bsp/lpc178x/applications/application.c
@@ -65,8 +65,6 @@ void rt_init_thread_entry(void *parameter)
 
         /* register ethernetif device */
         lpc17xx_emac_hw_init();
-        /* init all device */
-        rt_device_init_all();
 
         /* init lwip system */
         lwip_sys_init();
@@ -78,13 +76,11 @@ void rt_init_thread_entry(void *parameter)
     {
     	extern void rtgui_system_server_init(void);
 		extern void application_init(void);
-		
+
 		rt_device_t lcd;
 
 		/* init lcd */
 		rt_hw_lcd_init();
-		/* re-init device driver */
-		rt_device_init_all();
 
 		/* find lcd device */
 		lcd = rt_device_find("lcd");
diff --git a/bsp/lpc2148/applications/startup.c b/bsp/lpc2148/applications/startup.c
index b0f72afd42..5efc41fd80 100644
--- a/bsp/lpc2148/applications/startup.c
+++ b/bsp/lpc2148/applications/startup.c
@@ -100,9 +100,6 @@ void rtthread_startup(void)
 
     /* init hardware serial device */
     rt_hw_serial_init();
-
-    /*init all registed devices*/
-    rt_device_init_all();
 #endif
 
     /* init application */
diff --git a/bsp/ls1bdev/applications/application.c b/bsp/ls1bdev/applications/application.c
index d010f0f220..db345a1bb6 100644
--- a/bsp/ls1bdev/applications/application.c
+++ b/bsp/ls1bdev/applications/application.c
@@ -33,14 +33,11 @@ void rt_init_thread_entry(void *parameter)
 
 		/* init Display Controller */
 		rt_hw_dc_init();
-			
-		/* re-init device driver */
-		rt_device_init_all();
-	
+
 		/* find Display Controller device */
 		dc = rt_device_find("dc");
-	
-		/* set Display Controller device as rtgui graphic driver */		
+
+		/* set Display Controller device as rtgui graphic driver */
 		rtgui_graphic_set_device(dc);
 	}
 #endif
@@ -59,7 +56,7 @@ int rt_application_init(void)
 	tid = rt_thread_create("init",
 							rt_init_thread_entry, RT_NULL,
 							4096, 8, 20);
-	if (tid != RT_NULL) 
+	if (tid != RT_NULL)
 		rt_thread_startup(tid);
 
 	return 0;
diff --git a/bsp/ls1bdev/applications/startup.c b/bsp/ls1bdev/applications/startup.c
index 36ec17e46c..befa929d30 100644
--- a/bsp/ls1bdev/applications/startup.c
+++ b/bsp/ls1bdev/applications/startup.c
@@ -64,11 +64,6 @@ void rtthread_startup(void)
 	/* init scheduler system */
 	rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
 	/* init application */
 	rt_application_init();
 
@@ -85,7 +80,7 @@ void rtthread_startup(void)
 	rt_system_scheduler_start();
 
 	/* never reach here */
-	return;
+	return ;
 }
 
 /*@}*/
diff --git a/bsp/ls1bdev/ls1b_ram.lds b/bsp/ls1bdev/ls1b_ram.lds
index 28a6cef006..95fb2496f8 100644
--- a/bsp/ls1bdev/ls1b_ram.lds
+++ b/bsp/ls1bdev/ls1b_ram.lds
@@ -50,7 +50,7 @@ SECTIONS
          . = ALIGN(4);
          __rt_init_start = .;
          KEEP(*(SORT(.rti_fn*)))
-             __rt_init_end = .;
+          __rt_init_end = .;
          . = ALIGN(4);
     }
 
diff --git a/bsp/m16c62p/applications/startup.c b/bsp/m16c62p/applications/startup.c
index 3857b6cdad..a73fcd90ea 100644
--- a/bsp/m16c62p/applications/startup.c
+++ b/bsp/m16c62p/applications/startup.c
@@ -68,11 +68,6 @@ void rtthread_startup(void)
 
 	/* init scheduler system */
 	rt_system_scheduler_init();
-    
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
 
 	/* init application */
 	rt_application_init();
diff --git a/bsp/mb9bf500r/application.c b/bsp/mb9bf500r/application.c
index fe17f240ca..ff22c008b1 100644
--- a/bsp/mb9bf500r/application.c
+++ b/bsp/mb9bf500r/application.c
@@ -44,10 +44,7 @@ void rt_init_thread_entry(void *parameter)
 	rt_hw_adc_init();
 	rt_hw_lcd_init();      
 	rt_hw_cpu_init();
-    
-	/* re-init device driver */
-	rt_device_init_all();
-	
+
 #ifdef RT_USING_RTGUI
 	extern void rtgui_system_server_init(void);
 
diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c
index ab838c4fe3..9076d572d6 100644
--- a/bsp/mb9bf506r/applications/startup.c
+++ b/bsp/mb9bf506r/applications/startup.c
@@ -59,13 +59,9 @@ void rtthread_startup(void)
 	rt_system_scheduler_init();
 
 #ifdef RT_USING_DEVICE
-#ifdef RT_USING_DFS
-#ifdef RT_USING_DFS_UFFS
+#if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS)
 	rt_hw_nand_init();
 #endif
-#endif
-	/* initialize all device */
-	rt_device_init_all();
 #endif
 
 	/* initialize application */
@@ -91,7 +87,7 @@ int main(void)
 {
 	/* disable interrupt first */
 	rt_hw_interrupt_disable();
-    
+
 	/* startup RT-Thread RTOS */
 	rtthread_startup();
 
diff --git a/bsp/microblaze/startup.c b/bsp/microblaze/startup.c
index c98098c03e..fdcf5a1713 100755
--- a/bsp/microblaze/startup.c
+++ b/bsp/microblaze/startup.c
@@ -86,8 +86,6 @@ void rtthread_startup(void)
 #ifdef RT_USING_DEVICE
 	/* init hardware serial device */
 	rt_hw_serial_init();
-	/* init all device */
-	rt_device_init_all();
 #endif
 
 	/* init application */
diff --git a/bsp/mini2440/application.c b/bsp/mini2440/application.c
index 4f911980a5..fe2626a827 100644
--- a/bsp/mini2440/application.c
+++ b/bsp/mini2440/application.c
@@ -151,9 +151,6 @@ void rt_init_thread_entry(void *parameter)
 
 		/* init keypad */
 		rt_hw_key_init();
-		
-		/* re-init device driver */
-		rt_device_init_all();
 
 		/* find lcd device */
 		lcd = rt_device_find("lcd");
@@ -175,9 +172,6 @@ void rt_init_thread_entry(void *parameter)
 		/* register ethernetif device */
 		rt_hw_dm9000_init();
 
-		/* re-init device driver */
-		rt_device_init_all();
-
 		/* init lwip system */
 		lwip_sys_init();
 		rt_kprintf("TCP/IP initialized!\n");
@@ -197,9 +191,6 @@ void rt_init_thread_entry(void *parameter)
 		/* init keypad */
 		rt_hw_key_init();
 
-		/* re-init device driver */
-		rt_device_init_all();
-
 		/* create ftk thread */
 		ftk_thread = rt_thread_create("ftk",
 									rt_ftk_thread_entry, RT_NULL,
diff --git a/bsp/mini2440/startup.c b/bsp/mini2440/startup.c
index cf8ff261c2..349d5f68f0 100644
--- a/bsp/mini2440/startup.c
+++ b/bsp/mini2440/startup.c
@@ -126,9 +126,6 @@ void rtthread_startup(void)
 
 	/* rtc init */
 	rt_hw_rtc_init();
-
-	/*init all registed devices */
-	rt_device_init_all();
 #endif
 
 	/* init application */
diff --git a/bsp/mini4020/applications/startup.c b/bsp/mini4020/applications/startup.c
index 852b9dc897..bb43044a39 100644
--- a/bsp/mini4020/applications/startup.c
+++ b/bsp/mini4020/applications/startup.c
@@ -79,9 +79,6 @@ void rtthread_startup()
 	eth_system_device_init();
 	rt_hw_dm9161_init();
 #endif
-	
-	/*init all registed devices */
-	rt_device_init_all();
 #endif
 
 	/* init application */
@@ -108,10 +105,8 @@ void rtthread_startup()
 
 int main()
 {
-	rt_uint32_t UNUSED level;
-
 	/* disable interrupt first */
-	level = rt_hw_interrupt_disable();
+	rt_hw_interrupt_disable();
 
 	/* startup RT-Thread RTOS */
 	rtthread_startup();
diff --git a/bsp/sam7x/applications/startup.c b/bsp/sam7x/applications/startup.c
index 770573910f..441f41385f 100644
--- a/bsp/sam7x/applications/startup.c
+++ b/bsp/sam7x/applications/startup.c
@@ -116,9 +116,6 @@ void rtthread_startup(void)
 #ifdef RT_USING_DFS
 	rt_hw_sdcard_init();
 #endif
-
-	/*init all registed devices*/
-	rt_device_init_all();
 #endif
 
 	/* init application */
diff --git a/bsp/sep6200/application/startup.c b/bsp/sep6200/application/startup.c
index 6c9d390fa2..1514b1114b 100644
--- a/bsp/sep6200/application/startup.c
+++ b/bsp/sep6200/application/startup.c
@@ -78,20 +78,6 @@ void rtthread_startup()
 	/* init scheduler system */
 	rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-
-#ifdef RT_USING_DFS
-  /* Not implemented */
-#endif
-
-#ifdef RT_USING_LWIP
-  /* Not implemented */
-#endif
-
-	/*init all registed devices */
-	rt_device_init_all();
-#endif
-
 	/* init application */
 	rt_application_init();
 
diff --git a/bsp/simulator/applications/startup.c b/bsp/simulator/applications/startup.c
index 2b21c69016..bd6502da6e 100644
--- a/bsp/simulator/applications/startup.c
+++ b/bsp/simulator/applications/startup.c
@@ -58,10 +58,6 @@ void rtthread_startup(void)
     /* init scheduler system */
     rt_system_scheduler_init();
 
-    /* init all device */
-#ifdef RT_USING_DEVICE
-    rt_device_init_all();
-#endif
     /* init application */
     rt_application_init();
 
diff --git a/bsp/stm32f0x/applications/startup.c b/bsp/stm32f0x/applications/startup.c
index 52d473b8bc..b3ace8038c 100644
--- a/bsp/stm32f0x/applications/startup.c
+++ b/bsp/stm32f0x/applications/startup.c
@@ -86,11 +86,6 @@ void rtthread_startup(void)
 	/* init scheduler system */
 	rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
 	/* init application */
 	rt_application_init();
 
diff --git a/bsp/stm32f107/applications/startup.c b/bsp/stm32f107/applications/startup.c
index eae71a17e6..9041d59002 100644
--- a/bsp/stm32f107/applications/startup.c
+++ b/bsp/stm32f107/applications/startup.c
@@ -81,9 +81,6 @@ void rtthread_startup(void)
     /* init scheduler system */
     rt_system_scheduler_init();
 
-    /* init all device */
-    rt_device_init_all();
-
     /* init application */
     rt_application_init();
 
diff --git a/bsp/stm32f10x/applications/application.c b/bsp/stm32f10x/applications/application.c
index d57bb4e4c0..58720cf0f1 100644
--- a/bsp/stm32f10x/applications/application.c
+++ b/bsp/stm32f10x/applications/application.c
@@ -122,9 +122,6 @@ void rt_init_thread_entry(void* parameter)
         /* init touch panel */
         rtgui_touch_hw_init();
 
-        /* re-init device driver */
-        rt_device_init_all();
-
         /* find lcd device */
         lcd = rt_device_find("lcd");
 
diff --git a/bsp/stm32f20x/applications/application.c b/bsp/stm32f20x/applications/application.c
index 23c2bb817f..b288a26bbb 100644
--- a/bsp/stm32f20x/applications/application.c
+++ b/bsp/stm32f20x/applications/application.c
@@ -66,12 +66,9 @@ void rt_init_thread_entry(void* parameter)
 
 		/* register ethernetif device */
 		eth_system_device_init();
-	
+
 		/* initialize eth interface */
 		rt_hw_stm32_eth_init();
-	
-		/* re-init device driver */
-		rt_device_init_all();
 
 		/* init lwip system */
 		lwip_sys_init();
diff --git a/bsp/stm32f20x/applications/startup.c b/bsp/stm32f20x/applications/startup.c
index dd9969168d..d07e4ad5a5 100644
--- a/bsp/stm32f20x/applications/startup.c
+++ b/bsp/stm32f20x/applications/startup.c
@@ -107,9 +107,6 @@ void rtthread_startup(void)
 
 	rt_hw_rtc_init();
 
-	/* init all device */
-	rt_device_init_all();
-
 	/* init application */
 	rt_application_init();
 
diff --git a/bsp/stm32f40x/applications/application.c b/bsp/stm32f40x/applications/application.c
index d4ad72f64d..2a01107f6b 100644
--- a/bsp/stm32f40x/applications/application.c
+++ b/bsp/stm32f40x/applications/application.c
@@ -34,8 +34,6 @@ void rt_init_thread_entry(void* parameter)
         eth_system_device_init();
 
         rt_hw_stm32_eth_init();
-        /* re-init device driver */
-        rt_device_init_all();
 
         /* init lwip system */
         lwip_sys_init();
diff --git a/bsp/stm32f40x/applications/startup.c b/bsp/stm32f40x/applications/startup.c
index d5d31fa5e1..e0547efb78 100644
--- a/bsp/stm32f40x/applications/startup.c
+++ b/bsp/stm32f40x/applications/startup.c
@@ -85,9 +85,6 @@ void rtthread_startup(void)
     /* init scheduler system */
     rt_system_scheduler_init();
 
-    /* init all device */
-    rt_device_init_all();
-
     /* init application */
     rt_application_init();
 
diff --git a/bsp/upd70f3454/applications/startup.c b/bsp/upd70f3454/applications/startup.c
index f609fc7cbb..1a06957b04 100644
--- a/bsp/upd70f3454/applications/startup.c
+++ b/bsp/upd70f3454/applications/startup.c
@@ -68,11 +68,6 @@ void rtthread_startup(void)
     /* init scheduler system */
     rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-    /* init all device */
-    rt_device_init_all();
-#endif
-
     /* init application */
     rt_application_init();
 

From 21b9e64cd6c37aef3475b3403b69c0b2cb61a9d5 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 19 Jul 2014 06:51:43 +0800
Subject: [PATCH 55/86] [BSP] remove COMPONENTS_INIT for lpc176x and stm32f107
 porting.

---
 bsp/lpc176x/applications/application.c   | 38 +++++++++---
 bsp/lpc176x/rtconfig.h                   |  2 +-
 bsp/stm32f107/applications/application.c | 78 ++++++++++++++----------
 bsp/stm32f107/rtconfig.h                 |  4 +-
 4 files changed, 80 insertions(+), 42 deletions(-)

diff --git a/bsp/lpc176x/applications/application.c b/bsp/lpc176x/applications/application.c
index 3ea7c29034..1fda158cb1 100644
--- a/bsp/lpc176x/applications/application.c
+++ b/bsp/lpc176x/applications/application.c
@@ -19,14 +19,20 @@
 #include <rtthread.h>
 #include "platform.h"
 
-#ifdef RT_USING_COMPONENTS_INIT
-#include <components.h>
-#endif
 #ifdef RT_USING_LWIP
 #include <emac.h>
+#include <netif/ethernetif.h>
+extern int lwip_system_init(void);
 #endif
+
 #ifdef RT_USING_DFS
 #include <dfs_fs.h>
+#include <sd.h>
+#endif
+
+#ifdef RT_USING_FINSH
+#include <shell.h>
+#include <finsh.h>
 #endif
 
 /* thread phase init */
@@ -38,21 +44,39 @@ void rt_init_thread_entry(void *parameter)
 #ifdef RT_USING_LWIP
     /* register Ethernet interface device */
     lpc17xx_emac_hw_init();
-#endif
 
-#ifdef RT_USING_COMPONENTS_INIT
-    /* initialization RT-Thread Components */
-    rt_components_init();
+    /* initialize lwip stack */
+	/* register ethernetif device */
+	eth_system_device_init();
+
+	/* initialize lwip system */
+	lwip_system_init();
+	rt_kprintf("TCP/IP initialized!\n");
 #endif
 
     /* Filesystem Initialization */
 #ifdef RT_USING_DFS
+    rt_hw_sdcard_init();
+
+	/* initialize the device file system */
+	dfs_init();
+
+#ifdef RT_USING_DFS_ELMFAT
+	/* initialize the elm chan FatFS file system*/
+	elm_init();
+#endif
+
     /* mount sd card fat partition 1 as root directory */
     if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
     	rt_kprintf("File System initialized!\n");
     else
     	rt_kprintf("File System init failed!\n");
 #endif
+
+#ifdef RT_USING_FINSH
+	/* initialize finsh */
+	finsh_system_init();
+#endif
 }
 
 int rt_application_init()
diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h
index 8aefe475d3..07553e2470 100644
--- a/bsp/lpc176x/rtconfig.h
+++ b/bsp/lpc176x/rtconfig.h
@@ -78,7 +78,7 @@
 // </section>
 
 // <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-#define RT_USING_COMPONENTS_INIT
+// #define RT_USING_COMPONENTS_INIT
 // <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
 #define RT_USING_FINSH
 // <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
diff --git a/bsp/stm32f107/applications/application.c b/bsp/stm32f107/applications/application.c
index 025451d32e..ef28641004 100644
--- a/bsp/stm32f107/applications/application.c
+++ b/bsp/stm32f107/applications/application.c
@@ -22,11 +22,20 @@
 
 #ifdef RT_USING_DFS
 #include <dfs_fs.h>
+#include <dfs_init.h>
+#include <dfs_elm.h>
 #endif
 
-#ifdef RT_USING_COMPONENTS_INIT
-#include <components.h>
-#endif /* RT_USING_COMPONENTS_INIT */
+#ifdef RT_USING_LWIP
+#include <stm32_eth.h>
+#include <netif/ethernetif.h>
+extern int lwip_system_init(void);
+#endif
+
+#ifdef RT_USING_FINSH
+#include <shell.h>
+#include <finsh.h>
+#endif
 
 void rt_init_thread_entry(void* parameter)
 {
@@ -35,45 +44,50 @@ void rt_init_thread_entry(void* parameter)
         rt_platform_init();
     }
 
-#ifdef RT_USING_COMPONENTS_INIT
-    /* initialization RT-Thread Components */
-    rt_components_init();
-#endif
-
     /* Filesystem Initialization */
 #if defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT)
+	/* initialize the device file system */
+	dfs_init();
+
+	/* initialize the elm chan FatFS file system*/
+	elm_init();
+    
+    /* mount sd card fat partition 1 as root directory */
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
     {
-        /* mount sd card fat partition 1 as root directory */
-        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-        {
-            rt_kprintf("File System initialized!\n");
-        }
-        else
-        {
-            rt_kprintf("File System initialzation failed!\n");
-        }
+        rt_kprintf("File System initialized!\n");
+    }
+    else
+    {
+        rt_kprintf("File System initialzation failed!\n");
     }
 #endif /* RT_USING_DFS && RT_USING_DFS_ELMFAT */
+
+#ifdef RT_USING_LWIP
+	/* initialize lwip stack */
+	/* register ethernetif device */
+	eth_system_device_init();
+
+	/* initialize lwip system */
+	lwip_system_init();
+	rt_kprintf("TCP/IP initialized!\n");
+#endif
+
+#ifdef RT_USING_FINSH
+	/* initialize finsh */
+	finsh_system_init();
+	finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
 }
 
 int rt_application_init(void)
 {
-    rt_thread_t init_thread;
+    rt_thread_t tid;
 
-#if (RT_THREAD_PRIORITY_MAX == 32)
-    init_thread = rt_thread_create("init",
-                                   rt_init_thread_entry, RT_NULL,
-                                   2048, 8, 20);
-#else
-    init_thread = rt_thread_create("init",
-                                   rt_init_thread_entry, RT_NULL,
-                                   2048, 80, 20);
-#endif
-
-    if (init_thread != RT_NULL)
-    {
-        rt_thread_startup(init_thread);
-    }
+    tid = rt_thread_create("init",
+        rt_init_thread_entry, RT_NULL,
+        2048, RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
 
     return 0;
 }
diff --git a/bsp/stm32f107/rtconfig.h b/bsp/stm32f107/rtconfig.h
index 7450367dbf..7f308c103f 100644
--- a/bsp/stm32f107/rtconfig.h
+++ b/bsp/stm32f107/rtconfig.h
@@ -69,8 +69,8 @@
 #define RT_CONSOLE_DEVICE_NAME	"uart1"
 // </section>
 
-// <section name="RT_USING_COMPONENTS_INIT" description="Using components init" default="true" >
-#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_COMPONENTS_INIT" description="Using components init" default="false" >
+// #define RT_USING_COMPONENTS_INIT
 // </section>
 
 /* SECTION: finsh, a C-Express shell */

From 3610e38050958153f94a27501866e49206130295 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 19 Jul 2014 06:52:00 +0800
Subject: [PATCH 56/86] [BSP] remove rt_device_init_all() invoking.

---
 bsp/wh44b0/startup.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/bsp/wh44b0/startup.c b/bsp/wh44b0/startup.c
index 1acafba54d..2f8b4b5bfa 100644
--- a/bsp/wh44b0/startup.c
+++ b/bsp/wh44b0/startup.c
@@ -84,10 +84,6 @@ void rtthread_startup(void)
 	rt_thread_idle_sethook(rt_hw_led_flash);
 #endif
 
-#ifdef RT_USING_DEVICE
-    rt_device_init_all();
-#endif
-
 	/* init application */
 	rt_application_init();
 

From 0eb35940a400ca2c36a585d30696eac47c6d687a Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sat, 19 Jul 2014 06:52:35 +0800
Subject: [PATCH 57/86] [POSIX] fix mq_open and sem_open argument issue.

---
 components/pthreads/mqueue.c    | 3 +++
 components/pthreads/semaphore.c | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/components/pthreads/mqueue.c b/components/pthreads/mqueue.c
index c1303ae6b1..7b669dc367 100644
--- a/components/pthreads/mqueue.c
+++ b/components/pthreads/mqueue.c
@@ -119,6 +119,7 @@ mqd_t mq_open(const char *name, int oflag, ...)
 {
     mqd_t mqdes;
     va_list arg;
+    mode_t mode;
     struct mq_attr *attr = RT_NULL;
 
     /* lock posix mqueue list */
@@ -128,6 +129,8 @@ mqd_t mq_open(const char *name, int oflag, ...)
     if (oflag & O_CREAT)
     {
         va_start(arg, oflag);
+        mode = (mode_t)va_arg(arg, unsigned int);
+        mode = mode;
         attr = (struct mq_attr *)va_arg(arg, struct mq_attr *);
         va_end(arg);
 
diff --git a/components/pthreads/semaphore.c b/components/pthreads/semaphore.c
index 726246c95f..ae69e0d1bc 100644
--- a/components/pthreads/semaphore.c
+++ b/components/pthreads/semaphore.c
@@ -224,6 +224,7 @@ sem_t *sem_open(const char *name, int oflag, ...)
 {
     sem_t* sem;
     va_list arg;
+    mode_t mode;
     unsigned int value;
 
     sem = RT_NULL;
@@ -233,6 +234,7 @@ sem_t *sem_open(const char *name, int oflag, ...)
     if (oflag & O_CREAT)
     {
         va_start(arg, oflag);
+        mode = (mode_t) va_arg( arg, unsigned int); mode = mode;
         value = va_arg( arg, unsigned int);
         va_end(arg);
 

From f74d7f16c0694b01c190b9b00a1f3e8dab9d662d Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Sun, 20 Jul 2014 00:16:37 +0800
Subject: [PATCH 58/86] [bsp] modify the uart_driver to fit the new rt-thread
 serial device driver framework. Modify the template.uvproj for auto generate
 MDK project.

---
 bsp/tm4c129x/applications/application.c |   3 +-
 bsp/tm4c129x/applications/board.c       |  34 +-
 bsp/tm4c129x/drivers/drv_uart.c         | 145 ++--
 bsp/tm4c129x/project.uvproj             | 851 ------------------------
 bsp/tm4c129x/template.uvproj            |  77 ++-
 5 files changed, 152 insertions(+), 958 deletions(-)
 delete mode 100644 bsp/tm4c129x/project.uvproj

diff --git a/bsp/tm4c129x/applications/application.c b/bsp/tm4c129x/applications/application.c
index 3c07bb6128..80f58b6ed8 100644
--- a/bsp/tm4c129x/applications/application.c
+++ b/bsp/tm4c129x/applications/application.c
@@ -20,8 +20,9 @@
 void rt_init_thread_entry(void *parameter)
 {
     /* Initialization RT-Thread Components */
-#ifdef RT_USING_COMPONENTS_INIT
     rt_components_init();
+#ifdef RT_USING_FINSH
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 }
 
diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c
index e26f3f5076..cb3cf92eb6 100644
--- a/bsp/tm4c129x/applications/board.c
+++ b/bsp/tm4c129x/applications/board.c
@@ -15,14 +15,14 @@
 
 #include <rthw.h>
 #include <rtthread.h>
-#include <components.h>
 
 #include "board.h"
 #include "drv_uart.h"
-#include "interrupt.h"
-#include "sysctl.h"
-#include "systick.h"
-#include "fpu.h"
+
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/systick.h"
+#include "driverlib/fpu.h"
 #include "driverlib/rom_map.h"
 
 #define SYS_CLOCK_DEFAULT 120000000
@@ -56,16 +56,15 @@ void SysTick_Handler(void)
 extern void PendSV_Handler(void);
 extern void HardFault_Handler(void);
 
-
 /**
  * This function will initial LPC40xx board.
  */
 void rt_hw_board_init()
 {
     IntRegister(FAULT_HARD, HardFault_Handler);	
-		IntRegister(FAULT_PENDSV, PendSV_Handler);
-		IntRegister(FAULT_SYSTICK, SysTick_Handler);
-	
+    IntRegister(FAULT_PENDSV, PendSV_Handler);
+    IntRegister(FAULT_SYSTICK, SysTick_Handler);
+    
 	  //
     // Enable lazy stacking for interrupt handlers.  This allows floating-point
     // instructions to be used within interrupt handlers, but at the expense of
@@ -78,23 +77,24 @@ void rt_hw_board_init()
     // TODO: The SYSCTL_XTAL_ value must be changed to match the value of the
     // crystal on your board.
     //
-    SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480),
-                                            SYS_CLOCK_DEFAULT);
+    SysClock = MAP_SysCtlClockFreqSet(
+                (SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480),
+                SYS_CLOCK_DEFAULT);
 
-	MAP_SysTickDisable();
+    MAP_SysTickDisable();
     MAP_SysTickPeriodSet(SysClock/ RT_TICK_PER_SECOND - 1);
     MAP_SysTickIntEnable();
     MAP_SysTickEnable();	
 
-
     /* set pend exception priority */
-    //IntPrioritySet(FAULT_PENDSV, (1 << __NVIC_PRIO_BITS) - 1);
-    /*init uart device*/
-		
+    IntPrioritySet(FAULT_PENDSV, (1 << 5) - 1);
+    
+    /*init uart device*/		
     rt_hw_uart_init();
+		//redirect RTT stdio to CONSOLE device
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
     //
     // Enable interrupts to the processor.
     //
-	MAP_IntMasterEnable();
+	  MAP_IntMasterEnable();
 }
diff --git a/bsp/tm4c129x/drivers/drv_uart.c b/bsp/tm4c129x/drivers/drv_uart.c
index eba5eff67a..7f87083999 100644
--- a/bsp/tm4c129x/drivers/drv_uart.c
+++ b/bsp/tm4c129x/drivers/drv_uart.c
@@ -20,41 +20,83 @@
 #include "board.h"
 //#include <components.h>
 
-#include "sysctl.h"
-#include "gpio.h"
-#include "uart.h"
-#include "hw_memmap.h"
-#include "pin_map.h"
-#include "interrupt.h"
-#include "rom.h"
-#include "rom_map.h"
+#include "inc/hw_memmap.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/gpio.h"
+#include "driverlib/uart.h"
+#include "driverlib/pin_map.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/rom_map.h"
 typedef struct hw_uart_device
 {
     uint32_t hw_base; // base address
 }hw_uart_t;
 
-#define GetHwUartPtr(serial) ((hw_uart_t*)(serial->parent.user_data))
+#define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data))
 
 static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {	
+	uint32_t config;
 	hw_uart_t* uart;
     RT_ASSERT(serial != RT_NULL);
-    uart = GetHwUartPtr(serial);
-	MAP_UARTDisable(uart->hw_base);
-    /* Initialize UART Configuration parameter structure to default state:
-     * Baudrate = 115200 bps
-     * 8 data bit
-     * 1 Stop bit
-     * None parity
-     */
-    // Initialize UART0 peripheral with given to corresponding parameter
-    MAP_UARTConfigSetExpClk(uart->hw_base, SysClock, cfg->baud_rate,
-													(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
-		MAP_UARTFIFOEnable(uart->hw_base);
+    uart = mUartGetHwPtr(serial);
+
+	MAP_UARTDisable(uart->hw_base);
+	// build UART Configuration parameter structure
+    switch(cfg->data_bits)
+	{
+	case DATA_BITS_9:
+		// enable 9bit address mode and set DATA_BIT_8
+		MAP_UART9BitEnable(uart->hw_base);
+	case DATA_BITS_8:
+		config |= UART_CONFIG_WLEN_8;
+		break;
+	case DATA_BITS_7:
+		config |= UART_CONFIG_WLEN_7;
+		break;
+	case DATA_BITS_6:
+		config |= UART_CONFIG_WLEN_6;
+		break;
+	case DATA_BITS_5:
+		config |= UART_CONFIG_WLEN_5;
+		break;
+	default:
+		RT_ASSERT(0);
+		break;
+	}
+	switch(cfg->parity)
+	{
+	case PARITY_ODD:
+		config |= UART_CONFIG_PAR_ODD;
+		break;
+	case PARITY_EVEN:
+		config |= UART_CONFIG_PAR_EVEN;
+		break;
+	case PARITY_NONE:
+		config |= UART_CONFIG_PAR_NONE;
+		break;
+	default:
+		RT_ASSERT(0);
+		break;
+	}
+	switch(cfg->stop_bits)
+	{
+	case STOP_BITS_1:
+		config |= UART_CONFIG_STOP_ONE;
+		break;
+	case STOP_BITS_2:
+		config |= UART_CONFIG_STOP_TWO;
+		break;
+	default:
+		RT_ASSERT(0);
+		break;
+	}
+	
+	// Initialize UART0 peripheral with given to corresponding parameter
+    MAP_UARTConfigSetExpClk(uart->hw_base, SysClock, cfg->baud_rate, config);
+	MAP_UARTFIFOEnable(uart->hw_base);
 
-  //
 	// Enable the UART.
-	//
 	MAP_UARTEnable(uart->hw_base);
     return RT_EOK;
 }
@@ -63,7 +105,7 @@ static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
 	hw_uart_t* uart;
     RT_ASSERT(serial != RT_NULL);
-    uart = GetHwUartPtr(serial);
+    uart = mUartGetHwPtr(serial);
 
     switch (cmd)
     {
@@ -84,7 +126,7 @@ static int hw_putc(struct rt_serial_device *serial, char c)
 {
 	hw_uart_t* uart;
     RT_ASSERT(serial != RT_NULL);
-    uart = GetHwUartPtr(serial);
+    uart = mUartGetHwPtr(serial);
 	
     MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c));
     return 1;
@@ -94,7 +136,7 @@ static int hw_getc(struct rt_serial_device *serial)
 {
 	hw_uart_t* uart;
     RT_ASSERT(serial != RT_NULL);
-    uart = GetHwUartPtr(serial);
+    uart = mUartGetHwPtr(serial);
 	
 	return MAP_UARTCharGetNonBlocking(uart->hw_base);
 }
@@ -110,7 +152,6 @@ static const struct rt_uart_ops hw_uart_ops =
 #if defined(RT_USING_UART0)
 /* UART0 device driver structure */
 struct rt_serial_device serial0;
-struct serial_ringbuffer uart0_int_rx_buf;
 hw_uart_t uart0 =
 {
     UART0_BASE,
@@ -118,21 +159,20 @@ hw_uart_t uart0 =
 
 void UART0_IRQHandler(void)
 {
-	  uint32_t intsrc;
+	uint32_t intsrc;
     hw_uart_t *uart = &uart0;
 
     /* enter interrupt */
     rt_interrupt_enter();
 
     /* Determine the interrupt source */
-    intsrc = UARTIntStatus(uart->hw_base, true);
+    intsrc = MAP_UARTIntStatus(uart->hw_base, true);
 
     // Receive Data Available or Character time-out
     if (intsrc & (UART_INT_RX | UART_INT_RT))
     {
-						UARTIntClear(UART0_BASE, intsrc);
-        rt_hw_serial_isr(&serial0);
-
+        MAP_UARTIntClear(uart->hw_base, intsrc);
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
     }
 		
     /* leave interrupt */
@@ -144,57 +184,38 @@ int rt_hw_uart_init(void)
 {
     hw_uart_t* uart;
     struct serial_configure config;
-	
-#ifdef RT_USING_UART0
-    uart = &uart0;
+
     config.baud_rate = BAUD_RATE_115200;
     config.bit_order = BIT_ORDER_LSB;
     config.data_bits = DATA_BITS_8;
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
+	
+#ifdef RT_USING_UART0
+    uart = &uart0;
     serial0.ops    = &hw_uart_ops;
-    serial0.int_rx = &uart0_int_rx_buf;
     serial0.config = config;
 
-    //
-    // Enable the peripherals used by this example.
-    // The UART itself needs to be enabled, as well as the GPIO port
-    // containing the pins that will be used.
-    //
-
     MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
-
-    //
-    // Configure the GPIO pin muxing for the UART function.
-    // This is only necessary if your part supports GPIO pin function muxing.
-    // Study the data sheet to see which functions are allocated per pin.
-    // TODO: change this to select the port/pin you are using
-    //
     MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
     MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
-
-    //
-    // Since GPIO A0 and A1 are used for the UART function, they must be
-    // configured for use as a peripheral function (instead of GPIO).
-    // TODO: change this to match the port/pin you are using
-    //
+	
     MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
-
     MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
 
     /* preemption = 1, sub-priority = 1 */
-    //IntPrioritySet(INT_UART0, ((0x01 << 3) | 0x01));
+    IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01));
 
     /* Enable Interrupt for UART channel */
-	UARTIntRegister(uart->hw_base, UART0_IRQHandler);
-	MAP_IntEnable(INT_UART0);
-	MAP_UARTEnable(uart->hw_base);
+	  UARTIntRegister(uart->hw_base, UART0_IRQHandler);
+	  MAP_IntEnable(INT_UART0);
+	  MAP_UARTEnable(uart->hw_base);
 
     /* register UART0 device */
     rt_hw_serial_register(&serial0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif
 	return 0;
diff --git a/bsp/tm4c129x/project.uvproj b/bsp/tm4c129x/project.uvproj
deleted file mode 100644
index ea427a1500..0000000000
--- a/bsp/tm4c129x/project.uvproj
+++ /dev/null
@@ -1,851 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>Target 1</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>TM4C1294NCZAD</Device>
-          <Vendor>Texas Instruments</Vendor>
-          <Cpu>IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCZAD$Flash\TM4C129_1024.FLM))</FlashDriverDll>
-          <DeviceId>7089</DeviceId>
-          <RegisterFile>$$Device:TM4C1294NCZAD$Device\Include\TM4C129\TM4C129.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc>-DTM4C1294NCZAD</SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:TM4C1294NCZAD$SVD\TM4C129\TM4C1294NCZAD.svd</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\keil_bulid\</OutputDirectory>
-          <OutputName>project</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\keil_bulid\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>1</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopB1X>0</nStopB1X>
-            <nStopB2X>0</nStopB2X>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-          <ComprImg>1</ComprImg>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>-MPU</SimDllArguments>
-          <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments>-MPU</TargetDllArguments>
-          <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-            <RestoreSysVw>1</RestoreSysVw>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <RestoreTracepoints>1</RestoreTracepoints>
-            <RestoreSysVw>1</RestoreSysVw>
-            <UsePdscDebugDescription>1</UsePdscDebugDescription>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>3</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>BIN\lmidk-agdi.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4096</DriverSelection>
-          </Flash1>
-          <bUseTDR>1</bUseTDR>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-          <pFcarmOut></pFcarmOut>
-          <pFcarmGrp></pFcarmGrp>
-          <pFcArmRoot></pFcArmRoot>
-          <FcArmLst>0</FcArmLst>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M4"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>2</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>0</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x40000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x40000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>2</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>0</uC99>
-            <useXO>0</useXO>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define>PART_TM4C129XNCZAD</Define>
-              <Undefine></Undefine>
-              <IncludePath>..\..\src;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include\drivers;..\..\components\finsh;..\tm4c129x;.\libraries\driverlib;.\libraries\inc;.\libraries\startup;.\libraries;.\drivers;.\applications;..\..\components\init</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define>PART_TM4C129XNCZAD</Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>0</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>1</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x00000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile>project.sct</ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>applcaitions</GroupName>
-          <Files>
-            <File>
-              <FileName>application.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\applications\application.c</FilePath>
-            </File>
-            <File>
-              <FileName>board.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\applications\board.c</FilePath>
-            </File>
-            <File>
-              <FileName>startup.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\applications\startup.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>drivers</GroupName>
-          <Files>
-            <File>
-              <FileName>drv_uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\drivers\drv_uart.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>libraries</GroupName>
-          <Files>
-            <File>
-              <FileName>adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\adc.c</FilePath>
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-            <File>
-              <FileName>aes.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\aes.c</FilePath>
-            </File>
-            <File>
-              <FileName>can.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\can.c</FilePath>
-            </File>
-            <File>
-              <FileName>comp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\comp.c</FilePath>
-            </File>
-            <File>
-              <FileName>cpu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\cpu.c</FilePath>
-            </File>
-            <File>
-              <FileName>crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>des.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\des.c</FilePath>
-            </File>
-            <File>
-              <FileName>eeprom.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\eeprom.c</FilePath>
-            </File>
-            <File>
-              <FileName>emac.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\emac.c</FilePath>
-            </File>
-            <File>
-              <FileName>epi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\epi.c</FilePath>
-            </File>
-            <File>
-              <FileName>flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\flash.c</FilePath>
-            </File>
-            <File>
-              <FileName>fpu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\fpu.c</FilePath>
-            </File>
-            <File>
-              <FileName>gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\gpio.c</FilePath>
-            </File>
-            <File>
-              <FileName>hibernate.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\hibernate.c</FilePath>
-            </File>
-            <File>
-              <FileName>i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>interrupt.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\interrupt.c</FilePath>
-            </File>
-            <File>
-              <FileName>lcd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\lcd.c</FilePath>
-            </File>
-            <File>
-              <FileName>mpu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\mpu.c</FilePath>
-            </File>
-            <File>
-              <FileName>pwm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\pwm.c</FilePath>
-            </File>
-            <File>
-              <FileName>qei.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\qei.c</FilePath>
-            </File>
-            <File>
-              <FileName>shamd5.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\shamd5.c</FilePath>
-            </File>
-            <File>
-              <FileName>ssi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\ssi.c</FilePath>
-            </File>
-            <File>
-              <FileName>sw_crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\sw_crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>sysctl.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\sysctl.c</FilePath>
-            </File>
-            <File>
-              <FileName>sysexc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\sysexc.c</FilePath>
-            </File>
-            <File>
-              <FileName>systick.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\systick.c</FilePath>
-            </File>
-            <File>
-              <FileName>uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\uart.c</FilePath>
-            </File>
-            <File>
-              <FileName>udma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\udma.c</FilePath>
-            </File>
-            <File>
-              <FileName>usb.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\usb.c</FilePath>
-            </File>
-            <File>
-              <FileName>watchdog.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\watchdog.c</FilePath>
-            </File>
-            <File>
-              <FileName>startup_rvmdk.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>.\libraries\startup\startup_rvmdk.S</FilePath>
-            </File>
-            <File>
-              <FileName>tiva_timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\libraries\driverlib\tiva_timer.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>rt_core</GroupName>
-          <Files>
-            <File>
-              <FileName>clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>device.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
-            </File>
-            <File>
-              <FileName>idle.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\idle.c</FilePath>
-            </File>
-            <File>
-              <FileName>ipc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\ipc.c</FilePath>
-            </File>
-            <File>
-              <FileName>irq.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\irq.c</FilePath>
-            </File>
-            <File>
-              <FileName>kservice.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\kservice.c</FilePath>
-            </File>
-            <File>
-              <FileName>mem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mem.c</FilePath>
-            </File>
-            <File>
-              <FileName>memheap.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\memheap.c</FilePath>
-            </File>
-            <File>
-              <FileName>mempool.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mempool.c</FilePath>
-            </File>
-            <File>
-              <FileName>module.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\module.c</FilePath>
-            </File>
-            <File>
-              <FileName>object.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
-            </File>
-            <File>
-              <FileName>scheduler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler.c</FilePath>
-            </File>
-            <File>
-              <FileName>slab.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\slab.c</FilePath>
-            </File>
-            <File>
-              <FileName>thread.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
-            </File>
-            <File>
-              <FileName>timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>finsh</GroupName>
-          <Files>
-            <File>
-              <FileName>cmd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\cmd.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_compiler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_error.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_heap.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_init.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_node.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_ops.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_parser.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_token.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_var.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_vm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
-            </File>
-            <File>
-              <FileName>msh.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\msh.c</FilePath>
-            </File>
-            <File>
-              <FileName>msh_cmd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\msh_cmd.c</FilePath>
-            </File>
-            <File>
-              <FileName>shell.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\shell.c</FilePath>
-            </File>
-            <File>
-              <FileName>symbol.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\symbol.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>rt_hw</GroupName>
-          <Files>
-            <File>
-              <FileName>serial.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
-            </File>
-            <File>
-              <FileName>completion.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
-            </File>
-            <File>
-              <FileName>dataqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
-            </File>
-            <File>
-              <FileName>pipe.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
-            </File>
-            <File>
-              <FileName>portal.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
-            </File>
-            <File>
-              <FileName>ringbuffer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
-            </File>
-            <File>
-              <FileName>workqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>rt_components</GroupName>
-          <Files>
-            <File>
-              <FileName>components.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\init\components.c</FilePath>
-            </File>
-            <File>
-              <FileName>rtconfig.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>.\rtconfig.h</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>cpusupport</GroupName>
-          <Files>
-            <File>
-              <FileName>cpuport.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
-            </File>
-            <File>
-              <FileName>context_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
-            </File>
-            <File>
-              <FileName>backtrace.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
-            </File>
-            <File>
-              <FileName>div0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
-            </File>
-            <File>
-              <FileName>showmem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-</Project>
diff --git a/bsp/tm4c129x/template.uvproj b/bsp/tm4c129x/template.uvproj
index 22d359c599..1a84ba0131 100644
--- a/bsp/tm4c129x/template.uvproj
+++ b/bsp/tm4c129x/template.uvproj
@@ -7,35 +7,38 @@
 
   <Targets>
     <Target>
-      <TargetName>rt-thread_lm4f232</TargetName>
+      <TargetName>RT-Thread TM4C129X</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>LM4F232H5QD</Device>
+          <Device>TM4C129XNCZAD</Device>
           <Vendor>Texas Instruments</Vendor>
-          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0-0x3FFFF) CLOCK(16000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <PackID>Keil.TM4C_DFP.1.0.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"STARTUP\Luminary\Startup.s" ("Luminary Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_256 -FS00 -FL040000)</FlashDriverDll>
-          <DeviceId>5931</DeviceId>
-          <RegisterFile>LM4Fxxxx.H</RegisterFile>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C129XNCZAD$Flash\TM4C129_1024.FLM))</FlashDriverDll>
+          <DeviceId>7096</DeviceId>
+          <RegisterFile>$$Device:TM4C129XNCZAD$Device\Include\TM4C129\TM4C129.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
           <Linker></Linker>
           <OHString></OHString>
           <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
+          <SLE66CMisc>-DTM4C129XNCZAD</SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>SFD\Luminary\LM4F232H5QD.SFR</SFDFile>
+          <SFDFile>$$Device:TM4C129XNCZAD$SVD\TM4C129\TM4C129XNCZAD.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
           <IncludePath></IncludePath>
           <LibPath></LibPath>
-          <RegisterFilePath>Luminary\</RegisterFilePath>
-          <DBRegisterFilePath>Luminary\</DBRegisterFilePath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -44,13 +47,13 @@
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
           <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>project</OutputName>
+          <OutputName>rtthread-tm4c</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -61,6 +64,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -69,6 +74,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
           </BeforeMake>
           <AfterMake>
             <RunUserProg1>0</RunUserProg1>
@@ -95,6 +102,7 @@
           <StopOnExitCode>3</StopOnExitCode>
           <CustomArgument></CustomArgument>
           <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
@@ -124,6 +132,7 @@
             <RestoreFunctions>1</RestoreFunctions>
             <RestoreToolbox>1</RestoreToolbox>
             <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
           </Simulator>
           <Target>
             <UseTarget>1</UseTarget>
@@ -134,9 +143,12 @@
             <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
             <RestoreFunctions>0</RestoreFunctions>
             <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
           </Target>
           <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>4</TargetSelection>
+          <TargetSelection>3</TargetSelection>
           <SimDlls>
             <CpuDll></CpuDll>
             <CpuDllArguments></CpuDllArguments>
@@ -158,13 +170,18 @@
             <UseTargetDll>1</UseTargetDll>
             <UseExternalTool>0</UseExternalTool>
             <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
             <Capability>1</Capability>
-            <DriverSelection>4097</DriverSelection>
+            <DriverSelection>4096</DriverSelection>
           </Flash1>
-          <Flash2>BIN\lmidk-agdi.dll</Flash2>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
           <Flash3>"" ()</Flash3>
           <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
           <ArmAdsMisc>
@@ -208,7 +225,7 @@
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
+            <useUlib>0</useUlib>
             <EndSel>0</EndSel>
             <uLtcg>0</uLtcg>
             <RoSelD>3</RoSelD>
@@ -264,12 +281,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x8000</Size>
+                <Size>0x40000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x0</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x100000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -294,7 +311,7 @@
               <OCR_RVCT4>
                 <Type>1</Type>
                 <StartAddress>0x0</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x100000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -319,7 +336,7 @@
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                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x8000</Size>
+                <Size>0x40000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -334,14 +351,17 @@
             <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
+            <OneElfS>0</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
             <Ropi>0</Ropi>
             <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
+            <wLevel>2</wLevel>
             <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
             <VariousControls>
               <MiscControls></MiscControls>
               <Define></Define>
@@ -357,6 +377,8 @@
             <SplitLS>0</SplitLS>
             <SwStkChk>0</SwStkChk>
             <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
             <VariousControls>
               <MiscControls></MiscControls>
               <Define></Define>
@@ -372,8 +394,9 @@
             <RepFail>1</RepFail>
             <useFile>0</useFile>
             <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>tm4c_rom.sct</ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc></Misc>

From 99e18f008c716d43c31591983414c728a1f313e4 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sun, 20 Jul 2014 13:57:01 +0800
Subject: [PATCH 59/86] [Docs] Add RT-Thread logo.

---
 documentation/doxygen/rtthread_logo.png | Bin 0 -> 25064 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 documentation/doxygen/rtthread_logo.png

diff --git a/documentation/doxygen/rtthread_logo.png b/documentation/doxygen/rtthread_logo.png
new file mode 100644
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Ef@zAAMgRZ+

literal 0
HcmV?d00001


From 02faf9edb8162a4e8f60cb818ece20c7357a3abf Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sun, 20 Jul 2014 13:57:49 +0800
Subject: [PATCH 60/86] [Finsh] fix device_open issue when set_device in finsh.

---
 components/finsh/finsh.h | 1 -
 components/finsh/shell.c | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h
index cf7ee05808..0b270ddeaf 100644
--- a/components/finsh/finsh.h
+++ b/components/finsh/finsh.h
@@ -411,7 +411,6 @@ struct finsh_parser
  *
  * The basic data type in finsh shell
  */
-
 enum finsh_type {
 	finsh_type_unknown = 0, /**< unknown data type */
 	finsh_type_void,		/**< void  			*/
diff --git a/components/finsh/shell.c b/components/finsh/shell.c
index 5489cedf3d..a9559954e6 100644
--- a/components/finsh/shell.c
+++ b/components/finsh/shell.c
@@ -112,7 +112,7 @@ void finsh_set_device(const char* device_name)
     /* check whether it's a same device */
     if (dev == shell->device) return;
     /* open this device and set the new device in finsh shell */
-    if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
+    if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX) == RT_EOK)
     {
         if (shell->device != RT_NULL)
         {

From 9572d3e46ab081bf1a3440c9cc06d48a76daeb51 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 06:23:50 +0800
Subject: [PATCH 61/86] [bsp] Fix STM32F10x compiling warning.

---
 bsp/stm32f10x/drivers/board.c | 1 +
 bsp/stm32f10x/drivers/board.h | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bsp/stm32f10x/drivers/board.c b/bsp/stm32f10x/drivers/board.c
index a78428e711..d8374068c8 100644
--- a/bsp/stm32f10x/drivers/board.c
+++ b/bsp/stm32f10x/drivers/board.c
@@ -19,6 +19,7 @@
 #include "stm32f10x.h"
 #include "stm32f10x_fsmc.h"
 #include "board.h"
+#include "usart.h"
 
 #ifdef  RT_USING_COMPONENTS_INIT
 #include <components.h>
diff --git a/bsp/stm32f10x/drivers/board.h b/bsp/stm32f10x/drivers/board.h
index dc84db9c69..0fa68651b8 100644
--- a/bsp/stm32f10x/drivers/board.h
+++ b/bsp/stm32f10x/drivers/board.h
@@ -37,11 +37,13 @@
 #define STM32_SRAM_SIZE         64
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 
+// <<< Use Configuration Wizard in Context Menu >>>
+
 /* USART driver select. */
 #define RT_USING_UART1
 #define RT_USING_UART2
 #define RT_USING_UART3
 
-#endif /* __BOARD_H__ */
+void rt_hw_board_init(void);
 
-// <<< Use Configuration Wizard in Context Menu >>>
+#endif /* __BOARD_H__ */

From 4e2a6cc36179c1b5ffae707f9485e56c964b8988 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 06:28:43 +0800
Subject: [PATCH 62/86] [Kernel] The rt_object_find routine can support to find
 an object inside a module. The usage is:
 rt_object_find("module_name/object_name").

---
 src/object.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 60 insertions(+), 5 deletions(-)

diff --git a/src/object.c b/src/object.c
index ed3173a0f5..32dc0f2384 100644
--- a/src/object.c
+++ b/src/object.c
@@ -403,22 +403,77 @@ rt_object_t rt_object_find(const char *name, rt_uint8_t type)
 {
     struct rt_object *object;
     struct rt_list_node *node;
-    struct rt_object_information *information;
-    extern volatile rt_uint8_t rt_interrupt_nest;
+    struct rt_object_information *information = RT_NULL;
 
     /* parameter check */
     if ((name == RT_NULL) || (type > RT_Object_Class_Unknown))
         return RT_NULL;
 
     /* which is invoke in interrupt status */
-    if (rt_interrupt_nest != 0)
-        RT_ASSERT(0);
+    RT_DEBUG_NOT_IN_INTERRUPT;
+
+#ifdef RT_USING_MODULE
+    /* check whether to find a object inside a module. */
+    {
+        const char *name_ptr;
+        int module_name_length;
+        
+        name_ptr = name;
+        while ((*name_ptr != '\0') && (*name_ptr != '/'))
+            name_ptr ++;
+
+        if (*name_ptr == '/')
+        {
+            struct rt_module* module = RT_NULL;
+
+            /* get the name length of module */
+            module_name_length = name_ptr - name;
+
+            /* enter critical */
+            rt_enter_critical();
+
+            /* find module */
+            information = &rt_object_container[RT_Object_Class_Module];
+            for (node = information->object_list.next; 
+                node != &(information->object_list);
+                node  = node->next)
+            {
+                object = rt_list_entry(node, struct rt_object, list);
+                if ((rt_strncmp(object->name, name, module_name_length) == 0) &&
+                    module_name_length == RT_NAME_MAX || object->name[module_name_length] == '\0')
+                {
+                    /* get module */
+                    module = (struct rt_module*)object;
+                    break;
+                }
+            }
+            rt_exit_critical();
+
+            /* there is no this module inside the system */
+            if (module == RT_NULL) return RT_NULL; 
+
+            /* get the object pool of module */
+            information = &(module->module_object[type]);
+
+            /* get object name */
+            while ((*name_ptr == '/') && (*name_ptr != '\0')) name_ptr ++;
+            if (*name_ptr == '\0')
+            {
+                if (type == RT_Object_Class_Module) return object;
+                return RT_NULL;
+            }
+
+            /* point to the object name */
+            name = name_ptr;
+        }
+    }
+#endif
 
     /* enter critical */
     rt_enter_critical();
 
     /* try to find object */
-    information = &rt_object_container[type];
+    if (information == RT_NULL) information = &rt_object_container[type];
     for (node  = information->object_list.next;
          node != &(information->object_list);
          node  = node->next)

From 33fed1b167e1b2a653d9e58853537e40628f4e2e Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 06:29:15 +0800
Subject: [PATCH 63/86] [Kernel] Better documentation for doxygen.

---
 src/device.c | 2 +-
 src/module.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/device.c b/src/device.c
index 2bb3cc0f9c..835a517ce3 100644
--- a/src/device.c
+++ b/src/device.c
@@ -80,7 +80,7 @@ RTM_EXPORT(rt_device_unregister);
  *
  * @return the error code, RT_EOK on successfully.
  *
- * @deprecated This function is not needed because the initialization 
+ * @deprecated since 1.2.x, this function is not needed because the initialization 
  *             of a device is performed when applicaiton opens it.
  */
 rt_err_t rt_device_init_all(void)
diff --git a/src/module.c b/src/module.c
index 0603159b91..5d5d02c580 100644
--- a/src/module.c
+++ b/src/module.c
@@ -1120,8 +1120,8 @@ rt_module_t rt_module_open(const char *path)
  * This function will do a excutable program with main function and parameters.
  *
  * @param path the full path of application module
- * @cmd_line the command line of program
- * @size the size of command line of program
+ * @param cmd_line the command line of program
+ * @param size the size of command line of program
  *
  * @return the module object
  */

From 66c2d28fbfe354f11bcc3ac893ba3935afe47968 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 06:59:50 +0800
Subject: [PATCH 64/86] [bsp] Add MB9BF618 porting.

---
 .../CMSIS END USER LICENCE AGREEMENT.pdf      |   Bin 0 -> 24914 bytes
 .../DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h | 29269 +++++++++++++++
 .../DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h | 29338 ++++++++++++++++
 .../mb9bf61x/startup/arm/startup_mb9bf61x.S   |   333 +
 .../mb9bf61x/startup/gcc/startup_mb9bf61x.c   |   244 +
 .../mb9bf61x/startup/iar/startup_mb9bf61x.S   |   417 +
 .../fujitsu/mb9bf61x/system_mb9bf61x.c        |   206 +
 .../fujitsu/mb9bf61x/system_mb9bf61x.h        |   678 +
 .../CMSIS/Include/arm_common_tables.h         |    93 +
 .../CMSIS/Include/arm_const_structs.h         |    85 +
 bsp/mb9bf618s/CMSIS/Include/arm_math.h        |  7306 ++++
 bsp/mb9bf618s/CMSIS/Include/core_cm0.h        |   682 +
 bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h    |   793 +
 bsp/mb9bf618s/CMSIS/Include/core_cm3.h        |  1627 +
 bsp/mb9bf618s/CMSIS/Include/core_cm4.h        |  1772 +
 bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h   |   673 +
 bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h     |   636 +
 bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h    |   688 +
 bsp/mb9bf618s/CMSIS/Include/core_sc000.h      |   813 +
 bsp/mb9bf618s/CMSIS/Include/core_sc300.h      |  1598 +
 bsp/mb9bf618s/CMSIS/README.txt                |    37 +
 bsp/mb9bf618s/CMSIS/SConscript                |    21 +
 bsp/mb9bf618s/SConscript                      |    14 +
 bsp/mb9bf618s/SConstruct                      |    34 +
 bsp/mb9bf618s/applications/SConscript         |    11 +
 bsp/mb9bf618s/applications/application.c      |    58 +
 bsp/mb9bf618s/applications/startup.c          |    88 +
 bsp/mb9bf618s/drivers/SConscript              |    11 +
 bsp/mb9bf618s/drivers/board.c                 |   100 +
 bsp/mb9bf618s/drivers/board.h                 |    50 +
 bsp/mb9bf618s/drivers/led.c                   |   157 +
 bsp/mb9bf618s/drivers/serial.c                |   437 +
 bsp/mb9bf618s/drivers/serial.h                |    99 +
 bsp/mb9bf618s/rtconfig.h                      |    74 +
 bsp/mb9bf618s/rtconfig.py                     |   118 +
 bsp/mb9bf618s/rtthread-fm3.icf                |    33 +
 bsp/mb9bf618s/rtthread-fm3.ld                 |   143 +
 bsp/mb9bf618s/rtthread-fm3.sct                |    15 +
 bsp/mb9bf618s/template.ewp                    |  1839 +
 bsp/mb9bf618s/template.uvproj                 |   394 +
 40 files changed, 80984 insertions(+)
 create mode 100644 bsp/mb9bf618s/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
 create mode 100644 bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h
 create mode 100644 bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h
 create mode 100644 bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S
 create mode 100644 bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c
 create mode 100644 bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S
 create mode 100644 bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c
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diff --git a/bsp/mb9bf618s/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/bsp/mb9bf618s/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
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HcmV?d00001

diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h
new file mode 100644
index 0000000000..374040f314
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h
@@ -0,0 +1,29269 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/*                                                                      */
+/*  Header File for Device MB9BF618S                                    */
+/*  Version V1.00                                                       */
+/*  Date    2011-08-04                                                  */
+/*                                                                      */
+/************************************************************************/
+
+#ifndef _MB9BF618S_H_
+#define _MB9BF618S_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************************************************
+ * Configuration of the Cortex-M3 Processor and Core Peripherals
+ ******************************************************************************/
+#define __MPU_PRESENT           1 /* FM3 provide an MPU                           */
+#define __NVIC_PRIO_BITS        4 /* FM3 uses 4 Bits for the Priority Levels      */
+#define __Vendor_SysTickConfig  0 /* Set to 1 if different SysTick Config is used */
+
+
+/******************************************************************************
+ * Interrupt Number Definition
+ ******************************************************************************/
+typedef enum IRQn
+{
+    NMI_IRQn          = -14, /*  2 Non Maskable      */
+    HardFault_IRQn    = -13, /*  3 Hard Fault        */
+    MemManage_IRQn    = -12, /*  4 Memory Management */
+    BusFault_IRQn     = -11, /*  5 Bus Fault         */
+    UsageFault_IRQn   = -10, /*  6 Usage Fault       */
+    SVC_IRQn          = -5,  /* 11 SV Call           */
+    DebugMonitor_IRQn = -4,  /* 12 Debug Monitor     */
+    PendSV_IRQn       = -2,  /* 14 Pend SV           */
+    SysTick_IRQn      = -1,  /* 15 System Tick       */
+
+    CSV_IRQn          =  0, /* Clock Super Visor                             */
+    SWDT_IRQn         =  1, /* Software Watchdog Timer                       */
+    LVD_IRQn          =  2, /* Low Voltage Detector                          */
+    WFG_IRQn          =  3, /* Wave Form Generator                           */
+    EXINT0_7_IRQn     =  4, /* External Interrupt Request ch.0 to ch.7       */
+    EXINT8_31_IRQn    =  5, /* External Interrupt Request ch.8 to ch.31      */
+    DTIM_QDU_IRQn     =  6, /* Dual Timer / Quad Decoder                     */
+    MFS0RX_IRQn       =  7, /* MultiFunction Serial Reception ch.0           */
+    MFS0TX_IRQn       =  8, /* MultiFunction Serial Transmission ch.0        */
+    MFS1RX_IRQn       =  9, /* MultiFunction Serial Reception ch.1           */
+    MFS1TX_IRQn       = 10, /* MultiFunction Serial Transmission ch.1        */
+    MFS2RX_IRQn       = 11, /* MultiFunction Serial Reception ch.2           */
+    MFS2TX_IRQn       = 12, /* MultiFunction Serial Transmission ch.2        */
+    MFS3RX_IRQn       = 13, /* MultiFunction Serial Reception ch.3           */
+    MFS3TX_IRQn       = 14, /* MultiFunction Serial Transmission ch.3        */
+    MFS4RX_IRQn       = 15, /* MultiFunction Serial Reception ch.4           */
+    MFS4TX_IRQn       = 16, /* MultiFunction Serial Transmission ch.4        */
+    MFS5RX_IRQn       = 17, /* MultiFunction Serial Reception ch.5           */
+    MFS5TX_IRQn       = 18, /* MultiFunction Serial Transmission ch.5        */
+    MFS6RX_IRQn       = 19, /* MultiFunction Serial Reception ch.6           */
+    MFS6TX_IRQn       = 20, /* MultiFunction Serial Transmission ch.6        */
+    MFS7RX_IRQn       = 21, /* MultiFunction Serial Reception ch.7           */
+    MFS7TX_IRQn       = 22, /* MultiFunction Serial Transmission ch.7        */
+    PPG_IRQn          = 23, /* PPG                                           */
+    OSC_PLL_WC_IRQn   = 24, /* OSC / PLL / Watch Counter                     */
+    ADC0_IRQn         = 25, /* ADC0                                          */
+    ADC1_IRQn         = 26, /* ADC1                                          */
+    ADC2_IRQn         = 27, /* ADC2                                          */
+    FRTIM_IRQn        = 28, /* Free-run Timer                                */
+    INCAP_IRQn        = 29, /* Input Capture                                 */
+    OUTCOMP_IRQn      = 30, /* Output Compare                                */
+    BTIM0_7_IRQn      = 31, /* Base Timer ch.0 to ch.7                       */
+    ETHER_MAC0_IRQn   = 32, /* Ethernet MAC ch.0                             */
+    ETHER_MAC1_IRQn   = 33, /* Ethernet MAC ch.1                             */
+    USB0F_IRQn        = 34, /* USB Function ch.0                             */
+    USB0F_USB0H_IRQn  = 35, /* USB Function ch.0 / USB Host ch.0             */
+    USB1F_IRQn        = 36, /* USB Function ch.1                             */
+    USB1F_USB1H_IRQn  = 37, /* USB Function ch.1 / USB Host ch.1             */
+    DMAC0_IRQn        = 38, /* DMAC ch.0                                     */
+    DMAC1_IRQn        = 39, /* DMAC ch.1                                     */
+    DMAC2_IRQn        = 40, /* DMAC ch.2                                     */
+    DMAC3_IRQn        = 41, /* DMAC ch.3                                     */
+    DMAC4_IRQn        = 42, /* DMAC ch.4                                     */
+    DMAC5_IRQn        = 43, /* DMAC ch.5                                     */
+    DMAC6_IRQn        = 44, /* DMAC ch.6                                     */
+    DMAC7_IRQn        = 45, /* DMAC ch.7                                     */
+    BTIM8_15_IRQn     = 46  /* Base Timer ch.8 to ch.15                      */
+    /* Reserved       = 47                                                   */
+} IRQn_Type;
+
+
+#include <core_cm3.h>
+#include "system_mb9bf61x.h"
+#include <stdint.h>
+
+#define SUCCESS  0
+#define ERROR    -1
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/******************************************************************************
+ * Peripheral register bit fields
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash_IF_MODULE register bit fields */
+typedef struct stc_flash_if_faszr_field
+{
+  __IO uint32_t ASZ0       : 1;
+  __IO uint32_t ASZ1       : 1;
+} stc_flash_if_faszr_field_t;
+
+typedef struct stc_flash_if_frwtr_field
+{
+  __IO uint32_t RWT0       : 1;
+  __IO uint32_t RWT1       : 1;
+} stc_flash_if_frwtr_field_t;
+
+typedef struct stc_flash_if_fstr_field
+{
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t HNG        : 1;
+  __IO uint32_t EER        : 1;
+} stc_flash_if_fstr_field_t;
+
+typedef struct stc_flash_if_fsyndn_field
+{
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+} stc_flash_if_fsyndn_field_t;
+
+typedef struct stc_flash_if_crtrmm_field
+{
+  __IO uint32_t TRMM0      : 1;
+  __IO uint32_t TRMM1      : 1;
+  __IO uint32_t TRMM2      : 1;
+  __IO uint32_t TRMM3      : 1;
+  __IO uint32_t TRMM4      : 1;
+  __IO uint32_t TRMM5      : 1;
+  __IO uint32_t TRMM6      : 1;
+  __IO uint32_t TRMM7      : 1;
+  __IO uint32_t TRMM8      : 1;
+  __IO uint32_t TRMM9      : 1;
+} stc_flash_if_crtrmm_field_t;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock_Reset_MODULE register bit fields */
+typedef struct stc_crg_scm_ctl_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MOSCE      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SOSCE      : 1;
+  __IO  uint8_t PLLE       : 1;
+  __IO  uint8_t RCS0       : 1;
+  __IO  uint8_t RCS1       : 1;
+  __IO  uint8_t RCS2       : 1;
+} stc_crg_scm_ctl_field_t;
+
+typedef struct stc_crg_scm_str_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MORDY      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SORDY      : 1;
+  __IO  uint8_t PLRDY      : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t RCM2       : 1;
+} stc_crg_scm_str_field_t;
+
+typedef struct stc_crg_rst_str_field
+{
+  __IO uint16_t PONR       : 1;
+  __IO uint16_t INITX      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SWDT       : 1;
+  __IO uint16_t HWDT       : 1;
+  __IO uint16_t CSVR       : 1;
+  __IO uint16_t FCSR       : 1;
+  __IO uint16_t SRST       : 1;
+} stc_crg_rst_str_field_t;
+
+typedef struct stc_crg_bsc_psr_field
+{
+  __IO  uint8_t BSR0       : 1;
+  __IO  uint8_t BSR1       : 1;
+  __IO  uint8_t BSR2       : 1;
+} stc_crg_bsc_psr_field_t;
+
+typedef struct stc_crg_apbc0_psr_field
+{
+  __IO  uint8_t APBC00     : 1;
+  __IO  uint8_t APBC01     : 1;
+} stc_crg_apbc0_psr_field_t;
+
+typedef struct stc_crg_apbc1_psr_field
+{
+  __IO  uint8_t APBC10     : 1;
+  __IO  uint8_t APBC11     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC1RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC1EN    : 1;
+} stc_crg_apbc1_psr_field_t;
+
+typedef struct stc_crg_apbc2_psr_field
+{
+  __IO  uint8_t APBC20     : 1;
+  __IO  uint8_t APBC21     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC2RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC2EN    : 1;
+} stc_crg_apbc2_psr_field_t;
+
+typedef struct stc_crg_swc_psr_field
+{
+  __IO  uint8_t SWDS0      : 1;
+  __IO  uint8_t SWDS1      : 1;
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t TESTB      : 1;
+} stc_crg_swc_psr_field_t;
+
+typedef struct stc_crg_ttc_psr_field
+{
+  __IO  uint8_t TTC0       : 1;
+  __IO  uint8_t TTC1       : 1;
+} stc_crg_ttc_psr_field_t;
+
+typedef struct stc_crg_csw_tmr_field
+{
+  __IO  uint8_t MOWT0      : 1;
+  __IO  uint8_t MOWT1      : 1;
+  __IO  uint8_t MOWT2      : 1;
+  __IO  uint8_t MOWT3      : 1;
+  __IO  uint8_t SOWT0      : 1;
+  __IO  uint8_t SOWT1      : 1;
+  __IO  uint8_t SOWT2      : 1;
+} stc_crg_csw_tmr_field_t;
+
+typedef struct stc_crg_psw_tmr_field
+{
+  __IO  uint8_t POWT0      : 1;
+  __IO  uint8_t POWT1      : 1;
+  __IO  uint8_t POWT2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t PINC       : 1;
+} stc_crg_psw_tmr_field_t;
+
+typedef struct stc_crg_pll_ctl1_field
+{
+  __IO  uint8_t PLLM0      : 1;
+  __IO  uint8_t PLLM1      : 1;
+  __IO  uint8_t PLLM2      : 1;
+  __IO  uint8_t PLLM3      : 1;
+  __IO  uint8_t PLLK0      : 1;
+  __IO  uint8_t PLLK1      : 1;
+  __IO  uint8_t PLLK2      : 1;
+  __IO  uint8_t PLLK3      : 1;
+} stc_crg_pll_ctl1_field_t;
+
+typedef struct stc_crg_pll_ctl2_field
+{
+  __IO  uint8_t PLLN0      : 1;
+  __IO  uint8_t PLLN1      : 1;
+  __IO  uint8_t PLLN2      : 1;
+  __IO  uint8_t PLLN3      : 1;
+  __IO  uint8_t PLLN4      : 1;
+  __IO  uint8_t PLLN5      : 1;
+} stc_crg_pll_ctl2_field_t;
+
+typedef struct stc_crg_csv_ctl_field
+{
+  __IO uint16_t MCSVE      : 1;
+  __IO uint16_t SCSVE      : 1;
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t FCSDE      : 1;
+  __IO uint16_t FCSRE      : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t FCD0       : 1;
+  __IO uint16_t FCD1       : 1;
+  __IO uint16_t FCD2       : 1;
+} stc_crg_csv_ctl_field_t;
+
+typedef struct stc_crg_csv_str_field
+{
+  __IO  uint8_t MCMF       : 1;
+  __IO  uint8_t SCMF       : 1;
+} stc_crg_csv_str_field_t;
+
+typedef struct stc_crg_dbwdt_ctl_field
+{
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t DPSWBE     : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t DPHWBE     : 1;
+} stc_crg_dbwdt_ctl_field_t;
+
+typedef struct stc_crg_int_enr_field
+{
+  __IO  uint8_t MCSE       : 1;
+  __IO  uint8_t SCSE       : 1;
+  __IO  uint8_t PCSE       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSE       : 1;
+} stc_crg_int_enr_field_t;
+
+typedef struct stc_crg_int_str_field
+{
+  __IO  uint8_t MCSI       : 1;
+  __IO  uint8_t SCSI       : 1;
+  __IO  uint8_t PCSI       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSI       : 1;
+} stc_crg_int_str_field_t;
+
+typedef struct stc_crg_int_clr_field
+{
+  __IO  uint8_t MCSC       : 1;
+  __IO  uint8_t SCSC       : 1;
+  __IO  uint8_t PCSC       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSC       : 1;
+} stc_crg_int_clr_field_t;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* HWWDT_MODULE register bit fields */
+typedef struct stc_hwwdt_wdg_ctl_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_hwwdt_wdg_ctl_field_t;
+
+typedef struct stc_hwwdt_wdg_ris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_hwwdt_wdg_ris_field_t;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* SWWDT_MODULE register bit fields */
+typedef struct stc_swwdt_wdogcontrol_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_swwdt_wdogcontrol_field_t;
+
+typedef struct stc_swwdt_wdogris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_swwdt_wdogris_field_t;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* DTIM_MODULE register bit fields */
+typedef struct stc_dtim_timer1control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer1control_field_t;
+
+typedef struct stc_dtim_timer1ris_field
+{
+  __IO uint32_t TIMER1RIS  : 1;
+} stc_dtim_timer1ris_field_t;
+
+typedef struct stc_dtim_timer1mis_field
+{
+  __IO uint32_t TIMER1MIS  : 1;
+} stc_dtim_timer1mis_field_t;
+
+typedef struct stc_dtim_timer2control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer2control_field_t;
+
+typedef struct stc_dtim_timer2ris_field
+{
+  __IO uint32_t TIMER2RIS  : 1;
+} stc_dtim_timer2ris_field_t;
+
+typedef struct stc_dtim_timer2mis_field
+{
+  __IO uint32_t TIMER2MIS  : 1;
+} stc_dtim_timer2mis_field_t;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* MFT_FRT_MODULE register bit fields */
+typedef struct stc_mft_frt_tcsa0_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa0_field_t;
+
+typedef struct stc_mft_frt_tcsb0_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb0_field_t;
+
+typedef struct stc_mft_frt_tcsa1_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa1_field_t;
+
+typedef struct stc_mft_frt_tcsb1_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb1_field_t;
+
+typedef struct stc_mft_frt_tcsa2_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa2_field_t;
+
+typedef struct stc_mft_frt_tcsb2_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb2_field_t;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* MFT_OCU_MODULE register bit fields */
+typedef struct stc_mft_ocu_ocsa10_field
+{
+  __IO  uint8_t CST0       : 1;
+  __IO  uint8_t CST1       : 1;
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t IOE0       : 1;
+  __IO  uint8_t IOE1       : 1;
+  __IO  uint8_t IOP0       : 1;
+  __IO  uint8_t IOP1       : 1;
+} stc_mft_ocu_ocsa10_field_t;
+
+typedef struct stc_mft_ocu_ocsb10_field
+{
+  __IO  uint8_t OTD0       : 1;
+  __IO  uint8_t OTD1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+} stc_mft_ocu_ocsb10_field_t;
+
+typedef struct stc_mft_ocu_ocsa32_field
+{
+  __IO  uint8_t CST2       : 1;
+  __IO  uint8_t CST3       : 1;
+  __IO  uint8_t BDIS2      : 1;
+  __IO  uint8_t BDIS3      : 1;
+  __IO  uint8_t IOE2       : 1;
+  __IO  uint8_t IOE3       : 1;
+  __IO  uint8_t IOP2       : 1;
+  __IO  uint8_t IOP3       : 1;
+} stc_mft_ocu_ocsa32_field_t;
+
+typedef struct stc_mft_ocu_ocsb32_field
+{
+  __IO  uint8_t OTD2       : 1;
+  __IO  uint8_t OTD3       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS2       : 1;
+  __IO  uint8_t BTS3       : 1;
+} stc_mft_ocu_ocsb32_field_t;
+
+typedef struct stc_mft_ocu_ocsa54_field
+{
+  __IO  uint8_t CST4       : 1;
+  __IO  uint8_t CST5       : 1;
+  __IO  uint8_t BDIS4      : 1;
+  __IO  uint8_t BDIS5      : 1;
+  __IO  uint8_t IOE4       : 1;
+  __IO  uint8_t IOE5       : 1;
+  __IO  uint8_t IOP4       : 1;
+  __IO  uint8_t IOP5       : 1;
+} stc_mft_ocu_ocsa54_field_t;
+
+typedef struct stc_mft_ocu_ocsb54_field
+{
+  __IO  uint8_t OTD4       : 1;
+  __IO  uint8_t OTD5       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS4       : 1;
+  __IO  uint8_t BTS5       : 1;
+} stc_mft_ocu_ocsb54_field_t;
+
+typedef struct stc_mft_ocu_ocsc_field
+{
+  __IO  uint8_t MOD0       : 1;
+  __IO  uint8_t MOD1       : 1;
+  __IO  uint8_t MOD2       : 1;
+  __IO  uint8_t MOD3       : 1;
+  __IO  uint8_t MOD4       : 1;
+  __IO  uint8_t MOD5       : 1;
+} stc_mft_ocu_ocsc_field_t;
+
+typedef struct stc_mft_ocu_ocfs10_field
+{
+  __IO  uint8_t FSO00      : 1;
+  __IO  uint8_t FSO01      : 1;
+  __IO  uint8_t FSO02      : 1;
+  __IO  uint8_t FSO03      : 1;
+  __IO  uint8_t FSO10      : 1;
+  __IO  uint8_t FSO11      : 1;
+  __IO  uint8_t FSO12      : 1;
+  __IO  uint8_t FSO13      : 1;
+} stc_mft_ocu_ocfs10_field_t;
+
+typedef struct stc_mft_ocu_ocfs32_field
+{
+  __IO  uint8_t FSO20      : 1;
+  __IO  uint8_t FSO21      : 1;
+  __IO  uint8_t FSO22      : 1;
+  __IO  uint8_t FSO23      : 1;
+  __IO  uint8_t FSO30      : 1;
+  __IO  uint8_t FSO31      : 1;
+  __IO  uint8_t FSO32      : 1;
+  __IO  uint8_t FSO33      : 1;
+} stc_mft_ocu_ocfs32_field_t;
+
+typedef struct stc_mft_ocu_ocfs54_field
+{
+  __IO  uint8_t FSO40      : 1;
+  __IO  uint8_t FSO41      : 1;
+  __IO  uint8_t FSO42      : 1;
+  __IO  uint8_t FSO43      : 1;
+  __IO  uint8_t FSO50      : 1;
+  __IO  uint8_t FSO51      : 1;
+  __IO  uint8_t FSO52      : 1;
+  __IO  uint8_t FSO53      : 1;
+} stc_mft_ocu_ocfs54_field_t;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* MFT_WFG_MODULE register bit fields */
+typedef struct stc_mft_wfg_wfsa10_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD0       : 1;
+  __IO uint16_t TMD1       : 1;
+  __IO uint16_t TMD2       : 1;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa10_field_t;
+
+typedef struct stc_mft_wfg_wfsa32_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD0       : 1;
+  __IO uint16_t TMD1       : 1;
+  __IO uint16_t TMD2       : 1;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa32_field_t;
+
+typedef struct stc_mft_wfg_wfsa54_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD0       : 1;
+  __IO uint16_t TMD1       : 1;
+  __IO uint16_t TMD2       : 1;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa54_field_t;
+
+typedef struct stc_mft_wfg_wfir_field
+{
+  __IO uint16_t DTIF       : 1;
+  __IO uint16_t DTIC       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t TMIF10     : 1;
+  __IO uint16_t TMIC10     : 1;
+  __IO uint16_t TMIE10     : 1;
+  __IO uint16_t TMIS10     : 1;
+  __IO uint16_t TMIF32     : 1;
+  __IO uint16_t TMIC32     : 1;
+  __IO uint16_t TMIE32     : 1;
+  __IO uint16_t TMIS32     : 1;
+  __IO uint16_t TMIF54     : 1;
+  __IO uint16_t TMIC54     : 1;
+  __IO uint16_t TMIE54     : 1;
+  __IO uint16_t TMIS54     : 1;
+} stc_mft_wfg_wfir_field_t;
+
+typedef struct stc_mft_wfg_nzcl_field
+{
+  __IO uint16_t DTIE       : 1;
+  __IO uint16_t NWS0       : 1;
+  __IO uint16_t NWS1       : 1;
+  __IO uint16_t NWS2       : 1;
+  __IO uint16_t SDTI       : 1;
+} stc_mft_wfg_nzcl_field_t;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* MFT_ICU_MODULE register bit fields */
+typedef struct stc_mft_icu_icfs10_field
+{
+  __IO  uint8_t FSI00      : 1;
+  __IO  uint8_t FSI01      : 1;
+  __IO  uint8_t FSI02      : 1;
+  __IO  uint8_t FSI03      : 1;
+  __IO  uint8_t FSI10      : 1;
+  __IO  uint8_t FSI11      : 1;
+  __IO  uint8_t FSI12      : 1;
+  __IO  uint8_t FSI13      : 1;
+} stc_mft_icu_icfs10_field_t;
+
+typedef struct stc_mft_icu_icfs32_field
+{
+  __IO  uint8_t FSI20      : 1;
+  __IO  uint8_t FSI21      : 1;
+  __IO  uint8_t FSI22      : 1;
+  __IO  uint8_t FSI23      : 1;
+  __IO  uint8_t FSI30      : 1;
+  __IO  uint8_t FSI31      : 1;
+  __IO  uint8_t FSI32      : 1;
+  __IO  uint8_t FSI33      : 1;
+} stc_mft_icu_icfs32_field_t;
+
+typedef struct stc_mft_icu_icsa10_field
+{
+  __IO  uint8_t EG00       : 1;
+  __IO  uint8_t EG01       : 1;
+  __IO  uint8_t EG10       : 1;
+  __IO  uint8_t EG11       : 1;
+  __IO  uint8_t ICE0       : 1;
+  __IO  uint8_t ICE1       : 1;
+  __IO  uint8_t ICP0       : 1;
+  __IO  uint8_t ICP1       : 1;
+} stc_mft_icu_icsa10_field_t;
+
+typedef struct stc_mft_icu_icsb10_field
+{
+  __IO  uint8_t IEI0       : 1;
+  __IO  uint8_t IEI1       : 1;
+} stc_mft_icu_icsb10_field_t;
+
+typedef struct stc_mft_icu_icsa32_field
+{
+  __IO  uint8_t EG20       : 1;
+  __IO  uint8_t EG21       : 1;
+  __IO  uint8_t EG30       : 1;
+  __IO  uint8_t EG31       : 1;
+  __IO  uint8_t ICE2       : 1;
+  __IO  uint8_t ICE3       : 1;
+  __IO  uint8_t ICP2       : 1;
+  __IO  uint8_t ICP3       : 1;
+} stc_mft_icu_icsa32_field_t;
+
+typedef struct stc_mft_icu_icsb32_field
+{
+  __IO  uint8_t IEI2       : 1;
+  __IO  uint8_t IEI3       : 1;
+} stc_mft_icu_icsb32_field_t;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* MFT_ADCMP_MODULE register bit fields */
+typedef struct stc_mft_adcmp_acsb_field
+{
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t BDIS2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+  __IO  uint8_t BTS2       : 1;
+} stc_mft_adcmp_acsb_field_t;
+
+typedef struct stc_mft_adcmp_acsa_field
+{
+  __IO uint16_t CE00       : 1;
+  __IO uint16_t CE01       : 1;
+  __IO uint16_t CE10       : 1;
+  __IO uint16_t CE11       : 1;
+  __IO uint16_t CE20       : 1;
+  __IO uint16_t CE21       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SEL00      : 1;
+  __IO uint16_t SEL01      : 1;
+  __IO uint16_t SEL10      : 1;
+  __IO uint16_t SEL11      : 1;
+  __IO uint16_t SEL20      : 1;
+  __IO uint16_t SEL21      : 1;
+} stc_mft_adcmp_acsa_field_t;
+
+typedef struct stc_mft_adcmp_atsa_field
+{
+  __IO uint16_t AD0S0      : 1;
+  __IO uint16_t AD0S1      : 1;
+  __IO uint16_t AD1S0      : 1;
+  __IO uint16_t AD1S1      : 1;
+  __IO uint16_t AD2S0      : 1;
+  __IO uint16_t AD2S1      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t AD0P0      : 1;
+  __IO uint16_t AD0P1      : 1;
+  __IO uint16_t AD1P0      : 1;
+  __IO uint16_t AD1P1      : 1;
+  __IO uint16_t AD2P0      : 1;
+  __IO uint16_t AD2P1      : 1;
+} stc_mft_adcmp_atsa_field_t;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* MFT_PPG_MODULE register bit fields */
+typedef struct stc_mft_ppg_ttcr0_field
+{
+  __IO  uint8_t STR0       : 1;
+  __IO  uint8_t MONI0      : 1;
+  __IO  uint8_t CS00       : 1;
+  __IO  uint8_t CS01       : 1;
+  __IO  uint8_t TRG0O      : 1;
+  __IO  uint8_t TRG2O      : 1;
+  __IO  uint8_t TRG4O      : 1;
+  __IO  uint8_t TRG6O      : 1;
+} stc_mft_ppg_ttcr0_field_t;
+
+typedef struct stc_mft_ppg_ttcr1_field
+{
+  __IO  uint8_t STR1       : 1;
+  __IO  uint8_t MONI1      : 1;
+  __IO  uint8_t CS10       : 1;
+  __IO  uint8_t CS11       : 1;
+  __IO  uint8_t TRG1O      : 1;
+  __IO  uint8_t TRG3O      : 1;
+  __IO  uint8_t TRG5O      : 1;
+  __IO  uint8_t TRG7O      : 1;
+} stc_mft_ppg_ttcr1_field_t;
+
+typedef struct stc_mft_ppg_ttcr2_field
+{
+  __IO  uint8_t STR2       : 1;
+  __IO  uint8_t MONI2      : 1;
+  __IO  uint8_t CS20       : 1;
+  __IO  uint8_t CS21       : 1;
+  __IO  uint8_t TRG16O     : 1;
+  __IO  uint8_t TRG18O     : 1;
+  __IO  uint8_t TRG20O     : 1;
+  __IO  uint8_t TRG22O     : 1;
+} stc_mft_ppg_ttcr2_field_t;
+
+typedef struct stc_mft_ppg_trg_field
+{
+  __IO uint16_t PEN00      : 1;
+  __IO uint16_t PEN01      : 1;
+  __IO uint16_t PEN02      : 1;
+  __IO uint16_t PEN03      : 1;
+  __IO uint16_t PEN04      : 1;
+  __IO uint16_t PEN05      : 1;
+  __IO uint16_t PEN06      : 1;
+  __IO uint16_t PEN07      : 1;
+  __IO uint16_t PEN08      : 1;
+  __IO uint16_t PEN09      : 1;
+  __IO uint16_t PEN10      : 1;
+  __IO uint16_t PEN11      : 1;
+  __IO uint16_t PEN12      : 1;
+  __IO uint16_t PEN13      : 1;
+  __IO uint16_t PEN14      : 1;
+  __IO uint16_t PEN15      : 1;
+} stc_mft_ppg_trg_field_t;
+
+typedef struct stc_mft_ppg_trg1_field
+{
+  __IO uint16_t PEN16      : 1;
+  __IO uint16_t PEN17      : 1;
+  __IO uint16_t PEN18      : 1;
+  __IO uint16_t PEN19      : 1;
+  __IO uint16_t PEN20      : 1;
+  __IO uint16_t PEN21      : 1;
+  __IO uint16_t PEN22      : 1;
+  __IO uint16_t PEN23      : 1;
+} stc_mft_ppg_trg1_field_t;
+
+typedef struct stc_mft_ppg_revc_field
+{
+  __IO uint16_t REV00      : 1;
+  __IO uint16_t REV01      : 1;
+  __IO uint16_t REV02      : 1;
+  __IO uint16_t REV03      : 1;
+  __IO uint16_t REV04      : 1;
+  __IO uint16_t REV05      : 1;
+  __IO uint16_t REV06      : 1;
+  __IO uint16_t REV07      : 1;
+  __IO uint16_t REV08      : 1;
+  __IO uint16_t REV09      : 1;
+  __IO uint16_t REV10      : 1;
+  __IO uint16_t REV11      : 1;
+  __IO uint16_t REV12      : 1;
+  __IO uint16_t REV13      : 1;
+  __IO uint16_t REV14      : 1;
+  __IO uint16_t REV15      : 1;
+} stc_mft_ppg_revc_field_t;
+
+typedef struct stc_mft_ppg_revc1_field
+{
+  __IO uint16_t REV16      : 1;
+  __IO uint16_t REV17      : 1;
+  __IO uint16_t REV18      : 1;
+  __IO uint16_t REV19      : 1;
+  __IO uint16_t REV20      : 1;
+  __IO uint16_t REV21      : 1;
+  __IO uint16_t REV22      : 1;
+  __IO uint16_t REV23      : 1;
+} stc_mft_ppg_revc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc1_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc0_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc0_field_t;
+
+typedef struct stc_mft_ppg_ppgc3_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc3_field_t;
+
+typedef struct stc_mft_ppg_ppgc2_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc2_field_t;
+
+typedef struct stc_mft_ppg_gatec0_field
+{
+  __IO  uint8_t EDGE0      : 1;
+  __IO  uint8_t STRG0      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE2      : 1;
+  __IO  uint8_t STRG2      : 1;
+} stc_mft_ppg_gatec0_field_t;
+
+typedef struct stc_mft_ppg_ppgc5_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc5_field_t;
+
+typedef struct stc_mft_ppg_ppgc4_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc4_field_t;
+
+typedef struct stc_mft_ppg_ppgc7_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc7_field_t;
+
+typedef struct stc_mft_ppg_ppgc6_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc6_field_t;
+
+typedef struct stc_mft_ppg_gatec4_field
+{
+  __IO  uint8_t EDGE4      : 1;
+  __IO  uint8_t STRG4      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE6      : 1;
+  __IO  uint8_t STRG6      : 1;
+} stc_mft_ppg_gatec4_field_t;
+
+typedef struct stc_mft_ppg_ppgc9_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc9_field_t;
+
+typedef struct stc_mft_ppg_ppgc8_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc8_field_t;
+
+typedef struct stc_mft_ppg_ppgc11_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc11_field_t;
+
+typedef struct stc_mft_ppg_ppgc10_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc10_field_t;
+
+typedef struct stc_mft_ppg_gatec8_field
+{
+  __IO  uint8_t EDGE8      : 1;
+  __IO  uint8_t STRG8      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE10     : 1;
+  __IO  uint8_t STRG10     : 1;
+} stc_mft_ppg_gatec8_field_t;
+
+typedef struct stc_mft_ppg_ppgc13_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc13_field_t;
+
+typedef struct stc_mft_ppg_ppgc12_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc12_field_t;
+
+typedef struct stc_mft_ppg_ppgc15_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc15_field_t;
+
+typedef struct stc_mft_ppg_ppgc14_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc14_field_t;
+
+typedef struct stc_mft_ppg_gatec12_field
+{
+  __IO  uint8_t EDGE12     : 1;
+  __IO  uint8_t STRG12     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE14     : 1;
+  __IO  uint8_t STRG14     : 1;
+} stc_mft_ppg_gatec12_field_t;
+
+typedef struct stc_mft_ppg_ppgc17_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc17_field_t;
+
+typedef struct stc_mft_ppg_ppgc16_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc16_field_t;
+
+typedef struct stc_mft_ppg_ppgc19_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc19_field_t;
+
+typedef struct stc_mft_ppg_ppgc18_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc18_field_t;
+
+typedef struct stc_mft_ppg_gatec16_field
+{
+  __IO  uint8_t EDGE16     : 1;
+  __IO  uint8_t STRG16     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE18     : 1;
+  __IO  uint8_t STRG18     : 1;
+} stc_mft_ppg_gatec16_field_t;
+
+typedef struct stc_mft_ppg_ppgc21_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc21_field_t;
+
+typedef struct stc_mft_ppg_ppgc20_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc20_field_t;
+
+typedef struct stc_mft_ppg_ppgc23_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc23_field_t;
+
+typedef struct stc_mft_ppg_ppgc22_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc22_field_t;
+
+typedef struct stc_mft_ppg_gatec20_field
+{
+  __IO  uint8_t EDGE20     : 1;
+  __IO  uint8_t STRG20     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE22     : 1;
+  __IO  uint8_t STRG22     : 1;
+} stc_mft_ppg_gatec20_field_t;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* BT_PPG_MODULE register bit fields */
+typedef struct stc_bt_ppg_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_ppg_tmcr_field_t;
+
+typedef struct stc_bt_ppg_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_ppg_stc_field_t;
+
+typedef struct stc_bt_ppg_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_ppg_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* BT_PWM_MODULE register bit fields */
+typedef struct stc_bt_pwm_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwm_tmcr_field_t;
+
+typedef struct stc_bt_pwm_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+  __IO  uint8_t DTIR       : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t UDIE       : 1;
+  __IO  uint8_t DTIE       : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_pwm_stc_field_t;
+
+typedef struct stc_bt_pwm_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwm_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* BT_RT_MODULE register bit fields */
+typedef struct stc_bt_rt_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_rt_tmcr_field_t;
+
+typedef struct stc_bt_rt_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_rt_stc_field_t;
+
+typedef struct stc_bt_rt_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_rt_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* BT_PWC_MODULE register bit fields */
+typedef struct stc_bt_pwc_tmcr_field
+{
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t EGS2       : 1;
+       uint16_t RESERVED3  : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwc_tmcr_field_t;
+
+typedef struct stc_bt_pwc_stc_field
+{
+  __IO  uint8_t OVIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t EDIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t OVIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t EDIE       : 1;
+  __IO  uint8_t ERR        : 1;
+} stc_bt_pwc_stc_field_t;
+
+typedef struct stc_bt_pwc_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwc_tmcr2_field_t;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* BTIOSEL03_MODULE register bit fields */
+typedef struct stc_btiosel03_btsel0123_field
+{
+  __IO  uint8_t SEL01_0    : 1;
+  __IO  uint8_t SEL01_1    : 1;
+  __IO  uint8_t SEL01_2    : 1;
+  __IO  uint8_t SEL01_3    : 1;
+  __IO  uint8_t SEL23_0    : 1;
+  __IO  uint8_t SEL23_1    : 1;
+  __IO  uint8_t SEL23_2    : 1;
+  __IO  uint8_t SEL23_3    : 1;
+} stc_btiosel03_btsel0123_field_t;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* BTIOSEL47_MODULE register bit fields */
+typedef struct stc_btiosel47_btsel4567_field
+{
+  __IO  uint8_t SEL45_0    : 1;
+  __IO  uint8_t SEL45_1    : 1;
+  __IO  uint8_t SEL45_2    : 1;
+  __IO  uint8_t SEL45_3    : 1;
+  __IO  uint8_t SEL67_0    : 1;
+  __IO  uint8_t SEL67_1    : 1;
+  __IO  uint8_t SEL67_2    : 1;
+  __IO  uint8_t SEL67_3    : 1;
+} stc_btiosel47_btsel4567_field_t;
+
+/******************************************************************************
+ * BTIOSEL811_MODULE
+ ******************************************************************************/
+/* BTIOSEL811_MODULE register bit fields */
+typedef struct stc_btiosel8b_btsel89ab_field
+{
+  __IO  uint8_t SEL89_0    : 1;
+  __IO  uint8_t SEL89_1    : 1;
+  __IO  uint8_t SEL89_2    : 1;
+  __IO  uint8_t SEL89_3    : 1;
+  __IO  uint8_t SELAB_0    : 1;
+  __IO  uint8_t SELAB_1    : 1;
+  __IO  uint8_t SELAB_2    : 1;
+  __IO  uint8_t SELAB_3    : 1;
+} stc_btiosel8b_btsel89ab_field_t;
+
+/******************************************************************************
+ * BTIOSEL1215_MODULE
+ ******************************************************************************/
+/* BTIOSEL1215_MODULE register bit fields */
+typedef struct stc_btioselcf_btselcdef_field
+{
+  __IO  uint8_t SELCD_0    : 1;
+  __IO  uint8_t SELCD_1    : 1;
+  __IO  uint8_t SELCD_2    : 1;
+  __IO  uint8_t SELCD_3    : 1;
+  __IO  uint8_t SELEF_0    : 1;
+  __IO  uint8_t SELEF_1    : 1;
+  __IO  uint8_t SELEF_2    : 1;
+  __IO  uint8_t SELEF_3    : 1;
+} stc_btioselcf_btselcdef_field_t;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* SBSSR_MODULE register bit fields */
+typedef struct stc_sbssr_btsssr_field
+{
+  __IO uint16_t SSR0       : 1;
+  __IO uint16_t SSR1       : 1;
+  __IO uint16_t SSR2       : 1;
+  __IO uint16_t SSR3       : 1;
+  __IO uint16_t SSR4       : 1;
+  __IO uint16_t SSR5       : 1;
+  __IO uint16_t SSR6       : 1;
+  __IO uint16_t SSR7       : 1;
+  __IO uint16_t SSR8       : 1;
+  __IO uint16_t SSR9       : 1;
+  __IO uint16_t SSR10      : 1;
+  __IO uint16_t SSR11      : 1;
+  __IO uint16_t SSR12      : 1;
+  __IO uint16_t SSR13      : 1;
+  __IO uint16_t SSR14      : 1;
+  __IO uint16_t SSR15      : 1;
+} stc_sbssr_btsssr_field_t;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* QPRC_MODULE register bit fields */
+typedef struct stc_qprc_qicr_field
+{
+  __IO uint16_t QPCMIE     : 1;
+  __IO uint16_t QPCMF      : 1;
+  __IO uint16_t QPRCMIE    : 1;
+  __IO uint16_t QPRCMF     : 1;
+  __IO uint16_t OUZIE      : 1;
+  __IO uint16_t UFDF       : 1;
+  __IO uint16_t OFDF       : 1;
+  __IO uint16_t ZIIF       : 1;
+  __IO uint16_t CDCIE      : 1;
+  __IO uint16_t CDCF       : 1;
+  __IO uint16_t DIRPC      : 1;
+  __IO uint16_t DIROU      : 1;
+  __IO uint16_t QPCNRCMIE  : 1;
+  __IO uint16_t QPCNRCMF   : 1;
+} stc_qprc_qicr_field_t;
+
+typedef struct stc_qprc_qicrl_field
+{
+  __IO  uint8_t QPCMIE     : 1;
+  __IO  uint8_t QPCMF      : 1;
+  __IO  uint8_t QPRCMIE    : 1;
+  __IO  uint8_t QPRCMF     : 1;
+  __IO  uint8_t OUZIE      : 1;
+  __IO  uint8_t UFDF       : 1;
+  __IO  uint8_t OFDF       : 1;
+  __IO  uint8_t ZIIF       : 1;
+} stc_qprc_qicrl_field_t;
+
+typedef struct stc_qprc_qicrh_field
+{
+  __IO  uint8_t CDCIE      : 1;
+  __IO  uint8_t CDCF       : 1;
+  __IO  uint8_t DIRPC      : 1;
+  __IO  uint8_t DIROU      : 1;
+  __IO  uint8_t QPCNRCMIE  : 1;
+  __IO  uint8_t QPCNRCMF   : 1;
+} stc_qprc_qicrh_field_t;
+
+typedef struct stc_qprc_qcr_field
+{
+  __IO uint16_t PCM0       : 1;
+  __IO uint16_t PCM1       : 1;
+  __IO uint16_t RCM0       : 1;
+  __IO uint16_t RCM1       : 1;
+  __IO uint16_t PSTP       : 1;
+  __IO uint16_t CGSC       : 1;
+  __IO uint16_t RSEL       : 1;
+  __IO uint16_t SWAP       : 1;
+  __IO uint16_t PCRM0      : 1;
+  __IO uint16_t PCRM1      : 1;
+  __IO uint16_t AES0       : 1;
+  __IO uint16_t AES1       : 1;
+  __IO uint16_t BES0       : 1;
+  __IO uint16_t BES1       : 1;
+  __IO uint16_t CGE0       : 1;
+  __IO uint16_t CGE1       : 1;
+} stc_qprc_qcr_field_t;
+
+typedef struct stc_qprc_qcrl_field
+{
+  __IO  uint8_t PCM0       : 1;
+  __IO  uint8_t PCM1       : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t PSTP       : 1;
+  __IO  uint8_t CGSC       : 1;
+  __IO  uint8_t RSEL       : 1;
+  __IO  uint8_t SWAP       : 1;
+} stc_qprc_qcrl_field_t;
+
+typedef struct stc_qprc_qcrh_field
+{
+  __IO  uint8_t PCRM0      : 1;
+  __IO  uint8_t PCRM1      : 1;
+  __IO  uint8_t AES0       : 1;
+  __IO  uint8_t AES1       : 1;
+  __IO  uint8_t BES0       : 1;
+  __IO  uint8_t BES1       : 1;
+  __IO  uint8_t CGE0       : 1;
+  __IO  uint8_t CGE1       : 1;
+} stc_qprc_qcrh_field_t;
+
+typedef struct stc_qprc_qecr_field
+{
+  __IO uint16_t ORNGMD     : 1;
+  __IO uint16_t ORNGF      : 1;
+  __IO uint16_t ORNGIE     : 1;
+} stc_qprc_qecr_field_t;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* ADC12_MODULE register bit fields */
+typedef struct stc_adc_adsr_field
+{
+  __IO  uint8_t SCS        : 1;
+  __IO  uint8_t PCS        : 1;
+  __IO  uint8_t PCNS       : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t FDAS       : 1;
+  __IO  uint8_t ADSTP      : 1;
+} stc_adc_adsr_field_t;
+
+typedef struct stc_adc_adcr_field
+{
+  __IO  uint8_t OVRIE      : 1;
+  __IO  uint8_t CMPIE      : 1;
+  __IO  uint8_t PCIE       : 1;
+  __IO  uint8_t SCIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t CMPIF      : 1;
+  __IO  uint8_t PCIF       : 1;
+  __IO  uint8_t SCIF       : 1;
+} stc_adc_adcr_field_t;
+
+typedef struct stc_adc_sfns_field
+{
+  __IO  uint8_t SFS0       : 1;
+  __IO  uint8_t SFS1       : 1;
+  __IO  uint8_t SFS2       : 1;
+  __IO  uint8_t SFS3       : 1;
+} stc_adc_sfns_field_t;
+
+typedef struct stc_adc_sccr_field
+{
+  __IO  uint8_t SSTR       : 1;
+  __IO  uint8_t SHEN       : 1;
+  __IO  uint8_t RPT        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t SFCLR      : 1;
+  __IO  uint8_t SOVR       : 1;
+  __IO  uint8_t SFUL       : 1;
+  __IO  uint8_t SEMP       : 1;
+} stc_adc_sccr_field_t;
+
+typedef struct stc_adc_scfd_field
+{
+  __IO uint32_t SC0        : 1;
+  __IO uint32_t SC1        : 1;
+  __IO uint32_t SC2        : 1;
+  __IO uint32_t SC3        : 1;
+  __IO uint32_t SC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+  __IO uint32_t SD3        : 1;
+  __IO uint32_t SD4        : 1;
+  __IO uint32_t SD5        : 1;
+  __IO uint32_t SD6        : 1;
+  __IO uint32_t SD7        : 1;
+  __IO uint32_t SD8        : 1;
+  __IO uint32_t SD9        : 1;
+  __IO uint32_t SD10       : 1;
+  __IO uint32_t SD11       : 1;
+} stc_adc_scfd_field_t;
+
+typedef struct stc_adc_scfdl_field
+{
+  __IO uint16_t SC0        : 1;
+  __IO uint16_t SC1        : 1;
+  __IO uint16_t SC2        : 1;
+  __IO uint16_t SC3        : 1;
+  __IO uint16_t SC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t INVL       : 1;
+} stc_adc_scfdl_field_t;
+
+typedef struct stc_adc_scfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t SD0        : 1;
+  __IO uint16_t SD1        : 1;
+  __IO uint16_t SD2        : 1;
+  __IO uint16_t SD3        : 1;
+  __IO uint16_t SD4        : 1;
+  __IO uint16_t SD5        : 1;
+  __IO uint16_t SD6        : 1;
+  __IO uint16_t SD7        : 1;
+  __IO uint16_t SD8        : 1;
+  __IO uint16_t SD9        : 1;
+  __IO uint16_t SD10       : 1;
+  __IO uint16_t SD11       : 1;
+} stc_adc_scfdh_field_t;
+
+typedef struct stc_adc_scis23_field
+{
+  __IO uint16_t AN16       : 1;
+  __IO uint16_t AN17       : 1;
+  __IO uint16_t AN18       : 1;
+  __IO uint16_t AN19       : 1;
+  __IO uint16_t AN20       : 1;
+  __IO uint16_t AN21       : 1;
+  __IO uint16_t AN22       : 1;
+  __IO uint16_t AN23       : 1;
+  __IO uint16_t AN24       : 1;
+  __IO uint16_t AN25       : 1;
+  __IO uint16_t AN26       : 1;
+  __IO uint16_t AN27       : 1;
+  __IO uint16_t AN28       : 1;
+  __IO uint16_t AN29       : 1;
+  __IO uint16_t AN30       : 1;
+  __IO uint16_t AN31       : 1;
+} stc_adc_scis23_field_t;
+
+typedef struct stc_adc_scis2_field
+{
+  __IO  uint8_t AN16       : 1;
+  __IO  uint8_t AN17       : 1;
+  __IO  uint8_t AN18       : 1;
+  __IO  uint8_t AN19       : 1;
+  __IO  uint8_t AN20       : 1;
+  __IO  uint8_t AN21       : 1;
+  __IO  uint8_t AN22       : 1;
+  __IO  uint8_t AN23       : 1;
+} stc_adc_scis2_field_t;
+
+typedef struct stc_adc_scis3_field
+{
+  __IO  uint8_t AN24       : 1;
+  __IO  uint8_t AN25       : 1;
+  __IO  uint8_t AN26       : 1;
+  __IO  uint8_t AN27       : 1;
+  __IO  uint8_t AN28       : 1;
+  __IO  uint8_t AN29       : 1;
+  __IO  uint8_t AN30       : 1;
+  __IO  uint8_t AN31       : 1;
+} stc_adc_scis3_field_t;
+
+typedef struct stc_adc_scis01_field
+{
+  __IO uint16_t AN0        : 1;
+  __IO uint16_t AN1        : 1;
+  __IO uint16_t AN2        : 1;
+  __IO uint16_t AN3        : 1;
+  __IO uint16_t AN4        : 1;
+  __IO uint16_t AN5        : 1;
+  __IO uint16_t AN6        : 1;
+  __IO uint16_t AN7        : 1;
+  __IO uint16_t AN8        : 1;
+  __IO uint16_t AN9        : 1;
+  __IO uint16_t AN10       : 1;
+  __IO uint16_t AN11       : 1;
+  __IO uint16_t AN12       : 1;
+  __IO uint16_t AN13       : 1;
+  __IO uint16_t AN14       : 1;
+  __IO uint16_t AN15       : 1;
+} stc_adc_scis01_field_t;
+
+typedef struct stc_adc_scis0_field
+{
+  __IO  uint8_t AN0        : 1;
+  __IO  uint8_t AN1        : 1;
+  __IO  uint8_t AN2        : 1;
+  __IO  uint8_t AN3        : 1;
+  __IO  uint8_t AN4        : 1;
+  __IO  uint8_t AN5        : 1;
+  __IO  uint8_t AN6        : 1;
+  __IO  uint8_t AN7        : 1;
+} stc_adc_scis0_field_t;
+
+typedef struct stc_adc_scis1_field
+{
+  __IO  uint8_t AN8        : 1;
+  __IO  uint8_t AN9        : 1;
+  __IO  uint8_t AN10       : 1;
+  __IO  uint8_t AN11       : 1;
+  __IO  uint8_t AN12       : 1;
+  __IO  uint8_t AN13       : 1;
+  __IO  uint8_t AN14       : 1;
+  __IO  uint8_t AN15       : 1;
+} stc_adc_scis1_field_t;
+
+typedef struct stc_adc_pfns_field
+{
+  __IO  uint8_t PFS0       : 1;
+  __IO  uint8_t PFS1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TEST0      : 1;
+  __IO  uint8_t TEST1      : 1;
+} stc_adc_pfns_field_t;
+
+typedef struct stc_adc_pccr_field
+{
+  __IO  uint8_t PSTR       : 1;
+  __IO  uint8_t PHEN       : 1;
+  __IO  uint8_t PEEN       : 1;
+  __IO  uint8_t ESCE       : 1;
+  __IO  uint8_t PFCLR      : 1;
+  __IO  uint8_t POVR       : 1;
+  __IO  uint8_t PFUL       : 1;
+  __IO  uint8_t PEMP       : 1;
+} stc_adc_pccr_field_t;
+
+typedef struct stc_adc_pcfd_field
+{
+  __IO uint32_t PC0        : 1;
+  __IO uint32_t PC1        : 1;
+  __IO uint32_t PC2        : 1;
+  __IO uint32_t PC3        : 1;
+  __IO uint32_t PC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t PD0        : 1;
+  __IO uint32_t PD1        : 1;
+  __IO uint32_t PD2        : 1;
+  __IO uint32_t PD3        : 1;
+  __IO uint32_t PD4        : 1;
+  __IO uint32_t PD5        : 1;
+  __IO uint32_t PD6        : 1;
+  __IO uint32_t PD7        : 1;
+  __IO uint32_t PD8        : 1;
+  __IO uint32_t PD9        : 1;
+  __IO uint32_t PD10       : 1;
+  __IO uint32_t PD11       : 1;
+} stc_adc_pcfd_field_t;
+
+typedef struct stc_adc_pcfdl_field
+{
+  __IO uint16_t PC0        : 1;
+  __IO uint16_t PC1        : 1;
+  __IO uint16_t PC2        : 1;
+  __IO uint16_t PC3        : 1;
+  __IO uint16_t PC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+  __IO uint16_t RS2        : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t INVL       : 1;
+} stc_adc_pcfdl_field_t;
+
+typedef struct stc_adc_pcfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t PD0        : 1;
+  __IO uint16_t PD1        : 1;
+  __IO uint16_t PD2        : 1;
+  __IO uint16_t PD3        : 1;
+  __IO uint16_t PD4        : 1;
+  __IO uint16_t PD5        : 1;
+  __IO uint16_t PD6        : 1;
+  __IO uint16_t PD7        : 1;
+  __IO uint16_t PD8        : 1;
+  __IO uint16_t PD9        : 1;
+  __IO uint16_t PD10       : 1;
+  __IO uint16_t PD11       : 1;
+} stc_adc_pcfdh_field_t;
+
+typedef struct stc_adc_pcis_field
+{
+  __IO  uint8_t P1A0       : 1;
+  __IO  uint8_t P1A1       : 1;
+  __IO  uint8_t P1A2       : 1;
+  __IO  uint8_t P2A0       : 1;
+  __IO  uint8_t P2A1       : 1;
+  __IO  uint8_t P2A2       : 1;
+  __IO  uint8_t P2A3       : 1;
+  __IO  uint8_t P2A4       : 1;
+} stc_adc_pcis_field_t;
+
+typedef struct stc_adc_cmpcr_field
+{
+  __IO  uint8_t CCH0       : 1;
+  __IO  uint8_t CCH1       : 1;
+  __IO  uint8_t CCH2       : 1;
+  __IO  uint8_t CCH3       : 1;
+  __IO  uint8_t CCH4       : 1;
+  __IO  uint8_t CMD0       : 1;
+  __IO  uint8_t CMD1       : 1;
+  __IO  uint8_t CMPEN      : 1;
+} stc_adc_cmpcr_field_t;
+
+typedef struct stc_adc_cmpd_field
+{
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t CMAD2      : 1;
+  __IO uint16_t CMAD3      : 1;
+  __IO uint16_t CMAD4      : 1;
+  __IO uint16_t CMAD5      : 1;
+  __IO uint16_t CMAD6      : 1;
+  __IO uint16_t CMAD7      : 1;
+  __IO uint16_t CMAD8      : 1;
+  __IO uint16_t CMAD9      : 1;
+  __IO uint16_t CMAD10     : 1;
+  __IO uint16_t CMAD11     : 1;
+} stc_adc_cmpd_field_t;
+
+typedef struct stc_adc_adss23_field
+{
+  __IO uint16_t TS16       : 1;
+  __IO uint16_t TS17       : 1;
+  __IO uint16_t TS18       : 1;
+  __IO uint16_t TS19       : 1;
+  __IO uint16_t TS20       : 1;
+  __IO uint16_t TS21       : 1;
+  __IO uint16_t TS22       : 1;
+  __IO uint16_t TS23       : 1;
+  __IO uint16_t TS24       : 1;
+  __IO uint16_t TS25       : 1;
+  __IO uint16_t TS26       : 1;
+  __IO uint16_t TS27       : 1;
+  __IO uint16_t TS28       : 1;
+  __IO uint16_t TS29       : 1;
+  __IO uint16_t TS30       : 1;
+  __IO uint16_t TS31       : 1;
+} stc_adc_adss23_field_t;
+
+typedef struct stc_adc_adss2_field
+{
+  __IO  uint8_t TS16       : 1;
+  __IO  uint8_t TS17       : 1;
+  __IO  uint8_t TS18       : 1;
+  __IO  uint8_t TS19       : 1;
+  __IO  uint8_t TS20       : 1;
+  __IO  uint8_t TS21       : 1;
+  __IO  uint8_t TS22       : 1;
+  __IO  uint8_t TS23       : 1;
+} stc_adc_adss2_field_t;
+
+typedef struct stc_adc_adss3_field
+{
+  __IO  uint8_t TS24       : 1;
+  __IO  uint8_t TS25       : 1;
+  __IO  uint8_t TS26       : 1;
+  __IO  uint8_t TS27       : 1;
+  __IO  uint8_t TS28       : 1;
+  __IO  uint8_t TS29       : 1;
+  __IO  uint8_t TS30       : 1;
+  __IO  uint8_t TS31       : 1;
+} stc_adc_adss3_field_t;
+
+typedef struct stc_adc_adss01_field
+{
+  __IO uint16_t TS0        : 1;
+  __IO uint16_t TS1        : 1;
+  __IO uint16_t TS2        : 1;
+  __IO uint16_t TS3        : 1;
+  __IO uint16_t TS4        : 1;
+  __IO uint16_t TS5        : 1;
+  __IO uint16_t TS6        : 1;
+  __IO uint16_t TS7        : 1;
+  __IO uint16_t TS8        : 1;
+  __IO uint16_t TS9        : 1;
+  __IO uint16_t TS10       : 1;
+  __IO uint16_t TS11       : 1;
+  __IO uint16_t TS12       : 1;
+  __IO uint16_t TS13       : 1;
+  __IO uint16_t TS14       : 1;
+  __IO uint16_t TS15       : 1;
+} stc_adc_adss01_field_t;
+
+typedef struct stc_adc_adss0_field
+{
+  __IO  uint8_t TS0        : 1;
+  __IO  uint8_t TS1        : 1;
+  __IO  uint8_t TS2        : 1;
+  __IO  uint8_t TS3        : 1;
+  __IO  uint8_t TS4        : 1;
+  __IO  uint8_t TS5        : 1;
+  __IO  uint8_t TS6        : 1;
+  __IO  uint8_t TS7        : 1;
+} stc_adc_adss0_field_t;
+
+typedef struct stc_adc_adss1_field
+{
+  __IO  uint8_t TS8        : 1;
+  __IO  uint8_t TS9        : 1;
+  __IO  uint8_t TS10       : 1;
+  __IO  uint8_t TS11       : 1;
+  __IO  uint8_t TS12       : 1;
+  __IO  uint8_t TS13       : 1;
+  __IO  uint8_t TS14       : 1;
+  __IO  uint8_t TS15       : 1;
+} stc_adc_adss1_field_t;
+
+typedef struct stc_adc_adst01_field
+{
+  __IO uint16_t ST10       : 1;
+  __IO uint16_t ST11       : 1;
+  __IO uint16_t ST12       : 1;
+  __IO uint16_t ST13       : 1;
+  __IO uint16_t ST14       : 1;
+  __IO uint16_t STX10      : 1;
+  __IO uint16_t STX11      : 1;
+  __IO uint16_t STX12      : 1;
+  __IO uint16_t ST00       : 1;
+  __IO uint16_t ST01       : 1;
+  __IO uint16_t ST02       : 1;
+  __IO uint16_t ST03       : 1;
+  __IO uint16_t ST04       : 1;
+  __IO uint16_t STX00      : 1;
+  __IO uint16_t STX01      : 1;
+  __IO uint16_t STX02      : 1;
+} stc_adc_adst01_field_t;
+
+typedef struct stc_adc_adst1_field
+{
+  __IO  uint8_t ST10       : 1;
+  __IO  uint8_t ST11       : 1;
+  __IO  uint8_t ST12       : 1;
+  __IO  uint8_t ST13       : 1;
+  __IO  uint8_t ST14       : 1;
+  __IO  uint8_t STX10      : 1;
+  __IO  uint8_t STX11      : 1;
+  __IO  uint8_t STX12      : 1;
+} stc_adc_adst1_field_t;
+
+typedef struct stc_adc_adst0_field
+{
+  __IO  uint8_t ST00       : 1;
+  __IO  uint8_t ST01       : 1;
+  __IO  uint8_t ST02       : 1;
+  __IO  uint8_t ST03       : 1;
+  __IO  uint8_t ST04       : 1;
+  __IO  uint8_t STX00      : 1;
+  __IO  uint8_t STX01      : 1;
+  __IO  uint8_t STX02      : 1;
+} stc_adc_adst0_field_t;
+
+typedef struct stc_adc_adct_field
+{
+  __IO  uint8_t CT0        : 1;
+  __IO  uint8_t CT1        : 1;
+  __IO  uint8_t CT2        : 1;
+  __IO  uint8_t CT3        : 1;
+  __IO  uint8_t CT4        : 1;
+  __IO  uint8_t CT5        : 1;
+  __IO  uint8_t CT6        : 1;
+  __IO  uint8_t CT7        : 1;
+} stc_adc_adct_field_t;
+
+typedef struct stc_adc_prtsl_field
+{
+  __IO  uint8_t PRTSL0     : 1;
+  __IO  uint8_t PRTSL1     : 1;
+  __IO  uint8_t PRTSL2     : 1;
+  __IO  uint8_t PRTSL3     : 1;
+} stc_adc_prtsl_field_t;
+
+typedef struct stc_adc_sctsl_field
+{
+  __IO  uint8_t SCTSL0     : 1;
+  __IO  uint8_t SCTSL1     : 1;
+  __IO  uint8_t SCTSL2     : 1;
+  __IO  uint8_t SCTSL3     : 1;
+} stc_adc_sctsl_field_t;
+
+typedef struct stc_adc_adcen_field
+{
+  __IO  uint8_t ENBL       : 1;
+  __IO  uint8_t READY      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CYCLSL0    : 1;
+  __IO  uint8_t CYCLSL1    : 1;
+} stc_adc_adcen_field_t;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CRTRIM_MODULE register bit fields */
+typedef struct stc_crtrim_mcr_psr_field
+{
+  __IO  uint8_t CSR0       : 1;
+  __IO  uint8_t CSR1       : 1;
+} stc_crtrim_mcr_psr_field_t;
+
+typedef struct stc_crtrim_mcr_ftrm_field
+{
+  __IO uint16_t TRD0       : 1;
+  __IO uint16_t TRD1       : 1;
+  __IO uint16_t TRD2       : 1;
+  __IO uint16_t TRD3       : 1;
+  __IO uint16_t TRD4       : 1;
+  __IO uint16_t TRD5       : 1;
+  __IO uint16_t TRD6       : 1;
+  __IO uint16_t TRD7       : 1;
+} stc_crtrim_mcr_ftrm_field_t;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* EXTI_MODULE registEN bit fields */
+typedef struct stc_exti_enir_field
+{
+  __IO uint16_t EN0        : 1;
+  __IO uint16_t EN1        : 1;
+  __IO uint16_t EN2        : 1;
+  __IO uint16_t EN3        : 1;
+  __IO uint16_t EN4        : 1;
+  __IO uint16_t EN5        : 1;
+  __IO uint16_t EN6        : 1;
+  __IO uint16_t EN7        : 1;
+  __IO uint16_t EN8        : 1;
+  __IO uint16_t EN9        : 1;
+  __IO uint16_t EN10       : 1;
+  __IO uint16_t EN11       : 1;
+  __IO uint16_t EN12       : 1;
+  __IO uint16_t EN13       : 1;
+  __IO uint16_t EN14       : 1;
+  __IO uint16_t EN15       : 1;
+  __IO uint16_t EN16       : 1;
+  __IO uint16_t EN17       : 1;
+  __IO uint16_t EN18       : 1;
+  __IO uint16_t EN19       : 1;
+  __IO uint16_t EN20       : 1;
+  __IO uint16_t EN21       : 1;
+  __IO uint16_t EN22       : 1;
+  __IO uint16_t EN23       : 1;
+  __IO uint16_t EN24       : 1;
+  __IO uint16_t EN25       : 1;
+  __IO uint16_t EN26       : 1;
+  __IO uint16_t EN27       : 1;
+  __IO uint16_t EN28       : 1;
+  __IO uint16_t EN29       : 1;
+  __IO uint16_t EN30       : 1;
+  __IO uint16_t EN31       : 1;
+} stc_exti_enir_field_t;
+
+typedef struct stc_exti_eirr_field
+{
+  __IO uint16_t ER0        : 1;
+  __IO uint16_t ER1        : 1;
+  __IO uint16_t ER2        : 1;
+  __IO uint16_t ER3        : 1;
+  __IO uint16_t ER4        : 1;
+  __IO uint16_t ER5        : 1;
+  __IO uint16_t ER6        : 1;
+  __IO uint16_t ER7        : 1;
+  __IO uint16_t ER8        : 1;
+  __IO uint16_t ER9        : 1;
+  __IO uint16_t ER10       : 1;
+  __IO uint16_t ER11       : 1;
+  __IO uint16_t ER12       : 1;
+  __IO uint16_t ER13       : 1;
+  __IO uint16_t ER14       : 1;
+  __IO uint16_t ER15       : 1;
+  __IO uint16_t ER16       : 1;
+  __IO uint16_t ER17       : 1;
+  __IO uint16_t ER18       : 1;
+  __IO uint16_t ER19       : 1;
+  __IO uint16_t ER20       : 1;
+  __IO uint16_t ER21       : 1;
+  __IO uint16_t ER22       : 1;
+  __IO uint16_t ER23       : 1;
+  __IO uint16_t ER24       : 1;
+  __IO uint16_t ER25       : 1;
+  __IO uint16_t ER26       : 1;
+  __IO uint16_t ER27       : 1;
+  __IO uint16_t ER28       : 1;
+  __IO uint16_t ER29       : 1;
+  __IO uint16_t ER30       : 1;
+  __IO uint16_t ER31       : 1;
+} stc_exti_eirr_field_t;
+
+typedef struct stc_exti_eicl_field
+{
+  __IO uint16_t ECL0       : 1;
+  __IO uint16_t ECL1       : 1;
+  __IO uint16_t ECL2       : 1;
+  __IO uint16_t ECL3       : 1;
+  __IO uint16_t ECL4       : 1;
+  __IO uint16_t ECL5       : 1;
+  __IO uint16_t ECL6       : 1;
+  __IO uint16_t ECL7       : 1;
+  __IO uint16_t ECL8       : 1;
+  __IO uint16_t ECL9       : 1;
+  __IO uint16_t ECL10      : 1;
+  __IO uint16_t ECL11      : 1;
+  __IO uint16_t ECL12      : 1;
+  __IO uint16_t ECL13      : 1;
+  __IO uint16_t ECL14      : 1;
+  __IO uint16_t ECL15      : 1;
+  __IO uint16_t ECL16      : 1;
+  __IO uint16_t ECL17      : 1;
+  __IO uint16_t ECL18      : 1;
+  __IO uint16_t ECL19      : 1;
+  __IO uint16_t ECL20      : 1;
+  __IO uint16_t ECL21      : 1;
+  __IO uint16_t ECL22      : 1;
+  __IO uint16_t ECL23      : 1;
+  __IO uint16_t ECL24      : 1;
+  __IO uint16_t ECL25      : 1;
+  __IO uint16_t ECL26      : 1;
+  __IO uint16_t ECL27      : 1;
+  __IO uint16_t ECL28      : 1;
+  __IO uint16_t ECL29      : 1;
+  __IO uint16_t ECL30      : 1;
+  __IO uint16_t ECL31      : 1;
+} stc_exti_eicl_field_t;
+
+typedef struct stc_exti_elvr_field
+{
+  __IO uint32_t LA0        : 1;
+  __IO uint32_t LB0        : 1;
+  __IO uint32_t LA1        : 1;
+  __IO uint32_t LB1        : 1;
+  __IO uint32_t LA2        : 1;
+  __IO uint32_t LB2        : 1;
+  __IO uint32_t LA3        : 1;
+  __IO uint32_t LB3        : 1;
+  __IO uint32_t LA4        : 1;
+  __IO uint32_t LB4        : 1;
+  __IO uint32_t LA5        : 1;
+  __IO uint32_t LB5        : 1;
+  __IO uint32_t LA6        : 1;
+  __IO uint32_t LB6        : 1;
+  __IO uint32_t LA7        : 1;
+  __IO uint32_t LB7        : 1;
+  __IO uint32_t LA8        : 1;
+  __IO uint32_t LB8        : 1;
+  __IO uint32_t LA9        : 1;
+  __IO uint32_t LB9        : 1;
+  __IO uint32_t LA10       : 1;
+  __IO uint32_t LB10       : 1;
+  __IO uint32_t LA11       : 1;
+  __IO uint32_t LB11       : 1;
+  __IO uint32_t LA12       : 1;
+  __IO uint32_t LB12       : 1;
+  __IO uint32_t LA13       : 1;
+  __IO uint32_t LB13       : 1;
+  __IO uint32_t LA14       : 1;
+  __IO uint32_t LB14       : 1;
+  __IO uint32_t LA15       : 1;
+  __IO uint32_t LB15       : 1;
+} stc_exti_elvr_field_t;
+
+typedef struct stc_exti_elvr1_field
+{
+  __IO uint32_t LA16       : 1;
+  __IO uint32_t LB16       : 1;
+  __IO uint32_t LA17       : 1;
+  __IO uint32_t LB17       : 1;
+  __IO uint32_t LA18       : 1;
+  __IO uint32_t LB18       : 1;
+  __IO uint32_t LA19       : 1;
+  __IO uint32_t LB19       : 1;
+  __IO uint32_t LA20       : 1;
+  __IO uint32_t LB20       : 1;
+  __IO uint32_t LA21       : 1;
+  __IO uint32_t LB21       : 1;
+  __IO uint32_t LA22       : 1;
+  __IO uint32_t LB22       : 1;
+  __IO uint32_t LA23       : 1;
+  __IO uint32_t LB23       : 1;
+  __IO uint32_t LA24       : 1;
+  __IO uint32_t LB24       : 1;
+  __IO uint32_t LA25       : 1;
+  __IO uint32_t LB25       : 1;
+  __IO uint32_t LA26       : 1;
+  __IO uint32_t LB26       : 1;
+  __IO uint32_t LA27       : 1;
+  __IO uint32_t LB27       : 1;
+  __IO uint32_t LA28       : 1;
+  __IO uint32_t LB28       : 1;
+  __IO uint32_t LA29       : 1;
+  __IO uint32_t LB29       : 1;
+  __IO uint32_t LA30       : 1;
+  __IO uint32_t LB30       : 1;
+  __IO uint32_t LA31       : 1;
+  __IO uint32_t LB31       : 1;
+} stc_exti_elvr1_field_t;
+
+typedef struct stc_exti_nmirr_field
+{
+  __IO  uint8_t NR0        : 1;
+} stc_exti_nmirr_field_t;
+
+typedef struct stc_exti_nmicl_field
+{
+  __IO  uint8_t NCL0       : 1;
+} stc_exti_nmicl_field_t;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* INTREQ_MODULE register bit fields */
+typedef struct stc_intreq_drqsel_field
+{
+  __IO uint32_t DRQSEL0    : 1;
+  __IO uint32_t DRQSEL1    : 1;
+  __IO uint32_t DRQSEL2    : 1;
+  __IO uint32_t DRQSEL3    : 1;
+  __IO uint32_t DRQSEL4    : 1;
+  __IO uint32_t DRQSEL5    : 1;
+  __IO uint32_t DRQSEL6    : 1;
+  __IO uint32_t DRQSEL7    : 1;
+  __IO uint32_t DRQSEL8    : 1;
+  __IO uint32_t DRQSEL9    : 1;
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+  __IO uint32_t DRQSEL15   : 1;
+  __IO uint32_t DRQSEL16   : 1;
+  __IO uint32_t DRQSEL17   : 1;
+  __IO uint32_t DRQSEL18   : 1;
+  __IO uint32_t DRQSEL19   : 1;
+  __IO uint32_t DRQSEL20   : 1;
+  __IO uint32_t DRQSEL21   : 1;
+  __IO uint32_t DRQSEL22   : 1;
+  __IO uint32_t DRQSEL23   : 1;
+  __IO uint32_t DRQSEL24   : 1;
+  __IO uint32_t DRQSEL25   : 1;
+  __IO uint32_t DRQSEL26   : 1;
+  __IO uint32_t DRQSEL27   : 1;
+  __IO uint32_t DRQSEL28   : 1;
+  __IO uint32_t DRQSEL29   : 1;
+  __IO uint32_t DRQSEL30   : 1;
+  __IO uint32_t DRQSEL31   : 1;
+} stc_intreq_drqsel_field_t;
+
+typedef struct stc_intreq_oddpks_field
+{
+  __IO  uint8_t ODDPKS0    : 1;
+  __IO  uint8_t ODDPKS1    : 1;
+  __IO  uint8_t ODDPKS2    : 1;
+  __IO  uint8_t ODDPKS3    : 1;
+  __IO  uint8_t ODDPKS4    : 1;
+} stc_intreq_oddpks_field_t;
+
+typedef struct stc_intreq_exc02mon_field
+{
+  __IO uint32_t NMI        : 1;
+  __IO uint32_t HWINT      : 1;
+} stc_intreq_exc02mon_field_t;
+
+typedef struct stc_intreq_irq00mon_field
+{
+  __IO uint32_t FCSINT     : 1;
+} stc_intreq_irq00mon_field_t;
+
+typedef struct stc_intreq_irq01mon_field
+{
+  __IO uint32_t SWWDTINT   : 1;
+} stc_intreq_irq01mon_field_t;
+
+typedef struct stc_intreq_irq02mon_field
+{
+  __IO uint32_t LVDINT     : 1;
+} stc_intreq_irq02mon_field_t;
+
+typedef struct stc_intreq_irq03mon_field
+{
+  __IO uint32_t WAVE0INT0  : 1;
+  __IO uint32_t WAVE0INT1  : 1;
+  __IO uint32_t WAVE0INT2  : 1;
+  __IO uint32_t WAVE0INT3  : 1;
+  __IO uint32_t WAVE1INT0  : 1;
+  __IO uint32_t WAVE1INT1  : 1;
+  __IO uint32_t WAVE1INT2  : 1;
+  __IO uint32_t WAVE1INT3  : 1;
+  __IO uint32_t WAVE2INT0  : 1;
+  __IO uint32_t WAVE2INT1  : 1;
+  __IO uint32_t WAVE2INT2  : 1;
+  __IO uint32_t WAVE2INT3  : 1;
+} stc_intreq_irq03mon_field_t;
+
+typedef struct stc_intreq_irq04mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+} stc_intreq_irq04mon_field_t;
+
+typedef struct stc_intreq_irq05mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+  __IO uint32_t EXTINT8    : 1;
+  __IO uint32_t EXTINT9    : 1;
+  __IO uint32_t EXTINT10   : 1;
+  __IO uint32_t EXTINT11   : 1;
+  __IO uint32_t EXTINT12   : 1;
+  __IO uint32_t EXTINT13   : 1;
+  __IO uint32_t EXTINT14   : 1;
+  __IO uint32_t EXTINT15   : 1;
+  __IO uint32_t EXTINT16   : 1;
+  __IO uint32_t EXTINT17   : 1;
+  __IO uint32_t EXTINT18   : 1;
+  __IO uint32_t EXTINT19   : 1;
+  __IO uint32_t EXTINT20   : 1;
+  __IO uint32_t EXTINT21   : 1;
+  __IO uint32_t EXTINT22   : 1;
+  __IO uint32_t EXTINT23   : 1;
+} stc_intreq_irq05mon_field_t;
+
+typedef struct stc_intreq_irq06mon_field
+{
+  __IO uint32_t TIMINT1    : 1;
+  __IO uint32_t TIMINT2    : 1;
+  __IO uint32_t QUD0INT0   : 1;
+  __IO uint32_t QUD0INT1   : 1;
+  __IO uint32_t QUD0INT2   : 1;
+  __IO uint32_t QUD0INT3   : 1;
+  __IO uint32_t QUD0INT4   : 1;
+  __IO uint32_t QUD0INT5   : 1;
+  __IO uint32_t QUD1INT0   : 1;
+  __IO uint32_t QUD1INT1   : 1;
+  __IO uint32_t QUD1INT2   : 1;
+  __IO uint32_t QUD1INT3   : 1;
+  __IO uint32_t QUD1INT4   : 1;
+  __IO uint32_t QUD1INT5   : 1;
+  __IO uint32_t QUD2INT0   : 1;
+  __IO uint32_t QUD2INT1   : 1;
+  __IO uint32_t QUD2INT2   : 1;
+  __IO uint32_t QUD2INT3   : 1;
+  __IO uint32_t QUD2INT4   : 1;
+  __IO uint32_t QUD2INT5   : 1;
+} stc_intreq_irq06mon_field_t;
+
+typedef struct stc_intreq_irq07mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq07mon_field_t;
+
+typedef struct stc_intreq_irq08mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq08mon_field_t;
+
+typedef struct stc_intreq_irq09mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq09mon_field_t;
+
+typedef struct stc_intreq_irq10mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq10mon_field_t;
+
+typedef struct stc_intreq_irq11mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq11mon_field_t;
+
+typedef struct stc_intreq_irq12mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq12mon_field_t;
+
+typedef struct stc_intreq_irq13mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq13mon_field_t;
+
+typedef struct stc_intreq_irq14mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq14mon_field_t;
+
+typedef struct stc_intreq_irq15mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq15mon_field_t;
+
+typedef struct stc_intreq_irq16mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq16mon_field_t;
+
+typedef struct stc_intreq_irq17mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq17mon_field_t;
+
+typedef struct stc_intreq_irq18mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq18mon_field_t;
+
+typedef struct stc_intreq_irq19mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq19mon_field_t;
+
+typedef struct stc_intreq_irq20mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq20mon_field_t;
+
+typedef struct stc_intreq_irq21mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq21mon_field_t;
+
+typedef struct stc_intreq_irq22mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq22mon_field_t;
+
+typedef struct stc_intreq_irq23mon_field
+{
+  __IO uint32_t PPGINT0    : 1;
+  __IO uint32_t PPGINT1    : 1;
+  __IO uint32_t PPGINT2    : 1;
+  __IO uint32_t PPGINT3    : 1;
+  __IO uint32_t PPGINT4    : 1;
+  __IO uint32_t PPGINT5    : 1;
+  __IO uint32_t PPGINT6    : 1;
+  __IO uint32_t PPGINT7    : 1;
+  __IO uint32_t PPGINT8    : 1;
+} stc_intreq_irq23mon_field_t;
+
+typedef struct stc_intreq_irq24mon_field
+{
+  __IO uint32_t MOSCINT    : 1;
+  __IO uint32_t SOSCINT    : 1;
+  __IO uint32_t MPLLINT    : 1;
+  __IO uint32_t UPLLINT    : 1;
+  __IO uint32_t WCINT      : 1;
+} stc_intreq_irq24mon_field_t;
+
+typedef struct stc_intreq_irq25mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq25mon_field_t;
+
+typedef struct stc_intreq_irq26mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq26mon_field_t;
+
+typedef struct stc_intreq_irq27mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq27mon_field_t;
+
+typedef struct stc_intreq_irq28mon_field
+{
+  __IO uint32_t FRT0INT0   : 1;
+  __IO uint32_t FRT0INT1   : 1;
+  __IO uint32_t FRT0INT2   : 1;
+  __IO uint32_t FRT0INT3   : 1;
+  __IO uint32_t FRT0INT4   : 1;
+  __IO uint32_t FRT0INT5   : 1;
+  __IO uint32_t FRT1INT0   : 1;
+  __IO uint32_t FRT1INT1   : 1;
+  __IO uint32_t FRT1INT2   : 1;
+  __IO uint32_t FRT1INT3   : 1;
+  __IO uint32_t FRT1INT4   : 1;
+  __IO uint32_t FRT1INT5   : 1;
+  __IO uint32_t FRT2INT0   : 1;
+  __IO uint32_t FRT2INT1   : 1;
+  __IO uint32_t FRT2INT2   : 1;
+  __IO uint32_t FRT2INT3   : 1;
+  __IO uint32_t FRT2INT4   : 1;
+  __IO uint32_t FRT2INT5   : 1;
+} stc_intreq_irq28mon_field_t;
+
+typedef struct stc_intreq_irq29mon_field
+{
+  __IO uint32_t ICU0INT0   : 1;
+  __IO uint32_t ICU0INT1   : 1;
+  __IO uint32_t ICU0INT2   : 1;
+  __IO uint32_t ICU0INT3   : 1;
+  __IO uint32_t ICU1INT0   : 1;
+  __IO uint32_t ICU1INT1   : 1;
+  __IO uint32_t ICU1INT2   : 1;
+  __IO uint32_t ICU1INT3   : 1;
+  __IO uint32_t ICU2INT0   : 1;
+  __IO uint32_t ICU2INT1   : 1;
+  __IO uint32_t ICU2INT2   : 1;
+  __IO uint32_t ICU2INT3   : 1;
+} stc_intreq_irq29mon_field_t;
+
+typedef struct stc_intreq_irq30mon_field
+{
+  __IO uint32_t OCU0INT0   : 1;
+  __IO uint32_t OCU0INT1   : 1;
+  __IO uint32_t OCU0INT2   : 1;
+  __IO uint32_t OCU0INT3   : 1;
+  __IO uint32_t OCU0INT4   : 1;
+  __IO uint32_t OCU0INT5   : 1;
+  __IO uint32_t OCU1INT0   : 1;
+  __IO uint32_t OCU1INT1   : 1;
+  __IO uint32_t OCU1INT2   : 1;
+  __IO uint32_t OCU1INT3   : 1;
+  __IO uint32_t OCU1INT4   : 1;
+  __IO uint32_t OCU1INT5   : 1;
+  __IO uint32_t OCU2INT0   : 1;
+  __IO uint32_t OCU2INT1   : 1;
+  __IO uint32_t OCU2INT2   : 1;
+  __IO uint32_t OCU2INT3   : 1;
+  __IO uint32_t OCU2INT4   : 1;
+  __IO uint32_t OCU2INT5   : 1;
+} stc_intreq_irq30mon_field_t;
+
+typedef struct stc_intreq_irq31mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq31mon_field_t;
+
+typedef struct stc_intreq_irq32mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC0SBD    : 1;
+  __IO uint32_t MAC0PMI    : 1;
+  __IO uint32_t MAC0LPI    : 1;
+} stc_intreq_irq32mon_field_t;
+
+typedef struct stc_intreq_irq33mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC1SBD    : 1;
+  __IO uint32_t MAC1PMI    : 1;
+} stc_intreq_irq33mon_field_t;
+
+typedef struct stc_intreq_irq34mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+} stc_intreq_irq34mon_field_t;
+
+typedef struct stc_intreq_irq35mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+  __IO uint32_t USB0INT5   : 1;
+} stc_intreq_irq35mon_field_t;
+
+typedef struct stc_intreq_irq36mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+} stc_intreq_irq36mon_field_t;
+
+typedef struct stc_intreq_irq37mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+  __IO uint32_t USB1INT5   : 1;
+} stc_intreq_irq37mon_field_t;
+
+typedef struct stc_intreq_irq38mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq38mon_field_t;
+
+typedef struct stc_intreq_irq39mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq39mon_field_t;
+
+typedef struct stc_intreq_irq40mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq40mon_field_t;
+
+typedef struct stc_intreq_irq41mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq41mon_field_t;
+
+typedef struct stc_intreq_irq42mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq42mon_field_t;
+
+typedef struct stc_intreq_irq43mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq43mon_field_t;
+
+typedef struct stc_intreq_irq44mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq44mon_field_t;
+
+typedef struct stc_intreq_irq45mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq45mon_field_t;
+
+typedef struct stc_intreq_irq46mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq46mon_field_t;
+
+typedef struct stc_intreq_drqsel1_field
+{
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+} stc_intreq_drqsel1_field_t;
+
+typedef struct stc_intreq_dqesel_field
+{
+  __IO uint32_t ESEL100    : 1;
+  __IO uint32_t ESEL101    : 1;
+  __IO uint32_t ESEL102    : 1;
+  __IO uint32_t ESEL103    : 1;
+  __IO uint32_t ESEL110    : 1;
+  __IO uint32_t ESEL111    : 1;
+  __IO uint32_t ESEL112    : 1;
+  __IO uint32_t ESEL113    : 1;
+  __IO uint32_t ESEL240    : 1;
+  __IO uint32_t ESEL241    : 1;
+  __IO uint32_t ESEL242    : 1;
+  __IO uint32_t ESEL243    : 1;
+  __IO uint32_t ESEL250    : 1;
+  __IO uint32_t ESEL251    : 1;
+  __IO uint32_t ESEL252    : 1;
+  __IO uint32_t ESEL253    : 1;
+  __IO uint32_t ESEL260    : 1;
+  __IO uint32_t ESEL261    : 1;
+  __IO uint32_t ESEL262    : 1;
+  __IO uint32_t ESEL263    : 1;
+  __IO uint32_t ESEL270    : 1;
+  __IO uint32_t ESEL271    : 1;
+  __IO uint32_t ESEL272    : 1;
+  __IO uint32_t ESEL273    : 1;
+  __IO uint32_t ESEL300    : 1;
+  __IO uint32_t ESEL301    : 1;
+  __IO uint32_t ESEL302    : 1;
+  __IO uint32_t ESEL303    : 1;
+  __IO uint32_t ESEL310    : 1;
+  __IO uint32_t ESEL311    : 1;
+  __IO uint32_t ESEL312    : 1;
+  __IO uint32_t ESEL313    : 1;
+} stc_intreq_dqesel_field_t;
+
+typedef struct stc_intreq_oddpks1_field
+{
+  __IO  uint8_t ODDPKS10   : 1;
+  __IO  uint8_t ODDPKS11   : 1;
+  __IO  uint8_t ODDPKS12   : 1;
+  __IO  uint8_t ODDPKS13   : 1;
+  __IO  uint8_t ODDPKS14   : 1;
+} stc_intreq_oddpks1_field_t;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* GPIO_MODULE register bit fields */
+typedef struct stc_gpio_pfr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr0_field_t;
+
+typedef struct stc_gpio_pfr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr1_field_t;
+
+typedef struct stc_gpio_pfr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr2_field_t;
+
+typedef struct stc_gpio_pfr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr3_field_t;
+
+typedef struct stc_gpio_pfr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pfr4_field_t;
+
+typedef struct stc_gpio_pfr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pfr5_field_t;
+
+typedef struct stc_gpio_pfr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pfr6_field_t;
+
+typedef struct stc_gpio_pfr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pfr7_field_t;
+
+typedef struct stc_gpio_pfr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfr8_field_t;
+
+
+typedef struct stc_gpio_pfra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pfra_field_t;
+
+typedef struct stc_gpio_pfrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfrc_field_t;
+
+typedef struct stc_gpio_pfrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfrd_field_t;
+
+typedef struct stc_gpio_pfre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfre_field_t;
+
+typedef struct stc_gpio_pfrf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pfrf_field_t;
+
+typedef struct stc_gpio_pcr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr0_field_t;
+
+typedef struct stc_gpio_pcr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr1_field_t;
+
+typedef struct stc_gpio_pcr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr2_field_t;
+
+typedef struct stc_gpio_pcr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr3_field_t;
+
+typedef struct stc_gpio_pcr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pcr4_field_t;
+
+typedef struct stc_gpio_pcr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pcr5_field_t;
+
+typedef struct stc_gpio_pcr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pcr6_field_t;
+
+typedef struct stc_gpio_pcr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pcr7_field_t;
+
+typedef struct stc_gpio_pcra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pcra_field_t;
+
+typedef struct stc_gpio_pcrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcrc_field_t;
+
+typedef struct stc_gpio_pcrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcrd_field_t;
+
+typedef struct stc_gpio_pcre_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcre_field_t;
+
+typedef struct stc_gpio_ddr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr0_field_t;
+
+typedef struct stc_gpio_ddr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr1_field_t;
+
+typedef struct stc_gpio_ddr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr2_field_t;
+
+typedef struct stc_gpio_ddr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr3_field_t;
+
+typedef struct stc_gpio_ddr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_ddr4_field_t;
+
+typedef struct stc_gpio_ddr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_ddr5_field_t;
+
+typedef struct stc_gpio_ddr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_ddr6_field_t;
+
+typedef struct stc_gpio_ddr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_ddr7_field_t;
+
+typedef struct stc_gpio_ddr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddr8_field_t;
+
+typedef struct stc_gpio_ddra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_ddra_field_t;
+
+typedef struct stc_gpio_ddrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddrc_field_t;
+
+typedef struct stc_gpio_ddrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddrd_field_t;
+
+typedef struct stc_gpio_ddre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddre_field_t;
+
+typedef struct stc_gpio_ddrf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_ddrf_field_t;
+
+typedef struct stc_gpio_pdir0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir0_field_t;
+
+typedef struct stc_gpio_pdir1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir1_field_t;
+
+typedef struct stc_gpio_pdir2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir2_field_t;
+
+typedef struct stc_gpio_pdir3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir3_field_t;
+
+typedef struct stc_gpio_pdir4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdir4_field_t;
+
+typedef struct stc_gpio_pdir5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pdir5_field_t;
+
+typedef struct stc_gpio_pdir6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdir6_field_t;
+
+typedef struct stc_gpio_pdir7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pdir7_field_t;
+
+typedef struct stc_gpio_pdir8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdir8_field_t;
+
+typedef struct stc_gpio_pdira_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdira_field_t;
+
+typedef struct stc_gpio_pdirc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdirc_field_t;
+
+typedef struct stc_gpio_pdird_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdird_field_t;
+
+typedef struct stc_gpio_pdire_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdire_field_t;
+
+typedef struct stc_gpio_pdirf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdirf_field_t;
+
+typedef struct stc_gpio_pdor0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor0_field_t;
+
+typedef struct stc_gpio_pdor1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor1_field_t;
+
+typedef struct stc_gpio_pdor2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor2_field_t;
+
+typedef struct stc_gpio_pdor3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor3_field_t;
+
+typedef struct stc_gpio_pdor4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdor4_field_t;
+
+typedef struct stc_gpio_pdor5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pdor5_field_t;
+
+typedef struct stc_gpio_pdor6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdor6_field_t;
+
+typedef struct stc_gpio_pdor7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pdor7_field_t;
+
+typedef struct stc_gpio_pdor8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdor8_field_t;
+
+typedef struct stc_gpio_pdora_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdora_field_t;
+
+typedef struct stc_gpio_pdorc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdorc_field_t;
+
+typedef struct stc_gpio_pdord_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdord_field_t;
+
+typedef struct stc_gpio_pdore_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdore_field_t;
+
+typedef struct stc_gpio_pdorf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdorf_field_t;
+
+typedef struct stc_gpio_ade_field
+{
+  __IO uint32_t AN0        : 1;
+  __IO uint32_t AN1        : 1;
+  __IO uint32_t AN2        : 1;
+  __IO uint32_t AN3        : 1;
+  __IO uint32_t AN4        : 1;
+  __IO uint32_t AN5        : 1;
+  __IO uint32_t AN6        : 1;
+  __IO uint32_t AN7        : 1;
+  __IO uint32_t AN8        : 1;
+  __IO uint32_t AN9        : 1;
+  __IO uint32_t AN10       : 1;
+  __IO uint32_t AN11       : 1;
+  __IO uint32_t AN12       : 1;
+  __IO uint32_t AN13       : 1;
+  __IO uint32_t AN14       : 1;
+  __IO uint32_t AN15       : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t AN24       : 1;
+  __IO uint32_t AN25       : 1;
+  __IO uint32_t AN26       : 1;
+  __IO uint32_t AN27       : 1;
+  __IO uint32_t AN28       : 1;
+  __IO uint32_t AN29       : 1;
+  __IO uint32_t AN30       : 1;
+  __IO uint32_t AN31       : 1;
+} stc_gpio_ade_field_t;
+
+typedef struct stc_gpio_spsr_field
+{
+  __IO uint32_t SUBXC      : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAINXC     : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USB0C      : 1;
+  __IO uint32_t USB1C      : 1;
+} stc_gpio_spsr_field_t;
+
+typedef struct stc_gpio_epfr00_field
+{
+  __IO uint32_t NMIS       : 1;
+  __IO uint32_t CROUTE0    : 1;
+  __IO uint32_t CROUTE1    : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t SUBOUTE0   : 1;
+  __IO uint32_t SUBOUTE1   : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USBP0E     : 1;
+       uint32_t RESERVED3  : 3;
+  __IO uint32_t USBP1E     : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t JTAGEN0B   : 1;
+  __IO uint32_t JTAGEN1S   : 1;
+       uint32_t RESERVED5  : 6;
+  __IO uint32_t TRC0E      : 1;
+  __IO uint32_t TRC1E      : 1;
+} stc_gpio_epfr00_field_t;
+
+typedef struct stc_gpio_epfr01_field
+{
+  __IO uint32_t RTO00E0    : 1;
+  __IO uint32_t RTO00E1    : 1;
+  __IO uint32_t RTO01E0    : 1;
+  __IO uint32_t RTO01E1    : 1;
+  __IO uint32_t RTO02E0    : 1;
+  __IO uint32_t RTO02E1    : 1;
+  __IO uint32_t RTO03E0    : 1;
+  __IO uint32_t RTO03E1    : 1;
+  __IO uint32_t RTO04E0    : 1;
+  __IO uint32_t RTO04E1    : 1;
+  __IO uint32_t RTO05E0    : 1;
+  __IO uint32_t RTO05E1    : 1;
+  __IO uint32_t DTTI0C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI0S0    : 1;
+  __IO uint32_t DTTI0S1    : 1;
+  __IO uint32_t FRCK0S0    : 1;
+  __IO uint32_t FRCK0S1    : 1;
+  __IO uint32_t IC00S0     : 1;
+  __IO uint32_t IC00S1     : 1;
+  __IO uint32_t IC00S2     : 1;
+  __IO uint32_t IC01S0     : 1;
+  __IO uint32_t IC01S1     : 1;
+  __IO uint32_t IC01S2     : 1;
+  __IO uint32_t IC02S0     : 1;
+  __IO uint32_t IC02S1     : 1;
+  __IO uint32_t IC02S2     : 1;
+  __IO uint32_t IC03S0     : 1;
+  __IO uint32_t IC03S1     : 1;
+  __IO uint32_t IC03S2     : 1;
+} stc_gpio_epfr01_field_t;
+
+typedef struct stc_gpio_epfr02_field
+{
+  __IO uint32_t RTO10E0    : 1;
+  __IO uint32_t RTO10E1    : 1;
+  __IO uint32_t RTO11E0    : 1;
+  __IO uint32_t RTO11E1    : 1;
+  __IO uint32_t RTO12E0    : 1;
+  __IO uint32_t RTO12E1    : 1;
+  __IO uint32_t RTO13E0    : 1;
+  __IO uint32_t RTO13E1    : 1;
+  __IO uint32_t RTO14E0    : 1;
+  __IO uint32_t RTO14E1    : 1;
+  __IO uint32_t RTO15E0    : 1;
+  __IO uint32_t RTO15E1    : 1;
+  __IO uint32_t DTTI1C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI1S0    : 1;
+  __IO uint32_t DTTI1S1    : 1;
+  __IO uint32_t FRCK1S0    : 1;
+  __IO uint32_t FRCK1S1    : 1;
+  __IO uint32_t IC10S0     : 1;
+  __IO uint32_t IC10S1     : 1;
+  __IO uint32_t IC10S2     : 1;
+  __IO uint32_t IC11S0     : 1;
+  __IO uint32_t IC11S1     : 1;
+  __IO uint32_t IC11S2     : 1;
+  __IO uint32_t IC12S0     : 1;
+  __IO uint32_t IC12S1     : 1;
+  __IO uint32_t IC12S2     : 1;
+  __IO uint32_t IC13S0     : 1;
+  __IO uint32_t IC13S1     : 1;
+  __IO uint32_t IC13S2     : 1;
+} stc_gpio_epfr02_field_t;
+
+typedef struct stc_gpio_epfr03_field
+{
+  __IO uint32_t RTO20E0    : 1;
+  __IO uint32_t RTO20E1    : 1;
+  __IO uint32_t RTO21E0    : 1;
+  __IO uint32_t RTO21E1    : 1;
+  __IO uint32_t RTO22E0    : 1;
+  __IO uint32_t RTO22E1    : 1;
+  __IO uint32_t RTO23E0    : 1;
+  __IO uint32_t RTO23E1    : 1;
+  __IO uint32_t RTO24E0    : 1;
+  __IO uint32_t RTO24E1    : 1;
+  __IO uint32_t RTO25E0    : 1;
+  __IO uint32_t RTO25E1    : 1;
+  __IO uint32_t DTTI2C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI2S0    : 1;
+  __IO uint32_t DTTI2S1    : 1;
+  __IO uint32_t FRCK2S0    : 1;
+  __IO uint32_t FRCK2S1    : 1;
+  __IO uint32_t IC20S0     : 1;
+  __IO uint32_t IC20S1     : 1;
+  __IO uint32_t IC20S2     : 1;
+  __IO uint32_t IC21S0     : 1;
+  __IO uint32_t IC21S1     : 1;
+  __IO uint32_t IC21S2     : 1;
+  __IO uint32_t IC22S0     : 1;
+  __IO uint32_t IC22S1     : 1;
+  __IO uint32_t IC22S2     : 1;
+  __IO uint32_t IC23S0     : 1;
+  __IO uint32_t IC23S1     : 1;
+  __IO uint32_t IC23S2     : 1;
+} stc_gpio_epfr03_field_t;
+
+typedef struct stc_gpio_epfr04_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA0E0    : 1;
+  __IO uint32_t TIOA0E1    : 1;
+  __IO uint32_t TIOB0S0    : 1;
+  __IO uint32_t TIOB0S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA1S0    : 1;
+  __IO uint32_t TIOA1S1    : 1;
+  __IO uint32_t TIOA1E0    : 1;
+  __IO uint32_t TIOA1E1    : 1;
+  __IO uint32_t TIOB1S0    : 1;
+  __IO uint32_t TIOB1S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA2E0    : 1;
+  __IO uint32_t TIOA2E1    : 1;
+  __IO uint32_t TIOB2S0    : 1;
+  __IO uint32_t TIOB2S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA3S0    : 1;
+  __IO uint32_t TIOA3S1    : 1;
+  __IO uint32_t TIOA3E0    : 1;
+  __IO uint32_t TIOA3E1    : 1;
+  __IO uint32_t TIOB3S0    : 1;
+  __IO uint32_t TIOB3S1    : 1;
+} stc_gpio_epfr04_field_t;
+
+typedef struct stc_gpio_epfr05_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA4E0    : 1;
+  __IO uint32_t TIOA4E1    : 1;
+  __IO uint32_t TIOB4S0    : 1;
+  __IO uint32_t TIOB4S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA5S0    : 1;
+  __IO uint32_t TIOA5S1    : 1;
+  __IO uint32_t TIOA5E0    : 1;
+  __IO uint32_t TIOA5E1    : 1;
+  __IO uint32_t TIOB5S0    : 1;
+  __IO uint32_t TIOB5S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA6E0    : 1;
+  __IO uint32_t TIOA6E1    : 1;
+  __IO uint32_t TIOB6S0    : 1;
+  __IO uint32_t TIOB6S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA7S0    : 1;
+  __IO uint32_t TIOA7S1    : 1;
+  __IO uint32_t TIOA7E0    : 1;
+  __IO uint32_t TIOA7E1    : 1;
+  __IO uint32_t TIOB7S0    : 1;
+  __IO uint32_t TIOB7S1    : 1;
+} stc_gpio_epfr05_field_t;
+
+typedef struct stc_gpio_epfr06_field
+{
+  __IO uint32_t EINT00S0   : 1;
+  __IO uint32_t EINT00S1   : 1;
+  __IO uint32_t EINT01S0   : 1;
+  __IO uint32_t EINT01S1   : 1;
+  __IO uint32_t EINT02S0   : 1;
+  __IO uint32_t EINT02S1   : 1;
+  __IO uint32_t EINT03S0   : 1;
+  __IO uint32_t EINT03S1   : 1;
+  __IO uint32_t EINT04S0   : 1;
+  __IO uint32_t EINT04S1   : 1;
+  __IO uint32_t EINT05S0   : 1;
+  __IO uint32_t EINT05S1   : 1;
+  __IO uint32_t EINT06S0   : 1;
+  __IO uint32_t EINT06S1   : 1;
+  __IO uint32_t EINT07S0   : 1;
+  __IO uint32_t EINT07S1   : 1;
+  __IO uint32_t EINT08S0   : 1;
+  __IO uint32_t EINT08S1   : 1;
+  __IO uint32_t EINT09S0   : 1;
+  __IO uint32_t EINT09S1   : 1;
+  __IO uint32_t EINT10S0   : 1;
+  __IO uint32_t EINT10S1   : 1;
+  __IO uint32_t EINT11S0   : 1;
+  __IO uint32_t EINT11S1   : 1;
+  __IO uint32_t EINT12S0   : 1;
+  __IO uint32_t EINT12S1   : 1;
+  __IO uint32_t EINT13S0   : 1;
+  __IO uint32_t EINT13S1   : 1;
+  __IO uint32_t EINT14S0   : 1;
+  __IO uint32_t EINT14S1   : 1;
+  __IO uint32_t EINT15S0   : 1;
+  __IO uint32_t EINT15S1   : 1;
+} stc_gpio_epfr06_field_t;
+
+typedef struct stc_gpio_epfr07_field
+{
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t SIN0S0     : 1;
+  __IO uint32_t SIN0S1     : 1;
+  __IO uint32_t SOT0B0     : 1;
+  __IO uint32_t SOT0B1     : 1;
+  __IO uint32_t SCK0B0     : 1;
+  __IO uint32_t SCK0B1     : 1;
+  __IO uint32_t SIN1S0     : 1;
+  __IO uint32_t SIN1S1     : 1;
+  __IO uint32_t SOT1B0     : 1;
+  __IO uint32_t SOT1B1     : 1;
+  __IO uint32_t SCK1B0     : 1;
+  __IO uint32_t SCK1B1     : 1;
+  __IO uint32_t SIN2S0     : 1;
+  __IO uint32_t SIN2S1     : 1;
+  __IO uint32_t SOT2B0     : 1;
+  __IO uint32_t SOT2B1     : 1;
+  __IO uint32_t SCK2B0     : 1;
+  __IO uint32_t SCK2B1     : 1;
+  __IO uint32_t SIN3S0     : 1;
+  __IO uint32_t SIN3S1     : 1;
+  __IO uint32_t SOT3B0     : 1;
+  __IO uint32_t SOT3B1     : 1;
+  __IO uint32_t SCK3B0     : 1;
+  __IO uint32_t SCK3B1     : 1;
+} stc_gpio_epfr07_field_t;
+
+typedef struct stc_gpio_epfr08_field
+{
+  __IO uint32_t RTS4E0     : 1;
+  __IO uint32_t RTS4E1     : 1;
+  __IO uint32_t CTS4S0     : 1;
+  __IO uint32_t CTS4S1     : 1;
+  __IO uint32_t SIN4S0     : 1;
+  __IO uint32_t SIN4S1     : 1;
+  __IO uint32_t SOT4B0     : 1;
+  __IO uint32_t SOT4B1     : 1;
+  __IO uint32_t SCK4B0     : 1;
+  __IO uint32_t SCK4B1     : 1;
+  __IO uint32_t SIN5S0     : 1;
+  __IO uint32_t SIN5S1     : 1;
+  __IO uint32_t SOT5B0     : 1;
+  __IO uint32_t SOT5B1     : 1;
+  __IO uint32_t SCK5B0     : 1;
+  __IO uint32_t SCK5B1     : 1;
+  __IO uint32_t SIN6S0     : 1;
+  __IO uint32_t SIN6S1     : 1;
+  __IO uint32_t SOT6B0     : 1;
+  __IO uint32_t SOT6B1     : 1;
+  __IO uint32_t SCK6B0     : 1;
+  __IO uint32_t SCK6B1     : 1;
+  __IO uint32_t SIN7S0     : 1;
+  __IO uint32_t SIN7S1     : 1;
+  __IO uint32_t SOT7B0     : 1;
+  __IO uint32_t SOT7B1     : 1;
+  __IO uint32_t SCK7B0     : 1;
+  __IO uint32_t SCK7B1     : 1;
+} stc_gpio_epfr08_field_t;
+
+typedef struct stc_gpio_epfr09_field
+{
+  __IO uint32_t QAIN0S0    : 1;
+  __IO uint32_t QAIN0S1    : 1;
+  __IO uint32_t QBIN0S0    : 1;
+  __IO uint32_t QBIN0S1    : 1;
+  __IO uint32_t QZIN0S0    : 1;
+  __IO uint32_t QZIN0S1    : 1;
+  __IO uint32_t QAIN1S0    : 1;
+  __IO uint32_t QAIN1S1    : 1;
+  __IO uint32_t QBIN1S0    : 1;
+  __IO uint32_t QBIN1S1    : 1;
+  __IO uint32_t QZIN1S0    : 1;
+  __IO uint32_t QZIN1S1    : 1;
+  __IO uint32_t ADTRG0S0   : 1;
+  __IO uint32_t ADTRG0S1   : 1;
+  __IO uint32_t ADTRG0S2   : 1;
+  __IO uint32_t ADTRG0S3   : 1;
+  __IO uint32_t ADTRG1S0   : 1;
+  __IO uint32_t ADTRG1S1   : 1;
+  __IO uint32_t ADTRG1S2   : 1;
+  __IO uint32_t ADTRG1S3   : 1;
+  __IO uint32_t ADTRG2S0   : 1;
+  __IO uint32_t ADTRG2S1   : 1;
+  __IO uint32_t ADTRG2S2   : 1;
+  __IO uint32_t ADTRG2S3   : 1;
+} stc_gpio_epfr09_field_t;
+
+typedef struct stc_gpio_epfr10_field
+{
+  __IO uint32_t UEDEFB     : 1;
+  __IO uint32_t UEDTHB     : 1;
+  __IO uint32_t UECLKE     : 1;
+  __IO uint32_t UEWEXE     : 1;
+  __IO uint32_t UEDQME     : 1;
+  __IO uint32_t UEOEXE     : 1;
+  __IO uint32_t UEFLSE     : 1;
+  __IO uint32_t UECS1E     : 1;
+  __IO uint32_t UECS2E     : 1;
+  __IO uint32_t UECS3E     : 1;
+  __IO uint32_t UECS4E     : 1;
+  __IO uint32_t UECS5E     : 1;
+  __IO uint32_t UECS6E     : 1;
+  __IO uint32_t UECS7E     : 1;
+  __IO uint32_t UEAOOE     : 1;
+  __IO uint32_t UEA08E     : 1;
+  __IO uint32_t UEA09E     : 1;
+  __IO uint32_t UEA10E     : 1;
+  __IO uint32_t UEA11E     : 1;
+  __IO uint32_t UEA12E     : 1;
+  __IO uint32_t UEA13E     : 1;
+  __IO uint32_t UEA14E     : 1;
+  __IO uint32_t UEA15E     : 1;
+  __IO uint32_t UEA16E     : 1;
+  __IO uint32_t UEA17E     : 1;
+  __IO uint32_t UEA18E     : 1;
+} stc_gpio_epfr10_field_t;
+
+typedef struct stc_gpio_epfr11_field
+{
+  __IO uint32_t UEALEE     : 1;
+  __IO uint32_t UECS0E     : 1;
+  __IO uint32_t UEA01E     : 1;
+  __IO uint32_t UEA02E     : 1;
+  __IO uint32_t UEA03E     : 1;
+  __IO uint32_t UEA04E     : 1;
+  __IO uint32_t UEA05E     : 1;
+  __IO uint32_t UEA06E     : 1;
+  __IO uint32_t UEA07E     : 1;
+  __IO uint32_t UED00B     : 1;
+  __IO uint32_t UED01B     : 1;
+  __IO uint32_t UED02B     : 1;
+  __IO uint32_t UED03B     : 1;
+  __IO uint32_t UED04B     : 1;
+  __IO uint32_t UED05B     : 1;
+  __IO uint32_t UED06B     : 1;
+  __IO uint32_t UED07B     : 1;
+  __IO uint32_t UED08B     : 1;
+  __IO uint32_t UED09B     : 1;
+  __IO uint32_t UED10B     : 1;
+  __IO uint32_t UED11B     : 1;
+  __IO uint32_t UED12B     : 1;
+  __IO uint32_t UED13B     : 1;
+  __IO uint32_t UED14B     : 1;
+  __IO uint32_t UED15B     : 1;
+  __IO uint32_t UERLC      : 1;
+} stc_gpio_epfr11_field_t;
+
+typedef struct stc_gpio_epfr12_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA8E0    : 1;
+  __IO uint32_t TIOA8E1    : 1;
+  __IO uint32_t TIOB8S0    : 1;
+  __IO uint32_t TIOB8S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA9S0    : 1;
+  __IO uint32_t TIOA9S1    : 1;
+  __IO uint32_t TIOA9E0    : 1;
+  __IO uint32_t TIOA9E1    : 1;
+  __IO uint32_t TIOB9S0    : 1;
+  __IO uint32_t TIOB9S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA10E0   : 1;
+  __IO uint32_t TIOA10E1   : 1;
+  __IO uint32_t TIOB10S0   : 1;
+  __IO uint32_t TIOB10S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA11S0   : 1;
+  __IO uint32_t TIOA11S1   : 1;
+  __IO uint32_t TIOA11E0   : 1;
+  __IO uint32_t TIOA11E1   : 1;
+  __IO uint32_t TIOB11S0   : 1;
+  __IO uint32_t TIOB11S1   : 1;
+} stc_gpio_epfr12_field_t;
+
+typedef struct stc_gpio_epfr13_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA12E0   : 1;
+  __IO uint32_t TIOA12E1   : 1;
+  __IO uint32_t TIOB12S0   : 1;
+  __IO uint32_t TIOB12S1   : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA13S0   : 1;
+  __IO uint32_t TIOA13S1   : 1;
+  __IO uint32_t TIOA13E0   : 1;
+  __IO uint32_t TIOA13E1   : 1;
+  __IO uint32_t TIOB13S0   : 1;
+  __IO uint32_t TIOB13S1   : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA14E0   : 1;
+  __IO uint32_t TIOA14E1   : 1;
+  __IO uint32_t TIOB14S0   : 1;
+  __IO uint32_t TIOB14S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA15S0   : 1;
+  __IO uint32_t TIOA15S1   : 1;
+  __IO uint32_t TIOA15E0   : 1;
+  __IO uint32_t TIOA15E1   : 1;
+  __IO uint32_t TIOB15S0   : 1;
+  __IO uint32_t TIOB15S1   : 1;
+} stc_gpio_epfr13_field_t;
+
+typedef struct stc_gpio_epfr14_field
+{
+  __IO uint32_t QAIN2S0    : 1;
+  __IO uint32_t QAIN2S1    : 1;
+  __IO uint32_t QBIN2S0    : 1;
+  __IO uint32_t QBIN2S1    : 1;
+  __IO uint32_t QZIN2S0    : 1;
+  __IO uint32_t QZIN2S1    : 1;
+       uint32_t RESERVED1  : 12;
+  __IO uint32_t E_TD0E     : 1;
+  __IO uint32_t E_TD1E     : 1;
+  __IO uint32_t E_TE0E     : 1;
+  __IO uint32_t E_TE1E     : 1;
+  __IO uint32_t E_MC0E     : 1;
+  __IO uint32_t E_MC1B     : 1;
+  __IO uint32_t E_MD0B     : 1;
+  __IO uint32_t E_MD1B     : 1;
+  __IO uint32_t E_CKE      : 1;
+  __IO uint32_t E_PSE      : 1;
+  __IO uint32_t E_SPLC0    : 1;
+  __IO uint32_t E_SPLC1    : 1;
+} stc_gpio_epfr14_field_t;
+
+typedef struct stc_gpio_epfr15_field
+{
+  __IO uint32_t EINT16S0   : 1;
+  __IO uint32_t EINT16S1   : 1;
+  __IO uint32_t EINT17S0   : 1;
+  __IO uint32_t EINT17S1   : 1;
+  __IO uint32_t EINT18S0   : 1;
+  __IO uint32_t EINT18S1   : 1;
+  __IO uint32_t EINT19S0   : 1;
+  __IO uint32_t EINT19S1   : 1;
+  __IO uint32_t EINT20S0   : 1;
+  __IO uint32_t EINT20S1   : 1;
+  __IO uint32_t EINT21S0   : 1;
+  __IO uint32_t EINT21S1   : 1;
+  __IO uint32_t EINT22S0   : 1;
+  __IO uint32_t EINT22S1   : 1;
+  __IO uint32_t EINT23S0   : 1;
+  __IO uint32_t EINT23S1   : 1;
+  __IO uint32_t EINT24S0   : 1;
+  __IO uint32_t EINT24S1   : 1;
+  __IO uint32_t EINT25S0   : 1;
+  __IO uint32_t EINT25S1   : 1;
+  __IO uint32_t EINT26S0   : 1;
+  __IO uint32_t EINT26S1   : 1;
+  __IO uint32_t EINT27S0   : 1;
+  __IO uint32_t EINT27S1   : 1;
+  __IO uint32_t EINT28S0   : 1;
+  __IO uint32_t EINT28S1   : 1;
+  __IO uint32_t EINT29S0   : 1;
+  __IO uint32_t EINT29S1   : 1;
+  __IO uint32_t EINT30S0   : 1;
+  __IO uint32_t EINT30S1   : 1;
+  __IO uint32_t EINT31S0   : 1;
+  __IO uint32_t EINT31S1   : 1;
+} stc_gpio_epfr15_field_t;
+
+typedef struct stc_gpio_pzr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr0_field_t;
+
+typedef struct stc_gpio_pzr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr1_field_t;
+
+typedef struct stc_gpio_pzr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr2_field_t;
+
+typedef struct stc_gpio_pzr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr3_field_t;
+
+typedef struct stc_gpio_pzr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pzr4_field_t;
+
+typedef struct stc_gpio_pzr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pzr5_field_t;
+
+typedef struct stc_gpio_pzr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pzr6_field_t;
+
+typedef struct stc_gpio_pzr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pzr7_field_t;
+
+typedef struct stc_gpio_pzr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzr8_field_t;
+
+typedef struct stc_gpio_pzra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pzra_field_t;
+
+typedef struct stc_gpio_pzrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzrc_field_t;
+
+typedef struct stc_gpio_pzrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzrd_field_t;
+
+typedef struct stc_gpio_pzre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzre_field_t;
+
+typedef struct stc_gpio_pzrf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pzrf_field_t;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* LVD_MODULE register bit fields */
+typedef struct stc_lvd_lvd_ctl_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SVHI0      : 1;
+  __IO  uint8_t SVHI1      : 1;
+  __IO  uint8_t SVHI2      : 1;
+  __IO  uint8_t SVHI3      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t LVDIE      : 1;
+} stc_lvd_lvd_ctl_field_t;
+
+typedef struct stc_lvd_lvd_str_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIR      : 1;
+} stc_lvd_lvd_str_field_t;
+
+typedef struct stc_lvd_lvd_clr_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDCL      : 1;
+} stc_lvd_lvd_clr_field_t;
+
+typedef struct stc_lvd_lvd_str2_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIRDY    : 1;
+} stc_lvd_lvd_str2_field_t;
+
+/******************************************************************************
+ * USB Ethernet CLK
+ ******************************************************************************/
+/* USB ETHERNET CLK register bit fields */
+typedef struct stc_usbethernetclk_uccr_field
+{
+  __IO  uint8_t UCEN0      : 1;
+  __IO  uint8_t UCSEL0     : 1;
+  __IO  uint8_t UCSEL1     : 1;
+  __IO  uint8_t UCEN1      : 1;
+  __IO  uint8_t ECEN       : 1;
+  __IO  uint8_t ECSEL0     : 1;
+  __IO  uint8_t ECSEL1     : 1;
+} stc_usbethernetclk_uccr_field_t;
+
+typedef struct stc_usbethernetclk_upcr1_field
+{
+  __IO  uint8_t UPLLEN     : 1;
+  __IO  uint8_t UPINC      : 1;
+} stc_usbethernetclk_upcr1_field_t;
+
+typedef struct stc_usbethernetclk_upcr2_field
+{
+  __IO  uint8_t UPOWT0     : 1;
+  __IO  uint8_t UPOWT1     : 1;
+  __IO  uint8_t UPOWT2     : 1;
+} stc_usbethernetclk_upcr2_field_t;
+
+typedef struct stc_usbethernetclk_upcr3_field
+{
+  __IO  uint8_t UPLLK0     : 1;
+  __IO  uint8_t UPLLK1     : 1;
+  __IO  uint8_t UPLLK2     : 1;
+  __IO  uint8_t UPLLK3     : 1;
+  __IO  uint8_t UPLLK4     : 1;
+} stc_usbethernetclk_upcr3_field_t;
+
+typedef struct stc_usbethernetclk_upcr4_field
+{
+  __IO  uint8_t UPLLN0     : 1;
+  __IO  uint8_t UPLLN1     : 1;
+  __IO  uint8_t UPLLN2     : 1;
+  __IO  uint8_t UPLLN3     : 1;
+  __IO  uint8_t UPLLN4     : 1;
+  __IO  uint8_t UPLLN5     : 1;
+  __IO  uint8_t UPLLN6     : 1;
+} stc_usbethernetclk_upcr4_field_t;
+
+typedef struct stc_usbethernetclk_up_str_field
+{
+  __IO  uint8_t UPRDY      : 1;
+} stc_usbethernetclk_up_str_field_t;
+
+typedef struct stc_usbethernetclk_upint_enr_field
+{
+  __IO  uint8_t UPCSE      : 1;
+} stc_usbethernetclk_upint_enr_field_t;
+
+typedef struct stc_usbethernetclk_upint_clr_field
+{
+  __IO  uint8_t UPCSC      : 1;
+} stc_usbethernetclk_upint_clr_field_t;
+
+typedef struct stc_usbethernetclk_upint_str_field
+{
+  __IO  uint8_t UPCSI      : 1;
+} stc_usbethernetclk_upint_str_field_t;
+
+typedef struct stc_usbethernetclk_upcr5_field
+{
+  __IO  uint8_t UPLLM0     : 1;
+  __IO  uint8_t UPLLM1     : 1;
+  __IO  uint8_t UPLLM2     : 1;
+  __IO  uint8_t UPLLM3     : 1;
+} stc_usbethernetclk_upcr5_field_t;
+
+typedef struct stc_usbethernetclk_upcr6_field
+{
+  __IO  uint8_t UBSR0      : 1;
+  __IO  uint8_t UBSR1      : 1;
+  __IO  uint8_t UBSR2      : 1;
+  __IO  uint8_t UBSR3      : 1;
+} stc_usbethernetclk_upcr6_field_t;
+
+typedef struct stc_usbethernetclk_upcr7_field
+{
+  __IO  uint8_t EPLLEN     : 1;
+} stc_usbethernetclk_upcr7_field_t;
+
+typedef struct stc_usbethernetclk_usben0_field
+{
+  __IO  uint8_t USBEN0     : 1;
+} stc_usbethernetclk_usben0_field_t;
+
+typedef struct stc_usbethernetclk_usben1_field
+{
+  __IO  uint8_t USBEN1     : 1;
+} stc_usbethernetclk_usben1_field_t;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* MFS03_UART_MODULE register bit fields */
+typedef struct stc_mfs03_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_uart_smr_field_t;
+
+typedef struct stc_mfs03_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_uart_scr_field_t;
+
+typedef struct stc_mfs03_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs03_uart_escr_field_t;
+
+typedef struct stc_mfs03_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_uart_ssr_field_t;
+
+typedef struct stc_mfs03_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_rdr_field_t;
+
+typedef struct stc_mfs03_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_tdr_field_t;
+
+typedef struct stc_mfs03_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_uart_bgr_field_t;
+
+typedef struct stc_mfs03_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_uart_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* MFS03_CSIO_MODULE register bit fields */
+typedef struct stc_mfs03_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_csio_smr_field_t;
+
+typedef struct stc_mfs03_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_csio_scr_field_t;
+
+typedef struct stc_mfs03_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs03_csio_escr_field_t;
+
+typedef struct stc_mfs03_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_csio_ssr_field_t;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* MFS03_LIN_MODULE register bit fields */
+typedef struct stc_mfs03_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_lin_smr_field_t;
+
+typedef struct stc_mfs03_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_lin_scr_field_t;
+
+typedef struct stc_mfs03_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs03_lin_escr_field_t;
+
+typedef struct stc_mfs03_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_lin_ssr_field_t;
+
+typedef struct stc_mfs03_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_lin_bgr_field_t;
+
+typedef struct stc_mfs03_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_lin_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* MFS03_I2C_MODULE register bit fields */
+typedef struct stc_mfs03_i2c_smr_field
+{
+  __IO  uint8_t ITST0      : 1;
+  __IO  uint8_t ITST1      : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_i2c_smr_field_t;
+
+typedef struct stc_mfs03_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs03_i2c_ibcr_field_t;
+
+typedef struct stc_mfs03_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs03_i2c_ibsr_field_t;
+
+typedef struct stc_mfs03_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_i2c_ssr_field_t;
+
+typedef struct stc_mfs03_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs03_i2c_isba_field_t;
+
+typedef struct stc_mfs03_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs03_i2c_ismk_field_t;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* MFS47_UART_MODULE register bit fields */
+typedef struct stc_mfs47_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_uart_smr_field_t;
+
+typedef struct stc_mfs47_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_uart_scr_field_t;
+
+typedef struct stc_mfs47_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs47_uart_escr_field_t;
+
+typedef struct stc_mfs47_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_uart_ssr_field_t;
+
+typedef struct stc_mfs47_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_rdr_field_t;
+
+typedef struct stc_mfs47_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_tdr_field_t;
+
+typedef struct stc_mfs47_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_uart_bgr_field_t;
+
+typedef struct stc_mfs47_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_uart_bgr1_field_t;
+
+typedef struct stc_mfs47_uart_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_uart_fcr_field_t;
+
+typedef struct stc_mfs47_uart_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_uart_fcr0_field_t;
+
+typedef struct stc_mfs47_uart_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_uart_fcr1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_uart_fbyte_field_t;
+
+typedef struct stc_mfs47_uart_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_uart_fbyte1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_uart_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* MFS47_CSIO_MODULE register bit fields */
+typedef struct stc_mfs47_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_csio_smr_field_t;
+
+typedef struct stc_mfs47_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_csio_scr_field_t;
+
+typedef struct stc_mfs47_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs47_csio_escr_field_t;
+
+typedef struct stc_mfs47_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_csio_ssr_field_t;
+
+typedef struct stc_mfs47_csio_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_csio_fcr_field_t;
+
+typedef struct stc_mfs47_csio_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_csio_fcr0_field_t;
+
+typedef struct stc_mfs47_csio_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_csio_fcr1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_csio_fbyte_field_t;
+
+typedef struct stc_mfs47_csio_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_csio_fbyte1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_csio_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* MFS47_LIN_MODULE register bit fields */
+typedef struct stc_mfs47_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_lin_smr_field_t;
+
+typedef struct stc_mfs47_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_lin_scr_field_t;
+
+typedef struct stc_mfs47_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs47_lin_escr_field_t;
+
+typedef struct stc_mfs47_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_lin_ssr_field_t;
+
+typedef struct stc_mfs47_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_lin_bgr_field_t;
+
+typedef struct stc_mfs47_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_lin_bgr1_field_t;
+
+typedef struct stc_mfs47_lin_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_lin_fcr_field_t;
+
+typedef struct stc_mfs47_lin_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_lin_fcr0_field_t;
+
+typedef struct stc_mfs47_lin_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_lin_fcr1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_lin_fbyte_field_t;
+
+typedef struct stc_mfs47_lin_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_lin_fbyte1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_lin_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* MFS47_I2C_MODULE register bit fields */
+typedef struct stc_mfs47_i2c_smr_field
+{
+  __IO  uint8_t ITST0      : 1;
+  __IO  uint8_t ITST1      : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_i2c_smr_field_t;
+
+typedef struct stc_mfs47_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs47_i2c_ibcr_field_t;
+
+typedef struct stc_mfs47_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs47_i2c_ibsr_field_t;
+
+typedef struct stc_mfs47_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_i2c_ssr_field_t;
+
+typedef struct stc_mfs47_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs47_i2c_isba_field_t;
+
+typedef struct stc_mfs47_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs47_i2c_ismk_field_t;
+
+typedef struct stc_mfs47_i2c_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_i2c_fcr_field_t;
+
+typedef struct stc_mfs47_i2c_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_i2c_fcr0_field_t;
+
+typedef struct stc_mfs47_i2c_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_i2c_fcr1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_i2c_fbyte_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_i2c_fbyte1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_i2c_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct stc_mfs_nfc_i2cdnf_field
+{
+  __IO uint16_t I2CDNF00   : 1;
+  __IO uint16_t I2CDNF01   : 1;
+  __IO uint16_t I2CDNF10   : 1;
+  __IO uint16_t I2CDNF11   : 1;
+  __IO uint16_t I2CDNF20   : 1;
+  __IO uint16_t I2CDNF21   : 1;
+  __IO uint16_t I2CDNF30   : 1;
+  __IO uint16_t I2CDNF31   : 1;
+  __IO uint16_t I2CDNF40   : 1;
+  __IO uint16_t I2CDNF41   : 1;
+  __IO uint16_t I2CDNF50   : 1;
+  __IO uint16_t I2CDNF51   : 1;
+  __IO uint16_t I2CDNF60   : 1;
+  __IO uint16_t I2CDNF61   : 1;
+  __IO uint16_t I2CDNF70   : 1;
+  __IO uint16_t I2CDNF71   : 1;
+} stc_mfs_nfc_i2cdnf_field_t;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC_MODULE register bit fields */
+typedef struct stc_crc_crccr_field
+{
+  __IO  uint8_t INIT       : 1;
+  __IO  uint8_t CRC32      : 1;
+  __IO  uint8_t LTLEND     : 1;
+  __IO  uint8_t LSBFST     : 1;
+  __IO  uint8_t CRCLTE     : 1;
+  __IO  uint8_t CRCLSF     : 1;
+  __IO  uint8_t FXOR       : 1;
+} stc_crc_crccr_field_t;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* WC_MODULE register bit fields */
+typedef struct stc_wc_wcrd_field
+{
+  __IO  uint8_t CTR0       : 1;
+  __IO  uint8_t CTR1       : 1;
+  __IO  uint8_t CTR2       : 1;
+  __IO  uint8_t CTR3       : 1;
+  __IO  uint8_t CTR4       : 1;
+  __IO  uint8_t CTR5       : 1;
+} stc_wc_wcrd_field_t;
+
+typedef struct stc_wc_wcrl_field
+{
+  __IO  uint8_t RLC0       : 1;
+  __IO  uint8_t RLC1       : 1;
+  __IO  uint8_t RLC2       : 1;
+  __IO  uint8_t RLC3       : 1;
+  __IO  uint8_t RLC4       : 1;
+  __IO  uint8_t RLC5       : 1;
+} stc_wc_wcrl_field_t;
+
+typedef struct stc_wc_wccr_field
+{
+  __IO  uint8_t WCIF       : 1;
+  __IO  uint8_t WCIE       : 1;
+  __IO  uint8_t CS0        : 1;
+  __IO  uint8_t CS1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t WCOP       : 1;
+  __IO  uint8_t WCEN       : 1;
+} stc_wc_wccr_field_t;
+
+typedef struct stc_wc_clk_sel_field
+{
+  __IO uint16_t SEL_IN     : 1;
+       uint16_t RESERVED1  : 7;
+  __IO uint16_t SEL_OUT    : 1;
+} stc_wc_clk_sel_field_t;
+
+typedef struct stc_wc_clk_en_field
+{
+  __IO  uint8_t CLK_EN     : 1;
+  __IO  uint8_t CLK_EN_R   : 1;
+} stc_wc_clk_en_field_t;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* EXBUS_MODULE register bit fields */
+typedef struct stc_exbus_mode0_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode0_field_t;
+
+typedef struct stc_exbus_mode1_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode1_field_t;
+
+typedef struct stc_exbus_mode2_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode2_field_t;
+
+typedef struct stc_exbus_mode3_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode3_field_t;
+
+typedef struct stc_exbus_mode4_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode4_field_t;
+
+typedef struct stc_exbus_mode5_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode5_field_t;
+
+typedef struct stc_exbus_mode6_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode6_field_t;
+
+typedef struct stc_exbus_mode7_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode7_field_t;
+
+typedef struct stc_exbus_tim0_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim0_field_t;
+
+typedef struct stc_exbus_tim1_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim1_field_t;
+
+typedef struct stc_exbus_tim2_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim2_field_t;
+
+typedef struct stc_exbus_tim3_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim3_field_t;
+
+typedef struct stc_exbus_tim4_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim4_field_t;
+
+typedef struct stc_exbus_tim5_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim5_field_t;
+
+typedef struct stc_exbus_tim6_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim6_field_t;
+
+typedef struct stc_exbus_tim7_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim7_field_t;
+
+typedef struct stc_exbus_area0_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area0_field_t;
+
+typedef struct stc_exbus_area1_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area1_field_t;
+
+typedef struct stc_exbus_area2_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area2_field_t;
+
+typedef struct stc_exbus_area3_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area3_field_t;
+
+typedef struct stc_exbus_area4_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area4_field_t;
+
+typedef struct stc_exbus_area5_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area5_field_t;
+
+typedef struct stc_exbus_area6_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area6_field_t;
+
+typedef struct stc_exbus_area7_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area7_field_t;
+
+typedef struct stc_exbus_atim0_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim0_field_t;
+
+typedef struct stc_exbus_atim1_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim1_field_t;
+
+typedef struct stc_exbus_atim2_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim2_field_t;
+
+typedef struct stc_exbus_atim3_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim3_field_t;
+
+typedef struct stc_exbus_atim4_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim4_field_t;
+
+typedef struct stc_exbus_atim5_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim5_field_t;
+
+typedef struct stc_exbus_atim6_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim6_field_t;
+
+typedef struct stc_exbus_atim7_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim7_field_t;
+
+typedef struct stc_exbus_dclkr_field
+{
+  __IO  uint8_t MDIV0      : 1;
+  __IO  uint8_t MDIV1      : 1;
+  __IO  uint8_t MDIV2      : 1;
+  __IO  uint8_t MDIV3      : 1;
+  __IO  uint8_t MCLKON     : 1;
+} stc_exbus_dclkr_field_t;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB_MODULE register bit fields */
+typedef struct stc_usb_hcnt_field
+{
+  __IO uint16_t HOST       : 1;
+  __IO uint16_t URST       : 1;
+  __IO uint16_t SOFIRE     : 1;
+  __IO uint16_t DIRE       : 1;
+  __IO uint16_t CNNIRE     : 1;
+  __IO uint16_t CMPIRE     : 1;
+  __IO uint16_t URIRE      : 1;
+  __IO uint16_t RWKIRE     : 1;
+  __IO uint16_t RETRY      : 1;
+  __IO uint16_t CANCEL     : 1;
+  __IO uint16_t SOFSTEP    : 1;
+} stc_usb_hcnt_field_t;
+
+typedef struct stc_usb_hcnt0_field
+{
+  __IO  uint8_t HOST       : 1;
+  __IO  uint8_t URST       : 1;
+  __IO  uint8_t SOFIRE     : 1;
+  __IO  uint8_t DIRE       : 1;
+  __IO  uint8_t CNNIRE     : 1;
+  __IO  uint8_t CMPIRE     : 1;
+  __IO  uint8_t URIRE      : 1;
+  __IO  uint8_t RWKIRE     : 1;
+} stc_usb_hcnt0_field_t;
+
+typedef struct stc_usb_hcnt1_field
+{
+  __IO  uint8_t RETRY      : 1;
+  __IO  uint8_t CANCEL     : 1;
+  __IO  uint8_t SOFSTEP    : 1;
+} stc_usb_hcnt1_field_t;
+
+typedef struct stc_usb_hirq_field
+{
+  __IO  uint8_t SOFIRQ     : 1;
+  __IO  uint8_t DIRQ       : 1;
+  __IO  uint8_t CNNIRQ     : 1;
+  __IO  uint8_t CMPIRQ     : 1;
+  __IO  uint8_t URIRQ      : 1;
+  __IO  uint8_t RWKIRQ     : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TCAN       : 1;
+} stc_usb_hirq_field_t;
+
+typedef struct stc_usb_herr_field
+{
+  __IO  uint8_t HS0        : 1;
+  __IO  uint8_t HS1        : 1;
+  __IO  uint8_t STUFF      : 1;
+  __IO  uint8_t TGERR      : 1;
+  __IO  uint8_t CRC        : 1;
+  __IO  uint8_t TOUT       : 1;
+  __IO  uint8_t RERR       : 1;
+  __IO  uint8_t LSTOF      : 1;
+} stc_usb_herr_field_t;
+
+typedef struct stc_usb_hstate_field
+{
+  __IO  uint8_t CSTAT      : 1;
+  __IO  uint8_t TMODE      : 1;
+  __IO  uint8_t SUSP       : 1;
+  __IO  uint8_t SOFBUSY    : 1;
+  __IO  uint8_t CLKSEL     : 1;
+  __IO  uint8_t ALIVE      : 1;
+} stc_usb_hstate_field_t;
+
+typedef struct stc_usb_hfcomp_field
+{
+  __IO  uint8_t FRAMECOMP0 : 1;
+  __IO  uint8_t FRAMECOMP1 : 1;
+  __IO  uint8_t FRAMECOMP2 : 1;
+  __IO  uint8_t FRAMECOMP3 : 1;
+  __IO  uint8_t FRAMECOMP4 : 1;
+  __IO  uint8_t FRAMECOMP5 : 1;
+  __IO  uint8_t FRAMECOMP6 : 1;
+  __IO  uint8_t FRAMECOMP7 : 1;
+} stc_usb_hfcomp_field_t;
+
+typedef struct stc_usb_hrtimer_field
+{
+  __IO uint16_t RTIMER0    : 1;
+  __IO uint16_t RTIMER1    : 1;
+  __IO uint16_t RTIMER2    : 1;
+  __IO uint16_t RTIMER3    : 1;
+  __IO uint16_t RTIMER4    : 1;
+  __IO uint16_t RTIMER5    : 1;
+  __IO uint16_t RTIMER6    : 1;
+  __IO uint16_t RTIMER7    : 1;
+  __IO uint16_t RTIMER8    : 1;
+  __IO uint16_t RTIMER9    : 1;
+  __IO uint16_t RTIMER10   : 1;
+  __IO uint16_t RTIMER11   : 1;
+  __IO uint16_t RTIMER12   : 1;
+  __IO uint16_t RTIMER13   : 1;
+  __IO uint16_t RTIMER14   : 1;
+  __IO uint16_t RTIMER15   : 1;
+} stc_usb_hrtimer_field_t;
+
+typedef struct stc_usb_hrtimer0_field
+{
+  __IO  uint8_t RTIMER00   : 1;
+  __IO  uint8_t RTIMER01   : 1;
+  __IO  uint8_t RTIMER02   : 1;
+  __IO  uint8_t RTIMER03   : 1;
+  __IO  uint8_t RTIMER04   : 1;
+  __IO  uint8_t RTIMER05   : 1;
+  __IO  uint8_t RTIMER06   : 1;
+  __IO  uint8_t RTIMER07   : 1;
+} stc_usb_hrtimer0_field_t;
+
+typedef struct stc_usb_hrtimer1_field
+{
+  __IO  uint8_t RTIMER10   : 1;
+  __IO  uint8_t RTIMER11   : 1;
+  __IO  uint8_t RTIMER12   : 1;
+  __IO  uint8_t RTIMER13   : 1;
+  __IO  uint8_t RTIMER14   : 1;
+  __IO  uint8_t RTIMER15   : 1;
+  __IO  uint8_t RTIMER16   : 1;
+  __IO  uint8_t RTIMER17   : 1;
+} stc_usb_hrtimer1_field_t;
+
+typedef struct stc_usb_hrtimer2_field
+{
+  __IO  uint8_t RTIMER20   : 1;
+  __IO  uint8_t RTIMER21   : 1;
+  __IO  uint8_t RTIMER22   : 1;
+} stc_usb_hrtimer2_field_t;
+
+typedef struct stc_usb_hadr_field
+{
+  __IO  uint8_t ADDRESS0   : 1;
+  __IO  uint8_t ADDRESS1   : 1;
+  __IO  uint8_t ADDRESS2   : 1;
+  __IO  uint8_t ADDRESS3   : 1;
+  __IO  uint8_t ADDRESS4   : 1;
+  __IO  uint8_t ADDRESS5   : 1;
+  __IO  uint8_t ADDRESS6   : 1;
+} stc_usb_hadr_field_t;
+
+typedef struct stc_usb_heof_field
+{
+  __IO uint16_t EOF0       : 1;
+  __IO uint16_t EOF1       : 1;
+  __IO uint16_t EOF2       : 1;
+  __IO uint16_t EOF3       : 1;
+  __IO uint16_t EOF4       : 1;
+  __IO uint16_t EOF5       : 1;
+  __IO uint16_t EOF6       : 1;
+  __IO uint16_t EOF7       : 1;
+  __IO uint16_t EOF8       : 1;
+  __IO uint16_t EOF9       : 1;
+  __IO uint16_t EOF10      : 1;
+  __IO uint16_t EOF11      : 1;
+  __IO uint16_t EOF12      : 1;
+  __IO uint16_t EOF13      : 1;
+  __IO uint16_t EOF14      : 1;
+  __IO uint16_t EOF15      : 1;
+} stc_usb_heof_field_t;
+
+typedef struct stc_usb_heof0_field
+{
+  __IO  uint8_t EOF00      : 1;
+  __IO  uint8_t EOF01      : 1;
+  __IO  uint8_t EOF02      : 1;
+  __IO  uint8_t EOF03      : 1;
+  __IO  uint8_t EOF04      : 1;
+  __IO  uint8_t EOF05      : 1;
+  __IO  uint8_t EOF06      : 1;
+  __IO  uint8_t EOF07      : 1;
+} stc_usb_heof0_field_t;
+
+typedef struct stc_usb_heof1_field
+{
+  __IO  uint8_t EOF10      : 1;
+  __IO  uint8_t EOF11      : 1;
+  __IO  uint8_t EOF12      : 1;
+  __IO  uint8_t EOF13      : 1;
+  __IO  uint8_t EOF14      : 1;
+  __IO  uint8_t EOF15      : 1;
+} stc_usb_heof1_field_t;
+
+typedef struct stc_usb_hframe_field
+{
+  __IO uint16_t FRAME0     : 1;
+  __IO uint16_t FRAME1     : 1;
+  __IO uint16_t FRAME2     : 1;
+  __IO uint16_t FRAME3     : 1;
+  __IO uint16_t FRAME4     : 1;
+  __IO uint16_t FRAME5     : 1;
+  __IO uint16_t FRAME6     : 1;
+  __IO uint16_t FRAME7     : 1;
+  __IO uint16_t FRAME8     : 1;
+  __IO uint16_t FRAME9     : 1;
+  __IO uint16_t FRAME10    : 1;
+} stc_usb_hframe_field_t;
+
+typedef struct stc_usb_hframe0_field
+{
+  __IO  uint8_t FRAME00    : 1;
+  __IO  uint8_t FRAME01    : 1;
+  __IO  uint8_t FRAME02    : 1;
+  __IO  uint8_t FRAME03    : 1;
+  __IO  uint8_t FRAME04    : 1;
+  __IO  uint8_t FRAME05    : 1;
+  __IO  uint8_t FRAME06    : 1;
+  __IO  uint8_t FRAME07    : 1;
+} stc_usb_hframe0_field_t;
+
+typedef struct stc_usb_hframe1_field
+{
+  __IO  uint8_t FRAME10    : 1;
+  __IO  uint8_t FRAME11    : 1;
+  __IO  uint8_t FRAME12    : 1;
+  __IO  uint8_t FRAME13    : 1;
+} stc_usb_hframe1_field_t;
+
+typedef struct stc_usb_htoken_field
+{
+  __IO  uint8_t ENDPT0     : 1;
+  __IO  uint8_t ENDPT1     : 1;
+  __IO  uint8_t ENDPT2     : 1;
+  __IO  uint8_t ENDPT3     : 1;
+  __IO  uint8_t TKNEN0     : 1;
+  __IO  uint8_t TKNEN1     : 1;
+  __IO  uint8_t TKNEN2     : 1;
+  __IO  uint8_t TGGL       : 1;
+} stc_usb_htoken_field_t;
+
+typedef struct stc_usb_udcc_field
+{
+  __IO uint16_t PWC        : 1;
+  __IO uint16_t RFBK       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t STALCLREN  : 1;
+  __IO uint16_t USTP       : 1;
+  __IO uint16_t HCONX      : 1;
+  __IO uint16_t RESUM      : 1;
+  __IO uint16_t RST        : 1;
+} stc_usb_udcc_field_t;
+
+typedef struct stc_usb_ep0c_field
+{
+  __IO uint16_t PKS00      : 1;
+  __IO uint16_t PKS01      : 1;
+  __IO uint16_t PKS02      : 1;
+  __IO uint16_t PKS03      : 1;
+  __IO uint16_t PKS04      : 1;
+  __IO uint16_t PKS05      : 1;
+  __IO uint16_t PKS06      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+} stc_usb_ep0c_field_t;
+
+typedef struct stc_usb_ep1c_field
+{
+  __IO uint16_t PKS10      : 1;
+  __IO uint16_t PKS11      : 1;
+  __IO uint16_t PKS12      : 1;
+  __IO uint16_t PKS13      : 1;
+  __IO uint16_t PKS14      : 1;
+  __IO uint16_t PKS15      : 1;
+  __IO uint16_t PKS16      : 1;
+  __IO uint16_t PKS17      : 1;
+  __IO uint16_t PKS18      : 1;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep1c_field_t;
+
+typedef struct stc_usb_ep2c_field
+{
+  __IO uint16_t PKS20      : 1;
+  __IO uint16_t PKS21      : 1;
+  __IO uint16_t PKS22      : 1;
+  __IO uint16_t PKS23      : 1;
+  __IO uint16_t PKS24      : 1;
+  __IO uint16_t PKS25      : 1;
+  __IO uint16_t PKS26      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep2c_field_t;
+
+typedef struct stc_usb_ep3c_field
+{
+  __IO uint16_t PKS30      : 1;
+  __IO uint16_t PKS31      : 1;
+  __IO uint16_t PKS32      : 1;
+  __IO uint16_t PKS33      : 1;
+  __IO uint16_t PKS34      : 1;
+  __IO uint16_t PKS35      : 1;
+  __IO uint16_t PKS36      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep3c_field_t;
+
+typedef struct stc_usb_ep4c_field
+{
+  __IO uint16_t PKS40      : 1;
+  __IO uint16_t PKS41      : 1;
+  __IO uint16_t PKS42      : 1;
+  __IO uint16_t PKS43      : 1;
+  __IO uint16_t PKS44      : 1;
+  __IO uint16_t PKS45      : 1;
+  __IO uint16_t PKS46      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep4c_field_t;
+
+typedef struct stc_usb_ep5c_field
+{
+  __IO uint16_t PKS50      : 1;
+  __IO uint16_t PKS51      : 1;
+  __IO uint16_t PKS52      : 1;
+  __IO uint16_t PKS53      : 1;
+  __IO uint16_t PKS54      : 1;
+  __IO uint16_t PKS55      : 1;
+  __IO uint16_t PKS56      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep5c_field_t;
+
+typedef struct stc_usb_tmsp_field
+{
+  __IO uint16_t TMSP0      : 1;
+  __IO uint16_t TMSP1      : 1;
+  __IO uint16_t TMSP2      : 1;
+  __IO uint16_t TMSP3      : 1;
+  __IO uint16_t TMSP4      : 1;
+  __IO uint16_t TMSP5      : 1;
+  __IO uint16_t TMSP6      : 1;
+  __IO uint16_t TMSP7      : 1;
+  __IO uint16_t TMSP8      : 1;
+  __IO uint16_t TMSP9      : 1;
+  __IO uint16_t TMSP10     : 1;
+} stc_usb_tmsp_field_t;
+
+typedef struct stc_usb_udcs_field
+{
+  __IO  uint8_t CONF       : 1;
+  __IO  uint8_t SETP       : 1;
+  __IO  uint8_t WKUP       : 1;
+  __IO  uint8_t BRST       : 1;
+  __IO  uint8_t SOF        : 1;
+  __IO  uint8_t SUSP       : 1;
+} stc_usb_udcs_field_t;
+
+typedef struct stc_usb_udcie_field
+{
+  __IO  uint8_t CONFIE     : 1;
+  __IO  uint8_t CONFN      : 1;
+  __IO  uint8_t WKUPIE     : 1;
+  __IO  uint8_t BRSTIE     : 1;
+  __IO  uint8_t SOFIE      : 1;
+  __IO  uint8_t SUSPIE     : 1;
+} stc_usb_udcie_field_t;
+
+typedef struct stc_usb_ep0is_field
+{
+       uint16_t RESERVED1  : 10;
+  __IO uint16_t DRQI       : 1;
+       uint16_t RESERVED2  : 3;
+  __IO uint16_t DRQIIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0is_field_t;
+
+typedef struct stc_usb_ep0os_field
+{
+  __IO uint16_t SIZE0      : 1;
+  __IO uint16_t SIZE1      : 1;
+  __IO uint16_t SIZE2      : 1;
+  __IO uint16_t SIZE3      : 1;
+  __IO uint16_t SIZE4      : 1;
+  __IO uint16_t SIZE5      : 1;
+  __IO uint16_t SIZE6      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQO       : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQOIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0os_field_t;
+
+typedef struct stc_usb_ep1s_field
+{
+  __IO uint16_t SIZE10     : 1;
+  __IO uint16_t SIZE11     : 1;
+  __IO uint16_t SIZE12     : 1;
+  __IO uint16_t SIZE13     : 1;
+  __IO uint16_t SIZE14     : 1;
+  __IO uint16_t SIZE15     : 1;
+  __IO uint16_t SIZE16     : 1;
+  __IO uint16_t SIZE17     : 1;
+  __IO uint16_t SIZE18     : 1;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep1s_field_t;
+
+typedef struct stc_usb_ep2s_field
+{
+  __IO uint16_t SIZE20     : 1;
+  __IO uint16_t SIZE21     : 1;
+  __IO uint16_t SIZE22     : 1;
+  __IO uint16_t SIZE23     : 1;
+  __IO uint16_t SIZE24     : 1;
+  __IO uint16_t SIZE25     : 1;
+  __IO uint16_t SIZE26     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep2s_field_t;
+
+typedef struct stc_usb_ep4s_field
+{
+  __IO uint16_t SIZE40     : 1;
+  __IO uint16_t SIZE41     : 1;
+  __IO uint16_t SIZE42     : 1;
+  __IO uint16_t SIZE43     : 1;
+  __IO uint16_t SIZE44     : 1;
+  __IO uint16_t SIZE45     : 1;
+  __IO uint16_t SIZE46     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep4s_field_t;
+
+typedef struct stc_usb_ep5s_field
+{
+  __IO uint16_t SIZE50     : 1;
+  __IO uint16_t SIZE51     : 1;
+  __IO uint16_t SIZE52     : 1;
+  __IO uint16_t SIZE53     : 1;
+  __IO uint16_t SIZE54     : 1;
+  __IO uint16_t SIZE55     : 1;
+  __IO uint16_t SIZE56     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep5s_field_t;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMAC_MODULE register bit fields */
+typedef struct stc_dmac_dmacr_field
+{
+       uint32_t RESERVED1  : 24;
+  __IO uint32_t DH0        : 1;
+  __IO uint32_t DH1        : 1;
+  __IO uint32_t DH2        : 1;
+  __IO uint32_t DH3        : 1;
+  __IO uint32_t PR         : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t DS         : 1;
+  __IO uint32_t DE         : 1;
+} stc_dmac_dmacr_field_t;
+
+typedef struct stc_dmac_dmaca0_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca0_field_t;
+
+typedef struct stc_dmac_dmacb0_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb0_field_t;
+
+typedef struct stc_dmac_dmaca1_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca1_field_t;
+
+typedef struct stc_dmac_dmacb1_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb1_field_t;
+
+typedef struct stc_dmac_dmaca2_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca2_field_t;
+
+typedef struct stc_dmac_dmacb2_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb2_field_t;
+
+typedef struct stc_dmac_dmaca3_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca3_field_t;
+
+typedef struct stc_dmac_dmacb3_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb3_field_t;
+
+typedef struct stc_dmac_dmaca4_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca4_field_t;
+
+typedef struct stc_dmac_dmacb4_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb4_field_t;
+
+typedef struct stc_dmac_dmaca5_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca5_field_t;
+
+typedef struct stc_dmac_dmacb5_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb5_field_t;
+
+typedef struct stc_dmac_dmaca6_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca6_field_t;
+
+typedef struct stc_dmac_dmacb6_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb6_field_t;
+
+typedef struct stc_dmac_dmaca7_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca7_field_t;
+
+typedef struct stc_dmac_dmacb7_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb7_field_t;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET_MAC_MODULE register bit fields */
+typedef struct stc_ethernet_mac_mcr_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t RE         : 1;
+  __IO uint32_t TE         : 1;
+  __IO uint32_t DC         : 1;
+  __IO uint32_t BL0        : 1;
+  __IO uint32_t BL1        : 1;
+  __IO uint32_t ACS        : 1;
+  __IO uint32_t LUD        : 1;
+  __IO uint32_t DR         : 1;
+  __IO uint32_t IPC        : 1;
+  __IO uint32_t DM         : 1;
+  __IO uint32_t LM         : 1;
+  __IO uint32_t DO         : 1;
+  __IO uint32_t FES        : 1;
+  __IO uint32_t PS         : 1;
+  __IO uint32_t DCRS       : 1;
+  __IO uint32_t IFG0       : 1;
+  __IO uint32_t IFG1       : 1;
+  __IO uint32_t IFG2       : 1;
+  __IO uint32_t JE         : 1;
+  __IO uint32_t BE         : 1;
+  __IO uint32_t JD         : 1;
+  __IO uint32_t WD         : 1;
+  __IO uint32_t TC         : 1;
+  __IO uint32_t CST        : 1;
+} stc_ethernet_mac_mcr_field_t;
+
+typedef struct stc_ethernet_mac_mffr_field
+{
+  __IO uint32_t PR         : 1;
+  __IO uint32_t HUC        : 1;
+  __IO uint32_t HMC        : 1;
+  __IO uint32_t DAIF       : 1;
+  __IO uint32_t PM         : 1;
+  __IO uint32_t DB         : 1;
+  __IO uint32_t PCF0       : 1;
+  __IO uint32_t PCF1       : 1;
+  __IO uint32_t SAIF       : 1;
+  __IO uint32_t SAF        : 1;
+  __IO uint32_t HPF        : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t RA         : 1;
+} stc_ethernet_mac_mffr_field_t;
+
+typedef struct stc_ethernet_mac_mhtrh_field
+{
+  __IO uint32_t HTH0       : 1;
+  __IO uint32_t HTH1       : 1;
+  __IO uint32_t HTH2       : 1;
+  __IO uint32_t HTH3       : 1;
+  __IO uint32_t HTH4       : 1;
+  __IO uint32_t HTH5       : 1;
+  __IO uint32_t HTH6       : 1;
+  __IO uint32_t HTH7       : 1;
+  __IO uint32_t HTH8       : 1;
+  __IO uint32_t HTH9       : 1;
+  __IO uint32_t HTH10      : 1;
+  __IO uint32_t HTH11      : 1;
+  __IO uint32_t HTH12      : 1;
+  __IO uint32_t HTH13      : 1;
+  __IO uint32_t HTH14      : 1;
+  __IO uint32_t HTH15      : 1;
+  __IO uint32_t HTH16      : 1;
+  __IO uint32_t HTH17      : 1;
+  __IO uint32_t HTH18      : 1;
+  __IO uint32_t HTH19      : 1;
+  __IO uint32_t HTH20      : 1;
+  __IO uint32_t HTH21      : 1;
+  __IO uint32_t HTH22      : 1;
+  __IO uint32_t HTH23      : 1;
+  __IO uint32_t HTH24      : 1;
+  __IO uint32_t HTH25      : 1;
+  __IO uint32_t HTH26      : 1;
+  __IO uint32_t HTH27      : 1;
+  __IO uint32_t HTH28      : 1;
+  __IO uint32_t HTH29      : 1;
+  __IO uint32_t HTH30      : 1;
+  __IO uint32_t HTH31      : 1;
+} stc_ethernet_mac_mhtrh_field_t;
+
+typedef struct stc_ethernet_mac_mhtrl_field
+{
+  __IO uint32_t HTL0       : 1;
+  __IO uint32_t HTL1       : 1;
+  __IO uint32_t HTL2       : 1;
+  __IO uint32_t HTL3       : 1;
+  __IO uint32_t HTL4       : 1;
+  __IO uint32_t HTL5       : 1;
+  __IO uint32_t HTL6       : 1;
+  __IO uint32_t HTL7       : 1;
+  __IO uint32_t HTL8       : 1;
+  __IO uint32_t HTL9       : 1;
+  __IO uint32_t HTL10      : 1;
+  __IO uint32_t HTL11      : 1;
+  __IO uint32_t HTL12      : 1;
+  __IO uint32_t HTL13      : 1;
+  __IO uint32_t HTL14      : 1;
+  __IO uint32_t HTL15      : 1;
+  __IO uint32_t HTL16      : 1;
+  __IO uint32_t HTL17      : 1;
+  __IO uint32_t HTL18      : 1;
+  __IO uint32_t HTL19      : 1;
+  __IO uint32_t HTL20      : 1;
+  __IO uint32_t HTL21      : 1;
+  __IO uint32_t HTL22      : 1;
+  __IO uint32_t HTL23      : 1;
+  __IO uint32_t HTL24      : 1;
+  __IO uint32_t HTL25      : 1;
+  __IO uint32_t HTL26      : 1;
+  __IO uint32_t HTL27      : 1;
+  __IO uint32_t HTL28      : 1;
+  __IO uint32_t HTL29      : 1;
+  __IO uint32_t HTL30      : 1;
+  __IO uint32_t HTL31      : 1;
+} stc_ethernet_mac_mhtrl_field_t;
+
+typedef struct stc_ethernet_mac_gar_field
+{
+  __IO uint32_t GB         : 1;
+  __IO uint32_t GW         : 1;
+  __IO uint32_t CR0        : 1;
+  __IO uint32_t CR1        : 1;
+  __IO uint32_t CR2        : 1;
+  __IO uint32_t CR3        : 1;
+  __IO uint32_t GR0        : 1;
+  __IO uint32_t GR1        : 1;
+  __IO uint32_t GR2        : 1;
+  __IO uint32_t GR3        : 1;
+  __IO uint32_t GR4        : 1;
+  __IO uint32_t PA0        : 1;
+  __IO uint32_t PA1        : 1;
+  __IO uint32_t PA2        : 1;
+  __IO uint32_t PA3        : 1;
+  __IO uint32_t PA4        : 1;
+} stc_ethernet_mac_gar_field_t;
+
+typedef struct stc_ethernet_mac_gdr_field
+{
+  __IO uint32_t GD0        : 1;
+  __IO uint32_t GD1        : 1;
+  __IO uint32_t GD2        : 1;
+  __IO uint32_t GD3        : 1;
+  __IO uint32_t GD4        : 1;
+  __IO uint32_t GD5        : 1;
+  __IO uint32_t GD6        : 1;
+  __IO uint32_t GD7        : 1;
+  __IO uint32_t GD8        : 1;
+  __IO uint32_t GD9        : 1;
+  __IO uint32_t GD10       : 1;
+  __IO uint32_t GD11       : 1;
+  __IO uint32_t GD12       : 1;
+  __IO uint32_t GD13       : 1;
+  __IO uint32_t GD14       : 1;
+  __IO uint32_t GD15       : 1;
+} stc_ethernet_mac_gdr_field_t;
+
+typedef struct stc_ethernet_mac_fcr_field
+{
+  __IO uint32_t FCB_BPA    : 1;
+  __IO uint32_t TFE        : 1;
+  __IO uint32_t RFE        : 1;
+  __IO uint32_t UP         : 1;
+  __IO uint32_t PLT0       : 1;
+  __IO uint32_t PLT1       : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t DZPQ       : 1;
+       uint32_t RESERVED2  : 8;
+  __IO uint32_t PT0        : 1;
+  __IO uint32_t PT1        : 1;
+  __IO uint32_t PT2        : 1;
+  __IO uint32_t PT3        : 1;
+  __IO uint32_t PT4        : 1;
+  __IO uint32_t PT5        : 1;
+  __IO uint32_t PT6        : 1;
+  __IO uint32_t PT7        : 1;
+  __IO uint32_t PT8        : 1;
+  __IO uint32_t PT9        : 1;
+  __IO uint32_t PT10       : 1;
+  __IO uint32_t PT11       : 1;
+  __IO uint32_t PT12       : 1;
+  __IO uint32_t PT13       : 1;
+  __IO uint32_t PT14       : 1;
+  __IO uint32_t PT15       : 1;
+} stc_ethernet_mac_fcr_field_t;
+
+typedef struct stc_ethernet_mac_vtr_field
+{
+  __IO uint32_t VL0        : 1;
+  __IO uint32_t VL1        : 1;
+  __IO uint32_t VL2        : 1;
+  __IO uint32_t VL3        : 1;
+  __IO uint32_t VL4        : 1;
+  __IO uint32_t VL5        : 1;
+  __IO uint32_t VL6        : 1;
+  __IO uint32_t VL7        : 1;
+  __IO uint32_t VL8        : 1;
+  __IO uint32_t VL9        : 1;
+  __IO uint32_t VL10       : 1;
+  __IO uint32_t VL11       : 1;
+  __IO uint32_t VL12       : 1;
+  __IO uint32_t VL13       : 1;
+  __IO uint32_t VL14       : 1;
+  __IO uint32_t VL15       : 1;
+  __IO uint32_t ETV        : 1;
+} stc_ethernet_mac_vtr_field_t;
+
+typedef struct stc_ethernet_mac_rwffr_field
+{
+  __IO uint32_t RWFFR0     : 1;
+  __IO uint32_t RWFFR1     : 1;
+  __IO uint32_t RWFFR2     : 1;
+  __IO uint32_t RWFFR3     : 1;
+  __IO uint32_t RWFFR4     : 1;
+  __IO uint32_t RWFFR5     : 1;
+  __IO uint32_t RWFFR6     : 1;
+  __IO uint32_t RWFFR7     : 1;
+  __IO uint32_t RWFFR8     : 1;
+  __IO uint32_t RWFFR9     : 1;
+  __IO uint32_t RWFFR10    : 1;
+  __IO uint32_t RWFFR11    : 1;
+  __IO uint32_t RWFFR12    : 1;
+  __IO uint32_t RWFFR13    : 1;
+  __IO uint32_t RWFFR14    : 1;
+  __IO uint32_t RWFFR15    : 1;
+  __IO uint32_t RWFFR16    : 1;
+  __IO uint32_t RWFFR17    : 1;
+  __IO uint32_t RWFFR18    : 1;
+  __IO uint32_t RWFFR19    : 1;
+  __IO uint32_t RWFFR20    : 1;
+  __IO uint32_t RWFFR21    : 1;
+  __IO uint32_t RWFFR22    : 1;
+  __IO uint32_t RWFFR23    : 1;
+  __IO uint32_t RWFFR24    : 1;
+  __IO uint32_t RWFFR25    : 1;
+  __IO uint32_t RWFFR26    : 1;
+  __IO uint32_t RWFFR27    : 1;
+  __IO uint32_t RWFFR28    : 1;
+  __IO uint32_t RWFFR29    : 1;
+  __IO uint32_t RWFFR30    : 1;
+  __IO uint32_t RWFFR31    : 1;
+} stc_ethernet_mac_rwffr_field_t;
+
+typedef struct stc_ethernet_mac_pmtr_field
+{
+  __IO uint32_t PD         : 1;
+  __IO uint32_t MPE        : 1;
+  __IO uint32_t WFE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t MPR        : 1;
+  __IO uint32_t WPR        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t GU         : 1;
+       uint32_t RESERVED3  :21;
+  __IO uint32_t RWFFRPR    : 1;
+} stc_ethernet_mac_pmtr_field_t;
+
+typedef struct stc_ethernet_mac_lpicsr_field
+{
+  __IO uint32_t TLPIEN     : 1;
+  __IO uint32_t TLPIEX     : 1;
+  __IO uint32_t RLPIEN     : 1;
+  __IO uint32_t RLPIEX     : 1;
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t TLPIST     : 1;
+  __IO uint32_t RLPIST     : 1;
+       uint32_t RESERVED2  : 6;
+  __IO uint32_t LPIEN      : 1;
+  __IO uint32_t PLS        : 1;
+  __IO uint32_t PLSEN      : 1;
+  __IO uint32_t LPITXA     : 1;
+} stc_ethernet_mac_lpicsr_field_t;
+
+typedef struct stc_ethernet_mac_lpitcr_field
+{
+  __IO uint32_t TWT0       : 1;
+  __IO uint32_t TWT1       : 1;
+  __IO uint32_t TWT2       : 1;
+  __IO uint32_t TWT3       : 1;
+  __IO uint32_t TWT4       : 1;
+  __IO uint32_t TWT5       : 1;
+  __IO uint32_t TWT6       : 1;
+  __IO uint32_t TWT7       : 1;
+  __IO uint32_t TWT8       : 1;
+  __IO uint32_t TWT9       : 1;
+  __IO uint32_t TWT10      : 1;
+  __IO uint32_t TWT11      : 1;
+  __IO uint32_t TWT12      : 1;
+  __IO uint32_t TWT13      : 1;
+  __IO uint32_t TWT14      : 1;
+  __IO uint32_t TWT15      : 1;
+  __IO uint32_t LIT0       : 1;
+  __IO uint32_t LIT1       : 1;
+  __IO uint32_t LIT2       : 1;
+  __IO uint32_t LIT3       : 1;
+  __IO uint32_t LIT4       : 1;
+  __IO uint32_t LIT5       : 1;
+  __IO uint32_t LIT6       : 1;
+  __IO uint32_t LIT7       : 1;
+  __IO uint32_t LIT8       : 1;
+  __IO uint32_t LIT9       : 1;
+} stc_ethernet_mac_lpitcr_field_t;
+
+typedef struct stc_ethernet_mac_isr_field
+{
+  __IO uint32_t RGIS       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIS        : 1;
+  __IO uint32_t MIS        : 1;
+  __IO uint32_t RIS        : 1;
+  __IO uint32_t TIS        : 1;
+  __IO uint32_t COIS       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t TSIS       : 1;
+  __IO uint32_t LPIIS      : 1;
+} stc_ethernet_mac_isr_field_t;
+
+typedef struct stc_ethernet_mac_imr_field
+{
+  __IO uint32_t RGIM       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIM        : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t TSIM       : 1;
+  __IO uint32_t LPIIM      : 1;
+} stc_ethernet_mac_imr_field_t;
+
+typedef struct stc_ethernet_mac_mar0h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  :15;
+  __IO uint32_t MO         : 1;
+} stc_ethernet_mac_mar0h_field_t;
+
+typedef struct stc_ethernet_mac_mar0l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar0l_field_t;
+
+typedef struct stc_ethernet_mac_mar1h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar1h_field_t;
+
+typedef struct stc_ethernet_mac_mar1l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar1l_field_t;
+
+typedef struct stc_ethernet_mac_mar2h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar2h_field_t;
+
+typedef struct stc_ethernet_mac_mar2l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar2l_field_t;
+
+typedef struct stc_ethernet_mac_mar3h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar3h_field_t;
+
+typedef struct stc_ethernet_mac_mar3l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar3l_field_t;
+
+typedef struct stc_ethernet_mac_mar4h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar4h_field_t;
+
+typedef struct stc_ethernet_mac_mar4l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar4l_field_t;
+
+typedef struct stc_ethernet_mac_mar5h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar5h_field_t;
+
+typedef struct stc_ethernet_mac_mar5l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar5l_field_t;
+
+typedef struct stc_ethernet_mac_mar6h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar6h_field_t;
+
+typedef struct stc_ethernet_mac_mar6l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar6l_field_t;
+
+typedef struct stc_ethernet_mac_mar7h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar7h_field_t;
+
+typedef struct stc_ethernet_mac_mar7l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar7l_field_t;
+
+typedef struct stc_ethernet_mac_mar8h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar8h_field_t;
+
+typedef struct stc_ethernet_mac_mar8l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar8l_field_t;
+
+typedef struct stc_ethernet_mac_mar9h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar9h_field_t;
+
+typedef struct stc_ethernet_mac_mar9l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar9l_field_t;
+
+typedef struct stc_ethernet_mac_mar10h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar10h_field_t;
+
+typedef struct stc_ethernet_mac_mar10l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar10l_field_t;
+
+typedef struct stc_ethernet_mac_mar11h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar11h_field_t;
+
+typedef struct stc_ethernet_mac_mar11l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar11l_field_t;
+
+typedef struct stc_ethernet_mac_mar12h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar12h_field_t;
+
+typedef struct stc_ethernet_mac_mar12l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar12l_field_t;
+
+typedef struct stc_ethernet_mac_mar13h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar13h_field_t;
+
+typedef struct stc_ethernet_mac_mar13l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar13l_field_t;
+
+typedef struct stc_ethernet_mac_mar14h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar14h_field_t;
+
+typedef struct stc_ethernet_mac_mar14l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar14l_field_t;
+
+typedef struct stc_ethernet_mac_mar15h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar15h_field_t;
+
+typedef struct stc_ethernet_mac_mar15l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar15l_field_t;
+
+typedef struct stc_ethernet_mac_rgsr_field
+{
+  __IO uint32_t LM         : 1;
+  __IO uint32_t LSP0       : 1;
+  __IO uint32_t LSP1       : 1;
+  __IO uint32_t LS         : 1;
+} stc_ethernet_mac_rgsr_field_t;
+
+typedef struct stc_ethernet_mac_tscr_field
+{
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TFCU       : 1;
+  __IO uint32_t TSI        : 1;
+  __IO uint32_t TSU        : 1;
+  __IO uint32_t TITE       : 1;
+  __IO uint32_t TARU       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TSEA       : 1;
+  __IO uint32_t TSDB       : 1;
+  __IO uint32_t TSV2E      : 1;
+  __IO uint32_t TETSP      : 1;
+  __IO uint32_t TSIP6E     : 1;
+  __IO uint32_t TSIP4E     : 1;
+  __IO uint32_t TETSEM     : 1;
+  __IO uint32_t TSMRM      : 1;
+  __IO uint32_t TSPS0      : 1;
+  __IO uint32_t TSPS1      : 1;
+  __IO uint32_t TSENMF     : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t ATSFC      : 1;
+} stc_ethernet_mac_tscr_field_t;
+
+typedef struct stc_ethernet_mac_ssir_field
+{
+  __IO uint32_t SSINC0     : 1;
+  __IO uint32_t SSINC1     : 1;
+  __IO uint32_t SSINC2     : 1;
+  __IO uint32_t SSINC3     : 1;
+  __IO uint32_t SSINC4     : 1;
+  __IO uint32_t SSINC5     : 1;
+  __IO uint32_t SSINC6     : 1;
+  __IO uint32_t SSINC7     : 1;
+} stc_ethernet_mac_ssir_field_t;
+
+typedef struct stc_ethernet_mac_stsr_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsr_field_t;
+
+typedef struct stc_ethernet_mac_stnr_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+} stc_ethernet_mac_stnr_field_t;
+
+typedef struct stc_ethernet_mac_stsur_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsur_field_t;
+
+typedef struct stc_ethernet_mac_stnur_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+  __IO uint32_t ADDSUB     : 1;
+} stc_ethernet_mac_stnur_field_t;
+
+typedef struct stc_ethernet_mac_tsar_field
+{
+  __IO uint32_t TSAR0      : 1;
+  __IO uint32_t TSAR1      : 1;
+  __IO uint32_t TSAR2      : 1;
+  __IO uint32_t TSAR3      : 1;
+  __IO uint32_t TSAR4      : 1;
+  __IO uint32_t TSAR5      : 1;
+  __IO uint32_t TSAR6      : 1;
+  __IO uint32_t TSAR7      : 1;
+  __IO uint32_t TSAR8      : 1;
+  __IO uint32_t TSAR9      : 1;
+  __IO uint32_t TSAR10     : 1;
+  __IO uint32_t TSAR11     : 1;
+  __IO uint32_t TSAR12     : 1;
+  __IO uint32_t TSAR13     : 1;
+  __IO uint32_t TSAR14     : 1;
+  __IO uint32_t TSAR15     : 1;
+  __IO uint32_t TSAR16     : 1;
+  __IO uint32_t TSAR17     : 1;
+  __IO uint32_t TSAR18     : 1;
+  __IO uint32_t TSAR19     : 1;
+  __IO uint32_t TSAR20     : 1;
+  __IO uint32_t TSAR21     : 1;
+  __IO uint32_t TSAR22     : 1;
+  __IO uint32_t TSAR23     : 1;
+  __IO uint32_t TSAR24     : 1;
+  __IO uint32_t TSAR25     : 1;
+  __IO uint32_t TSAR26     : 1;
+  __IO uint32_t TSAR27     : 1;
+  __IO uint32_t TSAR28     : 1;
+  __IO uint32_t TSAR29     : 1;
+  __IO uint32_t TSAR30     : 1;
+  __IO uint32_t TSAR31     : 1;
+} stc_ethernet_mac_tsar_field_t;
+
+typedef struct stc_ethernet_mac_ttsr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+  __IO uint32_t TSTR31     : 1;
+} stc_ethernet_mac_ttsr_field_t;
+
+typedef struct stc_ethernet_mac_ttnr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+} stc_ethernet_mac_ttnr_field_t;
+
+typedef struct stc_ethernet_mac_sthwsr_field
+{
+  __IO uint32_t TSHWR0     : 1;
+  __IO uint32_t TSHWR1     : 1;
+  __IO uint32_t TSHWR2     : 1;
+  __IO uint32_t TSHWR3     : 1;
+  __IO uint32_t TSHWR4     : 1;
+  __IO uint32_t TSHWR5     : 1;
+  __IO uint32_t TSHWR6     : 1;
+  __IO uint32_t TSHWR7     : 1;
+  __IO uint32_t TSHWR8     : 1;
+  __IO uint32_t TSHWR9     : 1;
+  __IO uint32_t TSHWR10    : 1;
+  __IO uint32_t TSHWR11    : 1;
+  __IO uint32_t TSHWR12    : 1;
+  __IO uint32_t TSHWR13    : 1;
+  __IO uint32_t TSHWR14    : 1;
+  __IO uint32_t TSHWR15    : 1;
+} stc_ethernet_mac_sthwsr_field_t;
+
+typedef struct stc_ethernet_mac_tsr_field
+{
+  __IO uint32_t TSSOVF     : 1;
+  __IO uint32_t TSTART     : 1;
+  __IO uint32_t ATSTS      : 1;
+  __IO uint32_t TRGTER     : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t ATSSTM     : 1;
+  __IO uint32_t ATSNS0     : 1;
+  __IO uint32_t ATSNS1     : 1;
+  __IO uint32_t ATSNS2     : 1;
+} stc_ethernet_mac_tsr_field_t;
+
+typedef struct stc_ethernet_mac_ppscr_field
+{
+  __IO uint32_t PPSCTRL0   : 1;
+  __IO uint32_t PPSCTRL1   : 1;
+  __IO uint32_t PPSCTRL2   : 1;
+  __IO uint32_t PPSCTRL3   : 1;
+} stc_ethernet_mac_ppscr_field_t;
+
+typedef struct stc_ethernet_mac_atnr_field
+{
+  __IO uint32_t ATN0       : 1;
+  __IO uint32_t ATN1       : 1;
+  __IO uint32_t ATN2       : 1;
+  __IO uint32_t ATN3       : 1;
+  __IO uint32_t ATN4       : 1;
+  __IO uint32_t ATN5       : 1;
+  __IO uint32_t ATN6       : 1;
+  __IO uint32_t ATN7       : 1;
+  __IO uint32_t ATN8       : 1;
+  __IO uint32_t ATN9       : 1;
+  __IO uint32_t ATN10      : 1;
+  __IO uint32_t ATN11      : 1;
+  __IO uint32_t ATN12      : 1;
+  __IO uint32_t ATN13      : 1;
+  __IO uint32_t ATN14      : 1;
+  __IO uint32_t ATN15      : 1;
+  __IO uint32_t ATN16      : 1;
+  __IO uint32_t ATN17      : 1;
+  __IO uint32_t ATN18      : 1;
+  __IO uint32_t ATN19      : 1;
+  __IO uint32_t ATN20      : 1;
+  __IO uint32_t ATN21      : 1;
+  __IO uint32_t ATN22      : 1;
+  __IO uint32_t ATN23      : 1;
+  __IO uint32_t ATN24      : 1;
+  __IO uint32_t ATN25      : 1;
+  __IO uint32_t ATN26      : 1;
+  __IO uint32_t ATN27      : 1;
+  __IO uint32_t ATN28      : 1;
+  __IO uint32_t ATN29      : 1;
+  __IO uint32_t ATN30      : 1;
+} stc_ethernet_mac_atnr_field_t;
+
+typedef struct stc_ethernet_mac_atsr_field
+{
+  __IO uint32_t ATS0       : 1;
+  __IO uint32_t ATS1       : 1;
+  __IO uint32_t ATS2       : 1;
+  __IO uint32_t ATS3       : 1;
+  __IO uint32_t ATS4       : 1;
+  __IO uint32_t ATS5       : 1;
+  __IO uint32_t ATS6       : 1;
+  __IO uint32_t ATS7       : 1;
+  __IO uint32_t ATS8       : 1;
+  __IO uint32_t ATS9       : 1;
+  __IO uint32_t ATS10      : 1;
+  __IO uint32_t ATS11      : 1;
+  __IO uint32_t ATS12      : 1;
+  __IO uint32_t ATS13      : 1;
+  __IO uint32_t ATS14      : 1;
+  __IO uint32_t ATS15      : 1;
+  __IO uint32_t ATS16      : 1;
+  __IO uint32_t ATS17      : 1;
+  __IO uint32_t ATS18      : 1;
+  __IO uint32_t ATS19      : 1;
+  __IO uint32_t ATS20      : 1;
+  __IO uint32_t ATS21      : 1;
+  __IO uint32_t ATS22      : 1;
+  __IO uint32_t ATS23      : 1;
+  __IO uint32_t ATS24      : 1;
+  __IO uint32_t ATS25      : 1;
+  __IO uint32_t ATS26      : 1;
+  __IO uint32_t ATS27      : 1;
+  __IO uint32_t ATS28      : 1;
+  __IO uint32_t ATS29      : 1;
+  __IO uint32_t ATS30      : 1;
+  __IO uint32_t ATS31      : 1;
+} stc_ethernet_mac_atsr_field_t;
+
+typedef struct stc_ethernet_mac_mar16h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar16h_field_t;
+
+typedef struct stc_ethernet_mac_mar16l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar16l_field_t;
+
+typedef struct stc_ethernet_mac_mar17h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar17h_field_t;
+
+typedef struct stc_ethernet_mac_mar17l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar17l_field_t;
+
+typedef struct stc_ethernet_mac_mar18h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar18h_field_t;
+
+typedef struct stc_ethernet_mac_mar18l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar18l_field_t;
+
+typedef struct stc_ethernet_mac_mar19h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar19h_field_t;
+
+typedef struct stc_ethernet_mac_mar19l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar19l_field_t;
+
+typedef struct stc_ethernet_mac_mar20h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar20h_field_t;
+
+typedef struct stc_ethernet_mac_mar20l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar20l_field_t;
+
+typedef struct stc_ethernet_mac_mar21h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar21h_field_t;
+
+typedef struct stc_ethernet_mac_mar21l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar21l_field_t;
+
+typedef struct stc_ethernet_mac_mar22h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar22h_field_t;
+
+typedef struct stc_ethernet_mac_mar22l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar22l_field_t;
+
+typedef struct stc_ethernet_mac_mar23h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar23h_field_t;
+
+typedef struct stc_ethernet_mac_mar23l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar23l_field_t;
+
+typedef struct stc_ethernet_mac_mar24h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar24h_field_t;
+
+typedef struct stc_ethernet_mac_mar24l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar24l_field_t;
+
+typedef struct stc_ethernet_mac_mar25h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar25h_field_t;
+
+typedef struct stc_ethernet_mac_mar25l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar25l_field_t;
+
+typedef struct stc_ethernet_mac_mar26h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar26h_field_t;
+
+typedef struct stc_ethernet_mac_mar26l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar26l_field_t;
+
+typedef struct stc_ethernet_mac_mar27h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar27h_field_t;
+
+typedef struct stc_ethernet_mac_mar27l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar27l_field_t;
+
+typedef struct stc_ethernet_mac_mar28h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar28h_field_t;
+
+typedef struct stc_ethernet_mac_mar28l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar28l_field_t;
+
+typedef struct stc_ethernet_mac_mar29h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar29h_field_t;
+
+typedef struct stc_ethernet_mac_mar29l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar29l_field_t;
+
+typedef struct stc_ethernet_mac_mar30h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar30h_field_t;
+
+typedef struct stc_ethernet_mac_mar30l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar30l_field_t;
+
+typedef struct stc_ethernet_mac_mar31h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar31h_field_t;
+
+typedef struct stc_ethernet_mac_mar31l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar31l_field_t;
+
+typedef struct stc_ethernet_mac_bmr_field
+{
+  __IO uint32_t SWR        : 1;
+  __IO uint32_t DA         : 1;
+  __IO uint32_t DSL0       : 1;
+  __IO uint32_t DSL1       : 1;
+  __IO uint32_t DSL2       : 1;
+  __IO uint32_t DSL3       : 1;
+  __IO uint32_t DSL4       : 1;
+  __IO uint32_t ATDS       : 1;
+  __IO uint32_t PBL0       : 1;
+  __IO uint32_t PBL1       : 1;
+  __IO uint32_t PBL2       : 1;
+  __IO uint32_t PBL3       : 1;
+  __IO uint32_t PBL4       : 1;
+  __IO uint32_t PBL5       : 1;
+  __IO uint32_t PR0        : 1;
+  __IO uint32_t PR1        : 1;
+  __IO uint32_t FB         : 1;
+  __IO uint32_t RPBL0      : 1;
+  __IO uint32_t RPBL1      : 1;
+  __IO uint32_t RPBL2      : 1;
+  __IO uint32_t RPBL3      : 1;
+  __IO uint32_t RPBL4      : 1;
+  __IO uint32_t RPBL5      : 1;
+  __IO uint32_t USP        : 1;
+  __IO uint32_t _8XPBL     : 1;
+  __IO uint32_t AAL        : 1;
+  __IO uint32_t MB         : 1;
+  __IO uint32_t TXPR       : 1;
+} stc_ethernet_mac_bmr_field_t;
+
+typedef struct stc_ethernet_mac_tpdr_field
+{
+  __IO uint32_t TPD0       : 1;
+  __IO uint32_t TPD1       : 1;
+  __IO uint32_t TPD2       : 1;
+  __IO uint32_t TPD3       : 1;
+  __IO uint32_t TPD4       : 1;
+  __IO uint32_t TPD5       : 1;
+  __IO uint32_t TPD6       : 1;
+  __IO uint32_t TPD7       : 1;
+  __IO uint32_t TPD8       : 1;
+  __IO uint32_t TPD9       : 1;
+  __IO uint32_t TPD10      : 1;
+  __IO uint32_t TPD11      : 1;
+  __IO uint32_t TPD12      : 1;
+  __IO uint32_t TPD13      : 1;
+  __IO uint32_t TPD14      : 1;
+  __IO uint32_t TPD15      : 1;
+  __IO uint32_t TPD16      : 1;
+  __IO uint32_t TPD17      : 1;
+  __IO uint32_t TPD18      : 1;
+  __IO uint32_t TPD19      : 1;
+  __IO uint32_t TPD20      : 1;
+  __IO uint32_t TPD21      : 1;
+  __IO uint32_t TPD22      : 1;
+  __IO uint32_t TPD23      : 1;
+  __IO uint32_t TPD24      : 1;
+  __IO uint32_t TPD25      : 1;
+  __IO uint32_t TPD26      : 1;
+  __IO uint32_t TPD27      : 1;
+  __IO uint32_t TPD28      : 1;
+  __IO uint32_t TPD29      : 1;
+  __IO uint32_t TPD30      : 1;
+  __IO uint32_t TPD31      : 1;
+} stc_ethernet_mac_tpdr_field_t;
+
+typedef struct stc_ethernet_mac_rpdr_field
+{
+  __IO uint32_t RPD0       : 1;
+  __IO uint32_t RPD1       : 1;
+  __IO uint32_t RPD2       : 1;
+  __IO uint32_t RPD3       : 1;
+  __IO uint32_t RPD4       : 1;
+  __IO uint32_t RPD5       : 1;
+  __IO uint32_t RPD6       : 1;
+  __IO uint32_t RPD7       : 1;
+  __IO uint32_t RPD8       : 1;
+  __IO uint32_t RPD9       : 1;
+  __IO uint32_t RPD10      : 1;
+  __IO uint32_t RPD11      : 1;
+  __IO uint32_t RPD12      : 1;
+  __IO uint32_t RPD13      : 1;
+  __IO uint32_t RPD14      : 1;
+  __IO uint32_t RPD15      : 1;
+  __IO uint32_t RPD16      : 1;
+  __IO uint32_t RPD17      : 1;
+  __IO uint32_t RPD18      : 1;
+  __IO uint32_t RPD19      : 1;
+  __IO uint32_t RPD20      : 1;
+  __IO uint32_t RPD21      : 1;
+  __IO uint32_t RPD22      : 1;
+  __IO uint32_t RPD23      : 1;
+  __IO uint32_t RPD24      : 1;
+  __IO uint32_t RPD25      : 1;
+  __IO uint32_t RPD26      : 1;
+  __IO uint32_t RPD27      : 1;
+  __IO uint32_t RPD28      : 1;
+  __IO uint32_t RPD29      : 1;
+  __IO uint32_t RPD30      : 1;
+  __IO uint32_t RPD31      : 1;
+} stc_ethernet_mac_rpdr_field_t;
+
+typedef struct stc_ethernet_mac_rdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t SRL2       : 1;
+  __IO uint32_t SRL3       : 1;
+  __IO uint32_t SRL4       : 1;
+  __IO uint32_t SRL5       : 1;
+  __IO uint32_t SRL6       : 1;
+  __IO uint32_t SRL7       : 1;
+  __IO uint32_t SRL8       : 1;
+  __IO uint32_t SRL9       : 1;
+  __IO uint32_t SRL10      : 1;
+  __IO uint32_t SRL11      : 1;
+  __IO uint32_t SRL12      : 1;
+  __IO uint32_t SRL13      : 1;
+  __IO uint32_t SRL14      : 1;
+  __IO uint32_t SRL15      : 1;
+  __IO uint32_t SRL16      : 1;
+  __IO uint32_t SRL17      : 1;
+  __IO uint32_t SRL18      : 1;
+  __IO uint32_t SRL19      : 1;
+  __IO uint32_t SRL20      : 1;
+  __IO uint32_t SRL21      : 1;
+  __IO uint32_t SRL22      : 1;
+  __IO uint32_t SRL23      : 1;
+  __IO uint32_t SRL24      : 1;
+  __IO uint32_t SRL25      : 1;
+  __IO uint32_t SRL26      : 1;
+  __IO uint32_t SRL27      : 1;
+  __IO uint32_t SRL28      : 1;
+  __IO uint32_t SRL29      : 1;
+  __IO uint32_t SRL30      : 1;
+  __IO uint32_t SRL31      : 1;
+} stc_ethernet_mac_rdlar_field_t;
+
+typedef struct stc_ethernet_mac_tdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t STL2       : 1;
+  __IO uint32_t STL3       : 1;
+  __IO uint32_t STL4       : 1;
+  __IO uint32_t STL5       : 1;
+  __IO uint32_t STL6       : 1;
+  __IO uint32_t STL7       : 1;
+  __IO uint32_t STL8       : 1;
+  __IO uint32_t STL9       : 1;
+  __IO uint32_t STL10      : 1;
+  __IO uint32_t STL11      : 1;
+  __IO uint32_t STL12      : 1;
+  __IO uint32_t STL13      : 1;
+  __IO uint32_t STL14      : 1;
+  __IO uint32_t STL15      : 1;
+  __IO uint32_t STL16      : 1;
+  __IO uint32_t STL17      : 1;
+  __IO uint32_t STL18      : 1;
+  __IO uint32_t STL19      : 1;
+  __IO uint32_t STL20      : 1;
+  __IO uint32_t STL21      : 1;
+  __IO uint32_t STL22      : 1;
+  __IO uint32_t STL23      : 1;
+  __IO uint32_t STL24      : 1;
+  __IO uint32_t STL25      : 1;
+  __IO uint32_t STL26      : 1;
+  __IO uint32_t STL27      : 1;
+  __IO uint32_t STL28      : 1;
+  __IO uint32_t STL29      : 1;
+  __IO uint32_t STL30      : 1;
+  __IO uint32_t STL31      : 1;
+} stc_ethernet_mac_tdlar_field_t;
+
+typedef struct stc_ethernet_mac_sr_field
+{
+  __IO uint32_t TI         : 1;
+  __IO uint32_t TPS        : 1;
+  __IO uint32_t TU         : 1;
+  __IO uint32_t TJT        : 1;
+  __IO uint32_t OVF        : 1;
+  __IO uint32_t UNF        : 1;
+  __IO uint32_t RI         : 1;
+  __IO uint32_t RU         : 1;
+  __IO uint32_t RPS        : 1;
+  __IO uint32_t RWT        : 1;
+  __IO uint32_t ETI        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBI        : 1;
+  __IO uint32_t ERI        : 1;
+  __IO uint32_t AIS        : 1;
+  __IO uint32_t NIS        : 1;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+  __IO uint32_t TS0        : 1;
+  __IO uint32_t TS1        : 1;
+  __IO uint32_t TS2        : 1;
+  __IO uint32_t EB0        : 1;
+  __IO uint32_t EB1        : 1;
+  __IO uint32_t EB2        : 1;
+  __IO uint32_t GLI        : 1;
+  __IO uint32_t GMI        : 1;
+  __IO uint32_t GPI        : 1;
+  __IO uint32_t TTI        : 1;
+  __IO uint32_t GLPII      : 1;
+} stc_ethernet_mac_sr_field_t;
+
+typedef struct stc_ethernet_mac_omr_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t SR         : 1;
+  __IO uint32_t OSF        : 1;
+  __IO uint32_t RTC0       : 1;
+  __IO uint32_t RTC1       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t FUF        : 1;
+  __IO uint32_t FEF        : 1;
+       uint32_t RESERVED3  : 5;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t TTC0       : 1;
+  __IO uint32_t TTC1       : 1;
+  __IO uint32_t TTC2       : 1;
+       uint32_t RESERVED4  : 3;
+  __IO uint32_t FTF        : 1;
+  __IO uint32_t TSF        : 1;
+       uint32_t RESERVED5  : 2;
+  __IO uint32_t DFF        : 1;
+  __IO uint32_t RSF        : 1;
+  __IO uint32_t DT         : 1;
+} stc_ethernet_mac_omr_field_t;
+
+typedef struct stc_ethernet_mac_ier_field
+{
+  __IO uint32_t TIE        : 1;
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TUE        : 1;
+  __IO uint32_t TJE        : 1;
+  __IO uint32_t OVE        : 1;
+  __IO uint32_t UNE        : 1;
+  __IO uint32_t RIE        : 1;
+  __IO uint32_t RUE        : 1;
+  __IO uint32_t RSE        : 1;
+  __IO uint32_t RWE        : 1;
+  __IO uint32_t ETE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBE        : 1;
+  __IO uint32_t ERE        : 1;
+  __IO uint32_t AIE        : 1;
+  __IO uint32_t NIE        : 1;
+} stc_ethernet_mac_ier_field_t;
+
+typedef struct stc_ethernet_mac_mfbocr_field
+{
+  __IO uint32_t NMFH0      : 1;
+  __IO uint32_t NMFH1      : 1;
+  __IO uint32_t NMFH2      : 1;
+  __IO uint32_t NMFH3      : 1;
+  __IO uint32_t NMFH4      : 1;
+  __IO uint32_t NMFH5      : 1;
+  __IO uint32_t NMFH6      : 1;
+  __IO uint32_t NMFH7      : 1;
+  __IO uint32_t NMFH8      : 1;
+  __IO uint32_t NMFH9      : 1;
+  __IO uint32_t NMFH10     : 1;
+  __IO uint32_t NMFH11     : 1;
+  __IO uint32_t NMFH12     : 1;
+  __IO uint32_t NMFH13     : 1;
+  __IO uint32_t NMFH14     : 1;
+  __IO uint32_t NMFH15     : 1;
+  __IO uint32_t ONMFH      : 1;
+  __IO uint32_t NMFF0      : 1;
+  __IO uint32_t NMFF1      : 1;
+  __IO uint32_t NMFF2      : 1;
+  __IO uint32_t NMFF3      : 1;
+  __IO uint32_t NMFF4      : 1;
+  __IO uint32_t NMFF5      : 1;
+  __IO uint32_t NMFF6      : 1;
+  __IO uint32_t NMFF7      : 1;
+  __IO uint32_t NMFF8      : 1;
+  __IO uint32_t NMFF9      : 1;
+  __IO uint32_t NMFF10     : 1;
+  __IO uint32_t ONMFF      : 1;
+} stc_ethernet_mac_mfbocr_field_t;
+
+typedef struct stc_ethernet_mac_riwtr_field
+{
+  __IO uint32_t RIWT0      : 1;
+  __IO uint32_t RIWT1      : 1;
+  __IO uint32_t RIWT2      : 1;
+  __IO uint32_t RIWT3      : 1;
+  __IO uint32_t RIWT4      : 1;
+  __IO uint32_t RIWT5      : 1;
+  __IO uint32_t RIWT6      : 1;
+  __IO uint32_t RIWT7      : 1;
+} stc_ethernet_mac_riwtr_field_t;
+
+typedef struct stc_ethernet_mac_ahbsr_field
+{
+  __IO uint32_t AHBS       : 1;
+} stc_ethernet_mac_ahbsr_field_t;
+
+typedef struct stc_ethernet_mac_chtdr_field
+{
+  __IO uint32_t HTDAP0     : 1;
+  __IO uint32_t HTDAP1     : 1;
+  __IO uint32_t HTDAP2     : 1;
+  __IO uint32_t HTDAP3     : 1;
+  __IO uint32_t HTDAP4     : 1;
+  __IO uint32_t HTDAP5     : 1;
+  __IO uint32_t HTDAP6     : 1;
+  __IO uint32_t HTDAP7     : 1;
+  __IO uint32_t HTDAP8     : 1;
+  __IO uint32_t HTDAP9     : 1;
+  __IO uint32_t HTDAP10    : 1;
+  __IO uint32_t HTDAP11    : 1;
+  __IO uint32_t HTDAP12    : 1;
+  __IO uint32_t HTDAP13    : 1;
+  __IO uint32_t HTDAP14    : 1;
+  __IO uint32_t HTDAP15    : 1;
+  __IO uint32_t HTDAP16    : 1;
+  __IO uint32_t HTDAP17    : 1;
+  __IO uint32_t HTDAP18    : 1;
+  __IO uint32_t HTDAP19    : 1;
+  __IO uint32_t HTDAP20    : 1;
+  __IO uint32_t HTDAP21    : 1;
+  __IO uint32_t HTDAP22    : 1;
+  __IO uint32_t HTDAP23    : 1;
+  __IO uint32_t HTDAP24    : 1;
+  __IO uint32_t HTDAP25    : 1;
+  __IO uint32_t HTDAP26    : 1;
+  __IO uint32_t HTDAP27    : 1;
+  __IO uint32_t HTDAP28    : 1;
+  __IO uint32_t HTDAP29    : 1;
+  __IO uint32_t HTDAP30    : 1;
+  __IO uint32_t HTDAP31    : 1;
+} stc_ethernet_mac_chtdr_field_t;
+
+typedef struct stc_ethernet_mac_chrdr_field
+{
+  __IO uint32_t HRDAP0     : 1;
+  __IO uint32_t HRDAP1     : 1;
+  __IO uint32_t HRDAP2     : 1;
+  __IO uint32_t HRDAP3     : 1;
+  __IO uint32_t HRDAP4     : 1;
+  __IO uint32_t HRDAP5     : 1;
+  __IO uint32_t HRDAP6     : 1;
+  __IO uint32_t HRDAP7     : 1;
+  __IO uint32_t HRDAP8     : 1;
+  __IO uint32_t HRDAP9     : 1;
+  __IO uint32_t HRDAP10    : 1;
+  __IO uint32_t HRDAP11    : 1;
+  __IO uint32_t HRDAP12    : 1;
+  __IO uint32_t HRDAP13    : 1;
+  __IO uint32_t HRDAP14    : 1;
+  __IO uint32_t HRDAP15    : 1;
+  __IO uint32_t HRDAP16    : 1;
+  __IO uint32_t HRDAP17    : 1;
+  __IO uint32_t HRDAP18    : 1;
+  __IO uint32_t HRDAP19    : 1;
+  __IO uint32_t HRDAP20    : 1;
+  __IO uint32_t HRDAP21    : 1;
+  __IO uint32_t HRDAP22    : 1;
+  __IO uint32_t HRDAP23    : 1;
+  __IO uint32_t HRDAP24    : 1;
+  __IO uint32_t HRDAP25    : 1;
+  __IO uint32_t HRDAP26    : 1;
+  __IO uint32_t HRDAP27    : 1;
+  __IO uint32_t HRDAP28    : 1;
+  __IO uint32_t HRDAP29    : 1;
+  __IO uint32_t HRDAP30    : 1;
+  __IO uint32_t HRDAP31    : 1;
+} stc_ethernet_mac_chrdr_field_t;
+
+typedef struct stc_ethernet_mac_chtbar_field
+{
+  __IO uint32_t HTBAR0     : 1;
+  __IO uint32_t HTBAR1     : 1;
+  __IO uint32_t HTBAR2     : 1;
+  __IO uint32_t HTBAR3     : 1;
+  __IO uint32_t HTBAR4     : 1;
+  __IO uint32_t HTBAR5     : 1;
+  __IO uint32_t HTBAR6     : 1;
+  __IO uint32_t HTBAR7     : 1;
+  __IO uint32_t HTBAR8     : 1;
+  __IO uint32_t HTBAR9     : 1;
+  __IO uint32_t HTBAR10    : 1;
+  __IO uint32_t HTBAR11    : 1;
+  __IO uint32_t HTBAR12    : 1;
+  __IO uint32_t HTBAR13    : 1;
+  __IO uint32_t HTBAR14    : 1;
+  __IO uint32_t HTBAR15    : 1;
+  __IO uint32_t HTBAR16    : 1;
+  __IO uint32_t HTBAR17    : 1;
+  __IO uint32_t HTBAR18    : 1;
+  __IO uint32_t HTBAR19    : 1;
+  __IO uint32_t HTBAR20    : 1;
+  __IO uint32_t HTBAR21    : 1;
+  __IO uint32_t HTBAR22    : 1;
+  __IO uint32_t HTBAR23    : 1;
+  __IO uint32_t HTBAR24    : 1;
+  __IO uint32_t HTBAR25    : 1;
+  __IO uint32_t HTBAR26    : 1;
+  __IO uint32_t HTBAR27    : 1;
+  __IO uint32_t HTBAR28    : 1;
+  __IO uint32_t HTBAR29    : 1;
+  __IO uint32_t HTBAR30    : 1;
+  __IO uint32_t HTBAR31    : 1;
+} stc_ethernet_mac_chtbar_field_t;
+
+typedef struct stc_ethernet_mac_chrbar_field
+{
+  __IO uint32_t HRBAR0     : 1;
+  __IO uint32_t HRBAR1     : 1;
+  __IO uint32_t HRBAR2     : 1;
+  __IO uint32_t HRBAR3     : 1;
+  __IO uint32_t HRBAR4     : 1;
+  __IO uint32_t HRBAR5     : 1;
+  __IO uint32_t HRBAR6     : 1;
+  __IO uint32_t HRBAR7     : 1;
+  __IO uint32_t HRBAR8     : 1;
+  __IO uint32_t HRBAR9     : 1;
+  __IO uint32_t HRBAR10    : 1;
+  __IO uint32_t HRBAR11    : 1;
+  __IO uint32_t HRBAR12    : 1;
+  __IO uint32_t HRBAR13    : 1;
+  __IO uint32_t HRBAR14    : 1;
+  __IO uint32_t HRBAR15    : 1;
+  __IO uint32_t HRBAR16    : 1;
+  __IO uint32_t HRBAR17    : 1;
+  __IO uint32_t HRBAR18    : 1;
+  __IO uint32_t HRBAR19    : 1;
+  __IO uint32_t HRBAR20    : 1;
+  __IO uint32_t HRBAR21    : 1;
+  __IO uint32_t HRBAR22    : 1;
+  __IO uint32_t HRBAR23    : 1;
+  __IO uint32_t HRBAR24    : 1;
+  __IO uint32_t HRBAR25    : 1;
+  __IO uint32_t HRBAR26    : 1;
+  __IO uint32_t HRBAR27    : 1;
+  __IO uint32_t HRBAR28    : 1;
+  __IO uint32_t HRBAR29    : 1;
+  __IO uint32_t HRBAR30    : 1;
+  __IO uint32_t HRBAR31    : 1;
+} stc_ethernet_mac_chrbar_field_t;
+
+/* ETHERNET_CONTROL_MODULE register bit fields */
+typedef struct stc_ethernet_control_eth_mode_field
+{
+  __IO uint32_t IFMODE     : 1;
+       uint32_t RESERVED1  : 7;
+  __IO uint32_t RST0       : 1;
+  __IO uint32_t RST1       : 1;
+       uint32_t RESERVED2  :18;
+  __IO uint32_t ASZPPSSEL  : 1;
+} stc_ethernet_control_eth_mode_field_t;
+
+typedef struct stc_ethernet_control_eth_clkg_field
+{
+  __IO uint32_t MACEN0     : 1;
+  __IO uint32_t MACEN1     : 1;
+} stc_ethernet_control_eth_clkg_field_t;
+
+/******************************************************************************
+ * Peripheral register structures
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t FASZR;
+    stc_flash_if_faszr_field_t FASZR_f;
+  };
+  union {
+    __IO uint32_t FRWTR;
+    stc_flash_if_frwtr_field_t FRWTR_f;
+  };
+  union {
+    __IO uint32_t FSTR;
+    stc_flash_if_fstr_field_t FSTR_f;
+  };
+        uint8_t RESERVED0[4];
+  union {
+    __IO uint32_t FSYNDN;
+    stc_flash_if_fsyndn_field_t FSYNDN_f;
+  };
+        uint8_t RESERVED1[236];
+  union {
+    __IO uint32_t CRTRMM;
+    stc_flash_if_crtrmm_field_t CRTRMM_f;
+  };
+}FM3_FLASH_IF_TypeDef;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock and reset registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SCM_CTL;
+    stc_crg_scm_ctl_field_t SCM_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t SCM_STR;
+    stc_crg_scm_str_field_t SCM_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  __IO uint32_t STB_CTL;
+  union {
+    __IO uint16_t RST_STR;
+    stc_crg_rst_str_field_t RST_STR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t BSC_PSR;
+    stc_crg_bsc_psr_field_t BSC_PSR_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t APBC0_PSR;
+    stc_crg_apbc0_psr_field_t APBC0_PSR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t APBC1_PSR;
+    stc_crg_apbc1_psr_field_t APBC1_PSR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t APBC2_PSR;
+    stc_crg_apbc2_psr_field_t APBC2_PSR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t SWC_PSR;
+    stc_crg_swc_psr_field_t SWC_PSR_f;
+  };
+        uint8_t RESERVED7[7];
+  union {
+    __IO  uint8_t TTC_PSR;
+    stc_crg_ttc_psr_field_t TTC_PSR_f;
+  };
+        uint8_t RESERVED8[7];
+  union {
+    __IO  uint8_t CSW_TMR;
+    stc_crg_csw_tmr_field_t CSW_TMR_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t PSW_TMR;
+    stc_crg_psw_tmr_field_t PSW_TMR_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PLL_CTL1;
+    stc_crg_pll_ctl1_field_t PLL_CTL1_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t PLL_CTL2;
+    stc_crg_pll_ctl2_field_t PLL_CTL2_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO uint16_t CSV_CTL;
+    stc_crg_csv_ctl_field_t CSV_CTL_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO  uint8_t CSV_STR;
+    stc_crg_csv_str_field_t CSV_STR_f;
+  };
+        uint8_t RESERVED14[3];
+  __IO uint16_t FCSWH_CTL;
+        uint8_t RESERVED15[2];
+  __IO uint16_t FCSWL_CTL;
+        uint8_t RESERVED16[2];
+  __IO uint16_t FCSWD_CTL;
+        uint8_t RESERVED17[2];
+  union {
+    __IO  uint8_t DBWDT_CTL;
+    stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
+  };
+        uint8_t RESERVED18[11];
+  union {
+    __IO  uint8_t INT_ENR;
+    stc_crg_int_enr_field_t INT_ENR_f;
+  };
+        uint8_t RESERVED19[3];
+  union {
+    __IO  uint8_t INT_STR;
+    stc_crg_int_str_field_t INT_STR_f;
+  };
+        uint8_t RESERVED20[3];
+  union {
+    __IO  uint8_t INT_CLR;
+    stc_crg_int_clr_field_t INT_CLR_f;
+  };
+}FM3_CRG_TypeDef;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* Hardware watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDG_LDR;
+  __IO uint32_t WDG_VLR;
+  union {
+    __IO  uint8_t WDG_CTL;
+    stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO  uint8_t WDG_ICL;
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t WDG_RIS;
+    stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
+  };
+        uint8_t RESERVED2[3055];
+  __IO uint32_t WDG_LCK;
+}FM3_HWWDT_TypeDef;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* Software watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDOGLOAD;
+  __IO uint32_t WDOGVALUE;
+  union {
+    __IO  uint8_t WDOGCONTROL;
+    stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t WDOGINTCLR;
+  union {
+    __IO  uint8_t WDOGRIS;
+    stc_swwdt_wdogris_field_t WDOGRIS_f;
+  };
+        uint8_t RESERVED1[3055];
+  __IO uint32_t WDOGLOCK;
+}FM3_SWWDT_TypeDef;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* Dual timer 1/2 registers */
+typedef struct
+{
+  __IO uint32_t TIMER1LOAD;
+  __IO uint32_t TIMER1VALUE;
+  union {
+    __IO uint32_t TIMER1CONTROL;
+    stc_dtim_timer1control_field_t TIMER1CONTROL_f;
+  };
+  __IO uint32_t TIMER1INTCLR;
+  union {
+    __IO uint32_t TIMER1RIS;
+    stc_dtim_timer1ris_field_t TIMER1RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER1MIS;
+    stc_dtim_timer1mis_field_t TIMER1MIS_f;
+  };
+  __IO uint32_t TIMER1BGLOAD;
+        uint8_t RESERVED0[4];
+  __IO uint32_t TIMER2LOAD;
+  __IO uint32_t TIMER2VALUE;
+  union {
+    __IO uint32_t TIMER2CONTROL;
+    stc_dtim_timer2control_field_t TIMER2CONTROL_f;
+  };
+  __IO uint32_t TIMER2INTCLR;
+  union {
+    __IO uint32_t TIMER2RIS;
+    stc_dtim_timer2ris_field_t TIMER2RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER2MIS;
+    stc_dtim_timer2mis_field_t TIMER2MIS_f;
+  };
+  __IO uint32_t TIMER2BGLOAD;
+}FM3_DTIM_TypeDef;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Free Running Timer registers */
+typedef struct
+{
+        uint8_t RESERVED0[40];
+  __IO uint16_t TCCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TCDT0;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TCSA0;
+    stc_mft_frt_tcsa0_field_t TCSA0_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t TCSB0;
+    stc_mft_frt_tcsb0_field_t TCSB0_f;
+  };
+        uint8_t RESERVED4[2];
+  __IO uint16_t TCCP1;
+        uint8_t RESERVED5[2];
+  __IO uint16_t TCDT1;
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t TCSA1;
+    stc_mft_frt_tcsa1_field_t TCSA1_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t TCSB1;
+    stc_mft_frt_tcsb1_field_t TCSB1_f;
+  };
+        uint8_t RESERVED8[2];
+  __IO uint16_t TCCP2;
+        uint8_t RESERVED9[2];
+  __IO uint16_t TCDT2;
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t TCSA2;
+    stc_mft_frt_tcsa2_field_t TCSA2_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t TCSB2;
+    stc_mft_frt_tcsb2_field_t TCSB2_f;
+  };
+}FM3_MFT_FRT_TypeDef;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+typedef struct
+{
+  __IO uint16_t OCCP0;
+        uint8_t RESERVED0[2];
+  __IO uint16_t OCCP1;
+        uint8_t RESERVED1[2];
+  __IO uint16_t OCCP2;
+        uint8_t RESERVED2[2];
+  __IO uint16_t OCCP3;
+        uint8_t RESERVED3[2];
+  __IO uint16_t OCCP4;
+        uint8_t RESERVED4[2];
+  __IO uint16_t OCCP5;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t OCSA10;
+    stc_mft_ocu_ocsa10_field_t OCSA10_f;
+  };
+  union {
+    __IO  uint8_t OCSB10;
+    stc_mft_ocu_ocsb10_field_t OCSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t OCSA32;
+    stc_mft_ocu_ocsa32_field_t OCSA32_f;
+  };
+  union {
+    __IO  uint8_t OCSB32;
+    stc_mft_ocu_ocsb32_field_t OCSB32_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO  uint8_t OCSA54;
+    stc_mft_ocu_ocsa54_field_t OCSA54_f;
+  };
+  union {
+    __IO  uint8_t OCSB54;
+    stc_mft_ocu_ocsb54_field_t OCSB54_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t OCSC;
+    stc_mft_ocu_ocsc_field_t OCSC_f;
+  };
+        uint8_t RESERVED9[50];
+  union {
+    __IO  uint8_t OCFS10;
+    stc_mft_ocu_ocfs10_field_t OCFS10_f;
+  };
+  union {
+    __IO  uint8_t OCFS32;
+    stc_mft_ocu_ocfs32_field_t OCFS32_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO  uint8_t OCFS54;
+    stc_mft_ocu_ocfs54_field_t OCFS54_f;
+  };
+}FM3_MFT_OCU_TypeDef;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+typedef struct
+{
+        uint8_t RESERVED0[128];
+  __IO uint16_t WFTM10;
+        uint8_t RESERVED1[2];
+  __IO uint16_t WFTM32;
+        uint8_t RESERVED2[2];
+  __IO uint16_t WFTM54;
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t WFSA10;
+    stc_mft_wfg_wfsa10_field_t WFSA10_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t WFSA32;
+    stc_mft_wfg_wfsa32_field_t WFSA32_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t WFSA54;
+    stc_mft_wfg_wfsa54_field_t WFSA54_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t WFIR;
+    stc_mft_wfg_wfir_field_t WFIR_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t NZCL;
+    stc_mft_wfg_nzcl_field_t NZCL_f;
+  };
+}FM3_MFT_WFG_TypeDef;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[96];
+  union {
+    __IO  uint8_t ICFS10;
+    stc_mft_icu_icfs10_field_t ICFS10_f;
+  };
+  union {
+    __IO  uint8_t ICFS32;
+    stc_mft_icu_icfs32_field_t ICFS32_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint16_t ICCP0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ICCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ICCP2;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ICCP3;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t ICSA10;
+    stc_mft_icu_icsa10_field_t ICSA10_f;
+  };
+  union {
+    __IO  uint8_t ICSB10;
+    stc_mft_icu_icsb10_field_t ICSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ICSA32;
+    stc_mft_icu_icsa32_field_t ICSA32_f;
+  };
+  union {
+    __IO  uint8_t ICSB32;
+    stc_mft_icu_icsb32_field_t ICSB32_f;
+  };
+}FM3_MFT_ICU_TypeDef;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[160];
+  __IO uint16_t ACCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t ACCPDN0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ACCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ACCPDN1;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ACCP2;
+        uint8_t RESERVED5[2];
+  __IO uint16_t ACCPDN2;
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ACSB;
+    stc_mft_adcmp_acsb_field_t ACSB_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t ACSA;
+    stc_mft_adcmp_acsa_field_t ACSA_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t ATSA;
+    stc_mft_adcmp_atsa_field_t ATSA_f;
+  };
+}FM3_MFT_ADCMP_TypeDef;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer PPG registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t TTCR0;
+    stc_mft_ppg_ttcr0_field_t TTCR0_f;
+  };
+        uint8_t RESERVED1[7];
+  __IO  uint8_t COMP0;
+        uint8_t RESERVED2[2];
+  __IO  uint8_t COMP2;
+        uint8_t RESERVED3[4];
+  __IO  uint8_t COMP4;
+        uint8_t RESERVED4[2];
+  __IO  uint8_t COMP6;
+        uint8_t RESERVED5[12];
+  union {
+    __IO  uint8_t TTCR1;
+    stc_mft_ppg_ttcr1_field_t TTCR1_f;
+  };
+        uint8_t RESERVED6[7];
+  __IO  uint8_t COMP1;
+        uint8_t RESERVED7[2];
+  __IO  uint8_t COMP3;
+        uint8_t RESERVED8[4];
+  __IO  uint8_t COMP5;
+        uint8_t RESERVED9[2];
+  __IO  uint8_t COMP7;
+        uint8_t RESERVED10[12];
+  union {
+    __IO  uint8_t TTCR2;
+    stc_mft_ppg_ttcr2_field_t TTCR2_f;
+  };
+        uint8_t RESERVED11[7];
+  __IO  uint8_t COMP8;
+        uint8_t RESERVED12[2];
+  __IO  uint8_t COMP10;
+        uint8_t RESERVED13[4];
+  __IO  uint8_t COMP12;
+        uint8_t RESERVED14[2];
+  __IO  uint8_t COMP14;
+        uint8_t RESERVED15[171];
+  union {
+    __IO uint16_t TRG;
+    stc_mft_ppg_trg_field_t TRG_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t REVC;
+    stc_mft_ppg_revc_field_t REVC_f;
+  };
+        uint8_t RESERVED17[58];
+  union {
+    __IO uint16_t TRG1;
+    stc_mft_ppg_trg1_field_t TRG1_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t REVC1;
+    stc_mft_ppg_revc1_field_t REVC1_f;
+  };
+        uint8_t RESERVED19[186];
+  union {
+    __IO  uint8_t PPGC1;
+    stc_mft_ppg_ppgc1_field_t PPGC1_f;
+  };
+  union {
+    __IO  uint8_t PPGC0;
+    stc_mft_ppg_ppgc0_field_t PPGC0_f;
+  };
+        uint8_t RESERVED20[2];
+  union {
+    __IO  uint8_t PPGC3;
+    stc_mft_ppg_ppgc3_field_t PPGC3_f;
+  };
+  union {
+    __IO  uint8_t PPGC2;
+    stc_mft_ppg_ppgc2_field_t PPGC2_f;
+  };
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t PRL0;
+    struct {
+      __IO  uint8_t PRLL0;
+      __IO  uint8_t PRLH0;
+    };
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t PRL1;
+    struct {
+      __IO  uint8_t PRLL1;
+      __IO  uint8_t PRLH1;
+    };
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t PRL2;
+    struct {
+      __IO  uint8_t PRLL2;
+      __IO  uint8_t PRLH2;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t PRL3;
+    struct {
+      __IO  uint8_t PRLL3;
+      __IO  uint8_t PRLH3;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO  uint8_t GATEC0;
+    stc_mft_ppg_gatec0_field_t GATEC0_f;
+  };
+        uint8_t RESERVED26[39];
+  union {
+    __IO  uint8_t PPGC5;
+    stc_mft_ppg_ppgc5_field_t PPGC5_f;
+  };
+  union {
+    __IO  uint8_t PPGC4;
+    stc_mft_ppg_ppgc4_field_t PPGC4_f;
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO  uint8_t PPGC7;
+    stc_mft_ppg_ppgc7_field_t PPGC7_f;
+  };
+  union {
+    __IO  uint8_t PPGC6;
+    stc_mft_ppg_ppgc6_field_t PPGC6_f;
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t PRL4;
+    struct {
+      __IO  uint8_t PRLL4;
+      __IO  uint8_t PRLH4;
+    };
+  };
+        uint8_t RESERVED29[2];
+  union {
+    __IO uint16_t PRL5;
+    struct {
+      __IO  uint8_t PRLL5;
+      __IO  uint8_t PRLH5;
+    };
+  };
+        uint8_t RESERVED30[2];
+  union {
+    __IO uint16_t PRL6;
+    struct {
+      __IO  uint8_t PRLL6;
+      __IO  uint8_t PRLH6;
+    };
+  };
+        uint8_t RESERVED31[2];
+  union {
+    __IO uint16_t PRL7;
+    struct {
+      __IO  uint8_t PRLL7;
+      __IO  uint8_t PRLH7;
+    };
+  };
+        uint8_t RESERVED32[2];
+  union {
+    __IO  uint8_t GATEC4;
+    stc_mft_ppg_gatec4_field_t GATEC4_f;
+  };
+        uint8_t RESERVED33[39];
+  union {
+    __IO  uint8_t PPGC9;
+    stc_mft_ppg_ppgc9_field_t PPGC9_f;
+  };
+  union {
+    __IO  uint8_t PPGC8;
+    stc_mft_ppg_ppgc8_field_t PPGC8_f;
+  };
+        uint8_t RESERVED34[2];
+  union {
+    __IO  uint8_t PPGC11;
+    stc_mft_ppg_ppgc11_field_t PPGC11_f;
+  };
+  union {
+    __IO  uint8_t PPGC10;
+    stc_mft_ppg_ppgc10_field_t PPGC10_f;
+  };
+        uint8_t RESERVED35[2];
+  union {
+    __IO uint16_t PRL8;
+    struct {
+      __IO  uint8_t PRLL8;
+      __IO  uint8_t PRLH8;
+    };
+  };
+        uint8_t RESERVED36[2];
+  union {
+    __IO uint16_t PRL9;
+    struct {
+      __IO  uint8_t PRLL9;
+      __IO  uint8_t PRLH9;
+    };
+  };
+        uint8_t RESERVED37[2];
+  union {
+    __IO uint16_t PRL10;
+    struct {
+      __IO  uint8_t PRLL10;
+      __IO  uint8_t PRLH10;
+    };
+  };
+        uint8_t RESERVED38[2];
+  union {
+    __IO uint16_t PRL11;
+    struct {
+      __IO  uint8_t PRLL11;
+      __IO  uint8_t PRLH11;
+    };
+  };
+        uint8_t RESERVED39[2];
+  union {
+    __IO  uint8_t GATEC8;
+    stc_mft_ppg_gatec8_field_t GATEC8_f;
+  };
+        uint8_t RESERVED40[39];
+  union {
+    __IO  uint8_t PPGC13;
+    stc_mft_ppg_ppgc13_field_t PPGC13_f;
+  };
+  union {
+    __IO  uint8_t PPGC12;
+    stc_mft_ppg_ppgc12_field_t PPGC12_f;
+  };
+        uint8_t RESERVED41[2];
+  union {
+    __IO  uint8_t PPGC15;
+    stc_mft_ppg_ppgc15_field_t PPGC15_f;
+  };
+  union {
+    __IO  uint8_t PPGC14;
+    stc_mft_ppg_ppgc14_field_t PPGC14_f;
+  };
+        uint8_t RESERVED42[2];
+  union {
+    __IO uint16_t PRL12;
+    struct {
+      __IO  uint8_t PRLL12;
+      __IO  uint8_t PRLH12;
+    };
+  };
+        uint8_t RESERVED43[2];
+  union {
+    __IO uint16_t PRL13;
+    struct {
+      __IO  uint8_t PRLL13;
+      __IO  uint8_t PRLH13;
+    };
+  };
+        uint8_t RESERVED44[2];
+  union {
+    __IO uint16_t PRL14;
+    struct {
+      __IO  uint8_t PRLL14;
+      __IO  uint8_t PRLH14;
+    };
+  };
+        uint8_t RESERVED45[2];
+  union {
+    __IO uint16_t PRL15;
+    struct {
+      __IO  uint8_t PRLL15;
+      __IO  uint8_t PRLH15;
+    };
+  };
+        uint8_t RESERVED46[2];
+  union {
+    __IO  uint8_t GATEC12;
+    stc_mft_ppg_gatec12_field_t GATEC12_f;
+  };
+        uint8_t RESERVED47[39];
+  union {
+    __IO  uint8_t PPGC17;
+    stc_mft_ppg_ppgc17_field_t PPGC17_f;
+  };
+  union {
+    __IO  uint8_t PPGC16;
+    stc_mft_ppg_ppgc16_field_t PPGC16_f;
+  };
+        uint8_t RESERVED48[2];
+  union {
+    __IO  uint8_t PPGC19;
+    stc_mft_ppg_ppgc19_field_t PPGC19_f;
+  };
+  union {
+    __IO  uint8_t PPGC18;
+    stc_mft_ppg_ppgc18_field_t PPGC18_f;
+  };
+        uint8_t RESERVED49[2];
+  union {
+    __IO uint16_t PRL16;
+    struct {
+      __IO  uint8_t PRLL16;
+      __IO  uint8_t PRLH16;
+    };
+  };
+        uint8_t RESERVED50[2];
+  union {
+    __IO uint16_t PRL17;
+    struct {
+      __IO  uint8_t PRLL17;
+      __IO  uint8_t PRLH17;
+    };
+  };
+        uint8_t RESERVED51[2];
+  union {
+    __IO uint16_t PRL18;
+    struct {
+      __IO  uint8_t PRLL18;
+      __IO  uint8_t PRLH18;
+    };
+  };
+        uint8_t RESERVED52[2];
+  union {
+    __IO uint16_t PRL19;
+    struct {
+      __IO  uint8_t PRLL19;
+      __IO  uint8_t PRLH19;
+    };
+  };
+        uint8_t RESERVED53[2];
+  union {
+    __IO  uint8_t GATEC16;
+    stc_mft_ppg_gatec16_field_t GATEC16_f;
+  };
+        uint8_t RESERVED54[39];
+  union {
+    __IO  uint8_t PPGC21;
+    stc_mft_ppg_ppgc21_field_t PPGC21_f;
+  };
+  union {
+    __IO  uint8_t PPGC20;
+    stc_mft_ppg_ppgc20_field_t PPGC20_f;
+  };
+        uint8_t RESERVED55[2];
+  union {
+    __IO  uint8_t PPGC23;
+    stc_mft_ppg_ppgc23_field_t PPGC23_f;
+  };
+  union {
+    __IO  uint8_t PPGC22;
+    stc_mft_ppg_ppgc22_field_t PPGC22_f;
+  };
+        uint8_t RESERVED56[2];
+  union {
+    __IO uint16_t PRL20;
+    struct {
+      __IO  uint8_t PRLL20;
+      __IO  uint8_t PRLH20;
+    };
+  };
+        uint8_t RESERVED57[2];
+  union {
+    __IO uint16_t PRL21;
+    struct {
+      __IO  uint8_t PRLL21;
+      __IO  uint8_t PRLH21;
+    };
+  };
+        uint8_t RESERVED58[2];
+  union {
+    __IO uint16_t PRL22;
+    struct {
+      __IO  uint8_t PRLL22;
+      __IO  uint8_t PRLH22;
+    };
+  };
+        uint8_t RESERVED59[2];
+  union {
+    __IO uint16_t PRL23;
+    struct {
+      __IO  uint8_t PRLL23;
+      __IO  uint8_t PRLH23;
+    };
+  };
+        uint8_t RESERVED60[2];
+  union {
+    __IO  uint8_t GATEC20;
+    stc_mft_ppg_gatec20_field_t GATEC20_f;
+  };
+}FM3_MFT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PPG registers */
+typedef struct
+{
+  __IO uint16_t PRLL;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PRLH;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_ppg_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_ppg_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_ppg_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWM registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PDUT;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwm_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwm_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwm_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWM_TypeDef;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* Base Timer 0 RT registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[6];
+  __IO uint16_t TMR;
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_rt_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_rt_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_rt_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_RT_TypeDef;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWC registers */
+typedef struct
+{
+        uint8_t RESERVED0[4];
+  __IO uint16_t DTBF;
+        uint8_t RESERVED1[6];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwc_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwc_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwc_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWC_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL0123;
+    stc_btiosel03_btsel0123_field_t BTSEL0123_f;
+  };
+}FM3_BTIOSEL03_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL4567;
+    stc_btiosel47_btsel4567_field_t BTSEL4567_f;
+  };
+}FM3_BTIOSEL47_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL8B_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL89AB;
+    stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f;
+  };
+}FM3_BTIOSEL8B_TypeDef;
+
+/******************************************************************************
+ * BTIOSELCF_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSELCDEF;
+    stc_btioselcf_btselcdef_field_t BTSELCDEF_f;
+  };
+}FM3_BTIOSELCF_TypeDef;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* Software based Simulation Startup (Base Timer) register */
+typedef struct
+{
+  union {
+    __IO uint16_t BTSSSR;
+    stc_sbssr_btsssr_field_t BTSSSR_f;
+  };
+}FM3_SBSSR_TypeDef;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* Quad position and revolution counter channel 0 registers */
+typedef struct
+{
+  __IO uint16_t QPCR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t QRCR;
+        uint8_t RESERVED1[2];
+  __IO uint16_t QPCCR;
+        uint8_t RESERVED2[2];
+  __IO uint16_t QPRCR;
+        uint8_t RESERVED3[2];
+  __IO uint16_t QMPR;
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t QICR;
+      stc_qprc_qicr_field_t QICR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QICRL;
+        stc_qprc_qicrl_field_t QICRL_f;
+      };
+      union {
+        __IO  uint8_t QICRH;
+        stc_qprc_qicrh_field_t QICRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t QCR;
+      stc_qprc_qcr_field_t QCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QCRL;
+        stc_qprc_qcrl_field_t QCRL_f;
+      };
+      union {
+        __IO  uint8_t QCRH;
+        stc_qprc_qcrh_field_t QCRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t QECR;
+    stc_qprc_qecr_field_t QECR_f;
+  };
+        uint8_t RESERVED7[30];
+  __IO uint16_t QRCRR;
+  __IO uint16_t QPCRR;
+}FM3_QPRC_TypeDef;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* 12-bit ADC unit 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t ADSR;
+    stc_adc_adsr_field_t ADSR_f;
+  };
+  union {
+    __IO  uint8_t ADCR;
+    stc_adc_adcr_field_t ADCR_f;
+  };
+        uint8_t RESERVED0[6];
+  union {
+    __IO  uint8_t SFNS;
+    stc_adc_sfns_field_t SFNS_f;
+  };
+  union {
+    __IO  uint8_t SCCR;
+    stc_adc_sccr_field_t SCCR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint32_t SCFD;
+      stc_adc_scfd_field_t SCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t SCFDL;
+        stc_adc_scfdl_field_t SCFDL_f;
+      };
+      union {
+        __IO uint16_t SCFDH;
+        stc_adc_scfdh_field_t SCFDH_f;
+      };
+    };
+  };
+  union {
+    union {
+      __IO uint16_t SCIS23;
+      stc_adc_scis23_field_t SCIS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS2;
+        stc_adc_scis2_field_t SCIS2_f;
+      };
+      union {
+        __IO  uint8_t SCIS3;
+        stc_adc_scis3_field_t SCIS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t SCIS01;
+      stc_adc_scis01_field_t SCIS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS0;
+        stc_adc_scis0_field_t SCIS0_f;
+      };
+      union {
+        __IO  uint8_t SCIS1;
+        stc_adc_scis1_field_t SCIS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t PFNS;
+    stc_adc_pfns_field_t PFNS_f;
+  };
+  union {
+    __IO  uint8_t PCCR;
+    stc_adc_pccr_field_t PCCR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint32_t PCFD;
+      stc_adc_pcfd_field_t PCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t PCFDL;
+        stc_adc_pcfdl_field_t PCFDL_f;
+      };
+      union {
+        __IO uint16_t PCFDH;
+        stc_adc_pcfdh_field_t PCFDH_f;
+      };
+    };
+  };
+  union {
+    __IO  uint8_t PCIS;
+    stc_adc_pcis_field_t PCIS_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t CMPCR;
+    stc_adc_cmpcr_field_t CMPCR_f;
+  };
+        uint8_t RESERVED6;
+  union {
+    __IO uint16_t CMPD;
+    stc_adc_cmpd_field_t CMPD_f;
+  };
+  union {
+    union {
+      __IO uint16_t ADSS23;
+      stc_adc_adss23_field_t ADSS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS2;
+        stc_adc_adss2_field_t ADSS2_f;
+      };
+      union {
+        __IO  uint8_t ADSS3;
+        stc_adc_adss3_field_t ADSS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED7[2];
+  union {
+    union {
+      __IO uint16_t ADSS01;
+      stc_adc_adss01_field_t ADSS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS0;
+        stc_adc_adss0_field_t ADSS0_f;
+      };
+      union {
+        __IO  uint8_t ADSS1;
+        stc_adc_adss1_field_t ADSS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED8[2];
+  union {
+    union {
+      __IO uint16_t ADST01;
+      stc_adc_adst01_field_t ADST01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADST1;
+        stc_adc_adst1_field_t ADST1_f;
+      };
+      union {
+        __IO  uint8_t ADST0;
+        stc_adc_adst0_field_t ADST0_f;
+      };
+    };
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO  uint8_t ADCT;
+    stc_adc_adct_field_t ADCT_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PRTSL;
+    stc_adc_prtsl_field_t PRTSL_f;
+  };
+  union {
+    __IO  uint8_t SCTSL;
+    stc_adc_sctsl_field_t SCTSL_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO  uint8_t ADCEN;
+    stc_adc_adcen_field_t ADCEN_f;
+  };
+}FM3_ADC_TypeDef;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CR trimming registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t MCR_PSR;
+    stc_crtrim_mcr_psr_field_t MCR_PSR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO uint16_t MCR_FTRM;
+    stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint32_t MCR_RLR;
+}FM3_CRTRIM_TypeDef;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* External interrupt registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ENIR;
+    stc_exti_enir_field_t ENIR_f;
+  };
+  union {
+    __IO uint32_t EIRR;
+    stc_exti_eirr_field_t EIRR_f;
+  };
+  union {
+    __IO uint32_t EICL;
+    stc_exti_eicl_field_t EICL_f;
+  };
+  union {
+    __IO uint32_t ELVR;
+    stc_exti_elvr_field_t ELVR_f;
+  };
+  union {
+    __IO uint32_t ELVR1;
+    stc_exti_elvr1_field_t ELVR1_f;
+  };
+  union {
+    __IO  uint8_t NMIRR;
+    stc_exti_nmirr_field_t NMIRR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t NMICL;
+    stc_exti_nmicl_field_t NMICL_f;
+  };
+}FM3_EXTI_TypeDef;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* Interrupt request read registers */
+typedef struct
+{
+  union {
+    __IO uint32_t DRQSEL;
+    stc_intreq_drqsel_field_t DRQSEL_f;
+  };
+        uint8_t RESERVED0[7];
+  union {
+    __IO  uint8_t ODDPKS;
+    stc_intreq_oddpks_field_t ODDPKS_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t EXC02MON;
+    stc_intreq_exc02mon_field_t EXC02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ00MON;
+    stc_intreq_irq00mon_field_t IRQ00MON_f;
+  };
+  union {
+    __IO uint32_t IRQ01MON;
+    stc_intreq_irq01mon_field_t IRQ01MON_f;
+  };
+  union {
+    __IO uint32_t IRQ02MON;
+    stc_intreq_irq02mon_field_t IRQ02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ03MON;
+    stc_intreq_irq03mon_field_t IRQ03MON_f;
+  };
+  union {
+    __IO uint32_t IRQ04MON;
+    stc_intreq_irq04mon_field_t IRQ04MON_f;
+  };
+  union {
+    __IO uint32_t IRQ05MON;
+    stc_intreq_irq05mon_field_t IRQ05MON_f;
+  };
+  union {
+    __IO uint32_t IRQ06MON;
+    stc_intreq_irq06mon_field_t IRQ06MON_f;
+  };
+  union {
+    __IO uint32_t IRQ07MON;
+    stc_intreq_irq07mon_field_t IRQ07MON_f;
+  };
+  union {
+    __IO uint32_t IRQ08MON;
+    stc_intreq_irq08mon_field_t IRQ08MON_f;
+  };
+  union {
+    __IO uint32_t IRQ09MON;
+    stc_intreq_irq09mon_field_t IRQ09MON_f;
+  };
+  union {
+    __IO uint32_t IRQ10MON;
+    stc_intreq_irq10mon_field_t IRQ10MON_f;
+  };
+  union {
+    __IO uint32_t IRQ11MON;
+    stc_intreq_irq11mon_field_t IRQ11MON_f;
+  };
+  union {
+    __IO uint32_t IRQ12MON;
+    stc_intreq_irq12mon_field_t IRQ12MON_f;
+  };
+  union {
+    __IO uint32_t IRQ13MON;
+    stc_intreq_irq13mon_field_t IRQ13MON_f;
+  };
+  union {
+    __IO uint32_t IRQ14MON;
+    stc_intreq_irq14mon_field_t IRQ14MON_f;
+  };
+  union {
+    __IO uint32_t IRQ15MON;
+    stc_intreq_irq15mon_field_t IRQ15MON_f;
+  };
+  union {
+    __IO uint32_t IRQ16MON;
+    stc_intreq_irq16mon_field_t IRQ16MON_f;
+  };
+  union {
+    __IO uint32_t IRQ17MON;
+    stc_intreq_irq17mon_field_t IRQ17MON_f;
+  };
+  union {
+    __IO uint32_t IRQ18MON;
+    stc_intreq_irq18mon_field_t IRQ18MON_f;
+  };
+  union {
+    __IO uint32_t IRQ19MON;
+    stc_intreq_irq19mon_field_t IRQ19MON_f;
+  };
+  union {
+    __IO uint32_t IRQ20MON;
+    stc_intreq_irq20mon_field_t IRQ20MON_f;
+  };
+  union {
+    __IO uint32_t IRQ21MON;
+    stc_intreq_irq21mon_field_t IRQ21MON_f;
+  };
+  union {
+    __IO uint32_t IRQ22MON;
+    stc_intreq_irq22mon_field_t IRQ22MON_f;
+  };
+  union {
+    __IO uint32_t IRQ23MON;
+    stc_intreq_irq23mon_field_t IRQ23MON_f;
+  };
+  union {
+    __IO uint32_t IRQ24MON;
+    stc_intreq_irq24mon_field_t IRQ24MON_f;
+  };
+  union {
+    __IO uint32_t IRQ25MON;
+    stc_intreq_irq25mon_field_t IRQ25MON_f;
+  };
+  union {
+    __IO uint32_t IRQ26MON;
+    stc_intreq_irq26mon_field_t IRQ26MON_f;
+  };
+  union {
+    __IO uint32_t IRQ27MON;
+    stc_intreq_irq27mon_field_t IRQ27MON_f;
+  };
+  union {
+    __IO uint32_t IRQ28MON;
+    stc_intreq_irq28mon_field_t IRQ28MON_f;
+  };
+  union {
+    __IO uint32_t IRQ29MON;
+    stc_intreq_irq29mon_field_t IRQ29MON_f;
+  };
+  union {
+    __IO uint32_t IRQ30MON;
+    stc_intreq_irq30mon_field_t IRQ30MON_f;
+  };
+  union {
+    __IO uint32_t IRQ31MON;
+    stc_intreq_irq31mon_field_t IRQ31MON_f;
+  };
+  union {
+    __IO uint32_t IRQ32MON;
+    stc_intreq_irq32mon_field_t IRQ32MON_f;
+  };
+  union {
+    __IO uint32_t IRQ33MON;
+    stc_intreq_irq33mon_field_t IRQ33MON_f;
+  };
+  union {
+    __IO uint32_t IRQ34MON;
+    stc_intreq_irq34mon_field_t IRQ34MON_f;
+  };
+  union {
+    __IO uint32_t IRQ35MON;
+    stc_intreq_irq35mon_field_t IRQ35MON_f;
+  };
+  union {
+    __IO uint32_t IRQ36MON;
+    stc_intreq_irq36mon_field_t IRQ36MON_f;
+  };
+  union {
+    __IO uint32_t IRQ37MON;
+    stc_intreq_irq37mon_field_t IRQ37MON_f;
+  };
+  union {
+    __IO uint32_t IRQ38MON;
+    stc_intreq_irq38mon_field_t IRQ38MON_f;
+  };
+  union {
+    __IO uint32_t IRQ39MON;
+    stc_intreq_irq39mon_field_t IRQ39MON_f;
+  };
+  union {
+    __IO uint32_t IRQ40MON;
+    stc_intreq_irq40mon_field_t IRQ40MON_f;
+  };
+  union {
+    __IO uint32_t IRQ41MON;
+    stc_intreq_irq41mon_field_t IRQ41MON_f;
+  };
+  union {
+    __IO uint32_t IRQ42MON;
+    stc_intreq_irq42mon_field_t IRQ42MON_f;
+  };
+  union {
+    __IO uint32_t IRQ43MON;
+    stc_intreq_irq43mon_field_t IRQ43MON_f;
+  };
+  union {
+    __IO uint32_t IRQ44MON;
+    stc_intreq_irq44mon_field_t IRQ44MON_f;
+  };
+  union {
+    __IO uint32_t IRQ45MON;
+    stc_intreq_irq45mon_field_t IRQ45MON_f;
+  };
+  union {
+    __IO uint32_t IRQ46MON;
+    stc_intreq_irq46mon_field_t IRQ46MON_f;
+  };
+        uint8_t RESERVED2[300];
+  union {
+    __IO uint32_t DRQSEL1;
+    stc_intreq_drqsel1_field_t DRQSEL1_f;
+  };
+  union {
+    __IO uint32_t DQESEL;
+    stc_intreq_dqesel_field_t DQESEL_f;
+  };
+        uint8_t RESERVED3[7];
+  union {
+    __IO  uint8_t ODDPKS1;
+    stc_intreq_oddpks1_field_t ODDPKS1_f;
+  };
+}FM3_INTREQ_TypeDef;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* General purpose I/O registers */
+typedef struct
+{
+  union {
+    __IO uint32_t PFR0;
+    stc_gpio_pfr0_field_t PFR0_f;
+  };
+  union {
+    __IO uint32_t PFR1;
+    stc_gpio_pfr1_field_t PFR1_f;
+  };
+  union {
+    __IO uint32_t PFR2;
+    stc_gpio_pfr2_field_t PFR2_f;
+  };
+  union {
+    __IO uint32_t PFR3;
+    stc_gpio_pfr3_field_t PFR3_f;
+  };
+  union {
+    __IO uint32_t PFR4;
+    stc_gpio_pfr4_field_t PFR4_f;
+  };
+  union {
+    __IO uint32_t PFR5;
+    stc_gpio_pfr5_field_t PFR5_f;
+  };
+  union {
+    __IO uint32_t PFR6;
+    stc_gpio_pfr6_field_t PFR6_f;
+  };
+  union {
+    __IO uint32_t PFR7;
+    stc_gpio_pfr7_field_t PFR7_f;
+  };
+  union {
+    __IO uint32_t PFR8;
+    stc_gpio_pfr8_field_t PFR8_f;
+  };
+  __IO uint32_t PFR9;
+  union {
+    __IO uint32_t PFRA;
+    stc_gpio_pfra_field_t PFRA_f;
+  };
+  __IO uint32_t PFRB;
+  union {
+    __IO uint32_t PFRC;
+    stc_gpio_pfrc_field_t PFRC_f;
+  };
+  union {
+    __IO uint32_t PFRD;
+    stc_gpio_pfrd_field_t PFRD_f;
+  };
+  union {
+    __IO uint32_t PFRE;
+    stc_gpio_pfre_field_t PFRE_f;
+  };
+  union {
+    __IO uint32_t PFRF;
+    stc_gpio_pfrf_field_t PFRF_f;
+  };
+        uint8_t RESERVED0[192];
+  union {
+    __IO uint32_t PCR0;
+    stc_gpio_pcr0_field_t PCR0_f;
+  };
+  union {
+    __IO uint32_t PCR1;
+    stc_gpio_pcr1_field_t PCR1_f;
+  };
+  union {
+    __IO uint32_t PCR2;
+    stc_gpio_pcr2_field_t PCR2_f;
+  };
+  union {
+    __IO uint32_t PCR3;
+    stc_gpio_pcr3_field_t PCR3_f;
+  };
+  union {
+    __IO uint32_t PCR4;
+    stc_gpio_pcr4_field_t PCR4_f;
+  };
+  union {
+    __IO uint32_t PCR5;
+    stc_gpio_pcr5_field_t PCR5_f;
+  };
+  union {
+    __IO uint32_t PCR6;
+    stc_gpio_pcr6_field_t PCR6_f;
+  };
+  union {
+    __IO uint32_t PCR7;
+    stc_gpio_pcr7_field_t PCR7_f;
+  };
+  __IO uint32_t PCR8;
+  __IO uint32_t PCR9;
+  union {
+    __IO uint32_t PCRA;
+    stc_gpio_pcra_field_t PCRA_f;
+  };
+  __IO uint32_t PCRB;
+  union {
+    __IO uint32_t PCRC;
+    stc_gpio_pcrc_field_t PCRC_f;
+  };
+  union {
+    __IO uint32_t PCRD;
+    stc_gpio_pcrd_field_t PCRD_f;
+  };
+  union {
+    __IO uint32_t PCRE;
+    stc_gpio_pcre_field_t PCRE_f;
+  };
+  __IO uint32_t PCRF;
+        uint8_t RESERVED1[192];
+  union {
+    __IO uint32_t DDR0;
+    stc_gpio_ddr0_field_t DDR0_f;
+  };
+  union {
+    __IO uint32_t DDR1;
+    stc_gpio_ddr1_field_t DDR1_f;
+  };
+  union {
+    __IO uint32_t DDR2;
+    stc_gpio_ddr2_field_t DDR2_f;
+  };
+  union {
+    __IO uint32_t DDR3;
+    stc_gpio_ddr3_field_t DDR3_f;
+  };
+  union {
+    __IO uint32_t DDR4;
+    stc_gpio_ddr4_field_t DDR4_f;
+  };
+  union {
+    __IO uint32_t DDR5;
+    stc_gpio_ddr5_field_t DDR5_f;
+  };
+  union {
+    __IO uint32_t DDR6;
+    stc_gpio_ddr6_field_t DDR6_f;
+  };
+  union {
+    __IO uint32_t DDR7;
+    stc_gpio_ddr7_field_t DDR7_f;
+  };
+  union {
+    __IO uint32_t DDR8;
+    stc_gpio_ddr8_field_t DDR8_f;
+  };
+  __IO uint32_t DDR9;
+  union {
+    __IO uint32_t DDRA;
+    stc_gpio_ddra_field_t DDRA_f;
+  };
+  __IO uint32_t DDRB;
+  union {
+    __IO uint32_t DDRC;
+    stc_gpio_ddrc_field_t DDRC_f;
+  };
+  union {
+    __IO uint32_t DDRD;
+    stc_gpio_ddrd_field_t DDRD_f;
+  };
+  union {
+    __IO uint32_t DDRE;
+    stc_gpio_ddre_field_t DDRE_f;
+  };
+  union {
+    __IO uint32_t DDRF;
+    stc_gpio_ddrf_field_t DDRF_f;
+  };
+        uint8_t RESERVED2[192];
+  union {
+    __IO uint32_t PDIR0;
+    stc_gpio_pdir0_field_t PDIR0_f;
+  };
+  union {
+    __IO uint32_t PDIR1;
+    stc_gpio_pdir1_field_t PDIR1_f;
+  };
+  union {
+    __IO uint32_t PDIR2;
+    stc_gpio_pdir2_field_t PDIR2_f;
+  };
+  union {
+    __IO uint32_t PDIR3;
+    stc_gpio_pdir3_field_t PDIR3_f;
+  };
+  union {
+    __IO uint32_t PDIR4;
+    stc_gpio_pdir4_field_t PDIR4_f;
+  };
+  union {
+    __IO uint32_t PDIR5;
+    stc_gpio_pdir5_field_t PDIR5_f;
+  };
+  union {
+    __IO uint32_t PDIR6;
+    stc_gpio_pdir6_field_t PDIR6_f;
+  };
+  union {
+    __IO uint32_t PDIR7;
+    stc_gpio_pdir7_field_t PDIR7_f;
+  };
+  union {
+    __IO uint32_t PDIR8;
+    stc_gpio_pdir8_field_t PDIR8_f;
+  };
+  __IO uint32_t PDIR9;
+  union {
+    __IO uint32_t PDIRA;
+    stc_gpio_pdira_field_t PDIRA_f;
+  };
+  __IO uint32_t PDIRB;
+  union {
+    __IO uint32_t PDIRC;
+    stc_gpio_pdirc_field_t PDIRC_f;
+  };
+  union {
+    __IO uint32_t PDIRD;
+    stc_gpio_pdird_field_t PDIRD_f;
+  };
+  union {
+    __IO uint32_t PDIRE;
+    stc_gpio_pdire_field_t PDIRE_f;
+  };
+  union {
+    __IO uint32_t PDIRF;
+    stc_gpio_pdirf_field_t PDIRF_f;
+  };
+        uint8_t RESERVED3[192];
+  union {
+    __IO uint32_t PDOR0;
+    stc_gpio_pdor0_field_t PDOR0_f;
+  };
+  union {
+    __IO uint32_t PDOR1;
+    stc_gpio_pdor1_field_t PDOR1_f;
+  };
+  union {
+    __IO uint32_t PDOR2;
+    stc_gpio_pdor2_field_t PDOR2_f;
+  };
+  union {
+    __IO uint32_t PDOR3;
+    stc_gpio_pdor3_field_t PDOR3_f;
+  };
+  union {
+    __IO uint32_t PDOR4;
+    stc_gpio_pdor4_field_t PDOR4_f;
+  };
+  union {
+    __IO uint32_t PDOR5;
+    stc_gpio_pdor5_field_t PDOR5_f;
+  };
+  union {
+    __IO uint32_t PDOR6;
+    stc_gpio_pdor6_field_t PDOR6_f;
+  };
+  union {
+    __IO uint32_t PDOR7;
+    stc_gpio_pdor7_field_t PDOR7_f;
+  };
+  union {
+    __IO uint32_t PDOR8;
+    stc_gpio_pdor8_field_t PDOR8_f;
+  };
+  __IO uint32_t PDOR9;
+  union {
+    __IO uint32_t PDORA;
+    stc_gpio_pdora_field_t PDORA_f;
+  };
+  __IO uint32_t PDORB;
+  union {
+    __IO uint32_t PDORC;
+    stc_gpio_pdorc_field_t PDORC_f;
+  };
+  union {
+    __IO uint32_t PDORD;
+    stc_gpio_pdord_field_t PDORD_f;
+  };
+  union {
+    __IO uint32_t PDORE;
+    stc_gpio_pdore_field_t PDORE_f;
+  };
+  union {
+    __IO uint32_t PDORF;
+    stc_gpio_pdorf_field_t PDORF_f;
+  };
+        uint8_t RESERVED4[192];
+  union {
+    __IO uint32_t ADE;
+    stc_gpio_ade_field_t ADE_f;
+  };
+        uint8_t RESERVED5[124];
+  union {
+    __IO uint32_t SPSR;
+    stc_gpio_spsr_field_t SPSR_f;
+  };
+        uint8_t RESERVED6[124];
+  union {
+    __IO uint32_t EPFR00;
+    stc_gpio_epfr00_field_t EPFR00_f;
+  };
+  union {
+    __IO uint32_t EPFR01;
+    stc_gpio_epfr01_field_t EPFR01_f;
+  };
+  union {
+    __IO uint32_t EPFR02;
+    stc_gpio_epfr02_field_t EPFR02_f;
+  };
+  union {
+    __IO uint32_t EPFR03;
+    stc_gpio_epfr03_field_t EPFR03_f;
+  };
+  union {
+    __IO uint32_t EPFR04;
+    stc_gpio_epfr04_field_t EPFR04_f;
+  };
+  union {
+    __IO uint32_t EPFR05;
+    stc_gpio_epfr05_field_t EPFR05_f;
+  };
+  union {
+    __IO uint32_t EPFR06;
+    stc_gpio_epfr06_field_t EPFR06_f;
+  };
+  union {
+    __IO uint32_t EPFR07;
+    stc_gpio_epfr07_field_t EPFR07_f;
+  };
+  union {
+    __IO uint32_t EPFR08;
+    stc_gpio_epfr08_field_t EPFR08_f;
+  };
+  union {
+    __IO uint32_t EPFR09;
+    stc_gpio_epfr09_field_t EPFR09_f;
+  };
+  union {
+    __IO uint32_t EPFR10;
+    stc_gpio_epfr10_field_t EPFR10_f;
+  };
+  union {
+    __IO uint32_t EPFR11;
+    stc_gpio_epfr11_field_t EPFR11_f;
+  };
+  union {
+    __IO uint32_t EPFR12;
+    stc_gpio_epfr12_field_t EPFR12_f;
+  };
+  union {
+    __IO uint32_t EPFR13;
+    stc_gpio_epfr13_field_t EPFR13_f;
+  };
+  union {
+    __IO uint32_t EPFR14;
+    stc_gpio_epfr14_field_t EPFR14_f;
+  };
+  union {
+    __IO uint32_t EPFR15;
+    stc_gpio_epfr15_field_t EPFR15_f;
+  };
+        uint8_t RESERVED7[192];
+  union {
+    __IO uint32_t PZR0;
+    stc_gpio_pzr0_field_t PZR0_f;
+  };
+  union {
+    __IO uint32_t PZR1;
+    stc_gpio_pzr1_field_t PZR1_f;
+  };
+  union {
+    __IO uint32_t PZR2;
+    stc_gpio_pzr2_field_t PZR2_f;
+  };
+  union {
+    __IO uint32_t PZR3;
+    stc_gpio_pzr3_field_t PZR3_f;
+  };
+  union {
+    __IO uint32_t PZR4;
+    stc_gpio_pzr4_field_t PZR4_f;
+  };
+  union {
+    __IO uint32_t PZR5;
+    stc_gpio_pzr5_field_t PZR5_f;
+  };
+  union {
+    __IO uint32_t PZR6;
+    stc_gpio_pzr6_field_t PZR6_f;
+  };
+  union {
+    __IO uint32_t PZR7;
+    stc_gpio_pzr7_field_t PZR7_f;
+  };
+  union {
+    __IO uint32_t PZR8;
+    stc_gpio_pzr8_field_t PZR8_f;
+  };
+  __IO uint32_t PZR9;
+  union {
+    __IO uint32_t PZRA;
+    stc_gpio_pzra_field_t PZRA_f;
+  };
+  __IO uint32_t PZRB;
+  union {
+    __IO uint32_t PZRC;
+    stc_gpio_pzrc_field_t PZRC_f;
+  };
+  union {
+    __IO uint32_t PZRD;
+    stc_gpio_pzrd_field_t PZRD_f;
+  };
+  union {
+    __IO uint32_t PZRE;
+    stc_gpio_pzre_field_t PZRE_f;
+  };
+  union {
+    __IO uint32_t PZRF;
+    stc_gpio_pzrf_field_t PZRF_f;
+  };
+}FM3_GPIO_TypeDef;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* Low voltage detection registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t LVD_CTL;
+    stc_lvd_lvd_ctl_field_t LVD_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t LVD_STR;
+    stc_lvd_lvd_str_field_t LVD_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t LVD_CLR;
+    stc_lvd_lvd_clr_field_t LVD_CLR_f;
+  };
+        uint8_t RESERVED2[3];
+  __IO uint32_t LVD_RLR;
+  union {
+    __IO  uint8_t LVD_STR2;
+    stc_lvd_lvd_str2_field_t LVD_STR2_f;
+  };
+}FM3_LVD_TypeDef;
+
+/******************************************************************************
+ * USBETHERNETCLK
+ ******************************************************************************/
+/* USB Ethernet clock registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t UCCR;
+    stc_usbethernetclk_uccr_field_t UCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t UPCR1;
+    stc_usbethernetclk_upcr1_field_t UPCR1_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t UPCR2;
+    stc_usbethernetclk_upcr2_field_t UPCR2_f;
+  };
+        uint8_t RESERVED2[3];
+  union {
+    __IO  uint8_t UPCR3;
+    stc_usbethernetclk_upcr3_field_t UPCR3_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t UPCR4;
+    stc_usbethernetclk_upcr4_field_t UPCR4_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t UP_STR;
+    stc_usbethernetclk_up_str_field_t UP_STR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t UPINT_ENR;
+    stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t UPINT_CLR;
+    stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO  uint8_t UPINT_STR;
+    stc_usbethernetclk_upint_str_field_t UPINT_STR_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t UPCR5;
+    stc_usbethernetclk_upcr5_field_t UPCR5_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t UPCR6;
+    stc_usbethernetclk_upcr6_field_t UPCR6_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t UPCR7;
+    stc_usbethernetclk_upcr7_field_t UPCR7_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t USBEN0;
+    stc_usbethernetclk_usben0_field_t USBEN0_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO  uint8_t USBEN1;
+    stc_usbethernetclk_usben1_field_t USBEN1_f;
+  };
+}FM3_USBETHERNETCLK_TypeDef;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs03_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs03_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_UART_TypeDef;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+}FM3_MFS03_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs03_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs03_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs03_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs03_i2c_ismk_field_t ISMK_f;
+  };
+}FM3_MFS03_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs47_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs47_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_uart_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_uart_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_uart_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_uart_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_uart_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_uart_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_UART_TypeDef;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_csio_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_csio_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_csio_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_csio_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_csio_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_csio_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_lin_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_lin_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_lin_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_lin_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_lin_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_lin_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs47_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs47_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs47_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs47_i2c_ismk_field_t ISMK_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_i2c_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_i2c_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_i2c_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_i2c_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct
+{
+  union {
+    __IO  uint16_t I2CDNF;
+    stc_mfs_nfc_i2cdnf_field_t I2CDNF_f;
+  };
+}FM3_MFS_NFC_TypeDef;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t CRCCR;
+    stc_crc_crccr_field_t CRCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t CRCINIT;
+  union {
+    __IO uint32_t CRCIN;
+    struct {
+      union {
+        __IO uint16_t CRCINL;
+        struct {
+          __IO  uint8_t CRCINLL;
+          __IO  uint8_t CRCINLH;
+        };
+      };
+      union {
+        __IO uint16_t CRCINH;
+        struct {
+          __IO  uint8_t CRCINHL;
+          __IO  uint8_t CRCINHH;
+        };
+      };
+    };
+  };
+  __IO uint32_t CRCR;
+}FM3_CRC_TypeDef;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* Watch counter registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t WCRD;
+    stc_wc_wcrd_field_t WCRD_f;
+  };
+  union {
+    __IO  uint8_t WCRL;
+    stc_wc_wcrl_field_t WCRL_f;
+  };
+  union {
+    __IO  uint8_t WCCR;
+    stc_wc_wccr_field_t WCCR_f;
+  };
+        uint8_t RESERVED0[13];
+  union {
+    __IO uint16_t CLK_SEL;
+    stc_wc_clk_sel_field_t CLK_SEL_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t CLK_EN;
+    stc_wc_clk_en_field_t CLK_EN_f;
+  };
+}FM3_WC_TypeDef;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* External bus interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MODE0;
+    stc_exbus_mode0_field_t MODE0_f;
+  };
+  union {
+    __IO uint32_t MODE1;
+    stc_exbus_mode1_field_t MODE1_f;
+  };
+  union {
+    __IO uint32_t MODE2;
+    stc_exbus_mode2_field_t MODE2_f;
+  };
+  union {
+    __IO uint32_t MODE3;
+    stc_exbus_mode3_field_t MODE3_f;
+  };
+  union {
+    __IO uint32_t MODE4;
+    stc_exbus_mode4_field_t MODE4_f;
+  };
+  union {
+    __IO uint32_t MODE5;
+    stc_exbus_mode5_field_t MODE5_f;
+  };
+  union {
+    __IO uint32_t MODE6;
+    stc_exbus_mode6_field_t MODE6_f;
+  };
+  union {
+    __IO uint32_t MODE7;
+    stc_exbus_mode7_field_t MODE7_f;
+  };
+  union {
+    __IO uint32_t TIM0;
+    stc_exbus_tim0_field_t TIM0_f;
+  };
+  union {
+    __IO uint32_t TIM1;
+    stc_exbus_tim1_field_t TIM1_f;
+  };
+  union {
+    __IO uint32_t TIM2;
+    stc_exbus_tim2_field_t TIM2_f;
+  };
+  union {
+    __IO uint32_t TIM3;
+    stc_exbus_tim3_field_t TIM3_f;
+  };
+  union {
+    __IO uint32_t TIM4;
+    stc_exbus_tim4_field_t TIM4_f;
+  };
+  union {
+    __IO uint32_t TIM5;
+    stc_exbus_tim5_field_t TIM5_f;
+  };
+  union {
+    __IO uint32_t TIM6;
+    stc_exbus_tim6_field_t TIM6_f;
+  };
+  union {
+    __IO uint32_t TIM7;
+    stc_exbus_tim7_field_t TIM7_f;
+  };
+  union {
+    __IO uint32_t AREA0;
+    stc_exbus_area0_field_t AREA0_f;
+  };
+  union {
+    __IO uint32_t AREA1;
+    stc_exbus_area1_field_t AREA1_f;
+  };
+  union {
+    __IO uint32_t AREA2;
+    stc_exbus_area2_field_t AREA2_f;
+  };
+  union {
+    __IO uint32_t AREA3;
+    stc_exbus_area3_field_t AREA3_f;
+  };
+  union {
+    __IO uint32_t AREA4;
+    stc_exbus_area4_field_t AREA4_f;
+  };
+  union {
+    __IO uint32_t AREA5;
+    stc_exbus_area5_field_t AREA5_f;
+  };
+  union {
+    __IO uint32_t AREA6;
+    stc_exbus_area6_field_t AREA6_f;
+  };
+  union {
+    __IO uint32_t AREA7;
+    stc_exbus_area7_field_t AREA7_f;
+  };
+  union {
+    __IO uint16_t ATIM0;
+    stc_exbus_atim0_field_t ATIM0_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO uint16_t ATIM1;
+    stc_exbus_atim1_field_t ATIM1_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t ATIM2;
+    stc_exbus_atim2_field_t ATIM2_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t ATIM3;
+    stc_exbus_atim3_field_t ATIM3_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t ATIM4;
+    stc_exbus_atim4_field_t ATIM4_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t ATIM5;
+    stc_exbus_atim5_field_t ATIM5_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t ATIM6;
+    stc_exbus_atim6_field_t ATIM6_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t ATIM7;
+    stc_exbus_atim7_field_t ATIM7_f;
+  };
+        uint8_t RESERVED7[642];
+  union {
+    __IO  uint8_t DCLKR;
+    stc_exbus_dclkr_field_t DCLKR_f;
+  };
+}FM3_EXBUS_TypeDef;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB channel 0 registers */
+typedef struct
+{
+  union {
+    union {
+      __IO uint16_t HCNT;
+      stc_usb_hcnt_field_t HCNT_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HCNT0;
+        stc_usb_hcnt0_field_t HCNT0_f;
+      };
+      union {
+        __IO  uint8_t HCNT1;
+        stc_usb_hcnt1_field_t HCNT1_f;
+      };
+    };
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t HIRQ;
+    stc_usb_hirq_field_t HIRQ_f;
+  };
+  union {
+    __IO  uint8_t HERR;
+    stc_usb_herr_field_t HERR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t HSTATE;
+    stc_usb_hstate_field_t HSTATE_f;
+  };
+  union {
+    __IO  uint8_t HFCOMP;
+    stc_usb_hfcomp_field_t HFCOMP_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t HRTIMER;
+      stc_usb_hrtimer_field_t HRTIMER_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HRTIMER0;
+        stc_usb_hrtimer0_field_t HRTIMER0_f;
+      };
+      union {
+        __IO  uint8_t HRTIMER1;
+        stc_usb_hrtimer1_field_t HRTIMER1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t HRTIMER2;
+    stc_usb_hrtimer2_field_t HRTIMER2_f;
+  };
+  union {
+    __IO  uint8_t HADR;
+    stc_usb_hadr_field_t HADR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t HEOF;
+      stc_usb_heof_field_t HEOF_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HEOF0;
+        stc_usb_heof0_field_t HEOF0_f;
+      };
+      union {
+        __IO  uint8_t HEOF1;
+        stc_usb_heof1_field_t HEOF1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t HFRAME;
+      stc_usb_hframe_field_t HFRAME_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HFRAME0;
+        stc_usb_hframe0_field_t HFRAME0_f;
+      };
+      union {
+        __IO  uint8_t HFRAME1;
+        stc_usb_hframe1_field_t HFRAME1_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t HTOKEN;
+    stc_usb_htoken_field_t HTOKEN_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t UDCC;
+    stc_usb_udcc_field_t UDCC_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t EP0C;
+    stc_usb_ep0c_field_t EP0C_f;
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO uint16_t EP1C;
+    stc_usb_ep1c_field_t EP1C_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t EP2C;
+    stc_usb_ep2c_field_t EP2C_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t EP3C;
+    stc_usb_ep3c_field_t EP3C_f;
+  };
+        uint8_t RESERVED12[2];
+  union {
+    __IO uint16_t EP4C;
+    stc_usb_ep4c_field_t EP4C_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO uint16_t EP5C;
+    stc_usb_ep5c_field_t EP5C_f;
+  };
+        uint8_t RESERVED14[2];
+  union {
+    __IO uint16_t TMSP;
+    stc_usb_tmsp_field_t TMSP_f;
+  };
+        uint8_t RESERVED15[2];
+  union {
+    __IO  uint8_t UDCS;
+    stc_usb_udcs_field_t UDCS_f;
+  };
+  union {
+    __IO  uint8_t UDCIE;
+    stc_usb_udcie_field_t UDCIE_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t EP0IS;
+    stc_usb_ep0is_field_t EP0IS_f;
+  };
+        uint8_t RESERVED17[2];
+  union {
+    __IO uint16_t EP0OS;
+    stc_usb_ep0os_field_t EP0OS_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t EP1S;
+    stc_usb_ep1s_field_t EP1S_f;
+  };
+        uint8_t RESERVED19[2];
+  union {
+    __IO uint16_t EP2S;
+    stc_usb_ep2s_field_t EP2S_f;
+  };
+        uint8_t RESERVED20[2];
+  __IO uint16_t EP3S;
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t EP4S;
+    stc_usb_ep4s_field_t EP4S_f;
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t EP5S;
+    stc_usb_ep5s_field_t EP5S_f;
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t EP0DT;
+    struct {
+      __IO  uint8_t EP0DTL;
+      __IO  uint8_t EP0DTH;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t EP1DT;
+    struct {
+      __IO  uint8_t EP1DTL;
+      __IO  uint8_t EP1DTH;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO uint16_t EP2DT;
+    struct {
+      __IO  uint8_t EP2DTL;
+      __IO  uint8_t EP2DTH;
+    };
+  };
+        uint8_t RESERVED26[2];
+  union {
+    __IO uint16_t EP3DT;
+    struct {
+      __IO  uint8_t EP3DTL;
+      __IO  uint8_t EP3DTH;
+    };
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO uint16_t EP4DT;
+    struct {
+      __IO  uint8_t EP4DTL;
+      __IO  uint8_t EP4DTH;
+    };
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t EP5DT;
+    struct {
+      __IO  uint8_t EP5DTL;
+      __IO  uint8_t EP5DTH;
+    };
+  };
+}FM3_USB_TypeDef;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMA controller */
+typedef struct
+{
+  union {
+    __IO uint32_t DMACR;
+    stc_dmac_dmacr_field_t DMACR_f;
+  };
+        uint8_t RESERVED0[12];
+  union {
+    __IO uint32_t DMACA0;
+    stc_dmac_dmaca0_field_t DMACA0_f;
+  };
+  union {
+    __IO uint32_t DMACB0;
+    stc_dmac_dmacb0_field_t DMACB0_f;
+  };
+  __IO uint32_t DMACSA0;
+  __IO uint32_t DMACDA0;
+  union {
+    __IO uint32_t DMACA1;
+    stc_dmac_dmaca1_field_t DMACA1_f;
+  };
+  union {
+    __IO uint32_t DMACB1;
+    stc_dmac_dmacb1_field_t DMACB1_f;
+  };
+  __IO uint32_t DMACSA1;
+  __IO uint32_t DMACDA1;
+  union {
+    __IO uint32_t DMACA2;
+    stc_dmac_dmaca2_field_t DMACA2_f;
+  };
+  union {
+    __IO uint32_t DMACB2;
+    stc_dmac_dmacb2_field_t DMACB2_f;
+  };
+  __IO uint32_t DMACSA2;
+  __IO uint32_t DMACDA2;
+  union {
+    __IO uint32_t DMACA3;
+    stc_dmac_dmaca3_field_t DMACA3_f;
+  };
+  union {
+    __IO uint32_t DMACB3;
+    stc_dmac_dmacb3_field_t DMACB3_f;
+  };
+  __IO uint32_t DMACSA3;
+  __IO uint32_t DMACDA3;
+  union {
+    __IO uint32_t DMACA4;
+    stc_dmac_dmaca4_field_t DMACA4_f;
+  };
+  union {
+    __IO uint32_t DMACB4;
+    stc_dmac_dmacb4_field_t DMACB4_f;
+  };
+  __IO uint32_t DMACSA4;
+  __IO uint32_t DMACDA4;
+  union {
+    __IO uint32_t DMACA5;
+    stc_dmac_dmaca5_field_t DMACA5_f;
+  };
+  union {
+    __IO uint32_t DMACB5;
+    stc_dmac_dmacb5_field_t DMACB5_f;
+  };
+  __IO uint32_t DMACSA5;
+  __IO uint32_t DMACDA5;
+  union {
+    __IO uint32_t DMACA6;
+    stc_dmac_dmaca6_field_t DMACA6_f;
+  };
+  union {
+    __IO uint32_t DMACB6;
+    stc_dmac_dmacb6_field_t DMACB6_f;
+  };
+  __IO uint32_t DMACSA6;
+  __IO uint32_t DMACDA6;
+  union {
+    __IO uint32_t DMACA7;
+    stc_dmac_dmaca7_field_t DMACA7_f;
+  };
+  union {
+    __IO uint32_t DMACB7;
+    stc_dmac_dmacb7_field_t DMACB7_f;
+  };
+  __IO uint32_t DMACSA7;
+  __IO uint32_t DMACDA7;
+}FM3_DMAC_TypeDef;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET-MAC registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MCR;
+    stc_ethernet_mac_mcr_field_t MCR_f;
+  };
+  union {
+    __IO uint32_t MFFR;
+    stc_ethernet_mac_mffr_field_t MFFR_f;
+  };
+  union {
+    __IO uint32_t MHTRH;
+    stc_ethernet_mac_mhtrh_field_t MHTRH_f;
+  };
+  union {
+    __IO uint32_t MHTRL;
+    stc_ethernet_mac_mhtrl_field_t MHTRL_f;
+  };
+  union {
+    __IO uint32_t GAR;
+    stc_ethernet_mac_gar_field_t GAR_f;
+  };
+  union {
+    __IO uint32_t GDR;
+    stc_ethernet_mac_gdr_field_t GDR_f;
+  };
+  union {
+    __IO uint32_t FCR;
+    stc_ethernet_mac_fcr_field_t FCR_f;
+  };
+  union {
+    __IO uint32_t VTR;
+    stc_ethernet_mac_vtr_field_t VTR_f;
+  };
+        uint8_t RESERVED0[8];
+  union {
+    __IO uint32_t RWFFR;
+    stc_ethernet_mac_rwffr_field_t RWFFR_f;
+  };
+  union {
+    __IO uint32_t PMTR;
+    stc_ethernet_mac_pmtr_field_t PMTR_f;
+  };
+  union {
+    __IO uint32_t LPICSR;
+    stc_ethernet_mac_lpicsr_field_t LPICSR_f;
+  };
+  union {
+    __IO uint32_t LPITCR;
+    stc_ethernet_mac_lpitcr_field_t LPITCR_f;
+  };
+  union {
+    __IO uint32_t ISR;
+    stc_ethernet_mac_isr_field_t ISR_f;
+  };
+  union {
+    __IO uint32_t IMR;
+    stc_ethernet_mac_imr_field_t IMR_f;
+  };
+  union {
+    __IO uint32_t MAR0H;
+    stc_ethernet_mac_mar0h_field_t MAR0H_f;
+  };
+  union {
+    __IO uint32_t MAR0L;
+    stc_ethernet_mac_mar0l_field_t MAR0L_f;
+  };
+  union {
+    __IO uint32_t MAR1H;
+    stc_ethernet_mac_mar1h_field_t MAR1H_f;
+  };
+  union {
+    __IO uint32_t MAR1L;
+    stc_ethernet_mac_mar1l_field_t MAR1L_f;
+  };
+  union {
+    __IO uint32_t MAR2H;
+    stc_ethernet_mac_mar2h_field_t MAR2H_f;
+  };
+  union {
+    __IO uint32_t MAR2L;
+    stc_ethernet_mac_mar2l_field_t MAR2L_f;
+  };
+  union {
+    __IO uint32_t MAR3H;
+    stc_ethernet_mac_mar3h_field_t MAR3H_f;
+  };
+  union {
+    __IO uint32_t MAR3L;
+    stc_ethernet_mac_mar3l_field_t MAR3L_f;
+  };
+  union {
+    __IO uint32_t MAR4H;
+    stc_ethernet_mac_mar4h_field_t MAR4H_f;
+  };
+  union {
+    __IO uint32_t MAR4L;
+    stc_ethernet_mac_mar4l_field_t MAR4L_f;
+  };
+  union {
+    __IO uint32_t MAR5H;
+    stc_ethernet_mac_mar5h_field_t MAR5H_f;
+  };
+  union {
+    __IO uint32_t MAR5L;
+    stc_ethernet_mac_mar5l_field_t MAR5L_f;
+  };
+  union {
+    __IO uint32_t MAR6H;
+    stc_ethernet_mac_mar6h_field_t MAR6H_f;
+  };
+  union {
+    __IO uint32_t MAR6L;
+    stc_ethernet_mac_mar6l_field_t MAR6L_f;
+  };
+  union {
+    __IO uint32_t MAR7H;
+    stc_ethernet_mac_mar7h_field_t MAR7H_f;
+  };
+  union {
+    __IO uint32_t MAR7L;
+    stc_ethernet_mac_mar7l_field_t MAR7L_f;
+  };
+  union {
+    __IO uint32_t MAR8H;
+    stc_ethernet_mac_mar8h_field_t MAR8H_f;
+  };
+  union {
+    __IO uint32_t MAR8L;
+    stc_ethernet_mac_mar8l_field_t MAR8L_f;
+  };
+  union {
+    __IO uint32_t MAR9H;
+    stc_ethernet_mac_mar9h_field_t MAR9H_f;
+  };
+  union {
+    __IO uint32_t MAR9L;
+    stc_ethernet_mac_mar9l_field_t MAR9L_f;
+  };
+  union {
+    __IO uint32_t MAR10H;
+    stc_ethernet_mac_mar10h_field_t MAR10H_f;
+  };
+  union {
+    __IO uint32_t MAR10L;
+    stc_ethernet_mac_mar10l_field_t MAR10L_f;
+  };
+  union {
+    __IO uint32_t MAR11H;
+    stc_ethernet_mac_mar11h_field_t MAR11H_f;
+  };
+  union {
+    __IO uint32_t MAR11L;
+    stc_ethernet_mac_mar11l_field_t MAR11L_f;
+  };
+  union {
+    __IO uint32_t MAR12H;
+    stc_ethernet_mac_mar12h_field_t MAR12H_f;
+  };
+  union {
+    __IO uint32_t MAR12L;
+    stc_ethernet_mac_mar12l_field_t MAR12L_f;
+  };
+  union {
+    __IO uint32_t MAR13H;
+    stc_ethernet_mac_mar13h_field_t MAR13H_f;
+  };
+  union {
+    __IO uint32_t MAR13L;
+    stc_ethernet_mac_mar13l_field_t MAR13L_f;
+  };
+  union {
+    __IO uint32_t MAR14H;
+    stc_ethernet_mac_mar14h_field_t MAR14H_f;
+  };
+  union {
+    __IO uint32_t MAR14L;
+    stc_ethernet_mac_mar14l_field_t MAR14L_f;
+  };
+  union {
+    __IO uint32_t MAR15H;
+    stc_ethernet_mac_mar15h_field_t MAR15H_f;
+  };
+  union {
+    __IO uint32_t MAR15L;
+    stc_ethernet_mac_mar15l_field_t MAR15L_f;
+  };
+        uint8_t RESERVED1[24];
+  union {
+    __IO uint32_t RGSR;
+    stc_ethernet_mac_rgsr_field_t RGSR_f;
+  };
+        uint8_t RESERVED2[36];
+  __IO uint32_t mmc_cntl;
+  __IO uint32_t mmc_intr_rx;
+  __IO uint32_t mmc_intr_tx;
+  __IO uint32_t mmc_intr_mask_rx;
+  __IO uint32_t mmc_intr_mask_tx;
+  __IO uint32_t txoctetcount_gb;
+  __IO uint32_t txframecount_gb;
+  __IO uint32_t txbroadcastframes_g;
+  __IO uint32_t txmulticastframes_g;
+  __IO uint32_t tx64octets_gb;
+  __IO uint32_t tx65to127octets_gb;
+  __IO uint32_t tx128to255octets_gb;
+  __IO uint32_t tx256to511octets_gb;
+  __IO uint32_t tx512to1023octets_gb;
+  __IO uint32_t tx1024tomaxoctets_gb;
+  __IO uint32_t txunicastframes_gb;
+  __IO uint32_t txmulticastframes_gb;
+  __IO uint32_t txbroadcastframes_gb;
+  __IO uint32_t txunderflowerror;
+  __IO uint32_t txsinglecol_g;
+  __IO uint32_t txmulticol_g;
+  __IO uint32_t txdeferred;
+  __IO uint32_t txlatecol;
+  __IO uint32_t txexesscol;
+  __IO uint32_t txcarriererror;
+  __IO uint32_t txoctetcount_g;
+  __IO uint32_t txframecount_g;
+  __IO uint32_t txexecessdef_g;
+  __IO uint32_t txpauseframes;
+  __IO uint32_t txvlanframes_g;
+        uint8_t RESERVED3[8];
+  __IO uint32_t rxframecount_gb;
+  __IO uint32_t rxoctetcount_gb;
+  __IO uint32_t rxoctetcount_g;
+  __IO uint32_t rxbroadcastframes_g;
+  __IO uint32_t rxmulticastframes_g;
+  __IO uint32_t rxcrcerror;
+  __IO uint32_t rxallignmenterror;
+  __IO uint32_t rxrunterror;
+  __IO uint32_t rxjabbererror;
+  __IO uint32_t rxundersize_g;
+  __IO uint32_t rxoversize_g;
+  __IO uint32_t rx64octets_gb;
+  __IO uint32_t rx65to127octets_gb;
+  __IO uint32_t rx128to255octets_gb;
+  __IO uint32_t rx256to511octets_gb;
+  __IO uint32_t rx512to1023octets_gb;
+  __IO uint32_t rx1024tomaxoctets_gb;
+  __IO uint32_t rxunicastframes_g;
+  __IO uint32_t rxlengtherror;
+  __IO uint32_t rxoutofrangetype;
+  __IO uint32_t rxpauseframes;
+  __IO uint32_t rxfifooverflow;
+  __IO uint32_t rxvlanframes_gb;
+  __IO uint32_t rxwatchdogerror;
+        uint8_t RESERVED4[32];
+  __IO uint32_t mmc_ipc_intr_mask_rx;
+        uint8_t RESERVED5[4];
+  __IO uint32_t mmc_ipc_intr_rx;
+        uint8_t RESERVED6[4];
+  __IO uint32_t rxipv4_gd_frms;
+  __IO uint32_t rxipv4_hdrerr_frms;
+  __IO uint32_t rxipv4_nopay_frms;
+  __IO uint32_t rxipv4_frag_frms;
+  __IO uint32_t rxipv4_udsbl_frms;
+  __IO uint32_t rxipv6_gd_frms;
+  __IO uint32_t rxipv6_hdrerr_frms;
+  __IO uint32_t rxipv6_nopay_frms;
+  __IO uint32_t rxudp_gd_frms;
+  __IO uint32_t rxudp_err_frms;
+  __IO uint32_t rxtcp_gd_frms;
+  __IO uint32_t rxtcp_err_frms;
+  __IO uint32_t rxicmp_gd_frms;
+  __IO uint32_t rxicmp_err_frms;
+        uint8_t RESERVED7[8];
+  __IO uint32_t rxipv4_gd_octets;
+  __IO uint32_t rxipv4_hdrerr_octets;
+  __IO uint32_t rxipv4_nopay_octets;
+  __IO uint32_t rxipv4_frag_octets;
+  __IO uint32_t rxipv4_udsbl_octets;
+  __IO uint32_t rxipv6_gd_octets;
+  __IO uint32_t rxipv6_hdrerr_octets;
+  __IO uint32_t rxipv6_nopay_octets;
+  __IO uint32_t rxudp_gd_octets;
+  __IO uint32_t rxudp_err_octets;
+  __IO uint32_t rxtcp_gd_octets;
+  __IO uint32_t rxtcp_err_octets;
+  __IO uint32_t rxicmp_gd_octets;
+  __IO uint32_t rxicmp_err_octets;
+        uint8_t RESERVED8[1144];
+  union {
+    __IO uint32_t TSCR;
+    stc_ethernet_mac_tscr_field_t TSCR_f;
+  };
+  union {
+    __IO uint32_t SSIR;
+    stc_ethernet_mac_ssir_field_t SSIR_f;
+  };
+  union {
+    __IO uint32_t STSR;
+    stc_ethernet_mac_stsr_field_t STSR_f;
+  };
+  union {
+    __IO uint32_t STNR;
+    stc_ethernet_mac_stnr_field_t STNR_f;
+  };
+  union {
+    __IO uint32_t STSUR;
+    stc_ethernet_mac_stsur_field_t STSUR_f;
+  };
+  union {
+    __IO uint32_t STNUR;
+    stc_ethernet_mac_stnur_field_t STNUR_f;
+  };
+  union {
+    __IO uint32_t TSAR;
+    stc_ethernet_mac_tsar_field_t TSAR_f;
+  };
+  union {
+    __IO uint32_t TTSR;
+    stc_ethernet_mac_ttsr_field_t TTSR_f;
+  };
+  union {
+    __IO uint32_t TTNR;
+    stc_ethernet_mac_ttnr_field_t TTNR_f;
+  };
+  union {
+    __IO uint32_t STHWSR;
+    stc_ethernet_mac_sthwsr_field_t STHWSR_f;
+  };
+  union {
+    __IO uint32_t TSR;
+    stc_ethernet_mac_tsr_field_t TSR_f;
+  };
+  union {
+    __IO uint32_t PPSCR;
+    stc_ethernet_mac_ppscr_field_t PPSCR_f;
+  };
+  union {
+    __IO uint32_t ATNR;
+    stc_ethernet_mac_atnr_field_t ATNR_f;
+  };
+  union {
+    __IO uint32_t ATSR;
+    stc_ethernet_mac_atsr_field_t ATSR_f;
+  };
+        uint8_t RESERVED9[200];
+  union {
+    __IO uint32_t MAR16H;
+    stc_ethernet_mac_mar16h_field_t MAR16H_f;
+  };
+  union {
+    __IO uint32_t MAR16L;
+    stc_ethernet_mac_mar16l_field_t MAR16L_f;
+  };
+  union {
+    __IO uint32_t MAR17H;
+    stc_ethernet_mac_mar17h_field_t MAR17H_f;
+  };
+  union {
+    __IO uint32_t MAR17L;
+    stc_ethernet_mac_mar17l_field_t MAR17L_f;
+  };
+  union {
+    __IO uint32_t MAR18H;
+    stc_ethernet_mac_mar18h_field_t MAR18H_f;
+  };
+  union {
+    __IO uint32_t MAR18L;
+    stc_ethernet_mac_mar18l_field_t MAR18L_f;
+  };
+  union {
+    __IO uint32_t MAR19H;
+    stc_ethernet_mac_mar19h_field_t MAR19H_f;
+  };
+  union {
+    __IO uint32_t MAR19L;
+    stc_ethernet_mac_mar19l_field_t MAR19L_f;
+  };
+  union {
+    __IO uint32_t MAR20H;
+    stc_ethernet_mac_mar20h_field_t MAR20H_f;
+  };
+  union {
+    __IO uint32_t MAR20L;
+    stc_ethernet_mac_mar20l_field_t MAR20L_f;
+  };
+  union {
+    __IO uint32_t MAR21H;
+    stc_ethernet_mac_mar21h_field_t MAR21H_f;
+  };
+  union {
+    __IO uint32_t MAR21L;
+    stc_ethernet_mac_mar21l_field_t MAR21L_f;
+  };
+  union {
+    __IO uint32_t MAR22H;
+    stc_ethernet_mac_mar22h_field_t MAR22H_f;
+  };
+  union {
+    __IO uint32_t MAR22L;
+    stc_ethernet_mac_mar22l_field_t MAR22L_f;
+  };
+  union {
+    __IO uint32_t MAR23H;
+    stc_ethernet_mac_mar23h_field_t MAR23H_f;
+  };
+  union {
+    __IO uint32_t MAR23L;
+    stc_ethernet_mac_mar23l_field_t MAR23L_f;
+  };
+  union {
+    __IO uint32_t MAR24H;
+    stc_ethernet_mac_mar24h_field_t MAR24H_f;
+  };
+  union {
+    __IO uint32_t MAR24L;
+    stc_ethernet_mac_mar24l_field_t MAR24L_f;
+  };
+  union {
+    __IO uint32_t MAR25H;
+    stc_ethernet_mac_mar25h_field_t MAR25H_f;
+  };
+  union {
+    __IO uint32_t MAR25L;
+    stc_ethernet_mac_mar25l_field_t MAR25L_f;
+  };
+  union {
+    __IO uint32_t MAR26H;
+    stc_ethernet_mac_mar26h_field_t MAR26H_f;
+  };
+  union {
+    __IO uint32_t MAR26L;
+    stc_ethernet_mac_mar26l_field_t MAR26L_f;
+  };
+  union {
+    __IO uint32_t MAR27H;
+    stc_ethernet_mac_mar27h_field_t MAR27H_f;
+  };
+  union {
+    __IO uint32_t MAR27L;
+    stc_ethernet_mac_mar27l_field_t MAR27L_f;
+  };
+  union {
+    __IO uint32_t MAR28H;
+    stc_ethernet_mac_mar28h_field_t MAR28H_f;
+  };
+  union {
+    __IO uint32_t MAR28L;
+    stc_ethernet_mac_mar28l_field_t MAR28L_f;
+  };
+  union {
+    __IO uint32_t MAR29H;
+    stc_ethernet_mac_mar29h_field_t MAR29H_f;
+  };
+  union {
+    __IO uint32_t MAR29L;
+    stc_ethernet_mac_mar29l_field_t MAR29L_f;
+  };
+  union {
+    __IO uint32_t MAR30H;
+    stc_ethernet_mac_mar30h_field_t MAR30H_f;
+  };
+  union {
+    __IO uint32_t MAR30L;
+    stc_ethernet_mac_mar30l_field_t MAR30L_f;
+  };
+  union {
+    __IO uint32_t MAR31H;
+    stc_ethernet_mac_mar31h_field_t MAR31H_f;
+  };
+  union {
+    __IO uint32_t MAR31L;
+    stc_ethernet_mac_mar31l_field_t MAR31L_f;
+  };
+        uint8_t RESERVED10[1920];
+  union {
+    __IO uint32_t BMR;
+    stc_ethernet_mac_bmr_field_t BMR_f;
+  };
+  union {
+    __IO uint32_t TPDR;
+    stc_ethernet_mac_tpdr_field_t TPDR_f;
+  };
+  union {
+    __IO uint32_t RPDR;
+    stc_ethernet_mac_rpdr_field_t RPDR_f;
+  };
+  union {
+    __IO uint32_t RDLAR;
+    stc_ethernet_mac_rdlar_field_t RDLAR_f;
+  };
+  union {
+    __IO uint32_t TDLAR;
+    stc_ethernet_mac_tdlar_field_t TDLAR_f;
+  };
+  union {
+    __IO uint32_t SR;
+    stc_ethernet_mac_sr_field_t SR_f;
+  };
+  union {
+    __IO uint32_t OMR;
+    stc_ethernet_mac_omr_field_t OMR_f;
+  };
+  union {
+    __IO uint32_t IER;
+    stc_ethernet_mac_ier_field_t IER_f;
+  };
+  union {
+    __IO uint32_t MFBOCR;
+    stc_ethernet_mac_mfbocr_field_t MFBOCR_f;
+  };
+  union {
+    __IO uint32_t RIWTR;
+    stc_ethernet_mac_riwtr_field_t RIWTR_f;
+  };
+        uint8_t RESERVED11[4];
+  union {
+    __IO uint32_t AHBSR;
+    stc_ethernet_mac_ahbsr_field_t AHBSR_f;
+  };
+        uint8_t RESERVED12[24];
+  union {
+    __IO uint32_t CHTDR;
+    stc_ethernet_mac_chtdr_field_t CHTDR_f;
+  };
+  union {
+    __IO uint32_t CHRDR;
+    stc_ethernet_mac_chrdr_field_t CHRDR_f;
+  };
+  union {
+    __IO uint32_t CHTBAR;
+    stc_ethernet_mac_chtbar_field_t CHTBAR_f;
+  };
+  union {
+    __IO uint32_t CHRBAR;
+    stc_ethernet_mac_chrbar_field_t CHRBAR_f;
+  };
+}FM3_ETHERNET_MAC_TypeDef;
+
+/* ETHERNET-CONTROL registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ETH_MODE;
+    stc_ethernet_control_eth_mode_field_t ETH_MODE_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t ETH_CLKG;
+    stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f;
+  };
+}FM3_ETHERNET_CONTROL_TypeDef;
+
+/******************************************************************************
+ * Peripheral memory map
+ ******************************************************************************/
+#define FM3_FLASH_BASE        (0x00000000UL)                 /* Flash Base                             */
+#define FM3_PERIPH_BASE       (0x40000000UL)                 /* Peripheral  Base                       */
+#define FM3_CM3_BASE          (0xE0100000UL)                 /* CM3 Private                            */
+
+#define FM3_FLASH_IF_BASE     (FM3_PERIPH_BASE + 0x00000UL)  /* Flash interface registers              */
+#define FM3_CRG_BASE          (FM3_PERIPH_BASE + 0x10000UL)  /* Clock and reset registers              */
+#define FM3_HWWDT_BASE        (FM3_PERIPH_BASE + 0x11000UL)  /* Hardware watchdog registers            */
+#define FM3_SWWDT_BASE        (FM3_PERIPH_BASE + 0x12000UL)  /* Software watchdog registers            */
+#define FM3_DTIM_BASE         (FM3_PERIPH_BASE + 0x15000UL)  /* Dual timer 1/2 registers               */
+#define FM3_MFT0_FRT_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Free Running Timer registers */
+#define FM3_MFT0_OCU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Output Compare Unit registers */
+#define FM3_MFT0_WFG_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT0_ICU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Input Capture Unit registers */
+#define FM3_MFT0_ADCMP_BASE   (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define FM3_MFT1_FRT_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Free Running Timer registers */
+#define FM3_MFT1_OCU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Output Compare Unit registers */
+#define FM3_MFT1_WFG_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT1_ICU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Input Capture Unit registers */
+#define FM3_MFT1_ADCMP_BASE   (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define FM3_MFT2_FRT_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Free Running Timer registers */
+#define FM3_MFT2_OCU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Output Compare Unit registers */
+#define FM3_MFT2_WFG_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT2_ICU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Input Capture Unit registers */
+#define FM3_MFT2_ADCMP_BASE   (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define FM3_MFT_PPG_BASE      (FM3_PERIPH_BASE + 0x24000UL)  /* Multifunction Timer PPG registers      */
+#define FM3_BT0_PPG_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PPG registers             */
+#define FM3_BT0_PWM_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWM registers             */
+#define FM3_BT0_RT_BASE       (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 RT registers              */
+#define FM3_BT0_PWC_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWC registers             */
+#define FM3_BT1_PPG_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PPG registers             */
+#define FM3_BT1_PWM_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWM registers             */
+#define FM3_BT1_RT_BASE       (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 RT registers              */
+#define FM3_BT1_PWC_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWC registers             */
+#define FM3_BT2_PPG_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PPG registers             */
+#define FM3_BT2_PWM_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWM registers             */
+#define FM3_BT2_RT_BASE       (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 RT registers              */
+#define FM3_BT2_PWC_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWC registers             */
+#define FM3_BT3_PPG_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PPG registers             */
+#define FM3_BT3_PWM_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWM registers             */
+#define FM3_BT3_RT_BASE       (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 RT registers              */
+#define FM3_BT3_PWC_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWC registers             */
+#define FM3_BT4_PPG_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PPG registers             */
+#define FM3_BT4_PWM_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWM registers             */
+#define FM3_BT4_RT_BASE       (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 RT registers              */
+#define FM3_BT4_PWC_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWC registers             */
+#define FM3_BT5_PPG_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PPG registers             */
+#define FM3_BT5_PWM_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWM registers             */
+#define FM3_BT5_RT_BASE       (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 RT registers              */
+#define FM3_BT5_PWC_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWC registers             */
+#define FM3_BT6_PPG_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PPG registers             */
+#define FM3_BT6_PWM_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWM registers             */
+#define FM3_BT6_RT_BASE       (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 RT registers              */
+#define FM3_BT6_PWC_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWC registers             */
+#define FM3_BT7_PPG_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PPG registers             */
+#define FM3_BT7_PWM_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWM registers             */
+#define FM3_BT7_RT_BASE       (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 RT registers              */
+#define FM3_BT7_PWC_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWC registers             */
+#define FM3_BTIOSEL03_BASE    (FM3_PERIPH_BASE + 0x25100UL)  /* Base Timer I/O selector channel 0 - channel 3 registers */
+#define FM3_BTIOSEL47_BASE    (FM3_PERIPH_BASE + 0x25300UL)  /* Base Timer I/O selector channel 4 - channel 7 registers */
+#define FM3_BT8_PPG_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT8_PWM_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT8_RT_BASE       (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT8_PWC_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT9_PPG_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT9_PWM_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT9_RT_BASE       (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT9_PWC_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT10_PPG_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT10_PWM_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT10_RT_BASE      (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT10_PWC_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT11_PPG_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT11_PWM_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT11_RT_BASE      (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT11_PWC_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BT12_PPG_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT12_PWM_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT12_RT_BASE      (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT12_PWC_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT13_PPG_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT13_PWM_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT13_RT_BASE      (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT13_PWC_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT14_PPG_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT14_PWM_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT14_RT_BASE      (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT14_PWC_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT15_PPG_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT15_PWM_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT15_RT_BASE      (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT15_PWC_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BTIOSEL8B_BASE    (FM3_PERIPH_BASE + 0x25500UL)  /* Base Timer I/O selector channel 8 - channel 11 registers */
+#define FM3_BTIOSELCF_BASE    (FM3_PERIPH_BASE + 0x25700UL)  /* Base Timer I/O selector channel 12 - channel 15 registers */
+#define FM3_SBSSR_BASE        (FM3_PERIPH_BASE + 0x25FFCUL)  /* Software based Simulation Startup (Base Timer) register */
+#define FM3_QPRC0_BASE        (FM3_PERIPH_BASE + 0x26000UL)  /* Quad position and revolution counter channel 0 registers */
+#define FM3_QPRC1_BASE        (FM3_PERIPH_BASE + 0x26040UL)  /* Quad position and revolution counter channel 1 registers */
+#define FM3_QPRC2_BASE        (FM3_PERIPH_BASE + 0x26080UL)  /* Quad position and revolution counter channel 2 registers */
+#define FM3_ADC0_BASE         (FM3_PERIPH_BASE + 0x27000UL)  /* 12-bit ADC unit 0 registers            */
+#define FM3_ADC1_BASE         (FM3_PERIPH_BASE + 0x27100UL)  /* 12-bit ADC unit 1 registers            */
+#define FM3_ADC2_BASE         (FM3_PERIPH_BASE + 0x27200UL)  /* 12-bit ADC unit 2 registers            */
+#define FM3_CRTRIM_BASE       (FM3_PERIPH_BASE + 0x2E000UL)  /* CR trimming registers                  */
+#define FM3_EXTI_BASE         (FM3_PERIPH_BASE + 0x30000UL)  /* External interrupt registers           */
+#define FM3_INTREQ_BASE       (FM3_PERIPH_BASE + 0x31000UL)  /* Interrupt request read registers       */
+#define FM3_GPIO_BASE         (FM3_PERIPH_BASE + 0x33000UL)  /* General purpose I/O registers          */
+#define FM3_LVD_BASE          (FM3_PERIPH_BASE + 0x35000UL)  /* Low voltage detection registers        */
+#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL)  /* USB clock registers                    */
+#define FM3_MFS0_UART_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART asynchronous channel 0 registers  */
+#define FM3_MFS0_CSIO_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART synchronous channel 0 registers   */
+#define FM3_MFS0_LIN_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* UART LIN channel 0 registers           */
+#define FM3_MFS0_I2C_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* I2C channel 0 registers                */
+#define FM3_MFS1_UART_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART asynchronous channel 1 registers  */
+#define FM3_MFS1_CSIO_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART synchronous channel 1 registers   */
+#define FM3_MFS1_LIN_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* UART LIN channel 1 registers           */
+#define FM3_MFS1_I2C_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* I2C channel 1 registers                */
+#define FM3_MFS2_UART_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART asynchronous channel 2 registers  */
+#define FM3_MFS2_CSIO_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART synchronous channel 2 registers   */
+#define FM3_MFS2_LIN_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* UART LIN channel 2 registers           */
+#define FM3_MFS2_I2C_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* I2C channel 2 registers                */
+#define FM3_MFS3_UART_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART asynchronous channel 3 registers  */
+#define FM3_MFS3_CSIO_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART synchronous channel 3 registers   */
+#define FM3_MFS3_LIN_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* UART LIN channel 3 registers           */
+#define FM3_MFS3_I2C_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* I2C channel 3 registers                */
+#define FM3_MFS4_UART_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART asynchronous channel 4 registers  */
+#define FM3_MFS4_CSIO_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART synchronous channel 4 registers   */
+#define FM3_MFS4_LIN_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* UART LIN channel 4 registers           */
+#define FM3_MFS4_I2C_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* I2C channel 4 registers                */
+#define FM3_MFS5_UART_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART asynchronous channel 5 registers  */
+#define FM3_MFS5_CSIO_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART synchronous channel 5 registers   */
+#define FM3_MFS5_LIN_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* UART LIN channel 5 registers           */
+#define FM3_MFS5_I2C_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* I2C channel 5 registers                */
+#define FM3_MFS6_UART_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART asynchronous channel 6 registers  */
+#define FM3_MFS6_CSIO_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART synchronous channel 6 registers   */
+#define FM3_MFS6_LIN_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* UART LIN channel 6 registers           */
+#define FM3_MFS6_I2C_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* I2C channel 6 registers                */
+#define FM3_MFS7_UART_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART asynchronous channel 7 registers  */
+#define FM3_MFS7_CSIO_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART synchronous channel 7 registers   */
+#define FM3_MFS7_LIN_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* UART LIN channel 7 registers           */
+#define FM3_MFS7_I2C_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* I2C channel 7 registers                */
+#define FM3_MFS_NFC_BASE      (FM3_PERIPH_BASE + 0x38800UL)  /* MFS Noise Filter Control register      */
+#define FM3_CRC_BASE          (FM3_PERIPH_BASE + 0x39000UL)  /* CRC registers                          */
+#define FM3_WC_BASE           (FM3_PERIPH_BASE + 0x3A000UL)  /* Watch counter registers                */
+#define FM3_EXBUS_BASE        (FM3_PERIPH_BASE + 0x3F000UL)  /* External bus interface registers       */
+#define FM3_USB0_BASE         (FM3_PERIPH_BASE + 0x42100UL)  /* USB channel 0 registers                */
+#define FM3_USB1_BASE         (FM3_PERIPH_BASE + 0x52100UL)  /* USB channel 1 registers                */
+#define FM3_DMAC_BASE         (FM3_PERIPH_BASE + 0x60000UL)  /* DMA controller                         */
+#define FM3_ETHERNET_MAC0_BASE    (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers            */
+#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers      */
+#define FM3_ETHERNET_MAC1_BASE    (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers            */
+
+/******************************************************************************
+ * Peripheral declaration
+ ******************************************************************************/
+#define FM3_FLASH_IF    ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)
+#define FM3_CRG         ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
+#define FM3_HWWDT       ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
+#define FM3_SWWDT       ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
+#define FM3_DTIM        ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)
+#define FM3_MFT0_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)
+#define FM3_MFT0_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)
+#define FM3_MFT0_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)
+#define FM3_MFT0_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)
+#define FM3_MFT0_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)
+#define FM3_MFT1_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)
+#define FM3_MFT1_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)
+#define FM3_MFT1_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)
+#define FM3_MFT1_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)
+#define FM3_MFT1_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)
+#define FM3_MFT2_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE)
+#define FM3_MFT2_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE)
+#define FM3_MFT2_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE)
+#define FM3_MFT2_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE)
+#define FM3_MFT2_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE)
+#define FM3_MFT_PPG     ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)
+#define FM3_BT0_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)
+#define FM3_BT0_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)
+#define FM3_BT0_RT      ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)
+#define FM3_BT0_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)
+#define FM3_BT1_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)
+#define FM3_BT1_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)
+#define FM3_BT1_RT      ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)
+#define FM3_BT1_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)
+#define FM3_BT2_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)
+#define FM3_BT2_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)
+#define FM3_BT2_RT      ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)
+#define FM3_BT2_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)
+#define FM3_BT3_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)
+#define FM3_BT3_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)
+#define FM3_BT3_RT      ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)
+#define FM3_BT3_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)
+#define FM3_BT4_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)
+#define FM3_BT4_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)
+#define FM3_BT4_RT      ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)
+#define FM3_BT4_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)
+#define FM3_BT5_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)
+#define FM3_BT5_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)
+#define FM3_BT5_RT      ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)
+#define FM3_BT5_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)
+#define FM3_BT6_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)
+#define FM3_BT6_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)
+#define FM3_BT6_RT      ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)
+#define FM3_BT6_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)
+#define FM3_BT7_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)
+#define FM3_BT7_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)
+#define FM3_BT7_RT      ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)
+#define FM3_BT7_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)
+#define FM3_BTIOSEL03   ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)
+#define FM3_BTIOSEL47   ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)
+#define FM3_BT8_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE)
+#define FM3_BT8_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE)
+#define FM3_BT8_RT      ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE)
+#define FM3_BT8_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE)
+#define FM3_BT9_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE)
+#define FM3_BT9_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE)
+#define FM3_BT9_RT      ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE)
+#define FM3_BT9_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE)
+#define FM3_BT10_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE)
+#define FM3_BT10_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE)
+#define FM3_BT10_RT     ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE)
+#define FM3_BT10_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE)
+#define FM3_BT11_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE)
+#define FM3_BT11_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE)
+#define FM3_BT11_RT     ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE)
+#define FM3_BT11_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE)
+#define FM3_BT12_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE)
+#define FM3_BT12_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE)
+#define FM3_BT12_RT     ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE)
+#define FM3_BT12_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE)
+#define FM3_BT13_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE)
+#define FM3_BT13_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE)
+#define FM3_BT13_RT     ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE)
+#define FM3_BT13_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE)
+#define FM3_BT14_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE)
+#define FM3_BT14_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE)
+#define FM3_BT14_RT     ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE)
+#define FM3_BT14_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE)
+#define FM3_BT15_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE)
+#define FM3_BT15_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE)
+#define FM3_BT15_RT     ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE)
+#define FM3_BT15_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE)
+#define FM3_BTIOSEL8B   ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE)
+#define FM3_BTIOSELCF   ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE)
+#define FM3_SBSSR       ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)
+#define FM3_QPRC0       ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)
+#define FM3_QPRC1       ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)
+#define FM3_QPRC3       ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE)
+#define FM3_ADC0        ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)
+#define FM3_ADC1        ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)
+#define FM3_ADC2        ((FM3_ADC_TypeDef *)FM3_ADC2_BASE)
+#define FM3_CRTRIM      ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)
+#define FM3_EXTI        ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)
+#define FM3_INTREQ      ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)
+#define FM3_GPIO        ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)
+#define FM3_LVD         ((FM3_LVD_TypeDef *)FM3_LVD_BASE)
+#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE)
+#define FM3_MFS0_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)
+#define FM3_MFS0_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)
+#define FM3_MFS0_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)
+#define FM3_MFS0_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)
+#define FM3_MFS1_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)
+#define FM3_MFS1_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)
+#define FM3_MFS1_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)
+#define FM3_MFS1_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)
+#define FM3_MFS2_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)
+#define FM3_MFS2_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)
+#define FM3_MFS2_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)
+#define FM3_MFS2_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)
+#define FM3_MFS3_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)
+#define FM3_MFS3_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)
+#define FM3_MFS3_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)
+#define FM3_MFS3_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)
+#define FM3_MFS4_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)
+#define FM3_MFS4_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)
+#define FM3_MFS4_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)
+#define FM3_MFS4_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)
+#define FM3_MFS5_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)
+#define FM3_MFS5_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)
+#define FM3_MFS5_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)
+#define FM3_MFS5_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)
+#define FM3_MFS6_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)
+#define FM3_MFS6_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)
+#define FM3_MFS6_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)
+#define FM3_MFS6_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)
+#define FM3_MFS7_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)
+#define FM3_MFS7_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)
+#define FM3_MFS7_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)
+#define FM3_MFS7_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)
+#define FM3_MFS_NFC     ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE)
+#define FM3_CRC         ((FM3_CRC_TypeDef *)FM3_CRC_BASE)
+#define FM3_WC          ((FM3_WC_TypeDef *)FM3_WC_BASE)
+#define FM3_EXBUS       ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE)
+#define FM3_USB0        ((FM3_USB_TypeDef *)FM3_USB0_BASE)
+#define FM3_USB1        ((FM3_USB_TypeDef *)FM3_USB1_BASE)
+#define FM3_DMAC        ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)
+#define FM3_ETHERNET_MAC0    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE)
+#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_CONTROL_TypeDef *)FM3_ETHERNET_CONTROL_BASE)
+#define FM3_ETHERNET_MAC1    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE)
+
+/******************************************************************************
+ * Peripheral Bit Band Alias declaration
+ ******************************************************************************/
+
+/* Flash interface registers */
+#define bFM3_FLASH_IF_FASZR_ASZ0               *((volatile unsigned int*)(0x42000000UL))
+#define bFM3_FLASH_IF_FASZR_ASZ1               *((volatile unsigned int*)(0x42000004UL))
+#define bFM3_FLASH_IF_FRWTR_RWT0               *((volatile unsigned int*)(0x42000080UL))
+#define bFM3_FLASH_IF_FRWTR_RWT1               *((volatile unsigned int*)(0x42000084UL))
+#define bFM3_FLASH_IF_FSTR_RDY                 *((volatile unsigned int*)(0x42000100UL))
+#define bFM3_FLASH_IF_FSTR_HNG                 *((volatile unsigned int*)(0x42000104UL))
+#define bFM3_FLASH_IF_FSTR_EER                 *((volatile unsigned int*)(0x42000108UL))
+#define bFM3_FLASH_IF_FSYNDN_SD0               *((volatile unsigned int*)(0x42000200UL))
+#define bFM3_FLASH_IF_FSYNDN_SD1               *((volatile unsigned int*)(0x42000204UL))
+#define bFM3_FLASH_IF_FSYNDN_SD2               *((volatile unsigned int*)(0x42000208UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM0             *((volatile unsigned int*)(0x42002000UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM1             *((volatile unsigned int*)(0x42002004UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM2             *((volatile unsigned int*)(0x42002008UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM3             *((volatile unsigned int*)(0x4200200CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM4             *((volatile unsigned int*)(0x42002010UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM5             *((volatile unsigned int*)(0x42002014UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM6             *((volatile unsigned int*)(0x42002018UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM7             *((volatile unsigned int*)(0x4200201CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM8             *((volatile unsigned int*)(0x42002020UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM9             *((volatile unsigned int*)(0x42002024UL))
+
+/* Clock and reset registers */
+#define bFM3_CRG_SCM_CTL_MOSCE                 *((volatile unsigned int*)(0x42200004UL))
+#define bFM3_CRG_SCM_CTL_SOSCE                 *((volatile unsigned int*)(0x4220000CUL))
+#define bFM3_CRG_SCM_CTL_PLLE                  *((volatile unsigned int*)(0x42200010UL))
+#define bFM3_CRG_SCM_CTL_RCS0                  *((volatile unsigned int*)(0x42200014UL))
+#define bFM3_CRG_SCM_CTL_RCS1                  *((volatile unsigned int*)(0x42200018UL))
+#define bFM3_CRG_SCM_CTL_RCS2                  *((volatile unsigned int*)(0x4220001CUL))
+#define bFM3_CRG_SCM_STR_MORDY                 *((volatile unsigned int*)(0x42200084UL))
+#define bFM3_CRG_SCM_STR_SORDY                 *((volatile unsigned int*)(0x4220008CUL))
+#define bFM3_CRG_SCM_STR_PLRDY                 *((volatile unsigned int*)(0x42200090UL))
+#define bFM3_CRG_SCM_STR_RCM0                  *((volatile unsigned int*)(0x42200094UL))
+#define bFM3_CRG_SCM_STR_RCM1                  *((volatile unsigned int*)(0x42200098UL))
+#define bFM3_CRG_SCM_STR_RCM2                  *((volatile unsigned int*)(0x4220009CUL))
+#define bFM3_CRG_RST_STR_PONR                  *((volatile unsigned int*)(0x42200180UL))
+#define bFM3_CRG_RST_STR_INITX                 *((volatile unsigned int*)(0x42200184UL))
+#define bFM3_CRG_RST_STR_SWDT                  *((volatile unsigned int*)(0x42200190UL))
+#define bFM3_CRG_RST_STR_HWDT                  *((volatile unsigned int*)(0x42200194UL))
+#define bFM3_CRG_RST_STR_CSVR                  *((volatile unsigned int*)(0x42200198UL))
+#define bFM3_CRG_RST_STR_FCSR                  *((volatile unsigned int*)(0x4220019CUL))
+#define bFM3_CRG_RST_STR_SRST                  *((volatile unsigned int*)(0x422001A0UL))
+#define bFM3_CRG_BSC_PSR_BSR0                  *((volatile unsigned int*)(0x42200200UL))
+#define bFM3_CRG_BSC_PSR_BSR1                  *((volatile unsigned int*)(0x42200204UL))
+#define bFM3_CRG_BSC_PSR_BSR2                  *((volatile unsigned int*)(0x42200208UL))
+#define bFM3_CRG_APBC0_PSR_APBC00              *((volatile unsigned int*)(0x42200280UL))
+#define bFM3_CRG_APBC0_PSR_APBC01              *((volatile unsigned int*)(0x42200284UL))
+#define bFM3_CRG_APBC1_PSR_APBC10              *((volatile unsigned int*)(0x42200300UL))
+#define bFM3_CRG_APBC1_PSR_APBC11              *((volatile unsigned int*)(0x42200304UL))
+#define bFM3_CRG_APBC1_PSR_APBC1RST            *((volatile unsigned int*)(0x42200310UL))
+#define bFM3_CRG_APBC1_PSR_APBC1EN             *((volatile unsigned int*)(0x4220031CUL))
+#define bFM3_CRG_APBC2_PSR_APBC20              *((volatile unsigned int*)(0x42200380UL))
+#define bFM3_CRG_APBC2_PSR_APBC21              *((volatile unsigned int*)(0x42200384UL))
+#define bFM3_CRG_APBC2_PSR_APBC2RST            *((volatile unsigned int*)(0x42200390UL))
+#define bFM3_CRG_APBC2_PSR_APBC2EN             *((volatile unsigned int*)(0x4220039CUL))
+#define bFM3_CRG_SWC_PSR_SWDS0                 *((volatile unsigned int*)(0x42200400UL))
+#define bFM3_CRG_SWC_PSR_SWDS1                 *((volatile unsigned int*)(0x42200404UL))
+#define bFM3_CRG_SWC_PSR_TESTB                 *((volatile unsigned int*)(0x4220041CUL))
+#define bFM3_CRG_TTC_PSR_TTC0                  *((volatile unsigned int*)(0x42200500UL))
+#define bFM3_CRG_TTC_PSR_TTC1                  *((volatile unsigned int*)(0x42200504UL))
+#define bFM3_CRG_CSW_TMR_MOWT0                 *((volatile unsigned int*)(0x42200600UL))
+#define bFM3_CRG_CSW_TMR_MOWT1                 *((volatile unsigned int*)(0x42200604UL))
+#define bFM3_CRG_CSW_TMR_MOWT2                 *((volatile unsigned int*)(0x42200608UL))
+#define bFM3_CRG_CSW_TMR_MOWT3                 *((volatile unsigned int*)(0x4220060CUL))
+#define bFM3_CRG_CSW_TMR_SOWT0                 *((volatile unsigned int*)(0x42200610UL))
+#define bFM3_CRG_CSW_TMR_SOWT1                 *((volatile unsigned int*)(0x42200614UL))
+#define bFM3_CRG_CSW_TMR_SOWT2                 *((volatile unsigned int*)(0x42200618UL))
+#define bFM3_CRG_PSW_TMR_POWT0                 *((volatile unsigned int*)(0x42200680UL))
+#define bFM3_CRG_PSW_TMR_POWT1                 *((volatile unsigned int*)(0x42200684UL))
+#define bFM3_CRG_PSW_TMR_POWT2                 *((volatile unsigned int*)(0x42200688UL))
+#define bFM3_CRG_PSW_TMR_PINC                  *((volatile unsigned int*)(0x42200690UL))
+#define bFM3_CRG_PLL_CTL1_PLLM0                *((volatile unsigned int*)(0x42200700UL))
+#define bFM3_CRG_PLL_CTL1_PLLM1                *((volatile unsigned int*)(0x42200704UL))
+#define bFM3_CRG_PLL_CTL1_PLLM2                *((volatile unsigned int*)(0x42200708UL))
+#define bFM3_CRG_PLL_CTL1_PLLM3                *((volatile unsigned int*)(0x4220070CUL))
+#define bFM3_CRG_PLL_CTL1_PLLK0                *((volatile unsigned int*)(0x42200710UL))
+#define bFM3_CRG_PLL_CTL1_PLLK1                *((volatile unsigned int*)(0x42200714UL))
+#define bFM3_CRG_PLL_CTL1_PLLK2                *((volatile unsigned int*)(0x42200718UL))
+#define bFM3_CRG_PLL_CTL1_PLLK3                *((volatile unsigned int*)(0x4220071CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN0                *((volatile unsigned int*)(0x42200780UL))
+#define bFM3_CRG_PLL_CTL2_PLLN1                *((volatile unsigned int*)(0x42200784UL))
+#define bFM3_CRG_PLL_CTL2_PLLN2                *((volatile unsigned int*)(0x42200788UL))
+#define bFM3_CRG_PLL_CTL2_PLLN3                *((volatile unsigned int*)(0x4220078CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN4                *((volatile unsigned int*)(0x42200790UL))
+#define bFM3_CRG_PLL_CTL2_PLLN5                *((volatile unsigned int*)(0x42200794UL))
+#define bFM3_CRG_CSV_CTL_MCSVE                 *((volatile unsigned int*)(0x42200800UL))
+#define bFM3_CRG_CSV_CTL_SCSVE                 *((volatile unsigned int*)(0x42200804UL))
+#define bFM3_CRG_CSV_CTL_FCSDE                 *((volatile unsigned int*)(0x42200820UL))
+#define bFM3_CRG_CSV_CTL_FCSRE                 *((volatile unsigned int*)(0x42200824UL))
+#define bFM3_CRG_CSV_CTL_FCD0                  *((volatile unsigned int*)(0x42200830UL))
+#define bFM3_CRG_CSV_CTL_FCD1                  *((volatile unsigned int*)(0x42200834UL))
+#define bFM3_CRG_CSV_CTL_FCD2                  *((volatile unsigned int*)(0x42200838UL))
+#define bFM3_CRG_CSV_STR_MCMF                  *((volatile unsigned int*)(0x42200880UL))
+#define bFM3_CRG_CSV_STR_SCMF                  *((volatile unsigned int*)(0x42200884UL))
+#define bFM3_CRG_DBWDT_CTL_DPSWBE              *((volatile unsigned int*)(0x42200A94UL))
+#define bFM3_CRG_DBWDT_CTL_DPHWBE              *((volatile unsigned int*)(0x42200A9CUL))
+#define bFM3_CRG_INT_ENR_MCSE                  *((volatile unsigned int*)(0x42200C00UL))
+#define bFM3_CRG_INT_ENR_SCSE                  *((volatile unsigned int*)(0x42200C04UL))
+#define bFM3_CRG_INT_ENR_PCSE                  *((volatile unsigned int*)(0x42200C08UL))
+#define bFM3_CRG_INT_ENR_FCSE                  *((volatile unsigned int*)(0x42200C14UL))
+#define bFM3_CRG_INT_STR_MCSI                  *((volatile unsigned int*)(0x42200C80UL))
+#define bFM3_CRG_INT_STR_SCSI                  *((volatile unsigned int*)(0x42200C84UL))
+#define bFM3_CRG_INT_STR_PCSI                  *((volatile unsigned int*)(0x42200C88UL))
+#define bFM3_CRG_INT_STR_FCSI                  *((volatile unsigned int*)(0x42200C94UL))
+#define bFM3_CRG_INT_CLR_MCSC                  *((volatile unsigned int*)(0x42200D00UL))
+#define bFM3_CRG_INT_CLR_SCSC                  *((volatile unsigned int*)(0x42200D04UL))
+#define bFM3_CRG_INT_CLR_PCSC                  *((volatile unsigned int*)(0x42200D08UL))
+#define bFM3_CRG_INT_CLR_FCSC                  *((volatile unsigned int*)(0x42200D14UL))
+
+/* Hardware watchdog registers */
+#define bFM3_HWWDT_WDG_CTL_INTEN               *((volatile unsigned int*)(0x42220100UL))
+#define bFM3_HWWDT_WDG_CTL_RESEN               *((volatile unsigned int*)(0x42220104UL))
+#define bFM3_HWWDT_WDG_RIS_RIS                 *((volatile unsigned int*)(0x42220200UL))
+
+/* Software watchdog registers */
+#define bFM3_SWWDT_WDOGCONTROL_INTEN           *((volatile unsigned int*)(0x42240100UL))
+#define bFM3_SWWDT_WDOGCONTROL_RESEN           *((volatile unsigned int*)(0x42240104UL))
+#define bFM3_SWWDT_WDOGRIS_RIS                 *((volatile unsigned int*)(0x42240200UL))
+
+/* Dual timer 1/2 registers */
+#define bFM3_DTIM_TIMER1CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0100UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0104UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0108UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A010CUL))
+#define bFM3_DTIM_TIMER1CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0114UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0118UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A011CUL))
+#define bFM3_DTIM_TIMER1RIS_TIMER1RIS          *((volatile unsigned int*)(0x422A0200UL))
+#define bFM3_DTIM_TIMER1MIS_TIMER1MIS          *((volatile unsigned int*)(0x422A0280UL))
+#define bFM3_DTIM_TIMER2CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0500UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0504UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0508UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A050CUL))
+#define bFM3_DTIM_TIMER2CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0514UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0518UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A051CUL))
+#define bFM3_DTIM_TIMER2RIS_TIMER2RIS          *((volatile unsigned int*)(0x422A0600UL))
+#define bFM3_DTIM_TIMER2MIS_TIMER2MIS          *((volatile unsigned int*)(0x422A0680UL))
+
+/* Multifunction Timer unit 0 Free Running Timer registers */
+#define bFM3_MFT0_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42400600UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42400604UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42400608UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4240060CUL))
+#define bFM3_MFT0_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42400610UL))
+#define bFM3_MFT0_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42400614UL))
+#define bFM3_MFT0_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42400618UL))
+#define bFM3_MFT0_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4240061CUL))
+#define bFM3_MFT0_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42400620UL))
+#define bFM3_MFT0_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42400624UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42400634UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42400638UL))
+#define bFM3_MFT0_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4240063CUL))
+#define bFM3_MFT0_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42400680UL))
+#define bFM3_MFT0_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42400684UL))
+#define bFM3_MFT0_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42400688UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42400800UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42400804UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42400808UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4240080CUL))
+#define bFM3_MFT0_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42400810UL))
+#define bFM3_MFT0_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42400814UL))
+#define bFM3_MFT0_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42400818UL))
+#define bFM3_MFT0_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4240081CUL))
+#define bFM3_MFT0_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42400820UL))
+#define bFM3_MFT0_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42400824UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42400834UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42400838UL))
+#define bFM3_MFT0_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4240083CUL))
+#define bFM3_MFT0_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42400880UL))
+#define bFM3_MFT0_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42400884UL))
+#define bFM3_MFT0_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42400888UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42400A00UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42400A04UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42400A08UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42400A0CUL))
+#define bFM3_MFT0_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42400A10UL))
+#define bFM3_MFT0_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42400A14UL))
+#define bFM3_MFT0_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42400A18UL))
+#define bFM3_MFT0_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42400A1CUL))
+#define bFM3_MFT0_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42400A20UL))
+#define bFM3_MFT0_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42400A24UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42400A34UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42400A38UL))
+#define bFM3_MFT0_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42400A3CUL))
+#define bFM3_MFT0_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42400A80UL))
+#define bFM3_MFT0_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42400A84UL))
+#define bFM3_MFT0_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42400A88UL))
+
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+#define bFM3_MFT0_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42400300UL))
+#define bFM3_MFT0_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42400304UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42400308UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4240030CUL))
+#define bFM3_MFT0_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42400310UL))
+#define bFM3_MFT0_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42400314UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42400318UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4240031CUL))
+#define bFM3_MFT0_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42400320UL))
+#define bFM3_MFT0_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42400324UL))
+#define bFM3_MFT0_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42400330UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42400334UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42400338UL))
+#define bFM3_MFT0_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42400380UL))
+#define bFM3_MFT0_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42400384UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42400388UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4240038CUL))
+#define bFM3_MFT0_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42400390UL))
+#define bFM3_MFT0_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42400394UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42400398UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4240039CUL))
+#define bFM3_MFT0_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424003A0UL))
+#define bFM3_MFT0_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424003A4UL))
+#define bFM3_MFT0_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424003B0UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424003B4UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424003B8UL))
+#define bFM3_MFT0_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42400400UL))
+#define bFM3_MFT0_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42400404UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42400408UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4240040CUL))
+#define bFM3_MFT0_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42400410UL))
+#define bFM3_MFT0_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42400414UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42400418UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4240041CUL))
+#define bFM3_MFT0_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42400420UL))
+#define bFM3_MFT0_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42400424UL))
+#define bFM3_MFT0_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42400430UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42400434UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42400438UL))
+#define bFM3_MFT0_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424004A0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424004A4UL))
+#define bFM3_MFT0_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424004A8UL))
+#define bFM3_MFT0_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424004ACUL))
+#define bFM3_MFT0_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424004B0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424004B4UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42400B00UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42400B04UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42400B08UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42400B0CUL))
+#define bFM3_MFT0_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42400B10UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42400B14UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42400B18UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42400B1CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42400B20UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42400B24UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42400B28UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42400B2CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42400B30UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42400B34UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42400B38UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42400B3CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42400B80UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42400B84UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42400B88UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42400B8CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42400B90UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42400B94UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42400B98UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42400B9CUL))
+
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT0_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42401180UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42401184UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42401188UL))
+#define bFM3_MFT0_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4240118CUL))
+#define bFM3_MFT0_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42401190UL))
+#define bFM3_MFT0_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42401194UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42401198UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4240119CUL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424011A0UL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424011A4UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424011A8UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424011ACUL))
+#define bFM3_MFT0_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424011B0UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42401200UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42401204UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42401208UL))
+#define bFM3_MFT0_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4240120CUL))
+#define bFM3_MFT0_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42401210UL))
+#define bFM3_MFT0_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42401214UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42401218UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4240121CUL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42401220UL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42401224UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42401228UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4240122CUL))
+#define bFM3_MFT0_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42401230UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42401280UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42401284UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42401288UL))
+#define bFM3_MFT0_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4240128CUL))
+#define bFM3_MFT0_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42401290UL))
+#define bFM3_MFT0_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42401294UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42401298UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4240129CUL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424012A0UL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424012A4UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424012A8UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424012ACUL))
+#define bFM3_MFT0_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424012B0UL))
+#define bFM3_MFT0_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42401300UL))
+#define bFM3_MFT0_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42401304UL))
+#define bFM3_MFT0_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42401310UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42401314UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42401318UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4240131CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42401320UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42401324UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42401328UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4240132CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42401330UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42401334UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42401338UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4240133CUL))
+#define bFM3_MFT0_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42401380UL))
+#define bFM3_MFT0_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42401384UL))
+#define bFM3_MFT0_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42401388UL))
+#define bFM3_MFT0_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4240138CUL))
+#define bFM3_MFT0_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42401390UL))
+
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+#define bFM3_MFT0_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42400C00UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42400C04UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42400C08UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42400C0CUL))
+#define bFM3_MFT0_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42400C10UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42400C14UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42400C18UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42400C1CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42400C20UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42400C24UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42400C28UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42400C2CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42400C30UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42400C34UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42400C38UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42400C3CUL))
+#define bFM3_MFT0_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42400F00UL))
+#define bFM3_MFT0_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42400F04UL))
+#define bFM3_MFT0_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42400F08UL))
+#define bFM3_MFT0_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42400F0CUL))
+#define bFM3_MFT0_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42400F10UL))
+#define bFM3_MFT0_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42400F14UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42400F18UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42400F1CUL))
+#define bFM3_MFT0_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42400F20UL))
+#define bFM3_MFT0_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42400F24UL))
+#define bFM3_MFT0_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42400F80UL))
+#define bFM3_MFT0_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42400F84UL))
+#define bFM3_MFT0_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42400F88UL))
+#define bFM3_MFT0_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42400F8CUL))
+#define bFM3_MFT0_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42400F90UL))
+#define bFM3_MFT0_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42400F94UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42400F98UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42400F9CUL))
+#define bFM3_MFT0_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42400FA0UL))
+#define bFM3_MFT0_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42400FA4UL))
+
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define bFM3_MFT0_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42401700UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42401704UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42401708UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42401710UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42401714UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42401718UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42401780UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42401784UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42401788UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4240178CUL))
+#define bFM3_MFT0_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42401790UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42401794UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424017A0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424017A4UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424017A8UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424017ACUL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424017B0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424017B4UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42401800UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42401804UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42401808UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4240180CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42401810UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42401814UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42401820UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42401824UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42401828UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4240182CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42401830UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42401834UL))
+
+/* Multifunction Timer unit 1 Free Running Timer registers */
+#define bFM3_MFT1_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42420600UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42420604UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42420608UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4242060CUL))
+#define bFM3_MFT1_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42420610UL))
+#define bFM3_MFT1_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42420614UL))
+#define bFM3_MFT1_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42420618UL))
+#define bFM3_MFT1_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4242061CUL))
+#define bFM3_MFT1_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42420620UL))
+#define bFM3_MFT1_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42420624UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42420634UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42420638UL))
+#define bFM3_MFT1_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4242063CUL))
+#define bFM3_MFT1_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42420680UL))
+#define bFM3_MFT1_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42420684UL))
+#define bFM3_MFT1_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42420688UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42420800UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42420804UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42420808UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4242080CUL))
+#define bFM3_MFT1_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42420810UL))
+#define bFM3_MFT1_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42420814UL))
+#define bFM3_MFT1_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42420818UL))
+#define bFM3_MFT1_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4242081CUL))
+#define bFM3_MFT1_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42420820UL))
+#define bFM3_MFT1_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42420824UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42420834UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42420838UL))
+#define bFM3_MFT1_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4242083CUL))
+#define bFM3_MFT1_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42420880UL))
+#define bFM3_MFT1_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42420884UL))
+#define bFM3_MFT1_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42420888UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42420A00UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42420A04UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42420A08UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42420A0CUL))
+#define bFM3_MFT1_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42420A10UL))
+#define bFM3_MFT1_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42420A14UL))
+#define bFM3_MFT1_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42420A18UL))
+#define bFM3_MFT1_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42420A1CUL))
+#define bFM3_MFT1_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42420A20UL))
+#define bFM3_MFT1_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42420A24UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42420A34UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42420A38UL))
+#define bFM3_MFT1_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42420A3CUL))
+#define bFM3_MFT1_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42420A80UL))
+#define bFM3_MFT1_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42420A84UL))
+#define bFM3_MFT1_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42420A88UL))
+
+/* Multifunction Timer unit 1 Output Compare Unit registers */
+#define bFM3_MFT1_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42420300UL))
+#define bFM3_MFT1_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42420304UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42420308UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4242030CUL))
+#define bFM3_MFT1_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42420310UL))
+#define bFM3_MFT1_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42420314UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42420318UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4242031CUL))
+#define bFM3_MFT1_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42420320UL))
+#define bFM3_MFT1_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42420324UL))
+#define bFM3_MFT1_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42420330UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42420334UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42420338UL))
+#define bFM3_MFT1_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42420380UL))
+#define bFM3_MFT1_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42420384UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42420388UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4242038CUL))
+#define bFM3_MFT1_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42420390UL))
+#define bFM3_MFT1_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42420394UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42420398UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4242039CUL))
+#define bFM3_MFT1_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424203A0UL))
+#define bFM3_MFT1_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424203A4UL))
+#define bFM3_MFT1_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424203B0UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424203B4UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424203B8UL))
+#define bFM3_MFT1_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42420400UL))
+#define bFM3_MFT1_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42420404UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42420408UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4242040CUL))
+#define bFM3_MFT1_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42420410UL))
+#define bFM3_MFT1_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42420414UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42420418UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4242041CUL))
+#define bFM3_MFT1_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42420420UL))
+#define bFM3_MFT1_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42420424UL))
+#define bFM3_MFT1_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42420430UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42420434UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42420438UL))
+#define bFM3_MFT1_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424204A0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424204A4UL))
+#define bFM3_MFT1_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424204A8UL))
+#define bFM3_MFT1_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424204ACUL))
+#define bFM3_MFT1_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424204B0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424204B4UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42420B00UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42420B04UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42420B08UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42420B0CUL))
+#define bFM3_MFT1_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42420B10UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42420B14UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42420B18UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42420B1CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42420B20UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42420B24UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42420B28UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42420B2CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42420B30UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42420B34UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42420B38UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42420B3CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42420B80UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42420B84UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42420B88UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42420B8CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42420B90UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42420B94UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42420B98UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42420B9CUL))
+
+/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT1_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42421180UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42421184UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42421188UL))
+#define bFM3_MFT1_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4242118CUL))
+#define bFM3_MFT1_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42421190UL))
+#define bFM3_MFT1_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42421194UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42421198UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4242119CUL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424211A0UL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424211A4UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424211A8UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424211ACUL))
+#define bFM3_MFT1_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424211B0UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42421200UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42421204UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42421208UL))
+#define bFM3_MFT1_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4242120CUL))
+#define bFM3_MFT1_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42421210UL))
+#define bFM3_MFT1_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42421214UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42421218UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4242121CUL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42421220UL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42421224UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42421228UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4242122CUL))
+#define bFM3_MFT1_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42421230UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42421280UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42421284UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42421288UL))
+#define bFM3_MFT1_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4242128CUL))
+#define bFM3_MFT1_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42421290UL))
+#define bFM3_MFT1_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42421294UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42421298UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4242129CUL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424212A0UL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424212A4UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424212A8UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424212ACUL))
+#define bFM3_MFT1_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424212B0UL))
+#define bFM3_MFT1_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42421300UL))
+#define bFM3_MFT1_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42421304UL))
+#define bFM3_MFT1_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42421310UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42421314UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42421318UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4242131CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42421320UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42421324UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42421328UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4242132CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42421330UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42421334UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42421338UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4242133CUL))
+#define bFM3_MFT1_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42421380UL))
+#define bFM3_MFT1_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42421384UL))
+#define bFM3_MFT1_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42421388UL))
+#define bFM3_MFT1_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4242138CUL))
+#define bFM3_MFT1_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42421390UL))
+
+/* Multifunction Timer unit 1 Input Capture Unit registers */
+#define bFM3_MFT1_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42420C00UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42420C04UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42420C08UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42420C0CUL))
+#define bFM3_MFT1_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42420C10UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42420C14UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42420C18UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42420C1CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42420C20UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42420C24UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42420C28UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42420C2CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42420C30UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42420C34UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42420C38UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42420C3CUL))
+#define bFM3_MFT1_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42420F00UL))
+#define bFM3_MFT1_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42420F04UL))
+#define bFM3_MFT1_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42420F08UL))
+#define bFM3_MFT1_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42420F0CUL))
+#define bFM3_MFT1_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42420F10UL))
+#define bFM3_MFT1_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42420F14UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42420F18UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42420F1CUL))
+#define bFM3_MFT1_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42420F20UL))
+#define bFM3_MFT1_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42420F24UL))
+#define bFM3_MFT1_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42420F80UL))
+#define bFM3_MFT1_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42420F84UL))
+#define bFM3_MFT1_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42420F88UL))
+#define bFM3_MFT1_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42420F8CUL))
+#define bFM3_MFT1_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42420F90UL))
+#define bFM3_MFT1_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42420F94UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42420F98UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42420F9CUL))
+#define bFM3_MFT1_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42420FA0UL))
+#define bFM3_MFT1_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42420FA4UL))
+
+/* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define bFM3_MFT1_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42421700UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42421704UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42421708UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42421710UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42421714UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42421718UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42421780UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42421784UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42421788UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4242178CUL))
+#define bFM3_MFT1_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42421790UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42421794UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424217A0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424217A4UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424217A8UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424217ACUL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424217B0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424217B4UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42421800UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42421804UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42421808UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4242180CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42421810UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42421814UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42421820UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42421824UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42421828UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4242182CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42421830UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42421834UL))
+
+/* Multifunction Timer unit 2 Free Running Timer registers */
+#define bFM3_MFT2_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42440600UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42440604UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42440608UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4244060CUL))
+#define bFM3_MFT2_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42440610UL))
+#define bFM3_MFT2_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42440614UL))
+#define bFM3_MFT2_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42440618UL))
+#define bFM3_MFT2_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4244061CUL))
+#define bFM3_MFT2_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42440620UL))
+#define bFM3_MFT2_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42440624UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42440634UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42440638UL))
+#define bFM3_MFT2_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4244063CUL))
+#define bFM3_MFT2_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42440680UL))
+#define bFM3_MFT2_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42440684UL))
+#define bFM3_MFT2_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42440688UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42440800UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42440804UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42440808UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4244080CUL))
+#define bFM3_MFT2_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42440810UL))
+#define bFM3_MFT2_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42440814UL))
+#define bFM3_MFT2_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42440818UL))
+#define bFM3_MFT2_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4244081CUL))
+#define bFM3_MFT2_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42440820UL))
+#define bFM3_MFT2_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42440824UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42440834UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42440838UL))
+#define bFM3_MFT2_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4244083CUL))
+#define bFM3_MFT2_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42440880UL))
+#define bFM3_MFT2_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42440884UL))
+#define bFM3_MFT2_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42440888UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42440A00UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42440A04UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42440A08UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42440A0CUL))
+#define bFM3_MFT2_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42440A10UL))
+#define bFM3_MFT2_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42440A14UL))
+#define bFM3_MFT2_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42440A18UL))
+#define bFM3_MFT2_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42440A1CUL))
+#define bFM3_MFT2_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42440A20UL))
+#define bFM3_MFT2_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42440A24UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42440A34UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42440A38UL))
+#define bFM3_MFT2_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42440A3CUL))
+#define bFM3_MFT2_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42440A80UL))
+#define bFM3_MFT2_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42440A84UL))
+#define bFM3_MFT2_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42440A88UL))
+
+/* Multifunction Timer unit 2 Output Compare Unit registers */
+#define bFM3_MFT2_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42440300UL))
+#define bFM3_MFT2_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42440304UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42440308UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4244030CUL))
+#define bFM3_MFT2_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42440310UL))
+#define bFM3_MFT2_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42440314UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42440318UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4244031CUL))
+#define bFM3_MFT2_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42440320UL))
+#define bFM3_MFT2_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42440324UL))
+#define bFM3_MFT2_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42440330UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42440334UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42440338UL))
+#define bFM3_MFT2_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42440380UL))
+#define bFM3_MFT2_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42440384UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42440388UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4244038CUL))
+#define bFM3_MFT2_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42440390UL))
+#define bFM3_MFT2_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42440394UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42440398UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4244039CUL))
+#define bFM3_MFT2_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424403A0UL))
+#define bFM3_MFT2_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424403A4UL))
+#define bFM3_MFT2_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424403B0UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424403B4UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424403B8UL))
+#define bFM3_MFT2_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42440400UL))
+#define bFM3_MFT2_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42440404UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42440408UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4244040CUL))
+#define bFM3_MFT2_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42440410UL))
+#define bFM3_MFT2_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42440414UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42440418UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4244041CUL))
+#define bFM3_MFT2_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42440420UL))
+#define bFM3_MFT2_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42440424UL))
+#define bFM3_MFT2_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42440430UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42440434UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42440438UL))
+#define bFM3_MFT2_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424404A0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424404A4UL))
+#define bFM3_MFT2_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424404A8UL))
+#define bFM3_MFT2_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424404ACUL))
+#define bFM3_MFT2_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424404B0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424404B4UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42440B00UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42440B04UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42440B08UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42440B0CUL))
+#define bFM3_MFT2_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42440B10UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42440B14UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42440B18UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42440B1CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42440B20UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42440B24UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42440B28UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42440B2CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42440B30UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42440B34UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42440B38UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42440B3CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42440B80UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42440B84UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42440B88UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42440B8CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42440B90UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42440B94UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42440B98UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42440B9CUL))
+
+/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT2_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42441180UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42441184UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42441188UL))
+#define bFM3_MFT2_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4244118CUL))
+#define bFM3_MFT2_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42441190UL))
+#define bFM3_MFT2_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42441194UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42441198UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4244119CUL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424411A0UL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424411A4UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424411A8UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424411ACUL))
+#define bFM3_MFT2_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424411B0UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42441200UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42441204UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42441208UL))
+#define bFM3_MFT2_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4244120CUL))
+#define bFM3_MFT2_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42441210UL))
+#define bFM3_MFT2_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42441214UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42441218UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4244121CUL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42441220UL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42441224UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42441228UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4244122CUL))
+#define bFM3_MFT2_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42441230UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42441280UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42441284UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42441288UL))
+#define bFM3_MFT2_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4244128CUL))
+#define bFM3_MFT2_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42441290UL))
+#define bFM3_MFT2_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42441294UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42441298UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4244129CUL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424412A0UL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424412A4UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424412A8UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424412ACUL))
+#define bFM3_MFT2_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424412B0UL))
+#define bFM3_MFT2_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42441300UL))
+#define bFM3_MFT2_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42441304UL))
+#define bFM3_MFT2_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42441310UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42441314UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42441318UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4244131CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42441320UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42441324UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42441328UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4244132CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42441330UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42441334UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42441338UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4244133CUL))
+#define bFM3_MFT2_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42441380UL))
+#define bFM3_MFT2_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42441384UL))
+#define bFM3_MFT2_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42441388UL))
+#define bFM3_MFT2_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4244138CUL))
+#define bFM3_MFT2_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42441390UL))
+
+/* Multifunction Timer unit 2 Input Capture Unit registers */
+#define bFM3_MFT2_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42440C00UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42440C04UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42440C08UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42440C0CUL))
+#define bFM3_MFT2_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42440C10UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42440C14UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42440C18UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42440C1CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42440C20UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42440C24UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42440C28UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42440C2CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42440C30UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42440C34UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42440C38UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42440C3CUL))
+#define bFM3_MFT2_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42440F00UL))
+#define bFM3_MFT2_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42440F04UL))
+#define bFM3_MFT2_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42440F08UL))
+#define bFM3_MFT2_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42440F0CUL))
+#define bFM3_MFT2_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42440F10UL))
+#define bFM3_MFT2_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42440F14UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42440F18UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42440F1CUL))
+#define bFM3_MFT2_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42440F20UL))
+#define bFM3_MFT2_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42440F24UL))
+#define bFM3_MFT2_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42440F80UL))
+#define bFM3_MFT2_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42440F84UL))
+#define bFM3_MFT2_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42440F88UL))
+#define bFM3_MFT2_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42440F8CUL))
+#define bFM3_MFT2_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42440F90UL))
+#define bFM3_MFT2_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42440F94UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42440F98UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42440F9CUL))
+#define bFM3_MFT2_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42440FA0UL))
+#define bFM3_MFT2_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42440FA4UL))
+
+/* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define bFM3_MFT2_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42441700UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42441704UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42441708UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42441710UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42441714UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42441718UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42441780UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42441784UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42441788UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4244178CUL))
+#define bFM3_MFT2_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42441790UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42441794UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424417A0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424417A4UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424417A8UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424417ACUL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424417B0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424417B4UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42441800UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42441804UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42441808UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4244180CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42441810UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42441814UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42441820UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42441824UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42441828UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4244182CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42441830UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42441834UL))
+
+/* Multifunction Timer PPG registers */
+#define bFM3_MFT_PPG_TTCR0_STR0                *((volatile unsigned int*)(0x42480020UL))
+#define bFM3_MFT_PPG_TTCR0_MONI0               *((volatile unsigned int*)(0x42480024UL))
+#define bFM3_MFT_PPG_TTCR0_CS00                *((volatile unsigned int*)(0x42480028UL))
+#define bFM3_MFT_PPG_TTCR0_CS01                *((volatile unsigned int*)(0x4248002CUL))
+#define bFM3_MFT_PPG_TTCR0_TRG0O               *((volatile unsigned int*)(0x42480030UL))
+#define bFM3_MFT_PPG_TTCR0_TRG2O               *((volatile unsigned int*)(0x42480034UL))
+#define bFM3_MFT_PPG_TTCR0_TRG4O               *((volatile unsigned int*)(0x42480038UL))
+#define bFM3_MFT_PPG_TTCR0_TRG6O               *((volatile unsigned int*)(0x4248003CUL))
+#define bFM3_MFT_PPG_TTCR1_STR1                *((volatile unsigned int*)(0x42480420UL))
+#define bFM3_MFT_PPG_TTCR1_MONI1               *((volatile unsigned int*)(0x42480424UL))
+#define bFM3_MFT_PPG_TTCR1_CS10                *((volatile unsigned int*)(0x42480428UL))
+#define bFM3_MFT_PPG_TTCR1_CS11                *((volatile unsigned int*)(0x4248042CUL))
+#define bFM3_MFT_PPG_TTCR1_TRG1O               *((volatile unsigned int*)(0x42480430UL))
+#define bFM3_MFT_PPG_TTCR1_TRG3O               *((volatile unsigned int*)(0x42480434UL))
+#define bFM3_MFT_PPG_TTCR1_TRG5O               *((volatile unsigned int*)(0x42480438UL))
+#define bFM3_MFT_PPG_TTCR1_TRG7O               *((volatile unsigned int*)(0x4248043CUL))
+#define bFM3_MFT_PPG_TTCR2_STR2                *((volatile unsigned int*)(0x42480820UL))
+#define bFM3_MFT_PPG_TTCR2_MONI2               *((volatile unsigned int*)(0x42480824UL))
+#define bFM3_MFT_PPG_TTCR2_CS20                *((volatile unsigned int*)(0x42480828UL))
+#define bFM3_MFT_PPG_TTCR2_CS21                *((volatile unsigned int*)(0x4248082CUL))
+#define bFM3_MFT_PPG_TTCR2_TRG16O              *((volatile unsigned int*)(0x42480830UL))
+#define bFM3_MFT_PPG_TTCR2_TRG18O              *((volatile unsigned int*)(0x42480834UL))
+#define bFM3_MFT_PPG_TTCR2_TRG20O              *((volatile unsigned int*)(0x42480838UL))
+#define bFM3_MFT_PPG_TTCR2_TRG22O              *((volatile unsigned int*)(0x4248083CUL))
+#define bFM3_MFT_PPG_TRG_PEN00                 *((volatile unsigned int*)(0x42482000UL))
+#define bFM3_MFT_PPG_TRG_PEN01                 *((volatile unsigned int*)(0x42482004UL))
+#define bFM3_MFT_PPG_TRG_PEN02                 *((volatile unsigned int*)(0x42482008UL))
+#define bFM3_MFT_PPG_TRG_PEN03                 *((volatile unsigned int*)(0x4248200CUL))
+#define bFM3_MFT_PPG_TRG_PEN04                 *((volatile unsigned int*)(0x42482010UL))
+#define bFM3_MFT_PPG_TRG_PEN05                 *((volatile unsigned int*)(0x42482014UL))
+#define bFM3_MFT_PPG_TRG_PEN06                 *((volatile unsigned int*)(0x42482018UL))
+#define bFM3_MFT_PPG_TRG_PEN07                 *((volatile unsigned int*)(0x4248201CUL))
+#define bFM3_MFT_PPG_TRG_PEN08                 *((volatile unsigned int*)(0x42482020UL))
+#define bFM3_MFT_PPG_TRG_PEN09                 *((volatile unsigned int*)(0x42482024UL))
+#define bFM3_MFT_PPG_TRG_PEN10                 *((volatile unsigned int*)(0x42482028UL))
+#define bFM3_MFT_PPG_TRG_PEN11                 *((volatile unsigned int*)(0x4248202CUL))
+#define bFM3_MFT_PPG_TRG_PEN12                 *((volatile unsigned int*)(0x42482030UL))
+#define bFM3_MFT_PPG_TRG_PEN13                 *((volatile unsigned int*)(0x42482034UL))
+#define bFM3_MFT_PPG_TRG_PEN14                 *((volatile unsigned int*)(0x42482038UL))
+#define bFM3_MFT_PPG_TRG_PEN15                 *((volatile unsigned int*)(0x4248203CUL))
+#define bFM3_MFT_PPG_REVC_REV00                *((volatile unsigned int*)(0x42482080UL))
+#define bFM3_MFT_PPG_REVC_REV01                *((volatile unsigned int*)(0x42482084UL))
+#define bFM3_MFT_PPG_REVC_REV02                *((volatile unsigned int*)(0x42482088UL))
+#define bFM3_MFT_PPG_REVC_REV03                *((volatile unsigned int*)(0x4248208CUL))
+#define bFM3_MFT_PPG_REVC_REV04                *((volatile unsigned int*)(0x42482090UL))
+#define bFM3_MFT_PPG_REVC_REV05                *((volatile unsigned int*)(0x42482094UL))
+#define bFM3_MFT_PPG_REVC_REV06                *((volatile unsigned int*)(0x42482098UL))
+#define bFM3_MFT_PPG_REVC_REV07                *((volatile unsigned int*)(0x4248209CUL))
+#define bFM3_MFT_PPG_REVC_REV08                *((volatile unsigned int*)(0x424820A0UL))
+#define bFM3_MFT_PPG_REVC_REV09                *((volatile unsigned int*)(0x424820A4UL))
+#define bFM3_MFT_PPG_REVC_REV10                *((volatile unsigned int*)(0x424820A8UL))
+#define bFM3_MFT_PPG_REVC_REV11                *((volatile unsigned int*)(0x424820ACUL))
+#define bFM3_MFT_PPG_REVC_REV12                *((volatile unsigned int*)(0x424820B0UL))
+#define bFM3_MFT_PPG_REVC_REV13                *((volatile unsigned int*)(0x424820B4UL))
+#define bFM3_MFT_PPG_REVC_REV14                *((volatile unsigned int*)(0x424820B8UL))
+#define bFM3_MFT_PPG_REVC_REV15                *((volatile unsigned int*)(0x424820BCUL))
+#define bFM3_MFT_PPG_TRG1_PEN16                *((volatile unsigned int*)(0x42482800UL))
+#define bFM3_MFT_PPG_TRG1_PEN17                *((volatile unsigned int*)(0x42482804UL))
+#define bFM3_MFT_PPG_TRG1_PEN18                *((volatile unsigned int*)(0x42482808UL))
+#define bFM3_MFT_PPG_TRG1_PEN19                *((volatile unsigned int*)(0x4248280CUL))
+#define bFM3_MFT_PPG_TRG1_PEN20                *((volatile unsigned int*)(0x42482810UL))
+#define bFM3_MFT_PPG_TRG1_PEN21                *((volatile unsigned int*)(0x42482814UL))
+#define bFM3_MFT_PPG_TRG1_PEN22                *((volatile unsigned int*)(0x42482818UL))
+#define bFM3_MFT_PPG_TRG1_PEN23                *((volatile unsigned int*)(0x4248281CUL))
+#define bFM3_MFT_PPG_REVC1_REV16               *((volatile unsigned int*)(0x42482880UL))
+#define bFM3_MFT_PPG_REVC1_REV17               *((volatile unsigned int*)(0x42482884UL))
+#define bFM3_MFT_PPG_REVC1_REV18               *((volatile unsigned int*)(0x42482888UL))
+#define bFM3_MFT_PPG_REVC1_REV19               *((volatile unsigned int*)(0x4248288CUL))
+#define bFM3_MFT_PPG_REVC1_REV20               *((volatile unsigned int*)(0x42482890UL))
+#define bFM3_MFT_PPG_REVC1_REV21               *((volatile unsigned int*)(0x42482894UL))
+#define bFM3_MFT_PPG_REVC1_REV22               *((volatile unsigned int*)(0x42482898UL))
+#define bFM3_MFT_PPG_REVC1_REV23               *((volatile unsigned int*)(0x4248289CUL))
+#define bFM3_MFT_PPG_PPGC1_TTRG                *((volatile unsigned int*)(0x42484000UL))
+#define bFM3_MFT_PPG_PPGC1_MD0                 *((volatile unsigned int*)(0x42484004UL))
+#define bFM3_MFT_PPG_PPGC1_MD1                 *((volatile unsigned int*)(0x42484008UL))
+#define bFM3_MFT_PPG_PPGC1_PCS0                *((volatile unsigned int*)(0x4248400CUL))
+#define bFM3_MFT_PPG_PPGC1_PCS1                *((volatile unsigned int*)(0x42484010UL))
+#define bFM3_MFT_PPG_PPGC1_INTM                *((volatile unsigned int*)(0x42484014UL))
+#define bFM3_MFT_PPG_PPGC1_PUF                 *((volatile unsigned int*)(0x42484018UL))
+#define bFM3_MFT_PPG_PPGC1_PIE                 *((volatile unsigned int*)(0x4248401CUL))
+#define bFM3_MFT_PPG_PPGC0_TTRG                *((volatile unsigned int*)(0x42484020UL))
+#define bFM3_MFT_PPG_PPGC0_MD0                 *((volatile unsigned int*)(0x42484024UL))
+#define bFM3_MFT_PPG_PPGC0_MD1                 *((volatile unsigned int*)(0x42484028UL))
+#define bFM3_MFT_PPG_PPGC0_PCS0                *((volatile unsigned int*)(0x4248402CUL))
+#define bFM3_MFT_PPG_PPGC0_PCS1                *((volatile unsigned int*)(0x42484030UL))
+#define bFM3_MFT_PPG_PPGC0_INTM                *((volatile unsigned int*)(0x42484034UL))
+#define bFM3_MFT_PPG_PPGC0_PUF                 *((volatile unsigned int*)(0x42484038UL))
+#define bFM3_MFT_PPG_PPGC0_PIE                 *((volatile unsigned int*)(0x4248403CUL))
+#define bFM3_MFT_PPG_PPGC3_TTRG                *((volatile unsigned int*)(0x42484080UL))
+#define bFM3_MFT_PPG_PPGC3_MD0                 *((volatile unsigned int*)(0x42484084UL))
+#define bFM3_MFT_PPG_PPGC3_MD1                 *((volatile unsigned int*)(0x42484088UL))
+#define bFM3_MFT_PPG_PPGC3_PCS0                *((volatile unsigned int*)(0x4248408CUL))
+#define bFM3_MFT_PPG_PPGC3_PCS1                *((volatile unsigned int*)(0x42484090UL))
+#define bFM3_MFT_PPG_PPGC3_INTM                *((volatile unsigned int*)(0x42484094UL))
+#define bFM3_MFT_PPG_PPGC3_PUF                 *((volatile unsigned int*)(0x42484098UL))
+#define bFM3_MFT_PPG_PPGC3_PIE                 *((volatile unsigned int*)(0x4248409CUL))
+#define bFM3_MFT_PPG_PPGC2_TTRG                *((volatile unsigned int*)(0x424840A0UL))
+#define bFM3_MFT_PPG_PPGC2_MD0                 *((volatile unsigned int*)(0x424840A4UL))
+#define bFM3_MFT_PPG_PPGC2_MD1                 *((volatile unsigned int*)(0x424840A8UL))
+#define bFM3_MFT_PPG_PPGC2_PCS0                *((volatile unsigned int*)(0x424840ACUL))
+#define bFM3_MFT_PPG_PPGC2_PCS1                *((volatile unsigned int*)(0x424840B0UL))
+#define bFM3_MFT_PPG_PPGC2_INTM                *((volatile unsigned int*)(0x424840B4UL))
+#define bFM3_MFT_PPG_PPGC2_PUF                 *((volatile unsigned int*)(0x424840B8UL))
+#define bFM3_MFT_PPG_PPGC2_PIE                 *((volatile unsigned int*)(0x424840BCUL))
+#define bFM3_MFT_PPG_GATEC0_EDGE0              *((volatile unsigned int*)(0x42484300UL))
+#define bFM3_MFT_PPG_GATEC0_STRG0              *((volatile unsigned int*)(0x42484304UL))
+#define bFM3_MFT_PPG_GATEC0_EDGE2              *((volatile unsigned int*)(0x42484310UL))
+#define bFM3_MFT_PPG_GATEC0_STRG2              *((volatile unsigned int*)(0x42484314UL))
+#define bFM3_MFT_PPG_PPGC5_TTRG                *((volatile unsigned int*)(0x42484800UL))
+#define bFM3_MFT_PPG_PPGC5_MD0                 *((volatile unsigned int*)(0x42484804UL))
+#define bFM3_MFT_PPG_PPGC5_MD1                 *((volatile unsigned int*)(0x42484808UL))
+#define bFM3_MFT_PPG_PPGC5_PCS0                *((volatile unsigned int*)(0x4248480CUL))
+#define bFM3_MFT_PPG_PPGC5_PCS1                *((volatile unsigned int*)(0x42484810UL))
+#define bFM3_MFT_PPG_PPGC5_INTM                *((volatile unsigned int*)(0x42484814UL))
+#define bFM3_MFT_PPG_PPGC5_PUF                 *((volatile unsigned int*)(0x42484818UL))
+#define bFM3_MFT_PPG_PPGC5_PIE                 *((volatile unsigned int*)(0x4248481CUL))
+#define bFM3_MFT_PPG_PPGC4_TTRG                *((volatile unsigned int*)(0x42484820UL))
+#define bFM3_MFT_PPG_PPGC4_MD0                 *((volatile unsigned int*)(0x42484824UL))
+#define bFM3_MFT_PPG_PPGC4_MD1                 *((volatile unsigned int*)(0x42484828UL))
+#define bFM3_MFT_PPG_PPGC4_PCS0                *((volatile unsigned int*)(0x4248482CUL))
+#define bFM3_MFT_PPG_PPGC4_PCS1                *((volatile unsigned int*)(0x42484830UL))
+#define bFM3_MFT_PPG_PPGC4_INTM                *((volatile unsigned int*)(0x42484834UL))
+#define bFM3_MFT_PPG_PPGC4_PUF                 *((volatile unsigned int*)(0x42484838UL))
+#define bFM3_MFT_PPG_PPGC4_PIE                 *((volatile unsigned int*)(0x4248483CUL))
+#define bFM3_MFT_PPG_PPGC7_TTRG                *((volatile unsigned int*)(0x42484880UL))
+#define bFM3_MFT_PPG_PPGC7_MD0                 *((volatile unsigned int*)(0x42484884UL))
+#define bFM3_MFT_PPG_PPGC7_MD1                 *((volatile unsigned int*)(0x42484888UL))
+#define bFM3_MFT_PPG_PPGC7_PCS0                *((volatile unsigned int*)(0x4248488CUL))
+#define bFM3_MFT_PPG_PPGC7_PCS1                *((volatile unsigned int*)(0x42484890UL))
+#define bFM3_MFT_PPG_PPGC7_INTM                *((volatile unsigned int*)(0x42484894UL))
+#define bFM3_MFT_PPG_PPGC7_PUF                 *((volatile unsigned int*)(0x42484898UL))
+#define bFM3_MFT_PPG_PPGC7_PIE                 *((volatile unsigned int*)(0x4248489CUL))
+#define bFM3_MFT_PPG_PPGC6_TTRG                *((volatile unsigned int*)(0x424848A0UL))
+#define bFM3_MFT_PPG_PPGC6_MD0                 *((volatile unsigned int*)(0x424848A4UL))
+#define bFM3_MFT_PPG_PPGC6_MD1                 *((volatile unsigned int*)(0x424848A8UL))
+#define bFM3_MFT_PPG_PPGC6_PCS0                *((volatile unsigned int*)(0x424848ACUL))
+#define bFM3_MFT_PPG_PPGC6_PCS1                *((volatile unsigned int*)(0x424848B0UL))
+#define bFM3_MFT_PPG_PPGC6_INTM                *((volatile unsigned int*)(0x424848B4UL))
+#define bFM3_MFT_PPG_PPGC6_PUF                 *((volatile unsigned int*)(0x424848B8UL))
+#define bFM3_MFT_PPG_PPGC6_PIE                 *((volatile unsigned int*)(0x424848BCUL))
+#define bFM3_MFT_PPG_GATEC4_EDGE4              *((volatile unsigned int*)(0x42484B00UL))
+#define bFM3_MFT_PPG_GATEC4_STRG4              *((volatile unsigned int*)(0x42484B04UL))
+#define bFM3_MFT_PPG_GATEC4_EDGE6              *((volatile unsigned int*)(0x42484B10UL))
+#define bFM3_MFT_PPG_GATEC4_STRG6              *((volatile unsigned int*)(0x42484B14UL))
+#define bFM3_MFT_PPG_PPGC9_TTRG                *((volatile unsigned int*)(0x42485000UL))
+#define bFM3_MFT_PPG_PPGC9_MD0                 *((volatile unsigned int*)(0x42485004UL))
+#define bFM3_MFT_PPG_PPGC9_MD1                 *((volatile unsigned int*)(0x42485008UL))
+#define bFM3_MFT_PPG_PPGC9_PCS0                *((volatile unsigned int*)(0x4248500CUL))
+#define bFM3_MFT_PPG_PPGC9_PCS1                *((volatile unsigned int*)(0x42485010UL))
+#define bFM3_MFT_PPG_PPGC9_INTM                *((volatile unsigned int*)(0x42485014UL))
+#define bFM3_MFT_PPG_PPGC9_PUF                 *((volatile unsigned int*)(0x42485018UL))
+#define bFM3_MFT_PPG_PPGC9_PIE                 *((volatile unsigned int*)(0x4248501CUL))
+#define bFM3_MFT_PPG_PPGC8_TTRG                *((volatile unsigned int*)(0x42485020UL))
+#define bFM3_MFT_PPG_PPGC8_MD0                 *((volatile unsigned int*)(0x42485024UL))
+#define bFM3_MFT_PPG_PPGC8_MD1                 *((volatile unsigned int*)(0x42485028UL))
+#define bFM3_MFT_PPG_PPGC8_PCS0                *((volatile unsigned int*)(0x4248502CUL))
+#define bFM3_MFT_PPG_PPGC8_PCS1                *((volatile unsigned int*)(0x42485030UL))
+#define bFM3_MFT_PPG_PPGC8_INTM                *((volatile unsigned int*)(0x42485034UL))
+#define bFM3_MFT_PPG_PPGC8_PUF                 *((volatile unsigned int*)(0x42485038UL))
+#define bFM3_MFT_PPG_PPGC8_PIE                 *((volatile unsigned int*)(0x4248503CUL))
+#define bFM3_MFT_PPG_PPGC11_TTRG               *((volatile unsigned int*)(0x42485080UL))
+#define bFM3_MFT_PPG_PPGC11_MD0                *((volatile unsigned int*)(0x42485084UL))
+#define bFM3_MFT_PPG_PPGC11_MD1                *((volatile unsigned int*)(0x42485088UL))
+#define bFM3_MFT_PPG_PPGC11_PCS0               *((volatile unsigned int*)(0x4248508CUL))
+#define bFM3_MFT_PPG_PPGC11_PCS1               *((volatile unsigned int*)(0x42485090UL))
+#define bFM3_MFT_PPG_PPGC11_INTM               *((volatile unsigned int*)(0x42485094UL))
+#define bFM3_MFT_PPG_PPGC11_PUF                *((volatile unsigned int*)(0x42485098UL))
+#define bFM3_MFT_PPG_PPGC11_PIE                *((volatile unsigned int*)(0x4248509CUL))
+#define bFM3_MFT_PPG_PPGC10_TTRG               *((volatile unsigned int*)(0x424850A0UL))
+#define bFM3_MFT_PPG_PPGC10_MD0                *((volatile unsigned int*)(0x424850A4UL))
+#define bFM3_MFT_PPG_PPGC10_MD1                *((volatile unsigned int*)(0x424850A8UL))
+#define bFM3_MFT_PPG_PPGC10_PCS0               *((volatile unsigned int*)(0x424850ACUL))
+#define bFM3_MFT_PPG_PPGC10_PCS1               *((volatile unsigned int*)(0x424850B0UL))
+#define bFM3_MFT_PPG_PPGC10_INTM               *((volatile unsigned int*)(0x424850B4UL))
+#define bFM3_MFT_PPG_PPGC10_PUF                *((volatile unsigned int*)(0x424850B8UL))
+#define bFM3_MFT_PPG_PPGC10_PIE                *((volatile unsigned int*)(0x424850BCUL))
+#define bFM3_MFT_PPG_GATEC8_EDGE8              *((volatile unsigned int*)(0x42485300UL))
+#define bFM3_MFT_PPG_GATEC8_STRG8              *((volatile unsigned int*)(0x42485304UL))
+#define bFM3_MFT_PPG_GATEC8_EDGE10             *((volatile unsigned int*)(0x42485310UL))
+#define bFM3_MFT_PPG_GATEC8_STRG10             *((volatile unsigned int*)(0x42485314UL))
+#define bFM3_MFT_PPG_PPGC13_TTRG               *((volatile unsigned int*)(0x42485800UL))
+#define bFM3_MFT_PPG_PPGC13_MD0                *((volatile unsigned int*)(0x42485804UL))
+#define bFM3_MFT_PPG_PPGC13_MD1                *((volatile unsigned int*)(0x42485808UL))
+#define bFM3_MFT_PPG_PPGC13_PCS0               *((volatile unsigned int*)(0x4248580CUL))
+#define bFM3_MFT_PPG_PPGC13_PCS1               *((volatile unsigned int*)(0x42485810UL))
+#define bFM3_MFT_PPG_PPGC13_INTM               *((volatile unsigned int*)(0x42485814UL))
+#define bFM3_MFT_PPG_PPGC13_PUF                *((volatile unsigned int*)(0x42485818UL))
+#define bFM3_MFT_PPG_PPGC13_PIE                *((volatile unsigned int*)(0x4248581CUL))
+#define bFM3_MFT_PPG_PPGC12_TTRG               *((volatile unsigned int*)(0x42485820UL))
+#define bFM3_MFT_PPG_PPGC12_MD0                *((volatile unsigned int*)(0x42485824UL))
+#define bFM3_MFT_PPG_PPGC12_MD1                *((volatile unsigned int*)(0x42485828UL))
+#define bFM3_MFT_PPG_PPGC12_PCS0               *((volatile unsigned int*)(0x4248582CUL))
+#define bFM3_MFT_PPG_PPGC12_PCS1               *((volatile unsigned int*)(0x42485830UL))
+#define bFM3_MFT_PPG_PPGC12_INTM               *((volatile unsigned int*)(0x42485834UL))
+#define bFM3_MFT_PPG_PPGC12_PUF                *((volatile unsigned int*)(0x42485838UL))
+#define bFM3_MFT_PPG_PPGC12_PIE                *((volatile unsigned int*)(0x4248583CUL))
+#define bFM3_MFT_PPG_PPGC15_TTRG               *((volatile unsigned int*)(0x42485880UL))
+#define bFM3_MFT_PPG_PPGC15_MD0                *((volatile unsigned int*)(0x42485884UL))
+#define bFM3_MFT_PPG_PPGC15_MD1                *((volatile unsigned int*)(0x42485888UL))
+#define bFM3_MFT_PPG_PPGC15_PCS0               *((volatile unsigned int*)(0x4248588CUL))
+#define bFM3_MFT_PPG_PPGC15_PCS1               *((volatile unsigned int*)(0x42485890UL))
+#define bFM3_MFT_PPG_PPGC15_INTM               *((volatile unsigned int*)(0x42485894UL))
+#define bFM3_MFT_PPG_PPGC15_PUF                *((volatile unsigned int*)(0x42485898UL))
+#define bFM3_MFT_PPG_PPGC15_PIE                *((volatile unsigned int*)(0x4248589CUL))
+#define bFM3_MFT_PPG_PPGC14_TTRG               *((volatile unsigned int*)(0x424858A0UL))
+#define bFM3_MFT_PPG_PPGC14_MD0                *((volatile unsigned int*)(0x424858A4UL))
+#define bFM3_MFT_PPG_PPGC14_MD1                *((volatile unsigned int*)(0x424858A8UL))
+#define bFM3_MFT_PPG_PPGC14_PCS0               *((volatile unsigned int*)(0x424858ACUL))
+#define bFM3_MFT_PPG_PPGC14_PCS1               *((volatile unsigned int*)(0x424858B0UL))
+#define bFM3_MFT_PPG_PPGC14_INTM               *((volatile unsigned int*)(0x424858B4UL))
+#define bFM3_MFT_PPG_PPGC14_PUF                *((volatile unsigned int*)(0x424858B8UL))
+#define bFM3_MFT_PPG_PPGC14_PIE                *((volatile unsigned int*)(0x424858BCUL))
+#define bFM3_MFT_PPG_GATEC12_EDGE12            *((volatile unsigned int*)(0x42485B00UL))
+#define bFM3_MFT_PPG_GATEC12_STRG12            *((volatile unsigned int*)(0x42485B04UL))
+#define bFM3_MFT_PPG_GATEC12_EDGE14            *((volatile unsigned int*)(0x42485B10UL))
+#define bFM3_MFT_PPG_GATEC12_STRG14            *((volatile unsigned int*)(0x42485B14UL))
+#define bFM3_MFT_PPG_PPGC17_TTRG               *((volatile unsigned int*)(0x42486000UL))
+#define bFM3_MFT_PPG_PPGC17_MD0                *((volatile unsigned int*)(0x42486004UL))
+#define bFM3_MFT_PPG_PPGC17_MD1                *((volatile unsigned int*)(0x42486008UL))
+#define bFM3_MFT_PPG_PPGC17_PCS0               *((volatile unsigned int*)(0x4248600CUL))
+#define bFM3_MFT_PPG_PPGC17_PCS1               *((volatile unsigned int*)(0x42486010UL))
+#define bFM3_MFT_PPG_PPGC17_INTM               *((volatile unsigned int*)(0x42486014UL))
+#define bFM3_MFT_PPG_PPGC17_PUF                *((volatile unsigned int*)(0x42486018UL))
+#define bFM3_MFT_PPG_PPGC17_PIE                *((volatile unsigned int*)(0x4248601CUL))
+#define bFM3_MFT_PPG_PPGC16_TTRG               *((volatile unsigned int*)(0x42486020UL))
+#define bFM3_MFT_PPG_PPGC16_MD0                *((volatile unsigned int*)(0x42486024UL))
+#define bFM3_MFT_PPG_PPGC16_MD1                *((volatile unsigned int*)(0x42486028UL))
+#define bFM3_MFT_PPG_PPGC16_PCS0               *((volatile unsigned int*)(0x4248602CUL))
+#define bFM3_MFT_PPG_PPGC16_PCS1               *((volatile unsigned int*)(0x42486030UL))
+#define bFM3_MFT_PPG_PPGC16_INTM               *((volatile unsigned int*)(0x42486034UL))
+#define bFM3_MFT_PPG_PPGC16_PUF                *((volatile unsigned int*)(0x42486038UL))
+#define bFM3_MFT_PPG_PPGC16_PIE                *((volatile unsigned int*)(0x4248603CUL))
+#define bFM3_MFT_PPG_PPGC19_TTRG               *((volatile unsigned int*)(0x42486080UL))
+#define bFM3_MFT_PPG_PPGC19_MD0                *((volatile unsigned int*)(0x42486084UL))
+#define bFM3_MFT_PPG_PPGC19_MD1                *((volatile unsigned int*)(0x42486088UL))
+#define bFM3_MFT_PPG_PPGC19_PCS0               *((volatile unsigned int*)(0x4248608CUL))
+#define bFM3_MFT_PPG_PPGC19_PCS1               *((volatile unsigned int*)(0x42486090UL))
+#define bFM3_MFT_PPG_PPGC19_INTM               *((volatile unsigned int*)(0x42486094UL))
+#define bFM3_MFT_PPG_PPGC19_PUF                *((volatile unsigned int*)(0x42486098UL))
+#define bFM3_MFT_PPG_PPGC19_PIE                *((volatile unsigned int*)(0x4248609CUL))
+#define bFM3_MFT_PPG_PPGC18_TTRG               *((volatile unsigned int*)(0x424860A0UL))
+#define bFM3_MFT_PPG_PPGC18_MD0                *((volatile unsigned int*)(0x424860A4UL))
+#define bFM3_MFT_PPG_PPGC18_MD1                *((volatile unsigned int*)(0x424860A8UL))
+#define bFM3_MFT_PPG_PPGC18_PCS0               *((volatile unsigned int*)(0x424860ACUL))
+#define bFM3_MFT_PPG_PPGC18_PCS1               *((volatile unsigned int*)(0x424860B0UL))
+#define bFM3_MFT_PPG_PPGC18_INTM               *((volatile unsigned int*)(0x424860B4UL))
+#define bFM3_MFT_PPG_PPGC18_PUF                *((volatile unsigned int*)(0x424860B8UL))
+#define bFM3_MFT_PPG_PPGC18_PIE                *((volatile unsigned int*)(0x424860BCUL))
+#define bFM3_MFT_PPG_GATEC16_EDGE16            *((volatile unsigned int*)(0x42486300UL))
+#define bFM3_MFT_PPG_GATEC16_STRG16            *((volatile unsigned int*)(0x42486304UL))
+#define bFM3_MFT_PPG_GATEC16_EDGE18            *((volatile unsigned int*)(0x42486310UL))
+#define bFM3_MFT_PPG_GATEC16_STRG18            *((volatile unsigned int*)(0x42486314UL))
+#define bFM3_MFT_PPG_PPGC21_TTRG               *((volatile unsigned int*)(0x42486800UL))
+#define bFM3_MFT_PPG_PPGC21_MD0                *((volatile unsigned int*)(0x42486804UL))
+#define bFM3_MFT_PPG_PPGC21_MD1                *((volatile unsigned int*)(0x42486808UL))
+#define bFM3_MFT_PPG_PPGC21_PCS0               *((volatile unsigned int*)(0x4248680CUL))
+#define bFM3_MFT_PPG_PPGC21_PCS1               *((volatile unsigned int*)(0x42486810UL))
+#define bFM3_MFT_PPG_PPGC21_INTM               *((volatile unsigned int*)(0x42486814UL))
+#define bFM3_MFT_PPG_PPGC21_PUF                *((volatile unsigned int*)(0x42486818UL))
+#define bFM3_MFT_PPG_PPGC21_PIE                *((volatile unsigned int*)(0x4248681CUL))
+#define bFM3_MFT_PPG_PPGC20_TTRG               *((volatile unsigned int*)(0x42486820UL))
+#define bFM3_MFT_PPG_PPGC20_MD0                *((volatile unsigned int*)(0x42486824UL))
+#define bFM3_MFT_PPG_PPGC20_MD1                *((volatile unsigned int*)(0x42486828UL))
+#define bFM3_MFT_PPG_PPGC20_PCS0               *((volatile unsigned int*)(0x4248682CUL))
+#define bFM3_MFT_PPG_PPGC20_PCS1               *((volatile unsigned int*)(0x42486830UL))
+#define bFM3_MFT_PPG_PPGC20_INTM               *((volatile unsigned int*)(0x42486834UL))
+#define bFM3_MFT_PPG_PPGC20_PUF                *((volatile unsigned int*)(0x42486838UL))
+#define bFM3_MFT_PPG_PPGC20_PIE                *((volatile unsigned int*)(0x4248683CUL))
+#define bFM3_MFT_PPG_PPGC23_TTRG               *((volatile unsigned int*)(0x42486880UL))
+#define bFM3_MFT_PPG_PPGC23_MD0                *((volatile unsigned int*)(0x42486884UL))
+#define bFM3_MFT_PPG_PPGC23_MD1                *((volatile unsigned int*)(0x42486888UL))
+#define bFM3_MFT_PPG_PPGC23_PCS0               *((volatile unsigned int*)(0x4248688CUL))
+#define bFM3_MFT_PPG_PPGC23_PCS1               *((volatile unsigned int*)(0x42486890UL))
+#define bFM3_MFT_PPG_PPGC23_INTM               *((volatile unsigned int*)(0x42486894UL))
+#define bFM3_MFT_PPG_PPGC23_PUF                *((volatile unsigned int*)(0x42486898UL))
+#define bFM3_MFT_PPG_PPGC23_PIE                *((volatile unsigned int*)(0x4248689CUL))
+#define bFM3_MFT_PPG_PPGC22_TTRG               *((volatile unsigned int*)(0x424868A0UL))
+#define bFM3_MFT_PPG_PPGC22_MD0                *((volatile unsigned int*)(0x424868A4UL))
+#define bFM3_MFT_PPG_PPGC22_MD1                *((volatile unsigned int*)(0x424868A8UL))
+#define bFM3_MFT_PPG_PPGC22_PCS0               *((volatile unsigned int*)(0x424868ACUL))
+#define bFM3_MFT_PPG_PPGC22_PCS1               *((volatile unsigned int*)(0x424868B0UL))
+#define bFM3_MFT_PPG_PPGC22_INTM               *((volatile unsigned int*)(0x424868B4UL))
+#define bFM3_MFT_PPG_PPGC22_PUF                *((volatile unsigned int*)(0x424868B8UL))
+#define bFM3_MFT_PPG_PPGC22_PIE                *((volatile unsigned int*)(0x424868BCUL))
+#define bFM3_MFT_PPG_GATEC20_EDGE20            *((volatile unsigned int*)(0x42486B00UL))
+#define bFM3_MFT_PPG_GATEC20_STRG20            *((volatile unsigned int*)(0x42486B04UL))
+#define bFM3_MFT_PPG_GATEC20_EDGE22            *((volatile unsigned int*)(0x42486B10UL))
+#define bFM3_MFT_PPG_GATEC20_STRG22            *((volatile unsigned int*)(0x42486B14UL))
+
+/* Base Timer 0 PPG registers */
+#define bFM3_BT0_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWM registers */
+#define bFM3_BT0_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0204UL))
+#define bFM3_BT0_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0214UL))
+#define bFM3_BT0_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 RT registers */
+#define bFM3_BT0_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWC registers */
+#define bFM3_BT0_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A021CUL))
+#define bFM3_BT0_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 1 PPG registers */
+#define bFM3_BT1_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWM registers */
+#define bFM3_BT1_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0A04UL))
+#define bFM3_BT1_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0A14UL))
+#define bFM3_BT1_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 RT registers */
+#define bFM3_BT1_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWC registers */
+#define bFM3_BT1_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A0A1CUL))
+#define bFM3_BT1_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 2 PPG registers */
+#define bFM3_BT2_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWM registers */
+#define bFM3_BT2_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1204UL))
+#define bFM3_BT2_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1214UL))
+#define bFM3_BT2_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 RT registers */
+#define bFM3_BT2_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWC registers */
+#define bFM3_BT2_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A121CUL))
+#define bFM3_BT2_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 3 PPG registers */
+#define bFM3_BT3_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWM registers */
+#define bFM3_BT3_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1A04UL))
+#define bFM3_BT3_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1A14UL))
+#define bFM3_BT3_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 RT registers */
+#define bFM3_BT3_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWC registers */
+#define bFM3_BT3_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A1A1CUL))
+#define bFM3_BT3_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 4 PPG registers */
+#define bFM3_BT4_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWM registers */
+#define bFM3_BT4_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4204UL))
+#define bFM3_BT4_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4214UL))
+#define bFM3_BT4_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 RT registers */
+#define bFM3_BT4_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWC registers */
+#define bFM3_BT4_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A421CUL))
+#define bFM3_BT4_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 5 PPG registers */
+#define bFM3_BT5_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWM registers */
+#define bFM3_BT5_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4A04UL))
+#define bFM3_BT5_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4A14UL))
+#define bFM3_BT5_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 RT registers */
+#define bFM3_BT5_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWC registers */
+#define bFM3_BT5_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A4A1CUL))
+#define bFM3_BT5_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 6 PPG registers */
+#define bFM3_BT6_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWM registers */
+#define bFM3_BT6_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5204UL))
+#define bFM3_BT6_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5214UL))
+#define bFM3_BT6_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 RT registers */
+#define bFM3_BT6_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWC registers */
+#define bFM3_BT6_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A521CUL))
+#define bFM3_BT6_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 7 PPG registers */
+#define bFM3_BT7_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWM registers */
+#define bFM3_BT7_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5A04UL))
+#define bFM3_BT7_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5A14UL))
+#define bFM3_BT7_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 RT registers */
+#define bFM3_BT7_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWC registers */
+#define bFM3_BT7_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A5A1CUL))
+#define bFM3_BT7_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0       *((volatile unsigned int*)(0x424A2020UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1       *((volatile unsigned int*)(0x424A2024UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2       *((volatile unsigned int*)(0x424A2028UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3       *((volatile unsigned int*)(0x424A202CUL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0       *((volatile unsigned int*)(0x424A2030UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1       *((volatile unsigned int*)(0x424A2034UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2       *((volatile unsigned int*)(0x424A2038UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3       *((volatile unsigned int*)(0x424A203CUL))
+
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0       *((volatile unsigned int*)(0x424A6020UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1       *((volatile unsigned int*)(0x424A6024UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2       *((volatile unsigned int*)(0x424A6028UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3       *((volatile unsigned int*)(0x424A602CUL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0       *((volatile unsigned int*)(0x424A6030UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1       *((volatile unsigned int*)(0x424A6034UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2       *((volatile unsigned int*)(0x424A6038UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3       *((volatile unsigned int*)(0x424A603CUL))
+
+/* Base Timer 8 PPG registers */
+#define bFM3_BT8_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWM registers */
+#define bFM3_BT8_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8204UL))
+#define bFM3_BT8_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8214UL))
+#define bFM3_BT8_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 RT registers */
+#define bFM3_BT8_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWC registers */
+#define bFM3_BT8_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A821CUL))
+#define bFM3_BT8_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 9 PPG registers */
+#define bFM3_BT9_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWM registers */
+#define bFM3_BT9_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8A04UL))
+#define bFM3_BT9_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8A14UL))
+#define bFM3_BT9_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 RT registers */
+#define bFM3_BT9_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWC registers */
+#define bFM3_BT9_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A8A1CUL))
+#define bFM3_BT9_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 10 PPG registers */
+#define bFM3_BT10_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWM registers */
+#define bFM3_BT10_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9204UL))
+#define bFM3_BT10_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9214UL))
+#define bFM3_BT10_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 RT registers */
+#define bFM3_BT10_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWC registers */
+#define bFM3_BT10_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A921CUL))
+#define bFM3_BT10_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 11 PPG registers */
+#define bFM3_BT11_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWM registers */
+#define bFM3_BT11_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9A04UL))
+#define bFM3_BT11_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9A14UL))
+#define bFM3_BT11_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 RT registers */
+#define bFM3_BT11_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWC registers */
+#define bFM3_BT11_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A9A1CUL))
+#define bFM3_BT11_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 12 PPG registers */
+#define bFM3_BT12_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWM registers */
+#define bFM3_BT12_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AC204UL))
+#define bFM3_BT12_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AC214UL))
+#define bFM3_BT12_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 RT registers */
+#define bFM3_BT12_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWC registers */
+#define bFM3_BT12_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AC21CUL))
+#define bFM3_BT12_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 13 PPG registers */
+#define bFM3_BT13_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWM registers */
+#define bFM3_BT13_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ACA04UL))
+#define bFM3_BT13_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ACA14UL))
+#define bFM3_BT13_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 RT registers */
+#define bFM3_BT13_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWC registers */
+#define bFM3_BT13_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ACA1CUL))
+#define bFM3_BT13_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 14 PPG registers */
+#define bFM3_BT14_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWM registers */
+#define bFM3_BT14_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AD204UL))
+#define bFM3_BT14_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AD214UL))
+#define bFM3_BT14_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 RT registers */
+#define bFM3_BT14_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWC registers */
+#define bFM3_BT14_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AD21CUL))
+#define bFM3_BT14_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 15 PPG registers */
+#define bFM3_BT15_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWM registers */
+#define bFM3_BT15_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ADA04UL))
+#define bFM3_BT15_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ADA14UL))
+#define bFM3_BT15_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 RT registers */
+#define bFM3_BT15_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWC registers */
+#define bFM3_BT15_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ADA1CUL))
+#define bFM3_BT15_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0       *((volatile unsigned int*)(0x424AA020UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1       *((volatile unsigned int*)(0x424AA024UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2       *((volatile unsigned int*)(0x424AA028UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3       *((volatile unsigned int*)(0x424AA02CUL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0       *((volatile unsigned int*)(0x424AA030UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1       *((volatile unsigned int*)(0x424AA034UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2       *((volatile unsigned int*)(0x424AA038UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3       *((volatile unsigned int*)(0x424AA03CUL))
+
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0       *((volatile unsigned int*)(0x424AE020UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1       *((volatile unsigned int*)(0x424AE024UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2       *((volatile unsigned int*)(0x424AE028UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3       *((volatile unsigned int*)(0x424AE02CUL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0       *((volatile unsigned int*)(0x424AE030UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1       *((volatile unsigned int*)(0x424AE034UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2       *((volatile unsigned int*)(0x424AE038UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3       *((volatile unsigned int*)(0x424AE03CUL))
+
+/* Software based Simulation Startup (Base Timer) register */
+#define bFM3_SBSSR_BTSSSR_SSR0                 *((volatile unsigned int*)(0x424BFF80UL))
+#define bFM3_SBSSR_BTSSSR_SSR1                 *((volatile unsigned int*)(0x424BFF84UL))
+#define bFM3_SBSSR_BTSSSR_SSR2                 *((volatile unsigned int*)(0x424BFF88UL))
+#define bFM3_SBSSR_BTSSSR_SSR3                 *((volatile unsigned int*)(0x424BFF8CUL))
+#define bFM3_SBSSR_BTSSSR_SSR4                 *((volatile unsigned int*)(0x424BFF90UL))
+#define bFM3_SBSSR_BTSSSR_SSR5                 *((volatile unsigned int*)(0x424BFF94UL))
+#define bFM3_SBSSR_BTSSSR_SSR6                 *((volatile unsigned int*)(0x424BFF98UL))
+#define bFM3_SBSSR_BTSSSR_SSR7                 *((volatile unsigned int*)(0x424BFF9CUL))
+#define bFM3_SBSSR_BTSSSR_SSR8                 *((volatile unsigned int*)(0x424BFFA0UL))
+#define bFM3_SBSSR_BTSSSR_SSR9                 *((volatile unsigned int*)(0x424BFFA4UL))
+#define bFM3_SBSSR_BTSSSR_SSR10                *((volatile unsigned int*)(0x424BFFA8UL))
+#define bFM3_SBSSR_BTSSSR_SSR11                *((volatile unsigned int*)(0x424BFFACUL))
+#define bFM3_SBSSR_BTSSSR_SSR12                *((volatile unsigned int*)(0x424BFFB0UL))
+#define bFM3_SBSSR_BTSSSR_SSR13                *((volatile unsigned int*)(0x424BFFB4UL))
+#define bFM3_SBSSR_BTSSSR_SSR14                *((volatile unsigned int*)(0x424BFFB8UL))
+#define bFM3_SBSSR_BTSSSR_SSR15                *((volatile unsigned int*)(0x424BFFBCUL))
+
+/* Quad position and revolution counter channel 0 registers */
+#define bFM3_QPRC0_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICR_UFDF                   *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICR_OFDF                   *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICR_ZIIF                   *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICR_CDCIE                  *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICR_CDCF                   *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICR_DIRPC                  *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICR_DIROU                  *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICRH_CDCF                  *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICRH_DIROU                 *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QCR_PCM0                    *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCR_PCM1                    *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCR_RCM0                    *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCR_RCM1                    *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCR_PSTP                    *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCR_CGSC                    *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCR_RSEL                    *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCR_SWAP                    *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCR_AES0                    *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCR_AES1                    *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCR_BES0                    *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCR_BES1                    *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCR_CGE0                    *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCR_CGE1                    *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCRL_RCM1                   *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCRL_SWAP                   *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCRH_AES0                   *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCRH_AES1                   *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCRH_BES0                   *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCRH_BES1                   *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCRH_CGE1                   *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0380UL))
+#define bFM3_QPRC0_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0384UL))
+#define bFM3_QPRC0_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0388UL))
+
+/* Quad position and revolution counter channel 1 registers */
+#define bFM3_QPRC1_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICR_UFDF                   *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICR_OFDF                   *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICR_ZIIF                   *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICR_CDCIE                  *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICR_CDCF                   *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICR_DIRPC                  *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICR_DIROU                  *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICRH_CDCF                  *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICRH_DIROU                 *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QCR_PCM0                    *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCR_PCM1                    *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCR_RCM0                    *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCR_RCM1                    *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCR_PSTP                    *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCR_CGSC                    *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCR_RSEL                    *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCR_SWAP                    *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCR_AES0                    *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCR_AES1                    *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCR_BES0                    *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCR_BES1                    *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCR_CGE0                    *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCR_CGE1                    *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCRL_RCM1                   *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCRL_SWAP                   *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCRH_AES0                   *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCRH_AES1                   *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCRH_BES0                   *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCRH_BES1                   *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCRH_CGE1                   *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0B80UL))
+#define bFM3_QPRC1_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0B84UL))
+#define bFM3_QPRC1_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0B88UL))
+
+/* Quad position and revolution counter channel 2 registers */
+#define bFM3_QPRC2_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICR_QPCMF                  *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICR_OUZIE                  *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICR_UFDF                   *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICR_OFDF                   *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICR_ZIIF                   *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICR_CDCIE                  *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICR_CDCF                   *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICR_DIRPC                  *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICR_DIROU                  *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICRL_UFDF                  *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICRL_OFDF                  *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICRH_CDCF                  *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICRH_DIROU                 *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QCR_PCM0                    *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCR_PCM1                    *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCR_RCM0                    *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCR_RCM1                    *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCR_PSTP                    *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCR_CGSC                    *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCR_RSEL                    *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCR_SWAP                    *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCR_PCRM0                   *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCR_PCRM1                   *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCR_AES0                    *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCR_AES1                    *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCR_BES0                    *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCR_BES1                    *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCR_CGE0                    *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCR_CGE1                    *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QCRL_PCM0                   *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCRL_PCM1                   *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCRL_RCM0                   *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCRL_RCM1                   *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCRL_PSTP                   *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCRL_CGSC                   *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCRL_RSEL                   *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCRL_SWAP                   *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCRH_AES0                   *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCRH_AES1                   *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCRH_BES0                   *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCRH_BES1                   *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCRH_CGE0                   *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCRH_CGE1                   *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C1380UL))
+#define bFM3_QPRC2_QECR_ORNGF                  *((volatile unsigned int*)(0x424C1384UL))
+#define bFM3_QPRC2_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C1388UL))
+
+/* 12-bit ADC unit 0 registers */
+#define bFM3_ADC0_ADSR_SCS                     *((volatile unsigned int*)(0x424E0000UL))
+#define bFM3_ADC0_ADSR_PCS                     *((volatile unsigned int*)(0x424E0004UL))
+#define bFM3_ADC0_ADSR_PCNS                    *((volatile unsigned int*)(0x424E0008UL))
+#define bFM3_ADC0_ADSR_FDAS                    *((volatile unsigned int*)(0x424E0018UL))
+#define bFM3_ADC0_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E001CUL))
+#define bFM3_ADC0_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E0020UL))
+#define bFM3_ADC0_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E0024UL))
+#define bFM3_ADC0_ADCR_PCIE                    *((volatile unsigned int*)(0x424E0028UL))
+#define bFM3_ADC0_ADCR_SCIE                    *((volatile unsigned int*)(0x424E002CUL))
+#define bFM3_ADC0_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E0034UL))
+#define bFM3_ADC0_ADCR_PCIF                    *((volatile unsigned int*)(0x424E0038UL))
+#define bFM3_ADC0_ADCR_SCIF                    *((volatile unsigned int*)(0x424E003CUL))
+#define bFM3_ADC0_SFNS_SFS0                    *((volatile unsigned int*)(0x424E0100UL))
+#define bFM3_ADC0_SFNS_SFS1                    *((volatile unsigned int*)(0x424E0104UL))
+#define bFM3_ADC0_SFNS_SFS2                    *((volatile unsigned int*)(0x424E0108UL))
+#define bFM3_ADC0_SFNS_SFS3                    *((volatile unsigned int*)(0x424E010CUL))
+#define bFM3_ADC0_SCCR_SSTR                    *((volatile unsigned int*)(0x424E0120UL))
+#define bFM3_ADC0_SCCR_SHEN                    *((volatile unsigned int*)(0x424E0124UL))
+#define bFM3_ADC0_SCCR_RPT                     *((volatile unsigned int*)(0x424E0128UL))
+#define bFM3_ADC0_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E0130UL))
+#define bFM3_ADC0_SCCR_SOVR                    *((volatile unsigned int*)(0x424E0134UL))
+#define bFM3_ADC0_SCCR_SFUL                    *((volatile unsigned int*)(0x424E0138UL))
+#define bFM3_ADC0_SCCR_SEMP                    *((volatile unsigned int*)(0x424E013CUL))
+#define bFM3_ADC0_SCFD_SC0                     *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFD_SC1                     *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFD_SC2                     *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFD_SC3                     *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFD_SC4                     *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFD_RS0                     *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFD_RS1                     *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFD_INVL                    *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFD_SD0                     *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFD_SD1                     *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFD_SD2                     *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFD_SD3                     *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFD_SD4                     *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFD_SD5                     *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFD_SD6                     *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFD_SD7                     *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFD_SD8                     *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFD_SD9                     *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFD_SD10                    *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFD_SD11                    *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCFDL_SC0                    *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFDL_SC1                    *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFDL_SC2                    *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFDL_SC3                    *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFDL_SC4                    *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFDL_RS0                    *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFDL_RS1                    *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFDL_INVL                   *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFDH_SD0                    *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFDH_SD1                    *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFDH_SD2                    *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFDH_SD3                    *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFDH_SD4                    *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFDH_SD5                    *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFDH_SD6                    *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFDH_SD7                    *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFDH_SD8                    *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFDH_SD9                    *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFDH_SD10                   *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFDH_SD11                   *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCIS23_AN16                  *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS23_AN17                  *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS23_AN18                  *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS23_AN19                  *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS23_AN20                  *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS23_AN21                  *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS23_AN22                  *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS23_AN23                  *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS23_AN24                  *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS23_AN25                  *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS23_AN26                  *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS23_AN27                  *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS23_AN28                  *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS23_AN29                  *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS23_AN30                  *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS23_AN31                  *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS2_AN16                   *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS2_AN17                   *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS2_AN18                   *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS2_AN19                   *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS2_AN20                   *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS2_AN21                   *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS2_AN22                   *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS2_AN23                   *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS3_AN24                   *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS3_AN25                   *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS3_AN26                   *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS3_AN27                   *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS3_AN28                   *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS3_AN29                   *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS3_AN30                   *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS3_AN31                   *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS01_AN0                   *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS01_AN1                   *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS01_AN2                   *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS01_AN3                   *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS01_AN4                   *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS01_AN5                   *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS01_AN6                   *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS01_AN7                   *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS01_AN8                   *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS01_AN9                   *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS01_AN10                  *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS01_AN11                  *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS01_AN12                  *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS01_AN13                  *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS01_AN14                  *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS01_AN15                  *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_SCIS0_AN0                    *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS0_AN1                    *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS0_AN2                    *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS0_AN3                    *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS0_AN4                    *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS0_AN5                    *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS0_AN6                    *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS0_AN7                    *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS1_AN8                    *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS1_AN9                    *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS1_AN10                   *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS1_AN11                   *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS1_AN12                   *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS1_AN13                   *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS1_AN14                   *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS1_AN15                   *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_PFNS_PFS0                    *((volatile unsigned int*)(0x424E0300UL))
+#define bFM3_ADC0_PFNS_PFS1                    *((volatile unsigned int*)(0x424E0304UL))
+#define bFM3_ADC0_PFNS_TEST0                   *((volatile unsigned int*)(0x424E0310UL))
+#define bFM3_ADC0_PFNS_TEST1                   *((volatile unsigned int*)(0x424E0314UL))
+#define bFM3_ADC0_PCCR_PSTR                    *((volatile unsigned int*)(0x424E0320UL))
+#define bFM3_ADC0_PCCR_PHEN                    *((volatile unsigned int*)(0x424E0324UL))
+#define bFM3_ADC0_PCCR_PEEN                    *((volatile unsigned int*)(0x424E0328UL))
+#define bFM3_ADC0_PCCR_ESCE                    *((volatile unsigned int*)(0x424E032CUL))
+#define bFM3_ADC0_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E0330UL))
+#define bFM3_ADC0_PCCR_POVR                    *((volatile unsigned int*)(0x424E0334UL))
+#define bFM3_ADC0_PCCR_PFUL                    *((volatile unsigned int*)(0x424E0338UL))
+#define bFM3_ADC0_PCCR_PEMP                    *((volatile unsigned int*)(0x424E033CUL))
+#define bFM3_ADC0_PCFD_PC0                     *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFD_PC1                     *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFD_PC2                     *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFD_PC3                     *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFD_PC4                     *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFD_RS0                     *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFD_RS1                     *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFD_RS2                     *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFD_INVL                    *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFD_PD0                     *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFD_PD1                     *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFD_PD2                     *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFD_PD3                     *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFD_PD4                     *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFD_PD5                     *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFD_PD6                     *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFD_PD7                     *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFD_PD8                     *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFD_PD9                     *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFD_PD10                    *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFD_PD11                    *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCFDL_PC0                    *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFDL_PC1                    *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFDL_PC2                    *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFDL_PC3                    *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFDL_PC4                    *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFDL_RS0                    *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFDL_RS1                    *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFDL_RS2                    *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFDL_INVL                   *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFDH_PD0                    *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFDH_PD1                    *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFDH_PD2                    *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFDH_PD3                    *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFDH_PD4                    *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFDH_PD5                    *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFDH_PD6                    *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFDH_PD7                    *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFDH_PD8                    *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFDH_PD9                    *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFDH_PD10                   *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFDH_PD11                   *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCIS_P1A0                    *((volatile unsigned int*)(0x424E0400UL))
+#define bFM3_ADC0_PCIS_P1A1                    *((volatile unsigned int*)(0x424E0404UL))
+#define bFM3_ADC0_PCIS_P1A2                    *((volatile unsigned int*)(0x424E0408UL))
+#define bFM3_ADC0_PCIS_P2A0                    *((volatile unsigned int*)(0x424E040CUL))
+#define bFM3_ADC0_PCIS_P2A1                    *((volatile unsigned int*)(0x424E0410UL))
+#define bFM3_ADC0_PCIS_P2A2                    *((volatile unsigned int*)(0x424E0414UL))
+#define bFM3_ADC0_PCIS_P2A3                    *((volatile unsigned int*)(0x424E0418UL))
+#define bFM3_ADC0_PCIS_P2A4                    *((volatile unsigned int*)(0x424E041CUL))
+#define bFM3_ADC0_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E0480UL))
+#define bFM3_ADC0_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E0484UL))
+#define bFM3_ADC0_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E0488UL))
+#define bFM3_ADC0_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E048CUL))
+#define bFM3_ADC0_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E0490UL))
+#define bFM3_ADC0_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E0494UL))
+#define bFM3_ADC0_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E0498UL))
+#define bFM3_ADC0_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E049CUL))
+#define bFM3_ADC0_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E04D8UL))
+#define bFM3_ADC0_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E04DCUL))
+#define bFM3_ADC0_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E04E0UL))
+#define bFM3_ADC0_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E04E4UL))
+#define bFM3_ADC0_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E04E8UL))
+#define bFM3_ADC0_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E04ECUL))
+#define bFM3_ADC0_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E04F0UL))
+#define bFM3_ADC0_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E04F4UL))
+#define bFM3_ADC0_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E04F8UL))
+#define bFM3_ADC0_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E04FCUL))
+#define bFM3_ADC0_ADSS23_TS16                  *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS23_TS17                  *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS23_TS18                  *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS23_TS19                  *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS23_TS20                  *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS23_TS21                  *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS23_TS22                  *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS23_TS23                  *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS23_TS24                  *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS23_TS25                  *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS23_TS26                  *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS23_TS27                  *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS23_TS28                  *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS23_TS29                  *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS23_TS30                  *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS23_TS31                  *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS2_TS16                   *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS2_TS17                   *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS2_TS18                   *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS2_TS19                   *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS2_TS20                   *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS2_TS21                   *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS2_TS22                   *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS2_TS23                   *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS3_TS24                   *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS3_TS25                   *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS3_TS26                   *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS3_TS27                   *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS3_TS28                   *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS3_TS29                   *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS3_TS30                   *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS3_TS31                   *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS01_TS0                   *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS01_TS1                   *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS01_TS2                   *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS01_TS3                   *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS01_TS4                   *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS01_TS5                   *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS01_TS6                   *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS01_TS7                   *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS01_TS8                   *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS01_TS9                   *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS01_TS10                  *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS01_TS11                  *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS01_TS12                  *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS01_TS13                  *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS01_TS14                  *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS01_TS15                  *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADSS0_TS0                    *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS0_TS1                    *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS0_TS2                    *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS0_TS3                    *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS0_TS4                    *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS0_TS5                    *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS0_TS6                    *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS0_TS7                    *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS1_TS8                    *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS1_TS9                    *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS1_TS10                   *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS1_TS11                   *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS1_TS12                   *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS1_TS13                   *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS1_TS14                   *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS1_TS15                   *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADST01_ST10                  *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST01_ST11                  *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST01_ST12                  *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST01_ST13                  *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST01_ST14                  *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST01_STX10                 *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST01_STX11                 *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST01_STX12                 *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST01_ST00                  *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST01_ST01                  *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST01_ST02                  *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST01_ST03                  *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST01_ST04                  *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST01_STX00                 *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST01_STX01                 *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST01_STX02                 *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADST1_ST10                   *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST1_ST11                   *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST1_ST12                   *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST1_ST13                   *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST1_ST14                   *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST1_STX10                  *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST1_STX11                  *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST1_STX12                  *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST0_ST00                   *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST0_ST01                   *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST0_ST02                   *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST0_ST03                   *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST0_ST04                   *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST0_STX00                  *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST0_STX01                  *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST0_STX02                  *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADCT_CT0                     *((volatile unsigned int*)(0x424E0680UL))
+#define bFM3_ADC0_ADCT_CT1                     *((volatile unsigned int*)(0x424E0684UL))
+#define bFM3_ADC0_ADCT_CT2                     *((volatile unsigned int*)(0x424E0688UL))
+#define bFM3_ADC0_ADCT_CT3                     *((volatile unsigned int*)(0x424E068CUL))
+#define bFM3_ADC0_ADCT_CT4                     *((volatile unsigned int*)(0x424E0690UL))
+#define bFM3_ADC0_ADCT_CT5                     *((volatile unsigned int*)(0x424E0694UL))
+#define bFM3_ADC0_ADCT_CT6                     *((volatile unsigned int*)(0x424E0698UL))
+#define bFM3_ADC0_ADCT_CT7                     *((volatile unsigned int*)(0x424E069CUL))
+#define bFM3_ADC0_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E0700UL))
+#define bFM3_ADC0_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E0704UL))
+#define bFM3_ADC0_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E0708UL))
+#define bFM3_ADC0_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E070CUL))
+#define bFM3_ADC0_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E0720UL))
+#define bFM3_ADC0_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E0724UL))
+#define bFM3_ADC0_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E0728UL))
+#define bFM3_ADC0_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E072CUL))
+#define bFM3_ADC0_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E0780UL))
+#define bFM3_ADC0_ADCEN_READY                  *((volatile unsigned int*)(0x424E0784UL))
+#define bFM3_ADC0_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E0790UL))
+#define bFM3_ADC0_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E0794UL))
+
+/* 12-bit ADC unit 1 registers */
+#define bFM3_ADC1_ADSR_SCS                     *((volatile unsigned int*)(0x424E2000UL))
+#define bFM3_ADC1_ADSR_PCS                     *((volatile unsigned int*)(0x424E2004UL))
+#define bFM3_ADC1_ADSR_PCNS                    *((volatile unsigned int*)(0x424E2008UL))
+#define bFM3_ADC1_ADSR_FDAS                    *((volatile unsigned int*)(0x424E2018UL))
+#define bFM3_ADC1_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E201CUL))
+#define bFM3_ADC1_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E2020UL))
+#define bFM3_ADC1_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E2024UL))
+#define bFM3_ADC1_ADCR_PCIE                    *((volatile unsigned int*)(0x424E2028UL))
+#define bFM3_ADC1_ADCR_SCIE                    *((volatile unsigned int*)(0x424E202CUL))
+#define bFM3_ADC1_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E2034UL))
+#define bFM3_ADC1_ADCR_PCIF                    *((volatile unsigned int*)(0x424E2038UL))
+#define bFM3_ADC1_ADCR_SCIF                    *((volatile unsigned int*)(0x424E203CUL))
+#define bFM3_ADC1_SFNS_SFS0                    *((volatile unsigned int*)(0x424E2100UL))
+#define bFM3_ADC1_SFNS_SFS1                    *((volatile unsigned int*)(0x424E2104UL))
+#define bFM3_ADC1_SFNS_SFS2                    *((volatile unsigned int*)(0x424E2108UL))
+#define bFM3_ADC1_SFNS_SFS3                    *((volatile unsigned int*)(0x424E210CUL))
+#define bFM3_ADC1_SCCR_SSTR                    *((volatile unsigned int*)(0x424E2120UL))
+#define bFM3_ADC1_SCCR_SHEN                    *((volatile unsigned int*)(0x424E2124UL))
+#define bFM3_ADC1_SCCR_RPT                     *((volatile unsigned int*)(0x424E2128UL))
+#define bFM3_ADC1_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E2130UL))
+#define bFM3_ADC1_SCCR_SOVR                    *((volatile unsigned int*)(0x424E2134UL))
+#define bFM3_ADC1_SCCR_SFUL                    *((volatile unsigned int*)(0x424E2138UL))
+#define bFM3_ADC1_SCCR_SEMP                    *((volatile unsigned int*)(0x424E213CUL))
+#define bFM3_ADC1_SCFD_SC0                     *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFD_SC1                     *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFD_SC2                     *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFD_SC3                     *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFD_SC4                     *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFD_RS0                     *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFD_RS1                     *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFD_INVL                    *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFD_SD0                     *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFD_SD1                     *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFD_SD2                     *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFD_SD3                     *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFD_SD4                     *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFD_SD5                     *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFD_SD6                     *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFD_SD7                     *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFD_SD8                     *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFD_SD9                     *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFD_SD10                    *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFD_SD11                    *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCFDL_SC0                    *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFDL_SC1                    *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFDL_SC2                    *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFDL_SC3                    *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFDL_SC4                    *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFDL_RS0                    *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFDL_RS1                    *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFDL_INVL                   *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFDH_SD0                    *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFDH_SD1                    *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFDH_SD2                    *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFDH_SD3                    *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFDH_SD4                    *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFDH_SD5                    *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFDH_SD6                    *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFDH_SD7                    *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFDH_SD8                    *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFDH_SD9                    *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFDH_SD10                   *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFDH_SD11                   *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCIS23_AN16                  *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS23_AN17                  *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS23_AN18                  *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS23_AN19                  *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS23_AN20                  *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS23_AN21                  *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS23_AN22                  *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS23_AN23                  *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS23_AN24                  *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS23_AN25                  *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS23_AN26                  *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS23_AN27                  *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS23_AN28                  *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS23_AN29                  *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS23_AN30                  *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS23_AN31                  *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS2_AN16                   *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS2_AN17                   *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS2_AN18                   *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS2_AN19                   *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS2_AN20                   *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS2_AN21                   *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS2_AN22                   *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS2_AN23                   *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS3_AN24                   *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS3_AN25                   *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS3_AN26                   *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS3_AN27                   *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS3_AN28                   *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS3_AN29                   *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS3_AN30                   *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS3_AN31                   *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS01_AN0                   *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS01_AN1                   *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS01_AN2                   *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS01_AN3                   *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS01_AN4                   *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS01_AN5                   *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS01_AN6                   *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS01_AN7                   *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS01_AN8                   *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS01_AN9                   *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS01_AN10                  *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS01_AN11                  *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS01_AN12                  *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS01_AN13                  *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS01_AN14                  *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS01_AN15                  *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_SCIS0_AN0                    *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS0_AN1                    *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS0_AN2                    *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS0_AN3                    *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS0_AN4                    *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS0_AN5                    *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS0_AN6                    *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS0_AN7                    *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS1_AN8                    *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS1_AN9                    *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS1_AN10                   *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS1_AN11                   *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS1_AN12                   *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS1_AN13                   *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS1_AN14                   *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS1_AN15                   *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_PFNS_PFS0                    *((volatile unsigned int*)(0x424E2300UL))
+#define bFM3_ADC1_PFNS_PFS1                    *((volatile unsigned int*)(0x424E2304UL))
+#define bFM3_ADC1_PFNS_TEST0                   *((volatile unsigned int*)(0x424E2310UL))
+#define bFM3_ADC1_PFNS_TEST1                   *((volatile unsigned int*)(0x424E2314UL))
+#define bFM3_ADC1_PCCR_PSTR                    *((volatile unsigned int*)(0x424E2320UL))
+#define bFM3_ADC1_PCCR_PHEN                    *((volatile unsigned int*)(0x424E2324UL))
+#define bFM3_ADC1_PCCR_PEEN                    *((volatile unsigned int*)(0x424E2328UL))
+#define bFM3_ADC1_PCCR_ESCE                    *((volatile unsigned int*)(0x424E232CUL))
+#define bFM3_ADC1_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E2330UL))
+#define bFM3_ADC1_PCCR_POVR                    *((volatile unsigned int*)(0x424E2334UL))
+#define bFM3_ADC1_PCCR_PFUL                    *((volatile unsigned int*)(0x424E2338UL))
+#define bFM3_ADC1_PCCR_PEMP                    *((volatile unsigned int*)(0x424E233CUL))
+#define bFM3_ADC1_PCFD_PC0                     *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFD_PC1                     *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFD_PC2                     *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFD_PC3                     *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFD_PC4                     *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFD_RS0                     *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFD_RS1                     *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFD_RS2                     *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFD_INVL                    *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFD_PD0                     *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFD_PD1                     *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFD_PD2                     *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFD_PD3                     *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFD_PD4                     *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFD_PD5                     *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFD_PD6                     *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFD_PD7                     *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFD_PD8                     *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFD_PD9                     *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFD_PD10                    *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFD_PD11                    *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCFDL_PC0                    *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFDL_PC1                    *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFDL_PC2                    *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFDL_PC3                    *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFDL_PC4                    *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFDL_RS0                    *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFDL_RS1                    *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFDL_RS2                    *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFDL_INVL                   *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFDH_PD0                    *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFDH_PD1                    *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFDH_PD2                    *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFDH_PD3                    *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFDH_PD4                    *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFDH_PD5                    *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFDH_PD6                    *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFDH_PD7                    *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFDH_PD8                    *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFDH_PD9                    *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFDH_PD10                   *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFDH_PD11                   *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCIS_P1A0                    *((volatile unsigned int*)(0x424E2400UL))
+#define bFM3_ADC1_PCIS_P1A1                    *((volatile unsigned int*)(0x424E2404UL))
+#define bFM3_ADC1_PCIS_P1A2                    *((volatile unsigned int*)(0x424E2408UL))
+#define bFM3_ADC1_PCIS_P2A0                    *((volatile unsigned int*)(0x424E240CUL))
+#define bFM3_ADC1_PCIS_P2A1                    *((volatile unsigned int*)(0x424E2410UL))
+#define bFM3_ADC1_PCIS_P2A2                    *((volatile unsigned int*)(0x424E2414UL))
+#define bFM3_ADC1_PCIS_P2A3                    *((volatile unsigned int*)(0x424E2418UL))
+#define bFM3_ADC1_PCIS_P2A4                    *((volatile unsigned int*)(0x424E241CUL))
+#define bFM3_ADC1_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E2480UL))
+#define bFM3_ADC1_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E2484UL))
+#define bFM3_ADC1_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E2488UL))
+#define bFM3_ADC1_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E248CUL))
+#define bFM3_ADC1_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E2490UL))
+#define bFM3_ADC1_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E2494UL))
+#define bFM3_ADC1_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E2498UL))
+#define bFM3_ADC1_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E249CUL))
+#define bFM3_ADC1_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E24D8UL))
+#define bFM3_ADC1_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E24DCUL))
+#define bFM3_ADC1_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E24E0UL))
+#define bFM3_ADC1_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E24E4UL))
+#define bFM3_ADC1_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E24E8UL))
+#define bFM3_ADC1_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E24ECUL))
+#define bFM3_ADC1_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E24F0UL))
+#define bFM3_ADC1_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E24F4UL))
+#define bFM3_ADC1_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E24F8UL))
+#define bFM3_ADC1_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E24FCUL))
+#define bFM3_ADC1_ADSS23_TS16                  *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS23_TS17                  *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS23_TS18                  *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS23_TS19                  *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS23_TS20                  *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS23_TS21                  *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS23_TS22                  *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS23_TS23                  *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS23_TS24                  *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS23_TS25                  *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS23_TS26                  *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS23_TS27                  *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS23_TS28                  *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS23_TS29                  *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS23_TS30                  *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS23_TS31                  *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS2_TS16                   *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS2_TS17                   *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS2_TS18                   *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS2_TS19                   *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS2_TS20                   *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS2_TS21                   *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS2_TS22                   *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS2_TS23                   *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS3_TS24                   *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS3_TS25                   *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS3_TS26                   *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS3_TS27                   *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS3_TS28                   *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS3_TS29                   *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS3_TS30                   *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS3_TS31                   *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS01_TS0                   *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS01_TS1                   *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS01_TS2                   *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS01_TS3                   *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS01_TS4                   *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS01_TS5                   *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS01_TS6                   *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS01_TS7                   *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS01_TS8                   *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS01_TS9                   *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS01_TS10                  *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS01_TS11                  *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS01_TS12                  *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS01_TS13                  *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS01_TS14                  *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS01_TS15                  *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADSS0_TS0                    *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS0_TS1                    *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS0_TS2                    *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS0_TS3                    *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS0_TS4                    *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS0_TS5                    *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS0_TS6                    *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS0_TS7                    *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS1_TS8                    *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS1_TS9                    *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS1_TS10                   *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS1_TS11                   *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS1_TS12                   *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS1_TS13                   *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS1_TS14                   *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS1_TS15                   *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADST01_ST10                  *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST01_ST11                  *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST01_ST12                  *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST01_ST13                  *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST01_ST14                  *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST01_STX10                 *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST01_STX11                 *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST01_STX12                 *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST01_ST00                  *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST01_ST01                  *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST01_ST02                  *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST01_ST03                  *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST01_ST04                  *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST01_STX00                 *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST01_STX01                 *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST01_STX02                 *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADST1_ST10                   *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST1_ST11                   *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST1_ST12                   *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST1_ST13                   *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST1_ST14                   *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST1_STX10                  *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST1_STX11                  *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST1_STX12                  *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST0_ST00                   *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST0_ST01                   *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST0_ST02                   *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST0_ST03                   *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST0_ST04                   *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST0_STX00                  *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST0_STX01                  *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST0_STX02                  *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADCT_CT0                     *((volatile unsigned int*)(0x424E2680UL))
+#define bFM3_ADC1_ADCT_CT1                     *((volatile unsigned int*)(0x424E2684UL))
+#define bFM3_ADC1_ADCT_CT2                     *((volatile unsigned int*)(0x424E2688UL))
+#define bFM3_ADC1_ADCT_CT3                     *((volatile unsigned int*)(0x424E268CUL))
+#define bFM3_ADC1_ADCT_CT4                     *((volatile unsigned int*)(0x424E2690UL))
+#define bFM3_ADC1_ADCT_CT5                     *((volatile unsigned int*)(0x424E2694UL))
+#define bFM3_ADC1_ADCT_CT6                     *((volatile unsigned int*)(0x424E2698UL))
+#define bFM3_ADC1_ADCT_CT7                     *((volatile unsigned int*)(0x424E269CUL))
+#define bFM3_ADC1_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E2700UL))
+#define bFM3_ADC1_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E2704UL))
+#define bFM3_ADC1_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E2708UL))
+#define bFM3_ADC1_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E270CUL))
+#define bFM3_ADC1_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E2720UL))
+#define bFM3_ADC1_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E2724UL))
+#define bFM3_ADC1_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E2728UL))
+#define bFM3_ADC1_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E272CUL))
+#define bFM3_ADC1_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E2780UL))
+#define bFM3_ADC1_ADCEN_READY                  *((volatile unsigned int*)(0x424E2784UL))
+#define bFM3_ADC1_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E2790UL))
+#define bFM3_ADC1_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E2794UL))
+
+/* 12-bit ADC unit 2 registers */
+#define bFM3_ADC2_ADSR_SCS                     *((volatile unsigned int*)(0x424E4000UL))
+#define bFM3_ADC2_ADSR_PCS                     *((volatile unsigned int*)(0x424E4004UL))
+#define bFM3_ADC2_ADSR_PCNS                    *((volatile unsigned int*)(0x424E4008UL))
+#define bFM3_ADC2_ADSR_FDAS                    *((volatile unsigned int*)(0x424E4018UL))
+#define bFM3_ADC2_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E401CUL))
+#define bFM3_ADC2_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E4020UL))
+#define bFM3_ADC2_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E4024UL))
+#define bFM3_ADC2_ADCR_PCIE                    *((volatile unsigned int*)(0x424E4028UL))
+#define bFM3_ADC2_ADCR_SCIE                    *((volatile unsigned int*)(0x424E402CUL))
+#define bFM3_ADC2_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E4034UL))
+#define bFM3_ADC2_ADCR_PCIF                    *((volatile unsigned int*)(0x424E4038UL))
+#define bFM3_ADC2_ADCR_SCIF                    *((volatile unsigned int*)(0x424E403CUL))
+#define bFM3_ADC2_SFNS_SFS0                    *((volatile unsigned int*)(0x424E4100UL))
+#define bFM3_ADC2_SFNS_SFS1                    *((volatile unsigned int*)(0x424E4104UL))
+#define bFM3_ADC2_SFNS_SFS2                    *((volatile unsigned int*)(0x424E4108UL))
+#define bFM3_ADC2_SFNS_SFS3                    *((volatile unsigned int*)(0x424E410CUL))
+#define bFM3_ADC2_SCCR_SSTR                    *((volatile unsigned int*)(0x424E4120UL))
+#define bFM3_ADC2_SCCR_SHEN                    *((volatile unsigned int*)(0x424E4124UL))
+#define bFM3_ADC2_SCCR_RPT                     *((volatile unsigned int*)(0x424E4128UL))
+#define bFM3_ADC2_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E4130UL))
+#define bFM3_ADC2_SCCR_SOVR                    *((volatile unsigned int*)(0x424E4134UL))
+#define bFM3_ADC2_SCCR_SFUL                    *((volatile unsigned int*)(0x424E4138UL))
+#define bFM3_ADC2_SCCR_SEMP                    *((volatile unsigned int*)(0x424E413CUL))
+#define bFM3_ADC2_SCFD_SC0                     *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFD_SC1                     *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFD_SC2                     *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFD_SC3                     *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFD_SC4                     *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFD_RS0                     *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFD_RS1                     *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFD_INVL                    *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFD_SD0                     *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFD_SD1                     *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFD_SD2                     *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFD_SD3                     *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFD_SD4                     *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFD_SD5                     *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFD_SD6                     *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFD_SD7                     *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFD_SD8                     *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFD_SD9                     *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFD_SD10                    *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFD_SD11                    *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCFDL_SC0                    *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFDL_SC1                    *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFDL_SC2                    *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFDL_SC3                    *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFDL_SC4                    *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFDL_RS0                    *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFDL_RS1                    *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFDL_INVL                   *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFDH_SD0                    *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFDH_SD1                    *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFDH_SD2                    *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFDH_SD3                    *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFDH_SD4                    *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFDH_SD5                    *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFDH_SD6                    *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFDH_SD7                    *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFDH_SD8                    *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFDH_SD9                    *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFDH_SD10                   *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFDH_SD11                   *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCIS23_AN16                  *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS23_AN17                  *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS23_AN18                  *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS23_AN19                  *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS23_AN20                  *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS23_AN21                  *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS23_AN22                  *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS23_AN23                  *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS23_AN24                  *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS23_AN25                  *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS23_AN26                  *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS23_AN27                  *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS23_AN28                  *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS23_AN29                  *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS23_AN30                  *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS23_AN31                  *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS2_AN16                   *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS2_AN17                   *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS2_AN18                   *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS2_AN19                   *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS2_AN20                   *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS2_AN21                   *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS2_AN22                   *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS2_AN23                   *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS3_AN24                   *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS3_AN25                   *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS3_AN26                   *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS3_AN27                   *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS3_AN28                   *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS3_AN29                   *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS3_AN30                   *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS3_AN31                   *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS01_AN0                   *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS01_AN1                   *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS01_AN2                   *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS01_AN3                   *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS01_AN4                   *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS01_AN5                   *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS01_AN6                   *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS01_AN7                   *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS01_AN8                   *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS01_AN9                   *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS01_AN10                  *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS01_AN11                  *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS01_AN12                  *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS01_AN13                  *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS01_AN14                  *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS01_AN15                  *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_SCIS0_AN0                    *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS0_AN1                    *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS0_AN2                    *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS0_AN3                    *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS0_AN4                    *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS0_AN5                    *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS0_AN6                    *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS0_AN7                    *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS1_AN8                    *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS1_AN9                    *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS1_AN10                   *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS1_AN11                   *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS1_AN12                   *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS1_AN13                   *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS1_AN14                   *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS1_AN15                   *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_PFNS_PFS0                    *((volatile unsigned int*)(0x424E4300UL))
+#define bFM3_ADC2_PFNS_PFS1                    *((volatile unsigned int*)(0x424E4304UL))
+#define bFM3_ADC2_PFNS_TEST0                   *((volatile unsigned int*)(0x424E4310UL))
+#define bFM3_ADC2_PFNS_TEST1                   *((volatile unsigned int*)(0x424E4314UL))
+#define bFM3_ADC2_PCCR_PSTR                    *((volatile unsigned int*)(0x424E4320UL))
+#define bFM3_ADC2_PCCR_PHEN                    *((volatile unsigned int*)(0x424E4324UL))
+#define bFM3_ADC2_PCCR_PEEN                    *((volatile unsigned int*)(0x424E4328UL))
+#define bFM3_ADC2_PCCR_ESCE                    *((volatile unsigned int*)(0x424E432CUL))
+#define bFM3_ADC2_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E4330UL))
+#define bFM3_ADC2_PCCR_POVR                    *((volatile unsigned int*)(0x424E4334UL))
+#define bFM3_ADC2_PCCR_PFUL                    *((volatile unsigned int*)(0x424E4338UL))
+#define bFM3_ADC2_PCCR_PEMP                    *((volatile unsigned int*)(0x424E433CUL))
+#define bFM3_ADC2_PCFD_PC0                     *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFD_PC1                     *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFD_PC2                     *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFD_PC3                     *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFD_PC4                     *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFD_RS0                     *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFD_RS1                     *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFD_RS2                     *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFD_INVL                    *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFD_PD0                     *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFD_PD1                     *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFD_PD2                     *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFD_PD3                     *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFD_PD4                     *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFD_PD5                     *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFD_PD6                     *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFD_PD7                     *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFD_PD8                     *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFD_PD9                     *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFD_PD10                    *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFD_PD11                    *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCFDL_PC0                    *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFDL_PC1                    *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFDL_PC2                    *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFDL_PC3                    *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFDL_PC4                    *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFDL_RS0                    *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFDL_RS1                    *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFDL_RS2                    *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFDL_INVL                   *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFDH_PD0                    *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFDH_PD1                    *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFDH_PD2                    *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFDH_PD3                    *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFDH_PD4                    *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFDH_PD5                    *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFDH_PD6                    *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFDH_PD7                    *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFDH_PD8                    *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFDH_PD9                    *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFDH_PD10                   *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFDH_PD11                   *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCIS_P1A0                    *((volatile unsigned int*)(0x424E4400UL))
+#define bFM3_ADC2_PCIS_P1A1                    *((volatile unsigned int*)(0x424E4404UL))
+#define bFM3_ADC2_PCIS_P1A2                    *((volatile unsigned int*)(0x424E4408UL))
+#define bFM3_ADC2_PCIS_P2A0                    *((volatile unsigned int*)(0x424E440CUL))
+#define bFM3_ADC2_PCIS_P2A1                    *((volatile unsigned int*)(0x424E4410UL))
+#define bFM3_ADC2_PCIS_P2A2                    *((volatile unsigned int*)(0x424E4414UL))
+#define bFM3_ADC2_PCIS_P2A3                    *((volatile unsigned int*)(0x424E4418UL))
+#define bFM3_ADC2_PCIS_P2A4                    *((volatile unsigned int*)(0x424E441CUL))
+#define bFM3_ADC2_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E4480UL))
+#define bFM3_ADC2_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E4484UL))
+#define bFM3_ADC2_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E4488UL))
+#define bFM3_ADC2_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E448CUL))
+#define bFM3_ADC2_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E4490UL))
+#define bFM3_ADC2_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E4494UL))
+#define bFM3_ADC2_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E4498UL))
+#define bFM3_ADC2_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E449CUL))
+#define bFM3_ADC2_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E44D8UL))
+#define bFM3_ADC2_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E44DCUL))
+#define bFM3_ADC2_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E44E0UL))
+#define bFM3_ADC2_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E44E4UL))
+#define bFM3_ADC2_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E44E8UL))
+#define bFM3_ADC2_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E44ECUL))
+#define bFM3_ADC2_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E44F0UL))
+#define bFM3_ADC2_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E44F4UL))
+#define bFM3_ADC2_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E44F8UL))
+#define bFM3_ADC2_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E44FCUL))
+#define bFM3_ADC2_ADSS23_TS16                  *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS23_TS17                  *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS23_TS18                  *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS23_TS19                  *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS23_TS20                  *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS23_TS21                  *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS23_TS22                  *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS23_TS23                  *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS23_TS24                  *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS23_TS25                  *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS23_TS26                  *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS23_TS27                  *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS23_TS28                  *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS23_TS29                  *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS23_TS30                  *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS23_TS31                  *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS2_TS16                   *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS2_TS17                   *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS2_TS18                   *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS2_TS19                   *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS2_TS20                   *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS2_TS21                   *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS2_TS22                   *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS2_TS23                   *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS3_TS24                   *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS3_TS25                   *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS3_TS26                   *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS3_TS27                   *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS3_TS28                   *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS3_TS29                   *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS3_TS30                   *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS3_TS31                   *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS01_TS0                   *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS01_TS1                   *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS01_TS2                   *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS01_TS3                   *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS01_TS4                   *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS01_TS5                   *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS01_TS6                   *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS01_TS7                   *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS01_TS8                   *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS01_TS9                   *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS01_TS10                  *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS01_TS11                  *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS01_TS12                  *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS01_TS13                  *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS01_TS14                  *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS01_TS15                  *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADSS0_TS0                    *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS0_TS1                    *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS0_TS2                    *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS0_TS3                    *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS0_TS4                    *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS0_TS5                    *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS0_TS6                    *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS0_TS7                    *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS1_TS8                    *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS1_TS9                    *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS1_TS10                   *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS1_TS11                   *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS1_TS12                   *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS1_TS13                   *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS1_TS14                   *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS1_TS15                   *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADST01_ST10                  *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST01_ST11                  *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST01_ST12                  *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST01_ST13                  *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST01_ST14                  *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST01_STX10                 *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST01_STX11                 *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST01_STX12                 *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST01_ST00                  *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST01_ST01                  *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST01_ST02                  *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST01_ST03                  *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST01_ST04                  *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST01_STX00                 *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST01_STX01                 *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST01_STX02                 *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADST1_ST10                   *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST1_ST11                   *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST1_ST12                   *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST1_ST13                   *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST1_ST14                   *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST1_STX10                  *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST1_STX11                  *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST1_STX12                  *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST0_ST00                   *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST0_ST01                   *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST0_ST02                   *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST0_ST03                   *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST0_ST04                   *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST0_STX00                  *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST0_STX01                  *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST0_STX02                  *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADCT_CT0                     *((volatile unsigned int*)(0x424E4680UL))
+#define bFM3_ADC2_ADCT_CT1                     *((volatile unsigned int*)(0x424E4684UL))
+#define bFM3_ADC2_ADCT_CT2                     *((volatile unsigned int*)(0x424E4688UL))
+#define bFM3_ADC2_ADCT_CT3                     *((volatile unsigned int*)(0x424E468CUL))
+#define bFM3_ADC2_ADCT_CT4                     *((volatile unsigned int*)(0x424E4690UL))
+#define bFM3_ADC2_ADCT_CT5                     *((volatile unsigned int*)(0x424E4694UL))
+#define bFM3_ADC2_ADCT_CT6                     *((volatile unsigned int*)(0x424E4698UL))
+#define bFM3_ADC2_ADCT_CT7                     *((volatile unsigned int*)(0x424E469CUL))
+#define bFM3_ADC2_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E4700UL))
+#define bFM3_ADC2_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E4704UL))
+#define bFM3_ADC2_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E4708UL))
+#define bFM3_ADC2_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E470CUL))
+#define bFM3_ADC2_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E4720UL))
+#define bFM3_ADC2_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E4724UL))
+#define bFM3_ADC2_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E4728UL))
+#define bFM3_ADC2_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E472CUL))
+#define bFM3_ADC2_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E4780UL))
+#define bFM3_ADC2_ADCEN_READY                  *((volatile unsigned int*)(0x424E4784UL))
+#define bFM3_ADC2_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E4790UL))
+#define bFM3_ADC2_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E4794UL))
+
+/* CR trimming registers */
+#define bFM3_CRTRIM_MCR_PSR_CSR0               *((volatile unsigned int*)(0x425C0000UL))
+#define bFM3_CRTRIM_MCR_PSR_CSR1               *((volatile unsigned int*)(0x425C0004UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD0              *((volatile unsigned int*)(0x425C0080UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD1              *((volatile unsigned int*)(0x425C0084UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD2              *((volatile unsigned int*)(0x425C0088UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD3              *((volatile unsigned int*)(0x425C008CUL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD4              *((volatile unsigned int*)(0x425C0090UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD5              *((volatile unsigned int*)(0x425C0094UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD6              *((volatile unsigned int*)(0x425C0098UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD7              *((volatile unsigned int*)(0x425C009CUL))
+
+/* External interrupt registers */
+#define bFM3_EXTI_ENIR_EN0                     *((volatile unsigned int*)(0x42600000UL))
+#define bFM3_EXTI_ENIR_EN1                     *((volatile unsigned int*)(0x42600004UL))
+#define bFM3_EXTI_ENIR_EN2                     *((volatile unsigned int*)(0x42600008UL))
+#define bFM3_EXTI_ENIR_EN3                     *((volatile unsigned int*)(0x4260000CUL))
+#define bFM3_EXTI_ENIR_EN4                     *((volatile unsigned int*)(0x42600010UL))
+#define bFM3_EXTI_ENIR_EN5                     *((volatile unsigned int*)(0x42600014UL))
+#define bFM3_EXTI_ENIR_EN6                     *((volatile unsigned int*)(0x42600018UL))
+#define bFM3_EXTI_ENIR_EN7                     *((volatile unsigned int*)(0x4260001CUL))
+#define bFM3_EXTI_ENIR_EN8                     *((volatile unsigned int*)(0x42600020UL))
+#define bFM3_EXTI_ENIR_EN9                     *((volatile unsigned int*)(0x42600024UL))
+#define bFM3_EXTI_ENIR_EN10                    *((volatile unsigned int*)(0x42600028UL))
+#define bFM3_EXTI_ENIR_EN11                    *((volatile unsigned int*)(0x4260002CUL))
+#define bFM3_EXTI_ENIR_EN12                    *((volatile unsigned int*)(0x42600030UL))
+#define bFM3_EXTI_ENIR_EN13                    *((volatile unsigned int*)(0x42600034UL))
+#define bFM3_EXTI_ENIR_EN14                    *((volatile unsigned int*)(0x42600038UL))
+#define bFM3_EXTI_ENIR_EN15                    *((volatile unsigned int*)(0x4260003CUL))
+#define bFM3_EXTI_ENIR_EN16                    *((volatile unsigned int*)(0x42600040UL))
+#define bFM3_EXTI_ENIR_EN17                    *((volatile unsigned int*)(0x42600044UL))
+#define bFM3_EXTI_ENIR_EN18                    *((volatile unsigned int*)(0x42600048UL))
+#define bFM3_EXTI_ENIR_EN19                    *((volatile unsigned int*)(0x4260004CUL))
+#define bFM3_EXTI_ENIR_EN20                    *((volatile unsigned int*)(0x42600050UL))
+#define bFM3_EXTI_ENIR_EN21                    *((volatile unsigned int*)(0x42600054UL))
+#define bFM3_EXTI_ENIR_EN22                    *((volatile unsigned int*)(0x42600058UL))
+#define bFM3_EXTI_ENIR_EN23                    *((volatile unsigned int*)(0x4260005CUL))
+#define bFM3_EXTI_ENIR_EN24                    *((volatile unsigned int*)(0x42600060UL))
+#define bFM3_EXTI_ENIR_EN25                    *((volatile unsigned int*)(0x42600064UL))
+#define bFM3_EXTI_ENIR_EN26                    *((volatile unsigned int*)(0x42600068UL))
+#define bFM3_EXTI_ENIR_EN27                    *((volatile unsigned int*)(0x4260006CUL))
+#define bFM3_EXTI_ENIR_EN28                    *((volatile unsigned int*)(0x42600070UL))
+#define bFM3_EXTI_ENIR_EN29                    *((volatile unsigned int*)(0x42600074UL))
+#define bFM3_EXTI_ENIR_EN30                    *((volatile unsigned int*)(0x42600078UL))
+#define bFM3_EXTI_ENIR_EN31                    *((volatile unsigned int*)(0x4260007CUL))
+#define bFM3_EXTI_EIRR_ER0                     *((volatile unsigned int*)(0x42600080UL))
+#define bFM3_EXTI_EIRR_ER1                     *((volatile unsigned int*)(0x42600084UL))
+#define bFM3_EXTI_EIRR_ER2                     *((volatile unsigned int*)(0x42600088UL))
+#define bFM3_EXTI_EIRR_ER3                     *((volatile unsigned int*)(0x4260008CUL))
+#define bFM3_EXTI_EIRR_ER4                     *((volatile unsigned int*)(0x42600090UL))
+#define bFM3_EXTI_EIRR_ER5                     *((volatile unsigned int*)(0x42600094UL))
+#define bFM3_EXTI_EIRR_ER6                     *((volatile unsigned int*)(0x42600098UL))
+#define bFM3_EXTI_EIRR_ER7                     *((volatile unsigned int*)(0x4260009CUL))
+#define bFM3_EXTI_EIRR_ER8                     *((volatile unsigned int*)(0x426000A0UL))
+#define bFM3_EXTI_EIRR_ER9                     *((volatile unsigned int*)(0x426000A4UL))
+#define bFM3_EXTI_EIRR_ER10                    *((volatile unsigned int*)(0x426000A8UL))
+#define bFM3_EXTI_EIRR_ER11                    *((volatile unsigned int*)(0x426000ACUL))
+#define bFM3_EXTI_EIRR_ER12                    *((volatile unsigned int*)(0x426000B0UL))
+#define bFM3_EXTI_EIRR_ER13                    *((volatile unsigned int*)(0x426000B4UL))
+#define bFM3_EXTI_EIRR_ER14                    *((volatile unsigned int*)(0x426000B8UL))
+#define bFM3_EXTI_EIRR_ER15                    *((volatile unsigned int*)(0x426000BCUL))
+#define bFM3_EXTI_EIRR_ER16                    *((volatile unsigned int*)(0x426000C0UL))
+#define bFM3_EXTI_EIRR_ER17                    *((volatile unsigned int*)(0x426000C4UL))
+#define bFM3_EXTI_EIRR_ER18                    *((volatile unsigned int*)(0x426000C8UL))
+#define bFM3_EXTI_EIRR_ER19                    *((volatile unsigned int*)(0x426000CCUL))
+#define bFM3_EXTI_EIRR_ER20                    *((volatile unsigned int*)(0x426000D0UL))
+#define bFM3_EXTI_EIRR_ER21                    *((volatile unsigned int*)(0x426000D4UL))
+#define bFM3_EXTI_EIRR_ER22                    *((volatile unsigned int*)(0x426000D8UL))
+#define bFM3_EXTI_EIRR_ER23                    *((volatile unsigned int*)(0x426000DCUL))
+#define bFM3_EXTI_EIRR_ER24                    *((volatile unsigned int*)(0x426000E0UL))
+#define bFM3_EXTI_EIRR_ER25                    *((volatile unsigned int*)(0x426000E4UL))
+#define bFM3_EXTI_EIRR_ER26                    *((volatile unsigned int*)(0x426000E8UL))
+#define bFM3_EXTI_EIRR_ER27                    *((volatile unsigned int*)(0x426000ECUL))
+#define bFM3_EXTI_EIRR_ER28                    *((volatile unsigned int*)(0x426000F0UL))
+#define bFM3_EXTI_EIRR_ER29                    *((volatile unsigned int*)(0x426000F4UL))
+#define bFM3_EXTI_EIRR_ER30                    *((volatile unsigned int*)(0x426000F8UL))
+#define bFM3_EXTI_EIRR_ER31                    *((volatile unsigned int*)(0x426000FCUL))
+#define bFM3_EXTI_EICL_ECL0                    *((volatile unsigned int*)(0x42600100UL))
+#define bFM3_EXTI_EICL_ECL1                    *((volatile unsigned int*)(0x42600104UL))
+#define bFM3_EXTI_EICL_ECL2                    *((volatile unsigned int*)(0x42600108UL))
+#define bFM3_EXTI_EICL_ECL3                    *((volatile unsigned int*)(0x4260010CUL))
+#define bFM3_EXTI_EICL_ECL4                    *((volatile unsigned int*)(0x42600110UL))
+#define bFM3_EXTI_EICL_ECL5                    *((volatile unsigned int*)(0x42600114UL))
+#define bFM3_EXTI_EICL_ECL6                    *((volatile unsigned int*)(0x42600118UL))
+#define bFM3_EXTI_EICL_ECL7                    *((volatile unsigned int*)(0x4260011CUL))
+#define bFM3_EXTI_EICL_ECL8                    *((volatile unsigned int*)(0x42600120UL))
+#define bFM3_EXTI_EICL_ECL9                    *((volatile unsigned int*)(0x42600124UL))
+#define bFM3_EXTI_EICL_ECL10                   *((volatile unsigned int*)(0x42600128UL))
+#define bFM3_EXTI_EICL_ECL11                   *((volatile unsigned int*)(0x4260012CUL))
+#define bFM3_EXTI_EICL_ECL12                   *((volatile unsigned int*)(0x42600130UL))
+#define bFM3_EXTI_EICL_ECL13                   *((volatile unsigned int*)(0x42600134UL))
+#define bFM3_EXTI_EICL_ECL14                   *((volatile unsigned int*)(0x42600138UL))
+#define bFM3_EXTI_EICL_ECL15                   *((volatile unsigned int*)(0x4260013CUL))
+#define bFM3_EXTI_EICL_ECL16                   *((volatile unsigned int*)(0x42600140UL))
+#define bFM3_EXTI_EICL_ECL17                   *((volatile unsigned int*)(0x42600144UL))
+#define bFM3_EXTI_EICL_ECL18                   *((volatile unsigned int*)(0x42600148UL))
+#define bFM3_EXTI_EICL_ECL19                   *((volatile unsigned int*)(0x4260014CUL))
+#define bFM3_EXTI_EICL_ECL20                   *((volatile unsigned int*)(0x42600150UL))
+#define bFM3_EXTI_EICL_ECL21                   *((volatile unsigned int*)(0x42600154UL))
+#define bFM3_EXTI_EICL_ECL22                   *((volatile unsigned int*)(0x42600158UL))
+#define bFM3_EXTI_EICL_ECL23                   *((volatile unsigned int*)(0x4260015CUL))
+#define bFM3_EXTI_EICL_ECL24                   *((volatile unsigned int*)(0x42600160UL))
+#define bFM3_EXTI_EICL_ECL25                   *((volatile unsigned int*)(0x42600164UL))
+#define bFM3_EXTI_EICL_ECL26                   *((volatile unsigned int*)(0x42600168UL))
+#define bFM3_EXTI_EICL_ECL27                   *((volatile unsigned int*)(0x4260016CUL))
+#define bFM3_EXTI_EICL_ECL28                   *((volatile unsigned int*)(0x42600170UL))
+#define bFM3_EXTI_EICL_ECL29                   *((volatile unsigned int*)(0x42600174UL))
+#define bFM3_EXTI_EICL_ECL30                   *((volatile unsigned int*)(0x42600178UL))
+#define bFM3_EXTI_EICL_ECL31                   *((volatile unsigned int*)(0x4260017CUL))
+#define bFM3_EXTI_ELVR_LA0                     *((volatile unsigned int*)(0x42600180UL))
+#define bFM3_EXTI_ELVR_LB0                     *((volatile unsigned int*)(0x42600184UL))
+#define bFM3_EXTI_ELVR_LA1                     *((volatile unsigned int*)(0x42600188UL))
+#define bFM3_EXTI_ELVR_LB1                     *((volatile unsigned int*)(0x4260018CUL))
+#define bFM3_EXTI_ELVR_LA2                     *((volatile unsigned int*)(0x42600190UL))
+#define bFM3_EXTI_ELVR_LB2                     *((volatile unsigned int*)(0x42600194UL))
+#define bFM3_EXTI_ELVR_LA3                     *((volatile unsigned int*)(0x42600198UL))
+#define bFM3_EXTI_ELVR_LB3                     *((volatile unsigned int*)(0x4260019CUL))
+#define bFM3_EXTI_ELVR_LA4                     *((volatile unsigned int*)(0x426001A0UL))
+#define bFM3_EXTI_ELVR_LB4                     *((volatile unsigned int*)(0x426001A4UL))
+#define bFM3_EXTI_ELVR_LA5                     *((volatile unsigned int*)(0x426001A8UL))
+#define bFM3_EXTI_ELVR_LB5                     *((volatile unsigned int*)(0x426001ACUL))
+#define bFM3_EXTI_ELVR_LA6                     *((volatile unsigned int*)(0x426001B0UL))
+#define bFM3_EXTI_ELVR_LB6                     *((volatile unsigned int*)(0x426001B4UL))
+#define bFM3_EXTI_ELVR_LA7                     *((volatile unsigned int*)(0x426001B8UL))
+#define bFM3_EXTI_ELVR_LB7                     *((volatile unsigned int*)(0x426001BCUL))
+#define bFM3_EXTI_ELVR_LA8                     *((volatile unsigned int*)(0x426001C0UL))
+#define bFM3_EXTI_ELVR_LB8                     *((volatile unsigned int*)(0x426001C4UL))
+#define bFM3_EXTI_ELVR_LA9                     *((volatile unsigned int*)(0x426001C8UL))
+#define bFM3_EXTI_ELVR_LB9                     *((volatile unsigned int*)(0x426001CCUL))
+#define bFM3_EXTI_ELVR_LA10                    *((volatile unsigned int*)(0x426001D0UL))
+#define bFM3_EXTI_ELVR_LB10                    *((volatile unsigned int*)(0x426001D4UL))
+#define bFM3_EXTI_ELVR_LA11                    *((volatile unsigned int*)(0x426001D8UL))
+#define bFM3_EXTI_ELVR_LB11                    *((volatile unsigned int*)(0x426001DCUL))
+#define bFM3_EXTI_ELVR_LA12                    *((volatile unsigned int*)(0x426001E0UL))
+#define bFM3_EXTI_ELVR_LB12                    *((volatile unsigned int*)(0x426001E4UL))
+#define bFM3_EXTI_ELVR_LA13                    *((volatile unsigned int*)(0x426001E8UL))
+#define bFM3_EXTI_ELVR_LB13                    *((volatile unsigned int*)(0x426001ECUL))
+#define bFM3_EXTI_ELVR_LA14                    *((volatile unsigned int*)(0x426001F0UL))
+#define bFM3_EXTI_ELVR_LB14                    *((volatile unsigned int*)(0x426001F4UL))
+#define bFM3_EXTI_ELVR_LA15                    *((volatile unsigned int*)(0x426001F8UL))
+#define bFM3_EXTI_ELVR_LB15                    *((volatile unsigned int*)(0x426001FCUL))
+#define bFM3_EXTI_ELVR_LA16                    *((volatile unsigned int*)(0x42600200UL))
+#define bFM3_EXTI_ELVR_LB16                    *((volatile unsigned int*)(0x42600204UL))
+#define bFM3_EXTI_ELVR_LA17                    *((volatile unsigned int*)(0x42600208UL))
+#define bFM3_EXTI_ELVR_LB17                    *((volatile unsigned int*)(0x4260020CUL))
+#define bFM3_EXTI_ELVR_LA18                    *((volatile unsigned int*)(0x42600210UL))
+#define bFM3_EXTI_ELVR_LB18                    *((volatile unsigned int*)(0x42600214UL))
+#define bFM3_EXTI_ELVR_LA19                    *((volatile unsigned int*)(0x42600218UL))
+#define bFM3_EXTI_ELVR_LB19                    *((volatile unsigned int*)(0x4260021CUL))
+#define bFM3_EXTI_ELVR_LA20                    *((volatile unsigned int*)(0x42600220UL))
+#define bFM3_EXTI_ELVR_LB20                    *((volatile unsigned int*)(0x42600224UL))
+#define bFM3_EXTI_ELVR_LA21                    *((volatile unsigned int*)(0x42600228UL))
+#define bFM3_EXTI_ELVR_LB21                    *((volatile unsigned int*)(0x4260022CUL))
+#define bFM3_EXTI_ELVR_LA22                    *((volatile unsigned int*)(0x42600230UL))
+#define bFM3_EXTI_ELVR_LB22                    *((volatile unsigned int*)(0x42600234UL))
+#define bFM3_EXTI_ELVR_LA23                    *((volatile unsigned int*)(0x42600238UL))
+#define bFM3_EXTI_ELVR_LB23                    *((volatile unsigned int*)(0x4260023CUL))
+#define bFM3_EXTI_ELVR_LA24                    *((volatile unsigned int*)(0x42600240UL))
+#define bFM3_EXTI_ELVR_LB24                    *((volatile unsigned int*)(0x42600244UL))
+#define bFM3_EXTI_ELVR_LA25                    *((volatile unsigned int*)(0x42600248UL))
+#define bFM3_EXTI_ELVR_LB25                    *((volatile unsigned int*)(0x4260024CUL))
+#define bFM3_EXTI_ELVR_LA26                    *((volatile unsigned int*)(0x42600250UL))
+#define bFM3_EXTI_ELVR_LB26                    *((volatile unsigned int*)(0x42600254UL))
+#define bFM3_EXTI_ELVR_LA27                    *((volatile unsigned int*)(0x42600258UL))
+#define bFM3_EXTI_ELVR_LB27                    *((volatile unsigned int*)(0x4260025CUL))
+#define bFM3_EXTI_ELVR_LA28                    *((volatile unsigned int*)(0x42600260UL))
+#define bFM3_EXTI_ELVR_LB28                    *((volatile unsigned int*)(0x42600264UL))
+#define bFM3_EXTI_ELVR_LA29                    *((volatile unsigned int*)(0x42600268UL))
+#define bFM3_EXTI_ELVR_LB29                    *((volatile unsigned int*)(0x4260026CUL))
+#define bFM3_EXTI_ELVR_LA30                    *((volatile unsigned int*)(0x42600270UL))
+#define bFM3_EXTI_ELVR_LB30                    *((volatile unsigned int*)(0x42600274UL))
+#define bFM3_EXTI_ELVR_LA31                    *((volatile unsigned int*)(0x42600278UL))
+#define bFM3_EXTI_ELVR_LB31                    *((volatile unsigned int*)(0x4260027CUL))
+#define bFM3_EXTI_NMIRR_NR0                    *((volatile unsigned int*)(0x42600280UL))
+#define bFM3_EXTI_NMICL_NCL0                   *((volatile unsigned int*)(0x42600300UL))
+
+/* Interrupt request read registers */
+#define bFM3_INTREQ_DRQSEL_DRQSEL0             *((volatile unsigned int*)(0x42620000UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL1             *((volatile unsigned int*)(0x42620004UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL2             *((volatile unsigned int*)(0x42620008UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL3             *((volatile unsigned int*)(0x4262000CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL4             *((volatile unsigned int*)(0x42620010UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL5             *((volatile unsigned int*)(0x42620014UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL6             *((volatile unsigned int*)(0x42620018UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL7             *((volatile unsigned int*)(0x4262001CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL8             *((volatile unsigned int*)(0x42620020UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL9             *((volatile unsigned int*)(0x42620024UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL10            *((volatile unsigned int*)(0x42620028UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL11            *((volatile unsigned int*)(0x4262002CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL12            *((volatile unsigned int*)(0x42620030UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL13            *((volatile unsigned int*)(0x42620034UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL14            *((volatile unsigned int*)(0x42620038UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL15            *((volatile unsigned int*)(0x4262003CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL16            *((volatile unsigned int*)(0x42620040UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL17            *((volatile unsigned int*)(0x42620044UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL18            *((volatile unsigned int*)(0x42620048UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL19            *((volatile unsigned int*)(0x4262004CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL20            *((volatile unsigned int*)(0x42620050UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL21            *((volatile unsigned int*)(0x42620054UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL22            *((volatile unsigned int*)(0x42620058UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL23            *((volatile unsigned int*)(0x4262005CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL24            *((volatile unsigned int*)(0x42620060UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL25            *((volatile unsigned int*)(0x42620064UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL26            *((volatile unsigned int*)(0x42620068UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL27            *((volatile unsigned int*)(0x4262006CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL28            *((volatile unsigned int*)(0x42620070UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL29            *((volatile unsigned int*)(0x42620074UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL30            *((volatile unsigned int*)(0x42620078UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL31            *((volatile unsigned int*)(0x4262007CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS0             *((volatile unsigned char*)(0x42620160UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS1             *((volatile unsigned char*)(0x42620164UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS2             *((volatile unsigned char*)(0x42620168UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS3             *((volatile unsigned char*)(0x4262016CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS4             *((volatile unsigned char*)(0x42620170UL))
+#define bFM3_INTREQ_EXC02MON_NMI               *((volatile unsigned int*)(0x42620200UL))
+#define bFM3_INTREQ_EXC02MON_HWINT             *((volatile unsigned int*)(0x42620204UL))
+#define bFM3_INTREQ_IRQ00MON_FCSINT            *((volatile unsigned int*)(0x42620280UL))
+#define bFM3_INTREQ_IRQ01MON_SWWDTINT          *((volatile unsigned int*)(0x42620300UL))
+#define bFM3_INTREQ_IRQ02MON_LVDINT            *((volatile unsigned int*)(0x42620380UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT0         *((volatile unsigned int*)(0x42620400UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT1         *((volatile unsigned int*)(0x42620404UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT2         *((volatile unsigned int*)(0x42620408UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT3         *((volatile unsigned int*)(0x4262040CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT0         *((volatile unsigned int*)(0x42620410UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT1         *((volatile unsigned int*)(0x42620414UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT2         *((volatile unsigned int*)(0x42620418UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT3         *((volatile unsigned int*)(0x4262041CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT0         *((volatile unsigned int*)(0x42620420UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT1         *((volatile unsigned int*)(0x42620424UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT2         *((volatile unsigned int*)(0x42620428UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT3         *((volatile unsigned int*)(0x4262042CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT0           *((volatile unsigned int*)(0x42620480UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT1           *((volatile unsigned int*)(0x42620484UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT2           *((volatile unsigned int*)(0x42620488UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT3           *((volatile unsigned int*)(0x4262048CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT4           *((volatile unsigned int*)(0x42620490UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT5           *((volatile unsigned int*)(0x42620494UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT6           *((volatile unsigned int*)(0x42620498UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT7           *((volatile unsigned int*)(0x4262049CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT0           *((volatile unsigned int*)(0x42620500UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT1           *((volatile unsigned int*)(0x42620504UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT2           *((volatile unsigned int*)(0x42620508UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT3           *((volatile unsigned int*)(0x4262050CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT4           *((volatile unsigned int*)(0x42620510UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT5           *((volatile unsigned int*)(0x42620514UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT6           *((volatile unsigned int*)(0x42620518UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT7           *((volatile unsigned int*)(0x4262051CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT8           *((volatile unsigned int*)(0x42620520UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT9           *((volatile unsigned int*)(0x42620524UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT10          *((volatile unsigned int*)(0x42620528UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT11          *((volatile unsigned int*)(0x4262052CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT12          *((volatile unsigned int*)(0x42620530UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT13          *((volatile unsigned int*)(0x42620534UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT14          *((volatile unsigned int*)(0x42620538UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT15          *((volatile unsigned int*)(0x4262053CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT16          *((volatile unsigned int*)(0x42620540UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT17          *((volatile unsigned int*)(0x42620544UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT18          *((volatile unsigned int*)(0x42620548UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT19          *((volatile unsigned int*)(0x4262054CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT20          *((volatile unsigned int*)(0x42620550UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT21          *((volatile unsigned int*)(0x42620554UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT22          *((volatile unsigned int*)(0x42620558UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT23          *((volatile unsigned int*)(0x4262055CUL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT1           *((volatile unsigned int*)(0x42620580UL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT2           *((volatile unsigned int*)(0x42620584UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT0          *((volatile unsigned int*)(0x42620588UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT1          *((volatile unsigned int*)(0x4262058CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT2          *((volatile unsigned int*)(0x42620590UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT3          *((volatile unsigned int*)(0x42620594UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT4          *((volatile unsigned int*)(0x42620598UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT5          *((volatile unsigned int*)(0x4262059CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT0          *((volatile unsigned int*)(0x426205A0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT1          *((volatile unsigned int*)(0x426205A4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT2          *((volatile unsigned int*)(0x426205A8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT3          *((volatile unsigned int*)(0x426205ACUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT4          *((volatile unsigned int*)(0x426205B0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT5          *((volatile unsigned int*)(0x426205B4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT0          *((volatile unsigned int*)(0x426205B8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT1          *((volatile unsigned int*)(0x426205BCUL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT2          *((volatile unsigned int*)(0x426205C0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT3          *((volatile unsigned int*)(0x426205C4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT4          *((volatile unsigned int*)(0x426205C8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT5          *((volatile unsigned int*)(0x426205CCUL))
+#define bFM3_INTREQ_IRQ07MON_FMSINT            *((volatile unsigned int*)(0x42620600UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT0           *((volatile unsigned int*)(0x42620680UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT1           *((volatile unsigned int*)(0x42620684UL))
+#define bFM3_INTREQ_IRQ09MON_FMSINT            *((volatile unsigned int*)(0x42620700UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT0           *((volatile unsigned int*)(0x42620780UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT1           *((volatile unsigned int*)(0x42620784UL))
+#define bFM3_INTREQ_IRQ11MON_FMSINT            *((volatile unsigned int*)(0x42620800UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT0           *((volatile unsigned int*)(0x42620880UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT1           *((volatile unsigned int*)(0x42620884UL))
+#define bFM3_INTREQ_IRQ13MON_FMSINT            *((volatile unsigned int*)(0x42620900UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT0           *((volatile unsigned int*)(0x42620980UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT1           *((volatile unsigned int*)(0x42620984UL))
+#define bFM3_INTREQ_IRQ15MON_FMSINT            *((volatile unsigned int*)(0x42620A00UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT0           *((volatile unsigned int*)(0x42620A80UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT1           *((volatile unsigned int*)(0x42620A84UL))
+#define bFM3_INTREQ_IRQ17MON_FMSINT            *((volatile unsigned int*)(0x42620B00UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT0           *((volatile unsigned int*)(0x42620B80UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT1           *((volatile unsigned int*)(0x42620B84UL))
+#define bFM3_INTREQ_IRQ19MON_FMSINT            *((volatile unsigned int*)(0x42620C00UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT0           *((volatile unsigned int*)(0x42620C80UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT1           *((volatile unsigned int*)(0x42620C84UL))
+#define bFM3_INTREQ_IRQ21MON_FMSINT            *((volatile unsigned int*)(0x42620D00UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT0           *((volatile unsigned int*)(0x42620D80UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT1           *((volatile unsigned int*)(0x42620D84UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT0           *((volatile unsigned int*)(0x42620E00UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT1           *((volatile unsigned int*)(0x42620E04UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT2           *((volatile unsigned int*)(0x42620E08UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT3           *((volatile unsigned int*)(0x42620E0CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT4           *((volatile unsigned int*)(0x42620E10UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT5           *((volatile unsigned int*)(0x42620E14UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT6           *((volatile unsigned int*)(0x42620E18UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT7           *((volatile unsigned int*)(0x42620E1CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT8           *((volatile unsigned int*)(0x42620E20UL))
+#define bFM3_INTREQ_IRQ24MON_MOSCINT           *((volatile unsigned int*)(0x42620E80UL))
+#define bFM3_INTREQ_IRQ24MON_SOSCINT           *((volatile unsigned int*)(0x42620E84UL))
+#define bFM3_INTREQ_IRQ24MON_MPLLINT           *((volatile unsigned int*)(0x42620E88UL))
+#define bFM3_INTREQ_IRQ24MON_UPLLINT           *((volatile unsigned int*)(0x42620E8CUL))
+#define bFM3_INTREQ_IRQ24MON_WCINT             *((volatile unsigned int*)(0x42620E90UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT0           *((volatile unsigned int*)(0x42620F00UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT1           *((volatile unsigned int*)(0x42620F04UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT2           *((volatile unsigned int*)(0x42620F08UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT3           *((volatile unsigned int*)(0x42620F0CUL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT0           *((volatile unsigned int*)(0x42620F80UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT1           *((volatile unsigned int*)(0x42620F84UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT2           *((volatile unsigned int*)(0x42620F88UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT3           *((volatile unsigned int*)(0x42620F8CUL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT0           *((volatile unsigned int*)(0x42621000UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT1           *((volatile unsigned int*)(0x42621004UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT2           *((volatile unsigned int*)(0x42621008UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT3           *((volatile unsigned int*)(0x4262100CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT0          *((volatile unsigned int*)(0x42621080UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT1          *((volatile unsigned int*)(0x42621084UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT2          *((volatile unsigned int*)(0x42621088UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT3          *((volatile unsigned int*)(0x4262108CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT4          *((volatile unsigned int*)(0x42621090UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT5          *((volatile unsigned int*)(0x42621094UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT0          *((volatile unsigned int*)(0x42621098UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT1          *((volatile unsigned int*)(0x4262109CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT2          *((volatile unsigned int*)(0x426210A0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT3          *((volatile unsigned int*)(0x426210A4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT4          *((volatile unsigned int*)(0x426210A8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT5          *((volatile unsigned int*)(0x426210ACUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT0          *((volatile unsigned int*)(0x426210B0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT1          *((volatile unsigned int*)(0x426210B4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT2          *((volatile unsigned int*)(0x426210B8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT3          *((volatile unsigned int*)(0x426210BCUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT4          *((volatile unsigned int*)(0x426210C0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT5          *((volatile unsigned int*)(0x426210C4UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT0          *((volatile unsigned int*)(0x42621100UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT1          *((volatile unsigned int*)(0x42621104UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT2          *((volatile unsigned int*)(0x42621108UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT3          *((volatile unsigned int*)(0x4262110CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT0          *((volatile unsigned int*)(0x42621110UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT1          *((volatile unsigned int*)(0x42621114UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT2          *((volatile unsigned int*)(0x42621118UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT3          *((volatile unsigned int*)(0x4262111CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT0          *((volatile unsigned int*)(0x42621120UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT1          *((volatile unsigned int*)(0x42621124UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT2          *((volatile unsigned int*)(0x42621128UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT3          *((volatile unsigned int*)(0x4262112CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT0          *((volatile unsigned int*)(0x42621180UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT1          *((volatile unsigned int*)(0x42621184UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT2          *((volatile unsigned int*)(0x42621188UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT3          *((volatile unsigned int*)(0x4262118CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT4          *((volatile unsigned int*)(0x42621190UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT5          *((volatile unsigned int*)(0x42621194UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT0          *((volatile unsigned int*)(0x42621198UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT1          *((volatile unsigned int*)(0x4262119CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT2          *((volatile unsigned int*)(0x426211A0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT3          *((volatile unsigned int*)(0x426211A4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT4          *((volatile unsigned int*)(0x426211A8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT5          *((volatile unsigned int*)(0x426211ACUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT0          *((volatile unsigned int*)(0x426211B0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT1          *((volatile unsigned int*)(0x426211B4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT2          *((volatile unsigned int*)(0x426211B8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT3          *((volatile unsigned int*)(0x426211BCUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT4          *((volatile unsigned int*)(0x426211C0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT5          *((volatile unsigned int*)(0x426211C4UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT0            *((volatile unsigned int*)(0x42621200UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT1            *((volatile unsigned int*)(0x42621204UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT2            *((volatile unsigned int*)(0x42621208UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT3            *((volatile unsigned int*)(0x4262120CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT4            *((volatile unsigned int*)(0x42621210UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT5            *((volatile unsigned int*)(0x42621214UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT6            *((volatile unsigned int*)(0x42621218UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT7            *((volatile unsigned int*)(0x4262121CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT8            *((volatile unsigned int*)(0x42621220UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT9            *((volatile unsigned int*)(0x42621224UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT10           *((volatile unsigned int*)(0x42621228UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT11           *((volatile unsigned int*)(0x4262122CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT12           *((volatile unsigned int*)(0x42621230UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT13           *((volatile unsigned int*)(0x42621234UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT14           *((volatile unsigned int*)(0x42621238UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT15           *((volatile unsigned int*)(0x4262123CUL))
+#define bFM3_INTREQ_IRQ32MON_MAC0SBD           *((volatile unsigned int*)(0x42621284UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0PMI           *((volatile unsigned int*)(0x42621288UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0LPI           *((volatile unsigned int*)(0x4262128CUL))
+#define bFM3_INTREQ_IRQ33MON_MAC1SBD           *((volatile unsigned int*)(0x42621304UL))
+#define bFM3_INTREQ_IRQ33MON_MAC1PMI           *((volatile unsigned int*)(0x42621308UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT0          *((volatile unsigned int*)(0x42621380UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT1          *((volatile unsigned int*)(0x42621384UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT2          *((volatile unsigned int*)(0x42621388UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT3          *((volatile unsigned int*)(0x4262138CUL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT4          *((volatile unsigned int*)(0x42621390UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT0          *((volatile unsigned int*)(0x42621400UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT1          *((volatile unsigned int*)(0x42621404UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT2          *((volatile unsigned int*)(0x42621408UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT3          *((volatile unsigned int*)(0x4262140CUL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT4          *((volatile unsigned int*)(0x42621410UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT5          *((volatile unsigned int*)(0x42621414UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT0          *((volatile unsigned int*)(0x42621480UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT1          *((volatile unsigned int*)(0x42621484UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT2          *((volatile unsigned int*)(0x42621488UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT3          *((volatile unsigned int*)(0x4262148CUL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT4          *((volatile unsigned int*)(0x42621490UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT0          *((volatile unsigned int*)(0x42621500UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT1          *((volatile unsigned int*)(0x42621504UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT2          *((volatile unsigned int*)(0x42621508UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT3          *((volatile unsigned int*)(0x4262150CUL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT4          *((volatile unsigned int*)(0x42621510UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT5          *((volatile unsigned int*)(0x42621514UL))
+#define bFM3_INTREQ_IRQ38MON_DMAINT            *((volatile unsigned int*)(0x42621580UL))
+#define bFM3_INTREQ_IRQ39MON_DMAINT            *((volatile unsigned int*)(0x42621600UL))
+#define bFM3_INTREQ_IRQ40MON_DMAINT            *((volatile unsigned int*)(0x42621680UL))
+#define bFM3_INTREQ_IRQ41MON_DMAINT            *((volatile unsigned int*)(0x42621700UL))
+#define bFM3_INTREQ_IRQ42MON_DMAINT            *((volatile unsigned int*)(0x42621780UL))
+#define bFM3_INTREQ_IRQ43MON_DMAINT            *((volatile unsigned int*)(0x42621800UL))
+#define bFM3_INTREQ_IRQ44MON_DMAINT            *((volatile unsigned int*)(0x42621880UL))
+#define bFM3_INTREQ_IRQ45MON_DMAINT            *((volatile unsigned int*)(0x42621900UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT0            *((volatile unsigned int*)(0x42621980UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT1            *((volatile unsigned int*)(0x42621984UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT2            *((volatile unsigned int*)(0x42621988UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT3            *((volatile unsigned int*)(0x4262198CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT4            *((volatile unsigned int*)(0x42621990UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT5            *((volatile unsigned int*)(0x42621994UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT6            *((volatile unsigned int*)(0x42621998UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT7            *((volatile unsigned int*)(0x4262199CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT8            *((volatile unsigned int*)(0x426219A0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT9            *((volatile unsigned int*)(0x426219A4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT10           *((volatile unsigned int*)(0x426219A8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT11           *((volatile unsigned int*)(0x426219ACUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT12           *((volatile unsigned int*)(0x426219B0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT13           *((volatile unsigned int*)(0x426219B4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT14           *((volatile unsigned int*)(0x426219B8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT15           *((volatile unsigned int*)(0x426219BCUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL10           *((volatile unsigned int*)(0x42624000UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL11           *((volatile unsigned int*)(0x42624004UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL12           *((volatile unsigned int*)(0x42624008UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL13           *((volatile unsigned int*)(0x4262400CUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL14           *((volatile unsigned int*)(0x42624010UL))
+#define bFM3_INTREQ_DQESEL_ESEL100             *((volatile unsigned int*)(0x42624080UL))
+#define bFM3_INTREQ_DQESEL_ESEL101             *((volatile unsigned int*)(0x42624084UL))
+#define bFM3_INTREQ_DQESEL_ESEL102             *((volatile unsigned int*)(0x42624088UL))
+#define bFM3_INTREQ_DQESEL_ESEL103             *((volatile unsigned int*)(0x4262408CUL))
+#define bFM3_INTREQ_DQESEL_ESEL110             *((volatile unsigned int*)(0x42624090UL))
+#define bFM3_INTREQ_DQESEL_ESEL111             *((volatile unsigned int*)(0x42624094UL))
+#define bFM3_INTREQ_DQESEL_ESEL112             *((volatile unsigned int*)(0x42624098UL))
+#define bFM3_INTREQ_DQESEL_ESEL113             *((volatile unsigned int*)(0x4262409CUL))
+#define bFM3_INTREQ_DQESEL_ESEL240             *((volatile unsigned int*)(0x426240A0UL))
+#define bFM3_INTREQ_DQESEL_ESEL241             *((volatile unsigned int*)(0x426240A4UL))
+#define bFM3_INTREQ_DQESEL_ESEL242             *((volatile unsigned int*)(0x426240A8UL))
+#define bFM3_INTREQ_DQESEL_ESEL243             *((volatile unsigned int*)(0x426240ACUL))
+#define bFM3_INTREQ_DQESEL_ESEL250             *((volatile unsigned int*)(0x426240B0UL))
+#define bFM3_INTREQ_DQESEL_ESEL251             *((volatile unsigned int*)(0x426240B4UL))
+#define bFM3_INTREQ_DQESEL_ESEL252             *((volatile unsigned int*)(0x426240B8UL))
+#define bFM3_INTREQ_DQESEL_ESEL253             *((volatile unsigned int*)(0x426240BCUL))
+#define bFM3_INTREQ_DQESEL_ESEL260             *((volatile unsigned int*)(0x426240C0UL))
+#define bFM3_INTREQ_DQESEL_ESEL261             *((volatile unsigned int*)(0x426240C4UL))
+#define bFM3_INTREQ_DQESEL_ESEL262             *((volatile unsigned int*)(0x426240C8UL))
+#define bFM3_INTREQ_DQESEL_ESEL263             *((volatile unsigned int*)(0x426240CCUL))
+#define bFM3_INTREQ_DQESEL_ESEL270             *((volatile unsigned int*)(0x426240D0UL))
+#define bFM3_INTREQ_DQESEL_ESEL271             *((volatile unsigned int*)(0x426240D4UL))
+#define bFM3_INTREQ_DQESEL_ESEL272             *((volatile unsigned int*)(0x426240D8UL))
+#define bFM3_INTREQ_DQESEL_ESEL273             *((volatile unsigned int*)(0x426240DCUL))
+#define bFM3_INTREQ_DQESEL_ESEL300             *((volatile unsigned int*)(0x426240E0UL))
+#define bFM3_INTREQ_DQESEL_ESEL301             *((volatile unsigned int*)(0x426240E4UL))
+#define bFM3_INTREQ_DQESEL_ESEL302             *((volatile unsigned int*)(0x426240E8UL))
+#define bFM3_INTREQ_DQESEL_ESEL303             *((volatile unsigned int*)(0x426240ECUL))
+#define bFM3_INTREQ_DQESEL_ESEL310             *((volatile unsigned int*)(0x426240F0UL))
+#define bFM3_INTREQ_DQESEL_ESEL311             *((volatile unsigned int*)(0x426240F4UL))
+#define bFM3_INTREQ_DQESEL_ESEL312             *((volatile unsigned int*)(0x426240F8UL))
+#define bFM3_INTREQ_DQESEL_ESEL313             *((volatile unsigned int*)(0x426240FCUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS10           *((volatile unsigned char*)(0x426241E0UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS11           *((volatile unsigned char*)(0x426241E4UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS12           *((volatile unsigned char*)(0x426241E8UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS13           *((volatile unsigned char*)(0x426241ECUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS14           *((volatile unsigned char*)(0x426241F0UL))
+
+/* General purpose I/O registers */
+#define bFM3_GPIO_PFR0_P0                      *((volatile unsigned int*)(0x42660000UL))
+#define bFM3_GPIO_PFR0_P1                      *((volatile unsigned int*)(0x42660004UL))
+#define bFM3_GPIO_PFR0_P2                      *((volatile unsigned int*)(0x42660008UL))
+#define bFM3_GPIO_PFR0_P3                      *((volatile unsigned int*)(0x4266000CUL))
+#define bFM3_GPIO_PFR0_P4                      *((volatile unsigned int*)(0x42660010UL))
+#define bFM3_GPIO_PFR0_P5                      *((volatile unsigned int*)(0x42660014UL))
+#define bFM3_GPIO_PFR0_P6                      *((volatile unsigned int*)(0x42660018UL))
+#define bFM3_GPIO_PFR0_P7                      *((volatile unsigned int*)(0x4266001CUL))
+#define bFM3_GPIO_PFR0_P8                      *((volatile unsigned int*)(0x42660020UL))
+#define bFM3_GPIO_PFR0_P9                      *((volatile unsigned int*)(0x42660024UL))
+#define bFM3_GPIO_PFR1_P0                      *((volatile unsigned int*)(0x42660080UL))
+#define bFM3_GPIO_PFR1_P1                      *((volatile unsigned int*)(0x42660084UL))
+#define bFM3_GPIO_PFR1_P2                      *((volatile unsigned int*)(0x42660088UL))
+#define bFM3_GPIO_PFR1_P3                      *((volatile unsigned int*)(0x4266008CUL))
+#define bFM3_GPIO_PFR1_P4                      *((volatile unsigned int*)(0x42660090UL))
+#define bFM3_GPIO_PFR1_P5                      *((volatile unsigned int*)(0x42660094UL))
+#define bFM3_GPIO_PFR1_P6                      *((volatile unsigned int*)(0x42660098UL))
+#define bFM3_GPIO_PFR1_P7                      *((volatile unsigned int*)(0x4266009CUL))
+#define bFM3_GPIO_PFR1_P8                      *((volatile unsigned int*)(0x426600A0UL))
+#define bFM3_GPIO_PFR1_P9                      *((volatile unsigned int*)(0x426600A4UL))
+#define bFM3_GPIO_PFR1_PA                      *((volatile unsigned int*)(0x426600A8UL))
+#define bFM3_GPIO_PFR1_PB                      *((volatile unsigned int*)(0x426600ACUL))
+#define bFM3_GPIO_PFR1_PC                      *((volatile unsigned int*)(0x426600B0UL))
+#define bFM3_GPIO_PFR1_PD                      *((volatile unsigned int*)(0x426600B4UL))
+#define bFM3_GPIO_PFR1_PE                      *((volatile unsigned int*)(0x426600B8UL))
+#define bFM3_GPIO_PFR1_PF                      *((volatile unsigned int*)(0x426600BCUL))
+#define bFM3_GPIO_PFR2_P0                      *((volatile unsigned int*)(0x42660100UL))
+#define bFM3_GPIO_PFR2_P1                      *((volatile unsigned int*)(0x42660104UL))
+#define bFM3_GPIO_PFR2_P2                      *((volatile unsigned int*)(0x42660108UL))
+#define bFM3_GPIO_PFR2_P3                      *((volatile unsigned int*)(0x4266010CUL))
+#define bFM3_GPIO_PFR2_P4                      *((volatile unsigned int*)(0x42660110UL))
+#define bFM3_GPIO_PFR2_P5                      *((volatile unsigned int*)(0x42660114UL))
+#define bFM3_GPIO_PFR2_P6                      *((volatile unsigned int*)(0x42660118UL))
+#define bFM3_GPIO_PFR2_P7                      *((volatile unsigned int*)(0x4266011CUL))
+#define bFM3_GPIO_PFR2_P8                      *((volatile unsigned int*)(0x42660120UL))
+#define bFM3_GPIO_PFR2_P9                      *((volatile unsigned int*)(0x42660124UL))
+#define bFM3_GPIO_PFR3_P6                      *((volatile unsigned int*)(0x42660198UL))
+#define bFM3_GPIO_PFR3_P7                      *((volatile unsigned int*)(0x4266019CUL))
+#define bFM3_GPIO_PFR3_P8                      *((volatile unsigned int*)(0x426601A0UL))
+#define bFM3_GPIO_PFR3_P9                      *((volatile unsigned int*)(0x426601A4UL))
+#define bFM3_GPIO_PFR3_PA                      *((volatile unsigned int*)(0x426601A8UL))
+#define bFM3_GPIO_PFR3_PB                      *((volatile unsigned int*)(0x426601ACUL))
+#define bFM3_GPIO_PFR3_PC                      *((volatile unsigned int*)(0x426601B0UL))
+#define bFM3_GPIO_PFR3_PD                      *((volatile unsigned int*)(0x426601B4UL))
+#define bFM3_GPIO_PFR3_PE                      *((volatile unsigned int*)(0x426601B8UL))
+#define bFM3_GPIO_PFR3_PF                      *((volatile unsigned int*)(0x426601BCUL))
+#define bFM3_GPIO_PFR4_P0                      *((volatile unsigned int*)(0x42660200UL))
+#define bFM3_GPIO_PFR4_P1                      *((volatile unsigned int*)(0x42660204UL))
+#define bFM3_GPIO_PFR4_P2                      *((volatile unsigned int*)(0x42660208UL))
+#define bFM3_GPIO_PFR4_P3                      *((volatile unsigned int*)(0x4266020CUL))
+#define bFM3_GPIO_PFR4_P4                      *((volatile unsigned int*)(0x42660210UL))
+#define bFM3_GPIO_PFR4_P5                      *((volatile unsigned int*)(0x42660214UL))
+#define bFM3_GPIO_PFR4_P6                      *((volatile unsigned int*)(0x42660218UL))
+#define bFM3_GPIO_PFR4_P7                      *((volatile unsigned int*)(0x4266021CUL))
+#define bFM3_GPIO_PFR4_P8                      *((volatile unsigned int*)(0x42660220UL))
+#define bFM3_GPIO_PFR4_P9                      *((volatile unsigned int*)(0x42660224UL))
+#define bFM3_GPIO_PFR4_PA                      *((volatile unsigned int*)(0x42660228UL))
+#define bFM3_GPIO_PFR4_PB                      *((volatile unsigned int*)(0x4266022CUL))
+#define bFM3_GPIO_PFR4_PC                      *((volatile unsigned int*)(0x42660230UL))
+#define bFM3_GPIO_PFR4_PD                      *((volatile unsigned int*)(0x42660234UL))
+#define bFM3_GPIO_PFR4_PE                      *((volatile unsigned int*)(0x42660238UL))
+#define bFM3_GPIO_PFR5_P0                      *((volatile unsigned int*)(0x42660280UL))
+#define bFM3_GPIO_PFR5_P1                      *((volatile unsigned int*)(0x42660284UL))
+#define bFM3_GPIO_PFR5_P2                      *((volatile unsigned int*)(0x42660288UL))
+#define bFM3_GPIO_PFR5_P3                      *((volatile unsigned int*)(0x4266028CUL))
+#define bFM3_GPIO_PFR5_P4                      *((volatile unsigned int*)(0x42660290UL))
+#define bFM3_GPIO_PFR5_P5                      *((volatile unsigned int*)(0x42660294UL))
+#define bFM3_GPIO_PFR5_P6                      *((volatile unsigned int*)(0x42660298UL))
+#define bFM3_GPIO_PFR5_P7                      *((volatile unsigned int*)(0x4266029CUL))
+#define bFM3_GPIO_PFR5_P8                      *((volatile unsigned int*)(0x426602A0UL))
+#define bFM3_GPIO_PFR5_P9                      *((volatile unsigned int*)(0x426602A4UL))
+#define bFM3_GPIO_PFR5_PA                      *((volatile unsigned int*)(0x426602A8UL))
+#define bFM3_GPIO_PFR5_PB                      *((volatile unsigned int*)(0x426602ACUL))
+#define bFM3_GPIO_PFR6_P0                      *((volatile unsigned int*)(0x42660300UL))
+#define bFM3_GPIO_PFR6_P1                      *((volatile unsigned int*)(0x42660304UL))
+#define bFM3_GPIO_PFR6_P2                      *((volatile unsigned int*)(0x42660308UL))
+#define bFM3_GPIO_PFR7_P0                      *((volatile unsigned int*)(0x42660380UL))
+#define bFM3_GPIO_PFR7_P1                      *((volatile unsigned int*)(0x42660384UL))
+#define bFM3_GPIO_PFR7_P2                      *((volatile unsigned int*)(0x42660388UL))
+#define bFM3_GPIO_PFR7_P3                      *((volatile unsigned int*)(0x4266038CUL))
+#define bFM3_GPIO_PFR7_P4                      *((volatile unsigned int*)(0x42660390UL))
+#define bFM3_GPIO_PFR7_P5                      *((volatile unsigned int*)(0x42660394UL))
+#define bFM3_GPIO_PFR7_P6                      *((volatile unsigned int*)(0x42660398UL))
+#define bFM3_GPIO_PFR7_P7                      *((volatile unsigned int*)(0x4266039CUL))
+#define bFM3_GPIO_PFR7_P8                      *((volatile unsigned int*)(0x426603A0UL))
+#define bFM3_GPIO_PFR7_P9                      *((volatile unsigned int*)(0x426603A4UL))
+#define bFM3_GPIO_PFR7_PA                      *((volatile unsigned int*)(0x426603A8UL))
+#define bFM3_GPIO_PFR8_P0                      *((volatile unsigned int*)(0x42660400UL))
+#define bFM3_GPIO_PFR8_P1                      *((volatile unsigned int*)(0x42660404UL))
+#define bFM3_GPIO_PFR8_P2                      *((volatile unsigned int*)(0x42660408UL))
+#define bFM3_GPIO_PFR8_P3                      *((volatile unsigned int*)(0x4266040CUL))
+#define bFM3_GPIO_PFRA_P0                      *((volatile unsigned int*)(0x42660500UL))
+#define bFM3_GPIO_PFRA_P1                      *((volatile unsigned int*)(0x42660504UL))
+#define bFM3_GPIO_PFRA_P2                      *((volatile unsigned int*)(0x42660508UL))
+#define bFM3_GPIO_PFRA_P3                      *((volatile unsigned int*)(0x4266050CUL))
+#define bFM3_GPIO_PFRA_P4                      *((volatile unsigned int*)(0x42660510UL))
+#define bFM3_GPIO_PFRA_P5                      *((volatile unsigned int*)(0x42660514UL))
+#define bFM3_GPIO_PFRC_P0                      *((volatile unsigned int*)(0x42660600UL))
+#define bFM3_GPIO_PFRC_P1                      *((volatile unsigned int*)(0x42660604UL))
+#define bFM3_GPIO_PFRC_P2                      *((volatile unsigned int*)(0x42660608UL))
+#define bFM3_GPIO_PFRC_P3                      *((volatile unsigned int*)(0x4266060CUL))
+#define bFM3_GPIO_PFRC_P4                      *((volatile unsigned int*)(0x42660610UL))
+#define bFM3_GPIO_PFRC_P5                      *((volatile unsigned int*)(0x42660614UL))
+#define bFM3_GPIO_PFRC_P6                      *((volatile unsigned int*)(0x42660618UL))
+#define bFM3_GPIO_PFRC_P7                      *((volatile unsigned int*)(0x4266061CUL))
+#define bFM3_GPIO_PFRC_P8                      *((volatile unsigned int*)(0x42660620UL))
+#define bFM3_GPIO_PFRC_P9                      *((volatile unsigned int*)(0x42660624UL))
+#define bFM3_GPIO_PFRC_PA                      *((volatile unsigned int*)(0x42660628UL))
+#define bFM3_GPIO_PFRC_PB                      *((volatile unsigned int*)(0x4266062CUL))
+#define bFM3_GPIO_PFRC_PC                      *((volatile unsigned int*)(0x42660630UL))
+#define bFM3_GPIO_PFRC_PD                      *((volatile unsigned int*)(0x42660634UL))
+#define bFM3_GPIO_PFRC_PE                      *((volatile unsigned int*)(0x42660638UL))
+#define bFM3_GPIO_PFRC_PF                      *((volatile unsigned int*)(0x4266063CUL))
+#define bFM3_GPIO_PFRD_P0                      *((volatile unsigned int*)(0x42660680UL))
+#define bFM3_GPIO_PFRD_P1                      *((volatile unsigned int*)(0x42660684UL))
+#define bFM3_GPIO_PFRD_P2                      *((volatile unsigned int*)(0x42660688UL))
+#define bFM3_GPIO_PFRD_P3                      *((volatile unsigned int*)(0x4266068CUL))
+#define bFM3_GPIO_PFRE_P0                      *((volatile unsigned int*)(0x42660700UL))
+#define bFM3_GPIO_PFRE_P2                      *((volatile unsigned int*)(0x42660708UL))
+#define bFM3_GPIO_PFRE_P3                      *((volatile unsigned int*)(0x4266070CUL))
+#define bFM3_GPIO_PFRF_P5                      *((volatile unsigned int*)(0x42660794UL))
+#define bFM3_GPIO_PFRF_P6                      *((volatile unsigned int*)(0x42660798UL))
+#define bFM3_GPIO_PCR0_P0                      *((volatile unsigned int*)(0x42662000UL))
+#define bFM3_GPIO_PCR0_P1                      *((volatile unsigned int*)(0x42662004UL))
+#define bFM3_GPIO_PCR0_P2                      *((volatile unsigned int*)(0x42662008UL))
+#define bFM3_GPIO_PCR0_P3                      *((volatile unsigned int*)(0x4266200CUL))
+#define bFM3_GPIO_PCR0_P4                      *((volatile unsigned int*)(0x42662010UL))
+#define bFM3_GPIO_PCR0_P5                      *((volatile unsigned int*)(0x42662014UL))
+#define bFM3_GPIO_PCR0_P6                      *((volatile unsigned int*)(0x42662018UL))
+#define bFM3_GPIO_PCR0_P7                      *((volatile unsigned int*)(0x4266201CUL))
+#define bFM3_GPIO_PCR0_P8                      *((volatile unsigned int*)(0x42662020UL))
+#define bFM3_GPIO_PCR0_P9                      *((volatile unsigned int*)(0x42662024UL))
+#define bFM3_GPIO_PCR1_P0                      *((volatile unsigned int*)(0x42662080UL))
+#define bFM3_GPIO_PCR1_P1                      *((volatile unsigned int*)(0x42662084UL))
+#define bFM3_GPIO_PCR1_P2                      *((volatile unsigned int*)(0x42662088UL))
+#define bFM3_GPIO_PCR1_P3                      *((volatile unsigned int*)(0x4266208CUL))
+#define bFM3_GPIO_PCR1_P4                      *((volatile unsigned int*)(0x42662090UL))
+#define bFM3_GPIO_PCR1_P5                      *((volatile unsigned int*)(0x42662094UL))
+#define bFM3_GPIO_PCR1_P6                      *((volatile unsigned int*)(0x42662098UL))
+#define bFM3_GPIO_PCR1_P7                      *((volatile unsigned int*)(0x4266209CUL))
+#define bFM3_GPIO_PCR1_P8                      *((volatile unsigned int*)(0x426620A0UL))
+#define bFM3_GPIO_PCR1_P9                      *((volatile unsigned int*)(0x426620A4UL))
+#define bFM3_GPIO_PCR1_PA                      *((volatile unsigned int*)(0x426620A8UL))
+#define bFM3_GPIO_PCR1_PB                      *((volatile unsigned int*)(0x426620ACUL))
+#define bFM3_GPIO_PCR1_PC                      *((volatile unsigned int*)(0x426620B0UL))
+#define bFM3_GPIO_PCR1_PD                      *((volatile unsigned int*)(0x426620B4UL))
+#define bFM3_GPIO_PCR1_PE                      *((volatile unsigned int*)(0x426620B8UL))
+#define bFM3_GPIO_PCR1_PF                      *((volatile unsigned int*)(0x426620BCUL))
+#define bFM3_GPIO_PCR2_P0                      *((volatile unsigned int*)(0x42662100UL))
+#define bFM3_GPIO_PCR2_P1                      *((volatile unsigned int*)(0x42662104UL))
+#define bFM3_GPIO_PCR2_P2                      *((volatile unsigned int*)(0x42662108UL))
+#define bFM3_GPIO_PCR2_P3                      *((volatile unsigned int*)(0x4266210CUL))
+#define bFM3_GPIO_PCR2_P4                      *((volatile unsigned int*)(0x42662110UL))
+#define bFM3_GPIO_PCR2_P5                      *((volatile unsigned int*)(0x42662114UL))
+#define bFM3_GPIO_PCR2_P6                      *((volatile unsigned int*)(0x42662118UL))
+#define bFM3_GPIO_PCR2_P7                      *((volatile unsigned int*)(0x4266211CUL))
+#define bFM3_GPIO_PCR2_P8                      *((volatile unsigned int*)(0x42662120UL))
+#define bFM3_GPIO_PCR2_P9                      *((volatile unsigned int*)(0x42662124UL))
+#define bFM3_GPIO_PCR3_P6                      *((volatile unsigned int*)(0x42662198UL))
+#define bFM3_GPIO_PCR3_P7                      *((volatile unsigned int*)(0x4266219CUL))
+#define bFM3_GPIO_PCR3_P8                      *((volatile unsigned int*)(0x426621A0UL))
+#define bFM3_GPIO_PCR3_P9                      *((volatile unsigned int*)(0x426621A4UL))
+#define bFM3_GPIO_PCR3_PA                      *((volatile unsigned int*)(0x426621A8UL))
+#define bFM3_GPIO_PCR3_PB                      *((volatile unsigned int*)(0x426621ACUL))
+#define bFM3_GPIO_PCR3_PC                      *((volatile unsigned int*)(0x426621B0UL))
+#define bFM3_GPIO_PCR3_PD                      *((volatile unsigned int*)(0x426621B4UL))
+#define bFM3_GPIO_PCR3_PE                      *((volatile unsigned int*)(0x426621B8UL))
+#define bFM3_GPIO_PCR3_PF                      *((volatile unsigned int*)(0x426621BCUL))
+#define bFM3_GPIO_PCR4_P0                      *((volatile unsigned int*)(0x42662200UL))
+#define bFM3_GPIO_PCR4_P1                      *((volatile unsigned int*)(0x42662204UL))
+#define bFM3_GPIO_PCR4_P2                      *((volatile unsigned int*)(0x42662208UL))
+#define bFM3_GPIO_PCR4_P3                      *((volatile unsigned int*)(0x4266220CUL))
+#define bFM3_GPIO_PCR4_P4                      *((volatile unsigned int*)(0x42662210UL))
+#define bFM3_GPIO_PCR4_P5                      *((volatile unsigned int*)(0x42662214UL))
+#define bFM3_GPIO_PCR4_P6                      *((volatile unsigned int*)(0x42662218UL))
+#define bFM3_GPIO_PCR4_P7                      *((volatile unsigned int*)(0x4266221CUL))
+#define bFM3_GPIO_PCR4_P8                      *((volatile unsigned int*)(0x42662220UL))
+#define bFM3_GPIO_PCR4_P9                      *((volatile unsigned int*)(0x42662224UL))
+#define bFM3_GPIO_PCR4_PA                      *((volatile unsigned int*)(0x42662228UL))
+#define bFM3_GPIO_PCR4_PB                      *((volatile unsigned int*)(0x4266222CUL))
+#define bFM3_GPIO_PCR4_PC                      *((volatile unsigned int*)(0x42662230UL))
+#define bFM3_GPIO_PCR4_PD                      *((volatile unsigned int*)(0x42662234UL))
+#define bFM3_GPIO_PCR4_PE                      *((volatile unsigned int*)(0x42662238UL))
+#define bFM3_GPIO_PCR5_P0                      *((volatile unsigned int*)(0x42662280UL))
+#define bFM3_GPIO_PCR5_P1                      *((volatile unsigned int*)(0x42662284UL))
+#define bFM3_GPIO_PCR5_P2                      *((volatile unsigned int*)(0x42662288UL))
+#define bFM3_GPIO_PCR5_P3                      *((volatile unsigned int*)(0x4266228CUL))
+#define bFM3_GPIO_PCR5_P4                      *((volatile unsigned int*)(0x42662290UL))
+#define bFM3_GPIO_PCR5_P5                      *((volatile unsigned int*)(0x42662294UL))
+#define bFM3_GPIO_PCR5_P6                      *((volatile unsigned int*)(0x42662298UL))
+#define bFM3_GPIO_PCR5_P7                      *((volatile unsigned int*)(0x4266229CUL))
+#define bFM3_GPIO_PCR5_P8                      *((volatile unsigned int*)(0x426622A0UL))
+#define bFM3_GPIO_PCR5_P9                      *((volatile unsigned int*)(0x426622A4UL))
+#define bFM3_GPIO_PCR5_PA                      *((volatile unsigned int*)(0x426622A8UL))
+#define bFM3_GPIO_PCR5_PB                      *((volatile unsigned int*)(0x426622ACUL))
+#define bFM3_GPIO_PCR6_P0                      *((volatile unsigned int*)(0x42662300UL))
+#define bFM3_GPIO_PCR6_P1                      *((volatile unsigned int*)(0x42662304UL))
+#define bFM3_GPIO_PCR6_P2                      *((volatile unsigned int*)(0x42662308UL))
+#define bFM3_GPIO_PCR7_P0                      *((volatile unsigned int*)(0x42662380UL))
+#define bFM3_GPIO_PCR7_P1                      *((volatile unsigned int*)(0x42662384UL))
+#define bFM3_GPIO_PCR7_P2                      *((volatile unsigned int*)(0x42662388UL))
+#define bFM3_GPIO_PCR7_P3                      *((volatile unsigned int*)(0x4266238CUL))
+#define bFM3_GPIO_PCR7_P4                      *((volatile unsigned int*)(0x42662390UL))
+#define bFM3_GPIO_PCR7_P5                      *((volatile unsigned int*)(0x42662394UL))
+#define bFM3_GPIO_PCR7_P6                      *((volatile unsigned int*)(0x42662398UL))
+#define bFM3_GPIO_PCR7_P7                      *((volatile unsigned int*)(0x4266239CUL))
+#define bFM3_GPIO_PCR7_P8                      *((volatile unsigned int*)(0x426623A0UL))
+#define bFM3_GPIO_PCR7_P9                      *((volatile unsigned int*)(0x426623A4UL))
+#define bFM3_GPIO_PCR7_PA                      *((volatile unsigned int*)(0x426623A8UL))
+#define bFM3_GPIO_PCRA_P0                      *((volatile unsigned int*)(0x42662500UL))
+#define bFM3_GPIO_PCRA_P1                      *((volatile unsigned int*)(0x42662504UL))
+#define bFM3_GPIO_PCRA_P2                      *((volatile unsigned int*)(0x42662508UL))
+#define bFM3_GPIO_PCRA_P3                      *((volatile unsigned int*)(0x4266250CUL))
+#define bFM3_GPIO_PCRA_P4                      *((volatile unsigned int*)(0x42662510UL))
+#define bFM3_GPIO_PCRA_P5                      *((volatile unsigned int*)(0x42662514UL))
+#define bFM3_GPIO_PCRC_P0                      *((volatile unsigned int*)(0x42662600UL))
+#define bFM3_GPIO_PCRC_P1                      *((volatile unsigned int*)(0x42662604UL))
+#define bFM3_GPIO_PCRC_P2                      *((volatile unsigned int*)(0x42662608UL))
+#define bFM3_GPIO_PCRC_P3                      *((volatile unsigned int*)(0x4266260CUL))
+#define bFM3_GPIO_PCRC_P4                      *((volatile unsigned int*)(0x42662610UL))
+#define bFM3_GPIO_PCRC_P5                      *((volatile unsigned int*)(0x42662614UL))
+#define bFM3_GPIO_PCRC_P6                      *((volatile unsigned int*)(0x42662618UL))
+#define bFM3_GPIO_PCRC_P7                      *((volatile unsigned int*)(0x4266261CUL))
+#define bFM3_GPIO_PCRC_P8                      *((volatile unsigned int*)(0x42662620UL))
+#define bFM3_GPIO_PCRC_P9                      *((volatile unsigned int*)(0x42662624UL))
+#define bFM3_GPIO_PCRC_PA                      *((volatile unsigned int*)(0x42662628UL))
+#define bFM3_GPIO_PCRC_PB                      *((volatile unsigned int*)(0x4266262CUL))
+#define bFM3_GPIO_PCRC_PC                      *((volatile unsigned int*)(0x42662630UL))
+#define bFM3_GPIO_PCRC_PD                      *((volatile unsigned int*)(0x42662634UL))
+#define bFM3_GPIO_PCRC_PE                      *((volatile unsigned int*)(0x42662638UL))
+#define bFM3_GPIO_PCRC_PF                      *((volatile unsigned int*)(0x4266263CUL))
+#define bFM3_GPIO_PCRD_P0                      *((volatile unsigned int*)(0x42662680UL))
+#define bFM3_GPIO_PCRD_P1                      *((volatile unsigned int*)(0x42662684UL))
+#define bFM3_GPIO_PCRD_P2                      *((volatile unsigned int*)(0x42662688UL))
+#define bFM3_GPIO_PCRD_P3                      *((volatile unsigned int*)(0x4266268CUL))
+#define bFM3_GPIO_PCRE_P2                      *((volatile unsigned int*)(0x42662708UL))
+#define bFM3_GPIO_PCRE_P3                      *((volatile unsigned int*)(0x4266270CUL))
+#define bFM3_GPIO_DDR0_P0                      *((volatile unsigned int*)(0x42664000UL))
+#define bFM3_GPIO_DDR0_P1                      *((volatile unsigned int*)(0x42664004UL))
+#define bFM3_GPIO_DDR0_P2                      *((volatile unsigned int*)(0x42664008UL))
+#define bFM3_GPIO_DDR0_P3                      *((volatile unsigned int*)(0x4266400CUL))
+#define bFM3_GPIO_DDR0_P4                      *((volatile unsigned int*)(0x42664010UL))
+#define bFM3_GPIO_DDR0_P5                      *((volatile unsigned int*)(0x42664014UL))
+#define bFM3_GPIO_DDR0_P6                      *((volatile unsigned int*)(0x42664018UL))
+#define bFM3_GPIO_DDR0_P7                      *((volatile unsigned int*)(0x4266401CUL))
+#define bFM3_GPIO_DDR0_P8                      *((volatile unsigned int*)(0x42664020UL))
+#define bFM3_GPIO_DDR0_P9                      *((volatile unsigned int*)(0x42664024UL))
+#define bFM3_GPIO_DDR1_P0                      *((volatile unsigned int*)(0x42664080UL))
+#define bFM3_GPIO_DDR1_P1                      *((volatile unsigned int*)(0x42664084UL))
+#define bFM3_GPIO_DDR1_P2                      *((volatile unsigned int*)(0x42664088UL))
+#define bFM3_GPIO_DDR1_P3                      *((volatile unsigned int*)(0x4266408CUL))
+#define bFM3_GPIO_DDR1_P4                      *((volatile unsigned int*)(0x42664090UL))
+#define bFM3_GPIO_DDR1_P5                      *((volatile unsigned int*)(0x42664094UL))
+#define bFM3_GPIO_DDR1_P6                      *((volatile unsigned int*)(0x42664098UL))
+#define bFM3_GPIO_DDR1_P7                      *((volatile unsigned int*)(0x4266409CUL))
+#define bFM3_GPIO_DDR1_P8                      *((volatile unsigned int*)(0x426640A0UL))
+#define bFM3_GPIO_DDR1_P9                      *((volatile unsigned int*)(0x426640A4UL))
+#define bFM3_GPIO_DDR1_PA                      *((volatile unsigned int*)(0x426640A8UL))
+#define bFM3_GPIO_DDR1_PB                      *((volatile unsigned int*)(0x426640ACUL))
+#define bFM3_GPIO_DDR1_PC                      *((volatile unsigned int*)(0x426640B0UL))
+#define bFM3_GPIO_DDR1_PD                      *((volatile unsigned int*)(0x426640B4UL))
+#define bFM3_GPIO_DDR1_PE                      *((volatile unsigned int*)(0x426640B8UL))
+#define bFM3_GPIO_DDR1_PF                      *((volatile unsigned int*)(0x426640BCUL))
+#define bFM3_GPIO_DDR2_P0                      *((volatile unsigned int*)(0x42664100UL))
+#define bFM3_GPIO_DDR2_P1                      *((volatile unsigned int*)(0x42664104UL))
+#define bFM3_GPIO_DDR2_P2                      *((volatile unsigned int*)(0x42664108UL))
+#define bFM3_GPIO_DDR2_P3                      *((volatile unsigned int*)(0x4266410CUL))
+#define bFM3_GPIO_DDR2_P4                      *((volatile unsigned int*)(0x42664110UL))
+#define bFM3_GPIO_DDR2_P5                      *((volatile unsigned int*)(0x42664114UL))
+#define bFM3_GPIO_DDR2_P6                      *((volatile unsigned int*)(0x42664118UL))
+#define bFM3_GPIO_DDR2_P7                      *((volatile unsigned int*)(0x4266411CUL))
+#define bFM3_GPIO_DDR2_P8                      *((volatile unsigned int*)(0x42664120UL))
+#define bFM3_GPIO_DDR2_P9                      *((volatile unsigned int*)(0x42664124UL))
+#define bFM3_GPIO_DDR3_P6                      *((volatile unsigned int*)(0x42664198UL))
+#define bFM3_GPIO_DDR3_P7                      *((volatile unsigned int*)(0x4266419CUL))
+#define bFM3_GPIO_DDR3_P8                      *((volatile unsigned int*)(0x426641A0UL))
+#define bFM3_GPIO_DDR3_P9                      *((volatile unsigned int*)(0x426641A4UL))
+#define bFM3_GPIO_DDR3_PA                      *((volatile unsigned int*)(0x426641A8UL))
+#define bFM3_GPIO_DDR3_PB                      *((volatile unsigned int*)(0x426641ACUL))
+#define bFM3_GPIO_DDR3_PC                      *((volatile unsigned int*)(0x426641B0UL))
+#define bFM3_GPIO_DDR3_PD                      *((volatile unsigned int*)(0x426641B4UL))
+#define bFM3_GPIO_DDR3_PE                      *((volatile unsigned int*)(0x426641B8UL))
+#define bFM3_GPIO_DDR3_PF                      *((volatile unsigned int*)(0x426641BCUL))
+#define bFM3_GPIO_DDR4_P0                      *((volatile unsigned int*)(0x42664200UL))
+#define bFM3_GPIO_DDR4_P1                      *((volatile unsigned int*)(0x42664204UL))
+#define bFM3_GPIO_DDR4_P2                      *((volatile unsigned int*)(0x42664208UL))
+#define bFM3_GPIO_DDR4_P3                      *((volatile unsigned int*)(0x4266420CUL))
+#define bFM3_GPIO_DDR4_P4                      *((volatile unsigned int*)(0x42664210UL))
+#define bFM3_GPIO_DDR4_P5                      *((volatile unsigned int*)(0x42664214UL))
+#define bFM3_GPIO_DDR4_P6                      *((volatile unsigned int*)(0x42664218UL))
+#define bFM3_GPIO_DDR4_P7                      *((volatile unsigned int*)(0x4266421CUL))
+#define bFM3_GPIO_DDR4_P8                      *((volatile unsigned int*)(0x42664220UL))
+#define bFM3_GPIO_DDR4_P9                      *((volatile unsigned int*)(0x42664224UL))
+#define bFM3_GPIO_DDR4_PA                      *((volatile unsigned int*)(0x42664228UL))
+#define bFM3_GPIO_DDR4_PB                      *((volatile unsigned int*)(0x4266422CUL))
+#define bFM3_GPIO_DDR4_PC                      *((volatile unsigned int*)(0x42664230UL))
+#define bFM3_GPIO_DDR4_PD                      *((volatile unsigned int*)(0x42664234UL))
+#define bFM3_GPIO_DDR4_PE                      *((volatile unsigned int*)(0x42664238UL))
+#define bFM3_GPIO_DDR5_P0                      *((volatile unsigned int*)(0x42664280UL))
+#define bFM3_GPIO_DDR5_P1                      *((volatile unsigned int*)(0x42664284UL))
+#define bFM3_GPIO_DDR5_P2                      *((volatile unsigned int*)(0x42664288UL))
+#define bFM3_GPIO_DDR5_P3                      *((volatile unsigned int*)(0x4266428CUL))
+#define bFM3_GPIO_DDR5_P4                      *((volatile unsigned int*)(0x42664290UL))
+#define bFM3_GPIO_DDR5_P5                      *((volatile unsigned int*)(0x42664294UL))
+#define bFM3_GPIO_DDR5_P6                      *((volatile unsigned int*)(0x42664298UL))
+#define bFM3_GPIO_DDR5_P7                      *((volatile unsigned int*)(0x4266429CUL))
+#define bFM3_GPIO_DDR5_P8                      *((volatile unsigned int*)(0x426642A0UL))
+#define bFM3_GPIO_DDR5_P9                      *((volatile unsigned int*)(0x426642A4UL))
+#define bFM3_GPIO_DDR5_PA                      *((volatile unsigned int*)(0x426642A8UL))
+#define bFM3_GPIO_DDR5_PB                      *((volatile unsigned int*)(0x426642ACUL))
+#define bFM3_GPIO_DDR6_P0                      *((volatile unsigned int*)(0x42664300UL))
+#define bFM3_GPIO_DDR6_P1                      *((volatile unsigned int*)(0x42664304UL))
+#define bFM3_GPIO_DDR6_P2                      *((volatile unsigned int*)(0x42664308UL))
+#define bFM3_GPIO_DDR7_P0                      *((volatile unsigned int*)(0x42664380UL))
+#define bFM3_GPIO_DDR7_P1                      *((volatile unsigned int*)(0x42664384UL))
+#define bFM3_GPIO_DDR7_P2                      *((volatile unsigned int*)(0x42664388UL))
+#define bFM3_GPIO_DDR7_P3                      *((volatile unsigned int*)(0x4266438CUL))
+#define bFM3_GPIO_DDR7_P4                      *((volatile unsigned int*)(0x42664390UL))
+#define bFM3_GPIO_DDR7_P5                      *((volatile unsigned int*)(0x42664394UL))
+#define bFM3_GPIO_DDR7_P6                      *((volatile unsigned int*)(0x42664398UL))
+#define bFM3_GPIO_DDR7_P7                      *((volatile unsigned int*)(0x4266439CUL))
+#define bFM3_GPIO_DDR7_P8                      *((volatile unsigned int*)(0x426643A0UL))
+#define bFM3_GPIO_DDR7_P9                      *((volatile unsigned int*)(0x426643A4UL))
+#define bFM3_GPIO_DDR7_PA                      *((volatile unsigned int*)(0x426643A8UL))
+#define bFM3_GPIO_DDR8_P0                      *((volatile unsigned int*)(0x42664400UL))
+#define bFM3_GPIO_DDR8_P1                      *((volatile unsigned int*)(0x42664404UL))
+#define bFM3_GPIO_DDR8_P2                      *((volatile unsigned int*)(0x42664408UL))
+#define bFM3_GPIO_DDR8_P3                      *((volatile unsigned int*)(0x4266440CUL))
+#define bFM3_GPIO_DDRA_P0                      *((volatile unsigned int*)(0x42664500UL))
+#define bFM3_GPIO_DDRA_P1                      *((volatile unsigned int*)(0x42664504UL))
+#define bFM3_GPIO_DDRA_P2                      *((volatile unsigned int*)(0x42664508UL))
+#define bFM3_GPIO_DDRA_P3                      *((volatile unsigned int*)(0x4266450CUL))
+#define bFM3_GPIO_DDRA_P4                      *((volatile unsigned int*)(0x42664510UL))
+#define bFM3_GPIO_DDRA_P5                      *((volatile unsigned int*)(0x42664514UL))
+#define bFM3_GPIO_DDRC_P0                      *((volatile unsigned int*)(0x42664600UL))
+#define bFM3_GPIO_DDRC_P1                      *((volatile unsigned int*)(0x42664604UL))
+#define bFM3_GPIO_DDRC_P2                      *((volatile unsigned int*)(0x42664608UL))
+#define bFM3_GPIO_DDRC_P3                      *((volatile unsigned int*)(0x4266460CUL))
+#define bFM3_GPIO_DDRC_P4                      *((volatile unsigned int*)(0x42664610UL))
+#define bFM3_GPIO_DDRC_P5                      *((volatile unsigned int*)(0x42664614UL))
+#define bFM3_GPIO_DDRC_P6                      *((volatile unsigned int*)(0x42664618UL))
+#define bFM3_GPIO_DDRC_P7                      *((volatile unsigned int*)(0x4266461CUL))
+#define bFM3_GPIO_DDRC_P8                      *((volatile unsigned int*)(0x42664620UL))
+#define bFM3_GPIO_DDRC_P9                      *((volatile unsigned int*)(0x42664624UL))
+#define bFM3_GPIO_DDRC_PA                      *((volatile unsigned int*)(0x42664628UL))
+#define bFM3_GPIO_DDRC_PB                      *((volatile unsigned int*)(0x4266462CUL))
+#define bFM3_GPIO_DDRC_PC                      *((volatile unsigned int*)(0x42664630UL))
+#define bFM3_GPIO_DDRC_PD                      *((volatile unsigned int*)(0x42664634UL))
+#define bFM3_GPIO_DDRC_PE                      *((volatile unsigned int*)(0x42664638UL))
+#define bFM3_GPIO_DDRC_PF                      *((volatile unsigned int*)(0x4266463CUL))
+#define bFM3_GPIO_DDRD_P0                      *((volatile unsigned int*)(0x42664680UL))
+#define bFM3_GPIO_DDRD_P1                      *((volatile unsigned int*)(0x42664684UL))
+#define bFM3_GPIO_DDRD_P2                      *((volatile unsigned int*)(0x42664688UL))
+#define bFM3_GPIO_DDRD_P3                      *((volatile unsigned int*)(0x4266468CUL))
+#define bFM3_GPIO_DDRE_P0                      *((volatile unsigned int*)(0x42664700UL))
+#define bFM3_GPIO_DDRE_P2                      *((volatile unsigned int*)(0x42664708UL))
+#define bFM3_GPIO_DDRE_P3                      *((volatile unsigned int*)(0x4266470CUL))
+#define bFM3_GPIO_DDRF_P5                      *((volatile unsigned int*)(0x42664794UL))
+#define bFM3_GPIO_DDRF_P6                      *((volatile unsigned int*)(0x42664798UL))
+#define bFM3_GPIO_PDIR0_P0                     *((volatile unsigned int*)(0x42666000UL))
+#define bFM3_GPIO_PDIR0_P1                     *((volatile unsigned int*)(0x42666004UL))
+#define bFM3_GPIO_PDIR0_P2                     *((volatile unsigned int*)(0x42666008UL))
+#define bFM3_GPIO_PDIR0_P3                     *((volatile unsigned int*)(0x4266600CUL))
+#define bFM3_GPIO_PDIR0_P4                     *((volatile unsigned int*)(0x42666010UL))
+#define bFM3_GPIO_PDIR0_P5                     *((volatile unsigned int*)(0x42666014UL))
+#define bFM3_GPIO_PDIR0_P6                     *((volatile unsigned int*)(0x42666018UL))
+#define bFM3_GPIO_PDIR0_P7                     *((volatile unsigned int*)(0x4266601CUL))
+#define bFM3_GPIO_PDIR0_P8                     *((volatile unsigned int*)(0x42666020UL))
+#define bFM3_GPIO_PDIR0_P9                     *((volatile unsigned int*)(0x42666024UL))
+#define bFM3_GPIO_PDIR1_P0                     *((volatile unsigned int*)(0x42666080UL))
+#define bFM3_GPIO_PDIR1_P1                     *((volatile unsigned int*)(0x42666084UL))
+#define bFM3_GPIO_PDIR1_P2                     *((volatile unsigned int*)(0x42666088UL))
+#define bFM3_GPIO_PDIR1_P3                     *((volatile unsigned int*)(0x4266608CUL))
+#define bFM3_GPIO_PDIR1_P4                     *((volatile unsigned int*)(0x42666090UL))
+#define bFM3_GPIO_PDIR1_P5                     *((volatile unsigned int*)(0x42666094UL))
+#define bFM3_GPIO_PDIR1_P6                     *((volatile unsigned int*)(0x42666098UL))
+#define bFM3_GPIO_PDIR1_P7                     *((volatile unsigned int*)(0x4266609CUL))
+#define bFM3_GPIO_PDIR1_P8                     *((volatile unsigned int*)(0x426660A0UL))
+#define bFM3_GPIO_PDIR1_P9                     *((volatile unsigned int*)(0x426660A4UL))
+#define bFM3_GPIO_PDIR1_PA                     *((volatile unsigned int*)(0x426660A8UL))
+#define bFM3_GPIO_PDIR1_PB                     *((volatile unsigned int*)(0x426660ACUL))
+#define bFM3_GPIO_PDIR1_PC                     *((volatile unsigned int*)(0x426660B0UL))
+#define bFM3_GPIO_PDIR1_PD                     *((volatile unsigned int*)(0x426660B4UL))
+#define bFM3_GPIO_PDIR1_PE                     *((volatile unsigned int*)(0x426660B8UL))
+#define bFM3_GPIO_PDIR1_PF                     *((volatile unsigned int*)(0x426660BCUL))
+#define bFM3_GPIO_PDIR2_P0                     *((volatile unsigned int*)(0x42666100UL))
+#define bFM3_GPIO_PDIR2_P1                     *((volatile unsigned int*)(0x42666104UL))
+#define bFM3_GPIO_PDIR2_P2                     *((volatile unsigned int*)(0x42666108UL))
+#define bFM3_GPIO_PDIR2_P3                     *((volatile unsigned int*)(0x4266610CUL))
+#define bFM3_GPIO_PDIR2_P4                     *((volatile unsigned int*)(0x42666110UL))
+#define bFM3_GPIO_PDIR2_P5                     *((volatile unsigned int*)(0x42666114UL))
+#define bFM3_GPIO_PDIR2_P6                     *((volatile unsigned int*)(0x42666118UL))
+#define bFM3_GPIO_PDIR2_P7                     *((volatile unsigned int*)(0x4266611CUL))
+#define bFM3_GPIO_PDIR2_P8                     *((volatile unsigned int*)(0x42666120UL))
+#define bFM3_GPIO_PDIR2_P9                     *((volatile unsigned int*)(0x42666124UL))
+#define bFM3_GPIO_PDIR3_P6                     *((volatile unsigned int*)(0x42666198UL))
+#define bFM3_GPIO_PDIR3_P7                     *((volatile unsigned int*)(0x4266619CUL))
+#define bFM3_GPIO_PDIR3_P8                     *((volatile unsigned int*)(0x426661A0UL))
+#define bFM3_GPIO_PDIR3_P9                     *((volatile unsigned int*)(0x426661A4UL))
+#define bFM3_GPIO_PDIR3_PA                     *((volatile unsigned int*)(0x426661A8UL))
+#define bFM3_GPIO_PDIR3_PB                     *((volatile unsigned int*)(0x426661ACUL))
+#define bFM3_GPIO_PDIR3_PC                     *((volatile unsigned int*)(0x426661B0UL))
+#define bFM3_GPIO_PDIR3_PD                     *((volatile unsigned int*)(0x426661B4UL))
+#define bFM3_GPIO_PDIR3_PE                     *((volatile unsigned int*)(0x426661B8UL))
+#define bFM3_GPIO_PDIR3_PF                     *((volatile unsigned int*)(0x426661BCUL))
+#define bFM3_GPIO_PDIR4_P0                     *((volatile unsigned int*)(0x42666200UL))
+#define bFM3_GPIO_PDIR4_P1                     *((volatile unsigned int*)(0x42666204UL))
+#define bFM3_GPIO_PDIR4_P2                     *((volatile unsigned int*)(0x42666208UL))
+#define bFM3_GPIO_PDIR4_P3                     *((volatile unsigned int*)(0x4266620CUL))
+#define bFM3_GPIO_PDIR4_P4                     *((volatile unsigned int*)(0x42666210UL))
+#define bFM3_GPIO_PDIR4_P5                     *((volatile unsigned int*)(0x42666214UL))
+#define bFM3_GPIO_PDIR4_P6                     *((volatile unsigned int*)(0x42666218UL))
+#define bFM3_GPIO_PDIR4_P7                     *((volatile unsigned int*)(0x4266621CUL))
+#define bFM3_GPIO_PDIR4_P8                     *((volatile unsigned int*)(0x42666220UL))
+#define bFM3_GPIO_PDIR4_P9                     *((volatile unsigned int*)(0x42666224UL))
+#define bFM3_GPIO_PDIR4_PA                     *((volatile unsigned int*)(0x42666228UL))
+#define bFM3_GPIO_PDIR4_PB                     *((volatile unsigned int*)(0x4266622CUL))
+#define bFM3_GPIO_PDIR4_PC                     *((volatile unsigned int*)(0x42666230UL))
+#define bFM3_GPIO_PDIR4_PD                     *((volatile unsigned int*)(0x42666234UL))
+#define bFM3_GPIO_PDIR4_PE                     *((volatile unsigned int*)(0x42666238UL))
+#define bFM3_GPIO_PDIR5_P0                     *((volatile unsigned int*)(0x42666280UL))
+#define bFM3_GPIO_PDIR5_P1                     *((volatile unsigned int*)(0x42666284UL))
+#define bFM3_GPIO_PDIR5_P2                     *((volatile unsigned int*)(0x42666288UL))
+#define bFM3_GPIO_PDIR5_P3                     *((volatile unsigned int*)(0x4266628CUL))
+#define bFM3_GPIO_PDIR5_P4                     *((volatile unsigned int*)(0x42666290UL))
+#define bFM3_GPIO_PDIR5_P5                     *((volatile unsigned int*)(0x42666294UL))
+#define bFM3_GPIO_PDIR5_P6                     *((volatile unsigned int*)(0x42666298UL))
+#define bFM3_GPIO_PDIR5_P7                     *((volatile unsigned int*)(0x4266629CUL))
+#define bFM3_GPIO_PDIR5_P8                     *((volatile unsigned int*)(0x426662A0UL))
+#define bFM3_GPIO_PDIR5_P9                     *((volatile unsigned int*)(0x426662A4UL))
+#define bFM3_GPIO_PDIR5_PA                     *((volatile unsigned int*)(0x426662A8UL))
+#define bFM3_GPIO_PDIR5_PB                     *((volatile unsigned int*)(0x426662ACUL))
+#define bFM3_GPIO_PDIR6_P0                     *((volatile unsigned int*)(0x42666300UL))
+#define bFM3_GPIO_PDIR6_P1                     *((volatile unsigned int*)(0x42666304UL))
+#define bFM3_GPIO_PDIR6_P2                     *((volatile unsigned int*)(0x42666308UL))
+#define bFM3_GPIO_PDIR7_P0                     *((volatile unsigned int*)(0x42666380UL))
+#define bFM3_GPIO_PDIR7_P1                     *((volatile unsigned int*)(0x42666384UL))
+#define bFM3_GPIO_PDIR7_P2                     *((volatile unsigned int*)(0x42666388UL))
+#define bFM3_GPIO_PDIR7_P3                     *((volatile unsigned int*)(0x4266638CUL))
+#define bFM3_GPIO_PDIR7_P4                     *((volatile unsigned int*)(0x42666390UL))
+#define bFM3_GPIO_PDIR7_P5                     *((volatile unsigned int*)(0x42666394UL))
+#define bFM3_GPIO_PDIR7_P6                     *((volatile unsigned int*)(0x42666398UL))
+#define bFM3_GPIO_PDIR7_P7                     *((volatile unsigned int*)(0x4266639CUL))
+#define bFM3_GPIO_PDIR7_P8                     *((volatile unsigned int*)(0x426663A0UL))
+#define bFM3_GPIO_PDIR7_P9                     *((volatile unsigned int*)(0x426663A4UL))
+#define bFM3_GPIO_PDIR7_PA                     *((volatile unsigned int*)(0x426663A8UL))
+#define bFM3_GPIO_PDIR8_P0                     *((volatile unsigned int*)(0x42666400UL))
+#define bFM3_GPIO_PDIR8_P1                     *((volatile unsigned int*)(0x42666404UL))
+#define bFM3_GPIO_PDIR8_P2                     *((volatile unsigned int*)(0x42666408UL))
+#define bFM3_GPIO_PDIR8_P3                     *((volatile unsigned int*)(0x4266640CUL))
+#define bFM3_GPIO_PDIRA_P0                     *((volatile unsigned int*)(0x42666500UL))
+#define bFM3_GPIO_PDIRA_P1                     *((volatile unsigned int*)(0x42666504UL))
+#define bFM3_GPIO_PDIRA_P2                     *((volatile unsigned int*)(0x42666508UL))
+#define bFM3_GPIO_PDIRA_P3                     *((volatile unsigned int*)(0x4266650CUL))
+#define bFM3_GPIO_PDIRA_P4                     *((volatile unsigned int*)(0x42666510UL))
+#define bFM3_GPIO_PDIRA_P5                     *((volatile unsigned int*)(0x42666514UL))
+#define bFM3_GPIO_PDIRC_P0                     *((volatile unsigned int*)(0x42666600UL))
+#define bFM3_GPIO_PDIRC_P1                     *((volatile unsigned int*)(0x42666604UL))
+#define bFM3_GPIO_PDIRC_P2                     *((volatile unsigned int*)(0x42666608UL))
+#define bFM3_GPIO_PDIRC_P3                     *((volatile unsigned int*)(0x4266660CUL))
+#define bFM3_GPIO_PDIRC_P4                     *((volatile unsigned int*)(0x42666610UL))
+#define bFM3_GPIO_PDIRC_P5                     *((volatile unsigned int*)(0x42666614UL))
+#define bFM3_GPIO_PDIRC_P6                     *((volatile unsigned int*)(0x42666618UL))
+#define bFM3_GPIO_PDIRC_P7                     *((volatile unsigned int*)(0x4266661CUL))
+#define bFM3_GPIO_PDIRC_P8                     *((volatile unsigned int*)(0x42666620UL))
+#define bFM3_GPIO_PDIRC_P9                     *((volatile unsigned int*)(0x42666624UL))
+#define bFM3_GPIO_PDIRC_PA                     *((volatile unsigned int*)(0x42666628UL))
+#define bFM3_GPIO_PDIRC_PB                     *((volatile unsigned int*)(0x4266662CUL))
+#define bFM3_GPIO_PDIRC_PC                     *((volatile unsigned int*)(0x42666630UL))
+#define bFM3_GPIO_PDIRC_PD                     *((volatile unsigned int*)(0x42666634UL))
+#define bFM3_GPIO_PDIRC_PE                     *((volatile unsigned int*)(0x42666638UL))
+#define bFM3_GPIO_PDIRC_PF                     *((volatile unsigned int*)(0x4266663CUL))
+#define bFM3_GPIO_PDIRD_P0                     *((volatile unsigned int*)(0x42666680UL))
+#define bFM3_GPIO_PDIRD_P1                     *((volatile unsigned int*)(0x42666684UL))
+#define bFM3_GPIO_PDIRD_P2                     *((volatile unsigned int*)(0x42666688UL))
+#define bFM3_GPIO_PDIRD_P3                     *((volatile unsigned int*)(0x4266668CUL))
+#define bFM3_GPIO_PDIRE_P0                     *((volatile unsigned int*)(0x42666700UL))
+#define bFM3_GPIO_PDIRE_P2                     *((volatile unsigned int*)(0x42666708UL))
+#define bFM3_GPIO_PDIRE_P3                     *((volatile unsigned int*)(0x4266670CUL))
+#define bFM3_GPIO_PDIRF_P5                     *((volatile unsigned int*)(0x42666794UL))
+#define bFM3_GPIO_PDIRF_P6                     *((volatile unsigned int*)(0x42666798UL))
+#define bFM3_GPIO_PDOR0_P0                     *((volatile unsigned int*)(0x42668000UL))
+#define bFM3_GPIO_PDOR0_P1                     *((volatile unsigned int*)(0x42668004UL))
+#define bFM3_GPIO_PDOR0_P2                     *((volatile unsigned int*)(0x42668008UL))
+#define bFM3_GPIO_PDOR0_P3                     *((volatile unsigned int*)(0x4266800CUL))
+#define bFM3_GPIO_PDOR0_P4                     *((volatile unsigned int*)(0x42668010UL))
+#define bFM3_GPIO_PDOR0_P5                     *((volatile unsigned int*)(0x42668014UL))
+#define bFM3_GPIO_PDOR0_P6                     *((volatile unsigned int*)(0x42668018UL))
+#define bFM3_GPIO_PDOR0_P7                     *((volatile unsigned int*)(0x4266801CUL))
+#define bFM3_GPIO_PDOR0_P8                     *((volatile unsigned int*)(0x42668020UL))
+#define bFM3_GPIO_PDOR0_P9                     *((volatile unsigned int*)(0x42668024UL))
+#define bFM3_GPIO_PDOR1_P0                     *((volatile unsigned int*)(0x42668080UL))
+#define bFM3_GPIO_PDOR1_P1                     *((volatile unsigned int*)(0x42668084UL))
+#define bFM3_GPIO_PDOR1_P2                     *((volatile unsigned int*)(0x42668088UL))
+#define bFM3_GPIO_PDOR1_P3                     *((volatile unsigned int*)(0x4266808CUL))
+#define bFM3_GPIO_PDOR1_P4                     *((volatile unsigned int*)(0x42668090UL))
+#define bFM3_GPIO_PDOR1_P5                     *((volatile unsigned int*)(0x42668094UL))
+#define bFM3_GPIO_PDOR1_P6                     *((volatile unsigned int*)(0x42668098UL))
+#define bFM3_GPIO_PDOR1_P7                     *((volatile unsigned int*)(0x4266809CUL))
+#define bFM3_GPIO_PDOR1_P8                     *((volatile unsigned int*)(0x426680A0UL))
+#define bFM3_GPIO_PDOR1_P9                     *((volatile unsigned int*)(0x426680A4UL))
+#define bFM3_GPIO_PDOR1_PA                     *((volatile unsigned int*)(0x426680A8UL))
+#define bFM3_GPIO_PDOR1_PB                     *((volatile unsigned int*)(0x426680ACUL))
+#define bFM3_GPIO_PDOR1_PC                     *((volatile unsigned int*)(0x426680B0UL))
+#define bFM3_GPIO_PDOR1_PD                     *((volatile unsigned int*)(0x426680B4UL))
+#define bFM3_GPIO_PDOR1_PE                     *((volatile unsigned int*)(0x426680B8UL))
+#define bFM3_GPIO_PDOR1_PF                     *((volatile unsigned int*)(0x426680BCUL))
+#define bFM3_GPIO_PDOR2_P0                     *((volatile unsigned int*)(0x42668100UL))
+#define bFM3_GPIO_PDOR2_P1                     *((volatile unsigned int*)(0x42668104UL))
+#define bFM3_GPIO_PDOR2_P2                     *((volatile unsigned int*)(0x42668108UL))
+#define bFM3_GPIO_PDOR2_P3                     *((volatile unsigned int*)(0x4266810CUL))
+#define bFM3_GPIO_PDOR2_P4                     *((volatile unsigned int*)(0x42668110UL))
+#define bFM3_GPIO_PDOR2_P5                     *((volatile unsigned int*)(0x42668114UL))
+#define bFM3_GPIO_PDOR2_P6                     *((volatile unsigned int*)(0x42668118UL))
+#define bFM3_GPIO_PDOR2_P7                     *((volatile unsigned int*)(0x4266811CUL))
+#define bFM3_GPIO_PDOR2_P8                     *((volatile unsigned int*)(0x42668120UL))
+#define bFM3_GPIO_PDOR2_P9                     *((volatile unsigned int*)(0x42668124UL))
+#define bFM3_GPIO_PDOR3_P6                     *((volatile unsigned int*)(0x42668198UL))
+#define bFM3_GPIO_PDOR3_P7                     *((volatile unsigned int*)(0x4266819CUL))
+#define bFM3_GPIO_PDOR3_P8                     *((volatile unsigned int*)(0x426681A0UL))
+#define bFM3_GPIO_PDOR3_P9                     *((volatile unsigned int*)(0x426681A4UL))
+#define bFM3_GPIO_PDOR3_PA                     *((volatile unsigned int*)(0x426681A8UL))
+#define bFM3_GPIO_PDOR3_PB                     *((volatile unsigned int*)(0x426681ACUL))
+#define bFM3_GPIO_PDOR3_PC                     *((volatile unsigned int*)(0x426681B0UL))
+#define bFM3_GPIO_PDOR3_PD                     *((volatile unsigned int*)(0x426681B4UL))
+#define bFM3_GPIO_PDOR3_PE                     *((volatile unsigned int*)(0x426681B8UL))
+#define bFM3_GPIO_PDOR3_PF                     *((volatile unsigned int*)(0x426681BCUL))
+#define bFM3_GPIO_PDOR4_P0                     *((volatile unsigned int*)(0x42668200UL))
+#define bFM3_GPIO_PDOR4_P1                     *((volatile unsigned int*)(0x42668204UL))
+#define bFM3_GPIO_PDOR4_P2                     *((volatile unsigned int*)(0x42668208UL))
+#define bFM3_GPIO_PDOR4_P3                     *((volatile unsigned int*)(0x4266820CUL))
+#define bFM3_GPIO_PDOR4_P4                     *((volatile unsigned int*)(0x42668210UL))
+#define bFM3_GPIO_PDOR4_P5                     *((volatile unsigned int*)(0x42668214UL))
+#define bFM3_GPIO_PDOR4_P6                     *((volatile unsigned int*)(0x42668218UL))
+#define bFM3_GPIO_PDOR4_P7                     *((volatile unsigned int*)(0x4266821CUL))
+#define bFM3_GPIO_PDOR4_P8                     *((volatile unsigned int*)(0x42668220UL))
+#define bFM3_GPIO_PDOR4_P9                     *((volatile unsigned int*)(0x42668224UL))
+#define bFM3_GPIO_PDOR4_PA                     *((volatile unsigned int*)(0x42668228UL))
+#define bFM3_GPIO_PDOR4_PB                     *((volatile unsigned int*)(0x4266822CUL))
+#define bFM3_GPIO_PDOR4_PC                     *((volatile unsigned int*)(0x42668230UL))
+#define bFM3_GPIO_PDOR4_PD                     *((volatile unsigned int*)(0x42668234UL))
+#define bFM3_GPIO_PDOR4_PE                     *((volatile unsigned int*)(0x42668238UL))
+#define bFM3_GPIO_PDOR5_P0                     *((volatile unsigned int*)(0x42668280UL))
+#define bFM3_GPIO_PDOR5_P1                     *((volatile unsigned int*)(0x42668284UL))
+#define bFM3_GPIO_PDOR5_P2                     *((volatile unsigned int*)(0x42668288UL))
+#define bFM3_GPIO_PDOR5_P3                     *((volatile unsigned int*)(0x4266828CUL))
+#define bFM3_GPIO_PDOR5_P4                     *((volatile unsigned int*)(0x42668290UL))
+#define bFM3_GPIO_PDOR5_P5                     *((volatile unsigned int*)(0x42668294UL))
+#define bFM3_GPIO_PDOR5_P6                     *((volatile unsigned int*)(0x42668298UL))
+#define bFM3_GPIO_PDOR5_P7                     *((volatile unsigned int*)(0x4266829CUL))
+#define bFM3_GPIO_PDOR5_P8                     *((volatile unsigned int*)(0x426682A0UL))
+#define bFM3_GPIO_PDOR5_P9                     *((volatile unsigned int*)(0x426682A4UL))
+#define bFM3_GPIO_PDOR5_PA                     *((volatile unsigned int*)(0x426682A8UL))
+#define bFM3_GPIO_PDOR5_PB                     *((volatile unsigned int*)(0x426682ACUL))
+#define bFM3_GPIO_PDOR6_P0                     *((volatile unsigned int*)(0x42668300UL))
+#define bFM3_GPIO_PDOR6_P1                     *((volatile unsigned int*)(0x42668304UL))
+#define bFM3_GPIO_PDOR6_P2                     *((volatile unsigned int*)(0x42668308UL))
+#define bFM3_GPIO_PDOR7_P0                     *((volatile unsigned int*)(0x42668380UL))
+#define bFM3_GPIO_PDOR7_P1                     *((volatile unsigned int*)(0x42668384UL))
+#define bFM3_GPIO_PDOR7_P2                     *((volatile unsigned int*)(0x42668388UL))
+#define bFM3_GPIO_PDOR7_P3                     *((volatile unsigned int*)(0x4266838CUL))
+#define bFM3_GPIO_PDOR7_P4                     *((volatile unsigned int*)(0x42668390UL))
+#define bFM3_GPIO_PDOR7_P5                     *((volatile unsigned int*)(0x42668394UL))
+#define bFM3_GPIO_PDOR7_P6                     *((volatile unsigned int*)(0x42668398UL))
+#define bFM3_GPIO_PDOR7_P7                     *((volatile unsigned int*)(0x4266839CUL))
+#define bFM3_GPIO_PDOR7_P8                     *((volatile unsigned int*)(0x426683A0UL))
+#define bFM3_GPIO_PDOR7_P9                     *((volatile unsigned int*)(0x426683A4UL))
+#define bFM3_GPIO_PDOR7_PA                     *((volatile unsigned int*)(0x426683A8UL))
+#define bFM3_GPIO_PDOR8_P0                     *((volatile unsigned int*)(0x42668400UL))
+#define bFM3_GPIO_PDOR8_P1                     *((volatile unsigned int*)(0x42668404UL))
+#define bFM3_GPIO_PDOR8_P2                     *((volatile unsigned int*)(0x42668408UL))
+#define bFM3_GPIO_PDOR8_P3                     *((volatile unsigned int*)(0x4266840CUL))
+#define bFM3_GPIO_PDORA_P0                     *((volatile unsigned int*)(0x42668500UL))
+#define bFM3_GPIO_PDORA_P1                     *((volatile unsigned int*)(0x42668504UL))
+#define bFM3_GPIO_PDORA_P2                     *((volatile unsigned int*)(0x42668508UL))
+#define bFM3_GPIO_PDORA_P3                     *((volatile unsigned int*)(0x4266850CUL))
+#define bFM3_GPIO_PDORA_P4                     *((volatile unsigned int*)(0x42668510UL))
+#define bFM3_GPIO_PDORA_P5                     *((volatile unsigned int*)(0x42668514UL))
+#define bFM3_GPIO_PDORC_P0                     *((volatile unsigned int*)(0x42668600UL))
+#define bFM3_GPIO_PDORC_P1                     *((volatile unsigned int*)(0x42668604UL))
+#define bFM3_GPIO_PDORC_P2                     *((volatile unsigned int*)(0x42668608UL))
+#define bFM3_GPIO_PDORC_P3                     *((volatile unsigned int*)(0x4266860CUL))
+#define bFM3_GPIO_PDORC_P4                     *((volatile unsigned int*)(0x42668610UL))
+#define bFM3_GPIO_PDORC_P5                     *((volatile unsigned int*)(0x42668614UL))
+#define bFM3_GPIO_PDORC_P6                     *((volatile unsigned int*)(0x42668618UL))
+#define bFM3_GPIO_PDORC_P7                     *((volatile unsigned int*)(0x4266861CUL))
+#define bFM3_GPIO_PDORC_P8                     *((volatile unsigned int*)(0x42668620UL))
+#define bFM3_GPIO_PDORC_P9                     *((volatile unsigned int*)(0x42668624UL))
+#define bFM3_GPIO_PDORC_PA                     *((volatile unsigned int*)(0x42668628UL))
+#define bFM3_GPIO_PDORC_PB                     *((volatile unsigned int*)(0x4266862CUL))
+#define bFM3_GPIO_PDORC_PC                     *((volatile unsigned int*)(0x42668630UL))
+#define bFM3_GPIO_PDORC_PD                     *((volatile unsigned int*)(0x42668634UL))
+#define bFM3_GPIO_PDORC_PE                     *((volatile unsigned int*)(0x42668638UL))
+#define bFM3_GPIO_PDORC_PF                     *((volatile unsigned int*)(0x4266863CUL))
+#define bFM3_GPIO_PDORD_P0                     *((volatile unsigned int*)(0x42668680UL))
+#define bFM3_GPIO_PDORD_P1                     *((volatile unsigned int*)(0x42668684UL))
+#define bFM3_GPIO_PDORD_P2                     *((volatile unsigned int*)(0x42668688UL))
+#define bFM3_GPIO_PDORD_P3                     *((volatile unsigned int*)(0x4266868CUL))
+#define bFM3_GPIO_PDORE_P0                     *((volatile unsigned int*)(0x42668700UL))
+#define bFM3_GPIO_PDORE_P2                     *((volatile unsigned int*)(0x42668708UL))
+#define bFM3_GPIO_PDORE_P3                     *((volatile unsigned int*)(0x4266870CUL))
+#define bFM3_GPIO_PDORF_P5                     *((volatile unsigned int*)(0x42668794UL))
+#define bFM3_GPIO_PDORF_P6                     *((volatile unsigned int*)(0x42668798UL))
+#define bFM3_GPIO_ADE_AN0                      *((volatile unsigned int*)(0x4266A000UL))
+#define bFM3_GPIO_ADE_AN1                      *((volatile unsigned int*)(0x4266A004UL))
+#define bFM3_GPIO_ADE_AN2                      *((volatile unsigned int*)(0x4266A008UL))
+#define bFM3_GPIO_ADE_AN3                      *((volatile unsigned int*)(0x4266A00CUL))
+#define bFM3_GPIO_ADE_AN4                      *((volatile unsigned int*)(0x4266A010UL))
+#define bFM3_GPIO_ADE_AN5                      *((volatile unsigned int*)(0x4266A014UL))
+#define bFM3_GPIO_ADE_AN6                      *((volatile unsigned int*)(0x4266A018UL))
+#define bFM3_GPIO_ADE_AN7                      *((volatile unsigned int*)(0x4266A01CUL))
+#define bFM3_GPIO_ADE_AN8                      *((volatile unsigned int*)(0x4266A020UL))
+#define bFM3_GPIO_ADE_AN9                      *((volatile unsigned int*)(0x4266A024UL))
+#define bFM3_GPIO_ADE_AN10                     *((volatile unsigned int*)(0x4266A028UL))
+#define bFM3_GPIO_ADE_AN11                     *((volatile unsigned int*)(0x4266A02CUL))
+#define bFM3_GPIO_ADE_AN12                     *((volatile unsigned int*)(0x4266A030UL))
+#define bFM3_GPIO_ADE_AN13                     *((volatile unsigned int*)(0x4266A034UL))
+#define bFM3_GPIO_ADE_AN14                     *((volatile unsigned int*)(0x4266A038UL))
+#define bFM3_GPIO_ADE_AN15                     *((volatile unsigned int*)(0x4266A03CUL))
+#define bFM3_GPIO_ADE_AN24                     *((volatile unsigned int*)(0x4266A060UL))
+#define bFM3_GPIO_ADE_AN25                     *((volatile unsigned int*)(0x4266A064UL))
+#define bFM3_GPIO_ADE_AN26                     *((volatile unsigned int*)(0x4266A068UL))
+#define bFM3_GPIO_ADE_AN27                     *((volatile unsigned int*)(0x4266A06CUL))
+#define bFM3_GPIO_ADE_AN28                     *((volatile unsigned int*)(0x4266A070UL))
+#define bFM3_GPIO_ADE_AN29                     *((volatile unsigned int*)(0x4266A074UL))
+#define bFM3_GPIO_ADE_AN30                     *((volatile unsigned int*)(0x4266A078UL))
+#define bFM3_GPIO_ADE_AN31                     *((volatile unsigned int*)(0x4266A07CUL))
+#define bFM3_GPIO_SPSR_SUBXC                   *((volatile unsigned int*)(0x4266B000UL))
+#define bFM3_GPIO_SPSR_MAINXC                  *((volatile unsigned int*)(0x4266B008UL))
+#define bFM3_GPIO_SPSR_USB0C                   *((volatile unsigned int*)(0x4266B010UL))
+#define bFM3_GPIO_SPSR_USB1C                   *((volatile unsigned int*)(0x4266B014UL))
+#define bFM3_GPIO_EPFR00_NMIS                  *((volatile unsigned int*)(0x4266C000UL))
+#define bFM3_GPIO_EPFR00_CROUTE0               *((volatile unsigned int*)(0x4266C004UL))
+#define bFM3_GPIO_EPFR00_CROUTE1               *((volatile unsigned int*)(0x4266C008UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE0              *((volatile unsigned int*)(0x4266C018UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE1              *((volatile unsigned int*)(0x4266C01CUL))
+#define bFM3_GPIO_EPFR00_USBP0E                *((volatile unsigned int*)(0x4266C024UL))
+#define bFM3_GPIO_EPFR00_USBP1E                *((volatile unsigned int*)(0x4266C034UL))
+#define bFM3_GPIO_EPFR00_JTAGEN0B              *((volatile unsigned int*)(0x4266C040UL))
+#define bFM3_GPIO_EPFR00_JTAGEN1S              *((volatile unsigned int*)(0x4266C044UL))
+#define bFM3_GPIO_EPFR00_TRC0E                 *((volatile unsigned int*)(0x4266C060UL))
+#define bFM3_GPIO_EPFR00_TRC1E                 *((volatile unsigned int*)(0x4266C064UL))
+#define bFM3_GPIO_EPFR01_RTO00E0               *((volatile unsigned int*)(0x4266C080UL))
+#define bFM3_GPIO_EPFR01_RTO00E1               *((volatile unsigned int*)(0x4266C084UL))
+#define bFM3_GPIO_EPFR01_RTO01E0               *((volatile unsigned int*)(0x4266C088UL))
+#define bFM3_GPIO_EPFR01_RTO01E1               *((volatile unsigned int*)(0x4266C08CUL))
+#define bFM3_GPIO_EPFR01_RTO02E0               *((volatile unsigned int*)(0x4266C090UL))
+#define bFM3_GPIO_EPFR01_RTO02E1               *((volatile unsigned int*)(0x4266C094UL))
+#define bFM3_GPIO_EPFR01_RTO03E0               *((volatile unsigned int*)(0x4266C098UL))
+#define bFM3_GPIO_EPFR01_RTO03E1               *((volatile unsigned int*)(0x4266C09CUL))
+#define bFM3_GPIO_EPFR01_RTO04E0               *((volatile unsigned int*)(0x4266C0A0UL))
+#define bFM3_GPIO_EPFR01_RTO04E1               *((volatile unsigned int*)(0x4266C0A4UL))
+#define bFM3_GPIO_EPFR01_RTO05E0               *((volatile unsigned int*)(0x4266C0A8UL))
+#define bFM3_GPIO_EPFR01_RTO05E1               *((volatile unsigned int*)(0x4266C0ACUL))
+#define bFM3_GPIO_EPFR01_DTTI0C                *((volatile unsigned int*)(0x4266C0B0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S0               *((volatile unsigned int*)(0x4266C0C0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S1               *((volatile unsigned int*)(0x4266C0C4UL))
+#define bFM3_GPIO_EPFR01_FRCK0S0               *((volatile unsigned int*)(0x4266C0C8UL))
+#define bFM3_GPIO_EPFR01_FRCK0S1               *((volatile unsigned int*)(0x4266C0CCUL))
+#define bFM3_GPIO_EPFR01_IC00S0                *((volatile unsigned int*)(0x4266C0D0UL))
+#define bFM3_GPIO_EPFR01_IC00S1                *((volatile unsigned int*)(0x4266C0D4UL))
+#define bFM3_GPIO_EPFR01_IC00S2                *((volatile unsigned int*)(0x4266C0D8UL))
+#define bFM3_GPIO_EPFR01_IC01S0                *((volatile unsigned int*)(0x4266C0DCUL))
+#define bFM3_GPIO_EPFR01_IC01S1                *((volatile unsigned int*)(0x4266C0E0UL))
+#define bFM3_GPIO_EPFR01_IC01S2                *((volatile unsigned int*)(0x4266C0E4UL))
+#define bFM3_GPIO_EPFR01_IC02S0                *((volatile unsigned int*)(0x4266C0E8UL))
+#define bFM3_GPIO_EPFR01_IC02S1                *((volatile unsigned int*)(0x4266C0ECUL))
+#define bFM3_GPIO_EPFR01_IC02S2                *((volatile unsigned int*)(0x4266C0F0UL))
+#define bFM3_GPIO_EPFR01_IC03S0                *((volatile unsigned int*)(0x4266C0F4UL))
+#define bFM3_GPIO_EPFR01_IC03S1                *((volatile unsigned int*)(0x4266C0F8UL))
+#define bFM3_GPIO_EPFR01_IC03S2                *((volatile unsigned int*)(0x4266C0FCUL))
+#define bFM3_GPIO_EPFR02_RTO10E0               *((volatile unsigned int*)(0x4266C100UL))
+#define bFM3_GPIO_EPFR02_RTO10E1               *((volatile unsigned int*)(0x4266C104UL))
+#define bFM3_GPIO_EPFR02_RTO11E0               *((volatile unsigned int*)(0x4266C108UL))
+#define bFM3_GPIO_EPFR02_RTO11E1               *((volatile unsigned int*)(0x4266C10CUL))
+#define bFM3_GPIO_EPFR02_RTO12E0               *((volatile unsigned int*)(0x4266C110UL))
+#define bFM3_GPIO_EPFR02_RTO12E1               *((volatile unsigned int*)(0x4266C114UL))
+#define bFM3_GPIO_EPFR02_RTO13E0               *((volatile unsigned int*)(0x4266C118UL))
+#define bFM3_GPIO_EPFR02_RTO13E1               *((volatile unsigned int*)(0x4266C11CUL))
+#define bFM3_GPIO_EPFR02_RTO14E0               *((volatile unsigned int*)(0x4266C120UL))
+#define bFM3_GPIO_EPFR02_RTO14E1               *((volatile unsigned int*)(0x4266C124UL))
+#define bFM3_GPIO_EPFR02_RTO15E0               *((volatile unsigned int*)(0x4266C128UL))
+#define bFM3_GPIO_EPFR02_RTO15E1               *((volatile unsigned int*)(0x4266C12CUL))
+#define bFM3_GPIO_EPFR02_DTTI1C                *((volatile unsigned int*)(0x4266C130UL))
+#define bFM3_GPIO_EPFR02_DTTI1S0               *((volatile unsigned int*)(0x4266C140UL))
+#define bFM3_GPIO_EPFR02_DTTI1S1               *((volatile unsigned int*)(0x4266C144UL))
+#define bFM3_GPIO_EPFR02_FRCK1S0               *((volatile unsigned int*)(0x4266C148UL))
+#define bFM3_GPIO_EPFR02_FRCK1S1               *((volatile unsigned int*)(0x4266C14CUL))
+#define bFM3_GPIO_EPFR02_IC10S0                *((volatile unsigned int*)(0x4266C150UL))
+#define bFM3_GPIO_EPFR02_IC10S1                *((volatile unsigned int*)(0x4266C154UL))
+#define bFM3_GPIO_EPFR02_IC10S2                *((volatile unsigned int*)(0x4266C158UL))
+#define bFM3_GPIO_EPFR02_IC11S0                *((volatile unsigned int*)(0x4266C15CUL))
+#define bFM3_GPIO_EPFR02_IC11S1                *((volatile unsigned int*)(0x4266C160UL))
+#define bFM3_GPIO_EPFR02_IC11S2                *((volatile unsigned int*)(0x4266C164UL))
+#define bFM3_GPIO_EPFR02_IC12S0                *((volatile unsigned int*)(0x4266C168UL))
+#define bFM3_GPIO_EPFR02_IC12S1                *((volatile unsigned int*)(0x4266C16CUL))
+#define bFM3_GPIO_EPFR02_IC12S2                *((volatile unsigned int*)(0x4266C170UL))
+#define bFM3_GPIO_EPFR02_IC13S0                *((volatile unsigned int*)(0x4266C174UL))
+#define bFM3_GPIO_EPFR02_IC13S1                *((volatile unsigned int*)(0x4266C178UL))
+#define bFM3_GPIO_EPFR02_IC13S2                *((volatile unsigned int*)(0x4266C17CUL))
+#define bFM3_GPIO_EPFR03_RTO20E0               *((volatile unsigned int*)(0x4266C180UL))
+#define bFM3_GPIO_EPFR03_RTO20E1               *((volatile unsigned int*)(0x4266C184UL))
+#define bFM3_GPIO_EPFR03_RTO21E0               *((volatile unsigned int*)(0x4266C188UL))
+#define bFM3_GPIO_EPFR03_RTO21E1               *((volatile unsigned int*)(0x4266C18CUL))
+#define bFM3_GPIO_EPFR03_RTO22E0               *((volatile unsigned int*)(0x4266C190UL))
+#define bFM3_GPIO_EPFR03_RTO22E1               *((volatile unsigned int*)(0x4266C194UL))
+#define bFM3_GPIO_EPFR03_RTO23E0               *((volatile unsigned int*)(0x4266C198UL))
+#define bFM3_GPIO_EPFR03_RTO23E1               *((volatile unsigned int*)(0x4266C19CUL))
+#define bFM3_GPIO_EPFR03_RTO24E0               *((volatile unsigned int*)(0x4266C1A0UL))
+#define bFM3_GPIO_EPFR03_RTO24E1               *((volatile unsigned int*)(0x4266C1A4UL))
+#define bFM3_GPIO_EPFR03_RTO25E0               *((volatile unsigned int*)(0x4266C1A8UL))
+#define bFM3_GPIO_EPFR03_RTO25E1               *((volatile unsigned int*)(0x4266C1ACUL))
+#define bFM3_GPIO_EPFR03_DTTI2C                *((volatile unsigned int*)(0x4266C1B0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S0               *((volatile unsigned int*)(0x4266C1C0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S1               *((volatile unsigned int*)(0x4266C1C4UL))
+#define bFM3_GPIO_EPFR03_FRCK2S0               *((volatile unsigned int*)(0x4266C1C8UL))
+#define bFM3_GPIO_EPFR03_FRCK2S1               *((volatile unsigned int*)(0x4266C1CCUL))
+#define bFM3_GPIO_EPFR03_IC20S0                *((volatile unsigned int*)(0x4266C1D0UL))
+#define bFM3_GPIO_EPFR03_IC20S1                *((volatile unsigned int*)(0x4266C1D4UL))
+#define bFM3_GPIO_EPFR03_IC20S2                *((volatile unsigned int*)(0x4266C1D8UL))
+#define bFM3_GPIO_EPFR03_IC21S0                *((volatile unsigned int*)(0x4266C1DCUL))
+#define bFM3_GPIO_EPFR03_IC21S1                *((volatile unsigned int*)(0x4266C1E0UL))
+#define bFM3_GPIO_EPFR03_IC21S2                *((volatile unsigned int*)(0x4266C1E4UL))
+#define bFM3_GPIO_EPFR03_IC22S0                *((volatile unsigned int*)(0x4266C1E8UL))
+#define bFM3_GPIO_EPFR03_IC22S1                *((volatile unsigned int*)(0x4266C1ECUL))
+#define bFM3_GPIO_EPFR03_IC22S2                *((volatile unsigned int*)(0x4266C1F0UL))
+#define bFM3_GPIO_EPFR03_IC23S0                *((volatile unsigned int*)(0x4266C1F4UL))
+#define bFM3_GPIO_EPFR03_IC23S1                *((volatile unsigned int*)(0x4266C1F8UL))
+#define bFM3_GPIO_EPFR03_IC23S2                *((volatile unsigned int*)(0x4266C1FCUL))
+#define bFM3_GPIO_EPFR04_TIOA0E0               *((volatile unsigned int*)(0x4266C208UL))
+#define bFM3_GPIO_EPFR04_TIOA0E1               *((volatile unsigned int*)(0x4266C20CUL))
+#define bFM3_GPIO_EPFR04_TIOB0S0               *((volatile unsigned int*)(0x4266C210UL))
+#define bFM3_GPIO_EPFR04_TIOB0S1               *((volatile unsigned int*)(0x4266C214UL))
+#define bFM3_GPIO_EPFR04_TIOA1S0               *((volatile unsigned int*)(0x4266C220UL))
+#define bFM3_GPIO_EPFR04_TIOA1S1               *((volatile unsigned int*)(0x4266C224UL))
+#define bFM3_GPIO_EPFR04_TIOA1E0               *((volatile unsigned int*)(0x4266C228UL))
+#define bFM3_GPIO_EPFR04_TIOA1E1               *((volatile unsigned int*)(0x4266C22CUL))
+#define bFM3_GPIO_EPFR04_TIOB1S0               *((volatile unsigned int*)(0x4266C230UL))
+#define bFM3_GPIO_EPFR04_TIOB1S1               *((volatile unsigned int*)(0x4266C234UL))
+#define bFM3_GPIO_EPFR04_TIOA2E0               *((volatile unsigned int*)(0x4266C248UL))
+#define bFM3_GPIO_EPFR04_TIOA2E1               *((volatile unsigned int*)(0x4266C24CUL))
+#define bFM3_GPIO_EPFR04_TIOB2S0               *((volatile unsigned int*)(0x4266C250UL))
+#define bFM3_GPIO_EPFR04_TIOB2S1               *((volatile unsigned int*)(0x4266C254UL))
+#define bFM3_GPIO_EPFR04_TIOA3S0               *((volatile unsigned int*)(0x4266C260UL))
+#define bFM3_GPIO_EPFR04_TIOA3S1               *((volatile unsigned int*)(0x4266C264UL))
+#define bFM3_GPIO_EPFR04_TIOA3E0               *((volatile unsigned int*)(0x4266C268UL))
+#define bFM3_GPIO_EPFR04_TIOA3E1               *((volatile unsigned int*)(0x4266C26CUL))
+#define bFM3_GPIO_EPFR04_TIOB3S0               *((volatile unsigned int*)(0x4266C270UL))
+#define bFM3_GPIO_EPFR04_TIOB3S1               *((volatile unsigned int*)(0x4266C274UL))
+#define bFM3_GPIO_EPFR05_TIOA4E0               *((volatile unsigned int*)(0x4266C288UL))
+#define bFM3_GPIO_EPFR05_TIOA4E1               *((volatile unsigned int*)(0x4266C28CUL))
+#define bFM3_GPIO_EPFR05_TIOB4S0               *((volatile unsigned int*)(0x4266C290UL))
+#define bFM3_GPIO_EPFR05_TIOB4S1               *((volatile unsigned int*)(0x4266C294UL))
+#define bFM3_GPIO_EPFR05_TIOA5S0               *((volatile unsigned int*)(0x4266C2A0UL))
+#define bFM3_GPIO_EPFR05_TIOA5S1               *((volatile unsigned int*)(0x4266C2A4UL))
+#define bFM3_GPIO_EPFR05_TIOA5E0               *((volatile unsigned int*)(0x4266C2A8UL))
+#define bFM3_GPIO_EPFR05_TIOA5E1               *((volatile unsigned int*)(0x4266C2ACUL))
+#define bFM3_GPIO_EPFR05_TIOB5S0               *((volatile unsigned int*)(0x4266C2B0UL))
+#define bFM3_GPIO_EPFR05_TIOB5S1               *((volatile unsigned int*)(0x4266C2B4UL))
+#define bFM3_GPIO_EPFR05_TIOA6E0               *((volatile unsigned int*)(0x4266C2C8UL))
+#define bFM3_GPIO_EPFR05_TIOA6E1               *((volatile unsigned int*)(0x4266C2CCUL))
+#define bFM3_GPIO_EPFR05_TIOB6S0               *((volatile unsigned int*)(0x4266C2D0UL))
+#define bFM3_GPIO_EPFR05_TIOB6S1               *((volatile unsigned int*)(0x4266C2D4UL))
+#define bFM3_GPIO_EPFR05_TIOA7S0               *((volatile unsigned int*)(0x4266C2E0UL))
+#define bFM3_GPIO_EPFR05_TIOA7S1               *((volatile unsigned int*)(0x4266C2E4UL))
+#define bFM3_GPIO_EPFR05_TIOA7E0               *((volatile unsigned int*)(0x4266C2E8UL))
+#define bFM3_GPIO_EPFR05_TIOA7E1               *((volatile unsigned int*)(0x4266C2ECUL))
+#define bFM3_GPIO_EPFR05_TIOB7S0               *((volatile unsigned int*)(0x4266C2F0UL))
+#define bFM3_GPIO_EPFR05_TIOB7S1               *((volatile unsigned int*)(0x4266C2F4UL))
+#define bFM3_GPIO_EPFR06_EINT00S0              *((volatile unsigned int*)(0x4266C300UL))
+#define bFM3_GPIO_EPFR06_EINT00S1              *((volatile unsigned int*)(0x4266C304UL))
+#define bFM3_GPIO_EPFR06_EINT01S0              *((volatile unsigned int*)(0x4266C308UL))
+#define bFM3_GPIO_EPFR06_EINT01S1              *((volatile unsigned int*)(0x4266C30CUL))
+#define bFM3_GPIO_EPFR06_EINT02S0              *((volatile unsigned int*)(0x4266C310UL))
+#define bFM3_GPIO_EPFR06_EINT02S1              *((volatile unsigned int*)(0x4266C314UL))
+#define bFM3_GPIO_EPFR06_EINT03S0              *((volatile unsigned int*)(0x4266C318UL))
+#define bFM3_GPIO_EPFR06_EINT03S1              *((volatile unsigned int*)(0x4266C31CUL))
+#define bFM3_GPIO_EPFR06_EINT04S0              *((volatile unsigned int*)(0x4266C320UL))
+#define bFM3_GPIO_EPFR06_EINT04S1              *((volatile unsigned int*)(0x4266C324UL))
+#define bFM3_GPIO_EPFR06_EINT05S0              *((volatile unsigned int*)(0x4266C328UL))
+#define bFM3_GPIO_EPFR06_EINT05S1              *((volatile unsigned int*)(0x4266C32CUL))
+#define bFM3_GPIO_EPFR06_EINT06S0              *((volatile unsigned int*)(0x4266C330UL))
+#define bFM3_GPIO_EPFR06_EINT06S1              *((volatile unsigned int*)(0x4266C334UL))
+#define bFM3_GPIO_EPFR06_EINT07S0              *((volatile unsigned int*)(0x4266C338UL))
+#define bFM3_GPIO_EPFR06_EINT07S1              *((volatile unsigned int*)(0x4266C33CUL))
+#define bFM3_GPIO_EPFR06_EINT08S0              *((volatile unsigned int*)(0x4266C340UL))
+#define bFM3_GPIO_EPFR06_EINT08S1              *((volatile unsigned int*)(0x4266C344UL))
+#define bFM3_GPIO_EPFR06_EINT09S0              *((volatile unsigned int*)(0x4266C348UL))
+#define bFM3_GPIO_EPFR06_EINT09S1              *((volatile unsigned int*)(0x4266C34CUL))
+#define bFM3_GPIO_EPFR06_EINT10S0              *((volatile unsigned int*)(0x4266C350UL))
+#define bFM3_GPIO_EPFR06_EINT10S1              *((volatile unsigned int*)(0x4266C354UL))
+#define bFM3_GPIO_EPFR06_EINT11S0              *((volatile unsigned int*)(0x4266C358UL))
+#define bFM3_GPIO_EPFR06_EINT11S1              *((volatile unsigned int*)(0x4266C35CUL))
+#define bFM3_GPIO_EPFR06_EINT12S0              *((volatile unsigned int*)(0x4266C360UL))
+#define bFM3_GPIO_EPFR06_EINT12S1              *((volatile unsigned int*)(0x4266C364UL))
+#define bFM3_GPIO_EPFR06_EINT13S0              *((volatile unsigned int*)(0x4266C368UL))
+#define bFM3_GPIO_EPFR06_EINT13S1              *((volatile unsigned int*)(0x4266C36CUL))
+#define bFM3_GPIO_EPFR06_EINT14S0              *((volatile unsigned int*)(0x4266C370UL))
+#define bFM3_GPIO_EPFR06_EINT14S1              *((volatile unsigned int*)(0x4266C374UL))
+#define bFM3_GPIO_EPFR06_EINT15S0              *((volatile unsigned int*)(0x4266C378UL))
+#define bFM3_GPIO_EPFR06_EINT15S1              *((volatile unsigned int*)(0x4266C37CUL))
+#define bFM3_GPIO_EPFR07_SIN0S0                *((volatile unsigned int*)(0x4266C390UL))
+#define bFM3_GPIO_EPFR07_SIN0S1                *((volatile unsigned int*)(0x4266C394UL))
+#define bFM3_GPIO_EPFR07_SOT0B0                *((volatile unsigned int*)(0x4266C398UL))
+#define bFM3_GPIO_EPFR07_SOT0B1                *((volatile unsigned int*)(0x4266C39CUL))
+#define bFM3_GPIO_EPFR07_SCK0B0                *((volatile unsigned int*)(0x4266C3A0UL))
+#define bFM3_GPIO_EPFR07_SCK0B1                *((volatile unsigned int*)(0x4266C3A4UL))
+#define bFM3_GPIO_EPFR07_SIN1S0                *((volatile unsigned int*)(0x4266C3A8UL))
+#define bFM3_GPIO_EPFR07_SIN1S1                *((volatile unsigned int*)(0x4266C3ACUL))
+#define bFM3_GPIO_EPFR07_SOT1B0                *((volatile unsigned int*)(0x4266C3B0UL))
+#define bFM3_GPIO_EPFR07_SOT1B1                *((volatile unsigned int*)(0x4266C3B4UL))
+#define bFM3_GPIO_EPFR07_SCK1B0                *((volatile unsigned int*)(0x4266C3B8UL))
+#define bFM3_GPIO_EPFR07_SCK1B1                *((volatile unsigned int*)(0x4266C3BCUL))
+#define bFM3_GPIO_EPFR07_SIN2S0                *((volatile unsigned int*)(0x4266C3C0UL))
+#define bFM3_GPIO_EPFR07_SIN2S1                *((volatile unsigned int*)(0x4266C3C4UL))
+#define bFM3_GPIO_EPFR07_SOT2B0                *((volatile unsigned int*)(0x4266C3C8UL))
+#define bFM3_GPIO_EPFR07_SOT2B1                *((volatile unsigned int*)(0x4266C3CCUL))
+#define bFM3_GPIO_EPFR07_SCK2B0                *((volatile unsigned int*)(0x4266C3D0UL))
+#define bFM3_GPIO_EPFR07_SCK2B1                *((volatile unsigned int*)(0x4266C3D4UL))
+#define bFM3_GPIO_EPFR07_SIN3S0                *((volatile unsigned int*)(0x4266C3D8UL))
+#define bFM3_GPIO_EPFR07_SIN3S1                *((volatile unsigned int*)(0x4266C3DCUL))
+#define bFM3_GPIO_EPFR07_SOT3B0                *((volatile unsigned int*)(0x4266C3E0UL))
+#define bFM3_GPIO_EPFR07_SOT3B1                *((volatile unsigned int*)(0x4266C3E4UL))
+#define bFM3_GPIO_EPFR07_SCK3B0                *((volatile unsigned int*)(0x4266C3E8UL))
+#define bFM3_GPIO_EPFR07_SCK3B1                *((volatile unsigned int*)(0x4266C3ECUL))
+#define bFM3_GPIO_EPFR08_RTS4E0                *((volatile unsigned int*)(0x4266C400UL))
+#define bFM3_GPIO_EPFR08_RTS4E1                *((volatile unsigned int*)(0x4266C404UL))
+#define bFM3_GPIO_EPFR08_CTS4S0                *((volatile unsigned int*)(0x4266C408UL))
+#define bFM3_GPIO_EPFR08_CTS4S1                *((volatile unsigned int*)(0x4266C40CUL))
+#define bFM3_GPIO_EPFR08_SIN4S0                *((volatile unsigned int*)(0x4266C410UL))
+#define bFM3_GPIO_EPFR08_SIN4S1                *((volatile unsigned int*)(0x4266C414UL))
+#define bFM3_GPIO_EPFR08_SOT4B0                *((volatile unsigned int*)(0x4266C418UL))
+#define bFM3_GPIO_EPFR08_SOT4B1                *((volatile unsigned int*)(0x4266C41CUL))
+#define bFM3_GPIO_EPFR08_SCK4B0                *((volatile unsigned int*)(0x4266C420UL))
+#define bFM3_GPIO_EPFR08_SCK4B1                *((volatile unsigned int*)(0x4266C424UL))
+#define bFM3_GPIO_EPFR08_SIN5S0                *((volatile unsigned int*)(0x4266C428UL))
+#define bFM3_GPIO_EPFR08_SIN5S1                *((volatile unsigned int*)(0x4266C42CUL))
+#define bFM3_GPIO_EPFR08_SOT5B0                *((volatile unsigned int*)(0x4266C430UL))
+#define bFM3_GPIO_EPFR08_SOT5B1                *((volatile unsigned int*)(0x4266C434UL))
+#define bFM3_GPIO_EPFR08_SCK5B0                *((volatile unsigned int*)(0x4266C438UL))
+#define bFM3_GPIO_EPFR08_SCK5B1                *((volatile unsigned int*)(0x4266C43CUL))
+#define bFM3_GPIO_EPFR08_SIN6S0                *((volatile unsigned int*)(0x4266C440UL))
+#define bFM3_GPIO_EPFR08_SIN6S1                *((volatile unsigned int*)(0x4266C444UL))
+#define bFM3_GPIO_EPFR08_SOT6B0                *((volatile unsigned int*)(0x4266C448UL))
+#define bFM3_GPIO_EPFR08_SOT6B1                *((volatile unsigned int*)(0x4266C44CUL))
+#define bFM3_GPIO_EPFR08_SCK6B0                *((volatile unsigned int*)(0x4266C450UL))
+#define bFM3_GPIO_EPFR08_SCK6B1                *((volatile unsigned int*)(0x4266C454UL))
+#define bFM3_GPIO_EPFR08_SIN7S0                *((volatile unsigned int*)(0x4266C458UL))
+#define bFM3_GPIO_EPFR08_SIN7S1                *((volatile unsigned int*)(0x4266C45CUL))
+#define bFM3_GPIO_EPFR08_SOT7B0                *((volatile unsigned int*)(0x4266C460UL))
+#define bFM3_GPIO_EPFR08_SOT7B1                *((volatile unsigned int*)(0x4266C464UL))
+#define bFM3_GPIO_EPFR08_SCK7B0                *((volatile unsigned int*)(0x4266C468UL))
+#define bFM3_GPIO_EPFR08_SCK7B1                *((volatile unsigned int*)(0x4266C46CUL))
+#define bFM3_GPIO_EPFR09_QAIN0S0               *((volatile unsigned int*)(0x4266C480UL))
+#define bFM3_GPIO_EPFR09_QAIN0S1               *((volatile unsigned int*)(0x4266C484UL))
+#define bFM3_GPIO_EPFR09_QBIN0S0               *((volatile unsigned int*)(0x4266C488UL))
+#define bFM3_GPIO_EPFR09_QBIN0S1               *((volatile unsigned int*)(0x4266C48CUL))
+#define bFM3_GPIO_EPFR09_QZIN0S0               *((volatile unsigned int*)(0x4266C490UL))
+#define bFM3_GPIO_EPFR09_QZIN0S1               *((volatile unsigned int*)(0x4266C494UL))
+#define bFM3_GPIO_EPFR09_QAIN1S0               *((volatile unsigned int*)(0x4266C498UL))
+#define bFM3_GPIO_EPFR09_QAIN1S1               *((volatile unsigned int*)(0x4266C49CUL))
+#define bFM3_GPIO_EPFR09_QBIN1S0               *((volatile unsigned int*)(0x4266C4A0UL))
+#define bFM3_GPIO_EPFR09_QBIN1S1               *((volatile unsigned int*)(0x4266C4A4UL))
+#define bFM3_GPIO_EPFR09_QZIN1S0               *((volatile unsigned int*)(0x4266C4A8UL))
+#define bFM3_GPIO_EPFR09_QZIN1S1               *((volatile unsigned int*)(0x4266C4ACUL))
+#define bFM3_GPIO_EPFR09_ADTRG0S0              *((volatile unsigned int*)(0x4266C4B0UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S1              *((volatile unsigned int*)(0x4266C4B4UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S2              *((volatile unsigned int*)(0x4266C4B8UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S3              *((volatile unsigned int*)(0x4266C4BCUL))
+#define bFM3_GPIO_EPFR09_ADTRG1S0              *((volatile unsigned int*)(0x4266C4C0UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S1              *((volatile unsigned int*)(0x4266C4C4UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S2              *((volatile unsigned int*)(0x4266C4C8UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S3              *((volatile unsigned int*)(0x4266C4CCUL))
+#define bFM3_GPIO_EPFR09_ADTRG2S0              *((volatile unsigned int*)(0x4266C4D0UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S1              *((volatile unsigned int*)(0x4266C4D4UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S2              *((volatile unsigned int*)(0x4266C4D8UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S3              *((volatile unsigned int*)(0x4266C4DCUL))
+#define bFM3_GPIO_EPFR10_UEDEFB                *((volatile unsigned int*)(0x4266C500UL))
+#define bFM3_GPIO_EPFR10_UEDTHB                *((volatile unsigned int*)(0x4266C504UL))
+#define bFM3_GPIO_EPFR10_UECLKE                *((volatile unsigned int*)(0x4266C508UL))
+#define bFM3_GPIO_EPFR10_UEWEXE                *((volatile unsigned int*)(0x4266C50CUL))
+#define bFM3_GPIO_EPFR10_UEDQME                *((volatile unsigned int*)(0x4266C510UL))
+#define bFM3_GPIO_EPFR10_UEOEXE                *((volatile unsigned int*)(0x4266C514UL))
+#define bFM3_GPIO_EPFR10_UEFLSE                *((volatile unsigned int*)(0x4266C518UL))
+#define bFM3_GPIO_EPFR10_UECS1E                *((volatile unsigned int*)(0x4266C51CUL))
+#define bFM3_GPIO_EPFR10_UECS2E                *((volatile unsigned int*)(0x4266C520UL))
+#define bFM3_GPIO_EPFR10_UECS3E                *((volatile unsigned int*)(0x4266C524UL))
+#define bFM3_GPIO_EPFR10_UECS4E                *((volatile unsigned int*)(0x4266C528UL))
+#define bFM3_GPIO_EPFR10_UECS5E                *((volatile unsigned int*)(0x4266C52CUL))
+#define bFM3_GPIO_EPFR10_UECS6E                *((volatile unsigned int*)(0x4266C530UL))
+#define bFM3_GPIO_EPFR10_UECS7E                *((volatile unsigned int*)(0x4266C534UL))
+#define bFM3_GPIO_EPFR10_UEAOOE                *((volatile unsigned int*)(0x4266C538UL))
+#define bFM3_GPIO_EPFR10_UEA08E                *((volatile unsigned int*)(0x4266C53CUL))
+#define bFM3_GPIO_EPFR10_UEA09E                *((volatile unsigned int*)(0x4266C540UL))
+#define bFM3_GPIO_EPFR10_UEA10E                *((volatile unsigned int*)(0x4266C544UL))
+#define bFM3_GPIO_EPFR10_UEA11E                *((volatile unsigned int*)(0x4266C548UL))
+#define bFM3_GPIO_EPFR10_UEA12E                *((volatile unsigned int*)(0x4266C54CUL))
+#define bFM3_GPIO_EPFR10_UEA13E                *((volatile unsigned int*)(0x4266C550UL))
+#define bFM3_GPIO_EPFR10_UEA14E                *((volatile unsigned int*)(0x4266C554UL))
+#define bFM3_GPIO_EPFR10_UEA15E                *((volatile unsigned int*)(0x4266C558UL))
+#define bFM3_GPIO_EPFR10_UEA16E                *((volatile unsigned int*)(0x4266C55CUL))
+#define bFM3_GPIO_EPFR10_UEA17E                *((volatile unsigned int*)(0x4266C560UL))
+#define bFM3_GPIO_EPFR10_UEA18E                *((volatile unsigned int*)(0x4266C564UL))
+#define bFM3_GPIO_EPFR11_UEALEE                *((volatile unsigned int*)(0x4266C580UL))
+#define bFM3_GPIO_EPFR11_UECS0E                *((volatile unsigned int*)(0x4266C584UL))
+#define bFM3_GPIO_EPFR11_UEA01E                *((volatile unsigned int*)(0x4266C588UL))
+#define bFM3_GPIO_EPFR11_UEA02E                *((volatile unsigned int*)(0x4266C58CUL))
+#define bFM3_GPIO_EPFR11_UEA03E                *((volatile unsigned int*)(0x4266C590UL))
+#define bFM3_GPIO_EPFR11_UEA04E                *((volatile unsigned int*)(0x4266C594UL))
+#define bFM3_GPIO_EPFR11_UEA05E                *((volatile unsigned int*)(0x4266C598UL))
+#define bFM3_GPIO_EPFR11_UEA06E                *((volatile unsigned int*)(0x4266C59CUL))
+#define bFM3_GPIO_EPFR11_UEA07E                *((volatile unsigned int*)(0x4266C5A0UL))
+#define bFM3_GPIO_EPFR11_UED00B                *((volatile unsigned int*)(0x4266C5A4UL))
+#define bFM3_GPIO_EPFR11_UED01B                *((volatile unsigned int*)(0x4266C5A8UL))
+#define bFM3_GPIO_EPFR11_UED02B                *((volatile unsigned int*)(0x4266C5ACUL))
+#define bFM3_GPIO_EPFR11_UED03B                *((volatile unsigned int*)(0x4266C5B0UL))
+#define bFM3_GPIO_EPFR11_UED04B                *((volatile unsigned int*)(0x4266C5B4UL))
+#define bFM3_GPIO_EPFR11_UED05B                *((volatile unsigned int*)(0x4266C5B8UL))
+#define bFM3_GPIO_EPFR11_UED06B                *((volatile unsigned int*)(0x4266C5BCUL))
+#define bFM3_GPIO_EPFR11_UED07B                *((volatile unsigned int*)(0x4266C5C0UL))
+#define bFM3_GPIO_EPFR11_UED08B                *((volatile unsigned int*)(0x4266C5C4UL))
+#define bFM3_GPIO_EPFR11_UED09B                *((volatile unsigned int*)(0x4266C5C8UL))
+#define bFM3_GPIO_EPFR11_UED10B                *((volatile unsigned int*)(0x4266C5CCUL))
+#define bFM3_GPIO_EPFR11_UED11B                *((volatile unsigned int*)(0x4266C5D0UL))
+#define bFM3_GPIO_EPFR11_UED12B                *((volatile unsigned int*)(0x4266C5D4UL))
+#define bFM3_GPIO_EPFR11_UED13B                *((volatile unsigned int*)(0x4266C5D8UL))
+#define bFM3_GPIO_EPFR11_UED14B                *((volatile unsigned int*)(0x4266C5DCUL))
+#define bFM3_GPIO_EPFR11_UED15B                *((volatile unsigned int*)(0x4266C5E0UL))
+#define bFM3_GPIO_EPFR11_UERLC                 *((volatile unsigned int*)(0x4266C5E4UL))
+#define bFM3_GPIO_EPFR12_TIOA8E0               *((volatile unsigned int*)(0x4266C608UL))
+#define bFM3_GPIO_EPFR12_TIOA8E1               *((volatile unsigned int*)(0x4266C60CUL))
+#define bFM3_GPIO_EPFR12_TIOB8S0               *((volatile unsigned int*)(0x4266C610UL))
+#define bFM3_GPIO_EPFR12_TIOB8S1               *((volatile unsigned int*)(0x4266C614UL))
+#define bFM3_GPIO_EPFR12_TIOA9S0               *((volatile unsigned int*)(0x4266C620UL))
+#define bFM3_GPIO_EPFR12_TIOA9S1               *((volatile unsigned int*)(0x4266C624UL))
+#define bFM3_GPIO_EPFR12_TIOA9E0               *((volatile unsigned int*)(0x4266C628UL))
+#define bFM3_GPIO_EPFR12_TIOA9E1               *((volatile unsigned int*)(0x4266C62CUL))
+#define bFM3_GPIO_EPFR12_TIOB9S0               *((volatile unsigned int*)(0x4266C630UL))
+#define bFM3_GPIO_EPFR12_TIOB9S1               *((volatile unsigned int*)(0x4266C634UL))
+#define bFM3_GPIO_EPFR12_TIOA10E0              *((volatile unsigned int*)(0x4266C648UL))
+#define bFM3_GPIO_EPFR12_TIOA10E1              *((volatile unsigned int*)(0x4266C64CUL))
+#define bFM3_GPIO_EPFR12_TIOB10S0              *((volatile unsigned int*)(0x4266C650UL))
+#define bFM3_GPIO_EPFR12_TIOB10S1              *((volatile unsigned int*)(0x4266C654UL))
+#define bFM3_GPIO_EPFR12_TIOA11S0              *((volatile unsigned int*)(0x4266C660UL))
+#define bFM3_GPIO_EPFR12_TIOA11S1              *((volatile unsigned int*)(0x4266C664UL))
+#define bFM3_GPIO_EPFR12_TIOA11E0              *((volatile unsigned int*)(0x4266C668UL))
+#define bFM3_GPIO_EPFR12_TIOA11E1              *((volatile unsigned int*)(0x4266C66CUL))
+#define bFM3_GPIO_EPFR12_TIOB11S0              *((volatile unsigned int*)(0x4266C670UL))
+#define bFM3_GPIO_EPFR12_TIOB11S1              *((volatile unsigned int*)(0x4266C674UL))
+#define bFM3_GPIO_EPFR13_TIOA12E0              *((volatile unsigned int*)(0x4266C688UL))
+#define bFM3_GPIO_EPFR13_TIOA12E1              *((volatile unsigned int*)(0x4266C68CUL))
+#define bFM3_GPIO_EPFR13_TIOB12S0              *((volatile unsigned int*)(0x4266C690UL))
+#define bFM3_GPIO_EPFR13_TIOB12S1              *((volatile unsigned int*)(0x4266C694UL))
+#define bFM3_GPIO_EPFR13_TIOA13S0              *((volatile unsigned int*)(0x4266C6A0UL))
+#define bFM3_GPIO_EPFR13_TIOA13S1              *((volatile unsigned int*)(0x4266C6A4UL))
+#define bFM3_GPIO_EPFR13_TIOA13E0              *((volatile unsigned int*)(0x4266C6A8UL))
+#define bFM3_GPIO_EPFR13_TIOA13E1              *((volatile unsigned int*)(0x4266C6ACUL))
+#define bFM3_GPIO_EPFR13_TIOB13S0              *((volatile unsigned int*)(0x4266C6B0UL))
+#define bFM3_GPIO_EPFR13_TIOB13S1              *((volatile unsigned int*)(0x4266C6B4UL))
+#define bFM3_GPIO_EPFR13_TIOA14E0              *((volatile unsigned int*)(0x4266C6C8UL))
+#define bFM3_GPIO_EPFR13_TIOA14E1              *((volatile unsigned int*)(0x4266C6CCUL))
+#define bFM3_GPIO_EPFR13_TIOB14S0              *((volatile unsigned int*)(0x4266C6D0UL))
+#define bFM3_GPIO_EPFR13_TIOB14S1              *((volatile unsigned int*)(0x4266C6D4UL))
+#define bFM3_GPIO_EPFR13_TIOA15S0              *((volatile unsigned int*)(0x4266C6E0UL))
+#define bFM3_GPIO_EPFR13_TIOA15S1              *((volatile unsigned int*)(0x4266C6E4UL))
+#define bFM3_GPIO_EPFR13_TIOA15E0              *((volatile unsigned int*)(0x4266C6E8UL))
+#define bFM3_GPIO_EPFR13_TIOA15E1              *((volatile unsigned int*)(0x4266C6ECUL))
+#define bFM3_GPIO_EPFR13_TIOB15S0              *((volatile unsigned int*)(0x4266C6F0UL))
+#define bFM3_GPIO_EPFR13_TIOB15S1              *((volatile unsigned int*)(0x4266C6F4UL))
+#define bFM3_GPIO_EPFR14_QAIN2S0               *((volatile unsigned int*)(0x4266C700UL))
+#define bFM3_GPIO_EPFR14_QAIN2S1               *((volatile unsigned int*)(0x4266C704UL))
+#define bFM3_GPIO_EPFR14_QBIN2S0               *((volatile unsigned int*)(0x4266C708UL))
+#define bFM3_GPIO_EPFR14_QBIN2S1               *((volatile unsigned int*)(0x4266C70CUL))
+#define bFM3_GPIO_EPFR14_QZIN2S0               *((volatile unsigned int*)(0x4266C710UL))
+#define bFM3_GPIO_EPFR14_QZIN2S1               *((volatile unsigned int*)(0x4266C714UL))
+#define bFM3_GPIO_EPFR14_E_TD0E                *((volatile unsigned int*)(0x4266C748UL))
+#define bFM3_GPIO_EPFR14_E_TD1E                *((volatile unsigned int*)(0x4266C74CUL))
+#define bFM3_GPIO_EPFR14_E_TE0E                *((volatile unsigned int*)(0x4266C750UL))
+#define bFM3_GPIO_EPFR14_E_TE1E                *((volatile unsigned int*)(0x4266C754UL))
+#define bFM3_GPIO_EPFR14_E_MC0E                *((volatile unsigned int*)(0x4266C758UL))
+#define bFM3_GPIO_EPFR14_E_MC1B                *((volatile unsigned int*)(0x4266C75CUL))
+#define bFM3_GPIO_EPFR14_E_MD0B                *((volatile unsigned int*)(0x4266C760UL))
+#define bFM3_GPIO_EPFR14_E_MD1B                *((volatile unsigned int*)(0x4266C764UL))
+#define bFM3_GPIO_EPFR14_E_CKE                 *((volatile unsigned int*)(0x4266C768UL))
+#define bFM3_GPIO_EPFR14_E_PSE                 *((volatile unsigned int*)(0x4266C76CUL))
+#define bFM3_GPIO_EPFR14_E_SPLC0               *((volatile unsigned int*)(0x4266C770UL))
+#define bFM3_GPIO_EPFR14_E_SPLC1               *((volatile unsigned int*)(0x4266C774UL))
+#define bFM3_GPIO_EPFR15_EINT16S0              *((volatile unsigned int*)(0x4266C780UL))
+#define bFM3_GPIO_EPFR15_EINT16S1              *((volatile unsigned int*)(0x4266C784UL))
+#define bFM3_GPIO_EPFR15_EINT17S0              *((volatile unsigned int*)(0x4266C788UL))
+#define bFM3_GPIO_EPFR15_EINT17S1              *((volatile unsigned int*)(0x4266C78CUL))
+#define bFM3_GPIO_EPFR15_EINT18S0              *((volatile unsigned int*)(0x4266C790UL))
+#define bFM3_GPIO_EPFR15_EINT18S1              *((volatile unsigned int*)(0x4266C794UL))
+#define bFM3_GPIO_EPFR15_EINT19S0              *((volatile unsigned int*)(0x4266C798UL))
+#define bFM3_GPIO_EPFR15_EINT19S1              *((volatile unsigned int*)(0x4266C79CUL))
+#define bFM3_GPIO_EPFR15_EINT20S0              *((volatile unsigned int*)(0x4266C7A0UL))
+#define bFM3_GPIO_EPFR15_EINT20S1              *((volatile unsigned int*)(0x4266C7A4UL))
+#define bFM3_GPIO_EPFR15_EINT21S0              *((volatile unsigned int*)(0x4266C7A8UL))
+#define bFM3_GPIO_EPFR15_EINT21S1              *((volatile unsigned int*)(0x4266C7ACUL))
+#define bFM3_GPIO_EPFR15_EINT22S0              *((volatile unsigned int*)(0x4266C7B0UL))
+#define bFM3_GPIO_EPFR15_EINT22S1              *((volatile unsigned int*)(0x4266C7B4UL))
+#define bFM3_GPIO_EPFR15_EINT23S0              *((volatile unsigned int*)(0x4266C7B8UL))
+#define bFM3_GPIO_EPFR15_EINT23S1              *((volatile unsigned int*)(0x4266C7BCUL))
+#define bFM3_GPIO_EPFR15_EINT24S0              *((volatile unsigned int*)(0x4266C7C0UL))
+#define bFM3_GPIO_EPFR15_EINT24S1              *((volatile unsigned int*)(0x4266C7C4UL))
+#define bFM3_GPIO_EPFR15_EINT25S0              *((volatile unsigned int*)(0x4266C7C8UL))
+#define bFM3_GPIO_EPFR15_EINT25S1              *((volatile unsigned int*)(0x4266C7CCUL))
+#define bFM3_GPIO_EPFR15_EINT26S0              *((volatile unsigned int*)(0x4266C7D0UL))
+#define bFM3_GPIO_EPFR15_EINT26S1              *((volatile unsigned int*)(0x4266C7D4UL))
+#define bFM3_GPIO_EPFR15_EINT27S0              *((volatile unsigned int*)(0x4266C7D8UL))
+#define bFM3_GPIO_EPFR15_EINT27S1              *((volatile unsigned int*)(0x4266C7DCUL))
+#define bFM3_GPIO_EPFR15_EINT28S0              *((volatile unsigned int*)(0x4266C7E0UL))
+#define bFM3_GPIO_EPFR15_EINT28S1              *((volatile unsigned int*)(0x4266C7E4UL))
+#define bFM3_GPIO_EPFR15_EINT29S0              *((volatile unsigned int*)(0x4266C7E8UL))
+#define bFM3_GPIO_EPFR15_EINT29S1              *((volatile unsigned int*)(0x4266C7ECUL))
+#define bFM3_GPIO_EPFR15_EINT30S0              *((volatile unsigned int*)(0x4266C7F0UL))
+#define bFM3_GPIO_EPFR15_EINT30S1              *((volatile unsigned int*)(0x4266C7F4UL))
+#define bFM3_GPIO_EPFR15_EINT31S0              *((volatile unsigned int*)(0x4266C7F8UL))
+#define bFM3_GPIO_EPFR15_EINT31S1              *((volatile unsigned int*)(0x4266C7FCUL))
+#define bFM3_GPIO_PZR0_P0                      *((volatile unsigned int*)(0x4266E000UL))
+#define bFM3_GPIO_PZR0_P1                      *((volatile unsigned int*)(0x4266E004UL))
+#define bFM3_GPIO_PZR0_P2                      *((volatile unsigned int*)(0x4266E008UL))
+#define bFM3_GPIO_PZR0_P3                      *((volatile unsigned int*)(0x4266E00CUL))
+#define bFM3_GPIO_PZR0_P4                      *((volatile unsigned int*)(0x4266E010UL))
+#define bFM3_GPIO_PZR0_P5                      *((volatile unsigned int*)(0x4266E014UL))
+#define bFM3_GPIO_PZR0_P6                      *((volatile unsigned int*)(0x4266E018UL))
+#define bFM3_GPIO_PZR0_P7                      *((volatile unsigned int*)(0x4266E01CUL))
+#define bFM3_GPIO_PZR0_P8                      *((volatile unsigned int*)(0x4266E020UL))
+#define bFM3_GPIO_PZR0_P9                      *((volatile unsigned int*)(0x4266E024UL))
+#define bFM3_GPIO_PZR1_P0                      *((volatile unsigned int*)(0x4266E080UL))
+#define bFM3_GPIO_PZR1_P1                      *((volatile unsigned int*)(0x4266E084UL))
+#define bFM3_GPIO_PZR1_P2                      *((volatile unsigned int*)(0x4266E088UL))
+#define bFM3_GPIO_PZR1_P3                      *((volatile unsigned int*)(0x4266E08CUL))
+#define bFM3_GPIO_PZR1_P4                      *((volatile unsigned int*)(0x4266E090UL))
+#define bFM3_GPIO_PZR1_P5                      *((volatile unsigned int*)(0x4266E094UL))
+#define bFM3_GPIO_PZR1_P6                      *((volatile unsigned int*)(0x4266E098UL))
+#define bFM3_GPIO_PZR1_P7                      *((volatile unsigned int*)(0x4266E09CUL))
+#define bFM3_GPIO_PZR1_P8                      *((volatile unsigned int*)(0x4266E0A0UL))
+#define bFM3_GPIO_PZR1_P9                      *((volatile unsigned int*)(0x4266E0A4UL))
+#define bFM3_GPIO_PZR1_PA                      *((volatile unsigned int*)(0x4266E0A8UL))
+#define bFM3_GPIO_PZR1_PB                      *((volatile unsigned int*)(0x4266E0ACUL))
+#define bFM3_GPIO_PZR1_PC                      *((volatile unsigned int*)(0x4266E0B0UL))
+#define bFM3_GPIO_PZR1_PD                      *((volatile unsigned int*)(0x4266E0B4UL))
+#define bFM3_GPIO_PZR1_PE                      *((volatile unsigned int*)(0x4266E0B8UL))
+#define bFM3_GPIO_PZR1_PF                      *((volatile unsigned int*)(0x4266E0BCUL))
+#define bFM3_GPIO_PZR2_P0                      *((volatile unsigned int*)(0x4266E100UL))
+#define bFM3_GPIO_PZR2_P1                      *((volatile unsigned int*)(0x4266E104UL))
+#define bFM3_GPIO_PZR2_P2                      *((volatile unsigned int*)(0x4266E108UL))
+#define bFM3_GPIO_PZR2_P3                      *((volatile unsigned int*)(0x4266E10CUL))
+#define bFM3_GPIO_PZR2_P4                      *((volatile unsigned int*)(0x4266E110UL))
+#define bFM3_GPIO_PZR2_P5                      *((volatile unsigned int*)(0x4266E114UL))
+#define bFM3_GPIO_PZR2_P6                      *((volatile unsigned int*)(0x4266E118UL))
+#define bFM3_GPIO_PZR2_P7                      *((volatile unsigned int*)(0x4266E11CUL))
+#define bFM3_GPIO_PZR2_P8                      *((volatile unsigned int*)(0x4266E120UL))
+#define bFM3_GPIO_PZR2_P9                      *((volatile unsigned int*)(0x4266E124UL))
+#define bFM3_GPIO_PZR3_P6                      *((volatile unsigned int*)(0x4266E198UL))
+#define bFM3_GPIO_PZR3_P7                      *((volatile unsigned int*)(0x4266E19CUL))
+#define bFM3_GPIO_PZR3_P8                      *((volatile unsigned int*)(0x4266E1A0UL))
+#define bFM3_GPIO_PZR3_P9                      *((volatile unsigned int*)(0x4266E1A4UL))
+#define bFM3_GPIO_PZR3_PA                      *((volatile unsigned int*)(0x4266E1A8UL))
+#define bFM3_GPIO_PZR3_PB                      *((volatile unsigned int*)(0x4266E1ACUL))
+#define bFM3_GPIO_PZR3_PC                      *((volatile unsigned int*)(0x4266E1B0UL))
+#define bFM3_GPIO_PZR3_PD                      *((volatile unsigned int*)(0x4266E1B4UL))
+#define bFM3_GPIO_PZR3_PE                      *((volatile unsigned int*)(0x4266E1B8UL))
+#define bFM3_GPIO_PZR3_PF                      *((volatile unsigned int*)(0x4266E1BCUL))
+#define bFM3_GPIO_PZR4_P0                      *((volatile unsigned int*)(0x4266E200UL))
+#define bFM3_GPIO_PZR4_P1                      *((volatile unsigned int*)(0x4266E204UL))
+#define bFM3_GPIO_PZR4_P2                      *((volatile unsigned int*)(0x4266E208UL))
+#define bFM3_GPIO_PZR4_P3                      *((volatile unsigned int*)(0x4266E20CUL))
+#define bFM3_GPIO_PZR4_P4                      *((volatile unsigned int*)(0x4266E210UL))
+#define bFM3_GPIO_PZR4_P5                      *((volatile unsigned int*)(0x4266E214UL))
+#define bFM3_GPIO_PZR4_P6                      *((volatile unsigned int*)(0x4266E218UL))
+#define bFM3_GPIO_PZR4_P7                      *((volatile unsigned int*)(0x4266E21CUL))
+#define bFM3_GPIO_PZR4_P8                      *((volatile unsigned int*)(0x4266E220UL))
+#define bFM3_GPIO_PZR4_P9                      *((volatile unsigned int*)(0x4266E224UL))
+#define bFM3_GPIO_PZR4_PA                      *((volatile unsigned int*)(0x4266E228UL))
+#define bFM3_GPIO_PZR4_PB                      *((volatile unsigned int*)(0x4266E22CUL))
+#define bFM3_GPIO_PZR4_PC                      *((volatile unsigned int*)(0x4266E230UL))
+#define bFM3_GPIO_PZR4_PD                      *((volatile unsigned int*)(0x4266E234UL))
+#define bFM3_GPIO_PZR4_PE                      *((volatile unsigned int*)(0x4266E238UL))
+#define bFM3_GPIO_PZR5_P0                      *((volatile unsigned int*)(0x4266E280UL))
+#define bFM3_GPIO_PZR5_P1                      *((volatile unsigned int*)(0x4266E284UL))
+#define bFM3_GPIO_PZR5_P2                      *((volatile unsigned int*)(0x4266E288UL))
+#define bFM3_GPIO_PZR5_P3                      *((volatile unsigned int*)(0x4266E28CUL))
+#define bFM3_GPIO_PZR5_P4                      *((volatile unsigned int*)(0x4266E290UL))
+#define bFM3_GPIO_PZR5_P5                      *((volatile unsigned int*)(0x4266E294UL))
+#define bFM3_GPIO_PZR5_P6                      *((volatile unsigned int*)(0x4266E298UL))
+#define bFM3_GPIO_PZR5_P7                      *((volatile unsigned int*)(0x4266E29CUL))
+#define bFM3_GPIO_PZR5_P8                      *((volatile unsigned int*)(0x4266E2A0UL))
+#define bFM3_GPIO_PZR5_P9                      *((volatile unsigned int*)(0x4266E2A4UL))
+#define bFM3_GPIO_PZR5_PA                      *((volatile unsigned int*)(0x4266E2A8UL))
+#define bFM3_GPIO_PZR5_PB                      *((volatile unsigned int*)(0x4266E2ACUL))
+#define bFM3_GPIO_PZR6_P0                      *((volatile unsigned int*)(0x4266E300UL))
+#define bFM3_GPIO_PZR6_P1                      *((volatile unsigned int*)(0x4266E304UL))
+#define bFM3_GPIO_PZR6_P2                      *((volatile unsigned int*)(0x4266E308UL))
+#define bFM3_GPIO_PZR7_P0                      *((volatile unsigned int*)(0x4266E380UL))
+#define bFM3_GPIO_PZR7_P1                      *((volatile unsigned int*)(0x4266E384UL))
+#define bFM3_GPIO_PZR7_P2                      *((volatile unsigned int*)(0x4266E388UL))
+#define bFM3_GPIO_PZR7_P3                      *((volatile unsigned int*)(0x4266E38CUL))
+#define bFM3_GPIO_PZR7_P4                      *((volatile unsigned int*)(0x4266E390UL))
+#define bFM3_GPIO_PZR7_P5                      *((volatile unsigned int*)(0x4266E394UL))
+#define bFM3_GPIO_PZR7_P6                      *((volatile unsigned int*)(0x4266E398UL))
+#define bFM3_GPIO_PZR7_P7                      *((volatile unsigned int*)(0x4266E39CUL))
+#define bFM3_GPIO_PZR7_P8                      *((volatile unsigned int*)(0x4266E3A0UL))
+#define bFM3_GPIO_PZR7_P9                      *((volatile unsigned int*)(0x4266E3A4UL))
+#define bFM3_GPIO_PZR7_PA                      *((volatile unsigned int*)(0x4266E3A8UL))
+#define bFM3_GPIO_PZR8_P0                      *((volatile unsigned int*)(0x4266E400UL))
+#define bFM3_GPIO_PZR8_P1                      *((volatile unsigned int*)(0x4266E404UL))
+#define bFM3_GPIO_PZR8_P2                      *((volatile unsigned int*)(0x4266E408UL))
+#define bFM3_GPIO_PZR8_P3                      *((volatile unsigned int*)(0x4266E40CUL))
+#define bFM3_GPIO_PZRA_P0                      *((volatile unsigned int*)(0x4266E500UL))
+#define bFM3_GPIO_PZRA_P1                      *((volatile unsigned int*)(0x4266E504UL))
+#define bFM3_GPIO_PZRA_P2                      *((volatile unsigned int*)(0x4266E508UL))
+#define bFM3_GPIO_PZRA_P3                      *((volatile unsigned int*)(0x4266E50CUL))
+#define bFM3_GPIO_PZRA_P4                      *((volatile unsigned int*)(0x4266E510UL))
+#define bFM3_GPIO_PZRA_P5                      *((volatile unsigned int*)(0x4266E514UL))
+#define bFM3_GPIO_PZRC_P0                      *((volatile unsigned int*)(0x4266E600UL))
+#define bFM3_GPIO_PZRC_P1                      *((volatile unsigned int*)(0x4266E604UL))
+#define bFM3_GPIO_PZRC_P2                      *((volatile unsigned int*)(0x4266E608UL))
+#define bFM3_GPIO_PZRC_P3                      *((volatile unsigned int*)(0x4266E60CUL))
+#define bFM3_GPIO_PZRC_P4                      *((volatile unsigned int*)(0x4266E610UL))
+#define bFM3_GPIO_PZRC_P5                      *((volatile unsigned int*)(0x4266E614UL))
+#define bFM3_GPIO_PZRC_P6                      *((volatile unsigned int*)(0x4266E618UL))
+#define bFM3_GPIO_PZRC_P7                      *((volatile unsigned int*)(0x4266E61CUL))
+#define bFM3_GPIO_PZRC_P8                      *((volatile unsigned int*)(0x4266E620UL))
+#define bFM3_GPIO_PZRC_P9                      *((volatile unsigned int*)(0x4266E624UL))
+#define bFM3_GPIO_PZRC_PA                      *((volatile unsigned int*)(0x4266E628UL))
+#define bFM3_GPIO_PZRC_PB                      *((volatile unsigned int*)(0x4266E62CUL))
+#define bFM3_GPIO_PZRC_PC                      *((volatile unsigned int*)(0x4266E630UL))
+#define bFM3_GPIO_PZRC_PD                      *((volatile unsigned int*)(0x4266E634UL))
+#define bFM3_GPIO_PZRC_PE                      *((volatile unsigned int*)(0x4266E638UL))
+#define bFM3_GPIO_PZRC_PF                      *((volatile unsigned int*)(0x4266E63CUL))
+#define bFM3_GPIO_PZRD_P0                      *((volatile unsigned int*)(0x4266E680UL))
+#define bFM3_GPIO_PZRD_P1                      *((volatile unsigned int*)(0x4266E684UL))
+#define bFM3_GPIO_PZRD_P2                      *((volatile unsigned int*)(0x4266E688UL))
+#define bFM3_GPIO_PZRD_P3                      *((volatile unsigned int*)(0x4266E68CUL))
+#define bFM3_GPIO_PZRE_P0                      *((volatile unsigned int*)(0x4266E700UL))
+#define bFM3_GPIO_PZRE_P2                      *((volatile unsigned int*)(0x4266E708UL))
+#define bFM3_GPIO_PZRE_P3                      *((volatile unsigned int*)(0x4266E70CUL))
+#define bFM3_GPIO_PZRF_P5                      *((volatile unsigned int*)(0x4266E794UL))
+#define bFM3_GPIO_PZRF_P6                      *((volatile unsigned int*)(0x4266E798UL))
+
+/* Low voltage detection registers */
+#define bFM3_LVD_LVD_CTL_SVHI0                 *((volatile unsigned int*)(0x426A0008UL))
+#define bFM3_LVD_LVD_CTL_SVHI1                 *((volatile unsigned int*)(0x426A000CUL))
+#define bFM3_LVD_LVD_CTL_SVHI2                 *((volatile unsigned int*)(0x426A0010UL))
+#define bFM3_LVD_LVD_CTL_SVHI3                 *((volatile unsigned int*)(0x426A0014UL))
+#define bFM3_LVD_LVD_CTL_LVDIE                 *((volatile unsigned int*)(0x426A001CUL))
+#define bFM3_LVD_LVD_STR_LVDIR                 *((volatile unsigned int*)(0x426A009CUL))
+#define bFM3_LVD_LVD_CLR_LVDCL                 *((volatile unsigned int*)(0x426A011CUL))
+#define bFM3_LVD_LVD_STR2_LVDIRDY              *((volatile unsigned int*)(0x426A021CUL))
+
+/* USB clock registers */
+#define bFM3_USBETHERNETCLK_UCCR_UCEN0         *((volatile unsigned int*)(0x426C0000UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL0        *((volatile unsigned int*)(0x426C0004UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL1        *((volatile unsigned int*)(0x426C0008UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCEN1         *((volatile unsigned int*)(0x426C000CUL))
+#define bFM3_USBETHERNETCLK_UCCR_ECEN          *((volatile unsigned int*)(0x426C0010UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL0        *((volatile unsigned int*)(0x426C0014UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL1        *((volatile unsigned int*)(0x426C0018UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN       *((volatile unsigned int*)(0x426C0080UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPINC        *((volatile unsigned int*)(0x426C0084UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0       *((volatile unsigned int*)(0x426C0100UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1       *((volatile unsigned int*)(0x426C0104UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2       *((volatile unsigned int*)(0x426C0108UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0       *((volatile unsigned int*)(0x426C0180UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1       *((volatile unsigned int*)(0x426C0184UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2       *((volatile unsigned int*)(0x426C0188UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3       *((volatile unsigned int*)(0x426C018CUL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4       *((volatile unsigned int*)(0x426C0190UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0       *((volatile unsigned int*)(0x426C0200UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1       *((volatile unsigned int*)(0x426C0204UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2       *((volatile unsigned int*)(0x426C0208UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3       *((volatile unsigned int*)(0x426C020CUL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4       *((volatile unsigned int*)(0x426C0210UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5       *((volatile unsigned int*)(0x426C0214UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6       *((volatile unsigned int*)(0x426C0218UL))
+#define bFM3_USBETHERNETCLK_UP_STR_UPRDY       *((volatile unsigned int*)(0x426C0280UL))
+#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE    *((volatile unsigned int*)(0x426C0300UL))
+#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC    *((volatile unsigned int*)(0x426C0380UL))
+#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI    *((volatile unsigned int*)(0x426C0400UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0       *((volatile unsigned int*)(0x426C0480UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1       *((volatile unsigned int*)(0x426C0484UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2       *((volatile unsigned int*)(0x426C0488UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3       *((volatile unsigned int*)(0x426C048CUL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR0        *((volatile unsigned int*)(0x426C0500UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR1        *((volatile unsigned int*)(0x426C0504UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR2        *((volatile unsigned int*)(0x426C0508UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR3        *((volatile unsigned int*)(0x426C050CUL))
+#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN       *((volatile unsigned int*)(0x426C0580UL))
+#define bFM3_USBETHERNETCLK_USBEN0_USBEN0      *((volatile unsigned int*)(0x426C0600UL))
+#define bFM3_USBETHERNETCLK_USBEN1_USBEN1      *((volatile unsigned int*)(0x426C0680UL))
+
+/* UART asynchronous channel 0 registers */
+#define bFM3_MFS0_UART_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_UART_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_UART_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_UART_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_UART_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_UART_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_UART_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_UART_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_UART_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_UART_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_UART_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_UART_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_UART_ESCR_P                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_UART_ESCR_PEN                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_UART_ESCR_INV                *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_UART_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_UART_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_UART_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_UART_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_UART_SSR_FRE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_UART_SSR_PE                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_UART_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_UART_RDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_TDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_BGR_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_UART_BGR1_EXT                *((volatile unsigned int*)(0x427001BCUL))
+
+/* UART synchronous channel 0 registers */
+#define bFM3_MFS0_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42700004UL))
+#define bFM3_MFS0_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+
+/* UART LIN channel 0 registers */
+#define bFM3_MFS0_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_LIN_SCR_MS                   *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_LIN_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+
+/* I2C channel 0 registers */
+#define bFM3_MFS0_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42700004UL))
+#define bFM3_MFS0_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427000B8UL))
+#define bFM3_MFS0_I2C_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42700200UL))
+#define bFM3_MFS0_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42700204UL))
+#define bFM3_MFS0_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42700208UL))
+#define bFM3_MFS0_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270020CUL))
+#define bFM3_MFS0_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42700210UL))
+#define bFM3_MFS0_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42700214UL))
+#define bFM3_MFS0_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42700218UL))
+#define bFM3_MFS0_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270021CUL))
+#define bFM3_MFS0_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42700220UL))
+#define bFM3_MFS0_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42700224UL))
+#define bFM3_MFS0_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42700228UL))
+#define bFM3_MFS0_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270022CUL))
+#define bFM3_MFS0_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42700230UL))
+#define bFM3_MFS0_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42700234UL))
+#define bFM3_MFS0_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42700238UL))
+#define bFM3_MFS0_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270023CUL))
+
+/* UART asynchronous channel 1 registers */
+#define bFM3_MFS1_UART_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_UART_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_UART_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_UART_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_UART_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_UART_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_UART_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_UART_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_UART_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_UART_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_UART_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_UART_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_UART_ESCR_P                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_UART_ESCR_PEN                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_UART_ESCR_INV                *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_UART_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_UART_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_UART_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_UART_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_UART_SSR_FRE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_UART_SSR_PE                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_UART_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_UART_RDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_TDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_BGR_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_UART_BGR1_EXT                *((volatile unsigned int*)(0x427021BCUL))
+
+/* UART synchronous channel 1 registers */
+#define bFM3_MFS1_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42702004UL))
+#define bFM3_MFS1_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+
+/* UART LIN channel 1 registers */
+#define bFM3_MFS1_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_LIN_SCR_MS                   *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_LIN_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+
+/* I2C channel 1 registers */
+#define bFM3_MFS1_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42702004UL))
+#define bFM3_MFS1_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427020B8UL))
+#define bFM3_MFS1_I2C_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42702200UL))
+#define bFM3_MFS1_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42702204UL))
+#define bFM3_MFS1_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42702208UL))
+#define bFM3_MFS1_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270220CUL))
+#define bFM3_MFS1_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42702210UL))
+#define bFM3_MFS1_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42702214UL))
+#define bFM3_MFS1_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42702218UL))
+#define bFM3_MFS1_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270221CUL))
+#define bFM3_MFS1_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42702220UL))
+#define bFM3_MFS1_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42702224UL))
+#define bFM3_MFS1_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42702228UL))
+#define bFM3_MFS1_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270222CUL))
+#define bFM3_MFS1_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42702230UL))
+#define bFM3_MFS1_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42702234UL))
+#define bFM3_MFS1_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42702238UL))
+#define bFM3_MFS1_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270223CUL))
+
+/* UART asynchronous channel 2 registers */
+#define bFM3_MFS2_UART_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_UART_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_UART_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_UART_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_UART_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_UART_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_UART_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_UART_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_UART_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_UART_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_UART_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_UART_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_UART_ESCR_P                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_UART_ESCR_PEN                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_UART_ESCR_INV                *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_UART_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_UART_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_UART_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_UART_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_UART_SSR_FRE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_UART_SSR_PE                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_UART_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_UART_RDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_TDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_BGR_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_UART_BGR1_EXT                *((volatile unsigned int*)(0x427041BCUL))
+
+/* UART synchronous channel 2 registers */
+#define bFM3_MFS2_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42704004UL))
+#define bFM3_MFS2_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+
+/* UART LIN channel 2 registers */
+#define bFM3_MFS2_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_LIN_SCR_MS                   *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_LIN_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+
+/* I2C channel 2 registers */
+#define bFM3_MFS2_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42704004UL))
+#define bFM3_MFS2_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427040B8UL))
+#define bFM3_MFS2_I2C_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42704200UL))
+#define bFM3_MFS2_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42704204UL))
+#define bFM3_MFS2_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42704208UL))
+#define bFM3_MFS2_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270420CUL))
+#define bFM3_MFS2_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42704210UL))
+#define bFM3_MFS2_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42704214UL))
+#define bFM3_MFS2_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42704218UL))
+#define bFM3_MFS2_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270421CUL))
+#define bFM3_MFS2_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42704220UL))
+#define bFM3_MFS2_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42704224UL))
+#define bFM3_MFS2_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42704228UL))
+#define bFM3_MFS2_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270422CUL))
+#define bFM3_MFS2_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42704230UL))
+#define bFM3_MFS2_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42704234UL))
+#define bFM3_MFS2_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42704238UL))
+#define bFM3_MFS2_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270423CUL))
+
+/* UART asynchronous channel 3 registers */
+#define bFM3_MFS3_UART_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_UART_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_UART_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_UART_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_UART_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_UART_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_UART_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_UART_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_UART_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_UART_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_UART_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_UART_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_UART_ESCR_P                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_UART_ESCR_PEN                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_UART_ESCR_INV                *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_UART_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_UART_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_UART_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_UART_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_UART_SSR_FRE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_UART_SSR_PE                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_UART_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_UART_RDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_TDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_BGR_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_UART_BGR1_EXT                *((volatile unsigned int*)(0x427061BCUL))
+
+/* UART synchronous channel 3 registers */
+#define bFM3_MFS3_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42706004UL))
+#define bFM3_MFS3_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+
+/* UART LIN channel 3 registers */
+#define bFM3_MFS3_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_LIN_SCR_MS                   *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_LIN_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+
+/* I2C channel 3 registers */
+#define bFM3_MFS3_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42706004UL))
+#define bFM3_MFS3_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427060B8UL))
+#define bFM3_MFS3_I2C_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42706200UL))
+#define bFM3_MFS3_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42706204UL))
+#define bFM3_MFS3_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42706208UL))
+#define bFM3_MFS3_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270620CUL))
+#define bFM3_MFS3_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42706210UL))
+#define bFM3_MFS3_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42706214UL))
+#define bFM3_MFS3_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42706218UL))
+#define bFM3_MFS3_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270621CUL))
+#define bFM3_MFS3_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42706220UL))
+#define bFM3_MFS3_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42706224UL))
+#define bFM3_MFS3_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42706228UL))
+#define bFM3_MFS3_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270622CUL))
+#define bFM3_MFS3_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42706230UL))
+#define bFM3_MFS3_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42706234UL))
+#define bFM3_MFS3_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42706238UL))
+#define bFM3_MFS3_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270623CUL))
+
+/* UART asynchronous channel 4 registers */
+#define bFM3_MFS4_UART_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_UART_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_UART_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_UART_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_UART_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_UART_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_UART_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_UART_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_UART_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_UART_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_UART_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_UART_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_UART_ESCR_P                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_UART_ESCR_PEN                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_UART_ESCR_INV                *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_UART_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_UART_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_UART_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_UART_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_UART_SSR_FRE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_UART_SSR_PE                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_UART_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_UART_RDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_TDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_BGR_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_BGR1_EXT                *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART synchronous channel 4 registers */
+#define bFM3_MFS4_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42708004UL))
+#define bFM3_MFS4_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART LIN channel 4 registers */
+#define bFM3_MFS4_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_LIN_SCR_MS                   *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_LIN_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* I2C channel 4 registers */
+#define bFM3_MFS4_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42708004UL))
+#define bFM3_MFS4_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427080B8UL))
+#define bFM3_MFS4_I2C_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42708200UL))
+#define bFM3_MFS4_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42708204UL))
+#define bFM3_MFS4_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42708208UL))
+#define bFM3_MFS4_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270820CUL))
+#define bFM3_MFS4_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42708210UL))
+#define bFM3_MFS4_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42708214UL))
+#define bFM3_MFS4_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42708218UL))
+#define bFM3_MFS4_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270821CUL))
+#define bFM3_MFS4_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42708220UL))
+#define bFM3_MFS4_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42708224UL))
+#define bFM3_MFS4_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42708228UL))
+#define bFM3_MFS4_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270822CUL))
+#define bFM3_MFS4_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42708230UL))
+#define bFM3_MFS4_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42708234UL))
+#define bFM3_MFS4_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42708238UL))
+#define bFM3_MFS4_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270823CUL))
+#define bFM3_MFS4_I2C_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART asynchronous channel 5 registers */
+#define bFM3_MFS5_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_UART_ESCR_P                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_UART_ESCR_INV                *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_UART_SSR_PE                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_UART_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_UART_RDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_TDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART synchronous channel 5 registers */
+#define bFM3_MFS5_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270A004UL))
+#define bFM3_MFS5_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART LIN channel 5 registers */
+#define bFM3_MFS5_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* I2C channel 5 registers */
+#define bFM3_MFS5_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270A004UL))
+#define bFM3_MFS5_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270A0B8UL))
+#define bFM3_MFS5_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270A200UL))
+#define bFM3_MFS5_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270A204UL))
+#define bFM3_MFS5_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270A208UL))
+#define bFM3_MFS5_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270A20CUL))
+#define bFM3_MFS5_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270A210UL))
+#define bFM3_MFS5_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270A214UL))
+#define bFM3_MFS5_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270A218UL))
+#define bFM3_MFS5_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270A21CUL))
+#define bFM3_MFS5_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270A220UL))
+#define bFM3_MFS5_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270A224UL))
+#define bFM3_MFS5_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270A228UL))
+#define bFM3_MFS5_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270A22CUL))
+#define bFM3_MFS5_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270A230UL))
+#define bFM3_MFS5_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270A234UL))
+#define bFM3_MFS5_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270A238UL))
+#define bFM3_MFS5_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270A23CUL))
+#define bFM3_MFS5_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART asynchronous channel 6 registers */
+#define bFM3_MFS6_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_UART_ESCR_P                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_UART_ESCR_INV                *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_UART_SSR_PE                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_UART_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_UART_RDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_TDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART synchronous channel 6 registers */
+#define bFM3_MFS6_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270C004UL))
+#define bFM3_MFS6_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART LIN channel 6 registers */
+#define bFM3_MFS6_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* I2C channel 6 registers */
+#define bFM3_MFS6_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270C004UL))
+#define bFM3_MFS6_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270C0B8UL))
+#define bFM3_MFS6_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270C200UL))
+#define bFM3_MFS6_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270C204UL))
+#define bFM3_MFS6_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270C208UL))
+#define bFM3_MFS6_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270C20CUL))
+#define bFM3_MFS6_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270C210UL))
+#define bFM3_MFS6_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270C214UL))
+#define bFM3_MFS6_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270C218UL))
+#define bFM3_MFS6_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270C21CUL))
+#define bFM3_MFS6_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270C220UL))
+#define bFM3_MFS6_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270C224UL))
+#define bFM3_MFS6_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270C228UL))
+#define bFM3_MFS6_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270C22CUL))
+#define bFM3_MFS6_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270C230UL))
+#define bFM3_MFS6_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270C234UL))
+#define bFM3_MFS6_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270C238UL))
+#define bFM3_MFS6_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270C23CUL))
+#define bFM3_MFS6_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART asynchronous channel 7 registers */
+#define bFM3_MFS7_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_UART_ESCR_P                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_UART_ESCR_INV                *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_UART_SSR_PE                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_UART_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_UART_RDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_TDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART synchronous channel 7 registers */
+#define bFM3_MFS7_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270E004UL))
+#define bFM3_MFS7_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART LIN channel 7 registers */
+#define bFM3_MFS7_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* I2C channel 7 registers */
+#define bFM3_MFS7_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270E004UL))
+#define bFM3_MFS7_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270E0B8UL))
+#define bFM3_MFS7_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270E200UL))
+#define bFM3_MFS7_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270E204UL))
+#define bFM3_MFS7_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270E208UL))
+#define bFM3_MFS7_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270E20CUL))
+#define bFM3_MFS7_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270E210UL))
+#define bFM3_MFS7_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270E214UL))
+#define bFM3_MFS7_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270E218UL))
+#define bFM3_MFS7_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270E21CUL))
+#define bFM3_MFS7_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270E220UL))
+#define bFM3_MFS7_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270E224UL))
+#define bFM3_MFS7_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270E228UL))
+#define bFM3_MFS7_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270E22CUL))
+#define bFM3_MFS7_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270E230UL))
+#define bFM3_MFS7_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270E234UL))
+#define bFM3_MFS7_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270E238UL))
+#define bFM3_MFS7_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270E23CUL))
+#define bFM3_MFS7_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* MFS Noise Filter Control registers */
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF00           *((volatile unsigned int*)(0x42710000UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF01           *((volatile unsigned int*)(0x42710004UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF10           *((volatile unsigned int*)(0x42710008UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF11           *((volatile unsigned int*)(0x4271000CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF20           *((volatile unsigned int*)(0x42710010UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF21           *((volatile unsigned int*)(0x42710014UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF30           *((volatile unsigned int*)(0x42710018UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF31           *((volatile unsigned int*)(0x4271001CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF40           *((volatile unsigned int*)(0x42710020UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF41           *((volatile unsigned int*)(0x42710024UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF50           *((volatile unsigned int*)(0x42710028UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF51           *((volatile unsigned int*)(0x4271002CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF60           *((volatile unsigned int*)(0x42710030UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF61           *((volatile unsigned int*)(0x42710034UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF70           *((volatile unsigned int*)(0x42710038UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF71           *((volatile unsigned int*)(0x4271003CUL))
+
+/* CRC registers */
+#define bFM3_CRC_CRCCR_INIT                    *((volatile unsigned int*)(0x42720000UL))
+#define bFM3_CRC_CRCCR_CRC32                   *((volatile unsigned int*)(0x42720004UL))
+#define bFM3_CRC_CRCCR_LTLEND                  *((volatile unsigned int*)(0x42720008UL))
+#define bFM3_CRC_CRCCR_LSBFST                  *((volatile unsigned int*)(0x4272000CUL))
+#define bFM3_CRC_CRCCR_CRCLTE                  *((volatile unsigned int*)(0x42720010UL))
+#define bFM3_CRC_CRCCR_CRCLSF                  *((volatile unsigned int*)(0x42720014UL))
+#define bFM3_CRC_CRCCR_FXOR                    *((volatile unsigned int*)(0x42720018UL))
+
+/* Watch counter registers */
+#define bFM3_WC_WCRD_CTR0                      *((volatile unsigned int*)(0x42740000UL))
+#define bFM3_WC_WCRD_CTR1                      *((volatile unsigned int*)(0x42740004UL))
+#define bFM3_WC_WCRD_CTR2                      *((volatile unsigned int*)(0x42740008UL))
+#define bFM3_WC_WCRD_CTR3                      *((volatile unsigned int*)(0x4274000CUL))
+#define bFM3_WC_WCRD_CTR4                      *((volatile unsigned int*)(0x42740010UL))
+#define bFM3_WC_WCRD_CTR5                      *((volatile unsigned int*)(0x42740014UL))
+#define bFM3_WC_WCRL_RLC0                      *((volatile unsigned int*)(0x42740020UL))
+#define bFM3_WC_WCRL_RLC1                      *((volatile unsigned int*)(0x42740024UL))
+#define bFM3_WC_WCRL_RLC2                      *((volatile unsigned int*)(0x42740028UL))
+#define bFM3_WC_WCRL_RLC3                      *((volatile unsigned int*)(0x4274002CUL))
+#define bFM3_WC_WCRL_RLC4                      *((volatile unsigned int*)(0x42740030UL))
+#define bFM3_WC_WCRL_RLC5                      *((volatile unsigned int*)(0x42740034UL))
+#define bFM3_WC_WCCR_WCIF                      *((volatile unsigned int*)(0x42740040UL))
+#define bFM3_WC_WCCR_WCIE                      *((volatile unsigned int*)(0x42740044UL))
+#define bFM3_WC_WCCR_CS0                       *((volatile unsigned int*)(0x42740048UL))
+#define bFM3_WC_WCCR_CS1                       *((volatile unsigned int*)(0x4274004CUL))
+#define bFM3_WC_WCCR_WCOP                      *((volatile unsigned int*)(0x42740058UL))
+#define bFM3_WC_WCCR_WCEN                      *((volatile unsigned int*)(0x4274005CUL))
+#define bFM3_WC_CLK_SEL_SEL_IN                 *((volatile unsigned int*)(0x42740200UL))
+#define bFM3_WC_CLK_SEL_SEL_OUT                *((volatile unsigned int*)(0x42740220UL))
+#define bFM3_WC_CLK_EN_CLK_EN                  *((volatile unsigned int*)(0x42740280UL))
+#define bFM3_WC_CLK_EN_CLK_EN_R                *((volatile unsigned int*)(0x42740284UL))
+
+/* External bus interface registers */
+#define bFM3_EXBUS_MODE0_WDTH0                 *((volatile unsigned int*)(0x427E0000UL))
+#define bFM3_EXBUS_MODE0_WDTH1                 *((volatile unsigned int*)(0x427E0004UL))
+#define bFM3_EXBUS_MODE0_RBMON                 *((volatile unsigned int*)(0x427E0008UL))
+#define bFM3_EXBUS_MODE0_WEOFF                 *((volatile unsigned int*)(0x427E000CUL))
+#define bFM3_EXBUS_MODE0_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE0_PAGE                  *((volatile unsigned int*)(0x427E0014UL))
+#define bFM3_EXBUS_MODE0_RDY                   *((volatile unsigned int*)(0x427E0018UL))
+#define bFM3_EXBUS_MODE0_SHRTDOUT              *((volatile unsigned int*)(0x427E001CUL))
+#define bFM3_EXBUS_MODE0_MPXMODE               *((volatile unsigned int*)(0x427E0020UL))
+#define bFM3_EXBUS_MODE0_ALEINV                *((volatile unsigned int*)(0x427E0024UL))
+#define bFM3_EXBUS_MODE0_MPXDOFF               *((volatile unsigned int*)(0x427E002CUL))
+#define bFM3_EXBUS_MODE0_MPXCSOF               *((volatile unsigned int*)(0x427E0030UL))
+#define bFM3_EXBUS_MODE0_MOEXEUP               *((volatile unsigned int*)(0x427E0034UL))
+#define bFM3_EXBUS_MODE1_WDTH0                 *((volatile unsigned int*)(0x427E0080UL))
+#define bFM3_EXBUS_MODE1_WDTH1                 *((volatile unsigned int*)(0x427E0084UL))
+#define bFM3_EXBUS_MODE1_RBMON                 *((volatile unsigned int*)(0x427E0088UL))
+#define bFM3_EXBUS_MODE1_WEOFF                 *((volatile unsigned int*)(0x427E008CUL))
+#define bFM3_EXBUS_MODE1_NAND                  *((volatile unsigned int*)(0x427E0090UL))
+#define bFM3_EXBUS_MODE1_PAGE                  *((volatile unsigned int*)(0x427E0094UL))
+#define bFM3_EXBUS_MODE1_RDY                   *((volatile unsigned int*)(0x427E0098UL))
+#define bFM3_EXBUS_MODE1_SHRTDOUT              *((volatile unsigned int*)(0x427E009CUL))
+#define bFM3_EXBUS_MODE1_MPXMODE               *((volatile unsigned int*)(0x427E00A0UL))
+#define bFM3_EXBUS_MODE1_ALEINV                *((volatile unsigned int*)(0x427E00A4UL))
+#define bFM3_EXBUS_MODE1_MPXDOFF               *((volatile unsigned int*)(0x427E00ACUL))
+#define bFM3_EXBUS_MODE1_MPXCSOF               *((volatile unsigned int*)(0x427E00B0UL))
+#define bFM3_EXBUS_MODE1_MOEXEUP               *((volatile unsigned int*)(0x427E00B4UL))
+#define bFM3_EXBUS_MODE2_WDTH0                 *((volatile unsigned int*)(0x427E0100UL))
+#define bFM3_EXBUS_MODE2_WDTH1                 *((volatile unsigned int*)(0x427E0104UL))
+#define bFM3_EXBUS_MODE2_RBMON                 *((volatile unsigned int*)(0x427E0108UL))
+#define bFM3_EXBUS_MODE2_WEOFF                 *((volatile unsigned int*)(0x427E010CUL))
+#define bFM3_EXBUS_MODE2_NAND                  *((volatile unsigned int*)(0x427E0110UL))
+#define bFM3_EXBUS_MODE2_PAGE                  *((volatile unsigned int*)(0x427E0114UL))
+#define bFM3_EXBUS_MODE2_RDY                   *((volatile unsigned int*)(0x427E0118UL))
+#define bFM3_EXBUS_MODE2_SHRTDOUT              *((volatile unsigned int*)(0x427E011CUL))
+#define bFM3_EXBUS_MODE2_MPXMODE               *((volatile unsigned int*)(0x427E0120UL))
+#define bFM3_EXBUS_MODE2_ALEINV                *((volatile unsigned int*)(0x427E0124UL))
+#define bFM3_EXBUS_MODE2_MPXDOFF               *((volatile unsigned int*)(0x427E012CUL))
+#define bFM3_EXBUS_MODE2_MPXCSOF               *((volatile unsigned int*)(0x427E0130UL))
+#define bFM3_EXBUS_MODE2_MOEXEUP               *((volatile unsigned int*)(0x427E0134UL))
+#define bFM3_EXBUS_MODE3_WDTH0                 *((volatile unsigned int*)(0x427E0180UL))
+#define bFM3_EXBUS_MODE3_WDTH1                 *((volatile unsigned int*)(0x427E0184UL))
+#define bFM3_EXBUS_MODE3_RBMON                 *((volatile unsigned int*)(0x427E0188UL))
+#define bFM3_EXBUS_MODE3_WEOFF                 *((volatile unsigned int*)(0x427E018CUL))
+#define bFM3_EXBUS_MODE3_NAND                  *((volatile unsigned int*)(0x427E0190UL))
+#define bFM3_EXBUS_MODE3_PAGE                  *((volatile unsigned int*)(0x427E0194UL))
+#define bFM3_EXBUS_MODE3_RDY                   *((volatile unsigned int*)(0x427E0198UL))
+#define bFM3_EXBUS_MODE3_SHRTDOUT              *((volatile unsigned int*)(0x427E019CUL))
+#define bFM3_EXBUS_MODE3_MPXMODE               *((volatile unsigned int*)(0x427E01A0UL))
+#define bFM3_EXBUS_MODE3_ALEINV                *((volatile unsigned int*)(0x427E01A4UL))
+#define bFM3_EXBUS_MODE3_MPXDOFF               *((volatile unsigned int*)(0x427E01ACUL))
+#define bFM3_EXBUS_MODE3_MPXCSOF               *((volatile unsigned int*)(0x427E01B0UL))
+#define bFM3_EXBUS_MODE3_MOEXEUP               *((volatile unsigned int*)(0x427E01B4UL))
+#define bFM3_EXBUS_MODE4_WDTH0                 *((volatile unsigned int*)(0x427E0200UL))
+#define bFM3_EXBUS_MODE4_WDTH1                 *((volatile unsigned int*)(0x427E0204UL))
+#define bFM3_EXBUS_MODE4_RBMON                 *((volatile unsigned int*)(0x427E0208UL))
+#define bFM3_EXBUS_MODE4_WEOFF                 *((volatile unsigned int*)(0x427E020CUL))
+#define bFM3_EXBUS_MODE4_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE4_PAGE                  *((volatile unsigned int*)(0x427E0214UL))
+#define bFM3_EXBUS_MODE4_RDY                   *((volatile unsigned int*)(0x427E0218UL))
+#define bFM3_EXBUS_MODE4_SHRTDOUT              *((volatile unsigned int*)(0x427E021CUL))
+#define bFM3_EXBUS_MODE4_MPXMODE               *((volatile unsigned int*)(0x427E0220UL))
+#define bFM3_EXBUS_MODE4_ALEINV                *((volatile unsigned int*)(0x427E0224UL))
+#define bFM3_EXBUS_MODE4_MPXDOFF               *((volatile unsigned int*)(0x427E022CUL))
+#define bFM3_EXBUS_MODE4_MPXCSOF               *((volatile unsigned int*)(0x427E0230UL))
+#define bFM3_EXBUS_MODE4_MOEXEUP               *((volatile unsigned int*)(0x427E0234UL))
+#define bFM3_EXBUS_MODE5_WDTH0                 *((volatile unsigned int*)(0x427E0280UL))
+#define bFM3_EXBUS_MODE5_WDTH1                 *((volatile unsigned int*)(0x427E0284UL))
+#define bFM3_EXBUS_MODE5_RBMON                 *((volatile unsigned int*)(0x427E0288UL))
+#define bFM3_EXBUS_MODE5_WEOFF                 *((volatile unsigned int*)(0x427E028CUL))
+#define bFM3_EXBUS_MODE5_NAND                  *((volatile unsigned int*)(0x427E0290UL))
+#define bFM3_EXBUS_MODE5_PAGE                  *((volatile unsigned int*)(0x427E0294UL))
+#define bFM3_EXBUS_MODE5_RDY                   *((volatile unsigned int*)(0x427E0298UL))
+#define bFM3_EXBUS_MODE5_SHRTDOUT              *((volatile unsigned int*)(0x427E029CUL))
+#define bFM3_EXBUS_MODE5_MPXMODE               *((volatile unsigned int*)(0x427E02A0UL))
+#define bFM3_EXBUS_MODE5_ALEINV                *((volatile unsigned int*)(0x427E02A4UL))
+#define bFM3_EXBUS_MODE5_MPXDOFF               *((volatile unsigned int*)(0x427E02ACUL))
+#define bFM3_EXBUS_MODE5_MPXCSOF               *((volatile unsigned int*)(0x427E02B0UL))
+#define bFM3_EXBUS_MODE5_MOEXEUP               *((volatile unsigned int*)(0x427E02B4UL))
+#define bFM3_EXBUS_MODE6_WDTH0                 *((volatile unsigned int*)(0x427E0300UL))
+#define bFM3_EXBUS_MODE6_WDTH1                 *((volatile unsigned int*)(0x427E0304UL))
+#define bFM3_EXBUS_MODE6_RBMON                 *((volatile unsigned int*)(0x427E0308UL))
+#define bFM3_EXBUS_MODE6_WEOFF                 *((volatile unsigned int*)(0x427E030CUL))
+#define bFM3_EXBUS_MODE6_NAND                  *((volatile unsigned int*)(0x427E0310UL))
+#define bFM3_EXBUS_MODE6_PAGE                  *((volatile unsigned int*)(0x427E0314UL))
+#define bFM3_EXBUS_MODE6_RDY                   *((volatile unsigned int*)(0x427E0318UL))
+#define bFM3_EXBUS_MODE6_SHRTDOUT              *((volatile unsigned int*)(0x427E031CUL))
+#define bFM3_EXBUS_MODE6_MPXMODE               *((volatile unsigned int*)(0x427E0320UL))
+#define bFM3_EXBUS_MODE6_ALEINV                *((volatile unsigned int*)(0x427E0324UL))
+#define bFM3_EXBUS_MODE6_MPXDOFF               *((volatile unsigned int*)(0x427E032CUL))
+#define bFM3_EXBUS_MODE6_MPXCSOF               *((volatile unsigned int*)(0x427E0330UL))
+#define bFM3_EXBUS_MODE6_MOEXEUP               *((volatile unsigned int*)(0x427E0334UL))
+#define bFM3_EXBUS_MODE7_WDTH0                 *((volatile unsigned int*)(0x427E0380UL))
+#define bFM3_EXBUS_MODE7_WDTH1                 *((volatile unsigned int*)(0x427E0384UL))
+#define bFM3_EXBUS_MODE7_RBMON                 *((volatile unsigned int*)(0x427E0388UL))
+#define bFM3_EXBUS_MODE7_WEOFF                 *((volatile unsigned int*)(0x427E038CUL))
+#define bFM3_EXBUS_MODE7_NAND                  *((volatile unsigned int*)(0x427E0390UL))
+#define bFM3_EXBUS_MODE7_PAGE                  *((volatile unsigned int*)(0x427E0394UL))
+#define bFM3_EXBUS_MODE7_RDY                   *((volatile unsigned int*)(0x427E0398UL))
+#define bFM3_EXBUS_MODE7_SHRTDOUT              *((volatile unsigned int*)(0x427E039CUL))
+#define bFM3_EXBUS_MODE7_MPXMODE               *((volatile unsigned int*)(0x427E03A0UL))
+#define bFM3_EXBUS_MODE7_ALEINV                *((volatile unsigned int*)(0x427E03A4UL))
+#define bFM3_EXBUS_MODE7_MPXDOFF               *((volatile unsigned int*)(0x427E03ACUL))
+#define bFM3_EXBUS_MODE7_MPXCSOF               *((volatile unsigned int*)(0x427E03B0UL))
+#define bFM3_EXBUS_MODE7_MOEXEUP               *((volatile unsigned int*)(0x427E03B4UL))
+#define bFM3_EXBUS_TIM0_RACC0                  *((volatile unsigned int*)(0x427E0400UL))
+#define bFM3_EXBUS_TIM0_RACC1                  *((volatile unsigned int*)(0x427E0404UL))
+#define bFM3_EXBUS_TIM0_RACC2                  *((volatile unsigned int*)(0x427E0408UL))
+#define bFM3_EXBUS_TIM0_RACC3                  *((volatile unsigned int*)(0x427E040CUL))
+#define bFM3_EXBUS_TIM0_RADC0                  *((volatile unsigned int*)(0x427E0410UL))
+#define bFM3_EXBUS_TIM0_RADC1                  *((volatile unsigned int*)(0x427E0414UL))
+#define bFM3_EXBUS_TIM0_RADC2                  *((volatile unsigned int*)(0x427E0418UL))
+#define bFM3_EXBUS_TIM0_RADC3                  *((volatile unsigned int*)(0x427E041CUL))
+#define bFM3_EXBUS_TIM0_FRADC0                 *((volatile unsigned int*)(0x427E0420UL))
+#define bFM3_EXBUS_TIM0_FRADC1                 *((volatile unsigned int*)(0x427E0424UL))
+#define bFM3_EXBUS_TIM0_FRADC2                 *((volatile unsigned int*)(0x427E0428UL))
+#define bFM3_EXBUS_TIM0_FRADC3                 *((volatile unsigned int*)(0x427E042CUL))
+#define bFM3_EXBUS_TIM0_RIDLC0                 *((volatile unsigned int*)(0x427E0430UL))
+#define bFM3_EXBUS_TIM0_RIDLC1                 *((volatile unsigned int*)(0x427E0434UL))
+#define bFM3_EXBUS_TIM0_RIDLC2                 *((volatile unsigned int*)(0x427E0438UL))
+#define bFM3_EXBUS_TIM0_RIDLC3                 *((volatile unsigned int*)(0x427E043CUL))
+#define bFM3_EXBUS_TIM0_WACC0                  *((volatile unsigned int*)(0x427E0440UL))
+#define bFM3_EXBUS_TIM0_WACC1                  *((volatile unsigned int*)(0x427E0444UL))
+#define bFM3_EXBUS_TIM0_WACC2                  *((volatile unsigned int*)(0x427E0448UL))
+#define bFM3_EXBUS_TIM0_WACC3                  *((volatile unsigned int*)(0x427E044CUL))
+#define bFM3_EXBUS_TIM0_WADC0                  *((volatile unsigned int*)(0x427E0450UL))
+#define bFM3_EXBUS_TIM0_WADC1                  *((volatile unsigned int*)(0x427E0454UL))
+#define bFM3_EXBUS_TIM0_WADC2                  *((volatile unsigned int*)(0x427E0458UL))
+#define bFM3_EXBUS_TIM0_WADC3                  *((volatile unsigned int*)(0x427E045CUL))
+#define bFM3_EXBUS_TIM0_WWEC0                  *((volatile unsigned int*)(0x427E0460UL))
+#define bFM3_EXBUS_TIM0_WWEC1                  *((volatile unsigned int*)(0x427E0464UL))
+#define bFM3_EXBUS_TIM0_WWEC2                  *((volatile unsigned int*)(0x427E0468UL))
+#define bFM3_EXBUS_TIM0_WWEC3                  *((volatile unsigned int*)(0x427E046CUL))
+#define bFM3_EXBUS_TIM0_WIDLC0                 *((volatile unsigned int*)(0x427E0470UL))
+#define bFM3_EXBUS_TIM0_WIDLC1                 *((volatile unsigned int*)(0x427E0474UL))
+#define bFM3_EXBUS_TIM0_WIDLC2                 *((volatile unsigned int*)(0x427E0478UL))
+#define bFM3_EXBUS_TIM0_WIDLC3                 *((volatile unsigned int*)(0x427E047CUL))
+#define bFM3_EXBUS_TIM1_RACC0                  *((volatile unsigned int*)(0x427E0480UL))
+#define bFM3_EXBUS_TIM1_RACC1                  *((volatile unsigned int*)(0x427E0484UL))
+#define bFM3_EXBUS_TIM1_RACC2                  *((volatile unsigned int*)(0x427E0488UL))
+#define bFM3_EXBUS_TIM1_RACC3                  *((volatile unsigned int*)(0x427E048CUL))
+#define bFM3_EXBUS_TIM1_RADC0                  *((volatile unsigned int*)(0x427E0490UL))
+#define bFM3_EXBUS_TIM1_RADC1                  *((volatile unsigned int*)(0x427E0494UL))
+#define bFM3_EXBUS_TIM1_RADC2                  *((volatile unsigned int*)(0x427E0498UL))
+#define bFM3_EXBUS_TIM1_RADC3                  *((volatile unsigned int*)(0x427E049CUL))
+#define bFM3_EXBUS_TIM1_FRADC0                 *((volatile unsigned int*)(0x427E04A0UL))
+#define bFM3_EXBUS_TIM1_FRADC1                 *((volatile unsigned int*)(0x427E04A4UL))
+#define bFM3_EXBUS_TIM1_FRADC2                 *((volatile unsigned int*)(0x427E04A8UL))
+#define bFM3_EXBUS_TIM1_FRADC3                 *((volatile unsigned int*)(0x427E04ACUL))
+#define bFM3_EXBUS_TIM1_RIDLC0                 *((volatile unsigned int*)(0x427E04B0UL))
+#define bFM3_EXBUS_TIM1_RIDLC1                 *((volatile unsigned int*)(0x427E04B4UL))
+#define bFM3_EXBUS_TIM1_RIDLC2                 *((volatile unsigned int*)(0x427E04B8UL))
+#define bFM3_EXBUS_TIM1_RIDLC3                 *((volatile unsigned int*)(0x427E04BCUL))
+#define bFM3_EXBUS_TIM1_WACC0                  *((volatile unsigned int*)(0x427E04C0UL))
+#define bFM3_EXBUS_TIM1_WACC1                  *((volatile unsigned int*)(0x427E04C4UL))
+#define bFM3_EXBUS_TIM1_WACC2                  *((volatile unsigned int*)(0x427E04C8UL))
+#define bFM3_EXBUS_TIM1_WACC3                  *((volatile unsigned int*)(0x427E04CCUL))
+#define bFM3_EXBUS_TIM1_WADC0                  *((volatile unsigned int*)(0x427E04D0UL))
+#define bFM3_EXBUS_TIM1_WADC1                  *((volatile unsigned int*)(0x427E04D4UL))
+#define bFM3_EXBUS_TIM1_WADC2                  *((volatile unsigned int*)(0x427E04D8UL))
+#define bFM3_EXBUS_TIM1_WADC3                  *((volatile unsigned int*)(0x427E04DCUL))
+#define bFM3_EXBUS_TIM1_WWEC0                  *((volatile unsigned int*)(0x427E04E0UL))
+#define bFM3_EXBUS_TIM1_WWEC1                  *((volatile unsigned int*)(0x427E04E4UL))
+#define bFM3_EXBUS_TIM1_WWEC2                  *((volatile unsigned int*)(0x427E04E8UL))
+#define bFM3_EXBUS_TIM1_WWEC3                  *((volatile unsigned int*)(0x427E04ECUL))
+#define bFM3_EXBUS_TIM1_WIDLC0                 *((volatile unsigned int*)(0x427E04F0UL))
+#define bFM3_EXBUS_TIM1_WIDLC1                 *((volatile unsigned int*)(0x427E04F4UL))
+#define bFM3_EXBUS_TIM1_WIDLC2                 *((volatile unsigned int*)(0x427E04F8UL))
+#define bFM3_EXBUS_TIM1_WIDLC3                 *((volatile unsigned int*)(0x427E04FCUL))
+#define bFM3_EXBUS_TIM2_RACC0                  *((volatile unsigned int*)(0x427E0500UL))
+#define bFM3_EXBUS_TIM2_RACC1                  *((volatile unsigned int*)(0x427E0504UL))
+#define bFM3_EXBUS_TIM2_RACC2                  *((volatile unsigned int*)(0x427E0508UL))
+#define bFM3_EXBUS_TIM2_RACC3                  *((volatile unsigned int*)(0x427E050CUL))
+#define bFM3_EXBUS_TIM2_RADC0                  *((volatile unsigned int*)(0x427E0510UL))
+#define bFM3_EXBUS_TIM2_RADC1                  *((volatile unsigned int*)(0x427E0514UL))
+#define bFM3_EXBUS_TIM2_RADC2                  *((volatile unsigned int*)(0x427E0518UL))
+#define bFM3_EXBUS_TIM2_RADC3                  *((volatile unsigned int*)(0x427E051CUL))
+#define bFM3_EXBUS_TIM2_FRADC0                 *((volatile unsigned int*)(0x427E0520UL))
+#define bFM3_EXBUS_TIM2_FRADC1                 *((volatile unsigned int*)(0x427E0524UL))
+#define bFM3_EXBUS_TIM2_FRADC2                 *((volatile unsigned int*)(0x427E0528UL))
+#define bFM3_EXBUS_TIM2_FRADC3                 *((volatile unsigned int*)(0x427E052CUL))
+#define bFM3_EXBUS_TIM2_RIDLC0                 *((volatile unsigned int*)(0x427E0530UL))
+#define bFM3_EXBUS_TIM2_RIDLC1                 *((volatile unsigned int*)(0x427E0534UL))
+#define bFM3_EXBUS_TIM2_RIDLC2                 *((volatile unsigned int*)(0x427E0538UL))
+#define bFM3_EXBUS_TIM2_RIDLC3                 *((volatile unsigned int*)(0x427E053CUL))
+#define bFM3_EXBUS_TIM2_WACC0                  *((volatile unsigned int*)(0x427E0540UL))
+#define bFM3_EXBUS_TIM2_WACC1                  *((volatile unsigned int*)(0x427E0544UL))
+#define bFM3_EXBUS_TIM2_WACC2                  *((volatile unsigned int*)(0x427E0548UL))
+#define bFM3_EXBUS_TIM2_WACC3                  *((volatile unsigned int*)(0x427E054CUL))
+#define bFM3_EXBUS_TIM2_WADC0                  *((volatile unsigned int*)(0x427E0550UL))
+#define bFM3_EXBUS_TIM2_WADC1                  *((volatile unsigned int*)(0x427E0554UL))
+#define bFM3_EXBUS_TIM2_WADC2                  *((volatile unsigned int*)(0x427E0558UL))
+#define bFM3_EXBUS_TIM2_WADC3                  *((volatile unsigned int*)(0x427E055CUL))
+#define bFM3_EXBUS_TIM2_WWEC0                  *((volatile unsigned int*)(0x427E0560UL))
+#define bFM3_EXBUS_TIM2_WWEC1                  *((volatile unsigned int*)(0x427E0564UL))
+#define bFM3_EXBUS_TIM2_WWEC2                  *((volatile unsigned int*)(0x427E0568UL))
+#define bFM3_EXBUS_TIM2_WWEC3                  *((volatile unsigned int*)(0x427E056CUL))
+#define bFM3_EXBUS_TIM2_WIDLC0                 *((volatile unsigned int*)(0x427E0570UL))
+#define bFM3_EXBUS_TIM2_WIDLC1                 *((volatile unsigned int*)(0x427E0574UL))
+#define bFM3_EXBUS_TIM2_WIDLC2                 *((volatile unsigned int*)(0x427E0578UL))
+#define bFM3_EXBUS_TIM2_WIDLC3                 *((volatile unsigned int*)(0x427E057CUL))
+#define bFM3_EXBUS_TIM3_RACC0                  *((volatile unsigned int*)(0x427E0580UL))
+#define bFM3_EXBUS_TIM3_RACC1                  *((volatile unsigned int*)(0x427E0584UL))
+#define bFM3_EXBUS_TIM3_RACC2                  *((volatile unsigned int*)(0x427E0588UL))
+#define bFM3_EXBUS_TIM3_RACC3                  *((volatile unsigned int*)(0x427E058CUL))
+#define bFM3_EXBUS_TIM3_RADC0                  *((volatile unsigned int*)(0x427E0590UL))
+#define bFM3_EXBUS_TIM3_RADC1                  *((volatile unsigned int*)(0x427E0594UL))
+#define bFM3_EXBUS_TIM3_RADC2                  *((volatile unsigned int*)(0x427E0598UL))
+#define bFM3_EXBUS_TIM3_RADC3                  *((volatile unsigned int*)(0x427E059CUL))
+#define bFM3_EXBUS_TIM3_FRADC0                 *((volatile unsigned int*)(0x427E05A0UL))
+#define bFM3_EXBUS_TIM3_FRADC1                 *((volatile unsigned int*)(0x427E05A4UL))
+#define bFM3_EXBUS_TIM3_FRADC2                 *((volatile unsigned int*)(0x427E05A8UL))
+#define bFM3_EXBUS_TIM3_FRADC3                 *((volatile unsigned int*)(0x427E05ACUL))
+#define bFM3_EXBUS_TIM3_RIDLC0                 *((volatile unsigned int*)(0x427E05B0UL))
+#define bFM3_EXBUS_TIM3_RIDLC1                 *((volatile unsigned int*)(0x427E05B4UL))
+#define bFM3_EXBUS_TIM3_RIDLC2                 *((volatile unsigned int*)(0x427E05B8UL))
+#define bFM3_EXBUS_TIM3_RIDLC3                 *((volatile unsigned int*)(0x427E05BCUL))
+#define bFM3_EXBUS_TIM3_WACC0                  *((volatile unsigned int*)(0x427E05C0UL))
+#define bFM3_EXBUS_TIM3_WACC1                  *((volatile unsigned int*)(0x427E05C4UL))
+#define bFM3_EXBUS_TIM3_WACC2                  *((volatile unsigned int*)(0x427E05C8UL))
+#define bFM3_EXBUS_TIM3_WACC3                  *((volatile unsigned int*)(0x427E05CCUL))
+#define bFM3_EXBUS_TIM3_WADC0                  *((volatile unsigned int*)(0x427E05D0UL))
+#define bFM3_EXBUS_TIM3_WADC1                  *((volatile unsigned int*)(0x427E05D4UL))
+#define bFM3_EXBUS_TIM3_WADC2                  *((volatile unsigned int*)(0x427E05D8UL))
+#define bFM3_EXBUS_TIM3_WADC3                  *((volatile unsigned int*)(0x427E05DCUL))
+#define bFM3_EXBUS_TIM3_WWEC0                  *((volatile unsigned int*)(0x427E05E0UL))
+#define bFM3_EXBUS_TIM3_WWEC1                  *((volatile unsigned int*)(0x427E05E4UL))
+#define bFM3_EXBUS_TIM3_WWEC2                  *((volatile unsigned int*)(0x427E05E8UL))
+#define bFM3_EXBUS_TIM3_WWEC3                  *((volatile unsigned int*)(0x427E05ECUL))
+#define bFM3_EXBUS_TIM3_WIDLC0                 *((volatile unsigned int*)(0x427E05F0UL))
+#define bFM3_EXBUS_TIM3_WIDLC1                 *((volatile unsigned int*)(0x427E05F4UL))
+#define bFM3_EXBUS_TIM3_WIDLC2                 *((volatile unsigned int*)(0x427E05F8UL))
+#define bFM3_EXBUS_TIM3_WIDLC3                 *((volatile unsigned int*)(0x427E05FCUL))
+#define bFM3_EXBUS_TIM4_RACC0                  *((volatile unsigned int*)(0x427E0600UL))
+#define bFM3_EXBUS_TIM4_RACC1                  *((volatile unsigned int*)(0x427E0604UL))
+#define bFM3_EXBUS_TIM4_RACC2                  *((volatile unsigned int*)(0x427E0608UL))
+#define bFM3_EXBUS_TIM4_RACC3                  *((volatile unsigned int*)(0x427E060CUL))
+#define bFM3_EXBUS_TIM4_RADC0                  *((volatile unsigned int*)(0x427E0610UL))
+#define bFM3_EXBUS_TIM4_RADC1                  *((volatile unsigned int*)(0x427E0614UL))
+#define bFM3_EXBUS_TIM4_RADC2                  *((volatile unsigned int*)(0x427E0618UL))
+#define bFM3_EXBUS_TIM4_RADC3                  *((volatile unsigned int*)(0x427E061CUL))
+#define bFM3_EXBUS_TIM4_FRADC0                 *((volatile unsigned int*)(0x427E0620UL))
+#define bFM3_EXBUS_TIM4_FRADC1                 *((volatile unsigned int*)(0x427E0624UL))
+#define bFM3_EXBUS_TIM4_FRADC2                 *((volatile unsigned int*)(0x427E0628UL))
+#define bFM3_EXBUS_TIM4_FRADC3                 *((volatile unsigned int*)(0x427E062CUL))
+#define bFM3_EXBUS_TIM4_RIDLC0                 *((volatile unsigned int*)(0x427E0630UL))
+#define bFM3_EXBUS_TIM4_RIDLC1                 *((volatile unsigned int*)(0x427E0634UL))
+#define bFM3_EXBUS_TIM4_RIDLC2                 *((volatile unsigned int*)(0x427E0638UL))
+#define bFM3_EXBUS_TIM4_RIDLC3                 *((volatile unsigned int*)(0x427E063CUL))
+#define bFM3_EXBUS_TIM4_WACC0                  *((volatile unsigned int*)(0x427E0640UL))
+#define bFM3_EXBUS_TIM4_WACC1                  *((volatile unsigned int*)(0x427E0644UL))
+#define bFM3_EXBUS_TIM4_WACC2                  *((volatile unsigned int*)(0x427E0648UL))
+#define bFM3_EXBUS_TIM4_WACC3                  *((volatile unsigned int*)(0x427E064CUL))
+#define bFM3_EXBUS_TIM4_WADC0                  *((volatile unsigned int*)(0x427E0650UL))
+#define bFM3_EXBUS_TIM4_WADC1                  *((volatile unsigned int*)(0x427E0654UL))
+#define bFM3_EXBUS_TIM4_WADC2                  *((volatile unsigned int*)(0x427E0658UL))
+#define bFM3_EXBUS_TIM4_WADC3                  *((volatile unsigned int*)(0x427E065CUL))
+#define bFM3_EXBUS_TIM4_WWEC0                  *((volatile unsigned int*)(0x427E0660UL))
+#define bFM3_EXBUS_TIM4_WWEC1                  *((volatile unsigned int*)(0x427E0664UL))
+#define bFM3_EXBUS_TIM4_WWEC2                  *((volatile unsigned int*)(0x427E0668UL))
+#define bFM3_EXBUS_TIM4_WWEC3                  *((volatile unsigned int*)(0x427E066CUL))
+#define bFM3_EXBUS_TIM4_WIDLC0                 *((volatile unsigned int*)(0x427E0670UL))
+#define bFM3_EXBUS_TIM4_WIDLC1                 *((volatile unsigned int*)(0x427E0674UL))
+#define bFM3_EXBUS_TIM4_WIDLC2                 *((volatile unsigned int*)(0x427E0678UL))
+#define bFM3_EXBUS_TIM4_WIDLC3                 *((volatile unsigned int*)(0x427E067CUL))
+#define bFM3_EXBUS_TIM5_RACC0                  *((volatile unsigned int*)(0x427E0680UL))
+#define bFM3_EXBUS_TIM5_RACC1                  *((volatile unsigned int*)(0x427E0684UL))
+#define bFM3_EXBUS_TIM5_RACC2                  *((volatile unsigned int*)(0x427E0688UL))
+#define bFM3_EXBUS_TIM5_RACC3                  *((volatile unsigned int*)(0x427E068CUL))
+#define bFM3_EXBUS_TIM5_RADC0                  *((volatile unsigned int*)(0x427E0690UL))
+#define bFM3_EXBUS_TIM5_RADC1                  *((volatile unsigned int*)(0x427E0694UL))
+#define bFM3_EXBUS_TIM5_RADC2                  *((volatile unsigned int*)(0x427E0698UL))
+#define bFM3_EXBUS_TIM5_RADC3                  *((volatile unsigned int*)(0x427E069CUL))
+#define bFM3_EXBUS_TIM5_FRADC0                 *((volatile unsigned int*)(0x427E06A0UL))
+#define bFM3_EXBUS_TIM5_FRADC1                 *((volatile unsigned int*)(0x427E06A4UL))
+#define bFM3_EXBUS_TIM5_FRADC2                 *((volatile unsigned int*)(0x427E06A8UL))
+#define bFM3_EXBUS_TIM5_FRADC3                 *((volatile unsigned int*)(0x427E06ACUL))
+#define bFM3_EXBUS_TIM5_RIDLC0                 *((volatile unsigned int*)(0x427E06B0UL))
+#define bFM3_EXBUS_TIM5_RIDLC1                 *((volatile unsigned int*)(0x427E06B4UL))
+#define bFM3_EXBUS_TIM5_RIDLC2                 *((volatile unsigned int*)(0x427E06B8UL))
+#define bFM3_EXBUS_TIM5_RIDLC3                 *((volatile unsigned int*)(0x427E06BCUL))
+#define bFM3_EXBUS_TIM5_WACC0                  *((volatile unsigned int*)(0x427E06C0UL))
+#define bFM3_EXBUS_TIM5_WACC1                  *((volatile unsigned int*)(0x427E06C4UL))
+#define bFM3_EXBUS_TIM5_WACC2                  *((volatile unsigned int*)(0x427E06C8UL))
+#define bFM3_EXBUS_TIM5_WACC3                  *((volatile unsigned int*)(0x427E06CCUL))
+#define bFM3_EXBUS_TIM5_WADC0                  *((volatile unsigned int*)(0x427E06D0UL))
+#define bFM3_EXBUS_TIM5_WADC1                  *((volatile unsigned int*)(0x427E06D4UL))
+#define bFM3_EXBUS_TIM5_WADC2                  *((volatile unsigned int*)(0x427E06D8UL))
+#define bFM3_EXBUS_TIM5_WADC3                  *((volatile unsigned int*)(0x427E06DCUL))
+#define bFM3_EXBUS_TIM5_WWEC0                  *((volatile unsigned int*)(0x427E06E0UL))
+#define bFM3_EXBUS_TIM5_WWEC1                  *((volatile unsigned int*)(0x427E06E4UL))
+#define bFM3_EXBUS_TIM5_WWEC2                  *((volatile unsigned int*)(0x427E06E8UL))
+#define bFM3_EXBUS_TIM5_WWEC3                  *((volatile unsigned int*)(0x427E06ECUL))
+#define bFM3_EXBUS_TIM5_WIDLC0                 *((volatile unsigned int*)(0x427E06F0UL))
+#define bFM3_EXBUS_TIM5_WIDLC1                 *((volatile unsigned int*)(0x427E06F4UL))
+#define bFM3_EXBUS_TIM5_WIDLC2                 *((volatile unsigned int*)(0x427E06F8UL))
+#define bFM3_EXBUS_TIM5_WIDLC3                 *((volatile unsigned int*)(0x427E06FCUL))
+#define bFM3_EXBUS_TIM6_RACC0                  *((volatile unsigned int*)(0x427E0700UL))
+#define bFM3_EXBUS_TIM6_RACC1                  *((volatile unsigned int*)(0x427E0704UL))
+#define bFM3_EXBUS_TIM6_RACC2                  *((volatile unsigned int*)(0x427E0708UL))
+#define bFM3_EXBUS_TIM6_RACC3                  *((volatile unsigned int*)(0x427E070CUL))
+#define bFM3_EXBUS_TIM6_RADC0                  *((volatile unsigned int*)(0x427E0710UL))
+#define bFM3_EXBUS_TIM6_RADC1                  *((volatile unsigned int*)(0x427E0714UL))
+#define bFM3_EXBUS_TIM6_RADC2                  *((volatile unsigned int*)(0x427E0718UL))
+#define bFM3_EXBUS_TIM6_RADC3                  *((volatile unsigned int*)(0x427E071CUL))
+#define bFM3_EXBUS_TIM6_FRADC0                 *((volatile unsigned int*)(0x427E0720UL))
+#define bFM3_EXBUS_TIM6_FRADC1                 *((volatile unsigned int*)(0x427E0724UL))
+#define bFM3_EXBUS_TIM6_FRADC2                 *((volatile unsigned int*)(0x427E0728UL))
+#define bFM3_EXBUS_TIM6_FRADC3                 *((volatile unsigned int*)(0x427E072CUL))
+#define bFM3_EXBUS_TIM6_RIDLC0                 *((volatile unsigned int*)(0x427E0730UL))
+#define bFM3_EXBUS_TIM6_RIDLC1                 *((volatile unsigned int*)(0x427E0734UL))
+#define bFM3_EXBUS_TIM6_RIDLC2                 *((volatile unsigned int*)(0x427E0738UL))
+#define bFM3_EXBUS_TIM6_RIDLC3                 *((volatile unsigned int*)(0x427E073CUL))
+#define bFM3_EXBUS_TIM6_WACC0                  *((volatile unsigned int*)(0x427E0740UL))
+#define bFM3_EXBUS_TIM6_WACC1                  *((volatile unsigned int*)(0x427E0744UL))
+#define bFM3_EXBUS_TIM6_WACC2                  *((volatile unsigned int*)(0x427E0748UL))
+#define bFM3_EXBUS_TIM6_WACC3                  *((volatile unsigned int*)(0x427E074CUL))
+#define bFM3_EXBUS_TIM6_WADC0                  *((volatile unsigned int*)(0x427E0750UL))
+#define bFM3_EXBUS_TIM6_WADC1                  *((volatile unsigned int*)(0x427E0754UL))
+#define bFM3_EXBUS_TIM6_WADC2                  *((volatile unsigned int*)(0x427E0758UL))
+#define bFM3_EXBUS_TIM6_WADC3                  *((volatile unsigned int*)(0x427E075CUL))
+#define bFM3_EXBUS_TIM6_WWEC0                  *((volatile unsigned int*)(0x427E0760UL))
+#define bFM3_EXBUS_TIM6_WWEC1                  *((volatile unsigned int*)(0x427E0764UL))
+#define bFM3_EXBUS_TIM6_WWEC2                  *((volatile unsigned int*)(0x427E0768UL))
+#define bFM3_EXBUS_TIM6_WWEC3                  *((volatile unsigned int*)(0x427E076CUL))
+#define bFM3_EXBUS_TIM6_WIDLC0                 *((volatile unsigned int*)(0x427E0770UL))
+#define bFM3_EXBUS_TIM6_WIDLC1                 *((volatile unsigned int*)(0x427E0774UL))
+#define bFM3_EXBUS_TIM6_WIDLC2                 *((volatile unsigned int*)(0x427E0778UL))
+#define bFM3_EXBUS_TIM6_WIDLC3                 *((volatile unsigned int*)(0x427E077CUL))
+#define bFM3_EXBUS_TIM7_RACC0                  *((volatile unsigned int*)(0x427E0780UL))
+#define bFM3_EXBUS_TIM7_RACC1                  *((volatile unsigned int*)(0x427E0784UL))
+#define bFM3_EXBUS_TIM7_RACC2                  *((volatile unsigned int*)(0x427E0788UL))
+#define bFM3_EXBUS_TIM7_RACC3                  *((volatile unsigned int*)(0x427E078CUL))
+#define bFM3_EXBUS_TIM7_RADC0                  *((volatile unsigned int*)(0x427E0790UL))
+#define bFM3_EXBUS_TIM7_RADC1                  *((volatile unsigned int*)(0x427E0794UL))
+#define bFM3_EXBUS_TIM7_RADC2                  *((volatile unsigned int*)(0x427E0798UL))
+#define bFM3_EXBUS_TIM7_RADC3                  *((volatile unsigned int*)(0x427E079CUL))
+#define bFM3_EXBUS_TIM7_FRADC0                 *((volatile unsigned int*)(0x427E07A0UL))
+#define bFM3_EXBUS_TIM7_FRADC1                 *((volatile unsigned int*)(0x427E07A4UL))
+#define bFM3_EXBUS_TIM7_FRADC2                 *((volatile unsigned int*)(0x427E07A8UL))
+#define bFM3_EXBUS_TIM7_FRADC3                 *((volatile unsigned int*)(0x427E07ACUL))
+#define bFM3_EXBUS_TIM7_RIDLC0                 *((volatile unsigned int*)(0x427E07B0UL))
+#define bFM3_EXBUS_TIM7_RIDLC1                 *((volatile unsigned int*)(0x427E07B4UL))
+#define bFM3_EXBUS_TIM7_RIDLC2                 *((volatile unsigned int*)(0x427E07B8UL))
+#define bFM3_EXBUS_TIM7_RIDLC3                 *((volatile unsigned int*)(0x427E07BCUL))
+#define bFM3_EXBUS_TIM7_WACC0                  *((volatile unsigned int*)(0x427E07C0UL))
+#define bFM3_EXBUS_TIM7_WACC1                  *((volatile unsigned int*)(0x427E07C4UL))
+#define bFM3_EXBUS_TIM7_WACC2                  *((volatile unsigned int*)(0x427E07C8UL))
+#define bFM3_EXBUS_TIM7_WACC3                  *((volatile unsigned int*)(0x427E07CCUL))
+#define bFM3_EXBUS_TIM7_WADC0                  *((volatile unsigned int*)(0x427E07D0UL))
+#define bFM3_EXBUS_TIM7_WADC1                  *((volatile unsigned int*)(0x427E07D4UL))
+#define bFM3_EXBUS_TIM7_WADC2                  *((volatile unsigned int*)(0x427E07D8UL))
+#define bFM3_EXBUS_TIM7_WADC3                  *((volatile unsigned int*)(0x427E07DCUL))
+#define bFM3_EXBUS_TIM7_WWEC0                  *((volatile unsigned int*)(0x427E07E0UL))
+#define bFM3_EXBUS_TIM7_WWEC1                  *((volatile unsigned int*)(0x427E07E4UL))
+#define bFM3_EXBUS_TIM7_WWEC2                  *((volatile unsigned int*)(0x427E07E8UL))
+#define bFM3_EXBUS_TIM7_WWEC3                  *((volatile unsigned int*)(0x427E07ECUL))
+#define bFM3_EXBUS_TIM7_WIDLC0                 *((volatile unsigned int*)(0x427E07F0UL))
+#define bFM3_EXBUS_TIM7_WIDLC1                 *((volatile unsigned int*)(0x427E07F4UL))
+#define bFM3_EXBUS_TIM7_WIDLC2                 *((volatile unsigned int*)(0x427E07F8UL))
+#define bFM3_EXBUS_TIM7_WIDLC3                 *((volatile unsigned int*)(0x427E07FCUL))
+#define bFM3_EXBUS_AREA0_ADDR0                 *((volatile unsigned int*)(0x427E0800UL))
+#define bFM3_EXBUS_AREA0_ADDR1                 *((volatile unsigned int*)(0x427E0804UL))
+#define bFM3_EXBUS_AREA0_ADDR2                 *((volatile unsigned int*)(0x427E0808UL))
+#define bFM3_EXBUS_AREA0_ADDR3                 *((volatile unsigned int*)(0x427E080CUL))
+#define bFM3_EXBUS_AREA0_ADDR4                 *((volatile unsigned int*)(0x427E0810UL))
+#define bFM3_EXBUS_AREA0_ADDR5                 *((volatile unsigned int*)(0x427E0814UL))
+#define bFM3_EXBUS_AREA0_ADDR6                 *((volatile unsigned int*)(0x427E0818UL))
+#define bFM3_EXBUS_AREA0_ADDR7                 *((volatile unsigned int*)(0x427E081CUL))
+#define bFM3_EXBUS_AREA0_MASK0                 *((volatile unsigned int*)(0x427E0840UL))
+#define bFM3_EXBUS_AREA0_MASK1                 *((volatile unsigned int*)(0x427E0844UL))
+#define bFM3_EXBUS_AREA0_MASK2                 *((volatile unsigned int*)(0x427E0848UL))
+#define bFM3_EXBUS_AREA0_MASK3                 *((volatile unsigned int*)(0x427E084CUL))
+#define bFM3_EXBUS_AREA0_MASK4                 *((volatile unsigned int*)(0x427E0850UL))
+#define bFM3_EXBUS_AREA0_MASK5                 *((volatile unsigned int*)(0x427E0854UL))
+#define bFM3_EXBUS_AREA0_MASK6                 *((volatile unsigned int*)(0x427E0858UL))
+#define bFM3_EXBUS_AREA1_ADDR0                 *((volatile unsigned int*)(0x427E0880UL))
+#define bFM3_EXBUS_AREA1_ADDR1                 *((volatile unsigned int*)(0x427E0884UL))
+#define bFM3_EXBUS_AREA1_ADDR2                 *((volatile unsigned int*)(0x427E0888UL))
+#define bFM3_EXBUS_AREA1_ADDR3                 *((volatile unsigned int*)(0x427E088CUL))
+#define bFM3_EXBUS_AREA1_ADDR4                 *((volatile unsigned int*)(0x427E0890UL))
+#define bFM3_EXBUS_AREA1_ADDR5                 *((volatile unsigned int*)(0x427E0894UL))
+#define bFM3_EXBUS_AREA1_ADDR6                 *((volatile unsigned int*)(0x427E0898UL))
+#define bFM3_EXBUS_AREA1_ADDR7                 *((volatile unsigned int*)(0x427E089CUL))
+#define bFM3_EXBUS_AREA1_MASK0                 *((volatile unsigned int*)(0x427E08C0UL))
+#define bFM3_EXBUS_AREA1_MASK1                 *((volatile unsigned int*)(0x427E08C4UL))
+#define bFM3_EXBUS_AREA1_MASK2                 *((volatile unsigned int*)(0x427E08C8UL))
+#define bFM3_EXBUS_AREA1_MASK3                 *((volatile unsigned int*)(0x427E08CCUL))
+#define bFM3_EXBUS_AREA1_MASK4                 *((volatile unsigned int*)(0x427E08D0UL))
+#define bFM3_EXBUS_AREA1_MASK5                 *((volatile unsigned int*)(0x427E08D4UL))
+#define bFM3_EXBUS_AREA1_MASK6                 *((volatile unsigned int*)(0x427E08D8UL))
+#define bFM3_EXBUS_AREA2_ADDR0                 *((volatile unsigned int*)(0x427E0900UL))
+#define bFM3_EXBUS_AREA2_ADDR1                 *((volatile unsigned int*)(0x427E0904UL))
+#define bFM3_EXBUS_AREA2_ADDR2                 *((volatile unsigned int*)(0x427E0908UL))
+#define bFM3_EXBUS_AREA2_ADDR3                 *((volatile unsigned int*)(0x427E090CUL))
+#define bFM3_EXBUS_AREA2_ADDR4                 *((volatile unsigned int*)(0x427E0910UL))
+#define bFM3_EXBUS_AREA2_ADDR5                 *((volatile unsigned int*)(0x427E0914UL))
+#define bFM3_EXBUS_AREA2_ADDR6                 *((volatile unsigned int*)(0x427E0918UL))
+#define bFM3_EXBUS_AREA2_ADDR7                 *((volatile unsigned int*)(0x427E091CUL))
+#define bFM3_EXBUS_AREA2_MASK0                 *((volatile unsigned int*)(0x427E0940UL))
+#define bFM3_EXBUS_AREA2_MASK1                 *((volatile unsigned int*)(0x427E0944UL))
+#define bFM3_EXBUS_AREA2_MASK2                 *((volatile unsigned int*)(0x427E0948UL))
+#define bFM3_EXBUS_AREA2_MASK3                 *((volatile unsigned int*)(0x427E094CUL))
+#define bFM3_EXBUS_AREA2_MASK4                 *((volatile unsigned int*)(0x427E0950UL))
+#define bFM3_EXBUS_AREA2_MASK5                 *((volatile unsigned int*)(0x427E0954UL))
+#define bFM3_EXBUS_AREA2_MASK6                 *((volatile unsigned int*)(0x427E0958UL))
+#define bFM3_EXBUS_AREA3_ADDR0                 *((volatile unsigned int*)(0x427E0980UL))
+#define bFM3_EXBUS_AREA3_ADDR1                 *((volatile unsigned int*)(0x427E0984UL))
+#define bFM3_EXBUS_AREA3_ADDR2                 *((volatile unsigned int*)(0x427E0988UL))
+#define bFM3_EXBUS_AREA3_ADDR3                 *((volatile unsigned int*)(0x427E098CUL))
+#define bFM3_EXBUS_AREA3_ADDR4                 *((volatile unsigned int*)(0x427E0990UL))
+#define bFM3_EXBUS_AREA3_ADDR5                 *((volatile unsigned int*)(0x427E0994UL))
+#define bFM3_EXBUS_AREA3_ADDR6                 *((volatile unsigned int*)(0x427E0998UL))
+#define bFM3_EXBUS_AREA3_ADDR7                 *((volatile unsigned int*)(0x427E099CUL))
+#define bFM3_EXBUS_AREA3_MASK0                 *((volatile unsigned int*)(0x427E09C0UL))
+#define bFM3_EXBUS_AREA3_MASK1                 *((volatile unsigned int*)(0x427E09C4UL))
+#define bFM3_EXBUS_AREA3_MASK2                 *((volatile unsigned int*)(0x427E09C8UL))
+#define bFM3_EXBUS_AREA3_MASK3                 *((volatile unsigned int*)(0x427E09CCUL))
+#define bFM3_EXBUS_AREA3_MASK4                 *((volatile unsigned int*)(0x427E09D0UL))
+#define bFM3_EXBUS_AREA3_MASK5                 *((volatile unsigned int*)(0x427E09D4UL))
+#define bFM3_EXBUS_AREA3_MASK6                 *((volatile unsigned int*)(0x427E09D8UL))
+#define bFM3_EXBUS_AREA4_ADDR0                 *((volatile unsigned int*)(0x427E0A00UL))
+#define bFM3_EXBUS_AREA4_ADDR1                 *((volatile unsigned int*)(0x427E0A04UL))
+#define bFM3_EXBUS_AREA4_ADDR2                 *((volatile unsigned int*)(0x427E0A08UL))
+#define bFM3_EXBUS_AREA4_ADDR3                 *((volatile unsigned int*)(0x427E0A0CUL))
+#define bFM3_EXBUS_AREA4_ADDR4                 *((volatile unsigned int*)(0x427E0A10UL))
+#define bFM3_EXBUS_AREA4_ADDR5                 *((volatile unsigned int*)(0x427E0A14UL))
+#define bFM3_EXBUS_AREA4_ADDR6                 *((volatile unsigned int*)(0x427E0A18UL))
+#define bFM3_EXBUS_AREA4_ADDR7                 *((volatile unsigned int*)(0x427E0A1CUL))
+#define bFM3_EXBUS_AREA4_MASK0                 *((volatile unsigned int*)(0x427E0A40UL))
+#define bFM3_EXBUS_AREA4_MASK1                 *((volatile unsigned int*)(0x427E0A44UL))
+#define bFM3_EXBUS_AREA4_MASK2                 *((volatile unsigned int*)(0x427E0A48UL))
+#define bFM3_EXBUS_AREA4_MASK3                 *((volatile unsigned int*)(0x427E0A4CUL))
+#define bFM3_EXBUS_AREA4_MASK4                 *((volatile unsigned int*)(0x427E0A50UL))
+#define bFM3_EXBUS_AREA4_MASK5                 *((volatile unsigned int*)(0x427E0A54UL))
+#define bFM3_EXBUS_AREA4_MASK6                 *((volatile unsigned int*)(0x427E0A58UL))
+#define bFM3_EXBUS_AREA5_ADDR0                 *((volatile unsigned int*)(0x427E0A80UL))
+#define bFM3_EXBUS_AREA5_ADDR1                 *((volatile unsigned int*)(0x427E0A84UL))
+#define bFM3_EXBUS_AREA5_ADDR2                 *((volatile unsigned int*)(0x427E0A88UL))
+#define bFM3_EXBUS_AREA5_ADDR3                 *((volatile unsigned int*)(0x427E0A8CUL))
+#define bFM3_EXBUS_AREA5_ADDR4                 *((volatile unsigned int*)(0x427E0A90UL))
+#define bFM3_EXBUS_AREA5_ADDR5                 *((volatile unsigned int*)(0x427E0A94UL))
+#define bFM3_EXBUS_AREA5_ADDR6                 *((volatile unsigned int*)(0x427E0A98UL))
+#define bFM3_EXBUS_AREA5_ADDR7                 *((volatile unsigned int*)(0x427E0A9CUL))
+#define bFM3_EXBUS_AREA5_MASK0                 *((volatile unsigned int*)(0x427E0AC0UL))
+#define bFM3_EXBUS_AREA5_MASK1                 *((volatile unsigned int*)(0x427E0AC4UL))
+#define bFM3_EXBUS_AREA5_MASK2                 *((volatile unsigned int*)(0x427E0AC8UL))
+#define bFM3_EXBUS_AREA5_MASK3                 *((volatile unsigned int*)(0x427E0ACCUL))
+#define bFM3_EXBUS_AREA5_MASK4                 *((volatile unsigned int*)(0x427E0AD0UL))
+#define bFM3_EXBUS_AREA5_MASK5                 *((volatile unsigned int*)(0x427E0AD4UL))
+#define bFM3_EXBUS_AREA5_MASK6                 *((volatile unsigned int*)(0x427E0AD8UL))
+#define bFM3_EXBUS_AREA6_ADDR0                 *((volatile unsigned int*)(0x427E0B00UL))
+#define bFM3_EXBUS_AREA6_ADDR1                 *((volatile unsigned int*)(0x427E0B04UL))
+#define bFM3_EXBUS_AREA6_ADDR2                 *((volatile unsigned int*)(0x427E0B08UL))
+#define bFM3_EXBUS_AREA6_ADDR3                 *((volatile unsigned int*)(0x427E0B0CUL))
+#define bFM3_EXBUS_AREA6_ADDR4                 *((volatile unsigned int*)(0x427E0B10UL))
+#define bFM3_EXBUS_AREA6_ADDR5                 *((volatile unsigned int*)(0x427E0B14UL))
+#define bFM3_EXBUS_AREA6_ADDR6                 *((volatile unsigned int*)(0x427E0B18UL))
+#define bFM3_EXBUS_AREA6_ADDR7                 *((volatile unsigned int*)(0x427E0B1CUL))
+#define bFM3_EXBUS_AREA6_MASK0                 *((volatile unsigned int*)(0x427E0B40UL))
+#define bFM3_EXBUS_AREA6_MASK1                 *((volatile unsigned int*)(0x427E0B44UL))
+#define bFM3_EXBUS_AREA6_MASK2                 *((volatile unsigned int*)(0x427E0B48UL))
+#define bFM3_EXBUS_AREA6_MASK3                 *((volatile unsigned int*)(0x427E0B4CUL))
+#define bFM3_EXBUS_AREA6_MASK4                 *((volatile unsigned int*)(0x427E0B50UL))
+#define bFM3_EXBUS_AREA6_MASK5                 *((volatile unsigned int*)(0x427E0B54UL))
+#define bFM3_EXBUS_AREA6_MASK6                 *((volatile unsigned int*)(0x427E0B58UL))
+#define bFM3_EXBUS_AREA7_ADDR0                 *((volatile unsigned int*)(0x427E0B80UL))
+#define bFM3_EXBUS_AREA7_ADDR1                 *((volatile unsigned int*)(0x427E0B84UL))
+#define bFM3_EXBUS_AREA7_ADDR2                 *((volatile unsigned int*)(0x427E0B88UL))
+#define bFM3_EXBUS_AREA7_ADDR3                 *((volatile unsigned int*)(0x427E0B8CUL))
+#define bFM3_EXBUS_AREA7_ADDR4                 *((volatile unsigned int*)(0x427E0B90UL))
+#define bFM3_EXBUS_AREA7_ADDR5                 *((volatile unsigned int*)(0x427E0B94UL))
+#define bFM3_EXBUS_AREA7_ADDR6                 *((volatile unsigned int*)(0x427E0B98UL))
+#define bFM3_EXBUS_AREA7_ADDR7                 *((volatile unsigned int*)(0x427E0B9CUL))
+#define bFM3_EXBUS_AREA7_MASK0                 *((volatile unsigned int*)(0x427E0BC0UL))
+#define bFM3_EXBUS_AREA7_MASK1                 *((volatile unsigned int*)(0x427E0BC4UL))
+#define bFM3_EXBUS_AREA7_MASK2                 *((volatile unsigned int*)(0x427E0BC8UL))
+#define bFM3_EXBUS_AREA7_MASK3                 *((volatile unsigned int*)(0x427E0BCCUL))
+#define bFM3_EXBUS_AREA7_MASK4                 *((volatile unsigned int*)(0x427E0BD0UL))
+#define bFM3_EXBUS_AREA7_MASK5                 *((volatile unsigned int*)(0x427E0BD4UL))
+#define bFM3_EXBUS_AREA7_MASK6                 *((volatile unsigned int*)(0x427E0BD8UL))
+#define bFM3_EXBUS_ATIM0_ALC0                  *((volatile unsigned int*)(0x427E0C00UL))
+#define bFM3_EXBUS_ATIM0_ALC1                  *((volatile unsigned int*)(0x427E0C04UL))
+#define bFM3_EXBUS_ATIM0_ALC2                  *((volatile unsigned int*)(0x427E0C08UL))
+#define bFM3_EXBUS_ATIM0_ALC3                  *((volatile unsigned int*)(0x427E0C0CUL))
+#define bFM3_EXBUS_ATIM0_ALES0                 *((volatile unsigned int*)(0x427E0C10UL))
+#define bFM3_EXBUS_ATIM0_ALES1                 *((volatile unsigned int*)(0x427E0C14UL))
+#define bFM3_EXBUS_ATIM0_ALES2                 *((volatile unsigned int*)(0x427E0C18UL))
+#define bFM3_EXBUS_ATIM0_ALES3                 *((volatile unsigned int*)(0x427E0C1CUL))
+#define bFM3_EXBUS_ATIM0_ALEW0                 *((volatile unsigned int*)(0x427E0C20UL))
+#define bFM3_EXBUS_ATIM0_ALEW1                 *((volatile unsigned int*)(0x427E0C24UL))
+#define bFM3_EXBUS_ATIM0_ALEW2                 *((volatile unsigned int*)(0x427E0C28UL))
+#define bFM3_EXBUS_ATIM0_ALEW3                 *((volatile unsigned int*)(0x427E0C2CUL))
+#define bFM3_EXBUS_ATIM1_ALC0                  *((volatile unsigned int*)(0x427E0C80UL))
+#define bFM3_EXBUS_ATIM1_ALC1                  *((volatile unsigned int*)(0x427E0C84UL))
+#define bFM3_EXBUS_ATIM1_ALC2                  *((volatile unsigned int*)(0x427E0C88UL))
+#define bFM3_EXBUS_ATIM1_ALC3                  *((volatile unsigned int*)(0x427E0C8CUL))
+#define bFM3_EXBUS_ATIM1_ALES0                 *((volatile unsigned int*)(0x427E0C90UL))
+#define bFM3_EXBUS_ATIM1_ALES1                 *((volatile unsigned int*)(0x427E0C94UL))
+#define bFM3_EXBUS_ATIM1_ALES2                 *((volatile unsigned int*)(0x427E0C98UL))
+#define bFM3_EXBUS_ATIM1_ALES3                 *((volatile unsigned int*)(0x427E0C9CUL))
+#define bFM3_EXBUS_ATIM1_ALEW0                 *((volatile unsigned int*)(0x427E0CA0UL))
+#define bFM3_EXBUS_ATIM1_ALEW1                 *((volatile unsigned int*)(0x427E0CA4UL))
+#define bFM3_EXBUS_ATIM1_ALEW2                 *((volatile unsigned int*)(0x427E0CA8UL))
+#define bFM3_EXBUS_ATIM1_ALEW3                 *((volatile unsigned int*)(0x427E0CACUL))
+#define bFM3_EXBUS_ATIM2_ALC0                  *((volatile unsigned int*)(0x427E0D00UL))
+#define bFM3_EXBUS_ATIM2_ALC1                  *((volatile unsigned int*)(0x427E0D04UL))
+#define bFM3_EXBUS_ATIM2_ALC2                  *((volatile unsigned int*)(0x427E0D08UL))
+#define bFM3_EXBUS_ATIM2_ALC3                  *((volatile unsigned int*)(0x427E0D0CUL))
+#define bFM3_EXBUS_ATIM2_ALES0                 *((volatile unsigned int*)(0x427E0D10UL))
+#define bFM3_EXBUS_ATIM2_ALES1                 *((volatile unsigned int*)(0x427E0D14UL))
+#define bFM3_EXBUS_ATIM2_ALES2                 *((volatile unsigned int*)(0x427E0D18UL))
+#define bFM3_EXBUS_ATIM2_ALES3                 *((volatile unsigned int*)(0x427E0D1CUL))
+#define bFM3_EXBUS_ATIM2_ALEW0                 *((volatile unsigned int*)(0x427E0D20UL))
+#define bFM3_EXBUS_ATIM2_ALEW1                 *((volatile unsigned int*)(0x427E0D24UL))
+#define bFM3_EXBUS_ATIM2_ALEW2                 *((volatile unsigned int*)(0x427E0D28UL))
+#define bFM3_EXBUS_ATIM2_ALEW3                 *((volatile unsigned int*)(0x427E0D2CUL))
+#define bFM3_EXBUS_ATIM3_ALC0                  *((volatile unsigned int*)(0x427E0D80UL))
+#define bFM3_EXBUS_ATIM3_ALC1                  *((volatile unsigned int*)(0x427E0D84UL))
+#define bFM3_EXBUS_ATIM3_ALC2                  *((volatile unsigned int*)(0x427E0D88UL))
+#define bFM3_EXBUS_ATIM3_ALC3                  *((volatile unsigned int*)(0x427E0D8CUL))
+#define bFM3_EXBUS_ATIM3_ALES0                 *((volatile unsigned int*)(0x427E0D90UL))
+#define bFM3_EXBUS_ATIM3_ALES1                 *((volatile unsigned int*)(0x427E0D94UL))
+#define bFM3_EXBUS_ATIM3_ALES2                 *((volatile unsigned int*)(0x427E0D98UL))
+#define bFM3_EXBUS_ATIM3_ALES3                 *((volatile unsigned int*)(0x427E0D9CUL))
+#define bFM3_EXBUS_ATIM3_ALEW0                 *((volatile unsigned int*)(0x427E0DA0UL))
+#define bFM3_EXBUS_ATIM3_ALEW1                 *((volatile unsigned int*)(0x427E0DA4UL))
+#define bFM3_EXBUS_ATIM3_ALEW2                 *((volatile unsigned int*)(0x427E0DA8UL))
+#define bFM3_EXBUS_ATIM3_ALEW3                 *((volatile unsigned int*)(0x427E0DACUL))
+#define bFM3_EXBUS_ATIM4_ALC0                  *((volatile unsigned int*)(0x427E0E00UL))
+#define bFM3_EXBUS_ATIM4_ALC1                  *((volatile unsigned int*)(0x427E0E04UL))
+#define bFM3_EXBUS_ATIM4_ALC2                  *((volatile unsigned int*)(0x427E0E08UL))
+#define bFM3_EXBUS_ATIM4_ALC3                  *((volatile unsigned int*)(0x427E0E0CUL))
+#define bFM3_EXBUS_ATIM4_ALES0                 *((volatile unsigned int*)(0x427E0E10UL))
+#define bFM3_EXBUS_ATIM4_ALES1                 *((volatile unsigned int*)(0x427E0E14UL))
+#define bFM3_EXBUS_ATIM4_ALES2                 *((volatile unsigned int*)(0x427E0E18UL))
+#define bFM3_EXBUS_ATIM4_ALES3                 *((volatile unsigned int*)(0x427E0E1CUL))
+#define bFM3_EXBUS_ATIM4_ALEW0                 *((volatile unsigned int*)(0x427E0E20UL))
+#define bFM3_EXBUS_ATIM4_ALEW1                 *((volatile unsigned int*)(0x427E0E24UL))
+#define bFM3_EXBUS_ATIM4_ALEW2                 *((volatile unsigned int*)(0x427E0E28UL))
+#define bFM3_EXBUS_ATIM4_ALEW3                 *((volatile unsigned int*)(0x427E0E2CUL))
+#define bFM3_EXBUS_ATIM5_ALC0                  *((volatile unsigned int*)(0x427E0E80UL))
+#define bFM3_EXBUS_ATIM5_ALC1                  *((volatile unsigned int*)(0x427E0E84UL))
+#define bFM3_EXBUS_ATIM5_ALC2                  *((volatile unsigned int*)(0x427E0E88UL))
+#define bFM3_EXBUS_ATIM5_ALC3                  *((volatile unsigned int*)(0x427E0E8CUL))
+#define bFM3_EXBUS_ATIM5_ALES0                 *((volatile unsigned int*)(0x427E0E90UL))
+#define bFM3_EXBUS_ATIM5_ALES1                 *((volatile unsigned int*)(0x427E0E94UL))
+#define bFM3_EXBUS_ATIM5_ALES2                 *((volatile unsigned int*)(0x427E0E98UL))
+#define bFM3_EXBUS_ATIM5_ALES3                 *((volatile unsigned int*)(0x427E0E9CUL))
+#define bFM3_EXBUS_ATIM5_ALEW0                 *((volatile unsigned int*)(0x427E0EA0UL))
+#define bFM3_EXBUS_ATIM5_ALEW1                 *((volatile unsigned int*)(0x427E0EA4UL))
+#define bFM3_EXBUS_ATIM5_ALEW2                 *((volatile unsigned int*)(0x427E0EA8UL))
+#define bFM3_EXBUS_ATIM5_ALEW3                 *((volatile unsigned int*)(0x427E0EACUL))
+#define bFM3_EXBUS_ATIM6_ALC0                  *((volatile unsigned int*)(0x427E0F00UL))
+#define bFM3_EXBUS_ATIM6_ALC1                  *((volatile unsigned int*)(0x427E0F04UL))
+#define bFM3_EXBUS_ATIM6_ALC2                  *((volatile unsigned int*)(0x427E0F08UL))
+#define bFM3_EXBUS_ATIM6_ALC3                  *((volatile unsigned int*)(0x427E0F0CUL))
+#define bFM3_EXBUS_ATIM6_ALES0                 *((volatile unsigned int*)(0x427E0F10UL))
+#define bFM3_EXBUS_ATIM6_ALES1                 *((volatile unsigned int*)(0x427E0F14UL))
+#define bFM3_EXBUS_ATIM6_ALES2                 *((volatile unsigned int*)(0x427E0F18UL))
+#define bFM3_EXBUS_ATIM6_ALES3                 *((volatile unsigned int*)(0x427E0F1CUL))
+#define bFM3_EXBUS_ATIM6_ALEW0                 *((volatile unsigned int*)(0x427E0F20UL))
+#define bFM3_EXBUS_ATIM6_ALEW1                 *((volatile unsigned int*)(0x427E0F24UL))
+#define bFM3_EXBUS_ATIM6_ALEW2                 *((volatile unsigned int*)(0x427E0F28UL))
+#define bFM3_EXBUS_ATIM6_ALEW3                 *((volatile unsigned int*)(0x427E0F2CUL))
+#define bFM3_EXBUS_ATIM7_ALC0                  *((volatile unsigned int*)(0x427E0F80UL))
+#define bFM3_EXBUS_ATIM7_ALC1                  *((volatile unsigned int*)(0x427E0F84UL))
+#define bFM3_EXBUS_ATIM7_ALC2                  *((volatile unsigned int*)(0x427E0F88UL))
+#define bFM3_EXBUS_ATIM7_ALC3                  *((volatile unsigned int*)(0x427E0F8CUL))
+#define bFM3_EXBUS_ATIM7_ALES0                 *((volatile unsigned int*)(0x427E0F90UL))
+#define bFM3_EXBUS_ATIM7_ALES1                 *((volatile unsigned int*)(0x427E0F94UL))
+#define bFM3_EXBUS_ATIM7_ALES2                 *((volatile unsigned int*)(0x427E0F98UL))
+#define bFM3_EXBUS_ATIM7_ALES3                 *((volatile unsigned int*)(0x427E0F9CUL))
+#define bFM3_EXBUS_ATIM7_ALEW0                 *((volatile unsigned int*)(0x427E0FA0UL))
+#define bFM3_EXBUS_ATIM7_ALEW1                 *((volatile unsigned int*)(0x427E0FA4UL))
+#define bFM3_EXBUS_ATIM7_ALEW2                 *((volatile unsigned int*)(0x427E0FA8UL))
+#define bFM3_EXBUS_ATIM7_ALEW3                 *((volatile unsigned int*)(0x427E0FACUL))
+#define bFM3_EXBUS_DCLKR_MDIV0                 *((volatile unsigned int*)(0x427E6000UL))
+#define bFM3_EXBUS_DCLKR_MDIV1                 *((volatile unsigned int*)(0x427E6004UL))
+#define bFM3_EXBUS_DCLKR_MDIV2                 *((volatile unsigned int*)(0x427E6008UL))
+#define bFM3_EXBUS_DCLKR_MDIV3                 *((volatile unsigned int*)(0x427E600CUL))
+#define bFM3_EXBUS_DCLKR_MCLKON                *((volatile unsigned int*)(0x427E6010UL))
+
+/* USB channel 0 registers */
+#define bFM3_USB0_HCNT_HOST                    *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT_URST                    *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT_DIRE                    *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT_URIRE                   *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT_RWKIRE                  *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT_RETRY                   *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT_CANCEL                  *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HCNT0_HOST                   *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT0_URST                   *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT0_DIRE                   *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT0_URIRE                  *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT1_RETRY                  *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42842080UL))
+#define bFM3_USB0_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42842084UL))
+#define bFM3_USB0_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42842088UL))
+#define bFM3_USB0_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x4284208CUL))
+#define bFM3_USB0_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42842090UL))
+#define bFM3_USB0_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42842094UL))
+#define bFM3_USB0_HIRQ_TCAN                    *((volatile unsigned int*)(0x4284209CUL))
+#define bFM3_USB0_HERR_HS0                     *((volatile unsigned int*)(0x428420A0UL))
+#define bFM3_USB0_HERR_HS1                     *((volatile unsigned int*)(0x428420A4UL))
+#define bFM3_USB0_HERR_STUFF                   *((volatile unsigned int*)(0x428420A8UL))
+#define bFM3_USB0_HERR_TGERR                   *((volatile unsigned int*)(0x428420ACUL))
+#define bFM3_USB0_HERR_CRC                     *((volatile unsigned int*)(0x428420B0UL))
+#define bFM3_USB0_HERR_TOUT                    *((volatile unsigned int*)(0x428420B4UL))
+#define bFM3_USB0_HERR_RERR                    *((volatile unsigned int*)(0x428420B8UL))
+#define bFM3_USB0_HERR_LSTOF                   *((volatile unsigned int*)(0x428420BCUL))
+#define bFM3_USB0_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42842100UL))
+#define bFM3_USB0_HSTATE_TMODE                 *((volatile unsigned int*)(0x42842104UL))
+#define bFM3_USB0_HSTATE_SUSP                  *((volatile unsigned int*)(0x42842108UL))
+#define bFM3_USB0_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x4284210CUL))
+#define bFM3_USB0_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42842110UL))
+#define bFM3_USB0_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42842114UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42842120UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42842124UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42842128UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x4284212CUL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42842130UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42842134UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42842138UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x4284213CUL))
+#define bFM3_USB0_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42842200UL))
+#define bFM3_USB0_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42842204UL))
+#define bFM3_USB0_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42842208UL))
+#define bFM3_USB0_HADR_ADDRESS0                *((volatile unsigned int*)(0x42842220UL))
+#define bFM3_USB0_HADR_ADDRESS1                *((volatile unsigned int*)(0x42842224UL))
+#define bFM3_USB0_HADR_ADDRESS2                *((volatile unsigned int*)(0x42842228UL))
+#define bFM3_USB0_HADR_ADDRESS3                *((volatile unsigned int*)(0x4284222CUL))
+#define bFM3_USB0_HADR_ADDRESS4                *((volatile unsigned int*)(0x42842230UL))
+#define bFM3_USB0_HADR_ADDRESS5                *((volatile unsigned int*)(0x42842234UL))
+#define bFM3_USB0_HADR_ADDRESS6                *((volatile unsigned int*)(0x42842238UL))
+#define bFM3_USB0_HEOF_EOF0                    *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF_EOF1                    *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF_EOF2                    *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF_EOF3                    *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF_EOF4                    *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF_EOF5                    *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF_EOF6                    *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF_EOF7                    *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF_EOF8                    *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF_EOF9                    *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF_EOF10                   *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF_EOF11                   *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF_EOF12                   *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF_EOF13                   *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HEOF_EOF14                   *((volatile unsigned int*)(0x428422B8UL))
+#define bFM3_USB0_HEOF_EOF15                   *((volatile unsigned int*)(0x428422BCUL))
+#define bFM3_USB0_HEOF0_EOF00                  *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF0_EOF01                  *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF0_EOF02                  *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF0_EOF03                  *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF0_EOF04                  *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF0_EOF05                  *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF0_EOF06                  *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF0_EOF07                  *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF1_EOF10                  *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF1_EOF11                  *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF1_EOF12                  *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF1_EOF13                  *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF1_EOF14                  *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF1_EOF15                  *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HFRAME_FRAME0                *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME_FRAME1                *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME_FRAME2                *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME_FRAME3                *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME_FRAME4                *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME_FRAME5                *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME_FRAME6                *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME_FRAME7                *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME_FRAME8                *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME_FRAME9                *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME_FRAME10               *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME0_FRAME03              *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME0_FRAME07              *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME1_FRAME13              *((volatile unsigned int*)(0x4284232CUL))
+#define bFM3_USB0_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42842380UL))
+#define bFM3_USB0_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42842384UL))
+#define bFM3_USB0_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42842388UL))
+#define bFM3_USB0_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x4284238CUL))
+#define bFM3_USB0_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42842390UL))
+#define bFM3_USB0_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42842394UL))
+#define bFM3_USB0_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42842398UL))
+#define bFM3_USB0_HTOKEN_TGGL                  *((volatile unsigned int*)(0x4284239CUL))
+#define bFM3_USB0_UDCC_PWC                     *((volatile unsigned int*)(0x42842400UL))
+#define bFM3_USB0_UDCC_RFBK                    *((volatile unsigned int*)(0x42842404UL))
+#define bFM3_USB0_UDCC_STALCLREN               *((volatile unsigned int*)(0x4284240CUL))
+#define bFM3_USB0_UDCC_USTP                    *((volatile unsigned int*)(0x42842410UL))
+#define bFM3_USB0_UDCC_HCONX                   *((volatile unsigned int*)(0x42842414UL))
+#define bFM3_USB0_UDCC_RESUM                   *((volatile unsigned int*)(0x42842418UL))
+#define bFM3_USB0_UDCC_RST                     *((volatile unsigned int*)(0x4284241CUL))
+#define bFM3_USB0_EP0C_PKS00                   *((volatile unsigned int*)(0x42842480UL))
+#define bFM3_USB0_EP0C_PKS01                   *((volatile unsigned int*)(0x42842484UL))
+#define bFM3_USB0_EP0C_PKS02                   *((volatile unsigned int*)(0x42842488UL))
+#define bFM3_USB0_EP0C_PKS03                   *((volatile unsigned int*)(0x4284248CUL))
+#define bFM3_USB0_EP0C_PKS04                   *((volatile unsigned int*)(0x42842490UL))
+#define bFM3_USB0_EP0C_PKS05                   *((volatile unsigned int*)(0x42842494UL))
+#define bFM3_USB0_EP0C_PKS06                   *((volatile unsigned int*)(0x42842498UL))
+#define bFM3_USB0_EP0C_STAL                    *((volatile unsigned int*)(0x428424A4UL))
+#define bFM3_USB0_EP1C_PKS10                   *((volatile unsigned int*)(0x42842500UL))
+#define bFM3_USB0_EP1C_PKS11                   *((volatile unsigned int*)(0x42842504UL))
+#define bFM3_USB0_EP1C_PKS12                   *((volatile unsigned int*)(0x42842508UL))
+#define bFM3_USB0_EP1C_PKS13                   *((volatile unsigned int*)(0x4284250CUL))
+#define bFM3_USB0_EP1C_PKS14                   *((volatile unsigned int*)(0x42842510UL))
+#define bFM3_USB0_EP1C_PKS15                   *((volatile unsigned int*)(0x42842514UL))
+#define bFM3_USB0_EP1C_PKS16                   *((volatile unsigned int*)(0x42842518UL))
+#define bFM3_USB0_EP1C_PKS17                   *((volatile unsigned int*)(0x4284251CUL))
+#define bFM3_USB0_EP1C_PKS18                   *((volatile unsigned int*)(0x42842520UL))
+#define bFM3_USB0_EP1C_STAL                    *((volatile unsigned int*)(0x42842524UL))
+#define bFM3_USB0_EP1C_NULE                    *((volatile unsigned int*)(0x42842528UL))
+#define bFM3_USB0_EP1C_DMAE                    *((volatile unsigned int*)(0x4284252CUL))
+#define bFM3_USB0_EP1C_DIR                     *((volatile unsigned int*)(0x42842530UL))
+#define bFM3_USB0_EP1C_TYPE0                   *((volatile unsigned int*)(0x42842534UL))
+#define bFM3_USB0_EP1C_TYPE1                   *((volatile unsigned int*)(0x42842538UL))
+#define bFM3_USB0_EP1C_EPEN                    *((volatile unsigned int*)(0x4284253CUL))
+#define bFM3_USB0_EP2C_PKS20                   *((volatile unsigned int*)(0x42842580UL))
+#define bFM3_USB0_EP2C_PKS21                   *((volatile unsigned int*)(0x42842584UL))
+#define bFM3_USB0_EP2C_PKS22                   *((volatile unsigned int*)(0x42842588UL))
+#define bFM3_USB0_EP2C_PKS23                   *((volatile unsigned int*)(0x4284258CUL))
+#define bFM3_USB0_EP2C_PKS24                   *((volatile unsigned int*)(0x42842590UL))
+#define bFM3_USB0_EP2C_PKS25                   *((volatile unsigned int*)(0x42842594UL))
+#define bFM3_USB0_EP2C_PKS26                   *((volatile unsigned int*)(0x42842598UL))
+#define bFM3_USB0_EP2C_STAL                    *((volatile unsigned int*)(0x428425A4UL))
+#define bFM3_USB0_EP2C_NULE                    *((volatile unsigned int*)(0x428425A8UL))
+#define bFM3_USB0_EP2C_DMAE                    *((volatile unsigned int*)(0x428425ACUL))
+#define bFM3_USB0_EP2C_DIR                     *((volatile unsigned int*)(0x428425B0UL))
+#define bFM3_USB0_EP2C_TYPE0                   *((volatile unsigned int*)(0x428425B4UL))
+#define bFM3_USB0_EP2C_TYPE1                   *((volatile unsigned int*)(0x428425B8UL))
+#define bFM3_USB0_EP2C_EPEN                    *((volatile unsigned int*)(0x428425BCUL))
+#define bFM3_USB0_EP3C_PKS30                   *((volatile unsigned int*)(0x42842600UL))
+#define bFM3_USB0_EP3C_PKS31                   *((volatile unsigned int*)(0x42842604UL))
+#define bFM3_USB0_EP3C_PKS32                   *((volatile unsigned int*)(0x42842608UL))
+#define bFM3_USB0_EP3C_PKS33                   *((volatile unsigned int*)(0x4284260CUL))
+#define bFM3_USB0_EP3C_PKS34                   *((volatile unsigned int*)(0x42842610UL))
+#define bFM3_USB0_EP3C_PKS35                   *((volatile unsigned int*)(0x42842614UL))
+#define bFM3_USB0_EP3C_PKS36                   *((volatile unsigned int*)(0x42842618UL))
+#define bFM3_USB0_EP3C_STAL                    *((volatile unsigned int*)(0x42842624UL))
+#define bFM3_USB0_EP3C_NULE                    *((volatile unsigned int*)(0x42842628UL))
+#define bFM3_USB0_EP3C_DMAE                    *((volatile unsigned int*)(0x4284262CUL))
+#define bFM3_USB0_EP3C_DIR                     *((volatile unsigned int*)(0x42842630UL))
+#define bFM3_USB0_EP3C_TYPE0                   *((volatile unsigned int*)(0x42842634UL))
+#define bFM3_USB0_EP3C_TYPE1                   *((volatile unsigned int*)(0x42842638UL))
+#define bFM3_USB0_EP3C_EPEN                    *((volatile unsigned int*)(0x4284263CUL))
+#define bFM3_USB0_EP4C_PKS40                   *((volatile unsigned int*)(0x42842680UL))
+#define bFM3_USB0_EP4C_PKS41                   *((volatile unsigned int*)(0x42842684UL))
+#define bFM3_USB0_EP4C_PKS42                   *((volatile unsigned int*)(0x42842688UL))
+#define bFM3_USB0_EP4C_PKS43                   *((volatile unsigned int*)(0x4284268CUL))
+#define bFM3_USB0_EP4C_PKS44                   *((volatile unsigned int*)(0x42842690UL))
+#define bFM3_USB0_EP4C_PKS45                   *((volatile unsigned int*)(0x42842694UL))
+#define bFM3_USB0_EP4C_PKS46                   *((volatile unsigned int*)(0x42842698UL))
+#define bFM3_USB0_EP4C_STAL                    *((volatile unsigned int*)(0x428426A4UL))
+#define bFM3_USB0_EP4C_NULE                    *((volatile unsigned int*)(0x428426A8UL))
+#define bFM3_USB0_EP4C_DMAE                    *((volatile unsigned int*)(0x428426ACUL))
+#define bFM3_USB0_EP4C_DIR                     *((volatile unsigned int*)(0x428426B0UL))
+#define bFM3_USB0_EP4C_TYPE0                   *((volatile unsigned int*)(0x428426B4UL))
+#define bFM3_USB0_EP4C_TYPE1                   *((volatile unsigned int*)(0x428426B8UL))
+#define bFM3_USB0_EP4C_EPEN                    *((volatile unsigned int*)(0x428426BCUL))
+#define bFM3_USB0_EP5C_PKS50                   *((volatile unsigned int*)(0x42842700UL))
+#define bFM3_USB0_EP5C_PKS51                   *((volatile unsigned int*)(0x42842704UL))
+#define bFM3_USB0_EP5C_PKS52                   *((volatile unsigned int*)(0x42842708UL))
+#define bFM3_USB0_EP5C_PKS53                   *((volatile unsigned int*)(0x4284270CUL))
+#define bFM3_USB0_EP5C_PKS54                   *((volatile unsigned int*)(0x42842710UL))
+#define bFM3_USB0_EP5C_PKS55                   *((volatile unsigned int*)(0x42842714UL))
+#define bFM3_USB0_EP5C_PKS56                   *((volatile unsigned int*)(0x42842718UL))
+#define bFM3_USB0_EP5C_STAL                    *((volatile unsigned int*)(0x42842724UL))
+#define bFM3_USB0_EP5C_NULE                    *((volatile unsigned int*)(0x42842728UL))
+#define bFM3_USB0_EP5C_DMAE                    *((volatile unsigned int*)(0x4284272CUL))
+#define bFM3_USB0_EP5C_DIR                     *((volatile unsigned int*)(0x42842730UL))
+#define bFM3_USB0_EP5C_TYPE0                   *((volatile unsigned int*)(0x42842734UL))
+#define bFM3_USB0_EP5C_TYPE1                   *((volatile unsigned int*)(0x42842738UL))
+#define bFM3_USB0_EP5C_EPEN                    *((volatile unsigned int*)(0x4284273CUL))
+#define bFM3_USB0_TMSP_TMSP0                   *((volatile unsigned int*)(0x42842780UL))
+#define bFM3_USB0_TMSP_TMSP1                   *((volatile unsigned int*)(0x42842784UL))
+#define bFM3_USB0_TMSP_TMSP2                   *((volatile unsigned int*)(0x42842788UL))
+#define bFM3_USB0_TMSP_TMSP3                   *((volatile unsigned int*)(0x4284278CUL))
+#define bFM3_USB0_TMSP_TMSP4                   *((volatile unsigned int*)(0x42842790UL))
+#define bFM3_USB0_TMSP_TMSP5                   *((volatile unsigned int*)(0x42842794UL))
+#define bFM3_USB0_TMSP_TMSP6                   *((volatile unsigned int*)(0x42842798UL))
+#define bFM3_USB0_TMSP_TMSP7                   *((volatile unsigned int*)(0x4284279CUL))
+#define bFM3_USB0_TMSP_TMSP8                   *((volatile unsigned int*)(0x428427A0UL))
+#define bFM3_USB0_TMSP_TMSP9                   *((volatile unsigned int*)(0x428427A4UL))
+#define bFM3_USB0_TMSP_TMSP10                  *((volatile unsigned int*)(0x428427A8UL))
+#define bFM3_USB0_UDCS_CONF                    *((volatile unsigned int*)(0x42842800UL))
+#define bFM3_USB0_UDCS_SETP                    *((volatile unsigned int*)(0x42842804UL))
+#define bFM3_USB0_UDCS_WKUP                    *((volatile unsigned int*)(0x42842808UL))
+#define bFM3_USB0_UDCS_BRST                    *((volatile unsigned int*)(0x4284280CUL))
+#define bFM3_USB0_UDCS_SOF                     *((volatile unsigned int*)(0x42842810UL))
+#define bFM3_USB0_UDCS_SUSP                    *((volatile unsigned int*)(0x42842814UL))
+#define bFM3_USB0_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42842820UL))
+#define bFM3_USB0_UDCIE_CONFN                  *((volatile unsigned int*)(0x42842824UL))
+#define bFM3_USB0_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42842828UL))
+#define bFM3_USB0_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x4284282CUL))
+#define bFM3_USB0_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42842830UL))
+#define bFM3_USB0_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42842834UL))
+#define bFM3_USB0_EP0IS_DRQI                   *((volatile unsigned int*)(0x428428A8UL))
+#define bFM3_USB0_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x428428B8UL))
+#define bFM3_USB0_EP0IS_BFINI                  *((volatile unsigned int*)(0x428428BCUL))
+#define bFM3_USB0_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42842900UL))
+#define bFM3_USB0_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42842904UL))
+#define bFM3_USB0_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42842908UL))
+#define bFM3_USB0_EP0OS_SIZE3                  *((volatile unsigned int*)(0x4284290CUL))
+#define bFM3_USB0_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42842910UL))
+#define bFM3_USB0_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42842914UL))
+#define bFM3_USB0_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42842918UL))
+#define bFM3_USB0_EP0OS_SPK                    *((volatile unsigned int*)(0x42842924UL))
+#define bFM3_USB0_EP0OS_DRQO                   *((volatile unsigned int*)(0x42842928UL))
+#define bFM3_USB0_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42842934UL))
+#define bFM3_USB0_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42842938UL))
+#define bFM3_USB0_EP0OS_BFINI                  *((volatile unsigned int*)(0x4284293CUL))
+#define bFM3_USB0_EP1S_SIZE10                  *((volatile unsigned int*)(0x42842980UL))
+#define bFM3_USB0_EP1S_SIZE11                  *((volatile unsigned int*)(0x42842984UL))
+#define bFM3_USB0_EP1S_SIZE12                  *((volatile unsigned int*)(0x42842988UL))
+#define bFM3_USB0_EP1S_SIZE13                  *((volatile unsigned int*)(0x4284298CUL))
+#define bFM3_USB0_EP1S_SIZE14                  *((volatile unsigned int*)(0x42842990UL))
+#define bFM3_USB0_EP1S_SIZE15                  *((volatile unsigned int*)(0x42842994UL))
+#define bFM3_USB0_EP1S_SIZE16                  *((volatile unsigned int*)(0x42842998UL))
+#define bFM3_USB0_EP1S_SIZE17                  *((volatile unsigned int*)(0x4284299CUL))
+#define bFM3_USB0_EP1S_SIZE18                  *((volatile unsigned int*)(0x428429A0UL))
+#define bFM3_USB0_EP1S_SPK                     *((volatile unsigned int*)(0x428429A4UL))
+#define bFM3_USB0_EP1S_DRQ                     *((volatile unsigned int*)(0x428429A8UL))
+#define bFM3_USB0_EP1S_BUSY                    *((volatile unsigned int*)(0x428429ACUL))
+#define bFM3_USB0_EP1S_SPKIE                   *((volatile unsigned int*)(0x428429B4UL))
+#define bFM3_USB0_EP1S_DRQIE                   *((volatile unsigned int*)(0x428429B8UL))
+#define bFM3_USB0_EP1S_BFINI                   *((volatile unsigned int*)(0x428429BCUL))
+#define bFM3_USB0_EP2S_SIZE20                  *((volatile unsigned int*)(0x42842A00UL))
+#define bFM3_USB0_EP2S_SIZE21                  *((volatile unsigned int*)(0x42842A04UL))
+#define bFM3_USB0_EP2S_SIZE22                  *((volatile unsigned int*)(0x42842A08UL))
+#define bFM3_USB0_EP2S_SIZE23                  *((volatile unsigned int*)(0x42842A0CUL))
+#define bFM3_USB0_EP2S_SIZE24                  *((volatile unsigned int*)(0x42842A10UL))
+#define bFM3_USB0_EP2S_SIZE25                  *((volatile unsigned int*)(0x42842A14UL))
+#define bFM3_USB0_EP2S_SIZE26                  *((volatile unsigned int*)(0x42842A18UL))
+#define bFM3_USB0_EP2S_SPK                     *((volatile unsigned int*)(0x42842A24UL))
+#define bFM3_USB0_EP2S_DRQ                     *((volatile unsigned int*)(0x42842A28UL))
+#define bFM3_USB0_EP2S_BUSY                    *((volatile unsigned int*)(0x42842A2CUL))
+#define bFM3_USB0_EP2S_SPKIE                   *((volatile unsigned int*)(0x42842A34UL))
+#define bFM3_USB0_EP2S_DRQIE                   *((volatile unsigned int*)(0x42842A38UL))
+#define bFM3_USB0_EP2S_BFINI                   *((volatile unsigned int*)(0x42842A3CUL))
+#define bFM3_USB0_EP3S_SIZE30                  *((volatile unsigned int*)(0x42842A80UL))
+#define bFM3_USB0_EP3S_SIZE31                  *((volatile unsigned int*)(0x42842A84UL))
+#define bFM3_USB0_EP3S_SIZE32                  *((volatile unsigned int*)(0x42842A88UL))
+#define bFM3_USB0_EP3S_SIZE33                  *((volatile unsigned int*)(0x42842A8CUL))
+#define bFM3_USB0_EP3S_SIZE34                  *((volatile unsigned int*)(0x42842A90UL))
+#define bFM3_USB0_EP3S_SIZE35                  *((volatile unsigned int*)(0x42842A94UL))
+#define bFM3_USB0_EP3S_SIZE36                  *((volatile unsigned int*)(0x42842A98UL))
+#define bFM3_USB0_EP3S_SPK                     *((volatile unsigned int*)(0x42842AA4UL))
+#define bFM3_USB0_EP3S_DRQ                     *((volatile unsigned int*)(0x42842AA8UL))
+#define bFM3_USB0_EP3S_BUSY                    *((volatile unsigned int*)(0x42842AACUL))
+#define bFM3_USB0_EP3S_SPKIE                   *((volatile unsigned int*)(0x42842AB4UL))
+#define bFM3_USB0_EP3S_DRQIE                   *((volatile unsigned int*)(0x42842AB8UL))
+#define bFM3_USB0_EP3S_BFINI                   *((volatile unsigned int*)(0x42842ABCUL))
+#define bFM3_USB0_EP4S_SIZE40                  *((volatile unsigned int*)(0x42842B00UL))
+#define bFM3_USB0_EP4S_SIZE41                  *((volatile unsigned int*)(0x42842B04UL))
+#define bFM3_USB0_EP4S_SIZE42                  *((volatile unsigned int*)(0x42842B08UL))
+#define bFM3_USB0_EP4S_SIZE43                  *((volatile unsigned int*)(0x42842B0CUL))
+#define bFM3_USB0_EP4S_SIZE44                  *((volatile unsigned int*)(0x42842B10UL))
+#define bFM3_USB0_EP4S_SIZE45                  *((volatile unsigned int*)(0x42842B14UL))
+#define bFM3_USB0_EP4S_SIZE46                  *((volatile unsigned int*)(0x42842B18UL))
+#define bFM3_USB0_EP4S_SPK                     *((volatile unsigned int*)(0x42842B24UL))
+#define bFM3_USB0_EP4S_DRQ                     *((volatile unsigned int*)(0x42842B28UL))
+#define bFM3_USB0_EP4S_BUSY                    *((volatile unsigned int*)(0x42842B2CUL))
+#define bFM3_USB0_EP4S_SPKIE                   *((volatile unsigned int*)(0x42842B34UL))
+#define bFM3_USB0_EP4S_DRQIE                   *((volatile unsigned int*)(0x42842B38UL))
+#define bFM3_USB0_EP4S_BFINI                   *((volatile unsigned int*)(0x42842B3CUL))
+#define bFM3_USB0_EP5S_SIZE50                  *((volatile unsigned int*)(0x42842B80UL))
+#define bFM3_USB0_EP5S_SIZE51                  *((volatile unsigned int*)(0x42842B84UL))
+#define bFM3_USB0_EP5S_SIZE52                  *((volatile unsigned int*)(0x42842B88UL))
+#define bFM3_USB0_EP5S_SIZE53                  *((volatile unsigned int*)(0x42842B8CUL))
+#define bFM3_USB0_EP5S_SIZE54                  *((volatile unsigned int*)(0x42842B90UL))
+#define bFM3_USB0_EP5S_SIZE55                  *((volatile unsigned int*)(0x42842B94UL))
+#define bFM3_USB0_EP5S_SIZE56                  *((volatile unsigned int*)(0x42842B98UL))
+#define bFM3_USB0_EP5S_SPK                     *((volatile unsigned int*)(0x42842BA4UL))
+#define bFM3_USB0_EP5S_DRQ                     *((volatile unsigned int*)(0x42842BA8UL))
+#define bFM3_USB0_EP5S_BUSY                    *((volatile unsigned int*)(0x42842BACUL))
+#define bFM3_USB0_EP5S_SPKIE                   *((volatile unsigned int*)(0x42842BB4UL))
+#define bFM3_USB0_EP5S_DRQIE                   *((volatile unsigned int*)(0x42842BB8UL))
+#define bFM3_USB0_EP5S_BFINI                   *((volatile unsigned int*)(0x42842BBCUL))
+
+/* USB channel 1 registers */
+#define bFM3_USB1_HCNT_HOST                    *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT_URST                    *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT_DIRE                    *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT_URIRE                   *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT_RWKIRE                  *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT_RETRY                   *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT_CANCEL                  *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HCNT0_HOST                   *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT0_URST                   *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT0_DIRE                   *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT0_URIRE                  *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT1_RETRY                  *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42A42080UL))
+#define bFM3_USB1_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42A42084UL))
+#define bFM3_USB1_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42A42088UL))
+#define bFM3_USB1_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x42A4208CUL))
+#define bFM3_USB1_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42A42090UL))
+#define bFM3_USB1_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42A42094UL))
+#define bFM3_USB1_HIRQ_TCAN                    *((volatile unsigned int*)(0x42A4209CUL))
+#define bFM3_USB1_HERR_HS0                     *((volatile unsigned int*)(0x42A420A0UL))
+#define bFM3_USB1_HERR_HS1                     *((volatile unsigned int*)(0x42A420A4UL))
+#define bFM3_USB1_HERR_STUFF                   *((volatile unsigned int*)(0x42A420A8UL))
+#define bFM3_USB1_HERR_TGERR                   *((volatile unsigned int*)(0x42A420ACUL))
+#define bFM3_USB1_HERR_CRC                     *((volatile unsigned int*)(0x42A420B0UL))
+#define bFM3_USB1_HERR_TOUT                    *((volatile unsigned int*)(0x42A420B4UL))
+#define bFM3_USB1_HERR_RERR                    *((volatile unsigned int*)(0x42A420B8UL))
+#define bFM3_USB1_HERR_LSTOF                   *((volatile unsigned int*)(0x42A420BCUL))
+#define bFM3_USB1_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42A42100UL))
+#define bFM3_USB1_HSTATE_TMODE                 *((volatile unsigned int*)(0x42A42104UL))
+#define bFM3_USB1_HSTATE_SUSP                  *((volatile unsigned int*)(0x42A42108UL))
+#define bFM3_USB1_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x42A4210CUL))
+#define bFM3_USB1_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42A42110UL))
+#define bFM3_USB1_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42A42114UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42A42120UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42A42124UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42A42128UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x42A4212CUL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42A42130UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42A42134UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42A42138UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x42A4213CUL))
+#define bFM3_USB1_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42A42200UL))
+#define bFM3_USB1_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42A42204UL))
+#define bFM3_USB1_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42A42208UL))
+#define bFM3_USB1_HADR_ADDRESS0                *((volatile unsigned int*)(0x42A42220UL))
+#define bFM3_USB1_HADR_ADDRESS1                *((volatile unsigned int*)(0x42A42224UL))
+#define bFM3_USB1_HADR_ADDRESS2                *((volatile unsigned int*)(0x42A42228UL))
+#define bFM3_USB1_HADR_ADDRESS3                *((volatile unsigned int*)(0x42A4222CUL))
+#define bFM3_USB1_HADR_ADDRESS4                *((volatile unsigned int*)(0x42A42230UL))
+#define bFM3_USB1_HADR_ADDRESS5                *((volatile unsigned int*)(0x42A42234UL))
+#define bFM3_USB1_HADR_ADDRESS6                *((volatile unsigned int*)(0x42A42238UL))
+#define bFM3_USB1_HEOF_EOF0                    *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF_EOF1                    *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF_EOF2                    *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF_EOF3                    *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF_EOF4                    *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF_EOF5                    *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF_EOF6                    *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF_EOF7                    *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF_EOF8                    *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF_EOF9                    *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF_EOF10                   *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF_EOF11                   *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF_EOF12                   *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF_EOF13                   *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HEOF_EOF14                   *((volatile unsigned int*)(0x42A422B8UL))
+#define bFM3_USB1_HEOF_EOF15                   *((volatile unsigned int*)(0x42A422BCUL))
+#define bFM3_USB1_HEOF0_EOF00                  *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF0_EOF01                  *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF0_EOF02                  *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF0_EOF03                  *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF0_EOF04                  *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF0_EOF05                  *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF0_EOF06                  *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF0_EOF07                  *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF1_EOF10                  *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF1_EOF11                  *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF1_EOF12                  *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF1_EOF13                  *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF1_EOF14                  *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF1_EOF15                  *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HFRAME_FRAME0                *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME_FRAME1                *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME_FRAME2                *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME_FRAME3                *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME_FRAME4                *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME_FRAME5                *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME_FRAME6                *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME_FRAME7                *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME_FRAME8                *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME_FRAME9                *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME_FRAME10               *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME0_FRAME03              *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME0_FRAME07              *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME1_FRAME13              *((volatile unsigned int*)(0x42A4232CUL))
+#define bFM3_USB1_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42A42380UL))
+#define bFM3_USB1_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42A42384UL))
+#define bFM3_USB1_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42A42388UL))
+#define bFM3_USB1_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x42A4238CUL))
+#define bFM3_USB1_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42A42390UL))
+#define bFM3_USB1_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42A42394UL))
+#define bFM3_USB1_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42A42398UL))
+#define bFM3_USB1_HTOKEN_TGGL                  *((volatile unsigned int*)(0x42A4239CUL))
+#define bFM3_USB1_UDCC_PWC                     *((volatile unsigned int*)(0x42A42400UL))
+#define bFM3_USB1_UDCC_RFBK                    *((volatile unsigned int*)(0x42A42404UL))
+#define bFM3_USB1_UDCC_STALCLREN               *((volatile unsigned int*)(0x42A4240CUL))
+#define bFM3_USB1_UDCC_USTP                    *((volatile unsigned int*)(0x42A42410UL))
+#define bFM3_USB1_UDCC_HCONX                   *((volatile unsigned int*)(0x42A42414UL))
+#define bFM3_USB1_UDCC_RESUM                   *((volatile unsigned int*)(0x42A42418UL))
+#define bFM3_USB1_UDCC_RST                     *((volatile unsigned int*)(0x42A4241CUL))
+#define bFM3_USB1_EP0C_PKS00                   *((volatile unsigned int*)(0x42A42480UL))
+#define bFM3_USB1_EP0C_PKS01                   *((volatile unsigned int*)(0x42A42484UL))
+#define bFM3_USB1_EP0C_PKS02                   *((volatile unsigned int*)(0x42A42488UL))
+#define bFM3_USB1_EP0C_PKS03                   *((volatile unsigned int*)(0x42A4248CUL))
+#define bFM3_USB1_EP0C_PKS04                   *((volatile unsigned int*)(0x42A42490UL))
+#define bFM3_USB1_EP0C_PKS05                   *((volatile unsigned int*)(0x42A42494UL))
+#define bFM3_USB1_EP0C_PKS06                   *((volatile unsigned int*)(0x42A42498UL))
+#define bFM3_USB1_EP0C_STAL                    *((volatile unsigned int*)(0x42A424A4UL))
+#define bFM3_USB1_EP1C_PKS10                   *((volatile unsigned int*)(0x42A42500UL))
+#define bFM3_USB1_EP1C_PKS11                   *((volatile unsigned int*)(0x42A42504UL))
+#define bFM3_USB1_EP1C_PKS12                   *((volatile unsigned int*)(0x42A42508UL))
+#define bFM3_USB1_EP1C_PKS13                   *((volatile unsigned int*)(0x42A4250CUL))
+#define bFM3_USB1_EP1C_PKS14                   *((volatile unsigned int*)(0x42A42510UL))
+#define bFM3_USB1_EP1C_PKS15                   *((volatile unsigned int*)(0x42A42514UL))
+#define bFM3_USB1_EP1C_PKS16                   *((volatile unsigned int*)(0x42A42518UL))
+#define bFM3_USB1_EP1C_PKS17                   *((volatile unsigned int*)(0x42A4251CUL))
+#define bFM3_USB1_EP1C_PKS18                   *((volatile unsigned int*)(0x42A42520UL))
+#define bFM3_USB1_EP1C_STAL                    *((volatile unsigned int*)(0x42A42524UL))
+#define bFM3_USB1_EP1C_NULE                    *((volatile unsigned int*)(0x42A42528UL))
+#define bFM3_USB1_EP1C_DMAE                    *((volatile unsigned int*)(0x42A4252CUL))
+#define bFM3_USB1_EP1C_DIR                     *((volatile unsigned int*)(0x42A42530UL))
+#define bFM3_USB1_EP1C_TYPE0                   *((volatile unsigned int*)(0x42A42534UL))
+#define bFM3_USB1_EP1C_TYPE1                   *((volatile unsigned int*)(0x42A42538UL))
+#define bFM3_USB1_EP1C_EPEN                    *((volatile unsigned int*)(0x42A4253CUL))
+#define bFM3_USB1_EP2C_PKS20                   *((volatile unsigned int*)(0x42A42580UL))
+#define bFM3_USB1_EP2C_PKS21                   *((volatile unsigned int*)(0x42A42584UL))
+#define bFM3_USB1_EP2C_PKS22                   *((volatile unsigned int*)(0x42A42588UL))
+#define bFM3_USB1_EP2C_PKS23                   *((volatile unsigned int*)(0x42A4258CUL))
+#define bFM3_USB1_EP2C_PKS24                   *((volatile unsigned int*)(0x42A42590UL))
+#define bFM3_USB1_EP2C_PKS25                   *((volatile unsigned int*)(0x42A42594UL))
+#define bFM3_USB1_EP2C_PKS26                   *((volatile unsigned int*)(0x42A42598UL))
+#define bFM3_USB1_EP2C_STAL                    *((volatile unsigned int*)(0x42A425A4UL))
+#define bFM3_USB1_EP2C_NULE                    *((volatile unsigned int*)(0x42A425A8UL))
+#define bFM3_USB1_EP2C_DMAE                    *((volatile unsigned int*)(0x42A425ACUL))
+#define bFM3_USB1_EP2C_DIR                     *((volatile unsigned int*)(0x42A425B0UL))
+#define bFM3_USB1_EP2C_TYPE0                   *((volatile unsigned int*)(0x42A425B4UL))
+#define bFM3_USB1_EP2C_TYPE1                   *((volatile unsigned int*)(0x42A425B8UL))
+#define bFM3_USB1_EP2C_EPEN                    *((volatile unsigned int*)(0x42A425BCUL))
+#define bFM3_USB1_EP3C_PKS30                   *((volatile unsigned int*)(0x42A42600UL))
+#define bFM3_USB1_EP3C_PKS31                   *((volatile unsigned int*)(0x42A42604UL))
+#define bFM3_USB1_EP3C_PKS32                   *((volatile unsigned int*)(0x42A42608UL))
+#define bFM3_USB1_EP3C_PKS33                   *((volatile unsigned int*)(0x42A4260CUL))
+#define bFM3_USB1_EP3C_PKS34                   *((volatile unsigned int*)(0x42A42610UL))
+#define bFM3_USB1_EP3C_PKS35                   *((volatile unsigned int*)(0x42A42614UL))
+#define bFM3_USB1_EP3C_PKS36                   *((volatile unsigned int*)(0x42A42618UL))
+#define bFM3_USB1_EP3C_STAL                    *((volatile unsigned int*)(0x42A42624UL))
+#define bFM3_USB1_EP3C_NULE                    *((volatile unsigned int*)(0x42A42628UL))
+#define bFM3_USB1_EP3C_DMAE                    *((volatile unsigned int*)(0x42A4262CUL))
+#define bFM3_USB1_EP3C_DIR                     *((volatile unsigned int*)(0x42A42630UL))
+#define bFM3_USB1_EP3C_TYPE0                   *((volatile unsigned int*)(0x42A42634UL))
+#define bFM3_USB1_EP3C_TYPE1                   *((volatile unsigned int*)(0x42A42638UL))
+#define bFM3_USB1_EP3C_EPEN                    *((volatile unsigned int*)(0x42A4263CUL))
+#define bFM3_USB1_EP4C_PKS40                   *((volatile unsigned int*)(0x42A42680UL))
+#define bFM3_USB1_EP4C_PKS41                   *((volatile unsigned int*)(0x42A42684UL))
+#define bFM3_USB1_EP4C_PKS42                   *((volatile unsigned int*)(0x42A42688UL))
+#define bFM3_USB1_EP4C_PKS43                   *((volatile unsigned int*)(0x42A4268CUL))
+#define bFM3_USB1_EP4C_PKS44                   *((volatile unsigned int*)(0x42A42690UL))
+#define bFM3_USB1_EP4C_PKS45                   *((volatile unsigned int*)(0x42A42694UL))
+#define bFM3_USB1_EP4C_PKS46                   *((volatile unsigned int*)(0x42A42698UL))
+#define bFM3_USB1_EP4C_STAL                    *((volatile unsigned int*)(0x42A426A4UL))
+#define bFM3_USB1_EP4C_NULE                    *((volatile unsigned int*)(0x42A426A8UL))
+#define bFM3_USB1_EP4C_DMAE                    *((volatile unsigned int*)(0x42A426ACUL))
+#define bFM3_USB1_EP4C_DIR                     *((volatile unsigned int*)(0x42A426B0UL))
+#define bFM3_USB1_EP4C_TYPE0                   *((volatile unsigned int*)(0x42A426B4UL))
+#define bFM3_USB1_EP4C_TYPE1                   *((volatile unsigned int*)(0x42A426B8UL))
+#define bFM3_USB1_EP4C_EPEN                    *((volatile unsigned int*)(0x42A426BCUL))
+#define bFM3_USB1_EP5C_PKS50                   *((volatile unsigned int*)(0x42A42700UL))
+#define bFM3_USB1_EP5C_PKS51                   *((volatile unsigned int*)(0x42A42704UL))
+#define bFM3_USB1_EP5C_PKS52                   *((volatile unsigned int*)(0x42A42708UL))
+#define bFM3_USB1_EP5C_PKS53                   *((volatile unsigned int*)(0x42A4270CUL))
+#define bFM3_USB1_EP5C_PKS54                   *((volatile unsigned int*)(0x42A42710UL))
+#define bFM3_USB1_EP5C_PKS55                   *((volatile unsigned int*)(0x42A42714UL))
+#define bFM3_USB1_EP5C_PKS56                   *((volatile unsigned int*)(0x42A42718UL))
+#define bFM3_USB1_EP5C_STAL                    *((volatile unsigned int*)(0x42A42724UL))
+#define bFM3_USB1_EP5C_NULE                    *((volatile unsigned int*)(0x42A42728UL))
+#define bFM3_USB1_EP5C_DMAE                    *((volatile unsigned int*)(0x42A4272CUL))
+#define bFM3_USB1_EP5C_DIR                     *((volatile unsigned int*)(0x42A42730UL))
+#define bFM3_USB1_EP5C_TYPE0                   *((volatile unsigned int*)(0x42A42734UL))
+#define bFM3_USB1_EP5C_TYPE1                   *((volatile unsigned int*)(0x42A42738UL))
+#define bFM3_USB1_EP5C_EPEN                    *((volatile unsigned int*)(0x42A4273CUL))
+#define bFM3_USB1_TMSP_TMSP0                   *((volatile unsigned int*)(0x42A42780UL))
+#define bFM3_USB1_TMSP_TMSP1                   *((volatile unsigned int*)(0x42A42784UL))
+#define bFM3_USB1_TMSP_TMSP2                   *((volatile unsigned int*)(0x42A42788UL))
+#define bFM3_USB1_TMSP_TMSP3                   *((volatile unsigned int*)(0x42A4278CUL))
+#define bFM3_USB1_TMSP_TMSP4                   *((volatile unsigned int*)(0x42A42790UL))
+#define bFM3_USB1_TMSP_TMSP5                   *((volatile unsigned int*)(0x42A42794UL))
+#define bFM3_USB1_TMSP_TMSP6                   *((volatile unsigned int*)(0x42A42798UL))
+#define bFM3_USB1_TMSP_TMSP7                   *((volatile unsigned int*)(0x42A4279CUL))
+#define bFM3_USB1_TMSP_TMSP8                   *((volatile unsigned int*)(0x42A427A0UL))
+#define bFM3_USB1_TMSP_TMSP9                   *((volatile unsigned int*)(0x42A427A4UL))
+#define bFM3_USB1_TMSP_TMSP10                  *((volatile unsigned int*)(0x42A427A8UL))
+#define bFM3_USB1_UDCS_CONF                    *((volatile unsigned int*)(0x42A42800UL))
+#define bFM3_USB1_UDCS_SETP                    *((volatile unsigned int*)(0x42A42804UL))
+#define bFM3_USB1_UDCS_WKUP                    *((volatile unsigned int*)(0x42A42808UL))
+#define bFM3_USB1_UDCS_BRST                    *((volatile unsigned int*)(0x42A4280CUL))
+#define bFM3_USB1_UDCS_SOF                     *((volatile unsigned int*)(0x42A42810UL))
+#define bFM3_USB1_UDCS_SUSP                    *((volatile unsigned int*)(0x42A42814UL))
+#define bFM3_USB1_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42A42820UL))
+#define bFM3_USB1_UDCIE_CONFN                  *((volatile unsigned int*)(0x42A42824UL))
+#define bFM3_USB1_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42A42828UL))
+#define bFM3_USB1_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x42A4282CUL))
+#define bFM3_USB1_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42A42830UL))
+#define bFM3_USB1_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42A42834UL))
+#define bFM3_USB1_EP0IS_DRQI                   *((volatile unsigned int*)(0x42A428A8UL))
+#define bFM3_USB1_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x42A428B8UL))
+#define bFM3_USB1_EP0IS_BFINI                  *((volatile unsigned int*)(0x42A428BCUL))
+#define bFM3_USB1_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42A42900UL))
+#define bFM3_USB1_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42A42904UL))
+#define bFM3_USB1_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42A42908UL))
+#define bFM3_USB1_EP0OS_SIZE3                  *((volatile unsigned int*)(0x42A4290CUL))
+#define bFM3_USB1_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42A42910UL))
+#define bFM3_USB1_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42A42914UL))
+#define bFM3_USB1_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42A42918UL))
+#define bFM3_USB1_EP0OS_SPK                    *((volatile unsigned int*)(0x42A42924UL))
+#define bFM3_USB1_EP0OS_DRQO                   *((volatile unsigned int*)(0x42A42928UL))
+#define bFM3_USB1_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42A42934UL))
+#define bFM3_USB1_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42A42938UL))
+#define bFM3_USB1_EP0OS_BFINI                  *((volatile unsigned int*)(0x42A4293CUL))
+#define bFM3_USB1_EP1S_SIZE10                  *((volatile unsigned int*)(0x42A42980UL))
+#define bFM3_USB1_EP1S_SIZE11                  *((volatile unsigned int*)(0x42A42984UL))
+#define bFM3_USB1_EP1S_SIZE12                  *((volatile unsigned int*)(0x42A42988UL))
+#define bFM3_USB1_EP1S_SIZE13                  *((volatile unsigned int*)(0x42A4298CUL))
+#define bFM3_USB1_EP1S_SIZE14                  *((volatile unsigned int*)(0x42A42990UL))
+#define bFM3_USB1_EP1S_SIZE15                  *((volatile unsigned int*)(0x42A42994UL))
+#define bFM3_USB1_EP1S_SIZE16                  *((volatile unsigned int*)(0x42A42998UL))
+#define bFM3_USB1_EP1S_SIZE17                  *((volatile unsigned int*)(0x42A4299CUL))
+#define bFM3_USB1_EP1S_SIZE18                  *((volatile unsigned int*)(0x42A429A0UL))
+#define bFM3_USB1_EP1S_SPK                     *((volatile unsigned int*)(0x42A429A4UL))
+#define bFM3_USB1_EP1S_DRQ                     *((volatile unsigned int*)(0x42A429A8UL))
+#define bFM3_USB1_EP1S_BUSY                    *((volatile unsigned int*)(0x42A429ACUL))
+#define bFM3_USB1_EP1S_SPKIE                   *((volatile unsigned int*)(0x42A429B4UL))
+#define bFM3_USB1_EP1S_DRQIE                   *((volatile unsigned int*)(0x42A429B8UL))
+#define bFM3_USB1_EP1S_BFINI                   *((volatile unsigned int*)(0x42A429BCUL))
+#define bFM3_USB1_EP2S_SIZE20                  *((volatile unsigned int*)(0x42A42A00UL))
+#define bFM3_USB1_EP2S_SIZE21                  *((volatile unsigned int*)(0x42A42A04UL))
+#define bFM3_USB1_EP2S_SIZE22                  *((volatile unsigned int*)(0x42A42A08UL))
+#define bFM3_USB1_EP2S_SIZE23                  *((volatile unsigned int*)(0x42A42A0CUL))
+#define bFM3_USB1_EP2S_SIZE24                  *((volatile unsigned int*)(0x42A42A10UL))
+#define bFM3_USB1_EP2S_SIZE25                  *((volatile unsigned int*)(0x42A42A14UL))
+#define bFM3_USB1_EP2S_SIZE26                  *((volatile unsigned int*)(0x42A42A18UL))
+#define bFM3_USB1_EP2S_SPK                     *((volatile unsigned int*)(0x42A42A24UL))
+#define bFM3_USB1_EP2S_DRQ                     *((volatile unsigned int*)(0x42A42A28UL))
+#define bFM3_USB1_EP2S_BUSY                    *((volatile unsigned int*)(0x42A42A2CUL))
+#define bFM3_USB1_EP2S_SPKIE                   *((volatile unsigned int*)(0x42A42A34UL))
+#define bFM3_USB1_EP2S_DRQIE                   *((volatile unsigned int*)(0x42A42A38UL))
+#define bFM3_USB1_EP2S_BFINI                   *((volatile unsigned int*)(0x42A42A3CUL))
+#define bFM3_USB1_EP3S_SIZE30                  *((volatile unsigned int*)(0x42A42A80UL))
+#define bFM3_USB1_EP3S_SIZE31                  *((volatile unsigned int*)(0x42A42A84UL))
+#define bFM3_USB1_EP3S_SIZE32                  *((volatile unsigned int*)(0x42A42A88UL))
+#define bFM3_USB1_EP3S_SIZE33                  *((volatile unsigned int*)(0x42A42A8CUL))
+#define bFM3_USB1_EP3S_SIZE34                  *((volatile unsigned int*)(0x42A42A90UL))
+#define bFM3_USB1_EP3S_SIZE35                  *((volatile unsigned int*)(0x42A42A94UL))
+#define bFM3_USB1_EP3S_SIZE36                  *((volatile unsigned int*)(0x42A42A98UL))
+#define bFM3_USB1_EP3S_SPK                     *((volatile unsigned int*)(0x42A42AA4UL))
+#define bFM3_USB1_EP3S_DRQ                     *((volatile unsigned int*)(0x42A42AA8UL))
+#define bFM3_USB1_EP3S_BUSY                    *((volatile unsigned int*)(0x42A42AACUL))
+#define bFM3_USB1_EP3S_SPKIE                   *((volatile unsigned int*)(0x42A42AB4UL))
+#define bFM3_USB1_EP3S_DRQIE                   *((volatile unsigned int*)(0x42A42AB8UL))
+#define bFM3_USB1_EP3S_BFINI                   *((volatile unsigned int*)(0x42A42ABCUL))
+#define bFM3_USB1_EP4S_SIZE40                  *((volatile unsigned int*)(0x42A42B00UL))
+#define bFM3_USB1_EP4S_SIZE41                  *((volatile unsigned int*)(0x42A42B04UL))
+#define bFM3_USB1_EP4S_SIZE42                  *((volatile unsigned int*)(0x42A42B08UL))
+#define bFM3_USB1_EP4S_SIZE43                  *((volatile unsigned int*)(0x42A42B0CUL))
+#define bFM3_USB1_EP4S_SIZE44                  *((volatile unsigned int*)(0x42A42B10UL))
+#define bFM3_USB1_EP4S_SIZE45                  *((volatile unsigned int*)(0x42A42B14UL))
+#define bFM3_USB1_EP4S_SIZE46                  *((volatile unsigned int*)(0x42A42B18UL))
+#define bFM3_USB1_EP4S_SPK                     *((volatile unsigned int*)(0x42A42B24UL))
+#define bFM3_USB1_EP4S_DRQ                     *((volatile unsigned int*)(0x42A42B28UL))
+#define bFM3_USB1_EP4S_BUSY                    *((volatile unsigned int*)(0x42A42B2CUL))
+#define bFM3_USB1_EP4S_SPKIE                   *((volatile unsigned int*)(0x42A42B34UL))
+#define bFM3_USB1_EP4S_DRQIE                   *((volatile unsigned int*)(0x42A42B38UL))
+#define bFM3_USB1_EP4S_BFINI                   *((volatile unsigned int*)(0x42A42B3CUL))
+#define bFM3_USB1_EP5S_SIZE50                  *((volatile unsigned int*)(0x42A42B80UL))
+#define bFM3_USB1_EP5S_SIZE51                  *((volatile unsigned int*)(0x42A42B84UL))
+#define bFM3_USB1_EP5S_SIZE52                  *((volatile unsigned int*)(0x42A42B88UL))
+#define bFM3_USB1_EP5S_SIZE53                  *((volatile unsigned int*)(0x42A42B8CUL))
+#define bFM3_USB1_EP5S_SIZE54                  *((volatile unsigned int*)(0x42A42B90UL))
+#define bFM3_USB1_EP5S_SIZE55                  *((volatile unsigned int*)(0x42A42B94UL))
+#define bFM3_USB1_EP5S_SIZE56                  *((volatile unsigned int*)(0x42A42B98UL))
+#define bFM3_USB1_EP5S_SPK                     *((volatile unsigned int*)(0x42A42BA4UL))
+#define bFM3_USB1_EP5S_DRQ                     *((volatile unsigned int*)(0x42A42BA8UL))
+#define bFM3_USB1_EP5S_BUSY                    *((volatile unsigned int*)(0x42A42BACUL))
+#define bFM3_USB1_EP5S_SPKIE                   *((volatile unsigned int*)(0x42A42BB4UL))
+#define bFM3_USB1_EP5S_DRQIE                   *((volatile unsigned int*)(0x42A42BB8UL))
+#define bFM3_USB1_EP5S_BFINI                   *((volatile unsigned int*)(0x42A42BBCUL))
+
+/* DMA controller */
+#define bFM3_DMAC_DMACR_DH0                    *((volatile unsigned int*)(0x42C00060UL))
+#define bFM3_DMAC_DMACR_DH1                    *((volatile unsigned int*)(0x42C00064UL))
+#define bFM3_DMAC_DMACR_DH2                    *((volatile unsigned int*)(0x42C00068UL))
+#define bFM3_DMAC_DMACR_DH3                    *((volatile unsigned int*)(0x42C0006CUL))
+#define bFM3_DMAC_DMACR_PR                     *((volatile unsigned int*)(0x42C00070UL))
+#define bFM3_DMAC_DMACR_DS                     *((volatile unsigned int*)(0x42C00078UL))
+#define bFM3_DMAC_DMACR_DE                     *((volatile unsigned int*)(0x42C0007CUL))
+#define bFM3_DMAC_DMACA0_TC0                   *((volatile unsigned int*)(0x42C00200UL))
+#define bFM3_DMAC_DMACA0_TC1                   *((volatile unsigned int*)(0x42C00204UL))
+#define bFM3_DMAC_DMACA0_TC2                   *((volatile unsigned int*)(0x42C00208UL))
+#define bFM3_DMAC_DMACA0_TC3                   *((volatile unsigned int*)(0x42C0020CUL))
+#define bFM3_DMAC_DMACA0_TC4                   *((volatile unsigned int*)(0x42C00210UL))
+#define bFM3_DMAC_DMACA0_TC5                   *((volatile unsigned int*)(0x42C00214UL))
+#define bFM3_DMAC_DMACA0_TC6                   *((volatile unsigned int*)(0x42C00218UL))
+#define bFM3_DMAC_DMACA0_TC7                   *((volatile unsigned int*)(0x42C0021CUL))
+#define bFM3_DMAC_DMACA0_TC8                   *((volatile unsigned int*)(0x42C00220UL))
+#define bFM3_DMAC_DMACA0_TC9                   *((volatile unsigned int*)(0x42C00224UL))
+#define bFM3_DMAC_DMACA0_TC10                  *((volatile unsigned int*)(0x42C00228UL))
+#define bFM3_DMAC_DMACA0_TC11                  *((volatile unsigned int*)(0x42C0022CUL))
+#define bFM3_DMAC_DMACA0_TC12                  *((volatile unsigned int*)(0x42C00230UL))
+#define bFM3_DMAC_DMACA0_TC13                  *((volatile unsigned int*)(0x42C00234UL))
+#define bFM3_DMAC_DMACA0_TC14                  *((volatile unsigned int*)(0x42C00238UL))
+#define bFM3_DMAC_DMACA0_TC15                  *((volatile unsigned int*)(0x42C0023CUL))
+#define bFM3_DMAC_DMACA0_BC0                   *((volatile unsigned int*)(0x42C00240UL))
+#define bFM3_DMAC_DMACA0_BC1                   *((volatile unsigned int*)(0x42C00244UL))
+#define bFM3_DMAC_DMACA0_BC2                   *((volatile unsigned int*)(0x42C00248UL))
+#define bFM3_DMAC_DMACA0_BC3                   *((volatile unsigned int*)(0x42C0024CUL))
+#define bFM3_DMAC_DMACA0_IS0                   *((volatile unsigned int*)(0x42C0025CUL))
+#define bFM3_DMAC_DMACA0_IS1                   *((volatile unsigned int*)(0x42C00260UL))
+#define bFM3_DMAC_DMACA0_IS2                   *((volatile unsigned int*)(0x42C00264UL))
+#define bFM3_DMAC_DMACA0_IS3                   *((volatile unsigned int*)(0x42C00268UL))
+#define bFM3_DMAC_DMACA0_IS4                   *((volatile unsigned int*)(0x42C0026CUL))
+#define bFM3_DMAC_DMACA0_IS5                   *((volatile unsigned int*)(0x42C00270UL))
+#define bFM3_DMAC_DMACA0_ST                    *((volatile unsigned int*)(0x42C00274UL))
+#define bFM3_DMAC_DMACA0_PB                    *((volatile unsigned int*)(0x42C00278UL))
+#define bFM3_DMAC_DMACA0_EB                    *((volatile unsigned int*)(0x42C0027CUL))
+#define bFM3_DMAC_DMACB0_EM                    *((volatile unsigned int*)(0x42C00280UL))
+#define bFM3_DMAC_DMACB0_SS0                   *((volatile unsigned int*)(0x42C002C0UL))
+#define bFM3_DMAC_DMACB0_SS1                   *((volatile unsigned int*)(0x42C002C4UL))
+#define bFM3_DMAC_DMACB0_SS2                   *((volatile unsigned int*)(0x42C002C8UL))
+#define bFM3_DMAC_DMACB0_CI                    *((volatile unsigned int*)(0x42C002CCUL))
+#define bFM3_DMAC_DMACB0_EI                    *((volatile unsigned int*)(0x42C002D0UL))
+#define bFM3_DMAC_DMACB0_RD                    *((volatile unsigned int*)(0x42C002D4UL))
+#define bFM3_DMAC_DMACB0_RS                    *((volatile unsigned int*)(0x42C002D8UL))
+#define bFM3_DMAC_DMACB0_RC                    *((volatile unsigned int*)(0x42C002DCUL))
+#define bFM3_DMAC_DMACB0_FD                    *((volatile unsigned int*)(0x42C002E0UL))
+#define bFM3_DMAC_DMACB0_FS                    *((volatile unsigned int*)(0x42C002E4UL))
+#define bFM3_DMAC_DMACB0_TW0                   *((volatile unsigned int*)(0x42C002E8UL))
+#define bFM3_DMAC_DMACB0_TW1                   *((volatile unsigned int*)(0x42C002ECUL))
+#define bFM3_DMAC_DMACB0_MS0                   *((volatile unsigned int*)(0x42C002F0UL))
+#define bFM3_DMAC_DMACB0_MS1                   *((volatile unsigned int*)(0x42C002F4UL))
+#define bFM3_DMAC_DMACA1_TC0                   *((volatile unsigned int*)(0x42C00400UL))
+#define bFM3_DMAC_DMACA1_TC1                   *((volatile unsigned int*)(0x42C00404UL))
+#define bFM3_DMAC_DMACA1_TC2                   *((volatile unsigned int*)(0x42C00408UL))
+#define bFM3_DMAC_DMACA1_TC3                   *((volatile unsigned int*)(0x42C0040CUL))
+#define bFM3_DMAC_DMACA1_TC4                   *((volatile unsigned int*)(0x42C00410UL))
+#define bFM3_DMAC_DMACA1_TC5                   *((volatile unsigned int*)(0x42C00414UL))
+#define bFM3_DMAC_DMACA1_TC6                   *((volatile unsigned int*)(0x42C00418UL))
+#define bFM3_DMAC_DMACA1_TC7                   *((volatile unsigned int*)(0x42C0041CUL))
+#define bFM3_DMAC_DMACA1_TC8                   *((volatile unsigned int*)(0x42C00420UL))
+#define bFM3_DMAC_DMACA1_TC9                   *((volatile unsigned int*)(0x42C00424UL))
+#define bFM3_DMAC_DMACA1_TC10                  *((volatile unsigned int*)(0x42C00428UL))
+#define bFM3_DMAC_DMACA1_TC11                  *((volatile unsigned int*)(0x42C0042CUL))
+#define bFM3_DMAC_DMACA1_TC12                  *((volatile unsigned int*)(0x42C00430UL))
+#define bFM3_DMAC_DMACA1_TC13                  *((volatile unsigned int*)(0x42C00434UL))
+#define bFM3_DMAC_DMACA1_TC14                  *((volatile unsigned int*)(0x42C00438UL))
+#define bFM3_DMAC_DMACA1_TC15                  *((volatile unsigned int*)(0x42C0043CUL))
+#define bFM3_DMAC_DMACA1_BC0                   *((volatile unsigned int*)(0x42C00440UL))
+#define bFM3_DMAC_DMACA1_BC1                   *((volatile unsigned int*)(0x42C00444UL))
+#define bFM3_DMAC_DMACA1_BC2                   *((volatile unsigned int*)(0x42C00448UL))
+#define bFM3_DMAC_DMACA1_BC3                   *((volatile unsigned int*)(0x42C0044CUL))
+#define bFM3_DMAC_DMACA1_IS0                   *((volatile unsigned int*)(0x42C0045CUL))
+#define bFM3_DMAC_DMACA1_IS1                   *((volatile unsigned int*)(0x42C00460UL))
+#define bFM3_DMAC_DMACA1_IS2                   *((volatile unsigned int*)(0x42C00464UL))
+#define bFM3_DMAC_DMACA1_IS3                   *((volatile unsigned int*)(0x42C00468UL))
+#define bFM3_DMAC_DMACA1_IS4                   *((volatile unsigned int*)(0x42C0046CUL))
+#define bFM3_DMAC_DMACA1_IS5                   *((volatile unsigned int*)(0x42C00470UL))
+#define bFM3_DMAC_DMACA1_ST                    *((volatile unsigned int*)(0x42C00474UL))
+#define bFM3_DMAC_DMACA1_PB                    *((volatile unsigned int*)(0x42C00478UL))
+#define bFM3_DMAC_DMACA1_EB                    *((volatile unsigned int*)(0x42C0047CUL))
+#define bFM3_DMAC_DMACB1_EM                    *((volatile unsigned int*)(0x42C00480UL))
+#define bFM3_DMAC_DMACB1_SS0                   *((volatile unsigned int*)(0x42C004C0UL))
+#define bFM3_DMAC_DMACB1_SS1                   *((volatile unsigned int*)(0x42C004C4UL))
+#define bFM3_DMAC_DMACB1_SS2                   *((volatile unsigned int*)(0x42C004C8UL))
+#define bFM3_DMAC_DMACB1_CI                    *((volatile unsigned int*)(0x42C004CCUL))
+#define bFM3_DMAC_DMACB1_EI                    *((volatile unsigned int*)(0x42C004D0UL))
+#define bFM3_DMAC_DMACB1_RD                    *((volatile unsigned int*)(0x42C004D4UL))
+#define bFM3_DMAC_DMACB1_RS                    *((volatile unsigned int*)(0x42C004D8UL))
+#define bFM3_DMAC_DMACB1_RC                    *((volatile unsigned int*)(0x42C004DCUL))
+#define bFM3_DMAC_DMACB1_FD                    *((volatile unsigned int*)(0x42C004E0UL))
+#define bFM3_DMAC_DMACB1_FS                    *((volatile unsigned int*)(0x42C004E4UL))
+#define bFM3_DMAC_DMACB1_TW0                   *((volatile unsigned int*)(0x42C004E8UL))
+#define bFM3_DMAC_DMACB1_TW1                   *((volatile unsigned int*)(0x42C004ECUL))
+#define bFM3_DMAC_DMACB1_MS0                   *((volatile unsigned int*)(0x42C004F0UL))
+#define bFM3_DMAC_DMACB1_MS1                   *((volatile unsigned int*)(0x42C004F4UL))
+#define bFM3_DMAC_DMACA2_TC0                   *((volatile unsigned int*)(0x42C00600UL))
+#define bFM3_DMAC_DMACA2_TC1                   *((volatile unsigned int*)(0x42C00604UL))
+#define bFM3_DMAC_DMACA2_TC2                   *((volatile unsigned int*)(0x42C00608UL))
+#define bFM3_DMAC_DMACA2_TC3                   *((volatile unsigned int*)(0x42C0060CUL))
+#define bFM3_DMAC_DMACA2_TC4                   *((volatile unsigned int*)(0x42C00610UL))
+#define bFM3_DMAC_DMACA2_TC5                   *((volatile unsigned int*)(0x42C00614UL))
+#define bFM3_DMAC_DMACA2_TC6                   *((volatile unsigned int*)(0x42C00618UL))
+#define bFM3_DMAC_DMACA2_TC7                   *((volatile unsigned int*)(0x42C0061CUL))
+#define bFM3_DMAC_DMACA2_TC8                   *((volatile unsigned int*)(0x42C00620UL))
+#define bFM3_DMAC_DMACA2_TC9                   *((volatile unsigned int*)(0x42C00624UL))
+#define bFM3_DMAC_DMACA2_TC10                  *((volatile unsigned int*)(0x42C00628UL))
+#define bFM3_DMAC_DMACA2_TC11                  *((volatile unsigned int*)(0x42C0062CUL))
+#define bFM3_DMAC_DMACA2_TC12                  *((volatile unsigned int*)(0x42C00630UL))
+#define bFM3_DMAC_DMACA2_TC13                  *((volatile unsigned int*)(0x42C00634UL))
+#define bFM3_DMAC_DMACA2_TC14                  *((volatile unsigned int*)(0x42C00638UL))
+#define bFM3_DMAC_DMACA2_TC15                  *((volatile unsigned int*)(0x42C0063CUL))
+#define bFM3_DMAC_DMACA2_BC0                   *((volatile unsigned int*)(0x42C00640UL))
+#define bFM3_DMAC_DMACA2_BC1                   *((volatile unsigned int*)(0x42C00644UL))
+#define bFM3_DMAC_DMACA2_BC2                   *((volatile unsigned int*)(0x42C00648UL))
+#define bFM3_DMAC_DMACA2_BC3                   *((volatile unsigned int*)(0x42C0064CUL))
+#define bFM3_DMAC_DMACA2_IS0                   *((volatile unsigned int*)(0x42C0065CUL))
+#define bFM3_DMAC_DMACA2_IS1                   *((volatile unsigned int*)(0x42C00660UL))
+#define bFM3_DMAC_DMACA2_IS2                   *((volatile unsigned int*)(0x42C00664UL))
+#define bFM3_DMAC_DMACA2_IS3                   *((volatile unsigned int*)(0x42C00668UL))
+#define bFM3_DMAC_DMACA2_IS4                   *((volatile unsigned int*)(0x42C0066CUL))
+#define bFM3_DMAC_DMACA2_IS5                   *((volatile unsigned int*)(0x42C00670UL))
+#define bFM3_DMAC_DMACA2_ST                    *((volatile unsigned int*)(0x42C00674UL))
+#define bFM3_DMAC_DMACA2_PB                    *((volatile unsigned int*)(0x42C00678UL))
+#define bFM3_DMAC_DMACA2_EB                    *((volatile unsigned int*)(0x42C0067CUL))
+#define bFM3_DMAC_DMACB2_EM                    *((volatile unsigned int*)(0x42C00680UL))
+#define bFM3_DMAC_DMACB2_SS0                   *((volatile unsigned int*)(0x42C006C0UL))
+#define bFM3_DMAC_DMACB2_SS1                   *((volatile unsigned int*)(0x42C006C4UL))
+#define bFM3_DMAC_DMACB2_SS2                   *((volatile unsigned int*)(0x42C006C8UL))
+#define bFM3_DMAC_DMACB2_CI                    *((volatile unsigned int*)(0x42C006CCUL))
+#define bFM3_DMAC_DMACB2_EI                    *((volatile unsigned int*)(0x42C006D0UL))
+#define bFM3_DMAC_DMACB2_RD                    *((volatile unsigned int*)(0x42C006D4UL))
+#define bFM3_DMAC_DMACB2_RS                    *((volatile unsigned int*)(0x42C006D8UL))
+#define bFM3_DMAC_DMACB2_RC                    *((volatile unsigned int*)(0x42C006DCUL))
+#define bFM3_DMAC_DMACB2_FD                    *((volatile unsigned int*)(0x42C006E0UL))
+#define bFM3_DMAC_DMACB2_FS                    *((volatile unsigned int*)(0x42C006E4UL))
+#define bFM3_DMAC_DMACB2_TW0                   *((volatile unsigned int*)(0x42C006E8UL))
+#define bFM3_DMAC_DMACB2_TW1                   *((volatile unsigned int*)(0x42C006ECUL))
+#define bFM3_DMAC_DMACB2_MS0                   *((volatile unsigned int*)(0x42C006F0UL))
+#define bFM3_DMAC_DMACB2_MS1                   *((volatile unsigned int*)(0x42C006F4UL))
+#define bFM3_DMAC_DMACA3_TC0                   *((volatile unsigned int*)(0x42C00800UL))
+#define bFM3_DMAC_DMACA3_TC1                   *((volatile unsigned int*)(0x42C00804UL))
+#define bFM3_DMAC_DMACA3_TC2                   *((volatile unsigned int*)(0x42C00808UL))
+#define bFM3_DMAC_DMACA3_TC3                   *((volatile unsigned int*)(0x42C0080CUL))
+#define bFM3_DMAC_DMACA3_TC4                   *((volatile unsigned int*)(0x42C00810UL))
+#define bFM3_DMAC_DMACA3_TC5                   *((volatile unsigned int*)(0x42C00814UL))
+#define bFM3_DMAC_DMACA3_TC6                   *((volatile unsigned int*)(0x42C00818UL))
+#define bFM3_DMAC_DMACA3_TC7                   *((volatile unsigned int*)(0x42C0081CUL))
+#define bFM3_DMAC_DMACA3_TC8                   *((volatile unsigned int*)(0x42C00820UL))
+#define bFM3_DMAC_DMACA3_TC9                   *((volatile unsigned int*)(0x42C00824UL))
+#define bFM3_DMAC_DMACA3_TC10                  *((volatile unsigned int*)(0x42C00828UL))
+#define bFM3_DMAC_DMACA3_TC11                  *((volatile unsigned int*)(0x42C0082CUL))
+#define bFM3_DMAC_DMACA3_TC12                  *((volatile unsigned int*)(0x42C00830UL))
+#define bFM3_DMAC_DMACA3_TC13                  *((volatile unsigned int*)(0x42C00834UL))
+#define bFM3_DMAC_DMACA3_TC14                  *((volatile unsigned int*)(0x42C00838UL))
+#define bFM3_DMAC_DMACA3_TC15                  *((volatile unsigned int*)(0x42C0083CUL))
+#define bFM3_DMAC_DMACA3_BC0                   *((volatile unsigned int*)(0x42C00840UL))
+#define bFM3_DMAC_DMACA3_BC1                   *((volatile unsigned int*)(0x42C00844UL))
+#define bFM3_DMAC_DMACA3_BC2                   *((volatile unsigned int*)(0x42C00848UL))
+#define bFM3_DMAC_DMACA3_BC3                   *((volatile unsigned int*)(0x42C0084CUL))
+#define bFM3_DMAC_DMACA3_IS0                   *((volatile unsigned int*)(0x42C0085CUL))
+#define bFM3_DMAC_DMACA3_IS1                   *((volatile unsigned int*)(0x42C00860UL))
+#define bFM3_DMAC_DMACA3_IS2                   *((volatile unsigned int*)(0x42C00864UL))
+#define bFM3_DMAC_DMACA3_IS3                   *((volatile unsigned int*)(0x42C00868UL))
+#define bFM3_DMAC_DMACA3_IS4                   *((volatile unsigned int*)(0x42C0086CUL))
+#define bFM3_DMAC_DMACA3_IS5                   *((volatile unsigned int*)(0x42C00870UL))
+#define bFM3_DMAC_DMACA3_ST                    *((volatile unsigned int*)(0x42C00874UL))
+#define bFM3_DMAC_DMACA3_PB                    *((volatile unsigned int*)(0x42C00878UL))
+#define bFM3_DMAC_DMACA3_EB                    *((volatile unsigned int*)(0x42C0087CUL))
+#define bFM3_DMAC_DMACB3_EM                    *((volatile unsigned int*)(0x42C00880UL))
+#define bFM3_DMAC_DMACB3_SS0                   *((volatile unsigned int*)(0x42C008C0UL))
+#define bFM3_DMAC_DMACB3_SS1                   *((volatile unsigned int*)(0x42C008C4UL))
+#define bFM3_DMAC_DMACB3_SS2                   *((volatile unsigned int*)(0x42C008C8UL))
+#define bFM3_DMAC_DMACB3_CI                    *((volatile unsigned int*)(0x42C008CCUL))
+#define bFM3_DMAC_DMACB3_EI                    *((volatile unsigned int*)(0x42C008D0UL))
+#define bFM3_DMAC_DMACB3_RD                    *((volatile unsigned int*)(0x42C008D4UL))
+#define bFM3_DMAC_DMACB3_RS                    *((volatile unsigned int*)(0x42C008D8UL))
+#define bFM3_DMAC_DMACB3_RC                    *((volatile unsigned int*)(0x42C008DCUL))
+#define bFM3_DMAC_DMACB3_FD                    *((volatile unsigned int*)(0x42C008E0UL))
+#define bFM3_DMAC_DMACB3_FS                    *((volatile unsigned int*)(0x42C008E4UL))
+#define bFM3_DMAC_DMACB3_TW0                   *((volatile unsigned int*)(0x42C008E8UL))
+#define bFM3_DMAC_DMACB3_TW1                   *((volatile unsigned int*)(0x42C008ECUL))
+#define bFM3_DMAC_DMACB3_MS0                   *((volatile unsigned int*)(0x42C008F0UL))
+#define bFM3_DMAC_DMACB3_MS1                   *((volatile unsigned int*)(0x42C008F4UL))
+#define bFM3_DMAC_DMACA4_TC0                   *((volatile unsigned int*)(0x42C00A00UL))
+#define bFM3_DMAC_DMACA4_TC1                   *((volatile unsigned int*)(0x42C00A04UL))
+#define bFM3_DMAC_DMACA4_TC2                   *((volatile unsigned int*)(0x42C00A08UL))
+#define bFM3_DMAC_DMACA4_TC3                   *((volatile unsigned int*)(0x42C00A0CUL))
+#define bFM3_DMAC_DMACA4_TC4                   *((volatile unsigned int*)(0x42C00A10UL))
+#define bFM3_DMAC_DMACA4_TC5                   *((volatile unsigned int*)(0x42C00A14UL))
+#define bFM3_DMAC_DMACA4_TC6                   *((volatile unsigned int*)(0x42C00A18UL))
+#define bFM3_DMAC_DMACA4_TC7                   *((volatile unsigned int*)(0x42C00A1CUL))
+#define bFM3_DMAC_DMACA4_TC8                   *((volatile unsigned int*)(0x42C00A20UL))
+#define bFM3_DMAC_DMACA4_TC9                   *((volatile unsigned int*)(0x42C00A24UL))
+#define bFM3_DMAC_DMACA4_TC10                  *((volatile unsigned int*)(0x42C00A28UL))
+#define bFM3_DMAC_DMACA4_TC11                  *((volatile unsigned int*)(0x42C00A2CUL))
+#define bFM3_DMAC_DMACA4_TC12                  *((volatile unsigned int*)(0x42C00A30UL))
+#define bFM3_DMAC_DMACA4_TC13                  *((volatile unsigned int*)(0x42C00A34UL))
+#define bFM3_DMAC_DMACA4_TC14                  *((volatile unsigned int*)(0x42C00A38UL))
+#define bFM3_DMAC_DMACA4_TC15                  *((volatile unsigned int*)(0x42C00A3CUL))
+#define bFM3_DMAC_DMACA4_BC0                   *((volatile unsigned int*)(0x42C00A40UL))
+#define bFM3_DMAC_DMACA4_BC1                   *((volatile unsigned int*)(0x42C00A44UL))
+#define bFM3_DMAC_DMACA4_BC2                   *((volatile unsigned int*)(0x42C00A48UL))
+#define bFM3_DMAC_DMACA4_BC3                   *((volatile unsigned int*)(0x42C00A4CUL))
+#define bFM3_DMAC_DMACA4_IS0                   *((volatile unsigned int*)(0x42C00A5CUL))
+#define bFM3_DMAC_DMACA4_IS1                   *((volatile unsigned int*)(0x42C00A60UL))
+#define bFM3_DMAC_DMACA4_IS2                   *((volatile unsigned int*)(0x42C00A64UL))
+#define bFM3_DMAC_DMACA4_IS3                   *((volatile unsigned int*)(0x42C00A68UL))
+#define bFM3_DMAC_DMACA4_IS4                   *((volatile unsigned int*)(0x42C00A6CUL))
+#define bFM3_DMAC_DMACA4_IS5                   *((volatile unsigned int*)(0x42C00A70UL))
+#define bFM3_DMAC_DMACA4_ST                    *((volatile unsigned int*)(0x42C00A74UL))
+#define bFM3_DMAC_DMACA4_PB                    *((volatile unsigned int*)(0x42C00A78UL))
+#define bFM3_DMAC_DMACA4_EB                    *((volatile unsigned int*)(0x42C00A7CUL))
+#define bFM3_DMAC_DMACB4_EM                    *((volatile unsigned int*)(0x42C00A80UL))
+#define bFM3_DMAC_DMACB4_SS0                   *((volatile unsigned int*)(0x42C00AC0UL))
+#define bFM3_DMAC_DMACB4_SS1                   *((volatile unsigned int*)(0x42C00AC4UL))
+#define bFM3_DMAC_DMACB4_SS2                   *((volatile unsigned int*)(0x42C00AC8UL))
+#define bFM3_DMAC_DMACB4_CI                    *((volatile unsigned int*)(0x42C00ACCUL))
+#define bFM3_DMAC_DMACB4_EI                    *((volatile unsigned int*)(0x42C00AD0UL))
+#define bFM3_DMAC_DMACB4_RD                    *((volatile unsigned int*)(0x42C00AD4UL))
+#define bFM3_DMAC_DMACB4_RS                    *((volatile unsigned int*)(0x42C00AD8UL))
+#define bFM3_DMAC_DMACB4_RC                    *((volatile unsigned int*)(0x42C00ADCUL))
+#define bFM3_DMAC_DMACB4_FD                    *((volatile unsigned int*)(0x42C00AE0UL))
+#define bFM3_DMAC_DMACB4_FS                    *((volatile unsigned int*)(0x42C00AE4UL))
+#define bFM3_DMAC_DMACB4_TW0                   *((volatile unsigned int*)(0x42C00AE8UL))
+#define bFM3_DMAC_DMACB4_TW1                   *((volatile unsigned int*)(0x42C00AECUL))
+#define bFM3_DMAC_DMACB4_MS0                   *((volatile unsigned int*)(0x42C00AF0UL))
+#define bFM3_DMAC_DMACB4_MS1                   *((volatile unsigned int*)(0x42C00AF4UL))
+#define bFM3_DMAC_DMACA5_TC0                   *((volatile unsigned int*)(0x42C00C00UL))
+#define bFM3_DMAC_DMACA5_TC1                   *((volatile unsigned int*)(0x42C00C04UL))
+#define bFM3_DMAC_DMACA5_TC2                   *((volatile unsigned int*)(0x42C00C08UL))
+#define bFM3_DMAC_DMACA5_TC3                   *((volatile unsigned int*)(0x42C00C0CUL))
+#define bFM3_DMAC_DMACA5_TC4                   *((volatile unsigned int*)(0x42C00C10UL))
+#define bFM3_DMAC_DMACA5_TC5                   *((volatile unsigned int*)(0x42C00C14UL))
+#define bFM3_DMAC_DMACA5_TC6                   *((volatile unsigned int*)(0x42C00C18UL))
+#define bFM3_DMAC_DMACA5_TC7                   *((volatile unsigned int*)(0x42C00C1CUL))
+#define bFM3_DMAC_DMACA5_TC8                   *((volatile unsigned int*)(0x42C00C20UL))
+#define bFM3_DMAC_DMACA5_TC9                   *((volatile unsigned int*)(0x42C00C24UL))
+#define bFM3_DMAC_DMACA5_TC10                  *((volatile unsigned int*)(0x42C00C28UL))
+#define bFM3_DMAC_DMACA5_TC11                  *((volatile unsigned int*)(0x42C00C2CUL))
+#define bFM3_DMAC_DMACA5_TC12                  *((volatile unsigned int*)(0x42C00C30UL))
+#define bFM3_DMAC_DMACA5_TC13                  *((volatile unsigned int*)(0x42C00C34UL))
+#define bFM3_DMAC_DMACA5_TC14                  *((volatile unsigned int*)(0x42C00C38UL))
+#define bFM3_DMAC_DMACA5_TC15                  *((volatile unsigned int*)(0x42C00C3CUL))
+#define bFM3_DMAC_DMACA5_BC0                   *((volatile unsigned int*)(0x42C00C40UL))
+#define bFM3_DMAC_DMACA5_BC1                   *((volatile unsigned int*)(0x42C00C44UL))
+#define bFM3_DMAC_DMACA5_BC2                   *((volatile unsigned int*)(0x42C00C48UL))
+#define bFM3_DMAC_DMACA5_BC3                   *((volatile unsigned int*)(0x42C00C4CUL))
+#define bFM3_DMAC_DMACA5_IS0                   *((volatile unsigned int*)(0x42C00C5CUL))
+#define bFM3_DMAC_DMACA5_IS1                   *((volatile unsigned int*)(0x42C00C60UL))
+#define bFM3_DMAC_DMACA5_IS2                   *((volatile unsigned int*)(0x42C00C64UL))
+#define bFM3_DMAC_DMACA5_IS3                   *((volatile unsigned int*)(0x42C00C68UL))
+#define bFM3_DMAC_DMACA5_IS4                   *((volatile unsigned int*)(0x42C00C6CUL))
+#define bFM3_DMAC_DMACA5_IS5                   *((volatile unsigned int*)(0x42C00C70UL))
+#define bFM3_DMAC_DMACA5_ST                    *((volatile unsigned int*)(0x42C00C74UL))
+#define bFM3_DMAC_DMACA5_PB                    *((volatile unsigned int*)(0x42C00C78UL))
+#define bFM3_DMAC_DMACA5_EB                    *((volatile unsigned int*)(0x42C00C7CUL))
+#define bFM3_DMAC_DMACB5_EM                    *((volatile unsigned int*)(0x42C00C80UL))
+#define bFM3_DMAC_DMACB5_SS0                   *((volatile unsigned int*)(0x42C00CC0UL))
+#define bFM3_DMAC_DMACB5_SS1                   *((volatile unsigned int*)(0x42C00CC4UL))
+#define bFM3_DMAC_DMACB5_SS2                   *((volatile unsigned int*)(0x42C00CC8UL))
+#define bFM3_DMAC_DMACB5_CI                    *((volatile unsigned int*)(0x42C00CCCUL))
+#define bFM3_DMAC_DMACB5_EI                    *((volatile unsigned int*)(0x42C00CD0UL))
+#define bFM3_DMAC_DMACB5_RD                    *((volatile unsigned int*)(0x42C00CD4UL))
+#define bFM3_DMAC_DMACB5_RS                    *((volatile unsigned int*)(0x42C00CD8UL))
+#define bFM3_DMAC_DMACB5_RC                    *((volatile unsigned int*)(0x42C00CDCUL))
+#define bFM3_DMAC_DMACB5_FD                    *((volatile unsigned int*)(0x42C00CE0UL))
+#define bFM3_DMAC_DMACB5_FS                    *((volatile unsigned int*)(0x42C00CE4UL))
+#define bFM3_DMAC_DMACB5_TW0                   *((volatile unsigned int*)(0x42C00CE8UL))
+#define bFM3_DMAC_DMACB5_TW1                   *((volatile unsigned int*)(0x42C00CECUL))
+#define bFM3_DMAC_DMACB5_MS0                   *((volatile unsigned int*)(0x42C00CF0UL))
+#define bFM3_DMAC_DMACB5_MS1                   *((volatile unsigned int*)(0x42C00CF4UL))
+#define bFM3_DMAC_DMACA6_TC0                   *((volatile unsigned int*)(0x42C00E00UL))
+#define bFM3_DMAC_DMACA6_TC1                   *((volatile unsigned int*)(0x42C00E04UL))
+#define bFM3_DMAC_DMACA6_TC2                   *((volatile unsigned int*)(0x42C00E08UL))
+#define bFM3_DMAC_DMACA6_TC3                   *((volatile unsigned int*)(0x42C00E0CUL))
+#define bFM3_DMAC_DMACA6_TC4                   *((volatile unsigned int*)(0x42C00E10UL))
+#define bFM3_DMAC_DMACA6_TC5                   *((volatile unsigned int*)(0x42C00E14UL))
+#define bFM3_DMAC_DMACA6_TC6                   *((volatile unsigned int*)(0x42C00E18UL))
+#define bFM3_DMAC_DMACA6_TC7                   *((volatile unsigned int*)(0x42C00E1CUL))
+#define bFM3_DMAC_DMACA6_TC8                   *((volatile unsigned int*)(0x42C00E20UL))
+#define bFM3_DMAC_DMACA6_TC9                   *((volatile unsigned int*)(0x42C00E24UL))
+#define bFM3_DMAC_DMACA6_TC10                  *((volatile unsigned int*)(0x42C00E28UL))
+#define bFM3_DMAC_DMACA6_TC11                  *((volatile unsigned int*)(0x42C00E2CUL))
+#define bFM3_DMAC_DMACA6_TC12                  *((volatile unsigned int*)(0x42C00E30UL))
+#define bFM3_DMAC_DMACA6_TC13                  *((volatile unsigned int*)(0x42C00E34UL))
+#define bFM3_DMAC_DMACA6_TC14                  *((volatile unsigned int*)(0x42C00E38UL))
+#define bFM3_DMAC_DMACA6_TC15                  *((volatile unsigned int*)(0x42C00E3CUL))
+#define bFM3_DMAC_DMACA6_BC0                   *((volatile unsigned int*)(0x42C00E40UL))
+#define bFM3_DMAC_DMACA6_BC1                   *((volatile unsigned int*)(0x42C00E44UL))
+#define bFM3_DMAC_DMACA6_BC2                   *((volatile unsigned int*)(0x42C00E48UL))
+#define bFM3_DMAC_DMACA6_BC3                   *((volatile unsigned int*)(0x42C00E4CUL))
+#define bFM3_DMAC_DMACA6_IS0                   *((volatile unsigned int*)(0x42C00E5CUL))
+#define bFM3_DMAC_DMACA6_IS1                   *((volatile unsigned int*)(0x42C00E60UL))
+#define bFM3_DMAC_DMACA6_IS2                   *((volatile unsigned int*)(0x42C00E64UL))
+#define bFM3_DMAC_DMACA6_IS3                   *((volatile unsigned int*)(0x42C00E68UL))
+#define bFM3_DMAC_DMACA6_IS4                   *((volatile unsigned int*)(0x42C00E6CUL))
+#define bFM3_DMAC_DMACA6_IS5                   *((volatile unsigned int*)(0x42C00E70UL))
+#define bFM3_DMAC_DMACA6_ST                    *((volatile unsigned int*)(0x42C00E74UL))
+#define bFM3_DMAC_DMACA6_PB                    *((volatile unsigned int*)(0x42C00E78UL))
+#define bFM3_DMAC_DMACA6_EB                    *((volatile unsigned int*)(0x42C00E7CUL))
+#define bFM3_DMAC_DMACB6_EM                    *((volatile unsigned int*)(0x42C00E80UL))
+#define bFM3_DMAC_DMACB6_SS0                   *((volatile unsigned int*)(0x42C00EC0UL))
+#define bFM3_DMAC_DMACB6_SS1                   *((volatile unsigned int*)(0x42C00EC4UL))
+#define bFM3_DMAC_DMACB6_SS2                   *((volatile unsigned int*)(0x42C00EC8UL))
+#define bFM3_DMAC_DMACB6_CI                    *((volatile unsigned int*)(0x42C00ECCUL))
+#define bFM3_DMAC_DMACB6_EI                    *((volatile unsigned int*)(0x42C00ED0UL))
+#define bFM3_DMAC_DMACB6_RD                    *((volatile unsigned int*)(0x42C00ED4UL))
+#define bFM3_DMAC_DMACB6_RS                    *((volatile unsigned int*)(0x42C00ED8UL))
+#define bFM3_DMAC_DMACB6_RC                    *((volatile unsigned int*)(0x42C00EDCUL))
+#define bFM3_DMAC_DMACB6_FD                    *((volatile unsigned int*)(0x42C00EE0UL))
+#define bFM3_DMAC_DMACB6_FS                    *((volatile unsigned int*)(0x42C00EE4UL))
+#define bFM3_DMAC_DMACB6_TW0                   *((volatile unsigned int*)(0x42C00EE8UL))
+#define bFM3_DMAC_DMACB6_TW1                   *((volatile unsigned int*)(0x42C00EECUL))
+#define bFM3_DMAC_DMACB6_MS0                   *((volatile unsigned int*)(0x42C00EF0UL))
+#define bFM3_DMAC_DMACB6_MS1                   *((volatile unsigned int*)(0x42C00EF4UL))
+#define bFM3_DMAC_DMACA7_TC0                   *((volatile unsigned int*)(0x42C01000UL))
+#define bFM3_DMAC_DMACA7_TC1                   *((volatile unsigned int*)(0x42C01004UL))
+#define bFM3_DMAC_DMACA7_TC2                   *((volatile unsigned int*)(0x42C01008UL))
+#define bFM3_DMAC_DMACA7_TC3                   *((volatile unsigned int*)(0x42C0100CUL))
+#define bFM3_DMAC_DMACA7_TC4                   *((volatile unsigned int*)(0x42C01010UL))
+#define bFM3_DMAC_DMACA7_TC5                   *((volatile unsigned int*)(0x42C01014UL))
+#define bFM3_DMAC_DMACA7_TC6                   *((volatile unsigned int*)(0x42C01018UL))
+#define bFM3_DMAC_DMACA7_TC7                   *((volatile unsigned int*)(0x42C0101CUL))
+#define bFM3_DMAC_DMACA7_TC8                   *((volatile unsigned int*)(0x42C01020UL))
+#define bFM3_DMAC_DMACA7_TC9                   *((volatile unsigned int*)(0x42C01024UL))
+#define bFM3_DMAC_DMACA7_TC10                  *((volatile unsigned int*)(0x42C01028UL))
+#define bFM3_DMAC_DMACA7_TC11                  *((volatile unsigned int*)(0x42C0102CUL))
+#define bFM3_DMAC_DMACA7_TC12                  *((volatile unsigned int*)(0x42C01030UL))
+#define bFM3_DMAC_DMACA7_TC13                  *((volatile unsigned int*)(0x42C01034UL))
+#define bFM3_DMAC_DMACA7_TC14                  *((volatile unsigned int*)(0x42C01038UL))
+#define bFM3_DMAC_DMACA7_TC15                  *((volatile unsigned int*)(0x42C0103CUL))
+#define bFM3_DMAC_DMACA7_BC0                   *((volatile unsigned int*)(0x42C01040UL))
+#define bFM3_DMAC_DMACA7_BC1                   *((volatile unsigned int*)(0x42C01044UL))
+#define bFM3_DMAC_DMACA7_BC2                   *((volatile unsigned int*)(0x42C01048UL))
+#define bFM3_DMAC_DMACA7_BC3                   *((volatile unsigned int*)(0x42C0104CUL))
+#define bFM3_DMAC_DMACA7_IS0                   *((volatile unsigned int*)(0x42C0105CUL))
+#define bFM3_DMAC_DMACA7_IS1                   *((volatile unsigned int*)(0x42C01060UL))
+#define bFM3_DMAC_DMACA7_IS2                   *((volatile unsigned int*)(0x42C01064UL))
+#define bFM3_DMAC_DMACA7_IS3                   *((volatile unsigned int*)(0x42C01068UL))
+#define bFM3_DMAC_DMACA7_IS4                   *((volatile unsigned int*)(0x42C0106CUL))
+#define bFM3_DMAC_DMACA7_IS5                   *((volatile unsigned int*)(0x42C01070UL))
+#define bFM3_DMAC_DMACA7_ST                    *((volatile unsigned int*)(0x42C01074UL))
+#define bFM3_DMAC_DMACA7_PB                    *((volatile unsigned int*)(0x42C01078UL))
+#define bFM3_DMAC_DMACA7_EB                    *((volatile unsigned int*)(0x42C0107CUL))
+#define bFM3_DMAC_DMACB7_EM                    *((volatile unsigned int*)(0x42C01080UL))
+#define bFM3_DMAC_DMACB7_SS0                   *((volatile unsigned int*)(0x42C010C0UL))
+#define bFM3_DMAC_DMACB7_SS1                   *((volatile unsigned int*)(0x42C010C4UL))
+#define bFM3_DMAC_DMACB7_SS2                   *((volatile unsigned int*)(0x42C010C8UL))
+#define bFM3_DMAC_DMACB7_CI                    *((volatile unsigned int*)(0x42C010CCUL))
+#define bFM3_DMAC_DMACB7_EI                    *((volatile unsigned int*)(0x42C010D0UL))
+#define bFM3_DMAC_DMACB7_RD                    *((volatile unsigned int*)(0x42C010D4UL))
+#define bFM3_DMAC_DMACB7_RS                    *((volatile unsigned int*)(0x42C010D8UL))
+#define bFM3_DMAC_DMACB7_RC                    *((volatile unsigned int*)(0x42C010DCUL))
+#define bFM3_DMAC_DMACB7_FD                    *((volatile unsigned int*)(0x42C010E0UL))
+#define bFM3_DMAC_DMACB7_FS                    *((volatile unsigned int*)(0x42C010E4UL))
+#define bFM3_DMAC_DMACB7_TW0                   *((volatile unsigned int*)(0x42C010E8UL))
+#define bFM3_DMAC_DMACB7_TW1                   *((volatile unsigned int*)(0x42C010ECUL))
+#define bFM3_DMAC_DMACB7_MS0                   *((volatile unsigned int*)(0x42C010F0UL))
+#define bFM3_DMAC_DMACB7_MS1                   *((volatile unsigned int*)(0x42C010F4UL))
+
+/* ETHERNET-MAC0 registers*/
+#define bFM3_ETHERNET_MAC0_MCR_RE              *((volatile unsigned int*)(0x42C80008UL))
+#define bFM3_ETHERNET_MAC0_MCR_TE              *((volatile unsigned int*)(0x42C8000CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DC              *((volatile unsigned int*)(0x42C80010UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL0             *((volatile unsigned int*)(0x42C80014UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL1             *((volatile unsigned int*)(0x42C80018UL))
+#define bFM3_ETHERNET_MAC0_MCR_ACS             *((volatile unsigned int*)(0x42C8001CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LUD             *((volatile unsigned int*)(0x42C80020UL))
+#define bFM3_ETHERNET_MAC0_MCR_DR              *((volatile unsigned int*)(0x42C80024UL))
+#define bFM3_ETHERNET_MAC0_MCR_IPC             *((volatile unsigned int*)(0x42C80028UL))
+#define bFM3_ETHERNET_MAC0_MCR_DM              *((volatile unsigned int*)(0x42C8002CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LM              *((volatile unsigned int*)(0x42C80030UL))
+#define bFM3_ETHERNET_MAC0_MCR_DO              *((volatile unsigned int*)(0x42C80034UL))
+#define bFM3_ETHERNET_MAC0_MCR_FES             *((volatile unsigned int*)(0x42C80038UL))
+#define bFM3_ETHERNET_MAC0_MCR_PS              *((volatile unsigned int*)(0x42C8003CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DCRS            *((volatile unsigned int*)(0x42C80040UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG0            *((volatile unsigned int*)(0x42C80044UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG1            *((volatile unsigned int*)(0x42C80048UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG2            *((volatile unsigned int*)(0x42C8004CUL))
+#define bFM3_ETHERNET_MAC0_MCR_JE              *((volatile unsigned int*)(0x42C80050UL))
+#define bFM3_ETHERNET_MAC0_MCR_BE              *((volatile unsigned int*)(0x42C80054UL))
+#define bFM3_ETHERNET_MAC0_MCR_JD              *((volatile unsigned int*)(0x42C80058UL))
+#define bFM3_ETHERNET_MAC0_MCR_WD              *((volatile unsigned int*)(0x42C8005CUL))
+#define bFM3_ETHERNET_MAC0_MCR_TC              *((volatile unsigned int*)(0x42C80060UL))
+#define bFM3_ETHERNET_MAC0_MCR_CST             *((volatile unsigned int*)(0x42C80064UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PR             *((volatile unsigned int*)(0x42C80080UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HUC            *((volatile unsigned int*)(0x42C80084UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HMC            *((volatile unsigned int*)(0x42C80088UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DAIF           *((volatile unsigned int*)(0x42C8008CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_PM             *((volatile unsigned int*)(0x42C80090UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DB             *((volatile unsigned int*)(0x42C80094UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF0           *((volatile unsigned int*)(0x42C80098UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF1           *((volatile unsigned int*)(0x42C8009CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAIF           *((volatile unsigned int*)(0x42C800A0UL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAF            *((volatile unsigned int*)(0x42C800A4UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HPF            *((volatile unsigned int*)(0x42C800A8UL))
+#define bFM3_ETHERNET_MAC0_MFFR_RA             *((volatile unsigned int*)(0x42C800FCUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH0          *((volatile unsigned int*)(0x42C80100UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH1          *((volatile unsigned int*)(0x42C80104UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH2          *((volatile unsigned int*)(0x42C80108UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH3          *((volatile unsigned int*)(0x42C8010CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH4          *((volatile unsigned int*)(0x42C80110UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH5          *((volatile unsigned int*)(0x42C80114UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH6          *((volatile unsigned int*)(0x42C80118UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH7          *((volatile unsigned int*)(0x42C8011CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH8          *((volatile unsigned int*)(0x42C80120UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH9          *((volatile unsigned int*)(0x42C80124UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH10         *((volatile unsigned int*)(0x42C80128UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH11         *((volatile unsigned int*)(0x42C8012CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH12         *((volatile unsigned int*)(0x42C80130UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH13         *((volatile unsigned int*)(0x42C80134UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH14         *((volatile unsigned int*)(0x42C80138UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH15         *((volatile unsigned int*)(0x42C8013CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH16         *((volatile unsigned int*)(0x42C80140UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH17         *((volatile unsigned int*)(0x42C80144UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH18         *((volatile unsigned int*)(0x42C80148UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH19         *((volatile unsigned int*)(0x42C8014CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH20         *((volatile unsigned int*)(0x42C80150UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH21         *((volatile unsigned int*)(0x42C80154UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH22         *((volatile unsigned int*)(0x42C80158UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH23         *((volatile unsigned int*)(0x42C8015CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH24         *((volatile unsigned int*)(0x42C80160UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH25         *((volatile unsigned int*)(0x42C80164UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH26         *((volatile unsigned int*)(0x42C80168UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH27         *((volatile unsigned int*)(0x42C8016CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH28         *((volatile unsigned int*)(0x42C80170UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH29         *((volatile unsigned int*)(0x42C80174UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH30         *((volatile unsigned int*)(0x42C80178UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH31         *((volatile unsigned int*)(0x42C8017CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL0          *((volatile unsigned int*)(0x42C80180UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL1          *((volatile unsigned int*)(0x42C80184UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL2          *((volatile unsigned int*)(0x42C80188UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL3          *((volatile unsigned int*)(0x42C8018CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL4          *((volatile unsigned int*)(0x42C80190UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL5          *((volatile unsigned int*)(0x42C80194UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL6          *((volatile unsigned int*)(0x42C80198UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL7          *((volatile unsigned int*)(0x42C8019CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL8          *((volatile unsigned int*)(0x42C801A0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL9          *((volatile unsigned int*)(0x42C801A4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL10         *((volatile unsigned int*)(0x42C801A8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL11         *((volatile unsigned int*)(0x42C801ACUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL12         *((volatile unsigned int*)(0x42C801B0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL13         *((volatile unsigned int*)(0x42C801B4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL14         *((volatile unsigned int*)(0x42C801B8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL15         *((volatile unsigned int*)(0x42C801BCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL16         *((volatile unsigned int*)(0x42C801C0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL17         *((volatile unsigned int*)(0x42C801C4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL18         *((volatile unsigned int*)(0x42C801C8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL19         *((volatile unsigned int*)(0x42C801CCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL20         *((volatile unsigned int*)(0x42C801D0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL21         *((volatile unsigned int*)(0x42C801D4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL22         *((volatile unsigned int*)(0x42C801D8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL23         *((volatile unsigned int*)(0x42C801DCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL24         *((volatile unsigned int*)(0x42C801E0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL25         *((volatile unsigned int*)(0x42C801E4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL26         *((volatile unsigned int*)(0x42C801E8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL27         *((volatile unsigned int*)(0x42C801ECUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL28         *((volatile unsigned int*)(0x42C801F0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL29         *((volatile unsigned int*)(0x42C801F4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL30         *((volatile unsigned int*)(0x42C801F8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL31         *((volatile unsigned int*)(0x42C801FCUL))
+#define bFM3_ETHERNET_MAC0_GAR_GB              *((volatile unsigned int*)(0x42C80200UL))
+#define bFM3_ETHERNET_MAC0_GAR_GW              *((volatile unsigned int*)(0x42C80204UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR0             *((volatile unsigned int*)(0x42C80208UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR1             *((volatile unsigned int*)(0x42C8020CUL))
+#define bFM3_ETHERNET_MAC0_GAR_CR2             *((volatile unsigned int*)(0x42C80210UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR3             *((volatile unsigned int*)(0x42C80214UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR0             *((volatile unsigned int*)(0x42C80218UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR1             *((volatile unsigned int*)(0x42C8021CUL))
+#define bFM3_ETHERNET_MAC0_GAR_GR2             *((volatile unsigned int*)(0x42C80220UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR3             *((volatile unsigned int*)(0x42C80224UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR4             *((volatile unsigned int*)(0x42C80228UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA0             *((volatile unsigned int*)(0x42C8022CUL))
+#define bFM3_ETHERNET_MAC0_GAR_PA1             *((volatile unsigned int*)(0x42C80230UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA2             *((volatile unsigned int*)(0x42C80234UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA3             *((volatile unsigned int*)(0x42C80238UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA4             *((volatile unsigned int*)(0x42C8023CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD0             *((volatile unsigned int*)(0x42C80280UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD1             *((volatile unsigned int*)(0x42C80284UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD2             *((volatile unsigned int*)(0x42C80288UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD3             *((volatile unsigned int*)(0x42C8028CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD4             *((volatile unsigned int*)(0x42C80290UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD5             *((volatile unsigned int*)(0x42C80294UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD6             *((volatile unsigned int*)(0x42C80298UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD7             *((volatile unsigned int*)(0x42C8029CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD8             *((volatile unsigned int*)(0x42C802A0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD9             *((volatile unsigned int*)(0x42C802A4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD10            *((volatile unsigned int*)(0x42C802A8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD11            *((volatile unsigned int*)(0x42C802ACUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD12            *((volatile unsigned int*)(0x42C802B0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD13            *((volatile unsigned int*)(0x42C802B4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD14            *((volatile unsigned int*)(0x42C802B8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD15            *((volatile unsigned int*)(0x42C802BCUL))
+#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA         *((volatile unsigned int*)(0x42C80300UL))
+#define bFM3_ETHERNET_MAC0_FCR_TFE             *((volatile unsigned int*)(0x42C80304UL))
+#define bFM3_ETHERNET_MAC0_FCR_RFE             *((volatile unsigned int*)(0x42C80308UL))
+#define bFM3_ETHERNET_MAC0_FCR_UP              *((volatile unsigned int*)(0x42C8030CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT0            *((volatile unsigned int*)(0x42C80310UL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT1            *((volatile unsigned int*)(0x42C80314UL))
+#define bFM3_ETHERNET_MAC0_FCR_DZPQ            *((volatile unsigned int*)(0x42C8031CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT0             *((volatile unsigned int*)(0x42C80340UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT1             *((volatile unsigned int*)(0x42C80344UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT2             *((volatile unsigned int*)(0x42C80348UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT3             *((volatile unsigned int*)(0x42C8034CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT4             *((volatile unsigned int*)(0x42C80350UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT5             *((volatile unsigned int*)(0x42C80354UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT6             *((volatile unsigned int*)(0x42C80358UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT7             *((volatile unsigned int*)(0x42C8035CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT8             *((volatile unsigned int*)(0x42C80360UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT9             *((volatile unsigned int*)(0x42C80364UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT10            *((volatile unsigned int*)(0x42C80368UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT11            *((volatile unsigned int*)(0x42C8036CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT12            *((volatile unsigned int*)(0x42C80370UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT13            *((volatile unsigned int*)(0x42C80374UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT14            *((volatile unsigned int*)(0x42C80378UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT15            *((volatile unsigned int*)(0x42C8037CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL0             *((volatile unsigned int*)(0x42C80380UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL1             *((volatile unsigned int*)(0x42C80384UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL2             *((volatile unsigned int*)(0x42C80388UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL3             *((volatile unsigned int*)(0x42C8038CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL4             *((volatile unsigned int*)(0x42C80390UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL5             *((volatile unsigned int*)(0x42C80394UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL6             *((volatile unsigned int*)(0x42C80398UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL7             *((volatile unsigned int*)(0x42C8039CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL8             *((volatile unsigned int*)(0x42C803A0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL9             *((volatile unsigned int*)(0x42C803A4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL10            *((volatile unsigned int*)(0x42C803A8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL11            *((volatile unsigned int*)(0x42C803ACUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL12            *((volatile unsigned int*)(0x42C803B0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL13            *((volatile unsigned int*)(0x42C803B4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL14            *((volatile unsigned int*)(0x42C803B8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL15            *((volatile unsigned int*)(0x42C803BCUL))
+#define bFM3_ETHERNET_MAC0_VTR_ETV             *((volatile unsigned int*)(0x42C803C0UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42C80500UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42C80504UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42C80508UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42C8050CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42C80510UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42C80514UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42C80518UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42C8051CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42C80520UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42C80524UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42C80528UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42C8052CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42C80530UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42C80534UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42C80538UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42C8053CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42C80540UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42C80544UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42C80548UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42C8054CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42C80550UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42C80554UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42C80558UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42C8055CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42C80560UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42C80564UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42C80568UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42C8056CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42C80570UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42C80574UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42C80578UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42C8057CUL))
+#define bFM3_ETHERNET_MAC0_PMTR_PD             *((volatile unsigned int*)(0x42C80580UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPE            *((volatile unsigned int*)(0x42C80584UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WFE            *((volatile unsigned int*)(0x42C80588UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPR            *((volatile unsigned int*)(0x42C80594UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WPR            *((volatile unsigned int*)(0x42C80598UL))
+#define bFM3_ETHERNET_MAC0_PMTR_GU             *((volatile unsigned int*)(0x42C805A4UL))
+#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42C805FCUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42C80600UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42C80604UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42C80608UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42C8060CUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST       *((volatile unsigned int*)(0x42C80620UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST       *((volatile unsigned int*)(0x42C80624UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN        *((volatile unsigned int*)(0x42C80640UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLS          *((volatile unsigned int*)(0x42C80644UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN        *((volatile unsigned int*)(0x42C80648UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA       *((volatile unsigned int*)(0x42C8064CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT0         *((volatile unsigned int*)(0x42C80680UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT1         *((volatile unsigned int*)(0x42C80684UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT2         *((volatile unsigned int*)(0x42C80688UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT3         *((volatile unsigned int*)(0x42C8068CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT4         *((volatile unsigned int*)(0x42C80690UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT5         *((volatile unsigned int*)(0x42C80694UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT6         *((volatile unsigned int*)(0x42C80698UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT7         *((volatile unsigned int*)(0x42C8069CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT8         *((volatile unsigned int*)(0x42C806A0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT9         *((volatile unsigned int*)(0x42C806A4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT10        *((volatile unsigned int*)(0x42C806A8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT11        *((volatile unsigned int*)(0x42C806ACUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT12        *((volatile unsigned int*)(0x42C806B0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT13        *((volatile unsigned int*)(0x42C806B4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT14        *((volatile unsigned int*)(0x42C806B8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT15        *((volatile unsigned int*)(0x42C806BCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT0         *((volatile unsigned int*)(0x42C806C0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT1         *((volatile unsigned int*)(0x42C806C4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT2         *((volatile unsigned int*)(0x42C806C8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT3         *((volatile unsigned int*)(0x42C806CCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT4         *((volatile unsigned int*)(0x42C806D0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT5         *((volatile unsigned int*)(0x42C806D4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT6         *((volatile unsigned int*)(0x42C806D8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT7         *((volatile unsigned int*)(0x42C806DCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT8         *((volatile unsigned int*)(0x42C806E0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT9         *((volatile unsigned int*)(0x42C806E4UL))
+#define bFM3_ETHERNET_MAC0_ISR_RGIS            *((volatile unsigned int*)(0x42C80700UL))
+#define bFM3_ETHERNET_MAC0_ISR_PIS             *((volatile unsigned int*)(0x42C8070CUL))
+#define bFM3_ETHERNET_MAC0_ISR_MIS             *((volatile unsigned int*)(0x42C80710UL))
+#define bFM3_ETHERNET_MAC0_ISR_RIS             *((volatile unsigned int*)(0x42C80714UL))
+#define bFM3_ETHERNET_MAC0_ISR_TIS             *((volatile unsigned int*)(0x42C80718UL))
+#define bFM3_ETHERNET_MAC0_ISR_COIS            *((volatile unsigned int*)(0x42C8071CUL))
+#define bFM3_ETHERNET_MAC0_ISR_TSIS            *((volatile unsigned int*)(0x42C80724UL))
+#define bFM3_ETHERNET_MAC0_ISR_LPIIS           *((volatile unsigned int*)(0x42C80728UL))
+#define bFM3_ETHERNET_MAC0_IMR_RGIM            *((volatile unsigned int*)(0x42C80780UL))
+#define bFM3_ETHERNET_MAC0_IMR_PIM             *((volatile unsigned int*)(0x42C8078CUL))
+#define bFM3_ETHERNET_MAC0_IMR_TSIM            *((volatile unsigned int*)(0x42C80794UL))
+#define bFM3_ETHERNET_MAC0_IMR_LPIIM           *((volatile unsigned int*)(0x42C80798UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A32           *((volatile unsigned int*)(0x42C80800UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A33           *((volatile unsigned int*)(0x42C80804UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A34           *((volatile unsigned int*)(0x42C80808UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A35           *((volatile unsigned int*)(0x42C8080CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A36           *((volatile unsigned int*)(0x42C80810UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A37           *((volatile unsigned int*)(0x42C80814UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A38           *((volatile unsigned int*)(0x42C80818UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A39           *((volatile unsigned int*)(0x42C8081CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A40           *((volatile unsigned int*)(0x42C80820UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A41           *((volatile unsigned int*)(0x42C80824UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A42           *((volatile unsigned int*)(0x42C80828UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A43           *((volatile unsigned int*)(0x42C8082CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A44           *((volatile unsigned int*)(0x42C80830UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A45           *((volatile unsigned int*)(0x42C80834UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A46           *((volatile unsigned int*)(0x42C80838UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A47           *((volatile unsigned int*)(0x42C8083CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_MO            *((volatile unsigned int*)(0x42C8087CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A0            *((volatile unsigned int*)(0x42C80880UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A1            *((volatile unsigned int*)(0x42C80884UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A2            *((volatile unsigned int*)(0x42C80888UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A3            *((volatile unsigned int*)(0x42C8088CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A4            *((volatile unsigned int*)(0x42C80890UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A5            *((volatile unsigned int*)(0x42C80894UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A6            *((volatile unsigned int*)(0x42C80898UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A7            *((volatile unsigned int*)(0x42C8089CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A8            *((volatile unsigned int*)(0x42C808A0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A9            *((volatile unsigned int*)(0x42C808A4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A10           *((volatile unsigned int*)(0x42C808A8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A11           *((volatile unsigned int*)(0x42C808ACUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A12           *((volatile unsigned int*)(0x42C808B0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A13           *((volatile unsigned int*)(0x42C808B4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A14           *((volatile unsigned int*)(0x42C808B8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A15           *((volatile unsigned int*)(0x42C808BCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A16           *((volatile unsigned int*)(0x42C808C0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A17           *((volatile unsigned int*)(0x42C808C4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A18           *((volatile unsigned int*)(0x42C808C8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A19           *((volatile unsigned int*)(0x42C808CCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A20           *((volatile unsigned int*)(0x42C808D0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A21           *((volatile unsigned int*)(0x42C808D4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A22           *((volatile unsigned int*)(0x42C808D8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A23           *((volatile unsigned int*)(0x42C808DCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A24           *((volatile unsigned int*)(0x42C808E0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A25           *((volatile unsigned int*)(0x42C808E4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A26           *((volatile unsigned int*)(0x42C808E8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A27           *((volatile unsigned int*)(0x42C808ECUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A28           *((volatile unsigned int*)(0x42C808F0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A29           *((volatile unsigned int*)(0x42C808F4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A30           *((volatile unsigned int*)(0x42C808F8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A31           *((volatile unsigned int*)(0x42C808FCUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A32           *((volatile unsigned int*)(0x42C80900UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A33           *((volatile unsigned int*)(0x42C80904UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A34           *((volatile unsigned int*)(0x42C80908UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A35           *((volatile unsigned int*)(0x42C8090CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A36           *((volatile unsigned int*)(0x42C80910UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A37           *((volatile unsigned int*)(0x42C80914UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A38           *((volatile unsigned int*)(0x42C80918UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A39           *((volatile unsigned int*)(0x42C8091CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A40           *((volatile unsigned int*)(0x42C80920UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A41           *((volatile unsigned int*)(0x42C80924UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A42           *((volatile unsigned int*)(0x42C80928UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A43           *((volatile unsigned int*)(0x42C8092CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A44           *((volatile unsigned int*)(0x42C80930UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A45           *((volatile unsigned int*)(0x42C80934UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A46           *((volatile unsigned int*)(0x42C80938UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A47           *((volatile unsigned int*)(0x42C8093CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC0          *((volatile unsigned int*)(0x42C80960UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC1          *((volatile unsigned int*)(0x42C80964UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC2          *((volatile unsigned int*)(0x42C80968UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC3          *((volatile unsigned int*)(0x42C8096CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC4          *((volatile unsigned int*)(0x42C80970UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC5          *((volatile unsigned int*)(0x42C80974UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_SA            *((volatile unsigned int*)(0x42C80978UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_AE            *((volatile unsigned int*)(0x42C8097CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A0            *((volatile unsigned int*)(0x42C80980UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A1            *((volatile unsigned int*)(0x42C80984UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A2            *((volatile unsigned int*)(0x42C80988UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A3            *((volatile unsigned int*)(0x42C8098CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A4            *((volatile unsigned int*)(0x42C80990UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A5            *((volatile unsigned int*)(0x42C80994UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A6            *((volatile unsigned int*)(0x42C80998UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A7            *((volatile unsigned int*)(0x42C8099CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A8            *((volatile unsigned int*)(0x42C809A0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A9            *((volatile unsigned int*)(0x42C809A4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A10           *((volatile unsigned int*)(0x42C809A8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A11           *((volatile unsigned int*)(0x42C809ACUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A12           *((volatile unsigned int*)(0x42C809B0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A13           *((volatile unsigned int*)(0x42C809B4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A14           *((volatile unsigned int*)(0x42C809B8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A15           *((volatile unsigned int*)(0x42C809BCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A16           *((volatile unsigned int*)(0x42C809C0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A17           *((volatile unsigned int*)(0x42C809C4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A18           *((volatile unsigned int*)(0x42C809C8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A19           *((volatile unsigned int*)(0x42C809CCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A20           *((volatile unsigned int*)(0x42C809D0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A21           *((volatile unsigned int*)(0x42C809D4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A22           *((volatile unsigned int*)(0x42C809D8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A23           *((volatile unsigned int*)(0x42C809DCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A24           *((volatile unsigned int*)(0x42C809E0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A25           *((volatile unsigned int*)(0x42C809E4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A26           *((volatile unsigned int*)(0x42C809E8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A27           *((volatile unsigned int*)(0x42C809ECUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A28           *((volatile unsigned int*)(0x42C809F0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A29           *((volatile unsigned int*)(0x42C809F4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A30           *((volatile unsigned int*)(0x42C809F8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A31           *((volatile unsigned int*)(0x42C809FCUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A32           *((volatile unsigned int*)(0x42C80A00UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A33           *((volatile unsigned int*)(0x42C80A04UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A34           *((volatile unsigned int*)(0x42C80A08UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A35           *((volatile unsigned int*)(0x42C80A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A36           *((volatile unsigned int*)(0x42C80A10UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A37           *((volatile unsigned int*)(0x42C80A14UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A38           *((volatile unsigned int*)(0x42C80A18UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A39           *((volatile unsigned int*)(0x42C80A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A40           *((volatile unsigned int*)(0x42C80A20UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A41           *((volatile unsigned int*)(0x42C80A24UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A42           *((volatile unsigned int*)(0x42C80A28UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A43           *((volatile unsigned int*)(0x42C80A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A44           *((volatile unsigned int*)(0x42C80A30UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A45           *((volatile unsigned int*)(0x42C80A34UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A46           *((volatile unsigned int*)(0x42C80A38UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A47           *((volatile unsigned int*)(0x42C80A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC0          *((volatile unsigned int*)(0x42C80A60UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC1          *((volatile unsigned int*)(0x42C80A64UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC2          *((volatile unsigned int*)(0x42C80A68UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC3          *((volatile unsigned int*)(0x42C80A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC4          *((volatile unsigned int*)(0x42C80A70UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC5          *((volatile unsigned int*)(0x42C80A74UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_SA            *((volatile unsigned int*)(0x42C80A78UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_AE            *((volatile unsigned int*)(0x42C80A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A0            *((volatile unsigned int*)(0x42C80A80UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A1            *((volatile unsigned int*)(0x42C80A84UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A2            *((volatile unsigned int*)(0x42C80A88UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A3            *((volatile unsigned int*)(0x42C80A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A4            *((volatile unsigned int*)(0x42C80A90UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A5            *((volatile unsigned int*)(0x42C80A94UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A6            *((volatile unsigned int*)(0x42C80A98UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A7            *((volatile unsigned int*)(0x42C80A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A8            *((volatile unsigned int*)(0x42C80AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A9            *((volatile unsigned int*)(0x42C80AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A10           *((volatile unsigned int*)(0x42C80AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A11           *((volatile unsigned int*)(0x42C80AACUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A12           *((volatile unsigned int*)(0x42C80AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A13           *((volatile unsigned int*)(0x42C80AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A14           *((volatile unsigned int*)(0x42C80AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A15           *((volatile unsigned int*)(0x42C80ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A16           *((volatile unsigned int*)(0x42C80AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A17           *((volatile unsigned int*)(0x42C80AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A18           *((volatile unsigned int*)(0x42C80AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A19           *((volatile unsigned int*)(0x42C80ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A20           *((volatile unsigned int*)(0x42C80AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A21           *((volatile unsigned int*)(0x42C80AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A22           *((volatile unsigned int*)(0x42C80AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A23           *((volatile unsigned int*)(0x42C80ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A24           *((volatile unsigned int*)(0x42C80AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A25           *((volatile unsigned int*)(0x42C80AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A26           *((volatile unsigned int*)(0x42C80AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A27           *((volatile unsigned int*)(0x42C80AECUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A28           *((volatile unsigned int*)(0x42C80AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A29           *((volatile unsigned int*)(0x42C80AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A30           *((volatile unsigned int*)(0x42C80AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A31           *((volatile unsigned int*)(0x42C80AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A32           *((volatile unsigned int*)(0x42C80B00UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A33           *((volatile unsigned int*)(0x42C80B04UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A34           *((volatile unsigned int*)(0x42C80B08UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A35           *((volatile unsigned int*)(0x42C80B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A36           *((volatile unsigned int*)(0x42C80B10UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A37           *((volatile unsigned int*)(0x42C80B14UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A38           *((volatile unsigned int*)(0x42C80B18UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A39           *((volatile unsigned int*)(0x42C80B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A40           *((volatile unsigned int*)(0x42C80B20UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A41           *((volatile unsigned int*)(0x42C80B24UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A42           *((volatile unsigned int*)(0x42C80B28UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A43           *((volatile unsigned int*)(0x42C80B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A44           *((volatile unsigned int*)(0x42C80B30UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A45           *((volatile unsigned int*)(0x42C80B34UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A46           *((volatile unsigned int*)(0x42C80B38UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A47           *((volatile unsigned int*)(0x42C80B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC0          *((volatile unsigned int*)(0x42C80B60UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC1          *((volatile unsigned int*)(0x42C80B64UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC2          *((volatile unsigned int*)(0x42C80B68UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC3          *((volatile unsigned int*)(0x42C80B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC4          *((volatile unsigned int*)(0x42C80B70UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC5          *((volatile unsigned int*)(0x42C80B74UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_SA            *((volatile unsigned int*)(0x42C80B78UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_AE            *((volatile unsigned int*)(0x42C80B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A0            *((volatile unsigned int*)(0x42C80B80UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A1            *((volatile unsigned int*)(0x42C80B84UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A2            *((volatile unsigned int*)(0x42C80B88UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A3            *((volatile unsigned int*)(0x42C80B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A4            *((volatile unsigned int*)(0x42C80B90UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A5            *((volatile unsigned int*)(0x42C80B94UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A6            *((volatile unsigned int*)(0x42C80B98UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A7            *((volatile unsigned int*)(0x42C80B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A8            *((volatile unsigned int*)(0x42C80BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A9            *((volatile unsigned int*)(0x42C80BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A10           *((volatile unsigned int*)(0x42C80BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A11           *((volatile unsigned int*)(0x42C80BACUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A12           *((volatile unsigned int*)(0x42C80BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A13           *((volatile unsigned int*)(0x42C80BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A14           *((volatile unsigned int*)(0x42C80BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A15           *((volatile unsigned int*)(0x42C80BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A16           *((volatile unsigned int*)(0x42C80BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A17           *((volatile unsigned int*)(0x42C80BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A18           *((volatile unsigned int*)(0x42C80BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A19           *((volatile unsigned int*)(0x42C80BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A20           *((volatile unsigned int*)(0x42C80BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A21           *((volatile unsigned int*)(0x42C80BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A22           *((volatile unsigned int*)(0x42C80BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A23           *((volatile unsigned int*)(0x42C80BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A24           *((volatile unsigned int*)(0x42C80BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A25           *((volatile unsigned int*)(0x42C80BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A26           *((volatile unsigned int*)(0x42C80BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A27           *((volatile unsigned int*)(0x42C80BECUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A28           *((volatile unsigned int*)(0x42C80BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A29           *((volatile unsigned int*)(0x42C80BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A30           *((volatile unsigned int*)(0x42C80BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A31           *((volatile unsigned int*)(0x42C80BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A32           *((volatile unsigned int*)(0x42C80C00UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A33           *((volatile unsigned int*)(0x42C80C04UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A34           *((volatile unsigned int*)(0x42C80C08UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A35           *((volatile unsigned int*)(0x42C80C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A36           *((volatile unsigned int*)(0x42C80C10UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A37           *((volatile unsigned int*)(0x42C80C14UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A38           *((volatile unsigned int*)(0x42C80C18UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A39           *((volatile unsigned int*)(0x42C80C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A40           *((volatile unsigned int*)(0x42C80C20UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A41           *((volatile unsigned int*)(0x42C80C24UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A42           *((volatile unsigned int*)(0x42C80C28UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A43           *((volatile unsigned int*)(0x42C80C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A44           *((volatile unsigned int*)(0x42C80C30UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A45           *((volatile unsigned int*)(0x42C80C34UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A46           *((volatile unsigned int*)(0x42C80C38UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A47           *((volatile unsigned int*)(0x42C80C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC0          *((volatile unsigned int*)(0x42C80C60UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC1          *((volatile unsigned int*)(0x42C80C64UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC2          *((volatile unsigned int*)(0x42C80C68UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC3          *((volatile unsigned int*)(0x42C80C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC4          *((volatile unsigned int*)(0x42C80C70UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC5          *((volatile unsigned int*)(0x42C80C74UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_SA            *((volatile unsigned int*)(0x42C80C78UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_AE            *((volatile unsigned int*)(0x42C80C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A0            *((volatile unsigned int*)(0x42C80C80UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A1            *((volatile unsigned int*)(0x42C80C84UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A2            *((volatile unsigned int*)(0x42C80C88UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A3            *((volatile unsigned int*)(0x42C80C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A4            *((volatile unsigned int*)(0x42C80C90UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A5            *((volatile unsigned int*)(0x42C80C94UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A6            *((volatile unsigned int*)(0x42C80C98UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A7            *((volatile unsigned int*)(0x42C80C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A8            *((volatile unsigned int*)(0x42C80CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A9            *((volatile unsigned int*)(0x42C80CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A10           *((volatile unsigned int*)(0x42C80CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A11           *((volatile unsigned int*)(0x42C80CACUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A12           *((volatile unsigned int*)(0x42C80CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A13           *((volatile unsigned int*)(0x42C80CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A14           *((volatile unsigned int*)(0x42C80CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A15           *((volatile unsigned int*)(0x42C80CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A16           *((volatile unsigned int*)(0x42C80CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A17           *((volatile unsigned int*)(0x42C80CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A18           *((volatile unsigned int*)(0x42C80CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A19           *((volatile unsigned int*)(0x42C80CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A20           *((volatile unsigned int*)(0x42C80CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A21           *((volatile unsigned int*)(0x42C80CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A22           *((volatile unsigned int*)(0x42C80CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A23           *((volatile unsigned int*)(0x42C80CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A24           *((volatile unsigned int*)(0x42C80CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A25           *((volatile unsigned int*)(0x42C80CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A26           *((volatile unsigned int*)(0x42C80CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A27           *((volatile unsigned int*)(0x42C80CECUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A28           *((volatile unsigned int*)(0x42C80CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A29           *((volatile unsigned int*)(0x42C80CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A30           *((volatile unsigned int*)(0x42C80CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A31           *((volatile unsigned int*)(0x42C80CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A32           *((volatile unsigned int*)(0x42C80D00UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A33           *((volatile unsigned int*)(0x42C80D04UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A34           *((volatile unsigned int*)(0x42C80D08UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A35           *((volatile unsigned int*)(0x42C80D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A36           *((volatile unsigned int*)(0x42C80D10UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A37           *((volatile unsigned int*)(0x42C80D14UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A38           *((volatile unsigned int*)(0x42C80D18UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A39           *((volatile unsigned int*)(0x42C80D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A40           *((volatile unsigned int*)(0x42C80D20UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A41           *((volatile unsigned int*)(0x42C80D24UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A42           *((volatile unsigned int*)(0x42C80D28UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A43           *((volatile unsigned int*)(0x42C80D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A44           *((volatile unsigned int*)(0x42C80D30UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A45           *((volatile unsigned int*)(0x42C80D34UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A46           *((volatile unsigned int*)(0x42C80D38UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A47           *((volatile unsigned int*)(0x42C80D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC0          *((volatile unsigned int*)(0x42C80D60UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC1          *((volatile unsigned int*)(0x42C80D64UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC2          *((volatile unsigned int*)(0x42C80D68UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC3          *((volatile unsigned int*)(0x42C80D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC4          *((volatile unsigned int*)(0x42C80D70UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC5          *((volatile unsigned int*)(0x42C80D74UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_SA            *((volatile unsigned int*)(0x42C80D78UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_AE            *((volatile unsigned int*)(0x42C80D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A0            *((volatile unsigned int*)(0x42C80D80UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A1            *((volatile unsigned int*)(0x42C80D84UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A2            *((volatile unsigned int*)(0x42C80D88UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A3            *((volatile unsigned int*)(0x42C80D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A4            *((volatile unsigned int*)(0x42C80D90UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A5            *((volatile unsigned int*)(0x42C80D94UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A6            *((volatile unsigned int*)(0x42C80D98UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A7            *((volatile unsigned int*)(0x42C80D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A8            *((volatile unsigned int*)(0x42C80DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A9            *((volatile unsigned int*)(0x42C80DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A10           *((volatile unsigned int*)(0x42C80DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A11           *((volatile unsigned int*)(0x42C80DACUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A12           *((volatile unsigned int*)(0x42C80DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A13           *((volatile unsigned int*)(0x42C80DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A14           *((volatile unsigned int*)(0x42C80DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A15           *((volatile unsigned int*)(0x42C80DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A16           *((volatile unsigned int*)(0x42C80DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A17           *((volatile unsigned int*)(0x42C80DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A18           *((volatile unsigned int*)(0x42C80DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A19           *((volatile unsigned int*)(0x42C80DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A20           *((volatile unsigned int*)(0x42C80DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A21           *((volatile unsigned int*)(0x42C80DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A22           *((volatile unsigned int*)(0x42C80DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A23           *((volatile unsigned int*)(0x42C80DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A24           *((volatile unsigned int*)(0x42C80DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A25           *((volatile unsigned int*)(0x42C80DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A26           *((volatile unsigned int*)(0x42C80DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A27           *((volatile unsigned int*)(0x42C80DECUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A28           *((volatile unsigned int*)(0x42C80DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A29           *((volatile unsigned int*)(0x42C80DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A30           *((volatile unsigned int*)(0x42C80DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A31           *((volatile unsigned int*)(0x42C80DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A32           *((volatile unsigned int*)(0x42C80E00UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A33           *((volatile unsigned int*)(0x42C80E04UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A34           *((volatile unsigned int*)(0x42C80E08UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A35           *((volatile unsigned int*)(0x42C80E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A36           *((volatile unsigned int*)(0x42C80E10UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A37           *((volatile unsigned int*)(0x42C80E14UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A38           *((volatile unsigned int*)(0x42C80E18UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A39           *((volatile unsigned int*)(0x42C80E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A40           *((volatile unsigned int*)(0x42C80E20UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A41           *((volatile unsigned int*)(0x42C80E24UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A42           *((volatile unsigned int*)(0x42C80E28UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A43           *((volatile unsigned int*)(0x42C80E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A44           *((volatile unsigned int*)(0x42C80E30UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A45           *((volatile unsigned int*)(0x42C80E34UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A46           *((volatile unsigned int*)(0x42C80E38UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A47           *((volatile unsigned int*)(0x42C80E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC0          *((volatile unsigned int*)(0x42C80E60UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC1          *((volatile unsigned int*)(0x42C80E64UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC2          *((volatile unsigned int*)(0x42C80E68UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC3          *((volatile unsigned int*)(0x42C80E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC4          *((volatile unsigned int*)(0x42C80E70UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC5          *((volatile unsigned int*)(0x42C80E74UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_SA            *((volatile unsigned int*)(0x42C80E78UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_AE            *((volatile unsigned int*)(0x42C80E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A0            *((volatile unsigned int*)(0x42C80E80UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A1            *((volatile unsigned int*)(0x42C80E84UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A2            *((volatile unsigned int*)(0x42C80E88UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A3            *((volatile unsigned int*)(0x42C80E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A4            *((volatile unsigned int*)(0x42C80E90UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A5            *((volatile unsigned int*)(0x42C80E94UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A6            *((volatile unsigned int*)(0x42C80E98UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A7            *((volatile unsigned int*)(0x42C80E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A8            *((volatile unsigned int*)(0x42C80EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A9            *((volatile unsigned int*)(0x42C80EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A10           *((volatile unsigned int*)(0x42C80EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A11           *((volatile unsigned int*)(0x42C80EACUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A12           *((volatile unsigned int*)(0x42C80EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A13           *((volatile unsigned int*)(0x42C80EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A14           *((volatile unsigned int*)(0x42C80EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A15           *((volatile unsigned int*)(0x42C80EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A16           *((volatile unsigned int*)(0x42C80EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A17           *((volatile unsigned int*)(0x42C80EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A18           *((volatile unsigned int*)(0x42C80EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A19           *((volatile unsigned int*)(0x42C80ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A20           *((volatile unsigned int*)(0x42C80ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A21           *((volatile unsigned int*)(0x42C80ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A22           *((volatile unsigned int*)(0x42C80ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A23           *((volatile unsigned int*)(0x42C80EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A24           *((volatile unsigned int*)(0x42C80EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A25           *((volatile unsigned int*)(0x42C80EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A26           *((volatile unsigned int*)(0x42C80EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A27           *((volatile unsigned int*)(0x42C80EECUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A28           *((volatile unsigned int*)(0x42C80EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A29           *((volatile unsigned int*)(0x42C80EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A30           *((volatile unsigned int*)(0x42C80EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A31           *((volatile unsigned int*)(0x42C80EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A32           *((volatile unsigned int*)(0x42C80F00UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A33           *((volatile unsigned int*)(0x42C80F04UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A34           *((volatile unsigned int*)(0x42C80F08UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A35           *((volatile unsigned int*)(0x42C80F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A36           *((volatile unsigned int*)(0x42C80F10UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A37           *((volatile unsigned int*)(0x42C80F14UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A38           *((volatile unsigned int*)(0x42C80F18UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A39           *((volatile unsigned int*)(0x42C80F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A40           *((volatile unsigned int*)(0x42C80F20UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A41           *((volatile unsigned int*)(0x42C80F24UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A42           *((volatile unsigned int*)(0x42C80F28UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A43           *((volatile unsigned int*)(0x42C80F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A44           *((volatile unsigned int*)(0x42C80F30UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A45           *((volatile unsigned int*)(0x42C80F34UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A46           *((volatile unsigned int*)(0x42C80F38UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A47           *((volatile unsigned int*)(0x42C80F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC0          *((volatile unsigned int*)(0x42C80F60UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC1          *((volatile unsigned int*)(0x42C80F64UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC2          *((volatile unsigned int*)(0x42C80F68UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC3          *((volatile unsigned int*)(0x42C80F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC4          *((volatile unsigned int*)(0x42C80F70UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC5          *((volatile unsigned int*)(0x42C80F74UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_SA            *((volatile unsigned int*)(0x42C80F78UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_AE            *((volatile unsigned int*)(0x42C80F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A0            *((volatile unsigned int*)(0x42C80F80UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A1            *((volatile unsigned int*)(0x42C80F84UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A2            *((volatile unsigned int*)(0x42C80F88UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A3            *((volatile unsigned int*)(0x42C80F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A4            *((volatile unsigned int*)(0x42C80F90UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A5            *((volatile unsigned int*)(0x42C80F94UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A6            *((volatile unsigned int*)(0x42C80F98UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A7            *((volatile unsigned int*)(0x42C80F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A8            *((volatile unsigned int*)(0x42C80FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A9            *((volatile unsigned int*)(0x42C80FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A10           *((volatile unsigned int*)(0x42C80FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A11           *((volatile unsigned int*)(0x42C80FACUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A12           *((volatile unsigned int*)(0x42C80FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A13           *((volatile unsigned int*)(0x42C80FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A14           *((volatile unsigned int*)(0x42C80FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A15           *((volatile unsigned int*)(0x42C80FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A16           *((volatile unsigned int*)(0x42C80FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A17           *((volatile unsigned int*)(0x42C80FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A18           *((volatile unsigned int*)(0x42C80FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A19           *((volatile unsigned int*)(0x42C80FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A20           *((volatile unsigned int*)(0x42C80FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A21           *((volatile unsigned int*)(0x42C80FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A22           *((volatile unsigned int*)(0x42C80FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A23           *((volatile unsigned int*)(0x42C80FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A24           *((volatile unsigned int*)(0x42C80FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A25           *((volatile unsigned int*)(0x42C80FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A26           *((volatile unsigned int*)(0x42C80FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A27           *((volatile unsigned int*)(0x42C80FECUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A28           *((volatile unsigned int*)(0x42C80FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A29           *((volatile unsigned int*)(0x42C80FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A30           *((volatile unsigned int*)(0x42C80FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A31           *((volatile unsigned int*)(0x42C80FFCUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A32           *((volatile unsigned int*)(0x42C81000UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A33           *((volatile unsigned int*)(0x42C81004UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A34           *((volatile unsigned int*)(0x42C81008UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A35           *((volatile unsigned int*)(0x42C8100CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A36           *((volatile unsigned int*)(0x42C81010UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A37           *((volatile unsigned int*)(0x42C81014UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A38           *((volatile unsigned int*)(0x42C81018UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A39           *((volatile unsigned int*)(0x42C8101CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A40           *((volatile unsigned int*)(0x42C81020UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A41           *((volatile unsigned int*)(0x42C81024UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A42           *((volatile unsigned int*)(0x42C81028UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A43           *((volatile unsigned int*)(0x42C8102CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A44           *((volatile unsigned int*)(0x42C81030UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A45           *((volatile unsigned int*)(0x42C81034UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A46           *((volatile unsigned int*)(0x42C81038UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A47           *((volatile unsigned int*)(0x42C8103CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC0          *((volatile unsigned int*)(0x42C81060UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC1          *((volatile unsigned int*)(0x42C81064UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC2          *((volatile unsigned int*)(0x42C81068UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC3          *((volatile unsigned int*)(0x42C8106CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC4          *((volatile unsigned int*)(0x42C81070UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC5          *((volatile unsigned int*)(0x42C81074UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_SA            *((volatile unsigned int*)(0x42C81078UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_AE            *((volatile unsigned int*)(0x42C8107CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A0            *((volatile unsigned int*)(0x42C81080UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A1            *((volatile unsigned int*)(0x42C81084UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A2            *((volatile unsigned int*)(0x42C81088UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A3            *((volatile unsigned int*)(0x42C8108CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A4            *((volatile unsigned int*)(0x42C81090UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A5            *((volatile unsigned int*)(0x42C81094UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A6            *((volatile unsigned int*)(0x42C81098UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A7            *((volatile unsigned int*)(0x42C8109CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A8            *((volatile unsigned int*)(0x42C810A0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A9            *((volatile unsigned int*)(0x42C810A4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A10           *((volatile unsigned int*)(0x42C810A8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A11           *((volatile unsigned int*)(0x42C810ACUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A12           *((volatile unsigned int*)(0x42C810B0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A13           *((volatile unsigned int*)(0x42C810B4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A14           *((volatile unsigned int*)(0x42C810B8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A15           *((volatile unsigned int*)(0x42C810BCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A16           *((volatile unsigned int*)(0x42C810C0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A17           *((volatile unsigned int*)(0x42C810C4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A18           *((volatile unsigned int*)(0x42C810C8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A19           *((volatile unsigned int*)(0x42C810CCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A20           *((volatile unsigned int*)(0x42C810D0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A21           *((volatile unsigned int*)(0x42C810D4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A22           *((volatile unsigned int*)(0x42C810D8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A23           *((volatile unsigned int*)(0x42C810DCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A24           *((volatile unsigned int*)(0x42C810E0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A25           *((volatile unsigned int*)(0x42C810E4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A26           *((volatile unsigned int*)(0x42C810E8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A27           *((volatile unsigned int*)(0x42C810ECUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A28           *((volatile unsigned int*)(0x42C810F0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A29           *((volatile unsigned int*)(0x42C810F4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A30           *((volatile unsigned int*)(0x42C810F8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A31           *((volatile unsigned int*)(0x42C810FCUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A32           *((volatile unsigned int*)(0x42C81100UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A33           *((volatile unsigned int*)(0x42C81104UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A34           *((volatile unsigned int*)(0x42C81108UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A35           *((volatile unsigned int*)(0x42C8110CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A36           *((volatile unsigned int*)(0x42C81110UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A37           *((volatile unsigned int*)(0x42C81114UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A38           *((volatile unsigned int*)(0x42C81118UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A39           *((volatile unsigned int*)(0x42C8111CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A40           *((volatile unsigned int*)(0x42C81120UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A41           *((volatile unsigned int*)(0x42C81124UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A42           *((volatile unsigned int*)(0x42C81128UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A43           *((volatile unsigned int*)(0x42C8112CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A44           *((volatile unsigned int*)(0x42C81130UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A45           *((volatile unsigned int*)(0x42C81134UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A46           *((volatile unsigned int*)(0x42C81138UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A47           *((volatile unsigned int*)(0x42C8113CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC0          *((volatile unsigned int*)(0x42C81160UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC1          *((volatile unsigned int*)(0x42C81164UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC2          *((volatile unsigned int*)(0x42C81168UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC3          *((volatile unsigned int*)(0x42C8116CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC4          *((volatile unsigned int*)(0x42C81170UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC5          *((volatile unsigned int*)(0x42C81174UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_SA            *((volatile unsigned int*)(0x42C81178UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_AE            *((volatile unsigned int*)(0x42C8117CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A0            *((volatile unsigned int*)(0x42C81180UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A1            *((volatile unsigned int*)(0x42C81184UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A2            *((volatile unsigned int*)(0x42C81188UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A3            *((volatile unsigned int*)(0x42C8118CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A4            *((volatile unsigned int*)(0x42C81190UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A5            *((volatile unsigned int*)(0x42C81194UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A6            *((volatile unsigned int*)(0x42C81198UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A7            *((volatile unsigned int*)(0x42C8119CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A8            *((volatile unsigned int*)(0x42C811A0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A9            *((volatile unsigned int*)(0x42C811A4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A10           *((volatile unsigned int*)(0x42C811A8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A11           *((volatile unsigned int*)(0x42C811ACUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A12           *((volatile unsigned int*)(0x42C811B0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A13           *((volatile unsigned int*)(0x42C811B4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A14           *((volatile unsigned int*)(0x42C811B8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A15           *((volatile unsigned int*)(0x42C811BCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A16           *((volatile unsigned int*)(0x42C811C0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A17           *((volatile unsigned int*)(0x42C811C4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A18           *((volatile unsigned int*)(0x42C811C8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A19           *((volatile unsigned int*)(0x42C811CCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A20           *((volatile unsigned int*)(0x42C811D0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A21           *((volatile unsigned int*)(0x42C811D4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A22           *((volatile unsigned int*)(0x42C811D8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A23           *((volatile unsigned int*)(0x42C811DCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A24           *((volatile unsigned int*)(0x42C811E0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A25           *((volatile unsigned int*)(0x42C811E4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A26           *((volatile unsigned int*)(0x42C811E8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A27           *((volatile unsigned int*)(0x42C811ECUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A28           *((volatile unsigned int*)(0x42C811F0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A29           *((volatile unsigned int*)(0x42C811F4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A30           *((volatile unsigned int*)(0x42C811F8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A31           *((volatile unsigned int*)(0x42C811FCUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A32          *((volatile unsigned int*)(0x42C81200UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A33          *((volatile unsigned int*)(0x42C81204UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A34          *((volatile unsigned int*)(0x42C81208UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A35          *((volatile unsigned int*)(0x42C8120CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A36          *((volatile unsigned int*)(0x42C81210UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A37          *((volatile unsigned int*)(0x42C81214UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A38          *((volatile unsigned int*)(0x42C81218UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A39          *((volatile unsigned int*)(0x42C8121CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A40          *((volatile unsigned int*)(0x42C81220UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A41          *((volatile unsigned int*)(0x42C81224UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A42          *((volatile unsigned int*)(0x42C81228UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A43          *((volatile unsigned int*)(0x42C8122CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A44          *((volatile unsigned int*)(0x42C81230UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A45          *((volatile unsigned int*)(0x42C81234UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A46          *((volatile unsigned int*)(0x42C81238UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A47          *((volatile unsigned int*)(0x42C8123CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC0         *((volatile unsigned int*)(0x42C81260UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC1         *((volatile unsigned int*)(0x42C81264UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC2         *((volatile unsigned int*)(0x42C81268UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC3         *((volatile unsigned int*)(0x42C8126CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC4         *((volatile unsigned int*)(0x42C81270UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC5         *((volatile unsigned int*)(0x42C81274UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_SA           *((volatile unsigned int*)(0x42C81278UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_AE           *((volatile unsigned int*)(0x42C8127CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A0           *((volatile unsigned int*)(0x42C81280UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A1           *((volatile unsigned int*)(0x42C81284UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A2           *((volatile unsigned int*)(0x42C81288UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A3           *((volatile unsigned int*)(0x42C8128CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A4           *((volatile unsigned int*)(0x42C81290UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A5           *((volatile unsigned int*)(0x42C81294UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A6           *((volatile unsigned int*)(0x42C81298UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A7           *((volatile unsigned int*)(0x42C8129CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A8           *((volatile unsigned int*)(0x42C812A0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A9           *((volatile unsigned int*)(0x42C812A4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A10          *((volatile unsigned int*)(0x42C812A8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A11          *((volatile unsigned int*)(0x42C812ACUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A12          *((volatile unsigned int*)(0x42C812B0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A13          *((volatile unsigned int*)(0x42C812B4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A14          *((volatile unsigned int*)(0x42C812B8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A15          *((volatile unsigned int*)(0x42C812BCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A16          *((volatile unsigned int*)(0x42C812C0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A17          *((volatile unsigned int*)(0x42C812C4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A18          *((volatile unsigned int*)(0x42C812C8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A19          *((volatile unsigned int*)(0x42C812CCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A20          *((volatile unsigned int*)(0x42C812D0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A21          *((volatile unsigned int*)(0x42C812D4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A22          *((volatile unsigned int*)(0x42C812D8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A23          *((volatile unsigned int*)(0x42C812DCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A24          *((volatile unsigned int*)(0x42C812E0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A25          *((volatile unsigned int*)(0x42C812E4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A26          *((volatile unsigned int*)(0x42C812E8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A27          *((volatile unsigned int*)(0x42C812ECUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A28          *((volatile unsigned int*)(0x42C812F0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A29          *((volatile unsigned int*)(0x42C812F4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A30          *((volatile unsigned int*)(0x42C812F8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A31          *((volatile unsigned int*)(0x42C812FCUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A32          *((volatile unsigned int*)(0x42C81300UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A33          *((volatile unsigned int*)(0x42C81304UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A34          *((volatile unsigned int*)(0x42C81308UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A35          *((volatile unsigned int*)(0x42C8130CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A36          *((volatile unsigned int*)(0x42C81310UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A37          *((volatile unsigned int*)(0x42C81314UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A38          *((volatile unsigned int*)(0x42C81318UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A39          *((volatile unsigned int*)(0x42C8131CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A40          *((volatile unsigned int*)(0x42C81320UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A41          *((volatile unsigned int*)(0x42C81324UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A42          *((volatile unsigned int*)(0x42C81328UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A43          *((volatile unsigned int*)(0x42C8132CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A44          *((volatile unsigned int*)(0x42C81330UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A45          *((volatile unsigned int*)(0x42C81334UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A46          *((volatile unsigned int*)(0x42C81338UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A47          *((volatile unsigned int*)(0x42C8133CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC0         *((volatile unsigned int*)(0x42C81360UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC1         *((volatile unsigned int*)(0x42C81364UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC2         *((volatile unsigned int*)(0x42C81368UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC3         *((volatile unsigned int*)(0x42C8136CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC4         *((volatile unsigned int*)(0x42C81370UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC5         *((volatile unsigned int*)(0x42C81374UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_SA           *((volatile unsigned int*)(0x42C81378UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_AE           *((volatile unsigned int*)(0x42C8137CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A0           *((volatile unsigned int*)(0x42C81380UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A1           *((volatile unsigned int*)(0x42C81384UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A2           *((volatile unsigned int*)(0x42C81388UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A3           *((volatile unsigned int*)(0x42C8138CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A4           *((volatile unsigned int*)(0x42C81390UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A5           *((volatile unsigned int*)(0x42C81394UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A6           *((volatile unsigned int*)(0x42C81398UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A7           *((volatile unsigned int*)(0x42C8139CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A8           *((volatile unsigned int*)(0x42C813A0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A9           *((volatile unsigned int*)(0x42C813A4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A10          *((volatile unsigned int*)(0x42C813A8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A11          *((volatile unsigned int*)(0x42C813ACUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A12          *((volatile unsigned int*)(0x42C813B0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A13          *((volatile unsigned int*)(0x42C813B4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A14          *((volatile unsigned int*)(0x42C813B8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A15          *((volatile unsigned int*)(0x42C813BCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A16          *((volatile unsigned int*)(0x42C813C0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A17          *((volatile unsigned int*)(0x42C813C4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A18          *((volatile unsigned int*)(0x42C813C8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A19          *((volatile unsigned int*)(0x42C813CCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A20          *((volatile unsigned int*)(0x42C813D0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A21          *((volatile unsigned int*)(0x42C813D4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A22          *((volatile unsigned int*)(0x42C813D8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A23          *((volatile unsigned int*)(0x42C813DCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A24          *((volatile unsigned int*)(0x42C813E0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A25          *((volatile unsigned int*)(0x42C813E4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A26          *((volatile unsigned int*)(0x42C813E8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A27          *((volatile unsigned int*)(0x42C813ECUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A28          *((volatile unsigned int*)(0x42C813F0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A29          *((volatile unsigned int*)(0x42C813F4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A30          *((volatile unsigned int*)(0x42C813F8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A31          *((volatile unsigned int*)(0x42C813FCUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A32          *((volatile unsigned int*)(0x42C81400UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A33          *((volatile unsigned int*)(0x42C81404UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A34          *((volatile unsigned int*)(0x42C81408UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A35          *((volatile unsigned int*)(0x42C8140CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A36          *((volatile unsigned int*)(0x42C81410UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A37          *((volatile unsigned int*)(0x42C81414UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A38          *((volatile unsigned int*)(0x42C81418UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A39          *((volatile unsigned int*)(0x42C8141CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A40          *((volatile unsigned int*)(0x42C81420UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A41          *((volatile unsigned int*)(0x42C81424UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A42          *((volatile unsigned int*)(0x42C81428UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A43          *((volatile unsigned int*)(0x42C8142CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A44          *((volatile unsigned int*)(0x42C81430UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A45          *((volatile unsigned int*)(0x42C81434UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A46          *((volatile unsigned int*)(0x42C81438UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A47          *((volatile unsigned int*)(0x42C8143CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC0         *((volatile unsigned int*)(0x42C81460UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC1         *((volatile unsigned int*)(0x42C81464UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC2         *((volatile unsigned int*)(0x42C81468UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC3         *((volatile unsigned int*)(0x42C8146CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC4         *((volatile unsigned int*)(0x42C81470UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC5         *((volatile unsigned int*)(0x42C81474UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_SA           *((volatile unsigned int*)(0x42C81478UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_AE           *((volatile unsigned int*)(0x42C8147CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A0           *((volatile unsigned int*)(0x42C81480UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A1           *((volatile unsigned int*)(0x42C81484UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A2           *((volatile unsigned int*)(0x42C81488UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A3           *((volatile unsigned int*)(0x42C8148CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A4           *((volatile unsigned int*)(0x42C81490UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A5           *((volatile unsigned int*)(0x42C81494UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A6           *((volatile unsigned int*)(0x42C81498UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A7           *((volatile unsigned int*)(0x42C8149CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A8           *((volatile unsigned int*)(0x42C814A0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A9           *((volatile unsigned int*)(0x42C814A4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A10          *((volatile unsigned int*)(0x42C814A8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A11          *((volatile unsigned int*)(0x42C814ACUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A12          *((volatile unsigned int*)(0x42C814B0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A13          *((volatile unsigned int*)(0x42C814B4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A14          *((volatile unsigned int*)(0x42C814B8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A15          *((volatile unsigned int*)(0x42C814BCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A16          *((volatile unsigned int*)(0x42C814C0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A17          *((volatile unsigned int*)(0x42C814C4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A18          *((volatile unsigned int*)(0x42C814C8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A19          *((volatile unsigned int*)(0x42C814CCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A20          *((volatile unsigned int*)(0x42C814D0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A21          *((volatile unsigned int*)(0x42C814D4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A22          *((volatile unsigned int*)(0x42C814D8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A23          *((volatile unsigned int*)(0x42C814DCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A24          *((volatile unsigned int*)(0x42C814E0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A25          *((volatile unsigned int*)(0x42C814E4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A26          *((volatile unsigned int*)(0x42C814E8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A27          *((volatile unsigned int*)(0x42C814ECUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A28          *((volatile unsigned int*)(0x42C814F0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A29          *((volatile unsigned int*)(0x42C814F4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A30          *((volatile unsigned int*)(0x42C814F8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A31          *((volatile unsigned int*)(0x42C814FCUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A32          *((volatile unsigned int*)(0x42C81500UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A33          *((volatile unsigned int*)(0x42C81504UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A34          *((volatile unsigned int*)(0x42C81508UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A35          *((volatile unsigned int*)(0x42C8150CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A36          *((volatile unsigned int*)(0x42C81510UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A37          *((volatile unsigned int*)(0x42C81514UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A38          *((volatile unsigned int*)(0x42C81518UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A39          *((volatile unsigned int*)(0x42C8151CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A40          *((volatile unsigned int*)(0x42C81520UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A41          *((volatile unsigned int*)(0x42C81524UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A42          *((volatile unsigned int*)(0x42C81528UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A43          *((volatile unsigned int*)(0x42C8152CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A44          *((volatile unsigned int*)(0x42C81530UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A45          *((volatile unsigned int*)(0x42C81534UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A46          *((volatile unsigned int*)(0x42C81538UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A47          *((volatile unsigned int*)(0x42C8153CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC0         *((volatile unsigned int*)(0x42C81560UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC1         *((volatile unsigned int*)(0x42C81564UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC2         *((volatile unsigned int*)(0x42C81568UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC3         *((volatile unsigned int*)(0x42C8156CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC4         *((volatile unsigned int*)(0x42C81570UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC5         *((volatile unsigned int*)(0x42C81574UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_SA           *((volatile unsigned int*)(0x42C81578UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_AE           *((volatile unsigned int*)(0x42C8157CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A0           *((volatile unsigned int*)(0x42C81580UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A1           *((volatile unsigned int*)(0x42C81584UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A2           *((volatile unsigned int*)(0x42C81588UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A3           *((volatile unsigned int*)(0x42C8158CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A4           *((volatile unsigned int*)(0x42C81590UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A5           *((volatile unsigned int*)(0x42C81594UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A6           *((volatile unsigned int*)(0x42C81598UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A7           *((volatile unsigned int*)(0x42C8159CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A8           *((volatile unsigned int*)(0x42C815A0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A9           *((volatile unsigned int*)(0x42C815A4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A10          *((volatile unsigned int*)(0x42C815A8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A11          *((volatile unsigned int*)(0x42C815ACUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A12          *((volatile unsigned int*)(0x42C815B0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A13          *((volatile unsigned int*)(0x42C815B4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A14          *((volatile unsigned int*)(0x42C815B8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A15          *((volatile unsigned int*)(0x42C815BCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A16          *((volatile unsigned int*)(0x42C815C0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A17          *((volatile unsigned int*)(0x42C815C4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A18          *((volatile unsigned int*)(0x42C815C8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A19          *((volatile unsigned int*)(0x42C815CCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A20          *((volatile unsigned int*)(0x42C815D0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A21          *((volatile unsigned int*)(0x42C815D4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A22          *((volatile unsigned int*)(0x42C815D8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A23          *((volatile unsigned int*)(0x42C815DCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A24          *((volatile unsigned int*)(0x42C815E0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A25          *((volatile unsigned int*)(0x42C815E4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A26          *((volatile unsigned int*)(0x42C815E8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A27          *((volatile unsigned int*)(0x42C815ECUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A28          *((volatile unsigned int*)(0x42C815F0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A29          *((volatile unsigned int*)(0x42C815F4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A30          *((volatile unsigned int*)(0x42C815F8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A31          *((volatile unsigned int*)(0x42C815FCUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A32          *((volatile unsigned int*)(0x42C81600UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A33          *((volatile unsigned int*)(0x42C81604UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A34          *((volatile unsigned int*)(0x42C81608UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A35          *((volatile unsigned int*)(0x42C8160CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A36          *((volatile unsigned int*)(0x42C81610UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A37          *((volatile unsigned int*)(0x42C81614UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A38          *((volatile unsigned int*)(0x42C81618UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A39          *((volatile unsigned int*)(0x42C8161CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A40          *((volatile unsigned int*)(0x42C81620UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A41          *((volatile unsigned int*)(0x42C81624UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A42          *((volatile unsigned int*)(0x42C81628UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A43          *((volatile unsigned int*)(0x42C8162CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A44          *((volatile unsigned int*)(0x42C81630UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A45          *((volatile unsigned int*)(0x42C81634UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A46          *((volatile unsigned int*)(0x42C81638UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A47          *((volatile unsigned int*)(0x42C8163CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC0         *((volatile unsigned int*)(0x42C81660UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC1         *((volatile unsigned int*)(0x42C81664UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC2         *((volatile unsigned int*)(0x42C81668UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC3         *((volatile unsigned int*)(0x42C8166CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC4         *((volatile unsigned int*)(0x42C81670UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC5         *((volatile unsigned int*)(0x42C81674UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_SA           *((volatile unsigned int*)(0x42C81678UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_AE           *((volatile unsigned int*)(0x42C8167CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A0           *((volatile unsigned int*)(0x42C81680UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A1           *((volatile unsigned int*)(0x42C81684UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A2           *((volatile unsigned int*)(0x42C81688UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A3           *((volatile unsigned int*)(0x42C8168CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A4           *((volatile unsigned int*)(0x42C81690UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A5           *((volatile unsigned int*)(0x42C81694UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A6           *((volatile unsigned int*)(0x42C81698UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A7           *((volatile unsigned int*)(0x42C8169CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A8           *((volatile unsigned int*)(0x42C816A0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A9           *((volatile unsigned int*)(0x42C816A4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A10          *((volatile unsigned int*)(0x42C816A8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A11          *((volatile unsigned int*)(0x42C816ACUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A12          *((volatile unsigned int*)(0x42C816B0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A13          *((volatile unsigned int*)(0x42C816B4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A14          *((volatile unsigned int*)(0x42C816B8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A15          *((volatile unsigned int*)(0x42C816BCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A16          *((volatile unsigned int*)(0x42C816C0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A17          *((volatile unsigned int*)(0x42C816C4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A18          *((volatile unsigned int*)(0x42C816C8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A19          *((volatile unsigned int*)(0x42C816CCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A20          *((volatile unsigned int*)(0x42C816D0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A21          *((volatile unsigned int*)(0x42C816D4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A22          *((volatile unsigned int*)(0x42C816D8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A23          *((volatile unsigned int*)(0x42C816DCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A24          *((volatile unsigned int*)(0x42C816E0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A25          *((volatile unsigned int*)(0x42C816E4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A26          *((volatile unsigned int*)(0x42C816E8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A27          *((volatile unsigned int*)(0x42C816ECUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A28          *((volatile unsigned int*)(0x42C816F0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A29          *((volatile unsigned int*)(0x42C816F4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A30          *((volatile unsigned int*)(0x42C816F8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A31          *((volatile unsigned int*)(0x42C816FCUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A32          *((volatile unsigned int*)(0x42C81700UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A33          *((volatile unsigned int*)(0x42C81704UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A34          *((volatile unsigned int*)(0x42C81708UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A35          *((volatile unsigned int*)(0x42C8170CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A36          *((volatile unsigned int*)(0x42C81710UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A37          *((volatile unsigned int*)(0x42C81714UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A38          *((volatile unsigned int*)(0x42C81718UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A39          *((volatile unsigned int*)(0x42C8171CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A40          *((volatile unsigned int*)(0x42C81720UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A41          *((volatile unsigned int*)(0x42C81724UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A42          *((volatile unsigned int*)(0x42C81728UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A43          *((volatile unsigned int*)(0x42C8172CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A44          *((volatile unsigned int*)(0x42C81730UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A45          *((volatile unsigned int*)(0x42C81734UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A46          *((volatile unsigned int*)(0x42C81738UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A47          *((volatile unsigned int*)(0x42C8173CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC0         *((volatile unsigned int*)(0x42C81760UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC1         *((volatile unsigned int*)(0x42C81764UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC2         *((volatile unsigned int*)(0x42C81768UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC3         *((volatile unsigned int*)(0x42C8176CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC4         *((volatile unsigned int*)(0x42C81770UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC5         *((volatile unsigned int*)(0x42C81774UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_SA           *((volatile unsigned int*)(0x42C81778UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_AE           *((volatile unsigned int*)(0x42C8177CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A0           *((volatile unsigned int*)(0x42C81780UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A1           *((volatile unsigned int*)(0x42C81784UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A2           *((volatile unsigned int*)(0x42C81788UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A3           *((volatile unsigned int*)(0x42C8178CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A4           *((volatile unsigned int*)(0x42C81790UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A5           *((volatile unsigned int*)(0x42C81794UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A6           *((volatile unsigned int*)(0x42C81798UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A7           *((volatile unsigned int*)(0x42C8179CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A8           *((volatile unsigned int*)(0x42C817A0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A9           *((volatile unsigned int*)(0x42C817A4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A10          *((volatile unsigned int*)(0x42C817A8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A11          *((volatile unsigned int*)(0x42C817ACUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A12          *((volatile unsigned int*)(0x42C817B0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A13          *((volatile unsigned int*)(0x42C817B4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A14          *((volatile unsigned int*)(0x42C817B8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A15          *((volatile unsigned int*)(0x42C817BCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A16          *((volatile unsigned int*)(0x42C817C0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A17          *((volatile unsigned int*)(0x42C817C4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A18          *((volatile unsigned int*)(0x42C817C8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A19          *((volatile unsigned int*)(0x42C817CCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A20          *((volatile unsigned int*)(0x42C817D0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A21          *((volatile unsigned int*)(0x42C817D4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A22          *((volatile unsigned int*)(0x42C817D8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A23          *((volatile unsigned int*)(0x42C817DCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A24          *((volatile unsigned int*)(0x42C817E0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A25          *((volatile unsigned int*)(0x42C817E4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A26          *((volatile unsigned int*)(0x42C817E8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A27          *((volatile unsigned int*)(0x42C817ECUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A28          *((volatile unsigned int*)(0x42C817F0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A29          *((volatile unsigned int*)(0x42C817F4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A30          *((volatile unsigned int*)(0x42C817F8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A31          *((volatile unsigned int*)(0x42C817FCUL))
+#define bFM3_ETHERNET_MAC0_RGSR_LM             *((volatile unsigned int*)(0x42C81B00UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP0           *((volatile unsigned int*)(0x42C81B04UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP1           *((volatile unsigned int*)(0x42C81B08UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LS             *((volatile unsigned int*)(0x42C81B0CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSE            *((volatile unsigned int*)(0x42C8E000UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TFCU           *((volatile unsigned int*)(0x42C8E004UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSI            *((volatile unsigned int*)(0x42C8E008UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSU            *((volatile unsigned int*)(0x42C8E00CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TITE           *((volatile unsigned int*)(0x42C8E010UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TARU           *((volatile unsigned int*)(0x42C8E014UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSEA           *((volatile unsigned int*)(0x42C8E020UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSDB           *((volatile unsigned int*)(0x42C8E024UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSV2E          *((volatile unsigned int*)(0x42C8E028UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSP          *((volatile unsigned int*)(0x42C8E02CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E         *((volatile unsigned int*)(0x42C8E030UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E         *((volatile unsigned int*)(0x42C8E034UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSEM         *((volatile unsigned int*)(0x42C8E038UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSMRM          *((volatile unsigned int*)(0x42C8E03CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS0          *((volatile unsigned int*)(0x42C8E040UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS1          *((volatile unsigned int*)(0x42C8E044UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSENMF         *((volatile unsigned int*)(0x42C8E048UL))
+#define bFM3_ETHERNET_MAC0_TSCR_ATSFC          *((volatile unsigned int*)(0x42C8E060UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC0         *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC1         *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC2         *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC3         *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC4         *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC5         *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC6         *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC7         *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS0           *((volatile unsigned int*)(0x42C8E100UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS1           *((volatile unsigned int*)(0x42C8E104UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS2           *((volatile unsigned int*)(0x42C8E108UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS3           *((volatile unsigned int*)(0x42C8E10CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS4           *((volatile unsigned int*)(0x42C8E110UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS5           *((volatile unsigned int*)(0x42C8E114UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS6           *((volatile unsigned int*)(0x42C8E118UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS7           *((volatile unsigned int*)(0x42C8E11CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS8           *((volatile unsigned int*)(0x42C8E120UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS9           *((volatile unsigned int*)(0x42C8E124UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS10          *((volatile unsigned int*)(0x42C8E128UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS11          *((volatile unsigned int*)(0x42C8E12CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS12          *((volatile unsigned int*)(0x42C8E130UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS13          *((volatile unsigned int*)(0x42C8E134UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS14          *((volatile unsigned int*)(0x42C8E138UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS15          *((volatile unsigned int*)(0x42C8E13CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS16          *((volatile unsigned int*)(0x42C8E140UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS17          *((volatile unsigned int*)(0x42C8E144UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS18          *((volatile unsigned int*)(0x42C8E148UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS19          *((volatile unsigned int*)(0x42C8E14CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS20          *((volatile unsigned int*)(0x42C8E150UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS21          *((volatile unsigned int*)(0x42C8E154UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS22          *((volatile unsigned int*)(0x42C8E158UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS23          *((volatile unsigned int*)(0x42C8E15CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS24          *((volatile unsigned int*)(0x42C8E160UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS25          *((volatile unsigned int*)(0x42C8E164UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS26          *((volatile unsigned int*)(0x42C8E168UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS27          *((volatile unsigned int*)(0x42C8E16CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS28          *((volatile unsigned int*)(0x42C8E170UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS29          *((volatile unsigned int*)(0x42C8E174UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS30          *((volatile unsigned int*)(0x42C8E178UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS31          *((volatile unsigned int*)(0x42C8E17CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS0          *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS1          *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS2          *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS3          *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS4          *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS5          *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS6          *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS7          *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS8          *((volatile unsigned int*)(0x42C8E0A0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS9          *((volatile unsigned int*)(0x42C8E0A4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS10         *((volatile unsigned int*)(0x42C8E0A8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS11         *((volatile unsigned int*)(0x42C8E0ACUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS12         *((volatile unsigned int*)(0x42C8E0B0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS13         *((volatile unsigned int*)(0x42C8E0B4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS14         *((volatile unsigned int*)(0x42C8E0B8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS15         *((volatile unsigned int*)(0x42C8E0BCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS16         *((volatile unsigned int*)(0x42C8E0C0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS17         *((volatile unsigned int*)(0x42C8E0C4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS18         *((volatile unsigned int*)(0x42C8E0C8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS19         *((volatile unsigned int*)(0x42C8E0CCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS20         *((volatile unsigned int*)(0x42C8E0D0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS21         *((volatile unsigned int*)(0x42C8E0D4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS22         *((volatile unsigned int*)(0x42C8E0D8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS23         *((volatile unsigned int*)(0x42C8E0DCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS24         *((volatile unsigned int*)(0x42C8E0E0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS25         *((volatile unsigned int*)(0x42C8E0E4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS26         *((volatile unsigned int*)(0x42C8E0E8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS27         *((volatile unsigned int*)(0x42C8E0ECUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS28         *((volatile unsigned int*)(0x42C8E0F0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS29         *((volatile unsigned int*)(0x42C8E0F4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS30         *((volatile unsigned int*)(0x42C8E0F8UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS0          *((volatile unsigned int*)(0x42C8E200UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS1          *((volatile unsigned int*)(0x42C8E204UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS2          *((volatile unsigned int*)(0x42C8E208UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS3          *((volatile unsigned int*)(0x42C8E20CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS4          *((volatile unsigned int*)(0x42C8E210UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS5          *((volatile unsigned int*)(0x42C8E214UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS6          *((volatile unsigned int*)(0x42C8E218UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS7          *((volatile unsigned int*)(0x42C8E21CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS8          *((volatile unsigned int*)(0x42C8E220UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS9          *((volatile unsigned int*)(0x42C8E224UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS10         *((volatile unsigned int*)(0x42C8E228UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS11         *((volatile unsigned int*)(0x42C8E22CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS12         *((volatile unsigned int*)(0x42C8E230UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS13         *((volatile unsigned int*)(0x42C8E234UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS14         *((volatile unsigned int*)(0x42C8E238UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS15         *((volatile unsigned int*)(0x42C8E23CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS16         *((volatile unsigned int*)(0x42C8E240UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS17         *((volatile unsigned int*)(0x42C8E244UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS18         *((volatile unsigned int*)(0x42C8E248UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS19         *((volatile unsigned int*)(0x42C8E24CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS20         *((volatile unsigned int*)(0x42C8E250UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS21         *((volatile unsigned int*)(0x42C8E254UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS22         *((volatile unsigned int*)(0x42C8E258UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS23         *((volatile unsigned int*)(0x42C8E25CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS24         *((volatile unsigned int*)(0x42C8E260UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS25         *((volatile unsigned int*)(0x42C8E264UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS26         *((volatile unsigned int*)(0x42C8E268UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS27         *((volatile unsigned int*)(0x42C8E26CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS28         *((volatile unsigned int*)(0x42C8E270UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS29         *((volatile unsigned int*)(0x42C8E274UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS30         *((volatile unsigned int*)(0x42C8E278UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS31         *((volatile unsigned int*)(0x42C8E27CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS0         *((volatile unsigned int*)(0x42C8E280UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS1         *((volatile unsigned int*)(0x42C8E284UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS2         *((volatile unsigned int*)(0x42C8E288UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS3         *((volatile unsigned int*)(0x42C8E28CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS4         *((volatile unsigned int*)(0x42C8E290UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS5         *((volatile unsigned int*)(0x42C8E294UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS6         *((volatile unsigned int*)(0x42C8E298UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS7         *((volatile unsigned int*)(0x42C8E29CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS8         *((volatile unsigned int*)(0x42C8E2A0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS9         *((volatile unsigned int*)(0x42C8E2A4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS10        *((volatile unsigned int*)(0x42C8E2A8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS11        *((volatile unsigned int*)(0x42C8E2ACUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS12        *((volatile unsigned int*)(0x42C8E2B0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS13        *((volatile unsigned int*)(0x42C8E2B4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS14        *((volatile unsigned int*)(0x42C8E2B8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS15        *((volatile unsigned int*)(0x42C8E2BCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS16        *((volatile unsigned int*)(0x42C8E2C0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS17        *((volatile unsigned int*)(0x42C8E2C4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS18        *((volatile unsigned int*)(0x42C8E2C8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS19        *((volatile unsigned int*)(0x42C8E2CCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS20        *((volatile unsigned int*)(0x42C8E2D0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS21        *((volatile unsigned int*)(0x42C8E2D4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS22        *((volatile unsigned int*)(0x42C8E2D8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS23        *((volatile unsigned int*)(0x42C8E2DCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS24        *((volatile unsigned int*)(0x42C8E2E0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS25        *((volatile unsigned int*)(0x42C8E2E4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS26        *((volatile unsigned int*)(0x42C8E2E8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS27        *((volatile unsigned int*)(0x42C8E2ECUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS28        *((volatile unsigned int*)(0x42C8E2F0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS29        *((volatile unsigned int*)(0x42C8E2F4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS30        *((volatile unsigned int*)(0x42C8E2F8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB        *((volatile unsigned int*)(0x42C8E2FCUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR0          *((volatile unsigned int*)(0x42C8E300UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR1          *((volatile unsigned int*)(0x42C8E304UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR2          *((volatile unsigned int*)(0x42C8E308UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR3          *((volatile unsigned int*)(0x42C8E30CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR4          *((volatile unsigned int*)(0x42C8E310UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR5          *((volatile unsigned int*)(0x42C8E314UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR6          *((volatile unsigned int*)(0x42C8E318UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR7          *((volatile unsigned int*)(0x42C8E31CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR8          *((volatile unsigned int*)(0x42C8E320UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR9          *((volatile unsigned int*)(0x42C8E324UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR10         *((volatile unsigned int*)(0x42C8E328UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR11         *((volatile unsigned int*)(0x42C8E32CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR12         *((volatile unsigned int*)(0x42C8E330UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR13         *((volatile unsigned int*)(0x42C8E334UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR14         *((volatile unsigned int*)(0x42C8E338UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR15         *((volatile unsigned int*)(0x42C8E33CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR16         *((volatile unsigned int*)(0x42C8E340UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR17         *((volatile unsigned int*)(0x42C8E344UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR18         *((volatile unsigned int*)(0x42C8E348UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR19         *((volatile unsigned int*)(0x42C8E34CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR20         *((volatile unsigned int*)(0x42C8E350UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR21         *((volatile unsigned int*)(0x42C8E354UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR22         *((volatile unsigned int*)(0x42C8E358UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR23         *((volatile unsigned int*)(0x42C8E35CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR24         *((volatile unsigned int*)(0x42C8E360UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR25         *((volatile unsigned int*)(0x42C8E364UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR26         *((volatile unsigned int*)(0x42C8E368UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR27         *((volatile unsigned int*)(0x42C8E36CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR28         *((volatile unsigned int*)(0x42C8E370UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR29         *((volatile unsigned int*)(0x42C8E374UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR30         *((volatile unsigned int*)(0x42C8E378UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR31         *((volatile unsigned int*)(0x42C8E37CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR0          *((volatile unsigned int*)(0x42C8E380UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR1          *((volatile unsigned int*)(0x42C8E384UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR2          *((volatile unsigned int*)(0x42C8E388UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR3          *((volatile unsigned int*)(0x42C8E38CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR4          *((volatile unsigned int*)(0x42C8E390UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR5          *((volatile unsigned int*)(0x42C8E394UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR6          *((volatile unsigned int*)(0x42C8E398UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR7          *((volatile unsigned int*)(0x42C8E39CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR8          *((volatile unsigned int*)(0x42C8E3A0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR9          *((volatile unsigned int*)(0x42C8E3A4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR10         *((volatile unsigned int*)(0x42C8E3A8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR11         *((volatile unsigned int*)(0x42C8E3ACUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR12         *((volatile unsigned int*)(0x42C8E3B0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR13         *((volatile unsigned int*)(0x42C8E3B4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR14         *((volatile unsigned int*)(0x42C8E3B8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR15         *((volatile unsigned int*)(0x42C8E3BCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR16         *((volatile unsigned int*)(0x42C8E3C0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR17         *((volatile unsigned int*)(0x42C8E3C4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR18         *((volatile unsigned int*)(0x42C8E3C8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR19         *((volatile unsigned int*)(0x42C8E3CCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR20         *((volatile unsigned int*)(0x42C8E3D0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR21         *((volatile unsigned int*)(0x42C8E3D4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR22         *((volatile unsigned int*)(0x42C8E3D8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR23         *((volatile unsigned int*)(0x42C8E3DCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR24         *((volatile unsigned int*)(0x42C8E3E0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR25         *((volatile unsigned int*)(0x42C8E3E4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR26         *((volatile unsigned int*)(0x42C8E3E8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR27         *((volatile unsigned int*)(0x42C8E3ECUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR28         *((volatile unsigned int*)(0x42C8E3F0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR29         *((volatile unsigned int*)(0x42C8E3F4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR30         *((volatile unsigned int*)(0x42C8E3F8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR31         *((volatile unsigned int*)(0x42C8E3FCUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR0          *((volatile unsigned int*)(0x42C8E400UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR1          *((volatile unsigned int*)(0x42C8E404UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR2          *((volatile unsigned int*)(0x42C8E408UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR3          *((volatile unsigned int*)(0x42C8E40CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR4          *((volatile unsigned int*)(0x42C8E410UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR5          *((volatile unsigned int*)(0x42C8E414UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR6          *((volatile unsigned int*)(0x42C8E418UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR7          *((volatile unsigned int*)(0x42C8E41CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR8          *((volatile unsigned int*)(0x42C8E420UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR9          *((volatile unsigned int*)(0x42C8E424UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR10         *((volatile unsigned int*)(0x42C8E428UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR11         *((volatile unsigned int*)(0x42C8E42CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR12         *((volatile unsigned int*)(0x42C8E430UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR13         *((volatile unsigned int*)(0x42C8E434UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR14         *((volatile unsigned int*)(0x42C8E438UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR15         *((volatile unsigned int*)(0x42C8E43CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR16         *((volatile unsigned int*)(0x42C8E440UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR17         *((volatile unsigned int*)(0x42C8E444UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR18         *((volatile unsigned int*)(0x42C8E448UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR19         *((volatile unsigned int*)(0x42C8E44CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR20         *((volatile unsigned int*)(0x42C8E450UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR21         *((volatile unsigned int*)(0x42C8E454UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR22         *((volatile unsigned int*)(0x42C8E458UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR23         *((volatile unsigned int*)(0x42C8E45CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR24         *((volatile unsigned int*)(0x42C8E460UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR25         *((volatile unsigned int*)(0x42C8E464UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR26         *((volatile unsigned int*)(0x42C8E468UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR27         *((volatile unsigned int*)(0x42C8E46CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR28         *((volatile unsigned int*)(0x42C8E470UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR29         *((volatile unsigned int*)(0x42C8E474UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR30         *((volatile unsigned int*)(0x42C8E478UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42C8E480UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42C8E484UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42C8E488UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42C8E48CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42C8E490UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42C8E494UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42C8E498UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42C8E49CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42C8E4A0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42C8E4A4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42C8E4A8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42C8E4ACUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42C8E4B0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42C8E4B4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42C8E4B8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42C8E4BCUL))
+#define bFM3_ETHERNET_MAC0_TSR_TSSOVF          *((volatile unsigned int*)(0x42C8E500UL))
+#define bFM3_ETHERNET_MAC0_TSR_TSTART          *((volatile unsigned int*)(0x42C8E504UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSTS           *((volatile unsigned int*)(0x42C8E508UL))
+#define bFM3_ETHERNET_MAC0_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSSTM          *((volatile unsigned int*)(0x42C8E560UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS0          *((volatile unsigned int*)(0x42C8E564UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS1          *((volatile unsigned int*)(0x42C8E568UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS2          *((volatile unsigned int*)(0x42C8E56CUL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42C8E580UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42C8E584UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42C8E588UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42C8E58CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN0           *((volatile unsigned int*)(0x42C8E600UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN1           *((volatile unsigned int*)(0x42C8E604UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN2           *((volatile unsigned int*)(0x42C8E608UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN3           *((volatile unsigned int*)(0x42C8E60CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN4           *((volatile unsigned int*)(0x42C8E610UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN5           *((volatile unsigned int*)(0x42C8E614UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN6           *((volatile unsigned int*)(0x42C8E618UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN7           *((volatile unsigned int*)(0x42C8E61CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN8           *((volatile unsigned int*)(0x42C8E620UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN9           *((volatile unsigned int*)(0x42C8E624UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN10          *((volatile unsigned int*)(0x42C8E628UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN11          *((volatile unsigned int*)(0x42C8E62CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN12          *((volatile unsigned int*)(0x42C8E630UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN13          *((volatile unsigned int*)(0x42C8E634UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN14          *((volatile unsigned int*)(0x42C8E638UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN15          *((volatile unsigned int*)(0x42C8E63CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN16          *((volatile unsigned int*)(0x42C8E640UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN17          *((volatile unsigned int*)(0x42C8E644UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN18          *((volatile unsigned int*)(0x42C8E648UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN19          *((volatile unsigned int*)(0x42C8E64CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN20          *((volatile unsigned int*)(0x42C8E650UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN21          *((volatile unsigned int*)(0x42C8E654UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN22          *((volatile unsigned int*)(0x42C8E658UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN23          *((volatile unsigned int*)(0x42C8E65CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN24          *((volatile unsigned int*)(0x42C8E660UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN25          *((volatile unsigned int*)(0x42C8E664UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN26          *((volatile unsigned int*)(0x42C8E668UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN27          *((volatile unsigned int*)(0x42C8E66CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN28          *((volatile unsigned int*)(0x42C8E670UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN29          *((volatile unsigned int*)(0x42C8E674UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN30          *((volatile unsigned int*)(0x42C8E678UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS0           *((volatile unsigned int*)(0x42C8E680UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS1           *((volatile unsigned int*)(0x42C8E684UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS2           *((volatile unsigned int*)(0x42C8E688UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS3           *((volatile unsigned int*)(0x42C8E68CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS4           *((volatile unsigned int*)(0x42C8E690UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS5           *((volatile unsigned int*)(0x42C8E694UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS6           *((volatile unsigned int*)(0x42C8E698UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS7           *((volatile unsigned int*)(0x42C8E69CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS8           *((volatile unsigned int*)(0x42C8E6A0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS9           *((volatile unsigned int*)(0x42C8E6A4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS10          *((volatile unsigned int*)(0x42C8E6A8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS11          *((volatile unsigned int*)(0x42C8E6ACUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS12          *((volatile unsigned int*)(0x42C8E6B0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS13          *((volatile unsigned int*)(0x42C8E6B4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS14          *((volatile unsigned int*)(0x42C8E6B8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS15          *((volatile unsigned int*)(0x42C8E6BCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS16          *((volatile unsigned int*)(0x42C8E6C0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS17          *((volatile unsigned int*)(0x42C8E6C4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS18          *((volatile unsigned int*)(0x42C8E6C8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS19          *((volatile unsigned int*)(0x42C8E6CCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS20          *((volatile unsigned int*)(0x42C8E6D0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS21          *((volatile unsigned int*)(0x42C8E6D4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS22          *((volatile unsigned int*)(0x42C8E6D8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS23          *((volatile unsigned int*)(0x42C8E6DCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS24          *((volatile unsigned int*)(0x42C8E6E0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS25          *((volatile unsigned int*)(0x42C8E6E4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS26          *((volatile unsigned int*)(0x42C8E6E8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS27          *((volatile unsigned int*)(0x42C8E6ECUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS28          *((volatile unsigned int*)(0x42C8E6F0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS29          *((volatile unsigned int*)(0x42C8E6F4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS30          *((volatile unsigned int*)(0x42C8E6F8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS31          *((volatile unsigned int*)(0x42C8E6FCUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A32          *((volatile unsigned int*)(0x42C90000UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A33          *((volatile unsigned int*)(0x42C90004UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A34          *((volatile unsigned int*)(0x42C90008UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A35          *((volatile unsigned int*)(0x42C9000CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A36          *((volatile unsigned int*)(0x42C90010UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A37          *((volatile unsigned int*)(0x42C90014UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A38          *((volatile unsigned int*)(0x42C90018UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A39          *((volatile unsigned int*)(0x42C9001CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A40          *((volatile unsigned int*)(0x42C90020UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A41          *((volatile unsigned int*)(0x42C90024UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A42          *((volatile unsigned int*)(0x42C90028UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A43          *((volatile unsigned int*)(0x42C9002CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A44          *((volatile unsigned int*)(0x42C90030UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A45          *((volatile unsigned int*)(0x42C90034UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A46          *((volatile unsigned int*)(0x42C90038UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A47          *((volatile unsigned int*)(0x42C9003CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC0         *((volatile unsigned int*)(0x42C90060UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC1         *((volatile unsigned int*)(0x42C90064UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC2         *((volatile unsigned int*)(0x42C90068UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC3         *((volatile unsigned int*)(0x42C9006CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC4         *((volatile unsigned int*)(0x42C90070UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC5         *((volatile unsigned int*)(0x42C90074UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_SA           *((volatile unsigned int*)(0x42C90078UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_AE           *((volatile unsigned int*)(0x42C9007CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A0           *((volatile unsigned int*)(0x42C90080UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A1           *((volatile unsigned int*)(0x42C90084UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A2           *((volatile unsigned int*)(0x42C90088UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A3           *((volatile unsigned int*)(0x42C9008CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A4           *((volatile unsigned int*)(0x42C90090UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A5           *((volatile unsigned int*)(0x42C90094UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A6           *((volatile unsigned int*)(0x42C90098UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A7           *((volatile unsigned int*)(0x42C9009CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A8           *((volatile unsigned int*)(0x42C900A0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A9           *((volatile unsigned int*)(0x42C900A4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A10          *((volatile unsigned int*)(0x42C900A8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A11          *((volatile unsigned int*)(0x42C900ACUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A12          *((volatile unsigned int*)(0x42C900B0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A13          *((volatile unsigned int*)(0x42C900B4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A14          *((volatile unsigned int*)(0x42C900B8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A15          *((volatile unsigned int*)(0x42C900BCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A16          *((volatile unsigned int*)(0x42C900C0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A17          *((volatile unsigned int*)(0x42C900C4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A18          *((volatile unsigned int*)(0x42C900C8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A19          *((volatile unsigned int*)(0x42C900CCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A20          *((volatile unsigned int*)(0x42C900D0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A21          *((volatile unsigned int*)(0x42C900D4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A22          *((volatile unsigned int*)(0x42C900D8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A23          *((volatile unsigned int*)(0x42C900DCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A24          *((volatile unsigned int*)(0x42C900E0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A25          *((volatile unsigned int*)(0x42C900E4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A26          *((volatile unsigned int*)(0x42C900E8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A27          *((volatile unsigned int*)(0x42C900ECUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A28          *((volatile unsigned int*)(0x42C900F0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A29          *((volatile unsigned int*)(0x42C900F4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A30          *((volatile unsigned int*)(0x42C900F8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A31          *((volatile unsigned int*)(0x42C900FCUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A32          *((volatile unsigned int*)(0x42C90100UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A33          *((volatile unsigned int*)(0x42C90104UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A34          *((volatile unsigned int*)(0x42C90108UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A35          *((volatile unsigned int*)(0x42C9010CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A36          *((volatile unsigned int*)(0x42C90110UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A37          *((volatile unsigned int*)(0x42C90114UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A38          *((volatile unsigned int*)(0x42C90118UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A39          *((volatile unsigned int*)(0x42C9011CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A40          *((volatile unsigned int*)(0x42C90120UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A41          *((volatile unsigned int*)(0x42C90124UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A42          *((volatile unsigned int*)(0x42C90128UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A43          *((volatile unsigned int*)(0x42C9012CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A44          *((volatile unsigned int*)(0x42C90130UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A45          *((volatile unsigned int*)(0x42C90134UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A46          *((volatile unsigned int*)(0x42C90138UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A47          *((volatile unsigned int*)(0x42C9013CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC0         *((volatile unsigned int*)(0x42C90160UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC1         *((volatile unsigned int*)(0x42C90164UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC2         *((volatile unsigned int*)(0x42C90168UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC3         *((volatile unsigned int*)(0x42C9016CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC4         *((volatile unsigned int*)(0x42C90170UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC5         *((volatile unsigned int*)(0x42C90174UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_SA           *((volatile unsigned int*)(0x42C90178UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_AE           *((volatile unsigned int*)(0x42C9017CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A0           *((volatile unsigned int*)(0x42C90180UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A1           *((volatile unsigned int*)(0x42C90184UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A2           *((volatile unsigned int*)(0x42C90188UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A3           *((volatile unsigned int*)(0x42C9018CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A4           *((volatile unsigned int*)(0x42C90190UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A5           *((volatile unsigned int*)(0x42C90194UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A6           *((volatile unsigned int*)(0x42C90198UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A7           *((volatile unsigned int*)(0x42C9019CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A8           *((volatile unsigned int*)(0x42C901A0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A9           *((volatile unsigned int*)(0x42C901A4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A10          *((volatile unsigned int*)(0x42C901A8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A11          *((volatile unsigned int*)(0x42C901ACUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A12          *((volatile unsigned int*)(0x42C901B0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A13          *((volatile unsigned int*)(0x42C901B4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A14          *((volatile unsigned int*)(0x42C901B8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A15          *((volatile unsigned int*)(0x42C901BCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A16          *((volatile unsigned int*)(0x42C901C0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A17          *((volatile unsigned int*)(0x42C901C4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A18          *((volatile unsigned int*)(0x42C901C8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A19          *((volatile unsigned int*)(0x42C901CCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A20          *((volatile unsigned int*)(0x42C901D0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A21          *((volatile unsigned int*)(0x42C901D4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A22          *((volatile unsigned int*)(0x42C901D8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A23          *((volatile unsigned int*)(0x42C901DCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A24          *((volatile unsigned int*)(0x42C901E0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A25          *((volatile unsigned int*)(0x42C901E4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A26          *((volatile unsigned int*)(0x42C901E8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A27          *((volatile unsigned int*)(0x42C901ECUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A28          *((volatile unsigned int*)(0x42C901F0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A29          *((volatile unsigned int*)(0x42C901F4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A30          *((volatile unsigned int*)(0x42C901F8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A31          *((volatile unsigned int*)(0x42C901FCUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A32          *((volatile unsigned int*)(0x42C90200UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A33          *((volatile unsigned int*)(0x42C90204UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A34          *((volatile unsigned int*)(0x42C90208UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A35          *((volatile unsigned int*)(0x42C9020CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A36          *((volatile unsigned int*)(0x42C90210UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A37          *((volatile unsigned int*)(0x42C90214UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A38          *((volatile unsigned int*)(0x42C90218UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A39          *((volatile unsigned int*)(0x42C9021CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A40          *((volatile unsigned int*)(0x42C90220UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A41          *((volatile unsigned int*)(0x42C90224UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A42          *((volatile unsigned int*)(0x42C90228UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A43          *((volatile unsigned int*)(0x42C9022CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A44          *((volatile unsigned int*)(0x42C90230UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A45          *((volatile unsigned int*)(0x42C90234UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A46          *((volatile unsigned int*)(0x42C90238UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A47          *((volatile unsigned int*)(0x42C9023CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC0         *((volatile unsigned int*)(0x42C90260UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC1         *((volatile unsigned int*)(0x42C90264UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC2         *((volatile unsigned int*)(0x42C90268UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC3         *((volatile unsigned int*)(0x42C9026CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC4         *((volatile unsigned int*)(0x42C90270UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC5         *((volatile unsigned int*)(0x42C90274UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_SA           *((volatile unsigned int*)(0x42C90278UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_AE           *((volatile unsigned int*)(0x42C9027CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A0           *((volatile unsigned int*)(0x42C90280UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A1           *((volatile unsigned int*)(0x42C90284UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A2           *((volatile unsigned int*)(0x42C90288UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A3           *((volatile unsigned int*)(0x42C9028CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A4           *((volatile unsigned int*)(0x42C90290UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A5           *((volatile unsigned int*)(0x42C90294UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A6           *((volatile unsigned int*)(0x42C90298UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A7           *((volatile unsigned int*)(0x42C9029CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A8           *((volatile unsigned int*)(0x42C902A0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A9           *((volatile unsigned int*)(0x42C902A4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A10          *((volatile unsigned int*)(0x42C902A8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A11          *((volatile unsigned int*)(0x42C902ACUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A12          *((volatile unsigned int*)(0x42C902B0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A13          *((volatile unsigned int*)(0x42C902B4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A14          *((volatile unsigned int*)(0x42C902B8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A15          *((volatile unsigned int*)(0x42C902BCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A16          *((volatile unsigned int*)(0x42C902C0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A17          *((volatile unsigned int*)(0x42C902C4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A18          *((volatile unsigned int*)(0x42C902C8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A19          *((volatile unsigned int*)(0x42C902CCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A20          *((volatile unsigned int*)(0x42C902D0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A21          *((volatile unsigned int*)(0x42C902D4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A22          *((volatile unsigned int*)(0x42C902D8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A23          *((volatile unsigned int*)(0x42C902DCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A24          *((volatile unsigned int*)(0x42C902E0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A25          *((volatile unsigned int*)(0x42C902E4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A26          *((volatile unsigned int*)(0x42C902E8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A27          *((volatile unsigned int*)(0x42C902ECUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A28          *((volatile unsigned int*)(0x42C902F0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A29          *((volatile unsigned int*)(0x42C902F4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A30          *((volatile unsigned int*)(0x42C902F8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A31          *((volatile unsigned int*)(0x42C902FCUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A32          *((volatile unsigned int*)(0x42C90300UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A33          *((volatile unsigned int*)(0x42C90304UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A34          *((volatile unsigned int*)(0x42C90308UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A35          *((volatile unsigned int*)(0x42C9030CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A36          *((volatile unsigned int*)(0x42C90310UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A37          *((volatile unsigned int*)(0x42C90314UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A38          *((volatile unsigned int*)(0x42C90318UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A39          *((volatile unsigned int*)(0x42C9031CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A40          *((volatile unsigned int*)(0x42C90320UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A41          *((volatile unsigned int*)(0x42C90324UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A42          *((volatile unsigned int*)(0x42C90328UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A43          *((volatile unsigned int*)(0x42C9032CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A44          *((volatile unsigned int*)(0x42C90330UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A45          *((volatile unsigned int*)(0x42C90334UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A46          *((volatile unsigned int*)(0x42C90338UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A47          *((volatile unsigned int*)(0x42C9033CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC0         *((volatile unsigned int*)(0x42C90360UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC1         *((volatile unsigned int*)(0x42C90364UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC2         *((volatile unsigned int*)(0x42C90368UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC3         *((volatile unsigned int*)(0x42C9036CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC4         *((volatile unsigned int*)(0x42C90370UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC5         *((volatile unsigned int*)(0x42C90374UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_SA           *((volatile unsigned int*)(0x42C90378UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_AE           *((volatile unsigned int*)(0x42C9037CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A0           *((volatile unsigned int*)(0x42C90380UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A1           *((volatile unsigned int*)(0x42C90384UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A2           *((volatile unsigned int*)(0x42C90388UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A3           *((volatile unsigned int*)(0x42C9038CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A4           *((volatile unsigned int*)(0x42C90390UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A5           *((volatile unsigned int*)(0x42C90394UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A6           *((volatile unsigned int*)(0x42C90398UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A7           *((volatile unsigned int*)(0x42C9039CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A8           *((volatile unsigned int*)(0x42C903A0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A9           *((volatile unsigned int*)(0x42C903A4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A10          *((volatile unsigned int*)(0x42C903A8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A11          *((volatile unsigned int*)(0x42C903ACUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A12          *((volatile unsigned int*)(0x42C903B0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A13          *((volatile unsigned int*)(0x42C903B4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A14          *((volatile unsigned int*)(0x42C903B8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A15          *((volatile unsigned int*)(0x42C903BCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A16          *((volatile unsigned int*)(0x42C903C0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A17          *((volatile unsigned int*)(0x42C903C4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A18          *((volatile unsigned int*)(0x42C903C8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A19          *((volatile unsigned int*)(0x42C903CCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A20          *((volatile unsigned int*)(0x42C903D0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A21          *((volatile unsigned int*)(0x42C903D4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A22          *((volatile unsigned int*)(0x42C903D8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A23          *((volatile unsigned int*)(0x42C903DCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A24          *((volatile unsigned int*)(0x42C903E0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A25          *((volatile unsigned int*)(0x42C903E4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A26          *((volatile unsigned int*)(0x42C903E8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A27          *((volatile unsigned int*)(0x42C903ECUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A28          *((volatile unsigned int*)(0x42C903F0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A29          *((volatile unsigned int*)(0x42C903F4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A30          *((volatile unsigned int*)(0x42C903F8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A31          *((volatile unsigned int*)(0x42C903FCUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A32          *((volatile unsigned int*)(0x42C90400UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A33          *((volatile unsigned int*)(0x42C90404UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A34          *((volatile unsigned int*)(0x42C90408UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A35          *((volatile unsigned int*)(0x42C9040CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A36          *((volatile unsigned int*)(0x42C90410UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A37          *((volatile unsigned int*)(0x42C90414UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A38          *((volatile unsigned int*)(0x42C90418UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A39          *((volatile unsigned int*)(0x42C9041CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A40          *((volatile unsigned int*)(0x42C90420UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A41          *((volatile unsigned int*)(0x42C90424UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A42          *((volatile unsigned int*)(0x42C90428UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A43          *((volatile unsigned int*)(0x42C9042CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A44          *((volatile unsigned int*)(0x42C90430UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A45          *((volatile unsigned int*)(0x42C90434UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A46          *((volatile unsigned int*)(0x42C90438UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A47          *((volatile unsigned int*)(0x42C9043CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC0         *((volatile unsigned int*)(0x42C90460UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC1         *((volatile unsigned int*)(0x42C90464UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC2         *((volatile unsigned int*)(0x42C90468UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC3         *((volatile unsigned int*)(0x42C9046CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC4         *((volatile unsigned int*)(0x42C90470UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC5         *((volatile unsigned int*)(0x42C90474UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_SA           *((volatile unsigned int*)(0x42C90478UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_AE           *((volatile unsigned int*)(0x42C9047CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A0           *((volatile unsigned int*)(0x42C90480UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A1           *((volatile unsigned int*)(0x42C90484UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A2           *((volatile unsigned int*)(0x42C90488UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A3           *((volatile unsigned int*)(0x42C9048CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A4           *((volatile unsigned int*)(0x42C90490UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A5           *((volatile unsigned int*)(0x42C90494UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A6           *((volatile unsigned int*)(0x42C90498UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A7           *((volatile unsigned int*)(0x42C9049CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A8           *((volatile unsigned int*)(0x42C904A0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A9           *((volatile unsigned int*)(0x42C904A4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A10          *((volatile unsigned int*)(0x42C904A8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A11          *((volatile unsigned int*)(0x42C904ACUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A12          *((volatile unsigned int*)(0x42C904B0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A13          *((volatile unsigned int*)(0x42C904B4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A14          *((volatile unsigned int*)(0x42C904B8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A15          *((volatile unsigned int*)(0x42C904BCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A16          *((volatile unsigned int*)(0x42C904C0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A17          *((volatile unsigned int*)(0x42C904C4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A18          *((volatile unsigned int*)(0x42C904C8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A19          *((volatile unsigned int*)(0x42C904CCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A20          *((volatile unsigned int*)(0x42C904D0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A21          *((volatile unsigned int*)(0x42C904D4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A22          *((volatile unsigned int*)(0x42C904D8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A23          *((volatile unsigned int*)(0x42C904DCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A24          *((volatile unsigned int*)(0x42C904E0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A25          *((volatile unsigned int*)(0x42C904E4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A26          *((volatile unsigned int*)(0x42C904E8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A27          *((volatile unsigned int*)(0x42C904ECUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A28          *((volatile unsigned int*)(0x42C904F0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A29          *((volatile unsigned int*)(0x42C904F4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A30          *((volatile unsigned int*)(0x42C904F8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A31          *((volatile unsigned int*)(0x42C904FCUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A32          *((volatile unsigned int*)(0x42C90500UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A33          *((volatile unsigned int*)(0x42C90504UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A34          *((volatile unsigned int*)(0x42C90508UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A35          *((volatile unsigned int*)(0x42C9050CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A36          *((volatile unsigned int*)(0x42C90510UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A37          *((volatile unsigned int*)(0x42C90514UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A38          *((volatile unsigned int*)(0x42C90518UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A39          *((volatile unsigned int*)(0x42C9051CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A40          *((volatile unsigned int*)(0x42C90520UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A41          *((volatile unsigned int*)(0x42C90524UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A42          *((volatile unsigned int*)(0x42C90528UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A43          *((volatile unsigned int*)(0x42C9052CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A44          *((volatile unsigned int*)(0x42C90530UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A45          *((volatile unsigned int*)(0x42C90534UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A46          *((volatile unsigned int*)(0x42C90538UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A47          *((volatile unsigned int*)(0x42C9053CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC0         *((volatile unsigned int*)(0x42C90560UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC1         *((volatile unsigned int*)(0x42C90564UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC2         *((volatile unsigned int*)(0x42C90568UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC3         *((volatile unsigned int*)(0x42C9056CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC4         *((volatile unsigned int*)(0x42C90570UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC5         *((volatile unsigned int*)(0x42C90574UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_SA           *((volatile unsigned int*)(0x42C90578UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_AE           *((volatile unsigned int*)(0x42C9057CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A0           *((volatile unsigned int*)(0x42C90580UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A1           *((volatile unsigned int*)(0x42C90584UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A2           *((volatile unsigned int*)(0x42C90588UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A3           *((volatile unsigned int*)(0x42C9058CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A4           *((volatile unsigned int*)(0x42C90590UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A5           *((volatile unsigned int*)(0x42C90594UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A6           *((volatile unsigned int*)(0x42C90598UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A7           *((volatile unsigned int*)(0x42C9059CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A8           *((volatile unsigned int*)(0x42C905A0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A9           *((volatile unsigned int*)(0x42C905A4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A10          *((volatile unsigned int*)(0x42C905A8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A11          *((volatile unsigned int*)(0x42C905ACUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A12          *((volatile unsigned int*)(0x42C905B0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A13          *((volatile unsigned int*)(0x42C905B4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A14          *((volatile unsigned int*)(0x42C905B8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A15          *((volatile unsigned int*)(0x42C905BCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A16          *((volatile unsigned int*)(0x42C905C0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A17          *((volatile unsigned int*)(0x42C905C4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A18          *((volatile unsigned int*)(0x42C905C8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A19          *((volatile unsigned int*)(0x42C905CCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A20          *((volatile unsigned int*)(0x42C905D0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A21          *((volatile unsigned int*)(0x42C905D4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A22          *((volatile unsigned int*)(0x42C905D8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A23          *((volatile unsigned int*)(0x42C905DCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A24          *((volatile unsigned int*)(0x42C905E0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A25          *((volatile unsigned int*)(0x42C905E4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A26          *((volatile unsigned int*)(0x42C905E8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A27          *((volatile unsigned int*)(0x42C905ECUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A28          *((volatile unsigned int*)(0x42C905F0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A29          *((volatile unsigned int*)(0x42C905F4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A30          *((volatile unsigned int*)(0x42C905F8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A31          *((volatile unsigned int*)(0x42C905FCUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A32          *((volatile unsigned int*)(0x42C90600UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A33          *((volatile unsigned int*)(0x42C90604UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A34          *((volatile unsigned int*)(0x42C90608UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A35          *((volatile unsigned int*)(0x42C9060CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A36          *((volatile unsigned int*)(0x42C90610UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A37          *((volatile unsigned int*)(0x42C90614UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A38          *((volatile unsigned int*)(0x42C90618UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A39          *((volatile unsigned int*)(0x42C9061CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A40          *((volatile unsigned int*)(0x42C90620UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A41          *((volatile unsigned int*)(0x42C90624UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A42          *((volatile unsigned int*)(0x42C90628UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A43          *((volatile unsigned int*)(0x42C9062CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A44          *((volatile unsigned int*)(0x42C90630UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A45          *((volatile unsigned int*)(0x42C90634UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A46          *((volatile unsigned int*)(0x42C90638UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A47          *((volatile unsigned int*)(0x42C9063CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC0         *((volatile unsigned int*)(0x42C90660UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC1         *((volatile unsigned int*)(0x42C90664UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC2         *((volatile unsigned int*)(0x42C90668UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC3         *((volatile unsigned int*)(0x42C9066CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC4         *((volatile unsigned int*)(0x42C90670UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC5         *((volatile unsigned int*)(0x42C90674UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_SA           *((volatile unsigned int*)(0x42C90678UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_AE           *((volatile unsigned int*)(0x42C9067CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A0           *((volatile unsigned int*)(0x42C90680UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A1           *((volatile unsigned int*)(0x42C90684UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A2           *((volatile unsigned int*)(0x42C90688UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A3           *((volatile unsigned int*)(0x42C9068CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A4           *((volatile unsigned int*)(0x42C90690UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A5           *((volatile unsigned int*)(0x42C90694UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A6           *((volatile unsigned int*)(0x42C90698UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A7           *((volatile unsigned int*)(0x42C9069CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A8           *((volatile unsigned int*)(0x42C906A0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A9           *((volatile unsigned int*)(0x42C906A4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A10          *((volatile unsigned int*)(0x42C906A8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A11          *((volatile unsigned int*)(0x42C906ACUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A12          *((volatile unsigned int*)(0x42C906B0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A13          *((volatile unsigned int*)(0x42C906B4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A14          *((volatile unsigned int*)(0x42C906B8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A15          *((volatile unsigned int*)(0x42C906BCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A16          *((volatile unsigned int*)(0x42C906C0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A17          *((volatile unsigned int*)(0x42C906C4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A18          *((volatile unsigned int*)(0x42C906C8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A19          *((volatile unsigned int*)(0x42C906CCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A20          *((volatile unsigned int*)(0x42C906D0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A21          *((volatile unsigned int*)(0x42C906D4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A22          *((volatile unsigned int*)(0x42C906D8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A23          *((volatile unsigned int*)(0x42C906DCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A24          *((volatile unsigned int*)(0x42C906E0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A25          *((volatile unsigned int*)(0x42C906E4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A26          *((volatile unsigned int*)(0x42C906E8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A27          *((volatile unsigned int*)(0x42C906ECUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A28          *((volatile unsigned int*)(0x42C906F0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A29          *((volatile unsigned int*)(0x42C906F4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A30          *((volatile unsigned int*)(0x42C906F8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A31          *((volatile unsigned int*)(0x42C906FCUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A32          *((volatile unsigned int*)(0x42C90700UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A33          *((volatile unsigned int*)(0x42C90704UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A34          *((volatile unsigned int*)(0x42C90708UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A35          *((volatile unsigned int*)(0x42C9070CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A36          *((volatile unsigned int*)(0x42C90710UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A37          *((volatile unsigned int*)(0x42C90714UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A38          *((volatile unsigned int*)(0x42C90718UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A39          *((volatile unsigned int*)(0x42C9071CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A40          *((volatile unsigned int*)(0x42C90720UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A41          *((volatile unsigned int*)(0x42C90724UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A42          *((volatile unsigned int*)(0x42C90728UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A43          *((volatile unsigned int*)(0x42C9072CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A44          *((volatile unsigned int*)(0x42C90730UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A45          *((volatile unsigned int*)(0x42C90734UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A46          *((volatile unsigned int*)(0x42C90738UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A47          *((volatile unsigned int*)(0x42C9073CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC0         *((volatile unsigned int*)(0x42C90760UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC1         *((volatile unsigned int*)(0x42C90764UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC2         *((volatile unsigned int*)(0x42C90768UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC3         *((volatile unsigned int*)(0x42C9076CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC4         *((volatile unsigned int*)(0x42C90770UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC5         *((volatile unsigned int*)(0x42C90774UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_SA           *((volatile unsigned int*)(0x42C90778UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_AE           *((volatile unsigned int*)(0x42C9077CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A0           *((volatile unsigned int*)(0x42C90780UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A1           *((volatile unsigned int*)(0x42C90784UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A2           *((volatile unsigned int*)(0x42C90788UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A3           *((volatile unsigned int*)(0x42C9078CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A4           *((volatile unsigned int*)(0x42C90790UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A5           *((volatile unsigned int*)(0x42C90794UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A6           *((volatile unsigned int*)(0x42C90798UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A7           *((volatile unsigned int*)(0x42C9079CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A8           *((volatile unsigned int*)(0x42C907A0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A9           *((volatile unsigned int*)(0x42C907A4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A10          *((volatile unsigned int*)(0x42C907A8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A11          *((volatile unsigned int*)(0x42C907ACUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A12          *((volatile unsigned int*)(0x42C907B0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A13          *((volatile unsigned int*)(0x42C907B4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A14          *((volatile unsigned int*)(0x42C907B8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A15          *((volatile unsigned int*)(0x42C907BCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A16          *((volatile unsigned int*)(0x42C907C0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A17          *((volatile unsigned int*)(0x42C907C4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A18          *((volatile unsigned int*)(0x42C907C8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A19          *((volatile unsigned int*)(0x42C907CCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A20          *((volatile unsigned int*)(0x42C907D0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A21          *((volatile unsigned int*)(0x42C907D4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A22          *((volatile unsigned int*)(0x42C907D8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A23          *((volatile unsigned int*)(0x42C907DCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A24          *((volatile unsigned int*)(0x42C907E0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A25          *((volatile unsigned int*)(0x42C907E4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A26          *((volatile unsigned int*)(0x42C907E8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A27          *((volatile unsigned int*)(0x42C907ECUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A28          *((volatile unsigned int*)(0x42C907F0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A29          *((volatile unsigned int*)(0x42C907F4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A30          *((volatile unsigned int*)(0x42C907F8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A31          *((volatile unsigned int*)(0x42C907FCUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A32          *((volatile unsigned int*)(0x42C90800UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A33          *((volatile unsigned int*)(0x42C90804UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A34          *((volatile unsigned int*)(0x42C90808UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A35          *((volatile unsigned int*)(0x42C9080CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A36          *((volatile unsigned int*)(0x42C90810UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A37          *((volatile unsigned int*)(0x42C90814UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A38          *((volatile unsigned int*)(0x42C90818UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A39          *((volatile unsigned int*)(0x42C9081CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A40          *((volatile unsigned int*)(0x42C90820UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A41          *((volatile unsigned int*)(0x42C90824UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A42          *((volatile unsigned int*)(0x42C90828UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A43          *((volatile unsigned int*)(0x42C9082CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A44          *((volatile unsigned int*)(0x42C90830UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A45          *((volatile unsigned int*)(0x42C90834UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A46          *((volatile unsigned int*)(0x42C90838UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A47          *((volatile unsigned int*)(0x42C9083CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC0         *((volatile unsigned int*)(0x42C90860UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC1         *((volatile unsigned int*)(0x42C90864UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC2         *((volatile unsigned int*)(0x42C90868UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC3         *((volatile unsigned int*)(0x42C9086CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC4         *((volatile unsigned int*)(0x42C90870UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC5         *((volatile unsigned int*)(0x42C90874UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_SA           *((volatile unsigned int*)(0x42C90878UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_AE           *((volatile unsigned int*)(0x42C9087CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A0           *((volatile unsigned int*)(0x42C90880UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A1           *((volatile unsigned int*)(0x42C90884UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A2           *((volatile unsigned int*)(0x42C90888UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A3           *((volatile unsigned int*)(0x42C9088CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A4           *((volatile unsigned int*)(0x42C90890UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A5           *((volatile unsigned int*)(0x42C90894UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A6           *((volatile unsigned int*)(0x42C90898UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A7           *((volatile unsigned int*)(0x42C9089CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A8           *((volatile unsigned int*)(0x42C908A0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A9           *((volatile unsigned int*)(0x42C908A4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A10          *((volatile unsigned int*)(0x42C908A8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A11          *((volatile unsigned int*)(0x42C908ACUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A12          *((volatile unsigned int*)(0x42C908B0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A13          *((volatile unsigned int*)(0x42C908B4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A14          *((volatile unsigned int*)(0x42C908B8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A15          *((volatile unsigned int*)(0x42C908BCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A16          *((volatile unsigned int*)(0x42C908C0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A17          *((volatile unsigned int*)(0x42C908C4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A18          *((volatile unsigned int*)(0x42C908C8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A19          *((volatile unsigned int*)(0x42C908CCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A20          *((volatile unsigned int*)(0x42C908D0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A21          *((volatile unsigned int*)(0x42C908D4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A22          *((volatile unsigned int*)(0x42C908D8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A23          *((volatile unsigned int*)(0x42C908DCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A24          *((volatile unsigned int*)(0x42C908E0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A25          *((volatile unsigned int*)(0x42C908E4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A26          *((volatile unsigned int*)(0x42C908E8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A27          *((volatile unsigned int*)(0x42C908ECUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A28          *((volatile unsigned int*)(0x42C908F0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A29          *((volatile unsigned int*)(0x42C908F4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A30          *((volatile unsigned int*)(0x42C908F8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A31          *((volatile unsigned int*)(0x42C908FCUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A32          *((volatile unsigned int*)(0x42C90900UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A33          *((volatile unsigned int*)(0x42C90904UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A34          *((volatile unsigned int*)(0x42C90908UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A35          *((volatile unsigned int*)(0x42C9090CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A36          *((volatile unsigned int*)(0x42C90910UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A37          *((volatile unsigned int*)(0x42C90914UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A38          *((volatile unsigned int*)(0x42C90918UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A39          *((volatile unsigned int*)(0x42C9091CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A40          *((volatile unsigned int*)(0x42C90920UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A41          *((volatile unsigned int*)(0x42C90924UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A42          *((volatile unsigned int*)(0x42C90928UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A43          *((volatile unsigned int*)(0x42C9092CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A44          *((volatile unsigned int*)(0x42C90930UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A45          *((volatile unsigned int*)(0x42C90934UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A46          *((volatile unsigned int*)(0x42C90938UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A47          *((volatile unsigned int*)(0x42C9093CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC0         *((volatile unsigned int*)(0x42C90960UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC1         *((volatile unsigned int*)(0x42C90964UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC2         *((volatile unsigned int*)(0x42C90968UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC3         *((volatile unsigned int*)(0x42C9096CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC4         *((volatile unsigned int*)(0x42C90970UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC5         *((volatile unsigned int*)(0x42C90974UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_SA           *((volatile unsigned int*)(0x42C90978UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_AE           *((volatile unsigned int*)(0x42C9097CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A0           *((volatile unsigned int*)(0x42C90980UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A1           *((volatile unsigned int*)(0x42C90984UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A2           *((volatile unsigned int*)(0x42C90988UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A3           *((volatile unsigned int*)(0x42C9098CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A4           *((volatile unsigned int*)(0x42C90990UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A5           *((volatile unsigned int*)(0x42C90994UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A6           *((volatile unsigned int*)(0x42C90998UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A7           *((volatile unsigned int*)(0x42C9099CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A8           *((volatile unsigned int*)(0x42C909A0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A9           *((volatile unsigned int*)(0x42C909A4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A10          *((volatile unsigned int*)(0x42C909A8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A11          *((volatile unsigned int*)(0x42C909ACUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A12          *((volatile unsigned int*)(0x42C909B0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A13          *((volatile unsigned int*)(0x42C909B4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A14          *((volatile unsigned int*)(0x42C909B8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A15          *((volatile unsigned int*)(0x42C909BCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A16          *((volatile unsigned int*)(0x42C909C0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A17          *((volatile unsigned int*)(0x42C909C4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A18          *((volatile unsigned int*)(0x42C909C8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A19          *((volatile unsigned int*)(0x42C909CCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A20          *((volatile unsigned int*)(0x42C909D0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A21          *((volatile unsigned int*)(0x42C909D4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A22          *((volatile unsigned int*)(0x42C909D8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A23          *((volatile unsigned int*)(0x42C909DCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A24          *((volatile unsigned int*)(0x42C909E0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A25          *((volatile unsigned int*)(0x42C909E4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A26          *((volatile unsigned int*)(0x42C909E8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A27          *((volatile unsigned int*)(0x42C909ECUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A28          *((volatile unsigned int*)(0x42C909F0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A29          *((volatile unsigned int*)(0x42C909F4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A30          *((volatile unsigned int*)(0x42C909F8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A31          *((volatile unsigned int*)(0x42C909FCUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A32          *((volatile unsigned int*)(0x42C90A00UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A33          *((volatile unsigned int*)(0x42C90A04UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A34          *((volatile unsigned int*)(0x42C90A08UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A35          *((volatile unsigned int*)(0x42C90A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A36          *((volatile unsigned int*)(0x42C90A10UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A37          *((volatile unsigned int*)(0x42C90A14UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A38          *((volatile unsigned int*)(0x42C90A18UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A39          *((volatile unsigned int*)(0x42C90A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A40          *((volatile unsigned int*)(0x42C90A20UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A41          *((volatile unsigned int*)(0x42C90A24UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A42          *((volatile unsigned int*)(0x42C90A28UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A43          *((volatile unsigned int*)(0x42C90A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A44          *((volatile unsigned int*)(0x42C90A30UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A45          *((volatile unsigned int*)(0x42C90A34UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A46          *((volatile unsigned int*)(0x42C90A38UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A47          *((volatile unsigned int*)(0x42C90A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC0         *((volatile unsigned int*)(0x42C90A60UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC1         *((volatile unsigned int*)(0x42C90A64UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC2         *((volatile unsigned int*)(0x42C90A68UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC3         *((volatile unsigned int*)(0x42C90A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC4         *((volatile unsigned int*)(0x42C90A70UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC5         *((volatile unsigned int*)(0x42C90A74UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_SA           *((volatile unsigned int*)(0x42C90A78UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_AE           *((volatile unsigned int*)(0x42C90A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A0           *((volatile unsigned int*)(0x42C90A80UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A1           *((volatile unsigned int*)(0x42C90A84UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A2           *((volatile unsigned int*)(0x42C90A88UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A3           *((volatile unsigned int*)(0x42C90A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A4           *((volatile unsigned int*)(0x42C90A90UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A5           *((volatile unsigned int*)(0x42C90A94UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A6           *((volatile unsigned int*)(0x42C90A98UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A7           *((volatile unsigned int*)(0x42C90A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A8           *((volatile unsigned int*)(0x42C90AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A9           *((volatile unsigned int*)(0x42C90AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A10          *((volatile unsigned int*)(0x42C90AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A11          *((volatile unsigned int*)(0x42C90AACUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A12          *((volatile unsigned int*)(0x42C90AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A13          *((volatile unsigned int*)(0x42C90AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A14          *((volatile unsigned int*)(0x42C90AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A15          *((volatile unsigned int*)(0x42C90ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A16          *((volatile unsigned int*)(0x42C90AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A17          *((volatile unsigned int*)(0x42C90AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A18          *((volatile unsigned int*)(0x42C90AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A19          *((volatile unsigned int*)(0x42C90ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A20          *((volatile unsigned int*)(0x42C90AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A21          *((volatile unsigned int*)(0x42C90AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A22          *((volatile unsigned int*)(0x42C90AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A23          *((volatile unsigned int*)(0x42C90ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A24          *((volatile unsigned int*)(0x42C90AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A25          *((volatile unsigned int*)(0x42C90AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A26          *((volatile unsigned int*)(0x42C90AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A27          *((volatile unsigned int*)(0x42C90AECUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A28          *((volatile unsigned int*)(0x42C90AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A29          *((volatile unsigned int*)(0x42C90AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A30          *((volatile unsigned int*)(0x42C90AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A31          *((volatile unsigned int*)(0x42C90AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A32          *((volatile unsigned int*)(0x42C90B00UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A33          *((volatile unsigned int*)(0x42C90B04UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A34          *((volatile unsigned int*)(0x42C90B08UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A35          *((volatile unsigned int*)(0x42C90B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A36          *((volatile unsigned int*)(0x42C90B10UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A37          *((volatile unsigned int*)(0x42C90B14UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A38          *((volatile unsigned int*)(0x42C90B18UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A39          *((volatile unsigned int*)(0x42C90B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A40          *((volatile unsigned int*)(0x42C90B20UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A41          *((volatile unsigned int*)(0x42C90B24UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A42          *((volatile unsigned int*)(0x42C90B28UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A43          *((volatile unsigned int*)(0x42C90B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A44          *((volatile unsigned int*)(0x42C90B30UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A45          *((volatile unsigned int*)(0x42C90B34UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A46          *((volatile unsigned int*)(0x42C90B38UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A47          *((volatile unsigned int*)(0x42C90B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC0         *((volatile unsigned int*)(0x42C90B60UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC1         *((volatile unsigned int*)(0x42C90B64UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC2         *((volatile unsigned int*)(0x42C90B68UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC3         *((volatile unsigned int*)(0x42C90B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC4         *((volatile unsigned int*)(0x42C90B70UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC5         *((volatile unsigned int*)(0x42C90B74UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_SA           *((volatile unsigned int*)(0x42C90B78UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_AE           *((volatile unsigned int*)(0x42C90B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A0           *((volatile unsigned int*)(0x42C90B80UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A1           *((volatile unsigned int*)(0x42C90B84UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A2           *((volatile unsigned int*)(0x42C90B88UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A3           *((volatile unsigned int*)(0x42C90B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A4           *((volatile unsigned int*)(0x42C90B90UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A5           *((volatile unsigned int*)(0x42C90B94UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A6           *((volatile unsigned int*)(0x42C90B98UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A7           *((volatile unsigned int*)(0x42C90B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A8           *((volatile unsigned int*)(0x42C90BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A9           *((volatile unsigned int*)(0x42C90BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A10          *((volatile unsigned int*)(0x42C90BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A11          *((volatile unsigned int*)(0x42C90BACUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A12          *((volatile unsigned int*)(0x42C90BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A13          *((volatile unsigned int*)(0x42C90BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A14          *((volatile unsigned int*)(0x42C90BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A15          *((volatile unsigned int*)(0x42C90BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A16          *((volatile unsigned int*)(0x42C90BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A17          *((volatile unsigned int*)(0x42C90BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A18          *((volatile unsigned int*)(0x42C90BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A19          *((volatile unsigned int*)(0x42C90BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A20          *((volatile unsigned int*)(0x42C90BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A21          *((volatile unsigned int*)(0x42C90BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A22          *((volatile unsigned int*)(0x42C90BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A23          *((volatile unsigned int*)(0x42C90BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A24          *((volatile unsigned int*)(0x42C90BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A25          *((volatile unsigned int*)(0x42C90BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A26          *((volatile unsigned int*)(0x42C90BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A27          *((volatile unsigned int*)(0x42C90BECUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A28          *((volatile unsigned int*)(0x42C90BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A29          *((volatile unsigned int*)(0x42C90BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A30          *((volatile unsigned int*)(0x42C90BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A31          *((volatile unsigned int*)(0x42C90BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A32          *((volatile unsigned int*)(0x42C90C00UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A33          *((volatile unsigned int*)(0x42C90C04UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A34          *((volatile unsigned int*)(0x42C90C08UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A35          *((volatile unsigned int*)(0x42C90C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A36          *((volatile unsigned int*)(0x42C90C10UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A37          *((volatile unsigned int*)(0x42C90C14UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A38          *((volatile unsigned int*)(0x42C90C18UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A39          *((volatile unsigned int*)(0x42C90C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A40          *((volatile unsigned int*)(0x42C90C20UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A41          *((volatile unsigned int*)(0x42C90C24UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A42          *((volatile unsigned int*)(0x42C90C28UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A43          *((volatile unsigned int*)(0x42C90C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A44          *((volatile unsigned int*)(0x42C90C30UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A45          *((volatile unsigned int*)(0x42C90C34UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A46          *((volatile unsigned int*)(0x42C90C38UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A47          *((volatile unsigned int*)(0x42C90C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC0         *((volatile unsigned int*)(0x42C90C60UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC1         *((volatile unsigned int*)(0x42C90C64UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC2         *((volatile unsigned int*)(0x42C90C68UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC3         *((volatile unsigned int*)(0x42C90C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC4         *((volatile unsigned int*)(0x42C90C70UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC5         *((volatile unsigned int*)(0x42C90C74UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_SA           *((volatile unsigned int*)(0x42C90C78UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_AE           *((volatile unsigned int*)(0x42C90C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A0           *((volatile unsigned int*)(0x42C90C80UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A1           *((volatile unsigned int*)(0x42C90C84UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A2           *((volatile unsigned int*)(0x42C90C88UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A3           *((volatile unsigned int*)(0x42C90C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A4           *((volatile unsigned int*)(0x42C90C90UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A5           *((volatile unsigned int*)(0x42C90C94UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A6           *((volatile unsigned int*)(0x42C90C98UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A7           *((volatile unsigned int*)(0x42C90C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A8           *((volatile unsigned int*)(0x42C90CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A9           *((volatile unsigned int*)(0x42C90CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A10          *((volatile unsigned int*)(0x42C90CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A11          *((volatile unsigned int*)(0x42C90CACUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A12          *((volatile unsigned int*)(0x42C90CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A13          *((volatile unsigned int*)(0x42C90CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A14          *((volatile unsigned int*)(0x42C90CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A15          *((volatile unsigned int*)(0x42C90CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A16          *((volatile unsigned int*)(0x42C90CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A17          *((volatile unsigned int*)(0x42C90CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A18          *((volatile unsigned int*)(0x42C90CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A19          *((volatile unsigned int*)(0x42C90CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A20          *((volatile unsigned int*)(0x42C90CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A21          *((volatile unsigned int*)(0x42C90CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A22          *((volatile unsigned int*)(0x42C90CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A23          *((volatile unsigned int*)(0x42C90CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A24          *((volatile unsigned int*)(0x42C90CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A25          *((volatile unsigned int*)(0x42C90CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A26          *((volatile unsigned int*)(0x42C90CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A27          *((volatile unsigned int*)(0x42C90CECUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A28          *((volatile unsigned int*)(0x42C90CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A29          *((volatile unsigned int*)(0x42C90CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A30          *((volatile unsigned int*)(0x42C90CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A31          *((volatile unsigned int*)(0x42C90CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A32          *((volatile unsigned int*)(0x42C90D00UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A33          *((volatile unsigned int*)(0x42C90D04UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A34          *((volatile unsigned int*)(0x42C90D08UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A35          *((volatile unsigned int*)(0x42C90D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A36          *((volatile unsigned int*)(0x42C90D10UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A37          *((volatile unsigned int*)(0x42C90D14UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A38          *((volatile unsigned int*)(0x42C90D18UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A39          *((volatile unsigned int*)(0x42C90D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A40          *((volatile unsigned int*)(0x42C90D20UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A41          *((volatile unsigned int*)(0x42C90D24UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A42          *((volatile unsigned int*)(0x42C90D28UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A43          *((volatile unsigned int*)(0x42C90D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A44          *((volatile unsigned int*)(0x42C90D30UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A45          *((volatile unsigned int*)(0x42C90D34UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A46          *((volatile unsigned int*)(0x42C90D38UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A47          *((volatile unsigned int*)(0x42C90D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC0         *((volatile unsigned int*)(0x42C90D60UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC1         *((volatile unsigned int*)(0x42C90D64UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC2         *((volatile unsigned int*)(0x42C90D68UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC3         *((volatile unsigned int*)(0x42C90D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC4         *((volatile unsigned int*)(0x42C90D70UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC5         *((volatile unsigned int*)(0x42C90D74UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_SA           *((volatile unsigned int*)(0x42C90D78UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_AE           *((volatile unsigned int*)(0x42C90D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A0           *((volatile unsigned int*)(0x42C90D80UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A1           *((volatile unsigned int*)(0x42C90D84UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A2           *((volatile unsigned int*)(0x42C90D88UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A3           *((volatile unsigned int*)(0x42C90D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A4           *((volatile unsigned int*)(0x42C90D90UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A5           *((volatile unsigned int*)(0x42C90D94UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A6           *((volatile unsigned int*)(0x42C90D98UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A7           *((volatile unsigned int*)(0x42C90D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A8           *((volatile unsigned int*)(0x42C90DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A9           *((volatile unsigned int*)(0x42C90DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A10          *((volatile unsigned int*)(0x42C90DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A11          *((volatile unsigned int*)(0x42C90DACUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A12          *((volatile unsigned int*)(0x42C90DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A13          *((volatile unsigned int*)(0x42C90DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A14          *((volatile unsigned int*)(0x42C90DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A15          *((volatile unsigned int*)(0x42C90DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A16          *((volatile unsigned int*)(0x42C90DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A17          *((volatile unsigned int*)(0x42C90DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A18          *((volatile unsigned int*)(0x42C90DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A19          *((volatile unsigned int*)(0x42C90DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A20          *((volatile unsigned int*)(0x42C90DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A21          *((volatile unsigned int*)(0x42C90DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A22          *((volatile unsigned int*)(0x42C90DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A23          *((volatile unsigned int*)(0x42C90DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A24          *((volatile unsigned int*)(0x42C90DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A25          *((volatile unsigned int*)(0x42C90DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A26          *((volatile unsigned int*)(0x42C90DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A27          *((volatile unsigned int*)(0x42C90DECUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A28          *((volatile unsigned int*)(0x42C90DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A29          *((volatile unsigned int*)(0x42C90DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A30          *((volatile unsigned int*)(0x42C90DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A31          *((volatile unsigned int*)(0x42C90DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A32          *((volatile unsigned int*)(0x42C90E00UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A33          *((volatile unsigned int*)(0x42C90E04UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A34          *((volatile unsigned int*)(0x42C90E08UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A35          *((volatile unsigned int*)(0x42C90E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A36          *((volatile unsigned int*)(0x42C90E10UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A37          *((volatile unsigned int*)(0x42C90E14UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A38          *((volatile unsigned int*)(0x42C90E18UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A39          *((volatile unsigned int*)(0x42C90E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A40          *((volatile unsigned int*)(0x42C90E20UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A41          *((volatile unsigned int*)(0x42C90E24UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A42          *((volatile unsigned int*)(0x42C90E28UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A43          *((volatile unsigned int*)(0x42C90E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A44          *((volatile unsigned int*)(0x42C90E30UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A45          *((volatile unsigned int*)(0x42C90E34UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A46          *((volatile unsigned int*)(0x42C90E38UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A47          *((volatile unsigned int*)(0x42C90E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC0         *((volatile unsigned int*)(0x42C90E60UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC1         *((volatile unsigned int*)(0x42C90E64UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC2         *((volatile unsigned int*)(0x42C90E68UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC3         *((volatile unsigned int*)(0x42C90E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC4         *((volatile unsigned int*)(0x42C90E70UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC5         *((volatile unsigned int*)(0x42C90E74UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_SA           *((volatile unsigned int*)(0x42C90E78UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_AE           *((volatile unsigned int*)(0x42C90E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A0           *((volatile unsigned int*)(0x42C90E80UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A1           *((volatile unsigned int*)(0x42C90E84UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A2           *((volatile unsigned int*)(0x42C90E88UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A3           *((volatile unsigned int*)(0x42C90E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A4           *((volatile unsigned int*)(0x42C90E90UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A5           *((volatile unsigned int*)(0x42C90E94UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A6           *((volatile unsigned int*)(0x42C90E98UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A7           *((volatile unsigned int*)(0x42C90E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A8           *((volatile unsigned int*)(0x42C90EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A9           *((volatile unsigned int*)(0x42C90EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A10          *((volatile unsigned int*)(0x42C90EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A11          *((volatile unsigned int*)(0x42C90EACUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A12          *((volatile unsigned int*)(0x42C90EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A13          *((volatile unsigned int*)(0x42C90EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A14          *((volatile unsigned int*)(0x42C90EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A15          *((volatile unsigned int*)(0x42C90EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A16          *((volatile unsigned int*)(0x42C90EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A17          *((volatile unsigned int*)(0x42C90EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A18          *((volatile unsigned int*)(0x42C90EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A19          *((volatile unsigned int*)(0x42C90ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A20          *((volatile unsigned int*)(0x42C90ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A21          *((volatile unsigned int*)(0x42C90ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A22          *((volatile unsigned int*)(0x42C90ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A23          *((volatile unsigned int*)(0x42C90EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A24          *((volatile unsigned int*)(0x42C90EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A25          *((volatile unsigned int*)(0x42C90EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A26          *((volatile unsigned int*)(0x42C90EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A27          *((volatile unsigned int*)(0x42C90EECUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A28          *((volatile unsigned int*)(0x42C90EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A29          *((volatile unsigned int*)(0x42C90EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A30          *((volatile unsigned int*)(0x42C90EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A31          *((volatile unsigned int*)(0x42C90EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A32          *((volatile unsigned int*)(0x42C90F00UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A33          *((volatile unsigned int*)(0x42C90F04UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A34          *((volatile unsigned int*)(0x42C90F08UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A35          *((volatile unsigned int*)(0x42C90F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A36          *((volatile unsigned int*)(0x42C90F10UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A37          *((volatile unsigned int*)(0x42C90F14UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A38          *((volatile unsigned int*)(0x42C90F18UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A39          *((volatile unsigned int*)(0x42C90F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A40          *((volatile unsigned int*)(0x42C90F20UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A41          *((volatile unsigned int*)(0x42C90F24UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A42          *((volatile unsigned int*)(0x42C90F28UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A43          *((volatile unsigned int*)(0x42C90F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A44          *((volatile unsigned int*)(0x42C90F30UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A45          *((volatile unsigned int*)(0x42C90F34UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A46          *((volatile unsigned int*)(0x42C90F38UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A47          *((volatile unsigned int*)(0x42C90F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC0         *((volatile unsigned int*)(0x42C90F60UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC1         *((volatile unsigned int*)(0x42C90F64UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC2         *((volatile unsigned int*)(0x42C90F68UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC3         *((volatile unsigned int*)(0x42C90F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC4         *((volatile unsigned int*)(0x42C90F70UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC5         *((volatile unsigned int*)(0x42C90F74UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_SA           *((volatile unsigned int*)(0x42C90F78UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_AE           *((volatile unsigned int*)(0x42C90F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A0           *((volatile unsigned int*)(0x42C90F80UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A1           *((volatile unsigned int*)(0x42C90F84UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A2           *((volatile unsigned int*)(0x42C90F88UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A3           *((volatile unsigned int*)(0x42C90F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A4           *((volatile unsigned int*)(0x42C90F90UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A5           *((volatile unsigned int*)(0x42C90F94UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A6           *((volatile unsigned int*)(0x42C90F98UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A7           *((volatile unsigned int*)(0x42C90F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A8           *((volatile unsigned int*)(0x42C90FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A9           *((volatile unsigned int*)(0x42C90FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A10          *((volatile unsigned int*)(0x42C90FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A11          *((volatile unsigned int*)(0x42C90FACUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A12          *((volatile unsigned int*)(0x42C90FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A13          *((volatile unsigned int*)(0x42C90FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A14          *((volatile unsigned int*)(0x42C90FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A15          *((volatile unsigned int*)(0x42C90FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A16          *((volatile unsigned int*)(0x42C90FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A17          *((volatile unsigned int*)(0x42C90FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A18          *((volatile unsigned int*)(0x42C90FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A19          *((volatile unsigned int*)(0x42C90FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A20          *((volatile unsigned int*)(0x42C90FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A21          *((volatile unsigned int*)(0x42C90FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A22          *((volatile unsigned int*)(0x42C90FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A23          *((volatile unsigned int*)(0x42C90FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A24          *((volatile unsigned int*)(0x42C90FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A25          *((volatile unsigned int*)(0x42C90FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A26          *((volatile unsigned int*)(0x42C90FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A27          *((volatile unsigned int*)(0x42C90FECUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A28          *((volatile unsigned int*)(0x42C90FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A29          *((volatile unsigned int*)(0x42C90FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A30          *((volatile unsigned int*)(0x42C90FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A31          *((volatile unsigned int*)(0x42C90FFCUL))
+#define bFM3_ETHERNET_MAC0_BMR_SWR             *((volatile unsigned int*)(0x42CA0000UL))
+#define bFM3_ETHERNET_MAC0_BMR_DA              *((volatile unsigned int*)(0x42CA0004UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL0            *((volatile unsigned int*)(0x42CA0008UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL1            *((volatile unsigned int*)(0x42CA000CUL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL2            *((volatile unsigned int*)(0x42CA0010UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL3            *((volatile unsigned int*)(0x42CA0014UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL4            *((volatile unsigned int*)(0x42CA0018UL))
+#define bFM3_ETHERNET_MAC0_BMR_ATDS            *((volatile unsigned int*)(0x42CA001CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL0            *((volatile unsigned int*)(0x42CA0020UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL1            *((volatile unsigned int*)(0x42CA0024UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL2            *((volatile unsigned int*)(0x42CA0028UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL3            *((volatile unsigned int*)(0x42CA002CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL4            *((volatile unsigned int*)(0x42CA0030UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL5            *((volatile unsigned int*)(0x42CA0034UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR0             *((volatile unsigned int*)(0x42CA0038UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR1             *((volatile unsigned int*)(0x42CA003CUL))
+#define bFM3_ETHERNET_MAC0_BMR_FB              *((volatile unsigned int*)(0x42CA0040UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL0           *((volatile unsigned int*)(0x42CA0044UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL1           *((volatile unsigned int*)(0x42CA0048UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL2           *((volatile unsigned int*)(0x42CA004CUL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL3           *((volatile unsigned int*)(0x42CA0050UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL4           *((volatile unsigned int*)(0x42CA0054UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL5           *((volatile unsigned int*)(0x42CA0058UL))
+#define bFM3_ETHERNET_MAC0_BMR_USP             *((volatile unsigned int*)(0x42CA005CUL))
+#define bFM3_ETHERNET_MAC0_BMR_8XPBL           *((volatile unsigned int*)(0x42CA0060UL))
+#define bFM3_ETHERNET_MAC0_BMR_AAL             *((volatile unsigned int*)(0x42CA0064UL))
+#define bFM3_ETHERNET_MAC0_BMR_MB              *((volatile unsigned int*)(0x42CA0068UL))
+#define bFM3_ETHERNET_MAC0_BMR_TXPR            *((volatile unsigned int*)(0x42CA006CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD0           *((volatile unsigned int*)(0x42CA0080UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD1           *((volatile unsigned int*)(0x42CA0084UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD2           *((volatile unsigned int*)(0x42CA0088UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD3           *((volatile unsigned int*)(0x42CA008CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD4           *((volatile unsigned int*)(0x42CA0090UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD5           *((volatile unsigned int*)(0x42CA0094UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD6           *((volatile unsigned int*)(0x42CA0098UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD7           *((volatile unsigned int*)(0x42CA009CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD8           *((volatile unsigned int*)(0x42CA00A0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD9           *((volatile unsigned int*)(0x42CA00A4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD10          *((volatile unsigned int*)(0x42CA00A8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD11          *((volatile unsigned int*)(0x42CA00ACUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD12          *((volatile unsigned int*)(0x42CA00B0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD13          *((volatile unsigned int*)(0x42CA00B4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD14          *((volatile unsigned int*)(0x42CA00B8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD15          *((volatile unsigned int*)(0x42CA00BCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD16          *((volatile unsigned int*)(0x42CA00C0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD17          *((volatile unsigned int*)(0x42CA00C4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD18          *((volatile unsigned int*)(0x42CA00C8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD19          *((volatile unsigned int*)(0x42CA00CCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD20          *((volatile unsigned int*)(0x42CA00D0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD21          *((volatile unsigned int*)(0x42CA00D4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD22          *((volatile unsigned int*)(0x42CA00D8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD23          *((volatile unsigned int*)(0x42CA00DCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD24          *((volatile unsigned int*)(0x42CA00E0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD25          *((volatile unsigned int*)(0x42CA00E4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD26          *((volatile unsigned int*)(0x42CA00E8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD27          *((volatile unsigned int*)(0x42CA00ECUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD28          *((volatile unsigned int*)(0x42CA00F0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD29          *((volatile unsigned int*)(0x42CA00F4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD30          *((volatile unsigned int*)(0x42CA00F8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD31          *((volatile unsigned int*)(0x42CA00FCUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD0           *((volatile unsigned int*)(0x42CA0100UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD1           *((volatile unsigned int*)(0x42CA0104UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD2           *((volatile unsigned int*)(0x42CA0108UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD3           *((volatile unsigned int*)(0x42CA010CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD4           *((volatile unsigned int*)(0x42CA0110UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD5           *((volatile unsigned int*)(0x42CA0114UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD6           *((volatile unsigned int*)(0x42CA0118UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD7           *((volatile unsigned int*)(0x42CA011CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD8           *((volatile unsigned int*)(0x42CA0120UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD9           *((volatile unsigned int*)(0x42CA0124UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD10          *((volatile unsigned int*)(0x42CA0128UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD11          *((volatile unsigned int*)(0x42CA012CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD12          *((volatile unsigned int*)(0x42CA0130UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD13          *((volatile unsigned int*)(0x42CA0134UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD14          *((volatile unsigned int*)(0x42CA0138UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD15          *((volatile unsigned int*)(0x42CA013CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD16          *((volatile unsigned int*)(0x42CA0140UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD17          *((volatile unsigned int*)(0x42CA0144UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD18          *((volatile unsigned int*)(0x42CA0148UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD19          *((volatile unsigned int*)(0x42CA014CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD20          *((volatile unsigned int*)(0x42CA0150UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD21          *((volatile unsigned int*)(0x42CA0154UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD22          *((volatile unsigned int*)(0x42CA0158UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD23          *((volatile unsigned int*)(0x42CA015CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD24          *((volatile unsigned int*)(0x42CA0160UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD25          *((volatile unsigned int*)(0x42CA0164UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD26          *((volatile unsigned int*)(0x42CA0168UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD27          *((volatile unsigned int*)(0x42CA016CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD28          *((volatile unsigned int*)(0x42CA0170UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD29          *((volatile unsigned int*)(0x42CA0174UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD30          *((volatile unsigned int*)(0x42CA0178UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD31          *((volatile unsigned int*)(0x42CA017CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL2          *((volatile unsigned int*)(0x42CA0188UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL3          *((volatile unsigned int*)(0x42CA018CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL4          *((volatile unsigned int*)(0x42CA0190UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL5          *((volatile unsigned int*)(0x42CA0194UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL6          *((volatile unsigned int*)(0x42CA0198UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL7          *((volatile unsigned int*)(0x42CA019CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL8          *((volatile unsigned int*)(0x42CA01A0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL9          *((volatile unsigned int*)(0x42CA01A4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL10         *((volatile unsigned int*)(0x42CA01A8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL11         *((volatile unsigned int*)(0x42CA01ACUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL12         *((volatile unsigned int*)(0x42CA01B0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL13         *((volatile unsigned int*)(0x42CA01B4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL14         *((volatile unsigned int*)(0x42CA01B8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL15         *((volatile unsigned int*)(0x42CA01BCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL16         *((volatile unsigned int*)(0x42CA01C0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL17         *((volatile unsigned int*)(0x42CA01C4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL18         *((volatile unsigned int*)(0x42CA01C8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL19         *((volatile unsigned int*)(0x42CA01CCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL20         *((volatile unsigned int*)(0x42CA01D0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL21         *((volatile unsigned int*)(0x42CA01D4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL22         *((volatile unsigned int*)(0x42CA01D8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL23         *((volatile unsigned int*)(0x42CA01DCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL24         *((volatile unsigned int*)(0x42CA01E0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL25         *((volatile unsigned int*)(0x42CA01E4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL26         *((volatile unsigned int*)(0x42CA01E8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL27         *((volatile unsigned int*)(0x42CA01ECUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL28         *((volatile unsigned int*)(0x42CA01F0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL29         *((volatile unsigned int*)(0x42CA01F4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL30         *((volatile unsigned int*)(0x42CA01F8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL31         *((volatile unsigned int*)(0x42CA01FCUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL2          *((volatile unsigned int*)(0x42CA0208UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL3          *((volatile unsigned int*)(0x42CA020CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL4          *((volatile unsigned int*)(0x42CA0210UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL5          *((volatile unsigned int*)(0x42CA0214UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL6          *((volatile unsigned int*)(0x42CA0218UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL7          *((volatile unsigned int*)(0x42CA021CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL8          *((volatile unsigned int*)(0x42CA0220UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL9          *((volatile unsigned int*)(0x42CA0224UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL10         *((volatile unsigned int*)(0x42CA0228UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL11         *((volatile unsigned int*)(0x42CA022CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL12         *((volatile unsigned int*)(0x42CA0230UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL13         *((volatile unsigned int*)(0x42CA0234UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL14         *((volatile unsigned int*)(0x42CA0238UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL15         *((volatile unsigned int*)(0x42CA023CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL16         *((volatile unsigned int*)(0x42CA0240UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL17         *((volatile unsigned int*)(0x42CA0244UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL18         *((volatile unsigned int*)(0x42CA0248UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL19         *((volatile unsigned int*)(0x42CA024CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL20         *((volatile unsigned int*)(0x42CA0250UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL21         *((volatile unsigned int*)(0x42CA0254UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL22         *((volatile unsigned int*)(0x42CA0258UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL23         *((volatile unsigned int*)(0x42CA025CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL24         *((volatile unsigned int*)(0x42CA0260UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL25         *((volatile unsigned int*)(0x42CA0264UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL26         *((volatile unsigned int*)(0x42CA0268UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL27         *((volatile unsigned int*)(0x42CA026CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL28         *((volatile unsigned int*)(0x42CA0270UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL29         *((volatile unsigned int*)(0x42CA0274UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL30         *((volatile unsigned int*)(0x42CA0278UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL31         *((volatile unsigned int*)(0x42CA027CUL))
+#define bFM3_ETHERNET_MAC0_SR_TI               *((volatile unsigned int*)(0x42CA0280UL))
+#define bFM3_ETHERNET_MAC0_SR_TPS              *((volatile unsigned int*)(0x42CA0284UL))
+#define bFM3_ETHERNET_MAC0_SR_TU               *((volatile unsigned int*)(0x42CA0288UL))
+#define bFM3_ETHERNET_MAC0_SR_TJT              *((volatile unsigned int*)(0x42CA028CUL))
+#define bFM3_ETHERNET_MAC0_SR_OVF              *((volatile unsigned int*)(0x42CA0290UL))
+#define bFM3_ETHERNET_MAC0_SR_UNF              *((volatile unsigned int*)(0x42CA0294UL))
+#define bFM3_ETHERNET_MAC0_SR_RI               *((volatile unsigned int*)(0x42CA0298UL))
+#define bFM3_ETHERNET_MAC0_SR_RU               *((volatile unsigned int*)(0x42CA029CUL))
+#define bFM3_ETHERNET_MAC0_SR_RPS              *((volatile unsigned int*)(0x42CA02A0UL))
+#define bFM3_ETHERNET_MAC0_SR_RWT              *((volatile unsigned int*)(0x42CA02A4UL))
+#define bFM3_ETHERNET_MAC0_SR_ETI              *((volatile unsigned int*)(0x42CA02A8UL))
+#define bFM3_ETHERNET_MAC0_SR_FBI              *((volatile unsigned int*)(0x42CA02B4UL))
+#define bFM3_ETHERNET_MAC0_SR_ERI              *((volatile unsigned int*)(0x42CA02B8UL))
+#define bFM3_ETHERNET_MAC0_SR_AIS              *((volatile unsigned int*)(0x42CA02BCUL))
+#define bFM3_ETHERNET_MAC0_SR_NIS              *((volatile unsigned int*)(0x42CA02C0UL))
+#define bFM3_ETHERNET_MAC0_SR_RS0              *((volatile unsigned int*)(0x42CA02C4UL))
+#define bFM3_ETHERNET_MAC0_SR_RS1              *((volatile unsigned int*)(0x42CA02C8UL))
+#define bFM3_ETHERNET_MAC0_SR_RS2              *((volatile unsigned int*)(0x42CA02CCUL))
+#define bFM3_ETHERNET_MAC0_SR_TS0              *((volatile unsigned int*)(0x42CA02D0UL))
+#define bFM3_ETHERNET_MAC0_SR_TS1              *((volatile unsigned int*)(0x42CA02D4UL))
+#define bFM3_ETHERNET_MAC0_SR_TS2              *((volatile unsigned int*)(0x42CA02D8UL))
+#define bFM3_ETHERNET_MAC0_SR_EB0              *((volatile unsigned int*)(0x42CA02DCUL))
+#define bFM3_ETHERNET_MAC0_SR_EB1              *((volatile unsigned int*)(0x42CA02E0UL))
+#define bFM3_ETHERNET_MAC0_SR_EB2              *((volatile unsigned int*)(0x42CA02E4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLI              *((volatile unsigned int*)(0x42CA02E8UL))
+#define bFM3_ETHERNET_MAC0_SR_GMI              *((volatile unsigned int*)(0x42CA02ECUL))
+#define bFM3_ETHERNET_MAC0_SR_GPI              *((volatile unsigned int*)(0x42CA02F0UL))
+#define bFM3_ETHERNET_MAC0_SR_TTI              *((volatile unsigned int*)(0x42CA02F4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLPII            *((volatile unsigned int*)(0x42CA02F8UL))
+#define bFM3_ETHERNET_MAC0_OMR_SR              *((volatile unsigned int*)(0x42CA0304UL))
+#define bFM3_ETHERNET_MAC0_OMR_OSF             *((volatile unsigned int*)(0x42CA0308UL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC0            *((volatile unsigned int*)(0x42CA030CUL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC1            *((volatile unsigned int*)(0x42CA0310UL))
+#define bFM3_ETHERNET_MAC0_OMR_FUF             *((volatile unsigned int*)(0x42CA0318UL))
+#define bFM3_ETHERNET_MAC0_OMR_FEF             *((volatile unsigned int*)(0x42CA031CUL))
+#define bFM3_ETHERNET_MAC0_OMR_ST              *((volatile unsigned int*)(0x42CA0334UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC0            *((volatile unsigned int*)(0x42CA0338UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC1            *((volatile unsigned int*)(0x42CA033CUL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC2            *((volatile unsigned int*)(0x42CA0340UL))
+#define bFM3_ETHERNET_MAC0_OMR_FTF             *((volatile unsigned int*)(0x42CA0350UL))
+#define bFM3_ETHERNET_MAC0_OMR_TSF             *((volatile unsigned int*)(0x42CA0354UL))
+#define bFM3_ETHERNET_MAC0_OMR_DFF             *((volatile unsigned int*)(0x42CA0360UL))
+#define bFM3_ETHERNET_MAC0_OMR_RSF             *((volatile unsigned int*)(0x42CA0364UL))
+#define bFM3_ETHERNET_MAC0_OMR_DT              *((volatile unsigned int*)(0x42CA0368UL))
+#define bFM3_ETHERNET_MAC0_IER_TIE             *((volatile unsigned int*)(0x42CA0380UL))
+#define bFM3_ETHERNET_MAC0_IER_TSE             *((volatile unsigned int*)(0x42CA0384UL))
+#define bFM3_ETHERNET_MAC0_IER_TUE             *((volatile unsigned int*)(0x42CA0388UL))
+#define bFM3_ETHERNET_MAC0_IER_TJE             *((volatile unsigned int*)(0x42CA038CUL))
+#define bFM3_ETHERNET_MAC0_IER_OVE             *((volatile unsigned int*)(0x42CA0390UL))
+#define bFM3_ETHERNET_MAC0_IER_UNE             *((volatile unsigned int*)(0x42CA0394UL))
+#define bFM3_ETHERNET_MAC0_IER_RIE             *((volatile unsigned int*)(0x42CA0398UL))
+#define bFM3_ETHERNET_MAC0_IER_RUE             *((volatile unsigned int*)(0x42CA039CUL))
+#define bFM3_ETHERNET_MAC0_IER_RSE             *((volatile unsigned int*)(0x42CA03A0UL))
+#define bFM3_ETHERNET_MAC0_IER_RWE             *((volatile unsigned int*)(0x42CA03A4UL))
+#define bFM3_ETHERNET_MAC0_IER_ETE             *((volatile unsigned int*)(0x42CA03A8UL))
+#define bFM3_ETHERNET_MAC0_IER_FBE             *((volatile unsigned int*)(0x42CA03B4UL))
+#define bFM3_ETHERNET_MAC0_IER_ERE             *((volatile unsigned int*)(0x42CA03B8UL))
+#define bFM3_ETHERNET_MAC0_IER_AIE             *((volatile unsigned int*)(0x42CA03BCUL))
+#define bFM3_ETHERNET_MAC0_IER_NIE             *((volatile unsigned int*)(0x42CA03C0UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42CA0400UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42CA0404UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42CA0408UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42CA040CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42CA0410UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42CA0414UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42CA0418UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42CA041CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42CA0420UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42CA0424UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42CA0428UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42CA042CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42CA0430UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42CA0434UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42CA0438UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42CA043CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42CA0440UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42CA0444UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42CA0448UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42CA044CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42CA0450UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42CA0454UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42CA0458UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42CA045CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42CA0460UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42CA0464UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42CA0468UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42CA046CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42CA0470UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0         *((volatile unsigned int*)(0x42CA0480UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1         *((volatile unsigned int*)(0x42CA0484UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2         *((volatile unsigned int*)(0x42CA0488UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3         *((volatile unsigned int*)(0x42CA048CUL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4         *((volatile unsigned int*)(0x42CA0490UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5         *((volatile unsigned int*)(0x42CA0494UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6         *((volatile unsigned int*)(0x42CA0498UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7         *((volatile unsigned int*)(0x42CA049CUL))
+#define bFM3_ETHERNET_MAC0_AHBSR_AHBS          *((volatile unsigned int*)(0x42CA0580UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42CA0900UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42CA0904UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42CA0908UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42CA090CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42CA0910UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42CA0914UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42CA0918UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42CA091CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42CA0920UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42CA0924UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42CA0928UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42CA092CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42CA0930UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42CA0934UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42CA0938UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42CA093CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42CA0940UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42CA0944UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42CA0948UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42CA094CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42CA0950UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42CA0954UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42CA0958UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42CA095CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42CA0960UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42CA0964UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42CA0968UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42CA096CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42CA0970UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42CA0974UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42CA0978UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42CA097CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42CA0980UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42CA0984UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42CA0988UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42CA098CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42CA0990UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42CA0994UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42CA0998UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42CA099CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42CA09A0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42CA09A4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42CA09A8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42CA09ACUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42CA09B0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42CA09B4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42CA09B8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42CA09BCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42CA09C0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42CA09C4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42CA09C8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42CA09CCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42CA09D0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42CA09D4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42CA09D8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42CA09DCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42CA09E0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42CA09E4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42CA09E8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42CA09ECUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42CA09F0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42CA09F4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42CA09F8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42CA09FCUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42CA0A00UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42CA0A04UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42CA0A08UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42CA0A0CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42CA0A10UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42CA0A14UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42CA0A18UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42CA0A1CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42CA0A20UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42CA0A24UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42CA0A28UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42CA0A2CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42CA0A30UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42CA0A34UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42CA0A38UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42CA0A3CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42CA0A40UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42CA0A44UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42CA0A48UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42CA0A4CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42CA0A50UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42CA0A54UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42CA0A58UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42CA0A5CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42CA0A60UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42CA0A64UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42CA0A68UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42CA0A6CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42CA0A70UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42CA0A74UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42CA0A78UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42CA0A7CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42CA0A80UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42CA0A84UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42CA0A88UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42CA0A8CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42CA0A90UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42CA0A94UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42CA0A98UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42CA0A9CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42CA0AA0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42CA0AA4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42CA0AA8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42CA0AACUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42CA0AB0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42CA0AB4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42CA0AB8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42CA0ABCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42CA0AC0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42CA0AC4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42CA0AC8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42CA0ACCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42CA0AD0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42CA0AD4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42CA0AD8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42CA0ADCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42CA0AE0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42CA0AE4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42CA0AE8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42CA0AECUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42CA0AF0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42CA0AF4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42CA0AF8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42CA0AFCUL))
+
+/* ETHERNET-MAC-CONTROL registers */
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE  *((volatile unsigned int*)(0x42CC0000UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0    *((volatile unsigned int*)(0x42CC0020UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1    *((volatile unsigned int*)(0x42CC0024UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL  *((volatile unsigned int*)(0x42CC0070UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0  *((volatile unsigned int*)(0x42CC0100UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1  *((volatile unsigned int*)(0x42CC0104UL))
+
+/* ETHERNET-MAC1 registers*/
+#define bFM3_ETHERNET_MAC1_MCR_RE              *((volatile unsigned int*)(0x42CE0008UL))
+#define bFM3_ETHERNET_MAC1_MCR_TE              *((volatile unsigned int*)(0x42CE000CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DC              *((volatile unsigned int*)(0x42CE0010UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL0             *((volatile unsigned int*)(0x42CE0014UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL1             *((volatile unsigned int*)(0x42CE0018UL))
+#define bFM3_ETHERNET_MAC1_MCR_ACS             *((volatile unsigned int*)(0x42CE001CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LUD             *((volatile unsigned int*)(0x42CE0020UL))
+#define bFM3_ETHERNET_MAC1_MCR_DR              *((volatile unsigned int*)(0x42CE0024UL))
+#define bFM3_ETHERNET_MAC1_MCR_IPC             *((volatile unsigned int*)(0x42CE0028UL))
+#define bFM3_ETHERNET_MAC1_MCR_DM              *((volatile unsigned int*)(0x42CE002CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LM              *((volatile unsigned int*)(0x42CE0030UL))
+#define bFM3_ETHERNET_MAC1_MCR_DO              *((volatile unsigned int*)(0x42CE0034UL))
+#define bFM3_ETHERNET_MAC1_MCR_FES             *((volatile unsigned int*)(0x42CE0038UL))
+#define bFM3_ETHERNET_MAC1_MCR_PS              *((volatile unsigned int*)(0x42CE003CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DCRS            *((volatile unsigned int*)(0x42CE0040UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG0            *((volatile unsigned int*)(0x42CE0044UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG1            *((volatile unsigned int*)(0x42CE0048UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG2            *((volatile unsigned int*)(0x42CE004CUL))
+#define bFM3_ETHERNET_MAC1_MCR_JE              *((volatile unsigned int*)(0x42CE0050UL))
+#define bFM3_ETHERNET_MAC1_MCR_BE              *((volatile unsigned int*)(0x42CE0054UL))
+#define bFM3_ETHERNET_MAC1_MCR_JD              *((volatile unsigned int*)(0x42CE0058UL))
+#define bFM3_ETHERNET_MAC1_MCR_WD              *((volatile unsigned int*)(0x42CE005CUL))
+#define bFM3_ETHERNET_MAC1_MCR_TC              *((volatile unsigned int*)(0x42CE0060UL))
+#define bFM3_ETHERNET_MAC1_MCR_CST             *((volatile unsigned int*)(0x42CE0064UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PR             *((volatile unsigned int*)(0x42CE0080UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HUC            *((volatile unsigned int*)(0x42CE0084UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HMC            *((volatile unsigned int*)(0x42CE0088UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DAIF           *((volatile unsigned int*)(0x42CE008CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_PM             *((volatile unsigned int*)(0x42CE0090UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DB             *((volatile unsigned int*)(0x42CE0094UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF0           *((volatile unsigned int*)(0x42CE0098UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF1           *((volatile unsigned int*)(0x42CE009CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAIF           *((volatile unsigned int*)(0x42CE00A0UL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAF            *((volatile unsigned int*)(0x42CE00A4UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HPF            *((volatile unsigned int*)(0x42CE00A8UL))
+#define bFM3_ETHERNET_MAC1_MFFR_RA             *((volatile unsigned int*)(0x42CE00FCUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH0          *((volatile unsigned int*)(0x42CE0100UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH1          *((volatile unsigned int*)(0x42CE0104UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH2          *((volatile unsigned int*)(0x42CE0108UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH3          *((volatile unsigned int*)(0x42CE010CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH4          *((volatile unsigned int*)(0x42CE0110UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH5          *((volatile unsigned int*)(0x42CE0114UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH6          *((volatile unsigned int*)(0x42CE0118UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH7          *((volatile unsigned int*)(0x42CE011CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH8          *((volatile unsigned int*)(0x42CE0120UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH9          *((volatile unsigned int*)(0x42CE0124UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH10         *((volatile unsigned int*)(0x42CE0128UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH11         *((volatile unsigned int*)(0x42CE012CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH12         *((volatile unsigned int*)(0x42CE0130UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH13         *((volatile unsigned int*)(0x42CE0134UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH14         *((volatile unsigned int*)(0x42CE0138UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH15         *((volatile unsigned int*)(0x42CE013CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH16         *((volatile unsigned int*)(0x42CE0140UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH17         *((volatile unsigned int*)(0x42CE0144UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH18         *((volatile unsigned int*)(0x42CE0148UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH19         *((volatile unsigned int*)(0x42CE014CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH20         *((volatile unsigned int*)(0x42CE0150UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH21         *((volatile unsigned int*)(0x42CE0154UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH22         *((volatile unsigned int*)(0x42CE0158UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH23         *((volatile unsigned int*)(0x42CE015CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH24         *((volatile unsigned int*)(0x42CE0160UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH25         *((volatile unsigned int*)(0x42CE0164UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH26         *((volatile unsigned int*)(0x42CE0168UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH27         *((volatile unsigned int*)(0x42CE016CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH28         *((volatile unsigned int*)(0x42CE0170UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH29         *((volatile unsigned int*)(0x42CE0174UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH30         *((volatile unsigned int*)(0x42CE0178UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH31         *((volatile unsigned int*)(0x42CE017CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL0          *((volatile unsigned int*)(0x42CE0180UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL1          *((volatile unsigned int*)(0x42CE0184UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL2          *((volatile unsigned int*)(0x42CE0188UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL3          *((volatile unsigned int*)(0x42CE018CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL4          *((volatile unsigned int*)(0x42CE0190UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL5          *((volatile unsigned int*)(0x42CE0194UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL6          *((volatile unsigned int*)(0x42CE0198UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL7          *((volatile unsigned int*)(0x42CE019CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL8          *((volatile unsigned int*)(0x42CE01A0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL9          *((volatile unsigned int*)(0x42CE01A4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL10         *((volatile unsigned int*)(0x42CE01A8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL11         *((volatile unsigned int*)(0x42CE01ACUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL12         *((volatile unsigned int*)(0x42CE01B0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL13         *((volatile unsigned int*)(0x42CE01B4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL14         *((volatile unsigned int*)(0x42CE01B8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL15         *((volatile unsigned int*)(0x42CE01BCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL16         *((volatile unsigned int*)(0x42CE01C0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL17         *((volatile unsigned int*)(0x42CE01C4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL18         *((volatile unsigned int*)(0x42CE01C8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL19         *((volatile unsigned int*)(0x42CE01CCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL20         *((volatile unsigned int*)(0x42CE01D0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL21         *((volatile unsigned int*)(0x42CE01D4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL22         *((volatile unsigned int*)(0x42CE01D8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL23         *((volatile unsigned int*)(0x42CE01DCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL24         *((volatile unsigned int*)(0x42CE01E0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL25         *((volatile unsigned int*)(0x42CE01E4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL26         *((volatile unsigned int*)(0x42CE01E8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL27         *((volatile unsigned int*)(0x42CE01ECUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL28         *((volatile unsigned int*)(0x42CE01F0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL29         *((volatile unsigned int*)(0x42CE01F4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL30         *((volatile unsigned int*)(0x42CE01F8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL31         *((volatile unsigned int*)(0x42CE01FCUL))
+#define bFM3_ETHERNET_MAC1_GAR_GB              *((volatile unsigned int*)(0x42CE0200UL))
+#define bFM3_ETHERNET_MAC1_GAR_GW              *((volatile unsigned int*)(0x42CE0204UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR0             *((volatile unsigned int*)(0x42CE0208UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR1             *((volatile unsigned int*)(0x42CE020CUL))
+#define bFM3_ETHERNET_MAC1_GAR_CR2             *((volatile unsigned int*)(0x42CE0210UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR3             *((volatile unsigned int*)(0x42CE0214UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR0             *((volatile unsigned int*)(0x42CE0218UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR1             *((volatile unsigned int*)(0x42CE021CUL))
+#define bFM3_ETHERNET_MAC1_GAR_GR2             *((volatile unsigned int*)(0x42CE0220UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR3             *((volatile unsigned int*)(0x42CE0224UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR4             *((volatile unsigned int*)(0x42CE0228UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA0             *((volatile unsigned int*)(0x42CE022CUL))
+#define bFM3_ETHERNET_MAC1_GAR_PA1             *((volatile unsigned int*)(0x42CE0230UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA2             *((volatile unsigned int*)(0x42CE0234UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA3             *((volatile unsigned int*)(0x42CE0238UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA4             *((volatile unsigned int*)(0x42CE023CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD0             *((volatile unsigned int*)(0x42CE0280UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD1             *((volatile unsigned int*)(0x42CE0284UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD2             *((volatile unsigned int*)(0x42CE0288UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD3             *((volatile unsigned int*)(0x42CE028CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD4             *((volatile unsigned int*)(0x42CE0290UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD5             *((volatile unsigned int*)(0x42CE0294UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD6             *((volatile unsigned int*)(0x42CE0298UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD7             *((volatile unsigned int*)(0x42CE029CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD8             *((volatile unsigned int*)(0x42CE02A0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD9             *((volatile unsigned int*)(0x42CE02A4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD10            *((volatile unsigned int*)(0x42CE02A8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD11            *((volatile unsigned int*)(0x42CE02ACUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD12            *((volatile unsigned int*)(0x42CE02B0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD13            *((volatile unsigned int*)(0x42CE02B4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD14            *((volatile unsigned int*)(0x42CE02B8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD15            *((volatile unsigned int*)(0x42CE02BCUL))
+#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA         *((volatile unsigned int*)(0x42CE0300UL))
+#define bFM3_ETHERNET_MAC1_FCR_TFE             *((volatile unsigned int*)(0x42CE0304UL))
+#define bFM3_ETHERNET_MAC1_FCR_RFE             *((volatile unsigned int*)(0x42CE0308UL))
+#define bFM3_ETHERNET_MAC1_FCR_UP              *((volatile unsigned int*)(0x42CE030CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT0            *((volatile unsigned int*)(0x42CE0310UL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT1            *((volatile unsigned int*)(0x42CE0314UL))
+#define bFM3_ETHERNET_MAC1_FCR_DZPQ            *((volatile unsigned int*)(0x42CE031CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT0             *((volatile unsigned int*)(0x42CE0340UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT1             *((volatile unsigned int*)(0x42CE0344UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT2             *((volatile unsigned int*)(0x42CE0348UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT3             *((volatile unsigned int*)(0x42CE034CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT4             *((volatile unsigned int*)(0x42CE0350UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT5             *((volatile unsigned int*)(0x42CE0354UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT6             *((volatile unsigned int*)(0x42CE0358UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT7             *((volatile unsigned int*)(0x42CE035CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT8             *((volatile unsigned int*)(0x42CE0360UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT9             *((volatile unsigned int*)(0x42CE0364UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT10            *((volatile unsigned int*)(0x42CE0368UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT11            *((volatile unsigned int*)(0x42CE036CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT12            *((volatile unsigned int*)(0x42CE0370UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT13            *((volatile unsigned int*)(0x42CE0374UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT14            *((volatile unsigned int*)(0x42CE0378UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT15            *((volatile unsigned int*)(0x42CE037CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL0             *((volatile unsigned int*)(0x42CE0380UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL1             *((volatile unsigned int*)(0x42CE0384UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL2             *((volatile unsigned int*)(0x42CE0388UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL3             *((volatile unsigned int*)(0x42CE038CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL4             *((volatile unsigned int*)(0x42CE0390UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL5             *((volatile unsigned int*)(0x42CE0394UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL6             *((volatile unsigned int*)(0x42CE0398UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL7             *((volatile unsigned int*)(0x42CE039CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL8             *((volatile unsigned int*)(0x42CE03A0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL9             *((volatile unsigned int*)(0x42CE03A4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL10            *((volatile unsigned int*)(0x42CE03A8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL11            *((volatile unsigned int*)(0x42CE03ACUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL12            *((volatile unsigned int*)(0x42CE03B0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL13            *((volatile unsigned int*)(0x42CE03B4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL14            *((volatile unsigned int*)(0x42CE03B8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL15            *((volatile unsigned int*)(0x42CE03BCUL))
+#define bFM3_ETHERNET_MAC1_VTR_ETV             *((volatile unsigned int*)(0x42CE03C0UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42CE0500UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42CE0504UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42CE0508UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42CE050CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42CE0510UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42CE0514UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42CE0518UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42CE051CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42CE0520UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42CE0524UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42CE0528UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42CE052CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42CE0530UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42CE0534UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42CE0538UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42CE053CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42CE0540UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42CE0544UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42CE0548UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42CE054CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42CE0550UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42CE0554UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42CE0558UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42CE055CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42CE0560UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42CE0564UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42CE0568UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42CE056CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42CE0570UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42CE0574UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42CE0578UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42CE057CUL))
+#define bFM3_ETHERNET_MAC1_PMTR_PD             *((volatile unsigned int*)(0x42CE0580UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPE            *((volatile unsigned int*)(0x42CE0584UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WFE            *((volatile unsigned int*)(0x42CE0588UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPR            *((volatile unsigned int*)(0x42CE0594UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WPR            *((volatile unsigned int*)(0x42CE0598UL))
+#define bFM3_ETHERNET_MAC1_PMTR_GU             *((volatile unsigned int*)(0x42CE05A4UL))
+#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42CE05FCUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42CE0600UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42CE0604UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42CE0608UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42CE060CUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST       *((volatile unsigned int*)(0x42CE0620UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST       *((volatile unsigned int*)(0x42CE0624UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN        *((volatile unsigned int*)(0x42CE0640UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLS          *((volatile unsigned int*)(0x42CE0644UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN        *((volatile unsigned int*)(0x42CE0648UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA       *((volatile unsigned int*)(0x42CE064CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT0         *((volatile unsigned int*)(0x42CE0680UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT1         *((volatile unsigned int*)(0x42CE0684UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT2         *((volatile unsigned int*)(0x42CE0688UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT3         *((volatile unsigned int*)(0x42CE068CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT4         *((volatile unsigned int*)(0x42CE0690UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT5         *((volatile unsigned int*)(0x42CE0694UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT6         *((volatile unsigned int*)(0x42CE0698UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT7         *((volatile unsigned int*)(0x42CE069CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT8         *((volatile unsigned int*)(0x42CE06A0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT9         *((volatile unsigned int*)(0x42CE06A4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT10        *((volatile unsigned int*)(0x42CE06A8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT11        *((volatile unsigned int*)(0x42CE06ACUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT12        *((volatile unsigned int*)(0x42CE06B0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT13        *((volatile unsigned int*)(0x42CE06B4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT14        *((volatile unsigned int*)(0x42CE06B8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT15        *((volatile unsigned int*)(0x42CE06BCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT0         *((volatile unsigned int*)(0x42CE06C0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT1         *((volatile unsigned int*)(0x42CE06C4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT2         *((volatile unsigned int*)(0x42CE06C8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT3         *((volatile unsigned int*)(0x42CE06CCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT4         *((volatile unsigned int*)(0x42CE06D0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT5         *((volatile unsigned int*)(0x42CE06D4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT6         *((volatile unsigned int*)(0x42CE06D8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT7         *((volatile unsigned int*)(0x42CE06DCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT8         *((volatile unsigned int*)(0x42CE06E0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT9         *((volatile unsigned int*)(0x42CE06E4UL))
+#define bFM3_ETHERNET_MAC1_ISR_RGIS            *((volatile unsigned int*)(0x42CE0700UL))
+#define bFM3_ETHERNET_MAC1_ISR_PIS             *((volatile unsigned int*)(0x42CE070CUL))
+#define bFM3_ETHERNET_MAC1_ISR_MIS             *((volatile unsigned int*)(0x42CE0710UL))
+#define bFM3_ETHERNET_MAC1_ISR_RIS             *((volatile unsigned int*)(0x42CE0714UL))
+#define bFM3_ETHERNET_MAC1_ISR_TIS             *((volatile unsigned int*)(0x42CE0718UL))
+#define bFM3_ETHERNET_MAC1_ISR_COIS            *((volatile unsigned int*)(0x42CE071CUL))
+#define bFM3_ETHERNET_MAC1_ISR_TSIS            *((volatile unsigned int*)(0x42CE0724UL))
+#define bFM3_ETHERNET_MAC1_ISR_LPIIS           *((volatile unsigned int*)(0x42CE0728UL))
+#define bFM3_ETHERNET_MAC1_IMR_RGIM            *((volatile unsigned int*)(0x42CE0780UL))
+#define bFM3_ETHERNET_MAC1_IMR_PIM             *((volatile unsigned int*)(0x42CE078CUL))
+#define bFM3_ETHERNET_MAC1_IMR_TSIM            *((volatile unsigned int*)(0x42CE0794UL))
+#define bFM3_ETHERNET_MAC1_IMR_LPIIM           *((volatile unsigned int*)(0x42CE0798UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A32           *((volatile unsigned int*)(0x42CE0800UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A33           *((volatile unsigned int*)(0x42CE0804UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A34           *((volatile unsigned int*)(0x42CE0808UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A35           *((volatile unsigned int*)(0x42CE080CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A36           *((volatile unsigned int*)(0x42CE0810UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A37           *((volatile unsigned int*)(0x42CE0814UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A38           *((volatile unsigned int*)(0x42CE0818UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A39           *((volatile unsigned int*)(0x42CE081CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A40           *((volatile unsigned int*)(0x42CE0820UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A41           *((volatile unsigned int*)(0x42CE0824UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A42           *((volatile unsigned int*)(0x42CE0828UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A43           *((volatile unsigned int*)(0x42CE082CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A44           *((volatile unsigned int*)(0x42CE0830UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A45           *((volatile unsigned int*)(0x42CE0834UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A46           *((volatile unsigned int*)(0x42CE0838UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A47           *((volatile unsigned int*)(0x42CE083CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_MO            *((volatile unsigned int*)(0x42CE087CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A0            *((volatile unsigned int*)(0x42CE0880UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A1            *((volatile unsigned int*)(0x42CE0884UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A2            *((volatile unsigned int*)(0x42CE0888UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A3            *((volatile unsigned int*)(0x42CE088CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A4            *((volatile unsigned int*)(0x42CE0890UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A5            *((volatile unsigned int*)(0x42CE0894UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A6            *((volatile unsigned int*)(0x42CE0898UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A7            *((volatile unsigned int*)(0x42CE089CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A8            *((volatile unsigned int*)(0x42CE08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A9            *((volatile unsigned int*)(0x42CE08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A10           *((volatile unsigned int*)(0x42CE08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A11           *((volatile unsigned int*)(0x42CE08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A12           *((volatile unsigned int*)(0x42CE08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A13           *((volatile unsigned int*)(0x42CE08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A14           *((volatile unsigned int*)(0x42CE08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A15           *((volatile unsigned int*)(0x42CE08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A16           *((volatile unsigned int*)(0x42CE08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A17           *((volatile unsigned int*)(0x42CE08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A18           *((volatile unsigned int*)(0x42CE08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A19           *((volatile unsigned int*)(0x42CE08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A20           *((volatile unsigned int*)(0x42CE08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A21           *((volatile unsigned int*)(0x42CE08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A22           *((volatile unsigned int*)(0x42CE08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A23           *((volatile unsigned int*)(0x42CE08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A24           *((volatile unsigned int*)(0x42CE08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A25           *((volatile unsigned int*)(0x42CE08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A26           *((volatile unsigned int*)(0x42CE08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A27           *((volatile unsigned int*)(0x42CE08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A28           *((volatile unsigned int*)(0x42CE08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A29           *((volatile unsigned int*)(0x42CE08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A30           *((volatile unsigned int*)(0x42CE08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A31           *((volatile unsigned int*)(0x42CE08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A32           *((volatile unsigned int*)(0x42CE0900UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A33           *((volatile unsigned int*)(0x42CE0904UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A34           *((volatile unsigned int*)(0x42CE0908UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A35           *((volatile unsigned int*)(0x42CE090CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A36           *((volatile unsigned int*)(0x42CE0910UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A37           *((volatile unsigned int*)(0x42CE0914UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A38           *((volatile unsigned int*)(0x42CE0918UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A39           *((volatile unsigned int*)(0x42CE091CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A40           *((volatile unsigned int*)(0x42CE0920UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A41           *((volatile unsigned int*)(0x42CE0924UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A42           *((volatile unsigned int*)(0x42CE0928UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A43           *((volatile unsigned int*)(0x42CE092CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A44           *((volatile unsigned int*)(0x42CE0930UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A45           *((volatile unsigned int*)(0x42CE0934UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A46           *((volatile unsigned int*)(0x42CE0938UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A47           *((volatile unsigned int*)(0x42CE093CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC0          *((volatile unsigned int*)(0x42CE0960UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC1          *((volatile unsigned int*)(0x42CE0964UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC2          *((volatile unsigned int*)(0x42CE0968UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC3          *((volatile unsigned int*)(0x42CE096CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC4          *((volatile unsigned int*)(0x42CE0970UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC5          *((volatile unsigned int*)(0x42CE0974UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_SA            *((volatile unsigned int*)(0x42CE0978UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_AE            *((volatile unsigned int*)(0x42CE097CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A0            *((volatile unsigned int*)(0x42CE0980UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A1            *((volatile unsigned int*)(0x42CE0984UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A2            *((volatile unsigned int*)(0x42CE0988UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A3            *((volatile unsigned int*)(0x42CE098CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A4            *((volatile unsigned int*)(0x42CE0990UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A5            *((volatile unsigned int*)(0x42CE0994UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A6            *((volatile unsigned int*)(0x42CE0998UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A7            *((volatile unsigned int*)(0x42CE099CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A8            *((volatile unsigned int*)(0x42CE09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A9            *((volatile unsigned int*)(0x42CE09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A10           *((volatile unsigned int*)(0x42CE09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A11           *((volatile unsigned int*)(0x42CE09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A12           *((volatile unsigned int*)(0x42CE09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A13           *((volatile unsigned int*)(0x42CE09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A14           *((volatile unsigned int*)(0x42CE09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A15           *((volatile unsigned int*)(0x42CE09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A16           *((volatile unsigned int*)(0x42CE09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A17           *((volatile unsigned int*)(0x42CE09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A18           *((volatile unsigned int*)(0x42CE09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A19           *((volatile unsigned int*)(0x42CE09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A20           *((volatile unsigned int*)(0x42CE09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A21           *((volatile unsigned int*)(0x42CE09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A22           *((volatile unsigned int*)(0x42CE09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A23           *((volatile unsigned int*)(0x42CE09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A24           *((volatile unsigned int*)(0x42CE09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A25           *((volatile unsigned int*)(0x42CE09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A26           *((volatile unsigned int*)(0x42CE09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A27           *((volatile unsigned int*)(0x42CE09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A28           *((volatile unsigned int*)(0x42CE09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A29           *((volatile unsigned int*)(0x42CE09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A30           *((volatile unsigned int*)(0x42CE09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A31           *((volatile unsigned int*)(0x42CE09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A32           *((volatile unsigned int*)(0x42CE0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A33           *((volatile unsigned int*)(0x42CE0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A34           *((volatile unsigned int*)(0x42CE0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A35           *((volatile unsigned int*)(0x42CE0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A36           *((volatile unsigned int*)(0x42CE0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A37           *((volatile unsigned int*)(0x42CE0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A38           *((volatile unsigned int*)(0x42CE0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A39           *((volatile unsigned int*)(0x42CE0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A40           *((volatile unsigned int*)(0x42CE0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A41           *((volatile unsigned int*)(0x42CE0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A42           *((volatile unsigned int*)(0x42CE0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A43           *((volatile unsigned int*)(0x42CE0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A44           *((volatile unsigned int*)(0x42CE0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A45           *((volatile unsigned int*)(0x42CE0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A46           *((volatile unsigned int*)(0x42CE0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A47           *((volatile unsigned int*)(0x42CE0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC0          *((volatile unsigned int*)(0x42CE0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC1          *((volatile unsigned int*)(0x42CE0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC2          *((volatile unsigned int*)(0x42CE0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC3          *((volatile unsigned int*)(0x42CE0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC4          *((volatile unsigned int*)(0x42CE0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC5          *((volatile unsigned int*)(0x42CE0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_SA            *((volatile unsigned int*)(0x42CE0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_AE            *((volatile unsigned int*)(0x42CE0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A0            *((volatile unsigned int*)(0x42CE0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A1            *((volatile unsigned int*)(0x42CE0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A2            *((volatile unsigned int*)(0x42CE0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A3            *((volatile unsigned int*)(0x42CE0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A4            *((volatile unsigned int*)(0x42CE0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A5            *((volatile unsigned int*)(0x42CE0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A6            *((volatile unsigned int*)(0x42CE0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A7            *((volatile unsigned int*)(0x42CE0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A8            *((volatile unsigned int*)(0x42CE0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A9            *((volatile unsigned int*)(0x42CE0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A10           *((volatile unsigned int*)(0x42CE0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A11           *((volatile unsigned int*)(0x42CE0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A12           *((volatile unsigned int*)(0x42CE0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A13           *((volatile unsigned int*)(0x42CE0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A14           *((volatile unsigned int*)(0x42CE0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A15           *((volatile unsigned int*)(0x42CE0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A16           *((volatile unsigned int*)(0x42CE0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A17           *((volatile unsigned int*)(0x42CE0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A18           *((volatile unsigned int*)(0x42CE0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A19           *((volatile unsigned int*)(0x42CE0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A20           *((volatile unsigned int*)(0x42CE0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A21           *((volatile unsigned int*)(0x42CE0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A22           *((volatile unsigned int*)(0x42CE0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A23           *((volatile unsigned int*)(0x42CE0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A24           *((volatile unsigned int*)(0x42CE0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A25           *((volatile unsigned int*)(0x42CE0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A26           *((volatile unsigned int*)(0x42CE0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A27           *((volatile unsigned int*)(0x42CE0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A28           *((volatile unsigned int*)(0x42CE0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A29           *((volatile unsigned int*)(0x42CE0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A30           *((volatile unsigned int*)(0x42CE0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A31           *((volatile unsigned int*)(0x42CE0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A32           *((volatile unsigned int*)(0x42CE0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A33           *((volatile unsigned int*)(0x42CE0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A34           *((volatile unsigned int*)(0x42CE0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A35           *((volatile unsigned int*)(0x42CE0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A36           *((volatile unsigned int*)(0x42CE0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A37           *((volatile unsigned int*)(0x42CE0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A38           *((volatile unsigned int*)(0x42CE0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A39           *((volatile unsigned int*)(0x42CE0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A40           *((volatile unsigned int*)(0x42CE0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A41           *((volatile unsigned int*)(0x42CE0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A42           *((volatile unsigned int*)(0x42CE0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A43           *((volatile unsigned int*)(0x42CE0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A44           *((volatile unsigned int*)(0x42CE0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A45           *((volatile unsigned int*)(0x42CE0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A46           *((volatile unsigned int*)(0x42CE0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A47           *((volatile unsigned int*)(0x42CE0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC0          *((volatile unsigned int*)(0x42CE0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC1          *((volatile unsigned int*)(0x42CE0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC2          *((volatile unsigned int*)(0x42CE0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC3          *((volatile unsigned int*)(0x42CE0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC4          *((volatile unsigned int*)(0x42CE0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC5          *((volatile unsigned int*)(0x42CE0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_SA            *((volatile unsigned int*)(0x42CE0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_AE            *((volatile unsigned int*)(0x42CE0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A0            *((volatile unsigned int*)(0x42CE0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A1            *((volatile unsigned int*)(0x42CE0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A2            *((volatile unsigned int*)(0x42CE0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A3            *((volatile unsigned int*)(0x42CE0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A4            *((volatile unsigned int*)(0x42CE0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A5            *((volatile unsigned int*)(0x42CE0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A6            *((volatile unsigned int*)(0x42CE0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A7            *((volatile unsigned int*)(0x42CE0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A8            *((volatile unsigned int*)(0x42CE0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A9            *((volatile unsigned int*)(0x42CE0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A10           *((volatile unsigned int*)(0x42CE0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A11           *((volatile unsigned int*)(0x42CE0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A12           *((volatile unsigned int*)(0x42CE0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A13           *((volatile unsigned int*)(0x42CE0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A14           *((volatile unsigned int*)(0x42CE0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A15           *((volatile unsigned int*)(0x42CE0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A16           *((volatile unsigned int*)(0x42CE0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A17           *((volatile unsigned int*)(0x42CE0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A18           *((volatile unsigned int*)(0x42CE0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A19           *((volatile unsigned int*)(0x42CE0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A20           *((volatile unsigned int*)(0x42CE0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A21           *((volatile unsigned int*)(0x42CE0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A22           *((volatile unsigned int*)(0x42CE0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A23           *((volatile unsigned int*)(0x42CE0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A24           *((volatile unsigned int*)(0x42CE0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A25           *((volatile unsigned int*)(0x42CE0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A26           *((volatile unsigned int*)(0x42CE0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A27           *((volatile unsigned int*)(0x42CE0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A28           *((volatile unsigned int*)(0x42CE0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A29           *((volatile unsigned int*)(0x42CE0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A30           *((volatile unsigned int*)(0x42CE0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A31           *((volatile unsigned int*)(0x42CE0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A32           *((volatile unsigned int*)(0x42CE0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A33           *((volatile unsigned int*)(0x42CE0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A34           *((volatile unsigned int*)(0x42CE0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A35           *((volatile unsigned int*)(0x42CE0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A36           *((volatile unsigned int*)(0x42CE0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A37           *((volatile unsigned int*)(0x42CE0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A38           *((volatile unsigned int*)(0x42CE0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A39           *((volatile unsigned int*)(0x42CE0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A40           *((volatile unsigned int*)(0x42CE0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A41           *((volatile unsigned int*)(0x42CE0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A42           *((volatile unsigned int*)(0x42CE0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A43           *((volatile unsigned int*)(0x42CE0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A44           *((volatile unsigned int*)(0x42CE0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A45           *((volatile unsigned int*)(0x42CE0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A46           *((volatile unsigned int*)(0x42CE0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A47           *((volatile unsigned int*)(0x42CE0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC0          *((volatile unsigned int*)(0x42CE0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC1          *((volatile unsigned int*)(0x42CE0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC2          *((volatile unsigned int*)(0x42CE0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC3          *((volatile unsigned int*)(0x42CE0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC4          *((volatile unsigned int*)(0x42CE0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC5          *((volatile unsigned int*)(0x42CE0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_SA            *((volatile unsigned int*)(0x42CE0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_AE            *((volatile unsigned int*)(0x42CE0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A0            *((volatile unsigned int*)(0x42CE0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A1            *((volatile unsigned int*)(0x42CE0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A2            *((volatile unsigned int*)(0x42CE0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A3            *((volatile unsigned int*)(0x42CE0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A4            *((volatile unsigned int*)(0x42CE0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A5            *((volatile unsigned int*)(0x42CE0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A6            *((volatile unsigned int*)(0x42CE0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A7            *((volatile unsigned int*)(0x42CE0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A8            *((volatile unsigned int*)(0x42CE0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A9            *((volatile unsigned int*)(0x42CE0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A10           *((volatile unsigned int*)(0x42CE0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A11           *((volatile unsigned int*)(0x42CE0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A12           *((volatile unsigned int*)(0x42CE0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A13           *((volatile unsigned int*)(0x42CE0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A14           *((volatile unsigned int*)(0x42CE0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A15           *((volatile unsigned int*)(0x42CE0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A16           *((volatile unsigned int*)(0x42CE0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A17           *((volatile unsigned int*)(0x42CE0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A18           *((volatile unsigned int*)(0x42CE0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A19           *((volatile unsigned int*)(0x42CE0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A20           *((volatile unsigned int*)(0x42CE0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A21           *((volatile unsigned int*)(0x42CE0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A22           *((volatile unsigned int*)(0x42CE0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A23           *((volatile unsigned int*)(0x42CE0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A24           *((volatile unsigned int*)(0x42CE0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A25           *((volatile unsigned int*)(0x42CE0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A26           *((volatile unsigned int*)(0x42CE0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A27           *((volatile unsigned int*)(0x42CE0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A28           *((volatile unsigned int*)(0x42CE0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A29           *((volatile unsigned int*)(0x42CE0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A30           *((volatile unsigned int*)(0x42CE0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A31           *((volatile unsigned int*)(0x42CE0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A32           *((volatile unsigned int*)(0x42CE0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A33           *((volatile unsigned int*)(0x42CE0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A34           *((volatile unsigned int*)(0x42CE0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A35           *((volatile unsigned int*)(0x42CE0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A36           *((volatile unsigned int*)(0x42CE0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A37           *((volatile unsigned int*)(0x42CE0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A38           *((volatile unsigned int*)(0x42CE0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A39           *((volatile unsigned int*)(0x42CE0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A40           *((volatile unsigned int*)(0x42CE0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A41           *((volatile unsigned int*)(0x42CE0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A42           *((volatile unsigned int*)(0x42CE0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A43           *((volatile unsigned int*)(0x42CE0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A44           *((volatile unsigned int*)(0x42CE0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A45           *((volatile unsigned int*)(0x42CE0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A46           *((volatile unsigned int*)(0x42CE0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A47           *((volatile unsigned int*)(0x42CE0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC0          *((volatile unsigned int*)(0x42CE0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC1          *((volatile unsigned int*)(0x42CE0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC2          *((volatile unsigned int*)(0x42CE0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC3          *((volatile unsigned int*)(0x42CE0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC4          *((volatile unsigned int*)(0x42CE0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC5          *((volatile unsigned int*)(0x42CE0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_SA            *((volatile unsigned int*)(0x42CE0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_AE            *((volatile unsigned int*)(0x42CE0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A0            *((volatile unsigned int*)(0x42CE0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A1            *((volatile unsigned int*)(0x42CE0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A2            *((volatile unsigned int*)(0x42CE0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A3            *((volatile unsigned int*)(0x42CE0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A4            *((volatile unsigned int*)(0x42CE0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A5            *((volatile unsigned int*)(0x42CE0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A6            *((volatile unsigned int*)(0x42CE0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A7            *((volatile unsigned int*)(0x42CE0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A8            *((volatile unsigned int*)(0x42CE0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A9            *((volatile unsigned int*)(0x42CE0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A10           *((volatile unsigned int*)(0x42CE0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A11           *((volatile unsigned int*)(0x42CE0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A12           *((volatile unsigned int*)(0x42CE0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A13           *((volatile unsigned int*)(0x42CE0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A14           *((volatile unsigned int*)(0x42CE0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A15           *((volatile unsigned int*)(0x42CE0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A16           *((volatile unsigned int*)(0x42CE0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A17           *((volatile unsigned int*)(0x42CE0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A18           *((volatile unsigned int*)(0x42CE0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A19           *((volatile unsigned int*)(0x42CE0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A20           *((volatile unsigned int*)(0x42CE0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A21           *((volatile unsigned int*)(0x42CE0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A22           *((volatile unsigned int*)(0x42CE0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A23           *((volatile unsigned int*)(0x42CE0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A24           *((volatile unsigned int*)(0x42CE0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A25           *((volatile unsigned int*)(0x42CE0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A26           *((volatile unsigned int*)(0x42CE0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A27           *((volatile unsigned int*)(0x42CE0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A28           *((volatile unsigned int*)(0x42CE0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A29           *((volatile unsigned int*)(0x42CE0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A30           *((volatile unsigned int*)(0x42CE0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A31           *((volatile unsigned int*)(0x42CE0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A32           *((volatile unsigned int*)(0x42CE0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A33           *((volatile unsigned int*)(0x42CE0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A34           *((volatile unsigned int*)(0x42CE0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A35           *((volatile unsigned int*)(0x42CE0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A36           *((volatile unsigned int*)(0x42CE0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A37           *((volatile unsigned int*)(0x42CE0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A38           *((volatile unsigned int*)(0x42CE0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A39           *((volatile unsigned int*)(0x42CE0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A40           *((volatile unsigned int*)(0x42CE0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A41           *((volatile unsigned int*)(0x42CE0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A42           *((volatile unsigned int*)(0x42CE0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A43           *((volatile unsigned int*)(0x42CE0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A44           *((volatile unsigned int*)(0x42CE0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A45           *((volatile unsigned int*)(0x42CE0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A46           *((volatile unsigned int*)(0x42CE0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A47           *((volatile unsigned int*)(0x42CE0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC0          *((volatile unsigned int*)(0x42CE0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC1          *((volatile unsigned int*)(0x42CE0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC2          *((volatile unsigned int*)(0x42CE0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC3          *((volatile unsigned int*)(0x42CE0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC4          *((volatile unsigned int*)(0x42CE0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC5          *((volatile unsigned int*)(0x42CE0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_SA            *((volatile unsigned int*)(0x42CE0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_AE            *((volatile unsigned int*)(0x42CE0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A0            *((volatile unsigned int*)(0x42CE0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A1            *((volatile unsigned int*)(0x42CE0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A2            *((volatile unsigned int*)(0x42CE0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A3            *((volatile unsigned int*)(0x42CE0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A4            *((volatile unsigned int*)(0x42CE0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A5            *((volatile unsigned int*)(0x42CE0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A6            *((volatile unsigned int*)(0x42CE0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A7            *((volatile unsigned int*)(0x42CE0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A8            *((volatile unsigned int*)(0x42CE0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A9            *((volatile unsigned int*)(0x42CE0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A10           *((volatile unsigned int*)(0x42CE0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A11           *((volatile unsigned int*)(0x42CE0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A12           *((volatile unsigned int*)(0x42CE0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A13           *((volatile unsigned int*)(0x42CE0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A14           *((volatile unsigned int*)(0x42CE0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A15           *((volatile unsigned int*)(0x42CE0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A16           *((volatile unsigned int*)(0x42CE0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A17           *((volatile unsigned int*)(0x42CE0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A18           *((volatile unsigned int*)(0x42CE0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A19           *((volatile unsigned int*)(0x42CE0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A20           *((volatile unsigned int*)(0x42CE0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A21           *((volatile unsigned int*)(0x42CE0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A22           *((volatile unsigned int*)(0x42CE0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A23           *((volatile unsigned int*)(0x42CE0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A24           *((volatile unsigned int*)(0x42CE0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A25           *((volatile unsigned int*)(0x42CE0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A26           *((volatile unsigned int*)(0x42CE0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A27           *((volatile unsigned int*)(0x42CE0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A28           *((volatile unsigned int*)(0x42CE0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A29           *((volatile unsigned int*)(0x42CE0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A30           *((volatile unsigned int*)(0x42CE0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A31           *((volatile unsigned int*)(0x42CE0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A32           *((volatile unsigned int*)(0x42CE0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A33           *((volatile unsigned int*)(0x42CE0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A34           *((volatile unsigned int*)(0x42CE0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A35           *((volatile unsigned int*)(0x42CE0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A36           *((volatile unsigned int*)(0x42CE0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A37           *((volatile unsigned int*)(0x42CE0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A38           *((volatile unsigned int*)(0x42CE0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A39           *((volatile unsigned int*)(0x42CE0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A40           *((volatile unsigned int*)(0x42CE0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A41           *((volatile unsigned int*)(0x42CE0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A42           *((volatile unsigned int*)(0x42CE0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A43           *((volatile unsigned int*)(0x42CE0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A44           *((volatile unsigned int*)(0x42CE0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A45           *((volatile unsigned int*)(0x42CE0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A46           *((volatile unsigned int*)(0x42CE0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A47           *((volatile unsigned int*)(0x42CE0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC0          *((volatile unsigned int*)(0x42CE0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC1          *((volatile unsigned int*)(0x42CE0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC2          *((volatile unsigned int*)(0x42CE0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC3          *((volatile unsigned int*)(0x42CE0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC4          *((volatile unsigned int*)(0x42CE0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC5          *((volatile unsigned int*)(0x42CE0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_SA            *((volatile unsigned int*)(0x42CE0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_AE            *((volatile unsigned int*)(0x42CE0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A0            *((volatile unsigned int*)(0x42CE0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A1            *((volatile unsigned int*)(0x42CE0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A2            *((volatile unsigned int*)(0x42CE0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A3            *((volatile unsigned int*)(0x42CE0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A4            *((volatile unsigned int*)(0x42CE0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A5            *((volatile unsigned int*)(0x42CE0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A6            *((volatile unsigned int*)(0x42CE0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A7            *((volatile unsigned int*)(0x42CE0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A8            *((volatile unsigned int*)(0x42CE0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A9            *((volatile unsigned int*)(0x42CE0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A10           *((volatile unsigned int*)(0x42CE0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A11           *((volatile unsigned int*)(0x42CE0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A12           *((volatile unsigned int*)(0x42CE0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A13           *((volatile unsigned int*)(0x42CE0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A14           *((volatile unsigned int*)(0x42CE0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A15           *((volatile unsigned int*)(0x42CE0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A16           *((volatile unsigned int*)(0x42CE0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A17           *((volatile unsigned int*)(0x42CE0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A18           *((volatile unsigned int*)(0x42CE0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A19           *((volatile unsigned int*)(0x42CE0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A20           *((volatile unsigned int*)(0x42CE0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A21           *((volatile unsigned int*)(0x42CE0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A22           *((volatile unsigned int*)(0x42CE0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A23           *((volatile unsigned int*)(0x42CE0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A24           *((volatile unsigned int*)(0x42CE0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A25           *((volatile unsigned int*)(0x42CE0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A26           *((volatile unsigned int*)(0x42CE0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A27           *((volatile unsigned int*)(0x42CE0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A28           *((volatile unsigned int*)(0x42CE0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A29           *((volatile unsigned int*)(0x42CE0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A30           *((volatile unsigned int*)(0x42CE0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A31           *((volatile unsigned int*)(0x42CE0FFCUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A32           *((volatile unsigned int*)(0x42CE1000UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A33           *((volatile unsigned int*)(0x42CE1004UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A34           *((volatile unsigned int*)(0x42CE1008UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A35           *((volatile unsigned int*)(0x42CE100CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A36           *((volatile unsigned int*)(0x42CE1010UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A37           *((volatile unsigned int*)(0x42CE1014UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A38           *((volatile unsigned int*)(0x42CE1018UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A39           *((volatile unsigned int*)(0x42CE101CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A40           *((volatile unsigned int*)(0x42CE1020UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A41           *((volatile unsigned int*)(0x42CE1024UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A42           *((volatile unsigned int*)(0x42CE1028UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A43           *((volatile unsigned int*)(0x42CE102CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A44           *((volatile unsigned int*)(0x42CE1030UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A45           *((volatile unsigned int*)(0x42CE1034UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A46           *((volatile unsigned int*)(0x42CE1038UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A47           *((volatile unsigned int*)(0x42CE103CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC0          *((volatile unsigned int*)(0x42CE1060UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC1          *((volatile unsigned int*)(0x42CE1064UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC2          *((volatile unsigned int*)(0x42CE1068UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC3          *((volatile unsigned int*)(0x42CE106CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC4          *((volatile unsigned int*)(0x42CE1070UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC5          *((volatile unsigned int*)(0x42CE1074UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_SA            *((volatile unsigned int*)(0x42CE1078UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_AE            *((volatile unsigned int*)(0x42CE107CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A0            *((volatile unsigned int*)(0x42CE1080UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A1            *((volatile unsigned int*)(0x42CE1084UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A2            *((volatile unsigned int*)(0x42CE1088UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A3            *((volatile unsigned int*)(0x42CE108CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A4            *((volatile unsigned int*)(0x42CE1090UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A5            *((volatile unsigned int*)(0x42CE1094UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A6            *((volatile unsigned int*)(0x42CE1098UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A7            *((volatile unsigned int*)(0x42CE109CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A8            *((volatile unsigned int*)(0x42CE10A0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A9            *((volatile unsigned int*)(0x42CE10A4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A10           *((volatile unsigned int*)(0x42CE10A8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A11           *((volatile unsigned int*)(0x42CE10ACUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A12           *((volatile unsigned int*)(0x42CE10B0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A13           *((volatile unsigned int*)(0x42CE10B4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A14           *((volatile unsigned int*)(0x42CE10B8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A15           *((volatile unsigned int*)(0x42CE10BCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A16           *((volatile unsigned int*)(0x42CE10C0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A17           *((volatile unsigned int*)(0x42CE10C4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A18           *((volatile unsigned int*)(0x42CE10C8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A19           *((volatile unsigned int*)(0x42CE10CCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A20           *((volatile unsigned int*)(0x42CE10D0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A21           *((volatile unsigned int*)(0x42CE10D4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A22           *((volatile unsigned int*)(0x42CE10D8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A23           *((volatile unsigned int*)(0x42CE10DCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A24           *((volatile unsigned int*)(0x42CE10E0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A25           *((volatile unsigned int*)(0x42CE10E4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A26           *((volatile unsigned int*)(0x42CE10E8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A27           *((volatile unsigned int*)(0x42CE10ECUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A28           *((volatile unsigned int*)(0x42CE10F0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A29           *((volatile unsigned int*)(0x42CE10F4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A30           *((volatile unsigned int*)(0x42CE10F8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A31           *((volatile unsigned int*)(0x42CE10FCUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A32           *((volatile unsigned int*)(0x42CE1100UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A33           *((volatile unsigned int*)(0x42CE1104UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A34           *((volatile unsigned int*)(0x42CE1108UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A35           *((volatile unsigned int*)(0x42CE110CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A36           *((volatile unsigned int*)(0x42CE1110UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A37           *((volatile unsigned int*)(0x42CE1114UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A38           *((volatile unsigned int*)(0x42CE1118UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A39           *((volatile unsigned int*)(0x42CE111CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A40           *((volatile unsigned int*)(0x42CE1120UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A41           *((volatile unsigned int*)(0x42CE1124UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A42           *((volatile unsigned int*)(0x42CE1128UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A43           *((volatile unsigned int*)(0x42CE112CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A44           *((volatile unsigned int*)(0x42CE1130UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A45           *((volatile unsigned int*)(0x42CE1134UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A46           *((volatile unsigned int*)(0x42CE1138UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A47           *((volatile unsigned int*)(0x42CE113CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC0          *((volatile unsigned int*)(0x42CE1160UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC1          *((volatile unsigned int*)(0x42CE1164UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC2          *((volatile unsigned int*)(0x42CE1168UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC3          *((volatile unsigned int*)(0x42CE116CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC4          *((volatile unsigned int*)(0x42CE1170UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC5          *((volatile unsigned int*)(0x42CE1174UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_SA            *((volatile unsigned int*)(0x42CE1178UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_AE            *((volatile unsigned int*)(0x42CE117CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A0            *((volatile unsigned int*)(0x42CE1180UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A1            *((volatile unsigned int*)(0x42CE1184UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A2            *((volatile unsigned int*)(0x42CE1188UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A3            *((volatile unsigned int*)(0x42CE118CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A4            *((volatile unsigned int*)(0x42CE1190UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A5            *((volatile unsigned int*)(0x42CE1194UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A6            *((volatile unsigned int*)(0x42CE1198UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A7            *((volatile unsigned int*)(0x42CE119CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A8            *((volatile unsigned int*)(0x42CE11A0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A9            *((volatile unsigned int*)(0x42CE11A4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A10           *((volatile unsigned int*)(0x42CE11A8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A11           *((volatile unsigned int*)(0x42CE11ACUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A12           *((volatile unsigned int*)(0x42CE11B0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A13           *((volatile unsigned int*)(0x42CE11B4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A14           *((volatile unsigned int*)(0x42CE11B8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A15           *((volatile unsigned int*)(0x42CE11BCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A16           *((volatile unsigned int*)(0x42CE11C0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A17           *((volatile unsigned int*)(0x42CE11C4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A18           *((volatile unsigned int*)(0x42CE11C8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A19           *((volatile unsigned int*)(0x42CE11CCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A20           *((volatile unsigned int*)(0x42CE11D0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A21           *((volatile unsigned int*)(0x42CE11D4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A22           *((volatile unsigned int*)(0x42CE11D8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A23           *((volatile unsigned int*)(0x42CE11DCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A24           *((volatile unsigned int*)(0x42CE11E0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A25           *((volatile unsigned int*)(0x42CE11E4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A26           *((volatile unsigned int*)(0x42CE11E8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A27           *((volatile unsigned int*)(0x42CE11ECUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A28           *((volatile unsigned int*)(0x42CE11F0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A29           *((volatile unsigned int*)(0x42CE11F4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A30           *((volatile unsigned int*)(0x42CE11F8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A31           *((volatile unsigned int*)(0x42CE11FCUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A32          *((volatile unsigned int*)(0x42CE1200UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A33          *((volatile unsigned int*)(0x42CE1204UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A34          *((volatile unsigned int*)(0x42CE1208UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A35          *((volatile unsigned int*)(0x42CE120CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A36          *((volatile unsigned int*)(0x42CE1210UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A37          *((volatile unsigned int*)(0x42CE1214UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A38          *((volatile unsigned int*)(0x42CE1218UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A39          *((volatile unsigned int*)(0x42CE121CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A40          *((volatile unsigned int*)(0x42CE1220UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A41          *((volatile unsigned int*)(0x42CE1224UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A42          *((volatile unsigned int*)(0x42CE1228UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A43          *((volatile unsigned int*)(0x42CE122CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A44          *((volatile unsigned int*)(0x42CE1230UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A45          *((volatile unsigned int*)(0x42CE1234UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A46          *((volatile unsigned int*)(0x42CE1238UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A47          *((volatile unsigned int*)(0x42CE123CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC0         *((volatile unsigned int*)(0x42CE1260UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC1         *((volatile unsigned int*)(0x42CE1264UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC2         *((volatile unsigned int*)(0x42CE1268UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC3         *((volatile unsigned int*)(0x42CE126CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC4         *((volatile unsigned int*)(0x42CE1270UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC5         *((volatile unsigned int*)(0x42CE1274UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_SA           *((volatile unsigned int*)(0x42CE1278UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_AE           *((volatile unsigned int*)(0x42CE127CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A0           *((volatile unsigned int*)(0x42CE1280UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A1           *((volatile unsigned int*)(0x42CE1284UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A2           *((volatile unsigned int*)(0x42CE1288UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A3           *((volatile unsigned int*)(0x42CE128CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A4           *((volatile unsigned int*)(0x42CE1290UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A5           *((volatile unsigned int*)(0x42CE1294UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A6           *((volatile unsigned int*)(0x42CE1298UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A7           *((volatile unsigned int*)(0x42CE129CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A8           *((volatile unsigned int*)(0x42CE12A0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A9           *((volatile unsigned int*)(0x42CE12A4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A10          *((volatile unsigned int*)(0x42CE12A8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A11          *((volatile unsigned int*)(0x42CE12ACUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A12          *((volatile unsigned int*)(0x42CE12B0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A13          *((volatile unsigned int*)(0x42CE12B4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A14          *((volatile unsigned int*)(0x42CE12B8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A15          *((volatile unsigned int*)(0x42CE12BCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A16          *((volatile unsigned int*)(0x42CE12C0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A17          *((volatile unsigned int*)(0x42CE12C4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A18          *((volatile unsigned int*)(0x42CE12C8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A19          *((volatile unsigned int*)(0x42CE12CCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A20          *((volatile unsigned int*)(0x42CE12D0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A21          *((volatile unsigned int*)(0x42CE12D4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A22          *((volatile unsigned int*)(0x42CE12D8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A23          *((volatile unsigned int*)(0x42CE12DCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A24          *((volatile unsigned int*)(0x42CE12E0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A25          *((volatile unsigned int*)(0x42CE12E4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A26          *((volatile unsigned int*)(0x42CE12E8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A27          *((volatile unsigned int*)(0x42CE12ECUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A28          *((volatile unsigned int*)(0x42CE12F0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A29          *((volatile unsigned int*)(0x42CE12F4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A30          *((volatile unsigned int*)(0x42CE12F8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A31          *((volatile unsigned int*)(0x42CE12FCUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A32          *((volatile unsigned int*)(0x42CE1300UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A33          *((volatile unsigned int*)(0x42CE1304UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A34          *((volatile unsigned int*)(0x42CE1308UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A35          *((volatile unsigned int*)(0x42CE130CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A36          *((volatile unsigned int*)(0x42CE1310UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A37          *((volatile unsigned int*)(0x42CE1314UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A38          *((volatile unsigned int*)(0x42CE1318UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A39          *((volatile unsigned int*)(0x42CE131CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A40          *((volatile unsigned int*)(0x42CE1320UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A41          *((volatile unsigned int*)(0x42CE1324UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A42          *((volatile unsigned int*)(0x42CE1328UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A43          *((volatile unsigned int*)(0x42CE132CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A44          *((volatile unsigned int*)(0x42CE1330UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A45          *((volatile unsigned int*)(0x42CE1334UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A46          *((volatile unsigned int*)(0x42CE1338UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A47          *((volatile unsigned int*)(0x42CE133CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC0         *((volatile unsigned int*)(0x42CE1360UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC1         *((volatile unsigned int*)(0x42CE1364UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC2         *((volatile unsigned int*)(0x42CE1368UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC3         *((volatile unsigned int*)(0x42CE136CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC4         *((volatile unsigned int*)(0x42CE1370UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC5         *((volatile unsigned int*)(0x42CE1374UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_SA           *((volatile unsigned int*)(0x42CE1378UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_AE           *((volatile unsigned int*)(0x42CE137CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A0           *((volatile unsigned int*)(0x42CE1380UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A1           *((volatile unsigned int*)(0x42CE1384UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A2           *((volatile unsigned int*)(0x42CE1388UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A3           *((volatile unsigned int*)(0x42CE138CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A4           *((volatile unsigned int*)(0x42CE1390UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A5           *((volatile unsigned int*)(0x42CE1394UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A6           *((volatile unsigned int*)(0x42CE1398UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A7           *((volatile unsigned int*)(0x42CE139CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A8           *((volatile unsigned int*)(0x42CE13A0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A9           *((volatile unsigned int*)(0x42CE13A4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A10          *((volatile unsigned int*)(0x42CE13A8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A11          *((volatile unsigned int*)(0x42CE13ACUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A12          *((volatile unsigned int*)(0x42CE13B0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A13          *((volatile unsigned int*)(0x42CE13B4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A14          *((volatile unsigned int*)(0x42CE13B8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A15          *((volatile unsigned int*)(0x42CE13BCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A16          *((volatile unsigned int*)(0x42CE13C0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A17          *((volatile unsigned int*)(0x42CE13C4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A18          *((volatile unsigned int*)(0x42CE13C8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A19          *((volatile unsigned int*)(0x42CE13CCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A20          *((volatile unsigned int*)(0x42CE13D0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A21          *((volatile unsigned int*)(0x42CE13D4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A22          *((volatile unsigned int*)(0x42CE13D8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A23          *((volatile unsigned int*)(0x42CE13DCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A24          *((volatile unsigned int*)(0x42CE13E0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A25          *((volatile unsigned int*)(0x42CE13E4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A26          *((volatile unsigned int*)(0x42CE13E8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A27          *((volatile unsigned int*)(0x42CE13ECUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A28          *((volatile unsigned int*)(0x42CE13F0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A29          *((volatile unsigned int*)(0x42CE13F4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A30          *((volatile unsigned int*)(0x42CE13F8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A31          *((volatile unsigned int*)(0x42CE13FCUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A32          *((volatile unsigned int*)(0x42CE1400UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A33          *((volatile unsigned int*)(0x42CE1404UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A34          *((volatile unsigned int*)(0x42CE1408UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A35          *((volatile unsigned int*)(0x42CE140CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A36          *((volatile unsigned int*)(0x42CE1410UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A37          *((volatile unsigned int*)(0x42CE1414UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A38          *((volatile unsigned int*)(0x42CE1418UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A39          *((volatile unsigned int*)(0x42CE141CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A40          *((volatile unsigned int*)(0x42CE1420UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A41          *((volatile unsigned int*)(0x42CE1424UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A42          *((volatile unsigned int*)(0x42CE1428UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A43          *((volatile unsigned int*)(0x42CE142CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A44          *((volatile unsigned int*)(0x42CE1430UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A45          *((volatile unsigned int*)(0x42CE1434UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A46          *((volatile unsigned int*)(0x42CE1438UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A47          *((volatile unsigned int*)(0x42CE143CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC0         *((volatile unsigned int*)(0x42CE1460UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC1         *((volatile unsigned int*)(0x42CE1464UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC2         *((volatile unsigned int*)(0x42CE1468UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC3         *((volatile unsigned int*)(0x42CE146CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC4         *((volatile unsigned int*)(0x42CE1470UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC5         *((volatile unsigned int*)(0x42CE1474UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_SA           *((volatile unsigned int*)(0x42CE1478UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_AE           *((volatile unsigned int*)(0x42CE147CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A0           *((volatile unsigned int*)(0x42CE1480UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A1           *((volatile unsigned int*)(0x42CE1484UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A2           *((volatile unsigned int*)(0x42CE1488UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A3           *((volatile unsigned int*)(0x42CE148CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A4           *((volatile unsigned int*)(0x42CE1490UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A5           *((volatile unsigned int*)(0x42CE1494UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A6           *((volatile unsigned int*)(0x42CE1498UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A7           *((volatile unsigned int*)(0x42CE149CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A8           *((volatile unsigned int*)(0x42CE14A0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A9           *((volatile unsigned int*)(0x42CE14A4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A10          *((volatile unsigned int*)(0x42CE14A8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A11          *((volatile unsigned int*)(0x42CE14ACUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A12          *((volatile unsigned int*)(0x42CE14B0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A13          *((volatile unsigned int*)(0x42CE14B4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A14          *((volatile unsigned int*)(0x42CE14B8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A15          *((volatile unsigned int*)(0x42CE14BCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A16          *((volatile unsigned int*)(0x42CE14C0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A17          *((volatile unsigned int*)(0x42CE14C4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A18          *((volatile unsigned int*)(0x42CE14C8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A19          *((volatile unsigned int*)(0x42CE14CCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A20          *((volatile unsigned int*)(0x42CE14D0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A21          *((volatile unsigned int*)(0x42CE14D4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A22          *((volatile unsigned int*)(0x42CE14D8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A23          *((volatile unsigned int*)(0x42CE14DCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A24          *((volatile unsigned int*)(0x42CE14E0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A25          *((volatile unsigned int*)(0x42CE14E4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A26          *((volatile unsigned int*)(0x42CE14E8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A27          *((volatile unsigned int*)(0x42CE14ECUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A28          *((volatile unsigned int*)(0x42CE14F0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A29          *((volatile unsigned int*)(0x42CE14F4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A30          *((volatile unsigned int*)(0x42CE14F8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A31          *((volatile unsigned int*)(0x42CE14FCUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A32          *((volatile unsigned int*)(0x42CE1500UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A33          *((volatile unsigned int*)(0x42CE1504UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A34          *((volatile unsigned int*)(0x42CE1508UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A35          *((volatile unsigned int*)(0x42CE150CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A36          *((volatile unsigned int*)(0x42CE1510UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A37          *((volatile unsigned int*)(0x42CE1514UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A38          *((volatile unsigned int*)(0x42CE1518UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A39          *((volatile unsigned int*)(0x42CE151CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A40          *((volatile unsigned int*)(0x42CE1520UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A41          *((volatile unsigned int*)(0x42CE1524UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A42          *((volatile unsigned int*)(0x42CE1528UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A43          *((volatile unsigned int*)(0x42CE152CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A44          *((volatile unsigned int*)(0x42CE1530UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A45          *((volatile unsigned int*)(0x42CE1534UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A46          *((volatile unsigned int*)(0x42CE1538UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A47          *((volatile unsigned int*)(0x42CE153CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC0         *((volatile unsigned int*)(0x42CE1560UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC1         *((volatile unsigned int*)(0x42CE1564UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC2         *((volatile unsigned int*)(0x42CE1568UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC3         *((volatile unsigned int*)(0x42CE156CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC4         *((volatile unsigned int*)(0x42CE1570UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC5         *((volatile unsigned int*)(0x42CE1574UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_SA           *((volatile unsigned int*)(0x42CE1578UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_AE           *((volatile unsigned int*)(0x42CE157CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A0           *((volatile unsigned int*)(0x42CE1580UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A1           *((volatile unsigned int*)(0x42CE1584UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A2           *((volatile unsigned int*)(0x42CE1588UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A3           *((volatile unsigned int*)(0x42CE158CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A4           *((volatile unsigned int*)(0x42CE1590UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A5           *((volatile unsigned int*)(0x42CE1594UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A6           *((volatile unsigned int*)(0x42CE1598UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A7           *((volatile unsigned int*)(0x42CE159CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A8           *((volatile unsigned int*)(0x42CE15A0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A9           *((volatile unsigned int*)(0x42CE15A4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A10          *((volatile unsigned int*)(0x42CE15A8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A11          *((volatile unsigned int*)(0x42CE15ACUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A12          *((volatile unsigned int*)(0x42CE15B0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A13          *((volatile unsigned int*)(0x42CE15B4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A14          *((volatile unsigned int*)(0x42CE15B8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A15          *((volatile unsigned int*)(0x42CE15BCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A16          *((volatile unsigned int*)(0x42CE15C0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A17          *((volatile unsigned int*)(0x42CE15C4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A18          *((volatile unsigned int*)(0x42CE15C8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A19          *((volatile unsigned int*)(0x42CE15CCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A20          *((volatile unsigned int*)(0x42CE15D0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A21          *((volatile unsigned int*)(0x42CE15D4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A22          *((volatile unsigned int*)(0x42CE15D8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A23          *((volatile unsigned int*)(0x42CE15DCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A24          *((volatile unsigned int*)(0x42CE15E0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A25          *((volatile unsigned int*)(0x42CE15E4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A26          *((volatile unsigned int*)(0x42CE15E8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A27          *((volatile unsigned int*)(0x42CE15ECUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A28          *((volatile unsigned int*)(0x42CE15F0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A29          *((volatile unsigned int*)(0x42CE15F4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A30          *((volatile unsigned int*)(0x42CE15F8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A31          *((volatile unsigned int*)(0x42CE15FCUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A32          *((volatile unsigned int*)(0x42CE1600UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A33          *((volatile unsigned int*)(0x42CE1604UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A34          *((volatile unsigned int*)(0x42CE1608UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A35          *((volatile unsigned int*)(0x42CE160CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A36          *((volatile unsigned int*)(0x42CE1610UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A37          *((volatile unsigned int*)(0x42CE1614UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A38          *((volatile unsigned int*)(0x42CE1618UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A39          *((volatile unsigned int*)(0x42CE161CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A40          *((volatile unsigned int*)(0x42CE1620UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A41          *((volatile unsigned int*)(0x42CE1624UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A42          *((volatile unsigned int*)(0x42CE1628UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A43          *((volatile unsigned int*)(0x42CE162CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A44          *((volatile unsigned int*)(0x42CE1630UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A45          *((volatile unsigned int*)(0x42CE1634UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A46          *((volatile unsigned int*)(0x42CE1638UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A47          *((volatile unsigned int*)(0x42CE163CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC0         *((volatile unsigned int*)(0x42CE1660UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC1         *((volatile unsigned int*)(0x42CE1664UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC2         *((volatile unsigned int*)(0x42CE1668UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC3         *((volatile unsigned int*)(0x42CE166CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC4         *((volatile unsigned int*)(0x42CE1670UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC5         *((volatile unsigned int*)(0x42CE1674UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_SA           *((volatile unsigned int*)(0x42CE1678UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_AE           *((volatile unsigned int*)(0x42CE167CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A0           *((volatile unsigned int*)(0x42CE1680UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A1           *((volatile unsigned int*)(0x42CE1684UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A2           *((volatile unsigned int*)(0x42CE1688UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A3           *((volatile unsigned int*)(0x42CE168CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A4           *((volatile unsigned int*)(0x42CE1690UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A5           *((volatile unsigned int*)(0x42CE1694UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A6           *((volatile unsigned int*)(0x42CE1698UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A7           *((volatile unsigned int*)(0x42CE169CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A8           *((volatile unsigned int*)(0x42CE16A0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A9           *((volatile unsigned int*)(0x42CE16A4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A10          *((volatile unsigned int*)(0x42CE16A8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A11          *((volatile unsigned int*)(0x42CE16ACUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A12          *((volatile unsigned int*)(0x42CE16B0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A13          *((volatile unsigned int*)(0x42CE16B4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A14          *((volatile unsigned int*)(0x42CE16B8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A15          *((volatile unsigned int*)(0x42CE16BCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A16          *((volatile unsigned int*)(0x42CE16C0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A17          *((volatile unsigned int*)(0x42CE16C4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A18          *((volatile unsigned int*)(0x42CE16C8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A19          *((volatile unsigned int*)(0x42CE16CCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A20          *((volatile unsigned int*)(0x42CE16D0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A21          *((volatile unsigned int*)(0x42CE16D4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A22          *((volatile unsigned int*)(0x42CE16D8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A23          *((volatile unsigned int*)(0x42CE16DCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A24          *((volatile unsigned int*)(0x42CE16E0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A25          *((volatile unsigned int*)(0x42CE16E4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A26          *((volatile unsigned int*)(0x42CE16E8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A27          *((volatile unsigned int*)(0x42CE16ECUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A28          *((volatile unsigned int*)(0x42CE16F0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A29          *((volatile unsigned int*)(0x42CE16F4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A30          *((volatile unsigned int*)(0x42CE16F8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A31          *((volatile unsigned int*)(0x42CE16FCUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A32          *((volatile unsigned int*)(0x42CE1700UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A33          *((volatile unsigned int*)(0x42CE1704UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A34          *((volatile unsigned int*)(0x42CE1708UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A35          *((volatile unsigned int*)(0x42CE170CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A36          *((volatile unsigned int*)(0x42CE1710UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A37          *((volatile unsigned int*)(0x42CE1714UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A38          *((volatile unsigned int*)(0x42CE1718UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A39          *((volatile unsigned int*)(0x42CE171CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A40          *((volatile unsigned int*)(0x42CE1720UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A41          *((volatile unsigned int*)(0x42CE1724UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A42          *((volatile unsigned int*)(0x42CE1728UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A43          *((volatile unsigned int*)(0x42CE172CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A44          *((volatile unsigned int*)(0x42CE1730UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A45          *((volatile unsigned int*)(0x42CE1734UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A46          *((volatile unsigned int*)(0x42CE1738UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A47          *((volatile unsigned int*)(0x42CE173CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC0         *((volatile unsigned int*)(0x42CE1760UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC1         *((volatile unsigned int*)(0x42CE1764UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC2         *((volatile unsigned int*)(0x42CE1768UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC3         *((volatile unsigned int*)(0x42CE176CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC4         *((volatile unsigned int*)(0x42CE1770UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC5         *((volatile unsigned int*)(0x42CE1774UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_SA           *((volatile unsigned int*)(0x42CE1778UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_AE           *((volatile unsigned int*)(0x42CE177CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A0           *((volatile unsigned int*)(0x42CE1780UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A1           *((volatile unsigned int*)(0x42CE1784UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A2           *((volatile unsigned int*)(0x42CE1788UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A3           *((volatile unsigned int*)(0x42CE178CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A4           *((volatile unsigned int*)(0x42CE1790UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A5           *((volatile unsigned int*)(0x42CE1794UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A6           *((volatile unsigned int*)(0x42CE1798UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A7           *((volatile unsigned int*)(0x42CE179CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A8           *((volatile unsigned int*)(0x42CE17A0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A9           *((volatile unsigned int*)(0x42CE17A4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A10          *((volatile unsigned int*)(0x42CE17A8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A11          *((volatile unsigned int*)(0x42CE17ACUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A12          *((volatile unsigned int*)(0x42CE17B0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A13          *((volatile unsigned int*)(0x42CE17B4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A14          *((volatile unsigned int*)(0x42CE17B8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A15          *((volatile unsigned int*)(0x42CE17BCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A16          *((volatile unsigned int*)(0x42CE17C0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A17          *((volatile unsigned int*)(0x42CE17C4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A18          *((volatile unsigned int*)(0x42CE17C8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A19          *((volatile unsigned int*)(0x42CE17CCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A20          *((volatile unsigned int*)(0x42CE17D0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A21          *((volatile unsigned int*)(0x42CE17D4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A22          *((volatile unsigned int*)(0x42CE17D8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A23          *((volatile unsigned int*)(0x42CE17DCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A24          *((volatile unsigned int*)(0x42CE17E0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A25          *((volatile unsigned int*)(0x42CE17E4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A26          *((volatile unsigned int*)(0x42CE17E8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A27          *((volatile unsigned int*)(0x42CE17ECUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A28          *((volatile unsigned int*)(0x42CE17F0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A29          *((volatile unsigned int*)(0x42CE17F4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A30          *((volatile unsigned int*)(0x42CE17F8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A31          *((volatile unsigned int*)(0x42CE17FCUL))
+#define bFM3_ETHERNET_MAC1_RGSR_LM             *((volatile unsigned int*)(0x42CE1B00UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP0           *((volatile unsigned int*)(0x42CE1B04UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP1           *((volatile unsigned int*)(0x42CE1B08UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LS             *((volatile unsigned int*)(0x42CE1B0CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSE            *((volatile unsigned int*)(0x42CEE000UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TFCU           *((volatile unsigned int*)(0x42CEE004UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSI            *((volatile unsigned int*)(0x42CEE008UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSU            *((volatile unsigned int*)(0x42CEE00CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TITE           *((volatile unsigned int*)(0x42CEE010UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TARU           *((volatile unsigned int*)(0x42CEE014UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSEA           *((volatile unsigned int*)(0x42CEE020UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSDB           *((volatile unsigned int*)(0x42CEE024UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSV2E          *((volatile unsigned int*)(0x42CEE028UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSP          *((volatile unsigned int*)(0x42CEE02CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E         *((volatile unsigned int*)(0x42CEE030UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E         *((volatile unsigned int*)(0x42CEE034UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSEM         *((volatile unsigned int*)(0x42CEE038UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSMRM          *((volatile unsigned int*)(0x42CEE03CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS0          *((volatile unsigned int*)(0x42CEE040UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS1          *((volatile unsigned int*)(0x42CEE044UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSENMF         *((volatile unsigned int*)(0x42CEE048UL))
+#define bFM3_ETHERNET_MAC1_TSCR_ATSFC          *((volatile unsigned int*)(0x42CEE060UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC0         *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC1         *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC2         *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC3         *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC4         *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC5         *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC6         *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC7         *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS0           *((volatile unsigned int*)(0x42CEE100UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS1           *((volatile unsigned int*)(0x42CEE104UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS2           *((volatile unsigned int*)(0x42CEE108UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS3           *((volatile unsigned int*)(0x42CEE10CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS4           *((volatile unsigned int*)(0x42CEE110UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS5           *((volatile unsigned int*)(0x42CEE114UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS6           *((volatile unsigned int*)(0x42CEE118UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS7           *((volatile unsigned int*)(0x42CEE11CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS8           *((volatile unsigned int*)(0x42CEE120UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS9           *((volatile unsigned int*)(0x42CEE124UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS10          *((volatile unsigned int*)(0x42CEE128UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS11          *((volatile unsigned int*)(0x42CEE12CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS12          *((volatile unsigned int*)(0x42CEE130UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS13          *((volatile unsigned int*)(0x42CEE134UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS14          *((volatile unsigned int*)(0x42CEE138UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS15          *((volatile unsigned int*)(0x42CEE13CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS16          *((volatile unsigned int*)(0x42CEE140UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS17          *((volatile unsigned int*)(0x42CEE144UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS18          *((volatile unsigned int*)(0x42CEE148UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS19          *((volatile unsigned int*)(0x42CEE14CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS20          *((volatile unsigned int*)(0x42CEE150UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS21          *((volatile unsigned int*)(0x42CEE154UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS22          *((volatile unsigned int*)(0x42CEE158UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS23          *((volatile unsigned int*)(0x42CEE15CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS24          *((volatile unsigned int*)(0x42CEE160UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS25          *((volatile unsigned int*)(0x42CEE164UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS26          *((volatile unsigned int*)(0x42CEE168UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS27          *((volatile unsigned int*)(0x42CEE16CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS28          *((volatile unsigned int*)(0x42CEE170UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS29          *((volatile unsigned int*)(0x42CEE174UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS30          *((volatile unsigned int*)(0x42CEE178UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS31          *((volatile unsigned int*)(0x42CEE17CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS0          *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS1          *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS2          *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS3          *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS4          *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS5          *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS6          *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS7          *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS8          *((volatile unsigned int*)(0x42CEE0A0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS9          *((volatile unsigned int*)(0x42CEE0A4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS10         *((volatile unsigned int*)(0x42CEE0A8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS11         *((volatile unsigned int*)(0x42CEE0ACUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS12         *((volatile unsigned int*)(0x42CEE0B0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS13         *((volatile unsigned int*)(0x42CEE0B4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS14         *((volatile unsigned int*)(0x42CEE0B8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS15         *((volatile unsigned int*)(0x42CEE0BCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS16         *((volatile unsigned int*)(0x42CEE0C0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS17         *((volatile unsigned int*)(0x42CEE0C4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS18         *((volatile unsigned int*)(0x42CEE0C8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS19         *((volatile unsigned int*)(0x42CEE0CCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS20         *((volatile unsigned int*)(0x42CEE0D0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS21         *((volatile unsigned int*)(0x42CEE0D4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS22         *((volatile unsigned int*)(0x42CEE0D8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS23         *((volatile unsigned int*)(0x42CEE0DCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS24         *((volatile unsigned int*)(0x42CEE0E0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS25         *((volatile unsigned int*)(0x42CEE0E4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS26         *((volatile unsigned int*)(0x42CEE0E8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS27         *((volatile unsigned int*)(0x42CEE0ECUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS28         *((volatile unsigned int*)(0x42CEE0F0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS29         *((volatile unsigned int*)(0x42CEE0F4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS30         *((volatile unsigned int*)(0x42CEE0F8UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS0          *((volatile unsigned int*)(0x42CEE200UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS1          *((volatile unsigned int*)(0x42CEE204UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS2          *((volatile unsigned int*)(0x42CEE208UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS3          *((volatile unsigned int*)(0x42CEE20CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS4          *((volatile unsigned int*)(0x42CEE210UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS5          *((volatile unsigned int*)(0x42CEE214UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS6          *((volatile unsigned int*)(0x42CEE218UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS7          *((volatile unsigned int*)(0x42CEE21CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS8          *((volatile unsigned int*)(0x42CEE220UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS9          *((volatile unsigned int*)(0x42CEE224UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS10         *((volatile unsigned int*)(0x42CEE228UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS11         *((volatile unsigned int*)(0x42CEE22CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS12         *((volatile unsigned int*)(0x42CEE230UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS13         *((volatile unsigned int*)(0x42CEE234UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS14         *((volatile unsigned int*)(0x42CEE238UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS15         *((volatile unsigned int*)(0x42CEE23CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS16         *((volatile unsigned int*)(0x42CEE240UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS17         *((volatile unsigned int*)(0x42CEE244UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS18         *((volatile unsigned int*)(0x42CEE248UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS19         *((volatile unsigned int*)(0x42CEE24CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS20         *((volatile unsigned int*)(0x42CEE250UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS21         *((volatile unsigned int*)(0x42CEE254UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS22         *((volatile unsigned int*)(0x42CEE258UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS23         *((volatile unsigned int*)(0x42CEE25CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS24         *((volatile unsigned int*)(0x42CEE260UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS25         *((volatile unsigned int*)(0x42CEE264UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS26         *((volatile unsigned int*)(0x42CEE268UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS27         *((volatile unsigned int*)(0x42CEE26CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS28         *((volatile unsigned int*)(0x42CEE270UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS29         *((volatile unsigned int*)(0x42CEE274UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS30         *((volatile unsigned int*)(0x42CEE278UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS31         *((volatile unsigned int*)(0x42CEE27CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS0         *((volatile unsigned int*)(0x42CEE280UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS1         *((volatile unsigned int*)(0x42CEE284UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS2         *((volatile unsigned int*)(0x42CEE288UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS3         *((volatile unsigned int*)(0x42CEE28CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS4         *((volatile unsigned int*)(0x42CEE290UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS5         *((volatile unsigned int*)(0x42CEE294UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS6         *((volatile unsigned int*)(0x42CEE298UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS7         *((volatile unsigned int*)(0x42CEE29CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS8         *((volatile unsigned int*)(0x42CEE2A0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS9         *((volatile unsigned int*)(0x42CEE2A4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS10        *((volatile unsigned int*)(0x42CEE2A8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS11        *((volatile unsigned int*)(0x42CEE2ACUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS12        *((volatile unsigned int*)(0x42CEE2B0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS13        *((volatile unsigned int*)(0x42CEE2B4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS14        *((volatile unsigned int*)(0x42CEE2B8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS15        *((volatile unsigned int*)(0x42CEE2BCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS16        *((volatile unsigned int*)(0x42CEE2C0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS17        *((volatile unsigned int*)(0x42CEE2C4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS18        *((volatile unsigned int*)(0x42CEE2C8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS19        *((volatile unsigned int*)(0x42CEE2CCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS20        *((volatile unsigned int*)(0x42CEE2D0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS21        *((volatile unsigned int*)(0x42CEE2D4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS22        *((volatile unsigned int*)(0x42CEE2D8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS23        *((volatile unsigned int*)(0x42CEE2DCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS24        *((volatile unsigned int*)(0x42CEE2E0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS25        *((volatile unsigned int*)(0x42CEE2E4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS26        *((volatile unsigned int*)(0x42CEE2E8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS27        *((volatile unsigned int*)(0x42CEE2ECUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS28        *((volatile unsigned int*)(0x42CEE2F0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS29        *((volatile unsigned int*)(0x42CEE2F4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS30        *((volatile unsigned int*)(0x42CEE2F8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB        *((volatile unsigned int*)(0x42CEE2FCUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR0          *((volatile unsigned int*)(0x42CEE300UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR1          *((volatile unsigned int*)(0x42CEE304UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR2          *((volatile unsigned int*)(0x42CEE308UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR3          *((volatile unsigned int*)(0x42CEE30CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR4          *((volatile unsigned int*)(0x42CEE310UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR5          *((volatile unsigned int*)(0x42CEE314UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR6          *((volatile unsigned int*)(0x42CEE318UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR7          *((volatile unsigned int*)(0x42CEE31CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR8          *((volatile unsigned int*)(0x42CEE320UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR9          *((volatile unsigned int*)(0x42CEE324UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR10         *((volatile unsigned int*)(0x42CEE328UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR11         *((volatile unsigned int*)(0x42CEE32CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR12         *((volatile unsigned int*)(0x42CEE330UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR13         *((volatile unsigned int*)(0x42CEE334UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR14         *((volatile unsigned int*)(0x42CEE338UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR15         *((volatile unsigned int*)(0x42CEE33CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR16         *((volatile unsigned int*)(0x42CEE340UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR17         *((volatile unsigned int*)(0x42CEE344UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR18         *((volatile unsigned int*)(0x42CEE348UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR19         *((volatile unsigned int*)(0x42CEE34CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR20         *((volatile unsigned int*)(0x42CEE350UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR21         *((volatile unsigned int*)(0x42CEE354UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR22         *((volatile unsigned int*)(0x42CEE358UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR23         *((volatile unsigned int*)(0x42CEE35CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR24         *((volatile unsigned int*)(0x42CEE360UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR25         *((volatile unsigned int*)(0x42CEE364UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR26         *((volatile unsigned int*)(0x42CEE368UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR27         *((volatile unsigned int*)(0x42CEE36CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR28         *((volatile unsigned int*)(0x42CEE370UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR29         *((volatile unsigned int*)(0x42CEE374UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR30         *((volatile unsigned int*)(0x42CEE378UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR31         *((volatile unsigned int*)(0x42CEE37CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR0          *((volatile unsigned int*)(0x42CEE380UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR1          *((volatile unsigned int*)(0x42CEE384UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR2          *((volatile unsigned int*)(0x42CEE388UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR3          *((volatile unsigned int*)(0x42CEE38CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR4          *((volatile unsigned int*)(0x42CEE390UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR5          *((volatile unsigned int*)(0x42CEE394UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR6          *((volatile unsigned int*)(0x42CEE398UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR7          *((volatile unsigned int*)(0x42CEE39CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR8          *((volatile unsigned int*)(0x42CEE3A0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR9          *((volatile unsigned int*)(0x42CEE3A4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR10         *((volatile unsigned int*)(0x42CEE3A8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR11         *((volatile unsigned int*)(0x42CEE3ACUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR12         *((volatile unsigned int*)(0x42CEE3B0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR13         *((volatile unsigned int*)(0x42CEE3B4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR14         *((volatile unsigned int*)(0x42CEE3B8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR15         *((volatile unsigned int*)(0x42CEE3BCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR16         *((volatile unsigned int*)(0x42CEE3C0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR17         *((volatile unsigned int*)(0x42CEE3C4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR18         *((volatile unsigned int*)(0x42CEE3C8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR19         *((volatile unsigned int*)(0x42CEE3CCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR20         *((volatile unsigned int*)(0x42CEE3D0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR21         *((volatile unsigned int*)(0x42CEE3D4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR22         *((volatile unsigned int*)(0x42CEE3D8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR23         *((volatile unsigned int*)(0x42CEE3DCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR24         *((volatile unsigned int*)(0x42CEE3E0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR25         *((volatile unsigned int*)(0x42CEE3E4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR26         *((volatile unsigned int*)(0x42CEE3E8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR27         *((volatile unsigned int*)(0x42CEE3ECUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR28         *((volatile unsigned int*)(0x42CEE3F0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR29         *((volatile unsigned int*)(0x42CEE3F4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR30         *((volatile unsigned int*)(0x42CEE3F8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR31         *((volatile unsigned int*)(0x42CEE3FCUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR0          *((volatile unsigned int*)(0x42CEE400UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR1          *((volatile unsigned int*)(0x42CEE404UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR2          *((volatile unsigned int*)(0x42CEE408UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR3          *((volatile unsigned int*)(0x42CEE40CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR4          *((volatile unsigned int*)(0x42CEE410UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR5          *((volatile unsigned int*)(0x42CEE414UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR6          *((volatile unsigned int*)(0x42CEE418UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR7          *((volatile unsigned int*)(0x42CEE41CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR8          *((volatile unsigned int*)(0x42CEE420UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR9          *((volatile unsigned int*)(0x42CEE424UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR10         *((volatile unsigned int*)(0x42CEE428UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR11         *((volatile unsigned int*)(0x42CEE42CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR12         *((volatile unsigned int*)(0x42CEE430UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR13         *((volatile unsigned int*)(0x42CEE434UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR14         *((volatile unsigned int*)(0x42CEE438UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR15         *((volatile unsigned int*)(0x42CEE43CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR16         *((volatile unsigned int*)(0x42CEE440UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR17         *((volatile unsigned int*)(0x42CEE444UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR18         *((volatile unsigned int*)(0x42CEE448UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR19         *((volatile unsigned int*)(0x42CEE44CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR20         *((volatile unsigned int*)(0x42CEE450UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR21         *((volatile unsigned int*)(0x42CEE454UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR22         *((volatile unsigned int*)(0x42CEE458UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR23         *((volatile unsigned int*)(0x42CEE45CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR24         *((volatile unsigned int*)(0x42CEE460UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR25         *((volatile unsigned int*)(0x42CEE464UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR26         *((volatile unsigned int*)(0x42CEE468UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR27         *((volatile unsigned int*)(0x42CEE46CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR28         *((volatile unsigned int*)(0x42CEE470UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR29         *((volatile unsigned int*)(0x42CEE474UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR30         *((volatile unsigned int*)(0x42CEE478UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42CEE480UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42CEE484UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42CEE488UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42CEE48CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42CEE490UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42CEE494UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42CEE498UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42CEE49CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42CEE4A0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42CEE4A4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42CEE4A8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42CEE4ACUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42CEE4B0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42CEE4B4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42CEE4B8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42CEE4BCUL))
+#define bFM3_ETHERNET_MAC1_TSR_TSSOVF          *((volatile unsigned int*)(0x42CEE500UL))
+#define bFM3_ETHERNET_MAC1_TSR_TSTART          *((volatile unsigned int*)(0x42CEE504UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSTS           *((volatile unsigned int*)(0x42CEE508UL))
+#define bFM3_ETHERNET_MAC1_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSSTM          *((volatile unsigned int*)(0x42CEE560UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS0          *((volatile unsigned int*)(0x42CEE564UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS1          *((volatile unsigned int*)(0x42CEE568UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS2          *((volatile unsigned int*)(0x42CEE56CUL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42CEE580UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42CEE584UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42CEE588UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42CEE58CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN0           *((volatile unsigned int*)(0x42CEE600UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN1           *((volatile unsigned int*)(0x42CEE604UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN2           *((volatile unsigned int*)(0x42CEE608UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN3           *((volatile unsigned int*)(0x42CEE60CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN4           *((volatile unsigned int*)(0x42CEE610UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN5           *((volatile unsigned int*)(0x42CEE614UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN6           *((volatile unsigned int*)(0x42CEE618UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN7           *((volatile unsigned int*)(0x42CEE61CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN8           *((volatile unsigned int*)(0x42CEE620UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN9           *((volatile unsigned int*)(0x42CEE624UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN10          *((volatile unsigned int*)(0x42CEE628UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN11          *((volatile unsigned int*)(0x42CEE62CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN12          *((volatile unsigned int*)(0x42CEE630UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN13          *((volatile unsigned int*)(0x42CEE634UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN14          *((volatile unsigned int*)(0x42CEE638UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN15          *((volatile unsigned int*)(0x42CEE63CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN16          *((volatile unsigned int*)(0x42CEE640UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN17          *((volatile unsigned int*)(0x42CEE644UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN18          *((volatile unsigned int*)(0x42CEE648UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN19          *((volatile unsigned int*)(0x42CEE64CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN20          *((volatile unsigned int*)(0x42CEE650UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN21          *((volatile unsigned int*)(0x42CEE654UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN22          *((volatile unsigned int*)(0x42CEE658UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN23          *((volatile unsigned int*)(0x42CEE65CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN24          *((volatile unsigned int*)(0x42CEE660UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN25          *((volatile unsigned int*)(0x42CEE664UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN26          *((volatile unsigned int*)(0x42CEE668UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN27          *((volatile unsigned int*)(0x42CEE66CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN28          *((volatile unsigned int*)(0x42CEE670UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN29          *((volatile unsigned int*)(0x42CEE674UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN30          *((volatile unsigned int*)(0x42CEE678UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS0           *((volatile unsigned int*)(0x42CEE680UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS1           *((volatile unsigned int*)(0x42CEE684UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS2           *((volatile unsigned int*)(0x42CEE688UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS3           *((volatile unsigned int*)(0x42CEE68CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS4           *((volatile unsigned int*)(0x42CEE690UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS5           *((volatile unsigned int*)(0x42CEE694UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS6           *((volatile unsigned int*)(0x42CEE698UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS7           *((volatile unsigned int*)(0x42CEE69CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS8           *((volatile unsigned int*)(0x42CEE6A0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS9           *((volatile unsigned int*)(0x42CEE6A4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS10          *((volatile unsigned int*)(0x42CEE6A8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS11          *((volatile unsigned int*)(0x42CEE6ACUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS12          *((volatile unsigned int*)(0x42CEE6B0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS13          *((volatile unsigned int*)(0x42CEE6B4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS14          *((volatile unsigned int*)(0x42CEE6B8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS15          *((volatile unsigned int*)(0x42CEE6BCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS16          *((volatile unsigned int*)(0x42CEE6C0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS17          *((volatile unsigned int*)(0x42CEE6C4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS18          *((volatile unsigned int*)(0x42CEE6C8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS19          *((volatile unsigned int*)(0x42CEE6CCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS20          *((volatile unsigned int*)(0x42CEE6D0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS21          *((volatile unsigned int*)(0x42CEE6D4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS22          *((volatile unsigned int*)(0x42CEE6D8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS23          *((volatile unsigned int*)(0x42CEE6DCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS24          *((volatile unsigned int*)(0x42CEE6E0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS25          *((volatile unsigned int*)(0x42CEE6E4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS26          *((volatile unsigned int*)(0x42CEE6E8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS27          *((volatile unsigned int*)(0x42CEE6ECUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS28          *((volatile unsigned int*)(0x42CEE6F0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS29          *((volatile unsigned int*)(0x42CEE6F4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS30          *((volatile unsigned int*)(0x42CEE6F8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS31          *((volatile unsigned int*)(0x42CEE6FCUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A32          *((volatile unsigned int*)(0x42CF0000UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A33          *((volatile unsigned int*)(0x42CF0004UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A34          *((volatile unsigned int*)(0x42CF0008UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A35          *((volatile unsigned int*)(0x42CF000CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A36          *((volatile unsigned int*)(0x42CF0010UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A37          *((volatile unsigned int*)(0x42CF0014UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A38          *((volatile unsigned int*)(0x42CF0018UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A39          *((volatile unsigned int*)(0x42CF001CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A40          *((volatile unsigned int*)(0x42CF0020UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A41          *((volatile unsigned int*)(0x42CF0024UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A42          *((volatile unsigned int*)(0x42CF0028UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A43          *((volatile unsigned int*)(0x42CF002CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A44          *((volatile unsigned int*)(0x42CF0030UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A45          *((volatile unsigned int*)(0x42CF0034UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A46          *((volatile unsigned int*)(0x42CF0038UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A47          *((volatile unsigned int*)(0x42CF003CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC0         *((volatile unsigned int*)(0x42CF0060UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC1         *((volatile unsigned int*)(0x42CF0064UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC2         *((volatile unsigned int*)(0x42CF0068UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC3         *((volatile unsigned int*)(0x42CF006CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC4         *((volatile unsigned int*)(0x42CF0070UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC5         *((volatile unsigned int*)(0x42CF0074UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_SA           *((volatile unsigned int*)(0x42CF0078UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_AE           *((volatile unsigned int*)(0x42CF007CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A0           *((volatile unsigned int*)(0x42CF0080UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A1           *((volatile unsigned int*)(0x42CF0084UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A2           *((volatile unsigned int*)(0x42CF0088UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A3           *((volatile unsigned int*)(0x42CF008CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A4           *((volatile unsigned int*)(0x42CF0090UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A5           *((volatile unsigned int*)(0x42CF0094UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A6           *((volatile unsigned int*)(0x42CF0098UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A7           *((volatile unsigned int*)(0x42CF009CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A8           *((volatile unsigned int*)(0x42CF00A0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A9           *((volatile unsigned int*)(0x42CF00A4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A10          *((volatile unsigned int*)(0x42CF00A8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A11          *((volatile unsigned int*)(0x42CF00ACUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A12          *((volatile unsigned int*)(0x42CF00B0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A13          *((volatile unsigned int*)(0x42CF00B4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A14          *((volatile unsigned int*)(0x42CF00B8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A15          *((volatile unsigned int*)(0x42CF00BCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A16          *((volatile unsigned int*)(0x42CF00C0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A17          *((volatile unsigned int*)(0x42CF00C4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A18          *((volatile unsigned int*)(0x42CF00C8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A19          *((volatile unsigned int*)(0x42CF00CCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A20          *((volatile unsigned int*)(0x42CF00D0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A21          *((volatile unsigned int*)(0x42CF00D4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A22          *((volatile unsigned int*)(0x42CF00D8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A23          *((volatile unsigned int*)(0x42CF00DCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A24          *((volatile unsigned int*)(0x42CF00E0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A25          *((volatile unsigned int*)(0x42CF00E4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A26          *((volatile unsigned int*)(0x42CF00E8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A27          *((volatile unsigned int*)(0x42CF00ECUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A28          *((volatile unsigned int*)(0x42CF00F0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A29          *((volatile unsigned int*)(0x42CF00F4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A30          *((volatile unsigned int*)(0x42CF00F8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A31          *((volatile unsigned int*)(0x42CF00FCUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A32          *((volatile unsigned int*)(0x42CF0100UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A33          *((volatile unsigned int*)(0x42CF0104UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A34          *((volatile unsigned int*)(0x42CF0108UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A35          *((volatile unsigned int*)(0x42CF010CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A36          *((volatile unsigned int*)(0x42CF0110UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A37          *((volatile unsigned int*)(0x42CF0114UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A38          *((volatile unsigned int*)(0x42CF0118UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A39          *((volatile unsigned int*)(0x42CF011CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A40          *((volatile unsigned int*)(0x42CF0120UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A41          *((volatile unsigned int*)(0x42CF0124UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A42          *((volatile unsigned int*)(0x42CF0128UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A43          *((volatile unsigned int*)(0x42CF012CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A44          *((volatile unsigned int*)(0x42CF0130UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A45          *((volatile unsigned int*)(0x42CF0134UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A46          *((volatile unsigned int*)(0x42CF0138UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A47          *((volatile unsigned int*)(0x42CF013CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC0         *((volatile unsigned int*)(0x42CF0160UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC1         *((volatile unsigned int*)(0x42CF0164UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC2         *((volatile unsigned int*)(0x42CF0168UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC3         *((volatile unsigned int*)(0x42CF016CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC4         *((volatile unsigned int*)(0x42CF0170UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC5         *((volatile unsigned int*)(0x42CF0174UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_SA           *((volatile unsigned int*)(0x42CF0178UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_AE           *((volatile unsigned int*)(0x42CF017CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A0           *((volatile unsigned int*)(0x42CF0180UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A1           *((volatile unsigned int*)(0x42CF0184UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A2           *((volatile unsigned int*)(0x42CF0188UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A3           *((volatile unsigned int*)(0x42CF018CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A4           *((volatile unsigned int*)(0x42CF0190UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A5           *((volatile unsigned int*)(0x42CF0194UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A6           *((volatile unsigned int*)(0x42CF0198UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A7           *((volatile unsigned int*)(0x42CF019CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A8           *((volatile unsigned int*)(0x42CF01A0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A9           *((volatile unsigned int*)(0x42CF01A4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A10          *((volatile unsigned int*)(0x42CF01A8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A11          *((volatile unsigned int*)(0x42CF01ACUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A12          *((volatile unsigned int*)(0x42CF01B0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A13          *((volatile unsigned int*)(0x42CF01B4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A14          *((volatile unsigned int*)(0x42CF01B8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A15          *((volatile unsigned int*)(0x42CF01BCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A16          *((volatile unsigned int*)(0x42CF01C0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A17          *((volatile unsigned int*)(0x42CF01C4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A18          *((volatile unsigned int*)(0x42CF01C8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A19          *((volatile unsigned int*)(0x42CF01CCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A20          *((volatile unsigned int*)(0x42CF01D0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A21          *((volatile unsigned int*)(0x42CF01D4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A22          *((volatile unsigned int*)(0x42CF01D8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A23          *((volatile unsigned int*)(0x42CF01DCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A24          *((volatile unsigned int*)(0x42CF01E0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A25          *((volatile unsigned int*)(0x42CF01E4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A26          *((volatile unsigned int*)(0x42CF01E8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A27          *((volatile unsigned int*)(0x42CF01ECUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A28          *((volatile unsigned int*)(0x42CF01F0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A29          *((volatile unsigned int*)(0x42CF01F4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A30          *((volatile unsigned int*)(0x42CF01F8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A31          *((volatile unsigned int*)(0x42CF01FCUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A32          *((volatile unsigned int*)(0x42CF0200UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A33          *((volatile unsigned int*)(0x42CF0204UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A34          *((volatile unsigned int*)(0x42CF0208UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A35          *((volatile unsigned int*)(0x42CF020CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A36          *((volatile unsigned int*)(0x42CF0210UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A37          *((volatile unsigned int*)(0x42CF0214UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A38          *((volatile unsigned int*)(0x42CF0218UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A39          *((volatile unsigned int*)(0x42CF021CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A40          *((volatile unsigned int*)(0x42CF0220UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A41          *((volatile unsigned int*)(0x42CF0224UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A42          *((volatile unsigned int*)(0x42CF0228UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A43          *((volatile unsigned int*)(0x42CF022CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A44          *((volatile unsigned int*)(0x42CF0230UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A45          *((volatile unsigned int*)(0x42CF0234UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A46          *((volatile unsigned int*)(0x42CF0238UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A47          *((volatile unsigned int*)(0x42CF023CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC0         *((volatile unsigned int*)(0x42CF0260UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC1         *((volatile unsigned int*)(0x42CF0264UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC2         *((volatile unsigned int*)(0x42CF0268UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC3         *((volatile unsigned int*)(0x42CF026CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC4         *((volatile unsigned int*)(0x42CF0270UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC5         *((volatile unsigned int*)(0x42CF0274UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_SA           *((volatile unsigned int*)(0x42CF0278UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_AE           *((volatile unsigned int*)(0x42CF027CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A0           *((volatile unsigned int*)(0x42CF0280UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A1           *((volatile unsigned int*)(0x42CF0284UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A2           *((volatile unsigned int*)(0x42CF0288UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A3           *((volatile unsigned int*)(0x42CF028CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A4           *((volatile unsigned int*)(0x42CF0290UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A5           *((volatile unsigned int*)(0x42CF0294UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A6           *((volatile unsigned int*)(0x42CF0298UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A7           *((volatile unsigned int*)(0x42CF029CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A8           *((volatile unsigned int*)(0x42CF02A0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A9           *((volatile unsigned int*)(0x42CF02A4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A10          *((volatile unsigned int*)(0x42CF02A8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A11          *((volatile unsigned int*)(0x42CF02ACUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A12          *((volatile unsigned int*)(0x42CF02B0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A13          *((volatile unsigned int*)(0x42CF02B4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A14          *((volatile unsigned int*)(0x42CF02B8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A15          *((volatile unsigned int*)(0x42CF02BCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A16          *((volatile unsigned int*)(0x42CF02C0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A17          *((volatile unsigned int*)(0x42CF02C4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A18          *((volatile unsigned int*)(0x42CF02C8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A19          *((volatile unsigned int*)(0x42CF02CCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A20          *((volatile unsigned int*)(0x42CF02D0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A21          *((volatile unsigned int*)(0x42CF02D4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A22          *((volatile unsigned int*)(0x42CF02D8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A23          *((volatile unsigned int*)(0x42CF02DCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A24          *((volatile unsigned int*)(0x42CF02E0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A25          *((volatile unsigned int*)(0x42CF02E4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A26          *((volatile unsigned int*)(0x42CF02E8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A27          *((volatile unsigned int*)(0x42CF02ECUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A28          *((volatile unsigned int*)(0x42CF02F0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A29          *((volatile unsigned int*)(0x42CF02F4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A30          *((volatile unsigned int*)(0x42CF02F8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A31          *((volatile unsigned int*)(0x42CF02FCUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A32          *((volatile unsigned int*)(0x42CF0300UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A33          *((volatile unsigned int*)(0x42CF0304UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A34          *((volatile unsigned int*)(0x42CF0308UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A35          *((volatile unsigned int*)(0x42CF030CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A36          *((volatile unsigned int*)(0x42CF0310UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A37          *((volatile unsigned int*)(0x42CF0314UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A38          *((volatile unsigned int*)(0x42CF0318UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A39          *((volatile unsigned int*)(0x42CF031CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A40          *((volatile unsigned int*)(0x42CF0320UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A41          *((volatile unsigned int*)(0x42CF0324UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A42          *((volatile unsigned int*)(0x42CF0328UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A43          *((volatile unsigned int*)(0x42CF032CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A44          *((volatile unsigned int*)(0x42CF0330UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A45          *((volatile unsigned int*)(0x42CF0334UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A46          *((volatile unsigned int*)(0x42CF0338UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A47          *((volatile unsigned int*)(0x42CF033CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC0         *((volatile unsigned int*)(0x42CF0360UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC1         *((volatile unsigned int*)(0x42CF0364UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC2         *((volatile unsigned int*)(0x42CF0368UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC3         *((volatile unsigned int*)(0x42CF036CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC4         *((volatile unsigned int*)(0x42CF0370UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC5         *((volatile unsigned int*)(0x42CF0374UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_SA           *((volatile unsigned int*)(0x42CF0378UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_AE           *((volatile unsigned int*)(0x42CF037CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A0           *((volatile unsigned int*)(0x42CF0380UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A1           *((volatile unsigned int*)(0x42CF0384UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A2           *((volatile unsigned int*)(0x42CF0388UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A3           *((volatile unsigned int*)(0x42CF038CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A4           *((volatile unsigned int*)(0x42CF0390UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A5           *((volatile unsigned int*)(0x42CF0394UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A6           *((volatile unsigned int*)(0x42CF0398UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A7           *((volatile unsigned int*)(0x42CF039CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A8           *((volatile unsigned int*)(0x42CF03A0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A9           *((volatile unsigned int*)(0x42CF03A4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A10          *((volatile unsigned int*)(0x42CF03A8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A11          *((volatile unsigned int*)(0x42CF03ACUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A12          *((volatile unsigned int*)(0x42CF03B0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A13          *((volatile unsigned int*)(0x42CF03B4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A14          *((volatile unsigned int*)(0x42CF03B8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A15          *((volatile unsigned int*)(0x42CF03BCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A16          *((volatile unsigned int*)(0x42CF03C0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A17          *((volatile unsigned int*)(0x42CF03C4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A18          *((volatile unsigned int*)(0x42CF03C8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A19          *((volatile unsigned int*)(0x42CF03CCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A20          *((volatile unsigned int*)(0x42CF03D0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A21          *((volatile unsigned int*)(0x42CF03D4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A22          *((volatile unsigned int*)(0x42CF03D8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A23          *((volatile unsigned int*)(0x42CF03DCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A24          *((volatile unsigned int*)(0x42CF03E0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A25          *((volatile unsigned int*)(0x42CF03E4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A26          *((volatile unsigned int*)(0x42CF03E8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A27          *((volatile unsigned int*)(0x42CF03ECUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A28          *((volatile unsigned int*)(0x42CF03F0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A29          *((volatile unsigned int*)(0x42CF03F4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A30          *((volatile unsigned int*)(0x42CF03F8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A31          *((volatile unsigned int*)(0x42CF03FCUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A32          *((volatile unsigned int*)(0x42CF0400UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A33          *((volatile unsigned int*)(0x42CF0404UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A34          *((volatile unsigned int*)(0x42CF0408UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A35          *((volatile unsigned int*)(0x42CF040CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A36          *((volatile unsigned int*)(0x42CF0410UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A37          *((volatile unsigned int*)(0x42CF0414UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A38          *((volatile unsigned int*)(0x42CF0418UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A39          *((volatile unsigned int*)(0x42CF041CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A40          *((volatile unsigned int*)(0x42CF0420UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A41          *((volatile unsigned int*)(0x42CF0424UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A42          *((volatile unsigned int*)(0x42CF0428UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A43          *((volatile unsigned int*)(0x42CF042CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A44          *((volatile unsigned int*)(0x42CF0430UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A45          *((volatile unsigned int*)(0x42CF0434UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A46          *((volatile unsigned int*)(0x42CF0438UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A47          *((volatile unsigned int*)(0x42CF043CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC0         *((volatile unsigned int*)(0x42CF0460UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC1         *((volatile unsigned int*)(0x42CF0464UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC2         *((volatile unsigned int*)(0x42CF0468UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC3         *((volatile unsigned int*)(0x42CF046CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC4         *((volatile unsigned int*)(0x42CF0470UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC5         *((volatile unsigned int*)(0x42CF0474UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_SA           *((volatile unsigned int*)(0x42CF0478UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_AE           *((volatile unsigned int*)(0x42CF047CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A0           *((volatile unsigned int*)(0x42CF0480UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A1           *((volatile unsigned int*)(0x42CF0484UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A2           *((volatile unsigned int*)(0x42CF0488UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A3           *((volatile unsigned int*)(0x42CF048CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A4           *((volatile unsigned int*)(0x42CF0490UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A5           *((volatile unsigned int*)(0x42CF0494UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A6           *((volatile unsigned int*)(0x42CF0498UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A7           *((volatile unsigned int*)(0x42CF049CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A8           *((volatile unsigned int*)(0x42CF04A0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A9           *((volatile unsigned int*)(0x42CF04A4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A10          *((volatile unsigned int*)(0x42CF04A8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A11          *((volatile unsigned int*)(0x42CF04ACUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A12          *((volatile unsigned int*)(0x42CF04B0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A13          *((volatile unsigned int*)(0x42CF04B4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A14          *((volatile unsigned int*)(0x42CF04B8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A15          *((volatile unsigned int*)(0x42CF04BCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A16          *((volatile unsigned int*)(0x42CF04C0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A17          *((volatile unsigned int*)(0x42CF04C4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A18          *((volatile unsigned int*)(0x42CF04C8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A19          *((volatile unsigned int*)(0x42CF04CCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A20          *((volatile unsigned int*)(0x42CF04D0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A21          *((volatile unsigned int*)(0x42CF04D4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A22          *((volatile unsigned int*)(0x42CF04D8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A23          *((volatile unsigned int*)(0x42CF04DCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A24          *((volatile unsigned int*)(0x42CF04E0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A25          *((volatile unsigned int*)(0x42CF04E4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A26          *((volatile unsigned int*)(0x42CF04E8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A27          *((volatile unsigned int*)(0x42CF04ECUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A28          *((volatile unsigned int*)(0x42CF04F0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A29          *((volatile unsigned int*)(0x42CF04F4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A30          *((volatile unsigned int*)(0x42CF04F8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A31          *((volatile unsigned int*)(0x42CF04FCUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A32          *((volatile unsigned int*)(0x42CF0500UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A33          *((volatile unsigned int*)(0x42CF0504UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A34          *((volatile unsigned int*)(0x42CF0508UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A35          *((volatile unsigned int*)(0x42CF050CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A36          *((volatile unsigned int*)(0x42CF0510UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A37          *((volatile unsigned int*)(0x42CF0514UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A38          *((volatile unsigned int*)(0x42CF0518UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A39          *((volatile unsigned int*)(0x42CF051CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A40          *((volatile unsigned int*)(0x42CF0520UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A41          *((volatile unsigned int*)(0x42CF0524UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A42          *((volatile unsigned int*)(0x42CF0528UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A43          *((volatile unsigned int*)(0x42CF052CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A44          *((volatile unsigned int*)(0x42CF0530UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A45          *((volatile unsigned int*)(0x42CF0534UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A46          *((volatile unsigned int*)(0x42CF0538UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A47          *((volatile unsigned int*)(0x42CF053CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC0         *((volatile unsigned int*)(0x42CF0560UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC1         *((volatile unsigned int*)(0x42CF0564UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC2         *((volatile unsigned int*)(0x42CF0568UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC3         *((volatile unsigned int*)(0x42CF056CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC4         *((volatile unsigned int*)(0x42CF0570UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC5         *((volatile unsigned int*)(0x42CF0574UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_SA           *((volatile unsigned int*)(0x42CF0578UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_AE           *((volatile unsigned int*)(0x42CF057CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A0           *((volatile unsigned int*)(0x42CF0580UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A1           *((volatile unsigned int*)(0x42CF0584UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A2           *((volatile unsigned int*)(0x42CF0588UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A3           *((volatile unsigned int*)(0x42CF058CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A4           *((volatile unsigned int*)(0x42CF0590UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A5           *((volatile unsigned int*)(0x42CF0594UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A6           *((volatile unsigned int*)(0x42CF0598UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A7           *((volatile unsigned int*)(0x42CF059CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A8           *((volatile unsigned int*)(0x42CF05A0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A9           *((volatile unsigned int*)(0x42CF05A4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A10          *((volatile unsigned int*)(0x42CF05A8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A11          *((volatile unsigned int*)(0x42CF05ACUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A12          *((volatile unsigned int*)(0x42CF05B0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A13          *((volatile unsigned int*)(0x42CF05B4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A14          *((volatile unsigned int*)(0x42CF05B8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A15          *((volatile unsigned int*)(0x42CF05BCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A16          *((volatile unsigned int*)(0x42CF05C0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A17          *((volatile unsigned int*)(0x42CF05C4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A18          *((volatile unsigned int*)(0x42CF05C8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A19          *((volatile unsigned int*)(0x42CF05CCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A20          *((volatile unsigned int*)(0x42CF05D0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A21          *((volatile unsigned int*)(0x42CF05D4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A22          *((volatile unsigned int*)(0x42CF05D8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A23          *((volatile unsigned int*)(0x42CF05DCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A24          *((volatile unsigned int*)(0x42CF05E0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A25          *((volatile unsigned int*)(0x42CF05E4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A26          *((volatile unsigned int*)(0x42CF05E8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A27          *((volatile unsigned int*)(0x42CF05ECUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A28          *((volatile unsigned int*)(0x42CF05F0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A29          *((volatile unsigned int*)(0x42CF05F4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A30          *((volatile unsigned int*)(0x42CF05F8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A31          *((volatile unsigned int*)(0x42CF05FCUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A32          *((volatile unsigned int*)(0x42CF0600UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A33          *((volatile unsigned int*)(0x42CF0604UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A34          *((volatile unsigned int*)(0x42CF0608UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A35          *((volatile unsigned int*)(0x42CF060CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A36          *((volatile unsigned int*)(0x42CF0610UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A37          *((volatile unsigned int*)(0x42CF0614UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A38          *((volatile unsigned int*)(0x42CF0618UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A39          *((volatile unsigned int*)(0x42CF061CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A40          *((volatile unsigned int*)(0x42CF0620UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A41          *((volatile unsigned int*)(0x42CF0624UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A42          *((volatile unsigned int*)(0x42CF0628UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A43          *((volatile unsigned int*)(0x42CF062CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A44          *((volatile unsigned int*)(0x42CF0630UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A45          *((volatile unsigned int*)(0x42CF0634UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A46          *((volatile unsigned int*)(0x42CF0638UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A47          *((volatile unsigned int*)(0x42CF063CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC0         *((volatile unsigned int*)(0x42CF0660UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC1         *((volatile unsigned int*)(0x42CF0664UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC2         *((volatile unsigned int*)(0x42CF0668UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC3         *((volatile unsigned int*)(0x42CF066CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC4         *((volatile unsigned int*)(0x42CF0670UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC5         *((volatile unsigned int*)(0x42CF0674UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_SA           *((volatile unsigned int*)(0x42CF0678UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_AE           *((volatile unsigned int*)(0x42CF067CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A0           *((volatile unsigned int*)(0x42CF0680UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A1           *((volatile unsigned int*)(0x42CF0684UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A2           *((volatile unsigned int*)(0x42CF0688UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A3           *((volatile unsigned int*)(0x42CF068CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A4           *((volatile unsigned int*)(0x42CF0690UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A5           *((volatile unsigned int*)(0x42CF0694UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A6           *((volatile unsigned int*)(0x42CF0698UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A7           *((volatile unsigned int*)(0x42CF069CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A8           *((volatile unsigned int*)(0x42CF06A0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A9           *((volatile unsigned int*)(0x42CF06A4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A10          *((volatile unsigned int*)(0x42CF06A8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A11          *((volatile unsigned int*)(0x42CF06ACUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A12          *((volatile unsigned int*)(0x42CF06B0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A13          *((volatile unsigned int*)(0x42CF06B4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A14          *((volatile unsigned int*)(0x42CF06B8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A15          *((volatile unsigned int*)(0x42CF06BCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A16          *((volatile unsigned int*)(0x42CF06C0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A17          *((volatile unsigned int*)(0x42CF06C4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A18          *((volatile unsigned int*)(0x42CF06C8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A19          *((volatile unsigned int*)(0x42CF06CCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A20          *((volatile unsigned int*)(0x42CF06D0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A21          *((volatile unsigned int*)(0x42CF06D4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A22          *((volatile unsigned int*)(0x42CF06D8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A23          *((volatile unsigned int*)(0x42CF06DCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A24          *((volatile unsigned int*)(0x42CF06E0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A25          *((volatile unsigned int*)(0x42CF06E4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A26          *((volatile unsigned int*)(0x42CF06E8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A27          *((volatile unsigned int*)(0x42CF06ECUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A28          *((volatile unsigned int*)(0x42CF06F0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A29          *((volatile unsigned int*)(0x42CF06F4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A30          *((volatile unsigned int*)(0x42CF06F8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A31          *((volatile unsigned int*)(0x42CF06FCUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A32          *((volatile unsigned int*)(0x42CF0700UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A33          *((volatile unsigned int*)(0x42CF0704UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A34          *((volatile unsigned int*)(0x42CF0708UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A35          *((volatile unsigned int*)(0x42CF070CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A36          *((volatile unsigned int*)(0x42CF0710UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A37          *((volatile unsigned int*)(0x42CF0714UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A38          *((volatile unsigned int*)(0x42CF0718UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A39          *((volatile unsigned int*)(0x42CF071CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A40          *((volatile unsigned int*)(0x42CF0720UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A41          *((volatile unsigned int*)(0x42CF0724UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A42          *((volatile unsigned int*)(0x42CF0728UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A43          *((volatile unsigned int*)(0x42CF072CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A44          *((volatile unsigned int*)(0x42CF0730UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A45          *((volatile unsigned int*)(0x42CF0734UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A46          *((volatile unsigned int*)(0x42CF0738UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A47          *((volatile unsigned int*)(0x42CF073CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC0         *((volatile unsigned int*)(0x42CF0760UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC1         *((volatile unsigned int*)(0x42CF0764UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC2         *((volatile unsigned int*)(0x42CF0768UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC3         *((volatile unsigned int*)(0x42CF076CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC4         *((volatile unsigned int*)(0x42CF0770UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC5         *((volatile unsigned int*)(0x42CF0774UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_SA           *((volatile unsigned int*)(0x42CF0778UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_AE           *((volatile unsigned int*)(0x42CF077CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A0           *((volatile unsigned int*)(0x42CF0780UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A1           *((volatile unsigned int*)(0x42CF0784UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A2           *((volatile unsigned int*)(0x42CF0788UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A3           *((volatile unsigned int*)(0x42CF078CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A4           *((volatile unsigned int*)(0x42CF0790UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A5           *((volatile unsigned int*)(0x42CF0794UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A6           *((volatile unsigned int*)(0x42CF0798UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A7           *((volatile unsigned int*)(0x42CF079CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A8           *((volatile unsigned int*)(0x42CF07A0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A9           *((volatile unsigned int*)(0x42CF07A4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A10          *((volatile unsigned int*)(0x42CF07A8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A11          *((volatile unsigned int*)(0x42CF07ACUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A12          *((volatile unsigned int*)(0x42CF07B0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A13          *((volatile unsigned int*)(0x42CF07B4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A14          *((volatile unsigned int*)(0x42CF07B8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A15          *((volatile unsigned int*)(0x42CF07BCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A16          *((volatile unsigned int*)(0x42CF07C0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A17          *((volatile unsigned int*)(0x42CF07C4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A18          *((volatile unsigned int*)(0x42CF07C8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A19          *((volatile unsigned int*)(0x42CF07CCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A20          *((volatile unsigned int*)(0x42CF07D0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A21          *((volatile unsigned int*)(0x42CF07D4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A22          *((volatile unsigned int*)(0x42CF07D8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A23          *((volatile unsigned int*)(0x42CF07DCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A24          *((volatile unsigned int*)(0x42CF07E0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A25          *((volatile unsigned int*)(0x42CF07E4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A26          *((volatile unsigned int*)(0x42CF07E8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A27          *((volatile unsigned int*)(0x42CF07ECUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A28          *((volatile unsigned int*)(0x42CF07F0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A29          *((volatile unsigned int*)(0x42CF07F4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A30          *((volatile unsigned int*)(0x42CF07F8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A31          *((volatile unsigned int*)(0x42CF07FCUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A32          *((volatile unsigned int*)(0x42CF0800UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A33          *((volatile unsigned int*)(0x42CF0804UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A34          *((volatile unsigned int*)(0x42CF0808UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A35          *((volatile unsigned int*)(0x42CF080CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A36          *((volatile unsigned int*)(0x42CF0810UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A37          *((volatile unsigned int*)(0x42CF0814UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A38          *((volatile unsigned int*)(0x42CF0818UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A39          *((volatile unsigned int*)(0x42CF081CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A40          *((volatile unsigned int*)(0x42CF0820UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A41          *((volatile unsigned int*)(0x42CF0824UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A42          *((volatile unsigned int*)(0x42CF0828UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A43          *((volatile unsigned int*)(0x42CF082CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A44          *((volatile unsigned int*)(0x42CF0830UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A45          *((volatile unsigned int*)(0x42CF0834UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A46          *((volatile unsigned int*)(0x42CF0838UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A47          *((volatile unsigned int*)(0x42CF083CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC0         *((volatile unsigned int*)(0x42CF0860UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC1         *((volatile unsigned int*)(0x42CF0864UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC2         *((volatile unsigned int*)(0x42CF0868UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC3         *((volatile unsigned int*)(0x42CF086CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC4         *((volatile unsigned int*)(0x42CF0870UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC5         *((volatile unsigned int*)(0x42CF0874UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_SA           *((volatile unsigned int*)(0x42CF0878UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_AE           *((volatile unsigned int*)(0x42CF087CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A0           *((volatile unsigned int*)(0x42CF0880UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A1           *((volatile unsigned int*)(0x42CF0884UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A2           *((volatile unsigned int*)(0x42CF0888UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A3           *((volatile unsigned int*)(0x42CF088CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A4           *((volatile unsigned int*)(0x42CF0890UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A5           *((volatile unsigned int*)(0x42CF0894UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A6           *((volatile unsigned int*)(0x42CF0898UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A7           *((volatile unsigned int*)(0x42CF089CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A8           *((volatile unsigned int*)(0x42CF08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A9           *((volatile unsigned int*)(0x42CF08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A10          *((volatile unsigned int*)(0x42CF08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A11          *((volatile unsigned int*)(0x42CF08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A12          *((volatile unsigned int*)(0x42CF08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A13          *((volatile unsigned int*)(0x42CF08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A14          *((volatile unsigned int*)(0x42CF08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A15          *((volatile unsigned int*)(0x42CF08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A16          *((volatile unsigned int*)(0x42CF08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A17          *((volatile unsigned int*)(0x42CF08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A18          *((volatile unsigned int*)(0x42CF08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A19          *((volatile unsigned int*)(0x42CF08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A20          *((volatile unsigned int*)(0x42CF08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A21          *((volatile unsigned int*)(0x42CF08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A22          *((volatile unsigned int*)(0x42CF08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A23          *((volatile unsigned int*)(0x42CF08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A24          *((volatile unsigned int*)(0x42CF08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A25          *((volatile unsigned int*)(0x42CF08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A26          *((volatile unsigned int*)(0x42CF08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A27          *((volatile unsigned int*)(0x42CF08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A28          *((volatile unsigned int*)(0x42CF08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A29          *((volatile unsigned int*)(0x42CF08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A30          *((volatile unsigned int*)(0x42CF08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A31          *((volatile unsigned int*)(0x42CF08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A32          *((volatile unsigned int*)(0x42CF0900UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A33          *((volatile unsigned int*)(0x42CF0904UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A34          *((volatile unsigned int*)(0x42CF0908UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A35          *((volatile unsigned int*)(0x42CF090CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A36          *((volatile unsigned int*)(0x42CF0910UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A37          *((volatile unsigned int*)(0x42CF0914UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A38          *((volatile unsigned int*)(0x42CF0918UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A39          *((volatile unsigned int*)(0x42CF091CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A40          *((volatile unsigned int*)(0x42CF0920UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A41          *((volatile unsigned int*)(0x42CF0924UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A42          *((volatile unsigned int*)(0x42CF0928UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A43          *((volatile unsigned int*)(0x42CF092CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A44          *((volatile unsigned int*)(0x42CF0930UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A45          *((volatile unsigned int*)(0x42CF0934UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A46          *((volatile unsigned int*)(0x42CF0938UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A47          *((volatile unsigned int*)(0x42CF093CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC0         *((volatile unsigned int*)(0x42CF0960UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC1         *((volatile unsigned int*)(0x42CF0964UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC2         *((volatile unsigned int*)(0x42CF0968UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC3         *((volatile unsigned int*)(0x42CF096CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC4         *((volatile unsigned int*)(0x42CF0970UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC5         *((volatile unsigned int*)(0x42CF0974UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_SA           *((volatile unsigned int*)(0x42CF0978UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_AE           *((volatile unsigned int*)(0x42CF097CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A0           *((volatile unsigned int*)(0x42CF0980UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A1           *((volatile unsigned int*)(0x42CF0984UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A2           *((volatile unsigned int*)(0x42CF0988UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A3           *((volatile unsigned int*)(0x42CF098CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A4           *((volatile unsigned int*)(0x42CF0990UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A5           *((volatile unsigned int*)(0x42CF0994UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A6           *((volatile unsigned int*)(0x42CF0998UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A7           *((volatile unsigned int*)(0x42CF099CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A8           *((volatile unsigned int*)(0x42CF09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A9           *((volatile unsigned int*)(0x42CF09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A10          *((volatile unsigned int*)(0x42CF09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A11          *((volatile unsigned int*)(0x42CF09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A12          *((volatile unsigned int*)(0x42CF09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A13          *((volatile unsigned int*)(0x42CF09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A14          *((volatile unsigned int*)(0x42CF09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A15          *((volatile unsigned int*)(0x42CF09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A16          *((volatile unsigned int*)(0x42CF09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A17          *((volatile unsigned int*)(0x42CF09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A18          *((volatile unsigned int*)(0x42CF09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A19          *((volatile unsigned int*)(0x42CF09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A20          *((volatile unsigned int*)(0x42CF09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A21          *((volatile unsigned int*)(0x42CF09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A22          *((volatile unsigned int*)(0x42CF09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A23          *((volatile unsigned int*)(0x42CF09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A24          *((volatile unsigned int*)(0x42CF09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A25          *((volatile unsigned int*)(0x42CF09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A26          *((volatile unsigned int*)(0x42CF09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A27          *((volatile unsigned int*)(0x42CF09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A28          *((volatile unsigned int*)(0x42CF09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A29          *((volatile unsigned int*)(0x42CF09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A30          *((volatile unsigned int*)(0x42CF09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A31          *((volatile unsigned int*)(0x42CF09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A32          *((volatile unsigned int*)(0x42CF0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A33          *((volatile unsigned int*)(0x42CF0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A34          *((volatile unsigned int*)(0x42CF0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A35          *((volatile unsigned int*)(0x42CF0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A36          *((volatile unsigned int*)(0x42CF0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A37          *((volatile unsigned int*)(0x42CF0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A38          *((volatile unsigned int*)(0x42CF0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A39          *((volatile unsigned int*)(0x42CF0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A40          *((volatile unsigned int*)(0x42CF0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A41          *((volatile unsigned int*)(0x42CF0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A42          *((volatile unsigned int*)(0x42CF0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A43          *((volatile unsigned int*)(0x42CF0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A44          *((volatile unsigned int*)(0x42CF0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A45          *((volatile unsigned int*)(0x42CF0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A46          *((volatile unsigned int*)(0x42CF0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A47          *((volatile unsigned int*)(0x42CF0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC0         *((volatile unsigned int*)(0x42CF0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC1         *((volatile unsigned int*)(0x42CF0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC2         *((volatile unsigned int*)(0x42CF0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC3         *((volatile unsigned int*)(0x42CF0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC4         *((volatile unsigned int*)(0x42CF0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC5         *((volatile unsigned int*)(0x42CF0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_SA           *((volatile unsigned int*)(0x42CF0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_AE           *((volatile unsigned int*)(0x42CF0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A0           *((volatile unsigned int*)(0x42CF0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A1           *((volatile unsigned int*)(0x42CF0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A2           *((volatile unsigned int*)(0x42CF0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A3           *((volatile unsigned int*)(0x42CF0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A4           *((volatile unsigned int*)(0x42CF0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A5           *((volatile unsigned int*)(0x42CF0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A6           *((volatile unsigned int*)(0x42CF0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A7           *((volatile unsigned int*)(0x42CF0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A8           *((volatile unsigned int*)(0x42CF0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A9           *((volatile unsigned int*)(0x42CF0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A10          *((volatile unsigned int*)(0x42CF0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A11          *((volatile unsigned int*)(0x42CF0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A12          *((volatile unsigned int*)(0x42CF0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A13          *((volatile unsigned int*)(0x42CF0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A14          *((volatile unsigned int*)(0x42CF0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A15          *((volatile unsigned int*)(0x42CF0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A16          *((volatile unsigned int*)(0x42CF0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A17          *((volatile unsigned int*)(0x42CF0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A18          *((volatile unsigned int*)(0x42CF0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A19          *((volatile unsigned int*)(0x42CF0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A20          *((volatile unsigned int*)(0x42CF0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A21          *((volatile unsigned int*)(0x42CF0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A22          *((volatile unsigned int*)(0x42CF0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A23          *((volatile unsigned int*)(0x42CF0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A24          *((volatile unsigned int*)(0x42CF0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A25          *((volatile unsigned int*)(0x42CF0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A26          *((volatile unsigned int*)(0x42CF0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A27          *((volatile unsigned int*)(0x42CF0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A28          *((volatile unsigned int*)(0x42CF0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A29          *((volatile unsigned int*)(0x42CF0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A30          *((volatile unsigned int*)(0x42CF0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A31          *((volatile unsigned int*)(0x42CF0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A32          *((volatile unsigned int*)(0x42CF0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A33          *((volatile unsigned int*)(0x42CF0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A34          *((volatile unsigned int*)(0x42CF0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A35          *((volatile unsigned int*)(0x42CF0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A36          *((volatile unsigned int*)(0x42CF0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A37          *((volatile unsigned int*)(0x42CF0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A38          *((volatile unsigned int*)(0x42CF0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A39          *((volatile unsigned int*)(0x42CF0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A40          *((volatile unsigned int*)(0x42CF0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A41          *((volatile unsigned int*)(0x42CF0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A42          *((volatile unsigned int*)(0x42CF0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A43          *((volatile unsigned int*)(0x42CF0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A44          *((volatile unsigned int*)(0x42CF0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A45          *((volatile unsigned int*)(0x42CF0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A46          *((volatile unsigned int*)(0x42CF0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A47          *((volatile unsigned int*)(0x42CF0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC0         *((volatile unsigned int*)(0x42CF0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC1         *((volatile unsigned int*)(0x42CF0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC2         *((volatile unsigned int*)(0x42CF0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC3         *((volatile unsigned int*)(0x42CF0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC4         *((volatile unsigned int*)(0x42CF0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC5         *((volatile unsigned int*)(0x42CF0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_SA           *((volatile unsigned int*)(0x42CF0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_AE           *((volatile unsigned int*)(0x42CF0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A0           *((volatile unsigned int*)(0x42CF0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A1           *((volatile unsigned int*)(0x42CF0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A2           *((volatile unsigned int*)(0x42CF0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A3           *((volatile unsigned int*)(0x42CF0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A4           *((volatile unsigned int*)(0x42CF0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A5           *((volatile unsigned int*)(0x42CF0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A6           *((volatile unsigned int*)(0x42CF0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A7           *((volatile unsigned int*)(0x42CF0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A8           *((volatile unsigned int*)(0x42CF0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A9           *((volatile unsigned int*)(0x42CF0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A10          *((volatile unsigned int*)(0x42CF0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A11          *((volatile unsigned int*)(0x42CF0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A12          *((volatile unsigned int*)(0x42CF0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A13          *((volatile unsigned int*)(0x42CF0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A14          *((volatile unsigned int*)(0x42CF0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A15          *((volatile unsigned int*)(0x42CF0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A16          *((volatile unsigned int*)(0x42CF0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A17          *((volatile unsigned int*)(0x42CF0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A18          *((volatile unsigned int*)(0x42CF0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A19          *((volatile unsigned int*)(0x42CF0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A20          *((volatile unsigned int*)(0x42CF0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A21          *((volatile unsigned int*)(0x42CF0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A22          *((volatile unsigned int*)(0x42CF0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A23          *((volatile unsigned int*)(0x42CF0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A24          *((volatile unsigned int*)(0x42CF0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A25          *((volatile unsigned int*)(0x42CF0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A26          *((volatile unsigned int*)(0x42CF0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A27          *((volatile unsigned int*)(0x42CF0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A28          *((volatile unsigned int*)(0x42CF0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A29          *((volatile unsigned int*)(0x42CF0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A30          *((volatile unsigned int*)(0x42CF0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A31          *((volatile unsigned int*)(0x42CF0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A32          *((volatile unsigned int*)(0x42CF0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A33          *((volatile unsigned int*)(0x42CF0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A34          *((volatile unsigned int*)(0x42CF0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A35          *((volatile unsigned int*)(0x42CF0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A36          *((volatile unsigned int*)(0x42CF0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A37          *((volatile unsigned int*)(0x42CF0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A38          *((volatile unsigned int*)(0x42CF0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A39          *((volatile unsigned int*)(0x42CF0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A40          *((volatile unsigned int*)(0x42CF0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A41          *((volatile unsigned int*)(0x42CF0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A42          *((volatile unsigned int*)(0x42CF0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A43          *((volatile unsigned int*)(0x42CF0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A44          *((volatile unsigned int*)(0x42CF0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A45          *((volatile unsigned int*)(0x42CF0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A46          *((volatile unsigned int*)(0x42CF0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A47          *((volatile unsigned int*)(0x42CF0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC0         *((volatile unsigned int*)(0x42CF0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC1         *((volatile unsigned int*)(0x42CF0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC2         *((volatile unsigned int*)(0x42CF0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC3         *((volatile unsigned int*)(0x42CF0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC4         *((volatile unsigned int*)(0x42CF0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC5         *((volatile unsigned int*)(0x42CF0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_SA           *((volatile unsigned int*)(0x42CF0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_AE           *((volatile unsigned int*)(0x42CF0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A0           *((volatile unsigned int*)(0x42CF0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A1           *((volatile unsigned int*)(0x42CF0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A2           *((volatile unsigned int*)(0x42CF0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A3           *((volatile unsigned int*)(0x42CF0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A4           *((volatile unsigned int*)(0x42CF0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A5           *((volatile unsigned int*)(0x42CF0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A6           *((volatile unsigned int*)(0x42CF0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A7           *((volatile unsigned int*)(0x42CF0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A8           *((volatile unsigned int*)(0x42CF0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A9           *((volatile unsigned int*)(0x42CF0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A10          *((volatile unsigned int*)(0x42CF0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A11          *((volatile unsigned int*)(0x42CF0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A12          *((volatile unsigned int*)(0x42CF0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A13          *((volatile unsigned int*)(0x42CF0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A14          *((volatile unsigned int*)(0x42CF0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A15          *((volatile unsigned int*)(0x42CF0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A16          *((volatile unsigned int*)(0x42CF0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A17          *((volatile unsigned int*)(0x42CF0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A18          *((volatile unsigned int*)(0x42CF0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A19          *((volatile unsigned int*)(0x42CF0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A20          *((volatile unsigned int*)(0x42CF0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A21          *((volatile unsigned int*)(0x42CF0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A22          *((volatile unsigned int*)(0x42CF0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A23          *((volatile unsigned int*)(0x42CF0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A24          *((volatile unsigned int*)(0x42CF0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A25          *((volatile unsigned int*)(0x42CF0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A26          *((volatile unsigned int*)(0x42CF0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A27          *((volatile unsigned int*)(0x42CF0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A28          *((volatile unsigned int*)(0x42CF0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A29          *((volatile unsigned int*)(0x42CF0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A30          *((volatile unsigned int*)(0x42CF0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A31          *((volatile unsigned int*)(0x42CF0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A32          *((volatile unsigned int*)(0x42CF0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A33          *((volatile unsigned int*)(0x42CF0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A34          *((volatile unsigned int*)(0x42CF0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A35          *((volatile unsigned int*)(0x42CF0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A36          *((volatile unsigned int*)(0x42CF0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A37          *((volatile unsigned int*)(0x42CF0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A38          *((volatile unsigned int*)(0x42CF0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A39          *((volatile unsigned int*)(0x42CF0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A40          *((volatile unsigned int*)(0x42CF0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A41          *((volatile unsigned int*)(0x42CF0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A42          *((volatile unsigned int*)(0x42CF0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A43          *((volatile unsigned int*)(0x42CF0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A44          *((volatile unsigned int*)(0x42CF0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A45          *((volatile unsigned int*)(0x42CF0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A46          *((volatile unsigned int*)(0x42CF0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A47          *((volatile unsigned int*)(0x42CF0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC0         *((volatile unsigned int*)(0x42CF0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC1         *((volatile unsigned int*)(0x42CF0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC2         *((volatile unsigned int*)(0x42CF0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC3         *((volatile unsigned int*)(0x42CF0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC4         *((volatile unsigned int*)(0x42CF0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC5         *((volatile unsigned int*)(0x42CF0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_SA           *((volatile unsigned int*)(0x42CF0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_AE           *((volatile unsigned int*)(0x42CF0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A0           *((volatile unsigned int*)(0x42CF0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A1           *((volatile unsigned int*)(0x42CF0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A2           *((volatile unsigned int*)(0x42CF0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A3           *((volatile unsigned int*)(0x42CF0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A4           *((volatile unsigned int*)(0x42CF0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A5           *((volatile unsigned int*)(0x42CF0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A6           *((volatile unsigned int*)(0x42CF0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A7           *((volatile unsigned int*)(0x42CF0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A8           *((volatile unsigned int*)(0x42CF0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A9           *((volatile unsigned int*)(0x42CF0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A10          *((volatile unsigned int*)(0x42CF0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A11          *((volatile unsigned int*)(0x42CF0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A12          *((volatile unsigned int*)(0x42CF0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A13          *((volatile unsigned int*)(0x42CF0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A14          *((volatile unsigned int*)(0x42CF0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A15          *((volatile unsigned int*)(0x42CF0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A16          *((volatile unsigned int*)(0x42CF0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A17          *((volatile unsigned int*)(0x42CF0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A18          *((volatile unsigned int*)(0x42CF0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A19          *((volatile unsigned int*)(0x42CF0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A20          *((volatile unsigned int*)(0x42CF0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A21          *((volatile unsigned int*)(0x42CF0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A22          *((volatile unsigned int*)(0x42CF0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A23          *((volatile unsigned int*)(0x42CF0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A24          *((volatile unsigned int*)(0x42CF0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A25          *((volatile unsigned int*)(0x42CF0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A26          *((volatile unsigned int*)(0x42CF0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A27          *((volatile unsigned int*)(0x42CF0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A28          *((volatile unsigned int*)(0x42CF0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A29          *((volatile unsigned int*)(0x42CF0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A30          *((volatile unsigned int*)(0x42CF0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A31          *((volatile unsigned int*)(0x42CF0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A32          *((volatile unsigned int*)(0x42CF0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A33          *((volatile unsigned int*)(0x42CF0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A34          *((volatile unsigned int*)(0x42CF0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A35          *((volatile unsigned int*)(0x42CF0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A36          *((volatile unsigned int*)(0x42CF0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A37          *((volatile unsigned int*)(0x42CF0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A38          *((volatile unsigned int*)(0x42CF0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A39          *((volatile unsigned int*)(0x42CF0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A40          *((volatile unsigned int*)(0x42CF0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A41          *((volatile unsigned int*)(0x42CF0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A42          *((volatile unsigned int*)(0x42CF0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A43          *((volatile unsigned int*)(0x42CF0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A44          *((volatile unsigned int*)(0x42CF0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A45          *((volatile unsigned int*)(0x42CF0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A46          *((volatile unsigned int*)(0x42CF0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A47          *((volatile unsigned int*)(0x42CF0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC0         *((volatile unsigned int*)(0x42CF0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC1         *((volatile unsigned int*)(0x42CF0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC2         *((volatile unsigned int*)(0x42CF0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC3         *((volatile unsigned int*)(0x42CF0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC4         *((volatile unsigned int*)(0x42CF0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC5         *((volatile unsigned int*)(0x42CF0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_SA           *((volatile unsigned int*)(0x42CF0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_AE           *((volatile unsigned int*)(0x42CF0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A0           *((volatile unsigned int*)(0x42CF0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A1           *((volatile unsigned int*)(0x42CF0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A2           *((volatile unsigned int*)(0x42CF0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A3           *((volatile unsigned int*)(0x42CF0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A4           *((volatile unsigned int*)(0x42CF0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A5           *((volatile unsigned int*)(0x42CF0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A6           *((volatile unsigned int*)(0x42CF0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A7           *((volatile unsigned int*)(0x42CF0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A8           *((volatile unsigned int*)(0x42CF0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A9           *((volatile unsigned int*)(0x42CF0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A10          *((volatile unsigned int*)(0x42CF0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A11          *((volatile unsigned int*)(0x42CF0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A12          *((volatile unsigned int*)(0x42CF0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A13          *((volatile unsigned int*)(0x42CF0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A14          *((volatile unsigned int*)(0x42CF0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A15          *((volatile unsigned int*)(0x42CF0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A16          *((volatile unsigned int*)(0x42CF0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A17          *((volatile unsigned int*)(0x42CF0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A18          *((volatile unsigned int*)(0x42CF0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A19          *((volatile unsigned int*)(0x42CF0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A20          *((volatile unsigned int*)(0x42CF0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A21          *((volatile unsigned int*)(0x42CF0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A22          *((volatile unsigned int*)(0x42CF0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A23          *((volatile unsigned int*)(0x42CF0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A24          *((volatile unsigned int*)(0x42CF0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A25          *((volatile unsigned int*)(0x42CF0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A26          *((volatile unsigned int*)(0x42CF0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A27          *((volatile unsigned int*)(0x42CF0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A28          *((volatile unsigned int*)(0x42CF0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A29          *((volatile unsigned int*)(0x42CF0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A30          *((volatile unsigned int*)(0x42CF0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A31          *((volatile unsigned int*)(0x42CF0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A32          *((volatile unsigned int*)(0x42CF0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A33          *((volatile unsigned int*)(0x42CF0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A34          *((volatile unsigned int*)(0x42CF0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A35          *((volatile unsigned int*)(0x42CF0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A36          *((volatile unsigned int*)(0x42CF0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A37          *((volatile unsigned int*)(0x42CF0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A38          *((volatile unsigned int*)(0x42CF0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A39          *((volatile unsigned int*)(0x42CF0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A40          *((volatile unsigned int*)(0x42CF0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A41          *((volatile unsigned int*)(0x42CF0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A42          *((volatile unsigned int*)(0x42CF0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A43          *((volatile unsigned int*)(0x42CF0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A44          *((volatile unsigned int*)(0x42CF0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A45          *((volatile unsigned int*)(0x42CF0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A46          *((volatile unsigned int*)(0x42CF0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A47          *((volatile unsigned int*)(0x42CF0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC0         *((volatile unsigned int*)(0x42CF0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC1         *((volatile unsigned int*)(0x42CF0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC2         *((volatile unsigned int*)(0x42CF0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC3         *((volatile unsigned int*)(0x42CF0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC4         *((volatile unsigned int*)(0x42CF0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC5         *((volatile unsigned int*)(0x42CF0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_SA           *((volatile unsigned int*)(0x42CF0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_AE           *((volatile unsigned int*)(0x42CF0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A0           *((volatile unsigned int*)(0x42CF0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A1           *((volatile unsigned int*)(0x42CF0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A2           *((volatile unsigned int*)(0x42CF0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A3           *((volatile unsigned int*)(0x42CF0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A4           *((volatile unsigned int*)(0x42CF0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A5           *((volatile unsigned int*)(0x42CF0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A6           *((volatile unsigned int*)(0x42CF0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A7           *((volatile unsigned int*)(0x42CF0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A8           *((volatile unsigned int*)(0x42CF0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A9           *((volatile unsigned int*)(0x42CF0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A10          *((volatile unsigned int*)(0x42CF0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A11          *((volatile unsigned int*)(0x42CF0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A12          *((volatile unsigned int*)(0x42CF0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A13          *((volatile unsigned int*)(0x42CF0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A14          *((volatile unsigned int*)(0x42CF0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A15          *((volatile unsigned int*)(0x42CF0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A16          *((volatile unsigned int*)(0x42CF0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A17          *((volatile unsigned int*)(0x42CF0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A18          *((volatile unsigned int*)(0x42CF0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A19          *((volatile unsigned int*)(0x42CF0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A20          *((volatile unsigned int*)(0x42CF0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A21          *((volatile unsigned int*)(0x42CF0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A22          *((volatile unsigned int*)(0x42CF0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A23          *((volatile unsigned int*)(0x42CF0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A24          *((volatile unsigned int*)(0x42CF0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A25          *((volatile unsigned int*)(0x42CF0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A26          *((volatile unsigned int*)(0x42CF0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A27          *((volatile unsigned int*)(0x42CF0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A28          *((volatile unsigned int*)(0x42CF0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A29          *((volatile unsigned int*)(0x42CF0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A30          *((volatile unsigned int*)(0x42CF0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A31          *((volatile unsigned int*)(0x42CF0FFCUL))
+#define bFM3_ETHERNET_MAC1_BMR_SWR             *((volatile unsigned int*)(0x42D00000UL))
+#define bFM3_ETHERNET_MAC1_BMR_DA              *((volatile unsigned int*)(0x42D00004UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL0            *((volatile unsigned int*)(0x42D00008UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL1            *((volatile unsigned int*)(0x42D0000CUL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL2            *((volatile unsigned int*)(0x42D00010UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL3            *((volatile unsigned int*)(0x42D00014UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL4            *((volatile unsigned int*)(0x42D00018UL))
+#define bFM3_ETHERNET_MAC1_BMR_ATDS            *((volatile unsigned int*)(0x42D0001CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL0            *((volatile unsigned int*)(0x42D00020UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL1            *((volatile unsigned int*)(0x42D00024UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL2            *((volatile unsigned int*)(0x42D00028UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL3            *((volatile unsigned int*)(0x42D0002CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL4            *((volatile unsigned int*)(0x42D00030UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL5            *((volatile unsigned int*)(0x42D00034UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR0             *((volatile unsigned int*)(0x42D00038UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR1             *((volatile unsigned int*)(0x42D0003CUL))
+#define bFM3_ETHERNET_MAC1_BMR_FB              *((volatile unsigned int*)(0x42D00040UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL0           *((volatile unsigned int*)(0x42D00044UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL1           *((volatile unsigned int*)(0x42D00048UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL2           *((volatile unsigned int*)(0x42D0004CUL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL3           *((volatile unsigned int*)(0x42D00050UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL4           *((volatile unsigned int*)(0x42D00054UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL5           *((volatile unsigned int*)(0x42D00058UL))
+#define bFM3_ETHERNET_MAC1_BMR_USP             *((volatile unsigned int*)(0x42D0005CUL))
+#define bFM3_ETHERNET_MAC1_BMR_8XPBL           *((volatile unsigned int*)(0x42D00060UL))
+#define bFM3_ETHERNET_MAC1_BMR_AAL             *((volatile unsigned int*)(0x42D00064UL))
+#define bFM3_ETHERNET_MAC1_BMR_MB              *((volatile unsigned int*)(0x42D00068UL))
+#define bFM3_ETHERNET_MAC1_BMR_TXPR            *((volatile unsigned int*)(0x42D0006CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD0           *((volatile unsigned int*)(0x42D00080UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD1           *((volatile unsigned int*)(0x42D00084UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD2           *((volatile unsigned int*)(0x42D00088UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD3           *((volatile unsigned int*)(0x42D0008CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD4           *((volatile unsigned int*)(0x42D00090UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD5           *((volatile unsigned int*)(0x42D00094UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD6           *((volatile unsigned int*)(0x42D00098UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD7           *((volatile unsigned int*)(0x42D0009CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD8           *((volatile unsigned int*)(0x42D000A0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD9           *((volatile unsigned int*)(0x42D000A4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD10          *((volatile unsigned int*)(0x42D000A8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD11          *((volatile unsigned int*)(0x42D000ACUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD12          *((volatile unsigned int*)(0x42D000B0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD13          *((volatile unsigned int*)(0x42D000B4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD14          *((volatile unsigned int*)(0x42D000B8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD15          *((volatile unsigned int*)(0x42D000BCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD16          *((volatile unsigned int*)(0x42D000C0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD17          *((volatile unsigned int*)(0x42D000C4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD18          *((volatile unsigned int*)(0x42D000C8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD19          *((volatile unsigned int*)(0x42D000CCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD20          *((volatile unsigned int*)(0x42D000D0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD21          *((volatile unsigned int*)(0x42D000D4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD22          *((volatile unsigned int*)(0x42D000D8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD23          *((volatile unsigned int*)(0x42D000DCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD24          *((volatile unsigned int*)(0x42D000E0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD25          *((volatile unsigned int*)(0x42D000E4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD26          *((volatile unsigned int*)(0x42D000E8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD27          *((volatile unsigned int*)(0x42D000ECUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD28          *((volatile unsigned int*)(0x42D000F0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD29          *((volatile unsigned int*)(0x42D000F4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD30          *((volatile unsigned int*)(0x42D000F8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD31          *((volatile unsigned int*)(0x42D000FCUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD0           *((volatile unsigned int*)(0x42D00100UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD1           *((volatile unsigned int*)(0x42D00104UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD2           *((volatile unsigned int*)(0x42D00108UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD3           *((volatile unsigned int*)(0x42D0010CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD4           *((volatile unsigned int*)(0x42D00110UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD5           *((volatile unsigned int*)(0x42D00114UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD6           *((volatile unsigned int*)(0x42D00118UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD7           *((volatile unsigned int*)(0x42D0011CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD8           *((volatile unsigned int*)(0x42D00120UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD9           *((volatile unsigned int*)(0x42D00124UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD10          *((volatile unsigned int*)(0x42D00128UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD11          *((volatile unsigned int*)(0x42D0012CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD12          *((volatile unsigned int*)(0x42D00130UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD13          *((volatile unsigned int*)(0x42D00134UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD14          *((volatile unsigned int*)(0x42D00138UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD15          *((volatile unsigned int*)(0x42D0013CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD16          *((volatile unsigned int*)(0x42D00140UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD17          *((volatile unsigned int*)(0x42D00144UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD18          *((volatile unsigned int*)(0x42D00148UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD19          *((volatile unsigned int*)(0x42D0014CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD20          *((volatile unsigned int*)(0x42D00150UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD21          *((volatile unsigned int*)(0x42D00154UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD22          *((volatile unsigned int*)(0x42D00158UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD23          *((volatile unsigned int*)(0x42D0015CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD24          *((volatile unsigned int*)(0x42D00160UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD25          *((volatile unsigned int*)(0x42D00164UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD26          *((volatile unsigned int*)(0x42D00168UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD27          *((volatile unsigned int*)(0x42D0016CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD28          *((volatile unsigned int*)(0x42D00170UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD29          *((volatile unsigned int*)(0x42D00174UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD30          *((volatile unsigned int*)(0x42D00178UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD31          *((volatile unsigned int*)(0x42D0017CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL2          *((volatile unsigned int*)(0x42D00188UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL3          *((volatile unsigned int*)(0x42D0018CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL4          *((volatile unsigned int*)(0x42D00190UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL5          *((volatile unsigned int*)(0x42D00194UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL6          *((volatile unsigned int*)(0x42D00198UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL7          *((volatile unsigned int*)(0x42D0019CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL8          *((volatile unsigned int*)(0x42D001A0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL9          *((volatile unsigned int*)(0x42D001A4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL10         *((volatile unsigned int*)(0x42D001A8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL11         *((volatile unsigned int*)(0x42D001ACUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL12         *((volatile unsigned int*)(0x42D001B0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL13         *((volatile unsigned int*)(0x42D001B4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL14         *((volatile unsigned int*)(0x42D001B8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL15         *((volatile unsigned int*)(0x42D001BCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL16         *((volatile unsigned int*)(0x42D001C0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL17         *((volatile unsigned int*)(0x42D001C4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL18         *((volatile unsigned int*)(0x42D001C8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL19         *((volatile unsigned int*)(0x42D001CCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL20         *((volatile unsigned int*)(0x42D001D0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL21         *((volatile unsigned int*)(0x42D001D4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL22         *((volatile unsigned int*)(0x42D001D8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL23         *((volatile unsigned int*)(0x42D001DCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL24         *((volatile unsigned int*)(0x42D001E0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL25         *((volatile unsigned int*)(0x42D001E4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL26         *((volatile unsigned int*)(0x42D001E8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL27         *((volatile unsigned int*)(0x42D001ECUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL28         *((volatile unsigned int*)(0x42D001F0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL29         *((volatile unsigned int*)(0x42D001F4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL30         *((volatile unsigned int*)(0x42D001F8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL31         *((volatile unsigned int*)(0x42D001FCUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL2          *((volatile unsigned int*)(0x42D00208UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL3          *((volatile unsigned int*)(0x42D0020CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL4          *((volatile unsigned int*)(0x42D00210UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL5          *((volatile unsigned int*)(0x42D00214UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL6          *((volatile unsigned int*)(0x42D00218UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL7          *((volatile unsigned int*)(0x42D0021CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL8          *((volatile unsigned int*)(0x42D00220UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL9          *((volatile unsigned int*)(0x42D00224UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL10         *((volatile unsigned int*)(0x42D00228UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL11         *((volatile unsigned int*)(0x42D0022CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL12         *((volatile unsigned int*)(0x42D00230UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL13         *((volatile unsigned int*)(0x42D00234UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL14         *((volatile unsigned int*)(0x42D00238UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL15         *((volatile unsigned int*)(0x42D0023CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL16         *((volatile unsigned int*)(0x42D00240UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL17         *((volatile unsigned int*)(0x42D00244UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL18         *((volatile unsigned int*)(0x42D00248UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL19         *((volatile unsigned int*)(0x42D0024CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL20         *((volatile unsigned int*)(0x42D00250UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL21         *((volatile unsigned int*)(0x42D00254UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL22         *((volatile unsigned int*)(0x42D00258UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL23         *((volatile unsigned int*)(0x42D0025CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL24         *((volatile unsigned int*)(0x42D00260UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL25         *((volatile unsigned int*)(0x42D00264UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL26         *((volatile unsigned int*)(0x42D00268UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL27         *((volatile unsigned int*)(0x42D0026CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL28         *((volatile unsigned int*)(0x42D00270UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL29         *((volatile unsigned int*)(0x42D00274UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL30         *((volatile unsigned int*)(0x42D00278UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL31         *((volatile unsigned int*)(0x42D0027CUL))
+#define bFM3_ETHERNET_MAC1_SR_TI               *((volatile unsigned int*)(0x42D00280UL))
+#define bFM3_ETHERNET_MAC1_SR_TPS              *((volatile unsigned int*)(0x42D00284UL))
+#define bFM3_ETHERNET_MAC1_SR_TU               *((volatile unsigned int*)(0x42D00288UL))
+#define bFM3_ETHERNET_MAC1_SR_TJT              *((volatile unsigned int*)(0x42D0028CUL))
+#define bFM3_ETHERNET_MAC1_SR_OVF              *((volatile unsigned int*)(0x42D00290UL))
+#define bFM3_ETHERNET_MAC1_SR_UNF              *((volatile unsigned int*)(0x42D00294UL))
+#define bFM3_ETHERNET_MAC1_SR_RI               *((volatile unsigned int*)(0x42D00298UL))
+#define bFM3_ETHERNET_MAC1_SR_RU               *((volatile unsigned int*)(0x42D0029CUL))
+#define bFM3_ETHERNET_MAC1_SR_RPS              *((volatile unsigned int*)(0x42D002A0UL))
+#define bFM3_ETHERNET_MAC1_SR_RWT              *((volatile unsigned int*)(0x42D002A4UL))
+#define bFM3_ETHERNET_MAC1_SR_ETI              *((volatile unsigned int*)(0x42D002A8UL))
+#define bFM3_ETHERNET_MAC1_SR_FBI              *((volatile unsigned int*)(0x42D002B4UL))
+#define bFM3_ETHERNET_MAC1_SR_ERI              *((volatile unsigned int*)(0x42D002B8UL))
+#define bFM3_ETHERNET_MAC1_SR_AIS              *((volatile unsigned int*)(0x42D002BCUL))
+#define bFM3_ETHERNET_MAC1_SR_NIS              *((volatile unsigned int*)(0x42D002C0UL))
+#define bFM3_ETHERNET_MAC1_SR_RS0              *((volatile unsigned int*)(0x42D002C4UL))
+#define bFM3_ETHERNET_MAC1_SR_RS1              *((volatile unsigned int*)(0x42D002C8UL))
+#define bFM3_ETHERNET_MAC1_SR_RS2              *((volatile unsigned int*)(0x42D002CCUL))
+#define bFM3_ETHERNET_MAC1_SR_TS0              *((volatile unsigned int*)(0x42D002D0UL))
+#define bFM3_ETHERNET_MAC1_SR_TS1              *((volatile unsigned int*)(0x42D002D4UL))
+#define bFM3_ETHERNET_MAC1_SR_TS2              *((volatile unsigned int*)(0x42D002D8UL))
+#define bFM3_ETHERNET_MAC1_SR_EB0              *((volatile unsigned int*)(0x42D002DCUL))
+#define bFM3_ETHERNET_MAC1_SR_EB1              *((volatile unsigned int*)(0x42D002E0UL))
+#define bFM3_ETHERNET_MAC1_SR_EB2              *((volatile unsigned int*)(0x42D002E4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLI              *((volatile unsigned int*)(0x42D002E8UL))
+#define bFM3_ETHERNET_MAC1_SR_GMI              *((volatile unsigned int*)(0x42D002ECUL))
+#define bFM3_ETHERNET_MAC1_SR_GPI              *((volatile unsigned int*)(0x42D002F0UL))
+#define bFM3_ETHERNET_MAC1_SR_TTI              *((volatile unsigned int*)(0x42D002F4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLPII            *((volatile unsigned int*)(0x42D002F8UL))
+#define bFM3_ETHERNET_MAC1_OMR_SR              *((volatile unsigned int*)(0x42D00304UL))
+#define bFM3_ETHERNET_MAC1_OMR_OSF             *((volatile unsigned int*)(0x42D00308UL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC0            *((volatile unsigned int*)(0x42D0030CUL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC1            *((volatile unsigned int*)(0x42D00310UL))
+#define bFM3_ETHERNET_MAC1_OMR_FUF             *((volatile unsigned int*)(0x42D00318UL))
+#define bFM3_ETHERNET_MAC1_OMR_FEF             *((volatile unsigned int*)(0x42D0031CUL))
+#define bFM3_ETHERNET_MAC1_OMR_ST              *((volatile unsigned int*)(0x42D00334UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC0            *((volatile unsigned int*)(0x42D00338UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC1            *((volatile unsigned int*)(0x42D0033CUL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC2            *((volatile unsigned int*)(0x42D00340UL))
+#define bFM3_ETHERNET_MAC1_OMR_FTF             *((volatile unsigned int*)(0x42D00350UL))
+#define bFM3_ETHERNET_MAC1_OMR_TSF             *((volatile unsigned int*)(0x42D00354UL))
+#define bFM3_ETHERNET_MAC1_OMR_DFF             *((volatile unsigned int*)(0x42D00360UL))
+#define bFM3_ETHERNET_MAC1_OMR_RSF             *((volatile unsigned int*)(0x42D00364UL))
+#define bFM3_ETHERNET_MAC1_OMR_DT              *((volatile unsigned int*)(0x42D00368UL))
+#define bFM3_ETHERNET_MAC1_IER_TIE             *((volatile unsigned int*)(0x42D00380UL))
+#define bFM3_ETHERNET_MAC1_IER_TSE             *((volatile unsigned int*)(0x42D00384UL))
+#define bFM3_ETHERNET_MAC1_IER_TUE             *((volatile unsigned int*)(0x42D00388UL))
+#define bFM3_ETHERNET_MAC1_IER_TJE             *((volatile unsigned int*)(0x42D0038CUL))
+#define bFM3_ETHERNET_MAC1_IER_OVE             *((volatile unsigned int*)(0x42D00390UL))
+#define bFM3_ETHERNET_MAC1_IER_UNE             *((volatile unsigned int*)(0x42D00394UL))
+#define bFM3_ETHERNET_MAC1_IER_RIE             *((volatile unsigned int*)(0x42D00398UL))
+#define bFM3_ETHERNET_MAC1_IER_RUE             *((volatile unsigned int*)(0x42D0039CUL))
+#define bFM3_ETHERNET_MAC1_IER_RSE             *((volatile unsigned int*)(0x42D003A0UL))
+#define bFM3_ETHERNET_MAC1_IER_RWE             *((volatile unsigned int*)(0x42D003A4UL))
+#define bFM3_ETHERNET_MAC1_IER_ETE             *((volatile unsigned int*)(0x42D003A8UL))
+#define bFM3_ETHERNET_MAC1_IER_FBE             *((volatile unsigned int*)(0x42D003B4UL))
+#define bFM3_ETHERNET_MAC1_IER_ERE             *((volatile unsigned int*)(0x42D003B8UL))
+#define bFM3_ETHERNET_MAC1_IER_AIE             *((volatile unsigned int*)(0x42D003BCUL))
+#define bFM3_ETHERNET_MAC1_IER_NIE             *((volatile unsigned int*)(0x42D003C0UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42D00400UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42D00404UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42D00408UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42D0040CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42D00410UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42D00414UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42D00418UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42D0041CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42D00420UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42D00424UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42D00428UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42D0042CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42D00430UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42D00434UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42D00438UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42D0043CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42D00440UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42D00444UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42D00448UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42D0044CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42D00450UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42D00454UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42D00458UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42D0045CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42D00460UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42D00464UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42D00468UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42D0046CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42D00470UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0         *((volatile unsigned int*)(0x42D00480UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1         *((volatile unsigned int*)(0x42D00484UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2         *((volatile unsigned int*)(0x42D00488UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3         *((volatile unsigned int*)(0x42D0048CUL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4         *((volatile unsigned int*)(0x42D00490UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5         *((volatile unsigned int*)(0x42D00494UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6         *((volatile unsigned int*)(0x42D00498UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7         *((volatile unsigned int*)(0x42D0049CUL))
+#define bFM3_ETHERNET_MAC1_AHBSR_AHBS          *((volatile unsigned int*)(0x42D00580UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42D00900UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42D00904UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42D00908UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42D0090CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42D00910UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42D00914UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42D00918UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42D0091CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42D00920UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42D00924UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42D00928UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42D0092CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42D00930UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42D00934UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42D00938UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42D0093CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42D00940UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42D00944UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42D00948UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42D0094CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42D00950UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42D00954UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42D00958UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42D0095CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42D00960UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42D00964UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42D00968UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42D0096CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42D00970UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42D00974UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42D00978UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42D0097CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42D00980UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42D00984UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42D00988UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42D0098CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42D00990UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42D00994UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42D00998UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42D0099CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42D009A0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42D009A4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42D009A8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42D009ACUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42D009B0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42D009B4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42D009B8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42D009BCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42D009C0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42D009C4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42D009C8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42D009CCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42D009D0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42D009D4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42D009D8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42D009DCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42D009E0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42D009E4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42D009E8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42D009ECUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42D009F0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42D009F4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42D009F8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42D009FCUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42D00A00UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42D00A04UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42D00A08UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42D00A0CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42D00A10UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42D00A14UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42D00A18UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42D00A1CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42D00A20UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42D00A24UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42D00A28UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42D00A2CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42D00A30UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42D00A34UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42D00A38UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42D00A3CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42D00A40UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42D00A44UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42D00A48UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42D00A4CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42D00A50UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42D00A54UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42D00A58UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42D00A5CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42D00A60UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42D00A64UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42D00A68UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42D00A6CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42D00A70UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42D00A74UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42D00A78UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42D00A7CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42D00A80UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42D00A84UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42D00A88UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42D00A8CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42D00A90UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42D00A94UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42D00A98UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42D00A9CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42D00AA0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42D00AA4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42D00AA8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42D00AACUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42D00AB0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42D00AB4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42D00AB8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42D00ABCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42D00AC0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42D00AC4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42D00AC8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42D00ACCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42D00AD0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42D00AD4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42D00AD8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42D00ADCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42D00AE0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42D00AE4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42D00AE8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42D00AECUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42D00AF0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42D00AF4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42D00AF8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42D00AFCUL))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MB9BF618S_H_ */
+
diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h
new file mode 100644
index 0000000000..b75c77ba6b
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h
@@ -0,0 +1,29338 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/*                                                                      */
+/*  Header File for Device MB9B610T                                     */
+/*  Version V1.2                                                        */
+/*  Date    2012-02-23                                                  */
+/*                                                                      */
+/************************************************************************/
+
+/******************************************************************************
+ * History
+ * Date       Ver Description
+ * 2011-08-04 1.0 Initial
+ * 2011-10-04 1.1 Added FBFCR register
+ *                Removed the following bits from the bit fields
+ *                - TMD bits of WFSAxx register in MFT
+ *                - MD bits of PPGCx register in PPG
+ *                - FMD bits of TMCR register in BT
+ *                - MD bits of SMR register in MFS
+ * 2012-02-23 1.2 Added the following bits to the bit fields
+ *                - TMD bits of WFSAxx register in MFT
+ *                - MD bits of PPGCx register in PPG
+ *                - FMD bits of TMCR register in BT
+ *                - MD bits of SMR register in MFS
+ *
+ ******************************************************************************/
+
+#ifndef _MB9B610T_H_
+#define _MB9B610T_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+
+/******************************************************************************
+ * Configuration of the Cortex-M3 Processor and Core Peripherals
+ ******************************************************************************/
+#define __MPU_PRESENT           1 /* FM3 provide an MPU                           */
+#define __NVIC_PRIO_BITS        4 /* FM3 uses 4 Bits for the Priority Levels      */
+#define __Vendor_SysTickConfig  0 /* Set to 1 if different SysTick Config is used */
+
+
+/******************************************************************************
+ * Interrupt Number Definition
+ ******************************************************************************/
+typedef enum IRQn
+{
+    NMI_IRQn          = -14, /*  2 Non Maskable      */
+    HardFault_IRQn    = -13, /*  3 Hard Fault        */
+    MemManage_IRQn    = -12, /*  4 Memory Management */
+    BusFault_IRQn     = -11, /*  5 Bus Fault         */
+    UsageFault_IRQn   = -10, /*  6 Usage Fault       */
+    SVC_IRQn          = -5,  /* 11 SV Call           */
+    DebugMonitor_IRQn = -4,  /* 12 Debug Monitor     */
+    PendSV_IRQn       = -2,  /* 14 Pend SV           */
+    SysTick_IRQn      = -1,  /* 15 System Tick       */
+
+    CSV_IRQn          =  0, /* Clock Super Visor                             */
+    SWDT_IRQn         =  1, /* Software Watchdog Timer                       */
+    LVD_IRQn          =  2, /* Low Voltage Detector                          */
+    WFG_IRQn          =  3, /* Wave Form Generator                           */
+    EXINT0_7_IRQn     =  4, /* External Interrupt Request ch.0 to ch.7       */
+    EXINT8_31_IRQn    =  5, /* External Interrupt Request ch.8 to ch.31      */
+    DTIM_QDU_IRQn     =  6, /* Dual Timer / Quad Decoder                     */
+    MFS0RX_IRQn       =  7, /* MultiFunction Serial Reception ch.0           */
+    MFS0TX_IRQn       =  8, /* MultiFunction Serial Transmission ch.0        */
+    MFS1RX_IRQn       =  9, /* MultiFunction Serial Reception ch.1           */
+    MFS1TX_IRQn       = 10, /* MultiFunction Serial Transmission ch.1        */
+    MFS2RX_IRQn       = 11, /* MultiFunction Serial Reception ch.2           */
+    MFS2TX_IRQn       = 12, /* MultiFunction Serial Transmission ch.2        */
+    MFS3RX_IRQn       = 13, /* MultiFunction Serial Reception ch.3           */
+    MFS3TX_IRQn       = 14, /* MultiFunction Serial Transmission ch.3        */
+    MFS4RX_IRQn       = 15, /* MultiFunction Serial Reception ch.4           */
+    MFS4TX_IRQn       = 16, /* MultiFunction Serial Transmission ch.4        */
+    MFS5RX_IRQn       = 17, /* MultiFunction Serial Reception ch.5           */
+    MFS5TX_IRQn       = 18, /* MultiFunction Serial Transmission ch.5        */
+    MFS6RX_IRQn       = 19, /* MultiFunction Serial Reception ch.6           */
+    MFS6TX_IRQn       = 20, /* MultiFunction Serial Transmission ch.6        */
+    MFS7RX_IRQn       = 21, /* MultiFunction Serial Reception ch.7           */
+    MFS7TX_IRQn       = 22, /* MultiFunction Serial Transmission ch.7        */
+    PPG_IRQn          = 23, /* PPG                                           */
+    OSC_PLL_WC_IRQn   = 24, /* OSC / PLL / Watch Counter                     */
+    ADC0_IRQn         = 25, /* ADC0                                          */
+    ADC1_IRQn         = 26, /* ADC1                                          */
+    ADC2_IRQn         = 27, /* ADC2                                          */
+    FRTIM_IRQn        = 28, /* Free-run Timer                                */
+    INCAP_IRQn        = 29, /* Input Capture                                 */
+    OUTCOMP_IRQn      = 30, /* Output Compare                                */
+    BTIM0_7_IRQn      = 31, /* Base Timer ch.0 to ch.7                       */
+    ETHER_MAC0_IRQn   = 32, /* Ethernet MAC ch.0                             */
+    ETHER_MAC1_IRQn   = 33, /* Ethernet MAC ch.1                             */
+    USB0F_IRQn        = 34, /* USB Function ch.0                             */
+    USB0F_USB0H_IRQn  = 35, /* USB Function ch.0 / USB Host ch.0             */
+    USB1F_IRQn        = 36, /* USB Function ch.1                             */
+    USB1F_USB1H_IRQn  = 37, /* USB Function ch.1 / USB Host ch.1             */
+    DMAC0_IRQn        = 38, /* DMAC ch.0                                     */
+    DMAC1_IRQn        = 39, /* DMAC ch.1                                     */
+    DMAC2_IRQn        = 40, /* DMAC ch.2                                     */
+    DMAC3_IRQn        = 41, /* DMAC ch.3                                     */
+    DMAC4_IRQn        = 42, /* DMAC ch.4                                     */
+    DMAC5_IRQn        = 43, /* DMAC ch.5                                     */
+    DMAC6_IRQn        = 44, /* DMAC ch.6                                     */
+    DMAC7_IRQn        = 45, /* DMAC ch.7                                     */
+    BTIM8_15_IRQn     = 46  /* Base Timer ch.8 to ch.15                      */
+    /* Reserved       = 47                                                   */
+} IRQn_Type;
+
+
+#include <core_cm3.h>
+#include "system_mb9bf61x.h"
+#include <stdint.h>
+
+#define SUCCESS  0
+#define ERROR    -1
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/******************************************************************************
+ * Peripheral register bit fields
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash_IF_MODULE register bit fields */
+typedef struct stc_flash_if_faszr_field
+{
+  __IO uint32_t ASZ0       : 1;
+  __IO uint32_t ASZ1       : 1;
+} stc_flash_if_faszr_field_t;
+
+typedef struct stc_flash_if_frwtr_field
+{
+  __IO uint32_t RWT0       : 1;
+  __IO uint32_t RWT1       : 1;
+} stc_flash_if_frwtr_field_t;
+
+typedef struct stc_flash_if_fstr_field
+{
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t HNG        : 1;
+  __IO uint32_t EER        : 1;
+} stc_flash_if_fstr_field_t;
+
+typedef struct stc_flash_if_fsyndn_field
+{
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+} stc_flash_if_fsyndn_field_t;
+
+typedef struct stc_flash_if_fbfcr_field
+{
+  __IO uint32_t BE         : 1;
+  __IO uint32_t BS         : 1;
+} stc_flash_if_fbfcr_field_t;
+
+typedef struct stc_flash_if_crtrmm_field
+{
+  __IO uint32_t TRMM0      : 1;
+  __IO uint32_t TRMM1      : 1;
+  __IO uint32_t TRMM2      : 1;
+  __IO uint32_t TRMM3      : 1;
+  __IO uint32_t TRMM4      : 1;
+  __IO uint32_t TRMM5      : 1;
+  __IO uint32_t TRMM6      : 1;
+  __IO uint32_t TRMM7      : 1;
+  __IO uint32_t TRMM8      : 1;
+  __IO uint32_t TRMM9      : 1;
+} stc_flash_if_crtrmm_field_t;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock_Reset_MODULE register bit fields */
+typedef struct stc_crg_scm_ctl_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MOSCE      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SOSCE      : 1;
+  __IO  uint8_t PLLE       : 1;
+  __IO  uint8_t RCS0       : 1;
+  __IO  uint8_t RCS1       : 1;
+  __IO  uint8_t RCS2       : 1;
+} stc_crg_scm_ctl_field_t;
+
+typedef struct stc_crg_scm_str_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MORDY      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SORDY      : 1;
+  __IO  uint8_t PLRDY      : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t RCM2       : 1;
+} stc_crg_scm_str_field_t;
+
+typedef struct stc_crg_rst_str_field
+{
+  __IO uint16_t PONR       : 1;
+  __IO uint16_t INITX      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SWDT       : 1;
+  __IO uint16_t HWDT       : 1;
+  __IO uint16_t CSVR       : 1;
+  __IO uint16_t FCSR       : 1;
+  __IO uint16_t SRST       : 1;
+} stc_crg_rst_str_field_t;
+
+typedef struct stc_crg_bsc_psr_field
+{
+  __IO  uint8_t BSR0       : 1;
+  __IO  uint8_t BSR1       : 1;
+  __IO  uint8_t BSR2       : 1;
+} stc_crg_bsc_psr_field_t;
+
+typedef struct stc_crg_apbc0_psr_field
+{
+  __IO  uint8_t APBC00     : 1;
+  __IO  uint8_t APBC01     : 1;
+} stc_crg_apbc0_psr_field_t;
+
+typedef struct stc_crg_apbc1_psr_field
+{
+  __IO  uint8_t APBC10     : 1;
+  __IO  uint8_t APBC11     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC1RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC1EN    : 1;
+} stc_crg_apbc1_psr_field_t;
+
+typedef struct stc_crg_apbc2_psr_field
+{
+  __IO  uint8_t APBC20     : 1;
+  __IO  uint8_t APBC21     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC2RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC2EN    : 1;
+} stc_crg_apbc2_psr_field_t;
+
+typedef struct stc_crg_swc_psr_field
+{
+  __IO  uint8_t SWDS0      : 1;
+  __IO  uint8_t SWDS1      : 1;
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t TESTB      : 1;
+} stc_crg_swc_psr_field_t;
+
+typedef struct stc_crg_ttc_psr_field
+{
+  __IO  uint8_t TTC0       : 1;
+  __IO  uint8_t TTC1       : 1;
+} stc_crg_ttc_psr_field_t;
+
+typedef struct stc_crg_csw_tmr_field
+{
+  __IO  uint8_t MOWT0      : 1;
+  __IO  uint8_t MOWT1      : 1;
+  __IO  uint8_t MOWT2      : 1;
+  __IO  uint8_t MOWT3      : 1;
+  __IO  uint8_t SOWT0      : 1;
+  __IO  uint8_t SOWT1      : 1;
+  __IO  uint8_t SOWT2      : 1;
+} stc_crg_csw_tmr_field_t;
+
+typedef struct stc_crg_psw_tmr_field
+{
+  __IO  uint8_t POWT0      : 1;
+  __IO  uint8_t POWT1      : 1;
+  __IO  uint8_t POWT2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t PINC       : 1;
+} stc_crg_psw_tmr_field_t;
+
+typedef struct stc_crg_pll_ctl1_field
+{
+  __IO  uint8_t PLLM0      : 1;
+  __IO  uint8_t PLLM1      : 1;
+  __IO  uint8_t PLLM2      : 1;
+  __IO  uint8_t PLLM3      : 1;
+  __IO  uint8_t PLLK0      : 1;
+  __IO  uint8_t PLLK1      : 1;
+  __IO  uint8_t PLLK2      : 1;
+  __IO  uint8_t PLLK3      : 1;
+} stc_crg_pll_ctl1_field_t;
+
+typedef struct stc_crg_pll_ctl2_field
+{
+  __IO  uint8_t PLLN0      : 1;
+  __IO  uint8_t PLLN1      : 1;
+  __IO  uint8_t PLLN2      : 1;
+  __IO  uint8_t PLLN3      : 1;
+  __IO  uint8_t PLLN4      : 1;
+  __IO  uint8_t PLLN5      : 1;
+} stc_crg_pll_ctl2_field_t;
+
+typedef struct stc_crg_csv_ctl_field
+{
+  __IO uint16_t MCSVE      : 1;
+  __IO uint16_t SCSVE      : 1;
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t FCSDE      : 1;
+  __IO uint16_t FCSRE      : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t FCD0       : 1;
+  __IO uint16_t FCD1       : 1;
+  __IO uint16_t FCD2       : 1;
+} stc_crg_csv_ctl_field_t;
+
+typedef struct stc_crg_csv_str_field
+{
+  __IO  uint8_t MCMF       : 1;
+  __IO  uint8_t SCMF       : 1;
+} stc_crg_csv_str_field_t;
+
+typedef struct stc_crg_dbwdt_ctl_field
+{
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t DPSWBE     : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t DPHWBE     : 1;
+} stc_crg_dbwdt_ctl_field_t;
+
+typedef struct stc_crg_int_enr_field
+{
+  __IO  uint8_t MCSE       : 1;
+  __IO  uint8_t SCSE       : 1;
+  __IO  uint8_t PCSE       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSE       : 1;
+} stc_crg_int_enr_field_t;
+
+typedef struct stc_crg_int_str_field
+{
+  __IO  uint8_t MCSI       : 1;
+  __IO  uint8_t SCSI       : 1;
+  __IO  uint8_t PCSI       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSI       : 1;
+} stc_crg_int_str_field_t;
+
+typedef struct stc_crg_int_clr_field
+{
+  __IO  uint8_t MCSC       : 1;
+  __IO  uint8_t SCSC       : 1;
+  __IO  uint8_t PCSC       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSC       : 1;
+} stc_crg_int_clr_field_t;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* HWWDT_MODULE register bit fields */
+typedef struct stc_hwwdt_wdg_ctl_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_hwwdt_wdg_ctl_field_t;
+
+typedef struct stc_hwwdt_wdg_ris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_hwwdt_wdg_ris_field_t;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* SWWDT_MODULE register bit fields */
+typedef struct stc_swwdt_wdogcontrol_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_swwdt_wdogcontrol_field_t;
+
+typedef struct stc_swwdt_wdogris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_swwdt_wdogris_field_t;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* DTIM_MODULE register bit fields */
+typedef struct stc_dtim_timer1control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer1control_field_t;
+
+typedef struct stc_dtim_timer1ris_field
+{
+  __IO uint32_t TIMER1RIS  : 1;
+} stc_dtim_timer1ris_field_t;
+
+typedef struct stc_dtim_timer1mis_field
+{
+  __IO uint32_t TIMER1MIS  : 1;
+} stc_dtim_timer1mis_field_t;
+
+typedef struct stc_dtim_timer2control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer2control_field_t;
+
+typedef struct stc_dtim_timer2ris_field
+{
+  __IO uint32_t TIMER2RIS  : 1;
+} stc_dtim_timer2ris_field_t;
+
+typedef struct stc_dtim_timer2mis_field
+{
+  __IO uint32_t TIMER2MIS  : 1;
+} stc_dtim_timer2mis_field_t;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* MFT_FRT_MODULE register bit fields */
+typedef struct stc_mft_frt_tcsa0_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa0_field_t;
+
+typedef struct stc_mft_frt_tcsb0_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb0_field_t;
+
+typedef struct stc_mft_frt_tcsa1_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa1_field_t;
+
+typedef struct stc_mft_frt_tcsb1_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb1_field_t;
+
+typedef struct stc_mft_frt_tcsa2_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa2_field_t;
+
+typedef struct stc_mft_frt_tcsb2_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb2_field_t;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* MFT_OCU_MODULE register bit fields */
+typedef struct stc_mft_ocu_ocsa10_field
+{
+  __IO  uint8_t CST0       : 1;
+  __IO  uint8_t CST1       : 1;
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t IOE0       : 1;
+  __IO  uint8_t IOE1       : 1;
+  __IO  uint8_t IOP0       : 1;
+  __IO  uint8_t IOP1       : 1;
+} stc_mft_ocu_ocsa10_field_t;
+
+typedef struct stc_mft_ocu_ocsb10_field
+{
+  __IO  uint8_t OTD0       : 1;
+  __IO  uint8_t OTD1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+} stc_mft_ocu_ocsb10_field_t;
+
+typedef struct stc_mft_ocu_ocsa32_field
+{
+  __IO  uint8_t CST2       : 1;
+  __IO  uint8_t CST3       : 1;
+  __IO  uint8_t BDIS2      : 1;
+  __IO  uint8_t BDIS3      : 1;
+  __IO  uint8_t IOE2       : 1;
+  __IO  uint8_t IOE3       : 1;
+  __IO  uint8_t IOP2       : 1;
+  __IO  uint8_t IOP3       : 1;
+} stc_mft_ocu_ocsa32_field_t;
+
+typedef struct stc_mft_ocu_ocsb32_field
+{
+  __IO  uint8_t OTD2       : 1;
+  __IO  uint8_t OTD3       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS2       : 1;
+  __IO  uint8_t BTS3       : 1;
+} stc_mft_ocu_ocsb32_field_t;
+
+typedef struct stc_mft_ocu_ocsa54_field
+{
+  __IO  uint8_t CST4       : 1;
+  __IO  uint8_t CST5       : 1;
+  __IO  uint8_t BDIS4      : 1;
+  __IO  uint8_t BDIS5      : 1;
+  __IO  uint8_t IOE4       : 1;
+  __IO  uint8_t IOE5       : 1;
+  __IO  uint8_t IOP4       : 1;
+  __IO  uint8_t IOP5       : 1;
+} stc_mft_ocu_ocsa54_field_t;
+
+typedef struct stc_mft_ocu_ocsb54_field
+{
+  __IO  uint8_t OTD4       : 1;
+  __IO  uint8_t OTD5       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS4       : 1;
+  __IO  uint8_t BTS5       : 1;
+} stc_mft_ocu_ocsb54_field_t;
+
+typedef struct stc_mft_ocu_ocsc_field
+{
+  __IO  uint8_t MOD0       : 1;
+  __IO  uint8_t MOD1       : 1;
+  __IO  uint8_t MOD2       : 1;
+  __IO  uint8_t MOD3       : 1;
+  __IO  uint8_t MOD4       : 1;
+  __IO  uint8_t MOD5       : 1;
+} stc_mft_ocu_ocsc_field_t;
+
+typedef struct stc_mft_ocu_ocfs10_field
+{
+  __IO  uint8_t FSO00      : 1;
+  __IO  uint8_t FSO01      : 1;
+  __IO  uint8_t FSO02      : 1;
+  __IO  uint8_t FSO03      : 1;
+  __IO  uint8_t FSO10      : 1;
+  __IO  uint8_t FSO11      : 1;
+  __IO  uint8_t FSO12      : 1;
+  __IO  uint8_t FSO13      : 1;
+} stc_mft_ocu_ocfs10_field_t;
+
+typedef struct stc_mft_ocu_ocfs32_field
+{
+  __IO  uint8_t FSO20      : 1;
+  __IO  uint8_t FSO21      : 1;
+  __IO  uint8_t FSO22      : 1;
+  __IO  uint8_t FSO23      : 1;
+  __IO  uint8_t FSO30      : 1;
+  __IO  uint8_t FSO31      : 1;
+  __IO  uint8_t FSO32      : 1;
+  __IO  uint8_t FSO33      : 1;
+} stc_mft_ocu_ocfs32_field_t;
+
+typedef struct stc_mft_ocu_ocfs54_field
+{
+  __IO  uint8_t FSO40      : 1;
+  __IO  uint8_t FSO41      : 1;
+  __IO  uint8_t FSO42      : 1;
+  __IO  uint8_t FSO43      : 1;
+  __IO  uint8_t FSO50      : 1;
+  __IO  uint8_t FSO51      : 1;
+  __IO  uint8_t FSO52      : 1;
+  __IO  uint8_t FSO53      : 1;
+} stc_mft_ocu_ocfs54_field_t;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* MFT_WFG_MODULE register bit fields */
+typedef struct stc_mft_wfg_wfsa10_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD        : 3;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa10_field_t;
+
+typedef struct stc_mft_wfg_wfsa32_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD        : 3;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa32_field_t;
+
+typedef struct stc_mft_wfg_wfsa54_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD        : 3;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa54_field_t;
+
+typedef struct stc_mft_wfg_wfir_field
+{
+  __IO uint16_t DTIF       : 1;
+  __IO uint16_t DTIC       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t TMIF10     : 1;
+  __IO uint16_t TMIC10     : 1;
+  __IO uint16_t TMIE10     : 1;
+  __IO uint16_t TMIS10     : 1;
+  __IO uint16_t TMIF32     : 1;
+  __IO uint16_t TMIC32     : 1;
+  __IO uint16_t TMIE32     : 1;
+  __IO uint16_t TMIS32     : 1;
+  __IO uint16_t TMIF54     : 1;
+  __IO uint16_t TMIC54     : 1;
+  __IO uint16_t TMIE54     : 1;
+  __IO uint16_t TMIS54     : 1;
+} stc_mft_wfg_wfir_field_t;
+
+typedef struct stc_mft_wfg_nzcl_field
+{
+  __IO uint16_t DTIE       : 1;
+  __IO uint16_t NWS0       : 1;
+  __IO uint16_t NWS1       : 1;
+  __IO uint16_t NWS2       : 1;
+  __IO uint16_t SDTI       : 1;
+} stc_mft_wfg_nzcl_field_t;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* MFT_ICU_MODULE register bit fields */
+typedef struct stc_mft_icu_icfs10_field
+{
+  __IO  uint8_t FSI00      : 1;
+  __IO  uint8_t FSI01      : 1;
+  __IO  uint8_t FSI02      : 1;
+  __IO  uint8_t FSI03      : 1;
+  __IO  uint8_t FSI10      : 1;
+  __IO  uint8_t FSI11      : 1;
+  __IO  uint8_t FSI12      : 1;
+  __IO  uint8_t FSI13      : 1;
+} stc_mft_icu_icfs10_field_t;
+
+typedef struct stc_mft_icu_icfs32_field
+{
+  __IO  uint8_t FSI20      : 1;
+  __IO  uint8_t FSI21      : 1;
+  __IO  uint8_t FSI22      : 1;
+  __IO  uint8_t FSI23      : 1;
+  __IO  uint8_t FSI30      : 1;
+  __IO  uint8_t FSI31      : 1;
+  __IO  uint8_t FSI32      : 1;
+  __IO  uint8_t FSI33      : 1;
+} stc_mft_icu_icfs32_field_t;
+
+typedef struct stc_mft_icu_icsa10_field
+{
+  __IO  uint8_t EG00       : 1;
+  __IO  uint8_t EG01       : 1;
+  __IO  uint8_t EG10       : 1;
+  __IO  uint8_t EG11       : 1;
+  __IO  uint8_t ICE0       : 1;
+  __IO  uint8_t ICE1       : 1;
+  __IO  uint8_t ICP0       : 1;
+  __IO  uint8_t ICP1       : 1;
+} stc_mft_icu_icsa10_field_t;
+
+typedef struct stc_mft_icu_icsb10_field
+{
+  __IO  uint8_t IEI0       : 1;
+  __IO  uint8_t IEI1       : 1;
+} stc_mft_icu_icsb10_field_t;
+
+typedef struct stc_mft_icu_icsa32_field
+{
+  __IO  uint8_t EG20       : 1;
+  __IO  uint8_t EG21       : 1;
+  __IO  uint8_t EG30       : 1;
+  __IO  uint8_t EG31       : 1;
+  __IO  uint8_t ICE2       : 1;
+  __IO  uint8_t ICE3       : 1;
+  __IO  uint8_t ICP2       : 1;
+  __IO  uint8_t ICP3       : 1;
+} stc_mft_icu_icsa32_field_t;
+
+typedef struct stc_mft_icu_icsb32_field
+{
+  __IO  uint8_t IEI2       : 1;
+  __IO  uint8_t IEI3       : 1;
+} stc_mft_icu_icsb32_field_t;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* MFT_ADCMP_MODULE register bit fields */
+typedef struct stc_mft_adcmp_acsb_field
+{
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t BDIS2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+  __IO  uint8_t BTS2       : 1;
+} stc_mft_adcmp_acsb_field_t;
+
+typedef struct stc_mft_adcmp_acsa_field
+{
+  __IO uint16_t CE00       : 1;
+  __IO uint16_t CE01       : 1;
+  __IO uint16_t CE10       : 1;
+  __IO uint16_t CE11       : 1;
+  __IO uint16_t CE20       : 1;
+  __IO uint16_t CE21       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SEL00      : 1;
+  __IO uint16_t SEL01      : 1;
+  __IO uint16_t SEL10      : 1;
+  __IO uint16_t SEL11      : 1;
+  __IO uint16_t SEL20      : 1;
+  __IO uint16_t SEL21      : 1;
+} stc_mft_adcmp_acsa_field_t;
+
+typedef struct stc_mft_adcmp_atsa_field
+{
+  __IO uint16_t AD0S0      : 1;
+  __IO uint16_t AD0S1      : 1;
+  __IO uint16_t AD1S0      : 1;
+  __IO uint16_t AD1S1      : 1;
+  __IO uint16_t AD2S0      : 1;
+  __IO uint16_t AD2S1      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t AD0P0      : 1;
+  __IO uint16_t AD0P1      : 1;
+  __IO uint16_t AD1P0      : 1;
+  __IO uint16_t AD1P1      : 1;
+  __IO uint16_t AD2P0      : 1;
+  __IO uint16_t AD2P1      : 1;
+} stc_mft_adcmp_atsa_field_t;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* MFT_PPG_MODULE register bit fields */
+typedef struct stc_mft_ppg_ttcr0_field
+{
+  __IO  uint8_t STR0       : 1;
+  __IO  uint8_t MONI0      : 1;
+  __IO  uint8_t CS00       : 1;
+  __IO  uint8_t CS01       : 1;
+  __IO  uint8_t TRG0O      : 1;
+  __IO  uint8_t TRG2O      : 1;
+  __IO  uint8_t TRG4O      : 1;
+  __IO  uint8_t TRG6O      : 1;
+} stc_mft_ppg_ttcr0_field_t;
+
+typedef struct stc_mft_ppg_ttcr1_field
+{
+  __IO  uint8_t STR1       : 1;
+  __IO  uint8_t MONI1      : 1;
+  __IO  uint8_t CS10       : 1;
+  __IO  uint8_t CS11       : 1;
+  __IO  uint8_t TRG1O      : 1;
+  __IO  uint8_t TRG3O      : 1;
+  __IO  uint8_t TRG5O      : 1;
+  __IO  uint8_t TRG7O      : 1;
+} stc_mft_ppg_ttcr1_field_t;
+
+typedef struct stc_mft_ppg_ttcr2_field
+{
+  __IO  uint8_t STR2       : 1;
+  __IO  uint8_t MONI2      : 1;
+  __IO  uint8_t CS20       : 1;
+  __IO  uint8_t CS21       : 1;
+  __IO  uint8_t TRG16O     : 1;
+  __IO  uint8_t TRG18O     : 1;
+  __IO  uint8_t TRG20O     : 1;
+  __IO  uint8_t TRG22O     : 1;
+} stc_mft_ppg_ttcr2_field_t;
+
+typedef struct stc_mft_ppg_trg_field
+{
+  __IO uint16_t PEN00      : 1;
+  __IO uint16_t PEN01      : 1;
+  __IO uint16_t PEN02      : 1;
+  __IO uint16_t PEN03      : 1;
+  __IO uint16_t PEN04      : 1;
+  __IO uint16_t PEN05      : 1;
+  __IO uint16_t PEN06      : 1;
+  __IO uint16_t PEN07      : 1;
+  __IO uint16_t PEN08      : 1;
+  __IO uint16_t PEN09      : 1;
+  __IO uint16_t PEN10      : 1;
+  __IO uint16_t PEN11      : 1;
+  __IO uint16_t PEN12      : 1;
+  __IO uint16_t PEN13      : 1;
+  __IO uint16_t PEN14      : 1;
+  __IO uint16_t PEN15      : 1;
+} stc_mft_ppg_trg_field_t;
+
+typedef struct stc_mft_ppg_trg1_field
+{
+  __IO uint16_t PEN16      : 1;
+  __IO uint16_t PEN17      : 1;
+  __IO uint16_t PEN18      : 1;
+  __IO uint16_t PEN19      : 1;
+  __IO uint16_t PEN20      : 1;
+  __IO uint16_t PEN21      : 1;
+  __IO uint16_t PEN22      : 1;
+  __IO uint16_t PEN23      : 1;
+} stc_mft_ppg_trg1_field_t;
+
+typedef struct stc_mft_ppg_revc_field
+{
+  __IO uint16_t REV00      : 1;
+  __IO uint16_t REV01      : 1;
+  __IO uint16_t REV02      : 1;
+  __IO uint16_t REV03      : 1;
+  __IO uint16_t REV04      : 1;
+  __IO uint16_t REV05      : 1;
+  __IO uint16_t REV06      : 1;
+  __IO uint16_t REV07      : 1;
+  __IO uint16_t REV08      : 1;
+  __IO uint16_t REV09      : 1;
+  __IO uint16_t REV10      : 1;
+  __IO uint16_t REV11      : 1;
+  __IO uint16_t REV12      : 1;
+  __IO uint16_t REV13      : 1;
+  __IO uint16_t REV14      : 1;
+  __IO uint16_t REV15      : 1;
+} stc_mft_ppg_revc_field_t;
+
+typedef struct stc_mft_ppg_revc1_field
+{
+  __IO uint16_t REV16      : 1;
+  __IO uint16_t REV17      : 1;
+  __IO uint16_t REV18      : 1;
+  __IO uint16_t REV19      : 1;
+  __IO uint16_t REV20      : 1;
+  __IO uint16_t REV21      : 1;
+  __IO uint16_t REV22      : 1;
+  __IO uint16_t REV23      : 1;
+} stc_mft_ppg_revc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc1_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc0_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc0_field_t;
+
+typedef struct stc_mft_ppg_ppgc3_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc3_field_t;
+
+typedef struct stc_mft_ppg_ppgc2_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc2_field_t;
+
+typedef struct stc_mft_ppg_gatec0_field
+{
+  __IO  uint8_t EDGE0      : 1;
+  __IO  uint8_t STRG0      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE2      : 1;
+  __IO  uint8_t STRG2      : 1;
+} stc_mft_ppg_gatec0_field_t;
+
+typedef struct stc_mft_ppg_ppgc5_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc5_field_t;
+
+typedef struct stc_mft_ppg_ppgc4_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc4_field_t;
+
+typedef struct stc_mft_ppg_ppgc7_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc7_field_t;
+
+typedef struct stc_mft_ppg_ppgc6_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc6_field_t;
+
+typedef struct stc_mft_ppg_gatec4_field
+{
+  __IO  uint8_t EDGE4      : 1;
+  __IO  uint8_t STRG4      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE6      : 1;
+  __IO  uint8_t STRG6      : 1;
+} stc_mft_ppg_gatec4_field_t;
+
+typedef struct stc_mft_ppg_ppgc9_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc9_field_t;
+
+typedef struct stc_mft_ppg_ppgc8_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc8_field_t;
+
+typedef struct stc_mft_ppg_ppgc11_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc11_field_t;
+
+typedef struct stc_mft_ppg_ppgc10_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc10_field_t;
+
+typedef struct stc_mft_ppg_gatec8_field
+{
+  __IO  uint8_t EDGE8      : 1;
+  __IO  uint8_t STRG8      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE10     : 1;
+  __IO  uint8_t STRG10     : 1;
+} stc_mft_ppg_gatec8_field_t;
+
+typedef struct stc_mft_ppg_ppgc13_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc13_field_t;
+
+typedef struct stc_mft_ppg_ppgc12_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc12_field_t;
+
+typedef struct stc_mft_ppg_ppgc15_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc15_field_t;
+
+typedef struct stc_mft_ppg_ppgc14_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc14_field_t;
+
+typedef struct stc_mft_ppg_gatec12_field
+{
+  __IO  uint8_t EDGE12     : 1;
+  __IO  uint8_t STRG12     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE14     : 1;
+  __IO  uint8_t STRG14     : 1;
+} stc_mft_ppg_gatec12_field_t;
+
+typedef struct stc_mft_ppg_ppgc17_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc17_field_t;
+
+typedef struct stc_mft_ppg_ppgc16_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc16_field_t;
+
+typedef struct stc_mft_ppg_ppgc19_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc19_field_t;
+
+typedef struct stc_mft_ppg_ppgc18_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc18_field_t;
+
+typedef struct stc_mft_ppg_gatec16_field
+{
+  __IO  uint8_t EDGE16     : 1;
+  __IO  uint8_t STRG16     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE18     : 1;
+  __IO  uint8_t STRG18     : 1;
+} stc_mft_ppg_gatec16_field_t;
+
+typedef struct stc_mft_ppg_ppgc21_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc21_field_t;
+
+typedef struct stc_mft_ppg_ppgc20_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc20_field_t;
+
+typedef struct stc_mft_ppg_ppgc23_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc23_field_t;
+
+typedef struct stc_mft_ppg_ppgc22_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc22_field_t;
+
+typedef struct stc_mft_ppg_gatec20_field
+{
+  __IO  uint8_t EDGE20     : 1;
+  __IO  uint8_t STRG20     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE22     : 1;
+  __IO  uint8_t STRG22     : 1;
+} stc_mft_ppg_gatec20_field_t;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* BT_PPG_MODULE register bit fields */
+typedef struct stc_bt_ppg_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD        : 3;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_ppg_tmcr_field_t;
+
+typedef struct stc_bt_ppg_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_ppg_stc_field_t;
+
+typedef struct stc_bt_ppg_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_ppg_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* BT_PWM_MODULE register bit fields */
+typedef struct stc_bt_pwm_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD        : 3;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwm_tmcr_field_t;
+
+typedef struct stc_bt_pwm_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+  __IO  uint8_t DTIR       : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t UDIE       : 1;
+  __IO  uint8_t DTIE       : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_pwm_stc_field_t;
+
+typedef struct stc_bt_pwm_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwm_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* BT_RT_MODULE register bit fields */
+typedef struct stc_bt_rt_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD        : 3;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_rt_tmcr_field_t;
+
+typedef struct stc_bt_rt_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_rt_stc_field_t;
+
+typedef struct stc_bt_rt_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_rt_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* BT_PWC_MODULE register bit fields */
+typedef struct stc_bt_pwc_tmcr_field
+{
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FMD        : 3;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t EGS2       : 1;
+       uint16_t RESERVED3  : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwc_tmcr_field_t;
+
+typedef struct stc_bt_pwc_stc_field
+{
+  __IO  uint8_t OVIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t EDIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t OVIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t EDIE       : 1;
+  __IO  uint8_t ERR        : 1;
+} stc_bt_pwc_stc_field_t;
+
+typedef struct stc_bt_pwc_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwc_tmcr2_field_t;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* BTIOSEL03_MODULE register bit fields */
+typedef struct stc_btiosel03_btsel0123_field
+{
+  __IO  uint8_t SEL01_0    : 1;
+  __IO  uint8_t SEL01_1    : 1;
+  __IO  uint8_t SEL01_2    : 1;
+  __IO  uint8_t SEL01_3    : 1;
+  __IO  uint8_t SEL23_0    : 1;
+  __IO  uint8_t SEL23_1    : 1;
+  __IO  uint8_t SEL23_2    : 1;
+  __IO  uint8_t SEL23_3    : 1;
+} stc_btiosel03_btsel0123_field_t;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* BTIOSEL47_MODULE register bit fields */
+typedef struct stc_btiosel47_btsel4567_field
+{
+  __IO  uint8_t SEL45_0    : 1;
+  __IO  uint8_t SEL45_1    : 1;
+  __IO  uint8_t SEL45_2    : 1;
+  __IO  uint8_t SEL45_3    : 1;
+  __IO  uint8_t SEL67_0    : 1;
+  __IO  uint8_t SEL67_1    : 1;
+  __IO  uint8_t SEL67_2    : 1;
+  __IO  uint8_t SEL67_3    : 1;
+} stc_btiosel47_btsel4567_field_t;
+
+/******************************************************************************
+ * BTIOSEL811_MODULE
+ ******************************************************************************/
+/* BTIOSEL811_MODULE register bit fields */
+typedef struct stc_btiosel8b_btsel89ab_field
+{
+  __IO  uint8_t SEL89_0    : 1;
+  __IO  uint8_t SEL89_1    : 1;
+  __IO  uint8_t SEL89_2    : 1;
+  __IO  uint8_t SEL89_3    : 1;
+  __IO  uint8_t SELAB_0    : 1;
+  __IO  uint8_t SELAB_1    : 1;
+  __IO  uint8_t SELAB_2    : 1;
+  __IO  uint8_t SELAB_3    : 1;
+} stc_btiosel8b_btsel89ab_field_t;
+
+/******************************************************************************
+ * BTIOSEL1215_MODULE
+ ******************************************************************************/
+/* BTIOSEL1215_MODULE register bit fields */
+typedef struct stc_btioselcf_btselcdef_field
+{
+  __IO  uint8_t SELCD_0    : 1;
+  __IO  uint8_t SELCD_1    : 1;
+  __IO  uint8_t SELCD_2    : 1;
+  __IO  uint8_t SELCD_3    : 1;
+  __IO  uint8_t SELEF_0    : 1;
+  __IO  uint8_t SELEF_1    : 1;
+  __IO  uint8_t SELEF_2    : 1;
+  __IO  uint8_t SELEF_3    : 1;
+} stc_btioselcf_btselcdef_field_t;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* SBSSR_MODULE register bit fields */
+typedef struct stc_sbssr_btsssr_field
+{
+  __IO uint16_t SSR0       : 1;
+  __IO uint16_t SSR1       : 1;
+  __IO uint16_t SSR2       : 1;
+  __IO uint16_t SSR3       : 1;
+  __IO uint16_t SSR4       : 1;
+  __IO uint16_t SSR5       : 1;
+  __IO uint16_t SSR6       : 1;
+  __IO uint16_t SSR7       : 1;
+  __IO uint16_t SSR8       : 1;
+  __IO uint16_t SSR9       : 1;
+  __IO uint16_t SSR10      : 1;
+  __IO uint16_t SSR11      : 1;
+  __IO uint16_t SSR12      : 1;
+  __IO uint16_t SSR13      : 1;
+  __IO uint16_t SSR14      : 1;
+  __IO uint16_t SSR15      : 1;
+} stc_sbssr_btsssr_field_t;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* QPRC_MODULE register bit fields */
+typedef struct stc_qprc_qicr_field
+{
+  __IO uint16_t QPCMIE     : 1;
+  __IO uint16_t QPCMF      : 1;
+  __IO uint16_t QPRCMIE    : 1;
+  __IO uint16_t QPRCMF     : 1;
+  __IO uint16_t OUZIE      : 1;
+  __IO uint16_t UFDF       : 1;
+  __IO uint16_t OFDF       : 1;
+  __IO uint16_t ZIIF       : 1;
+  __IO uint16_t CDCIE      : 1;
+  __IO uint16_t CDCF       : 1;
+  __IO uint16_t DIRPC      : 1;
+  __IO uint16_t DIROU      : 1;
+  __IO uint16_t QPCNRCMIE  : 1;
+  __IO uint16_t QPCNRCMF   : 1;
+} stc_qprc_qicr_field_t;
+
+typedef struct stc_qprc_qicrl_field
+{
+  __IO  uint8_t QPCMIE     : 1;
+  __IO  uint8_t QPCMF      : 1;
+  __IO  uint8_t QPRCMIE    : 1;
+  __IO  uint8_t QPRCMF     : 1;
+  __IO  uint8_t OUZIE      : 1;
+  __IO  uint8_t UFDF       : 1;
+  __IO  uint8_t OFDF       : 1;
+  __IO  uint8_t ZIIF       : 1;
+} stc_qprc_qicrl_field_t;
+
+typedef struct stc_qprc_qicrh_field
+{
+  __IO  uint8_t CDCIE      : 1;
+  __IO  uint8_t CDCF       : 1;
+  __IO  uint8_t DIRPC      : 1;
+  __IO  uint8_t DIROU      : 1;
+  __IO  uint8_t QPCNRCMIE  : 1;
+  __IO  uint8_t QPCNRCMF   : 1;
+} stc_qprc_qicrh_field_t;
+
+typedef struct stc_qprc_qcr_field
+{
+  __IO uint16_t PCM0       : 1;
+  __IO uint16_t PCM1       : 1;
+  __IO uint16_t RCM0       : 1;
+  __IO uint16_t RCM1       : 1;
+  __IO uint16_t PSTP       : 1;
+  __IO uint16_t CGSC       : 1;
+  __IO uint16_t RSEL       : 1;
+  __IO uint16_t SWAP       : 1;
+  __IO uint16_t PCRM0      : 1;
+  __IO uint16_t PCRM1      : 1;
+  __IO uint16_t AES0       : 1;
+  __IO uint16_t AES1       : 1;
+  __IO uint16_t BES0       : 1;
+  __IO uint16_t BES1       : 1;
+  __IO uint16_t CGE0       : 1;
+  __IO uint16_t CGE1       : 1;
+} stc_qprc_qcr_field_t;
+
+typedef struct stc_qprc_qcrl_field
+{
+  __IO  uint8_t PCM0       : 1;
+  __IO  uint8_t PCM1       : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t PSTP       : 1;
+  __IO  uint8_t CGSC       : 1;
+  __IO  uint8_t RSEL       : 1;
+  __IO  uint8_t SWAP       : 1;
+} stc_qprc_qcrl_field_t;
+
+typedef struct stc_qprc_qcrh_field
+{
+  __IO  uint8_t PCRM0      : 1;
+  __IO  uint8_t PCRM1      : 1;
+  __IO  uint8_t AES0       : 1;
+  __IO  uint8_t AES1       : 1;
+  __IO  uint8_t BES0       : 1;
+  __IO  uint8_t BES1       : 1;
+  __IO  uint8_t CGE0       : 1;
+  __IO  uint8_t CGE1       : 1;
+} stc_qprc_qcrh_field_t;
+
+typedef struct stc_qprc_qecr_field
+{
+  __IO uint16_t ORNGMD     : 1;
+  __IO uint16_t ORNGF      : 1;
+  __IO uint16_t ORNGIE     : 1;
+} stc_qprc_qecr_field_t;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* ADC12_MODULE register bit fields */
+typedef struct stc_adc_adsr_field
+{
+  __IO  uint8_t SCS        : 1;
+  __IO  uint8_t PCS        : 1;
+  __IO  uint8_t PCNS       : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t FDAS       : 1;
+  __IO  uint8_t ADSTP      : 1;
+} stc_adc_adsr_field_t;
+
+typedef struct stc_adc_adcr_field
+{
+  __IO  uint8_t OVRIE      : 1;
+  __IO  uint8_t CMPIE      : 1;
+  __IO  uint8_t PCIE       : 1;
+  __IO  uint8_t SCIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t CMPIF      : 1;
+  __IO  uint8_t PCIF       : 1;
+  __IO  uint8_t SCIF       : 1;
+} stc_adc_adcr_field_t;
+
+typedef struct stc_adc_sfns_field
+{
+  __IO  uint8_t SFS0       : 1;
+  __IO  uint8_t SFS1       : 1;
+  __IO  uint8_t SFS2       : 1;
+  __IO  uint8_t SFS3       : 1;
+} stc_adc_sfns_field_t;
+
+typedef struct stc_adc_sccr_field
+{
+  __IO  uint8_t SSTR       : 1;
+  __IO  uint8_t SHEN       : 1;
+  __IO  uint8_t RPT        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t SFCLR      : 1;
+  __IO  uint8_t SOVR       : 1;
+  __IO  uint8_t SFUL       : 1;
+  __IO  uint8_t SEMP       : 1;
+} stc_adc_sccr_field_t;
+
+typedef struct stc_adc_scfd_field
+{
+  __IO uint32_t SC0        : 1;
+  __IO uint32_t SC1        : 1;
+  __IO uint32_t SC2        : 1;
+  __IO uint32_t SC3        : 1;
+  __IO uint32_t SC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+  __IO uint32_t SD3        : 1;
+  __IO uint32_t SD4        : 1;
+  __IO uint32_t SD5        : 1;
+  __IO uint32_t SD6        : 1;
+  __IO uint32_t SD7        : 1;
+  __IO uint32_t SD8        : 1;
+  __IO uint32_t SD9        : 1;
+  __IO uint32_t SD10       : 1;
+  __IO uint32_t SD11       : 1;
+} stc_adc_scfd_field_t;
+
+typedef struct stc_adc_scfdl_field
+{
+  __IO uint16_t SC0        : 1;
+  __IO uint16_t SC1        : 1;
+  __IO uint16_t SC2        : 1;
+  __IO uint16_t SC3        : 1;
+  __IO uint16_t SC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t INVL       : 1;
+} stc_adc_scfdl_field_t;
+
+typedef struct stc_adc_scfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t SD0        : 1;
+  __IO uint16_t SD1        : 1;
+  __IO uint16_t SD2        : 1;
+  __IO uint16_t SD3        : 1;
+  __IO uint16_t SD4        : 1;
+  __IO uint16_t SD5        : 1;
+  __IO uint16_t SD6        : 1;
+  __IO uint16_t SD7        : 1;
+  __IO uint16_t SD8        : 1;
+  __IO uint16_t SD9        : 1;
+  __IO uint16_t SD10       : 1;
+  __IO uint16_t SD11       : 1;
+} stc_adc_scfdh_field_t;
+
+typedef struct stc_adc_scis23_field
+{
+  __IO uint16_t AN16       : 1;
+  __IO uint16_t AN17       : 1;
+  __IO uint16_t AN18       : 1;
+  __IO uint16_t AN19       : 1;
+  __IO uint16_t AN20       : 1;
+  __IO uint16_t AN21       : 1;
+  __IO uint16_t AN22       : 1;
+  __IO uint16_t AN23       : 1;
+  __IO uint16_t AN24       : 1;
+  __IO uint16_t AN25       : 1;
+  __IO uint16_t AN26       : 1;
+  __IO uint16_t AN27       : 1;
+  __IO uint16_t AN28       : 1;
+  __IO uint16_t AN29       : 1;
+  __IO uint16_t AN30       : 1;
+  __IO uint16_t AN31       : 1;
+} stc_adc_scis23_field_t;
+
+typedef struct stc_adc_scis2_field
+{
+  __IO  uint8_t AN16       : 1;
+  __IO  uint8_t AN17       : 1;
+  __IO  uint8_t AN18       : 1;
+  __IO  uint8_t AN19       : 1;
+  __IO  uint8_t AN20       : 1;
+  __IO  uint8_t AN21       : 1;
+  __IO  uint8_t AN22       : 1;
+  __IO  uint8_t AN23       : 1;
+} stc_adc_scis2_field_t;
+
+typedef struct stc_adc_scis3_field
+{
+  __IO  uint8_t AN24       : 1;
+  __IO  uint8_t AN25       : 1;
+  __IO  uint8_t AN26       : 1;
+  __IO  uint8_t AN27       : 1;
+  __IO  uint8_t AN28       : 1;
+  __IO  uint8_t AN29       : 1;
+  __IO  uint8_t AN30       : 1;
+  __IO  uint8_t AN31       : 1;
+} stc_adc_scis3_field_t;
+
+typedef struct stc_adc_scis01_field
+{
+  __IO uint16_t AN0        : 1;
+  __IO uint16_t AN1        : 1;
+  __IO uint16_t AN2        : 1;
+  __IO uint16_t AN3        : 1;
+  __IO uint16_t AN4        : 1;
+  __IO uint16_t AN5        : 1;
+  __IO uint16_t AN6        : 1;
+  __IO uint16_t AN7        : 1;
+  __IO uint16_t AN8        : 1;
+  __IO uint16_t AN9        : 1;
+  __IO uint16_t AN10       : 1;
+  __IO uint16_t AN11       : 1;
+  __IO uint16_t AN12       : 1;
+  __IO uint16_t AN13       : 1;
+  __IO uint16_t AN14       : 1;
+  __IO uint16_t AN15       : 1;
+} stc_adc_scis01_field_t;
+
+typedef struct stc_adc_scis0_field
+{
+  __IO  uint8_t AN0        : 1;
+  __IO  uint8_t AN1        : 1;
+  __IO  uint8_t AN2        : 1;
+  __IO  uint8_t AN3        : 1;
+  __IO  uint8_t AN4        : 1;
+  __IO  uint8_t AN5        : 1;
+  __IO  uint8_t AN6        : 1;
+  __IO  uint8_t AN7        : 1;
+} stc_adc_scis0_field_t;
+
+typedef struct stc_adc_scis1_field
+{
+  __IO  uint8_t AN8        : 1;
+  __IO  uint8_t AN9        : 1;
+  __IO  uint8_t AN10       : 1;
+  __IO  uint8_t AN11       : 1;
+  __IO  uint8_t AN12       : 1;
+  __IO  uint8_t AN13       : 1;
+  __IO  uint8_t AN14       : 1;
+  __IO  uint8_t AN15       : 1;
+} stc_adc_scis1_field_t;
+
+typedef struct stc_adc_pfns_field
+{
+  __IO  uint8_t PFS0       : 1;
+  __IO  uint8_t PFS1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TEST0      : 1;
+  __IO  uint8_t TEST1      : 1;
+} stc_adc_pfns_field_t;
+
+typedef struct stc_adc_pccr_field
+{
+  __IO  uint8_t PSTR       : 1;
+  __IO  uint8_t PHEN       : 1;
+  __IO  uint8_t PEEN       : 1;
+  __IO  uint8_t ESCE       : 1;
+  __IO  uint8_t PFCLR      : 1;
+  __IO  uint8_t POVR       : 1;
+  __IO  uint8_t PFUL       : 1;
+  __IO  uint8_t PEMP       : 1;
+} stc_adc_pccr_field_t;
+
+typedef struct stc_adc_pcfd_field
+{
+  __IO uint32_t PC0        : 1;
+  __IO uint32_t PC1        : 1;
+  __IO uint32_t PC2        : 1;
+  __IO uint32_t PC3        : 1;
+  __IO uint32_t PC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t PD0        : 1;
+  __IO uint32_t PD1        : 1;
+  __IO uint32_t PD2        : 1;
+  __IO uint32_t PD3        : 1;
+  __IO uint32_t PD4        : 1;
+  __IO uint32_t PD5        : 1;
+  __IO uint32_t PD6        : 1;
+  __IO uint32_t PD7        : 1;
+  __IO uint32_t PD8        : 1;
+  __IO uint32_t PD9        : 1;
+  __IO uint32_t PD10       : 1;
+  __IO uint32_t PD11       : 1;
+} stc_adc_pcfd_field_t;
+
+typedef struct stc_adc_pcfdl_field
+{
+  __IO uint16_t PC0        : 1;
+  __IO uint16_t PC1        : 1;
+  __IO uint16_t PC2        : 1;
+  __IO uint16_t PC3        : 1;
+  __IO uint16_t PC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+  __IO uint16_t RS2        : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t INVL       : 1;
+} stc_adc_pcfdl_field_t;
+
+typedef struct stc_adc_pcfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t PD0        : 1;
+  __IO uint16_t PD1        : 1;
+  __IO uint16_t PD2        : 1;
+  __IO uint16_t PD3        : 1;
+  __IO uint16_t PD4        : 1;
+  __IO uint16_t PD5        : 1;
+  __IO uint16_t PD6        : 1;
+  __IO uint16_t PD7        : 1;
+  __IO uint16_t PD8        : 1;
+  __IO uint16_t PD9        : 1;
+  __IO uint16_t PD10       : 1;
+  __IO uint16_t PD11       : 1;
+} stc_adc_pcfdh_field_t;
+
+typedef struct stc_adc_pcis_field
+{
+  __IO  uint8_t P1A0       : 1;
+  __IO  uint8_t P1A1       : 1;
+  __IO  uint8_t P1A2       : 1;
+  __IO  uint8_t P2A0       : 1;
+  __IO  uint8_t P2A1       : 1;
+  __IO  uint8_t P2A2       : 1;
+  __IO  uint8_t P2A3       : 1;
+  __IO  uint8_t P2A4       : 1;
+} stc_adc_pcis_field_t;
+
+typedef struct stc_adc_cmpcr_field
+{
+  __IO  uint8_t CCH0       : 1;
+  __IO  uint8_t CCH1       : 1;
+  __IO  uint8_t CCH2       : 1;
+  __IO  uint8_t CCH3       : 1;
+  __IO  uint8_t CCH4       : 1;
+  __IO  uint8_t CMD0       : 1;
+  __IO  uint8_t CMD1       : 1;
+  __IO  uint8_t CMPEN      : 1;
+} stc_adc_cmpcr_field_t;
+
+typedef struct stc_adc_cmpd_field
+{
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t CMAD2      : 1;
+  __IO uint16_t CMAD3      : 1;
+  __IO uint16_t CMAD4      : 1;
+  __IO uint16_t CMAD5      : 1;
+  __IO uint16_t CMAD6      : 1;
+  __IO uint16_t CMAD7      : 1;
+  __IO uint16_t CMAD8      : 1;
+  __IO uint16_t CMAD9      : 1;
+  __IO uint16_t CMAD10     : 1;
+  __IO uint16_t CMAD11     : 1;
+} stc_adc_cmpd_field_t;
+
+typedef struct stc_adc_adss23_field
+{
+  __IO uint16_t TS16       : 1;
+  __IO uint16_t TS17       : 1;
+  __IO uint16_t TS18       : 1;
+  __IO uint16_t TS19       : 1;
+  __IO uint16_t TS20       : 1;
+  __IO uint16_t TS21       : 1;
+  __IO uint16_t TS22       : 1;
+  __IO uint16_t TS23       : 1;
+  __IO uint16_t TS24       : 1;
+  __IO uint16_t TS25       : 1;
+  __IO uint16_t TS26       : 1;
+  __IO uint16_t TS27       : 1;
+  __IO uint16_t TS28       : 1;
+  __IO uint16_t TS29       : 1;
+  __IO uint16_t TS30       : 1;
+  __IO uint16_t TS31       : 1;
+} stc_adc_adss23_field_t;
+
+typedef struct stc_adc_adss2_field
+{
+  __IO  uint8_t TS16       : 1;
+  __IO  uint8_t TS17       : 1;
+  __IO  uint8_t TS18       : 1;
+  __IO  uint8_t TS19       : 1;
+  __IO  uint8_t TS20       : 1;
+  __IO  uint8_t TS21       : 1;
+  __IO  uint8_t TS22       : 1;
+  __IO  uint8_t TS23       : 1;
+} stc_adc_adss2_field_t;
+
+typedef struct stc_adc_adss3_field
+{
+  __IO  uint8_t TS24       : 1;
+  __IO  uint8_t TS25       : 1;
+  __IO  uint8_t TS26       : 1;
+  __IO  uint8_t TS27       : 1;
+  __IO  uint8_t TS28       : 1;
+  __IO  uint8_t TS29       : 1;
+  __IO  uint8_t TS30       : 1;
+  __IO  uint8_t TS31       : 1;
+} stc_adc_adss3_field_t;
+
+typedef struct stc_adc_adss01_field
+{
+  __IO uint16_t TS0        : 1;
+  __IO uint16_t TS1        : 1;
+  __IO uint16_t TS2        : 1;
+  __IO uint16_t TS3        : 1;
+  __IO uint16_t TS4        : 1;
+  __IO uint16_t TS5        : 1;
+  __IO uint16_t TS6        : 1;
+  __IO uint16_t TS7        : 1;
+  __IO uint16_t TS8        : 1;
+  __IO uint16_t TS9        : 1;
+  __IO uint16_t TS10       : 1;
+  __IO uint16_t TS11       : 1;
+  __IO uint16_t TS12       : 1;
+  __IO uint16_t TS13       : 1;
+  __IO uint16_t TS14       : 1;
+  __IO uint16_t TS15       : 1;
+} stc_adc_adss01_field_t;
+
+typedef struct stc_adc_adss0_field
+{
+  __IO  uint8_t TS0        : 1;
+  __IO  uint8_t TS1        : 1;
+  __IO  uint8_t TS2        : 1;
+  __IO  uint8_t TS3        : 1;
+  __IO  uint8_t TS4        : 1;
+  __IO  uint8_t TS5        : 1;
+  __IO  uint8_t TS6        : 1;
+  __IO  uint8_t TS7        : 1;
+} stc_adc_adss0_field_t;
+
+typedef struct stc_adc_adss1_field
+{
+  __IO  uint8_t TS8        : 1;
+  __IO  uint8_t TS9        : 1;
+  __IO  uint8_t TS10       : 1;
+  __IO  uint8_t TS11       : 1;
+  __IO  uint8_t TS12       : 1;
+  __IO  uint8_t TS13       : 1;
+  __IO  uint8_t TS14       : 1;
+  __IO  uint8_t TS15       : 1;
+} stc_adc_adss1_field_t;
+
+typedef struct stc_adc_adst01_field
+{
+  __IO uint16_t ST10       : 1;
+  __IO uint16_t ST11       : 1;
+  __IO uint16_t ST12       : 1;
+  __IO uint16_t ST13       : 1;
+  __IO uint16_t ST14       : 1;
+  __IO uint16_t STX10      : 1;
+  __IO uint16_t STX11      : 1;
+  __IO uint16_t STX12      : 1;
+  __IO uint16_t ST00       : 1;
+  __IO uint16_t ST01       : 1;
+  __IO uint16_t ST02       : 1;
+  __IO uint16_t ST03       : 1;
+  __IO uint16_t ST04       : 1;
+  __IO uint16_t STX00      : 1;
+  __IO uint16_t STX01      : 1;
+  __IO uint16_t STX02      : 1;
+} stc_adc_adst01_field_t;
+
+typedef struct stc_adc_adst1_field
+{
+  __IO  uint8_t ST10       : 1;
+  __IO  uint8_t ST11       : 1;
+  __IO  uint8_t ST12       : 1;
+  __IO  uint8_t ST13       : 1;
+  __IO  uint8_t ST14       : 1;
+  __IO  uint8_t STX10      : 1;
+  __IO  uint8_t STX11      : 1;
+  __IO  uint8_t STX12      : 1;
+} stc_adc_adst1_field_t;
+
+typedef struct stc_adc_adst0_field
+{
+  __IO  uint8_t ST00       : 1;
+  __IO  uint8_t ST01       : 1;
+  __IO  uint8_t ST02       : 1;
+  __IO  uint8_t ST03       : 1;
+  __IO  uint8_t ST04       : 1;
+  __IO  uint8_t STX00      : 1;
+  __IO  uint8_t STX01      : 1;
+  __IO  uint8_t STX02      : 1;
+} stc_adc_adst0_field_t;
+
+typedef struct stc_adc_adct_field
+{
+  __IO  uint8_t CT0        : 1;
+  __IO  uint8_t CT1        : 1;
+  __IO  uint8_t CT2        : 1;
+  __IO  uint8_t CT3        : 1;
+  __IO  uint8_t CT4        : 1;
+  __IO  uint8_t CT5        : 1;
+  __IO  uint8_t CT6        : 1;
+  __IO  uint8_t CT7        : 1;
+} stc_adc_adct_field_t;
+
+typedef struct stc_adc_prtsl_field
+{
+  __IO  uint8_t PRTSL0     : 1;
+  __IO  uint8_t PRTSL1     : 1;
+  __IO  uint8_t PRTSL2     : 1;
+  __IO  uint8_t PRTSL3     : 1;
+} stc_adc_prtsl_field_t;
+
+typedef struct stc_adc_sctsl_field
+{
+  __IO  uint8_t SCTSL0     : 1;
+  __IO  uint8_t SCTSL1     : 1;
+  __IO  uint8_t SCTSL2     : 1;
+  __IO  uint8_t SCTSL3     : 1;
+} stc_adc_sctsl_field_t;
+
+typedef struct stc_adc_adcen_field
+{
+  __IO  uint8_t ENBL       : 1;
+  __IO  uint8_t READY      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CYCLSL0    : 1;
+  __IO  uint8_t CYCLSL1    : 1;
+} stc_adc_adcen_field_t;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CRTRIM_MODULE register bit fields */
+typedef struct stc_crtrim_mcr_psr_field
+{
+  __IO  uint8_t CSR0       : 1;
+  __IO  uint8_t CSR1       : 1;
+} stc_crtrim_mcr_psr_field_t;
+
+typedef struct stc_crtrim_mcr_ftrm_field
+{
+  __IO uint16_t TRD0       : 1;
+  __IO uint16_t TRD1       : 1;
+  __IO uint16_t TRD2       : 1;
+  __IO uint16_t TRD3       : 1;
+  __IO uint16_t TRD4       : 1;
+  __IO uint16_t TRD5       : 1;
+  __IO uint16_t TRD6       : 1;
+  __IO uint16_t TRD7       : 1;
+} stc_crtrim_mcr_ftrm_field_t;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* EXTI_MODULE registEN bit fields */
+typedef struct stc_exti_enir_field
+{
+  __IO uint16_t EN0        : 1;
+  __IO uint16_t EN1        : 1;
+  __IO uint16_t EN2        : 1;
+  __IO uint16_t EN3        : 1;
+  __IO uint16_t EN4        : 1;
+  __IO uint16_t EN5        : 1;
+  __IO uint16_t EN6        : 1;
+  __IO uint16_t EN7        : 1;
+  __IO uint16_t EN8        : 1;
+  __IO uint16_t EN9        : 1;
+  __IO uint16_t EN10       : 1;
+  __IO uint16_t EN11       : 1;
+  __IO uint16_t EN12       : 1;
+  __IO uint16_t EN13       : 1;
+  __IO uint16_t EN14       : 1;
+  __IO uint16_t EN15       : 1;
+  __IO uint16_t EN16       : 1;
+  __IO uint16_t EN17       : 1;
+  __IO uint16_t EN18       : 1;
+  __IO uint16_t EN19       : 1;
+  __IO uint16_t EN20       : 1;
+  __IO uint16_t EN21       : 1;
+  __IO uint16_t EN22       : 1;
+  __IO uint16_t EN23       : 1;
+  __IO uint16_t EN24       : 1;
+  __IO uint16_t EN25       : 1;
+  __IO uint16_t EN26       : 1;
+  __IO uint16_t EN27       : 1;
+  __IO uint16_t EN28       : 1;
+  __IO uint16_t EN29       : 1;
+  __IO uint16_t EN30       : 1;
+  __IO uint16_t EN31       : 1;
+} stc_exti_enir_field_t;
+
+typedef struct stc_exti_eirr_field
+{
+  __IO uint16_t ER0        : 1;
+  __IO uint16_t ER1        : 1;
+  __IO uint16_t ER2        : 1;
+  __IO uint16_t ER3        : 1;
+  __IO uint16_t ER4        : 1;
+  __IO uint16_t ER5        : 1;
+  __IO uint16_t ER6        : 1;
+  __IO uint16_t ER7        : 1;
+  __IO uint16_t ER8        : 1;
+  __IO uint16_t ER9        : 1;
+  __IO uint16_t ER10       : 1;
+  __IO uint16_t ER11       : 1;
+  __IO uint16_t ER12       : 1;
+  __IO uint16_t ER13       : 1;
+  __IO uint16_t ER14       : 1;
+  __IO uint16_t ER15       : 1;
+  __IO uint16_t ER16       : 1;
+  __IO uint16_t ER17       : 1;
+  __IO uint16_t ER18       : 1;
+  __IO uint16_t ER19       : 1;
+  __IO uint16_t ER20       : 1;
+  __IO uint16_t ER21       : 1;
+  __IO uint16_t ER22       : 1;
+  __IO uint16_t ER23       : 1;
+  __IO uint16_t ER24       : 1;
+  __IO uint16_t ER25       : 1;
+  __IO uint16_t ER26       : 1;
+  __IO uint16_t ER27       : 1;
+  __IO uint16_t ER28       : 1;
+  __IO uint16_t ER29       : 1;
+  __IO uint16_t ER30       : 1;
+  __IO uint16_t ER31       : 1;
+} stc_exti_eirr_field_t;
+
+typedef struct stc_exti_eicl_field
+{
+  __IO uint16_t ECL0       : 1;
+  __IO uint16_t ECL1       : 1;
+  __IO uint16_t ECL2       : 1;
+  __IO uint16_t ECL3       : 1;
+  __IO uint16_t ECL4       : 1;
+  __IO uint16_t ECL5       : 1;
+  __IO uint16_t ECL6       : 1;
+  __IO uint16_t ECL7       : 1;
+  __IO uint16_t ECL8       : 1;
+  __IO uint16_t ECL9       : 1;
+  __IO uint16_t ECL10      : 1;
+  __IO uint16_t ECL11      : 1;
+  __IO uint16_t ECL12      : 1;
+  __IO uint16_t ECL13      : 1;
+  __IO uint16_t ECL14      : 1;
+  __IO uint16_t ECL15      : 1;
+  __IO uint16_t ECL16      : 1;
+  __IO uint16_t ECL17      : 1;
+  __IO uint16_t ECL18      : 1;
+  __IO uint16_t ECL19      : 1;
+  __IO uint16_t ECL20      : 1;
+  __IO uint16_t ECL21      : 1;
+  __IO uint16_t ECL22      : 1;
+  __IO uint16_t ECL23      : 1;
+  __IO uint16_t ECL24      : 1;
+  __IO uint16_t ECL25      : 1;
+  __IO uint16_t ECL26      : 1;
+  __IO uint16_t ECL27      : 1;
+  __IO uint16_t ECL28      : 1;
+  __IO uint16_t ECL29      : 1;
+  __IO uint16_t ECL30      : 1;
+  __IO uint16_t ECL31      : 1;
+} stc_exti_eicl_field_t;
+
+typedef struct stc_exti_elvr_field
+{
+  __IO uint32_t LA0        : 1;
+  __IO uint32_t LB0        : 1;
+  __IO uint32_t LA1        : 1;
+  __IO uint32_t LB1        : 1;
+  __IO uint32_t LA2        : 1;
+  __IO uint32_t LB2        : 1;
+  __IO uint32_t LA3        : 1;
+  __IO uint32_t LB3        : 1;
+  __IO uint32_t LA4        : 1;
+  __IO uint32_t LB4        : 1;
+  __IO uint32_t LA5        : 1;
+  __IO uint32_t LB5        : 1;
+  __IO uint32_t LA6        : 1;
+  __IO uint32_t LB6        : 1;
+  __IO uint32_t LA7        : 1;
+  __IO uint32_t LB7        : 1;
+  __IO uint32_t LA8        : 1;
+  __IO uint32_t LB8        : 1;
+  __IO uint32_t LA9        : 1;
+  __IO uint32_t LB9        : 1;
+  __IO uint32_t LA10       : 1;
+  __IO uint32_t LB10       : 1;
+  __IO uint32_t LA11       : 1;
+  __IO uint32_t LB11       : 1;
+  __IO uint32_t LA12       : 1;
+  __IO uint32_t LB12       : 1;
+  __IO uint32_t LA13       : 1;
+  __IO uint32_t LB13       : 1;
+  __IO uint32_t LA14       : 1;
+  __IO uint32_t LB14       : 1;
+  __IO uint32_t LA15       : 1;
+  __IO uint32_t LB15       : 1;
+} stc_exti_elvr_field_t;
+
+typedef struct stc_exti_elvr1_field
+{
+  __IO uint32_t LA16       : 1;
+  __IO uint32_t LB16       : 1;
+  __IO uint32_t LA17       : 1;
+  __IO uint32_t LB17       : 1;
+  __IO uint32_t LA18       : 1;
+  __IO uint32_t LB18       : 1;
+  __IO uint32_t LA19       : 1;
+  __IO uint32_t LB19       : 1;
+  __IO uint32_t LA20       : 1;
+  __IO uint32_t LB20       : 1;
+  __IO uint32_t LA21       : 1;
+  __IO uint32_t LB21       : 1;
+  __IO uint32_t LA22       : 1;
+  __IO uint32_t LB22       : 1;
+  __IO uint32_t LA23       : 1;
+  __IO uint32_t LB23       : 1;
+  __IO uint32_t LA24       : 1;
+  __IO uint32_t LB24       : 1;
+  __IO uint32_t LA25       : 1;
+  __IO uint32_t LB25       : 1;
+  __IO uint32_t LA26       : 1;
+  __IO uint32_t LB26       : 1;
+  __IO uint32_t LA27       : 1;
+  __IO uint32_t LB27       : 1;
+  __IO uint32_t LA28       : 1;
+  __IO uint32_t LB28       : 1;
+  __IO uint32_t LA29       : 1;
+  __IO uint32_t LB29       : 1;
+  __IO uint32_t LA30       : 1;
+  __IO uint32_t LB30       : 1;
+  __IO uint32_t LA31       : 1;
+  __IO uint32_t LB31       : 1;
+} stc_exti_elvr1_field_t;
+
+typedef struct stc_exti_nmirr_field
+{
+  __IO  uint8_t NR0        : 1;
+} stc_exti_nmirr_field_t;
+
+typedef struct stc_exti_nmicl_field
+{
+  __IO  uint8_t NCL0       : 1;
+} stc_exti_nmicl_field_t;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* INTREQ_MODULE register bit fields */
+typedef struct stc_intreq_drqsel_field
+{
+  __IO uint32_t DRQSEL0    : 1;
+  __IO uint32_t DRQSEL1    : 1;
+  __IO uint32_t DRQSEL2    : 1;
+  __IO uint32_t DRQSEL3    : 1;
+  __IO uint32_t DRQSEL4    : 1;
+  __IO uint32_t DRQSEL5    : 1;
+  __IO uint32_t DRQSEL6    : 1;
+  __IO uint32_t DRQSEL7    : 1;
+  __IO uint32_t DRQSEL8    : 1;
+  __IO uint32_t DRQSEL9    : 1;
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+  __IO uint32_t DRQSEL15   : 1;
+  __IO uint32_t DRQSEL16   : 1;
+  __IO uint32_t DRQSEL17   : 1;
+  __IO uint32_t DRQSEL18   : 1;
+  __IO uint32_t DRQSEL19   : 1;
+  __IO uint32_t DRQSEL20   : 1;
+  __IO uint32_t DRQSEL21   : 1;
+  __IO uint32_t DRQSEL22   : 1;
+  __IO uint32_t DRQSEL23   : 1;
+  __IO uint32_t DRQSEL24   : 1;
+  __IO uint32_t DRQSEL25   : 1;
+  __IO uint32_t DRQSEL26   : 1;
+  __IO uint32_t DRQSEL27   : 1;
+  __IO uint32_t DRQSEL28   : 1;
+  __IO uint32_t DRQSEL29   : 1;
+  __IO uint32_t DRQSEL30   : 1;
+  __IO uint32_t DRQSEL31   : 1;
+} stc_intreq_drqsel_field_t;
+
+typedef struct stc_intreq_oddpks_field
+{
+  __IO  uint8_t ODDPKS0    : 1;
+  __IO  uint8_t ODDPKS1    : 1;
+  __IO  uint8_t ODDPKS2    : 1;
+  __IO  uint8_t ODDPKS3    : 1;
+  __IO  uint8_t ODDPKS4    : 1;
+} stc_intreq_oddpks_field_t;
+
+typedef struct stc_intreq_exc02mon_field
+{
+  __IO uint32_t NMI        : 1;
+  __IO uint32_t HWINT      : 1;
+} stc_intreq_exc02mon_field_t;
+
+typedef struct stc_intreq_irq00mon_field
+{
+  __IO uint32_t FCSINT     : 1;
+} stc_intreq_irq00mon_field_t;
+
+typedef struct stc_intreq_irq01mon_field
+{
+  __IO uint32_t SWWDTINT   : 1;
+} stc_intreq_irq01mon_field_t;
+
+typedef struct stc_intreq_irq02mon_field
+{
+  __IO uint32_t LVDINT     : 1;
+} stc_intreq_irq02mon_field_t;
+
+typedef struct stc_intreq_irq03mon_field
+{
+  __IO uint32_t WAVE0INT0  : 1;
+  __IO uint32_t WAVE0INT1  : 1;
+  __IO uint32_t WAVE0INT2  : 1;
+  __IO uint32_t WAVE0INT3  : 1;
+  __IO uint32_t WAVE1INT0  : 1;
+  __IO uint32_t WAVE1INT1  : 1;
+  __IO uint32_t WAVE1INT2  : 1;
+  __IO uint32_t WAVE1INT3  : 1;
+  __IO uint32_t WAVE2INT0  : 1;
+  __IO uint32_t WAVE2INT1  : 1;
+  __IO uint32_t WAVE2INT2  : 1;
+  __IO uint32_t WAVE2INT3  : 1;
+} stc_intreq_irq03mon_field_t;
+
+typedef struct stc_intreq_irq04mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+} stc_intreq_irq04mon_field_t;
+
+typedef struct stc_intreq_irq05mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+  __IO uint32_t EXTINT8    : 1;
+  __IO uint32_t EXTINT9    : 1;
+  __IO uint32_t EXTINT10   : 1;
+  __IO uint32_t EXTINT11   : 1;
+  __IO uint32_t EXTINT12   : 1;
+  __IO uint32_t EXTINT13   : 1;
+  __IO uint32_t EXTINT14   : 1;
+  __IO uint32_t EXTINT15   : 1;
+  __IO uint32_t EXTINT16   : 1;
+  __IO uint32_t EXTINT17   : 1;
+  __IO uint32_t EXTINT18   : 1;
+  __IO uint32_t EXTINT19   : 1;
+  __IO uint32_t EXTINT20   : 1;
+  __IO uint32_t EXTINT21   : 1;
+  __IO uint32_t EXTINT22   : 1;
+  __IO uint32_t EXTINT23   : 1;
+} stc_intreq_irq05mon_field_t;
+
+typedef struct stc_intreq_irq06mon_field
+{
+  __IO uint32_t TIMINT1    : 1;
+  __IO uint32_t TIMINT2    : 1;
+  __IO uint32_t QUD0INT0   : 1;
+  __IO uint32_t QUD0INT1   : 1;
+  __IO uint32_t QUD0INT2   : 1;
+  __IO uint32_t QUD0INT3   : 1;
+  __IO uint32_t QUD0INT4   : 1;
+  __IO uint32_t QUD0INT5   : 1;
+  __IO uint32_t QUD1INT0   : 1;
+  __IO uint32_t QUD1INT1   : 1;
+  __IO uint32_t QUD1INT2   : 1;
+  __IO uint32_t QUD1INT3   : 1;
+  __IO uint32_t QUD1INT4   : 1;
+  __IO uint32_t QUD1INT5   : 1;
+  __IO uint32_t QUD2INT0   : 1;
+  __IO uint32_t QUD2INT1   : 1;
+  __IO uint32_t QUD2INT2   : 1;
+  __IO uint32_t QUD2INT3   : 1;
+  __IO uint32_t QUD2INT4   : 1;
+  __IO uint32_t QUD2INT5   : 1;
+} stc_intreq_irq06mon_field_t;
+
+typedef struct stc_intreq_irq07mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq07mon_field_t;
+
+typedef struct stc_intreq_irq08mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq08mon_field_t;
+
+typedef struct stc_intreq_irq09mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq09mon_field_t;
+
+typedef struct stc_intreq_irq10mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq10mon_field_t;
+
+typedef struct stc_intreq_irq11mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq11mon_field_t;
+
+typedef struct stc_intreq_irq12mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq12mon_field_t;
+
+typedef struct stc_intreq_irq13mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq13mon_field_t;
+
+typedef struct stc_intreq_irq14mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq14mon_field_t;
+
+typedef struct stc_intreq_irq15mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq15mon_field_t;
+
+typedef struct stc_intreq_irq16mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq16mon_field_t;
+
+typedef struct stc_intreq_irq17mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq17mon_field_t;
+
+typedef struct stc_intreq_irq18mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq18mon_field_t;
+
+typedef struct stc_intreq_irq19mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq19mon_field_t;
+
+typedef struct stc_intreq_irq20mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq20mon_field_t;
+
+typedef struct stc_intreq_irq21mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq21mon_field_t;
+
+typedef struct stc_intreq_irq22mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq22mon_field_t;
+
+typedef struct stc_intreq_irq23mon_field
+{
+  __IO uint32_t PPGINT0    : 1;
+  __IO uint32_t PPGINT1    : 1;
+  __IO uint32_t PPGINT2    : 1;
+  __IO uint32_t PPGINT3    : 1;
+  __IO uint32_t PPGINT4    : 1;
+  __IO uint32_t PPGINT5    : 1;
+  __IO uint32_t PPGINT6    : 1;
+  __IO uint32_t PPGINT7    : 1;
+  __IO uint32_t PPGINT8    : 1;
+} stc_intreq_irq23mon_field_t;
+
+typedef struct stc_intreq_irq24mon_field
+{
+  __IO uint32_t MOSCINT    : 1;
+  __IO uint32_t SOSCINT    : 1;
+  __IO uint32_t MPLLINT    : 1;
+  __IO uint32_t UPLLINT    : 1;
+  __IO uint32_t WCINT      : 1;
+} stc_intreq_irq24mon_field_t;
+
+typedef struct stc_intreq_irq25mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq25mon_field_t;
+
+typedef struct stc_intreq_irq26mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq26mon_field_t;
+
+typedef struct stc_intreq_irq27mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq27mon_field_t;
+
+typedef struct stc_intreq_irq28mon_field
+{
+  __IO uint32_t FRT0INT0   : 1;
+  __IO uint32_t FRT0INT1   : 1;
+  __IO uint32_t FRT0INT2   : 1;
+  __IO uint32_t FRT0INT3   : 1;
+  __IO uint32_t FRT0INT4   : 1;
+  __IO uint32_t FRT0INT5   : 1;
+  __IO uint32_t FRT1INT0   : 1;
+  __IO uint32_t FRT1INT1   : 1;
+  __IO uint32_t FRT1INT2   : 1;
+  __IO uint32_t FRT1INT3   : 1;
+  __IO uint32_t FRT1INT4   : 1;
+  __IO uint32_t FRT1INT5   : 1;
+  __IO uint32_t FRT2INT0   : 1;
+  __IO uint32_t FRT2INT1   : 1;
+  __IO uint32_t FRT2INT2   : 1;
+  __IO uint32_t FRT2INT3   : 1;
+  __IO uint32_t FRT2INT4   : 1;
+  __IO uint32_t FRT2INT5   : 1;
+} stc_intreq_irq28mon_field_t;
+
+typedef struct stc_intreq_irq29mon_field
+{
+  __IO uint32_t ICU0INT0   : 1;
+  __IO uint32_t ICU0INT1   : 1;
+  __IO uint32_t ICU0INT2   : 1;
+  __IO uint32_t ICU0INT3   : 1;
+  __IO uint32_t ICU1INT0   : 1;
+  __IO uint32_t ICU1INT1   : 1;
+  __IO uint32_t ICU1INT2   : 1;
+  __IO uint32_t ICU1INT3   : 1;
+  __IO uint32_t ICU2INT0   : 1;
+  __IO uint32_t ICU2INT1   : 1;
+  __IO uint32_t ICU2INT2   : 1;
+  __IO uint32_t ICU2INT3   : 1;
+} stc_intreq_irq29mon_field_t;
+
+typedef struct stc_intreq_irq30mon_field
+{
+  __IO uint32_t OCU0INT0   : 1;
+  __IO uint32_t OCU0INT1   : 1;
+  __IO uint32_t OCU0INT2   : 1;
+  __IO uint32_t OCU0INT3   : 1;
+  __IO uint32_t OCU0INT4   : 1;
+  __IO uint32_t OCU0INT5   : 1;
+  __IO uint32_t OCU1INT0   : 1;
+  __IO uint32_t OCU1INT1   : 1;
+  __IO uint32_t OCU1INT2   : 1;
+  __IO uint32_t OCU1INT3   : 1;
+  __IO uint32_t OCU1INT4   : 1;
+  __IO uint32_t OCU1INT5   : 1;
+  __IO uint32_t OCU2INT0   : 1;
+  __IO uint32_t OCU2INT1   : 1;
+  __IO uint32_t OCU2INT2   : 1;
+  __IO uint32_t OCU2INT3   : 1;
+  __IO uint32_t OCU2INT4   : 1;
+  __IO uint32_t OCU2INT5   : 1;
+} stc_intreq_irq30mon_field_t;
+
+typedef struct stc_intreq_irq31mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq31mon_field_t;
+
+typedef struct stc_intreq_irq32mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC0SBD    : 1;
+  __IO uint32_t MAC0PMI    : 1;
+  __IO uint32_t MAC0LPI    : 1;
+} stc_intreq_irq32mon_field_t;
+
+typedef struct stc_intreq_irq33mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC1SBD    : 1;
+  __IO uint32_t MAC1PMI    : 1;
+} stc_intreq_irq33mon_field_t;
+
+typedef struct stc_intreq_irq34mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+} stc_intreq_irq34mon_field_t;
+
+typedef struct stc_intreq_irq35mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+  __IO uint32_t USB0INT5   : 1;
+} stc_intreq_irq35mon_field_t;
+
+typedef struct stc_intreq_irq36mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+} stc_intreq_irq36mon_field_t;
+
+typedef struct stc_intreq_irq37mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+  __IO uint32_t USB1INT5   : 1;
+} stc_intreq_irq37mon_field_t;
+
+typedef struct stc_intreq_irq38mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq38mon_field_t;
+
+typedef struct stc_intreq_irq39mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq39mon_field_t;
+
+typedef struct stc_intreq_irq40mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq40mon_field_t;
+
+typedef struct stc_intreq_irq41mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq41mon_field_t;
+
+typedef struct stc_intreq_irq42mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq42mon_field_t;
+
+typedef struct stc_intreq_irq43mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq43mon_field_t;
+
+typedef struct stc_intreq_irq44mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq44mon_field_t;
+
+typedef struct stc_intreq_irq45mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq45mon_field_t;
+
+typedef struct stc_intreq_irq46mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq46mon_field_t;
+
+typedef struct stc_intreq_drqsel1_field
+{
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+} stc_intreq_drqsel1_field_t;
+
+typedef struct stc_intreq_dqesel_field
+{
+  __IO uint32_t ESEL100    : 1;
+  __IO uint32_t ESEL101    : 1;
+  __IO uint32_t ESEL102    : 1;
+  __IO uint32_t ESEL103    : 1;
+  __IO uint32_t ESEL110    : 1;
+  __IO uint32_t ESEL111    : 1;
+  __IO uint32_t ESEL112    : 1;
+  __IO uint32_t ESEL113    : 1;
+  __IO uint32_t ESEL240    : 1;
+  __IO uint32_t ESEL241    : 1;
+  __IO uint32_t ESEL242    : 1;
+  __IO uint32_t ESEL243    : 1;
+  __IO uint32_t ESEL250    : 1;
+  __IO uint32_t ESEL251    : 1;
+  __IO uint32_t ESEL252    : 1;
+  __IO uint32_t ESEL253    : 1;
+  __IO uint32_t ESEL260    : 1;
+  __IO uint32_t ESEL261    : 1;
+  __IO uint32_t ESEL262    : 1;
+  __IO uint32_t ESEL263    : 1;
+  __IO uint32_t ESEL270    : 1;
+  __IO uint32_t ESEL271    : 1;
+  __IO uint32_t ESEL272    : 1;
+  __IO uint32_t ESEL273    : 1;
+  __IO uint32_t ESEL300    : 1;
+  __IO uint32_t ESEL301    : 1;
+  __IO uint32_t ESEL302    : 1;
+  __IO uint32_t ESEL303    : 1;
+  __IO uint32_t ESEL310    : 1;
+  __IO uint32_t ESEL311    : 1;
+  __IO uint32_t ESEL312    : 1;
+  __IO uint32_t ESEL313    : 1;
+} stc_intreq_dqesel_field_t;
+
+typedef struct stc_intreq_oddpks1_field
+{
+  __IO  uint8_t ODDPKS10   : 1;
+  __IO  uint8_t ODDPKS11   : 1;
+  __IO  uint8_t ODDPKS12   : 1;
+  __IO  uint8_t ODDPKS13   : 1;
+  __IO  uint8_t ODDPKS14   : 1;
+} stc_intreq_oddpks1_field_t;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* GPIO_MODULE register bit fields */
+typedef struct stc_gpio_pfr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr0_field_t;
+
+typedef struct stc_gpio_pfr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr1_field_t;
+
+typedef struct stc_gpio_pfr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr2_field_t;
+
+typedef struct stc_gpio_pfr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr3_field_t;
+
+typedef struct stc_gpio_pfr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pfr4_field_t;
+
+typedef struct stc_gpio_pfr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pfr5_field_t;
+
+typedef struct stc_gpio_pfr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pfr6_field_t;
+
+typedef struct stc_gpio_pfr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr7_field_t;
+
+typedef struct stc_gpio_pfr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfr8_field_t;
+
+typedef struct stc_gpio_pfr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pfr9_field_t;
+
+typedef struct stc_gpio_pfra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pfra_field_t;
+
+typedef struct stc_gpio_pfrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pfrb_field_t;
+
+typedef struct stc_gpio_pfrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfrc_field_t;
+
+typedef struct stc_gpio_pfrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfrd_field_t;
+
+typedef struct stc_gpio_pfre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfre_field_t;
+
+typedef struct stc_gpio_pfrf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pfrf_field_t;
+
+typedef struct stc_gpio_pcr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr0_field_t;
+
+typedef struct stc_gpio_pcr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr1_field_t;
+
+typedef struct stc_gpio_pcr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr2_field_t;
+
+typedef struct stc_gpio_pcr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr3_field_t;
+
+typedef struct stc_gpio_pcr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pcr4_field_t;
+
+typedef struct stc_gpio_pcr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pcr5_field_t;
+
+typedef struct stc_gpio_pcr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pcr6_field_t;
+
+typedef struct stc_gpio_pcr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr7_field_t;
+
+typedef struct stc_gpio_pcr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pcr9_field_t;
+
+typedef struct stc_gpio_pcra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pcra_field_t;
+
+typedef struct stc_gpio_pcrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pcrb_field_t;
+
+typedef struct stc_gpio_pcrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcrc_field_t;
+
+typedef struct stc_gpio_pcrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcrd_field_t;
+
+typedef struct stc_gpio_pcre_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcre_field_t;
+
+typedef struct stc_gpio_ddr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr0_field_t;
+
+typedef struct stc_gpio_ddr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr1_field_t;
+
+typedef struct stc_gpio_ddr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr2_field_t;
+
+typedef struct stc_gpio_ddr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr3_field_t;
+
+typedef struct stc_gpio_ddr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_ddr4_field_t;
+
+typedef struct stc_gpio_ddr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_ddr5_field_t;
+
+typedef struct stc_gpio_ddr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_ddr6_field_t;
+
+typedef struct stc_gpio_ddr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr7_field_t;
+
+typedef struct stc_gpio_ddr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddr8_field_t;
+
+typedef struct stc_gpio_ddr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_ddr9_field_t;
+
+typedef struct stc_gpio_ddra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_ddra_field_t;
+
+typedef struct stc_gpio_ddrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_ddrb_field_t;
+
+typedef struct stc_gpio_ddrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddrc_field_t;
+
+typedef struct stc_gpio_ddrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddrd_field_t;
+
+typedef struct stc_gpio_ddre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddre_field_t;
+
+typedef struct stc_gpio_ddrf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_ddrf_field_t;
+
+typedef struct stc_gpio_pdir0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir0_field_t;
+
+typedef struct stc_gpio_pdir1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir1_field_t;
+
+typedef struct stc_gpio_pdir2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir2_field_t;
+
+typedef struct stc_gpio_pdir3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir3_field_t;
+
+typedef struct stc_gpio_pdir4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdir4_field_t;
+
+typedef struct stc_gpio_pdir5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pdir5_field_t;
+
+typedef struct stc_gpio_pdir6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdir6_field_t;
+
+typedef struct stc_gpio_pdir7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir7_field_t;
+
+typedef struct stc_gpio_pdir8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdir8_field_t;
+
+typedef struct stc_gpio_pdir9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdir9_field_t;
+
+typedef struct stc_gpio_pdira_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdira_field_t;
+
+typedef struct stc_gpio_pdirb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pdirb_field_t;
+
+typedef struct stc_gpio_pdirc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdirc_field_t;
+
+typedef struct stc_gpio_pdird_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdird_field_t;
+
+typedef struct stc_gpio_pdire_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdire_field_t;
+
+typedef struct stc_gpio_pdirf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdirf_field_t;
+
+typedef struct stc_gpio_pdor0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor0_field_t;
+
+typedef struct stc_gpio_pdor1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor1_field_t;
+
+typedef struct stc_gpio_pdor2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor2_field_t;
+
+typedef struct stc_gpio_pdor3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor3_field_t;
+
+typedef struct stc_gpio_pdor4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdor4_field_t;
+
+typedef struct stc_gpio_pdor5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pdor5_field_t;
+
+typedef struct stc_gpio_pdor6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdor6_field_t;
+
+typedef struct stc_gpio_pdor7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor7_field_t;
+
+typedef struct stc_gpio_pdor8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdor8_field_t;
+
+typedef struct stc_gpio_pdor9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdor9_field_t;
+
+typedef struct stc_gpio_pdora_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdora_field_t;
+
+typedef struct stc_gpio_pdorb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pdorb_field_t;
+
+typedef struct stc_gpio_pdorc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdorc_field_t;
+
+typedef struct stc_gpio_pdord_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdord_field_t;
+
+typedef struct stc_gpio_pdore_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdore_field_t;
+
+typedef struct stc_gpio_pdorf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdorf_field_t;
+
+typedef struct stc_gpio_ade_field
+{
+  __IO uint32_t AN0        : 1;
+  __IO uint32_t AN1        : 1;
+  __IO uint32_t AN2        : 1;
+  __IO uint32_t AN3        : 1;
+  __IO uint32_t AN4        : 1;
+  __IO uint32_t AN5        : 1;
+  __IO uint32_t AN6        : 1;
+  __IO uint32_t AN7        : 1;
+  __IO uint32_t AN8        : 1;
+  __IO uint32_t AN9        : 1;
+  __IO uint32_t AN10       : 1;
+  __IO uint32_t AN11       : 1;
+  __IO uint32_t AN12       : 1;
+  __IO uint32_t AN13       : 1;
+  __IO uint32_t AN14       : 1;
+  __IO uint32_t AN15       : 1;
+  __IO uint32_t AN16       : 1;
+  __IO uint32_t AN17       : 1;
+  __IO uint32_t AN18       : 1;
+  __IO uint32_t AN19       : 1;
+  __IO uint32_t AN20       : 1;
+  __IO uint32_t AN21       : 1;
+  __IO uint32_t AN22       : 1;
+  __IO uint32_t AN23       : 1;
+  __IO uint32_t AN24       : 1;
+  __IO uint32_t AN25       : 1;
+  __IO uint32_t AN26       : 1;
+  __IO uint32_t AN27       : 1;
+  __IO uint32_t AN28       : 1;
+  __IO uint32_t AN29       : 1;
+  __IO uint32_t AN30       : 1;
+  __IO uint32_t AN31       : 1;
+} stc_gpio_ade_field_t;
+
+typedef struct stc_gpio_spsr_field
+{
+  __IO uint32_t SUBXC      : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAINXC     : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USB0C      : 1;
+  __IO uint32_t USB1C      : 1;
+} stc_gpio_spsr_field_t;
+
+typedef struct stc_gpio_epfr00_field
+{
+  __IO uint32_t NMIS       : 1;
+  __IO uint32_t CROUTE0    : 1;
+  __IO uint32_t CROUTE1    : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t SUBOUTE0   : 1;
+  __IO uint32_t SUBOUTE1   : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USBP0E     : 1;
+       uint32_t RESERVED3  : 3;
+  __IO uint32_t USBP1E     : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t JTAGEN0B   : 1;
+  __IO uint32_t JTAGEN1S   : 1;
+       uint32_t RESERVED5  : 6;
+  __IO uint32_t TRC0E      : 1;
+  __IO uint32_t TRC1E      : 1;
+} stc_gpio_epfr00_field_t;
+
+typedef struct stc_gpio_epfr01_field
+{
+  __IO uint32_t RTO00E0    : 1;
+  __IO uint32_t RTO00E1    : 1;
+  __IO uint32_t RTO01E0    : 1;
+  __IO uint32_t RTO01E1    : 1;
+  __IO uint32_t RTO02E0    : 1;
+  __IO uint32_t RTO02E1    : 1;
+  __IO uint32_t RTO03E0    : 1;
+  __IO uint32_t RTO03E1    : 1;
+  __IO uint32_t RTO04E0    : 1;
+  __IO uint32_t RTO04E1    : 1;
+  __IO uint32_t RTO05E0    : 1;
+  __IO uint32_t RTO05E1    : 1;
+  __IO uint32_t DTTI0C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI0S0    : 1;
+  __IO uint32_t DTTI0S1    : 1;
+  __IO uint32_t FRCK0S0    : 1;
+  __IO uint32_t FRCK0S1    : 1;
+  __IO uint32_t IC00S0     : 1;
+  __IO uint32_t IC00S1     : 1;
+  __IO uint32_t IC00S2     : 1;
+  __IO uint32_t IC01S0     : 1;
+  __IO uint32_t IC01S1     : 1;
+  __IO uint32_t IC01S2     : 1;
+  __IO uint32_t IC02S0     : 1;
+  __IO uint32_t IC02S1     : 1;
+  __IO uint32_t IC02S2     : 1;
+  __IO uint32_t IC03S0     : 1;
+  __IO uint32_t IC03S1     : 1;
+  __IO uint32_t IC03S2     : 1;
+} stc_gpio_epfr01_field_t;
+
+typedef struct stc_gpio_epfr02_field
+{
+  __IO uint32_t RTO10E0    : 1;
+  __IO uint32_t RTO10E1    : 1;
+  __IO uint32_t RTO11E0    : 1;
+  __IO uint32_t RTO11E1    : 1;
+  __IO uint32_t RTO12E0    : 1;
+  __IO uint32_t RTO12E1    : 1;
+  __IO uint32_t RTO13E0    : 1;
+  __IO uint32_t RTO13E1    : 1;
+  __IO uint32_t RTO14E0    : 1;
+  __IO uint32_t RTO14E1    : 1;
+  __IO uint32_t RTO15E0    : 1;
+  __IO uint32_t RTO15E1    : 1;
+  __IO uint32_t DTTI1C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI1S0    : 1;
+  __IO uint32_t DTTI1S1    : 1;
+  __IO uint32_t FRCK1S0    : 1;
+  __IO uint32_t FRCK1S1    : 1;
+  __IO uint32_t IC10S0     : 1;
+  __IO uint32_t IC10S1     : 1;
+  __IO uint32_t IC10S2     : 1;
+  __IO uint32_t IC11S0     : 1;
+  __IO uint32_t IC11S1     : 1;
+  __IO uint32_t IC11S2     : 1;
+  __IO uint32_t IC12S0     : 1;
+  __IO uint32_t IC12S1     : 1;
+  __IO uint32_t IC12S2     : 1;
+  __IO uint32_t IC13S0     : 1;
+  __IO uint32_t IC13S1     : 1;
+  __IO uint32_t IC13S2     : 1;
+} stc_gpio_epfr02_field_t;
+
+typedef struct stc_gpio_epfr03_field
+{
+  __IO uint32_t RTO20E0    : 1;
+  __IO uint32_t RTO20E1    : 1;
+  __IO uint32_t RTO21E0    : 1;
+  __IO uint32_t RTO21E1    : 1;
+  __IO uint32_t RTO22E0    : 1;
+  __IO uint32_t RTO22E1    : 1;
+  __IO uint32_t RTO23E0    : 1;
+  __IO uint32_t RTO23E1    : 1;
+  __IO uint32_t RTO24E0    : 1;
+  __IO uint32_t RTO24E1    : 1;
+  __IO uint32_t RTO25E0    : 1;
+  __IO uint32_t RTO25E1    : 1;
+  __IO uint32_t DTTI2C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI2S0    : 1;
+  __IO uint32_t DTTI2S1    : 1;
+  __IO uint32_t FRCK2S0    : 1;
+  __IO uint32_t FRCK2S1    : 1;
+  __IO uint32_t IC20S0     : 1;
+  __IO uint32_t IC20S1     : 1;
+  __IO uint32_t IC20S2     : 1;
+  __IO uint32_t IC21S0     : 1;
+  __IO uint32_t IC21S1     : 1;
+  __IO uint32_t IC21S2     : 1;
+  __IO uint32_t IC22S0     : 1;
+  __IO uint32_t IC22S1     : 1;
+  __IO uint32_t IC22S2     : 1;
+  __IO uint32_t IC23S0     : 1;
+  __IO uint32_t IC23S1     : 1;
+  __IO uint32_t IC23S2     : 1;
+} stc_gpio_epfr03_field_t;
+
+typedef struct stc_gpio_epfr04_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA0E0    : 1;
+  __IO uint32_t TIOA0E1    : 1;
+  __IO uint32_t TIOB0S0    : 1;
+  __IO uint32_t TIOB0S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA1S0    : 1;
+  __IO uint32_t TIOA1S1    : 1;
+  __IO uint32_t TIOA1E0    : 1;
+  __IO uint32_t TIOA1E1    : 1;
+  __IO uint32_t TIOB1S0    : 1;
+  __IO uint32_t TIOB1S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA2E0    : 1;
+  __IO uint32_t TIOA2E1    : 1;
+  __IO uint32_t TIOB2S0    : 1;
+  __IO uint32_t TIOB2S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA3S0    : 1;
+  __IO uint32_t TIOA3S1    : 1;
+  __IO uint32_t TIOA3E0    : 1;
+  __IO uint32_t TIOA3E1    : 1;
+  __IO uint32_t TIOB3S0    : 1;
+  __IO uint32_t TIOB3S1    : 1;
+} stc_gpio_epfr04_field_t;
+
+typedef struct stc_gpio_epfr05_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA4E0    : 1;
+  __IO uint32_t TIOA4E1    : 1;
+  __IO uint32_t TIOB4S0    : 1;
+  __IO uint32_t TIOB4S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA5S0    : 1;
+  __IO uint32_t TIOA5S1    : 1;
+  __IO uint32_t TIOA5E0    : 1;
+  __IO uint32_t TIOA5E1    : 1;
+  __IO uint32_t TIOB5S0    : 1;
+  __IO uint32_t TIOB5S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA6E0    : 1;
+  __IO uint32_t TIOA6E1    : 1;
+  __IO uint32_t TIOB6S0    : 1;
+  __IO uint32_t TIOB6S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA7S0    : 1;
+  __IO uint32_t TIOA7S1    : 1;
+  __IO uint32_t TIOA7E0    : 1;
+  __IO uint32_t TIOA7E1    : 1;
+  __IO uint32_t TIOB7S0    : 1;
+  __IO uint32_t TIOB7S1    : 1;
+} stc_gpio_epfr05_field_t;
+
+typedef struct stc_gpio_epfr06_field
+{
+  __IO uint32_t EINT00S0   : 1;
+  __IO uint32_t EINT00S1   : 1;
+  __IO uint32_t EINT01S0   : 1;
+  __IO uint32_t EINT01S1   : 1;
+  __IO uint32_t EINT02S0   : 1;
+  __IO uint32_t EINT02S1   : 1;
+  __IO uint32_t EINT03S0   : 1;
+  __IO uint32_t EINT03S1   : 1;
+  __IO uint32_t EINT04S0   : 1;
+  __IO uint32_t EINT04S1   : 1;
+  __IO uint32_t EINT05S0   : 1;
+  __IO uint32_t EINT05S1   : 1;
+  __IO uint32_t EINT06S0   : 1;
+  __IO uint32_t EINT06S1   : 1;
+  __IO uint32_t EINT07S0   : 1;
+  __IO uint32_t EINT07S1   : 1;
+  __IO uint32_t EINT08S0   : 1;
+  __IO uint32_t EINT08S1   : 1;
+  __IO uint32_t EINT09S0   : 1;
+  __IO uint32_t EINT09S1   : 1;
+  __IO uint32_t EINT10S0   : 1;
+  __IO uint32_t EINT10S1   : 1;
+  __IO uint32_t EINT11S0   : 1;
+  __IO uint32_t EINT11S1   : 1;
+  __IO uint32_t EINT12S0   : 1;
+  __IO uint32_t EINT12S1   : 1;
+  __IO uint32_t EINT13S0   : 1;
+  __IO uint32_t EINT13S1   : 1;
+  __IO uint32_t EINT14S0   : 1;
+  __IO uint32_t EINT14S1   : 1;
+  __IO uint32_t EINT15S0   : 1;
+  __IO uint32_t EINT15S1   : 1;
+} stc_gpio_epfr06_field_t;
+
+typedef struct stc_gpio_epfr07_field
+{
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t SIN0S0     : 1;
+  __IO uint32_t SIN0S1     : 1;
+  __IO uint32_t SOT0B0     : 1;
+  __IO uint32_t SOT0B1     : 1;
+  __IO uint32_t SCK0B0     : 1;
+  __IO uint32_t SCK0B1     : 1;
+  __IO uint32_t SIN1S0     : 1;
+  __IO uint32_t SIN1S1     : 1;
+  __IO uint32_t SOT1B0     : 1;
+  __IO uint32_t SOT1B1     : 1;
+  __IO uint32_t SCK1B0     : 1;
+  __IO uint32_t SCK1B1     : 1;
+  __IO uint32_t SIN2S0     : 1;
+  __IO uint32_t SIN2S1     : 1;
+  __IO uint32_t SOT2B0     : 1;
+  __IO uint32_t SOT2B1     : 1;
+  __IO uint32_t SCK2B0     : 1;
+  __IO uint32_t SCK2B1     : 1;
+  __IO uint32_t SIN3S0     : 1;
+  __IO uint32_t SIN3S1     : 1;
+  __IO uint32_t SOT3B0     : 1;
+  __IO uint32_t SOT3B1     : 1;
+  __IO uint32_t SCK3B0     : 1;
+  __IO uint32_t SCK3B1     : 1;
+} stc_gpio_epfr07_field_t;
+
+typedef struct stc_gpio_epfr08_field
+{
+  __IO uint32_t RTS4E0     : 1;
+  __IO uint32_t RTS4E1     : 1;
+  __IO uint32_t CTS4S0     : 1;
+  __IO uint32_t CTS4S1     : 1;
+  __IO uint32_t SIN4S0     : 1;
+  __IO uint32_t SIN4S1     : 1;
+  __IO uint32_t SOT4B0     : 1;
+  __IO uint32_t SOT4B1     : 1;
+  __IO uint32_t SCK4B0     : 1;
+  __IO uint32_t SCK4B1     : 1;
+  __IO uint32_t SIN5S0     : 1;
+  __IO uint32_t SIN5S1     : 1;
+  __IO uint32_t SOT5B0     : 1;
+  __IO uint32_t SOT5B1     : 1;
+  __IO uint32_t SCK5B0     : 1;
+  __IO uint32_t SCK5B1     : 1;
+  __IO uint32_t SIN6S0     : 1;
+  __IO uint32_t SIN6S1     : 1;
+  __IO uint32_t SOT6B0     : 1;
+  __IO uint32_t SOT6B1     : 1;
+  __IO uint32_t SCK6B0     : 1;
+  __IO uint32_t SCK6B1     : 1;
+  __IO uint32_t SIN7S0     : 1;
+  __IO uint32_t SIN7S1     : 1;
+  __IO uint32_t SOT7B0     : 1;
+  __IO uint32_t SOT7B1     : 1;
+  __IO uint32_t SCK7B0     : 1;
+  __IO uint32_t SCK7B1     : 1;
+} stc_gpio_epfr08_field_t;
+
+typedef struct stc_gpio_epfr09_field
+{
+  __IO uint32_t QAIN0S0    : 1;
+  __IO uint32_t QAIN0S1    : 1;
+  __IO uint32_t QBIN0S0    : 1;
+  __IO uint32_t QBIN0S1    : 1;
+  __IO uint32_t QZIN0S0    : 1;
+  __IO uint32_t QZIN0S1    : 1;
+  __IO uint32_t QAIN1S0    : 1;
+  __IO uint32_t QAIN1S1    : 1;
+  __IO uint32_t QBIN1S0    : 1;
+  __IO uint32_t QBIN1S1    : 1;
+  __IO uint32_t QZIN1S0    : 1;
+  __IO uint32_t QZIN1S1    : 1;
+  __IO uint32_t ADTRG0S0   : 1;
+  __IO uint32_t ADTRG0S1   : 1;
+  __IO uint32_t ADTRG0S2   : 1;
+  __IO uint32_t ADTRG0S3   : 1;
+  __IO uint32_t ADTRG1S0   : 1;
+  __IO uint32_t ADTRG1S1   : 1;
+  __IO uint32_t ADTRG1S2   : 1;
+  __IO uint32_t ADTRG1S3   : 1;
+  __IO uint32_t ADTRG2S0   : 1;
+  __IO uint32_t ADTRG2S1   : 1;
+  __IO uint32_t ADTRG2S2   : 1;
+  __IO uint32_t ADTRG2S3   : 1;
+} stc_gpio_epfr09_field_t;
+
+typedef struct stc_gpio_epfr10_field
+{
+  __IO uint32_t UEDEFB     : 1;
+  __IO uint32_t UEDTHB     : 1;
+  __IO uint32_t UECLKE     : 1;
+  __IO uint32_t UEWEXE     : 1;
+  __IO uint32_t UEDQME     : 1;
+  __IO uint32_t UEOEXE     : 1;
+  __IO uint32_t UEFLSE     : 1;
+  __IO uint32_t UECS1E     : 1;
+  __IO uint32_t UECS2E     : 1;
+  __IO uint32_t UECS3E     : 1;
+  __IO uint32_t UECS4E     : 1;
+  __IO uint32_t UECS5E     : 1;
+  __IO uint32_t UECS6E     : 1;
+  __IO uint32_t UECS7E     : 1;
+  __IO uint32_t UEAOOE     : 1;
+  __IO uint32_t UEA08E     : 1;
+  __IO uint32_t UEA09E     : 1;
+  __IO uint32_t UEA10E     : 1;
+  __IO uint32_t UEA11E     : 1;
+  __IO uint32_t UEA12E     : 1;
+  __IO uint32_t UEA13E     : 1;
+  __IO uint32_t UEA14E     : 1;
+  __IO uint32_t UEA15E     : 1;
+  __IO uint32_t UEA16E     : 1;
+  __IO uint32_t UEA17E     : 1;
+  __IO uint32_t UEA18E     : 1;
+  __IO uint32_t UEA19E     : 1;
+  __IO uint32_t UEA20E     : 1;
+  __IO uint32_t UEA21E     : 1;
+  __IO uint32_t UEA22E     : 1;
+  __IO uint32_t UEA23E     : 1;
+  __IO uint32_t UEA24E     : 1;
+} stc_gpio_epfr10_field_t;
+
+typedef struct stc_gpio_epfr11_field
+{
+  __IO uint32_t UEALEE     : 1;
+  __IO uint32_t UECS0E     : 1;
+  __IO uint32_t UEA01E     : 1;
+  __IO uint32_t UEA02E     : 1;
+  __IO uint32_t UEA03E     : 1;
+  __IO uint32_t UEA04E     : 1;
+  __IO uint32_t UEA05E     : 1;
+  __IO uint32_t UEA06E     : 1;
+  __IO uint32_t UEA07E     : 1;
+  __IO uint32_t UED00B     : 1;
+  __IO uint32_t UED01B     : 1;
+  __IO uint32_t UED02B     : 1;
+  __IO uint32_t UED03B     : 1;
+  __IO uint32_t UED04B     : 1;
+  __IO uint32_t UED05B     : 1;
+  __IO uint32_t UED06B     : 1;
+  __IO uint32_t UED07B     : 1;
+  __IO uint32_t UED08B     : 1;
+  __IO uint32_t UED09B     : 1;
+  __IO uint32_t UED10B     : 1;
+  __IO uint32_t UED11B     : 1;
+  __IO uint32_t UED12B     : 1;
+  __IO uint32_t UED13B     : 1;
+  __IO uint32_t UED14B     : 1;
+  __IO uint32_t UED15B     : 1;
+  __IO uint32_t UERLC      : 1;
+} stc_gpio_epfr11_field_t;
+
+typedef struct stc_gpio_epfr12_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA8E0    : 1;
+  __IO uint32_t TIOA8E1    : 1;
+  __IO uint32_t TIOB8S0    : 1;
+  __IO uint32_t TIOB8S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA9S0    : 1;
+  __IO uint32_t TIOA9S1    : 1;
+  __IO uint32_t TIOA9E0    : 1;
+  __IO uint32_t TIOA9E1    : 1;
+  __IO uint32_t TIOB9S0    : 1;
+  __IO uint32_t TIOB9S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA10E0   : 1;
+  __IO uint32_t TIOA10E1   : 1;
+  __IO uint32_t TIOB10S0   : 1;
+  __IO uint32_t TIOB10S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA11S0   : 1;
+  __IO uint32_t TIOA11S1   : 1;
+  __IO uint32_t TIOA11E0   : 1;
+  __IO uint32_t TIOA11E1   : 1;
+  __IO uint32_t TIOB11S0   : 1;
+  __IO uint32_t TIOB11S1   : 1;
+} stc_gpio_epfr12_field_t;
+
+typedef struct stc_gpio_epfr13_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA12E0   : 1;
+  __IO uint32_t TIOA12E1   : 1;
+  __IO uint32_t TIOB12S0   : 1;
+  __IO uint32_t TIOB12S1   : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA13S0   : 1;
+  __IO uint32_t TIOA13S1   : 1;
+  __IO uint32_t TIOA13E0   : 1;
+  __IO uint32_t TIOA13E1   : 1;
+  __IO uint32_t TIOB13S0   : 1;
+  __IO uint32_t TIOB13S1   : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA14E0   : 1;
+  __IO uint32_t TIOA14E1   : 1;
+  __IO uint32_t TIOB14S0   : 1;
+  __IO uint32_t TIOB14S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA15S0   : 1;
+  __IO uint32_t TIOA15S1   : 1;
+  __IO uint32_t TIOA15E0   : 1;
+  __IO uint32_t TIOA15E1   : 1;
+  __IO uint32_t TIOB15S0   : 1;
+  __IO uint32_t TIOB15S1   : 1;
+} stc_gpio_epfr13_field_t;
+
+typedef struct stc_gpio_epfr14_field
+{
+  __IO uint32_t QAIN2S0    : 1;
+  __IO uint32_t QAIN2S1    : 1;
+  __IO uint32_t QBIN2S0    : 1;
+  __IO uint32_t QBIN2S1    : 1;
+  __IO uint32_t QZIN2S0    : 1;
+  __IO uint32_t QZIN2S1    : 1;
+       uint32_t RESERVED1  : 12;
+  __IO uint32_t E_TD0E     : 1;
+  __IO uint32_t E_TD1E     : 1;
+  __IO uint32_t E_TE0E     : 1;
+  __IO uint32_t E_TE1E     : 1;
+  __IO uint32_t E_MC0E     : 1;
+  __IO uint32_t E_MC1B     : 1;
+  __IO uint32_t E_MD0B     : 1;
+  __IO uint32_t E_MD1B     : 1;
+  __IO uint32_t E_CKE      : 1;
+  __IO uint32_t E_PSE      : 1;
+  __IO uint32_t E_SPLC0    : 1;
+  __IO uint32_t E_SPLC1    : 1;
+} stc_gpio_epfr14_field_t;
+
+typedef struct stc_gpio_epfr15_field
+{
+  __IO uint32_t EINT16S0   : 1;
+  __IO uint32_t EINT16S1   : 1;
+  __IO uint32_t EINT17S0   : 1;
+  __IO uint32_t EINT17S1   : 1;
+  __IO uint32_t EINT18S0   : 1;
+  __IO uint32_t EINT18S1   : 1;
+  __IO uint32_t EINT19S0   : 1;
+  __IO uint32_t EINT19S1   : 1;
+  __IO uint32_t EINT20S0   : 1;
+  __IO uint32_t EINT20S1   : 1;
+  __IO uint32_t EINT21S0   : 1;
+  __IO uint32_t EINT21S1   : 1;
+  __IO uint32_t EINT22S0   : 1;
+  __IO uint32_t EINT22S1   : 1;
+  __IO uint32_t EINT23S0   : 1;
+  __IO uint32_t EINT23S1   : 1;
+  __IO uint32_t EINT24S0   : 1;
+  __IO uint32_t EINT24S1   : 1;
+  __IO uint32_t EINT25S0   : 1;
+  __IO uint32_t EINT25S1   : 1;
+  __IO uint32_t EINT26S0   : 1;
+  __IO uint32_t EINT26S1   : 1;
+  __IO uint32_t EINT27S0   : 1;
+  __IO uint32_t EINT27S1   : 1;
+  __IO uint32_t EINT28S0   : 1;
+  __IO uint32_t EINT28S1   : 1;
+  __IO uint32_t EINT29S0   : 1;
+  __IO uint32_t EINT29S1   : 1;
+  __IO uint32_t EINT30S0   : 1;
+  __IO uint32_t EINT30S1   : 1;
+  __IO uint32_t EINT31S0   : 1;
+  __IO uint32_t EINT31S1   : 1;
+} stc_gpio_epfr15_field_t;
+
+typedef struct stc_gpio_pzr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr0_field_t;
+
+typedef struct stc_gpio_pzr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr1_field_t;
+
+typedef struct stc_gpio_pzr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr2_field_t;
+
+typedef struct stc_gpio_pzr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr3_field_t;
+
+typedef struct stc_gpio_pzr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pzr4_field_t;
+
+typedef struct stc_gpio_pzr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pzr5_field_t;
+
+typedef struct stc_gpio_pzr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pzr6_field_t;
+
+typedef struct stc_gpio_pzr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr7_field_t;
+
+typedef struct stc_gpio_pzr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzr8_field_t;
+
+typedef struct stc_gpio_pzr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pzr9_field_t;
+
+typedef struct stc_gpio_pzra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pzra_field_t;
+
+typedef struct stc_gpio_pzrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pzrb_field_t;
+
+typedef struct stc_gpio_pzrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzrc_field_t;
+
+typedef struct stc_gpio_pzrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzrd_field_t;
+
+typedef struct stc_gpio_pzre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzre_field_t;
+
+typedef struct stc_gpio_pzrf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pzrf_field_t;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* LVD_MODULE register bit fields */
+typedef struct stc_lvd_lvd_ctl_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SVHI0      : 1;
+  __IO  uint8_t SVHI1      : 1;
+  __IO  uint8_t SVHI2      : 1;
+  __IO  uint8_t SVHI3      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t LVDIE      : 1;
+} stc_lvd_lvd_ctl_field_t;
+
+typedef struct stc_lvd_lvd_str_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIR      : 1;
+} stc_lvd_lvd_str_field_t;
+
+typedef struct stc_lvd_lvd_clr_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDCL      : 1;
+} stc_lvd_lvd_clr_field_t;
+
+typedef struct stc_lvd_lvd_str2_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIRDY    : 1;
+} stc_lvd_lvd_str2_field_t;
+
+/******************************************************************************
+ * USB Ethernet CLK
+ ******************************************************************************/
+/* USB ETHERNET CLK register bit fields */
+typedef struct stc_usbethernetclk_uccr_field
+{
+  __IO  uint8_t UCEN0      : 1;
+  __IO  uint8_t UCSEL0     : 1;
+  __IO  uint8_t UCSEL1     : 1;
+  __IO  uint8_t UCEN1      : 1;
+  __IO  uint8_t ECEN       : 1;
+  __IO  uint8_t ECSEL0     : 1;
+  __IO  uint8_t ECSEL1     : 1;
+} stc_usbethernetclk_uccr_field_t;
+
+typedef struct stc_usbethernetclk_upcr1_field
+{
+  __IO  uint8_t UPLLEN     : 1;
+  __IO  uint8_t UPINC      : 1;
+} stc_usbethernetclk_upcr1_field_t;
+
+typedef struct stc_usbethernetclk_upcr2_field
+{
+  __IO  uint8_t UPOWT0     : 1;
+  __IO  uint8_t UPOWT1     : 1;
+  __IO  uint8_t UPOWT2     : 1;
+} stc_usbethernetclk_upcr2_field_t;
+
+typedef struct stc_usbethernetclk_upcr3_field
+{
+  __IO  uint8_t UPLLK0     : 1;
+  __IO  uint8_t UPLLK1     : 1;
+  __IO  uint8_t UPLLK2     : 1;
+  __IO  uint8_t UPLLK3     : 1;
+  __IO  uint8_t UPLLK4     : 1;
+} stc_usbethernetclk_upcr3_field_t;
+
+typedef struct stc_usbethernetclk_upcr4_field
+{
+  __IO  uint8_t UPLLN0     : 1;
+  __IO  uint8_t UPLLN1     : 1;
+  __IO  uint8_t UPLLN2     : 1;
+  __IO  uint8_t UPLLN3     : 1;
+  __IO  uint8_t UPLLN4     : 1;
+  __IO  uint8_t UPLLN5     : 1;
+  __IO  uint8_t UPLLN6     : 1;
+} stc_usbethernetclk_upcr4_field_t;
+
+typedef struct stc_usbethernetclk_up_str_field
+{
+  __IO  uint8_t UPRDY      : 1;
+} stc_usbethernetclk_up_str_field_t;
+
+typedef struct stc_usbethernetclk_upint_enr_field
+{
+  __IO  uint8_t UPCSE      : 1;
+} stc_usbethernetclk_upint_enr_field_t;
+
+typedef struct stc_usbethernetclk_upint_clr_field
+{
+  __IO  uint8_t UPCSC      : 1;
+} stc_usbethernetclk_upint_clr_field_t;
+
+typedef struct stc_usbethernetclk_upint_str_field
+{
+  __IO  uint8_t UPCSI      : 1;
+} stc_usbethernetclk_upint_str_field_t;
+
+typedef struct stc_usbethernetclk_upcr5_field
+{
+  __IO  uint8_t UPLLM0     : 1;
+  __IO  uint8_t UPLLM1     : 1;
+  __IO  uint8_t UPLLM2     : 1;
+  __IO  uint8_t UPLLM3     : 1;
+} stc_usbethernetclk_upcr5_field_t;
+
+typedef struct stc_usbethernetclk_upcr6_field
+{
+  __IO  uint8_t UBSR0      : 1;
+  __IO  uint8_t UBSR1      : 1;
+  __IO  uint8_t UBSR2      : 1;
+  __IO  uint8_t UBSR3      : 1;
+} stc_usbethernetclk_upcr6_field_t;
+
+typedef struct stc_usbethernetclk_upcr7_field
+{
+  __IO  uint8_t EPLLEN     : 1;
+} stc_usbethernetclk_upcr7_field_t;
+
+typedef struct stc_usbethernetclk_usben0_field
+{
+  __IO  uint8_t USBEN0     : 1;
+} stc_usbethernetclk_usben0_field_t;
+
+typedef struct stc_usbethernetclk_usben1_field
+{
+  __IO  uint8_t USBEN1     : 1;
+} stc_usbethernetclk_usben1_field_t;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* MFS03_UART_MODULE register bit fields */
+typedef struct stc_mfs03_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_uart_smr_field_t;
+
+typedef struct stc_mfs03_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_uart_scr_field_t;
+
+typedef struct stc_mfs03_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs03_uart_escr_field_t;
+
+typedef struct stc_mfs03_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_uart_ssr_field_t;
+
+typedef struct stc_mfs03_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_rdr_field_t;
+
+typedef struct stc_mfs03_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_tdr_field_t;
+
+typedef struct stc_mfs03_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_uart_bgr_field_t;
+
+typedef struct stc_mfs03_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_uart_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* MFS03_CSIO_MODULE register bit fields */
+typedef struct stc_mfs03_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_csio_smr_field_t;
+
+typedef struct stc_mfs03_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_csio_scr_field_t;
+
+typedef struct stc_mfs03_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs03_csio_escr_field_t;
+
+typedef struct stc_mfs03_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_csio_ssr_field_t;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* MFS03_LIN_MODULE register bit fields */
+typedef struct stc_mfs03_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_lin_smr_field_t;
+
+typedef struct stc_mfs03_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_lin_scr_field_t;
+
+typedef struct stc_mfs03_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs03_lin_escr_field_t;
+
+typedef struct stc_mfs03_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_lin_ssr_field_t;
+
+typedef struct stc_mfs03_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_lin_bgr_field_t;
+
+typedef struct stc_mfs03_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_lin_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* MFS03_I2C_MODULE register bit fields */
+typedef struct stc_mfs03_i2c_smr_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_i2c_smr_field_t;
+
+typedef struct stc_mfs03_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs03_i2c_ibcr_field_t;
+
+typedef struct stc_mfs03_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs03_i2c_ibsr_field_t;
+
+typedef struct stc_mfs03_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_i2c_ssr_field_t;
+
+typedef struct stc_mfs03_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs03_i2c_isba_field_t;
+
+typedef struct stc_mfs03_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs03_i2c_ismk_field_t;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* MFS47_UART_MODULE register bit fields */
+typedef struct stc_mfs47_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_uart_smr_field_t;
+
+typedef struct stc_mfs47_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_uart_scr_field_t;
+
+typedef struct stc_mfs47_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs47_uart_escr_field_t;
+
+typedef struct stc_mfs47_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_uart_ssr_field_t;
+
+typedef struct stc_mfs47_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_rdr_field_t;
+
+typedef struct stc_mfs47_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_tdr_field_t;
+
+typedef struct stc_mfs47_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_uart_bgr_field_t;
+
+typedef struct stc_mfs47_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_uart_bgr1_field_t;
+
+typedef struct stc_mfs47_uart_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_uart_fcr_field_t;
+
+typedef struct stc_mfs47_uart_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_uart_fcr0_field_t;
+
+typedef struct stc_mfs47_uart_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_uart_fcr1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_uart_fbyte_field_t;
+
+typedef struct stc_mfs47_uart_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_uart_fbyte1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_uart_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* MFS47_CSIO_MODULE register bit fields */
+typedef struct stc_mfs47_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_csio_smr_field_t;
+
+typedef struct stc_mfs47_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_csio_scr_field_t;
+
+typedef struct stc_mfs47_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs47_csio_escr_field_t;
+
+typedef struct stc_mfs47_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_csio_ssr_field_t;
+
+typedef struct stc_mfs47_csio_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_csio_fcr_field_t;
+
+typedef struct stc_mfs47_csio_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_csio_fcr0_field_t;
+
+typedef struct stc_mfs47_csio_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_csio_fcr1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_csio_fbyte_field_t;
+
+typedef struct stc_mfs47_csio_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_csio_fbyte1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_csio_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* MFS47_LIN_MODULE register bit fields */
+typedef struct stc_mfs47_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_lin_smr_field_t;
+
+typedef struct stc_mfs47_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_lin_scr_field_t;
+
+typedef struct stc_mfs47_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs47_lin_escr_field_t;
+
+typedef struct stc_mfs47_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_lin_ssr_field_t;
+
+typedef struct stc_mfs47_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_lin_bgr_field_t;
+
+typedef struct stc_mfs47_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_lin_bgr1_field_t;
+
+typedef struct stc_mfs47_lin_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_lin_fcr_field_t;
+
+typedef struct stc_mfs47_lin_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_lin_fcr0_field_t;
+
+typedef struct stc_mfs47_lin_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_lin_fcr1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_lin_fbyte_field_t;
+
+typedef struct stc_mfs47_lin_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_lin_fbyte1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_lin_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* MFS47_I2C_MODULE register bit fields */
+typedef struct stc_mfs47_i2c_smr_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_i2c_smr_field_t;
+
+typedef struct stc_mfs47_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs47_i2c_ibcr_field_t;
+
+typedef struct stc_mfs47_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs47_i2c_ibsr_field_t;
+
+typedef struct stc_mfs47_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_i2c_ssr_field_t;
+
+typedef struct stc_mfs47_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs47_i2c_isba_field_t;
+
+typedef struct stc_mfs47_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs47_i2c_ismk_field_t;
+
+typedef struct stc_mfs47_i2c_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_i2c_fcr_field_t;
+
+typedef struct stc_mfs47_i2c_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_i2c_fcr0_field_t;
+
+typedef struct stc_mfs47_i2c_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_i2c_fcr1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_i2c_fbyte_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_i2c_fbyte1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_i2c_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct stc_mfs_nfc_i2cdnf_field
+{
+  __IO uint16_t I2CDNF00   : 1;
+  __IO uint16_t I2CDNF01   : 1;
+  __IO uint16_t I2CDNF10   : 1;
+  __IO uint16_t I2CDNF11   : 1;
+  __IO uint16_t I2CDNF20   : 1;
+  __IO uint16_t I2CDNF21   : 1;
+  __IO uint16_t I2CDNF30   : 1;
+  __IO uint16_t I2CDNF31   : 1;
+  __IO uint16_t I2CDNF40   : 1;
+  __IO uint16_t I2CDNF41   : 1;
+  __IO uint16_t I2CDNF50   : 1;
+  __IO uint16_t I2CDNF51   : 1;
+  __IO uint16_t I2CDNF60   : 1;
+  __IO uint16_t I2CDNF61   : 1;
+  __IO uint16_t I2CDNF70   : 1;
+  __IO uint16_t I2CDNF71   : 1;
+} stc_mfs_nfc_i2cdnf_field_t;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC_MODULE register bit fields */
+typedef struct stc_crc_crccr_field
+{
+  __IO  uint8_t INIT       : 1;
+  __IO  uint8_t CRC32      : 1;
+  __IO  uint8_t LTLEND     : 1;
+  __IO  uint8_t LSBFST     : 1;
+  __IO  uint8_t CRCLTE     : 1;
+  __IO  uint8_t CRCLSF     : 1;
+  __IO  uint8_t FXOR       : 1;
+} stc_crc_crccr_field_t;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* WC_MODULE register bit fields */
+typedef struct stc_wc_wcrd_field
+{
+  __IO  uint8_t CTR0       : 1;
+  __IO  uint8_t CTR1       : 1;
+  __IO  uint8_t CTR2       : 1;
+  __IO  uint8_t CTR3       : 1;
+  __IO  uint8_t CTR4       : 1;
+  __IO  uint8_t CTR5       : 1;
+} stc_wc_wcrd_field_t;
+
+typedef struct stc_wc_wcrl_field
+{
+  __IO  uint8_t RLC0       : 1;
+  __IO  uint8_t RLC1       : 1;
+  __IO  uint8_t RLC2       : 1;
+  __IO  uint8_t RLC3       : 1;
+  __IO  uint8_t RLC4       : 1;
+  __IO  uint8_t RLC5       : 1;
+} stc_wc_wcrl_field_t;
+
+typedef struct stc_wc_wccr_field
+{
+  __IO  uint8_t WCIF       : 1;
+  __IO  uint8_t WCIE       : 1;
+  __IO  uint8_t CS0        : 1;
+  __IO  uint8_t CS1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t WCOP       : 1;
+  __IO  uint8_t WCEN       : 1;
+} stc_wc_wccr_field_t;
+
+typedef struct stc_wc_clk_sel_field
+{
+  __IO uint16_t SEL_IN     : 1;
+       uint16_t RESERVED1  : 7;
+  __IO uint16_t SEL_OUT    : 1;
+} stc_wc_clk_sel_field_t;
+
+typedef struct stc_wc_clk_en_field
+{
+  __IO  uint8_t CLK_EN     : 1;
+  __IO  uint8_t CLK_EN_R   : 1;
+} stc_wc_clk_en_field_t;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* EXBUS_MODULE register bit fields */
+typedef struct stc_exbus_mode0_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode0_field_t;
+
+typedef struct stc_exbus_mode1_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode1_field_t;
+
+typedef struct stc_exbus_mode2_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode2_field_t;
+
+typedef struct stc_exbus_mode3_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode3_field_t;
+
+typedef struct stc_exbus_mode4_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode4_field_t;
+
+typedef struct stc_exbus_mode5_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode5_field_t;
+
+typedef struct stc_exbus_mode6_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode6_field_t;
+
+typedef struct stc_exbus_mode7_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode7_field_t;
+
+typedef struct stc_exbus_tim0_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim0_field_t;
+
+typedef struct stc_exbus_tim1_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim1_field_t;
+
+typedef struct stc_exbus_tim2_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim2_field_t;
+
+typedef struct stc_exbus_tim3_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim3_field_t;
+
+typedef struct stc_exbus_tim4_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim4_field_t;
+
+typedef struct stc_exbus_tim5_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim5_field_t;
+
+typedef struct stc_exbus_tim6_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim6_field_t;
+
+typedef struct stc_exbus_tim7_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim7_field_t;
+
+typedef struct stc_exbus_area0_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area0_field_t;
+
+typedef struct stc_exbus_area1_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area1_field_t;
+
+typedef struct stc_exbus_area2_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area2_field_t;
+
+typedef struct stc_exbus_area3_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area3_field_t;
+
+typedef struct stc_exbus_area4_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area4_field_t;
+
+typedef struct stc_exbus_area5_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area5_field_t;
+
+typedef struct stc_exbus_area6_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area6_field_t;
+
+typedef struct stc_exbus_area7_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area7_field_t;
+
+typedef struct stc_exbus_atim0_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim0_field_t;
+
+typedef struct stc_exbus_atim1_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim1_field_t;
+
+typedef struct stc_exbus_atim2_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim2_field_t;
+
+typedef struct stc_exbus_atim3_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim3_field_t;
+
+typedef struct stc_exbus_atim4_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim4_field_t;
+
+typedef struct stc_exbus_atim5_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim5_field_t;
+
+typedef struct stc_exbus_atim6_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim6_field_t;
+
+typedef struct stc_exbus_atim7_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim7_field_t;
+
+typedef struct stc_exbus_dclkr_field
+{
+  __IO  uint8_t MDIV0      : 1;
+  __IO  uint8_t MDIV1      : 1;
+  __IO  uint8_t MDIV2      : 1;
+  __IO  uint8_t MDIV3      : 1;
+  __IO  uint8_t MCLKON     : 1;
+} stc_exbus_dclkr_field_t;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB_MODULE register bit fields */
+typedef struct stc_usb_hcnt_field
+{
+  __IO uint16_t HOST       : 1;
+  __IO uint16_t URST       : 1;
+  __IO uint16_t SOFIRE     : 1;
+  __IO uint16_t DIRE       : 1;
+  __IO uint16_t CNNIRE     : 1;
+  __IO uint16_t CMPIRE     : 1;
+  __IO uint16_t URIRE      : 1;
+  __IO uint16_t RWKIRE     : 1;
+  __IO uint16_t RETRY      : 1;
+  __IO uint16_t CANCEL     : 1;
+  __IO uint16_t SOFSTEP    : 1;
+} stc_usb_hcnt_field_t;
+
+typedef struct stc_usb_hcnt0_field
+{
+  __IO  uint8_t HOST       : 1;
+  __IO  uint8_t URST       : 1;
+  __IO  uint8_t SOFIRE     : 1;
+  __IO  uint8_t DIRE       : 1;
+  __IO  uint8_t CNNIRE     : 1;
+  __IO  uint8_t CMPIRE     : 1;
+  __IO  uint8_t URIRE      : 1;
+  __IO  uint8_t RWKIRE     : 1;
+} stc_usb_hcnt0_field_t;
+
+typedef struct stc_usb_hcnt1_field
+{
+  __IO  uint8_t RETRY      : 1;
+  __IO  uint8_t CANCEL     : 1;
+  __IO  uint8_t SOFSTEP    : 1;
+} stc_usb_hcnt1_field_t;
+
+typedef struct stc_usb_hirq_field
+{
+  __IO  uint8_t SOFIRQ     : 1;
+  __IO  uint8_t DIRQ       : 1;
+  __IO  uint8_t CNNIRQ     : 1;
+  __IO  uint8_t CMPIRQ     : 1;
+  __IO  uint8_t URIRQ      : 1;
+  __IO  uint8_t RWKIRQ     : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TCAN       : 1;
+} stc_usb_hirq_field_t;
+
+typedef struct stc_usb_herr_field
+{
+  __IO  uint8_t HS0        : 1;
+  __IO  uint8_t HS1        : 1;
+  __IO  uint8_t STUFF      : 1;
+  __IO  uint8_t TGERR      : 1;
+  __IO  uint8_t CRC        : 1;
+  __IO  uint8_t TOUT       : 1;
+  __IO  uint8_t RERR       : 1;
+  __IO  uint8_t LSTOF      : 1;
+} stc_usb_herr_field_t;
+
+typedef struct stc_usb_hstate_field
+{
+  __IO  uint8_t CSTAT      : 1;
+  __IO  uint8_t TMODE      : 1;
+  __IO  uint8_t SUSP       : 1;
+  __IO  uint8_t SOFBUSY    : 1;
+  __IO  uint8_t CLKSEL     : 1;
+  __IO  uint8_t ALIVE      : 1;
+} stc_usb_hstate_field_t;
+
+typedef struct stc_usb_hfcomp_field
+{
+  __IO  uint8_t FRAMECOMP0 : 1;
+  __IO  uint8_t FRAMECOMP1 : 1;
+  __IO  uint8_t FRAMECOMP2 : 1;
+  __IO  uint8_t FRAMECOMP3 : 1;
+  __IO  uint8_t FRAMECOMP4 : 1;
+  __IO  uint8_t FRAMECOMP5 : 1;
+  __IO  uint8_t FRAMECOMP6 : 1;
+  __IO  uint8_t FRAMECOMP7 : 1;
+} stc_usb_hfcomp_field_t;
+
+typedef struct stc_usb_hrtimer_field
+{
+  __IO uint16_t RTIMER0    : 1;
+  __IO uint16_t RTIMER1    : 1;
+  __IO uint16_t RTIMER2    : 1;
+  __IO uint16_t RTIMER3    : 1;
+  __IO uint16_t RTIMER4    : 1;
+  __IO uint16_t RTIMER5    : 1;
+  __IO uint16_t RTIMER6    : 1;
+  __IO uint16_t RTIMER7    : 1;
+  __IO uint16_t RTIMER8    : 1;
+  __IO uint16_t RTIMER9    : 1;
+  __IO uint16_t RTIMER10   : 1;
+  __IO uint16_t RTIMER11   : 1;
+  __IO uint16_t RTIMER12   : 1;
+  __IO uint16_t RTIMER13   : 1;
+  __IO uint16_t RTIMER14   : 1;
+  __IO uint16_t RTIMER15   : 1;
+} stc_usb_hrtimer_field_t;
+
+typedef struct stc_usb_hrtimer0_field
+{
+  __IO  uint8_t RTIMER00   : 1;
+  __IO  uint8_t RTIMER01   : 1;
+  __IO  uint8_t RTIMER02   : 1;
+  __IO  uint8_t RTIMER03   : 1;
+  __IO  uint8_t RTIMER04   : 1;
+  __IO  uint8_t RTIMER05   : 1;
+  __IO  uint8_t RTIMER06   : 1;
+  __IO  uint8_t RTIMER07   : 1;
+} stc_usb_hrtimer0_field_t;
+
+typedef struct stc_usb_hrtimer1_field
+{
+  __IO  uint8_t RTIMER10   : 1;
+  __IO  uint8_t RTIMER11   : 1;
+  __IO  uint8_t RTIMER12   : 1;
+  __IO  uint8_t RTIMER13   : 1;
+  __IO  uint8_t RTIMER14   : 1;
+  __IO  uint8_t RTIMER15   : 1;
+  __IO  uint8_t RTIMER16   : 1;
+  __IO  uint8_t RTIMER17   : 1;
+} stc_usb_hrtimer1_field_t;
+
+typedef struct stc_usb_hrtimer2_field
+{
+  __IO  uint8_t RTIMER20   : 1;
+  __IO  uint8_t RTIMER21   : 1;
+  __IO  uint8_t RTIMER22   : 1;
+} stc_usb_hrtimer2_field_t;
+
+typedef struct stc_usb_hadr_field
+{
+  __IO  uint8_t ADDRESS0   : 1;
+  __IO  uint8_t ADDRESS1   : 1;
+  __IO  uint8_t ADDRESS2   : 1;
+  __IO  uint8_t ADDRESS3   : 1;
+  __IO  uint8_t ADDRESS4   : 1;
+  __IO  uint8_t ADDRESS5   : 1;
+  __IO  uint8_t ADDRESS6   : 1;
+} stc_usb_hadr_field_t;
+
+typedef struct stc_usb_heof_field
+{
+  __IO uint16_t EOF0       : 1;
+  __IO uint16_t EOF1       : 1;
+  __IO uint16_t EOF2       : 1;
+  __IO uint16_t EOF3       : 1;
+  __IO uint16_t EOF4       : 1;
+  __IO uint16_t EOF5       : 1;
+  __IO uint16_t EOF6       : 1;
+  __IO uint16_t EOF7       : 1;
+  __IO uint16_t EOF8       : 1;
+  __IO uint16_t EOF9       : 1;
+  __IO uint16_t EOF10      : 1;
+  __IO uint16_t EOF11      : 1;
+  __IO uint16_t EOF12      : 1;
+  __IO uint16_t EOF13      : 1;
+  __IO uint16_t EOF14      : 1;
+  __IO uint16_t EOF15      : 1;
+} stc_usb_heof_field_t;
+
+typedef struct stc_usb_heof0_field
+{
+  __IO  uint8_t EOF00      : 1;
+  __IO  uint8_t EOF01      : 1;
+  __IO  uint8_t EOF02      : 1;
+  __IO  uint8_t EOF03      : 1;
+  __IO  uint8_t EOF04      : 1;
+  __IO  uint8_t EOF05      : 1;
+  __IO  uint8_t EOF06      : 1;
+  __IO  uint8_t EOF07      : 1;
+} stc_usb_heof0_field_t;
+
+typedef struct stc_usb_heof1_field
+{
+  __IO  uint8_t EOF10      : 1;
+  __IO  uint8_t EOF11      : 1;
+  __IO  uint8_t EOF12      : 1;
+  __IO  uint8_t EOF13      : 1;
+  __IO  uint8_t EOF14      : 1;
+  __IO  uint8_t EOF15      : 1;
+} stc_usb_heof1_field_t;
+
+typedef struct stc_usb_hframe_field
+{
+  __IO uint16_t FRAME0     : 1;
+  __IO uint16_t FRAME1     : 1;
+  __IO uint16_t FRAME2     : 1;
+  __IO uint16_t FRAME3     : 1;
+  __IO uint16_t FRAME4     : 1;
+  __IO uint16_t FRAME5     : 1;
+  __IO uint16_t FRAME6     : 1;
+  __IO uint16_t FRAME7     : 1;
+  __IO uint16_t FRAME8     : 1;
+  __IO uint16_t FRAME9     : 1;
+  __IO uint16_t FRAME10    : 1;
+} stc_usb_hframe_field_t;
+
+typedef struct stc_usb_hframe0_field
+{
+  __IO  uint8_t FRAME00    : 1;
+  __IO  uint8_t FRAME01    : 1;
+  __IO  uint8_t FRAME02    : 1;
+  __IO  uint8_t FRAME03    : 1;
+  __IO  uint8_t FRAME04    : 1;
+  __IO  uint8_t FRAME05    : 1;
+  __IO  uint8_t FRAME06    : 1;
+  __IO  uint8_t FRAME07    : 1;
+} stc_usb_hframe0_field_t;
+
+typedef struct stc_usb_hframe1_field
+{
+  __IO  uint8_t FRAME10    : 1;
+  __IO  uint8_t FRAME11    : 1;
+  __IO  uint8_t FRAME12    : 1;
+  __IO  uint8_t FRAME13    : 1;
+} stc_usb_hframe1_field_t;
+
+typedef struct stc_usb_htoken_field
+{
+  __IO  uint8_t ENDPT0     : 1;
+  __IO  uint8_t ENDPT1     : 1;
+  __IO  uint8_t ENDPT2     : 1;
+  __IO  uint8_t ENDPT3     : 1;
+  __IO  uint8_t TKNEN0     : 1;
+  __IO  uint8_t TKNEN1     : 1;
+  __IO  uint8_t TKNEN2     : 1;
+  __IO  uint8_t TGGL       : 1;
+} stc_usb_htoken_field_t;
+
+typedef struct stc_usb_udcc_field
+{
+  __IO uint16_t PWC        : 1;
+  __IO uint16_t RFBK       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t STALCLREN  : 1;
+  __IO uint16_t USTP       : 1;
+  __IO uint16_t HCONX      : 1;
+  __IO uint16_t RESUM      : 1;
+  __IO uint16_t RST        : 1;
+} stc_usb_udcc_field_t;
+
+typedef struct stc_usb_ep0c_field
+{
+  __IO uint16_t PKS00      : 1;
+  __IO uint16_t PKS01      : 1;
+  __IO uint16_t PKS02      : 1;
+  __IO uint16_t PKS03      : 1;
+  __IO uint16_t PKS04      : 1;
+  __IO uint16_t PKS05      : 1;
+  __IO uint16_t PKS06      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+} stc_usb_ep0c_field_t;
+
+typedef struct stc_usb_ep1c_field
+{
+  __IO uint16_t PKS10      : 1;
+  __IO uint16_t PKS11      : 1;
+  __IO uint16_t PKS12      : 1;
+  __IO uint16_t PKS13      : 1;
+  __IO uint16_t PKS14      : 1;
+  __IO uint16_t PKS15      : 1;
+  __IO uint16_t PKS16      : 1;
+  __IO uint16_t PKS17      : 1;
+  __IO uint16_t PKS18      : 1;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep1c_field_t;
+
+typedef struct stc_usb_ep2c_field
+{
+  __IO uint16_t PKS20      : 1;
+  __IO uint16_t PKS21      : 1;
+  __IO uint16_t PKS22      : 1;
+  __IO uint16_t PKS23      : 1;
+  __IO uint16_t PKS24      : 1;
+  __IO uint16_t PKS25      : 1;
+  __IO uint16_t PKS26      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep2c_field_t;
+
+typedef struct stc_usb_ep3c_field
+{
+  __IO uint16_t PKS30      : 1;
+  __IO uint16_t PKS31      : 1;
+  __IO uint16_t PKS32      : 1;
+  __IO uint16_t PKS33      : 1;
+  __IO uint16_t PKS34      : 1;
+  __IO uint16_t PKS35      : 1;
+  __IO uint16_t PKS36      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep3c_field_t;
+
+typedef struct stc_usb_ep4c_field
+{
+  __IO uint16_t PKS40      : 1;
+  __IO uint16_t PKS41      : 1;
+  __IO uint16_t PKS42      : 1;
+  __IO uint16_t PKS43      : 1;
+  __IO uint16_t PKS44      : 1;
+  __IO uint16_t PKS45      : 1;
+  __IO uint16_t PKS46      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep4c_field_t;
+
+typedef struct stc_usb_ep5c_field
+{
+  __IO uint16_t PKS50      : 1;
+  __IO uint16_t PKS51      : 1;
+  __IO uint16_t PKS52      : 1;
+  __IO uint16_t PKS53      : 1;
+  __IO uint16_t PKS54      : 1;
+  __IO uint16_t PKS55      : 1;
+  __IO uint16_t PKS56      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep5c_field_t;
+
+typedef struct stc_usb_tmsp_field
+{
+  __IO uint16_t TMSP0      : 1;
+  __IO uint16_t TMSP1      : 1;
+  __IO uint16_t TMSP2      : 1;
+  __IO uint16_t TMSP3      : 1;
+  __IO uint16_t TMSP4      : 1;
+  __IO uint16_t TMSP5      : 1;
+  __IO uint16_t TMSP6      : 1;
+  __IO uint16_t TMSP7      : 1;
+  __IO uint16_t TMSP8      : 1;
+  __IO uint16_t TMSP9      : 1;
+  __IO uint16_t TMSP10     : 1;
+} stc_usb_tmsp_field_t;
+
+typedef struct stc_usb_udcs_field
+{
+  __IO  uint8_t CONF       : 1;
+  __IO  uint8_t SETP       : 1;
+  __IO  uint8_t WKUP       : 1;
+  __IO  uint8_t BRST       : 1;
+  __IO  uint8_t SOF        : 1;
+  __IO  uint8_t SUSP       : 1;
+} stc_usb_udcs_field_t;
+
+typedef struct stc_usb_udcie_field
+{
+  __IO  uint8_t CONFIE     : 1;
+  __IO  uint8_t CONFN      : 1;
+  __IO  uint8_t WKUPIE     : 1;
+  __IO  uint8_t BRSTIE     : 1;
+  __IO  uint8_t SOFIE      : 1;
+  __IO  uint8_t SUSPIE     : 1;
+} stc_usb_udcie_field_t;
+
+typedef struct stc_usb_ep0is_field
+{
+       uint16_t RESERVED1  : 10;
+  __IO uint16_t DRQI       : 1;
+       uint16_t RESERVED2  : 3;
+  __IO uint16_t DRQIIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0is_field_t;
+
+typedef struct stc_usb_ep0os_field
+{
+  __IO uint16_t SIZE0      : 1;
+  __IO uint16_t SIZE1      : 1;
+  __IO uint16_t SIZE2      : 1;
+  __IO uint16_t SIZE3      : 1;
+  __IO uint16_t SIZE4      : 1;
+  __IO uint16_t SIZE5      : 1;
+  __IO uint16_t SIZE6      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQO       : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQOIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0os_field_t;
+
+typedef struct stc_usb_ep1s_field
+{
+  __IO uint16_t SIZE10     : 1;
+  __IO uint16_t SIZE11     : 1;
+  __IO uint16_t SIZE12     : 1;
+  __IO uint16_t SIZE13     : 1;
+  __IO uint16_t SIZE14     : 1;
+  __IO uint16_t SIZE15     : 1;
+  __IO uint16_t SIZE16     : 1;
+  __IO uint16_t SIZE17     : 1;
+  __IO uint16_t SIZE18     : 1;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep1s_field_t;
+
+typedef struct stc_usb_ep2s_field
+{
+  __IO uint16_t SIZE20     : 1;
+  __IO uint16_t SIZE21     : 1;
+  __IO uint16_t SIZE22     : 1;
+  __IO uint16_t SIZE23     : 1;
+  __IO uint16_t SIZE24     : 1;
+  __IO uint16_t SIZE25     : 1;
+  __IO uint16_t SIZE26     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep2s_field_t;
+
+typedef struct stc_usb_ep4s_field
+{
+  __IO uint16_t SIZE40     : 1;
+  __IO uint16_t SIZE41     : 1;
+  __IO uint16_t SIZE42     : 1;
+  __IO uint16_t SIZE43     : 1;
+  __IO uint16_t SIZE44     : 1;
+  __IO uint16_t SIZE45     : 1;
+  __IO uint16_t SIZE46     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep4s_field_t;
+
+typedef struct stc_usb_ep5s_field
+{
+  __IO uint16_t SIZE50     : 1;
+  __IO uint16_t SIZE51     : 1;
+  __IO uint16_t SIZE52     : 1;
+  __IO uint16_t SIZE53     : 1;
+  __IO uint16_t SIZE54     : 1;
+  __IO uint16_t SIZE55     : 1;
+  __IO uint16_t SIZE56     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep5s_field_t;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMAC_MODULE register bit fields */
+typedef struct stc_dmac_dmacr_field
+{
+       uint32_t RESERVED1  : 24;
+  __IO uint32_t DH0        : 1;
+  __IO uint32_t DH1        : 1;
+  __IO uint32_t DH2        : 1;
+  __IO uint32_t DH3        : 1;
+  __IO uint32_t PR         : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t DS         : 1;
+  __IO uint32_t DE         : 1;
+} stc_dmac_dmacr_field_t;
+
+typedef struct stc_dmac_dmaca0_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca0_field_t;
+
+typedef struct stc_dmac_dmacb0_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb0_field_t;
+
+typedef struct stc_dmac_dmaca1_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca1_field_t;
+
+typedef struct stc_dmac_dmacb1_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb1_field_t;
+
+typedef struct stc_dmac_dmaca2_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca2_field_t;
+
+typedef struct stc_dmac_dmacb2_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb2_field_t;
+
+typedef struct stc_dmac_dmaca3_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca3_field_t;
+
+typedef struct stc_dmac_dmacb3_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb3_field_t;
+
+typedef struct stc_dmac_dmaca4_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca4_field_t;
+
+typedef struct stc_dmac_dmacb4_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb4_field_t;
+
+typedef struct stc_dmac_dmaca5_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca5_field_t;
+
+typedef struct stc_dmac_dmacb5_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb5_field_t;
+
+typedef struct stc_dmac_dmaca6_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca6_field_t;
+
+typedef struct stc_dmac_dmacb6_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb6_field_t;
+
+typedef struct stc_dmac_dmaca7_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca7_field_t;
+
+typedef struct stc_dmac_dmacb7_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb7_field_t;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET_MAC_MODULE register bit fields */
+typedef struct stc_ethernet_mac_mcr_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t RE         : 1;
+  __IO uint32_t TE         : 1;
+  __IO uint32_t DC         : 1;
+  __IO uint32_t BL0        : 1;
+  __IO uint32_t BL1        : 1;
+  __IO uint32_t ACS        : 1;
+  __IO uint32_t LUD        : 1;
+  __IO uint32_t DR         : 1;
+  __IO uint32_t IPC        : 1;
+  __IO uint32_t DM         : 1;
+  __IO uint32_t LM         : 1;
+  __IO uint32_t DO         : 1;
+  __IO uint32_t FES        : 1;
+  __IO uint32_t PS         : 1;
+  __IO uint32_t DCRS       : 1;
+  __IO uint32_t IFG0       : 1;
+  __IO uint32_t IFG1       : 1;
+  __IO uint32_t IFG2       : 1;
+  __IO uint32_t JE         : 1;
+  __IO uint32_t BE         : 1;
+  __IO uint32_t JD         : 1;
+  __IO uint32_t WD         : 1;
+  __IO uint32_t TC         : 1;
+  __IO uint32_t CST        : 1;
+} stc_ethernet_mac_mcr_field_t;
+
+typedef struct stc_ethernet_mac_mffr_field
+{
+  __IO uint32_t PR         : 1;
+  __IO uint32_t HUC        : 1;
+  __IO uint32_t HMC        : 1;
+  __IO uint32_t DAIF       : 1;
+  __IO uint32_t PM         : 1;
+  __IO uint32_t DB         : 1;
+  __IO uint32_t PCF0       : 1;
+  __IO uint32_t PCF1       : 1;
+  __IO uint32_t SAIF       : 1;
+  __IO uint32_t SAF        : 1;
+  __IO uint32_t HPF        : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t RA         : 1;
+} stc_ethernet_mac_mffr_field_t;
+
+typedef struct stc_ethernet_mac_mhtrh_field
+{
+  __IO uint32_t HTH0       : 1;
+  __IO uint32_t HTH1       : 1;
+  __IO uint32_t HTH2       : 1;
+  __IO uint32_t HTH3       : 1;
+  __IO uint32_t HTH4       : 1;
+  __IO uint32_t HTH5       : 1;
+  __IO uint32_t HTH6       : 1;
+  __IO uint32_t HTH7       : 1;
+  __IO uint32_t HTH8       : 1;
+  __IO uint32_t HTH9       : 1;
+  __IO uint32_t HTH10      : 1;
+  __IO uint32_t HTH11      : 1;
+  __IO uint32_t HTH12      : 1;
+  __IO uint32_t HTH13      : 1;
+  __IO uint32_t HTH14      : 1;
+  __IO uint32_t HTH15      : 1;
+  __IO uint32_t HTH16      : 1;
+  __IO uint32_t HTH17      : 1;
+  __IO uint32_t HTH18      : 1;
+  __IO uint32_t HTH19      : 1;
+  __IO uint32_t HTH20      : 1;
+  __IO uint32_t HTH21      : 1;
+  __IO uint32_t HTH22      : 1;
+  __IO uint32_t HTH23      : 1;
+  __IO uint32_t HTH24      : 1;
+  __IO uint32_t HTH25      : 1;
+  __IO uint32_t HTH26      : 1;
+  __IO uint32_t HTH27      : 1;
+  __IO uint32_t HTH28      : 1;
+  __IO uint32_t HTH29      : 1;
+  __IO uint32_t HTH30      : 1;
+  __IO uint32_t HTH31      : 1;
+} stc_ethernet_mac_mhtrh_field_t;
+
+typedef struct stc_ethernet_mac_mhtrl_field
+{
+  __IO uint32_t HTL0       : 1;
+  __IO uint32_t HTL1       : 1;
+  __IO uint32_t HTL2       : 1;
+  __IO uint32_t HTL3       : 1;
+  __IO uint32_t HTL4       : 1;
+  __IO uint32_t HTL5       : 1;
+  __IO uint32_t HTL6       : 1;
+  __IO uint32_t HTL7       : 1;
+  __IO uint32_t HTL8       : 1;
+  __IO uint32_t HTL9       : 1;
+  __IO uint32_t HTL10      : 1;
+  __IO uint32_t HTL11      : 1;
+  __IO uint32_t HTL12      : 1;
+  __IO uint32_t HTL13      : 1;
+  __IO uint32_t HTL14      : 1;
+  __IO uint32_t HTL15      : 1;
+  __IO uint32_t HTL16      : 1;
+  __IO uint32_t HTL17      : 1;
+  __IO uint32_t HTL18      : 1;
+  __IO uint32_t HTL19      : 1;
+  __IO uint32_t HTL20      : 1;
+  __IO uint32_t HTL21      : 1;
+  __IO uint32_t HTL22      : 1;
+  __IO uint32_t HTL23      : 1;
+  __IO uint32_t HTL24      : 1;
+  __IO uint32_t HTL25      : 1;
+  __IO uint32_t HTL26      : 1;
+  __IO uint32_t HTL27      : 1;
+  __IO uint32_t HTL28      : 1;
+  __IO uint32_t HTL29      : 1;
+  __IO uint32_t HTL30      : 1;
+  __IO uint32_t HTL31      : 1;
+} stc_ethernet_mac_mhtrl_field_t;
+
+typedef struct stc_ethernet_mac_gar_field
+{
+  __IO uint32_t GB         : 1;
+  __IO uint32_t GW         : 1;
+  __IO uint32_t CR0        : 1;
+  __IO uint32_t CR1        : 1;
+  __IO uint32_t CR2        : 1;
+  __IO uint32_t CR3        : 1;
+  __IO uint32_t GR0        : 1;
+  __IO uint32_t GR1        : 1;
+  __IO uint32_t GR2        : 1;
+  __IO uint32_t GR3        : 1;
+  __IO uint32_t GR4        : 1;
+  __IO uint32_t PA0        : 1;
+  __IO uint32_t PA1        : 1;
+  __IO uint32_t PA2        : 1;
+  __IO uint32_t PA3        : 1;
+  __IO uint32_t PA4        : 1;
+} stc_ethernet_mac_gar_field_t;
+
+typedef struct stc_ethernet_mac_gdr_field
+{
+  __IO uint32_t GD0        : 1;
+  __IO uint32_t GD1        : 1;
+  __IO uint32_t GD2        : 1;
+  __IO uint32_t GD3        : 1;
+  __IO uint32_t GD4        : 1;
+  __IO uint32_t GD5        : 1;
+  __IO uint32_t GD6        : 1;
+  __IO uint32_t GD7        : 1;
+  __IO uint32_t GD8        : 1;
+  __IO uint32_t GD9        : 1;
+  __IO uint32_t GD10       : 1;
+  __IO uint32_t GD11       : 1;
+  __IO uint32_t GD12       : 1;
+  __IO uint32_t GD13       : 1;
+  __IO uint32_t GD14       : 1;
+  __IO uint32_t GD15       : 1;
+} stc_ethernet_mac_gdr_field_t;
+
+typedef struct stc_ethernet_mac_fcr_field
+{
+  __IO uint32_t FCB_BPA    : 1;
+  __IO uint32_t TFE        : 1;
+  __IO uint32_t RFE        : 1;
+  __IO uint32_t UP         : 1;
+  __IO uint32_t PLT0       : 1;
+  __IO uint32_t PLT1       : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t DZPQ       : 1;
+       uint32_t RESERVED2  : 8;
+  __IO uint32_t PT0        : 1;
+  __IO uint32_t PT1        : 1;
+  __IO uint32_t PT2        : 1;
+  __IO uint32_t PT3        : 1;
+  __IO uint32_t PT4        : 1;
+  __IO uint32_t PT5        : 1;
+  __IO uint32_t PT6        : 1;
+  __IO uint32_t PT7        : 1;
+  __IO uint32_t PT8        : 1;
+  __IO uint32_t PT9        : 1;
+  __IO uint32_t PT10       : 1;
+  __IO uint32_t PT11       : 1;
+  __IO uint32_t PT12       : 1;
+  __IO uint32_t PT13       : 1;
+  __IO uint32_t PT14       : 1;
+  __IO uint32_t PT15       : 1;
+} stc_ethernet_mac_fcr_field_t;
+
+typedef struct stc_ethernet_mac_vtr_field
+{
+  __IO uint32_t VL0        : 1;
+  __IO uint32_t VL1        : 1;
+  __IO uint32_t VL2        : 1;
+  __IO uint32_t VL3        : 1;
+  __IO uint32_t VL4        : 1;
+  __IO uint32_t VL5        : 1;
+  __IO uint32_t VL6        : 1;
+  __IO uint32_t VL7        : 1;
+  __IO uint32_t VL8        : 1;
+  __IO uint32_t VL9        : 1;
+  __IO uint32_t VL10       : 1;
+  __IO uint32_t VL11       : 1;
+  __IO uint32_t VL12       : 1;
+  __IO uint32_t VL13       : 1;
+  __IO uint32_t VL14       : 1;
+  __IO uint32_t VL15       : 1;
+  __IO uint32_t ETV        : 1;
+} stc_ethernet_mac_vtr_field_t;
+
+typedef struct stc_ethernet_mac_rwffr_field
+{
+  __IO uint32_t RWFFR0     : 1;
+  __IO uint32_t RWFFR1     : 1;
+  __IO uint32_t RWFFR2     : 1;
+  __IO uint32_t RWFFR3     : 1;
+  __IO uint32_t RWFFR4     : 1;
+  __IO uint32_t RWFFR5     : 1;
+  __IO uint32_t RWFFR6     : 1;
+  __IO uint32_t RWFFR7     : 1;
+  __IO uint32_t RWFFR8     : 1;
+  __IO uint32_t RWFFR9     : 1;
+  __IO uint32_t RWFFR10    : 1;
+  __IO uint32_t RWFFR11    : 1;
+  __IO uint32_t RWFFR12    : 1;
+  __IO uint32_t RWFFR13    : 1;
+  __IO uint32_t RWFFR14    : 1;
+  __IO uint32_t RWFFR15    : 1;
+  __IO uint32_t RWFFR16    : 1;
+  __IO uint32_t RWFFR17    : 1;
+  __IO uint32_t RWFFR18    : 1;
+  __IO uint32_t RWFFR19    : 1;
+  __IO uint32_t RWFFR20    : 1;
+  __IO uint32_t RWFFR21    : 1;
+  __IO uint32_t RWFFR22    : 1;
+  __IO uint32_t RWFFR23    : 1;
+  __IO uint32_t RWFFR24    : 1;
+  __IO uint32_t RWFFR25    : 1;
+  __IO uint32_t RWFFR26    : 1;
+  __IO uint32_t RWFFR27    : 1;
+  __IO uint32_t RWFFR28    : 1;
+  __IO uint32_t RWFFR29    : 1;
+  __IO uint32_t RWFFR30    : 1;
+  __IO uint32_t RWFFR31    : 1;
+} stc_ethernet_mac_rwffr_field_t;
+
+typedef struct stc_ethernet_mac_pmtr_field
+{
+  __IO uint32_t PD         : 1;
+  __IO uint32_t MPE        : 1;
+  __IO uint32_t WFE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t MPR        : 1;
+  __IO uint32_t WPR        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t GU         : 1;
+       uint32_t RESERVED3  :21;
+  __IO uint32_t RWFFRPR    : 1;
+} stc_ethernet_mac_pmtr_field_t;
+
+typedef struct stc_ethernet_mac_lpicsr_field
+{
+  __IO uint32_t TLPIEN     : 1;
+  __IO uint32_t TLPIEX     : 1;
+  __IO uint32_t RLPIEN     : 1;
+  __IO uint32_t RLPIEX     : 1;
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t TLPIST     : 1;
+  __IO uint32_t RLPIST     : 1;
+       uint32_t RESERVED2  : 6;
+  __IO uint32_t LPIEN      : 1;
+  __IO uint32_t PLS        : 1;
+  __IO uint32_t PLSEN      : 1;
+  __IO uint32_t LPITXA     : 1;
+} stc_ethernet_mac_lpicsr_field_t;
+
+typedef struct stc_ethernet_mac_lpitcr_field
+{
+  __IO uint32_t TWT0       : 1;
+  __IO uint32_t TWT1       : 1;
+  __IO uint32_t TWT2       : 1;
+  __IO uint32_t TWT3       : 1;
+  __IO uint32_t TWT4       : 1;
+  __IO uint32_t TWT5       : 1;
+  __IO uint32_t TWT6       : 1;
+  __IO uint32_t TWT7       : 1;
+  __IO uint32_t TWT8       : 1;
+  __IO uint32_t TWT9       : 1;
+  __IO uint32_t TWT10      : 1;
+  __IO uint32_t TWT11      : 1;
+  __IO uint32_t TWT12      : 1;
+  __IO uint32_t TWT13      : 1;
+  __IO uint32_t TWT14      : 1;
+  __IO uint32_t TWT15      : 1;
+  __IO uint32_t LIT0       : 1;
+  __IO uint32_t LIT1       : 1;
+  __IO uint32_t LIT2       : 1;
+  __IO uint32_t LIT3       : 1;
+  __IO uint32_t LIT4       : 1;
+  __IO uint32_t LIT5       : 1;
+  __IO uint32_t LIT6       : 1;
+  __IO uint32_t LIT7       : 1;
+  __IO uint32_t LIT8       : 1;
+  __IO uint32_t LIT9       : 1;
+} stc_ethernet_mac_lpitcr_field_t;
+
+typedef struct stc_ethernet_mac_isr_field
+{
+  __IO uint32_t RGIS       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIS        : 1;
+  __IO uint32_t MIS        : 1;
+  __IO uint32_t RIS        : 1;
+  __IO uint32_t TIS        : 1;
+  __IO uint32_t COIS       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t TSIS       : 1;
+  __IO uint32_t LPIIS      : 1;
+} stc_ethernet_mac_isr_field_t;
+
+typedef struct stc_ethernet_mac_imr_field
+{
+  __IO uint32_t RGIM       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIM        : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t TSIM       : 1;
+  __IO uint32_t LPIIM      : 1;
+} stc_ethernet_mac_imr_field_t;
+
+typedef struct stc_ethernet_mac_mar0h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  :15;
+  __IO uint32_t MO         : 1;
+} stc_ethernet_mac_mar0h_field_t;
+
+typedef struct stc_ethernet_mac_mar0l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar0l_field_t;
+
+typedef struct stc_ethernet_mac_mar1h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar1h_field_t;
+
+typedef struct stc_ethernet_mac_mar1l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar1l_field_t;
+
+typedef struct stc_ethernet_mac_mar2h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar2h_field_t;
+
+typedef struct stc_ethernet_mac_mar2l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar2l_field_t;
+
+typedef struct stc_ethernet_mac_mar3h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar3h_field_t;
+
+typedef struct stc_ethernet_mac_mar3l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar3l_field_t;
+
+typedef struct stc_ethernet_mac_mar4h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar4h_field_t;
+
+typedef struct stc_ethernet_mac_mar4l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar4l_field_t;
+
+typedef struct stc_ethernet_mac_mar5h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar5h_field_t;
+
+typedef struct stc_ethernet_mac_mar5l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar5l_field_t;
+
+typedef struct stc_ethernet_mac_mar6h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar6h_field_t;
+
+typedef struct stc_ethernet_mac_mar6l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar6l_field_t;
+
+typedef struct stc_ethernet_mac_mar7h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar7h_field_t;
+
+typedef struct stc_ethernet_mac_mar7l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar7l_field_t;
+
+typedef struct stc_ethernet_mac_mar8h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar8h_field_t;
+
+typedef struct stc_ethernet_mac_mar8l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar8l_field_t;
+
+typedef struct stc_ethernet_mac_mar9h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar9h_field_t;
+
+typedef struct stc_ethernet_mac_mar9l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar9l_field_t;
+
+typedef struct stc_ethernet_mac_mar10h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar10h_field_t;
+
+typedef struct stc_ethernet_mac_mar10l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar10l_field_t;
+
+typedef struct stc_ethernet_mac_mar11h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar11h_field_t;
+
+typedef struct stc_ethernet_mac_mar11l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar11l_field_t;
+
+typedef struct stc_ethernet_mac_mar12h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar12h_field_t;
+
+typedef struct stc_ethernet_mac_mar12l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar12l_field_t;
+
+typedef struct stc_ethernet_mac_mar13h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar13h_field_t;
+
+typedef struct stc_ethernet_mac_mar13l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar13l_field_t;
+
+typedef struct stc_ethernet_mac_mar14h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar14h_field_t;
+
+typedef struct stc_ethernet_mac_mar14l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar14l_field_t;
+
+typedef struct stc_ethernet_mac_mar15h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar15h_field_t;
+
+typedef struct stc_ethernet_mac_mar15l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar15l_field_t;
+
+typedef struct stc_ethernet_mac_rgsr_field
+{
+  __IO uint32_t LM         : 1;
+  __IO uint32_t LSP0       : 1;
+  __IO uint32_t LSP1       : 1;
+  __IO uint32_t LS         : 1;
+} stc_ethernet_mac_rgsr_field_t;
+
+typedef struct stc_ethernet_mac_tscr_field
+{
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TFCU       : 1;
+  __IO uint32_t TSI        : 1;
+  __IO uint32_t TSU        : 1;
+  __IO uint32_t TITE       : 1;
+  __IO uint32_t TARU       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TSEA       : 1;
+  __IO uint32_t TSDB       : 1;
+  __IO uint32_t TSV2E      : 1;
+  __IO uint32_t TETSP      : 1;
+  __IO uint32_t TSIP6E     : 1;
+  __IO uint32_t TSIP4E     : 1;
+  __IO uint32_t TETSEM     : 1;
+  __IO uint32_t TSMRM      : 1;
+  __IO uint32_t TSPS0      : 1;
+  __IO uint32_t TSPS1      : 1;
+  __IO uint32_t TSENMF     : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t ATSFC      : 1;
+} stc_ethernet_mac_tscr_field_t;
+
+typedef struct stc_ethernet_mac_ssir_field
+{
+  __IO uint32_t SSINC0     : 1;
+  __IO uint32_t SSINC1     : 1;
+  __IO uint32_t SSINC2     : 1;
+  __IO uint32_t SSINC3     : 1;
+  __IO uint32_t SSINC4     : 1;
+  __IO uint32_t SSINC5     : 1;
+  __IO uint32_t SSINC6     : 1;
+  __IO uint32_t SSINC7     : 1;
+} stc_ethernet_mac_ssir_field_t;
+
+typedef struct stc_ethernet_mac_stsr_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsr_field_t;
+
+typedef struct stc_ethernet_mac_stnr_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+} stc_ethernet_mac_stnr_field_t;
+
+typedef struct stc_ethernet_mac_stsur_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsur_field_t;
+
+typedef struct stc_ethernet_mac_stnur_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+  __IO uint32_t ADDSUB     : 1;
+} stc_ethernet_mac_stnur_field_t;
+
+typedef struct stc_ethernet_mac_tsar_field
+{
+  __IO uint32_t TSAR0      : 1;
+  __IO uint32_t TSAR1      : 1;
+  __IO uint32_t TSAR2      : 1;
+  __IO uint32_t TSAR3      : 1;
+  __IO uint32_t TSAR4      : 1;
+  __IO uint32_t TSAR5      : 1;
+  __IO uint32_t TSAR6      : 1;
+  __IO uint32_t TSAR7      : 1;
+  __IO uint32_t TSAR8      : 1;
+  __IO uint32_t TSAR9      : 1;
+  __IO uint32_t TSAR10     : 1;
+  __IO uint32_t TSAR11     : 1;
+  __IO uint32_t TSAR12     : 1;
+  __IO uint32_t TSAR13     : 1;
+  __IO uint32_t TSAR14     : 1;
+  __IO uint32_t TSAR15     : 1;
+  __IO uint32_t TSAR16     : 1;
+  __IO uint32_t TSAR17     : 1;
+  __IO uint32_t TSAR18     : 1;
+  __IO uint32_t TSAR19     : 1;
+  __IO uint32_t TSAR20     : 1;
+  __IO uint32_t TSAR21     : 1;
+  __IO uint32_t TSAR22     : 1;
+  __IO uint32_t TSAR23     : 1;
+  __IO uint32_t TSAR24     : 1;
+  __IO uint32_t TSAR25     : 1;
+  __IO uint32_t TSAR26     : 1;
+  __IO uint32_t TSAR27     : 1;
+  __IO uint32_t TSAR28     : 1;
+  __IO uint32_t TSAR29     : 1;
+  __IO uint32_t TSAR30     : 1;
+  __IO uint32_t TSAR31     : 1;
+} stc_ethernet_mac_tsar_field_t;
+
+typedef struct stc_ethernet_mac_ttsr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+  __IO uint32_t TSTR31     : 1;
+} stc_ethernet_mac_ttsr_field_t;
+
+typedef struct stc_ethernet_mac_ttnr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+} stc_ethernet_mac_ttnr_field_t;
+
+typedef struct stc_ethernet_mac_sthwsr_field
+{
+  __IO uint32_t TSHWR0     : 1;
+  __IO uint32_t TSHWR1     : 1;
+  __IO uint32_t TSHWR2     : 1;
+  __IO uint32_t TSHWR3     : 1;
+  __IO uint32_t TSHWR4     : 1;
+  __IO uint32_t TSHWR5     : 1;
+  __IO uint32_t TSHWR6     : 1;
+  __IO uint32_t TSHWR7     : 1;
+  __IO uint32_t TSHWR8     : 1;
+  __IO uint32_t TSHWR9     : 1;
+  __IO uint32_t TSHWR10    : 1;
+  __IO uint32_t TSHWR11    : 1;
+  __IO uint32_t TSHWR12    : 1;
+  __IO uint32_t TSHWR13    : 1;
+  __IO uint32_t TSHWR14    : 1;
+  __IO uint32_t TSHWR15    : 1;
+} stc_ethernet_mac_sthwsr_field_t;
+
+typedef struct stc_ethernet_mac_tsr_field
+{
+  __IO uint32_t TSSOVF     : 1;
+  __IO uint32_t TSTART     : 1;
+  __IO uint32_t ATSTS      : 1;
+  __IO uint32_t TRGTER     : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t ATSSTM     : 1;
+  __IO uint32_t ATSNS0     : 1;
+  __IO uint32_t ATSNS1     : 1;
+  __IO uint32_t ATSNS2     : 1;
+} stc_ethernet_mac_tsr_field_t;
+
+typedef struct stc_ethernet_mac_ppscr_field
+{
+  __IO uint32_t PPSCTRL0   : 1;
+  __IO uint32_t PPSCTRL1   : 1;
+  __IO uint32_t PPSCTRL2   : 1;
+  __IO uint32_t PPSCTRL3   : 1;
+} stc_ethernet_mac_ppscr_field_t;
+
+typedef struct stc_ethernet_mac_atnr_field
+{
+  __IO uint32_t ATN0       : 1;
+  __IO uint32_t ATN1       : 1;
+  __IO uint32_t ATN2       : 1;
+  __IO uint32_t ATN3       : 1;
+  __IO uint32_t ATN4       : 1;
+  __IO uint32_t ATN5       : 1;
+  __IO uint32_t ATN6       : 1;
+  __IO uint32_t ATN7       : 1;
+  __IO uint32_t ATN8       : 1;
+  __IO uint32_t ATN9       : 1;
+  __IO uint32_t ATN10      : 1;
+  __IO uint32_t ATN11      : 1;
+  __IO uint32_t ATN12      : 1;
+  __IO uint32_t ATN13      : 1;
+  __IO uint32_t ATN14      : 1;
+  __IO uint32_t ATN15      : 1;
+  __IO uint32_t ATN16      : 1;
+  __IO uint32_t ATN17      : 1;
+  __IO uint32_t ATN18      : 1;
+  __IO uint32_t ATN19      : 1;
+  __IO uint32_t ATN20      : 1;
+  __IO uint32_t ATN21      : 1;
+  __IO uint32_t ATN22      : 1;
+  __IO uint32_t ATN23      : 1;
+  __IO uint32_t ATN24      : 1;
+  __IO uint32_t ATN25      : 1;
+  __IO uint32_t ATN26      : 1;
+  __IO uint32_t ATN27      : 1;
+  __IO uint32_t ATN28      : 1;
+  __IO uint32_t ATN29      : 1;
+  __IO uint32_t ATN30      : 1;
+} stc_ethernet_mac_atnr_field_t;
+
+typedef struct stc_ethernet_mac_atsr_field
+{
+  __IO uint32_t ATS0       : 1;
+  __IO uint32_t ATS1       : 1;
+  __IO uint32_t ATS2       : 1;
+  __IO uint32_t ATS3       : 1;
+  __IO uint32_t ATS4       : 1;
+  __IO uint32_t ATS5       : 1;
+  __IO uint32_t ATS6       : 1;
+  __IO uint32_t ATS7       : 1;
+  __IO uint32_t ATS8       : 1;
+  __IO uint32_t ATS9       : 1;
+  __IO uint32_t ATS10      : 1;
+  __IO uint32_t ATS11      : 1;
+  __IO uint32_t ATS12      : 1;
+  __IO uint32_t ATS13      : 1;
+  __IO uint32_t ATS14      : 1;
+  __IO uint32_t ATS15      : 1;
+  __IO uint32_t ATS16      : 1;
+  __IO uint32_t ATS17      : 1;
+  __IO uint32_t ATS18      : 1;
+  __IO uint32_t ATS19      : 1;
+  __IO uint32_t ATS20      : 1;
+  __IO uint32_t ATS21      : 1;
+  __IO uint32_t ATS22      : 1;
+  __IO uint32_t ATS23      : 1;
+  __IO uint32_t ATS24      : 1;
+  __IO uint32_t ATS25      : 1;
+  __IO uint32_t ATS26      : 1;
+  __IO uint32_t ATS27      : 1;
+  __IO uint32_t ATS28      : 1;
+  __IO uint32_t ATS29      : 1;
+  __IO uint32_t ATS30      : 1;
+  __IO uint32_t ATS31      : 1;
+} stc_ethernet_mac_atsr_field_t;
+
+typedef struct stc_ethernet_mac_mar16h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar16h_field_t;
+
+typedef struct stc_ethernet_mac_mar16l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar16l_field_t;
+
+typedef struct stc_ethernet_mac_mar17h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar17h_field_t;
+
+typedef struct stc_ethernet_mac_mar17l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar17l_field_t;
+
+typedef struct stc_ethernet_mac_mar18h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar18h_field_t;
+
+typedef struct stc_ethernet_mac_mar18l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar18l_field_t;
+
+typedef struct stc_ethernet_mac_mar19h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar19h_field_t;
+
+typedef struct stc_ethernet_mac_mar19l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar19l_field_t;
+
+typedef struct stc_ethernet_mac_mar20h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar20h_field_t;
+
+typedef struct stc_ethernet_mac_mar20l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar20l_field_t;
+
+typedef struct stc_ethernet_mac_mar21h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar21h_field_t;
+
+typedef struct stc_ethernet_mac_mar21l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar21l_field_t;
+
+typedef struct stc_ethernet_mac_mar22h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar22h_field_t;
+
+typedef struct stc_ethernet_mac_mar22l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar22l_field_t;
+
+typedef struct stc_ethernet_mac_mar23h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar23h_field_t;
+
+typedef struct stc_ethernet_mac_mar23l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar23l_field_t;
+
+typedef struct stc_ethernet_mac_mar24h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar24h_field_t;
+
+typedef struct stc_ethernet_mac_mar24l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar24l_field_t;
+
+typedef struct stc_ethernet_mac_mar25h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar25h_field_t;
+
+typedef struct stc_ethernet_mac_mar25l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar25l_field_t;
+
+typedef struct stc_ethernet_mac_mar26h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar26h_field_t;
+
+typedef struct stc_ethernet_mac_mar26l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar26l_field_t;
+
+typedef struct stc_ethernet_mac_mar27h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar27h_field_t;
+
+typedef struct stc_ethernet_mac_mar27l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar27l_field_t;
+
+typedef struct stc_ethernet_mac_mar28h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar28h_field_t;
+
+typedef struct stc_ethernet_mac_mar28l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar28l_field_t;
+
+typedef struct stc_ethernet_mac_mar29h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar29h_field_t;
+
+typedef struct stc_ethernet_mac_mar29l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar29l_field_t;
+
+typedef struct stc_ethernet_mac_mar30h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar30h_field_t;
+
+typedef struct stc_ethernet_mac_mar30l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar30l_field_t;
+
+typedef struct stc_ethernet_mac_mar31h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar31h_field_t;
+
+typedef struct stc_ethernet_mac_mar31l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar31l_field_t;
+
+typedef struct stc_ethernet_mac_bmr_field
+{
+  __IO uint32_t SWR        : 1;
+  __IO uint32_t DA         : 1;
+  __IO uint32_t DSL0       : 1;
+  __IO uint32_t DSL1       : 1;
+  __IO uint32_t DSL2       : 1;
+  __IO uint32_t DSL3       : 1;
+  __IO uint32_t DSL4       : 1;
+  __IO uint32_t ATDS       : 1;
+  __IO uint32_t PBL0       : 1;
+  __IO uint32_t PBL1       : 1;
+  __IO uint32_t PBL2       : 1;
+  __IO uint32_t PBL3       : 1;
+  __IO uint32_t PBL4       : 1;
+  __IO uint32_t PBL5       : 1;
+  __IO uint32_t PR0        : 1;
+  __IO uint32_t PR1        : 1;
+  __IO uint32_t FB         : 1;
+  __IO uint32_t RPBL0      : 1;
+  __IO uint32_t RPBL1      : 1;
+  __IO uint32_t RPBL2      : 1;
+  __IO uint32_t RPBL3      : 1;
+  __IO uint32_t RPBL4      : 1;
+  __IO uint32_t RPBL5      : 1;
+  __IO uint32_t USP        : 1;
+  __IO uint32_t _8XPBL     : 1;
+  __IO uint32_t AAL        : 1;
+  __IO uint32_t MB         : 1;
+  __IO uint32_t TXPR       : 1;
+} stc_ethernet_mac_bmr_field_t;
+
+typedef struct stc_ethernet_mac_tpdr_field
+{
+  __IO uint32_t TPD0       : 1;
+  __IO uint32_t TPD1       : 1;
+  __IO uint32_t TPD2       : 1;
+  __IO uint32_t TPD3       : 1;
+  __IO uint32_t TPD4       : 1;
+  __IO uint32_t TPD5       : 1;
+  __IO uint32_t TPD6       : 1;
+  __IO uint32_t TPD7       : 1;
+  __IO uint32_t TPD8       : 1;
+  __IO uint32_t TPD9       : 1;
+  __IO uint32_t TPD10      : 1;
+  __IO uint32_t TPD11      : 1;
+  __IO uint32_t TPD12      : 1;
+  __IO uint32_t TPD13      : 1;
+  __IO uint32_t TPD14      : 1;
+  __IO uint32_t TPD15      : 1;
+  __IO uint32_t TPD16      : 1;
+  __IO uint32_t TPD17      : 1;
+  __IO uint32_t TPD18      : 1;
+  __IO uint32_t TPD19      : 1;
+  __IO uint32_t TPD20      : 1;
+  __IO uint32_t TPD21      : 1;
+  __IO uint32_t TPD22      : 1;
+  __IO uint32_t TPD23      : 1;
+  __IO uint32_t TPD24      : 1;
+  __IO uint32_t TPD25      : 1;
+  __IO uint32_t TPD26      : 1;
+  __IO uint32_t TPD27      : 1;
+  __IO uint32_t TPD28      : 1;
+  __IO uint32_t TPD29      : 1;
+  __IO uint32_t TPD30      : 1;
+  __IO uint32_t TPD31      : 1;
+} stc_ethernet_mac_tpdr_field_t;
+
+typedef struct stc_ethernet_mac_rpdr_field
+{
+  __IO uint32_t RPD0       : 1;
+  __IO uint32_t RPD1       : 1;
+  __IO uint32_t RPD2       : 1;
+  __IO uint32_t RPD3       : 1;
+  __IO uint32_t RPD4       : 1;
+  __IO uint32_t RPD5       : 1;
+  __IO uint32_t RPD6       : 1;
+  __IO uint32_t RPD7       : 1;
+  __IO uint32_t RPD8       : 1;
+  __IO uint32_t RPD9       : 1;
+  __IO uint32_t RPD10      : 1;
+  __IO uint32_t RPD11      : 1;
+  __IO uint32_t RPD12      : 1;
+  __IO uint32_t RPD13      : 1;
+  __IO uint32_t RPD14      : 1;
+  __IO uint32_t RPD15      : 1;
+  __IO uint32_t RPD16      : 1;
+  __IO uint32_t RPD17      : 1;
+  __IO uint32_t RPD18      : 1;
+  __IO uint32_t RPD19      : 1;
+  __IO uint32_t RPD20      : 1;
+  __IO uint32_t RPD21      : 1;
+  __IO uint32_t RPD22      : 1;
+  __IO uint32_t RPD23      : 1;
+  __IO uint32_t RPD24      : 1;
+  __IO uint32_t RPD25      : 1;
+  __IO uint32_t RPD26      : 1;
+  __IO uint32_t RPD27      : 1;
+  __IO uint32_t RPD28      : 1;
+  __IO uint32_t RPD29      : 1;
+  __IO uint32_t RPD30      : 1;
+  __IO uint32_t RPD31      : 1;
+} stc_ethernet_mac_rpdr_field_t;
+
+typedef struct stc_ethernet_mac_rdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t SRL2       : 1;
+  __IO uint32_t SRL3       : 1;
+  __IO uint32_t SRL4       : 1;
+  __IO uint32_t SRL5       : 1;
+  __IO uint32_t SRL6       : 1;
+  __IO uint32_t SRL7       : 1;
+  __IO uint32_t SRL8       : 1;
+  __IO uint32_t SRL9       : 1;
+  __IO uint32_t SRL10      : 1;
+  __IO uint32_t SRL11      : 1;
+  __IO uint32_t SRL12      : 1;
+  __IO uint32_t SRL13      : 1;
+  __IO uint32_t SRL14      : 1;
+  __IO uint32_t SRL15      : 1;
+  __IO uint32_t SRL16      : 1;
+  __IO uint32_t SRL17      : 1;
+  __IO uint32_t SRL18      : 1;
+  __IO uint32_t SRL19      : 1;
+  __IO uint32_t SRL20      : 1;
+  __IO uint32_t SRL21      : 1;
+  __IO uint32_t SRL22      : 1;
+  __IO uint32_t SRL23      : 1;
+  __IO uint32_t SRL24      : 1;
+  __IO uint32_t SRL25      : 1;
+  __IO uint32_t SRL26      : 1;
+  __IO uint32_t SRL27      : 1;
+  __IO uint32_t SRL28      : 1;
+  __IO uint32_t SRL29      : 1;
+  __IO uint32_t SRL30      : 1;
+  __IO uint32_t SRL31      : 1;
+} stc_ethernet_mac_rdlar_field_t;
+
+typedef struct stc_ethernet_mac_tdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t STL2       : 1;
+  __IO uint32_t STL3       : 1;
+  __IO uint32_t STL4       : 1;
+  __IO uint32_t STL5       : 1;
+  __IO uint32_t STL6       : 1;
+  __IO uint32_t STL7       : 1;
+  __IO uint32_t STL8       : 1;
+  __IO uint32_t STL9       : 1;
+  __IO uint32_t STL10      : 1;
+  __IO uint32_t STL11      : 1;
+  __IO uint32_t STL12      : 1;
+  __IO uint32_t STL13      : 1;
+  __IO uint32_t STL14      : 1;
+  __IO uint32_t STL15      : 1;
+  __IO uint32_t STL16      : 1;
+  __IO uint32_t STL17      : 1;
+  __IO uint32_t STL18      : 1;
+  __IO uint32_t STL19      : 1;
+  __IO uint32_t STL20      : 1;
+  __IO uint32_t STL21      : 1;
+  __IO uint32_t STL22      : 1;
+  __IO uint32_t STL23      : 1;
+  __IO uint32_t STL24      : 1;
+  __IO uint32_t STL25      : 1;
+  __IO uint32_t STL26      : 1;
+  __IO uint32_t STL27      : 1;
+  __IO uint32_t STL28      : 1;
+  __IO uint32_t STL29      : 1;
+  __IO uint32_t STL30      : 1;
+  __IO uint32_t STL31      : 1;
+} stc_ethernet_mac_tdlar_field_t;
+
+typedef struct stc_ethernet_mac_sr_field
+{
+  __IO uint32_t TI         : 1;
+  __IO uint32_t TPS        : 1;
+  __IO uint32_t TU         : 1;
+  __IO uint32_t TJT        : 1;
+  __IO uint32_t OVF        : 1;
+  __IO uint32_t UNF        : 1;
+  __IO uint32_t RI         : 1;
+  __IO uint32_t RU         : 1;
+  __IO uint32_t RPS        : 1;
+  __IO uint32_t RWT        : 1;
+  __IO uint32_t ETI        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBI        : 1;
+  __IO uint32_t ERI        : 1;
+  __IO uint32_t AIS        : 1;
+  __IO uint32_t NIS        : 1;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+  __IO uint32_t TS0        : 1;
+  __IO uint32_t TS1        : 1;
+  __IO uint32_t TS2        : 1;
+  __IO uint32_t EB0        : 1;
+  __IO uint32_t EB1        : 1;
+  __IO uint32_t EB2        : 1;
+  __IO uint32_t GLI        : 1;
+  __IO uint32_t GMI        : 1;
+  __IO uint32_t GPI        : 1;
+  __IO uint32_t TTI        : 1;
+  __IO uint32_t GLPII      : 1;
+} stc_ethernet_mac_sr_field_t;
+
+typedef struct stc_ethernet_mac_omr_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t SR         : 1;
+  __IO uint32_t OSF        : 1;
+  __IO uint32_t RTC0       : 1;
+  __IO uint32_t RTC1       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t FUF        : 1;
+  __IO uint32_t FEF        : 1;
+       uint32_t RESERVED3  : 5;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t TTC0       : 1;
+  __IO uint32_t TTC1       : 1;
+  __IO uint32_t TTC2       : 1;
+       uint32_t RESERVED4  : 3;
+  __IO uint32_t FTF        : 1;
+  __IO uint32_t TSF        : 1;
+       uint32_t RESERVED5  : 2;
+  __IO uint32_t DFF        : 1;
+  __IO uint32_t RSF        : 1;
+  __IO uint32_t DT         : 1;
+} stc_ethernet_mac_omr_field_t;
+
+typedef struct stc_ethernet_mac_ier_field
+{
+  __IO uint32_t TIE        : 1;
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TUE        : 1;
+  __IO uint32_t TJE        : 1;
+  __IO uint32_t OVE        : 1;
+  __IO uint32_t UNE        : 1;
+  __IO uint32_t RIE        : 1;
+  __IO uint32_t RUE        : 1;
+  __IO uint32_t RSE        : 1;
+  __IO uint32_t RWE        : 1;
+  __IO uint32_t ETE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBE        : 1;
+  __IO uint32_t ERE        : 1;
+  __IO uint32_t AIE        : 1;
+  __IO uint32_t NIE        : 1;
+} stc_ethernet_mac_ier_field_t;
+
+typedef struct stc_ethernet_mac_mfbocr_field
+{
+  __IO uint32_t NMFH0      : 1;
+  __IO uint32_t NMFH1      : 1;
+  __IO uint32_t NMFH2      : 1;
+  __IO uint32_t NMFH3      : 1;
+  __IO uint32_t NMFH4      : 1;
+  __IO uint32_t NMFH5      : 1;
+  __IO uint32_t NMFH6      : 1;
+  __IO uint32_t NMFH7      : 1;
+  __IO uint32_t NMFH8      : 1;
+  __IO uint32_t NMFH9      : 1;
+  __IO uint32_t NMFH10     : 1;
+  __IO uint32_t NMFH11     : 1;
+  __IO uint32_t NMFH12     : 1;
+  __IO uint32_t NMFH13     : 1;
+  __IO uint32_t NMFH14     : 1;
+  __IO uint32_t NMFH15     : 1;
+  __IO uint32_t ONMFH      : 1;
+  __IO uint32_t NMFF0      : 1;
+  __IO uint32_t NMFF1      : 1;
+  __IO uint32_t NMFF2      : 1;
+  __IO uint32_t NMFF3      : 1;
+  __IO uint32_t NMFF4      : 1;
+  __IO uint32_t NMFF5      : 1;
+  __IO uint32_t NMFF6      : 1;
+  __IO uint32_t NMFF7      : 1;
+  __IO uint32_t NMFF8      : 1;
+  __IO uint32_t NMFF9      : 1;
+  __IO uint32_t NMFF10     : 1;
+  __IO uint32_t ONMFF      : 1;
+} stc_ethernet_mac_mfbocr_field_t;
+
+typedef struct stc_ethernet_mac_riwtr_field
+{
+  __IO uint32_t RIWT0      : 1;
+  __IO uint32_t RIWT1      : 1;
+  __IO uint32_t RIWT2      : 1;
+  __IO uint32_t RIWT3      : 1;
+  __IO uint32_t RIWT4      : 1;
+  __IO uint32_t RIWT5      : 1;
+  __IO uint32_t RIWT6      : 1;
+  __IO uint32_t RIWT7      : 1;
+} stc_ethernet_mac_riwtr_field_t;
+
+typedef struct stc_ethernet_mac_ahbsr_field
+{
+  __IO uint32_t AHBS       : 1;
+} stc_ethernet_mac_ahbsr_field_t;
+
+typedef struct stc_ethernet_mac_chtdr_field
+{
+  __IO uint32_t HTDAP0     : 1;
+  __IO uint32_t HTDAP1     : 1;
+  __IO uint32_t HTDAP2     : 1;
+  __IO uint32_t HTDAP3     : 1;
+  __IO uint32_t HTDAP4     : 1;
+  __IO uint32_t HTDAP5     : 1;
+  __IO uint32_t HTDAP6     : 1;
+  __IO uint32_t HTDAP7     : 1;
+  __IO uint32_t HTDAP8     : 1;
+  __IO uint32_t HTDAP9     : 1;
+  __IO uint32_t HTDAP10    : 1;
+  __IO uint32_t HTDAP11    : 1;
+  __IO uint32_t HTDAP12    : 1;
+  __IO uint32_t HTDAP13    : 1;
+  __IO uint32_t HTDAP14    : 1;
+  __IO uint32_t HTDAP15    : 1;
+  __IO uint32_t HTDAP16    : 1;
+  __IO uint32_t HTDAP17    : 1;
+  __IO uint32_t HTDAP18    : 1;
+  __IO uint32_t HTDAP19    : 1;
+  __IO uint32_t HTDAP20    : 1;
+  __IO uint32_t HTDAP21    : 1;
+  __IO uint32_t HTDAP22    : 1;
+  __IO uint32_t HTDAP23    : 1;
+  __IO uint32_t HTDAP24    : 1;
+  __IO uint32_t HTDAP25    : 1;
+  __IO uint32_t HTDAP26    : 1;
+  __IO uint32_t HTDAP27    : 1;
+  __IO uint32_t HTDAP28    : 1;
+  __IO uint32_t HTDAP29    : 1;
+  __IO uint32_t HTDAP30    : 1;
+  __IO uint32_t HTDAP31    : 1;
+} stc_ethernet_mac_chtdr_field_t;
+
+typedef struct stc_ethernet_mac_chrdr_field
+{
+  __IO uint32_t HRDAP0     : 1;
+  __IO uint32_t HRDAP1     : 1;
+  __IO uint32_t HRDAP2     : 1;
+  __IO uint32_t HRDAP3     : 1;
+  __IO uint32_t HRDAP4     : 1;
+  __IO uint32_t HRDAP5     : 1;
+  __IO uint32_t HRDAP6     : 1;
+  __IO uint32_t HRDAP7     : 1;
+  __IO uint32_t HRDAP8     : 1;
+  __IO uint32_t HRDAP9     : 1;
+  __IO uint32_t HRDAP10    : 1;
+  __IO uint32_t HRDAP11    : 1;
+  __IO uint32_t HRDAP12    : 1;
+  __IO uint32_t HRDAP13    : 1;
+  __IO uint32_t HRDAP14    : 1;
+  __IO uint32_t HRDAP15    : 1;
+  __IO uint32_t HRDAP16    : 1;
+  __IO uint32_t HRDAP17    : 1;
+  __IO uint32_t HRDAP18    : 1;
+  __IO uint32_t HRDAP19    : 1;
+  __IO uint32_t HRDAP20    : 1;
+  __IO uint32_t HRDAP21    : 1;
+  __IO uint32_t HRDAP22    : 1;
+  __IO uint32_t HRDAP23    : 1;
+  __IO uint32_t HRDAP24    : 1;
+  __IO uint32_t HRDAP25    : 1;
+  __IO uint32_t HRDAP26    : 1;
+  __IO uint32_t HRDAP27    : 1;
+  __IO uint32_t HRDAP28    : 1;
+  __IO uint32_t HRDAP29    : 1;
+  __IO uint32_t HRDAP30    : 1;
+  __IO uint32_t HRDAP31    : 1;
+} stc_ethernet_mac_chrdr_field_t;
+
+typedef struct stc_ethernet_mac_chtbar_field
+{
+  __IO uint32_t HTBAR0     : 1;
+  __IO uint32_t HTBAR1     : 1;
+  __IO uint32_t HTBAR2     : 1;
+  __IO uint32_t HTBAR3     : 1;
+  __IO uint32_t HTBAR4     : 1;
+  __IO uint32_t HTBAR5     : 1;
+  __IO uint32_t HTBAR6     : 1;
+  __IO uint32_t HTBAR7     : 1;
+  __IO uint32_t HTBAR8     : 1;
+  __IO uint32_t HTBAR9     : 1;
+  __IO uint32_t HTBAR10    : 1;
+  __IO uint32_t HTBAR11    : 1;
+  __IO uint32_t HTBAR12    : 1;
+  __IO uint32_t HTBAR13    : 1;
+  __IO uint32_t HTBAR14    : 1;
+  __IO uint32_t HTBAR15    : 1;
+  __IO uint32_t HTBAR16    : 1;
+  __IO uint32_t HTBAR17    : 1;
+  __IO uint32_t HTBAR18    : 1;
+  __IO uint32_t HTBAR19    : 1;
+  __IO uint32_t HTBAR20    : 1;
+  __IO uint32_t HTBAR21    : 1;
+  __IO uint32_t HTBAR22    : 1;
+  __IO uint32_t HTBAR23    : 1;
+  __IO uint32_t HTBAR24    : 1;
+  __IO uint32_t HTBAR25    : 1;
+  __IO uint32_t HTBAR26    : 1;
+  __IO uint32_t HTBAR27    : 1;
+  __IO uint32_t HTBAR28    : 1;
+  __IO uint32_t HTBAR29    : 1;
+  __IO uint32_t HTBAR30    : 1;
+  __IO uint32_t HTBAR31    : 1;
+} stc_ethernet_mac_chtbar_field_t;
+
+typedef struct stc_ethernet_mac_chrbar_field
+{
+  __IO uint32_t HRBAR0     : 1;
+  __IO uint32_t HRBAR1     : 1;
+  __IO uint32_t HRBAR2     : 1;
+  __IO uint32_t HRBAR3     : 1;
+  __IO uint32_t HRBAR4     : 1;
+  __IO uint32_t HRBAR5     : 1;
+  __IO uint32_t HRBAR6     : 1;
+  __IO uint32_t HRBAR7     : 1;
+  __IO uint32_t HRBAR8     : 1;
+  __IO uint32_t HRBAR9     : 1;
+  __IO uint32_t HRBAR10    : 1;
+  __IO uint32_t HRBAR11    : 1;
+  __IO uint32_t HRBAR12    : 1;
+  __IO uint32_t HRBAR13    : 1;
+  __IO uint32_t HRBAR14    : 1;
+  __IO uint32_t HRBAR15    : 1;
+  __IO uint32_t HRBAR16    : 1;
+  __IO uint32_t HRBAR17    : 1;
+  __IO uint32_t HRBAR18    : 1;
+  __IO uint32_t HRBAR19    : 1;
+  __IO uint32_t HRBAR20    : 1;
+  __IO uint32_t HRBAR21    : 1;
+  __IO uint32_t HRBAR22    : 1;
+  __IO uint32_t HRBAR23    : 1;
+  __IO uint32_t HRBAR24    : 1;
+  __IO uint32_t HRBAR25    : 1;
+  __IO uint32_t HRBAR26    : 1;
+  __IO uint32_t HRBAR27    : 1;
+  __IO uint32_t HRBAR28    : 1;
+  __IO uint32_t HRBAR29    : 1;
+  __IO uint32_t HRBAR30    : 1;
+  __IO uint32_t HRBAR31    : 1;
+} stc_ethernet_mac_chrbar_field_t;
+
+/* ETHERNET_CONTROL_MODULE register bit fields */
+typedef struct stc_ethernet_control_eth_mode_field
+{
+  __IO uint32_t IFMODE     : 1;
+       uint32_t RESERVED1  : 7;
+  __IO uint32_t RST0       : 1;
+  __IO uint32_t RST1       : 1;
+       uint32_t RESERVED2  :18;
+  __IO uint32_t ASZPPSSEL  : 1;
+} stc_ethernet_control_eth_mode_field_t;
+
+typedef struct stc_ethernet_control_eth_clkg_field
+{
+  __IO uint32_t MACEN0     : 1;
+  __IO uint32_t MACEN1     : 1;
+} stc_ethernet_control_eth_clkg_field_t;
+
+/******************************************************************************
+ * Peripheral register structures
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t FASZR;
+    stc_flash_if_faszr_field_t FASZR_f;
+  };
+  union {
+    __IO uint32_t FRWTR;
+    stc_flash_if_frwtr_field_t FRWTR_f;
+  };
+  union {
+    __IO uint32_t FSTR;
+    stc_flash_if_fstr_field_t FSTR_f;
+  };
+        uint8_t RESERVED0[4];
+  union {
+    __IO uint32_t FSYNDN;
+    stc_flash_if_fsyndn_field_t FSYNDN_f;
+  };
+  union {
+    __IO uint32_t FBFCR;
+    stc_flash_if_fbfcr_field_t FBFCR_f;
+  };
+        uint8_t RESERVED1[232];
+  union {
+    __IO uint32_t CRTRMM;
+    stc_flash_if_crtrmm_field_t CRTRMM_f;
+  };
+}FM3_FLASH_IF_TypeDef;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock and reset registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SCM_CTL;
+    stc_crg_scm_ctl_field_t SCM_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t SCM_STR;
+    stc_crg_scm_str_field_t SCM_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  __IO uint32_t STB_CTL;
+  union {
+    __IO uint16_t RST_STR;
+    stc_crg_rst_str_field_t RST_STR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t BSC_PSR;
+    stc_crg_bsc_psr_field_t BSC_PSR_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t APBC0_PSR;
+    stc_crg_apbc0_psr_field_t APBC0_PSR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t APBC1_PSR;
+    stc_crg_apbc1_psr_field_t APBC1_PSR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t APBC2_PSR;
+    stc_crg_apbc2_psr_field_t APBC2_PSR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t SWC_PSR;
+    stc_crg_swc_psr_field_t SWC_PSR_f;
+  };
+        uint8_t RESERVED7[7];
+  union {
+    __IO  uint8_t TTC_PSR;
+    stc_crg_ttc_psr_field_t TTC_PSR_f;
+  };
+        uint8_t RESERVED8[7];
+  union {
+    __IO  uint8_t CSW_TMR;
+    stc_crg_csw_tmr_field_t CSW_TMR_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t PSW_TMR;
+    stc_crg_psw_tmr_field_t PSW_TMR_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PLL_CTL1;
+    stc_crg_pll_ctl1_field_t PLL_CTL1_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t PLL_CTL2;
+    stc_crg_pll_ctl2_field_t PLL_CTL2_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO uint16_t CSV_CTL;
+    stc_crg_csv_ctl_field_t CSV_CTL_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO  uint8_t CSV_STR;
+    stc_crg_csv_str_field_t CSV_STR_f;
+  };
+        uint8_t RESERVED14[3];
+  __IO uint16_t FCSWH_CTL;
+        uint8_t RESERVED15[2];
+  __IO uint16_t FCSWL_CTL;
+        uint8_t RESERVED16[2];
+  __IO uint16_t FCSWD_CTL;
+        uint8_t RESERVED17[2];
+  union {
+    __IO  uint8_t DBWDT_CTL;
+    stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
+  };
+        uint8_t RESERVED18[11];
+  union {
+    __IO  uint8_t INT_ENR;
+    stc_crg_int_enr_field_t INT_ENR_f;
+  };
+        uint8_t RESERVED19[3];
+  union {
+    __IO  uint8_t INT_STR;
+    stc_crg_int_str_field_t INT_STR_f;
+  };
+        uint8_t RESERVED20[3];
+  union {
+    __IO  uint8_t INT_CLR;
+    stc_crg_int_clr_field_t INT_CLR_f;
+  };
+}FM3_CRG_TypeDef;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* Hardware watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDG_LDR;
+  __IO uint32_t WDG_VLR;
+  union {
+    __IO  uint8_t WDG_CTL;
+    stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO  uint8_t WDG_ICL;
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t WDG_RIS;
+    stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
+  };
+        uint8_t RESERVED2[3055];
+  __IO uint32_t WDG_LCK;
+}FM3_HWWDT_TypeDef;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* Software watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDOGLOAD;
+  __IO uint32_t WDOGVALUE;
+  union {
+    __IO  uint8_t WDOGCONTROL;
+    stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t WDOGINTCLR;
+  union {
+    __IO  uint8_t WDOGRIS;
+    stc_swwdt_wdogris_field_t WDOGRIS_f;
+  };
+        uint8_t RESERVED1[3055];
+  __IO uint32_t WDOGLOCK;
+}FM3_SWWDT_TypeDef;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* Dual timer 1/2 registers */
+typedef struct
+{
+  __IO uint32_t TIMER1LOAD;
+  __IO uint32_t TIMER1VALUE;
+  union {
+    __IO uint32_t TIMER1CONTROL;
+    stc_dtim_timer1control_field_t TIMER1CONTROL_f;
+  };
+  __IO uint32_t TIMER1INTCLR;
+  union {
+    __IO uint32_t TIMER1RIS;
+    stc_dtim_timer1ris_field_t TIMER1RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER1MIS;
+    stc_dtim_timer1mis_field_t TIMER1MIS_f;
+  };
+  __IO uint32_t TIMER1BGLOAD;
+        uint8_t RESERVED0[4];
+  __IO uint32_t TIMER2LOAD;
+  __IO uint32_t TIMER2VALUE;
+  union {
+    __IO uint32_t TIMER2CONTROL;
+    stc_dtim_timer2control_field_t TIMER2CONTROL_f;
+  };
+  __IO uint32_t TIMER2INTCLR;
+  union {
+    __IO uint32_t TIMER2RIS;
+    stc_dtim_timer2ris_field_t TIMER2RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER2MIS;
+    stc_dtim_timer2mis_field_t TIMER2MIS_f;
+  };
+  __IO uint32_t TIMER2BGLOAD;
+}FM3_DTIM_TypeDef;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Free Running Timer registers */
+typedef struct
+{
+        uint8_t RESERVED0[40];
+  __IO uint16_t TCCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TCDT0;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TCSA0;
+    stc_mft_frt_tcsa0_field_t TCSA0_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t TCSB0;
+    stc_mft_frt_tcsb0_field_t TCSB0_f;
+  };
+        uint8_t RESERVED4[2];
+  __IO uint16_t TCCP1;
+        uint8_t RESERVED5[2];
+  __IO uint16_t TCDT1;
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t TCSA1;
+    stc_mft_frt_tcsa1_field_t TCSA1_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t TCSB1;
+    stc_mft_frt_tcsb1_field_t TCSB1_f;
+  };
+        uint8_t RESERVED8[2];
+  __IO uint16_t TCCP2;
+        uint8_t RESERVED9[2];
+  __IO uint16_t TCDT2;
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t TCSA2;
+    stc_mft_frt_tcsa2_field_t TCSA2_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t TCSB2;
+    stc_mft_frt_tcsb2_field_t TCSB2_f;
+  };
+}FM3_MFT_FRT_TypeDef;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+typedef struct
+{
+  __IO uint16_t OCCP0;
+        uint8_t RESERVED0[2];
+  __IO uint16_t OCCP1;
+        uint8_t RESERVED1[2];
+  __IO uint16_t OCCP2;
+        uint8_t RESERVED2[2];
+  __IO uint16_t OCCP3;
+        uint8_t RESERVED3[2];
+  __IO uint16_t OCCP4;
+        uint8_t RESERVED4[2];
+  __IO uint16_t OCCP5;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t OCSA10;
+    stc_mft_ocu_ocsa10_field_t OCSA10_f;
+  };
+  union {
+    __IO  uint8_t OCSB10;
+    stc_mft_ocu_ocsb10_field_t OCSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t OCSA32;
+    stc_mft_ocu_ocsa32_field_t OCSA32_f;
+  };
+  union {
+    __IO  uint8_t OCSB32;
+    stc_mft_ocu_ocsb32_field_t OCSB32_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO  uint8_t OCSA54;
+    stc_mft_ocu_ocsa54_field_t OCSA54_f;
+  };
+  union {
+    __IO  uint8_t OCSB54;
+    stc_mft_ocu_ocsb54_field_t OCSB54_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t OCSC;
+    stc_mft_ocu_ocsc_field_t OCSC_f;
+  };
+        uint8_t RESERVED9[50];
+  union {
+    __IO  uint8_t OCFS10;
+    stc_mft_ocu_ocfs10_field_t OCFS10_f;
+  };
+  union {
+    __IO  uint8_t OCFS32;
+    stc_mft_ocu_ocfs32_field_t OCFS32_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO  uint8_t OCFS54;
+    stc_mft_ocu_ocfs54_field_t OCFS54_f;
+  };
+}FM3_MFT_OCU_TypeDef;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+typedef struct
+{
+        uint8_t RESERVED0[128];
+  __IO uint16_t WFTM10;
+        uint8_t RESERVED1[2];
+  __IO uint16_t WFTM32;
+        uint8_t RESERVED2[2];
+  __IO uint16_t WFTM54;
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t WFSA10;
+    stc_mft_wfg_wfsa10_field_t WFSA10_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t WFSA32;
+    stc_mft_wfg_wfsa32_field_t WFSA32_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t WFSA54;
+    stc_mft_wfg_wfsa54_field_t WFSA54_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t WFIR;
+    stc_mft_wfg_wfir_field_t WFIR_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t NZCL;
+    stc_mft_wfg_nzcl_field_t NZCL_f;
+  };
+}FM3_MFT_WFG_TypeDef;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[96];
+  union {
+    __IO  uint8_t ICFS10;
+    stc_mft_icu_icfs10_field_t ICFS10_f;
+  };
+  union {
+    __IO  uint8_t ICFS32;
+    stc_mft_icu_icfs32_field_t ICFS32_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint16_t ICCP0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ICCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ICCP2;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ICCP3;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t ICSA10;
+    stc_mft_icu_icsa10_field_t ICSA10_f;
+  };
+  union {
+    __IO  uint8_t ICSB10;
+    stc_mft_icu_icsb10_field_t ICSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ICSA32;
+    stc_mft_icu_icsa32_field_t ICSA32_f;
+  };
+  union {
+    __IO  uint8_t ICSB32;
+    stc_mft_icu_icsb32_field_t ICSB32_f;
+  };
+}FM3_MFT_ICU_TypeDef;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[160];
+  __IO uint16_t ACCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t ACCPDN0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ACCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ACCPDN1;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ACCP2;
+        uint8_t RESERVED5[2];
+  __IO uint16_t ACCPDN2;
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ACSB;
+    stc_mft_adcmp_acsb_field_t ACSB_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t ACSA;
+    stc_mft_adcmp_acsa_field_t ACSA_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t ATSA;
+    stc_mft_adcmp_atsa_field_t ATSA_f;
+  };
+}FM3_MFT_ADCMP_TypeDef;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer PPG registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t TTCR0;
+    stc_mft_ppg_ttcr0_field_t TTCR0_f;
+  };
+        uint8_t RESERVED1[7];
+  __IO  uint8_t COMP0;
+        uint8_t RESERVED2[2];
+  __IO  uint8_t COMP2;
+        uint8_t RESERVED3[4];
+  __IO  uint8_t COMP4;
+        uint8_t RESERVED4[2];
+  __IO  uint8_t COMP6;
+        uint8_t RESERVED5[12];
+  union {
+    __IO  uint8_t TTCR1;
+    stc_mft_ppg_ttcr1_field_t TTCR1_f;
+  };
+        uint8_t RESERVED6[7];
+  __IO  uint8_t COMP1;
+        uint8_t RESERVED7[2];
+  __IO  uint8_t COMP3;
+        uint8_t RESERVED8[4];
+  __IO  uint8_t COMP5;
+        uint8_t RESERVED9[2];
+  __IO  uint8_t COMP7;
+        uint8_t RESERVED10[12];
+  union {
+    __IO  uint8_t TTCR2;
+    stc_mft_ppg_ttcr2_field_t TTCR2_f;
+  };
+        uint8_t RESERVED11[7];
+  __IO  uint8_t COMP8;
+        uint8_t RESERVED12[2];
+  __IO  uint8_t COMP10;
+        uint8_t RESERVED13[4];
+  __IO  uint8_t COMP12;
+        uint8_t RESERVED14[2];
+  __IO  uint8_t COMP14;
+        uint8_t RESERVED15[171];
+  union {
+    __IO uint16_t TRG;
+    stc_mft_ppg_trg_field_t TRG_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t REVC;
+    stc_mft_ppg_revc_field_t REVC_f;
+  };
+        uint8_t RESERVED17[58];
+  union {
+    __IO uint16_t TRG1;
+    stc_mft_ppg_trg1_field_t TRG1_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t REVC1;
+    stc_mft_ppg_revc1_field_t REVC1_f;
+  };
+        uint8_t RESERVED19[186];
+  union {
+    __IO  uint8_t PPGC1;
+    stc_mft_ppg_ppgc1_field_t PPGC1_f;
+  };
+  union {
+    __IO  uint8_t PPGC0;
+    stc_mft_ppg_ppgc0_field_t PPGC0_f;
+  };
+        uint8_t RESERVED20[2];
+  union {
+    __IO  uint8_t PPGC3;
+    stc_mft_ppg_ppgc3_field_t PPGC3_f;
+  };
+  union {
+    __IO  uint8_t PPGC2;
+    stc_mft_ppg_ppgc2_field_t PPGC2_f;
+  };
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t PRL0;
+    struct {
+      __IO  uint8_t PRLL0;
+      __IO  uint8_t PRLH0;
+    };
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t PRL1;
+    struct {
+      __IO  uint8_t PRLL1;
+      __IO  uint8_t PRLH1;
+    };
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t PRL2;
+    struct {
+      __IO  uint8_t PRLL2;
+      __IO  uint8_t PRLH2;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t PRL3;
+    struct {
+      __IO  uint8_t PRLL3;
+      __IO  uint8_t PRLH3;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO  uint8_t GATEC0;
+    stc_mft_ppg_gatec0_field_t GATEC0_f;
+  };
+        uint8_t RESERVED26[39];
+  union {
+    __IO  uint8_t PPGC5;
+    stc_mft_ppg_ppgc5_field_t PPGC5_f;
+  };
+  union {
+    __IO  uint8_t PPGC4;
+    stc_mft_ppg_ppgc4_field_t PPGC4_f;
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO  uint8_t PPGC7;
+    stc_mft_ppg_ppgc7_field_t PPGC7_f;
+  };
+  union {
+    __IO  uint8_t PPGC6;
+    stc_mft_ppg_ppgc6_field_t PPGC6_f;
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t PRL4;
+    struct {
+      __IO  uint8_t PRLL4;
+      __IO  uint8_t PRLH4;
+    };
+  };
+        uint8_t RESERVED29[2];
+  union {
+    __IO uint16_t PRL5;
+    struct {
+      __IO  uint8_t PRLL5;
+      __IO  uint8_t PRLH5;
+    };
+  };
+        uint8_t RESERVED30[2];
+  union {
+    __IO uint16_t PRL6;
+    struct {
+      __IO  uint8_t PRLL6;
+      __IO  uint8_t PRLH6;
+    };
+  };
+        uint8_t RESERVED31[2];
+  union {
+    __IO uint16_t PRL7;
+    struct {
+      __IO  uint8_t PRLL7;
+      __IO  uint8_t PRLH7;
+    };
+  };
+        uint8_t RESERVED32[2];
+  union {
+    __IO  uint8_t GATEC4;
+    stc_mft_ppg_gatec4_field_t GATEC4_f;
+  };
+        uint8_t RESERVED33[39];
+  union {
+    __IO  uint8_t PPGC9;
+    stc_mft_ppg_ppgc9_field_t PPGC9_f;
+  };
+  union {
+    __IO  uint8_t PPGC8;
+    stc_mft_ppg_ppgc8_field_t PPGC8_f;
+  };
+        uint8_t RESERVED34[2];
+  union {
+    __IO  uint8_t PPGC11;
+    stc_mft_ppg_ppgc11_field_t PPGC11_f;
+  };
+  union {
+    __IO  uint8_t PPGC10;
+    stc_mft_ppg_ppgc10_field_t PPGC10_f;
+  };
+        uint8_t RESERVED35[2];
+  union {
+    __IO uint16_t PRL8;
+    struct {
+      __IO  uint8_t PRLL8;
+      __IO  uint8_t PRLH8;
+    };
+  };
+        uint8_t RESERVED36[2];
+  union {
+    __IO uint16_t PRL9;
+    struct {
+      __IO  uint8_t PRLL9;
+      __IO  uint8_t PRLH9;
+    };
+  };
+        uint8_t RESERVED37[2];
+  union {
+    __IO uint16_t PRL10;
+    struct {
+      __IO  uint8_t PRLL10;
+      __IO  uint8_t PRLH10;
+    };
+  };
+        uint8_t RESERVED38[2];
+  union {
+    __IO uint16_t PRL11;
+    struct {
+      __IO  uint8_t PRLL11;
+      __IO  uint8_t PRLH11;
+    };
+  };
+        uint8_t RESERVED39[2];
+  union {
+    __IO  uint8_t GATEC8;
+    stc_mft_ppg_gatec8_field_t GATEC8_f;
+  };
+        uint8_t RESERVED40[39];
+  union {
+    __IO  uint8_t PPGC13;
+    stc_mft_ppg_ppgc13_field_t PPGC13_f;
+  };
+  union {
+    __IO  uint8_t PPGC12;
+    stc_mft_ppg_ppgc12_field_t PPGC12_f;
+  };
+        uint8_t RESERVED41[2];
+  union {
+    __IO  uint8_t PPGC15;
+    stc_mft_ppg_ppgc15_field_t PPGC15_f;
+  };
+  union {
+    __IO  uint8_t PPGC14;
+    stc_mft_ppg_ppgc14_field_t PPGC14_f;
+  };
+        uint8_t RESERVED42[2];
+  union {
+    __IO uint16_t PRL12;
+    struct {
+      __IO  uint8_t PRLL12;
+      __IO  uint8_t PRLH12;
+    };
+  };
+        uint8_t RESERVED43[2];
+  union {
+    __IO uint16_t PRL13;
+    struct {
+      __IO  uint8_t PRLL13;
+      __IO  uint8_t PRLH13;
+    };
+  };
+        uint8_t RESERVED44[2];
+  union {
+    __IO uint16_t PRL14;
+    struct {
+      __IO  uint8_t PRLL14;
+      __IO  uint8_t PRLH14;
+    };
+  };
+        uint8_t RESERVED45[2];
+  union {
+    __IO uint16_t PRL15;
+    struct {
+      __IO  uint8_t PRLL15;
+      __IO  uint8_t PRLH15;
+    };
+  };
+        uint8_t RESERVED46[2];
+  union {
+    __IO  uint8_t GATEC12;
+    stc_mft_ppg_gatec12_field_t GATEC12_f;
+  };
+        uint8_t RESERVED47[39];  
+  union {
+    __IO  uint8_t PPGC17;
+    stc_mft_ppg_ppgc17_field_t PPGC17_f;
+  };
+  union {
+    __IO  uint8_t PPGC16;
+    stc_mft_ppg_ppgc16_field_t PPGC16_f;
+  };
+        uint8_t RESERVED48[2];
+  union {
+    __IO  uint8_t PPGC19;
+    stc_mft_ppg_ppgc19_field_t PPGC19_f;
+  };
+  union {
+    __IO  uint8_t PPGC18;
+    stc_mft_ppg_ppgc18_field_t PPGC18_f;
+  };
+        uint8_t RESERVED49[2];
+  union {
+    __IO uint16_t PRL16;
+    struct {
+      __IO  uint8_t PRLL16;
+      __IO  uint8_t PRLH16;
+    };
+  };
+        uint8_t RESERVED50[2];
+  union {
+    __IO uint16_t PRL17;
+    struct {
+      __IO  uint8_t PRLL17;
+      __IO  uint8_t PRLH17;
+    };
+  };
+        uint8_t RESERVED51[2];
+  union {
+    __IO uint16_t PRL18;
+    struct {
+      __IO  uint8_t PRLL18;
+      __IO  uint8_t PRLH18;
+    };
+  };
+        uint8_t RESERVED52[2];
+  union {
+    __IO uint16_t PRL19;
+    struct {
+      __IO  uint8_t PRLL19;
+      __IO  uint8_t PRLH19;
+    };
+  };
+        uint8_t RESERVED53[2];
+  union {
+    __IO  uint8_t GATEC16;
+    stc_mft_ppg_gatec16_field_t GATEC16_f;
+  };
+        uint8_t RESERVED54[39];
+  union {
+    __IO  uint8_t PPGC21;
+    stc_mft_ppg_ppgc21_field_t PPGC21_f;
+  };
+  union {
+    __IO  uint8_t PPGC20;
+    stc_mft_ppg_ppgc20_field_t PPGC20_f;
+  };
+        uint8_t RESERVED55[2];
+  union {
+    __IO  uint8_t PPGC23;
+    stc_mft_ppg_ppgc23_field_t PPGC23_f;
+  };
+  union {
+    __IO  uint8_t PPGC22;
+    stc_mft_ppg_ppgc22_field_t PPGC22_f;
+  };
+        uint8_t RESERVED56[2];
+  union {
+    __IO uint16_t PRL20;
+    struct {
+      __IO  uint8_t PRLL20;
+      __IO  uint8_t PRLH20;
+    };
+  };
+        uint8_t RESERVED57[2];
+  union {
+    __IO uint16_t PRL21;
+    struct {
+      __IO  uint8_t PRLL21;
+      __IO  uint8_t PRLH21;
+    };
+  };
+        uint8_t RESERVED58[2];
+  union {
+    __IO uint16_t PRL22;
+    struct {
+      __IO  uint8_t PRLL22;
+      __IO  uint8_t PRLH22;
+    };
+  };
+        uint8_t RESERVED59[2];
+  union {
+    __IO uint16_t PRL23;
+    struct {
+      __IO  uint8_t PRLL23;
+      __IO  uint8_t PRLH23;
+    };
+  };
+        uint8_t RESERVED60[2];
+  union {
+    __IO  uint8_t GATEC20;
+    stc_mft_ppg_gatec20_field_t GATEC20_f;
+  };
+}FM3_MFT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PPG registers */
+typedef struct
+{
+  __IO uint16_t PRLL;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PRLH;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_ppg_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_ppg_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_ppg_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWM registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PDUT;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwm_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwm_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwm_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWM_TypeDef;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* Base Timer 0 RT registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[6];
+  __IO uint16_t TMR;
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_rt_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_rt_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_rt_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_RT_TypeDef;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWC registers */
+typedef struct
+{
+        uint8_t RESERVED0[4];
+  __IO uint16_t DTBF;
+        uint8_t RESERVED1[6];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwc_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwc_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwc_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWC_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL0123;
+    stc_btiosel03_btsel0123_field_t BTSEL0123_f;
+  };
+}FM3_BTIOSEL03_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL4567;
+    stc_btiosel47_btsel4567_field_t BTSEL4567_f;
+  };
+}FM3_BTIOSEL47_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL8B_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL89AB;
+    stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f;
+  };
+}FM3_BTIOSEL8B_TypeDef;
+
+/******************************************************************************
+ * BTIOSELCF_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSELCDEF;
+    stc_btioselcf_btselcdef_field_t BTSELCDEF_f;
+  };
+}FM3_BTIOSELCF_TypeDef;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* Software based Simulation Startup (Base Timer) register */
+typedef struct
+{
+  union {
+    __IO uint16_t BTSSSR;
+    stc_sbssr_btsssr_field_t BTSSSR_f;
+  };
+}FM3_SBSSR_TypeDef;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* Quad position and revolution counter channel 0 registers */
+typedef struct
+{
+  __IO uint16_t QPCR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t QRCR;
+        uint8_t RESERVED1[2];
+  __IO uint16_t QPCCR;
+        uint8_t RESERVED2[2];
+  __IO uint16_t QPRCR;
+        uint8_t RESERVED3[2];
+  __IO uint16_t QMPR;
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t QICR;
+      stc_qprc_qicr_field_t QICR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QICRL;
+        stc_qprc_qicrl_field_t QICRL_f;
+      };
+      union {
+        __IO  uint8_t QICRH;
+        stc_qprc_qicrh_field_t QICRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t QCR;
+      stc_qprc_qcr_field_t QCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QCRL;
+        stc_qprc_qcrl_field_t QCRL_f;
+      };
+      union {
+        __IO  uint8_t QCRH;
+        stc_qprc_qcrh_field_t QCRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t QECR;
+    stc_qprc_qecr_field_t QECR_f;
+  };
+        uint8_t RESERVED7[30];
+  __IO uint16_t QRCRR;
+  __IO uint16_t QPCRR;
+}FM3_QPRC_TypeDef;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* 12-bit ADC unit 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t ADSR;
+    stc_adc_adsr_field_t ADSR_f;
+  };
+  union {
+    __IO  uint8_t ADCR;
+    stc_adc_adcr_field_t ADCR_f;
+  };
+        uint8_t RESERVED0[6];
+  union {
+    __IO  uint8_t SFNS;
+    stc_adc_sfns_field_t SFNS_f;
+  };
+  union {
+    __IO  uint8_t SCCR;
+    stc_adc_sccr_field_t SCCR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint32_t SCFD;
+      stc_adc_scfd_field_t SCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t SCFDL;
+        stc_adc_scfdl_field_t SCFDL_f;
+      };
+      union {
+        __IO uint16_t SCFDH;
+        stc_adc_scfdh_field_t SCFDH_f;
+      };
+    };
+  };
+  union {
+    union {
+      __IO uint16_t SCIS23;
+      stc_adc_scis23_field_t SCIS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS2;
+        stc_adc_scis2_field_t SCIS2_f;
+      };
+      union {
+        __IO  uint8_t SCIS3;
+        stc_adc_scis3_field_t SCIS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t SCIS01;
+      stc_adc_scis01_field_t SCIS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS0;
+        stc_adc_scis0_field_t SCIS0_f;
+      };
+      union {
+        __IO  uint8_t SCIS1;
+        stc_adc_scis1_field_t SCIS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t PFNS;
+    stc_adc_pfns_field_t PFNS_f;
+  };
+  union {
+    __IO  uint8_t PCCR;
+    stc_adc_pccr_field_t PCCR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint32_t PCFD;
+      stc_adc_pcfd_field_t PCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t PCFDL;
+        stc_adc_pcfdl_field_t PCFDL_f;
+      };
+      union {
+        __IO uint16_t PCFDH;
+        stc_adc_pcfdh_field_t PCFDH_f;
+      };
+    };
+  };
+  union {
+    __IO  uint8_t PCIS;
+    stc_adc_pcis_field_t PCIS_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t CMPCR;
+    stc_adc_cmpcr_field_t CMPCR_f;
+  };
+        uint8_t RESERVED6;
+  union {
+    __IO uint16_t CMPD;
+    stc_adc_cmpd_field_t CMPD_f;
+  };
+  union {
+    union {
+      __IO uint16_t ADSS23;
+      stc_adc_adss23_field_t ADSS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS2;
+        stc_adc_adss2_field_t ADSS2_f;
+      };
+      union {
+        __IO  uint8_t ADSS3;
+        stc_adc_adss3_field_t ADSS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED7[2];
+  union {
+    union {
+      __IO uint16_t ADSS01;
+      stc_adc_adss01_field_t ADSS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS0;
+        stc_adc_adss0_field_t ADSS0_f;
+      };
+      union {
+        __IO  uint8_t ADSS1;
+        stc_adc_adss1_field_t ADSS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED8[2];
+  union {
+    union {
+      __IO uint16_t ADST01;
+      stc_adc_adst01_field_t ADST01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADST1;
+        stc_adc_adst1_field_t ADST1_f;
+      };
+      union {
+        __IO  uint8_t ADST0;
+        stc_adc_adst0_field_t ADST0_f;
+      };
+    };
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO  uint8_t ADCT;
+    stc_adc_adct_field_t ADCT_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PRTSL;
+    stc_adc_prtsl_field_t PRTSL_f;
+  };
+  union {
+    __IO  uint8_t SCTSL;
+    stc_adc_sctsl_field_t SCTSL_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO  uint8_t ADCEN;
+    stc_adc_adcen_field_t ADCEN_f;
+  };
+}FM3_ADC_TypeDef;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CR trimming registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t MCR_PSR;
+    stc_crtrim_mcr_psr_field_t MCR_PSR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO uint16_t MCR_FTRM;
+    stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint32_t MCR_RLR;
+}FM3_CRTRIM_TypeDef;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* External interrupt registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ENIR;
+    stc_exti_enir_field_t ENIR_f;
+  };
+  union {
+    __IO uint32_t EIRR;
+    stc_exti_eirr_field_t EIRR_f;
+  };
+  union {
+    __IO uint32_t EICL;
+    stc_exti_eicl_field_t EICL_f;
+  };
+  union {
+    __IO uint32_t ELVR;
+    stc_exti_elvr_field_t ELVR_f;
+  };
+  union {
+    __IO uint32_t ELVR1;
+    stc_exti_elvr1_field_t ELVR1_f;
+  };
+  union {
+    __IO  uint8_t NMIRR;
+    stc_exti_nmirr_field_t NMIRR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t NMICL;
+    stc_exti_nmicl_field_t NMICL_f;
+  };
+}FM3_EXTI_TypeDef;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* Interrupt request read registers */
+typedef struct
+{
+  union {
+    __IO uint32_t DRQSEL;
+    stc_intreq_drqsel_field_t DRQSEL_f;
+  };
+        uint8_t RESERVED0[7];
+  union {
+    __IO  uint8_t ODDPKS;
+    stc_intreq_oddpks_field_t ODDPKS_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t EXC02MON;
+    stc_intreq_exc02mon_field_t EXC02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ00MON;
+    stc_intreq_irq00mon_field_t IRQ00MON_f;
+  };
+  union {
+    __IO uint32_t IRQ01MON;
+    stc_intreq_irq01mon_field_t IRQ01MON_f;
+  };
+  union {
+    __IO uint32_t IRQ02MON;
+    stc_intreq_irq02mon_field_t IRQ02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ03MON;
+    stc_intreq_irq03mon_field_t IRQ03MON_f;
+  };
+  union {
+    __IO uint32_t IRQ04MON;
+    stc_intreq_irq04mon_field_t IRQ04MON_f;
+  };
+  union {
+    __IO uint32_t IRQ05MON;
+    stc_intreq_irq05mon_field_t IRQ05MON_f;
+  };
+  union {
+    __IO uint32_t IRQ06MON;
+    stc_intreq_irq06mon_field_t IRQ06MON_f;
+  };
+  union {
+    __IO uint32_t IRQ07MON;
+    stc_intreq_irq07mon_field_t IRQ07MON_f;
+  };
+  union {
+    __IO uint32_t IRQ08MON;
+    stc_intreq_irq08mon_field_t IRQ08MON_f;
+  };
+  union {
+    __IO uint32_t IRQ09MON;
+    stc_intreq_irq09mon_field_t IRQ09MON_f;
+  };
+  union {
+    __IO uint32_t IRQ10MON;
+    stc_intreq_irq10mon_field_t IRQ10MON_f;
+  };
+  union {
+    __IO uint32_t IRQ11MON;
+    stc_intreq_irq11mon_field_t IRQ11MON_f;
+  };
+  union {
+    __IO uint32_t IRQ12MON;
+    stc_intreq_irq12mon_field_t IRQ12MON_f;
+  };
+  union {
+    __IO uint32_t IRQ13MON;
+    stc_intreq_irq13mon_field_t IRQ13MON_f;
+  };
+  union {
+    __IO uint32_t IRQ14MON;
+    stc_intreq_irq14mon_field_t IRQ14MON_f;
+  };
+  union {
+    __IO uint32_t IRQ15MON;
+    stc_intreq_irq15mon_field_t IRQ15MON_f;
+  };
+  union {
+    __IO uint32_t IRQ16MON;
+    stc_intreq_irq16mon_field_t IRQ16MON_f;
+  };
+  union {
+    __IO uint32_t IRQ17MON;
+    stc_intreq_irq17mon_field_t IRQ17MON_f;
+  };
+  union {
+    __IO uint32_t IRQ18MON;
+    stc_intreq_irq18mon_field_t IRQ18MON_f;
+  };
+  union {
+    __IO uint32_t IRQ19MON;
+    stc_intreq_irq19mon_field_t IRQ19MON_f;
+  };
+  union {
+    __IO uint32_t IRQ20MON;
+    stc_intreq_irq20mon_field_t IRQ20MON_f;
+  };
+  union {
+    __IO uint32_t IRQ21MON;
+    stc_intreq_irq21mon_field_t IRQ21MON_f;
+  };
+  union {
+    __IO uint32_t IRQ22MON;
+    stc_intreq_irq22mon_field_t IRQ22MON_f;
+  };
+  union {
+    __IO uint32_t IRQ23MON;
+    stc_intreq_irq23mon_field_t IRQ23MON_f;
+  };
+  union {
+    __IO uint32_t IRQ24MON;
+    stc_intreq_irq24mon_field_t IRQ24MON_f;
+  };
+  union {
+    __IO uint32_t IRQ25MON;
+    stc_intreq_irq25mon_field_t IRQ25MON_f;
+  };
+  union {
+    __IO uint32_t IRQ26MON;
+    stc_intreq_irq26mon_field_t IRQ26MON_f;
+  };
+  union {
+    __IO uint32_t IRQ27MON;
+    stc_intreq_irq27mon_field_t IRQ27MON_f;
+  };
+  union {
+    __IO uint32_t IRQ28MON;
+    stc_intreq_irq28mon_field_t IRQ28MON_f;
+  };
+  union {
+    __IO uint32_t IRQ29MON;
+    stc_intreq_irq29mon_field_t IRQ29MON_f;
+  };
+  union {
+    __IO uint32_t IRQ30MON;
+    stc_intreq_irq30mon_field_t IRQ30MON_f;
+  };
+  union {
+    __IO uint32_t IRQ31MON;
+    stc_intreq_irq31mon_field_t IRQ31MON_f;
+  };
+  union {
+    __IO uint32_t IRQ32MON;
+    stc_intreq_irq32mon_field_t IRQ32MON_f;
+  };
+  union {
+    __IO uint32_t IRQ33MON;
+    stc_intreq_irq33mon_field_t IRQ33MON_f;
+  };
+  union {
+    __IO uint32_t IRQ34MON;
+    stc_intreq_irq34mon_field_t IRQ34MON_f;
+  };
+  union {
+    __IO uint32_t IRQ35MON;
+    stc_intreq_irq35mon_field_t IRQ35MON_f;
+  };
+  union {
+    __IO uint32_t IRQ36MON;
+    stc_intreq_irq36mon_field_t IRQ36MON_f;
+  };
+  union {
+    __IO uint32_t IRQ37MON;
+    stc_intreq_irq37mon_field_t IRQ37MON_f;
+  };
+  union {
+    __IO uint32_t IRQ38MON;
+    stc_intreq_irq38mon_field_t IRQ38MON_f;
+  };
+  union {
+    __IO uint32_t IRQ39MON;
+    stc_intreq_irq39mon_field_t IRQ39MON_f;
+  };
+  union {
+    __IO uint32_t IRQ40MON;
+    stc_intreq_irq40mon_field_t IRQ40MON_f;
+  };
+  union {
+    __IO uint32_t IRQ41MON;
+    stc_intreq_irq41mon_field_t IRQ41MON_f;
+  };
+  union {
+    __IO uint32_t IRQ42MON;
+    stc_intreq_irq42mon_field_t IRQ42MON_f;
+  };
+  union {
+    __IO uint32_t IRQ43MON;
+    stc_intreq_irq43mon_field_t IRQ43MON_f;
+  };
+  union {
+    __IO uint32_t IRQ44MON;
+    stc_intreq_irq44mon_field_t IRQ44MON_f;
+  };
+  union {
+    __IO uint32_t IRQ45MON;
+    stc_intreq_irq45mon_field_t IRQ45MON_f;
+  };
+  union {
+    __IO uint32_t IRQ46MON;
+    stc_intreq_irq46mon_field_t IRQ46MON_f;
+  };
+    __IO uint32_t IRQ47MON;
+        uint8_t RESERVED2[300];
+  union {
+    __IO uint32_t DRQSEL1;
+    stc_intreq_drqsel1_field_t DRQSEL1_f;
+  };
+  union {
+    __IO uint32_t DQESEL;
+    stc_intreq_dqesel_field_t DQESEL_f;
+  };
+        uint8_t RESERVED3[7];
+  union {
+    __IO  uint8_t ODDPKS1;
+    stc_intreq_oddpks1_field_t ODDPKS1_f;
+  };
+}FM3_INTREQ_TypeDef;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* General purpose I/O registers */
+typedef struct
+{
+  union {
+    __IO uint32_t PFR0;
+    stc_gpio_pfr0_field_t PFR0_f;
+  };
+  union {
+    __IO uint32_t PFR1;
+    stc_gpio_pfr1_field_t PFR1_f;
+  };
+  union {
+    __IO uint32_t PFR2;
+    stc_gpio_pfr2_field_t PFR2_f;
+  };
+  union {
+    __IO uint32_t PFR3;
+    stc_gpio_pfr3_field_t PFR3_f;
+  };
+  union {
+    __IO uint32_t PFR4;
+    stc_gpio_pfr4_field_t PFR4_f;
+  };
+  union {
+    __IO uint32_t PFR5;
+    stc_gpio_pfr5_field_t PFR5_f;
+  };
+  union {
+    __IO uint32_t PFR6;
+    stc_gpio_pfr6_field_t PFR6_f;
+  };
+  union {
+    __IO uint32_t PFR7;
+    stc_gpio_pfr7_field_t PFR7_f;
+  };
+  union {
+    __IO uint32_t PFR8;
+    stc_gpio_pfr8_field_t PFR8_f;
+  };
+  union {
+    __IO uint32_t PFR9;
+    stc_gpio_pfr9_field_t PFR9_f;
+  };
+  union {
+    __IO uint32_t PFRA;
+    stc_gpio_pfra_field_t PFRA_f;
+  };
+  union {
+    __IO uint32_t PFRB;
+    stc_gpio_pfrb_field_t PFRB_f;
+  };
+  union {
+    __IO uint32_t PFRC;
+    stc_gpio_pfrc_field_t PFRC_f;
+  };
+  union {
+    __IO uint32_t PFRD;
+    stc_gpio_pfrd_field_t PFRD_f;
+  };
+  union {
+    __IO uint32_t PFRE;
+    stc_gpio_pfre_field_t PFRE_f;
+  };
+  union {
+    __IO uint32_t PFRF;
+    stc_gpio_pfrf_field_t PFRF_f;
+  };
+        uint8_t RESERVED0[192];
+  union {
+    __IO uint32_t PCR0;
+    stc_gpio_pcr0_field_t PCR0_f;
+  };
+  union {
+    __IO uint32_t PCR1;
+    stc_gpio_pcr1_field_t PCR1_f;
+  };
+  union {
+    __IO uint32_t PCR2;
+    stc_gpio_pcr2_field_t PCR2_f;
+  };
+  union {
+    __IO uint32_t PCR3;
+    stc_gpio_pcr3_field_t PCR3_f;
+  };
+  union {
+    __IO uint32_t PCR4;
+    stc_gpio_pcr4_field_t PCR4_f;
+  };
+  union {
+    __IO uint32_t PCR5;
+    stc_gpio_pcr5_field_t PCR5_f;
+  };
+  union {
+    __IO uint32_t PCR6;
+    stc_gpio_pcr6_field_t PCR6_f;
+  };
+  union {
+    __IO uint32_t PCR7;
+    stc_gpio_pcr7_field_t PCR7_f;
+  };
+  __IO uint32_t PCR8;
+  union {
+    __IO uint32_t PCR9;
+    stc_gpio_pcr9_field_t PCR9_f;
+  };
+  union {
+    __IO uint32_t PCRA;
+    stc_gpio_pcra_field_t PCRA_f;
+  };
+  union {
+    __IO uint32_t PCRB;
+    stc_gpio_pcrb_field_t PCRB_f;
+  };
+  union {
+    __IO uint32_t PCRC;
+    stc_gpio_pcrc_field_t PCRC_f;
+  };
+  union {
+    __IO uint32_t PCRD;
+    stc_gpio_pcrd_field_t PCRD_f;
+  };
+  union {
+    __IO uint32_t PCRE;
+    stc_gpio_pcre_field_t PCRE_f;
+  };
+  __IO uint32_t PCRF;
+        uint8_t RESERVED1[192];
+  union {
+    __IO uint32_t DDR0;
+    stc_gpio_ddr0_field_t DDR0_f;
+  };
+  union {
+    __IO uint32_t DDR1;
+    stc_gpio_ddr1_field_t DDR1_f;
+  };
+  union {
+    __IO uint32_t DDR2;
+    stc_gpio_ddr2_field_t DDR2_f;
+  };
+  union {
+    __IO uint32_t DDR3;
+    stc_gpio_ddr3_field_t DDR3_f;
+  };
+  union {
+    __IO uint32_t DDR4;
+    stc_gpio_ddr4_field_t DDR4_f;
+  };
+  union {
+    __IO uint32_t DDR5;
+    stc_gpio_ddr5_field_t DDR5_f;
+  };
+  union {
+    __IO uint32_t DDR6;
+    stc_gpio_ddr6_field_t DDR6_f;
+  };
+  union {
+    __IO uint32_t DDR7;
+    stc_gpio_ddr7_field_t DDR7_f;
+  };
+  union {
+    __IO uint32_t DDR8;
+    stc_gpio_ddr8_field_t DDR8_f;
+  };
+  union {
+    __IO uint32_t DDR9;
+    stc_gpio_ddr9_field_t DDR9_f;
+  };
+  union {
+    __IO uint32_t DDRA;
+    stc_gpio_ddra_field_t DDRA_f;
+  };
+  union {
+    __IO uint32_t DDRB;
+    stc_gpio_ddrb_field_t DDRB_f;
+  };
+  union {
+    __IO uint32_t DDRC;
+    stc_gpio_ddrc_field_t DDRC_f;
+  };
+  union {
+    __IO uint32_t DDRD;
+    stc_gpio_ddrd_field_t DDRD_f;
+  };
+  union {
+    __IO uint32_t DDRE;
+    stc_gpio_ddre_field_t DDRE_f;
+  };
+  union {
+    __IO uint32_t DDRF;
+    stc_gpio_ddrf_field_t DDRF_f;
+  };
+        uint8_t RESERVED2[192];
+  union {
+    __IO uint32_t PDIR0;
+    stc_gpio_pdir0_field_t PDIR0_f;
+  };
+  union {
+    __IO uint32_t PDIR1;
+    stc_gpio_pdir1_field_t PDIR1_f;
+  };
+  union {
+    __IO uint32_t PDIR2;
+    stc_gpio_pdir2_field_t PDIR2_f;
+  };
+  union {
+    __IO uint32_t PDIR3;
+    stc_gpio_pdir3_field_t PDIR3_f;
+  };
+  union {
+    __IO uint32_t PDIR4;
+    stc_gpio_pdir4_field_t PDIR4_f;
+  };
+  union {
+    __IO uint32_t PDIR5;
+    stc_gpio_pdir5_field_t PDIR5_f;
+  };
+  union {
+    __IO uint32_t PDIR6;
+    stc_gpio_pdir6_field_t PDIR6_f;
+  };
+  union {
+    __IO uint32_t PDIR7;
+    stc_gpio_pdir7_field_t PDIR7_f;
+  };
+  union {
+    __IO uint32_t PDIR8;
+    stc_gpio_pdir8_field_t PDIR8_f;
+  };
+  union {
+    __IO uint32_t PDIR9;
+    stc_gpio_pdir9_field_t PDIR9_f;
+  };
+  union {
+    __IO uint32_t PDIRA;
+    stc_gpio_pdira_field_t PDIRA_f;
+  };
+  union {
+    __IO uint32_t PDIRB;
+    stc_gpio_pdirb_field_t PDIRB_f;
+  };
+  union {
+    __IO uint32_t PDIRC;
+    stc_gpio_pdirc_field_t PDIRC_f;
+  };
+  union {
+    __IO uint32_t PDIRD;
+    stc_gpio_pdird_field_t PDIRD_f;
+  };
+  union {
+    __IO uint32_t PDIRE;
+    stc_gpio_pdire_field_t PDIRE_f;
+  };
+  union {
+    __IO uint32_t PDIRF;
+    stc_gpio_pdirf_field_t PDIRF_f;
+  };
+        uint8_t RESERVED3[192];
+  union {
+    __IO uint32_t PDOR0;
+    stc_gpio_pdor0_field_t PDOR0_f;
+  };
+  union {
+    __IO uint32_t PDOR1;
+    stc_gpio_pdor1_field_t PDOR1_f;
+  };
+  union {
+    __IO uint32_t PDOR2;
+    stc_gpio_pdor2_field_t PDOR2_f;
+  };
+  union {
+    __IO uint32_t PDOR3;
+    stc_gpio_pdor3_field_t PDOR3_f;
+  };
+  union {
+    __IO uint32_t PDOR4;
+    stc_gpio_pdor4_field_t PDOR4_f;
+  };
+  union {
+    __IO uint32_t PDOR5;
+    stc_gpio_pdor5_field_t PDOR5_f;
+  };
+  union {
+    __IO uint32_t PDOR6;
+    stc_gpio_pdor6_field_t PDOR6_f;
+  };
+  union {
+    __IO uint32_t PDOR7;
+    stc_gpio_pdor7_field_t PDOR7_f;
+  };
+  union {
+    __IO uint32_t PDOR8;
+    stc_gpio_pdor8_field_t PDOR8_f;
+  };
+  union {
+    __IO uint32_t PDOR9;
+    stc_gpio_pdor9_field_t PDOR9_f;
+  };
+  union {
+    __IO uint32_t PDORA;
+    stc_gpio_pdora_field_t PDORA_f;
+  };
+  union {
+    __IO uint32_t PDORB;
+    stc_gpio_pdorb_field_t PDORB_f;
+  };
+  union {
+    __IO uint32_t PDORC;
+    stc_gpio_pdorc_field_t PDORC_f;
+  };
+  union {
+    __IO uint32_t PDORD;
+    stc_gpio_pdord_field_t PDORD_f;
+  };
+  union {
+    __IO uint32_t PDORE;
+    stc_gpio_pdore_field_t PDORE_f;
+  };
+  union {
+    __IO uint32_t PDORF;
+    stc_gpio_pdorf_field_t PDORF_f;
+  };
+        uint8_t RESERVED4[192];
+  union {
+    __IO uint32_t ADE;
+    stc_gpio_ade_field_t ADE_f;
+  };
+        uint8_t RESERVED5[124];
+  union {
+    __IO uint32_t SPSR;
+    stc_gpio_spsr_field_t SPSR_f;
+  };
+        uint8_t RESERVED6[124];
+  union {
+    __IO uint32_t EPFR00;
+    stc_gpio_epfr00_field_t EPFR00_f;
+  };
+  union {
+    __IO uint32_t EPFR01;
+    stc_gpio_epfr01_field_t EPFR01_f;
+  };
+  union {
+    __IO uint32_t EPFR02;
+    stc_gpio_epfr02_field_t EPFR02_f;
+  };
+  union {
+    __IO uint32_t EPFR03;
+    stc_gpio_epfr03_field_t EPFR03_f;
+  };
+  union {
+    __IO uint32_t EPFR04;
+    stc_gpio_epfr04_field_t EPFR04_f;
+  };
+  union {
+    __IO uint32_t EPFR05;
+    stc_gpio_epfr05_field_t EPFR05_f;
+  };
+  union {
+    __IO uint32_t EPFR06;
+    stc_gpio_epfr06_field_t EPFR06_f;
+  };
+  union {
+    __IO uint32_t EPFR07;
+    stc_gpio_epfr07_field_t EPFR07_f;
+  };
+  union {
+    __IO uint32_t EPFR08;
+    stc_gpio_epfr08_field_t EPFR08_f;
+  };
+  union {
+    __IO uint32_t EPFR09;
+    stc_gpio_epfr09_field_t EPFR09_f;
+  };
+  union {
+    __IO uint32_t EPFR10;
+    stc_gpio_epfr10_field_t EPFR10_f;
+  };
+  union {
+    __IO uint32_t EPFR11;
+    stc_gpio_epfr11_field_t EPFR11_f;
+  };
+  union {
+    __IO uint32_t EPFR12;
+    stc_gpio_epfr12_field_t EPFR12_f;
+  };
+  union {
+    __IO uint32_t EPFR13;
+    stc_gpio_epfr13_field_t EPFR13_f;
+  };
+  union {
+    __IO uint32_t EPFR14;
+    stc_gpio_epfr14_field_t EPFR14_f;
+  };
+  union {
+    __IO uint32_t EPFR15;
+    stc_gpio_epfr15_field_t EPFR15_f;
+  };
+        uint8_t RESERVED7[192];
+  union {
+    __IO uint32_t PZR0;
+    stc_gpio_pzr0_field_t PZR0_f;
+  };
+  union {
+    __IO uint32_t PZR1;
+    stc_gpio_pzr1_field_t PZR1_f;
+  };
+  union {
+    __IO uint32_t PZR2;
+    stc_gpio_pzr2_field_t PZR2_f;
+  };
+  union {
+    __IO uint32_t PZR3;
+    stc_gpio_pzr3_field_t PZR3_f;
+  };
+  union {
+    __IO uint32_t PZR4;
+    stc_gpio_pzr4_field_t PZR4_f;
+  };
+  union {
+    __IO uint32_t PZR5;
+    stc_gpio_pzr5_field_t PZR5_f;
+  };
+  union {
+    __IO uint32_t PZR6;
+    stc_gpio_pzr6_field_t PZR6_f;
+  };
+  union {
+    __IO uint32_t PZR7;
+    stc_gpio_pzr7_field_t PZR7_f;
+  };
+  union {
+    __IO uint32_t PZR8;
+    stc_gpio_pzr8_field_t PZR8_f;
+  };
+  union {
+    __IO uint32_t PZR9;
+    stc_gpio_pzr9_field_t PZR9_f;
+  };
+  union {
+    __IO uint32_t PZRA;
+    stc_gpio_pzra_field_t PZRA_f;
+  };
+  union {
+    __IO uint32_t PZRB;
+    stc_gpio_pzrb_field_t PZRB_f;
+  };
+  union {
+    __IO uint32_t PZRC;
+    stc_gpio_pzrc_field_t PZRC_f;
+  };
+  union {
+    __IO uint32_t PZRD;
+    stc_gpio_pzrd_field_t PZRD_f;
+  };
+  union {
+    __IO uint32_t PZRE;
+    stc_gpio_pzre_field_t PZRE_f;
+  };
+  union {
+    __IO uint32_t PZRF;
+    stc_gpio_pzrf_field_t PZRF_f;
+  };
+}FM3_GPIO_TypeDef;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* Low voltage detection registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t LVD_CTL;
+    stc_lvd_lvd_ctl_field_t LVD_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t LVD_STR;
+    stc_lvd_lvd_str_field_t LVD_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t LVD_CLR;
+    stc_lvd_lvd_clr_field_t LVD_CLR_f;
+  };
+        uint8_t RESERVED2[3];
+  __IO uint32_t LVD_RLR;
+  union {
+    __IO  uint8_t LVD_STR2;
+    stc_lvd_lvd_str2_field_t LVD_STR2_f;
+  };
+}FM3_LVD_TypeDef;
+
+/******************************************************************************
+ * USBETHERNETCLK
+ ******************************************************************************/
+/* USB Ethernet clock registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t UCCR;
+    stc_usbethernetclk_uccr_field_t UCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t UPCR1;
+    stc_usbethernetclk_upcr1_field_t UPCR1_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t UPCR2;
+    stc_usbethernetclk_upcr2_field_t UPCR2_f;
+  };
+        uint8_t RESERVED2[3];
+  union {
+    __IO  uint8_t UPCR3;
+    stc_usbethernetclk_upcr3_field_t UPCR3_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t UPCR4;
+    stc_usbethernetclk_upcr4_field_t UPCR4_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t UP_STR;
+    stc_usbethernetclk_up_str_field_t UP_STR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t UPINT_ENR;
+    stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t UPINT_CLR;
+    stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO  uint8_t UPINT_STR;
+    stc_usbethernetclk_upint_str_field_t UPINT_STR_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t UPCR5;
+    stc_usbethernetclk_upcr5_field_t UPCR5_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t UPCR6;
+    stc_usbethernetclk_upcr6_field_t UPCR6_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t UPCR7;
+    stc_usbethernetclk_upcr7_field_t UPCR7_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t USBEN0;
+    stc_usbethernetclk_usben0_field_t USBEN0_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO  uint8_t USBEN1;
+    stc_usbethernetclk_usben1_field_t USBEN1_f;
+  };
+}FM3_USBETHERNETCLK_TypeDef;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs03_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs03_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_UART_TypeDef;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+}FM3_MFS03_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs03_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs03_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs03_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs03_i2c_ismk_field_t ISMK_f;
+  };
+}FM3_MFS03_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs47_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs47_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_uart_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_uart_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_uart_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_uart_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_uart_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_uart_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_UART_TypeDef;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_csio_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_csio_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_csio_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_csio_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_csio_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_csio_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_lin_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_lin_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_lin_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_lin_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_lin_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_lin_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs47_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs47_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs47_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs47_i2c_ismk_field_t ISMK_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_i2c_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_i2c_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_i2c_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_i2c_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct
+{
+  union {
+    __IO  uint16_t I2CDNF;
+    stc_mfs_nfc_i2cdnf_field_t I2CDNF_f;
+  };
+}FM3_MFS_NFC_TypeDef;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t CRCCR;
+    stc_crc_crccr_field_t CRCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t CRCINIT;
+  union {
+    __IO uint32_t CRCIN;
+    struct {
+      union {
+        __IO uint16_t CRCINL;
+        struct {
+          __IO  uint8_t CRCINLL;
+          __IO  uint8_t CRCINLH;
+        };
+      };
+      union {
+        __IO uint16_t CRCINH;
+        struct {
+          __IO  uint8_t CRCINHL;
+          __IO  uint8_t CRCINHH;
+        };
+      };
+    };
+  };
+  __IO uint32_t CRCR;
+}FM3_CRC_TypeDef;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* Watch counter registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t WCRD;
+    stc_wc_wcrd_field_t WCRD_f;
+  };
+  union {
+    __IO  uint8_t WCRL;
+    stc_wc_wcrl_field_t WCRL_f;
+  };
+  union {
+    __IO  uint8_t WCCR;
+    stc_wc_wccr_field_t WCCR_f;
+  };
+        uint8_t RESERVED0[13];
+  union {
+    __IO uint16_t CLK_SEL;
+    stc_wc_clk_sel_field_t CLK_SEL_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t CLK_EN;
+    stc_wc_clk_en_field_t CLK_EN_f;
+  };
+}FM3_WC_TypeDef;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* External bus interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MODE0;
+    stc_exbus_mode0_field_t MODE0_f;
+  };
+  union {
+    __IO uint32_t MODE1;
+    stc_exbus_mode1_field_t MODE1_f;
+  };
+  union {
+    __IO uint32_t MODE2;
+    stc_exbus_mode2_field_t MODE2_f;
+  };
+  union {
+    __IO uint32_t MODE3;
+    stc_exbus_mode3_field_t MODE3_f;
+  };
+  union {
+    __IO uint32_t MODE4;
+    stc_exbus_mode4_field_t MODE4_f;
+  };
+  union {
+    __IO uint32_t MODE5;
+    stc_exbus_mode5_field_t MODE5_f;
+  };
+  union {
+    __IO uint32_t MODE6;
+    stc_exbus_mode6_field_t MODE6_f;
+  };
+  union {
+    __IO uint32_t MODE7;
+    stc_exbus_mode7_field_t MODE7_f;
+  };
+  union {
+    __IO uint32_t TIM0;
+    stc_exbus_tim0_field_t TIM0_f;
+  };
+  union {
+    __IO uint32_t TIM1;
+    stc_exbus_tim1_field_t TIM1_f;
+  };
+  union {
+    __IO uint32_t TIM2;
+    stc_exbus_tim2_field_t TIM2_f;
+  };
+  union {
+    __IO uint32_t TIM3;
+    stc_exbus_tim3_field_t TIM3_f;
+  };
+  union {
+    __IO uint32_t TIM4;
+    stc_exbus_tim4_field_t TIM4_f;
+  };
+  union {
+    __IO uint32_t TIM5;
+    stc_exbus_tim5_field_t TIM5_f;
+  };
+  union {
+    __IO uint32_t TIM6;
+    stc_exbus_tim6_field_t TIM6_f;
+  };
+  union {
+    __IO uint32_t TIM7;
+    stc_exbus_tim7_field_t TIM7_f;
+  };
+  union {
+    __IO uint32_t AREA0;
+    stc_exbus_area0_field_t AREA0_f;
+  };
+  union {
+    __IO uint32_t AREA1;
+    stc_exbus_area1_field_t AREA1_f;
+  };
+  union {
+    __IO uint32_t AREA2;
+    stc_exbus_area2_field_t AREA2_f;
+  };
+  union {
+    __IO uint32_t AREA3;
+    stc_exbus_area3_field_t AREA3_f;
+  };
+  union {
+    __IO uint32_t AREA4;
+    stc_exbus_area4_field_t AREA4_f;
+  };
+  union {
+    __IO uint32_t AREA5;
+    stc_exbus_area5_field_t AREA5_f;
+  };
+  union {
+    __IO uint32_t AREA6;
+    stc_exbus_area6_field_t AREA6_f;
+  };
+  union {
+    __IO uint32_t AREA7;
+    stc_exbus_area7_field_t AREA7_f;
+  };
+  union {
+    __IO uint16_t ATIM0;
+    stc_exbus_atim0_field_t ATIM0_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO uint16_t ATIM1;
+    stc_exbus_atim1_field_t ATIM1_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t ATIM2;
+    stc_exbus_atim2_field_t ATIM2_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t ATIM3;
+    stc_exbus_atim3_field_t ATIM3_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t ATIM4;
+    stc_exbus_atim4_field_t ATIM4_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t ATIM5;
+    stc_exbus_atim5_field_t ATIM5_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t ATIM6;
+    stc_exbus_atim6_field_t ATIM6_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t ATIM7;
+    stc_exbus_atim7_field_t ATIM7_f;
+  };
+        uint8_t RESERVED7[642];
+  union {
+    __IO  uint8_t DCLKR;
+    stc_exbus_dclkr_field_t DCLKR_f;
+  };
+}FM3_EXBUS_TypeDef;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB channel 0 registers */
+typedef struct
+{
+  union {
+    union {
+      __IO uint16_t HCNT;
+      stc_usb_hcnt_field_t HCNT_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HCNT0;
+        stc_usb_hcnt0_field_t HCNT0_f;
+      };
+      union {
+        __IO  uint8_t HCNT1;
+        stc_usb_hcnt1_field_t HCNT1_f;
+      };
+    };
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t HIRQ;
+    stc_usb_hirq_field_t HIRQ_f;
+  };
+  union {
+    __IO  uint8_t HERR;
+    stc_usb_herr_field_t HERR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t HSTATE;
+    stc_usb_hstate_field_t HSTATE_f;
+  };
+  union {
+    __IO  uint8_t HFCOMP;
+    stc_usb_hfcomp_field_t HFCOMP_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t HRTIMER;
+      stc_usb_hrtimer_field_t HRTIMER_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HRTIMER0;
+        stc_usb_hrtimer0_field_t HRTIMER0_f;
+      };
+      union {
+        __IO  uint8_t HRTIMER1;
+        stc_usb_hrtimer1_field_t HRTIMER1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t HRTIMER2;
+    stc_usb_hrtimer2_field_t HRTIMER2_f;
+  };
+  union {
+    __IO  uint8_t HADR;
+    stc_usb_hadr_field_t HADR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t HEOF;
+      stc_usb_heof_field_t HEOF_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HEOF0;
+        stc_usb_heof0_field_t HEOF0_f;
+      };
+      union {
+        __IO  uint8_t HEOF1;
+        stc_usb_heof1_field_t HEOF1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t HFRAME;
+      stc_usb_hframe_field_t HFRAME_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HFRAME0;
+        stc_usb_hframe0_field_t HFRAME0_f;
+      };
+      union {
+        __IO  uint8_t HFRAME1;
+        stc_usb_hframe1_field_t HFRAME1_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t HTOKEN;
+    stc_usb_htoken_field_t HTOKEN_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t UDCC;
+    stc_usb_udcc_field_t UDCC_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t EP0C;
+    stc_usb_ep0c_field_t EP0C_f;
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO uint16_t EP1C;
+    stc_usb_ep1c_field_t EP1C_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t EP2C;
+    stc_usb_ep2c_field_t EP2C_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t EP3C;
+    stc_usb_ep3c_field_t EP3C_f;
+  };
+        uint8_t RESERVED12[2];
+  union {
+    __IO uint16_t EP4C;
+    stc_usb_ep4c_field_t EP4C_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO uint16_t EP5C;
+    stc_usb_ep5c_field_t EP5C_f;
+  };
+        uint8_t RESERVED14[2];
+  union {
+    __IO uint16_t TMSP;
+    stc_usb_tmsp_field_t TMSP_f;
+  };
+        uint8_t RESERVED15[2];
+  union {
+    __IO  uint8_t UDCS;
+    stc_usb_udcs_field_t UDCS_f;
+  };
+  union {
+    __IO  uint8_t UDCIE;
+    stc_usb_udcie_field_t UDCIE_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t EP0IS;
+    stc_usb_ep0is_field_t EP0IS_f;
+  };
+        uint8_t RESERVED17[2];
+  union {
+    __IO uint16_t EP0OS;
+    stc_usb_ep0os_field_t EP0OS_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t EP1S;
+    stc_usb_ep1s_field_t EP1S_f;
+  };
+        uint8_t RESERVED19[2];
+  union {
+    __IO uint16_t EP2S;
+    stc_usb_ep2s_field_t EP2S_f;
+  };
+        uint8_t RESERVED20[2];
+  __IO uint16_t EP3S;
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t EP4S;
+    stc_usb_ep4s_field_t EP4S_f;
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t EP5S;
+    stc_usb_ep5s_field_t EP5S_f;
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t EP0DT;
+    struct {
+      __IO  uint8_t EP0DTL;
+      __IO  uint8_t EP0DTH;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t EP1DT;
+    struct {
+      __IO  uint8_t EP1DTL;
+      __IO  uint8_t EP1DTH;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO uint16_t EP2DT;
+    struct {
+      __IO  uint8_t EP2DTL;
+      __IO  uint8_t EP2DTH;
+    };
+  };
+        uint8_t RESERVED26[2];
+  union {
+    __IO uint16_t EP3DT;
+    struct {
+      __IO  uint8_t EP3DTL;
+      __IO  uint8_t EP3DTH;
+    };
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO uint16_t EP4DT;
+    struct {
+      __IO  uint8_t EP4DTL;
+      __IO  uint8_t EP4DTH;
+    };
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t EP5DT;
+    struct {
+      __IO  uint8_t EP5DTL;
+      __IO  uint8_t EP5DTH;
+    };
+  };
+}FM3_USB_TypeDef;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMA controller */
+typedef struct
+{
+  union {
+    __IO uint32_t DMACR;
+    stc_dmac_dmacr_field_t DMACR_f;
+  };
+        uint8_t RESERVED0[12];
+  union {
+    __IO uint32_t DMACA0;
+    stc_dmac_dmaca0_field_t DMACA0_f;
+  };
+  union {
+    __IO uint32_t DMACB0;
+    stc_dmac_dmacb0_field_t DMACB0_f;
+  };
+  __IO uint32_t DMACSA0;
+  __IO uint32_t DMACDA0;
+  union {
+    __IO uint32_t DMACA1;
+    stc_dmac_dmaca1_field_t DMACA1_f;
+  };
+  union {
+    __IO uint32_t DMACB1;
+    stc_dmac_dmacb1_field_t DMACB1_f;
+  };
+  __IO uint32_t DMACSA1;
+  __IO uint32_t DMACDA1;
+  union {
+    __IO uint32_t DMACA2;
+    stc_dmac_dmaca2_field_t DMACA2_f;
+  };
+  union {
+    __IO uint32_t DMACB2;
+    stc_dmac_dmacb2_field_t DMACB2_f;
+  };
+  __IO uint32_t DMACSA2;
+  __IO uint32_t DMACDA2;
+  union {
+    __IO uint32_t DMACA3;
+    stc_dmac_dmaca3_field_t DMACA3_f;
+  };
+  union {
+    __IO uint32_t DMACB3;
+    stc_dmac_dmacb3_field_t DMACB3_f;
+  };
+  __IO uint32_t DMACSA3;
+  __IO uint32_t DMACDA3;
+  union {
+    __IO uint32_t DMACA4;
+    stc_dmac_dmaca4_field_t DMACA4_f;
+  };
+  union {
+    __IO uint32_t DMACB4;
+    stc_dmac_dmacb4_field_t DMACB4_f;
+  };
+  __IO uint32_t DMACSA4;
+  __IO uint32_t DMACDA4;
+  union {
+    __IO uint32_t DMACA5;
+    stc_dmac_dmaca5_field_t DMACA5_f;
+  };
+  union {
+    __IO uint32_t DMACB5;
+    stc_dmac_dmacb5_field_t DMACB5_f;
+  };
+  __IO uint32_t DMACSA5;
+  __IO uint32_t DMACDA5;
+  union {
+    __IO uint32_t DMACA6;
+    stc_dmac_dmaca6_field_t DMACA6_f;
+  };
+  union {
+    __IO uint32_t DMACB6;
+    stc_dmac_dmacb6_field_t DMACB6_f;
+  };
+  __IO uint32_t DMACSA6;
+  __IO uint32_t DMACDA6;
+  union {
+    __IO uint32_t DMACA7;
+    stc_dmac_dmaca7_field_t DMACA7_f;
+  };
+  union {
+    __IO uint32_t DMACB7;
+    stc_dmac_dmacb7_field_t DMACB7_f;
+  };
+  __IO uint32_t DMACSA7;
+  __IO uint32_t DMACDA7;
+}FM3_DMAC_TypeDef;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET-MAC registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MCR;
+    stc_ethernet_mac_mcr_field_t MCR_f;
+  };
+  union {
+    __IO uint32_t MFFR;
+    stc_ethernet_mac_mffr_field_t MFFR_f;
+  };
+  union {
+    __IO uint32_t MHTRH;
+    stc_ethernet_mac_mhtrh_field_t MHTRH_f;
+  };
+  union {
+    __IO uint32_t MHTRL;
+    stc_ethernet_mac_mhtrl_field_t MHTRL_f;
+  };
+  union {
+    __IO uint32_t GAR;
+    stc_ethernet_mac_gar_field_t GAR_f;
+  };
+  union {
+    __IO uint32_t GDR;
+    stc_ethernet_mac_gdr_field_t GDR_f;
+  };
+  union {
+    __IO uint32_t FCR;
+    stc_ethernet_mac_fcr_field_t FCR_f;
+  };
+  union {
+    __IO uint32_t VTR;
+    stc_ethernet_mac_vtr_field_t VTR_f;
+  };
+        uint8_t RESERVED0[8];
+  union {
+    __IO uint32_t RWFFR;
+    stc_ethernet_mac_rwffr_field_t RWFFR_f;
+  };
+  union {
+    __IO uint32_t PMTR;
+    stc_ethernet_mac_pmtr_field_t PMTR_f;
+  };
+  union {
+    __IO uint32_t LPICSR;
+    stc_ethernet_mac_lpicsr_field_t LPICSR_f;
+  };
+  union {
+    __IO uint32_t LPITCR;
+    stc_ethernet_mac_lpitcr_field_t LPITCR_f;
+  };
+  union {
+    __IO uint32_t ISR;
+    stc_ethernet_mac_isr_field_t ISR_f;
+  };
+  union {
+    __IO uint32_t IMR;
+    stc_ethernet_mac_imr_field_t IMR_f;
+  };
+  union {
+    __IO uint32_t MAR0H;
+    stc_ethernet_mac_mar0h_field_t MAR0H_f;
+  };
+  union {
+    __IO uint32_t MAR0L;
+    stc_ethernet_mac_mar0l_field_t MAR0L_f;
+  };
+  union {
+    __IO uint32_t MAR1H;
+    stc_ethernet_mac_mar1h_field_t MAR1H_f;
+  };
+  union {
+    __IO uint32_t MAR1L;
+    stc_ethernet_mac_mar1l_field_t MAR1L_f;
+  };
+  union {
+    __IO uint32_t MAR2H;
+    stc_ethernet_mac_mar2h_field_t MAR2H_f;
+  };
+  union {
+    __IO uint32_t MAR2L;
+    stc_ethernet_mac_mar2l_field_t MAR2L_f;
+  };
+  union {
+    __IO uint32_t MAR3H;
+    stc_ethernet_mac_mar3h_field_t MAR3H_f;
+  };
+  union {
+    __IO uint32_t MAR3L;
+    stc_ethernet_mac_mar3l_field_t MAR3L_f;
+  };
+  union {
+    __IO uint32_t MAR4H;
+    stc_ethernet_mac_mar4h_field_t MAR4H_f;
+  };
+  union {
+    __IO uint32_t MAR4L;
+    stc_ethernet_mac_mar4l_field_t MAR4L_f;
+  };
+  union {
+    __IO uint32_t MAR5H;
+    stc_ethernet_mac_mar5h_field_t MAR5H_f;
+  };
+  union {
+    __IO uint32_t MAR5L;
+    stc_ethernet_mac_mar5l_field_t MAR5L_f;
+  };
+  union {
+    __IO uint32_t MAR6H;
+    stc_ethernet_mac_mar6h_field_t MAR6H_f;
+  };
+  union {
+    __IO uint32_t MAR6L;
+    stc_ethernet_mac_mar6l_field_t MAR6L_f;
+  };
+  union {
+    __IO uint32_t MAR7H;
+    stc_ethernet_mac_mar7h_field_t MAR7H_f;
+  };
+  union {
+    __IO uint32_t MAR7L;
+    stc_ethernet_mac_mar7l_field_t MAR7L_f;
+  };
+  union {
+    __IO uint32_t MAR8H;
+    stc_ethernet_mac_mar8h_field_t MAR8H_f;
+  };
+  union {
+    __IO uint32_t MAR8L;
+    stc_ethernet_mac_mar8l_field_t MAR8L_f;
+  };
+  union {
+    __IO uint32_t MAR9H;
+    stc_ethernet_mac_mar9h_field_t MAR9H_f;
+  };
+  union {
+    __IO uint32_t MAR9L;
+    stc_ethernet_mac_mar9l_field_t MAR9L_f;
+  };
+  union {
+    __IO uint32_t MAR10H;
+    stc_ethernet_mac_mar10h_field_t MAR10H_f;
+  };
+  union {
+    __IO uint32_t MAR10L;
+    stc_ethernet_mac_mar10l_field_t MAR10L_f;
+  };
+  union {
+    __IO uint32_t MAR11H;
+    stc_ethernet_mac_mar11h_field_t MAR11H_f;
+  };
+  union {
+    __IO uint32_t MAR11L;
+    stc_ethernet_mac_mar11l_field_t MAR11L_f;
+  };
+  union {
+    __IO uint32_t MAR12H;
+    stc_ethernet_mac_mar12h_field_t MAR12H_f;
+  };
+  union {
+    __IO uint32_t MAR12L;
+    stc_ethernet_mac_mar12l_field_t MAR12L_f;
+  };
+  union {
+    __IO uint32_t MAR13H;
+    stc_ethernet_mac_mar13h_field_t MAR13H_f;
+  };
+  union {
+    __IO uint32_t MAR13L;
+    stc_ethernet_mac_mar13l_field_t MAR13L_f;
+  };
+  union {
+    __IO uint32_t MAR14H;
+    stc_ethernet_mac_mar14h_field_t MAR14H_f;
+  };
+  union {
+    __IO uint32_t MAR14L;
+    stc_ethernet_mac_mar14l_field_t MAR14L_f;
+  };
+  union {
+    __IO uint32_t MAR15H;
+    stc_ethernet_mac_mar15h_field_t MAR15H_f;
+  };
+  union {
+    __IO uint32_t MAR15L;
+    stc_ethernet_mac_mar15l_field_t MAR15L_f;
+  };
+        uint8_t RESERVED1[24];
+  union {
+    __IO uint32_t RGSR;
+    stc_ethernet_mac_rgsr_field_t RGSR_f;
+  };
+        uint8_t RESERVED2[36];
+  __IO uint32_t mmc_cntl;
+  __IO uint32_t mmc_intr_rx;
+  __IO uint32_t mmc_intr_tx;
+  __IO uint32_t mmc_intr_mask_rx;
+  __IO uint32_t mmc_intr_mask_tx;
+  __IO uint32_t txoctetcount_gb;
+  __IO uint32_t txframecount_gb;
+  __IO uint32_t txbroadcastframes_g;
+  __IO uint32_t txmulticastframes_g;
+  __IO uint32_t tx64octets_gb;
+  __IO uint32_t tx65to127octets_gb;
+  __IO uint32_t tx128to255octets_gb;
+  __IO uint32_t tx256to511octets_gb;
+  __IO uint32_t tx512to1023octets_gb;
+  __IO uint32_t tx1024tomaxoctets_gb;
+  __IO uint32_t txunicastframes_gb;
+  __IO uint32_t txmulticastframes_gb;
+  __IO uint32_t txbroadcastframes_gb;
+  __IO uint32_t txunderflowerror;
+  __IO uint32_t txsinglecol_g;
+  __IO uint32_t txmulticol_g;
+  __IO uint32_t txdeferred;
+  __IO uint32_t txlatecol;
+  __IO uint32_t txexesscol;
+  __IO uint32_t txcarriererror;
+  __IO uint32_t txoctetcount_g;
+  __IO uint32_t txframecount_g;
+  __IO uint32_t txexecessdef_g;
+  __IO uint32_t txpauseframes;
+  __IO uint32_t txvlanframes_g;
+        uint8_t RESERVED3[8];
+  __IO uint32_t rxframecount_gb;
+  __IO uint32_t rxoctetcount_gb;
+  __IO uint32_t rxoctetcount_g;
+  __IO uint32_t rxbroadcastframes_g;
+  __IO uint32_t rxmulticastframes_g;
+  __IO uint32_t rxcrcerror;
+  __IO uint32_t rxallignmenterror;
+  __IO uint32_t rxrunterror;
+  __IO uint32_t rxjabbererror;
+  __IO uint32_t rxundersize_g;
+  __IO uint32_t rxoversize_g;
+  __IO uint32_t rx64octets_gb;
+  __IO uint32_t rx65to127octets_gb;
+  __IO uint32_t rx128to255octets_gb;
+  __IO uint32_t rx256to511octets_gb;
+  __IO uint32_t rx512to1023octets_gb;
+  __IO uint32_t rx1024tomaxoctets_gb;
+  __IO uint32_t rxunicastframes_g;
+  __IO uint32_t rxlengtherror;
+  __IO uint32_t rxoutofrangetype;
+  __IO uint32_t rxpauseframes;
+  __IO uint32_t rxfifooverflow;
+  __IO uint32_t rxvlanframes_gb;
+  __IO uint32_t rxwatchdogerror;
+        uint8_t RESERVED4[32];
+  __IO uint32_t mmc_ipc_intr_mask_rx;
+        uint8_t RESERVED5[4];
+  __IO uint32_t mmc_ipc_intr_rx;
+        uint8_t RESERVED6[4];
+  __IO uint32_t rxipv4_gd_frms;
+  __IO uint32_t rxipv4_hdrerr_frms;
+  __IO uint32_t rxipv4_nopay_frms;
+  __IO uint32_t rxipv4_frag_frms;
+  __IO uint32_t rxipv4_udsbl_frms;
+  __IO uint32_t rxipv6_gd_frms;
+  __IO uint32_t rxipv6_hdrerr_frms;
+  __IO uint32_t rxipv6_nopay_frms;
+  __IO uint32_t rxudp_gd_frms;
+  __IO uint32_t rxudp_err_frms;
+  __IO uint32_t rxtcp_gd_frms;
+  __IO uint32_t rxtcp_err_frms;
+  __IO uint32_t rxicmp_gd_frms;
+  __IO uint32_t rxicmp_err_frms;
+        uint8_t RESERVED7[8];
+  __IO uint32_t rxipv4_gd_octets;
+  __IO uint32_t rxipv4_hdrerr_octets;
+  __IO uint32_t rxipv4_nopay_octets;
+  __IO uint32_t rxipv4_frag_octets;
+  __IO uint32_t rxipv4_udsbl_octets;
+  __IO uint32_t rxipv6_gd_octets;
+  __IO uint32_t rxipv6_hdrerr_octets;
+  __IO uint32_t rxipv6_nopay_octets;
+  __IO uint32_t rxudp_gd_octets;
+  __IO uint32_t rxudp_err_octets;
+  __IO uint32_t rxtcp_gd_octets;
+  __IO uint32_t rxtcp_err_octets;
+  __IO uint32_t rxicmp_gd_octets;
+  __IO uint32_t rxicmp_err_octets;
+        uint8_t RESERVED8[1144];
+  union {
+    __IO uint32_t TSCR;
+    stc_ethernet_mac_tscr_field_t TSCR_f;
+  };
+  union {
+    __IO uint32_t SSIR;
+    stc_ethernet_mac_ssir_field_t SSIR_f;
+  };
+  union {
+    __IO uint32_t STSR;
+    stc_ethernet_mac_stsr_field_t STSR_f;
+  };
+  union {
+    __IO uint32_t STNR;
+    stc_ethernet_mac_stnr_field_t STNR_f;
+  };
+  union {
+    __IO uint32_t STSUR;
+    stc_ethernet_mac_stsur_field_t STSUR_f;
+  };
+  union {
+    __IO uint32_t STNUR;
+    stc_ethernet_mac_stnur_field_t STNUR_f;
+  };
+  union {
+    __IO uint32_t TSAR;
+    stc_ethernet_mac_tsar_field_t TSAR_f;
+  };
+  union {
+    __IO uint32_t TTSR;
+    stc_ethernet_mac_ttsr_field_t TTSR_f;
+  };
+  union {
+    __IO uint32_t TTNR;
+    stc_ethernet_mac_ttnr_field_t TTNR_f;
+  };
+  union {
+    __IO uint32_t STHWSR;
+    stc_ethernet_mac_sthwsr_field_t STHWSR_f;
+  };
+  union {
+    __IO uint32_t TSR;
+    stc_ethernet_mac_tsr_field_t TSR_f;
+  };
+  union {
+    __IO uint32_t PPSCR;
+    stc_ethernet_mac_ppscr_field_t PPSCR_f;
+  };
+  union {
+    __IO uint32_t ATNR;
+    stc_ethernet_mac_atnr_field_t ATNR_f;
+  };
+  union {
+    __IO uint32_t ATSR;
+    stc_ethernet_mac_atsr_field_t ATSR_f;
+  };
+        uint8_t RESERVED9[200];
+  union {
+    __IO uint32_t MAR16H;
+    stc_ethernet_mac_mar16h_field_t MAR16H_f;
+  };
+  union {
+    __IO uint32_t MAR16L;
+    stc_ethernet_mac_mar16l_field_t MAR16L_f;
+  };
+  union {
+    __IO uint32_t MAR17H;
+    stc_ethernet_mac_mar17h_field_t MAR17H_f;
+  };
+  union {
+    __IO uint32_t MAR17L;
+    stc_ethernet_mac_mar17l_field_t MAR17L_f;
+  };
+  union {
+    __IO uint32_t MAR18H;
+    stc_ethernet_mac_mar18h_field_t MAR18H_f;
+  };
+  union {
+    __IO uint32_t MAR18L;
+    stc_ethernet_mac_mar18l_field_t MAR18L_f;
+  };
+  union {
+    __IO uint32_t MAR19H;
+    stc_ethernet_mac_mar19h_field_t MAR19H_f;
+  };
+  union {
+    __IO uint32_t MAR19L;
+    stc_ethernet_mac_mar19l_field_t MAR19L_f;
+  };
+  union {
+    __IO uint32_t MAR20H;
+    stc_ethernet_mac_mar20h_field_t MAR20H_f;
+  };
+  union {
+    __IO uint32_t MAR20L;
+    stc_ethernet_mac_mar20l_field_t MAR20L_f;
+  };
+  union {
+    __IO uint32_t MAR21H;
+    stc_ethernet_mac_mar21h_field_t MAR21H_f;
+  };
+  union {
+    __IO uint32_t MAR21L;
+    stc_ethernet_mac_mar21l_field_t MAR21L_f;
+  };
+  union {
+    __IO uint32_t MAR22H;
+    stc_ethernet_mac_mar22h_field_t MAR22H_f;
+  };
+  union {
+    __IO uint32_t MAR22L;
+    stc_ethernet_mac_mar22l_field_t MAR22L_f;
+  };
+  union {
+    __IO uint32_t MAR23H;
+    stc_ethernet_mac_mar23h_field_t MAR23H_f;
+  };
+  union {
+    __IO uint32_t MAR23L;
+    stc_ethernet_mac_mar23l_field_t MAR23L_f;
+  };
+  union {
+    __IO uint32_t MAR24H;
+    stc_ethernet_mac_mar24h_field_t MAR24H_f;
+  };
+  union {
+    __IO uint32_t MAR24L;
+    stc_ethernet_mac_mar24l_field_t MAR24L_f;
+  };
+  union {
+    __IO uint32_t MAR25H;
+    stc_ethernet_mac_mar25h_field_t MAR25H_f;
+  };
+  union {
+    __IO uint32_t MAR25L;
+    stc_ethernet_mac_mar25l_field_t MAR25L_f;
+  };
+  union {
+    __IO uint32_t MAR26H;
+    stc_ethernet_mac_mar26h_field_t MAR26H_f;
+  };
+  union {
+    __IO uint32_t MAR26L;
+    stc_ethernet_mac_mar26l_field_t MAR26L_f;
+  };
+  union {
+    __IO uint32_t MAR27H;
+    stc_ethernet_mac_mar27h_field_t MAR27H_f;
+  };
+  union {
+    __IO uint32_t MAR27L;
+    stc_ethernet_mac_mar27l_field_t MAR27L_f;
+  };
+  union {
+    __IO uint32_t MAR28H;
+    stc_ethernet_mac_mar28h_field_t MAR28H_f;
+  };
+  union {
+    __IO uint32_t MAR28L;
+    stc_ethernet_mac_mar28l_field_t MAR28L_f;
+  };
+  union {
+    __IO uint32_t MAR29H;
+    stc_ethernet_mac_mar29h_field_t MAR29H_f;
+  };
+  union {
+    __IO uint32_t MAR29L;
+    stc_ethernet_mac_mar29l_field_t MAR29L_f;
+  };
+  union {
+    __IO uint32_t MAR30H;
+    stc_ethernet_mac_mar30h_field_t MAR30H_f;
+  };
+  union {
+    __IO uint32_t MAR30L;
+    stc_ethernet_mac_mar30l_field_t MAR30L_f;
+  };
+  union {
+    __IO uint32_t MAR31H;
+    stc_ethernet_mac_mar31h_field_t MAR31H_f;
+  };
+  union {
+    __IO uint32_t MAR31L;
+    stc_ethernet_mac_mar31l_field_t MAR31L_f;
+  };
+        uint8_t RESERVED10[1920];
+  union {
+    __IO uint32_t BMR;
+    stc_ethernet_mac_bmr_field_t BMR_f;
+  };
+  union {
+    __IO uint32_t TPDR;
+    stc_ethernet_mac_tpdr_field_t TPDR_f;
+  };
+  union {
+    __IO uint32_t RPDR;
+    stc_ethernet_mac_rpdr_field_t RPDR_f;
+  };
+  union {
+    __IO uint32_t RDLAR;
+    stc_ethernet_mac_rdlar_field_t RDLAR_f;
+  };
+  union {
+    __IO uint32_t TDLAR;
+    stc_ethernet_mac_tdlar_field_t TDLAR_f;
+  };
+  union {
+    __IO uint32_t SR;
+    stc_ethernet_mac_sr_field_t SR_f;
+  };
+  union {
+    __IO uint32_t OMR;
+    stc_ethernet_mac_omr_field_t OMR_f;
+  };
+  union {
+    __IO uint32_t IER;
+    stc_ethernet_mac_ier_field_t IER_f;
+  };
+  union {
+    __IO uint32_t MFBOCR;
+    stc_ethernet_mac_mfbocr_field_t MFBOCR_f;
+  };
+  union {
+    __IO uint32_t RIWTR;
+    stc_ethernet_mac_riwtr_field_t RIWTR_f;
+  };
+        uint8_t RESERVED11[4];
+  union {
+    __IO uint32_t AHBSR;
+    stc_ethernet_mac_ahbsr_field_t AHBSR_f;
+  };
+        uint8_t RESERVED12[24];
+  union {
+    __IO uint32_t CHTDR;
+    stc_ethernet_mac_chtdr_field_t CHTDR_f;
+  };
+  union {
+    __IO uint32_t CHRDR;
+    stc_ethernet_mac_chrdr_field_t CHRDR_f;
+  };
+  union {
+    __IO uint32_t CHTBAR;
+    stc_ethernet_mac_chtbar_field_t CHTBAR_f;
+  };
+  union {
+    __IO uint32_t CHRBAR;
+    stc_ethernet_mac_chrbar_field_t CHRBAR_f;
+  };
+}FM3_ETHERNET_MAC_TypeDef;
+
+/* ETHERNET-CONTROL registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ETH_MODE;
+    stc_ethernet_control_eth_mode_field_t ETH_MODE_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t ETH_CLKG;
+    stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f;
+  };
+}FM3_ETHERNET_CONTROL_TypeDef;
+
+/******************************************************************************
+ * Peripheral memory map
+ ******************************************************************************/
+#define FM3_FLASH_BASE        (0x00000000UL)                 /* Flash Base                             */
+#define FM3_PERIPH_BASE       (0x40000000UL)                 /* Peripheral  Base                       */
+#define FM3_CM3_BASE          (0xE0100000UL)                 /* CM3 Private                            */
+
+#define FM3_FLASH_IF_BASE     (FM3_PERIPH_BASE + 0x00000UL)  /* Flash interface registers              */
+#define FM3_CRG_BASE          (FM3_PERIPH_BASE + 0x10000UL)  /* Clock and reset registers              */
+#define FM3_HWWDT_BASE        (FM3_PERIPH_BASE + 0x11000UL)  /* Hardware watchdog registers            */
+#define FM3_SWWDT_BASE        (FM3_PERIPH_BASE + 0x12000UL)  /* Software watchdog registers            */
+#define FM3_DTIM_BASE         (FM3_PERIPH_BASE + 0x15000UL)  /* Dual timer 1/2 registers               */
+#define FM3_MFT0_FRT_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Free Running Timer registers */
+#define FM3_MFT0_OCU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Output Compare Unit registers */
+#define FM3_MFT0_WFG_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT0_ICU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Input Capture Unit registers */
+#define FM3_MFT0_ADCMP_BASE   (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define FM3_MFT1_FRT_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Free Running Timer registers */
+#define FM3_MFT1_OCU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Output Compare Unit registers */
+#define FM3_MFT1_WFG_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT1_ICU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Input Capture Unit registers */
+#define FM3_MFT1_ADCMP_BASE   (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define FM3_MFT2_FRT_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Free Running Timer registers */
+#define FM3_MFT2_OCU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Output Compare Unit registers */
+#define FM3_MFT2_WFG_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT2_ICU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Input Capture Unit registers */
+#define FM3_MFT2_ADCMP_BASE   (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define FM3_MFT_PPG_BASE      (FM3_PERIPH_BASE + 0x24000UL)  /* Multifunction Timer PPG registers      */
+#define FM3_BT0_PPG_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PPG registers             */
+#define FM3_BT0_PWM_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWM registers             */
+#define FM3_BT0_RT_BASE       (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 RT registers              */
+#define FM3_BT0_PWC_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWC registers             */
+#define FM3_BT1_PPG_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PPG registers             */
+#define FM3_BT1_PWM_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWM registers             */
+#define FM3_BT1_RT_BASE       (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 RT registers              */
+#define FM3_BT1_PWC_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWC registers             */
+#define FM3_BT2_PPG_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PPG registers             */
+#define FM3_BT2_PWM_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWM registers             */
+#define FM3_BT2_RT_BASE       (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 RT registers              */
+#define FM3_BT2_PWC_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWC registers             */
+#define FM3_BT3_PPG_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PPG registers             */
+#define FM3_BT3_PWM_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWM registers             */
+#define FM3_BT3_RT_BASE       (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 RT registers              */
+#define FM3_BT3_PWC_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWC registers             */
+#define FM3_BT4_PPG_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PPG registers             */
+#define FM3_BT4_PWM_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWM registers             */
+#define FM3_BT4_RT_BASE       (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 RT registers              */
+#define FM3_BT4_PWC_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWC registers             */
+#define FM3_BT5_PPG_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PPG registers             */
+#define FM3_BT5_PWM_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWM registers             */
+#define FM3_BT5_RT_BASE       (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 RT registers              */
+#define FM3_BT5_PWC_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWC registers             */
+#define FM3_BT6_PPG_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PPG registers             */
+#define FM3_BT6_PWM_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWM registers             */
+#define FM3_BT6_RT_BASE       (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 RT registers              */
+#define FM3_BT6_PWC_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWC registers             */
+#define FM3_BT7_PPG_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PPG registers             */
+#define FM3_BT7_PWM_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWM registers             */
+#define FM3_BT7_RT_BASE       (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 RT registers              */
+#define FM3_BT7_PWC_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWC registers             */
+#define FM3_BTIOSEL03_BASE    (FM3_PERIPH_BASE + 0x25100UL)  /* Base Timer I/O selector channel 0 - channel 3 registers */
+#define FM3_BTIOSEL47_BASE    (FM3_PERIPH_BASE + 0x25300UL)  /* Base Timer I/O selector channel 4 - channel 7 registers */
+#define FM3_BT8_PPG_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT8_PWM_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT8_RT_BASE       (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT8_PWC_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT9_PPG_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT9_PWM_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT9_RT_BASE       (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT9_PWC_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT10_PPG_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT10_PWM_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT10_RT_BASE      (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT10_PWC_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT11_PPG_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT11_PWM_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT11_RT_BASE      (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT11_PWC_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BT12_PPG_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT12_PWM_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT12_RT_BASE      (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT12_PWC_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT13_PPG_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT13_PWM_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT13_RT_BASE      (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT13_PWC_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT14_PPG_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT14_PWM_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT14_RT_BASE      (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT14_PWC_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT15_PPG_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT15_PWM_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT15_RT_BASE      (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT15_PWC_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BTIOSEL8B_BASE    (FM3_PERIPH_BASE + 0x25500UL)  /* Base Timer I/O selector channel 8 - channel 11 registers */
+#define FM3_BTIOSELCF_BASE    (FM3_PERIPH_BASE + 0x25700UL)  /* Base Timer I/O selector channel 12 - channel 15 registers */
+#define FM3_SBSSR_BASE        (FM3_PERIPH_BASE + 0x25FFCUL)  /* Software based Simulation Startup (Base Timer) register */
+#define FM3_QPRC0_BASE        (FM3_PERIPH_BASE + 0x26000UL)  /* Quad position and revolution counter channel 0 registers */
+#define FM3_QPRC1_BASE        (FM3_PERIPH_BASE + 0x26040UL)  /* Quad position and revolution counter channel 1 registers */
+#define FM3_QPRC2_BASE        (FM3_PERIPH_BASE + 0x26080UL)  /* Quad position and revolution counter channel 2 registers */
+#define FM3_ADC0_BASE         (FM3_PERIPH_BASE + 0x27000UL)  /* 12-bit ADC unit 0 registers            */
+#define FM3_ADC1_BASE         (FM3_PERIPH_BASE + 0x27100UL)  /* 12-bit ADC unit 1 registers            */
+#define FM3_ADC2_BASE         (FM3_PERIPH_BASE + 0x27200UL)  /* 12-bit ADC unit 2 registers            */
+#define FM3_CRTRIM_BASE       (FM3_PERIPH_BASE + 0x2E000UL)  /* CR trimming registers                  */
+#define FM3_EXTI_BASE         (FM3_PERIPH_BASE + 0x30000UL)  /* External interrupt registers           */
+#define FM3_INTREQ_BASE       (FM3_PERIPH_BASE + 0x31000UL)  /* Interrupt request read registers       */
+#define FM3_GPIO_BASE         (FM3_PERIPH_BASE + 0x33000UL)  /* General purpose I/O registers          */
+#define FM3_LVD_BASE          (FM3_PERIPH_BASE + 0x35000UL)  /* Low voltage detection registers        */
+#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL)  /* USB clock registers                    */
+#define FM3_MFS0_UART_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART asynchronous channel 0 registers  */
+#define FM3_MFS0_CSIO_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART synchronous channel 0 registers   */
+#define FM3_MFS0_LIN_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* UART LIN channel 0 registers           */
+#define FM3_MFS0_I2C_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* I2C channel 0 registers                */
+#define FM3_MFS1_UART_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART asynchronous channel 1 registers  */
+#define FM3_MFS1_CSIO_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART synchronous channel 1 registers   */
+#define FM3_MFS1_LIN_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* UART LIN channel 1 registers           */
+#define FM3_MFS1_I2C_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* I2C channel 1 registers                */
+#define FM3_MFS2_UART_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART asynchronous channel 2 registers  */
+#define FM3_MFS2_CSIO_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART synchronous channel 2 registers   */
+#define FM3_MFS2_LIN_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* UART LIN channel 2 registers           */
+#define FM3_MFS2_I2C_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* I2C channel 2 registers                */
+#define FM3_MFS3_UART_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART asynchronous channel 3 registers  */
+#define FM3_MFS3_CSIO_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART synchronous channel 3 registers   */
+#define FM3_MFS3_LIN_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* UART LIN channel 3 registers           */
+#define FM3_MFS3_I2C_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* I2C channel 3 registers                */
+#define FM3_MFS4_UART_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART asynchronous channel 4 registers  */
+#define FM3_MFS4_CSIO_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART synchronous channel 4 registers   */
+#define FM3_MFS4_LIN_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* UART LIN channel 4 registers           */
+#define FM3_MFS4_I2C_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* I2C channel 4 registers                */
+#define FM3_MFS5_UART_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART asynchronous channel 5 registers  */
+#define FM3_MFS5_CSIO_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART synchronous channel 5 registers   */
+#define FM3_MFS5_LIN_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* UART LIN channel 5 registers           */
+#define FM3_MFS5_I2C_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* I2C channel 5 registers                */
+#define FM3_MFS6_UART_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART asynchronous channel 6 registers  */
+#define FM3_MFS6_CSIO_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART synchronous channel 6 registers   */
+#define FM3_MFS6_LIN_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* UART LIN channel 6 registers           */
+#define FM3_MFS6_I2C_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* I2C channel 6 registers                */
+#define FM3_MFS7_UART_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART asynchronous channel 7 registers  */
+#define FM3_MFS7_CSIO_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART synchronous channel 7 registers   */
+#define FM3_MFS7_LIN_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* UART LIN channel 7 registers           */
+#define FM3_MFS7_I2C_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* I2C channel 7 registers                */
+#define FM3_MFS_NFC_BASE      (FM3_PERIPH_BASE + 0x38800UL)  /* MFS Noise Filter Control register      */
+#define FM3_CRC_BASE          (FM3_PERIPH_BASE + 0x39000UL)  /* CRC registers                          */
+#define FM3_WC_BASE           (FM3_PERIPH_BASE + 0x3A000UL)  /* Watch counter registers                */
+#define FM3_EXBUS_BASE        (FM3_PERIPH_BASE + 0x3F000UL)  /* External bus interface registers       */
+#define FM3_USB0_BASE         (FM3_PERIPH_BASE + 0x42100UL)  /* USB channel 0 registers                */
+#define FM3_USB1_BASE         (FM3_PERIPH_BASE + 0x52100UL)  /* USB channel 1 registers                */
+#define FM3_DMAC_BASE         (FM3_PERIPH_BASE + 0x60000UL)  /* DMA controller                         */
+#define FM3_ETHERNET_MAC0_BASE    (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers            */
+#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers      */
+#define FM3_ETHERNET_MAC1_BASE    (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers            */
+
+/******************************************************************************
+ * Peripheral declaration
+ ******************************************************************************/
+#define FM3_FLASH_IF    ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)
+#define FM3_CRG         ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
+#define FM3_HWWDT       ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
+#define FM3_SWWDT       ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
+#define FM3_DTIM        ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)
+#define FM3_MFT0_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)
+#define FM3_MFT0_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)
+#define FM3_MFT0_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)
+#define FM3_MFT0_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)
+#define FM3_MFT0_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)
+#define FM3_MFT1_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)
+#define FM3_MFT1_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)
+#define FM3_MFT1_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)
+#define FM3_MFT1_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)
+#define FM3_MFT1_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)
+#define FM3_MFT2_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE)
+#define FM3_MFT2_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE)
+#define FM3_MFT2_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE)
+#define FM3_MFT2_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE)
+#define FM3_MFT2_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE)
+#define FM3_MFT_PPG     ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)
+#define FM3_BT0_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)
+#define FM3_BT0_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)
+#define FM3_BT0_RT      ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)
+#define FM3_BT0_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)
+#define FM3_BT1_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)
+#define FM3_BT1_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)
+#define FM3_BT1_RT      ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)
+#define FM3_BT1_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)
+#define FM3_BT2_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)
+#define FM3_BT2_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)
+#define FM3_BT2_RT      ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)
+#define FM3_BT2_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)
+#define FM3_BT3_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)
+#define FM3_BT3_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)
+#define FM3_BT3_RT      ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)
+#define FM3_BT3_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)
+#define FM3_BT4_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)
+#define FM3_BT4_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)
+#define FM3_BT4_RT      ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)
+#define FM3_BT4_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)
+#define FM3_BT5_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)
+#define FM3_BT5_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)
+#define FM3_BT5_RT      ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)
+#define FM3_BT5_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)
+#define FM3_BT6_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)
+#define FM3_BT6_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)
+#define FM3_BT6_RT      ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)
+#define FM3_BT6_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)
+#define FM3_BT7_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)
+#define FM3_BT7_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)
+#define FM3_BT7_RT      ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)
+#define FM3_BT7_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)
+#define FM3_BTIOSEL03   ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)
+#define FM3_BTIOSEL47   ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)
+#define FM3_BT8_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE)
+#define FM3_BT8_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE)
+#define FM3_BT8_RT      ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE)
+#define FM3_BT8_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE)
+#define FM3_BT9_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE)
+#define FM3_BT9_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE)
+#define FM3_BT9_RT      ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE)
+#define FM3_BT9_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE)
+#define FM3_BT10_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE)
+#define FM3_BT10_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE)
+#define FM3_BT10_RT     ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE)
+#define FM3_BT10_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE)
+#define FM3_BT11_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE)
+#define FM3_BT11_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE)
+#define FM3_BT11_RT     ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE)
+#define FM3_BT11_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE)
+#define FM3_BT12_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE)
+#define FM3_BT12_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE)
+#define FM3_BT12_RT     ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE)
+#define FM3_BT12_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE)
+#define FM3_BT13_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE)
+#define FM3_BT13_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE)
+#define FM3_BT13_RT     ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE)
+#define FM3_BT13_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE)
+#define FM3_BT14_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE)
+#define FM3_BT14_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE)
+#define FM3_BT14_RT     ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE)
+#define FM3_BT14_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE)
+#define FM3_BT15_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE)
+#define FM3_BT15_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE)
+#define FM3_BT15_RT     ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE)
+#define FM3_BT15_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE)
+#define FM3_BTIOSEL8B   ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE)
+#define FM3_BTIOSELCF   ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE)
+#define FM3_SBSSR       ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)
+#define FM3_QPRC0       ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)
+#define FM3_QPRC1       ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)
+#define FM3_QPRC2       ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE)
+#define FM3_ADC0        ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)
+#define FM3_ADC1        ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)
+#define FM3_ADC2        ((FM3_ADC_TypeDef *)FM3_ADC2_BASE)
+#define FM3_CRTRIM      ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)
+#define FM3_EXTI        ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)
+#define FM3_INTREQ      ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)
+#define FM3_GPIO        ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)
+#define FM3_LVD         ((FM3_LVD_TypeDef *)FM3_LVD_BASE)
+#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE)
+#define FM3_MFS0_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)
+#define FM3_MFS0_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)
+#define FM3_MFS0_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)
+#define FM3_MFS0_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)
+#define FM3_MFS1_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)
+#define FM3_MFS1_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)
+#define FM3_MFS1_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)
+#define FM3_MFS1_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)
+#define FM3_MFS2_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)
+#define FM3_MFS2_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)
+#define FM3_MFS2_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)
+#define FM3_MFS2_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)
+#define FM3_MFS3_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)
+#define FM3_MFS3_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)
+#define FM3_MFS3_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)
+#define FM3_MFS3_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)
+#define FM3_MFS4_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)
+#define FM3_MFS4_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)
+#define FM3_MFS4_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)
+#define FM3_MFS4_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)
+#define FM3_MFS5_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)
+#define FM3_MFS5_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)
+#define FM3_MFS5_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)
+#define FM3_MFS5_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)
+#define FM3_MFS6_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)
+#define FM3_MFS6_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)
+#define FM3_MFS6_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)
+#define FM3_MFS6_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)
+#define FM3_MFS7_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)
+#define FM3_MFS7_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)
+#define FM3_MFS7_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)
+#define FM3_MFS7_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)
+#define FM3_MFS_NFC     ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE)
+#define FM3_CRC         ((FM3_CRC_TypeDef *)FM3_CRC_BASE)
+#define FM3_WC          ((FM3_WC_TypeDef *)FM3_WC_BASE)
+#define FM3_EXBUS       ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE)
+#define FM3_USB0        ((FM3_USB_TypeDef *)FM3_USB0_BASE)
+#define FM3_USB1        ((FM3_USB_TypeDef *)FM3_USB1_BASE)
+#define FM3_DMAC        ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)
+#define FM3_ETHERNET_MAC0    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE)
+#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_SET_TypeDef *)FM3_ETHERNET_SET_BASE)
+#define FM3_ETHERNET_MAC1    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE)
+
+/******************************************************************************
+ * Peripheral Bit Band Alias declaration
+ ******************************************************************************/
+
+/* Flash interface registers */
+#define bFM3_FLASH_IF_FASZR_ASZ0               *((volatile unsigned int*)(0x42000000UL))
+#define bFM3_FLASH_IF_FASZR_ASZ1               *((volatile unsigned int*)(0x42000004UL))
+#define bFM3_FLASH_IF_FRWTR_RWT0               *((volatile unsigned int*)(0x42000080UL))
+#define bFM3_FLASH_IF_FRWTR_RWT1               *((volatile unsigned int*)(0x42000084UL))
+#define bFM3_FLASH_IF_FSTR_RDY                 *((volatile unsigned int*)(0x42000100UL))
+#define bFM3_FLASH_IF_FSTR_HNG                 *((volatile unsigned int*)(0x42000104UL))
+#define bFM3_FLASH_IF_FSTR_EER                 *((volatile unsigned int*)(0x42000108UL))
+#define bFM3_FLASH_IF_FSYNDN_SD0               *((volatile unsigned int*)(0x42000200UL))
+#define bFM3_FLASH_IF_FSYNDN_SD1               *((volatile unsigned int*)(0x42000204UL))
+#define bFM3_FLASH_IF_FSYNDN_SD2               *((volatile unsigned int*)(0x42000208UL))
+#define bFM3_FLASH_IF_FBFCR_BE                 *((volatile unsigned int*)(0x42000280UL))
+#define bFM3_FLASH_IF_FBFCR_BS                 *((volatile unsigned int*)(0x42000284UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM0             *((volatile unsigned int*)(0x42002000UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM1             *((volatile unsigned int*)(0x42002004UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM2             *((volatile unsigned int*)(0x42002008UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM3             *((volatile unsigned int*)(0x4200200CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM4             *((volatile unsigned int*)(0x42002010UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM5             *((volatile unsigned int*)(0x42002014UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM6             *((volatile unsigned int*)(0x42002018UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM7             *((volatile unsigned int*)(0x4200201CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM8             *((volatile unsigned int*)(0x42002020UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM9             *((volatile unsigned int*)(0x42002024UL))
+
+/* Clock and reset registers */
+#define bFM3_CRG_SCM_CTL_MOSCE                 *((volatile unsigned int*)(0x42200004UL))
+#define bFM3_CRG_SCM_CTL_SOSCE                 *((volatile unsigned int*)(0x4220000CUL))
+#define bFM3_CRG_SCM_CTL_PLLE                  *((volatile unsigned int*)(0x42200010UL))
+#define bFM3_CRG_SCM_CTL_RCS0                  *((volatile unsigned int*)(0x42200014UL))
+#define bFM3_CRG_SCM_CTL_RCS1                  *((volatile unsigned int*)(0x42200018UL))
+#define bFM3_CRG_SCM_CTL_RCS2                  *((volatile unsigned int*)(0x4220001CUL))
+#define bFM3_CRG_SCM_STR_MORDY                 *((volatile unsigned int*)(0x42200084UL))
+#define bFM3_CRG_SCM_STR_SORDY                 *((volatile unsigned int*)(0x4220008CUL))
+#define bFM3_CRG_SCM_STR_PLRDY                 *((volatile unsigned int*)(0x42200090UL))
+#define bFM3_CRG_SCM_STR_RCM0                  *((volatile unsigned int*)(0x42200094UL))
+#define bFM3_CRG_SCM_STR_RCM1                  *((volatile unsigned int*)(0x42200098UL))
+#define bFM3_CRG_SCM_STR_RCM2                  *((volatile unsigned int*)(0x4220009CUL))
+#define bFM3_CRG_RST_STR_PONR                  *((volatile unsigned int*)(0x42200180UL))
+#define bFM3_CRG_RST_STR_INITX                 *((volatile unsigned int*)(0x42200184UL))
+#define bFM3_CRG_RST_STR_SWDT                  *((volatile unsigned int*)(0x42200190UL))
+#define bFM3_CRG_RST_STR_HWDT                  *((volatile unsigned int*)(0x42200194UL))
+#define bFM3_CRG_RST_STR_CSVR                  *((volatile unsigned int*)(0x42200198UL))
+#define bFM3_CRG_RST_STR_FCSR                  *((volatile unsigned int*)(0x4220019CUL))
+#define bFM3_CRG_RST_STR_SRST                  *((volatile unsigned int*)(0x422001A0UL))
+#define bFM3_CRG_BSC_PSR_BSR0                  *((volatile unsigned int*)(0x42200200UL))
+#define bFM3_CRG_BSC_PSR_BSR1                  *((volatile unsigned int*)(0x42200204UL))
+#define bFM3_CRG_BSC_PSR_BSR2                  *((volatile unsigned int*)(0x42200208UL))
+#define bFM3_CRG_APBC0_PSR_APBC00              *((volatile unsigned int*)(0x42200280UL))
+#define bFM3_CRG_APBC0_PSR_APBC01              *((volatile unsigned int*)(0x42200284UL))
+#define bFM3_CRG_APBC1_PSR_APBC10              *((volatile unsigned int*)(0x42200300UL))
+#define bFM3_CRG_APBC1_PSR_APBC11              *((volatile unsigned int*)(0x42200304UL))
+#define bFM3_CRG_APBC1_PSR_APBC1RST            *((volatile unsigned int*)(0x42200310UL))
+#define bFM3_CRG_APBC1_PSR_APBC1EN             *((volatile unsigned int*)(0x4220031CUL))
+#define bFM3_CRG_APBC2_PSR_APBC20              *((volatile unsigned int*)(0x42200380UL))
+#define bFM3_CRG_APBC2_PSR_APBC21              *((volatile unsigned int*)(0x42200384UL))
+#define bFM3_CRG_APBC2_PSR_APBC2RST            *((volatile unsigned int*)(0x42200390UL))
+#define bFM3_CRG_APBC2_PSR_APBC2EN             *((volatile unsigned int*)(0x4220039CUL))
+#define bFM3_CRG_SWC_PSR_SWDS0                 *((volatile unsigned int*)(0x42200400UL))
+#define bFM3_CRG_SWC_PSR_SWDS1                 *((volatile unsigned int*)(0x42200404UL))
+#define bFM3_CRG_SWC_PSR_TESTB                 *((volatile unsigned int*)(0x4220041CUL))
+#define bFM3_CRG_TTC_PSR_TTC0                  *((volatile unsigned int*)(0x42200500UL))
+#define bFM3_CRG_TTC_PSR_TTC1                  *((volatile unsigned int*)(0x42200504UL))
+#define bFM3_CRG_CSW_TMR_MOWT0                 *((volatile unsigned int*)(0x42200600UL))
+#define bFM3_CRG_CSW_TMR_MOWT1                 *((volatile unsigned int*)(0x42200604UL))
+#define bFM3_CRG_CSW_TMR_MOWT2                 *((volatile unsigned int*)(0x42200608UL))
+#define bFM3_CRG_CSW_TMR_MOWT3                 *((volatile unsigned int*)(0x4220060CUL))
+#define bFM3_CRG_CSW_TMR_SOWT0                 *((volatile unsigned int*)(0x42200610UL))
+#define bFM3_CRG_CSW_TMR_SOWT1                 *((volatile unsigned int*)(0x42200614UL))
+#define bFM3_CRG_CSW_TMR_SOWT2                 *((volatile unsigned int*)(0x42200618UL))
+#define bFM3_CRG_PSW_TMR_POWT0                 *((volatile unsigned int*)(0x42200680UL))
+#define bFM3_CRG_PSW_TMR_POWT1                 *((volatile unsigned int*)(0x42200684UL))
+#define bFM3_CRG_PSW_TMR_POWT2                 *((volatile unsigned int*)(0x42200688UL))
+#define bFM3_CRG_PSW_TMR_PINC                  *((volatile unsigned int*)(0x42200690UL))
+#define bFM3_CRG_PLL_CTL1_PLLM0                *((volatile unsigned int*)(0x42200700UL))
+#define bFM3_CRG_PLL_CTL1_PLLM1                *((volatile unsigned int*)(0x42200704UL))
+#define bFM3_CRG_PLL_CTL1_PLLM2                *((volatile unsigned int*)(0x42200708UL))
+#define bFM3_CRG_PLL_CTL1_PLLM3                *((volatile unsigned int*)(0x4220070CUL))
+#define bFM3_CRG_PLL_CTL1_PLLK0                *((volatile unsigned int*)(0x42200710UL))
+#define bFM3_CRG_PLL_CTL1_PLLK1                *((volatile unsigned int*)(0x42200714UL))
+#define bFM3_CRG_PLL_CTL1_PLLK2                *((volatile unsigned int*)(0x42200718UL))
+#define bFM3_CRG_PLL_CTL1_PLLK3                *((volatile unsigned int*)(0x4220071CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN0                *((volatile unsigned int*)(0x42200780UL))
+#define bFM3_CRG_PLL_CTL2_PLLN1                *((volatile unsigned int*)(0x42200784UL))
+#define bFM3_CRG_PLL_CTL2_PLLN2                *((volatile unsigned int*)(0x42200788UL))
+#define bFM3_CRG_PLL_CTL2_PLLN3                *((volatile unsigned int*)(0x4220078CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN4                *((volatile unsigned int*)(0x42200790UL))
+#define bFM3_CRG_PLL_CTL2_PLLN5                *((volatile unsigned int*)(0x42200794UL))
+#define bFM3_CRG_CSV_CTL_MCSVE                 *((volatile unsigned int*)(0x42200800UL))
+#define bFM3_CRG_CSV_CTL_SCSVE                 *((volatile unsigned int*)(0x42200804UL))
+#define bFM3_CRG_CSV_CTL_FCSDE                 *((volatile unsigned int*)(0x42200820UL))
+#define bFM3_CRG_CSV_CTL_FCSRE                 *((volatile unsigned int*)(0x42200824UL))
+#define bFM3_CRG_CSV_CTL_FCD0                  *((volatile unsigned int*)(0x42200830UL))
+#define bFM3_CRG_CSV_CTL_FCD1                  *((volatile unsigned int*)(0x42200834UL))
+#define bFM3_CRG_CSV_CTL_FCD2                  *((volatile unsigned int*)(0x42200838UL))
+#define bFM3_CRG_CSV_STR_MCMF                  *((volatile unsigned int*)(0x42200880UL))
+#define bFM3_CRG_CSV_STR_SCMF                  *((volatile unsigned int*)(0x42200884UL))
+#define bFM3_CRG_DBWDT_CTL_DPSWBE              *((volatile unsigned int*)(0x42200A94UL))
+#define bFM3_CRG_DBWDT_CTL_DPHWBE              *((volatile unsigned int*)(0x42200A9CUL))
+#define bFM3_CRG_INT_ENR_MCSE                  *((volatile unsigned int*)(0x42200C00UL))
+#define bFM3_CRG_INT_ENR_SCSE                  *((volatile unsigned int*)(0x42200C04UL))
+#define bFM3_CRG_INT_ENR_PCSE                  *((volatile unsigned int*)(0x42200C08UL))
+#define bFM3_CRG_INT_ENR_FCSE                  *((volatile unsigned int*)(0x42200C14UL))
+#define bFM3_CRG_INT_STR_MCSI                  *((volatile unsigned int*)(0x42200C80UL))
+#define bFM3_CRG_INT_STR_SCSI                  *((volatile unsigned int*)(0x42200C84UL))
+#define bFM3_CRG_INT_STR_PCSI                  *((volatile unsigned int*)(0x42200C88UL))
+#define bFM3_CRG_INT_STR_FCSI                  *((volatile unsigned int*)(0x42200C94UL))
+#define bFM3_CRG_INT_CLR_MCSC                  *((volatile unsigned int*)(0x42200D00UL))
+#define bFM3_CRG_INT_CLR_SCSC                  *((volatile unsigned int*)(0x42200D04UL))
+#define bFM3_CRG_INT_CLR_PCSC                  *((volatile unsigned int*)(0x42200D08UL))
+#define bFM3_CRG_INT_CLR_FCSC                  *((volatile unsigned int*)(0x42200D14UL))
+
+/* Hardware watchdog registers */
+#define bFM3_HWWDT_WDG_CTL_INTEN               *((volatile unsigned int*)(0x42220100UL))
+#define bFM3_HWWDT_WDG_CTL_RESEN               *((volatile unsigned int*)(0x42220104UL))
+#define bFM3_HWWDT_WDG_RIS_RIS                 *((volatile unsigned int*)(0x42220200UL))
+
+/* Software watchdog registers */
+#define bFM3_SWWDT_WDOGCONTROL_INTEN           *((volatile unsigned int*)(0x42240100UL))
+#define bFM3_SWWDT_WDOGCONTROL_RESEN           *((volatile unsigned int*)(0x42240104UL))
+#define bFM3_SWWDT_WDOGRIS_RIS                 *((volatile unsigned int*)(0x42240200UL))
+
+/* Dual timer 1/2 registers */
+#define bFM3_DTIM_TIMER1CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0100UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0104UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0108UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A010CUL))
+#define bFM3_DTIM_TIMER1CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0114UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0118UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A011CUL))
+#define bFM3_DTIM_TIMER1RIS_TIMER1RIS          *((volatile unsigned int*)(0x422A0200UL))
+#define bFM3_DTIM_TIMER1MIS_TIMER1MIS          *((volatile unsigned int*)(0x422A0280UL))
+#define bFM3_DTIM_TIMER2CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0500UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0504UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0508UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A050CUL))
+#define bFM3_DTIM_TIMER2CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0514UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0518UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A051CUL))
+#define bFM3_DTIM_TIMER2RIS_TIMER2RIS          *((volatile unsigned int*)(0x422A0600UL))
+#define bFM3_DTIM_TIMER2MIS_TIMER2MIS          *((volatile unsigned int*)(0x422A0680UL))
+
+/* Multifunction Timer unit 0 Free Running Timer registers */
+#define bFM3_MFT0_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42400600UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42400604UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42400608UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4240060CUL))
+#define bFM3_MFT0_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42400610UL))
+#define bFM3_MFT0_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42400614UL))
+#define bFM3_MFT0_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42400618UL))
+#define bFM3_MFT0_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4240061CUL))
+#define bFM3_MFT0_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42400620UL))
+#define bFM3_MFT0_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42400624UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42400634UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42400638UL))
+#define bFM3_MFT0_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4240063CUL))
+#define bFM3_MFT0_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42400680UL))
+#define bFM3_MFT0_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42400684UL))
+#define bFM3_MFT0_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42400688UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42400800UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42400804UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42400808UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4240080CUL))
+#define bFM3_MFT0_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42400810UL))
+#define bFM3_MFT0_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42400814UL))
+#define bFM3_MFT0_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42400818UL))
+#define bFM3_MFT0_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4240081CUL))
+#define bFM3_MFT0_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42400820UL))
+#define bFM3_MFT0_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42400824UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42400834UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42400838UL))
+#define bFM3_MFT0_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4240083CUL))
+#define bFM3_MFT0_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42400880UL))
+#define bFM3_MFT0_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42400884UL))
+#define bFM3_MFT0_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42400888UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42400A00UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42400A04UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42400A08UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42400A0CUL))
+#define bFM3_MFT0_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42400A10UL))
+#define bFM3_MFT0_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42400A14UL))
+#define bFM3_MFT0_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42400A18UL))
+#define bFM3_MFT0_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42400A1CUL))
+#define bFM3_MFT0_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42400A20UL))
+#define bFM3_MFT0_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42400A24UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42400A34UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42400A38UL))
+#define bFM3_MFT0_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42400A3CUL))
+#define bFM3_MFT0_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42400A80UL))
+#define bFM3_MFT0_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42400A84UL))
+#define bFM3_MFT0_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42400A88UL))
+
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+#define bFM3_MFT0_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42400300UL))
+#define bFM3_MFT0_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42400304UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42400308UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4240030CUL))
+#define bFM3_MFT0_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42400310UL))
+#define bFM3_MFT0_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42400314UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42400318UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4240031CUL))
+#define bFM3_MFT0_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42400320UL))
+#define bFM3_MFT0_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42400324UL))
+#define bFM3_MFT0_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42400330UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42400334UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42400338UL))
+#define bFM3_MFT0_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42400380UL))
+#define bFM3_MFT0_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42400384UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42400388UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4240038CUL))
+#define bFM3_MFT0_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42400390UL))
+#define bFM3_MFT0_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42400394UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42400398UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4240039CUL))
+#define bFM3_MFT0_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424003A0UL))
+#define bFM3_MFT0_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424003A4UL))
+#define bFM3_MFT0_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424003B0UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424003B4UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424003B8UL))
+#define bFM3_MFT0_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42400400UL))
+#define bFM3_MFT0_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42400404UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42400408UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4240040CUL))
+#define bFM3_MFT0_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42400410UL))
+#define bFM3_MFT0_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42400414UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42400418UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4240041CUL))
+#define bFM3_MFT0_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42400420UL))
+#define bFM3_MFT0_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42400424UL))
+#define bFM3_MFT0_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42400430UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42400434UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42400438UL))
+#define bFM3_MFT0_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424004A0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424004A4UL))
+#define bFM3_MFT0_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424004A8UL))
+#define bFM3_MFT0_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424004ACUL))
+#define bFM3_MFT0_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424004B0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424004B4UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42400B00UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42400B04UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42400B08UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42400B0CUL))
+#define bFM3_MFT0_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42400B10UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42400B14UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42400B18UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42400B1CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42400B20UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42400B24UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42400B28UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42400B2CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42400B30UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42400B34UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42400B38UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42400B3CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42400B80UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42400B84UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42400B88UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42400B8CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42400B90UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42400B94UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42400B98UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42400B9CUL))
+
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT0_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42401180UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42401184UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42401188UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42401198UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4240119CUL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424011A0UL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424011A4UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424011A8UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424011ACUL))
+#define bFM3_MFT0_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424011B0UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42401200UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42401204UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42401208UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42401218UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4240121CUL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42401220UL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42401224UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42401228UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4240122CUL))
+#define bFM3_MFT0_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42401230UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42401280UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42401284UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42401288UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42401298UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4240129CUL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424012A0UL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424012A4UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424012A8UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424012ACUL))
+#define bFM3_MFT0_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424012B0UL))
+#define bFM3_MFT0_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42401300UL))
+#define bFM3_MFT0_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42401304UL))
+#define bFM3_MFT0_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42401310UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42401314UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42401318UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4240131CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42401320UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42401324UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42401328UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4240132CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42401330UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42401334UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42401338UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4240133CUL))
+#define bFM3_MFT0_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42401380UL))
+#define bFM3_MFT0_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42401384UL))
+#define bFM3_MFT0_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42401388UL))
+#define bFM3_MFT0_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4240138CUL))
+#define bFM3_MFT0_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42401390UL))
+
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+#define bFM3_MFT0_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42400C00UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42400C04UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42400C08UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42400C0CUL))
+#define bFM3_MFT0_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42400C10UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42400C14UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42400C18UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42400C1CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42400C20UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42400C24UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42400C28UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42400C2CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42400C30UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42400C34UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42400C38UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42400C3CUL))
+#define bFM3_MFT0_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42400F00UL))
+#define bFM3_MFT0_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42400F04UL))
+#define bFM3_MFT0_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42400F08UL))
+#define bFM3_MFT0_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42400F0CUL))
+#define bFM3_MFT0_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42400F10UL))
+#define bFM3_MFT0_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42400F14UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42400F18UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42400F1CUL))
+#define bFM3_MFT0_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42400F20UL))
+#define bFM3_MFT0_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42400F24UL))
+#define bFM3_MFT0_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42400F80UL))
+#define bFM3_MFT0_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42400F84UL))
+#define bFM3_MFT0_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42400F88UL))
+#define bFM3_MFT0_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42400F8CUL))
+#define bFM3_MFT0_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42400F90UL))
+#define bFM3_MFT0_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42400F94UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42400F98UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42400F9CUL))
+#define bFM3_MFT0_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42400FA0UL))
+#define bFM3_MFT0_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42400FA4UL))
+
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define bFM3_MFT0_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42401700UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42401704UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42401708UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42401710UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42401714UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42401718UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42401780UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42401784UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42401788UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4240178CUL))
+#define bFM3_MFT0_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42401790UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42401794UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424017A0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424017A4UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424017A8UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424017ACUL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424017B0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424017B4UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42401800UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42401804UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42401808UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4240180CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42401810UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42401814UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42401820UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42401824UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42401828UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4240182CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42401830UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42401834UL))
+
+/* Multifunction Timer unit 1 Free Running Timer registers */
+#define bFM3_MFT1_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42420600UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42420604UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42420608UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4242060CUL))
+#define bFM3_MFT1_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42420610UL))
+#define bFM3_MFT1_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42420614UL))
+#define bFM3_MFT1_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42420618UL))
+#define bFM3_MFT1_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4242061CUL))
+#define bFM3_MFT1_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42420620UL))
+#define bFM3_MFT1_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42420624UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42420634UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42420638UL))
+#define bFM3_MFT1_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4242063CUL))
+#define bFM3_MFT1_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42420680UL))
+#define bFM3_MFT1_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42420684UL))
+#define bFM3_MFT1_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42420688UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42420800UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42420804UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42420808UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4242080CUL))
+#define bFM3_MFT1_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42420810UL))
+#define bFM3_MFT1_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42420814UL))
+#define bFM3_MFT1_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42420818UL))
+#define bFM3_MFT1_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4242081CUL))
+#define bFM3_MFT1_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42420820UL))
+#define bFM3_MFT1_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42420824UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42420834UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42420838UL))
+#define bFM3_MFT1_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4242083CUL))
+#define bFM3_MFT1_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42420880UL))
+#define bFM3_MFT1_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42420884UL))
+#define bFM3_MFT1_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42420888UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42420A00UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42420A04UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42420A08UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42420A0CUL))
+#define bFM3_MFT1_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42420A10UL))
+#define bFM3_MFT1_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42420A14UL))
+#define bFM3_MFT1_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42420A18UL))
+#define bFM3_MFT1_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42420A1CUL))
+#define bFM3_MFT1_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42420A20UL))
+#define bFM3_MFT1_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42420A24UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42420A34UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42420A38UL))
+#define bFM3_MFT1_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42420A3CUL))
+#define bFM3_MFT1_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42420A80UL))
+#define bFM3_MFT1_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42420A84UL))
+#define bFM3_MFT1_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42420A88UL))
+
+/* Multifunction Timer unit 1 Output Compare Unit registers */
+#define bFM3_MFT1_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42420300UL))
+#define bFM3_MFT1_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42420304UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42420308UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4242030CUL))
+#define bFM3_MFT1_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42420310UL))
+#define bFM3_MFT1_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42420314UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42420318UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4242031CUL))
+#define bFM3_MFT1_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42420320UL))
+#define bFM3_MFT1_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42420324UL))
+#define bFM3_MFT1_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42420330UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42420334UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42420338UL))
+#define bFM3_MFT1_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42420380UL))
+#define bFM3_MFT1_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42420384UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42420388UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4242038CUL))
+#define bFM3_MFT1_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42420390UL))
+#define bFM3_MFT1_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42420394UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42420398UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4242039CUL))
+#define bFM3_MFT1_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424203A0UL))
+#define bFM3_MFT1_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424203A4UL))
+#define bFM3_MFT1_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424203B0UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424203B4UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424203B8UL))
+#define bFM3_MFT1_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42420400UL))
+#define bFM3_MFT1_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42420404UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42420408UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4242040CUL))
+#define bFM3_MFT1_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42420410UL))
+#define bFM3_MFT1_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42420414UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42420418UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4242041CUL))
+#define bFM3_MFT1_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42420420UL))
+#define bFM3_MFT1_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42420424UL))
+#define bFM3_MFT1_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42420430UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42420434UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42420438UL))
+#define bFM3_MFT1_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424204A0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424204A4UL))
+#define bFM3_MFT1_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424204A8UL))
+#define bFM3_MFT1_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424204ACUL))
+#define bFM3_MFT1_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424204B0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424204B4UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42420B00UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42420B04UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42420B08UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42420B0CUL))
+#define bFM3_MFT1_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42420B10UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42420B14UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42420B18UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42420B1CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42420B20UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42420B24UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42420B28UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42420B2CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42420B30UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42420B34UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42420B38UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42420B3CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42420B80UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42420B84UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42420B88UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42420B8CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42420B90UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42420B94UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42420B98UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42420B9CUL))
+
+/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT1_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42421180UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42421184UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42421188UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42421198UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4242119CUL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424211A0UL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424211A4UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424211A8UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424211ACUL))
+#define bFM3_MFT1_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424211B0UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42421200UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42421204UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42421208UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42421218UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4242121CUL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42421220UL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42421224UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42421228UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4242122CUL))
+#define bFM3_MFT1_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42421230UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42421280UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42421284UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42421288UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42421298UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4242129CUL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424212A0UL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424212A4UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424212A8UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424212ACUL))
+#define bFM3_MFT1_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424212B0UL))
+#define bFM3_MFT1_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42421300UL))
+#define bFM3_MFT1_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42421304UL))
+#define bFM3_MFT1_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42421310UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42421314UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42421318UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4242131CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42421320UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42421324UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42421328UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4242132CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42421330UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42421334UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42421338UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4242133CUL))
+#define bFM3_MFT1_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42421380UL))
+#define bFM3_MFT1_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42421384UL))
+#define bFM3_MFT1_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42421388UL))
+#define bFM3_MFT1_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4242138CUL))
+#define bFM3_MFT1_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42421390UL))
+
+/* Multifunction Timer unit 1 Input Capture Unit registers */
+#define bFM3_MFT1_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42420C00UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42420C04UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42420C08UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42420C0CUL))
+#define bFM3_MFT1_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42420C10UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42420C14UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42420C18UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42420C1CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42420C20UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42420C24UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42420C28UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42420C2CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42420C30UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42420C34UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42420C38UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42420C3CUL))
+#define bFM3_MFT1_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42420F00UL))
+#define bFM3_MFT1_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42420F04UL))
+#define bFM3_MFT1_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42420F08UL))
+#define bFM3_MFT1_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42420F0CUL))
+#define bFM3_MFT1_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42420F10UL))
+#define bFM3_MFT1_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42420F14UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42420F18UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42420F1CUL))
+#define bFM3_MFT1_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42420F20UL))
+#define bFM3_MFT1_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42420F24UL))
+#define bFM3_MFT1_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42420F80UL))
+#define bFM3_MFT1_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42420F84UL))
+#define bFM3_MFT1_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42420F88UL))
+#define bFM3_MFT1_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42420F8CUL))
+#define bFM3_MFT1_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42420F90UL))
+#define bFM3_MFT1_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42420F94UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42420F98UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42420F9CUL))
+#define bFM3_MFT1_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42420FA0UL))
+#define bFM3_MFT1_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42420FA4UL))
+
+/* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define bFM3_MFT1_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42421700UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42421704UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42421708UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42421710UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42421714UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42421718UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42421780UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42421784UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42421788UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4242178CUL))
+#define bFM3_MFT1_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42421790UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42421794UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424217A0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424217A4UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424217A8UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424217ACUL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424217B0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424217B4UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42421800UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42421804UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42421808UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4242180CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42421810UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42421814UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42421820UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42421824UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42421828UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4242182CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42421830UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42421834UL))
+
+/* Multifunction Timer unit 2 Free Running Timer registers */
+#define bFM3_MFT2_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42440600UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42440604UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42440608UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4244060CUL))
+#define bFM3_MFT2_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42440610UL))
+#define bFM3_MFT2_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42440614UL))
+#define bFM3_MFT2_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42440618UL))
+#define bFM3_MFT2_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4244061CUL))
+#define bFM3_MFT2_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42440620UL))
+#define bFM3_MFT2_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42440624UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42440634UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42440638UL))
+#define bFM3_MFT2_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4244063CUL))
+#define bFM3_MFT2_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42440680UL))
+#define bFM3_MFT2_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42440684UL))
+#define bFM3_MFT2_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42440688UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42440800UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42440804UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42440808UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4244080CUL))
+#define bFM3_MFT2_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42440810UL))
+#define bFM3_MFT2_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42440814UL))
+#define bFM3_MFT2_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42440818UL))
+#define bFM3_MFT2_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4244081CUL))
+#define bFM3_MFT2_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42440820UL))
+#define bFM3_MFT2_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42440824UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42440834UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42440838UL))
+#define bFM3_MFT2_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4244083CUL))
+#define bFM3_MFT2_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42440880UL))
+#define bFM3_MFT2_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42440884UL))
+#define bFM3_MFT2_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42440888UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42440A00UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42440A04UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42440A08UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42440A0CUL))
+#define bFM3_MFT2_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42440A10UL))
+#define bFM3_MFT2_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42440A14UL))
+#define bFM3_MFT2_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42440A18UL))
+#define bFM3_MFT2_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42440A1CUL))
+#define bFM3_MFT2_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42440A20UL))
+#define bFM3_MFT2_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42440A24UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42440A34UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42440A38UL))
+#define bFM3_MFT2_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42440A3CUL))
+#define bFM3_MFT2_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42440A80UL))
+#define bFM3_MFT2_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42440A84UL))
+#define bFM3_MFT2_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42440A88UL))
+
+/* Multifunction Timer unit 2 Output Compare Unit registers */
+#define bFM3_MFT2_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42440300UL))
+#define bFM3_MFT2_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42440304UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42440308UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4244030CUL))
+#define bFM3_MFT2_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42440310UL))
+#define bFM3_MFT2_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42440314UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42440318UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4244031CUL))
+#define bFM3_MFT2_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42440320UL))
+#define bFM3_MFT2_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42440324UL))
+#define bFM3_MFT2_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42440330UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42440334UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42440338UL))
+#define bFM3_MFT2_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42440380UL))
+#define bFM3_MFT2_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42440384UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42440388UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4244038CUL))
+#define bFM3_MFT2_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42440390UL))
+#define bFM3_MFT2_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42440394UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42440398UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4244039CUL))
+#define bFM3_MFT2_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424403A0UL))
+#define bFM3_MFT2_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424403A4UL))
+#define bFM3_MFT2_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424403B0UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424403B4UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424403B8UL))
+#define bFM3_MFT2_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42440400UL))
+#define bFM3_MFT2_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42440404UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42440408UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4244040CUL))
+#define bFM3_MFT2_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42440410UL))
+#define bFM3_MFT2_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42440414UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42440418UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4244041CUL))
+#define bFM3_MFT2_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42440420UL))
+#define bFM3_MFT2_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42440424UL))
+#define bFM3_MFT2_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42440430UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42440434UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42440438UL))
+#define bFM3_MFT2_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424404A0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424404A4UL))
+#define bFM3_MFT2_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424404A8UL))
+#define bFM3_MFT2_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424404ACUL))
+#define bFM3_MFT2_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424404B0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424404B4UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42440B00UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42440B04UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42440B08UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42440B0CUL))
+#define bFM3_MFT2_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42440B10UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42440B14UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42440B18UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42440B1CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42440B20UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42440B24UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42440B28UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42440B2CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42440B30UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42440B34UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42440B38UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42440B3CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42440B80UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42440B84UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42440B88UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42440B8CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42440B90UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42440B94UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42440B98UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42440B9CUL))
+
+/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT2_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42441180UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42441184UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42441188UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42441198UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4244119CUL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424411A0UL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424411A4UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424411A8UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424411ACUL))
+#define bFM3_MFT2_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424411B0UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42441200UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42441204UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42441208UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42441218UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4244121CUL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42441220UL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42441224UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42441228UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4244122CUL))
+#define bFM3_MFT2_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42441230UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42441280UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42441284UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42441288UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42441298UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4244129CUL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424412A0UL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424412A4UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424412A8UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424412ACUL))
+#define bFM3_MFT2_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424412B0UL))
+#define bFM3_MFT2_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42441300UL))
+#define bFM3_MFT2_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42441304UL))
+#define bFM3_MFT2_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42441310UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42441314UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42441318UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4244131CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42441320UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42441324UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42441328UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4244132CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42441330UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42441334UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42441338UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4244133CUL))
+#define bFM3_MFT2_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42441380UL))
+#define bFM3_MFT2_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42441384UL))
+#define bFM3_MFT2_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42441388UL))
+#define bFM3_MFT2_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4244138CUL))
+#define bFM3_MFT2_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42441390UL))
+
+/* Multifunction Timer unit 2 Input Capture Unit registers */
+#define bFM3_MFT2_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42440C00UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42440C04UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42440C08UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42440C0CUL))
+#define bFM3_MFT2_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42440C10UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42440C14UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42440C18UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42440C1CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42440C20UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42440C24UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42440C28UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42440C2CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42440C30UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42440C34UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42440C38UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42440C3CUL))
+#define bFM3_MFT2_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42440F00UL))
+#define bFM3_MFT2_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42440F04UL))
+#define bFM3_MFT2_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42440F08UL))
+#define bFM3_MFT2_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42440F0CUL))
+#define bFM3_MFT2_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42440F10UL))
+#define bFM3_MFT2_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42440F14UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42440F18UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42440F1CUL))
+#define bFM3_MFT2_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42440F20UL))
+#define bFM3_MFT2_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42440F24UL))
+#define bFM3_MFT2_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42440F80UL))
+#define bFM3_MFT2_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42440F84UL))
+#define bFM3_MFT2_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42440F88UL))
+#define bFM3_MFT2_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42440F8CUL))
+#define bFM3_MFT2_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42440F90UL))
+#define bFM3_MFT2_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42440F94UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42440F98UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42440F9CUL))
+#define bFM3_MFT2_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42440FA0UL))
+#define bFM3_MFT2_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42440FA4UL))
+
+/* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define bFM3_MFT2_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42441700UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42441704UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42441708UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42441710UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42441714UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42441718UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42441780UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42441784UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42441788UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4244178CUL))
+#define bFM3_MFT2_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42441790UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42441794UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424417A0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424417A4UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424417A8UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424417ACUL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424417B0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424417B4UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42441800UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42441804UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42441808UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4244180CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42441810UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42441814UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42441820UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42441824UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42441828UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4244182CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42441830UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42441834UL))
+
+/* Multifunction Timer PPG registers */
+#define bFM3_MFT_PPG_TTCR0_STR0                *((volatile unsigned int*)(0x42480020UL))
+#define bFM3_MFT_PPG_TTCR0_MONI0               *((volatile unsigned int*)(0x42480024UL))
+#define bFM3_MFT_PPG_TTCR0_CS00                *((volatile unsigned int*)(0x42480028UL))
+#define bFM3_MFT_PPG_TTCR0_CS01                *((volatile unsigned int*)(0x4248002CUL))
+#define bFM3_MFT_PPG_TTCR0_TRG0O               *((volatile unsigned int*)(0x42480030UL))
+#define bFM3_MFT_PPG_TTCR0_TRG2O               *((volatile unsigned int*)(0x42480034UL))
+#define bFM3_MFT_PPG_TTCR0_TRG4O               *((volatile unsigned int*)(0x42480038UL))
+#define bFM3_MFT_PPG_TTCR0_TRG6O               *((volatile unsigned int*)(0x4248003CUL))
+#define bFM3_MFT_PPG_TTCR1_STR1                *((volatile unsigned int*)(0x42480420UL))
+#define bFM3_MFT_PPG_TTCR1_MONI1               *((volatile unsigned int*)(0x42480424UL))
+#define bFM3_MFT_PPG_TTCR1_CS10                *((volatile unsigned int*)(0x42480428UL))
+#define bFM3_MFT_PPG_TTCR1_CS11                *((volatile unsigned int*)(0x4248042CUL))
+#define bFM3_MFT_PPG_TTCR1_TRG1O               *((volatile unsigned int*)(0x42480430UL))
+#define bFM3_MFT_PPG_TTCR1_TRG3O               *((volatile unsigned int*)(0x42480434UL))
+#define bFM3_MFT_PPG_TTCR1_TRG5O               *((volatile unsigned int*)(0x42480438UL))
+#define bFM3_MFT_PPG_TTCR1_TRG7O               *((volatile unsigned int*)(0x4248043CUL))
+#define bFM3_MFT_PPG_TTCR2_STR2                *((volatile unsigned int*)(0x42480820UL))
+#define bFM3_MFT_PPG_TTCR2_MONI2               *((volatile unsigned int*)(0x42480824UL))
+#define bFM3_MFT_PPG_TTCR2_CS20                *((volatile unsigned int*)(0x42480828UL))
+#define bFM3_MFT_PPG_TTCR2_CS21                *((volatile unsigned int*)(0x4248082CUL))
+#define bFM3_MFT_PPG_TTCR2_TRG16O              *((volatile unsigned int*)(0x42480830UL))
+#define bFM3_MFT_PPG_TTCR2_TRG18O              *((volatile unsigned int*)(0x42480834UL))
+#define bFM3_MFT_PPG_TTCR2_TRG20O              *((volatile unsigned int*)(0x42480838UL))
+#define bFM3_MFT_PPG_TTCR2_TRG22O              *((volatile unsigned int*)(0x4248083CUL))
+#define bFM3_MFT_PPG_TRG_PEN00                 *((volatile unsigned int*)(0x42482000UL))
+#define bFM3_MFT_PPG_TRG_PEN01                 *((volatile unsigned int*)(0x42482004UL))
+#define bFM3_MFT_PPG_TRG_PEN02                 *((volatile unsigned int*)(0x42482008UL))
+#define bFM3_MFT_PPG_TRG_PEN03                 *((volatile unsigned int*)(0x4248200CUL))
+#define bFM3_MFT_PPG_TRG_PEN04                 *((volatile unsigned int*)(0x42482010UL))
+#define bFM3_MFT_PPG_TRG_PEN05                 *((volatile unsigned int*)(0x42482014UL))
+#define bFM3_MFT_PPG_TRG_PEN06                 *((volatile unsigned int*)(0x42482018UL))
+#define bFM3_MFT_PPG_TRG_PEN07                 *((volatile unsigned int*)(0x4248201CUL))
+#define bFM3_MFT_PPG_TRG_PEN08                 *((volatile unsigned int*)(0x42482020UL))
+#define bFM3_MFT_PPG_TRG_PEN09                 *((volatile unsigned int*)(0x42482024UL))
+#define bFM3_MFT_PPG_TRG_PEN10                 *((volatile unsigned int*)(0x42482028UL))
+#define bFM3_MFT_PPG_TRG_PEN11                 *((volatile unsigned int*)(0x4248202CUL))
+#define bFM3_MFT_PPG_TRG_PEN12                 *((volatile unsigned int*)(0x42482030UL))
+#define bFM3_MFT_PPG_TRG_PEN13                 *((volatile unsigned int*)(0x42482034UL))
+#define bFM3_MFT_PPG_TRG_PEN14                 *((volatile unsigned int*)(0x42482038UL))
+#define bFM3_MFT_PPG_TRG_PEN15                 *((volatile unsigned int*)(0x4248203CUL))
+#define bFM3_MFT_PPG_REVC_REV00                *((volatile unsigned int*)(0x42482080UL))
+#define bFM3_MFT_PPG_REVC_REV01                *((volatile unsigned int*)(0x42482084UL))
+#define bFM3_MFT_PPG_REVC_REV02                *((volatile unsigned int*)(0x42482088UL))
+#define bFM3_MFT_PPG_REVC_REV03                *((volatile unsigned int*)(0x4248208CUL))
+#define bFM3_MFT_PPG_REVC_REV04                *((volatile unsigned int*)(0x42482090UL))
+#define bFM3_MFT_PPG_REVC_REV05                *((volatile unsigned int*)(0x42482094UL))
+#define bFM3_MFT_PPG_REVC_REV06                *((volatile unsigned int*)(0x42482098UL))
+#define bFM3_MFT_PPG_REVC_REV07                *((volatile unsigned int*)(0x4248209CUL))
+#define bFM3_MFT_PPG_REVC_REV08                *((volatile unsigned int*)(0x424820A0UL))
+#define bFM3_MFT_PPG_REVC_REV09                *((volatile unsigned int*)(0x424820A4UL))
+#define bFM3_MFT_PPG_REVC_REV10                *((volatile unsigned int*)(0x424820A8UL))
+#define bFM3_MFT_PPG_REVC_REV11                *((volatile unsigned int*)(0x424820ACUL))
+#define bFM3_MFT_PPG_REVC_REV12                *((volatile unsigned int*)(0x424820B0UL))
+#define bFM3_MFT_PPG_REVC_REV13                *((volatile unsigned int*)(0x424820B4UL))
+#define bFM3_MFT_PPG_REVC_REV14                *((volatile unsigned int*)(0x424820B8UL))
+#define bFM3_MFT_PPG_REVC_REV15                *((volatile unsigned int*)(0x424820BCUL))
+#define bFM3_MFT_PPG_TRG1_PEN16                *((volatile unsigned int*)(0x42482800UL))
+#define bFM3_MFT_PPG_TRG1_PEN17                *((volatile unsigned int*)(0x42482804UL))
+#define bFM3_MFT_PPG_TRG1_PEN18                *((volatile unsigned int*)(0x42482808UL))
+#define bFM3_MFT_PPG_TRG1_PEN19                *((volatile unsigned int*)(0x4248280CUL))
+#define bFM3_MFT_PPG_TRG1_PEN20                *((volatile unsigned int*)(0x42482810UL))
+#define bFM3_MFT_PPG_TRG1_PEN21                *((volatile unsigned int*)(0x42482814UL))
+#define bFM3_MFT_PPG_TRG1_PEN22                *((volatile unsigned int*)(0x42482818UL))
+#define bFM3_MFT_PPG_TRG1_PEN23                *((volatile unsigned int*)(0x4248281CUL))
+#define bFM3_MFT_PPG_REVC1_REV16               *((volatile unsigned int*)(0x42482880UL))
+#define bFM3_MFT_PPG_REVC1_REV17               *((volatile unsigned int*)(0x42482884UL))
+#define bFM3_MFT_PPG_REVC1_REV18               *((volatile unsigned int*)(0x42482888UL))
+#define bFM3_MFT_PPG_REVC1_REV19               *((volatile unsigned int*)(0x4248288CUL))
+#define bFM3_MFT_PPG_REVC1_REV20               *((volatile unsigned int*)(0x42482890UL))
+#define bFM3_MFT_PPG_REVC1_REV21               *((volatile unsigned int*)(0x42482894UL))
+#define bFM3_MFT_PPG_REVC1_REV22               *((volatile unsigned int*)(0x42482898UL))
+#define bFM3_MFT_PPG_REVC1_REV23               *((volatile unsigned int*)(0x4248289CUL))
+#define bFM3_MFT_PPG_PPGC1_TTRG                *((volatile unsigned int*)(0x42484000UL))
+#define bFM3_MFT_PPG_PPGC1_PCS0                *((volatile unsigned int*)(0x4248400CUL))
+#define bFM3_MFT_PPG_PPGC1_PCS1                *((volatile unsigned int*)(0x42484010UL))
+#define bFM3_MFT_PPG_PPGC1_INTM                *((volatile unsigned int*)(0x42484014UL))
+#define bFM3_MFT_PPG_PPGC1_PUF                 *((volatile unsigned int*)(0x42484018UL))
+#define bFM3_MFT_PPG_PPGC1_PIE                 *((volatile unsigned int*)(0x4248401CUL))
+#define bFM3_MFT_PPG_PPGC0_TTRG                *((volatile unsigned int*)(0x42484020UL))
+#define bFM3_MFT_PPG_PPGC0_PCS0                *((volatile unsigned int*)(0x4248402CUL))
+#define bFM3_MFT_PPG_PPGC0_PCS1                *((volatile unsigned int*)(0x42484030UL))
+#define bFM3_MFT_PPG_PPGC0_INTM                *((volatile unsigned int*)(0x42484034UL))
+#define bFM3_MFT_PPG_PPGC0_PUF                 *((volatile unsigned int*)(0x42484038UL))
+#define bFM3_MFT_PPG_PPGC0_PIE                 *((volatile unsigned int*)(0x4248403CUL))
+#define bFM3_MFT_PPG_PPGC3_TTRG                *((volatile unsigned int*)(0x42484080UL))
+#define bFM3_MFT_PPG_PPGC3_PCS0                *((volatile unsigned int*)(0x4248408CUL))
+#define bFM3_MFT_PPG_PPGC3_PCS1                *((volatile unsigned int*)(0x42484090UL))
+#define bFM3_MFT_PPG_PPGC3_INTM                *((volatile unsigned int*)(0x42484094UL))
+#define bFM3_MFT_PPG_PPGC3_PUF                 *((volatile unsigned int*)(0x42484098UL))
+#define bFM3_MFT_PPG_PPGC3_PIE                 *((volatile unsigned int*)(0x4248409CUL))
+#define bFM3_MFT_PPG_PPGC2_TTRG                *((volatile unsigned int*)(0x424840A0UL))
+#define bFM3_MFT_PPG_PPGC2_PCS0                *((volatile unsigned int*)(0x424840ACUL))
+#define bFM3_MFT_PPG_PPGC2_PCS1                *((volatile unsigned int*)(0x424840B0UL))
+#define bFM3_MFT_PPG_PPGC2_INTM                *((volatile unsigned int*)(0x424840B4UL))
+#define bFM3_MFT_PPG_PPGC2_PUF                 *((volatile unsigned int*)(0x424840B8UL))
+#define bFM3_MFT_PPG_PPGC2_PIE                 *((volatile unsigned int*)(0x424840BCUL))
+#define bFM3_MFT_PPG_GATEC0_EDGE0              *((volatile unsigned int*)(0x42484300UL))
+#define bFM3_MFT_PPG_GATEC0_STRG0              *((volatile unsigned int*)(0x42484304UL))
+#define bFM3_MFT_PPG_GATEC0_EDGE2              *((volatile unsigned int*)(0x42484310UL))
+#define bFM3_MFT_PPG_GATEC0_STRG2              *((volatile unsigned int*)(0x42484314UL))
+#define bFM3_MFT_PPG_PPGC5_TTRG                *((volatile unsigned int*)(0x42484800UL))
+#define bFM3_MFT_PPG_PPGC5_PCS0                *((volatile unsigned int*)(0x4248480CUL))
+#define bFM3_MFT_PPG_PPGC5_PCS1                *((volatile unsigned int*)(0x42484810UL))
+#define bFM3_MFT_PPG_PPGC5_INTM                *((volatile unsigned int*)(0x42484814UL))
+#define bFM3_MFT_PPG_PPGC5_PUF                 *((volatile unsigned int*)(0x42484818UL))
+#define bFM3_MFT_PPG_PPGC5_PIE                 *((volatile unsigned int*)(0x4248481CUL))
+#define bFM3_MFT_PPG_PPGC4_TTRG                *((volatile unsigned int*)(0x42484820UL))
+#define bFM3_MFT_PPG_PPGC4_PCS0                *((volatile unsigned int*)(0x4248482CUL))
+#define bFM3_MFT_PPG_PPGC4_PCS1                *((volatile unsigned int*)(0x42484830UL))
+#define bFM3_MFT_PPG_PPGC4_INTM                *((volatile unsigned int*)(0x42484834UL))
+#define bFM3_MFT_PPG_PPGC4_PUF                 *((volatile unsigned int*)(0x42484838UL))
+#define bFM3_MFT_PPG_PPGC4_PIE                 *((volatile unsigned int*)(0x4248483CUL))
+#define bFM3_MFT_PPG_PPGC7_TTRG                *((volatile unsigned int*)(0x42484880UL))
+#define bFM3_MFT_PPG_PPGC7_PCS0                *((volatile unsigned int*)(0x4248488CUL))
+#define bFM3_MFT_PPG_PPGC7_PCS1                *((volatile unsigned int*)(0x42484890UL))
+#define bFM3_MFT_PPG_PPGC7_INTM                *((volatile unsigned int*)(0x42484894UL))
+#define bFM3_MFT_PPG_PPGC7_PUF                 *((volatile unsigned int*)(0x42484898UL))
+#define bFM3_MFT_PPG_PPGC7_PIE                 *((volatile unsigned int*)(0x4248489CUL))
+#define bFM3_MFT_PPG_PPGC6_TTRG                *((volatile unsigned int*)(0x424848A0UL))
+#define bFM3_MFT_PPG_PPGC6_PCS0                *((volatile unsigned int*)(0x424848ACUL))
+#define bFM3_MFT_PPG_PPGC6_PCS1                *((volatile unsigned int*)(0x424848B0UL))
+#define bFM3_MFT_PPG_PPGC6_INTM                *((volatile unsigned int*)(0x424848B4UL))
+#define bFM3_MFT_PPG_PPGC6_PUF                 *((volatile unsigned int*)(0x424848B8UL))
+#define bFM3_MFT_PPG_PPGC6_PIE                 *((volatile unsigned int*)(0x424848BCUL))
+#define bFM3_MFT_PPG_GATEC4_EDGE4              *((volatile unsigned int*)(0x42484B00UL))
+#define bFM3_MFT_PPG_GATEC4_STRG4              *((volatile unsigned int*)(0x42484B04UL))
+#define bFM3_MFT_PPG_GATEC4_EDGE6              *((volatile unsigned int*)(0x42484B10UL))
+#define bFM3_MFT_PPG_GATEC4_STRG6              *((volatile unsigned int*)(0x42484B14UL))
+#define bFM3_MFT_PPG_PPGC9_TTRG                *((volatile unsigned int*)(0x42485000UL))
+#define bFM3_MFT_PPG_PPGC9_PCS0                *((volatile unsigned int*)(0x4248500CUL))
+#define bFM3_MFT_PPG_PPGC9_PCS1                *((volatile unsigned int*)(0x42485010UL))
+#define bFM3_MFT_PPG_PPGC9_INTM                *((volatile unsigned int*)(0x42485014UL))
+#define bFM3_MFT_PPG_PPGC9_PUF                 *((volatile unsigned int*)(0x42485018UL))
+#define bFM3_MFT_PPG_PPGC9_PIE                 *((volatile unsigned int*)(0x4248501CUL))
+#define bFM3_MFT_PPG_PPGC8_TTRG                *((volatile unsigned int*)(0x42485020UL))
+#define bFM3_MFT_PPG_PPGC8_PCS0                *((volatile unsigned int*)(0x4248502CUL))
+#define bFM3_MFT_PPG_PPGC8_PCS1                *((volatile unsigned int*)(0x42485030UL))
+#define bFM3_MFT_PPG_PPGC8_INTM                *((volatile unsigned int*)(0x42485034UL))
+#define bFM3_MFT_PPG_PPGC8_PUF                 *((volatile unsigned int*)(0x42485038UL))
+#define bFM3_MFT_PPG_PPGC8_PIE                 *((volatile unsigned int*)(0x4248503CUL))
+#define bFM3_MFT_PPG_PPGC11_TTRG               *((volatile unsigned int*)(0x42485080UL))
+#define bFM3_MFT_PPG_PPGC11_PCS0               *((volatile unsigned int*)(0x4248508CUL))
+#define bFM3_MFT_PPG_PPGC11_PCS1               *((volatile unsigned int*)(0x42485090UL))
+#define bFM3_MFT_PPG_PPGC11_INTM               *((volatile unsigned int*)(0x42485094UL))
+#define bFM3_MFT_PPG_PPGC11_PUF                *((volatile unsigned int*)(0x42485098UL))
+#define bFM3_MFT_PPG_PPGC11_PIE                *((volatile unsigned int*)(0x4248509CUL))
+#define bFM3_MFT_PPG_PPGC10_TTRG               *((volatile unsigned int*)(0x424850A0UL))
+#define bFM3_MFT_PPG_PPGC10_PCS0               *((volatile unsigned int*)(0x424850ACUL))
+#define bFM3_MFT_PPG_PPGC10_PCS1               *((volatile unsigned int*)(0x424850B0UL))
+#define bFM3_MFT_PPG_PPGC10_INTM               *((volatile unsigned int*)(0x424850B4UL))
+#define bFM3_MFT_PPG_PPGC10_PUF                *((volatile unsigned int*)(0x424850B8UL))
+#define bFM3_MFT_PPG_PPGC10_PIE                *((volatile unsigned int*)(0x424850BCUL))
+#define bFM3_MFT_PPG_GATEC8_EDGE8              *((volatile unsigned int*)(0x42485300UL))
+#define bFM3_MFT_PPG_GATEC8_STRG8              *((volatile unsigned int*)(0x42485304UL))
+#define bFM3_MFT_PPG_GATEC8_EDGE10             *((volatile unsigned int*)(0x42485310UL))
+#define bFM3_MFT_PPG_GATEC8_STRG10             *((volatile unsigned int*)(0x42485314UL))
+#define bFM3_MFT_PPG_PPGC13_TTRG               *((volatile unsigned int*)(0x42485800UL))
+#define bFM3_MFT_PPG_PPGC13_PCS0               *((volatile unsigned int*)(0x4248580CUL))
+#define bFM3_MFT_PPG_PPGC13_PCS1               *((volatile unsigned int*)(0x42485810UL))
+#define bFM3_MFT_PPG_PPGC13_INTM               *((volatile unsigned int*)(0x42485814UL))
+#define bFM3_MFT_PPG_PPGC13_PUF                *((volatile unsigned int*)(0x42485818UL))
+#define bFM3_MFT_PPG_PPGC13_PIE                *((volatile unsigned int*)(0x4248581CUL))
+#define bFM3_MFT_PPG_PPGC12_TTRG               *((volatile unsigned int*)(0x42485820UL))
+#define bFM3_MFT_PPG_PPGC12_PCS0               *((volatile unsigned int*)(0x4248582CUL))
+#define bFM3_MFT_PPG_PPGC12_PCS1               *((volatile unsigned int*)(0x42485830UL))
+#define bFM3_MFT_PPG_PPGC12_INTM               *((volatile unsigned int*)(0x42485834UL))
+#define bFM3_MFT_PPG_PPGC12_PUF                *((volatile unsigned int*)(0x42485838UL))
+#define bFM3_MFT_PPG_PPGC12_PIE                *((volatile unsigned int*)(0x4248583CUL))
+#define bFM3_MFT_PPG_PPGC15_TTRG               *((volatile unsigned int*)(0x42485880UL))
+#define bFM3_MFT_PPG_PPGC15_PCS0               *((volatile unsigned int*)(0x4248588CUL))
+#define bFM3_MFT_PPG_PPGC15_PCS1               *((volatile unsigned int*)(0x42485890UL))
+#define bFM3_MFT_PPG_PPGC15_INTM               *((volatile unsigned int*)(0x42485894UL))
+#define bFM3_MFT_PPG_PPGC15_PUF                *((volatile unsigned int*)(0x42485898UL))
+#define bFM3_MFT_PPG_PPGC15_PIE                *((volatile unsigned int*)(0x4248589CUL))
+#define bFM3_MFT_PPG_PPGC14_TTRG               *((volatile unsigned int*)(0x424858A0UL))
+#define bFM3_MFT_PPG_PPGC14_PCS0               *((volatile unsigned int*)(0x424858ACUL))
+#define bFM3_MFT_PPG_PPGC14_PCS1               *((volatile unsigned int*)(0x424858B0UL))
+#define bFM3_MFT_PPG_PPGC14_INTM               *((volatile unsigned int*)(0x424858B4UL))
+#define bFM3_MFT_PPG_PPGC14_PUF                *((volatile unsigned int*)(0x424858B8UL))
+#define bFM3_MFT_PPG_PPGC14_PIE                *((volatile unsigned int*)(0x424858BCUL))
+#define bFM3_MFT_PPG_GATEC12_EDGE12            *((volatile unsigned int*)(0x42485B00UL))
+#define bFM3_MFT_PPG_GATEC12_STRG12            *((volatile unsigned int*)(0x42485B04UL))
+#define bFM3_MFT_PPG_GATEC12_EDGE14            *((volatile unsigned int*)(0x42485B10UL))
+#define bFM3_MFT_PPG_GATEC12_STRG14            *((volatile unsigned int*)(0x42485B14UL))
+#define bFM3_MFT_PPG_PPGC17_TTRG               *((volatile unsigned int*)(0x42486000UL))
+#define bFM3_MFT_PPG_PPGC17_PCS0               *((volatile unsigned int*)(0x4248600CUL))
+#define bFM3_MFT_PPG_PPGC17_PCS1               *((volatile unsigned int*)(0x42486010UL))
+#define bFM3_MFT_PPG_PPGC17_INTM               *((volatile unsigned int*)(0x42486014UL))
+#define bFM3_MFT_PPG_PPGC17_PUF                *((volatile unsigned int*)(0x42486018UL))
+#define bFM3_MFT_PPG_PPGC17_PIE                *((volatile unsigned int*)(0x4248601CUL))
+#define bFM3_MFT_PPG_PPGC16_TTRG               *((volatile unsigned int*)(0x42486020UL))
+#define bFM3_MFT_PPG_PPGC16_PCS0               *((volatile unsigned int*)(0x4248602CUL))
+#define bFM3_MFT_PPG_PPGC16_PCS1               *((volatile unsigned int*)(0x42486030UL))
+#define bFM3_MFT_PPG_PPGC16_INTM               *((volatile unsigned int*)(0x42486034UL))
+#define bFM3_MFT_PPG_PPGC16_PUF                *((volatile unsigned int*)(0x42486038UL))
+#define bFM3_MFT_PPG_PPGC16_PIE                *((volatile unsigned int*)(0x4248603CUL))
+#define bFM3_MFT_PPG_PPGC19_TTRG               *((volatile unsigned int*)(0x42486080UL))
+#define bFM3_MFT_PPG_PPGC19_PCS0               *((volatile unsigned int*)(0x4248608CUL))
+#define bFM3_MFT_PPG_PPGC19_PCS1               *((volatile unsigned int*)(0x42486090UL))
+#define bFM3_MFT_PPG_PPGC19_INTM               *((volatile unsigned int*)(0x42486094UL))
+#define bFM3_MFT_PPG_PPGC19_PUF                *((volatile unsigned int*)(0x42486098UL))
+#define bFM3_MFT_PPG_PPGC19_PIE                *((volatile unsigned int*)(0x4248609CUL))
+#define bFM3_MFT_PPG_PPGC18_TTRG               *((volatile unsigned int*)(0x424860A0UL))
+#define bFM3_MFT_PPG_PPGC18_PCS0               *((volatile unsigned int*)(0x424860ACUL))
+#define bFM3_MFT_PPG_PPGC18_PCS1               *((volatile unsigned int*)(0x424860B0UL))
+#define bFM3_MFT_PPG_PPGC18_INTM               *((volatile unsigned int*)(0x424860B4UL))
+#define bFM3_MFT_PPG_PPGC18_PUF                *((volatile unsigned int*)(0x424860B8UL))
+#define bFM3_MFT_PPG_PPGC18_PIE                *((volatile unsigned int*)(0x424860BCUL))
+#define bFM3_MFT_PPG_GATEC16_EDGE16            *((volatile unsigned int*)(0x42486300UL))
+#define bFM3_MFT_PPG_GATEC16_STRG16            *((volatile unsigned int*)(0x42486304UL))
+#define bFM3_MFT_PPG_GATEC16_EDGE18            *((volatile unsigned int*)(0x42486310UL))
+#define bFM3_MFT_PPG_GATEC16_STRG18            *((volatile unsigned int*)(0x42486314UL))
+#define bFM3_MFT_PPG_PPGC21_TTRG               *((volatile unsigned int*)(0x42486800UL))
+#define bFM3_MFT_PPG_PPGC21_PCS0               *((volatile unsigned int*)(0x4248680CUL))
+#define bFM3_MFT_PPG_PPGC21_PCS1               *((volatile unsigned int*)(0x42486810UL))
+#define bFM3_MFT_PPG_PPGC21_INTM               *((volatile unsigned int*)(0x42486814UL))
+#define bFM3_MFT_PPG_PPGC21_PUF                *((volatile unsigned int*)(0x42486818UL))
+#define bFM3_MFT_PPG_PPGC21_PIE                *((volatile unsigned int*)(0x4248681CUL))
+#define bFM3_MFT_PPG_PPGC20_TTRG               *((volatile unsigned int*)(0x42486820UL))
+#define bFM3_MFT_PPG_PPGC20_PCS0               *((volatile unsigned int*)(0x4248682CUL))
+#define bFM3_MFT_PPG_PPGC20_PCS1               *((volatile unsigned int*)(0x42486830UL))
+#define bFM3_MFT_PPG_PPGC20_INTM               *((volatile unsigned int*)(0x42486834UL))
+#define bFM3_MFT_PPG_PPGC20_PUF                *((volatile unsigned int*)(0x42486838UL))
+#define bFM3_MFT_PPG_PPGC20_PIE                *((volatile unsigned int*)(0x4248683CUL))
+#define bFM3_MFT_PPG_PPGC23_TTRG               *((volatile unsigned int*)(0x42486880UL))
+#define bFM3_MFT_PPG_PPGC23_PCS0               *((volatile unsigned int*)(0x4248688CUL))
+#define bFM3_MFT_PPG_PPGC23_PCS1               *((volatile unsigned int*)(0x42486890UL))
+#define bFM3_MFT_PPG_PPGC23_INTM               *((volatile unsigned int*)(0x42486894UL))
+#define bFM3_MFT_PPG_PPGC23_PUF                *((volatile unsigned int*)(0x42486898UL))
+#define bFM3_MFT_PPG_PPGC23_PIE                *((volatile unsigned int*)(0x4248689CUL))
+#define bFM3_MFT_PPG_PPGC22_TTRG               *((volatile unsigned int*)(0x424868A0UL))
+#define bFM3_MFT_PPG_PPGC22_PCS0               *((volatile unsigned int*)(0x424868ACUL))
+#define bFM3_MFT_PPG_PPGC22_PCS1               *((volatile unsigned int*)(0x424868B0UL))
+#define bFM3_MFT_PPG_PPGC22_INTM               *((volatile unsigned int*)(0x424868B4UL))
+#define bFM3_MFT_PPG_PPGC22_PUF                *((volatile unsigned int*)(0x424868B8UL))
+#define bFM3_MFT_PPG_PPGC22_PIE                *((volatile unsigned int*)(0x424868BCUL))
+#define bFM3_MFT_PPG_GATEC20_EDGE20            *((volatile unsigned int*)(0x42486B00UL))
+#define bFM3_MFT_PPG_GATEC20_STRG20            *((volatile unsigned int*)(0x42486B04UL))
+#define bFM3_MFT_PPG_GATEC20_EDGE22            *((volatile unsigned int*)(0x42486B10UL))
+#define bFM3_MFT_PPG_GATEC20_STRG22            *((volatile unsigned int*)(0x42486B14UL))
+
+/* Base Timer 0 PPG registers */
+#define bFM3_BT0_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWM registers */
+#define bFM3_BT0_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0204UL))
+#define bFM3_BT0_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0214UL))
+#define bFM3_BT0_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 RT registers */
+#define bFM3_BT0_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWC registers */
+#define bFM3_BT0_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A021CUL))
+#define bFM3_BT0_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 1 PPG registers */
+#define bFM3_BT1_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWM registers */
+#define bFM3_BT1_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0A04UL))
+#define bFM3_BT1_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0A14UL))
+#define bFM3_BT1_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 RT registers */
+#define bFM3_BT1_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWC registers */
+#define bFM3_BT1_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A0A1CUL))
+#define bFM3_BT1_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 2 PPG registers */
+#define bFM3_BT2_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWM registers */
+#define bFM3_BT2_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1204UL))
+#define bFM3_BT2_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1214UL))
+#define bFM3_BT2_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 RT registers */
+#define bFM3_BT2_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWC registers */
+#define bFM3_BT2_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A121CUL))
+#define bFM3_BT2_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 3 PPG registers */
+#define bFM3_BT3_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWM registers */
+#define bFM3_BT3_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1A04UL))
+#define bFM3_BT3_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1A14UL))
+#define bFM3_BT3_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 RT registers */
+#define bFM3_BT3_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWC registers */
+#define bFM3_BT3_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A1A1CUL))
+#define bFM3_BT3_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 4 PPG registers */
+#define bFM3_BT4_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWM registers */
+#define bFM3_BT4_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4204UL))
+#define bFM3_BT4_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4214UL))
+#define bFM3_BT4_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 RT registers */
+#define bFM3_BT4_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWC registers */
+#define bFM3_BT4_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A421CUL))
+#define bFM3_BT4_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 5 PPG registers */
+#define bFM3_BT5_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWM registers */
+#define bFM3_BT5_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4A04UL))
+#define bFM3_BT5_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4A14UL))
+#define bFM3_BT5_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 RT registers */
+#define bFM3_BT5_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWC registers */
+#define bFM3_BT5_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A4A1CUL))
+#define bFM3_BT5_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 6 PPG registers */
+#define bFM3_BT6_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWM registers */
+#define bFM3_BT6_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5204UL))
+#define bFM3_BT6_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5214UL))
+#define bFM3_BT6_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 RT registers */
+#define bFM3_BT6_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWC registers */
+#define bFM3_BT6_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A521CUL))
+#define bFM3_BT6_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 7 PPG registers */
+#define bFM3_BT7_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWM registers */
+#define bFM3_BT7_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5A04UL))
+#define bFM3_BT7_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5A14UL))
+#define bFM3_BT7_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 RT registers */
+#define bFM3_BT7_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWC registers */
+#define bFM3_BT7_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A5A1CUL))
+#define bFM3_BT7_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0       *((volatile unsigned int*)(0x424A2020UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1       *((volatile unsigned int*)(0x424A2024UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2       *((volatile unsigned int*)(0x424A2028UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3       *((volatile unsigned int*)(0x424A202CUL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0       *((volatile unsigned int*)(0x424A2030UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1       *((volatile unsigned int*)(0x424A2034UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2       *((volatile unsigned int*)(0x424A2038UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3       *((volatile unsigned int*)(0x424A203CUL))
+
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0       *((volatile unsigned int*)(0x424A6020UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1       *((volatile unsigned int*)(0x424A6024UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2       *((volatile unsigned int*)(0x424A6028UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3       *((volatile unsigned int*)(0x424A602CUL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0       *((volatile unsigned int*)(0x424A6030UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1       *((volatile unsigned int*)(0x424A6034UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2       *((volatile unsigned int*)(0x424A6038UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3       *((volatile unsigned int*)(0x424A603CUL))
+
+/* Base Timer 8 PPG registers */
+#define bFM3_BT8_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWM registers */
+#define bFM3_BT8_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8204UL))
+#define bFM3_BT8_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8214UL))
+#define bFM3_BT8_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 RT registers */
+#define bFM3_BT8_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWC registers */
+#define bFM3_BT8_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A821CUL))
+#define bFM3_BT8_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 9 PPG registers */
+#define bFM3_BT9_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWM registers */
+#define bFM3_BT9_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8A04UL))
+#define bFM3_BT9_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8A14UL))
+#define bFM3_BT9_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 RT registers */
+#define bFM3_BT9_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWC registers */
+#define bFM3_BT9_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A8A1CUL))
+#define bFM3_BT9_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 10 PPG registers */
+#define bFM3_BT10_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWM registers */
+#define bFM3_BT10_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9204UL))
+#define bFM3_BT10_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9214UL))
+#define bFM3_BT10_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 RT registers */
+#define bFM3_BT10_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWC registers */
+#define bFM3_BT10_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A921CUL))
+#define bFM3_BT10_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 11 PPG registers */
+#define bFM3_BT11_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWM registers */
+#define bFM3_BT11_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9A04UL))
+#define bFM3_BT11_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9A14UL))
+#define bFM3_BT11_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 RT registers */
+#define bFM3_BT11_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWC registers */
+#define bFM3_BT11_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A9A1CUL))
+#define bFM3_BT11_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 12 PPG registers */
+#define bFM3_BT12_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWM registers */
+#define bFM3_BT12_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AC204UL))
+#define bFM3_BT12_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AC214UL))
+#define bFM3_BT12_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 RT registers */
+#define bFM3_BT12_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWC registers */
+#define bFM3_BT12_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AC21CUL))
+#define bFM3_BT12_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 13 PPG registers */
+#define bFM3_BT13_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWM registers */
+#define bFM3_BT13_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ACA04UL))
+#define bFM3_BT13_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ACA14UL))
+#define bFM3_BT13_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 RT registers */
+#define bFM3_BT13_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWC registers */
+#define bFM3_BT13_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ACA1CUL))
+#define bFM3_BT13_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 14 PPG registers */
+#define bFM3_BT14_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWM registers */
+#define bFM3_BT14_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AD204UL))
+#define bFM3_BT14_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AD214UL))
+#define bFM3_BT14_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 RT registers */
+#define bFM3_BT14_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWC registers */
+#define bFM3_BT14_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AD21CUL))
+#define bFM3_BT14_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 15 PPG registers */
+#define bFM3_BT15_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWM registers */
+#define bFM3_BT15_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ADA04UL))
+#define bFM3_BT15_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ADA14UL))
+#define bFM3_BT15_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 RT registers */
+#define bFM3_BT15_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWC registers */
+#define bFM3_BT15_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ADA1CUL))
+#define bFM3_BT15_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0       *((volatile unsigned int*)(0x424AA020UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1       *((volatile unsigned int*)(0x424AA024UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2       *((volatile unsigned int*)(0x424AA028UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3       *((volatile unsigned int*)(0x424AA02CUL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0       *((volatile unsigned int*)(0x424AA030UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1       *((volatile unsigned int*)(0x424AA034UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2       *((volatile unsigned int*)(0x424AA038UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3       *((volatile unsigned int*)(0x424AA03CUL))
+
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0       *((volatile unsigned int*)(0x424AE020UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1       *((volatile unsigned int*)(0x424AE024UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2       *((volatile unsigned int*)(0x424AE028UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3       *((volatile unsigned int*)(0x424AE02CUL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0       *((volatile unsigned int*)(0x424AE030UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1       *((volatile unsigned int*)(0x424AE034UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2       *((volatile unsigned int*)(0x424AE038UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3       *((volatile unsigned int*)(0x424AE03CUL))
+
+/* Software based Simulation Startup (Base Timer) register */
+#define bFM3_SBSSR_BTSSSR_SSR0                 *((volatile unsigned int*)(0x424BFF80UL))
+#define bFM3_SBSSR_BTSSSR_SSR1                 *((volatile unsigned int*)(0x424BFF84UL))
+#define bFM3_SBSSR_BTSSSR_SSR2                 *((volatile unsigned int*)(0x424BFF88UL))
+#define bFM3_SBSSR_BTSSSR_SSR3                 *((volatile unsigned int*)(0x424BFF8CUL))
+#define bFM3_SBSSR_BTSSSR_SSR4                 *((volatile unsigned int*)(0x424BFF90UL))
+#define bFM3_SBSSR_BTSSSR_SSR5                 *((volatile unsigned int*)(0x424BFF94UL))
+#define bFM3_SBSSR_BTSSSR_SSR6                 *((volatile unsigned int*)(0x424BFF98UL))
+#define bFM3_SBSSR_BTSSSR_SSR7                 *((volatile unsigned int*)(0x424BFF9CUL))
+#define bFM3_SBSSR_BTSSSR_SSR8                 *((volatile unsigned int*)(0x424BFFA0UL))
+#define bFM3_SBSSR_BTSSSR_SSR9                 *((volatile unsigned int*)(0x424BFFA4UL))
+#define bFM3_SBSSR_BTSSSR_SSR10                *((volatile unsigned int*)(0x424BFFA8UL))
+#define bFM3_SBSSR_BTSSSR_SSR11                *((volatile unsigned int*)(0x424BFFACUL))
+#define bFM3_SBSSR_BTSSSR_SSR12                *((volatile unsigned int*)(0x424BFFB0UL))
+#define bFM3_SBSSR_BTSSSR_SSR13                *((volatile unsigned int*)(0x424BFFB4UL))
+#define bFM3_SBSSR_BTSSSR_SSR14                *((volatile unsigned int*)(0x424BFFB8UL))
+#define bFM3_SBSSR_BTSSSR_SSR15                *((volatile unsigned int*)(0x424BFFBCUL))
+
+/* Quad position and revolution counter channel 0 registers */
+#define bFM3_QPRC0_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICR_UFDF                   *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICR_OFDF                   *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICR_ZIIF                   *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICR_CDCIE                  *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICR_CDCF                   *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICR_DIRPC                  *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICR_DIROU                  *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICRH_CDCF                  *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICRH_DIROU                 *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QCR_PCM0                    *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCR_PCM1                    *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCR_RCM0                    *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCR_RCM1                    *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCR_PSTP                    *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCR_CGSC                    *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCR_RSEL                    *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCR_SWAP                    *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCR_AES0                    *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCR_AES1                    *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCR_BES0                    *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCR_BES1                    *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCR_CGE0                    *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCR_CGE1                    *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCRL_RCM1                   *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCRL_SWAP                   *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCRH_AES0                   *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCRH_AES1                   *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCRH_BES0                   *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCRH_BES1                   *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCRH_CGE1                   *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0380UL))
+#define bFM3_QPRC0_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0384UL))
+#define bFM3_QPRC0_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0388UL))
+
+/* Quad position and revolution counter channel 1 registers */
+#define bFM3_QPRC1_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICR_UFDF                   *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICR_OFDF                   *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICR_ZIIF                   *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICR_CDCIE                  *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICR_CDCF                   *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICR_DIRPC                  *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICR_DIROU                  *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICRH_CDCF                  *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICRH_DIROU                 *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QCR_PCM0                    *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCR_PCM1                    *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCR_RCM0                    *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCR_RCM1                    *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCR_PSTP                    *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCR_CGSC                    *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCR_RSEL                    *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCR_SWAP                    *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCR_AES0                    *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCR_AES1                    *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCR_BES0                    *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCR_BES1                    *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCR_CGE0                    *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCR_CGE1                    *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCRL_RCM1                   *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCRL_SWAP                   *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCRH_AES0                   *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCRH_AES1                   *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCRH_BES0                   *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCRH_BES1                   *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCRH_CGE1                   *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0B80UL))
+#define bFM3_QPRC1_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0B84UL))
+#define bFM3_QPRC1_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0B88UL))
+
+/* Quad position and revolution counter channel 2 registers */
+#define bFM3_QPRC2_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICR_QPCMF                  *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICR_OUZIE                  *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICR_UFDF                   *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICR_OFDF                   *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICR_ZIIF                   *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICR_CDCIE                  *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICR_CDCF                   *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICR_DIRPC                  *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICR_DIROU                  *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICRL_UFDF                  *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICRL_OFDF                  *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICRH_CDCF                  *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICRH_DIROU                 *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QCR_PCM0                    *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCR_PCM1                    *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCR_RCM0                    *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCR_RCM1                    *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCR_PSTP                    *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCR_CGSC                    *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCR_RSEL                    *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCR_SWAP                    *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCR_PCRM0                   *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCR_PCRM1                   *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCR_AES0                    *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCR_AES1                    *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCR_BES0                    *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCR_BES1                    *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCR_CGE0                    *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCR_CGE1                    *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QCRL_PCM0                   *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCRL_PCM1                   *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCRL_RCM0                   *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCRL_RCM1                   *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCRL_PSTP                   *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCRL_CGSC                   *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCRL_RSEL                   *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCRL_SWAP                   *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCRH_AES0                   *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCRH_AES1                   *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCRH_BES0                   *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCRH_BES1                   *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCRH_CGE0                   *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCRH_CGE1                   *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C1380UL))
+#define bFM3_QPRC2_QECR_ORNGF                  *((volatile unsigned int*)(0x424C1384UL))
+#define bFM3_QPRC2_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C1388UL))
+
+/* 12-bit ADC unit 0 registers */
+#define bFM3_ADC0_ADSR_SCS                     *((volatile unsigned int*)(0x424E0000UL))
+#define bFM3_ADC0_ADSR_PCS                     *((volatile unsigned int*)(0x424E0004UL))
+#define bFM3_ADC0_ADSR_PCNS                    *((volatile unsigned int*)(0x424E0008UL))
+#define bFM3_ADC0_ADSR_FDAS                    *((volatile unsigned int*)(0x424E0018UL))
+#define bFM3_ADC0_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E001CUL))
+#define bFM3_ADC0_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E0020UL))
+#define bFM3_ADC0_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E0024UL))
+#define bFM3_ADC0_ADCR_PCIE                    *((volatile unsigned int*)(0x424E0028UL))
+#define bFM3_ADC0_ADCR_SCIE                    *((volatile unsigned int*)(0x424E002CUL))
+#define bFM3_ADC0_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E0034UL))
+#define bFM3_ADC0_ADCR_PCIF                    *((volatile unsigned int*)(0x424E0038UL))
+#define bFM3_ADC0_ADCR_SCIF                    *((volatile unsigned int*)(0x424E003CUL))
+#define bFM3_ADC0_SFNS_SFS0                    *((volatile unsigned int*)(0x424E0100UL))
+#define bFM3_ADC0_SFNS_SFS1                    *((volatile unsigned int*)(0x424E0104UL))
+#define bFM3_ADC0_SFNS_SFS2                    *((volatile unsigned int*)(0x424E0108UL))
+#define bFM3_ADC0_SFNS_SFS3                    *((volatile unsigned int*)(0x424E010CUL))
+#define bFM3_ADC0_SCCR_SSTR                    *((volatile unsigned int*)(0x424E0120UL))
+#define bFM3_ADC0_SCCR_SHEN                    *((volatile unsigned int*)(0x424E0124UL))
+#define bFM3_ADC0_SCCR_RPT                     *((volatile unsigned int*)(0x424E0128UL))
+#define bFM3_ADC0_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E0130UL))
+#define bFM3_ADC0_SCCR_SOVR                    *((volatile unsigned int*)(0x424E0134UL))
+#define bFM3_ADC0_SCCR_SFUL                    *((volatile unsigned int*)(0x424E0138UL))
+#define bFM3_ADC0_SCCR_SEMP                    *((volatile unsigned int*)(0x424E013CUL))
+#define bFM3_ADC0_SCFD_SC0                     *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFD_SC1                     *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFD_SC2                     *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFD_SC3                     *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFD_SC4                     *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFD_RS0                     *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFD_RS1                     *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFD_INVL                    *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFD_SD0                     *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFD_SD1                     *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFD_SD2                     *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFD_SD3                     *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFD_SD4                     *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFD_SD5                     *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFD_SD6                     *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFD_SD7                     *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFD_SD8                     *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFD_SD9                     *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFD_SD10                    *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFD_SD11                    *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCFDL_SC0                    *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFDL_SC1                    *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFDL_SC2                    *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFDL_SC3                    *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFDL_SC4                    *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFDL_RS0                    *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFDL_RS1                    *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFDL_INVL                   *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFDH_SD0                    *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFDH_SD1                    *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFDH_SD2                    *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFDH_SD3                    *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFDH_SD4                    *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFDH_SD5                    *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFDH_SD6                    *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFDH_SD7                    *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFDH_SD8                    *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFDH_SD9                    *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFDH_SD10                   *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFDH_SD11                   *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCIS23_AN16                  *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS23_AN17                  *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS23_AN18                  *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS23_AN19                  *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS23_AN20                  *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS23_AN21                  *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS23_AN22                  *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS23_AN23                  *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS23_AN24                  *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS23_AN25                  *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS23_AN26                  *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS23_AN27                  *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS23_AN28                  *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS23_AN29                  *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS23_AN30                  *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS23_AN31                  *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS2_AN16                   *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS2_AN17                   *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS2_AN18                   *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS2_AN19                   *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS2_AN20                   *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS2_AN21                   *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS2_AN22                   *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS2_AN23                   *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS3_AN24                   *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS3_AN25                   *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS3_AN26                   *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS3_AN27                   *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS3_AN28                   *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS3_AN29                   *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS3_AN30                   *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS3_AN31                   *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS01_AN0                   *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS01_AN1                   *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS01_AN2                   *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS01_AN3                   *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS01_AN4                   *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS01_AN5                   *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS01_AN6                   *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS01_AN7                   *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS01_AN8                   *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS01_AN9                   *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS01_AN10                  *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS01_AN11                  *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS01_AN12                  *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS01_AN13                  *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS01_AN14                  *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS01_AN15                  *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_SCIS0_AN0                    *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS0_AN1                    *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS0_AN2                    *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS0_AN3                    *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS0_AN4                    *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS0_AN5                    *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS0_AN6                    *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS0_AN7                    *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS1_AN8                    *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS1_AN9                    *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS1_AN10                   *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS1_AN11                   *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS1_AN12                   *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS1_AN13                   *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS1_AN14                   *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS1_AN15                   *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_PFNS_PFS0                    *((volatile unsigned int*)(0x424E0300UL))
+#define bFM3_ADC0_PFNS_PFS1                    *((volatile unsigned int*)(0x424E0304UL))
+#define bFM3_ADC0_PFNS_TEST0                   *((volatile unsigned int*)(0x424E0310UL))
+#define bFM3_ADC0_PFNS_TEST1                   *((volatile unsigned int*)(0x424E0314UL))
+#define bFM3_ADC0_PCCR_PSTR                    *((volatile unsigned int*)(0x424E0320UL))
+#define bFM3_ADC0_PCCR_PHEN                    *((volatile unsigned int*)(0x424E0324UL))
+#define bFM3_ADC0_PCCR_PEEN                    *((volatile unsigned int*)(0x424E0328UL))
+#define bFM3_ADC0_PCCR_ESCE                    *((volatile unsigned int*)(0x424E032CUL))
+#define bFM3_ADC0_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E0330UL))
+#define bFM3_ADC0_PCCR_POVR                    *((volatile unsigned int*)(0x424E0334UL))
+#define bFM3_ADC0_PCCR_PFUL                    *((volatile unsigned int*)(0x424E0338UL))
+#define bFM3_ADC0_PCCR_PEMP                    *((volatile unsigned int*)(0x424E033CUL))
+#define bFM3_ADC0_PCFD_PC0                     *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFD_PC1                     *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFD_PC2                     *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFD_PC3                     *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFD_PC4                     *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFD_RS0                     *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFD_RS1                     *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFD_RS2                     *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFD_INVL                    *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFD_PD0                     *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFD_PD1                     *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFD_PD2                     *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFD_PD3                     *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFD_PD4                     *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFD_PD5                     *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFD_PD6                     *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFD_PD7                     *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFD_PD8                     *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFD_PD9                     *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFD_PD10                    *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFD_PD11                    *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCFDL_PC0                    *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFDL_PC1                    *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFDL_PC2                    *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFDL_PC3                    *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFDL_PC4                    *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFDL_RS0                    *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFDL_RS1                    *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFDL_RS2                    *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFDL_INVL                   *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFDH_PD0                    *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFDH_PD1                    *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFDH_PD2                    *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFDH_PD3                    *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFDH_PD4                    *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFDH_PD5                    *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFDH_PD6                    *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFDH_PD7                    *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFDH_PD8                    *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFDH_PD9                    *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFDH_PD10                   *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFDH_PD11                   *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCIS_P1A0                    *((volatile unsigned int*)(0x424E0400UL))
+#define bFM3_ADC0_PCIS_P1A1                    *((volatile unsigned int*)(0x424E0404UL))
+#define bFM3_ADC0_PCIS_P1A2                    *((volatile unsigned int*)(0x424E0408UL))
+#define bFM3_ADC0_PCIS_P2A0                    *((volatile unsigned int*)(0x424E040CUL))
+#define bFM3_ADC0_PCIS_P2A1                    *((volatile unsigned int*)(0x424E0410UL))
+#define bFM3_ADC0_PCIS_P2A2                    *((volatile unsigned int*)(0x424E0414UL))
+#define bFM3_ADC0_PCIS_P2A3                    *((volatile unsigned int*)(0x424E0418UL))
+#define bFM3_ADC0_PCIS_P2A4                    *((volatile unsigned int*)(0x424E041CUL))
+#define bFM3_ADC0_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E0480UL))
+#define bFM3_ADC0_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E0484UL))
+#define bFM3_ADC0_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E0488UL))
+#define bFM3_ADC0_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E048CUL))
+#define bFM3_ADC0_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E0490UL))
+#define bFM3_ADC0_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E0494UL))
+#define bFM3_ADC0_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E0498UL))
+#define bFM3_ADC0_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E049CUL))
+#define bFM3_ADC0_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E04D8UL))
+#define bFM3_ADC0_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E04DCUL))
+#define bFM3_ADC0_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E04E0UL))
+#define bFM3_ADC0_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E04E4UL))
+#define bFM3_ADC0_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E04E8UL))
+#define bFM3_ADC0_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E04ECUL))
+#define bFM3_ADC0_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E04F0UL))
+#define bFM3_ADC0_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E04F4UL))
+#define bFM3_ADC0_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E04F8UL))
+#define bFM3_ADC0_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E04FCUL))
+#define bFM3_ADC0_ADSS23_TS16                  *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS23_TS17                  *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS23_TS18                  *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS23_TS19                  *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS23_TS20                  *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS23_TS21                  *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS23_TS22                  *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS23_TS23                  *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS23_TS24                  *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS23_TS25                  *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS23_TS26                  *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS23_TS27                  *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS23_TS28                  *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS23_TS29                  *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS23_TS30                  *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS23_TS31                  *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS2_TS16                   *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS2_TS17                   *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS2_TS18                   *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS2_TS19                   *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS2_TS20                   *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS2_TS21                   *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS2_TS22                   *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS2_TS23                   *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS3_TS24                   *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS3_TS25                   *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS3_TS26                   *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS3_TS27                   *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS3_TS28                   *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS3_TS29                   *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS3_TS30                   *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS3_TS31                   *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS01_TS0                   *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS01_TS1                   *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS01_TS2                   *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS01_TS3                   *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS01_TS4                   *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS01_TS5                   *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS01_TS6                   *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS01_TS7                   *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS01_TS8                   *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS01_TS9                   *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS01_TS10                  *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS01_TS11                  *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS01_TS12                  *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS01_TS13                  *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS01_TS14                  *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS01_TS15                  *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADSS0_TS0                    *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS0_TS1                    *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS0_TS2                    *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS0_TS3                    *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS0_TS4                    *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS0_TS5                    *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS0_TS6                    *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS0_TS7                    *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS1_TS8                    *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS1_TS9                    *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS1_TS10                   *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS1_TS11                   *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS1_TS12                   *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS1_TS13                   *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS1_TS14                   *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS1_TS15                   *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADST01_ST10                  *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST01_ST11                  *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST01_ST12                  *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST01_ST13                  *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST01_ST14                  *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST01_STX10                 *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST01_STX11                 *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST01_STX12                 *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST01_ST00                  *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST01_ST01                  *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST01_ST02                  *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST01_ST03                  *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST01_ST04                  *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST01_STX00                 *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST01_STX01                 *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST01_STX02                 *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADST1_ST10                   *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST1_ST11                   *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST1_ST12                   *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST1_ST13                   *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST1_ST14                   *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST1_STX10                  *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST1_STX11                  *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST1_STX12                  *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST0_ST00                   *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST0_ST01                   *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST0_ST02                   *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST0_ST03                   *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST0_ST04                   *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST0_STX00                  *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST0_STX01                  *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST0_STX02                  *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADCT_CT0                     *((volatile unsigned int*)(0x424E0680UL))
+#define bFM3_ADC0_ADCT_CT1                     *((volatile unsigned int*)(0x424E0684UL))
+#define bFM3_ADC0_ADCT_CT2                     *((volatile unsigned int*)(0x424E0688UL))
+#define bFM3_ADC0_ADCT_CT3                     *((volatile unsigned int*)(0x424E068CUL))
+#define bFM3_ADC0_ADCT_CT4                     *((volatile unsigned int*)(0x424E0690UL))
+#define bFM3_ADC0_ADCT_CT5                     *((volatile unsigned int*)(0x424E0694UL))
+#define bFM3_ADC0_ADCT_CT6                     *((volatile unsigned int*)(0x424E0698UL))
+#define bFM3_ADC0_ADCT_CT7                     *((volatile unsigned int*)(0x424E069CUL))
+#define bFM3_ADC0_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E0700UL))
+#define bFM3_ADC0_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E0704UL))
+#define bFM3_ADC0_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E0708UL))
+#define bFM3_ADC0_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E070CUL))
+#define bFM3_ADC0_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E0720UL))
+#define bFM3_ADC0_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E0724UL))
+#define bFM3_ADC0_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E0728UL))
+#define bFM3_ADC0_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E072CUL))
+#define bFM3_ADC0_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E0780UL))
+#define bFM3_ADC0_ADCEN_READY                  *((volatile unsigned int*)(0x424E0784UL))
+#define bFM3_ADC0_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E0790UL))
+#define bFM3_ADC0_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E0794UL))
+
+/* 12-bit ADC unit 1 registers */
+#define bFM3_ADC1_ADSR_SCS                     *((volatile unsigned int*)(0x424E2000UL))
+#define bFM3_ADC1_ADSR_PCS                     *((volatile unsigned int*)(0x424E2004UL))
+#define bFM3_ADC1_ADSR_PCNS                    *((volatile unsigned int*)(0x424E2008UL))
+#define bFM3_ADC1_ADSR_FDAS                    *((volatile unsigned int*)(0x424E2018UL))
+#define bFM3_ADC1_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E201CUL))
+#define bFM3_ADC1_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E2020UL))
+#define bFM3_ADC1_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E2024UL))
+#define bFM3_ADC1_ADCR_PCIE                    *((volatile unsigned int*)(0x424E2028UL))
+#define bFM3_ADC1_ADCR_SCIE                    *((volatile unsigned int*)(0x424E202CUL))
+#define bFM3_ADC1_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E2034UL))
+#define bFM3_ADC1_ADCR_PCIF                    *((volatile unsigned int*)(0x424E2038UL))
+#define bFM3_ADC1_ADCR_SCIF                    *((volatile unsigned int*)(0x424E203CUL))
+#define bFM3_ADC1_SFNS_SFS0                    *((volatile unsigned int*)(0x424E2100UL))
+#define bFM3_ADC1_SFNS_SFS1                    *((volatile unsigned int*)(0x424E2104UL))
+#define bFM3_ADC1_SFNS_SFS2                    *((volatile unsigned int*)(0x424E2108UL))
+#define bFM3_ADC1_SFNS_SFS3                    *((volatile unsigned int*)(0x424E210CUL))
+#define bFM3_ADC1_SCCR_SSTR                    *((volatile unsigned int*)(0x424E2120UL))
+#define bFM3_ADC1_SCCR_SHEN                    *((volatile unsigned int*)(0x424E2124UL))
+#define bFM3_ADC1_SCCR_RPT                     *((volatile unsigned int*)(0x424E2128UL))
+#define bFM3_ADC1_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E2130UL))
+#define bFM3_ADC1_SCCR_SOVR                    *((volatile unsigned int*)(0x424E2134UL))
+#define bFM3_ADC1_SCCR_SFUL                    *((volatile unsigned int*)(0x424E2138UL))
+#define bFM3_ADC1_SCCR_SEMP                    *((volatile unsigned int*)(0x424E213CUL))
+#define bFM3_ADC1_SCFD_SC0                     *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFD_SC1                     *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFD_SC2                     *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFD_SC3                     *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFD_SC4                     *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFD_RS0                     *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFD_RS1                     *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFD_INVL                    *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFD_SD0                     *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFD_SD1                     *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFD_SD2                     *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFD_SD3                     *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFD_SD4                     *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFD_SD5                     *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFD_SD6                     *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFD_SD7                     *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFD_SD8                     *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFD_SD9                     *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFD_SD10                    *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFD_SD11                    *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCFDL_SC0                    *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFDL_SC1                    *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFDL_SC2                    *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFDL_SC3                    *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFDL_SC4                    *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFDL_RS0                    *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFDL_RS1                    *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFDL_INVL                   *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFDH_SD0                    *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFDH_SD1                    *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFDH_SD2                    *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFDH_SD3                    *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFDH_SD4                    *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFDH_SD5                    *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFDH_SD6                    *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFDH_SD7                    *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFDH_SD8                    *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFDH_SD9                    *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFDH_SD10                   *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFDH_SD11                   *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCIS23_AN16                  *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS23_AN17                  *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS23_AN18                  *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS23_AN19                  *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS23_AN20                  *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS23_AN21                  *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS23_AN22                  *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS23_AN23                  *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS23_AN24                  *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS23_AN25                  *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS23_AN26                  *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS23_AN27                  *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS23_AN28                  *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS23_AN29                  *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS23_AN30                  *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS23_AN31                  *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS2_AN16                   *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS2_AN17                   *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS2_AN18                   *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS2_AN19                   *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS2_AN20                   *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS2_AN21                   *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS2_AN22                   *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS2_AN23                   *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS3_AN24                   *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS3_AN25                   *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS3_AN26                   *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS3_AN27                   *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS3_AN28                   *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS3_AN29                   *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS3_AN30                   *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS3_AN31                   *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS01_AN0                   *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS01_AN1                   *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS01_AN2                   *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS01_AN3                   *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS01_AN4                   *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS01_AN5                   *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS01_AN6                   *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS01_AN7                   *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS01_AN8                   *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS01_AN9                   *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS01_AN10                  *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS01_AN11                  *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS01_AN12                  *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS01_AN13                  *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS01_AN14                  *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS01_AN15                  *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_SCIS0_AN0                    *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS0_AN1                    *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS0_AN2                    *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS0_AN3                    *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS0_AN4                    *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS0_AN5                    *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS0_AN6                    *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS0_AN7                    *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS1_AN8                    *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS1_AN9                    *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS1_AN10                   *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS1_AN11                   *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS1_AN12                   *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS1_AN13                   *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS1_AN14                   *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS1_AN15                   *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_PFNS_PFS0                    *((volatile unsigned int*)(0x424E2300UL))
+#define bFM3_ADC1_PFNS_PFS1                    *((volatile unsigned int*)(0x424E2304UL))
+#define bFM3_ADC1_PFNS_TEST0                   *((volatile unsigned int*)(0x424E2310UL))
+#define bFM3_ADC1_PFNS_TEST1                   *((volatile unsigned int*)(0x424E2314UL))
+#define bFM3_ADC1_PCCR_PSTR                    *((volatile unsigned int*)(0x424E2320UL))
+#define bFM3_ADC1_PCCR_PHEN                    *((volatile unsigned int*)(0x424E2324UL))
+#define bFM3_ADC1_PCCR_PEEN                    *((volatile unsigned int*)(0x424E2328UL))
+#define bFM3_ADC1_PCCR_ESCE                    *((volatile unsigned int*)(0x424E232CUL))
+#define bFM3_ADC1_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E2330UL))
+#define bFM3_ADC1_PCCR_POVR                    *((volatile unsigned int*)(0x424E2334UL))
+#define bFM3_ADC1_PCCR_PFUL                    *((volatile unsigned int*)(0x424E2338UL))
+#define bFM3_ADC1_PCCR_PEMP                    *((volatile unsigned int*)(0x424E233CUL))
+#define bFM3_ADC1_PCFD_PC0                     *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFD_PC1                     *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFD_PC2                     *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFD_PC3                     *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFD_PC4                     *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFD_RS0                     *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFD_RS1                     *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFD_RS2                     *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFD_INVL                    *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFD_PD0                     *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFD_PD1                     *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFD_PD2                     *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFD_PD3                     *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFD_PD4                     *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFD_PD5                     *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFD_PD6                     *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFD_PD7                     *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFD_PD8                     *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFD_PD9                     *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFD_PD10                    *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFD_PD11                    *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCFDL_PC0                    *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFDL_PC1                    *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFDL_PC2                    *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFDL_PC3                    *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFDL_PC4                    *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFDL_RS0                    *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFDL_RS1                    *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFDL_RS2                    *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFDL_INVL                   *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFDH_PD0                    *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFDH_PD1                    *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFDH_PD2                    *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFDH_PD3                    *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFDH_PD4                    *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFDH_PD5                    *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFDH_PD6                    *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFDH_PD7                    *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFDH_PD8                    *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFDH_PD9                    *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFDH_PD10                   *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFDH_PD11                   *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCIS_P1A0                    *((volatile unsigned int*)(0x424E2400UL))
+#define bFM3_ADC1_PCIS_P1A1                    *((volatile unsigned int*)(0x424E2404UL))
+#define bFM3_ADC1_PCIS_P1A2                    *((volatile unsigned int*)(0x424E2408UL))
+#define bFM3_ADC1_PCIS_P2A0                    *((volatile unsigned int*)(0x424E240CUL))
+#define bFM3_ADC1_PCIS_P2A1                    *((volatile unsigned int*)(0x424E2410UL))
+#define bFM3_ADC1_PCIS_P2A2                    *((volatile unsigned int*)(0x424E2414UL))
+#define bFM3_ADC1_PCIS_P2A3                    *((volatile unsigned int*)(0x424E2418UL))
+#define bFM3_ADC1_PCIS_P2A4                    *((volatile unsigned int*)(0x424E241CUL))
+#define bFM3_ADC1_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E2480UL))
+#define bFM3_ADC1_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E2484UL))
+#define bFM3_ADC1_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E2488UL))
+#define bFM3_ADC1_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E248CUL))
+#define bFM3_ADC1_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E2490UL))
+#define bFM3_ADC1_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E2494UL))
+#define bFM3_ADC1_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E2498UL))
+#define bFM3_ADC1_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E249CUL))
+#define bFM3_ADC1_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E24D8UL))
+#define bFM3_ADC1_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E24DCUL))
+#define bFM3_ADC1_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E24E0UL))
+#define bFM3_ADC1_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E24E4UL))
+#define bFM3_ADC1_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E24E8UL))
+#define bFM3_ADC1_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E24ECUL))
+#define bFM3_ADC1_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E24F0UL))
+#define bFM3_ADC1_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E24F4UL))
+#define bFM3_ADC1_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E24F8UL))
+#define bFM3_ADC1_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E24FCUL))
+#define bFM3_ADC1_ADSS23_TS16                  *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS23_TS17                  *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS23_TS18                  *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS23_TS19                  *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS23_TS20                  *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS23_TS21                  *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS23_TS22                  *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS23_TS23                  *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS23_TS24                  *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS23_TS25                  *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS23_TS26                  *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS23_TS27                  *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS23_TS28                  *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS23_TS29                  *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS23_TS30                  *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS23_TS31                  *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS2_TS16                   *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS2_TS17                   *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS2_TS18                   *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS2_TS19                   *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS2_TS20                   *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS2_TS21                   *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS2_TS22                   *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS2_TS23                   *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS3_TS24                   *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS3_TS25                   *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS3_TS26                   *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS3_TS27                   *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS3_TS28                   *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS3_TS29                   *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS3_TS30                   *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS3_TS31                   *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS01_TS0                   *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS01_TS1                   *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS01_TS2                   *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS01_TS3                   *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS01_TS4                   *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS01_TS5                   *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS01_TS6                   *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS01_TS7                   *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS01_TS8                   *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS01_TS9                   *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS01_TS10                  *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS01_TS11                  *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS01_TS12                  *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS01_TS13                  *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS01_TS14                  *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS01_TS15                  *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADSS0_TS0                    *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS0_TS1                    *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS0_TS2                    *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS0_TS3                    *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS0_TS4                    *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS0_TS5                    *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS0_TS6                    *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS0_TS7                    *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS1_TS8                    *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS1_TS9                    *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS1_TS10                   *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS1_TS11                   *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS1_TS12                   *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS1_TS13                   *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS1_TS14                   *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS1_TS15                   *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADST01_ST10                  *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST01_ST11                  *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST01_ST12                  *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST01_ST13                  *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST01_ST14                  *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST01_STX10                 *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST01_STX11                 *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST01_STX12                 *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST01_ST00                  *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST01_ST01                  *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST01_ST02                  *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST01_ST03                  *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST01_ST04                  *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST01_STX00                 *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST01_STX01                 *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST01_STX02                 *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADST1_ST10                   *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST1_ST11                   *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST1_ST12                   *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST1_ST13                   *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST1_ST14                   *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST1_STX10                  *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST1_STX11                  *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST1_STX12                  *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST0_ST00                   *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST0_ST01                   *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST0_ST02                   *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST0_ST03                   *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST0_ST04                   *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST0_STX00                  *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST0_STX01                  *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST0_STX02                  *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADCT_CT0                     *((volatile unsigned int*)(0x424E2680UL))
+#define bFM3_ADC1_ADCT_CT1                     *((volatile unsigned int*)(0x424E2684UL))
+#define bFM3_ADC1_ADCT_CT2                     *((volatile unsigned int*)(0x424E2688UL))
+#define bFM3_ADC1_ADCT_CT3                     *((volatile unsigned int*)(0x424E268CUL))
+#define bFM3_ADC1_ADCT_CT4                     *((volatile unsigned int*)(0x424E2690UL))
+#define bFM3_ADC1_ADCT_CT5                     *((volatile unsigned int*)(0x424E2694UL))
+#define bFM3_ADC1_ADCT_CT6                     *((volatile unsigned int*)(0x424E2698UL))
+#define bFM3_ADC1_ADCT_CT7                     *((volatile unsigned int*)(0x424E269CUL))
+#define bFM3_ADC1_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E2700UL))
+#define bFM3_ADC1_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E2704UL))
+#define bFM3_ADC1_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E2708UL))
+#define bFM3_ADC1_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E270CUL))
+#define bFM3_ADC1_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E2720UL))
+#define bFM3_ADC1_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E2724UL))
+#define bFM3_ADC1_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E2728UL))
+#define bFM3_ADC1_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E272CUL))
+#define bFM3_ADC1_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E2780UL))
+#define bFM3_ADC1_ADCEN_READY                  *((volatile unsigned int*)(0x424E2784UL))
+#define bFM3_ADC1_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E2790UL))
+#define bFM3_ADC1_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E2794UL))
+
+/* 12-bit ADC unit 2 registers */
+#define bFM3_ADC2_ADSR_SCS                     *((volatile unsigned int*)(0x424E4000UL))
+#define bFM3_ADC2_ADSR_PCS                     *((volatile unsigned int*)(0x424E4004UL))
+#define bFM3_ADC2_ADSR_PCNS                    *((volatile unsigned int*)(0x424E4008UL))
+#define bFM3_ADC2_ADSR_FDAS                    *((volatile unsigned int*)(0x424E4018UL))
+#define bFM3_ADC2_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E401CUL))
+#define bFM3_ADC2_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E4020UL))
+#define bFM3_ADC2_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E4024UL))
+#define bFM3_ADC2_ADCR_PCIE                    *((volatile unsigned int*)(0x424E4028UL))
+#define bFM3_ADC2_ADCR_SCIE                    *((volatile unsigned int*)(0x424E402CUL))
+#define bFM3_ADC2_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E4034UL))
+#define bFM3_ADC2_ADCR_PCIF                    *((volatile unsigned int*)(0x424E4038UL))
+#define bFM3_ADC2_ADCR_SCIF                    *((volatile unsigned int*)(0x424E403CUL))
+#define bFM3_ADC2_SFNS_SFS0                    *((volatile unsigned int*)(0x424E4100UL))
+#define bFM3_ADC2_SFNS_SFS1                    *((volatile unsigned int*)(0x424E4104UL))
+#define bFM3_ADC2_SFNS_SFS2                    *((volatile unsigned int*)(0x424E4108UL))
+#define bFM3_ADC2_SFNS_SFS3                    *((volatile unsigned int*)(0x424E410CUL))
+#define bFM3_ADC2_SCCR_SSTR                    *((volatile unsigned int*)(0x424E4120UL))
+#define bFM3_ADC2_SCCR_SHEN                    *((volatile unsigned int*)(0x424E4124UL))
+#define bFM3_ADC2_SCCR_RPT                     *((volatile unsigned int*)(0x424E4128UL))
+#define bFM3_ADC2_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E4130UL))
+#define bFM3_ADC2_SCCR_SOVR                    *((volatile unsigned int*)(0x424E4134UL))
+#define bFM3_ADC2_SCCR_SFUL                    *((volatile unsigned int*)(0x424E4138UL))
+#define bFM3_ADC2_SCCR_SEMP                    *((volatile unsigned int*)(0x424E413CUL))
+#define bFM3_ADC2_SCFD_SC0                     *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFD_SC1                     *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFD_SC2                     *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFD_SC3                     *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFD_SC4                     *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFD_RS0                     *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFD_RS1                     *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFD_INVL                    *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFD_SD0                     *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFD_SD1                     *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFD_SD2                     *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFD_SD3                     *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFD_SD4                     *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFD_SD5                     *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFD_SD6                     *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFD_SD7                     *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFD_SD8                     *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFD_SD9                     *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFD_SD10                    *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFD_SD11                    *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCFDL_SC0                    *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFDL_SC1                    *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFDL_SC2                    *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFDL_SC3                    *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFDL_SC4                    *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFDL_RS0                    *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFDL_RS1                    *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFDL_INVL                   *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFDH_SD0                    *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFDH_SD1                    *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFDH_SD2                    *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFDH_SD3                    *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFDH_SD4                    *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFDH_SD5                    *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFDH_SD6                    *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFDH_SD7                    *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFDH_SD8                    *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFDH_SD9                    *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFDH_SD10                   *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFDH_SD11                   *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCIS23_AN16                  *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS23_AN17                  *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS23_AN18                  *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS23_AN19                  *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS23_AN20                  *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS23_AN21                  *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS23_AN22                  *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS23_AN23                  *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS23_AN24                  *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS23_AN25                  *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS23_AN26                  *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS23_AN27                  *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS23_AN28                  *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS23_AN29                  *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS23_AN30                  *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS23_AN31                  *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS2_AN16                   *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS2_AN17                   *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS2_AN18                   *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS2_AN19                   *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS2_AN20                   *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS2_AN21                   *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS2_AN22                   *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS2_AN23                   *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS3_AN24                   *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS3_AN25                   *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS3_AN26                   *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS3_AN27                   *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS3_AN28                   *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS3_AN29                   *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS3_AN30                   *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS3_AN31                   *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS01_AN0                   *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS01_AN1                   *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS01_AN2                   *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS01_AN3                   *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS01_AN4                   *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS01_AN5                   *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS01_AN6                   *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS01_AN7                   *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS01_AN8                   *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS01_AN9                   *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS01_AN10                  *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS01_AN11                  *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS01_AN12                  *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS01_AN13                  *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS01_AN14                  *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS01_AN15                  *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_SCIS0_AN0                    *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS0_AN1                    *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS0_AN2                    *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS0_AN3                    *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS0_AN4                    *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS0_AN5                    *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS0_AN6                    *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS0_AN7                    *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS1_AN8                    *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS1_AN9                    *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS1_AN10                   *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS1_AN11                   *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS1_AN12                   *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS1_AN13                   *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS1_AN14                   *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS1_AN15                   *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_PFNS_PFS0                    *((volatile unsigned int*)(0x424E4300UL))
+#define bFM3_ADC2_PFNS_PFS1                    *((volatile unsigned int*)(0x424E4304UL))
+#define bFM3_ADC2_PFNS_TEST0                   *((volatile unsigned int*)(0x424E4310UL))
+#define bFM3_ADC2_PFNS_TEST1                   *((volatile unsigned int*)(0x424E4314UL))
+#define bFM3_ADC2_PCCR_PSTR                    *((volatile unsigned int*)(0x424E4320UL))
+#define bFM3_ADC2_PCCR_PHEN                    *((volatile unsigned int*)(0x424E4324UL))
+#define bFM3_ADC2_PCCR_PEEN                    *((volatile unsigned int*)(0x424E4328UL))
+#define bFM3_ADC2_PCCR_ESCE                    *((volatile unsigned int*)(0x424E432CUL))
+#define bFM3_ADC2_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E4330UL))
+#define bFM3_ADC2_PCCR_POVR                    *((volatile unsigned int*)(0x424E4334UL))
+#define bFM3_ADC2_PCCR_PFUL                    *((volatile unsigned int*)(0x424E4338UL))
+#define bFM3_ADC2_PCCR_PEMP                    *((volatile unsigned int*)(0x424E433CUL))
+#define bFM3_ADC2_PCFD_PC0                     *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFD_PC1                     *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFD_PC2                     *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFD_PC3                     *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFD_PC4                     *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFD_RS0                     *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFD_RS1                     *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFD_RS2                     *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFD_INVL                    *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFD_PD0                     *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFD_PD1                     *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFD_PD2                     *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFD_PD3                     *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFD_PD4                     *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFD_PD5                     *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFD_PD6                     *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFD_PD7                     *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFD_PD8                     *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFD_PD9                     *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFD_PD10                    *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFD_PD11                    *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCFDL_PC0                    *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFDL_PC1                    *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFDL_PC2                    *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFDL_PC3                    *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFDL_PC4                    *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFDL_RS0                    *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFDL_RS1                    *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFDL_RS2                    *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFDL_INVL                   *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFDH_PD0                    *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFDH_PD1                    *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFDH_PD2                    *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFDH_PD3                    *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFDH_PD4                    *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFDH_PD5                    *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFDH_PD6                    *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFDH_PD7                    *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFDH_PD8                    *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFDH_PD9                    *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFDH_PD10                   *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFDH_PD11                   *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCIS_P1A0                    *((volatile unsigned int*)(0x424E4400UL))
+#define bFM3_ADC2_PCIS_P1A1                    *((volatile unsigned int*)(0x424E4404UL))
+#define bFM3_ADC2_PCIS_P1A2                    *((volatile unsigned int*)(0x424E4408UL))
+#define bFM3_ADC2_PCIS_P2A0                    *((volatile unsigned int*)(0x424E440CUL))
+#define bFM3_ADC2_PCIS_P2A1                    *((volatile unsigned int*)(0x424E4410UL))
+#define bFM3_ADC2_PCIS_P2A2                    *((volatile unsigned int*)(0x424E4414UL))
+#define bFM3_ADC2_PCIS_P2A3                    *((volatile unsigned int*)(0x424E4418UL))
+#define bFM3_ADC2_PCIS_P2A4                    *((volatile unsigned int*)(0x424E441CUL))
+#define bFM3_ADC2_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E4480UL))
+#define bFM3_ADC2_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E4484UL))
+#define bFM3_ADC2_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E4488UL))
+#define bFM3_ADC2_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E448CUL))
+#define bFM3_ADC2_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E4490UL))
+#define bFM3_ADC2_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E4494UL))
+#define bFM3_ADC2_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E4498UL))
+#define bFM3_ADC2_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E449CUL))
+#define bFM3_ADC2_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E44D8UL))
+#define bFM3_ADC2_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E44DCUL))
+#define bFM3_ADC2_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E44E0UL))
+#define bFM3_ADC2_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E44E4UL))
+#define bFM3_ADC2_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E44E8UL))
+#define bFM3_ADC2_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E44ECUL))
+#define bFM3_ADC2_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E44F0UL))
+#define bFM3_ADC2_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E44F4UL))
+#define bFM3_ADC2_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E44F8UL))
+#define bFM3_ADC2_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E44FCUL))
+#define bFM3_ADC2_ADSS23_TS16                  *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS23_TS17                  *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS23_TS18                  *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS23_TS19                  *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS23_TS20                  *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS23_TS21                  *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS23_TS22                  *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS23_TS23                  *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS23_TS24                  *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS23_TS25                  *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS23_TS26                  *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS23_TS27                  *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS23_TS28                  *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS23_TS29                  *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS23_TS30                  *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS23_TS31                  *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS2_TS16                   *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS2_TS17                   *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS2_TS18                   *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS2_TS19                   *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS2_TS20                   *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS2_TS21                   *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS2_TS22                   *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS2_TS23                   *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS3_TS24                   *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS3_TS25                   *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS3_TS26                   *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS3_TS27                   *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS3_TS28                   *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS3_TS29                   *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS3_TS30                   *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS3_TS31                   *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS01_TS0                   *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS01_TS1                   *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS01_TS2                   *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS01_TS3                   *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS01_TS4                   *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS01_TS5                   *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS01_TS6                   *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS01_TS7                   *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS01_TS8                   *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS01_TS9                   *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS01_TS10                  *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS01_TS11                  *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS01_TS12                  *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS01_TS13                  *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS01_TS14                  *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS01_TS15                  *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADSS0_TS0                    *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS0_TS1                    *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS0_TS2                    *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS0_TS3                    *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS0_TS4                    *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS0_TS5                    *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS0_TS6                    *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS0_TS7                    *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS1_TS8                    *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS1_TS9                    *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS1_TS10                   *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS1_TS11                   *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS1_TS12                   *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS1_TS13                   *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS1_TS14                   *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS1_TS15                   *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADST01_ST10                  *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST01_ST11                  *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST01_ST12                  *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST01_ST13                  *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST01_ST14                  *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST01_STX10                 *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST01_STX11                 *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST01_STX12                 *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST01_ST00                  *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST01_ST01                  *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST01_ST02                  *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST01_ST03                  *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST01_ST04                  *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST01_STX00                 *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST01_STX01                 *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST01_STX02                 *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADST1_ST10                   *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST1_ST11                   *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST1_ST12                   *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST1_ST13                   *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST1_ST14                   *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST1_STX10                  *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST1_STX11                  *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST1_STX12                  *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST0_ST00                   *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST0_ST01                   *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST0_ST02                   *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST0_ST03                   *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST0_ST04                   *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST0_STX00                  *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST0_STX01                  *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST0_STX02                  *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADCT_CT0                     *((volatile unsigned int*)(0x424E4680UL))
+#define bFM3_ADC2_ADCT_CT1                     *((volatile unsigned int*)(0x424E4684UL))
+#define bFM3_ADC2_ADCT_CT2                     *((volatile unsigned int*)(0x424E4688UL))
+#define bFM3_ADC2_ADCT_CT3                     *((volatile unsigned int*)(0x424E468CUL))
+#define bFM3_ADC2_ADCT_CT4                     *((volatile unsigned int*)(0x424E4690UL))
+#define bFM3_ADC2_ADCT_CT5                     *((volatile unsigned int*)(0x424E4694UL))
+#define bFM3_ADC2_ADCT_CT6                     *((volatile unsigned int*)(0x424E4698UL))
+#define bFM3_ADC2_ADCT_CT7                     *((volatile unsigned int*)(0x424E469CUL))
+#define bFM3_ADC2_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E4700UL))
+#define bFM3_ADC2_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E4704UL))
+#define bFM3_ADC2_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E4708UL))
+#define bFM3_ADC2_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E470CUL))
+#define bFM3_ADC2_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E4720UL))
+#define bFM3_ADC2_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E4724UL))
+#define bFM3_ADC2_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E4728UL))
+#define bFM3_ADC2_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E472CUL))
+#define bFM3_ADC2_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E4780UL))
+#define bFM3_ADC2_ADCEN_READY                  *((volatile unsigned int*)(0x424E4784UL))
+#define bFM3_ADC2_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E4790UL))
+#define bFM3_ADC2_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E4794UL))
+
+/* CR trimming registers */
+#define bFM3_CRTRIM_MCR_PSR_CSR0               *((volatile unsigned int*)(0x425C0000UL))
+#define bFM3_CRTRIM_MCR_PSR_CSR1               *((volatile unsigned int*)(0x425C0004UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD0              *((volatile unsigned int*)(0x425C0080UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD1              *((volatile unsigned int*)(0x425C0084UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD2              *((volatile unsigned int*)(0x425C0088UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD3              *((volatile unsigned int*)(0x425C008CUL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD4              *((volatile unsigned int*)(0x425C0090UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD5              *((volatile unsigned int*)(0x425C0094UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD6              *((volatile unsigned int*)(0x425C0098UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD7              *((volatile unsigned int*)(0x425C009CUL))
+
+/* External interrupt registers */
+#define bFM3_EXTI_ENIR_EN0                     *((volatile unsigned int*)(0x42600000UL))
+#define bFM3_EXTI_ENIR_EN1                     *((volatile unsigned int*)(0x42600004UL))
+#define bFM3_EXTI_ENIR_EN2                     *((volatile unsigned int*)(0x42600008UL))
+#define bFM3_EXTI_ENIR_EN3                     *((volatile unsigned int*)(0x4260000CUL))
+#define bFM3_EXTI_ENIR_EN4                     *((volatile unsigned int*)(0x42600010UL))
+#define bFM3_EXTI_ENIR_EN5                     *((volatile unsigned int*)(0x42600014UL))
+#define bFM3_EXTI_ENIR_EN6                     *((volatile unsigned int*)(0x42600018UL))
+#define bFM3_EXTI_ENIR_EN7                     *((volatile unsigned int*)(0x4260001CUL))
+#define bFM3_EXTI_ENIR_EN8                     *((volatile unsigned int*)(0x42600020UL))
+#define bFM3_EXTI_ENIR_EN9                     *((volatile unsigned int*)(0x42600024UL))
+#define bFM3_EXTI_ENIR_EN10                    *((volatile unsigned int*)(0x42600028UL))
+#define bFM3_EXTI_ENIR_EN11                    *((volatile unsigned int*)(0x4260002CUL))
+#define bFM3_EXTI_ENIR_EN12                    *((volatile unsigned int*)(0x42600030UL))
+#define bFM3_EXTI_ENIR_EN13                    *((volatile unsigned int*)(0x42600034UL))
+#define bFM3_EXTI_ENIR_EN14                    *((volatile unsigned int*)(0x42600038UL))
+#define bFM3_EXTI_ENIR_EN15                    *((volatile unsigned int*)(0x4260003CUL))
+#define bFM3_EXTI_ENIR_EN16                    *((volatile unsigned int*)(0x42600040UL))
+#define bFM3_EXTI_ENIR_EN17                    *((volatile unsigned int*)(0x42600044UL))
+#define bFM3_EXTI_ENIR_EN18                    *((volatile unsigned int*)(0x42600048UL))
+#define bFM3_EXTI_ENIR_EN19                    *((volatile unsigned int*)(0x4260004CUL))
+#define bFM3_EXTI_ENIR_EN20                    *((volatile unsigned int*)(0x42600050UL))
+#define bFM3_EXTI_ENIR_EN21                    *((volatile unsigned int*)(0x42600054UL))
+#define bFM3_EXTI_ENIR_EN22                    *((volatile unsigned int*)(0x42600058UL))
+#define bFM3_EXTI_ENIR_EN23                    *((volatile unsigned int*)(0x4260005CUL))
+#define bFM3_EXTI_ENIR_EN24                    *((volatile unsigned int*)(0x42600060UL))
+#define bFM3_EXTI_ENIR_EN25                    *((volatile unsigned int*)(0x42600064UL))
+#define bFM3_EXTI_ENIR_EN26                    *((volatile unsigned int*)(0x42600068UL))
+#define bFM3_EXTI_ENIR_EN27                    *((volatile unsigned int*)(0x4260006CUL))
+#define bFM3_EXTI_ENIR_EN28                    *((volatile unsigned int*)(0x42600070UL))
+#define bFM3_EXTI_ENIR_EN29                    *((volatile unsigned int*)(0x42600074UL))
+#define bFM3_EXTI_ENIR_EN30                    *((volatile unsigned int*)(0x42600078UL))
+#define bFM3_EXTI_ENIR_EN31                    *((volatile unsigned int*)(0x4260007CUL))
+#define bFM3_EXTI_EIRR_ER0                     *((volatile unsigned int*)(0x42600080UL))
+#define bFM3_EXTI_EIRR_ER1                     *((volatile unsigned int*)(0x42600084UL))
+#define bFM3_EXTI_EIRR_ER2                     *((volatile unsigned int*)(0x42600088UL))
+#define bFM3_EXTI_EIRR_ER3                     *((volatile unsigned int*)(0x4260008CUL))
+#define bFM3_EXTI_EIRR_ER4                     *((volatile unsigned int*)(0x42600090UL))
+#define bFM3_EXTI_EIRR_ER5                     *((volatile unsigned int*)(0x42600094UL))
+#define bFM3_EXTI_EIRR_ER6                     *((volatile unsigned int*)(0x42600098UL))
+#define bFM3_EXTI_EIRR_ER7                     *((volatile unsigned int*)(0x4260009CUL))
+#define bFM3_EXTI_EIRR_ER8                     *((volatile unsigned int*)(0x426000A0UL))
+#define bFM3_EXTI_EIRR_ER9                     *((volatile unsigned int*)(0x426000A4UL))
+#define bFM3_EXTI_EIRR_ER10                    *((volatile unsigned int*)(0x426000A8UL))
+#define bFM3_EXTI_EIRR_ER11                    *((volatile unsigned int*)(0x426000ACUL))
+#define bFM3_EXTI_EIRR_ER12                    *((volatile unsigned int*)(0x426000B0UL))
+#define bFM3_EXTI_EIRR_ER13                    *((volatile unsigned int*)(0x426000B4UL))
+#define bFM3_EXTI_EIRR_ER14                    *((volatile unsigned int*)(0x426000B8UL))
+#define bFM3_EXTI_EIRR_ER15                    *((volatile unsigned int*)(0x426000BCUL))
+#define bFM3_EXTI_EIRR_ER16                    *((volatile unsigned int*)(0x426000C0UL))
+#define bFM3_EXTI_EIRR_ER17                    *((volatile unsigned int*)(0x426000C4UL))
+#define bFM3_EXTI_EIRR_ER18                    *((volatile unsigned int*)(0x426000C8UL))
+#define bFM3_EXTI_EIRR_ER19                    *((volatile unsigned int*)(0x426000CCUL))
+#define bFM3_EXTI_EIRR_ER20                    *((volatile unsigned int*)(0x426000D0UL))
+#define bFM3_EXTI_EIRR_ER21                    *((volatile unsigned int*)(0x426000D4UL))
+#define bFM3_EXTI_EIRR_ER22                    *((volatile unsigned int*)(0x426000D8UL))
+#define bFM3_EXTI_EIRR_ER23                    *((volatile unsigned int*)(0x426000DCUL))
+#define bFM3_EXTI_EIRR_ER24                    *((volatile unsigned int*)(0x426000E0UL))
+#define bFM3_EXTI_EIRR_ER25                    *((volatile unsigned int*)(0x426000E4UL))
+#define bFM3_EXTI_EIRR_ER26                    *((volatile unsigned int*)(0x426000E8UL))
+#define bFM3_EXTI_EIRR_ER27                    *((volatile unsigned int*)(0x426000ECUL))
+#define bFM3_EXTI_EIRR_ER28                    *((volatile unsigned int*)(0x426000F0UL))
+#define bFM3_EXTI_EIRR_ER29                    *((volatile unsigned int*)(0x426000F4UL))
+#define bFM3_EXTI_EIRR_ER30                    *((volatile unsigned int*)(0x426000F8UL))
+#define bFM3_EXTI_EIRR_ER31                    *((volatile unsigned int*)(0x426000FCUL))
+#define bFM3_EXTI_EICL_ECL0                    *((volatile unsigned int*)(0x42600100UL))
+#define bFM3_EXTI_EICL_ECL1                    *((volatile unsigned int*)(0x42600104UL))
+#define bFM3_EXTI_EICL_ECL2                    *((volatile unsigned int*)(0x42600108UL))
+#define bFM3_EXTI_EICL_ECL3                    *((volatile unsigned int*)(0x4260010CUL))
+#define bFM3_EXTI_EICL_ECL4                    *((volatile unsigned int*)(0x42600110UL))
+#define bFM3_EXTI_EICL_ECL5                    *((volatile unsigned int*)(0x42600114UL))
+#define bFM3_EXTI_EICL_ECL6                    *((volatile unsigned int*)(0x42600118UL))
+#define bFM3_EXTI_EICL_ECL7                    *((volatile unsigned int*)(0x4260011CUL))
+#define bFM3_EXTI_EICL_ECL8                    *((volatile unsigned int*)(0x42600120UL))
+#define bFM3_EXTI_EICL_ECL9                    *((volatile unsigned int*)(0x42600124UL))
+#define bFM3_EXTI_EICL_ECL10                   *((volatile unsigned int*)(0x42600128UL))
+#define bFM3_EXTI_EICL_ECL11                   *((volatile unsigned int*)(0x4260012CUL))
+#define bFM3_EXTI_EICL_ECL12                   *((volatile unsigned int*)(0x42600130UL))
+#define bFM3_EXTI_EICL_ECL13                   *((volatile unsigned int*)(0x42600134UL))
+#define bFM3_EXTI_EICL_ECL14                   *((volatile unsigned int*)(0x42600138UL))
+#define bFM3_EXTI_EICL_ECL15                   *((volatile unsigned int*)(0x4260013CUL))
+#define bFM3_EXTI_EICL_ECL16                   *((volatile unsigned int*)(0x42600140UL))
+#define bFM3_EXTI_EICL_ECL17                   *((volatile unsigned int*)(0x42600144UL))
+#define bFM3_EXTI_EICL_ECL18                   *((volatile unsigned int*)(0x42600148UL))
+#define bFM3_EXTI_EICL_ECL19                   *((volatile unsigned int*)(0x4260014CUL))
+#define bFM3_EXTI_EICL_ECL20                   *((volatile unsigned int*)(0x42600150UL))
+#define bFM3_EXTI_EICL_ECL21                   *((volatile unsigned int*)(0x42600154UL))
+#define bFM3_EXTI_EICL_ECL22                   *((volatile unsigned int*)(0x42600158UL))
+#define bFM3_EXTI_EICL_ECL23                   *((volatile unsigned int*)(0x4260015CUL))
+#define bFM3_EXTI_EICL_ECL24                   *((volatile unsigned int*)(0x42600160UL))
+#define bFM3_EXTI_EICL_ECL25                   *((volatile unsigned int*)(0x42600164UL))
+#define bFM3_EXTI_EICL_ECL26                   *((volatile unsigned int*)(0x42600168UL))
+#define bFM3_EXTI_EICL_ECL27                   *((volatile unsigned int*)(0x4260016CUL))
+#define bFM3_EXTI_EICL_ECL28                   *((volatile unsigned int*)(0x42600170UL))
+#define bFM3_EXTI_EICL_ECL29                   *((volatile unsigned int*)(0x42600174UL))
+#define bFM3_EXTI_EICL_ECL30                   *((volatile unsigned int*)(0x42600178UL))
+#define bFM3_EXTI_EICL_ECL31                   *((volatile unsigned int*)(0x4260017CUL))
+#define bFM3_EXTI_ELVR_LA0                     *((volatile unsigned int*)(0x42600180UL))
+#define bFM3_EXTI_ELVR_LB0                     *((volatile unsigned int*)(0x42600184UL))
+#define bFM3_EXTI_ELVR_LA1                     *((volatile unsigned int*)(0x42600188UL))
+#define bFM3_EXTI_ELVR_LB1                     *((volatile unsigned int*)(0x4260018CUL))
+#define bFM3_EXTI_ELVR_LA2                     *((volatile unsigned int*)(0x42600190UL))
+#define bFM3_EXTI_ELVR_LB2                     *((volatile unsigned int*)(0x42600194UL))
+#define bFM3_EXTI_ELVR_LA3                     *((volatile unsigned int*)(0x42600198UL))
+#define bFM3_EXTI_ELVR_LB3                     *((volatile unsigned int*)(0x4260019CUL))
+#define bFM3_EXTI_ELVR_LA4                     *((volatile unsigned int*)(0x426001A0UL))
+#define bFM3_EXTI_ELVR_LB4                     *((volatile unsigned int*)(0x426001A4UL))
+#define bFM3_EXTI_ELVR_LA5                     *((volatile unsigned int*)(0x426001A8UL))
+#define bFM3_EXTI_ELVR_LB5                     *((volatile unsigned int*)(0x426001ACUL))
+#define bFM3_EXTI_ELVR_LA6                     *((volatile unsigned int*)(0x426001B0UL))
+#define bFM3_EXTI_ELVR_LB6                     *((volatile unsigned int*)(0x426001B4UL))
+#define bFM3_EXTI_ELVR_LA7                     *((volatile unsigned int*)(0x426001B8UL))
+#define bFM3_EXTI_ELVR_LB7                     *((volatile unsigned int*)(0x426001BCUL))
+#define bFM3_EXTI_ELVR_LA8                     *((volatile unsigned int*)(0x426001C0UL))
+#define bFM3_EXTI_ELVR_LB8                     *((volatile unsigned int*)(0x426001C4UL))
+#define bFM3_EXTI_ELVR_LA9                     *((volatile unsigned int*)(0x426001C8UL))
+#define bFM3_EXTI_ELVR_LB9                     *((volatile unsigned int*)(0x426001CCUL))
+#define bFM3_EXTI_ELVR_LA10                    *((volatile unsigned int*)(0x426001D0UL))
+#define bFM3_EXTI_ELVR_LB10                    *((volatile unsigned int*)(0x426001D4UL))
+#define bFM3_EXTI_ELVR_LA11                    *((volatile unsigned int*)(0x426001D8UL))
+#define bFM3_EXTI_ELVR_LB11                    *((volatile unsigned int*)(0x426001DCUL))
+#define bFM3_EXTI_ELVR_LA12                    *((volatile unsigned int*)(0x426001E0UL))
+#define bFM3_EXTI_ELVR_LB12                    *((volatile unsigned int*)(0x426001E4UL))
+#define bFM3_EXTI_ELVR_LA13                    *((volatile unsigned int*)(0x426001E8UL))
+#define bFM3_EXTI_ELVR_LB13                    *((volatile unsigned int*)(0x426001ECUL))
+#define bFM3_EXTI_ELVR_LA14                    *((volatile unsigned int*)(0x426001F0UL))
+#define bFM3_EXTI_ELVR_LB14                    *((volatile unsigned int*)(0x426001F4UL))
+#define bFM3_EXTI_ELVR_LA15                    *((volatile unsigned int*)(0x426001F8UL))
+#define bFM3_EXTI_ELVR_LB15                    *((volatile unsigned int*)(0x426001FCUL))
+#define bFM3_EXTI_ELVR_LA16                    *((volatile unsigned int*)(0x42600200UL))
+#define bFM3_EXTI_ELVR_LB16                    *((volatile unsigned int*)(0x42600204UL))
+#define bFM3_EXTI_ELVR_LA17                    *((volatile unsigned int*)(0x42600208UL))
+#define bFM3_EXTI_ELVR_LB17                    *((volatile unsigned int*)(0x4260020CUL))
+#define bFM3_EXTI_ELVR_LA18                    *((volatile unsigned int*)(0x42600210UL))
+#define bFM3_EXTI_ELVR_LB18                    *((volatile unsigned int*)(0x42600214UL))
+#define bFM3_EXTI_ELVR_LA19                    *((volatile unsigned int*)(0x42600218UL))
+#define bFM3_EXTI_ELVR_LB19                    *((volatile unsigned int*)(0x4260021CUL))
+#define bFM3_EXTI_ELVR_LA20                    *((volatile unsigned int*)(0x42600220UL))
+#define bFM3_EXTI_ELVR_LB20                    *((volatile unsigned int*)(0x42600224UL))
+#define bFM3_EXTI_ELVR_LA21                    *((volatile unsigned int*)(0x42600228UL))
+#define bFM3_EXTI_ELVR_LB21                    *((volatile unsigned int*)(0x4260022CUL))
+#define bFM3_EXTI_ELVR_LA22                    *((volatile unsigned int*)(0x42600230UL))
+#define bFM3_EXTI_ELVR_LB22                    *((volatile unsigned int*)(0x42600234UL))
+#define bFM3_EXTI_ELVR_LA23                    *((volatile unsigned int*)(0x42600238UL))
+#define bFM3_EXTI_ELVR_LB23                    *((volatile unsigned int*)(0x4260023CUL))
+#define bFM3_EXTI_ELVR_LA24                    *((volatile unsigned int*)(0x42600240UL))
+#define bFM3_EXTI_ELVR_LB24                    *((volatile unsigned int*)(0x42600244UL))
+#define bFM3_EXTI_ELVR_LA25                    *((volatile unsigned int*)(0x42600248UL))
+#define bFM3_EXTI_ELVR_LB25                    *((volatile unsigned int*)(0x4260024CUL))
+#define bFM3_EXTI_ELVR_LA26                    *((volatile unsigned int*)(0x42600250UL))
+#define bFM3_EXTI_ELVR_LB26                    *((volatile unsigned int*)(0x42600254UL))
+#define bFM3_EXTI_ELVR_LA27                    *((volatile unsigned int*)(0x42600258UL))
+#define bFM3_EXTI_ELVR_LB27                    *((volatile unsigned int*)(0x4260025CUL))
+#define bFM3_EXTI_ELVR_LA28                    *((volatile unsigned int*)(0x42600260UL))
+#define bFM3_EXTI_ELVR_LB28                    *((volatile unsigned int*)(0x42600264UL))
+#define bFM3_EXTI_ELVR_LA29                    *((volatile unsigned int*)(0x42600268UL))
+#define bFM3_EXTI_ELVR_LB29                    *((volatile unsigned int*)(0x4260026CUL))
+#define bFM3_EXTI_ELVR_LA30                    *((volatile unsigned int*)(0x42600270UL))
+#define bFM3_EXTI_ELVR_LB30                    *((volatile unsigned int*)(0x42600274UL))
+#define bFM3_EXTI_ELVR_LA31                    *((volatile unsigned int*)(0x42600278UL))
+#define bFM3_EXTI_ELVR_LB31                    *((volatile unsigned int*)(0x4260027CUL))
+#define bFM3_EXTI_NMIRR_NR0                    *((volatile unsigned int*)(0x42600280UL))
+#define bFM3_EXTI_NMICL_NCL0                   *((volatile unsigned int*)(0x42600300UL))
+
+/* Interrupt request read registers */
+#define bFM3_INTREQ_DRQSEL_DRQSEL0             *((volatile unsigned int*)(0x42620000UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL1             *((volatile unsigned int*)(0x42620004UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL2             *((volatile unsigned int*)(0x42620008UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL3             *((volatile unsigned int*)(0x4262000CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL4             *((volatile unsigned int*)(0x42620010UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL5             *((volatile unsigned int*)(0x42620014UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL6             *((volatile unsigned int*)(0x42620018UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL7             *((volatile unsigned int*)(0x4262001CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL8             *((volatile unsigned int*)(0x42620020UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL9             *((volatile unsigned int*)(0x42620024UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL10            *((volatile unsigned int*)(0x42620028UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL11            *((volatile unsigned int*)(0x4262002CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL12            *((volatile unsigned int*)(0x42620030UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL13            *((volatile unsigned int*)(0x42620034UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL14            *((volatile unsigned int*)(0x42620038UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL15            *((volatile unsigned int*)(0x4262003CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL16            *((volatile unsigned int*)(0x42620040UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL17            *((volatile unsigned int*)(0x42620044UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL18            *((volatile unsigned int*)(0x42620048UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL19            *((volatile unsigned int*)(0x4262004CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL20            *((volatile unsigned int*)(0x42620050UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL21            *((volatile unsigned int*)(0x42620054UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL22            *((volatile unsigned int*)(0x42620058UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL23            *((volatile unsigned int*)(0x4262005CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL24            *((volatile unsigned int*)(0x42620060UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL25            *((volatile unsigned int*)(0x42620064UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL26            *((volatile unsigned int*)(0x42620068UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL27            *((volatile unsigned int*)(0x4262006CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL28            *((volatile unsigned int*)(0x42620070UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL29            *((volatile unsigned int*)(0x42620074UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL30            *((volatile unsigned int*)(0x42620078UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL31            *((volatile unsigned int*)(0x4262007CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS0             *((volatile unsigned char*)(0x42620160UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS1             *((volatile unsigned char*)(0x42620164UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS2             *((volatile unsigned char*)(0x42620168UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS3             *((volatile unsigned char*)(0x4262016CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS4             *((volatile unsigned char*)(0x42620170UL))
+#define bFM3_INTREQ_EXC02MON_NMI               *((volatile unsigned int*)(0x42620200UL))
+#define bFM3_INTREQ_EXC02MON_HWINT             *((volatile unsigned int*)(0x42620204UL))
+#define bFM3_INTREQ_IRQ00MON_FCSINT            *((volatile unsigned int*)(0x42620280UL))
+#define bFM3_INTREQ_IRQ01MON_SWWDTINT          *((volatile unsigned int*)(0x42620300UL))
+#define bFM3_INTREQ_IRQ02MON_LVDINT            *((volatile unsigned int*)(0x42620380UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT0         *((volatile unsigned int*)(0x42620400UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT1         *((volatile unsigned int*)(0x42620404UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT2         *((volatile unsigned int*)(0x42620408UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT3         *((volatile unsigned int*)(0x4262040CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT0         *((volatile unsigned int*)(0x42620410UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT1         *((volatile unsigned int*)(0x42620414UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT2         *((volatile unsigned int*)(0x42620418UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT3         *((volatile unsigned int*)(0x4262041CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT0         *((volatile unsigned int*)(0x42620420UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT1         *((volatile unsigned int*)(0x42620424UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT2         *((volatile unsigned int*)(0x42620428UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT3         *((volatile unsigned int*)(0x4262042CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT0           *((volatile unsigned int*)(0x42620480UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT1           *((volatile unsigned int*)(0x42620484UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT2           *((volatile unsigned int*)(0x42620488UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT3           *((volatile unsigned int*)(0x4262048CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT4           *((volatile unsigned int*)(0x42620490UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT5           *((volatile unsigned int*)(0x42620494UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT6           *((volatile unsigned int*)(0x42620498UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT7           *((volatile unsigned int*)(0x4262049CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT0           *((volatile unsigned int*)(0x42620500UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT1           *((volatile unsigned int*)(0x42620504UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT2           *((volatile unsigned int*)(0x42620508UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT3           *((volatile unsigned int*)(0x4262050CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT4           *((volatile unsigned int*)(0x42620510UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT5           *((volatile unsigned int*)(0x42620514UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT6           *((volatile unsigned int*)(0x42620518UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT7           *((volatile unsigned int*)(0x4262051CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT8           *((volatile unsigned int*)(0x42620520UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT9           *((volatile unsigned int*)(0x42620524UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT10          *((volatile unsigned int*)(0x42620528UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT11          *((volatile unsigned int*)(0x4262052CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT12          *((volatile unsigned int*)(0x42620530UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT13          *((volatile unsigned int*)(0x42620534UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT14          *((volatile unsigned int*)(0x42620538UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT15          *((volatile unsigned int*)(0x4262053CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT16          *((volatile unsigned int*)(0x42620540UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT17          *((volatile unsigned int*)(0x42620544UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT18          *((volatile unsigned int*)(0x42620548UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT19          *((volatile unsigned int*)(0x4262054CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT20          *((volatile unsigned int*)(0x42620550UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT21          *((volatile unsigned int*)(0x42620554UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT22          *((volatile unsigned int*)(0x42620558UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT23          *((volatile unsigned int*)(0x4262055CUL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT1           *((volatile unsigned int*)(0x42620580UL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT2           *((volatile unsigned int*)(0x42620584UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT0          *((volatile unsigned int*)(0x42620588UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT1          *((volatile unsigned int*)(0x4262058CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT2          *((volatile unsigned int*)(0x42620590UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT3          *((volatile unsigned int*)(0x42620594UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT4          *((volatile unsigned int*)(0x42620598UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT5          *((volatile unsigned int*)(0x4262059CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT0          *((volatile unsigned int*)(0x426205A0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT1          *((volatile unsigned int*)(0x426205A4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT2          *((volatile unsigned int*)(0x426205A8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT3          *((volatile unsigned int*)(0x426205ACUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT4          *((volatile unsigned int*)(0x426205B0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT5          *((volatile unsigned int*)(0x426205B4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT0          *((volatile unsigned int*)(0x426205B8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT1          *((volatile unsigned int*)(0x426205BCUL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT2          *((volatile unsigned int*)(0x426205C0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT3          *((volatile unsigned int*)(0x426205C4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT4          *((volatile unsigned int*)(0x426205C8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT5          *((volatile unsigned int*)(0x426205CCUL))
+#define bFM3_INTREQ_IRQ07MON_FMSINT            *((volatile unsigned int*)(0x42620600UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT0           *((volatile unsigned int*)(0x42620680UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT1           *((volatile unsigned int*)(0x42620684UL))
+#define bFM3_INTREQ_IRQ09MON_FMSINT            *((volatile unsigned int*)(0x42620700UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT0           *((volatile unsigned int*)(0x42620780UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT1           *((volatile unsigned int*)(0x42620784UL))
+#define bFM3_INTREQ_IRQ11MON_FMSINT            *((volatile unsigned int*)(0x42620800UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT0           *((volatile unsigned int*)(0x42620880UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT1           *((volatile unsigned int*)(0x42620884UL))
+#define bFM3_INTREQ_IRQ13MON_FMSINT            *((volatile unsigned int*)(0x42620900UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT0           *((volatile unsigned int*)(0x42620980UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT1           *((volatile unsigned int*)(0x42620984UL))
+#define bFM3_INTREQ_IRQ15MON_FMSINT            *((volatile unsigned int*)(0x42620A00UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT0           *((volatile unsigned int*)(0x42620A80UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT1           *((volatile unsigned int*)(0x42620A84UL))
+#define bFM3_INTREQ_IRQ17MON_FMSINT            *((volatile unsigned int*)(0x42620B00UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT0           *((volatile unsigned int*)(0x42620B80UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT1           *((volatile unsigned int*)(0x42620B84UL))
+#define bFM3_INTREQ_IRQ19MON_FMSINT            *((volatile unsigned int*)(0x42620C00UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT0           *((volatile unsigned int*)(0x42620C80UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT1           *((volatile unsigned int*)(0x42620C84UL))
+#define bFM3_INTREQ_IRQ21MON_FMSINT            *((volatile unsigned int*)(0x42620D00UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT0           *((volatile unsigned int*)(0x42620D80UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT1           *((volatile unsigned int*)(0x42620D84UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT0           *((volatile unsigned int*)(0x42620E00UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT1           *((volatile unsigned int*)(0x42620E04UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT2           *((volatile unsigned int*)(0x42620E08UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT3           *((volatile unsigned int*)(0x42620E0CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT4           *((volatile unsigned int*)(0x42620E10UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT5           *((volatile unsigned int*)(0x42620E14UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT6           *((volatile unsigned int*)(0x42620E18UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT7           *((volatile unsigned int*)(0x42620E1CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT8           *((volatile unsigned int*)(0x42620E20UL))
+#define bFM3_INTREQ_IRQ24MON_MOSCINT           *((volatile unsigned int*)(0x42620E80UL))
+#define bFM3_INTREQ_IRQ24MON_SOSCINT           *((volatile unsigned int*)(0x42620E84UL))
+#define bFM3_INTREQ_IRQ24MON_MPLLINT           *((volatile unsigned int*)(0x42620E88UL))
+#define bFM3_INTREQ_IRQ24MON_UPLLINT           *((volatile unsigned int*)(0x42620E8CUL))
+#define bFM3_INTREQ_IRQ24MON_WCINT             *((volatile unsigned int*)(0x42620E90UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT0           *((volatile unsigned int*)(0x42620F00UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT1           *((volatile unsigned int*)(0x42620F04UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT2           *((volatile unsigned int*)(0x42620F08UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT3           *((volatile unsigned int*)(0x42620F0CUL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT0           *((volatile unsigned int*)(0x42620F80UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT1           *((volatile unsigned int*)(0x42620F84UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT2           *((volatile unsigned int*)(0x42620F88UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT3           *((volatile unsigned int*)(0x42620F8CUL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT0           *((volatile unsigned int*)(0x42621000UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT1           *((volatile unsigned int*)(0x42621004UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT2           *((volatile unsigned int*)(0x42621008UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT3           *((volatile unsigned int*)(0x4262100CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT0          *((volatile unsigned int*)(0x42621080UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT1          *((volatile unsigned int*)(0x42621084UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT2          *((volatile unsigned int*)(0x42621088UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT3          *((volatile unsigned int*)(0x4262108CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT4          *((volatile unsigned int*)(0x42621090UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT5          *((volatile unsigned int*)(0x42621094UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT0          *((volatile unsigned int*)(0x42621098UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT1          *((volatile unsigned int*)(0x4262109CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT2          *((volatile unsigned int*)(0x426210A0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT3          *((volatile unsigned int*)(0x426210A4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT4          *((volatile unsigned int*)(0x426210A8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT5          *((volatile unsigned int*)(0x426210ACUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT0          *((volatile unsigned int*)(0x426210B0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT1          *((volatile unsigned int*)(0x426210B4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT2          *((volatile unsigned int*)(0x426210B8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT3          *((volatile unsigned int*)(0x426210BCUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT4          *((volatile unsigned int*)(0x426210C0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT5          *((volatile unsigned int*)(0x426210C4UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT0          *((volatile unsigned int*)(0x42621100UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT1          *((volatile unsigned int*)(0x42621104UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT2          *((volatile unsigned int*)(0x42621108UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT3          *((volatile unsigned int*)(0x4262110CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT0          *((volatile unsigned int*)(0x42621110UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT1          *((volatile unsigned int*)(0x42621114UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT2          *((volatile unsigned int*)(0x42621118UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT3          *((volatile unsigned int*)(0x4262111CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT0          *((volatile unsigned int*)(0x42621120UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT1          *((volatile unsigned int*)(0x42621124UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT2          *((volatile unsigned int*)(0x42621128UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT3          *((volatile unsigned int*)(0x4262112CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT0          *((volatile unsigned int*)(0x42621180UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT1          *((volatile unsigned int*)(0x42621184UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT2          *((volatile unsigned int*)(0x42621188UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT3          *((volatile unsigned int*)(0x4262118CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT4          *((volatile unsigned int*)(0x42621190UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT5          *((volatile unsigned int*)(0x42621194UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT0          *((volatile unsigned int*)(0x42621198UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT1          *((volatile unsigned int*)(0x4262119CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT2          *((volatile unsigned int*)(0x426211A0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT3          *((volatile unsigned int*)(0x426211A4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT4          *((volatile unsigned int*)(0x426211A8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT5          *((volatile unsigned int*)(0x426211ACUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT0          *((volatile unsigned int*)(0x426211B0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT1          *((volatile unsigned int*)(0x426211B4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT2          *((volatile unsigned int*)(0x426211B8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT3          *((volatile unsigned int*)(0x426211BCUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT4          *((volatile unsigned int*)(0x426211C0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT5          *((volatile unsigned int*)(0x426211C4UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT0            *((volatile unsigned int*)(0x42621200UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT1            *((volatile unsigned int*)(0x42621204UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT2            *((volatile unsigned int*)(0x42621208UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT3            *((volatile unsigned int*)(0x4262120CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT4            *((volatile unsigned int*)(0x42621210UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT5            *((volatile unsigned int*)(0x42621214UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT6            *((volatile unsigned int*)(0x42621218UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT7            *((volatile unsigned int*)(0x4262121CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT8            *((volatile unsigned int*)(0x42621220UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT9            *((volatile unsigned int*)(0x42621224UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT10           *((volatile unsigned int*)(0x42621228UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT11           *((volatile unsigned int*)(0x4262122CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT12           *((volatile unsigned int*)(0x42621230UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT13           *((volatile unsigned int*)(0x42621234UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT14           *((volatile unsigned int*)(0x42621238UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT15           *((volatile unsigned int*)(0x4262123CUL))
+#define bFM3_INTREQ_IRQ32MON_MAC0SBD           *((volatile unsigned int*)(0x42621284UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0PMI           *((volatile unsigned int*)(0x42621288UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0LPI           *((volatile unsigned int*)(0x4262128CUL))
+#define bFM3_INTREQ_IRQ33MON_MAC1SBD           *((volatile unsigned int*)(0x42621304UL))
+#define bFM3_INTREQ_IRQ33MON_MAC1PMI           *((volatile unsigned int*)(0x42621308UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT0          *((volatile unsigned int*)(0x42621380UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT1          *((volatile unsigned int*)(0x42621384UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT2          *((volatile unsigned int*)(0x42621388UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT3          *((volatile unsigned int*)(0x4262138CUL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT4          *((volatile unsigned int*)(0x42621390UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT0          *((volatile unsigned int*)(0x42621400UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT1          *((volatile unsigned int*)(0x42621404UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT2          *((volatile unsigned int*)(0x42621408UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT3          *((volatile unsigned int*)(0x4262140CUL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT4          *((volatile unsigned int*)(0x42621410UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT5          *((volatile unsigned int*)(0x42621414UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT0          *((volatile unsigned int*)(0x42621480UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT1          *((volatile unsigned int*)(0x42621484UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT2          *((volatile unsigned int*)(0x42621488UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT3          *((volatile unsigned int*)(0x4262148CUL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT4          *((volatile unsigned int*)(0x42621490UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT0          *((volatile unsigned int*)(0x42621500UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT1          *((volatile unsigned int*)(0x42621504UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT2          *((volatile unsigned int*)(0x42621508UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT3          *((volatile unsigned int*)(0x4262150CUL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT4          *((volatile unsigned int*)(0x42621510UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT5          *((volatile unsigned int*)(0x42621514UL))
+#define bFM3_INTREQ_IRQ38MON_DMAINT            *((volatile unsigned int*)(0x42621580UL))
+#define bFM3_INTREQ_IRQ39MON_DMAINT            *((volatile unsigned int*)(0x42621600UL))
+#define bFM3_INTREQ_IRQ40MON_DMAINT            *((volatile unsigned int*)(0x42621680UL))
+#define bFM3_INTREQ_IRQ41MON_DMAINT            *((volatile unsigned int*)(0x42621700UL))
+#define bFM3_INTREQ_IRQ42MON_DMAINT            *((volatile unsigned int*)(0x42621780UL))
+#define bFM3_INTREQ_IRQ43MON_DMAINT            *((volatile unsigned int*)(0x42621800UL))
+#define bFM3_INTREQ_IRQ44MON_DMAINT            *((volatile unsigned int*)(0x42621880UL))
+#define bFM3_INTREQ_IRQ45MON_DMAINT            *((volatile unsigned int*)(0x42621900UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT0            *((volatile unsigned int*)(0x42621980UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT1            *((volatile unsigned int*)(0x42621984UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT2            *((volatile unsigned int*)(0x42621988UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT3            *((volatile unsigned int*)(0x4262198CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT4            *((volatile unsigned int*)(0x42621990UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT5            *((volatile unsigned int*)(0x42621994UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT6            *((volatile unsigned int*)(0x42621998UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT7            *((volatile unsigned int*)(0x4262199CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT8            *((volatile unsigned int*)(0x426219A0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT9            *((volatile unsigned int*)(0x426219A4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT10           *((volatile unsigned int*)(0x426219A8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT11           *((volatile unsigned int*)(0x426219ACUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT12           *((volatile unsigned int*)(0x426219B0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT13           *((volatile unsigned int*)(0x426219B4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT14           *((volatile unsigned int*)(0x426219B8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT15           *((volatile unsigned int*)(0x426219BCUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL10           *((volatile unsigned int*)(0x42624000UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL11           *((volatile unsigned int*)(0x42624004UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL12           *((volatile unsigned int*)(0x42624008UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL13           *((volatile unsigned int*)(0x4262400CUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL14           *((volatile unsigned int*)(0x42624010UL))
+#define bFM3_INTREQ_DQESEL_ESEL100             *((volatile unsigned int*)(0x42624080UL))
+#define bFM3_INTREQ_DQESEL_ESEL101             *((volatile unsigned int*)(0x42624084UL))
+#define bFM3_INTREQ_DQESEL_ESEL102             *((volatile unsigned int*)(0x42624088UL))
+#define bFM3_INTREQ_DQESEL_ESEL103             *((volatile unsigned int*)(0x4262408CUL))
+#define bFM3_INTREQ_DQESEL_ESEL110             *((volatile unsigned int*)(0x42624090UL))
+#define bFM3_INTREQ_DQESEL_ESEL111             *((volatile unsigned int*)(0x42624094UL))
+#define bFM3_INTREQ_DQESEL_ESEL112             *((volatile unsigned int*)(0x42624098UL))
+#define bFM3_INTREQ_DQESEL_ESEL113             *((volatile unsigned int*)(0x4262409CUL))
+#define bFM3_INTREQ_DQESEL_ESEL240             *((volatile unsigned int*)(0x426240A0UL))
+#define bFM3_INTREQ_DQESEL_ESEL241             *((volatile unsigned int*)(0x426240A4UL))
+#define bFM3_INTREQ_DQESEL_ESEL242             *((volatile unsigned int*)(0x426240A8UL))
+#define bFM3_INTREQ_DQESEL_ESEL243             *((volatile unsigned int*)(0x426240ACUL))
+#define bFM3_INTREQ_DQESEL_ESEL250             *((volatile unsigned int*)(0x426240B0UL))
+#define bFM3_INTREQ_DQESEL_ESEL251             *((volatile unsigned int*)(0x426240B4UL))
+#define bFM3_INTREQ_DQESEL_ESEL252             *((volatile unsigned int*)(0x426240B8UL))
+#define bFM3_INTREQ_DQESEL_ESEL253             *((volatile unsigned int*)(0x426240BCUL))
+#define bFM3_INTREQ_DQESEL_ESEL260             *((volatile unsigned int*)(0x426240C0UL))
+#define bFM3_INTREQ_DQESEL_ESEL261             *((volatile unsigned int*)(0x426240C4UL))
+#define bFM3_INTREQ_DQESEL_ESEL262             *((volatile unsigned int*)(0x426240C8UL))
+#define bFM3_INTREQ_DQESEL_ESEL263             *((volatile unsigned int*)(0x426240CCUL))
+#define bFM3_INTREQ_DQESEL_ESEL270             *((volatile unsigned int*)(0x426240D0UL))
+#define bFM3_INTREQ_DQESEL_ESEL271             *((volatile unsigned int*)(0x426240D4UL))
+#define bFM3_INTREQ_DQESEL_ESEL272             *((volatile unsigned int*)(0x426240D8UL))
+#define bFM3_INTREQ_DQESEL_ESEL273             *((volatile unsigned int*)(0x426240DCUL))
+#define bFM3_INTREQ_DQESEL_ESEL300             *((volatile unsigned int*)(0x426240E0UL))
+#define bFM3_INTREQ_DQESEL_ESEL301             *((volatile unsigned int*)(0x426240E4UL))
+#define bFM3_INTREQ_DQESEL_ESEL302             *((volatile unsigned int*)(0x426240E8UL))
+#define bFM3_INTREQ_DQESEL_ESEL303             *((volatile unsigned int*)(0x426240ECUL))
+#define bFM3_INTREQ_DQESEL_ESEL310             *((volatile unsigned int*)(0x426240F0UL))
+#define bFM3_INTREQ_DQESEL_ESEL311             *((volatile unsigned int*)(0x426240F4UL))
+#define bFM3_INTREQ_DQESEL_ESEL312             *((volatile unsigned int*)(0x426240F8UL))
+#define bFM3_INTREQ_DQESEL_ESEL313             *((volatile unsigned int*)(0x426240FCUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS10           *((volatile unsigned char*)(0x426241E0UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS11           *((volatile unsigned char*)(0x426241E4UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS12           *((volatile unsigned char*)(0x426241E8UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS13           *((volatile unsigned char*)(0x426241ECUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS14           *((volatile unsigned char*)(0x426241F0UL))
+
+/* General purpose I/O registers */
+#define bFM3_GPIO_PFR0_P0                      *((volatile unsigned int*)(0x42660000UL))
+#define bFM3_GPIO_PFR0_P1                      *((volatile unsigned int*)(0x42660004UL))
+#define bFM3_GPIO_PFR0_P2                      *((volatile unsigned int*)(0x42660008UL))
+#define bFM3_GPIO_PFR0_P3                      *((volatile unsigned int*)(0x4266000CUL))
+#define bFM3_GPIO_PFR0_P4                      *((volatile unsigned int*)(0x42660010UL))
+#define bFM3_GPIO_PFR0_P5                      *((volatile unsigned int*)(0x42660014UL))
+#define bFM3_GPIO_PFR0_P6                      *((volatile unsigned int*)(0x42660018UL))
+#define bFM3_GPIO_PFR0_P7                      *((volatile unsigned int*)(0x4266001CUL))
+#define bFM3_GPIO_PFR0_P8                      *((volatile unsigned int*)(0x42660020UL))
+#define bFM3_GPIO_PFR0_P9                      *((volatile unsigned int*)(0x42660024UL))
+#define bFM3_GPIO_PFR1_P0                      *((volatile unsigned int*)(0x42660080UL))
+#define bFM3_GPIO_PFR1_P1                      *((volatile unsigned int*)(0x42660084UL))
+#define bFM3_GPIO_PFR1_P2                      *((volatile unsigned int*)(0x42660088UL))
+#define bFM3_GPIO_PFR1_P3                      *((volatile unsigned int*)(0x4266008CUL))
+#define bFM3_GPIO_PFR1_P4                      *((volatile unsigned int*)(0x42660090UL))
+#define bFM3_GPIO_PFR1_P5                      *((volatile unsigned int*)(0x42660094UL))
+#define bFM3_GPIO_PFR1_P6                      *((volatile unsigned int*)(0x42660098UL))
+#define bFM3_GPIO_PFR1_P7                      *((volatile unsigned int*)(0x4266009CUL))
+#define bFM3_GPIO_PFR1_P8                      *((volatile unsigned int*)(0x426600A0UL))
+#define bFM3_GPIO_PFR1_P9                      *((volatile unsigned int*)(0x426600A4UL))
+#define bFM3_GPIO_PFR1_PA                      *((volatile unsigned int*)(0x426600A8UL))
+#define bFM3_GPIO_PFR1_PB                      *((volatile unsigned int*)(0x426600ACUL))
+#define bFM3_GPIO_PFR1_PC                      *((volatile unsigned int*)(0x426600B0UL))
+#define bFM3_GPIO_PFR1_PD                      *((volatile unsigned int*)(0x426600B4UL))
+#define bFM3_GPIO_PFR1_PE                      *((volatile unsigned int*)(0x426600B8UL))
+#define bFM3_GPIO_PFR1_PF                      *((volatile unsigned int*)(0x426600BCUL))
+#define bFM3_GPIO_PFR2_P0                      *((volatile unsigned int*)(0x42660100UL))
+#define bFM3_GPIO_PFR2_P1                      *((volatile unsigned int*)(0x42660104UL))
+#define bFM3_GPIO_PFR2_P2                      *((volatile unsigned int*)(0x42660108UL))
+#define bFM3_GPIO_PFR2_P3                      *((volatile unsigned int*)(0x4266010CUL))
+#define bFM3_GPIO_PFR2_P4                      *((volatile unsigned int*)(0x42660110UL))
+#define bFM3_GPIO_PFR2_P5                      *((volatile unsigned int*)(0x42660114UL))
+#define bFM3_GPIO_PFR2_P6                      *((volatile unsigned int*)(0x42660118UL))
+#define bFM3_GPIO_PFR2_P7                      *((volatile unsigned int*)(0x4266011CUL))
+#define bFM3_GPIO_PFR2_P8                      *((volatile unsigned int*)(0x42660120UL))
+#define bFM3_GPIO_PFR2_P9                      *((volatile unsigned int*)(0x42660124UL))
+#define bFM3_GPIO_PFR3_P0                      *((volatile unsigned int*)(0x42660180UL))
+#define bFM3_GPIO_PFR3_P1                      *((volatile unsigned int*)(0x42660184UL))
+#define bFM3_GPIO_PFR3_P2                      *((volatile unsigned int*)(0x42660188UL))
+#define bFM3_GPIO_PFR3_P3                      *((volatile unsigned int*)(0x4266018CUL))
+#define bFM3_GPIO_PFR3_P4                      *((volatile unsigned int*)(0x42660190UL))
+#define bFM3_GPIO_PFR3_P5                      *((volatile unsigned int*)(0x42660194UL))
+#define bFM3_GPIO_PFR3_P6                      *((volatile unsigned int*)(0x42660198UL))
+#define bFM3_GPIO_PFR3_P7                      *((volatile unsigned int*)(0x4266019CUL))
+#define bFM3_GPIO_PFR3_P8                      *((volatile unsigned int*)(0x426601A0UL))
+#define bFM3_GPIO_PFR3_P9                      *((volatile unsigned int*)(0x426601A4UL))
+#define bFM3_GPIO_PFR3_PA                      *((volatile unsigned int*)(0x426601A8UL))
+#define bFM3_GPIO_PFR3_PB                      *((volatile unsigned int*)(0x426601ACUL))
+#define bFM3_GPIO_PFR3_PC                      *((volatile unsigned int*)(0x426601B0UL))
+#define bFM3_GPIO_PFR3_PD                      *((volatile unsigned int*)(0x426601B4UL))
+#define bFM3_GPIO_PFR3_PE                      *((volatile unsigned int*)(0x426601B8UL))
+#define bFM3_GPIO_PFR3_PF                      *((volatile unsigned int*)(0x426601BCUL))
+#define bFM3_GPIO_PFR4_P0                      *((volatile unsigned int*)(0x42660200UL))
+#define bFM3_GPIO_PFR4_P1                      *((volatile unsigned int*)(0x42660204UL))
+#define bFM3_GPIO_PFR4_P2                      *((volatile unsigned int*)(0x42660208UL))
+#define bFM3_GPIO_PFR4_P3                      *((volatile unsigned int*)(0x4266020CUL))
+#define bFM3_GPIO_PFR4_P4                      *((volatile unsigned int*)(0x42660210UL))
+#define bFM3_GPIO_PFR4_P5                      *((volatile unsigned int*)(0x42660214UL))
+#define bFM3_GPIO_PFR4_P6                      *((volatile unsigned int*)(0x42660218UL))
+#define bFM3_GPIO_PFR4_P7                      *((volatile unsigned int*)(0x4266021CUL))
+#define bFM3_GPIO_PFR4_P8                      *((volatile unsigned int*)(0x42660220UL))
+#define bFM3_GPIO_PFR4_P9                      *((volatile unsigned int*)(0x42660224UL))
+#define bFM3_GPIO_PFR4_PA                      *((volatile unsigned int*)(0x42660228UL))
+#define bFM3_GPIO_PFR4_PB                      *((volatile unsigned int*)(0x4266022CUL))
+#define bFM3_GPIO_PFR4_PC                      *((volatile unsigned int*)(0x42660230UL))
+#define bFM3_GPIO_PFR4_PD                      *((volatile unsigned int*)(0x42660234UL))
+#define bFM3_GPIO_PFR4_PE                      *((volatile unsigned int*)(0x42660238UL))
+#define bFM3_GPIO_PFR5_P0                      *((volatile unsigned int*)(0x42660280UL))
+#define bFM3_GPIO_PFR5_P1                      *((volatile unsigned int*)(0x42660284UL))
+#define bFM3_GPIO_PFR5_P2                      *((volatile unsigned int*)(0x42660288UL))
+#define bFM3_GPIO_PFR5_P3                      *((volatile unsigned int*)(0x4266028CUL))
+#define bFM3_GPIO_PFR5_P4                      *((volatile unsigned int*)(0x42660290UL))
+#define bFM3_GPIO_PFR5_P5                      *((volatile unsigned int*)(0x42660294UL))
+#define bFM3_GPIO_PFR5_P6                      *((volatile unsigned int*)(0x42660298UL))
+#define bFM3_GPIO_PFR5_P7                      *((volatile unsigned int*)(0x4266029CUL))
+#define bFM3_GPIO_PFR5_P8                      *((volatile unsigned int*)(0x426602A0UL))
+#define bFM3_GPIO_PFR5_P9                      *((volatile unsigned int*)(0x426602A4UL))
+#define bFM3_GPIO_PFR5_PA                      *((volatile unsigned int*)(0x426602A8UL))
+#define bFM3_GPIO_PFR5_PB                      *((volatile unsigned int*)(0x426602ACUL))
+#define bFM3_GPIO_PFR5_PC                      *((volatile unsigned int*)(0x426602B0UL))
+#define bFM3_GPIO_PFR5_PD                      *((volatile unsigned int*)(0x426602B4UL))
+#define bFM3_GPIO_PFR6_P0                      *((volatile unsigned int*)(0x42660300UL))
+#define bFM3_GPIO_PFR6_P1                      *((volatile unsigned int*)(0x42660304UL))
+#define bFM3_GPIO_PFR6_P2                      *((volatile unsigned int*)(0x42660308UL))
+#define bFM3_GPIO_PFR7_P0                      *((volatile unsigned int*)(0x42660380UL))
+#define bFM3_GPIO_PFR7_P1                      *((volatile unsigned int*)(0x42660384UL))
+#define bFM3_GPIO_PFR7_P2                      *((volatile unsigned int*)(0x42660388UL))
+#define bFM3_GPIO_PFR7_P3                      *((volatile unsigned int*)(0x4266038CUL))
+#define bFM3_GPIO_PFR7_P4                      *((volatile unsigned int*)(0x42660390UL))
+#define bFM3_GPIO_PFR7_P5                      *((volatile unsigned int*)(0x42660394UL))
+#define bFM3_GPIO_PFR7_P6                      *((volatile unsigned int*)(0x42660398UL))
+#define bFM3_GPIO_PFR7_P7                      *((volatile unsigned int*)(0x4266039CUL))
+#define bFM3_GPIO_PFR7_P8                      *((volatile unsigned int*)(0x426603A0UL))
+#define bFM3_GPIO_PFR7_P9                      *((volatile unsigned int*)(0x426603A4UL))
+#define bFM3_GPIO_PFR7_PA                      *((volatile unsigned int*)(0x426603A8UL))
+#define bFM3_GPIO_PFR7_PB                      *((volatile unsigned int*)(0x426603ACUL))
+#define bFM3_GPIO_PFR7_PC                      *((volatile unsigned int*)(0x426603B0UL))
+#define bFM3_GPIO_PFR7_PD                      *((volatile unsigned int*)(0x426603B4UL))
+#define bFM3_GPIO_PFR7_PE                      *((volatile unsigned int*)(0x426603B8UL))
+#define bFM3_GPIO_PFR7_PF                      *((volatile unsigned int*)(0x426603BCUL))
+#define bFM3_GPIO_PFR8_P0                      *((volatile unsigned int*)(0x42660400UL))
+#define bFM3_GPIO_PFR8_P1                      *((volatile unsigned int*)(0x42660404UL))
+#define bFM3_GPIO_PFR8_P2                      *((volatile unsigned int*)(0x42660408UL))
+#define bFM3_GPIO_PFR8_P3                      *((volatile unsigned int*)(0x4266040CUL))
+#define bFM3_GPIO_PFR9_P0                      *((volatile unsigned int*)(0x42660480UL))
+#define bFM3_GPIO_PFR9_P1                      *((volatile unsigned int*)(0x42660484UL))
+#define bFM3_GPIO_PFR9_P2                      *((volatile unsigned int*)(0x42660488UL))
+#define bFM3_GPIO_PFR9_P3                      *((volatile unsigned int*)(0x4266048CUL))
+#define bFM3_GPIO_PFR9_P4                      *((volatile unsigned int*)(0x42660490UL))
+#define bFM3_GPIO_PFR9_P5                      *((volatile unsigned int*)(0x42660494UL))
+#define bFM3_GPIO_PFRA_P0                      *((volatile unsigned int*)(0x42660500UL))
+#define bFM3_GPIO_PFRA_P1                      *((volatile unsigned int*)(0x42660504UL))
+#define bFM3_GPIO_PFRA_P2                      *((volatile unsigned int*)(0x42660508UL))
+#define bFM3_GPIO_PFRA_P3                      *((volatile unsigned int*)(0x4266050CUL))
+#define bFM3_GPIO_PFRA_P4                      *((volatile unsigned int*)(0x42660510UL))
+#define bFM3_GPIO_PFRA_P5                      *((volatile unsigned int*)(0x42660514UL))
+#define bFM3_GPIO_PFRB_P0                      *((volatile unsigned int*)(0x42660580UL))
+#define bFM3_GPIO_PFRB_P1                      *((volatile unsigned int*)(0x42660584UL))
+#define bFM3_GPIO_PFRB_P2                      *((volatile unsigned int*)(0x42660588UL))
+#define bFM3_GPIO_PFRB_P3                      *((volatile unsigned int*)(0x4266058CUL))
+#define bFM3_GPIO_PFRB_P4                      *((volatile unsigned int*)(0x42660590UL))
+#define bFM3_GPIO_PFRB_P5                      *((volatile unsigned int*)(0x42660594UL))
+#define bFM3_GPIO_PFRB_P6                      *((volatile unsigned int*)(0x42660598UL))
+#define bFM3_GPIO_PFRB_P7                      *((volatile unsigned int*)(0x4266059CUL))
+#define bFM3_GPIO_PFRC_P0                      *((volatile unsigned int*)(0x42660600UL))
+#define bFM3_GPIO_PFRC_P1                      *((volatile unsigned int*)(0x42660604UL))
+#define bFM3_GPIO_PFRC_P2                      *((volatile unsigned int*)(0x42660608UL))
+#define bFM3_GPIO_PFRC_P3                      *((volatile unsigned int*)(0x4266060CUL))
+#define bFM3_GPIO_PFRC_P4                      *((volatile unsigned int*)(0x42660610UL))
+#define bFM3_GPIO_PFRC_P5                      *((volatile unsigned int*)(0x42660614UL))
+#define bFM3_GPIO_PFRC_P6                      *((volatile unsigned int*)(0x42660618UL))
+#define bFM3_GPIO_PFRC_P7                      *((volatile unsigned int*)(0x4266061CUL))
+#define bFM3_GPIO_PFRC_P8                      *((volatile unsigned int*)(0x42660620UL))
+#define bFM3_GPIO_PFRC_P9                      *((volatile unsigned int*)(0x42660624UL))
+#define bFM3_GPIO_PFRC_PA                      *((volatile unsigned int*)(0x42660628UL))
+#define bFM3_GPIO_PFRC_PB                      *((volatile unsigned int*)(0x4266062CUL))
+#define bFM3_GPIO_PFRC_PC                      *((volatile unsigned int*)(0x42660630UL))
+#define bFM3_GPIO_PFRC_PD                      *((volatile unsigned int*)(0x42660634UL))
+#define bFM3_GPIO_PFRC_PE                      *((volatile unsigned int*)(0x42660638UL))
+#define bFM3_GPIO_PFRC_PF                      *((volatile unsigned int*)(0x4266063CUL))
+#define bFM3_GPIO_PFRD_P0                      *((volatile unsigned int*)(0x42660680UL))
+#define bFM3_GPIO_PFRD_P1                      *((volatile unsigned int*)(0x42660684UL))
+#define bFM3_GPIO_PFRD_P2                      *((volatile unsigned int*)(0x42660688UL))
+#define bFM3_GPIO_PFRD_P3                      *((volatile unsigned int*)(0x4266068CUL))
+#define bFM3_GPIO_PFRE_P0                      *((volatile unsigned int*)(0x42660700UL))
+#define bFM3_GPIO_PFRE_P2                      *((volatile unsigned int*)(0x42660708UL))
+#define bFM3_GPIO_PFRE_P3                      *((volatile unsigned int*)(0x4266070CUL))
+#define bFM3_GPIO_PFRF_P0                      *((volatile unsigned int*)(0x42660780UL))
+#define bFM3_GPIO_PFRF_P1                      *((volatile unsigned int*)(0x42660784UL))
+#define bFM3_GPIO_PFRF_P2                      *((volatile unsigned int*)(0x42660788UL))
+#define bFM3_GPIO_PFRF_P3                      *((volatile unsigned int*)(0x4266078CUL))
+#define bFM3_GPIO_PFRF_P4                      *((volatile unsigned int*)(0x42660790UL))
+#define bFM3_GPIO_PFRF_P5                      *((volatile unsigned int*)(0x42660794UL))
+#define bFM3_GPIO_PFRF_P6                      *((volatile unsigned int*)(0x42660798UL))
+#define bFM3_GPIO_PCR0_P0                      *((volatile unsigned int*)(0x42662000UL))
+#define bFM3_GPIO_PCR0_P1                      *((volatile unsigned int*)(0x42662004UL))
+#define bFM3_GPIO_PCR0_P2                      *((volatile unsigned int*)(0x42662008UL))
+#define bFM3_GPIO_PCR0_P3                      *((volatile unsigned int*)(0x4266200CUL))
+#define bFM3_GPIO_PCR0_P4                      *((volatile unsigned int*)(0x42662010UL))
+#define bFM3_GPIO_PCR0_P5                      *((volatile unsigned int*)(0x42662014UL))
+#define bFM3_GPIO_PCR0_P6                      *((volatile unsigned int*)(0x42662018UL))
+#define bFM3_GPIO_PCR0_P7                      *((volatile unsigned int*)(0x4266201CUL))
+#define bFM3_GPIO_PCR0_P8                      *((volatile unsigned int*)(0x42662020UL))
+#define bFM3_GPIO_PCR0_P9                      *((volatile unsigned int*)(0x42662024UL))
+#define bFM3_GPIO_PCR1_P0                      *((volatile unsigned int*)(0x42662080UL))
+#define bFM3_GPIO_PCR1_P1                      *((volatile unsigned int*)(0x42662084UL))
+#define bFM3_GPIO_PCR1_P2                      *((volatile unsigned int*)(0x42662088UL))
+#define bFM3_GPIO_PCR1_P3                      *((volatile unsigned int*)(0x4266208CUL))
+#define bFM3_GPIO_PCR1_P4                      *((volatile unsigned int*)(0x42662090UL))
+#define bFM3_GPIO_PCR1_P5                      *((volatile unsigned int*)(0x42662094UL))
+#define bFM3_GPIO_PCR1_P6                      *((volatile unsigned int*)(0x42662098UL))
+#define bFM3_GPIO_PCR1_P7                      *((volatile unsigned int*)(0x4266209CUL))
+#define bFM3_GPIO_PCR1_P8                      *((volatile unsigned int*)(0x426620A0UL))
+#define bFM3_GPIO_PCR1_P9                      *((volatile unsigned int*)(0x426620A4UL))
+#define bFM3_GPIO_PCR1_PA                      *((volatile unsigned int*)(0x426620A8UL))
+#define bFM3_GPIO_PCR1_PB                      *((volatile unsigned int*)(0x426620ACUL))
+#define bFM3_GPIO_PCR1_PC                      *((volatile unsigned int*)(0x426620B0UL))
+#define bFM3_GPIO_PCR1_PD                      *((volatile unsigned int*)(0x426620B4UL))
+#define bFM3_GPIO_PCR1_PE                      *((volatile unsigned int*)(0x426620B8UL))
+#define bFM3_GPIO_PCR1_PF                      *((volatile unsigned int*)(0x426620BCUL))
+#define bFM3_GPIO_PCR2_P0                      *((volatile unsigned int*)(0x42662100UL))
+#define bFM3_GPIO_PCR2_P1                      *((volatile unsigned int*)(0x42662104UL))
+#define bFM3_GPIO_PCR2_P2                      *((volatile unsigned int*)(0x42662108UL))
+#define bFM3_GPIO_PCR2_P3                      *((volatile unsigned int*)(0x4266210CUL))
+#define bFM3_GPIO_PCR2_P4                      *((volatile unsigned int*)(0x42662110UL))
+#define bFM3_GPIO_PCR2_P5                      *((volatile unsigned int*)(0x42662114UL))
+#define bFM3_GPIO_PCR2_P6                      *((volatile unsigned int*)(0x42662118UL))
+#define bFM3_GPIO_PCR2_P7                      *((volatile unsigned int*)(0x4266211CUL))
+#define bFM3_GPIO_PCR2_P8                      *((volatile unsigned int*)(0x42662120UL))
+#define bFM3_GPIO_PCR2_P9                      *((volatile unsigned int*)(0x42662124UL))
+#define bFM3_GPIO_PCR3_P0                      *((volatile unsigned int*)(0x42662180UL))
+#define bFM3_GPIO_PCR3_P1                      *((volatile unsigned int*)(0x42662184UL))
+#define bFM3_GPIO_PCR3_P2                      *((volatile unsigned int*)(0x42662188UL))
+#define bFM3_GPIO_PCR3_P3                      *((volatile unsigned int*)(0x4266218CUL))
+#define bFM3_GPIO_PCR3_P4                      *((volatile unsigned int*)(0x42662190UL))
+#define bFM3_GPIO_PCR3_P5                      *((volatile unsigned int*)(0x42662194UL))
+#define bFM3_GPIO_PCR3_P6                      *((volatile unsigned int*)(0x42662198UL))
+#define bFM3_GPIO_PCR3_P7                      *((volatile unsigned int*)(0x4266219CUL))
+#define bFM3_GPIO_PCR3_P8                      *((volatile unsigned int*)(0x426621A0UL))
+#define bFM3_GPIO_PCR3_P9                      *((volatile unsigned int*)(0x426621A4UL))
+#define bFM3_GPIO_PCR3_PA                      *((volatile unsigned int*)(0x426621A8UL))
+#define bFM3_GPIO_PCR3_PB                      *((volatile unsigned int*)(0x426621ACUL))
+#define bFM3_GPIO_PCR3_PC                      *((volatile unsigned int*)(0x426621B0UL))
+#define bFM3_GPIO_PCR3_PD                      *((volatile unsigned int*)(0x426621B4UL))
+#define bFM3_GPIO_PCR3_PE                      *((volatile unsigned int*)(0x426621B8UL))
+#define bFM3_GPIO_PCR3_PF                      *((volatile unsigned int*)(0x426621BCUL))
+#define bFM3_GPIO_PCR4_P0                      *((volatile unsigned int*)(0x42662200UL))
+#define bFM3_GPIO_PCR4_P1                      *((volatile unsigned int*)(0x42662204UL))
+#define bFM3_GPIO_PCR4_P2                      *((volatile unsigned int*)(0x42662208UL))
+#define bFM3_GPIO_PCR4_P3                      *((volatile unsigned int*)(0x4266220CUL))
+#define bFM3_GPIO_PCR4_P4                      *((volatile unsigned int*)(0x42662210UL))
+#define bFM3_GPIO_PCR4_P5                      *((volatile unsigned int*)(0x42662214UL))
+#define bFM3_GPIO_PCR4_P6                      *((volatile unsigned int*)(0x42662218UL))
+#define bFM3_GPIO_PCR4_P7                      *((volatile unsigned int*)(0x4266221CUL))
+#define bFM3_GPIO_PCR4_P8                      *((volatile unsigned int*)(0x42662220UL))
+#define bFM3_GPIO_PCR4_P9                      *((volatile unsigned int*)(0x42662224UL))
+#define bFM3_GPIO_PCR4_PA                      *((volatile unsigned int*)(0x42662228UL))
+#define bFM3_GPIO_PCR4_PB                      *((volatile unsigned int*)(0x4266222CUL))
+#define bFM3_GPIO_PCR4_PC                      *((volatile unsigned int*)(0x42662230UL))
+#define bFM3_GPIO_PCR4_PD                      *((volatile unsigned int*)(0x42662234UL))
+#define bFM3_GPIO_PCR4_PE                      *((volatile unsigned int*)(0x42662238UL))
+#define bFM3_GPIO_PCR5_P0                      *((volatile unsigned int*)(0x42662280UL))
+#define bFM3_GPIO_PCR5_P1                      *((volatile unsigned int*)(0x42662284UL))
+#define bFM3_GPIO_PCR5_P2                      *((volatile unsigned int*)(0x42662288UL))
+#define bFM3_GPIO_PCR5_P3                      *((volatile unsigned int*)(0x4266228CUL))
+#define bFM3_GPIO_PCR5_P4                      *((volatile unsigned int*)(0x42662290UL))
+#define bFM3_GPIO_PCR5_P5                      *((volatile unsigned int*)(0x42662294UL))
+#define bFM3_GPIO_PCR5_P6                      *((volatile unsigned int*)(0x42662298UL))
+#define bFM3_GPIO_PCR5_P7                      *((volatile unsigned int*)(0x4266229CUL))
+#define bFM3_GPIO_PCR5_P8                      *((volatile unsigned int*)(0x426622A0UL))
+#define bFM3_GPIO_PCR5_P9                      *((volatile unsigned int*)(0x426622A4UL))
+#define bFM3_GPIO_PCR5_PA                      *((volatile unsigned int*)(0x426622A8UL))
+#define bFM3_GPIO_PCR5_PB                      *((volatile unsigned int*)(0x426622ACUL))
+#define bFM3_GPIO_PCR5_PC                      *((volatile unsigned int*)(0x426622B0UL))
+#define bFM3_GPIO_PCR5_PD                      *((volatile unsigned int*)(0x426622B4UL))
+#define bFM3_GPIO_PCR6_P0                      *((volatile unsigned int*)(0x42662300UL))
+#define bFM3_GPIO_PCR6_P1                      *((volatile unsigned int*)(0x42662304UL))
+#define bFM3_GPIO_PCR6_P2                      *((volatile unsigned int*)(0x42662308UL))
+#define bFM3_GPIO_PCR7_P0                      *((volatile unsigned int*)(0x42662380UL))
+#define bFM3_GPIO_PCR7_P1                      *((volatile unsigned int*)(0x42662384UL))
+#define bFM3_GPIO_PCR7_P2                      *((volatile unsigned int*)(0x42662388UL))
+#define bFM3_GPIO_PCR7_P3                      *((volatile unsigned int*)(0x4266238CUL))
+#define bFM3_GPIO_PCR7_P4                      *((volatile unsigned int*)(0x42662390UL))
+#define bFM3_GPIO_PCR7_P5                      *((volatile unsigned int*)(0x42662394UL))
+#define bFM3_GPIO_PCR7_P6                      *((volatile unsigned int*)(0x42662398UL))
+#define bFM3_GPIO_PCR7_P7                      *((volatile unsigned int*)(0x4266239CUL))
+#define bFM3_GPIO_PCR7_P8                      *((volatile unsigned int*)(0x426623A0UL))
+#define bFM3_GPIO_PCR7_P9                      *((volatile unsigned int*)(0x426623A4UL))
+#define bFM3_GPIO_PCR7_PA                      *((volatile unsigned int*)(0x426623A8UL))
+#define bFM3_GPIO_PCR7_PB                      *((volatile unsigned int*)(0x426623ACUL))
+#define bFM3_GPIO_PCR7_PC                      *((volatile unsigned int*)(0x426623B0UL))
+#define bFM3_GPIO_PCR7_PD                      *((volatile unsigned int*)(0x426623B4UL))
+#define bFM3_GPIO_PCR7_PE                      *((volatile unsigned int*)(0x426623B8UL))
+#define bFM3_GPIO_PCR7_PF                      *((volatile unsigned int*)(0x426623BCUL))
+#define bFM3_GPIO_PCR9_P0                      *((volatile unsigned int*)(0x42662480UL))
+#define bFM3_GPIO_PCR9_P1                      *((volatile unsigned int*)(0x42662484UL))
+#define bFM3_GPIO_PCR9_P2                      *((volatile unsigned int*)(0x42662488UL))
+#define bFM3_GPIO_PCR9_P3                      *((volatile unsigned int*)(0x4266248CUL))
+#define bFM3_GPIO_PCR9_P4                      *((volatile unsigned int*)(0x42662490UL))
+#define bFM3_GPIO_PCR9_P5                      *((volatile unsigned int*)(0x42662494UL))
+#define bFM3_GPIO_PCRA_P0                      *((volatile unsigned int*)(0x42662500UL))
+#define bFM3_GPIO_PCRA_P1                      *((volatile unsigned int*)(0x42662504UL))
+#define bFM3_GPIO_PCRA_P2                      *((volatile unsigned int*)(0x42662508UL))
+#define bFM3_GPIO_PCRA_P3                      *((volatile unsigned int*)(0x4266250CUL))
+#define bFM3_GPIO_PCRA_P4                      *((volatile unsigned int*)(0x42662510UL))
+#define bFM3_GPIO_PCRA_P5                      *((volatile unsigned int*)(0x42662514UL))
+#define bFM3_GPIO_PCRB_P0                      *((volatile unsigned int*)(0x42662580UL))
+#define bFM3_GPIO_PCRB_P1                      *((volatile unsigned int*)(0x42662584UL))
+#define bFM3_GPIO_PCRB_P2                      *((volatile unsigned int*)(0x42662588UL))
+#define bFM3_GPIO_PCRB_P3                      *((volatile unsigned int*)(0x4266258CUL))
+#define bFM3_GPIO_PCRB_P4                      *((volatile unsigned int*)(0x42662590UL))
+#define bFM3_GPIO_PCRB_P5                      *((volatile unsigned int*)(0x42662594UL))
+#define bFM3_GPIO_PCRB_P6                      *((volatile unsigned int*)(0x42662598UL))
+#define bFM3_GPIO_PCRB_P7                      *((volatile unsigned int*)(0x4266259CUL))
+#define bFM3_GPIO_PCRC_P0                      *((volatile unsigned int*)(0x42662600UL))
+#define bFM3_GPIO_PCRC_P1                      *((volatile unsigned int*)(0x42662604UL))
+#define bFM3_GPIO_PCRC_P2                      *((volatile unsigned int*)(0x42662608UL))
+#define bFM3_GPIO_PCRC_P3                      *((volatile unsigned int*)(0x4266260CUL))
+#define bFM3_GPIO_PCRC_P4                      *((volatile unsigned int*)(0x42662610UL))
+#define bFM3_GPIO_PCRC_P5                      *((volatile unsigned int*)(0x42662614UL))
+#define bFM3_GPIO_PCRC_P6                      *((volatile unsigned int*)(0x42662618UL))
+#define bFM3_GPIO_PCRC_P7                      *((volatile unsigned int*)(0x4266261CUL))
+#define bFM3_GPIO_PCRC_P8                      *((volatile unsigned int*)(0x42662620UL))
+#define bFM3_GPIO_PCRC_P9                      *((volatile unsigned int*)(0x42662624UL))
+#define bFM3_GPIO_PCRC_PA                      *((volatile unsigned int*)(0x42662628UL))
+#define bFM3_GPIO_PCRC_PB                      *((volatile unsigned int*)(0x4266262CUL))
+#define bFM3_GPIO_PCRC_PC                      *((volatile unsigned int*)(0x42662630UL))
+#define bFM3_GPIO_PCRC_PD                      *((volatile unsigned int*)(0x42662634UL))
+#define bFM3_GPIO_PCRC_PE                      *((volatile unsigned int*)(0x42662638UL))
+#define bFM3_GPIO_PCRC_PF                      *((volatile unsigned int*)(0x4266263CUL))
+#define bFM3_GPIO_PCRD_P0                      *((volatile unsigned int*)(0x42662680UL))
+#define bFM3_GPIO_PCRD_P1                      *((volatile unsigned int*)(0x42662684UL))
+#define bFM3_GPIO_PCRD_P2                      *((volatile unsigned int*)(0x42662688UL))
+#define bFM3_GPIO_PCRD_P3                      *((volatile unsigned int*)(0x4266268CUL))
+#define bFM3_GPIO_PCRE_P2                      *((volatile unsigned int*)(0x42662708UL))
+#define bFM3_GPIO_PCRE_P3                      *((volatile unsigned int*)(0x4266270CUL))
+#define bFM3_GPIO_DDR0_P0                      *((volatile unsigned int*)(0x42664000UL))
+#define bFM3_GPIO_DDR0_P1                      *((volatile unsigned int*)(0x42664004UL))
+#define bFM3_GPIO_DDR0_P2                      *((volatile unsigned int*)(0x42664008UL))
+#define bFM3_GPIO_DDR0_P3                      *((volatile unsigned int*)(0x4266400CUL))
+#define bFM3_GPIO_DDR0_P4                      *((volatile unsigned int*)(0x42664010UL))
+#define bFM3_GPIO_DDR0_P5                      *((volatile unsigned int*)(0x42664014UL))
+#define bFM3_GPIO_DDR0_P6                      *((volatile unsigned int*)(0x42664018UL))
+#define bFM3_GPIO_DDR0_P7                      *((volatile unsigned int*)(0x4266401CUL))
+#define bFM3_GPIO_DDR0_P8                      *((volatile unsigned int*)(0x42664020UL))
+#define bFM3_GPIO_DDR0_P9                      *((volatile unsigned int*)(0x42664024UL))
+#define bFM3_GPIO_DDR1_P0                      *((volatile unsigned int*)(0x42664080UL))
+#define bFM3_GPIO_DDR1_P1                      *((volatile unsigned int*)(0x42664084UL))
+#define bFM3_GPIO_DDR1_P2                      *((volatile unsigned int*)(0x42664088UL))
+#define bFM3_GPIO_DDR1_P3                      *((volatile unsigned int*)(0x4266408CUL))
+#define bFM3_GPIO_DDR1_P4                      *((volatile unsigned int*)(0x42664090UL))
+#define bFM3_GPIO_DDR1_P5                      *((volatile unsigned int*)(0x42664094UL))
+#define bFM3_GPIO_DDR1_P6                      *((volatile unsigned int*)(0x42664098UL))
+#define bFM3_GPIO_DDR1_P7                      *((volatile unsigned int*)(0x4266409CUL))
+#define bFM3_GPIO_DDR1_P8                      *((volatile unsigned int*)(0x426640A0UL))
+#define bFM3_GPIO_DDR1_P9                      *((volatile unsigned int*)(0x426640A4UL))
+#define bFM3_GPIO_DDR1_PA                      *((volatile unsigned int*)(0x426640A8UL))
+#define bFM3_GPIO_DDR1_PB                      *((volatile unsigned int*)(0x426640ACUL))
+#define bFM3_GPIO_DDR1_PC                      *((volatile unsigned int*)(0x426640B0UL))
+#define bFM3_GPIO_DDR1_PD                      *((volatile unsigned int*)(0x426640B4UL))
+#define bFM3_GPIO_DDR1_PE                      *((volatile unsigned int*)(0x426640B8UL))
+#define bFM3_GPIO_DDR1_PF                      *((volatile unsigned int*)(0x426640BCUL))
+#define bFM3_GPIO_DDR2_P0                      *((volatile unsigned int*)(0x42664100UL))
+#define bFM3_GPIO_DDR2_P1                      *((volatile unsigned int*)(0x42664104UL))
+#define bFM3_GPIO_DDR2_P2                      *((volatile unsigned int*)(0x42664108UL))
+#define bFM3_GPIO_DDR2_P3                      *((volatile unsigned int*)(0x4266410CUL))
+#define bFM3_GPIO_DDR2_P4                      *((volatile unsigned int*)(0x42664110UL))
+#define bFM3_GPIO_DDR2_P5                      *((volatile unsigned int*)(0x42664114UL))
+#define bFM3_GPIO_DDR2_P6                      *((volatile unsigned int*)(0x42664118UL))
+#define bFM3_GPIO_DDR2_P7                      *((volatile unsigned int*)(0x4266411CUL))
+#define bFM3_GPIO_DDR2_P8                      *((volatile unsigned int*)(0x42664120UL))
+#define bFM3_GPIO_DDR2_P9                      *((volatile unsigned int*)(0x42664124UL))
+#define bFM3_GPIO_DDR3_P0                      *((volatile unsigned int*)(0x42664180UL))
+#define bFM3_GPIO_DDR3_P1                      *((volatile unsigned int*)(0x42664184UL))
+#define bFM3_GPIO_DDR3_P2                      *((volatile unsigned int*)(0x42664188UL))
+#define bFM3_GPIO_DDR3_P3                      *((volatile unsigned int*)(0x4266418CUL))
+#define bFM3_GPIO_DDR3_P4                      *((volatile unsigned int*)(0x42664190UL))
+#define bFM3_GPIO_DDR3_P5                      *((volatile unsigned int*)(0x42664194UL))
+#define bFM3_GPIO_DDR3_P6                      *((volatile unsigned int*)(0x42664198UL))
+#define bFM3_GPIO_DDR3_P7                      *((volatile unsigned int*)(0x4266419CUL))
+#define bFM3_GPIO_DDR3_P8                      *((volatile unsigned int*)(0x426641A0UL))
+#define bFM3_GPIO_DDR3_P9                      *((volatile unsigned int*)(0x426641A4UL))
+#define bFM3_GPIO_DDR3_PA                      *((volatile unsigned int*)(0x426641A8UL))
+#define bFM3_GPIO_DDR3_PB                      *((volatile unsigned int*)(0x426641ACUL))
+#define bFM3_GPIO_DDR3_PC                      *((volatile unsigned int*)(0x426641B0UL))
+#define bFM3_GPIO_DDR3_PD                      *((volatile unsigned int*)(0x426641B4UL))
+#define bFM3_GPIO_DDR3_PE                      *((volatile unsigned int*)(0x426641B8UL))
+#define bFM3_GPIO_DDR3_PF                      *((volatile unsigned int*)(0x426641BCUL))
+#define bFM3_GPIO_DDR4_P0                      *((volatile unsigned int*)(0x42664200UL))
+#define bFM3_GPIO_DDR4_P1                      *((volatile unsigned int*)(0x42664204UL))
+#define bFM3_GPIO_DDR4_P2                      *((volatile unsigned int*)(0x42664208UL))
+#define bFM3_GPIO_DDR4_P3                      *((volatile unsigned int*)(0x4266420CUL))
+#define bFM3_GPIO_DDR4_P4                      *((volatile unsigned int*)(0x42664210UL))
+#define bFM3_GPIO_DDR4_P5                      *((volatile unsigned int*)(0x42664214UL))
+#define bFM3_GPIO_DDR4_P6                      *((volatile unsigned int*)(0x42664218UL))
+#define bFM3_GPIO_DDR4_P7                      *((volatile unsigned int*)(0x4266421CUL))
+#define bFM3_GPIO_DDR4_P8                      *((volatile unsigned int*)(0x42664220UL))
+#define bFM3_GPIO_DDR4_P9                      *((volatile unsigned int*)(0x42664224UL))
+#define bFM3_GPIO_DDR4_PA                      *((volatile unsigned int*)(0x42664228UL))
+#define bFM3_GPIO_DDR4_PB                      *((volatile unsigned int*)(0x4266422CUL))
+#define bFM3_GPIO_DDR4_PC                      *((volatile unsigned int*)(0x42664230UL))
+#define bFM3_GPIO_DDR4_PD                      *((volatile unsigned int*)(0x42664234UL))
+#define bFM3_GPIO_DDR4_PE                      *((volatile unsigned int*)(0x42664238UL))
+#define bFM3_GPIO_DDR5_P0                      *((volatile unsigned int*)(0x42664280UL))
+#define bFM3_GPIO_DDR5_P1                      *((volatile unsigned int*)(0x42664284UL))
+#define bFM3_GPIO_DDR5_P2                      *((volatile unsigned int*)(0x42664288UL))
+#define bFM3_GPIO_DDR5_P3                      *((volatile unsigned int*)(0x4266428CUL))
+#define bFM3_GPIO_DDR5_P4                      *((volatile unsigned int*)(0x42664290UL))
+#define bFM3_GPIO_DDR5_P5                      *((volatile unsigned int*)(0x42664294UL))
+#define bFM3_GPIO_DDR5_P6                      *((volatile unsigned int*)(0x42664298UL))
+#define bFM3_GPIO_DDR5_P7                      *((volatile unsigned int*)(0x4266429CUL))
+#define bFM3_GPIO_DDR5_P8                      *((volatile unsigned int*)(0x426642A0UL))
+#define bFM3_GPIO_DDR5_P9                      *((volatile unsigned int*)(0x426642A4UL))
+#define bFM3_GPIO_DDR5_PA                      *((volatile unsigned int*)(0x426642A8UL))
+#define bFM3_GPIO_DDR5_PB                      *((volatile unsigned int*)(0x426642ACUL))
+#define bFM3_GPIO_DDR5_PC                      *((volatile unsigned int*)(0x426642B0UL))
+#define bFM3_GPIO_DDR5_PD                      *((volatile unsigned int*)(0x426642B4UL))
+#define bFM3_GPIO_DDR6_P0                      *((volatile unsigned int*)(0x42664300UL))
+#define bFM3_GPIO_DDR6_P1                      *((volatile unsigned int*)(0x42664304UL))
+#define bFM3_GPIO_DDR6_P2                      *((volatile unsigned int*)(0x42664308UL))
+#define bFM3_GPIO_DDR7_P0                      *((volatile unsigned int*)(0x42664380UL))
+#define bFM3_GPIO_DDR7_P1                      *((volatile unsigned int*)(0x42664384UL))
+#define bFM3_GPIO_DDR7_P2                      *((volatile unsigned int*)(0x42664388UL))
+#define bFM3_GPIO_DDR7_P3                      *((volatile unsigned int*)(0x4266438CUL))
+#define bFM3_GPIO_DDR7_P4                      *((volatile unsigned int*)(0x42664390UL))
+#define bFM3_GPIO_DDR7_P5                      *((volatile unsigned int*)(0x42664394UL))
+#define bFM3_GPIO_DDR7_P6                      *((volatile unsigned int*)(0x42664398UL))
+#define bFM3_GPIO_DDR7_P7                      *((volatile unsigned int*)(0x4266439CUL))
+#define bFM3_GPIO_DDR7_P8                      *((volatile unsigned int*)(0x426643A0UL))
+#define bFM3_GPIO_DDR7_P9                      *((volatile unsigned int*)(0x426643A4UL))
+#define bFM3_GPIO_DDR7_PA                      *((volatile unsigned int*)(0x426643A8UL))
+#define bFM3_GPIO_DDR7_PB                      *((volatile unsigned int*)(0x426643ACUL))
+#define bFM3_GPIO_DDR7_PC                      *((volatile unsigned int*)(0x426643B0UL))
+#define bFM3_GPIO_DDR7_PD                      *((volatile unsigned int*)(0x426643B4UL))
+#define bFM3_GPIO_DDR7_PE                      *((volatile unsigned int*)(0x426643B8UL))
+#define bFM3_GPIO_DDR7_PF                      *((volatile unsigned int*)(0x426643BCUL))
+#define bFM3_GPIO_DDR8_P0                      *((volatile unsigned int*)(0x42664400UL))
+#define bFM3_GPIO_DDR8_P1                      *((volatile unsigned int*)(0x42664404UL))
+#define bFM3_GPIO_DDR8_P2                      *((volatile unsigned int*)(0x42664408UL))
+#define bFM3_GPIO_DDR8_P3                      *((volatile unsigned int*)(0x4266440CUL))
+#define bFM3_GPIO_DDR9_P0                      *((volatile unsigned int*)(0x42664480UL))
+#define bFM3_GPIO_DDR9_P1                      *((volatile unsigned int*)(0x42664484UL))
+#define bFM3_GPIO_DDR9_P2                      *((volatile unsigned int*)(0x42664488UL))
+#define bFM3_GPIO_DDR9_P3                      *((volatile unsigned int*)(0x4266448CUL))
+#define bFM3_GPIO_DDR9_P4                      *((volatile unsigned int*)(0x42664490UL))
+#define bFM3_GPIO_DDR9_P5                      *((volatile unsigned int*)(0x42664494UL))
+#define bFM3_GPIO_DDRA_P0                      *((volatile unsigned int*)(0x42664500UL))
+#define bFM3_GPIO_DDRA_P1                      *((volatile unsigned int*)(0x42664504UL))
+#define bFM3_GPIO_DDRA_P2                      *((volatile unsigned int*)(0x42664508UL))
+#define bFM3_GPIO_DDRA_P3                      *((volatile unsigned int*)(0x4266450CUL))
+#define bFM3_GPIO_DDRA_P4                      *((volatile unsigned int*)(0x42664510UL))
+#define bFM3_GPIO_DDRA_P5                      *((volatile unsigned int*)(0x42664514UL))
+#define bFM3_GPIO_DDRB_P0                      *((volatile unsigned int*)(0x42664580UL))
+#define bFM3_GPIO_DDRB_P1                      *((volatile unsigned int*)(0x42664584UL))
+#define bFM3_GPIO_DDRB_P2                      *((volatile unsigned int*)(0x42664588UL))
+#define bFM3_GPIO_DDRB_P3                      *((volatile unsigned int*)(0x4266458CUL))
+#define bFM3_GPIO_DDRB_P4                      *((volatile unsigned int*)(0x42664590UL))
+#define bFM3_GPIO_DDRB_P5                      *((volatile unsigned int*)(0x42664594UL))
+#define bFM3_GPIO_DDRB_P6                      *((volatile unsigned int*)(0x42664598UL))
+#define bFM3_GPIO_DDRB_P7                      *((volatile unsigned int*)(0x4266459CUL))
+#define bFM3_GPIO_DDRC_P0                      *((volatile unsigned int*)(0x42664600UL))
+#define bFM3_GPIO_DDRC_P1                      *((volatile unsigned int*)(0x42664604UL))
+#define bFM3_GPIO_DDRC_P2                      *((volatile unsigned int*)(0x42664608UL))
+#define bFM3_GPIO_DDRC_P3                      *((volatile unsigned int*)(0x4266460CUL))
+#define bFM3_GPIO_DDRC_P4                      *((volatile unsigned int*)(0x42664610UL))
+#define bFM3_GPIO_DDRC_P5                      *((volatile unsigned int*)(0x42664614UL))
+#define bFM3_GPIO_DDRC_P6                      *((volatile unsigned int*)(0x42664618UL))
+#define bFM3_GPIO_DDRC_P7                      *((volatile unsigned int*)(0x4266461CUL))
+#define bFM3_GPIO_DDRC_P8                      *((volatile unsigned int*)(0x42664620UL))
+#define bFM3_GPIO_DDRC_P9                      *((volatile unsigned int*)(0x42664624UL))
+#define bFM3_GPIO_DDRC_PA                      *((volatile unsigned int*)(0x42664628UL))
+#define bFM3_GPIO_DDRC_PB                      *((volatile unsigned int*)(0x4266462CUL))
+#define bFM3_GPIO_DDRC_PC                      *((volatile unsigned int*)(0x42664630UL))
+#define bFM3_GPIO_DDRC_PD                      *((volatile unsigned int*)(0x42664634UL))
+#define bFM3_GPIO_DDRC_PE                      *((volatile unsigned int*)(0x42664638UL))
+#define bFM3_GPIO_DDRC_PF                      *((volatile unsigned int*)(0x4266463CUL))
+#define bFM3_GPIO_DDRD_P0                      *((volatile unsigned int*)(0x42664680UL))
+#define bFM3_GPIO_DDRD_P1                      *((volatile unsigned int*)(0x42664684UL))
+#define bFM3_GPIO_DDRD_P2                      *((volatile unsigned int*)(0x42664688UL))
+#define bFM3_GPIO_DDRD_P3                      *((volatile unsigned int*)(0x4266468CUL))
+#define bFM3_GPIO_DDRE_P0                      *((volatile unsigned int*)(0x42664700UL))
+#define bFM3_GPIO_DDRE_P2                      *((volatile unsigned int*)(0x42664708UL))
+#define bFM3_GPIO_DDRE_P3                      *((volatile unsigned int*)(0x4266470CUL))
+#define bFM3_GPIO_DDRF_P0                      *((volatile unsigned int*)(0x42664780UL))
+#define bFM3_GPIO_DDRF_P1                      *((volatile unsigned int*)(0x42664784UL))
+#define bFM3_GPIO_DDRF_P2                      *((volatile unsigned int*)(0x42664788UL))
+#define bFM3_GPIO_DDRF_P3                      *((volatile unsigned int*)(0x4266478CUL))
+#define bFM3_GPIO_DDRF_P4                      *((volatile unsigned int*)(0x42664790UL))
+#define bFM3_GPIO_DDRF_P5                      *((volatile unsigned int*)(0x42664794UL))
+#define bFM3_GPIO_DDRF_P6                      *((volatile unsigned int*)(0x42664798UL))
+#define bFM3_GPIO_PDIR0_P0                     *((volatile unsigned int*)(0x42666000UL))
+#define bFM3_GPIO_PDIR0_P1                     *((volatile unsigned int*)(0x42666004UL))
+#define bFM3_GPIO_PDIR0_P2                     *((volatile unsigned int*)(0x42666008UL))
+#define bFM3_GPIO_PDIR0_P3                     *((volatile unsigned int*)(0x4266600CUL))
+#define bFM3_GPIO_PDIR0_P4                     *((volatile unsigned int*)(0x42666010UL))
+#define bFM3_GPIO_PDIR0_P5                     *((volatile unsigned int*)(0x42666014UL))
+#define bFM3_GPIO_PDIR0_P6                     *((volatile unsigned int*)(0x42666018UL))
+#define bFM3_GPIO_PDIR0_P7                     *((volatile unsigned int*)(0x4266601CUL))
+#define bFM3_GPIO_PDIR0_P8                     *((volatile unsigned int*)(0x42666020UL))
+#define bFM3_GPIO_PDIR0_P9                     *((volatile unsigned int*)(0x42666024UL))
+#define bFM3_GPIO_PDIR1_P0                     *((volatile unsigned int*)(0x42666080UL))
+#define bFM3_GPIO_PDIR1_P1                     *((volatile unsigned int*)(0x42666084UL))
+#define bFM3_GPIO_PDIR1_P2                     *((volatile unsigned int*)(0x42666088UL))
+#define bFM3_GPIO_PDIR1_P3                     *((volatile unsigned int*)(0x4266608CUL))
+#define bFM3_GPIO_PDIR1_P4                     *((volatile unsigned int*)(0x42666090UL))
+#define bFM3_GPIO_PDIR1_P5                     *((volatile unsigned int*)(0x42666094UL))
+#define bFM3_GPIO_PDIR1_P6                     *((volatile unsigned int*)(0x42666098UL))
+#define bFM3_GPIO_PDIR1_P7                     *((volatile unsigned int*)(0x4266609CUL))
+#define bFM3_GPIO_PDIR1_P8                     *((volatile unsigned int*)(0x426660A0UL))
+#define bFM3_GPIO_PDIR1_P9                     *((volatile unsigned int*)(0x426660A4UL))
+#define bFM3_GPIO_PDIR1_PA                     *((volatile unsigned int*)(0x426660A8UL))
+#define bFM3_GPIO_PDIR1_PB                     *((volatile unsigned int*)(0x426660ACUL))
+#define bFM3_GPIO_PDIR1_PC                     *((volatile unsigned int*)(0x426660B0UL))
+#define bFM3_GPIO_PDIR1_PD                     *((volatile unsigned int*)(0x426660B4UL))
+#define bFM3_GPIO_PDIR1_PE                     *((volatile unsigned int*)(0x426660B8UL))
+#define bFM3_GPIO_PDIR1_PF                     *((volatile unsigned int*)(0x426660BCUL))
+#define bFM3_GPIO_PDIR2_P0                     *((volatile unsigned int*)(0x42666100UL))
+#define bFM3_GPIO_PDIR2_P1                     *((volatile unsigned int*)(0x42666104UL))
+#define bFM3_GPIO_PDIR2_P2                     *((volatile unsigned int*)(0x42666108UL))
+#define bFM3_GPIO_PDIR2_P3                     *((volatile unsigned int*)(0x4266610CUL))
+#define bFM3_GPIO_PDIR2_P4                     *((volatile unsigned int*)(0x42666110UL))
+#define bFM3_GPIO_PDIR2_P5                     *((volatile unsigned int*)(0x42666114UL))
+#define bFM3_GPIO_PDIR2_P6                     *((volatile unsigned int*)(0x42666118UL))
+#define bFM3_GPIO_PDIR2_P7                     *((volatile unsigned int*)(0x4266611CUL))
+#define bFM3_GPIO_PDIR2_P8                     *((volatile unsigned int*)(0x42666120UL))
+#define bFM3_GPIO_PDIR2_P9                     *((volatile unsigned int*)(0x42666124UL))
+#define bFM3_GPIO_PDIR3_P0                     *((volatile unsigned int*)(0x42666180UL))
+#define bFM3_GPIO_PDIR3_P1                     *((volatile unsigned int*)(0x42666184UL))
+#define bFM3_GPIO_PDIR3_P2                     *((volatile unsigned int*)(0x42666188UL))
+#define bFM3_GPIO_PDIR3_P3                     *((volatile unsigned int*)(0x4266618CUL))
+#define bFM3_GPIO_PDIR3_P4                     *((volatile unsigned int*)(0x42666190UL))
+#define bFM3_GPIO_PDIR3_P5                     *((volatile unsigned int*)(0x42666194UL))
+#define bFM3_GPIO_PDIR3_P6                     *((volatile unsigned int*)(0x42666198UL))
+#define bFM3_GPIO_PDIR3_P7                     *((volatile unsigned int*)(0x4266619CUL))
+#define bFM3_GPIO_PDIR3_P8                     *((volatile unsigned int*)(0x426661A0UL))
+#define bFM3_GPIO_PDIR3_P9                     *((volatile unsigned int*)(0x426661A4UL))
+#define bFM3_GPIO_PDIR3_PA                     *((volatile unsigned int*)(0x426661A8UL))
+#define bFM3_GPIO_PDIR3_PB                     *((volatile unsigned int*)(0x426661ACUL))
+#define bFM3_GPIO_PDIR3_PC                     *((volatile unsigned int*)(0x426661B0UL))
+#define bFM3_GPIO_PDIR3_PD                     *((volatile unsigned int*)(0x426661B4UL))
+#define bFM3_GPIO_PDIR3_PE                     *((volatile unsigned int*)(0x426661B8UL))
+#define bFM3_GPIO_PDIR3_PF                     *((volatile unsigned int*)(0x426661BCUL))
+#define bFM3_GPIO_PDIR4_P0                     *((volatile unsigned int*)(0x42666200UL))
+#define bFM3_GPIO_PDIR4_P1                     *((volatile unsigned int*)(0x42666204UL))
+#define bFM3_GPIO_PDIR4_P2                     *((volatile unsigned int*)(0x42666208UL))
+#define bFM3_GPIO_PDIR4_P3                     *((volatile unsigned int*)(0x4266620CUL))
+#define bFM3_GPIO_PDIR4_P4                     *((volatile unsigned int*)(0x42666210UL))
+#define bFM3_GPIO_PDIR4_P5                     *((volatile unsigned int*)(0x42666214UL))
+#define bFM3_GPIO_PDIR4_P6                     *((volatile unsigned int*)(0x42666218UL))
+#define bFM3_GPIO_PDIR4_P7                     *((volatile unsigned int*)(0x4266621CUL))
+#define bFM3_GPIO_PDIR4_P8                     *((volatile unsigned int*)(0x42666220UL))
+#define bFM3_GPIO_PDIR4_P9                     *((volatile unsigned int*)(0x42666224UL))
+#define bFM3_GPIO_PDIR4_PA                     *((volatile unsigned int*)(0x42666228UL))
+#define bFM3_GPIO_PDIR4_PB                     *((volatile unsigned int*)(0x4266622CUL))
+#define bFM3_GPIO_PDIR4_PC                     *((volatile unsigned int*)(0x42666230UL))
+#define bFM3_GPIO_PDIR4_PD                     *((volatile unsigned int*)(0x42666234UL))
+#define bFM3_GPIO_PDIR4_PE                     *((volatile unsigned int*)(0x42666238UL))
+#define bFM3_GPIO_PDIR5_P0                     *((volatile unsigned int*)(0x42666280UL))
+#define bFM3_GPIO_PDIR5_P1                     *((volatile unsigned int*)(0x42666284UL))
+#define bFM3_GPIO_PDIR5_P2                     *((volatile unsigned int*)(0x42666288UL))
+#define bFM3_GPIO_PDIR5_P3                     *((volatile unsigned int*)(0x4266628CUL))
+#define bFM3_GPIO_PDIR5_P4                     *((volatile unsigned int*)(0x42666290UL))
+#define bFM3_GPIO_PDIR5_P5                     *((volatile unsigned int*)(0x42666294UL))
+#define bFM3_GPIO_PDIR5_P6                     *((volatile unsigned int*)(0x42666298UL))
+#define bFM3_GPIO_PDIR5_P7                     *((volatile unsigned int*)(0x4266629CUL))
+#define bFM3_GPIO_PDIR5_P8                     *((volatile unsigned int*)(0x426662A0UL))
+#define bFM3_GPIO_PDIR5_P9                     *((volatile unsigned int*)(0x426662A4UL))
+#define bFM3_GPIO_PDIR5_PA                     *((volatile unsigned int*)(0x426662A8UL))
+#define bFM3_GPIO_PDIR5_PB                     *((volatile unsigned int*)(0x426662ACUL))
+#define bFM3_GPIO_PDIR5_PC                     *((volatile unsigned int*)(0x426662B0UL))
+#define bFM3_GPIO_PDIR5_PD                     *((volatile unsigned int*)(0x426662B4UL))
+#define bFM3_GPIO_PDIR6_P0                     *((volatile unsigned int*)(0x42666300UL))
+#define bFM3_GPIO_PDIR6_P1                     *((volatile unsigned int*)(0x42666304UL))
+#define bFM3_GPIO_PDIR6_P2                     *((volatile unsigned int*)(0x42666308UL))
+#define bFM3_GPIO_PDIR7_P0                     *((volatile unsigned int*)(0x42666380UL))
+#define bFM3_GPIO_PDIR7_P1                     *((volatile unsigned int*)(0x42666384UL))
+#define bFM3_GPIO_PDIR7_P2                     *((volatile unsigned int*)(0x42666388UL))
+#define bFM3_GPIO_PDIR7_P3                     *((volatile unsigned int*)(0x4266638CUL))
+#define bFM3_GPIO_PDIR7_P4                     *((volatile unsigned int*)(0x42666390UL))
+#define bFM3_GPIO_PDIR7_P5                     *((volatile unsigned int*)(0x42666394UL))
+#define bFM3_GPIO_PDIR7_P6                     *((volatile unsigned int*)(0x42666398UL))
+#define bFM3_GPIO_PDIR7_P7                     *((volatile unsigned int*)(0x4266639CUL))
+#define bFM3_GPIO_PDIR7_P8                     *((volatile unsigned int*)(0x426663A0UL))
+#define bFM3_GPIO_PDIR7_P9                     *((volatile unsigned int*)(0x426663A4UL))
+#define bFM3_GPIO_PDIR7_PA                     *((volatile unsigned int*)(0x426663A8UL))
+#define bFM3_GPIO_PDIR7_PB                     *((volatile unsigned int*)(0x426663ACUL))
+#define bFM3_GPIO_PDIR7_PC                     *((volatile unsigned int*)(0x426663B0UL))
+#define bFM3_GPIO_PDIR7_PD                     *((volatile unsigned int*)(0x426663B4UL))
+#define bFM3_GPIO_PDIR7_PE                     *((volatile unsigned int*)(0x426663B8UL))
+#define bFM3_GPIO_PDIR7_PF                     *((volatile unsigned int*)(0x426663BCUL))
+#define bFM3_GPIO_PDIR8_P0                     *((volatile unsigned int*)(0x42666400UL))
+#define bFM3_GPIO_PDIR8_P1                     *((volatile unsigned int*)(0x42666404UL))
+#define bFM3_GPIO_PDIR8_P2                     *((volatile unsigned int*)(0x42666408UL))
+#define bFM3_GPIO_PDIR8_P3                     *((volatile unsigned int*)(0x4266640CUL))
+#define bFM3_GPIO_PDIR9_P0                     *((volatile unsigned int*)(0x42666480UL))
+#define bFM3_GPIO_PDIR9_P1                     *((volatile unsigned int*)(0x42666484UL))
+#define bFM3_GPIO_PDIR9_P2                     *((volatile unsigned int*)(0x42666488UL))
+#define bFM3_GPIO_PDIR9_P3                     *((volatile unsigned int*)(0x4266648CUL))
+#define bFM3_GPIO_PDIR9_P4                     *((volatile unsigned int*)(0x42666490UL))
+#define bFM3_GPIO_PDIR9_P5                     *((volatile unsigned int*)(0x42666494UL))
+#define bFM3_GPIO_PDIRA_P0                     *((volatile unsigned int*)(0x42666500UL))
+#define bFM3_GPIO_PDIRA_P1                     *((volatile unsigned int*)(0x42666504UL))
+#define bFM3_GPIO_PDIRA_P2                     *((volatile unsigned int*)(0x42666508UL))
+#define bFM3_GPIO_PDIRA_P3                     *((volatile unsigned int*)(0x4266650CUL))
+#define bFM3_GPIO_PDIRA_P4                     *((volatile unsigned int*)(0x42666510UL))
+#define bFM3_GPIO_PDIRA_P5                     *((volatile unsigned int*)(0x42666514UL))
+#define bFM3_GPIO_PDIRB_P0                     *((volatile unsigned int*)(0x42666580UL))
+#define bFM3_GPIO_PDIRB_P1                     *((volatile unsigned int*)(0x42666584UL))
+#define bFM3_GPIO_PDIRB_P2                     *((volatile unsigned int*)(0x42666588UL))
+#define bFM3_GPIO_PDIRB_P3                     *((volatile unsigned int*)(0x4266658CUL))
+#define bFM3_GPIO_PDIRB_P4                     *((volatile unsigned int*)(0x42666590UL))
+#define bFM3_GPIO_PDIRB_P5                     *((volatile unsigned int*)(0x42666594UL))
+#define bFM3_GPIO_PDIRB_P6                     *((volatile unsigned int*)(0x42666598UL))
+#define bFM3_GPIO_PDIRB_P7                     *((volatile unsigned int*)(0x4266659CUL))
+#define bFM3_GPIO_PDIRC_P0                     *((volatile unsigned int*)(0x42666600UL))
+#define bFM3_GPIO_PDIRC_P1                     *((volatile unsigned int*)(0x42666604UL))
+#define bFM3_GPIO_PDIRC_P2                     *((volatile unsigned int*)(0x42666608UL))
+#define bFM3_GPIO_PDIRC_P3                     *((volatile unsigned int*)(0x4266660CUL))
+#define bFM3_GPIO_PDIRC_P4                     *((volatile unsigned int*)(0x42666610UL))
+#define bFM3_GPIO_PDIRC_P5                     *((volatile unsigned int*)(0x42666614UL))
+#define bFM3_GPIO_PDIRC_P6                     *((volatile unsigned int*)(0x42666618UL))
+#define bFM3_GPIO_PDIRC_P7                     *((volatile unsigned int*)(0x4266661CUL))
+#define bFM3_GPIO_PDIRC_P8                     *((volatile unsigned int*)(0x42666620UL))
+#define bFM3_GPIO_PDIRC_P9                     *((volatile unsigned int*)(0x42666624UL))
+#define bFM3_GPIO_PDIRC_PA                     *((volatile unsigned int*)(0x42666628UL))
+#define bFM3_GPIO_PDIRC_PB                     *((volatile unsigned int*)(0x4266662CUL))
+#define bFM3_GPIO_PDIRC_PC                     *((volatile unsigned int*)(0x42666630UL))
+#define bFM3_GPIO_PDIRC_PD                     *((volatile unsigned int*)(0x42666634UL))
+#define bFM3_GPIO_PDIRC_PE                     *((volatile unsigned int*)(0x42666638UL))
+#define bFM3_GPIO_PDIRC_PF                     *((volatile unsigned int*)(0x4266663CUL))
+#define bFM3_GPIO_PDIRD_P0                     *((volatile unsigned int*)(0x42666680UL))
+#define bFM3_GPIO_PDIRD_P1                     *((volatile unsigned int*)(0x42666684UL))
+#define bFM3_GPIO_PDIRD_P2                     *((volatile unsigned int*)(0x42666688UL))
+#define bFM3_GPIO_PDIRD_P3                     *((volatile unsigned int*)(0x4266668CUL))
+#define bFM3_GPIO_PDIRE_P0                     *((volatile unsigned int*)(0x42666700UL))
+#define bFM3_GPIO_PDIRE_P2                     *((volatile unsigned int*)(0x42666708UL))
+#define bFM3_GPIO_PDIRE_P3                     *((volatile unsigned int*)(0x4266670CUL))
+#define bFM3_GPIO_PDIRF_P0                     *((volatile unsigned int*)(0x42666780UL))
+#define bFM3_GPIO_PDIRF_P1                     *((volatile unsigned int*)(0x42666784UL))
+#define bFM3_GPIO_PDIRF_P2                     *((volatile unsigned int*)(0x42666788UL))
+#define bFM3_GPIO_PDIRF_P3                     *((volatile unsigned int*)(0x4266678CUL))
+#define bFM3_GPIO_PDIRF_P4                     *((volatile unsigned int*)(0x42666790UL))
+#define bFM3_GPIO_PDIRF_P5                     *((volatile unsigned int*)(0x42666794UL))
+#define bFM3_GPIO_PDIRF_P6                     *((volatile unsigned int*)(0x42666798UL))
+#define bFM3_GPIO_PDOR0_P0                     *((volatile unsigned int*)(0x42668000UL))
+#define bFM3_GPIO_PDOR0_P1                     *((volatile unsigned int*)(0x42668004UL))
+#define bFM3_GPIO_PDOR0_P2                     *((volatile unsigned int*)(0x42668008UL))
+#define bFM3_GPIO_PDOR0_P3                     *((volatile unsigned int*)(0x4266800CUL))
+#define bFM3_GPIO_PDOR0_P4                     *((volatile unsigned int*)(0x42668010UL))
+#define bFM3_GPIO_PDOR0_P5                     *((volatile unsigned int*)(0x42668014UL))
+#define bFM3_GPIO_PDOR0_P6                     *((volatile unsigned int*)(0x42668018UL))
+#define bFM3_GPIO_PDOR0_P7                     *((volatile unsigned int*)(0x4266801CUL))
+#define bFM3_GPIO_PDOR0_P8                     *((volatile unsigned int*)(0x42668020UL))
+#define bFM3_GPIO_PDOR0_P9                     *((volatile unsigned int*)(0x42668024UL))
+#define bFM3_GPIO_PDOR1_P0                     *((volatile unsigned int*)(0x42668080UL))
+#define bFM3_GPIO_PDOR1_P1                     *((volatile unsigned int*)(0x42668084UL))
+#define bFM3_GPIO_PDOR1_P2                     *((volatile unsigned int*)(0x42668088UL))
+#define bFM3_GPIO_PDOR1_P3                     *((volatile unsigned int*)(0x4266808CUL))
+#define bFM3_GPIO_PDOR1_P4                     *((volatile unsigned int*)(0x42668090UL))
+#define bFM3_GPIO_PDOR1_P5                     *((volatile unsigned int*)(0x42668094UL))
+#define bFM3_GPIO_PDOR1_P6                     *((volatile unsigned int*)(0x42668098UL))
+#define bFM3_GPIO_PDOR1_P7                     *((volatile unsigned int*)(0x4266809CUL))
+#define bFM3_GPIO_PDOR1_P8                     *((volatile unsigned int*)(0x426680A0UL))
+#define bFM3_GPIO_PDOR1_P9                     *((volatile unsigned int*)(0x426680A4UL))
+#define bFM3_GPIO_PDOR1_PA                     *((volatile unsigned int*)(0x426680A8UL))
+#define bFM3_GPIO_PDOR1_PB                     *((volatile unsigned int*)(0x426680ACUL))
+#define bFM3_GPIO_PDOR1_PC                     *((volatile unsigned int*)(0x426680B0UL))
+#define bFM3_GPIO_PDOR1_PD                     *((volatile unsigned int*)(0x426680B4UL))
+#define bFM3_GPIO_PDOR1_PE                     *((volatile unsigned int*)(0x426680B8UL))
+#define bFM3_GPIO_PDOR1_PF                     *((volatile unsigned int*)(0x426680BCUL))
+#define bFM3_GPIO_PDOR2_P0                     *((volatile unsigned int*)(0x42668100UL))
+#define bFM3_GPIO_PDOR2_P1                     *((volatile unsigned int*)(0x42668104UL))
+#define bFM3_GPIO_PDOR2_P2                     *((volatile unsigned int*)(0x42668108UL))
+#define bFM3_GPIO_PDOR2_P3                     *((volatile unsigned int*)(0x4266810CUL))
+#define bFM3_GPIO_PDOR2_P4                     *((volatile unsigned int*)(0x42668110UL))
+#define bFM3_GPIO_PDOR2_P5                     *((volatile unsigned int*)(0x42668114UL))
+#define bFM3_GPIO_PDOR2_P6                     *((volatile unsigned int*)(0x42668118UL))
+#define bFM3_GPIO_PDOR2_P7                     *((volatile unsigned int*)(0x4266811CUL))
+#define bFM3_GPIO_PDOR2_P8                     *((volatile unsigned int*)(0x42668120UL))
+#define bFM3_GPIO_PDOR2_P9                     *((volatile unsigned int*)(0x42668124UL))
+#define bFM3_GPIO_PDOR3_P0                     *((volatile unsigned int*)(0x42668180UL))
+#define bFM3_GPIO_PDOR3_P1                     *((volatile unsigned int*)(0x42668184UL))
+#define bFM3_GPIO_PDOR3_P2                     *((volatile unsigned int*)(0x42668188UL))
+#define bFM3_GPIO_PDOR3_P3                     *((volatile unsigned int*)(0x4266818CUL))
+#define bFM3_GPIO_PDOR3_P4                     *((volatile unsigned int*)(0x42668190UL))
+#define bFM3_GPIO_PDOR3_P5                     *((volatile unsigned int*)(0x42668194UL))
+#define bFM3_GPIO_PDOR3_P6                     *((volatile unsigned int*)(0x42668198UL))
+#define bFM3_GPIO_PDOR3_P7                     *((volatile unsigned int*)(0x4266819CUL))
+#define bFM3_GPIO_PDOR3_P8                     *((volatile unsigned int*)(0x426681A0UL))
+#define bFM3_GPIO_PDOR3_P9                     *((volatile unsigned int*)(0x426681A4UL))
+#define bFM3_GPIO_PDOR3_PA                     *((volatile unsigned int*)(0x426681A8UL))
+#define bFM3_GPIO_PDOR3_PB                     *((volatile unsigned int*)(0x426681ACUL))
+#define bFM3_GPIO_PDOR3_PC                     *((volatile unsigned int*)(0x426681B0UL))
+#define bFM3_GPIO_PDOR3_PD                     *((volatile unsigned int*)(0x426681B4UL))
+#define bFM3_GPIO_PDOR3_PE                     *((volatile unsigned int*)(0x426681B8UL))
+#define bFM3_GPIO_PDOR3_PF                     *((volatile unsigned int*)(0x426681BCUL))
+#define bFM3_GPIO_PDOR4_P0                     *((volatile unsigned int*)(0x42668200UL))
+#define bFM3_GPIO_PDOR4_P1                     *((volatile unsigned int*)(0x42668204UL))
+#define bFM3_GPIO_PDOR4_P2                     *((volatile unsigned int*)(0x42668208UL))
+#define bFM3_GPIO_PDOR4_P3                     *((volatile unsigned int*)(0x4266820CUL))
+#define bFM3_GPIO_PDOR4_P4                     *((volatile unsigned int*)(0x42668210UL))
+#define bFM3_GPIO_PDOR4_P5                     *((volatile unsigned int*)(0x42668214UL))
+#define bFM3_GPIO_PDOR4_P6                     *((volatile unsigned int*)(0x42668218UL))
+#define bFM3_GPIO_PDOR4_P7                     *((volatile unsigned int*)(0x4266821CUL))
+#define bFM3_GPIO_PDOR4_P8                     *((volatile unsigned int*)(0x42668220UL))
+#define bFM3_GPIO_PDOR4_P9                     *((volatile unsigned int*)(0x42668224UL))
+#define bFM3_GPIO_PDOR4_PA                     *((volatile unsigned int*)(0x42668228UL))
+#define bFM3_GPIO_PDOR4_PB                     *((volatile unsigned int*)(0x4266822CUL))
+#define bFM3_GPIO_PDOR4_PC                     *((volatile unsigned int*)(0x42668230UL))
+#define bFM3_GPIO_PDOR4_PD                     *((volatile unsigned int*)(0x42668234UL))
+#define bFM3_GPIO_PDOR4_PE                     *((volatile unsigned int*)(0x42668238UL))
+#define bFM3_GPIO_PDOR5_P0                     *((volatile unsigned int*)(0x42668280UL))
+#define bFM3_GPIO_PDOR5_P1                     *((volatile unsigned int*)(0x42668284UL))
+#define bFM3_GPIO_PDOR5_P2                     *((volatile unsigned int*)(0x42668288UL))
+#define bFM3_GPIO_PDOR5_P3                     *((volatile unsigned int*)(0x4266828CUL))
+#define bFM3_GPIO_PDOR5_P4                     *((volatile unsigned int*)(0x42668290UL))
+#define bFM3_GPIO_PDOR5_P5                     *((volatile unsigned int*)(0x42668294UL))
+#define bFM3_GPIO_PDOR5_P6                     *((volatile unsigned int*)(0x42668298UL))
+#define bFM3_GPIO_PDOR5_P7                     *((volatile unsigned int*)(0x4266829CUL))
+#define bFM3_GPIO_PDOR5_P8                     *((volatile unsigned int*)(0x426682A0UL))
+#define bFM3_GPIO_PDOR5_P9                     *((volatile unsigned int*)(0x426682A4UL))
+#define bFM3_GPIO_PDOR5_PA                     *((volatile unsigned int*)(0x426682A8UL))
+#define bFM3_GPIO_PDOR5_PB                     *((volatile unsigned int*)(0x426682ACUL))
+#define bFM3_GPIO_PDOR5_PC                     *((volatile unsigned int*)(0x426682B0UL))
+#define bFM3_GPIO_PDOR5_PD                     *((volatile unsigned int*)(0x426682B4UL))
+#define bFM3_GPIO_PDOR6_P0                     *((volatile unsigned int*)(0x42668300UL))
+#define bFM3_GPIO_PDOR6_P1                     *((volatile unsigned int*)(0x42668304UL))
+#define bFM3_GPIO_PDOR6_P2                     *((volatile unsigned int*)(0x42668308UL))
+#define bFM3_GPIO_PDOR7_P0                     *((volatile unsigned int*)(0x42668380UL))
+#define bFM3_GPIO_PDOR7_P1                     *((volatile unsigned int*)(0x42668384UL))
+#define bFM3_GPIO_PDOR7_P2                     *((volatile unsigned int*)(0x42668388UL))
+#define bFM3_GPIO_PDOR7_P3                     *((volatile unsigned int*)(0x4266838CUL))
+#define bFM3_GPIO_PDOR7_P4                     *((volatile unsigned int*)(0x42668390UL))
+#define bFM3_GPIO_PDOR7_P5                     *((volatile unsigned int*)(0x42668394UL))
+#define bFM3_GPIO_PDOR7_P6                     *((volatile unsigned int*)(0x42668398UL))
+#define bFM3_GPIO_PDOR7_P7                     *((volatile unsigned int*)(0x4266839CUL))
+#define bFM3_GPIO_PDOR7_P8                     *((volatile unsigned int*)(0x426683A0UL))
+#define bFM3_GPIO_PDOR7_P9                     *((volatile unsigned int*)(0x426683A4UL))
+#define bFM3_GPIO_PDOR7_PA                     *((volatile unsigned int*)(0x426683A8UL))
+#define bFM3_GPIO_PDOR7_PB                     *((volatile unsigned int*)(0x426683ACUL))
+#define bFM3_GPIO_PDOR7_PC                     *((volatile unsigned int*)(0x426683B0UL))
+#define bFM3_GPIO_PDOR7_PD                     *((volatile unsigned int*)(0x426683B4UL))
+#define bFM3_GPIO_PDOR7_PE                     *((volatile unsigned int*)(0x426683B8UL))
+#define bFM3_GPIO_PDOR7_PF                     *((volatile unsigned int*)(0x426683BCUL))
+#define bFM3_GPIO_PDOR8_P0                     *((volatile unsigned int*)(0x42668400UL))
+#define bFM3_GPIO_PDOR8_P1                     *((volatile unsigned int*)(0x42668404UL))
+#define bFM3_GPIO_PDOR8_P2                     *((volatile unsigned int*)(0x42668408UL))
+#define bFM3_GPIO_PDOR8_P3                     *((volatile unsigned int*)(0x4266840CUL))
+#define bFM3_GPIO_PDOR9_P0                     *((volatile unsigned int*)(0x42668480UL))
+#define bFM3_GPIO_PDOR9_P1                     *((volatile unsigned int*)(0x42668484UL))
+#define bFM3_GPIO_PDOR9_P2                     *((volatile unsigned int*)(0x42668488UL))
+#define bFM3_GPIO_PDOR9_P3                     *((volatile unsigned int*)(0x4266848CUL))
+#define bFM3_GPIO_PDOR9_P4                     *((volatile unsigned int*)(0x42668490UL))
+#define bFM3_GPIO_PDOR9_P5                     *((volatile unsigned int*)(0x42668494UL))
+#define bFM3_GPIO_PDORA_P0                     *((volatile unsigned int*)(0x42668500UL))
+#define bFM3_GPIO_PDORA_P1                     *((volatile unsigned int*)(0x42668504UL))
+#define bFM3_GPIO_PDORA_P2                     *((volatile unsigned int*)(0x42668508UL))
+#define bFM3_GPIO_PDORA_P3                     *((volatile unsigned int*)(0x4266850CUL))
+#define bFM3_GPIO_PDORA_P4                     *((volatile unsigned int*)(0x42668510UL))
+#define bFM3_GPIO_PDORA_P5                     *((volatile unsigned int*)(0x42668514UL))
+#define bFM3_GPIO_PDORB_P0                     *((volatile unsigned int*)(0x42668580UL))
+#define bFM3_GPIO_PDORB_P1                     *((volatile unsigned int*)(0x42668584UL))
+#define bFM3_GPIO_PDORB_P2                     *((volatile unsigned int*)(0x42668588UL))
+#define bFM3_GPIO_PDORB_P3                     *((volatile unsigned int*)(0x4266858CUL))
+#define bFM3_GPIO_PDORB_P4                     *((volatile unsigned int*)(0x42668590UL))
+#define bFM3_GPIO_PDORB_P5                     *((volatile unsigned int*)(0x42668594UL))
+#define bFM3_GPIO_PDORB_P6                     *((volatile unsigned int*)(0x42668598UL))
+#define bFM3_GPIO_PDORB_P7                     *((volatile unsigned int*)(0x4266859CUL))
+#define bFM3_GPIO_PDORC_P0                     *((volatile unsigned int*)(0x42668600UL))
+#define bFM3_GPIO_PDORC_P1                     *((volatile unsigned int*)(0x42668604UL))
+#define bFM3_GPIO_PDORC_P2                     *((volatile unsigned int*)(0x42668608UL))
+#define bFM3_GPIO_PDORC_P3                     *((volatile unsigned int*)(0x4266860CUL))
+#define bFM3_GPIO_PDORC_P4                     *((volatile unsigned int*)(0x42668610UL))
+#define bFM3_GPIO_PDORC_P5                     *((volatile unsigned int*)(0x42668614UL))
+#define bFM3_GPIO_PDORC_P6                     *((volatile unsigned int*)(0x42668618UL))
+#define bFM3_GPIO_PDORC_P7                     *((volatile unsigned int*)(0x4266861CUL))
+#define bFM3_GPIO_PDORC_P8                     *((volatile unsigned int*)(0x42668620UL))
+#define bFM3_GPIO_PDORC_P9                     *((volatile unsigned int*)(0x42668624UL))
+#define bFM3_GPIO_PDORC_PA                     *((volatile unsigned int*)(0x42668628UL))
+#define bFM3_GPIO_PDORC_PB                     *((volatile unsigned int*)(0x4266862CUL))
+#define bFM3_GPIO_PDORC_PC                     *((volatile unsigned int*)(0x42668630UL))
+#define bFM3_GPIO_PDORC_PD                     *((volatile unsigned int*)(0x42668634UL))
+#define bFM3_GPIO_PDORC_PE                     *((volatile unsigned int*)(0x42668638UL))
+#define bFM3_GPIO_PDORC_PF                     *((volatile unsigned int*)(0x4266863CUL))
+#define bFM3_GPIO_PDORD_P0                     *((volatile unsigned int*)(0x42668680UL))
+#define bFM3_GPIO_PDORD_P1                     *((volatile unsigned int*)(0x42668684UL))
+#define bFM3_GPIO_PDORD_P2                     *((volatile unsigned int*)(0x42668688UL))
+#define bFM3_GPIO_PDORD_P3                     *((volatile unsigned int*)(0x4266868CUL))
+#define bFM3_GPIO_PDORE_P0                     *((volatile unsigned int*)(0x42668700UL))
+#define bFM3_GPIO_PDORE_P2                     *((volatile unsigned int*)(0x42668708UL))
+#define bFM3_GPIO_PDORE_P3                     *((volatile unsigned int*)(0x4266870CUL))
+#define bFM3_GPIO_PDORF_P0                     *((volatile unsigned int*)(0x42668780UL))
+#define bFM3_GPIO_PDORF_P1                     *((volatile unsigned int*)(0x42668784UL))
+#define bFM3_GPIO_PDORF_P2                     *((volatile unsigned int*)(0x42668788UL))
+#define bFM3_GPIO_PDORF_P3                     *((volatile unsigned int*)(0x4266878CUL))
+#define bFM3_GPIO_PDORF_P4                     *((volatile unsigned int*)(0x42668790UL))
+#define bFM3_GPIO_PDORF_P5                     *((volatile unsigned int*)(0x42668794UL))
+#define bFM3_GPIO_PDORF_P6                     *((volatile unsigned int*)(0x42668798UL))
+#define bFM3_GPIO_ADE_AN0                      *((volatile unsigned int*)(0x4266A000UL))
+#define bFM3_GPIO_ADE_AN1                      *((volatile unsigned int*)(0x4266A004UL))
+#define bFM3_GPIO_ADE_AN2                      *((volatile unsigned int*)(0x4266A008UL))
+#define bFM3_GPIO_ADE_AN3                      *((volatile unsigned int*)(0x4266A00CUL))
+#define bFM3_GPIO_ADE_AN4                      *((volatile unsigned int*)(0x4266A010UL))
+#define bFM3_GPIO_ADE_AN5                      *((volatile unsigned int*)(0x4266A014UL))
+#define bFM3_GPIO_ADE_AN6                      *((volatile unsigned int*)(0x4266A018UL))
+#define bFM3_GPIO_ADE_AN7                      *((volatile unsigned int*)(0x4266A01CUL))
+#define bFM3_GPIO_ADE_AN8                      *((volatile unsigned int*)(0x4266A020UL))
+#define bFM3_GPIO_ADE_AN9                      *((volatile unsigned int*)(0x4266A024UL))
+#define bFM3_GPIO_ADE_AN10                     *((volatile unsigned int*)(0x4266A028UL))
+#define bFM3_GPIO_ADE_AN11                     *((volatile unsigned int*)(0x4266A02CUL))
+#define bFM3_GPIO_ADE_AN12                     *((volatile unsigned int*)(0x4266A030UL))
+#define bFM3_GPIO_ADE_AN13                     *((volatile unsigned int*)(0x4266A034UL))
+#define bFM3_GPIO_ADE_AN14                     *((volatile unsigned int*)(0x4266A038UL))
+#define bFM3_GPIO_ADE_AN15                     *((volatile unsigned int*)(0x4266A03CUL))
+#define bFM3_GPIO_ADE_AN16                     *((volatile unsigned int*)(0x4266A040UL))
+#define bFM3_GPIO_ADE_AN17                     *((volatile unsigned int*)(0x4266A044UL))
+#define bFM3_GPIO_ADE_AN18                     *((volatile unsigned int*)(0x4266A048UL))
+#define bFM3_GPIO_ADE_AN19                     *((volatile unsigned int*)(0x4266A04CUL))
+#define bFM3_GPIO_ADE_AN20                     *((volatile unsigned int*)(0x4266A050UL))
+#define bFM3_GPIO_ADE_AN21                     *((volatile unsigned int*)(0x4266A054UL))
+#define bFM3_GPIO_ADE_AN22                     *((volatile unsigned int*)(0x4266A058UL))
+#define bFM3_GPIO_ADE_AN23                     *((volatile unsigned int*)(0x4266A05CUL))
+#define bFM3_GPIO_ADE_AN24                     *((volatile unsigned int*)(0x4266A060UL))
+#define bFM3_GPIO_ADE_AN25                     *((volatile unsigned int*)(0x4266A064UL))
+#define bFM3_GPIO_ADE_AN26                     *((volatile unsigned int*)(0x4266A068UL))
+#define bFM3_GPIO_ADE_AN27                     *((volatile unsigned int*)(0x4266A06CUL))
+#define bFM3_GPIO_ADE_AN28                     *((volatile unsigned int*)(0x4266A070UL))
+#define bFM3_GPIO_ADE_AN29                     *((volatile unsigned int*)(0x4266A074UL))
+#define bFM3_GPIO_ADE_AN30                     *((volatile unsigned int*)(0x4266A078UL))
+#define bFM3_GPIO_ADE_AN31                     *((volatile unsigned int*)(0x4266A07CUL))
+#define bFM3_GPIO_SPSR_SUBXC                   *((volatile unsigned int*)(0x4266B000UL))
+#define bFM3_GPIO_SPSR_MAINXC                  *((volatile unsigned int*)(0x4266B008UL))
+#define bFM3_GPIO_SPSR_USB0C                   *((volatile unsigned int*)(0x4266B010UL))
+#define bFM3_GPIO_SPSR_USB1C                   *((volatile unsigned int*)(0x4266B014UL))
+#define bFM3_GPIO_EPFR00_NMIS                  *((volatile unsigned int*)(0x4266C000UL))
+#define bFM3_GPIO_EPFR00_CROUTE0               *((volatile unsigned int*)(0x4266C004UL))
+#define bFM3_GPIO_EPFR00_CROUTE1               *((volatile unsigned int*)(0x4266C008UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE0              *((volatile unsigned int*)(0x4266C018UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE1              *((volatile unsigned int*)(0x4266C01CUL))
+#define bFM3_GPIO_EPFR00_USBP0E                *((volatile unsigned int*)(0x4266C024UL))
+#define bFM3_GPIO_EPFR00_USBP1E                *((volatile unsigned int*)(0x4266C034UL))
+#define bFM3_GPIO_EPFR00_JTAGEN0B              *((volatile unsigned int*)(0x4266C040UL))
+#define bFM3_GPIO_EPFR00_JTAGEN1S              *((volatile unsigned int*)(0x4266C044UL))
+#define bFM3_GPIO_EPFR00_TRC0E                 *((volatile unsigned int*)(0x4266C060UL))
+#define bFM3_GPIO_EPFR00_TRC1E                 *((volatile unsigned int*)(0x4266C064UL))
+#define bFM3_GPIO_EPFR01_RTO00E0               *((volatile unsigned int*)(0x4266C080UL))
+#define bFM3_GPIO_EPFR01_RTO00E1               *((volatile unsigned int*)(0x4266C084UL))
+#define bFM3_GPIO_EPFR01_RTO01E0               *((volatile unsigned int*)(0x4266C088UL))
+#define bFM3_GPIO_EPFR01_RTO01E1               *((volatile unsigned int*)(0x4266C08CUL))
+#define bFM3_GPIO_EPFR01_RTO02E0               *((volatile unsigned int*)(0x4266C090UL))
+#define bFM3_GPIO_EPFR01_RTO02E1               *((volatile unsigned int*)(0x4266C094UL))
+#define bFM3_GPIO_EPFR01_RTO03E0               *((volatile unsigned int*)(0x4266C098UL))
+#define bFM3_GPIO_EPFR01_RTO03E1               *((volatile unsigned int*)(0x4266C09CUL))
+#define bFM3_GPIO_EPFR01_RTO04E0               *((volatile unsigned int*)(0x4266C0A0UL))
+#define bFM3_GPIO_EPFR01_RTO04E1               *((volatile unsigned int*)(0x4266C0A4UL))
+#define bFM3_GPIO_EPFR01_RTO05E0               *((volatile unsigned int*)(0x4266C0A8UL))
+#define bFM3_GPIO_EPFR01_RTO05E1               *((volatile unsigned int*)(0x4266C0ACUL))
+#define bFM3_GPIO_EPFR01_DTTI0C                *((volatile unsigned int*)(0x4266C0B0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S0               *((volatile unsigned int*)(0x4266C0C0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S1               *((volatile unsigned int*)(0x4266C0C4UL))
+#define bFM3_GPIO_EPFR01_FRCK0S0               *((volatile unsigned int*)(0x4266C0C8UL))
+#define bFM3_GPIO_EPFR01_FRCK0S1               *((volatile unsigned int*)(0x4266C0CCUL))
+#define bFM3_GPIO_EPFR01_IC00S0                *((volatile unsigned int*)(0x4266C0D0UL))
+#define bFM3_GPIO_EPFR01_IC00S1                *((volatile unsigned int*)(0x4266C0D4UL))
+#define bFM3_GPIO_EPFR01_IC00S2                *((volatile unsigned int*)(0x4266C0D8UL))
+#define bFM3_GPIO_EPFR01_IC01S0                *((volatile unsigned int*)(0x4266C0DCUL))
+#define bFM3_GPIO_EPFR01_IC01S1                *((volatile unsigned int*)(0x4266C0E0UL))
+#define bFM3_GPIO_EPFR01_IC01S2                *((volatile unsigned int*)(0x4266C0E4UL))
+#define bFM3_GPIO_EPFR01_IC02S0                *((volatile unsigned int*)(0x4266C0E8UL))
+#define bFM3_GPIO_EPFR01_IC02S1                *((volatile unsigned int*)(0x4266C0ECUL))
+#define bFM3_GPIO_EPFR01_IC02S2                *((volatile unsigned int*)(0x4266C0F0UL))
+#define bFM3_GPIO_EPFR01_IC03S0                *((volatile unsigned int*)(0x4266C0F4UL))
+#define bFM3_GPIO_EPFR01_IC03S1                *((volatile unsigned int*)(0x4266C0F8UL))
+#define bFM3_GPIO_EPFR01_IC03S2                *((volatile unsigned int*)(0x4266C0FCUL))
+#define bFM3_GPIO_EPFR02_RTO10E0               *((volatile unsigned int*)(0x4266C100UL))
+#define bFM3_GPIO_EPFR02_RTO10E1               *((volatile unsigned int*)(0x4266C104UL))
+#define bFM3_GPIO_EPFR02_RTO11E0               *((volatile unsigned int*)(0x4266C108UL))
+#define bFM3_GPIO_EPFR02_RTO11E1               *((volatile unsigned int*)(0x4266C10CUL))
+#define bFM3_GPIO_EPFR02_RTO12E0               *((volatile unsigned int*)(0x4266C110UL))
+#define bFM3_GPIO_EPFR02_RTO12E1               *((volatile unsigned int*)(0x4266C114UL))
+#define bFM3_GPIO_EPFR02_RTO13E0               *((volatile unsigned int*)(0x4266C118UL))
+#define bFM3_GPIO_EPFR02_RTO13E1               *((volatile unsigned int*)(0x4266C11CUL))
+#define bFM3_GPIO_EPFR02_RTO14E0               *((volatile unsigned int*)(0x4266C120UL))
+#define bFM3_GPIO_EPFR02_RTO14E1               *((volatile unsigned int*)(0x4266C124UL))
+#define bFM3_GPIO_EPFR02_RTO15E0               *((volatile unsigned int*)(0x4266C128UL))
+#define bFM3_GPIO_EPFR02_RTO15E1               *((volatile unsigned int*)(0x4266C12CUL))
+#define bFM3_GPIO_EPFR02_DTTI1C                *((volatile unsigned int*)(0x4266C130UL))
+#define bFM3_GPIO_EPFR02_DTTI1S0               *((volatile unsigned int*)(0x4266C140UL))
+#define bFM3_GPIO_EPFR02_DTTI1S1               *((volatile unsigned int*)(0x4266C144UL))
+#define bFM3_GPIO_EPFR02_FRCK1S0               *((volatile unsigned int*)(0x4266C148UL))
+#define bFM3_GPIO_EPFR02_FRCK1S1               *((volatile unsigned int*)(0x4266C14CUL))
+#define bFM3_GPIO_EPFR02_IC10S0                *((volatile unsigned int*)(0x4266C150UL))
+#define bFM3_GPIO_EPFR02_IC10S1                *((volatile unsigned int*)(0x4266C154UL))
+#define bFM3_GPIO_EPFR02_IC10S2                *((volatile unsigned int*)(0x4266C158UL))
+#define bFM3_GPIO_EPFR02_IC11S0                *((volatile unsigned int*)(0x4266C15CUL))
+#define bFM3_GPIO_EPFR02_IC11S1                *((volatile unsigned int*)(0x4266C160UL))
+#define bFM3_GPIO_EPFR02_IC11S2                *((volatile unsigned int*)(0x4266C164UL))
+#define bFM3_GPIO_EPFR02_IC12S0                *((volatile unsigned int*)(0x4266C168UL))
+#define bFM3_GPIO_EPFR02_IC12S1                *((volatile unsigned int*)(0x4266C16CUL))
+#define bFM3_GPIO_EPFR02_IC12S2                *((volatile unsigned int*)(0x4266C170UL))
+#define bFM3_GPIO_EPFR02_IC13S0                *((volatile unsigned int*)(0x4266C174UL))
+#define bFM3_GPIO_EPFR02_IC13S1                *((volatile unsigned int*)(0x4266C178UL))
+#define bFM3_GPIO_EPFR02_IC13S2                *((volatile unsigned int*)(0x4266C17CUL))
+#define bFM3_GPIO_EPFR03_RTO20E0               *((volatile unsigned int*)(0x4266C180UL))
+#define bFM3_GPIO_EPFR03_RTO20E1               *((volatile unsigned int*)(0x4266C184UL))
+#define bFM3_GPIO_EPFR03_RTO21E0               *((volatile unsigned int*)(0x4266C188UL))
+#define bFM3_GPIO_EPFR03_RTO21E1               *((volatile unsigned int*)(0x4266C18CUL))
+#define bFM3_GPIO_EPFR03_RTO22E0               *((volatile unsigned int*)(0x4266C190UL))
+#define bFM3_GPIO_EPFR03_RTO22E1               *((volatile unsigned int*)(0x4266C194UL))
+#define bFM3_GPIO_EPFR03_RTO23E0               *((volatile unsigned int*)(0x4266C198UL))
+#define bFM3_GPIO_EPFR03_RTO23E1               *((volatile unsigned int*)(0x4266C19CUL))
+#define bFM3_GPIO_EPFR03_RTO24E0               *((volatile unsigned int*)(0x4266C1A0UL))
+#define bFM3_GPIO_EPFR03_RTO24E1               *((volatile unsigned int*)(0x4266C1A4UL))
+#define bFM3_GPIO_EPFR03_RTO25E0               *((volatile unsigned int*)(0x4266C1A8UL))
+#define bFM3_GPIO_EPFR03_RTO25E1               *((volatile unsigned int*)(0x4266C1ACUL))
+#define bFM3_GPIO_EPFR03_DTTI2C                *((volatile unsigned int*)(0x4266C1B0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S0               *((volatile unsigned int*)(0x4266C1C0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S1               *((volatile unsigned int*)(0x4266C1C4UL))
+#define bFM3_GPIO_EPFR03_FRCK2S0               *((volatile unsigned int*)(0x4266C1C8UL))
+#define bFM3_GPIO_EPFR03_FRCK2S1               *((volatile unsigned int*)(0x4266C1CCUL))
+#define bFM3_GPIO_EPFR03_IC20S0                *((volatile unsigned int*)(0x4266C1D0UL))
+#define bFM3_GPIO_EPFR03_IC20S1                *((volatile unsigned int*)(0x4266C1D4UL))
+#define bFM3_GPIO_EPFR03_IC20S2                *((volatile unsigned int*)(0x4266C1D8UL))
+#define bFM3_GPIO_EPFR03_IC21S0                *((volatile unsigned int*)(0x4266C1DCUL))
+#define bFM3_GPIO_EPFR03_IC21S1                *((volatile unsigned int*)(0x4266C1E0UL))
+#define bFM3_GPIO_EPFR03_IC21S2                *((volatile unsigned int*)(0x4266C1E4UL))
+#define bFM3_GPIO_EPFR03_IC22S0                *((volatile unsigned int*)(0x4266C1E8UL))
+#define bFM3_GPIO_EPFR03_IC22S1                *((volatile unsigned int*)(0x4266C1ECUL))
+#define bFM3_GPIO_EPFR03_IC22S2                *((volatile unsigned int*)(0x4266C1F0UL))
+#define bFM3_GPIO_EPFR03_IC23S0                *((volatile unsigned int*)(0x4266C1F4UL))
+#define bFM3_GPIO_EPFR03_IC23S1                *((volatile unsigned int*)(0x4266C1F8UL))
+#define bFM3_GPIO_EPFR03_IC23S2                *((volatile unsigned int*)(0x4266C1FCUL))
+#define bFM3_GPIO_EPFR04_TIOA0E0               *((volatile unsigned int*)(0x4266C208UL))
+#define bFM3_GPIO_EPFR04_TIOA0E1               *((volatile unsigned int*)(0x4266C20CUL))
+#define bFM3_GPIO_EPFR04_TIOB0S0               *((volatile unsigned int*)(0x4266C210UL))
+#define bFM3_GPIO_EPFR04_TIOB0S1               *((volatile unsigned int*)(0x4266C214UL))
+#define bFM3_GPIO_EPFR04_TIOA1S0               *((volatile unsigned int*)(0x4266C220UL))
+#define bFM3_GPIO_EPFR04_TIOA1S1               *((volatile unsigned int*)(0x4266C224UL))
+#define bFM3_GPIO_EPFR04_TIOA1E0               *((volatile unsigned int*)(0x4266C228UL))
+#define bFM3_GPIO_EPFR04_TIOA1E1               *((volatile unsigned int*)(0x4266C22CUL))
+#define bFM3_GPIO_EPFR04_TIOB1S0               *((volatile unsigned int*)(0x4266C230UL))
+#define bFM3_GPIO_EPFR04_TIOB1S1               *((volatile unsigned int*)(0x4266C234UL))
+#define bFM3_GPIO_EPFR04_TIOA2E0               *((volatile unsigned int*)(0x4266C248UL))
+#define bFM3_GPIO_EPFR04_TIOA2E1               *((volatile unsigned int*)(0x4266C24CUL))
+#define bFM3_GPIO_EPFR04_TIOB2S0               *((volatile unsigned int*)(0x4266C250UL))
+#define bFM3_GPIO_EPFR04_TIOB2S1               *((volatile unsigned int*)(0x4266C254UL))
+#define bFM3_GPIO_EPFR04_TIOA3S0               *((volatile unsigned int*)(0x4266C260UL))
+#define bFM3_GPIO_EPFR04_TIOA3S1               *((volatile unsigned int*)(0x4266C264UL))
+#define bFM3_GPIO_EPFR04_TIOA3E0               *((volatile unsigned int*)(0x4266C268UL))
+#define bFM3_GPIO_EPFR04_TIOA3E1               *((volatile unsigned int*)(0x4266C26CUL))
+#define bFM3_GPIO_EPFR04_TIOB3S0               *((volatile unsigned int*)(0x4266C270UL))
+#define bFM3_GPIO_EPFR04_TIOB3S1               *((volatile unsigned int*)(0x4266C274UL))
+#define bFM3_GPIO_EPFR05_TIOA4E0               *((volatile unsigned int*)(0x4266C288UL))
+#define bFM3_GPIO_EPFR05_TIOA4E1               *((volatile unsigned int*)(0x4266C28CUL))
+#define bFM3_GPIO_EPFR05_TIOB4S0               *((volatile unsigned int*)(0x4266C290UL))
+#define bFM3_GPIO_EPFR05_TIOB4S1               *((volatile unsigned int*)(0x4266C294UL))
+#define bFM3_GPIO_EPFR05_TIOA5S0               *((volatile unsigned int*)(0x4266C2A0UL))
+#define bFM3_GPIO_EPFR05_TIOA5S1               *((volatile unsigned int*)(0x4266C2A4UL))
+#define bFM3_GPIO_EPFR05_TIOA5E0               *((volatile unsigned int*)(0x4266C2A8UL))
+#define bFM3_GPIO_EPFR05_TIOA5E1               *((volatile unsigned int*)(0x4266C2ACUL))
+#define bFM3_GPIO_EPFR05_TIOB5S0               *((volatile unsigned int*)(0x4266C2B0UL))
+#define bFM3_GPIO_EPFR05_TIOB5S1               *((volatile unsigned int*)(0x4266C2B4UL))
+#define bFM3_GPIO_EPFR05_TIOA6E0               *((volatile unsigned int*)(0x4266C2C8UL))
+#define bFM3_GPIO_EPFR05_TIOA6E1               *((volatile unsigned int*)(0x4266C2CCUL))
+#define bFM3_GPIO_EPFR05_TIOB6S0               *((volatile unsigned int*)(0x4266C2D0UL))
+#define bFM3_GPIO_EPFR05_TIOB6S1               *((volatile unsigned int*)(0x4266C2D4UL))
+#define bFM3_GPIO_EPFR05_TIOA7S0               *((volatile unsigned int*)(0x4266C2E0UL))
+#define bFM3_GPIO_EPFR05_TIOA7S1               *((volatile unsigned int*)(0x4266C2E4UL))
+#define bFM3_GPIO_EPFR05_TIOA7E0               *((volatile unsigned int*)(0x4266C2E8UL))
+#define bFM3_GPIO_EPFR05_TIOA7E1               *((volatile unsigned int*)(0x4266C2ECUL))
+#define bFM3_GPIO_EPFR05_TIOB7S0               *((volatile unsigned int*)(0x4266C2F0UL))
+#define bFM3_GPIO_EPFR05_TIOB7S1               *((volatile unsigned int*)(0x4266C2F4UL))
+#define bFM3_GPIO_EPFR06_EINT00S0              *((volatile unsigned int*)(0x4266C300UL))
+#define bFM3_GPIO_EPFR06_EINT00S1              *((volatile unsigned int*)(0x4266C304UL))
+#define bFM3_GPIO_EPFR06_EINT01S0              *((volatile unsigned int*)(0x4266C308UL))
+#define bFM3_GPIO_EPFR06_EINT01S1              *((volatile unsigned int*)(0x4266C30CUL))
+#define bFM3_GPIO_EPFR06_EINT02S0              *((volatile unsigned int*)(0x4266C310UL))
+#define bFM3_GPIO_EPFR06_EINT02S1              *((volatile unsigned int*)(0x4266C314UL))
+#define bFM3_GPIO_EPFR06_EINT03S0              *((volatile unsigned int*)(0x4266C318UL))
+#define bFM3_GPIO_EPFR06_EINT03S1              *((volatile unsigned int*)(0x4266C31CUL))
+#define bFM3_GPIO_EPFR06_EINT04S0              *((volatile unsigned int*)(0x4266C320UL))
+#define bFM3_GPIO_EPFR06_EINT04S1              *((volatile unsigned int*)(0x4266C324UL))
+#define bFM3_GPIO_EPFR06_EINT05S0              *((volatile unsigned int*)(0x4266C328UL))
+#define bFM3_GPIO_EPFR06_EINT05S1              *((volatile unsigned int*)(0x4266C32CUL))
+#define bFM3_GPIO_EPFR06_EINT06S0              *((volatile unsigned int*)(0x4266C330UL))
+#define bFM3_GPIO_EPFR06_EINT06S1              *((volatile unsigned int*)(0x4266C334UL))
+#define bFM3_GPIO_EPFR06_EINT07S0              *((volatile unsigned int*)(0x4266C338UL))
+#define bFM3_GPIO_EPFR06_EINT07S1              *((volatile unsigned int*)(0x4266C33CUL))
+#define bFM3_GPIO_EPFR06_EINT08S0              *((volatile unsigned int*)(0x4266C340UL))
+#define bFM3_GPIO_EPFR06_EINT08S1              *((volatile unsigned int*)(0x4266C344UL))
+#define bFM3_GPIO_EPFR06_EINT09S0              *((volatile unsigned int*)(0x4266C348UL))
+#define bFM3_GPIO_EPFR06_EINT09S1              *((volatile unsigned int*)(0x4266C34CUL))
+#define bFM3_GPIO_EPFR06_EINT10S0              *((volatile unsigned int*)(0x4266C350UL))
+#define bFM3_GPIO_EPFR06_EINT10S1              *((volatile unsigned int*)(0x4266C354UL))
+#define bFM3_GPIO_EPFR06_EINT11S0              *((volatile unsigned int*)(0x4266C358UL))
+#define bFM3_GPIO_EPFR06_EINT11S1              *((volatile unsigned int*)(0x4266C35CUL))
+#define bFM3_GPIO_EPFR06_EINT12S0              *((volatile unsigned int*)(0x4266C360UL))
+#define bFM3_GPIO_EPFR06_EINT12S1              *((volatile unsigned int*)(0x4266C364UL))
+#define bFM3_GPIO_EPFR06_EINT13S0              *((volatile unsigned int*)(0x4266C368UL))
+#define bFM3_GPIO_EPFR06_EINT13S1              *((volatile unsigned int*)(0x4266C36CUL))
+#define bFM3_GPIO_EPFR06_EINT14S0              *((volatile unsigned int*)(0x4266C370UL))
+#define bFM3_GPIO_EPFR06_EINT14S1              *((volatile unsigned int*)(0x4266C374UL))
+#define bFM3_GPIO_EPFR06_EINT15S0              *((volatile unsigned int*)(0x4266C378UL))
+#define bFM3_GPIO_EPFR06_EINT15S1              *((volatile unsigned int*)(0x4266C37CUL))
+#define bFM3_GPIO_EPFR07_SIN0S0                *((volatile unsigned int*)(0x4266C390UL))
+#define bFM3_GPIO_EPFR07_SIN0S1                *((volatile unsigned int*)(0x4266C394UL))
+#define bFM3_GPIO_EPFR07_SOT0B0                *((volatile unsigned int*)(0x4266C398UL))
+#define bFM3_GPIO_EPFR07_SOT0B1                *((volatile unsigned int*)(0x4266C39CUL))
+#define bFM3_GPIO_EPFR07_SCK0B0                *((volatile unsigned int*)(0x4266C3A0UL))
+#define bFM3_GPIO_EPFR07_SCK0B1                *((volatile unsigned int*)(0x4266C3A4UL))
+#define bFM3_GPIO_EPFR07_SIN1S0                *((volatile unsigned int*)(0x4266C3A8UL))
+#define bFM3_GPIO_EPFR07_SIN1S1                *((volatile unsigned int*)(0x4266C3ACUL))
+#define bFM3_GPIO_EPFR07_SOT1B0                *((volatile unsigned int*)(0x4266C3B0UL))
+#define bFM3_GPIO_EPFR07_SOT1B1                *((volatile unsigned int*)(0x4266C3B4UL))
+#define bFM3_GPIO_EPFR07_SCK1B0                *((volatile unsigned int*)(0x4266C3B8UL))
+#define bFM3_GPIO_EPFR07_SCK1B1                *((volatile unsigned int*)(0x4266C3BCUL))
+#define bFM3_GPIO_EPFR07_SIN2S0                *((volatile unsigned int*)(0x4266C3C0UL))
+#define bFM3_GPIO_EPFR07_SIN2S1                *((volatile unsigned int*)(0x4266C3C4UL))
+#define bFM3_GPIO_EPFR07_SOT2B0                *((volatile unsigned int*)(0x4266C3C8UL))
+#define bFM3_GPIO_EPFR07_SOT2B1                *((volatile unsigned int*)(0x4266C3CCUL))
+#define bFM3_GPIO_EPFR07_SCK2B0                *((volatile unsigned int*)(0x4266C3D0UL))
+#define bFM3_GPIO_EPFR07_SCK2B1                *((volatile unsigned int*)(0x4266C3D4UL))
+#define bFM3_GPIO_EPFR07_SIN3S0                *((volatile unsigned int*)(0x4266C3D8UL))
+#define bFM3_GPIO_EPFR07_SIN3S1                *((volatile unsigned int*)(0x4266C3DCUL))
+#define bFM3_GPIO_EPFR07_SOT3B0                *((volatile unsigned int*)(0x4266C3E0UL))
+#define bFM3_GPIO_EPFR07_SOT3B1                *((volatile unsigned int*)(0x4266C3E4UL))
+#define bFM3_GPIO_EPFR07_SCK3B0                *((volatile unsigned int*)(0x4266C3E8UL))
+#define bFM3_GPIO_EPFR07_SCK3B1                *((volatile unsigned int*)(0x4266C3ECUL))
+#define bFM3_GPIO_EPFR08_RTS4E0                *((volatile unsigned int*)(0x4266C400UL))
+#define bFM3_GPIO_EPFR08_RTS4E1                *((volatile unsigned int*)(0x4266C404UL))
+#define bFM3_GPIO_EPFR08_CTS4S0                *((volatile unsigned int*)(0x4266C408UL))
+#define bFM3_GPIO_EPFR08_CTS4S1                *((volatile unsigned int*)(0x4266C40CUL))
+#define bFM3_GPIO_EPFR08_SIN4S0                *((volatile unsigned int*)(0x4266C410UL))
+#define bFM3_GPIO_EPFR08_SIN4S1                *((volatile unsigned int*)(0x4266C414UL))
+#define bFM3_GPIO_EPFR08_SOT4B0                *((volatile unsigned int*)(0x4266C418UL))
+#define bFM3_GPIO_EPFR08_SOT4B1                *((volatile unsigned int*)(0x4266C41CUL))
+#define bFM3_GPIO_EPFR08_SCK4B0                *((volatile unsigned int*)(0x4266C420UL))
+#define bFM3_GPIO_EPFR08_SCK4B1                *((volatile unsigned int*)(0x4266C424UL))
+#define bFM3_GPIO_EPFR08_SIN5S0                *((volatile unsigned int*)(0x4266C428UL))
+#define bFM3_GPIO_EPFR08_SIN5S1                *((volatile unsigned int*)(0x4266C42CUL))
+#define bFM3_GPIO_EPFR08_SOT5B0                *((volatile unsigned int*)(0x4266C430UL))
+#define bFM3_GPIO_EPFR08_SOT5B1                *((volatile unsigned int*)(0x4266C434UL))
+#define bFM3_GPIO_EPFR08_SCK5B0                *((volatile unsigned int*)(0x4266C438UL))
+#define bFM3_GPIO_EPFR08_SCK5B1                *((volatile unsigned int*)(0x4266C43CUL))
+#define bFM3_GPIO_EPFR08_SIN6S0                *((volatile unsigned int*)(0x4266C440UL))
+#define bFM3_GPIO_EPFR08_SIN6S1                *((volatile unsigned int*)(0x4266C444UL))
+#define bFM3_GPIO_EPFR08_SOT6B0                *((volatile unsigned int*)(0x4266C448UL))
+#define bFM3_GPIO_EPFR08_SOT6B1                *((volatile unsigned int*)(0x4266C44CUL))
+#define bFM3_GPIO_EPFR08_SCK6B0                *((volatile unsigned int*)(0x4266C450UL))
+#define bFM3_GPIO_EPFR08_SCK6B1                *((volatile unsigned int*)(0x4266C454UL))
+#define bFM3_GPIO_EPFR08_SIN7S0                *((volatile unsigned int*)(0x4266C458UL))
+#define bFM3_GPIO_EPFR08_SIN7S1                *((volatile unsigned int*)(0x4266C45CUL))
+#define bFM3_GPIO_EPFR08_SOT7B0                *((volatile unsigned int*)(0x4266C460UL))
+#define bFM3_GPIO_EPFR08_SOT7B1                *((volatile unsigned int*)(0x4266C464UL))
+#define bFM3_GPIO_EPFR08_SCK7B0                *((volatile unsigned int*)(0x4266C468UL))
+#define bFM3_GPIO_EPFR08_SCK7B1                *((volatile unsigned int*)(0x4266C46CUL))
+#define bFM3_GPIO_EPFR09_QAIN0S0               *((volatile unsigned int*)(0x4266C480UL))
+#define bFM3_GPIO_EPFR09_QAIN0S1               *((volatile unsigned int*)(0x4266C484UL))
+#define bFM3_GPIO_EPFR09_QBIN0S0               *((volatile unsigned int*)(0x4266C488UL))
+#define bFM3_GPIO_EPFR09_QBIN0S1               *((volatile unsigned int*)(0x4266C48CUL))
+#define bFM3_GPIO_EPFR09_QZIN0S0               *((volatile unsigned int*)(0x4266C490UL))
+#define bFM3_GPIO_EPFR09_QZIN0S1               *((volatile unsigned int*)(0x4266C494UL))
+#define bFM3_GPIO_EPFR09_QAIN1S0               *((volatile unsigned int*)(0x4266C498UL))
+#define bFM3_GPIO_EPFR09_QAIN1S1               *((volatile unsigned int*)(0x4266C49CUL))
+#define bFM3_GPIO_EPFR09_QBIN1S0               *((volatile unsigned int*)(0x4266C4A0UL))
+#define bFM3_GPIO_EPFR09_QBIN1S1               *((volatile unsigned int*)(0x4266C4A4UL))
+#define bFM3_GPIO_EPFR09_QZIN1S0               *((volatile unsigned int*)(0x4266C4A8UL))
+#define bFM3_GPIO_EPFR09_QZIN1S1               *((volatile unsigned int*)(0x4266C4ACUL))
+#define bFM3_GPIO_EPFR09_ADTRG0S0              *((volatile unsigned int*)(0x4266C4B0UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S1              *((volatile unsigned int*)(0x4266C4B4UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S2              *((volatile unsigned int*)(0x4266C4B8UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S3              *((volatile unsigned int*)(0x4266C4BCUL))
+#define bFM3_GPIO_EPFR09_ADTRG1S0              *((volatile unsigned int*)(0x4266C4C0UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S1              *((volatile unsigned int*)(0x4266C4C4UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S2              *((volatile unsigned int*)(0x4266C4C8UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S3              *((volatile unsigned int*)(0x4266C4CCUL))
+#define bFM3_GPIO_EPFR09_ADTRG2S0              *((volatile unsigned int*)(0x4266C4D0UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S1              *((volatile unsigned int*)(0x4266C4D4UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S2              *((volatile unsigned int*)(0x4266C4D8UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S3              *((volatile unsigned int*)(0x4266C4DCUL))
+#define bFM3_GPIO_EPFR10_UEDEFB                *((volatile unsigned int*)(0x4266C500UL))
+#define bFM3_GPIO_EPFR10_UEDTHB                *((volatile unsigned int*)(0x4266C504UL))
+#define bFM3_GPIO_EPFR10_UECLKE                *((volatile unsigned int*)(0x4266C508UL))
+#define bFM3_GPIO_EPFR10_UEWEXE                *((volatile unsigned int*)(0x4266C50CUL))
+#define bFM3_GPIO_EPFR10_UEDQME                *((volatile unsigned int*)(0x4266C510UL))
+#define bFM3_GPIO_EPFR10_UEOEXE                *((volatile unsigned int*)(0x4266C514UL))
+#define bFM3_GPIO_EPFR10_UEFLSE                *((volatile unsigned int*)(0x4266C518UL))
+#define bFM3_GPIO_EPFR10_UECS1E                *((volatile unsigned int*)(0x4266C51CUL))
+#define bFM3_GPIO_EPFR10_UECS2E                *((volatile unsigned int*)(0x4266C520UL))
+#define bFM3_GPIO_EPFR10_UECS3E                *((volatile unsigned int*)(0x4266C524UL))
+#define bFM3_GPIO_EPFR10_UECS4E                *((volatile unsigned int*)(0x4266C528UL))
+#define bFM3_GPIO_EPFR10_UECS5E                *((volatile unsigned int*)(0x4266C52CUL))
+#define bFM3_GPIO_EPFR10_UECS6E                *((volatile unsigned int*)(0x4266C530UL))
+#define bFM3_GPIO_EPFR10_UECS7E                *((volatile unsigned int*)(0x4266C534UL))
+#define bFM3_GPIO_EPFR10_UEAOOE                *((volatile unsigned int*)(0x4266C538UL))
+#define bFM3_GPIO_EPFR10_UEA08E                *((volatile unsigned int*)(0x4266C53CUL))
+#define bFM3_GPIO_EPFR10_UEA09E                *((volatile unsigned int*)(0x4266C540UL))
+#define bFM3_GPIO_EPFR10_UEA10E                *((volatile unsigned int*)(0x4266C544UL))
+#define bFM3_GPIO_EPFR10_UEA11E                *((volatile unsigned int*)(0x4266C548UL))
+#define bFM3_GPIO_EPFR10_UEA12E                *((volatile unsigned int*)(0x4266C54CUL))
+#define bFM3_GPIO_EPFR10_UEA13E                *((volatile unsigned int*)(0x4266C550UL))
+#define bFM3_GPIO_EPFR10_UEA14E                *((volatile unsigned int*)(0x4266C554UL))
+#define bFM3_GPIO_EPFR10_UEA15E                *((volatile unsigned int*)(0x4266C558UL))
+#define bFM3_GPIO_EPFR10_UEA16E                *((volatile unsigned int*)(0x4266C55CUL))
+#define bFM3_GPIO_EPFR10_UEA17E                *((volatile unsigned int*)(0x4266C560UL))
+#define bFM3_GPIO_EPFR10_UEA18E                *((volatile unsigned int*)(0x4266C564UL))
+#define bFM3_GPIO_EPFR10_UEA19E                *((volatile unsigned int*)(0x4266C568UL))
+#define bFM3_GPIO_EPFR10_UEA20E                *((volatile unsigned int*)(0x4266C56CUL))
+#define bFM3_GPIO_EPFR10_UEA21E                *((volatile unsigned int*)(0x4266C570UL))
+#define bFM3_GPIO_EPFR10_UEA22E                *((volatile unsigned int*)(0x4266C574UL))
+#define bFM3_GPIO_EPFR10_UEA23E                *((volatile unsigned int*)(0x4266C578UL))
+#define bFM3_GPIO_EPFR10_UEA24E                *((volatile unsigned int*)(0x4266C57CUL))
+#define bFM3_GPIO_EPFR11_UEALEE                *((volatile unsigned int*)(0x4266C580UL))
+#define bFM3_GPIO_EPFR11_UECS0E                *((volatile unsigned int*)(0x4266C584UL))
+#define bFM3_GPIO_EPFR11_UEA01E                *((volatile unsigned int*)(0x4266C588UL))
+#define bFM3_GPIO_EPFR11_UEA02E                *((volatile unsigned int*)(0x4266C58CUL))
+#define bFM3_GPIO_EPFR11_UEA03E                *((volatile unsigned int*)(0x4266C590UL))
+#define bFM3_GPIO_EPFR11_UEA04E                *((volatile unsigned int*)(0x4266C594UL))
+#define bFM3_GPIO_EPFR11_UEA05E                *((volatile unsigned int*)(0x4266C598UL))
+#define bFM3_GPIO_EPFR11_UEA06E                *((volatile unsigned int*)(0x4266C59CUL))
+#define bFM3_GPIO_EPFR11_UEA07E                *((volatile unsigned int*)(0x4266C5A0UL))
+#define bFM3_GPIO_EPFR11_UED00B                *((volatile unsigned int*)(0x4266C5A4UL))
+#define bFM3_GPIO_EPFR11_UED01B                *((volatile unsigned int*)(0x4266C5A8UL))
+#define bFM3_GPIO_EPFR11_UED02B                *((volatile unsigned int*)(0x4266C5ACUL))
+#define bFM3_GPIO_EPFR11_UED03B                *((volatile unsigned int*)(0x4266C5B0UL))
+#define bFM3_GPIO_EPFR11_UED04B                *((volatile unsigned int*)(0x4266C5B4UL))
+#define bFM3_GPIO_EPFR11_UED05B                *((volatile unsigned int*)(0x4266C5B8UL))
+#define bFM3_GPIO_EPFR11_UED06B                *((volatile unsigned int*)(0x4266C5BCUL))
+#define bFM3_GPIO_EPFR11_UED07B                *((volatile unsigned int*)(0x4266C5C0UL))
+#define bFM3_GPIO_EPFR11_UED08B                *((volatile unsigned int*)(0x4266C5C4UL))
+#define bFM3_GPIO_EPFR11_UED09B                *((volatile unsigned int*)(0x4266C5C8UL))
+#define bFM3_GPIO_EPFR11_UED10B                *((volatile unsigned int*)(0x4266C5CCUL))
+#define bFM3_GPIO_EPFR11_UED11B                *((volatile unsigned int*)(0x4266C5D0UL))
+#define bFM3_GPIO_EPFR11_UED12B                *((volatile unsigned int*)(0x4266C5D4UL))
+#define bFM3_GPIO_EPFR11_UED13B                *((volatile unsigned int*)(0x4266C5D8UL))
+#define bFM3_GPIO_EPFR11_UED14B                *((volatile unsigned int*)(0x4266C5DCUL))
+#define bFM3_GPIO_EPFR11_UED15B                *((volatile unsigned int*)(0x4266C5E0UL))
+#define bFM3_GPIO_EPFR11_UERLC                 *((volatile unsigned int*)(0x4266C5E4UL))
+#define bFM3_GPIO_EPFR12_TIOA8E0               *((volatile unsigned int*)(0x4266C608UL))
+#define bFM3_GPIO_EPFR12_TIOA8E1               *((volatile unsigned int*)(0x4266C60CUL))
+#define bFM3_GPIO_EPFR12_TIOB8S0               *((volatile unsigned int*)(0x4266C610UL))
+#define bFM3_GPIO_EPFR12_TIOB8S1               *((volatile unsigned int*)(0x4266C614UL))
+#define bFM3_GPIO_EPFR12_TIOA9S0               *((volatile unsigned int*)(0x4266C620UL))
+#define bFM3_GPIO_EPFR12_TIOA9S1               *((volatile unsigned int*)(0x4266C624UL))
+#define bFM3_GPIO_EPFR12_TIOA9E0               *((volatile unsigned int*)(0x4266C628UL))
+#define bFM3_GPIO_EPFR12_TIOA9E1               *((volatile unsigned int*)(0x4266C62CUL))
+#define bFM3_GPIO_EPFR12_TIOB9S0               *((volatile unsigned int*)(0x4266C630UL))
+#define bFM3_GPIO_EPFR12_TIOB9S1               *((volatile unsigned int*)(0x4266C634UL))
+#define bFM3_GPIO_EPFR12_TIOA10E0              *((volatile unsigned int*)(0x4266C648UL))
+#define bFM3_GPIO_EPFR12_TIOA10E1              *((volatile unsigned int*)(0x4266C64CUL))
+#define bFM3_GPIO_EPFR12_TIOB10S0              *((volatile unsigned int*)(0x4266C650UL))
+#define bFM3_GPIO_EPFR12_TIOB10S1              *((volatile unsigned int*)(0x4266C654UL))
+#define bFM3_GPIO_EPFR12_TIOA11S0              *((volatile unsigned int*)(0x4266C660UL))
+#define bFM3_GPIO_EPFR12_TIOA11S1              *((volatile unsigned int*)(0x4266C664UL))
+#define bFM3_GPIO_EPFR12_TIOA11E0              *((volatile unsigned int*)(0x4266C668UL))
+#define bFM3_GPIO_EPFR12_TIOA11E1              *((volatile unsigned int*)(0x4266C66CUL))
+#define bFM3_GPIO_EPFR12_TIOB11S0              *((volatile unsigned int*)(0x4266C670UL))
+#define bFM3_GPIO_EPFR12_TIOB11S1              *((volatile unsigned int*)(0x4266C674UL))
+#define bFM3_GPIO_EPFR13_TIOA12E0              *((volatile unsigned int*)(0x4266C688UL))
+#define bFM3_GPIO_EPFR13_TIOA12E1              *((volatile unsigned int*)(0x4266C68CUL))
+#define bFM3_GPIO_EPFR13_TIOB12S0              *((volatile unsigned int*)(0x4266C690UL))
+#define bFM3_GPIO_EPFR13_TIOB12S1              *((volatile unsigned int*)(0x4266C694UL))
+#define bFM3_GPIO_EPFR13_TIOA13S0              *((volatile unsigned int*)(0x4266C6A0UL))
+#define bFM3_GPIO_EPFR13_TIOA13S1              *((volatile unsigned int*)(0x4266C6A4UL))
+#define bFM3_GPIO_EPFR13_TIOA13E0              *((volatile unsigned int*)(0x4266C6A8UL))
+#define bFM3_GPIO_EPFR13_TIOA13E1              *((volatile unsigned int*)(0x4266C6ACUL))
+#define bFM3_GPIO_EPFR13_TIOB13S0              *((volatile unsigned int*)(0x4266C6B0UL))
+#define bFM3_GPIO_EPFR13_TIOB13S1              *((volatile unsigned int*)(0x4266C6B4UL))
+#define bFM3_GPIO_EPFR13_TIOA14E0              *((volatile unsigned int*)(0x4266C6C8UL))
+#define bFM3_GPIO_EPFR13_TIOA14E1              *((volatile unsigned int*)(0x4266C6CCUL))
+#define bFM3_GPIO_EPFR13_TIOB14S0              *((volatile unsigned int*)(0x4266C6D0UL))
+#define bFM3_GPIO_EPFR13_TIOB14S1              *((volatile unsigned int*)(0x4266C6D4UL))
+#define bFM3_GPIO_EPFR13_TIOA15S0              *((volatile unsigned int*)(0x4266C6E0UL))
+#define bFM3_GPIO_EPFR13_TIOA15S1              *((volatile unsigned int*)(0x4266C6E4UL))
+#define bFM3_GPIO_EPFR13_TIOA15E0              *((volatile unsigned int*)(0x4266C6E8UL))
+#define bFM3_GPIO_EPFR13_TIOA15E1              *((volatile unsigned int*)(0x4266C6ECUL))
+#define bFM3_GPIO_EPFR13_TIOB15S0              *((volatile unsigned int*)(0x4266C6F0UL))
+#define bFM3_GPIO_EPFR13_TIOB15S1              *((volatile unsigned int*)(0x4266C6F4UL))
+#define bFM3_GPIO_EPFR14_QAIN2S0               *((volatile unsigned int*)(0x4266C700UL))
+#define bFM3_GPIO_EPFR14_QAIN2S1               *((volatile unsigned int*)(0x4266C704UL))
+#define bFM3_GPIO_EPFR14_QBIN2S0               *((volatile unsigned int*)(0x4266C708UL))
+#define bFM3_GPIO_EPFR14_QBIN2S1               *((volatile unsigned int*)(0x4266C70CUL))
+#define bFM3_GPIO_EPFR14_QZIN2S0               *((volatile unsigned int*)(0x4266C710UL))
+#define bFM3_GPIO_EPFR14_QZIN2S1               *((volatile unsigned int*)(0x4266C714UL))
+#define bFM3_GPIO_EPFR14_E_TD0E                *((volatile unsigned int*)(0x4266C748UL))
+#define bFM3_GPIO_EPFR14_E_TD1E                *((volatile unsigned int*)(0x4266C74CUL))
+#define bFM3_GPIO_EPFR14_E_TE0E                *((volatile unsigned int*)(0x4266C750UL))
+#define bFM3_GPIO_EPFR14_E_TE1E                *((volatile unsigned int*)(0x4266C754UL))
+#define bFM3_GPIO_EPFR14_E_MC0E                *((volatile unsigned int*)(0x4266C758UL))
+#define bFM3_GPIO_EPFR14_E_MC1B                *((volatile unsigned int*)(0x4266C75CUL))
+#define bFM3_GPIO_EPFR14_E_MD0B                *((volatile unsigned int*)(0x4266C760UL))
+#define bFM3_GPIO_EPFR14_E_MD1B                *((volatile unsigned int*)(0x4266C764UL))
+#define bFM3_GPIO_EPFR14_E_CKE                 *((volatile unsigned int*)(0x4266C768UL))
+#define bFM3_GPIO_EPFR14_E_PSE                 *((volatile unsigned int*)(0x4266C76CUL))
+#define bFM3_GPIO_EPFR14_E_SPLC0               *((volatile unsigned int*)(0x4266C770UL))
+#define bFM3_GPIO_EPFR14_E_SPLC1               *((volatile unsigned int*)(0x4266C774UL))
+#define bFM3_GPIO_EPFR15_EINT16S0              *((volatile unsigned int*)(0x4266C780UL))
+#define bFM3_GPIO_EPFR15_EINT16S1              *((volatile unsigned int*)(0x4266C784UL))
+#define bFM3_GPIO_EPFR15_EINT17S0              *((volatile unsigned int*)(0x4266C788UL))
+#define bFM3_GPIO_EPFR15_EINT17S1              *((volatile unsigned int*)(0x4266C78CUL))
+#define bFM3_GPIO_EPFR15_EINT18S0              *((volatile unsigned int*)(0x4266C790UL))
+#define bFM3_GPIO_EPFR15_EINT18S1              *((volatile unsigned int*)(0x4266C794UL))
+#define bFM3_GPIO_EPFR15_EINT19S0              *((volatile unsigned int*)(0x4266C798UL))
+#define bFM3_GPIO_EPFR15_EINT19S1              *((volatile unsigned int*)(0x4266C79CUL))
+#define bFM3_GPIO_EPFR15_EINT20S0              *((volatile unsigned int*)(0x4266C7A0UL))
+#define bFM3_GPIO_EPFR15_EINT20S1              *((volatile unsigned int*)(0x4266C7A4UL))
+#define bFM3_GPIO_EPFR15_EINT21S0              *((volatile unsigned int*)(0x4266C7A8UL))
+#define bFM3_GPIO_EPFR15_EINT21S1              *((volatile unsigned int*)(0x4266C7ACUL))
+#define bFM3_GPIO_EPFR15_EINT22S0              *((volatile unsigned int*)(0x4266C7B0UL))
+#define bFM3_GPIO_EPFR15_EINT22S1              *((volatile unsigned int*)(0x4266C7B4UL))
+#define bFM3_GPIO_EPFR15_EINT23S0              *((volatile unsigned int*)(0x4266C7B8UL))
+#define bFM3_GPIO_EPFR15_EINT23S1              *((volatile unsigned int*)(0x4266C7BCUL))
+#define bFM3_GPIO_EPFR15_EINT24S0              *((volatile unsigned int*)(0x4266C7C0UL))
+#define bFM3_GPIO_EPFR15_EINT24S1              *((volatile unsigned int*)(0x4266C7C4UL))
+#define bFM3_GPIO_EPFR15_EINT25S0              *((volatile unsigned int*)(0x4266C7C8UL))
+#define bFM3_GPIO_EPFR15_EINT25S1              *((volatile unsigned int*)(0x4266C7CCUL))
+#define bFM3_GPIO_EPFR15_EINT26S0              *((volatile unsigned int*)(0x4266C7D0UL))
+#define bFM3_GPIO_EPFR15_EINT26S1              *((volatile unsigned int*)(0x4266C7D4UL))
+#define bFM3_GPIO_EPFR15_EINT27S0              *((volatile unsigned int*)(0x4266C7D8UL))
+#define bFM3_GPIO_EPFR15_EINT27S1              *((volatile unsigned int*)(0x4266C7DCUL))
+#define bFM3_GPIO_EPFR15_EINT28S0              *((volatile unsigned int*)(0x4266C7E0UL))
+#define bFM3_GPIO_EPFR15_EINT28S1              *((volatile unsigned int*)(0x4266C7E4UL))
+#define bFM3_GPIO_EPFR15_EINT29S0              *((volatile unsigned int*)(0x4266C7E8UL))
+#define bFM3_GPIO_EPFR15_EINT29S1              *((volatile unsigned int*)(0x4266C7ECUL))
+#define bFM3_GPIO_EPFR15_EINT30S0              *((volatile unsigned int*)(0x4266C7F0UL))
+#define bFM3_GPIO_EPFR15_EINT30S1              *((volatile unsigned int*)(0x4266C7F4UL))
+#define bFM3_GPIO_EPFR15_EINT31S0              *((volatile unsigned int*)(0x4266C7F8UL))
+#define bFM3_GPIO_EPFR15_EINT31S1              *((volatile unsigned int*)(0x4266C7FCUL))
+#define bFM3_GPIO_PZR0_P0                      *((volatile unsigned int*)(0x4266E000UL))
+#define bFM3_GPIO_PZR0_P1                      *((volatile unsigned int*)(0x4266E004UL))
+#define bFM3_GPIO_PZR0_P2                      *((volatile unsigned int*)(0x4266E008UL))
+#define bFM3_GPIO_PZR0_P3                      *((volatile unsigned int*)(0x4266E00CUL))
+#define bFM3_GPIO_PZR0_P4                      *((volatile unsigned int*)(0x4266E010UL))
+#define bFM3_GPIO_PZR0_P5                      *((volatile unsigned int*)(0x4266E014UL))
+#define bFM3_GPIO_PZR0_P6                      *((volatile unsigned int*)(0x4266E018UL))
+#define bFM3_GPIO_PZR0_P7                      *((volatile unsigned int*)(0x4266E01CUL))
+#define bFM3_GPIO_PZR0_P8                      *((volatile unsigned int*)(0x4266E020UL))
+#define bFM3_GPIO_PZR0_P9                      *((volatile unsigned int*)(0x4266E024UL))
+#define bFM3_GPIO_PZR1_P0                      *((volatile unsigned int*)(0x4266E080UL))
+#define bFM3_GPIO_PZR1_P1                      *((volatile unsigned int*)(0x4266E084UL))
+#define bFM3_GPIO_PZR1_P2                      *((volatile unsigned int*)(0x4266E088UL))
+#define bFM3_GPIO_PZR1_P3                      *((volatile unsigned int*)(0x4266E08CUL))
+#define bFM3_GPIO_PZR1_P4                      *((volatile unsigned int*)(0x4266E090UL))
+#define bFM3_GPIO_PZR1_P5                      *((volatile unsigned int*)(0x4266E094UL))
+#define bFM3_GPIO_PZR1_P6                      *((volatile unsigned int*)(0x4266E098UL))
+#define bFM3_GPIO_PZR1_P7                      *((volatile unsigned int*)(0x4266E09CUL))
+#define bFM3_GPIO_PZR1_P8                      *((volatile unsigned int*)(0x4266E0A0UL))
+#define bFM3_GPIO_PZR1_P9                      *((volatile unsigned int*)(0x4266E0A4UL))
+#define bFM3_GPIO_PZR1_PA                      *((volatile unsigned int*)(0x4266E0A8UL))
+#define bFM3_GPIO_PZR1_PB                      *((volatile unsigned int*)(0x4266E0ACUL))
+#define bFM3_GPIO_PZR1_PC                      *((volatile unsigned int*)(0x4266E0B0UL))
+#define bFM3_GPIO_PZR1_PD                      *((volatile unsigned int*)(0x4266E0B4UL))
+#define bFM3_GPIO_PZR1_PE                      *((volatile unsigned int*)(0x4266E0B8UL))
+#define bFM3_GPIO_PZR1_PF                      *((volatile unsigned int*)(0x4266E0BCUL))
+#define bFM3_GPIO_PZR2_P0                      *((volatile unsigned int*)(0x4266E100UL))
+#define bFM3_GPIO_PZR2_P1                      *((volatile unsigned int*)(0x4266E104UL))
+#define bFM3_GPIO_PZR2_P2                      *((volatile unsigned int*)(0x4266E108UL))
+#define bFM3_GPIO_PZR2_P3                      *((volatile unsigned int*)(0x4266E10CUL))
+#define bFM3_GPIO_PZR2_P4                      *((volatile unsigned int*)(0x4266E110UL))
+#define bFM3_GPIO_PZR2_P5                      *((volatile unsigned int*)(0x4266E114UL))
+#define bFM3_GPIO_PZR2_P6                      *((volatile unsigned int*)(0x4266E118UL))
+#define bFM3_GPIO_PZR2_P7                      *((volatile unsigned int*)(0x4266E11CUL))
+#define bFM3_GPIO_PZR2_P8                      *((volatile unsigned int*)(0x4266E120UL))
+#define bFM3_GPIO_PZR2_P9                      *((volatile unsigned int*)(0x4266E124UL))
+#define bFM3_GPIO_PZR3_P0                      *((volatile unsigned int*)(0x4266E180UL))
+#define bFM3_GPIO_PZR3_P1                      *((volatile unsigned int*)(0x4266E184UL))
+#define bFM3_GPIO_PZR3_P2                      *((volatile unsigned int*)(0x4266E188UL))
+#define bFM3_GPIO_PZR3_P3                      *((volatile unsigned int*)(0x4266E18CUL))
+#define bFM3_GPIO_PZR3_P4                      *((volatile unsigned int*)(0x4266E190UL))
+#define bFM3_GPIO_PZR3_P5                      *((volatile unsigned int*)(0x4266E194UL))
+#define bFM3_GPIO_PZR3_P6                      *((volatile unsigned int*)(0x4266E198UL))
+#define bFM3_GPIO_PZR3_P7                      *((volatile unsigned int*)(0x4266E19CUL))
+#define bFM3_GPIO_PZR3_P8                      *((volatile unsigned int*)(0x4266E1A0UL))
+#define bFM3_GPIO_PZR3_P9                      *((volatile unsigned int*)(0x4266E1A4UL))
+#define bFM3_GPIO_PZR3_PA                      *((volatile unsigned int*)(0x4266E1A8UL))
+#define bFM3_GPIO_PZR3_PB                      *((volatile unsigned int*)(0x4266E1ACUL))
+#define bFM3_GPIO_PZR3_PC                      *((volatile unsigned int*)(0x4266E1B0UL))
+#define bFM3_GPIO_PZR3_PD                      *((volatile unsigned int*)(0x4266E1B4UL))
+#define bFM3_GPIO_PZR3_PE                      *((volatile unsigned int*)(0x4266E1B8UL))
+#define bFM3_GPIO_PZR3_PF                      *((volatile unsigned int*)(0x4266E1BCUL))
+#define bFM3_GPIO_PZR4_P0                      *((volatile unsigned int*)(0x4266E200UL))
+#define bFM3_GPIO_PZR4_P1                      *((volatile unsigned int*)(0x4266E204UL))
+#define bFM3_GPIO_PZR4_P2                      *((volatile unsigned int*)(0x4266E208UL))
+#define bFM3_GPIO_PZR4_P3                      *((volatile unsigned int*)(0x4266E20CUL))
+#define bFM3_GPIO_PZR4_P4                      *((volatile unsigned int*)(0x4266E210UL))
+#define bFM3_GPIO_PZR4_P5                      *((volatile unsigned int*)(0x4266E214UL))
+#define bFM3_GPIO_PZR4_P6                      *((volatile unsigned int*)(0x4266E218UL))
+#define bFM3_GPIO_PZR4_P7                      *((volatile unsigned int*)(0x4266E21CUL))
+#define bFM3_GPIO_PZR4_P8                      *((volatile unsigned int*)(0x4266E220UL))
+#define bFM3_GPIO_PZR4_P9                      *((volatile unsigned int*)(0x4266E224UL))
+#define bFM3_GPIO_PZR4_PA                      *((volatile unsigned int*)(0x4266E228UL))
+#define bFM3_GPIO_PZR4_PB                      *((volatile unsigned int*)(0x4266E22CUL))
+#define bFM3_GPIO_PZR4_PC                      *((volatile unsigned int*)(0x4266E230UL))
+#define bFM3_GPIO_PZR4_PD                      *((volatile unsigned int*)(0x4266E234UL))
+#define bFM3_GPIO_PZR4_PE                      *((volatile unsigned int*)(0x4266E238UL))
+#define bFM3_GPIO_PZR5_P0                      *((volatile unsigned int*)(0x4266E280UL))
+#define bFM3_GPIO_PZR5_P1                      *((volatile unsigned int*)(0x4266E284UL))
+#define bFM3_GPIO_PZR5_P2                      *((volatile unsigned int*)(0x4266E288UL))
+#define bFM3_GPIO_PZR5_P3                      *((volatile unsigned int*)(0x4266E28CUL))
+#define bFM3_GPIO_PZR5_P4                      *((volatile unsigned int*)(0x4266E290UL))
+#define bFM3_GPIO_PZR5_P5                      *((volatile unsigned int*)(0x4266E294UL))
+#define bFM3_GPIO_PZR5_P6                      *((volatile unsigned int*)(0x4266E298UL))
+#define bFM3_GPIO_PZR5_P7                      *((volatile unsigned int*)(0x4266E29CUL))
+#define bFM3_GPIO_PZR5_P8                      *((volatile unsigned int*)(0x4266E2A0UL))
+#define bFM3_GPIO_PZR5_P9                      *((volatile unsigned int*)(0x4266E2A4UL))
+#define bFM3_GPIO_PZR5_PA                      *((volatile unsigned int*)(0x4266E2A8UL))
+#define bFM3_GPIO_PZR5_PB                      *((volatile unsigned int*)(0x4266E2ACUL))
+#define bFM3_GPIO_PZR5_PC                      *((volatile unsigned int*)(0x4266E2B0UL))
+#define bFM3_GPIO_PZR5_PD                      *((volatile unsigned int*)(0x4266E2B4UL))
+#define bFM3_GPIO_PZR6_P0                      *((volatile unsigned int*)(0x4266E300UL))
+#define bFM3_GPIO_PZR6_P1                      *((volatile unsigned int*)(0x4266E304UL))
+#define bFM3_GPIO_PZR6_P2                      *((volatile unsigned int*)(0x4266E308UL))
+#define bFM3_GPIO_PZR7_P0                      *((volatile unsigned int*)(0x4266E380UL))
+#define bFM3_GPIO_PZR7_P1                      *((volatile unsigned int*)(0x4266E384UL))
+#define bFM3_GPIO_PZR7_P2                      *((volatile unsigned int*)(0x4266E388UL))
+#define bFM3_GPIO_PZR7_P3                      *((volatile unsigned int*)(0x4266E38CUL))
+#define bFM3_GPIO_PZR7_P4                      *((volatile unsigned int*)(0x4266E390UL))
+#define bFM3_GPIO_PZR7_P5                      *((volatile unsigned int*)(0x4266E394UL))
+#define bFM3_GPIO_PZR7_P6                      *((volatile unsigned int*)(0x4266E398UL))
+#define bFM3_GPIO_PZR7_P7                      *((volatile unsigned int*)(0x4266E39CUL))
+#define bFM3_GPIO_PZR7_P8                      *((volatile unsigned int*)(0x4266E3A0UL))
+#define bFM3_GPIO_PZR7_P9                      *((volatile unsigned int*)(0x4266E3A4UL))
+#define bFM3_GPIO_PZR7_PA                      *((volatile unsigned int*)(0x4266E3A8UL))
+#define bFM3_GPIO_PZR7_PB                      *((volatile unsigned int*)(0x4266E3ACUL))
+#define bFM3_GPIO_PZR7_PC                      *((volatile unsigned int*)(0x4266E3B0UL))
+#define bFM3_GPIO_PZR7_PD                      *((volatile unsigned int*)(0x4266E3B4UL))
+#define bFM3_GPIO_PZR7_PE                      *((volatile unsigned int*)(0x4266E3B8UL))
+#define bFM3_GPIO_PZR7_PF                      *((volatile unsigned int*)(0x4266E3BCUL))
+#define bFM3_GPIO_PZR8_P0                      *((volatile unsigned int*)(0x4266E400UL))
+#define bFM3_GPIO_PZR8_P1                      *((volatile unsigned int*)(0x4266E404UL))
+#define bFM3_GPIO_PZR8_P2                      *((volatile unsigned int*)(0x4266E408UL))
+#define bFM3_GPIO_PZR8_P3                      *((volatile unsigned int*)(0x4266E40CUL))
+#define bFM3_GPIO_PZR9_P0                      *((volatile unsigned int*)(0x4266E480UL))
+#define bFM3_GPIO_PZR9_P1                      *((volatile unsigned int*)(0x4266E484UL))
+#define bFM3_GPIO_PZR9_P2                      *((volatile unsigned int*)(0x4266E488UL))
+#define bFM3_GPIO_PZR9_P3                      *((volatile unsigned int*)(0x4266E48CUL))
+#define bFM3_GPIO_PZR9_P4                      *((volatile unsigned int*)(0x4266E490UL))
+#define bFM3_GPIO_PZR9_P5                      *((volatile unsigned int*)(0x4266E494UL))
+#define bFM3_GPIO_PZRA_P0                      *((volatile unsigned int*)(0x4266E500UL))
+#define bFM3_GPIO_PZRA_P1                      *((volatile unsigned int*)(0x4266E504UL))
+#define bFM3_GPIO_PZRA_P2                      *((volatile unsigned int*)(0x4266E508UL))
+#define bFM3_GPIO_PZRA_P3                      *((volatile unsigned int*)(0x4266E50CUL))
+#define bFM3_GPIO_PZRA_P4                      *((volatile unsigned int*)(0x4266E510UL))
+#define bFM3_GPIO_PZRA_P5                      *((volatile unsigned int*)(0x4266E514UL))
+#define bFM3_GPIO_PZRB_P0                      *((volatile unsigned int*)(0x4266E580UL))
+#define bFM3_GPIO_PZRB_P1                      *((volatile unsigned int*)(0x4266E584UL))
+#define bFM3_GPIO_PZRB_P2                      *((volatile unsigned int*)(0x4266E588UL))
+#define bFM3_GPIO_PZRB_P3                      *((volatile unsigned int*)(0x4266E58CUL))
+#define bFM3_GPIO_PZRB_P4                      *((volatile unsigned int*)(0x4266E590UL))
+#define bFM3_GPIO_PZRB_P5                      *((volatile unsigned int*)(0x4266E594UL))
+#define bFM3_GPIO_PZRB_P6                      *((volatile unsigned int*)(0x4266E598UL))
+#define bFM3_GPIO_PZRB_P7                      *((volatile unsigned int*)(0x4266E59CUL))
+#define bFM3_GPIO_PZRC_P0                      *((volatile unsigned int*)(0x4266E600UL))
+#define bFM3_GPIO_PZRC_P1                      *((volatile unsigned int*)(0x4266E604UL))
+#define bFM3_GPIO_PZRC_P2                      *((volatile unsigned int*)(0x4266E608UL))
+#define bFM3_GPIO_PZRC_P3                      *((volatile unsigned int*)(0x4266E60CUL))
+#define bFM3_GPIO_PZRC_P4                      *((volatile unsigned int*)(0x4266E610UL))
+#define bFM3_GPIO_PZRC_P5                      *((volatile unsigned int*)(0x4266E614UL))
+#define bFM3_GPIO_PZRC_P6                      *((volatile unsigned int*)(0x4266E618UL))
+#define bFM3_GPIO_PZRC_P7                      *((volatile unsigned int*)(0x4266E61CUL))
+#define bFM3_GPIO_PZRC_P8                      *((volatile unsigned int*)(0x4266E620UL))
+#define bFM3_GPIO_PZRC_P9                      *((volatile unsigned int*)(0x4266E624UL))
+#define bFM3_GPIO_PZRC_PA                      *((volatile unsigned int*)(0x4266E628UL))
+#define bFM3_GPIO_PZRC_PB                      *((volatile unsigned int*)(0x4266E62CUL))
+#define bFM3_GPIO_PZRC_PC                      *((volatile unsigned int*)(0x4266E630UL))
+#define bFM3_GPIO_PZRC_PD                      *((volatile unsigned int*)(0x4266E634UL))
+#define bFM3_GPIO_PZRC_PE                      *((volatile unsigned int*)(0x4266E638UL))
+#define bFM3_GPIO_PZRC_PF                      *((volatile unsigned int*)(0x4266E63CUL))
+#define bFM3_GPIO_PZRD_P0                      *((volatile unsigned int*)(0x4266E680UL))
+#define bFM3_GPIO_PZRD_P1                      *((volatile unsigned int*)(0x4266E684UL))
+#define bFM3_GPIO_PZRD_P2                      *((volatile unsigned int*)(0x4266E688UL))
+#define bFM3_GPIO_PZRD_P3                      *((volatile unsigned int*)(0x4266E68CUL))
+#define bFM3_GPIO_PZRE_P0                      *((volatile unsigned int*)(0x4266E700UL))
+#define bFM3_GPIO_PZRE_P2                      *((volatile unsigned int*)(0x4266E708UL))
+#define bFM3_GPIO_PZRE_P3                      *((volatile unsigned int*)(0x4266E70CUL))
+#define bFM3_GPIO_PZRF_P0                      *((volatile unsigned int*)(0x4266E780UL))
+#define bFM3_GPIO_PZRF_P1                      *((volatile unsigned int*)(0x4266E784UL))
+#define bFM3_GPIO_PZRF_P2                      *((volatile unsigned int*)(0x4266E788UL))
+#define bFM3_GPIO_PZRF_P3                      *((volatile unsigned int*)(0x4266E78CUL))
+#define bFM3_GPIO_PZRF_P4                      *((volatile unsigned int*)(0x4266E790UL))
+#define bFM3_GPIO_PZRF_P5                      *((volatile unsigned int*)(0x4266E794UL))
+#define bFM3_GPIO_PZRF_P6                      *((volatile unsigned int*)(0x4266E798UL))
+
+/* Low voltage detection registers */
+#define bFM3_LVD_LVD_CTL_SVHI0                 *((volatile unsigned int*)(0x426A0008UL))
+#define bFM3_LVD_LVD_CTL_SVHI1                 *((volatile unsigned int*)(0x426A000CUL))
+#define bFM3_LVD_LVD_CTL_SVHI2                 *((volatile unsigned int*)(0x426A0010UL))
+#define bFM3_LVD_LVD_CTL_SVHI3                 *((volatile unsigned int*)(0x426A0014UL))
+#define bFM3_LVD_LVD_CTL_LVDIE                 *((volatile unsigned int*)(0x426A001CUL))
+#define bFM3_LVD_LVD_STR_LVDIR                 *((volatile unsigned int*)(0x426A009CUL))
+#define bFM3_LVD_LVD_CLR_LVDCL                 *((volatile unsigned int*)(0x426A011CUL))
+#define bFM3_LVD_LVD_STR2_LVDIRDY              *((volatile unsigned int*)(0x426A021CUL))
+
+/* USB clock registers */
+#define bFM3_USBETHERNETCLK_UCCR_UCEN0         *((volatile unsigned int*)(0x426C0000UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL0        *((volatile unsigned int*)(0x426C0004UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL1        *((volatile unsigned int*)(0x426C0008UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCEN1         *((volatile unsigned int*)(0x426C000CUL))
+#define bFM3_USBETHERNETCLK_UCCR_ECEN          *((volatile unsigned int*)(0x426C0010UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL0        *((volatile unsigned int*)(0x426C0014UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL1        *((volatile unsigned int*)(0x426C0018UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN       *((volatile unsigned int*)(0x426C0080UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPINC        *((volatile unsigned int*)(0x426C0084UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0       *((volatile unsigned int*)(0x426C0100UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1       *((volatile unsigned int*)(0x426C0104UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2       *((volatile unsigned int*)(0x426C0108UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0       *((volatile unsigned int*)(0x426C0180UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1       *((volatile unsigned int*)(0x426C0184UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2       *((volatile unsigned int*)(0x426C0188UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3       *((volatile unsigned int*)(0x426C018CUL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4       *((volatile unsigned int*)(0x426C0190UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0       *((volatile unsigned int*)(0x426C0200UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1       *((volatile unsigned int*)(0x426C0204UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2       *((volatile unsigned int*)(0x426C0208UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3       *((volatile unsigned int*)(0x426C020CUL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4       *((volatile unsigned int*)(0x426C0210UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5       *((volatile unsigned int*)(0x426C0214UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6       *((volatile unsigned int*)(0x426C0218UL))
+#define bFM3_USBETHERNETCLK_UP_STR_UPRDY       *((volatile unsigned int*)(0x426C0280UL))
+#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE    *((volatile unsigned int*)(0x426C0300UL))
+#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC    *((volatile unsigned int*)(0x426C0380UL))
+#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI    *((volatile unsigned int*)(0x426C0400UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0       *((volatile unsigned int*)(0x426C0480UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1       *((volatile unsigned int*)(0x426C0484UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2       *((volatile unsigned int*)(0x426C0488UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3       *((volatile unsigned int*)(0x426C048CUL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR0        *((volatile unsigned int*)(0x426C0500UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR1        *((volatile unsigned int*)(0x426C0504UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR2        *((volatile unsigned int*)(0x426C0508UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR3        *((volatile unsigned int*)(0x426C050CUL))
+#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN       *((volatile unsigned int*)(0x426C0580UL))
+#define bFM3_USBETHERNETCLK_USBEN0_USBEN0      *((volatile unsigned int*)(0x426C0600UL))
+#define bFM3_USBETHERNETCLK_USBEN1_USBEN1      *((volatile unsigned int*)(0x426C0680UL))
+
+/* UART asynchronous channel 0 registers */
+#define bFM3_MFS0_UART_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_UART_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_UART_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_UART_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_UART_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_UART_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_UART_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_UART_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_UART_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_UART_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_UART_ESCR_P                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_UART_ESCR_PEN                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_UART_ESCR_INV                *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_UART_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_UART_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_UART_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_UART_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_UART_SSR_FRE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_UART_SSR_PE                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_UART_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_UART_RDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_TDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_BGR_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_UART_BGR1_EXT                *((volatile unsigned int*)(0x427001BCUL))
+
+/* UART synchronous channel 0 registers */
+#define bFM3_MFS0_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42700004UL))
+#define bFM3_MFS0_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+
+/* UART LIN channel 0 registers */
+#define bFM3_MFS0_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_LIN_SCR_MS                   *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_LIN_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+
+/* I2C channel 0 registers */
+#define bFM3_MFS0_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427000B8UL))
+#define bFM3_MFS0_I2C_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42700200UL))
+#define bFM3_MFS0_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42700204UL))
+#define bFM3_MFS0_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42700208UL))
+#define bFM3_MFS0_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270020CUL))
+#define bFM3_MFS0_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42700210UL))
+#define bFM3_MFS0_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42700214UL))
+#define bFM3_MFS0_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42700218UL))
+#define bFM3_MFS0_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270021CUL))
+#define bFM3_MFS0_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42700220UL))
+#define bFM3_MFS0_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42700224UL))
+#define bFM3_MFS0_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42700228UL))
+#define bFM3_MFS0_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270022CUL))
+#define bFM3_MFS0_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42700230UL))
+#define bFM3_MFS0_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42700234UL))
+#define bFM3_MFS0_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42700238UL))
+#define bFM3_MFS0_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270023CUL))
+
+/* UART asynchronous channel 1 registers */
+#define bFM3_MFS1_UART_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_UART_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_UART_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_UART_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_UART_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_UART_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_UART_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_UART_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_UART_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_UART_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_UART_ESCR_P                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_UART_ESCR_PEN                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_UART_ESCR_INV                *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_UART_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_UART_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_UART_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_UART_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_UART_SSR_FRE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_UART_SSR_PE                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_UART_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_UART_RDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_TDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_BGR_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_UART_BGR1_EXT                *((volatile unsigned int*)(0x427021BCUL))
+
+/* UART synchronous channel 1 registers */
+#define bFM3_MFS1_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42702004UL))
+#define bFM3_MFS1_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+
+/* UART LIN channel 1 registers */
+#define bFM3_MFS1_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_LIN_SCR_MS                   *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_LIN_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+
+/* I2C channel 1 registers */
+#define bFM3_MFS1_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427020B8UL))
+#define bFM3_MFS1_I2C_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42702200UL))
+#define bFM3_MFS1_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42702204UL))
+#define bFM3_MFS1_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42702208UL))
+#define bFM3_MFS1_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270220CUL))
+#define bFM3_MFS1_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42702210UL))
+#define bFM3_MFS1_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42702214UL))
+#define bFM3_MFS1_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42702218UL))
+#define bFM3_MFS1_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270221CUL))
+#define bFM3_MFS1_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42702220UL))
+#define bFM3_MFS1_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42702224UL))
+#define bFM3_MFS1_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42702228UL))
+#define bFM3_MFS1_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270222CUL))
+#define bFM3_MFS1_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42702230UL))
+#define bFM3_MFS1_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42702234UL))
+#define bFM3_MFS1_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42702238UL))
+#define bFM3_MFS1_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270223CUL))
+
+/* UART asynchronous channel 2 registers */
+#define bFM3_MFS2_UART_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_UART_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_UART_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_UART_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_UART_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_UART_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_UART_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_UART_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_UART_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_UART_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_UART_ESCR_P                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_UART_ESCR_PEN                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_UART_ESCR_INV                *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_UART_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_UART_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_UART_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_UART_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_UART_SSR_FRE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_UART_SSR_PE                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_UART_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_UART_RDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_TDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_BGR_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_UART_BGR1_EXT                *((volatile unsigned int*)(0x427041BCUL))
+
+/* UART synchronous channel 2 registers */
+#define bFM3_MFS2_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42704004UL))
+#define bFM3_MFS2_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+
+/* UART LIN channel 2 registers */
+#define bFM3_MFS2_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_LIN_SCR_MS                   *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_LIN_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+
+/* I2C channel 2 registers */
+#define bFM3_MFS2_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427040B8UL))
+#define bFM3_MFS2_I2C_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42704200UL))
+#define bFM3_MFS2_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42704204UL))
+#define bFM3_MFS2_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42704208UL))
+#define bFM3_MFS2_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270420CUL))
+#define bFM3_MFS2_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42704210UL))
+#define bFM3_MFS2_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42704214UL))
+#define bFM3_MFS2_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42704218UL))
+#define bFM3_MFS2_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270421CUL))
+#define bFM3_MFS2_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42704220UL))
+#define bFM3_MFS2_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42704224UL))
+#define bFM3_MFS2_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42704228UL))
+#define bFM3_MFS2_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270422CUL))
+#define bFM3_MFS2_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42704230UL))
+#define bFM3_MFS2_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42704234UL))
+#define bFM3_MFS2_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42704238UL))
+#define bFM3_MFS2_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270423CUL))
+
+/* UART asynchronous channel 3 registers */
+#define bFM3_MFS3_UART_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_UART_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_UART_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_UART_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_UART_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_UART_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_UART_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_UART_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_UART_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_UART_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_UART_ESCR_P                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_UART_ESCR_PEN                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_UART_ESCR_INV                *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_UART_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_UART_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_UART_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_UART_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_UART_SSR_FRE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_UART_SSR_PE                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_UART_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_UART_RDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_TDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_BGR_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_UART_BGR1_EXT                *((volatile unsigned int*)(0x427061BCUL))
+
+/* UART synchronous channel 3 registers */
+#define bFM3_MFS3_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42706004UL))
+#define bFM3_MFS3_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+
+/* UART LIN channel 3 registers */
+#define bFM3_MFS3_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_LIN_SCR_MS                   *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_LIN_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+
+/* I2C channel 3 registers */
+#define bFM3_MFS3_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427060B8UL))
+#define bFM3_MFS3_I2C_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42706200UL))
+#define bFM3_MFS3_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42706204UL))
+#define bFM3_MFS3_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42706208UL))
+#define bFM3_MFS3_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270620CUL))
+#define bFM3_MFS3_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42706210UL))
+#define bFM3_MFS3_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42706214UL))
+#define bFM3_MFS3_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42706218UL))
+#define bFM3_MFS3_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270621CUL))
+#define bFM3_MFS3_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42706220UL))
+#define bFM3_MFS3_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42706224UL))
+#define bFM3_MFS3_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42706228UL))
+#define bFM3_MFS3_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270622CUL))
+#define bFM3_MFS3_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42706230UL))
+#define bFM3_MFS3_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42706234UL))
+#define bFM3_MFS3_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42706238UL))
+#define bFM3_MFS3_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270623CUL))
+
+/* UART asynchronous channel 4 registers */
+#define bFM3_MFS4_UART_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_UART_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_UART_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_UART_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_UART_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_UART_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_UART_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_UART_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_UART_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_UART_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_UART_ESCR_P                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_UART_ESCR_PEN                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_UART_ESCR_INV                *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_UART_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_UART_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_UART_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_UART_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_UART_SSR_FRE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_UART_SSR_PE                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_UART_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_UART_RDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_TDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_BGR_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_BGR1_EXT                *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART synchronous channel 4 registers */
+#define bFM3_MFS4_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42708004UL))
+#define bFM3_MFS4_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART LIN channel 4 registers */
+#define bFM3_MFS4_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_LIN_SCR_MS                   *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_LIN_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* I2C channel 4 registers */
+#define bFM3_MFS4_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427080B8UL))
+#define bFM3_MFS4_I2C_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42708200UL))
+#define bFM3_MFS4_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42708204UL))
+#define bFM3_MFS4_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42708208UL))
+#define bFM3_MFS4_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270820CUL))
+#define bFM3_MFS4_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42708210UL))
+#define bFM3_MFS4_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42708214UL))
+#define bFM3_MFS4_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42708218UL))
+#define bFM3_MFS4_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270821CUL))
+#define bFM3_MFS4_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42708220UL))
+#define bFM3_MFS4_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42708224UL))
+#define bFM3_MFS4_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42708228UL))
+#define bFM3_MFS4_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270822CUL))
+#define bFM3_MFS4_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42708230UL))
+#define bFM3_MFS4_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42708234UL))
+#define bFM3_MFS4_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42708238UL))
+#define bFM3_MFS4_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270823CUL))
+#define bFM3_MFS4_I2C_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART asynchronous channel 5 registers */
+#define bFM3_MFS5_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_UART_ESCR_P                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_UART_ESCR_INV                *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_UART_SSR_PE                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_UART_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_UART_RDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_TDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART synchronous channel 5 registers */
+#define bFM3_MFS5_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270A004UL))
+#define bFM3_MFS5_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART LIN channel 5 registers */
+#define bFM3_MFS5_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* I2C channel 5 registers */
+#define bFM3_MFS5_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270A0B8UL))
+#define bFM3_MFS5_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270A200UL))
+#define bFM3_MFS5_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270A204UL))
+#define bFM3_MFS5_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270A208UL))
+#define bFM3_MFS5_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270A20CUL))
+#define bFM3_MFS5_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270A210UL))
+#define bFM3_MFS5_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270A214UL))
+#define bFM3_MFS5_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270A218UL))
+#define bFM3_MFS5_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270A21CUL))
+#define bFM3_MFS5_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270A220UL))
+#define bFM3_MFS5_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270A224UL))
+#define bFM3_MFS5_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270A228UL))
+#define bFM3_MFS5_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270A22CUL))
+#define bFM3_MFS5_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270A230UL))
+#define bFM3_MFS5_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270A234UL))
+#define bFM3_MFS5_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270A238UL))
+#define bFM3_MFS5_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270A23CUL))
+#define bFM3_MFS5_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART asynchronous channel 6 registers */
+#define bFM3_MFS6_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_UART_ESCR_P                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_UART_ESCR_INV                *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_UART_SSR_PE                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_UART_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_UART_RDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_TDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART synchronous channel 6 registers */
+#define bFM3_MFS6_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270C004UL))
+#define bFM3_MFS6_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART LIN channel 6 registers */
+#define bFM3_MFS6_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* I2C channel 6 registers */
+#define bFM3_MFS6_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270C0B8UL))
+#define bFM3_MFS6_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270C200UL))
+#define bFM3_MFS6_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270C204UL))
+#define bFM3_MFS6_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270C208UL))
+#define bFM3_MFS6_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270C20CUL))
+#define bFM3_MFS6_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270C210UL))
+#define bFM3_MFS6_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270C214UL))
+#define bFM3_MFS6_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270C218UL))
+#define bFM3_MFS6_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270C21CUL))
+#define bFM3_MFS6_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270C220UL))
+#define bFM3_MFS6_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270C224UL))
+#define bFM3_MFS6_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270C228UL))
+#define bFM3_MFS6_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270C22CUL))
+#define bFM3_MFS6_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270C230UL))
+#define bFM3_MFS6_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270C234UL))
+#define bFM3_MFS6_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270C238UL))
+#define bFM3_MFS6_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270C23CUL))
+#define bFM3_MFS6_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART asynchronous channel 7 registers */
+#define bFM3_MFS7_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_UART_ESCR_P                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_UART_ESCR_INV                *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_UART_SSR_PE                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_UART_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_UART_RDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_TDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART synchronous channel 7 registers */
+#define bFM3_MFS7_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270E004UL))
+#define bFM3_MFS7_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART LIN channel 7 registers */
+#define bFM3_MFS7_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* I2C channel 7 registers */
+#define bFM3_MFS7_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270E0B8UL))
+#define bFM3_MFS7_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270E200UL))
+#define bFM3_MFS7_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270E204UL))
+#define bFM3_MFS7_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270E208UL))
+#define bFM3_MFS7_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270E20CUL))
+#define bFM3_MFS7_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270E210UL))
+#define bFM3_MFS7_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270E214UL))
+#define bFM3_MFS7_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270E218UL))
+#define bFM3_MFS7_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270E21CUL))
+#define bFM3_MFS7_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270E220UL))
+#define bFM3_MFS7_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270E224UL))
+#define bFM3_MFS7_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270E228UL))
+#define bFM3_MFS7_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270E22CUL))
+#define bFM3_MFS7_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270E230UL))
+#define bFM3_MFS7_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270E234UL))
+#define bFM3_MFS7_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270E238UL))
+#define bFM3_MFS7_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270E23CUL))
+#define bFM3_MFS7_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* MFS Noise Filter Control registers */
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF00           *((volatile unsigned int*)(0x42710000UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF01           *((volatile unsigned int*)(0x42710004UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF10           *((volatile unsigned int*)(0x42710008UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF11           *((volatile unsigned int*)(0x4271000CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF20           *((volatile unsigned int*)(0x42710010UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF21           *((volatile unsigned int*)(0x42710014UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF30           *((volatile unsigned int*)(0x42710018UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF31           *((volatile unsigned int*)(0x4271001CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF40           *((volatile unsigned int*)(0x42710020UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF41           *((volatile unsigned int*)(0x42710024UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF50           *((volatile unsigned int*)(0x42710028UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF51           *((volatile unsigned int*)(0x4271002CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF60           *((volatile unsigned int*)(0x42710030UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF61           *((volatile unsigned int*)(0x42710034UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF70           *((volatile unsigned int*)(0x42710038UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF71           *((volatile unsigned int*)(0x4271003CUL))
+
+/* CRC registers */
+#define bFM3_CRC_CRCCR_INIT                    *((volatile unsigned int*)(0x42720000UL))
+#define bFM3_CRC_CRCCR_CRC32                   *((volatile unsigned int*)(0x42720004UL))
+#define bFM3_CRC_CRCCR_LTLEND                  *((volatile unsigned int*)(0x42720008UL))
+#define bFM3_CRC_CRCCR_LSBFST                  *((volatile unsigned int*)(0x4272000CUL))
+#define bFM3_CRC_CRCCR_CRCLTE                  *((volatile unsigned int*)(0x42720010UL))
+#define bFM3_CRC_CRCCR_CRCLSF                  *((volatile unsigned int*)(0x42720014UL))
+#define bFM3_CRC_CRCCR_FXOR                    *((volatile unsigned int*)(0x42720018UL))
+
+/* Watch counter registers */
+#define bFM3_WC_WCRD_CTR0                      *((volatile unsigned int*)(0x42740000UL))
+#define bFM3_WC_WCRD_CTR1                      *((volatile unsigned int*)(0x42740004UL))
+#define bFM3_WC_WCRD_CTR2                      *((volatile unsigned int*)(0x42740008UL))
+#define bFM3_WC_WCRD_CTR3                      *((volatile unsigned int*)(0x4274000CUL))
+#define bFM3_WC_WCRD_CTR4                      *((volatile unsigned int*)(0x42740010UL))
+#define bFM3_WC_WCRD_CTR5                      *((volatile unsigned int*)(0x42740014UL))
+#define bFM3_WC_WCRL_RLC0                      *((volatile unsigned int*)(0x42740020UL))
+#define bFM3_WC_WCRL_RLC1                      *((volatile unsigned int*)(0x42740024UL))
+#define bFM3_WC_WCRL_RLC2                      *((volatile unsigned int*)(0x42740028UL))
+#define bFM3_WC_WCRL_RLC3                      *((volatile unsigned int*)(0x4274002CUL))
+#define bFM3_WC_WCRL_RLC4                      *((volatile unsigned int*)(0x42740030UL))
+#define bFM3_WC_WCRL_RLC5                      *((volatile unsigned int*)(0x42740034UL))
+#define bFM3_WC_WCCR_WCIF                      *((volatile unsigned int*)(0x42740040UL))
+#define bFM3_WC_WCCR_WCIE                      *((volatile unsigned int*)(0x42740044UL))
+#define bFM3_WC_WCCR_CS0                       *((volatile unsigned int*)(0x42740048UL))
+#define bFM3_WC_WCCR_CS1                       *((volatile unsigned int*)(0x4274004CUL))
+#define bFM3_WC_WCCR_WCOP                      *((volatile unsigned int*)(0x42740058UL))
+#define bFM3_WC_WCCR_WCEN                      *((volatile unsigned int*)(0x4274005CUL))
+#define bFM3_WC_CLK_SEL_SEL_IN                 *((volatile unsigned int*)(0x42740200UL))
+#define bFM3_WC_CLK_SEL_SEL_OUT                *((volatile unsigned int*)(0x42740220UL))
+#define bFM3_WC_CLK_EN_CLK_EN                  *((volatile unsigned int*)(0x42740280UL))
+#define bFM3_WC_CLK_EN_CLK_EN_R                *((volatile unsigned int*)(0x42740284UL))
+
+/* External bus interface registers */
+#define bFM3_EXBUS_MODE0_WDTH0                 *((volatile unsigned int*)(0x427E0000UL))
+#define bFM3_EXBUS_MODE0_WDTH1                 *((volatile unsigned int*)(0x427E0004UL))
+#define bFM3_EXBUS_MODE0_RBMON                 *((volatile unsigned int*)(0x427E0008UL))
+#define bFM3_EXBUS_MODE0_WEOFF                 *((volatile unsigned int*)(0x427E000CUL))
+#define bFM3_EXBUS_MODE0_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE0_PAGE                  *((volatile unsigned int*)(0x427E0014UL))
+#define bFM3_EXBUS_MODE0_RDY                   *((volatile unsigned int*)(0x427E0018UL))
+#define bFM3_EXBUS_MODE0_SHRTDOUT              *((volatile unsigned int*)(0x427E001CUL))
+#define bFM3_EXBUS_MODE0_MPXMODE               *((volatile unsigned int*)(0x427E0020UL))
+#define bFM3_EXBUS_MODE0_ALEINV                *((volatile unsigned int*)(0x427E0024UL))
+#define bFM3_EXBUS_MODE0_MPXDOFF               *((volatile unsigned int*)(0x427E002CUL))
+#define bFM3_EXBUS_MODE0_MPXCSOF               *((volatile unsigned int*)(0x427E0030UL))
+#define bFM3_EXBUS_MODE0_MOEXEUP               *((volatile unsigned int*)(0x427E0034UL))
+#define bFM3_EXBUS_MODE1_WDTH0                 *((volatile unsigned int*)(0x427E0080UL))
+#define bFM3_EXBUS_MODE1_WDTH1                 *((volatile unsigned int*)(0x427E0084UL))
+#define bFM3_EXBUS_MODE1_RBMON                 *((volatile unsigned int*)(0x427E0088UL))
+#define bFM3_EXBUS_MODE1_WEOFF                 *((volatile unsigned int*)(0x427E008CUL))
+#define bFM3_EXBUS_MODE1_NAND                  *((volatile unsigned int*)(0x427E0090UL))
+#define bFM3_EXBUS_MODE1_PAGE                  *((volatile unsigned int*)(0x427E0094UL))
+#define bFM3_EXBUS_MODE1_RDY                   *((volatile unsigned int*)(0x427E0098UL))
+#define bFM3_EXBUS_MODE1_SHRTDOUT              *((volatile unsigned int*)(0x427E009CUL))
+#define bFM3_EXBUS_MODE1_MPXMODE               *((volatile unsigned int*)(0x427E00A0UL))
+#define bFM3_EXBUS_MODE1_ALEINV                *((volatile unsigned int*)(0x427E00A4UL))
+#define bFM3_EXBUS_MODE1_MPXDOFF               *((volatile unsigned int*)(0x427E00ACUL))
+#define bFM3_EXBUS_MODE1_MPXCSOF               *((volatile unsigned int*)(0x427E00B0UL))
+#define bFM3_EXBUS_MODE1_MOEXEUP               *((volatile unsigned int*)(0x427E00B4UL))
+#define bFM3_EXBUS_MODE2_WDTH0                 *((volatile unsigned int*)(0x427E0100UL))
+#define bFM3_EXBUS_MODE2_WDTH1                 *((volatile unsigned int*)(0x427E0104UL))
+#define bFM3_EXBUS_MODE2_RBMON                 *((volatile unsigned int*)(0x427E0108UL))
+#define bFM3_EXBUS_MODE2_WEOFF                 *((volatile unsigned int*)(0x427E010CUL))
+#define bFM3_EXBUS_MODE2_NAND                  *((volatile unsigned int*)(0x427E0110UL))
+#define bFM3_EXBUS_MODE2_PAGE                  *((volatile unsigned int*)(0x427E0114UL))
+#define bFM3_EXBUS_MODE2_RDY                   *((volatile unsigned int*)(0x427E0118UL))
+#define bFM3_EXBUS_MODE2_SHRTDOUT              *((volatile unsigned int*)(0x427E011CUL))
+#define bFM3_EXBUS_MODE2_MPXMODE               *((volatile unsigned int*)(0x427E0120UL))
+#define bFM3_EXBUS_MODE2_ALEINV                *((volatile unsigned int*)(0x427E0124UL))
+#define bFM3_EXBUS_MODE2_MPXDOFF               *((volatile unsigned int*)(0x427E012CUL))
+#define bFM3_EXBUS_MODE2_MPXCSOF               *((volatile unsigned int*)(0x427E0130UL))
+#define bFM3_EXBUS_MODE2_MOEXEUP               *((volatile unsigned int*)(0x427E0134UL))
+#define bFM3_EXBUS_MODE3_WDTH0                 *((volatile unsigned int*)(0x427E0180UL))
+#define bFM3_EXBUS_MODE3_WDTH1                 *((volatile unsigned int*)(0x427E0184UL))
+#define bFM3_EXBUS_MODE3_RBMON                 *((volatile unsigned int*)(0x427E0188UL))
+#define bFM3_EXBUS_MODE3_WEOFF                 *((volatile unsigned int*)(0x427E018CUL))
+#define bFM3_EXBUS_MODE3_NAND                  *((volatile unsigned int*)(0x427E0190UL))
+#define bFM3_EXBUS_MODE3_PAGE                  *((volatile unsigned int*)(0x427E0194UL))
+#define bFM3_EXBUS_MODE3_RDY                   *((volatile unsigned int*)(0x427E0198UL))
+#define bFM3_EXBUS_MODE3_SHRTDOUT              *((volatile unsigned int*)(0x427E019CUL))
+#define bFM3_EXBUS_MODE3_MPXMODE               *((volatile unsigned int*)(0x427E01A0UL))
+#define bFM3_EXBUS_MODE3_ALEINV                *((volatile unsigned int*)(0x427E01A4UL))
+#define bFM3_EXBUS_MODE3_MPXDOFF               *((volatile unsigned int*)(0x427E01ACUL))
+#define bFM3_EXBUS_MODE3_MPXCSOF               *((volatile unsigned int*)(0x427E01B0UL))
+#define bFM3_EXBUS_MODE3_MOEXEUP               *((volatile unsigned int*)(0x427E01B4UL))
+#define bFM3_EXBUS_MODE4_WDTH0                 *((volatile unsigned int*)(0x427E0200UL))
+#define bFM3_EXBUS_MODE4_WDTH1                 *((volatile unsigned int*)(0x427E0204UL))
+#define bFM3_EXBUS_MODE4_RBMON                 *((volatile unsigned int*)(0x427E0208UL))
+#define bFM3_EXBUS_MODE4_WEOFF                 *((volatile unsigned int*)(0x427E020CUL))
+#define bFM3_EXBUS_MODE4_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE4_PAGE                  *((volatile unsigned int*)(0x427E0214UL))
+#define bFM3_EXBUS_MODE4_RDY                   *((volatile unsigned int*)(0x427E0218UL))
+#define bFM3_EXBUS_MODE4_SHRTDOUT              *((volatile unsigned int*)(0x427E021CUL))
+#define bFM3_EXBUS_MODE4_MPXMODE               *((volatile unsigned int*)(0x427E0220UL))
+#define bFM3_EXBUS_MODE4_ALEINV                *((volatile unsigned int*)(0x427E0224UL))
+#define bFM3_EXBUS_MODE4_MPXDOFF               *((volatile unsigned int*)(0x427E022CUL))
+#define bFM3_EXBUS_MODE4_MPXCSOF               *((volatile unsigned int*)(0x427E0230UL))
+#define bFM3_EXBUS_MODE4_MOEXEUP               *((volatile unsigned int*)(0x427E0234UL))
+#define bFM3_EXBUS_MODE5_WDTH0                 *((volatile unsigned int*)(0x427E0280UL))
+#define bFM3_EXBUS_MODE5_WDTH1                 *((volatile unsigned int*)(0x427E0284UL))
+#define bFM3_EXBUS_MODE5_RBMON                 *((volatile unsigned int*)(0x427E0288UL))
+#define bFM3_EXBUS_MODE5_WEOFF                 *((volatile unsigned int*)(0x427E028CUL))
+#define bFM3_EXBUS_MODE5_NAND                  *((volatile unsigned int*)(0x427E0290UL))
+#define bFM3_EXBUS_MODE5_PAGE                  *((volatile unsigned int*)(0x427E0294UL))
+#define bFM3_EXBUS_MODE5_RDY                   *((volatile unsigned int*)(0x427E0298UL))
+#define bFM3_EXBUS_MODE5_SHRTDOUT              *((volatile unsigned int*)(0x427E029CUL))
+#define bFM3_EXBUS_MODE5_MPXMODE               *((volatile unsigned int*)(0x427E02A0UL))
+#define bFM3_EXBUS_MODE5_ALEINV                *((volatile unsigned int*)(0x427E02A4UL))
+#define bFM3_EXBUS_MODE5_MPXDOFF               *((volatile unsigned int*)(0x427E02ACUL))
+#define bFM3_EXBUS_MODE5_MPXCSOF               *((volatile unsigned int*)(0x427E02B0UL))
+#define bFM3_EXBUS_MODE5_MOEXEUP               *((volatile unsigned int*)(0x427E02B4UL))
+#define bFM3_EXBUS_MODE6_WDTH0                 *((volatile unsigned int*)(0x427E0300UL))
+#define bFM3_EXBUS_MODE6_WDTH1                 *((volatile unsigned int*)(0x427E0304UL))
+#define bFM3_EXBUS_MODE6_RBMON                 *((volatile unsigned int*)(0x427E0308UL))
+#define bFM3_EXBUS_MODE6_WEOFF                 *((volatile unsigned int*)(0x427E030CUL))
+#define bFM3_EXBUS_MODE6_NAND                  *((volatile unsigned int*)(0x427E0310UL))
+#define bFM3_EXBUS_MODE6_PAGE                  *((volatile unsigned int*)(0x427E0314UL))
+#define bFM3_EXBUS_MODE6_RDY                   *((volatile unsigned int*)(0x427E0318UL))
+#define bFM3_EXBUS_MODE6_SHRTDOUT              *((volatile unsigned int*)(0x427E031CUL))
+#define bFM3_EXBUS_MODE6_MPXMODE               *((volatile unsigned int*)(0x427E0320UL))
+#define bFM3_EXBUS_MODE6_ALEINV                *((volatile unsigned int*)(0x427E0324UL))
+#define bFM3_EXBUS_MODE6_MPXDOFF               *((volatile unsigned int*)(0x427E032CUL))
+#define bFM3_EXBUS_MODE6_MPXCSOF               *((volatile unsigned int*)(0x427E0330UL))
+#define bFM3_EXBUS_MODE6_MOEXEUP               *((volatile unsigned int*)(0x427E0334UL))
+#define bFM3_EXBUS_MODE7_WDTH0                 *((volatile unsigned int*)(0x427E0380UL))
+#define bFM3_EXBUS_MODE7_WDTH1                 *((volatile unsigned int*)(0x427E0384UL))
+#define bFM3_EXBUS_MODE7_RBMON                 *((volatile unsigned int*)(0x427E0388UL))
+#define bFM3_EXBUS_MODE7_WEOFF                 *((volatile unsigned int*)(0x427E038CUL))
+#define bFM3_EXBUS_MODE7_NAND                  *((volatile unsigned int*)(0x427E0390UL))
+#define bFM3_EXBUS_MODE7_PAGE                  *((volatile unsigned int*)(0x427E0394UL))
+#define bFM3_EXBUS_MODE7_RDY                   *((volatile unsigned int*)(0x427E0398UL))
+#define bFM3_EXBUS_MODE7_SHRTDOUT              *((volatile unsigned int*)(0x427E039CUL))
+#define bFM3_EXBUS_MODE7_MPXMODE               *((volatile unsigned int*)(0x427E03A0UL))
+#define bFM3_EXBUS_MODE7_ALEINV                *((volatile unsigned int*)(0x427E03A4UL))
+#define bFM3_EXBUS_MODE7_MPXDOFF               *((volatile unsigned int*)(0x427E03ACUL))
+#define bFM3_EXBUS_MODE7_MPXCSOF               *((volatile unsigned int*)(0x427E03B0UL))
+#define bFM3_EXBUS_MODE7_MOEXEUP               *((volatile unsigned int*)(0x427E03B4UL))
+#define bFM3_EXBUS_TIM0_RACC0                  *((volatile unsigned int*)(0x427E0400UL))
+#define bFM3_EXBUS_TIM0_RACC1                  *((volatile unsigned int*)(0x427E0404UL))
+#define bFM3_EXBUS_TIM0_RACC2                  *((volatile unsigned int*)(0x427E0408UL))
+#define bFM3_EXBUS_TIM0_RACC3                  *((volatile unsigned int*)(0x427E040CUL))
+#define bFM3_EXBUS_TIM0_RADC0                  *((volatile unsigned int*)(0x427E0410UL))
+#define bFM3_EXBUS_TIM0_RADC1                  *((volatile unsigned int*)(0x427E0414UL))
+#define bFM3_EXBUS_TIM0_RADC2                  *((volatile unsigned int*)(0x427E0418UL))
+#define bFM3_EXBUS_TIM0_RADC3                  *((volatile unsigned int*)(0x427E041CUL))
+#define bFM3_EXBUS_TIM0_FRADC0                 *((volatile unsigned int*)(0x427E0420UL))
+#define bFM3_EXBUS_TIM0_FRADC1                 *((volatile unsigned int*)(0x427E0424UL))
+#define bFM3_EXBUS_TIM0_FRADC2                 *((volatile unsigned int*)(0x427E0428UL))
+#define bFM3_EXBUS_TIM0_FRADC3                 *((volatile unsigned int*)(0x427E042CUL))
+#define bFM3_EXBUS_TIM0_RIDLC0                 *((volatile unsigned int*)(0x427E0430UL))
+#define bFM3_EXBUS_TIM0_RIDLC1                 *((volatile unsigned int*)(0x427E0434UL))
+#define bFM3_EXBUS_TIM0_RIDLC2                 *((volatile unsigned int*)(0x427E0438UL))
+#define bFM3_EXBUS_TIM0_RIDLC3                 *((volatile unsigned int*)(0x427E043CUL))
+#define bFM3_EXBUS_TIM0_WACC0                  *((volatile unsigned int*)(0x427E0440UL))
+#define bFM3_EXBUS_TIM0_WACC1                  *((volatile unsigned int*)(0x427E0444UL))
+#define bFM3_EXBUS_TIM0_WACC2                  *((volatile unsigned int*)(0x427E0448UL))
+#define bFM3_EXBUS_TIM0_WACC3                  *((volatile unsigned int*)(0x427E044CUL))
+#define bFM3_EXBUS_TIM0_WADC0                  *((volatile unsigned int*)(0x427E0450UL))
+#define bFM3_EXBUS_TIM0_WADC1                  *((volatile unsigned int*)(0x427E0454UL))
+#define bFM3_EXBUS_TIM0_WADC2                  *((volatile unsigned int*)(0x427E0458UL))
+#define bFM3_EXBUS_TIM0_WADC3                  *((volatile unsigned int*)(0x427E045CUL))
+#define bFM3_EXBUS_TIM0_WWEC0                  *((volatile unsigned int*)(0x427E0460UL))
+#define bFM3_EXBUS_TIM0_WWEC1                  *((volatile unsigned int*)(0x427E0464UL))
+#define bFM3_EXBUS_TIM0_WWEC2                  *((volatile unsigned int*)(0x427E0468UL))
+#define bFM3_EXBUS_TIM0_WWEC3                  *((volatile unsigned int*)(0x427E046CUL))
+#define bFM3_EXBUS_TIM0_WIDLC0                 *((volatile unsigned int*)(0x427E0470UL))
+#define bFM3_EXBUS_TIM0_WIDLC1                 *((volatile unsigned int*)(0x427E0474UL))
+#define bFM3_EXBUS_TIM0_WIDLC2                 *((volatile unsigned int*)(0x427E0478UL))
+#define bFM3_EXBUS_TIM0_WIDLC3                 *((volatile unsigned int*)(0x427E047CUL))
+#define bFM3_EXBUS_TIM1_RACC0                  *((volatile unsigned int*)(0x427E0480UL))
+#define bFM3_EXBUS_TIM1_RACC1                  *((volatile unsigned int*)(0x427E0484UL))
+#define bFM3_EXBUS_TIM1_RACC2                  *((volatile unsigned int*)(0x427E0488UL))
+#define bFM3_EXBUS_TIM1_RACC3                  *((volatile unsigned int*)(0x427E048CUL))
+#define bFM3_EXBUS_TIM1_RADC0                  *((volatile unsigned int*)(0x427E0490UL))
+#define bFM3_EXBUS_TIM1_RADC1                  *((volatile unsigned int*)(0x427E0494UL))
+#define bFM3_EXBUS_TIM1_RADC2                  *((volatile unsigned int*)(0x427E0498UL))
+#define bFM3_EXBUS_TIM1_RADC3                  *((volatile unsigned int*)(0x427E049CUL))
+#define bFM3_EXBUS_TIM1_FRADC0                 *((volatile unsigned int*)(0x427E04A0UL))
+#define bFM3_EXBUS_TIM1_FRADC1                 *((volatile unsigned int*)(0x427E04A4UL))
+#define bFM3_EXBUS_TIM1_FRADC2                 *((volatile unsigned int*)(0x427E04A8UL))
+#define bFM3_EXBUS_TIM1_FRADC3                 *((volatile unsigned int*)(0x427E04ACUL))
+#define bFM3_EXBUS_TIM1_RIDLC0                 *((volatile unsigned int*)(0x427E04B0UL))
+#define bFM3_EXBUS_TIM1_RIDLC1                 *((volatile unsigned int*)(0x427E04B4UL))
+#define bFM3_EXBUS_TIM1_RIDLC2                 *((volatile unsigned int*)(0x427E04B8UL))
+#define bFM3_EXBUS_TIM1_RIDLC3                 *((volatile unsigned int*)(0x427E04BCUL))
+#define bFM3_EXBUS_TIM1_WACC0                  *((volatile unsigned int*)(0x427E04C0UL))
+#define bFM3_EXBUS_TIM1_WACC1                  *((volatile unsigned int*)(0x427E04C4UL))
+#define bFM3_EXBUS_TIM1_WACC2                  *((volatile unsigned int*)(0x427E04C8UL))
+#define bFM3_EXBUS_TIM1_WACC3                  *((volatile unsigned int*)(0x427E04CCUL))
+#define bFM3_EXBUS_TIM1_WADC0                  *((volatile unsigned int*)(0x427E04D0UL))
+#define bFM3_EXBUS_TIM1_WADC1                  *((volatile unsigned int*)(0x427E04D4UL))
+#define bFM3_EXBUS_TIM1_WADC2                  *((volatile unsigned int*)(0x427E04D8UL))
+#define bFM3_EXBUS_TIM1_WADC3                  *((volatile unsigned int*)(0x427E04DCUL))
+#define bFM3_EXBUS_TIM1_WWEC0                  *((volatile unsigned int*)(0x427E04E0UL))
+#define bFM3_EXBUS_TIM1_WWEC1                  *((volatile unsigned int*)(0x427E04E4UL))
+#define bFM3_EXBUS_TIM1_WWEC2                  *((volatile unsigned int*)(0x427E04E8UL))
+#define bFM3_EXBUS_TIM1_WWEC3                  *((volatile unsigned int*)(0x427E04ECUL))
+#define bFM3_EXBUS_TIM1_WIDLC0                 *((volatile unsigned int*)(0x427E04F0UL))
+#define bFM3_EXBUS_TIM1_WIDLC1                 *((volatile unsigned int*)(0x427E04F4UL))
+#define bFM3_EXBUS_TIM1_WIDLC2                 *((volatile unsigned int*)(0x427E04F8UL))
+#define bFM3_EXBUS_TIM1_WIDLC3                 *((volatile unsigned int*)(0x427E04FCUL))
+#define bFM3_EXBUS_TIM2_RACC0                  *((volatile unsigned int*)(0x427E0500UL))
+#define bFM3_EXBUS_TIM2_RACC1                  *((volatile unsigned int*)(0x427E0504UL))
+#define bFM3_EXBUS_TIM2_RACC2                  *((volatile unsigned int*)(0x427E0508UL))
+#define bFM3_EXBUS_TIM2_RACC3                  *((volatile unsigned int*)(0x427E050CUL))
+#define bFM3_EXBUS_TIM2_RADC0                  *((volatile unsigned int*)(0x427E0510UL))
+#define bFM3_EXBUS_TIM2_RADC1                  *((volatile unsigned int*)(0x427E0514UL))
+#define bFM3_EXBUS_TIM2_RADC2                  *((volatile unsigned int*)(0x427E0518UL))
+#define bFM3_EXBUS_TIM2_RADC3                  *((volatile unsigned int*)(0x427E051CUL))
+#define bFM3_EXBUS_TIM2_FRADC0                 *((volatile unsigned int*)(0x427E0520UL))
+#define bFM3_EXBUS_TIM2_FRADC1                 *((volatile unsigned int*)(0x427E0524UL))
+#define bFM3_EXBUS_TIM2_FRADC2                 *((volatile unsigned int*)(0x427E0528UL))
+#define bFM3_EXBUS_TIM2_FRADC3                 *((volatile unsigned int*)(0x427E052CUL))
+#define bFM3_EXBUS_TIM2_RIDLC0                 *((volatile unsigned int*)(0x427E0530UL))
+#define bFM3_EXBUS_TIM2_RIDLC1                 *((volatile unsigned int*)(0x427E0534UL))
+#define bFM3_EXBUS_TIM2_RIDLC2                 *((volatile unsigned int*)(0x427E0538UL))
+#define bFM3_EXBUS_TIM2_RIDLC3                 *((volatile unsigned int*)(0x427E053CUL))
+#define bFM3_EXBUS_TIM2_WACC0                  *((volatile unsigned int*)(0x427E0540UL))
+#define bFM3_EXBUS_TIM2_WACC1                  *((volatile unsigned int*)(0x427E0544UL))
+#define bFM3_EXBUS_TIM2_WACC2                  *((volatile unsigned int*)(0x427E0548UL))
+#define bFM3_EXBUS_TIM2_WACC3                  *((volatile unsigned int*)(0x427E054CUL))
+#define bFM3_EXBUS_TIM2_WADC0                  *((volatile unsigned int*)(0x427E0550UL))
+#define bFM3_EXBUS_TIM2_WADC1                  *((volatile unsigned int*)(0x427E0554UL))
+#define bFM3_EXBUS_TIM2_WADC2                  *((volatile unsigned int*)(0x427E0558UL))
+#define bFM3_EXBUS_TIM2_WADC3                  *((volatile unsigned int*)(0x427E055CUL))
+#define bFM3_EXBUS_TIM2_WWEC0                  *((volatile unsigned int*)(0x427E0560UL))
+#define bFM3_EXBUS_TIM2_WWEC1                  *((volatile unsigned int*)(0x427E0564UL))
+#define bFM3_EXBUS_TIM2_WWEC2                  *((volatile unsigned int*)(0x427E0568UL))
+#define bFM3_EXBUS_TIM2_WWEC3                  *((volatile unsigned int*)(0x427E056CUL))
+#define bFM3_EXBUS_TIM2_WIDLC0                 *((volatile unsigned int*)(0x427E0570UL))
+#define bFM3_EXBUS_TIM2_WIDLC1                 *((volatile unsigned int*)(0x427E0574UL))
+#define bFM3_EXBUS_TIM2_WIDLC2                 *((volatile unsigned int*)(0x427E0578UL))
+#define bFM3_EXBUS_TIM2_WIDLC3                 *((volatile unsigned int*)(0x427E057CUL))
+#define bFM3_EXBUS_TIM3_RACC0                  *((volatile unsigned int*)(0x427E0580UL))
+#define bFM3_EXBUS_TIM3_RACC1                  *((volatile unsigned int*)(0x427E0584UL))
+#define bFM3_EXBUS_TIM3_RACC2                  *((volatile unsigned int*)(0x427E0588UL))
+#define bFM3_EXBUS_TIM3_RACC3                  *((volatile unsigned int*)(0x427E058CUL))
+#define bFM3_EXBUS_TIM3_RADC0                  *((volatile unsigned int*)(0x427E0590UL))
+#define bFM3_EXBUS_TIM3_RADC1                  *((volatile unsigned int*)(0x427E0594UL))
+#define bFM3_EXBUS_TIM3_RADC2                  *((volatile unsigned int*)(0x427E0598UL))
+#define bFM3_EXBUS_TIM3_RADC3                  *((volatile unsigned int*)(0x427E059CUL))
+#define bFM3_EXBUS_TIM3_FRADC0                 *((volatile unsigned int*)(0x427E05A0UL))
+#define bFM3_EXBUS_TIM3_FRADC1                 *((volatile unsigned int*)(0x427E05A4UL))
+#define bFM3_EXBUS_TIM3_FRADC2                 *((volatile unsigned int*)(0x427E05A8UL))
+#define bFM3_EXBUS_TIM3_FRADC3                 *((volatile unsigned int*)(0x427E05ACUL))
+#define bFM3_EXBUS_TIM3_RIDLC0                 *((volatile unsigned int*)(0x427E05B0UL))
+#define bFM3_EXBUS_TIM3_RIDLC1                 *((volatile unsigned int*)(0x427E05B4UL))
+#define bFM3_EXBUS_TIM3_RIDLC2                 *((volatile unsigned int*)(0x427E05B8UL))
+#define bFM3_EXBUS_TIM3_RIDLC3                 *((volatile unsigned int*)(0x427E05BCUL))
+#define bFM3_EXBUS_TIM3_WACC0                  *((volatile unsigned int*)(0x427E05C0UL))
+#define bFM3_EXBUS_TIM3_WACC1                  *((volatile unsigned int*)(0x427E05C4UL))
+#define bFM3_EXBUS_TIM3_WACC2                  *((volatile unsigned int*)(0x427E05C8UL))
+#define bFM3_EXBUS_TIM3_WACC3                  *((volatile unsigned int*)(0x427E05CCUL))
+#define bFM3_EXBUS_TIM3_WADC0                  *((volatile unsigned int*)(0x427E05D0UL))
+#define bFM3_EXBUS_TIM3_WADC1                  *((volatile unsigned int*)(0x427E05D4UL))
+#define bFM3_EXBUS_TIM3_WADC2                  *((volatile unsigned int*)(0x427E05D8UL))
+#define bFM3_EXBUS_TIM3_WADC3                  *((volatile unsigned int*)(0x427E05DCUL))
+#define bFM3_EXBUS_TIM3_WWEC0                  *((volatile unsigned int*)(0x427E05E0UL))
+#define bFM3_EXBUS_TIM3_WWEC1                  *((volatile unsigned int*)(0x427E05E4UL))
+#define bFM3_EXBUS_TIM3_WWEC2                  *((volatile unsigned int*)(0x427E05E8UL))
+#define bFM3_EXBUS_TIM3_WWEC3                  *((volatile unsigned int*)(0x427E05ECUL))
+#define bFM3_EXBUS_TIM3_WIDLC0                 *((volatile unsigned int*)(0x427E05F0UL))
+#define bFM3_EXBUS_TIM3_WIDLC1                 *((volatile unsigned int*)(0x427E05F4UL))
+#define bFM3_EXBUS_TIM3_WIDLC2                 *((volatile unsigned int*)(0x427E05F8UL))
+#define bFM3_EXBUS_TIM3_WIDLC3                 *((volatile unsigned int*)(0x427E05FCUL))
+#define bFM3_EXBUS_TIM4_RACC0                  *((volatile unsigned int*)(0x427E0600UL))
+#define bFM3_EXBUS_TIM4_RACC1                  *((volatile unsigned int*)(0x427E0604UL))
+#define bFM3_EXBUS_TIM4_RACC2                  *((volatile unsigned int*)(0x427E0608UL))
+#define bFM3_EXBUS_TIM4_RACC3                  *((volatile unsigned int*)(0x427E060CUL))
+#define bFM3_EXBUS_TIM4_RADC0                  *((volatile unsigned int*)(0x427E0610UL))
+#define bFM3_EXBUS_TIM4_RADC1                  *((volatile unsigned int*)(0x427E0614UL))
+#define bFM3_EXBUS_TIM4_RADC2                  *((volatile unsigned int*)(0x427E0618UL))
+#define bFM3_EXBUS_TIM4_RADC3                  *((volatile unsigned int*)(0x427E061CUL))
+#define bFM3_EXBUS_TIM4_FRADC0                 *((volatile unsigned int*)(0x427E0620UL))
+#define bFM3_EXBUS_TIM4_FRADC1                 *((volatile unsigned int*)(0x427E0624UL))
+#define bFM3_EXBUS_TIM4_FRADC2                 *((volatile unsigned int*)(0x427E0628UL))
+#define bFM3_EXBUS_TIM4_FRADC3                 *((volatile unsigned int*)(0x427E062CUL))
+#define bFM3_EXBUS_TIM4_RIDLC0                 *((volatile unsigned int*)(0x427E0630UL))
+#define bFM3_EXBUS_TIM4_RIDLC1                 *((volatile unsigned int*)(0x427E0634UL))
+#define bFM3_EXBUS_TIM4_RIDLC2                 *((volatile unsigned int*)(0x427E0638UL))
+#define bFM3_EXBUS_TIM4_RIDLC3                 *((volatile unsigned int*)(0x427E063CUL))
+#define bFM3_EXBUS_TIM4_WACC0                  *((volatile unsigned int*)(0x427E0640UL))
+#define bFM3_EXBUS_TIM4_WACC1                  *((volatile unsigned int*)(0x427E0644UL))
+#define bFM3_EXBUS_TIM4_WACC2                  *((volatile unsigned int*)(0x427E0648UL))
+#define bFM3_EXBUS_TIM4_WACC3                  *((volatile unsigned int*)(0x427E064CUL))
+#define bFM3_EXBUS_TIM4_WADC0                  *((volatile unsigned int*)(0x427E0650UL))
+#define bFM3_EXBUS_TIM4_WADC1                  *((volatile unsigned int*)(0x427E0654UL))
+#define bFM3_EXBUS_TIM4_WADC2                  *((volatile unsigned int*)(0x427E0658UL))
+#define bFM3_EXBUS_TIM4_WADC3                  *((volatile unsigned int*)(0x427E065CUL))
+#define bFM3_EXBUS_TIM4_WWEC0                  *((volatile unsigned int*)(0x427E0660UL))
+#define bFM3_EXBUS_TIM4_WWEC1                  *((volatile unsigned int*)(0x427E0664UL))
+#define bFM3_EXBUS_TIM4_WWEC2                  *((volatile unsigned int*)(0x427E0668UL))
+#define bFM3_EXBUS_TIM4_WWEC3                  *((volatile unsigned int*)(0x427E066CUL))
+#define bFM3_EXBUS_TIM4_WIDLC0                 *((volatile unsigned int*)(0x427E0670UL))
+#define bFM3_EXBUS_TIM4_WIDLC1                 *((volatile unsigned int*)(0x427E0674UL))
+#define bFM3_EXBUS_TIM4_WIDLC2                 *((volatile unsigned int*)(0x427E0678UL))
+#define bFM3_EXBUS_TIM4_WIDLC3                 *((volatile unsigned int*)(0x427E067CUL))
+#define bFM3_EXBUS_TIM5_RACC0                  *((volatile unsigned int*)(0x427E0680UL))
+#define bFM3_EXBUS_TIM5_RACC1                  *((volatile unsigned int*)(0x427E0684UL))
+#define bFM3_EXBUS_TIM5_RACC2                  *((volatile unsigned int*)(0x427E0688UL))
+#define bFM3_EXBUS_TIM5_RACC3                  *((volatile unsigned int*)(0x427E068CUL))
+#define bFM3_EXBUS_TIM5_RADC0                  *((volatile unsigned int*)(0x427E0690UL))
+#define bFM3_EXBUS_TIM5_RADC1                  *((volatile unsigned int*)(0x427E0694UL))
+#define bFM3_EXBUS_TIM5_RADC2                  *((volatile unsigned int*)(0x427E0698UL))
+#define bFM3_EXBUS_TIM5_RADC3                  *((volatile unsigned int*)(0x427E069CUL))
+#define bFM3_EXBUS_TIM5_FRADC0                 *((volatile unsigned int*)(0x427E06A0UL))
+#define bFM3_EXBUS_TIM5_FRADC1                 *((volatile unsigned int*)(0x427E06A4UL))
+#define bFM3_EXBUS_TIM5_FRADC2                 *((volatile unsigned int*)(0x427E06A8UL))
+#define bFM3_EXBUS_TIM5_FRADC3                 *((volatile unsigned int*)(0x427E06ACUL))
+#define bFM3_EXBUS_TIM5_RIDLC0                 *((volatile unsigned int*)(0x427E06B0UL))
+#define bFM3_EXBUS_TIM5_RIDLC1                 *((volatile unsigned int*)(0x427E06B4UL))
+#define bFM3_EXBUS_TIM5_RIDLC2                 *((volatile unsigned int*)(0x427E06B8UL))
+#define bFM3_EXBUS_TIM5_RIDLC3                 *((volatile unsigned int*)(0x427E06BCUL))
+#define bFM3_EXBUS_TIM5_WACC0                  *((volatile unsigned int*)(0x427E06C0UL))
+#define bFM3_EXBUS_TIM5_WACC1                  *((volatile unsigned int*)(0x427E06C4UL))
+#define bFM3_EXBUS_TIM5_WACC2                  *((volatile unsigned int*)(0x427E06C8UL))
+#define bFM3_EXBUS_TIM5_WACC3                  *((volatile unsigned int*)(0x427E06CCUL))
+#define bFM3_EXBUS_TIM5_WADC0                  *((volatile unsigned int*)(0x427E06D0UL))
+#define bFM3_EXBUS_TIM5_WADC1                  *((volatile unsigned int*)(0x427E06D4UL))
+#define bFM3_EXBUS_TIM5_WADC2                  *((volatile unsigned int*)(0x427E06D8UL))
+#define bFM3_EXBUS_TIM5_WADC3                  *((volatile unsigned int*)(0x427E06DCUL))
+#define bFM3_EXBUS_TIM5_WWEC0                  *((volatile unsigned int*)(0x427E06E0UL))
+#define bFM3_EXBUS_TIM5_WWEC1                  *((volatile unsigned int*)(0x427E06E4UL))
+#define bFM3_EXBUS_TIM5_WWEC2                  *((volatile unsigned int*)(0x427E06E8UL))
+#define bFM3_EXBUS_TIM5_WWEC3                  *((volatile unsigned int*)(0x427E06ECUL))
+#define bFM3_EXBUS_TIM5_WIDLC0                 *((volatile unsigned int*)(0x427E06F0UL))
+#define bFM3_EXBUS_TIM5_WIDLC1                 *((volatile unsigned int*)(0x427E06F4UL))
+#define bFM3_EXBUS_TIM5_WIDLC2                 *((volatile unsigned int*)(0x427E06F8UL))
+#define bFM3_EXBUS_TIM5_WIDLC3                 *((volatile unsigned int*)(0x427E06FCUL))
+#define bFM3_EXBUS_TIM6_RACC0                  *((volatile unsigned int*)(0x427E0700UL))
+#define bFM3_EXBUS_TIM6_RACC1                  *((volatile unsigned int*)(0x427E0704UL))
+#define bFM3_EXBUS_TIM6_RACC2                  *((volatile unsigned int*)(0x427E0708UL))
+#define bFM3_EXBUS_TIM6_RACC3                  *((volatile unsigned int*)(0x427E070CUL))
+#define bFM3_EXBUS_TIM6_RADC0                  *((volatile unsigned int*)(0x427E0710UL))
+#define bFM3_EXBUS_TIM6_RADC1                  *((volatile unsigned int*)(0x427E0714UL))
+#define bFM3_EXBUS_TIM6_RADC2                  *((volatile unsigned int*)(0x427E0718UL))
+#define bFM3_EXBUS_TIM6_RADC3                  *((volatile unsigned int*)(0x427E071CUL))
+#define bFM3_EXBUS_TIM6_FRADC0                 *((volatile unsigned int*)(0x427E0720UL))
+#define bFM3_EXBUS_TIM6_FRADC1                 *((volatile unsigned int*)(0x427E0724UL))
+#define bFM3_EXBUS_TIM6_FRADC2                 *((volatile unsigned int*)(0x427E0728UL))
+#define bFM3_EXBUS_TIM6_FRADC3                 *((volatile unsigned int*)(0x427E072CUL))
+#define bFM3_EXBUS_TIM6_RIDLC0                 *((volatile unsigned int*)(0x427E0730UL))
+#define bFM3_EXBUS_TIM6_RIDLC1                 *((volatile unsigned int*)(0x427E0734UL))
+#define bFM3_EXBUS_TIM6_RIDLC2                 *((volatile unsigned int*)(0x427E0738UL))
+#define bFM3_EXBUS_TIM6_RIDLC3                 *((volatile unsigned int*)(0x427E073CUL))
+#define bFM3_EXBUS_TIM6_WACC0                  *((volatile unsigned int*)(0x427E0740UL))
+#define bFM3_EXBUS_TIM6_WACC1                  *((volatile unsigned int*)(0x427E0744UL))
+#define bFM3_EXBUS_TIM6_WACC2                  *((volatile unsigned int*)(0x427E0748UL))
+#define bFM3_EXBUS_TIM6_WACC3                  *((volatile unsigned int*)(0x427E074CUL))
+#define bFM3_EXBUS_TIM6_WADC0                  *((volatile unsigned int*)(0x427E0750UL))
+#define bFM3_EXBUS_TIM6_WADC1                  *((volatile unsigned int*)(0x427E0754UL))
+#define bFM3_EXBUS_TIM6_WADC2                  *((volatile unsigned int*)(0x427E0758UL))
+#define bFM3_EXBUS_TIM6_WADC3                  *((volatile unsigned int*)(0x427E075CUL))
+#define bFM3_EXBUS_TIM6_WWEC0                  *((volatile unsigned int*)(0x427E0760UL))
+#define bFM3_EXBUS_TIM6_WWEC1                  *((volatile unsigned int*)(0x427E0764UL))
+#define bFM3_EXBUS_TIM6_WWEC2                  *((volatile unsigned int*)(0x427E0768UL))
+#define bFM3_EXBUS_TIM6_WWEC3                  *((volatile unsigned int*)(0x427E076CUL))
+#define bFM3_EXBUS_TIM6_WIDLC0                 *((volatile unsigned int*)(0x427E0770UL))
+#define bFM3_EXBUS_TIM6_WIDLC1                 *((volatile unsigned int*)(0x427E0774UL))
+#define bFM3_EXBUS_TIM6_WIDLC2                 *((volatile unsigned int*)(0x427E0778UL))
+#define bFM3_EXBUS_TIM6_WIDLC3                 *((volatile unsigned int*)(0x427E077CUL))
+#define bFM3_EXBUS_TIM7_RACC0                  *((volatile unsigned int*)(0x427E0780UL))
+#define bFM3_EXBUS_TIM7_RACC1                  *((volatile unsigned int*)(0x427E0784UL))
+#define bFM3_EXBUS_TIM7_RACC2                  *((volatile unsigned int*)(0x427E0788UL))
+#define bFM3_EXBUS_TIM7_RACC3                  *((volatile unsigned int*)(0x427E078CUL))
+#define bFM3_EXBUS_TIM7_RADC0                  *((volatile unsigned int*)(0x427E0790UL))
+#define bFM3_EXBUS_TIM7_RADC1                  *((volatile unsigned int*)(0x427E0794UL))
+#define bFM3_EXBUS_TIM7_RADC2                  *((volatile unsigned int*)(0x427E0798UL))
+#define bFM3_EXBUS_TIM7_RADC3                  *((volatile unsigned int*)(0x427E079CUL))
+#define bFM3_EXBUS_TIM7_FRADC0                 *((volatile unsigned int*)(0x427E07A0UL))
+#define bFM3_EXBUS_TIM7_FRADC1                 *((volatile unsigned int*)(0x427E07A4UL))
+#define bFM3_EXBUS_TIM7_FRADC2                 *((volatile unsigned int*)(0x427E07A8UL))
+#define bFM3_EXBUS_TIM7_FRADC3                 *((volatile unsigned int*)(0x427E07ACUL))
+#define bFM3_EXBUS_TIM7_RIDLC0                 *((volatile unsigned int*)(0x427E07B0UL))
+#define bFM3_EXBUS_TIM7_RIDLC1                 *((volatile unsigned int*)(0x427E07B4UL))
+#define bFM3_EXBUS_TIM7_RIDLC2                 *((volatile unsigned int*)(0x427E07B8UL))
+#define bFM3_EXBUS_TIM7_RIDLC3                 *((volatile unsigned int*)(0x427E07BCUL))
+#define bFM3_EXBUS_TIM7_WACC0                  *((volatile unsigned int*)(0x427E07C0UL))
+#define bFM3_EXBUS_TIM7_WACC1                  *((volatile unsigned int*)(0x427E07C4UL))
+#define bFM3_EXBUS_TIM7_WACC2                  *((volatile unsigned int*)(0x427E07C8UL))
+#define bFM3_EXBUS_TIM7_WACC3                  *((volatile unsigned int*)(0x427E07CCUL))
+#define bFM3_EXBUS_TIM7_WADC0                  *((volatile unsigned int*)(0x427E07D0UL))
+#define bFM3_EXBUS_TIM7_WADC1                  *((volatile unsigned int*)(0x427E07D4UL))
+#define bFM3_EXBUS_TIM7_WADC2                  *((volatile unsigned int*)(0x427E07D8UL))
+#define bFM3_EXBUS_TIM7_WADC3                  *((volatile unsigned int*)(0x427E07DCUL))
+#define bFM3_EXBUS_TIM7_WWEC0                  *((volatile unsigned int*)(0x427E07E0UL))
+#define bFM3_EXBUS_TIM7_WWEC1                  *((volatile unsigned int*)(0x427E07E4UL))
+#define bFM3_EXBUS_TIM7_WWEC2                  *((volatile unsigned int*)(0x427E07E8UL))
+#define bFM3_EXBUS_TIM7_WWEC3                  *((volatile unsigned int*)(0x427E07ECUL))
+#define bFM3_EXBUS_TIM7_WIDLC0                 *((volatile unsigned int*)(0x427E07F0UL))
+#define bFM3_EXBUS_TIM7_WIDLC1                 *((volatile unsigned int*)(0x427E07F4UL))
+#define bFM3_EXBUS_TIM7_WIDLC2                 *((volatile unsigned int*)(0x427E07F8UL))
+#define bFM3_EXBUS_TIM7_WIDLC3                 *((volatile unsigned int*)(0x427E07FCUL))
+#define bFM3_EXBUS_AREA0_ADDR0                 *((volatile unsigned int*)(0x427E0800UL))
+#define bFM3_EXBUS_AREA0_ADDR1                 *((volatile unsigned int*)(0x427E0804UL))
+#define bFM3_EXBUS_AREA0_ADDR2                 *((volatile unsigned int*)(0x427E0808UL))
+#define bFM3_EXBUS_AREA0_ADDR3                 *((volatile unsigned int*)(0x427E080CUL))
+#define bFM3_EXBUS_AREA0_ADDR4                 *((volatile unsigned int*)(0x427E0810UL))
+#define bFM3_EXBUS_AREA0_ADDR5                 *((volatile unsigned int*)(0x427E0814UL))
+#define bFM3_EXBUS_AREA0_ADDR6                 *((volatile unsigned int*)(0x427E0818UL))
+#define bFM3_EXBUS_AREA0_ADDR7                 *((volatile unsigned int*)(0x427E081CUL))
+#define bFM3_EXBUS_AREA0_MASK0                 *((volatile unsigned int*)(0x427E0840UL))
+#define bFM3_EXBUS_AREA0_MASK1                 *((volatile unsigned int*)(0x427E0844UL))
+#define bFM3_EXBUS_AREA0_MASK2                 *((volatile unsigned int*)(0x427E0848UL))
+#define bFM3_EXBUS_AREA0_MASK3                 *((volatile unsigned int*)(0x427E084CUL))
+#define bFM3_EXBUS_AREA0_MASK4                 *((volatile unsigned int*)(0x427E0850UL))
+#define bFM3_EXBUS_AREA0_MASK5                 *((volatile unsigned int*)(0x427E0854UL))
+#define bFM3_EXBUS_AREA0_MASK6                 *((volatile unsigned int*)(0x427E0858UL))
+#define bFM3_EXBUS_AREA1_ADDR0                 *((volatile unsigned int*)(0x427E0880UL))
+#define bFM3_EXBUS_AREA1_ADDR1                 *((volatile unsigned int*)(0x427E0884UL))
+#define bFM3_EXBUS_AREA1_ADDR2                 *((volatile unsigned int*)(0x427E0888UL))
+#define bFM3_EXBUS_AREA1_ADDR3                 *((volatile unsigned int*)(0x427E088CUL))
+#define bFM3_EXBUS_AREA1_ADDR4                 *((volatile unsigned int*)(0x427E0890UL))
+#define bFM3_EXBUS_AREA1_ADDR5                 *((volatile unsigned int*)(0x427E0894UL))
+#define bFM3_EXBUS_AREA1_ADDR6                 *((volatile unsigned int*)(0x427E0898UL))
+#define bFM3_EXBUS_AREA1_ADDR7                 *((volatile unsigned int*)(0x427E089CUL))
+#define bFM3_EXBUS_AREA1_MASK0                 *((volatile unsigned int*)(0x427E08C0UL))
+#define bFM3_EXBUS_AREA1_MASK1                 *((volatile unsigned int*)(0x427E08C4UL))
+#define bFM3_EXBUS_AREA1_MASK2                 *((volatile unsigned int*)(0x427E08C8UL))
+#define bFM3_EXBUS_AREA1_MASK3                 *((volatile unsigned int*)(0x427E08CCUL))
+#define bFM3_EXBUS_AREA1_MASK4                 *((volatile unsigned int*)(0x427E08D0UL))
+#define bFM3_EXBUS_AREA1_MASK5                 *((volatile unsigned int*)(0x427E08D4UL))
+#define bFM3_EXBUS_AREA1_MASK6                 *((volatile unsigned int*)(0x427E08D8UL))
+#define bFM3_EXBUS_AREA2_ADDR0                 *((volatile unsigned int*)(0x427E0900UL))
+#define bFM3_EXBUS_AREA2_ADDR1                 *((volatile unsigned int*)(0x427E0904UL))
+#define bFM3_EXBUS_AREA2_ADDR2                 *((volatile unsigned int*)(0x427E0908UL))
+#define bFM3_EXBUS_AREA2_ADDR3                 *((volatile unsigned int*)(0x427E090CUL))
+#define bFM3_EXBUS_AREA2_ADDR4                 *((volatile unsigned int*)(0x427E0910UL))
+#define bFM3_EXBUS_AREA2_ADDR5                 *((volatile unsigned int*)(0x427E0914UL))
+#define bFM3_EXBUS_AREA2_ADDR6                 *((volatile unsigned int*)(0x427E0918UL))
+#define bFM3_EXBUS_AREA2_ADDR7                 *((volatile unsigned int*)(0x427E091CUL))
+#define bFM3_EXBUS_AREA2_MASK0                 *((volatile unsigned int*)(0x427E0940UL))
+#define bFM3_EXBUS_AREA2_MASK1                 *((volatile unsigned int*)(0x427E0944UL))
+#define bFM3_EXBUS_AREA2_MASK2                 *((volatile unsigned int*)(0x427E0948UL))
+#define bFM3_EXBUS_AREA2_MASK3                 *((volatile unsigned int*)(0x427E094CUL))
+#define bFM3_EXBUS_AREA2_MASK4                 *((volatile unsigned int*)(0x427E0950UL))
+#define bFM3_EXBUS_AREA2_MASK5                 *((volatile unsigned int*)(0x427E0954UL))
+#define bFM3_EXBUS_AREA2_MASK6                 *((volatile unsigned int*)(0x427E0958UL))
+#define bFM3_EXBUS_AREA3_ADDR0                 *((volatile unsigned int*)(0x427E0980UL))
+#define bFM3_EXBUS_AREA3_ADDR1                 *((volatile unsigned int*)(0x427E0984UL))
+#define bFM3_EXBUS_AREA3_ADDR2                 *((volatile unsigned int*)(0x427E0988UL))
+#define bFM3_EXBUS_AREA3_ADDR3                 *((volatile unsigned int*)(0x427E098CUL))
+#define bFM3_EXBUS_AREA3_ADDR4                 *((volatile unsigned int*)(0x427E0990UL))
+#define bFM3_EXBUS_AREA3_ADDR5                 *((volatile unsigned int*)(0x427E0994UL))
+#define bFM3_EXBUS_AREA3_ADDR6                 *((volatile unsigned int*)(0x427E0998UL))
+#define bFM3_EXBUS_AREA3_ADDR7                 *((volatile unsigned int*)(0x427E099CUL))
+#define bFM3_EXBUS_AREA3_MASK0                 *((volatile unsigned int*)(0x427E09C0UL))
+#define bFM3_EXBUS_AREA3_MASK1                 *((volatile unsigned int*)(0x427E09C4UL))
+#define bFM3_EXBUS_AREA3_MASK2                 *((volatile unsigned int*)(0x427E09C8UL))
+#define bFM3_EXBUS_AREA3_MASK3                 *((volatile unsigned int*)(0x427E09CCUL))
+#define bFM3_EXBUS_AREA3_MASK4                 *((volatile unsigned int*)(0x427E09D0UL))
+#define bFM3_EXBUS_AREA3_MASK5                 *((volatile unsigned int*)(0x427E09D4UL))
+#define bFM3_EXBUS_AREA3_MASK6                 *((volatile unsigned int*)(0x427E09D8UL))
+#define bFM3_EXBUS_AREA4_ADDR0                 *((volatile unsigned int*)(0x427E0A00UL))
+#define bFM3_EXBUS_AREA4_ADDR1                 *((volatile unsigned int*)(0x427E0A04UL))
+#define bFM3_EXBUS_AREA4_ADDR2                 *((volatile unsigned int*)(0x427E0A08UL))
+#define bFM3_EXBUS_AREA4_ADDR3                 *((volatile unsigned int*)(0x427E0A0CUL))
+#define bFM3_EXBUS_AREA4_ADDR4                 *((volatile unsigned int*)(0x427E0A10UL))
+#define bFM3_EXBUS_AREA4_ADDR5                 *((volatile unsigned int*)(0x427E0A14UL))
+#define bFM3_EXBUS_AREA4_ADDR6                 *((volatile unsigned int*)(0x427E0A18UL))
+#define bFM3_EXBUS_AREA4_ADDR7                 *((volatile unsigned int*)(0x427E0A1CUL))
+#define bFM3_EXBUS_AREA4_MASK0                 *((volatile unsigned int*)(0x427E0A40UL))
+#define bFM3_EXBUS_AREA4_MASK1                 *((volatile unsigned int*)(0x427E0A44UL))
+#define bFM3_EXBUS_AREA4_MASK2                 *((volatile unsigned int*)(0x427E0A48UL))
+#define bFM3_EXBUS_AREA4_MASK3                 *((volatile unsigned int*)(0x427E0A4CUL))
+#define bFM3_EXBUS_AREA4_MASK4                 *((volatile unsigned int*)(0x427E0A50UL))
+#define bFM3_EXBUS_AREA4_MASK5                 *((volatile unsigned int*)(0x427E0A54UL))
+#define bFM3_EXBUS_AREA4_MASK6                 *((volatile unsigned int*)(0x427E0A58UL))
+#define bFM3_EXBUS_AREA5_ADDR0                 *((volatile unsigned int*)(0x427E0A80UL))
+#define bFM3_EXBUS_AREA5_ADDR1                 *((volatile unsigned int*)(0x427E0A84UL))
+#define bFM3_EXBUS_AREA5_ADDR2                 *((volatile unsigned int*)(0x427E0A88UL))
+#define bFM3_EXBUS_AREA5_ADDR3                 *((volatile unsigned int*)(0x427E0A8CUL))
+#define bFM3_EXBUS_AREA5_ADDR4                 *((volatile unsigned int*)(0x427E0A90UL))
+#define bFM3_EXBUS_AREA5_ADDR5                 *((volatile unsigned int*)(0x427E0A94UL))
+#define bFM3_EXBUS_AREA5_ADDR6                 *((volatile unsigned int*)(0x427E0A98UL))
+#define bFM3_EXBUS_AREA5_ADDR7                 *((volatile unsigned int*)(0x427E0A9CUL))
+#define bFM3_EXBUS_AREA5_MASK0                 *((volatile unsigned int*)(0x427E0AC0UL))
+#define bFM3_EXBUS_AREA5_MASK1                 *((volatile unsigned int*)(0x427E0AC4UL))
+#define bFM3_EXBUS_AREA5_MASK2                 *((volatile unsigned int*)(0x427E0AC8UL))
+#define bFM3_EXBUS_AREA5_MASK3                 *((volatile unsigned int*)(0x427E0ACCUL))
+#define bFM3_EXBUS_AREA5_MASK4                 *((volatile unsigned int*)(0x427E0AD0UL))
+#define bFM3_EXBUS_AREA5_MASK5                 *((volatile unsigned int*)(0x427E0AD4UL))
+#define bFM3_EXBUS_AREA5_MASK6                 *((volatile unsigned int*)(0x427E0AD8UL))
+#define bFM3_EXBUS_AREA6_ADDR0                 *((volatile unsigned int*)(0x427E0B00UL))
+#define bFM3_EXBUS_AREA6_ADDR1                 *((volatile unsigned int*)(0x427E0B04UL))
+#define bFM3_EXBUS_AREA6_ADDR2                 *((volatile unsigned int*)(0x427E0B08UL))
+#define bFM3_EXBUS_AREA6_ADDR3                 *((volatile unsigned int*)(0x427E0B0CUL))
+#define bFM3_EXBUS_AREA6_ADDR4                 *((volatile unsigned int*)(0x427E0B10UL))
+#define bFM3_EXBUS_AREA6_ADDR5                 *((volatile unsigned int*)(0x427E0B14UL))
+#define bFM3_EXBUS_AREA6_ADDR6                 *((volatile unsigned int*)(0x427E0B18UL))
+#define bFM3_EXBUS_AREA6_ADDR7                 *((volatile unsigned int*)(0x427E0B1CUL))
+#define bFM3_EXBUS_AREA6_MASK0                 *((volatile unsigned int*)(0x427E0B40UL))
+#define bFM3_EXBUS_AREA6_MASK1                 *((volatile unsigned int*)(0x427E0B44UL))
+#define bFM3_EXBUS_AREA6_MASK2                 *((volatile unsigned int*)(0x427E0B48UL))
+#define bFM3_EXBUS_AREA6_MASK3                 *((volatile unsigned int*)(0x427E0B4CUL))
+#define bFM3_EXBUS_AREA6_MASK4                 *((volatile unsigned int*)(0x427E0B50UL))
+#define bFM3_EXBUS_AREA6_MASK5                 *((volatile unsigned int*)(0x427E0B54UL))
+#define bFM3_EXBUS_AREA6_MASK6                 *((volatile unsigned int*)(0x427E0B58UL))
+#define bFM3_EXBUS_AREA7_ADDR0                 *((volatile unsigned int*)(0x427E0B80UL))
+#define bFM3_EXBUS_AREA7_ADDR1                 *((volatile unsigned int*)(0x427E0B84UL))
+#define bFM3_EXBUS_AREA7_ADDR2                 *((volatile unsigned int*)(0x427E0B88UL))
+#define bFM3_EXBUS_AREA7_ADDR3                 *((volatile unsigned int*)(0x427E0B8CUL))
+#define bFM3_EXBUS_AREA7_ADDR4                 *((volatile unsigned int*)(0x427E0B90UL))
+#define bFM3_EXBUS_AREA7_ADDR5                 *((volatile unsigned int*)(0x427E0B94UL))
+#define bFM3_EXBUS_AREA7_ADDR6                 *((volatile unsigned int*)(0x427E0B98UL))
+#define bFM3_EXBUS_AREA7_ADDR7                 *((volatile unsigned int*)(0x427E0B9CUL))
+#define bFM3_EXBUS_AREA7_MASK0                 *((volatile unsigned int*)(0x427E0BC0UL))
+#define bFM3_EXBUS_AREA7_MASK1                 *((volatile unsigned int*)(0x427E0BC4UL))
+#define bFM3_EXBUS_AREA7_MASK2                 *((volatile unsigned int*)(0x427E0BC8UL))
+#define bFM3_EXBUS_AREA7_MASK3                 *((volatile unsigned int*)(0x427E0BCCUL))
+#define bFM3_EXBUS_AREA7_MASK4                 *((volatile unsigned int*)(0x427E0BD0UL))
+#define bFM3_EXBUS_AREA7_MASK5                 *((volatile unsigned int*)(0x427E0BD4UL))
+#define bFM3_EXBUS_AREA7_MASK6                 *((volatile unsigned int*)(0x427E0BD8UL))
+#define bFM3_EXBUS_ATIM0_ALC0                  *((volatile unsigned int*)(0x427E0C00UL))
+#define bFM3_EXBUS_ATIM0_ALC1                  *((volatile unsigned int*)(0x427E0C04UL))
+#define bFM3_EXBUS_ATIM0_ALC2                  *((volatile unsigned int*)(0x427E0C08UL))
+#define bFM3_EXBUS_ATIM0_ALC3                  *((volatile unsigned int*)(0x427E0C0CUL))
+#define bFM3_EXBUS_ATIM0_ALES0                 *((volatile unsigned int*)(0x427E0C10UL))
+#define bFM3_EXBUS_ATIM0_ALES1                 *((volatile unsigned int*)(0x427E0C14UL))
+#define bFM3_EXBUS_ATIM0_ALES2                 *((volatile unsigned int*)(0x427E0C18UL))
+#define bFM3_EXBUS_ATIM0_ALES3                 *((volatile unsigned int*)(0x427E0C1CUL))
+#define bFM3_EXBUS_ATIM0_ALEW0                 *((volatile unsigned int*)(0x427E0C20UL))
+#define bFM3_EXBUS_ATIM0_ALEW1                 *((volatile unsigned int*)(0x427E0C24UL))
+#define bFM3_EXBUS_ATIM0_ALEW2                 *((volatile unsigned int*)(0x427E0C28UL))
+#define bFM3_EXBUS_ATIM0_ALEW3                 *((volatile unsigned int*)(0x427E0C2CUL))
+#define bFM3_EXBUS_ATIM1_ALC0                  *((volatile unsigned int*)(0x427E0C80UL))
+#define bFM3_EXBUS_ATIM1_ALC1                  *((volatile unsigned int*)(0x427E0C84UL))
+#define bFM3_EXBUS_ATIM1_ALC2                  *((volatile unsigned int*)(0x427E0C88UL))
+#define bFM3_EXBUS_ATIM1_ALC3                  *((volatile unsigned int*)(0x427E0C8CUL))
+#define bFM3_EXBUS_ATIM1_ALES0                 *((volatile unsigned int*)(0x427E0C90UL))
+#define bFM3_EXBUS_ATIM1_ALES1                 *((volatile unsigned int*)(0x427E0C94UL))
+#define bFM3_EXBUS_ATIM1_ALES2                 *((volatile unsigned int*)(0x427E0C98UL))
+#define bFM3_EXBUS_ATIM1_ALES3                 *((volatile unsigned int*)(0x427E0C9CUL))
+#define bFM3_EXBUS_ATIM1_ALEW0                 *((volatile unsigned int*)(0x427E0CA0UL))
+#define bFM3_EXBUS_ATIM1_ALEW1                 *((volatile unsigned int*)(0x427E0CA4UL))
+#define bFM3_EXBUS_ATIM1_ALEW2                 *((volatile unsigned int*)(0x427E0CA8UL))
+#define bFM3_EXBUS_ATIM1_ALEW3                 *((volatile unsigned int*)(0x427E0CACUL))
+#define bFM3_EXBUS_ATIM2_ALC0                  *((volatile unsigned int*)(0x427E0D00UL))
+#define bFM3_EXBUS_ATIM2_ALC1                  *((volatile unsigned int*)(0x427E0D04UL))
+#define bFM3_EXBUS_ATIM2_ALC2                  *((volatile unsigned int*)(0x427E0D08UL))
+#define bFM3_EXBUS_ATIM2_ALC3                  *((volatile unsigned int*)(0x427E0D0CUL))
+#define bFM3_EXBUS_ATIM2_ALES0                 *((volatile unsigned int*)(0x427E0D10UL))
+#define bFM3_EXBUS_ATIM2_ALES1                 *((volatile unsigned int*)(0x427E0D14UL))
+#define bFM3_EXBUS_ATIM2_ALES2                 *((volatile unsigned int*)(0x427E0D18UL))
+#define bFM3_EXBUS_ATIM2_ALES3                 *((volatile unsigned int*)(0x427E0D1CUL))
+#define bFM3_EXBUS_ATIM2_ALEW0                 *((volatile unsigned int*)(0x427E0D20UL))
+#define bFM3_EXBUS_ATIM2_ALEW1                 *((volatile unsigned int*)(0x427E0D24UL))
+#define bFM3_EXBUS_ATIM2_ALEW2                 *((volatile unsigned int*)(0x427E0D28UL))
+#define bFM3_EXBUS_ATIM2_ALEW3                 *((volatile unsigned int*)(0x427E0D2CUL))
+#define bFM3_EXBUS_ATIM3_ALC0                  *((volatile unsigned int*)(0x427E0D80UL))
+#define bFM3_EXBUS_ATIM3_ALC1                  *((volatile unsigned int*)(0x427E0D84UL))
+#define bFM3_EXBUS_ATIM3_ALC2                  *((volatile unsigned int*)(0x427E0D88UL))
+#define bFM3_EXBUS_ATIM3_ALC3                  *((volatile unsigned int*)(0x427E0D8CUL))
+#define bFM3_EXBUS_ATIM3_ALES0                 *((volatile unsigned int*)(0x427E0D90UL))
+#define bFM3_EXBUS_ATIM3_ALES1                 *((volatile unsigned int*)(0x427E0D94UL))
+#define bFM3_EXBUS_ATIM3_ALES2                 *((volatile unsigned int*)(0x427E0D98UL))
+#define bFM3_EXBUS_ATIM3_ALES3                 *((volatile unsigned int*)(0x427E0D9CUL))
+#define bFM3_EXBUS_ATIM3_ALEW0                 *((volatile unsigned int*)(0x427E0DA0UL))
+#define bFM3_EXBUS_ATIM3_ALEW1                 *((volatile unsigned int*)(0x427E0DA4UL))
+#define bFM3_EXBUS_ATIM3_ALEW2                 *((volatile unsigned int*)(0x427E0DA8UL))
+#define bFM3_EXBUS_ATIM3_ALEW3                 *((volatile unsigned int*)(0x427E0DACUL))
+#define bFM3_EXBUS_ATIM4_ALC0                  *((volatile unsigned int*)(0x427E0E00UL))
+#define bFM3_EXBUS_ATIM4_ALC1                  *((volatile unsigned int*)(0x427E0E04UL))
+#define bFM3_EXBUS_ATIM4_ALC2                  *((volatile unsigned int*)(0x427E0E08UL))
+#define bFM3_EXBUS_ATIM4_ALC3                  *((volatile unsigned int*)(0x427E0E0CUL))
+#define bFM3_EXBUS_ATIM4_ALES0                 *((volatile unsigned int*)(0x427E0E10UL))
+#define bFM3_EXBUS_ATIM4_ALES1                 *((volatile unsigned int*)(0x427E0E14UL))
+#define bFM3_EXBUS_ATIM4_ALES2                 *((volatile unsigned int*)(0x427E0E18UL))
+#define bFM3_EXBUS_ATIM4_ALES3                 *((volatile unsigned int*)(0x427E0E1CUL))
+#define bFM3_EXBUS_ATIM4_ALEW0                 *((volatile unsigned int*)(0x427E0E20UL))
+#define bFM3_EXBUS_ATIM4_ALEW1                 *((volatile unsigned int*)(0x427E0E24UL))
+#define bFM3_EXBUS_ATIM4_ALEW2                 *((volatile unsigned int*)(0x427E0E28UL))
+#define bFM3_EXBUS_ATIM4_ALEW3                 *((volatile unsigned int*)(0x427E0E2CUL))
+#define bFM3_EXBUS_ATIM5_ALC0                  *((volatile unsigned int*)(0x427E0E80UL))
+#define bFM3_EXBUS_ATIM5_ALC1                  *((volatile unsigned int*)(0x427E0E84UL))
+#define bFM3_EXBUS_ATIM5_ALC2                  *((volatile unsigned int*)(0x427E0E88UL))
+#define bFM3_EXBUS_ATIM5_ALC3                  *((volatile unsigned int*)(0x427E0E8CUL))
+#define bFM3_EXBUS_ATIM5_ALES0                 *((volatile unsigned int*)(0x427E0E90UL))
+#define bFM3_EXBUS_ATIM5_ALES1                 *((volatile unsigned int*)(0x427E0E94UL))
+#define bFM3_EXBUS_ATIM5_ALES2                 *((volatile unsigned int*)(0x427E0E98UL))
+#define bFM3_EXBUS_ATIM5_ALES3                 *((volatile unsigned int*)(0x427E0E9CUL))
+#define bFM3_EXBUS_ATIM5_ALEW0                 *((volatile unsigned int*)(0x427E0EA0UL))
+#define bFM3_EXBUS_ATIM5_ALEW1                 *((volatile unsigned int*)(0x427E0EA4UL))
+#define bFM3_EXBUS_ATIM5_ALEW2                 *((volatile unsigned int*)(0x427E0EA8UL))
+#define bFM3_EXBUS_ATIM5_ALEW3                 *((volatile unsigned int*)(0x427E0EACUL))
+#define bFM3_EXBUS_ATIM6_ALC0                  *((volatile unsigned int*)(0x427E0F00UL))
+#define bFM3_EXBUS_ATIM6_ALC1                  *((volatile unsigned int*)(0x427E0F04UL))
+#define bFM3_EXBUS_ATIM6_ALC2                  *((volatile unsigned int*)(0x427E0F08UL))
+#define bFM3_EXBUS_ATIM6_ALC3                  *((volatile unsigned int*)(0x427E0F0CUL))
+#define bFM3_EXBUS_ATIM6_ALES0                 *((volatile unsigned int*)(0x427E0F10UL))
+#define bFM3_EXBUS_ATIM6_ALES1                 *((volatile unsigned int*)(0x427E0F14UL))
+#define bFM3_EXBUS_ATIM6_ALES2                 *((volatile unsigned int*)(0x427E0F18UL))
+#define bFM3_EXBUS_ATIM6_ALES3                 *((volatile unsigned int*)(0x427E0F1CUL))
+#define bFM3_EXBUS_ATIM6_ALEW0                 *((volatile unsigned int*)(0x427E0F20UL))
+#define bFM3_EXBUS_ATIM6_ALEW1                 *((volatile unsigned int*)(0x427E0F24UL))
+#define bFM3_EXBUS_ATIM6_ALEW2                 *((volatile unsigned int*)(0x427E0F28UL))
+#define bFM3_EXBUS_ATIM6_ALEW3                 *((volatile unsigned int*)(0x427E0F2CUL))
+#define bFM3_EXBUS_ATIM7_ALC0                  *((volatile unsigned int*)(0x427E0F80UL))
+#define bFM3_EXBUS_ATIM7_ALC1                  *((volatile unsigned int*)(0x427E0F84UL))
+#define bFM3_EXBUS_ATIM7_ALC2                  *((volatile unsigned int*)(0x427E0F88UL))
+#define bFM3_EXBUS_ATIM7_ALC3                  *((volatile unsigned int*)(0x427E0F8CUL))
+#define bFM3_EXBUS_ATIM7_ALES0                 *((volatile unsigned int*)(0x427E0F90UL))
+#define bFM3_EXBUS_ATIM7_ALES1                 *((volatile unsigned int*)(0x427E0F94UL))
+#define bFM3_EXBUS_ATIM7_ALES2                 *((volatile unsigned int*)(0x427E0F98UL))
+#define bFM3_EXBUS_ATIM7_ALES3                 *((volatile unsigned int*)(0x427E0F9CUL))
+#define bFM3_EXBUS_ATIM7_ALEW0                 *((volatile unsigned int*)(0x427E0FA0UL))
+#define bFM3_EXBUS_ATIM7_ALEW1                 *((volatile unsigned int*)(0x427E0FA4UL))
+#define bFM3_EXBUS_ATIM7_ALEW2                 *((volatile unsigned int*)(0x427E0FA8UL))
+#define bFM3_EXBUS_ATIM7_ALEW3                 *((volatile unsigned int*)(0x427E0FACUL))
+#define bFM3_EXBUS_DCLKR_MDIV0                 *((volatile unsigned int*)(0x427E6000UL))
+#define bFM3_EXBUS_DCLKR_MDIV1                 *((volatile unsigned int*)(0x427E6004UL))
+#define bFM3_EXBUS_DCLKR_MDIV2                 *((volatile unsigned int*)(0x427E6008UL))
+#define bFM3_EXBUS_DCLKR_MDIV3                 *((volatile unsigned int*)(0x427E600CUL))
+#define bFM3_EXBUS_DCLKR_MCLKON                *((volatile unsigned int*)(0x427E6010UL))
+
+/* USB channel 0 registers */
+#define bFM3_USB0_HCNT_HOST                    *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT_URST                    *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT_DIRE                    *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT_URIRE                   *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT_RWKIRE                  *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT_RETRY                   *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT_CANCEL                  *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HCNT0_HOST                   *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT0_URST                   *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT0_DIRE                   *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT0_URIRE                  *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT1_RETRY                  *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42842080UL))
+#define bFM3_USB0_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42842084UL))
+#define bFM3_USB0_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42842088UL))
+#define bFM3_USB0_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x4284208CUL))
+#define bFM3_USB0_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42842090UL))
+#define bFM3_USB0_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42842094UL))
+#define bFM3_USB0_HIRQ_TCAN                    *((volatile unsigned int*)(0x4284209CUL))
+#define bFM3_USB0_HERR_HS0                     *((volatile unsigned int*)(0x428420A0UL))
+#define bFM3_USB0_HERR_HS1                     *((volatile unsigned int*)(0x428420A4UL))
+#define bFM3_USB0_HERR_STUFF                   *((volatile unsigned int*)(0x428420A8UL))
+#define bFM3_USB0_HERR_TGERR                   *((volatile unsigned int*)(0x428420ACUL))
+#define bFM3_USB0_HERR_CRC                     *((volatile unsigned int*)(0x428420B0UL))
+#define bFM3_USB0_HERR_TOUT                    *((volatile unsigned int*)(0x428420B4UL))
+#define bFM3_USB0_HERR_RERR                    *((volatile unsigned int*)(0x428420B8UL))
+#define bFM3_USB0_HERR_LSTOF                   *((volatile unsigned int*)(0x428420BCUL))
+#define bFM3_USB0_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42842100UL))
+#define bFM3_USB0_HSTATE_TMODE                 *((volatile unsigned int*)(0x42842104UL))
+#define bFM3_USB0_HSTATE_SUSP                  *((volatile unsigned int*)(0x42842108UL))
+#define bFM3_USB0_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x4284210CUL))
+#define bFM3_USB0_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42842110UL))
+#define bFM3_USB0_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42842114UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42842120UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42842124UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42842128UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x4284212CUL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42842130UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42842134UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42842138UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x4284213CUL))
+#define bFM3_USB0_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42842200UL))
+#define bFM3_USB0_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42842204UL))
+#define bFM3_USB0_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42842208UL))
+#define bFM3_USB0_HADR_ADDRESS0                *((volatile unsigned int*)(0x42842220UL))
+#define bFM3_USB0_HADR_ADDRESS1                *((volatile unsigned int*)(0x42842224UL))
+#define bFM3_USB0_HADR_ADDRESS2                *((volatile unsigned int*)(0x42842228UL))
+#define bFM3_USB0_HADR_ADDRESS3                *((volatile unsigned int*)(0x4284222CUL))
+#define bFM3_USB0_HADR_ADDRESS4                *((volatile unsigned int*)(0x42842230UL))
+#define bFM3_USB0_HADR_ADDRESS5                *((volatile unsigned int*)(0x42842234UL))
+#define bFM3_USB0_HADR_ADDRESS6                *((volatile unsigned int*)(0x42842238UL))
+#define bFM3_USB0_HEOF_EOF0                    *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF_EOF1                    *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF_EOF2                    *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF_EOF3                    *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF_EOF4                    *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF_EOF5                    *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF_EOF6                    *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF_EOF7                    *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF_EOF8                    *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF_EOF9                    *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF_EOF10                   *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF_EOF11                   *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF_EOF12                   *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF_EOF13                   *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HEOF_EOF14                   *((volatile unsigned int*)(0x428422B8UL))
+#define bFM3_USB0_HEOF_EOF15                   *((volatile unsigned int*)(0x428422BCUL))
+#define bFM3_USB0_HEOF0_EOF00                  *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF0_EOF01                  *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF0_EOF02                  *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF0_EOF03                  *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF0_EOF04                  *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF0_EOF05                  *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF0_EOF06                  *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF0_EOF07                  *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF1_EOF10                  *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF1_EOF11                  *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF1_EOF12                  *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF1_EOF13                  *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF1_EOF14                  *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF1_EOF15                  *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HFRAME_FRAME0                *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME_FRAME1                *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME_FRAME2                *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME_FRAME3                *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME_FRAME4                *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME_FRAME5                *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME_FRAME6                *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME_FRAME7                *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME_FRAME8                *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME_FRAME9                *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME_FRAME10               *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME0_FRAME03              *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME0_FRAME07              *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME1_FRAME13              *((volatile unsigned int*)(0x4284232CUL))
+#define bFM3_USB0_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42842380UL))
+#define bFM3_USB0_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42842384UL))
+#define bFM3_USB0_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42842388UL))
+#define bFM3_USB0_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x4284238CUL))
+#define bFM3_USB0_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42842390UL))
+#define bFM3_USB0_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42842394UL))
+#define bFM3_USB0_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42842398UL))
+#define bFM3_USB0_HTOKEN_TGGL                  *((volatile unsigned int*)(0x4284239CUL))
+#define bFM3_USB0_UDCC_PWC                     *((volatile unsigned int*)(0x42842400UL))
+#define bFM3_USB0_UDCC_RFBK                    *((volatile unsigned int*)(0x42842404UL))
+#define bFM3_USB0_UDCC_STALCLREN               *((volatile unsigned int*)(0x4284240CUL))
+#define bFM3_USB0_UDCC_USTP                    *((volatile unsigned int*)(0x42842410UL))
+#define bFM3_USB0_UDCC_HCONX                   *((volatile unsigned int*)(0x42842414UL))
+#define bFM3_USB0_UDCC_RESUM                   *((volatile unsigned int*)(0x42842418UL))
+#define bFM3_USB0_UDCC_RST                     *((volatile unsigned int*)(0x4284241CUL))
+#define bFM3_USB0_EP0C_PKS00                   *((volatile unsigned int*)(0x42842480UL))
+#define bFM3_USB0_EP0C_PKS01                   *((volatile unsigned int*)(0x42842484UL))
+#define bFM3_USB0_EP0C_PKS02                   *((volatile unsigned int*)(0x42842488UL))
+#define bFM3_USB0_EP0C_PKS03                   *((volatile unsigned int*)(0x4284248CUL))
+#define bFM3_USB0_EP0C_PKS04                   *((volatile unsigned int*)(0x42842490UL))
+#define bFM3_USB0_EP0C_PKS05                   *((volatile unsigned int*)(0x42842494UL))
+#define bFM3_USB0_EP0C_PKS06                   *((volatile unsigned int*)(0x42842498UL))
+#define bFM3_USB0_EP0C_STAL                    *((volatile unsigned int*)(0x428424A4UL))
+#define bFM3_USB0_EP1C_PKS10                   *((volatile unsigned int*)(0x42842500UL))
+#define bFM3_USB0_EP1C_PKS11                   *((volatile unsigned int*)(0x42842504UL))
+#define bFM3_USB0_EP1C_PKS12                   *((volatile unsigned int*)(0x42842508UL))
+#define bFM3_USB0_EP1C_PKS13                   *((volatile unsigned int*)(0x4284250CUL))
+#define bFM3_USB0_EP1C_PKS14                   *((volatile unsigned int*)(0x42842510UL))
+#define bFM3_USB0_EP1C_PKS15                   *((volatile unsigned int*)(0x42842514UL))
+#define bFM3_USB0_EP1C_PKS16                   *((volatile unsigned int*)(0x42842518UL))
+#define bFM3_USB0_EP1C_PKS17                   *((volatile unsigned int*)(0x4284251CUL))
+#define bFM3_USB0_EP1C_PKS18                   *((volatile unsigned int*)(0x42842520UL))
+#define bFM3_USB0_EP1C_STAL                    *((volatile unsigned int*)(0x42842524UL))
+#define bFM3_USB0_EP1C_NULE                    *((volatile unsigned int*)(0x42842528UL))
+#define bFM3_USB0_EP1C_DMAE                    *((volatile unsigned int*)(0x4284252CUL))
+#define bFM3_USB0_EP1C_DIR                     *((volatile unsigned int*)(0x42842530UL))
+#define bFM3_USB0_EP1C_TYPE0                   *((volatile unsigned int*)(0x42842534UL))
+#define bFM3_USB0_EP1C_TYPE1                   *((volatile unsigned int*)(0x42842538UL))
+#define bFM3_USB0_EP1C_EPEN                    *((volatile unsigned int*)(0x4284253CUL))
+#define bFM3_USB0_EP2C_PKS20                   *((volatile unsigned int*)(0x42842580UL))
+#define bFM3_USB0_EP2C_PKS21                   *((volatile unsigned int*)(0x42842584UL))
+#define bFM3_USB0_EP2C_PKS22                   *((volatile unsigned int*)(0x42842588UL))
+#define bFM3_USB0_EP2C_PKS23                   *((volatile unsigned int*)(0x4284258CUL))
+#define bFM3_USB0_EP2C_PKS24                   *((volatile unsigned int*)(0x42842590UL))
+#define bFM3_USB0_EP2C_PKS25                   *((volatile unsigned int*)(0x42842594UL))
+#define bFM3_USB0_EP2C_PKS26                   *((volatile unsigned int*)(0x42842598UL))
+#define bFM3_USB0_EP2C_STAL                    *((volatile unsigned int*)(0x428425A4UL))
+#define bFM3_USB0_EP2C_NULE                    *((volatile unsigned int*)(0x428425A8UL))
+#define bFM3_USB0_EP2C_DMAE                    *((volatile unsigned int*)(0x428425ACUL))
+#define bFM3_USB0_EP2C_DIR                     *((volatile unsigned int*)(0x428425B0UL))
+#define bFM3_USB0_EP2C_TYPE0                   *((volatile unsigned int*)(0x428425B4UL))
+#define bFM3_USB0_EP2C_TYPE1                   *((volatile unsigned int*)(0x428425B8UL))
+#define bFM3_USB0_EP2C_EPEN                    *((volatile unsigned int*)(0x428425BCUL))
+#define bFM3_USB0_EP3C_PKS30                   *((volatile unsigned int*)(0x42842600UL))
+#define bFM3_USB0_EP3C_PKS31                   *((volatile unsigned int*)(0x42842604UL))
+#define bFM3_USB0_EP3C_PKS32                   *((volatile unsigned int*)(0x42842608UL))
+#define bFM3_USB0_EP3C_PKS33                   *((volatile unsigned int*)(0x4284260CUL))
+#define bFM3_USB0_EP3C_PKS34                   *((volatile unsigned int*)(0x42842610UL))
+#define bFM3_USB0_EP3C_PKS35                   *((volatile unsigned int*)(0x42842614UL))
+#define bFM3_USB0_EP3C_PKS36                   *((volatile unsigned int*)(0x42842618UL))
+#define bFM3_USB0_EP3C_STAL                    *((volatile unsigned int*)(0x42842624UL))
+#define bFM3_USB0_EP3C_NULE                    *((volatile unsigned int*)(0x42842628UL))
+#define bFM3_USB0_EP3C_DMAE                    *((volatile unsigned int*)(0x4284262CUL))
+#define bFM3_USB0_EP3C_DIR                     *((volatile unsigned int*)(0x42842630UL))
+#define bFM3_USB0_EP3C_TYPE0                   *((volatile unsigned int*)(0x42842634UL))
+#define bFM3_USB0_EP3C_TYPE1                   *((volatile unsigned int*)(0x42842638UL))
+#define bFM3_USB0_EP3C_EPEN                    *((volatile unsigned int*)(0x4284263CUL))
+#define bFM3_USB0_EP4C_PKS40                   *((volatile unsigned int*)(0x42842680UL))
+#define bFM3_USB0_EP4C_PKS41                   *((volatile unsigned int*)(0x42842684UL))
+#define bFM3_USB0_EP4C_PKS42                   *((volatile unsigned int*)(0x42842688UL))
+#define bFM3_USB0_EP4C_PKS43                   *((volatile unsigned int*)(0x4284268CUL))
+#define bFM3_USB0_EP4C_PKS44                   *((volatile unsigned int*)(0x42842690UL))
+#define bFM3_USB0_EP4C_PKS45                   *((volatile unsigned int*)(0x42842694UL))
+#define bFM3_USB0_EP4C_PKS46                   *((volatile unsigned int*)(0x42842698UL))
+#define bFM3_USB0_EP4C_STAL                    *((volatile unsigned int*)(0x428426A4UL))
+#define bFM3_USB0_EP4C_NULE                    *((volatile unsigned int*)(0x428426A8UL))
+#define bFM3_USB0_EP4C_DMAE                    *((volatile unsigned int*)(0x428426ACUL))
+#define bFM3_USB0_EP4C_DIR                     *((volatile unsigned int*)(0x428426B0UL))
+#define bFM3_USB0_EP4C_TYPE0                   *((volatile unsigned int*)(0x428426B4UL))
+#define bFM3_USB0_EP4C_TYPE1                   *((volatile unsigned int*)(0x428426B8UL))
+#define bFM3_USB0_EP4C_EPEN                    *((volatile unsigned int*)(0x428426BCUL))
+#define bFM3_USB0_EP5C_PKS50                   *((volatile unsigned int*)(0x42842700UL))
+#define bFM3_USB0_EP5C_PKS51                   *((volatile unsigned int*)(0x42842704UL))
+#define bFM3_USB0_EP5C_PKS52                   *((volatile unsigned int*)(0x42842708UL))
+#define bFM3_USB0_EP5C_PKS53                   *((volatile unsigned int*)(0x4284270CUL))
+#define bFM3_USB0_EP5C_PKS54                   *((volatile unsigned int*)(0x42842710UL))
+#define bFM3_USB0_EP5C_PKS55                   *((volatile unsigned int*)(0x42842714UL))
+#define bFM3_USB0_EP5C_PKS56                   *((volatile unsigned int*)(0x42842718UL))
+#define bFM3_USB0_EP5C_STAL                    *((volatile unsigned int*)(0x42842724UL))
+#define bFM3_USB0_EP5C_NULE                    *((volatile unsigned int*)(0x42842728UL))
+#define bFM3_USB0_EP5C_DMAE                    *((volatile unsigned int*)(0x4284272CUL))
+#define bFM3_USB0_EP5C_DIR                     *((volatile unsigned int*)(0x42842730UL))
+#define bFM3_USB0_EP5C_TYPE0                   *((volatile unsigned int*)(0x42842734UL))
+#define bFM3_USB0_EP5C_TYPE1                   *((volatile unsigned int*)(0x42842738UL))
+#define bFM3_USB0_EP5C_EPEN                    *((volatile unsigned int*)(0x4284273CUL))
+#define bFM3_USB0_TMSP_TMSP0                   *((volatile unsigned int*)(0x42842780UL))
+#define bFM3_USB0_TMSP_TMSP1                   *((volatile unsigned int*)(0x42842784UL))
+#define bFM3_USB0_TMSP_TMSP2                   *((volatile unsigned int*)(0x42842788UL))
+#define bFM3_USB0_TMSP_TMSP3                   *((volatile unsigned int*)(0x4284278CUL))
+#define bFM3_USB0_TMSP_TMSP4                   *((volatile unsigned int*)(0x42842790UL))
+#define bFM3_USB0_TMSP_TMSP5                   *((volatile unsigned int*)(0x42842794UL))
+#define bFM3_USB0_TMSP_TMSP6                   *((volatile unsigned int*)(0x42842798UL))
+#define bFM3_USB0_TMSP_TMSP7                   *((volatile unsigned int*)(0x4284279CUL))
+#define bFM3_USB0_TMSP_TMSP8                   *((volatile unsigned int*)(0x428427A0UL))
+#define bFM3_USB0_TMSP_TMSP9                   *((volatile unsigned int*)(0x428427A4UL))
+#define bFM3_USB0_TMSP_TMSP10                  *((volatile unsigned int*)(0x428427A8UL))
+#define bFM3_USB0_UDCS_CONF                    *((volatile unsigned int*)(0x42842800UL))
+#define bFM3_USB0_UDCS_SETP                    *((volatile unsigned int*)(0x42842804UL))
+#define bFM3_USB0_UDCS_WKUP                    *((volatile unsigned int*)(0x42842808UL))
+#define bFM3_USB0_UDCS_BRST                    *((volatile unsigned int*)(0x4284280CUL))
+#define bFM3_USB0_UDCS_SOF                     *((volatile unsigned int*)(0x42842810UL))
+#define bFM3_USB0_UDCS_SUSP                    *((volatile unsigned int*)(0x42842814UL))
+#define bFM3_USB0_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42842820UL))
+#define bFM3_USB0_UDCIE_CONFN                  *((volatile unsigned int*)(0x42842824UL))
+#define bFM3_USB0_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42842828UL))
+#define bFM3_USB0_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x4284282CUL))
+#define bFM3_USB0_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42842830UL))
+#define bFM3_USB0_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42842834UL))
+#define bFM3_USB0_EP0IS_DRQI                   *((volatile unsigned int*)(0x428428A8UL))
+#define bFM3_USB0_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x428428B8UL))
+#define bFM3_USB0_EP0IS_BFINI                  *((volatile unsigned int*)(0x428428BCUL))
+#define bFM3_USB0_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42842900UL))
+#define bFM3_USB0_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42842904UL))
+#define bFM3_USB0_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42842908UL))
+#define bFM3_USB0_EP0OS_SIZE3                  *((volatile unsigned int*)(0x4284290CUL))
+#define bFM3_USB0_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42842910UL))
+#define bFM3_USB0_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42842914UL))
+#define bFM3_USB0_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42842918UL))
+#define bFM3_USB0_EP0OS_SPK                    *((volatile unsigned int*)(0x42842924UL))
+#define bFM3_USB0_EP0OS_DRQO                   *((volatile unsigned int*)(0x42842928UL))
+#define bFM3_USB0_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42842934UL))
+#define bFM3_USB0_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42842938UL))
+#define bFM3_USB0_EP0OS_BFINI                  *((volatile unsigned int*)(0x4284293CUL))
+#define bFM3_USB0_EP1S_SIZE10                  *((volatile unsigned int*)(0x42842980UL))
+#define bFM3_USB0_EP1S_SIZE11                  *((volatile unsigned int*)(0x42842984UL))
+#define bFM3_USB0_EP1S_SIZE12                  *((volatile unsigned int*)(0x42842988UL))
+#define bFM3_USB0_EP1S_SIZE13                  *((volatile unsigned int*)(0x4284298CUL))
+#define bFM3_USB0_EP1S_SIZE14                  *((volatile unsigned int*)(0x42842990UL))
+#define bFM3_USB0_EP1S_SIZE15                  *((volatile unsigned int*)(0x42842994UL))
+#define bFM3_USB0_EP1S_SIZE16                  *((volatile unsigned int*)(0x42842998UL))
+#define bFM3_USB0_EP1S_SIZE17                  *((volatile unsigned int*)(0x4284299CUL))
+#define bFM3_USB0_EP1S_SIZE18                  *((volatile unsigned int*)(0x428429A0UL))
+#define bFM3_USB0_EP1S_SPK                     *((volatile unsigned int*)(0x428429A4UL))
+#define bFM3_USB0_EP1S_DRQ                     *((volatile unsigned int*)(0x428429A8UL))
+#define bFM3_USB0_EP1S_BUSY                    *((volatile unsigned int*)(0x428429ACUL))
+#define bFM3_USB0_EP1S_SPKIE                   *((volatile unsigned int*)(0x428429B4UL))
+#define bFM3_USB0_EP1S_DRQIE                   *((volatile unsigned int*)(0x428429B8UL))
+#define bFM3_USB0_EP1S_BFINI                   *((volatile unsigned int*)(0x428429BCUL))
+#define bFM3_USB0_EP2S_SIZE20                  *((volatile unsigned int*)(0x42842A00UL))
+#define bFM3_USB0_EP2S_SIZE21                  *((volatile unsigned int*)(0x42842A04UL))
+#define bFM3_USB0_EP2S_SIZE22                  *((volatile unsigned int*)(0x42842A08UL))
+#define bFM3_USB0_EP2S_SIZE23                  *((volatile unsigned int*)(0x42842A0CUL))
+#define bFM3_USB0_EP2S_SIZE24                  *((volatile unsigned int*)(0x42842A10UL))
+#define bFM3_USB0_EP2S_SIZE25                  *((volatile unsigned int*)(0x42842A14UL))
+#define bFM3_USB0_EP2S_SIZE26                  *((volatile unsigned int*)(0x42842A18UL))
+#define bFM3_USB0_EP2S_SPK                     *((volatile unsigned int*)(0x42842A24UL))
+#define bFM3_USB0_EP2S_DRQ                     *((volatile unsigned int*)(0x42842A28UL))
+#define bFM3_USB0_EP2S_BUSY                    *((volatile unsigned int*)(0x42842A2CUL))
+#define bFM3_USB0_EP2S_SPKIE                   *((volatile unsigned int*)(0x42842A34UL))
+#define bFM3_USB0_EP2S_DRQIE                   *((volatile unsigned int*)(0x42842A38UL))
+#define bFM3_USB0_EP2S_BFINI                   *((volatile unsigned int*)(0x42842A3CUL))
+#define bFM3_USB0_EP3S_SIZE30                  *((volatile unsigned int*)(0x42842A80UL))
+#define bFM3_USB0_EP3S_SIZE31                  *((volatile unsigned int*)(0x42842A84UL))
+#define bFM3_USB0_EP3S_SIZE32                  *((volatile unsigned int*)(0x42842A88UL))
+#define bFM3_USB0_EP3S_SIZE33                  *((volatile unsigned int*)(0x42842A8CUL))
+#define bFM3_USB0_EP3S_SIZE34                  *((volatile unsigned int*)(0x42842A90UL))
+#define bFM3_USB0_EP3S_SIZE35                  *((volatile unsigned int*)(0x42842A94UL))
+#define bFM3_USB0_EP3S_SIZE36                  *((volatile unsigned int*)(0x42842A98UL))
+#define bFM3_USB0_EP3S_SPK                     *((volatile unsigned int*)(0x42842AA4UL))
+#define bFM3_USB0_EP3S_DRQ                     *((volatile unsigned int*)(0x42842AA8UL))
+#define bFM3_USB0_EP3S_BUSY                    *((volatile unsigned int*)(0x42842AACUL))
+#define bFM3_USB0_EP3S_SPKIE                   *((volatile unsigned int*)(0x42842AB4UL))
+#define bFM3_USB0_EP3S_DRQIE                   *((volatile unsigned int*)(0x42842AB8UL))
+#define bFM3_USB0_EP3S_BFINI                   *((volatile unsigned int*)(0x42842ABCUL))
+#define bFM3_USB0_EP4S_SIZE40                  *((volatile unsigned int*)(0x42842B00UL))
+#define bFM3_USB0_EP4S_SIZE41                  *((volatile unsigned int*)(0x42842B04UL))
+#define bFM3_USB0_EP4S_SIZE42                  *((volatile unsigned int*)(0x42842B08UL))
+#define bFM3_USB0_EP4S_SIZE43                  *((volatile unsigned int*)(0x42842B0CUL))
+#define bFM3_USB0_EP4S_SIZE44                  *((volatile unsigned int*)(0x42842B10UL))
+#define bFM3_USB0_EP4S_SIZE45                  *((volatile unsigned int*)(0x42842B14UL))
+#define bFM3_USB0_EP4S_SIZE46                  *((volatile unsigned int*)(0x42842B18UL))
+#define bFM3_USB0_EP4S_SPK                     *((volatile unsigned int*)(0x42842B24UL))
+#define bFM3_USB0_EP4S_DRQ                     *((volatile unsigned int*)(0x42842B28UL))
+#define bFM3_USB0_EP4S_BUSY                    *((volatile unsigned int*)(0x42842B2CUL))
+#define bFM3_USB0_EP4S_SPKIE                   *((volatile unsigned int*)(0x42842B34UL))
+#define bFM3_USB0_EP4S_DRQIE                   *((volatile unsigned int*)(0x42842B38UL))
+#define bFM3_USB0_EP4S_BFINI                   *((volatile unsigned int*)(0x42842B3CUL))
+#define bFM3_USB0_EP5S_SIZE50                  *((volatile unsigned int*)(0x42842B80UL))
+#define bFM3_USB0_EP5S_SIZE51                  *((volatile unsigned int*)(0x42842B84UL))
+#define bFM3_USB0_EP5S_SIZE52                  *((volatile unsigned int*)(0x42842B88UL))
+#define bFM3_USB0_EP5S_SIZE53                  *((volatile unsigned int*)(0x42842B8CUL))
+#define bFM3_USB0_EP5S_SIZE54                  *((volatile unsigned int*)(0x42842B90UL))
+#define bFM3_USB0_EP5S_SIZE55                  *((volatile unsigned int*)(0x42842B94UL))
+#define bFM3_USB0_EP5S_SIZE56                  *((volatile unsigned int*)(0x42842B98UL))
+#define bFM3_USB0_EP5S_SPK                     *((volatile unsigned int*)(0x42842BA4UL))
+#define bFM3_USB0_EP5S_DRQ                     *((volatile unsigned int*)(0x42842BA8UL))
+#define bFM3_USB0_EP5S_BUSY                    *((volatile unsigned int*)(0x42842BACUL))
+#define bFM3_USB0_EP5S_SPKIE                   *((volatile unsigned int*)(0x42842BB4UL))
+#define bFM3_USB0_EP5S_DRQIE                   *((volatile unsigned int*)(0x42842BB8UL))
+#define bFM3_USB0_EP5S_BFINI                   *((volatile unsigned int*)(0x42842BBCUL))
+
+/* USB channel 1 registers */
+#define bFM3_USB1_HCNT_HOST                    *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT_URST                    *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT_DIRE                    *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT_URIRE                   *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT_RWKIRE                  *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT_RETRY                   *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT_CANCEL                  *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HCNT0_HOST                   *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT0_URST                   *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT0_DIRE                   *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT0_URIRE                  *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT1_RETRY                  *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42A42080UL))
+#define bFM3_USB1_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42A42084UL))
+#define bFM3_USB1_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42A42088UL))
+#define bFM3_USB1_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x42A4208CUL))
+#define bFM3_USB1_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42A42090UL))
+#define bFM3_USB1_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42A42094UL))
+#define bFM3_USB1_HIRQ_TCAN                    *((volatile unsigned int*)(0x42A4209CUL))
+#define bFM3_USB1_HERR_HS0                     *((volatile unsigned int*)(0x42A420A0UL))
+#define bFM3_USB1_HERR_HS1                     *((volatile unsigned int*)(0x42A420A4UL))
+#define bFM3_USB1_HERR_STUFF                   *((volatile unsigned int*)(0x42A420A8UL))
+#define bFM3_USB1_HERR_TGERR                   *((volatile unsigned int*)(0x42A420ACUL))
+#define bFM3_USB1_HERR_CRC                     *((volatile unsigned int*)(0x42A420B0UL))
+#define bFM3_USB1_HERR_TOUT                    *((volatile unsigned int*)(0x42A420B4UL))
+#define bFM3_USB1_HERR_RERR                    *((volatile unsigned int*)(0x42A420B8UL))
+#define bFM3_USB1_HERR_LSTOF                   *((volatile unsigned int*)(0x42A420BCUL))
+#define bFM3_USB1_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42A42100UL))
+#define bFM3_USB1_HSTATE_TMODE                 *((volatile unsigned int*)(0x42A42104UL))
+#define bFM3_USB1_HSTATE_SUSP                  *((volatile unsigned int*)(0x42A42108UL))
+#define bFM3_USB1_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x42A4210CUL))
+#define bFM3_USB1_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42A42110UL))
+#define bFM3_USB1_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42A42114UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42A42120UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42A42124UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42A42128UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x42A4212CUL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42A42130UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42A42134UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42A42138UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x42A4213CUL))
+#define bFM3_USB1_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42A42200UL))
+#define bFM3_USB1_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42A42204UL))
+#define bFM3_USB1_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42A42208UL))
+#define bFM3_USB1_HADR_ADDRESS0                *((volatile unsigned int*)(0x42A42220UL))
+#define bFM3_USB1_HADR_ADDRESS1                *((volatile unsigned int*)(0x42A42224UL))
+#define bFM3_USB1_HADR_ADDRESS2                *((volatile unsigned int*)(0x42A42228UL))
+#define bFM3_USB1_HADR_ADDRESS3                *((volatile unsigned int*)(0x42A4222CUL))
+#define bFM3_USB1_HADR_ADDRESS4                *((volatile unsigned int*)(0x42A42230UL))
+#define bFM3_USB1_HADR_ADDRESS5                *((volatile unsigned int*)(0x42A42234UL))
+#define bFM3_USB1_HADR_ADDRESS6                *((volatile unsigned int*)(0x42A42238UL))
+#define bFM3_USB1_HEOF_EOF0                    *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF_EOF1                    *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF_EOF2                    *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF_EOF3                    *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF_EOF4                    *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF_EOF5                    *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF_EOF6                    *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF_EOF7                    *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF_EOF8                    *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF_EOF9                    *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF_EOF10                   *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF_EOF11                   *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF_EOF12                   *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF_EOF13                   *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HEOF_EOF14                   *((volatile unsigned int*)(0x42A422B8UL))
+#define bFM3_USB1_HEOF_EOF15                   *((volatile unsigned int*)(0x42A422BCUL))
+#define bFM3_USB1_HEOF0_EOF00                  *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF0_EOF01                  *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF0_EOF02                  *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF0_EOF03                  *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF0_EOF04                  *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF0_EOF05                  *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF0_EOF06                  *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF0_EOF07                  *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF1_EOF10                  *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF1_EOF11                  *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF1_EOF12                  *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF1_EOF13                  *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF1_EOF14                  *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF1_EOF15                  *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HFRAME_FRAME0                *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME_FRAME1                *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME_FRAME2                *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME_FRAME3                *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME_FRAME4                *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME_FRAME5                *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME_FRAME6                *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME_FRAME7                *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME_FRAME8                *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME_FRAME9                *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME_FRAME10               *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME0_FRAME03              *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME0_FRAME07              *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME1_FRAME13              *((volatile unsigned int*)(0x42A4232CUL))
+#define bFM3_USB1_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42A42380UL))
+#define bFM3_USB1_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42A42384UL))
+#define bFM3_USB1_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42A42388UL))
+#define bFM3_USB1_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x42A4238CUL))
+#define bFM3_USB1_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42A42390UL))
+#define bFM3_USB1_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42A42394UL))
+#define bFM3_USB1_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42A42398UL))
+#define bFM3_USB1_HTOKEN_TGGL                  *((volatile unsigned int*)(0x42A4239CUL))
+#define bFM3_USB1_UDCC_PWC                     *((volatile unsigned int*)(0x42A42400UL))
+#define bFM3_USB1_UDCC_RFBK                    *((volatile unsigned int*)(0x42A42404UL))
+#define bFM3_USB1_UDCC_STALCLREN               *((volatile unsigned int*)(0x42A4240CUL))
+#define bFM3_USB1_UDCC_USTP                    *((volatile unsigned int*)(0x42A42410UL))
+#define bFM3_USB1_UDCC_HCONX                   *((volatile unsigned int*)(0x42A42414UL))
+#define bFM3_USB1_UDCC_RESUM                   *((volatile unsigned int*)(0x42A42418UL))
+#define bFM3_USB1_UDCC_RST                     *((volatile unsigned int*)(0x42A4241CUL))
+#define bFM3_USB1_EP0C_PKS00                   *((volatile unsigned int*)(0x42A42480UL))
+#define bFM3_USB1_EP0C_PKS01                   *((volatile unsigned int*)(0x42A42484UL))
+#define bFM3_USB1_EP0C_PKS02                   *((volatile unsigned int*)(0x42A42488UL))
+#define bFM3_USB1_EP0C_PKS03                   *((volatile unsigned int*)(0x42A4248CUL))
+#define bFM3_USB1_EP0C_PKS04                   *((volatile unsigned int*)(0x42A42490UL))
+#define bFM3_USB1_EP0C_PKS05                   *((volatile unsigned int*)(0x42A42494UL))
+#define bFM3_USB1_EP0C_PKS06                   *((volatile unsigned int*)(0x42A42498UL))
+#define bFM3_USB1_EP0C_STAL                    *((volatile unsigned int*)(0x42A424A4UL))
+#define bFM3_USB1_EP1C_PKS10                   *((volatile unsigned int*)(0x42A42500UL))
+#define bFM3_USB1_EP1C_PKS11                   *((volatile unsigned int*)(0x42A42504UL))
+#define bFM3_USB1_EP1C_PKS12                   *((volatile unsigned int*)(0x42A42508UL))
+#define bFM3_USB1_EP1C_PKS13                   *((volatile unsigned int*)(0x42A4250CUL))
+#define bFM3_USB1_EP1C_PKS14                   *((volatile unsigned int*)(0x42A42510UL))
+#define bFM3_USB1_EP1C_PKS15                   *((volatile unsigned int*)(0x42A42514UL))
+#define bFM3_USB1_EP1C_PKS16                   *((volatile unsigned int*)(0x42A42518UL))
+#define bFM3_USB1_EP1C_PKS17                   *((volatile unsigned int*)(0x42A4251CUL))
+#define bFM3_USB1_EP1C_PKS18                   *((volatile unsigned int*)(0x42A42520UL))
+#define bFM3_USB1_EP1C_STAL                    *((volatile unsigned int*)(0x42A42524UL))
+#define bFM3_USB1_EP1C_NULE                    *((volatile unsigned int*)(0x42A42528UL))
+#define bFM3_USB1_EP1C_DMAE                    *((volatile unsigned int*)(0x42A4252CUL))
+#define bFM3_USB1_EP1C_DIR                     *((volatile unsigned int*)(0x42A42530UL))
+#define bFM3_USB1_EP1C_TYPE0                   *((volatile unsigned int*)(0x42A42534UL))
+#define bFM3_USB1_EP1C_TYPE1                   *((volatile unsigned int*)(0x42A42538UL))
+#define bFM3_USB1_EP1C_EPEN                    *((volatile unsigned int*)(0x42A4253CUL))
+#define bFM3_USB1_EP2C_PKS20                   *((volatile unsigned int*)(0x42A42580UL))
+#define bFM3_USB1_EP2C_PKS21                   *((volatile unsigned int*)(0x42A42584UL))
+#define bFM3_USB1_EP2C_PKS22                   *((volatile unsigned int*)(0x42A42588UL))
+#define bFM3_USB1_EP2C_PKS23                   *((volatile unsigned int*)(0x42A4258CUL))
+#define bFM3_USB1_EP2C_PKS24                   *((volatile unsigned int*)(0x42A42590UL))
+#define bFM3_USB1_EP2C_PKS25                   *((volatile unsigned int*)(0x42A42594UL))
+#define bFM3_USB1_EP2C_PKS26                   *((volatile unsigned int*)(0x42A42598UL))
+#define bFM3_USB1_EP2C_STAL                    *((volatile unsigned int*)(0x42A425A4UL))
+#define bFM3_USB1_EP2C_NULE                    *((volatile unsigned int*)(0x42A425A8UL))
+#define bFM3_USB1_EP2C_DMAE                    *((volatile unsigned int*)(0x42A425ACUL))
+#define bFM3_USB1_EP2C_DIR                     *((volatile unsigned int*)(0x42A425B0UL))
+#define bFM3_USB1_EP2C_TYPE0                   *((volatile unsigned int*)(0x42A425B4UL))
+#define bFM3_USB1_EP2C_TYPE1                   *((volatile unsigned int*)(0x42A425B8UL))
+#define bFM3_USB1_EP2C_EPEN                    *((volatile unsigned int*)(0x42A425BCUL))
+#define bFM3_USB1_EP3C_PKS30                   *((volatile unsigned int*)(0x42A42600UL))
+#define bFM3_USB1_EP3C_PKS31                   *((volatile unsigned int*)(0x42A42604UL))
+#define bFM3_USB1_EP3C_PKS32                   *((volatile unsigned int*)(0x42A42608UL))
+#define bFM3_USB1_EP3C_PKS33                   *((volatile unsigned int*)(0x42A4260CUL))
+#define bFM3_USB1_EP3C_PKS34                   *((volatile unsigned int*)(0x42A42610UL))
+#define bFM3_USB1_EP3C_PKS35                   *((volatile unsigned int*)(0x42A42614UL))
+#define bFM3_USB1_EP3C_PKS36                   *((volatile unsigned int*)(0x42A42618UL))
+#define bFM3_USB1_EP3C_STAL                    *((volatile unsigned int*)(0x42A42624UL))
+#define bFM3_USB1_EP3C_NULE                    *((volatile unsigned int*)(0x42A42628UL))
+#define bFM3_USB1_EP3C_DMAE                    *((volatile unsigned int*)(0x42A4262CUL))
+#define bFM3_USB1_EP3C_DIR                     *((volatile unsigned int*)(0x42A42630UL))
+#define bFM3_USB1_EP3C_TYPE0                   *((volatile unsigned int*)(0x42A42634UL))
+#define bFM3_USB1_EP3C_TYPE1                   *((volatile unsigned int*)(0x42A42638UL))
+#define bFM3_USB1_EP3C_EPEN                    *((volatile unsigned int*)(0x42A4263CUL))
+#define bFM3_USB1_EP4C_PKS40                   *((volatile unsigned int*)(0x42A42680UL))
+#define bFM3_USB1_EP4C_PKS41                   *((volatile unsigned int*)(0x42A42684UL))
+#define bFM3_USB1_EP4C_PKS42                   *((volatile unsigned int*)(0x42A42688UL))
+#define bFM3_USB1_EP4C_PKS43                   *((volatile unsigned int*)(0x42A4268CUL))
+#define bFM3_USB1_EP4C_PKS44                   *((volatile unsigned int*)(0x42A42690UL))
+#define bFM3_USB1_EP4C_PKS45                   *((volatile unsigned int*)(0x42A42694UL))
+#define bFM3_USB1_EP4C_PKS46                   *((volatile unsigned int*)(0x42A42698UL))
+#define bFM3_USB1_EP4C_STAL                    *((volatile unsigned int*)(0x42A426A4UL))
+#define bFM3_USB1_EP4C_NULE                    *((volatile unsigned int*)(0x42A426A8UL))
+#define bFM3_USB1_EP4C_DMAE                    *((volatile unsigned int*)(0x42A426ACUL))
+#define bFM3_USB1_EP4C_DIR                     *((volatile unsigned int*)(0x42A426B0UL))
+#define bFM3_USB1_EP4C_TYPE0                   *((volatile unsigned int*)(0x42A426B4UL))
+#define bFM3_USB1_EP4C_TYPE1                   *((volatile unsigned int*)(0x42A426B8UL))
+#define bFM3_USB1_EP4C_EPEN                    *((volatile unsigned int*)(0x42A426BCUL))
+#define bFM3_USB1_EP5C_PKS50                   *((volatile unsigned int*)(0x42A42700UL))
+#define bFM3_USB1_EP5C_PKS51                   *((volatile unsigned int*)(0x42A42704UL))
+#define bFM3_USB1_EP5C_PKS52                   *((volatile unsigned int*)(0x42A42708UL))
+#define bFM3_USB1_EP5C_PKS53                   *((volatile unsigned int*)(0x42A4270CUL))
+#define bFM3_USB1_EP5C_PKS54                   *((volatile unsigned int*)(0x42A42710UL))
+#define bFM3_USB1_EP5C_PKS55                   *((volatile unsigned int*)(0x42A42714UL))
+#define bFM3_USB1_EP5C_PKS56                   *((volatile unsigned int*)(0x42A42718UL))
+#define bFM3_USB1_EP5C_STAL                    *((volatile unsigned int*)(0x42A42724UL))
+#define bFM3_USB1_EP5C_NULE                    *((volatile unsigned int*)(0x42A42728UL))
+#define bFM3_USB1_EP5C_DMAE                    *((volatile unsigned int*)(0x42A4272CUL))
+#define bFM3_USB1_EP5C_DIR                     *((volatile unsigned int*)(0x42A42730UL))
+#define bFM3_USB1_EP5C_TYPE0                   *((volatile unsigned int*)(0x42A42734UL))
+#define bFM3_USB1_EP5C_TYPE1                   *((volatile unsigned int*)(0x42A42738UL))
+#define bFM3_USB1_EP5C_EPEN                    *((volatile unsigned int*)(0x42A4273CUL))
+#define bFM3_USB1_TMSP_TMSP0                   *((volatile unsigned int*)(0x42A42780UL))
+#define bFM3_USB1_TMSP_TMSP1                   *((volatile unsigned int*)(0x42A42784UL))
+#define bFM3_USB1_TMSP_TMSP2                   *((volatile unsigned int*)(0x42A42788UL))
+#define bFM3_USB1_TMSP_TMSP3                   *((volatile unsigned int*)(0x42A4278CUL))
+#define bFM3_USB1_TMSP_TMSP4                   *((volatile unsigned int*)(0x42A42790UL))
+#define bFM3_USB1_TMSP_TMSP5                   *((volatile unsigned int*)(0x42A42794UL))
+#define bFM3_USB1_TMSP_TMSP6                   *((volatile unsigned int*)(0x42A42798UL))
+#define bFM3_USB1_TMSP_TMSP7                   *((volatile unsigned int*)(0x42A4279CUL))
+#define bFM3_USB1_TMSP_TMSP8                   *((volatile unsigned int*)(0x42A427A0UL))
+#define bFM3_USB1_TMSP_TMSP9                   *((volatile unsigned int*)(0x42A427A4UL))
+#define bFM3_USB1_TMSP_TMSP10                  *((volatile unsigned int*)(0x42A427A8UL))
+#define bFM3_USB1_UDCS_CONF                    *((volatile unsigned int*)(0x42A42800UL))
+#define bFM3_USB1_UDCS_SETP                    *((volatile unsigned int*)(0x42A42804UL))
+#define bFM3_USB1_UDCS_WKUP                    *((volatile unsigned int*)(0x42A42808UL))
+#define bFM3_USB1_UDCS_BRST                    *((volatile unsigned int*)(0x42A4280CUL))
+#define bFM3_USB1_UDCS_SOF                     *((volatile unsigned int*)(0x42A42810UL))
+#define bFM3_USB1_UDCS_SUSP                    *((volatile unsigned int*)(0x42A42814UL))
+#define bFM3_USB1_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42A42820UL))
+#define bFM3_USB1_UDCIE_CONFN                  *((volatile unsigned int*)(0x42A42824UL))
+#define bFM3_USB1_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42A42828UL))
+#define bFM3_USB1_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x42A4282CUL))
+#define bFM3_USB1_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42A42830UL))
+#define bFM3_USB1_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42A42834UL))
+#define bFM3_USB1_EP0IS_DRQI                   *((volatile unsigned int*)(0x42A428A8UL))
+#define bFM3_USB1_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x42A428B8UL))
+#define bFM3_USB1_EP0IS_BFINI                  *((volatile unsigned int*)(0x42A428BCUL))
+#define bFM3_USB1_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42A42900UL))
+#define bFM3_USB1_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42A42904UL))
+#define bFM3_USB1_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42A42908UL))
+#define bFM3_USB1_EP0OS_SIZE3                  *((volatile unsigned int*)(0x42A4290CUL))
+#define bFM3_USB1_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42A42910UL))
+#define bFM3_USB1_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42A42914UL))
+#define bFM3_USB1_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42A42918UL))
+#define bFM3_USB1_EP0OS_SPK                    *((volatile unsigned int*)(0x42A42924UL))
+#define bFM3_USB1_EP0OS_DRQO                   *((volatile unsigned int*)(0x42A42928UL))
+#define bFM3_USB1_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42A42934UL))
+#define bFM3_USB1_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42A42938UL))
+#define bFM3_USB1_EP0OS_BFINI                  *((volatile unsigned int*)(0x42A4293CUL))
+#define bFM3_USB1_EP1S_SIZE10                  *((volatile unsigned int*)(0x42A42980UL))
+#define bFM3_USB1_EP1S_SIZE11                  *((volatile unsigned int*)(0x42A42984UL))
+#define bFM3_USB1_EP1S_SIZE12                  *((volatile unsigned int*)(0x42A42988UL))
+#define bFM3_USB1_EP1S_SIZE13                  *((volatile unsigned int*)(0x42A4298CUL))
+#define bFM3_USB1_EP1S_SIZE14                  *((volatile unsigned int*)(0x42A42990UL))
+#define bFM3_USB1_EP1S_SIZE15                  *((volatile unsigned int*)(0x42A42994UL))
+#define bFM3_USB1_EP1S_SIZE16                  *((volatile unsigned int*)(0x42A42998UL))
+#define bFM3_USB1_EP1S_SIZE17                  *((volatile unsigned int*)(0x42A4299CUL))
+#define bFM3_USB1_EP1S_SIZE18                  *((volatile unsigned int*)(0x42A429A0UL))
+#define bFM3_USB1_EP1S_SPK                     *((volatile unsigned int*)(0x42A429A4UL))
+#define bFM3_USB1_EP1S_DRQ                     *((volatile unsigned int*)(0x42A429A8UL))
+#define bFM3_USB1_EP1S_BUSY                    *((volatile unsigned int*)(0x42A429ACUL))
+#define bFM3_USB1_EP1S_SPKIE                   *((volatile unsigned int*)(0x42A429B4UL))
+#define bFM3_USB1_EP1S_DRQIE                   *((volatile unsigned int*)(0x42A429B8UL))
+#define bFM3_USB1_EP1S_BFINI                   *((volatile unsigned int*)(0x42A429BCUL))
+#define bFM3_USB1_EP2S_SIZE20                  *((volatile unsigned int*)(0x42A42A00UL))
+#define bFM3_USB1_EP2S_SIZE21                  *((volatile unsigned int*)(0x42A42A04UL))
+#define bFM3_USB1_EP2S_SIZE22                  *((volatile unsigned int*)(0x42A42A08UL))
+#define bFM3_USB1_EP2S_SIZE23                  *((volatile unsigned int*)(0x42A42A0CUL))
+#define bFM3_USB1_EP2S_SIZE24                  *((volatile unsigned int*)(0x42A42A10UL))
+#define bFM3_USB1_EP2S_SIZE25                  *((volatile unsigned int*)(0x42A42A14UL))
+#define bFM3_USB1_EP2S_SIZE26                  *((volatile unsigned int*)(0x42A42A18UL))
+#define bFM3_USB1_EP2S_SPK                     *((volatile unsigned int*)(0x42A42A24UL))
+#define bFM3_USB1_EP2S_DRQ                     *((volatile unsigned int*)(0x42A42A28UL))
+#define bFM3_USB1_EP2S_BUSY                    *((volatile unsigned int*)(0x42A42A2CUL))
+#define bFM3_USB1_EP2S_SPKIE                   *((volatile unsigned int*)(0x42A42A34UL))
+#define bFM3_USB1_EP2S_DRQIE                   *((volatile unsigned int*)(0x42A42A38UL))
+#define bFM3_USB1_EP2S_BFINI                   *((volatile unsigned int*)(0x42A42A3CUL))
+#define bFM3_USB1_EP3S_SIZE30                  *((volatile unsigned int*)(0x42A42A80UL))
+#define bFM3_USB1_EP3S_SIZE31                  *((volatile unsigned int*)(0x42A42A84UL))
+#define bFM3_USB1_EP3S_SIZE32                  *((volatile unsigned int*)(0x42A42A88UL))
+#define bFM3_USB1_EP3S_SIZE33                  *((volatile unsigned int*)(0x42A42A8CUL))
+#define bFM3_USB1_EP3S_SIZE34                  *((volatile unsigned int*)(0x42A42A90UL))
+#define bFM3_USB1_EP3S_SIZE35                  *((volatile unsigned int*)(0x42A42A94UL))
+#define bFM3_USB1_EP3S_SIZE36                  *((volatile unsigned int*)(0x42A42A98UL))
+#define bFM3_USB1_EP3S_SPK                     *((volatile unsigned int*)(0x42A42AA4UL))
+#define bFM3_USB1_EP3S_DRQ                     *((volatile unsigned int*)(0x42A42AA8UL))
+#define bFM3_USB1_EP3S_BUSY                    *((volatile unsigned int*)(0x42A42AACUL))
+#define bFM3_USB1_EP3S_SPKIE                   *((volatile unsigned int*)(0x42A42AB4UL))
+#define bFM3_USB1_EP3S_DRQIE                   *((volatile unsigned int*)(0x42A42AB8UL))
+#define bFM3_USB1_EP3S_BFINI                   *((volatile unsigned int*)(0x42A42ABCUL))
+#define bFM3_USB1_EP4S_SIZE40                  *((volatile unsigned int*)(0x42A42B00UL))
+#define bFM3_USB1_EP4S_SIZE41                  *((volatile unsigned int*)(0x42A42B04UL))
+#define bFM3_USB1_EP4S_SIZE42                  *((volatile unsigned int*)(0x42A42B08UL))
+#define bFM3_USB1_EP4S_SIZE43                  *((volatile unsigned int*)(0x42A42B0CUL))
+#define bFM3_USB1_EP4S_SIZE44                  *((volatile unsigned int*)(0x42A42B10UL))
+#define bFM3_USB1_EP4S_SIZE45                  *((volatile unsigned int*)(0x42A42B14UL))
+#define bFM3_USB1_EP4S_SIZE46                  *((volatile unsigned int*)(0x42A42B18UL))
+#define bFM3_USB1_EP4S_SPK                     *((volatile unsigned int*)(0x42A42B24UL))
+#define bFM3_USB1_EP4S_DRQ                     *((volatile unsigned int*)(0x42A42B28UL))
+#define bFM3_USB1_EP4S_BUSY                    *((volatile unsigned int*)(0x42A42B2CUL))
+#define bFM3_USB1_EP4S_SPKIE                   *((volatile unsigned int*)(0x42A42B34UL))
+#define bFM3_USB1_EP4S_DRQIE                   *((volatile unsigned int*)(0x42A42B38UL))
+#define bFM3_USB1_EP4S_BFINI                   *((volatile unsigned int*)(0x42A42B3CUL))
+#define bFM3_USB1_EP5S_SIZE50                  *((volatile unsigned int*)(0x42A42B80UL))
+#define bFM3_USB1_EP5S_SIZE51                  *((volatile unsigned int*)(0x42A42B84UL))
+#define bFM3_USB1_EP5S_SIZE52                  *((volatile unsigned int*)(0x42A42B88UL))
+#define bFM3_USB1_EP5S_SIZE53                  *((volatile unsigned int*)(0x42A42B8CUL))
+#define bFM3_USB1_EP5S_SIZE54                  *((volatile unsigned int*)(0x42A42B90UL))
+#define bFM3_USB1_EP5S_SIZE55                  *((volatile unsigned int*)(0x42A42B94UL))
+#define bFM3_USB1_EP5S_SIZE56                  *((volatile unsigned int*)(0x42A42B98UL))
+#define bFM3_USB1_EP5S_SPK                     *((volatile unsigned int*)(0x42A42BA4UL))
+#define bFM3_USB1_EP5S_DRQ                     *((volatile unsigned int*)(0x42A42BA8UL))
+#define bFM3_USB1_EP5S_BUSY                    *((volatile unsigned int*)(0x42A42BACUL))
+#define bFM3_USB1_EP5S_SPKIE                   *((volatile unsigned int*)(0x42A42BB4UL))
+#define bFM3_USB1_EP5S_DRQIE                   *((volatile unsigned int*)(0x42A42BB8UL))
+#define bFM3_USB1_EP5S_BFINI                   *((volatile unsigned int*)(0x42A42BBCUL))
+
+/* DMA controller */
+#define bFM3_DMAC_DMACR_DH0                    *((volatile unsigned int*)(0x42C00060UL))
+#define bFM3_DMAC_DMACR_DH1                    *((volatile unsigned int*)(0x42C00064UL))
+#define bFM3_DMAC_DMACR_DH2                    *((volatile unsigned int*)(0x42C00068UL))
+#define bFM3_DMAC_DMACR_DH3                    *((volatile unsigned int*)(0x42C0006CUL))
+#define bFM3_DMAC_DMACR_PR                     *((volatile unsigned int*)(0x42C00070UL))
+#define bFM3_DMAC_DMACR_DS                     *((volatile unsigned int*)(0x42C00078UL))
+#define bFM3_DMAC_DMACR_DE                     *((volatile unsigned int*)(0x42C0007CUL))
+#define bFM3_DMAC_DMACA0_TC0                   *((volatile unsigned int*)(0x42C00200UL))
+#define bFM3_DMAC_DMACA0_TC1                   *((volatile unsigned int*)(0x42C00204UL))
+#define bFM3_DMAC_DMACA0_TC2                   *((volatile unsigned int*)(0x42C00208UL))
+#define bFM3_DMAC_DMACA0_TC3                   *((volatile unsigned int*)(0x42C0020CUL))
+#define bFM3_DMAC_DMACA0_TC4                   *((volatile unsigned int*)(0x42C00210UL))
+#define bFM3_DMAC_DMACA0_TC5                   *((volatile unsigned int*)(0x42C00214UL))
+#define bFM3_DMAC_DMACA0_TC6                   *((volatile unsigned int*)(0x42C00218UL))
+#define bFM3_DMAC_DMACA0_TC7                   *((volatile unsigned int*)(0x42C0021CUL))
+#define bFM3_DMAC_DMACA0_TC8                   *((volatile unsigned int*)(0x42C00220UL))
+#define bFM3_DMAC_DMACA0_TC9                   *((volatile unsigned int*)(0x42C00224UL))
+#define bFM3_DMAC_DMACA0_TC10                  *((volatile unsigned int*)(0x42C00228UL))
+#define bFM3_DMAC_DMACA0_TC11                  *((volatile unsigned int*)(0x42C0022CUL))
+#define bFM3_DMAC_DMACA0_TC12                  *((volatile unsigned int*)(0x42C00230UL))
+#define bFM3_DMAC_DMACA0_TC13                  *((volatile unsigned int*)(0x42C00234UL))
+#define bFM3_DMAC_DMACA0_TC14                  *((volatile unsigned int*)(0x42C00238UL))
+#define bFM3_DMAC_DMACA0_TC15                  *((volatile unsigned int*)(0x42C0023CUL))
+#define bFM3_DMAC_DMACA0_BC0                   *((volatile unsigned int*)(0x42C00240UL))
+#define bFM3_DMAC_DMACA0_BC1                   *((volatile unsigned int*)(0x42C00244UL))
+#define bFM3_DMAC_DMACA0_BC2                   *((volatile unsigned int*)(0x42C00248UL))
+#define bFM3_DMAC_DMACA0_BC3                   *((volatile unsigned int*)(0x42C0024CUL))
+#define bFM3_DMAC_DMACA0_IS0                   *((volatile unsigned int*)(0x42C0025CUL))
+#define bFM3_DMAC_DMACA0_IS1                   *((volatile unsigned int*)(0x42C00260UL))
+#define bFM3_DMAC_DMACA0_IS2                   *((volatile unsigned int*)(0x42C00264UL))
+#define bFM3_DMAC_DMACA0_IS3                   *((volatile unsigned int*)(0x42C00268UL))
+#define bFM3_DMAC_DMACA0_IS4                   *((volatile unsigned int*)(0x42C0026CUL))
+#define bFM3_DMAC_DMACA0_IS5                   *((volatile unsigned int*)(0x42C00270UL))
+#define bFM3_DMAC_DMACA0_ST                    *((volatile unsigned int*)(0x42C00274UL))
+#define bFM3_DMAC_DMACA0_PB                    *((volatile unsigned int*)(0x42C00278UL))
+#define bFM3_DMAC_DMACA0_EB                    *((volatile unsigned int*)(0x42C0027CUL))
+#define bFM3_DMAC_DMACB0_EM                    *((volatile unsigned int*)(0x42C00280UL))
+#define bFM3_DMAC_DMACB0_SS0                   *((volatile unsigned int*)(0x42C002C0UL))
+#define bFM3_DMAC_DMACB0_SS1                   *((volatile unsigned int*)(0x42C002C4UL))
+#define bFM3_DMAC_DMACB0_SS2                   *((volatile unsigned int*)(0x42C002C8UL))
+#define bFM3_DMAC_DMACB0_CI                    *((volatile unsigned int*)(0x42C002CCUL))
+#define bFM3_DMAC_DMACB0_EI                    *((volatile unsigned int*)(0x42C002D0UL))
+#define bFM3_DMAC_DMACB0_RD                    *((volatile unsigned int*)(0x42C002D4UL))
+#define bFM3_DMAC_DMACB0_RS                    *((volatile unsigned int*)(0x42C002D8UL))
+#define bFM3_DMAC_DMACB0_RC                    *((volatile unsigned int*)(0x42C002DCUL))
+#define bFM3_DMAC_DMACB0_FD                    *((volatile unsigned int*)(0x42C002E0UL))
+#define bFM3_DMAC_DMACB0_FS                    *((volatile unsigned int*)(0x42C002E4UL))
+#define bFM3_DMAC_DMACB0_TW0                   *((volatile unsigned int*)(0x42C002E8UL))
+#define bFM3_DMAC_DMACB0_TW1                   *((volatile unsigned int*)(0x42C002ECUL))
+#define bFM3_DMAC_DMACB0_MS0                   *((volatile unsigned int*)(0x42C002F0UL))
+#define bFM3_DMAC_DMACB0_MS1                   *((volatile unsigned int*)(0x42C002F4UL))
+#define bFM3_DMAC_DMACA1_TC0                   *((volatile unsigned int*)(0x42C00400UL))
+#define bFM3_DMAC_DMACA1_TC1                   *((volatile unsigned int*)(0x42C00404UL))
+#define bFM3_DMAC_DMACA1_TC2                   *((volatile unsigned int*)(0x42C00408UL))
+#define bFM3_DMAC_DMACA1_TC3                   *((volatile unsigned int*)(0x42C0040CUL))
+#define bFM3_DMAC_DMACA1_TC4                   *((volatile unsigned int*)(0x42C00410UL))
+#define bFM3_DMAC_DMACA1_TC5                   *((volatile unsigned int*)(0x42C00414UL))
+#define bFM3_DMAC_DMACA1_TC6                   *((volatile unsigned int*)(0x42C00418UL))
+#define bFM3_DMAC_DMACA1_TC7                   *((volatile unsigned int*)(0x42C0041CUL))
+#define bFM3_DMAC_DMACA1_TC8                   *((volatile unsigned int*)(0x42C00420UL))
+#define bFM3_DMAC_DMACA1_TC9                   *((volatile unsigned int*)(0x42C00424UL))
+#define bFM3_DMAC_DMACA1_TC10                  *((volatile unsigned int*)(0x42C00428UL))
+#define bFM3_DMAC_DMACA1_TC11                  *((volatile unsigned int*)(0x42C0042CUL))
+#define bFM3_DMAC_DMACA1_TC12                  *((volatile unsigned int*)(0x42C00430UL))
+#define bFM3_DMAC_DMACA1_TC13                  *((volatile unsigned int*)(0x42C00434UL))
+#define bFM3_DMAC_DMACA1_TC14                  *((volatile unsigned int*)(0x42C00438UL))
+#define bFM3_DMAC_DMACA1_TC15                  *((volatile unsigned int*)(0x42C0043CUL))
+#define bFM3_DMAC_DMACA1_BC0                   *((volatile unsigned int*)(0x42C00440UL))
+#define bFM3_DMAC_DMACA1_BC1                   *((volatile unsigned int*)(0x42C00444UL))
+#define bFM3_DMAC_DMACA1_BC2                   *((volatile unsigned int*)(0x42C00448UL))
+#define bFM3_DMAC_DMACA1_BC3                   *((volatile unsigned int*)(0x42C0044CUL))
+#define bFM3_DMAC_DMACA1_IS0                   *((volatile unsigned int*)(0x42C0045CUL))
+#define bFM3_DMAC_DMACA1_IS1                   *((volatile unsigned int*)(0x42C00460UL))
+#define bFM3_DMAC_DMACA1_IS2                   *((volatile unsigned int*)(0x42C00464UL))
+#define bFM3_DMAC_DMACA1_IS3                   *((volatile unsigned int*)(0x42C00468UL))
+#define bFM3_DMAC_DMACA1_IS4                   *((volatile unsigned int*)(0x42C0046CUL))
+#define bFM3_DMAC_DMACA1_IS5                   *((volatile unsigned int*)(0x42C00470UL))
+#define bFM3_DMAC_DMACA1_ST                    *((volatile unsigned int*)(0x42C00474UL))
+#define bFM3_DMAC_DMACA1_PB                    *((volatile unsigned int*)(0x42C00478UL))
+#define bFM3_DMAC_DMACA1_EB                    *((volatile unsigned int*)(0x42C0047CUL))
+#define bFM3_DMAC_DMACB1_EM                    *((volatile unsigned int*)(0x42C00480UL))
+#define bFM3_DMAC_DMACB1_SS0                   *((volatile unsigned int*)(0x42C004C0UL))
+#define bFM3_DMAC_DMACB1_SS1                   *((volatile unsigned int*)(0x42C004C4UL))
+#define bFM3_DMAC_DMACB1_SS2                   *((volatile unsigned int*)(0x42C004C8UL))
+#define bFM3_DMAC_DMACB1_CI                    *((volatile unsigned int*)(0x42C004CCUL))
+#define bFM3_DMAC_DMACB1_EI                    *((volatile unsigned int*)(0x42C004D0UL))
+#define bFM3_DMAC_DMACB1_RD                    *((volatile unsigned int*)(0x42C004D4UL))
+#define bFM3_DMAC_DMACB1_RS                    *((volatile unsigned int*)(0x42C004D8UL))
+#define bFM3_DMAC_DMACB1_RC                    *((volatile unsigned int*)(0x42C004DCUL))
+#define bFM3_DMAC_DMACB1_FD                    *((volatile unsigned int*)(0x42C004E0UL))
+#define bFM3_DMAC_DMACB1_FS                    *((volatile unsigned int*)(0x42C004E4UL))
+#define bFM3_DMAC_DMACB1_TW0                   *((volatile unsigned int*)(0x42C004E8UL))
+#define bFM3_DMAC_DMACB1_TW1                   *((volatile unsigned int*)(0x42C004ECUL))
+#define bFM3_DMAC_DMACB1_MS0                   *((volatile unsigned int*)(0x42C004F0UL))
+#define bFM3_DMAC_DMACB1_MS1                   *((volatile unsigned int*)(0x42C004F4UL))
+#define bFM3_DMAC_DMACA2_TC0                   *((volatile unsigned int*)(0x42C00600UL))
+#define bFM3_DMAC_DMACA2_TC1                   *((volatile unsigned int*)(0x42C00604UL))
+#define bFM3_DMAC_DMACA2_TC2                   *((volatile unsigned int*)(0x42C00608UL))
+#define bFM3_DMAC_DMACA2_TC3                   *((volatile unsigned int*)(0x42C0060CUL))
+#define bFM3_DMAC_DMACA2_TC4                   *((volatile unsigned int*)(0x42C00610UL))
+#define bFM3_DMAC_DMACA2_TC5                   *((volatile unsigned int*)(0x42C00614UL))
+#define bFM3_DMAC_DMACA2_TC6                   *((volatile unsigned int*)(0x42C00618UL))
+#define bFM3_DMAC_DMACA2_TC7                   *((volatile unsigned int*)(0x42C0061CUL))
+#define bFM3_DMAC_DMACA2_TC8                   *((volatile unsigned int*)(0x42C00620UL))
+#define bFM3_DMAC_DMACA2_TC9                   *((volatile unsigned int*)(0x42C00624UL))
+#define bFM3_DMAC_DMACA2_TC10                  *((volatile unsigned int*)(0x42C00628UL))
+#define bFM3_DMAC_DMACA2_TC11                  *((volatile unsigned int*)(0x42C0062CUL))
+#define bFM3_DMAC_DMACA2_TC12                  *((volatile unsigned int*)(0x42C00630UL))
+#define bFM3_DMAC_DMACA2_TC13                  *((volatile unsigned int*)(0x42C00634UL))
+#define bFM3_DMAC_DMACA2_TC14                  *((volatile unsigned int*)(0x42C00638UL))
+#define bFM3_DMAC_DMACA2_TC15                  *((volatile unsigned int*)(0x42C0063CUL))
+#define bFM3_DMAC_DMACA2_BC0                   *((volatile unsigned int*)(0x42C00640UL))
+#define bFM3_DMAC_DMACA2_BC1                   *((volatile unsigned int*)(0x42C00644UL))
+#define bFM3_DMAC_DMACA2_BC2                   *((volatile unsigned int*)(0x42C00648UL))
+#define bFM3_DMAC_DMACA2_BC3                   *((volatile unsigned int*)(0x42C0064CUL))
+#define bFM3_DMAC_DMACA2_IS0                   *((volatile unsigned int*)(0x42C0065CUL))
+#define bFM3_DMAC_DMACA2_IS1                   *((volatile unsigned int*)(0x42C00660UL))
+#define bFM3_DMAC_DMACA2_IS2                   *((volatile unsigned int*)(0x42C00664UL))
+#define bFM3_DMAC_DMACA2_IS3                   *((volatile unsigned int*)(0x42C00668UL))
+#define bFM3_DMAC_DMACA2_IS4                   *((volatile unsigned int*)(0x42C0066CUL))
+#define bFM3_DMAC_DMACA2_IS5                   *((volatile unsigned int*)(0x42C00670UL))
+#define bFM3_DMAC_DMACA2_ST                    *((volatile unsigned int*)(0x42C00674UL))
+#define bFM3_DMAC_DMACA2_PB                    *((volatile unsigned int*)(0x42C00678UL))
+#define bFM3_DMAC_DMACA2_EB                    *((volatile unsigned int*)(0x42C0067CUL))
+#define bFM3_DMAC_DMACB2_EM                    *((volatile unsigned int*)(0x42C00680UL))
+#define bFM3_DMAC_DMACB2_SS0                   *((volatile unsigned int*)(0x42C006C0UL))
+#define bFM3_DMAC_DMACB2_SS1                   *((volatile unsigned int*)(0x42C006C4UL))
+#define bFM3_DMAC_DMACB2_SS2                   *((volatile unsigned int*)(0x42C006C8UL))
+#define bFM3_DMAC_DMACB2_CI                    *((volatile unsigned int*)(0x42C006CCUL))
+#define bFM3_DMAC_DMACB2_EI                    *((volatile unsigned int*)(0x42C006D0UL))
+#define bFM3_DMAC_DMACB2_RD                    *((volatile unsigned int*)(0x42C006D4UL))
+#define bFM3_DMAC_DMACB2_RS                    *((volatile unsigned int*)(0x42C006D8UL))
+#define bFM3_DMAC_DMACB2_RC                    *((volatile unsigned int*)(0x42C006DCUL))
+#define bFM3_DMAC_DMACB2_FD                    *((volatile unsigned int*)(0x42C006E0UL))
+#define bFM3_DMAC_DMACB2_FS                    *((volatile unsigned int*)(0x42C006E4UL))
+#define bFM3_DMAC_DMACB2_TW0                   *((volatile unsigned int*)(0x42C006E8UL))
+#define bFM3_DMAC_DMACB2_TW1                   *((volatile unsigned int*)(0x42C006ECUL))
+#define bFM3_DMAC_DMACB2_MS0                   *((volatile unsigned int*)(0x42C006F0UL))
+#define bFM3_DMAC_DMACB2_MS1                   *((volatile unsigned int*)(0x42C006F4UL))
+#define bFM3_DMAC_DMACA3_TC0                   *((volatile unsigned int*)(0x42C00800UL))
+#define bFM3_DMAC_DMACA3_TC1                   *((volatile unsigned int*)(0x42C00804UL))
+#define bFM3_DMAC_DMACA3_TC2                   *((volatile unsigned int*)(0x42C00808UL))
+#define bFM3_DMAC_DMACA3_TC3                   *((volatile unsigned int*)(0x42C0080CUL))
+#define bFM3_DMAC_DMACA3_TC4                   *((volatile unsigned int*)(0x42C00810UL))
+#define bFM3_DMAC_DMACA3_TC5                   *((volatile unsigned int*)(0x42C00814UL))
+#define bFM3_DMAC_DMACA3_TC6                   *((volatile unsigned int*)(0x42C00818UL))
+#define bFM3_DMAC_DMACA3_TC7                   *((volatile unsigned int*)(0x42C0081CUL))
+#define bFM3_DMAC_DMACA3_TC8                   *((volatile unsigned int*)(0x42C00820UL))
+#define bFM3_DMAC_DMACA3_TC9                   *((volatile unsigned int*)(0x42C00824UL))
+#define bFM3_DMAC_DMACA3_TC10                  *((volatile unsigned int*)(0x42C00828UL))
+#define bFM3_DMAC_DMACA3_TC11                  *((volatile unsigned int*)(0x42C0082CUL))
+#define bFM3_DMAC_DMACA3_TC12                  *((volatile unsigned int*)(0x42C00830UL))
+#define bFM3_DMAC_DMACA3_TC13                  *((volatile unsigned int*)(0x42C00834UL))
+#define bFM3_DMAC_DMACA3_TC14                  *((volatile unsigned int*)(0x42C00838UL))
+#define bFM3_DMAC_DMACA3_TC15                  *((volatile unsigned int*)(0x42C0083CUL))
+#define bFM3_DMAC_DMACA3_BC0                   *((volatile unsigned int*)(0x42C00840UL))
+#define bFM3_DMAC_DMACA3_BC1                   *((volatile unsigned int*)(0x42C00844UL))
+#define bFM3_DMAC_DMACA3_BC2                   *((volatile unsigned int*)(0x42C00848UL))
+#define bFM3_DMAC_DMACA3_BC3                   *((volatile unsigned int*)(0x42C0084CUL))
+#define bFM3_DMAC_DMACA3_IS0                   *((volatile unsigned int*)(0x42C0085CUL))
+#define bFM3_DMAC_DMACA3_IS1                   *((volatile unsigned int*)(0x42C00860UL))
+#define bFM3_DMAC_DMACA3_IS2                   *((volatile unsigned int*)(0x42C00864UL))
+#define bFM3_DMAC_DMACA3_IS3                   *((volatile unsigned int*)(0x42C00868UL))
+#define bFM3_DMAC_DMACA3_IS4                   *((volatile unsigned int*)(0x42C0086CUL))
+#define bFM3_DMAC_DMACA3_IS5                   *((volatile unsigned int*)(0x42C00870UL))
+#define bFM3_DMAC_DMACA3_ST                    *((volatile unsigned int*)(0x42C00874UL))
+#define bFM3_DMAC_DMACA3_PB                    *((volatile unsigned int*)(0x42C00878UL))
+#define bFM3_DMAC_DMACA3_EB                    *((volatile unsigned int*)(0x42C0087CUL))
+#define bFM3_DMAC_DMACB3_EM                    *((volatile unsigned int*)(0x42C00880UL))
+#define bFM3_DMAC_DMACB3_SS0                   *((volatile unsigned int*)(0x42C008C0UL))
+#define bFM3_DMAC_DMACB3_SS1                   *((volatile unsigned int*)(0x42C008C4UL))
+#define bFM3_DMAC_DMACB3_SS2                   *((volatile unsigned int*)(0x42C008C8UL))
+#define bFM3_DMAC_DMACB3_CI                    *((volatile unsigned int*)(0x42C008CCUL))
+#define bFM3_DMAC_DMACB3_EI                    *((volatile unsigned int*)(0x42C008D0UL))
+#define bFM3_DMAC_DMACB3_RD                    *((volatile unsigned int*)(0x42C008D4UL))
+#define bFM3_DMAC_DMACB3_RS                    *((volatile unsigned int*)(0x42C008D8UL))
+#define bFM3_DMAC_DMACB3_RC                    *((volatile unsigned int*)(0x42C008DCUL))
+#define bFM3_DMAC_DMACB3_FD                    *((volatile unsigned int*)(0x42C008E0UL))
+#define bFM3_DMAC_DMACB3_FS                    *((volatile unsigned int*)(0x42C008E4UL))
+#define bFM3_DMAC_DMACB3_TW0                   *((volatile unsigned int*)(0x42C008E8UL))
+#define bFM3_DMAC_DMACB3_TW1                   *((volatile unsigned int*)(0x42C008ECUL))
+#define bFM3_DMAC_DMACB3_MS0                   *((volatile unsigned int*)(0x42C008F0UL))
+#define bFM3_DMAC_DMACB3_MS1                   *((volatile unsigned int*)(0x42C008F4UL))
+#define bFM3_DMAC_DMACA4_TC0                   *((volatile unsigned int*)(0x42C00A00UL))
+#define bFM3_DMAC_DMACA4_TC1                   *((volatile unsigned int*)(0x42C00A04UL))
+#define bFM3_DMAC_DMACA4_TC2                   *((volatile unsigned int*)(0x42C00A08UL))
+#define bFM3_DMAC_DMACA4_TC3                   *((volatile unsigned int*)(0x42C00A0CUL))
+#define bFM3_DMAC_DMACA4_TC4                   *((volatile unsigned int*)(0x42C00A10UL))
+#define bFM3_DMAC_DMACA4_TC5                   *((volatile unsigned int*)(0x42C00A14UL))
+#define bFM3_DMAC_DMACA4_TC6                   *((volatile unsigned int*)(0x42C00A18UL))
+#define bFM3_DMAC_DMACA4_TC7                   *((volatile unsigned int*)(0x42C00A1CUL))
+#define bFM3_DMAC_DMACA4_TC8                   *((volatile unsigned int*)(0x42C00A20UL))
+#define bFM3_DMAC_DMACA4_TC9                   *((volatile unsigned int*)(0x42C00A24UL))
+#define bFM3_DMAC_DMACA4_TC10                  *((volatile unsigned int*)(0x42C00A28UL))
+#define bFM3_DMAC_DMACA4_TC11                  *((volatile unsigned int*)(0x42C00A2CUL))
+#define bFM3_DMAC_DMACA4_TC12                  *((volatile unsigned int*)(0x42C00A30UL))
+#define bFM3_DMAC_DMACA4_TC13                  *((volatile unsigned int*)(0x42C00A34UL))
+#define bFM3_DMAC_DMACA4_TC14                  *((volatile unsigned int*)(0x42C00A38UL))
+#define bFM3_DMAC_DMACA4_TC15                  *((volatile unsigned int*)(0x42C00A3CUL))
+#define bFM3_DMAC_DMACA4_BC0                   *((volatile unsigned int*)(0x42C00A40UL))
+#define bFM3_DMAC_DMACA4_BC1                   *((volatile unsigned int*)(0x42C00A44UL))
+#define bFM3_DMAC_DMACA4_BC2                   *((volatile unsigned int*)(0x42C00A48UL))
+#define bFM3_DMAC_DMACA4_BC3                   *((volatile unsigned int*)(0x42C00A4CUL))
+#define bFM3_DMAC_DMACA4_IS0                   *((volatile unsigned int*)(0x42C00A5CUL))
+#define bFM3_DMAC_DMACA4_IS1                   *((volatile unsigned int*)(0x42C00A60UL))
+#define bFM3_DMAC_DMACA4_IS2                   *((volatile unsigned int*)(0x42C00A64UL))
+#define bFM3_DMAC_DMACA4_IS3                   *((volatile unsigned int*)(0x42C00A68UL))
+#define bFM3_DMAC_DMACA4_IS4                   *((volatile unsigned int*)(0x42C00A6CUL))
+#define bFM3_DMAC_DMACA4_IS5                   *((volatile unsigned int*)(0x42C00A70UL))
+#define bFM3_DMAC_DMACA4_ST                    *((volatile unsigned int*)(0x42C00A74UL))
+#define bFM3_DMAC_DMACA4_PB                    *((volatile unsigned int*)(0x42C00A78UL))
+#define bFM3_DMAC_DMACA4_EB                    *((volatile unsigned int*)(0x42C00A7CUL))
+#define bFM3_DMAC_DMACB4_EM                    *((volatile unsigned int*)(0x42C00A80UL))
+#define bFM3_DMAC_DMACB4_SS0                   *((volatile unsigned int*)(0x42C00AC0UL))
+#define bFM3_DMAC_DMACB4_SS1                   *((volatile unsigned int*)(0x42C00AC4UL))
+#define bFM3_DMAC_DMACB4_SS2                   *((volatile unsigned int*)(0x42C00AC8UL))
+#define bFM3_DMAC_DMACB4_CI                    *((volatile unsigned int*)(0x42C00ACCUL))
+#define bFM3_DMAC_DMACB4_EI                    *((volatile unsigned int*)(0x42C00AD0UL))
+#define bFM3_DMAC_DMACB4_RD                    *((volatile unsigned int*)(0x42C00AD4UL))
+#define bFM3_DMAC_DMACB4_RS                    *((volatile unsigned int*)(0x42C00AD8UL))
+#define bFM3_DMAC_DMACB4_RC                    *((volatile unsigned int*)(0x42C00ADCUL))
+#define bFM3_DMAC_DMACB4_FD                    *((volatile unsigned int*)(0x42C00AE0UL))
+#define bFM3_DMAC_DMACB4_FS                    *((volatile unsigned int*)(0x42C00AE4UL))
+#define bFM3_DMAC_DMACB4_TW0                   *((volatile unsigned int*)(0x42C00AE8UL))
+#define bFM3_DMAC_DMACB4_TW1                   *((volatile unsigned int*)(0x42C00AECUL))
+#define bFM3_DMAC_DMACB4_MS0                   *((volatile unsigned int*)(0x42C00AF0UL))
+#define bFM3_DMAC_DMACB4_MS1                   *((volatile unsigned int*)(0x42C00AF4UL))
+#define bFM3_DMAC_DMACA5_TC0                   *((volatile unsigned int*)(0x42C00C00UL))
+#define bFM3_DMAC_DMACA5_TC1                   *((volatile unsigned int*)(0x42C00C04UL))
+#define bFM3_DMAC_DMACA5_TC2                   *((volatile unsigned int*)(0x42C00C08UL))
+#define bFM3_DMAC_DMACA5_TC3                   *((volatile unsigned int*)(0x42C00C0CUL))
+#define bFM3_DMAC_DMACA5_TC4                   *((volatile unsigned int*)(0x42C00C10UL))
+#define bFM3_DMAC_DMACA5_TC5                   *((volatile unsigned int*)(0x42C00C14UL))
+#define bFM3_DMAC_DMACA5_TC6                   *((volatile unsigned int*)(0x42C00C18UL))
+#define bFM3_DMAC_DMACA5_TC7                   *((volatile unsigned int*)(0x42C00C1CUL))
+#define bFM3_DMAC_DMACA5_TC8                   *((volatile unsigned int*)(0x42C00C20UL))
+#define bFM3_DMAC_DMACA5_TC9                   *((volatile unsigned int*)(0x42C00C24UL))
+#define bFM3_DMAC_DMACA5_TC10                  *((volatile unsigned int*)(0x42C00C28UL))
+#define bFM3_DMAC_DMACA5_TC11                  *((volatile unsigned int*)(0x42C00C2CUL))
+#define bFM3_DMAC_DMACA5_TC12                  *((volatile unsigned int*)(0x42C00C30UL))
+#define bFM3_DMAC_DMACA5_TC13                  *((volatile unsigned int*)(0x42C00C34UL))
+#define bFM3_DMAC_DMACA5_TC14                  *((volatile unsigned int*)(0x42C00C38UL))
+#define bFM3_DMAC_DMACA5_TC15                  *((volatile unsigned int*)(0x42C00C3CUL))
+#define bFM3_DMAC_DMACA5_BC0                   *((volatile unsigned int*)(0x42C00C40UL))
+#define bFM3_DMAC_DMACA5_BC1                   *((volatile unsigned int*)(0x42C00C44UL))
+#define bFM3_DMAC_DMACA5_BC2                   *((volatile unsigned int*)(0x42C00C48UL))
+#define bFM3_DMAC_DMACA5_BC3                   *((volatile unsigned int*)(0x42C00C4CUL))
+#define bFM3_DMAC_DMACA5_IS0                   *((volatile unsigned int*)(0x42C00C5CUL))
+#define bFM3_DMAC_DMACA5_IS1                   *((volatile unsigned int*)(0x42C00C60UL))
+#define bFM3_DMAC_DMACA5_IS2                   *((volatile unsigned int*)(0x42C00C64UL))
+#define bFM3_DMAC_DMACA5_IS3                   *((volatile unsigned int*)(0x42C00C68UL))
+#define bFM3_DMAC_DMACA5_IS4                   *((volatile unsigned int*)(0x42C00C6CUL))
+#define bFM3_DMAC_DMACA5_IS5                   *((volatile unsigned int*)(0x42C00C70UL))
+#define bFM3_DMAC_DMACA5_ST                    *((volatile unsigned int*)(0x42C00C74UL))
+#define bFM3_DMAC_DMACA5_PB                    *((volatile unsigned int*)(0x42C00C78UL))
+#define bFM3_DMAC_DMACA5_EB                    *((volatile unsigned int*)(0x42C00C7CUL))
+#define bFM3_DMAC_DMACB5_EM                    *((volatile unsigned int*)(0x42C00C80UL))
+#define bFM3_DMAC_DMACB5_SS0                   *((volatile unsigned int*)(0x42C00CC0UL))
+#define bFM3_DMAC_DMACB5_SS1                   *((volatile unsigned int*)(0x42C00CC4UL))
+#define bFM3_DMAC_DMACB5_SS2                   *((volatile unsigned int*)(0x42C00CC8UL))
+#define bFM3_DMAC_DMACB5_CI                    *((volatile unsigned int*)(0x42C00CCCUL))
+#define bFM3_DMAC_DMACB5_EI                    *((volatile unsigned int*)(0x42C00CD0UL))
+#define bFM3_DMAC_DMACB5_RD                    *((volatile unsigned int*)(0x42C00CD4UL))
+#define bFM3_DMAC_DMACB5_RS                    *((volatile unsigned int*)(0x42C00CD8UL))
+#define bFM3_DMAC_DMACB5_RC                    *((volatile unsigned int*)(0x42C00CDCUL))
+#define bFM3_DMAC_DMACB5_FD                    *((volatile unsigned int*)(0x42C00CE0UL))
+#define bFM3_DMAC_DMACB5_FS                    *((volatile unsigned int*)(0x42C00CE4UL))
+#define bFM3_DMAC_DMACB5_TW0                   *((volatile unsigned int*)(0x42C00CE8UL))
+#define bFM3_DMAC_DMACB5_TW1                   *((volatile unsigned int*)(0x42C00CECUL))
+#define bFM3_DMAC_DMACB5_MS0                   *((volatile unsigned int*)(0x42C00CF0UL))
+#define bFM3_DMAC_DMACB5_MS1                   *((volatile unsigned int*)(0x42C00CF4UL))
+#define bFM3_DMAC_DMACA6_TC0                   *((volatile unsigned int*)(0x42C00E00UL))
+#define bFM3_DMAC_DMACA6_TC1                   *((volatile unsigned int*)(0x42C00E04UL))
+#define bFM3_DMAC_DMACA6_TC2                   *((volatile unsigned int*)(0x42C00E08UL))
+#define bFM3_DMAC_DMACA6_TC3                   *((volatile unsigned int*)(0x42C00E0CUL))
+#define bFM3_DMAC_DMACA6_TC4                   *((volatile unsigned int*)(0x42C00E10UL))
+#define bFM3_DMAC_DMACA6_TC5                   *((volatile unsigned int*)(0x42C00E14UL))
+#define bFM3_DMAC_DMACA6_TC6                   *((volatile unsigned int*)(0x42C00E18UL))
+#define bFM3_DMAC_DMACA6_TC7                   *((volatile unsigned int*)(0x42C00E1CUL))
+#define bFM3_DMAC_DMACA6_TC8                   *((volatile unsigned int*)(0x42C00E20UL))
+#define bFM3_DMAC_DMACA6_TC9                   *((volatile unsigned int*)(0x42C00E24UL))
+#define bFM3_DMAC_DMACA6_TC10                  *((volatile unsigned int*)(0x42C00E28UL))
+#define bFM3_DMAC_DMACA6_TC11                  *((volatile unsigned int*)(0x42C00E2CUL))
+#define bFM3_DMAC_DMACA6_TC12                  *((volatile unsigned int*)(0x42C00E30UL))
+#define bFM3_DMAC_DMACA6_TC13                  *((volatile unsigned int*)(0x42C00E34UL))
+#define bFM3_DMAC_DMACA6_TC14                  *((volatile unsigned int*)(0x42C00E38UL))
+#define bFM3_DMAC_DMACA6_TC15                  *((volatile unsigned int*)(0x42C00E3CUL))
+#define bFM3_DMAC_DMACA6_BC0                   *((volatile unsigned int*)(0x42C00E40UL))
+#define bFM3_DMAC_DMACA6_BC1                   *((volatile unsigned int*)(0x42C00E44UL))
+#define bFM3_DMAC_DMACA6_BC2                   *((volatile unsigned int*)(0x42C00E48UL))
+#define bFM3_DMAC_DMACA6_BC3                   *((volatile unsigned int*)(0x42C00E4CUL))
+#define bFM3_DMAC_DMACA6_IS0                   *((volatile unsigned int*)(0x42C00E5CUL))
+#define bFM3_DMAC_DMACA6_IS1                   *((volatile unsigned int*)(0x42C00E60UL))
+#define bFM3_DMAC_DMACA6_IS2                   *((volatile unsigned int*)(0x42C00E64UL))
+#define bFM3_DMAC_DMACA6_IS3                   *((volatile unsigned int*)(0x42C00E68UL))
+#define bFM3_DMAC_DMACA6_IS4                   *((volatile unsigned int*)(0x42C00E6CUL))
+#define bFM3_DMAC_DMACA6_IS5                   *((volatile unsigned int*)(0x42C00E70UL))
+#define bFM3_DMAC_DMACA6_ST                    *((volatile unsigned int*)(0x42C00E74UL))
+#define bFM3_DMAC_DMACA6_PB                    *((volatile unsigned int*)(0x42C00E78UL))
+#define bFM3_DMAC_DMACA6_EB                    *((volatile unsigned int*)(0x42C00E7CUL))
+#define bFM3_DMAC_DMACB6_EM                    *((volatile unsigned int*)(0x42C00E80UL))
+#define bFM3_DMAC_DMACB6_SS0                   *((volatile unsigned int*)(0x42C00EC0UL))
+#define bFM3_DMAC_DMACB6_SS1                   *((volatile unsigned int*)(0x42C00EC4UL))
+#define bFM3_DMAC_DMACB6_SS2                   *((volatile unsigned int*)(0x42C00EC8UL))
+#define bFM3_DMAC_DMACB6_CI                    *((volatile unsigned int*)(0x42C00ECCUL))
+#define bFM3_DMAC_DMACB6_EI                    *((volatile unsigned int*)(0x42C00ED0UL))
+#define bFM3_DMAC_DMACB6_RD                    *((volatile unsigned int*)(0x42C00ED4UL))
+#define bFM3_DMAC_DMACB6_RS                    *((volatile unsigned int*)(0x42C00ED8UL))
+#define bFM3_DMAC_DMACB6_RC                    *((volatile unsigned int*)(0x42C00EDCUL))
+#define bFM3_DMAC_DMACB6_FD                    *((volatile unsigned int*)(0x42C00EE0UL))
+#define bFM3_DMAC_DMACB6_FS                    *((volatile unsigned int*)(0x42C00EE4UL))
+#define bFM3_DMAC_DMACB6_TW0                   *((volatile unsigned int*)(0x42C00EE8UL))
+#define bFM3_DMAC_DMACB6_TW1                   *((volatile unsigned int*)(0x42C00EECUL))
+#define bFM3_DMAC_DMACB6_MS0                   *((volatile unsigned int*)(0x42C00EF0UL))
+#define bFM3_DMAC_DMACB6_MS1                   *((volatile unsigned int*)(0x42C00EF4UL))
+#define bFM3_DMAC_DMACA7_TC0                   *((volatile unsigned int*)(0x42C01000UL))
+#define bFM3_DMAC_DMACA7_TC1                   *((volatile unsigned int*)(0x42C01004UL))
+#define bFM3_DMAC_DMACA7_TC2                   *((volatile unsigned int*)(0x42C01008UL))
+#define bFM3_DMAC_DMACA7_TC3                   *((volatile unsigned int*)(0x42C0100CUL))
+#define bFM3_DMAC_DMACA7_TC4                   *((volatile unsigned int*)(0x42C01010UL))
+#define bFM3_DMAC_DMACA7_TC5                   *((volatile unsigned int*)(0x42C01014UL))
+#define bFM3_DMAC_DMACA7_TC6                   *((volatile unsigned int*)(0x42C01018UL))
+#define bFM3_DMAC_DMACA7_TC7                   *((volatile unsigned int*)(0x42C0101CUL))
+#define bFM3_DMAC_DMACA7_TC8                   *((volatile unsigned int*)(0x42C01020UL))
+#define bFM3_DMAC_DMACA7_TC9                   *((volatile unsigned int*)(0x42C01024UL))
+#define bFM3_DMAC_DMACA7_TC10                  *((volatile unsigned int*)(0x42C01028UL))
+#define bFM3_DMAC_DMACA7_TC11                  *((volatile unsigned int*)(0x42C0102CUL))
+#define bFM3_DMAC_DMACA7_TC12                  *((volatile unsigned int*)(0x42C01030UL))
+#define bFM3_DMAC_DMACA7_TC13                  *((volatile unsigned int*)(0x42C01034UL))
+#define bFM3_DMAC_DMACA7_TC14                  *((volatile unsigned int*)(0x42C01038UL))
+#define bFM3_DMAC_DMACA7_TC15                  *((volatile unsigned int*)(0x42C0103CUL))
+#define bFM3_DMAC_DMACA7_BC0                   *((volatile unsigned int*)(0x42C01040UL))
+#define bFM3_DMAC_DMACA7_BC1                   *((volatile unsigned int*)(0x42C01044UL))
+#define bFM3_DMAC_DMACA7_BC2                   *((volatile unsigned int*)(0x42C01048UL))
+#define bFM3_DMAC_DMACA7_BC3                   *((volatile unsigned int*)(0x42C0104CUL))
+#define bFM3_DMAC_DMACA7_IS0                   *((volatile unsigned int*)(0x42C0105CUL))
+#define bFM3_DMAC_DMACA7_IS1                   *((volatile unsigned int*)(0x42C01060UL))
+#define bFM3_DMAC_DMACA7_IS2                   *((volatile unsigned int*)(0x42C01064UL))
+#define bFM3_DMAC_DMACA7_IS3                   *((volatile unsigned int*)(0x42C01068UL))
+#define bFM3_DMAC_DMACA7_IS4                   *((volatile unsigned int*)(0x42C0106CUL))
+#define bFM3_DMAC_DMACA7_IS5                   *((volatile unsigned int*)(0x42C01070UL))
+#define bFM3_DMAC_DMACA7_ST                    *((volatile unsigned int*)(0x42C01074UL))
+#define bFM3_DMAC_DMACA7_PB                    *((volatile unsigned int*)(0x42C01078UL))
+#define bFM3_DMAC_DMACA7_EB                    *((volatile unsigned int*)(0x42C0107CUL))
+#define bFM3_DMAC_DMACB7_EM                    *((volatile unsigned int*)(0x42C01080UL))
+#define bFM3_DMAC_DMACB7_SS0                   *((volatile unsigned int*)(0x42C010C0UL))
+#define bFM3_DMAC_DMACB7_SS1                   *((volatile unsigned int*)(0x42C010C4UL))
+#define bFM3_DMAC_DMACB7_SS2                   *((volatile unsigned int*)(0x42C010C8UL))
+#define bFM3_DMAC_DMACB7_CI                    *((volatile unsigned int*)(0x42C010CCUL))
+#define bFM3_DMAC_DMACB7_EI                    *((volatile unsigned int*)(0x42C010D0UL))
+#define bFM3_DMAC_DMACB7_RD                    *((volatile unsigned int*)(0x42C010D4UL))
+#define bFM3_DMAC_DMACB7_RS                    *((volatile unsigned int*)(0x42C010D8UL))
+#define bFM3_DMAC_DMACB7_RC                    *((volatile unsigned int*)(0x42C010DCUL))
+#define bFM3_DMAC_DMACB7_FD                    *((volatile unsigned int*)(0x42C010E0UL))
+#define bFM3_DMAC_DMACB7_FS                    *((volatile unsigned int*)(0x42C010E4UL))
+#define bFM3_DMAC_DMACB7_TW0                   *((volatile unsigned int*)(0x42C010E8UL))
+#define bFM3_DMAC_DMACB7_TW1                   *((volatile unsigned int*)(0x42C010ECUL))
+#define bFM3_DMAC_DMACB7_MS0                   *((volatile unsigned int*)(0x42C010F0UL))
+#define bFM3_DMAC_DMACB7_MS1                   *((volatile unsigned int*)(0x42C010F4UL))
+
+/* ETHERNET-MAC0 registers*/
+#define bFM3_ETHERNET_MAC0_MCR_RE              *((volatile unsigned int*)(0x42C80008UL))
+#define bFM3_ETHERNET_MAC0_MCR_TE              *((volatile unsigned int*)(0x42C8000CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DC              *((volatile unsigned int*)(0x42C80010UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL0             *((volatile unsigned int*)(0x42C80014UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL1             *((volatile unsigned int*)(0x42C80018UL))
+#define bFM3_ETHERNET_MAC0_MCR_ACS             *((volatile unsigned int*)(0x42C8001CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LUD             *((volatile unsigned int*)(0x42C80020UL))
+#define bFM3_ETHERNET_MAC0_MCR_DR              *((volatile unsigned int*)(0x42C80024UL))
+#define bFM3_ETHERNET_MAC0_MCR_IPC             *((volatile unsigned int*)(0x42C80028UL))
+#define bFM3_ETHERNET_MAC0_MCR_DM              *((volatile unsigned int*)(0x42C8002CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LM              *((volatile unsigned int*)(0x42C80030UL))
+#define bFM3_ETHERNET_MAC0_MCR_DO              *((volatile unsigned int*)(0x42C80034UL))
+#define bFM3_ETHERNET_MAC0_MCR_FES             *((volatile unsigned int*)(0x42C80038UL))
+#define bFM3_ETHERNET_MAC0_MCR_PS              *((volatile unsigned int*)(0x42C8003CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DCRS            *((volatile unsigned int*)(0x42C80040UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG0            *((volatile unsigned int*)(0x42C80044UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG1            *((volatile unsigned int*)(0x42C80048UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG2            *((volatile unsigned int*)(0x42C8004CUL))
+#define bFM3_ETHERNET_MAC0_MCR_JE              *((volatile unsigned int*)(0x42C80050UL))
+#define bFM3_ETHERNET_MAC0_MCR_BE              *((volatile unsigned int*)(0x42C80054UL))
+#define bFM3_ETHERNET_MAC0_MCR_JD              *((volatile unsigned int*)(0x42C80058UL))
+#define bFM3_ETHERNET_MAC0_MCR_WD              *((volatile unsigned int*)(0x42C8005CUL))
+#define bFM3_ETHERNET_MAC0_MCR_TC              *((volatile unsigned int*)(0x42C80060UL))
+#define bFM3_ETHERNET_MAC0_MCR_CST             *((volatile unsigned int*)(0x42C80064UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PR             *((volatile unsigned int*)(0x42C80080UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HUC            *((volatile unsigned int*)(0x42C80084UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HMC            *((volatile unsigned int*)(0x42C80088UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DAIF           *((volatile unsigned int*)(0x42C8008CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_PM             *((volatile unsigned int*)(0x42C80090UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DB             *((volatile unsigned int*)(0x42C80094UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF0           *((volatile unsigned int*)(0x42C80098UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF1           *((volatile unsigned int*)(0x42C8009CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAIF           *((volatile unsigned int*)(0x42C800A0UL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAF            *((volatile unsigned int*)(0x42C800A4UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HPF            *((volatile unsigned int*)(0x42C800A8UL))
+#define bFM3_ETHERNET_MAC0_MFFR_RA             *((volatile unsigned int*)(0x42C800FCUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH0          *((volatile unsigned int*)(0x42C80100UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH1          *((volatile unsigned int*)(0x42C80104UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH2          *((volatile unsigned int*)(0x42C80108UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH3          *((volatile unsigned int*)(0x42C8010CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH4          *((volatile unsigned int*)(0x42C80110UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH5          *((volatile unsigned int*)(0x42C80114UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH6          *((volatile unsigned int*)(0x42C80118UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH7          *((volatile unsigned int*)(0x42C8011CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH8          *((volatile unsigned int*)(0x42C80120UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH9          *((volatile unsigned int*)(0x42C80124UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH10         *((volatile unsigned int*)(0x42C80128UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH11         *((volatile unsigned int*)(0x42C8012CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH12         *((volatile unsigned int*)(0x42C80130UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH13         *((volatile unsigned int*)(0x42C80134UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH14         *((volatile unsigned int*)(0x42C80138UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH15         *((volatile unsigned int*)(0x42C8013CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH16         *((volatile unsigned int*)(0x42C80140UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH17         *((volatile unsigned int*)(0x42C80144UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH18         *((volatile unsigned int*)(0x42C80148UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH19         *((volatile unsigned int*)(0x42C8014CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH20         *((volatile unsigned int*)(0x42C80150UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH21         *((volatile unsigned int*)(0x42C80154UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH22         *((volatile unsigned int*)(0x42C80158UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH23         *((volatile unsigned int*)(0x42C8015CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH24         *((volatile unsigned int*)(0x42C80160UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH25         *((volatile unsigned int*)(0x42C80164UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH26         *((volatile unsigned int*)(0x42C80168UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH27         *((volatile unsigned int*)(0x42C8016CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH28         *((volatile unsigned int*)(0x42C80170UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH29         *((volatile unsigned int*)(0x42C80174UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH30         *((volatile unsigned int*)(0x42C80178UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH31         *((volatile unsigned int*)(0x42C8017CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL0          *((volatile unsigned int*)(0x42C80180UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL1          *((volatile unsigned int*)(0x42C80184UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL2          *((volatile unsigned int*)(0x42C80188UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL3          *((volatile unsigned int*)(0x42C8018CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL4          *((volatile unsigned int*)(0x42C80190UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL5          *((volatile unsigned int*)(0x42C80194UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL6          *((volatile unsigned int*)(0x42C80198UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL7          *((volatile unsigned int*)(0x42C8019CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL8          *((volatile unsigned int*)(0x42C801A0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL9          *((volatile unsigned int*)(0x42C801A4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL10         *((volatile unsigned int*)(0x42C801A8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL11         *((volatile unsigned int*)(0x42C801ACUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL12         *((volatile unsigned int*)(0x42C801B0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL13         *((volatile unsigned int*)(0x42C801B4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL14         *((volatile unsigned int*)(0x42C801B8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL15         *((volatile unsigned int*)(0x42C801BCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL16         *((volatile unsigned int*)(0x42C801C0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL17         *((volatile unsigned int*)(0x42C801C4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL18         *((volatile unsigned int*)(0x42C801C8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL19         *((volatile unsigned int*)(0x42C801CCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL20         *((volatile unsigned int*)(0x42C801D0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL21         *((volatile unsigned int*)(0x42C801D4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL22         *((volatile unsigned int*)(0x42C801D8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL23         *((volatile unsigned int*)(0x42C801DCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL24         *((volatile unsigned int*)(0x42C801E0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL25         *((volatile unsigned int*)(0x42C801E4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL26         *((volatile unsigned int*)(0x42C801E8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL27         *((volatile unsigned int*)(0x42C801ECUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL28         *((volatile unsigned int*)(0x42C801F0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL29         *((volatile unsigned int*)(0x42C801F4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL30         *((volatile unsigned int*)(0x42C801F8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL31         *((volatile unsigned int*)(0x42C801FCUL))
+#define bFM3_ETHERNET_MAC0_GAR_GB              *((volatile unsigned int*)(0x42C80200UL))
+#define bFM3_ETHERNET_MAC0_GAR_GW              *((volatile unsigned int*)(0x42C80204UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR0             *((volatile unsigned int*)(0x42C80208UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR1             *((volatile unsigned int*)(0x42C8020CUL))
+#define bFM3_ETHERNET_MAC0_GAR_CR2             *((volatile unsigned int*)(0x42C80210UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR3             *((volatile unsigned int*)(0x42C80214UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR0             *((volatile unsigned int*)(0x42C80218UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR1             *((volatile unsigned int*)(0x42C8021CUL))
+#define bFM3_ETHERNET_MAC0_GAR_GR2             *((volatile unsigned int*)(0x42C80220UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR3             *((volatile unsigned int*)(0x42C80224UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR4             *((volatile unsigned int*)(0x42C80228UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA0             *((volatile unsigned int*)(0x42C8022CUL))
+#define bFM3_ETHERNET_MAC0_GAR_PA1             *((volatile unsigned int*)(0x42C80230UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA2             *((volatile unsigned int*)(0x42C80234UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA3             *((volatile unsigned int*)(0x42C80238UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA4             *((volatile unsigned int*)(0x42C8023CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD0             *((volatile unsigned int*)(0x42C80280UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD1             *((volatile unsigned int*)(0x42C80284UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD2             *((volatile unsigned int*)(0x42C80288UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD3             *((volatile unsigned int*)(0x42C8028CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD4             *((volatile unsigned int*)(0x42C80290UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD5             *((volatile unsigned int*)(0x42C80294UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD6             *((volatile unsigned int*)(0x42C80298UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD7             *((volatile unsigned int*)(0x42C8029CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD8             *((volatile unsigned int*)(0x42C802A0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD9             *((volatile unsigned int*)(0x42C802A4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD10            *((volatile unsigned int*)(0x42C802A8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD11            *((volatile unsigned int*)(0x42C802ACUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD12            *((volatile unsigned int*)(0x42C802B0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD13            *((volatile unsigned int*)(0x42C802B4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD14            *((volatile unsigned int*)(0x42C802B8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD15            *((volatile unsigned int*)(0x42C802BCUL))
+#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA         *((volatile unsigned int*)(0x42C80300UL))
+#define bFM3_ETHERNET_MAC0_FCR_TFE             *((volatile unsigned int*)(0x42C80304UL))
+#define bFM3_ETHERNET_MAC0_FCR_RFE             *((volatile unsigned int*)(0x42C80308UL))
+#define bFM3_ETHERNET_MAC0_FCR_UP              *((volatile unsigned int*)(0x42C8030CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT0            *((volatile unsigned int*)(0x42C80310UL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT1            *((volatile unsigned int*)(0x42C80314UL))
+#define bFM3_ETHERNET_MAC0_FCR_DZPQ            *((volatile unsigned int*)(0x42C8031CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT0             *((volatile unsigned int*)(0x42C80340UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT1             *((volatile unsigned int*)(0x42C80344UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT2             *((volatile unsigned int*)(0x42C80348UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT3             *((volatile unsigned int*)(0x42C8034CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT4             *((volatile unsigned int*)(0x42C80350UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT5             *((volatile unsigned int*)(0x42C80354UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT6             *((volatile unsigned int*)(0x42C80358UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT7             *((volatile unsigned int*)(0x42C8035CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT8             *((volatile unsigned int*)(0x42C80360UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT9             *((volatile unsigned int*)(0x42C80364UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT10            *((volatile unsigned int*)(0x42C80368UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT11            *((volatile unsigned int*)(0x42C8036CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT12            *((volatile unsigned int*)(0x42C80370UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT13            *((volatile unsigned int*)(0x42C80374UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT14            *((volatile unsigned int*)(0x42C80378UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT15            *((volatile unsigned int*)(0x42C8037CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL0             *((volatile unsigned int*)(0x42C80380UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL1             *((volatile unsigned int*)(0x42C80384UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL2             *((volatile unsigned int*)(0x42C80388UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL3             *((volatile unsigned int*)(0x42C8038CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL4             *((volatile unsigned int*)(0x42C80390UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL5             *((volatile unsigned int*)(0x42C80394UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL6             *((volatile unsigned int*)(0x42C80398UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL7             *((volatile unsigned int*)(0x42C8039CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL8             *((volatile unsigned int*)(0x42C803A0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL9             *((volatile unsigned int*)(0x42C803A4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL10            *((volatile unsigned int*)(0x42C803A8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL11            *((volatile unsigned int*)(0x42C803ACUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL12            *((volatile unsigned int*)(0x42C803B0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL13            *((volatile unsigned int*)(0x42C803B4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL14            *((volatile unsigned int*)(0x42C803B8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL15            *((volatile unsigned int*)(0x42C803BCUL))
+#define bFM3_ETHERNET_MAC0_VTR_ETV             *((volatile unsigned int*)(0x42C803C0UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42C80500UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42C80504UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42C80508UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42C8050CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42C80510UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42C80514UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42C80518UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42C8051CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42C80520UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42C80524UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42C80528UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42C8052CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42C80530UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42C80534UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42C80538UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42C8053CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42C80540UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42C80544UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42C80548UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42C8054CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42C80550UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42C80554UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42C80558UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42C8055CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42C80560UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42C80564UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42C80568UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42C8056CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42C80570UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42C80574UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42C80578UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42C8057CUL))
+#define bFM3_ETHERNET_MAC0_PMTR_PD             *((volatile unsigned int*)(0x42C80580UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPE            *((volatile unsigned int*)(0x42C80584UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WFE            *((volatile unsigned int*)(0x42C80588UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPR            *((volatile unsigned int*)(0x42C80594UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WPR            *((volatile unsigned int*)(0x42C80598UL))
+#define bFM3_ETHERNET_MAC0_PMTR_GU             *((volatile unsigned int*)(0x42C805A4UL))
+#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42C805FCUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42C80600UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42C80604UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42C80608UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42C8060CUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST       *((volatile unsigned int*)(0x42C80620UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST       *((volatile unsigned int*)(0x42C80624UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN        *((volatile unsigned int*)(0x42C80640UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLS          *((volatile unsigned int*)(0x42C80644UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN        *((volatile unsigned int*)(0x42C80648UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA       *((volatile unsigned int*)(0x42C8064CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT0         *((volatile unsigned int*)(0x42C80680UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT1         *((volatile unsigned int*)(0x42C80684UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT2         *((volatile unsigned int*)(0x42C80688UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT3         *((volatile unsigned int*)(0x42C8068CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT4         *((volatile unsigned int*)(0x42C80690UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT5         *((volatile unsigned int*)(0x42C80694UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT6         *((volatile unsigned int*)(0x42C80698UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT7         *((volatile unsigned int*)(0x42C8069CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT8         *((volatile unsigned int*)(0x42C806A0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT9         *((volatile unsigned int*)(0x42C806A4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT10        *((volatile unsigned int*)(0x42C806A8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT11        *((volatile unsigned int*)(0x42C806ACUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT12        *((volatile unsigned int*)(0x42C806B0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT13        *((volatile unsigned int*)(0x42C806B4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT14        *((volatile unsigned int*)(0x42C806B8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT15        *((volatile unsigned int*)(0x42C806BCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT0         *((volatile unsigned int*)(0x42C806C0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT1         *((volatile unsigned int*)(0x42C806C4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT2         *((volatile unsigned int*)(0x42C806C8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT3         *((volatile unsigned int*)(0x42C806CCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT4         *((volatile unsigned int*)(0x42C806D0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT5         *((volatile unsigned int*)(0x42C806D4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT6         *((volatile unsigned int*)(0x42C806D8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT7         *((volatile unsigned int*)(0x42C806DCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT8         *((volatile unsigned int*)(0x42C806E0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT9         *((volatile unsigned int*)(0x42C806E4UL))
+#define bFM3_ETHERNET_MAC0_ISR_RGIS            *((volatile unsigned int*)(0x42C80700UL))
+#define bFM3_ETHERNET_MAC0_ISR_PIS             *((volatile unsigned int*)(0x42C8070CUL))
+#define bFM3_ETHERNET_MAC0_ISR_MIS             *((volatile unsigned int*)(0x42C80710UL))
+#define bFM3_ETHERNET_MAC0_ISR_RIS             *((volatile unsigned int*)(0x42C80714UL))
+#define bFM3_ETHERNET_MAC0_ISR_TIS             *((volatile unsigned int*)(0x42C80718UL))
+#define bFM3_ETHERNET_MAC0_ISR_COIS            *((volatile unsigned int*)(0x42C8071CUL))
+#define bFM3_ETHERNET_MAC0_ISR_TSIS            *((volatile unsigned int*)(0x42C80724UL))
+#define bFM3_ETHERNET_MAC0_ISR_LPIIS           *((volatile unsigned int*)(0x42C80728UL))
+#define bFM3_ETHERNET_MAC0_IMR_RGIM            *((volatile unsigned int*)(0x42C80780UL))
+#define bFM3_ETHERNET_MAC0_IMR_PIM             *((volatile unsigned int*)(0x42C8078CUL))
+#define bFM3_ETHERNET_MAC0_IMR_TSIM            *((volatile unsigned int*)(0x42C80794UL))
+#define bFM3_ETHERNET_MAC0_IMR_LPIIM           *((volatile unsigned int*)(0x42C80798UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A32           *((volatile unsigned int*)(0x42C80800UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A33           *((volatile unsigned int*)(0x42C80804UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A34           *((volatile unsigned int*)(0x42C80808UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A35           *((volatile unsigned int*)(0x42C8080CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A36           *((volatile unsigned int*)(0x42C80810UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A37           *((volatile unsigned int*)(0x42C80814UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A38           *((volatile unsigned int*)(0x42C80818UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A39           *((volatile unsigned int*)(0x42C8081CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A40           *((volatile unsigned int*)(0x42C80820UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A41           *((volatile unsigned int*)(0x42C80824UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A42           *((volatile unsigned int*)(0x42C80828UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A43           *((volatile unsigned int*)(0x42C8082CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A44           *((volatile unsigned int*)(0x42C80830UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A45           *((volatile unsigned int*)(0x42C80834UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A46           *((volatile unsigned int*)(0x42C80838UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A47           *((volatile unsigned int*)(0x42C8083CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_MO            *((volatile unsigned int*)(0x42C8087CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A0            *((volatile unsigned int*)(0x42C80880UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A1            *((volatile unsigned int*)(0x42C80884UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A2            *((volatile unsigned int*)(0x42C80888UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A3            *((volatile unsigned int*)(0x42C8088CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A4            *((volatile unsigned int*)(0x42C80890UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A5            *((volatile unsigned int*)(0x42C80894UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A6            *((volatile unsigned int*)(0x42C80898UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A7            *((volatile unsigned int*)(0x42C8089CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A8            *((volatile unsigned int*)(0x42C808A0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A9            *((volatile unsigned int*)(0x42C808A4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A10           *((volatile unsigned int*)(0x42C808A8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A11           *((volatile unsigned int*)(0x42C808ACUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A12           *((volatile unsigned int*)(0x42C808B0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A13           *((volatile unsigned int*)(0x42C808B4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A14           *((volatile unsigned int*)(0x42C808B8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A15           *((volatile unsigned int*)(0x42C808BCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A16           *((volatile unsigned int*)(0x42C808C0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A17           *((volatile unsigned int*)(0x42C808C4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A18           *((volatile unsigned int*)(0x42C808C8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A19           *((volatile unsigned int*)(0x42C808CCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A20           *((volatile unsigned int*)(0x42C808D0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A21           *((volatile unsigned int*)(0x42C808D4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A22           *((volatile unsigned int*)(0x42C808D8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A23           *((volatile unsigned int*)(0x42C808DCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A24           *((volatile unsigned int*)(0x42C808E0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A25           *((volatile unsigned int*)(0x42C808E4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A26           *((volatile unsigned int*)(0x42C808E8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A27           *((volatile unsigned int*)(0x42C808ECUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A28           *((volatile unsigned int*)(0x42C808F0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A29           *((volatile unsigned int*)(0x42C808F4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A30           *((volatile unsigned int*)(0x42C808F8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A31           *((volatile unsigned int*)(0x42C808FCUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A32           *((volatile unsigned int*)(0x42C80900UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A33           *((volatile unsigned int*)(0x42C80904UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A34           *((volatile unsigned int*)(0x42C80908UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A35           *((volatile unsigned int*)(0x42C8090CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A36           *((volatile unsigned int*)(0x42C80910UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A37           *((volatile unsigned int*)(0x42C80914UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A38           *((volatile unsigned int*)(0x42C80918UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A39           *((volatile unsigned int*)(0x42C8091CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A40           *((volatile unsigned int*)(0x42C80920UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A41           *((volatile unsigned int*)(0x42C80924UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A42           *((volatile unsigned int*)(0x42C80928UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A43           *((volatile unsigned int*)(0x42C8092CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A44           *((volatile unsigned int*)(0x42C80930UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A45           *((volatile unsigned int*)(0x42C80934UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A46           *((volatile unsigned int*)(0x42C80938UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A47           *((volatile unsigned int*)(0x42C8093CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC0          *((volatile unsigned int*)(0x42C80960UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC1          *((volatile unsigned int*)(0x42C80964UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC2          *((volatile unsigned int*)(0x42C80968UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC3          *((volatile unsigned int*)(0x42C8096CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC4          *((volatile unsigned int*)(0x42C80970UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC5          *((volatile unsigned int*)(0x42C80974UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_SA            *((volatile unsigned int*)(0x42C80978UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_AE            *((volatile unsigned int*)(0x42C8097CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A0            *((volatile unsigned int*)(0x42C80980UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A1            *((volatile unsigned int*)(0x42C80984UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A2            *((volatile unsigned int*)(0x42C80988UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A3            *((volatile unsigned int*)(0x42C8098CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A4            *((volatile unsigned int*)(0x42C80990UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A5            *((volatile unsigned int*)(0x42C80994UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A6            *((volatile unsigned int*)(0x42C80998UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A7            *((volatile unsigned int*)(0x42C8099CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A8            *((volatile unsigned int*)(0x42C809A0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A9            *((volatile unsigned int*)(0x42C809A4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A10           *((volatile unsigned int*)(0x42C809A8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A11           *((volatile unsigned int*)(0x42C809ACUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A12           *((volatile unsigned int*)(0x42C809B0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A13           *((volatile unsigned int*)(0x42C809B4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A14           *((volatile unsigned int*)(0x42C809B8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A15           *((volatile unsigned int*)(0x42C809BCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A16           *((volatile unsigned int*)(0x42C809C0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A17           *((volatile unsigned int*)(0x42C809C4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A18           *((volatile unsigned int*)(0x42C809C8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A19           *((volatile unsigned int*)(0x42C809CCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A20           *((volatile unsigned int*)(0x42C809D0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A21           *((volatile unsigned int*)(0x42C809D4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A22           *((volatile unsigned int*)(0x42C809D8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A23           *((volatile unsigned int*)(0x42C809DCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A24           *((volatile unsigned int*)(0x42C809E0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A25           *((volatile unsigned int*)(0x42C809E4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A26           *((volatile unsigned int*)(0x42C809E8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A27           *((volatile unsigned int*)(0x42C809ECUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A28           *((volatile unsigned int*)(0x42C809F0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A29           *((volatile unsigned int*)(0x42C809F4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A30           *((volatile unsigned int*)(0x42C809F8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A31           *((volatile unsigned int*)(0x42C809FCUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A32           *((volatile unsigned int*)(0x42C80A00UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A33           *((volatile unsigned int*)(0x42C80A04UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A34           *((volatile unsigned int*)(0x42C80A08UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A35           *((volatile unsigned int*)(0x42C80A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A36           *((volatile unsigned int*)(0x42C80A10UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A37           *((volatile unsigned int*)(0x42C80A14UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A38           *((volatile unsigned int*)(0x42C80A18UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A39           *((volatile unsigned int*)(0x42C80A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A40           *((volatile unsigned int*)(0x42C80A20UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A41           *((volatile unsigned int*)(0x42C80A24UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A42           *((volatile unsigned int*)(0x42C80A28UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A43           *((volatile unsigned int*)(0x42C80A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A44           *((volatile unsigned int*)(0x42C80A30UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A45           *((volatile unsigned int*)(0x42C80A34UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A46           *((volatile unsigned int*)(0x42C80A38UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A47           *((volatile unsigned int*)(0x42C80A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC0          *((volatile unsigned int*)(0x42C80A60UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC1          *((volatile unsigned int*)(0x42C80A64UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC2          *((volatile unsigned int*)(0x42C80A68UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC3          *((volatile unsigned int*)(0x42C80A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC4          *((volatile unsigned int*)(0x42C80A70UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC5          *((volatile unsigned int*)(0x42C80A74UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_SA            *((volatile unsigned int*)(0x42C80A78UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_AE            *((volatile unsigned int*)(0x42C80A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A0            *((volatile unsigned int*)(0x42C80A80UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A1            *((volatile unsigned int*)(0x42C80A84UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A2            *((volatile unsigned int*)(0x42C80A88UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A3            *((volatile unsigned int*)(0x42C80A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A4            *((volatile unsigned int*)(0x42C80A90UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A5            *((volatile unsigned int*)(0x42C80A94UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A6            *((volatile unsigned int*)(0x42C80A98UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A7            *((volatile unsigned int*)(0x42C80A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A8            *((volatile unsigned int*)(0x42C80AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A9            *((volatile unsigned int*)(0x42C80AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A10           *((volatile unsigned int*)(0x42C80AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A11           *((volatile unsigned int*)(0x42C80AACUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A12           *((volatile unsigned int*)(0x42C80AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A13           *((volatile unsigned int*)(0x42C80AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A14           *((volatile unsigned int*)(0x42C80AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A15           *((volatile unsigned int*)(0x42C80ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A16           *((volatile unsigned int*)(0x42C80AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A17           *((volatile unsigned int*)(0x42C80AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A18           *((volatile unsigned int*)(0x42C80AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A19           *((volatile unsigned int*)(0x42C80ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A20           *((volatile unsigned int*)(0x42C80AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A21           *((volatile unsigned int*)(0x42C80AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A22           *((volatile unsigned int*)(0x42C80AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A23           *((volatile unsigned int*)(0x42C80ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A24           *((volatile unsigned int*)(0x42C80AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A25           *((volatile unsigned int*)(0x42C80AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A26           *((volatile unsigned int*)(0x42C80AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A27           *((volatile unsigned int*)(0x42C80AECUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A28           *((volatile unsigned int*)(0x42C80AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A29           *((volatile unsigned int*)(0x42C80AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A30           *((volatile unsigned int*)(0x42C80AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A31           *((volatile unsigned int*)(0x42C80AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A32           *((volatile unsigned int*)(0x42C80B00UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A33           *((volatile unsigned int*)(0x42C80B04UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A34           *((volatile unsigned int*)(0x42C80B08UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A35           *((volatile unsigned int*)(0x42C80B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A36           *((volatile unsigned int*)(0x42C80B10UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A37           *((volatile unsigned int*)(0x42C80B14UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A38           *((volatile unsigned int*)(0x42C80B18UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A39           *((volatile unsigned int*)(0x42C80B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A40           *((volatile unsigned int*)(0x42C80B20UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A41           *((volatile unsigned int*)(0x42C80B24UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A42           *((volatile unsigned int*)(0x42C80B28UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A43           *((volatile unsigned int*)(0x42C80B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A44           *((volatile unsigned int*)(0x42C80B30UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A45           *((volatile unsigned int*)(0x42C80B34UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A46           *((volatile unsigned int*)(0x42C80B38UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A47           *((volatile unsigned int*)(0x42C80B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC0          *((volatile unsigned int*)(0x42C80B60UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC1          *((volatile unsigned int*)(0x42C80B64UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC2          *((volatile unsigned int*)(0x42C80B68UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC3          *((volatile unsigned int*)(0x42C80B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC4          *((volatile unsigned int*)(0x42C80B70UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC5          *((volatile unsigned int*)(0x42C80B74UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_SA            *((volatile unsigned int*)(0x42C80B78UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_AE            *((volatile unsigned int*)(0x42C80B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A0            *((volatile unsigned int*)(0x42C80B80UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A1            *((volatile unsigned int*)(0x42C80B84UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A2            *((volatile unsigned int*)(0x42C80B88UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A3            *((volatile unsigned int*)(0x42C80B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A4            *((volatile unsigned int*)(0x42C80B90UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A5            *((volatile unsigned int*)(0x42C80B94UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A6            *((volatile unsigned int*)(0x42C80B98UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A7            *((volatile unsigned int*)(0x42C80B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A8            *((volatile unsigned int*)(0x42C80BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A9            *((volatile unsigned int*)(0x42C80BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A10           *((volatile unsigned int*)(0x42C80BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A11           *((volatile unsigned int*)(0x42C80BACUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A12           *((volatile unsigned int*)(0x42C80BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A13           *((volatile unsigned int*)(0x42C80BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A14           *((volatile unsigned int*)(0x42C80BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A15           *((volatile unsigned int*)(0x42C80BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A16           *((volatile unsigned int*)(0x42C80BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A17           *((volatile unsigned int*)(0x42C80BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A18           *((volatile unsigned int*)(0x42C80BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A19           *((volatile unsigned int*)(0x42C80BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A20           *((volatile unsigned int*)(0x42C80BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A21           *((volatile unsigned int*)(0x42C80BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A22           *((volatile unsigned int*)(0x42C80BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A23           *((volatile unsigned int*)(0x42C80BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A24           *((volatile unsigned int*)(0x42C80BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A25           *((volatile unsigned int*)(0x42C80BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A26           *((volatile unsigned int*)(0x42C80BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A27           *((volatile unsigned int*)(0x42C80BECUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A28           *((volatile unsigned int*)(0x42C80BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A29           *((volatile unsigned int*)(0x42C80BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A30           *((volatile unsigned int*)(0x42C80BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A31           *((volatile unsigned int*)(0x42C80BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A32           *((volatile unsigned int*)(0x42C80C00UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A33           *((volatile unsigned int*)(0x42C80C04UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A34           *((volatile unsigned int*)(0x42C80C08UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A35           *((volatile unsigned int*)(0x42C80C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A36           *((volatile unsigned int*)(0x42C80C10UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A37           *((volatile unsigned int*)(0x42C80C14UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A38           *((volatile unsigned int*)(0x42C80C18UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A39           *((volatile unsigned int*)(0x42C80C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A40           *((volatile unsigned int*)(0x42C80C20UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A41           *((volatile unsigned int*)(0x42C80C24UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A42           *((volatile unsigned int*)(0x42C80C28UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A43           *((volatile unsigned int*)(0x42C80C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A44           *((volatile unsigned int*)(0x42C80C30UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A45           *((volatile unsigned int*)(0x42C80C34UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A46           *((volatile unsigned int*)(0x42C80C38UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A47           *((volatile unsigned int*)(0x42C80C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC0          *((volatile unsigned int*)(0x42C80C60UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC1          *((volatile unsigned int*)(0x42C80C64UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC2          *((volatile unsigned int*)(0x42C80C68UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC3          *((volatile unsigned int*)(0x42C80C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC4          *((volatile unsigned int*)(0x42C80C70UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC5          *((volatile unsigned int*)(0x42C80C74UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_SA            *((volatile unsigned int*)(0x42C80C78UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_AE            *((volatile unsigned int*)(0x42C80C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A0            *((volatile unsigned int*)(0x42C80C80UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A1            *((volatile unsigned int*)(0x42C80C84UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A2            *((volatile unsigned int*)(0x42C80C88UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A3            *((volatile unsigned int*)(0x42C80C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A4            *((volatile unsigned int*)(0x42C80C90UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A5            *((volatile unsigned int*)(0x42C80C94UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A6            *((volatile unsigned int*)(0x42C80C98UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A7            *((volatile unsigned int*)(0x42C80C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A8            *((volatile unsigned int*)(0x42C80CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A9            *((volatile unsigned int*)(0x42C80CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A10           *((volatile unsigned int*)(0x42C80CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A11           *((volatile unsigned int*)(0x42C80CACUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A12           *((volatile unsigned int*)(0x42C80CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A13           *((volatile unsigned int*)(0x42C80CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A14           *((volatile unsigned int*)(0x42C80CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A15           *((volatile unsigned int*)(0x42C80CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A16           *((volatile unsigned int*)(0x42C80CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A17           *((volatile unsigned int*)(0x42C80CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A18           *((volatile unsigned int*)(0x42C80CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A19           *((volatile unsigned int*)(0x42C80CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A20           *((volatile unsigned int*)(0x42C80CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A21           *((volatile unsigned int*)(0x42C80CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A22           *((volatile unsigned int*)(0x42C80CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A23           *((volatile unsigned int*)(0x42C80CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A24           *((volatile unsigned int*)(0x42C80CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A25           *((volatile unsigned int*)(0x42C80CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A26           *((volatile unsigned int*)(0x42C80CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A27           *((volatile unsigned int*)(0x42C80CECUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A28           *((volatile unsigned int*)(0x42C80CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A29           *((volatile unsigned int*)(0x42C80CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A30           *((volatile unsigned int*)(0x42C80CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A31           *((volatile unsigned int*)(0x42C80CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A32           *((volatile unsigned int*)(0x42C80D00UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A33           *((volatile unsigned int*)(0x42C80D04UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A34           *((volatile unsigned int*)(0x42C80D08UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A35           *((volatile unsigned int*)(0x42C80D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A36           *((volatile unsigned int*)(0x42C80D10UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A37           *((volatile unsigned int*)(0x42C80D14UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A38           *((volatile unsigned int*)(0x42C80D18UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A39           *((volatile unsigned int*)(0x42C80D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A40           *((volatile unsigned int*)(0x42C80D20UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A41           *((volatile unsigned int*)(0x42C80D24UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A42           *((volatile unsigned int*)(0x42C80D28UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A43           *((volatile unsigned int*)(0x42C80D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A44           *((volatile unsigned int*)(0x42C80D30UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A45           *((volatile unsigned int*)(0x42C80D34UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A46           *((volatile unsigned int*)(0x42C80D38UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A47           *((volatile unsigned int*)(0x42C80D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC0          *((volatile unsigned int*)(0x42C80D60UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC1          *((volatile unsigned int*)(0x42C80D64UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC2          *((volatile unsigned int*)(0x42C80D68UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC3          *((volatile unsigned int*)(0x42C80D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC4          *((volatile unsigned int*)(0x42C80D70UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC5          *((volatile unsigned int*)(0x42C80D74UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_SA            *((volatile unsigned int*)(0x42C80D78UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_AE            *((volatile unsigned int*)(0x42C80D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A0            *((volatile unsigned int*)(0x42C80D80UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A1            *((volatile unsigned int*)(0x42C80D84UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A2            *((volatile unsigned int*)(0x42C80D88UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A3            *((volatile unsigned int*)(0x42C80D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A4            *((volatile unsigned int*)(0x42C80D90UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A5            *((volatile unsigned int*)(0x42C80D94UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A6            *((volatile unsigned int*)(0x42C80D98UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A7            *((volatile unsigned int*)(0x42C80D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A8            *((volatile unsigned int*)(0x42C80DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A9            *((volatile unsigned int*)(0x42C80DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A10           *((volatile unsigned int*)(0x42C80DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A11           *((volatile unsigned int*)(0x42C80DACUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A12           *((volatile unsigned int*)(0x42C80DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A13           *((volatile unsigned int*)(0x42C80DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A14           *((volatile unsigned int*)(0x42C80DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A15           *((volatile unsigned int*)(0x42C80DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A16           *((volatile unsigned int*)(0x42C80DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A17           *((volatile unsigned int*)(0x42C80DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A18           *((volatile unsigned int*)(0x42C80DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A19           *((volatile unsigned int*)(0x42C80DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A20           *((volatile unsigned int*)(0x42C80DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A21           *((volatile unsigned int*)(0x42C80DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A22           *((volatile unsigned int*)(0x42C80DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A23           *((volatile unsigned int*)(0x42C80DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A24           *((volatile unsigned int*)(0x42C80DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A25           *((volatile unsigned int*)(0x42C80DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A26           *((volatile unsigned int*)(0x42C80DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A27           *((volatile unsigned int*)(0x42C80DECUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A28           *((volatile unsigned int*)(0x42C80DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A29           *((volatile unsigned int*)(0x42C80DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A30           *((volatile unsigned int*)(0x42C80DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A31           *((volatile unsigned int*)(0x42C80DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A32           *((volatile unsigned int*)(0x42C80E00UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A33           *((volatile unsigned int*)(0x42C80E04UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A34           *((volatile unsigned int*)(0x42C80E08UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A35           *((volatile unsigned int*)(0x42C80E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A36           *((volatile unsigned int*)(0x42C80E10UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A37           *((volatile unsigned int*)(0x42C80E14UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A38           *((volatile unsigned int*)(0x42C80E18UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A39           *((volatile unsigned int*)(0x42C80E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A40           *((volatile unsigned int*)(0x42C80E20UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A41           *((volatile unsigned int*)(0x42C80E24UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A42           *((volatile unsigned int*)(0x42C80E28UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A43           *((volatile unsigned int*)(0x42C80E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A44           *((volatile unsigned int*)(0x42C80E30UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A45           *((volatile unsigned int*)(0x42C80E34UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A46           *((volatile unsigned int*)(0x42C80E38UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A47           *((volatile unsigned int*)(0x42C80E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC0          *((volatile unsigned int*)(0x42C80E60UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC1          *((volatile unsigned int*)(0x42C80E64UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC2          *((volatile unsigned int*)(0x42C80E68UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC3          *((volatile unsigned int*)(0x42C80E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC4          *((volatile unsigned int*)(0x42C80E70UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC5          *((volatile unsigned int*)(0x42C80E74UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_SA            *((volatile unsigned int*)(0x42C80E78UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_AE            *((volatile unsigned int*)(0x42C80E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A0            *((volatile unsigned int*)(0x42C80E80UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A1            *((volatile unsigned int*)(0x42C80E84UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A2            *((volatile unsigned int*)(0x42C80E88UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A3            *((volatile unsigned int*)(0x42C80E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A4            *((volatile unsigned int*)(0x42C80E90UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A5            *((volatile unsigned int*)(0x42C80E94UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A6            *((volatile unsigned int*)(0x42C80E98UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A7            *((volatile unsigned int*)(0x42C80E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A8            *((volatile unsigned int*)(0x42C80EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A9            *((volatile unsigned int*)(0x42C80EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A10           *((volatile unsigned int*)(0x42C80EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A11           *((volatile unsigned int*)(0x42C80EACUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A12           *((volatile unsigned int*)(0x42C80EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A13           *((volatile unsigned int*)(0x42C80EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A14           *((volatile unsigned int*)(0x42C80EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A15           *((volatile unsigned int*)(0x42C80EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A16           *((volatile unsigned int*)(0x42C80EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A17           *((volatile unsigned int*)(0x42C80EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A18           *((volatile unsigned int*)(0x42C80EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A19           *((volatile unsigned int*)(0x42C80ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A20           *((volatile unsigned int*)(0x42C80ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A21           *((volatile unsigned int*)(0x42C80ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A22           *((volatile unsigned int*)(0x42C80ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A23           *((volatile unsigned int*)(0x42C80EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A24           *((volatile unsigned int*)(0x42C80EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A25           *((volatile unsigned int*)(0x42C80EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A26           *((volatile unsigned int*)(0x42C80EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A27           *((volatile unsigned int*)(0x42C80EECUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A28           *((volatile unsigned int*)(0x42C80EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A29           *((volatile unsigned int*)(0x42C80EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A30           *((volatile unsigned int*)(0x42C80EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A31           *((volatile unsigned int*)(0x42C80EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A32           *((volatile unsigned int*)(0x42C80F00UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A33           *((volatile unsigned int*)(0x42C80F04UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A34           *((volatile unsigned int*)(0x42C80F08UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A35           *((volatile unsigned int*)(0x42C80F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A36           *((volatile unsigned int*)(0x42C80F10UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A37           *((volatile unsigned int*)(0x42C80F14UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A38           *((volatile unsigned int*)(0x42C80F18UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A39           *((volatile unsigned int*)(0x42C80F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A40           *((volatile unsigned int*)(0x42C80F20UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A41           *((volatile unsigned int*)(0x42C80F24UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A42           *((volatile unsigned int*)(0x42C80F28UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A43           *((volatile unsigned int*)(0x42C80F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A44           *((volatile unsigned int*)(0x42C80F30UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A45           *((volatile unsigned int*)(0x42C80F34UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A46           *((volatile unsigned int*)(0x42C80F38UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A47           *((volatile unsigned int*)(0x42C80F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC0          *((volatile unsigned int*)(0x42C80F60UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC1          *((volatile unsigned int*)(0x42C80F64UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC2          *((volatile unsigned int*)(0x42C80F68UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC3          *((volatile unsigned int*)(0x42C80F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC4          *((volatile unsigned int*)(0x42C80F70UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC5          *((volatile unsigned int*)(0x42C80F74UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_SA            *((volatile unsigned int*)(0x42C80F78UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_AE            *((volatile unsigned int*)(0x42C80F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A0            *((volatile unsigned int*)(0x42C80F80UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A1            *((volatile unsigned int*)(0x42C80F84UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A2            *((volatile unsigned int*)(0x42C80F88UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A3            *((volatile unsigned int*)(0x42C80F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A4            *((volatile unsigned int*)(0x42C80F90UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A5            *((volatile unsigned int*)(0x42C80F94UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A6            *((volatile unsigned int*)(0x42C80F98UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A7            *((volatile unsigned int*)(0x42C80F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A8            *((volatile unsigned int*)(0x42C80FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A9            *((volatile unsigned int*)(0x42C80FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A10           *((volatile unsigned int*)(0x42C80FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A11           *((volatile unsigned int*)(0x42C80FACUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A12           *((volatile unsigned int*)(0x42C80FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A13           *((volatile unsigned int*)(0x42C80FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A14           *((volatile unsigned int*)(0x42C80FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A15           *((volatile unsigned int*)(0x42C80FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A16           *((volatile unsigned int*)(0x42C80FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A17           *((volatile unsigned int*)(0x42C80FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A18           *((volatile unsigned int*)(0x42C80FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A19           *((volatile unsigned int*)(0x42C80FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A20           *((volatile unsigned int*)(0x42C80FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A21           *((volatile unsigned int*)(0x42C80FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A22           *((volatile unsigned int*)(0x42C80FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A23           *((volatile unsigned int*)(0x42C80FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A24           *((volatile unsigned int*)(0x42C80FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A25           *((volatile unsigned int*)(0x42C80FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A26           *((volatile unsigned int*)(0x42C80FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A27           *((volatile unsigned int*)(0x42C80FECUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A28           *((volatile unsigned int*)(0x42C80FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A29           *((volatile unsigned int*)(0x42C80FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A30           *((volatile unsigned int*)(0x42C80FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A31           *((volatile unsigned int*)(0x42C80FFCUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A32           *((volatile unsigned int*)(0x42C81000UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A33           *((volatile unsigned int*)(0x42C81004UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A34           *((volatile unsigned int*)(0x42C81008UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A35           *((volatile unsigned int*)(0x42C8100CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A36           *((volatile unsigned int*)(0x42C81010UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A37           *((volatile unsigned int*)(0x42C81014UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A38           *((volatile unsigned int*)(0x42C81018UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A39           *((volatile unsigned int*)(0x42C8101CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A40           *((volatile unsigned int*)(0x42C81020UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A41           *((volatile unsigned int*)(0x42C81024UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A42           *((volatile unsigned int*)(0x42C81028UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A43           *((volatile unsigned int*)(0x42C8102CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A44           *((volatile unsigned int*)(0x42C81030UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A45           *((volatile unsigned int*)(0x42C81034UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A46           *((volatile unsigned int*)(0x42C81038UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A47           *((volatile unsigned int*)(0x42C8103CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC0          *((volatile unsigned int*)(0x42C81060UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC1          *((volatile unsigned int*)(0x42C81064UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC2          *((volatile unsigned int*)(0x42C81068UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC3          *((volatile unsigned int*)(0x42C8106CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC4          *((volatile unsigned int*)(0x42C81070UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC5          *((volatile unsigned int*)(0x42C81074UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_SA            *((volatile unsigned int*)(0x42C81078UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_AE            *((volatile unsigned int*)(0x42C8107CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A0            *((volatile unsigned int*)(0x42C81080UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A1            *((volatile unsigned int*)(0x42C81084UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A2            *((volatile unsigned int*)(0x42C81088UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A3            *((volatile unsigned int*)(0x42C8108CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A4            *((volatile unsigned int*)(0x42C81090UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A5            *((volatile unsigned int*)(0x42C81094UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A6            *((volatile unsigned int*)(0x42C81098UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A7            *((volatile unsigned int*)(0x42C8109CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A8            *((volatile unsigned int*)(0x42C810A0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A9            *((volatile unsigned int*)(0x42C810A4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A10           *((volatile unsigned int*)(0x42C810A8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A11           *((volatile unsigned int*)(0x42C810ACUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A12           *((volatile unsigned int*)(0x42C810B0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A13           *((volatile unsigned int*)(0x42C810B4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A14           *((volatile unsigned int*)(0x42C810B8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A15           *((volatile unsigned int*)(0x42C810BCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A16           *((volatile unsigned int*)(0x42C810C0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A17           *((volatile unsigned int*)(0x42C810C4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A18           *((volatile unsigned int*)(0x42C810C8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A19           *((volatile unsigned int*)(0x42C810CCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A20           *((volatile unsigned int*)(0x42C810D0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A21           *((volatile unsigned int*)(0x42C810D4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A22           *((volatile unsigned int*)(0x42C810D8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A23           *((volatile unsigned int*)(0x42C810DCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A24           *((volatile unsigned int*)(0x42C810E0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A25           *((volatile unsigned int*)(0x42C810E4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A26           *((volatile unsigned int*)(0x42C810E8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A27           *((volatile unsigned int*)(0x42C810ECUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A28           *((volatile unsigned int*)(0x42C810F0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A29           *((volatile unsigned int*)(0x42C810F4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A30           *((volatile unsigned int*)(0x42C810F8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A31           *((volatile unsigned int*)(0x42C810FCUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A32           *((volatile unsigned int*)(0x42C81100UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A33           *((volatile unsigned int*)(0x42C81104UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A34           *((volatile unsigned int*)(0x42C81108UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A35           *((volatile unsigned int*)(0x42C8110CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A36           *((volatile unsigned int*)(0x42C81110UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A37           *((volatile unsigned int*)(0x42C81114UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A38           *((volatile unsigned int*)(0x42C81118UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A39           *((volatile unsigned int*)(0x42C8111CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A40           *((volatile unsigned int*)(0x42C81120UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A41           *((volatile unsigned int*)(0x42C81124UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A42           *((volatile unsigned int*)(0x42C81128UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A43           *((volatile unsigned int*)(0x42C8112CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A44           *((volatile unsigned int*)(0x42C81130UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A45           *((volatile unsigned int*)(0x42C81134UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A46           *((volatile unsigned int*)(0x42C81138UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A47           *((volatile unsigned int*)(0x42C8113CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC0          *((volatile unsigned int*)(0x42C81160UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC1          *((volatile unsigned int*)(0x42C81164UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC2          *((volatile unsigned int*)(0x42C81168UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC3          *((volatile unsigned int*)(0x42C8116CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC4          *((volatile unsigned int*)(0x42C81170UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC5          *((volatile unsigned int*)(0x42C81174UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_SA            *((volatile unsigned int*)(0x42C81178UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_AE            *((volatile unsigned int*)(0x42C8117CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A0            *((volatile unsigned int*)(0x42C81180UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A1            *((volatile unsigned int*)(0x42C81184UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A2            *((volatile unsigned int*)(0x42C81188UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A3            *((volatile unsigned int*)(0x42C8118CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A4            *((volatile unsigned int*)(0x42C81190UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A5            *((volatile unsigned int*)(0x42C81194UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A6            *((volatile unsigned int*)(0x42C81198UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A7            *((volatile unsigned int*)(0x42C8119CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A8            *((volatile unsigned int*)(0x42C811A0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A9            *((volatile unsigned int*)(0x42C811A4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A10           *((volatile unsigned int*)(0x42C811A8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A11           *((volatile unsigned int*)(0x42C811ACUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A12           *((volatile unsigned int*)(0x42C811B0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A13           *((volatile unsigned int*)(0x42C811B4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A14           *((volatile unsigned int*)(0x42C811B8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A15           *((volatile unsigned int*)(0x42C811BCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A16           *((volatile unsigned int*)(0x42C811C0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A17           *((volatile unsigned int*)(0x42C811C4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A18           *((volatile unsigned int*)(0x42C811C8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A19           *((volatile unsigned int*)(0x42C811CCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A20           *((volatile unsigned int*)(0x42C811D0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A21           *((volatile unsigned int*)(0x42C811D4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A22           *((volatile unsigned int*)(0x42C811D8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A23           *((volatile unsigned int*)(0x42C811DCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A24           *((volatile unsigned int*)(0x42C811E0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A25           *((volatile unsigned int*)(0x42C811E4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A26           *((volatile unsigned int*)(0x42C811E8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A27           *((volatile unsigned int*)(0x42C811ECUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A28           *((volatile unsigned int*)(0x42C811F0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A29           *((volatile unsigned int*)(0x42C811F4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A30           *((volatile unsigned int*)(0x42C811F8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A31           *((volatile unsigned int*)(0x42C811FCUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A32          *((volatile unsigned int*)(0x42C81200UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A33          *((volatile unsigned int*)(0x42C81204UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A34          *((volatile unsigned int*)(0x42C81208UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A35          *((volatile unsigned int*)(0x42C8120CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A36          *((volatile unsigned int*)(0x42C81210UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A37          *((volatile unsigned int*)(0x42C81214UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A38          *((volatile unsigned int*)(0x42C81218UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A39          *((volatile unsigned int*)(0x42C8121CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A40          *((volatile unsigned int*)(0x42C81220UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A41          *((volatile unsigned int*)(0x42C81224UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A42          *((volatile unsigned int*)(0x42C81228UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A43          *((volatile unsigned int*)(0x42C8122CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A44          *((volatile unsigned int*)(0x42C81230UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A45          *((volatile unsigned int*)(0x42C81234UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A46          *((volatile unsigned int*)(0x42C81238UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A47          *((volatile unsigned int*)(0x42C8123CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC0         *((volatile unsigned int*)(0x42C81260UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC1         *((volatile unsigned int*)(0x42C81264UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC2         *((volatile unsigned int*)(0x42C81268UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC3         *((volatile unsigned int*)(0x42C8126CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC4         *((volatile unsigned int*)(0x42C81270UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC5         *((volatile unsigned int*)(0x42C81274UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_SA           *((volatile unsigned int*)(0x42C81278UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_AE           *((volatile unsigned int*)(0x42C8127CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A0           *((volatile unsigned int*)(0x42C81280UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A1           *((volatile unsigned int*)(0x42C81284UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A2           *((volatile unsigned int*)(0x42C81288UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A3           *((volatile unsigned int*)(0x42C8128CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A4           *((volatile unsigned int*)(0x42C81290UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A5           *((volatile unsigned int*)(0x42C81294UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A6           *((volatile unsigned int*)(0x42C81298UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A7           *((volatile unsigned int*)(0x42C8129CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A8           *((volatile unsigned int*)(0x42C812A0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A9           *((volatile unsigned int*)(0x42C812A4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A10          *((volatile unsigned int*)(0x42C812A8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A11          *((volatile unsigned int*)(0x42C812ACUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A12          *((volatile unsigned int*)(0x42C812B0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A13          *((volatile unsigned int*)(0x42C812B4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A14          *((volatile unsigned int*)(0x42C812B8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A15          *((volatile unsigned int*)(0x42C812BCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A16          *((volatile unsigned int*)(0x42C812C0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A17          *((volatile unsigned int*)(0x42C812C4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A18          *((volatile unsigned int*)(0x42C812C8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A19          *((volatile unsigned int*)(0x42C812CCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A20          *((volatile unsigned int*)(0x42C812D0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A21          *((volatile unsigned int*)(0x42C812D4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A22          *((volatile unsigned int*)(0x42C812D8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A23          *((volatile unsigned int*)(0x42C812DCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A24          *((volatile unsigned int*)(0x42C812E0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A25          *((volatile unsigned int*)(0x42C812E4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A26          *((volatile unsigned int*)(0x42C812E8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A27          *((volatile unsigned int*)(0x42C812ECUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A28          *((volatile unsigned int*)(0x42C812F0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A29          *((volatile unsigned int*)(0x42C812F4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A30          *((volatile unsigned int*)(0x42C812F8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A31          *((volatile unsigned int*)(0x42C812FCUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A32          *((volatile unsigned int*)(0x42C81300UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A33          *((volatile unsigned int*)(0x42C81304UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A34          *((volatile unsigned int*)(0x42C81308UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A35          *((volatile unsigned int*)(0x42C8130CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A36          *((volatile unsigned int*)(0x42C81310UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A37          *((volatile unsigned int*)(0x42C81314UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A38          *((volatile unsigned int*)(0x42C81318UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A39          *((volatile unsigned int*)(0x42C8131CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A40          *((volatile unsigned int*)(0x42C81320UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A41          *((volatile unsigned int*)(0x42C81324UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A42          *((volatile unsigned int*)(0x42C81328UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A43          *((volatile unsigned int*)(0x42C8132CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A44          *((volatile unsigned int*)(0x42C81330UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A45          *((volatile unsigned int*)(0x42C81334UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A46          *((volatile unsigned int*)(0x42C81338UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A47          *((volatile unsigned int*)(0x42C8133CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC0         *((volatile unsigned int*)(0x42C81360UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC1         *((volatile unsigned int*)(0x42C81364UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC2         *((volatile unsigned int*)(0x42C81368UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC3         *((volatile unsigned int*)(0x42C8136CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC4         *((volatile unsigned int*)(0x42C81370UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC5         *((volatile unsigned int*)(0x42C81374UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_SA           *((volatile unsigned int*)(0x42C81378UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_AE           *((volatile unsigned int*)(0x42C8137CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A0           *((volatile unsigned int*)(0x42C81380UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A1           *((volatile unsigned int*)(0x42C81384UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A2           *((volatile unsigned int*)(0x42C81388UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A3           *((volatile unsigned int*)(0x42C8138CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A4           *((volatile unsigned int*)(0x42C81390UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A5           *((volatile unsigned int*)(0x42C81394UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A6           *((volatile unsigned int*)(0x42C81398UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A7           *((volatile unsigned int*)(0x42C8139CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A8           *((volatile unsigned int*)(0x42C813A0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A9           *((volatile unsigned int*)(0x42C813A4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A10          *((volatile unsigned int*)(0x42C813A8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A11          *((volatile unsigned int*)(0x42C813ACUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A12          *((volatile unsigned int*)(0x42C813B0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A13          *((volatile unsigned int*)(0x42C813B4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A14          *((volatile unsigned int*)(0x42C813B8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A15          *((volatile unsigned int*)(0x42C813BCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A16          *((volatile unsigned int*)(0x42C813C0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A17          *((volatile unsigned int*)(0x42C813C4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A18          *((volatile unsigned int*)(0x42C813C8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A19          *((volatile unsigned int*)(0x42C813CCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A20          *((volatile unsigned int*)(0x42C813D0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A21          *((volatile unsigned int*)(0x42C813D4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A22          *((volatile unsigned int*)(0x42C813D8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A23          *((volatile unsigned int*)(0x42C813DCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A24          *((volatile unsigned int*)(0x42C813E0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A25          *((volatile unsigned int*)(0x42C813E4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A26          *((volatile unsigned int*)(0x42C813E8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A27          *((volatile unsigned int*)(0x42C813ECUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A28          *((volatile unsigned int*)(0x42C813F0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A29          *((volatile unsigned int*)(0x42C813F4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A30          *((volatile unsigned int*)(0x42C813F8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A31          *((volatile unsigned int*)(0x42C813FCUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A32          *((volatile unsigned int*)(0x42C81400UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A33          *((volatile unsigned int*)(0x42C81404UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A34          *((volatile unsigned int*)(0x42C81408UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A35          *((volatile unsigned int*)(0x42C8140CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A36          *((volatile unsigned int*)(0x42C81410UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A37          *((volatile unsigned int*)(0x42C81414UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A38          *((volatile unsigned int*)(0x42C81418UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A39          *((volatile unsigned int*)(0x42C8141CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A40          *((volatile unsigned int*)(0x42C81420UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A41          *((volatile unsigned int*)(0x42C81424UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A42          *((volatile unsigned int*)(0x42C81428UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A43          *((volatile unsigned int*)(0x42C8142CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A44          *((volatile unsigned int*)(0x42C81430UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A45          *((volatile unsigned int*)(0x42C81434UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A46          *((volatile unsigned int*)(0x42C81438UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A47          *((volatile unsigned int*)(0x42C8143CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC0         *((volatile unsigned int*)(0x42C81460UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC1         *((volatile unsigned int*)(0x42C81464UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC2         *((volatile unsigned int*)(0x42C81468UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC3         *((volatile unsigned int*)(0x42C8146CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC4         *((volatile unsigned int*)(0x42C81470UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC5         *((volatile unsigned int*)(0x42C81474UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_SA           *((volatile unsigned int*)(0x42C81478UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_AE           *((volatile unsigned int*)(0x42C8147CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A0           *((volatile unsigned int*)(0x42C81480UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A1           *((volatile unsigned int*)(0x42C81484UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A2           *((volatile unsigned int*)(0x42C81488UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A3           *((volatile unsigned int*)(0x42C8148CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A4           *((volatile unsigned int*)(0x42C81490UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A5           *((volatile unsigned int*)(0x42C81494UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A6           *((volatile unsigned int*)(0x42C81498UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A7           *((volatile unsigned int*)(0x42C8149CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A8           *((volatile unsigned int*)(0x42C814A0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A9           *((volatile unsigned int*)(0x42C814A4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A10          *((volatile unsigned int*)(0x42C814A8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A11          *((volatile unsigned int*)(0x42C814ACUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A12          *((volatile unsigned int*)(0x42C814B0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A13          *((volatile unsigned int*)(0x42C814B4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A14          *((volatile unsigned int*)(0x42C814B8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A15          *((volatile unsigned int*)(0x42C814BCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A16          *((volatile unsigned int*)(0x42C814C0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A17          *((volatile unsigned int*)(0x42C814C4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A18          *((volatile unsigned int*)(0x42C814C8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A19          *((volatile unsigned int*)(0x42C814CCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A20          *((volatile unsigned int*)(0x42C814D0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A21          *((volatile unsigned int*)(0x42C814D4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A22          *((volatile unsigned int*)(0x42C814D8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A23          *((volatile unsigned int*)(0x42C814DCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A24          *((volatile unsigned int*)(0x42C814E0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A25          *((volatile unsigned int*)(0x42C814E4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A26          *((volatile unsigned int*)(0x42C814E8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A27          *((volatile unsigned int*)(0x42C814ECUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A28          *((volatile unsigned int*)(0x42C814F0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A29          *((volatile unsigned int*)(0x42C814F4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A30          *((volatile unsigned int*)(0x42C814F8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A31          *((volatile unsigned int*)(0x42C814FCUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A32          *((volatile unsigned int*)(0x42C81500UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A33          *((volatile unsigned int*)(0x42C81504UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A34          *((volatile unsigned int*)(0x42C81508UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A35          *((volatile unsigned int*)(0x42C8150CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A36          *((volatile unsigned int*)(0x42C81510UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A37          *((volatile unsigned int*)(0x42C81514UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A38          *((volatile unsigned int*)(0x42C81518UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A39          *((volatile unsigned int*)(0x42C8151CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A40          *((volatile unsigned int*)(0x42C81520UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A41          *((volatile unsigned int*)(0x42C81524UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A42          *((volatile unsigned int*)(0x42C81528UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A43          *((volatile unsigned int*)(0x42C8152CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A44          *((volatile unsigned int*)(0x42C81530UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A45          *((volatile unsigned int*)(0x42C81534UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A46          *((volatile unsigned int*)(0x42C81538UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A47          *((volatile unsigned int*)(0x42C8153CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC0         *((volatile unsigned int*)(0x42C81560UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC1         *((volatile unsigned int*)(0x42C81564UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC2         *((volatile unsigned int*)(0x42C81568UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC3         *((volatile unsigned int*)(0x42C8156CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC4         *((volatile unsigned int*)(0x42C81570UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC5         *((volatile unsigned int*)(0x42C81574UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_SA           *((volatile unsigned int*)(0x42C81578UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_AE           *((volatile unsigned int*)(0x42C8157CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A0           *((volatile unsigned int*)(0x42C81580UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A1           *((volatile unsigned int*)(0x42C81584UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A2           *((volatile unsigned int*)(0x42C81588UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A3           *((volatile unsigned int*)(0x42C8158CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A4           *((volatile unsigned int*)(0x42C81590UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A5           *((volatile unsigned int*)(0x42C81594UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A6           *((volatile unsigned int*)(0x42C81598UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A7           *((volatile unsigned int*)(0x42C8159CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A8           *((volatile unsigned int*)(0x42C815A0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A9           *((volatile unsigned int*)(0x42C815A4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A10          *((volatile unsigned int*)(0x42C815A8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A11          *((volatile unsigned int*)(0x42C815ACUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A12          *((volatile unsigned int*)(0x42C815B0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A13          *((volatile unsigned int*)(0x42C815B4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A14          *((volatile unsigned int*)(0x42C815B8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A15          *((volatile unsigned int*)(0x42C815BCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A16          *((volatile unsigned int*)(0x42C815C0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A17          *((volatile unsigned int*)(0x42C815C4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A18          *((volatile unsigned int*)(0x42C815C8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A19          *((volatile unsigned int*)(0x42C815CCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A20          *((volatile unsigned int*)(0x42C815D0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A21          *((volatile unsigned int*)(0x42C815D4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A22          *((volatile unsigned int*)(0x42C815D8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A23          *((volatile unsigned int*)(0x42C815DCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A24          *((volatile unsigned int*)(0x42C815E0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A25          *((volatile unsigned int*)(0x42C815E4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A26          *((volatile unsigned int*)(0x42C815E8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A27          *((volatile unsigned int*)(0x42C815ECUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A28          *((volatile unsigned int*)(0x42C815F0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A29          *((volatile unsigned int*)(0x42C815F4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A30          *((volatile unsigned int*)(0x42C815F8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A31          *((volatile unsigned int*)(0x42C815FCUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A32          *((volatile unsigned int*)(0x42C81600UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A33          *((volatile unsigned int*)(0x42C81604UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A34          *((volatile unsigned int*)(0x42C81608UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A35          *((volatile unsigned int*)(0x42C8160CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A36          *((volatile unsigned int*)(0x42C81610UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A37          *((volatile unsigned int*)(0x42C81614UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A38          *((volatile unsigned int*)(0x42C81618UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A39          *((volatile unsigned int*)(0x42C8161CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A40          *((volatile unsigned int*)(0x42C81620UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A41          *((volatile unsigned int*)(0x42C81624UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A42          *((volatile unsigned int*)(0x42C81628UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A43          *((volatile unsigned int*)(0x42C8162CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A44          *((volatile unsigned int*)(0x42C81630UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A45          *((volatile unsigned int*)(0x42C81634UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A46          *((volatile unsigned int*)(0x42C81638UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A47          *((volatile unsigned int*)(0x42C8163CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC0         *((volatile unsigned int*)(0x42C81660UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC1         *((volatile unsigned int*)(0x42C81664UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC2         *((volatile unsigned int*)(0x42C81668UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC3         *((volatile unsigned int*)(0x42C8166CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC4         *((volatile unsigned int*)(0x42C81670UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC5         *((volatile unsigned int*)(0x42C81674UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_SA           *((volatile unsigned int*)(0x42C81678UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_AE           *((volatile unsigned int*)(0x42C8167CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A0           *((volatile unsigned int*)(0x42C81680UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A1           *((volatile unsigned int*)(0x42C81684UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A2           *((volatile unsigned int*)(0x42C81688UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A3           *((volatile unsigned int*)(0x42C8168CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A4           *((volatile unsigned int*)(0x42C81690UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A5           *((volatile unsigned int*)(0x42C81694UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A6           *((volatile unsigned int*)(0x42C81698UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A7           *((volatile unsigned int*)(0x42C8169CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A8           *((volatile unsigned int*)(0x42C816A0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A9           *((volatile unsigned int*)(0x42C816A4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A10          *((volatile unsigned int*)(0x42C816A8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A11          *((volatile unsigned int*)(0x42C816ACUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A12          *((volatile unsigned int*)(0x42C816B0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A13          *((volatile unsigned int*)(0x42C816B4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A14          *((volatile unsigned int*)(0x42C816B8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A15          *((volatile unsigned int*)(0x42C816BCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A16          *((volatile unsigned int*)(0x42C816C0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A17          *((volatile unsigned int*)(0x42C816C4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A18          *((volatile unsigned int*)(0x42C816C8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A19          *((volatile unsigned int*)(0x42C816CCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A20          *((volatile unsigned int*)(0x42C816D0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A21          *((volatile unsigned int*)(0x42C816D4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A22          *((volatile unsigned int*)(0x42C816D8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A23          *((volatile unsigned int*)(0x42C816DCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A24          *((volatile unsigned int*)(0x42C816E0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A25          *((volatile unsigned int*)(0x42C816E4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A26          *((volatile unsigned int*)(0x42C816E8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A27          *((volatile unsigned int*)(0x42C816ECUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A28          *((volatile unsigned int*)(0x42C816F0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A29          *((volatile unsigned int*)(0x42C816F4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A30          *((volatile unsigned int*)(0x42C816F8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A31          *((volatile unsigned int*)(0x42C816FCUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A32          *((volatile unsigned int*)(0x42C81700UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A33          *((volatile unsigned int*)(0x42C81704UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A34          *((volatile unsigned int*)(0x42C81708UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A35          *((volatile unsigned int*)(0x42C8170CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A36          *((volatile unsigned int*)(0x42C81710UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A37          *((volatile unsigned int*)(0x42C81714UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A38          *((volatile unsigned int*)(0x42C81718UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A39          *((volatile unsigned int*)(0x42C8171CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A40          *((volatile unsigned int*)(0x42C81720UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A41          *((volatile unsigned int*)(0x42C81724UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A42          *((volatile unsigned int*)(0x42C81728UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A43          *((volatile unsigned int*)(0x42C8172CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A44          *((volatile unsigned int*)(0x42C81730UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A45          *((volatile unsigned int*)(0x42C81734UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A46          *((volatile unsigned int*)(0x42C81738UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A47          *((volatile unsigned int*)(0x42C8173CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC0         *((volatile unsigned int*)(0x42C81760UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC1         *((volatile unsigned int*)(0x42C81764UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC2         *((volatile unsigned int*)(0x42C81768UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC3         *((volatile unsigned int*)(0x42C8176CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC4         *((volatile unsigned int*)(0x42C81770UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC5         *((volatile unsigned int*)(0x42C81774UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_SA           *((volatile unsigned int*)(0x42C81778UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_AE           *((volatile unsigned int*)(0x42C8177CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A0           *((volatile unsigned int*)(0x42C81780UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A1           *((volatile unsigned int*)(0x42C81784UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A2           *((volatile unsigned int*)(0x42C81788UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A3           *((volatile unsigned int*)(0x42C8178CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A4           *((volatile unsigned int*)(0x42C81790UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A5           *((volatile unsigned int*)(0x42C81794UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A6           *((volatile unsigned int*)(0x42C81798UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A7           *((volatile unsigned int*)(0x42C8179CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A8           *((volatile unsigned int*)(0x42C817A0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A9           *((volatile unsigned int*)(0x42C817A4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A10          *((volatile unsigned int*)(0x42C817A8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A11          *((volatile unsigned int*)(0x42C817ACUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A12          *((volatile unsigned int*)(0x42C817B0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A13          *((volatile unsigned int*)(0x42C817B4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A14          *((volatile unsigned int*)(0x42C817B8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A15          *((volatile unsigned int*)(0x42C817BCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A16          *((volatile unsigned int*)(0x42C817C0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A17          *((volatile unsigned int*)(0x42C817C4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A18          *((volatile unsigned int*)(0x42C817C8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A19          *((volatile unsigned int*)(0x42C817CCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A20          *((volatile unsigned int*)(0x42C817D0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A21          *((volatile unsigned int*)(0x42C817D4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A22          *((volatile unsigned int*)(0x42C817D8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A23          *((volatile unsigned int*)(0x42C817DCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A24          *((volatile unsigned int*)(0x42C817E0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A25          *((volatile unsigned int*)(0x42C817E4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A26          *((volatile unsigned int*)(0x42C817E8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A27          *((volatile unsigned int*)(0x42C817ECUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A28          *((volatile unsigned int*)(0x42C817F0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A29          *((volatile unsigned int*)(0x42C817F4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A30          *((volatile unsigned int*)(0x42C817F8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A31          *((volatile unsigned int*)(0x42C817FCUL))
+#define bFM3_ETHERNET_MAC0_RGSR_LM             *((volatile unsigned int*)(0x42C81B00UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP0           *((volatile unsigned int*)(0x42C81B04UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP1           *((volatile unsigned int*)(0x42C81B08UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LS             *((volatile unsigned int*)(0x42C81B0CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSE            *((volatile unsigned int*)(0x42C8E000UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TFCU           *((volatile unsigned int*)(0x42C8E004UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSI            *((volatile unsigned int*)(0x42C8E008UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSU            *((volatile unsigned int*)(0x42C8E00CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TITE           *((volatile unsigned int*)(0x42C8E010UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TARU           *((volatile unsigned int*)(0x42C8E014UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSEA           *((volatile unsigned int*)(0x42C8E020UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSDB           *((volatile unsigned int*)(0x42C8E024UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSV2E          *((volatile unsigned int*)(0x42C8E028UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSP          *((volatile unsigned int*)(0x42C8E02CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E         *((volatile unsigned int*)(0x42C8E030UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E         *((volatile unsigned int*)(0x42C8E034UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSEM         *((volatile unsigned int*)(0x42C8E038UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSMRM          *((volatile unsigned int*)(0x42C8E03CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS0          *((volatile unsigned int*)(0x42C8E040UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS1          *((volatile unsigned int*)(0x42C8E044UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSENMF         *((volatile unsigned int*)(0x42C8E048UL))
+#define bFM3_ETHERNET_MAC0_TSCR_ATSFC          *((volatile unsigned int*)(0x42C8E060UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC0         *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC1         *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC2         *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC3         *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC4         *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC5         *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC6         *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC7         *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS0           *((volatile unsigned int*)(0x42C8E100UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS1           *((volatile unsigned int*)(0x42C8E104UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS2           *((volatile unsigned int*)(0x42C8E108UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS3           *((volatile unsigned int*)(0x42C8E10CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS4           *((volatile unsigned int*)(0x42C8E110UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS5           *((volatile unsigned int*)(0x42C8E114UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS6           *((volatile unsigned int*)(0x42C8E118UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS7           *((volatile unsigned int*)(0x42C8E11CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS8           *((volatile unsigned int*)(0x42C8E120UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS9           *((volatile unsigned int*)(0x42C8E124UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS10          *((volatile unsigned int*)(0x42C8E128UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS11          *((volatile unsigned int*)(0x42C8E12CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS12          *((volatile unsigned int*)(0x42C8E130UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS13          *((volatile unsigned int*)(0x42C8E134UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS14          *((volatile unsigned int*)(0x42C8E138UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS15          *((volatile unsigned int*)(0x42C8E13CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS16          *((volatile unsigned int*)(0x42C8E140UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS17          *((volatile unsigned int*)(0x42C8E144UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS18          *((volatile unsigned int*)(0x42C8E148UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS19          *((volatile unsigned int*)(0x42C8E14CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS20          *((volatile unsigned int*)(0x42C8E150UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS21          *((volatile unsigned int*)(0x42C8E154UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS22          *((volatile unsigned int*)(0x42C8E158UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS23          *((volatile unsigned int*)(0x42C8E15CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS24          *((volatile unsigned int*)(0x42C8E160UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS25          *((volatile unsigned int*)(0x42C8E164UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS26          *((volatile unsigned int*)(0x42C8E168UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS27          *((volatile unsigned int*)(0x42C8E16CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS28          *((volatile unsigned int*)(0x42C8E170UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS29          *((volatile unsigned int*)(0x42C8E174UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS30          *((volatile unsigned int*)(0x42C8E178UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS31          *((volatile unsigned int*)(0x42C8E17CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS0          *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS1          *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS2          *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS3          *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS4          *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS5          *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS6          *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS7          *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS8          *((volatile unsigned int*)(0x42C8E0A0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS9          *((volatile unsigned int*)(0x42C8E0A4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS10         *((volatile unsigned int*)(0x42C8E0A8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS11         *((volatile unsigned int*)(0x42C8E0ACUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS12         *((volatile unsigned int*)(0x42C8E0B0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS13         *((volatile unsigned int*)(0x42C8E0B4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS14         *((volatile unsigned int*)(0x42C8E0B8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS15         *((volatile unsigned int*)(0x42C8E0BCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS16         *((volatile unsigned int*)(0x42C8E0C0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS17         *((volatile unsigned int*)(0x42C8E0C4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS18         *((volatile unsigned int*)(0x42C8E0C8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS19         *((volatile unsigned int*)(0x42C8E0CCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS20         *((volatile unsigned int*)(0x42C8E0D0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS21         *((volatile unsigned int*)(0x42C8E0D4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS22         *((volatile unsigned int*)(0x42C8E0D8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS23         *((volatile unsigned int*)(0x42C8E0DCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS24         *((volatile unsigned int*)(0x42C8E0E0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS25         *((volatile unsigned int*)(0x42C8E0E4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS26         *((volatile unsigned int*)(0x42C8E0E8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS27         *((volatile unsigned int*)(0x42C8E0ECUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS28         *((volatile unsigned int*)(0x42C8E0F0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS29         *((volatile unsigned int*)(0x42C8E0F4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS30         *((volatile unsigned int*)(0x42C8E0F8UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS0          *((volatile unsigned int*)(0x42C8E200UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS1          *((volatile unsigned int*)(0x42C8E204UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS2          *((volatile unsigned int*)(0x42C8E208UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS3          *((volatile unsigned int*)(0x42C8E20CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS4          *((volatile unsigned int*)(0x42C8E210UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS5          *((volatile unsigned int*)(0x42C8E214UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS6          *((volatile unsigned int*)(0x42C8E218UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS7          *((volatile unsigned int*)(0x42C8E21CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS8          *((volatile unsigned int*)(0x42C8E220UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS9          *((volatile unsigned int*)(0x42C8E224UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS10         *((volatile unsigned int*)(0x42C8E228UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS11         *((volatile unsigned int*)(0x42C8E22CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS12         *((volatile unsigned int*)(0x42C8E230UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS13         *((volatile unsigned int*)(0x42C8E234UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS14         *((volatile unsigned int*)(0x42C8E238UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS15         *((volatile unsigned int*)(0x42C8E23CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS16         *((volatile unsigned int*)(0x42C8E240UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS17         *((volatile unsigned int*)(0x42C8E244UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS18         *((volatile unsigned int*)(0x42C8E248UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS19         *((volatile unsigned int*)(0x42C8E24CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS20         *((volatile unsigned int*)(0x42C8E250UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS21         *((volatile unsigned int*)(0x42C8E254UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS22         *((volatile unsigned int*)(0x42C8E258UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS23         *((volatile unsigned int*)(0x42C8E25CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS24         *((volatile unsigned int*)(0x42C8E260UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS25         *((volatile unsigned int*)(0x42C8E264UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS26         *((volatile unsigned int*)(0x42C8E268UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS27         *((volatile unsigned int*)(0x42C8E26CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS28         *((volatile unsigned int*)(0x42C8E270UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS29         *((volatile unsigned int*)(0x42C8E274UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS30         *((volatile unsigned int*)(0x42C8E278UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS31         *((volatile unsigned int*)(0x42C8E27CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS0         *((volatile unsigned int*)(0x42C8E280UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS1         *((volatile unsigned int*)(0x42C8E284UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS2         *((volatile unsigned int*)(0x42C8E288UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS3         *((volatile unsigned int*)(0x42C8E28CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS4         *((volatile unsigned int*)(0x42C8E290UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS5         *((volatile unsigned int*)(0x42C8E294UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS6         *((volatile unsigned int*)(0x42C8E298UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS7         *((volatile unsigned int*)(0x42C8E29CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS8         *((volatile unsigned int*)(0x42C8E2A0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS9         *((volatile unsigned int*)(0x42C8E2A4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS10        *((volatile unsigned int*)(0x42C8E2A8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS11        *((volatile unsigned int*)(0x42C8E2ACUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS12        *((volatile unsigned int*)(0x42C8E2B0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS13        *((volatile unsigned int*)(0x42C8E2B4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS14        *((volatile unsigned int*)(0x42C8E2B8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS15        *((volatile unsigned int*)(0x42C8E2BCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS16        *((volatile unsigned int*)(0x42C8E2C0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS17        *((volatile unsigned int*)(0x42C8E2C4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS18        *((volatile unsigned int*)(0x42C8E2C8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS19        *((volatile unsigned int*)(0x42C8E2CCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS20        *((volatile unsigned int*)(0x42C8E2D0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS21        *((volatile unsigned int*)(0x42C8E2D4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS22        *((volatile unsigned int*)(0x42C8E2D8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS23        *((volatile unsigned int*)(0x42C8E2DCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS24        *((volatile unsigned int*)(0x42C8E2E0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS25        *((volatile unsigned int*)(0x42C8E2E4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS26        *((volatile unsigned int*)(0x42C8E2E8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS27        *((volatile unsigned int*)(0x42C8E2ECUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS28        *((volatile unsigned int*)(0x42C8E2F0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS29        *((volatile unsigned int*)(0x42C8E2F4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS30        *((volatile unsigned int*)(0x42C8E2F8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB        *((volatile unsigned int*)(0x42C8E2FCUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR0          *((volatile unsigned int*)(0x42C8E300UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR1          *((volatile unsigned int*)(0x42C8E304UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR2          *((volatile unsigned int*)(0x42C8E308UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR3          *((volatile unsigned int*)(0x42C8E30CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR4          *((volatile unsigned int*)(0x42C8E310UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR5          *((volatile unsigned int*)(0x42C8E314UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR6          *((volatile unsigned int*)(0x42C8E318UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR7          *((volatile unsigned int*)(0x42C8E31CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR8          *((volatile unsigned int*)(0x42C8E320UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR9          *((volatile unsigned int*)(0x42C8E324UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR10         *((volatile unsigned int*)(0x42C8E328UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR11         *((volatile unsigned int*)(0x42C8E32CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR12         *((volatile unsigned int*)(0x42C8E330UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR13         *((volatile unsigned int*)(0x42C8E334UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR14         *((volatile unsigned int*)(0x42C8E338UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR15         *((volatile unsigned int*)(0x42C8E33CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR16         *((volatile unsigned int*)(0x42C8E340UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR17         *((volatile unsigned int*)(0x42C8E344UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR18         *((volatile unsigned int*)(0x42C8E348UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR19         *((volatile unsigned int*)(0x42C8E34CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR20         *((volatile unsigned int*)(0x42C8E350UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR21         *((volatile unsigned int*)(0x42C8E354UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR22         *((volatile unsigned int*)(0x42C8E358UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR23         *((volatile unsigned int*)(0x42C8E35CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR24         *((volatile unsigned int*)(0x42C8E360UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR25         *((volatile unsigned int*)(0x42C8E364UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR26         *((volatile unsigned int*)(0x42C8E368UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR27         *((volatile unsigned int*)(0x42C8E36CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR28         *((volatile unsigned int*)(0x42C8E370UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR29         *((volatile unsigned int*)(0x42C8E374UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR30         *((volatile unsigned int*)(0x42C8E378UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR31         *((volatile unsigned int*)(0x42C8E37CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR0          *((volatile unsigned int*)(0x42C8E380UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR1          *((volatile unsigned int*)(0x42C8E384UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR2          *((volatile unsigned int*)(0x42C8E388UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR3          *((volatile unsigned int*)(0x42C8E38CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR4          *((volatile unsigned int*)(0x42C8E390UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR5          *((volatile unsigned int*)(0x42C8E394UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR6          *((volatile unsigned int*)(0x42C8E398UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR7          *((volatile unsigned int*)(0x42C8E39CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR8          *((volatile unsigned int*)(0x42C8E3A0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR9          *((volatile unsigned int*)(0x42C8E3A4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR10         *((volatile unsigned int*)(0x42C8E3A8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR11         *((volatile unsigned int*)(0x42C8E3ACUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR12         *((volatile unsigned int*)(0x42C8E3B0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR13         *((volatile unsigned int*)(0x42C8E3B4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR14         *((volatile unsigned int*)(0x42C8E3B8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR15         *((volatile unsigned int*)(0x42C8E3BCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR16         *((volatile unsigned int*)(0x42C8E3C0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR17         *((volatile unsigned int*)(0x42C8E3C4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR18         *((volatile unsigned int*)(0x42C8E3C8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR19         *((volatile unsigned int*)(0x42C8E3CCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR20         *((volatile unsigned int*)(0x42C8E3D0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR21         *((volatile unsigned int*)(0x42C8E3D4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR22         *((volatile unsigned int*)(0x42C8E3D8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR23         *((volatile unsigned int*)(0x42C8E3DCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR24         *((volatile unsigned int*)(0x42C8E3E0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR25         *((volatile unsigned int*)(0x42C8E3E4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR26         *((volatile unsigned int*)(0x42C8E3E8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR27         *((volatile unsigned int*)(0x42C8E3ECUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR28         *((volatile unsigned int*)(0x42C8E3F0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR29         *((volatile unsigned int*)(0x42C8E3F4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR30         *((volatile unsigned int*)(0x42C8E3F8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR31         *((volatile unsigned int*)(0x42C8E3FCUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR0          *((volatile unsigned int*)(0x42C8E400UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR1          *((volatile unsigned int*)(0x42C8E404UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR2          *((volatile unsigned int*)(0x42C8E408UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR3          *((volatile unsigned int*)(0x42C8E40CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR4          *((volatile unsigned int*)(0x42C8E410UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR5          *((volatile unsigned int*)(0x42C8E414UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR6          *((volatile unsigned int*)(0x42C8E418UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR7          *((volatile unsigned int*)(0x42C8E41CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR8          *((volatile unsigned int*)(0x42C8E420UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR9          *((volatile unsigned int*)(0x42C8E424UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR10         *((volatile unsigned int*)(0x42C8E428UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR11         *((volatile unsigned int*)(0x42C8E42CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR12         *((volatile unsigned int*)(0x42C8E430UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR13         *((volatile unsigned int*)(0x42C8E434UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR14         *((volatile unsigned int*)(0x42C8E438UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR15         *((volatile unsigned int*)(0x42C8E43CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR16         *((volatile unsigned int*)(0x42C8E440UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR17         *((volatile unsigned int*)(0x42C8E444UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR18         *((volatile unsigned int*)(0x42C8E448UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR19         *((volatile unsigned int*)(0x42C8E44CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR20         *((volatile unsigned int*)(0x42C8E450UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR21         *((volatile unsigned int*)(0x42C8E454UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR22         *((volatile unsigned int*)(0x42C8E458UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR23         *((volatile unsigned int*)(0x42C8E45CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR24         *((volatile unsigned int*)(0x42C8E460UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR25         *((volatile unsigned int*)(0x42C8E464UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR26         *((volatile unsigned int*)(0x42C8E468UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR27         *((volatile unsigned int*)(0x42C8E46CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR28         *((volatile unsigned int*)(0x42C8E470UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR29         *((volatile unsigned int*)(0x42C8E474UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR30         *((volatile unsigned int*)(0x42C8E478UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42C8E480UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42C8E484UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42C8E488UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42C8E48CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42C8E490UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42C8E494UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42C8E498UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42C8E49CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42C8E4A0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42C8E4A4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42C8E4A8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42C8E4ACUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42C8E4B0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42C8E4B4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42C8E4B8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42C8E4BCUL))
+#define bFM3_ETHERNET_MAC0_TSR_TSSOVF          *((volatile unsigned int*)(0x42C8E500UL))
+#define bFM3_ETHERNET_MAC0_TSR_TSTART          *((volatile unsigned int*)(0x42C8E504UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSTS           *((volatile unsigned int*)(0x42C8E508UL))
+#define bFM3_ETHERNET_MAC0_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSSTM          *((volatile unsigned int*)(0x42C8E560UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS0          *((volatile unsigned int*)(0x42C8E564UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS1          *((volatile unsigned int*)(0x42C8E568UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS2          *((volatile unsigned int*)(0x42C8E56CUL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42C8E580UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42C8E584UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42C8E588UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42C8E58CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN0           *((volatile unsigned int*)(0x42C8E600UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN1           *((volatile unsigned int*)(0x42C8E604UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN2           *((volatile unsigned int*)(0x42C8E608UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN3           *((volatile unsigned int*)(0x42C8E60CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN4           *((volatile unsigned int*)(0x42C8E610UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN5           *((volatile unsigned int*)(0x42C8E614UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN6           *((volatile unsigned int*)(0x42C8E618UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN7           *((volatile unsigned int*)(0x42C8E61CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN8           *((volatile unsigned int*)(0x42C8E620UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN9           *((volatile unsigned int*)(0x42C8E624UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN10          *((volatile unsigned int*)(0x42C8E628UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN11          *((volatile unsigned int*)(0x42C8E62CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN12          *((volatile unsigned int*)(0x42C8E630UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN13          *((volatile unsigned int*)(0x42C8E634UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN14          *((volatile unsigned int*)(0x42C8E638UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN15          *((volatile unsigned int*)(0x42C8E63CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN16          *((volatile unsigned int*)(0x42C8E640UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN17          *((volatile unsigned int*)(0x42C8E644UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN18          *((volatile unsigned int*)(0x42C8E648UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN19          *((volatile unsigned int*)(0x42C8E64CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN20          *((volatile unsigned int*)(0x42C8E650UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN21          *((volatile unsigned int*)(0x42C8E654UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN22          *((volatile unsigned int*)(0x42C8E658UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN23          *((volatile unsigned int*)(0x42C8E65CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN24          *((volatile unsigned int*)(0x42C8E660UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN25          *((volatile unsigned int*)(0x42C8E664UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN26          *((volatile unsigned int*)(0x42C8E668UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN27          *((volatile unsigned int*)(0x42C8E66CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN28          *((volatile unsigned int*)(0x42C8E670UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN29          *((volatile unsigned int*)(0x42C8E674UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN30          *((volatile unsigned int*)(0x42C8E678UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS0           *((volatile unsigned int*)(0x42C8E680UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS1           *((volatile unsigned int*)(0x42C8E684UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS2           *((volatile unsigned int*)(0x42C8E688UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS3           *((volatile unsigned int*)(0x42C8E68CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS4           *((volatile unsigned int*)(0x42C8E690UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS5           *((volatile unsigned int*)(0x42C8E694UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS6           *((volatile unsigned int*)(0x42C8E698UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS7           *((volatile unsigned int*)(0x42C8E69CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS8           *((volatile unsigned int*)(0x42C8E6A0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS9           *((volatile unsigned int*)(0x42C8E6A4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS10          *((volatile unsigned int*)(0x42C8E6A8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS11          *((volatile unsigned int*)(0x42C8E6ACUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS12          *((volatile unsigned int*)(0x42C8E6B0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS13          *((volatile unsigned int*)(0x42C8E6B4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS14          *((volatile unsigned int*)(0x42C8E6B8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS15          *((volatile unsigned int*)(0x42C8E6BCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS16          *((volatile unsigned int*)(0x42C8E6C0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS17          *((volatile unsigned int*)(0x42C8E6C4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS18          *((volatile unsigned int*)(0x42C8E6C8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS19          *((volatile unsigned int*)(0x42C8E6CCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS20          *((volatile unsigned int*)(0x42C8E6D0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS21          *((volatile unsigned int*)(0x42C8E6D4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS22          *((volatile unsigned int*)(0x42C8E6D8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS23          *((volatile unsigned int*)(0x42C8E6DCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS24          *((volatile unsigned int*)(0x42C8E6E0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS25          *((volatile unsigned int*)(0x42C8E6E4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS26          *((volatile unsigned int*)(0x42C8E6E8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS27          *((volatile unsigned int*)(0x42C8E6ECUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS28          *((volatile unsigned int*)(0x42C8E6F0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS29          *((volatile unsigned int*)(0x42C8E6F4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS30          *((volatile unsigned int*)(0x42C8E6F8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS31          *((volatile unsigned int*)(0x42C8E6FCUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A32          *((volatile unsigned int*)(0x42C90000UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A33          *((volatile unsigned int*)(0x42C90004UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A34          *((volatile unsigned int*)(0x42C90008UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A35          *((volatile unsigned int*)(0x42C9000CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A36          *((volatile unsigned int*)(0x42C90010UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A37          *((volatile unsigned int*)(0x42C90014UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A38          *((volatile unsigned int*)(0x42C90018UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A39          *((volatile unsigned int*)(0x42C9001CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A40          *((volatile unsigned int*)(0x42C90020UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A41          *((volatile unsigned int*)(0x42C90024UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A42          *((volatile unsigned int*)(0x42C90028UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A43          *((volatile unsigned int*)(0x42C9002CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A44          *((volatile unsigned int*)(0x42C90030UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A45          *((volatile unsigned int*)(0x42C90034UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A46          *((volatile unsigned int*)(0x42C90038UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A47          *((volatile unsigned int*)(0x42C9003CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC0         *((volatile unsigned int*)(0x42C90060UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC1         *((volatile unsigned int*)(0x42C90064UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC2         *((volatile unsigned int*)(0x42C90068UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC3         *((volatile unsigned int*)(0x42C9006CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC4         *((volatile unsigned int*)(0x42C90070UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC5         *((volatile unsigned int*)(0x42C90074UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_SA           *((volatile unsigned int*)(0x42C90078UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_AE           *((volatile unsigned int*)(0x42C9007CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A0           *((volatile unsigned int*)(0x42C90080UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A1           *((volatile unsigned int*)(0x42C90084UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A2           *((volatile unsigned int*)(0x42C90088UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A3           *((volatile unsigned int*)(0x42C9008CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A4           *((volatile unsigned int*)(0x42C90090UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A5           *((volatile unsigned int*)(0x42C90094UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A6           *((volatile unsigned int*)(0x42C90098UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A7           *((volatile unsigned int*)(0x42C9009CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A8           *((volatile unsigned int*)(0x42C900A0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A9           *((volatile unsigned int*)(0x42C900A4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A10          *((volatile unsigned int*)(0x42C900A8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A11          *((volatile unsigned int*)(0x42C900ACUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A12          *((volatile unsigned int*)(0x42C900B0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A13          *((volatile unsigned int*)(0x42C900B4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A14          *((volatile unsigned int*)(0x42C900B8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A15          *((volatile unsigned int*)(0x42C900BCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A16          *((volatile unsigned int*)(0x42C900C0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A17          *((volatile unsigned int*)(0x42C900C4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A18          *((volatile unsigned int*)(0x42C900C8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A19          *((volatile unsigned int*)(0x42C900CCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A20          *((volatile unsigned int*)(0x42C900D0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A21          *((volatile unsigned int*)(0x42C900D4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A22          *((volatile unsigned int*)(0x42C900D8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A23          *((volatile unsigned int*)(0x42C900DCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A24          *((volatile unsigned int*)(0x42C900E0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A25          *((volatile unsigned int*)(0x42C900E4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A26          *((volatile unsigned int*)(0x42C900E8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A27          *((volatile unsigned int*)(0x42C900ECUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A28          *((volatile unsigned int*)(0x42C900F0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A29          *((volatile unsigned int*)(0x42C900F4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A30          *((volatile unsigned int*)(0x42C900F8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A31          *((volatile unsigned int*)(0x42C900FCUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A32          *((volatile unsigned int*)(0x42C90100UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A33          *((volatile unsigned int*)(0x42C90104UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A34          *((volatile unsigned int*)(0x42C90108UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A35          *((volatile unsigned int*)(0x42C9010CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A36          *((volatile unsigned int*)(0x42C90110UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A37          *((volatile unsigned int*)(0x42C90114UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A38          *((volatile unsigned int*)(0x42C90118UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A39          *((volatile unsigned int*)(0x42C9011CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A40          *((volatile unsigned int*)(0x42C90120UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A41          *((volatile unsigned int*)(0x42C90124UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A42          *((volatile unsigned int*)(0x42C90128UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A43          *((volatile unsigned int*)(0x42C9012CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A44          *((volatile unsigned int*)(0x42C90130UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A45          *((volatile unsigned int*)(0x42C90134UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A46          *((volatile unsigned int*)(0x42C90138UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A47          *((volatile unsigned int*)(0x42C9013CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC0         *((volatile unsigned int*)(0x42C90160UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC1         *((volatile unsigned int*)(0x42C90164UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC2         *((volatile unsigned int*)(0x42C90168UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC3         *((volatile unsigned int*)(0x42C9016CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC4         *((volatile unsigned int*)(0x42C90170UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC5         *((volatile unsigned int*)(0x42C90174UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_SA           *((volatile unsigned int*)(0x42C90178UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_AE           *((volatile unsigned int*)(0x42C9017CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A0           *((volatile unsigned int*)(0x42C90180UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A1           *((volatile unsigned int*)(0x42C90184UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A2           *((volatile unsigned int*)(0x42C90188UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A3           *((volatile unsigned int*)(0x42C9018CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A4           *((volatile unsigned int*)(0x42C90190UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A5           *((volatile unsigned int*)(0x42C90194UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A6           *((volatile unsigned int*)(0x42C90198UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A7           *((volatile unsigned int*)(0x42C9019CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A8           *((volatile unsigned int*)(0x42C901A0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A9           *((volatile unsigned int*)(0x42C901A4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A10          *((volatile unsigned int*)(0x42C901A8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A11          *((volatile unsigned int*)(0x42C901ACUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A12          *((volatile unsigned int*)(0x42C901B0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A13          *((volatile unsigned int*)(0x42C901B4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A14          *((volatile unsigned int*)(0x42C901B8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A15          *((volatile unsigned int*)(0x42C901BCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A16          *((volatile unsigned int*)(0x42C901C0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A17          *((volatile unsigned int*)(0x42C901C4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A18          *((volatile unsigned int*)(0x42C901C8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A19          *((volatile unsigned int*)(0x42C901CCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A20          *((volatile unsigned int*)(0x42C901D0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A21          *((volatile unsigned int*)(0x42C901D4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A22          *((volatile unsigned int*)(0x42C901D8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A23          *((volatile unsigned int*)(0x42C901DCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A24          *((volatile unsigned int*)(0x42C901E0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A25          *((volatile unsigned int*)(0x42C901E4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A26          *((volatile unsigned int*)(0x42C901E8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A27          *((volatile unsigned int*)(0x42C901ECUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A28          *((volatile unsigned int*)(0x42C901F0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A29          *((volatile unsigned int*)(0x42C901F4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A30          *((volatile unsigned int*)(0x42C901F8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A31          *((volatile unsigned int*)(0x42C901FCUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A32          *((volatile unsigned int*)(0x42C90200UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A33          *((volatile unsigned int*)(0x42C90204UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A34          *((volatile unsigned int*)(0x42C90208UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A35          *((volatile unsigned int*)(0x42C9020CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A36          *((volatile unsigned int*)(0x42C90210UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A37          *((volatile unsigned int*)(0x42C90214UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A38          *((volatile unsigned int*)(0x42C90218UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A39          *((volatile unsigned int*)(0x42C9021CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A40          *((volatile unsigned int*)(0x42C90220UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A41          *((volatile unsigned int*)(0x42C90224UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A42          *((volatile unsigned int*)(0x42C90228UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A43          *((volatile unsigned int*)(0x42C9022CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A44          *((volatile unsigned int*)(0x42C90230UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A45          *((volatile unsigned int*)(0x42C90234UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A46          *((volatile unsigned int*)(0x42C90238UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A47          *((volatile unsigned int*)(0x42C9023CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC0         *((volatile unsigned int*)(0x42C90260UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC1         *((volatile unsigned int*)(0x42C90264UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC2         *((volatile unsigned int*)(0x42C90268UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC3         *((volatile unsigned int*)(0x42C9026CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC4         *((volatile unsigned int*)(0x42C90270UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC5         *((volatile unsigned int*)(0x42C90274UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_SA           *((volatile unsigned int*)(0x42C90278UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_AE           *((volatile unsigned int*)(0x42C9027CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A0           *((volatile unsigned int*)(0x42C90280UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A1           *((volatile unsigned int*)(0x42C90284UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A2           *((volatile unsigned int*)(0x42C90288UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A3           *((volatile unsigned int*)(0x42C9028CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A4           *((volatile unsigned int*)(0x42C90290UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A5           *((volatile unsigned int*)(0x42C90294UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A6           *((volatile unsigned int*)(0x42C90298UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A7           *((volatile unsigned int*)(0x42C9029CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A8           *((volatile unsigned int*)(0x42C902A0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A9           *((volatile unsigned int*)(0x42C902A4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A10          *((volatile unsigned int*)(0x42C902A8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A11          *((volatile unsigned int*)(0x42C902ACUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A12          *((volatile unsigned int*)(0x42C902B0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A13          *((volatile unsigned int*)(0x42C902B4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A14          *((volatile unsigned int*)(0x42C902B8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A15          *((volatile unsigned int*)(0x42C902BCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A16          *((volatile unsigned int*)(0x42C902C0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A17          *((volatile unsigned int*)(0x42C902C4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A18          *((volatile unsigned int*)(0x42C902C8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A19          *((volatile unsigned int*)(0x42C902CCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A20          *((volatile unsigned int*)(0x42C902D0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A21          *((volatile unsigned int*)(0x42C902D4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A22          *((volatile unsigned int*)(0x42C902D8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A23          *((volatile unsigned int*)(0x42C902DCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A24          *((volatile unsigned int*)(0x42C902E0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A25          *((volatile unsigned int*)(0x42C902E4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A26          *((volatile unsigned int*)(0x42C902E8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A27          *((volatile unsigned int*)(0x42C902ECUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A28          *((volatile unsigned int*)(0x42C902F0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A29          *((volatile unsigned int*)(0x42C902F4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A30          *((volatile unsigned int*)(0x42C902F8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A31          *((volatile unsigned int*)(0x42C902FCUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A32          *((volatile unsigned int*)(0x42C90300UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A33          *((volatile unsigned int*)(0x42C90304UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A34          *((volatile unsigned int*)(0x42C90308UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A35          *((volatile unsigned int*)(0x42C9030CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A36          *((volatile unsigned int*)(0x42C90310UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A37          *((volatile unsigned int*)(0x42C90314UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A38          *((volatile unsigned int*)(0x42C90318UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A39          *((volatile unsigned int*)(0x42C9031CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A40          *((volatile unsigned int*)(0x42C90320UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A41          *((volatile unsigned int*)(0x42C90324UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A42          *((volatile unsigned int*)(0x42C90328UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A43          *((volatile unsigned int*)(0x42C9032CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A44          *((volatile unsigned int*)(0x42C90330UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A45          *((volatile unsigned int*)(0x42C90334UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A46          *((volatile unsigned int*)(0x42C90338UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A47          *((volatile unsigned int*)(0x42C9033CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC0         *((volatile unsigned int*)(0x42C90360UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC1         *((volatile unsigned int*)(0x42C90364UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC2         *((volatile unsigned int*)(0x42C90368UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC3         *((volatile unsigned int*)(0x42C9036CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC4         *((volatile unsigned int*)(0x42C90370UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC5         *((volatile unsigned int*)(0x42C90374UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_SA           *((volatile unsigned int*)(0x42C90378UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_AE           *((volatile unsigned int*)(0x42C9037CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A0           *((volatile unsigned int*)(0x42C90380UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A1           *((volatile unsigned int*)(0x42C90384UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A2           *((volatile unsigned int*)(0x42C90388UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A3           *((volatile unsigned int*)(0x42C9038CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A4           *((volatile unsigned int*)(0x42C90390UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A5           *((volatile unsigned int*)(0x42C90394UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A6           *((volatile unsigned int*)(0x42C90398UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A7           *((volatile unsigned int*)(0x42C9039CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A8           *((volatile unsigned int*)(0x42C903A0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A9           *((volatile unsigned int*)(0x42C903A4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A10          *((volatile unsigned int*)(0x42C903A8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A11          *((volatile unsigned int*)(0x42C903ACUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A12          *((volatile unsigned int*)(0x42C903B0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A13          *((volatile unsigned int*)(0x42C903B4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A14          *((volatile unsigned int*)(0x42C903B8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A15          *((volatile unsigned int*)(0x42C903BCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A16          *((volatile unsigned int*)(0x42C903C0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A17          *((volatile unsigned int*)(0x42C903C4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A18          *((volatile unsigned int*)(0x42C903C8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A19          *((volatile unsigned int*)(0x42C903CCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A20          *((volatile unsigned int*)(0x42C903D0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A21          *((volatile unsigned int*)(0x42C903D4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A22          *((volatile unsigned int*)(0x42C903D8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A23          *((volatile unsigned int*)(0x42C903DCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A24          *((volatile unsigned int*)(0x42C903E0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A25          *((volatile unsigned int*)(0x42C903E4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A26          *((volatile unsigned int*)(0x42C903E8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A27          *((volatile unsigned int*)(0x42C903ECUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A28          *((volatile unsigned int*)(0x42C903F0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A29          *((volatile unsigned int*)(0x42C903F4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A30          *((volatile unsigned int*)(0x42C903F8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A31          *((volatile unsigned int*)(0x42C903FCUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A32          *((volatile unsigned int*)(0x42C90400UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A33          *((volatile unsigned int*)(0x42C90404UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A34          *((volatile unsigned int*)(0x42C90408UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A35          *((volatile unsigned int*)(0x42C9040CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A36          *((volatile unsigned int*)(0x42C90410UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A37          *((volatile unsigned int*)(0x42C90414UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A38          *((volatile unsigned int*)(0x42C90418UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A39          *((volatile unsigned int*)(0x42C9041CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A40          *((volatile unsigned int*)(0x42C90420UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A41          *((volatile unsigned int*)(0x42C90424UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A42          *((volatile unsigned int*)(0x42C90428UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A43          *((volatile unsigned int*)(0x42C9042CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A44          *((volatile unsigned int*)(0x42C90430UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A45          *((volatile unsigned int*)(0x42C90434UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A46          *((volatile unsigned int*)(0x42C90438UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A47          *((volatile unsigned int*)(0x42C9043CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC0         *((volatile unsigned int*)(0x42C90460UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC1         *((volatile unsigned int*)(0x42C90464UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC2         *((volatile unsigned int*)(0x42C90468UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC3         *((volatile unsigned int*)(0x42C9046CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC4         *((volatile unsigned int*)(0x42C90470UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC5         *((volatile unsigned int*)(0x42C90474UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_SA           *((volatile unsigned int*)(0x42C90478UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_AE           *((volatile unsigned int*)(0x42C9047CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A0           *((volatile unsigned int*)(0x42C90480UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A1           *((volatile unsigned int*)(0x42C90484UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A2           *((volatile unsigned int*)(0x42C90488UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A3           *((volatile unsigned int*)(0x42C9048CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A4           *((volatile unsigned int*)(0x42C90490UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A5           *((volatile unsigned int*)(0x42C90494UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A6           *((volatile unsigned int*)(0x42C90498UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A7           *((volatile unsigned int*)(0x42C9049CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A8           *((volatile unsigned int*)(0x42C904A0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A9           *((volatile unsigned int*)(0x42C904A4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A10          *((volatile unsigned int*)(0x42C904A8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A11          *((volatile unsigned int*)(0x42C904ACUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A12          *((volatile unsigned int*)(0x42C904B0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A13          *((volatile unsigned int*)(0x42C904B4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A14          *((volatile unsigned int*)(0x42C904B8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A15          *((volatile unsigned int*)(0x42C904BCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A16          *((volatile unsigned int*)(0x42C904C0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A17          *((volatile unsigned int*)(0x42C904C4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A18          *((volatile unsigned int*)(0x42C904C8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A19          *((volatile unsigned int*)(0x42C904CCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A20          *((volatile unsigned int*)(0x42C904D0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A21          *((volatile unsigned int*)(0x42C904D4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A22          *((volatile unsigned int*)(0x42C904D8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A23          *((volatile unsigned int*)(0x42C904DCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A24          *((volatile unsigned int*)(0x42C904E0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A25          *((volatile unsigned int*)(0x42C904E4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A26          *((volatile unsigned int*)(0x42C904E8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A27          *((volatile unsigned int*)(0x42C904ECUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A28          *((volatile unsigned int*)(0x42C904F0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A29          *((volatile unsigned int*)(0x42C904F4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A30          *((volatile unsigned int*)(0x42C904F8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A31          *((volatile unsigned int*)(0x42C904FCUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A32          *((volatile unsigned int*)(0x42C90500UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A33          *((volatile unsigned int*)(0x42C90504UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A34          *((volatile unsigned int*)(0x42C90508UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A35          *((volatile unsigned int*)(0x42C9050CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A36          *((volatile unsigned int*)(0x42C90510UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A37          *((volatile unsigned int*)(0x42C90514UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A38          *((volatile unsigned int*)(0x42C90518UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A39          *((volatile unsigned int*)(0x42C9051CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A40          *((volatile unsigned int*)(0x42C90520UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A41          *((volatile unsigned int*)(0x42C90524UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A42          *((volatile unsigned int*)(0x42C90528UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A43          *((volatile unsigned int*)(0x42C9052CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A44          *((volatile unsigned int*)(0x42C90530UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A45          *((volatile unsigned int*)(0x42C90534UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A46          *((volatile unsigned int*)(0x42C90538UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A47          *((volatile unsigned int*)(0x42C9053CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC0         *((volatile unsigned int*)(0x42C90560UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC1         *((volatile unsigned int*)(0x42C90564UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC2         *((volatile unsigned int*)(0x42C90568UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC3         *((volatile unsigned int*)(0x42C9056CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC4         *((volatile unsigned int*)(0x42C90570UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC5         *((volatile unsigned int*)(0x42C90574UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_SA           *((volatile unsigned int*)(0x42C90578UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_AE           *((volatile unsigned int*)(0x42C9057CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A0           *((volatile unsigned int*)(0x42C90580UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A1           *((volatile unsigned int*)(0x42C90584UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A2           *((volatile unsigned int*)(0x42C90588UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A3           *((volatile unsigned int*)(0x42C9058CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A4           *((volatile unsigned int*)(0x42C90590UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A5           *((volatile unsigned int*)(0x42C90594UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A6           *((volatile unsigned int*)(0x42C90598UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A7           *((volatile unsigned int*)(0x42C9059CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A8           *((volatile unsigned int*)(0x42C905A0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A9           *((volatile unsigned int*)(0x42C905A4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A10          *((volatile unsigned int*)(0x42C905A8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A11          *((volatile unsigned int*)(0x42C905ACUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A12          *((volatile unsigned int*)(0x42C905B0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A13          *((volatile unsigned int*)(0x42C905B4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A14          *((volatile unsigned int*)(0x42C905B8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A15          *((volatile unsigned int*)(0x42C905BCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A16          *((volatile unsigned int*)(0x42C905C0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A17          *((volatile unsigned int*)(0x42C905C4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A18          *((volatile unsigned int*)(0x42C905C8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A19          *((volatile unsigned int*)(0x42C905CCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A20          *((volatile unsigned int*)(0x42C905D0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A21          *((volatile unsigned int*)(0x42C905D4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A22          *((volatile unsigned int*)(0x42C905D8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A23          *((volatile unsigned int*)(0x42C905DCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A24          *((volatile unsigned int*)(0x42C905E0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A25          *((volatile unsigned int*)(0x42C905E4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A26          *((volatile unsigned int*)(0x42C905E8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A27          *((volatile unsigned int*)(0x42C905ECUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A28          *((volatile unsigned int*)(0x42C905F0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A29          *((volatile unsigned int*)(0x42C905F4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A30          *((volatile unsigned int*)(0x42C905F8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A31          *((volatile unsigned int*)(0x42C905FCUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A32          *((volatile unsigned int*)(0x42C90600UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A33          *((volatile unsigned int*)(0x42C90604UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A34          *((volatile unsigned int*)(0x42C90608UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A35          *((volatile unsigned int*)(0x42C9060CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A36          *((volatile unsigned int*)(0x42C90610UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A37          *((volatile unsigned int*)(0x42C90614UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A38          *((volatile unsigned int*)(0x42C90618UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A39          *((volatile unsigned int*)(0x42C9061CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A40          *((volatile unsigned int*)(0x42C90620UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A41          *((volatile unsigned int*)(0x42C90624UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A42          *((volatile unsigned int*)(0x42C90628UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A43          *((volatile unsigned int*)(0x42C9062CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A44          *((volatile unsigned int*)(0x42C90630UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A45          *((volatile unsigned int*)(0x42C90634UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A46          *((volatile unsigned int*)(0x42C90638UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A47          *((volatile unsigned int*)(0x42C9063CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC0         *((volatile unsigned int*)(0x42C90660UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC1         *((volatile unsigned int*)(0x42C90664UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC2         *((volatile unsigned int*)(0x42C90668UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC3         *((volatile unsigned int*)(0x42C9066CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC4         *((volatile unsigned int*)(0x42C90670UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC5         *((volatile unsigned int*)(0x42C90674UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_SA           *((volatile unsigned int*)(0x42C90678UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_AE           *((volatile unsigned int*)(0x42C9067CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A0           *((volatile unsigned int*)(0x42C90680UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A1           *((volatile unsigned int*)(0x42C90684UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A2           *((volatile unsigned int*)(0x42C90688UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A3           *((volatile unsigned int*)(0x42C9068CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A4           *((volatile unsigned int*)(0x42C90690UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A5           *((volatile unsigned int*)(0x42C90694UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A6           *((volatile unsigned int*)(0x42C90698UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A7           *((volatile unsigned int*)(0x42C9069CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A8           *((volatile unsigned int*)(0x42C906A0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A9           *((volatile unsigned int*)(0x42C906A4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A10          *((volatile unsigned int*)(0x42C906A8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A11          *((volatile unsigned int*)(0x42C906ACUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A12          *((volatile unsigned int*)(0x42C906B0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A13          *((volatile unsigned int*)(0x42C906B4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A14          *((volatile unsigned int*)(0x42C906B8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A15          *((volatile unsigned int*)(0x42C906BCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A16          *((volatile unsigned int*)(0x42C906C0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A17          *((volatile unsigned int*)(0x42C906C4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A18          *((volatile unsigned int*)(0x42C906C8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A19          *((volatile unsigned int*)(0x42C906CCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A20          *((volatile unsigned int*)(0x42C906D0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A21          *((volatile unsigned int*)(0x42C906D4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A22          *((volatile unsigned int*)(0x42C906D8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A23          *((volatile unsigned int*)(0x42C906DCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A24          *((volatile unsigned int*)(0x42C906E0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A25          *((volatile unsigned int*)(0x42C906E4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A26          *((volatile unsigned int*)(0x42C906E8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A27          *((volatile unsigned int*)(0x42C906ECUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A28          *((volatile unsigned int*)(0x42C906F0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A29          *((volatile unsigned int*)(0x42C906F4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A30          *((volatile unsigned int*)(0x42C906F8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A31          *((volatile unsigned int*)(0x42C906FCUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A32          *((volatile unsigned int*)(0x42C90700UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A33          *((volatile unsigned int*)(0x42C90704UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A34          *((volatile unsigned int*)(0x42C90708UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A35          *((volatile unsigned int*)(0x42C9070CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A36          *((volatile unsigned int*)(0x42C90710UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A37          *((volatile unsigned int*)(0x42C90714UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A38          *((volatile unsigned int*)(0x42C90718UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A39          *((volatile unsigned int*)(0x42C9071CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A40          *((volatile unsigned int*)(0x42C90720UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A41          *((volatile unsigned int*)(0x42C90724UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A42          *((volatile unsigned int*)(0x42C90728UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A43          *((volatile unsigned int*)(0x42C9072CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A44          *((volatile unsigned int*)(0x42C90730UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A45          *((volatile unsigned int*)(0x42C90734UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A46          *((volatile unsigned int*)(0x42C90738UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A47          *((volatile unsigned int*)(0x42C9073CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC0         *((volatile unsigned int*)(0x42C90760UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC1         *((volatile unsigned int*)(0x42C90764UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC2         *((volatile unsigned int*)(0x42C90768UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC3         *((volatile unsigned int*)(0x42C9076CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC4         *((volatile unsigned int*)(0x42C90770UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC5         *((volatile unsigned int*)(0x42C90774UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_SA           *((volatile unsigned int*)(0x42C90778UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_AE           *((volatile unsigned int*)(0x42C9077CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A0           *((volatile unsigned int*)(0x42C90780UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A1           *((volatile unsigned int*)(0x42C90784UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A2           *((volatile unsigned int*)(0x42C90788UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A3           *((volatile unsigned int*)(0x42C9078CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A4           *((volatile unsigned int*)(0x42C90790UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A5           *((volatile unsigned int*)(0x42C90794UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A6           *((volatile unsigned int*)(0x42C90798UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A7           *((volatile unsigned int*)(0x42C9079CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A8           *((volatile unsigned int*)(0x42C907A0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A9           *((volatile unsigned int*)(0x42C907A4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A10          *((volatile unsigned int*)(0x42C907A8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A11          *((volatile unsigned int*)(0x42C907ACUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A12          *((volatile unsigned int*)(0x42C907B0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A13          *((volatile unsigned int*)(0x42C907B4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A14          *((volatile unsigned int*)(0x42C907B8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A15          *((volatile unsigned int*)(0x42C907BCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A16          *((volatile unsigned int*)(0x42C907C0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A17          *((volatile unsigned int*)(0x42C907C4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A18          *((volatile unsigned int*)(0x42C907C8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A19          *((volatile unsigned int*)(0x42C907CCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A20          *((volatile unsigned int*)(0x42C907D0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A21          *((volatile unsigned int*)(0x42C907D4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A22          *((volatile unsigned int*)(0x42C907D8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A23          *((volatile unsigned int*)(0x42C907DCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A24          *((volatile unsigned int*)(0x42C907E0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A25          *((volatile unsigned int*)(0x42C907E4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A26          *((volatile unsigned int*)(0x42C907E8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A27          *((volatile unsigned int*)(0x42C907ECUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A28          *((volatile unsigned int*)(0x42C907F0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A29          *((volatile unsigned int*)(0x42C907F4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A30          *((volatile unsigned int*)(0x42C907F8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A31          *((volatile unsigned int*)(0x42C907FCUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A32          *((volatile unsigned int*)(0x42C90800UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A33          *((volatile unsigned int*)(0x42C90804UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A34          *((volatile unsigned int*)(0x42C90808UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A35          *((volatile unsigned int*)(0x42C9080CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A36          *((volatile unsigned int*)(0x42C90810UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A37          *((volatile unsigned int*)(0x42C90814UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A38          *((volatile unsigned int*)(0x42C90818UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A39          *((volatile unsigned int*)(0x42C9081CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A40          *((volatile unsigned int*)(0x42C90820UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A41          *((volatile unsigned int*)(0x42C90824UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A42          *((volatile unsigned int*)(0x42C90828UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A43          *((volatile unsigned int*)(0x42C9082CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A44          *((volatile unsigned int*)(0x42C90830UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A45          *((volatile unsigned int*)(0x42C90834UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A46          *((volatile unsigned int*)(0x42C90838UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A47          *((volatile unsigned int*)(0x42C9083CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC0         *((volatile unsigned int*)(0x42C90860UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC1         *((volatile unsigned int*)(0x42C90864UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC2         *((volatile unsigned int*)(0x42C90868UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC3         *((volatile unsigned int*)(0x42C9086CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC4         *((volatile unsigned int*)(0x42C90870UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC5         *((volatile unsigned int*)(0x42C90874UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_SA           *((volatile unsigned int*)(0x42C90878UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_AE           *((volatile unsigned int*)(0x42C9087CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A0           *((volatile unsigned int*)(0x42C90880UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A1           *((volatile unsigned int*)(0x42C90884UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A2           *((volatile unsigned int*)(0x42C90888UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A3           *((volatile unsigned int*)(0x42C9088CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A4           *((volatile unsigned int*)(0x42C90890UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A5           *((volatile unsigned int*)(0x42C90894UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A6           *((volatile unsigned int*)(0x42C90898UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A7           *((volatile unsigned int*)(0x42C9089CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A8           *((volatile unsigned int*)(0x42C908A0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A9           *((volatile unsigned int*)(0x42C908A4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A10          *((volatile unsigned int*)(0x42C908A8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A11          *((volatile unsigned int*)(0x42C908ACUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A12          *((volatile unsigned int*)(0x42C908B0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A13          *((volatile unsigned int*)(0x42C908B4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A14          *((volatile unsigned int*)(0x42C908B8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A15          *((volatile unsigned int*)(0x42C908BCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A16          *((volatile unsigned int*)(0x42C908C0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A17          *((volatile unsigned int*)(0x42C908C4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A18          *((volatile unsigned int*)(0x42C908C8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A19          *((volatile unsigned int*)(0x42C908CCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A20          *((volatile unsigned int*)(0x42C908D0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A21          *((volatile unsigned int*)(0x42C908D4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A22          *((volatile unsigned int*)(0x42C908D8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A23          *((volatile unsigned int*)(0x42C908DCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A24          *((volatile unsigned int*)(0x42C908E0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A25          *((volatile unsigned int*)(0x42C908E4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A26          *((volatile unsigned int*)(0x42C908E8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A27          *((volatile unsigned int*)(0x42C908ECUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A28          *((volatile unsigned int*)(0x42C908F0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A29          *((volatile unsigned int*)(0x42C908F4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A30          *((volatile unsigned int*)(0x42C908F8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A31          *((volatile unsigned int*)(0x42C908FCUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A32          *((volatile unsigned int*)(0x42C90900UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A33          *((volatile unsigned int*)(0x42C90904UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A34          *((volatile unsigned int*)(0x42C90908UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A35          *((volatile unsigned int*)(0x42C9090CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A36          *((volatile unsigned int*)(0x42C90910UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A37          *((volatile unsigned int*)(0x42C90914UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A38          *((volatile unsigned int*)(0x42C90918UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A39          *((volatile unsigned int*)(0x42C9091CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A40          *((volatile unsigned int*)(0x42C90920UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A41          *((volatile unsigned int*)(0x42C90924UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A42          *((volatile unsigned int*)(0x42C90928UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A43          *((volatile unsigned int*)(0x42C9092CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A44          *((volatile unsigned int*)(0x42C90930UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A45          *((volatile unsigned int*)(0x42C90934UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A46          *((volatile unsigned int*)(0x42C90938UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A47          *((volatile unsigned int*)(0x42C9093CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC0         *((volatile unsigned int*)(0x42C90960UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC1         *((volatile unsigned int*)(0x42C90964UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC2         *((volatile unsigned int*)(0x42C90968UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC3         *((volatile unsigned int*)(0x42C9096CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC4         *((volatile unsigned int*)(0x42C90970UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC5         *((volatile unsigned int*)(0x42C90974UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_SA           *((volatile unsigned int*)(0x42C90978UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_AE           *((volatile unsigned int*)(0x42C9097CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A0           *((volatile unsigned int*)(0x42C90980UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A1           *((volatile unsigned int*)(0x42C90984UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A2           *((volatile unsigned int*)(0x42C90988UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A3           *((volatile unsigned int*)(0x42C9098CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A4           *((volatile unsigned int*)(0x42C90990UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A5           *((volatile unsigned int*)(0x42C90994UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A6           *((volatile unsigned int*)(0x42C90998UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A7           *((volatile unsigned int*)(0x42C9099CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A8           *((volatile unsigned int*)(0x42C909A0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A9           *((volatile unsigned int*)(0x42C909A4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A10          *((volatile unsigned int*)(0x42C909A8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A11          *((volatile unsigned int*)(0x42C909ACUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A12          *((volatile unsigned int*)(0x42C909B0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A13          *((volatile unsigned int*)(0x42C909B4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A14          *((volatile unsigned int*)(0x42C909B8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A15          *((volatile unsigned int*)(0x42C909BCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A16          *((volatile unsigned int*)(0x42C909C0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A17          *((volatile unsigned int*)(0x42C909C4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A18          *((volatile unsigned int*)(0x42C909C8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A19          *((volatile unsigned int*)(0x42C909CCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A20          *((volatile unsigned int*)(0x42C909D0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A21          *((volatile unsigned int*)(0x42C909D4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A22          *((volatile unsigned int*)(0x42C909D8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A23          *((volatile unsigned int*)(0x42C909DCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A24          *((volatile unsigned int*)(0x42C909E0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A25          *((volatile unsigned int*)(0x42C909E4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A26          *((volatile unsigned int*)(0x42C909E8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A27          *((volatile unsigned int*)(0x42C909ECUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A28          *((volatile unsigned int*)(0x42C909F0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A29          *((volatile unsigned int*)(0x42C909F4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A30          *((volatile unsigned int*)(0x42C909F8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A31          *((volatile unsigned int*)(0x42C909FCUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A32          *((volatile unsigned int*)(0x42C90A00UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A33          *((volatile unsigned int*)(0x42C90A04UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A34          *((volatile unsigned int*)(0x42C90A08UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A35          *((volatile unsigned int*)(0x42C90A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A36          *((volatile unsigned int*)(0x42C90A10UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A37          *((volatile unsigned int*)(0x42C90A14UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A38          *((volatile unsigned int*)(0x42C90A18UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A39          *((volatile unsigned int*)(0x42C90A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A40          *((volatile unsigned int*)(0x42C90A20UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A41          *((volatile unsigned int*)(0x42C90A24UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A42          *((volatile unsigned int*)(0x42C90A28UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A43          *((volatile unsigned int*)(0x42C90A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A44          *((volatile unsigned int*)(0x42C90A30UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A45          *((volatile unsigned int*)(0x42C90A34UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A46          *((volatile unsigned int*)(0x42C90A38UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A47          *((volatile unsigned int*)(0x42C90A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC0         *((volatile unsigned int*)(0x42C90A60UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC1         *((volatile unsigned int*)(0x42C90A64UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC2         *((volatile unsigned int*)(0x42C90A68UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC3         *((volatile unsigned int*)(0x42C90A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC4         *((volatile unsigned int*)(0x42C90A70UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC5         *((volatile unsigned int*)(0x42C90A74UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_SA           *((volatile unsigned int*)(0x42C90A78UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_AE           *((volatile unsigned int*)(0x42C90A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A0           *((volatile unsigned int*)(0x42C90A80UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A1           *((volatile unsigned int*)(0x42C90A84UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A2           *((volatile unsigned int*)(0x42C90A88UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A3           *((volatile unsigned int*)(0x42C90A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A4           *((volatile unsigned int*)(0x42C90A90UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A5           *((volatile unsigned int*)(0x42C90A94UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A6           *((volatile unsigned int*)(0x42C90A98UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A7           *((volatile unsigned int*)(0x42C90A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A8           *((volatile unsigned int*)(0x42C90AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A9           *((volatile unsigned int*)(0x42C90AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A10          *((volatile unsigned int*)(0x42C90AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A11          *((volatile unsigned int*)(0x42C90AACUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A12          *((volatile unsigned int*)(0x42C90AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A13          *((volatile unsigned int*)(0x42C90AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A14          *((volatile unsigned int*)(0x42C90AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A15          *((volatile unsigned int*)(0x42C90ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A16          *((volatile unsigned int*)(0x42C90AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A17          *((volatile unsigned int*)(0x42C90AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A18          *((volatile unsigned int*)(0x42C90AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A19          *((volatile unsigned int*)(0x42C90ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A20          *((volatile unsigned int*)(0x42C90AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A21          *((volatile unsigned int*)(0x42C90AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A22          *((volatile unsigned int*)(0x42C90AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A23          *((volatile unsigned int*)(0x42C90ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A24          *((volatile unsigned int*)(0x42C90AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A25          *((volatile unsigned int*)(0x42C90AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A26          *((volatile unsigned int*)(0x42C90AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A27          *((volatile unsigned int*)(0x42C90AECUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A28          *((volatile unsigned int*)(0x42C90AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A29          *((volatile unsigned int*)(0x42C90AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A30          *((volatile unsigned int*)(0x42C90AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A31          *((volatile unsigned int*)(0x42C90AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A32          *((volatile unsigned int*)(0x42C90B00UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A33          *((volatile unsigned int*)(0x42C90B04UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A34          *((volatile unsigned int*)(0x42C90B08UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A35          *((volatile unsigned int*)(0x42C90B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A36          *((volatile unsigned int*)(0x42C90B10UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A37          *((volatile unsigned int*)(0x42C90B14UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A38          *((volatile unsigned int*)(0x42C90B18UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A39          *((volatile unsigned int*)(0x42C90B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A40          *((volatile unsigned int*)(0x42C90B20UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A41          *((volatile unsigned int*)(0x42C90B24UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A42          *((volatile unsigned int*)(0x42C90B28UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A43          *((volatile unsigned int*)(0x42C90B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A44          *((volatile unsigned int*)(0x42C90B30UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A45          *((volatile unsigned int*)(0x42C90B34UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A46          *((volatile unsigned int*)(0x42C90B38UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A47          *((volatile unsigned int*)(0x42C90B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC0         *((volatile unsigned int*)(0x42C90B60UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC1         *((volatile unsigned int*)(0x42C90B64UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC2         *((volatile unsigned int*)(0x42C90B68UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC3         *((volatile unsigned int*)(0x42C90B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC4         *((volatile unsigned int*)(0x42C90B70UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC5         *((volatile unsigned int*)(0x42C90B74UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_SA           *((volatile unsigned int*)(0x42C90B78UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_AE           *((volatile unsigned int*)(0x42C90B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A0           *((volatile unsigned int*)(0x42C90B80UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A1           *((volatile unsigned int*)(0x42C90B84UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A2           *((volatile unsigned int*)(0x42C90B88UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A3           *((volatile unsigned int*)(0x42C90B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A4           *((volatile unsigned int*)(0x42C90B90UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A5           *((volatile unsigned int*)(0x42C90B94UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A6           *((volatile unsigned int*)(0x42C90B98UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A7           *((volatile unsigned int*)(0x42C90B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A8           *((volatile unsigned int*)(0x42C90BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A9           *((volatile unsigned int*)(0x42C90BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A10          *((volatile unsigned int*)(0x42C90BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A11          *((volatile unsigned int*)(0x42C90BACUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A12          *((volatile unsigned int*)(0x42C90BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A13          *((volatile unsigned int*)(0x42C90BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A14          *((volatile unsigned int*)(0x42C90BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A15          *((volatile unsigned int*)(0x42C90BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A16          *((volatile unsigned int*)(0x42C90BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A17          *((volatile unsigned int*)(0x42C90BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A18          *((volatile unsigned int*)(0x42C90BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A19          *((volatile unsigned int*)(0x42C90BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A20          *((volatile unsigned int*)(0x42C90BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A21          *((volatile unsigned int*)(0x42C90BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A22          *((volatile unsigned int*)(0x42C90BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A23          *((volatile unsigned int*)(0x42C90BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A24          *((volatile unsigned int*)(0x42C90BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A25          *((volatile unsigned int*)(0x42C90BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A26          *((volatile unsigned int*)(0x42C90BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A27          *((volatile unsigned int*)(0x42C90BECUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A28          *((volatile unsigned int*)(0x42C90BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A29          *((volatile unsigned int*)(0x42C90BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A30          *((volatile unsigned int*)(0x42C90BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A31          *((volatile unsigned int*)(0x42C90BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A32          *((volatile unsigned int*)(0x42C90C00UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A33          *((volatile unsigned int*)(0x42C90C04UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A34          *((volatile unsigned int*)(0x42C90C08UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A35          *((volatile unsigned int*)(0x42C90C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A36          *((volatile unsigned int*)(0x42C90C10UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A37          *((volatile unsigned int*)(0x42C90C14UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A38          *((volatile unsigned int*)(0x42C90C18UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A39          *((volatile unsigned int*)(0x42C90C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A40          *((volatile unsigned int*)(0x42C90C20UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A41          *((volatile unsigned int*)(0x42C90C24UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A42          *((volatile unsigned int*)(0x42C90C28UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A43          *((volatile unsigned int*)(0x42C90C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A44          *((volatile unsigned int*)(0x42C90C30UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A45          *((volatile unsigned int*)(0x42C90C34UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A46          *((volatile unsigned int*)(0x42C90C38UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A47          *((volatile unsigned int*)(0x42C90C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC0         *((volatile unsigned int*)(0x42C90C60UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC1         *((volatile unsigned int*)(0x42C90C64UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC2         *((volatile unsigned int*)(0x42C90C68UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC3         *((volatile unsigned int*)(0x42C90C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC4         *((volatile unsigned int*)(0x42C90C70UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC5         *((volatile unsigned int*)(0x42C90C74UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_SA           *((volatile unsigned int*)(0x42C90C78UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_AE           *((volatile unsigned int*)(0x42C90C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A0           *((volatile unsigned int*)(0x42C90C80UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A1           *((volatile unsigned int*)(0x42C90C84UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A2           *((volatile unsigned int*)(0x42C90C88UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A3           *((volatile unsigned int*)(0x42C90C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A4           *((volatile unsigned int*)(0x42C90C90UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A5           *((volatile unsigned int*)(0x42C90C94UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A6           *((volatile unsigned int*)(0x42C90C98UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A7           *((volatile unsigned int*)(0x42C90C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A8           *((volatile unsigned int*)(0x42C90CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A9           *((volatile unsigned int*)(0x42C90CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A10          *((volatile unsigned int*)(0x42C90CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A11          *((volatile unsigned int*)(0x42C90CACUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A12          *((volatile unsigned int*)(0x42C90CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A13          *((volatile unsigned int*)(0x42C90CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A14          *((volatile unsigned int*)(0x42C90CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A15          *((volatile unsigned int*)(0x42C90CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A16          *((volatile unsigned int*)(0x42C90CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A17          *((volatile unsigned int*)(0x42C90CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A18          *((volatile unsigned int*)(0x42C90CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A19          *((volatile unsigned int*)(0x42C90CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A20          *((volatile unsigned int*)(0x42C90CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A21          *((volatile unsigned int*)(0x42C90CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A22          *((volatile unsigned int*)(0x42C90CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A23          *((volatile unsigned int*)(0x42C90CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A24          *((volatile unsigned int*)(0x42C90CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A25          *((volatile unsigned int*)(0x42C90CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A26          *((volatile unsigned int*)(0x42C90CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A27          *((volatile unsigned int*)(0x42C90CECUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A28          *((volatile unsigned int*)(0x42C90CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A29          *((volatile unsigned int*)(0x42C90CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A30          *((volatile unsigned int*)(0x42C90CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A31          *((volatile unsigned int*)(0x42C90CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A32          *((volatile unsigned int*)(0x42C90D00UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A33          *((volatile unsigned int*)(0x42C90D04UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A34          *((volatile unsigned int*)(0x42C90D08UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A35          *((volatile unsigned int*)(0x42C90D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A36          *((volatile unsigned int*)(0x42C90D10UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A37          *((volatile unsigned int*)(0x42C90D14UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A38          *((volatile unsigned int*)(0x42C90D18UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A39          *((volatile unsigned int*)(0x42C90D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A40          *((volatile unsigned int*)(0x42C90D20UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A41          *((volatile unsigned int*)(0x42C90D24UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A42          *((volatile unsigned int*)(0x42C90D28UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A43          *((volatile unsigned int*)(0x42C90D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A44          *((volatile unsigned int*)(0x42C90D30UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A45          *((volatile unsigned int*)(0x42C90D34UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A46          *((volatile unsigned int*)(0x42C90D38UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A47          *((volatile unsigned int*)(0x42C90D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC0         *((volatile unsigned int*)(0x42C90D60UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC1         *((volatile unsigned int*)(0x42C90D64UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC2         *((volatile unsigned int*)(0x42C90D68UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC3         *((volatile unsigned int*)(0x42C90D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC4         *((volatile unsigned int*)(0x42C90D70UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC5         *((volatile unsigned int*)(0x42C90D74UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_SA           *((volatile unsigned int*)(0x42C90D78UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_AE           *((volatile unsigned int*)(0x42C90D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A0           *((volatile unsigned int*)(0x42C90D80UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A1           *((volatile unsigned int*)(0x42C90D84UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A2           *((volatile unsigned int*)(0x42C90D88UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A3           *((volatile unsigned int*)(0x42C90D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A4           *((volatile unsigned int*)(0x42C90D90UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A5           *((volatile unsigned int*)(0x42C90D94UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A6           *((volatile unsigned int*)(0x42C90D98UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A7           *((volatile unsigned int*)(0x42C90D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A8           *((volatile unsigned int*)(0x42C90DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A9           *((volatile unsigned int*)(0x42C90DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A10          *((volatile unsigned int*)(0x42C90DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A11          *((volatile unsigned int*)(0x42C90DACUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A12          *((volatile unsigned int*)(0x42C90DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A13          *((volatile unsigned int*)(0x42C90DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A14          *((volatile unsigned int*)(0x42C90DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A15          *((volatile unsigned int*)(0x42C90DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A16          *((volatile unsigned int*)(0x42C90DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A17          *((volatile unsigned int*)(0x42C90DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A18          *((volatile unsigned int*)(0x42C90DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A19          *((volatile unsigned int*)(0x42C90DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A20          *((volatile unsigned int*)(0x42C90DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A21          *((volatile unsigned int*)(0x42C90DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A22          *((volatile unsigned int*)(0x42C90DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A23          *((volatile unsigned int*)(0x42C90DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A24          *((volatile unsigned int*)(0x42C90DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A25          *((volatile unsigned int*)(0x42C90DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A26          *((volatile unsigned int*)(0x42C90DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A27          *((volatile unsigned int*)(0x42C90DECUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A28          *((volatile unsigned int*)(0x42C90DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A29          *((volatile unsigned int*)(0x42C90DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A30          *((volatile unsigned int*)(0x42C90DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A31          *((volatile unsigned int*)(0x42C90DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A32          *((volatile unsigned int*)(0x42C90E00UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A33          *((volatile unsigned int*)(0x42C90E04UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A34          *((volatile unsigned int*)(0x42C90E08UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A35          *((volatile unsigned int*)(0x42C90E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A36          *((volatile unsigned int*)(0x42C90E10UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A37          *((volatile unsigned int*)(0x42C90E14UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A38          *((volatile unsigned int*)(0x42C90E18UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A39          *((volatile unsigned int*)(0x42C90E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A40          *((volatile unsigned int*)(0x42C90E20UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A41          *((volatile unsigned int*)(0x42C90E24UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A42          *((volatile unsigned int*)(0x42C90E28UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A43          *((volatile unsigned int*)(0x42C90E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A44          *((volatile unsigned int*)(0x42C90E30UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A45          *((volatile unsigned int*)(0x42C90E34UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A46          *((volatile unsigned int*)(0x42C90E38UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A47          *((volatile unsigned int*)(0x42C90E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC0         *((volatile unsigned int*)(0x42C90E60UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC1         *((volatile unsigned int*)(0x42C90E64UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC2         *((volatile unsigned int*)(0x42C90E68UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC3         *((volatile unsigned int*)(0x42C90E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC4         *((volatile unsigned int*)(0x42C90E70UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC5         *((volatile unsigned int*)(0x42C90E74UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_SA           *((volatile unsigned int*)(0x42C90E78UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_AE           *((volatile unsigned int*)(0x42C90E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A0           *((volatile unsigned int*)(0x42C90E80UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A1           *((volatile unsigned int*)(0x42C90E84UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A2           *((volatile unsigned int*)(0x42C90E88UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A3           *((volatile unsigned int*)(0x42C90E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A4           *((volatile unsigned int*)(0x42C90E90UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A5           *((volatile unsigned int*)(0x42C90E94UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A6           *((volatile unsigned int*)(0x42C90E98UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A7           *((volatile unsigned int*)(0x42C90E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A8           *((volatile unsigned int*)(0x42C90EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A9           *((volatile unsigned int*)(0x42C90EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A10          *((volatile unsigned int*)(0x42C90EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A11          *((volatile unsigned int*)(0x42C90EACUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A12          *((volatile unsigned int*)(0x42C90EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A13          *((volatile unsigned int*)(0x42C90EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A14          *((volatile unsigned int*)(0x42C90EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A15          *((volatile unsigned int*)(0x42C90EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A16          *((volatile unsigned int*)(0x42C90EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A17          *((volatile unsigned int*)(0x42C90EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A18          *((volatile unsigned int*)(0x42C90EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A19          *((volatile unsigned int*)(0x42C90ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A20          *((volatile unsigned int*)(0x42C90ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A21          *((volatile unsigned int*)(0x42C90ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A22          *((volatile unsigned int*)(0x42C90ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A23          *((volatile unsigned int*)(0x42C90EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A24          *((volatile unsigned int*)(0x42C90EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A25          *((volatile unsigned int*)(0x42C90EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A26          *((volatile unsigned int*)(0x42C90EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A27          *((volatile unsigned int*)(0x42C90EECUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A28          *((volatile unsigned int*)(0x42C90EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A29          *((volatile unsigned int*)(0x42C90EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A30          *((volatile unsigned int*)(0x42C90EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A31          *((volatile unsigned int*)(0x42C90EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A32          *((volatile unsigned int*)(0x42C90F00UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A33          *((volatile unsigned int*)(0x42C90F04UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A34          *((volatile unsigned int*)(0x42C90F08UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A35          *((volatile unsigned int*)(0x42C90F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A36          *((volatile unsigned int*)(0x42C90F10UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A37          *((volatile unsigned int*)(0x42C90F14UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A38          *((volatile unsigned int*)(0x42C90F18UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A39          *((volatile unsigned int*)(0x42C90F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A40          *((volatile unsigned int*)(0x42C90F20UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A41          *((volatile unsigned int*)(0x42C90F24UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A42          *((volatile unsigned int*)(0x42C90F28UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A43          *((volatile unsigned int*)(0x42C90F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A44          *((volatile unsigned int*)(0x42C90F30UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A45          *((volatile unsigned int*)(0x42C90F34UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A46          *((volatile unsigned int*)(0x42C90F38UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A47          *((volatile unsigned int*)(0x42C90F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC0         *((volatile unsigned int*)(0x42C90F60UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC1         *((volatile unsigned int*)(0x42C90F64UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC2         *((volatile unsigned int*)(0x42C90F68UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC3         *((volatile unsigned int*)(0x42C90F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC4         *((volatile unsigned int*)(0x42C90F70UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC5         *((volatile unsigned int*)(0x42C90F74UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_SA           *((volatile unsigned int*)(0x42C90F78UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_AE           *((volatile unsigned int*)(0x42C90F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A0           *((volatile unsigned int*)(0x42C90F80UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A1           *((volatile unsigned int*)(0x42C90F84UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A2           *((volatile unsigned int*)(0x42C90F88UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A3           *((volatile unsigned int*)(0x42C90F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A4           *((volatile unsigned int*)(0x42C90F90UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A5           *((volatile unsigned int*)(0x42C90F94UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A6           *((volatile unsigned int*)(0x42C90F98UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A7           *((volatile unsigned int*)(0x42C90F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A8           *((volatile unsigned int*)(0x42C90FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A9           *((volatile unsigned int*)(0x42C90FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A10          *((volatile unsigned int*)(0x42C90FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A11          *((volatile unsigned int*)(0x42C90FACUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A12          *((volatile unsigned int*)(0x42C90FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A13          *((volatile unsigned int*)(0x42C90FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A14          *((volatile unsigned int*)(0x42C90FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A15          *((volatile unsigned int*)(0x42C90FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A16          *((volatile unsigned int*)(0x42C90FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A17          *((volatile unsigned int*)(0x42C90FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A18          *((volatile unsigned int*)(0x42C90FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A19          *((volatile unsigned int*)(0x42C90FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A20          *((volatile unsigned int*)(0x42C90FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A21          *((volatile unsigned int*)(0x42C90FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A22          *((volatile unsigned int*)(0x42C90FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A23          *((volatile unsigned int*)(0x42C90FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A24          *((volatile unsigned int*)(0x42C90FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A25          *((volatile unsigned int*)(0x42C90FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A26          *((volatile unsigned int*)(0x42C90FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A27          *((volatile unsigned int*)(0x42C90FECUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A28          *((volatile unsigned int*)(0x42C90FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A29          *((volatile unsigned int*)(0x42C90FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A30          *((volatile unsigned int*)(0x42C90FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A31          *((volatile unsigned int*)(0x42C90FFCUL))
+#define bFM3_ETHERNET_MAC0_BMR_SWR             *((volatile unsigned int*)(0x42CA0000UL))
+#define bFM3_ETHERNET_MAC0_BMR_DA              *((volatile unsigned int*)(0x42CA0004UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL0            *((volatile unsigned int*)(0x42CA0008UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL1            *((volatile unsigned int*)(0x42CA000CUL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL2            *((volatile unsigned int*)(0x42CA0010UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL3            *((volatile unsigned int*)(0x42CA0014UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL4            *((volatile unsigned int*)(0x42CA0018UL))
+#define bFM3_ETHERNET_MAC0_BMR_ATDS            *((volatile unsigned int*)(0x42CA001CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL0            *((volatile unsigned int*)(0x42CA0020UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL1            *((volatile unsigned int*)(0x42CA0024UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL2            *((volatile unsigned int*)(0x42CA0028UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL3            *((volatile unsigned int*)(0x42CA002CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL4            *((volatile unsigned int*)(0x42CA0030UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL5            *((volatile unsigned int*)(0x42CA0034UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR0             *((volatile unsigned int*)(0x42CA0038UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR1             *((volatile unsigned int*)(0x42CA003CUL))
+#define bFM3_ETHERNET_MAC0_BMR_FB              *((volatile unsigned int*)(0x42CA0040UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL0           *((volatile unsigned int*)(0x42CA0044UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL1           *((volatile unsigned int*)(0x42CA0048UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL2           *((volatile unsigned int*)(0x42CA004CUL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL3           *((volatile unsigned int*)(0x42CA0050UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL4           *((volatile unsigned int*)(0x42CA0054UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL5           *((volatile unsigned int*)(0x42CA0058UL))
+#define bFM3_ETHERNET_MAC0_BMR_USP             *((volatile unsigned int*)(0x42CA005CUL))
+#define bFM3_ETHERNET_MAC0_BMR_8XPBL           *((volatile unsigned int*)(0x42CA0060UL))
+#define bFM3_ETHERNET_MAC0_BMR_AAL             *((volatile unsigned int*)(0x42CA0064UL))
+#define bFM3_ETHERNET_MAC0_BMR_MB              *((volatile unsigned int*)(0x42CA0068UL))
+#define bFM3_ETHERNET_MAC0_BMR_TXPR            *((volatile unsigned int*)(0x42CA006CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD0           *((volatile unsigned int*)(0x42CA0080UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD1           *((volatile unsigned int*)(0x42CA0084UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD2           *((volatile unsigned int*)(0x42CA0088UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD3           *((volatile unsigned int*)(0x42CA008CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD4           *((volatile unsigned int*)(0x42CA0090UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD5           *((volatile unsigned int*)(0x42CA0094UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD6           *((volatile unsigned int*)(0x42CA0098UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD7           *((volatile unsigned int*)(0x42CA009CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD8           *((volatile unsigned int*)(0x42CA00A0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD9           *((volatile unsigned int*)(0x42CA00A4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD10          *((volatile unsigned int*)(0x42CA00A8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD11          *((volatile unsigned int*)(0x42CA00ACUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD12          *((volatile unsigned int*)(0x42CA00B0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD13          *((volatile unsigned int*)(0x42CA00B4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD14          *((volatile unsigned int*)(0x42CA00B8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD15          *((volatile unsigned int*)(0x42CA00BCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD16          *((volatile unsigned int*)(0x42CA00C0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD17          *((volatile unsigned int*)(0x42CA00C4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD18          *((volatile unsigned int*)(0x42CA00C8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD19          *((volatile unsigned int*)(0x42CA00CCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD20          *((volatile unsigned int*)(0x42CA00D0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD21          *((volatile unsigned int*)(0x42CA00D4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD22          *((volatile unsigned int*)(0x42CA00D8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD23          *((volatile unsigned int*)(0x42CA00DCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD24          *((volatile unsigned int*)(0x42CA00E0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD25          *((volatile unsigned int*)(0x42CA00E4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD26          *((volatile unsigned int*)(0x42CA00E8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD27          *((volatile unsigned int*)(0x42CA00ECUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD28          *((volatile unsigned int*)(0x42CA00F0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD29          *((volatile unsigned int*)(0x42CA00F4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD30          *((volatile unsigned int*)(0x42CA00F8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD31          *((volatile unsigned int*)(0x42CA00FCUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD0           *((volatile unsigned int*)(0x42CA0100UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD1           *((volatile unsigned int*)(0x42CA0104UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD2           *((volatile unsigned int*)(0x42CA0108UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD3           *((volatile unsigned int*)(0x42CA010CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD4           *((volatile unsigned int*)(0x42CA0110UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD5           *((volatile unsigned int*)(0x42CA0114UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD6           *((volatile unsigned int*)(0x42CA0118UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD7           *((volatile unsigned int*)(0x42CA011CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD8           *((volatile unsigned int*)(0x42CA0120UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD9           *((volatile unsigned int*)(0x42CA0124UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD10          *((volatile unsigned int*)(0x42CA0128UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD11          *((volatile unsigned int*)(0x42CA012CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD12          *((volatile unsigned int*)(0x42CA0130UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD13          *((volatile unsigned int*)(0x42CA0134UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD14          *((volatile unsigned int*)(0x42CA0138UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD15          *((volatile unsigned int*)(0x42CA013CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD16          *((volatile unsigned int*)(0x42CA0140UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD17          *((volatile unsigned int*)(0x42CA0144UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD18          *((volatile unsigned int*)(0x42CA0148UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD19          *((volatile unsigned int*)(0x42CA014CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD20          *((volatile unsigned int*)(0x42CA0150UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD21          *((volatile unsigned int*)(0x42CA0154UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD22          *((volatile unsigned int*)(0x42CA0158UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD23          *((volatile unsigned int*)(0x42CA015CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD24          *((volatile unsigned int*)(0x42CA0160UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD25          *((volatile unsigned int*)(0x42CA0164UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD26          *((volatile unsigned int*)(0x42CA0168UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD27          *((volatile unsigned int*)(0x42CA016CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD28          *((volatile unsigned int*)(0x42CA0170UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD29          *((volatile unsigned int*)(0x42CA0174UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD30          *((volatile unsigned int*)(0x42CA0178UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD31          *((volatile unsigned int*)(0x42CA017CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL2          *((volatile unsigned int*)(0x42CA0188UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL3          *((volatile unsigned int*)(0x42CA018CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL4          *((volatile unsigned int*)(0x42CA0190UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL5          *((volatile unsigned int*)(0x42CA0194UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL6          *((volatile unsigned int*)(0x42CA0198UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL7          *((volatile unsigned int*)(0x42CA019CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL8          *((volatile unsigned int*)(0x42CA01A0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL9          *((volatile unsigned int*)(0x42CA01A4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL10         *((volatile unsigned int*)(0x42CA01A8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL11         *((volatile unsigned int*)(0x42CA01ACUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL12         *((volatile unsigned int*)(0x42CA01B0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL13         *((volatile unsigned int*)(0x42CA01B4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL14         *((volatile unsigned int*)(0x42CA01B8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL15         *((volatile unsigned int*)(0x42CA01BCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL16         *((volatile unsigned int*)(0x42CA01C0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL17         *((volatile unsigned int*)(0x42CA01C4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL18         *((volatile unsigned int*)(0x42CA01C8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL19         *((volatile unsigned int*)(0x42CA01CCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL20         *((volatile unsigned int*)(0x42CA01D0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL21         *((volatile unsigned int*)(0x42CA01D4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL22         *((volatile unsigned int*)(0x42CA01D8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL23         *((volatile unsigned int*)(0x42CA01DCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL24         *((volatile unsigned int*)(0x42CA01E0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL25         *((volatile unsigned int*)(0x42CA01E4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL26         *((volatile unsigned int*)(0x42CA01E8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL27         *((volatile unsigned int*)(0x42CA01ECUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL28         *((volatile unsigned int*)(0x42CA01F0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL29         *((volatile unsigned int*)(0x42CA01F4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL30         *((volatile unsigned int*)(0x42CA01F8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL31         *((volatile unsigned int*)(0x42CA01FCUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL2          *((volatile unsigned int*)(0x42CA0208UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL3          *((volatile unsigned int*)(0x42CA020CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL4          *((volatile unsigned int*)(0x42CA0210UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL5          *((volatile unsigned int*)(0x42CA0214UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL6          *((volatile unsigned int*)(0x42CA0218UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL7          *((volatile unsigned int*)(0x42CA021CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL8          *((volatile unsigned int*)(0x42CA0220UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL9          *((volatile unsigned int*)(0x42CA0224UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL10         *((volatile unsigned int*)(0x42CA0228UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL11         *((volatile unsigned int*)(0x42CA022CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL12         *((volatile unsigned int*)(0x42CA0230UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL13         *((volatile unsigned int*)(0x42CA0234UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL14         *((volatile unsigned int*)(0x42CA0238UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL15         *((volatile unsigned int*)(0x42CA023CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL16         *((volatile unsigned int*)(0x42CA0240UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL17         *((volatile unsigned int*)(0x42CA0244UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL18         *((volatile unsigned int*)(0x42CA0248UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL19         *((volatile unsigned int*)(0x42CA024CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL20         *((volatile unsigned int*)(0x42CA0250UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL21         *((volatile unsigned int*)(0x42CA0254UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL22         *((volatile unsigned int*)(0x42CA0258UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL23         *((volatile unsigned int*)(0x42CA025CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL24         *((volatile unsigned int*)(0x42CA0260UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL25         *((volatile unsigned int*)(0x42CA0264UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL26         *((volatile unsigned int*)(0x42CA0268UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL27         *((volatile unsigned int*)(0x42CA026CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL28         *((volatile unsigned int*)(0x42CA0270UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL29         *((volatile unsigned int*)(0x42CA0274UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL30         *((volatile unsigned int*)(0x42CA0278UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL31         *((volatile unsigned int*)(0x42CA027CUL))
+#define bFM3_ETHERNET_MAC0_SR_TI               *((volatile unsigned int*)(0x42CA0280UL))
+#define bFM3_ETHERNET_MAC0_SR_TPS              *((volatile unsigned int*)(0x42CA0284UL))
+#define bFM3_ETHERNET_MAC0_SR_TU               *((volatile unsigned int*)(0x42CA0288UL))
+#define bFM3_ETHERNET_MAC0_SR_TJT              *((volatile unsigned int*)(0x42CA028CUL))
+#define bFM3_ETHERNET_MAC0_SR_OVF              *((volatile unsigned int*)(0x42CA0290UL))
+#define bFM3_ETHERNET_MAC0_SR_UNF              *((volatile unsigned int*)(0x42CA0294UL))
+#define bFM3_ETHERNET_MAC0_SR_RI               *((volatile unsigned int*)(0x42CA0298UL))
+#define bFM3_ETHERNET_MAC0_SR_RU               *((volatile unsigned int*)(0x42CA029CUL))
+#define bFM3_ETHERNET_MAC0_SR_RPS              *((volatile unsigned int*)(0x42CA02A0UL))
+#define bFM3_ETHERNET_MAC0_SR_RWT              *((volatile unsigned int*)(0x42CA02A4UL))
+#define bFM3_ETHERNET_MAC0_SR_ETI              *((volatile unsigned int*)(0x42CA02A8UL))
+#define bFM3_ETHERNET_MAC0_SR_FBI              *((volatile unsigned int*)(0x42CA02B4UL))
+#define bFM3_ETHERNET_MAC0_SR_ERI              *((volatile unsigned int*)(0x42CA02B8UL))
+#define bFM3_ETHERNET_MAC0_SR_AIS              *((volatile unsigned int*)(0x42CA02BCUL))
+#define bFM3_ETHERNET_MAC0_SR_NIS              *((volatile unsigned int*)(0x42CA02C0UL))
+#define bFM3_ETHERNET_MAC0_SR_RS0              *((volatile unsigned int*)(0x42CA02C4UL))
+#define bFM3_ETHERNET_MAC0_SR_RS1              *((volatile unsigned int*)(0x42CA02C8UL))
+#define bFM3_ETHERNET_MAC0_SR_RS2              *((volatile unsigned int*)(0x42CA02CCUL))
+#define bFM3_ETHERNET_MAC0_SR_TS0              *((volatile unsigned int*)(0x42CA02D0UL))
+#define bFM3_ETHERNET_MAC0_SR_TS1              *((volatile unsigned int*)(0x42CA02D4UL))
+#define bFM3_ETHERNET_MAC0_SR_TS2              *((volatile unsigned int*)(0x42CA02D8UL))
+#define bFM3_ETHERNET_MAC0_SR_EB0              *((volatile unsigned int*)(0x42CA02DCUL))
+#define bFM3_ETHERNET_MAC0_SR_EB1              *((volatile unsigned int*)(0x42CA02E0UL))
+#define bFM3_ETHERNET_MAC0_SR_EB2              *((volatile unsigned int*)(0x42CA02E4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLI              *((volatile unsigned int*)(0x42CA02E8UL))
+#define bFM3_ETHERNET_MAC0_SR_GMI              *((volatile unsigned int*)(0x42CA02ECUL))
+#define bFM3_ETHERNET_MAC0_SR_GPI              *((volatile unsigned int*)(0x42CA02F0UL))
+#define bFM3_ETHERNET_MAC0_SR_TTI              *((volatile unsigned int*)(0x42CA02F4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLPII            *((volatile unsigned int*)(0x42CA02F8UL))
+#define bFM3_ETHERNET_MAC0_OMR_SR              *((volatile unsigned int*)(0x42CA0304UL))
+#define bFM3_ETHERNET_MAC0_OMR_OSF             *((volatile unsigned int*)(0x42CA0308UL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC0            *((volatile unsigned int*)(0x42CA030CUL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC1            *((volatile unsigned int*)(0x42CA0310UL))
+#define bFM3_ETHERNET_MAC0_OMR_FUF             *((volatile unsigned int*)(0x42CA0318UL))
+#define bFM3_ETHERNET_MAC0_OMR_FEF             *((volatile unsigned int*)(0x42CA031CUL))
+#define bFM3_ETHERNET_MAC0_OMR_ST              *((volatile unsigned int*)(0x42CA0334UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC0            *((volatile unsigned int*)(0x42CA0338UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC1            *((volatile unsigned int*)(0x42CA033CUL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC2            *((volatile unsigned int*)(0x42CA0340UL))
+#define bFM3_ETHERNET_MAC0_OMR_FTF             *((volatile unsigned int*)(0x42CA0350UL))
+#define bFM3_ETHERNET_MAC0_OMR_TSF             *((volatile unsigned int*)(0x42CA0354UL))
+#define bFM3_ETHERNET_MAC0_OMR_DFF             *((volatile unsigned int*)(0x42CA0360UL))
+#define bFM3_ETHERNET_MAC0_OMR_RSF             *((volatile unsigned int*)(0x42CA0364UL))
+#define bFM3_ETHERNET_MAC0_OMR_DT              *((volatile unsigned int*)(0x42CA0368UL))
+#define bFM3_ETHERNET_MAC0_IER_TIE             *((volatile unsigned int*)(0x42CA0380UL))
+#define bFM3_ETHERNET_MAC0_IER_TSE             *((volatile unsigned int*)(0x42CA0384UL))
+#define bFM3_ETHERNET_MAC0_IER_TUE             *((volatile unsigned int*)(0x42CA0388UL))
+#define bFM3_ETHERNET_MAC0_IER_TJE             *((volatile unsigned int*)(0x42CA038CUL))
+#define bFM3_ETHERNET_MAC0_IER_OVE             *((volatile unsigned int*)(0x42CA0390UL))
+#define bFM3_ETHERNET_MAC0_IER_UNE             *((volatile unsigned int*)(0x42CA0394UL))
+#define bFM3_ETHERNET_MAC0_IER_RIE             *((volatile unsigned int*)(0x42CA0398UL))
+#define bFM3_ETHERNET_MAC0_IER_RUE             *((volatile unsigned int*)(0x42CA039CUL))
+#define bFM3_ETHERNET_MAC0_IER_RSE             *((volatile unsigned int*)(0x42CA03A0UL))
+#define bFM3_ETHERNET_MAC0_IER_RWE             *((volatile unsigned int*)(0x42CA03A4UL))
+#define bFM3_ETHERNET_MAC0_IER_ETE             *((volatile unsigned int*)(0x42CA03A8UL))
+#define bFM3_ETHERNET_MAC0_IER_FBE             *((volatile unsigned int*)(0x42CA03B4UL))
+#define bFM3_ETHERNET_MAC0_IER_ERE             *((volatile unsigned int*)(0x42CA03B8UL))
+#define bFM3_ETHERNET_MAC0_IER_AIE             *((volatile unsigned int*)(0x42CA03BCUL))
+#define bFM3_ETHERNET_MAC0_IER_NIE             *((volatile unsigned int*)(0x42CA03C0UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42CA0400UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42CA0404UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42CA0408UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42CA040CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42CA0410UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42CA0414UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42CA0418UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42CA041CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42CA0420UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42CA0424UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42CA0428UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42CA042CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42CA0430UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42CA0434UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42CA0438UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42CA043CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42CA0440UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42CA0444UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42CA0448UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42CA044CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42CA0450UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42CA0454UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42CA0458UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42CA045CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42CA0460UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42CA0464UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42CA0468UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42CA046CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42CA0470UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0         *((volatile unsigned int*)(0x42CA0480UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1         *((volatile unsigned int*)(0x42CA0484UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2         *((volatile unsigned int*)(0x42CA0488UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3         *((volatile unsigned int*)(0x42CA048CUL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4         *((volatile unsigned int*)(0x42CA0490UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5         *((volatile unsigned int*)(0x42CA0494UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6         *((volatile unsigned int*)(0x42CA0498UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7         *((volatile unsigned int*)(0x42CA049CUL))
+#define bFM3_ETHERNET_MAC0_AHBSR_AHBS          *((volatile unsigned int*)(0x42CA0580UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42CA0900UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42CA0904UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42CA0908UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42CA090CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42CA0910UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42CA0914UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42CA0918UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42CA091CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42CA0920UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42CA0924UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42CA0928UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42CA092CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42CA0930UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42CA0934UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42CA0938UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42CA093CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42CA0940UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42CA0944UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42CA0948UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42CA094CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42CA0950UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42CA0954UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42CA0958UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42CA095CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42CA0960UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42CA0964UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42CA0968UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42CA096CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42CA0970UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42CA0974UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42CA0978UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42CA097CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42CA0980UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42CA0984UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42CA0988UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42CA098CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42CA0990UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42CA0994UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42CA0998UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42CA099CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42CA09A0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42CA09A4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42CA09A8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42CA09ACUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42CA09B0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42CA09B4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42CA09B8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42CA09BCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42CA09C0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42CA09C4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42CA09C8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42CA09CCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42CA09D0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42CA09D4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42CA09D8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42CA09DCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42CA09E0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42CA09E4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42CA09E8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42CA09ECUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42CA09F0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42CA09F4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42CA09F8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42CA09FCUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42CA0A00UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42CA0A04UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42CA0A08UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42CA0A0CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42CA0A10UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42CA0A14UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42CA0A18UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42CA0A1CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42CA0A20UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42CA0A24UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42CA0A28UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42CA0A2CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42CA0A30UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42CA0A34UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42CA0A38UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42CA0A3CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42CA0A40UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42CA0A44UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42CA0A48UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42CA0A4CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42CA0A50UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42CA0A54UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42CA0A58UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42CA0A5CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42CA0A60UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42CA0A64UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42CA0A68UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42CA0A6CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42CA0A70UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42CA0A74UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42CA0A78UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42CA0A7CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42CA0A80UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42CA0A84UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42CA0A88UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42CA0A8CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42CA0A90UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42CA0A94UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42CA0A98UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42CA0A9CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42CA0AA0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42CA0AA4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42CA0AA8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42CA0AACUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42CA0AB0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42CA0AB4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42CA0AB8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42CA0ABCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42CA0AC0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42CA0AC4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42CA0AC8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42CA0ACCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42CA0AD0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42CA0AD4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42CA0AD8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42CA0ADCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42CA0AE0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42CA0AE4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42CA0AE8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42CA0AECUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42CA0AF0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42CA0AF4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42CA0AF8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42CA0AFCUL))
+
+/* ETHERNET-MAC-CONTROL registers */
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE  *((volatile unsigned int*)(0x42CC0000UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0    *((volatile unsigned int*)(0x42CC0020UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1    *((volatile unsigned int*)(0x42CC0024UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL  *((volatile unsigned int*)(0x42CC0070UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0  *((volatile unsigned int*)(0x42CC0100UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1  *((volatile unsigned int*)(0x42CC0104UL))
+
+/* ETHERNET-MAC1 registers*/
+#define bFM3_ETHERNET_MAC1_MCR_RE              *((volatile unsigned int*)(0x42CE0008UL))
+#define bFM3_ETHERNET_MAC1_MCR_TE              *((volatile unsigned int*)(0x42CE000CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DC              *((volatile unsigned int*)(0x42CE0010UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL0             *((volatile unsigned int*)(0x42CE0014UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL1             *((volatile unsigned int*)(0x42CE0018UL))
+#define bFM3_ETHERNET_MAC1_MCR_ACS             *((volatile unsigned int*)(0x42CE001CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LUD             *((volatile unsigned int*)(0x42CE0020UL))
+#define bFM3_ETHERNET_MAC1_MCR_DR              *((volatile unsigned int*)(0x42CE0024UL))
+#define bFM3_ETHERNET_MAC1_MCR_IPC             *((volatile unsigned int*)(0x42CE0028UL))
+#define bFM3_ETHERNET_MAC1_MCR_DM              *((volatile unsigned int*)(0x42CE002CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LM              *((volatile unsigned int*)(0x42CE0030UL))
+#define bFM3_ETHERNET_MAC1_MCR_DO              *((volatile unsigned int*)(0x42CE0034UL))
+#define bFM3_ETHERNET_MAC1_MCR_FES             *((volatile unsigned int*)(0x42CE0038UL))
+#define bFM3_ETHERNET_MAC1_MCR_PS              *((volatile unsigned int*)(0x42CE003CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DCRS            *((volatile unsigned int*)(0x42CE0040UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG0            *((volatile unsigned int*)(0x42CE0044UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG1            *((volatile unsigned int*)(0x42CE0048UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG2            *((volatile unsigned int*)(0x42CE004CUL))
+#define bFM3_ETHERNET_MAC1_MCR_JE              *((volatile unsigned int*)(0x42CE0050UL))
+#define bFM3_ETHERNET_MAC1_MCR_BE              *((volatile unsigned int*)(0x42CE0054UL))
+#define bFM3_ETHERNET_MAC1_MCR_JD              *((volatile unsigned int*)(0x42CE0058UL))
+#define bFM3_ETHERNET_MAC1_MCR_WD              *((volatile unsigned int*)(0x42CE005CUL))
+#define bFM3_ETHERNET_MAC1_MCR_TC              *((volatile unsigned int*)(0x42CE0060UL))
+#define bFM3_ETHERNET_MAC1_MCR_CST             *((volatile unsigned int*)(0x42CE0064UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PR             *((volatile unsigned int*)(0x42CE0080UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HUC            *((volatile unsigned int*)(0x42CE0084UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HMC            *((volatile unsigned int*)(0x42CE0088UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DAIF           *((volatile unsigned int*)(0x42CE008CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_PM             *((volatile unsigned int*)(0x42CE0090UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DB             *((volatile unsigned int*)(0x42CE0094UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF0           *((volatile unsigned int*)(0x42CE0098UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF1           *((volatile unsigned int*)(0x42CE009CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAIF           *((volatile unsigned int*)(0x42CE00A0UL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAF            *((volatile unsigned int*)(0x42CE00A4UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HPF            *((volatile unsigned int*)(0x42CE00A8UL))
+#define bFM3_ETHERNET_MAC1_MFFR_RA             *((volatile unsigned int*)(0x42CE00FCUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH0          *((volatile unsigned int*)(0x42CE0100UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH1          *((volatile unsigned int*)(0x42CE0104UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH2          *((volatile unsigned int*)(0x42CE0108UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH3          *((volatile unsigned int*)(0x42CE010CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH4          *((volatile unsigned int*)(0x42CE0110UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH5          *((volatile unsigned int*)(0x42CE0114UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH6          *((volatile unsigned int*)(0x42CE0118UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH7          *((volatile unsigned int*)(0x42CE011CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH8          *((volatile unsigned int*)(0x42CE0120UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH9          *((volatile unsigned int*)(0x42CE0124UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH10         *((volatile unsigned int*)(0x42CE0128UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH11         *((volatile unsigned int*)(0x42CE012CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH12         *((volatile unsigned int*)(0x42CE0130UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH13         *((volatile unsigned int*)(0x42CE0134UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH14         *((volatile unsigned int*)(0x42CE0138UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH15         *((volatile unsigned int*)(0x42CE013CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH16         *((volatile unsigned int*)(0x42CE0140UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH17         *((volatile unsigned int*)(0x42CE0144UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH18         *((volatile unsigned int*)(0x42CE0148UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH19         *((volatile unsigned int*)(0x42CE014CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH20         *((volatile unsigned int*)(0x42CE0150UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH21         *((volatile unsigned int*)(0x42CE0154UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH22         *((volatile unsigned int*)(0x42CE0158UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH23         *((volatile unsigned int*)(0x42CE015CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH24         *((volatile unsigned int*)(0x42CE0160UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH25         *((volatile unsigned int*)(0x42CE0164UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH26         *((volatile unsigned int*)(0x42CE0168UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH27         *((volatile unsigned int*)(0x42CE016CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH28         *((volatile unsigned int*)(0x42CE0170UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH29         *((volatile unsigned int*)(0x42CE0174UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH30         *((volatile unsigned int*)(0x42CE0178UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH31         *((volatile unsigned int*)(0x42CE017CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL0          *((volatile unsigned int*)(0x42CE0180UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL1          *((volatile unsigned int*)(0x42CE0184UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL2          *((volatile unsigned int*)(0x42CE0188UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL3          *((volatile unsigned int*)(0x42CE018CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL4          *((volatile unsigned int*)(0x42CE0190UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL5          *((volatile unsigned int*)(0x42CE0194UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL6          *((volatile unsigned int*)(0x42CE0198UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL7          *((volatile unsigned int*)(0x42CE019CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL8          *((volatile unsigned int*)(0x42CE01A0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL9          *((volatile unsigned int*)(0x42CE01A4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL10         *((volatile unsigned int*)(0x42CE01A8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL11         *((volatile unsigned int*)(0x42CE01ACUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL12         *((volatile unsigned int*)(0x42CE01B0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL13         *((volatile unsigned int*)(0x42CE01B4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL14         *((volatile unsigned int*)(0x42CE01B8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL15         *((volatile unsigned int*)(0x42CE01BCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL16         *((volatile unsigned int*)(0x42CE01C0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL17         *((volatile unsigned int*)(0x42CE01C4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL18         *((volatile unsigned int*)(0x42CE01C8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL19         *((volatile unsigned int*)(0x42CE01CCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL20         *((volatile unsigned int*)(0x42CE01D0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL21         *((volatile unsigned int*)(0x42CE01D4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL22         *((volatile unsigned int*)(0x42CE01D8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL23         *((volatile unsigned int*)(0x42CE01DCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL24         *((volatile unsigned int*)(0x42CE01E0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL25         *((volatile unsigned int*)(0x42CE01E4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL26         *((volatile unsigned int*)(0x42CE01E8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL27         *((volatile unsigned int*)(0x42CE01ECUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL28         *((volatile unsigned int*)(0x42CE01F0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL29         *((volatile unsigned int*)(0x42CE01F4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL30         *((volatile unsigned int*)(0x42CE01F8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL31         *((volatile unsigned int*)(0x42CE01FCUL))
+#define bFM3_ETHERNET_MAC1_GAR_GB              *((volatile unsigned int*)(0x42CE0200UL))
+#define bFM3_ETHERNET_MAC1_GAR_GW              *((volatile unsigned int*)(0x42CE0204UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR0             *((volatile unsigned int*)(0x42CE0208UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR1             *((volatile unsigned int*)(0x42CE020CUL))
+#define bFM3_ETHERNET_MAC1_GAR_CR2             *((volatile unsigned int*)(0x42CE0210UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR3             *((volatile unsigned int*)(0x42CE0214UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR0             *((volatile unsigned int*)(0x42CE0218UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR1             *((volatile unsigned int*)(0x42CE021CUL))
+#define bFM3_ETHERNET_MAC1_GAR_GR2             *((volatile unsigned int*)(0x42CE0220UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR3             *((volatile unsigned int*)(0x42CE0224UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR4             *((volatile unsigned int*)(0x42CE0228UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA0             *((volatile unsigned int*)(0x42CE022CUL))
+#define bFM3_ETHERNET_MAC1_GAR_PA1             *((volatile unsigned int*)(0x42CE0230UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA2             *((volatile unsigned int*)(0x42CE0234UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA3             *((volatile unsigned int*)(0x42CE0238UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA4             *((volatile unsigned int*)(0x42CE023CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD0             *((volatile unsigned int*)(0x42CE0280UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD1             *((volatile unsigned int*)(0x42CE0284UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD2             *((volatile unsigned int*)(0x42CE0288UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD3             *((volatile unsigned int*)(0x42CE028CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD4             *((volatile unsigned int*)(0x42CE0290UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD5             *((volatile unsigned int*)(0x42CE0294UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD6             *((volatile unsigned int*)(0x42CE0298UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD7             *((volatile unsigned int*)(0x42CE029CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD8             *((volatile unsigned int*)(0x42CE02A0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD9             *((volatile unsigned int*)(0x42CE02A4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD10            *((volatile unsigned int*)(0x42CE02A8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD11            *((volatile unsigned int*)(0x42CE02ACUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD12            *((volatile unsigned int*)(0x42CE02B0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD13            *((volatile unsigned int*)(0x42CE02B4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD14            *((volatile unsigned int*)(0x42CE02B8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD15            *((volatile unsigned int*)(0x42CE02BCUL))
+#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA         *((volatile unsigned int*)(0x42CE0300UL))
+#define bFM3_ETHERNET_MAC1_FCR_TFE             *((volatile unsigned int*)(0x42CE0304UL))
+#define bFM3_ETHERNET_MAC1_FCR_RFE             *((volatile unsigned int*)(0x42CE0308UL))
+#define bFM3_ETHERNET_MAC1_FCR_UP              *((volatile unsigned int*)(0x42CE030CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT0            *((volatile unsigned int*)(0x42CE0310UL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT1            *((volatile unsigned int*)(0x42CE0314UL))
+#define bFM3_ETHERNET_MAC1_FCR_DZPQ            *((volatile unsigned int*)(0x42CE031CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT0             *((volatile unsigned int*)(0x42CE0340UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT1             *((volatile unsigned int*)(0x42CE0344UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT2             *((volatile unsigned int*)(0x42CE0348UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT3             *((volatile unsigned int*)(0x42CE034CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT4             *((volatile unsigned int*)(0x42CE0350UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT5             *((volatile unsigned int*)(0x42CE0354UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT6             *((volatile unsigned int*)(0x42CE0358UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT7             *((volatile unsigned int*)(0x42CE035CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT8             *((volatile unsigned int*)(0x42CE0360UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT9             *((volatile unsigned int*)(0x42CE0364UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT10            *((volatile unsigned int*)(0x42CE0368UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT11            *((volatile unsigned int*)(0x42CE036CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT12            *((volatile unsigned int*)(0x42CE0370UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT13            *((volatile unsigned int*)(0x42CE0374UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT14            *((volatile unsigned int*)(0x42CE0378UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT15            *((volatile unsigned int*)(0x42CE037CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL0             *((volatile unsigned int*)(0x42CE0380UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL1             *((volatile unsigned int*)(0x42CE0384UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL2             *((volatile unsigned int*)(0x42CE0388UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL3             *((volatile unsigned int*)(0x42CE038CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL4             *((volatile unsigned int*)(0x42CE0390UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL5             *((volatile unsigned int*)(0x42CE0394UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL6             *((volatile unsigned int*)(0x42CE0398UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL7             *((volatile unsigned int*)(0x42CE039CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL8             *((volatile unsigned int*)(0x42CE03A0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL9             *((volatile unsigned int*)(0x42CE03A4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL10            *((volatile unsigned int*)(0x42CE03A8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL11            *((volatile unsigned int*)(0x42CE03ACUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL12            *((volatile unsigned int*)(0x42CE03B0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL13            *((volatile unsigned int*)(0x42CE03B4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL14            *((volatile unsigned int*)(0x42CE03B8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL15            *((volatile unsigned int*)(0x42CE03BCUL))
+#define bFM3_ETHERNET_MAC1_VTR_ETV             *((volatile unsigned int*)(0x42CE03C0UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42CE0500UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42CE0504UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42CE0508UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42CE050CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42CE0510UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42CE0514UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42CE0518UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42CE051CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42CE0520UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42CE0524UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42CE0528UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42CE052CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42CE0530UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42CE0534UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42CE0538UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42CE053CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42CE0540UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42CE0544UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42CE0548UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42CE054CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42CE0550UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42CE0554UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42CE0558UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42CE055CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42CE0560UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42CE0564UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42CE0568UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42CE056CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42CE0570UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42CE0574UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42CE0578UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42CE057CUL))
+#define bFM3_ETHERNET_MAC1_PMTR_PD             *((volatile unsigned int*)(0x42CE0580UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPE            *((volatile unsigned int*)(0x42CE0584UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WFE            *((volatile unsigned int*)(0x42CE0588UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPR            *((volatile unsigned int*)(0x42CE0594UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WPR            *((volatile unsigned int*)(0x42CE0598UL))
+#define bFM3_ETHERNET_MAC1_PMTR_GU             *((volatile unsigned int*)(0x42CE05A4UL))
+#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42CE05FCUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42CE0600UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42CE0604UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42CE0608UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42CE060CUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST       *((volatile unsigned int*)(0x42CE0620UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST       *((volatile unsigned int*)(0x42CE0624UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN        *((volatile unsigned int*)(0x42CE0640UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLS          *((volatile unsigned int*)(0x42CE0644UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN        *((volatile unsigned int*)(0x42CE0648UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA       *((volatile unsigned int*)(0x42CE064CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT0         *((volatile unsigned int*)(0x42CE0680UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT1         *((volatile unsigned int*)(0x42CE0684UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT2         *((volatile unsigned int*)(0x42CE0688UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT3         *((volatile unsigned int*)(0x42CE068CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT4         *((volatile unsigned int*)(0x42CE0690UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT5         *((volatile unsigned int*)(0x42CE0694UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT6         *((volatile unsigned int*)(0x42CE0698UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT7         *((volatile unsigned int*)(0x42CE069CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT8         *((volatile unsigned int*)(0x42CE06A0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT9         *((volatile unsigned int*)(0x42CE06A4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT10        *((volatile unsigned int*)(0x42CE06A8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT11        *((volatile unsigned int*)(0x42CE06ACUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT12        *((volatile unsigned int*)(0x42CE06B0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT13        *((volatile unsigned int*)(0x42CE06B4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT14        *((volatile unsigned int*)(0x42CE06B8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT15        *((volatile unsigned int*)(0x42CE06BCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT0         *((volatile unsigned int*)(0x42CE06C0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT1         *((volatile unsigned int*)(0x42CE06C4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT2         *((volatile unsigned int*)(0x42CE06C8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT3         *((volatile unsigned int*)(0x42CE06CCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT4         *((volatile unsigned int*)(0x42CE06D0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT5         *((volatile unsigned int*)(0x42CE06D4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT6         *((volatile unsigned int*)(0x42CE06D8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT7         *((volatile unsigned int*)(0x42CE06DCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT8         *((volatile unsigned int*)(0x42CE06E0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT9         *((volatile unsigned int*)(0x42CE06E4UL))
+#define bFM3_ETHERNET_MAC1_ISR_RGIS            *((volatile unsigned int*)(0x42CE0700UL))
+#define bFM3_ETHERNET_MAC1_ISR_PIS             *((volatile unsigned int*)(0x42CE070CUL))
+#define bFM3_ETHERNET_MAC1_ISR_MIS             *((volatile unsigned int*)(0x42CE0710UL))
+#define bFM3_ETHERNET_MAC1_ISR_RIS             *((volatile unsigned int*)(0x42CE0714UL))
+#define bFM3_ETHERNET_MAC1_ISR_TIS             *((volatile unsigned int*)(0x42CE0718UL))
+#define bFM3_ETHERNET_MAC1_ISR_COIS            *((volatile unsigned int*)(0x42CE071CUL))
+#define bFM3_ETHERNET_MAC1_ISR_TSIS            *((volatile unsigned int*)(0x42CE0724UL))
+#define bFM3_ETHERNET_MAC1_ISR_LPIIS           *((volatile unsigned int*)(0x42CE0728UL))
+#define bFM3_ETHERNET_MAC1_IMR_RGIM            *((volatile unsigned int*)(0x42CE0780UL))
+#define bFM3_ETHERNET_MAC1_IMR_PIM             *((volatile unsigned int*)(0x42CE078CUL))
+#define bFM3_ETHERNET_MAC1_IMR_TSIM            *((volatile unsigned int*)(0x42CE0794UL))
+#define bFM3_ETHERNET_MAC1_IMR_LPIIM           *((volatile unsigned int*)(0x42CE0798UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A32           *((volatile unsigned int*)(0x42CE0800UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A33           *((volatile unsigned int*)(0x42CE0804UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A34           *((volatile unsigned int*)(0x42CE0808UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A35           *((volatile unsigned int*)(0x42CE080CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A36           *((volatile unsigned int*)(0x42CE0810UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A37           *((volatile unsigned int*)(0x42CE0814UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A38           *((volatile unsigned int*)(0x42CE0818UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A39           *((volatile unsigned int*)(0x42CE081CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A40           *((volatile unsigned int*)(0x42CE0820UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A41           *((volatile unsigned int*)(0x42CE0824UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A42           *((volatile unsigned int*)(0x42CE0828UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A43           *((volatile unsigned int*)(0x42CE082CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A44           *((volatile unsigned int*)(0x42CE0830UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A45           *((volatile unsigned int*)(0x42CE0834UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A46           *((volatile unsigned int*)(0x42CE0838UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A47           *((volatile unsigned int*)(0x42CE083CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_MO            *((volatile unsigned int*)(0x42CE087CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A0            *((volatile unsigned int*)(0x42CE0880UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A1            *((volatile unsigned int*)(0x42CE0884UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A2            *((volatile unsigned int*)(0x42CE0888UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A3            *((volatile unsigned int*)(0x42CE088CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A4            *((volatile unsigned int*)(0x42CE0890UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A5            *((volatile unsigned int*)(0x42CE0894UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A6            *((volatile unsigned int*)(0x42CE0898UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A7            *((volatile unsigned int*)(0x42CE089CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A8            *((volatile unsigned int*)(0x42CE08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A9            *((volatile unsigned int*)(0x42CE08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A10           *((volatile unsigned int*)(0x42CE08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A11           *((volatile unsigned int*)(0x42CE08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A12           *((volatile unsigned int*)(0x42CE08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A13           *((volatile unsigned int*)(0x42CE08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A14           *((volatile unsigned int*)(0x42CE08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A15           *((volatile unsigned int*)(0x42CE08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A16           *((volatile unsigned int*)(0x42CE08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A17           *((volatile unsigned int*)(0x42CE08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A18           *((volatile unsigned int*)(0x42CE08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A19           *((volatile unsigned int*)(0x42CE08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A20           *((volatile unsigned int*)(0x42CE08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A21           *((volatile unsigned int*)(0x42CE08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A22           *((volatile unsigned int*)(0x42CE08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A23           *((volatile unsigned int*)(0x42CE08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A24           *((volatile unsigned int*)(0x42CE08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A25           *((volatile unsigned int*)(0x42CE08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A26           *((volatile unsigned int*)(0x42CE08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A27           *((volatile unsigned int*)(0x42CE08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A28           *((volatile unsigned int*)(0x42CE08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A29           *((volatile unsigned int*)(0x42CE08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A30           *((volatile unsigned int*)(0x42CE08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A31           *((volatile unsigned int*)(0x42CE08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A32           *((volatile unsigned int*)(0x42CE0900UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A33           *((volatile unsigned int*)(0x42CE0904UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A34           *((volatile unsigned int*)(0x42CE0908UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A35           *((volatile unsigned int*)(0x42CE090CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A36           *((volatile unsigned int*)(0x42CE0910UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A37           *((volatile unsigned int*)(0x42CE0914UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A38           *((volatile unsigned int*)(0x42CE0918UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A39           *((volatile unsigned int*)(0x42CE091CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A40           *((volatile unsigned int*)(0x42CE0920UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A41           *((volatile unsigned int*)(0x42CE0924UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A42           *((volatile unsigned int*)(0x42CE0928UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A43           *((volatile unsigned int*)(0x42CE092CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A44           *((volatile unsigned int*)(0x42CE0930UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A45           *((volatile unsigned int*)(0x42CE0934UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A46           *((volatile unsigned int*)(0x42CE0938UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A47           *((volatile unsigned int*)(0x42CE093CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC0          *((volatile unsigned int*)(0x42CE0960UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC1          *((volatile unsigned int*)(0x42CE0964UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC2          *((volatile unsigned int*)(0x42CE0968UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC3          *((volatile unsigned int*)(0x42CE096CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC4          *((volatile unsigned int*)(0x42CE0970UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC5          *((volatile unsigned int*)(0x42CE0974UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_SA            *((volatile unsigned int*)(0x42CE0978UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_AE            *((volatile unsigned int*)(0x42CE097CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A0            *((volatile unsigned int*)(0x42CE0980UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A1            *((volatile unsigned int*)(0x42CE0984UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A2            *((volatile unsigned int*)(0x42CE0988UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A3            *((volatile unsigned int*)(0x42CE098CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A4            *((volatile unsigned int*)(0x42CE0990UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A5            *((volatile unsigned int*)(0x42CE0994UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A6            *((volatile unsigned int*)(0x42CE0998UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A7            *((volatile unsigned int*)(0x42CE099CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A8            *((volatile unsigned int*)(0x42CE09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A9            *((volatile unsigned int*)(0x42CE09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A10           *((volatile unsigned int*)(0x42CE09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A11           *((volatile unsigned int*)(0x42CE09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A12           *((volatile unsigned int*)(0x42CE09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A13           *((volatile unsigned int*)(0x42CE09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A14           *((volatile unsigned int*)(0x42CE09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A15           *((volatile unsigned int*)(0x42CE09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A16           *((volatile unsigned int*)(0x42CE09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A17           *((volatile unsigned int*)(0x42CE09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A18           *((volatile unsigned int*)(0x42CE09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A19           *((volatile unsigned int*)(0x42CE09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A20           *((volatile unsigned int*)(0x42CE09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A21           *((volatile unsigned int*)(0x42CE09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A22           *((volatile unsigned int*)(0x42CE09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A23           *((volatile unsigned int*)(0x42CE09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A24           *((volatile unsigned int*)(0x42CE09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A25           *((volatile unsigned int*)(0x42CE09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A26           *((volatile unsigned int*)(0x42CE09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A27           *((volatile unsigned int*)(0x42CE09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A28           *((volatile unsigned int*)(0x42CE09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A29           *((volatile unsigned int*)(0x42CE09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A30           *((volatile unsigned int*)(0x42CE09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A31           *((volatile unsigned int*)(0x42CE09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A32           *((volatile unsigned int*)(0x42CE0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A33           *((volatile unsigned int*)(0x42CE0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A34           *((volatile unsigned int*)(0x42CE0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A35           *((volatile unsigned int*)(0x42CE0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A36           *((volatile unsigned int*)(0x42CE0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A37           *((volatile unsigned int*)(0x42CE0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A38           *((volatile unsigned int*)(0x42CE0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A39           *((volatile unsigned int*)(0x42CE0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A40           *((volatile unsigned int*)(0x42CE0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A41           *((volatile unsigned int*)(0x42CE0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A42           *((volatile unsigned int*)(0x42CE0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A43           *((volatile unsigned int*)(0x42CE0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A44           *((volatile unsigned int*)(0x42CE0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A45           *((volatile unsigned int*)(0x42CE0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A46           *((volatile unsigned int*)(0x42CE0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A47           *((volatile unsigned int*)(0x42CE0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC0          *((volatile unsigned int*)(0x42CE0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC1          *((volatile unsigned int*)(0x42CE0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC2          *((volatile unsigned int*)(0x42CE0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC3          *((volatile unsigned int*)(0x42CE0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC4          *((volatile unsigned int*)(0x42CE0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC5          *((volatile unsigned int*)(0x42CE0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_SA            *((volatile unsigned int*)(0x42CE0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_AE            *((volatile unsigned int*)(0x42CE0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A0            *((volatile unsigned int*)(0x42CE0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A1            *((volatile unsigned int*)(0x42CE0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A2            *((volatile unsigned int*)(0x42CE0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A3            *((volatile unsigned int*)(0x42CE0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A4            *((volatile unsigned int*)(0x42CE0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A5            *((volatile unsigned int*)(0x42CE0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A6            *((volatile unsigned int*)(0x42CE0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A7            *((volatile unsigned int*)(0x42CE0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A8            *((volatile unsigned int*)(0x42CE0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A9            *((volatile unsigned int*)(0x42CE0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A10           *((volatile unsigned int*)(0x42CE0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A11           *((volatile unsigned int*)(0x42CE0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A12           *((volatile unsigned int*)(0x42CE0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A13           *((volatile unsigned int*)(0x42CE0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A14           *((volatile unsigned int*)(0x42CE0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A15           *((volatile unsigned int*)(0x42CE0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A16           *((volatile unsigned int*)(0x42CE0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A17           *((volatile unsigned int*)(0x42CE0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A18           *((volatile unsigned int*)(0x42CE0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A19           *((volatile unsigned int*)(0x42CE0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A20           *((volatile unsigned int*)(0x42CE0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A21           *((volatile unsigned int*)(0x42CE0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A22           *((volatile unsigned int*)(0x42CE0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A23           *((volatile unsigned int*)(0x42CE0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A24           *((volatile unsigned int*)(0x42CE0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A25           *((volatile unsigned int*)(0x42CE0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A26           *((volatile unsigned int*)(0x42CE0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A27           *((volatile unsigned int*)(0x42CE0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A28           *((volatile unsigned int*)(0x42CE0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A29           *((volatile unsigned int*)(0x42CE0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A30           *((volatile unsigned int*)(0x42CE0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A31           *((volatile unsigned int*)(0x42CE0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A32           *((volatile unsigned int*)(0x42CE0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A33           *((volatile unsigned int*)(0x42CE0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A34           *((volatile unsigned int*)(0x42CE0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A35           *((volatile unsigned int*)(0x42CE0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A36           *((volatile unsigned int*)(0x42CE0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A37           *((volatile unsigned int*)(0x42CE0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A38           *((volatile unsigned int*)(0x42CE0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A39           *((volatile unsigned int*)(0x42CE0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A40           *((volatile unsigned int*)(0x42CE0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A41           *((volatile unsigned int*)(0x42CE0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A42           *((volatile unsigned int*)(0x42CE0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A43           *((volatile unsigned int*)(0x42CE0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A44           *((volatile unsigned int*)(0x42CE0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A45           *((volatile unsigned int*)(0x42CE0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A46           *((volatile unsigned int*)(0x42CE0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A47           *((volatile unsigned int*)(0x42CE0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC0          *((volatile unsigned int*)(0x42CE0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC1          *((volatile unsigned int*)(0x42CE0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC2          *((volatile unsigned int*)(0x42CE0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC3          *((volatile unsigned int*)(0x42CE0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC4          *((volatile unsigned int*)(0x42CE0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC5          *((volatile unsigned int*)(0x42CE0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_SA            *((volatile unsigned int*)(0x42CE0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_AE            *((volatile unsigned int*)(0x42CE0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A0            *((volatile unsigned int*)(0x42CE0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A1            *((volatile unsigned int*)(0x42CE0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A2            *((volatile unsigned int*)(0x42CE0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A3            *((volatile unsigned int*)(0x42CE0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A4            *((volatile unsigned int*)(0x42CE0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A5            *((volatile unsigned int*)(0x42CE0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A6            *((volatile unsigned int*)(0x42CE0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A7            *((volatile unsigned int*)(0x42CE0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A8            *((volatile unsigned int*)(0x42CE0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A9            *((volatile unsigned int*)(0x42CE0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A10           *((volatile unsigned int*)(0x42CE0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A11           *((volatile unsigned int*)(0x42CE0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A12           *((volatile unsigned int*)(0x42CE0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A13           *((volatile unsigned int*)(0x42CE0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A14           *((volatile unsigned int*)(0x42CE0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A15           *((volatile unsigned int*)(0x42CE0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A16           *((volatile unsigned int*)(0x42CE0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A17           *((volatile unsigned int*)(0x42CE0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A18           *((volatile unsigned int*)(0x42CE0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A19           *((volatile unsigned int*)(0x42CE0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A20           *((volatile unsigned int*)(0x42CE0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A21           *((volatile unsigned int*)(0x42CE0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A22           *((volatile unsigned int*)(0x42CE0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A23           *((volatile unsigned int*)(0x42CE0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A24           *((volatile unsigned int*)(0x42CE0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A25           *((volatile unsigned int*)(0x42CE0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A26           *((volatile unsigned int*)(0x42CE0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A27           *((volatile unsigned int*)(0x42CE0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A28           *((volatile unsigned int*)(0x42CE0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A29           *((volatile unsigned int*)(0x42CE0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A30           *((volatile unsigned int*)(0x42CE0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A31           *((volatile unsigned int*)(0x42CE0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A32           *((volatile unsigned int*)(0x42CE0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A33           *((volatile unsigned int*)(0x42CE0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A34           *((volatile unsigned int*)(0x42CE0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A35           *((volatile unsigned int*)(0x42CE0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A36           *((volatile unsigned int*)(0x42CE0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A37           *((volatile unsigned int*)(0x42CE0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A38           *((volatile unsigned int*)(0x42CE0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A39           *((volatile unsigned int*)(0x42CE0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A40           *((volatile unsigned int*)(0x42CE0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A41           *((volatile unsigned int*)(0x42CE0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A42           *((volatile unsigned int*)(0x42CE0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A43           *((volatile unsigned int*)(0x42CE0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A44           *((volatile unsigned int*)(0x42CE0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A45           *((volatile unsigned int*)(0x42CE0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A46           *((volatile unsigned int*)(0x42CE0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A47           *((volatile unsigned int*)(0x42CE0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC0          *((volatile unsigned int*)(0x42CE0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC1          *((volatile unsigned int*)(0x42CE0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC2          *((volatile unsigned int*)(0x42CE0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC3          *((volatile unsigned int*)(0x42CE0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC4          *((volatile unsigned int*)(0x42CE0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC5          *((volatile unsigned int*)(0x42CE0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_SA            *((volatile unsigned int*)(0x42CE0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_AE            *((volatile unsigned int*)(0x42CE0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A0            *((volatile unsigned int*)(0x42CE0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A1            *((volatile unsigned int*)(0x42CE0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A2            *((volatile unsigned int*)(0x42CE0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A3            *((volatile unsigned int*)(0x42CE0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A4            *((volatile unsigned int*)(0x42CE0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A5            *((volatile unsigned int*)(0x42CE0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A6            *((volatile unsigned int*)(0x42CE0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A7            *((volatile unsigned int*)(0x42CE0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A8            *((volatile unsigned int*)(0x42CE0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A9            *((volatile unsigned int*)(0x42CE0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A10           *((volatile unsigned int*)(0x42CE0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A11           *((volatile unsigned int*)(0x42CE0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A12           *((volatile unsigned int*)(0x42CE0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A13           *((volatile unsigned int*)(0x42CE0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A14           *((volatile unsigned int*)(0x42CE0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A15           *((volatile unsigned int*)(0x42CE0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A16           *((volatile unsigned int*)(0x42CE0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A17           *((volatile unsigned int*)(0x42CE0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A18           *((volatile unsigned int*)(0x42CE0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A19           *((volatile unsigned int*)(0x42CE0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A20           *((volatile unsigned int*)(0x42CE0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A21           *((volatile unsigned int*)(0x42CE0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A22           *((volatile unsigned int*)(0x42CE0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A23           *((volatile unsigned int*)(0x42CE0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A24           *((volatile unsigned int*)(0x42CE0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A25           *((volatile unsigned int*)(0x42CE0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A26           *((volatile unsigned int*)(0x42CE0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A27           *((volatile unsigned int*)(0x42CE0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A28           *((volatile unsigned int*)(0x42CE0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A29           *((volatile unsigned int*)(0x42CE0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A30           *((volatile unsigned int*)(0x42CE0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A31           *((volatile unsigned int*)(0x42CE0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A32           *((volatile unsigned int*)(0x42CE0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A33           *((volatile unsigned int*)(0x42CE0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A34           *((volatile unsigned int*)(0x42CE0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A35           *((volatile unsigned int*)(0x42CE0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A36           *((volatile unsigned int*)(0x42CE0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A37           *((volatile unsigned int*)(0x42CE0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A38           *((volatile unsigned int*)(0x42CE0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A39           *((volatile unsigned int*)(0x42CE0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A40           *((volatile unsigned int*)(0x42CE0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A41           *((volatile unsigned int*)(0x42CE0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A42           *((volatile unsigned int*)(0x42CE0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A43           *((volatile unsigned int*)(0x42CE0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A44           *((volatile unsigned int*)(0x42CE0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A45           *((volatile unsigned int*)(0x42CE0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A46           *((volatile unsigned int*)(0x42CE0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A47           *((volatile unsigned int*)(0x42CE0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC0          *((volatile unsigned int*)(0x42CE0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC1          *((volatile unsigned int*)(0x42CE0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC2          *((volatile unsigned int*)(0x42CE0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC3          *((volatile unsigned int*)(0x42CE0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC4          *((volatile unsigned int*)(0x42CE0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC5          *((volatile unsigned int*)(0x42CE0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_SA            *((volatile unsigned int*)(0x42CE0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_AE            *((volatile unsigned int*)(0x42CE0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A0            *((volatile unsigned int*)(0x42CE0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A1            *((volatile unsigned int*)(0x42CE0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A2            *((volatile unsigned int*)(0x42CE0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A3            *((volatile unsigned int*)(0x42CE0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A4            *((volatile unsigned int*)(0x42CE0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A5            *((volatile unsigned int*)(0x42CE0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A6            *((volatile unsigned int*)(0x42CE0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A7            *((volatile unsigned int*)(0x42CE0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A8            *((volatile unsigned int*)(0x42CE0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A9            *((volatile unsigned int*)(0x42CE0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A10           *((volatile unsigned int*)(0x42CE0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A11           *((volatile unsigned int*)(0x42CE0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A12           *((volatile unsigned int*)(0x42CE0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A13           *((volatile unsigned int*)(0x42CE0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A14           *((volatile unsigned int*)(0x42CE0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A15           *((volatile unsigned int*)(0x42CE0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A16           *((volatile unsigned int*)(0x42CE0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A17           *((volatile unsigned int*)(0x42CE0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A18           *((volatile unsigned int*)(0x42CE0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A19           *((volatile unsigned int*)(0x42CE0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A20           *((volatile unsigned int*)(0x42CE0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A21           *((volatile unsigned int*)(0x42CE0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A22           *((volatile unsigned int*)(0x42CE0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A23           *((volatile unsigned int*)(0x42CE0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A24           *((volatile unsigned int*)(0x42CE0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A25           *((volatile unsigned int*)(0x42CE0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A26           *((volatile unsigned int*)(0x42CE0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A27           *((volatile unsigned int*)(0x42CE0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A28           *((volatile unsigned int*)(0x42CE0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A29           *((volatile unsigned int*)(0x42CE0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A30           *((volatile unsigned int*)(0x42CE0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A31           *((volatile unsigned int*)(0x42CE0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A32           *((volatile unsigned int*)(0x42CE0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A33           *((volatile unsigned int*)(0x42CE0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A34           *((volatile unsigned int*)(0x42CE0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A35           *((volatile unsigned int*)(0x42CE0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A36           *((volatile unsigned int*)(0x42CE0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A37           *((volatile unsigned int*)(0x42CE0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A38           *((volatile unsigned int*)(0x42CE0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A39           *((volatile unsigned int*)(0x42CE0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A40           *((volatile unsigned int*)(0x42CE0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A41           *((volatile unsigned int*)(0x42CE0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A42           *((volatile unsigned int*)(0x42CE0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A43           *((volatile unsigned int*)(0x42CE0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A44           *((volatile unsigned int*)(0x42CE0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A45           *((volatile unsigned int*)(0x42CE0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A46           *((volatile unsigned int*)(0x42CE0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A47           *((volatile unsigned int*)(0x42CE0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC0          *((volatile unsigned int*)(0x42CE0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC1          *((volatile unsigned int*)(0x42CE0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC2          *((volatile unsigned int*)(0x42CE0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC3          *((volatile unsigned int*)(0x42CE0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC4          *((volatile unsigned int*)(0x42CE0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC5          *((volatile unsigned int*)(0x42CE0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_SA            *((volatile unsigned int*)(0x42CE0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_AE            *((volatile unsigned int*)(0x42CE0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A0            *((volatile unsigned int*)(0x42CE0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A1            *((volatile unsigned int*)(0x42CE0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A2            *((volatile unsigned int*)(0x42CE0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A3            *((volatile unsigned int*)(0x42CE0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A4            *((volatile unsigned int*)(0x42CE0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A5            *((volatile unsigned int*)(0x42CE0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A6            *((volatile unsigned int*)(0x42CE0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A7            *((volatile unsigned int*)(0x42CE0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A8            *((volatile unsigned int*)(0x42CE0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A9            *((volatile unsigned int*)(0x42CE0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A10           *((volatile unsigned int*)(0x42CE0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A11           *((volatile unsigned int*)(0x42CE0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A12           *((volatile unsigned int*)(0x42CE0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A13           *((volatile unsigned int*)(0x42CE0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A14           *((volatile unsigned int*)(0x42CE0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A15           *((volatile unsigned int*)(0x42CE0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A16           *((volatile unsigned int*)(0x42CE0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A17           *((volatile unsigned int*)(0x42CE0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A18           *((volatile unsigned int*)(0x42CE0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A19           *((volatile unsigned int*)(0x42CE0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A20           *((volatile unsigned int*)(0x42CE0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A21           *((volatile unsigned int*)(0x42CE0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A22           *((volatile unsigned int*)(0x42CE0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A23           *((volatile unsigned int*)(0x42CE0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A24           *((volatile unsigned int*)(0x42CE0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A25           *((volatile unsigned int*)(0x42CE0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A26           *((volatile unsigned int*)(0x42CE0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A27           *((volatile unsigned int*)(0x42CE0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A28           *((volatile unsigned int*)(0x42CE0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A29           *((volatile unsigned int*)(0x42CE0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A30           *((volatile unsigned int*)(0x42CE0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A31           *((volatile unsigned int*)(0x42CE0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A32           *((volatile unsigned int*)(0x42CE0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A33           *((volatile unsigned int*)(0x42CE0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A34           *((volatile unsigned int*)(0x42CE0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A35           *((volatile unsigned int*)(0x42CE0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A36           *((volatile unsigned int*)(0x42CE0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A37           *((volatile unsigned int*)(0x42CE0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A38           *((volatile unsigned int*)(0x42CE0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A39           *((volatile unsigned int*)(0x42CE0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A40           *((volatile unsigned int*)(0x42CE0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A41           *((volatile unsigned int*)(0x42CE0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A42           *((volatile unsigned int*)(0x42CE0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A43           *((volatile unsigned int*)(0x42CE0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A44           *((volatile unsigned int*)(0x42CE0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A45           *((volatile unsigned int*)(0x42CE0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A46           *((volatile unsigned int*)(0x42CE0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A47           *((volatile unsigned int*)(0x42CE0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC0          *((volatile unsigned int*)(0x42CE0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC1          *((volatile unsigned int*)(0x42CE0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC2          *((volatile unsigned int*)(0x42CE0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC3          *((volatile unsigned int*)(0x42CE0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC4          *((volatile unsigned int*)(0x42CE0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC5          *((volatile unsigned int*)(0x42CE0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_SA            *((volatile unsigned int*)(0x42CE0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_AE            *((volatile unsigned int*)(0x42CE0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A0            *((volatile unsigned int*)(0x42CE0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A1            *((volatile unsigned int*)(0x42CE0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A2            *((volatile unsigned int*)(0x42CE0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A3            *((volatile unsigned int*)(0x42CE0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A4            *((volatile unsigned int*)(0x42CE0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A5            *((volatile unsigned int*)(0x42CE0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A6            *((volatile unsigned int*)(0x42CE0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A7            *((volatile unsigned int*)(0x42CE0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A8            *((volatile unsigned int*)(0x42CE0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A9            *((volatile unsigned int*)(0x42CE0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A10           *((volatile unsigned int*)(0x42CE0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A11           *((volatile unsigned int*)(0x42CE0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A12           *((volatile unsigned int*)(0x42CE0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A13           *((volatile unsigned int*)(0x42CE0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A14           *((volatile unsigned int*)(0x42CE0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A15           *((volatile unsigned int*)(0x42CE0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A16           *((volatile unsigned int*)(0x42CE0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A17           *((volatile unsigned int*)(0x42CE0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A18           *((volatile unsigned int*)(0x42CE0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A19           *((volatile unsigned int*)(0x42CE0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A20           *((volatile unsigned int*)(0x42CE0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A21           *((volatile unsigned int*)(0x42CE0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A22           *((volatile unsigned int*)(0x42CE0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A23           *((volatile unsigned int*)(0x42CE0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A24           *((volatile unsigned int*)(0x42CE0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A25           *((volatile unsigned int*)(0x42CE0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A26           *((volatile unsigned int*)(0x42CE0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A27           *((volatile unsigned int*)(0x42CE0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A28           *((volatile unsigned int*)(0x42CE0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A29           *((volatile unsigned int*)(0x42CE0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A30           *((volatile unsigned int*)(0x42CE0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A31           *((volatile unsigned int*)(0x42CE0FFCUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A32           *((volatile unsigned int*)(0x42CE1000UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A33           *((volatile unsigned int*)(0x42CE1004UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A34           *((volatile unsigned int*)(0x42CE1008UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A35           *((volatile unsigned int*)(0x42CE100CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A36           *((volatile unsigned int*)(0x42CE1010UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A37           *((volatile unsigned int*)(0x42CE1014UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A38           *((volatile unsigned int*)(0x42CE1018UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A39           *((volatile unsigned int*)(0x42CE101CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A40           *((volatile unsigned int*)(0x42CE1020UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A41           *((volatile unsigned int*)(0x42CE1024UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A42           *((volatile unsigned int*)(0x42CE1028UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A43           *((volatile unsigned int*)(0x42CE102CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A44           *((volatile unsigned int*)(0x42CE1030UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A45           *((volatile unsigned int*)(0x42CE1034UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A46           *((volatile unsigned int*)(0x42CE1038UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A47           *((volatile unsigned int*)(0x42CE103CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC0          *((volatile unsigned int*)(0x42CE1060UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC1          *((volatile unsigned int*)(0x42CE1064UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC2          *((volatile unsigned int*)(0x42CE1068UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC3          *((volatile unsigned int*)(0x42CE106CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC4          *((volatile unsigned int*)(0x42CE1070UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC5          *((volatile unsigned int*)(0x42CE1074UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_SA            *((volatile unsigned int*)(0x42CE1078UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_AE            *((volatile unsigned int*)(0x42CE107CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A0            *((volatile unsigned int*)(0x42CE1080UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A1            *((volatile unsigned int*)(0x42CE1084UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A2            *((volatile unsigned int*)(0x42CE1088UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A3            *((volatile unsigned int*)(0x42CE108CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A4            *((volatile unsigned int*)(0x42CE1090UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A5            *((volatile unsigned int*)(0x42CE1094UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A6            *((volatile unsigned int*)(0x42CE1098UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A7            *((volatile unsigned int*)(0x42CE109CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A8            *((volatile unsigned int*)(0x42CE10A0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A9            *((volatile unsigned int*)(0x42CE10A4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A10           *((volatile unsigned int*)(0x42CE10A8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A11           *((volatile unsigned int*)(0x42CE10ACUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A12           *((volatile unsigned int*)(0x42CE10B0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A13           *((volatile unsigned int*)(0x42CE10B4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A14           *((volatile unsigned int*)(0x42CE10B8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A15           *((volatile unsigned int*)(0x42CE10BCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A16           *((volatile unsigned int*)(0x42CE10C0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A17           *((volatile unsigned int*)(0x42CE10C4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A18           *((volatile unsigned int*)(0x42CE10C8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A19           *((volatile unsigned int*)(0x42CE10CCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A20           *((volatile unsigned int*)(0x42CE10D0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A21           *((volatile unsigned int*)(0x42CE10D4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A22           *((volatile unsigned int*)(0x42CE10D8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A23           *((volatile unsigned int*)(0x42CE10DCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A24           *((volatile unsigned int*)(0x42CE10E0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A25           *((volatile unsigned int*)(0x42CE10E4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A26           *((volatile unsigned int*)(0x42CE10E8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A27           *((volatile unsigned int*)(0x42CE10ECUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A28           *((volatile unsigned int*)(0x42CE10F0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A29           *((volatile unsigned int*)(0x42CE10F4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A30           *((volatile unsigned int*)(0x42CE10F8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A31           *((volatile unsigned int*)(0x42CE10FCUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A32           *((volatile unsigned int*)(0x42CE1100UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A33           *((volatile unsigned int*)(0x42CE1104UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A34           *((volatile unsigned int*)(0x42CE1108UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A35           *((volatile unsigned int*)(0x42CE110CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A36           *((volatile unsigned int*)(0x42CE1110UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A37           *((volatile unsigned int*)(0x42CE1114UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A38           *((volatile unsigned int*)(0x42CE1118UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A39           *((volatile unsigned int*)(0x42CE111CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A40           *((volatile unsigned int*)(0x42CE1120UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A41           *((volatile unsigned int*)(0x42CE1124UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A42           *((volatile unsigned int*)(0x42CE1128UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A43           *((volatile unsigned int*)(0x42CE112CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A44           *((volatile unsigned int*)(0x42CE1130UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A45           *((volatile unsigned int*)(0x42CE1134UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A46           *((volatile unsigned int*)(0x42CE1138UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A47           *((volatile unsigned int*)(0x42CE113CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC0          *((volatile unsigned int*)(0x42CE1160UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC1          *((volatile unsigned int*)(0x42CE1164UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC2          *((volatile unsigned int*)(0x42CE1168UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC3          *((volatile unsigned int*)(0x42CE116CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC4          *((volatile unsigned int*)(0x42CE1170UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC5          *((volatile unsigned int*)(0x42CE1174UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_SA            *((volatile unsigned int*)(0x42CE1178UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_AE            *((volatile unsigned int*)(0x42CE117CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A0            *((volatile unsigned int*)(0x42CE1180UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A1            *((volatile unsigned int*)(0x42CE1184UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A2            *((volatile unsigned int*)(0x42CE1188UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A3            *((volatile unsigned int*)(0x42CE118CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A4            *((volatile unsigned int*)(0x42CE1190UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A5            *((volatile unsigned int*)(0x42CE1194UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A6            *((volatile unsigned int*)(0x42CE1198UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A7            *((volatile unsigned int*)(0x42CE119CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A8            *((volatile unsigned int*)(0x42CE11A0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A9            *((volatile unsigned int*)(0x42CE11A4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A10           *((volatile unsigned int*)(0x42CE11A8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A11           *((volatile unsigned int*)(0x42CE11ACUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A12           *((volatile unsigned int*)(0x42CE11B0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A13           *((volatile unsigned int*)(0x42CE11B4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A14           *((volatile unsigned int*)(0x42CE11B8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A15           *((volatile unsigned int*)(0x42CE11BCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A16           *((volatile unsigned int*)(0x42CE11C0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A17           *((volatile unsigned int*)(0x42CE11C4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A18           *((volatile unsigned int*)(0x42CE11C8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A19           *((volatile unsigned int*)(0x42CE11CCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A20           *((volatile unsigned int*)(0x42CE11D0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A21           *((volatile unsigned int*)(0x42CE11D4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A22           *((volatile unsigned int*)(0x42CE11D8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A23           *((volatile unsigned int*)(0x42CE11DCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A24           *((volatile unsigned int*)(0x42CE11E0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A25           *((volatile unsigned int*)(0x42CE11E4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A26           *((volatile unsigned int*)(0x42CE11E8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A27           *((volatile unsigned int*)(0x42CE11ECUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A28           *((volatile unsigned int*)(0x42CE11F0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A29           *((volatile unsigned int*)(0x42CE11F4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A30           *((volatile unsigned int*)(0x42CE11F8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A31           *((volatile unsigned int*)(0x42CE11FCUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A32          *((volatile unsigned int*)(0x42CE1200UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A33          *((volatile unsigned int*)(0x42CE1204UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A34          *((volatile unsigned int*)(0x42CE1208UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A35          *((volatile unsigned int*)(0x42CE120CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A36          *((volatile unsigned int*)(0x42CE1210UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A37          *((volatile unsigned int*)(0x42CE1214UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A38          *((volatile unsigned int*)(0x42CE1218UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A39          *((volatile unsigned int*)(0x42CE121CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A40          *((volatile unsigned int*)(0x42CE1220UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A41          *((volatile unsigned int*)(0x42CE1224UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A42          *((volatile unsigned int*)(0x42CE1228UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A43          *((volatile unsigned int*)(0x42CE122CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A44          *((volatile unsigned int*)(0x42CE1230UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A45          *((volatile unsigned int*)(0x42CE1234UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A46          *((volatile unsigned int*)(0x42CE1238UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A47          *((volatile unsigned int*)(0x42CE123CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC0         *((volatile unsigned int*)(0x42CE1260UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC1         *((volatile unsigned int*)(0x42CE1264UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC2         *((volatile unsigned int*)(0x42CE1268UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC3         *((volatile unsigned int*)(0x42CE126CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC4         *((volatile unsigned int*)(0x42CE1270UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC5         *((volatile unsigned int*)(0x42CE1274UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_SA           *((volatile unsigned int*)(0x42CE1278UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_AE           *((volatile unsigned int*)(0x42CE127CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A0           *((volatile unsigned int*)(0x42CE1280UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A1           *((volatile unsigned int*)(0x42CE1284UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A2           *((volatile unsigned int*)(0x42CE1288UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A3           *((volatile unsigned int*)(0x42CE128CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A4           *((volatile unsigned int*)(0x42CE1290UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A5           *((volatile unsigned int*)(0x42CE1294UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A6           *((volatile unsigned int*)(0x42CE1298UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A7           *((volatile unsigned int*)(0x42CE129CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A8           *((volatile unsigned int*)(0x42CE12A0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A9           *((volatile unsigned int*)(0x42CE12A4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A10          *((volatile unsigned int*)(0x42CE12A8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A11          *((volatile unsigned int*)(0x42CE12ACUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A12          *((volatile unsigned int*)(0x42CE12B0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A13          *((volatile unsigned int*)(0x42CE12B4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A14          *((volatile unsigned int*)(0x42CE12B8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A15          *((volatile unsigned int*)(0x42CE12BCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A16          *((volatile unsigned int*)(0x42CE12C0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A17          *((volatile unsigned int*)(0x42CE12C4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A18          *((volatile unsigned int*)(0x42CE12C8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A19          *((volatile unsigned int*)(0x42CE12CCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A20          *((volatile unsigned int*)(0x42CE12D0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A21          *((volatile unsigned int*)(0x42CE12D4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A22          *((volatile unsigned int*)(0x42CE12D8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A23          *((volatile unsigned int*)(0x42CE12DCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A24          *((volatile unsigned int*)(0x42CE12E0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A25          *((volatile unsigned int*)(0x42CE12E4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A26          *((volatile unsigned int*)(0x42CE12E8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A27          *((volatile unsigned int*)(0x42CE12ECUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A28          *((volatile unsigned int*)(0x42CE12F0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A29          *((volatile unsigned int*)(0x42CE12F4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A30          *((volatile unsigned int*)(0x42CE12F8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A31          *((volatile unsigned int*)(0x42CE12FCUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A32          *((volatile unsigned int*)(0x42CE1300UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A33          *((volatile unsigned int*)(0x42CE1304UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A34          *((volatile unsigned int*)(0x42CE1308UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A35          *((volatile unsigned int*)(0x42CE130CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A36          *((volatile unsigned int*)(0x42CE1310UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A37          *((volatile unsigned int*)(0x42CE1314UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A38          *((volatile unsigned int*)(0x42CE1318UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A39          *((volatile unsigned int*)(0x42CE131CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A40          *((volatile unsigned int*)(0x42CE1320UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A41          *((volatile unsigned int*)(0x42CE1324UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A42          *((volatile unsigned int*)(0x42CE1328UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A43          *((volatile unsigned int*)(0x42CE132CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A44          *((volatile unsigned int*)(0x42CE1330UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A45          *((volatile unsigned int*)(0x42CE1334UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A46          *((volatile unsigned int*)(0x42CE1338UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A47          *((volatile unsigned int*)(0x42CE133CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC0         *((volatile unsigned int*)(0x42CE1360UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC1         *((volatile unsigned int*)(0x42CE1364UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC2         *((volatile unsigned int*)(0x42CE1368UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC3         *((volatile unsigned int*)(0x42CE136CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC4         *((volatile unsigned int*)(0x42CE1370UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC5         *((volatile unsigned int*)(0x42CE1374UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_SA           *((volatile unsigned int*)(0x42CE1378UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_AE           *((volatile unsigned int*)(0x42CE137CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A0           *((volatile unsigned int*)(0x42CE1380UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A1           *((volatile unsigned int*)(0x42CE1384UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A2           *((volatile unsigned int*)(0x42CE1388UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A3           *((volatile unsigned int*)(0x42CE138CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A4           *((volatile unsigned int*)(0x42CE1390UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A5           *((volatile unsigned int*)(0x42CE1394UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A6           *((volatile unsigned int*)(0x42CE1398UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A7           *((volatile unsigned int*)(0x42CE139CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A8           *((volatile unsigned int*)(0x42CE13A0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A9           *((volatile unsigned int*)(0x42CE13A4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A10          *((volatile unsigned int*)(0x42CE13A8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A11          *((volatile unsigned int*)(0x42CE13ACUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A12          *((volatile unsigned int*)(0x42CE13B0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A13          *((volatile unsigned int*)(0x42CE13B4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A14          *((volatile unsigned int*)(0x42CE13B8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A15          *((volatile unsigned int*)(0x42CE13BCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A16          *((volatile unsigned int*)(0x42CE13C0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A17          *((volatile unsigned int*)(0x42CE13C4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A18          *((volatile unsigned int*)(0x42CE13C8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A19          *((volatile unsigned int*)(0x42CE13CCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A20          *((volatile unsigned int*)(0x42CE13D0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A21          *((volatile unsigned int*)(0x42CE13D4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A22          *((volatile unsigned int*)(0x42CE13D8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A23          *((volatile unsigned int*)(0x42CE13DCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A24          *((volatile unsigned int*)(0x42CE13E0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A25          *((volatile unsigned int*)(0x42CE13E4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A26          *((volatile unsigned int*)(0x42CE13E8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A27          *((volatile unsigned int*)(0x42CE13ECUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A28          *((volatile unsigned int*)(0x42CE13F0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A29          *((volatile unsigned int*)(0x42CE13F4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A30          *((volatile unsigned int*)(0x42CE13F8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A31          *((volatile unsigned int*)(0x42CE13FCUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A32          *((volatile unsigned int*)(0x42CE1400UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A33          *((volatile unsigned int*)(0x42CE1404UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A34          *((volatile unsigned int*)(0x42CE1408UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A35          *((volatile unsigned int*)(0x42CE140CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A36          *((volatile unsigned int*)(0x42CE1410UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A37          *((volatile unsigned int*)(0x42CE1414UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A38          *((volatile unsigned int*)(0x42CE1418UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A39          *((volatile unsigned int*)(0x42CE141CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A40          *((volatile unsigned int*)(0x42CE1420UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A41          *((volatile unsigned int*)(0x42CE1424UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A42          *((volatile unsigned int*)(0x42CE1428UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A43          *((volatile unsigned int*)(0x42CE142CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A44          *((volatile unsigned int*)(0x42CE1430UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A45          *((volatile unsigned int*)(0x42CE1434UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A46          *((volatile unsigned int*)(0x42CE1438UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A47          *((volatile unsigned int*)(0x42CE143CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC0         *((volatile unsigned int*)(0x42CE1460UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC1         *((volatile unsigned int*)(0x42CE1464UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC2         *((volatile unsigned int*)(0x42CE1468UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC3         *((volatile unsigned int*)(0x42CE146CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC4         *((volatile unsigned int*)(0x42CE1470UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC5         *((volatile unsigned int*)(0x42CE1474UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_SA           *((volatile unsigned int*)(0x42CE1478UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_AE           *((volatile unsigned int*)(0x42CE147CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A0           *((volatile unsigned int*)(0x42CE1480UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A1           *((volatile unsigned int*)(0x42CE1484UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A2           *((volatile unsigned int*)(0x42CE1488UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A3           *((volatile unsigned int*)(0x42CE148CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A4           *((volatile unsigned int*)(0x42CE1490UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A5           *((volatile unsigned int*)(0x42CE1494UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A6           *((volatile unsigned int*)(0x42CE1498UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A7           *((volatile unsigned int*)(0x42CE149CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A8           *((volatile unsigned int*)(0x42CE14A0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A9           *((volatile unsigned int*)(0x42CE14A4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A10          *((volatile unsigned int*)(0x42CE14A8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A11          *((volatile unsigned int*)(0x42CE14ACUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A12          *((volatile unsigned int*)(0x42CE14B0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A13          *((volatile unsigned int*)(0x42CE14B4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A14          *((volatile unsigned int*)(0x42CE14B8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A15          *((volatile unsigned int*)(0x42CE14BCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A16          *((volatile unsigned int*)(0x42CE14C0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A17          *((volatile unsigned int*)(0x42CE14C4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A18          *((volatile unsigned int*)(0x42CE14C8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A19          *((volatile unsigned int*)(0x42CE14CCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A20          *((volatile unsigned int*)(0x42CE14D0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A21          *((volatile unsigned int*)(0x42CE14D4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A22          *((volatile unsigned int*)(0x42CE14D8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A23          *((volatile unsigned int*)(0x42CE14DCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A24          *((volatile unsigned int*)(0x42CE14E0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A25          *((volatile unsigned int*)(0x42CE14E4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A26          *((volatile unsigned int*)(0x42CE14E8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A27          *((volatile unsigned int*)(0x42CE14ECUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A28          *((volatile unsigned int*)(0x42CE14F0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A29          *((volatile unsigned int*)(0x42CE14F4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A30          *((volatile unsigned int*)(0x42CE14F8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A31          *((volatile unsigned int*)(0x42CE14FCUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A32          *((volatile unsigned int*)(0x42CE1500UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A33          *((volatile unsigned int*)(0x42CE1504UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A34          *((volatile unsigned int*)(0x42CE1508UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A35          *((volatile unsigned int*)(0x42CE150CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A36          *((volatile unsigned int*)(0x42CE1510UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A37          *((volatile unsigned int*)(0x42CE1514UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A38          *((volatile unsigned int*)(0x42CE1518UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A39          *((volatile unsigned int*)(0x42CE151CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A40          *((volatile unsigned int*)(0x42CE1520UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A41          *((volatile unsigned int*)(0x42CE1524UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A42          *((volatile unsigned int*)(0x42CE1528UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A43          *((volatile unsigned int*)(0x42CE152CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A44          *((volatile unsigned int*)(0x42CE1530UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A45          *((volatile unsigned int*)(0x42CE1534UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A46          *((volatile unsigned int*)(0x42CE1538UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A47          *((volatile unsigned int*)(0x42CE153CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC0         *((volatile unsigned int*)(0x42CE1560UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC1         *((volatile unsigned int*)(0x42CE1564UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC2         *((volatile unsigned int*)(0x42CE1568UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC3         *((volatile unsigned int*)(0x42CE156CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC4         *((volatile unsigned int*)(0x42CE1570UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC5         *((volatile unsigned int*)(0x42CE1574UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_SA           *((volatile unsigned int*)(0x42CE1578UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_AE           *((volatile unsigned int*)(0x42CE157CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A0           *((volatile unsigned int*)(0x42CE1580UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A1           *((volatile unsigned int*)(0x42CE1584UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A2           *((volatile unsigned int*)(0x42CE1588UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A3           *((volatile unsigned int*)(0x42CE158CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A4           *((volatile unsigned int*)(0x42CE1590UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A5           *((volatile unsigned int*)(0x42CE1594UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A6           *((volatile unsigned int*)(0x42CE1598UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A7           *((volatile unsigned int*)(0x42CE159CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A8           *((volatile unsigned int*)(0x42CE15A0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A9           *((volatile unsigned int*)(0x42CE15A4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A10          *((volatile unsigned int*)(0x42CE15A8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A11          *((volatile unsigned int*)(0x42CE15ACUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A12          *((volatile unsigned int*)(0x42CE15B0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A13          *((volatile unsigned int*)(0x42CE15B4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A14          *((volatile unsigned int*)(0x42CE15B8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A15          *((volatile unsigned int*)(0x42CE15BCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A16          *((volatile unsigned int*)(0x42CE15C0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A17          *((volatile unsigned int*)(0x42CE15C4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A18          *((volatile unsigned int*)(0x42CE15C8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A19          *((volatile unsigned int*)(0x42CE15CCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A20          *((volatile unsigned int*)(0x42CE15D0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A21          *((volatile unsigned int*)(0x42CE15D4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A22          *((volatile unsigned int*)(0x42CE15D8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A23          *((volatile unsigned int*)(0x42CE15DCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A24          *((volatile unsigned int*)(0x42CE15E0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A25          *((volatile unsigned int*)(0x42CE15E4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A26          *((volatile unsigned int*)(0x42CE15E8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A27          *((volatile unsigned int*)(0x42CE15ECUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A28          *((volatile unsigned int*)(0x42CE15F0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A29          *((volatile unsigned int*)(0x42CE15F4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A30          *((volatile unsigned int*)(0x42CE15F8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A31          *((volatile unsigned int*)(0x42CE15FCUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A32          *((volatile unsigned int*)(0x42CE1600UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A33          *((volatile unsigned int*)(0x42CE1604UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A34          *((volatile unsigned int*)(0x42CE1608UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A35          *((volatile unsigned int*)(0x42CE160CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A36          *((volatile unsigned int*)(0x42CE1610UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A37          *((volatile unsigned int*)(0x42CE1614UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A38          *((volatile unsigned int*)(0x42CE1618UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A39          *((volatile unsigned int*)(0x42CE161CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A40          *((volatile unsigned int*)(0x42CE1620UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A41          *((volatile unsigned int*)(0x42CE1624UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A42          *((volatile unsigned int*)(0x42CE1628UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A43          *((volatile unsigned int*)(0x42CE162CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A44          *((volatile unsigned int*)(0x42CE1630UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A45          *((volatile unsigned int*)(0x42CE1634UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A46          *((volatile unsigned int*)(0x42CE1638UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A47          *((volatile unsigned int*)(0x42CE163CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC0         *((volatile unsigned int*)(0x42CE1660UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC1         *((volatile unsigned int*)(0x42CE1664UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC2         *((volatile unsigned int*)(0x42CE1668UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC3         *((volatile unsigned int*)(0x42CE166CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC4         *((volatile unsigned int*)(0x42CE1670UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC5         *((volatile unsigned int*)(0x42CE1674UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_SA           *((volatile unsigned int*)(0x42CE1678UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_AE           *((volatile unsigned int*)(0x42CE167CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A0           *((volatile unsigned int*)(0x42CE1680UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A1           *((volatile unsigned int*)(0x42CE1684UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A2           *((volatile unsigned int*)(0x42CE1688UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A3           *((volatile unsigned int*)(0x42CE168CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A4           *((volatile unsigned int*)(0x42CE1690UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A5           *((volatile unsigned int*)(0x42CE1694UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A6           *((volatile unsigned int*)(0x42CE1698UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A7           *((volatile unsigned int*)(0x42CE169CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A8           *((volatile unsigned int*)(0x42CE16A0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A9           *((volatile unsigned int*)(0x42CE16A4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A10          *((volatile unsigned int*)(0x42CE16A8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A11          *((volatile unsigned int*)(0x42CE16ACUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A12          *((volatile unsigned int*)(0x42CE16B0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A13          *((volatile unsigned int*)(0x42CE16B4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A14          *((volatile unsigned int*)(0x42CE16B8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A15          *((volatile unsigned int*)(0x42CE16BCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A16          *((volatile unsigned int*)(0x42CE16C0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A17          *((volatile unsigned int*)(0x42CE16C4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A18          *((volatile unsigned int*)(0x42CE16C8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A19          *((volatile unsigned int*)(0x42CE16CCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A20          *((volatile unsigned int*)(0x42CE16D0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A21          *((volatile unsigned int*)(0x42CE16D4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A22          *((volatile unsigned int*)(0x42CE16D8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A23          *((volatile unsigned int*)(0x42CE16DCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A24          *((volatile unsigned int*)(0x42CE16E0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A25          *((volatile unsigned int*)(0x42CE16E4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A26          *((volatile unsigned int*)(0x42CE16E8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A27          *((volatile unsigned int*)(0x42CE16ECUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A28          *((volatile unsigned int*)(0x42CE16F0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A29          *((volatile unsigned int*)(0x42CE16F4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A30          *((volatile unsigned int*)(0x42CE16F8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A31          *((volatile unsigned int*)(0x42CE16FCUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A32          *((volatile unsigned int*)(0x42CE1700UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A33          *((volatile unsigned int*)(0x42CE1704UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A34          *((volatile unsigned int*)(0x42CE1708UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A35          *((volatile unsigned int*)(0x42CE170CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A36          *((volatile unsigned int*)(0x42CE1710UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A37          *((volatile unsigned int*)(0x42CE1714UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A38          *((volatile unsigned int*)(0x42CE1718UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A39          *((volatile unsigned int*)(0x42CE171CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A40          *((volatile unsigned int*)(0x42CE1720UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A41          *((volatile unsigned int*)(0x42CE1724UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A42          *((volatile unsigned int*)(0x42CE1728UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A43          *((volatile unsigned int*)(0x42CE172CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A44          *((volatile unsigned int*)(0x42CE1730UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A45          *((volatile unsigned int*)(0x42CE1734UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A46          *((volatile unsigned int*)(0x42CE1738UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A47          *((volatile unsigned int*)(0x42CE173CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC0         *((volatile unsigned int*)(0x42CE1760UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC1         *((volatile unsigned int*)(0x42CE1764UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC2         *((volatile unsigned int*)(0x42CE1768UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC3         *((volatile unsigned int*)(0x42CE176CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC4         *((volatile unsigned int*)(0x42CE1770UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC5         *((volatile unsigned int*)(0x42CE1774UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_SA           *((volatile unsigned int*)(0x42CE1778UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_AE           *((volatile unsigned int*)(0x42CE177CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A0           *((volatile unsigned int*)(0x42CE1780UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A1           *((volatile unsigned int*)(0x42CE1784UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A2           *((volatile unsigned int*)(0x42CE1788UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A3           *((volatile unsigned int*)(0x42CE178CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A4           *((volatile unsigned int*)(0x42CE1790UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A5           *((volatile unsigned int*)(0x42CE1794UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A6           *((volatile unsigned int*)(0x42CE1798UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A7           *((volatile unsigned int*)(0x42CE179CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A8           *((volatile unsigned int*)(0x42CE17A0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A9           *((volatile unsigned int*)(0x42CE17A4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A10          *((volatile unsigned int*)(0x42CE17A8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A11          *((volatile unsigned int*)(0x42CE17ACUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A12          *((volatile unsigned int*)(0x42CE17B0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A13          *((volatile unsigned int*)(0x42CE17B4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A14          *((volatile unsigned int*)(0x42CE17B8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A15          *((volatile unsigned int*)(0x42CE17BCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A16          *((volatile unsigned int*)(0x42CE17C0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A17          *((volatile unsigned int*)(0x42CE17C4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A18          *((volatile unsigned int*)(0x42CE17C8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A19          *((volatile unsigned int*)(0x42CE17CCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A20          *((volatile unsigned int*)(0x42CE17D0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A21          *((volatile unsigned int*)(0x42CE17D4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A22          *((volatile unsigned int*)(0x42CE17D8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A23          *((volatile unsigned int*)(0x42CE17DCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A24          *((volatile unsigned int*)(0x42CE17E0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A25          *((volatile unsigned int*)(0x42CE17E4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A26          *((volatile unsigned int*)(0x42CE17E8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A27          *((volatile unsigned int*)(0x42CE17ECUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A28          *((volatile unsigned int*)(0x42CE17F0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A29          *((volatile unsigned int*)(0x42CE17F4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A30          *((volatile unsigned int*)(0x42CE17F8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A31          *((volatile unsigned int*)(0x42CE17FCUL))
+#define bFM3_ETHERNET_MAC1_RGSR_LM             *((volatile unsigned int*)(0x42CE1B00UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP0           *((volatile unsigned int*)(0x42CE1B04UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP1           *((volatile unsigned int*)(0x42CE1B08UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LS             *((volatile unsigned int*)(0x42CE1B0CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSE            *((volatile unsigned int*)(0x42CEE000UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TFCU           *((volatile unsigned int*)(0x42CEE004UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSI            *((volatile unsigned int*)(0x42CEE008UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSU            *((volatile unsigned int*)(0x42CEE00CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TITE           *((volatile unsigned int*)(0x42CEE010UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TARU           *((volatile unsigned int*)(0x42CEE014UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSEA           *((volatile unsigned int*)(0x42CEE020UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSDB           *((volatile unsigned int*)(0x42CEE024UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSV2E          *((volatile unsigned int*)(0x42CEE028UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSP          *((volatile unsigned int*)(0x42CEE02CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E         *((volatile unsigned int*)(0x42CEE030UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E         *((volatile unsigned int*)(0x42CEE034UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSEM         *((volatile unsigned int*)(0x42CEE038UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSMRM          *((volatile unsigned int*)(0x42CEE03CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS0          *((volatile unsigned int*)(0x42CEE040UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS1          *((volatile unsigned int*)(0x42CEE044UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSENMF         *((volatile unsigned int*)(0x42CEE048UL))
+#define bFM3_ETHERNET_MAC1_TSCR_ATSFC          *((volatile unsigned int*)(0x42CEE060UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC0         *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC1         *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC2         *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC3         *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC4         *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC5         *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC6         *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC7         *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS0           *((volatile unsigned int*)(0x42CEE100UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS1           *((volatile unsigned int*)(0x42CEE104UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS2           *((volatile unsigned int*)(0x42CEE108UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS3           *((volatile unsigned int*)(0x42CEE10CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS4           *((volatile unsigned int*)(0x42CEE110UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS5           *((volatile unsigned int*)(0x42CEE114UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS6           *((volatile unsigned int*)(0x42CEE118UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS7           *((volatile unsigned int*)(0x42CEE11CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS8           *((volatile unsigned int*)(0x42CEE120UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS9           *((volatile unsigned int*)(0x42CEE124UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS10          *((volatile unsigned int*)(0x42CEE128UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS11          *((volatile unsigned int*)(0x42CEE12CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS12          *((volatile unsigned int*)(0x42CEE130UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS13          *((volatile unsigned int*)(0x42CEE134UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS14          *((volatile unsigned int*)(0x42CEE138UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS15          *((volatile unsigned int*)(0x42CEE13CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS16          *((volatile unsigned int*)(0x42CEE140UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS17          *((volatile unsigned int*)(0x42CEE144UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS18          *((volatile unsigned int*)(0x42CEE148UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS19          *((volatile unsigned int*)(0x42CEE14CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS20          *((volatile unsigned int*)(0x42CEE150UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS21          *((volatile unsigned int*)(0x42CEE154UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS22          *((volatile unsigned int*)(0x42CEE158UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS23          *((volatile unsigned int*)(0x42CEE15CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS24          *((volatile unsigned int*)(0x42CEE160UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS25          *((volatile unsigned int*)(0x42CEE164UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS26          *((volatile unsigned int*)(0x42CEE168UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS27          *((volatile unsigned int*)(0x42CEE16CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS28          *((volatile unsigned int*)(0x42CEE170UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS29          *((volatile unsigned int*)(0x42CEE174UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS30          *((volatile unsigned int*)(0x42CEE178UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS31          *((volatile unsigned int*)(0x42CEE17CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS0          *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS1          *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS2          *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS3          *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS4          *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS5          *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS6          *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS7          *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS8          *((volatile unsigned int*)(0x42CEE0A0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS9          *((volatile unsigned int*)(0x42CEE0A4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS10         *((volatile unsigned int*)(0x42CEE0A8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS11         *((volatile unsigned int*)(0x42CEE0ACUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS12         *((volatile unsigned int*)(0x42CEE0B0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS13         *((volatile unsigned int*)(0x42CEE0B4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS14         *((volatile unsigned int*)(0x42CEE0B8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS15         *((volatile unsigned int*)(0x42CEE0BCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS16         *((volatile unsigned int*)(0x42CEE0C0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS17         *((volatile unsigned int*)(0x42CEE0C4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS18         *((volatile unsigned int*)(0x42CEE0C8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS19         *((volatile unsigned int*)(0x42CEE0CCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS20         *((volatile unsigned int*)(0x42CEE0D0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS21         *((volatile unsigned int*)(0x42CEE0D4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS22         *((volatile unsigned int*)(0x42CEE0D8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS23         *((volatile unsigned int*)(0x42CEE0DCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS24         *((volatile unsigned int*)(0x42CEE0E0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS25         *((volatile unsigned int*)(0x42CEE0E4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS26         *((volatile unsigned int*)(0x42CEE0E8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS27         *((volatile unsigned int*)(0x42CEE0ECUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS28         *((volatile unsigned int*)(0x42CEE0F0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS29         *((volatile unsigned int*)(0x42CEE0F4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS30         *((volatile unsigned int*)(0x42CEE0F8UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS0          *((volatile unsigned int*)(0x42CEE200UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS1          *((volatile unsigned int*)(0x42CEE204UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS2          *((volatile unsigned int*)(0x42CEE208UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS3          *((volatile unsigned int*)(0x42CEE20CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS4          *((volatile unsigned int*)(0x42CEE210UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS5          *((volatile unsigned int*)(0x42CEE214UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS6          *((volatile unsigned int*)(0x42CEE218UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS7          *((volatile unsigned int*)(0x42CEE21CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS8          *((volatile unsigned int*)(0x42CEE220UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS9          *((volatile unsigned int*)(0x42CEE224UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS10         *((volatile unsigned int*)(0x42CEE228UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS11         *((volatile unsigned int*)(0x42CEE22CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS12         *((volatile unsigned int*)(0x42CEE230UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS13         *((volatile unsigned int*)(0x42CEE234UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS14         *((volatile unsigned int*)(0x42CEE238UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS15         *((volatile unsigned int*)(0x42CEE23CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS16         *((volatile unsigned int*)(0x42CEE240UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS17         *((volatile unsigned int*)(0x42CEE244UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS18         *((volatile unsigned int*)(0x42CEE248UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS19         *((volatile unsigned int*)(0x42CEE24CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS20         *((volatile unsigned int*)(0x42CEE250UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS21         *((volatile unsigned int*)(0x42CEE254UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS22         *((volatile unsigned int*)(0x42CEE258UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS23         *((volatile unsigned int*)(0x42CEE25CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS24         *((volatile unsigned int*)(0x42CEE260UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS25         *((volatile unsigned int*)(0x42CEE264UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS26         *((volatile unsigned int*)(0x42CEE268UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS27         *((volatile unsigned int*)(0x42CEE26CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS28         *((volatile unsigned int*)(0x42CEE270UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS29         *((volatile unsigned int*)(0x42CEE274UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS30         *((volatile unsigned int*)(0x42CEE278UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS31         *((volatile unsigned int*)(0x42CEE27CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS0         *((volatile unsigned int*)(0x42CEE280UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS1         *((volatile unsigned int*)(0x42CEE284UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS2         *((volatile unsigned int*)(0x42CEE288UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS3         *((volatile unsigned int*)(0x42CEE28CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS4         *((volatile unsigned int*)(0x42CEE290UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS5         *((volatile unsigned int*)(0x42CEE294UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS6         *((volatile unsigned int*)(0x42CEE298UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS7         *((volatile unsigned int*)(0x42CEE29CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS8         *((volatile unsigned int*)(0x42CEE2A0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS9         *((volatile unsigned int*)(0x42CEE2A4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS10        *((volatile unsigned int*)(0x42CEE2A8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS11        *((volatile unsigned int*)(0x42CEE2ACUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS12        *((volatile unsigned int*)(0x42CEE2B0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS13        *((volatile unsigned int*)(0x42CEE2B4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS14        *((volatile unsigned int*)(0x42CEE2B8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS15        *((volatile unsigned int*)(0x42CEE2BCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS16        *((volatile unsigned int*)(0x42CEE2C0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS17        *((volatile unsigned int*)(0x42CEE2C4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS18        *((volatile unsigned int*)(0x42CEE2C8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS19        *((volatile unsigned int*)(0x42CEE2CCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS20        *((volatile unsigned int*)(0x42CEE2D0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS21        *((volatile unsigned int*)(0x42CEE2D4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS22        *((volatile unsigned int*)(0x42CEE2D8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS23        *((volatile unsigned int*)(0x42CEE2DCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS24        *((volatile unsigned int*)(0x42CEE2E0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS25        *((volatile unsigned int*)(0x42CEE2E4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS26        *((volatile unsigned int*)(0x42CEE2E8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS27        *((volatile unsigned int*)(0x42CEE2ECUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS28        *((volatile unsigned int*)(0x42CEE2F0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS29        *((volatile unsigned int*)(0x42CEE2F4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS30        *((volatile unsigned int*)(0x42CEE2F8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB        *((volatile unsigned int*)(0x42CEE2FCUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR0          *((volatile unsigned int*)(0x42CEE300UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR1          *((volatile unsigned int*)(0x42CEE304UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR2          *((volatile unsigned int*)(0x42CEE308UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR3          *((volatile unsigned int*)(0x42CEE30CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR4          *((volatile unsigned int*)(0x42CEE310UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR5          *((volatile unsigned int*)(0x42CEE314UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR6          *((volatile unsigned int*)(0x42CEE318UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR7          *((volatile unsigned int*)(0x42CEE31CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR8          *((volatile unsigned int*)(0x42CEE320UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR9          *((volatile unsigned int*)(0x42CEE324UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR10         *((volatile unsigned int*)(0x42CEE328UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR11         *((volatile unsigned int*)(0x42CEE32CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR12         *((volatile unsigned int*)(0x42CEE330UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR13         *((volatile unsigned int*)(0x42CEE334UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR14         *((volatile unsigned int*)(0x42CEE338UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR15         *((volatile unsigned int*)(0x42CEE33CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR16         *((volatile unsigned int*)(0x42CEE340UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR17         *((volatile unsigned int*)(0x42CEE344UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR18         *((volatile unsigned int*)(0x42CEE348UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR19         *((volatile unsigned int*)(0x42CEE34CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR20         *((volatile unsigned int*)(0x42CEE350UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR21         *((volatile unsigned int*)(0x42CEE354UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR22         *((volatile unsigned int*)(0x42CEE358UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR23         *((volatile unsigned int*)(0x42CEE35CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR24         *((volatile unsigned int*)(0x42CEE360UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR25         *((volatile unsigned int*)(0x42CEE364UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR26         *((volatile unsigned int*)(0x42CEE368UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR27         *((volatile unsigned int*)(0x42CEE36CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR28         *((volatile unsigned int*)(0x42CEE370UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR29         *((volatile unsigned int*)(0x42CEE374UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR30         *((volatile unsigned int*)(0x42CEE378UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR31         *((volatile unsigned int*)(0x42CEE37CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR0          *((volatile unsigned int*)(0x42CEE380UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR1          *((volatile unsigned int*)(0x42CEE384UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR2          *((volatile unsigned int*)(0x42CEE388UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR3          *((volatile unsigned int*)(0x42CEE38CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR4          *((volatile unsigned int*)(0x42CEE390UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR5          *((volatile unsigned int*)(0x42CEE394UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR6          *((volatile unsigned int*)(0x42CEE398UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR7          *((volatile unsigned int*)(0x42CEE39CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR8          *((volatile unsigned int*)(0x42CEE3A0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR9          *((volatile unsigned int*)(0x42CEE3A4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR10         *((volatile unsigned int*)(0x42CEE3A8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR11         *((volatile unsigned int*)(0x42CEE3ACUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR12         *((volatile unsigned int*)(0x42CEE3B0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR13         *((volatile unsigned int*)(0x42CEE3B4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR14         *((volatile unsigned int*)(0x42CEE3B8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR15         *((volatile unsigned int*)(0x42CEE3BCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR16         *((volatile unsigned int*)(0x42CEE3C0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR17         *((volatile unsigned int*)(0x42CEE3C4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR18         *((volatile unsigned int*)(0x42CEE3C8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR19         *((volatile unsigned int*)(0x42CEE3CCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR20         *((volatile unsigned int*)(0x42CEE3D0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR21         *((volatile unsigned int*)(0x42CEE3D4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR22         *((volatile unsigned int*)(0x42CEE3D8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR23         *((volatile unsigned int*)(0x42CEE3DCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR24         *((volatile unsigned int*)(0x42CEE3E0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR25         *((volatile unsigned int*)(0x42CEE3E4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR26         *((volatile unsigned int*)(0x42CEE3E8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR27         *((volatile unsigned int*)(0x42CEE3ECUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR28         *((volatile unsigned int*)(0x42CEE3F0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR29         *((volatile unsigned int*)(0x42CEE3F4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR30         *((volatile unsigned int*)(0x42CEE3F8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR31         *((volatile unsigned int*)(0x42CEE3FCUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR0          *((volatile unsigned int*)(0x42CEE400UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR1          *((volatile unsigned int*)(0x42CEE404UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR2          *((volatile unsigned int*)(0x42CEE408UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR3          *((volatile unsigned int*)(0x42CEE40CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR4          *((volatile unsigned int*)(0x42CEE410UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR5          *((volatile unsigned int*)(0x42CEE414UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR6          *((volatile unsigned int*)(0x42CEE418UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR7          *((volatile unsigned int*)(0x42CEE41CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR8          *((volatile unsigned int*)(0x42CEE420UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR9          *((volatile unsigned int*)(0x42CEE424UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR10         *((volatile unsigned int*)(0x42CEE428UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR11         *((volatile unsigned int*)(0x42CEE42CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR12         *((volatile unsigned int*)(0x42CEE430UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR13         *((volatile unsigned int*)(0x42CEE434UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR14         *((volatile unsigned int*)(0x42CEE438UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR15         *((volatile unsigned int*)(0x42CEE43CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR16         *((volatile unsigned int*)(0x42CEE440UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR17         *((volatile unsigned int*)(0x42CEE444UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR18         *((volatile unsigned int*)(0x42CEE448UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR19         *((volatile unsigned int*)(0x42CEE44CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR20         *((volatile unsigned int*)(0x42CEE450UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR21         *((volatile unsigned int*)(0x42CEE454UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR22         *((volatile unsigned int*)(0x42CEE458UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR23         *((volatile unsigned int*)(0x42CEE45CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR24         *((volatile unsigned int*)(0x42CEE460UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR25         *((volatile unsigned int*)(0x42CEE464UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR26         *((volatile unsigned int*)(0x42CEE468UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR27         *((volatile unsigned int*)(0x42CEE46CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR28         *((volatile unsigned int*)(0x42CEE470UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR29         *((volatile unsigned int*)(0x42CEE474UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR30         *((volatile unsigned int*)(0x42CEE478UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42CEE480UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42CEE484UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42CEE488UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42CEE48CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42CEE490UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42CEE494UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42CEE498UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42CEE49CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42CEE4A0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42CEE4A4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42CEE4A8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42CEE4ACUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42CEE4B0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42CEE4B4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42CEE4B8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42CEE4BCUL))
+#define bFM3_ETHERNET_MAC1_TSR_TSSOVF          *((volatile unsigned int*)(0x42CEE500UL))
+#define bFM3_ETHERNET_MAC1_TSR_TSTART          *((volatile unsigned int*)(0x42CEE504UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSTS           *((volatile unsigned int*)(0x42CEE508UL))
+#define bFM3_ETHERNET_MAC1_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSSTM          *((volatile unsigned int*)(0x42CEE560UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS0          *((volatile unsigned int*)(0x42CEE564UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS1          *((volatile unsigned int*)(0x42CEE568UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS2          *((volatile unsigned int*)(0x42CEE56CUL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42CEE580UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42CEE584UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42CEE588UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42CEE58CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN0           *((volatile unsigned int*)(0x42CEE600UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN1           *((volatile unsigned int*)(0x42CEE604UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN2           *((volatile unsigned int*)(0x42CEE608UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN3           *((volatile unsigned int*)(0x42CEE60CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN4           *((volatile unsigned int*)(0x42CEE610UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN5           *((volatile unsigned int*)(0x42CEE614UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN6           *((volatile unsigned int*)(0x42CEE618UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN7           *((volatile unsigned int*)(0x42CEE61CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN8           *((volatile unsigned int*)(0x42CEE620UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN9           *((volatile unsigned int*)(0x42CEE624UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN10          *((volatile unsigned int*)(0x42CEE628UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN11          *((volatile unsigned int*)(0x42CEE62CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN12          *((volatile unsigned int*)(0x42CEE630UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN13          *((volatile unsigned int*)(0x42CEE634UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN14          *((volatile unsigned int*)(0x42CEE638UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN15          *((volatile unsigned int*)(0x42CEE63CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN16          *((volatile unsigned int*)(0x42CEE640UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN17          *((volatile unsigned int*)(0x42CEE644UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN18          *((volatile unsigned int*)(0x42CEE648UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN19          *((volatile unsigned int*)(0x42CEE64CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN20          *((volatile unsigned int*)(0x42CEE650UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN21          *((volatile unsigned int*)(0x42CEE654UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN22          *((volatile unsigned int*)(0x42CEE658UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN23          *((volatile unsigned int*)(0x42CEE65CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN24          *((volatile unsigned int*)(0x42CEE660UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN25          *((volatile unsigned int*)(0x42CEE664UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN26          *((volatile unsigned int*)(0x42CEE668UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN27          *((volatile unsigned int*)(0x42CEE66CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN28          *((volatile unsigned int*)(0x42CEE670UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN29          *((volatile unsigned int*)(0x42CEE674UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN30          *((volatile unsigned int*)(0x42CEE678UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS0           *((volatile unsigned int*)(0x42CEE680UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS1           *((volatile unsigned int*)(0x42CEE684UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS2           *((volatile unsigned int*)(0x42CEE688UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS3           *((volatile unsigned int*)(0x42CEE68CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS4           *((volatile unsigned int*)(0x42CEE690UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS5           *((volatile unsigned int*)(0x42CEE694UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS6           *((volatile unsigned int*)(0x42CEE698UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS7           *((volatile unsigned int*)(0x42CEE69CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS8           *((volatile unsigned int*)(0x42CEE6A0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS9           *((volatile unsigned int*)(0x42CEE6A4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS10          *((volatile unsigned int*)(0x42CEE6A8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS11          *((volatile unsigned int*)(0x42CEE6ACUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS12          *((volatile unsigned int*)(0x42CEE6B0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS13          *((volatile unsigned int*)(0x42CEE6B4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS14          *((volatile unsigned int*)(0x42CEE6B8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS15          *((volatile unsigned int*)(0x42CEE6BCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS16          *((volatile unsigned int*)(0x42CEE6C0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS17          *((volatile unsigned int*)(0x42CEE6C4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS18          *((volatile unsigned int*)(0x42CEE6C8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS19          *((volatile unsigned int*)(0x42CEE6CCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS20          *((volatile unsigned int*)(0x42CEE6D0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS21          *((volatile unsigned int*)(0x42CEE6D4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS22          *((volatile unsigned int*)(0x42CEE6D8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS23          *((volatile unsigned int*)(0x42CEE6DCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS24          *((volatile unsigned int*)(0x42CEE6E0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS25          *((volatile unsigned int*)(0x42CEE6E4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS26          *((volatile unsigned int*)(0x42CEE6E8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS27          *((volatile unsigned int*)(0x42CEE6ECUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS28          *((volatile unsigned int*)(0x42CEE6F0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS29          *((volatile unsigned int*)(0x42CEE6F4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS30          *((volatile unsigned int*)(0x42CEE6F8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS31          *((volatile unsigned int*)(0x42CEE6FCUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A32          *((volatile unsigned int*)(0x42CF0000UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A33          *((volatile unsigned int*)(0x42CF0004UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A34          *((volatile unsigned int*)(0x42CF0008UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A35          *((volatile unsigned int*)(0x42CF000CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A36          *((volatile unsigned int*)(0x42CF0010UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A37          *((volatile unsigned int*)(0x42CF0014UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A38          *((volatile unsigned int*)(0x42CF0018UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A39          *((volatile unsigned int*)(0x42CF001CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A40          *((volatile unsigned int*)(0x42CF0020UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A41          *((volatile unsigned int*)(0x42CF0024UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A42          *((volatile unsigned int*)(0x42CF0028UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A43          *((volatile unsigned int*)(0x42CF002CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A44          *((volatile unsigned int*)(0x42CF0030UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A45          *((volatile unsigned int*)(0x42CF0034UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A46          *((volatile unsigned int*)(0x42CF0038UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A47          *((volatile unsigned int*)(0x42CF003CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC0         *((volatile unsigned int*)(0x42CF0060UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC1         *((volatile unsigned int*)(0x42CF0064UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC2         *((volatile unsigned int*)(0x42CF0068UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC3         *((volatile unsigned int*)(0x42CF006CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC4         *((volatile unsigned int*)(0x42CF0070UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC5         *((volatile unsigned int*)(0x42CF0074UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_SA           *((volatile unsigned int*)(0x42CF0078UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_AE           *((volatile unsigned int*)(0x42CF007CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A0           *((volatile unsigned int*)(0x42CF0080UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A1           *((volatile unsigned int*)(0x42CF0084UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A2           *((volatile unsigned int*)(0x42CF0088UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A3           *((volatile unsigned int*)(0x42CF008CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A4           *((volatile unsigned int*)(0x42CF0090UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A5           *((volatile unsigned int*)(0x42CF0094UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A6           *((volatile unsigned int*)(0x42CF0098UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A7           *((volatile unsigned int*)(0x42CF009CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A8           *((volatile unsigned int*)(0x42CF00A0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A9           *((volatile unsigned int*)(0x42CF00A4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A10          *((volatile unsigned int*)(0x42CF00A8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A11          *((volatile unsigned int*)(0x42CF00ACUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A12          *((volatile unsigned int*)(0x42CF00B0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A13          *((volatile unsigned int*)(0x42CF00B4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A14          *((volatile unsigned int*)(0x42CF00B8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A15          *((volatile unsigned int*)(0x42CF00BCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A16          *((volatile unsigned int*)(0x42CF00C0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A17          *((volatile unsigned int*)(0x42CF00C4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A18          *((volatile unsigned int*)(0x42CF00C8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A19          *((volatile unsigned int*)(0x42CF00CCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A20          *((volatile unsigned int*)(0x42CF00D0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A21          *((volatile unsigned int*)(0x42CF00D4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A22          *((volatile unsigned int*)(0x42CF00D8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A23          *((volatile unsigned int*)(0x42CF00DCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A24          *((volatile unsigned int*)(0x42CF00E0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A25          *((volatile unsigned int*)(0x42CF00E4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A26          *((volatile unsigned int*)(0x42CF00E8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A27          *((volatile unsigned int*)(0x42CF00ECUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A28          *((volatile unsigned int*)(0x42CF00F0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A29          *((volatile unsigned int*)(0x42CF00F4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A30          *((volatile unsigned int*)(0x42CF00F8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A31          *((volatile unsigned int*)(0x42CF00FCUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A32          *((volatile unsigned int*)(0x42CF0100UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A33          *((volatile unsigned int*)(0x42CF0104UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A34          *((volatile unsigned int*)(0x42CF0108UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A35          *((volatile unsigned int*)(0x42CF010CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A36          *((volatile unsigned int*)(0x42CF0110UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A37          *((volatile unsigned int*)(0x42CF0114UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A38          *((volatile unsigned int*)(0x42CF0118UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A39          *((volatile unsigned int*)(0x42CF011CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A40          *((volatile unsigned int*)(0x42CF0120UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A41          *((volatile unsigned int*)(0x42CF0124UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A42          *((volatile unsigned int*)(0x42CF0128UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A43          *((volatile unsigned int*)(0x42CF012CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A44          *((volatile unsigned int*)(0x42CF0130UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A45          *((volatile unsigned int*)(0x42CF0134UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A46          *((volatile unsigned int*)(0x42CF0138UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A47          *((volatile unsigned int*)(0x42CF013CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC0         *((volatile unsigned int*)(0x42CF0160UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC1         *((volatile unsigned int*)(0x42CF0164UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC2         *((volatile unsigned int*)(0x42CF0168UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC3         *((volatile unsigned int*)(0x42CF016CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC4         *((volatile unsigned int*)(0x42CF0170UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC5         *((volatile unsigned int*)(0x42CF0174UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_SA           *((volatile unsigned int*)(0x42CF0178UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_AE           *((volatile unsigned int*)(0x42CF017CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A0           *((volatile unsigned int*)(0x42CF0180UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A1           *((volatile unsigned int*)(0x42CF0184UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A2           *((volatile unsigned int*)(0x42CF0188UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A3           *((volatile unsigned int*)(0x42CF018CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A4           *((volatile unsigned int*)(0x42CF0190UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A5           *((volatile unsigned int*)(0x42CF0194UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A6           *((volatile unsigned int*)(0x42CF0198UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A7           *((volatile unsigned int*)(0x42CF019CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A8           *((volatile unsigned int*)(0x42CF01A0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A9           *((volatile unsigned int*)(0x42CF01A4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A10          *((volatile unsigned int*)(0x42CF01A8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A11          *((volatile unsigned int*)(0x42CF01ACUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A12          *((volatile unsigned int*)(0x42CF01B0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A13          *((volatile unsigned int*)(0x42CF01B4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A14          *((volatile unsigned int*)(0x42CF01B8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A15          *((volatile unsigned int*)(0x42CF01BCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A16          *((volatile unsigned int*)(0x42CF01C0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A17          *((volatile unsigned int*)(0x42CF01C4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A18          *((volatile unsigned int*)(0x42CF01C8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A19          *((volatile unsigned int*)(0x42CF01CCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A20          *((volatile unsigned int*)(0x42CF01D0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A21          *((volatile unsigned int*)(0x42CF01D4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A22          *((volatile unsigned int*)(0x42CF01D8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A23          *((volatile unsigned int*)(0x42CF01DCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A24          *((volatile unsigned int*)(0x42CF01E0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A25          *((volatile unsigned int*)(0x42CF01E4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A26          *((volatile unsigned int*)(0x42CF01E8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A27          *((volatile unsigned int*)(0x42CF01ECUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A28          *((volatile unsigned int*)(0x42CF01F0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A29          *((volatile unsigned int*)(0x42CF01F4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A30          *((volatile unsigned int*)(0x42CF01F8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A31          *((volatile unsigned int*)(0x42CF01FCUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A32          *((volatile unsigned int*)(0x42CF0200UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A33          *((volatile unsigned int*)(0x42CF0204UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A34          *((volatile unsigned int*)(0x42CF0208UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A35          *((volatile unsigned int*)(0x42CF020CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A36          *((volatile unsigned int*)(0x42CF0210UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A37          *((volatile unsigned int*)(0x42CF0214UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A38          *((volatile unsigned int*)(0x42CF0218UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A39          *((volatile unsigned int*)(0x42CF021CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A40          *((volatile unsigned int*)(0x42CF0220UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A41          *((volatile unsigned int*)(0x42CF0224UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A42          *((volatile unsigned int*)(0x42CF0228UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A43          *((volatile unsigned int*)(0x42CF022CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A44          *((volatile unsigned int*)(0x42CF0230UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A45          *((volatile unsigned int*)(0x42CF0234UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A46          *((volatile unsigned int*)(0x42CF0238UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A47          *((volatile unsigned int*)(0x42CF023CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC0         *((volatile unsigned int*)(0x42CF0260UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC1         *((volatile unsigned int*)(0x42CF0264UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC2         *((volatile unsigned int*)(0x42CF0268UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC3         *((volatile unsigned int*)(0x42CF026CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC4         *((volatile unsigned int*)(0x42CF0270UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC5         *((volatile unsigned int*)(0x42CF0274UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_SA           *((volatile unsigned int*)(0x42CF0278UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_AE           *((volatile unsigned int*)(0x42CF027CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A0           *((volatile unsigned int*)(0x42CF0280UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A1           *((volatile unsigned int*)(0x42CF0284UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A2           *((volatile unsigned int*)(0x42CF0288UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A3           *((volatile unsigned int*)(0x42CF028CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A4           *((volatile unsigned int*)(0x42CF0290UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A5           *((volatile unsigned int*)(0x42CF0294UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A6           *((volatile unsigned int*)(0x42CF0298UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A7           *((volatile unsigned int*)(0x42CF029CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A8           *((volatile unsigned int*)(0x42CF02A0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A9           *((volatile unsigned int*)(0x42CF02A4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A10          *((volatile unsigned int*)(0x42CF02A8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A11          *((volatile unsigned int*)(0x42CF02ACUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A12          *((volatile unsigned int*)(0x42CF02B0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A13          *((volatile unsigned int*)(0x42CF02B4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A14          *((volatile unsigned int*)(0x42CF02B8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A15          *((volatile unsigned int*)(0x42CF02BCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A16          *((volatile unsigned int*)(0x42CF02C0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A17          *((volatile unsigned int*)(0x42CF02C4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A18          *((volatile unsigned int*)(0x42CF02C8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A19          *((volatile unsigned int*)(0x42CF02CCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A20          *((volatile unsigned int*)(0x42CF02D0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A21          *((volatile unsigned int*)(0x42CF02D4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A22          *((volatile unsigned int*)(0x42CF02D8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A23          *((volatile unsigned int*)(0x42CF02DCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A24          *((volatile unsigned int*)(0x42CF02E0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A25          *((volatile unsigned int*)(0x42CF02E4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A26          *((volatile unsigned int*)(0x42CF02E8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A27          *((volatile unsigned int*)(0x42CF02ECUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A28          *((volatile unsigned int*)(0x42CF02F0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A29          *((volatile unsigned int*)(0x42CF02F4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A30          *((volatile unsigned int*)(0x42CF02F8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A31          *((volatile unsigned int*)(0x42CF02FCUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A32          *((volatile unsigned int*)(0x42CF0300UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A33          *((volatile unsigned int*)(0x42CF0304UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A34          *((volatile unsigned int*)(0x42CF0308UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A35          *((volatile unsigned int*)(0x42CF030CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A36          *((volatile unsigned int*)(0x42CF0310UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A37          *((volatile unsigned int*)(0x42CF0314UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A38          *((volatile unsigned int*)(0x42CF0318UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A39          *((volatile unsigned int*)(0x42CF031CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A40          *((volatile unsigned int*)(0x42CF0320UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A41          *((volatile unsigned int*)(0x42CF0324UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A42          *((volatile unsigned int*)(0x42CF0328UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A43          *((volatile unsigned int*)(0x42CF032CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A44          *((volatile unsigned int*)(0x42CF0330UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A45          *((volatile unsigned int*)(0x42CF0334UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A46          *((volatile unsigned int*)(0x42CF0338UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A47          *((volatile unsigned int*)(0x42CF033CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC0         *((volatile unsigned int*)(0x42CF0360UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC1         *((volatile unsigned int*)(0x42CF0364UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC2         *((volatile unsigned int*)(0x42CF0368UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC3         *((volatile unsigned int*)(0x42CF036CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC4         *((volatile unsigned int*)(0x42CF0370UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC5         *((volatile unsigned int*)(0x42CF0374UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_SA           *((volatile unsigned int*)(0x42CF0378UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_AE           *((volatile unsigned int*)(0x42CF037CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A0           *((volatile unsigned int*)(0x42CF0380UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A1           *((volatile unsigned int*)(0x42CF0384UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A2           *((volatile unsigned int*)(0x42CF0388UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A3           *((volatile unsigned int*)(0x42CF038CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A4           *((volatile unsigned int*)(0x42CF0390UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A5           *((volatile unsigned int*)(0x42CF0394UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A6           *((volatile unsigned int*)(0x42CF0398UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A7           *((volatile unsigned int*)(0x42CF039CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A8           *((volatile unsigned int*)(0x42CF03A0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A9           *((volatile unsigned int*)(0x42CF03A4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A10          *((volatile unsigned int*)(0x42CF03A8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A11          *((volatile unsigned int*)(0x42CF03ACUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A12          *((volatile unsigned int*)(0x42CF03B0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A13          *((volatile unsigned int*)(0x42CF03B4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A14          *((volatile unsigned int*)(0x42CF03B8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A15          *((volatile unsigned int*)(0x42CF03BCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A16          *((volatile unsigned int*)(0x42CF03C0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A17          *((volatile unsigned int*)(0x42CF03C4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A18          *((volatile unsigned int*)(0x42CF03C8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A19          *((volatile unsigned int*)(0x42CF03CCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A20          *((volatile unsigned int*)(0x42CF03D0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A21          *((volatile unsigned int*)(0x42CF03D4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A22          *((volatile unsigned int*)(0x42CF03D8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A23          *((volatile unsigned int*)(0x42CF03DCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A24          *((volatile unsigned int*)(0x42CF03E0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A25          *((volatile unsigned int*)(0x42CF03E4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A26          *((volatile unsigned int*)(0x42CF03E8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A27          *((volatile unsigned int*)(0x42CF03ECUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A28          *((volatile unsigned int*)(0x42CF03F0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A29          *((volatile unsigned int*)(0x42CF03F4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A30          *((volatile unsigned int*)(0x42CF03F8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A31          *((volatile unsigned int*)(0x42CF03FCUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A32          *((volatile unsigned int*)(0x42CF0400UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A33          *((volatile unsigned int*)(0x42CF0404UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A34          *((volatile unsigned int*)(0x42CF0408UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A35          *((volatile unsigned int*)(0x42CF040CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A36          *((volatile unsigned int*)(0x42CF0410UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A37          *((volatile unsigned int*)(0x42CF0414UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A38          *((volatile unsigned int*)(0x42CF0418UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A39          *((volatile unsigned int*)(0x42CF041CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A40          *((volatile unsigned int*)(0x42CF0420UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A41          *((volatile unsigned int*)(0x42CF0424UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A42          *((volatile unsigned int*)(0x42CF0428UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A43          *((volatile unsigned int*)(0x42CF042CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A44          *((volatile unsigned int*)(0x42CF0430UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A45          *((volatile unsigned int*)(0x42CF0434UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A46          *((volatile unsigned int*)(0x42CF0438UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A47          *((volatile unsigned int*)(0x42CF043CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC0         *((volatile unsigned int*)(0x42CF0460UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC1         *((volatile unsigned int*)(0x42CF0464UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC2         *((volatile unsigned int*)(0x42CF0468UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC3         *((volatile unsigned int*)(0x42CF046CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC4         *((volatile unsigned int*)(0x42CF0470UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC5         *((volatile unsigned int*)(0x42CF0474UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_SA           *((volatile unsigned int*)(0x42CF0478UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_AE           *((volatile unsigned int*)(0x42CF047CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A0           *((volatile unsigned int*)(0x42CF0480UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A1           *((volatile unsigned int*)(0x42CF0484UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A2           *((volatile unsigned int*)(0x42CF0488UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A3           *((volatile unsigned int*)(0x42CF048CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A4           *((volatile unsigned int*)(0x42CF0490UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A5           *((volatile unsigned int*)(0x42CF0494UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A6           *((volatile unsigned int*)(0x42CF0498UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A7           *((volatile unsigned int*)(0x42CF049CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A8           *((volatile unsigned int*)(0x42CF04A0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A9           *((volatile unsigned int*)(0x42CF04A4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A10          *((volatile unsigned int*)(0x42CF04A8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A11          *((volatile unsigned int*)(0x42CF04ACUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A12          *((volatile unsigned int*)(0x42CF04B0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A13          *((volatile unsigned int*)(0x42CF04B4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A14          *((volatile unsigned int*)(0x42CF04B8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A15          *((volatile unsigned int*)(0x42CF04BCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A16          *((volatile unsigned int*)(0x42CF04C0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A17          *((volatile unsigned int*)(0x42CF04C4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A18          *((volatile unsigned int*)(0x42CF04C8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A19          *((volatile unsigned int*)(0x42CF04CCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A20          *((volatile unsigned int*)(0x42CF04D0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A21          *((volatile unsigned int*)(0x42CF04D4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A22          *((volatile unsigned int*)(0x42CF04D8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A23          *((volatile unsigned int*)(0x42CF04DCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A24          *((volatile unsigned int*)(0x42CF04E0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A25          *((volatile unsigned int*)(0x42CF04E4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A26          *((volatile unsigned int*)(0x42CF04E8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A27          *((volatile unsigned int*)(0x42CF04ECUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A28          *((volatile unsigned int*)(0x42CF04F0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A29          *((volatile unsigned int*)(0x42CF04F4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A30          *((volatile unsigned int*)(0x42CF04F8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A31          *((volatile unsigned int*)(0x42CF04FCUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A32          *((volatile unsigned int*)(0x42CF0500UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A33          *((volatile unsigned int*)(0x42CF0504UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A34          *((volatile unsigned int*)(0x42CF0508UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A35          *((volatile unsigned int*)(0x42CF050CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A36          *((volatile unsigned int*)(0x42CF0510UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A37          *((volatile unsigned int*)(0x42CF0514UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A38          *((volatile unsigned int*)(0x42CF0518UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A39          *((volatile unsigned int*)(0x42CF051CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A40          *((volatile unsigned int*)(0x42CF0520UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A41          *((volatile unsigned int*)(0x42CF0524UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A42          *((volatile unsigned int*)(0x42CF0528UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A43          *((volatile unsigned int*)(0x42CF052CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A44          *((volatile unsigned int*)(0x42CF0530UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A45          *((volatile unsigned int*)(0x42CF0534UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A46          *((volatile unsigned int*)(0x42CF0538UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A47          *((volatile unsigned int*)(0x42CF053CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC0         *((volatile unsigned int*)(0x42CF0560UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC1         *((volatile unsigned int*)(0x42CF0564UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC2         *((volatile unsigned int*)(0x42CF0568UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC3         *((volatile unsigned int*)(0x42CF056CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC4         *((volatile unsigned int*)(0x42CF0570UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC5         *((volatile unsigned int*)(0x42CF0574UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_SA           *((volatile unsigned int*)(0x42CF0578UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_AE           *((volatile unsigned int*)(0x42CF057CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A0           *((volatile unsigned int*)(0x42CF0580UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A1           *((volatile unsigned int*)(0x42CF0584UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A2           *((volatile unsigned int*)(0x42CF0588UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A3           *((volatile unsigned int*)(0x42CF058CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A4           *((volatile unsigned int*)(0x42CF0590UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A5           *((volatile unsigned int*)(0x42CF0594UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A6           *((volatile unsigned int*)(0x42CF0598UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A7           *((volatile unsigned int*)(0x42CF059CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A8           *((volatile unsigned int*)(0x42CF05A0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A9           *((volatile unsigned int*)(0x42CF05A4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A10          *((volatile unsigned int*)(0x42CF05A8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A11          *((volatile unsigned int*)(0x42CF05ACUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A12          *((volatile unsigned int*)(0x42CF05B0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A13          *((volatile unsigned int*)(0x42CF05B4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A14          *((volatile unsigned int*)(0x42CF05B8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A15          *((volatile unsigned int*)(0x42CF05BCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A16          *((volatile unsigned int*)(0x42CF05C0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A17          *((volatile unsigned int*)(0x42CF05C4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A18          *((volatile unsigned int*)(0x42CF05C8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A19          *((volatile unsigned int*)(0x42CF05CCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A20          *((volatile unsigned int*)(0x42CF05D0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A21          *((volatile unsigned int*)(0x42CF05D4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A22          *((volatile unsigned int*)(0x42CF05D8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A23          *((volatile unsigned int*)(0x42CF05DCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A24          *((volatile unsigned int*)(0x42CF05E0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A25          *((volatile unsigned int*)(0x42CF05E4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A26          *((volatile unsigned int*)(0x42CF05E8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A27          *((volatile unsigned int*)(0x42CF05ECUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A28          *((volatile unsigned int*)(0x42CF05F0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A29          *((volatile unsigned int*)(0x42CF05F4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A30          *((volatile unsigned int*)(0x42CF05F8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A31          *((volatile unsigned int*)(0x42CF05FCUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A32          *((volatile unsigned int*)(0x42CF0600UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A33          *((volatile unsigned int*)(0x42CF0604UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A34          *((volatile unsigned int*)(0x42CF0608UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A35          *((volatile unsigned int*)(0x42CF060CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A36          *((volatile unsigned int*)(0x42CF0610UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A37          *((volatile unsigned int*)(0x42CF0614UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A38          *((volatile unsigned int*)(0x42CF0618UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A39          *((volatile unsigned int*)(0x42CF061CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A40          *((volatile unsigned int*)(0x42CF0620UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A41          *((volatile unsigned int*)(0x42CF0624UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A42          *((volatile unsigned int*)(0x42CF0628UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A43          *((volatile unsigned int*)(0x42CF062CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A44          *((volatile unsigned int*)(0x42CF0630UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A45          *((volatile unsigned int*)(0x42CF0634UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A46          *((volatile unsigned int*)(0x42CF0638UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A47          *((volatile unsigned int*)(0x42CF063CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC0         *((volatile unsigned int*)(0x42CF0660UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC1         *((volatile unsigned int*)(0x42CF0664UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC2         *((volatile unsigned int*)(0x42CF0668UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC3         *((volatile unsigned int*)(0x42CF066CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC4         *((volatile unsigned int*)(0x42CF0670UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC5         *((volatile unsigned int*)(0x42CF0674UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_SA           *((volatile unsigned int*)(0x42CF0678UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_AE           *((volatile unsigned int*)(0x42CF067CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A0           *((volatile unsigned int*)(0x42CF0680UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A1           *((volatile unsigned int*)(0x42CF0684UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A2           *((volatile unsigned int*)(0x42CF0688UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A3           *((volatile unsigned int*)(0x42CF068CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A4           *((volatile unsigned int*)(0x42CF0690UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A5           *((volatile unsigned int*)(0x42CF0694UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A6           *((volatile unsigned int*)(0x42CF0698UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A7           *((volatile unsigned int*)(0x42CF069CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A8           *((volatile unsigned int*)(0x42CF06A0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A9           *((volatile unsigned int*)(0x42CF06A4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A10          *((volatile unsigned int*)(0x42CF06A8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A11          *((volatile unsigned int*)(0x42CF06ACUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A12          *((volatile unsigned int*)(0x42CF06B0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A13          *((volatile unsigned int*)(0x42CF06B4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A14          *((volatile unsigned int*)(0x42CF06B8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A15          *((volatile unsigned int*)(0x42CF06BCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A16          *((volatile unsigned int*)(0x42CF06C0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A17          *((volatile unsigned int*)(0x42CF06C4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A18          *((volatile unsigned int*)(0x42CF06C8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A19          *((volatile unsigned int*)(0x42CF06CCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A20          *((volatile unsigned int*)(0x42CF06D0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A21          *((volatile unsigned int*)(0x42CF06D4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A22          *((volatile unsigned int*)(0x42CF06D8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A23          *((volatile unsigned int*)(0x42CF06DCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A24          *((volatile unsigned int*)(0x42CF06E0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A25          *((volatile unsigned int*)(0x42CF06E4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A26          *((volatile unsigned int*)(0x42CF06E8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A27          *((volatile unsigned int*)(0x42CF06ECUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A28          *((volatile unsigned int*)(0x42CF06F0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A29          *((volatile unsigned int*)(0x42CF06F4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A30          *((volatile unsigned int*)(0x42CF06F8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A31          *((volatile unsigned int*)(0x42CF06FCUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A32          *((volatile unsigned int*)(0x42CF0700UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A33          *((volatile unsigned int*)(0x42CF0704UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A34          *((volatile unsigned int*)(0x42CF0708UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A35          *((volatile unsigned int*)(0x42CF070CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A36          *((volatile unsigned int*)(0x42CF0710UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A37          *((volatile unsigned int*)(0x42CF0714UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A38          *((volatile unsigned int*)(0x42CF0718UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A39          *((volatile unsigned int*)(0x42CF071CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A40          *((volatile unsigned int*)(0x42CF0720UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A41          *((volatile unsigned int*)(0x42CF0724UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A42          *((volatile unsigned int*)(0x42CF0728UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A43          *((volatile unsigned int*)(0x42CF072CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A44          *((volatile unsigned int*)(0x42CF0730UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A45          *((volatile unsigned int*)(0x42CF0734UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A46          *((volatile unsigned int*)(0x42CF0738UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A47          *((volatile unsigned int*)(0x42CF073CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC0         *((volatile unsigned int*)(0x42CF0760UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC1         *((volatile unsigned int*)(0x42CF0764UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC2         *((volatile unsigned int*)(0x42CF0768UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC3         *((volatile unsigned int*)(0x42CF076CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC4         *((volatile unsigned int*)(0x42CF0770UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC5         *((volatile unsigned int*)(0x42CF0774UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_SA           *((volatile unsigned int*)(0x42CF0778UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_AE           *((volatile unsigned int*)(0x42CF077CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A0           *((volatile unsigned int*)(0x42CF0780UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A1           *((volatile unsigned int*)(0x42CF0784UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A2           *((volatile unsigned int*)(0x42CF0788UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A3           *((volatile unsigned int*)(0x42CF078CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A4           *((volatile unsigned int*)(0x42CF0790UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A5           *((volatile unsigned int*)(0x42CF0794UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A6           *((volatile unsigned int*)(0x42CF0798UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A7           *((volatile unsigned int*)(0x42CF079CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A8           *((volatile unsigned int*)(0x42CF07A0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A9           *((volatile unsigned int*)(0x42CF07A4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A10          *((volatile unsigned int*)(0x42CF07A8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A11          *((volatile unsigned int*)(0x42CF07ACUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A12          *((volatile unsigned int*)(0x42CF07B0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A13          *((volatile unsigned int*)(0x42CF07B4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A14          *((volatile unsigned int*)(0x42CF07B8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A15          *((volatile unsigned int*)(0x42CF07BCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A16          *((volatile unsigned int*)(0x42CF07C0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A17          *((volatile unsigned int*)(0x42CF07C4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A18          *((volatile unsigned int*)(0x42CF07C8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A19          *((volatile unsigned int*)(0x42CF07CCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A20          *((volatile unsigned int*)(0x42CF07D0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A21          *((volatile unsigned int*)(0x42CF07D4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A22          *((volatile unsigned int*)(0x42CF07D8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A23          *((volatile unsigned int*)(0x42CF07DCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A24          *((volatile unsigned int*)(0x42CF07E0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A25          *((volatile unsigned int*)(0x42CF07E4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A26          *((volatile unsigned int*)(0x42CF07E8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A27          *((volatile unsigned int*)(0x42CF07ECUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A28          *((volatile unsigned int*)(0x42CF07F0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A29          *((volatile unsigned int*)(0x42CF07F4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A30          *((volatile unsigned int*)(0x42CF07F8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A31          *((volatile unsigned int*)(0x42CF07FCUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A32          *((volatile unsigned int*)(0x42CF0800UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A33          *((volatile unsigned int*)(0x42CF0804UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A34          *((volatile unsigned int*)(0x42CF0808UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A35          *((volatile unsigned int*)(0x42CF080CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A36          *((volatile unsigned int*)(0x42CF0810UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A37          *((volatile unsigned int*)(0x42CF0814UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A38          *((volatile unsigned int*)(0x42CF0818UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A39          *((volatile unsigned int*)(0x42CF081CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A40          *((volatile unsigned int*)(0x42CF0820UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A41          *((volatile unsigned int*)(0x42CF0824UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A42          *((volatile unsigned int*)(0x42CF0828UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A43          *((volatile unsigned int*)(0x42CF082CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A44          *((volatile unsigned int*)(0x42CF0830UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A45          *((volatile unsigned int*)(0x42CF0834UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A46          *((volatile unsigned int*)(0x42CF0838UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A47          *((volatile unsigned int*)(0x42CF083CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC0         *((volatile unsigned int*)(0x42CF0860UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC1         *((volatile unsigned int*)(0x42CF0864UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC2         *((volatile unsigned int*)(0x42CF0868UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC3         *((volatile unsigned int*)(0x42CF086CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC4         *((volatile unsigned int*)(0x42CF0870UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC5         *((volatile unsigned int*)(0x42CF0874UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_SA           *((volatile unsigned int*)(0x42CF0878UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_AE           *((volatile unsigned int*)(0x42CF087CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A0           *((volatile unsigned int*)(0x42CF0880UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A1           *((volatile unsigned int*)(0x42CF0884UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A2           *((volatile unsigned int*)(0x42CF0888UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A3           *((volatile unsigned int*)(0x42CF088CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A4           *((volatile unsigned int*)(0x42CF0890UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A5           *((volatile unsigned int*)(0x42CF0894UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A6           *((volatile unsigned int*)(0x42CF0898UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A7           *((volatile unsigned int*)(0x42CF089CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A8           *((volatile unsigned int*)(0x42CF08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A9           *((volatile unsigned int*)(0x42CF08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A10          *((volatile unsigned int*)(0x42CF08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A11          *((volatile unsigned int*)(0x42CF08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A12          *((volatile unsigned int*)(0x42CF08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A13          *((volatile unsigned int*)(0x42CF08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A14          *((volatile unsigned int*)(0x42CF08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A15          *((volatile unsigned int*)(0x42CF08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A16          *((volatile unsigned int*)(0x42CF08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A17          *((volatile unsigned int*)(0x42CF08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A18          *((volatile unsigned int*)(0x42CF08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A19          *((volatile unsigned int*)(0x42CF08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A20          *((volatile unsigned int*)(0x42CF08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A21          *((volatile unsigned int*)(0x42CF08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A22          *((volatile unsigned int*)(0x42CF08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A23          *((volatile unsigned int*)(0x42CF08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A24          *((volatile unsigned int*)(0x42CF08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A25          *((volatile unsigned int*)(0x42CF08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A26          *((volatile unsigned int*)(0x42CF08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A27          *((volatile unsigned int*)(0x42CF08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A28          *((volatile unsigned int*)(0x42CF08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A29          *((volatile unsigned int*)(0x42CF08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A30          *((volatile unsigned int*)(0x42CF08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A31          *((volatile unsigned int*)(0x42CF08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A32          *((volatile unsigned int*)(0x42CF0900UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A33          *((volatile unsigned int*)(0x42CF0904UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A34          *((volatile unsigned int*)(0x42CF0908UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A35          *((volatile unsigned int*)(0x42CF090CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A36          *((volatile unsigned int*)(0x42CF0910UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A37          *((volatile unsigned int*)(0x42CF0914UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A38          *((volatile unsigned int*)(0x42CF0918UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A39          *((volatile unsigned int*)(0x42CF091CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A40          *((volatile unsigned int*)(0x42CF0920UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A41          *((volatile unsigned int*)(0x42CF0924UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A42          *((volatile unsigned int*)(0x42CF0928UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A43          *((volatile unsigned int*)(0x42CF092CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A44          *((volatile unsigned int*)(0x42CF0930UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A45          *((volatile unsigned int*)(0x42CF0934UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A46          *((volatile unsigned int*)(0x42CF0938UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A47          *((volatile unsigned int*)(0x42CF093CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC0         *((volatile unsigned int*)(0x42CF0960UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC1         *((volatile unsigned int*)(0x42CF0964UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC2         *((volatile unsigned int*)(0x42CF0968UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC3         *((volatile unsigned int*)(0x42CF096CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC4         *((volatile unsigned int*)(0x42CF0970UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC5         *((volatile unsigned int*)(0x42CF0974UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_SA           *((volatile unsigned int*)(0x42CF0978UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_AE           *((volatile unsigned int*)(0x42CF097CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A0           *((volatile unsigned int*)(0x42CF0980UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A1           *((volatile unsigned int*)(0x42CF0984UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A2           *((volatile unsigned int*)(0x42CF0988UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A3           *((volatile unsigned int*)(0x42CF098CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A4           *((volatile unsigned int*)(0x42CF0990UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A5           *((volatile unsigned int*)(0x42CF0994UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A6           *((volatile unsigned int*)(0x42CF0998UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A7           *((volatile unsigned int*)(0x42CF099CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A8           *((volatile unsigned int*)(0x42CF09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A9           *((volatile unsigned int*)(0x42CF09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A10          *((volatile unsigned int*)(0x42CF09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A11          *((volatile unsigned int*)(0x42CF09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A12          *((volatile unsigned int*)(0x42CF09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A13          *((volatile unsigned int*)(0x42CF09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A14          *((volatile unsigned int*)(0x42CF09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A15          *((volatile unsigned int*)(0x42CF09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A16          *((volatile unsigned int*)(0x42CF09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A17          *((volatile unsigned int*)(0x42CF09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A18          *((volatile unsigned int*)(0x42CF09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A19          *((volatile unsigned int*)(0x42CF09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A20          *((volatile unsigned int*)(0x42CF09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A21          *((volatile unsigned int*)(0x42CF09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A22          *((volatile unsigned int*)(0x42CF09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A23          *((volatile unsigned int*)(0x42CF09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A24          *((volatile unsigned int*)(0x42CF09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A25          *((volatile unsigned int*)(0x42CF09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A26          *((volatile unsigned int*)(0x42CF09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A27          *((volatile unsigned int*)(0x42CF09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A28          *((volatile unsigned int*)(0x42CF09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A29          *((volatile unsigned int*)(0x42CF09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A30          *((volatile unsigned int*)(0x42CF09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A31          *((volatile unsigned int*)(0x42CF09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A32          *((volatile unsigned int*)(0x42CF0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A33          *((volatile unsigned int*)(0x42CF0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A34          *((volatile unsigned int*)(0x42CF0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A35          *((volatile unsigned int*)(0x42CF0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A36          *((volatile unsigned int*)(0x42CF0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A37          *((volatile unsigned int*)(0x42CF0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A38          *((volatile unsigned int*)(0x42CF0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A39          *((volatile unsigned int*)(0x42CF0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A40          *((volatile unsigned int*)(0x42CF0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A41          *((volatile unsigned int*)(0x42CF0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A42          *((volatile unsigned int*)(0x42CF0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A43          *((volatile unsigned int*)(0x42CF0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A44          *((volatile unsigned int*)(0x42CF0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A45          *((volatile unsigned int*)(0x42CF0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A46          *((volatile unsigned int*)(0x42CF0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A47          *((volatile unsigned int*)(0x42CF0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC0         *((volatile unsigned int*)(0x42CF0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC1         *((volatile unsigned int*)(0x42CF0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC2         *((volatile unsigned int*)(0x42CF0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC3         *((volatile unsigned int*)(0x42CF0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC4         *((volatile unsigned int*)(0x42CF0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC5         *((volatile unsigned int*)(0x42CF0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_SA           *((volatile unsigned int*)(0x42CF0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_AE           *((volatile unsigned int*)(0x42CF0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A0           *((volatile unsigned int*)(0x42CF0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A1           *((volatile unsigned int*)(0x42CF0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A2           *((volatile unsigned int*)(0x42CF0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A3           *((volatile unsigned int*)(0x42CF0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A4           *((volatile unsigned int*)(0x42CF0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A5           *((volatile unsigned int*)(0x42CF0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A6           *((volatile unsigned int*)(0x42CF0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A7           *((volatile unsigned int*)(0x42CF0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A8           *((volatile unsigned int*)(0x42CF0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A9           *((volatile unsigned int*)(0x42CF0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A10          *((volatile unsigned int*)(0x42CF0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A11          *((volatile unsigned int*)(0x42CF0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A12          *((volatile unsigned int*)(0x42CF0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A13          *((volatile unsigned int*)(0x42CF0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A14          *((volatile unsigned int*)(0x42CF0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A15          *((volatile unsigned int*)(0x42CF0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A16          *((volatile unsigned int*)(0x42CF0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A17          *((volatile unsigned int*)(0x42CF0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A18          *((volatile unsigned int*)(0x42CF0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A19          *((volatile unsigned int*)(0x42CF0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A20          *((volatile unsigned int*)(0x42CF0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A21          *((volatile unsigned int*)(0x42CF0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A22          *((volatile unsigned int*)(0x42CF0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A23          *((volatile unsigned int*)(0x42CF0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A24          *((volatile unsigned int*)(0x42CF0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A25          *((volatile unsigned int*)(0x42CF0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A26          *((volatile unsigned int*)(0x42CF0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A27          *((volatile unsigned int*)(0x42CF0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A28          *((volatile unsigned int*)(0x42CF0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A29          *((volatile unsigned int*)(0x42CF0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A30          *((volatile unsigned int*)(0x42CF0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A31          *((volatile unsigned int*)(0x42CF0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A32          *((volatile unsigned int*)(0x42CF0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A33          *((volatile unsigned int*)(0x42CF0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A34          *((volatile unsigned int*)(0x42CF0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A35          *((volatile unsigned int*)(0x42CF0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A36          *((volatile unsigned int*)(0x42CF0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A37          *((volatile unsigned int*)(0x42CF0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A38          *((volatile unsigned int*)(0x42CF0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A39          *((volatile unsigned int*)(0x42CF0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A40          *((volatile unsigned int*)(0x42CF0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A41          *((volatile unsigned int*)(0x42CF0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A42          *((volatile unsigned int*)(0x42CF0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A43          *((volatile unsigned int*)(0x42CF0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A44          *((volatile unsigned int*)(0x42CF0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A45          *((volatile unsigned int*)(0x42CF0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A46          *((volatile unsigned int*)(0x42CF0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A47          *((volatile unsigned int*)(0x42CF0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC0         *((volatile unsigned int*)(0x42CF0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC1         *((volatile unsigned int*)(0x42CF0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC2         *((volatile unsigned int*)(0x42CF0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC3         *((volatile unsigned int*)(0x42CF0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC4         *((volatile unsigned int*)(0x42CF0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC5         *((volatile unsigned int*)(0x42CF0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_SA           *((volatile unsigned int*)(0x42CF0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_AE           *((volatile unsigned int*)(0x42CF0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A0           *((volatile unsigned int*)(0x42CF0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A1           *((volatile unsigned int*)(0x42CF0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A2           *((volatile unsigned int*)(0x42CF0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A3           *((volatile unsigned int*)(0x42CF0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A4           *((volatile unsigned int*)(0x42CF0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A5           *((volatile unsigned int*)(0x42CF0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A6           *((volatile unsigned int*)(0x42CF0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A7           *((volatile unsigned int*)(0x42CF0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A8           *((volatile unsigned int*)(0x42CF0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A9           *((volatile unsigned int*)(0x42CF0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A10          *((volatile unsigned int*)(0x42CF0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A11          *((volatile unsigned int*)(0x42CF0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A12          *((volatile unsigned int*)(0x42CF0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A13          *((volatile unsigned int*)(0x42CF0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A14          *((volatile unsigned int*)(0x42CF0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A15          *((volatile unsigned int*)(0x42CF0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A16          *((volatile unsigned int*)(0x42CF0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A17          *((volatile unsigned int*)(0x42CF0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A18          *((volatile unsigned int*)(0x42CF0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A19          *((volatile unsigned int*)(0x42CF0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A20          *((volatile unsigned int*)(0x42CF0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A21          *((volatile unsigned int*)(0x42CF0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A22          *((volatile unsigned int*)(0x42CF0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A23          *((volatile unsigned int*)(0x42CF0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A24          *((volatile unsigned int*)(0x42CF0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A25          *((volatile unsigned int*)(0x42CF0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A26          *((volatile unsigned int*)(0x42CF0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A27          *((volatile unsigned int*)(0x42CF0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A28          *((volatile unsigned int*)(0x42CF0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A29          *((volatile unsigned int*)(0x42CF0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A30          *((volatile unsigned int*)(0x42CF0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A31          *((volatile unsigned int*)(0x42CF0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A32          *((volatile unsigned int*)(0x42CF0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A33          *((volatile unsigned int*)(0x42CF0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A34          *((volatile unsigned int*)(0x42CF0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A35          *((volatile unsigned int*)(0x42CF0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A36          *((volatile unsigned int*)(0x42CF0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A37          *((volatile unsigned int*)(0x42CF0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A38          *((volatile unsigned int*)(0x42CF0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A39          *((volatile unsigned int*)(0x42CF0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A40          *((volatile unsigned int*)(0x42CF0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A41          *((volatile unsigned int*)(0x42CF0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A42          *((volatile unsigned int*)(0x42CF0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A43          *((volatile unsigned int*)(0x42CF0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A44          *((volatile unsigned int*)(0x42CF0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A45          *((volatile unsigned int*)(0x42CF0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A46          *((volatile unsigned int*)(0x42CF0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A47          *((volatile unsigned int*)(0x42CF0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC0         *((volatile unsigned int*)(0x42CF0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC1         *((volatile unsigned int*)(0x42CF0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC2         *((volatile unsigned int*)(0x42CF0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC3         *((volatile unsigned int*)(0x42CF0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC4         *((volatile unsigned int*)(0x42CF0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC5         *((volatile unsigned int*)(0x42CF0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_SA           *((volatile unsigned int*)(0x42CF0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_AE           *((volatile unsigned int*)(0x42CF0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A0           *((volatile unsigned int*)(0x42CF0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A1           *((volatile unsigned int*)(0x42CF0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A2           *((volatile unsigned int*)(0x42CF0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A3           *((volatile unsigned int*)(0x42CF0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A4           *((volatile unsigned int*)(0x42CF0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A5           *((volatile unsigned int*)(0x42CF0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A6           *((volatile unsigned int*)(0x42CF0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A7           *((volatile unsigned int*)(0x42CF0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A8           *((volatile unsigned int*)(0x42CF0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A9           *((volatile unsigned int*)(0x42CF0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A10          *((volatile unsigned int*)(0x42CF0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A11          *((volatile unsigned int*)(0x42CF0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A12          *((volatile unsigned int*)(0x42CF0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A13          *((volatile unsigned int*)(0x42CF0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A14          *((volatile unsigned int*)(0x42CF0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A15          *((volatile unsigned int*)(0x42CF0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A16          *((volatile unsigned int*)(0x42CF0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A17          *((volatile unsigned int*)(0x42CF0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A18          *((volatile unsigned int*)(0x42CF0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A19          *((volatile unsigned int*)(0x42CF0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A20          *((volatile unsigned int*)(0x42CF0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A21          *((volatile unsigned int*)(0x42CF0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A22          *((volatile unsigned int*)(0x42CF0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A23          *((volatile unsigned int*)(0x42CF0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A24          *((volatile unsigned int*)(0x42CF0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A25          *((volatile unsigned int*)(0x42CF0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A26          *((volatile unsigned int*)(0x42CF0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A27          *((volatile unsigned int*)(0x42CF0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A28          *((volatile unsigned int*)(0x42CF0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A29          *((volatile unsigned int*)(0x42CF0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A30          *((volatile unsigned int*)(0x42CF0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A31          *((volatile unsigned int*)(0x42CF0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A32          *((volatile unsigned int*)(0x42CF0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A33          *((volatile unsigned int*)(0x42CF0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A34          *((volatile unsigned int*)(0x42CF0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A35          *((volatile unsigned int*)(0x42CF0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A36          *((volatile unsigned int*)(0x42CF0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A37          *((volatile unsigned int*)(0x42CF0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A38          *((volatile unsigned int*)(0x42CF0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A39          *((volatile unsigned int*)(0x42CF0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A40          *((volatile unsigned int*)(0x42CF0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A41          *((volatile unsigned int*)(0x42CF0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A42          *((volatile unsigned int*)(0x42CF0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A43          *((volatile unsigned int*)(0x42CF0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A44          *((volatile unsigned int*)(0x42CF0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A45          *((volatile unsigned int*)(0x42CF0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A46          *((volatile unsigned int*)(0x42CF0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A47          *((volatile unsigned int*)(0x42CF0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC0         *((volatile unsigned int*)(0x42CF0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC1         *((volatile unsigned int*)(0x42CF0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC2         *((volatile unsigned int*)(0x42CF0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC3         *((volatile unsigned int*)(0x42CF0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC4         *((volatile unsigned int*)(0x42CF0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC5         *((volatile unsigned int*)(0x42CF0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_SA           *((volatile unsigned int*)(0x42CF0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_AE           *((volatile unsigned int*)(0x42CF0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A0           *((volatile unsigned int*)(0x42CF0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A1           *((volatile unsigned int*)(0x42CF0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A2           *((volatile unsigned int*)(0x42CF0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A3           *((volatile unsigned int*)(0x42CF0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A4           *((volatile unsigned int*)(0x42CF0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A5           *((volatile unsigned int*)(0x42CF0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A6           *((volatile unsigned int*)(0x42CF0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A7           *((volatile unsigned int*)(0x42CF0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A8           *((volatile unsigned int*)(0x42CF0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A9           *((volatile unsigned int*)(0x42CF0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A10          *((volatile unsigned int*)(0x42CF0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A11          *((volatile unsigned int*)(0x42CF0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A12          *((volatile unsigned int*)(0x42CF0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A13          *((volatile unsigned int*)(0x42CF0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A14          *((volatile unsigned int*)(0x42CF0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A15          *((volatile unsigned int*)(0x42CF0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A16          *((volatile unsigned int*)(0x42CF0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A17          *((volatile unsigned int*)(0x42CF0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A18          *((volatile unsigned int*)(0x42CF0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A19          *((volatile unsigned int*)(0x42CF0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A20          *((volatile unsigned int*)(0x42CF0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A21          *((volatile unsigned int*)(0x42CF0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A22          *((volatile unsigned int*)(0x42CF0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A23          *((volatile unsigned int*)(0x42CF0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A24          *((volatile unsigned int*)(0x42CF0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A25          *((volatile unsigned int*)(0x42CF0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A26          *((volatile unsigned int*)(0x42CF0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A27          *((volatile unsigned int*)(0x42CF0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A28          *((volatile unsigned int*)(0x42CF0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A29          *((volatile unsigned int*)(0x42CF0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A30          *((volatile unsigned int*)(0x42CF0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A31          *((volatile unsigned int*)(0x42CF0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A32          *((volatile unsigned int*)(0x42CF0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A33          *((volatile unsigned int*)(0x42CF0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A34          *((volatile unsigned int*)(0x42CF0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A35          *((volatile unsigned int*)(0x42CF0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A36          *((volatile unsigned int*)(0x42CF0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A37          *((volatile unsigned int*)(0x42CF0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A38          *((volatile unsigned int*)(0x42CF0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A39          *((volatile unsigned int*)(0x42CF0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A40          *((volatile unsigned int*)(0x42CF0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A41          *((volatile unsigned int*)(0x42CF0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A42          *((volatile unsigned int*)(0x42CF0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A43          *((volatile unsigned int*)(0x42CF0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A44          *((volatile unsigned int*)(0x42CF0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A45          *((volatile unsigned int*)(0x42CF0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A46          *((volatile unsigned int*)(0x42CF0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A47          *((volatile unsigned int*)(0x42CF0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC0         *((volatile unsigned int*)(0x42CF0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC1         *((volatile unsigned int*)(0x42CF0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC2         *((volatile unsigned int*)(0x42CF0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC3         *((volatile unsigned int*)(0x42CF0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC4         *((volatile unsigned int*)(0x42CF0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC5         *((volatile unsigned int*)(0x42CF0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_SA           *((volatile unsigned int*)(0x42CF0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_AE           *((volatile unsigned int*)(0x42CF0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A0           *((volatile unsigned int*)(0x42CF0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A1           *((volatile unsigned int*)(0x42CF0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A2           *((volatile unsigned int*)(0x42CF0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A3           *((volatile unsigned int*)(0x42CF0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A4           *((volatile unsigned int*)(0x42CF0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A5           *((volatile unsigned int*)(0x42CF0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A6           *((volatile unsigned int*)(0x42CF0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A7           *((volatile unsigned int*)(0x42CF0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A8           *((volatile unsigned int*)(0x42CF0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A9           *((volatile unsigned int*)(0x42CF0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A10          *((volatile unsigned int*)(0x42CF0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A11          *((volatile unsigned int*)(0x42CF0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A12          *((volatile unsigned int*)(0x42CF0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A13          *((volatile unsigned int*)(0x42CF0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A14          *((volatile unsigned int*)(0x42CF0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A15          *((volatile unsigned int*)(0x42CF0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A16          *((volatile unsigned int*)(0x42CF0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A17          *((volatile unsigned int*)(0x42CF0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A18          *((volatile unsigned int*)(0x42CF0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A19          *((volatile unsigned int*)(0x42CF0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A20          *((volatile unsigned int*)(0x42CF0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A21          *((volatile unsigned int*)(0x42CF0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A22          *((volatile unsigned int*)(0x42CF0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A23          *((volatile unsigned int*)(0x42CF0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A24          *((volatile unsigned int*)(0x42CF0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A25          *((volatile unsigned int*)(0x42CF0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A26          *((volatile unsigned int*)(0x42CF0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A27          *((volatile unsigned int*)(0x42CF0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A28          *((volatile unsigned int*)(0x42CF0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A29          *((volatile unsigned int*)(0x42CF0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A30          *((volatile unsigned int*)(0x42CF0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A31          *((volatile unsigned int*)(0x42CF0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A32          *((volatile unsigned int*)(0x42CF0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A33          *((volatile unsigned int*)(0x42CF0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A34          *((volatile unsigned int*)(0x42CF0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A35          *((volatile unsigned int*)(0x42CF0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A36          *((volatile unsigned int*)(0x42CF0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A37          *((volatile unsigned int*)(0x42CF0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A38          *((volatile unsigned int*)(0x42CF0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A39          *((volatile unsigned int*)(0x42CF0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A40          *((volatile unsigned int*)(0x42CF0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A41          *((volatile unsigned int*)(0x42CF0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A42          *((volatile unsigned int*)(0x42CF0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A43          *((volatile unsigned int*)(0x42CF0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A44          *((volatile unsigned int*)(0x42CF0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A45          *((volatile unsigned int*)(0x42CF0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A46          *((volatile unsigned int*)(0x42CF0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A47          *((volatile unsigned int*)(0x42CF0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC0         *((volatile unsigned int*)(0x42CF0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC1         *((volatile unsigned int*)(0x42CF0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC2         *((volatile unsigned int*)(0x42CF0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC3         *((volatile unsigned int*)(0x42CF0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC4         *((volatile unsigned int*)(0x42CF0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC5         *((volatile unsigned int*)(0x42CF0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_SA           *((volatile unsigned int*)(0x42CF0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_AE           *((volatile unsigned int*)(0x42CF0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A0           *((volatile unsigned int*)(0x42CF0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A1           *((volatile unsigned int*)(0x42CF0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A2           *((volatile unsigned int*)(0x42CF0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A3           *((volatile unsigned int*)(0x42CF0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A4           *((volatile unsigned int*)(0x42CF0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A5           *((volatile unsigned int*)(0x42CF0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A6           *((volatile unsigned int*)(0x42CF0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A7           *((volatile unsigned int*)(0x42CF0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A8           *((volatile unsigned int*)(0x42CF0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A9           *((volatile unsigned int*)(0x42CF0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A10          *((volatile unsigned int*)(0x42CF0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A11          *((volatile unsigned int*)(0x42CF0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A12          *((volatile unsigned int*)(0x42CF0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A13          *((volatile unsigned int*)(0x42CF0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A14          *((volatile unsigned int*)(0x42CF0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A15          *((volatile unsigned int*)(0x42CF0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A16          *((volatile unsigned int*)(0x42CF0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A17          *((volatile unsigned int*)(0x42CF0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A18          *((volatile unsigned int*)(0x42CF0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A19          *((volatile unsigned int*)(0x42CF0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A20          *((volatile unsigned int*)(0x42CF0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A21          *((volatile unsigned int*)(0x42CF0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A22          *((volatile unsigned int*)(0x42CF0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A23          *((volatile unsigned int*)(0x42CF0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A24          *((volatile unsigned int*)(0x42CF0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A25          *((volatile unsigned int*)(0x42CF0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A26          *((volatile unsigned int*)(0x42CF0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A27          *((volatile unsigned int*)(0x42CF0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A28          *((volatile unsigned int*)(0x42CF0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A29          *((volatile unsigned int*)(0x42CF0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A30          *((volatile unsigned int*)(0x42CF0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A31          *((volatile unsigned int*)(0x42CF0FFCUL))
+#define bFM3_ETHERNET_MAC1_BMR_SWR             *((volatile unsigned int*)(0x42D00000UL))
+#define bFM3_ETHERNET_MAC1_BMR_DA              *((volatile unsigned int*)(0x42D00004UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL0            *((volatile unsigned int*)(0x42D00008UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL1            *((volatile unsigned int*)(0x42D0000CUL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL2            *((volatile unsigned int*)(0x42D00010UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL3            *((volatile unsigned int*)(0x42D00014UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL4            *((volatile unsigned int*)(0x42D00018UL))
+#define bFM3_ETHERNET_MAC1_BMR_ATDS            *((volatile unsigned int*)(0x42D0001CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL0            *((volatile unsigned int*)(0x42D00020UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL1            *((volatile unsigned int*)(0x42D00024UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL2            *((volatile unsigned int*)(0x42D00028UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL3            *((volatile unsigned int*)(0x42D0002CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL4            *((volatile unsigned int*)(0x42D00030UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL5            *((volatile unsigned int*)(0x42D00034UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR0             *((volatile unsigned int*)(0x42D00038UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR1             *((volatile unsigned int*)(0x42D0003CUL))
+#define bFM3_ETHERNET_MAC1_BMR_FB              *((volatile unsigned int*)(0x42D00040UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL0           *((volatile unsigned int*)(0x42D00044UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL1           *((volatile unsigned int*)(0x42D00048UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL2           *((volatile unsigned int*)(0x42D0004CUL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL3           *((volatile unsigned int*)(0x42D00050UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL4           *((volatile unsigned int*)(0x42D00054UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL5           *((volatile unsigned int*)(0x42D00058UL))
+#define bFM3_ETHERNET_MAC1_BMR_USP             *((volatile unsigned int*)(0x42D0005CUL))
+#define bFM3_ETHERNET_MAC1_BMR_8XPBL           *((volatile unsigned int*)(0x42D00060UL))
+#define bFM3_ETHERNET_MAC1_BMR_AAL             *((volatile unsigned int*)(0x42D00064UL))
+#define bFM3_ETHERNET_MAC1_BMR_MB              *((volatile unsigned int*)(0x42D00068UL))
+#define bFM3_ETHERNET_MAC1_BMR_TXPR            *((volatile unsigned int*)(0x42D0006CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD0           *((volatile unsigned int*)(0x42D00080UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD1           *((volatile unsigned int*)(0x42D00084UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD2           *((volatile unsigned int*)(0x42D00088UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD3           *((volatile unsigned int*)(0x42D0008CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD4           *((volatile unsigned int*)(0x42D00090UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD5           *((volatile unsigned int*)(0x42D00094UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD6           *((volatile unsigned int*)(0x42D00098UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD7           *((volatile unsigned int*)(0x42D0009CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD8           *((volatile unsigned int*)(0x42D000A0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD9           *((volatile unsigned int*)(0x42D000A4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD10          *((volatile unsigned int*)(0x42D000A8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD11          *((volatile unsigned int*)(0x42D000ACUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD12          *((volatile unsigned int*)(0x42D000B0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD13          *((volatile unsigned int*)(0x42D000B4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD14          *((volatile unsigned int*)(0x42D000B8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD15          *((volatile unsigned int*)(0x42D000BCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD16          *((volatile unsigned int*)(0x42D000C0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD17          *((volatile unsigned int*)(0x42D000C4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD18          *((volatile unsigned int*)(0x42D000C8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD19          *((volatile unsigned int*)(0x42D000CCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD20          *((volatile unsigned int*)(0x42D000D0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD21          *((volatile unsigned int*)(0x42D000D4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD22          *((volatile unsigned int*)(0x42D000D8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD23          *((volatile unsigned int*)(0x42D000DCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD24          *((volatile unsigned int*)(0x42D000E0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD25          *((volatile unsigned int*)(0x42D000E4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD26          *((volatile unsigned int*)(0x42D000E8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD27          *((volatile unsigned int*)(0x42D000ECUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD28          *((volatile unsigned int*)(0x42D000F0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD29          *((volatile unsigned int*)(0x42D000F4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD30          *((volatile unsigned int*)(0x42D000F8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD31          *((volatile unsigned int*)(0x42D000FCUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD0           *((volatile unsigned int*)(0x42D00100UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD1           *((volatile unsigned int*)(0x42D00104UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD2           *((volatile unsigned int*)(0x42D00108UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD3           *((volatile unsigned int*)(0x42D0010CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD4           *((volatile unsigned int*)(0x42D00110UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD5           *((volatile unsigned int*)(0x42D00114UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD6           *((volatile unsigned int*)(0x42D00118UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD7           *((volatile unsigned int*)(0x42D0011CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD8           *((volatile unsigned int*)(0x42D00120UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD9           *((volatile unsigned int*)(0x42D00124UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD10          *((volatile unsigned int*)(0x42D00128UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD11          *((volatile unsigned int*)(0x42D0012CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD12          *((volatile unsigned int*)(0x42D00130UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD13          *((volatile unsigned int*)(0x42D00134UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD14          *((volatile unsigned int*)(0x42D00138UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD15          *((volatile unsigned int*)(0x42D0013CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD16          *((volatile unsigned int*)(0x42D00140UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD17          *((volatile unsigned int*)(0x42D00144UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD18          *((volatile unsigned int*)(0x42D00148UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD19          *((volatile unsigned int*)(0x42D0014CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD20          *((volatile unsigned int*)(0x42D00150UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD21          *((volatile unsigned int*)(0x42D00154UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD22          *((volatile unsigned int*)(0x42D00158UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD23          *((volatile unsigned int*)(0x42D0015CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD24          *((volatile unsigned int*)(0x42D00160UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD25          *((volatile unsigned int*)(0x42D00164UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD26          *((volatile unsigned int*)(0x42D00168UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD27          *((volatile unsigned int*)(0x42D0016CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD28          *((volatile unsigned int*)(0x42D00170UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD29          *((volatile unsigned int*)(0x42D00174UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD30          *((volatile unsigned int*)(0x42D00178UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD31          *((volatile unsigned int*)(0x42D0017CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL2          *((volatile unsigned int*)(0x42D00188UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL3          *((volatile unsigned int*)(0x42D0018CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL4          *((volatile unsigned int*)(0x42D00190UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL5          *((volatile unsigned int*)(0x42D00194UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL6          *((volatile unsigned int*)(0x42D00198UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL7          *((volatile unsigned int*)(0x42D0019CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL8          *((volatile unsigned int*)(0x42D001A0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL9          *((volatile unsigned int*)(0x42D001A4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL10         *((volatile unsigned int*)(0x42D001A8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL11         *((volatile unsigned int*)(0x42D001ACUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL12         *((volatile unsigned int*)(0x42D001B0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL13         *((volatile unsigned int*)(0x42D001B4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL14         *((volatile unsigned int*)(0x42D001B8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL15         *((volatile unsigned int*)(0x42D001BCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL16         *((volatile unsigned int*)(0x42D001C0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL17         *((volatile unsigned int*)(0x42D001C4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL18         *((volatile unsigned int*)(0x42D001C8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL19         *((volatile unsigned int*)(0x42D001CCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL20         *((volatile unsigned int*)(0x42D001D0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL21         *((volatile unsigned int*)(0x42D001D4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL22         *((volatile unsigned int*)(0x42D001D8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL23         *((volatile unsigned int*)(0x42D001DCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL24         *((volatile unsigned int*)(0x42D001E0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL25         *((volatile unsigned int*)(0x42D001E4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL26         *((volatile unsigned int*)(0x42D001E8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL27         *((volatile unsigned int*)(0x42D001ECUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL28         *((volatile unsigned int*)(0x42D001F0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL29         *((volatile unsigned int*)(0x42D001F4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL30         *((volatile unsigned int*)(0x42D001F8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL31         *((volatile unsigned int*)(0x42D001FCUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL2          *((volatile unsigned int*)(0x42D00208UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL3          *((volatile unsigned int*)(0x42D0020CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL4          *((volatile unsigned int*)(0x42D00210UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL5          *((volatile unsigned int*)(0x42D00214UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL6          *((volatile unsigned int*)(0x42D00218UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL7          *((volatile unsigned int*)(0x42D0021CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL8          *((volatile unsigned int*)(0x42D00220UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL9          *((volatile unsigned int*)(0x42D00224UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL10         *((volatile unsigned int*)(0x42D00228UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL11         *((volatile unsigned int*)(0x42D0022CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL12         *((volatile unsigned int*)(0x42D00230UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL13         *((volatile unsigned int*)(0x42D00234UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL14         *((volatile unsigned int*)(0x42D00238UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL15         *((volatile unsigned int*)(0x42D0023CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL16         *((volatile unsigned int*)(0x42D00240UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL17         *((volatile unsigned int*)(0x42D00244UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL18         *((volatile unsigned int*)(0x42D00248UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL19         *((volatile unsigned int*)(0x42D0024CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL20         *((volatile unsigned int*)(0x42D00250UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL21         *((volatile unsigned int*)(0x42D00254UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL22         *((volatile unsigned int*)(0x42D00258UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL23         *((volatile unsigned int*)(0x42D0025CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL24         *((volatile unsigned int*)(0x42D00260UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL25         *((volatile unsigned int*)(0x42D00264UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL26         *((volatile unsigned int*)(0x42D00268UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL27         *((volatile unsigned int*)(0x42D0026CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL28         *((volatile unsigned int*)(0x42D00270UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL29         *((volatile unsigned int*)(0x42D00274UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL30         *((volatile unsigned int*)(0x42D00278UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL31         *((volatile unsigned int*)(0x42D0027CUL))
+#define bFM3_ETHERNET_MAC1_SR_TI               *((volatile unsigned int*)(0x42D00280UL))
+#define bFM3_ETHERNET_MAC1_SR_TPS              *((volatile unsigned int*)(0x42D00284UL))
+#define bFM3_ETHERNET_MAC1_SR_TU               *((volatile unsigned int*)(0x42D00288UL))
+#define bFM3_ETHERNET_MAC1_SR_TJT              *((volatile unsigned int*)(0x42D0028CUL))
+#define bFM3_ETHERNET_MAC1_SR_OVF              *((volatile unsigned int*)(0x42D00290UL))
+#define bFM3_ETHERNET_MAC1_SR_UNF              *((volatile unsigned int*)(0x42D00294UL))
+#define bFM3_ETHERNET_MAC1_SR_RI               *((volatile unsigned int*)(0x42D00298UL))
+#define bFM3_ETHERNET_MAC1_SR_RU               *((volatile unsigned int*)(0x42D0029CUL))
+#define bFM3_ETHERNET_MAC1_SR_RPS              *((volatile unsigned int*)(0x42D002A0UL))
+#define bFM3_ETHERNET_MAC1_SR_RWT              *((volatile unsigned int*)(0x42D002A4UL))
+#define bFM3_ETHERNET_MAC1_SR_ETI              *((volatile unsigned int*)(0x42D002A8UL))
+#define bFM3_ETHERNET_MAC1_SR_FBI              *((volatile unsigned int*)(0x42D002B4UL))
+#define bFM3_ETHERNET_MAC1_SR_ERI              *((volatile unsigned int*)(0x42D002B8UL))
+#define bFM3_ETHERNET_MAC1_SR_AIS              *((volatile unsigned int*)(0x42D002BCUL))
+#define bFM3_ETHERNET_MAC1_SR_NIS              *((volatile unsigned int*)(0x42D002C0UL))
+#define bFM3_ETHERNET_MAC1_SR_RS0              *((volatile unsigned int*)(0x42D002C4UL))
+#define bFM3_ETHERNET_MAC1_SR_RS1              *((volatile unsigned int*)(0x42D002C8UL))
+#define bFM3_ETHERNET_MAC1_SR_RS2              *((volatile unsigned int*)(0x42D002CCUL))
+#define bFM3_ETHERNET_MAC1_SR_TS0              *((volatile unsigned int*)(0x42D002D0UL))
+#define bFM3_ETHERNET_MAC1_SR_TS1              *((volatile unsigned int*)(0x42D002D4UL))
+#define bFM3_ETHERNET_MAC1_SR_TS2              *((volatile unsigned int*)(0x42D002D8UL))
+#define bFM3_ETHERNET_MAC1_SR_EB0              *((volatile unsigned int*)(0x42D002DCUL))
+#define bFM3_ETHERNET_MAC1_SR_EB1              *((volatile unsigned int*)(0x42D002E0UL))
+#define bFM3_ETHERNET_MAC1_SR_EB2              *((volatile unsigned int*)(0x42D002E4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLI              *((volatile unsigned int*)(0x42D002E8UL))
+#define bFM3_ETHERNET_MAC1_SR_GMI              *((volatile unsigned int*)(0x42D002ECUL))
+#define bFM3_ETHERNET_MAC1_SR_GPI              *((volatile unsigned int*)(0x42D002F0UL))
+#define bFM3_ETHERNET_MAC1_SR_TTI              *((volatile unsigned int*)(0x42D002F4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLPII            *((volatile unsigned int*)(0x42D002F8UL))
+#define bFM3_ETHERNET_MAC1_OMR_SR              *((volatile unsigned int*)(0x42D00304UL))
+#define bFM3_ETHERNET_MAC1_OMR_OSF             *((volatile unsigned int*)(0x42D00308UL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC0            *((volatile unsigned int*)(0x42D0030CUL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC1            *((volatile unsigned int*)(0x42D00310UL))
+#define bFM3_ETHERNET_MAC1_OMR_FUF             *((volatile unsigned int*)(0x42D00318UL))
+#define bFM3_ETHERNET_MAC1_OMR_FEF             *((volatile unsigned int*)(0x42D0031CUL))
+#define bFM3_ETHERNET_MAC1_OMR_ST              *((volatile unsigned int*)(0x42D00334UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC0            *((volatile unsigned int*)(0x42D00338UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC1            *((volatile unsigned int*)(0x42D0033CUL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC2            *((volatile unsigned int*)(0x42D00340UL))
+#define bFM3_ETHERNET_MAC1_OMR_FTF             *((volatile unsigned int*)(0x42D00350UL))
+#define bFM3_ETHERNET_MAC1_OMR_TSF             *((volatile unsigned int*)(0x42D00354UL))
+#define bFM3_ETHERNET_MAC1_OMR_DFF             *((volatile unsigned int*)(0x42D00360UL))
+#define bFM3_ETHERNET_MAC1_OMR_RSF             *((volatile unsigned int*)(0x42D00364UL))
+#define bFM3_ETHERNET_MAC1_OMR_DT              *((volatile unsigned int*)(0x42D00368UL))
+#define bFM3_ETHERNET_MAC1_IER_TIE             *((volatile unsigned int*)(0x42D00380UL))
+#define bFM3_ETHERNET_MAC1_IER_TSE             *((volatile unsigned int*)(0x42D00384UL))
+#define bFM3_ETHERNET_MAC1_IER_TUE             *((volatile unsigned int*)(0x42D00388UL))
+#define bFM3_ETHERNET_MAC1_IER_TJE             *((volatile unsigned int*)(0x42D0038CUL))
+#define bFM3_ETHERNET_MAC1_IER_OVE             *((volatile unsigned int*)(0x42D00390UL))
+#define bFM3_ETHERNET_MAC1_IER_UNE             *((volatile unsigned int*)(0x42D00394UL))
+#define bFM3_ETHERNET_MAC1_IER_RIE             *((volatile unsigned int*)(0x42D00398UL))
+#define bFM3_ETHERNET_MAC1_IER_RUE             *((volatile unsigned int*)(0x42D0039CUL))
+#define bFM3_ETHERNET_MAC1_IER_RSE             *((volatile unsigned int*)(0x42D003A0UL))
+#define bFM3_ETHERNET_MAC1_IER_RWE             *((volatile unsigned int*)(0x42D003A4UL))
+#define bFM3_ETHERNET_MAC1_IER_ETE             *((volatile unsigned int*)(0x42D003A8UL))
+#define bFM3_ETHERNET_MAC1_IER_FBE             *((volatile unsigned int*)(0x42D003B4UL))
+#define bFM3_ETHERNET_MAC1_IER_ERE             *((volatile unsigned int*)(0x42D003B8UL))
+#define bFM3_ETHERNET_MAC1_IER_AIE             *((volatile unsigned int*)(0x42D003BCUL))
+#define bFM3_ETHERNET_MAC1_IER_NIE             *((volatile unsigned int*)(0x42D003C0UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42D00400UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42D00404UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42D00408UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42D0040CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42D00410UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42D00414UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42D00418UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42D0041CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42D00420UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42D00424UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42D00428UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42D0042CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42D00430UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42D00434UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42D00438UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42D0043CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42D00440UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42D00444UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42D00448UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42D0044CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42D00450UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42D00454UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42D00458UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42D0045CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42D00460UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42D00464UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42D00468UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42D0046CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42D00470UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0         *((volatile unsigned int*)(0x42D00480UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1         *((volatile unsigned int*)(0x42D00484UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2         *((volatile unsigned int*)(0x42D00488UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3         *((volatile unsigned int*)(0x42D0048CUL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4         *((volatile unsigned int*)(0x42D00490UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5         *((volatile unsigned int*)(0x42D00494UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6         *((volatile unsigned int*)(0x42D00498UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7         *((volatile unsigned int*)(0x42D0049CUL))
+#define bFM3_ETHERNET_MAC1_AHBSR_AHBS          *((volatile unsigned int*)(0x42D00580UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42D00900UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42D00904UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42D00908UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42D0090CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42D00910UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42D00914UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42D00918UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42D0091CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42D00920UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42D00924UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42D00928UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42D0092CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42D00930UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42D00934UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42D00938UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42D0093CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42D00940UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42D00944UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42D00948UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42D0094CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42D00950UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42D00954UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42D00958UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42D0095CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42D00960UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42D00964UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42D00968UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42D0096CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42D00970UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42D00974UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42D00978UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42D0097CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42D00980UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42D00984UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42D00988UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42D0098CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42D00990UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42D00994UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42D00998UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42D0099CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42D009A0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42D009A4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42D009A8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42D009ACUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42D009B0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42D009B4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42D009B8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42D009BCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42D009C0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42D009C4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42D009C8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42D009CCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42D009D0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42D009D4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42D009D8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42D009DCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42D009E0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42D009E4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42D009E8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42D009ECUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42D009F0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42D009F4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42D009F8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42D009FCUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42D00A00UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42D00A04UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42D00A08UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42D00A0CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42D00A10UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42D00A14UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42D00A18UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42D00A1CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42D00A20UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42D00A24UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42D00A28UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42D00A2CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42D00A30UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42D00A34UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42D00A38UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42D00A3CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42D00A40UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42D00A44UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42D00A48UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42D00A4CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42D00A50UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42D00A54UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42D00A58UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42D00A5CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42D00A60UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42D00A64UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42D00A68UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42D00A6CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42D00A70UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42D00A74UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42D00A78UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42D00A7CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42D00A80UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42D00A84UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42D00A88UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42D00A8CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42D00A90UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42D00A94UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42D00A98UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42D00A9CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42D00AA0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42D00AA4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42D00AA8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42D00AACUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42D00AB0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42D00AB4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42D00AB8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42D00ABCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42D00AC0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42D00AC4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42D00AC8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42D00ACCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42D00AD0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42D00AD4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42D00AD8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42D00ADCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42D00AE0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42D00AE4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42D00AE8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42D00AECUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42D00AF0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42D00AF4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42D00AF8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42D00AFCUL))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MB9B610T_H_ */
+
diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S
new file mode 100644
index 0000000000..85d59276e2
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S
@@ -0,0 +1,333 @@
+;/************************************************************************/
+;/*               (C) Fujitsu Semiconductor Europe GmbH                  */
+;/*                                                                      */
+;/* The following software deliverable is intended for and must only be  */
+;/* used for reference and in an evaluation laboratory environment.      */
+;/* It is provided on an as-is basis without charge and is subject to    */
+;/* alterations.                                                         */
+;/* It is the user’s obligation to fully test the software in its        */
+;/* environment and to ensure proper functionality, qualification and    */
+;/* compliance with component specifications.                            */
+;/*                                                                      */
+;/* In the event the software deliverable includes the use of open       */
+;/* source components, the provisions of the governing open source       */
+;/* license agreement shall apply with respect to such software          */
+;/* deliverable.                                                         */
+;/* FSEU does not warrant that the deliverables do not infringe any      */
+;/* third party intellectual property right (IPR). In the event that     */
+;/* the deliverables infringe a third party IPR it is the sole           */
+;/* responsibility of the customer to obtain necessary licenses to       */
+;/* continue the usage of the deliverable.                               */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not       */
+;/* limited to, warranties of merchantability and fitness for a          */
+;/* particular purpose for which the deliverable is not designated.      */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */
+;/* is restricted to intention and gross negligence.                     */
+;/* FSEU is not liable for consequential damages.                        */
+;/*                                                                      */
+;/* (V1.4)                                                               */
+;/************************************************************************/
+;/*  Startup for ARM                                                     */
+;/*  Version     V1.02                                                   */
+;/*  Date        2011-07-25                                              */
+;/*  Target-mcu  MB9B61x                                                 */
+;/************************************************************************/
+
+; Stack Configuration
+;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                DCD     CSV_Handler               ; 0: Clock Super Visor
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer
+                DCD     LVD_Handler               ; 2: Low Voltage Detector
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7
+                DCD     INT8_31_Handler           ; 5: External Interrupt Request ch.8 to ch.31
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7
+                DCD     PPG_Handler               ; 23: PPG
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter
+                DCD     ADC0_IRQHandler           ; 25: ADC0
+                DCD     ADC1_IRQHandler           ; 26: ADC1
+                DCD     ADC2_IRQHandler           ; 27: ADC2
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare
+                DCD     BT0_7_IRQHandler          ; 31: Base Timer ch.0 to ch.7
+                DCD     ETHER_MAC0_IRQHandler     ; 32: Ethernet MAC ch.0
+                DCD     ETHER_MAC1_IRQHandler     ; 33: Ethernet MAC ch.1
+                DCD     USB0F_Handler             ; 34: USB0 Function
+                DCD     USB0_Handler              ; 35: USB0 Function / USB0 HOST
+                DCD     USB1F_Handler             ; 36: USB1 Function
+                DCD     USB1_Handler              ; 37: USB1 Function / USB1 HOST
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7
+                DCD     BT8_15_IRQHandler         ; 46: Base Timer ch.8 to ch.15
+                DCD     DummyHandler              ; 47: Reserved
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  CSV_Handler	          [WEAK]
+                EXPORT  SWDT_Handler              [WEAK]
+                EXPORT  LVD_Handler               [WEAK]
+                EXPORT  MFT_WG_IRQHandler         [WEAK]
+                EXPORT  INT0_7_Handler            [WEAK]
+                EXPORT  INT8_31_Handler           [WEAK]
+                EXPORT  DT_Handler                [WEAK]
+                EXPORT  MFS0RX_IRQHandler         [WEAK]
+                EXPORT  MFS0TX_IRQHandler         [WEAK]
+                EXPORT  MFS1RX_IRQHandler         [WEAK]
+                EXPORT  MFS1TX_IRQHandler         [WEAK]
+                EXPORT  MFS2RX_IRQHandler         [WEAK]
+                EXPORT  MFS2TX_IRQHandler         [WEAK]
+                EXPORT  MFS3RX_IRQHandler         [WEAK]
+                EXPORT  MFS3TX_IRQHandler         [WEAK]
+                EXPORT  MFS4RX_IRQHandler         [WEAK]
+                EXPORT  MFS4TX_IRQHandler         [WEAK]
+                EXPORT  MFS5RX_IRQHandler         [WEAK]
+                EXPORT  MFS5TX_IRQHandler         [WEAK]
+                EXPORT  MFS6RX_IRQHandler         [WEAK]
+                EXPORT  MFS6TX_IRQHandler         [WEAK]
+                EXPORT  MFS7RX_IRQHandler         [WEAK]
+                EXPORT  MFS7TX_IRQHandler         [WEAK]
+                EXPORT  PPG_Handler               [WEAK]
+                EXPORT  TIM_IRQHandler            [WEAK]
+                EXPORT  ADC0_IRQHandler           [WEAK]
+                EXPORT  ADC1_IRQHandler           [WEAK]
+                EXPORT  ADC2_IRQHandler           [WEAK]
+                EXPORT  MFT_FRT_IRQHandler        [WEAK]
+                EXPORT  MFT_IPC_IRQHandler        [WEAK]
+                EXPORT  MFT_OPC_IRQHandler        [WEAK]
+                EXPORT  BT0_7_IRQHandler          [WEAK]
+                EXPORT  ETHER_MAC0_IRQHandler     [WEAK]
+                EXPORT  ETHER_MAC1_IRQHandler     [WEAK]
+                EXPORT  USB0F_Handler             [WEAK]
+                EXPORT  USB0_Handler              [WEAK]
+                EXPORT  USB1F_Handler             [WEAK]
+                EXPORT  USB1_Handler              [WEAK]
+                EXPORT  DMAC0_Handler             [WEAK]
+                EXPORT  DMAC1_Handler             [WEAK]
+                EXPORT  DMAC2_Handler             [WEAK]
+                EXPORT  DMAC3_Handler             [WEAK]
+                EXPORT  DMAC4_Handler             [WEAK]
+                EXPORT  DMAC5_Handler             [WEAK]
+                EXPORT  DMAC6_Handler             [WEAK]
+                EXPORT  DMAC7_Handler             [WEAK]
+                EXPORT  BT8_15_IRQHandler         [WEAK]
+                EXPORT  DummyHandler              [WEAK]
+
+CSV_Handler
+SWDT_Handler
+LVD_Handler
+MFT_WG_IRQHandler
+INT0_7_Handler
+INT8_31_Handler
+DT_Handler
+MFS0RX_IRQHandler
+MFS0TX_IRQHandler
+MFS1RX_IRQHandler
+MFS1TX_IRQHandler
+MFS2RX_IRQHandler
+MFS2TX_IRQHandler
+MFS3RX_IRQHandler
+MFS3TX_IRQHandler
+MFS4RX_IRQHandler
+MFS4TX_IRQHandler
+MFS5RX_IRQHandler
+MFS5TX_IRQHandler
+MFS6RX_IRQHandler
+MFS6TX_IRQHandler
+MFS7RX_IRQHandler
+MFS7TX_IRQHandler
+PPG_Handler
+TIM_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+ADC2_IRQHandler
+MFT_FRT_IRQHandler
+MFT_IPC_IRQHandler
+MFT_OPC_IRQHandler
+BT0_7_IRQHandler
+DMAC0_Handler
+DMAC1_Handler
+DMAC2_Handler
+DMAC3_Handler
+DMAC4_Handler
+DMAC5_Handler
+DMAC6_Handler
+DMAC7_Handler
+ETHER_MAC0_IRQHandler
+ETHER_MAC1_IRQHandler
+USB0F_Handler
+USB0_Handler
+USB1F_Handler
+USB1_Handler
+BT8_15_IRQHandler
+DummyHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c
new file mode 100644
index 0000000000..ef641de1ef
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c
@@ -0,0 +1,244 @@
+/*
+ ****************************************************************************
+**
+**  File        : startup_mb9bf61x.c
+**
+**  Abstract    : This file contains interrupt vector and startup code.
+**
+**  Functions   : Reset_Handler
+**
+**  Target      : Fujitsu FM3 microcontrollers
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+ ****************************************************************************
+*/
+
+/**
+**===========================================================================
+**  Revisions
+**===========================================================================
+**       Date        Modification
+**       2011-08-18  First issue.
+**===========================================================================
+*/
+
+/**
+**===========================================================================
+**  External declarations
+**===========================================================================
+*/
+extern unsigned long _sdata, _edata, _sidata, _sbss, _ebss, _isr_vector;
+extern unsigned long _estack;
+extern void __libc_init_array();
+extern void SystemInit();
+extern void main();
+
+/**
+**===========================================================================
+**  Default interrupt handler
+**===========================================================================
+*/
+void Default_Handler()
+{
+	/* Hang here */
+	while(1)
+	{
+	}
+}
+
+/**
+**===========================================================================
+**  Reset handler
+**===========================================================================
+*/
+__attribute__((naked)) void Reset_Handler()
+{
+	/* Data and BSS variables */
+	unsigned long *srcdata, *dstdata, *sbss;
+
+	/* Set up the stack pointer */
+	asm("ldr sp,=_estack\n\t");
+
+    /* Set up vector table offset register */
+	dstdata = (unsigned long *)0xe000ed08;
+	*dstdata = (unsigned long)&_isr_vector;
+
+	srcdata = &_sidata;
+	dstdata = &_sdata;
+	sbss = &_sbss;
+
+	/* Copy data */
+	while(dstdata != &_edata)
+	{
+		*(dstdata++) = *(srcdata++);
+	}
+
+	/* Clear BSS */
+	while(sbss != &_ebss)
+	{
+		*(sbss++) = '\0';
+	}
+
+	/* Run static constructors */
+	//__libc_init_array();
+
+	/* Call the clock system initialization function.*/
+	SystemInit();
+
+	/* Jump to main */
+	main();
+
+	/* In case main returns, use default handler */
+	Default_Handler();
+}
+
+/**
+**===========================================================================
+**  Weak definitions of handlers point to Default_Handler if not implemented
+**===========================================================================
+*/
+void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DebugMonitor_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
+
+void CSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SWDT_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void LVD_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_WG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void INT0_7_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void INT8_31_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DT_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS0RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS0TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS1RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS1TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS2RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS2TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS3RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS3TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS4RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS4TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS5RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS5TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS6RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS6TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS7RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS7TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PPG_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void TIM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_FRT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_IPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_OPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void BT0_7_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ETHER_MAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ETHER_MAC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void USB0F_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB0_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB1F_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB1_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC0_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC1_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC2_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC3_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC4_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC5_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC6_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC7_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void BT8_15_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+
+
+/**
+**===========================================================================
+**  Interrupt Vector Table
+**===========================================================================
+*/
+void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) = {
+		/* Processor exceptions */
+		(void (*)(void))&_estack, /* 0 - Stack pointer */
+		Reset_Handler,            /* 1 - Reset */
+		NMI_Handler,              /* 2 - NMI  */
+		HardFault_Handler,        /* 3 - Hard fault */
+		MemManage_Handler,        /* 4 - Memory management fault */
+		BusFault_Handler,         /* 5 - Bus fault */
+		UsageFault_Handler,       /* 6 - Usage fault */
+		0,                        /* 7 - Reserved */
+		0,                        /* 8 - Reserved */
+		0,                        /* 9 - Reserved */
+		0,                        /* 10 - Reserved */
+		SVC_Handler,              /* 11 - SVCall */
+		DebugMonitor_Handler,     /* 12 - Reserved for Debug */
+		0,                        /* 13 - Reserved */
+		PendSV_Handler,           /* 14 - PendSV */
+		SysTick_Handler,          /* 15 - Systick */
+
+		/* External Interrupts */
+		CSV_Handler,              /* 0: Clock Super Visor */
+		SWDT_Handler,             /* 1: Software Watchdog Timer */
+		LVD_Handler,              /* 2: Low Voltage Detector */
+		MFT_WG_IRQHandler,        /* 3: Wave Form Generator / DTIF */
+		INT0_7_Handler,           /* 4: External Interrupt Request ch.0 to ch.7 */
+		INT8_31_Handler,          /* 5: External Interrupt Request ch.8 to ch.31 */
+		DT_Handler,               /* 6: Dual Timer / Quad Decoder */
+		MFS0RX_IRQHandler,        /* 7: MultiFunction Serial ch.0 */
+		MFS0TX_IRQHandler,        /* 8: MultiFunction Serial ch.0 */
+		MFS1RX_IRQHandler,        /* 9: MultiFunction Serial ch.1 */
+		MFS1TX_IRQHandler,        /* 10: MultiFunction Serial ch.1 */
+		MFS2RX_IRQHandler,        /* 11: MultiFunction Serial ch.2 */
+		MFS2TX_IRQHandler,        /* 12: MultiFunction Serial ch.2 */
+		MFS3RX_IRQHandler,        /* 13: MultiFunction Serial ch.3 */
+		MFS3TX_IRQHandler,        /* 14: MultiFunction Serial ch.3 */
+		MFS4RX_IRQHandler,        /* 15: MultiFunction Serial ch.4 */
+		MFS4TX_IRQHandler,        /* 16: MultiFunction Serial ch.4 */
+		MFS5RX_IRQHandler,        /* 17: MultiFunction Serial ch.5 */
+		MFS5TX_IRQHandler,        /* 18: MultiFunction Serial ch.5 */
+		MFS6RX_IRQHandler,        /* 19: MultiFunction Serial ch.6 */
+		MFS6TX_IRQHandler,        /* 20: MultiFunction Serial ch.6 */
+		MFS7RX_IRQHandler,        /* 21: MultiFunction Serial ch.7 */
+		MFS7TX_IRQHandler,        /* 22: MultiFunction Serial ch.7 */
+		PPG_Handler,              /* 23: PPG */
+		TIM_IRQHandler,           /* 24: OSC / PLL / Watch Counter */
+		ADC0_IRQHandler,          /* 25: ADC0 */
+		ADC1_IRQHandler,          /* 26: ADC1 */
+		ADC2_IRQHandler,          /* 27: ADC2 */
+		MFT_FRT_IRQHandler,       /* 28: Free-run Timer */
+		MFT_IPC_IRQHandler,       /* 29: Input Capture */
+		MFT_OPC_IRQHandler,       /* 30: Output Compare */
+		BT0_7_IRQHandler,         /* 31: Base Timer ch.0 to ch.7 */
+		ETHER_MAC0_IRQHandler,    /* 32: Ethernet MAC ch.0 */
+		ETHER_MAC1_IRQHandler,    /* 33: Ethernet MAC ch.1 */
+		USB0F_Handler,            /* 34: USB0 Function */
+		USB0_Handler,             /* 35: USB0 Function / USB0 HOST */
+		USB1F_Handler,            /* 36: USB1 Function */
+		USB1_Handler,             /* 37: USB1 Function / USB1 HOST */
+		DMAC0_Handler,            /* 38: DMAC ch.0 */
+		DMAC1_Handler,            /* 39: DMAC ch.1 */
+		DMAC2_Handler,            /* 40: DMAC ch.2 */
+		DMAC3_Handler,            /* 41: DMAC ch.3 */
+		DMAC4_Handler,            /* 42: DMAC ch.4 */
+		DMAC5_Handler,            /* 43: DMAC ch.5 */
+		DMAC6_Handler,            /* 44: DMAC ch.6 */
+		DMAC7_Handler,            /* 45: DMAC ch.7 */
+		BT8_15_IRQHandler,        /* 46: Base Timer ch.8 to ch.15 */
+		Default_Handler           /* 47: Reserved */
+};
diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S
new file mode 100644
index 0000000000..7bc1acf0cd
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S
@@ -0,0 +1,417 @@
+;/************************************************************************/
+;/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+;/*                                                                      */
+;/* The following software deliverable is intended for and must only be  */
+;/* used for reference and in an evaluation laboratory environment.      */
+;/* It is provided on an as-is basis without charge and is subject to    */
+;/* alterations.                                                         */
+;/* It is the user's obligation to fully test the software in its        */
+;/* environment and to ensure proper functionality, qualification and    */
+;/* compliance with component specifications.                            */
+;/*                                                                      */
+;/* In the event the software deliverable includes the use of open       */
+;/* source components, the provisions of the governing open source       */
+;/* license agreement shall apply with respect to such software          */
+;/* deliverable.                                                         */
+;/* FSEU does not warrant that the deliverables do not infringe any      */
+;/* third party intellectual property right (IPR). In the event that     */
+;/* the deliverables infringe a third party IPR it is the sole           */
+;/* responsibility of the customer to obtain necessary licenses to       */
+;/* continue the usage of the deliverable.                               */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not       */
+;/* limited to, warranties of merchantability and fitness for a          */
+;/* particular purpose for which the deliverable is not designated.      */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */
+;/* is restricted to intentional misconduct and gross negligence.        */
+;/* FSEU is not liable for consequential damages.                        */
+;/*                                                                      */
+;/* (V1.5)                                                               */
+;/************************************************************************/
+;/*  Startup for IAR                                                     */
+;/*  Version     V1.00                                                   */
+;/*  Date        2011-07-25                                              */
+;/*  Target-mcu  MB9B610                                                 */
+;/************************************************************************/
+
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)               ; Top of Stack
+		        DCD     Reset_Handler             ; Reset
+                DCD     NMI_Handler               ; NMI
+                DCD     HardFault_Handler         ; Hard Fault
+                DCD     MemManage_Handler         ; MPU Fault
+                DCD     BusFault_Handler          ; Bus Fault
+                DCD     UsageFault_Handler        ; Usage Fault
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall
+                DCD     DebugMon_Handler          ; Debug Monitor
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV
+                DCD     SysTick_Handler           ; SysTick
+
+                DCD     CSV_Handler               ; 0: Clock Super Visor
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer
+                DCD     LVD_Handler               ; 2: Low Voltage Detector
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7
+                DCD     INT8_31_Handler           ; 5: External Interrupt Request ch.8 to ch.31
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7
+                DCD     PPG_Handler               ; 23: PPG
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter
+                DCD     ADC0_IRQHandler           ; 25: ADC0
+                DCD     ADC1_IRQHandler           ; 26: ADC1
+                DCD     ADC2_IRQHandler           ; 27: ADC2
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare
+                DCD     BT0_7_IRQHandler          ; 31: Base Timer ch.0 to ch.7
+                DCD     ETHER_MAC0_IRQHandler     ; 32: Ethernet MAC ch.0
+                DCD     ETHER_MAC1_IRQHandler     ; 33: Ethernet MAC ch.1
+                DCD     USB0F_Handler             ; 34: USB0 Function
+                DCD     USB0_Handler              ; 35: USB0 Function / USB0 HOST
+                DCD     USB1F_Handler             ; 36: USB1 Function
+                DCD     USB1_Handler              ; 37: USB1 Function / USB1 HOST
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7
+                DCD     BT8_15_IRQHandler         ; 46: Base Timer ch.8 to ch.15
+                DCD     DummyHandler              ; 47: Reserved
+
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK MemManage_Handler
+                SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER(1)
+SVC_Handler
+                B       SVC_Handler
+
+                PUBWEAK DebugMon_Handler
+                SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+                B       DebugMon_Handler
+
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+                B       PendSV_Handler
+
+                PUBWEAK SysTick_Handler
+                SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+                B       SysTick_Handler
+
+
+
+                PUBWEAK CSV_Handler
+                SECTION .text:CODE:REORDER(1)
+CSV_Handler
+                B       CSV_Handler
+
+                PUBWEAK SWDT_Handler
+                SECTION .text:CODE:REORDER(1)
+SWDT_Handler
+                B       SWDT_Handler
+
+                PUBWEAK LVD_Handler
+                SECTION .text:CODE:REORDER(1)
+LVD_Handler
+                B       LVD_Handler
+
+                PUBWEAK MFT_WG_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_WG_IRQHandler
+                B       MFT_WG_IRQHandler
+                
+                PUBWEAK INT0_7_Handler
+                SECTION .text:CODE:REORDER(1)
+INT0_7_Handler
+                B       INT0_7_Handler
+
+                PUBWEAK INT8_31_Handler
+                SECTION .text:CODE:REORDER(1)
+INT8_31_Handler
+                B       INT8_31_Handler
+                
+                PUBWEAK DT_Handler
+                SECTION .text:CODE:REORDER(1)
+DT_Handler
+                B       DT_Handler
+
+                PUBWEAK MFS0RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS0RX_IRQHandler
+                B       MFS0RX_IRQHandler
+
+                PUBWEAK MFS0TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS0TX_IRQHandler
+                B       MFS0TX_IRQHandler
+
+                PUBWEAK MFS1RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS1RX_IRQHandler
+                B       MFS1RX_IRQHandler
+
+                PUBWEAK MFS1TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS1TX_IRQHandler
+                B       MFS1TX_IRQHandler
+
+                PUBWEAK MFS2RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS2RX_IRQHandler
+                B       MFS2RX_IRQHandler
+
+                PUBWEAK MFS2TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS2TX_IRQHandler
+                B       MFS2TX_IRQHandler
+
+                PUBWEAK MFS3RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS3RX_IRQHandler
+                B       MFS3RX_IRQHandler
+
+                PUBWEAK MFS3TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS3TX_IRQHandler
+                B       MFS3TX_IRQHandler
+
+                PUBWEAK MFS4RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS4RX_IRQHandler
+                B       MFS4RX_IRQHandler
+
+                PUBWEAK MFS4TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS4TX_IRQHandler
+                B       MFS4TX_IRQHandler
+
+                PUBWEAK MFS5RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS5RX_IRQHandler
+                B       MFS5RX_IRQHandler
+
+                PUBWEAK MFS5TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS5TX_IRQHandler
+                B       MFS5TX_IRQHandler
+
+                PUBWEAK MFS6RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS6RX_IRQHandler
+                B       MFS6RX_IRQHandler
+
+                PUBWEAK MFS6TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS6TX_IRQHandler
+                B       MFS6TX_IRQHandler
+
+                PUBWEAK MFS7RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS7RX_IRQHandler
+                B       MFS7RX_IRQHandler
+
+                PUBWEAK MFS7TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS7TX_IRQHandler
+                B       MFS7TX_IRQHandler
+
+                PUBWEAK PPG_Handler
+                SECTION .text:CODE:REORDER(1)
+PPG_Handler
+                B       PPG_Handler
+
+                PUBWEAK TIM_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+TIM_IRQHandler
+                B       TIM_IRQHandler
+
+                PUBWEAK ADC0_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC0_IRQHandler
+                B       ADC0_IRQHandler
+
+                PUBWEAK ADC1_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+                B       ADC1_IRQHandler
+
+                PUBWEAK ADC2_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC2_IRQHandler
+                B       ADC2_IRQHandler
+
+                PUBWEAK MFT_FRT_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_FRT_IRQHandler
+                B       MFT_FRT_IRQHandler
+
+                PUBWEAK MFT_IPC_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_IPC_IRQHandler
+                B       MFT_IPC_IRQHandler
+
+                PUBWEAK MFT_OPC_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_OPC_IRQHandler
+                B       MFT_OPC_IRQHandler
+
+                PUBWEAK BT0_7_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+BT0_7_IRQHandler
+                B       BT0_7_IRQHandler
+
+                PUBWEAK ETHER_MAC0_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ETHER_MAC0_IRQHandler
+                B       ETHER_MAC0_IRQHandler
+
+                PUBWEAK ETHER_MAC1_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ETHER_MAC1_IRQHandler
+                B       ETHER_MAC1_IRQHandler
+
+                PUBWEAK USB0F_Handler
+                SECTION .text:CODE:REORDER(1)
+USB0F_Handler
+                B       USB0F_Handler
+
+                PUBWEAK USB0_Handler
+                SECTION .text:CODE:REORDER(1)
+USB0_Handler
+                B       USB0_Handler
+
+                PUBWEAK USB1F_Handler
+                SECTION .text:CODE:REORDER(1)
+USB1F_Handler
+                B       USB1F_Handler
+
+                PUBWEAK USB1_Handler
+                SECTION .text:CODE:REORDER(1)
+USB1_Handler
+                B       USB1_Handler
+
+                PUBWEAK DMAC0_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC0_Handler
+                B       DMAC0_Handler
+
+
+                PUBWEAK DMAC1_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC1_Handler
+                B       DMAC1_Handler
+
+                PUBWEAK DMAC2_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC2_Handler
+                B       DMAC2_Handler
+
+                PUBWEAK DMAC3_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC3_Handler
+                B       DMAC3_Handler
+
+                PUBWEAK DMAC4_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC4_Handler
+                B       DMAC4_Handler
+
+                PUBWEAK DMAC5_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC5_Handler
+                B       DMAC5_Handler
+
+                PUBWEAK DMAC6_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC6_Handler
+                B       DMAC6_Handler
+
+                PUBWEAK DMAC7_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC7_Handler
+                B       DMAC7_Handler
+
+                PUBWEAK BT8_15_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+BT8_15_IRQHandler
+                B       BT8_15_IRQHandler
+
+                PUBWEAK DummyHandler
+                SECTION .text:CODE:REORDER(1)
+DummyHandler
+                B       DummyHandler
+
+                END
diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c
new file mode 100644
index 0000000000..a039f02431
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c
@@ -0,0 +1,206 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+
+#include "board.h"
+
+/** \file system_mb9bf61x.c
+ **
+ ** FM3 system initialization functions
+ ** All adjustments can be done in belonging header file.
+ **
+ ** History:
+ ** 2011-07-07 V1.0 MWi original version
+ ******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = __HCLK;
+
+/**
+ ******************************************************************************
+ ** \brief  Update the System Core Clock with current core Clock retrieved from
+ ** cpu registers.
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemCoreClockUpdate (void) {
+  uint32_t masterClk;
+  uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
+
+  switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
+    case 0:                                 /* internal High-speed Cr osc.    */
+      masterClk = __CLKHC;
+      break;
+
+    case 1:                                 /* external main osc.             */
+      masterClk = __CLKMO;
+      break;
+
+    case 2:                                 /* PLL clock                      */
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violation:
+  //   "Unordered accesses to a volatile location"
+      u32RegisterRead = (__CLKMO  * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
+      masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
+      break;
+
+    case 4:                                 /* internal Low-speed CR osc.     */
+      masterClk = __CLKLC;
+      break;
+
+    case 5:                                 /* external Sub osc.              */
+      masterClk = __CLKSO;
+      break;
+
+    default:
+      masterClk = 0Ul;
+      break;
+  }
+
+  switch (FM3_CRG->BSC_PSR & 0x07) {
+    case 0:
+      SystemCoreClock = masterClk;
+      break;
+
+    case 1:
+      SystemCoreClock = masterClk / 2;
+      break;
+
+    case 2:
+      SystemCoreClock = masterClk / 3;
+      break;
+
+    case 3:
+      SystemCoreClock = masterClk / 4;
+      break;
+
+    case 4:
+      SystemCoreClock = masterClk / 6;
+      break;
+
+    case 5:
+      SystemCoreClock = masterClk /8;
+      break;
+
+    case 6:
+      SystemCoreClock = masterClk /16;
+      break;
+
+    default:
+      SystemCoreClock = 0Ul;
+      break;
+  }
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief  Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemInit (void) {
+
+  static uint32_t u32IoRegisterRead;  // Workaround variable for MISRA C rule conformance
+
+#if (HWWD_DISABLE)                                 /* HW Watchdog Disable */
+  FM3_HWWDT->WDG_LCK = 0x1ACCE551;                 /* HW Watchdog Unlock */
+  FM3_HWWDT->WDG_LCK = 0xE5331AAE;
+  FM3_HWWDT->WDG_CTL = 0;                          /* HW Watchdog stop */
+#endif
+
+#if (CLOCK_SETUP)                                   /* Clock Setup */
+  FM3_CRG->BSC_PSR   = BSC_PSR_Val;                /* set System Clock presacaler */
+  FM3_CRG->APBC0_PSR = APBC0_PSR_Val;              /* set APB0 presacaler */
+  FM3_CRG->APBC1_PSR = APBC1_PSR_Val;              /* set APB1 presacaler */
+  FM3_CRG->APBC2_PSR = APBC2_PSR_Val;              /* set APB2 presacaler */
+  FM3_CRG->SWC_PSR   = SWC_PSR_Val | (1UL << 7);   /* set SW Watchdog presacaler */
+  FM3_CRG->TTC_PSR   = TTC_PSR_Val;                /* set Trace Clock presacaler */
+
+  FM3_CRG->CSW_TMR   = CSW_TMR_Val;                /* set oscillation stabilization wait time */
+
+  if (SCM_CTL_Val & (1UL << 1)) {                    /* Main clock oscillator enabled ? */
+    FM3_CRG->SCM_CTL |= (1UL << 1);                /* enable main oscillator */
+    while (!(FM3_CRG->SCM_STR & (1UL << 1)));      /* wait for Main clock oscillation stable */
+  }
+
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */
+    FM3_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */
+    while (!(FM3_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */
+  }
+
+  FM3_CRG->PSW_TMR   = PSW_TMR_Val;                /* set PLL stabilization wait time */
+  FM3_CRG->PLL_CTL1  = PLL_CTL1_Val;               /* set PLLM and PLLK */
+  FM3_CRG->PLL_CTL2  = PLL_CTL2_Val;               /* set PLLN          */
+
+  if (SCM_CTL_Val & (1UL << 4)) {                    /* PLL enabled ? */
+    FM3_CRG->SCM_CTL  |= (1UL << 4);               /* enable PLL */
+    while (!(FM3_CRG->SCM_STR & (1UL << 4)));      /* wait for PLL stable */
+  }
+
+  FM3_CRG->SCM_CTL  |= (SCM_CTL_Val & 0xE0);       /* Set Master Clock switch */
+
+  {
+      volatile unsigned int i;
+      for(i=0;i<200000;i++);
+  }
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violations:
+  //   "Unordered reads and writes to or from same location" and
+  //   "Unordered accesses to a volatile location"
+  do
+  {
+    u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
+  }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
+#endif // (CLOCK_SETUP)
+
+#if (CR_TRIM_SETUP)
+  /* CR Trimming Data  */
+  if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
+  {
+    /* UnLock (MCR_FTRM) */
+    FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
+    /* Set MCR_FTRM */
+    FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
+    /* Lock (MCR_FTRM) */
+    FM3_CRTRIM->MCR_RLR = 0x00000000;
+  }
+#endif // (CR_TRIM_SETUP)
+}
+
+
+
diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h
new file mode 100644
index 0000000000..819f3646e9
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h
@@ -0,0 +1,678 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/** \file system_mb9bf61x.h
+ **
+ ** Headerfile for FM3 system parameters
+ **
+ ** User clock definitions can be done for the following clock settings:
+ ** - CLOCK_SETUP : Execute the clock settings form the settings below in
+ **                 SystemInit()
+ ** - __CLKMO : External clock frequency for main oscillion
+ ** - __CLKSO : External clock frequency for sub oscillion
+ ** - SCM_CTL : System Clock Mode Control Register
+ ** - BSC_PSR : Base Clock Prescaler Register
+ ** - APBC0_PSR : APB0 Prescaler Register
+ ** - APBC1_PSR : APB1 Prescaler Register
+ ** - APBC2_PSR : APB2 Prescaler Register
+ ** - SWC_PSR : Software Watchdog Clock Prescaler Register
+ ** - TTC_PSR : Trace Clock Prescaler Register
+ ** - CSW_TMR : Clock Stabilization Wait Time Register
+ ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register
+ ** - PLL_CTL1 : PLL Control Register 1
+ ** - PLL_CTL2 : PLL Control Register 2
+ **
+ ** The register settings are check for correct values of reserved bits.
+ ** Otherwise a preprocessor error is output and stops the build process.
+ ** Furthermore the 'master clock' is retrieved from the register settings
+ ** and the system clock (HCLK) is calculated from the Base Clock Prescaler
+ ** Register (BSC_PSR). This value is used for the global CMSIS variable
+ ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is
+ ** is checked. Note that not all possible wrong setting are checked! The
+ ** user has to take care to fulfill the settings stated in the according
+ ** device's data sheet!
+ **
+ ** User definition for Hardware Watchdog:
+ ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()
+ **
+ ** User definition for CR Trimming:
+ ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()
+ **
+ ** History:
+ ** 2011-05-16 V1.0 MWi original version
+ *****************************************************************************/
+
+#ifndef _SYSTEM_MB9BF61X_H_
+#define _SYSTEM_MB9BF61X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/******************************************************************************/
+/* Include files                                                              */
+/******************************************************************************/
+   
+#include <stdint.h>
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('define')                             */
+/******************************************************************************/
+   
+/******************************************************************************/
+/*                                                                            */
+/*                      START OF USER SETTINGS HERE                           */
+/*                      ===========================                           */   
+/*                                                                            */
+/*                 All lines with '<<<' can be set by user.                   */
+/*                                                                            */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Clock Setup Enable
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = No clock setup done by system_mb9xfxxx.c
+ ** - 1 = Clock setup done by system_mb9xfxxx.c
+ ******************************************************************************/ 
+#define CLOCK_SETUP               1   // <<< Define clock setup here
+
+/**
+ ******************************************************************************
+ ** \brief External Main Clock Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/    
+#define __CLKMO        ( 4000000UL)   // <<< External   4MHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief External Sub Clock Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/  
+#define __CLKSO        (   32768UL)   // <<<  External  32KHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief System Clock Mode Control Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** SCM_CTL
+ **
+ ** Bit#7-5 : RCS[2:0]
+ ** - 0 = Internal high-speed CR oscillation (default)
+ ** - 1 = Main oscillation clock
+ ** - 2 = PLL oscillation clock
+ ** - 3 = (not allowed)
+ ** - 4 = Internal low-speed CR oscillation
+ ** - 5 = Sub clock oscillation
+ ** - 6 = (not allowed)
+ ** - 7 = (not allowed)
+ **
+ ** Bit#4 : PLLE
+ ** - 0 = Disable PLL (default)
+ ** - 1 = Enable PLL
+ **
+ ** Bit#3 : SOSCE
+ ** - 0 = Disable sub oscillation (default)
+ ** - 1 = Enable sub oscillation
+ **
+ ** Bit#2 : (reserved)
+ **
+ ** Bit#1 : MOSCE
+ ** - 0 = Disable main oscillation (default)
+ ** - 1 = Enable main oscillation  
+ **
+ ** Bit#0 : (reserved)  
+ ******************************************************************************/ 
+#define SCM_CTL_Val           0x00000052    // <<< Define SCM_CTL here
+
+/**
+ ******************************************************************************
+ ** \brief Base Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** BSC_PSR
+ **
+ ** Bit#7-3 : (reserved)
+ **
+ ** Bit#2-0 : BSR[2:0]
+ ** - 0 = HCLK = Master Clock
+ ** - 1 = HCLK = Master Clock / 2
+ ** - 2 = HCLK = Master Clock / 3
+ ** - 3 = HCLK = Master Clock / 4
+ ** - 4 = HCLK = Master Clock / 6
+ ** - 5 = HCLK = Master Clock / 8
+ ** - 6 = HCLK = Master Clock / 16
+ ** - 7 = (reserved)
+ ******************************************************************************/    
+#define BSC_PSR_Val           0x00000000    // <<< Define BSC_PSR here
+ 
+/**
+ ******************************************************************************
+ ** \brief APB0 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC0_PSR
+ **
+ ** Bit#7-2 : (reserved)
+ **
+ ** Bit#1-0 : BSR[2:0] 
+ ** - 0 = PCLK0 = HCLK
+ ** - 1 = PCLK0 = HCLK / 2
+ ** - 2 = PCLK0 = HCLK / 4
+ ** - 3 = PCLK0 = HCLK / 8
+ ******************************************************************************/    
+#define APBC0_PSR_Val         0x00000001     // <<< Define APBC0_PSR here
+   
+/**
+ ******************************************************************************
+ ** \brief APB1 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC1_PSR
+ **
+ ** Bit#7 : APBC1EN
+ ** - 0 = Disable PCLK1 output
+ ** - 1 = Enables PCLK1 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ **
+ ** Bit#4 : APBC1RST
+ ** - 0 = APB1 bus reset, inactive (default)
+ ** - 1 = APB1 bus reset, active  
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC1[2:0]
+ ** - 0 = PCLK1 = HCLK
+ ** - 1 = PCLK1 = HCLK / 2
+ ** - 2 = PCLK1 = HCLK / 4
+ ** - 3 = PCLK1 = HCLK / 8
+ ******************************************************************************/     
+#define APBC1_PSR_Val         0x00000081    // <<< Define APBC1_PSR here
+   
+/**
+ ******************************************************************************
+ ** \brief APB2 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC2_PSR
+ **
+ ** Bit#7 : APBC2EN
+ ** - 0 = Disable PCLK2 output
+ ** - 1 = Enables PCLK2 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ ** 
+ ** Bit#4 : APBC2RST
+ ** - 0 = APB2 bus reset, inactive (default)
+ ** - 1 = APB2 bus reset, active  
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC2[1:0]
+ ** - 0 = PCLK2 = HCLK
+ ** - 1 = PCLK2 = HCLK / 2
+ ** - 2 = PCLK2 = HCLK / 4
+ ** - 3 = PCLK2 = HCLK / 8
+ ******************************************************************************/    
+#define APBC2_PSR_Val         0x00000081    // <<< Define APBC2_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Software Watchdog Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** SWC_PSR
+ **
+ ** Bit#7 : TESTB
+ ** - 0 = (not allowed)
+ ** - 1 = (always write "1" to this bit)
+ **
+ ** Bit#6-2 : (reserved)
+ **
+ ** Bit#1-0 : SWDS[2:0]
+ ** - 0 = SWDGOGCLK = PCLK0
+ ** - 1 = SWDGOGCLK = PCLK0 / 2
+ ** - 2 = SWDGOGCLK = PCLK0 / 4
+ ** - 3 = SWDGOGCLK = PCLK0 / 8
+ ******************************************************************************/  
+#define SWC_PSR_Val           0x00000003    // <<< Define SWC_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Trace Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** TTC_PSR
+ **
+ ** Bit#7-1 : (reserved)
+ **
+ ** Bit#0 : TTC
+ ** - 0 = TPIUCLK = HCLK
+ ** - 1 = TPIUCLK = HCLK / 2
+ ******************************************************************************/  
+#define TTC_PSR_Val           0x00000000    // <<< Define TTC_PSR here
+ 
+/**
+ ******************************************************************************
+ ** \brief Clock Stabilization Wait Time Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** CSW_TMR
+ **
+ ** Bit#7 : (reserved)
+ **
+ ** Bit#6-4 : SOWT[2:0]
+ ** - 0 = ~10.3 ms (default)
+ ** - 1 = ~20.5 ms
+ ** - 2 = ~41 ms
+ ** - 3 = ~82 ms
+ ** - 4 = ~164 ms
+ ** - 5 = ~327 ms
+ ** - 6 = ~655 ms
+ ** - 7 = ~1.31 s 
+ **
+ ** Bit#3-0 : MOWT[3:0]
+ ** - 0 = ~500 ns (default)
+ ** - 1 = ~8 us
+ ** - 2 = ~16 us
+ ** - 3 = ~32 us
+ ** - 4 = ~64 us
+ ** - 5 = ~128 us
+ ** - 6 = ~256 us
+ ** - 7 = ~512 us
+ ** - 8 = ~1.0 ms
+ ** - 9 = ~2.0 ms
+ ** - 10 = ~4.0 ms
+ ** - 11 = ~8.0 ms
+ ** - 12 = ~33.0 ms
+ ** - 13 = ~131 ms
+ ** - 14 = ~524 ms
+ ** - 15 = ~2.0 s
+ ******************************************************************************/     
+#define CSW_TMR_Val           0x0000005C    // <<< Define CSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Clock Stabilization Wait Time Setup Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PSW_TMR
+ **
+ ** Bit#7-5 : (reserved)
+ **
+ ** Bit#4 : PINC
+ ** - 0 = Selects CLKMO (main oscillation) (default)
+ ** - 1 = (setting diabled)
+ **
+ ** Bit#3 : (reserved)
+ **
+ ** Bit#2-0 : POWT[2:0]
+ ** - 0 = ~128 us (default) 
+ ** - 1 = ~256 us
+ ** - 2 = ~512 us
+ ** - 3 = ~1.02 ms
+ ** - 4 = ~2.05 ms
+ ** - 5 = ~4.10 ms
+ ** - 6 = ~8.20 ms
+ ** - 7 = ~16.40 ms
+ ******************************************************************************/    
+#define PSW_TMR_Val           0x00000000    // <<< Define PSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 1 value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PLL_CTL1
+ **
+ ** Bit#7-4 : PLLK[3:0]
+ ** - 0 = Division(PLLK) = 1/1 (default)
+ ** - 1 = Division(PLLK) = 1/2
+ ** - 2 = Division(PLLK) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLK) = 1/16
+ **
+ ** Bit#3-0 : PLLM[3:0]
+ ** - 0 = Division(PLLM) = 1/1 (default)
+ ** - 1 = Division(PLLM) = 1/2
+ ** - 2 = Division(PLLM) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLM) = 1/16
+ ******************************************************************************/    
+#define PLL_CTL1_Val          0x00000001    // <<< Define PLL_CTL1 here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 2 value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PLL_CTL2
+ **
+ ** Bit#7-6 : (reserved)
+ **
+ ** Bit#5-0 : PLLN[5:0]
+ ** - 0 = Division(PLLN) = 1/1 (default)
+ ** - 1 = Division(PLLN) = 1/2
+ ** - 2 = Division(PLLN) = 1/3
+ ** - . . .
+ ** - 63 = Division(PLLN) = 1/64
+ ******************************************************************************/    
+#define PLL_CTL2_Val          0x00000023    // <<< Define PLL_CTL2 here
+   
+/**
+ ******************************************************************************
+ ** \brief Hardware Watchdog disable definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = Hardware Watchdog enable
+ ** - 1 = Hardware Watchdog disable
+ ******************************************************************************/  
+#define HWWD_DISABLE          1   // <<< Define HW Watach dog enable here
+
+/**
+ ******************************************************************************
+ ** \brief Trimming CR
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = CR is not trimmed at startup
+ ** - 1 = CR is trimmed at startup
+ ******************************************************************************/  
+#define CR_TRIM_SETUP         1   // <<< Define CR trimming at startup enable here
+
+   
+/******************************************************************************/
+/*                                                                            */
+/*                         END OF USER SETTINGS HERE                          */
+/*                         =========================                          */ 
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Device dependent System Clock absolute maximum ranges                      */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/    
+#define __CLKHC        ( 4000000UL)         /* Internal   4MHz CR Oscillator  */
+   
+/**
+ ******************************************************************************
+ ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKLC        (  100000UL)         /* Internal 100KHz CR Oscillator  */  
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKMOMIN    (  4000000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Maximum Main Clock frequency using external clock
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKMOMAX    ( 50000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Sub Clock frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKSOMIN    (    32000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Maximum Sub Clock frequency using external clock
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKSOMAX    (   100000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL input frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKINMIN (  4000000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL input frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKINMAX ( 16000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL oscillation frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKMIN   (200000000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL oscillation  frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKMAX   (300000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum System Clock frequency (HCLK)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __HCLKMAX     (144000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking range (clock settings)
+ ******************************************************************************/ 
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+   
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking bits with mask (clock settings)
+ ******************************************************************************/ 
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+
+/******************************************************************************/
+/* Check register settings                                                    */
+/******************************************************************************/
+#if (CHECK_RSVD((SCM_CTL_Val),    ~0x000000FA))
+   #error "SCM_CTL: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
+   #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
+#endif
+
+#if (CHECK_RSVD((CSW_TMR_Val),    ~0x0000007F))
+   #error "CSW_TMR: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0x10))       /* if PLL is used */
+  #if (CHECK_RSVD((PSW_TMR_val),  ~0x00000007))
+     #error "PSW_TMR: Invalid values of reserved bits!"
+  #endif
+
+  #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
+     #error "PLL_CTL1: Invalid values of reserved bits!"
+  #endif
+
+  #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))
+    #error "PLL_CTL2: Invalid values of reserved bits!"
+  #endif
+#endif
+
+#if (CHECK_RSVD((BSC_PSR_Val),    ~0x00000007))
+  #error "BSC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC0_PSR_Val),  ~0x00000003))
+  #error "APBC0_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC1_PSR_Val),  ~0x00000083))
+  #error "APBC1_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC2_PSR_Val),  ~0x00000083))
+  #error "APBC2_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((SWC_PSR_Val),    ~0x00000003))
+  #error "SWC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((TTC_PSR_Val),    ~0x00000001))
+  #error "TTC_PSR: Invalid values of reserved bits!"
+#endif
+
+/******************************************************************************/
+/* Define clocks with checking settings                                       */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL K factor from settings
+ ******************************************************************************/
+#define __PLLK         (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL N factor from settings
+ ******************************************************************************/
+#define __PLLN         (((PLL_CTL2_Val     ) & 0x3F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL M factor from settings
+ ******************************************************************************/
+#define __PLLM         (((PLL_CTL1_Val     ) & 0x0F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL output frequency from settings
+ ******************************************************************************/
+#define __PLLCLK       ((__CLKMO  * __PLLN) / __PLLK)
+
+/******************************************************************************/
+/* Determine core clock frequency according to settings                       */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Define Master Clock from settings
+ ******************************************************************************/
+#if   (((SCM_CTL_Val >> 5) & 0x07) == 0)
+  #define __MASTERCLK     (__CLKHC)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
+  #define __MASTERCLK     (__CLKMO)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
+  #define __MASTERCLK     (__PLLCLK)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
+  #define __MASTERCLK     (__CLKLC)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
+  #define __MASTERCLK     (__CLKSO)
+#else
+  #define __MASTERCLK     (0UL)
+#endif
+
+/**
+ ******************************************************************************
+ ** \brief Define System Clock Frequency (Core Clock) from settings
+ ******************************************************************************/
+#if   ((BSC_PSR_Val & 0x07) == 0)
+  #define __HCLK         (__MASTERCLK / 1)
+#elif ((BSC_PSR_Val & 0x07) == 1)
+  #define __HCLK         (__MASTERCLK / 2)
+#elif ((BSC_PSR_Val & 0x07) == 2)
+  #define __HCLK         (__MASTERCLK / 3)
+#elif ((BSC_PSR_Val & 0x07) == 3)
+  #define __HCLK         (__MASTERCLK / 4)
+#elif ((BSC_PSR_Val & 0x07) == 4)
+  #define __HCLK         (__MASTERCLK / 6)
+#elif ((BSC_PSR_Val & 0x07) == 5)
+  #define __HCLK         (__MASTERCLK / 8)
+#elif ((BSC_PSR_Val & 0x07) == 6)
+  #define __HCLK         (__MASTERCLK /16)
+#else
+  #define __HCLK         (0UL)
+#endif
+
+/******************************************************************************/
+/* HCLK range check                                                           */
+/******************************************************************************/
+#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)
+  #error "Main Oscillator Clock (CLKMO) out of range!"
+#endif   
+
+#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)
+  #error "Sub Oscillator Clock (CLKMO) out of range!"
+#endif   
+
+#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)
+  #error "PLL input frequency out of range!"
+#endif  
+
+#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)
+  #error "PLL oscillation frequency out of range!"
+#endif  
+   
+#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)
+  #error "System Clock (HCLK) out of range!"
+#endif
+   
+/******************************************************************************/
+/* Global function prototypes ('extern', definition in C source)              */
+/******************************************************************************/
+
+extern uint32_t SystemCoreClock;          // System Clock Frequency (Core Clock)
+   
+extern void SystemInit (void);            // Initialize the system
+
+extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_MB9BF61X_H */
diff --git a/bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h b/bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..7a59b5923e
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h b/bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000000..8d7fac0f04
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*               user convenience.  For example, some can be given as
+*               arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+      16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+      32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+      64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+      128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+      256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+      512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+      1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+      2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+      4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+   };
+
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/arm_math.h b/bsp/mb9bf618s/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..65304c127d
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/arm_math.h
@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("push")         \
+     _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT \
+     _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm0.h b/bsp/mb9bf618s/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..ab31de0ee8
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cm0.h
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h b/bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..5cea74e9af
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm3.h b/bsp/mb9bf618s/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..122c9aa4a8
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm4.h b/bsp/mb9bf618s/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..d65016c714
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h b/bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000..83db95b5f1
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h b/bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000..0a18fafc30
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h b/bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000..d213f0eed7
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_sc000.h b/bsp/mb9bf618s/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..1a2a0f2e30
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_sc000.h
@@ -0,0 +1,813 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/Include/core_sc300.h b/bsp/mb9bf618s/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..cc34d6fc0e
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1598 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf618s/CMSIS/README.txt b/bsp/mb9bf618s/CMSIS/README.txt
new file mode 100644
index 0000000000..23717194f4
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/README.txt
@@ -0,0 +1,37 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2013 ARM Limited. All rights reserved.  
+* 
+* Date:        18 March 2013  
+* Revision:    V3.20 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.
diff --git a/bsp/mb9bf618s/CMSIS/SConscript b/bsp/mb9bf618s/CMSIS/SConscript
new file mode 100644
index 0000000000..64f6f21408
--- /dev/null
+++ b/bsp/mb9bf618s/CMSIS/SConscript
@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('DeviceSupport/fujitsu/mb9bf61x/*.c')
+
+CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport/fujitsu/mb9bf61x/']
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S']
+elif rtconfig.CROSS_TOOL == 'iar':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S']
+
+CPPDEFINES = [rtconfig.FM3_TYPE]
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/mb9bf618s/SConscript b/bsp/mb9bf618s/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/mb9bf618s/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/mb9bf618s/SConstruct b/bsp/mb9bf618s/SConstruct
new file mode 100644
index 0000000000..8c58439102
--- /dev/null
+++ b/bsp/mb9bf618s/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+	env.Replace(ARFLAGS = '')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/mb9bf618s/applications/SConscript b/bsp/mb9bf618s/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/mb9bf618s/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/mb9bf618s/applications/application.c b/bsp/mb9bf618s/applications/application.c
new file mode 100644
index 0000000000..ac377e6b53
--- /dev/null
+++ b/bsp/mb9bf618s/applications/application.c
@@ -0,0 +1,58 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-24     Bernard      the first version
+ */
+
+/**
+ * @addtogroup FM3
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+void rt_init_thread_entry(void *parameter)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+#ifdef  RT_USING_FINSH
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif  /* RT_USING_FINSH */
+
+    /**< init led device */
+    {
+        extern void rt_led_hw_init(void);
+        rt_led_hw_init();
+    }
+
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry, RT_NULL,
+                           2048, 8, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/mb9bf618s/applications/startup.c b/bsp/mb9bf618s/applications/startup.c
new file mode 100644
index 0000000000..c95f4640fe
--- /dev/null
+++ b/bsp/mb9bf618s/applications/startup.c
@@ -0,0 +1,88 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup FM3
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
+#endif
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/mb9bf618s/drivers/SConscript b/bsp/mb9bf618s/drivers/SConscript
new file mode 100644
index 0000000000..5bbef48785
--- /dev/null
+++ b/bsp/mb9bf618s/drivers/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/mb9bf618s/drivers/board.c b/bsp/mb9bf618s/drivers/board.c
new file mode 100644
index 0000000000..53ec7e7a70
--- /dev/null
+++ b/bsp/mb9bf618s/drivers/board.c
@@ -0,0 +1,100 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include "serial.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+/**
+ * @addtogroup FM3
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This fucntion returns milliseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_millisecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_MS (1000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+ * This fucntion returns microseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_microsecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_US	(1000000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+* This function will initial FM3 Easy Kit board.
+ */
+void rt_hw_board_init(void)
+{
+    /* disable all analog input. */
+    FM3_GPIO->ADE = 0;
+
+    /* init systick */
+    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
+
+    /* initialize UART device */
+    rt_hw_serial_init();
+    /* set console as UART device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/
diff --git a/bsp/mb9bf618s/drivers/board.h b/bsp/mb9bf618s/drivers/board.h
new file mode 100644
index 0000000000..3e5887b8f1
--- /dev/null
+++ b/bsp/mb9bf618s/drivers/board.h
@@ -0,0 +1,50 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2011-03-04     lgnq         add board.h to FM3 bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#if   defined MB9B610S
+#   include <mb9b610s.h>
+#elif defined MB9B610T
+#   include <mb9b610t.h>
+#else
+#   warning "you must define CPU type. e.g: MB9B610S or MB9B610T"
+#   warning "define MB9B610S default"
+#   define MB9B610S /* default: MB9B610S */
+#   include <mb9b610s.h>
+#endif
+
+#include "serial.h"
+
+//Internal SRAM memory size[Kbytes] <8-64>
+//product  MB9BFx16S/T  MB9BFx17S/T  MB9BFx18S/T
+//FLASH  :    512           768          1024
+//SRAM0  :    32            48           64
+//SRAM1  :    32            48           64
+#define FM3_SRAM_SIZE         128
+#define FM3_SRAM_END          (0x1FFF0000 + FM3_SRAM_SIZE * 1024)
+
+/* RT_USING_UART */
+#define RT_USING_UART0
+//#define RT_USING_UART2
+//#define RT_USING_UART4
+#define RT_UART_RX_BUFFER_SIZE        64
+
+void rt_hw_board_init(void);
+rt_uint32_t rt_hw_tick_get_millisecond(void);
+rt_uint32_t rt_hw_tick_get_microsecond(void);
+
+#endif
diff --git a/bsp/mb9bf618s/drivers/led.c b/bsp/mb9bf618s/drivers/led.c
new file mode 100644
index 0000000000..15fe12b4f2
--- /dev/null
+++ b/bsp/mb9bf618s/drivers/led.c
@@ -0,0 +1,157 @@
+#include <rtthread.h>
+#include "board.h"
+
+#define RT_DEVICE_CTRL_RTC_GET_COUNT        0x81        /**< get count                                   */
+
+#define LED_NUM                             4
+struct fm3_gpio_ctrl
+{
+    uint32_t led_num;
+    volatile uint32_t * PDOR;
+    volatile uint32_t * PDIR;
+};
+
+struct fm3_led
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    struct fm3_gpio_ctrl fm3_gpio_ctrl[LED_NUM];
+};
+
+static struct fm3_led fm3_led;
+
+static rt_err_t rt_led_init (rt_device_t dev)
+{
+    uint32_t i;
+
+    /* led0 : P54 */
+    FM3_GPIO->PFR5 &= ~((1<<7) | (1<<6) | (1<<5) |(1<<4));  /* set P54 fuction is GPIO. */
+    FM3_GPIO->DDR5 |=  (1<<7) | (1<<6) | (1<<5) |(1<<4);    /* set P54 output. */
+
+    /* LED0 */
+    i = 0;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 4;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    /* LED1 */
+    i++;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 5;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    /* LED2 */
+    i++;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 6;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    /* LED3 */
+    i++;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 7;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                              rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nr = size;
+    rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm3_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nr; index++)
+    {
+        if(*fm3_led.fm3_gpio_ctrl[pos+index].PDIR & 1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num)
+        {
+            *value = 0;
+        }
+        else
+        {
+            *value = 1;
+        }
+        value++;
+    }
+    return index;
+}
+
+static rt_size_t rt_led_write (rt_device_t dev, rt_off_t pos,
+                               const void* buffer, rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nw = size;
+    const rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm3_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nw; index++)
+    {
+        if(*value++)
+        {
+            *fm3_led.fm3_gpio_ctrl[pos+index].PDOR &= ~(1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num);
+        }
+        else
+        {
+            *fm3_led.fm3_gpio_ctrl[pos+index].PDOR |= (1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num);
+        }
+    }
+    return index;
+}
+
+static rt_err_t rt_led_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev == &fm3_led.parent);
+
+    if(cmd == RT_DEVICE_CTRL_RTC_GET_COUNT)
+    {
+        rt_uint32_t * led_num = args;
+        *led_num = LED_NUM;
+    }
+    return RT_EOK;
+}
+
+void rt_led_hw_init(void)
+{
+    fm3_led.parent.type 		= RT_Device_Class_Char;
+    fm3_led.parent.rx_indicate  = RT_NULL;
+    fm3_led.parent.tx_complete  = RT_NULL;
+    fm3_led.parent.init 		= rt_led_init;
+    fm3_led.parent.open		    = rt_led_open;
+    fm3_led.parent.close		= rt_led_close;
+    fm3_led.parent.read         = rt_led_read;
+    fm3_led.parent.write 		= rt_led_write;
+    fm3_led.parent.control 	    = rt_led_control;
+    fm3_led.parent.user_data	= RT_NULL;
+
+    /* register a character device */
+    rt_device_register(&fm3_led.parent, "led", RT_DEVICE_FLAG_RDWR);
+    /* init led device */
+    rt_led_init(&fm3_led.parent);
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led(rt_uint32_t led, rt_uint32_t value)
+{
+    rt_uint8_t led_value = value;
+    rt_led_write(&fm3_led.parent, led, &led_value, 1);
+}
+FINSH_FUNCTION_EXPORT(led, e.g:led(0,100).)
+#endif
diff --git a/bsp/mb9bf618s/drivers/serial.c b/bsp/mb9bf618s/drivers/serial.c
new file mode 100644
index 0000000000..6d63daebb3
--- /dev/null
+++ b/bsp/mb9bf618s/drivers/serial.c
@@ -0,0 +1,437 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#include <rtthread.h>
+
+#include "serial.h"
+
+/**
+ * @addtogroup FM3 MB9B610
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+/**
+ * This function initializes serial
+ */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+    struct serial_device* uart = (struct serial_device*) dev->user_data;
+
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0,
+                      sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = uart->int_rx->save_index = 0;
+        }
+
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_memset(uart->int_tx->tx_buffer, 0,
+                      sizeof(uart->int_tx->tx_buffer));
+            uart->int_tx->write_index = uart->int_tx->save_index = 0;
+        }
+
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
+
+    return RT_EOK;
+}
+
+/* save a char to serial buffer */
+static void rt_serial_savechar(struct serial_device* uart, char ch)
+{
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+    uart->int_rx->save_index ++;
+    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+        uart->int_rx->save_index = 0;
+
+    /* if the next position is read index, discard this 'read char' */
+    if (uart->int_rx->save_index == uart->int_rx->read_index)
+    {
+        uart->int_rx->read_index ++;
+        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->read_index = 0;
+    }
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable interrupt */
+        UART_ENABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        UART_DISABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                                 rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        rt_base_t level;
+
+        /* interrupt mode Rx */
+        while (size)
+        {
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size --;
+
+                /* disable interrupt */
+                level = rt_hw_interrupt_disable();
+
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
+
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (uart->uart_device->SSR & SSR_RDRF)
+            {
+                *ptr = uart->uart_device->RDR & 0xff;
+                ptr ++;
+            }
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos,
+                                  const void* buffer, rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx */
+        while (uart->int_tx->save_index != uart->int_tx->write_index)
+        {
+            /* save on tx buffer */
+            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+            -- size;
+
+            /* move to next position */
+            uart->int_tx->save_index ++;
+
+            /* wrap save index */
+            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+                uart->int_tx->save_index = 0;
+        }
+
+        /* set error code */
+        if (size > 0)
+            err_code = -RT_EFULL;
+    }
+    else
+    {
+        /* polling mode */
+        while (size)
+        {
+            /*
+             * to be polite with serial console add a line feed
+             * to the carriage return character
+             */
+            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+            {
+                while (!(uart->uart_device->SSR & SSR_TDRE));
+                uart->uart_device->TDR = '\r';
+            }
+
+            while (!(uart->uart_device->SSR & SSR_TDRE));
+            uart->uart_device->TDR = (*ptr & 0x1FF);
+
+            ++ptr;
+            --size;
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
+
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/*
+ * serial register
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
+                               rt_uint32_t flag, struct serial_device *serial)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    device->type 		= RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init 		= rt_serial_init;
+    device->open		= rt_serial_open;
+    device->close		= rt_serial_close;
+    device->read 		= rt_serial_read;
+    device->write 		= rt_serial_write;
+    device->control 	= rt_serial_control;
+    device->user_data	= serial;
+
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+    struct serial_device* uart = (struct serial_device*) device->user_data;
+
+    /* interrupt mode receive */
+    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+    /* save on rx buffer */
+    while (uart->uart_device->SSR & SSR_RDRF)
+    {
+        rt_serial_savechar(uart, uart->uart_device->RDR & 0xff);
+    }
+
+    /* invoke callback */
+    if (device->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
+
+        /* get rx length */
+        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+                    uart->int_rx->save_index - uart->int_rx->read_index;
+
+        device->rx_indicate(device, rx_length);
+    }
+}
+
+#ifdef RT_USING_UART0
+/* UART0 device driver structure */
+#define UART0	FM3_MFS0_UART
+struct serial_int_rx uart0_int_rx;
+struct serial_device uart0 =
+{
+    UART0,
+    MFS0RX_IRQn,
+    MFS0TX_IRQn,
+    &uart0_int_rx,
+    RT_NULL
+};
+struct rt_device uart0_device;
+
+void MFS0RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart0_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /**< #ifdef RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+/* UART2 device driver structure */
+#define UART2	FM3_MFS2_UART
+struct serial_int_rx uart2_int_rx;
+struct serial_device uart2 =
+{
+    UART2,
+    MFS2RX_IRQn,
+    MFS2TX_IRQn,
+    &uart2_int_rx,
+    RT_NULL
+};
+struct rt_device uart2_device;
+
+void MFS2RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart2_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /**< #ifdef RT_USING_UART2 */
+
+#ifdef RT_USING_UART4
+/* UART4 device driver structure */
+#define UART4	FM3_MFS4_UART
+struct serial_int_rx uart4_int_rx;
+struct serial_device uart4 =
+{
+    (FM3_MFS03_UART_TypeDef*)UART4,
+    MFS4RX_IRQn,
+    MFS4TX_IRQn,
+    &uart4_int_rx,
+    RT_NULL
+};
+struct rt_device uart4_device;
+
+void MFS4RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart4_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /**< #ifdef RT_USING_UART4 */
+
+void rt_hw_serial_init(void)
+{
+    uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
+
+#ifdef RT_USING_UART0
+    /* initialize UART0 */
+    /* Set Uart Ch0 Port, SIN0_0:P21, SOT0_0:P22 */
+    FM3_GPIO->ADE &= ~(1UL<<31); /* disable P22 AN31 function */
+    FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | (1<<1) | (1<<2);
+    FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 & ~(3<<4 | 3<<6) | (1<<4) | (1<<6);
+
+    uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart0.uart_device->ESCR = ESCR_DATABITS_8;
+    uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&uart0_device,
+                          "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+#endif /**< #ifdef RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+    /* initialize UART2 */
+    /* Set Uart Ch2 Port, SIN2_2:P17, SOT2_2:P18 */
+    FM3_GPIO->ADE &= ~(1<<7 | 1<<8); /* disable P17 AN07 and P18 AN08 function */
+    FM3_GPIO->PFR1 = FM3_GPIO->PFR1 | (1<<7) | (1<<8) ;
+    FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | (3<<16) | (3<<18) ;
+
+    uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart2.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart2.uart_device->ESCR = ESCR_DATABITS_8;
+    uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&uart2_device,
+                          "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart2);
+#endif /**< #ifdef RT_USING_UART2 */
+
+#ifdef RT_USING_UART4
+    /* initialize UART4 */
+    /* Set Uart Ch4 Port, SIN4_2:P05, SOT4_2:P06 */
+    FM3_GPIO->PFR0 = FM3_GPIO->PFR0 | (1<<5) | (1<<6);
+    FM3_GPIO->EPFR08 = FM3_GPIO->EPFR08 | (3<<4) | (3<<6);
+
+    uart4.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart4.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart4.uart_device->ESCR = ESCR_DATABITS_8;
+    uart4.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    /* register UART4 device */
+    rt_hw_serial_register(&uart4_device,
+                          "uart4",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart4);
+#endif /**< #ifdef RT_USING_UART4 */
+}
+
+/*@}*/
diff --git a/bsp/mb9bf618s/drivers/serial.h b/bsp/mb9bf618s/drivers/serial.h
new file mode 100644
index 0000000000..9a47cba38f
--- /dev/null
+++ b/bsp/mb9bf618s/drivers/serial.h
@@ -0,0 +1,99 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.      	  	
+ */
+
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#define SMR_SOE          0x01U
+#define SMR_BDS          0x04U
+#define SMR_SBL          0x08U
+#define SMR_WUCR         0x10U
+#define SMR_MD_UART      0x00U
+#define SMR_MD_UART_MP   0x20U
+#define SMR_MD_SIO       0x40U
+#define SMR_MD_LIN       0x60U
+#define SMR_MD_I2C       0x80U
+
+#define SCR_TXE          0x01U
+#define SCR_RXE          0x02U
+#define SCR_TBIE         0x04U
+#define SCR_TIE          0x08U
+#define SCR_RIE          0x10U
+#define SCR_UPGL         0x80U
+
+#define SSR_TBI          0x01U
+#define SSR_TDRE         0x02U
+#define SSR_RDRF         0x04U
+#define SSR_ORE          0x08U
+#define SSR_FRE          0x10U
+#define SSR_PE           0x20U
+#define SSR_REC          0x80U
+
+#define ESCR_P           0x08U
+#define ESCR_PEN         0x10U
+#define ESCR_INV         0x20U
+#define ESCR_ESBL        0x40U
+#define ESCR_FLWEN       0x80U
+#define ESCR_DATABITS_8  0x00U
+#define ESCR_DATABITS_5  0x01U
+#define ESCR_DATABITS_6  0x02U
+#define ESCR_DATABITS_7  0x03U
+#define ESCR_DATABITS_9  0x04U
+
+#define BPS					115200	/* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE		64
+#define UART_TX_BUFFER_SIZE		64
+
+struct serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+	rt_uint32_t write_index, save_index;
+};
+
+/*
+ *  Enable/DISABLE Interrupt Controller
+ */
+/* deviation from MISRA-C:2004 Rule 19.7 */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct serial_device
+{
+	FM3_MFS03_UART_TypeDef* uart_device;
+	/* irq number */
+	IRQn_Type rx_irq, tx_irq;
+
+	/* rx structure */
+	struct serial_int_rx* int_rx;
+	/* tx structure */
+	struct serial_int_tx* int_tx;
+};
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_init(void);
+
+#endif
diff --git a/bsp/mb9bf618s/rtconfig.h b/bsp/mb9bf618s/rtconfig.h
new file mode 100644
index 0000000000..85c8719d36
--- /dev/null
+++ b/bsp/mb9bf618s/rtconfig.h
@@ -0,0 +1,74 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX				        8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE			        4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	        32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND		        100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore */
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+
+/* SECTION: Console options */
+/* #define RT_TINY_SIZE */
+#define RT_USING_CONSOLE
+/* the buffer size of console */
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	        "uart0"
+
+/* SECTION: finsh, a C-Express shell */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_STACK_SIZE         1024
+
+#endif
diff --git a/bsp/mb9bf618s/rtconfig.py b/bsp/mb9bf618s/rtconfig.py
new file mode 100644
index 0000000000..4620b93e01
--- /dev/null
+++ b/bsp/mb9bf618s/rtconfig.py
@@ -0,0 +1,118 @@
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='keil'
+
+#device options
+# FM3_TYPE = 
+# 'MB9B610S','MB9B610T',
+FM3_TYPE = 'MB9B610S'
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= r'F:\Program Files\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI_2013.05.23\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= r'E:/Keil'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	IAR_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-fm3.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread-fm3.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = ''
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    CFLAGS += ' --cpu=Cortex-M3' 
+    CFLAGS += ' -e' 
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+    CFLAGS += ' --use_c++_inline'    
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    AFLAGS += ' --cpu Cortex-M3' 
+    AFLAGS += ' --fpu None' 
+    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+
+    LFLAGS = ' --config mb9bf506.icf'
+    LFLAGS += ' --semihosting' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' 
diff --git a/bsp/mb9bf618s/rtthread-fm3.icf b/bsp/mb9bf618s/rtthread-fm3.icf
new file mode 100644
index 0000000000..be53bfb67e
--- /dev/null
+++ b/bsp/mb9bf618s/rtthread-fm3.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__   = 0x000FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block CSTACK, last block HEAP };
diff --git a/bsp/mb9bf618s/rtthread-fm3.ld b/bsp/mb9bf618s/rtthread-fm3.ld
new file mode 100644
index 0000000000..6696a0b1c2
--- /dev/null
+++ b/bsp/mb9bf618s/rtthread-fm3.ld
@@ -0,0 +1,143 @@
+/*
+ * linker script for Fujitsu with GNU ld
+ * aozima 2013-07-13
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH =   1M /*   1MB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram, 64KB SRAM0 + 64KB SRAM1 */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x400;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _isr_vector = .;     /* define isr_vector start address */
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/mb9bf618s/rtthread-fm3.sct b/bsp/mb9bf618s/rtthread-fm3.sct
new file mode 100644
index 0000000000..405f2ebb65
--- /dev/null
+++ b/bsp/mb9bf618s/rtthread-fm3.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x1FFF0000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/mb9bf618s/template.ewp b/bsp/mb9bf618s/template.ewp
new file mode 100644
index 0000000000..4883fc16e7
--- /dev/null
+++ b/bsp/mb9bf618s/template.ewp
@@ -0,0 +1,1839 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>Debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>6.50.2.4581</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.2.4581</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MB9BF618S	Fujitsu MB9BF618S</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>0000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>project.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\rtthread-fm3.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
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+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <name>FillerStart</name>
+          <state>0x0</state>
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+          <name>FillerEnd</name>
+          <state>0x0</state>
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+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
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+    <debug>0</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Release\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Release\Obj</state>
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+        <option>
+          <name>ListPath</name>
+          <state>Release\List</state>
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+        <option>
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+          <version>20</version>
+          <state>38</state>
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+          <version>3</version>
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+          <name>Input description</name>
+          <state>Automatic choice of formatter.</state>
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+          <version>2</version>
+          <state>0</state>
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+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter.</state>
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+          <state>0</state>
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+        <option>
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+          <name>OGCoreOrChip</name>
+          <state>1</state>
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+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+          <state>6.50.2.4581</state>
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+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MB9BF618S	Fujitsu MB9BF618S</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
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+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
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+        <option>
+          <name>GenStdoutInterface</name>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+      <archiveVersion>2</archiveVersion>
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+        <wantNonLocal>1</wantNonLocal>
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+        <option>
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+          <state>NDEBUG</state>
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+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
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+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
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+          <state>1</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
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+          <name>CCMultibyteSupport</name>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
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+          <name>IFpuProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>OutputFile</name>
+          <state></state>
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+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
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+          <state></state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <state>3</state>
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+          <version>0</version>
+          <state>0</state>
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+          <name>IccLang</name>
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+          <state>1</state>
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+          <name>IccCppDialect</name>
+          <state>1</state>
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+          <state>1</state>
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+          <name>IccRTTI</name>
+          <state>1</state>
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+          <name>IccStaticDestr</name>
+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
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+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
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+        <option>
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+          <state>1</state>
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+          <state></state>
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+          <state>0</state>
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+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>template.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\rtthread-fm3.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+</project>
+
+
diff --git a/bsp/mb9bf618s/template.uvproj b/bsp/mb9bf618s/template.uvproj
new file mode 100644
index 0000000000..ec72dd0f7f
--- /dev/null
+++ b/bsp/mb9bf618s/template.uvproj
@@ -0,0 +1,394 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MB9BF618S</Device>
+          <Vendor>Fujitsu Semiconductors</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IRAM2(0x1FFF0000-0x1FFFFFFF) IROM(0x00000000-0x000FFFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"Startup\Fujitsu\MB9BF610\startup_mb9bf61x.s" ("Fujitsu MB9BF610 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx08_1024 -FS00 -FL0100000)</FlashDriverDll>
+          <DeviceId>6149</DeviceId>
+          <RegisterFile>mb9bf618s.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\Fujitsu\MB9BF610\MB9BF618S.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Fujitsu\MB9BF610\</RegisterFilePath>
+          <DBRegisterFilePath>Fujitsu\MB9BF610\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread-fm3</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4099</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2>Segger\JL2CM3.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>rtthread-fm3.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>

From 318452796fb5ef136be246638a974f6b514a97ae Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 07:00:47 +0800
Subject: [PATCH 65/86] [bsp] Add MB9BF618 porting.

---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index 94b130fdd7..28920e49c6 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -36,6 +36,7 @@ env:
 #  - RTT_BSP='m16c62p' # m32c
   - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='microblaze' # no scons
   - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm' 
 #  - RTT_BSP='mini4020' # no scons
@@ -57,4 +58,3 @@ env:
   - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
-

From 2a269a8a2aa273e78c00aaee1cdfb76632b20d54 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 07:28:44 +0800
Subject: [PATCH 66/86] [bsp] Fix MB9BF618S building issue.

---
 bsp/mb9bf618s/rtconfig.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/bsp/mb9bf618s/rtconfig.py b/bsp/mb9bf618s/rtconfig.py
index 4620b93e01..8c60f44864 100644
--- a/bsp/mb9bf618s/rtconfig.py
+++ b/bsp/mb9bf618s/rtconfig.py
@@ -1,8 +1,13 @@
+import os
+
 # toolchains options
 ARCH='arm'
 CPU='cortex-m3'
 CROSS_TOOL='keil'
 
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
 #device options
 # FM3_TYPE = 
 # 'MB9B610S','MB9B610T',
@@ -110,7 +115,7 @@ elif PLATFORM == 'iar':
     AFLAGS += ' --fpu None' 
     AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
 
-    LFLAGS = ' --config mb9bf506.icf'
+    LFLAGS = ' --config rtthread-fm3.icf'
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 

From b21c35df63585c56cf97d71184dd62c229191ab0 Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Mon, 21 Jul 2014 19:09:15 +0800
Subject: [PATCH 67/86] [bsp] Add IAR EWARM project template for SCONS project
 auto generation.

---
 bsp/tm4c129x/applications/board.c             |    3 +-
 bsp/tm4c129x/drivers/drv_uart.c               |    4 +-
 .../libraries/startup/startup_ewarm.c         |   13 +-
 bsp/tm4c129x/libraries/startup/startup_gcc.c  |    6 +-
 bsp/tm4c129x/template.ewp                     | 1889 +++++++++++++++++
 bsp/tm4c129x/template.eww                     |   10 +
 bsp/tm4c129x/tm4c_rom.icf                     |    2 +
 7 files changed, 1917 insertions(+), 10 deletions(-)
 create mode 100644 bsp/tm4c129x/template.ewp
 create mode 100644 bsp/tm4c129x/template.eww

diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c
index cb3cf92eb6..c638369a5a 100644
--- a/bsp/tm4c129x/applications/board.c
+++ b/bsp/tm4c129x/applications/board.c
@@ -61,6 +61,7 @@ extern void HardFault_Handler(void);
  */
 void rt_hw_board_init()
 {
+  MAP_IntMasterDisable();
     IntRegister(FAULT_HARD, HardFault_Handler);	
     IntRegister(FAULT_PENDSV, PendSV_Handler);
     IntRegister(FAULT_SYSTICK, SysTick_Handler);
@@ -87,7 +88,7 @@ void rt_hw_board_init()
     MAP_SysTickEnable();	
 
     /* set pend exception priority */
-    IntPrioritySet(FAULT_PENDSV, (1 << 5) - 1);
+    //IntPrioritySet(FAULT_PENDSV, (1 << 5) - 1);
     
     /*init uart device*/		
     rt_hw_uart_init();
diff --git a/bsp/tm4c129x/drivers/drv_uart.c b/bsp/tm4c129x/drivers/drv_uart.c
index 7f87083999..20ce0db224 100644
--- a/bsp/tm4c129x/drivers/drv_uart.c
+++ b/bsp/tm4c129x/drivers/drv_uart.c
@@ -36,7 +36,7 @@ typedef struct hw_uart_device
 
 static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {	
-	uint32_t config;
+	uint32_t config = 0;
 	hw_uart_t* uart;
     RT_ASSERT(serial != RT_NULL);
     uart = mUartGetHwPtr(serial);
@@ -206,7 +206,7 @@ int rt_hw_uart_init(void)
     MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
 
     /* preemption = 1, sub-priority = 1 */
-    IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01));
+    //IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01));
 
     /* Enable Interrupt for UART channel */
 	  UARTIntRegister(uart->hw_base, UART0_IRQHandler);
diff --git a/bsp/tm4c129x/libraries/startup/startup_ewarm.c b/bsp/tm4c129x/libraries/startup/startup_ewarm.c
index eb852f59a2..cbcbda31e5 100644
--- a/bsp/tm4c129x/libraries/startup/startup_ewarm.c
+++ b/bsp/tm4c129x/libraries/startup/startup_ewarm.c
@@ -50,7 +50,10 @@ static void IntDefaultHandler(void);
 //
 //*****************************************************************************
 extern void __iar_program_start(void);
-
+extern void PendSV_Handler(void);
+extern void SysTick_Handler(void);
+extern void UART0_IRQHandler(void);
+extern void HardFault_Handler(void);
 //*****************************************************************************
 //
 // Reserve space for the system stack.
@@ -84,7 +87,7 @@ __root const uVectorEntry __vector_table[] @ ".intvec" =
                                             // The initial stack pointer
     ResetISR,                               // The reset handler
     NmiSR,                                  // The NMI handler
-    FaultISR,                               // The hard fault handler
+    HardFault_Handler,                               // The hard fault handler
     IntDefaultHandler,                      // The MPU fault handler
     IntDefaultHandler,                      // The bus fault handler
     IntDefaultHandler,                      // The usage fault handler
@@ -95,14 +98,14 @@ __root const uVectorEntry __vector_table[] @ ".intvec" =
     IntDefaultHandler,                      // SVCall handler
     IntDefaultHandler,                      // Debug monitor handler
     0,                                      // Reserved
-    IntDefaultHandler,                      // The PendSV handler
-    IntDefaultHandler,                      // The SysTick handler
+    PendSV_Handler, //IntDefaultHandler,                      // The PendSV handler
+    SysTick_Handler,//IntDefaultHandler,                      // The SysTick handler
     IntDefaultHandler,                      // GPIO Port A
     IntDefaultHandler,                      // GPIO Port B
     IntDefaultHandler,                      // GPIO Port C
     IntDefaultHandler,                      // GPIO Port D
     IntDefaultHandler,                      // GPIO Port E
-    IntDefaultHandler,                      // UART0 Rx and Tx
+    UART0_IRQHandler, //IntDefaultHandler,                      // UART0 Rx and Tx
     IntDefaultHandler,                      // UART1 Rx and Tx
     IntDefaultHandler,                      // SSI0 Rx and Tx
     IntDefaultHandler,                      // I2C0 Master and Slave
diff --git a/bsp/tm4c129x/libraries/startup/startup_gcc.c b/bsp/tm4c129x/libraries/startup/startup_gcc.c
index 8bba1ae36d..ae10bf8e6c 100644
--- a/bsp/tm4c129x/libraries/startup/startup_gcc.c
+++ b/bsp/tm4c129x/libraries/startup/startup_gcc.c
@@ -45,6 +45,8 @@ extern int main(void);
 
 extern void SysTick_Handler(void);
 extern void PendSV_Handler(void);
+extern void UART0_IRQHandler(void);
+extern void HardFault_Handler(void);
 //*****************************************************************************
 //
 // Reserve space for the system stack.
@@ -65,7 +67,7 @@ void (* const g_pfnVectors[])(void) =
                                             // The initial stack pointer
     ResetISR,                               // The reset handler
     NmiSR,                                  // The NMI handler
-    FaultISR,                               // The hard fault handler
+    HardFault_Handler,                      // The hard fault handler
     IntDefaultHandler,                      // The MPU fault handler
     IntDefaultHandler,                      // The bus fault handler
     IntDefaultHandler,                      // The usage fault handler
@@ -83,7 +85,7 @@ void (* const g_pfnVectors[])(void) =
     IntDefaultHandler,                      // GPIO Port C
     IntDefaultHandler,                      // GPIO Port D
     IntDefaultHandler,                      // GPIO Port E
-    IntDefaultHandler,                      // UART0 Rx and Tx
+    UART0_IRQHandler,                      // UART0 Rx and Tx
     IntDefaultHandler,                      // UART1 Rx and Tx
     IntDefaultHandler,                      // SSI0 Rx and Tx
     IntDefaultHandler,                      // I2C0 Master and Slave
diff --git a/bsp/tm4c129x/template.ewp b/bsp/tm4c129x/template.ewp
new file mode 100644
index 0000000000..97696050b6
--- /dev/null
+++ b/bsp/tm4c129x/template.ewp
@@ -0,0 +1,1889 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>22</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>build\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>build\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>build\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>40</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>7.20.1.7306</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.20.1.7306</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>TM4C1294NCPDT	TexasInstruments TM4C1294NCPDT</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>40</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>40</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCDefines</name>
+          <state>ewarm</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
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+          <state>1</state>
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+        <extensions></extensions>
+        <cmdline></cmdline>
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+        <option>
+          <name>RTConfigPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCDefines</name>
+          <state>NDEBUG</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>11111110</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>###Unitialized###</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>lnk0t.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+</project>
+
+
diff --git a/bsp/tm4c129x/template.eww b/bsp/tm4c129x/template.eww
new file mode 100644
index 0000000000..bd036bb4c9
--- /dev/null
+++ b/bsp/tm4c129x/template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/tm4c129x/tm4c_rom.icf b/bsp/tm4c129x/tm4c_rom.icf
index 38c73c9e28..b09595243d 100644
--- a/bsp/tm4c129x/tm4c_rom.icf
+++ b/bsp/tm4c129x/tm4c_rom.icf
@@ -76,3 +76,5 @@ place at start of SRAM { section VTABLE };
 // Place all read/write items into SRAM.
 //
 place in SRAM { readwrite, block HEAP };
+keep { section FSymTab };
+keep { section VSymTab };
\ No newline at end of file

From 4e624d857eff6fd0779ca20f55dcff7195cdbbbf Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 22:02:27 +0800
Subject: [PATCH 68/86] [bsp] Fix MB9BF618s scons building issue

---
 bsp/mb9bf618s/rtconfig.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/bsp/mb9bf618s/rtconfig.py b/bsp/mb9bf618s/rtconfig.py
index 8c60f44864..5a21a70555 100644
--- a/bsp/mb9bf618s/rtconfig.py
+++ b/bsp/mb9bf618s/rtconfig.py
@@ -26,6 +26,9 @@ elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
 	IAR_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
 
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
 BUILD = 'debug'
 
 if PLATFORM == 'gcc':

From 0135dd38cf2b485b071b143ca544bb4d7c801a68 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Mon, 21 Jul 2014 22:04:06 +0800
Subject: [PATCH 69/86] [bsp] Add tm4c129x bsp building in travis-ci

---
 .travis.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.travis.yml b/.travis.yml
index 28920e49c6..6c6206fe2b 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -28,6 +28,7 @@ env:
   - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm' 

From 666d12988a2ab3fc9eb878e3b52cb083c85e6dbe Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Fri, 25 Jul 2014 18:58:56 +0800
Subject: [PATCH 70/86] [BSP] tm4c129x: 1. Add ETH MAC driver using DMA for Tx
 and Rx lwip pBuf. 2. Modify the tivaware emac library to fix the bug that PHY
 read is not stable when sysclk is 120MHz 3. In PHY IRQ handler, insert a
 dummy reading (REG_BMSR) before read PHY_STS to force update STS register.

---
 bsp/lm4f232/rtconfig.h                  |    2 +-
 bsp/tm4c129x/applications/application.c |    6 +
 bsp/tm4c129x/applications/board.c       |    2 +-
 bsp/tm4c129x/drivers/drv_eth.c          | 1446 +++++++++++++++++++++++
 bsp/tm4c129x/drivers/drv_eth.h          |   20 +
 bsp/tm4c129x/libraries/driverlib/emac.c |    1 +
 6 files changed, 1475 insertions(+), 2 deletions(-)
 create mode 100644 bsp/tm4c129x/drivers/drv_eth.c
 create mode 100644 bsp/tm4c129x/drivers/drv_eth.h

diff --git a/bsp/lm4f232/rtconfig.h b/bsp/lm4f232/rtconfig.h
index 723077dd50..586b4adac2 100644
--- a/bsp/lm4f232/rtconfig.h
+++ b/bsp/lm4f232/rtconfig.h
@@ -93,7 +93,7 @@
 #define DFS_FD_MAX					4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
-/* #define RT_USING_LWIP */
+#define RT_USING_LWIP
 /* LwIP uses RT-Thread Memory Management */
 #define RT_LWIP_USING_RT_MEM
 /* Enable ICMP protocol*/
diff --git a/bsp/tm4c129x/applications/application.c b/bsp/tm4c129x/applications/application.c
index 80f58b6ed8..984e622157 100644
--- a/bsp/tm4c129x/applications/application.c
+++ b/bsp/tm4c129x/applications/application.c
@@ -16,6 +16,9 @@
 #include <board.h>
 #include <components.h>
 
+#ifdef RT_USING_LWIP
+#include "drv_eth.h"
+#endif
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
@@ -24,6 +27,9 @@ void rt_init_thread_entry(void *parameter)
 #ifdef RT_USING_FINSH
     finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+#ifdef RT_USING_LWIP
+    rt_hw_tiva_eth_init();
+#endif
 }
 
 int rt_application_init(void)
diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c
index c638369a5a..2953e76c58 100644
--- a/bsp/tm4c129x/applications/board.c
+++ b/bsp/tm4c129x/applications/board.c
@@ -92,7 +92,7 @@ void rt_hw_board_init()
     
     /*init uart device*/		
     rt_hw_uart_init();
-		//redirect RTT stdio to CONSOLE device
+    //redirect RTT stdio to CONSOLE device
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
     //
     // Enable interrupts to the processor.
diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c
new file mode 100644
index 0000000000..ea4813be00
--- /dev/null
+++ b/bsp/tm4c129x/drivers/drv_eth.c
@@ -0,0 +1,1446 @@
+/*
+ * File      : drv_eth.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-25     ArdaFu       Port to TM4C129X
+ */
+
+/**
+ * @file - tivaif.c
+ * lwIP Ethernet interface for Stellaris LM4F Devices
+ *
+ */
+
+/**
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICui32AR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/**
+ * Copyright (c) 2008-2012 Texas Instruments Incorporated
+ *
+ * This file is derived from the ``ethernetif.c'' skeleton Ethernet network
+ * interface driver for lwIP.
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include <lwip/stats.h>
+#include <lwip/snmp.h>
+#include "lwip/tcpip.h"
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+
+/**
+ * Sanity Check:  This interface driver will NOT work if the following defines
+ * are incorrect.
+ *
+ */
+#if (PBUF_LINK_HLEN != 16)
+#error "PBUF_LINK_HLEN must be 16 for this interface driver!"
+#endif
+#if (ETH_PAD_SIZE != 0)
+#error "ETH_PAD_SIZE must be 0 for this interface driver!"
+#endif
+#if (!SYS_LIGHTWEIGHT_PROT)
+#error "SYS_LIGHTWEIGHT_PROT must be enabled for this interface driver!"
+#endif
+
+/**
+ * Set the physical address of the PHY we will be using if this is not
+ * specified in lwipopts.h.  We assume 0 for the internal PHY.
+ */
+#ifndef PHY_PHYS_ADDR
+#define PHY_PHYS_ADDR 0
+#endif
+
+#if 0
+#ifndef EMAC_PHY_CONFIG
+#define EMAC_PHY_CONFIG (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN |      \
+                         EMAC_PHY_AN_100B_T_FULL_DUPLEX)
+#endif
+#endif
+
+/**
+ * If necessary, set the defaui32t number of transmit and receive DMA descriptors
+ * used by the Ethernet MAC.
+ *
+ */
+#ifndef NUM_RX_DESCRIPTORS
+#define NUM_RX_DESCRIPTORS 4
+#endif
+
+#ifndef NUM_TX_DESCRIPTORS
+#define NUM_TX_DESCRIPTORS 8
+#endif
+
+/**
+ * Setup processing for PTP (IEEE-1588).
+ *
+ */
+#if LWIP_PTPD
+extern uint32_t g_ui32SysClk;
+extern uint32_t g_ui32PTPTickRate;
+extern void lwIPHostGetTime(u32_t *time_s, u32_t *time_ns);
+#endif
+
+/**
+ * Stellaris DriverLib Header Files required for this interface driver.
+ *
+ */
+#include <stdint.h>
+#include <stdbool.h>
+#include "inc/hw_emac.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+
+#include "driverlib/emac.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
+
+#include "driverlib/pin_map.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/gpio.h"
+
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+#include "drv_eth.h"
+
+/**
+ * A structure used to keep track of driver state and error counts.
+ */
+typedef struct {
+    uint32_t ui32TXCount;
+    uint32_t ui32TXCopyCount;
+    uint32_t ui32TXCopyFailCount;
+    uint32_t ui32TXNoDescCount;
+    uint32_t ui32TXBufQueuedCount;
+    uint32_t ui32TXBufFreedCount;
+    uint32_t ui32RXBufReadCount;
+    uint32_t ui32RXPacketReadCount;
+    uint32_t ui32RXPacketErrCount;
+    uint32_t ui32RXPacketCBErrCount;
+    uint32_t ui32RXNoBufCount;
+}
+tDriverStats;
+
+tDriverStats g_sDriverStats;
+
+#ifdef DEBUG
+/**
+ * Note: This rather weird construction where we invoke the macro with the
+ * name of the field minus its Hungarian prefix is a workaround for a problem
+ * experienced with GCC which does not like concatenating tokens after an
+ * operator, specifically '.' or '->', in a macro.
+ */
+#define DRIVER_STATS_INC(x) do{ g_sDriverStats.ui32##x++; } while(0)
+#define DRIVER_STATS_DEC(x) do{ g_sDriverStats.ui32##x--; } while(0)
+#define DRIVER_STATS_ADD(x, inc) do{ g_sDriverStats.ui32##x += (inc); } while(0)
+#define DRIVER_STATS_SUB(x, dec) do{ g_sDriverStats.ui32##x -= (dec); } while(0)
+#else
+#define DRIVER_STATS_INC(x)
+#define DRIVER_STATS_DEC(x)
+#define DRIVER_STATS_ADD(x, inc)
+#define DRIVER_STATS_SUB(x, dec)
+#endif
+
+/**
+ *  Helper struct holding a DMA descriptor and the pbuf it currently refers
+ *  to.
+ */
+typedef struct {
+  tEMACDMADescriptor Desc;
+  struct pbuf *pBuf;
+} tDescriptor;
+
+typedef struct {
+    tDescriptor *pDescriptors;
+    uint32_t ui32NumDescs;
+    uint32_t ui32Read;
+    uint32_t ui32Write;
+} tDescriptorList;
+
+/**
+ * Helper struct to hold private data used to operate your ethernet interface.
+ * Keeping the ethernet address of the MAC in this struct is not necessary
+ * as it is already kept in the struct netif.
+ * But this is only an example, anyway...
+ */
+typedef struct {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+  tDescriptorList *pTxDescList;
+  tDescriptorList *pRxDescList;
+} tStellarisIF;
+
+/**
+ * Global variable for this interface's private data.  Needed to allow
+ * the interrupt handlers access to this information outside of the
+ * context of the lwIP netif.
+ *
+ */
+tDescriptor g_pTxDescriptors[NUM_TX_DESCRIPTORS];
+tDescriptor g_pRxDescriptors[NUM_RX_DESCRIPTORS];
+tDescriptorList g_TxDescList = {
+    g_pTxDescriptors, NUM_TX_DESCRIPTORS, 0, 0
+};
+tDescriptorList g_RxDescList = {
+    g_pRxDescriptors, NUM_RX_DESCRIPTORS, 0, 0
+};
+static tStellarisIF g_StellarisIFData = {
+    0, &g_TxDescList, &g_RxDescList
+};
+
+/**
+ * Interrupt counters (for debug purposes).
+ */
+volatile uint32_t g_ui32NormalInts;
+volatile uint32_t g_ui32AbnormalInts;
+
+/**
+ * A macro which determines whether a pointer is within the SRAM address
+ * space and, hence, points to a buffer that the Ethernet MAC can directly
+ * DMA from.
+ */
+#define PTR_SAFE_FOR_EMAC_DMA(ptr) (((uint32_t)(ptr) >= 0x2000000) &&   \
+                                    ((uint32_t)(ptr) < 0x20070000))
+
+
+typedef struct 
+{
+	/* inherit from ethernet device */
+	struct eth_device parent;
+	tStellarisIF* dma_if;
+	/* for rx_thread async get pbuf */
+	rt_mailbox_t rx_pbuf_mb;
+} net_device;
+typedef net_device* net_device_t; 
+
+static char               rx_pbuf_mb_pool[8*4];
+static struct rt_mailbox  eth_rx_pbuf_mb;
+static net_device         eth_dev_entry;
+static net_device_t       eth_dev = &eth_dev_entry;
+
+/**
+ * Initialize the transmit and receive DMA descriptor lists.
+ */
+void
+InitDMADescriptors(void)
+{
+    uint32_t ui32Loop;
+
+    /* Transmit list -  mark all descriptors as not owned by the hardware */
+   for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++)
+   {
+       g_pTxDescriptors[ui32Loop].pBuf = (struct pbuf *)0;
+       g_pTxDescriptors[ui32Loop].Desc.ui32Count = 0;
+       g_pTxDescriptors[ui32Loop].Desc.pvBuffer1 = 0;
+       g_pTxDescriptors[ui32Loop].Desc.DES3.pLink =
+               ((ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ?
+               &g_pTxDescriptors[0].Desc : &g_pTxDescriptors[ui32Loop + 1].Desc);
+       g_pTxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_TX_CTRL_INTERRUPT |
+               DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_IP_ALL_CKHSUMS;
+
+   }
+
+   g_TxDescList.ui32Read = 0;
+   g_TxDescList.ui32Write = 0;
+
+
+   /* Receive list -  tag each descriptor with a pbuf and set all fields to
+    * allow packets to be received.
+    */
+  for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++)
+  {
+      g_pRxDescriptors[ui32Loop].pBuf = pbuf_alloc(PBUF_RAW, PBUF_POOL_BUFSIZE,
+                                                 PBUF_POOL);
+      g_pRxDescriptors[ui32Loop].Desc.ui32Count = DES1_RX_CTRL_CHAINED;
+      if(g_pRxDescriptors[ui32Loop].pBuf)
+      {
+          /* Set the DMA to write directly into the pbuf payload. */
+          g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 =
+                  g_pRxDescriptors[ui32Loop].pBuf->payload;
+          g_pRxDescriptors[ui32Loop].Desc.ui32Count |=
+             (g_pRxDescriptors[ui32Loop].pBuf->len << DES1_RX_CTRL_BUFF1_SIZE_S);
+          g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_RX_CTRL_OWN;
+      }
+      else
+      {
+          LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_init: pbuf_alloc error\n"));
+
+          /* No pbuf available so leave the buffer pointer empty. */
+          g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = 0;
+          g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = 0;
+      }
+      g_pRxDescriptors[ui32Loop].Desc.DES3.pLink =
+              ((ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ?
+              &g_pRxDescriptors[0].Desc : &g_pRxDescriptors[ui32Loop + 1].Desc);
+  }
+
+  g_TxDescList.ui32Read = 0;
+  g_TxDescList.ui32Write = 0;
+
+  //
+  // Set the descriptor pointers in the hardware.
+  //
+  EMACRxDMADescriptorListSet(EMAC0_BASE, &g_pRxDescriptors[0].Desc);
+  EMACTxDMADescriptorListSet(EMAC0_BASE, &g_pTxDescriptors[0].Desc);
+}
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from tivaif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void
+tivaif_hwinit(struct netif *psNetif)
+{
+  uint16_t ui16Val;
+
+  /* Initialize the DMA descriptors. */
+  InitDMADescriptors();
+
+  /* Clear any stray PHY interrupts that may be set. */
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2);
+
+  /* Configure and enable the link status change interrupt in the PHY. */
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR);
+  ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT);
+  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val);
+  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN |
+               EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN));
+
+  /* Read the PHY interrupt status to clear any stray events. */
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
+
+  /**
+   * Set MAC filtering options.  We receive all broadcast and mui32ticast
+   * packets along with those addressed specifically for us.
+   */
+  EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_HASH_AND_PERFECT |
+                     EMAC_FRMFILTER_PASS_MULTICAST));
+
+#if LWIP_PTPD
+  //
+  // Enable timestamping on all received packets.
+  //
+  // We set the fine clock adjustment mode and configure the subsecond
+  // increment to half the 25MHz PTPD clock.  This will give us maximum control
+  // over the clock rate adjustment and keep the arithmetic easy later.  It
+  // should be possible to synchronize with higher accuracy than this with
+  // appropriate juggling of the subsecond increment count and the addend
+  // register value, though.
+  //
+  EMACTimestampConfigSet(EMAC0_BASE, (EMAC_TS_ALL_RX_FRAMES |
+                         EMAC_TS_DIGITAL_ROLLOVER |
+                         EMAC_TS_PROCESS_IPV4_UDP | EMAC_TS_ALL |
+                         EMAC_TS_PTP_VERSION_1 | EMAC_TS_UPDATE_FINE),
+                         (1000000000 / (25000000 / 2)));
+  EMACTimestampAddendSet(EMAC0_BASE, 0x80000000);
+  EMACTimestampEnable(EMAC0_BASE);
+#endif
+
+  /* Clear any pending MAC interrupts. */
+  EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false));
+
+  /* Enable the Ethernet MAC transmitter and receiver. */
+  EMACTxEnable(EMAC0_BASE);
+  EMACRxEnable(EMAC0_BASE);
+
+  /* Enable the Ethernet RX and TX interrupt source. */
+  EMACIntEnable(EMAC0_BASE, (EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT |
+                EMAC_INT_TX_STOPPED | EMAC_INT_RX_NO_BUFFER |
+                EMAC_INT_RX_STOPPED | EMAC_INT_PHY));
+
+  /* Enable the Ethernet interrupt. */
+  IntEnable(INT_EMAC0);
+
+  /* Enable all processor interrupts. */
+  IntMasterEnable();
+
+  /* Tell the PHY to start an auto-negotiation cycle. */
+  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN |
+               EPHY_BMCR_RESTARTAN));
+}
+
+#ifdef DEBUG
+/**
+ * Dump the chain of pbuf pointers to the debug output.
+ */
+void
+tivaif_trace_pbuf(const char *pcTitle, struct pbuf *p)
+{
+    LWIP_DEBUGF(NETIF_DEBUG, ("%s %08x (%d, %d)", pcTitle, p, p->tot_len,
+                p->len));
+
+    do
+    {
+        p = p->next;
+        if(p)
+        {
+            LWIP_DEBUGF(NETIF_DEBUG, ("->%08x(%d)", p, p->len));
+        }
+        else
+        {
+            LWIP_DEBUGF(NETIF_DEBUG, ("->%08x", p));
+        }
+
+    } while((p != NULL) && (p->tot_len != p->len));
+
+    LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+}
+#endif
+
+/**
+ * This function is used to check whether a passed pbuf contains only buffers
+ * resident in regions of memory that the Ethernet MAC can access.  If any
+ * buffers in the chain are outside a directly-DMAable section of memory,
+ * the pbuf is copied to SRAM and a different pointer returned.  If all
+ * buffers are safe, the pbuf reference count is incremented and the original
+ * pointer returned.
+ */
+static struct pbuf *
+tivaif_check_pbuf(struct pbuf *p)
+{
+    struct pbuf *pBuf;
+    rt_err_t Err;
+
+    pBuf = p;
+
+#ifdef DEBUG
+    tivaif_trace_pbuf("Original:", p);
+#endif
+
+    /* Walk the list of buffers in the pbuf checking each. */
+    do
+    {
+        /* Does this pbuf's payload reside in memory that the Ethernet DMA
+         * can access?
+         */
+        if(!PTR_SAFE_FOR_EMAC_DMA(pBuf->payload))
+        {
+            /* This buffer is outside the DMA-able memory space so we need
+             * to copy the pbuf.
+             */
+            pBuf = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_POOL);
+
+            /* If we got a new pbuf... */
+            if(pBuf)
+            {
+                /* ...copy the old pbuf into the new one. */
+                Err = pbuf_copy(pBuf, p);
+
+                /* If we failed to copy the pbuf, free the newly allocated one
+                 * and make sure we return a NULL to show a problem.
+                 */
+                if(Err != RT_EOK)
+                {
+                    DRIVER_STATS_INC(TXCopyFailCount);
+                    pbuf_free(pBuf);
+                    pBuf = NULL;
+                }
+                else
+                {
+#ifdef DEBUG
+                    tivaif_trace_pbuf("Copied:", pBuf);
+#endif
+                    DRIVER_STATS_INC(TXCopyCount);
+
+                    /* Reduce the reference count on the original pbuf since
+                     * we're not going to hold on to it after returning from
+                     * tivaif_transmit.  Note that we already bumped
+                     * the reference count at the top of tivaif_transmit.
+                     */
+                    pbuf_free(p);
+                }
+            }
+
+            /* Send back the new pbuf pointer or NULL if an error occurred. */
+            return(pBuf);
+        }
+
+        /* Move on to the next buffer in the queue */
+        pBuf = pBuf->next;
+    }
+    while(pBuf);
+
+    /**
+     * If we get here, the passed pbuf can be safely used without needing to
+     * be copied.
+     */
+    return(p);
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf might be
+ * chained.
+ *
+ * @param psNetif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return RT_EOK if the packet coui32d be sent
+ *         an err_t value if the packet coui32dn't be sent
+ */
+static rt_err_t
+tivaif_transmit(net_device_t dev, struct pbuf *p)
+{
+  tStellarisIF *pIF;
+  tDescriptor *pDesc;
+  struct pbuf *pBuf;
+  uint32_t ui32NumChained, ui32NumDescs;
+  bool bFirst;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_transmit 0x%08x, len %d\n", p,
+              p->tot_len));
+
+  /**
+   * This entire function must run within a "critical section" to preserve
+   * the integrity of the transmit pbuf queue.
+   */
+  SYS_ARCH_PROTECT(lev);
+
+  /* Update our transmit attempt counter. */
+  DRIVER_STATS_INC(TXCount);
+
+  /**
+   * Increase the reference count on the packet provided so that we can
+   * hold on to it until we are finished transmitting its content.
+   */
+  pbuf_ref(p);
+
+  /**
+   * Determine whether all buffers passed are within SRAM and, if not, copy
+   * the pbuf into SRAM-resident buffers so that the Ethernet DMA can access
+   * the data.
+   */
+  p = tivaif_check_pbuf(p);
+
+  /* Make sure we still have a valid buffer (it may have been copied) */
+  if(!p)
+  {
+      LINK_STATS_INC(link.memerr);
+      SYS_ARCH_UNPROTECT(lev);
+      return(-RT_ENOMEM);
+  }
+
+  /* Get our state data from the netif structure we were passed. */
+  //pIF = (tStellarisIF *)psNetif->state;
+  pIF = dev->dma_if;
+  
+  /* Make sure that the transmit descriptors are not all in use */
+  pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]);
+  if(pDesc->pBuf)
+  {
+      /**
+       * The current write descriptor has a pbuf attached to it so this
+       * implies that the ring is fui32l. Reject this transmit request with a
+       * memory error since we can't satisfy it just now.
+       */
+      pbuf_free(p);
+      LINK_STATS_INC(link.memerr);
+      DRIVER_STATS_INC(TXNoDescCount);
+      SYS_ARCH_UNPROTECT(lev);
+      return (-RT_ENOMEM);
+  }
+
+  /* How many pbufs are in the chain passed? */
+  ui32NumChained = (uint32_t)pbuf_clen(p);
+
+  /* How many free transmit descriptors do we have? */
+  ui32NumDescs = (pIF->pTxDescList->ui32Read > pIF->pTxDescList->ui32Write) ?
+          (pIF->pTxDescList->ui32Read - pIF->pTxDescList->ui32Write) :
+          ((NUM_TX_DESCRIPTORS - pIF->pTxDescList->ui32Write) +
+           pIF->pTxDescList->ui32Read);
+
+  /* Do we have enough free descriptors to send the whole packet? */
+  if(ui32NumDescs < ui32NumChained)
+  {
+      /* No - we can't transmit this whole packet so return an error. */
+      pbuf_free(p);
+      LINK_STATS_INC(link.memerr);
+      DRIVER_STATS_INC(TXNoDescCount);
+      SYS_ARCH_UNPROTECT(lev);
+      return (-RT_ENOMEM);
+  }
+
+  /* Tag the first descriptor as the start of the packet. */
+  bFirst = true;
+  pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG;
+
+  /* Here, we know we can send the packet so write it to the descriptors */
+  pBuf = p;
+
+  while(ui32NumChained)
+  {
+      /* Get a pointer to the descriptor we will write next. */
+      pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]);
+
+      /* Fill in the buffer pointer and length */
+      pDesc->Desc.ui32Count = (uint32_t)pBuf->len;
+      pDesc->Desc.pvBuffer1 = pBuf->payload;
+
+      /* Tag the first descriptor as the start of the packet. */
+      if(bFirst)
+      {
+          bFirst = false;
+          pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG;
+      }
+      else
+      {
+          pDesc->Desc.ui32CtrlStatus = 0;
+      }
+
+      pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_IP_ALL_CKHSUMS |
+                                     DES0_TX_CTRL_CHAINED);
+
+      /* Decrement our descriptor counter, move on to the next buffer in the
+       * pbuf chain. */
+      ui32NumChained--;
+      pBuf = pBuf->next;
+
+      /* Update the descriptor list write index. */
+      pIF->pTxDescList->ui32Write++;
+      if(pIF->pTxDescList->ui32Write == NUM_TX_DESCRIPTORS)
+      {
+          pIF->pTxDescList->ui32Write = 0;
+      }
+
+      /* If this is the last descriptor, mark it as the end of the packet. */
+      if(!ui32NumChained)
+      {
+          pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_LAST_SEG |
+                                         DES0_TX_CTRL_INTERRUPT);
+
+          /* Tag the descriptor with the original pbuf pointer. */
+          pDesc->pBuf = p;
+      }
+      else
+      {
+          /* Set the lsb of the pbuf pointer.  We use this as a signal that
+           * we should not free the pbuf when we are walking the descriptor
+           * list while processing the transmit interrupt.  We only free the
+           * pbuf when processing the last descriptor used to transmit its
+           * chain.
+           */
+          pDesc->pBuf = (struct pbuf *)((uint32_t)p + 1);
+      }
+
+      DRIVER_STATS_INC(TXBufQueuedCount);
+
+      /* Hand the descriptor over to the hardware. */
+      pDesc->Desc.ui32CtrlStatus |= DES0_TX_CTRL_OWN;
+  }
+
+  /* Tell the transmitter to start (in case it had stopped). */
+  EMACTxDMAPollDemand(EMAC0_BASE);
+
+  /* Update lwIP statistics */
+  LINK_STATS_INC(link.xmit);
+
+  SYS_ARCH_UNPROTECT(lev);
+
+  return(RT_EOK);
+}
+
+/**
+ * This function will process all transmit descriptors and free pbufs attached
+ * to any that have been transmitted since we last checked.
+ *
+ * This function is called only from the Ethernet interrupt handler.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return None.
+ */
+static void
+tivaif_process_transmit(tStellarisIF *pIF)
+{
+    tDescriptorList *pDescList;
+    uint32_t ui32NumDescs;
+
+    /* Get a pointer to the transmit descriptor list. */
+    pDescList = pIF->pTxDescList;
+
+    /* Walk the list until we have checked all descriptors or we reach the
+     * write pointer or find a descriptor that the hardware is still working
+     * on.
+     */
+    for(ui32NumDescs = 0; ui32NumDescs < pDescList->ui32NumDescs; ui32NumDescs++)
+    {
+        /* Has the buffer attached to this descriptor been transmitted? */
+        if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+           DES0_TX_CTRL_OWN)
+        {
+            /* No - we're finished. */
+            break;
+        }
+
+        /* Does this descriptor have a buffer attached to it? */
+        if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
+        {
+            /* Yes - free it if it's not marked as an intermediate pbuf */
+            if(!((uint32_t)(pDescList->pDescriptors[pDescList->ui32Read].pBuf) & 1))
+            {
+                pbuf_free(pDescList->pDescriptors[pDescList->ui32Read].pBuf);
+                DRIVER_STATS_INC(TXBufFreedCount);
+            }
+            pDescList->pDescriptors[pDescList->ui32Read].pBuf = NULL;
+        }
+        else
+        {
+            /* If the descriptor has no buffer, we are finished. */
+            break;
+        }
+
+        /* Move on to the next descriptor. */
+        pDescList->ui32Read++;
+        if(pDescList->ui32Read == pDescList->ui32NumDescs)
+        {
+            pDescList->ui32Read = 0;
+        }
+    }
+}
+
+/**
+ * This function will process all receive descriptors that contain newly read
+ * data and pass complete frames up the lwIP stack as they are found.  The
+ * timestamp of the packet will be placed into the pbuf structure if PTPD is
+ * enabled.
+ *
+ * This function is called only from the Ethernet interrupt handler.
+ *
+ * @param psNetif the lwip network interface structure for this ethernetif
+ * @return None.
+ */
+static void
+tivaif_receive(net_device_t dev)
+{
+  tDescriptorList *pDescList;
+  tStellarisIF *pIF;
+  struct pbuf *pBuf;
+  uint32_t ui32DescEnd;
+
+  /* Get a pointer to our state data */
+  pIF = dev->dma_if;
+
+  /* Get a pointer to the receive descriptor list. */
+  pDescList = pIF->pRxDescList;
+
+  /* Start with a NULL pbuf so that we don't try to link chain the first
+   * time round.
+   */
+  pBuf = NULL;
+
+  /* Determine where we start and end our walk of the descriptor list */
+   ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1);
+
+  /* Step through the descriptors that are marked for CPU attention. */
+  while(pDescList->ui32Read != ui32DescEnd)
+  {
+      /* Does the current descriptor have a buffer attached to it? */
+      if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
+      {
+          /* Yes - determine if the host has filled it yet. */
+          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+             DES0_RX_CTRL_OWN)
+          {
+              /* The DMA engine still owns the descriptor so we are finished */
+              break;
+          }
+
+          DRIVER_STATS_INC(RXBufReadCount);
+
+          /* If this descriptor contains the end of the packet, fix up the
+           * buffer size accordingly.
+           */
+          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+             DES0_RX_STAT_LAST_DESC)
+          {
+              /* This is the last descriptor for the frame so fix up the
+               * length.  It is safe for us to modify the internal fields
+               * directly here (rather than calling pbuf_realloc) since we
+               * know each of these pbufs is never chained.
+               */
+              pDescList->pDescriptors[pDescList->ui32Read].pBuf->len =
+                       (pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+                        DES0_RX_STAT_FRAME_LENGTH_M) >>
+                        DES0_RX_STAT_FRAME_LENGTH_S;
+              pDescList->pDescriptors[pDescList->ui32Read].pBuf->tot_len =
+                        pDescList->pDescriptors[pDescList->ui32Read].pBuf->len;
+          }
+
+          if(pBuf)
+          {
+              /* Link this pbuf to the last one we looked at since this buffer
+               * is a continuation of an existing frame (split across mui32tiple
+               * pbufs).  Note that we use pbuf_cat() here rather than
+               * pbuf_chain() since we don't want to increase the reference
+               * count of either pbuf - we only want to link them together.
+               */
+              pbuf_cat(pBuf, pDescList->pDescriptors[pDescList->ui32Read].pBuf);
+              pDescList->pDescriptors[pDescList->ui32Read].pBuf = pBuf;
+          }
+
+          /* Remember the buffer associated with this descriptor. */
+          pBuf = pDescList->pDescriptors[pDescList->ui32Read].pBuf;
+
+          /* Is this the last descriptor for the current frame? */
+          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+             DES0_RX_STAT_LAST_DESC)
+          {
+              /* Yes - does the frame contain errors? */
+              if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+                 DES0_RX_STAT_ERR)
+              {
+                  /* This is a bad frame so discard it and update the relevant
+                   * statistics.
+                   */
+                  LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: packet error\n"));
+                  pbuf_free(pBuf);
+                  LINK_STATS_INC(link.drop);
+                  DRIVER_STATS_INC(RXPacketErrCount);
+              }
+              else
+              {
+                  /* This is a good frame so pass it up the stack. */
+                  LINK_STATS_INC(link.recv);
+                  DRIVER_STATS_INC(RXPacketReadCount);
+
+#if LWIP_PTPD
+                  /* Place the timestamp in the PBUF if PTPD is enabled */
+                  pBuf->time_s =
+                       pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeHi;
+                  pBuf->time_ns =
+                       pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeLo;
+#endif
+
+#if NO_SYS
+                  if(ethernet_input(pBuf, psNetif) != RT_EOK)
+                  {
+#else
+                  //if(tcpip_input(pBuf, psNetif) != RT_EOK)
+				  if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) ||
+					(eth_device_ready(&(dev->parent)) != RT_EOK))
+                  {
+#endif
+                      /* drop the packet */
+                      LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_input: input error\n"));
+                      pbuf_free(pBuf);
+
+                      /* Adjust the link statistics */
+                      LINK_STATS_INC(link.memerr);
+                      LINK_STATS_INC(link.drop);
+                      DRIVER_STATS_INC(RXPacketCBErrCount);
+                  }
+
+                  /* We're finished with this packet so make sure we don't try
+                   * to link the next buffer to it.
+                   */
+                  pBuf = NULL;
+              }
+          }
+      }
+
+      /* Allocate a new buffer for this descriptor */
+      pDescList->pDescriptors[pDescList->ui32Read].pBuf = pbuf_alloc(PBUF_RAW,
+                                                        PBUF_POOL_BUFSIZE,
+                                                        PBUF_POOL);
+      pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count =
+                                                        DES1_RX_CTRL_CHAINED;
+      if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
+      {
+          /* We got a buffer so fill in the payload pointer and size. */
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 =
+                              pDescList->pDescriptors[pDescList->ui32Read].pBuf->payload;
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count |=
+                              (pDescList->pDescriptors[pDescList->ui32Read].pBuf->len <<
+                               DES1_RX_CTRL_BUFF1_SIZE_S);
+
+          /* Give this descriptor back to the hardware */
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus =
+                              DES0_RX_CTRL_OWN;
+      }
+      else
+      {
+          LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: pbuf_alloc error\n"));
+
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = 0;
+
+          /* Update the stats to show we coui32dn't allocate a pbuf. */
+          DRIVER_STATS_INC(RXNoBufCount);
+          LINK_STATS_INC(link.memerr);
+
+          /* Stop parsing here since we can't leave a broken descriptor in
+           * the chain.
+           */
+          break;
+      }
+
+      /* Move on to the next descriptor in the chain, taking care to wrap. */
+      pDescList->ui32Read++;
+      if(pDescList->ui32Read == pDescList->ui32NumDescs)
+      {
+          pDescList->ui32Read = 0;
+      }
+  }
+}
+
+/**
+ * Process interrupts from the PHY.
+ *
+ * should be called from the Stellaris Ethernet Interrupt Handler.  This
+ * function will read packets from the Stellaris Ethernet fifo and place them
+ * into a pbuf queue.  If the transmitter is idle and there is at least one packet
+ * on the transmit queue, it will place it in the transmit fifo and start the
+ * transmitter.
+ *
+ */
+void
+tivaif_process_phy_interrupt(net_device_t dev)
+{
+    uint16_t ui16Val, ui16Status;
+    uint32_t ui32Config, ui32Mode, ui32RxMaxFrameSize;
+
+    /* Read the PHY interrupt status.  This clears all interrupt sources.
+     * Note that we are only enabling sources in EPHY_MISR1 so we don't
+     * read EPHY_MISR2.
+     */
+    ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
+
+	/* 
+	 * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register
+	 */
+		EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR);
+    /* Read the current PHY status. */
+    ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS);
+
+    /* Has the link status changed? */
+    if(ui16Val & EPHY_MISR1_LINKSTAT)
+    {
+        /* Is link up or down now? */
+        if(ui16Status & EPHY_STS_LINK)
+        {
+            /* Tell lwIP the link is up. */
+#if NO_SYS
+            netif_set_link_up(psNetif);
+#else
+            //tcpip_callback((tcpip_callback_fn)netif_set_link_up, psNetif);
+			eth_device_linkchange(&(dev->parent), RT_TRUE);
+#endif
+
+            /* In this case we drop through since we may need to reconfigure
+             * the MAC depending upon the speed and half/fui32l-duplex settings.
+             */
+        }
+        else
+        {
+            /* Tell lwIP the link is down */
+#if NO_SYS
+            netif_set_link_down(psNetif);
+#else
+            //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif);
+			eth_device_linkchange(&(dev->parent), RT_FALSE);
+#endif
+        }
+    }
+
+    /* Has the speed or duplex status changed? */
+    if(ui16Val & (EPHY_MISR1_SPEED | EPHY_MISR1_SPEED | EPHY_MISR1_ANC))
+    {
+        /* Get the current MAC configuration. */
+        EMACConfigGet(EMAC0_BASE, &ui32Config, &ui32Mode,
+                        &ui32RxMaxFrameSize);
+
+        /* What speed is the interface running at now?
+         */
+        if(ui16Status & EPHY_STS_SPEED)
+        {
+            /* 10Mbps is selected */
+            ui32Config &= ~EMAC_CONFIG_100MBPS;
+        }
+        else
+        {
+            /* 100Mbps is selected */
+            ui32Config |= EMAC_CONFIG_100MBPS;
+        }
+
+        /* Are we in fui32l- or half-duplex mode? */
+        if(ui16Status & EPHY_STS_DUPLEX)
+        {
+            /* Fui32l duplex. */
+            ui32Config |= EMAC_CONFIG_FULL_DUPLEX;
+        }
+        else
+        {
+            /* Half duplex. */
+            ui32Config &= ~EMAC_CONFIG_FULL_DUPLEX;
+        }
+
+        /* Reconfigure the MAC */
+        EMACConfigSet(EMAC0_BASE, ui32Config, ui32Mode, ui32RxMaxFrameSize);
+    }
+}
+
+/**
+ * Process tx and rx packets at the low-level interrupt.
+ *
+ * should be called from the Stellaris Ethernet Interrupt Handler.  This
+ * function will read packets from the Stellaris Ethernet fifo and place them
+ * into a pbuf queue.  If the transmitter is idle and there is at least one packet
+ * on the transmit queue, it will place it in the transmit fifo and start the
+ * transmitter.
+ *
+ */
+void
+tivaif_interrupt(net_device_t dev, uint32_t ui32Status)
+{
+
+  /* Update our debug interrupt counters. */
+  if(ui32Status & EMAC_INT_NORMAL_INT)
+  {
+      g_ui32NormalInts++;
+  }
+
+  if(ui32Status & EMAC_INT_ABNORMAL_INT)
+  {
+      g_ui32AbnormalInts++;
+  }
+
+  /* Is this an interrupt from the PHY? */
+  if(ui32Status & EMAC_INT_PHY)
+  {
+      tivaif_process_phy_interrupt(dev);
+  }
+
+  /* Process the transmit DMA list, freeing any buffers that have been
+   * transmitted since our last interrupt.
+   */
+  if(ui32Status & EMAC_INT_TRANSMIT)
+  {
+      tivaif_process_transmit(dev->dma_if);
+  }
+
+  /**
+   * Process the receive DMA list and pass all successfui32ly received packets
+   * up the stack.  We also call this function in cases where the receiver has
+   * stalled due to missing buffers since the receive function will attempt to
+   * allocate new pbufs for descriptor entries which have none.
+   */
+  if(ui32Status & (EMAC_INT_RECEIVE | EMAC_INT_RX_NO_BUFFER |
+     EMAC_INT_RX_STOPPED))
+  {
+      tivaif_receive(dev);
+  }
+}
+
+#if NETIF_DEBUG
+/* Print an IP header by using LWIP_DEBUGF
+ * @param p an IP packet, p->payload pointing to the IP header
+ */
+void
+tivaif_debug_print(struct pbuf *p)
+{
+  struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload;
+  u16_t *plen = (u16_t *)p->payload;
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("ETH header:\n"));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Packet Length:%5"U16_F" \n",*plen));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Destination: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n",
+    ethhdr->dest.addr[0],
+    ethhdr->dest.addr[1],
+    ethhdr->dest.addr[2],
+    ethhdr->dest.addr[3],
+    ethhdr->dest.addr[4],
+    ethhdr->dest.addr[5]));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Source: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n",
+    ethhdr->src.addr[0],
+    ethhdr->src.addr[1],
+    ethhdr->src.addr[2],
+    ethhdr->src.addr[3],
+    ethhdr->src.addr[4],
+    ethhdr->src.addr[5]));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Packet Type:0x%04"U16_F" \n", ethhdr->type));
+}
+#endif /* NETIF_DEBUG */
+
+void lwIPEthernetIntHandler(void)
+{
+    uint32_t ui32Status;
+#ifdef DEF_INT_TEMPSTAMP
+    uint32_t ui32TimerStatus;
+#endif
+    //
+    // Read and Clear the interrupt.
+    //
+    ui32Status = MAP_EMACIntStatus(EMAC0_BASE, true);
+
+    //
+    // If the interrupt really came from the Ethernet and not our
+    // timer, clear it.
+    //
+    if(ui32Status)
+    {
+        MAP_EMACIntClear(EMAC0_BASE, ui32Status);
+    }
+#ifdef DEF_INT_TEMPSTAMP
+    //
+    // Check to see whether a hardware timer interrupt has been reported.
+    //
+    if(ui32Status & EMAC_INT_TIMESTAMP)
+    {
+        //
+        // Yes - read and clear the timestamp interrupt status.
+        //
+        ui32TimerStatus = EMACTimestampIntStatus(EMAC0_BASE);
+
+        //
+        // If a timer interrupt handler has been registered, call it.
+        //
+        if(g_pfnTimerHandler)
+        {
+            g_pfnTimerHandler(EMAC0_BASE, ui32TimerStatus);
+        }
+    }
+#endif
+    //
+    // The handling of the interrupt is different based on the use of a RTOS.
+    //
+
+    //
+    // No RTOS is being used.  If a transmit/receive interrupt was active,
+    // run the low-level interrupt handler.
+    //
+    if(ui32Status)
+    {
+        tivaif_interrupt(eth_dev, ui32Status);
+    }
+
+    //
+    // Service the lwIP timers.
+    //
+    //lwIPServiceTimers();
+}
+
+
+// OUI:00-12-37 (hex) Texas Instruments, only for test 
+static int tiva_eth_mac_addr_init(void)
+{
+	int retVal =0; 
+	uint32_t ulUser[2];
+	uint8_t mac_addr[6];
+	
+	MAP_FlashUserGet(&ulUser[0], &ulUser[1]);
+	if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff))
+	{
+		rt_kprintf("Fail to get mac address from eeprom.\n");
+		rt_kprintf("Using default mac address\n");
+		// OUI:00-12-37 (hex) Texas Instruments, only for test 
+		// Configure the hardware MAC address 
+		ulUser[0] = 0x00371200;
+		ulUser[1] = 0x00563412;
+		//FlashUserSet(ulUser0, ulUser1); 
+		retVal =-1;
+	}
+	
+	
+	//Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
+	//address needed to program the hardware registers, then program the MAC
+	//address into the Ethernet Controller registers.
+	
+	mac_addr[0] = ((ulUser[0] >>  0) & 0xff);
+	mac_addr[1] = ((ulUser[0] >>  8) & 0xff);
+	mac_addr[2] = ((ulUser[0] >> 16) & 0xff);
+	mac_addr[3] = ((ulUser[1] >>  0) & 0xff);
+	mac_addr[4] = ((ulUser[1] >>  8) & 0xff);
+	mac_addr[5] = ((ulUser[1] >> 16) & 0xff);
+	
+	//
+    // Program the hardware with its MAC address (for filtering).
+    //
+    MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr);
+	return retVal;
+}
+
+#ifndef EMAC_PHY_CONFIG
+#define EMAC_PHY_CONFIG         (EMAC_PHY_TYPE_INTERNAL |                     \
+                                 EMAC_PHY_INT_MDIX_EN |                       \
+                                 EMAC_PHY_AN_100B_T_FULL_DUPLEX)
+#endif
+
+ void tiva_eth_lowlevel_init(void)
+{
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
+    //
+    // PF1/PK4/PK6 are used for Ethernet LEDs.
+    //
+    MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0);
+    MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1);
+    GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0);
+    GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4);
+	
+    //
+    // Enable the ethernet peripheral.
+    //
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
+    MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
+    //
+    // Enable the internal PHY if it's present and we're being
+    // asked to use it.
+    //
+    if((EMAC_PHY_CONFIG & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
+    {
+        //
+        // We've been asked to configure for use with the internal
+        // PHY.  Is it present?
+        //
+        if(SysCtlPeripheralPresent(SYSCTL_PERIPH_EPHY0))
+        {
+            //
+            // Yes - enable and reset it.
+            //
+            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
+            MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
+        }
+        else
+        {
+            //
+            // Internal PHY is not present on this part so hang here.
+            //
+			rt_kprintf("Internal PHY is not present on this part.\n");
+            while(1)
+            {
+            }
+        }
+    }
+
+    //
+    // Wait for the MAC to come out of reset.
+    //
+    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
+    {
+    }
+
+    //
+    // Configure for use with whichever PHY the user requires.
+    //
+    MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG);
+
+    //
+    // Initialize the MAC and set the DMA mode.
+    //
+    MAP_EMACInit(EMAC0_BASE, 120000000, //system clock = 120MHz
+                 EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED,
+                 4, 4, 0);
+
+    //
+    // Set MAC configuration options.
+    //
+    MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX |
+                                   EMAC_CONFIG_CHECKSUM_OFFLOAD |
+                                   EMAC_CONFIG_7BYTE_PREAMBLE |
+                                   EMAC_CONFIG_IF_GAP_96BITS |
+                                   EMAC_CONFIG_USE_MACADDR0 |
+                                   EMAC_CONFIG_SA_FROM_DESCRIPTOR |
+                                   EMAC_CONFIG_BO_LIMIT_1024),
+                      (EMAC_MODE_RX_STORE_FORWARD |
+                       EMAC_MODE_TX_STORE_FORWARD |
+                       EMAC_MODE_TX_THRESHOLD_64_BYTES |
+                       EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);
+		   
+	EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler);
+
+}
+
+static rt_err_t eth_dev_init(rt_device_t device)
+{
+	net_device_t net_dev = (net_device_t)device;
+	struct netif *psNetif = (net_dev->parent.netif);
+	
+	LWIP_ASSERT("psNetif != NULL", (psNetif != NULL));
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  psNetif->hostname = "t4mc";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000);
+  
+  net_dev->dma_if = &g_StellarisIFData;
+
+  /* Remember our MAC address. */
+  g_StellarisIFData.ethaddr = (struct eth_addr *)&(psNetif->hwaddr[0]);
+
+  /* Initialize the hardware */
+  tivaif_hwinit(psNetif);
+  return RT_EOK;
+}
+
+/* control the interface */
+static rt_err_t eth_dev_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	switch(cmd)
+	{
+	case NIOCTL_GADDR:
+		/* get mac address */
+		if(args) 
+			MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args);
+		else 
+			return -RT_ERROR;
+		break;
+
+	default :
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/* Open the interface */
+static rt_err_t eth_dev_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+/* Close the interface */
+static rt_err_t eth_dev_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+/* Read */
+static rt_size_t eth_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+/* Write */
+static rt_size_t eth_dev_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_err_t eth_dev_tx(rt_device_t dev, struct pbuf *p)
+{
+	return tivaif_transmit((net_device_t)dev, p);
+}
+
+static struct pbuf* eth_dev_rx(rt_device_t dev)
+{
+	rt_err_t result;
+	rt_uint32_t temp =0;
+	net_device_t net_dev = (net_device_t)dev;
+	result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO);
+	
+	return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL;
+}
+
+rt_err_t rt_hw_tiva_eth_init(void)
+{
+	rt_err_t result;
+
+	/* Clock GPIO and etc */
+	tiva_eth_lowlevel_init(); 
+	tiva_eth_mac_addr_init();
+
+	/* init rt-thread device interface */
+	eth_dev->parent.parent.init     = eth_dev_init;
+	eth_dev->parent.parent.open     = eth_dev_open;
+	eth_dev->parent.parent.close    = eth_dev_close;
+	eth_dev->parent.parent.read     = eth_dev_read;
+	eth_dev->parent.parent.write    = eth_dev_write;
+	eth_dev->parent.parent.control  = eth_dev_control;
+	eth_dev->parent.eth_rx          = eth_dev_rx;
+	eth_dev->parent.eth_tx          = eth_dev_tx;
+	
+	result = rt_mb_init(&eth_rx_pbuf_mb, "epbuf",
+                        &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4,
+                        RT_IPC_FLAG_FIFO);
+	RT_ASSERT(result == RT_EOK);
+	eth_dev->rx_pbuf_mb = &eth_rx_pbuf_mb;
+	
+	
+	result = eth_device_init(&(eth_dev->parent), "e0");
+	return result;
+}
+
+#ifdef RT_USING_FINSH
+#include "finsh.h"
+void PHY_Read(uint8_t addr)
+{
+	uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr);
+	rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data);
+}
+FINSH_FUNCTION_EXPORT(PHY_Read, (add));
+
+void PHY_Write(uint8_t addr , uint16_t data)
+{
+   EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, addr, data);
+	rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data);
+}
+FINSH_FUNCTION_EXPORT(PHY_Write, (add, data));
+
+void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, 
+                uint8_t addr3, uint8_t addr4, uint8_t addr5)
+{
+	uint32_t ulUser[2];
+	ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0;
+	ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3;
+	
+	MAP_FlashUserSet(ulUser[0], ulUser[1]);
+	MAP_FlashUserSave();
+	rt_kprintf("Save to EEPROM. please reboot.");
+}
+FINSH_FUNCTION_EXPORT(PHY_SetAdd, (add0-add5));
+#endif //RT_USING_FINSH
diff --git a/bsp/tm4c129x/drivers/drv_eth.h b/bsp/tm4c129x/drivers/drv_eth.h
new file mode 100644
index 0000000000..5f27139d5f
--- /dev/null
+++ b/bsp/tm4c129x/drivers/drv_eth.h
@@ -0,0 +1,20 @@
+/*
+ * File      : drv_eth.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-25     ArdaFu       Port to TM4C129X
+ */
+ 
+#ifndef __TIVA_ETH_H__
+#define __TIVA_ETH_H__
+
+rt_err_t rt_hw_tiva_eth_init(void);
+
+#endif
diff --git a/bsp/tm4c129x/libraries/driverlib/emac.c b/bsp/tm4c129x/libraries/driverlib/emac.c
index dcedfdf657..a9e5d14a65 100644
--- a/bsp/tm4c129x/libraries/driverlib/emac.c
+++ b/bsp/tm4c129x/libraries/driverlib/emac.c
@@ -2917,6 +2917,7 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
     //
     HWREG(ui32Base + EMAC_O_MIIADDR) =
         ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
+					EMAC_MIIADDR_CR_100_150 |
          (ui8RegAddr << EMAC_MIIADDR_MII_S) |
          (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
 

From 1e396417d82b39b7d648eedc230c2e08a62a50de Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Fri, 25 Jul 2014 19:02:37 +0800
Subject: [PATCH 71/86] Revert "[BSP] tm4c129x:"

This reverts commit 666d12988a2ab3fc9eb878e3b52cb083c85e6dbe.
---
 bsp/lm4f232/rtconfig.h                  |    2 +-
 bsp/tm4c129x/applications/application.c |    6 -
 bsp/tm4c129x/applications/board.c       |    2 +-
 bsp/tm4c129x/drivers/drv_eth.c          | 1446 -----------------------
 bsp/tm4c129x/drivers/drv_eth.h          |   20 -
 bsp/tm4c129x/libraries/driverlib/emac.c |    1 -
 6 files changed, 2 insertions(+), 1475 deletions(-)
 delete mode 100644 bsp/tm4c129x/drivers/drv_eth.c
 delete mode 100644 bsp/tm4c129x/drivers/drv_eth.h

diff --git a/bsp/lm4f232/rtconfig.h b/bsp/lm4f232/rtconfig.h
index 586b4adac2..723077dd50 100644
--- a/bsp/lm4f232/rtconfig.h
+++ b/bsp/lm4f232/rtconfig.h
@@ -93,7 +93,7 @@
 #define DFS_FD_MAX					4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
-#define RT_USING_LWIP
+/* #define RT_USING_LWIP */
 /* LwIP uses RT-Thread Memory Management */
 #define RT_LWIP_USING_RT_MEM
 /* Enable ICMP protocol*/
diff --git a/bsp/tm4c129x/applications/application.c b/bsp/tm4c129x/applications/application.c
index 984e622157..80f58b6ed8 100644
--- a/bsp/tm4c129x/applications/application.c
+++ b/bsp/tm4c129x/applications/application.c
@@ -16,9 +16,6 @@
 #include <board.h>
 #include <components.h>
 
-#ifdef RT_USING_LWIP
-#include "drv_eth.h"
-#endif
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
@@ -27,9 +24,6 @@ void rt_init_thread_entry(void *parameter)
 #ifdef RT_USING_FINSH
     finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-#ifdef RT_USING_LWIP
-    rt_hw_tiva_eth_init();
-#endif
 }
 
 int rt_application_init(void)
diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c
index 2953e76c58..c638369a5a 100644
--- a/bsp/tm4c129x/applications/board.c
+++ b/bsp/tm4c129x/applications/board.c
@@ -92,7 +92,7 @@ void rt_hw_board_init()
     
     /*init uart device*/		
     rt_hw_uart_init();
-    //redirect RTT stdio to CONSOLE device
+		//redirect RTT stdio to CONSOLE device
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
     //
     // Enable interrupts to the processor.
diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c
deleted file mode 100644
index ea4813be00..0000000000
--- a/bsp/tm4c129x/drivers/drv_eth.c
+++ /dev/null
@@ -1,1446 +0,0 @@
-/*
- * File      : drv_eth.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-07-25     ArdaFu       Port to TM4C129X
- */
-
-/**
- * @file - tivaif.c
- * lwIP Ethernet interface for Stellaris LM4F Devices
- *
- */
-
-/**
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICui32AR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-/**
- * Copyright (c) 2008-2012 Texas Instruments Incorporated
- *
- * This file is derived from the ``ethernetif.c'' skeleton Ethernet network
- * interface driver for lwIP.
- *
- */
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include <lwip/stats.h>
-#include <lwip/snmp.h>
-#include "lwip/tcpip.h"
-#include "netif/etharp.h"
-#include "netif/ppp_oe.h"
-
-
-/**
- * Sanity Check:  This interface driver will NOT work if the following defines
- * are incorrect.
- *
- */
-#if (PBUF_LINK_HLEN != 16)
-#error "PBUF_LINK_HLEN must be 16 for this interface driver!"
-#endif
-#if (ETH_PAD_SIZE != 0)
-#error "ETH_PAD_SIZE must be 0 for this interface driver!"
-#endif
-#if (!SYS_LIGHTWEIGHT_PROT)
-#error "SYS_LIGHTWEIGHT_PROT must be enabled for this interface driver!"
-#endif
-
-/**
- * Set the physical address of the PHY we will be using if this is not
- * specified in lwipopts.h.  We assume 0 for the internal PHY.
- */
-#ifndef PHY_PHYS_ADDR
-#define PHY_PHYS_ADDR 0
-#endif
-
-#if 0
-#ifndef EMAC_PHY_CONFIG
-#define EMAC_PHY_CONFIG (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN |      \
-                         EMAC_PHY_AN_100B_T_FULL_DUPLEX)
-#endif
-#endif
-
-/**
- * If necessary, set the defaui32t number of transmit and receive DMA descriptors
- * used by the Ethernet MAC.
- *
- */
-#ifndef NUM_RX_DESCRIPTORS
-#define NUM_RX_DESCRIPTORS 4
-#endif
-
-#ifndef NUM_TX_DESCRIPTORS
-#define NUM_TX_DESCRIPTORS 8
-#endif
-
-/**
- * Setup processing for PTP (IEEE-1588).
- *
- */
-#if LWIP_PTPD
-extern uint32_t g_ui32SysClk;
-extern uint32_t g_ui32PTPTickRate;
-extern void lwIPHostGetTime(u32_t *time_s, u32_t *time_ns);
-#endif
-
-/**
- * Stellaris DriverLib Header Files required for this interface driver.
- *
- */
-#include <stdint.h>
-#include <stdbool.h>
-#include "inc/hw_emac.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-
-#include "driverlib/emac.h"
-#include "driverlib/interrupt.h"
-#include "driverlib/sysctl.h"
-#include "driverlib/flash.h"
-#include "driverlib/interrupt.h"
-
-#include "driverlib/pin_map.h"
-#include "driverlib/rom_map.h"
-#include "driverlib/gpio.h"
-
-#include <netif/ethernetif.h>
-#include "lwipopts.h"
-#include "drv_eth.h"
-
-/**
- * A structure used to keep track of driver state and error counts.
- */
-typedef struct {
-    uint32_t ui32TXCount;
-    uint32_t ui32TXCopyCount;
-    uint32_t ui32TXCopyFailCount;
-    uint32_t ui32TXNoDescCount;
-    uint32_t ui32TXBufQueuedCount;
-    uint32_t ui32TXBufFreedCount;
-    uint32_t ui32RXBufReadCount;
-    uint32_t ui32RXPacketReadCount;
-    uint32_t ui32RXPacketErrCount;
-    uint32_t ui32RXPacketCBErrCount;
-    uint32_t ui32RXNoBufCount;
-}
-tDriverStats;
-
-tDriverStats g_sDriverStats;
-
-#ifdef DEBUG
-/**
- * Note: This rather weird construction where we invoke the macro with the
- * name of the field minus its Hungarian prefix is a workaround for a problem
- * experienced with GCC which does not like concatenating tokens after an
- * operator, specifically '.' or '->', in a macro.
- */
-#define DRIVER_STATS_INC(x) do{ g_sDriverStats.ui32##x++; } while(0)
-#define DRIVER_STATS_DEC(x) do{ g_sDriverStats.ui32##x--; } while(0)
-#define DRIVER_STATS_ADD(x, inc) do{ g_sDriverStats.ui32##x += (inc); } while(0)
-#define DRIVER_STATS_SUB(x, dec) do{ g_sDriverStats.ui32##x -= (dec); } while(0)
-#else
-#define DRIVER_STATS_INC(x)
-#define DRIVER_STATS_DEC(x)
-#define DRIVER_STATS_ADD(x, inc)
-#define DRIVER_STATS_SUB(x, dec)
-#endif
-
-/**
- *  Helper struct holding a DMA descriptor and the pbuf it currently refers
- *  to.
- */
-typedef struct {
-  tEMACDMADescriptor Desc;
-  struct pbuf *pBuf;
-} tDescriptor;
-
-typedef struct {
-    tDescriptor *pDescriptors;
-    uint32_t ui32NumDescs;
-    uint32_t ui32Read;
-    uint32_t ui32Write;
-} tDescriptorList;
-
-/**
- * Helper struct to hold private data used to operate your ethernet interface.
- * Keeping the ethernet address of the MAC in this struct is not necessary
- * as it is already kept in the struct netif.
- * But this is only an example, anyway...
- */
-typedef struct {
-  struct eth_addr *ethaddr;
-  /* Add whatever per-interface state that is needed here. */
-  tDescriptorList *pTxDescList;
-  tDescriptorList *pRxDescList;
-} tStellarisIF;
-
-/**
- * Global variable for this interface's private data.  Needed to allow
- * the interrupt handlers access to this information outside of the
- * context of the lwIP netif.
- *
- */
-tDescriptor g_pTxDescriptors[NUM_TX_DESCRIPTORS];
-tDescriptor g_pRxDescriptors[NUM_RX_DESCRIPTORS];
-tDescriptorList g_TxDescList = {
-    g_pTxDescriptors, NUM_TX_DESCRIPTORS, 0, 0
-};
-tDescriptorList g_RxDescList = {
-    g_pRxDescriptors, NUM_RX_DESCRIPTORS, 0, 0
-};
-static tStellarisIF g_StellarisIFData = {
-    0, &g_TxDescList, &g_RxDescList
-};
-
-/**
- * Interrupt counters (for debug purposes).
- */
-volatile uint32_t g_ui32NormalInts;
-volatile uint32_t g_ui32AbnormalInts;
-
-/**
- * A macro which determines whether a pointer is within the SRAM address
- * space and, hence, points to a buffer that the Ethernet MAC can directly
- * DMA from.
- */
-#define PTR_SAFE_FOR_EMAC_DMA(ptr) (((uint32_t)(ptr) >= 0x2000000) &&   \
-                                    ((uint32_t)(ptr) < 0x20070000))
-
-
-typedef struct 
-{
-	/* inherit from ethernet device */
-	struct eth_device parent;
-	tStellarisIF* dma_if;
-	/* for rx_thread async get pbuf */
-	rt_mailbox_t rx_pbuf_mb;
-} net_device;
-typedef net_device* net_device_t; 
-
-static char               rx_pbuf_mb_pool[8*4];
-static struct rt_mailbox  eth_rx_pbuf_mb;
-static net_device         eth_dev_entry;
-static net_device_t       eth_dev = &eth_dev_entry;
-
-/**
- * Initialize the transmit and receive DMA descriptor lists.
- */
-void
-InitDMADescriptors(void)
-{
-    uint32_t ui32Loop;
-
-    /* Transmit list -  mark all descriptors as not owned by the hardware */
-   for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++)
-   {
-       g_pTxDescriptors[ui32Loop].pBuf = (struct pbuf *)0;
-       g_pTxDescriptors[ui32Loop].Desc.ui32Count = 0;
-       g_pTxDescriptors[ui32Loop].Desc.pvBuffer1 = 0;
-       g_pTxDescriptors[ui32Loop].Desc.DES3.pLink =
-               ((ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ?
-               &g_pTxDescriptors[0].Desc : &g_pTxDescriptors[ui32Loop + 1].Desc);
-       g_pTxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_TX_CTRL_INTERRUPT |
-               DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_IP_ALL_CKHSUMS;
-
-   }
-
-   g_TxDescList.ui32Read = 0;
-   g_TxDescList.ui32Write = 0;
-
-
-   /* Receive list -  tag each descriptor with a pbuf and set all fields to
-    * allow packets to be received.
-    */
-  for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++)
-  {
-      g_pRxDescriptors[ui32Loop].pBuf = pbuf_alloc(PBUF_RAW, PBUF_POOL_BUFSIZE,
-                                                 PBUF_POOL);
-      g_pRxDescriptors[ui32Loop].Desc.ui32Count = DES1_RX_CTRL_CHAINED;
-      if(g_pRxDescriptors[ui32Loop].pBuf)
-      {
-          /* Set the DMA to write directly into the pbuf payload. */
-          g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 =
-                  g_pRxDescriptors[ui32Loop].pBuf->payload;
-          g_pRxDescriptors[ui32Loop].Desc.ui32Count |=
-             (g_pRxDescriptors[ui32Loop].pBuf->len << DES1_RX_CTRL_BUFF1_SIZE_S);
-          g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_RX_CTRL_OWN;
-      }
-      else
-      {
-          LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_init: pbuf_alloc error\n"));
-
-          /* No pbuf available so leave the buffer pointer empty. */
-          g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = 0;
-          g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = 0;
-      }
-      g_pRxDescriptors[ui32Loop].Desc.DES3.pLink =
-              ((ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ?
-              &g_pRxDescriptors[0].Desc : &g_pRxDescriptors[ui32Loop + 1].Desc);
-  }
-
-  g_TxDescList.ui32Read = 0;
-  g_TxDescList.ui32Write = 0;
-
-  //
-  // Set the descriptor pointers in the hardware.
-  //
-  EMACRxDMADescriptorListSet(EMAC0_BASE, &g_pRxDescriptors[0].Desc);
-  EMACTxDMADescriptorListSet(EMAC0_BASE, &g_pTxDescriptors[0].Desc);
-}
-
-/**
- * In this function, the hardware should be initialized.
- * Called from tivaif_init().
- *
- * @param netif the already initialized lwip network interface structure
- *        for this ethernetif
- */
-static void
-tivaif_hwinit(struct netif *psNetif)
-{
-  uint16_t ui16Val;
-
-  /* Initialize the DMA descriptors. */
-  InitDMADescriptors();
-
-  /* Clear any stray PHY interrupts that may be set. */
-  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
-  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2);
-
-  /* Configure and enable the link status change interrupt in the PHY. */
-  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR);
-  ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT);
-  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val);
-  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN |
-               EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN));
-
-  /* Read the PHY interrupt status to clear any stray events. */
-  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
-
-  /**
-   * Set MAC filtering options.  We receive all broadcast and mui32ticast
-   * packets along with those addressed specifically for us.
-   */
-  EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_HASH_AND_PERFECT |
-                     EMAC_FRMFILTER_PASS_MULTICAST));
-
-#if LWIP_PTPD
-  //
-  // Enable timestamping on all received packets.
-  //
-  // We set the fine clock adjustment mode and configure the subsecond
-  // increment to half the 25MHz PTPD clock.  This will give us maximum control
-  // over the clock rate adjustment and keep the arithmetic easy later.  It
-  // should be possible to synchronize with higher accuracy than this with
-  // appropriate juggling of the subsecond increment count and the addend
-  // register value, though.
-  //
-  EMACTimestampConfigSet(EMAC0_BASE, (EMAC_TS_ALL_RX_FRAMES |
-                         EMAC_TS_DIGITAL_ROLLOVER |
-                         EMAC_TS_PROCESS_IPV4_UDP | EMAC_TS_ALL |
-                         EMAC_TS_PTP_VERSION_1 | EMAC_TS_UPDATE_FINE),
-                         (1000000000 / (25000000 / 2)));
-  EMACTimestampAddendSet(EMAC0_BASE, 0x80000000);
-  EMACTimestampEnable(EMAC0_BASE);
-#endif
-
-  /* Clear any pending MAC interrupts. */
-  EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false));
-
-  /* Enable the Ethernet MAC transmitter and receiver. */
-  EMACTxEnable(EMAC0_BASE);
-  EMACRxEnable(EMAC0_BASE);
-
-  /* Enable the Ethernet RX and TX interrupt source. */
-  EMACIntEnable(EMAC0_BASE, (EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT |
-                EMAC_INT_TX_STOPPED | EMAC_INT_RX_NO_BUFFER |
-                EMAC_INT_RX_STOPPED | EMAC_INT_PHY));
-
-  /* Enable the Ethernet interrupt. */
-  IntEnable(INT_EMAC0);
-
-  /* Enable all processor interrupts. */
-  IntMasterEnable();
-
-  /* Tell the PHY to start an auto-negotiation cycle. */
-  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN |
-               EPHY_BMCR_RESTARTAN));
-}
-
-#ifdef DEBUG
-/**
- * Dump the chain of pbuf pointers to the debug output.
- */
-void
-tivaif_trace_pbuf(const char *pcTitle, struct pbuf *p)
-{
-    LWIP_DEBUGF(NETIF_DEBUG, ("%s %08x (%d, %d)", pcTitle, p, p->tot_len,
-                p->len));
-
-    do
-    {
-        p = p->next;
-        if(p)
-        {
-            LWIP_DEBUGF(NETIF_DEBUG, ("->%08x(%d)", p, p->len));
-        }
-        else
-        {
-            LWIP_DEBUGF(NETIF_DEBUG, ("->%08x", p));
-        }
-
-    } while((p != NULL) && (p->tot_len != p->len));
-
-    LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
-}
-#endif
-
-/**
- * This function is used to check whether a passed pbuf contains only buffers
- * resident in regions of memory that the Ethernet MAC can access.  If any
- * buffers in the chain are outside a directly-DMAable section of memory,
- * the pbuf is copied to SRAM and a different pointer returned.  If all
- * buffers are safe, the pbuf reference count is incremented and the original
- * pointer returned.
- */
-static struct pbuf *
-tivaif_check_pbuf(struct pbuf *p)
-{
-    struct pbuf *pBuf;
-    rt_err_t Err;
-
-    pBuf = p;
-
-#ifdef DEBUG
-    tivaif_trace_pbuf("Original:", p);
-#endif
-
-    /* Walk the list of buffers in the pbuf checking each. */
-    do
-    {
-        /* Does this pbuf's payload reside in memory that the Ethernet DMA
-         * can access?
-         */
-        if(!PTR_SAFE_FOR_EMAC_DMA(pBuf->payload))
-        {
-            /* This buffer is outside the DMA-able memory space so we need
-             * to copy the pbuf.
-             */
-            pBuf = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_POOL);
-
-            /* If we got a new pbuf... */
-            if(pBuf)
-            {
-                /* ...copy the old pbuf into the new one. */
-                Err = pbuf_copy(pBuf, p);
-
-                /* If we failed to copy the pbuf, free the newly allocated one
-                 * and make sure we return a NULL to show a problem.
-                 */
-                if(Err != RT_EOK)
-                {
-                    DRIVER_STATS_INC(TXCopyFailCount);
-                    pbuf_free(pBuf);
-                    pBuf = NULL;
-                }
-                else
-                {
-#ifdef DEBUG
-                    tivaif_trace_pbuf("Copied:", pBuf);
-#endif
-                    DRIVER_STATS_INC(TXCopyCount);
-
-                    /* Reduce the reference count on the original pbuf since
-                     * we're not going to hold on to it after returning from
-                     * tivaif_transmit.  Note that we already bumped
-                     * the reference count at the top of tivaif_transmit.
-                     */
-                    pbuf_free(p);
-                }
-            }
-
-            /* Send back the new pbuf pointer or NULL if an error occurred. */
-            return(pBuf);
-        }
-
-        /* Move on to the next buffer in the queue */
-        pBuf = pBuf->next;
-    }
-    while(pBuf);
-
-    /**
-     * If we get here, the passed pbuf can be safely used without needing to
-     * be copied.
-     */
-    return(p);
-}
-
-/**
- * This function should do the actual transmission of the packet. The packet is
- * contained in the pbuf that is passed to the function. This pbuf might be
- * chained.
- *
- * @param psNetif the lwip network interface structure for this ethernetif
- * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
- * @return RT_EOK if the packet coui32d be sent
- *         an err_t value if the packet coui32dn't be sent
- */
-static rt_err_t
-tivaif_transmit(net_device_t dev, struct pbuf *p)
-{
-  tStellarisIF *pIF;
-  tDescriptor *pDesc;
-  struct pbuf *pBuf;
-  uint32_t ui32NumChained, ui32NumDescs;
-  bool bFirst;
-  SYS_ARCH_DECL_PROTECT(lev);
-
-  LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_transmit 0x%08x, len %d\n", p,
-              p->tot_len));
-
-  /**
-   * This entire function must run within a "critical section" to preserve
-   * the integrity of the transmit pbuf queue.
-   */
-  SYS_ARCH_PROTECT(lev);
-
-  /* Update our transmit attempt counter. */
-  DRIVER_STATS_INC(TXCount);
-
-  /**
-   * Increase the reference count on the packet provided so that we can
-   * hold on to it until we are finished transmitting its content.
-   */
-  pbuf_ref(p);
-
-  /**
-   * Determine whether all buffers passed are within SRAM and, if not, copy
-   * the pbuf into SRAM-resident buffers so that the Ethernet DMA can access
-   * the data.
-   */
-  p = tivaif_check_pbuf(p);
-
-  /* Make sure we still have a valid buffer (it may have been copied) */
-  if(!p)
-  {
-      LINK_STATS_INC(link.memerr);
-      SYS_ARCH_UNPROTECT(lev);
-      return(-RT_ENOMEM);
-  }
-
-  /* Get our state data from the netif structure we were passed. */
-  //pIF = (tStellarisIF *)psNetif->state;
-  pIF = dev->dma_if;
-  
-  /* Make sure that the transmit descriptors are not all in use */
-  pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]);
-  if(pDesc->pBuf)
-  {
-      /**
-       * The current write descriptor has a pbuf attached to it so this
-       * implies that the ring is fui32l. Reject this transmit request with a
-       * memory error since we can't satisfy it just now.
-       */
-      pbuf_free(p);
-      LINK_STATS_INC(link.memerr);
-      DRIVER_STATS_INC(TXNoDescCount);
-      SYS_ARCH_UNPROTECT(lev);
-      return (-RT_ENOMEM);
-  }
-
-  /* How many pbufs are in the chain passed? */
-  ui32NumChained = (uint32_t)pbuf_clen(p);
-
-  /* How many free transmit descriptors do we have? */
-  ui32NumDescs = (pIF->pTxDescList->ui32Read > pIF->pTxDescList->ui32Write) ?
-          (pIF->pTxDescList->ui32Read - pIF->pTxDescList->ui32Write) :
-          ((NUM_TX_DESCRIPTORS - pIF->pTxDescList->ui32Write) +
-           pIF->pTxDescList->ui32Read);
-
-  /* Do we have enough free descriptors to send the whole packet? */
-  if(ui32NumDescs < ui32NumChained)
-  {
-      /* No - we can't transmit this whole packet so return an error. */
-      pbuf_free(p);
-      LINK_STATS_INC(link.memerr);
-      DRIVER_STATS_INC(TXNoDescCount);
-      SYS_ARCH_UNPROTECT(lev);
-      return (-RT_ENOMEM);
-  }
-
-  /* Tag the first descriptor as the start of the packet. */
-  bFirst = true;
-  pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG;
-
-  /* Here, we know we can send the packet so write it to the descriptors */
-  pBuf = p;
-
-  while(ui32NumChained)
-  {
-      /* Get a pointer to the descriptor we will write next. */
-      pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]);
-
-      /* Fill in the buffer pointer and length */
-      pDesc->Desc.ui32Count = (uint32_t)pBuf->len;
-      pDesc->Desc.pvBuffer1 = pBuf->payload;
-
-      /* Tag the first descriptor as the start of the packet. */
-      if(bFirst)
-      {
-          bFirst = false;
-          pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG;
-      }
-      else
-      {
-          pDesc->Desc.ui32CtrlStatus = 0;
-      }
-
-      pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_IP_ALL_CKHSUMS |
-                                     DES0_TX_CTRL_CHAINED);
-
-      /* Decrement our descriptor counter, move on to the next buffer in the
-       * pbuf chain. */
-      ui32NumChained--;
-      pBuf = pBuf->next;
-
-      /* Update the descriptor list write index. */
-      pIF->pTxDescList->ui32Write++;
-      if(pIF->pTxDescList->ui32Write == NUM_TX_DESCRIPTORS)
-      {
-          pIF->pTxDescList->ui32Write = 0;
-      }
-
-      /* If this is the last descriptor, mark it as the end of the packet. */
-      if(!ui32NumChained)
-      {
-          pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_LAST_SEG |
-                                         DES0_TX_CTRL_INTERRUPT);
-
-          /* Tag the descriptor with the original pbuf pointer. */
-          pDesc->pBuf = p;
-      }
-      else
-      {
-          /* Set the lsb of the pbuf pointer.  We use this as a signal that
-           * we should not free the pbuf when we are walking the descriptor
-           * list while processing the transmit interrupt.  We only free the
-           * pbuf when processing the last descriptor used to transmit its
-           * chain.
-           */
-          pDesc->pBuf = (struct pbuf *)((uint32_t)p + 1);
-      }
-
-      DRIVER_STATS_INC(TXBufQueuedCount);
-
-      /* Hand the descriptor over to the hardware. */
-      pDesc->Desc.ui32CtrlStatus |= DES0_TX_CTRL_OWN;
-  }
-
-  /* Tell the transmitter to start (in case it had stopped). */
-  EMACTxDMAPollDemand(EMAC0_BASE);
-
-  /* Update lwIP statistics */
-  LINK_STATS_INC(link.xmit);
-
-  SYS_ARCH_UNPROTECT(lev);
-
-  return(RT_EOK);
-}
-
-/**
- * This function will process all transmit descriptors and free pbufs attached
- * to any that have been transmitted since we last checked.
- *
- * This function is called only from the Ethernet interrupt handler.
- *
- * @param netif the lwip network interface structure for this ethernetif
- * @return None.
- */
-static void
-tivaif_process_transmit(tStellarisIF *pIF)
-{
-    tDescriptorList *pDescList;
-    uint32_t ui32NumDescs;
-
-    /* Get a pointer to the transmit descriptor list. */
-    pDescList = pIF->pTxDescList;
-
-    /* Walk the list until we have checked all descriptors or we reach the
-     * write pointer or find a descriptor that the hardware is still working
-     * on.
-     */
-    for(ui32NumDescs = 0; ui32NumDescs < pDescList->ui32NumDescs; ui32NumDescs++)
-    {
-        /* Has the buffer attached to this descriptor been transmitted? */
-        if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
-           DES0_TX_CTRL_OWN)
-        {
-            /* No - we're finished. */
-            break;
-        }
-
-        /* Does this descriptor have a buffer attached to it? */
-        if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
-        {
-            /* Yes - free it if it's not marked as an intermediate pbuf */
-            if(!((uint32_t)(pDescList->pDescriptors[pDescList->ui32Read].pBuf) & 1))
-            {
-                pbuf_free(pDescList->pDescriptors[pDescList->ui32Read].pBuf);
-                DRIVER_STATS_INC(TXBufFreedCount);
-            }
-            pDescList->pDescriptors[pDescList->ui32Read].pBuf = NULL;
-        }
-        else
-        {
-            /* If the descriptor has no buffer, we are finished. */
-            break;
-        }
-
-        /* Move on to the next descriptor. */
-        pDescList->ui32Read++;
-        if(pDescList->ui32Read == pDescList->ui32NumDescs)
-        {
-            pDescList->ui32Read = 0;
-        }
-    }
-}
-
-/**
- * This function will process all receive descriptors that contain newly read
- * data and pass complete frames up the lwIP stack as they are found.  The
- * timestamp of the packet will be placed into the pbuf structure if PTPD is
- * enabled.
- *
- * This function is called only from the Ethernet interrupt handler.
- *
- * @param psNetif the lwip network interface structure for this ethernetif
- * @return None.
- */
-static void
-tivaif_receive(net_device_t dev)
-{
-  tDescriptorList *pDescList;
-  tStellarisIF *pIF;
-  struct pbuf *pBuf;
-  uint32_t ui32DescEnd;
-
-  /* Get a pointer to our state data */
-  pIF = dev->dma_if;
-
-  /* Get a pointer to the receive descriptor list. */
-  pDescList = pIF->pRxDescList;
-
-  /* Start with a NULL pbuf so that we don't try to link chain the first
-   * time round.
-   */
-  pBuf = NULL;
-
-  /* Determine where we start and end our walk of the descriptor list */
-   ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1);
-
-  /* Step through the descriptors that are marked for CPU attention. */
-  while(pDescList->ui32Read != ui32DescEnd)
-  {
-      /* Does the current descriptor have a buffer attached to it? */
-      if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
-      {
-          /* Yes - determine if the host has filled it yet. */
-          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
-             DES0_RX_CTRL_OWN)
-          {
-              /* The DMA engine still owns the descriptor so we are finished */
-              break;
-          }
-
-          DRIVER_STATS_INC(RXBufReadCount);
-
-          /* If this descriptor contains the end of the packet, fix up the
-           * buffer size accordingly.
-           */
-          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
-             DES0_RX_STAT_LAST_DESC)
-          {
-              /* This is the last descriptor for the frame so fix up the
-               * length.  It is safe for us to modify the internal fields
-               * directly here (rather than calling pbuf_realloc) since we
-               * know each of these pbufs is never chained.
-               */
-              pDescList->pDescriptors[pDescList->ui32Read].pBuf->len =
-                       (pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
-                        DES0_RX_STAT_FRAME_LENGTH_M) >>
-                        DES0_RX_STAT_FRAME_LENGTH_S;
-              pDescList->pDescriptors[pDescList->ui32Read].pBuf->tot_len =
-                        pDescList->pDescriptors[pDescList->ui32Read].pBuf->len;
-          }
-
-          if(pBuf)
-          {
-              /* Link this pbuf to the last one we looked at since this buffer
-               * is a continuation of an existing frame (split across mui32tiple
-               * pbufs).  Note that we use pbuf_cat() here rather than
-               * pbuf_chain() since we don't want to increase the reference
-               * count of either pbuf - we only want to link them together.
-               */
-              pbuf_cat(pBuf, pDescList->pDescriptors[pDescList->ui32Read].pBuf);
-              pDescList->pDescriptors[pDescList->ui32Read].pBuf = pBuf;
-          }
-
-          /* Remember the buffer associated with this descriptor. */
-          pBuf = pDescList->pDescriptors[pDescList->ui32Read].pBuf;
-
-          /* Is this the last descriptor for the current frame? */
-          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
-             DES0_RX_STAT_LAST_DESC)
-          {
-              /* Yes - does the frame contain errors? */
-              if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
-                 DES0_RX_STAT_ERR)
-              {
-                  /* This is a bad frame so discard it and update the relevant
-                   * statistics.
-                   */
-                  LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: packet error\n"));
-                  pbuf_free(pBuf);
-                  LINK_STATS_INC(link.drop);
-                  DRIVER_STATS_INC(RXPacketErrCount);
-              }
-              else
-              {
-                  /* This is a good frame so pass it up the stack. */
-                  LINK_STATS_INC(link.recv);
-                  DRIVER_STATS_INC(RXPacketReadCount);
-
-#if LWIP_PTPD
-                  /* Place the timestamp in the PBUF if PTPD is enabled */
-                  pBuf->time_s =
-                       pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeHi;
-                  pBuf->time_ns =
-                       pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeLo;
-#endif
-
-#if NO_SYS
-                  if(ethernet_input(pBuf, psNetif) != RT_EOK)
-                  {
-#else
-                  //if(tcpip_input(pBuf, psNetif) != RT_EOK)
-				  if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) ||
-					(eth_device_ready(&(dev->parent)) != RT_EOK))
-                  {
-#endif
-                      /* drop the packet */
-                      LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_input: input error\n"));
-                      pbuf_free(pBuf);
-
-                      /* Adjust the link statistics */
-                      LINK_STATS_INC(link.memerr);
-                      LINK_STATS_INC(link.drop);
-                      DRIVER_STATS_INC(RXPacketCBErrCount);
-                  }
-
-                  /* We're finished with this packet so make sure we don't try
-                   * to link the next buffer to it.
-                   */
-                  pBuf = NULL;
-              }
-          }
-      }
-
-      /* Allocate a new buffer for this descriptor */
-      pDescList->pDescriptors[pDescList->ui32Read].pBuf = pbuf_alloc(PBUF_RAW,
-                                                        PBUF_POOL_BUFSIZE,
-                                                        PBUF_POOL);
-      pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count =
-                                                        DES1_RX_CTRL_CHAINED;
-      if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
-      {
-          /* We got a buffer so fill in the payload pointer and size. */
-          pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 =
-                              pDescList->pDescriptors[pDescList->ui32Read].pBuf->payload;
-          pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count |=
-                              (pDescList->pDescriptors[pDescList->ui32Read].pBuf->len <<
-                               DES1_RX_CTRL_BUFF1_SIZE_S);
-
-          /* Give this descriptor back to the hardware */
-          pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus =
-                              DES0_RX_CTRL_OWN;
-      }
-      else
-      {
-          LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: pbuf_alloc error\n"));
-
-          pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = 0;
-
-          /* Update the stats to show we coui32dn't allocate a pbuf. */
-          DRIVER_STATS_INC(RXNoBufCount);
-          LINK_STATS_INC(link.memerr);
-
-          /* Stop parsing here since we can't leave a broken descriptor in
-           * the chain.
-           */
-          break;
-      }
-
-      /* Move on to the next descriptor in the chain, taking care to wrap. */
-      pDescList->ui32Read++;
-      if(pDescList->ui32Read == pDescList->ui32NumDescs)
-      {
-          pDescList->ui32Read = 0;
-      }
-  }
-}
-
-/**
- * Process interrupts from the PHY.
- *
- * should be called from the Stellaris Ethernet Interrupt Handler.  This
- * function will read packets from the Stellaris Ethernet fifo and place them
- * into a pbuf queue.  If the transmitter is idle and there is at least one packet
- * on the transmit queue, it will place it in the transmit fifo and start the
- * transmitter.
- *
- */
-void
-tivaif_process_phy_interrupt(net_device_t dev)
-{
-    uint16_t ui16Val, ui16Status;
-    uint32_t ui32Config, ui32Mode, ui32RxMaxFrameSize;
-
-    /* Read the PHY interrupt status.  This clears all interrupt sources.
-     * Note that we are only enabling sources in EPHY_MISR1 so we don't
-     * read EPHY_MISR2.
-     */
-    ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
-
-	/* 
-	 * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register
-	 */
-		EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR);
-    /* Read the current PHY status. */
-    ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS);
-
-    /* Has the link status changed? */
-    if(ui16Val & EPHY_MISR1_LINKSTAT)
-    {
-        /* Is link up or down now? */
-        if(ui16Status & EPHY_STS_LINK)
-        {
-            /* Tell lwIP the link is up. */
-#if NO_SYS
-            netif_set_link_up(psNetif);
-#else
-            //tcpip_callback((tcpip_callback_fn)netif_set_link_up, psNetif);
-			eth_device_linkchange(&(dev->parent), RT_TRUE);
-#endif
-
-            /* In this case we drop through since we may need to reconfigure
-             * the MAC depending upon the speed and half/fui32l-duplex settings.
-             */
-        }
-        else
-        {
-            /* Tell lwIP the link is down */
-#if NO_SYS
-            netif_set_link_down(psNetif);
-#else
-            //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif);
-			eth_device_linkchange(&(dev->parent), RT_FALSE);
-#endif
-        }
-    }
-
-    /* Has the speed or duplex status changed? */
-    if(ui16Val & (EPHY_MISR1_SPEED | EPHY_MISR1_SPEED | EPHY_MISR1_ANC))
-    {
-        /* Get the current MAC configuration. */
-        EMACConfigGet(EMAC0_BASE, &ui32Config, &ui32Mode,
-                        &ui32RxMaxFrameSize);
-
-        /* What speed is the interface running at now?
-         */
-        if(ui16Status & EPHY_STS_SPEED)
-        {
-            /* 10Mbps is selected */
-            ui32Config &= ~EMAC_CONFIG_100MBPS;
-        }
-        else
-        {
-            /* 100Mbps is selected */
-            ui32Config |= EMAC_CONFIG_100MBPS;
-        }
-
-        /* Are we in fui32l- or half-duplex mode? */
-        if(ui16Status & EPHY_STS_DUPLEX)
-        {
-            /* Fui32l duplex. */
-            ui32Config |= EMAC_CONFIG_FULL_DUPLEX;
-        }
-        else
-        {
-            /* Half duplex. */
-            ui32Config &= ~EMAC_CONFIG_FULL_DUPLEX;
-        }
-
-        /* Reconfigure the MAC */
-        EMACConfigSet(EMAC0_BASE, ui32Config, ui32Mode, ui32RxMaxFrameSize);
-    }
-}
-
-/**
- * Process tx and rx packets at the low-level interrupt.
- *
- * should be called from the Stellaris Ethernet Interrupt Handler.  This
- * function will read packets from the Stellaris Ethernet fifo and place them
- * into a pbuf queue.  If the transmitter is idle and there is at least one packet
- * on the transmit queue, it will place it in the transmit fifo and start the
- * transmitter.
- *
- */
-void
-tivaif_interrupt(net_device_t dev, uint32_t ui32Status)
-{
-
-  /* Update our debug interrupt counters. */
-  if(ui32Status & EMAC_INT_NORMAL_INT)
-  {
-      g_ui32NormalInts++;
-  }
-
-  if(ui32Status & EMAC_INT_ABNORMAL_INT)
-  {
-      g_ui32AbnormalInts++;
-  }
-
-  /* Is this an interrupt from the PHY? */
-  if(ui32Status & EMAC_INT_PHY)
-  {
-      tivaif_process_phy_interrupt(dev);
-  }
-
-  /* Process the transmit DMA list, freeing any buffers that have been
-   * transmitted since our last interrupt.
-   */
-  if(ui32Status & EMAC_INT_TRANSMIT)
-  {
-      tivaif_process_transmit(dev->dma_if);
-  }
-
-  /**
-   * Process the receive DMA list and pass all successfui32ly received packets
-   * up the stack.  We also call this function in cases where the receiver has
-   * stalled due to missing buffers since the receive function will attempt to
-   * allocate new pbufs for descriptor entries which have none.
-   */
-  if(ui32Status & (EMAC_INT_RECEIVE | EMAC_INT_RX_NO_BUFFER |
-     EMAC_INT_RX_STOPPED))
-  {
-      tivaif_receive(dev);
-  }
-}
-
-#if NETIF_DEBUG
-/* Print an IP header by using LWIP_DEBUGF
- * @param p an IP packet, p->payload pointing to the IP header
- */
-void
-tivaif_debug_print(struct pbuf *p)
-{
-  struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload;
-  u16_t *plen = (u16_t *)p->payload;
-
-  LWIP_DEBUGF(NETIF_DEBUG, ("ETH header:\n"));
-  LWIP_DEBUGF(NETIF_DEBUG, ("Packet Length:%5"U16_F" \n",*plen));
-  LWIP_DEBUGF(NETIF_DEBUG, ("Destination: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n",
-    ethhdr->dest.addr[0],
-    ethhdr->dest.addr[1],
-    ethhdr->dest.addr[2],
-    ethhdr->dest.addr[3],
-    ethhdr->dest.addr[4],
-    ethhdr->dest.addr[5]));
-  LWIP_DEBUGF(NETIF_DEBUG, ("Source: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n",
-    ethhdr->src.addr[0],
-    ethhdr->src.addr[1],
-    ethhdr->src.addr[2],
-    ethhdr->src.addr[3],
-    ethhdr->src.addr[4],
-    ethhdr->src.addr[5]));
-  LWIP_DEBUGF(NETIF_DEBUG, ("Packet Type:0x%04"U16_F" \n", ethhdr->type));
-}
-#endif /* NETIF_DEBUG */
-
-void lwIPEthernetIntHandler(void)
-{
-    uint32_t ui32Status;
-#ifdef DEF_INT_TEMPSTAMP
-    uint32_t ui32TimerStatus;
-#endif
-    //
-    // Read and Clear the interrupt.
-    //
-    ui32Status = MAP_EMACIntStatus(EMAC0_BASE, true);
-
-    //
-    // If the interrupt really came from the Ethernet and not our
-    // timer, clear it.
-    //
-    if(ui32Status)
-    {
-        MAP_EMACIntClear(EMAC0_BASE, ui32Status);
-    }
-#ifdef DEF_INT_TEMPSTAMP
-    //
-    // Check to see whether a hardware timer interrupt has been reported.
-    //
-    if(ui32Status & EMAC_INT_TIMESTAMP)
-    {
-        //
-        // Yes - read and clear the timestamp interrupt status.
-        //
-        ui32TimerStatus = EMACTimestampIntStatus(EMAC0_BASE);
-
-        //
-        // If a timer interrupt handler has been registered, call it.
-        //
-        if(g_pfnTimerHandler)
-        {
-            g_pfnTimerHandler(EMAC0_BASE, ui32TimerStatus);
-        }
-    }
-#endif
-    //
-    // The handling of the interrupt is different based on the use of a RTOS.
-    //
-
-    //
-    // No RTOS is being used.  If a transmit/receive interrupt was active,
-    // run the low-level interrupt handler.
-    //
-    if(ui32Status)
-    {
-        tivaif_interrupt(eth_dev, ui32Status);
-    }
-
-    //
-    // Service the lwIP timers.
-    //
-    //lwIPServiceTimers();
-}
-
-
-// OUI:00-12-37 (hex) Texas Instruments, only for test 
-static int tiva_eth_mac_addr_init(void)
-{
-	int retVal =0; 
-	uint32_t ulUser[2];
-	uint8_t mac_addr[6];
-	
-	MAP_FlashUserGet(&ulUser[0], &ulUser[1]);
-	if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff))
-	{
-		rt_kprintf("Fail to get mac address from eeprom.\n");
-		rt_kprintf("Using default mac address\n");
-		// OUI:00-12-37 (hex) Texas Instruments, only for test 
-		// Configure the hardware MAC address 
-		ulUser[0] = 0x00371200;
-		ulUser[1] = 0x00563412;
-		//FlashUserSet(ulUser0, ulUser1); 
-		retVal =-1;
-	}
-	
-	
-	//Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
-	//address needed to program the hardware registers, then program the MAC
-	//address into the Ethernet Controller registers.
-	
-	mac_addr[0] = ((ulUser[0] >>  0) & 0xff);
-	mac_addr[1] = ((ulUser[0] >>  8) & 0xff);
-	mac_addr[2] = ((ulUser[0] >> 16) & 0xff);
-	mac_addr[3] = ((ulUser[1] >>  0) & 0xff);
-	mac_addr[4] = ((ulUser[1] >>  8) & 0xff);
-	mac_addr[5] = ((ulUser[1] >> 16) & 0xff);
-	
-	//
-    // Program the hardware with its MAC address (for filtering).
-    //
-    MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr);
-	return retVal;
-}
-
-#ifndef EMAC_PHY_CONFIG
-#define EMAC_PHY_CONFIG         (EMAC_PHY_TYPE_INTERNAL |                     \
-                                 EMAC_PHY_INT_MDIX_EN |                       \
-                                 EMAC_PHY_AN_100B_T_FULL_DUPLEX)
-#endif
-
- void tiva_eth_lowlevel_init(void)
-{
-    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
-    //
-    // PF1/PK4/PK6 are used for Ethernet LEDs.
-    //
-    MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0);
-    MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1);
-    GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0);
-    GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4);
-	
-    //
-    // Enable the ethernet peripheral.
-    //
-    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
-    MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
-    //
-    // Enable the internal PHY if it's present and we're being
-    // asked to use it.
-    //
-    if((EMAC_PHY_CONFIG & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
-    {
-        //
-        // We've been asked to configure for use with the internal
-        // PHY.  Is it present?
-        //
-        if(SysCtlPeripheralPresent(SYSCTL_PERIPH_EPHY0))
-        {
-            //
-            // Yes - enable and reset it.
-            //
-            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
-            MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
-        }
-        else
-        {
-            //
-            // Internal PHY is not present on this part so hang here.
-            //
-			rt_kprintf("Internal PHY is not present on this part.\n");
-            while(1)
-            {
-            }
-        }
-    }
-
-    //
-    // Wait for the MAC to come out of reset.
-    //
-    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
-    {
-    }
-
-    //
-    // Configure for use with whichever PHY the user requires.
-    //
-    MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG);
-
-    //
-    // Initialize the MAC and set the DMA mode.
-    //
-    MAP_EMACInit(EMAC0_BASE, 120000000, //system clock = 120MHz
-                 EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED,
-                 4, 4, 0);
-
-    //
-    // Set MAC configuration options.
-    //
-    MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX |
-                                   EMAC_CONFIG_CHECKSUM_OFFLOAD |
-                                   EMAC_CONFIG_7BYTE_PREAMBLE |
-                                   EMAC_CONFIG_IF_GAP_96BITS |
-                                   EMAC_CONFIG_USE_MACADDR0 |
-                                   EMAC_CONFIG_SA_FROM_DESCRIPTOR |
-                                   EMAC_CONFIG_BO_LIMIT_1024),
-                      (EMAC_MODE_RX_STORE_FORWARD |
-                       EMAC_MODE_TX_STORE_FORWARD |
-                       EMAC_MODE_TX_THRESHOLD_64_BYTES |
-                       EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);
-		   
-	EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler);
-
-}
-
-static rt_err_t eth_dev_init(rt_device_t device)
-{
-	net_device_t net_dev = (net_device_t)device;
-	struct netif *psNetif = (net_dev->parent.netif);
-	
-	LWIP_ASSERT("psNetif != NULL", (psNetif != NULL));
-
-#if LWIP_NETIF_HOSTNAME
-  /* Initialize interface hostname */
-  psNetif->hostname = "t4mc";
-#endif /* LWIP_NETIF_HOSTNAME */
-
-  /*
-   * Initialize the snmp variables and counters inside the struct netif.
-   * The last argument should be replaced with your link speed, in units
-   * of bits per second.
-   */
-  //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000);
-  
-  net_dev->dma_if = &g_StellarisIFData;
-
-  /* Remember our MAC address. */
-  g_StellarisIFData.ethaddr = (struct eth_addr *)&(psNetif->hwaddr[0]);
-
-  /* Initialize the hardware */
-  tivaif_hwinit(psNetif);
-  return RT_EOK;
-}
-
-/* control the interface */
-static rt_err_t eth_dev_control(rt_device_t dev, rt_uint8_t cmd, void *args)
-{
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if(args) 
-			MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args);
-		else 
-			return -RT_ERROR;
-		break;
-
-	default :
-		break;
-	}
-
-	return RT_EOK;
-}
-
-/* Open the interface */
-static rt_err_t eth_dev_open(rt_device_t dev, rt_uint16_t oflag)
-{
-	return RT_EOK;
-}
-
-/* Close the interface */
-static rt_err_t eth_dev_close(rt_device_t dev)
-{
-	return RT_EOK;
-}
-
-/* Read */
-static rt_size_t eth_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
-}
-
-/* Write */
-static rt_size_t eth_dev_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
-}
-
-static rt_err_t eth_dev_tx(rt_device_t dev, struct pbuf *p)
-{
-	return tivaif_transmit((net_device_t)dev, p);
-}
-
-static struct pbuf* eth_dev_rx(rt_device_t dev)
-{
-	rt_err_t result;
-	rt_uint32_t temp =0;
-	net_device_t net_dev = (net_device_t)dev;
-	result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO);
-	
-	return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL;
-}
-
-rt_err_t rt_hw_tiva_eth_init(void)
-{
-	rt_err_t result;
-
-	/* Clock GPIO and etc */
-	tiva_eth_lowlevel_init(); 
-	tiva_eth_mac_addr_init();
-
-	/* init rt-thread device interface */
-	eth_dev->parent.parent.init     = eth_dev_init;
-	eth_dev->parent.parent.open     = eth_dev_open;
-	eth_dev->parent.parent.close    = eth_dev_close;
-	eth_dev->parent.parent.read     = eth_dev_read;
-	eth_dev->parent.parent.write    = eth_dev_write;
-	eth_dev->parent.parent.control  = eth_dev_control;
-	eth_dev->parent.eth_rx          = eth_dev_rx;
-	eth_dev->parent.eth_tx          = eth_dev_tx;
-	
-	result = rt_mb_init(&eth_rx_pbuf_mb, "epbuf",
-                        &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4,
-                        RT_IPC_FLAG_FIFO);
-	RT_ASSERT(result == RT_EOK);
-	eth_dev->rx_pbuf_mb = &eth_rx_pbuf_mb;
-	
-	
-	result = eth_device_init(&(eth_dev->parent), "e0");
-	return result;
-}
-
-#ifdef RT_USING_FINSH
-#include "finsh.h"
-void PHY_Read(uint8_t addr)
-{
-	uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr);
-	rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data);
-}
-FINSH_FUNCTION_EXPORT(PHY_Read, (add));
-
-void PHY_Write(uint8_t addr , uint16_t data)
-{
-   EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, addr, data);
-	rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data);
-}
-FINSH_FUNCTION_EXPORT(PHY_Write, (add, data));
-
-void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, 
-                uint8_t addr3, uint8_t addr4, uint8_t addr5)
-{
-	uint32_t ulUser[2];
-	ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0;
-	ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3;
-	
-	MAP_FlashUserSet(ulUser[0], ulUser[1]);
-	MAP_FlashUserSave();
-	rt_kprintf("Save to EEPROM. please reboot.");
-}
-FINSH_FUNCTION_EXPORT(PHY_SetAdd, (add0-add5));
-#endif //RT_USING_FINSH
diff --git a/bsp/tm4c129x/drivers/drv_eth.h b/bsp/tm4c129x/drivers/drv_eth.h
deleted file mode 100644
index 5f27139d5f..0000000000
--- a/bsp/tm4c129x/drivers/drv_eth.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * File      : drv_eth.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-07-25     ArdaFu       Port to TM4C129X
- */
- 
-#ifndef __TIVA_ETH_H__
-#define __TIVA_ETH_H__
-
-rt_err_t rt_hw_tiva_eth_init(void);
-
-#endif
diff --git a/bsp/tm4c129x/libraries/driverlib/emac.c b/bsp/tm4c129x/libraries/driverlib/emac.c
index a9e5d14a65..dcedfdf657 100644
--- a/bsp/tm4c129x/libraries/driverlib/emac.c
+++ b/bsp/tm4c129x/libraries/driverlib/emac.c
@@ -2917,7 +2917,6 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
     //
     HWREG(ui32Base + EMAC_O_MIIADDR) =
         ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
-					EMAC_MIIADDR_CR_100_150 |
          (ui8RegAddr << EMAC_MIIADDR_MII_S) |
          (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
 

From 3879133d90c935ec28a66f83cbe1316e68797c51 Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Fri, 25 Jul 2014 19:07:25 +0800
Subject: [PATCH 72/86] [BSP] tm4c129x add eth driver 1. Add ETH MAC driver
 using DMA for Tx and Rx lwip pBuf. 2. Modify the tivaware emac library to fix
 the bug that PHY read is not stable when sysclk is 120MHz 3. In PHY IRQ
 handler, insert a dummy reading (REG_BMSR) before read PHY_STS to force
 update STS register.

---
 bsp/tm4c129x/applications/application.c |    6 +
 bsp/tm4c129x/applications/board.c       |    2 +-
 bsp/tm4c129x/drivers/drv_eth.c          | 1439 +++++++++++++++++++++++
 bsp/tm4c129x/drivers/drv_eth.h          |   20 +
 bsp/tm4c129x/libraries/driverlib/emac.c |    1 +
 5 files changed, 1467 insertions(+), 1 deletion(-)
 create mode 100644 bsp/tm4c129x/drivers/drv_eth.c
 create mode 100644 bsp/tm4c129x/drivers/drv_eth.h

diff --git a/bsp/tm4c129x/applications/application.c b/bsp/tm4c129x/applications/application.c
index 80f58b6ed8..984e622157 100644
--- a/bsp/tm4c129x/applications/application.c
+++ b/bsp/tm4c129x/applications/application.c
@@ -16,6 +16,9 @@
 #include <board.h>
 #include <components.h>
 
+#ifdef RT_USING_LWIP
+#include "drv_eth.h"
+#endif
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
@@ -24,6 +27,9 @@ void rt_init_thread_entry(void *parameter)
 #ifdef RT_USING_FINSH
     finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+#ifdef RT_USING_LWIP
+    rt_hw_tiva_eth_init();
+#endif
 }
 
 int rt_application_init(void)
diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c
index c638369a5a..2953e76c58 100644
--- a/bsp/tm4c129x/applications/board.c
+++ b/bsp/tm4c129x/applications/board.c
@@ -92,7 +92,7 @@ void rt_hw_board_init()
     
     /*init uart device*/		
     rt_hw_uart_init();
-		//redirect RTT stdio to CONSOLE device
+    //redirect RTT stdio to CONSOLE device
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
     //
     // Enable interrupts to the processor.
diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c
new file mode 100644
index 0000000000..1355f533cf
--- /dev/null
+++ b/bsp/tm4c129x/drivers/drv_eth.c
@@ -0,0 +1,1439 @@
+/*
+ * File      : drv_eth.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-25     ArdaFu       Port to TM4C129X
+ */
+
+/**
+ * @file - tivaif.c
+ * lwIP Ethernet interface for Stellaris LM4F Devices
+ *
+ */
+
+/**
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICui32AR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/**
+ * Copyright (c) 2008-2012 Texas Instruments Incorporated
+ *
+ * This file is derived from the ``ethernetif.c'' skeleton Ethernet network
+ * interface driver for lwIP.
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include <lwip/stats.h>
+#include <lwip/snmp.h>
+#include "lwip/tcpip.h"
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+
+/**
+ * Sanity Check:  This interface driver will NOT work if the following defines
+ * are incorrect.
+ *
+ */
+#if (PBUF_LINK_HLEN != 16)
+#error "PBUF_LINK_HLEN must be 16 for this interface driver!"
+#endif
+#if (ETH_PAD_SIZE != 0)
+#error "ETH_PAD_SIZE must be 0 for this interface driver!"
+#endif
+#if (!SYS_LIGHTWEIGHT_PROT)
+#error "SYS_LIGHTWEIGHT_PROT must be enabled for this interface driver!"
+#endif
+
+/**
+ * Set the physical address of the PHY we will be using if this is not
+ * specified in lwipopts.h.  We assume 0 for the internal PHY.
+ */
+#ifndef PHY_PHYS_ADDR
+#define PHY_PHYS_ADDR 0
+#endif
+
+#ifndef EMAC_PHY_CONFIG
+#define EMAC_PHY_CONFIG (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN |      \
+                         EMAC_PHY_AN_100B_T_FULL_DUPLEX)
+#endif
+
+/**
+ * If necessary, set the defaui32t number of transmit and receive DMA descriptors
+ * used by the Ethernet MAC.
+ *
+ */
+#ifndef NUM_RX_DESCRIPTORS
+#define NUM_RX_DESCRIPTORS 4
+#endif
+
+#ifndef NUM_TX_DESCRIPTORS
+#define NUM_TX_DESCRIPTORS 8
+#endif
+
+/**
+ * Setup processing for PTP (IEEE-1588).
+ *
+ */
+#if LWIP_PTPD
+extern uint32_t g_ui32SysClk;
+extern uint32_t g_ui32PTPTickRate;
+extern void lwIPHostGetTime(u32_t *time_s, u32_t *time_ns);
+#endif
+
+/**
+ * Stellaris DriverLib Header Files required for this interface driver.
+ *
+ */
+#include <stdint.h>
+#include <stdbool.h>
+#include "inc/hw_emac.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+
+#include "driverlib/emac.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
+
+#include "driverlib/pin_map.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/gpio.h"
+
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+#include "drv_eth.h"
+
+/**
+ * A structure used to keep track of driver state and error counts.
+ */
+typedef struct {
+    uint32_t ui32TXCount;
+    uint32_t ui32TXCopyCount;
+    uint32_t ui32TXCopyFailCount;
+    uint32_t ui32TXNoDescCount;
+    uint32_t ui32TXBufQueuedCount;
+    uint32_t ui32TXBufFreedCount;
+    uint32_t ui32RXBufReadCount;
+    uint32_t ui32RXPacketReadCount;
+    uint32_t ui32RXPacketErrCount;
+    uint32_t ui32RXPacketCBErrCount;
+    uint32_t ui32RXNoBufCount;
+}
+tDriverStats;
+
+tDriverStats g_sDriverStats;
+
+#ifdef DEBUG
+/**
+ * Note: This rather weird construction where we invoke the macro with the
+ * name of the field minus its Hungarian prefix is a workaround for a problem
+ * experienced with GCC which does not like concatenating tokens after an
+ * operator, specifically '.' or '->', in a macro.
+ */
+#define DRIVER_STATS_INC(x) do{ g_sDriverStats.ui32##x++; } while(0)
+#define DRIVER_STATS_DEC(x) do{ g_sDriverStats.ui32##x--; } while(0)
+#define DRIVER_STATS_ADD(x, inc) do{ g_sDriverStats.ui32##x += (inc); } while(0)
+#define DRIVER_STATS_SUB(x, dec) do{ g_sDriverStats.ui32##x -= (dec); } while(0)
+#else
+#define DRIVER_STATS_INC(x)
+#define DRIVER_STATS_DEC(x)
+#define DRIVER_STATS_ADD(x, inc)
+#define DRIVER_STATS_SUB(x, dec)
+#endif
+
+/**
+ *  Helper struct holding a DMA descriptor and the pbuf it currently refers
+ *  to.
+ */
+typedef struct {
+  tEMACDMADescriptor Desc;
+  struct pbuf *pBuf;
+} tDescriptor;
+
+typedef struct {
+    tDescriptor *pDescriptors;
+    uint32_t ui32NumDescs;
+    uint32_t ui32Read;
+    uint32_t ui32Write;
+} tDescriptorList;
+
+/**
+ * Helper struct to hold private data used to operate your ethernet interface.
+ * Keeping the ethernet address of the MAC in this struct is not necessary
+ * as it is already kept in the struct netif.
+ * But this is only an example, anyway...
+ */
+typedef struct {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+  tDescriptorList *pTxDescList;
+  tDescriptorList *pRxDescList;
+} tStellarisIF;
+
+/**
+ * Global variable for this interface's private data.  Needed to allow
+ * the interrupt handlers access to this information outside of the
+ * context of the lwIP netif.
+ *
+ */
+tDescriptor g_pTxDescriptors[NUM_TX_DESCRIPTORS];
+tDescriptor g_pRxDescriptors[NUM_RX_DESCRIPTORS];
+tDescriptorList g_TxDescList = {
+    g_pTxDescriptors, NUM_TX_DESCRIPTORS, 0, 0
+};
+tDescriptorList g_RxDescList = {
+    g_pRxDescriptors, NUM_RX_DESCRIPTORS, 0, 0
+};
+static tStellarisIF g_StellarisIFData = {
+    0, &g_TxDescList, &g_RxDescList
+};
+
+/**
+ * Interrupt counters (for debug purposes).
+ */
+volatile uint32_t g_ui32NormalInts;
+volatile uint32_t g_ui32AbnormalInts;
+
+/**
+ * A macro which determines whether a pointer is within the SRAM address
+ * space and, hence, points to a buffer that the Ethernet MAC can directly
+ * DMA from.
+ */
+#define PTR_SAFE_FOR_EMAC_DMA(ptr) (((uint32_t)(ptr) >= 0x2000000) &&   \
+                                    ((uint32_t)(ptr) < 0x20070000))
+
+
+typedef struct 
+{
+	/* inherit from ethernet device */
+	struct eth_device parent;
+	tStellarisIF* dma_if;
+	/* for rx_thread async get pbuf */
+	rt_mailbox_t rx_pbuf_mb;
+} net_device;
+typedef net_device* net_device_t; 
+
+static char               rx_pbuf_mb_pool[8*4];
+static struct rt_mailbox  eth_rx_pbuf_mb;
+static net_device         eth_dev_entry;
+static net_device_t       eth_dev = &eth_dev_entry;
+
+/**
+ * Initialize the transmit and receive DMA descriptor lists.
+ */
+void
+InitDMADescriptors(void)
+{
+    uint32_t ui32Loop;
+
+    /* Transmit list -  mark all descriptors as not owned by the hardware */
+   for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++)
+   {
+       g_pTxDescriptors[ui32Loop].pBuf = (struct pbuf *)0;
+       g_pTxDescriptors[ui32Loop].Desc.ui32Count = 0;
+       g_pTxDescriptors[ui32Loop].Desc.pvBuffer1 = 0;
+       g_pTxDescriptors[ui32Loop].Desc.DES3.pLink =
+               ((ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ?
+               &g_pTxDescriptors[0].Desc : &g_pTxDescriptors[ui32Loop + 1].Desc);
+       g_pTxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_TX_CTRL_INTERRUPT |
+               DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_IP_ALL_CKHSUMS;
+
+   }
+
+   g_TxDescList.ui32Read = 0;
+   g_TxDescList.ui32Write = 0;
+
+
+   /* Receive list -  tag each descriptor with a pbuf and set all fields to
+    * allow packets to be received.
+    */
+  for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++)
+  {
+      g_pRxDescriptors[ui32Loop].pBuf = pbuf_alloc(PBUF_RAW, PBUF_POOL_BUFSIZE,
+                                                 PBUF_POOL);
+      g_pRxDescriptors[ui32Loop].Desc.ui32Count = DES1_RX_CTRL_CHAINED;
+      if(g_pRxDescriptors[ui32Loop].pBuf)
+      {
+          /* Set the DMA to write directly into the pbuf payload. */
+          g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 =
+                  g_pRxDescriptors[ui32Loop].pBuf->payload;
+          g_pRxDescriptors[ui32Loop].Desc.ui32Count |=
+             (g_pRxDescriptors[ui32Loop].pBuf->len << DES1_RX_CTRL_BUFF1_SIZE_S);
+          g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_RX_CTRL_OWN;
+      }
+      else
+      {
+          LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_init: pbuf_alloc error\n"));
+
+          /* No pbuf available so leave the buffer pointer empty. */
+          g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = 0;
+          g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = 0;
+      }
+      g_pRxDescriptors[ui32Loop].Desc.DES3.pLink =
+              ((ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ?
+              &g_pRxDescriptors[0].Desc : &g_pRxDescriptors[ui32Loop + 1].Desc);
+  }
+
+  g_TxDescList.ui32Read = 0;
+  g_TxDescList.ui32Write = 0;
+
+  //
+  // Set the descriptor pointers in the hardware.
+  //
+  EMACRxDMADescriptorListSet(EMAC0_BASE, &g_pRxDescriptors[0].Desc);
+  EMACTxDMADescriptorListSet(EMAC0_BASE, &g_pTxDescriptors[0].Desc);
+}
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from tivaif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void
+tivaif_hwinit(struct netif *psNetif)
+{
+  uint16_t ui16Val;
+
+  /* Initialize the DMA descriptors. */
+  InitDMADescriptors();
+
+  /* Clear any stray PHY interrupts that may be set. */
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2);
+
+  /* Configure and enable the link status change interrupt in the PHY. */
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR);
+  ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT);
+  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val);
+  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN |
+               EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN));
+
+  /* Read the PHY interrupt status to clear any stray events. */
+  ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
+
+  /**
+   * Set MAC filtering options.  We receive all broadcast and mui32ticast
+   * packets along with those addressed specifically for us.
+   */
+  EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_HASH_AND_PERFECT |
+                     EMAC_FRMFILTER_PASS_MULTICAST));
+
+#if LWIP_PTPD
+  //
+  // Enable timestamping on all received packets.
+  //
+  // We set the fine clock adjustment mode and configure the subsecond
+  // increment to half the 25MHz PTPD clock.  This will give us maximum control
+  // over the clock rate adjustment and keep the arithmetic easy later.  It
+  // should be possible to synchronize with higher accuracy than this with
+  // appropriate juggling of the subsecond increment count and the addend
+  // register value, though.
+  //
+  EMACTimestampConfigSet(EMAC0_BASE, (EMAC_TS_ALL_RX_FRAMES |
+                         EMAC_TS_DIGITAL_ROLLOVER |
+                         EMAC_TS_PROCESS_IPV4_UDP | EMAC_TS_ALL |
+                         EMAC_TS_PTP_VERSION_1 | EMAC_TS_UPDATE_FINE),
+                         (1000000000 / (25000000 / 2)));
+  EMACTimestampAddendSet(EMAC0_BASE, 0x80000000);
+  EMACTimestampEnable(EMAC0_BASE);
+#endif
+
+  /* Clear any pending MAC interrupts. */
+  EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false));
+
+  /* Enable the Ethernet MAC transmitter and receiver. */
+  EMACTxEnable(EMAC0_BASE);
+  EMACRxEnable(EMAC0_BASE);
+
+  /* Enable the Ethernet RX and TX interrupt source. */
+  EMACIntEnable(EMAC0_BASE, (EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT |
+                EMAC_INT_TX_STOPPED | EMAC_INT_RX_NO_BUFFER |
+                EMAC_INT_RX_STOPPED | EMAC_INT_PHY));
+
+  /* Enable the Ethernet interrupt. */
+  IntEnable(INT_EMAC0);
+
+  /* Enable all processor interrupts. */
+  IntMasterEnable();
+
+  /* Tell the PHY to start an auto-negotiation cycle. */
+  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN |
+               EPHY_BMCR_RESTARTAN));
+}
+
+#ifdef DEBUG
+/**
+ * Dump the chain of pbuf pointers to the debug output.
+ */
+void
+tivaif_trace_pbuf(const char *pcTitle, struct pbuf *p)
+{
+    LWIP_DEBUGF(NETIF_DEBUG, ("%s %08x (%d, %d)", pcTitle, p, p->tot_len,
+                p->len));
+
+    do
+    {
+        p = p->next;
+        if(p)
+        {
+            LWIP_DEBUGF(NETIF_DEBUG, ("->%08x(%d)", p, p->len));
+        }
+        else
+        {
+            LWIP_DEBUGF(NETIF_DEBUG, ("->%08x", p));
+        }
+
+    } while((p != NULL) && (p->tot_len != p->len));
+
+    LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+}
+#endif
+
+/**
+ * This function is used to check whether a passed pbuf contains only buffers
+ * resident in regions of memory that the Ethernet MAC can access.  If any
+ * buffers in the chain are outside a directly-DMAable section of memory,
+ * the pbuf is copied to SRAM and a different pointer returned.  If all
+ * buffers are safe, the pbuf reference count is incremented and the original
+ * pointer returned.
+ */
+static struct pbuf *
+tivaif_check_pbuf(struct pbuf *p)
+{
+    struct pbuf *pBuf;
+    rt_err_t Err;
+
+    pBuf = p;
+
+#ifdef DEBUG
+    tivaif_trace_pbuf("Original:", p);
+#endif
+
+    /* Walk the list of buffers in the pbuf checking each. */
+    do
+    {
+        /* Does this pbuf's payload reside in memory that the Ethernet DMA
+         * can access?
+         */
+        if(!PTR_SAFE_FOR_EMAC_DMA(pBuf->payload))
+        {
+            /* This buffer is outside the DMA-able memory space so we need
+             * to copy the pbuf.
+             */
+            pBuf = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_POOL);
+
+            /* If we got a new pbuf... */
+            if(pBuf)
+            {
+                /* ...copy the old pbuf into the new one. */
+                Err = pbuf_copy(pBuf, p);
+
+                /* If we failed to copy the pbuf, free the newly allocated one
+                 * and make sure we return a NULL to show a problem.
+                 */
+                if(Err != RT_EOK)
+                {
+                    DRIVER_STATS_INC(TXCopyFailCount);
+                    pbuf_free(pBuf);
+                    pBuf = NULL;
+                }
+                else
+                {
+#ifdef DEBUG
+                    tivaif_trace_pbuf("Copied:", pBuf);
+#endif
+                    DRIVER_STATS_INC(TXCopyCount);
+
+                    /* Reduce the reference count on the original pbuf since
+                     * we're not going to hold on to it after returning from
+                     * tivaif_transmit.  Note that we already bumped
+                     * the reference count at the top of tivaif_transmit.
+                     */
+                    pbuf_free(p);
+                }
+            }
+
+            /* Send back the new pbuf pointer or NULL if an error occurred. */
+            return(pBuf);
+        }
+
+        /* Move on to the next buffer in the queue */
+        pBuf = pBuf->next;
+    }
+    while(pBuf);
+
+    /**
+     * If we get here, the passed pbuf can be safely used without needing to
+     * be copied.
+     */
+    return(p);
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf might be
+ * chained.
+ *
+ * @param psNetif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return RT_EOK if the packet coui32d be sent
+ *         an err_t value if the packet coui32dn't be sent
+ */
+static rt_err_t
+tivaif_transmit(net_device_t dev, struct pbuf *p)
+{
+  tStellarisIF *pIF;
+  tDescriptor *pDesc;
+  struct pbuf *pBuf;
+  uint32_t ui32NumChained, ui32NumDescs;
+  bool bFirst;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_transmit 0x%08x, len %d\n", p,
+              p->tot_len));
+
+  /**
+   * This entire function must run within a "critical section" to preserve
+   * the integrity of the transmit pbuf queue.
+   */
+  SYS_ARCH_PROTECT(lev);
+
+  /* Update our transmit attempt counter. */
+  DRIVER_STATS_INC(TXCount);
+
+  /**
+   * Increase the reference count on the packet provided so that we can
+   * hold on to it until we are finished transmitting its content.
+   */
+  pbuf_ref(p);
+
+  /**
+   * Determine whether all buffers passed are within SRAM and, if not, copy
+   * the pbuf into SRAM-resident buffers so that the Ethernet DMA can access
+   * the data.
+   */
+  p = tivaif_check_pbuf(p);
+
+  /* Make sure we still have a valid buffer (it may have been copied) */
+  if(!p)
+  {
+      LINK_STATS_INC(link.memerr);
+      SYS_ARCH_UNPROTECT(lev);
+      return(-RT_ENOMEM);
+  }
+
+  /* Get our state data from the netif structure we were passed. */
+  //pIF = (tStellarisIF *)psNetif->state;
+  pIF = dev->dma_if;
+  
+  /* Make sure that the transmit descriptors are not all in use */
+  pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]);
+  if(pDesc->pBuf)
+  {
+      /**
+       * The current write descriptor has a pbuf attached to it so this
+       * implies that the ring is fui32l. Reject this transmit request with a
+       * memory error since we can't satisfy it just now.
+       */
+      pbuf_free(p);
+      LINK_STATS_INC(link.memerr);
+      DRIVER_STATS_INC(TXNoDescCount);
+      SYS_ARCH_UNPROTECT(lev);
+      return (-RT_ENOMEM);
+  }
+
+  /* How many pbufs are in the chain passed? */
+  ui32NumChained = (uint32_t)pbuf_clen(p);
+
+  /* How many free transmit descriptors do we have? */
+  ui32NumDescs = (pIF->pTxDescList->ui32Read > pIF->pTxDescList->ui32Write) ?
+          (pIF->pTxDescList->ui32Read - pIF->pTxDescList->ui32Write) :
+          ((NUM_TX_DESCRIPTORS - pIF->pTxDescList->ui32Write) +
+           pIF->pTxDescList->ui32Read);
+
+  /* Do we have enough free descriptors to send the whole packet? */
+  if(ui32NumDescs < ui32NumChained)
+  {
+      /* No - we can't transmit this whole packet so return an error. */
+      pbuf_free(p);
+      LINK_STATS_INC(link.memerr);
+      DRIVER_STATS_INC(TXNoDescCount);
+      SYS_ARCH_UNPROTECT(lev);
+      return (-RT_ENOMEM);
+  }
+
+  /* Tag the first descriptor as the start of the packet. */
+  bFirst = true;
+  pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG;
+
+  /* Here, we know we can send the packet so write it to the descriptors */
+  pBuf = p;
+
+  while(ui32NumChained)
+  {
+      /* Get a pointer to the descriptor we will write next. */
+      pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]);
+
+      /* Fill in the buffer pointer and length */
+      pDesc->Desc.ui32Count = (uint32_t)pBuf->len;
+      pDesc->Desc.pvBuffer1 = pBuf->payload;
+
+      /* Tag the first descriptor as the start of the packet. */
+      if(bFirst)
+      {
+          bFirst = false;
+          pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG;
+      }
+      else
+      {
+          pDesc->Desc.ui32CtrlStatus = 0;
+      }
+
+      pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_IP_ALL_CKHSUMS |
+                                     DES0_TX_CTRL_CHAINED);
+
+      /* Decrement our descriptor counter, move on to the next buffer in the
+       * pbuf chain. */
+      ui32NumChained--;
+      pBuf = pBuf->next;
+
+      /* Update the descriptor list write index. */
+      pIF->pTxDescList->ui32Write++;
+      if(pIF->pTxDescList->ui32Write == NUM_TX_DESCRIPTORS)
+      {
+          pIF->pTxDescList->ui32Write = 0;
+      }
+
+      /* If this is the last descriptor, mark it as the end of the packet. */
+      if(!ui32NumChained)
+      {
+          pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_LAST_SEG |
+                                         DES0_TX_CTRL_INTERRUPT);
+
+          /* Tag the descriptor with the original pbuf pointer. */
+          pDesc->pBuf = p;
+      }
+      else
+      {
+          /* Set the lsb of the pbuf pointer.  We use this as a signal that
+           * we should not free the pbuf when we are walking the descriptor
+           * list while processing the transmit interrupt.  We only free the
+           * pbuf when processing the last descriptor used to transmit its
+           * chain.
+           */
+          pDesc->pBuf = (struct pbuf *)((uint32_t)p + 1);
+      }
+
+      DRIVER_STATS_INC(TXBufQueuedCount);
+
+      /* Hand the descriptor over to the hardware. */
+      pDesc->Desc.ui32CtrlStatus |= DES0_TX_CTRL_OWN;
+  }
+
+  /* Tell the transmitter to start (in case it had stopped). */
+  EMACTxDMAPollDemand(EMAC0_BASE);
+
+  /* Update lwIP statistics */
+  LINK_STATS_INC(link.xmit);
+
+  SYS_ARCH_UNPROTECT(lev);
+
+  return(RT_EOK);
+}
+
+/**
+ * This function will process all transmit descriptors and free pbufs attached
+ * to any that have been transmitted since we last checked.
+ *
+ * This function is called only from the Ethernet interrupt handler.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return None.
+ */
+static void
+tivaif_process_transmit(tStellarisIF *pIF)
+{
+    tDescriptorList *pDescList;
+    uint32_t ui32NumDescs;
+
+    /* Get a pointer to the transmit descriptor list. */
+    pDescList = pIF->pTxDescList;
+
+    /* Walk the list until we have checked all descriptors or we reach the
+     * write pointer or find a descriptor that the hardware is still working
+     * on.
+     */
+    for(ui32NumDescs = 0; ui32NumDescs < pDescList->ui32NumDescs; ui32NumDescs++)
+    {
+        /* Has the buffer attached to this descriptor been transmitted? */
+        if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+           DES0_TX_CTRL_OWN)
+        {
+            /* No - we're finished. */
+            break;
+        }
+
+        /* Does this descriptor have a buffer attached to it? */
+        if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
+        {
+            /* Yes - free it if it's not marked as an intermediate pbuf */
+            if(!((uint32_t)(pDescList->pDescriptors[pDescList->ui32Read].pBuf) & 1))
+            {
+                pbuf_free(pDescList->pDescriptors[pDescList->ui32Read].pBuf);
+                DRIVER_STATS_INC(TXBufFreedCount);
+            }
+            pDescList->pDescriptors[pDescList->ui32Read].pBuf = NULL;
+        }
+        else
+        {
+            /* If the descriptor has no buffer, we are finished. */
+            break;
+        }
+
+        /* Move on to the next descriptor. */
+        pDescList->ui32Read++;
+        if(pDescList->ui32Read == pDescList->ui32NumDescs)
+        {
+            pDescList->ui32Read = 0;
+        }
+    }
+}
+
+/**
+ * This function will process all receive descriptors that contain newly read
+ * data and pass complete frames up the lwIP stack as they are found.  The
+ * timestamp of the packet will be placed into the pbuf structure if PTPD is
+ * enabled.
+ *
+ * This function is called only from the Ethernet interrupt handler.
+ *
+ * @param psNetif the lwip network interface structure for this ethernetif
+ * @return None.
+ */
+static void
+tivaif_receive(net_device_t dev)
+{
+  tDescriptorList *pDescList;
+  tStellarisIF *pIF;
+  struct pbuf *pBuf;
+  uint32_t ui32DescEnd;
+
+  /* Get a pointer to our state data */
+  pIF = dev->dma_if;
+
+  /* Get a pointer to the receive descriptor list. */
+  pDescList = pIF->pRxDescList;
+
+  /* Start with a NULL pbuf so that we don't try to link chain the first
+   * time round.
+   */
+  pBuf = NULL;
+
+  /* Determine where we start and end our walk of the descriptor list */
+   ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1);
+
+  /* Step through the descriptors that are marked for CPU attention. */
+  while(pDescList->ui32Read != ui32DescEnd)
+  {
+      /* Does the current descriptor have a buffer attached to it? */
+      if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
+      {
+          /* Yes - determine if the host has filled it yet. */
+          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+             DES0_RX_CTRL_OWN)
+          {
+              /* The DMA engine still owns the descriptor so we are finished */
+              break;
+          }
+
+          DRIVER_STATS_INC(RXBufReadCount);
+
+          /* If this descriptor contains the end of the packet, fix up the
+           * buffer size accordingly.
+           */
+          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+             DES0_RX_STAT_LAST_DESC)
+          {
+              /* This is the last descriptor for the frame so fix up the
+               * length.  It is safe for us to modify the internal fields
+               * directly here (rather than calling pbuf_realloc) since we
+               * know each of these pbufs is never chained.
+               */
+              pDescList->pDescriptors[pDescList->ui32Read].pBuf->len =
+                       (pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+                        DES0_RX_STAT_FRAME_LENGTH_M) >>
+                        DES0_RX_STAT_FRAME_LENGTH_S;
+              pDescList->pDescriptors[pDescList->ui32Read].pBuf->tot_len =
+                        pDescList->pDescriptors[pDescList->ui32Read].pBuf->len;
+          }
+
+          if(pBuf)
+          {
+              /* Link this pbuf to the last one we looked at since this buffer
+               * is a continuation of an existing frame (split across mui32tiple
+               * pbufs).  Note that we use pbuf_cat() here rather than
+               * pbuf_chain() since we don't want to increase the reference
+               * count of either pbuf - we only want to link them together.
+               */
+              pbuf_cat(pBuf, pDescList->pDescriptors[pDescList->ui32Read].pBuf);
+              pDescList->pDescriptors[pDescList->ui32Read].pBuf = pBuf;
+          }
+
+          /* Remember the buffer associated with this descriptor. */
+          pBuf = pDescList->pDescriptors[pDescList->ui32Read].pBuf;
+
+          /* Is this the last descriptor for the current frame? */
+          if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+             DES0_RX_STAT_LAST_DESC)
+          {
+              /* Yes - does the frame contain errors? */
+              if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus &
+                 DES0_RX_STAT_ERR)
+              {
+                  /* This is a bad frame so discard it and update the relevant
+                   * statistics.
+                   */
+                  LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: packet error\n"));
+                  pbuf_free(pBuf);
+                  LINK_STATS_INC(link.drop);
+                  DRIVER_STATS_INC(RXPacketErrCount);
+              }
+              else
+              {
+                  /* This is a good frame so pass it up the stack. */
+                  LINK_STATS_INC(link.recv);
+                  DRIVER_STATS_INC(RXPacketReadCount);
+
+#if LWIP_PTPD
+                  /* Place the timestamp in the PBUF if PTPD is enabled */
+                  pBuf->time_s =
+                       pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeHi;
+                  pBuf->time_ns =
+                       pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeLo;
+#endif
+
+#if NO_SYS
+                  if(ethernet_input(pBuf, psNetif) != RT_EOK)
+                  {
+#else
+                  //if(tcpip_input(pBuf, psNetif) != RT_EOK)
+				  if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) ||
+					(eth_device_ready(&(dev->parent)) != RT_EOK))
+                  {
+#endif
+                      /* drop the packet */
+                      LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_input: input error\n"));
+                      pbuf_free(pBuf);
+
+                      /* Adjust the link statistics */
+                      LINK_STATS_INC(link.memerr);
+                      LINK_STATS_INC(link.drop);
+                      DRIVER_STATS_INC(RXPacketCBErrCount);
+                  }
+
+                  /* We're finished with this packet so make sure we don't try
+                   * to link the next buffer to it.
+                   */
+                  pBuf = NULL;
+              }
+          }
+      }
+
+      /* Allocate a new buffer for this descriptor */
+      pDescList->pDescriptors[pDescList->ui32Read].pBuf = pbuf_alloc(PBUF_RAW,
+                                                        PBUF_POOL_BUFSIZE,
+                                                        PBUF_POOL);
+      pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count =
+                                                        DES1_RX_CTRL_CHAINED;
+      if(pDescList->pDescriptors[pDescList->ui32Read].pBuf)
+      {
+          /* We got a buffer so fill in the payload pointer and size. */
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 =
+                              pDescList->pDescriptors[pDescList->ui32Read].pBuf->payload;
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count |=
+                              (pDescList->pDescriptors[pDescList->ui32Read].pBuf->len <<
+                               DES1_RX_CTRL_BUFF1_SIZE_S);
+
+          /* Give this descriptor back to the hardware */
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus =
+                              DES0_RX_CTRL_OWN;
+      }
+      else
+      {
+          LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: pbuf_alloc error\n"));
+
+          pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = 0;
+
+          /* Update the stats to show we coui32dn't allocate a pbuf. */
+          DRIVER_STATS_INC(RXNoBufCount);
+          LINK_STATS_INC(link.memerr);
+
+          /* Stop parsing here since we can't leave a broken descriptor in
+           * the chain.
+           */
+          break;
+      }
+
+      /* Move on to the next descriptor in the chain, taking care to wrap. */
+      pDescList->ui32Read++;
+      if(pDescList->ui32Read == pDescList->ui32NumDescs)
+      {
+          pDescList->ui32Read = 0;
+      }
+  }
+}
+
+/**
+ * Process interrupts from the PHY.
+ *
+ * should be called from the Stellaris Ethernet Interrupt Handler.  This
+ * function will read packets from the Stellaris Ethernet fifo and place them
+ * into a pbuf queue.  If the transmitter is idle and there is at least one packet
+ * on the transmit queue, it will place it in the transmit fifo and start the
+ * transmitter.
+ *
+ */
+void
+tivaif_process_phy_interrupt(net_device_t dev)
+{
+    uint16_t ui16Val, ui16Status;
+    uint32_t ui32Config, ui32Mode, ui32RxMaxFrameSize;
+
+    /* Read the PHY interrupt status.  This clears all interrupt sources.
+     * Note that we are only enabling sources in EPHY_MISR1 so we don't
+     * read EPHY_MISR2.
+     */
+    ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1);
+
+	/* 
+	 * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register
+	 */
+		EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR);
+    /* Read the current PHY status. */
+    ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS);
+
+    /* Has the link status changed? */
+    if(ui16Val & EPHY_MISR1_LINKSTAT)
+    {
+        /* Is link up or down now? */
+        if(ui16Status & EPHY_STS_LINK)
+        {
+            /* Tell lwIP the link is up. */
+#if NO_SYS
+            netif_set_link_up(psNetif);
+#else
+            //tcpip_callback((tcpip_callback_fn)netif_set_link_up, psNetif);
+			eth_device_linkchange(&(dev->parent), RT_TRUE);
+#endif
+
+            /* In this case we drop through since we may need to reconfigure
+             * the MAC depending upon the speed and half/fui32l-duplex settings.
+             */
+        }
+        else
+        {
+            /* Tell lwIP the link is down */
+#if NO_SYS
+            netif_set_link_down(psNetif);
+#else
+            //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif);
+			eth_device_linkchange(&(dev->parent), RT_FALSE);
+#endif
+        }
+    }
+
+    /* Has the speed or duplex status changed? */
+    if(ui16Val & (EPHY_MISR1_SPEED | EPHY_MISR1_SPEED | EPHY_MISR1_ANC))
+    {
+        /* Get the current MAC configuration. */
+        EMACConfigGet(EMAC0_BASE, &ui32Config, &ui32Mode,
+                        &ui32RxMaxFrameSize);
+
+        /* What speed is the interface running at now?
+         */
+        if(ui16Status & EPHY_STS_SPEED)
+        {
+            /* 10Mbps is selected */
+            ui32Config &= ~EMAC_CONFIG_100MBPS;
+        }
+        else
+        {
+            /* 100Mbps is selected */
+            ui32Config |= EMAC_CONFIG_100MBPS;
+        }
+
+        /* Are we in fui32l- or half-duplex mode? */
+        if(ui16Status & EPHY_STS_DUPLEX)
+        {
+            /* Fui32l duplex. */
+            ui32Config |= EMAC_CONFIG_FULL_DUPLEX;
+        }
+        else
+        {
+            /* Half duplex. */
+            ui32Config &= ~EMAC_CONFIG_FULL_DUPLEX;
+        }
+
+        /* Reconfigure the MAC */
+        EMACConfigSet(EMAC0_BASE, ui32Config, ui32Mode, ui32RxMaxFrameSize);
+    }
+}
+
+/**
+ * Process tx and rx packets at the low-level interrupt.
+ *
+ * should be called from the Stellaris Ethernet Interrupt Handler.  This
+ * function will read packets from the Stellaris Ethernet fifo and place them
+ * into a pbuf queue.  If the transmitter is idle and there is at least one packet
+ * on the transmit queue, it will place it in the transmit fifo and start the
+ * transmitter.
+ *
+ */
+void
+tivaif_interrupt(net_device_t dev, uint32_t ui32Status)
+{
+
+  /* Update our debug interrupt counters. */
+  if(ui32Status & EMAC_INT_NORMAL_INT)
+  {
+      g_ui32NormalInts++;
+  }
+
+  if(ui32Status & EMAC_INT_ABNORMAL_INT)
+  {
+      g_ui32AbnormalInts++;
+  }
+
+  /* Is this an interrupt from the PHY? */
+  if(ui32Status & EMAC_INT_PHY)
+  {
+      tivaif_process_phy_interrupt(dev);
+  }
+
+  /* Process the transmit DMA list, freeing any buffers that have been
+   * transmitted since our last interrupt.
+   */
+  if(ui32Status & EMAC_INT_TRANSMIT)
+  {
+      tivaif_process_transmit(dev->dma_if);
+  }
+
+  /**
+   * Process the receive DMA list and pass all successfui32ly received packets
+   * up the stack.  We also call this function in cases where the receiver has
+   * stalled due to missing buffers since the receive function will attempt to
+   * allocate new pbufs for descriptor entries which have none.
+   */
+  if(ui32Status & (EMAC_INT_RECEIVE | EMAC_INT_RX_NO_BUFFER |
+     EMAC_INT_RX_STOPPED))
+  {
+      tivaif_receive(dev);
+  }
+}
+
+#if NETIF_DEBUG
+/* Print an IP header by using LWIP_DEBUGF
+ * @param p an IP packet, p->payload pointing to the IP header
+ */
+void
+tivaif_debug_print(struct pbuf *p)
+{
+  struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload;
+  u16_t *plen = (u16_t *)p->payload;
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("ETH header:\n"));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Packet Length:%5"U16_F" \n",*plen));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Destination: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n",
+    ethhdr->dest.addr[0],
+    ethhdr->dest.addr[1],
+    ethhdr->dest.addr[2],
+    ethhdr->dest.addr[3],
+    ethhdr->dest.addr[4],
+    ethhdr->dest.addr[5]));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Source: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n",
+    ethhdr->src.addr[0],
+    ethhdr->src.addr[1],
+    ethhdr->src.addr[2],
+    ethhdr->src.addr[3],
+    ethhdr->src.addr[4],
+    ethhdr->src.addr[5]));
+  LWIP_DEBUGF(NETIF_DEBUG, ("Packet Type:0x%04"U16_F" \n", ethhdr->type));
+}
+#endif /* NETIF_DEBUG */
+
+void lwIPEthernetIntHandler(void)
+{
+    uint32_t ui32Status;
+#ifdef DEF_INT_TEMPSTAMP
+    uint32_t ui32TimerStatus;
+#endif
+    //
+    // Read and Clear the interrupt.
+    //
+    ui32Status = MAP_EMACIntStatus(EMAC0_BASE, true);
+
+    //
+    // If the interrupt really came from the Ethernet and not our
+    // timer, clear it.
+    //
+    if(ui32Status)
+    {
+        MAP_EMACIntClear(EMAC0_BASE, ui32Status);
+    }
+#ifdef DEF_INT_TEMPSTAMP
+    //
+    // Check to see whether a hardware timer interrupt has been reported.
+    //
+    if(ui32Status & EMAC_INT_TIMESTAMP)
+    {
+        //
+        // Yes - read and clear the timestamp interrupt status.
+        //
+        ui32TimerStatus = EMACTimestampIntStatus(EMAC0_BASE);
+
+        //
+        // If a timer interrupt handler has been registered, call it.
+        //
+        if(g_pfnTimerHandler)
+        {
+            g_pfnTimerHandler(EMAC0_BASE, ui32TimerStatus);
+        }
+    }
+#endif
+    //
+    // The handling of the interrupt is different based on the use of a RTOS.
+    //
+
+    //
+    // No RTOS is being used.  If a transmit/receive interrupt was active,
+    // run the low-level interrupt handler.
+    //
+    if(ui32Status)
+    {
+        tivaif_interrupt(eth_dev, ui32Status);
+    }
+
+    //
+    // Service the lwIP timers.
+    //
+    //lwIPServiceTimers();
+}
+
+
+// OUI:00-12-37 (hex) Texas Instruments, only for test 
+static int tiva_eth_mac_addr_init(void)
+{
+	int retVal =0; 
+	uint32_t ulUser[2];
+	uint8_t mac_addr[6];
+	
+	MAP_FlashUserGet(&ulUser[0], &ulUser[1]);
+	if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff))
+	{
+		rt_kprintf("Fail to get mac address from eeprom.\n");
+		rt_kprintf("Using default mac address\n");
+		// OUI:00-12-37 (hex) Texas Instruments, only for test 
+		// Configure the hardware MAC address 
+		ulUser[0] = 0x00371200;
+		ulUser[1] = 0x00563412;
+		//FlashUserSet(ulUser0, ulUser1); 
+		retVal =-1;
+	}
+	
+	
+	//Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
+	//address needed to program the hardware registers, then program the MAC
+	//address into the Ethernet Controller registers.
+	
+	mac_addr[0] = ((ulUser[0] >>  0) & 0xff);
+	mac_addr[1] = ((ulUser[0] >>  8) & 0xff);
+	mac_addr[2] = ((ulUser[0] >> 16) & 0xff);
+	mac_addr[3] = ((ulUser[1] >>  0) & 0xff);
+	mac_addr[4] = ((ulUser[1] >>  8) & 0xff);
+	mac_addr[5] = ((ulUser[1] >> 16) & 0xff);
+	
+	//
+    // Program the hardware with its MAC address (for filtering).
+    //
+    MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr);
+	return retVal;
+}
+
+ void tiva_eth_lowlevel_init(void)
+{
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
+    //
+    // PF1/PK4/PK6 are used for Ethernet LEDs.
+    //
+    MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0);
+    MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1);
+    GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0);
+    GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4);
+	
+    //
+    // Enable the ethernet peripheral.
+    //
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
+    MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
+    //
+    // Enable the internal PHY if it's present and we're being
+    // asked to use it.
+    //
+    if((EMAC_PHY_CONFIG & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
+    {
+        //
+        // We've been asked to configure for use with the internal
+        // PHY.  Is it present?
+        //
+        if(SysCtlPeripheralPresent(SYSCTL_PERIPH_EPHY0))
+        {
+            //
+            // Yes - enable and reset it.
+            //
+            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
+            MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
+        }
+        else
+        {
+            //
+            // Internal PHY is not present on this part so hang here.
+            //
+			rt_kprintf("Internal PHY is not present on this part.\n");
+            while(1)
+            {
+            }
+        }
+    }
+
+    //
+    // Wait for the MAC to come out of reset.
+    //
+    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
+    {
+    }
+
+    //
+    // Configure for use with whichever PHY the user requires.
+    //
+    MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG);
+
+    //
+    // Initialize the MAC and set the DMA mode.
+    //
+    MAP_EMACInit(EMAC0_BASE, 120000000, //system clock = 120MHz
+                 EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED,
+                 4, 4, 0);
+
+    //
+    // Set MAC configuration options.
+    //
+    MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX |
+                                   EMAC_CONFIG_CHECKSUM_OFFLOAD |
+                                   EMAC_CONFIG_7BYTE_PREAMBLE |
+                                   EMAC_CONFIG_IF_GAP_96BITS |
+                                   EMAC_CONFIG_USE_MACADDR0 |
+                                   EMAC_CONFIG_SA_FROM_DESCRIPTOR |
+                                   EMAC_CONFIG_BO_LIMIT_1024),
+                      (EMAC_MODE_RX_STORE_FORWARD |
+                       EMAC_MODE_TX_STORE_FORWARD |
+                       EMAC_MODE_TX_THRESHOLD_64_BYTES |
+                       EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);
+		   
+	EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler);
+
+}
+
+static rt_err_t eth_dev_init(rt_device_t device)
+{
+	net_device_t net_dev = (net_device_t)device;
+	struct netif *psNetif = (net_dev->parent.netif);
+	
+	LWIP_ASSERT("psNetif != NULL", (psNetif != NULL));
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  psNetif->hostname = "t4mc";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000);
+  
+  net_dev->dma_if = &g_StellarisIFData;
+
+  /* Remember our MAC address. */
+  g_StellarisIFData.ethaddr = (struct eth_addr *)&(psNetif->hwaddr[0]);
+
+  /* Initialize the hardware */
+  tivaif_hwinit(psNetif);
+  return RT_EOK;
+}
+
+/* control the interface */
+static rt_err_t eth_dev_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	switch(cmd)
+	{
+	case NIOCTL_GADDR:
+		/* get mac address */
+		if(args) 
+			MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args);
+		else 
+			return -RT_ERROR;
+		break;
+
+	default :
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/* Open the interface */
+static rt_err_t eth_dev_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+/* Close the interface */
+static rt_err_t eth_dev_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+/* Read */
+static rt_size_t eth_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+/* Write */
+static rt_size_t eth_dev_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_err_t eth_dev_tx(rt_device_t dev, struct pbuf *p)
+{
+	return tivaif_transmit((net_device_t)dev, p);
+}
+
+static struct pbuf* eth_dev_rx(rt_device_t dev)
+{
+	rt_err_t result;
+	rt_uint32_t temp =0;
+	net_device_t net_dev = (net_device_t)dev;
+	result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO);
+	
+	return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL;
+}
+
+rt_err_t rt_hw_tiva_eth_init(void)
+{
+	rt_err_t result;
+
+	/* Clock GPIO and etc */
+	tiva_eth_lowlevel_init(); 
+	tiva_eth_mac_addr_init();
+
+	/* init rt-thread device interface */
+	eth_dev->parent.parent.init     = eth_dev_init;
+	eth_dev->parent.parent.open     = eth_dev_open;
+	eth_dev->parent.parent.close    = eth_dev_close;
+	eth_dev->parent.parent.read     = eth_dev_read;
+	eth_dev->parent.parent.write    = eth_dev_write;
+	eth_dev->parent.parent.control  = eth_dev_control;
+	eth_dev->parent.eth_rx          = eth_dev_rx;
+	eth_dev->parent.eth_tx          = eth_dev_tx;
+	
+	result = rt_mb_init(&eth_rx_pbuf_mb, "epbuf",
+                        &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4,
+                        RT_IPC_FLAG_FIFO);
+	RT_ASSERT(result == RT_EOK);
+	eth_dev->rx_pbuf_mb = &eth_rx_pbuf_mb;
+	
+	
+	result = eth_device_init(&(eth_dev->parent), "e0");
+	return result;
+}
+#if 0
+#ifdef RT_USING_FINSH
+#include "finsh.h"
+void PHY_Read(uint8_t addr)
+{
+	uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr);
+	rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data);
+}
+FINSH_FUNCTION_EXPORT(PHY_Read, (add));
+
+void PHY_Write(uint8_t addr , uint16_t data)
+{
+   EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, addr, data);
+	rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data);
+}
+FINSH_FUNCTION_EXPORT(PHY_Write, (add, data));
+
+void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, 
+                uint8_t addr3, uint8_t addr4, uint8_t addr5)
+{
+	uint32_t ulUser[2];
+	ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0;
+	ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3;
+	
+	MAP_FlashUserSet(ulUser[0], ulUser[1]);
+	MAP_FlashUserSave();
+	rt_kprintf("Save to EEPROM. please reboot.");
+}
+FINSH_FUNCTION_EXPORT(PHY_SetAdd, (add0-add5));
+#endif //RT_USING_FINSH
+#endif
diff --git a/bsp/tm4c129x/drivers/drv_eth.h b/bsp/tm4c129x/drivers/drv_eth.h
new file mode 100644
index 0000000000..5f27139d5f
--- /dev/null
+++ b/bsp/tm4c129x/drivers/drv_eth.h
@@ -0,0 +1,20 @@
+/*
+ * File      : drv_eth.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-25     ArdaFu       Port to TM4C129X
+ */
+ 
+#ifndef __TIVA_ETH_H__
+#define __TIVA_ETH_H__
+
+rt_err_t rt_hw_tiva_eth_init(void);
+
+#endif
diff --git a/bsp/tm4c129x/libraries/driverlib/emac.c b/bsp/tm4c129x/libraries/driverlib/emac.c
index dcedfdf657..a9e5d14a65 100644
--- a/bsp/tm4c129x/libraries/driverlib/emac.c
+++ b/bsp/tm4c129x/libraries/driverlib/emac.c
@@ -2917,6 +2917,7 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
     //
     HWREG(ui32Base + EMAC_O_MIIADDR) =
         ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
+					EMAC_MIIADDR_CR_100_150 |
          (ui8RegAddr << EMAC_MIIADDR_MII_S) |
          (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
 

From baf608f156bb33d98affed82d292a2073ec97c85 Mon Sep 17 00:00:00 2001
From: ArdaFu <pengfei.fu@gmail.com>
Date: Fri, 25 Jul 2014 23:25:32 +0800
Subject: [PATCH 73/86] [BSP] tm4c129x: fix compile bug when turn 
 RT_USING_LWIP 1. Resize RT_LWIP_SEG_NUM drom 8 to 12 2. modify gcc compile
 switch, using C99

---
 bsp/tm4c129x/rtconfig.h  | 4 ++--
 bsp/tm4c129x/rtconfig.py | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/bsp/tm4c129x/rtconfig.h b/bsp/tm4c129x/rtconfig.h
index 50cde4df7f..9d76c80f06 100644
--- a/bsp/tm4c129x/rtconfig.h
+++ b/bsp/tm4c129x/rtconfig.h
@@ -166,7 +166,7 @@
 // </section>
 
 // <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
-//#define RT_USING_LWIP
+#define RT_USING_LWIP
 // <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
 #define RT_USING_LWIP141
 // <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
@@ -192,7 +192,7 @@
 // <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
 // #define RT_LWIP_DHCP
 // <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
-#define RT_LWIP_TCP_SEG_NUM 8
+#define RT_LWIP_TCP_SEG_NUM 12
 // <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
 #define RT_LWIP_TCPTHREAD_PRIORITY  12
 // <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
diff --git a/bsp/tm4c129x/rtconfig.py b/bsp/tm4c129x/rtconfig.py
index fb370aed47..93e3f3e257 100644
--- a/bsp/tm4c129x/rtconfig.py
+++ b/bsp/tm4c129x/rtconfig.py
@@ -45,7 +45,7 @@ if PLATFORM == 'gcc':
     OBJCPY = PREFIX + 'objcopy'
 	
     DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
-    CFLAGS = DEVICE + ' -std=gnu11 -Dgcc'
+    CFLAGS = DEVICE + ' -std=c99 -Dgcc'
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
     LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-tm4c129x.map,-cref,-u,Reset_Handler -T tm4c_rom.ld'
 

From 94883a92fbc43b41e4888beb27fc2c3e2a95d4f1 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Thu, 31 Jul 2014 08:34:36 +0800
Subject: [PATCH 74/86] [pthreads] Fix pthread_cond_init issue. #261

---
 components/pthreads/pthread_cond.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/components/pthreads/pthread_cond.c b/components/pthreads/pthread_cond.c
index e5342dd775..25628fc2b3 100644
--- a/components/pthreads/pthread_cond.c
+++ b/components/pthreads/pthread_cond.c
@@ -98,7 +98,11 @@ int pthread_cond_init(pthread_cond_t *cond, const pthread_condattr_t *attr)
 
     rt_snprintf(cond_name, sizeof(cond_name), "cond%02d", cond_num++);
 
-    cond->attr = *attr;
+	if (attr == RT_NULL) /* use default value */
+		cond->attr = PTHREAD_PROCESS_PRIVATE;
+	else 
+	    cond->attr = *attr;
+
     result = rt_sem_init(&cond->sem, cond_name, 0, RT_IPC_FLAG_FIFO);
     if (result != RT_EOK)
         return EINVAL;

From 59c128c0733c4b3ffa61558bb2ce8bf981c78adb Mon Sep 17 00:00:00 2001
From: Bernard Xiong <root@VM-152-115-ubuntu.(none)>
Date: Thu, 31 Jul 2014 09:30:18 +0800
Subject: [PATCH 75/86] [libc] fix compiling warning

---
 components/dfs/src/dfs_posix.c    | 11 ++++++++---
 components/libc/newlib/syscalls.c |  8 ++++++++
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/components/dfs/src/dfs_posix.c b/components/dfs/src/dfs_posix.c
index 96139837e9..a7d6159a1c 100644
--- a/components/dfs/src/dfs_posix.c
+++ b/components/dfs/src/dfs_posix.c
@@ -537,12 +537,17 @@ struct dirent *readdir(DIR *d)
     if (fd == RT_NULL)
     {
         rt_set_errno(-DFS_STATUS_EBADF);
-
         return RT_NULL;
     }
 
-    if (!d->num ||
-        (d->cur += ((struct dirent *)(d->buf + d->cur))->d_reclen) >= d->num)
+    if (d->num)
+    {
+        struct dirent* dirent_ptr;
+        dirent_ptr = (struct dirent*)&d->buf[d->cur];
+        d->cur += dirent_ptr->d_reclen;
+    }
+
+    if (!d->num || d->cur >= d->num)
     {
         /* get a new entry */
         result = dfs_file_getdents(fd,
diff --git a/components/libc/newlib/syscalls.c b/components/libc/newlib/syscalls.c
index 5b829f4753..388d240c94 100644
--- a/components/libc/newlib/syscalls.c
+++ b/components/libc/newlib/syscalls.c
@@ -3,6 +3,14 @@
 #include <sys/time.h>
 #include <rtthread.h>
 
+#ifdef RT_USING_DFS
+#include <dfs_posix.h>
+#endif
+
+#ifdef RT_USING_PTHREADS 
+#include <pthread.h>
+#endif
+
 /* Reentrant versions of system calls.  */
 
 int

From 07c486413b982e41f9c7afdbced5b2a684677a5c Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Thu, 31 Jul 2014 09:46:01 +0800
Subject: [PATCH 76/86] [external] PNG_NO_WRITE_SUPPORTED issue

Move PNG_NO_WRITE_SUPPORTED outside of RT_USING_NEWLIB. #197
---
 components/external/libpng/pngconf.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/external/libpng/pngconf.h b/components/external/libpng/pngconf.h
index bb0a189f9d..cca0657e4c 100644
--- a/components/external/libpng/pngconf.h
+++ b/components/external/libpng/pngconf.h
@@ -24,10 +24,10 @@
 #define PNG_MAX_MALLOC_64K
 #define PNG_NO_STDIO
 #define PNG_NO_ERROR_NUMBERS
+#define PNG_NO_WRITE_SUPPORTED
 #define PNG_ABORT() do { rt_kprintf("libpng abort.\n"); } while (0)
 
 #ifndef RT_USING_NEWLIB
-#define PNG_NO_WRITE_SUPPORTED
 #define PNG_NO_SETJMP_SUPPORTED
 #define malloc	rtgui_malloc
 #define free	rtgui_free

From 2c47f2e6838c713a9b64f0e9566b1ca24ad0a9b5 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Thu, 31 Jul 2014 13:53:57 +0800
Subject: [PATCH 77/86] Fix some spell error;

---
 libcpu/arm/cortex-m0/context_gcc.S  | 8 ++++----
 libcpu/arm/cortex-m0/context_iar.S  | 8 ++++----
 libcpu/arm/cortex-m0/context_rvds.S | 8 ++++----
 libcpu/arm/cortex-m3/context_gcc.S  | 8 ++++----
 libcpu/arm/cortex-m3/context_iar.S  | 8 ++++----
 libcpu/arm/cortex-m3/context_rvds.S | 8 ++++----
 libcpu/arm/cortex-m4/context_gcc.S  | 8 ++++----
 libcpu/arm/cortex-m4/context_iar.S  | 8 ++++----
 libcpu/arm/cortex-m4/context_rvds.S | 8 ++++----
 9 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index 997c345179..3186a5ae9f 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -79,8 +79,8 @@ _reswitch:
     STR     R1, [R0]
     BX      LR
 
-/* R0 --> swith from thread stack
- * R1 --> swith to thread stack
+/* R0 --> switch from thread stack
+ * R1 --> switch to thread stack
  * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
  */
     .global PendSV_Handler
@@ -103,7 +103,7 @@ PendSV_Handler:
     LDR     R0, =rt_interrupt_from_thread
     LDR     R1, [R0]
     CMP     R1, #0x00
-    BEQ     swtich_to_thread    /* skip register save at the first time */
+    BEQ     switch_to_thread    /* skip register save at the first time */
 
 	MRS     R1, PSP                 /* get from thread stack pointer */
 
@@ -118,7 +118,7 @@ PendSV_Handler:
     MOV     R6, R10
     MOV     R7, R11
     STMIA   R1!, {R4 - R7}          /* push thread {R8 - R11} high register to thread stack */
-swtich_to_thread:
+switch_to_thread:
     LDR     R1, =rt_interrupt_to_thread
     LDR     R1, [R1]
     LDR     R1, [R1]                /* load thread stack pointer */
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index f1318e552d..67ea808d8c 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -81,8 +81,8 @@ _reswitch
     STR     r1, [r0]
     BX      LR
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
     EXPORT PendSV_Handler
 PendSV_Handler:
@@ -104,7 +104,7 @@ PendSV_Handler:
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
     CMP     r1, #0x00
-    BEQ     swtich_to_thread        ; skip register save at the first time
+    BEQ     switch_to_thread        ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -120,7 +120,7 @@ PendSV_Handler:
     MOV     r7, r11
     STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index 9c2f42ac83..89ac029282 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -85,8 +85,8 @@ _reswitch
     BX      LR
     ENDP
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 PendSV_Handler    PROC
     EXPORT PendSV_Handler
@@ -108,7 +108,7 @@ PendSV_Handler    PROC
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
     CMP     r1, #0x00
-    BEQ     swtich_to_thread        ; skip register save at the first time
+    BEQ     switch_to_thread        ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -124,7 +124,7 @@ PendSV_Handler    PROC
     MOV     r7, r11
     STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S
index 7ff810d534..ca961bbd87 100644
--- a/libcpu/arm/cortex-m3/context_gcc.S
+++ b/libcpu/arm/cortex-m3/context_gcc.S
@@ -80,8 +80,8 @@ _reswitch:
     STR     R1, [R0]
     BX      LR
 
-/* R0 --> swith from thread stack
- * R1 --> swith to thread stack
+/* R0 --> switch from thread stack
+ * R1 --> switch to thread stack
  * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
  */
     .global PendSV_Handler
@@ -102,14 +102,14 @@ PendSV_Handler:
 
     LDR     R0, =rt_interrupt_from_thread
     LDR     R1, [R0]
-    CBZ     R1, swtich_to_thread    /* skip register save at the first time */
+    CBZ     R1, switch_to_thread    /* skip register save at the first time */
 
     MRS     R1, PSP                 /* get from thread stack pointer */
     STMFD   R1!, {R4 - R11}         /* push R4 - R11 register */
     LDR     R0, [R0]
     STR     R1, [R0]                /* update from thread stack pointer */
 
-swtich_to_thread:
+switch_to_thread:
     LDR     R1, =rt_interrupt_to_thread
     LDR     R1, [R1]
     LDR     R1, [R1]                /* load thread stack pointer */
diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S
index 7dc595f6c1..ad9fa0dd0f 100644
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@@ -81,8 +81,8 @@ _reswitch
     STR     r1, [r0]
     BX      LR
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
     EXPORT PendSV_Handler
 PendSV_Handler:
@@ -102,14 +102,14 @@ PendSV_Handler:
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
     STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index 7f431cc042..c86b70e1f9 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -84,8 +84,8 @@ _reswitch
     BX      LR
     ENDP
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 PendSV_Handler   PROC
     EXPORT PendSV_Handler
@@ -105,14 +105,14 @@ PendSV_Handler   PROC
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
     STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index 6a910355a8..908a44f847 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -82,8 +82,8 @@ _reswitch:
     STR r1, [r0]
     BX  LR
 
-/* r0 --> swith from thread stack
- * r1 --> swith to thread stack
+/* r0 --> switch from thread stack
+ * r1 --> switch to thread stack
  * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
  */
 .global PendSV_Handler
@@ -104,7 +104,7 @@ PendSV_Handler:
 
     LDR r0, =rt_interrupt_from_thread
     LDR r1, [r0]
-    CBZ r1, swtich_to_thread    /* skip register save at the first time */
+    CBZ r1, switch_to_thread    /* skip register save at the first time */
 
     MRS r1, psp                 /* get from thread stack pointer */
     
@@ -127,7 +127,7 @@ PendSV_Handler:
     LDR r0, [r0]
     STR r1, [r0]                /* update from thread stack pointer */
 
-swtich_to_thread:
+switch_to_thread:
     LDR r1, =rt_interrupt_to_thread
     LDR r1, [r1]
     LDR r1, [r1]                /* load thread stack pointer */
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index e882f36f64..8761a97052 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -82,8 +82,8 @@ _reswitch
     STR     r1, [r0]
     BX      LR
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
     EXPORT PendSV_Handler
 PendSV_Handler:
@@ -103,7 +103,7 @@ PendSV_Handler:
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -130,7 +130,7 @@ push_flag
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index 189ae33db1..af7461fd49 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -85,8 +85,8 @@ _reswitch
     BX      LR
     ENDP
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 PendSV_Handler   PROC
     EXPORT PendSV_Handler
@@ -106,7 +106,7 @@ PendSV_Handler   PROC
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -129,7 +129,7 @@ PendSV_Handler   PROC
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer

From 0fc1ac6189ce1ac2862e96099fbe1c4876a7cf80 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Thu, 31 Jul 2014 14:42:37 +0800
Subject: [PATCH 78/86] add more SPI device driver.

---
 components/drivers/spi/SConscript             |  24 +-
 components/drivers/spi/device_driver_list.txt |  15 +
 components/drivers/spi/enc28j60.c             | 876 ++++++++++++++++++
 components/drivers/spi/enc28j60.h             | 329 +++++++
 components/drivers/spi/spi_flash_at45dbxx.c   | 437 +++++++++
 components/drivers/spi/spi_flash_at45dbxx.h   |  17 +
 components/drivers/spi/spi_flash_sst25vfxx.c  | 346 +++++++
 components/drivers/spi/spi_flash_sst25vfxx.h  |  32 +
 components/drivers/spi/spi_flash_w25qxx.c     | 371 ++++++++
 components/drivers/spi/spi_flash_w25qxx.h     |  34 +
 components/drivers/spi/spi_wifi_rw009.c       | 590 ++++++++++++
 components/drivers/spi/spi_wifi_rw009.h       | 123 +++
 12 files changed, 3192 insertions(+), 2 deletions(-)
 create mode 100644 components/drivers/spi/device_driver_list.txt
 create mode 100644 components/drivers/spi/enc28j60.c
 create mode 100644 components/drivers/spi/enc28j60.h
 create mode 100644 components/drivers/spi/spi_flash_at45dbxx.c
 create mode 100644 components/drivers/spi/spi_flash_at45dbxx.h
 create mode 100644 components/drivers/spi/spi_flash_sst25vfxx.c
 create mode 100644 components/drivers/spi/spi_flash_sst25vfxx.h
 create mode 100644 components/drivers/spi/spi_flash_w25qxx.c
 create mode 100644 components/drivers/spi/spi_flash_w25qxx.h
 create mode 100644 components/drivers/spi/spi_wifi_rw009.c
 create mode 100644 components/drivers/spi/spi_wifi_rw009.h

diff --git a/components/drivers/spi/SConscript b/components/drivers/spi/SConscript
index f114ef7a41..f9fc82a777 100644
--- a/components/drivers/spi/SConscript
+++ b/components/drivers/spi/SConscript
@@ -1,8 +1,28 @@
 from building import *
 
-cwd     = GetCurrentDir()
-src	= Glob('*.c')
+cwd = GetCurrentDir()
+src = ['spi_core.c', 'spi_dev.c']
 CPPPATH = [cwd + '/../include']
+
+src_device = []
+
+if GetDepend('RT_USING_SPI_WIFI'):
+    src_device += ['spi_wifi_rw009.c']
+
+if GetDepend('RT_USING_W25QXX'):
+    src_device += ['spi_flash_w25qxx.c']
+
+if GetDepend('RT_USING_ENC28J60'):
+    src_device += ['enc28j60.c']
+
+if GetDepend('RT_USING_AT45DBXX'):
+    src_device += ['spi_flash_at45dbxx.c']
+
+if GetDepend('RT_USING_SST25VFXX'):
+    src_device += ['spi_flash_sst25vfxx.c']
+
+src += src_device
+
 group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SPI'], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/components/drivers/spi/device_driver_list.txt b/components/drivers/spi/device_driver_list.txt
new file mode 100644
index 0000000000..2c9d6a16b8
--- /dev/null
+++ b/components/drivers/spi/device_driver_list.txt
@@ -0,0 +1,15 @@
+spi_wifi_rw009.c/spi_wifi_rw009.h
+RW009
+http://www.rt-thread.com/
+
+enc28j60.c/enc28j60.h
+http://www.microchip.com/
+
+spi_flash_at45dbxx.c/spi_flash_at45dbxx.h
+http://www.atmel.com/
+
+spi_flash_sst25vfxx.c/spi_flash_sst25vfxx.h
+http://www.microchip.com/
+
+spi_flash_w25qxx.c/spi_flash_w25qxx.h
+http://www.winbond.com/
diff --git a/components/drivers/spi/enc28j60.c b/components/drivers/spi/enc28j60.c
new file mode 100644
index 0000000000..68f1181dcc
--- /dev/null
+++ b/components/drivers/spi/enc28j60.c
@@ -0,0 +1,876 @@
+#include "enc28j60.h"
+
+#define NET_TRACE
+#define ETH_RX_DUMP
+#define ETH_TX_DUMP
+
+#ifdef NET_TRACE
+#define NET_DEBUG         rt_kprintf
+#else
+#define NET_DEBUG(...)
+#endif /* #ifdef NET_TRACE */
+
+struct enc28j60_tx_list_typedef
+{
+    struct enc28j60_tx_list_typedef * prev;
+    struct enc28j60_tx_list_typedef * next;
+    rt_uint32_t addr; /* pkt addr in buffer */
+    rt_uint32_t len;  /* pkt len */
+    volatile rt_bool_t free; /* 0:busy, 1:free */
+};
+static struct enc28j60_tx_list_typedef enc28j60_tx_list[2];
+static volatile struct enc28j60_tx_list_typedef * tx_current;
+static volatile struct enc28j60_tx_list_typedef * tx_ack;
+static struct rt_event tx_event;
+
+/* private enc28j60 define */
+/* enc28j60 spi interface function */
+static uint8_t spi_read_op(struct rt_spi_device * spi_device, uint8_t op, uint8_t address);
+static void spi_write_op(struct rt_spi_device * spi_device, uint8_t op, uint8_t address, uint8_t data);
+
+static uint8_t spi_read(struct rt_spi_device * spi_device, uint8_t address);
+static void spi_write(struct rt_spi_device * spi_device, rt_uint8_t address, rt_uint8_t data);
+
+static void enc28j60_clkout(struct rt_spi_device * spi_device, rt_uint8_t clk);
+static void enc28j60_set_bank(struct rt_spi_device * spi_device, uint8_t address);
+static uint32_t enc28j60_interrupt_disable(struct rt_spi_device * spi_device);
+static void enc28j60_interrupt_enable(struct rt_spi_device * spi_device, uint32_t level);
+
+static uint16_t enc28j60_phy_read(struct rt_spi_device * spi_device, rt_uint8_t address);
+static void enc28j60_phy_write(struct rt_spi_device * spi_device, rt_uint8_t address, uint16_t data);
+static rt_bool_t enc28j60_check_link_status(struct rt_spi_device * spi_device);
+
+#define enc28j60_lock(dev)      rt_mutex_take(&((struct net_device*)dev)->lock, RT_WAITING_FOREVER);
+#define enc28j60_unlock(dev)    rt_mutex_release(&((struct net_device*)dev)->lock);
+
+static struct net_device  enc28j60_dev;
+static uint8_t  Enc28j60Bank;
+//struct rt_spi_device * spi_device;
+static uint16_t NextPacketPtr;
+
+static void _delay_us(uint32_t us)
+{
+    volatile uint32_t len;
+    for (; us > 0; us --)
+        for (len = 0; len < 20; len++ );
+}
+
+/* enc28j60 spi interface function */
+static uint8_t spi_read_op(struct rt_spi_device * spi_device, uint8_t op, uint8_t address)
+{
+    uint8_t send_buffer[2];
+    uint8_t recv_buffer[1];
+    uint32_t send_size = 1;
+
+    send_buffer[0] = op | (address & ADDR_MASK);
+    send_buffer[1] = 0xFF;
+
+    /* do dummy read if needed (for mac and mii, see datasheet page 29). */
+    if(address & 0x80)
+    {
+        send_size = 2;
+    }
+
+    rt_spi_send_then_recv(spi_device, send_buffer, send_size, recv_buffer, 1);
+    return (recv_buffer[0]);
+}
+
+static void spi_write_op(struct rt_spi_device * spi_device, uint8_t op, uint8_t address, uint8_t data)
+{
+    uint32_t level;
+    uint8_t buffer[2];
+
+    level = rt_hw_interrupt_disable();
+
+    buffer[0] = op | (address & ADDR_MASK);
+    buffer[1] = data;
+    rt_spi_send(spi_device, buffer, 2);
+
+    rt_hw_interrupt_enable(level);
+}
+
+/* enc28j60 function */
+static void enc28j60_clkout(struct rt_spi_device * spi_device, rt_uint8_t clk)
+{
+    /* setup clkout: 2 is 12.5MHz: */
+    spi_write(spi_device, ECOCON, clk & 0x7);
+}
+
+static void enc28j60_set_bank(struct rt_spi_device * spi_device, uint8_t address)
+{
+    /* set the bank (if needed) .*/
+    if((address & BANK_MASK) != Enc28j60Bank)
+    {
+        /* set the bank. */
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
+        Enc28j60Bank = (address & BANK_MASK);
+    }
+}
+
+static uint8_t spi_read(struct rt_spi_device * spi_device, uint8_t address)
+{
+    /* set the bank. */
+    enc28j60_set_bank(spi_device, address);
+    /* do the read. */
+    return spi_read_op(spi_device, ENC28J60_READ_CTRL_REG, address);
+}
+
+static void spi_write(struct rt_spi_device * spi_device, rt_uint8_t address, rt_uint8_t data)
+{
+    /* set the bank. */
+    enc28j60_set_bank(spi_device, address);
+    /* do the write. */
+    spi_write_op(spi_device, ENC28J60_WRITE_CTRL_REG, address, data);
+}
+
+static uint16_t enc28j60_phy_read(struct rt_spi_device * spi_device, rt_uint8_t address)
+{
+    uint16_t value;
+
+    /* Set the right address and start the register read operation. */
+    spi_write(spi_device, MIREGADR, address);
+    spi_write(spi_device, MICMD, MICMD_MIIRD);
+
+    _delay_us(15);
+
+    /* wait until the PHY read completes. */
+    while(spi_read(spi_device, MISTAT) & MISTAT_BUSY);
+
+    /* reset reading bit */
+    spi_write(spi_device, MICMD, 0x00);
+
+    value = spi_read(spi_device, MIRDL) | spi_read(spi_device, MIRDH)<<8;
+
+    return (value);
+}
+
+static void enc28j60_phy_write(struct rt_spi_device * spi_device, rt_uint8_t address, uint16_t data)
+{
+    /* set the PHY register address. */
+    spi_write(spi_device, MIREGADR, address);
+
+    /* write the PHY data. */
+    spi_write(spi_device, MIWRL, data);
+    spi_write(spi_device, MIWRH, data>>8);
+
+    /* wait until the PHY write completes. */
+    while(spi_read(spi_device, MISTAT) & MISTAT_BUSY)
+    {
+        _delay_us(15);
+    }
+}
+
+static uint32_t enc28j60_interrupt_disable(struct rt_spi_device * spi_device)
+{
+    uint32_t level;
+
+    /* switch to bank 0 */
+    enc28j60_set_bank(spi_device, EIE);
+
+    /* get last interrupt level */
+    level = spi_read(spi_device, EIE);
+    /* disable interrutps */
+    spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIE, level);
+
+    return level;
+}
+
+static void enc28j60_interrupt_enable(struct rt_spi_device * spi_device, uint32_t level)
+{
+    /* switch to bank 0 */
+    enc28j60_set_bank(spi_device, EIE);
+    spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, EIE, level);
+}
+
+/*
+ * Access the PHY to determine link status
+ */
+static rt_bool_t enc28j60_check_link_status(struct rt_spi_device * spi_device)
+{
+    uint16_t reg;
+    int duplex;
+
+    reg = enc28j60_phy_read(spi_device, PHSTAT2);
+    duplex = reg & PHSTAT2_DPXSTAT;
+
+    if (reg & PHSTAT2_LSTAT)
+    {
+        /* on */
+        return RT_TRUE;
+    }
+    else
+    {
+        /* off */
+        return RT_FALSE;
+    }
+}
+
+
+/************************* RT-Thread Device Interface *************************/
+void enc28j60_isr(void)
+{
+    eth_device_ready(&enc28j60_dev.parent);
+    NET_DEBUG("enc28j60_isr\r\n");
+}
+
+static void _tx_chain_init(void)
+{
+    enc28j60_tx_list[0].next = &enc28j60_tx_list[1];
+    enc28j60_tx_list[1].next = &enc28j60_tx_list[0];
+
+    enc28j60_tx_list[0].prev = &enc28j60_tx_list[1];
+    enc28j60_tx_list[1].prev = &enc28j60_tx_list[0];
+
+    enc28j60_tx_list[0].addr = TXSTART_INIT;
+    enc28j60_tx_list[1].addr = TXSTART_INIT + MAX_TX_PACKAGE_SIZE;
+
+    enc28j60_tx_list[0].free = RT_TRUE;
+    enc28j60_tx_list[1].free = RT_TRUE;
+
+    tx_current = &enc28j60_tx_list[0];
+    tx_ack = tx_current;
+}
+
+/* initialize the interface */
+static rt_err_t enc28j60_init(rt_device_t dev)
+{
+    struct net_device * enc28j60 = (struct net_device *)dev;
+    struct rt_spi_device * spi_device = enc28j60->spi_device;
+
+    enc28j60_lock(dev);
+
+    _tx_chain_init();
+
+    // perform system reset
+    spi_write_op(spi_device, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
+    rt_thread_delay(RT_TICK_PER_SECOND/50); /* delay 20ms */
+
+    NextPacketPtr = RXSTART_INIT;
+
+    // Rx start
+    spi_write(spi_device, ERXSTL, RXSTART_INIT&0xFF);
+    spi_write(spi_device, ERXSTH, RXSTART_INIT>>8);
+    // set receive pointer address
+    spi_write(spi_device, ERXRDPTL, RXSTOP_INIT&0xFF);
+    spi_write(spi_device, ERXRDPTH, RXSTOP_INIT>>8);
+    // RX end
+    spi_write(spi_device, ERXNDL, RXSTOP_INIT&0xFF);
+    spi_write(spi_device, ERXNDH, RXSTOP_INIT>>8);
+
+    // TX start
+    spi_write(spi_device, ETXSTL, TXSTART_INIT&0xFF);
+    spi_write(spi_device, ETXSTH, TXSTART_INIT>>8);
+    // set transmission pointer address
+    spi_write(spi_device, EWRPTL, TXSTART_INIT&0xFF);
+    spi_write(spi_device, EWRPTH, TXSTART_INIT>>8);
+    // TX end
+    spi_write(spi_device, ETXNDL, TXSTOP_INIT&0xFF);
+    spi_write(spi_device, ETXNDH, TXSTOP_INIT>>8);
+
+    // do bank 1 stuff, packet filter:
+    // For broadcast packets we allow only ARP packtets
+    // All other packets should be unicast only for our mac (MAADR)
+    //
+    // The pattern to match on is therefore
+    // Type     ETH.DST
+    // ARP      BROADCAST
+    // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
+    // in binary these poitions are:11 0000 0011 1111
+    // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
+    spi_write(spi_device, ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_BCEN);
+
+    // do bank 2 stuff
+    // enable MAC receive
+    spi_write(spi_device, MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
+    // enable automatic padding to 60bytes and CRC operations
+    // spi_write_op(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
+    spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
+    // bring MAC out of reset
+
+    // set inter-frame gap (back-to-back)
+    // spi_write(MABBIPG, 0x12);
+    spi_write(spi_device, MABBIPG, 0x15);
+
+    spi_write(spi_device, MACON4, MACON4_DEFER);
+    spi_write(spi_device, MACLCON2, 63);
+
+    // set inter-frame gap (non-back-to-back)
+    spi_write(spi_device, MAIPGL, 0x12);
+    spi_write(spi_device, MAIPGH, 0x0C);
+
+    // Set the maximum packet size which the controller will accept
+    // Do not send packets longer than MAX_FRAMELEN:
+    spi_write(spi_device, MAMXFLL, MAX_FRAMELEN&0xFF);
+    spi_write(spi_device, MAMXFLH, MAX_FRAMELEN>>8);
+
+    // do bank 3 stuff
+    // write MAC address
+    // NOTE: MAC address in ENC28J60 is byte-backward
+    spi_write(spi_device, MAADR0, enc28j60->dev_addr[5]);
+    spi_write(spi_device, MAADR1, enc28j60->dev_addr[4]);
+    spi_write(spi_device, MAADR2, enc28j60->dev_addr[3]);
+    spi_write(spi_device, MAADR3, enc28j60->dev_addr[2]);
+    spi_write(spi_device, MAADR4, enc28j60->dev_addr[1]);
+    spi_write(spi_device, MAADR5, enc28j60->dev_addr[0]);
+
+    /* output off */
+    spi_write(spi_device, ECOCON, 0x00);
+
+    // enc28j60_phy_write(PHCON1, 0x00);
+    enc28j60_phy_write(spi_device, PHCON1, PHCON1_PDPXMD); // full duplex
+    // no loopback of transmitted frames
+    enc28j60_phy_write(spi_device, PHCON2, PHCON2_HDLDIS);
+
+    enc28j60_set_bank(spi_device, ECON2);
+    spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC);
+
+    // switch to bank 0
+    enc28j60_set_bank(spi_device, ECON1);
+    // enable all interrutps
+    spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, EIE, 0xFF);
+    // enable packet reception
+    spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
+
+    /* clock out */
+    enc28j60_clkout(spi_device, 2);
+
+    enc28j60_phy_write(spi_device, PHLCON, 0xD76);	//0x476
+    rt_thread_delay(RT_TICK_PER_SECOND/50); /* delay 20ms */
+
+    enc28j60_unlock(dev);
+    return RT_EOK;
+}
+
+/* control the interface */
+static rt_err_t enc28j60_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    struct net_device * enc28j60 = (struct net_device *)dev;
+    switch(cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if(args) rt_memcpy(args, enc28j60->dev_addr, 6);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/* Open the ethernet interface */
+static rt_err_t enc28j60_open(rt_device_t dev, uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+/* Close the interface */
+static rt_err_t enc28j60_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+/* Read */
+static rt_size_t enc28j60_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return RT_EOK;
+}
+
+/* Write */
+static rt_size_t enc28j60_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+/* ethernet device interface */
+/* Transmit packet. */
+static rt_err_t enc28j60_tx( rt_device_t dev, struct pbuf* p)
+{
+    struct net_device * enc28j60 = (struct net_device *)dev;
+    struct rt_spi_device * spi_device = enc28j60->spi_device;
+    struct pbuf* q;
+    rt_uint32_t level;
+#ifdef ETH_TX_DUMP
+    rt_size_t dump_count = 0;
+    rt_uint8_t * dump_ptr;
+    rt_size_t dump_i;
+#endif
+
+    if(tx_current->free == RT_FALSE)
+    {
+        NET_DEBUG("[Tx] no empty buffer!\r\n");
+        while(tx_current->free == RT_FALSE)
+        {
+            rt_err_t result;
+            rt_uint32_t recved;
+
+            /* there is no block yet, wait a flag */
+            result = rt_event_recv(&tx_event, 0x01,
+                                   RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+
+            RT_ASSERT(result == RT_EOK);
+        }
+        NET_DEBUG("[Tx] wait empty buffer done!\r\n");
+    }
+
+    enc28j60_lock(dev);
+
+    /* disable enc28j60 interrupt */
+    level = enc28j60_interrupt_disable(spi_device);
+
+    // Set the write pointer to start of transmit buffer area
+//    spi_write(EWRPTL, TXSTART_INIT&0xFF);
+//    spi_write(EWRPTH, TXSTART_INIT>>8);
+    spi_write(spi_device, EWRPTL, (tx_current->addr)&0xFF);
+    spi_write(spi_device, EWRPTH, (tx_current->addr)>>8);
+    // Set the TXND pointer to correspond to the packet size given
+    tx_current->len = p->tot_len;
+//    spi_write(ETXNDL, (TXSTART_INIT+ p->tot_len + 1)&0xFF);
+//    spi_write(ETXNDH, (TXSTART_INIT+ p->tot_len + 1)>>8);
+
+    // write per-packet control byte (0x00 means use macon3 settings)
+    spi_write_op(spi_device, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
+
+#ifdef ETH_TX_DUMP
+    NET_DEBUG("tx_dump, size:%d\r\n", p->tot_len);
+#endif
+    for (q = p; q != NULL; q = q->next)
+    {
+        uint8_t cmd = ENC28J60_WRITE_BUF_MEM;
+        rt_spi_send_then_send(enc28j60->spi_device, &cmd, 1, q->payload, q->len);
+#ifdef ETH_RX_DUMP
+        dump_ptr = q->payload;
+        for(dump_i=0; dump_i<q->len; dump_i++)
+        {
+            NET_DEBUG("%02x ", *dump_ptr);
+            if( ((dump_count+1)%8) == 0 )
+            {
+                NET_DEBUG("  ");
+            }
+            if( ((dump_count+1)%16) == 0 )
+            {
+                NET_DEBUG("\r\n");
+            }
+            dump_count++;
+            dump_ptr++;
+        }
+#endif
+    }
+#ifdef ETH_RX_DUMP
+    NET_DEBUG("\r\n");
+#endif
+
+    // send the contents of the transmit buffer onto the network
+    if(tx_current == tx_ack)
+    {
+        NET_DEBUG("[Tx] stop, restart!\r\n");
+        // TX start
+        spi_write(spi_device, ETXSTL, (tx_current->addr)&0xFF);
+        spi_write(spi_device, ETXSTH, (tx_current->addr)>>8);
+        // TX end
+        spi_write(spi_device, ETXNDL, (tx_current->addr + tx_current->len)&0xFF);
+        spi_write(spi_device, ETXNDH, (tx_current->addr + tx_current->len)>>8);
+
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
+    }
+    else
+    {
+        NET_DEBUG("[Tx] busy, add to chain!\r\n");
+    }
+
+    tx_current->free = RT_FALSE;
+    tx_current = tx_current->next;
+
+    /* Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12. */
+    if( (spi_read(spi_device, EIR) & EIR_TXERIF) )
+    {
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
+    }
+
+    /* enable enc28j60 interrupt */
+    enc28j60_interrupt_enable(spi_device, level);
+
+    enc28j60_unlock(dev);
+
+    return RT_EOK;
+}
+
+/* recv packet. */
+static struct pbuf *enc28j60_rx(rt_device_t dev)
+{
+    struct net_device * enc28j60 = (struct net_device *)dev;
+    struct rt_spi_device * spi_device = enc28j60->spi_device;
+    struct pbuf* p = RT_NULL;
+
+    uint8_t eir, eir_clr;
+    uint32_t pk_counter;
+    rt_uint32_t level;
+    rt_uint32_t len;
+    rt_uint16_t rxstat;
+
+    enc28j60_lock(dev);
+
+    /* disable enc28j60 interrupt */
+    level = enc28j60_interrupt_disable(spi_device);
+
+    /* get EIR */
+    eir = spi_read(spi_device, EIR);
+
+    while(eir & ~EIR_PKTIF)
+    {
+        eir_clr = 0;
+
+        /* clear PKTIF */
+        if (eir & EIR_PKTIF)
+        {
+            NET_DEBUG("EIR_PKTIF\r\n");
+
+            /* switch to bank 0. */
+            enc28j60_set_bank(spi_device, EIE);
+            /* disable rx interrutps. */
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIE, EIE_PKTIE);
+            eir_clr |= EIR_PKTIF;
+//            enc28j60_set_bank(spi_device, EIR);
+//            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_PKTIF);
+        }
+
+        /* clear DMAIF */
+        if (eir & EIR_DMAIF)
+        {
+            NET_DEBUG("EIR_DMAIF\r\n");
+            eir_clr |= EIR_DMAIF;
+//            enc28j60_set_bank(spi_device, EIR);
+//            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_DMAIF);
+        }
+
+        /* LINK changed handler */
+        if ( eir & EIR_LINKIF)
+        {
+            rt_bool_t link_status;
+
+            NET_DEBUG("EIR_LINKIF\r\n");
+            link_status = enc28j60_check_link_status(spi_device);
+
+            /* read PHIR to clear the flag */
+            enc28j60_phy_read(spi_device, PHIR);
+            eir_clr |= EIR_LINKIF;
+//            enc28j60_set_bank(spi_device, EIR);
+//            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_LINKIF);
+
+            eth_device_linkchange(&(enc28j60->parent), link_status);
+        }
+
+        if (eir & EIR_TXIF)
+        {
+            /* A frame has been transmitted. */
+            enc28j60_set_bank(spi_device, EIR);
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXIF);
+
+            tx_ack->free = RT_TRUE;
+            tx_ack = tx_ack->next;
+            if(tx_ack->free == RT_FALSE)
+            {
+                NET_DEBUG("[tx isr] Tx chain not empty, continue send the next pkt!\r\n");
+                // TX start
+                spi_write(spi_device, ETXSTL, (tx_ack->addr)&0xFF);
+                spi_write(spi_device, ETXSTH, (tx_ack->addr)>>8);
+                // TX end
+                spi_write(spi_device, ETXNDL, (tx_ack->addr + tx_ack->len)&0xFF);
+                spi_write(spi_device, ETXNDH, (tx_ack->addr + tx_ack->len)>>8);
+
+                spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
+            }
+            else
+            {
+                NET_DEBUG("[tx isr] Tx chain empty, stop!\r\n");
+            }
+
+            /* set event */
+            rt_event_send(&tx_event, 0x01);
+        }
+
+        /* wake up handler */
+        if ( eir & EIR_WOLIF)
+        {
+            NET_DEBUG("EIR_WOLIF\r\n");
+            eir_clr |= EIR_WOLIF;
+//            enc28j60_set_bank(spi_device, EIR);
+//            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_WOLIF);
+        }
+
+        /* TX Error handler */
+        if ((eir & EIR_TXERIF) != 0)
+        {
+            NET_DEBUG("EIR_TXERIF re-start tx chain!\r\n");
+            enc28j60_set_bank(spi_device, ECON1);
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
+            eir_clr |= EIR_TXERIF;
+//            enc28j60_set_bank(spi_device, EIR);
+//            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF);
+
+            /* re-init tx chain */
+            _tx_chain_init();
+        }
+
+        /* RX Error handler */
+        if ((eir & EIR_RXERIF) != 0)
+        {
+            NET_DEBUG("EIR_RXERIF re-start rx!\r\n");
+
+            NextPacketPtr = RXSTART_INIT;
+            enc28j60_set_bank(spi_device, ECON1);
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXRST);
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXRST);
+            /* switch to bank 0. */
+            enc28j60_set_bank(spi_device, ECON1);
+            /* enable packet reception. */
+            spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
+            eir_clr |= EIR_RXERIF;
+//            enc28j60_set_bank(spi_device, EIR);
+//            spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_RXERIF);
+        }
+
+        enc28j60_set_bank(spi_device, EIR);
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, eir_clr);
+
+        eir = spi_read(spi_device, EIR);
+    }
+
+    /* read pkt */
+    pk_counter = spi_read(spi_device, EPKTCNT);
+    if(pk_counter)
+    {
+        /* Set the read pointer to the start of the received packet. */
+        spi_write(spi_device, ERDPTL, (NextPacketPtr));
+        spi_write(spi_device, ERDPTH, (NextPacketPtr)>>8);
+
+        /* read the next packet pointer. */
+        NextPacketPtr  = spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0);
+        NextPacketPtr |= spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0)<<8;
+
+        /* read the packet length (see datasheet page 43). */
+        len  = spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0);	    //0x54
+        len |= spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0)<<8;	//5554
+
+        len-=4; //remove the CRC count
+
+        // read the receive status (see datasheet page 43)
+        rxstat  = spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0);
+        rxstat |= ((rt_uint16_t)spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0))<<8;
+
+        // check CRC and symbol errors (see datasheet page 44, table 7-3):
+        // The ERXFCON.CRCEN is set by default. Normally we should not
+        // need to check this.
+        if ((rxstat & 0x80)==0)
+        {
+            // invalid
+            len=0;
+        }
+        else
+        {
+            /* allocation pbuf */
+            p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
+            if (p != RT_NULL)
+            {
+                struct pbuf* q;
+#ifdef ETH_RX_DUMP
+                rt_size_t dump_count = 0;
+                rt_uint8_t * dump_ptr;
+                rt_size_t dump_i;
+                NET_DEBUG("rx_dump, size:%d\r\n", len);
+#endif
+                for (q = p; q != RT_NULL; q= q->next)
+                {
+                    uint8_t cmd = ENC28J60_READ_BUF_MEM;
+                    rt_spi_send_then_recv(spi_device, &cmd, 1, q->payload, q->len);
+#ifdef ETH_RX_DUMP
+                    dump_ptr = q->payload;
+                    for(dump_i=0; dump_i<q->len; dump_i++)
+                    {
+                        NET_DEBUG("%02x ", *dump_ptr);
+                        if( ((dump_count+1)%8) == 0 )
+                        {
+                            NET_DEBUG("  ");
+                        }
+                        if( ((dump_count+1)%16) == 0 )
+                        {
+                            NET_DEBUG("\r\n");
+                        }
+                        dump_count++;
+                        dump_ptr++;
+                    }
+#endif
+                }
+#ifdef ETH_RX_DUMP
+                NET_DEBUG("\r\n");
+#endif
+            }
+        }
+
+        /* Move the RX read pointer to the start of the next received packet. */
+        /* This frees the memory we just read out. */
+        spi_write(spi_device, ERXRDPTL, (NextPacketPtr));
+        spi_write(spi_device, ERXRDPTH, (NextPacketPtr)>>8);
+
+        /* decrement the packet counter indicate we are done with this packet. */
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
+    }
+    else
+    {
+        /* switch to bank 0. */
+        enc28j60_set_bank(spi_device, ECON1);
+        /* enable packet reception. */
+        spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
+
+        level |= EIE_PKTIE;
+    }
+
+    /* enable enc28j60 interrupt */
+    enc28j60_interrupt_enable(spi_device, level);
+
+    enc28j60_unlock(dev);
+
+    return p;
+}
+
+rt_err_t enc28j60_attach(const char * spi_device_name)
+{
+    struct rt_spi_device * spi_device;
+
+    spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
+    if(spi_device == RT_NULL)
+    {
+        NET_DEBUG("spi device %s not found!\r\n", spi_device_name);
+        return -RT_ENOSYS;
+    }
+
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */
+        cfg.max_hz = 20 * 1000 * 1000; /* SPI Interface with Clock Speeds Up to 20 MHz */
+        rt_spi_configure(spi_device, &cfg);
+    } /* config spi */
+
+    memset(&enc28j60_dev, 0, sizeof(enc28j60_dev));
+
+    rt_event_init(&tx_event, "eth_tx", RT_IPC_FLAG_FIFO);
+    enc28j60_dev.spi_device = spi_device;
+
+    /* detect device */
+    {
+        uint16_t value;
+
+        /* perform system reset. */
+        spi_write_op(spi_device, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
+        rt_thread_delay(1); /* delay 20ms */
+
+        enc28j60_dev.emac_rev = spi_read(spi_device, EREVID);
+        value = enc28j60_phy_read(spi_device, PHHID2);
+        enc28j60_dev.phy_rev = value&0x0F;
+        enc28j60_dev.phy_pn = (value>>4)&0x3F;
+        enc28j60_dev.phy_id = (enc28j60_phy_read(spi_device, PHHID1) | ((value>>10)<<16))<<3;
+
+        if(enc28j60_dev.phy_id != 0x00280418)
+        {
+            NET_DEBUG("ENC28J60 PHY ID not correct!\r\n");
+            NET_DEBUG("emac_rev:%d\r\n", enc28j60_dev.emac_rev);
+            NET_DEBUG("phy_rev:%02X\r\n", enc28j60_dev.phy_rev);
+            NET_DEBUG("phy_pn:%02X\r\n", enc28j60_dev.phy_pn);
+            NET_DEBUG("phy_id:%08X\r\n", enc28j60_dev.phy_id);
+            return RT_EIO;
+        }
+    }
+
+    /* OUI 00-04-A3 (hex): Microchip Technology, Inc. */
+    enc28j60_dev.dev_addr[0] = 0x00;
+    enc28j60_dev.dev_addr[1] = 0x04;
+    enc28j60_dev.dev_addr[2] = 0xA3;
+    /* set MAC address, only for test */
+    enc28j60_dev.dev_addr[3] = 0x12;
+    enc28j60_dev.dev_addr[4] = 0x34;
+    enc28j60_dev.dev_addr[5] = 0x56;
+
+    /* init rt-thread device struct */
+    enc28j60_dev.parent.parent.type    = RT_Device_Class_NetIf;
+    enc28j60_dev.parent.parent.init    = enc28j60_init;
+    enc28j60_dev.parent.parent.open    = enc28j60_open;
+    enc28j60_dev.parent.parent.close   = enc28j60_close;
+    enc28j60_dev.parent.parent.read    = enc28j60_read;
+    enc28j60_dev.parent.parent.write   = enc28j60_write;
+    enc28j60_dev.parent.parent.control = enc28j60_control;
+
+    /* init rt-thread ethernet device struct */
+    enc28j60_dev.parent.eth_rx  = enc28j60_rx;
+    enc28j60_dev.parent.eth_tx  = enc28j60_tx;
+
+    rt_mutex_init(&enc28j60_dev.lock, "enc28j60", RT_IPC_FLAG_FIFO);
+
+    eth_device_init(&(enc28j60_dev.parent), "e0");
+
+    return RT_EOK;
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+/*
+ * Debug routine to dump useful register contents
+ */
+static void enc28j60(void)
+{
+    struct rt_spi_device * spi_device = enc28j60_dev.spi_device;
+    enc28j60_lock(&enc28j60_dev);
+
+    rt_kprintf("-- enc28j60 registers:\n");
+    rt_kprintf("HwRevID: 0x%02X\n", spi_read(spi_device, EREVID));
+
+    rt_kprintf("Cntrl: ECON1 ECON2 ESTAT  EIR  EIE\n");
+    rt_kprintf("       0x%02X  0x%02X  0x%02X  0x%02X  0x%02X\n",
+               spi_read(spi_device, ECON1),
+               spi_read(spi_device, ECON2),
+               spi_read(spi_device, ESTAT),
+               spi_read(spi_device, EIR),
+               spi_read(spi_device, EIE));
+
+    rt_kprintf("MAC  : MACON1 MACON3 MACON4\n");
+    rt_kprintf("       0x%02X   0x%02X   0x%02X\n",
+               spi_read(spi_device, MACON1),
+               spi_read(spi_device, MACON3),
+               spi_read(spi_device, MACON4));
+
+    rt_kprintf("Rx   : ERXST  ERXND  ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n");
+    rt_kprintf("       0x%04X 0x%04X 0x%04X  0x%04X  ",
+               (spi_read(spi_device, ERXSTH) << 8) | spi_read(spi_device, ERXSTL),
+               (spi_read(spi_device, ERXNDH) << 8) | spi_read(spi_device, ERXNDL),
+               (spi_read(spi_device, ERXWRPTH) << 8) | spi_read(spi_device, ERXWRPTL),
+               (spi_read(spi_device, ERXRDPTH) << 8) | spi_read(spi_device, ERXRDPTL));
+
+    rt_kprintf("0x%02X    0x%02X    0x%04X\n",
+               spi_read(spi_device, ERXFCON),
+               spi_read(spi_device, EPKTCNT),
+               (spi_read(spi_device, MAMXFLH) << 8) | spi_read(spi_device, MAMXFLL));
+
+    rt_kprintf("Tx   : ETXST  ETXND  MACLCON1 MACLCON2 MAPHSUP\n");
+    rt_kprintf("       0x%04X 0x%04X 0x%02X     0x%02X     0x%02X\n",
+               (spi_read(spi_device, ETXSTH) << 8) | spi_read(spi_device, ETXSTL),
+               (spi_read(spi_device, ETXNDH) << 8) | spi_read(spi_device, ETXNDL),
+               spi_read(spi_device, MACLCON1),
+               spi_read(spi_device, MACLCON2),
+               spi_read(spi_device, MAPHSUP));
+
+    rt_kprintf("PHY   : PHCON1 PHSTAT1\r\n");
+    rt_kprintf("        0x%04X 0x%04X\r\n",
+               enc28j60_phy_read(spi_device, PHCON1),
+               enc28j60_phy_read(spi_device, PHSTAT1));
+
+    enc28j60_unlock(&enc28j60_dev);
+}
+FINSH_FUNCTION_EXPORT(enc28j60, dump enc28j60 registers);
+#endif
diff --git a/components/drivers/spi/enc28j60.h b/components/drivers/spi/enc28j60.h
new file mode 100644
index 0000000000..8c647d5fc2
--- /dev/null
+++ b/components/drivers/spi/enc28j60.h
@@ -0,0 +1,329 @@
+#ifndef EN28J60_H_INCLUDED
+#define EN28J60_H_INCLUDED
+
+#include <stdint.h>
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+#include <netif/ethernetif.h>
+
+// ENC28J60 Control Registers
+// Control register definitions are a combination of address,
+// bank number, and Ethernet/MAC/PHY indicator bits.
+// - Register address        (bits 0-4)
+// - Bank number        (bits 5-6)
+// - MAC/PHY indicator        (bit 7)
+#define ADDR_MASK        0x1F
+#define BANK_MASK        0x60
+#define SPRD_MASK        0x80
+// All-bank registers
+#define EIE              0x1B
+#define EIR              0x1C
+#define ESTAT            0x1D
+#define ECON2            0x1E
+#define ECON1            0x1F
+// Bank 0 registers
+#define ERDPTL           (0x00|0x00)
+#define ERDPTH           (0x01|0x00)
+#define EWRPTL           (0x02|0x00)
+#define EWRPTH           (0x03|0x00)
+#define ETXSTL           (0x04|0x00)
+#define ETXSTH           (0x05|0x00)
+#define ETXNDL           (0x06|0x00)
+#define ETXNDH           (0x07|0x00)
+#define ERXSTL           (0x08|0x00)
+#define ERXSTH           (0x09|0x00)
+#define ERXNDL           (0x0A|0x00)
+#define ERXNDH           (0x0B|0x00)
+#define ERXRDPTL         (0x0C|0x00)
+#define ERXRDPTH         (0x0D|0x00)
+#define ERXWRPTL         (0x0E|0x00)
+#define ERXWRPTH         (0x0F|0x00)
+#define EDMASTL          (0x10|0x00)
+#define EDMASTH          (0x11|0x00)
+#define EDMANDL          (0x12|0x00)
+#define EDMANDH          (0x13|0x00)
+#define EDMADSTL         (0x14|0x00)
+#define EDMADSTH         (0x15|0x00)
+#define EDMACSL          (0x16|0x00)
+#define EDMACSH          (0x17|0x00)
+// Bank 1 registers
+#define EHT0             (0x00|0x20)
+#define EHT1             (0x01|0x20)
+#define EHT2             (0x02|0x20)
+#define EHT3             (0x03|0x20)
+#define EHT4             (0x04|0x20)
+#define EHT5             (0x05|0x20)
+#define EHT6             (0x06|0x20)
+#define EHT7             (0x07|0x20)
+#define EPMM0            (0x08|0x20)
+#define EPMM1            (0x09|0x20)
+#define EPMM2            (0x0A|0x20)
+#define EPMM3            (0x0B|0x20)
+#define EPMM4            (0x0C|0x20)
+#define EPMM5            (0x0D|0x20)
+#define EPMM6            (0x0E|0x20)
+#define EPMM7            (0x0F|0x20)
+#define EPMCSL           (0x10|0x20)
+#define EPMCSH           (0x11|0x20)
+#define EPMOL            (0x14|0x20)
+#define EPMOH            (0x15|0x20)
+#define EWOLIE           (0x16|0x20)
+#define EWOLIR           (0x17|0x20)
+#define ERXFCON          (0x18|0x20)
+#define EPKTCNT          (0x19|0x20)
+// Bank 2 registers
+#define MACON1           (0x00|0x40|0x80)
+#define MACON2           (0x01|0x40|0x80)
+#define MACON3           (0x02|0x40|0x80)
+#define MACON4           (0x03|0x40|0x80)
+#define MABBIPG          (0x04|0x40|0x80)
+#define MAIPGL           (0x06|0x40|0x80)
+#define MAIPGH           (0x07|0x40|0x80)
+#define MACLCON1         (0x08|0x40|0x80)
+#define MACLCON2         (0x09|0x40|0x80)
+#define MAMXFLL          (0x0A|0x40|0x80)
+#define MAMXFLH          (0x0B|0x40|0x80)
+#define MAPHSUP          (0x0D|0x40|0x80)
+#define MICON            (0x11|0x40|0x80)
+#define MICMD            (0x12|0x40|0x80)
+#define MIREGADR         (0x14|0x40|0x80)
+#define MIWRL            (0x16|0x40|0x80)
+#define MIWRH            (0x17|0x40|0x80)
+#define MIRDL            (0x18|0x40|0x80)
+#define MIRDH            (0x19|0x40|0x80)
+// Bank 3 registers
+#define MAADR1           (0x00|0x60|0x80)
+#define MAADR0           (0x01|0x60|0x80)
+#define MAADR3           (0x02|0x60|0x80)
+#define MAADR2           (0x03|0x60|0x80)
+#define MAADR5           (0x04|0x60|0x80)
+#define MAADR4           (0x05|0x60|0x80)
+#define EBSTSD           (0x06|0x60)
+#define EBSTCON          (0x07|0x60)
+#define EBSTCSL          (0x08|0x60)
+#define EBSTCSH          (0x09|0x60)
+#define MISTAT           (0x0A|0x60|0x80)
+#define EREVID           (0x12|0x60)
+#define ECOCON           (0x15|0x60)
+#define EFLOCON          (0x17|0x60)
+#define EPAUSL           (0x18|0x60)
+#define EPAUSH           (0x19|0x60)
+// PHY registers
+#define PHCON1           0x00
+#define PHSTAT1          0x01
+#define PHHID1           0x02
+#define PHHID2           0x03
+#define PHCON2           0x10
+#define PHSTAT2          0x11
+#define PHIE             0x12
+#define PHIR             0x13
+#define PHLCON           0x14
+
+// ENC28J60 ERXFCON Register Bit Definitions
+#define ERXFCON_UCEN     0x80
+#define ERXFCON_ANDOR    0x40
+#define ERXFCON_CRCEN    0x20
+#define ERXFCON_PMEN     0x10
+#define ERXFCON_MPEN     0x08
+#define ERXFCON_HTEN     0x04
+#define ERXFCON_MCEN     0x02
+#define ERXFCON_BCEN     0x01
+// ENC28J60 EIE Register Bit Definitions
+#define EIE_INTIE        0x80
+#define EIE_PKTIE        0x40
+#define EIE_DMAIE        0x20
+#define EIE_LINKIE       0x10
+#define EIE_TXIE         0x08
+#define EIE_WOLIE        0x04
+#define EIE_TXERIE       0x02
+#define EIE_RXERIE       0x01
+// ENC28J60 EIR Register Bit Definitions
+#define EIR_PKTIF        0x40
+#define EIR_DMAIF        0x20
+#define EIR_LINKIF       0x10
+#define EIR_TXIF         0x08
+#define EIR_WOLIF        0x04
+#define EIR_TXERIF       0x02
+#define EIR_RXERIF       0x01
+// ENC28J60 ESTAT Register Bit Definitions
+#define ESTAT_INT        0x80
+#define ESTAT_LATECOL    0x10
+#define ESTAT_RXBUSY     0x04
+#define ESTAT_TXABRT     0x02
+#define ESTAT_CLKRDY     0x01
+// ENC28J60 ECON2 Register Bit Definitions
+#define ECON2_AUTOINC    0x80
+#define ECON2_PKTDEC     0x40
+#define ECON2_PWRSV      0x20
+#define ECON2_VRPS       0x08
+// ENC28J60 ECON1 Register Bit Definitions
+#define ECON1_TXRST      0x80
+#define ECON1_RXRST      0x40
+#define ECON1_DMAST      0x20
+#define ECON1_CSUMEN     0x10
+#define ECON1_TXRTS      0x08
+#define ECON1_RXEN       0x04
+#define ECON1_BSEL1      0x02
+#define ECON1_BSEL0      0x01
+// ENC28J60 MACON1 Register Bit Definitions
+#define MACON1_LOOPBK    0x10
+#define MACON1_TXPAUS    0x08
+#define MACON1_RXPAUS    0x04
+#define MACON1_PASSALL   0x02
+#define MACON1_MARXEN    0x01
+// ENC28J60 MACON2 Register Bit Definitions
+#define MACON2_MARST     0x80
+#define MACON2_RNDRST    0x40
+#define MACON2_MARXRST   0x08
+#define MACON2_RFUNRST   0x04
+#define MACON2_MATXRST   0x02
+#define MACON2_TFUNRST   0x01
+// ENC28J60 MACON3 Register Bit Definitions
+#define MACON3_PADCFG2   0x80
+#define MACON3_PADCFG1   0x40
+#define MACON3_PADCFG0   0x20
+#define MACON3_TXCRCEN   0x10
+#define MACON3_PHDRLEN   0x08
+#define MACON3_HFRMLEN   0x04
+#define MACON3_FRMLNEN   0x02
+#define MACON3_FULDPX    0x01
+// ENC28J60 MACON4 Register Bit Definitions
+#define	MACON4_DEFER	(1<<6)
+#define	MACON4_BPEN		(1<<5)
+#define	MACON4_NOBKOFF	(1<<4)
+// ENC28J60 MICMD Register Bit Definitions
+#define MICMD_MIISCAN    0x02
+#define MICMD_MIIRD      0x01
+// ENC28J60 MISTAT Register Bit Definitions
+#define MISTAT_NVALID    0x04
+#define MISTAT_SCAN      0x02
+#define MISTAT_BUSY      0x01
+// ENC28J60 PHY PHCON1 Register Bit Definitions
+#define PHCON1_PRST      0x8000
+#define PHCON1_PLOOPBK   0x4000
+#define PHCON1_PPWRSV    0x0800
+#define PHCON1_PDPXMD    0x0100
+// ENC28J60 PHY PHSTAT1 Register Bit Definitions
+#define PHSTAT1_PFDPX    0x1000
+#define PHSTAT1_PHDPX    0x0800
+#define PHSTAT1_LLSTAT   0x0004
+#define PHSTAT1_JBSTAT   0x0002
+/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
+#define PHSTAT2_TXSTAT	(1 << 13)
+#define PHSTAT2_RXSTAT	(1 << 12)
+#define PHSTAT2_COLSTAT	(1 << 11)
+#define PHSTAT2_LSTAT	(1 << 10)
+#define PHSTAT2_DPXSTAT	(1 << 9)
+#define PHSTAT2_PLRITY	(1 << 5)
+// ENC28J60 PHY PHCON2 Register Bit Definitions
+#define PHCON2_FRCLINK   0x4000
+#define PHCON2_TXDIS     0x2000
+#define PHCON2_JABBER    0x0400
+#define PHCON2_HDLDIS    0x0100
+
+// ENC28J60 Packet Control Byte Bit Definitions
+#define PKTCTRL_PHUGEEN  0x08
+#define PKTCTRL_PPADEN   0x04
+#define PKTCTRL_PCRCEN   0x02
+#define PKTCTRL_POVERRIDE 0x01
+
+/* ENC28J60 Transmit Status Vector */
+#define TSV_TXBYTECNT           0
+#define TSV_TXCOLLISIONCNT      16
+#define TSV_TXCRCERROR          20
+#define TSV_TXLENCHKERROR       21
+#define TSV_TXLENOUTOFRANGE     22
+#define TSV_TXDONE              23
+#define TSV_TXMULTICAST         24
+#define TSV_TXBROADCAST         25
+#define TSV_TXPACKETDEFER       26
+#define TSV_TXEXDEFER           27
+#define TSV_TXEXCOLLISION       28
+#define TSV_TXLATECOLLISION     29
+#define TSV_TXGIANT             30
+#define TSV_TXUNDERRUN          31
+#define TSV_TOTBYTETXONWIRE     32
+#define TSV_TXCONTROLFRAME      48
+#define TSV_TXPAUSEFRAME        49
+#define TSV_BACKPRESSUREAPP     50
+#define TSV_TXVLANTAGFRAME      51
+
+#define TSV_SIZE                7
+#define TSV_BYTEOF(x)           ((x) / 8)
+#define TSV_BITMASK(x)          (1 << ((x) % 8))
+#define TSV_GETBIT(x, y)        (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
+
+/* ENC28J60 Receive Status Vector */
+#define RSV_RXLONGEVDROPEV      16
+#define RSV_CARRIEREV           18
+#define RSV_CRCERROR            20
+#define RSV_LENCHECKERR         21
+#define RSV_LENOUTOFRANGE       22
+#define RSV_RXOK                23
+#define RSV_RXMULTICAST         24
+#define RSV_RXBROADCAST         25
+#define RSV_DRIBBLENIBBLE       26
+#define RSV_RXCONTROLFRAME      27
+#define RSV_RXPAUSEFRAME        28
+#define RSV_RXUNKNOWNOPCODE     29
+#define RSV_RXTYPEVLAN          30
+
+#define RSV_SIZE                6
+#define RSV_BITMASK(x)          (1 << ((x) - 16))
+#define RSV_GETBIT(x, y)        (((x) & RSV_BITMASK(y)) ? 1 : 0)
+
+// SPI operation codes
+#define ENC28J60_READ_CTRL_REG       0x00
+#define ENC28J60_READ_BUF_MEM        0x3A
+#define ENC28J60_WRITE_CTRL_REG      0x40
+#define ENC28J60_WRITE_BUF_MEM       0x7A
+#define ENC28J60_BIT_FIELD_SET       0x80
+#define ENC28J60_BIT_FIELD_CLR       0xA0
+#define ENC28J60_SOFT_RESET          0xFF
+
+// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
+// buffer boundaries applied to internal 8K ram
+// the entire available packet buffer space is allocated
+//
+
+#define MAX_TX_PACKAGE_SIZE    (1536)
+
+// start with recbuf at 0/
+#define RXSTART_INIT	0x0
+// receive buffer end
+#define RXSTOP_INIT		(0x1FFF - MAX_TX_PACKAGE_SIZE*2) - 1
+// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
+
+#define TXSTART_INIT	(0x1FFF - MAX_TX_PACKAGE_SIZE*2)
+// stp TX buffer at end of mem
+#define TXSTOP_INIT		0x1FFF
+
+// max frame length which the conroller will accept:
+#define MAX_FRAMELEN	1518
+
+#define MAX_ADDR_LEN    6
+
+struct net_device
+{
+	/* inherit from ethernet device */
+	struct eth_device parent;
+
+	/* interface address info. */
+	rt_uint8_t  dev_addr[MAX_ADDR_LEN]; /* hw address	*/
+
+	rt_uint8_t emac_rev;
+	rt_uint8_t phy_rev;
+	rt_uint8_t phy_pn;
+	rt_uint32_t phy_id;
+
+	/* spi device */
+	struct rt_spi_device * spi_device;
+	struct rt_mutex lock;
+};
+
+/* export function */
+extern rt_err_t enc28j60_attach(const char * spi_device_name);
+extern void enc28j60_isr(void);
+
+#endif // EN28J60_H_INCLUDED
diff --git a/components/drivers/spi/spi_flash_at45dbxx.c b/components/drivers/spi/spi_flash_at45dbxx.c
new file mode 100644
index 0000000000..be474f7c65
--- /dev/null
+++ b/components/drivers/spi/spi_flash_at45dbxx.c
@@ -0,0 +1,437 @@
+/*
+ * File      : rtdef.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-12-16     aozima       the first version
+ */
+
+#include <stdint.h>
+#include "spi_flash_at45dbxx.h"
+
+#define FLASH_DEBUG
+#define DMA_BUFFER_SIZE                         512
+
+#ifdef FLASH_DEBUG
+#define FLASH_TRACE         rt_kprintf
+#else
+#define FLASH_TRACE(...)
+#endif /**< #ifdef FLASH_DEBUG */
+
+/* JEDEC Manufacturer¡¯s ID */
+#define MF_ID                (0x1F) /* atmel */
+#define DENSITY_CODE_011D    (0x02) /* AT45DB011D Density Code : 00010 = 1-Mbit */
+#define DENSITY_CODE_021D    (0x03) /* AT45DB021D Density Code : 00011 = 2-Mbit */
+#define DENSITY_CODE_041D    (0x04) /* AT45DB041D Density Code : 00100 = 4-Mbit */
+#define DENSITY_CODE_081D    (0x05) /* AT45DB081D Density Code : 00101 = 8-Mbit */
+#define DENSITY_CODE_161D    (0x06) /* AT45DB161D Density Code : 00110 = 16-Mbit */
+#define DENSITY_CODE_321D    (0x07) /* AT45DB321D Density Code : 00111 = 32-Mbit */
+#define DENSITY_CODE_642D    (0x08) /* AT45DB642D Density Code : 01000 = 64-Mbit */
+
+struct JEDEC_ID
+{
+    uint8_t manufacturer_id;          /* Manufacturer ID */
+    uint8_t density_code:5; /* Density Code */
+    uint8_t family_code:3;  /* Family Code */
+    uint8_t version_code:5; /* Product Version Code */
+    uint8_t mlc_code:3;     /* MLC Code */
+    uint8_t byte_count;     /* Byte Count */
+};
+
+#define AT45DB_BUFFER_1_WRITE                 0x84
+#define AT45DB_BUFFER_2_WRITE                 0x87
+#define AT45DB_BUFFER_1_READ                  0xD4
+#define AT45DB_BUFFER_2_READ                  0xD6
+#define AT45DB_B1_TO_MM_PAGE_PROG_WITH_ERASE  0x83
+#define AT45DB_B2_TO_MM_PAGE_PROG_WITH_ERASE  0x86
+#define AT45DB_MM_PAGE_TO_B1_XFER             0x53
+#define AT45DB_MM_PAGE_TO_B2_XFER             0x55
+#define AT45DB_PAGE_ERASE                     0x81
+#define AT45DB_SECTOR_ERASE                   0x7C
+#define AT45DB_READ_STATE_REGISTER            0xD7
+#define AT45DB_MM_PAGE_READ                   0xD2
+#define AT45DB_MM_PAGE_PROG_THRU_BUFFER1      0x82
+#define AT45DB_CMD_JEDEC_ID                   0x9F
+
+static struct spi_flash_at45dbxx  spi_flash_at45dbxx;
+
+/*****************************************************************************/
+/*Status Register Format:                                   */
+/* ------------------------------------------------------------------------- */
+/* | bit7   | bit6   | bit5   | bit4   | bit3   | bit2   | bit1   | bit0   | */
+/* |--------|--------|--------|--------|--------|--------|--------|--------| */
+/* |RDY/BUSY| COMP   |         device density            |   X    |   X    | */
+/* ------------------------------------------------------------------------- */
+/* 0:busy   |        |        AT45DB041:0111             | protect|page size */
+/* 1:ready  |        |        AT45DB161:1011             |                   */
+/* --------------------------------------------------------------------------*/
+/*****************************************************************************/
+static uint8_t AT45DB_StatusRegisterRead(void)
+{
+    return rt_spi_sendrecv8(spi_flash_at45dbxx.rt_spi_device, AT45DB_READ_STATE_REGISTER);
+}
+
+static void wait_busy(void)
+{
+    uint16_t i = 0;
+    while (i++ < 10000)
+    {
+        if (AT45DB_StatusRegisterRead() & 0x80)
+        {
+            return;
+        }
+    }
+    FLASH_TRACE("\r\nSPI_FLASH timeout!!!\r\n");
+}
+
+/* RT-Thread Device Driver Interface */
+static rt_err_t AT45DB_flash_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t AT45DB_flash_open(rt_device_t dev, rt_uint16_t oflag)
+{
+
+    return RT_EOK;
+}
+
+static rt_err_t AT45DB_flash_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t AT45DB_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    {
+        struct rt_device_blk_geometry *geometry;
+
+        geometry = (struct rt_device_blk_geometry *)args;
+        if (geometry == RT_NULL) return -RT_ERROR;
+
+        geometry->bytes_per_sector = 512;
+        geometry->sector_count = 4096;
+        geometry->block_size = 4096; /* block erase: 4k */
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t AT45DB_flash_read_page_256(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    uint32_t index, nr;
+    uint8_t * read_buffer = buffer;
+
+    nr = size;
+
+    for (index = 0; index < nr; index++)
+    {
+        uint32_t  page = pos;
+        uint8_t send_buffer[8];
+        uint32_t i;
+
+        for(i=0; i<sizeof(send_buffer); i++)
+        {
+            send_buffer[i] = 0;
+        }
+
+        send_buffer[0] = AT45DB_MM_PAGE_READ;
+        send_buffer[1] = (uint8_t)(page >> 7);
+        send_buffer[2] = (uint8_t)(page << 1);
+
+        rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, send_buffer, 8, read_buffer, 256);
+        read_buffer += 256;
+        page++;
+    }
+
+    return size;
+}
+
+static rt_size_t AT45DB_flash_read_page_512(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    uint32_t index, nr;
+    uint8_t * read_buffer = buffer;
+
+    nr = size;
+
+    for (index = 0; index < nr; index++)
+    {
+        uint32_t  page = pos;
+        uint8_t send_buffer[8];
+        uint32_t i;
+
+        for(i=0; i<sizeof(send_buffer); i++)
+        {
+            send_buffer[i] = 0;
+        }
+
+        send_buffer[0] = AT45DB_MM_PAGE_READ;
+        send_buffer[1] = (uint8_t)(page >> 6);
+        send_buffer[2] = (uint8_t)(page << 2);
+
+        rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, send_buffer, 8, read_buffer, 512);
+        read_buffer += 512;
+        page++;
+    }
+
+    return size;
+}
+
+static rt_size_t AT45DB_flash_read_page_1024(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    uint32_t index, nr;
+    uint8_t * read_buffer = buffer;
+
+    nr = size;
+
+    for (index = 0; index < nr; index++)
+    {
+        uint32_t  page = pos;
+        uint8_t send_buffer[8];
+        uint32_t i;
+
+        for(i=0; i<sizeof(send_buffer); i++)
+        {
+            send_buffer[i] = 0;
+        }
+
+        send_buffer[0] = AT45DB_MM_PAGE_READ;
+        send_buffer[1] = (uint8_t)(page >> 5);
+        send_buffer[2] = (uint8_t)(page << 3);
+
+        rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, send_buffer, 8, read_buffer, 1024);
+        read_buffer += 1024;
+        page++;
+    }
+
+    return size;
+}
+
+static rt_size_t AT45DB_flash_write_page_256(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    rt_uint32_t index, nr;
+    const uint8_t * write_buffer = buffer;
+
+    nr = size;
+
+    for (index = 0; index < nr; index++)
+    {
+        uint32_t  page = pos;
+        uint8_t send_buffer[4];
+
+        send_buffer[0] = AT45DB_MM_PAGE_PROG_THRU_BUFFER1;
+        send_buffer[1] = (uint8_t) (page >> 7);
+        send_buffer[2] = (uint8_t) (page << 1);
+        send_buffer[3] = 0;
+
+        rt_spi_send_then_send(spi_flash_at45dbxx.rt_spi_device, send_buffer, 4, write_buffer, 256);
+
+        write_buffer += 256;
+        page++;
+
+        wait_busy();
+    }
+
+    return size;
+}
+
+static rt_size_t AT45DB_flash_write_page_512(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    rt_uint32_t index, nr;
+    const uint8_t * write_buffer = buffer;
+
+    nr = size;
+
+    for (index = 0; index < nr; index++)
+    {
+        uint32_t  page = pos;
+        uint8_t send_buffer[4];
+
+        send_buffer[0] = AT45DB_MM_PAGE_PROG_THRU_BUFFER1;
+        send_buffer[1] = (uint8_t) (page >> 6);
+        send_buffer[2] = (uint8_t) (page << 2);
+        send_buffer[3] = 0;
+
+        rt_spi_send_then_send(spi_flash_at45dbxx.rt_spi_device, send_buffer, 4, write_buffer, 512);
+
+        write_buffer += 512;
+        page++;
+
+        wait_busy();
+    }
+
+    return size;
+}
+
+static rt_size_t AT45DB_flash_write_page_1024(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    rt_uint32_t index, nr;
+    const uint8_t * write_buffer = buffer;
+
+    nr = size;
+
+    for (index = 0; index < nr; index++)
+    {
+        uint32_t  page = pos;
+        uint8_t send_buffer[4];
+
+        send_buffer[0] = AT45DB_MM_PAGE_PROG_THRU_BUFFER1;
+        send_buffer[1] = (uint8_t) (page >> 5);
+        send_buffer[2] = (uint8_t) (page << 3);
+        send_buffer[3] = 0;
+
+        rt_spi_send_then_send(spi_flash_at45dbxx.rt_spi_device, send_buffer, 4, write_buffer, 1024);
+
+        write_buffer += 1024;
+        page++;
+
+        wait_busy();
+    }
+
+    return size;
+}
+
+rt_err_t at45dbxx_init(const char * flash_device_name, const char * spi_device_name)
+{
+    struct rt_spi_device * rt_spi_device;
+    struct JEDEC_ID * JEDEC_ID;
+
+    rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
+    if(rt_spi_device == RT_NULL)
+    {
+        FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
+        return -RT_ENOSYS;
+    }
+    spi_flash_at45dbxx.rt_spi_device = rt_spi_device;
+
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 and 3 */
+        cfg.max_hz = 66000000; /* Atmel RapidS Serial Interface: 66MHz Maximum Clock Frequency */
+        rt_spi_configure(spi_flash_at45dbxx.rt_spi_device, &cfg);
+    }
+
+    /* read JEDEC ID */
+    {
+        uint8_t cmd;
+        uint8_t id_recv[6];
+        JEDEC_ID = (struct JEDEC_ID *)id_recv;
+
+        cmd = AT45DB_CMD_JEDEC_ID;
+        rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, &cmd, 1, id_recv, 6);
+
+        /**< 1FH = Atmel */
+        /**< 001 = Atmel DataFlash */
+        if(JEDEC_ID->manufacturer_id != 0x1F || JEDEC_ID->family_code != 0x01)
+        {
+            FLASH_TRACE("Manufacturer¡¯s ID or Memory Type error!\r\n");
+            FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
+            return -RT_ENOSYS;
+        }
+
+        if(JEDEC_ID->density_code == DENSITY_CODE_011D)
+        {
+            /**< AT45DB011D Density Code : 00010 = 1-Mbit */
+            FLASH_TRACE("AT45DB011D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
+            spi_flash_at45dbxx.geometry.sector_count = 512;     /* 1-Mbit / 8 / 256 = 512 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*2;    /* Block Erase (2-Kbytes) */
+        }
+        else if(JEDEC_ID->density_code == DENSITY_CODE_021D)
+        {
+            /**< AT45DB021D Density Code : 00011 = 2-Mbit */
+            FLASH_TRACE("AT45DB021D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
+            spi_flash_at45dbxx.geometry.sector_count = 512*2;   /* 2-Mbit / 8 / 256 = 1024 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*2;    /* Block Erase (2-Kbytes) */
+        }
+        else if(JEDEC_ID->density_code == DENSITY_CODE_041D)
+        {
+            /**< AT45DB041D Density Code : 00100 = 4-Mbit */
+            FLASH_TRACE("AT45DB041D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
+            spi_flash_at45dbxx.geometry.sector_count = 512*4;   /* 4-Mbit / 8 / 256 = 2048 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*2;    /* Block Erase (2-Kbytes) */
+        }
+        else if(JEDEC_ID->density_code == DENSITY_CODE_081D)
+        {
+            /**< AT45DB081D Density Code : 00101 = 8-Mbit */
+            FLASH_TRACE("AT45DB081D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
+            spi_flash_at45dbxx.geometry.sector_count = 512*8;   /* 8-Mbit / 8 / 256 = 4096 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*2;    /* Block Erase (2-Kbytes) */
+        }
+        else if(JEDEC_ID->density_code == DENSITY_CODE_161D)
+        {
+            /**< AT45DB161D Density Code : 00110 = 16-Mbit */
+            FLASH_TRACE("AT45DB161D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 512; /* Page Erase (512 Bytes) */
+            spi_flash_at45dbxx.geometry.sector_count = 256*16;  /* 16-Mbit / 8 / 512 = 4096 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*4;    /* Block Erase (4-Kbytes) */
+        }
+        else if(JEDEC_ID->density_code == DENSITY_CODE_321D)
+        {
+            /**< AT45DB321D Density Code : 00111 = 32-Mbit */
+            FLASH_TRACE("AT45DB321D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 512; /* Page Erase (512 Bytes) */
+            spi_flash_at45dbxx.geometry.sector_count = 256*32;  /* 32-Mbit / 8 / 512 = 8192 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*4;    /* Block Erase (4-Kbytes) */
+        }
+        else if(JEDEC_ID->density_code == DENSITY_CODE_642D)
+        {
+            /**< AT45DB642D Density Code : 01000 = 64-Mbit */
+            FLASH_TRACE("AT45DB642D detection\r\n");
+            spi_flash_at45dbxx.geometry.bytes_per_sector = 1024; /* Page Erase (1 Kbyte) */
+            spi_flash_at45dbxx.geometry.sector_count = 128*64;   /* 64-Mbit / 8 / 1024 = 8192 */
+            spi_flash_at45dbxx.geometry.block_size = 1024*8;     /* Block Erase (8 Kbytes) */
+        }
+        else
+        {
+            FLASH_TRACE("Memory Capacity error!\r\n");
+            return -RT_ENOSYS;
+        }
+    }
+
+    /* register device */
+    spi_flash_at45dbxx.flash_device.type    = RT_Device_Class_Block;
+    spi_flash_at45dbxx.flash_device.init    = AT45DB_flash_init;
+    spi_flash_at45dbxx.flash_device.open    = AT45DB_flash_open;
+    spi_flash_at45dbxx.flash_device.close   = AT45DB_flash_close;
+    spi_flash_at45dbxx.flash_device.control = AT45DB_flash_control;
+
+    if(JEDEC_ID->density_code == DENSITY_CODE_642D)
+    {
+        spi_flash_at45dbxx.flash_device.read 	  = AT45DB_flash_read_page_1024;
+        spi_flash_at45dbxx.flash_device.write   = AT45DB_flash_write_page_1024;
+    }
+    else if(JEDEC_ID->density_code == DENSITY_CODE_161D
+            || JEDEC_ID->density_code == DENSITY_CODE_321D )
+    {
+        spi_flash_at45dbxx.flash_device.read 	  = AT45DB_flash_read_page_512;
+        spi_flash_at45dbxx.flash_device.write   = AT45DB_flash_write_page_512;
+    }
+    else
+    {
+        spi_flash_at45dbxx.flash_device.read 	  = AT45DB_flash_read_page_256;
+        spi_flash_at45dbxx.flash_device.write   = AT45DB_flash_write_page_256;
+    }
+
+    /* no private */
+    spi_flash_at45dbxx.flash_device.user_data = RT_NULL;
+
+    rt_device_register(&spi_flash_at45dbxx.flash_device, flash_device_name,
+                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
+
+    return RT_EOK;
+}
diff --git a/components/drivers/spi/spi_flash_at45dbxx.h b/components/drivers/spi/spi_flash_at45dbxx.h
new file mode 100644
index 0000000000..9b72cf0a0f
--- /dev/null
+++ b/components/drivers/spi/spi_flash_at45dbxx.h
@@ -0,0 +1,17 @@
+#ifndef SPI_FLASH_AT45DBXX_H_INCLUDED
+#define SPI_FLASH_AT45DBXX_H_INCLUDED
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+
+struct spi_flash_at45dbxx
+{
+    struct rt_device                flash_device;
+    struct rt_device_blk_geometry   geometry;
+    struct rt_spi_device *          rt_spi_device;
+};
+
+extern rt_err_t at45dbxx_init(const char * flash_device_name, const char * spi_device_name);
+
+
+#endif // SPI_FLASH_AT45DBXX_H_INCLUDED
diff --git a/components/drivers/spi/spi_flash_sst25vfxx.c b/components/drivers/spi/spi_flash_sst25vfxx.c
new file mode 100644
index 0000000000..f0e28b5584
--- /dev/null
+++ b/components/drivers/spi/spi_flash_sst25vfxx.c
@@ -0,0 +1,346 @@
+/*
+ * File      : rtdef.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-12-16     aozima       the first version
+ */
+
+#include <stdint.h>
+#include "spi_flash_sst25vfxx.h"
+
+#define FLASH_DEBUG
+
+#ifdef FLASH_DEBUG
+#define FLASH_TRACE         rt_kprintf
+#else
+#define FLASH_TRACE(...)
+#endif /* #ifdef FLASH_DEBUG */
+
+/* JEDEC Manufacturer¡¯s ID */
+#define MF_ID                       (0xBF)
+/* JEDEC Device ID : Memory Type */
+#define MT_ID                       (0x25)
+/* JEDEC Device ID: Memory Capacity */
+#define MC_ID_SST25VF020B            (0x8C) /* 2Mbit  */
+#define MC_ID_SST25VF040B            (0x8D) /* 4Mbit  */
+#define MC_ID_SST25VF080B            (0x8E) /* 8Mbit  */
+#define MC_ID_SST25VF016B            (0x41) /* 16Mbit */
+#define MC_ID_SST25VF032B            (0x4A) /* 32Mbit */
+#define MC_ID_SST25VF064C            (0x4B) /* 64Mbit */
+
+/* command list */
+#define CMD_RDSR                    (0x05)
+#define CMD_WRSR                    (0x01)
+#define CMD_EWSR                    (0x50)
+#define CMD_WRDI                    (0x04)
+#define CMD_WREN                    (0x06)
+#define CMD_READ                    (0x03)
+#define CMD_FAST_READ               (0x0B)
+#define CMD_BP                      (0x02)
+#define CMD_AAIP                    (0xAD)
+#define CMD_ERASE_4K                (0x20)
+#define CMD_ERASE_32K               (0x52)
+#define CMD_ERASE_64K               (0xD8)
+#define CMD_ERASE_full              (0xC7)
+#define CMD_JEDEC_ID                (0x9F)
+#define CMD_EBSY                    (0x70)
+#define CMD_DBSY                    (0x80)
+
+#define DUMMY                       (0xFF)
+
+static struct spi_flash_sst25vfxx  spi_flash_sst25vfxx;
+
+static uint8_t sst25vfxx_read_status(struct spi_flash_sst25vfxx * spi_flash)
+{
+    return rt_spi_sendrecv8(spi_flash->rt_spi_device, CMD_RDSR);
+}
+
+static void sst25vfxx_wait_busy(struct spi_flash_sst25vfxx * spi_flash)
+{
+    while( sst25vfxx_read_status(spi_flash) & (0x01));
+}
+
+/** \brief write N page on [page]
+ *
+ * \param page uint32_t unit : byte (4096 * N,1 page = 4096byte)
+ * \param buffer const uint8_t*
+ * \param size uint32_t unit : byte ( 4096*N )
+ * \return uint32_t
+ *
+ */
+static uint32_t sst25vfxx_page_write(struct spi_flash_sst25vfxx * spi_flash, uint32_t page, const uint8_t * buffer, uint32_t size)
+{
+    uint32_t index;
+    uint32_t need_wirte = size;
+    uint8_t send_buffer[6];
+
+    page &= ~0xFFF; // page size = 4096byte
+
+    send_buffer[0] = CMD_WREN;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_ERASE_4K;
+    send_buffer[1] = (page >> 16);
+    send_buffer[2] = (page >> 8);
+    send_buffer[3] = (page);
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 4);
+
+    sst25vfxx_wait_busy(spi_flash); // wait erase done.
+
+    send_buffer[0] = CMD_WREN;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_AAIP;
+    send_buffer[1] = (uint8_t)(page >> 16);
+    send_buffer[2] = (uint8_t)(page >> 8);
+    send_buffer[3] = (uint8_t)(page);
+    send_buffer[4] = *buffer++;
+    send_buffer[5] = *buffer++;
+    need_wirte -= 2;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 6);
+
+    sst25vfxx_wait_busy(spi_flash);
+
+    for(index=0; index < need_wirte/2; index++)
+    {
+        send_buffer[0] = CMD_AAIP;
+        send_buffer[1] = *buffer++;
+        send_buffer[2] = *buffer++;
+        rt_spi_send(spi_flash->rt_spi_device, send_buffer, 3);
+        sst25vfxx_wait_busy(spi_flash);
+    }
+
+    send_buffer[0] = CMD_WRDI;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
+
+    return size;
+}
+
+/* RT-Thread device interface */
+static rt_err_t sst25vfxx_flash_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t sst25vfxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    rt_err_t result;
+    uint8_t send_buffer[2];
+    struct spi_flash_sst25vfxx * spi_flash = (struct spi_flash_sst25vfxx *)dev;
+
+    /* lock spi flash */
+    result = rt_mutex_take(&(spi_flash->lock), RT_WAITING_FOREVER);
+    if(result != RT_EOK)
+    {
+        return result;
+    }
+
+    send_buffer[0] = CMD_DBSY;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_EWSR;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_WRSR;
+    send_buffer[1] = 0;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 2);
+
+    /* release lock */
+    rt_mutex_release(&(spi_flash->lock));
+
+    return RT_EOK;
+}
+
+static rt_err_t sst25vfxx_flash_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t sst25vfxx_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    struct spi_flash_sst25vfxx * spi_flash;
+
+    spi_flash = (struct spi_flash_sst25vfxx *)dev;
+
+    RT_ASSERT(dev != RT_NULL);
+
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    {
+        struct rt_device_blk_geometry *geometry;
+
+        geometry = (struct rt_device_blk_geometry *)args;
+        if (geometry == RT_NULL) return -RT_ERROR;
+
+        geometry->bytes_per_sector = spi_flash->geometry.bytes_per_sector;
+        geometry->sector_count = spi_flash->geometry.sector_count;
+        geometry->block_size = spi_flash->geometry.block_size;
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t sst25vfxx_flash_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    rt_err_t result;
+    uint8_t send_buffer[4];
+    struct spi_flash_sst25vfxx * spi_flash = (struct spi_flash_sst25vfxx *)dev;
+    uint32_t offset = pos * spi_flash->geometry.bytes_per_sector;
+
+    /* lock spi flash */
+    result = rt_mutex_take(&(spi_flash->lock), RT_WAITING_FOREVER);
+    if(result != RT_EOK)
+    {
+        return 0;
+    }
+
+    send_buffer[0] = CMD_WRDI;
+    rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_READ;
+    send_buffer[1] = (uint8_t)(offset>>16);
+    send_buffer[2] = (uint8_t)(offset>>8);
+    send_buffer[3] = (uint8_t)(offset);
+    rt_spi_send_then_recv(spi_flash->rt_spi_device, send_buffer, 4, buffer, size * spi_flash->geometry.bytes_per_sector);
+
+    /* release lock */
+    rt_mutex_release(&(spi_flash->lock));
+
+    return size;
+}
+
+static rt_size_t sst25vfxx_flash_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    uint32_t i;
+    rt_err_t result;
+    const uint8_t * write_buffer = buffer;
+    struct spi_flash_sst25vfxx * spi_flash = (struct spi_flash_sst25vfxx *)dev;
+
+    /* lock spi flash */
+    result = rt_mutex_take(&(spi_flash->lock), RT_WAITING_FOREVER);
+    if(result != RT_EOK)
+    {
+        return 0;
+    }
+
+    for(i=0; i<size; i++)
+    {
+        sst25vfxx_page_write(spi_flash,
+                             (pos + i) * spi_flash->geometry.bytes_per_sector,
+                             write_buffer,
+                             spi_flash->geometry.bytes_per_sector);
+        write_buffer += spi_flash->geometry.bytes_per_sector;
+    }
+
+    /* release lock */
+    rt_mutex_release(&(spi_flash->lock));
+
+    return size;
+}
+
+rt_err_t sst25vfxx_init(const char * flash_device_name, const char * spi_device_name)
+{
+    struct rt_spi_device * rt_spi_device;
+    struct spi_flash_sst25vfxx * spi_flash = &spi_flash_sst25vfxx;
+
+    rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
+    if(rt_spi_device == RT_NULL)
+    {
+        FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
+        return -RT_ENOSYS;
+    }
+    spi_flash->rt_spi_device = rt_spi_device;
+
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
+        cfg.max_hz = 50000000; /* 50M */
+        rt_spi_configure(spi_flash->rt_spi_device, &cfg);
+    }
+
+    /* init flash */
+    {
+        rt_uint8_t cmd;
+        rt_uint8_t id_recv[3];
+
+        cmd = CMD_WRDI;
+        rt_spi_send(spi_flash->rt_spi_device, &cmd, 1);
+
+        /* read flash id */
+        cmd = CMD_JEDEC_ID;
+        rt_spi_send_then_recv(spi_flash->rt_spi_device, &cmd, 1, id_recv, 3);
+
+        if(id_recv[0] != MF_ID || id_recv[1] != MT_ID)
+        {
+            FLASH_TRACE("Manufacturer¡¯s ID or Memory Type error!\r\n");
+            FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
+            return -RT_ENOSYS;
+        }
+
+        spi_flash->geometry.bytes_per_sector = 4096;
+        spi_flash->geometry.block_size = 4096; /* block erase: 4k */
+
+        if(id_recv[2] == MC_ID_SST25VF020B)
+        {
+            FLASH_TRACE("SST25VF020B detection\r\n");
+            spi_flash->geometry.sector_count = 64;
+        }
+        else if(id_recv[2] == MC_ID_SST25VF040B)
+        {
+            FLASH_TRACE("SST25VF040B detection\r\n");
+            spi_flash->geometry.sector_count = 128;
+        }
+        else if(id_recv[2] == MC_ID_SST25VF080B)
+        {
+            FLASH_TRACE("SST25VF080B detection\r\n");
+            spi_flash->geometry.sector_count = 256;
+        }
+        else if(id_recv[2] == MC_ID_SST25VF016B)
+        {
+            FLASH_TRACE("SST25VF016B detection\r\n");
+            spi_flash->geometry.sector_count = 512;
+        }
+        else if(id_recv[2] == MC_ID_SST25VF032B)
+        {
+            FLASH_TRACE("SST25VF032B detection\r\n");
+            spi_flash->geometry.sector_count = 1024;
+        }
+        else if(id_recv[2] == MC_ID_SST25VF064C)
+        {
+            FLASH_TRACE("SST25VF064C detection\r\n");
+            spi_flash->geometry.sector_count = 2048;
+        }
+        else
+        {
+            FLASH_TRACE("Memory Capacity error!\r\n");
+            return -RT_ENOSYS;
+        }
+    }
+
+    /* initialize mutex lock */
+    rt_mutex_init(&spi_flash->lock, flash_device_name, RT_IPC_FLAG_PRIO);
+
+    /* register device */
+    spi_flash->flash_device.type    = RT_Device_Class_Block;
+    spi_flash->flash_device.init    = sst25vfxx_flash_init;
+    spi_flash->flash_device.open    = sst25vfxx_flash_open;
+    spi_flash->flash_device.close   = sst25vfxx_flash_close;
+    spi_flash->flash_device.read    = sst25vfxx_flash_read;
+    spi_flash->flash_device.write   = sst25vfxx_flash_write;
+    spi_flash->flash_device.control = sst25vfxx_flash_control;
+    /* no private */
+    spi_flash->flash_device.user_data = RT_NULL;
+
+    rt_device_register(&spi_flash->flash_device, flash_device_name,
+                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
+
+    return RT_EOK;
+}
diff --git a/components/drivers/spi/spi_flash_sst25vfxx.h b/components/drivers/spi/spi_flash_sst25vfxx.h
new file mode 100644
index 0000000000..b4575c2b68
--- /dev/null
+++ b/components/drivers/spi/spi_flash_sst25vfxx.h
@@ -0,0 +1,32 @@
+/*
+ * File      : rtdef.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-12-16     aozima      the first version
+ */
+
+#ifndef SPI_FLASH_SST25VFXX_H_INCLUDED
+#define SPI_FLASH_SST25VFXX_H_INCLUDED
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+
+struct spi_flash_sst25vfxx
+{
+    struct rt_device                flash_device;
+    struct rt_device_blk_geometry   geometry;
+    struct rt_spi_device *          rt_spi_device;
+    struct rt_mutex                 lock;
+};
+
+extern rt_err_t sst25vfxx_init(const char * flash_device_name, const char * spi_device_name);
+
+
+#endif // SPI_FLASH_SST25VFXX_H_INCLUDED
diff --git a/components/drivers/spi/spi_flash_w25qxx.c b/components/drivers/spi/spi_flash_w25qxx.c
new file mode 100644
index 0000000000..bdcdbd83c1
--- /dev/null
+++ b/components/drivers/spi/spi_flash_w25qxx.c
@@ -0,0 +1,371 @@
+/*
+ * File      : spi_flash_w25qxx.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-12-16     aozima       the first version
+ * 2012-05-06     aozima       can page write.
+ * 2012-08-23     aozima       add flash lock.
+ * 2012-08-24     aozima       fixed write status register BUG.
+ */
+
+#include <stdint.h>
+#include "spi_flash_w25qxx.h"
+
+#define FLASH_DEBUG
+
+#ifdef FLASH_DEBUG
+#define FLASH_TRACE         rt_kprintf
+#else
+#define FLASH_TRACE(...)
+#endif /* #ifdef FLASH_DEBUG */
+
+#define PAGE_SIZE           4096
+
+/* JEDEC Manufacturer¡¯s ID */
+#define MF_ID           (0xEF)
+/* JEDEC Device ID: Memory type and Capacity */
+#define MTC_W25Q16_BV_CL_CV   (0x4015) /* W25Q16BV W25Q16CL W25Q16CV  */
+#define MTC_W25Q16_DW         (0x6015) /* W25Q16DW  */
+#define MTC_W25Q32_BV         (0x4016) /* W25Q32BV */
+#define MTC_W25Q32_DW         (0x6016) /* W25Q32DW */
+#define MTC_W25Q64_BV_CV      (0x4017) /* W25Q64BV W25Q64CV */
+#define MTC_W25Q64_DW         (0x4017) /* W25Q64DW */
+#define MTC_W25Q128_BV        (0x4018) /* W25Q128BV */
+#define MTC_W25Q256_FV        (TBD)    /* W25Q256FV */
+
+/* command list */
+#define CMD_WRSR                    (0x01)  /* Write Status Register */
+#define CMD_PP                      (0x02)  /* Page Program */
+#define CMD_READ                    (0x03)  /* Read Data */
+#define CMD_WRDI                    (0x04)  /* Write Disable */
+#define CMD_RDSR1                   (0x05)  /* Read Status Register-1 */
+#define CMD_WREN                    (0x06)  /* Write Enable */
+#define CMD_FAST_READ               (0x0B)  /* Fast Read */
+#define CMD_ERASE_4K                (0x20)  /* Sector Erase:4K */
+#define CMD_RDSR2                   (0x35)  /* Read Status Register-2 */
+#define CMD_ERASE_32K               (0x52)  /* 32KB Block Erase */
+#define CMD_JEDEC_ID                (0x9F)  /* Read JEDEC ID */
+#define CMD_ERASE_full              (0xC7)  /* Chip Erase */
+#define CMD_ERASE_64K               (0xD8)  /* 64KB Block Erase */
+
+#define DUMMY                       (0xFF)
+
+static struct spi_flash_device  spi_flash_device;
+
+static void flash_lock(struct spi_flash_device * flash_device)
+{
+    rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
+}
+
+static void flash_unlock(struct spi_flash_device * flash_device)
+{
+    rt_mutex_release(&flash_device->lock);
+}
+
+static uint8_t w25qxx_read_status(void)
+{
+    return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
+}
+
+static void w25qxx_wait_busy(void)
+{
+    while( w25qxx_read_status() & (0x01));
+}
+
+/** \brief read [size] byte from [offset] to [buffer]
+ *
+ * \param offset uint32_t unit : byte
+ * \param buffer uint8_t*
+ * \param size uint32_t   unit : byte
+ * \return uint32_t byte for read
+ *
+ */
+static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
+{
+    uint8_t send_buffer[4];
+
+    send_buffer[0] = CMD_WRDI;
+    rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_READ;
+    send_buffer[1] = (uint8_t)(offset>>16);
+    send_buffer[2] = (uint8_t)(offset>>8);
+    send_buffer[3] = (uint8_t)(offset);
+
+    rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
+                          send_buffer, 4,
+                          buffer, size);
+
+    return size;
+}
+
+/** \brief write N page on [page]
+ *
+ * \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
+ * \param buffer const uint8_t*
+ * \return uint32_t
+ *
+ */
+uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
+{
+    uint32_t index;
+    uint8_t send_buffer[4];
+
+    RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
+
+    send_buffer[0] = CMD_WREN;
+    rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_ERASE_4K;
+    send_buffer[1] = (page_addr >> 16);
+    send_buffer[2] = (page_addr >> 8);
+    send_buffer[3] = (page_addr);
+    rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
+
+    w25qxx_wait_busy(); // wait erase done.
+
+    for(index=0; index < (PAGE_SIZE / 256); index++)
+    {
+        send_buffer[0] = CMD_WREN;
+        rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
+
+        send_buffer[0] = CMD_PP;
+        send_buffer[1] = (uint8_t)(page_addr >> 16);
+        send_buffer[2] = (uint8_t)(page_addr >> 8);
+        send_buffer[3] = (uint8_t)(page_addr);
+
+        rt_spi_send_then_send(spi_flash_device.rt_spi_device,
+                              send_buffer,
+                              4,
+                              buffer,
+                              256);
+
+        buffer += 256;
+        page_addr += 256;
+        w25qxx_wait_busy();
+    }
+
+    send_buffer[0] = CMD_WRDI;
+    rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
+
+    return PAGE_SIZE;
+}
+
+/* RT-Thread device interface */
+static rt_err_t w25qxx_flash_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    uint8_t send_buffer[3];
+
+    flash_lock((struct spi_flash_device *)dev);
+
+    send_buffer[0] = CMD_WREN;
+    rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
+
+    send_buffer[0] = CMD_WRSR;
+    send_buffer[1] = 0;
+    send_buffer[2] = 0;
+    rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
+
+    w25qxx_wait_busy();
+
+    flash_unlock((struct spi_flash_device *)dev);
+
+    return RT_EOK;
+}
+
+static rt_err_t w25qxx_flash_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t w25qxx_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    {
+        struct rt_device_blk_geometry *geometry;
+
+        geometry = (struct rt_device_blk_geometry *)args;
+        if (geometry == RT_NULL) return -RT_ERROR;
+
+        geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
+        geometry->sector_count = spi_flash_device.geometry.sector_count;
+        geometry->block_size = spi_flash_device.geometry.block_size;
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t w25qxx_flash_read(rt_device_t dev,
+                                   rt_off_t pos,
+                                   void* buffer,
+                                   rt_size_t size)
+{
+    flash_lock((struct spi_flash_device *)dev);
+
+    w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
+                buffer,
+                size*spi_flash_device.geometry.bytes_per_sector);
+
+    flash_unlock((struct spi_flash_device *)dev);
+
+    return size;
+}
+
+static rt_size_t w25qxx_flash_write(rt_device_t dev,
+                                    rt_off_t pos,
+                                    const void* buffer,
+                                    rt_size_t size)
+{
+    rt_size_t i = 0;
+    rt_size_t block = size;
+    const uint8_t * ptr = buffer;
+
+    flash_lock((struct spi_flash_device *)dev);
+
+    while(block--)
+    {
+        w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
+                          ptr);
+        ptr += PAGE_SIZE;
+        i++;
+    }
+
+    flash_unlock((struct spi_flash_device *)dev);
+
+    return size;
+}
+
+rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_name)
+{
+    struct rt_spi_device * rt_spi_device;
+
+    /* initialize mutex */
+    if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
+    {
+        rt_kprintf("init sd lock mutex failed\n");
+        return -RT_ENOSYS;
+    }
+
+    rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
+    if(rt_spi_device == RT_NULL)
+    {
+        FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
+        return -RT_ENOSYS;
+    }
+    spi_flash_device.rt_spi_device = rt_spi_device;
+
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
+        cfg.max_hz = 50 * 1000 * 1000; /* 50M */
+        rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
+    }
+
+    /* init flash */
+    {
+        rt_uint8_t cmd;
+        rt_uint8_t id_recv[3];
+        uint16_t memory_type_capacity;
+
+        flash_lock(&spi_flash_device);
+
+        cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
+        rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
+
+        cmd = CMD_WRDI;
+        rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
+
+        /* read flash id */
+        cmd = CMD_JEDEC_ID;
+        rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
+
+        flash_unlock(&spi_flash_device);
+
+        if(id_recv[0] != MF_ID)
+        {
+            FLASH_TRACE("Manufacturers ID error!\r\n");
+            FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
+            return -RT_ENOSYS;
+        }
+
+        spi_flash_device.geometry.bytes_per_sector = 4096;
+        spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
+
+        /* get memory type and capacity */
+        memory_type_capacity = id_recv[1];
+        memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
+
+        if(memory_type_capacity == MTC_W25Q128_BV)
+        {
+            FLASH_TRACE("W25Q128BV detection\r\n");
+            spi_flash_device.geometry.sector_count = 4096;
+        }
+        else if(memory_type_capacity == MTC_W25Q64_BV_CV)
+        {
+            FLASH_TRACE("W25Q64BV or W25Q64CV detection\r\n");
+            spi_flash_device.geometry.sector_count = 2048;
+        }
+        else if(memory_type_capacity == MTC_W25Q64_DW)
+        {
+            FLASH_TRACE("W25Q64DW detection\r\n");
+            spi_flash_device.geometry.sector_count = 2048;
+        }
+        else if(memory_type_capacity == MTC_W25Q32_BV)
+        {
+            FLASH_TRACE("W25Q32BV detection\r\n");
+            spi_flash_device.geometry.sector_count = 1024;
+        }
+        else if(memory_type_capacity == MTC_W25Q32_DW)
+        {
+            FLASH_TRACE("W25Q32DW detection\r\n");
+            spi_flash_device.geometry.sector_count = 1024;
+        }
+        else if(memory_type_capacity == MTC_W25Q16_BV_CL_CV)
+        {
+            FLASH_TRACE("W25Q16BV or W25Q16CL or W25Q16CV detection\r\n");
+            spi_flash_device.geometry.sector_count = 512;
+        }
+        else if(memory_type_capacity == MTC_W25Q16_DW)
+        {
+            FLASH_TRACE("W25Q16DW detection\r\n");
+            spi_flash_device.geometry.sector_count = 512;
+        }
+        else
+        {
+            FLASH_TRACE("Memory Capacity error!\r\n");
+            return -RT_ENOSYS;
+        }
+    }
+
+    /* register device */
+    spi_flash_device.flash_device.type    = RT_Device_Class_Block;
+    spi_flash_device.flash_device.init    = w25qxx_flash_init;
+    spi_flash_device.flash_device.open    = w25qxx_flash_open;
+    spi_flash_device.flash_device.close   = w25qxx_flash_close;
+    spi_flash_device.flash_device.read    = w25qxx_flash_read;
+    spi_flash_device.flash_device.write   = w25qxx_flash_write;
+    spi_flash_device.flash_device.control = w25qxx_flash_control;
+    /* no private */
+    spi_flash_device.flash_device.user_data = RT_NULL;
+
+    rt_device_register(&spi_flash_device.flash_device, flash_device_name,
+                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
+
+    return RT_EOK;
+}
diff --git a/components/drivers/spi/spi_flash_w25qxx.h b/components/drivers/spi/spi_flash_w25qxx.h
new file mode 100644
index 0000000000..ebab35da33
--- /dev/null
+++ b/components/drivers/spi/spi_flash_w25qxx.h
@@ -0,0 +1,34 @@
+/*
+ * File      : spi_flash_w25qxx.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-12-16     aozima      the first version
+ * 2012-08-23     aozima       add flash lock.
+ */
+
+#ifndef SPI_FLASH_W25QXX_H_INCLUDED
+#define SPI_FLASH_W25QXX_H_INCLUDED
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+
+struct spi_flash_device
+{
+    struct rt_device                flash_device;
+    struct rt_device_blk_geometry   geometry;
+    struct rt_spi_device *          rt_spi_device;
+    struct rt_mutex                 lock;
+};
+
+extern rt_err_t w25qxx_init(const char * flash_device_name,
+                            const char * spi_device_name);
+
+
+#endif // SPI_FLASH_W25QXX_H_INCLUDED
diff --git a/components/drivers/spi/spi_wifi_rw009.c b/components/drivers/spi/spi_wifi_rw009.c
new file mode 100644
index 0000000000..f45d493717
--- /dev/null
+++ b/components/drivers/spi/spi_wifi_rw009.c
@@ -0,0 +1,590 @@
+/*
+ * File      : spi_wifi_rw009.c
+ * This file is part of RT-Thread RTOS
+ * Copyright by Shanghai Real-Thread Electronic Technology Co.,Ltd
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-31     aozima       the first version
+ */
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+
+#include <netif/ethernetif.h>
+#include <netif/etharp.h>
+#include <lwip/icmp.h>
+#include "lwipopts.h"
+
+#include "spi_wifi_rw009.h"
+
+#define SSID_NAME      "AP_SSID"
+#define SSID_PASSWORD  "AP_passwd"
+
+//#define WIFI_DEBUG_ON
+// #define ETH_RX_DUMP
+// #define ETH_TX_DUMP
+
+#ifdef WIFI_DEBUG_ON
+#define WIFI_DEBUG         rt_kprintf("[WIFI] ");rt_kprintf
+#else
+#define WIFI_DEBUG(...)
+#endif /* #ifdef WIFI_DEBUG_ON */
+
+#define MAX_BUFFER_SIZE     (sizeof(struct response) + MAX_DATA_LEN)
+#define MAX_ADDR_LEN 6
+struct spi_wifi_eth
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+
+    struct rt_spi_device *rt_spi_device;
+
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* hw address   */
+    rt_uint8_t  active;
+
+    struct rt_mempool spi_tx_mp;
+    struct rt_mempool spi_rx_mp;
+
+    struct rt_mailbox spi_tx_mb;
+    struct rt_mailbox eth_rx_mb;
+
+    int spi_tx_mb_pool[SPI_TX_POOL_SIZE];
+    int eth_rx_mb_pool[SPI_TX_POOL_SIZE];
+
+    int spi_wifi_cmd_mb_pool[3];
+    struct rt_mailbox spi_wifi_cmd_mb;
+
+    ALIGN(4)
+    rt_uint8_t spi_tx_mempool[(sizeof(struct spi_data_packet) + 4) * SPI_TX_POOL_SIZE];
+    ALIGN(4)
+    rt_uint8_t spi_rx_mempool[(sizeof(struct spi_data_packet) + 4) * SPI_TX_POOL_SIZE];
+
+    ALIGN(4)
+    uint8_t spi_hw_rx_buffer[MAX_BUFFER_SIZE];
+};
+static struct spi_wifi_eth spi_wifi_device;
+static struct rt_event spi_wifi_data_event;
+
+static void resp_handler(struct spi_wifi_eth *wifi_device, struct spi_wifi_resp *resp)
+{
+    struct spi_wifi_resp *resp_return;
+
+    switch (resp->cmd)
+    {
+    case SPI_WIFI_CMD_INIT:
+        WIFI_DEBUG("resp_handler SPI_WIFI_CMD_INIT\n");
+        resp_return = (struct spi_wifi_resp *)rt_malloc(sizeof(struct spi_wifi_resp)); //TODO:
+        memcpy(resp_return, resp, 10);
+        rt_mb_send(&wifi_device->spi_wifi_cmd_mb, (rt_uint32_t)resp_return);
+        break;
+
+    case SPI_WIFI_CMD_SCAN:
+        WIFI_DEBUG("resp_handler SPI_WIFI_CMD_SCAN\n");
+        break;
+
+    case SPI_WIFI_CMD_JOIN:
+        WIFI_DEBUG("resp_handler SPI_WIFI_CMD_JOIN\n");
+        wifi_device->active = 1;
+        eth_device_linkchange(&wifi_device->parent, RT_TRUE);
+        break;
+
+    default:
+        WIFI_DEBUG("resp_handler %d\n", resp->cmd);
+        break;
+    }
+
+}
+
+static rt_err_t spi_wifi_transfer(struct spi_wifi_eth *dev)
+{
+    struct pbuf *p = RT_NULL;
+    struct cmd_request cmd;
+    struct response resp;
+
+    rt_err_t result;
+    const struct spi_data_packet *data_packet = RT_NULL;
+
+    struct spi_wifi_eth *wifi_device = (struct spi_wifi_eth *)dev;
+    struct rt_spi_device *rt_spi_device = wifi_device->rt_spi_device;
+
+    spi_wifi_int_cmd(0);
+    while (spi_wifi_is_busy());
+    WIFI_DEBUG("sequence start!\n");
+
+    memset(&cmd, 0, sizeof(struct cmd_request));
+    cmd.magic1 = CMD_MAGIC1;
+    cmd.magic2 = CMD_MAGIC2;
+
+    cmd.flag |= CMD_FLAG_MRDY;
+
+    result = rt_mb_recv(&wifi_device->spi_tx_mb,
+                        (rt_uint32_t *)&data_packet,
+                        0);
+    if ((result == RT_EOK) && (data_packet != RT_NULL) && (data_packet->data_len > 0))
+    {
+        cmd.M2S_len = data_packet->data_len + member_offset(struct spi_data_packet, buffer);
+        //WIFI_DEBUG("cmd.M2S_len = %d\n", cmd.M2S_len);
+    }
+
+    rt_spi_send(rt_spi_device, &cmd, sizeof(cmd));
+    while (spi_wifi_is_busy());
+
+    {
+        struct rt_spi_message message;
+        uint32_t max_data_len = 0;
+
+        /* setup message */
+        message.send_buf = RT_NULL;
+        message.recv_buf = &resp;
+        message.length = sizeof(resp);
+        message.cs_take = 1;
+        message.cs_release = 0;
+
+        rt_spi_take_bus(rt_spi_device);
+
+        /* transfer message */
+        rt_spi_device->bus->ops->xfer(rt_spi_device, &message);
+
+        if ((resp.magic1 != RESP_MAGIC1) || (resp.magic2 != RESP_MAGIC2))
+        {
+            WIFI_DEBUG("bad resp magic, abort!\n");
+            goto _bad_resp_magic;
+        }
+
+        if (resp.flag & RESP_FLAG_SRDY)
+        {
+            WIFI_DEBUG("RESP_FLAG_SRDY\n");
+            max_data_len = cmd.M2S_len;
+        }
+
+        if (resp.S2M_len)
+        {
+            WIFI_DEBUG("resp.S2M_len: %d\n", resp.S2M_len);
+            if (resp.S2M_len > sizeof(struct spi_data_packet))
+            {
+                WIFI_DEBUG("resp.S2M_len > sizeof(struct spi_data_packet), drop!\n");
+                resp.S2M_len = 0;//drop
+            }
+
+            if (resp.S2M_len > max_data_len)
+                max_data_len = resp.S2M_len;
+        }
+
+        if (max_data_len == 0)
+        {
+            WIFI_DEBUG("no rx or tx data!\n");
+        }
+
+        //WIFI_DEBUG("max_data_len = %d\n", max_data_len);
+
+_bad_resp_magic:
+        /* setup message */
+        message.send_buf = data_packet;//&tx_buffer;
+        message.recv_buf = wifi_device->spi_hw_rx_buffer;//&rx_buffer;
+        message.length = max_data_len;
+        message.cs_take = 0;
+        message.cs_release = 1;
+
+        /* transfer message */
+        rt_spi_device->bus->ops->xfer(rt_spi_device, &message);
+
+        rt_spi_release_bus(rt_spi_device);
+
+        if (cmd.M2S_len && (resp.flag & RESP_FLAG_SRDY))
+        {
+            rt_mp_free((void *)data_packet);
+        }
+
+        if ((resp.S2M_len) && (resp.S2M_len <= MAX_DATA_LEN))
+        {
+            data_packet = (struct spi_data_packet *)wifi_device->spi_hw_rx_buffer;
+            if (data_packet->data_type == data_type_eth_data)
+            {
+
+                if (wifi_device->active)
+                {
+                    p = pbuf_alloc(PBUF_LINK, data_packet->data_len, PBUF_RAM);
+                    pbuf_take(p, (rt_uint8_t *)data_packet->buffer, data_packet->data_len);
+
+                    rt_mb_send(&wifi_device->eth_rx_mb, (rt_uint32_t)p);
+                    eth_device_ready((struct eth_device *)dev);
+                }
+                else
+                {
+                    WIFI_DEBUG("!active, RX drop.\n");
+                }
+            }
+            else if (data_packet->data_type == data_type_resp)
+            {
+                WIFI_DEBUG("data_type_resp\n");
+                resp_handler(dev, (struct spi_wifi_resp *)data_packet->buffer);
+            }
+            else
+            {
+                WIFI_DEBUG("data_type: %d, %dbyte\n",
+                           data_packet->data_type,
+                           data_packet->data_len);
+            }
+        }
+    }
+    spi_wifi_int_cmd(1);
+
+    WIFI_DEBUG("sequence finish!\n\n");
+
+    if ((cmd.M2S_len == 0) && (resp.S2M_len == 0))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+#if defined(ETH_RX_DUMP) ||  defined(ETH_TX_DUMP)
+static void packet_dump(const char *msg, const struct pbuf *p)
+{
+    rt_uint32_t i;
+    rt_uint8_t *ptr = p->payload;
+
+    rt_kprintf("%s %d byte\n", msg, p->tot_len);
+
+    for (i = 0; i < p->tot_len; i++)
+    {
+        if ((i % 8) == 0)
+        {
+            rt_kprintf("  ");
+        }
+        if ((i % 16) == 0)
+        {
+            rt_kprintf("\r\n");
+        }
+        rt_kprintf("%02x ", *ptr);
+        ptr++;
+    }
+    rt_kprintf("\n\n");
+}
+#endif /* dump */
+
+/* initialize the interface */
+static rt_err_t spi_wifi_eth_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t spi_wifi_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t spi_wifi_eth_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t spi_wifi_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t spi_wifi_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+
+static rt_err_t spi_wifi_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    struct spi_wifi_eth *wifi_device = (struct spi_wifi_eth *)dev;
+    struct spi_data_packet *data_packet;
+    struct spi_wifi_cmd *wifi_cmd;
+    struct spi_wifi_resp *resp;
+
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        memcpy(args, wifi_device->dev_addr, 6);
+        break;
+
+    case SPI_WIFI_CMD_INIT:
+        /* get mac address */
+        if (args)
+        {
+            rt_err_t result;
+
+            data_packet = (struct spi_data_packet *)rt_mp_alloc(&wifi_device->spi_tx_mp, RT_WAITING_FOREVER);
+            // TODO: check result.
+
+            wifi_cmd = (struct spi_wifi_cmd *)data_packet->buffer;
+            wifi_cmd->cmd = SPI_WIFI_CMD_INIT;
+
+            data_packet->data_type = data_type_cmd;
+            data_packet->data_len = member_offset(struct spi_wifi_cmd, buffer) + 0;
+
+            rt_mb_send(&wifi_device->spi_tx_mb, (rt_uint32_t)data_packet);
+            rt_event_send(&spi_wifi_data_event, 1);
+
+            result = rt_mb_recv(&wifi_device->spi_wifi_cmd_mb,
+                                (rt_uint32_t *)&resp,
+                                RT_WAITING_FOREVER);
+
+            if ((result == RT_EOK) && (resp != RT_NULL))
+            {
+                WIFI_DEBUG("resp cmd: %d\n", resp->cmd);
+
+                rt_memcpy(args, resp->buffer, 6);
+            }
+        }
+        else return -RT_ERROR;
+        break;
+
+
+    case SPI_WIFI_CMD_SCAN:
+
+    case SPI_WIFI_CMD_JOIN:
+        if (args)
+        {
+            struct cmd_join *cmd_join;
+
+            data_packet = (struct spi_data_packet *)rt_mp_alloc(&wifi_device->spi_tx_mp, RT_WAITING_FOREVER);
+
+            wifi_cmd = (struct spi_wifi_cmd *)data_packet->buffer;
+            wifi_cmd->cmd = SPI_WIFI_CMD_JOIN;
+            cmd_join = (struct cmd_join *)wifi_cmd->buffer;
+
+#define WPA_SECURITY    0x00200000
+#define WPA2_SECURITY   0x00400000
+
+#define TKIP_ENABLED    0x0002
+#define AES_ENABLED     0x0004
+
+
+            strncpy(cmd_join->ssid, SSID_NAME, SSID_NAME_LENGTH_MAX);
+            strncpy(cmd_join->passwd, SSID_PASSWORD, PASSWORD_LENGTH_MAX);
+            cmd_join->security = WPA2_SECURITY | TKIP_ENABLED | AES_ENABLED;
+            // cmd_join->security = WPA_SECURITY | TKIP_ENABLED;
+            data_packet->data_type = data_type_cmd;
+            data_packet->data_len = sizeof(struct cmd_join) + member_offset(struct spi_wifi_cmd, buffer);
+
+            rt_mb_send(&wifi_device->spi_tx_mb, (rt_uint32_t)data_packet);
+            rt_event_send(&spi_wifi_data_event, 1);
+        }
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/* transmit packet. */
+rt_err_t spi_wifi_eth_tx(rt_device_t dev, struct pbuf *p)
+{
+    rt_err_t result = RT_EOK;
+    struct spi_data_packet *data_packet;
+    struct spi_wifi_eth *wifi_device = (struct spi_wifi_eth *)dev;
+
+    if (!wifi_device->active)
+    {
+        WIFI_DEBUG("!active, TX drop!\n");
+        return RT_EOK;
+    }
+
+    /* get free tx buffer */
+    data_packet = (struct spi_data_packet *)rt_mp_alloc(&wifi_device->spi_tx_mp, RT_WAITING_FOREVER);
+    if (data_packet != RT_NULL)
+    {
+        data_packet->data_type = data_type_eth_data;
+        data_packet->data_len = p->tot_len;
+
+        pbuf_copy_partial(p, data_packet->buffer, data_packet->data_len, 0);
+
+        rt_mb_send(&wifi_device->spi_tx_mb, (rt_uint32_t)data_packet);
+        eth_device_ready((struct eth_device *)dev);
+    }
+    else
+        return -RT_ERROR;
+
+#ifdef ETH_TX_DUMP
+    packet_dump("TX dump", p);
+#endif /* ETH_TX_DUMP */
+
+    /* Return SUCCESS */
+    return result;
+}
+
+/* reception packet. */
+struct pbuf *spi_wifi_eth_rx(rt_device_t dev)
+{
+    struct pbuf *p = RT_NULL;
+    struct spi_wifi_eth *wifi_device = (struct spi_wifi_eth *)dev;
+
+    if (rt_mb_recv(&wifi_device->eth_rx_mb, (rt_uint32_t *)&p, 0) != RT_EOK)
+    {
+        return RT_NULL;
+    }
+
+
+
+    return p;
+}
+
+static void spi_wifi_data_thread_entry(void *parameter)
+{
+    rt_uint32_t e;
+    rt_err_t result;
+
+    while (1)
+    {
+        /* receive first event */
+        if (rt_event_recv(&spi_wifi_data_event,
+                          1,
+                          RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR,
+                          RT_WAITING_FOREVER,
+                          &e) != RT_EOK)
+        {
+            continue;
+        }
+
+        result = spi_wifi_transfer(&spi_wifi_device);
+
+        if (result == RT_EOK)
+        {
+            rt_event_send(&spi_wifi_data_event, 1);
+        }
+    }
+}
+
+rt_err_t rt_hw_wifi_init(const char *spi_device_name)
+{
+    memset(&spi_wifi_device, 0, sizeof(struct spi_wifi_eth));
+
+    spi_wifi_device.rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
+
+    if (spi_wifi_device.rt_spi_device == RT_NULL)
+    {
+        WIFI_DEBUG("spi device %s not found!\r\n", spi_device_name);
+        return -RT_ENOSYS;
+    }
+
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
+        cfg.max_hz = 1000000; /* 50M */
+        rt_spi_configure(spi_wifi_device.rt_spi_device, &cfg);
+    }
+
+    spi_wifi_device.parent.parent.init       = spi_wifi_eth_init;
+    spi_wifi_device.parent.parent.open       = spi_wifi_eth_open;
+    spi_wifi_device.parent.parent.close      = spi_wifi_eth_close;
+    spi_wifi_device.parent.parent.read       = spi_wifi_eth_read;
+    spi_wifi_device.parent.parent.write      = spi_wifi_eth_write;
+    spi_wifi_device.parent.parent.control    = spi_wifi_eth_control;
+    spi_wifi_device.parent.parent.user_data  = RT_NULL;
+
+    spi_wifi_device.parent.eth_rx     = spi_wifi_eth_rx;
+    spi_wifi_device.parent.eth_tx     = spi_wifi_eth_tx;
+
+    rt_mp_init(&spi_wifi_device.spi_tx_mp,
+               "spi_tx",
+               &spi_wifi_device.spi_tx_mempool[0],
+               sizeof(spi_wifi_device.spi_tx_mempool),
+               sizeof(struct spi_data_packet));
+
+    rt_mp_init(&spi_wifi_device.spi_rx_mp,
+               "spi_rx",
+               &spi_wifi_device.spi_rx_mempool[0],
+               sizeof(spi_wifi_device.spi_rx_mempool),
+               sizeof(struct spi_data_packet));
+
+    rt_mb_init(&spi_wifi_device.spi_tx_mb,
+               "spi_tx",
+               &spi_wifi_device.spi_tx_mb_pool[0],
+               SPI_TX_POOL_SIZE,
+               RT_IPC_FLAG_PRIO);
+
+    rt_mb_init(&spi_wifi_device.eth_rx_mb,
+               "eth_rx",
+               &spi_wifi_device.eth_rx_mb_pool[0],
+               SPI_TX_POOL_SIZE,
+               RT_IPC_FLAG_PRIO);
+
+    rt_mb_init(&spi_wifi_device.spi_wifi_cmd_mb,
+               "wifi_cmd",
+               &spi_wifi_device.spi_wifi_cmd_mb_pool[0],
+               sizeof(spi_wifi_device.spi_wifi_cmd_mb_pool) / 4,
+               RT_IPC_FLAG_PRIO);
+    rt_event_init(&spi_wifi_data_event, "wifi", RT_IPC_FLAG_FIFO);
+
+    spi_wifi_hw_init();
+
+    {
+        rt_thread_t tid;
+
+
+        tid = rt_thread_create("wifi",
+                               spi_wifi_data_thread_entry,
+                               RT_NULL,
+                               2048,
+                               RT_THREAD_PRIORITY_MAX - 2,
+                               20);
+
+        if (tid != RT_NULL)
+            rt_thread_startup(tid);
+    }
+
+    /* init: get mac address */
+    {
+        WIFI_DEBUG("wifi_control SPI_WIFI_CMD_INIT\n");
+        spi_wifi_eth_control((rt_device_t)&spi_wifi_device,
+                             SPI_WIFI_CMD_INIT,
+                             (void *)&spi_wifi_device.dev_addr[0]);
+
+    }
+    /* register eth device */
+    eth_device_init(&(spi_wifi_device.parent), "w0");
+    eth_device_linkchange(&spi_wifi_device.parent, RT_FALSE);
+
+    {
+        WIFI_DEBUG("wifi_control SPI_WIFI_CMD_JOIN\n");
+        spi_wifi_eth_control((rt_device_t)&spi_wifi_device,
+                             SPI_WIFI_CMD_JOIN,
+                             (void *)&spi_wifi_device.dev_addr[0]);
+
+        WIFI_DEBUG("wifi_control exit\n");
+    }
+
+    return RT_EOK;
+}
+
+void spi_wifi_isr(int vector)
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+    WIFI_DEBUG("spi_wifi_isr\n");
+    rt_event_send(&spi_wifi_data_event, 1);
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
diff --git a/components/drivers/spi/spi_wifi_rw009.h b/components/drivers/spi/spi_wifi_rw009.h
new file mode 100644
index 0000000000..b609e7cb13
--- /dev/null
+++ b/components/drivers/spi/spi_wifi_rw009.h
@@ -0,0 +1,123 @@
+/*
+ * File      : spi_wifi_rw009.h
+ * This file is part of RT-Thread RTOS
+ * Copyright by Shanghai Real-Thread Electronic Technology Co.,Ltd
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-31     aozima       the first version
+ */
+
+#ifndef SPI_WIFI_H_INCLUDED
+#define SPI_WIFI_H_INCLUDED
+
+#include <stdint.h>
+
+// little-endian
+struct cmd_request
+{
+    uint32_t flag;
+    uint32_t M2S_len; // master to slave data len.
+    uint32_t magic1;
+    uint32_t magic2;
+};
+
+#define CMD_MAGIC1          (0x67452301)
+#define CMD_MAGIC2          (0xEFCDAB89)
+
+#define CMD_FLAG_MRDY       (0x01)
+
+// little-endian
+struct response
+{
+    uint32_t flag;
+    uint32_t S2M_len; // slave to master data len.
+    uint32_t magic1;
+    uint32_t magic2;
+};
+
+#define RESP_FLAG_SRDY      (0x01)
+#define RESP_MAGIC1         (0x98BADCFE)
+#define RESP_MAGIC2         (0x10325476)
+
+/* spi slave configure. */
+#define MAX_DATA_LEN        1520
+#define SPI_TX_POOL_SIZE    2
+
+// align check
+#if (MAX_DATA_LEN & 0x03) != 0
+#error MAX_DATA_LEN must ALIGN to 4byte!
+#endif
+
+typedef enum
+{
+    data_type_eth_data = 0,
+    data_type_cmd,
+    data_type_resp,
+}
+app_data_type_typedef;
+
+struct spi_data_packet
+{
+    uint32_t data_len;
+    uint32_t data_type;
+    char buffer[MAX_DATA_LEN];
+};
+
+struct spi_wifi_cmd
+{
+    uint32_t cmd;
+    char buffer[128];
+};
+
+struct spi_wifi_resp
+{
+    uint32_t cmd;
+    char buffer[128];
+};
+
+#define SPI_WIFI_CMD_INIT         128  //wait
+#define SPI_WIFI_CMD_SCAN         129  //no wait
+#define SPI_WIFI_CMD_JOIN         130  //no wait
+
+/* porting */
+extern void spi_wifi_hw_init(void);
+extern void spi_wifi_int_cmd(rt_bool_t cmd);
+extern rt_bool_t spi_wifi_is_busy(void);
+
+/* tools */
+#define node_entry(node, type, member) \
+    ((type *)((char *)(node) - (unsigned long)(&((type *)0)->member)))
+#define member_offset(type, member) \
+    ((unsigned long)(&((type *)0)->member))
+
+#define SSID_NAME_LENGTH_MAX        (32)
+#define PASSWORD_LENGTH_MAX         (32)
+
+struct cmd_join
+{
+    char ssid[SSID_NAME_LENGTH_MAX];
+    char passwd[PASSWORD_LENGTH_MAX];
+
+    uint8_t bssid[8]; // 6byte + 2byte PAD.
+
+    uint32_t channel;
+    uint32_t security;
+};
+
+
+#endif // SPI_WIFI_H_INCLUDED

From 516711dc1d08ed332704ec53fd377edbdd0b9834 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Fri, 1 Aug 2014 12:03:11 +0800
Subject: [PATCH 79/86] [DFS] make comments cleanup.

---
 components/dfs/src/dfs_file.c  | 16 ++++++++++++----
 components/dfs/src/dfs_posix.c | 13 ++++++++-----
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/components/dfs/src/dfs_file.c b/components/dfs/src/dfs_file.c
index 32198371d7..f5619e2354 100644
--- a/components/dfs/src/dfs_file.c
+++ b/components/dfs/src/dfs_file.c
@@ -555,7 +555,7 @@ void ls(const char *pathname)
     if (pathname == RT_NULL) 
         rt_free(path);
 }
-FINSH_FUNCTION_EXPORT(ls, list directory contents)
+FINSH_FUNCTION_EXPORT(ls, list directory contents);
 
 void rm(const char *filename)
 {
@@ -564,7 +564,7 @@ void rm(const char *filename)
         rt_kprintf("Delete %s failed\n", filename);
     }
 }
-FINSH_FUNCTION_EXPORT(rm, remove files or directories)
+FINSH_FUNCTION_EXPORT(rm, remove files or directories);
 
 void cat(const char* filename)
 {
@@ -590,7 +590,7 @@ void cat(const char* filename)
 
     dfs_file_close(&fd);
 }
-FINSH_FUNCTION_EXPORT(cat, print file)
+FINSH_FUNCTION_EXPORT(cat, print file);
 
 #define BUF_SZ  4096
 static void copyfile(const char *src, const char *dst)
@@ -629,7 +629,15 @@ static void copyfile(const char *src, const char *dst)
         read_bytes = dfs_file_read(&src_fd, block_ptr, BUF_SZ);
         if (read_bytes > 0)
         {
-            dfs_file_write(&fd, block_ptr, read_bytes);
+			int length;
+			
+            length = dfs_file_write(&fd, block_ptr, read_bytes);
+			if (length != read_bytes)
+			{
+				/* write failed. */
+				rt_kprintf("Write file data failed, errno=%d\n", length);
+				break;
+			}
         }
     } while (read_bytes > 0);
 
diff --git a/components/dfs/src/dfs_posix.c b/components/dfs/src/dfs_posix.c
index 96139837e9..f516eccd93 100644
--- a/components/dfs/src/dfs_posix.c
+++ b/components/dfs/src/dfs_posix.c
@@ -33,11 +33,11 @@
 
 /**
  * this function is a POSIX compliant version, which will open a file and
- * return a file descriptor.
+ * return a file descriptor according specified flags.
  *
  * @param file the path name of file.
  * @param flags the file open flags.
- * @param mode
+ * @param mode ignored parameter
  *
  * @return the non-negative integer on successful open, others for failed.
  */
@@ -120,7 +120,8 @@ RTM_EXPORT(close);
  * @param buf the buffer to save the read data.
  * @param len the maximal length of data buffer
  *
- * @return the actual read data buffer length
+ * @return the actual read data buffer length. If the returned value is 0, it
+ * may be reach the end of file, please check errno.
  */
 int read(int fd, void *buf, size_t len)
 {
@@ -200,7 +201,7 @@ RTM_EXPORT(write);
  * @param offset the offset to be seeked.
  * @param whence the directory of seek.
  *
- * @return the current file position, or -1 on failed.
+ * @return the current read/write position in the file, or -1 on failed.
  */
 off_t lseek(int fd, off_t offset, int whence)
 {
@@ -336,6 +337,8 @@ RTM_EXPORT(stat);
  *
  * @param fildes the file description
  * @param buf the data buffer to save stat description.
+ *
+ * @return 0 on successful, -1 on failed.
  */
 int fstat(int fildes, struct stat *buf)
 {
@@ -470,7 +473,7 @@ RTM_EXPORT(rmdir);
  *
  * @param name the path name to be open.
  *
- * @return the DIR pointer of directory, NULL on open failed.
+ * @return the DIR pointer of directory, NULL on open directory failed.
  */
 DIR *opendir(const char *name)
 {

From 5397e18c56d533a1475968cbd9eae8fbc398260f Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sun, 3 Aug 2014 14:29:46 +0800
Subject: [PATCH 80/86] [DeviceDrivers] Fix compiling warning.

---
 components/drivers/i2c/i2c-bit-ops.c |  3 ---
 components/drivers/i2c/i2c_dev.c     | 11 ++-------
 components/drivers/spi/spi_dev.c     | 35 +++-------------------------
 3 files changed, 5 insertions(+), 44 deletions(-)

diff --git a/components/drivers/i2c/i2c-bit-ops.c b/components/drivers/i2c/i2c-bit-ops.c
index 0d82d55fd4..d4a26ea72a 100644
--- a/components/drivers/i2c/i2c-bit-ops.c
+++ b/components/drivers/i2c/i2c-bit-ops.c
@@ -451,9 +451,6 @@ static const struct rt_i2c_bus_device_ops i2c_bit_bus_ops =
 rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
                             const char               *bus_name)
 {
-    struct rt_i2c_bit_ops *bit_ops = bus->priv;
-    RT_ASSERT(bit_ops != RT_NULL);
-
     bus->ops = &i2c_bit_bus_ops;
 
     return rt_i2c_bus_device_register(bus, bus_name);
diff --git a/components/drivers/i2c/i2c_dev.c b/components/drivers/i2c/i2c_dev.c
index cce53d5c92..4b811c62ea 100644
--- a/components/drivers/i2c/i2c_dev.c
+++ b/components/drivers/i2c/i2c_dev.c
@@ -20,18 +20,11 @@
  * Change Logs:
  * Date           Author        Notes
  * 2012-04-25     weety         first version
+ * 2014-08-03     bernard       fix some compiling warning
  */
 
 #include <rtdevice.h>
 
-static rt_err_t i2c_bus_device_init(rt_device_t dev)
-{
-    struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
-    RT_ASSERT(bus != RT_NULL);
-
-    return RT_EOK;
-}
-
 static rt_size_t i2c_bus_device_read(rt_device_t dev,
                                      rt_off_t    pos,
                                      void       *buffer,
@@ -122,7 +115,7 @@ rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus,
     /* set device type */
     device->type    = RT_Device_Class_I2CBUS;
     /* initialize device interface */
-    device->init    = i2c_bus_device_init;
+    device->init    = RT_NULL;
     device->open    = RT_NULL;
     device->close   = RT_NULL;
     device->read    = i2c_bus_device_read;
diff --git a/components/drivers/spi/spi_dev.c b/components/drivers/spi/spi_dev.c
index b1f6e41a86..375a5e0fa1 100644
--- a/components/drivers/spi/spi_dev.c
+++ b/components/drivers/spi/spi_dev.c
@@ -25,16 +25,6 @@
 #include <drivers/spi.h>
 
 /* SPI bus device interface, compatible with RT-Thread 0.3.x/1.0.x */
-static rt_err_t _spi_bus_device_init(rt_device_t dev)
-{
-    struct rt_spi_bus *bus;
-
-    bus = (struct rt_spi_bus *)dev;
-    RT_ASSERT(bus != RT_NULL);
-
-    return RT_EOK;
-}
-
 static rt_size_t _spi_bus_device_read(rt_device_t dev,
                                       rt_off_t    pos,
                                       void       *buffer,
@@ -67,11 +57,7 @@ static rt_err_t _spi_bus_device_control(rt_device_t dev,
                                         rt_uint8_t  cmd,
                                         void       *args)
 {
-    struct rt_spi_bus *bus;
-
-    bus = (struct rt_spi_bus *)dev;
-    RT_ASSERT(bus != RT_NULL);
-
+    /* TODO: add control command handle */
     switch (cmd)
     {
     case 0: /* set device */
@@ -93,7 +79,7 @@ rt_err_t rt_spi_bus_device_init(struct rt_spi_bus *bus, const char *name)
     /* set device type */
     device->type    = RT_Device_Class_SPIBUS;
     /* initialize device interface */
-    device->init    = _spi_bus_device_init;
+    device->init    = RT_NULL;
     device->open    = RT_NULL;
     device->close   = RT_NULL;
     device->read    = _spi_bus_device_read;
@@ -105,16 +91,6 @@ rt_err_t rt_spi_bus_device_init(struct rt_spi_bus *bus, const char *name)
 }
 
 /* SPI Dev device interface, compatible with RT-Thread 0.3.x/1.0.x */
-static rt_err_t _spidev_device_init(rt_device_t dev)
-{
-    struct rt_spi_device *device;
-
-    device = (struct rt_spi_device *)dev;
-    RT_ASSERT(device != RT_NULL);
-
-    return RT_EOK;
-}
-
 static rt_size_t _spidev_device_read(rt_device_t dev,
                                      rt_off_t    pos,
                                      void       *buffer,
@@ -147,11 +123,6 @@ static rt_err_t _spidev_device_control(rt_device_t dev,
                                        rt_uint8_t  cmd,
                                        void       *args)
 {
-    struct rt_spi_device *device;
-
-    device = (struct rt_spi_device *)dev;
-    RT_ASSERT(device != RT_NULL);
-
     switch (cmd)
     {
     case 0: /* set device */
@@ -172,7 +143,7 @@ rt_err_t rt_spidev_device_init(struct rt_spi_device *dev, const char *name)
 
     /* set device type */
     device->type    = RT_Device_Class_SPIDevice;
-    device->init    = _spidev_device_init;
+    device->init    = RT_NULL;
     device->open    = RT_NULL;
     device->close   = RT_NULL;
     device->read    = _spidev_device_read;

From fccd0e6b8314ecc95bde542fe7031bc881dac722 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sun, 3 Aug 2014 14:30:31 +0800
Subject: [PATCH 81/86] [libc] Use __SIZE_TYPE__ instead of rt_size_t in
 minilibc.

---
 components/libc/minilibc/sys/types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/libc/minilibc/sys/types.h b/components/libc/minilibc/sys/types.h
index 6d92d80826..a6860f2aee 100644
--- a/components/libc/minilibc/sys/types.h
+++ b/components/libc/minilibc/sys/types.h
@@ -4,7 +4,7 @@
 #include <rtthread.h>
 
 typedef long    	off_t;
-typedef rt_size_t 	size_t;
+typedef __SIZE_TYPE__ 	size_t;
 typedef signed long ssize_t;		/* Used for a count of bytes or an error indication. */
 
 typedef rt_uint8_t 	u_char;

From 4ee93b75524e7194e5a9dc3468409e08e69e0663 Mon Sep 17 00:00:00 2001
From: bernard <bernard.xiong@gmail.com>
Date: Sun, 3 Aug 2014 14:31:19 +0800
Subject: [PATCH 82/86] [libc] Fix system issue when use msh and make code
 cleanup.

---
 components/libc/armlibc/mem_std.c | 22 ++++++++++++++++++----
 components/libc/armlibc/stubs.c   | 22 +++++++++++-----------
 2 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/components/libc/armlibc/mem_std.c b/components/libc/armlibc/mem_std.c
index 017ed77fef..6faf86555f 100644
--- a/components/libc/armlibc/mem_std.c
+++ b/components/libc/armlibc/mem_std.c
@@ -1,7 +1,16 @@
 /*
- * File:    mem_std.c
- * Brief:   Replace memory management functions of arm standard c library
+ * File     : mem_std.c
+ * Brief    : implement standard memory routins.
  *
+ * This file is part of Device File System in RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE.
+ *
+ * Change Logs:
+ * 2014-08-03     bernard      Add file header.
  */
 
 #include "rtthread.h"
@@ -9,16 +18,21 @@
 /* avoid the heap and heap-using library functions supplied by arm */
 #pragma import(__use_no_heap)
 
-void * malloc(int n)
+void *malloc(int n)
 {
     return rt_malloc(n);
 }
 
-void * realloc(void *rmem, rt_size_t newsize)
+void *realloc(void *rmem, rt_size_t newsize)
 {
     return rt_realloc(rmem, newsize);
 }
 
+void *calloc(rt_size_t nelem, rt_size_t elsize)
+{
+	return rt_calloc(nelem, elsize);
+}
+
 void free(void *rmem)
 {
     rt_free(rmem);
diff --git a/components/libc/armlibc/stubs.c b/components/libc/armlibc/stubs.c
index d219b3430a..1f9e01ba3c 100644
--- a/components/libc/armlibc/stubs.c
+++ b/components/libc/armlibc/stubs.c
@@ -13,6 +13,8 @@
  * Date           Author       Notes
  * 2012-11-23     Yihui        The first version
  * 2013-11-24     aozima       fixed _sys_read()/_sys_write() issues.
+ * 2014-08-03     bernard      If using msh, use system() implementation 
+ *                             in msh.
  */
 
 #include <string.h>
@@ -194,9 +196,13 @@ char *_sys_command_string(char *cmd, int len)
     return cmd;
 }
 
+/* This function writes a character to the console. */
 void _ttywrch(int ch)
 {
-   /* TODO */
+    char c;
+
+    c = (char)ch;
+    rt_kprintf(&c);
 }
 
 void _sys_exit(int return_code)
@@ -231,18 +237,12 @@ int remove(const char *filename)
 #endif
 }
 
-/* rename() is defined in dfs_posix.c instead */
-#if 0
-int rename(const char *old, const char *new)
-{
-    return -1;
-}
-#endif
-
+#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) && defined(RT_USING_MODULE) && defined(RT_USING_DFS)
+/* use system implementation in the msh */
+#else
 int system(const char *string)
 {
     RT_ASSERT(0);
     for(;;);
 }
-
-
+#endif

From 0ad17f462d06c5c43ea84f8c71c2b84e44095b18 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Mon, 4 Aug 2014 16:40:40 +0800
Subject: [PATCH 83/86] [DeviceDrivers] Add modification under Linux

---
 components/drivers/src/workqueue.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/drivers/src/workqueue.c b/components/drivers/src/workqueue.c
index 52f6002595..d9062e6cdb 100644
--- a/components/drivers/src/workqueue.c
+++ b/components/drivers/src/workqueue.c
@@ -33,7 +33,7 @@ static void _workqueue_thread_entry(void* parameter)
 struct rt_workqueue *rt_workqueue_create(const char* name, rt_uint16_t stack_size, rt_uint8_t priority)
 {
 	struct rt_workqueue *queue = RT_NULL;
-
+
 	queue = (struct rt_workqueue*)RT_KERNEL_MALLOC(sizeof(struct rt_workqueue));
 	if (queue != RT_NULL)
 	{

From 0cf9018e49f7d61635c9782a2ad006ba9860df05 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Tue, 5 Aug 2014 11:51:32 +0800
Subject: [PATCH 84/86] Update keil.py

clear old groups in template.uvproj.
---
 tools/keil.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/keil.py b/tools/keil.py
index ef0dece3f8..912c358488 100644
--- a/tools/keil.py
+++ b/tools/keil.py
@@ -107,6 +107,7 @@ def MDK4Project(target, script):
     groups = tree.find('Targets/Target/Groups')
     if groups is None:
         groups = SubElement(tree.find('Targets/Target'), 'Groups')
+    groups.clear() # clean old groups
     for group in script:
         group_xml = MDK4AddGroup(ProjectFiles, groups, group['name'], group['src'], project_path)
         

From b833a5ca80de2aef127bf33ed3a9efe635e69ff9 Mon Sep 17 00:00:00 2001
From: hduffddybz <ffddybz123@126.com>
Date: Wed, 6 Aug 2014 00:19:13 -0800
Subject: [PATCH 85/86] correct spelling error

---
 components/net/lwip-1.4.1/src/netif/ethernetif.c | 4 ++++
 examples/network/tcpclient.c                     | 2 +-
 examples/network/tcpserver.c                     | 2 +-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/components/net/lwip-1.4.1/src/netif/ethernetif.c b/components/net/lwip-1.4.1/src/netif/ethernetif.c
index ab7743290a..c47bb8e191 100644
--- a/components/net/lwip-1.4.1/src/netif/ethernetif.c
+++ b/components/net/lwip-1.4.1/src/netif/ethernetif.c
@@ -428,6 +428,10 @@ INIT_DEVICE_EXPORT(eth_system_device_init);
 #include <finsh.h>
 void set_if(char* netif_name, char* ip_addr, char* gw_addr, char* nm_addr)
 {
+#if	LWIP_DHCP
+	return ;
+#endif
+
     struct ip_addr *ip;
     struct ip_addr addr;
     struct netif * netif = netif_list;
diff --git a/examples/network/tcpclient.c b/examples/network/tcpclient.c
index 088206fdb1..7a0d4b5365 100644
--- a/examples/network/tcpclient.c
+++ b/examples/network/tcpclient.c
@@ -81,7 +81,7 @@ void tcpclient(const char* url, int port)
         else
         {
             /* 在控制终端显示收到的数� */
-            rt_kprintf("\nRecieved data = %s " , recv_data);
+            rt_kprintf("\nReceived data = %s " , recv_data);
         }
 
         /* ��数�到sock连接 */
diff --git a/examples/network/tcpserver.c b/examples/network/tcpserver.c
index 54b8c9301d..3f34bc2c29 100644
--- a/examples/network/tcpserver.c
+++ b/examples/network/tcpserver.c
@@ -101,7 +101,7 @@ void tcpserv(void* parameter)
            else
            {
                /* 在控制终端显示收到的数� */
-               rt_kprintf("RECIEVED DATA = %s \n" , recv_data);
+               rt_kprintf("RECEIVED DATA = %s \n" , recv_data);
            }
        }
    }

From f14d93b1b5dc26c7afd7c54d9d7867b95821dfee Mon Sep 17 00:00:00 2001
From: hduffddybz <ffddybz123@126.com>
Date: Wed, 6 Aug 2014 00:28:44 -0800
Subject: [PATCH 86/86] correct spelling error

---
 components/net/lwip-1.4.1/src/netif/ethernetif.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/components/net/lwip-1.4.1/src/netif/ethernetif.c b/components/net/lwip-1.4.1/src/netif/ethernetif.c
index c47bb8e191..ab7743290a 100644
--- a/components/net/lwip-1.4.1/src/netif/ethernetif.c
+++ b/components/net/lwip-1.4.1/src/netif/ethernetif.c
@@ -428,10 +428,6 @@ INIT_DEVICE_EXPORT(eth_system_device_init);
 #include <finsh.h>
 void set_if(char* netif_name, char* ip_addr, char* gw_addr, char* nm_addr)
 {
-#if	LWIP_DHCP
-	return ;
-#endif
-
     struct ip_addr *ip;
     struct ip_addr addr;
     struct netif * netif = netif_list;